diff --git a/hw_handoff/Arty_Z7_20_wrapper.hdf b/hw_handoff/Arty_Z7_20_wrapper.hdf index 689619c..b42d18a 100644 Binary files a/hw_handoff/Arty_Z7_20_wrapper.hdf and b/hw_handoff/Arty_Z7_20_wrapper.hdf differ diff --git a/sdk/Arty_Z7_20_wrapper_hw_platform_0/system.hdf b/sdk/Arty_Z7_20_wrapper_hw_platform_0/system.hdf index 689619c..b42d18a 100644 Binary files a/sdk/Arty_Z7_20_wrapper_hw_platform_0/system.hdf and b/sdk/Arty_Z7_20_wrapper_hw_platform_0/system.hdf differ diff --git a/sdk/displaydemo_bsp/system.mss b/sdk/displaydemo_bsp/system.mss index fa09d91..ecf8503 100644 --- a/sdk/displaydemo_bsp/system.mss +++ b/sdk/displaydemo_bsp/system.mss @@ -288,4 +288,16 @@ BEGIN DRIVER PARAMETER HW_INSTANCE = xadc_wiz_0 END +BEGIN DRIVER + PARAMETER DRIVER_NAME = gpio + PARAMETER DRIVER_VER = 4.3 + PARAMETER HW_INSTANCE = axi_gpio_video +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = vtc + PARAMETER DRIVER_VER = 7.2 + PARAMETER HW_INSTANCE = v_tc_1 +END + diff --git a/sdk/fsbl_bsp/system.mss b/sdk/fsbl_bsp/system.mss index 3aafdca..6f2ba78 100644 --- a/sdk/fsbl_bsp/system.mss +++ b/sdk/fsbl_bsp/system.mss @@ -288,6 +288,18 @@ BEGIN DRIVER PARAMETER HW_INSTANCE = xadc_wiz_0 END +BEGIN DRIVER + PARAMETER DRIVER_NAME = gpio + PARAMETER DRIVER_VER = 4.3 + PARAMETER HW_INSTANCE = axi_gpio_video +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = vtc + PARAMETER DRIVER_VER = 7.2 + PARAMETER HW_INSTANCE = v_tc_1 +END + BEGIN LIBRARY PARAMETER LIBRARY_NAME = xilffs diff --git a/src/bd/Arty_Z7_20/Arty_Z7_20.bd b/src/bd/Arty_Z7_20/Arty_Z7_20.bd index b4b8f7b..edb04c7 100644 --- a/src/bd/Arty_Z7_20/Arty_Z7_20.bd +++ b/src/bd/Arty_Z7_20/Arty_Z7_20.bd @@ -1,5 +1,5 @@  - + xilinx.com @@ -252,6 +252,24 @@ + + TMDS_In + + + + + + DDC_In + + + + + + hdmi_in_hpd + + + + CLK.SYS_CLOCK Clk @@ -357,7 +375,7 @@ Arty_Z7_20_axi_gpio_shield_1_0 0 - 1 + 0 shield_dp0_dp13 @@ -366,7 +384,7 @@ Arty_Z7_20_axi_gpio_shield_2_0 - 1 + 0 true shield_dp26_dp41 @@ -387,6 +405,7 @@ Arty_Z7_20_axi_mem_intercon_0 + 2 1 4 2 @@ -398,11 +417,16 @@ Arty_Z7_20_axi_vdma_0_0 - 1 + 32 + 64 + 3 0 - 4096 - 16 - 0 + 2 + 2048 + 2048 + 32 + 32 + 1 @@ -510,7 +534,7 @@ 108.333336 200 100 - 142 + 120 75 50 650.000000 @@ -534,7 +558,7 @@ 200.000000 200.000000 100.000000 - 142.857132 + 118.181816 76.923080 50.000000 108.333336 @@ -544,7 +568,7 @@ 108.333336 108.333336 100000000 - 142857132 + 118181816 76923080 50000000 0 @@ -758,7 +782,7 @@ IO PLL IO PLL IO PLL - IO PLL + ARM PLL IO PLL IO PLL IO PLL @@ -992,7 +1016,7 @@ Arty_Z7_20_processing_system7_0_axi_periph_0 - 9 + 11 xilinx.com:ip:axi_interconnect:2.1 @@ -1084,7 +1108,7 @@ Arty_Z7_20_xlconcat_0_0 - 7 + 8 @@ -1120,13 +1144,29 @@ Arty_Z7_20_clk_wiz_0_0 + PLL + true + 2 125 - false + 200 + BUFG + BUFG + BUFG + BUFG + BUFG + BUFG + BUFG + true 1 - 8.000 + 8 + ZHOLD + 8 + 5 true sys_clock 119.348 + 109.241 + 96.948 @@ -1136,6 +1176,80 @@ Arty_Z7_20_proc_sys_reset_0_2 + + dvi2rgb_0 + + + Arty_Z7_20_dvi2rgb_0_0 + false + true + + + + v_vid_in_axi4s_0 + + + Arty_Z7_20_v_vid_in_axi4s_0_0 + 1 + 12 + + + + proc_sys_reset_0 + + + Arty_Z7_20_proc_sys_reset_0_3 + 0 + + + + v_tc_1 + + + Arty_Z7_20_v_tc_1_0 + true + 2048 + false + false + false + + + + axi_gpio_video + + + Arty_Z7_20_axi_gpio_0_0 + 1 + 1 + 1 + 1 + 1 + 1 + + + + axis_subset_converter_1 + + + Arty_Z7_20_axis_subset_converter_0_1 + 3 + 1 + 1 + 1 + tdata[7:0] + tuser[0:0] + 1'b0 + + + + v_rgb2ycrcb_0 + + + Arty_Z7_20_v_rgb2ycrcb_0_0 + 1280 + 720 + + @@ -1218,6 +1332,46 @@ + + dvi2rgb_0_RGB + + + + + processing_system7_0_axi_periph_M09_AXI + + + + + v_vid_in_axi4s_0_vtiming_out + + + + + axi_vdma_0_M_AXI_S2MM + + + + + processing_system7_0_axi_periph_M10_AXI + + + + + axis_subset_converter_1_M_AXIS + + + + + v_vid_in_axi4s_0_video_out + + + + + v_rgb2ycrcb_0_video_out + + + @@ -1247,16 +1401,6 @@ - - axi_gpio_shield_1_ip2intc_irpt - - - - - axi_gpio_shield_2_ip2intc_irpt - - - axi_vdma_0_mm2s_introut @@ -1277,6 +1421,8 @@ + + @@ -1288,6 +1434,8 @@ + + processing_system7_0_FCLK_CLK1 @@ -1298,9 +1446,15 @@ + + + + + + processing_system7_0_FCLK_RESET0_N @@ -1310,6 +1464,7 @@ + processing_system7_0_SPI0_SS1_O @@ -1338,6 +1493,9 @@ + + + @@ -1348,6 +1506,8 @@ + + rst_processing_system7_0_142M_interconnect_aresetn @@ -1359,6 +1519,7 @@ + v_axi4s_vid_out_0_vtg_ce @@ -1384,6 +1545,7 @@ xlconstant_0_dout + processing_system7_0_FCLK_CLK2 @@ -1410,6 +1572,49 @@ + + clk_wiz_0_clk_out2 + + + + + dvi2rgb_0_PixelClk + + + + + + + dvi2rgb_0_aPixelClkLckd + + + + + + proc_sys_reset_0_peripheral_reset + + + + + proc_sys_reset_0_peripheral_aresetn + + + + + axi_vdma_0_s2mm_introut + + + + + v_tc_1_irq + + + + + axi_gpio_video_ip2intc_irpt + + + @@ -1481,6 +1686,15 @@ + + + + + + + + + @@ -1550,6 +1764,18 @@ + + M09_AXI + + + + + + M10_AXI + + + + CLK.ACLK Clk @@ -2146,6 +2372,118 @@ + + CLK.M09_ACLK + Clk + Clock + + + + + + + CLK + + + M09_ACLK + + + + + + ASSOCIATED_BUSIF + M09_AXI + + + + + + + + ASSOCIATED_RESET + M09_ARESETN + + + + + + + + + + RST.M09_ARESETN + Reset + Reset + + + + + + + RST + + + M09_ARESETN + + + + + + CLK.M10_ACLK + Clk + Clock + + + + + + + CLK + + + M10_ACLK + + + + + + ASSOCIATED_BUSIF + M10_AXI + + + + + + + + ASSOCIATED_RESET + M10_ARESETN + + + + + + + + + + RST.M10_ARESETN + Reset + Reset + + + + + + + RST + + + M10_ARESETN + + + + @@ -2288,6 +2626,30 @@ in + + M09_ACLK + + in + + + + M09_ARESETN + + in + + + + M10_ACLK + + in + + + + M10_ARESETN + + in + + @@ -2304,7 +2666,7 @@ Arty_Z7_20_xbar_0 1 - 9 + 11 0 @@ -2348,6 +2710,14 @@ m08_couplers + + m09_couplers + + + + m10_couplers + + @@ -2400,6 +2770,16 @@ + + xbar_to_m09_couplers + + + + + xbar_to_m10_couplers + + + @@ -2416,6 +2796,8 @@ + + processing_system7_0_axi_periph_ARESETN_net @@ -2431,6 +2813,8 @@ + + S00_ACLK_1 @@ -2532,6 +2916,26 @@ + + M09_ACLK_1 + + + + + M09_ARESETN_1 + + + + + M10_ACLK_1 + + + + + M10_ARESETN_1 + + + @@ -2564,13 +2968,19 @@ + + + + + + xilinx.com BlockDiagram/Arty_Z7_20_imp/processing_system7_0_axi_periph_imp - m08_couplers + m10_couplers 1.00.a @@ -2703,7 +3113,7 @@ BlockDiagram :vivado.xilinx.com: - + @@ -2738,13 +3148,13 @@ xilinx.com BlockDiagram/Arty_Z7_20_imp/processing_system7_0_axi_periph_imp - m08_couplers_imp + m10_couplers_imp 1.00.a - - + + @@ -2752,7 +3162,7 @@ xilinx.com BlockDiagram/Arty_Z7_20_imp/processing_system7_0_axi_periph_imp - m07_couplers + m09_couplers 1.00.a @@ -2885,7 +3295,7 @@ BlockDiagram :vivado.xilinx.com: - + @@ -2920,13 +3330,13 @@ xilinx.com BlockDiagram/Arty_Z7_20_imp/processing_system7_0_axi_periph_imp - m07_couplers_imp + m09_couplers_imp 1.00.a - - + + @@ -2934,7 +3344,7 @@ xilinx.com BlockDiagram/Arty_Z7_20_imp/processing_system7_0_axi_periph_imp - m06_couplers + m08_couplers 1.00.a @@ -3067,7 +3477,7 @@ BlockDiagram :vivado.xilinx.com: - + @@ -3102,13 +3512,13 @@ xilinx.com BlockDiagram/Arty_Z7_20_imp/processing_system7_0_axi_periph_imp - m06_couplers_imp + m08_couplers_imp 1.00.a - - + + @@ -3116,7 +3526,7 @@ xilinx.com BlockDiagram/Arty_Z7_20_imp/processing_system7_0_axi_periph_imp - m05_couplers + m07_couplers 1.00.a @@ -3249,7 +3659,7 @@ BlockDiagram :vivado.xilinx.com: - + @@ -3284,13 +3694,13 @@ xilinx.com BlockDiagram/Arty_Z7_20_imp/processing_system7_0_axi_periph_imp - m05_couplers_imp + m07_couplers_imp 1.00.a - - + + @@ -3298,7 +3708,7 @@ xilinx.com BlockDiagram/Arty_Z7_20_imp/processing_system7_0_axi_periph_imp - m04_couplers + m06_couplers 1.00.a @@ -3431,7 +3841,7 @@ BlockDiagram :vivado.xilinx.com: - + @@ -3466,13 +3876,13 @@ xilinx.com BlockDiagram/Arty_Z7_20_imp/processing_system7_0_axi_periph_imp - m04_couplers_imp + m06_couplers_imp 1.00.a - - + + @@ -3480,7 +3890,7 @@ xilinx.com BlockDiagram/Arty_Z7_20_imp/processing_system7_0_axi_periph_imp - m03_couplers + m05_couplers 1.00.a @@ -3613,7 +4023,7 @@ BlockDiagram :vivado.xilinx.com: - + @@ -3648,13 +4058,13 @@ xilinx.com BlockDiagram/Arty_Z7_20_imp/processing_system7_0_axi_periph_imp - m03_couplers_imp + m05_couplers_imp 1.00.a - - + + @@ -3662,7 +4072,7 @@ xilinx.com BlockDiagram/Arty_Z7_20_imp/processing_system7_0_axi_periph_imp - m02_couplers + m04_couplers 1.00.a @@ -3795,7 +4205,7 @@ BlockDiagram :vivado.xilinx.com: - + @@ -3830,13 +4240,13 @@ xilinx.com BlockDiagram/Arty_Z7_20_imp/processing_system7_0_axi_periph_imp - m02_couplers_imp + m04_couplers_imp 1.00.a - - + + @@ -3844,7 +4254,7 @@ xilinx.com BlockDiagram/Arty_Z7_20_imp/processing_system7_0_axi_periph_imp - m01_couplers + m03_couplers 1.00.a @@ -3977,7 +4387,7 @@ BlockDiagram :vivado.xilinx.com: - + @@ -4012,13 +4422,13 @@ xilinx.com BlockDiagram/Arty_Z7_20_imp/processing_system7_0_axi_periph_imp - m01_couplers_imp + m03_couplers_imp 1.00.a - - + + @@ -4026,7 +4436,7 @@ xilinx.com BlockDiagram/Arty_Z7_20_imp/processing_system7_0_axi_periph_imp - m00_couplers + m02_couplers 1.00.a @@ -4159,7 +4569,7 @@ BlockDiagram :vivado.xilinx.com: - + @@ -4194,13 +4604,13 @@ xilinx.com BlockDiagram/Arty_Z7_20_imp/processing_system7_0_axi_periph_imp - m00_couplers_imp + m02_couplers_imp 1.00.a - - + + @@ -4208,7 +4618,7 @@ xilinx.com BlockDiagram/Arty_Z7_20_imp/processing_system7_0_axi_periph_imp - s00_couplers + m01_couplers 1.00.a @@ -4341,7 +4751,7 @@ BlockDiagram :vivado.xilinx.com: - + @@ -4376,98 +4786,37 @@ xilinx.com BlockDiagram/Arty_Z7_20_imp/processing_system7_0_axi_periph_imp - s00_couplers_imp + m01_couplers_imp 1.00.a - - - auto_pc - - - Arty_Z7_20_auto_pc_1 - AXI3 - AXI4LITE - - - - - - S_ACLK_1 - - - - - S_ARESETN_1 - - - - + - - - - - + + xilinx.com - BlockDiagram/Arty_Z7_20_imp - axi_mem_intercon + BlockDiagram/Arty_Z7_20_imp/processing_system7_0_axi_periph_imp + m00_couplers 1.00.a - S00_AXI - - - - - - M00_AXI + M_AXI - CLK.ACLK - Clk - Clock - - - - - - - CLK - - - ACLK - - - - - - RST.ARESETN - Reset - Reset - - + S_AXI - - - - RST - - - ARESETN - - - + + - CLK.S00_ACLK + CLK.M_ACLK Clk Clock @@ -4479,14 +4828,14 @@ CLK - S00_ACLK + M_ACLK ASSOCIATED_BUSIF - S00_AXI + M_AXI @@ -4495,7 +4844,7 @@ ASSOCIATED_RESET - S00_ARESETN + M_ARESETN @@ -4505,7 +4854,7 @@ - RST.S00_ARESETN + RST.M_ARESETN Reset Reset @@ -4517,13 +4866,13 @@ RST - S00_ARESETN + M_ARESETN - CLK.M00_ACLK + CLK.S_ACLK Clk Clock @@ -4535,14 +4884,14 @@ CLK - M00_ACLK + S_ACLK ASSOCIATED_BUSIF - M00_AXI + S_AXI @@ -4551,7 +4900,7 @@ ASSOCIATED_RESET - M00_ARESETN + S_ARESETN @@ -4561,7 +4910,7 @@ - RST.M00_ARESETN + RST.S_ARESETN Reset Reset @@ -4573,7 +4922,7 @@ RST - M00_ARESETN + S_ARESETN @@ -4584,42 +4933,30 @@ BlockDiagram :vivado.xilinx.com: - + - ACLK - - in - - - - ARESETN - - in - - - - S00_ACLK + M_ACLK in - S00_ARESETN + M_ARESETN in - M00_ACLK + S_ACLK in - M00_ARESETN + S_ARESETN in @@ -4630,51 +4967,21 @@ xilinx.com - BlockDiagram/Arty_Z7_20_imp - axi_mem_intercon_imp + BlockDiagram/Arty_Z7_20_imp/processing_system7_0_axi_periph_imp + m00_couplers_imp 1.00.a - - - s00_couplers - - - - - - axi_mem_intercon_ACLK_net - - - - - axi_mem_intercon_ARESETN_net - - - - - S00_ACLK_1 - - - - - S00_ARESETN_1 - - - - + - - - - - + + xilinx.com - BlockDiagram/Arty_Z7_20_imp/axi_mem_intercon_imp + BlockDiagram/Arty_Z7_20_imp/processing_system7_0_axi_periph_imp s00_couplers 1.00.a @@ -4808,7 +5115,7 @@ BlockDiagram :vivado.xilinx.com: - + @@ -4842,44 +5149,1023 @@ xilinx.com - BlockDiagram/Arty_Z7_20_imp/axi_mem_intercon_imp + BlockDiagram/Arty_Z7_20_imp/processing_system7_0_axi_periph_imp s00_couplers_imp 1.00.a - s00_regslice - + auto_pc + - Arty_Z7_20_s00_regslice_0 + Arty_Z7_20_auto_pc_1 + AXI3 + AXI4LITE + + + + + S_ACLK_1 + + + + + S_ARESETN_1 + + + + + + + + + + + + + + + + xilinx.com + BlockDiagram/Arty_Z7_20_imp + axi_mem_intercon + 1.00.a + + + S00_AXI + + + + + + M00_AXI + + + + + + S01_AXI + + + + + + CLK.ACLK + Clk + Clock + + + + + + + CLK + + + ACLK + + + + + + RST.ARESETN + Reset + Reset + + + + + + + RST + + + ARESETN + + + + + + CLK.S00_ACLK + Clk + Clock + + + + + + + CLK + + + S00_ACLK + + + + + + ASSOCIATED_BUSIF + S00_AXI + + + + + + + + ASSOCIATED_RESET + S00_ARESETN + + + + + + + + + + RST.S00_ARESETN + Reset + Reset + + + + + + + RST + + + S00_ARESETN + + + + + + CLK.M00_ACLK + Clk + Clock + + + + + + + CLK + + + M00_ACLK + + + + + + ASSOCIATED_BUSIF + M00_AXI + + + + + + + + ASSOCIATED_RESET + M00_ARESETN + + + + + + + + + + RST.M00_ARESETN + Reset + Reset + + + + + + + RST + + + M00_ARESETN + + + + + + CLK.S01_ACLK + Clk + Clock + + + + + + + CLK + + + S01_ACLK + + + + + + ASSOCIATED_BUSIF + S01_AXI + + + + + + + + ASSOCIATED_RESET + S01_ARESETN + + + + + + + + + + RST.S01_ARESETN + Reset + Reset + + + + + + + RST + + + S01_ARESETN + + + + + + + + + BlockDiagram + :vivado.xilinx.com: + + + + + + ACLK + + in + + + + ARESETN + + in + + + + S00_ACLK + + in + + + + S00_ARESETN + + in + + + + M00_ACLK + + in + + + + M00_ARESETN + + in + + + + S01_ACLK + + in + + + + S01_ARESETN + + in + + + + + + + + xilinx.com + BlockDiagram/Arty_Z7_20_imp + axi_mem_intercon_imp + 1.00.a + + + xbar + + + Arty_Z7_20_xbar_1 + 2 + 1 + 0 + + + + s00_couplers + + + + s01_couplers + + + + m00_couplers + + + + + + s00_couplers_to_xbar + + + + + s01_couplers_to_xbar + + + + + xbar_to_m00_couplers + + + + + + + axi_mem_intercon_ACLK_net + + + + + + + + axi_mem_intercon_ARESETN_net + + + + + + + + S00_ACLK_1 + + + + + S00_ARESETN_1 + + + + + S01_ACLK_1 + + + + + S01_ARESETN_1 + + + + + M00_ACLK_1 + + + + + M00_ARESETN_1 + + + + + + + + + + + + + + + + + + + xilinx.com + BlockDiagram/Arty_Z7_20_imp/axi_mem_intercon_imp + m00_couplers + 1.00.a + + + M_AXI + + + + + + S_AXI + + + + + + CLK.M_ACLK + Clk + Clock + + + + + + + CLK + + + M_ACLK + + + + + + ASSOCIATED_BUSIF + M_AXI + + + + + + + + ASSOCIATED_RESET + M_ARESETN + + + + + + + + + + RST.M_ARESETN + Reset + Reset + + + + + + + RST + + + M_ARESETN + + + + + + CLK.S_ACLK + Clk + Clock + + + + + + + CLK + + + S_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI + + + + + + + + ASSOCIATED_RESET + S_ARESETN + + + + + + + + + + RST.S_ARESETN + Reset + Reset + + + + + + + RST + + + S_ARESETN + + + + + + + + + BlockDiagram + :vivado.xilinx.com: + + + + + + M_ACLK + + in + + + + M_ARESETN + + in + + + + S_ACLK + + in + + + + S_ARESETN + + in + + + + + + + + xilinx.com + BlockDiagram/Arty_Z7_20_imp/axi_mem_intercon_imp + m00_couplers_imp + 1.00.a + + + auto_pc + + + Arty_Z7_20_auto_pc_0 + AXI4 + AXI3 + + + + + + + S_ACLK_1 + + + + + S_ARESETN_1 + + + + + + + + + + + + + + + + xilinx.com + BlockDiagram/Arty_Z7_20_imp/axi_mem_intercon_imp + s01_couplers + 1.00.a + + + M_AXI + + + + + + S_AXI + + + + + + CLK.M_ACLK + Clk + Clock + + + + + + + CLK + + + M_ACLK + + + + + + ASSOCIATED_BUSIF + M_AXI + + + + + + + + ASSOCIATED_RESET + M_ARESETN + + + + + + + + + + RST.M_ARESETN + Reset + Reset + + + + + + + RST + + + M_ARESETN + + + + + + CLK.S_ACLK + Clk + Clock + + + + + + + CLK + + + S_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI + + + + + + + + ASSOCIATED_RESET + S_ARESETN + + + + + + + + + + RST.S_ARESETN + Reset + Reset + + + + + + + RST + + + S_ARESETN + + + + + + + + + BlockDiagram + :vivado.xilinx.com: + + + + + + M_ACLK + + in + + + + M_ARESETN + + in + + + + S_ACLK + + in + + + + S_ARESETN + + in + + + + + + + + xilinx.com + BlockDiagram/Arty_Z7_20_imp/axi_mem_intercon_imp + s01_couplers_imp + 1.00.a + + + + + + + + + + + xilinx.com + BlockDiagram/Arty_Z7_20_imp/axi_mem_intercon_imp + s00_couplers + 1.00.a + + + M_AXI + + + + + + S_AXI + + + + + + CLK.M_ACLK + Clk + Clock + + + + + + + CLK + + + M_ACLK + + + + + + ASSOCIATED_BUSIF + M_AXI + + + + + + + + ASSOCIATED_RESET + M_ARESETN + + + + + + + + + + RST.M_ARESETN + Reset + Reset + + + + + + + RST + + + M_ARESETN + + + + + + CLK.S_ACLK + Clk + Clock + + + + + + + CLK + + + S_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI + + + + + + + + ASSOCIATED_RESET + S_ARESETN + + + + + + + + + + RST.S_ARESETN + Reset + Reset + + + + + + + RST + + + S_ARESETN + + + + + + + + + BlockDiagram + :vivado.xilinx.com: + + + + + + M_ACLK + + in + + + + M_ARESETN + + in + + + + S_ACLK + + in + + + + S_ARESETN + + in + + + + + + + + xilinx.com + BlockDiagram/Arty_Z7_20_imp/axi_mem_intercon_imp + s00_couplers_imp + 1.00.a + - s00_data_fifo - + s00_regslice + - Arty_Z7_20_s00_data_fifo_0 + Arty_Z7_20_s00_regslice_0 - auto_pc - + s00_data_fifo + - Arty_Z7_20_auto_pc_0 - AXI4 - AXI3 + Arty_Z7_20_s00_data_fifo_0 - s00_regslice_to_auto_pc + s00_regslice_to_s00_data_fifo - - - - auto_pc_to_s00_data_fifo - @@ -4887,13 +6173,11 @@ S_ACLK_1 - S_ARESETN_1 - M_ACLK_1 @@ -4935,6 +6219,19 @@ + + Data_S2MM + 4G + 32 + + + SEG_processing_system7_0_HP0_DDR_LOWOCM + /processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM + 0x00000000 + 512M + + + @@ -4961,6 +6258,12 @@ 0x41200000 64K + + SEG_axi_gpio_0_Reg1 + /axi_gpio_video/S_AXI/Reg + 0x41250000 + 64K + SEG_axi_gpio_1_Reg /axi_gpio_shield_1/S_AXI/Reg @@ -4997,6 +6300,12 @@ 0x43C00000 64K + + SEG_v_tc_1_Reg + /v_tc_1/ctrl/Reg + 0x43C30000 + 64K + SEG_xadc_wiz_0_Reg /xadc_wiz_0/s_axi_lite/Reg diff --git a/src/bd/Arty_Z7_20/Arty_Z7_20.bxml b/src/bd/Arty_Z7_20/Arty_Z7_20.bxml index d648dda..f81e445 100644 --- a/src/bd/Arty_Z7_20/Arty_Z7_20.bxml +++ b/src/bd/Arty_Z7_20/Arty_Z7_20.bxml @@ -2,9 +2,9 @@ Composite Fileset - - - + + + @@ -212,6 +212,70 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -229,7 +293,7 @@ - + diff --git a/src/bd/Arty_Z7_20/Arty_Z7_20_ooc.xdc b/src/bd/Arty_Z7_20/Arty_Z7_20_ooc.xdc index 2772c85..7c146be 100644 --- a/src/bd/Arty_Z7_20/Arty_Z7_20_ooc.xdc +++ b/src/bd/Arty_Z7_20/Arty_Z7_20_ooc.xdc @@ -7,8 +7,10 @@ # of Vivado) ################################################################################ create_clock -name sys_clock -period 8 [get_ports sys_clock] +create_clock -name TMDS_In_clk_p -period 10 [get_ports TMDS_In_clk_p] +create_clock -name TMDS_In_clk_n -period 10 [get_ports TMDS_In_clk_n] create_clock -name processing_system7_0_FCLK_CLK0 -period 10 [get_pins processing_system7_0/FCLK_CLK0] -create_clock -name processing_system7_0_FCLK_CLK1 -period 7 [get_pins processing_system7_0/FCLK_CLK1] +create_clock -name processing_system7_0_FCLK_CLK1 -period 8.462 [get_pins processing_system7_0/FCLK_CLK1] create_clock -name processing_system7_0_FCLK_CLK2 -period 13 [get_pins processing_system7_0/FCLK_CLK2] create_clock -name processing_system7_0_FCLK_CLK3 -period 20 [get_pins processing_system7_0/FCLK_CLK3] diff --git a/src/bd/Arty_Z7_20/hdl/Arty_Z7_20.hwdef b/src/bd/Arty_Z7_20/hdl/Arty_Z7_20.hwdef index 689fcc8..5c921e5 100644 Binary files a/src/bd/Arty_Z7_20/hdl/Arty_Z7_20.hwdef and b/src/bd/Arty_Z7_20/hdl/Arty_Z7_20.hwdef differ diff --git a/src/bd/Arty_Z7_20/hdl/Arty_Z7_20.vhd b/src/bd/Arty_Z7_20/hdl/Arty_Z7_20.vhd index 99de603..01bbc92 100644 --- a/src/bd/Arty_Z7_20/hdl/Arty_Z7_20.vhd +++ b/src/bd/Arty_Z7_20/hdl/Arty_Z7_20.vhd @@ -1,7 +1,7 @@ --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------- --Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 ---Date : Mon Feb 27 10:04:53 2017 +--Date : Mon Mar 06 11:44:15 2017 --Host : WK73 running 64-bit Service Pack 1 (build 7601) --Command : generate_target Arty_Z7_20.bd --Design : Arty_Z7_20 @@ -112,6 +112,422 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; +entity m00_couplers_imp_GMOBOL is + port ( + M_ACLK : in STD_LOGIC; + M_ARESETN : in STD_LOGIC; + M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_arready : in STD_LOGIC; + M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_arvalid : out STD_LOGIC; + M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_awready : in STD_LOGIC; + M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_awvalid : out STD_LOGIC; + M_AXI_bid : in STD_LOGIC_VECTOR ( 5 downto 0 ); + M_AXI_bready : out STD_LOGIC; + M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_bvalid : in STD_LOGIC; + M_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + M_AXI_rid : in STD_LOGIC_VECTOR ( 5 downto 0 ); + M_AXI_rlast : in STD_LOGIC; + M_AXI_rready : out STD_LOGIC; + M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_rvalid : in STD_LOGIC; + M_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + M_AXI_wid : out STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_wlast : out STD_LOGIC; + M_AXI_wready : in STD_LOGIC; + M_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + M_AXI_wvalid : out STD_LOGIC; + S_ACLK : in STD_LOGIC; + S_ARESETN : in STD_LOGIC; + S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); + S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); + S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_arready : out STD_LOGIC; + S_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_arvalid : in STD_LOGIC; + S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); + S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); + S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_awready : out STD_LOGIC; + S_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_awvalid : in STD_LOGIC; + S_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 ); + S_AXI_bready : in STD_LOGIC; + S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_bvalid : out STD_LOGIC; + S_AXI_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 ); + S_AXI_rlast : out STD_LOGIC; + S_AXI_rready : in STD_LOGIC; + S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_rvalid : out STD_LOGIC; + S_AXI_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_wlast : in STD_LOGIC; + S_AXI_wready : out STD_LOGIC; + S_AXI_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_wvalid : in STD_LOGIC + ); +end m00_couplers_imp_GMOBOL; + +architecture STRUCTURE of m00_couplers_imp_GMOBOL is + component Arty_Z7_20_auto_pc_0 is + port ( + aclk : in STD_LOGIC; + aresetn : in STD_LOGIC; + s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_wlast : in STD_LOGIC; + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arvalid : in STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rlast : out STD_LOGIC; + s_axi_rvalid : out STD_LOGIC; + s_axi_rready : in STD_LOGIC; + m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awvalid : out STD_LOGIC; + m_axi_awready : in STD_LOGIC; + m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_wlast : out STD_LOGIC; + m_axi_wvalid : out STD_LOGIC; + m_axi_wready : in STD_LOGIC; + m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_bvalid : in STD_LOGIC; + m_axi_bready : out STD_LOGIC; + m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arvalid : out STD_LOGIC; + m_axi_arready : in STD_LOGIC; + m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_rlast : in STD_LOGIC; + m_axi_rvalid : in STD_LOGIC; + m_axi_rready : out STD_LOGIC + ); + end component Arty_Z7_20_auto_pc_0; + signal S_ACLK_1 : STD_LOGIC; + signal S_ARESETN_1 : STD_LOGIC; + signal auto_pc_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal auto_pc_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_pc_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_pc_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal auto_pc_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_pc_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_pc_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal auto_pc_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_pc_to_m00_couplers_ARREADY : STD_LOGIC; + signal auto_pc_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal auto_pc_to_m00_couplers_ARVALID : STD_LOGIC; + signal auto_pc_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal auto_pc_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_pc_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_pc_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal auto_pc_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_pc_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_pc_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal auto_pc_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal auto_pc_to_m00_couplers_AWREADY : STD_LOGIC; + signal auto_pc_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal auto_pc_to_m00_couplers_AWVALID : STD_LOGIC; + signal auto_pc_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal auto_pc_to_m00_couplers_BREADY : STD_LOGIC; + signal auto_pc_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_pc_to_m00_couplers_BVALID : STD_LOGIC; + signal auto_pc_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal auto_pc_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal auto_pc_to_m00_couplers_RLAST : STD_LOGIC; + signal auto_pc_to_m00_couplers_RREADY : STD_LOGIC; + signal auto_pc_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal auto_pc_to_m00_couplers_RVALID : STD_LOGIC; + signal auto_pc_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal auto_pc_to_m00_couplers_WID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal auto_pc_to_m00_couplers_WLAST : STD_LOGIC; + signal auto_pc_to_m00_couplers_WREADY : STD_LOGIC; + signal auto_pc_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal auto_pc_to_m00_couplers_WVALID : STD_LOGIC; + signal m00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal m00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal m00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal m00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); + signal m00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal m00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal m00_couplers_to_auto_pc_ARREADY : STD_LOGIC; + signal m00_couplers_to_auto_pc_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal m00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal m00_couplers_to_auto_pc_ARVALID : STD_LOGIC; + signal m00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal m00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal m00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal m00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); + signal m00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal m00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal m00_couplers_to_auto_pc_AWREADY : STD_LOGIC; + signal m00_couplers_to_auto_pc_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal m00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal m00_couplers_to_auto_pc_AWVALID : STD_LOGIC; + signal m00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal m00_couplers_to_auto_pc_BREADY : STD_LOGIC; + signal m00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m00_couplers_to_auto_pc_BVALID : STD_LOGIC; + signal m00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal m00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal m00_couplers_to_auto_pc_RLAST : STD_LOGIC; + signal m00_couplers_to_auto_pc_RREADY : STD_LOGIC; + signal m00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m00_couplers_to_auto_pc_RVALID : STD_LOGIC; + signal m00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal m00_couplers_to_auto_pc_WLAST : STD_LOGIC; + signal m00_couplers_to_auto_pc_WREADY : STD_LOGIC; + signal m00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal m00_couplers_to_auto_pc_WVALID : STD_LOGIC; +begin + M_AXI_araddr(31 downto 0) <= auto_pc_to_m00_couplers_ARADDR(31 downto 0); + M_AXI_arburst(1 downto 0) <= auto_pc_to_m00_couplers_ARBURST(1 downto 0); + M_AXI_arcache(3 downto 0) <= auto_pc_to_m00_couplers_ARCACHE(3 downto 0); + M_AXI_arid(0) <= auto_pc_to_m00_couplers_ARID(0); + M_AXI_arlen(3 downto 0) <= auto_pc_to_m00_couplers_ARLEN(3 downto 0); + M_AXI_arlock(1 downto 0) <= auto_pc_to_m00_couplers_ARLOCK(1 downto 0); + M_AXI_arprot(2 downto 0) <= auto_pc_to_m00_couplers_ARPROT(2 downto 0); + M_AXI_arqos(3 downto 0) <= auto_pc_to_m00_couplers_ARQOS(3 downto 0); + M_AXI_arsize(2 downto 0) <= auto_pc_to_m00_couplers_ARSIZE(2 downto 0); + M_AXI_arvalid <= auto_pc_to_m00_couplers_ARVALID; + M_AXI_awaddr(31 downto 0) <= auto_pc_to_m00_couplers_AWADDR(31 downto 0); + M_AXI_awburst(1 downto 0) <= auto_pc_to_m00_couplers_AWBURST(1 downto 0); + M_AXI_awcache(3 downto 0) <= auto_pc_to_m00_couplers_AWCACHE(3 downto 0); + M_AXI_awid(0) <= auto_pc_to_m00_couplers_AWID(0); + M_AXI_awlen(3 downto 0) <= auto_pc_to_m00_couplers_AWLEN(3 downto 0); + M_AXI_awlock(1 downto 0) <= auto_pc_to_m00_couplers_AWLOCK(1 downto 0); + M_AXI_awprot(2 downto 0) <= auto_pc_to_m00_couplers_AWPROT(2 downto 0); + M_AXI_awqos(3 downto 0) <= auto_pc_to_m00_couplers_AWQOS(3 downto 0); + M_AXI_awsize(2 downto 0) <= auto_pc_to_m00_couplers_AWSIZE(2 downto 0); + M_AXI_awvalid <= auto_pc_to_m00_couplers_AWVALID; + M_AXI_bready <= auto_pc_to_m00_couplers_BREADY; + M_AXI_rready <= auto_pc_to_m00_couplers_RREADY; + M_AXI_wdata(63 downto 0) <= auto_pc_to_m00_couplers_WDATA(63 downto 0); + M_AXI_wid(0) <= auto_pc_to_m00_couplers_WID(0); + M_AXI_wlast <= auto_pc_to_m00_couplers_WLAST; + M_AXI_wstrb(7 downto 0) <= auto_pc_to_m00_couplers_WSTRB(7 downto 0); + M_AXI_wvalid <= auto_pc_to_m00_couplers_WVALID; + S_ACLK_1 <= S_ACLK; + S_ARESETN_1 <= S_ARESETN; + S_AXI_arready <= m00_couplers_to_auto_pc_ARREADY; + S_AXI_awready <= m00_couplers_to_auto_pc_AWREADY; + S_AXI_bid(0) <= m00_couplers_to_auto_pc_BID(0); + S_AXI_bresp(1 downto 0) <= m00_couplers_to_auto_pc_BRESP(1 downto 0); + S_AXI_bvalid <= m00_couplers_to_auto_pc_BVALID; + S_AXI_rdata(63 downto 0) <= m00_couplers_to_auto_pc_RDATA(63 downto 0); + S_AXI_rid(0) <= m00_couplers_to_auto_pc_RID(0); + S_AXI_rlast <= m00_couplers_to_auto_pc_RLAST; + S_AXI_rresp(1 downto 0) <= m00_couplers_to_auto_pc_RRESP(1 downto 0); + S_AXI_rvalid <= m00_couplers_to_auto_pc_RVALID; + S_AXI_wready <= m00_couplers_to_auto_pc_WREADY; + auto_pc_to_m00_couplers_ARREADY <= M_AXI_arready; + auto_pc_to_m00_couplers_AWREADY <= M_AXI_awready; + auto_pc_to_m00_couplers_BID(5 downto 0) <= M_AXI_bid(5 downto 0); + auto_pc_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); + auto_pc_to_m00_couplers_BVALID <= M_AXI_bvalid; + auto_pc_to_m00_couplers_RDATA(63 downto 0) <= M_AXI_rdata(63 downto 0); + auto_pc_to_m00_couplers_RID(5 downto 0) <= M_AXI_rid(5 downto 0); + auto_pc_to_m00_couplers_RLAST <= M_AXI_rlast; + auto_pc_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); + auto_pc_to_m00_couplers_RVALID <= M_AXI_rvalid; + auto_pc_to_m00_couplers_WREADY <= M_AXI_wready; + m00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0); + m00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0); + m00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0); + m00_couplers_to_auto_pc_ARID(0) <= S_AXI_arid(0); + m00_couplers_to_auto_pc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0); + m00_couplers_to_auto_pc_ARLOCK(0) <= S_AXI_arlock(0); + m00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0); + m00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0); + m00_couplers_to_auto_pc_ARREGION(3 downto 0) <= S_AXI_arregion(3 downto 0); + m00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0); + m00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid; + m00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0); + m00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0); + m00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0); + m00_couplers_to_auto_pc_AWID(0) <= S_AXI_awid(0); + m00_couplers_to_auto_pc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0); + m00_couplers_to_auto_pc_AWLOCK(0) <= S_AXI_awlock(0); + m00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0); + m00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0); + m00_couplers_to_auto_pc_AWREGION(3 downto 0) <= S_AXI_awregion(3 downto 0); + m00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0); + m00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid; + m00_couplers_to_auto_pc_BREADY <= S_AXI_bready; + m00_couplers_to_auto_pc_RREADY <= S_AXI_rready; + m00_couplers_to_auto_pc_WDATA(63 downto 0) <= S_AXI_wdata(63 downto 0); + m00_couplers_to_auto_pc_WLAST <= S_AXI_wlast; + m00_couplers_to_auto_pc_WSTRB(7 downto 0) <= S_AXI_wstrb(7 downto 0); + m00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid; +auto_pc: component Arty_Z7_20_auto_pc_0 + port map ( + aclk => S_ACLK_1, + aresetn => S_ARESETN_1, + m_axi_araddr(31 downto 0) => auto_pc_to_m00_couplers_ARADDR(31 downto 0), + m_axi_arburst(1 downto 0) => auto_pc_to_m00_couplers_ARBURST(1 downto 0), + m_axi_arcache(3 downto 0) => auto_pc_to_m00_couplers_ARCACHE(3 downto 0), + m_axi_arid(0) => auto_pc_to_m00_couplers_ARID(0), + m_axi_arlen(3 downto 0) => auto_pc_to_m00_couplers_ARLEN(3 downto 0), + m_axi_arlock(1 downto 0) => auto_pc_to_m00_couplers_ARLOCK(1 downto 0), + m_axi_arprot(2 downto 0) => auto_pc_to_m00_couplers_ARPROT(2 downto 0), + m_axi_arqos(3 downto 0) => auto_pc_to_m00_couplers_ARQOS(3 downto 0), + m_axi_arready => auto_pc_to_m00_couplers_ARREADY, + m_axi_arsize(2 downto 0) => auto_pc_to_m00_couplers_ARSIZE(2 downto 0), + m_axi_arvalid => auto_pc_to_m00_couplers_ARVALID, + m_axi_awaddr(31 downto 0) => auto_pc_to_m00_couplers_AWADDR(31 downto 0), + m_axi_awburst(1 downto 0) => auto_pc_to_m00_couplers_AWBURST(1 downto 0), + m_axi_awcache(3 downto 0) => auto_pc_to_m00_couplers_AWCACHE(3 downto 0), + m_axi_awid(0) => auto_pc_to_m00_couplers_AWID(0), + m_axi_awlen(3 downto 0) => auto_pc_to_m00_couplers_AWLEN(3 downto 0), + m_axi_awlock(1 downto 0) => auto_pc_to_m00_couplers_AWLOCK(1 downto 0), + m_axi_awprot(2 downto 0) => auto_pc_to_m00_couplers_AWPROT(2 downto 0), + m_axi_awqos(3 downto 0) => auto_pc_to_m00_couplers_AWQOS(3 downto 0), + m_axi_awready => auto_pc_to_m00_couplers_AWREADY, + m_axi_awsize(2 downto 0) => auto_pc_to_m00_couplers_AWSIZE(2 downto 0), + m_axi_awvalid => auto_pc_to_m00_couplers_AWVALID, + m_axi_bid(0) => auto_pc_to_m00_couplers_BID(0), + m_axi_bready => auto_pc_to_m00_couplers_BREADY, + m_axi_bresp(1 downto 0) => auto_pc_to_m00_couplers_BRESP(1 downto 0), + m_axi_bvalid => auto_pc_to_m00_couplers_BVALID, + m_axi_rdata(63 downto 0) => auto_pc_to_m00_couplers_RDATA(63 downto 0), + m_axi_rid(0) => auto_pc_to_m00_couplers_RID(0), + m_axi_rlast => auto_pc_to_m00_couplers_RLAST, + m_axi_rready => auto_pc_to_m00_couplers_RREADY, + m_axi_rresp(1 downto 0) => auto_pc_to_m00_couplers_RRESP(1 downto 0), + m_axi_rvalid => auto_pc_to_m00_couplers_RVALID, + m_axi_wdata(63 downto 0) => auto_pc_to_m00_couplers_WDATA(63 downto 0), + m_axi_wid(0) => auto_pc_to_m00_couplers_WID(0), + m_axi_wlast => auto_pc_to_m00_couplers_WLAST, + m_axi_wready => auto_pc_to_m00_couplers_WREADY, + m_axi_wstrb(7 downto 0) => auto_pc_to_m00_couplers_WSTRB(7 downto 0), + m_axi_wvalid => auto_pc_to_m00_couplers_WVALID, + s_axi_araddr(31 downto 0) => m00_couplers_to_auto_pc_ARADDR(31 downto 0), + s_axi_arburst(1 downto 0) => m00_couplers_to_auto_pc_ARBURST(1 downto 0), + s_axi_arcache(3 downto 0) => m00_couplers_to_auto_pc_ARCACHE(3 downto 0), + s_axi_arid(0) => m00_couplers_to_auto_pc_ARID(0), + s_axi_arlen(7 downto 0) => m00_couplers_to_auto_pc_ARLEN(7 downto 0), + s_axi_arlock(0) => m00_couplers_to_auto_pc_ARLOCK(0), + s_axi_arprot(2 downto 0) => m00_couplers_to_auto_pc_ARPROT(2 downto 0), + s_axi_arqos(3 downto 0) => m00_couplers_to_auto_pc_ARQOS(3 downto 0), + s_axi_arready => m00_couplers_to_auto_pc_ARREADY, + s_axi_arregion(3 downto 0) => m00_couplers_to_auto_pc_ARREGION(3 downto 0), + s_axi_arsize(2 downto 0) => m00_couplers_to_auto_pc_ARSIZE(2 downto 0), + s_axi_arvalid => m00_couplers_to_auto_pc_ARVALID, + s_axi_awaddr(31 downto 0) => m00_couplers_to_auto_pc_AWADDR(31 downto 0), + s_axi_awburst(1 downto 0) => m00_couplers_to_auto_pc_AWBURST(1 downto 0), + s_axi_awcache(3 downto 0) => m00_couplers_to_auto_pc_AWCACHE(3 downto 0), + s_axi_awid(0) => m00_couplers_to_auto_pc_AWID(0), + s_axi_awlen(7 downto 0) => m00_couplers_to_auto_pc_AWLEN(7 downto 0), + s_axi_awlock(0) => m00_couplers_to_auto_pc_AWLOCK(0), + s_axi_awprot(2 downto 0) => m00_couplers_to_auto_pc_AWPROT(2 downto 0), + s_axi_awqos(3 downto 0) => m00_couplers_to_auto_pc_AWQOS(3 downto 0), + s_axi_awready => m00_couplers_to_auto_pc_AWREADY, + s_axi_awregion(3 downto 0) => m00_couplers_to_auto_pc_AWREGION(3 downto 0), + s_axi_awsize(2 downto 0) => m00_couplers_to_auto_pc_AWSIZE(2 downto 0), + s_axi_awvalid => m00_couplers_to_auto_pc_AWVALID, + s_axi_bid(0) => m00_couplers_to_auto_pc_BID(0), + s_axi_bready => m00_couplers_to_auto_pc_BREADY, + s_axi_bresp(1 downto 0) => m00_couplers_to_auto_pc_BRESP(1 downto 0), + s_axi_bvalid => m00_couplers_to_auto_pc_BVALID, + s_axi_rdata(63 downto 0) => m00_couplers_to_auto_pc_RDATA(63 downto 0), + s_axi_rid(0) => m00_couplers_to_auto_pc_RID(0), + s_axi_rlast => m00_couplers_to_auto_pc_RLAST, + s_axi_rready => m00_couplers_to_auto_pc_RREADY, + s_axi_rresp(1 downto 0) => m00_couplers_to_auto_pc_RRESP(1 downto 0), + s_axi_rvalid => m00_couplers_to_auto_pc_RVALID, + s_axi_wdata(63 downto 0) => m00_couplers_to_auto_pc_WDATA(63 downto 0), + s_axi_wlast => m00_couplers_to_auto_pc_WLAST, + s_axi_wready => m00_couplers_to_auto_pc_WREADY, + s_axi_wstrb(7 downto 0) => m00_couplers_to_auto_pc_WSTRB(7 downto 0), + s_axi_wvalid => m00_couplers_to_auto_pc_WVALID + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; entity m01_couplers_imp_YWG3GZ is port ( M_ACLK : in STD_LOGIC; @@ -925,6 +1341,208 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; +entity m09_couplers_imp_1Q673FL is + port ( + M_ACLK : in STD_LOGIC; + M_ARESETN : in STD_LOGIC; + M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_arready : in STD_LOGIC; + M_AXI_arvalid : out STD_LOGIC; + M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_awready : in STD_LOGIC; + M_AXI_awvalid : out STD_LOGIC; + M_AXI_bready : out STD_LOGIC; + M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_bvalid : in STD_LOGIC; + M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_rready : out STD_LOGIC; + M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_rvalid : in STD_LOGIC; + M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_wready : in STD_LOGIC; + M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_wvalid : out STD_LOGIC; + S_ACLK : in STD_LOGIC; + S_ARESETN : in STD_LOGIC; + S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_arready : out STD_LOGIC; + S_AXI_arvalid : in STD_LOGIC; + S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_awready : out STD_LOGIC; + S_AXI_awvalid : in STD_LOGIC; + S_AXI_bready : in STD_LOGIC; + S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_bvalid : out STD_LOGIC; + S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_rready : in STD_LOGIC; + S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_rvalid : out STD_LOGIC; + S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_wready : out STD_LOGIC; + S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_wvalid : in STD_LOGIC + ); +end m09_couplers_imp_1Q673FL; + +architecture STRUCTURE of m09_couplers_imp_1Q673FL is + signal m09_couplers_to_m09_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m09_couplers_to_m09_couplers_ARREADY : STD_LOGIC; + signal m09_couplers_to_m09_couplers_ARVALID : STD_LOGIC; + signal m09_couplers_to_m09_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m09_couplers_to_m09_couplers_AWREADY : STD_LOGIC; + signal m09_couplers_to_m09_couplers_AWVALID : STD_LOGIC; + signal m09_couplers_to_m09_couplers_BREADY : STD_LOGIC; + signal m09_couplers_to_m09_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m09_couplers_to_m09_couplers_BVALID : STD_LOGIC; + signal m09_couplers_to_m09_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m09_couplers_to_m09_couplers_RREADY : STD_LOGIC; + signal m09_couplers_to_m09_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m09_couplers_to_m09_couplers_RVALID : STD_LOGIC; + signal m09_couplers_to_m09_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m09_couplers_to_m09_couplers_WREADY : STD_LOGIC; + signal m09_couplers_to_m09_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal m09_couplers_to_m09_couplers_WVALID : STD_LOGIC; +begin + M_AXI_araddr(31 downto 0) <= m09_couplers_to_m09_couplers_ARADDR(31 downto 0); + M_AXI_arvalid <= m09_couplers_to_m09_couplers_ARVALID; + M_AXI_awaddr(31 downto 0) <= m09_couplers_to_m09_couplers_AWADDR(31 downto 0); + M_AXI_awvalid <= m09_couplers_to_m09_couplers_AWVALID; + M_AXI_bready <= m09_couplers_to_m09_couplers_BREADY; + M_AXI_rready <= m09_couplers_to_m09_couplers_RREADY; + M_AXI_wdata(31 downto 0) <= m09_couplers_to_m09_couplers_WDATA(31 downto 0); + M_AXI_wstrb(3 downto 0) <= m09_couplers_to_m09_couplers_WSTRB(3 downto 0); + M_AXI_wvalid <= m09_couplers_to_m09_couplers_WVALID; + S_AXI_arready <= m09_couplers_to_m09_couplers_ARREADY; + S_AXI_awready <= m09_couplers_to_m09_couplers_AWREADY; + S_AXI_bresp(1 downto 0) <= m09_couplers_to_m09_couplers_BRESP(1 downto 0); + S_AXI_bvalid <= m09_couplers_to_m09_couplers_BVALID; + S_AXI_rdata(31 downto 0) <= m09_couplers_to_m09_couplers_RDATA(31 downto 0); + S_AXI_rresp(1 downto 0) <= m09_couplers_to_m09_couplers_RRESP(1 downto 0); + S_AXI_rvalid <= m09_couplers_to_m09_couplers_RVALID; + S_AXI_wready <= m09_couplers_to_m09_couplers_WREADY; + m09_couplers_to_m09_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0); + m09_couplers_to_m09_couplers_ARREADY <= M_AXI_arready; + m09_couplers_to_m09_couplers_ARVALID <= S_AXI_arvalid; + m09_couplers_to_m09_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0); + m09_couplers_to_m09_couplers_AWREADY <= M_AXI_awready; + m09_couplers_to_m09_couplers_AWVALID <= S_AXI_awvalid; + m09_couplers_to_m09_couplers_BREADY <= S_AXI_bready; + m09_couplers_to_m09_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); + m09_couplers_to_m09_couplers_BVALID <= M_AXI_bvalid; + m09_couplers_to_m09_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0); + m09_couplers_to_m09_couplers_RREADY <= S_AXI_rready; + m09_couplers_to_m09_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); + m09_couplers_to_m09_couplers_RVALID <= M_AXI_rvalid; + m09_couplers_to_m09_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0); + m09_couplers_to_m09_couplers_WREADY <= M_AXI_wready; + m09_couplers_to_m09_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0); + m09_couplers_to_m09_couplers_WVALID <= S_AXI_wvalid; +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity m10_couplers_imp_11L1DU3 is + port ( + M_ACLK : in STD_LOGIC; + M_ARESETN : in STD_LOGIC; + M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_arready : in STD_LOGIC; + M_AXI_arvalid : out STD_LOGIC; + M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_awready : in STD_LOGIC; + M_AXI_awvalid : out STD_LOGIC; + M_AXI_bready : out STD_LOGIC; + M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_bvalid : in STD_LOGIC; + M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_rready : out STD_LOGIC; + M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_rvalid : in STD_LOGIC; + M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_wready : in STD_LOGIC; + M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_wvalid : out STD_LOGIC; + S_ACLK : in STD_LOGIC; + S_ARESETN : in STD_LOGIC; + S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_arready : out STD_LOGIC; + S_AXI_arvalid : in STD_LOGIC; + S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_awready : out STD_LOGIC; + S_AXI_awvalid : in STD_LOGIC; + S_AXI_bready : in STD_LOGIC; + S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_bvalid : out STD_LOGIC; + S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_rready : in STD_LOGIC; + S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_rvalid : out STD_LOGIC; + S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_wready : out STD_LOGIC; + S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_wvalid : in STD_LOGIC + ); +end m10_couplers_imp_11L1DU3; + +architecture STRUCTURE of m10_couplers_imp_11L1DU3 is + signal m10_couplers_to_m10_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m10_couplers_to_m10_couplers_ARREADY : STD_LOGIC; + signal m10_couplers_to_m10_couplers_ARVALID : STD_LOGIC; + signal m10_couplers_to_m10_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m10_couplers_to_m10_couplers_AWREADY : STD_LOGIC; + signal m10_couplers_to_m10_couplers_AWVALID : STD_LOGIC; + signal m10_couplers_to_m10_couplers_BREADY : STD_LOGIC; + signal m10_couplers_to_m10_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m10_couplers_to_m10_couplers_BVALID : STD_LOGIC; + signal m10_couplers_to_m10_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m10_couplers_to_m10_couplers_RREADY : STD_LOGIC; + signal m10_couplers_to_m10_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m10_couplers_to_m10_couplers_RVALID : STD_LOGIC; + signal m10_couplers_to_m10_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m10_couplers_to_m10_couplers_WREADY : STD_LOGIC; + signal m10_couplers_to_m10_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal m10_couplers_to_m10_couplers_WVALID : STD_LOGIC; +begin + M_AXI_araddr(31 downto 0) <= m10_couplers_to_m10_couplers_ARADDR(31 downto 0); + M_AXI_arvalid <= m10_couplers_to_m10_couplers_ARVALID; + M_AXI_awaddr(31 downto 0) <= m10_couplers_to_m10_couplers_AWADDR(31 downto 0); + M_AXI_awvalid <= m10_couplers_to_m10_couplers_AWVALID; + M_AXI_bready <= m10_couplers_to_m10_couplers_BREADY; + M_AXI_rready <= m10_couplers_to_m10_couplers_RREADY; + M_AXI_wdata(31 downto 0) <= m10_couplers_to_m10_couplers_WDATA(31 downto 0); + M_AXI_wstrb(3 downto 0) <= m10_couplers_to_m10_couplers_WSTRB(3 downto 0); + M_AXI_wvalid <= m10_couplers_to_m10_couplers_WVALID; + S_AXI_arready <= m10_couplers_to_m10_couplers_ARREADY; + S_AXI_awready <= m10_couplers_to_m10_couplers_AWREADY; + S_AXI_bresp(1 downto 0) <= m10_couplers_to_m10_couplers_BRESP(1 downto 0); + S_AXI_bvalid <= m10_couplers_to_m10_couplers_BVALID; + S_AXI_rdata(31 downto 0) <= m10_couplers_to_m10_couplers_RDATA(31 downto 0); + S_AXI_rresp(1 downto 0) <= m10_couplers_to_m10_couplers_RRESP(1 downto 0); + S_AXI_rvalid <= m10_couplers_to_m10_couplers_RVALID; + S_AXI_wready <= m10_couplers_to_m10_couplers_WREADY; + m10_couplers_to_m10_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0); + m10_couplers_to_m10_couplers_ARREADY <= M_AXI_arready; + m10_couplers_to_m10_couplers_ARVALID <= S_AXI_arvalid; + m10_couplers_to_m10_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0); + m10_couplers_to_m10_couplers_AWREADY <= M_AXI_awready; + m10_couplers_to_m10_couplers_AWVALID <= S_AXI_awvalid; + m10_couplers_to_m10_couplers_BREADY <= S_AXI_bready; + m10_couplers_to_m10_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); + m10_couplers_to_m10_couplers_BVALID <= M_AXI_bvalid; + m10_couplers_to_m10_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0); + m10_couplers_to_m10_couplers_RREADY <= S_AXI_rready; + m10_couplers_to_m10_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); + m10_couplers_to_m10_couplers_RVALID <= M_AXI_rvalid; + m10_couplers_to_m10_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0); + m10_couplers_to_m10_couplers_WREADY <= M_AXI_wready; + m10_couplers_to_m10_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0); + m10_couplers_to_m10_couplers_WVALID <= S_AXI_wvalid; +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; entity s00_couplers_imp_OVN3S4 is port ( M_ACLK : in STD_LOGIC; @@ -932,8 +1550,8 @@ entity s00_couplers_imp_OVN3S4 is M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); - M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); - M_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); + M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_arready : in STD_LOGIC; @@ -1002,42 +1620,6 @@ architecture STRUCTURE of s00_couplers_imp_OVN3S4 is ); end component Arty_Z7_20_s00_regslice_0; component Arty_Z7_20_s00_data_fifo_0 is - port ( - aclk : in STD_LOGIC; - aresetn : in STD_LOGIC; - s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); - s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); - s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_arvalid : in STD_LOGIC; - s_axi_arready : out STD_LOGIC; - s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); - s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_rlast : out STD_LOGIC; - s_axi_rvalid : out STD_LOGIC; - s_axi_rready : in STD_LOGIC; - m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); - m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); - m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); - m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); - m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); - m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); - m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); - m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); - m_axi_arvalid : out STD_LOGIC; - m_axi_arready : in STD_LOGIC; - m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); - m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); - m_axi_rlast : in STD_LOGIC; - m_axi_rvalid : in STD_LOGIC; - m_axi_rready : out STD_LOGIC - ); - end component Arty_Z7_20_s00_data_fifo_0; - component Arty_Z7_20_auto_pc_0 is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; @@ -1058,12 +1640,13 @@ architecture STRUCTURE of s00_couplers_imp_OVN3S4 is s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); - m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); - m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; @@ -1073,26 +1656,11 @@ architecture STRUCTURE of s00_couplers_imp_OVN3S4 is m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); - end component Arty_Z7_20_auto_pc_0; + end component Arty_Z7_20_s00_data_fifo_0; signal M_ACLK_1 : STD_LOGIC; signal M_ARESETN_1 : STD_LOGIC; signal S_ACLK_1 : STD_LOGIC; signal S_ARESETN_1 : STD_LOGIC; - signal auto_pc_to_s00_data_fifo_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal auto_pc_to_s00_data_fifo_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal auto_pc_to_s00_data_fifo_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal auto_pc_to_s00_data_fifo_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal auto_pc_to_s00_data_fifo_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal auto_pc_to_s00_data_fifo_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal auto_pc_to_s00_data_fifo_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal auto_pc_to_s00_data_fifo_ARREADY : STD_LOGIC; - signal auto_pc_to_s00_data_fifo_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal auto_pc_to_s00_data_fifo_ARVALID : STD_LOGIC; - signal auto_pc_to_s00_data_fifo_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); - signal auto_pc_to_s00_data_fifo_RLAST : STD_LOGIC; - signal auto_pc_to_s00_data_fifo_RREADY : STD_LOGIC; - signal auto_pc_to_s00_data_fifo_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal auto_pc_to_s00_data_fifo_RVALID : STD_LOGIC; signal s00_couplers_to_s00_regslice_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_couplers_to_s00_regslice_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_couplers_to_s00_regslice_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); @@ -1109,8 +1677,8 @@ architecture STRUCTURE of s00_couplers_imp_OVN3S4 is signal s00_data_fifo_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal s00_data_fifo_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_data_fifo_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal s00_data_fifo_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal s00_data_fifo_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_data_fifo_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal s00_data_fifo_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); signal s00_data_fifo_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); signal s00_data_fifo_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal s00_data_fifo_to_s00_couplers_ARREADY : STD_LOGIC; @@ -1121,30 +1689,31 @@ architecture STRUCTURE of s00_couplers_imp_OVN3S4 is signal s00_data_fifo_to_s00_couplers_RREADY : STD_LOGIC; signal s00_data_fifo_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal s00_data_fifo_to_s00_couplers_RVALID : STD_LOGIC; - signal s00_regslice_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal s00_regslice_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal s00_regslice_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal s00_regslice_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal s00_regslice_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); - signal s00_regslice_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal s00_regslice_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal s00_regslice_to_auto_pc_ARREADY : STD_LOGIC; - signal s00_regslice_to_auto_pc_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal s00_regslice_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal s00_regslice_to_auto_pc_ARVALID : STD_LOGIC; - signal s00_regslice_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); - signal s00_regslice_to_auto_pc_RLAST : STD_LOGIC; - signal s00_regslice_to_auto_pc_RREADY : STD_LOGIC; - signal s00_regslice_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal s00_regslice_to_auto_pc_RVALID : STD_LOGIC; + signal s00_regslice_to_s00_data_fifo_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_regslice_to_s00_data_fifo_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_regslice_to_s00_data_fifo_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_regslice_to_s00_data_fifo_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal s00_regslice_to_s00_data_fifo_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); + signal s00_regslice_to_s00_data_fifo_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_regslice_to_s00_data_fifo_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_regslice_to_s00_data_fifo_ARREADY : STD_LOGIC; + signal s00_regslice_to_s00_data_fifo_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_regslice_to_s00_data_fifo_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_regslice_to_s00_data_fifo_ARVALID : STD_LOGIC; + signal s00_regslice_to_s00_data_fifo_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal s00_regslice_to_s00_data_fifo_RLAST : STD_LOGIC; + signal s00_regslice_to_s00_data_fifo_RREADY : STD_LOGIC; + signal s00_regslice_to_s00_data_fifo_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_regslice_to_s00_data_fifo_RVALID : STD_LOGIC; + signal NLW_s00_data_fifo_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); begin M_ACLK_1 <= M_ACLK; M_ARESETN_1 <= M_ARESETN; M_AXI_araddr(31 downto 0) <= s00_data_fifo_to_s00_couplers_ARADDR(31 downto 0); M_AXI_arburst(1 downto 0) <= s00_data_fifo_to_s00_couplers_ARBURST(1 downto 0); M_AXI_arcache(3 downto 0) <= s00_data_fifo_to_s00_couplers_ARCACHE(3 downto 0); - M_AXI_arlen(3 downto 0) <= s00_data_fifo_to_s00_couplers_ARLEN(3 downto 0); - M_AXI_arlock(1 downto 0) <= s00_data_fifo_to_s00_couplers_ARLOCK(1 downto 0); + M_AXI_arlen(7 downto 0) <= s00_data_fifo_to_s00_couplers_ARLEN(7 downto 0); + M_AXI_arlock(0) <= s00_data_fifo_to_s00_couplers_ARLOCK(0); M_AXI_arprot(2 downto 0) <= s00_data_fifo_to_s00_couplers_ARPROT(2 downto 0); M_AXI_arqos(3 downto 0) <= s00_data_fifo_to_s00_couplers_ARQOS(3 downto 0); M_AXI_arsize(2 downto 0) <= s00_data_fifo_to_s00_couplers_ARSIZE(2 downto 0); @@ -1170,42 +1739,6 @@ begin s00_data_fifo_to_s00_couplers_RLAST <= M_AXI_rlast; s00_data_fifo_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0); s00_data_fifo_to_s00_couplers_RVALID <= M_AXI_rvalid; -auto_pc: component Arty_Z7_20_auto_pc_0 - port map ( - aclk => S_ACLK_1, - aresetn => S_ARESETN_1, - m_axi_araddr(31 downto 0) => auto_pc_to_s00_data_fifo_ARADDR(31 downto 0), - m_axi_arburst(1 downto 0) => auto_pc_to_s00_data_fifo_ARBURST(1 downto 0), - m_axi_arcache(3 downto 0) => auto_pc_to_s00_data_fifo_ARCACHE(3 downto 0), - m_axi_arlen(3 downto 0) => auto_pc_to_s00_data_fifo_ARLEN(3 downto 0), - m_axi_arlock(1 downto 0) => auto_pc_to_s00_data_fifo_ARLOCK(1 downto 0), - m_axi_arprot(2 downto 0) => auto_pc_to_s00_data_fifo_ARPROT(2 downto 0), - m_axi_arqos(3 downto 0) => auto_pc_to_s00_data_fifo_ARQOS(3 downto 0), - m_axi_arready => auto_pc_to_s00_data_fifo_ARREADY, - m_axi_arsize(2 downto 0) => auto_pc_to_s00_data_fifo_ARSIZE(2 downto 0), - m_axi_arvalid => auto_pc_to_s00_data_fifo_ARVALID, - m_axi_rdata(63 downto 0) => auto_pc_to_s00_data_fifo_RDATA(63 downto 0), - m_axi_rlast => auto_pc_to_s00_data_fifo_RLAST, - m_axi_rready => auto_pc_to_s00_data_fifo_RREADY, - m_axi_rresp(1 downto 0) => auto_pc_to_s00_data_fifo_RRESP(1 downto 0), - m_axi_rvalid => auto_pc_to_s00_data_fifo_RVALID, - s_axi_araddr(31 downto 0) => s00_regslice_to_auto_pc_ARADDR(31 downto 0), - s_axi_arburst(1 downto 0) => s00_regslice_to_auto_pc_ARBURST(1 downto 0), - s_axi_arcache(3 downto 0) => s00_regslice_to_auto_pc_ARCACHE(3 downto 0), - s_axi_arlen(7 downto 0) => s00_regslice_to_auto_pc_ARLEN(7 downto 0), - s_axi_arlock(0) => s00_regslice_to_auto_pc_ARLOCK(0), - s_axi_arprot(2 downto 0) => s00_regslice_to_auto_pc_ARPROT(2 downto 0), - s_axi_arqos(3 downto 0) => s00_regslice_to_auto_pc_ARQOS(3 downto 0), - s_axi_arready => s00_regslice_to_auto_pc_ARREADY, - s_axi_arregion(3 downto 0) => s00_regslice_to_auto_pc_ARREGION(3 downto 0), - s_axi_arsize(2 downto 0) => s00_regslice_to_auto_pc_ARSIZE(2 downto 0), - s_axi_arvalid => s00_regslice_to_auto_pc_ARVALID, - s_axi_rdata(63 downto 0) => s00_regslice_to_auto_pc_RDATA(63 downto 0), - s_axi_rlast => s00_regslice_to_auto_pc_RLAST, - s_axi_rready => s00_regslice_to_auto_pc_RREADY, - s_axi_rresp(1 downto 0) => s00_regslice_to_auto_pc_RRESP(1 downto 0), - s_axi_rvalid => s00_regslice_to_auto_pc_RVALID - ); s00_data_fifo: component Arty_Z7_20_s00_data_fifo_0 port map ( aclk => M_ACLK_1, @@ -1213,11 +1746,12 @@ s00_data_fifo: component Arty_Z7_20_s00_data_fifo_0 m_axi_araddr(31 downto 0) => s00_data_fifo_to_s00_couplers_ARADDR(31 downto 0), m_axi_arburst(1 downto 0) => s00_data_fifo_to_s00_couplers_ARBURST(1 downto 0), m_axi_arcache(3 downto 0) => s00_data_fifo_to_s00_couplers_ARCACHE(3 downto 0), - m_axi_arlen(3 downto 0) => s00_data_fifo_to_s00_couplers_ARLEN(3 downto 0), - m_axi_arlock(1 downto 0) => s00_data_fifo_to_s00_couplers_ARLOCK(1 downto 0), + m_axi_arlen(7 downto 0) => s00_data_fifo_to_s00_couplers_ARLEN(7 downto 0), + m_axi_arlock(0) => s00_data_fifo_to_s00_couplers_ARLOCK(0), m_axi_arprot(2 downto 0) => s00_data_fifo_to_s00_couplers_ARPROT(2 downto 0), m_axi_arqos(3 downto 0) => s00_data_fifo_to_s00_couplers_ARQOS(3 downto 0), m_axi_arready => s00_data_fifo_to_s00_couplers_ARREADY, + m_axi_arregion(3 downto 0) => NLW_s00_data_fifo_m_axi_arregion_UNCONNECTED(3 downto 0), m_axi_arsize(2 downto 0) => s00_data_fifo_to_s00_couplers_ARSIZE(2 downto 0), m_axi_arvalid => s00_data_fifo_to_s00_couplers_ARVALID, m_axi_rdata(63 downto 0) => s00_data_fifo_to_s00_couplers_RDATA(63 downto 0), @@ -1225,42 +1759,43 @@ s00_data_fifo: component Arty_Z7_20_s00_data_fifo_0 m_axi_rready => s00_data_fifo_to_s00_couplers_RREADY, m_axi_rresp(1 downto 0) => s00_data_fifo_to_s00_couplers_RRESP(1 downto 0), m_axi_rvalid => s00_data_fifo_to_s00_couplers_RVALID, - s_axi_araddr(31 downto 0) => auto_pc_to_s00_data_fifo_ARADDR(31 downto 0), - s_axi_arburst(1 downto 0) => auto_pc_to_s00_data_fifo_ARBURST(1 downto 0), - s_axi_arcache(3 downto 0) => auto_pc_to_s00_data_fifo_ARCACHE(3 downto 0), - s_axi_arlen(3 downto 0) => auto_pc_to_s00_data_fifo_ARLEN(3 downto 0), - s_axi_arlock(1 downto 0) => auto_pc_to_s00_data_fifo_ARLOCK(1 downto 0), - s_axi_arprot(2 downto 0) => auto_pc_to_s00_data_fifo_ARPROT(2 downto 0), - s_axi_arqos(3 downto 0) => auto_pc_to_s00_data_fifo_ARQOS(3 downto 0), - s_axi_arready => auto_pc_to_s00_data_fifo_ARREADY, - s_axi_arsize(2 downto 0) => auto_pc_to_s00_data_fifo_ARSIZE(2 downto 0), - s_axi_arvalid => auto_pc_to_s00_data_fifo_ARVALID, - s_axi_rdata(63 downto 0) => auto_pc_to_s00_data_fifo_RDATA(63 downto 0), - s_axi_rlast => auto_pc_to_s00_data_fifo_RLAST, - s_axi_rready => auto_pc_to_s00_data_fifo_RREADY, - s_axi_rresp(1 downto 0) => auto_pc_to_s00_data_fifo_RRESP(1 downto 0), - s_axi_rvalid => auto_pc_to_s00_data_fifo_RVALID + s_axi_araddr(31 downto 0) => s00_regslice_to_s00_data_fifo_ARADDR(31 downto 0), + s_axi_arburst(1 downto 0) => s00_regslice_to_s00_data_fifo_ARBURST(1 downto 0), + s_axi_arcache(3 downto 0) => s00_regslice_to_s00_data_fifo_ARCACHE(3 downto 0), + s_axi_arlen(7 downto 0) => s00_regslice_to_s00_data_fifo_ARLEN(7 downto 0), + s_axi_arlock(0) => s00_regslice_to_s00_data_fifo_ARLOCK(0), + s_axi_arprot(2 downto 0) => s00_regslice_to_s00_data_fifo_ARPROT(2 downto 0), + s_axi_arqos(3 downto 0) => s00_regslice_to_s00_data_fifo_ARQOS(3 downto 0), + s_axi_arready => s00_regslice_to_s00_data_fifo_ARREADY, + s_axi_arregion(3 downto 0) => s00_regslice_to_s00_data_fifo_ARREGION(3 downto 0), + s_axi_arsize(2 downto 0) => s00_regslice_to_s00_data_fifo_ARSIZE(2 downto 0), + s_axi_arvalid => s00_regslice_to_s00_data_fifo_ARVALID, + s_axi_rdata(63 downto 0) => s00_regslice_to_s00_data_fifo_RDATA(63 downto 0), + s_axi_rlast => s00_regslice_to_s00_data_fifo_RLAST, + s_axi_rready => s00_regslice_to_s00_data_fifo_RREADY, + s_axi_rresp(1 downto 0) => s00_regslice_to_s00_data_fifo_RRESP(1 downto 0), + s_axi_rvalid => s00_regslice_to_s00_data_fifo_RVALID ); s00_regslice: component Arty_Z7_20_s00_regslice_0 port map ( aclk => S_ACLK_1, aresetn => S_ARESETN_1, - m_axi_araddr(31 downto 0) => s00_regslice_to_auto_pc_ARADDR(31 downto 0), - m_axi_arburst(1 downto 0) => s00_regslice_to_auto_pc_ARBURST(1 downto 0), - m_axi_arcache(3 downto 0) => s00_regslice_to_auto_pc_ARCACHE(3 downto 0), - m_axi_arlen(7 downto 0) => s00_regslice_to_auto_pc_ARLEN(7 downto 0), - m_axi_arlock(0) => s00_regslice_to_auto_pc_ARLOCK(0), - m_axi_arprot(2 downto 0) => s00_regslice_to_auto_pc_ARPROT(2 downto 0), - m_axi_arqos(3 downto 0) => s00_regslice_to_auto_pc_ARQOS(3 downto 0), - m_axi_arready => s00_regslice_to_auto_pc_ARREADY, - m_axi_arregion(3 downto 0) => s00_regslice_to_auto_pc_ARREGION(3 downto 0), - m_axi_arsize(2 downto 0) => s00_regslice_to_auto_pc_ARSIZE(2 downto 0), - m_axi_arvalid => s00_regslice_to_auto_pc_ARVALID, - m_axi_rdata(63 downto 0) => s00_regslice_to_auto_pc_RDATA(63 downto 0), - m_axi_rlast => s00_regslice_to_auto_pc_RLAST, - m_axi_rready => s00_regslice_to_auto_pc_RREADY, - m_axi_rresp(1 downto 0) => s00_regslice_to_auto_pc_RRESP(1 downto 0), - m_axi_rvalid => s00_regslice_to_auto_pc_RVALID, + m_axi_araddr(31 downto 0) => s00_regslice_to_s00_data_fifo_ARADDR(31 downto 0), + m_axi_arburst(1 downto 0) => s00_regslice_to_s00_data_fifo_ARBURST(1 downto 0), + m_axi_arcache(3 downto 0) => s00_regslice_to_s00_data_fifo_ARCACHE(3 downto 0), + m_axi_arlen(7 downto 0) => s00_regslice_to_s00_data_fifo_ARLEN(7 downto 0), + m_axi_arlock(0) => s00_regslice_to_s00_data_fifo_ARLOCK(0), + m_axi_arprot(2 downto 0) => s00_regslice_to_s00_data_fifo_ARPROT(2 downto 0), + m_axi_arqos(3 downto 0) => s00_regslice_to_s00_data_fifo_ARQOS(3 downto 0), + m_axi_arready => s00_regslice_to_s00_data_fifo_ARREADY, + m_axi_arregion(3 downto 0) => s00_regslice_to_s00_data_fifo_ARREGION(3 downto 0), + m_axi_arsize(2 downto 0) => s00_regslice_to_s00_data_fifo_ARSIZE(2 downto 0), + m_axi_arvalid => s00_regslice_to_s00_data_fifo_ARVALID, + m_axi_rdata(63 downto 0) => s00_regslice_to_s00_data_fifo_RDATA(63 downto 0), + m_axi_rlast => s00_regslice_to_s00_data_fifo_RLAST, + m_axi_rready => s00_regslice_to_s00_data_fifo_RREADY, + m_axi_rresp(1 downto 0) => s00_regslice_to_s00_data_fifo_RRESP(1 downto 0), + m_axi_rvalid => s00_regslice_to_s00_data_fifo_RVALID, s_axi_araddr(31 downto 0) => s00_couplers_to_s00_regslice_ARADDR(31 downto 0), s_axi_arburst(1 downto 0) => s00_couplers_to_s00_regslice_ARBURST(1 downto 0), s_axi_arcache(3 downto 0) => s00_couplers_to_s00_regslice_ARCACHE(3 downto 0), @@ -1599,6 +2134,102 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; +entity s01_couplers_imp_GVC6G2 is + port ( + M_ACLK : in STD_LOGIC; + M_ARESETN : in STD_LOGIC; + M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); + M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_awready : in STD_LOGIC; + M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_awvalid : out STD_LOGIC; + M_AXI_bready : out STD_LOGIC; + M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_bvalid : in STD_LOGIC; + M_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + M_AXI_wlast : out STD_LOGIC; + M_AXI_wready : in STD_LOGIC; + M_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + M_AXI_wvalid : out STD_LOGIC; + S_ACLK : in STD_LOGIC; + S_ARESETN : in STD_LOGIC; + S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_awready : out STD_LOGIC; + S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_awvalid : in STD_LOGIC; + S_AXI_bready : in STD_LOGIC; + S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_bvalid : out STD_LOGIC; + S_AXI_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_wlast : in STD_LOGIC; + S_AXI_wready : out STD_LOGIC; + S_AXI_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_wvalid : in STD_LOGIC + ); +end s01_couplers_imp_GVC6G2; + +architecture STRUCTURE of s01_couplers_imp_GVC6G2 is + signal s01_couplers_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s01_couplers_to_s01_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s01_couplers_to_s01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s01_couplers_to_s01_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal s01_couplers_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s01_couplers_to_s01_couplers_AWREADY : STD_LOGIC; + signal s01_couplers_to_s01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s01_couplers_to_s01_couplers_AWVALID : STD_LOGIC; + signal s01_couplers_to_s01_couplers_BREADY : STD_LOGIC; + signal s01_couplers_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s01_couplers_to_s01_couplers_BVALID : STD_LOGIC; + signal s01_couplers_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal s01_couplers_to_s01_couplers_WLAST : STD_LOGIC; + signal s01_couplers_to_s01_couplers_WREADY : STD_LOGIC; + signal s01_couplers_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal s01_couplers_to_s01_couplers_WVALID : STD_LOGIC; +begin + M_AXI_awaddr(31 downto 0) <= s01_couplers_to_s01_couplers_AWADDR(31 downto 0); + M_AXI_awburst(1 downto 0) <= s01_couplers_to_s01_couplers_AWBURST(1 downto 0); + M_AXI_awcache(3 downto 0) <= s01_couplers_to_s01_couplers_AWCACHE(3 downto 0); + M_AXI_awlen(7 downto 0) <= s01_couplers_to_s01_couplers_AWLEN(7 downto 0); + M_AXI_awprot(2 downto 0) <= s01_couplers_to_s01_couplers_AWPROT(2 downto 0); + M_AXI_awsize(2 downto 0) <= s01_couplers_to_s01_couplers_AWSIZE(2 downto 0); + M_AXI_awvalid <= s01_couplers_to_s01_couplers_AWVALID; + M_AXI_bready <= s01_couplers_to_s01_couplers_BREADY; + M_AXI_wdata(63 downto 0) <= s01_couplers_to_s01_couplers_WDATA(63 downto 0); + M_AXI_wlast <= s01_couplers_to_s01_couplers_WLAST; + M_AXI_wstrb(7 downto 0) <= s01_couplers_to_s01_couplers_WSTRB(7 downto 0); + M_AXI_wvalid <= s01_couplers_to_s01_couplers_WVALID; + S_AXI_awready <= s01_couplers_to_s01_couplers_AWREADY; + S_AXI_bresp(1 downto 0) <= s01_couplers_to_s01_couplers_BRESP(1 downto 0); + S_AXI_bvalid <= s01_couplers_to_s01_couplers_BVALID; + S_AXI_wready <= s01_couplers_to_s01_couplers_WREADY; + s01_couplers_to_s01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0); + s01_couplers_to_s01_couplers_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0); + s01_couplers_to_s01_couplers_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0); + s01_couplers_to_s01_couplers_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0); + s01_couplers_to_s01_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0); + s01_couplers_to_s01_couplers_AWREADY <= M_AXI_awready; + s01_couplers_to_s01_couplers_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0); + s01_couplers_to_s01_couplers_AWVALID <= S_AXI_awvalid; + s01_couplers_to_s01_couplers_BREADY <= S_AXI_bready; + s01_couplers_to_s01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0); + s01_couplers_to_s01_couplers_BVALID <= M_AXI_bvalid; + s01_couplers_to_s01_couplers_WDATA(63 downto 0) <= S_AXI_wdata(63 downto 0); + s01_couplers_to_s01_couplers_WLAST <= S_AXI_wlast; + s01_couplers_to_s01_couplers_WREADY <= M_AXI_wready; + s01_couplers_to_s01_couplers_WSTRB(7 downto 0) <= S_AXI_wstrb(7 downto 0); + s01_couplers_to_s01_couplers_WVALID <= S_AXI_wvalid; +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20_axi_mem_intercon_0 is port ( ACLK : in STD_LOGIC; @@ -1608,6 +2239,7 @@ entity Arty_Z7_20_axi_mem_intercon_0 is M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 ); M00_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); M00_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); @@ -1615,11 +2247,33 @@ entity Arty_Z7_20_axi_mem_intercon_0 is M00_AXI_arready : in STD_LOGIC; M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); M00_AXI_arvalid : out STD_LOGIC; + M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 ); + M00_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M00_AXI_awready : in STD_LOGIC; + M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M00_AXI_awvalid : out STD_LOGIC; + M00_AXI_bid : in STD_LOGIC_VECTOR ( 5 downto 0 ); + M00_AXI_bready : out STD_LOGIC; + M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M00_AXI_bvalid : in STD_LOGIC; M00_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + M00_AXI_rid : in STD_LOGIC_VECTOR ( 5 downto 0 ); M00_AXI_rlast : in STD_LOGIC; M00_AXI_rready : out STD_LOGIC; M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); M00_AXI_rvalid : in STD_LOGIC; + M00_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + M00_AXI_wid : out STD_LOGIC_VECTOR ( 0 to 0 ); + M00_AXI_wlast : out STD_LOGIC; + M00_AXI_wready : in STD_LOGIC; + M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + M00_AXI_wvalid : out STD_LOGIC; S00_ACLK : in STD_LOGIC; S00_ARESETN : in STD_LOGIC; S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); @@ -1634,13 +2288,117 @@ entity Arty_Z7_20_axi_mem_intercon_0 is S00_AXI_rlast : out STD_LOGIC; S00_AXI_rready : in STD_LOGIC; S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); - S00_AXI_rvalid : out STD_LOGIC + S00_AXI_rvalid : out STD_LOGIC; + S01_ACLK : in STD_LOGIC; + S01_ARESETN : in STD_LOGIC; + S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S01_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S01_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S01_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S01_AXI_awready : out STD_LOGIC; + S01_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S01_AXI_awvalid : in STD_LOGIC; + S01_AXI_bready : in STD_LOGIC; + S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S01_AXI_bvalid : out STD_LOGIC; + S01_AXI_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + S01_AXI_wlast : in STD_LOGIC; + S01_AXI_wready : out STD_LOGIC; + S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 ); + S01_AXI_wvalid : in STD_LOGIC ); end Arty_Z7_20_axi_mem_intercon_0; architecture STRUCTURE of Arty_Z7_20_axi_mem_intercon_0 is + component Arty_Z7_20_xbar_1 is + port ( + aclk : in STD_LOGIC; + aresetn : in STD_LOGIC; + s_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 15 downto 0 ); + s_axi_awsize : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_awburst : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awcache : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_awqos : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_awvalid : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awready : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 ); + s_axi_wlast : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_wvalid : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_wready : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bid : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bresp : out STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_bvalid : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bready : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axi_arlen : in STD_LOGIC_VECTOR ( 15 downto 0 ); + s_axi_arsize : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_arburst : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arcache : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_arprot : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_arqos : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_arvalid : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arready : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rid : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_rlast : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rvalid : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rready : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rready : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + end component Arty_Z7_20_xbar_1; + signal M00_ACLK_1 : STD_LOGIC; + signal M00_ARESETN_1 : STD_LOGIC; signal S00_ACLK_1 : STD_LOGIC; signal S00_ARESETN_1 : STD_LOGIC; + signal S01_ACLK_1 : STD_LOGIC; + signal S01_ARESETN_1 : STD_LOGIC; signal axi_mem_intercon_ACLK_net : STD_LOGIC; signal axi_mem_intercon_ARESETN_net : STD_LOGIC; signal axi_mem_intercon_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); @@ -1656,32 +2414,171 @@ architecture STRUCTURE of Arty_Z7_20_axi_mem_intercon_0 is signal axi_mem_intercon_to_s00_couplers_RREADY : STD_LOGIC; signal axi_mem_intercon_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_to_s00_couplers_RVALID : STD_LOGIC; - signal s00_couplers_to_axi_mem_intercon_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal s00_couplers_to_axi_mem_intercon_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal s00_couplers_to_axi_mem_intercon_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal s00_couplers_to_axi_mem_intercon_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal s00_couplers_to_axi_mem_intercon_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal s00_couplers_to_axi_mem_intercon_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal s00_couplers_to_axi_mem_intercon_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal s00_couplers_to_axi_mem_intercon_ARREADY : STD_LOGIC; - signal s00_couplers_to_axi_mem_intercon_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal s00_couplers_to_axi_mem_intercon_ARVALID : STD_LOGIC; - signal s00_couplers_to_axi_mem_intercon_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); - signal s00_couplers_to_axi_mem_intercon_RLAST : STD_LOGIC; - signal s00_couplers_to_axi_mem_intercon_RREADY : STD_LOGIC; - signal s00_couplers_to_axi_mem_intercon_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal s00_couplers_to_axi_mem_intercon_RVALID : STD_LOGIC; + signal axi_mem_intercon_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_mem_intercon_to_s01_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_to_s01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_to_s01_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal axi_mem_intercon_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_mem_intercon_to_s01_couplers_AWREADY : STD_LOGIC; + signal axi_mem_intercon_to_s01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_mem_intercon_to_s01_couplers_AWVALID : STD_LOGIC; + signal axi_mem_intercon_to_s01_couplers_BREADY : STD_LOGIC; + signal axi_mem_intercon_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_to_s01_couplers_BVALID : STD_LOGIC; + signal axi_mem_intercon_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal axi_mem_intercon_to_s01_couplers_WLAST : STD_LOGIC; + signal axi_mem_intercon_to_s01_couplers_WREADY : STD_LOGIC; + signal axi_mem_intercon_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal axi_mem_intercon_to_s01_couplers_WVALID : STD_LOGIC; + signal m00_couplers_to_axi_mem_intercon_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m00_couplers_to_axi_mem_intercon_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m00_couplers_to_axi_mem_intercon_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal m00_couplers_to_axi_mem_intercon_ARID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal m00_couplers_to_axi_mem_intercon_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal m00_couplers_to_axi_mem_intercon_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m00_couplers_to_axi_mem_intercon_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal m00_couplers_to_axi_mem_intercon_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal m00_couplers_to_axi_mem_intercon_ARREADY : STD_LOGIC; + signal m00_couplers_to_axi_mem_intercon_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal m00_couplers_to_axi_mem_intercon_ARVALID : STD_LOGIC; + signal m00_couplers_to_axi_mem_intercon_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m00_couplers_to_axi_mem_intercon_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m00_couplers_to_axi_mem_intercon_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal m00_couplers_to_axi_mem_intercon_AWID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal m00_couplers_to_axi_mem_intercon_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal m00_couplers_to_axi_mem_intercon_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m00_couplers_to_axi_mem_intercon_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal m00_couplers_to_axi_mem_intercon_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal m00_couplers_to_axi_mem_intercon_AWREADY : STD_LOGIC; + signal m00_couplers_to_axi_mem_intercon_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal m00_couplers_to_axi_mem_intercon_AWVALID : STD_LOGIC; + signal m00_couplers_to_axi_mem_intercon_BID : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal m00_couplers_to_axi_mem_intercon_BREADY : STD_LOGIC; + signal m00_couplers_to_axi_mem_intercon_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m00_couplers_to_axi_mem_intercon_BVALID : STD_LOGIC; + signal m00_couplers_to_axi_mem_intercon_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal m00_couplers_to_axi_mem_intercon_RID : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal m00_couplers_to_axi_mem_intercon_RLAST : STD_LOGIC; + signal m00_couplers_to_axi_mem_intercon_RREADY : STD_LOGIC; + signal m00_couplers_to_axi_mem_intercon_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m00_couplers_to_axi_mem_intercon_RVALID : STD_LOGIC; + signal m00_couplers_to_axi_mem_intercon_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal m00_couplers_to_axi_mem_intercon_WID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal m00_couplers_to_axi_mem_intercon_WLAST : STD_LOGIC; + signal m00_couplers_to_axi_mem_intercon_WREADY : STD_LOGIC; + signal m00_couplers_to_axi_mem_intercon_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal m00_couplers_to_axi_mem_intercon_WVALID : STD_LOGIC; + signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s00_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal s00_couplers_to_xbar_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); + signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_xbar_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 ); + signal s00_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s00_couplers_to_xbar_ARVALID : STD_LOGIC; + signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal s00_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 0 to 0 ); + signal s00_couplers_to_xbar_RREADY : STD_LOGIC; + signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal s01_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s01_couplers_to_xbar_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal s01_couplers_to_xbar_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal s01_couplers_to_xbar_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal s01_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s01_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 1 to 1 ); + signal s01_couplers_to_xbar_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s01_couplers_to_xbar_AWVALID : STD_LOGIC; + signal s01_couplers_to_xbar_BREADY : STD_LOGIC; + signal s01_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal s01_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 1 to 1 ); + signal s01_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal s01_couplers_to_xbar_WLAST : STD_LOGIC; + signal s01_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 1 to 1 ); + signal s01_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal s01_couplers_to_xbar_WVALID : STD_LOGIC; + signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal xbar_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal xbar_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal xbar_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal xbar_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal xbar_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); + signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal xbar_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal xbar_to_m00_couplers_ARREADY : STD_LOGIC; + signal xbar_to_m00_couplers_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal xbar_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal xbar_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal xbar_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal xbar_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal xbar_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal xbar_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 ); + signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal xbar_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal xbar_to_m00_couplers_AWREADY : STD_LOGIC; + signal xbar_to_m00_couplers_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal xbar_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal xbar_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 ); + signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal xbar_to_m00_couplers_BVALID : STD_LOGIC; + signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal xbar_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal xbar_to_m00_couplers_RLAST : STD_LOGIC; + signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 ); + signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal xbar_to_m00_couplers_RVALID : STD_LOGIC; + signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal xbar_to_m00_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 ); + signal xbar_to_m00_couplers_WREADY : STD_LOGIC; + signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_xbar_s_axi_arready_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); + signal NLW_xbar_s_axi_awready_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_xbar_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_xbar_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_xbar_s_axi_bvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_xbar_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 127 downto 64 ); + signal NLW_xbar_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_xbar_s_axi_rlast_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); + signal NLW_xbar_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal NLW_xbar_s_axi_rvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); + signal NLW_xbar_s_axi_wready_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); begin - M00_AXI_araddr(31 downto 0) <= s00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0); - M00_AXI_arburst(1 downto 0) <= s00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0); - M00_AXI_arcache(3 downto 0) <= s00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0); - M00_AXI_arlen(3 downto 0) <= s00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0); - M00_AXI_arlock(1 downto 0) <= s00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0); - M00_AXI_arprot(2 downto 0) <= s00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0); - M00_AXI_arqos(3 downto 0) <= s00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0); - M00_AXI_arsize(2 downto 0) <= s00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0); - M00_AXI_arvalid <= s00_couplers_to_axi_mem_intercon_ARVALID; - M00_AXI_rready <= s00_couplers_to_axi_mem_intercon_RREADY; + M00_ACLK_1 <= M00_ACLK; + M00_ARESETN_1 <= M00_ARESETN; + M00_AXI_araddr(31 downto 0) <= m00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0); + M00_AXI_arburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0); + M00_AXI_arcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0); + M00_AXI_arid(0) <= m00_couplers_to_axi_mem_intercon_ARID(0); + M00_AXI_arlen(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0); + M00_AXI_arlock(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0); + M00_AXI_arprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0); + M00_AXI_arqos(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0); + M00_AXI_arsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0); + M00_AXI_arvalid <= m00_couplers_to_axi_mem_intercon_ARVALID; + M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0); + M00_AXI_awburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0); + M00_AXI_awcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0); + M00_AXI_awid(0) <= m00_couplers_to_axi_mem_intercon_AWID(0); + M00_AXI_awlen(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0); + M00_AXI_awlock(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWLOCK(1 downto 0); + M00_AXI_awprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0); + M00_AXI_awqos(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0); + M00_AXI_awsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0); + M00_AXI_awvalid <= m00_couplers_to_axi_mem_intercon_AWVALID; + M00_AXI_bready <= m00_couplers_to_axi_mem_intercon_BREADY; + M00_AXI_rready <= m00_couplers_to_axi_mem_intercon_RREADY; + M00_AXI_wdata(63 downto 0) <= m00_couplers_to_axi_mem_intercon_WDATA(63 downto 0); + M00_AXI_wid(0) <= m00_couplers_to_axi_mem_intercon_WID(0); + M00_AXI_wlast <= m00_couplers_to_axi_mem_intercon_WLAST; + M00_AXI_wstrb(7 downto 0) <= m00_couplers_to_axi_mem_intercon_WSTRB(7 downto 0); + M00_AXI_wvalid <= m00_couplers_to_axi_mem_intercon_WVALID; S00_ACLK_1 <= S00_ACLK; S00_ARESETN_1 <= S00_ARESETN; S00_AXI_arready <= axi_mem_intercon_to_s00_couplers_ARREADY; @@ -1689,8 +2586,14 @@ begin S00_AXI_rlast <= axi_mem_intercon_to_s00_couplers_RLAST; S00_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0); S00_AXI_rvalid <= axi_mem_intercon_to_s00_couplers_RVALID; - axi_mem_intercon_ACLK_net <= M00_ACLK; - axi_mem_intercon_ARESETN_net <= M00_ARESETN; + S01_ACLK_1 <= S01_ACLK; + S01_ARESETN_1 <= S01_ARESETN; + S01_AXI_awready <= axi_mem_intercon_to_s01_couplers_AWREADY; + S01_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s01_couplers_BRESP(1 downto 0); + S01_AXI_bvalid <= axi_mem_intercon_to_s01_couplers_BVALID; + S01_AXI_wready <= axi_mem_intercon_to_s01_couplers_WREADY; + axi_mem_intercon_ACLK_net <= ACLK; + axi_mem_intercon_ARESETN_net <= ARESETN; axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0); axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0); axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0); @@ -1699,30 +2602,132 @@ begin axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0); axi_mem_intercon_to_s00_couplers_ARVALID <= S00_AXI_arvalid; axi_mem_intercon_to_s00_couplers_RREADY <= S00_AXI_rready; - s00_couplers_to_axi_mem_intercon_ARREADY <= M00_AXI_arready; - s00_couplers_to_axi_mem_intercon_RDATA(63 downto 0) <= M00_AXI_rdata(63 downto 0); - s00_couplers_to_axi_mem_intercon_RLAST <= M00_AXI_rlast; - s00_couplers_to_axi_mem_intercon_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0); - s00_couplers_to_axi_mem_intercon_RVALID <= M00_AXI_rvalid; + axi_mem_intercon_to_s01_couplers_AWADDR(31 downto 0) <= S01_AXI_awaddr(31 downto 0); + axi_mem_intercon_to_s01_couplers_AWBURST(1 downto 0) <= S01_AXI_awburst(1 downto 0); + axi_mem_intercon_to_s01_couplers_AWCACHE(3 downto 0) <= S01_AXI_awcache(3 downto 0); + axi_mem_intercon_to_s01_couplers_AWLEN(7 downto 0) <= S01_AXI_awlen(7 downto 0); + axi_mem_intercon_to_s01_couplers_AWPROT(2 downto 0) <= S01_AXI_awprot(2 downto 0); + axi_mem_intercon_to_s01_couplers_AWSIZE(2 downto 0) <= S01_AXI_awsize(2 downto 0); + axi_mem_intercon_to_s01_couplers_AWVALID <= S01_AXI_awvalid; + axi_mem_intercon_to_s01_couplers_BREADY <= S01_AXI_bready; + axi_mem_intercon_to_s01_couplers_WDATA(63 downto 0) <= S01_AXI_wdata(63 downto 0); + axi_mem_intercon_to_s01_couplers_WLAST <= S01_AXI_wlast; + axi_mem_intercon_to_s01_couplers_WSTRB(7 downto 0) <= S01_AXI_wstrb(7 downto 0); + axi_mem_intercon_to_s01_couplers_WVALID <= S01_AXI_wvalid; + m00_couplers_to_axi_mem_intercon_ARREADY <= M00_AXI_arready; + m00_couplers_to_axi_mem_intercon_AWREADY <= M00_AXI_awready; + m00_couplers_to_axi_mem_intercon_BID(5 downto 0) <= M00_AXI_bid(5 downto 0); + m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0); + m00_couplers_to_axi_mem_intercon_BVALID <= M00_AXI_bvalid; + m00_couplers_to_axi_mem_intercon_RDATA(63 downto 0) <= M00_AXI_rdata(63 downto 0); + m00_couplers_to_axi_mem_intercon_RID(5 downto 0) <= M00_AXI_rid(5 downto 0); + m00_couplers_to_axi_mem_intercon_RLAST <= M00_AXI_rlast; + m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0); + m00_couplers_to_axi_mem_intercon_RVALID <= M00_AXI_rvalid; + m00_couplers_to_axi_mem_intercon_WREADY <= M00_AXI_wready; +m00_couplers: entity work.m00_couplers_imp_GMOBOL + port map ( + M_ACLK => M00_ACLK_1, + M_ARESETN => M00_ARESETN_1, + M_AXI_araddr(31 downto 0) => m00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0), + M_AXI_arburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0), + M_AXI_arcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0), + M_AXI_arid(0) => m00_couplers_to_axi_mem_intercon_ARID(0), + M_AXI_arlen(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0), + M_AXI_arlock(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0), + M_AXI_arprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0), + M_AXI_arqos(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0), + M_AXI_arready => m00_couplers_to_axi_mem_intercon_ARREADY, + M_AXI_arsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0), + M_AXI_arvalid => m00_couplers_to_axi_mem_intercon_ARVALID, + M_AXI_awaddr(31 downto 0) => m00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0), + M_AXI_awburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0), + M_AXI_awcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0), + M_AXI_awid(0) => m00_couplers_to_axi_mem_intercon_AWID(0), + M_AXI_awlen(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0), + M_AXI_awlock(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWLOCK(1 downto 0), + M_AXI_awprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0), + M_AXI_awqos(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0), + M_AXI_awready => m00_couplers_to_axi_mem_intercon_AWREADY, + M_AXI_awsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0), + M_AXI_awvalid => m00_couplers_to_axi_mem_intercon_AWVALID, + M_AXI_bid(5 downto 0) => m00_couplers_to_axi_mem_intercon_BID(5 downto 0), + M_AXI_bready => m00_couplers_to_axi_mem_intercon_BREADY, + M_AXI_bresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0), + M_AXI_bvalid => m00_couplers_to_axi_mem_intercon_BVALID, + M_AXI_rdata(63 downto 0) => m00_couplers_to_axi_mem_intercon_RDATA(63 downto 0), + M_AXI_rid(5 downto 0) => m00_couplers_to_axi_mem_intercon_RID(5 downto 0), + M_AXI_rlast => m00_couplers_to_axi_mem_intercon_RLAST, + M_AXI_rready => m00_couplers_to_axi_mem_intercon_RREADY, + M_AXI_rresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0), + M_AXI_rvalid => m00_couplers_to_axi_mem_intercon_RVALID, + M_AXI_wdata(63 downto 0) => m00_couplers_to_axi_mem_intercon_WDATA(63 downto 0), + M_AXI_wid(0) => m00_couplers_to_axi_mem_intercon_WID(0), + M_AXI_wlast => m00_couplers_to_axi_mem_intercon_WLAST, + M_AXI_wready => m00_couplers_to_axi_mem_intercon_WREADY, + M_AXI_wstrb(7 downto 0) => m00_couplers_to_axi_mem_intercon_WSTRB(7 downto 0), + M_AXI_wvalid => m00_couplers_to_axi_mem_intercon_WVALID, + S_ACLK => axi_mem_intercon_ACLK_net, + S_ARESETN => axi_mem_intercon_ARESETN_net, + S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0), + S_AXI_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0), + S_AXI_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0), + S_AXI_arid(0) => xbar_to_m00_couplers_ARID(0), + S_AXI_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0), + S_AXI_arlock(0) => xbar_to_m00_couplers_ARLOCK(0), + S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0), + S_AXI_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0), + S_AXI_arready => xbar_to_m00_couplers_ARREADY, + S_AXI_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0), + S_AXI_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0), + S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0), + S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0), + S_AXI_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0), + S_AXI_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0), + S_AXI_awid(0) => xbar_to_m00_couplers_AWID(0), + S_AXI_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0), + S_AXI_awlock(0) => xbar_to_m00_couplers_AWLOCK(0), + S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0), + S_AXI_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0), + S_AXI_awready => xbar_to_m00_couplers_AWREADY, + S_AXI_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0), + S_AXI_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0), + S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0), + S_AXI_bid(0) => xbar_to_m00_couplers_BID(0), + S_AXI_bready => xbar_to_m00_couplers_BREADY(0), + S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0), + S_AXI_bvalid => xbar_to_m00_couplers_BVALID, + S_AXI_rdata(63 downto 0) => xbar_to_m00_couplers_RDATA(63 downto 0), + S_AXI_rid(0) => xbar_to_m00_couplers_RID(0), + S_AXI_rlast => xbar_to_m00_couplers_RLAST, + S_AXI_rready => xbar_to_m00_couplers_RREADY(0), + S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0), + S_AXI_rvalid => xbar_to_m00_couplers_RVALID, + S_AXI_wdata(63 downto 0) => xbar_to_m00_couplers_WDATA(63 downto 0), + S_AXI_wlast => xbar_to_m00_couplers_WLAST(0), + S_AXI_wready => xbar_to_m00_couplers_WREADY, + S_AXI_wstrb(7 downto 0) => xbar_to_m00_couplers_WSTRB(7 downto 0), + S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0) + ); s00_couplers: entity work.s00_couplers_imp_OVN3S4 port map ( M_ACLK => axi_mem_intercon_ACLK_net, M_ARESETN => axi_mem_intercon_ARESETN_net, - M_AXI_araddr(31 downto 0) => s00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0), - M_AXI_arburst(1 downto 0) => s00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0), - M_AXI_arcache(3 downto 0) => s00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0), - M_AXI_arlen(3 downto 0) => s00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0), - M_AXI_arlock(1 downto 0) => s00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0), - M_AXI_arprot(2 downto 0) => s00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0), - M_AXI_arqos(3 downto 0) => s00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0), - M_AXI_arready => s00_couplers_to_axi_mem_intercon_ARREADY, - M_AXI_arsize(2 downto 0) => s00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0), - M_AXI_arvalid => s00_couplers_to_axi_mem_intercon_ARVALID, - M_AXI_rdata(63 downto 0) => s00_couplers_to_axi_mem_intercon_RDATA(63 downto 0), - M_AXI_rlast => s00_couplers_to_axi_mem_intercon_RLAST, - M_AXI_rready => s00_couplers_to_axi_mem_intercon_RREADY, - M_AXI_rresp(1 downto 0) => s00_couplers_to_axi_mem_intercon_RRESP(1 downto 0), - M_AXI_rvalid => s00_couplers_to_axi_mem_intercon_RVALID, + M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0), + M_AXI_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0), + M_AXI_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0), + M_AXI_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0), + M_AXI_arlock(0) => s00_couplers_to_xbar_ARLOCK(0), + M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0), + M_AXI_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0), + M_AXI_arready => s00_couplers_to_xbar_ARREADY(0), + M_AXI_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0), + M_AXI_arvalid => s00_couplers_to_xbar_ARVALID, + M_AXI_rdata(63 downto 0) => s00_couplers_to_xbar_RDATA(63 downto 0), + M_AXI_rlast => s00_couplers_to_xbar_RLAST(0), + M_AXI_rready => s00_couplers_to_xbar_RREADY, + M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0), + M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0), S_ACLK => S00_ACLK_1, S_ARESETN => S00_ARESETN_1, S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0), @@ -1739,6 +2744,157 @@ s00_couplers: entity work.s00_couplers_imp_OVN3S4 S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0), S_AXI_rvalid => axi_mem_intercon_to_s00_couplers_RVALID ); +s01_couplers: entity work.s01_couplers_imp_GVC6G2 + port map ( + M_ACLK => axi_mem_intercon_ACLK_net, + M_ARESETN => axi_mem_intercon_ARESETN_net, + M_AXI_awaddr(31 downto 0) => s01_couplers_to_xbar_AWADDR(31 downto 0), + M_AXI_awburst(1 downto 0) => s01_couplers_to_xbar_AWBURST(1 downto 0), + M_AXI_awcache(3 downto 0) => s01_couplers_to_xbar_AWCACHE(3 downto 0), + M_AXI_awlen(7 downto 0) => s01_couplers_to_xbar_AWLEN(7 downto 0), + M_AXI_awprot(2 downto 0) => s01_couplers_to_xbar_AWPROT(2 downto 0), + M_AXI_awready => s01_couplers_to_xbar_AWREADY(1), + M_AXI_awsize(2 downto 0) => s01_couplers_to_xbar_AWSIZE(2 downto 0), + M_AXI_awvalid => s01_couplers_to_xbar_AWVALID, + M_AXI_bready => s01_couplers_to_xbar_BREADY, + M_AXI_bresp(1 downto 0) => s01_couplers_to_xbar_BRESP(3 downto 2), + M_AXI_bvalid => s01_couplers_to_xbar_BVALID(1), + M_AXI_wdata(63 downto 0) => s01_couplers_to_xbar_WDATA(63 downto 0), + M_AXI_wlast => s01_couplers_to_xbar_WLAST, + M_AXI_wready => s01_couplers_to_xbar_WREADY(1), + M_AXI_wstrb(7 downto 0) => s01_couplers_to_xbar_WSTRB(7 downto 0), + M_AXI_wvalid => s01_couplers_to_xbar_WVALID, + S_ACLK => S01_ACLK_1, + S_ARESETN => S01_ARESETN_1, + S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s01_couplers_AWADDR(31 downto 0), + S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s01_couplers_AWBURST(1 downto 0), + S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s01_couplers_AWCACHE(3 downto 0), + S_AXI_awlen(7 downto 0) => axi_mem_intercon_to_s01_couplers_AWLEN(7 downto 0), + S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s01_couplers_AWPROT(2 downto 0), + S_AXI_awready => axi_mem_intercon_to_s01_couplers_AWREADY, + S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s01_couplers_AWSIZE(2 downto 0), + S_AXI_awvalid => axi_mem_intercon_to_s01_couplers_AWVALID, + S_AXI_bready => axi_mem_intercon_to_s01_couplers_BREADY, + S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s01_couplers_BRESP(1 downto 0), + S_AXI_bvalid => axi_mem_intercon_to_s01_couplers_BVALID, + S_AXI_wdata(63 downto 0) => axi_mem_intercon_to_s01_couplers_WDATA(63 downto 0), + S_AXI_wlast => axi_mem_intercon_to_s01_couplers_WLAST, + S_AXI_wready => axi_mem_intercon_to_s01_couplers_WREADY, + S_AXI_wstrb(7 downto 0) => axi_mem_intercon_to_s01_couplers_WSTRB(7 downto 0), + S_AXI_wvalid => axi_mem_intercon_to_s01_couplers_WVALID + ); +xbar: component Arty_Z7_20_xbar_1 + port map ( + aclk => axi_mem_intercon_ACLK_net, + aresetn => axi_mem_intercon_ARESETN_net, + m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0), + m_axi_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0), + m_axi_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0), + m_axi_arid(0) => xbar_to_m00_couplers_ARID(0), + m_axi_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0), + m_axi_arlock(0) => xbar_to_m00_couplers_ARLOCK(0), + m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0), + m_axi_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0), + m_axi_arready(0) => xbar_to_m00_couplers_ARREADY, + m_axi_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0), + m_axi_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0), + m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0), + m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0), + m_axi_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0), + m_axi_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0), + m_axi_awid(0) => xbar_to_m00_couplers_AWID(0), + m_axi_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0), + m_axi_awlock(0) => xbar_to_m00_couplers_AWLOCK(0), + m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0), + m_axi_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0), + m_axi_awready(0) => xbar_to_m00_couplers_AWREADY, + m_axi_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0), + m_axi_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0), + m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0), + m_axi_bid(0) => xbar_to_m00_couplers_BID(0), + m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0), + m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0), + m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID, + m_axi_rdata(63 downto 0) => xbar_to_m00_couplers_RDATA(63 downto 0), + m_axi_rid(0) => xbar_to_m00_couplers_RID(0), + m_axi_rlast(0) => xbar_to_m00_couplers_RLAST, + m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0), + m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0), + m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID, + m_axi_wdata(63 downto 0) => xbar_to_m00_couplers_WDATA(63 downto 0), + m_axi_wlast(0) => xbar_to_m00_couplers_WLAST(0), + m_axi_wready(0) => xbar_to_m00_couplers_WREADY, + m_axi_wstrb(7 downto 0) => xbar_to_m00_couplers_WSTRB(7 downto 0), + m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0), + s_axi_araddr(63 downto 32) => B"00000000000000000000000000000000", + s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0), + s_axi_arburst(3 downto 2) => B"00", + s_axi_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0), + s_axi_arcache(7 downto 4) => B"0000", + s_axi_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0), + s_axi_arid(1 downto 0) => B"00", + s_axi_arlen(15 downto 8) => B"00000000", + s_axi_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0), + s_axi_arlock(1) => '0', + s_axi_arlock(0) => s00_couplers_to_xbar_ARLOCK(0), + s_axi_arprot(5 downto 3) => B"000", + s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0), + s_axi_arqos(7 downto 4) => B"0000", + s_axi_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0), + s_axi_arready(1) => NLW_xbar_s_axi_arready_UNCONNECTED(1), + s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0), + s_axi_arsize(5 downto 3) => B"000", + s_axi_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0), + s_axi_arvalid(1) => '0', + s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID, + s_axi_awaddr(63 downto 32) => s01_couplers_to_xbar_AWADDR(31 downto 0), + s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", + s_axi_awburst(3 downto 2) => s01_couplers_to_xbar_AWBURST(1 downto 0), + s_axi_awburst(1 downto 0) => B"00", + s_axi_awcache(7 downto 4) => s01_couplers_to_xbar_AWCACHE(3 downto 0), + s_axi_awcache(3 downto 0) => B"0000", + s_axi_awid(1 downto 0) => B"00", + s_axi_awlen(15 downto 8) => s01_couplers_to_xbar_AWLEN(7 downto 0), + s_axi_awlen(7 downto 0) => B"00000000", + s_axi_awlock(1 downto 0) => B"00", + s_axi_awprot(5 downto 3) => s01_couplers_to_xbar_AWPROT(2 downto 0), + s_axi_awprot(2 downto 0) => B"000", + s_axi_awqos(7 downto 0) => B"00000000", + s_axi_awready(1) => s01_couplers_to_xbar_AWREADY(1), + s_axi_awready(0) => NLW_xbar_s_axi_awready_UNCONNECTED(0), + s_axi_awsize(5 downto 3) => s01_couplers_to_xbar_AWSIZE(2 downto 0), + s_axi_awsize(2 downto 0) => B"000", + s_axi_awvalid(1) => s01_couplers_to_xbar_AWVALID, + s_axi_awvalid(0) => '0', + s_axi_bid(1 downto 0) => NLW_xbar_s_axi_bid_UNCONNECTED(1 downto 0), + s_axi_bready(1) => s01_couplers_to_xbar_BREADY, + s_axi_bready(0) => '0', + s_axi_bresp(3 downto 2) => s01_couplers_to_xbar_BRESP(3 downto 2), + s_axi_bresp(1 downto 0) => NLW_xbar_s_axi_bresp_UNCONNECTED(1 downto 0), + s_axi_bvalid(1) => s01_couplers_to_xbar_BVALID(1), + s_axi_bvalid(0) => NLW_xbar_s_axi_bvalid_UNCONNECTED(0), + s_axi_rdata(127 downto 64) => NLW_xbar_s_axi_rdata_UNCONNECTED(127 downto 64), + s_axi_rdata(63 downto 0) => s00_couplers_to_xbar_RDATA(63 downto 0), + s_axi_rid(1 downto 0) => NLW_xbar_s_axi_rid_UNCONNECTED(1 downto 0), + s_axi_rlast(1) => NLW_xbar_s_axi_rlast_UNCONNECTED(1), + s_axi_rlast(0) => s00_couplers_to_xbar_RLAST(0), + s_axi_rready(1) => '0', + s_axi_rready(0) => s00_couplers_to_xbar_RREADY, + s_axi_rresp(3 downto 2) => NLW_xbar_s_axi_rresp_UNCONNECTED(3 downto 2), + s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0), + s_axi_rvalid(1) => NLW_xbar_s_axi_rvalid_UNCONNECTED(1), + s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0), + s_axi_wdata(127 downto 64) => s01_couplers_to_xbar_WDATA(63 downto 0), + s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + s_axi_wlast(1) => s01_couplers_to_xbar_WLAST, + s_axi_wlast(0) => '1', + s_axi_wready(1) => s01_couplers_to_xbar_WREADY(1), + s_axi_wready(0) => NLW_xbar_s_axi_wready_UNCONNECTED(0), + s_axi_wstrb(15 downto 8) => s01_couplers_to_xbar_WSTRB(7 downto 0), + s_axi_wstrb(7 downto 0) => B"11111111", + s_axi_wvalid(1) => s01_couplers_to_xbar_WVALID, + s_axi_wvalid(0) => '0' + ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; @@ -1920,6 +3076,44 @@ entity Arty_Z7_20_processing_system7_0_axi_periph_0 is M08_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 ); M08_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); M08_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + M09_ACLK : in STD_LOGIC; + M09_ARESETN : in STD_LOGIC; + M09_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M09_AXI_arready : in STD_LOGIC; + M09_AXI_arvalid : out STD_LOGIC; + M09_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M09_AXI_awready : in STD_LOGIC; + M09_AXI_awvalid : out STD_LOGIC; + M09_AXI_bready : out STD_LOGIC; + M09_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M09_AXI_bvalid : in STD_LOGIC; + M09_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M09_AXI_rready : out STD_LOGIC; + M09_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M09_AXI_rvalid : in STD_LOGIC; + M09_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M09_AXI_wready : in STD_LOGIC; + M09_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M09_AXI_wvalid : out STD_LOGIC; + M10_ACLK : in STD_LOGIC; + M10_ARESETN : in STD_LOGIC; + M10_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M10_AXI_arready : in STD_LOGIC; + M10_AXI_arvalid : out STD_LOGIC; + M10_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M10_AXI_awready : in STD_LOGIC; + M10_AXI_awvalid : out STD_LOGIC; + M10_AXI_bready : out STD_LOGIC; + M10_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M10_AXI_bvalid : in STD_LOGIC; + M10_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M10_AXI_rready : out STD_LOGIC; + M10_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M10_AXI_rvalid : in STD_LOGIC; + M10_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M10_AXI_wready : in STD_LOGIC; + M10_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M10_AXI_wvalid : out STD_LOGIC; S00_ACLK : in STD_LOGIC; S00_ARESETN : in STD_LOGIC; S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); @@ -1987,25 +3181,25 @@ architecture STRUCTURE of Arty_Z7_20_processing_system7_0_axi_periph_0 is s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_awaddr : out STD_LOGIC_VECTOR ( 287 downto 0 ); - m_axi_awprot : out STD_LOGIC_VECTOR ( 26 downto 0 ); - m_axi_awvalid : out STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_awready : in STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_wdata : out STD_LOGIC_VECTOR ( 287 downto 0 ); - m_axi_wstrb : out STD_LOGIC_VECTOR ( 35 downto 0 ); - m_axi_wvalid : out STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_wready : in STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_bresp : in STD_LOGIC_VECTOR ( 17 downto 0 ); - m_axi_bvalid : in STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_bready : out STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_araddr : out STD_LOGIC_VECTOR ( 287 downto 0 ); - m_axi_arprot : out STD_LOGIC_VECTOR ( 26 downto 0 ); - m_axi_arvalid : out STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_arready : in STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_rdata : in STD_LOGIC_VECTOR ( 287 downto 0 ); - m_axi_rresp : in STD_LOGIC_VECTOR ( 17 downto 0 ); - m_axi_rvalid : in STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_rready : out STD_LOGIC_VECTOR ( 8 downto 0 ) + m_axi_awaddr : out STD_LOGIC_VECTOR ( 351 downto 0 ); + m_axi_awprot : out STD_LOGIC_VECTOR ( 32 downto 0 ); + m_axi_awvalid : out STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_awready : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_wdata : out STD_LOGIC_VECTOR ( 351 downto 0 ); + m_axi_wstrb : out STD_LOGIC_VECTOR ( 43 downto 0 ); + m_axi_wvalid : out STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_wready : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_bresp : in STD_LOGIC_VECTOR ( 21 downto 0 ); + m_axi_bvalid : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_bready : out STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_araddr : out STD_LOGIC_VECTOR ( 351 downto 0 ); + m_axi_arprot : out STD_LOGIC_VECTOR ( 32 downto 0 ); + m_axi_arvalid : out STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_arready : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_rdata : in STD_LOGIC_VECTOR ( 351 downto 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 21 downto 0 ); + m_axi_rvalid : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_rready : out STD_LOGIC_VECTOR ( 10 downto 0 ) ); end component Arty_Z7_20_xbar_0; signal M00_ACLK_1 : STD_LOGIC; @@ -2026,6 +3220,10 @@ architecture STRUCTURE of Arty_Z7_20_processing_system7_0_axi_periph_0 is signal M07_ARESETN_1 : STD_LOGIC; signal M08_ACLK_1 : STD_LOGIC; signal M08_ARESETN_1 : STD_LOGIC; + signal M09_ACLK_1 : STD_LOGIC; + signal M09_ARESETN_1 : STD_LOGIC; + signal M10_ACLK_1 : STD_LOGIC; + signal M10_ARESETN_1 : STD_LOGIC; signal S00_ACLK_1 : STD_LOGIC; signal S00_ARESETN_1 : STD_LOGIC; signal m00_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); @@ -2182,6 +3380,40 @@ architecture STRUCTURE of Arty_Z7_20_processing_system7_0_axi_periph_0 is signal m08_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 ); signal m08_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal m08_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal m09_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m09_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC; + signal m09_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC; + signal m09_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m09_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC; + signal m09_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC; + signal m09_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC; + signal m09_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m09_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC; + signal m09_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m09_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC; + signal m09_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m09_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC; + signal m09_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m09_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC; + signal m09_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal m09_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC; + signal m10_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m10_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC; + signal m10_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC; + signal m10_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m10_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC; + signal m10_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC; + signal m10_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC; + signal m10_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m10_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC; + signal m10_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m10_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC; + signal m10_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m10_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC; + signal m10_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal m10_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC; + signal m10_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal m10_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC; signal processing_system7_0_axi_periph_ACLK_net : STD_LOGIC; signal processing_system7_0_axi_periph_ARESETN_net : STD_LOGIC; signal processing_system7_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); @@ -2395,8 +3627,42 @@ architecture STRUCTURE of Arty_Z7_20_processing_system7_0_axi_periph_0 is signal xbar_to_m08_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 ); signal xbar_to_m08_couplers_WSTRB : STD_LOGIC_VECTOR ( 35 downto 32 ); signal xbar_to_m08_couplers_WVALID : STD_LOGIC_VECTOR ( 8 to 8 ); - signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 26 downto 0 ); - signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 26 downto 0 ); + signal xbar_to_m09_couplers_ARADDR : STD_LOGIC_VECTOR ( 319 downto 288 ); + signal xbar_to_m09_couplers_ARREADY : STD_LOGIC; + signal xbar_to_m09_couplers_ARVALID : STD_LOGIC_VECTOR ( 9 to 9 ); + signal xbar_to_m09_couplers_AWADDR : STD_LOGIC_VECTOR ( 319 downto 288 ); + signal xbar_to_m09_couplers_AWREADY : STD_LOGIC; + signal xbar_to_m09_couplers_AWVALID : STD_LOGIC_VECTOR ( 9 to 9 ); + signal xbar_to_m09_couplers_BREADY : STD_LOGIC_VECTOR ( 9 to 9 ); + signal xbar_to_m09_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal xbar_to_m09_couplers_BVALID : STD_LOGIC; + signal xbar_to_m09_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal xbar_to_m09_couplers_RREADY : STD_LOGIC_VECTOR ( 9 to 9 ); + signal xbar_to_m09_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal xbar_to_m09_couplers_RVALID : STD_LOGIC; + signal xbar_to_m09_couplers_WDATA : STD_LOGIC_VECTOR ( 319 downto 288 ); + signal xbar_to_m09_couplers_WREADY : STD_LOGIC; + signal xbar_to_m09_couplers_WSTRB : STD_LOGIC_VECTOR ( 39 downto 36 ); + signal xbar_to_m09_couplers_WVALID : STD_LOGIC_VECTOR ( 9 to 9 ); + signal xbar_to_m10_couplers_ARADDR : STD_LOGIC_VECTOR ( 351 downto 320 ); + signal xbar_to_m10_couplers_ARREADY : STD_LOGIC; + signal xbar_to_m10_couplers_ARVALID : STD_LOGIC_VECTOR ( 10 to 10 ); + signal xbar_to_m10_couplers_AWADDR : STD_LOGIC_VECTOR ( 351 downto 320 ); + signal xbar_to_m10_couplers_AWREADY : STD_LOGIC; + signal xbar_to_m10_couplers_AWVALID : STD_LOGIC_VECTOR ( 10 to 10 ); + signal xbar_to_m10_couplers_BREADY : STD_LOGIC_VECTOR ( 10 to 10 ); + signal xbar_to_m10_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal xbar_to_m10_couplers_BVALID : STD_LOGIC; + signal xbar_to_m10_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal xbar_to_m10_couplers_RREADY : STD_LOGIC_VECTOR ( 10 to 10 ); + signal xbar_to_m10_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal xbar_to_m10_couplers_RVALID : STD_LOGIC; + signal xbar_to_m10_couplers_WDATA : STD_LOGIC_VECTOR ( 351 downto 320 ); + signal xbar_to_m10_couplers_WREADY : STD_LOGIC; + signal xbar_to_m10_couplers_WSTRB : STD_LOGIC_VECTOR ( 43 downto 40 ); + signal xbar_to_m10_couplers_WVALID : STD_LOGIC_VECTOR ( 10 to 10 ); + signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 32 downto 0 ); + signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 32 downto 0 ); signal NLW_xbar_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 12 ); begin M00_ACLK_1 <= M00_ACLK; @@ -2499,6 +3765,28 @@ begin M08_AXI_wdata(31 downto 0) <= m08_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0); M08_AXI_wstrb(3 downto 0) <= m08_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0); M08_AXI_wvalid(0) <= m08_couplers_to_processing_system7_0_axi_periph_WVALID(0); + M09_ACLK_1 <= M09_ACLK; + M09_ARESETN_1 <= M09_ARESETN; + M09_AXI_araddr(31 downto 0) <= m09_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0); + M09_AXI_arvalid <= m09_couplers_to_processing_system7_0_axi_periph_ARVALID; + M09_AXI_awaddr(31 downto 0) <= m09_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0); + M09_AXI_awvalid <= m09_couplers_to_processing_system7_0_axi_periph_AWVALID; + M09_AXI_bready <= m09_couplers_to_processing_system7_0_axi_periph_BREADY; + M09_AXI_rready <= m09_couplers_to_processing_system7_0_axi_periph_RREADY; + M09_AXI_wdata(31 downto 0) <= m09_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0); + M09_AXI_wstrb(3 downto 0) <= m09_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0); + M09_AXI_wvalid <= m09_couplers_to_processing_system7_0_axi_periph_WVALID; + M10_ACLK_1 <= M10_ACLK; + M10_ARESETN_1 <= M10_ARESETN; + M10_AXI_araddr(31 downto 0) <= m10_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0); + M10_AXI_arvalid <= m10_couplers_to_processing_system7_0_axi_periph_ARVALID; + M10_AXI_awaddr(31 downto 0) <= m10_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0); + M10_AXI_awvalid <= m10_couplers_to_processing_system7_0_axi_periph_AWVALID; + M10_AXI_bready <= m10_couplers_to_processing_system7_0_axi_periph_BREADY; + M10_AXI_rready <= m10_couplers_to_processing_system7_0_axi_periph_RREADY; + M10_AXI_wdata(31 downto 0) <= m10_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0); + M10_AXI_wstrb(3 downto 0) <= m10_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0); + M10_AXI_wvalid <= m10_couplers_to_processing_system7_0_axi_periph_WVALID; S00_ACLK_1 <= S00_ACLK; S00_ARESETN_1 <= S00_ARESETN; S00_AXI_arready <= processing_system7_0_axi_periph_to_s00_couplers_ARREADY; @@ -2584,6 +3872,22 @@ begin m08_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M08_AXI_rresp(1 downto 0); m08_couplers_to_processing_system7_0_axi_periph_RVALID(0) <= M08_AXI_rvalid(0); m08_couplers_to_processing_system7_0_axi_periph_WREADY(0) <= M08_AXI_wready(0); + m09_couplers_to_processing_system7_0_axi_periph_ARREADY <= M09_AXI_arready; + m09_couplers_to_processing_system7_0_axi_periph_AWREADY <= M09_AXI_awready; + m09_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M09_AXI_bresp(1 downto 0); + m09_couplers_to_processing_system7_0_axi_periph_BVALID <= M09_AXI_bvalid; + m09_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M09_AXI_rdata(31 downto 0); + m09_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M09_AXI_rresp(1 downto 0); + m09_couplers_to_processing_system7_0_axi_periph_RVALID <= M09_AXI_rvalid; + m09_couplers_to_processing_system7_0_axi_periph_WREADY <= M09_AXI_wready; + m10_couplers_to_processing_system7_0_axi_periph_ARREADY <= M10_AXI_arready; + m10_couplers_to_processing_system7_0_axi_periph_AWREADY <= M10_AXI_awready; + m10_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M10_AXI_bresp(1 downto 0); + m10_couplers_to_processing_system7_0_axi_periph_BVALID <= M10_AXI_bvalid; + m10_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M10_AXI_rdata(31 downto 0); + m10_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M10_AXI_rresp(1 downto 0); + m10_couplers_to_processing_system7_0_axi_periph_RVALID <= M10_AXI_rvalid; + m10_couplers_to_processing_system7_0_axi_periph_WREADY <= M10_AXI_wready; processing_system7_0_axi_periph_ACLK_net <= ACLK; processing_system7_0_axi_periph_ARESETN_net <= ARESETN; processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0); @@ -2984,6 +4288,88 @@ m08_couplers: entity work.m08_couplers_imp_1113B6V S_AXI_wstrb(3 downto 0) => xbar_to_m08_couplers_WSTRB(35 downto 32), S_AXI_wvalid(0) => xbar_to_m08_couplers_WVALID(8) ); +m09_couplers: entity work.m09_couplers_imp_1Q673FL + port map ( + M_ACLK => M09_ACLK_1, + M_ARESETN => M09_ARESETN_1, + M_AXI_araddr(31 downto 0) => m09_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0), + M_AXI_arready => m09_couplers_to_processing_system7_0_axi_periph_ARREADY, + M_AXI_arvalid => m09_couplers_to_processing_system7_0_axi_periph_ARVALID, + M_AXI_awaddr(31 downto 0) => m09_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0), + M_AXI_awready => m09_couplers_to_processing_system7_0_axi_periph_AWREADY, + M_AXI_awvalid => m09_couplers_to_processing_system7_0_axi_periph_AWVALID, + M_AXI_bready => m09_couplers_to_processing_system7_0_axi_periph_BREADY, + M_AXI_bresp(1 downto 0) => m09_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0), + M_AXI_bvalid => m09_couplers_to_processing_system7_0_axi_periph_BVALID, + M_AXI_rdata(31 downto 0) => m09_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0), + M_AXI_rready => m09_couplers_to_processing_system7_0_axi_periph_RREADY, + M_AXI_rresp(1 downto 0) => m09_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0), + M_AXI_rvalid => m09_couplers_to_processing_system7_0_axi_periph_RVALID, + M_AXI_wdata(31 downto 0) => m09_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0), + M_AXI_wready => m09_couplers_to_processing_system7_0_axi_periph_WREADY, + M_AXI_wstrb(3 downto 0) => m09_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0), + M_AXI_wvalid => m09_couplers_to_processing_system7_0_axi_periph_WVALID, + S_ACLK => processing_system7_0_axi_periph_ACLK_net, + S_ARESETN => processing_system7_0_axi_periph_ARESETN_net, + S_AXI_araddr(31 downto 0) => xbar_to_m09_couplers_ARADDR(319 downto 288), + S_AXI_arready => xbar_to_m09_couplers_ARREADY, + S_AXI_arvalid => xbar_to_m09_couplers_ARVALID(9), + S_AXI_awaddr(31 downto 0) => xbar_to_m09_couplers_AWADDR(319 downto 288), + S_AXI_awready => xbar_to_m09_couplers_AWREADY, + S_AXI_awvalid => xbar_to_m09_couplers_AWVALID(9), + S_AXI_bready => xbar_to_m09_couplers_BREADY(9), + S_AXI_bresp(1 downto 0) => xbar_to_m09_couplers_BRESP(1 downto 0), + S_AXI_bvalid => xbar_to_m09_couplers_BVALID, + S_AXI_rdata(31 downto 0) => xbar_to_m09_couplers_RDATA(31 downto 0), + S_AXI_rready => xbar_to_m09_couplers_RREADY(9), + S_AXI_rresp(1 downto 0) => xbar_to_m09_couplers_RRESP(1 downto 0), + S_AXI_rvalid => xbar_to_m09_couplers_RVALID, + S_AXI_wdata(31 downto 0) => xbar_to_m09_couplers_WDATA(319 downto 288), + S_AXI_wready => xbar_to_m09_couplers_WREADY, + S_AXI_wstrb(3 downto 0) => xbar_to_m09_couplers_WSTRB(39 downto 36), + S_AXI_wvalid => xbar_to_m09_couplers_WVALID(9) + ); +m10_couplers: entity work.m10_couplers_imp_11L1DU3 + port map ( + M_ACLK => M10_ACLK_1, + M_ARESETN => M10_ARESETN_1, + M_AXI_araddr(31 downto 0) => m10_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0), + M_AXI_arready => m10_couplers_to_processing_system7_0_axi_periph_ARREADY, + M_AXI_arvalid => m10_couplers_to_processing_system7_0_axi_periph_ARVALID, + M_AXI_awaddr(31 downto 0) => m10_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0), + M_AXI_awready => m10_couplers_to_processing_system7_0_axi_periph_AWREADY, + M_AXI_awvalid => m10_couplers_to_processing_system7_0_axi_periph_AWVALID, + M_AXI_bready => m10_couplers_to_processing_system7_0_axi_periph_BREADY, + M_AXI_bresp(1 downto 0) => m10_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0), + M_AXI_bvalid => m10_couplers_to_processing_system7_0_axi_periph_BVALID, + M_AXI_rdata(31 downto 0) => m10_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0), + M_AXI_rready => m10_couplers_to_processing_system7_0_axi_periph_RREADY, + M_AXI_rresp(1 downto 0) => m10_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0), + M_AXI_rvalid => m10_couplers_to_processing_system7_0_axi_periph_RVALID, + M_AXI_wdata(31 downto 0) => m10_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0), + M_AXI_wready => m10_couplers_to_processing_system7_0_axi_periph_WREADY, + M_AXI_wstrb(3 downto 0) => m10_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0), + M_AXI_wvalid => m10_couplers_to_processing_system7_0_axi_periph_WVALID, + S_ACLK => processing_system7_0_axi_periph_ACLK_net, + S_ARESETN => processing_system7_0_axi_periph_ARESETN_net, + S_AXI_araddr(31 downto 0) => xbar_to_m10_couplers_ARADDR(351 downto 320), + S_AXI_arready => xbar_to_m10_couplers_ARREADY, + S_AXI_arvalid => xbar_to_m10_couplers_ARVALID(10), + S_AXI_awaddr(31 downto 0) => xbar_to_m10_couplers_AWADDR(351 downto 320), + S_AXI_awready => xbar_to_m10_couplers_AWREADY, + S_AXI_awvalid => xbar_to_m10_couplers_AWVALID(10), + S_AXI_bready => xbar_to_m10_couplers_BREADY(10), + S_AXI_bresp(1 downto 0) => xbar_to_m10_couplers_BRESP(1 downto 0), + S_AXI_bvalid => xbar_to_m10_couplers_BVALID, + S_AXI_rdata(31 downto 0) => xbar_to_m10_couplers_RDATA(31 downto 0), + S_AXI_rready => xbar_to_m10_couplers_RREADY(10), + S_AXI_rresp(1 downto 0) => xbar_to_m10_couplers_RRESP(1 downto 0), + S_AXI_rvalid => xbar_to_m10_couplers_RVALID, + S_AXI_wdata(31 downto 0) => xbar_to_m10_couplers_WDATA(351 downto 320), + S_AXI_wready => xbar_to_m10_couplers_WREADY, + S_AXI_wstrb(3 downto 0) => xbar_to_m10_couplers_WSTRB(43 downto 40), + S_AXI_wvalid => xbar_to_m10_couplers_WVALID(10) + ); s00_couplers: entity work.s00_couplers_imp_Y3SZYS port map ( M_ACLK => processing_system7_0_axi_periph_ACLK_net, @@ -3052,6 +4438,8 @@ xbar: component Arty_Z7_20_xbar_0 port map ( aclk => processing_system7_0_axi_periph_ACLK_net, aresetn => processing_system7_0_axi_periph_ARESETN_net, + m_axi_araddr(351 downto 320) => xbar_to_m10_couplers_ARADDR(351 downto 320), + m_axi_araddr(319 downto 288) => xbar_to_m09_couplers_ARADDR(319 downto 288), m_axi_araddr(287 downto 256) => xbar_to_m08_couplers_ARADDR(287 downto 256), m_axi_araddr(255 downto 224) => xbar_to_m07_couplers_ARADDR(255 downto 224), m_axi_araddr(223 downto 192) => xbar_to_m06_couplers_ARADDR(223 downto 192), @@ -3061,9 +4449,11 @@ xbar: component Arty_Z7_20_xbar_0 m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64), m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32), m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0), - m_axi_arprot(26 downto 18) => NLW_xbar_m_axi_arprot_UNCONNECTED(26 downto 18), + m_axi_arprot(32 downto 18) => NLW_xbar_m_axi_arprot_UNCONNECTED(32 downto 18), m_axi_arprot(17 downto 15) => xbar_to_m05_couplers_ARPROT(17 downto 15), m_axi_arprot(14 downto 0) => NLW_xbar_m_axi_arprot_UNCONNECTED(14 downto 0), + m_axi_arready(10) => xbar_to_m10_couplers_ARREADY, + m_axi_arready(9) => xbar_to_m09_couplers_ARREADY, m_axi_arready(8) => xbar_to_m08_couplers_ARREADY(0), m_axi_arready(7) => xbar_to_m07_couplers_ARREADY, m_axi_arready(6) => xbar_to_m06_couplers_ARREADY(0), @@ -3073,6 +4463,8 @@ xbar: component Arty_Z7_20_xbar_0 m_axi_arready(2) => xbar_to_m02_couplers_ARREADY(0), m_axi_arready(1) => xbar_to_m01_couplers_ARREADY(0), m_axi_arready(0) => xbar_to_m00_couplers_ARREADY(0), + m_axi_arvalid(10) => xbar_to_m10_couplers_ARVALID(10), + m_axi_arvalid(9) => xbar_to_m09_couplers_ARVALID(9), m_axi_arvalid(8) => xbar_to_m08_couplers_ARVALID(8), m_axi_arvalid(7) => xbar_to_m07_couplers_ARVALID(7), m_axi_arvalid(6) => xbar_to_m06_couplers_ARVALID(6), @@ -3082,6 +4474,8 @@ xbar: component Arty_Z7_20_xbar_0 m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2), m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1), m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0), + m_axi_awaddr(351 downto 320) => xbar_to_m10_couplers_AWADDR(351 downto 320), + m_axi_awaddr(319 downto 288) => xbar_to_m09_couplers_AWADDR(319 downto 288), m_axi_awaddr(287 downto 256) => xbar_to_m08_couplers_AWADDR(287 downto 256), m_axi_awaddr(255 downto 224) => xbar_to_m07_couplers_AWADDR(255 downto 224), m_axi_awaddr(223 downto 192) => xbar_to_m06_couplers_AWADDR(223 downto 192), @@ -3091,9 +4485,11 @@ xbar: component Arty_Z7_20_xbar_0 m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64), m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32), m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0), - m_axi_awprot(26 downto 18) => NLW_xbar_m_axi_awprot_UNCONNECTED(26 downto 18), + m_axi_awprot(32 downto 18) => NLW_xbar_m_axi_awprot_UNCONNECTED(32 downto 18), m_axi_awprot(17 downto 15) => xbar_to_m05_couplers_AWPROT(17 downto 15), m_axi_awprot(14 downto 0) => NLW_xbar_m_axi_awprot_UNCONNECTED(14 downto 0), + m_axi_awready(10) => xbar_to_m10_couplers_AWREADY, + m_axi_awready(9) => xbar_to_m09_couplers_AWREADY, m_axi_awready(8) => xbar_to_m08_couplers_AWREADY(0), m_axi_awready(7) => xbar_to_m07_couplers_AWREADY, m_axi_awready(6) => xbar_to_m06_couplers_AWREADY(0), @@ -3103,6 +4499,8 @@ xbar: component Arty_Z7_20_xbar_0 m_axi_awready(2) => xbar_to_m02_couplers_AWREADY(0), m_axi_awready(1) => xbar_to_m01_couplers_AWREADY(0), m_axi_awready(0) => xbar_to_m00_couplers_AWREADY(0), + m_axi_awvalid(10) => xbar_to_m10_couplers_AWVALID(10), + m_axi_awvalid(9) => xbar_to_m09_couplers_AWVALID(9), m_axi_awvalid(8) => xbar_to_m08_couplers_AWVALID(8), m_axi_awvalid(7) => xbar_to_m07_couplers_AWVALID(7), m_axi_awvalid(6) => xbar_to_m06_couplers_AWVALID(6), @@ -3112,6 +4510,8 @@ xbar: component Arty_Z7_20_xbar_0 m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2), m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1), m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0), + m_axi_bready(10) => xbar_to_m10_couplers_BREADY(10), + m_axi_bready(9) => xbar_to_m09_couplers_BREADY(9), m_axi_bready(8) => xbar_to_m08_couplers_BREADY(8), m_axi_bready(7) => xbar_to_m07_couplers_BREADY(7), m_axi_bready(6) => xbar_to_m06_couplers_BREADY(6), @@ -3121,6 +4521,8 @@ xbar: component Arty_Z7_20_xbar_0 m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2), m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1), m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0), + m_axi_bresp(21 downto 20) => xbar_to_m10_couplers_BRESP(1 downto 0), + m_axi_bresp(19 downto 18) => xbar_to_m09_couplers_BRESP(1 downto 0), m_axi_bresp(17 downto 16) => xbar_to_m08_couplers_BRESP(1 downto 0), m_axi_bresp(15 downto 14) => xbar_to_m07_couplers_BRESP(1 downto 0), m_axi_bresp(13 downto 12) => xbar_to_m06_couplers_BRESP(1 downto 0), @@ -3130,6 +4532,8 @@ xbar: component Arty_Z7_20_xbar_0 m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0), m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0), m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0), + m_axi_bvalid(10) => xbar_to_m10_couplers_BVALID, + m_axi_bvalid(9) => xbar_to_m09_couplers_BVALID, m_axi_bvalid(8) => xbar_to_m08_couplers_BVALID(0), m_axi_bvalid(7) => xbar_to_m07_couplers_BVALID, m_axi_bvalid(6) => xbar_to_m06_couplers_BVALID(0), @@ -3139,6 +4543,8 @@ xbar: component Arty_Z7_20_xbar_0 m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID(0), m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID(0), m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID(0), + m_axi_rdata(351 downto 320) => xbar_to_m10_couplers_RDATA(31 downto 0), + m_axi_rdata(319 downto 288) => xbar_to_m09_couplers_RDATA(31 downto 0), m_axi_rdata(287 downto 256) => xbar_to_m08_couplers_RDATA(31 downto 0), m_axi_rdata(255 downto 224) => xbar_to_m07_couplers_RDATA(31 downto 0), m_axi_rdata(223 downto 192) => xbar_to_m06_couplers_RDATA(31 downto 0), @@ -3148,6 +4554,8 @@ xbar: component Arty_Z7_20_xbar_0 m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0), m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0), m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0), + m_axi_rready(10) => xbar_to_m10_couplers_RREADY(10), + m_axi_rready(9) => xbar_to_m09_couplers_RREADY(9), m_axi_rready(8) => xbar_to_m08_couplers_RREADY(8), m_axi_rready(7) => xbar_to_m07_couplers_RREADY(7), m_axi_rready(6) => xbar_to_m06_couplers_RREADY(6), @@ -3157,6 +4565,8 @@ xbar: component Arty_Z7_20_xbar_0 m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2), m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1), m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0), + m_axi_rresp(21 downto 20) => xbar_to_m10_couplers_RRESP(1 downto 0), + m_axi_rresp(19 downto 18) => xbar_to_m09_couplers_RRESP(1 downto 0), m_axi_rresp(17 downto 16) => xbar_to_m08_couplers_RRESP(1 downto 0), m_axi_rresp(15 downto 14) => xbar_to_m07_couplers_RRESP(1 downto 0), m_axi_rresp(13 downto 12) => xbar_to_m06_couplers_RRESP(1 downto 0), @@ -3166,6 +4576,8 @@ xbar: component Arty_Z7_20_xbar_0 m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0), m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0), m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0), + m_axi_rvalid(10) => xbar_to_m10_couplers_RVALID, + m_axi_rvalid(9) => xbar_to_m09_couplers_RVALID, m_axi_rvalid(8) => xbar_to_m08_couplers_RVALID(0), m_axi_rvalid(7) => xbar_to_m07_couplers_RVALID, m_axi_rvalid(6) => xbar_to_m06_couplers_RVALID(0), @@ -3175,6 +4587,8 @@ xbar: component Arty_Z7_20_xbar_0 m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID(0), m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID(0), m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID(0), + m_axi_wdata(351 downto 320) => xbar_to_m10_couplers_WDATA(351 downto 320), + m_axi_wdata(319 downto 288) => xbar_to_m09_couplers_WDATA(319 downto 288), m_axi_wdata(287 downto 256) => xbar_to_m08_couplers_WDATA(287 downto 256), m_axi_wdata(255 downto 224) => xbar_to_m07_couplers_WDATA(255 downto 224), m_axi_wdata(223 downto 192) => xbar_to_m06_couplers_WDATA(223 downto 192), @@ -3184,6 +4598,8 @@ xbar: component Arty_Z7_20_xbar_0 m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64), m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32), m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0), + m_axi_wready(10) => xbar_to_m10_couplers_WREADY, + m_axi_wready(9) => xbar_to_m09_couplers_WREADY, m_axi_wready(8) => xbar_to_m08_couplers_WREADY(0), m_axi_wready(7) => xbar_to_m07_couplers_WREADY, m_axi_wready(6) => xbar_to_m06_couplers_WREADY(0), @@ -3193,6 +4609,8 @@ xbar: component Arty_Z7_20_xbar_0 m_axi_wready(2) => xbar_to_m02_couplers_WREADY(0), m_axi_wready(1) => xbar_to_m01_couplers_WREADY(0), m_axi_wready(0) => xbar_to_m00_couplers_WREADY(0), + m_axi_wstrb(43 downto 40) => xbar_to_m10_couplers_WSTRB(43 downto 40), + m_axi_wstrb(39 downto 36) => xbar_to_m09_couplers_WSTRB(39 downto 36), m_axi_wstrb(35 downto 32) => xbar_to_m08_couplers_WSTRB(35 downto 32), m_axi_wstrb(31 downto 28) => xbar_to_m07_couplers_WSTRB(31 downto 28), m_axi_wstrb(27 downto 24) => xbar_to_m06_couplers_WSTRB(27 downto 24), @@ -3202,6 +4620,8 @@ xbar: component Arty_Z7_20_xbar_0 m_axi_wstrb(11 downto 8) => xbar_to_m02_couplers_WSTRB(11 downto 8), m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4), m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0), + m_axi_wvalid(10) => xbar_to_m10_couplers_WVALID(10), + m_axi_wvalid(9) => xbar_to_m09_couplers_WVALID(9), m_axi_wvalid(8) => xbar_to_m08_couplers_WVALID(8), m_axi_wvalid(7) => xbar_to_m07_couplers_WVALID(7), m_axi_wvalid(6) => xbar_to_m06_couplers_WVALID(6), @@ -3238,6 +4658,12 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20 is port ( + DDC_In_scl_i : in STD_LOGIC; + DDC_In_scl_o : out STD_LOGIC; + DDC_In_scl_t : out STD_LOGIC; + DDC_In_sda_i : in STD_LOGIC; + DDC_In_sda_o : out STD_LOGIC; + DDC_In_sda_t : out STD_LOGIC; DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_cas_n : inout STD_LOGIC; @@ -3269,6 +4695,10 @@ entity Arty_Z7_20 is RGBLED_tri_i : in STD_LOGIC_VECTOR ( 5 downto 0 ); RGBLED_tri_o : out STD_LOGIC_VECTOR ( 5 downto 0 ); RGBLED_tri_t : out STD_LOGIC_VECTOR ( 5 downto 0 ); + TMDS_In_clk_n : in STD_LOGIC; + TMDS_In_clk_p : in STD_LOGIC; + TMDS_In_data_n : in STD_LOGIC_VECTOR ( 2 downto 0 ); + TMDS_In_data_p : in STD_LOGIC_VECTOR ( 2 downto 0 ); TMDS_clk_n : out STD_LOGIC; TMDS_clk_p : out STD_LOGIC; TMDS_data_n : out STD_LOGIC_VECTOR ( 2 downto 0 ); @@ -3294,6 +4724,7 @@ entity Arty_Z7_20 is Vp_Vn_v_n : in STD_LOGIC; Vp_Vn_v_p : in STD_LOGIC; btns_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 ); + hdmi_in_hpd_tri_o : out STD_LOGIC_VECTOR ( 0 to 0 ); leds_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 ); leds_4bits_tri_o : out STD_LOGIC_VECTOR ( 3 downto 0 ); leds_4bits_tri_t : out STD_LOGIC_VECTOR ( 3 downto 0 ); @@ -3325,7 +4756,7 @@ entity Arty_Z7_20 is sys_clock : in STD_LOGIC ); attribute CORE_GENERATION_INFO : string; - attribute CORE_GENERATION_INFO of Arty_Z7_20 : entity is "Arty_Z7_20,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=Arty_Z7_20,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=40,numReposBlks=27,numNonXlnxBlks=2,numHierBlks=13,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}"; + attribute CORE_GENERATION_INFO of Arty_Z7_20 : entity is "Arty_Z7_20,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=Arty_Z7_20,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=52,numReposBlks=35,numNonXlnxBlks=3,numHierBlks=17,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=5,synth_mode=OOC_per_IP}"; attribute HW_HANDOFF : string; attribute HW_HANDOFF of Arty_Z7_20 : entity is "Arty_Z7_20.hwdef"; end Arty_Z7_20; @@ -3432,7 +4863,6 @@ architecture STRUCTURE of Arty_Z7_20 is s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; - ip2intc_irpt : out STD_LOGIC; gpio_io_i : in STD_LOGIC_VECTOR ( 13 downto 0 ); gpio_io_o : out STD_LOGIC_VECTOR ( 13 downto 0 ); gpio_io_t : out STD_LOGIC_VECTOR ( 13 downto 0 ) @@ -3459,7 +4889,6 @@ architecture STRUCTURE of Arty_Z7_20 is s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; - ip2intc_irpt : out STD_LOGIC; gpio_io_i : in STD_LOGIC_VECTOR ( 15 downto 0 ); gpio_io_o : out STD_LOGIC_VECTOR ( 15 downto 0 ); gpio_io_t : out STD_LOGIC_VECTOR ( 15 downto 0 ) @@ -3496,6 +4925,8 @@ architecture STRUCTURE of Arty_Z7_20 is s_axi_lite_aclk : in STD_LOGIC; m_axi_mm2s_aclk : in STD_LOGIC; m_axis_mm2s_aclk : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC; axi_resetn : in STD_LOGIC; s_axi_lite_awvalid : in STD_LOGIC; s_axi_lite_awready : out STD_LOGIC; @@ -3514,6 +4945,8 @@ architecture STRUCTURE of Arty_Z7_20 is s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); mm2s_frame_ptr_out : out STD_LOGIC_VECTOR ( 5 downto 0 ); + s2mm_frame_ptr_in : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s2mm_frame_ptr_out : out STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); @@ -3533,7 +4966,30 @@ architecture STRUCTURE of Arty_Z7_20 is m_axis_mm2s_tvalid : out STD_LOGIC; m_axis_mm2s_tready : in STD_LOGIC; m_axis_mm2s_tlast : out STD_LOGIC; - mm2s_introut : out STD_LOGIC + m_axi_s2mm_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_s2mm_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_s2mm_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_s2mm_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_s2mm_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_s2mm_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_s2mm_awvalid : out STD_LOGIC; + m_axi_s2mm_awready : in STD_LOGIC; + m_axi_s2mm_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_s2mm_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_s2mm_wlast : out STD_LOGIC; + m_axi_s2mm_wvalid : out STD_LOGIC; + m_axi_s2mm_wready : in STD_LOGIC; + m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_s2mm_bvalid : in STD_LOGIC; + m_axi_s2mm_bready : out STD_LOGIC; + s_axis_s2mm_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axis_s2mm_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axis_s2mm_tuser : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axis_s2mm_tvalid : in STD_LOGIC; + s_axis_s2mm_tready : out STD_LOGIC; + s_axis_s2mm_tlast : in STD_LOGIC; + mm2s_introut : out STD_LOGIC; + s2mm_introut : out STD_LOGIC ); end component Arty_Z7_20_axi_vdma_0_0; component Arty_Z7_20_axis_subset_converter_0_0 is @@ -3672,7 +5128,7 @@ architecture STRUCTURE of Arty_Z7_20 is S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); - IRQ_F2P : in STD_LOGIC_VECTOR ( 6 downto 0 ); + IRQ_F2P : in STD_LOGIC_VECTOR ( 7 downto 0 ); FCLK_CLK0 : out STD_LOGIC; FCLK_CLK1 : out STD_LOGIC; FCLK_CLK2 : out STD_LOGIC; @@ -3878,7 +5334,8 @@ architecture STRUCTURE of Arty_Z7_20 is In4 : in STD_LOGIC_VECTOR ( 0 to 0 ); In5 : in STD_LOGIC_VECTOR ( 0 to 0 ); In6 : in STD_LOGIC_VECTOR ( 0 to 0 ); - dout : out STD_LOGIC_VECTOR ( 6 downto 0 ) + In7 : in STD_LOGIC_VECTOR ( 0 to 0 ); + dout : out STD_LOGIC_VECTOR ( 7 downto 0 ) ); end component Arty_Z7_20_xlconcat_0_0; component Arty_Z7_20_xlconcat_1_0 is @@ -3923,8 +5380,10 @@ architecture STRUCTURE of Arty_Z7_20 is end component Arty_Z7_20_proc_sys_reset_0_1; component Arty_Z7_20_clk_wiz_0_0 is port ( + reset : in STD_LOGIC; clk_in1 : in STD_LOGIC; clk_out1 : out STD_LOGIC; + clk_out2 : out STD_LOGIC; locked : out STD_LOGIC ); end component Arty_Z7_20_clk_wiz_0_0; @@ -3942,6 +5401,171 @@ architecture STRUCTURE of Arty_Z7_20 is peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) ); end component Arty_Z7_20_proc_sys_reset_0_2; + component Arty_Z7_20_dvi2rgb_0_0 is + port ( + TMDS_Clk_p : in STD_LOGIC; + TMDS_Clk_n : in STD_LOGIC; + TMDS_Data_p : in STD_LOGIC_VECTOR ( 2 downto 0 ); + TMDS_Data_n : in STD_LOGIC_VECTOR ( 2 downto 0 ); + RefClk : in STD_LOGIC; + aRst_n : in STD_LOGIC; + vid_pData : out STD_LOGIC_VECTOR ( 23 downto 0 ); + vid_pVDE : out STD_LOGIC; + vid_pHSync : out STD_LOGIC; + vid_pVSync : out STD_LOGIC; + PixelClk : out STD_LOGIC; + aPixelClkLckd : out STD_LOGIC; + DDC_SDA_I : in STD_LOGIC; + DDC_SDA_O : out STD_LOGIC; + DDC_SDA_T : out STD_LOGIC; + DDC_SCL_I : in STD_LOGIC; + DDC_SCL_O : out STD_LOGIC; + DDC_SCL_T : out STD_LOGIC; + pRst_n : in STD_LOGIC + ); + end component Arty_Z7_20_dvi2rgb_0_0; + component Arty_Z7_20_v_vid_in_axi4s_0_0 is + port ( + vid_io_in_clk : in STD_LOGIC; + vid_io_in_ce : in STD_LOGIC; + vid_io_in_reset : in STD_LOGIC; + vid_active_video : in STD_LOGIC; + vid_vblank : in STD_LOGIC; + vid_hblank : in STD_LOGIC; + vid_vsync : in STD_LOGIC; + vid_hsync : in STD_LOGIC; + vid_field_id : in STD_LOGIC; + vid_data : in STD_LOGIC_VECTOR ( 23 downto 0 ); + aclk : in STD_LOGIC; + aclken : in STD_LOGIC; + aresetn : in STD_LOGIC; + m_axis_video_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 ); + m_axis_video_tvalid : out STD_LOGIC; + m_axis_video_tready : in STD_LOGIC; + m_axis_video_tuser : out STD_LOGIC; + m_axis_video_tlast : out STD_LOGIC; + fid : out STD_LOGIC; + vtd_active_video : out STD_LOGIC; + vtd_vblank : out STD_LOGIC; + vtd_hblank : out STD_LOGIC; + vtd_vsync : out STD_LOGIC; + vtd_hsync : out STD_LOGIC; + vtd_field_id : out STD_LOGIC; + overflow : out STD_LOGIC; + underflow : out STD_LOGIC; + axis_enable : in STD_LOGIC + ); + end component Arty_Z7_20_v_vid_in_axi4s_0_0; + component Arty_Z7_20_proc_sys_reset_0_3 is + port ( + slowest_sync_clk : in STD_LOGIC; + ext_reset_in : in STD_LOGIC; + aux_reset_in : in STD_LOGIC; + mb_debug_sys_rst : in STD_LOGIC; + dcm_locked : in STD_LOGIC; + mb_reset : out STD_LOGIC; + bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); + peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); + interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); + peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + end component Arty_Z7_20_proc_sys_reset_0_3; + component Arty_Z7_20_v_tc_1_0 is + port ( + clk : in STD_LOGIC; + clken : in STD_LOGIC; + s_axi_aclk : in STD_LOGIC; + s_axi_aclken : in STD_LOGIC; + det_clken : in STD_LOGIC; + intc_if : out STD_LOGIC_VECTOR ( 31 downto 0 ); + hsync_in : in STD_LOGIC; + vsync_in : in STD_LOGIC; + active_video_in : in STD_LOGIC; + resetn : in STD_LOGIC; + s_axi_aresetn : in STD_LOGIC; + s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_arvalid : in STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rvalid : out STD_LOGIC; + s_axi_rready : in STD_LOGIC; + irq : out STD_LOGIC + ); + end component Arty_Z7_20_v_tc_1_0; + component Arty_Z7_20_axi_gpio_0_0 is + port ( + s_axi_aclk : in STD_LOGIC; + s_axi_aresetn : in STD_LOGIC; + s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_arvalid : in STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rvalid : out STD_LOGIC; + s_axi_rready : in STD_LOGIC; + ip2intc_irpt : out STD_LOGIC; + gpio_io_o : out STD_LOGIC_VECTOR ( 0 to 0 ); + gpio2_io_i : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + end component Arty_Z7_20_axi_gpio_0_0; + component Arty_Z7_20_axis_subset_converter_0_1 is + port ( + aclk : in STD_LOGIC; + aresetn : in STD_LOGIC; + s_axis_tvalid : in STD_LOGIC; + s_axis_tready : out STD_LOGIC; + s_axis_tdata : in STD_LOGIC_VECTOR ( 23 downto 0 ); + s_axis_tlast : in STD_LOGIC; + s_axis_tuser : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axis_tvalid : out STD_LOGIC; + m_axis_tready : in STD_LOGIC; + m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axis_tlast : out STD_LOGIC; + m_axis_tuser : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + end component Arty_Z7_20_axis_subset_converter_0_1; + component Arty_Z7_20_v_rgb2ycrcb_0_0 is + port ( + aclk : in STD_LOGIC; + aclken : in STD_LOGIC; + aresetn : in STD_LOGIC; + s_axis_video_tdata : in STD_LOGIC_VECTOR ( 23 downto 0 ); + s_axis_video_tready : out STD_LOGIC; + s_axis_video_tvalid : in STD_LOGIC; + s_axis_video_tlast : in STD_LOGIC; + s_axis_video_tuser_sof : in STD_LOGIC; + m_axis_video_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 ); + m_axis_video_tvalid : out STD_LOGIC; + m_axis_video_tready : in STD_LOGIC; + m_axis_video_tlast : out STD_LOGIC; + m_axis_video_tuser_sof : out STD_LOGIC + ); + end component Arty_Z7_20_v_rgb2ycrcb_0_0; + signal TMDS_1_1_CLK_N : STD_LOGIC; + signal TMDS_1_1_CLK_P : STD_LOGIC; + signal TMDS_1_1_DATA_N : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal TMDS_1_1_DATA_P : STD_LOGIC_VECTOR ( 2 downto 0 ); signal Vaux0_1_V_N : STD_LOGIC; signal Vaux0_1_V_P : STD_LOGIC; signal Vaux12_1_V_N : STD_LOGIC; @@ -3976,14 +5600,15 @@ architecture STRUCTURE of Arty_Z7_20 is signal axi_gpio_2_GPIO_TRI_T : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_gpio_hdmi_GPIO_TRI_I : STD_LOGIC_VECTOR ( 0 to 0 ); signal axi_gpio_hdmi_ip2intc_irpt : STD_LOGIC; - signal axi_gpio_shield_1_ip2intc_irpt : STD_LOGIC; signal axi_gpio_shield_2_GPIO_TRI_I : STD_LOGIC_VECTOR ( 15 downto 0 ); signal axi_gpio_shield_2_GPIO_TRI_O : STD_LOGIC_VECTOR ( 15 downto 0 ); signal axi_gpio_shield_2_GPIO_TRI_T : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal axi_gpio_shield_2_ip2intc_irpt : STD_LOGIC; + signal axi_gpio_video_GPIO_TRI_O : STD_LOGIC_VECTOR ( 0 to 0 ); + signal axi_gpio_video_ip2intc_irpt : STD_LOGIC; signal axi_mem_intercon_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_mem_intercon_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_M00_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 ); signal axi_mem_intercon_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_mem_intercon_M00_AXI_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); @@ -3991,11 +5616,33 @@ architecture STRUCTURE of Arty_Z7_20 is signal axi_mem_intercon_M00_AXI_ARREADY : STD_LOGIC; signal axi_mem_intercon_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); signal axi_mem_intercon_M00_AXI_ARVALID : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal axi_mem_intercon_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWREADY : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_mem_intercon_M00_AXI_AWVALID : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_BID : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal axi_mem_intercon_M00_AXI_BREADY : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_mem_intercon_M00_AXI_BVALID : STD_LOGIC; signal axi_mem_intercon_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal axi_mem_intercon_M00_AXI_RID : STD_LOGIC_VECTOR ( 5 downto 0 ); signal axi_mem_intercon_M00_AXI_RLAST : STD_LOGIC; signal axi_mem_intercon_M00_AXI_RREADY : STD_LOGIC; signal axi_mem_intercon_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_mem_intercon_M00_AXI_RVALID : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal axi_mem_intercon_M00_AXI_WID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal axi_mem_intercon_M00_AXI_WLAST : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_WREADY : STD_LOGIC; + signal axi_mem_intercon_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal axi_mem_intercon_M00_AXI_WVALID : STD_LOGIC; signal axi_vdma_0_M_AXIS_MM2S_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); signal axi_vdma_0_M_AXIS_MM2S_TKEEP : STD_LOGIC_VECTOR ( 3 downto 0 ); signal axi_vdma_0_M_AXIS_MM2S_TLAST : STD_LOGIC; @@ -4015,14 +5662,51 @@ architecture STRUCTURE of Arty_Z7_20 is signal axi_vdma_0_M_AXI_MM2S_RREADY : STD_LOGIC; signal axi_vdma_0_M_AXI_MM2S_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_vdma_0_M_AXI_MM2S_RVALID : STD_LOGIC; + signal axi_vdma_0_M_AXI_S2MM_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal axi_vdma_0_M_AXI_S2MM_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_vdma_0_M_AXI_S2MM_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal axi_vdma_0_M_AXI_S2MM_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal axi_vdma_0_M_AXI_S2MM_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_vdma_0_M_AXI_S2MM_AWREADY : STD_LOGIC; + signal axi_vdma_0_M_AXI_S2MM_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal axi_vdma_0_M_AXI_S2MM_AWVALID : STD_LOGIC; + signal axi_vdma_0_M_AXI_S2MM_BREADY : STD_LOGIC; + signal axi_vdma_0_M_AXI_S2MM_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal axi_vdma_0_M_AXI_S2MM_BVALID : STD_LOGIC; + signal axi_vdma_0_M_AXI_S2MM_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal axi_vdma_0_M_AXI_S2MM_WLAST : STD_LOGIC; + signal axi_vdma_0_M_AXI_S2MM_WREADY : STD_LOGIC; + signal axi_vdma_0_M_AXI_S2MM_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal axi_vdma_0_M_AXI_S2MM_WVALID : STD_LOGIC; signal axi_vdma_0_mm2s_introut : STD_LOGIC; + signal axi_vdma_0_s2mm_introut : STD_LOGIC; signal axis_subset_converter_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 23 downto 0 ); signal axis_subset_converter_0_M_AXIS_TLAST : STD_LOGIC; signal axis_subset_converter_0_M_AXIS_TREADY : STD_LOGIC; signal axis_subset_converter_0_M_AXIS_TUSER : STD_LOGIC_VECTOR ( 0 to 0 ); signal axis_subset_converter_0_M_AXIS_TVALID : STD_LOGIC; + signal axis_subset_converter_1_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal axis_subset_converter_1_M_AXIS_TLAST : STD_LOGIC; + signal axis_subset_converter_1_M_AXIS_TREADY : STD_LOGIC; + signal axis_subset_converter_1_M_AXIS_TUSER : STD_LOGIC_VECTOR ( 0 to 0 ); + signal axis_subset_converter_1_M_AXIS_TVALID : STD_LOGIC; signal clk_wiz_0_clk_out1 : STD_LOGIC; + signal clk_wiz_0_clk_out2 : STD_LOGIC; signal clk_wiz_0_locked : STD_LOGIC; + signal dvi2rgb_0_DDC_SCL_I : STD_LOGIC; + signal dvi2rgb_0_DDC_SCL_O : STD_LOGIC; + signal dvi2rgb_0_DDC_SCL_T : STD_LOGIC; + signal dvi2rgb_0_DDC_SDA_I : STD_LOGIC; + signal dvi2rgb_0_DDC_SDA_O : STD_LOGIC; + signal dvi2rgb_0_DDC_SDA_T : STD_LOGIC; + signal dvi2rgb_0_PixelClk : STD_LOGIC; + signal dvi2rgb_0_RGB_ACTIVE_VIDEO : STD_LOGIC; + signal dvi2rgb_0_RGB_DATA : STD_LOGIC_VECTOR ( 23 downto 0 ); + signal dvi2rgb_0_RGB_HSYNC : STD_LOGIC; + signal dvi2rgb_0_RGB_VSYNC : STD_LOGIC; + signal dvi2rgb_0_aPixelClkLckd : STD_LOGIC; + signal proc_sys_reset_0_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 ); + signal proc_sys_reset_0_peripheral_reset : STD_LOGIC_VECTOR ( 0 to 0 ); signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 ); signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 ); signal processing_system7_0_DDR_CAS_N : STD_LOGIC; @@ -4270,6 +5954,40 @@ architecture STRUCTURE of Arty_Z7_20 is signal processing_system7_0_axi_periph_M08_AXI_WREADY : STD_LOGIC; signal processing_system7_0_axi_periph_M08_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_axi_periph_M08_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 ); + signal processing_system7_0_axi_periph_M09_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_axi_periph_M09_AXI_ARREADY : STD_LOGIC; + signal processing_system7_0_axi_periph_M09_AXI_ARVALID : STD_LOGIC; + signal processing_system7_0_axi_periph_M09_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_axi_periph_M09_AXI_AWREADY : STD_LOGIC; + signal processing_system7_0_axi_periph_M09_AXI_AWVALID : STD_LOGIC; + signal processing_system7_0_axi_periph_M09_AXI_BREADY : STD_LOGIC; + signal processing_system7_0_axi_periph_M09_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_axi_periph_M09_AXI_BVALID : STD_LOGIC; + signal processing_system7_0_axi_periph_M09_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_axi_periph_M09_AXI_RREADY : STD_LOGIC; + signal processing_system7_0_axi_periph_M09_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_axi_periph_M09_AXI_RVALID : STD_LOGIC; + signal processing_system7_0_axi_periph_M09_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_axi_periph_M09_AXI_WREADY : STD_LOGIC; + signal processing_system7_0_axi_periph_M09_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_axi_periph_M09_AXI_WVALID : STD_LOGIC; + signal processing_system7_0_axi_periph_M10_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_axi_periph_M10_AXI_ARREADY : STD_LOGIC; + signal processing_system7_0_axi_periph_M10_AXI_ARVALID : STD_LOGIC; + signal processing_system7_0_axi_periph_M10_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_axi_periph_M10_AXI_AWREADY : STD_LOGIC; + signal processing_system7_0_axi_periph_M10_AXI_AWVALID : STD_LOGIC; + signal processing_system7_0_axi_periph_M10_AXI_BREADY : STD_LOGIC; + signal processing_system7_0_axi_periph_M10_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_axi_periph_M10_AXI_BVALID : STD_LOGIC; + signal processing_system7_0_axi_periph_M10_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_axi_periph_M10_AXI_RREADY : STD_LOGIC; + signal processing_system7_0_axi_periph_M10_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal processing_system7_0_axi_periph_M10_AXI_RVALID : STD_LOGIC; + signal processing_system7_0_axi_periph_M10_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal processing_system7_0_axi_periph_M10_AXI_WREADY : STD_LOGIC; + signal processing_system7_0_axi_periph_M10_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal processing_system7_0_axi_periph_M10_AXI_WVALID : STD_LOGIC; signal rgb2dvi_0_TMDS_CLK_N : STD_LOGIC; signal rgb2dvi_0_TMDS_CLK_P : STD_LOGIC; signal rgb2dvi_0_TMDS_DATA_N : STD_LOGIC_VECTOR ( 2 downto 0 ); @@ -4284,17 +6002,35 @@ architecture STRUCTURE of Arty_Z7_20 is signal v_axi4s_vid_out_0_vid_io_out_HSYNC : STD_LOGIC; signal v_axi4s_vid_out_0_vid_io_out_VSYNC : STD_LOGIC; signal v_axi4s_vid_out_0_vtg_ce : STD_LOGIC; + signal v_rgb2ycrcb_0_video_out_TDATA : STD_LOGIC_VECTOR ( 23 downto 0 ); + signal v_rgb2ycrcb_0_video_out_TLAST : STD_LOGIC; + signal v_rgb2ycrcb_0_video_out_TREADY : STD_LOGIC; + signal v_rgb2ycrcb_0_video_out_TUSER : STD_LOGIC; + signal v_rgb2ycrcb_0_video_out_TVALID : STD_LOGIC; signal v_tc_0_irq : STD_LOGIC; signal v_tc_0_vtiming_out_ACTIVE_VIDEO : STD_LOGIC; signal v_tc_0_vtiming_out_HBLANK : STD_LOGIC; signal v_tc_0_vtiming_out_HSYNC : STD_LOGIC; signal v_tc_0_vtiming_out_VBLANK : STD_LOGIC; signal v_tc_0_vtiming_out_VSYNC : STD_LOGIC; + signal v_tc_1_irq : STD_LOGIC; + signal v_vid_in_axi4s_0_video_out_TDATA : STD_LOGIC_VECTOR ( 23 downto 0 ); + signal v_vid_in_axi4s_0_video_out_TLAST : STD_LOGIC; + signal v_vid_in_axi4s_0_video_out_TREADY : STD_LOGIC; + signal v_vid_in_axi4s_0_video_out_TUSER : STD_LOGIC; + signal v_vid_in_axi4s_0_video_out_TVALID : STD_LOGIC; + signal v_vid_in_axi4s_0_vtiming_out_ACTIVE_VIDEO : STD_LOGIC; + signal v_vid_in_axi4s_0_vtiming_out_HSYNC : STD_LOGIC; + signal v_vid_in_axi4s_0_vtiming_out_VSYNC : STD_LOGIC; signal xadc_wiz_0_ip2intc_irpt : STD_LOGIC; - signal xlconcat_0_dout : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal xlconcat_0_dout : STD_LOGIC_VECTOR ( 7 downto 0 ); signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_axi_vdma_0_mm2s_frame_ptr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_axi_vdma_0_s2mm_frame_ptr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_axis_subset_converter_0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_proc_sys_reset_0_mb_reset_UNCONNECTED : STD_LOGIC; + signal NLW_proc_sys_reset_0_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_proc_sys_reset_0_interconnect_aresetn_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_proc_sys_reset_2_mb_reset_UNCONNECTED : STD_LOGIC; signal NLW_proc_sys_reset_2_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_proc_sys_reset_2_interconnect_aresetn_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); @@ -4310,15 +6046,9 @@ architecture STRUCTURE of Arty_Z7_20 is signal NLW_proc_sys_reset_sysclk_interconnect_aresetn_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_proc_sys_reset_sysclk_peripheral_aresetn_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_proc_sys_reset_sysclk_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_processing_system7_0_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC; - signal NLW_processing_system7_0_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC; - signal NLW_processing_system7_0_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC; - signal NLW_processing_system7_0_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); - signal NLW_processing_system7_0_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal NLW_processing_system7_0_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); @@ -4336,6 +6066,13 @@ architecture STRUCTURE of Arty_Z7_20 is signal NLW_v_axi4s_vid_out_0_vid_vblank_UNCONNECTED : STD_LOGIC; signal NLW_v_axi4s_vid_out_0_status_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_v_tc_0_fsync_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_v_tc_1_intc_if_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_v_vid_in_axi4s_0_fid_UNCONNECTED : STD_LOGIC; + signal NLW_v_vid_in_axi4s_0_overflow_UNCONNECTED : STD_LOGIC; + signal NLW_v_vid_in_axi4s_0_underflow_UNCONNECTED : STD_LOGIC; + signal NLW_v_vid_in_axi4s_0_vtd_field_id_UNCONNECTED : STD_LOGIC; + signal NLW_v_vid_in_axi4s_0_vtd_hblank_UNCONNECTED : STD_LOGIC; + signal NLW_v_vid_in_axi4s_0_vtd_vblank_UNCONNECTED : STD_LOGIC; signal NLW_xadc_wiz_0_alarm_out_UNCONNECTED : STD_LOGIC; signal NLW_xadc_wiz_0_busy_out_UNCONNECTED : STD_LOGIC; signal NLW_xadc_wiz_0_eoc_out_UNCONNECTED : STD_LOGIC; @@ -4349,12 +6086,20 @@ architecture STRUCTURE of Arty_Z7_20 is signal NLW_xadc_wiz_0_channel_out_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_xlconcat_1_dout_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); begin + DDC_In_scl_o <= dvi2rgb_0_DDC_SCL_O; + DDC_In_scl_t <= dvi2rgb_0_DDC_SCL_T; + DDC_In_sda_o <= dvi2rgb_0_DDC_SDA_O; + DDC_In_sda_t <= dvi2rgb_0_DDC_SDA_T; HDMI_DDC_scl_o <= processing_system7_0_IIC_0_SCL_O; HDMI_DDC_scl_t <= processing_system7_0_IIC_0_SCL_T; HDMI_DDC_sda_o <= processing_system7_0_IIC_0_SDA_O; HDMI_DDC_sda_t <= processing_system7_0_IIC_0_SDA_T; RGBLED_tri_o(5 downto 0) <= processing_system7_0_GPIO_0_TRI_O(5 downto 0); RGBLED_tri_t(5 downto 0) <= processing_system7_0_GPIO_0_TRI_T(5 downto 0); + TMDS_1_1_CLK_N <= TMDS_In_clk_n; + TMDS_1_1_CLK_P <= TMDS_In_clk_p; + TMDS_1_1_DATA_N(2 downto 0) <= TMDS_In_data_n(2 downto 0); + TMDS_1_1_DATA_P(2 downto 0) <= TMDS_In_data_p(2 downto 0); TMDS_clk_n <= rgb2dvi_0_TMDS_CLK_N; TMDS_clk_p <= rgb2dvi_0_TMDS_CLK_P; TMDS_data_n(2 downto 0) <= rgb2dvi_0_TMDS_DATA_N(2 downto 0); @@ -4385,6 +6130,9 @@ begin axi_gpio_2_GPIO_TRI_I(3 downto 0) <= leds_4bits_tri_i(3 downto 0); axi_gpio_hdmi_GPIO_TRI_I(0) <= HDMI_HPD_tri_i(0); axi_gpio_shield_2_GPIO_TRI_I(15 downto 0) <= shield_dp26_dp41_tri_i(15 downto 0); + dvi2rgb_0_DDC_SCL_I <= DDC_In_scl_i; + dvi2rgb_0_DDC_SDA_I <= DDC_In_sda_i; + hdmi_in_hpd_tri_o(0) <= axi_gpio_video_GPIO_TRI_O(0); leds_4bits_tri_o(3 downto 0) <= axi_gpio_2_GPIO_TRI_O(3 downto 0); leds_4bits_tri_t(3 downto 0) <= axi_gpio_2_GPIO_TRI_T(3 downto 0); processing_system7_0_GPIO_0_TRI_I(5 downto 0) <= RGBLED_tri_i(5 downto 0); @@ -4495,7 +6243,6 @@ axi_gpio_shield_1: component Arty_Z7_20_axi_gpio_shield_1_0 gpio_io_i(13 downto 0) => axi_gpio_1_GPIO_TRI_I(13 downto 0), gpio_io_o(13 downto 0) => axi_gpio_1_GPIO_TRI_O(13 downto 0), gpio_io_t(13 downto 0) => axi_gpio_1_GPIO_TRI_T(13 downto 0), - ip2intc_irpt => axi_gpio_shield_1_ip2intc_irpt, s_axi_aclk => processing_system7_0_FCLK_CLK0, s_axi_araddr(8 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(8 downto 0), s_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0), @@ -4521,7 +6268,6 @@ axi_gpio_shield_2: component Arty_Z7_20_axi_gpio_shield_2_0 gpio_io_i(15 downto 0) => axi_gpio_shield_2_GPIO_TRI_I(15 downto 0), gpio_io_o(15 downto 0) => axi_gpio_shield_2_GPIO_TRI_O(15 downto 0), gpio_io_t(15 downto 0) => axi_gpio_shield_2_GPIO_TRI_T(15 downto 0), - ip2intc_irpt => axi_gpio_shield_2_ip2intc_irpt, s_axi_aclk => processing_system7_0_FCLK_CLK0, s_axi_araddr(8 downto 0) => processing_system7_0_axi_periph_M08_AXI_ARADDR(8 downto 0), s_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0), @@ -4567,6 +6313,31 @@ axi_gpio_sw: component Arty_Z7_20_axi_gpio_sw_0 s_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_WSTRB(3 downto 0), s_axi_wvalid => processing_system7_0_axi_periph_M00_AXI_WVALID(0) ); +axi_gpio_video: component Arty_Z7_20_axi_gpio_0_0 + port map ( + gpio2_io_i(0) => dvi2rgb_0_aPixelClkLckd, + gpio_io_o(0) => axi_gpio_video_GPIO_TRI_O(0), + ip2intc_irpt => axi_gpio_video_ip2intc_irpt, + s_axi_aclk => processing_system7_0_FCLK_CLK0, + s_axi_araddr(8 downto 0) => processing_system7_0_axi_periph_M10_AXI_ARADDR(8 downto 0), + s_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0), + s_axi_arready => processing_system7_0_axi_periph_M10_AXI_ARREADY, + s_axi_arvalid => processing_system7_0_axi_periph_M10_AXI_ARVALID, + s_axi_awaddr(8 downto 0) => processing_system7_0_axi_periph_M10_AXI_AWADDR(8 downto 0), + s_axi_awready => processing_system7_0_axi_periph_M10_AXI_AWREADY, + s_axi_awvalid => processing_system7_0_axi_periph_M10_AXI_AWVALID, + s_axi_bready => processing_system7_0_axi_periph_M10_AXI_BREADY, + s_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M10_AXI_BRESP(1 downto 0), + s_axi_bvalid => processing_system7_0_axi_periph_M10_AXI_BVALID, + s_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M10_AXI_RDATA(31 downto 0), + s_axi_rready => processing_system7_0_axi_periph_M10_AXI_RREADY, + s_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M10_AXI_RRESP(1 downto 0), + s_axi_rvalid => processing_system7_0_axi_periph_M10_AXI_RVALID, + s_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M10_AXI_WDATA(31 downto 0), + s_axi_wready => processing_system7_0_axi_periph_M10_AXI_WREADY, + s_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M10_AXI_WSTRB(3 downto 0), + s_axi_wvalid => processing_system7_0_axi_periph_M10_AXI_WVALID + ); axi_mem_intercon: entity work.Arty_Z7_20_axi_mem_intercon_0 port map ( ACLK => processing_system7_0_FCLK_CLK1, @@ -4576,6 +6347,7 @@ axi_mem_intercon: entity work.Arty_Z7_20_axi_mem_intercon_0 M00_AXI_araddr(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0), M00_AXI_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0), M00_AXI_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0), + M00_AXI_arid(0) => axi_mem_intercon_M00_AXI_ARID(0), M00_AXI_arlen(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0), M00_AXI_arlock(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0), M00_AXI_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0), @@ -4583,11 +6355,33 @@ axi_mem_intercon: entity work.Arty_Z7_20_axi_mem_intercon_0 M00_AXI_arready => axi_mem_intercon_M00_AXI_ARREADY, M00_AXI_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0), M00_AXI_arvalid => axi_mem_intercon_M00_AXI_ARVALID, + M00_AXI_awaddr(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0), + M00_AXI_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0), + M00_AXI_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0), + M00_AXI_awid(0) => axi_mem_intercon_M00_AXI_AWID(0), + M00_AXI_awlen(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0), + M00_AXI_awlock(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0), + M00_AXI_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0), + M00_AXI_awqos(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0), + M00_AXI_awready => axi_mem_intercon_M00_AXI_AWREADY, + M00_AXI_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0), + M00_AXI_awvalid => axi_mem_intercon_M00_AXI_AWVALID, + M00_AXI_bid(5 downto 0) => axi_mem_intercon_M00_AXI_BID(5 downto 0), + M00_AXI_bready => axi_mem_intercon_M00_AXI_BREADY, + M00_AXI_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0), + M00_AXI_bvalid => axi_mem_intercon_M00_AXI_BVALID, M00_AXI_rdata(63 downto 0) => axi_mem_intercon_M00_AXI_RDATA(63 downto 0), + M00_AXI_rid(5 downto 0) => axi_mem_intercon_M00_AXI_RID(5 downto 0), M00_AXI_rlast => axi_mem_intercon_M00_AXI_RLAST, M00_AXI_rready => axi_mem_intercon_M00_AXI_RREADY, M00_AXI_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0), M00_AXI_rvalid => axi_mem_intercon_M00_AXI_RVALID, + M00_AXI_wdata(63 downto 0) => axi_mem_intercon_M00_AXI_WDATA(63 downto 0), + M00_AXI_wid(0) => axi_mem_intercon_M00_AXI_WID(0), + M00_AXI_wlast => axi_mem_intercon_M00_AXI_WLAST, + M00_AXI_wready => axi_mem_intercon_M00_AXI_WREADY, + M00_AXI_wstrb(7 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(7 downto 0), + M00_AXI_wvalid => axi_mem_intercon_M00_AXI_WVALID, S00_ACLK => processing_system7_0_FCLK_CLK1, S00_ARESETN => rst_processing_system7_0_142M_peripheral_aresetn(0), S00_AXI_araddr(31 downto 0) => axi_vdma_0_M_AXI_MM2S_ARADDR(31 downto 0), @@ -4602,7 +6396,25 @@ axi_mem_intercon: entity work.Arty_Z7_20_axi_mem_intercon_0 S00_AXI_rlast => axi_vdma_0_M_AXI_MM2S_RLAST, S00_AXI_rready => axi_vdma_0_M_AXI_MM2S_RREADY, S00_AXI_rresp(1 downto 0) => axi_vdma_0_M_AXI_MM2S_RRESP(1 downto 0), - S00_AXI_rvalid => axi_vdma_0_M_AXI_MM2S_RVALID + S00_AXI_rvalid => axi_vdma_0_M_AXI_MM2S_RVALID, + S01_ACLK => processing_system7_0_FCLK_CLK1, + S01_ARESETN => rst_processing_system7_0_142M_peripheral_aresetn(0), + S01_AXI_awaddr(31 downto 0) => axi_vdma_0_M_AXI_S2MM_AWADDR(31 downto 0), + S01_AXI_awburst(1 downto 0) => axi_vdma_0_M_AXI_S2MM_AWBURST(1 downto 0), + S01_AXI_awcache(3 downto 0) => axi_vdma_0_M_AXI_S2MM_AWCACHE(3 downto 0), + S01_AXI_awlen(7 downto 0) => axi_vdma_0_M_AXI_S2MM_AWLEN(7 downto 0), + S01_AXI_awprot(2 downto 0) => axi_vdma_0_M_AXI_S2MM_AWPROT(2 downto 0), + S01_AXI_awready => axi_vdma_0_M_AXI_S2MM_AWREADY, + S01_AXI_awsize(2 downto 0) => axi_vdma_0_M_AXI_S2MM_AWSIZE(2 downto 0), + S01_AXI_awvalid => axi_vdma_0_M_AXI_S2MM_AWVALID, + S01_AXI_bready => axi_vdma_0_M_AXI_S2MM_BREADY, + S01_AXI_bresp(1 downto 0) => axi_vdma_0_M_AXI_S2MM_BRESP(1 downto 0), + S01_AXI_bvalid => axi_vdma_0_M_AXI_S2MM_BVALID, + S01_AXI_wdata(63 downto 0) => axi_vdma_0_M_AXI_S2MM_WDATA(63 downto 0), + S01_AXI_wlast => axi_vdma_0_M_AXI_S2MM_WLAST, + S01_AXI_wready => axi_vdma_0_M_AXI_S2MM_WREADY, + S01_AXI_wstrb(7 downto 0) => axi_vdma_0_M_AXI_S2MM_WSTRB(7 downto 0), + S01_AXI_wvalid => axi_vdma_0_M_AXI_S2MM_WVALID ); axi_vdma_0: component Arty_Z7_20_axi_vdma_0_0 port map ( @@ -4621,6 +6433,23 @@ axi_vdma_0: component Arty_Z7_20_axi_vdma_0_0 m_axi_mm2s_rready => axi_vdma_0_M_AXI_MM2S_RREADY, m_axi_mm2s_rresp(1 downto 0) => axi_vdma_0_M_AXI_MM2S_RRESP(1 downto 0), m_axi_mm2s_rvalid => axi_vdma_0_M_AXI_MM2S_RVALID, + m_axi_s2mm_aclk => processing_system7_0_FCLK_CLK1, + m_axi_s2mm_awaddr(31 downto 0) => axi_vdma_0_M_AXI_S2MM_AWADDR(31 downto 0), + m_axi_s2mm_awburst(1 downto 0) => axi_vdma_0_M_AXI_S2MM_AWBURST(1 downto 0), + m_axi_s2mm_awcache(3 downto 0) => axi_vdma_0_M_AXI_S2MM_AWCACHE(3 downto 0), + m_axi_s2mm_awlen(7 downto 0) => axi_vdma_0_M_AXI_S2MM_AWLEN(7 downto 0), + m_axi_s2mm_awprot(2 downto 0) => axi_vdma_0_M_AXI_S2MM_AWPROT(2 downto 0), + m_axi_s2mm_awready => axi_vdma_0_M_AXI_S2MM_AWREADY, + m_axi_s2mm_awsize(2 downto 0) => axi_vdma_0_M_AXI_S2MM_AWSIZE(2 downto 0), + m_axi_s2mm_awvalid => axi_vdma_0_M_AXI_S2MM_AWVALID, + m_axi_s2mm_bready => axi_vdma_0_M_AXI_S2MM_BREADY, + m_axi_s2mm_bresp(1 downto 0) => axi_vdma_0_M_AXI_S2MM_BRESP(1 downto 0), + m_axi_s2mm_bvalid => axi_vdma_0_M_AXI_S2MM_BVALID, + m_axi_s2mm_wdata(63 downto 0) => axi_vdma_0_M_AXI_S2MM_WDATA(63 downto 0), + m_axi_s2mm_wlast => axi_vdma_0_M_AXI_S2MM_WLAST, + m_axi_s2mm_wready => axi_vdma_0_M_AXI_S2MM_WREADY, + m_axi_s2mm_wstrb(7 downto 0) => axi_vdma_0_M_AXI_S2MM_WSTRB(7 downto 0), + m_axi_s2mm_wvalid => axi_vdma_0_M_AXI_S2MM_WVALID, m_axis_mm2s_aclk => processing_system7_0_FCLK_CLK1, m_axis_mm2s_tdata(31 downto 0) => axi_vdma_0_M_AXIS_MM2S_TDATA(31 downto 0), m_axis_mm2s_tkeep(3 downto 0) => axi_vdma_0_M_AXIS_MM2S_TKEEP(3 downto 0), @@ -4630,6 +6459,9 @@ axi_vdma_0: component Arty_Z7_20_axi_vdma_0_0 m_axis_mm2s_tvalid => axi_vdma_0_M_AXIS_MM2S_TVALID, mm2s_frame_ptr_out(5 downto 0) => NLW_axi_vdma_0_mm2s_frame_ptr_out_UNCONNECTED(5 downto 0), mm2s_introut => axi_vdma_0_mm2s_introut, + s2mm_frame_ptr_in(5 downto 0) => B"000000", + s2mm_frame_ptr_out(5 downto 0) => NLW_axi_vdma_0_s2mm_frame_ptr_out_UNCONNECTED(5 downto 0), + s2mm_introut => axi_vdma_0_s2mm_introut, s_axi_lite_aclk => processing_system7_0_FCLK_CLK0, s_axi_lite_araddr(8 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARADDR(8 downto 0), s_axi_lite_arready => processing_system7_0_axi_periph_M03_AXI_ARREADY, @@ -4646,7 +6478,14 @@ axi_vdma_0: component Arty_Z7_20_axi_vdma_0_0 s_axi_lite_rvalid => processing_system7_0_axi_periph_M03_AXI_RVALID, s_axi_lite_wdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_WDATA(31 downto 0), s_axi_lite_wready => processing_system7_0_axi_periph_M03_AXI_WREADY, - s_axi_lite_wvalid => processing_system7_0_axi_periph_M03_AXI_WVALID(0) + s_axi_lite_wvalid => processing_system7_0_axi_periph_M03_AXI_WVALID(0), + s_axis_s2mm_aclk => processing_system7_0_FCLK_CLK1, + s_axis_s2mm_tdata(7 downto 0) => axis_subset_converter_1_M_AXIS_TDATA(7 downto 0), + s_axis_s2mm_tkeep(0) => '1', + s_axis_s2mm_tlast => axis_subset_converter_1_M_AXIS_TLAST, + s_axis_s2mm_tready => axis_subset_converter_1_M_AXIS_TREADY, + s_axis_s2mm_tuser(0) => axis_subset_converter_1_M_AXIS_TUSER(0), + s_axis_s2mm_tvalid => axis_subset_converter_1_M_AXIS_TVALID ); axis_subset_converter_0: component Arty_Z7_20_axis_subset_converter_0_0 port map ( @@ -4665,11 +6504,63 @@ axis_subset_converter_0: component Arty_Z7_20_axis_subset_converter_0_0 s_axis_tuser(0) => axi_vdma_0_M_AXIS_MM2S_TUSER(0), s_axis_tvalid => axi_vdma_0_M_AXIS_MM2S_TVALID ); +axis_subset_converter_1: component Arty_Z7_20_axis_subset_converter_0_1 + port map ( + aclk => processing_system7_0_FCLK_CLK1, + aresetn => xlconstant_0_dout(0), + m_axis_tdata(7 downto 0) => axis_subset_converter_1_M_AXIS_TDATA(7 downto 0), + m_axis_tlast => axis_subset_converter_1_M_AXIS_TLAST, + m_axis_tready => axis_subset_converter_1_M_AXIS_TREADY, + m_axis_tuser(0) => axis_subset_converter_1_M_AXIS_TUSER(0), + m_axis_tvalid => axis_subset_converter_1_M_AXIS_TVALID, + s_axis_tdata(23 downto 0) => v_rgb2ycrcb_0_video_out_TDATA(23 downto 0), + s_axis_tlast => v_rgb2ycrcb_0_video_out_TLAST, + s_axis_tready => v_rgb2ycrcb_0_video_out_TREADY, + s_axis_tuser(0) => v_rgb2ycrcb_0_video_out_TUSER, + s_axis_tvalid => v_rgb2ycrcb_0_video_out_TVALID + ); clk_wiz_0: component Arty_Z7_20_clk_wiz_0_0 port map ( clk_in1 => sys_clock_1, clk_out1 => clk_wiz_0_clk_out1, - locked => clk_wiz_0_locked + clk_out2 => clk_wiz_0_clk_out2, + locked => clk_wiz_0_locked, + reset => '0' + ); +dvi2rgb_0: component Arty_Z7_20_dvi2rgb_0_0 + port map ( + DDC_SCL_I => dvi2rgb_0_DDC_SCL_I, + DDC_SCL_O => dvi2rgb_0_DDC_SCL_O, + DDC_SCL_T => dvi2rgb_0_DDC_SCL_T, + DDC_SDA_I => dvi2rgb_0_DDC_SDA_I, + DDC_SDA_O => dvi2rgb_0_DDC_SDA_O, + DDC_SDA_T => dvi2rgb_0_DDC_SDA_T, + PixelClk => dvi2rgb_0_PixelClk, + RefClk => clk_wiz_0_clk_out2, + TMDS_Clk_n => TMDS_1_1_CLK_N, + TMDS_Clk_p => TMDS_1_1_CLK_P, + TMDS_Data_n(2 downto 0) => TMDS_1_1_DATA_N(2 downto 0), + TMDS_Data_p(2 downto 0) => TMDS_1_1_DATA_P(2 downto 0), + aPixelClkLckd => dvi2rgb_0_aPixelClkLckd, + aRst_n => rst_processing_system7_0_100M_peripheral_aresetn(0), + pRst_n => '1', + vid_pData(23 downto 0) => dvi2rgb_0_RGB_DATA(23 downto 0), + vid_pHSync => dvi2rgb_0_RGB_HSYNC, + vid_pVDE => dvi2rgb_0_RGB_ACTIVE_VIDEO, + vid_pVSync => dvi2rgb_0_RGB_VSYNC + ); +proc_sys_reset_0: component Arty_Z7_20_proc_sys_reset_0_3 + port map ( + aux_reset_in => dvi2rgb_0_aPixelClkLckd, + bus_struct_reset(0) => NLW_proc_sys_reset_0_bus_struct_reset_UNCONNECTED(0), + dcm_locked => '1', + ext_reset_in => processing_system7_0_FCLK_RESET0_N, + interconnect_aresetn(0) => NLW_proc_sys_reset_0_interconnect_aresetn_UNCONNECTED(0), + mb_debug_sys_rst => '0', + mb_reset => NLW_proc_sys_reset_0_mb_reset_UNCONNECTED, + peripheral_aresetn(0) => proc_sys_reset_0_peripheral_aresetn(0), + peripheral_reset(0) => proc_sys_reset_0_peripheral_reset(0), + slowest_sync_clk => dvi2rgb_0_PixelClk ); proc_sys_reset_2: component Arty_Z7_20_proc_sys_reset_0_0 port map ( @@ -4749,7 +6640,7 @@ processing_system7_0: component Arty_Z7_20_processing_system7_0_0 I2C1_SDA_I => processing_system7_0_IIC_1_SDA_I, I2C1_SDA_O => processing_system7_0_IIC_1_SDA_O, I2C1_SDA_T => processing_system7_0_IIC_1_SDA_T, - IRQ_F2P(6 downto 0) => xlconcat_0_dout(6 downto 0), + IRQ_F2P(7 downto 0) => xlconcat_0_dout(7 downto 0), MIO(53 downto 0) => FIXED_IO_mio(53 downto 0), M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0, M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0), @@ -4811,7 +6702,8 @@ processing_system7_0: component Arty_Z7_20_processing_system7_0_0 S_AXI_HP0_ARADDR(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0), S_AXI_HP0_ARBURST(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0), S_AXI_HP0_ARCACHE(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0), - S_AXI_HP0_ARID(5 downto 0) => B"000000", + S_AXI_HP0_ARID(5 downto 1) => B"00000", + S_AXI_HP0_ARID(0) => axi_mem_intercon_M00_AXI_ARID(0), S_AXI_HP0_ARLEN(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0), S_AXI_HP0_ARLOCK(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0), S_AXI_HP0_ARPROT(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0), @@ -4819,39 +6711,41 @@ processing_system7_0: component Arty_Z7_20_processing_system7_0_0 S_AXI_HP0_ARREADY => axi_mem_intercon_M00_AXI_ARREADY, S_AXI_HP0_ARSIZE(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0), S_AXI_HP0_ARVALID => axi_mem_intercon_M00_AXI_ARVALID, - S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000", - S_AXI_HP0_AWBURST(1 downto 0) => B"00", - S_AXI_HP0_AWCACHE(3 downto 0) => B"0000", - S_AXI_HP0_AWID(5 downto 0) => B"000000", - S_AXI_HP0_AWLEN(3 downto 0) => B"0000", - S_AXI_HP0_AWLOCK(1 downto 0) => B"00", - S_AXI_HP0_AWPROT(2 downto 0) => B"000", - S_AXI_HP0_AWQOS(3 downto 0) => B"0000", - S_AXI_HP0_AWREADY => NLW_processing_system7_0_S_AXI_HP0_AWREADY_UNCONNECTED, - S_AXI_HP0_AWSIZE(2 downto 0) => B"000", - S_AXI_HP0_AWVALID => '0', - S_AXI_HP0_BID(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_BID_UNCONNECTED(5 downto 0), - S_AXI_HP0_BREADY => '0', - S_AXI_HP0_BRESP(1 downto 0) => NLW_processing_system7_0_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0), - S_AXI_HP0_BVALID => NLW_processing_system7_0_S_AXI_HP0_BVALID_UNCONNECTED, + S_AXI_HP0_AWADDR(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0), + S_AXI_HP0_AWBURST(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0), + S_AXI_HP0_AWCACHE(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0), + S_AXI_HP0_AWID(5 downto 1) => B"00000", + S_AXI_HP0_AWID(0) => axi_mem_intercon_M00_AXI_AWID(0), + S_AXI_HP0_AWLEN(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0), + S_AXI_HP0_AWLOCK(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0), + S_AXI_HP0_AWPROT(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0), + S_AXI_HP0_AWQOS(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0), + S_AXI_HP0_AWREADY => axi_mem_intercon_M00_AXI_AWREADY, + S_AXI_HP0_AWSIZE(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0), + S_AXI_HP0_AWVALID => axi_mem_intercon_M00_AXI_AWVALID, + S_AXI_HP0_BID(5 downto 0) => axi_mem_intercon_M00_AXI_BID(5 downto 0), + S_AXI_HP0_BREADY => axi_mem_intercon_M00_AXI_BREADY, + S_AXI_HP0_BRESP(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0), + S_AXI_HP0_BVALID => axi_mem_intercon_M00_AXI_BVALID, S_AXI_HP0_RACOUNT(2 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP0_RCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP0_RDATA(63 downto 0) => axi_mem_intercon_M00_AXI_RDATA(63 downto 0), S_AXI_HP0_RDISSUECAP1_EN => '0', - S_AXI_HP0_RID(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RID_UNCONNECTED(5 downto 0), + S_AXI_HP0_RID(5 downto 0) => axi_mem_intercon_M00_AXI_RID(5 downto 0), S_AXI_HP0_RLAST => axi_mem_intercon_M00_AXI_RLAST, S_AXI_HP0_RREADY => axi_mem_intercon_M00_AXI_RREADY, S_AXI_HP0_RRESP(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0), S_AXI_HP0_RVALID => axi_mem_intercon_M00_AXI_RVALID, S_AXI_HP0_WACOUNT(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP0_WCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0), - S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", - S_AXI_HP0_WID(5 downto 0) => B"000000", - S_AXI_HP0_WLAST => '0', - S_AXI_HP0_WREADY => NLW_processing_system7_0_S_AXI_HP0_WREADY_UNCONNECTED, + S_AXI_HP0_WDATA(63 downto 0) => axi_mem_intercon_M00_AXI_WDATA(63 downto 0), + S_AXI_HP0_WID(5 downto 1) => B"00000", + S_AXI_HP0_WID(0) => axi_mem_intercon_M00_AXI_WID(0), + S_AXI_HP0_WLAST => axi_mem_intercon_M00_AXI_WLAST, + S_AXI_HP0_WREADY => axi_mem_intercon_M00_AXI_WREADY, S_AXI_HP0_WRISSUECAP1_EN => '0', - S_AXI_HP0_WSTRB(7 downto 0) => B"00000000", - S_AXI_HP0_WVALID => '0', + S_AXI_HP0_WSTRB(7 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(7 downto 0), + S_AXI_HP0_WVALID => axi_mem_intercon_M00_AXI_WVALID, USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0), USB0_VBUS_PWRFAULT => '0', USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED @@ -5032,6 +6926,44 @@ processing_system7_0_axi_periph: entity work.Arty_Z7_20_processing_system7_0_axi M08_AXI_wready(0) => processing_system7_0_axi_periph_M08_AXI_WREADY, M08_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M08_AXI_WSTRB(3 downto 0), M08_AXI_wvalid(0) => processing_system7_0_axi_periph_M08_AXI_WVALID(0), + M09_ACLK => processing_system7_0_FCLK_CLK0, + M09_ARESETN => rst_processing_system7_0_100M_peripheral_aresetn(0), + M09_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M09_AXI_ARADDR(31 downto 0), + M09_AXI_arready => processing_system7_0_axi_periph_M09_AXI_ARREADY, + M09_AXI_arvalid => processing_system7_0_axi_periph_M09_AXI_ARVALID, + M09_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M09_AXI_AWADDR(31 downto 0), + M09_AXI_awready => processing_system7_0_axi_periph_M09_AXI_AWREADY, + M09_AXI_awvalid => processing_system7_0_axi_periph_M09_AXI_AWVALID, + M09_AXI_bready => processing_system7_0_axi_periph_M09_AXI_BREADY, + M09_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M09_AXI_BRESP(1 downto 0), + M09_AXI_bvalid => processing_system7_0_axi_periph_M09_AXI_BVALID, + M09_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M09_AXI_RDATA(31 downto 0), + M09_AXI_rready => processing_system7_0_axi_periph_M09_AXI_RREADY, + M09_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M09_AXI_RRESP(1 downto 0), + M09_AXI_rvalid => processing_system7_0_axi_periph_M09_AXI_RVALID, + M09_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M09_AXI_WDATA(31 downto 0), + M09_AXI_wready => processing_system7_0_axi_periph_M09_AXI_WREADY, + M09_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M09_AXI_WSTRB(3 downto 0), + M09_AXI_wvalid => processing_system7_0_axi_periph_M09_AXI_WVALID, + M10_ACLK => processing_system7_0_FCLK_CLK0, + M10_ARESETN => rst_processing_system7_0_100M_peripheral_aresetn(0), + M10_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M10_AXI_ARADDR(31 downto 0), + M10_AXI_arready => processing_system7_0_axi_periph_M10_AXI_ARREADY, + M10_AXI_arvalid => processing_system7_0_axi_periph_M10_AXI_ARVALID, + M10_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M10_AXI_AWADDR(31 downto 0), + M10_AXI_awready => processing_system7_0_axi_periph_M10_AXI_AWREADY, + M10_AXI_awvalid => processing_system7_0_axi_periph_M10_AXI_AWVALID, + M10_AXI_bready => processing_system7_0_axi_periph_M10_AXI_BREADY, + M10_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M10_AXI_BRESP(1 downto 0), + M10_AXI_bvalid => processing_system7_0_axi_periph_M10_AXI_BVALID, + M10_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M10_AXI_RDATA(31 downto 0), + M10_AXI_rready => processing_system7_0_axi_periph_M10_AXI_RREADY, + M10_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M10_AXI_RRESP(1 downto 0), + M10_AXI_rvalid => processing_system7_0_axi_periph_M10_AXI_RVALID, + M10_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M10_AXI_WDATA(31 downto 0), + M10_AXI_wready => processing_system7_0_axi_periph_M10_AXI_WREADY, + M10_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M10_AXI_WSTRB(3 downto 0), + M10_AXI_wvalid => processing_system7_0_axi_periph_M10_AXI_WVALID, S00_ACLK => processing_system7_0_FCLK_CLK0, S00_ARESETN => rst_processing_system7_0_100M_peripheral_aresetn(0), S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0), @@ -5146,6 +7078,22 @@ v_axi4s_vid_out_0: component Arty_Z7_20_v_axi4s_vid_out_0_0 vtg_vblank => v_tc_0_vtiming_out_VBLANK, vtg_vsync => v_tc_0_vtiming_out_VSYNC ); +v_rgb2ycrcb_0: component Arty_Z7_20_v_rgb2ycrcb_0_0 + port map ( + aclk => processing_system7_0_FCLK_CLK1, + aclken => '1', + aresetn => '1', + m_axis_video_tdata(23 downto 0) => v_rgb2ycrcb_0_video_out_TDATA(23 downto 0), + m_axis_video_tlast => v_rgb2ycrcb_0_video_out_TLAST, + m_axis_video_tready => v_rgb2ycrcb_0_video_out_TREADY, + m_axis_video_tuser_sof => v_rgb2ycrcb_0_video_out_TUSER, + m_axis_video_tvalid => v_rgb2ycrcb_0_video_out_TVALID, + s_axis_video_tdata(23 downto 0) => v_vid_in_axi4s_0_video_out_TDATA(23 downto 0), + s_axis_video_tlast => v_vid_in_axi4s_0_video_out_TLAST, + s_axis_video_tready => v_vid_in_axi4s_0_video_out_TREADY, + s_axis_video_tuser_sof => v_vid_in_axi4s_0_video_out_TUSER, + s_axis_video_tvalid => v_vid_in_axi4s_0_video_out_TVALID + ); v_tc_0: component Arty_Z7_20_v_tc_0_0 port map ( active_video_out => v_tc_0_vtiming_out_ACTIVE_VIDEO, @@ -5181,6 +7129,69 @@ v_tc_0: component Arty_Z7_20_v_tc_0_0 vblank_out => v_tc_0_vtiming_out_VBLANK, vsync_out => v_tc_0_vtiming_out_VSYNC ); +v_tc_1: component Arty_Z7_20_v_tc_1_0 + port map ( + active_video_in => v_vid_in_axi4s_0_vtiming_out_ACTIVE_VIDEO, + clk => dvi2rgb_0_PixelClk, + clken => '1', + det_clken => '1', + hsync_in => v_vid_in_axi4s_0_vtiming_out_HSYNC, + intc_if(31 downto 0) => NLW_v_tc_1_intc_if_UNCONNECTED(31 downto 0), + irq => v_tc_1_irq, + resetn => proc_sys_reset_0_peripheral_aresetn(0), + s_axi_aclk => processing_system7_0_FCLK_CLK0, + s_axi_aclken => '1', + s_axi_araddr(8 downto 0) => processing_system7_0_axi_periph_M09_AXI_ARADDR(8 downto 0), + s_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0), + s_axi_arready => processing_system7_0_axi_periph_M09_AXI_ARREADY, + s_axi_arvalid => processing_system7_0_axi_periph_M09_AXI_ARVALID, + s_axi_awaddr(8 downto 0) => processing_system7_0_axi_periph_M09_AXI_AWADDR(8 downto 0), + s_axi_awready => processing_system7_0_axi_periph_M09_AXI_AWREADY, + s_axi_awvalid => processing_system7_0_axi_periph_M09_AXI_AWVALID, + s_axi_bready => processing_system7_0_axi_periph_M09_AXI_BREADY, + s_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M09_AXI_BRESP(1 downto 0), + s_axi_bvalid => processing_system7_0_axi_periph_M09_AXI_BVALID, + s_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M09_AXI_RDATA(31 downto 0), + s_axi_rready => processing_system7_0_axi_periph_M09_AXI_RREADY, + s_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M09_AXI_RRESP(1 downto 0), + s_axi_rvalid => processing_system7_0_axi_periph_M09_AXI_RVALID, + s_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M09_AXI_WDATA(31 downto 0), + s_axi_wready => processing_system7_0_axi_periph_M09_AXI_WREADY, + s_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M09_AXI_WSTRB(3 downto 0), + s_axi_wvalid => processing_system7_0_axi_periph_M09_AXI_WVALID, + vsync_in => v_vid_in_axi4s_0_vtiming_out_VSYNC + ); +v_vid_in_axi4s_0: component Arty_Z7_20_v_vid_in_axi4s_0_0 + port map ( + aclk => processing_system7_0_FCLK_CLK1, + aclken => '1', + aresetn => '1', + axis_enable => '1', + fid => NLW_v_vid_in_axi4s_0_fid_UNCONNECTED, + m_axis_video_tdata(23 downto 0) => v_vid_in_axi4s_0_video_out_TDATA(23 downto 0), + m_axis_video_tlast => v_vid_in_axi4s_0_video_out_TLAST, + m_axis_video_tready => v_vid_in_axi4s_0_video_out_TREADY, + m_axis_video_tuser => v_vid_in_axi4s_0_video_out_TUSER, + m_axis_video_tvalid => v_vid_in_axi4s_0_video_out_TVALID, + overflow => NLW_v_vid_in_axi4s_0_overflow_UNCONNECTED, + underflow => NLW_v_vid_in_axi4s_0_underflow_UNCONNECTED, + vid_active_video => dvi2rgb_0_RGB_ACTIVE_VIDEO, + vid_data(23 downto 0) => dvi2rgb_0_RGB_DATA(23 downto 0), + vid_field_id => '0', + vid_hblank => '0', + vid_hsync => dvi2rgb_0_RGB_HSYNC, + vid_io_in_ce => '1', + vid_io_in_clk => dvi2rgb_0_PixelClk, + vid_io_in_reset => proc_sys_reset_0_peripheral_reset(0), + vid_vblank => '0', + vid_vsync => dvi2rgb_0_RGB_VSYNC, + vtd_active_video => v_vid_in_axi4s_0_vtiming_out_ACTIVE_VIDEO, + vtd_field_id => NLW_v_vid_in_axi4s_0_vtd_field_id_UNCONNECTED, + vtd_hblank => NLW_v_vid_in_axi4s_0_vtd_hblank_UNCONNECTED, + vtd_hsync => v_vid_in_axi4s_0_vtiming_out_HSYNC, + vtd_vblank => NLW_v_vid_in_axi4s_0_vtd_vblank_UNCONNECTED, + vtd_vsync => v_vid_in_axi4s_0_vtiming_out_VSYNC + ); xadc_wiz_0: component Arty_Z7_20_xadc_wiz_0_0 port map ( alarm_out => NLW_xadc_wiz_0_alarm_out_UNCONNECTED, @@ -5242,9 +7253,10 @@ xlconcat_0: component Arty_Z7_20_xlconcat_0_0 In2(0) => v_tc_0_irq, In3(0) => axi_gpio_0_ip2intc_irpt, In4(0) => xadc_wiz_0_ip2intc_irpt, - In5(0) => axi_gpio_shield_1_ip2intc_irpt, - In6(0) => axi_gpio_shield_2_ip2intc_irpt, - dout(6 downto 0) => xlconcat_0_dout(6 downto 0) + In5(0) => v_tc_1_irq, + In6(0) => axi_gpio_video_ip2intc_irpt, + In7(0) => axi_vdma_0_s2mm_introut, + dout(7 downto 0) => xlconcat_0_dout(7 downto 0) ); xlconcat_1: component Arty_Z7_20_xlconcat_1_0 port map ( diff --git a/src/bd/Arty_Z7_20/hdl/Arty_Z7_20_wrapper.vhd b/src/bd/Arty_Z7_20/hdl/Arty_Z7_20_wrapper.vhd index c419c1d..2e722ac 100644 --- a/src/bd/Arty_Z7_20/hdl/Arty_Z7_20_wrapper.vhd +++ b/src/bd/Arty_Z7_20/hdl/Arty_Z7_20_wrapper.vhd @@ -1,7 +1,7 @@ --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------- --Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 ---Date : Mon Feb 27 10:04:54 2017 +--Date : Mon Mar 06 11:44:15 2017 --Host : WK73 running 64-bit Service Pack 1 (build 7601) --Command : generate_target Arty_Z7_20_wrapper.bd --Design : Arty_Z7_20_wrapper @@ -34,6 +34,10 @@ entity Arty_Z7_20_wrapper is FIXED_IO_ps_clk : inout STD_LOGIC; FIXED_IO_ps_porb : inout STD_LOGIC; FIXED_IO_ps_srstb : inout STD_LOGIC; + TMDS_In_clk_n : in STD_LOGIC; + TMDS_In_clk_p : in STD_LOGIC; + TMDS_In_data_n : in STD_LOGIC_VECTOR ( 2 downto 0 ); + TMDS_In_data_p : in STD_LOGIC_VECTOR ( 2 downto 0 ); TMDS_clk_n : out STD_LOGIC; TMDS_clk_p : out STD_LOGIC; TMDS_data_n : out STD_LOGIC_VECTOR ( 2 downto 0 ); @@ -59,9 +63,12 @@ entity Arty_Z7_20_wrapper is Vp_Vn_v_n : in STD_LOGIC; Vp_Vn_v_p : in STD_LOGIC; btns_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 ); + ddc_in_scl_io : inout STD_LOGIC; + ddc_in_sda_io : inout STD_LOGIC; hdmi_ddc_scl_io : inout STD_LOGIC; hdmi_ddc_sda_io : inout STD_LOGIC; hdmi_hpd_tri_i : in STD_LOGIC_VECTOR ( 0 to 0 ); + hdmi_in_hpd_tri_o : out STD_LOGIC_VECTOR ( 0 to 0 ); leds_4bits_tri_io : inout STD_LOGIC_VECTOR ( 3 downto 0 ); rgbled_tri_io : inout STD_LOGIC_VECTOR ( 5 downto 0 ); shield_dp0_dp13_tri_io : inout STD_LOGIC_VECTOR ( 13 downto 0 ); @@ -164,6 +171,17 @@ architecture STRUCTURE of Arty_Z7_20_wrapper is shield_dp26_dp41_tri_o : out STD_LOGIC_VECTOR ( 15 downto 0 ); shield_dp26_dp41_tri_t : out STD_LOGIC_VECTOR ( 15 downto 0 ); sws_2bits_tri_i : in STD_LOGIC_VECTOR ( 1 downto 0 ); + TMDS_In_clk_p : in STD_LOGIC; + TMDS_In_clk_n : in STD_LOGIC; + TMDS_In_data_p : in STD_LOGIC_VECTOR ( 2 downto 0 ); + TMDS_In_data_n : in STD_LOGIC_VECTOR ( 2 downto 0 ); + DDC_In_scl_i : in STD_LOGIC; + DDC_In_scl_o : out STD_LOGIC; + DDC_In_scl_t : out STD_LOGIC; + DDC_In_sda_i : in STD_LOGIC; + DDC_In_sda_o : out STD_LOGIC; + DDC_In_sda_t : out STD_LOGIC; + hdmi_in_hpd_tri_o : out STD_LOGIC_VECTOR ( 0 to 0 ); sys_clock : in STD_LOGIC ); end component Arty_Z7_20; @@ -175,6 +193,12 @@ architecture STRUCTURE of Arty_Z7_20_wrapper is IO : inout STD_LOGIC ); end component IOBUF; + signal ddc_in_scl_i : STD_LOGIC; + signal ddc_in_scl_o : STD_LOGIC; + signal ddc_in_scl_t : STD_LOGIC; + signal ddc_in_sda_i : STD_LOGIC; + signal ddc_in_sda_o : STD_LOGIC; + signal ddc_in_sda_t : STD_LOGIC; signal hdmi_ddc_scl_i : STD_LOGIC; signal hdmi_ddc_scl_o : STD_LOGIC; signal hdmi_ddc_scl_t : STD_LOGIC; @@ -362,6 +386,12 @@ architecture STRUCTURE of Arty_Z7_20_wrapper is begin Arty_Z7_20_i: component Arty_Z7_20 port map ( + DDC_In_scl_i => ddc_in_scl_i, + DDC_In_scl_o => ddc_in_scl_o, + DDC_In_scl_t => ddc_in_scl_t, + DDC_In_sda_i => ddc_in_sda_i, + DDC_In_sda_o => ddc_in_sda_o, + DDC_In_sda_t => ddc_in_sda_t, DDR_addr(14 downto 0) => DDR_addr(14 downto 0), DDR_ba(2 downto 0) => DDR_ba(2 downto 0), DDR_cas_n => DDR_cas_n, @@ -408,6 +438,10 @@ Arty_Z7_20_i: component Arty_Z7_20 RGBLED_tri_t(2) => rgbled_tri_t_2(2), RGBLED_tri_t(1) => rgbled_tri_t_1(1), RGBLED_tri_t(0) => rgbled_tri_t_0(0), + TMDS_In_clk_n => TMDS_In_clk_n, + TMDS_In_clk_p => TMDS_In_clk_p, + TMDS_In_data_n(2 downto 0) => TMDS_In_data_n(2 downto 0), + TMDS_In_data_p(2 downto 0) => TMDS_In_data_p(2 downto 0), TMDS_clk_n => TMDS_clk_n, TMDS_clk_p => TMDS_clk_p, TMDS_data_n(2 downto 0) => TMDS_data_n(2 downto 0), @@ -433,6 +467,7 @@ Arty_Z7_20_i: component Arty_Z7_20 Vp_Vn_v_n => Vp_Vn_v_n, Vp_Vn_v_p => Vp_Vn_v_p, btns_4bits_tri_i(3 downto 0) => btns_4bits_tri_i(3 downto 0), + hdmi_in_hpd_tri_o(0) => hdmi_in_hpd_tri_o(0), leds_4bits_tri_i(3) => leds_4bits_tri_i_3(3), leds_4bits_tri_i(2) => leds_4bits_tri_i_2(2), leds_4bits_tri_i(1) => leds_4bits_tri_i_1(1), @@ -556,6 +591,20 @@ Arty_Z7_20_i: component Arty_Z7_20 sws_2bits_tri_i(1 downto 0) => sws_2bits_tri_i(1 downto 0), sys_clock => sys_clock ); +ddc_in_scl_iobuf: component IOBUF + port map ( + I => ddc_in_scl_o, + IO => ddc_in_scl_io, + O => ddc_in_scl_i, + T => ddc_in_scl_t + ); +ddc_in_sda_iobuf: component IOBUF + port map ( + I => ddc_in_sda_o, + IO => ddc_in_sda_io, + O => ddc_in_sda_i, + T => ddc_in_sda_t + ); hdmi_ddc_scl_iobuf: component IOBUF port map ( I => hdmi_ddc_scl_o, diff --git a/src/bd/Arty_Z7_20/hw_handoff/Arty_Z7_20.hwh b/src/bd/Arty_Z7_20/hw_handoff/Arty_Z7_20.hwh index abaf5ca..5270452 100644 --- a/src/bd/Arty_Z7_20/hw_handoff/Arty_Z7_20.hwh +++ b/src/bd/Arty_Z7_20/hw_handoff/Arty_Z7_20.hwh @@ -1,5 +1,5 @@  - + @@ -90,6 +90,17 @@ + + + + + + + + + + + @@ -289,6 +300,29 @@ + + + + + + + + + + + + + + + + + + + + + + + @@ -1382,7 +1416,7 @@ - + @@ -1492,11 +1526,6 @@ - - - - - @@ -1742,7 +1771,7 @@ - + @@ -1852,11 +1881,6 @@ - - - - - @@ -2284,77 +2308,443 @@ - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -2637,6 +3027,16 @@ + + + + + + + + + + @@ -2667,7 +3067,7 @@ - + @@ -2677,12 +3077,12 @@ - + - + @@ -2737,17 +3137,17 @@ - + - + - + @@ -2757,7 +3157,7 @@ - + @@ -2767,7 +3167,7 @@ - + @@ -2787,42 +3187,42 @@ - + - + - + - + - + - + - + - + @@ -2892,35 +3292,115 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -2953,6 +3433,26 @@ + + + + + + + + + + + + + + + + + + + + @@ -4462,7 +4962,7 @@ - + @@ -4478,26 +4978,26 @@ - + - + - - + + - + - + - + @@ -4523,12 +5023,12 @@ - + - + @@ -4537,20 +5037,20 @@ - + - + - + - + - - + + @@ -4583,12 +5083,22 @@ - + - + + + + + + + + + + + @@ -4679,6 +5189,8 @@ + + @@ -4774,11 +5286,122 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -4836,7 +5459,7 @@ - + @@ -4855,7 +5478,7 @@ - + @@ -4878,6 +5501,56 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -4887,7 +5560,7 @@ - + @@ -4900,9 +5573,32 @@ + + + + + + + + + + + + + + + + + + + + + + + @@ -4954,7 +5650,7 @@ - + @@ -5031,7 +5727,7 @@ - + @@ -5053,7 +5749,7 @@ - + @@ -5068,71 +5764,223 @@ - + - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + @@ -5146,14 +5994,14 @@ - + - + @@ -5174,7 +6022,7 @@ - + @@ -5188,7 +6036,7 @@ - + @@ -5216,7 +6064,7 @@ - + @@ -5311,7 +6159,7 @@ - + @@ -5326,8 +6174,8 @@ - - + + @@ -5347,7 +6195,7 @@ - + @@ -5374,7 +6222,7 @@ - + @@ -5394,7 +6242,7 @@ - + @@ -5423,13 +6271,13 @@ - + - + @@ -5459,7 +6307,7 @@ - + @@ -5506,7 +6354,7 @@ - + @@ -5528,7 +6376,7 @@ - + @@ -5539,11 +6387,11 @@ - + - + @@ -5619,8 +6467,8 @@ - - + + @@ -5638,6 +6486,7 @@ + @@ -5648,6 +6497,11 @@ + + + + + @@ -5656,7 +6510,110 @@ - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -5670,15 +6627,15 @@ - + - + - + @@ -5686,18 +6643,30 @@ - + + + + + - + + + + + - + + + + + - + @@ -5711,15 +6680,15 @@ - + - + - + @@ -5738,7 +6707,7 @@ - + @@ -5752,7 +6721,48 @@ - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -5822,7 +6832,7 @@ - + @@ -5976,7 +6986,7 @@ - + @@ -6000,7 +7010,7 @@ - + @@ -6010,7 +7020,7 @@ - + @@ -6024,7 +7034,7 @@ - + @@ -6164,7 +7174,7 @@ - + @@ -6431,7 +7441,7 @@ - + @@ -7020,7 +8030,7 @@ - + @@ -7162,7 +8172,7 @@ - + @@ -7181,6 +8191,8 @@ + + @@ -7192,9 +8204,11 @@ + + - + @@ -7202,9 +8216,15 @@ + + + + + + @@ -7224,6 +8244,7 @@ + @@ -7430,7 +8451,7 @@ - + @@ -7504,10 +8525,12 @@ + + @@ -7515,10 +8538,12 @@ + + @@ -7527,7 +8552,7 @@ - + @@ -7954,6 +8979,26 @@ + + + + + + + + + + + + + + + + + + + + @@ -8914,6 +9959,176 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -9148,6 +10363,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -9275,6 +10532,9 @@ + + + @@ -9285,6 +10545,8 @@ + + @@ -9310,7 +10572,7 @@ - + @@ -9335,6 +10597,7 @@ + @@ -9363,7 +10626,7 @@ - + @@ -9472,48 +10735,601 @@ - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - + + + + + - - - - - - + + + + + + + + + + + + + + + + + - + - - - - - - - + + + + + - + - + @@ -9576,17 +11392,17 @@ - + - + - + - - + + @@ -9597,14 +11413,14 @@ - + - + - + @@ -9668,31 +11484,31 @@ - + - + - + - + - - + + - + - + @@ -9702,137 +11518,126 @@ - - - - - - + + + - - - - - - + - + - + - + - + - + - + - - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + @@ -9854,8 +11659,8 @@ - - + + @@ -9883,13 +11688,165 @@ - + - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -10423,8 +12380,8 @@ - - + + @@ -10454,17 +12411,22 @@ - + + + + + + - + - + - + - + @@ -10539,6 +12501,7 @@ + diff --git a/src/bd/Arty_Z7_20/hw_handoff/Arty_Z7_20_bd.tcl b/src/bd/Arty_Z7_20/hw_handoff/Arty_Z7_20_bd.tcl index 6e1502e..e2ded53 100644 --- a/src/bd/Arty_Z7_20/hw_handoff/Arty_Z7_20_bd.tcl +++ b/src/bd/Arty_Z7_20/hw_handoff/Arty_Z7_20_bd.tcl @@ -152,12 +152,14 @@ proc create_root_design { parentCell } { # Create interface ports + set DDC_In [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 DDC_In ] set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] set HDMI_DDC [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 HDMI_DDC ] set HDMI_HPD [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 HDMI_HPD ] set RGBLED [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 RGBLED ] set TMDS [ create_bd_intf_port -mode Master -vlnv digilentinc.com:interface:tmds_rtl:1.0 TMDS ] + set TMDS_In [ create_bd_intf_port -mode Slave -vlnv digilentinc.com:interface:tmds_rtl:1.0 TMDS_In ] set Vaux0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux0 ] set Vaux1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux1 ] set Vaux5 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux5 ] @@ -169,6 +171,7 @@ proc create_root_design { parentCell } { set Vaux15 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux15 ] set Vp_Vn [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn ] set btns_4bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 btns_4bits ] + set hdmi_in_hpd [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 hdmi_in_hpd ] set leds_4bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 leds_4bits ] set shield_IIC [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 shield_IIC ] set shield_SPI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:spi_rtl:1.0 shield_SPI ] @@ -207,7 +210,7 @@ CONFIG.USE_BOARD_FLOW {true} \ set_property -dict [ list \ CONFIG.C_GPIO2_WIDTH {32} \ CONFIG.C_GPIO_WIDTH {14} \ -CONFIG.C_INTERRUPT_PRESENT {1} \ +CONFIG.C_INTERRUPT_PRESENT {0} \ CONFIG.C_IS_DUAL {0} \ CONFIG.GPIO_BOARD_INTERFACE {shield_dp0_dp13} \ ] $axi_gpio_shield_1 @@ -216,7 +219,7 @@ CONFIG.GPIO_BOARD_INTERFACE {shield_dp0_dp13} \ set axi_gpio_shield_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_shield_2 ] set_property -dict [ list \ CONFIG.C_GPIO_WIDTH {16} \ -CONFIG.C_INTERRUPT_PRESENT {1} \ +CONFIG.C_INTERRUPT_PRESENT {0} \ CONFIG.GPIO_BOARD_INTERFACE {shield_dp26_dp41} \ CONFIG.USE_BOARD_FLOW {true} \ ] $axi_gpio_shield_2 @@ -230,10 +233,22 @@ CONFIG.GPIO_BOARD_INTERFACE {btns_4bits} \ CONFIG.USE_BOARD_FLOW {true} \ ] $axi_gpio_sw + # Create instance: axi_gpio_video, and set properties + set axi_gpio_video [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_video ] + set_property -dict [ list \ +CONFIG.C_ALL_INPUTS_2 {1} \ +CONFIG.C_ALL_OUTPUTS {1} \ +CONFIG.C_GPIO2_WIDTH {1} \ +CONFIG.C_GPIO_WIDTH {1} \ +CONFIG.C_INTERRUPT_PRESENT {1} \ +CONFIG.C_IS_DUAL {1} \ + ] $axi_gpio_video + # Create instance: axi_mem_intercon, and set properties set axi_mem_intercon [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_intercon ] set_property -dict [ list \ CONFIG.NUM_MI {1} \ +CONFIG.NUM_SI {2} \ CONFIG.S00_HAS_DATA_FIFO {2} \ CONFIG.S00_HAS_REGSLICE {4} \ ] $axi_mem_intercon @@ -241,12 +256,16 @@ CONFIG.S00_HAS_REGSLICE {4} \ # Create instance: axi_vdma_0, and set properties set axi_vdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.2 axi_vdma_0 ] set_property -dict [ list \ -CONFIG.c_include_s2mm {0} \ +CONFIG.c_include_s2mm {1} \ +CONFIG.c_m_axi_s2mm_data_width {64} \ +CONFIG.c_m_axis_mm2s_tdata_width {32} \ CONFIG.c_mm2s_genlock_mode {0} \ -CONFIG.c_mm2s_linebuffer_depth {4096} \ -CONFIG.c_mm2s_max_burst_length {16} \ -CONFIG.c_num_fstores {1} \ -CONFIG.c_s2mm_genlock_mode {0} \ +CONFIG.c_mm2s_linebuffer_depth {2048} \ +CONFIG.c_mm2s_max_burst_length {32} \ +CONFIG.c_num_fstores {3} \ +CONFIG.c_s2mm_genlock_mode {2} \ +CONFIG.c_s2mm_linebuffer_depth {2048} \ +CONFIG.c_s2mm_max_burst_length {32} \ ] $axi_vdma_0 # Create instance: axis_subset_converter_0, and set properties @@ -260,34 +279,71 @@ CONFIG.TDATA_REMAP {tdata[23:16],tdata[7:0],tdata[15:8]} \ CONFIG.TUSER_REMAP {tuser[0:0]} \ ] $axis_subset_converter_0 + # Create instance: axis_subset_converter_1, and set properties + set axis_subset_converter_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_subset_converter:1.1 axis_subset_converter_1 ] + set_property -dict [ list \ +CONFIG.M_TDATA_NUM_BYTES {1} \ +CONFIG.M_TUSER_WIDTH {1} \ +CONFIG.S_TDATA_NUM_BYTES {3} \ +CONFIG.S_TUSER_WIDTH {1} \ +CONFIG.TDATA_REMAP {tdata[7:0]} \ +CONFIG.TKEEP_REMAP {1'b0} \ +CONFIG.TUSER_REMAP {tuser[0:0]} \ + ] $axis_subset_converter_1 + # Create instance: clk_wiz_0, and set properties set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 clk_wiz_0 ] set_property -dict [ list \ CONFIG.CLKIN1_JITTER_PS {80.0} \ +CONFIG.CLKOUT1_DRIVES {BUFG} \ CONFIG.CLKOUT1_JITTER {119.348} \ CONFIG.CLKOUT1_PHASE_ERROR {96.948} \ CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {125} \ +CONFIG.CLKOUT2_DRIVES {BUFG} \ +CONFIG.CLKOUT2_JITTER {109.241} \ +CONFIG.CLKOUT2_PHASE_ERROR {96.948} \ +CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \ +CONFIG.CLKOUT2_USED {true} \ +CONFIG.CLKOUT3_DRIVES {BUFG} \ +CONFIG.CLKOUT4_DRIVES {BUFG} \ +CONFIG.CLKOUT5_DRIVES {BUFG} \ +CONFIG.CLKOUT6_DRIVES {BUFG} \ +CONFIG.CLKOUT7_DRIVES {BUFG} \ CONFIG.CLK_IN1_BOARD_INTERFACE {sys_clock} \ -CONFIG.MMCM_CLKFBOUT_MULT_F {8.000} \ +CONFIG.MMCM_CLKFBOUT_MULT_F {8} \ CONFIG.MMCM_CLKIN1_PERIOD {8.0} \ CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ -CONFIG.MMCM_CLKOUT0_DIVIDE_F {8.000} \ +CONFIG.MMCM_CLKOUT0_DIVIDE_F {8} \ +CONFIG.MMCM_CLKOUT1_DIVIDE {5} \ CONFIG.MMCM_COMPENSATION {ZHOLD} \ CONFIG.MMCM_DIVCLK_DIVIDE {1} \ +CONFIG.NUM_OUT_CLKS {2} \ +CONFIG.PRIMITIVE {PLL} \ CONFIG.USE_BOARD_FLOW {true} \ -CONFIG.USE_RESET {false} \ +CONFIG.USE_RESET {true} \ ] $clk_wiz_0 # Need to retain value_src of defaults set_property -dict [ list \ CONFIG.CLKIN1_JITTER_PS.VALUE_SRC {DEFAULT} \ CONFIG.CLKOUT1_PHASE_ERROR.VALUE_SRC {DEFAULT} \ -CONFIG.MMCM_CLKFBOUT_MULT_F.VALUE_SRC {DEFAULT} \ CONFIG.MMCM_CLKIN1_PERIOD.VALUE_SRC {DEFAULT} \ CONFIG.MMCM_CLKIN2_PERIOD.VALUE_SRC {DEFAULT} \ -CONFIG.MMCM_COMPENSATION.VALUE_SRC {DEFAULT} \ ] $clk_wiz_0 + # Create instance: dvi2rgb_0, and set properties + set dvi2rgb_0 [ create_bd_cell -type ip -vlnv digilentinc.com:ip:dvi2rgb:1.7 dvi2rgb_0 ] + set_property -dict [ list \ +CONFIG.kAddBUFG {true} \ +CONFIG.kRstActiveHigh {false} \ + ] $dvi2rgb_0 + + # Create instance: proc_sys_reset_0, and set properties + set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] + set_property -dict [ list \ +CONFIG.C_AUX_RESET_HIGH {0} \ + ] $proc_sys_reset_0 + # Create instance: proc_sys_reset_2, and set properties set proc_sys_reset_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_2 ] @@ -308,7 +364,7 @@ CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.096154} \ CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \ CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \ CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \ -CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {142.857132} \ +CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {118.181816} \ CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {76.923080} \ CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {50.000000} \ CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50} \ @@ -354,7 +410,7 @@ CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \ CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \ CONFIG.PCW_CAN_PERIPHERAL_VALID {0} \ CONFIG.PCW_CLK0_FREQ {100000000} \ -CONFIG.PCW_CLK1_FREQ {142857132} \ +CONFIG.PCW_CLK1_FREQ {118181816} \ CONFIG.PCW_CLK2_FREQ {76923080} \ CONFIG.PCW_CLK3_FREQ {50000000} \ CONFIG.PCW_CORE0_FIQ_INTR {0} \ @@ -490,8 +546,8 @@ CONFIG.PCW_EN_WDT {0} \ CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \ CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \ CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \ -CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \ -CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {7} \ +CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {ARM PLL} \ +CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {11} \ CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \ CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \ CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {13} \ @@ -504,7 +560,7 @@ CONFIG.PCW_FCLK_CLK1_BUF {TRUE} \ CONFIG.PCW_FCLK_CLK2_BUF {TRUE} \ CONFIG.PCW_FCLK_CLK3_BUF {TRUE} \ CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \ -CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {142} \ +CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {120} \ CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {75} \ CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \ CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \ @@ -1267,7 +1323,7 @@ CONFIG.PCW_WDT_WDT_IO.VALUE_SRC {DEFAULT} \ # Create instance: processing_system7_0_axi_periph, and set properties set processing_system7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 processing_system7_0_axi_periph ] set_property -dict [ list \ -CONFIG.NUM_MI {9} \ +CONFIG.NUM_MI {11} \ ] $processing_system7_0_axi_periph # Create instance: rgb2dvi_0, and set properties @@ -1294,12 +1350,36 @@ CONFIG.C_S_AXIS_VIDEO_FORMAT {2} \ CONFIG.C_VTG_MASTER_SLAVE {1} \ ] $v_axi4s_vid_out_0 + # Create instance: v_rgb2ycrcb_0, and set properties + set v_rgb2ycrcb_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:v_rgb2ycrcb:7.1 v_rgb2ycrcb_0 ] + set_property -dict [ list \ +CONFIG.ACTIVE_COLS {1280} \ +CONFIG.ACTIVE_ROWS {720} \ + ] $v_rgb2ycrcb_0 + # Create instance: v_tc_0, and set properties set v_tc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:v_tc:6.1 v_tc_0 ] set_property -dict [ list \ CONFIG.enable_detection {false} \ ] $v_tc_0 + # Create instance: v_tc_1, and set properties + set v_tc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:v_tc:6.1 v_tc_1 ] + set_property -dict [ list \ +CONFIG.HAS_INTC_IF {true} \ +CONFIG.enable_generation {false} \ +CONFIG.horizontal_blank_detection {false} \ +CONFIG.max_lines_per_frame {2048} \ +CONFIG.vertical_blank_detection {false} \ + ] $v_tc_1 + + # Create instance: v_vid_in_axi4s_0, and set properties + set v_vid_in_axi4s_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:v_vid_in_axi4s:4.0 v_vid_in_axi4s_0 ] + set_property -dict [ list \ +CONFIG.C_ADDR_WIDTH {12} \ +CONFIG.C_HAS_ASYNC_CLK {1} \ + ] $v_vid_in_axi4s_0 + # Create instance: xadc_wiz_0, and set properties set xadc_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.3 xadc_wiz_0 ] set_property -dict [ list \ @@ -1356,7 +1436,7 @@ CONFIG.INTERFACE_SELECTION.VALUE_SRC {DEFAULT} \ # Create instance: xlconcat_0, and set properties set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] set_property -dict [ list \ -CONFIG.NUM_PORTS {7} \ +CONFIG.NUM_PORTS {8} \ ] $xlconcat_0 # Create instance: xlconcat_1, and set properties @@ -1366,6 +1446,7 @@ CONFIG.NUM_PORTS {7} \ set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] # Create interface connections + connect_bd_intf_net -intf_net TMDS_1_1 [get_bd_intf_ports TMDS_In] [get_bd_intf_pins dvi2rgb_0/TMDS] connect_bd_intf_net -intf_net Vaux0_1 [get_bd_intf_ports Vaux0] [get_bd_intf_pins xadc_wiz_0/Vaux0] connect_bd_intf_net -intf_net Vaux12_1 [get_bd_intf_ports Vaux12] [get_bd_intf_pins xadc_wiz_0/Vaux12] connect_bd_intf_net -intf_net Vaux13_1 [get_bd_intf_ports Vaux13] [get_bd_intf_pins xadc_wiz_0/Vaux13] @@ -1382,10 +1463,15 @@ CONFIG.NUM_PORTS {7} \ connect_bd_intf_net -intf_net axi_gpio_2_GPIO [get_bd_intf_ports leds_4bits] [get_bd_intf_pins axi_gpio_led/GPIO] connect_bd_intf_net -intf_net axi_gpio_hdmi_GPIO [get_bd_intf_ports HDMI_HPD] [get_bd_intf_pins axi_gpio_hdmi/GPIO] connect_bd_intf_net -intf_net axi_gpio_shield_2_GPIO [get_bd_intf_ports shield_dp26_dp41] [get_bd_intf_pins axi_gpio_shield_2/GPIO] + connect_bd_intf_net -intf_net axi_gpio_video_GPIO [get_bd_intf_ports hdmi_in_hpd] [get_bd_intf_pins axi_gpio_video/GPIO] connect_bd_intf_net -intf_net axi_mem_intercon_M00_AXI [get_bd_intf_pins axi_mem_intercon/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0] connect_bd_intf_net -intf_net axi_vdma_0_M_AXIS_MM2S [get_bd_intf_pins axi_vdma_0/M_AXIS_MM2S] [get_bd_intf_pins axis_subset_converter_0/S_AXIS] connect_bd_intf_net -intf_net axi_vdma_0_M_AXI_MM2S [get_bd_intf_pins axi_mem_intercon/S00_AXI] [get_bd_intf_pins axi_vdma_0/M_AXI_MM2S] + connect_bd_intf_net -intf_net axi_vdma_0_M_AXI_S2MM [get_bd_intf_pins axi_mem_intercon/S01_AXI] [get_bd_intf_pins axi_vdma_0/M_AXI_S2MM] connect_bd_intf_net -intf_net axis_subset_converter_0_M_AXIS [get_bd_intf_pins axis_subset_converter_0/M_AXIS] [get_bd_intf_pins v_axi4s_vid_out_0/video_in] + connect_bd_intf_net -intf_net axis_subset_converter_1_M_AXIS [get_bd_intf_pins axi_vdma_0/S_AXIS_S2MM] [get_bd_intf_pins axis_subset_converter_1/M_AXIS] + connect_bd_intf_net -intf_net dvi2rgb_0_DDC [get_bd_intf_ports DDC_In] [get_bd_intf_pins dvi2rgb_0/DDC] + connect_bd_intf_net -intf_net dvi2rgb_0_RGB [get_bd_intf_pins dvi2rgb_0/RGB] [get_bd_intf_pins v_vid_in_axi4s_0/vid_io_in] connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO] connect_bd_intf_net -intf_net processing_system7_0_GPIO_0 [get_bd_intf_ports RGBLED] [get_bd_intf_pins processing_system7_0/GPIO_0] @@ -1402,9 +1488,14 @@ CONFIG.NUM_PORTS {7} \ connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M06_AXI [get_bd_intf_pins axi_gpio_hdmi/S_AXI] [get_bd_intf_pins processing_system7_0_axi_periph/M06_AXI] connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M07_AXI [get_bd_intf_pins processing_system7_0_axi_periph/M07_AXI] [get_bd_intf_pins xadc_wiz_0/s_axi_lite] connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M08_AXI [get_bd_intf_pins axi_gpio_shield_2/S_AXI] [get_bd_intf_pins processing_system7_0_axi_periph/M08_AXI] + connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M09_AXI [get_bd_intf_pins processing_system7_0_axi_periph/M09_AXI] [get_bd_intf_pins v_tc_1/ctrl] + connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M10_AXI [get_bd_intf_pins axi_gpio_video/S_AXI] [get_bd_intf_pins processing_system7_0_axi_periph/M10_AXI] connect_bd_intf_net -intf_net rgb2dvi_0_TMDS [get_bd_intf_ports TMDS] [get_bd_intf_pins rgb2dvi_0/TMDS] connect_bd_intf_net -intf_net v_axi4s_vid_out_0_vid_io_out [get_bd_intf_pins rgb2dvi_0/RGB] [get_bd_intf_pins v_axi4s_vid_out_0/vid_io_out] + connect_bd_intf_net -intf_net v_rgb2ycrcb_0_video_out [get_bd_intf_pins axis_subset_converter_1/S_AXIS] [get_bd_intf_pins v_rgb2ycrcb_0/video_out] connect_bd_intf_net -intf_net v_tc_0_vtiming_out [get_bd_intf_pins v_axi4s_vid_out_0/vtiming_in] [get_bd_intf_pins v_tc_0/vtiming_out] + connect_bd_intf_net -intf_net v_vid_in_axi4s_0_video_out [get_bd_intf_pins v_rgb2ycrcb_0/video_in] [get_bd_intf_pins v_vid_in_axi4s_0/video_out] + connect_bd_intf_net -intf_net v_vid_in_axi4s_0_vtiming_out [get_bd_intf_pins v_tc_1/vtiming_in] [get_bd_intf_pins v_vid_in_axi4s_0/vtiming_out] # Create port connections connect_bd_net -net axi_dynclk_0_LOCKED_O [get_bd_pins axi_dynclk_0/LOCKED_O] [get_bd_pins rgb2dvi_0/aRst_n] @@ -1412,160 +1503,197 @@ CONFIG.NUM_PORTS {7} \ connect_bd_net -net axi_dynclk_0_PXL_CLK_O [get_bd_pins axi_dynclk_0/PXL_CLK_O] [get_bd_pins rgb2dvi_0/PixelClk] [get_bd_pins v_axi4s_vid_out_0/vid_io_out_clk] [get_bd_pins v_tc_0/clk] connect_bd_net -net axi_gpio_0_ip2intc_irpt [get_bd_pins axi_gpio_sw/ip2intc_irpt] [get_bd_pins xlconcat_0/In3] connect_bd_net -net axi_gpio_hdmi_ip2intc_irpt [get_bd_pins axi_gpio_hdmi/ip2intc_irpt] [get_bd_pins xlconcat_0/In0] - connect_bd_net -net axi_gpio_shield_1_ip2intc_irpt [get_bd_pins axi_gpio_shield_1/ip2intc_irpt] [get_bd_pins xlconcat_0/In5] - connect_bd_net -net axi_gpio_shield_2_ip2intc_irpt [get_bd_pins axi_gpio_shield_2/ip2intc_irpt] [get_bd_pins xlconcat_0/In6] + connect_bd_net -net axi_gpio_video_ip2intc_irpt [get_bd_pins axi_gpio_video/ip2intc_irpt] [get_bd_pins xlconcat_0/In6] connect_bd_net -net axi_vdma_0_mm2s_introut [get_bd_pins axi_vdma_0/mm2s_introut] [get_bd_pins xlconcat_0/In1] + connect_bd_net -net axi_vdma_0_s2mm_introut [get_bd_pins axi_vdma_0/s2mm_introut] [get_bd_pins xlconcat_0/In7] connect_bd_net -net clk_wiz_0_clk_out1 [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins proc_sys_reset_sysclk/slowest_sync_clk] + connect_bd_net -net clk_wiz_0_clk_out2 [get_bd_pins clk_wiz_0/clk_out2] [get_bd_pins dvi2rgb_0/RefClk] connect_bd_net -net clk_wiz_0_locked [get_bd_pins clk_wiz_0/locked] [get_bd_pins proc_sys_reset_sysclk/dcm_locked] - connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins axi_dynclk_0/REF_CLK_I] [get_bd_pins axi_dynclk_0/s00_axi_aclk] [get_bd_pins axi_gpio_hdmi/s_axi_aclk] [get_bd_pins axi_gpio_led/s_axi_aclk] [get_bd_pins axi_gpio_shield_1/s_axi_aclk] [get_bd_pins axi_gpio_shield_2/s_axi_aclk] [get_bd_pins axi_gpio_sw/s_axi_aclk] [get_bd_pins axi_vdma_0/s_axi_lite_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0_axi_periph/ACLK] [get_bd_pins processing_system7_0_axi_periph/M00_ACLK] [get_bd_pins processing_system7_0_axi_periph/M01_ACLK] [get_bd_pins processing_system7_0_axi_periph/M02_ACLK] [get_bd_pins processing_system7_0_axi_periph/M03_ACLK] [get_bd_pins processing_system7_0_axi_periph/M04_ACLK] [get_bd_pins processing_system7_0_axi_periph/M05_ACLK] [get_bd_pins processing_system7_0_axi_periph/M06_ACLK] [get_bd_pins processing_system7_0_axi_periph/M07_ACLK] [get_bd_pins processing_system7_0_axi_periph/M08_ACLK] [get_bd_pins processing_system7_0_axi_periph/S00_ACLK] [get_bd_pins rst_processing_system7_0_100M/slowest_sync_clk] [get_bd_pins v_tc_0/s_axi_aclk] [get_bd_pins xadc_wiz_0/s_axi_aclk] - connect_bd_net -net processing_system7_0_FCLK_CLK1 [get_bd_pins axi_mem_intercon/ACLK] [get_bd_pins axi_mem_intercon/M00_ACLK] [get_bd_pins axi_mem_intercon/S00_ACLK] [get_bd_pins axi_vdma_0/m_axi_mm2s_aclk] [get_bd_pins axi_vdma_0/m_axis_mm2s_aclk] [get_bd_pins axis_subset_converter_0/aclk] [get_bd_pins processing_system7_0/FCLK_CLK1] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins rst_processing_system7_0_142M/slowest_sync_clk] [get_bd_pins v_axi4s_vid_out_0/aclk] + connect_bd_net -net dvi2rgb_0_PixelClk [get_bd_pins dvi2rgb_0/PixelClk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins v_tc_1/clk] [get_bd_pins v_vid_in_axi4s_0/vid_io_in_clk] + connect_bd_net -net dvi2rgb_0_aPixelClkLckd [get_bd_pins axi_gpio_video/gpio2_io_i] [get_bd_pins dvi2rgb_0/aPixelClkLckd] [get_bd_pins proc_sys_reset_0/aux_reset_in] + connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins v_tc_1/resetn] + connect_bd_net -net proc_sys_reset_0_peripheral_reset [get_bd_pins proc_sys_reset_0/peripheral_reset] [get_bd_pins v_vid_in_axi4s_0/vid_io_in_reset] + connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins axi_dynclk_0/REF_CLK_I] [get_bd_pins axi_dynclk_0/s00_axi_aclk] [get_bd_pins axi_gpio_hdmi/s_axi_aclk] [get_bd_pins axi_gpio_led/s_axi_aclk] [get_bd_pins axi_gpio_shield_1/s_axi_aclk] [get_bd_pins axi_gpio_shield_2/s_axi_aclk] [get_bd_pins axi_gpio_sw/s_axi_aclk] [get_bd_pins axi_gpio_video/s_axi_aclk] [get_bd_pins axi_vdma_0/s_axi_lite_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0_axi_periph/ACLK] [get_bd_pins processing_system7_0_axi_periph/M00_ACLK] [get_bd_pins processing_system7_0_axi_periph/M01_ACLK] [get_bd_pins processing_system7_0_axi_periph/M02_ACLK] [get_bd_pins processing_system7_0_axi_periph/M03_ACLK] [get_bd_pins processing_system7_0_axi_periph/M04_ACLK] [get_bd_pins processing_system7_0_axi_periph/M05_ACLK] [get_bd_pins processing_system7_0_axi_periph/M06_ACLK] [get_bd_pins processing_system7_0_axi_periph/M07_ACLK] [get_bd_pins processing_system7_0_axi_periph/M08_ACLK] [get_bd_pins processing_system7_0_axi_periph/M09_ACLK] [get_bd_pins processing_system7_0_axi_periph/M10_ACLK] [get_bd_pins processing_system7_0_axi_periph/S00_ACLK] [get_bd_pins rst_processing_system7_0_100M/slowest_sync_clk] [get_bd_pins v_tc_0/s_axi_aclk] [get_bd_pins v_tc_1/s_axi_aclk] [get_bd_pins xadc_wiz_0/s_axi_aclk] + connect_bd_net -net processing_system7_0_FCLK_CLK1 [get_bd_pins axi_mem_intercon/ACLK] [get_bd_pins axi_mem_intercon/M00_ACLK] [get_bd_pins axi_mem_intercon/S00_ACLK] [get_bd_pins axi_mem_intercon/S01_ACLK] [get_bd_pins axi_vdma_0/m_axi_mm2s_aclk] [get_bd_pins axi_vdma_0/m_axi_s2mm_aclk] [get_bd_pins axi_vdma_0/m_axis_mm2s_aclk] [get_bd_pins axi_vdma_0/s_axis_s2mm_aclk] [get_bd_pins axis_subset_converter_0/aclk] [get_bd_pins axis_subset_converter_1/aclk] [get_bd_pins processing_system7_0/FCLK_CLK1] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins rst_processing_system7_0_142M/slowest_sync_clk] [get_bd_pins v_axi4s_vid_out_0/aclk] [get_bd_pins v_rgb2ycrcb_0/aclk] [get_bd_pins v_vid_in_axi4s_0/aclk] connect_bd_net -net processing_system7_0_FCLK_CLK2 [get_bd_pins proc_sys_reset_2/slowest_sync_clk] [get_bd_pins processing_system7_0/FCLK_CLK2] connect_bd_net -net processing_system7_0_FCLK_CLK3 [get_bd_pins proc_sys_reset_3/slowest_sync_clk] [get_bd_pins processing_system7_0/FCLK_CLK3] - connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins proc_sys_reset_2/ext_reset_in] [get_bd_pins proc_sys_reset_3/ext_reset_in] [get_bd_pins proc_sys_reset_sysclk/ext_reset_in] [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_processing_system7_0_100M/ext_reset_in] [get_bd_pins rst_processing_system7_0_142M/ext_reset_in] + connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins proc_sys_reset_2/ext_reset_in] [get_bd_pins proc_sys_reset_3/ext_reset_in] [get_bd_pins proc_sys_reset_sysclk/ext_reset_in] [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_processing_system7_0_100M/ext_reset_in] [get_bd_pins rst_processing_system7_0_142M/ext_reset_in] connect_bd_net -net processing_system7_0_SPI0_SS1_O [get_bd_pins processing_system7_0/SPI0_SS1_O] [get_bd_pins xlconcat_1/In0] connect_bd_net -net processing_system7_0_SPI0_SS2_O [get_bd_pins processing_system7_0/SPI0_SS2_O] [get_bd_pins xlconcat_1/In1] connect_bd_net -net rst_processing_system7_0_100M_interconnect_aresetn [get_bd_pins processing_system7_0_axi_periph/ARESETN] [get_bd_pins rst_processing_system7_0_100M/interconnect_aresetn] - connect_bd_net -net rst_processing_system7_0_100M_peripheral_aresetn [get_bd_pins axi_dynclk_0/s00_axi_aresetn] [get_bd_pins axi_gpio_hdmi/s_axi_aresetn] [get_bd_pins axi_gpio_led/s_axi_aresetn] [get_bd_pins axi_gpio_shield_1/s_axi_aresetn] [get_bd_pins axi_gpio_shield_2/s_axi_aresetn] [get_bd_pins axi_gpio_sw/s_axi_aresetn] [get_bd_pins axi_vdma_0/axi_resetn] [get_bd_pins processing_system7_0_axi_periph/M00_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M01_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M02_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M03_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M04_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M05_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M06_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M07_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M08_ARESETN] [get_bd_pins processing_system7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_processing_system7_0_100M/peripheral_aresetn] [get_bd_pins v_tc_0/s_axi_aresetn] [get_bd_pins xadc_wiz_0/s_axi_aresetn] + connect_bd_net -net rst_processing_system7_0_100M_peripheral_aresetn [get_bd_pins axi_dynclk_0/s00_axi_aresetn] [get_bd_pins axi_gpio_hdmi/s_axi_aresetn] [get_bd_pins axi_gpio_led/s_axi_aresetn] [get_bd_pins axi_gpio_shield_1/s_axi_aresetn] [get_bd_pins axi_gpio_shield_2/s_axi_aresetn] [get_bd_pins axi_gpio_sw/s_axi_aresetn] [get_bd_pins axi_gpio_video/s_axi_aresetn] [get_bd_pins axi_vdma_0/axi_resetn] [get_bd_pins dvi2rgb_0/aRst_n] [get_bd_pins processing_system7_0_axi_periph/M00_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M01_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M02_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M03_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M04_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M05_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M06_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M07_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M08_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M09_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M10_ARESETN] [get_bd_pins processing_system7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_processing_system7_0_100M/peripheral_aresetn] [get_bd_pins v_tc_0/s_axi_aresetn] [get_bd_pins v_tc_1/s_axi_aresetn] [get_bd_pins xadc_wiz_0/s_axi_aresetn] connect_bd_net -net rst_processing_system7_0_142M_interconnect_aresetn [get_bd_pins axi_mem_intercon/ARESETN] [get_bd_pins rst_processing_system7_0_142M/interconnect_aresetn] - connect_bd_net -net rst_processing_system7_0_142M_peripheral_aresetn [get_bd_pins axi_mem_intercon/M00_ARESETN] [get_bd_pins axi_mem_intercon/S00_ARESETN] [get_bd_pins rst_processing_system7_0_142M/peripheral_aresetn] + connect_bd_net -net rst_processing_system7_0_142M_peripheral_aresetn [get_bd_pins axi_mem_intercon/M00_ARESETN] [get_bd_pins axi_mem_intercon/S00_ARESETN] [get_bd_pins axi_mem_intercon/S01_ARESETN] [get_bd_pins rst_processing_system7_0_142M/peripheral_aresetn] connect_bd_net -net sys_clock_1 [get_bd_ports sys_clock] [get_bd_pins clk_wiz_0/clk_in1] connect_bd_net -net v_axi4s_vid_out_0_vtg_ce [get_bd_pins v_axi4s_vid_out_0/vtg_ce] [get_bd_pins v_tc_0/gen_clken] connect_bd_net -net v_tc_0_irq [get_bd_pins v_tc_0/irq] [get_bd_pins xlconcat_0/In2] + connect_bd_net -net v_tc_1_irq [get_bd_pins v_tc_1/irq] [get_bd_pins xlconcat_0/In5] connect_bd_net -net xadc_wiz_0_ip2intc_irpt [get_bd_pins xadc_wiz_0/ip2intc_irpt] [get_bd_pins xlconcat_0/In4] connect_bd_net -net xlconcat_0_dout [get_bd_pins processing_system7_0/IRQ_F2P] [get_bd_pins xlconcat_0/dout] - connect_bd_net -net xlconstant_0_dout [get_bd_pins axis_subset_converter_0/aresetn] [get_bd_pins xlconstant_0/dout] + connect_bd_net -net xlconstant_0_dout [get_bd_pins axis_subset_converter_0/aresetn] [get_bd_pins axis_subset_converter_1/aresetn] [get_bd_pins xlconstant_0/dout] # Create address segments create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces axi_vdma_0/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces axi_vdma_0/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM create_bd_addr_seg -range 0x00010000 -offset 0x43C10000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_dynclk_0/s00_axi/reg0] SEG_axi_dynclk_0_reg0 create_bd_addr_seg -range 0x00010000 -offset 0x41200000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_sw/S_AXI/Reg] SEG_axi_gpio_0_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x41250000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_video/S_AXI/Reg] SEG_axi_gpio_0_Reg1 create_bd_addr_seg -range 0x00010000 -offset 0x41210000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_shield_1/S_AXI/Reg] SEG_axi_gpio_1_Reg create_bd_addr_seg -range 0x00010000 -offset 0x41220000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_led/S_AXI/Reg] SEG_axi_gpio_2_Reg create_bd_addr_seg -range 0x00010000 -offset 0x41230000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_hdmi/S_AXI/Reg] SEG_axi_gpio_hdmi_Reg create_bd_addr_seg -range 0x00010000 -offset 0x41240000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_shield_2/S_AXI/Reg] SEG_axi_gpio_shield_2_Reg create_bd_addr_seg -range 0x00010000 -offset 0x43000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_vdma_0/S_AXI_LITE/Reg] SEG_axi_vdma_0_Reg create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs v_tc_0/ctrl/Reg] SEG_v_tc_0_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x43C30000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs v_tc_1/ctrl/Reg] SEG_v_tc_1_Reg create_bd_addr_seg -range 0x00010000 -offset 0x43C20000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs xadc_wiz_0/s_axi_lite/Reg] SEG_xadc_wiz_0_Reg # Perform GUI Layout regenerate_bd_layout -layout_string { + DisplayTieOff: "1", guistr: "# # String gsaved with Nlview 6.6.5b 2016-09-06 bk=1.3687 VDI=39 GEI=35 GUI=JA:1.6 # -string -flagsOSRD -preplace port btns_4bits -pg 1 -y 810 -defaultsOSRD -preplace port DDR -pg 1 -y 930 -defaultsOSRD -preplace port Vp_Vn -pg 1 -y 1250 -defaultsOSRD -preplace port shield_dp26_dp41 -pg 1 -y 700 -defaultsOSRD -preplace port TMDS -pg 1 -y 110 -defaultsOSRD -preplace port RGBLED -pg 1 -y 910 -defaultsOSRD -preplace port shield_SPI -pg 1 -y 1010 -defaultsOSRD -preplace port Vaux0 -pg 1 -y 1270 -defaultsOSRD -preplace port HDMI_HPD -pg 1 -y 350 -defaultsOSRD -preplace port Vaux1 -pg 1 -y 1290 -defaultsOSRD -preplace port sys_clock -pg 1 -y 1500 -defaultsOSRD -preplace port shield_IIC -pg 1 -y 990 -defaultsOSRD -preplace port leds_4bits -pg 1 -y 240 -defaultsOSRD -preplace port shield_dp0_dp13 -pg 1 -y 550 -defaultsOSRD -preplace port Vaux12 -pg 1 -y 1390 -defaultsOSRD -preplace port Vaux5 -pg 1 -y 1310 -defaultsOSRD -preplace port HDMI_DDC -pg 1 -y 970 -defaultsOSRD -preplace port FIXED_IO -pg 1 -y 950 -defaultsOSRD -preplace port sws_2bits -pg 1 -y 830 -defaultsOSRD -preplace port Vaux13 -pg 1 -y 1410 -defaultsOSRD -preplace port Vaux6 -pg 1 -y 1330 -defaultsOSRD -preplace port Vaux15 -pg 1 -y 1430 -defaultsOSRD -preplace port Vaux8 -pg 1 -y 1350 -defaultsOSRD -preplace port Vaux9 -pg 1 -y 1370 -defaultsOSRD -preplace inst v_axi4s_vid_out_0 -pg 1 -lvl 9 -y 390 -defaultsOSRD -preplace inst v_tc_0 -pg 1 -lvl 8 -y 370 -defaultsOSRD -preplace inst axi_vdma_0 -pg 1 -lvl 2 -y 850 -defaultsOSRD -preplace inst xlconstant_0 -pg 1 -lvl 7 -y 640 -defaultsOSRD -preplace inst rst_processing_system7_0_100M -pg 1 -lvl 1 -y 550 -defaultsOSRD -preplace inst xadc_wiz_0 -pg 1 -lvl 6 -y 1350 -defaultsOSRD -preplace inst axi_gpio_sw -pg 1 -lvl 10 -y 830 -defaultsOSRD -preplace inst xlconcat_0 -pg 1 -lvl 3 -y 720 -defaultsOSRD -preplace inst axi_gpio_led -pg 1 -lvl 10 -y 240 -defaultsOSRD -preplace inst xlconcat_1 -pg 1 -lvl 5 -y 1080 -defaultsOSRD -preplace inst rgb2dvi_0 -pg 1 -lvl 10 -y 110 -defaultsOSRD -preplace inst axi_gpio_hdmi -pg 1 -lvl 10 -y 360 -defaultsOSRD -preplace inst proc_sys_reset_2 -pg 1 -lvl 5 -y 1520 -defaultsOSRD -preplace inst axis_subset_converter_0 -pg 1 -lvl 8 -y 620 -defaultsOSRD -preplace inst axi_dynclk_0 -pg 1 -lvl 6 -y 360 -defaultsOSRD -preplace inst proc_sys_reset_3 -pg 1 -lvl 5 -y 1680 -defaultsOSRD -preplace inst clk_wiz_0 -pg 1 -lvl 1 -y 1500 -defaultsOSRD -preplace inst axi_gpio_shield_1 -pg 1 -lvl 10 -y 560 -defaultsOSRD -preplace inst proc_sys_reset_sysclk -pg 1 -lvl 2 -y 1530 -defaultsOSRD -preplace inst rst_processing_system7_0_142M -pg 1 -lvl 2 -y 1030 -defaultsOSRD -preplace inst axi_mem_intercon -pg 1 -lvl 3 -y 1000 -defaultsOSRD -preplace inst axi_gpio_shield_2 -pg 1 -lvl 10 -y 710 -defaultsOSRD -preplace inst processing_system7_0_axi_periph -pg 1 -lvl 5 -y 270 -defaultsOSRD -preplace inst processing_system7_0 -pg 1 -lvl 4 -y 1050 -defaultsOSRD -preplace netloc axi_gpio_2_GPIO 1 10 1 NJ -preplace netloc Vaux5_1 1 0 6 NJ 1310 NJ 1310 NJ 1310 NJ 1310 NJ 1310 NJ -preplace netloc axi_vdma_0_M_AXI_MM2S 1 2 1 710 -preplace netloc processing_system7_0_axi_periph_M08_AXI 1 5 5 1860 690 NJ 690 NJ 690 NJ 690 NJ -preplace netloc processing_system7_0_FIXED_IO 1 4 7 NJ 950 NJ 950 NJ 950 NJ 950 NJ 950 NJ 950 NJ +preplace port btns_4bits -pg 1 -y 1540 -defaultsOSRD +preplace port DDR -pg 1 -y 700 -defaultsOSRD +preplace port Vp_Vn -pg 1 -y 1480 -defaultsOSRD +preplace port shield_dp26_dp41 -pg 1 -y 1050 -defaultsOSRD +preplace port TMDS -pg 1 -y 330 -defaultsOSRD +preplace port RGBLED -pg 1 -y 660 -defaultsOSRD +preplace port shield_SPI -pg 1 -y 560 -defaultsOSRD +preplace port Vaux0 -pg 1 -y 1660 -defaultsOSRD +preplace port HDMI_HPD -pg 1 -y 1430 -defaultsOSRD +preplace port Vaux1 -pg 1 -y 1680 -defaultsOSRD +preplace port sys_clock -pg 1 -y 1560 -defaultsOSRD +preplace port shield_IIC -pg 1 -y 740 -defaultsOSRD +preplace port leds_4bits -pg 1 -y 930 -defaultsOSRD +preplace port DDC_In -pg 1 -y 1340 -defaultsOSRD +preplace port shield_dp0_dp13 -pg 1 -y 810 -defaultsOSRD +preplace port Vaux12 -pg 1 -y 1780 -defaultsOSRD +preplace port Vaux5 -pg 1 -y 1700 -defaultsOSRD +preplace port HDMI_DDC -pg 1 -y 720 -defaultsOSRD +preplace port FIXED_IO -pg 1 -y 680 -defaultsOSRD +preplace port sws_2bits -pg 1 -y 1560 -defaultsOSRD +preplace port Vaux13 -pg 1 -y 1800 -defaultsOSRD +preplace port Vaux6 -pg 1 -y 1720 -defaultsOSRD +preplace port Vaux15 -pg 1 -y 1820 -defaultsOSRD +preplace port Vaux8 -pg 1 -y 1740 -defaultsOSRD +preplace port hdmi_in_hpd -pg 1 -y 1230 -defaultsOSRD +preplace port TMDS_In -pg 1 -y 1360 -defaultsOSRD +preplace port Vaux9 -pg 1 -y 1760 -defaultsOSRD +preplace inst v_axi4s_vid_out_0 -pg 1 -lvl 12 -y 570 -defaultsOSRD +preplace inst v_tc_0 -pg 1 -lvl 11 -y 560 -defaultsOSRD +preplace inst axi_vdma_0 -pg 1 -lvl 6 -y 1060 -defaultsOSRD +preplace inst v_tc_1 -pg 1 -lvl 10 -y 1090 -defaultsOSRD +preplace inst xlconstant_0 -pg 1 -lvl 4 -y 800 -defaultsOSRD +preplace inst rst_processing_system7_0_100M -pg 1 -lvl 1 -y 1270 -defaultsOSRD +preplace inst xadc_wiz_0 -pg 1 -lvl 10 -y 1740 -defaultsOSRD +preplace inst axi_gpio_sw -pg 1 -lvl 13 -y 1560 -defaultsOSRD +preplace inst proc_sys_reset_0 -pg 1 -lvl 2 -y 1190 -defaultsOSRD +preplace inst xlconcat_0 -pg 1 -lvl 7 -y 1170 -defaultsOSRD +preplace inst axi_gpio_led -pg 1 -lvl 13 -y 930 -defaultsOSRD +preplace inst xlconcat_1 -pg 1 -lvl 9 -y 760 -defaultsOSRD +preplace inst rgb2dvi_0 -pg 1 -lvl 13 -y 330 -defaultsOSRD +preplace inst axi_gpio_hdmi -pg 1 -lvl 13 -y 1440 -defaultsOSRD +preplace inst axi_gpio_video -pg 1 -lvl 13 -y 1260 -defaultsOSRD +preplace inst proc_sys_reset_2 -pg 1 -lvl 9 -y 950 -defaultsOSRD +preplace inst axis_subset_converter_0 -pg 1 -lvl 11 -y 990 -defaultsOSRD +preplace inst axi_dynclk_0 -pg 1 -lvl 10 -y 340 -defaultsOSRD +preplace inst axis_subset_converter_1 -pg 1 -lvl 5 -y 780 -defaultsOSRD +preplace inst v_vid_in_axi4s_0 -pg 1 -lvl 3 -y 880 -defaultsOSRD +preplace inst proc_sys_reset_3 -pg 1 -lvl 9 -y 1460 -defaultsOSRD +preplace inst v_rgb2ycrcb_0 -pg 1 -lvl 4 -y 950 -defaultsOSRD +preplace inst clk_wiz_0 -pg 1 -lvl 1 -y 1550 -defaultsOSRD +preplace inst axi_gpio_shield_1 -pg 1 -lvl 13 -y 810 -defaultsOSRD +preplace inst dvi2rgb_0 -pg 1 -lvl 2 -y 1390 -defaultsOSRD +preplace inst proc_sys_reset_sysclk -pg 1 -lvl 2 -y 1570 -defaultsOSRD +preplace inst rst_processing_system7_0_142M -pg 1 -lvl 6 -y 750 -defaultsOSRD +preplace inst axi_mem_intercon -pg 1 -lvl 7 -y 810 -defaultsOSRD +preplace inst axi_gpio_shield_2 -pg 1 -lvl 13 -y 1050 -defaultsOSRD +preplace inst processing_system7_0_axi_periph -pg 1 -lvl 9 -y 310 -defaultsOSRD +preplace inst processing_system7_0 -pg 1 -lvl 8 -y 760 -defaultsOSRD +preplace netloc axi_gpio_2_GPIO 1 13 1 NJ +preplace netloc Vaux5_1 1 0 10 NJ 1700 NJ 1700 NJ 1700 NJ 1700 NJ 1700 NJ 1700 NJ 1700 NJ 1700 NJ 1700 NJ +preplace netloc axi_vdma_0_M_AXI_MM2S 1 6 1 1960 +preplace netloc axi_gpio_video_GPIO 1 13 1 NJ +preplace netloc processing_system7_0_axi_periph_M08_AXI 1 9 4 3200 420 NJ 420 NJ 420 4130J +preplace netloc processing_system7_0_FIXED_IO 1 8 6 NJ 660 NJ 660 3550J 700 NJ 700 4140J 680 NJ +preplace netloc axi_vdma_0_M_AXI_S2MM 1 6 1 1980 preplace netloc sys_clock_1 1 0 1 NJ -preplace netloc processing_system7_0_SPI0_SS2_O 1 4 1 1520 -preplace netloc axi_vdma_0_M_AXIS_MM2S 1 2 6 700J 590 NJ 590 NJ 590 NJ 590 NJ 590 2280 -preplace netloc xlconcat_0_dout 1 3 1 1050 -preplace netloc v_tc_0_vtiming_out 1 8 1 2600 -preplace netloc processing_system7_0_GPIO_0 1 4 7 NJ 910 NJ 910 NJ 910 NJ 910 NJ 910 NJ 910 NJ -preplace netloc axi_gpio_shield_1_ip2intc_irpt 1 2 9 760 560 NJ 560 NJ 560 NJ 560 NJ 560 2340J 540 NJ 540 2880J 470 3190 -preplace netloc axi_gpio_0_GPIO 1 10 1 NJ -preplace netloc processing_system7_0_axi_periph_M06_AXI 1 5 5 1870J 230 NJ 230 NJ 230 NJ 230 2890 -preplace netloc processing_system7_0_DDR 1 4 7 NJ 930 NJ 930 NJ 930 NJ 930 NJ 930 NJ 930 NJ -preplace netloc axi_gpio_0_GPIO2 1 10 1 NJ -preplace netloc axi_gpio_shield_2_GPIO 1 10 1 NJ -preplace netloc Vaux12_1 1 0 6 NJ 1390 NJ 1390 NJ 1390 NJ 1390 NJ 1390 NJ -preplace netloc Vaux15_1 1 0 6 NJ 1430 NJ 1430 NJ 1430 NJ 1430 NJ 1430 NJ -preplace netloc processing_system7_0_axi_periph_M05_AXI 1 5 1 1890 -preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 5 20 1660 360 1660 NJ 1660 NJ 1660 1490 -preplace netloc rst_processing_system7_0_142M_peripheral_aresetn 1 2 1 780 -preplace netloc processing_system7_0_axi_periph_M02_AXI 1 5 5 1850J 220 NJ 220 NJ 220 NJ 220 N -preplace netloc processing_system7_0_axi_periph_M03_AXI 1 1 5 370 610 NJ 610 NJ 610 NJ 610 1850 -preplace netloc Vaux13_1 1 0 6 NJ 1410 NJ 1410 NJ 1410 NJ 1410 NJ 1410 NJ -preplace netloc axi_gpio_0_ip2intc_irpt 1 2 9 750 850 NJ 850 NJ 850 NJ 850 NJ 850 NJ 850 NJ 850 2930J 490 3170 -preplace netloc processing_system7_0_axi_periph_M07_AXI 1 5 1 1870 -preplace netloc axi_gpio_hdmi_ip2intc_irpt 1 2 9 750 550 NJ 550 NJ 550 NJ 550 NJ 550 NJ 550 NJ 550 2870J 450 3190 -preplace netloc axi_vdma_0_mm2s_introut 1 2 1 720 -preplace netloc processing_system7_0_IIC_0 1 4 7 NJ 970 NJ 970 NJ 970 NJ 970 NJ 970 NJ 970 NJ -preplace netloc Vp_Vn_1 1 0 6 NJ 1250 NJ 1250 NJ 1250 NJ 1250 NJ 1250 NJ -preplace netloc processing_system7_0_axi_periph_M01_AXI 1 5 5 N 210 NJ 210 NJ 210 NJ 210 2900J -preplace netloc processing_system7_0_IIC_1 1 4 7 NJ 990 NJ 990 NJ 990 NJ 990 NJ 990 NJ 990 NJ -preplace netloc Vaux0_1 1 0 6 NJ 1270 NJ 1270 NJ 1270 NJ 1270 NJ 1270 NJ -preplace netloc processing_system7_0_SPI_0 1 4 7 NJ 1010 NJ 1010 NJ 1010 NJ 1010 NJ 1010 NJ 1010 NJ -preplace netloc processing_system7_0_FCLK_CLK0 1 0 10 10 760 350 760 740J 860 1070 860 1510 860 1880 860 NJ 860 2320 860 NJ 860 2920 -preplace netloc axi_dynclk_0_PXL_CLK_O 1 6 4 NJ 340 2290 140 2620 120 NJ -preplace netloc processing_system7_0_FCLK_CLK1 1 1 8 360 580 730 580 1080 580 1500 580 NJ 580 NJ 580 2310 240 2610J -preplace netloc processing_system7_0_FCLK_CLK2 1 4 1 1520 -preplace netloc rst_processing_system7_0_100M_interconnect_aresetn 1 1 4 360J 90 NJ 90 NJ 90 N -preplace netloc processing_system7_0_axi_periph_M00_AXI 1 5 5 NJ 190 NJ 190 NJ 190 NJ 190 2910 -preplace netloc clk_wiz_0_locked 1 1 1 340 -preplace netloc processing_system7_0_FCLK_CLK3 1 4 1 1500 -preplace netloc Vaux8_1 1 0 6 NJ 1350 NJ 1350 NJ 1350 NJ 1350 NJ 1350 NJ -preplace netloc v_tc_0_irq 1 2 7 780 830 NJ 830 NJ 830 NJ 830 NJ 830 NJ 830 2600 -preplace netloc xadc_wiz_0_ip2intc_irpt 1 2 5 790 840 NJ 840 NJ 840 NJ 840 2150 -preplace netloc rst_processing_system7_0_142M_interconnect_aresetn 1 2 1 760 -preplace netloc axi_dynclk_0_LOCKED_O 1 6 4 2150 100 NJ 100 NJ 100 NJ -preplace netloc Vaux6_1 1 0 6 NJ 1330 NJ 1330 NJ 1330 NJ 1330 NJ 1330 NJ -preplace netloc processing_system7_0_SPI0_SS1_O 1 4 1 1530 -preplace netloc axi_gpio_hdmi_GPIO 1 10 1 NJ -preplace netloc v_axi4s_vid_out_0_vtg_ce 1 7 3 2340 150 NJ 150 2870 +preplace netloc processing_system7_0_SPI0_SS2_O 1 8 1 2750 +preplace netloc axi_vdma_0_s2mm_introut 1 6 1 1960 +preplace netloc v_vid_in_axi4s_0_video_out 1 3 1 860 +preplace netloc dvi2rgb_0_aPixelClkLckd 1 1 13 250 1310 580 1360 NJ 1360 NJ 1360 NJ 1360 NJ 1360 NJ 1360 NJ 1360 NJ 1360 NJ 1360 NJ 1360 NJ 1360 4470 +preplace netloc axi_vdma_0_M_AXIS_MM2S 1 6 5 NJ 1040 NJ 1040 NJ 1040 3260J 960 3540 +preplace netloc axis_subset_converter_1_M_AXIS 1 5 1 1540 +preplace netloc proc_sys_reset_0_peripheral_reset 1 2 1 600 +preplace netloc xlconcat_0_dout 1 7 1 2330 +preplace netloc v_tc_0_vtiming_out 1 11 1 3850 +preplace netloc processing_system7_0_GPIO_0 1 8 6 2840J 700 3200J 710 NJ 710 NJ 710 NJ 710 4470J +preplace netloc axi_gpio_0_GPIO 1 13 1 NJ +preplace netloc processing_system7_0_axi_periph_M06_AXI 1 9 4 3180 1420 NJ 1420 NJ 1420 NJ +preplace netloc processing_system7_0_DDR 1 8 6 NJ 640 NJ 640 3560J 720 NJ 720 4150J 700 NJ +preplace netloc dvi2rgb_0_DDC 1 2 12 570J 1350 NJ 1350 NJ 1350 NJ 1350 NJ 1350 NJ 1350 NJ 1350 NJ 1350 NJ 1350 NJ 1350 NJ 1350 4480J +preplace netloc axi_gpio_0_GPIO2 1 13 1 NJ +preplace netloc axi_gpio_shield_2_GPIO 1 13 1 NJ +preplace netloc Vaux12_1 1 0 10 NJ 1780 NJ 1780 NJ 1780 NJ 1780 NJ 1780 NJ 1780 NJ 1780 NJ 1780 NJ 1780 NJ +preplace netloc axi_gpio_video_ip2intc_irpt 1 6 8 2030 1340 NJ 1340 NJ 1340 NJ 1340 NJ 1340 NJ 1340 NJ 1340 4460 +preplace netloc v_tc_1_irq 1 6 5 2040 1290 NJ 1290 NJ 1290 NJ 1290 3560 +preplace netloc Vaux15_1 1 0 10 NJ 1820 NJ 1820 NJ 1820 NJ 1820 NJ 1820 NJ 1820 NJ 1820 NJ 1820 NJ 1820 NJ +preplace netloc processing_system7_0_axi_periph_M05_AXI 1 9 1 N +preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 9 -120 540 240 540 NJ 540 NJ 540 NJ 540 1560 540 NJ 540 NJ 540 2780 +preplace netloc rst_processing_system7_0_142M_peripheral_aresetn 1 6 1 1970 +preplace netloc TMDS_1_1 1 0 2 NJ 1360 NJ +preplace netloc processing_system7_0_axi_periph_M10_AXI 1 9 4 3190 1240 NJ 1240 NJ 1240 NJ +preplace netloc proc_sys_reset_0_peripheral_aresetn 1 2 8 NJ 1230 NJ 1230 NJ 1230 1530J 1250 1990J 1020 NJ 1020 2730J 1150 N +preplace netloc processing_system7_0_axi_periph_M02_AXI 1 9 4 N 250 NJ 250 NJ 250 4160J +preplace netloc processing_system7_0_axi_periph_M03_AXI 1 5 5 1570 520 NJ 520 NJ 520 2850J 630 3170 +preplace netloc Vaux13_1 1 0 10 NJ 1800 NJ 1800 NJ 1800 NJ 1800 NJ 1800 NJ 1800 NJ 1800 NJ 1800 NJ 1800 NJ +preplace netloc axi_gpio_0_ip2intc_irpt 1 6 8 2010 1560 NJ 1560 NJ 1560 NJ 1560 NJ 1560 NJ 1560 4120J 1630 4460 +preplace netloc processing_system7_0_axi_periph_M07_AXI 1 9 1 3210 +preplace netloc axi_gpio_hdmi_ip2intc_irpt 1 6 8 2000 1550 NJ 1550 NJ 1550 NJ 1550 NJ 1550 NJ 1550 4130J 1640 4480 +preplace netloc processing_system7_0_axi_periph_M09_AXI 1 9 1 3240 +preplace netloc axi_vdma_0_mm2s_introut 1 6 1 1980 +preplace netloc Vp_Vn_1 1 0 10 NJ 1480 NJ 1480 NJ 1480 NJ 1480 NJ 1480 NJ 1480 NJ 1480 NJ 1480 2740J 1640 NJ +preplace netloc processing_system7_0_IIC_0 1 8 6 2770J 850 NJ 850 NJ 850 NJ 850 4190J 720 NJ +preplace netloc processing_system7_0_IIC_1 1 8 6 2810J 820 NJ 820 NJ 820 NJ 820 4200J 730 4470J +preplace netloc processing_system7_0_axi_periph_M01_AXI 1 9 4 N 230 NJ 230 NJ 230 4180J +preplace netloc dvi2rgb_0_PixelClk 1 1 9 250 1100 610 1400 NJ 1400 NJ 1400 NJ 1400 NJ 1400 NJ 1400 2820J 1050 N +preplace netloc Vaux0_1 1 0 10 NJ 1660 NJ 1660 NJ 1660 NJ 1660 NJ 1660 NJ 1660 NJ 1660 NJ 1660 NJ 1660 NJ +preplace netloc processing_system7_0_SPI_0 1 8 6 2760J 830 3230J 740 NJ 740 NJ 740 NJ 740 4460J +preplace netloc dvi2rgb_0_RGB 1 2 1 590 +preplace netloc processing_system7_0_FCLK_CLK0 1 0 13 -110 1840 NJ 1840 NJ 1840 NJ 1840 NJ 1840 1540 1840 NJ 1840 2320 1840 2800 1840 3220 540 3580 810 NJ 810 4180 +preplace netloc axi_dynclk_0_PXL_CLK_O 1 10 3 3580 320 3860 320 4140J +preplace netloc processing_system7_0_FCLK_CLK1 1 2 10 620 530 870 530 1250 530 1550 530 2000 530 2310 530 2730 840 NJ 840 3570 690 3880J +preplace netloc v_rgb2ycrcb_0_video_out 1 4 1 1270 +preplace netloc processing_system7_0_FCLK_CLK2 1 8 1 2760 +preplace netloc rst_processing_system7_0_100M_interconnect_aresetn 1 1 8 220J 90 NJ 90 NJ 90 NJ 90 NJ 90 NJ 90 NJ 90 N +preplace netloc processing_system7_0_axi_periph_M00_AXI 1 9 4 N 210 NJ 210 NJ 210 4170J +preplace netloc clk_wiz_0_locked 1 1 1 210 +preplace netloc processing_system7_0_FCLK_CLK3 1 8 1 2740 +preplace netloc Vaux8_1 1 0 10 NJ 1740 NJ 1740 NJ 1740 NJ 1740 NJ 1740 NJ 1740 NJ 1740 NJ 1740 NJ 1740 NJ +preplace netloc v_tc_0_irq 1 6 6 2040 560 NJ 560 2820J 860 NJ 860 NJ 860 3850 +preplace netloc xadc_wiz_0_ip2intc_irpt 1 6 5 2020 1310 NJ 1310 NJ 1310 NJ 1310 3560 +preplace netloc rst_processing_system7_0_142M_interconnect_aresetn 1 6 1 1990 +preplace netloc axi_dynclk_0_LOCKED_O 1 10 3 NJ 360 NJ 360 4150 +preplace netloc Vaux6_1 1 0 10 NJ 1720 NJ 1720 NJ 1720 NJ 1720 NJ 1720 NJ 1720 NJ 1720 NJ 1720 NJ 1720 NJ +preplace netloc v_vid_in_axi4s_0_vtiming_out 1 3 7 880J 550 NJ 550 NJ 550 NJ 550 NJ 550 2790J 690 3170 +preplace netloc processing_system7_0_SPI0_SS1_O 1 8 1 2790 +preplace netloc axi_gpio_hdmi_GPIO 1 13 1 NJ +preplace netloc v_axi4s_vid_out_0_vtg_ce 1 10 3 3590 750 NJ 750 4120 preplace netloc clk_wiz_0_clk_out1 1 1 1 N -preplace netloc axi_gpio_1_GPIO 1 10 1 NJ -preplace netloc processing_system7_0_M_AXI_GP0 1 4 1 1490 -preplace netloc xlconstant_0_dout 1 7 1 NJ -preplace netloc Vaux1_1 1 0 6 NJ 1290 NJ 1290 NJ 1290 NJ 1290 NJ 1290 NJ -preplace netloc rgb2dvi_0_TMDS 1 10 1 NJ -preplace netloc axi_mem_intercon_M00_AXI 1 3 1 1060 -preplace netloc axis_subset_converter_0_M_AXIS 1 8 1 2630 -preplace netloc Vaux9_1 1 0 6 NJ 1370 NJ 1370 NJ 1370 NJ 1370 NJ 1370 NJ -preplace netloc axi_gpio_shield_2_ip2intc_irpt 1 2 9 770 570 1090J 720 NJ 720 NJ 720 NJ 720 NJ 720 NJ 720 2950J 480 3180 -preplace netloc processing_system7_0_axi_periph_M04_AXI 1 5 3 NJ 270 NJ 270 2300 -preplace netloc rst_processing_system7_0_100M_peripheral_aresetn 1 1 9 340 600 NJ 600 NJ 600 1530 730 1890 730 NJ 730 2330 730 NJ 730 2940 -preplace netloc axi_dynclk_0_PXL_CLK_5X_O 1 6 4 N 360 2280J 120 2610J 140 NJ -preplace netloc v_axi4s_vid_out_0_vid_io_out 1 9 1 2880 -levelinfo -pg 1 -10 180 540 920 1290 1690 2020 2220 2470 2750 3060 3210 -top 0 -bot 1770 +preplace netloc axi_gpio_1_GPIO 1 13 1 NJ +preplace netloc clk_wiz_0_clk_out2 1 1 1 230 +preplace netloc processing_system7_0_M_AXI_GP0 1 8 1 2740 +preplace netloc xlconstant_0_dout 1 4 7 1260 570 NJ 570 NJ 570 NJ 570 2770J 670 NJ 670 3530J +preplace netloc Vaux1_1 1 0 10 NJ 1680 NJ 1680 NJ 1680 NJ 1680 NJ 1680 NJ 1680 NJ 1680 NJ 1680 NJ 1680 NJ +preplace netloc rgb2dvi_0_TMDS 1 13 1 NJ +preplace netloc axi_mem_intercon_M00_AXI 1 7 1 2300 +preplace netloc axis_subset_converter_0_M_AXIS 1 11 1 3870 +preplace netloc Vaux9_1 1 0 10 NJ 1760 NJ 1760 NJ 1760 NJ 1760 NJ 1760 NJ 1760 NJ 1760 NJ 1760 NJ 1760 NJ +preplace netloc processing_system7_0_axi_periph_M04_AXI 1 9 2 3260 480 NJ +preplace netloc rst_processing_system7_0_100M_peripheral_aresetn 1 1 12 220 1860 NJ 1860 NJ 1860 NJ 1860 1560 1860 NJ 1860 NJ 1860 2830 1860 3250 620 3540 830 NJ 830 4140 +preplace netloc axi_dynclk_0_PXL_CLK_5X_O 1 10 3 NJ 340 NJ 340 4130 +preplace netloc v_axi4s_vid_out_0_vid_io_out 1 12 1 4120 +levelinfo -pg 1 -140 50 410 740 1150 1400 1770 2170 2530 3010 3400 3720 4000 4330 4510 -top 0 -bot 1910 ", } diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0.dcp b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0.dcp index d534d23..892e211 100644 Binary files a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0.dcp and b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0.dcp differ diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0.xci b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0.xci index 3dd47e9..a82cfa4 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0.xci +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0.xci @@ -12,7 +12,7 @@ S_AXI:M_AXI ARESETN Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 - 142857132 + 118181816 0.000 32 0 @@ -20,25 +20,25 @@ 0 Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 64 - 142857132 - 0 + 118181816 + 1 0 0 0 - 0 + 1 0 0 1 - 0 - 0 + 1 + 1 16 - 2 + 8 1 8 1 0.000 AXI3 - READ_ONLY + READ_WRITE 0 0 0 @@ -52,25 +52,25 @@ 0 Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 64 - 142857132 - 0 - 0 - 0 - 0 - 0 - 0 - 0 + 118181816 + 1 + 1 + 1 + 1 + 1 + 1 + 1 1 - 0 - 0 - 16 - 2 + 1 + 1 + 32 + 8 1 8 1 0.000 AXI4 - READ_ONLY + READ_WRITE 0 0 0 @@ -85,10 +85,10 @@ 1 1 0 - 0 + 1 1 zynq - 1 + 0 1 0 2 @@ -98,9 +98,9 @@ 0 Arty_Z7_20_auto_pc_0 64 - 0 + 1 AXI3 - READ_ONLY + READ_WRITE 0 AXI4 2 @@ -116,7 +116,7 @@ TRUE TRUE - e193e54cc8136853 + 9e235cd5cbe1aa68 IP_Integrator 11 TRUE @@ -132,65 +132,51 @@ - - - - + - + - + - + - - + - - - - - - - - - - + + + + + + + - - - + + + - - - - + + - - - - - diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0.xml b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0.xml index 8e64ce0..5b4cf1c 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0.xml +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0.xml @@ -384,11 +384,11 @@ FREQ_HZ - 142857132 + 118181816 ID_WIDTH - 0 + 1 ADDR_WIDTH @@ -416,39 +416,39 @@ READ_WRITE_MODE - READ_ONLY + READ_WRITE HAS_BURST - 0 + 1 HAS_LOCK - 0 + 1 HAS_PROT - 0 + 1 HAS_CACHE - 0 + 1 HAS_QOS - 0 + 1 HAS_REGION - 0 + 1 HAS_WSTRB - 0 + 1 HAS_BRESP - 0 + 1 HAS_RRESP @@ -460,7 +460,7 @@ NUM_READ_OUTSTANDING - 2 + 8 NUM_WRITE_OUTSTANDING @@ -468,7 +468,7 @@ MAX_BURST_LENGTH - 16 + 32 PHASE @@ -875,11 +875,11 @@ FREQ_HZ - 142857132 + 118181816 ID_WIDTH - 0 + 1 ADDR_WIDTH @@ -907,7 +907,7 @@ READ_WRITE_MODE - READ_ONLY + READ_WRITE HAS_BURST @@ -919,7 +919,7 @@ HAS_PROT - 0 + 1 HAS_CACHE @@ -935,11 +935,11 @@ HAS_WSTRB - 0 + 1 HAS_BRESP - 0 + 1 HAS_RRESP @@ -951,7 +951,7 @@ NUM_READ_OUTSTANDING - 2 + 8 NUM_WRITE_OUTSTANDING @@ -1008,7 +1008,7 @@ FREQ_HZ aclk frequency aclk frequency - 142857132 + 118181816 PHASE @@ -1087,11 +1087,11 @@ GENtimestamp - Mon Feb 27 18:05:27 UTC 2017 + Mon Mar 06 19:44:20 UTC 2017 boundaryCRC - 14da0d00 + 8295c24a boundaryCRCversion @@ -1099,7 +1099,7 @@ customizationCRC - 59a9d58a + b94d0c33 customizationCRCversion @@ -1117,11 +1117,11 @@ GENtimestamp - Mon Feb 27 18:05:27 UTC 2017 + Mon Mar 06 19:44:20 UTC 2017 boundaryCRC - 14da0d00 + 8295c24a boundaryCRCversion @@ -1129,7 +1129,7 @@ customizationCRC - 59a9d58a + b94d0c33 customizationCRCversion @@ -1148,11 +1148,11 @@ GENtimestamp - Mon Feb 27 18:05:27 UTC 2017 + Mon Mar 06 19:44:20 UTC 2017 boundaryCRC - 14da0d00 + 8295c24a boundaryCRCversion @@ -1160,7 +1160,7 @@ customizationCRC - 59a9d58a + b94d0c33 customizationCRCversion @@ -1194,11 +1194,11 @@ GENtimestamp - Mon Feb 27 18:05:27 UTC 2017 + Mon Mar 06 19:44:19 UTC 2017 boundaryCRC - 14da0d00 + 8295c24a boundaryCRCversion @@ -1206,7 +1206,7 @@ customizationCRC - 08e97a9b + c7172c46 customizationCRCversion @@ -1225,11 +1225,11 @@ GENtimestamp - Mon Feb 27 18:05:27 UTC 2017 + Mon Mar 06 19:44:20 UTC 2017 boundaryCRC - 14da0d00 + 8295c24a boundaryCRCversion @@ -1237,7 +1237,7 @@ customizationCRC - 08e97a9b + c7172c46 customizationCRCversion @@ -1255,11 +1255,11 @@ GENtimestamp - Mon Feb 27 18:05:33 UTC 2017 + Mon Mar 06 19:44:25 UTC 2017 boundaryCRC - 14da0d00 + 8295c24a boundaryCRCversion @@ -1267,7 +1267,7 @@ customizationCRC - 59a9d58a + b94d0c33 customizationCRCversion @@ -1325,7 +1325,7 @@ - false + true @@ -1352,7 +1352,7 @@ - false + true @@ -1379,7 +1379,7 @@ - false + true @@ -1406,7 +1406,7 @@ - false + true @@ -1433,7 +1433,7 @@ - false + true @@ -1460,7 +1460,7 @@ - false + true @@ -1487,7 +1487,7 @@ - false + true @@ -1514,7 +1514,7 @@ - false + true @@ -1541,7 +1541,7 @@ - false + true @@ -1568,7 +1568,7 @@ - false + true @@ -1618,7 +1618,7 @@ - false + true @@ -1638,7 +1638,7 @@ - false + true @@ -1692,7 +1692,7 @@ - false + true @@ -1719,7 +1719,7 @@ - false + true @@ -1742,7 +1742,7 @@ - false + true @@ -1792,7 +1792,7 @@ - false + true @@ -1812,7 +1812,7 @@ - false + true @@ -1836,7 +1836,7 @@ - false + true @@ -1860,7 +1860,7 @@ - false + true @@ -1904,7 +1904,7 @@ - false + true @@ -1927,7 +1927,7 @@ - false + true @@ -1954,7 +1954,7 @@ - false + true @@ -2291,7 +2291,7 @@ - false + true @@ -2450,7 +2450,7 @@ - false + true @@ -2474,7 +2474,7 @@ - false + true @@ -2498,7 +2498,7 @@ - false + true @@ -2522,7 +2522,7 @@ - false + true @@ -2546,7 +2546,7 @@ - false + true @@ -2570,7 +2570,7 @@ - false + true @@ -2594,7 +2594,7 @@ - false + true @@ -2618,7 +2618,7 @@ - false + true @@ -2666,7 +2666,7 @@ - false + true @@ -2710,7 +2710,7 @@ - false + true @@ -2733,7 +2733,7 @@ - false + true @@ -2757,7 +2757,7 @@ - false + true @@ -2781,7 +2781,7 @@ - false + true @@ -2805,7 +2805,7 @@ - false + true @@ -2825,7 +2825,7 @@ - false + true @@ -2869,7 +2869,7 @@ - false + true @@ -2892,7 +2892,7 @@ - false + true @@ -2919,7 +2919,7 @@ - false + true @@ -2946,7 +2946,7 @@ - false + true @@ -2996,7 +2996,7 @@ - false + true @@ -3016,7 +3016,7 @@ - false + true @@ -3040,7 +3040,7 @@ - false + true @@ -3350,7 +3350,7 @@ - false + true @@ -3518,7 +3518,7 @@ C_IGNORE_ID - 1 + 0 C_AXI_ID_WIDTH @@ -3534,7 +3534,7 @@ C_AXI_SUPPORTS_WRITE - 0 + 1 C_AXI_SUPPORTS_READ @@ -3902,7 +3902,7 @@ READ_WRITE_MODE READ_WRITE Mode - READ_ONLY + READ_WRITE TRANSLATION_MODE @@ -3922,7 +3922,7 @@ ID_WIDTH ID Width - 0 + 1 AWUSER_WIDTH @@ -3962,65 +3962,51 @@ - - - - + - + - + - + - - + - - - - - - - - - - + + + + + + + - - - + + + - - - - + + - - - - - diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0_ooc.xdc b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0_ooc.xdc index ab4e818..6259de8 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0_ooc.xdc +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0_ooc.xdc @@ -52,6 +52,6 @@ # ######################################################### -create_clock -period 7 -name aclk [get_ports aclk] +create_clock -period 8.462 -name aclk [get_ports aclk] diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0_sim_netlist.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0_sim_netlist.v index ed3ff10..fc5a5be 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0_sim_netlist.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0_sim_netlist.v @@ -1,7 +1,7 @@ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -// Date : Fri Feb 24 16:07:07 2017 +// Date : Sat Mar 04 18:58:36 2017 // Host : WK73 running 64-bit Service Pack 1 (build 7601) // Command : write_verilog -force -mode funcsim -rename_top Arty_Z7_20_auto_pc_0 -prefix // Arty_Z7_20_auto_pc_0_ Arty_Z7_20_auto_pc_0_sim_netlist.v @@ -17,6 +17,28 @@ module Arty_Z7_20_auto_pc_0 (aclk, aresetn, + s_axi_awid, + s_axi_awaddr, + s_axi_awlen, + s_axi_awsize, + s_axi_awburst, + s_axi_awlock, + s_axi_awcache, + s_axi_awprot, + s_axi_awregion, + s_axi_awqos, + s_axi_awvalid, + s_axi_awready, + s_axi_wdata, + s_axi_wstrb, + s_axi_wlast, + s_axi_wvalid, + s_axi_wready, + s_axi_bid, + s_axi_bresp, + s_axi_bvalid, + s_axi_bready, + s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, @@ -28,11 +50,34 @@ module Arty_Z7_20_auto_pc_0 s_axi_arqos, s_axi_arvalid, s_axi_arready, + s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, + m_axi_awid, + m_axi_awaddr, + m_axi_awlen, + m_axi_awsize, + m_axi_awburst, + m_axi_awlock, + m_axi_awcache, + m_axi_awprot, + m_axi_awqos, + m_axi_awvalid, + m_axi_awready, + m_axi_wid, + m_axi_wdata, + m_axi_wstrb, + m_axi_wlast, + m_axi_wvalid, + m_axi_wready, + m_axi_bid, + m_axi_bresp, + m_axi_bvalid, + m_axi_bready, + m_axi_arid, m_axi_araddr, m_axi_arlen, m_axi_arsize, @@ -43,6 +88,7 @@ module Arty_Z7_20_auto_pc_0 m_axi_arqos, m_axi_arvalid, m_axi_arready, + m_axi_rid, m_axi_rdata, m_axi_rresp, m_axi_rlast, @@ -50,6 +96,28 @@ module Arty_Z7_20_auto_pc_0 m_axi_rready); (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *) input aclk; (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *) input aresetn; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input [0:0]s_axi_awid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [31:0]s_axi_awaddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [7:0]s_axi_awlen; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input [0:0]s_axi_awlock; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *) input [3:0]s_axi_awregion; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *) input [3:0]s_axi_awqos; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [63:0]s_axi_wdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [7:0]s_axi_wstrb; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) output [0:0]s_axi_bid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) input [0:0]s_axi_arid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [31:0]s_axi_araddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [7:0]s_axi_arlen; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize; @@ -61,11 +129,34 @@ module Arty_Z7_20_auto_pc_0 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) input [3:0]s_axi_arqos; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) output [0:0]s_axi_rid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [63:0]s_axi_rdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *) output [0:0]m_axi_awid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output [31:0]m_axi_awaddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *) output [3:0]m_axi_awlen; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *) output [2:0]m_axi_awsize; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *) output [1:0]m_axi_awburst; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *) output [1:0]m_axi_awlock; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *) output [3:0]m_axi_awcache; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output [2:0]m_axi_awprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *) output [3:0]m_axi_awqos; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output m_axi_awvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input m_axi_awready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WID" *) output [0:0]m_axi_wid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output [63:0]m_axi_wdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output [7:0]m_axi_wstrb; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *) output m_axi_wlast; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output m_axi_wvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input m_axi_wready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *) input [0:0]m_axi_bid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input [1:0]m_axi_bresp; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input m_axi_bvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output m_axi_bready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *) output [0:0]m_axi_arid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output [31:0]m_axi_araddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *) output [3:0]m_axi_arlen; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *) output [2:0]m_axi_arsize; @@ -76,6 +167,7 @@ module Arty_Z7_20_auto_pc_0 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *) output [3:0]m_axi_arqos; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output m_axi_arvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input m_axi_arready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *) input [0:0]m_axi_rid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input [63:0]m_axi_rdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]m_axi_rresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *) input m_axi_rlast; @@ -87,6 +179,7 @@ module Arty_Z7_20_auto_pc_0 wire [31:0]m_axi_araddr; wire [1:0]m_axi_arburst; wire [3:0]m_axi_arcache; + wire [0:0]m_axi_arid; wire [3:0]m_axi_arlen; wire [1:0]m_axi_arlock; wire [2:0]m_axi_arprot; @@ -94,14 +187,37 @@ module Arty_Z7_20_auto_pc_0 wire m_axi_arready; wire [2:0]m_axi_arsize; wire m_axi_arvalid; + wire [31:0]m_axi_awaddr; + wire [1:0]m_axi_awburst; + wire [3:0]m_axi_awcache; + wire [0:0]m_axi_awid; + wire [3:0]m_axi_awlen; + wire [1:0]m_axi_awlock; + wire [2:0]m_axi_awprot; + wire [3:0]m_axi_awqos; + wire m_axi_awready; + wire [2:0]m_axi_awsize; + wire m_axi_awvalid; + wire [0:0]m_axi_bid; + wire m_axi_bready; + wire [1:0]m_axi_bresp; + wire m_axi_bvalid; wire [63:0]m_axi_rdata; + wire [0:0]m_axi_rid; wire m_axi_rlast; wire m_axi_rready; wire [1:0]m_axi_rresp; wire m_axi_rvalid; + wire [63:0]m_axi_wdata; + wire [0:0]m_axi_wid; + wire m_axi_wlast; + wire m_axi_wready; + wire [7:0]m_axi_wstrb; + wire m_axi_wvalid; wire [31:0]s_axi_araddr; wire [1:0]s_axi_arburst; wire [3:0]s_axi_arcache; + wire [0:0]s_axi_arid; wire [7:0]s_axi_arlen; wire [0:0]s_axi_arlock; wire [2:0]s_axi_arprot; @@ -110,40 +226,39 @@ module Arty_Z7_20_auto_pc_0 wire [3:0]s_axi_arregion; wire [2:0]s_axi_arsize; wire s_axi_arvalid; + wire [31:0]s_axi_awaddr; + wire [1:0]s_axi_awburst; + wire [3:0]s_axi_awcache; + wire [0:0]s_axi_awid; + wire [7:0]s_axi_awlen; + wire [0:0]s_axi_awlock; + wire [2:0]s_axi_awprot; + wire [3:0]s_axi_awqos; + wire s_axi_awready; + wire [3:0]s_axi_awregion; + wire [2:0]s_axi_awsize; + wire s_axi_awvalid; + wire [0:0]s_axi_bid; + wire s_axi_bready; + wire [1:0]s_axi_bresp; + wire s_axi_bvalid; wire [63:0]s_axi_rdata; + wire [0:0]s_axi_rid; wire s_axi_rlast; wire s_axi_rready; wire [1:0]s_axi_rresp; wire s_axi_rvalid; - wire NLW_inst_m_axi_awvalid_UNCONNECTED; - wire NLW_inst_m_axi_bready_UNCONNECTED; - wire NLW_inst_m_axi_wlast_UNCONNECTED; - wire NLW_inst_m_axi_wvalid_UNCONNECTED; - wire NLW_inst_s_axi_awready_UNCONNECTED; - wire NLW_inst_s_axi_bvalid_UNCONNECTED; - wire NLW_inst_s_axi_wready_UNCONNECTED; - wire [0:0]NLW_inst_m_axi_arid_UNCONNECTED; + wire [63:0]s_axi_wdata; + wire s_axi_wlast; + wire s_axi_wready; + wire [7:0]s_axi_wstrb; + wire s_axi_wvalid; wire [3:0]NLW_inst_m_axi_arregion_UNCONNECTED; wire [0:0]NLW_inst_m_axi_aruser_UNCONNECTED; - wire [31:0]NLW_inst_m_axi_awaddr_UNCONNECTED; - wire [1:0]NLW_inst_m_axi_awburst_UNCONNECTED; - wire [3:0]NLW_inst_m_axi_awcache_UNCONNECTED; - wire [0:0]NLW_inst_m_axi_awid_UNCONNECTED; - wire [3:0]NLW_inst_m_axi_awlen_UNCONNECTED; - wire [1:0]NLW_inst_m_axi_awlock_UNCONNECTED; - wire [2:0]NLW_inst_m_axi_awprot_UNCONNECTED; - wire [3:0]NLW_inst_m_axi_awqos_UNCONNECTED; wire [3:0]NLW_inst_m_axi_awregion_UNCONNECTED; - wire [2:0]NLW_inst_m_axi_awsize_UNCONNECTED; wire [0:0]NLW_inst_m_axi_awuser_UNCONNECTED; - wire [63:0]NLW_inst_m_axi_wdata_UNCONNECTED; - wire [0:0]NLW_inst_m_axi_wid_UNCONNECTED; - wire [7:0]NLW_inst_m_axi_wstrb_UNCONNECTED; wire [0:0]NLW_inst_m_axi_wuser_UNCONNECTED; - wire [0:0]NLW_inst_s_axi_bid_UNCONNECTED; - wire [1:0]NLW_inst_s_axi_bresp_UNCONNECTED; wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED; - wire [0:0]NLW_inst_s_axi_rid_UNCONNECTED; wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED; (* C_AXI_ADDR_WIDTH = "32" *) @@ -155,13 +270,14 @@ module Arty_Z7_20_auto_pc_0 (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_READ = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *) - (* C_AXI_SUPPORTS_WRITE = "0" *) + (* C_AXI_SUPPORTS_WRITE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_FAMILY = "zynq" *) - (* C_IGNORE_ID = "1" *) + (* C_IGNORE_ID = "0" *) (* C_M_AXI_PROTOCOL = "1" *) (* C_S_AXI_PROTOCOL = "0" *) (* C_TRANSLATION_MODE = "2" *) + (* DowngradeIPIdentifiedWarnings = "yes" *) (* P_AXI3 = "1" *) (* P_AXI4 = "0" *) (* P_AXILITE = "2" *) @@ -171,14 +287,13 @@ module Arty_Z7_20_auto_pc_0 (* P_INCR = "2'b01" *) (* P_PROTECTION = "1" *) (* P_SLVERR = "2'b10" *) - (* downgradeipidentifiedwarnings = "yes" *) Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter inst (.aclk(aclk), .aresetn(aresetn), .m_axi_araddr(m_axi_araddr), .m_axi_arburst(m_axi_arburst), .m_axi_arcache(m_axi_arcache), - .m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[0]), + .m_axi_arid(m_axi_arid), .m_axi_arlen(m_axi_arlen), .m_axi_arlock(m_axi_arlock), .m_axi_arprot(m_axi_arprot), @@ -188,42 +303,42 @@ module Arty_Z7_20_auto_pc_0 .m_axi_arsize(m_axi_arsize), .m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[0]), .m_axi_arvalid(m_axi_arvalid), - .m_axi_awaddr(NLW_inst_m_axi_awaddr_UNCONNECTED[31:0]), - .m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[1:0]), - .m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[3:0]), - .m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[0]), - .m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[3:0]), - .m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[1:0]), - .m_axi_awprot(NLW_inst_m_axi_awprot_UNCONNECTED[2:0]), - .m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[3:0]), - .m_axi_awready(1'b0), + .m_axi_awaddr(m_axi_awaddr), + .m_axi_awburst(m_axi_awburst), + .m_axi_awcache(m_axi_awcache), + .m_axi_awid(m_axi_awid), + .m_axi_awlen(m_axi_awlen), + .m_axi_awlock(m_axi_awlock), + .m_axi_awprot(m_axi_awprot), + .m_axi_awqos(m_axi_awqos), + .m_axi_awready(m_axi_awready), .m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[3:0]), - .m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[2:0]), + .m_axi_awsize(m_axi_awsize), .m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[0]), - .m_axi_awvalid(NLW_inst_m_axi_awvalid_UNCONNECTED), - .m_axi_bid(1'b0), - .m_axi_bready(NLW_inst_m_axi_bready_UNCONNECTED), - .m_axi_bresp({1'b0,1'b0}), + .m_axi_awvalid(m_axi_awvalid), + .m_axi_bid(m_axi_bid), + .m_axi_bready(m_axi_bready), + .m_axi_bresp(m_axi_bresp), .m_axi_buser(1'b0), - .m_axi_bvalid(1'b0), + .m_axi_bvalid(m_axi_bvalid), .m_axi_rdata(m_axi_rdata), - .m_axi_rid(1'b0), + .m_axi_rid(m_axi_rid), .m_axi_rlast(m_axi_rlast), .m_axi_rready(m_axi_rready), .m_axi_rresp(m_axi_rresp), .m_axi_ruser(1'b0), .m_axi_rvalid(m_axi_rvalid), - .m_axi_wdata(NLW_inst_m_axi_wdata_UNCONNECTED[63:0]), - .m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[0]), - .m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED), - .m_axi_wready(1'b0), - .m_axi_wstrb(NLW_inst_m_axi_wstrb_UNCONNECTED[7:0]), + .m_axi_wdata(m_axi_wdata), + .m_axi_wid(m_axi_wid), + .m_axi_wlast(m_axi_wlast), + .m_axi_wready(m_axi_wready), + .m_axi_wstrb(m_axi_wstrb), .m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[0]), - .m_axi_wvalid(NLW_inst_m_axi_wvalid_UNCONNECTED), + .m_axi_wvalid(m_axi_wvalid), .s_axi_araddr(s_axi_araddr), .s_axi_arburst(s_axi_arburst), .s_axi_arcache(s_axi_arcache), - .s_axi_arid(1'b0), + .s_axi_arid(s_axi_arid), .s_axi_arlen(s_axi_arlen), .s_axi_arlock(s_axi_arlock), .s_axi_arprot(s_axi_arprot), @@ -233,482 +348,824 @@ module Arty_Z7_20_auto_pc_0 .s_axi_arsize(s_axi_arsize), .s_axi_aruser(1'b0), .s_axi_arvalid(s_axi_arvalid), - .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_awburst({1'b0,1'b1}), - .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}), - .s_axi_awid(1'b0), - .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axi_awlock(1'b0), - .s_axi_awprot({1'b0,1'b0,1'b0}), - .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}), - .s_axi_awready(NLW_inst_s_axi_awready_UNCONNECTED), - .s_axi_awregion({1'b0,1'b0,1'b0,1'b0}), - .s_axi_awsize({1'b0,1'b0,1'b0}), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awburst(s_axi_awburst), + .s_axi_awcache(s_axi_awcache), + .s_axi_awid(s_axi_awid), + .s_axi_awlen(s_axi_awlen), + .s_axi_awlock(s_axi_awlock), + .s_axi_awprot(s_axi_awprot), + .s_axi_awqos(s_axi_awqos), + .s_axi_awready(s_axi_awready), + .s_axi_awregion(s_axi_awregion), + .s_axi_awsize(s_axi_awsize), .s_axi_awuser(1'b0), - .s_axi_awvalid(1'b0), - .s_axi_bid(NLW_inst_s_axi_bid_UNCONNECTED[0]), - .s_axi_bready(1'b0), - .s_axi_bresp(NLW_inst_s_axi_bresp_UNCONNECTED[1:0]), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_bid(s_axi_bid), + .s_axi_bready(s_axi_bready), + .s_axi_bresp(s_axi_bresp), .s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]), - .s_axi_bvalid(NLW_inst_s_axi_bvalid_UNCONNECTED), + .s_axi_bvalid(s_axi_bvalid), .s_axi_rdata(s_axi_rdata), - .s_axi_rid(NLW_inst_s_axi_rid_UNCONNECTED[0]), + .s_axi_rid(s_axi_rid), .s_axi_rlast(s_axi_rlast), .s_axi_rready(s_axi_rready), .s_axi_rresp(s_axi_rresp), .s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]), .s_axi_rvalid(s_axi_rvalid), - .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_wdata(s_axi_wdata), .s_axi_wid(1'b0), - .s_axi_wlast(1'b1), - .s_axi_wready(NLW_inst_s_axi_wready_UNCONNECTED), - .s_axi_wstrb({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), + .s_axi_wlast(s_axi_wlast), + .s_axi_wready(s_axi_wready), + .s_axi_wstrb(s_axi_wstrb), .s_axi_wuser(1'b0), - .s_axi_wvalid(1'b0)); + .s_axi_wvalid(s_axi_wvalid)); endmodule module Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_axic_fifo - (SR, + (dout, + full, + empty, + SR, din, - cmd_push, - rd_cmd_ready, + \cmd_depth_reg[5] , D, - cmd_empty0, - pushed_new_cmd, + m_axi_wvalid, E, - m_axi_arvalid, - s_axi_rvalid, - s_axi_rlast, - m_axi_rready, - S_AXI_AREADY_I_reg, - cmd_push_block_reg, + s_axi_wready, \queue_id_reg[0] , - command_ongoing_reg, - multiple_id_non_split_reg, split_in_progress_reg, + multiple_id_non_split_reg, aclk, - Q, - need_to_split_q, - cmd_push_block, - command_ongoing, - m_axi_arready, - \cmd_depth_reg[3] , - \cmd_depth_reg[1] , - m_axi_rlast, - s_axi_rready, - m_axi_rvalid, - multiple_id_non_split, - cmd_empty, \S_AXI_AID_Q_reg[0] , - queue_id, + wr_cmd_ready, + Q, split_in_progress_reg_0, - aresetn, - almost_empty, - access_is_incr_q, - num_transactions_q, + allow_split_cmd__1, + ram_full_i_reg, + command_ongoing, + cmd_push_block, + \S_AXI_ALEN_Q_reg[3] , + need_to_split_q, \pushed_commands_reg[3] , - \areset_d_reg[1] , - S_AXI_AREADY_I_reg_0, - s_axi_arvalid, - \areset_d_reg[1]_0 , - \S_AXI_AID_Q_reg[0]_0 , - cmd_empty_reg); + s_axi_wvalid, + m_axi_wready, + aresetn, + queue_id, + split_in_progress_reg_1, + cmd_empty_reg, + multiple_id_non_split); + output [4:0]dout; + output full; + output empty; output [0:0]SR; - output [0:0]din; - output cmd_push; - output rd_cmd_ready; + output [3:0]din; + output \cmd_depth_reg[5] ; output [4:0]D; - output cmd_empty0; - output pushed_new_cmd; + output m_axi_wvalid; output [0:0]E; - output m_axi_arvalid; - output s_axi_rvalid; - output s_axi_rlast; - output m_axi_rready; - output S_AXI_AREADY_I_reg; - output cmd_push_block_reg; + output s_axi_wready; output \queue_id_reg[0] ; - output command_ongoing_reg; - output multiple_id_non_split_reg; output split_in_progress_reg; + output multiple_id_non_split_reg; input aclk; - input [5:0]Q; - input need_to_split_q; - input cmd_push_block; - input command_ongoing; - input m_axi_arready; - input \cmd_depth_reg[3] ; - input \cmd_depth_reg[1] ; - input m_axi_rlast; - input s_axi_rready; - input m_axi_rvalid; - input multiple_id_non_split; - input cmd_empty; input \S_AXI_AID_Q_reg[0] ; - input queue_id; + input wr_cmd_ready; + input [5:0]Q; input split_in_progress_reg_0; - input aresetn; - input almost_empty; - input access_is_incr_q; - input [3:0]num_transactions_q; + input allow_split_cmd__1; + input ram_full_i_reg; + input command_ongoing; + input cmd_push_block; + input [3:0]\S_AXI_ALEN_Q_reg[3] ; + input need_to_split_q; input [3:0]\pushed_commands_reg[3] ; - input [1:0]\areset_d_reg[1] ; - input S_AXI_AREADY_I_reg_0; - input s_axi_arvalid; - input \areset_d_reg[1]_0 ; - input \S_AXI_AID_Q_reg[0]_0 ; + input s_axi_wvalid; + input m_axi_wready; + input aresetn; + input queue_id; + input split_in_progress_reg_1; input cmd_empty_reg; + input multiple_id_non_split; wire [4:0]D; wire [0:0]E; wire [5:0]Q; wire [0:0]SR; wire \S_AXI_AID_Q_reg[0] ; - wire \S_AXI_AID_Q_reg[0]_0 ; - wire S_AXI_AREADY_I_reg; - wire S_AXI_AREADY_I_reg_0; - wire access_is_incr_q; + wire [3:0]\S_AXI_ALEN_Q_reg[3] ; wire aclk; - wire almost_empty; - wire [1:0]\areset_d_reg[1] ; - wire \areset_d_reg[1]_0 ; + wire allow_split_cmd__1; wire aresetn; - wire \cmd_depth_reg[1] ; - wire \cmd_depth_reg[3] ; - wire cmd_empty; - wire cmd_empty0; + wire \cmd_depth_reg[5] ; wire cmd_empty_reg; - wire cmd_push; wire cmd_push_block; - wire cmd_push_block_reg; wire command_ongoing; - wire command_ongoing_reg; - wire [0:0]din; - wire m_axi_arready; - wire m_axi_arvalid; - wire m_axi_rlast; - wire m_axi_rready; - wire m_axi_rvalid; + wire [3:0]din; + wire [4:0]dout; + wire empty; + wire full; + wire m_axi_wready; + wire m_axi_wvalid; wire multiple_id_non_split; wire multiple_id_non_split_reg; wire need_to_split_q; - wire [3:0]num_transactions_q; wire [3:0]\pushed_commands_reg[3] ; - wire pushed_new_cmd; wire queue_id; wire \queue_id_reg[0] ; - wire rd_cmd_ready; - wire s_axi_arvalid; - wire s_axi_rlast; - wire s_axi_rready; - wire s_axi_rvalid; + wire ram_full_i_reg; + wire s_axi_wready; + wire s_axi_wvalid; wire split_in_progress_reg; wire split_in_progress_reg_0; + wire split_in_progress_reg_1; + wire wr_cmd_ready; - Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen inst + Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen_6 inst (.D(D), .E(E), .Q(Q), .SR(SR), .\S_AXI_AID_Q_reg[0] (\S_AXI_AID_Q_reg[0] ), - .\S_AXI_AID_Q_reg[0]_0 (\S_AXI_AID_Q_reg[0]_0 ), - .S_AXI_AREADY_I_reg(S_AXI_AREADY_I_reg), - .S_AXI_AREADY_I_reg_0(S_AXI_AREADY_I_reg_0), - .access_is_incr_q(access_is_incr_q), + .\S_AXI_ALEN_Q_reg[3] (\S_AXI_ALEN_Q_reg[3] ), .aclk(aclk), - .almost_empty(almost_empty), - .\areset_d_reg[1] (\areset_d_reg[1] ), - .\areset_d_reg[1]_0 (\areset_d_reg[1]_0 ), + .allow_split_cmd__1(allow_split_cmd__1), .aresetn(aresetn), - .\cmd_depth_reg[1] (cmd_empty0), - .\cmd_depth_reg[1]_0 (\cmd_depth_reg[1] ), - .\cmd_depth_reg[3] (\cmd_depth_reg[3] ), - .cmd_empty(cmd_empty), .cmd_empty_reg(cmd_empty_reg), .cmd_push_block(cmd_push_block), - .cmd_push_block_reg(cmd_push_block_reg), .command_ongoing(command_ongoing), - .command_ongoing_reg(command_ongoing_reg), .din(din), - .m_axi_arready(m_axi_arready), - .m_axi_arvalid(m_axi_arvalid), - .m_axi_rlast(m_axi_rlast), - .m_axi_rready(m_axi_rready), - .m_axi_rvalid(m_axi_rvalid), + .dout(dout), + .empty(empty), + .full(full), + .m_axi_wready(m_axi_wready), + .m_axi_wvalid(m_axi_wvalid), .multiple_id_non_split(multiple_id_non_split), .multiple_id_non_split_reg(multiple_id_non_split_reg), .need_to_split_q(need_to_split_q), - .num_transactions_q(num_transactions_q), - .\pushed_commands_reg[0] (pushed_new_cmd), .\pushed_commands_reg[3] (\pushed_commands_reg[3] ), .queue_id(queue_id), .\queue_id_reg[0] (\queue_id_reg[0] ), - .rd_en(rd_cmd_ready), - .s_axi_arvalid(s_axi_arvalid), - .s_axi_rlast(s_axi_rlast), - .s_axi_rready(s_axi_rready), - .s_axi_rvalid(s_axi_rvalid), + .ram_full_i_reg(ram_full_i_reg), + .s_axi_wready(s_axi_wready), + .s_axi_wvalid(s_axi_wvalid), .split_in_progress_reg(split_in_progress_reg), .split_in_progress_reg_0(split_in_progress_reg_0), - .wr_en(cmd_push)); + .split_in_progress_reg_1(split_in_progress_reg_1), + .wr_cmd_ready(wr_cmd_ready), + .wr_en(\cmd_depth_reg[5] )); endmodule -module Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen - (SR, +(* ORIG_REF_NAME = "axi_data_fifo_v2_1_10_axic_fifo" *) +module Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_axic_fifo_0 + (\S_AXI_BRESP_ACC_reg[0] , + full, din, - wr_en, - rd_en, D, - \cmd_depth_reg[1] , - \pushed_commands_reg[0] , + m_axi_awvalid, + multiple_id_non_split_reg, + multiple_id_non_split_reg_0, + split_ongoing_reg, + cmd_b_push_block_reg, E, - m_axi_arvalid, - s_axi_rvalid, - s_axi_rlast, - m_axi_rready, + \USE_B_CHANNEL.cmd_b_empty_reg , + \pushed_commands_reg[0] , + allow_split_cmd__1, S_AXI_AREADY_I_reg, cmd_push_block_reg, - \queue_id_reg[0] , command_ongoing_reg, - multiple_id_non_split_reg, - split_in_progress_reg, aclk, + SR, + \num_transactions_q_reg[3] , Q, - need_to_split_q, - cmd_push_block, - command_ongoing, - m_axi_arready, - \cmd_depth_reg[3] , - \cmd_depth_reg[1]_0 , - m_axi_rlast, - s_axi_rready, - m_axi_rvalid, - multiple_id_non_split, + cmd_b_push_block, + m_axi_bvalid, + last_word, + s_axi_bready, cmd_empty, - \S_AXI_AID_Q_reg[0] , - queue_id, - split_in_progress_reg_0, - aresetn, + wr_cmd_ready, almost_empty, + aresetn, + split_in_progress_reg, + queue_id, + \S_AXI_AID_Q_reg[0] , + cmd_b_empty, + need_to_split_q, access_is_incr_q, - num_transactions_q, \pushed_commands_reg[3] , - \areset_d_reg[1] , S_AXI_AREADY_I_reg_0, - s_axi_arvalid, - \areset_d_reg[1]_0 , - \S_AXI_AID_Q_reg[0]_0 , - cmd_empty_reg); - output [0:0]SR; + almost_b_empty, + m_axi_awready, + command_ongoing, + ram_full_i_reg, + cmd_push_block, + multiple_id_non_split, + \pushed_commands_reg[3]_0 , + s_axi_awvalid, + \areset_d_reg[0] , + areset_d, + \areset_d_reg[1] ); + output [4:0]\S_AXI_BRESP_ACC_reg[0] ; + output full; output [0:0]din; - output wr_en; - output rd_en; output [4:0]D; - output \cmd_depth_reg[1] ; - output \pushed_commands_reg[0] ; + output m_axi_awvalid; + output multiple_id_non_split_reg; + output multiple_id_non_split_reg_0; + output split_ongoing_reg; + output cmd_b_push_block_reg; output [0:0]E; - output m_axi_arvalid; - output s_axi_rvalid; - output s_axi_rlast; - output m_axi_rready; + output \USE_B_CHANNEL.cmd_b_empty_reg ; + output [0:0]\pushed_commands_reg[0] ; + output allow_split_cmd__1; output S_AXI_AREADY_I_reg; output cmd_push_block_reg; - output \queue_id_reg[0] ; output command_ongoing_reg; - output multiple_id_non_split_reg; - output split_in_progress_reg; input aclk; + input [0:0]SR; + input [3:0]\num_transactions_q_reg[3] ; input [5:0]Q; - input need_to_split_q; - input cmd_push_block; - input command_ongoing; - input m_axi_arready; - input \cmd_depth_reg[3] ; - input \cmd_depth_reg[1]_0 ; - input m_axi_rlast; - input s_axi_rready; - input m_axi_rvalid; - input multiple_id_non_split; + input cmd_b_push_block; + input m_axi_bvalid; + input last_word; + input s_axi_bready; input cmd_empty; - input \S_AXI_AID_Q_reg[0] ; - input queue_id; - input split_in_progress_reg_0; - input aresetn; + input wr_cmd_ready; input almost_empty; + input aresetn; + input split_in_progress_reg; + input queue_id; + input \S_AXI_AID_Q_reg[0] ; + input cmd_b_empty; + input need_to_split_q; input access_is_incr_q; - input [3:0]num_transactions_q; input [3:0]\pushed_commands_reg[3] ; - input [1:0]\areset_d_reg[1] ; input S_AXI_AREADY_I_reg_0; - input s_axi_arvalid; - input \areset_d_reg[1]_0 ; - input \S_AXI_AID_Q_reg[0]_0 ; - input cmd_empty_reg; + input almost_b_empty; + input m_axi_awready; + input command_ongoing; + input ram_full_i_reg; + input cmd_push_block; + input multiple_id_non_split; + input \pushed_commands_reg[3]_0 ; + input s_axi_awvalid; + input \areset_d_reg[0] ; + input [0:0]areset_d; + input \areset_d_reg[1] ; wire [4:0]D; wire [0:0]E; wire [5:0]Q; wire [0:0]SR; wire \S_AXI_AID_Q_reg[0] ; - wire \S_AXI_AID_Q_reg[0]_0 ; - wire S_AXI_AREADY_I_i_3_n_0; - wire S_AXI_AREADY_I_i_4_n_0; wire S_AXI_AREADY_I_reg; wire S_AXI_AREADY_I_reg_0; + wire [4:0]\S_AXI_BRESP_ACC_reg[0] ; + wire \USE_B_CHANNEL.cmd_b_empty_reg ; wire access_is_incr_q; wire aclk; + wire allow_split_cmd__1; + wire almost_b_empty; wire almost_empty; - wire [1:0]\areset_d_reg[1] ; - wire \areset_d_reg[1]_0 ; + wire [0:0]areset_d; + wire \areset_d_reg[0] ; + wire \areset_d_reg[1] ; wire aresetn; - wire \cmd_depth_reg[1] ; - wire \cmd_depth_reg[1]_0 ; - wire \cmd_depth_reg[3] ; + wire cmd_b_empty; + wire cmd_b_push_block; + wire cmd_b_push_block_reg; wire cmd_empty; - wire cmd_empty_reg; wire cmd_push_block; wire cmd_push_block_reg; wire command_ongoing; wire command_ongoing_reg; wire [0:0]din; - wire empty; wire full; + wire last_word; + wire m_axi_awready; + wire m_axi_awvalid; + wire m_axi_bvalid; + wire multiple_id_non_split; + wire multiple_id_non_split_reg; + wire multiple_id_non_split_reg_0; + wire need_to_split_q; + wire [3:0]\num_transactions_q_reg[3] ; + wire [0:0]\pushed_commands_reg[0] ; + wire [3:0]\pushed_commands_reg[3] ; + wire \pushed_commands_reg[3]_0 ; + wire queue_id; + wire ram_full_i_reg; + wire s_axi_awvalid; + wire s_axi_bready; + wire split_in_progress_reg; + wire split_ongoing_reg; + wire wr_cmd_ready; + + Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen inst + (.D(D), + .E(E), + .Q(Q), + .SR(SR), + .\S_AXI_AID_Q_reg[0] (\S_AXI_AID_Q_reg[0] ), + .S_AXI_AREADY_I_reg(S_AXI_AREADY_I_reg), + .S_AXI_AREADY_I_reg_0(S_AXI_AREADY_I_reg_0), + .\S_AXI_BRESP_ACC_reg[0] (\S_AXI_BRESP_ACC_reg[0] ), + .\USE_B_CHANNEL.cmd_b_empty_reg (\USE_B_CHANNEL.cmd_b_empty_reg ), + .access_is_incr_q(access_is_incr_q), + .aclk(aclk), + .allow_split_cmd__1(allow_split_cmd__1), + .almost_b_empty(almost_b_empty), + .almost_empty(almost_empty), + .areset_d(areset_d), + .\areset_d_reg[0] (\areset_d_reg[0] ), + .\areset_d_reg[1] (\areset_d_reg[1] ), + .aresetn(aresetn), + .cmd_b_empty(cmd_b_empty), + .cmd_b_push_block(cmd_b_push_block), + .cmd_b_push_block_reg(cmd_b_push_block_reg), + .cmd_empty(cmd_empty), + .cmd_push_block(cmd_push_block), + .cmd_push_block_reg(cmd_push_block_reg), + .command_ongoing(command_ongoing), + .command_ongoing_reg(command_ongoing_reg), + .din(din), + .full(full), + .last_word(last_word), + .m_axi_awready(m_axi_awready), + .m_axi_awvalid(m_axi_awvalid), + .m_axi_bvalid(m_axi_bvalid), + .multiple_id_non_split(multiple_id_non_split), + .multiple_id_non_split_reg(multiple_id_non_split_reg), + .multiple_id_non_split_reg_0(multiple_id_non_split_reg_0), + .need_to_split_q(need_to_split_q), + .\num_transactions_q_reg[3] (\num_transactions_q_reg[3] ), + .\pushed_commands_reg[0] (\pushed_commands_reg[0] ), + .\pushed_commands_reg[3] (\pushed_commands_reg[3] ), + .\pushed_commands_reg[3]_0 (\pushed_commands_reg[3]_0 ), + .queue_id(queue_id), + .ram_full_i_reg(ram_full_i_reg), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_bready(s_axi_bready), + .split_in_progress_reg(split_in_progress_reg), + .split_ongoing_reg(split_ongoing_reg), + .wr_cmd_ready(wr_cmd_ready)); +endmodule + +(* ORIG_REF_NAME = "axi_data_fifo_v2_1_10_axic_fifo" *) +module Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_axic_fifo__parameterized0 + (din, + split_in_progress_reg, + rd_cmd_ready, + D, + split_ongoing_reg, + m_axi_rready, + s_axi_rvalid, + s_axi_rlast, + E, + cmd_push_block_reg, + \cmd_depth_reg[5] , + m_axi_arvalid, + S_AXI_AREADY_I_reg, + \queue_id_reg[0] , + command_ongoing_reg, + multiple_id_non_split_reg, + split_in_progress_reg_0, + aclk, + aresetn_0, + Q, + cmd_push_block, + command_ongoing, + almost_empty, + cmd_empty, + aresetn, + need_to_split_q, + access_is_incr_q, + \num_transactions_q_reg[3] , + \pushed_commands_reg[3] , + m_axi_rvalid, + s_axi_rready, + m_axi_rlast, + m_axi_arready, + multiple_id_non_split, + \S_AXI_AID_Q_reg[0] , + \queue_id_reg[0]_0 , + split_in_progress_reg_1, + \num_transactions_q_reg[0] , + \num_transactions_q_reg[2] , + \num_transactions_q_reg[1] , + \pushed_commands_reg[3]_0 , + s_axi_arvalid, + S_AXI_AREADY_I_reg_0, + areset_d, + \areset_d_reg[1] , + split_in_progress_reg_2, + allow_split_cmd__1); + output [0:0]din; + output split_in_progress_reg; + output rd_cmd_ready; + output [4:0]D; + output split_ongoing_reg; + output m_axi_rready; + output s_axi_rvalid; + output s_axi_rlast; + output [0:0]E; + output cmd_push_block_reg; + output [0:0]\cmd_depth_reg[5] ; + output m_axi_arvalid; + output S_AXI_AREADY_I_reg; + output \queue_id_reg[0] ; + output command_ongoing_reg; + output multiple_id_non_split_reg; + output split_in_progress_reg_0; + input aclk; + input aresetn_0; + input [5:0]Q; + input cmd_push_block; + input command_ongoing; + input almost_empty; + input cmd_empty; + input aresetn; + input need_to_split_q; + input access_is_incr_q; + input \num_transactions_q_reg[3] ; + input [3:0]\pushed_commands_reg[3] ; + input m_axi_rvalid; + input s_axi_rready; + input m_axi_rlast; + input m_axi_arready; + input multiple_id_non_split; + input \S_AXI_AID_Q_reg[0] ; + input \queue_id_reg[0]_0 ; + input split_in_progress_reg_1; + input \num_transactions_q_reg[0] ; + input \num_transactions_q_reg[2] ; + input \num_transactions_q_reg[1] ; + input \pushed_commands_reg[3]_0 ; + input s_axi_arvalid; + input S_AXI_AREADY_I_reg_0; + input [1:0]areset_d; + input \areset_d_reg[1] ; + input split_in_progress_reg_2; + input allow_split_cmd__1; + + wire [4:0]D; + wire [0:0]E; + wire [5:0]Q; + wire \S_AXI_AID_Q_reg[0] ; + wire S_AXI_AREADY_I_reg; + wire S_AXI_AREADY_I_reg_0; + wire access_is_incr_q; + wire aclk; + wire allow_split_cmd__1; + wire almost_empty; + wire [1:0]areset_d; + wire \areset_d_reg[1] ; + wire aresetn; + wire aresetn_0; + wire [0:0]\cmd_depth_reg[5] ; + wire cmd_empty; + wire cmd_push_block; + wire cmd_push_block_reg; + wire command_ongoing; + wire command_ongoing_reg; + wire [0:0]din; wire m_axi_arready; wire m_axi_arvalid; - wire m_axi_arvalid_INST_0_i_1_n_0; wire m_axi_rlast; wire m_axi_rready; wire m_axi_rvalid; wire multiple_id_non_split; wire multiple_id_non_split_reg; wire need_to_split_q; - wire [3:0]num_transactions_q; - wire \pushed_commands_reg[0] ; + wire \num_transactions_q_reg[0] ; + wire \num_transactions_q_reg[1] ; + wire \num_transactions_q_reg[2] ; + wire \num_transactions_q_reg[3] ; wire [3:0]\pushed_commands_reg[3] ; - wire queue_id; + wire \pushed_commands_reg[3]_0 ; wire \queue_id_reg[0] ; - wire rd_cmd_split; - wire rd_en; + wire \queue_id_reg[0]_0 ; + wire rd_cmd_ready; wire s_axi_arvalid; wire s_axi_rlast; wire s_axi_rready; wire s_axi_rvalid; - wire split_in_progress; - wire split_in_progress_i_3_n_0; wire split_in_progress_reg; wire split_in_progress_reg_0; - wire wr_en; - wire NLW_fifo_gen_inst_almost_empty_UNCONNECTED; - wire NLW_fifo_gen_inst_almost_full_UNCONNECTED; - wire NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED; - wire NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED; - wire NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED; - wire NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED; - wire NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED; - wire NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED; - wire NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED; - wire NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED; - wire NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED; - wire NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED; - wire NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED; - wire NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED; - wire NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED; - wire NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED; - wire NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED; - wire NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED; - wire NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED; - wire NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED; - wire NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED; - wire NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED; - wire NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED; - wire NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED; - wire NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED; - wire NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED; - wire NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED; - wire NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED; - wire NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED; - wire NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED; - wire NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED; - wire NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED; - wire NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED; - wire NLW_fifo_gen_inst_axis_overflow_UNCONNECTED; - wire NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED; - wire NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED; - wire NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED; - wire NLW_fifo_gen_inst_axis_underflow_UNCONNECTED; - wire NLW_fifo_gen_inst_dbiterr_UNCONNECTED; - wire NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED; - wire NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED; - wire NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED; - wire NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED; - wire NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED; - wire NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED; - wire NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED; - wire NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED; - wire NLW_fifo_gen_inst_overflow_UNCONNECTED; - wire NLW_fifo_gen_inst_prog_empty_UNCONNECTED; - wire NLW_fifo_gen_inst_prog_full_UNCONNECTED; - wire NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED; - wire NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED; - wire NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED; - wire NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED; - wire NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED; - wire NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED; - wire NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED; - wire NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED; - wire NLW_fifo_gen_inst_sbiterr_UNCONNECTED; - wire NLW_fifo_gen_inst_underflow_UNCONNECTED; - wire NLW_fifo_gen_inst_valid_UNCONNECTED; - wire NLW_fifo_gen_inst_wr_ack_UNCONNECTED; - wire NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED; - wire [4:0]NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED; - wire [4:0]NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED; - wire [4:0]NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED; - wire [4:0]NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED; - wire [4:0]NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED; - wire [4:0]NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED; - wire [4:0]NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED; - wire [4:0]NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED; - wire [4:0]NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED; - wire [10:0]NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED; - wire [10:0]NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED; - wire [10:0]NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED; - wire [10:0]NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED; - wire [10:0]NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED; - wire [10:0]NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED; - wire [10:0]NLW_fifo_gen_inst_axis_data_count_UNCONNECTED; - wire [10:0]NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED; - wire [10:0]NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED; - wire [5:0]NLW_fifo_gen_inst_data_count_UNCONNECTED; - wire [31:0]NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED; - wire [1:0]NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED; - wire [3:0]NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED; - wire [3:0]NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED; - wire [7:0]NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED; - wire [1:0]NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED; - wire [2:0]NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED; - wire [3:0]NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED; - wire [3:0]NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED; - wire [2:0]NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED; - wire [0:0]NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED; - wire [31:0]NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED; - wire [1:0]NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED; - wire [3:0]NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED; - wire [3:0]NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED; - wire [7:0]NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED; - wire [1:0]NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED; - wire [2:0]NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED; - wire [3:0]NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED; - wire [3:0]NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED; - wire [2:0]NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED; - wire [0:0]NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED; - wire [63:0]NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED; - wire [3:0]NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED; - wire [7:0]NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED; - wire [0:0]NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED; - wire [63:0]NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED; - wire [3:0]NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED; - wire [7:0]NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED; + wire split_in_progress_reg_1; + wire split_in_progress_reg_2; + wire split_ongoing_reg; + + Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen__parameterized0 inst + (.D(D), + .E(E), + .Q(Q), + .\S_AXI_AID_Q_reg[0] (\S_AXI_AID_Q_reg[0] ), + .S_AXI_AREADY_I_reg(S_AXI_AREADY_I_reg), + .S_AXI_AREADY_I_reg_0(S_AXI_AREADY_I_reg_0), + .access_is_incr_q(access_is_incr_q), + .aclk(aclk), + .allow_split_cmd__1(allow_split_cmd__1), + .almost_empty(almost_empty), + .areset_d(areset_d), + .\areset_d_reg[1] (\areset_d_reg[1] ), + .aresetn(aresetn), + .aresetn_0(aresetn_0), + .\cmd_depth_reg[5] (\cmd_depth_reg[5] ), + .cmd_empty(cmd_empty), + .cmd_push_block(cmd_push_block), + .cmd_push_block_reg(cmd_push_block_reg), + .command_ongoing(command_ongoing), + .command_ongoing_reg(command_ongoing_reg), + .din(din), + .m_axi_arready(m_axi_arready), + .m_axi_arvalid(m_axi_arvalid), + .m_axi_rlast(m_axi_rlast), + .m_axi_rready(m_axi_rready), + .m_axi_rvalid(m_axi_rvalid), + .multiple_id_non_split(multiple_id_non_split), + .multiple_id_non_split_reg(multiple_id_non_split_reg), + .need_to_split_q(need_to_split_q), + .\num_transactions_q_reg[0] (\num_transactions_q_reg[0] ), + .\num_transactions_q_reg[1] (\num_transactions_q_reg[1] ), + .\num_transactions_q_reg[2] (\num_transactions_q_reg[2] ), + .\num_transactions_q_reg[3] (\num_transactions_q_reg[3] ), + .\pushed_commands_reg[3] (\pushed_commands_reg[3] ), + .\pushed_commands_reg[3]_0 (\pushed_commands_reg[3]_0 ), + .\queue_id_reg[0] (\queue_id_reg[0] ), + .\queue_id_reg[0]_0 (\queue_id_reg[0]_0 ), + .rd_en(rd_cmd_ready), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_rlast(s_axi_rlast), + .s_axi_rready(s_axi_rready), + .s_axi_rvalid(s_axi_rvalid), + .split_in_progress_reg(split_in_progress_reg_0), + .split_in_progress_reg_0(split_in_progress_reg_1), + .split_in_progress_reg_1(split_in_progress_reg_2), + .split_ongoing_reg(split_ongoing_reg), + .wr_en(split_in_progress_reg)); +endmodule + +module Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen + (\S_AXI_BRESP_ACC_reg[0] , + full, + din, + D, + m_axi_awvalid, + multiple_id_non_split_reg, + multiple_id_non_split_reg_0, + split_ongoing_reg, + cmd_b_push_block_reg, + E, + \USE_B_CHANNEL.cmd_b_empty_reg , + \pushed_commands_reg[0] , + allow_split_cmd__1, + S_AXI_AREADY_I_reg, + cmd_push_block_reg, + command_ongoing_reg, + aclk, + SR, + \num_transactions_q_reg[3] , + Q, + cmd_b_push_block, + m_axi_bvalid, + last_word, + s_axi_bready, + cmd_empty, + wr_cmd_ready, + almost_empty, + aresetn, + split_in_progress_reg, + queue_id, + \S_AXI_AID_Q_reg[0] , + cmd_b_empty, + need_to_split_q, + access_is_incr_q, + \pushed_commands_reg[3] , + S_AXI_AREADY_I_reg_0, + almost_b_empty, + m_axi_awready, + command_ongoing, + ram_full_i_reg, + cmd_push_block, + multiple_id_non_split, + \pushed_commands_reg[3]_0 , + s_axi_awvalid, + \areset_d_reg[0] , + areset_d, + \areset_d_reg[1] ); + output [4:0]\S_AXI_BRESP_ACC_reg[0] ; + output full; + output [0:0]din; + output [4:0]D; + output m_axi_awvalid; + output multiple_id_non_split_reg; + output multiple_id_non_split_reg_0; + output split_ongoing_reg; + output cmd_b_push_block_reg; + output [0:0]E; + output \USE_B_CHANNEL.cmd_b_empty_reg ; + output [0:0]\pushed_commands_reg[0] ; + output allow_split_cmd__1; + output S_AXI_AREADY_I_reg; + output cmd_push_block_reg; + output command_ongoing_reg; + input aclk; + input [0:0]SR; + input [3:0]\num_transactions_q_reg[3] ; + input [5:0]Q; + input cmd_b_push_block; + input m_axi_bvalid; + input last_word; + input s_axi_bready; + input cmd_empty; + input wr_cmd_ready; + input almost_empty; + input aresetn; + input split_in_progress_reg; + input queue_id; + input \S_AXI_AID_Q_reg[0] ; + input cmd_b_empty; + input need_to_split_q; + input access_is_incr_q; + input [3:0]\pushed_commands_reg[3] ; + input S_AXI_AREADY_I_reg_0; + input almost_b_empty; + input m_axi_awready; + input command_ongoing; + input ram_full_i_reg; + input cmd_push_block; + input multiple_id_non_split; + input \pushed_commands_reg[3]_0 ; + input s_axi_awvalid; + input \areset_d_reg[0] ; + input [0:0]areset_d; + input \areset_d_reg[1] ; + + wire [4:0]D; + wire [0:0]E; + wire [5:0]Q; + wire [0:0]SR; + wire \S_AXI_AID_Q_reg[0] ; + wire S_AXI_AREADY_I_reg; + wire S_AXI_AREADY_I_reg_0; + wire [4:0]\S_AXI_BRESP_ACC_reg[0] ; + wire \USE_B_CHANNEL.cmd_b_depth[4]_i_2_n_0 ; + wire \USE_B_CHANNEL.cmd_b_depth[5]_i_3_n_0 ; + wire \USE_B_CHANNEL.cmd_b_empty_reg ; + wire access_is_incr_q; + wire aclk; + wire allow_split_cmd__1; + wire almost_b_empty; + wire almost_empty; + wire [0:0]areset_d; + wire \areset_d_reg[0] ; + wire \areset_d_reg[1] ; + wire aresetn; + wire cmd_b_empty; + wire cmd_b_push_block; + wire cmd_b_push_block_reg; + wire cmd_empty; + wire cmd_push_block; + wire cmd_push_block_reg; + wire command_ongoing; + wire command_ongoing_reg; + wire [0:0]din; + wire empty; + wire fifo_gen_inst_i_2__1_n_0; + wire full; + wire last_word; + wire m_axi_awready; + wire m_axi_awvalid; + wire m_axi_bvalid; + wire multiple_id_non_split; + wire multiple_id_non_split_i_3_n_0; + wire multiple_id_non_split_reg; + wire multiple_id_non_split_reg_0; + wire need_to_split_q; + wire [3:0]\num_transactions_q_reg[3] ; + wire [0:0]\pushed_commands_reg[0] ; + wire [3:0]\pushed_commands_reg[3] ; + wire \pushed_commands_reg[3]_0 ; + wire queue_id; + wire ram_full_i_reg; + wire s_axi_awvalid; + wire s_axi_bready; + wire split_in_progress_reg; + wire split_ongoing_reg; + wire wr_cmd_b_ready; + wire wr_cmd_ready; + wire NLW_fifo_gen_inst_almost_empty_UNCONNECTED; + wire NLW_fifo_gen_inst_almost_full_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axis_overflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED; + wire NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED; + wire NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axis_underflow_UNCONNECTED; + wire NLW_fifo_gen_inst_dbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED; + wire NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED; + wire NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED; + wire NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED; + wire NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED; + wire NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED; + wire NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED; + wire NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED; + wire NLW_fifo_gen_inst_overflow_UNCONNECTED; + wire NLW_fifo_gen_inst_prog_empty_UNCONNECTED; + wire NLW_fifo_gen_inst_prog_full_UNCONNECTED; + wire NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED; + wire NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED; + wire NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED; + wire NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED; + wire NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED; + wire NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED; + wire NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED; + wire NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED; + wire NLW_fifo_gen_inst_sbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_underflow_UNCONNECTED; + wire NLW_fifo_gen_inst_valid_UNCONNECTED; + wire NLW_fifo_gen_inst_wr_ack_UNCONNECTED; + wire NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED; + wire [4:0]NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED; + wire [4:0]NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED; + wire [4:0]NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED; + wire [4:0]NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED; + wire [4:0]NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED; + wire [4:0]NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED; + wire [4:0]NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED; + wire [4:0]NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED; + wire [4:0]NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED; + wire [10:0]NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED; + wire [10:0]NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED; + wire [10:0]NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED; + wire [10:0]NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED; + wire [10:0]NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED; + wire [10:0]NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED; + wire [10:0]NLW_fifo_gen_inst_axis_data_count_UNCONNECTED; + wire [10:0]NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED; + wire [10:0]NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED; + wire [5:0]NLW_fifo_gen_inst_data_count_UNCONNECTED; + wire [31:0]NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED; + wire [1:0]NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED; + wire [7:0]NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED; + wire [1:0]NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED; + wire [2:0]NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED; + wire [2:0]NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED; + wire [0:0]NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED; + wire [31:0]NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED; + wire [1:0]NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED; + wire [7:0]NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED; + wire [1:0]NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED; + wire [2:0]NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED; + wire [2:0]NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED; + wire [0:0]NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED; + wire [63:0]NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED; + wire [7:0]NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED; + wire [0:0]NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED; + wire [63:0]NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED; + wire [7:0]NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED; wire [3:0]NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED; wire [3:0]NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED; wire [3:0]NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED; @@ -722,124 +1179,126 @@ module Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen wire [0:0]NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED; wire [5:0]NLW_fifo_gen_inst_wr_data_count_UNCONNECTED; - (* SOFT_HLUTNM = "soft_lutpair7" *) - LUT1 #( - .INIT(2'h1)) - S_AXI_AREADY_I_i_1 - (.I0(aresetn), - .O(SR)); LUT6 #( - .INIT(64'h444444F4FFFF44F4)) + .INIT(64'h0F88FFFF0F880F88)) S_AXI_AREADY_I_i_2 - (.I0(\areset_d_reg[1] [0]), - .I1(\areset_d_reg[1] [1]), - .I2(\pushed_commands_reg[0] ), - .I3(S_AXI_AREADY_I_i_3_n_0), - .I4(S_AXI_AREADY_I_reg_0), - .I5(s_axi_arvalid), + (.I0(\pushed_commands_reg[0] ), + .I1(\pushed_commands_reg[3]_0 ), + .I2(s_axi_awvalid), + .I3(S_AXI_AREADY_I_reg_0), + .I4(\areset_d_reg[0] ), + .I5(areset_d), .O(S_AXI_AREADY_I_reg)); - LUT6 #( - .INIT(64'h8AA8AAAAAAAA8AA8)) - S_AXI_AREADY_I_i_3 - (.I0(access_is_incr_q), - .I1(S_AXI_AREADY_I_i_4_n_0), - .I2(num_transactions_q[3]), - .I3(\pushed_commands_reg[3] [3]), - .I4(num_transactions_q[1]), - .I5(\pushed_commands_reg[3] [1]), - .O(S_AXI_AREADY_I_i_3_n_0)); - LUT4 #( - .INIT(16'h6FF6)) - S_AXI_AREADY_I_i_4 - (.I0(num_transactions_q[0]), - .I1(\pushed_commands_reg[3] [0]), - .I2(num_transactions_q[2]), - .I3(\pushed_commands_reg[3] [2]), - .O(S_AXI_AREADY_I_i_4_n_0)); LUT3 #( .INIT(8'h69)) - \cmd_depth[1]_i_1 - (.I0(\cmd_depth_reg[1] ), - .I1(Q[0]), + \USE_B_CHANNEL.cmd_b_depth[1]_i_1 + (.I0(Q[0]), + .I1(\USE_B_CHANNEL.cmd_b_depth[4]_i_2_n_0 ), .I2(Q[1]), .O(D[0])); - (* SOFT_HLUTNM = "soft_lutpair6" *) + (* SOFT_HLUTNM = "soft_lutpair41" *) LUT4 #( - .INIT(16'h6AA9)) - \cmd_depth[2]_i_1 - (.I0(Q[2]), - .I1(Q[1]), - .I2(\cmd_depth_reg[1] ), - .I3(Q[0]), + .INIT(16'h78E1)) + \USE_B_CHANNEL.cmd_b_depth[2]_i_1 + (.I0(Q[0]), + .I1(\USE_B_CHANNEL.cmd_b_depth[4]_i_2_n_0 ), + .I2(Q[2]), + .I3(Q[1]), .O(D[1])); - (* SOFT_HLUTNM = "soft_lutpair6" *) + (* SOFT_HLUTNM = "soft_lutpair41" *) LUT5 #( - .INIT(32'h6AAAAAA9)) - \cmd_depth[3]_i_1 - (.I0(Q[3]), - .I1(Q[1]), - .I2(Q[0]), - .I3(\cmd_depth_reg[1] ), + .INIT(32'h7F80FE01)) + \USE_B_CHANNEL.cmd_b_depth[3]_i_1 + (.I0(\USE_B_CHANNEL.cmd_b_depth[4]_i_2_n_0 ), + .I1(Q[0]), + .I2(Q[1]), + .I3(Q[3]), .I4(Q[2]), .O(D[2])); LUT6 #( - .INIT(64'h6AAAAAAAAAAAAAA9)) - \cmd_depth[4]_i_1 - (.I0(Q[4]), - .I1(Q[2]), - .I2(Q[1]), - .I3(Q[3]), - .I4(\cmd_depth_reg[1] ), - .I5(Q[0]), + .INIT(64'h7FFF8000FFFE0001)) + \USE_B_CHANNEL.cmd_b_depth[4]_i_1 + (.I0(Q[1]), + .I1(Q[0]), + .I2(\USE_B_CHANNEL.cmd_b_depth[4]_i_2_n_0 ), + .I3(Q[2]), + .I4(Q[4]), + .I5(Q[3]), .O(D[3])); - (* SOFT_HLUTNM = "soft_lutpair4" *) - LUT5 #( - .INIT(32'hFF7F0080)) - \cmd_depth[5]_i_1 - (.I0(m_axi_rlast), - .I1(s_axi_rready), - .I2(m_axi_rvalid), - .I3(empty), - .I4(wr_en), + LUT6 #( + .INIT(64'h4444444404444444)) + \USE_B_CHANNEL.cmd_b_depth[4]_i_2 + (.I0(cmd_b_push_block), + .I1(m_axi_awvalid), + .I2(m_axi_bvalid), + .I3(last_word), + .I4(s_axi_bready), + .I5(empty), + .O(\USE_B_CHANNEL.cmd_b_depth[4]_i_2_n_0 )); + LUT6 #( + .INIT(64'h2D22222222222222)) + \USE_B_CHANNEL.cmd_b_depth[5]_i_1 + (.I0(m_axi_awvalid), + .I1(cmd_b_push_block), + .I2(empty), + .I3(s_axi_bready), + .I4(last_word), + .I5(m_axi_bvalid), .O(E)); + LUT5 #( + .INIT(32'h7F80FE01)) + \USE_B_CHANNEL.cmd_b_depth[5]_i_2 + (.I0(Q[2]), + .I1(\USE_B_CHANNEL.cmd_b_depth[5]_i_3_n_0 ), + .I2(Q[3]), + .I3(Q[5]), + .I4(Q[4]), + .O(D[4])); LUT6 #( - .INIT(64'hAAA9AAAA6AA96AAA)) - \cmd_depth[5]_i_2 - (.I0(Q[5]), - .I1(Q[4]), + .INIT(64'h5454545454D55454)) + \USE_B_CHANNEL.cmd_b_depth[5]_i_3 + (.I0(Q[2]), + .I1(Q[1]), .I2(Q[0]), - .I3(\cmd_depth_reg[1] ), - .I4(\cmd_depth_reg[3] ), - .I5(\cmd_depth_reg[1]_0 ), - .O(D[4])); - (* SOFT_HLUTNM = "soft_lutpair8" *) - LUT5 #( - .INIT(32'h00000010)) - cmd_empty_i_3 - (.I0(m_axi_arvalid_INST_0_i_1_n_0), - .I1(full), - .I2(command_ongoing), - .I3(cmd_push_block), - .I4(rd_en), - .O(\cmd_depth_reg[1] )); - (* SOFT_HLUTNM = "soft_lutpair7" *) + .I3(cmd_b_push_block), + .I4(m_axi_awvalid), + .I5(wr_cmd_b_ready), + .O(\USE_B_CHANNEL.cmd_b_depth[5]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair40" *) LUT5 #( - .INIT(32'h0000AE00)) + .INIT(32'hF2DDD000)) + \USE_B_CHANNEL.cmd_b_empty_i_1 + (.I0(m_axi_awvalid), + .I1(cmd_b_push_block), + .I2(almost_b_empty), + .I3(wr_cmd_b_ready), + .I4(cmd_b_empty), + .O(\USE_B_CHANNEL.cmd_b_empty_reg )); + (* SOFT_HLUTNM = "soft_lutpair42" *) + LUT4 #( + .INIT(16'h00E0)) + cmd_b_push_block_i_1 + (.I0(m_axi_awvalid), + .I1(cmd_b_push_block), + .I2(aresetn), + .I3(S_AXI_AREADY_I_reg_0), + .O(cmd_b_push_block_reg)); + LUT4 #( + .INIT(16'h08C8)) cmd_push_block_i_1 (.I0(cmd_push_block), - .I1(wr_en), - .I2(m_axi_arready), - .I3(aresetn), - .I4(\pushed_commands_reg[0] ), + .I1(aresetn), + .I2(m_axi_awvalid), + .I3(m_axi_awready), .O(cmd_push_block_reg)); LUT6 #( - .INIT(64'hFFFFFDDD0000F000)) + .INIT(64'hFFFFF7770000F000)) command_ongoing_i_1 (.I0(\pushed_commands_reg[0] ), - .I1(S_AXI_AREADY_I_i_3_n_0), - .I2(S_AXI_AREADY_I_reg_0), - .I3(s_axi_arvalid), - .I4(\areset_d_reg[1]_0 ), + .I1(\pushed_commands_reg[3]_0 ), + .I2(s_axi_awvalid), + .I3(S_AXI_AREADY_I_reg_0), + .I4(\areset_d_reg[1] ), .I5(command_ongoing), .O(command_ongoing_reg)); (* C_ADD_NGC_CONSTRAINT = "0" *) @@ -871,7 +1330,7 @@ module Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen (* C_COUNT_TYPE = "0" *) (* C_DATA_COUNT_WIDTH = "6" *) (* C_DEFAULT_VALUE = "BlankString" *) - (* C_DIN_WIDTH = "1" *) + (* C_DIN_WIDTH = "5" *) (* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *) @@ -879,7 +1338,7 @@ module Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *) (* C_DOUT_RST_VAL = "0" *) - (* C_DOUT_WIDTH = "1" *) + (* C_DOUT_WIDTH = "5" *) (* C_ENABLE_RLOCS = "0" *) (* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) @@ -1130,8 +1589,8 @@ module Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen .clk(aclk), .data_count(NLW_fifo_gen_inst_data_count_UNCONNECTED[5:0]), .dbiterr(NLW_fifo_gen_inst_dbiterr_UNCONNECTED), - .din(din), - .dout(rd_cmd_split), + .din({din,\num_transactions_q_reg[3] }), + .dout(\S_AXI_BRESP_ACC_reg[0] ), .empty(empty), .full(full), .injectdbiterr(1'b0), @@ -1204,7 +1663,7 @@ module Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen .prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0}), .rd_clk(1'b0), .rd_data_count(NLW_fifo_gen_inst_rd_data_count_UNCONNECTED[5:0]), - .rd_en(rd_en), + .rd_en(wr_cmd_b_ready), .rd_rst(1'b0), .rd_rst_busy(NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED), .rst(SR), @@ -1273,764 +1732,4891 @@ module Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen .wr_ack(NLW_fifo_gen_inst_wr_ack_UNCONNECTED), .wr_clk(1'b0), .wr_data_count(NLW_fifo_gen_inst_wr_data_count_UNCONNECTED[5:0]), - .wr_en(wr_en), + .wr_en(fifo_gen_inst_i_2__1_n_0), .wr_rst(1'b0), .wr_rst_busy(NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED)); - LUT2 #( - .INIT(4'h8)) - fifo_gen_inst_i_1 - (.I0(S_AXI_AREADY_I_i_3_n_0), - .I1(need_to_split_q), + LUT5 #( + .INIT(32'h08808888)) + fifo_gen_inst_i_1__0 + (.I0(need_to_split_q), + .I1(access_is_incr_q), + .I2(\num_transactions_q_reg[3] [3]), + .I3(\pushed_commands_reg[3] [3]), + .I4(split_ongoing_reg), .O(din)); - (* SOFT_HLUTNM = "soft_lutpair5" *) - LUT4 #( - .INIT(16'h0010)) - fifo_gen_inst_i_2 - (.I0(m_axi_arvalid_INST_0_i_1_n_0), - .I1(cmd_push_block), - .I2(command_ongoing), - .I3(full), - .O(wr_en)); - (* SOFT_HLUTNM = "soft_lutpair4" *) + (* SOFT_HLUTNM = "soft_lutpair40" *) + LUT2 #( + .INIT(4'h2)) + fifo_gen_inst_i_2__1 + (.I0(m_axi_awvalid), + .I1(cmd_b_push_block), + .O(fifo_gen_inst_i_2__1_n_0)); LUT4 #( .INIT(16'h4000)) fifo_gen_inst_i_3 (.I0(empty), - .I1(m_axi_rvalid), - .I2(s_axi_rready), - .I3(m_axi_rlast), - .O(rd_en)); - (* SOFT_HLUTNM = "soft_lutpair8" *) - LUT4 #( - .INIT(16'hAA02)) - m_axi_arvalid_INST_0 + .I1(s_axi_bready), + .I2(last_word), + .I3(m_axi_bvalid), + .O(wr_cmd_b_ready)); + LUT6 #( + .INIT(64'h9009000000009009)) + fifo_gen_inst_i_4 + (.I0(\num_transactions_q_reg[3] [0]), + .I1(\pushed_commands_reg[3] [0]), + .I2(\pushed_commands_reg[3] [2]), + .I3(\num_transactions_q_reg[3] [2]), + .I4(\pushed_commands_reg[3] [1]), + .I5(\num_transactions_q_reg[3] [1]), + .O(split_ongoing_reg)); + LUT6 #( + .INIT(64'hAAAAAAAA00002220)) + m_axi_awvalid_INST_0 (.I0(command_ongoing), .I1(full), - .I2(m_axi_arvalid_INST_0_i_1_n_0), - .I3(cmd_push_block), - .O(m_axi_arvalid)); + .I2(allow_split_cmd__1), + .I3(multiple_id_non_split_reg_0), + .I4(ram_full_i_reg), + .I5(cmd_push_block), + .O(m_axi_awvalid)); LUT6 #( - .INIT(64'hABBA0330ABBA0000)) - m_axi_arvalid_INST_0_i_1 + .INIT(64'h4444400440044004)) + m_axi_awvalid_INST_0_i_1 (.I0(multiple_id_non_split), - .I1(cmd_empty), - .I2(\S_AXI_AID_Q_reg[0] ), - .I3(queue_id), - .I4(need_to_split_q), - .I5(split_in_progress_reg_0), - .O(m_axi_arvalid_INST_0_i_1_n_0)); - (* SOFT_HLUTNM = "soft_lutpair9" *) - LUT3 #( - .INIT(8'h0D)) - m_axi_rready_INST_0 - (.I0(m_axi_rvalid), - .I1(s_axi_rready), - .I2(empty), - .O(m_axi_rready)); + .I1(need_to_split_q), + .I2(queue_id), + .I3(\S_AXI_AID_Q_reg[0] ), + .I4(cmd_b_empty), + .I5(cmd_empty), + .O(allow_split_cmd__1)); LUT6 #( - .INIT(64'h00000000AAAAAEAA)) - multiple_id_non_split_i_1 - (.I0(multiple_id_non_split), - .I1(\S_AXI_AID_Q_reg[0]_0 ), - .I2(cmd_push_block), - .I3(command_ongoing), - .I4(full), - .I5(split_in_progress), + .INIT(64'h00000000FFD7D7D7)) + m_axi_awvalid_INST_0_i_2 + (.I0(split_in_progress_reg), + .I1(queue_id), + .I2(\S_AXI_AID_Q_reg[0] ), + .I3(cmd_b_empty), + .I4(cmd_empty), + .I5(need_to_split_q), + .O(multiple_id_non_split_reg_0)); + LUT5 #( + .INIT(32'hA888FFFF)) + multiple_id_non_split_i_2 + (.I0(multiple_id_non_split_i_3_n_0), + .I1(cmd_empty), + .I2(wr_cmd_ready), + .I3(almost_empty), + .I4(aresetn), .O(multiple_id_non_split_reg)); - LUT4 #( - .INIT(16'hFF8F)) + LUT6 #( + .INIT(64'hBAAAAAAAAAAAAAAA)) multiple_id_non_split_i_3 - (.I0(almost_empty), - .I1(rd_en), - .I2(aresetn), - .I3(cmd_empty), - .O(split_in_progress)); - LUT3 #( - .INIT(8'hB8)) - \queue_id[0]_i_1 - (.I0(\S_AXI_AID_Q_reg[0] ), - .I1(wr_en), - .I2(queue_id), - .O(\queue_id_reg[0] )); - LUT2 #( - .INIT(4'h2)) - s_axi_rlast_INST_0 - (.I0(m_axi_rlast), - .I1(rd_cmd_split), - .O(s_axi_rlast)); - (* SOFT_HLUTNM = "soft_lutpair9" *) - LUT2 #( - .INIT(4'h2)) - s_axi_rvalid_INST_0 - (.I0(m_axi_rvalid), + (.I0(cmd_b_empty), .I1(empty), - .O(s_axi_rvalid)); - LUT6 #( - .INIT(64'h00000000AAAAAEAA)) - split_in_progress_i_1 - (.I0(split_in_progress_reg_0), - .I1(cmd_empty_reg), - .I2(multiple_id_non_split), - .I3(need_to_split_q), - .I4(split_in_progress_i_3_n_0), - .I5(split_in_progress), - .O(split_in_progress_reg)); - LUT3 #( - .INIT(8'hFB)) - split_in_progress_i_3 - (.I0(full), - .I1(command_ongoing), - .I2(cmd_push_block), - .O(split_in_progress_i_3_n_0)); - (* SOFT_HLUTNM = "soft_lutpair5" *) - LUT5 #( - .INIT(32'hF1000000)) + .I2(s_axi_bready), + .I3(last_word), + .I4(m_axi_bvalid), + .I5(almost_b_empty), + .O(multiple_id_non_split_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair42" *) + LUT2 #( + .INIT(4'h8)) split_ongoing_i_1 - (.I0(full), - .I1(m_axi_arvalid_INST_0_i_1_n_0), - .I2(cmd_push_block), - .I3(command_ongoing), - .I4(m_axi_arready), + (.I0(m_axi_awvalid), + .I1(m_axi_awready), .O(\pushed_commands_reg[0] )); endmodule -module Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_a_axi3_conv - (E, - M_AXI_ARID, - m_axi_arsize, - m_axi_arburst, - m_axi_arcache, - m_axi_arprot, - m_axi_arqos, - m_axi_araddr, - m_axi_arvalid, - s_axi_rvalid, - m_axi_arlen, - m_axi_arlock, - s_axi_rlast, - m_axi_rready, - s_axi_arsize, - s_axi_arlen, +(* ORIG_REF_NAME = "axi_data_fifo_v2_1_10_fifo_gen" *) +module Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen_6 + (dout, + full, + empty, + SR, + din, + wr_en, + D, + m_axi_wvalid, + E, + s_axi_wready, + \queue_id_reg[0] , + split_in_progress_reg, + multiple_id_non_split_reg, aclk, - s_axi_arid, - s_axi_araddr, - s_axi_arburst, - s_axi_arlock, - s_axi_arcache, - s_axi_arprot, - s_axi_arqos, - m_axi_arready, - m_axi_rlast, - s_axi_rready, - m_axi_rvalid, + \S_AXI_AID_Q_reg[0] , + wr_cmd_ready, + Q, + split_in_progress_reg_0, + allow_split_cmd__1, + ram_full_i_reg, + command_ongoing, + cmd_push_block, + \S_AXI_ALEN_Q_reg[3] , + need_to_split_q, + \pushed_commands_reg[3] , + s_axi_wvalid, + m_axi_wready, aresetn, - s_axi_arvalid); + queue_id, + split_in_progress_reg_1, + cmd_empty_reg, + multiple_id_non_split); + output [4:0]dout; + output full; + output empty; + output [0:0]SR; + output [3:0]din; + output wr_en; + output [4:0]D; + output m_axi_wvalid; output [0:0]E; - output [0:0]M_AXI_ARID; - output [2:0]m_axi_arsize; - output [1:0]m_axi_arburst; - output [3:0]m_axi_arcache; - output [2:0]m_axi_arprot; - output [3:0]m_axi_arqos; - output [31:0]m_axi_araddr; - output m_axi_arvalid; - output s_axi_rvalid; - output [3:0]m_axi_arlen; - output [0:0]m_axi_arlock; - output s_axi_rlast; - output m_axi_rready; - input [2:0]s_axi_arsize; - input [7:0]s_axi_arlen; + output s_axi_wready; + output \queue_id_reg[0] ; + output split_in_progress_reg; + output multiple_id_non_split_reg; input aclk; - input [0:0]s_axi_arid; - input [31:0]s_axi_araddr; - input [1:0]s_axi_arburst; - input [0:0]s_axi_arlock; - input [3:0]s_axi_arcache; - input [2:0]s_axi_arprot; - input [3:0]s_axi_arqos; - input m_axi_arready; - input m_axi_rlast; - input s_axi_rready; - input m_axi_rvalid; + input \S_AXI_AID_Q_reg[0] ; + input wr_cmd_ready; + input [5:0]Q; + input split_in_progress_reg_0; + input allow_split_cmd__1; + input ram_full_i_reg; + input command_ongoing; + input cmd_push_block; + input [3:0]\S_AXI_ALEN_Q_reg[3] ; + input need_to_split_q; + input [3:0]\pushed_commands_reg[3] ; + input s_axi_wvalid; + input m_axi_wready; input aresetn; - input s_axi_arvalid; + input queue_id; + input split_in_progress_reg_1; + input cmd_empty_reg; + input multiple_id_non_split; + wire [4:0]D; wire [0:0]E; - wire [0:0]M_AXI_ARID; - wire [31:0]S_AXI_AADDR_Q; - wire [3:0]S_AXI_ALEN_Q; - wire \S_AXI_ALOCK_Q_reg_n_0_[0] ; - wire \USE_R_CHANNEL.cmd_queue_n_0 ; - wire \USE_R_CHANNEL.cmd_queue_n_1 ; - wire \USE_R_CHANNEL.cmd_queue_n_11 ; - wire \USE_R_CHANNEL.cmd_queue_n_16 ; - wire \USE_R_CHANNEL.cmd_queue_n_17 ; - wire \USE_R_CHANNEL.cmd_queue_n_18 ; - wire \USE_R_CHANNEL.cmd_queue_n_19 ; - wire \USE_R_CHANNEL.cmd_queue_n_20 ; - wire \USE_R_CHANNEL.cmd_queue_n_21 ; - wire \USE_R_CHANNEL.cmd_queue_n_4 ; - wire \USE_R_CHANNEL.cmd_queue_n_5 ; - wire \USE_R_CHANNEL.cmd_queue_n_6 ; - wire \USE_R_CHANNEL.cmd_queue_n_7 ; - wire \USE_R_CHANNEL.cmd_queue_n_8 ; - wire access_is_incr; - wire access_is_incr_q; + wire [5:0]Q; + wire [0:0]SR; + wire \S_AXI_AID_Q_reg[0] ; + wire [3:0]\S_AXI_ALEN_Q_reg[3] ; wire aclk; - wire [11:5]addr_step; - wire [11:5]addr_step_q; - wire almost_empty; - wire [1:0]areset_d; + wire allow_split_cmd__1; wire aresetn; - wire \cmd_depth[0]_i_1_n_0 ; + wire \cmd_depth[4]_i_2_n_0 ; wire \cmd_depth[5]_i_3_n_0 ; - wire \cmd_depth[5]_i_4_n_0 ; - wire [5:0]cmd_depth_reg__0; - wire cmd_empty; - wire cmd_empty0; - wire cmd_empty_i_1_n_0; - wire cmd_push; + wire cmd_empty_reg; wire cmd_push_block; wire command_ongoing; - wire command_ongoing_i_2_n_0; - wire [11:4]first_step; - wire [11:0]first_step_q; - wire \first_step_q[0]_i_1_n_0 ; - wire \first_step_q[10]_i_2_n_0 ; - wire \first_step_q[11]_i_2_n_0 ; - wire \first_step_q[1]_i_1_n_0 ; - wire \first_step_q[2]_i_1_n_0 ; - wire \first_step_q[3]_i_1_n_0 ; - wire \first_step_q[6]_i_2_n_0 ; - wire \first_step_q[7]_i_2_n_0 ; - wire \first_step_q[8]_i_2_n_0 ; - wire \first_step_q[9]_i_2_n_0 ; - wire incr_need_to_split__0; - wire [31:0]m_axi_araddr; - wire [1:0]m_axi_arburst; - wire [3:0]m_axi_arcache; - wire [3:0]m_axi_arlen; - wire [0:0]m_axi_arlock; - wire [2:0]m_axi_arprot; - wire [3:0]m_axi_arqos; - wire m_axi_arready; - wire [2:0]m_axi_arsize; - wire m_axi_arvalid; - wire m_axi_rlast; - wire m_axi_rready; - wire m_axi_rvalid; + wire [3:0]din; + wire [4:0]dout; + wire empty; + wire full; + wire m_axi_wready; + wire m_axi_wvalid; wire multiple_id_non_split; - wire multiple_id_non_split_i_2_n_0; + wire multiple_id_non_split_reg; wire need_to_split_q; - wire [31:0]next_mi_addr; - wire \next_mi_addr[11]_i_2_n_0 ; - wire \next_mi_addr[11]_i_3_n_0 ; - wire \next_mi_addr[11]_i_4_n_0 ; - wire \next_mi_addr[11]_i_5_n_0 ; - wire \next_mi_addr[11]_i_6_n_0 ; - wire \next_mi_addr[15]_i_2_n_0 ; - wire \next_mi_addr[15]_i_3_n_0 ; - wire \next_mi_addr[15]_i_4_n_0 ; - wire \next_mi_addr[15]_i_5_n_0 ; - wire \next_mi_addr[15]_i_6_n_0 ; - wire \next_mi_addr[15]_i_7_n_0 ; - wire \next_mi_addr[15]_i_8_n_0 ; - wire \next_mi_addr[15]_i_9_n_0 ; - wire \next_mi_addr[19]_i_2_n_0 ; - wire \next_mi_addr[19]_i_3_n_0 ; - wire \next_mi_addr[19]_i_4_n_0 ; - wire \next_mi_addr[19]_i_5_n_0 ; - wire \next_mi_addr[23]_i_2_n_0 ; - wire \next_mi_addr[23]_i_3_n_0 ; - wire \next_mi_addr[23]_i_4_n_0 ; - wire \next_mi_addr[23]_i_5_n_0 ; - wire \next_mi_addr[27]_i_2_n_0 ; - wire \next_mi_addr[27]_i_3_n_0 ; - wire \next_mi_addr[27]_i_4_n_0 ; - wire \next_mi_addr[27]_i_5_n_0 ; - wire \next_mi_addr[31]_i_2_n_0 ; - wire \next_mi_addr[31]_i_3_n_0 ; - wire \next_mi_addr[31]_i_4_n_0 ; - wire \next_mi_addr[31]_i_5_n_0 ; - wire \next_mi_addr[3]_i_2_n_0 ; - wire \next_mi_addr[3]_i_3_n_0 ; - wire \next_mi_addr[3]_i_4_n_0 ; - wire \next_mi_addr[3]_i_5_n_0 ; - wire \next_mi_addr[3]_i_6_n_0 ; - wire \next_mi_addr[7]_i_2_n_0 ; - wire \next_mi_addr[7]_i_3_n_0 ; - wire \next_mi_addr[7]_i_4_n_0 ; - wire \next_mi_addr[7]_i_5_n_0 ; - wire \next_mi_addr_reg[11]_i_1_n_0 ; - wire \next_mi_addr_reg[11]_i_1_n_1 ; - wire \next_mi_addr_reg[11]_i_1_n_2 ; - wire \next_mi_addr_reg[11]_i_1_n_3 ; - wire \next_mi_addr_reg[11]_i_1_n_4 ; - wire \next_mi_addr_reg[11]_i_1_n_5 ; - wire \next_mi_addr_reg[11]_i_1_n_6 ; - wire \next_mi_addr_reg[11]_i_1_n_7 ; - wire \next_mi_addr_reg[15]_i_1_n_0 ; - wire \next_mi_addr_reg[15]_i_1_n_1 ; - wire \next_mi_addr_reg[15]_i_1_n_2 ; - wire \next_mi_addr_reg[15]_i_1_n_3 ; - wire \next_mi_addr_reg[15]_i_1_n_4 ; - wire \next_mi_addr_reg[15]_i_1_n_5 ; - wire \next_mi_addr_reg[15]_i_1_n_6 ; - wire \next_mi_addr_reg[15]_i_1_n_7 ; - wire \next_mi_addr_reg[19]_i_1_n_0 ; - wire \next_mi_addr_reg[19]_i_1_n_1 ; - wire \next_mi_addr_reg[19]_i_1_n_2 ; - wire \next_mi_addr_reg[19]_i_1_n_3 ; - wire \next_mi_addr_reg[19]_i_1_n_4 ; - wire \next_mi_addr_reg[19]_i_1_n_5 ; - wire \next_mi_addr_reg[19]_i_1_n_6 ; - wire \next_mi_addr_reg[19]_i_1_n_7 ; - wire \next_mi_addr_reg[23]_i_1_n_0 ; - wire \next_mi_addr_reg[23]_i_1_n_1 ; - wire \next_mi_addr_reg[23]_i_1_n_2 ; - wire \next_mi_addr_reg[23]_i_1_n_3 ; - wire \next_mi_addr_reg[23]_i_1_n_4 ; - wire \next_mi_addr_reg[23]_i_1_n_5 ; - wire \next_mi_addr_reg[23]_i_1_n_6 ; - wire \next_mi_addr_reg[23]_i_1_n_7 ; - wire \next_mi_addr_reg[27]_i_1_n_0 ; - wire \next_mi_addr_reg[27]_i_1_n_1 ; - wire \next_mi_addr_reg[27]_i_1_n_2 ; - wire \next_mi_addr_reg[27]_i_1_n_3 ; - wire \next_mi_addr_reg[27]_i_1_n_4 ; - wire \next_mi_addr_reg[27]_i_1_n_5 ; - wire \next_mi_addr_reg[27]_i_1_n_6 ; - wire \next_mi_addr_reg[27]_i_1_n_7 ; - wire \next_mi_addr_reg[31]_i_1_n_1 ; - wire \next_mi_addr_reg[31]_i_1_n_2 ; - wire \next_mi_addr_reg[31]_i_1_n_3 ; - wire \next_mi_addr_reg[31]_i_1_n_4 ; - wire \next_mi_addr_reg[31]_i_1_n_5 ; - wire \next_mi_addr_reg[31]_i_1_n_6 ; - wire \next_mi_addr_reg[31]_i_1_n_7 ; - wire \next_mi_addr_reg[3]_i_1_n_0 ; - wire \next_mi_addr_reg[3]_i_1_n_1 ; - wire \next_mi_addr_reg[3]_i_1_n_2 ; - wire \next_mi_addr_reg[3]_i_1_n_3 ; - wire \next_mi_addr_reg[3]_i_1_n_4 ; - wire \next_mi_addr_reg[3]_i_1_n_5 ; - wire \next_mi_addr_reg[3]_i_1_n_6 ; - wire \next_mi_addr_reg[3]_i_1_n_7 ; - wire \next_mi_addr_reg[7]_i_1_n_0 ; - wire \next_mi_addr_reg[7]_i_1_n_1 ; - wire \next_mi_addr_reg[7]_i_1_n_2 ; - wire \next_mi_addr_reg[7]_i_1_n_3 ; - wire \next_mi_addr_reg[7]_i_1_n_4 ; - wire \next_mi_addr_reg[7]_i_1_n_5 ; - wire \next_mi_addr_reg[7]_i_1_n_6 ; - wire \next_mi_addr_reg[7]_i_1_n_7 ; - wire [3:0]num_transactions_q; - wire [3:0]p_0_in; - wire \pushed_commands[3]_i_1_n_0 ; - wire [3:0]pushed_commands_reg__0; - wire pushed_new_cmd; + wire [3:0]\pushed_commands_reg[3] ; wire queue_id; - wire rd_cmd_ready; - wire [31:0]s_axi_araddr; - wire [1:0]s_axi_arburst; - wire [3:0]s_axi_arcache; - wire [0:0]s_axi_arid; - wire [7:0]s_axi_arlen; - wire [0:0]s_axi_arlock; - wire [2:0]s_axi_arprot; - wire [3:0]s_axi_arqos; - wire [2:0]s_axi_arsize; - wire s_axi_arvalid; - wire s_axi_rlast; - wire s_axi_rready; - wire s_axi_rvalid; - wire [6:0]size_mask; - wire [31:0]size_mask_q; - wire split_in_progress_i_2_n_0; - wire split_in_progress_reg_n_0; - wire split_ongoing; - wire [3:3]\NLW_next_mi_addr_reg[31]_i_1_CO_UNCONNECTED ; - - FDRE \S_AXI_AADDR_Q_reg[0] - (.C(aclk), - .CE(E), - .D(s_axi_araddr[0]), - .Q(S_AXI_AADDR_Q[0]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \S_AXI_AADDR_Q_reg[10] - (.C(aclk), - .CE(E), - .D(s_axi_araddr[10]), - .Q(S_AXI_AADDR_Q[10]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \S_AXI_AADDR_Q_reg[11] - (.C(aclk), - .CE(E), - .D(s_axi_araddr[11]), - .Q(S_AXI_AADDR_Q[11]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \S_AXI_AADDR_Q_reg[12] - (.C(aclk), - .CE(E), - .D(s_axi_araddr[12]), - .Q(S_AXI_AADDR_Q[12]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \S_AXI_AADDR_Q_reg[13] - (.C(aclk), - .CE(E), - .D(s_axi_araddr[13]), - .Q(S_AXI_AADDR_Q[13]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \S_AXI_AADDR_Q_reg[14] - (.C(aclk), - .CE(E), - .D(s_axi_araddr[14]), - .Q(S_AXI_AADDR_Q[14]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \S_AXI_AADDR_Q_reg[15] - (.C(aclk), - .CE(E), - .D(s_axi_araddr[15]), - .Q(S_AXI_AADDR_Q[15]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \S_AXI_AADDR_Q_reg[16] - (.C(aclk), - .CE(E), - .D(s_axi_araddr[16]), - .Q(S_AXI_AADDR_Q[16]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \S_AXI_AADDR_Q_reg[17] - (.C(aclk), - .CE(E), - .D(s_axi_araddr[17]), - .Q(S_AXI_AADDR_Q[17]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \S_AXI_AADDR_Q_reg[18] - (.C(aclk), - .CE(E), - .D(s_axi_araddr[18]), - .Q(S_AXI_AADDR_Q[18]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \S_AXI_AADDR_Q_reg[19] - (.C(aclk), - .CE(E), - .D(s_axi_araddr[19]), - .Q(S_AXI_AADDR_Q[19]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \S_AXI_AADDR_Q_reg[1] - (.C(aclk), - .CE(E), - .D(s_axi_araddr[1]), - .Q(S_AXI_AADDR_Q[1]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \S_AXI_AADDR_Q_reg[20] - (.C(aclk), - .CE(E), - .D(s_axi_araddr[20]), - .Q(S_AXI_AADDR_Q[20]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \S_AXI_AADDR_Q_reg[21] - (.C(aclk), - .CE(E), - .D(s_axi_araddr[21]), - .Q(S_AXI_AADDR_Q[21]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \S_AXI_AADDR_Q_reg[22] - (.C(aclk), - .CE(E), - .D(s_axi_araddr[22]), - .Q(S_AXI_AADDR_Q[22]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \S_AXI_AADDR_Q_reg[23] - (.C(aclk), - .CE(E), - .D(s_axi_araddr[23]), - .Q(S_AXI_AADDR_Q[23]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \S_AXI_AADDR_Q_reg[24] - (.C(aclk), + wire \queue_id_reg[0] ; + wire ram_full_i_reg; + wire s_axi_wready; + wire s_axi_wvalid; + wire split_in_progress_reg; + wire split_in_progress_reg_0; + wire split_in_progress_reg_1; + wire wr_cmd_ready; + wire wr_en; + wire NLW_fifo_gen_inst_almost_empty_UNCONNECTED; + wire NLW_fifo_gen_inst_almost_full_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axis_overflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED; + wire NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED; + wire NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axis_underflow_UNCONNECTED; + wire NLW_fifo_gen_inst_dbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED; + wire NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED; + wire NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED; + wire NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED; + wire NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED; + wire NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED; + wire NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED; + wire NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED; + wire NLW_fifo_gen_inst_overflow_UNCONNECTED; + wire NLW_fifo_gen_inst_prog_empty_UNCONNECTED; + wire NLW_fifo_gen_inst_prog_full_UNCONNECTED; + wire NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED; + wire NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED; + wire NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED; + wire NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED; + wire NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED; + wire NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED; + wire NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED; + wire NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED; + wire NLW_fifo_gen_inst_sbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_underflow_UNCONNECTED; + wire NLW_fifo_gen_inst_valid_UNCONNECTED; + wire NLW_fifo_gen_inst_wr_ack_UNCONNECTED; + wire NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED; + wire [4:0]NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED; + wire [4:0]NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED; + wire [4:0]NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED; + wire [4:0]NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED; + wire [4:0]NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED; + wire [4:0]NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED; + wire [4:0]NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED; + wire [4:0]NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED; + wire [4:0]NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED; + wire [10:0]NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED; + wire [10:0]NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED; + wire [10:0]NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED; + wire [10:0]NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED; + wire [10:0]NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED; + wire [10:0]NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED; + wire [10:0]NLW_fifo_gen_inst_axis_data_count_UNCONNECTED; + wire [10:0]NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED; + wire [10:0]NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED; + wire [5:0]NLW_fifo_gen_inst_data_count_UNCONNECTED; + wire [31:0]NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED; + wire [1:0]NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED; + wire [7:0]NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED; + wire [1:0]NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED; + wire [2:0]NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED; + wire [2:0]NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED; + wire [0:0]NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED; + wire [31:0]NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED; + wire [1:0]NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED; + wire [7:0]NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED; + wire [1:0]NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED; + wire [2:0]NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED; + wire [2:0]NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED; + wire [0:0]NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED; + wire [63:0]NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED; + wire [7:0]NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED; + wire [0:0]NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED; + wire [63:0]NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED; + wire [7:0]NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED; + wire [5:0]NLW_fifo_gen_inst_rd_data_count_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED; + wire [1:0]NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED; + wire [0:0]NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED; + wire [63:0]NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED; + wire [1:0]NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED; + wire [0:0]NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED; + wire [5:0]NLW_fifo_gen_inst_wr_data_count_UNCONNECTED; + + LUT1 #( + .INIT(2'h1)) + S_AXI_AREADY_I_i_1 + (.I0(aresetn), + .O(SR)); + LUT3 #( + .INIT(8'h69)) + \cmd_depth[1]_i_1 + (.I0(Q[0]), + .I1(\cmd_depth[4]_i_2_n_0 ), + .I2(Q[1]), + .O(D[0])); + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT4 #( + .INIT(16'h78E1)) + \cmd_depth[2]_i_1 + (.I0(Q[0]), + .I1(\cmd_depth[4]_i_2_n_0 ), + .I2(Q[2]), + .I3(Q[1]), + .O(D[1])); + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT5 #( + .INIT(32'h7F80FE01)) + \cmd_depth[3]_i_1 + (.I0(\cmd_depth[4]_i_2_n_0 ), + .I1(Q[0]), + .I2(Q[1]), + .I3(Q[3]), + .I4(Q[2]), + .O(D[2])); + LUT6 #( + .INIT(64'h7FFF8000FFFE0001)) + \cmd_depth[4]_i_1 + (.I0(Q[1]), + .I1(Q[0]), + .I2(\cmd_depth[4]_i_2_n_0 ), + .I3(Q[2]), + .I4(Q[4]), + .I5(Q[3]), + .O(D[3])); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT2 #( + .INIT(4'h2)) + \cmd_depth[4]_i_2 + (.I0(wr_en), + .I1(wr_cmd_ready), + .O(\cmd_depth[4]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT2 #( + .INIT(4'h6)) + \cmd_depth[5]_i_1 + (.I0(wr_en), + .I1(wr_cmd_ready), + .O(E)); + LUT4 #( + .INIT(16'h78E1)) + \cmd_depth[5]_i_2 + (.I0(\cmd_depth[5]_i_3_n_0 ), + .I1(Q[3]), + .I2(Q[5]), + .I3(Q[4]), + .O(D[4])); + LUT6 #( + .INIT(64'h5D55555555554544)) + \cmd_depth[5]_i_3 + (.I0(Q[3]), + .I1(Q[2]), + .I2(wr_cmd_ready), + .I3(wr_en), + .I4(Q[0]), + .I5(Q[1]), + .O(\cmd_depth[5]_i_3_n_0 )); + (* C_ADD_NGC_CONSTRAINT = "0" *) + (* C_APPLICATION_TYPE_AXIS = "0" *) + (* C_APPLICATION_TYPE_RACH = "0" *) + (* C_APPLICATION_TYPE_RDCH = "0" *) + (* C_APPLICATION_TYPE_WACH = "0" *) + (* C_APPLICATION_TYPE_WDCH = "0" *) + (* C_APPLICATION_TYPE_WRCH = "0" *) + (* C_AXIS_TDATA_WIDTH = "64" *) + (* C_AXIS_TDEST_WIDTH = "4" *) + (* C_AXIS_TID_WIDTH = "8" *) + (* C_AXIS_TKEEP_WIDTH = "4" *) + (* C_AXIS_TSTRB_WIDTH = "4" *) + (* C_AXIS_TUSER_WIDTH = "4" *) + (* C_AXIS_TYPE = "0" *) + (* C_AXI_ADDR_WIDTH = "32" *) + (* C_AXI_ARUSER_WIDTH = "1" *) + (* C_AXI_AWUSER_WIDTH = "1" *) + (* C_AXI_BUSER_WIDTH = "1" *) + (* C_AXI_DATA_WIDTH = "64" *) + (* C_AXI_ID_WIDTH = "4" *) + (* C_AXI_LEN_WIDTH = "8" *) + (* C_AXI_LOCK_WIDTH = "2" *) + (* C_AXI_RUSER_WIDTH = "1" *) + (* C_AXI_TYPE = "0" *) + (* C_AXI_WUSER_WIDTH = "1" *) + (* C_COMMON_CLOCK = "1" *) + (* C_COUNT_TYPE = "0" *) + (* C_DATA_COUNT_WIDTH = "6" *) + (* C_DEFAULT_VALUE = "BlankString" *) + (* C_DIN_WIDTH = "5" *) + (* C_DIN_WIDTH_AXIS = "1" *) + (* C_DIN_WIDTH_RACH = "32" *) + (* C_DIN_WIDTH_RDCH = "64" *) + (* C_DIN_WIDTH_WACH = "32" *) + (* C_DIN_WIDTH_WDCH = "64" *) + (* C_DIN_WIDTH_WRCH = "2" *) + (* C_DOUT_RST_VAL = "0" *) + (* C_DOUT_WIDTH = "5" *) + (* C_ENABLE_RLOCS = "0" *) + (* C_ENABLE_RST_SYNC = "1" *) + (* C_EN_SAFETY_CKT = "0" *) + (* C_ERROR_INJECTION_TYPE = "0" *) + (* C_ERROR_INJECTION_TYPE_AXIS = "0" *) + (* C_ERROR_INJECTION_TYPE_RACH = "0" *) + (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) + (* C_ERROR_INJECTION_TYPE_WACH = "0" *) + (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) + (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) + (* C_FAMILY = "zynq" *) + (* C_FULL_FLAGS_RST_VAL = "0" *) + (* C_HAS_ALMOST_EMPTY = "0" *) + (* C_HAS_ALMOST_FULL = "0" *) + (* C_HAS_AXIS_TDATA = "0" *) + (* C_HAS_AXIS_TDEST = "0" *) + (* C_HAS_AXIS_TID = "0" *) + (* C_HAS_AXIS_TKEEP = "0" *) + (* C_HAS_AXIS_TLAST = "0" *) + (* C_HAS_AXIS_TREADY = "1" *) + (* C_HAS_AXIS_TSTRB = "0" *) + (* C_HAS_AXIS_TUSER = "0" *) + (* C_HAS_AXI_ARUSER = "0" *) + (* C_HAS_AXI_AWUSER = "0" *) + (* C_HAS_AXI_BUSER = "0" *) + (* C_HAS_AXI_ID = "0" *) + (* C_HAS_AXI_RD_CHANNEL = "0" *) + (* C_HAS_AXI_RUSER = "0" *) + (* C_HAS_AXI_WR_CHANNEL = "0" *) + (* C_HAS_AXI_WUSER = "0" *) + (* C_HAS_BACKUP = "0" *) + (* C_HAS_DATA_COUNT = "0" *) + (* C_HAS_DATA_COUNTS_AXIS = "0" *) + (* C_HAS_DATA_COUNTS_RACH = "0" *) + (* C_HAS_DATA_COUNTS_RDCH = "0" *) + (* C_HAS_DATA_COUNTS_WACH = "0" *) + (* C_HAS_DATA_COUNTS_WDCH = "0" *) + (* C_HAS_DATA_COUNTS_WRCH = "0" *) + (* C_HAS_INT_CLK = "0" *) + (* C_HAS_MASTER_CE = "0" *) + (* C_HAS_MEMINIT_FILE = "0" *) + (* C_HAS_OVERFLOW = "0" *) + (* C_HAS_PROG_FLAGS_AXIS = "0" *) + (* C_HAS_PROG_FLAGS_RACH = "0" *) + (* C_HAS_PROG_FLAGS_RDCH = "0" *) + (* C_HAS_PROG_FLAGS_WACH = "0" *) + (* C_HAS_PROG_FLAGS_WDCH = "0" *) + (* C_HAS_PROG_FLAGS_WRCH = "0" *) + (* C_HAS_RD_DATA_COUNT = "0" *) + (* C_HAS_RD_RST = "0" *) + (* C_HAS_RST = "1" *) + (* C_HAS_SLAVE_CE = "0" *) + (* C_HAS_SRST = "0" *) + (* C_HAS_UNDERFLOW = "0" *) + (* C_HAS_VALID = "0" *) + (* C_HAS_WR_ACK = "0" *) + (* C_HAS_WR_DATA_COUNT = "0" *) + (* C_HAS_WR_RST = "0" *) + (* C_IMPLEMENTATION_TYPE = "0" *) + (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) + (* C_IMPLEMENTATION_TYPE_RACH = "1" *) + (* C_IMPLEMENTATION_TYPE_RDCH = "1" *) + (* C_IMPLEMENTATION_TYPE_WACH = "1" *) + (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) + (* C_IMPLEMENTATION_TYPE_WRCH = "1" *) + (* C_INIT_WR_PNTR_VAL = "0" *) + (* C_INTERFACE_TYPE = "0" *) + (* C_MEMORY_TYPE = "2" *) + (* C_MIF_FILE_NAME = "BlankString" *) + (* C_MSGON_VAL = "1" *) + (* C_OPTIMIZATION_MODE = "0" *) + (* C_OVERFLOW_LOW = "0" *) + (* C_POWER_SAVING_MODE = "0" *) + (* C_PRELOAD_LATENCY = "0" *) + (* C_PRELOAD_REGS = "1" *) + (* C_PRIM_FIFO_TYPE = "512x36" *) + (* C_PRIM_FIFO_TYPE_AXIS = "512x36" *) + (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) + (* C_PRIM_FIFO_TYPE_RDCH = "512x36" *) + (* C_PRIM_FIFO_TYPE_WACH = "512x36" *) + (* C_PRIM_FIFO_TYPE_WDCH = "512x36" *) + (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL = "4" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) + (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "5" *) + (* C_PROG_EMPTY_TYPE = "0" *) + (* C_PROG_EMPTY_TYPE_AXIS = "0" *) + (* C_PROG_EMPTY_TYPE_RACH = "0" *) + (* C_PROG_EMPTY_TYPE_RDCH = "0" *) + (* C_PROG_EMPTY_TYPE_WACH = "0" *) + (* C_PROG_EMPTY_TYPE_WDCH = "0" *) + (* C_PROG_EMPTY_TYPE_WRCH = "0" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL = "31" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) + (* C_PROG_FULL_THRESH_NEGATE_VAL = "30" *) + (* C_PROG_FULL_TYPE = "0" *) + (* C_PROG_FULL_TYPE_AXIS = "0" *) + (* C_PROG_FULL_TYPE_RACH = "0" *) + (* C_PROG_FULL_TYPE_RDCH = "0" *) + (* C_PROG_FULL_TYPE_WACH = "0" *) + (* C_PROG_FULL_TYPE_WDCH = "0" *) + (* C_PROG_FULL_TYPE_WRCH = "0" *) + (* C_RACH_TYPE = "0" *) + (* C_RDCH_TYPE = "0" *) + (* C_RD_DATA_COUNT_WIDTH = "6" *) + (* C_RD_DEPTH = "32" *) + (* C_RD_FREQ = "1" *) + (* C_RD_PNTR_WIDTH = "5" *) + (* C_REG_SLICE_MODE_AXIS = "0" *) + (* C_REG_SLICE_MODE_RACH = "0" *) + (* C_REG_SLICE_MODE_RDCH = "0" *) + (* C_REG_SLICE_MODE_WACH = "0" *) + (* C_REG_SLICE_MODE_WDCH = "0" *) + (* C_REG_SLICE_MODE_WRCH = "0" *) + (* C_SELECT_XPM = "0" *) + (* C_SYNCHRONIZER_STAGE = "3" *) + (* C_UNDERFLOW_LOW = "0" *) + (* C_USE_COMMON_OVERFLOW = "0" *) + (* C_USE_COMMON_UNDERFLOW = "0" *) + (* C_USE_DEFAULT_SETTINGS = "0" *) + (* C_USE_DOUT_RST = "0" *) + (* C_USE_ECC = "0" *) + (* C_USE_ECC_AXIS = "0" *) + (* C_USE_ECC_RACH = "0" *) + (* C_USE_ECC_RDCH = "0" *) + (* C_USE_ECC_WACH = "0" *) + (* C_USE_ECC_WDCH = "0" *) + (* C_USE_ECC_WRCH = "0" *) + (* C_USE_EMBEDDED_REG = "0" *) + (* C_USE_FIFO16_FLAGS = "0" *) + (* C_USE_FWFT_DATA_COUNT = "1" *) + (* C_USE_PIPELINE_REG = "0" *) + (* C_VALID_LOW = "0" *) + (* C_WACH_TYPE = "0" *) + (* C_WDCH_TYPE = "0" *) + (* C_WRCH_TYPE = "0" *) + (* C_WR_ACK_LOW = "0" *) + (* C_WR_DATA_COUNT_WIDTH = "6" *) + (* C_WR_DEPTH = "32" *) + (* C_WR_DEPTH_AXIS = "1024" *) + (* C_WR_DEPTH_RACH = "16" *) + (* C_WR_DEPTH_RDCH = "1024" *) + (* C_WR_DEPTH_WACH = "16" *) + (* C_WR_DEPTH_WDCH = "1024" *) + (* C_WR_DEPTH_WRCH = "16" *) + (* C_WR_FREQ = "1" *) + (* C_WR_PNTR_WIDTH = "5" *) + (* C_WR_PNTR_WIDTH_AXIS = "10" *) + (* C_WR_PNTR_WIDTH_RACH = "4" *) + (* C_WR_PNTR_WIDTH_RDCH = "10" *) + (* C_WR_PNTR_WIDTH_WACH = "4" *) + (* C_WR_PNTR_WIDTH_WDCH = "10" *) + (* C_WR_PNTR_WIDTH_WRCH = "4" *) + (* C_WR_RESPONSE_LATENCY = "1" *) + Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1 fifo_gen_inst + (.almost_empty(NLW_fifo_gen_inst_almost_empty_UNCONNECTED), + .almost_full(NLW_fifo_gen_inst_almost_full_UNCONNECTED), + .axi_ar_data_count(NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED[4:0]), + .axi_ar_dbiterr(NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED), + .axi_ar_injectdbiterr(1'b0), + .axi_ar_injectsbiterr(1'b0), + .axi_ar_overflow(NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED), + .axi_ar_prog_empty(NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED), + .axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), + .axi_ar_prog_full(NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED), + .axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), + .axi_ar_rd_data_count(NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED[4:0]), + .axi_ar_sbiterr(NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED), + .axi_ar_underflow(NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED), + .axi_ar_wr_data_count(NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED[4:0]), + .axi_aw_data_count(NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED[4:0]), + .axi_aw_dbiterr(NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED), + .axi_aw_injectdbiterr(1'b0), + .axi_aw_injectsbiterr(1'b0), + .axi_aw_overflow(NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED), + .axi_aw_prog_empty(NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED), + .axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), + .axi_aw_prog_full(NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED), + .axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), + .axi_aw_rd_data_count(NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED[4:0]), + .axi_aw_sbiterr(NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED), + .axi_aw_underflow(NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED), + .axi_aw_wr_data_count(NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED[4:0]), + .axi_b_data_count(NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED[4:0]), + .axi_b_dbiterr(NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED), + .axi_b_injectdbiterr(1'b0), + .axi_b_injectsbiterr(1'b0), + .axi_b_overflow(NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED), + .axi_b_prog_empty(NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED), + .axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), + .axi_b_prog_full(NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED), + .axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), + .axi_b_rd_data_count(NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED[4:0]), + .axi_b_sbiterr(NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED), + .axi_b_underflow(NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED), + .axi_b_wr_data_count(NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED[4:0]), + .axi_r_data_count(NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED[10:0]), + .axi_r_dbiterr(NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED), + .axi_r_injectdbiterr(1'b0), + .axi_r_injectsbiterr(1'b0), + .axi_r_overflow(NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED), + .axi_r_prog_empty(NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED), + .axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .axi_r_prog_full(NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED), + .axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .axi_r_rd_data_count(NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED[10:0]), + .axi_r_sbiterr(NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED), + .axi_r_underflow(NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED), + .axi_r_wr_data_count(NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED[10:0]), + .axi_w_data_count(NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED[10:0]), + .axi_w_dbiterr(NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED), + .axi_w_injectdbiterr(1'b0), + .axi_w_injectsbiterr(1'b0), + .axi_w_overflow(NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED), + .axi_w_prog_empty(NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED), + .axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .axi_w_prog_full(NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED), + .axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .axi_w_rd_data_count(NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED[10:0]), + .axi_w_sbiterr(NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED), + .axi_w_underflow(NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED), + .axi_w_wr_data_count(NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED[10:0]), + .axis_data_count(NLW_fifo_gen_inst_axis_data_count_UNCONNECTED[10:0]), + .axis_dbiterr(NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED), + .axis_injectdbiterr(1'b0), + .axis_injectsbiterr(1'b0), + .axis_overflow(NLW_fifo_gen_inst_axis_overflow_UNCONNECTED), + .axis_prog_empty(NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED), + .axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .axis_prog_full(NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED), + .axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .axis_rd_data_count(NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED[10:0]), + .axis_sbiterr(NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED), + .axis_underflow(NLW_fifo_gen_inst_axis_underflow_UNCONNECTED), + .axis_wr_data_count(NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED[10:0]), + .backup(1'b0), + .backup_marker(1'b0), + .clk(aclk), + .data_count(NLW_fifo_gen_inst_data_count_UNCONNECTED[5:0]), + .dbiterr(NLW_fifo_gen_inst_dbiterr_UNCONNECTED), + .din({\S_AXI_AID_Q_reg[0] ,din}), + .dout(dout), + .empty(empty), + .full(full), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + .int_clk(1'b0), + .m_aclk(1'b0), + .m_aclk_en(1'b0), + .m_axi_araddr(NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED[31:0]), + .m_axi_arburst(NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED[1:0]), + .m_axi_arcache(NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED[3:0]), + .m_axi_arid(NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED[3:0]), + .m_axi_arlen(NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED[7:0]), + .m_axi_arlock(NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED[1:0]), + .m_axi_arprot(NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED[2:0]), + .m_axi_arqos(NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED[3:0]), + .m_axi_arready(1'b0), + .m_axi_arregion(NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED[3:0]), + .m_axi_arsize(NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED[2:0]), + .m_axi_aruser(NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED[0]), + .m_axi_arvalid(NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED), + .m_axi_awaddr(NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED[31:0]), + .m_axi_awburst(NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED[1:0]), + .m_axi_awcache(NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED[3:0]), + .m_axi_awid(NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED[3:0]), + .m_axi_awlen(NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED[7:0]), + .m_axi_awlock(NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED[1:0]), + .m_axi_awprot(NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED[2:0]), + .m_axi_awqos(NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED[3:0]), + .m_axi_awready(1'b0), + .m_axi_awregion(NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED[3:0]), + .m_axi_awsize(NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED[2:0]), + .m_axi_awuser(NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED[0]), + .m_axi_awvalid(NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED), + .m_axi_bid({1'b0,1'b0,1'b0,1'b0}), + .m_axi_bready(NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED), + .m_axi_bresp({1'b0,1'b0}), + .m_axi_buser(1'b0), + .m_axi_bvalid(1'b0), + .m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .m_axi_rid({1'b0,1'b0,1'b0,1'b0}), + .m_axi_rlast(1'b0), + .m_axi_rready(NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED), + .m_axi_rresp({1'b0,1'b0}), + .m_axi_ruser(1'b0), + .m_axi_rvalid(1'b0), + .m_axi_wdata(NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED[63:0]), + .m_axi_wid(NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED[3:0]), + .m_axi_wlast(NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED), + .m_axi_wready(1'b0), + .m_axi_wstrb(NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED[7:0]), + .m_axi_wuser(NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED[0]), + .m_axi_wvalid(NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED), + .m_axis_tdata(NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED[63:0]), + .m_axis_tdest(NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED[3:0]), + .m_axis_tid(NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED[7:0]), + .m_axis_tkeep(NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED[3:0]), + .m_axis_tlast(NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED), + .m_axis_tready(1'b0), + .m_axis_tstrb(NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED[3:0]), + .m_axis_tuser(NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED[3:0]), + .m_axis_tvalid(NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED), + .overflow(NLW_fifo_gen_inst_overflow_UNCONNECTED), + .prog_empty(NLW_fifo_gen_inst_prog_empty_UNCONNECTED), + .prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_full(NLW_fifo_gen_inst_prog_full_UNCONNECTED), + .prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0}), + .rd_clk(1'b0), + .rd_data_count(NLW_fifo_gen_inst_rd_data_count_UNCONNECTED[5:0]), + .rd_en(wr_cmd_ready), + .rd_rst(1'b0), + .rd_rst_busy(NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED), + .rst(SR), + .s_aclk(1'b0), + .s_aclk_en(1'b0), + .s_aresetn(1'b0), + .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_arburst({1'b0,1'b0}), + .s_axi_arcache({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arid({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_arlock({1'b0,1'b0}), + .s_axi_arprot({1'b0,1'b0,1'b0}), + .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arready(NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED), + .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arsize({1'b0,1'b0,1'b0}), + .s_axi_aruser(1'b0), + .s_axi_arvalid(1'b0), + .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_awburst({1'b0,1'b0}), + .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awid({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_awlock({1'b0,1'b0}), + .s_axi_awprot({1'b0,1'b0,1'b0}), + .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awready(NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED), + .s_axi_awregion({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awsize({1'b0,1'b0,1'b0}), + .s_axi_awuser(1'b0), + .s_axi_awvalid(1'b0), + .s_axi_bid(NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED[3:0]), + .s_axi_bready(1'b0), + .s_axi_bresp(NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED[1:0]), + .s_axi_buser(NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED[0]), + .s_axi_bvalid(NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED), + .s_axi_rdata(NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED[63:0]), + .s_axi_rid(NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED[3:0]), + .s_axi_rlast(NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED), + .s_axi_rready(1'b0), + .s_axi_rresp(NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED[1:0]), + .s_axi_ruser(NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED[0]), + .s_axi_rvalid(NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED), + .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_wid({1'b0,1'b0,1'b0,1'b0}), + .s_axi_wlast(1'b0), + .s_axi_wready(NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED), + .s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_wuser(1'b0), + .s_axi_wvalid(1'b0), + .s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axis_tdest({1'b0,1'b0,1'b0,1'b0}), + .s_axis_tid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axis_tkeep({1'b0,1'b0,1'b0,1'b0}), + .s_axis_tlast(1'b0), + .s_axis_tready(NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED), + .s_axis_tstrb({1'b0,1'b0,1'b0,1'b0}), + .s_axis_tuser({1'b0,1'b0,1'b0,1'b0}), + .s_axis_tvalid(1'b0), + .sbiterr(NLW_fifo_gen_inst_sbiterr_UNCONNECTED), + .sleep(1'b0), + .srst(1'b0), + .underflow(NLW_fifo_gen_inst_underflow_UNCONNECTED), + .valid(NLW_fifo_gen_inst_valid_UNCONNECTED), + .wr_ack(NLW_fifo_gen_inst_wr_ack_UNCONNECTED), + .wr_clk(1'b0), + .wr_data_count(NLW_fifo_gen_inst_wr_data_count_UNCONNECTED[5:0]), + .wr_en(wr_en), + .wr_rst(1'b0), + .wr_rst_busy(NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED)); + LUT6 #( + .INIT(64'h0000000000540000)) + fifo_gen_inst_i_1 + (.I0(full), + .I1(split_in_progress_reg_0), + .I2(allow_split_cmd__1), + .I3(ram_full_i_reg), + .I4(command_ongoing), + .I5(cmd_push_block), + .O(wr_en)); + LUT6 #( + .INIT(64'hEEEEEEEEEEEEEEEA)) + \m_axi_awlen[0]_INST_0 + (.I0(\S_AXI_ALEN_Q_reg[3] [0]), + .I1(need_to_split_q), + .I2(\pushed_commands_reg[3] [2]), + .I3(\pushed_commands_reg[3] [3]), + .I4(\pushed_commands_reg[3] [1]), + .I5(\pushed_commands_reg[3] [0]), + .O(din[0])); + LUT6 #( + .INIT(64'hEEEEEEEEEEEEEEEA)) + \m_axi_awlen[1]_INST_0 + (.I0(\S_AXI_ALEN_Q_reg[3] [1]), + .I1(need_to_split_q), + .I2(\pushed_commands_reg[3] [2]), + .I3(\pushed_commands_reg[3] [3]), + .I4(\pushed_commands_reg[3] [1]), + .I5(\pushed_commands_reg[3] [0]), + .O(din[1])); + LUT6 #( + .INIT(64'hEEEEEEEEEEEEEEEA)) + \m_axi_awlen[2]_INST_0 + (.I0(\S_AXI_ALEN_Q_reg[3] [2]), + .I1(need_to_split_q), + .I2(\pushed_commands_reg[3] [2]), + .I3(\pushed_commands_reg[3] [3]), + .I4(\pushed_commands_reg[3] [1]), + .I5(\pushed_commands_reg[3] [0]), + .O(din[2])); + LUT6 #( + .INIT(64'hEEEEEEEEEEEEEEEA)) + \m_axi_awlen[3]_INST_0 + (.I0(\S_AXI_ALEN_Q_reg[3] [3]), + .I1(need_to_split_q), + .I2(\pushed_commands_reg[3] [2]), + .I3(\pushed_commands_reg[3] [3]), + .I4(\pushed_commands_reg[3] [1]), + .I5(\pushed_commands_reg[3] [0]), + .O(din[3])); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT2 #( + .INIT(4'h2)) + m_axi_wvalid_INST_0 + (.I0(s_axi_wvalid), + .I1(empty), + .O(m_axi_wvalid)); + LUT6 #( + .INIT(64'h00000000BEAAAAAA)) + multiple_id_non_split_i_1 + (.I0(multiple_id_non_split), + .I1(queue_id), + .I2(\S_AXI_AID_Q_reg[0] ), + .I3(wr_en), + .I4(split_in_progress_reg_0), + .I5(cmd_empty_reg), + .O(multiple_id_non_split_reg)); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT3 #( + .INIT(8'hB8)) + \queue_id[0]_i_1 + (.I0(\S_AXI_AID_Q_reg[0] ), + .I1(wr_en), + .I2(queue_id), + .O(\queue_id_reg[0] )); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT3 #( + .INIT(8'h40)) + s_axi_wready_INST_0 + (.I0(empty), + .I1(s_axi_wvalid), + .I2(m_axi_wready), + .O(s_axi_wready)); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT4 #( + .INIT(16'h00EA)) + split_in_progress_i_1 + (.I0(split_in_progress_reg_1), + .I1(wr_en), + .I2(allow_split_cmd__1), + .I3(cmd_empty_reg), + .O(split_in_progress_reg)); +endmodule + +(* ORIG_REF_NAME = "axi_data_fifo_v2_1_10_fifo_gen" *) +module Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen__parameterized0 + (din, + wr_en, + rd_en, + D, + split_ongoing_reg, + m_axi_rready, + s_axi_rvalid, + s_axi_rlast, + E, + cmd_push_block_reg, + \cmd_depth_reg[5] , + m_axi_arvalid, + S_AXI_AREADY_I_reg, + \queue_id_reg[0] , + command_ongoing_reg, + multiple_id_non_split_reg, + split_in_progress_reg, + aclk, + aresetn_0, + Q, + cmd_push_block, + command_ongoing, + almost_empty, + cmd_empty, + aresetn, + need_to_split_q, + access_is_incr_q, + \num_transactions_q_reg[3] , + \pushed_commands_reg[3] , + m_axi_rvalid, + s_axi_rready, + m_axi_rlast, + m_axi_arready, + multiple_id_non_split, + \S_AXI_AID_Q_reg[0] , + \queue_id_reg[0]_0 , + split_in_progress_reg_0, + \num_transactions_q_reg[0] , + \num_transactions_q_reg[2] , + \num_transactions_q_reg[1] , + \pushed_commands_reg[3]_0 , + s_axi_arvalid, + S_AXI_AREADY_I_reg_0, + areset_d, + \areset_d_reg[1] , + split_in_progress_reg_1, + allow_split_cmd__1); + output [0:0]din; + output wr_en; + output rd_en; + output [4:0]D; + output split_ongoing_reg; + output m_axi_rready; + output s_axi_rvalid; + output s_axi_rlast; + output [0:0]E; + output cmd_push_block_reg; + output [0:0]\cmd_depth_reg[5] ; + output m_axi_arvalid; + output S_AXI_AREADY_I_reg; + output \queue_id_reg[0] ; + output command_ongoing_reg; + output multiple_id_non_split_reg; + output split_in_progress_reg; + input aclk; + input aresetn_0; + input [5:0]Q; + input cmd_push_block; + input command_ongoing; + input almost_empty; + input cmd_empty; + input aresetn; + input need_to_split_q; + input access_is_incr_q; + input \num_transactions_q_reg[3] ; + input [3:0]\pushed_commands_reg[3] ; + input m_axi_rvalid; + input s_axi_rready; + input m_axi_rlast; + input m_axi_arready; + input multiple_id_non_split; + input \S_AXI_AID_Q_reg[0] ; + input \queue_id_reg[0]_0 ; + input split_in_progress_reg_0; + input \num_transactions_q_reg[0] ; + input \num_transactions_q_reg[2] ; + input \num_transactions_q_reg[1] ; + input \pushed_commands_reg[3]_0 ; + input s_axi_arvalid; + input S_AXI_AREADY_I_reg_0; + input [1:0]areset_d; + input \areset_d_reg[1] ; + input split_in_progress_reg_1; + input allow_split_cmd__1; + + wire [4:0]D; + wire [0:0]E; + wire [5:0]Q; + wire \S_AXI_AID_Q_reg[0] ; + wire S_AXI_AREADY_I_reg; + wire S_AXI_AREADY_I_reg_0; + wire access_is_incr_q; + wire aclk; + wire allow_split_cmd__1; + wire almost_empty; + wire [1:0]areset_d; + wire \areset_d_reg[1] ; + wire aresetn; + wire aresetn_0; + wire \cmd_depth[4]_i_2__0_n_0 ; + wire \cmd_depth[5]_i_3__0_n_0 ; + wire [0:0]\cmd_depth_reg[5] ; + wire cmd_empty; + wire cmd_push_block; + wire cmd_push_block_reg; + wire command_ongoing; + wire command_ongoing_reg; + wire [0:0]din; + wire empty; + wire full; + wire m_axi_arready; + wire m_axi_arvalid; + wire m_axi_arvalid_INST_0_i_1_n_0; + wire m_axi_rlast; + wire m_axi_rready; + wire m_axi_rvalid; + wire multiple_id_non_split; + wire multiple_id_non_split_i_3__0_n_0; + wire multiple_id_non_split_reg; + wire need_to_split_q; + wire \num_transactions_q_reg[0] ; + wire \num_transactions_q_reg[1] ; + wire \num_transactions_q_reg[2] ; + wire \num_transactions_q_reg[3] ; + wire [3:0]\pushed_commands_reg[3] ; + wire \pushed_commands_reg[3]_0 ; + wire \queue_id_reg[0] ; + wire \queue_id_reg[0]_0 ; + wire rd_cmd_split; + wire rd_en; + wire s_axi_arvalid; + wire s_axi_rlast; + wire s_axi_rready; + wire s_axi_rvalid; + wire split_in_progress_reg; + wire split_in_progress_reg_0; + wire split_in_progress_reg_1; + wire split_ongoing_reg; + wire wr_en; + wire NLW_fifo_gen_inst_almost_empty_UNCONNECTED; + wire NLW_fifo_gen_inst_almost_full_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axis_overflow_UNCONNECTED; + wire NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED; + wire NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED; + wire NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_axis_underflow_UNCONNECTED; + wire NLW_fifo_gen_inst_dbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED; + wire NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED; + wire NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED; + wire NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED; + wire NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED; + wire NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED; + wire NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED; + wire NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED; + wire NLW_fifo_gen_inst_overflow_UNCONNECTED; + wire NLW_fifo_gen_inst_prog_empty_UNCONNECTED; + wire NLW_fifo_gen_inst_prog_full_UNCONNECTED; + wire NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED; + wire NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED; + wire NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED; + wire NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED; + wire NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED; + wire NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED; + wire NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED; + wire NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED; + wire NLW_fifo_gen_inst_sbiterr_UNCONNECTED; + wire NLW_fifo_gen_inst_underflow_UNCONNECTED; + wire NLW_fifo_gen_inst_valid_UNCONNECTED; + wire NLW_fifo_gen_inst_wr_ack_UNCONNECTED; + wire NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED; + wire [4:0]NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED; + wire [4:0]NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED; + wire [4:0]NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED; + wire [4:0]NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED; + wire [4:0]NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED; + wire [4:0]NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED; + wire [4:0]NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED; + wire [4:0]NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED; + wire [4:0]NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED; + wire [10:0]NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED; + wire [10:0]NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED; + wire [10:0]NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED; + wire [10:0]NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED; + wire [10:0]NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED; + wire [10:0]NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED; + wire [10:0]NLW_fifo_gen_inst_axis_data_count_UNCONNECTED; + wire [10:0]NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED; + wire [10:0]NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED; + wire [5:0]NLW_fifo_gen_inst_data_count_UNCONNECTED; + wire [31:0]NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED; + wire [1:0]NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED; + wire [7:0]NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED; + wire [1:0]NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED; + wire [2:0]NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED; + wire [2:0]NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED; + wire [0:0]NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED; + wire [31:0]NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED; + wire [1:0]NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED; + wire [7:0]NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED; + wire [1:0]NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED; + wire [2:0]NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED; + wire [2:0]NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED; + wire [0:0]NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED; + wire [63:0]NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED; + wire [7:0]NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED; + wire [0:0]NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED; + wire [63:0]NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED; + wire [7:0]NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED; + wire [5:0]NLW_fifo_gen_inst_rd_data_count_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED; + wire [1:0]NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED; + wire [0:0]NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED; + wire [63:0]NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED; + wire [3:0]NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED; + wire [1:0]NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED; + wire [0:0]NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED; + wire [5:0]NLW_fifo_gen_inst_wr_data_count_UNCONNECTED; + + LUT6 #( + .INIT(64'h0F88FFFF0F880F88)) + S_AXI_AREADY_I_i_1__0 + (.I0(E), + .I1(\pushed_commands_reg[3]_0 ), + .I2(s_axi_arvalid), + .I3(S_AXI_AREADY_I_reg_0), + .I4(areset_d[0]), + .I5(areset_d[1]), + .O(S_AXI_AREADY_I_reg)); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT3 #( + .INIT(8'h69)) + \cmd_depth[1]_i_1__0 + (.I0(Q[0]), + .I1(\cmd_depth[4]_i_2__0_n_0 ), + .I2(Q[1]), + .O(D[0])); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT4 #( + .INIT(16'h78E1)) + \cmd_depth[2]_i_1__0 + (.I0(Q[0]), + .I1(\cmd_depth[4]_i_2__0_n_0 ), + .I2(Q[2]), + .I3(Q[1]), + .O(D[1])); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT5 #( + .INIT(32'h7F80FE01)) + \cmd_depth[3]_i_1__0 + (.I0(\cmd_depth[4]_i_2__0_n_0 ), + .I1(Q[0]), + .I2(Q[1]), + .I3(Q[3]), + .I4(Q[2]), + .O(D[2])); + LUT6 #( + .INIT(64'h7FFF8000FFFE0001)) + \cmd_depth[4]_i_1__0 + (.I0(Q[1]), + .I1(Q[0]), + .I2(\cmd_depth[4]_i_2__0_n_0 ), + .I3(Q[2]), + .I4(Q[4]), + .I5(Q[3]), + .O(D[3])); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT5 #( + .INIT(32'h00000040)) + \cmd_depth[4]_i_2__0 + (.I0(cmd_push_block), + .I1(command_ongoing), + .I2(m_axi_arvalid_INST_0_i_1_n_0), + .I3(full), + .I4(rd_en), + .O(\cmd_depth[4]_i_2__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT5 #( + .INIT(32'hAAAA6AAA)) + \cmd_depth[5]_i_1__0 + (.I0(wr_en), + .I1(s_axi_rready), + .I2(m_axi_rvalid), + .I3(m_axi_rlast), + .I4(empty), + .O(\cmd_depth_reg[5] )); + LUT4 #( + .INIT(16'h78E1)) + \cmd_depth[5]_i_2__0 + (.I0(\cmd_depth[5]_i_3__0_n_0 ), + .I1(Q[3]), + .I2(Q[5]), + .I3(Q[4]), + .O(D[4])); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT5 #( + .INIT(32'hD5555554)) + \cmd_depth[5]_i_3__0 + (.I0(Q[3]), + .I1(Q[2]), + .I2(\cmd_depth[4]_i_2__0_n_0 ), + .I3(Q[0]), + .I4(Q[1]), + .O(\cmd_depth[5]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'h55000000FF080000)) + cmd_push_block_i_1__0 + (.I0(command_ongoing), + .I1(m_axi_arvalid_INST_0_i_1_n_0), + .I2(full), + .I3(cmd_push_block), + .I4(aresetn), + .I5(m_axi_arready), + .O(cmd_push_block_reg)); + LUT6 #( + .INIT(64'hFFFFF7770000F000)) + command_ongoing_i_1__0 + (.I0(E), + .I1(\pushed_commands_reg[3]_0 ), + .I2(s_axi_arvalid), + .I3(S_AXI_AREADY_I_reg_0), + .I4(\areset_d_reg[1] ), + .I5(command_ongoing), + .O(command_ongoing_reg)); + (* C_ADD_NGC_CONSTRAINT = "0" *) + (* C_APPLICATION_TYPE_AXIS = "0" *) + (* C_APPLICATION_TYPE_RACH = "0" *) + (* C_APPLICATION_TYPE_RDCH = "0" *) + (* C_APPLICATION_TYPE_WACH = "0" *) + (* C_APPLICATION_TYPE_WDCH = "0" *) + (* C_APPLICATION_TYPE_WRCH = "0" *) + (* C_AXIS_TDATA_WIDTH = "64" *) + (* C_AXIS_TDEST_WIDTH = "4" *) + (* C_AXIS_TID_WIDTH = "8" *) + (* C_AXIS_TKEEP_WIDTH = "4" *) + (* C_AXIS_TSTRB_WIDTH = "4" *) + (* C_AXIS_TUSER_WIDTH = "4" *) + (* C_AXIS_TYPE = "0" *) + (* C_AXI_ADDR_WIDTH = "32" *) + (* C_AXI_ARUSER_WIDTH = "1" *) + (* C_AXI_AWUSER_WIDTH = "1" *) + (* C_AXI_BUSER_WIDTH = "1" *) + (* C_AXI_DATA_WIDTH = "64" *) + (* C_AXI_ID_WIDTH = "4" *) + (* C_AXI_LEN_WIDTH = "8" *) + (* C_AXI_LOCK_WIDTH = "2" *) + (* C_AXI_RUSER_WIDTH = "1" *) + (* C_AXI_TYPE = "0" *) + (* C_AXI_WUSER_WIDTH = "1" *) + (* C_COMMON_CLOCK = "1" *) + (* C_COUNT_TYPE = "0" *) + (* C_DATA_COUNT_WIDTH = "6" *) + (* C_DEFAULT_VALUE = "BlankString" *) + (* C_DIN_WIDTH = "1" *) + (* C_DIN_WIDTH_AXIS = "1" *) + (* C_DIN_WIDTH_RACH = "32" *) + (* C_DIN_WIDTH_RDCH = "64" *) + (* C_DIN_WIDTH_WACH = "32" *) + (* C_DIN_WIDTH_WDCH = "64" *) + (* C_DIN_WIDTH_WRCH = "2" *) + (* C_DOUT_RST_VAL = "0" *) + (* C_DOUT_WIDTH = "1" *) + (* C_ENABLE_RLOCS = "0" *) + (* C_ENABLE_RST_SYNC = "1" *) + (* C_EN_SAFETY_CKT = "0" *) + (* C_ERROR_INJECTION_TYPE = "0" *) + (* C_ERROR_INJECTION_TYPE_AXIS = "0" *) + (* C_ERROR_INJECTION_TYPE_RACH = "0" *) + (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) + (* C_ERROR_INJECTION_TYPE_WACH = "0" *) + (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) + (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) + (* C_FAMILY = "zynq" *) + (* C_FULL_FLAGS_RST_VAL = "0" *) + (* C_HAS_ALMOST_EMPTY = "0" *) + (* C_HAS_ALMOST_FULL = "0" *) + (* C_HAS_AXIS_TDATA = "0" *) + (* C_HAS_AXIS_TDEST = "0" *) + (* C_HAS_AXIS_TID = "0" *) + (* C_HAS_AXIS_TKEEP = "0" *) + (* C_HAS_AXIS_TLAST = "0" *) + (* C_HAS_AXIS_TREADY = "1" *) + (* C_HAS_AXIS_TSTRB = "0" *) + (* C_HAS_AXIS_TUSER = "0" *) + (* C_HAS_AXI_ARUSER = "0" *) + (* C_HAS_AXI_AWUSER = "0" *) + (* C_HAS_AXI_BUSER = "0" *) + (* C_HAS_AXI_ID = "0" *) + (* C_HAS_AXI_RD_CHANNEL = "0" *) + (* C_HAS_AXI_RUSER = "0" *) + (* C_HAS_AXI_WR_CHANNEL = "0" *) + (* C_HAS_AXI_WUSER = "0" *) + (* C_HAS_BACKUP = "0" *) + (* C_HAS_DATA_COUNT = "0" *) + (* C_HAS_DATA_COUNTS_AXIS = "0" *) + (* C_HAS_DATA_COUNTS_RACH = "0" *) + (* C_HAS_DATA_COUNTS_RDCH = "0" *) + (* C_HAS_DATA_COUNTS_WACH = "0" *) + (* C_HAS_DATA_COUNTS_WDCH = "0" *) + (* C_HAS_DATA_COUNTS_WRCH = "0" *) + (* C_HAS_INT_CLK = "0" *) + (* C_HAS_MASTER_CE = "0" *) + (* C_HAS_MEMINIT_FILE = "0" *) + (* C_HAS_OVERFLOW = "0" *) + (* C_HAS_PROG_FLAGS_AXIS = "0" *) + (* C_HAS_PROG_FLAGS_RACH = "0" *) + (* C_HAS_PROG_FLAGS_RDCH = "0" *) + (* C_HAS_PROG_FLAGS_WACH = "0" *) + (* C_HAS_PROG_FLAGS_WDCH = "0" *) + (* C_HAS_PROG_FLAGS_WRCH = "0" *) + (* C_HAS_RD_DATA_COUNT = "0" *) + (* C_HAS_RD_RST = "0" *) + (* C_HAS_RST = "1" *) + (* C_HAS_SLAVE_CE = "0" *) + (* C_HAS_SRST = "0" *) + (* C_HAS_UNDERFLOW = "0" *) + (* C_HAS_VALID = "0" *) + (* C_HAS_WR_ACK = "0" *) + (* C_HAS_WR_DATA_COUNT = "0" *) + (* C_HAS_WR_RST = "0" *) + (* C_IMPLEMENTATION_TYPE = "0" *) + (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) + (* C_IMPLEMENTATION_TYPE_RACH = "1" *) + (* C_IMPLEMENTATION_TYPE_RDCH = "1" *) + (* C_IMPLEMENTATION_TYPE_WACH = "1" *) + (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) + (* C_IMPLEMENTATION_TYPE_WRCH = "1" *) + (* C_INIT_WR_PNTR_VAL = "0" *) + (* C_INTERFACE_TYPE = "0" *) + (* C_MEMORY_TYPE = "2" *) + (* C_MIF_FILE_NAME = "BlankString" *) + (* C_MSGON_VAL = "1" *) + (* C_OPTIMIZATION_MODE = "0" *) + (* C_OVERFLOW_LOW = "0" *) + (* C_POWER_SAVING_MODE = "0" *) + (* C_PRELOAD_LATENCY = "0" *) + (* C_PRELOAD_REGS = "1" *) + (* C_PRIM_FIFO_TYPE = "512x36" *) + (* C_PRIM_FIFO_TYPE_AXIS = "512x36" *) + (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) + (* C_PRIM_FIFO_TYPE_RDCH = "512x36" *) + (* C_PRIM_FIFO_TYPE_WACH = "512x36" *) + (* C_PRIM_FIFO_TYPE_WDCH = "512x36" *) + (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL = "4" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) + (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "5" *) + (* C_PROG_EMPTY_TYPE = "0" *) + (* C_PROG_EMPTY_TYPE_AXIS = "0" *) + (* C_PROG_EMPTY_TYPE_RACH = "0" *) + (* C_PROG_EMPTY_TYPE_RDCH = "0" *) + (* C_PROG_EMPTY_TYPE_WACH = "0" *) + (* C_PROG_EMPTY_TYPE_WDCH = "0" *) + (* C_PROG_EMPTY_TYPE_WRCH = "0" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL = "31" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) + (* C_PROG_FULL_THRESH_NEGATE_VAL = "30" *) + (* C_PROG_FULL_TYPE = "0" *) + (* C_PROG_FULL_TYPE_AXIS = "0" *) + (* C_PROG_FULL_TYPE_RACH = "0" *) + (* C_PROG_FULL_TYPE_RDCH = "0" *) + (* C_PROG_FULL_TYPE_WACH = "0" *) + (* C_PROG_FULL_TYPE_WDCH = "0" *) + (* C_PROG_FULL_TYPE_WRCH = "0" *) + (* C_RACH_TYPE = "0" *) + (* C_RDCH_TYPE = "0" *) + (* C_RD_DATA_COUNT_WIDTH = "6" *) + (* C_RD_DEPTH = "32" *) + (* C_RD_FREQ = "1" *) + (* C_RD_PNTR_WIDTH = "5" *) + (* C_REG_SLICE_MODE_AXIS = "0" *) + (* C_REG_SLICE_MODE_RACH = "0" *) + (* C_REG_SLICE_MODE_RDCH = "0" *) + (* C_REG_SLICE_MODE_WACH = "0" *) + (* C_REG_SLICE_MODE_WDCH = "0" *) + (* C_REG_SLICE_MODE_WRCH = "0" *) + (* C_SELECT_XPM = "0" *) + (* C_SYNCHRONIZER_STAGE = "3" *) + (* C_UNDERFLOW_LOW = "0" *) + (* C_USE_COMMON_OVERFLOW = "0" *) + (* C_USE_COMMON_UNDERFLOW = "0" *) + (* C_USE_DEFAULT_SETTINGS = "0" *) + (* C_USE_DOUT_RST = "0" *) + (* C_USE_ECC = "0" *) + (* C_USE_ECC_AXIS = "0" *) + (* C_USE_ECC_RACH = "0" *) + (* C_USE_ECC_RDCH = "0" *) + (* C_USE_ECC_WACH = "0" *) + (* C_USE_ECC_WDCH = "0" *) + (* C_USE_ECC_WRCH = "0" *) + (* C_USE_EMBEDDED_REG = "0" *) + (* C_USE_FIFO16_FLAGS = "0" *) + (* C_USE_FWFT_DATA_COUNT = "1" *) + (* C_USE_PIPELINE_REG = "0" *) + (* C_VALID_LOW = "0" *) + (* C_WACH_TYPE = "0" *) + (* C_WDCH_TYPE = "0" *) + (* C_WRCH_TYPE = "0" *) + (* C_WR_ACK_LOW = "0" *) + (* C_WR_DATA_COUNT_WIDTH = "6" *) + (* C_WR_DEPTH = "32" *) + (* C_WR_DEPTH_AXIS = "1024" *) + (* C_WR_DEPTH_RACH = "16" *) + (* C_WR_DEPTH_RDCH = "1024" *) + (* C_WR_DEPTH_WACH = "16" *) + (* C_WR_DEPTH_WDCH = "1024" *) + (* C_WR_DEPTH_WRCH = "16" *) + (* C_WR_FREQ = "1" *) + (* C_WR_PNTR_WIDTH = "5" *) + (* C_WR_PNTR_WIDTH_AXIS = "10" *) + (* C_WR_PNTR_WIDTH_RACH = "4" *) + (* C_WR_PNTR_WIDTH_RDCH = "10" *) + (* C_WR_PNTR_WIDTH_WACH = "4" *) + (* C_WR_PNTR_WIDTH_WDCH = "10" *) + (* C_WR_PNTR_WIDTH_WRCH = "4" *) + (* C_WR_RESPONSE_LATENCY = "1" *) + Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0 fifo_gen_inst + (.almost_empty(NLW_fifo_gen_inst_almost_empty_UNCONNECTED), + .almost_full(NLW_fifo_gen_inst_almost_full_UNCONNECTED), + .axi_ar_data_count(NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED[4:0]), + .axi_ar_dbiterr(NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED), + .axi_ar_injectdbiterr(1'b0), + .axi_ar_injectsbiterr(1'b0), + .axi_ar_overflow(NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED), + .axi_ar_prog_empty(NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED), + .axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), + .axi_ar_prog_full(NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED), + .axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), + .axi_ar_rd_data_count(NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED[4:0]), + .axi_ar_sbiterr(NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED), + .axi_ar_underflow(NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED), + .axi_ar_wr_data_count(NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED[4:0]), + .axi_aw_data_count(NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED[4:0]), + .axi_aw_dbiterr(NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED), + .axi_aw_injectdbiterr(1'b0), + .axi_aw_injectsbiterr(1'b0), + .axi_aw_overflow(NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED), + .axi_aw_prog_empty(NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED), + .axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), + .axi_aw_prog_full(NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED), + .axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), + .axi_aw_rd_data_count(NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED[4:0]), + .axi_aw_sbiterr(NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED), + .axi_aw_underflow(NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED), + .axi_aw_wr_data_count(NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED[4:0]), + .axi_b_data_count(NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED[4:0]), + .axi_b_dbiterr(NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED), + .axi_b_injectdbiterr(1'b0), + .axi_b_injectsbiterr(1'b0), + .axi_b_overflow(NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED), + .axi_b_prog_empty(NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED), + .axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), + .axi_b_prog_full(NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED), + .axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), + .axi_b_rd_data_count(NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED[4:0]), + .axi_b_sbiterr(NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED), + .axi_b_underflow(NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED), + .axi_b_wr_data_count(NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED[4:0]), + .axi_r_data_count(NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED[10:0]), + .axi_r_dbiterr(NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED), + .axi_r_injectdbiterr(1'b0), + .axi_r_injectsbiterr(1'b0), + .axi_r_overflow(NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED), + .axi_r_prog_empty(NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED), + .axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .axi_r_prog_full(NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED), + .axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .axi_r_rd_data_count(NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED[10:0]), + .axi_r_sbiterr(NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED), + .axi_r_underflow(NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED), + .axi_r_wr_data_count(NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED[10:0]), + .axi_w_data_count(NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED[10:0]), + .axi_w_dbiterr(NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED), + .axi_w_injectdbiterr(1'b0), + .axi_w_injectsbiterr(1'b0), + .axi_w_overflow(NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED), + .axi_w_prog_empty(NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED), + .axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .axi_w_prog_full(NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED), + .axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .axi_w_rd_data_count(NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED[10:0]), + .axi_w_sbiterr(NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED), + .axi_w_underflow(NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED), + .axi_w_wr_data_count(NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED[10:0]), + .axis_data_count(NLW_fifo_gen_inst_axis_data_count_UNCONNECTED[10:0]), + .axis_dbiterr(NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED), + .axis_injectdbiterr(1'b0), + .axis_injectsbiterr(1'b0), + .axis_overflow(NLW_fifo_gen_inst_axis_overflow_UNCONNECTED), + .axis_prog_empty(NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED), + .axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .axis_prog_full(NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED), + .axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .axis_rd_data_count(NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED[10:0]), + .axis_sbiterr(NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED), + .axis_underflow(NLW_fifo_gen_inst_axis_underflow_UNCONNECTED), + .axis_wr_data_count(NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED[10:0]), + .backup(1'b0), + .backup_marker(1'b0), + .clk(aclk), + .data_count(NLW_fifo_gen_inst_data_count_UNCONNECTED[5:0]), + .dbiterr(NLW_fifo_gen_inst_dbiterr_UNCONNECTED), + .din(din), + .dout(rd_cmd_split), + .empty(empty), + .full(full), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + .int_clk(1'b0), + .m_aclk(1'b0), + .m_aclk_en(1'b0), + .m_axi_araddr(NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED[31:0]), + .m_axi_arburst(NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED[1:0]), + .m_axi_arcache(NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED[3:0]), + .m_axi_arid(NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED[3:0]), + .m_axi_arlen(NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED[7:0]), + .m_axi_arlock(NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED[1:0]), + .m_axi_arprot(NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED[2:0]), + .m_axi_arqos(NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED[3:0]), + .m_axi_arready(1'b0), + .m_axi_arregion(NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED[3:0]), + .m_axi_arsize(NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED[2:0]), + .m_axi_aruser(NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED[0]), + .m_axi_arvalid(NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED), + .m_axi_awaddr(NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED[31:0]), + .m_axi_awburst(NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED[1:0]), + .m_axi_awcache(NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED[3:0]), + .m_axi_awid(NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED[3:0]), + .m_axi_awlen(NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED[7:0]), + .m_axi_awlock(NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED[1:0]), + .m_axi_awprot(NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED[2:0]), + .m_axi_awqos(NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED[3:0]), + .m_axi_awready(1'b0), + .m_axi_awregion(NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED[3:0]), + .m_axi_awsize(NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED[2:0]), + .m_axi_awuser(NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED[0]), + .m_axi_awvalid(NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED), + .m_axi_bid({1'b0,1'b0,1'b0,1'b0}), + .m_axi_bready(NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED), + .m_axi_bresp({1'b0,1'b0}), + .m_axi_buser(1'b0), + .m_axi_bvalid(1'b0), + .m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .m_axi_rid({1'b0,1'b0,1'b0,1'b0}), + .m_axi_rlast(1'b0), + .m_axi_rready(NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED), + .m_axi_rresp({1'b0,1'b0}), + .m_axi_ruser(1'b0), + .m_axi_rvalid(1'b0), + .m_axi_wdata(NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED[63:0]), + .m_axi_wid(NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED[3:0]), + .m_axi_wlast(NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED), + .m_axi_wready(1'b0), + .m_axi_wstrb(NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED[7:0]), + .m_axi_wuser(NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED[0]), + .m_axi_wvalid(NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED), + .m_axis_tdata(NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED[63:0]), + .m_axis_tdest(NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED[3:0]), + .m_axis_tid(NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED[7:0]), + .m_axis_tkeep(NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED[3:0]), + .m_axis_tlast(NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED), + .m_axis_tready(1'b0), + .m_axis_tstrb(NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED[3:0]), + .m_axis_tuser(NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED[3:0]), + .m_axis_tvalid(NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED), + .overflow(NLW_fifo_gen_inst_overflow_UNCONNECTED), + .prog_empty(NLW_fifo_gen_inst_prog_empty_UNCONNECTED), + .prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_full(NLW_fifo_gen_inst_prog_full_UNCONNECTED), + .prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0}), + .rd_clk(1'b0), + .rd_data_count(NLW_fifo_gen_inst_rd_data_count_UNCONNECTED[5:0]), + .rd_en(rd_en), + .rd_rst(1'b0), + .rd_rst_busy(NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED), + .rst(aresetn_0), + .s_aclk(1'b0), + .s_aclk_en(1'b0), + .s_aresetn(1'b0), + .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_arburst({1'b0,1'b0}), + .s_axi_arcache({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arid({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_arlock({1'b0,1'b0}), + .s_axi_arprot({1'b0,1'b0,1'b0}), + .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arready(NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED), + .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arsize({1'b0,1'b0,1'b0}), + .s_axi_aruser(1'b0), + .s_axi_arvalid(1'b0), + .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_awburst({1'b0,1'b0}), + .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awid({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_awlock({1'b0,1'b0}), + .s_axi_awprot({1'b0,1'b0,1'b0}), + .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awready(NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED), + .s_axi_awregion({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awsize({1'b0,1'b0,1'b0}), + .s_axi_awuser(1'b0), + .s_axi_awvalid(1'b0), + .s_axi_bid(NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED[3:0]), + .s_axi_bready(1'b0), + .s_axi_bresp(NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED[1:0]), + .s_axi_buser(NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED[0]), + .s_axi_bvalid(NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED), + .s_axi_rdata(NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED[63:0]), + .s_axi_rid(NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED[3:0]), + .s_axi_rlast(NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED), + .s_axi_rready(1'b0), + .s_axi_rresp(NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED[1:0]), + .s_axi_ruser(NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED[0]), + .s_axi_rvalid(NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED), + .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_wid({1'b0,1'b0,1'b0,1'b0}), + .s_axi_wlast(1'b0), + .s_axi_wready(NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED), + .s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_wuser(1'b0), + .s_axi_wvalid(1'b0), + .s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axis_tdest({1'b0,1'b0,1'b0,1'b0}), + .s_axis_tid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axis_tkeep({1'b0,1'b0,1'b0,1'b0}), + .s_axis_tlast(1'b0), + .s_axis_tready(NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED), + .s_axis_tstrb({1'b0,1'b0,1'b0,1'b0}), + .s_axis_tuser({1'b0,1'b0,1'b0,1'b0}), + .s_axis_tvalid(1'b0), + .sbiterr(NLW_fifo_gen_inst_sbiterr_UNCONNECTED), + .sleep(1'b0), + .srst(1'b0), + .underflow(NLW_fifo_gen_inst_underflow_UNCONNECTED), + .valid(NLW_fifo_gen_inst_valid_UNCONNECTED), + .wr_ack(NLW_fifo_gen_inst_wr_ack_UNCONNECTED), + .wr_clk(1'b0), + .wr_data_count(NLW_fifo_gen_inst_wr_data_count_UNCONNECTED[5:0]), + .wr_en(wr_en), + .wr_rst(1'b0), + .wr_rst_busy(NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED)); + LUT5 #( + .INIT(32'h08808888)) + fifo_gen_inst_i_1__1 + (.I0(need_to_split_q), + .I1(access_is_incr_q), + .I2(\num_transactions_q_reg[3] ), + .I3(\pushed_commands_reg[3] [3]), + .I4(split_ongoing_reg), + .O(din)); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h0040)) + fifo_gen_inst_i_2__0 + (.I0(full), + .I1(m_axi_arvalid_INST_0_i_1_n_0), + .I2(command_ongoing), + .I3(cmd_push_block), + .O(wr_en)); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT4 #( + .INIT(16'h0080)) + fifo_gen_inst_i_3__0 + (.I0(s_axi_rready), + .I1(m_axi_rvalid), + .I2(m_axi_rlast), + .I3(empty), + .O(rd_en)); + LUT6 #( + .INIT(64'h9009000000009009)) + fifo_gen_inst_i_4__0 + (.I0(\num_transactions_q_reg[0] ), + .I1(\pushed_commands_reg[3] [0]), + .I2(\pushed_commands_reg[3] [2]), + .I3(\num_transactions_q_reg[2] ), + .I4(\pushed_commands_reg[3] [1]), + .I5(\num_transactions_q_reg[1] ), + .O(split_ongoing_reg)); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT4 #( + .INIT(16'hAA08)) + m_axi_arvalid_INST_0 + (.I0(command_ongoing), + .I1(m_axi_arvalid_INST_0_i_1_n_0), + .I2(full), + .I3(cmd_push_block), + .O(m_axi_arvalid)); + LUT6 #( + .INIT(64'h7770707777737377)) + m_axi_arvalid_INST_0_i_1 + (.I0(multiple_id_non_split), + .I1(need_to_split_q), + .I2(cmd_empty), + .I3(\S_AXI_AID_Q_reg[0] ), + .I4(\queue_id_reg[0]_0 ), + .I5(split_in_progress_reg_0), + .O(m_axi_arvalid_INST_0_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT3 #( + .INIT(8'h0D)) + m_axi_rready_INST_0 + (.I0(m_axi_rvalid), + .I1(s_axi_rready), + .I2(empty), + .O(m_axi_rready)); + LUT6 #( + .INIT(64'h00000000BEAAAAAA)) + multiple_id_non_split_i_1__0 + (.I0(multiple_id_non_split), + .I1(\queue_id_reg[0]_0 ), + .I2(\S_AXI_AID_Q_reg[0] ), + .I3(wr_en), + .I4(split_in_progress_reg_1), + .I5(multiple_id_non_split_i_3__0_n_0), + .O(multiple_id_non_split_reg)); + LUT4 #( + .INIT(16'hF8FF)) + multiple_id_non_split_i_3__0 + (.I0(almost_empty), + .I1(rd_en), + .I2(cmd_empty), + .I3(aresetn), + .O(multiple_id_non_split_i_3__0_n_0)); + LUT3 #( + .INIT(8'hB8)) + \queue_id[0]_i_1__0 + (.I0(\S_AXI_AID_Q_reg[0] ), + .I1(wr_en), + .I2(\queue_id_reg[0]_0 ), + .O(\queue_id_reg[0] )); + LUT2 #( + .INIT(4'h2)) + s_axi_rlast_INST_0 + (.I0(m_axi_rlast), + .I1(rd_cmd_split), + .O(s_axi_rlast)); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT2 #( + .INIT(4'h2)) + s_axi_rvalid_INST_0 + (.I0(m_axi_rvalid), + .I1(empty), + .O(s_axi_rvalid)); + LUT4 #( + .INIT(16'h00EA)) + split_in_progress_i_1__0 + (.I0(split_in_progress_reg_0), + .I1(wr_en), + .I2(allow_split_cmd__1), + .I3(multiple_id_non_split_i_3__0_n_0), + .O(split_in_progress_reg)); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT5 #( + .INIT(32'hAA080000)) + split_ongoing_i_1__0 + (.I0(command_ongoing), + .I1(m_axi_arvalid_INST_0_i_1_n_0), + .I2(full), + .I3(cmd_push_block), + .I4(m_axi_arready), + .O(E)); +endmodule + +module Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_a_axi3_conv + (dout, + empty, + \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg , + din, + \S_AXI_BRESP_ACC_reg[0] , + E, + areset_d, + m_axi_awvalid, + m_axi_wvalid, + m_axi_awlock, + command_ongoing_reg_0, + m_axi_awaddr, + s_axi_wready, + m_axi_awsize, + m_axi_awburst, + m_axi_awcache, + m_axi_awprot, + m_axi_awqos, + aclk, + wr_cmd_ready, + s_axi_awid, + s_axi_awlock, + s_axi_awlen, + m_axi_bvalid, + last_word, + s_axi_bready, + aresetn, + s_axi_awsize, + s_axi_wvalid, + m_axi_awready, + m_axi_wready, + s_axi_awvalid, + s_axi_awaddr, + s_axi_awburst, + s_axi_awcache, + s_axi_awprot, + s_axi_awqos); + output [4:0]dout; + output empty; + output \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg ; + output [4:0]din; + output [4:0]\S_AXI_BRESP_ACC_reg[0] ; + output [0:0]E; + output [1:0]areset_d; + output m_axi_awvalid; + output m_axi_wvalid; + output [0:0]m_axi_awlock; + output command_ongoing_reg_0; + output [31:0]m_axi_awaddr; + output s_axi_wready; + output [2:0]m_axi_awsize; + output [1:0]m_axi_awburst; + output [3:0]m_axi_awcache; + output [2:0]m_axi_awprot; + output [3:0]m_axi_awqos; + input aclk; + input wr_cmd_ready; + input [0:0]s_axi_awid; + input [0:0]s_axi_awlock; + input [7:0]s_axi_awlen; + input m_axi_bvalid; + input last_word; + input s_axi_bready; + input aresetn; + input [2:0]s_axi_awsize; + input s_axi_wvalid; + input m_axi_awready; + input m_axi_wready; + input s_axi_awvalid; + input [31:0]s_axi_awaddr; + input [1:0]s_axi_awburst; + input [3:0]s_axi_awcache; + input [2:0]s_axi_awprot; + input [3:0]s_axi_awqos; + + wire [0:0]E; + wire M_AXI_AADDR_I1__0; + wire [31:0]S_AXI_AADDR_Q; + wire [3:0]S_AXI_ALEN_Q; + wire \S_AXI_ALOCK_Q_reg_n_0_[0] ; + wire S_AXI_AREADY_I_i_3_n_0; + wire [4:0]\S_AXI_BRESP_ACC_reg[0] ; + wire \USE_BURSTS.cmd_queue_n_12 ; + wire \USE_BURSTS.cmd_queue_n_13 ; + wire \USE_BURSTS.cmd_queue_n_14 ; + wire \USE_BURSTS.cmd_queue_n_15 ; + wire \USE_BURSTS.cmd_queue_n_16 ; + wire \USE_BURSTS.cmd_queue_n_17 ; + wire \USE_BURSTS.cmd_queue_n_19 ; + wire \USE_BURSTS.cmd_queue_n_21 ; + wire \USE_BURSTS.cmd_queue_n_22 ; + wire \USE_BURSTS.cmd_queue_n_23 ; + wire \USE_B_CHANNEL.cmd_b_depth[0]_i_1_n_0 ; + wire [5:0]\USE_B_CHANNEL.cmd_b_depth_reg__0 ; + wire \USE_B_CHANNEL.cmd_b_queue_n_10 ; + wire \USE_B_CHANNEL.cmd_b_queue_n_11 ; + wire \USE_B_CHANNEL.cmd_b_queue_n_13 ; + wire \USE_B_CHANNEL.cmd_b_queue_n_14 ; + wire \USE_B_CHANNEL.cmd_b_queue_n_15 ; + wire \USE_B_CHANNEL.cmd_b_queue_n_16 ; + wire \USE_B_CHANNEL.cmd_b_queue_n_17 ; + wire \USE_B_CHANNEL.cmd_b_queue_n_18 ; + wire \USE_B_CHANNEL.cmd_b_queue_n_21 ; + wire \USE_B_CHANNEL.cmd_b_queue_n_22 ; + wire \USE_B_CHANNEL.cmd_b_queue_n_23 ; + wire \USE_B_CHANNEL.cmd_b_queue_n_6 ; + wire \USE_B_CHANNEL.cmd_b_queue_n_7 ; + wire \USE_B_CHANNEL.cmd_b_queue_n_8 ; + wire \USE_B_CHANNEL.cmd_b_queue_n_9 ; + wire access_is_incr; + wire access_is_incr_q; + wire aclk; + wire [11:5]addr_step; + wire [11:5]addr_step_q; + wire allow_split_cmd__1; + wire almost_b_empty; + wire almost_empty; + wire [1:0]areset_d; + wire aresetn; + wire cmd_b_empty; + wire cmd_b_push_block; + wire \cmd_depth[0]_i_1_n_0 ; + wire [5:0]cmd_depth_reg__0; + wire cmd_empty; + wire cmd_empty_i_1_n_0; + wire cmd_push_block; + wire command_ongoing; + wire command_ongoing_reg_0; + wire [4:0]din; + wire [4:0]dout; + wire empty; + wire first_split__2; + wire [11:4]first_step; + wire [11:0]first_step_q; + wire \first_step_q[0]_i_1_n_0 ; + wire \first_step_q[10]_i_2_n_0 ; + wire \first_step_q[11]_i_2_n_0 ; + wire \first_step_q[1]_i_1_n_0 ; + wire \first_step_q[2]_i_1_n_0 ; + wire \first_step_q[3]_i_1_n_0 ; + wire \first_step_q[6]_i_2_n_0 ; + wire \first_step_q[7]_i_2_n_0 ; + wire \first_step_q[8]_i_2_n_0 ; + wire \first_step_q[9]_i_2_n_0 ; + wire incr_need_to_split__0; + wire \inst/full ; + wire \inst/full_0 ; + wire last_word; + wire [31:0]m_axi_awaddr; + wire [1:0]m_axi_awburst; + wire [3:0]m_axi_awcache; + wire [0:0]m_axi_awlock; + wire [2:0]m_axi_awprot; + wire [3:0]m_axi_awqos; + wire m_axi_awready; + wire [2:0]m_axi_awsize; + wire m_axi_awvalid; + wire m_axi_bvalid; + wire m_axi_wready; + wire m_axi_wvalid; + wire multiple_id_non_split; + wire need_to_split_q; + wire [31:0]next_mi_addr; + wire \next_mi_addr[11]_i_2_n_0 ; + wire \next_mi_addr[11]_i_3_n_0 ; + wire \next_mi_addr[11]_i_4_n_0 ; + wire \next_mi_addr[11]_i_5_n_0 ; + wire \next_mi_addr[15]_i_2_n_0 ; + wire \next_mi_addr[15]_i_3_n_0 ; + wire \next_mi_addr[15]_i_4_n_0 ; + wire \next_mi_addr[15]_i_5_n_0 ; + wire \next_mi_addr[15]_i_6_n_0 ; + wire \next_mi_addr[15]_i_7_n_0 ; + wire \next_mi_addr[15]_i_8_n_0 ; + wire \next_mi_addr[15]_i_9_n_0 ; + wire \next_mi_addr[19]_i_2_n_0 ; + wire \next_mi_addr[19]_i_3_n_0 ; + wire \next_mi_addr[19]_i_4_n_0 ; + wire \next_mi_addr[19]_i_5_n_0 ; + wire \next_mi_addr[23]_i_2_n_0 ; + wire \next_mi_addr[23]_i_3_n_0 ; + wire \next_mi_addr[23]_i_4_n_0 ; + wire \next_mi_addr[23]_i_5_n_0 ; + wire \next_mi_addr[27]_i_2_n_0 ; + wire \next_mi_addr[27]_i_3_n_0 ; + wire \next_mi_addr[27]_i_4_n_0 ; + wire \next_mi_addr[27]_i_5_n_0 ; + wire \next_mi_addr[31]_i_2_n_0 ; + wire \next_mi_addr[31]_i_3_n_0 ; + wire \next_mi_addr[31]_i_4_n_0 ; + wire \next_mi_addr[31]_i_5_n_0 ; + wire \next_mi_addr[3]_i_2_n_0 ; + wire \next_mi_addr[3]_i_3_n_0 ; + wire \next_mi_addr[3]_i_4_n_0 ; + wire \next_mi_addr[3]_i_5_n_0 ; + wire \next_mi_addr[7]_i_2_n_0 ; + wire \next_mi_addr[7]_i_3_n_0 ; + wire \next_mi_addr[7]_i_4_n_0 ; + wire \next_mi_addr[7]_i_5_n_0 ; + wire \next_mi_addr_reg[11]_i_1_n_0 ; + wire \next_mi_addr_reg[11]_i_1_n_1 ; + wire \next_mi_addr_reg[11]_i_1_n_2 ; + wire \next_mi_addr_reg[11]_i_1_n_3 ; + wire \next_mi_addr_reg[11]_i_1_n_4 ; + wire \next_mi_addr_reg[11]_i_1_n_5 ; + wire \next_mi_addr_reg[11]_i_1_n_6 ; + wire \next_mi_addr_reg[11]_i_1_n_7 ; + wire \next_mi_addr_reg[15]_i_1_n_0 ; + wire \next_mi_addr_reg[15]_i_1_n_1 ; + wire \next_mi_addr_reg[15]_i_1_n_2 ; + wire \next_mi_addr_reg[15]_i_1_n_3 ; + wire \next_mi_addr_reg[15]_i_1_n_4 ; + wire \next_mi_addr_reg[15]_i_1_n_5 ; + wire \next_mi_addr_reg[15]_i_1_n_6 ; + wire \next_mi_addr_reg[15]_i_1_n_7 ; + wire \next_mi_addr_reg[19]_i_1_n_0 ; + wire \next_mi_addr_reg[19]_i_1_n_1 ; + wire \next_mi_addr_reg[19]_i_1_n_2 ; + wire \next_mi_addr_reg[19]_i_1_n_3 ; + wire \next_mi_addr_reg[19]_i_1_n_4 ; + wire \next_mi_addr_reg[19]_i_1_n_5 ; + wire \next_mi_addr_reg[19]_i_1_n_6 ; + wire \next_mi_addr_reg[19]_i_1_n_7 ; + wire \next_mi_addr_reg[23]_i_1_n_0 ; + wire \next_mi_addr_reg[23]_i_1_n_1 ; + wire \next_mi_addr_reg[23]_i_1_n_2 ; + wire \next_mi_addr_reg[23]_i_1_n_3 ; + wire \next_mi_addr_reg[23]_i_1_n_4 ; + wire \next_mi_addr_reg[23]_i_1_n_5 ; + wire \next_mi_addr_reg[23]_i_1_n_6 ; + wire \next_mi_addr_reg[23]_i_1_n_7 ; + wire \next_mi_addr_reg[27]_i_1_n_0 ; + wire \next_mi_addr_reg[27]_i_1_n_1 ; + wire \next_mi_addr_reg[27]_i_1_n_2 ; + wire \next_mi_addr_reg[27]_i_1_n_3 ; + wire \next_mi_addr_reg[27]_i_1_n_4 ; + wire \next_mi_addr_reg[27]_i_1_n_5 ; + wire \next_mi_addr_reg[27]_i_1_n_6 ; + wire \next_mi_addr_reg[27]_i_1_n_7 ; + wire \next_mi_addr_reg[31]_i_1_n_1 ; + wire \next_mi_addr_reg[31]_i_1_n_2 ; + wire \next_mi_addr_reg[31]_i_1_n_3 ; + wire \next_mi_addr_reg[31]_i_1_n_4 ; + wire \next_mi_addr_reg[31]_i_1_n_5 ; + wire \next_mi_addr_reg[31]_i_1_n_6 ; + wire \next_mi_addr_reg[31]_i_1_n_7 ; + wire \next_mi_addr_reg[3]_i_1_n_0 ; + wire \next_mi_addr_reg[3]_i_1_n_1 ; + wire \next_mi_addr_reg[3]_i_1_n_2 ; + wire \next_mi_addr_reg[3]_i_1_n_3 ; + wire \next_mi_addr_reg[3]_i_1_n_4 ; + wire \next_mi_addr_reg[3]_i_1_n_5 ; + wire \next_mi_addr_reg[3]_i_1_n_6 ; + wire \next_mi_addr_reg[3]_i_1_n_7 ; + wire \next_mi_addr_reg[7]_i_1_n_0 ; + wire \next_mi_addr_reg[7]_i_1_n_1 ; + wire \next_mi_addr_reg[7]_i_1_n_2 ; + wire \next_mi_addr_reg[7]_i_1_n_3 ; + wire \next_mi_addr_reg[7]_i_1_n_4 ; + wire \next_mi_addr_reg[7]_i_1_n_5 ; + wire \next_mi_addr_reg[7]_i_1_n_6 ; + wire \next_mi_addr_reg[7]_i_1_n_7 ; + wire \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg ; + wire [3:0]num_transactions_q; + wire [3:0]p_0_in; + wire \pushed_commands[3]_i_1_n_0 ; + wire [3:0]pushed_commands_reg__0; + wire pushed_new_cmd; + wire queue_id; + wire [31:0]s_axi_awaddr; + wire [1:0]s_axi_awburst; + wire [3:0]s_axi_awcache; + wire [0:0]s_axi_awid; + wire [7:0]s_axi_awlen; + wire [0:0]s_axi_awlock; + wire [2:0]s_axi_awprot; + wire [3:0]s_axi_awqos; + wire [2:0]s_axi_awsize; + wire s_axi_awvalid; + wire s_axi_bready; + wire s_axi_wready; + wire s_axi_wvalid; + wire [6:0]size_mask; + wire [31:0]size_mask_q; + wire split_in_progress_reg_n_0; + wire split_ongoing; + wire wr_cmd_ready; + wire [3:3]\NLW_next_mi_addr_reg[31]_i_1_CO_UNCONNECTED ; + + FDRE \S_AXI_AADDR_Q_reg[0] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[0]), + .Q(S_AXI_AADDR_Q[0]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[10] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[10]), + .Q(S_AXI_AADDR_Q[10]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[11] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[11]), + .Q(S_AXI_AADDR_Q[11]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[12] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[12]), + .Q(S_AXI_AADDR_Q[12]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[13] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[13]), + .Q(S_AXI_AADDR_Q[13]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[14] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[14]), + .Q(S_AXI_AADDR_Q[14]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[15] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[15]), + .Q(S_AXI_AADDR_Q[15]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[16] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[16]), + .Q(S_AXI_AADDR_Q[16]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[17] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[17]), + .Q(S_AXI_AADDR_Q[17]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[18] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[18]), + .Q(S_AXI_AADDR_Q[18]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[19] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[19]), + .Q(S_AXI_AADDR_Q[19]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[1] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[1]), + .Q(S_AXI_AADDR_Q[1]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[20] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[20]), + .Q(S_AXI_AADDR_Q[20]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[21] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[21]), + .Q(S_AXI_AADDR_Q[21]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[22] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[22]), + .Q(S_AXI_AADDR_Q[22]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[23] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[23]), + .Q(S_AXI_AADDR_Q[23]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[24] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[24]), + .Q(S_AXI_AADDR_Q[24]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[25] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[25]), + .Q(S_AXI_AADDR_Q[25]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[26] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[26]), + .Q(S_AXI_AADDR_Q[26]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[27] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[27]), + .Q(S_AXI_AADDR_Q[27]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[28] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[28]), + .Q(S_AXI_AADDR_Q[28]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[29] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[29]), + .Q(S_AXI_AADDR_Q[29]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[2] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[2]), + .Q(S_AXI_AADDR_Q[2]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[30] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[30]), + .Q(S_AXI_AADDR_Q[30]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[31] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[31]), + .Q(S_AXI_AADDR_Q[31]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[3] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[3]), + .Q(S_AXI_AADDR_Q[3]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[4] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[4]), + .Q(S_AXI_AADDR_Q[4]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[5] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[5]), + .Q(S_AXI_AADDR_Q[5]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[6] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[6]), + .Q(S_AXI_AADDR_Q[6]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[7] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[7]), + .Q(S_AXI_AADDR_Q[7]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[8] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[8]), + .Q(S_AXI_AADDR_Q[8]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AADDR_Q_reg[9] + (.C(aclk), + .CE(E), + .D(s_axi_awaddr[9]), + .Q(S_AXI_AADDR_Q[9]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_ABURST_Q_reg[0] + (.C(aclk), + .CE(E), + .D(s_axi_awburst[0]), + .Q(m_axi_awburst[0]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_ABURST_Q_reg[1] + (.C(aclk), + .CE(E), + .D(s_axi_awburst[1]), + .Q(m_axi_awburst[1]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_ACACHE_Q_reg[0] + (.C(aclk), + .CE(E), + .D(s_axi_awcache[0]), + .Q(m_axi_awcache[0]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_ACACHE_Q_reg[1] + (.C(aclk), + .CE(E), + .D(s_axi_awcache[1]), + .Q(m_axi_awcache[1]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_ACACHE_Q_reg[2] + (.C(aclk), + .CE(E), + .D(s_axi_awcache[2]), + .Q(m_axi_awcache[2]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_ACACHE_Q_reg[3] + (.C(aclk), + .CE(E), + .D(s_axi_awcache[3]), + .Q(m_axi_awcache[3]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AID_Q_reg[0] + (.C(aclk), + .CE(E), + .D(s_axi_awid), + .Q(din[4]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_ALEN_Q_reg[0] + (.C(aclk), + .CE(E), + .D(s_axi_awlen[0]), + .Q(S_AXI_ALEN_Q[0]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_ALEN_Q_reg[1] + (.C(aclk), + .CE(E), + .D(s_axi_awlen[1]), + .Q(S_AXI_ALEN_Q[1]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_ALEN_Q_reg[2] + (.C(aclk), + .CE(E), + .D(s_axi_awlen[2]), + .Q(S_AXI_ALEN_Q[2]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_ALEN_Q_reg[3] + (.C(aclk), + .CE(E), + .D(s_axi_awlen[3]), + .Q(S_AXI_ALEN_Q[3]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_ALOCK_Q_reg[0] + (.C(aclk), + .CE(E), + .D(s_axi_awlock), + .Q(\S_AXI_ALOCK_Q_reg_n_0_[0] ), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_APROT_Q_reg[0] + (.C(aclk), + .CE(E), + .D(s_axi_awprot[0]), + .Q(m_axi_awprot[0]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_APROT_Q_reg[1] + (.C(aclk), + .CE(E), + .D(s_axi_awprot[1]), + .Q(m_axi_awprot[1]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_APROT_Q_reg[2] + (.C(aclk), + .CE(E), + .D(s_axi_awprot[2]), + .Q(m_axi_awprot[2]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AQOS_Q_reg[0] + (.C(aclk), + .CE(E), + .D(s_axi_awqos[0]), + .Q(m_axi_awqos[0]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AQOS_Q_reg[1] + (.C(aclk), + .CE(E), + .D(s_axi_awqos[1]), + .Q(m_axi_awqos[1]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AQOS_Q_reg[2] + (.C(aclk), + .CE(E), + .D(s_axi_awqos[2]), + .Q(m_axi_awqos[2]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_AQOS_Q_reg[3] + (.C(aclk), + .CE(E), + .D(s_axi_awqos[3]), + .Q(m_axi_awqos[3]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + LUT4 #( + .INIT(16'h82FF)) + S_AXI_AREADY_I_i_3 + (.I0(\USE_B_CHANNEL.cmd_b_queue_n_15 ), + .I1(pushed_commands_reg__0[3]), + .I2(num_transactions_q[3]), + .I3(access_is_incr_q), + .O(S_AXI_AREADY_I_i_3_n_0)); + FDRE S_AXI_AREADY_I_reg + (.C(aclk), + .CE(1'b1), + .D(\USE_B_CHANNEL.cmd_b_queue_n_21 ), + .Q(E), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_ASIZE_Q_reg[0] + (.C(aclk), + .CE(E), + .D(s_axi_awsize[0]), + .Q(m_axi_awsize[0]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_ASIZE_Q_reg[1] + (.C(aclk), + .CE(E), + .D(s_axi_awsize[1]), + .Q(m_axi_awsize[1]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \S_AXI_ASIZE_Q_reg[2] + (.C(aclk), + .CE(E), + .D(s_axi_awsize[2]), + .Q(m_axi_awsize[2]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_axic_fifo \USE_BURSTS.cmd_queue + (.D({\USE_BURSTS.cmd_queue_n_13 ,\USE_BURSTS.cmd_queue_n_14 ,\USE_BURSTS.cmd_queue_n_15 ,\USE_BURSTS.cmd_queue_n_16 ,\USE_BURSTS.cmd_queue_n_17 }), + .E(\USE_BURSTS.cmd_queue_n_19 ), + .Q(cmd_depth_reg__0), + .SR(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg ), + .\S_AXI_AID_Q_reg[0] (din[4]), + .\S_AXI_ALEN_Q_reg[3] (S_AXI_ALEN_Q), + .aclk(aclk), + .allow_split_cmd__1(allow_split_cmd__1), + .aresetn(aresetn), + .\cmd_depth_reg[5] (\USE_BURSTS.cmd_queue_n_12 ), + .cmd_empty_reg(\USE_B_CHANNEL.cmd_b_queue_n_13 ), + .cmd_push_block(cmd_push_block), + .command_ongoing(command_ongoing), + .din(din[3:0]), + .dout(dout), + .empty(empty), + .full(\inst/full ), + .m_axi_wready(m_axi_wready), + .m_axi_wvalid(m_axi_wvalid), + .multiple_id_non_split(multiple_id_non_split), + .multiple_id_non_split_reg(\USE_BURSTS.cmd_queue_n_23 ), + .need_to_split_q(need_to_split_q), + .\pushed_commands_reg[3] (pushed_commands_reg__0), + .queue_id(queue_id), + .\queue_id_reg[0] (\USE_BURSTS.cmd_queue_n_21 ), + .ram_full_i_reg(\inst/full_0 ), + .s_axi_wready(s_axi_wready), + .s_axi_wvalid(s_axi_wvalid), + .split_in_progress_reg(\USE_BURSTS.cmd_queue_n_22 ), + .split_in_progress_reg_0(\USE_B_CHANNEL.cmd_b_queue_n_14 ), + .split_in_progress_reg_1(split_in_progress_reg_n_0), + .wr_cmd_ready(wr_cmd_ready)); + LUT1 #( + .INIT(2'h1)) + \USE_B_CHANNEL.cmd_b_depth[0]_i_1 + (.I0(\USE_B_CHANNEL.cmd_b_depth_reg__0 [0]), + .O(\USE_B_CHANNEL.cmd_b_depth[0]_i_1_n_0 )); + FDRE \USE_B_CHANNEL.cmd_b_depth_reg[0] + (.C(aclk), + .CE(\USE_B_CHANNEL.cmd_b_queue_n_17 ), + .D(\USE_B_CHANNEL.cmd_b_depth[0]_i_1_n_0 ), + .Q(\USE_B_CHANNEL.cmd_b_depth_reg__0 [0]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \USE_B_CHANNEL.cmd_b_depth_reg[1] + (.C(aclk), + .CE(\USE_B_CHANNEL.cmd_b_queue_n_17 ), + .D(\USE_B_CHANNEL.cmd_b_queue_n_11 ), + .Q(\USE_B_CHANNEL.cmd_b_depth_reg__0 [1]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \USE_B_CHANNEL.cmd_b_depth_reg[2] + (.C(aclk), + .CE(\USE_B_CHANNEL.cmd_b_queue_n_17 ), + .D(\USE_B_CHANNEL.cmd_b_queue_n_10 ), + .Q(\USE_B_CHANNEL.cmd_b_depth_reg__0 [2]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \USE_B_CHANNEL.cmd_b_depth_reg[3] + (.C(aclk), + .CE(\USE_B_CHANNEL.cmd_b_queue_n_17 ), + .D(\USE_B_CHANNEL.cmd_b_queue_n_9 ), + .Q(\USE_B_CHANNEL.cmd_b_depth_reg__0 [3]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \USE_B_CHANNEL.cmd_b_depth_reg[4] + (.C(aclk), + .CE(\USE_B_CHANNEL.cmd_b_queue_n_17 ), + .D(\USE_B_CHANNEL.cmd_b_queue_n_8 ), + .Q(\USE_B_CHANNEL.cmd_b_depth_reg__0 [4]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \USE_B_CHANNEL.cmd_b_depth_reg[5] + (.C(aclk), + .CE(\USE_B_CHANNEL.cmd_b_queue_n_17 ), + .D(\USE_B_CHANNEL.cmd_b_queue_n_7 ), + .Q(\USE_B_CHANNEL.cmd_b_depth_reg__0 [5]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + LUT6 #( + .INIT(64'h0000000000000100)) + \USE_B_CHANNEL.cmd_b_empty_i_2 + (.I0(\USE_B_CHANNEL.cmd_b_depth_reg__0 [4]), + .I1(\USE_B_CHANNEL.cmd_b_depth_reg__0 [3]), + .I2(\USE_B_CHANNEL.cmd_b_depth_reg__0 [5]), + .I3(\USE_B_CHANNEL.cmd_b_depth_reg__0 [0]), + .I4(\USE_B_CHANNEL.cmd_b_depth_reg__0 [1]), + .I5(\USE_B_CHANNEL.cmd_b_depth_reg__0 [2]), + .O(almost_b_empty)); + FDSE \USE_B_CHANNEL.cmd_b_empty_reg + (.C(aclk), + .CE(1'b1), + .D(\USE_B_CHANNEL.cmd_b_queue_n_18 ), + .Q(cmd_b_empty), + .S(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_axic_fifo_0 \USE_B_CHANNEL.cmd_b_queue + (.D({\USE_B_CHANNEL.cmd_b_queue_n_7 ,\USE_B_CHANNEL.cmd_b_queue_n_8 ,\USE_B_CHANNEL.cmd_b_queue_n_9 ,\USE_B_CHANNEL.cmd_b_queue_n_10 ,\USE_B_CHANNEL.cmd_b_queue_n_11 }), + .E(\USE_B_CHANNEL.cmd_b_queue_n_17 ), + .Q(\USE_B_CHANNEL.cmd_b_depth_reg__0 ), + .SR(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg ), + .\S_AXI_AID_Q_reg[0] (din[4]), + .S_AXI_AREADY_I_reg(\USE_B_CHANNEL.cmd_b_queue_n_21 ), + .S_AXI_AREADY_I_reg_0(E), + .\S_AXI_BRESP_ACC_reg[0] (\S_AXI_BRESP_ACC_reg[0] ), + .\USE_B_CHANNEL.cmd_b_empty_reg (\USE_B_CHANNEL.cmd_b_queue_n_18 ), + .access_is_incr_q(access_is_incr_q), + .aclk(aclk), + .allow_split_cmd__1(allow_split_cmd__1), + .almost_b_empty(almost_b_empty), + .almost_empty(almost_empty), + .areset_d(areset_d[1]), + .\areset_d_reg[0] (areset_d[0]), + .\areset_d_reg[1] (command_ongoing_reg_0), + .aresetn(aresetn), + .cmd_b_empty(cmd_b_empty), + .cmd_b_push_block(cmd_b_push_block), + .cmd_b_push_block_reg(\USE_B_CHANNEL.cmd_b_queue_n_16 ), + .cmd_empty(cmd_empty), + .cmd_push_block(cmd_push_block), + .cmd_push_block_reg(\USE_B_CHANNEL.cmd_b_queue_n_22 ), + .command_ongoing(command_ongoing), + .command_ongoing_reg(\USE_B_CHANNEL.cmd_b_queue_n_23 ), + .din(\USE_B_CHANNEL.cmd_b_queue_n_6 ), + .full(\inst/full_0 ), + .last_word(last_word), + .m_axi_awready(m_axi_awready), + .m_axi_awvalid(m_axi_awvalid), + .m_axi_bvalid(m_axi_bvalid), + .multiple_id_non_split(multiple_id_non_split), + .multiple_id_non_split_reg(\USE_B_CHANNEL.cmd_b_queue_n_13 ), + .multiple_id_non_split_reg_0(\USE_B_CHANNEL.cmd_b_queue_n_14 ), + .need_to_split_q(need_to_split_q), + .\num_transactions_q_reg[3] (num_transactions_q), + .\pushed_commands_reg[0] (pushed_new_cmd), + .\pushed_commands_reg[3] (pushed_commands_reg__0), + .\pushed_commands_reg[3]_0 (S_AXI_AREADY_I_i_3_n_0), + .queue_id(queue_id), + .ram_full_i_reg(\inst/full ), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_bready(s_axi_bready), + .split_in_progress_reg(split_in_progress_reg_n_0), + .split_ongoing_reg(\USE_B_CHANNEL.cmd_b_queue_n_15 ), + .wr_cmd_ready(wr_cmd_ready)); + LUT2 #( + .INIT(4'h2)) + access_is_incr_q_i_1 + (.I0(s_axi_awburst[0]), + .I1(s_axi_awburst[1]), + .O(access_is_incr)); + FDRE access_is_incr_q_reg + (.C(aclk), + .CE(E), + .D(access_is_incr), + .Q(access_is_incr_q), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + (* SOFT_HLUTNM = "soft_lutpair49" *) + LUT3 #( + .INIT(8'h08)) + \addr_step_q[10]_i_1 + (.I0(s_axi_awsize[1]), + .I1(s_axi_awsize[2]), + .I2(s_axi_awsize[0]), + .O(addr_step[10])); + (* SOFT_HLUTNM = "soft_lutpair47" *) + LUT3 #( + .INIT(8'h80)) + \addr_step_q[11]_i_1 + (.I0(s_axi_awsize[1]), + .I1(s_axi_awsize[0]), + .I2(s_axi_awsize[2]), + .O(addr_step[11])); + (* SOFT_HLUTNM = "soft_lutpair52" *) + LUT3 #( + .INIT(8'h04)) + \addr_step_q[5]_i_1 + (.I0(s_axi_awsize[2]), + .I1(s_axi_awsize[0]), + .I2(s_axi_awsize[1]), + .O(addr_step[5])); + (* SOFT_HLUTNM = "soft_lutpair47" *) + LUT3 #( + .INIT(8'h04)) + \addr_step_q[6]_i_1 + (.I0(s_axi_awsize[0]), + .I1(s_axi_awsize[1]), + .I2(s_axi_awsize[2]), + .O(addr_step[6])); + (* SOFT_HLUTNM = "soft_lutpair52" *) + LUT3 #( + .INIT(8'h08)) + \addr_step_q[7]_i_1 + (.I0(s_axi_awsize[1]), + .I1(s_axi_awsize[0]), + .I2(s_axi_awsize[2]), + .O(addr_step[7])); + (* SOFT_HLUTNM = "soft_lutpair48" *) + LUT3 #( + .INIT(8'h04)) + \addr_step_q[8]_i_1 + (.I0(s_axi_awsize[0]), + .I1(s_axi_awsize[2]), + .I2(s_axi_awsize[1]), + .O(addr_step[8])); + (* SOFT_HLUTNM = "soft_lutpair45" *) + LUT3 #( + .INIT(8'h08)) + \addr_step_q[9]_i_1 + (.I0(s_axi_awsize[2]), + .I1(s_axi_awsize[0]), + .I2(s_axi_awsize[1]), + .O(addr_step[9])); + FDRE \addr_step_q_reg[10] + (.C(aclk), + .CE(E), + .D(addr_step[10]), + .Q(addr_step_q[10]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \addr_step_q_reg[11] + (.C(aclk), + .CE(E), + .D(addr_step[11]), + .Q(addr_step_q[11]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \addr_step_q_reg[5] + (.C(aclk), + .CE(E), + .D(addr_step[5]), + .Q(addr_step_q[5]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \addr_step_q_reg[6] + (.C(aclk), + .CE(E), + .D(addr_step[6]), + .Q(addr_step_q[6]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \addr_step_q_reg[7] + (.C(aclk), + .CE(E), + .D(addr_step[7]), + .Q(addr_step_q[7]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \addr_step_q_reg[8] + (.C(aclk), + .CE(E), + .D(addr_step[8]), + .Q(addr_step_q[8]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \addr_step_q_reg[9] + (.C(aclk), + .CE(E), + .D(addr_step[9]), + .Q(addr_step_q[9]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \areset_d_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg ), + .Q(areset_d[0]), + .R(1'b0)); + FDRE \areset_d_reg[1] + (.C(aclk), + .CE(1'b1), + .D(areset_d[0]), + .Q(areset_d[1]), + .R(1'b0)); + FDRE cmd_b_push_block_reg + (.C(aclk), + .CE(1'b1), + .D(\USE_B_CHANNEL.cmd_b_queue_n_16 ), + .Q(cmd_b_push_block), + .R(1'b0)); + LUT1 #( + .INIT(2'h1)) + \cmd_depth[0]_i_1 + (.I0(cmd_depth_reg__0[0]), + .O(\cmd_depth[0]_i_1_n_0 )); + FDRE \cmd_depth_reg[0] + (.C(aclk), + .CE(\USE_BURSTS.cmd_queue_n_19 ), + .D(\cmd_depth[0]_i_1_n_0 ), + .Q(cmd_depth_reg__0[0]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \cmd_depth_reg[1] + (.C(aclk), + .CE(\USE_BURSTS.cmd_queue_n_19 ), + .D(\USE_BURSTS.cmd_queue_n_17 ), + .Q(cmd_depth_reg__0[1]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \cmd_depth_reg[2] + (.C(aclk), + .CE(\USE_BURSTS.cmd_queue_n_19 ), + .D(\USE_BURSTS.cmd_queue_n_16 ), + .Q(cmd_depth_reg__0[2]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \cmd_depth_reg[3] + (.C(aclk), + .CE(\USE_BURSTS.cmd_queue_n_19 ), + .D(\USE_BURSTS.cmd_queue_n_15 ), + .Q(cmd_depth_reg__0[3]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \cmd_depth_reg[4] + (.C(aclk), + .CE(\USE_BURSTS.cmd_queue_n_19 ), + .D(\USE_BURSTS.cmd_queue_n_14 ), + .Q(cmd_depth_reg__0[4]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \cmd_depth_reg[5] + (.C(aclk), + .CE(\USE_BURSTS.cmd_queue_n_19 ), + .D(\USE_BURSTS.cmd_queue_n_13 ), + .Q(cmd_depth_reg__0[5]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + LUT4 #( + .INIT(16'hCB08)) + cmd_empty_i_1 + (.I0(almost_empty), + .I1(wr_cmd_ready), + .I2(\USE_BURSTS.cmd_queue_n_12 ), + .I3(cmd_empty), + .O(cmd_empty_i_1_n_0)); + LUT6 #( + .INIT(64'h0000000000000100)) + cmd_empty_i_2 + (.I0(cmd_depth_reg__0[4]), + .I1(cmd_depth_reg__0[3]), + .I2(cmd_depth_reg__0[5]), + .I3(cmd_depth_reg__0[0]), + .I4(cmd_depth_reg__0[1]), + .I5(cmd_depth_reg__0[2]), + .O(almost_empty)); + FDSE cmd_empty_reg + (.C(aclk), + .CE(1'b1), + .D(cmd_empty_i_1_n_0), + .Q(cmd_empty), + .S(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE cmd_push_block_reg + (.C(aclk), + .CE(1'b1), + .D(\USE_B_CHANNEL.cmd_b_queue_n_22 ), + .Q(cmd_push_block), + .R(1'b0)); + LUT2 #( + .INIT(4'h2)) + command_ongoing_i_2 + (.I0(areset_d[1]), + .I1(areset_d[0]), + .O(command_ongoing_reg_0)); + FDRE command_ongoing_reg + (.C(aclk), + .CE(1'b1), + .D(\USE_B_CHANNEL.cmd_b_queue_n_23 ), + .Q(command_ongoing), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + (* SOFT_HLUTNM = "soft_lutpair44" *) + LUT4 #( + .INIT(16'h0001)) + \first_step_q[0]_i_1 + (.I0(s_axi_awsize[1]), + .I1(s_axi_awsize[0]), + .I2(s_axi_awlen[0]), + .I3(s_axi_awsize[2]), + .O(\first_step_q[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair53" *) + LUT2 #( + .INIT(4'h8)) + \first_step_q[10]_i_1 + (.I0(s_axi_awsize[2]), + .I1(\first_step_q[10]_i_2_n_0 ), + .O(first_step[10])); + LUT6 #( + .INIT(64'h2AAA800080000000)) + \first_step_q[10]_i_2 + (.I0(s_axi_awsize[1]), + .I1(s_axi_awlen[2]), + .I2(s_axi_awlen[0]), + .I3(s_axi_awlen[1]), + .I4(s_axi_awlen[3]), + .I5(s_axi_awsize[0]), + .O(\first_step_q[10]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair57" *) + LUT2 #( + .INIT(4'h8)) + \first_step_q[11]_i_1 + (.I0(s_axi_awsize[2]), + .I1(\first_step_q[11]_i_2_n_0 ), + .O(first_step[11])); + LUT6 #( + .INIT(64'h8000000000000000)) + \first_step_q[11]_i_2 + (.I0(s_axi_awsize[1]), + .I1(s_axi_awlen[3]), + .I2(s_axi_awlen[1]), + .I3(s_axi_awlen[0]), + .I4(s_axi_awlen[2]), + .I5(s_axi_awsize[0]), + .O(\first_step_q[11]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair45" *) + LUT5 #( + .INIT(32'h00000514)) + \first_step_q[1]_i_1 + (.I0(s_axi_awsize[1]), + .I1(s_axi_awsize[0]), + .I2(s_axi_awlen[0]), + .I3(s_axi_awlen[1]), + .I4(s_axi_awsize[2]), + .O(\first_step_q[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00000000000F3C6A)) + \first_step_q[2]_i_1 + (.I0(s_axi_awlen[2]), + .I1(s_axi_awlen[1]), + .I2(s_axi_awlen[0]), + .I3(s_axi_awsize[0]), + .I4(s_axi_awsize[1]), + .I5(s_axi_awsize[2]), + .O(\first_step_q[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair54" *) + LUT2 #( + .INIT(4'h2)) + \first_step_q[3]_i_1 + (.I0(\first_step_q[7]_i_2_n_0 ), + .I1(s_axi_awsize[2]), + .O(\first_step_q[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair44" *) + LUT5 #( + .INIT(32'h01FF0100)) + \first_step_q[4]_i_1 + (.I0(s_axi_awlen[0]), + .I1(s_axi_awsize[0]), + .I2(s_axi_awsize[1]), + .I3(s_axi_awsize[2]), + .I4(\first_step_q[8]_i_2_n_0 ), + .O(first_step[4])); + LUT6 #( + .INIT(64'h0036FFFF00360000)) + \first_step_q[5]_i_1 + (.I0(s_axi_awlen[1]), + .I1(s_axi_awlen[0]), + .I2(s_axi_awsize[0]), + .I3(s_axi_awsize[1]), + .I4(s_axi_awsize[2]), + .I5(\first_step_q[9]_i_2_n_0 ), + .O(first_step[5])); + (* SOFT_HLUTNM = "soft_lutpair53" *) + LUT3 #( + .INIT(8'hB8)) + \first_step_q[6]_i_1 + (.I0(\first_step_q[6]_i_2_n_0 ), + .I1(s_axi_awsize[2]), + .I2(\first_step_q[10]_i_2_n_0 ), + .O(first_step[6])); + LUT5 #( + .INIT(32'h07531642)) + \first_step_q[6]_i_2 + (.I0(s_axi_awsize[1]), + .I1(s_axi_awsize[0]), + .I2(s_axi_awlen[0]), + .I3(s_axi_awlen[1]), + .I4(s_axi_awlen[2]), + .O(\first_step_q[6]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair54" *) + LUT3 #( + .INIT(8'hB8)) + \first_step_q[7]_i_1 + (.I0(\first_step_q[7]_i_2_n_0 ), + .I1(s_axi_awsize[2]), + .I2(\first_step_q[11]_i_2_n_0 ), + .O(first_step[7])); + LUT6 #( + .INIT(64'h07FD53B916EC42A8)) + \first_step_q[7]_i_2 + (.I0(s_axi_awsize[1]), + .I1(s_axi_awsize[0]), + .I2(s_axi_awlen[1]), + .I3(s_axi_awlen[0]), + .I4(s_axi_awlen[2]), + .I5(s_axi_awlen[3]), + .O(\first_step_q[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair56" *) + LUT2 #( + .INIT(4'h8)) + \first_step_q[8]_i_1 + (.I0(s_axi_awsize[2]), + .I1(\first_step_q[8]_i_2_n_0 ), + .O(first_step[8])); + LUT6 #( + .INIT(64'h14EAEA6262C8C840)) + \first_step_q[8]_i_2 + (.I0(s_axi_awsize[1]), + .I1(s_axi_awsize[0]), + .I2(s_axi_awlen[3]), + .I3(s_axi_awlen[1]), + .I4(s_axi_awlen[0]), + .I5(s_axi_awlen[2]), + .O(\first_step_q[8]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair57" *) + LUT2 #( + .INIT(4'h8)) + \first_step_q[9]_i_1 + (.I0(s_axi_awsize[2]), + .I1(\first_step_q[9]_i_2_n_0 ), + .O(first_step[9])); + LUT6 #( + .INIT(64'h4AA2A2A228808080)) + \first_step_q[9]_i_2 + (.I0(s_axi_awsize[1]), + .I1(s_axi_awsize[0]), + .I2(s_axi_awlen[2]), + .I3(s_axi_awlen[0]), + .I4(s_axi_awlen[1]), + .I5(s_axi_awlen[3]), + .O(\first_step_q[9]_i_2_n_0 )); + FDRE \first_step_q_reg[0] + (.C(aclk), + .CE(E), + .D(\first_step_q[0]_i_1_n_0 ), + .Q(first_step_q[0]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \first_step_q_reg[10] + (.C(aclk), + .CE(E), + .D(first_step[10]), + .Q(first_step_q[10]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \first_step_q_reg[11] + (.C(aclk), + .CE(E), + .D(first_step[11]), + .Q(first_step_q[11]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \first_step_q_reg[1] + (.C(aclk), + .CE(E), + .D(\first_step_q[1]_i_1_n_0 ), + .Q(first_step_q[1]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \first_step_q_reg[2] + (.C(aclk), + .CE(E), + .D(\first_step_q[2]_i_1_n_0 ), + .Q(first_step_q[2]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \first_step_q_reg[3] + (.C(aclk), + .CE(E), + .D(\first_step_q[3]_i_1_n_0 ), + .Q(first_step_q[3]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \first_step_q_reg[4] + (.C(aclk), + .CE(E), + .D(first_step[4]), + .Q(first_step_q[4]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \first_step_q_reg[5] + (.C(aclk), + .CE(E), + .D(first_step[5]), + .Q(first_step_q[5]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \first_step_q_reg[6] + (.C(aclk), + .CE(E), + .D(first_step[6]), + .Q(first_step_q[6]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \first_step_q_reg[7] + (.C(aclk), + .CE(E), + .D(first_step[7]), + .Q(first_step_q[7]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \first_step_q_reg[8] + (.C(aclk), + .CE(E), + .D(first_step[8]), + .Q(first_step_q[8]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \first_step_q_reg[9] + (.C(aclk), + .CE(E), + .D(first_step[9]), + .Q(first_step_q[9]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + LUT6 #( + .INIT(64'h4444444444444440)) + incr_need_to_split + (.I0(s_axi_awburst[1]), + .I1(s_axi_awburst[0]), + .I2(s_axi_awlen[5]), + .I3(s_axi_awlen[4]), + .I4(s_axi_awlen[6]), + .I5(s_axi_awlen[7]), + .O(incr_need_to_split__0)); + FDRE incr_need_to_split_q_reg + (.C(aclk), + .CE(E), + .D(incr_need_to_split__0), + .Q(need_to_split_q), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[0]_INST_0 + (.I0(next_mi_addr[0]), + .I1(size_mask_q[0]), + .I2(S_AXI_AADDR_Q[0]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[0])); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[10]_INST_0 + (.I0(next_mi_addr[10]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[10]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[10])); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[11]_INST_0 + (.I0(next_mi_addr[11]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[11]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[11])); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[12]_INST_0 + (.I0(next_mi_addr[12]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[12]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[12])); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[13]_INST_0 + (.I0(next_mi_addr[13]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[13]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[13])); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[14]_INST_0 + (.I0(next_mi_addr[14]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[14]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[14])); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[15]_INST_0 + (.I0(next_mi_addr[15]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[15]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[15])); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[16]_INST_0 + (.I0(next_mi_addr[16]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[16]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[16])); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[17]_INST_0 + (.I0(next_mi_addr[17]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[17]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[17])); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[18]_INST_0 + (.I0(next_mi_addr[18]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[18]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[18])); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[19]_INST_0 + (.I0(next_mi_addr[19]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[19]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[19])); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[1]_INST_0 + (.I0(next_mi_addr[1]), + .I1(size_mask_q[1]), + .I2(S_AXI_AADDR_Q[1]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[1])); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[20]_INST_0 + (.I0(next_mi_addr[20]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[20]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[20])); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[21]_INST_0 + (.I0(next_mi_addr[21]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[21]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[21])); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[22]_INST_0 + (.I0(next_mi_addr[22]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[22]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[22])); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[23]_INST_0 + (.I0(next_mi_addr[23]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[23]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[23])); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[24]_INST_0 + (.I0(next_mi_addr[24]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[24]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[24])); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[25]_INST_0 + (.I0(next_mi_addr[25]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[25]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[25])); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[26]_INST_0 + (.I0(next_mi_addr[26]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[26]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[26])); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[27]_INST_0 + (.I0(next_mi_addr[27]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[27]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[27])); + (* SOFT_HLUTNM = "soft_lutpair43" *) + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[28]_INST_0 + (.I0(next_mi_addr[28]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[28]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[28])); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[29]_INST_0 + (.I0(next_mi_addr[29]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[29]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[29])); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[2]_INST_0 + (.I0(next_mi_addr[2]), + .I1(size_mask_q[2]), + .I2(S_AXI_AADDR_Q[2]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[2])); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[30]_INST_0 + (.I0(next_mi_addr[30]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[30]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[30])); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[31]_INST_0 + (.I0(next_mi_addr[31]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[31]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[31])); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[3]_INST_0 + (.I0(next_mi_addr[3]), + .I1(size_mask_q[3]), + .I2(S_AXI_AADDR_Q[3]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[3])); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[4]_INST_0 + (.I0(next_mi_addr[4]), + .I1(size_mask_q[4]), + .I2(S_AXI_AADDR_Q[4]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[4])); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[5]_INST_0 + (.I0(next_mi_addr[5]), + .I1(size_mask_q[5]), + .I2(S_AXI_AADDR_Q[5]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[5])); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[6]_INST_0 + (.I0(next_mi_addr[6]), + .I1(size_mask_q[6]), + .I2(S_AXI_AADDR_Q[6]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[6])); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[7]_INST_0 + (.I0(next_mi_addr[7]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[7]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[7])); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[8]_INST_0 + (.I0(next_mi_addr[8]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[8]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[8])); + LUT5 #( + .INIT(32'h88F0F0F0)) + \m_axi_awaddr[9]_INST_0 + (.I0(next_mi_addr[9]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[9]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(m_axi_awaddr[9])); + LUT2 #( + .INIT(4'h2)) + \m_axi_awlock[0]_INST_0 + (.I0(\S_AXI_ALOCK_Q_reg_n_0_[0] ), + .I1(need_to_split_q), + .O(m_axi_awlock)); + FDRE multiple_id_non_split_reg + (.C(aclk), + .CE(1'b1), + .D(\USE_BURSTS.cmd_queue_n_23 ), + .Q(multiple_id_non_split), + .R(1'b0)); + LUT4 #( + .INIT(16'h569A)) + \next_mi_addr[11]_i_2 + (.I0(m_axi_awaddr[11]), + .I1(first_split__2), + .I2(addr_step_q[11]), + .I3(first_step_q[11]), + .O(\next_mi_addr[11]_i_2_n_0 )); + LUT4 #( + .INIT(16'h569A)) + \next_mi_addr[11]_i_3 + (.I0(m_axi_awaddr[10]), + .I1(first_split__2), + .I2(addr_step_q[10]), + .I3(first_step_q[10]), + .O(\next_mi_addr[11]_i_3_n_0 )); + LUT4 #( + .INIT(16'h569A)) + \next_mi_addr[11]_i_4 + (.I0(m_axi_awaddr[9]), + .I1(first_split__2), + .I2(addr_step_q[9]), + .I3(first_step_q[9]), + .O(\next_mi_addr[11]_i_4_n_0 )); + LUT4 #( + .INIT(16'h569A)) + \next_mi_addr[11]_i_5 + (.I0(m_axi_awaddr[8]), + .I1(first_split__2), + .I2(addr_step_q[8]), + .I3(first_step_q[8]), + .O(\next_mi_addr[11]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair46" *) + LUT4 #( + .INIT(16'h0001)) + \next_mi_addr[11]_i_6 + (.I0(pushed_commands_reg__0[2]), + .I1(pushed_commands_reg__0[3]), + .I2(pushed_commands_reg__0[1]), + .I3(pushed_commands_reg__0[0]), + .O(first_split__2)); + LUT5 #( + .INIT(32'h88F0F0F0)) + \next_mi_addr[15]_i_2 + (.I0(next_mi_addr[15]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[15]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[15]_i_2_n_0 )); + LUT5 #( + .INIT(32'h88F0F0F0)) + \next_mi_addr[15]_i_3 + (.I0(next_mi_addr[14]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[14]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[15]_i_3_n_0 )); + LUT5 #( + .INIT(32'h88F0F0F0)) + \next_mi_addr[15]_i_4 + (.I0(next_mi_addr[13]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[13]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[15]_i_4_n_0 )); + LUT5 #( + .INIT(32'h88F0F0F0)) + \next_mi_addr[15]_i_5 + (.I0(next_mi_addr[12]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[12]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[15]_i_5_n_0 )); + LUT5 #( + .INIT(32'h88F0F0F0)) + \next_mi_addr[15]_i_6 + (.I0(next_mi_addr[15]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[15]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[15]_i_6_n_0 )); + LUT5 #( + .INIT(32'h88F0F0F0)) + \next_mi_addr[15]_i_7 + (.I0(next_mi_addr[14]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[14]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[15]_i_7_n_0 )); + LUT5 #( + .INIT(32'h88F0F0F0)) + \next_mi_addr[15]_i_8 + (.I0(next_mi_addr[13]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[13]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[15]_i_8_n_0 )); + LUT5 #( + .INIT(32'h88F0F0F0)) + \next_mi_addr[15]_i_9 + (.I0(next_mi_addr[12]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[12]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[15]_i_9_n_0 )); + LUT5 #( + .INIT(32'h88F0F0F0)) + \next_mi_addr[19]_i_2 + (.I0(next_mi_addr[19]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[19]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[19]_i_2_n_0 )); + LUT5 #( + .INIT(32'h88F0F0F0)) + \next_mi_addr[19]_i_3 + (.I0(next_mi_addr[18]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[18]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[19]_i_3_n_0 )); + LUT5 #( + .INIT(32'h88F0F0F0)) + \next_mi_addr[19]_i_4 + (.I0(next_mi_addr[17]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[17]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[19]_i_4_n_0 )); + LUT5 #( + .INIT(32'h88F0F0F0)) + \next_mi_addr[19]_i_5 + (.I0(next_mi_addr[16]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[16]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[19]_i_5_n_0 )); + LUT5 #( + .INIT(32'h88F0F0F0)) + \next_mi_addr[23]_i_2 + (.I0(next_mi_addr[23]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[23]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[23]_i_2_n_0 )); + LUT5 #( + .INIT(32'h88F0F0F0)) + \next_mi_addr[23]_i_3 + (.I0(next_mi_addr[22]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[22]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[23]_i_3_n_0 )); + LUT5 #( + .INIT(32'h88F0F0F0)) + \next_mi_addr[23]_i_4 + (.I0(next_mi_addr[21]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[21]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[23]_i_4_n_0 )); + LUT5 #( + .INIT(32'h88F0F0F0)) + \next_mi_addr[23]_i_5 + (.I0(next_mi_addr[20]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[20]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[23]_i_5_n_0 )); + LUT5 #( + .INIT(32'h88F0F0F0)) + \next_mi_addr[27]_i_2 + (.I0(next_mi_addr[27]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[27]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[27]_i_2_n_0 )); + LUT5 #( + .INIT(32'h88F0F0F0)) + \next_mi_addr[27]_i_3 + (.I0(next_mi_addr[26]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[26]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[27]_i_3_n_0 )); + LUT5 #( + .INIT(32'h88F0F0F0)) + \next_mi_addr[27]_i_4 + (.I0(next_mi_addr[25]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[25]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[27]_i_4_n_0 )); + LUT5 #( + .INIT(32'h88F0F0F0)) + \next_mi_addr[27]_i_5 + (.I0(next_mi_addr[24]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[24]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[27]_i_5_n_0 )); + LUT5 #( + .INIT(32'h88F0F0F0)) + \next_mi_addr[31]_i_2 + (.I0(next_mi_addr[31]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[31]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[31]_i_2_n_0 )); + LUT5 #( + .INIT(32'h88F0F0F0)) + \next_mi_addr[31]_i_3 + (.I0(next_mi_addr[30]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[30]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[31]_i_3_n_0 )); + LUT5 #( + .INIT(32'h88F0F0F0)) + \next_mi_addr[31]_i_4 + (.I0(next_mi_addr[29]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[29]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[31]_i_4_n_0 )); + LUT5 #( + .INIT(32'h88F0F0F0)) + \next_mi_addr[31]_i_5 + (.I0(next_mi_addr[28]), + .I1(size_mask_q[31]), + .I2(S_AXI_AADDR_Q[28]), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[31]_i_5_n_0 )); + LUT6 #( + .INIT(64'h1BBBE444E444E444)) + \next_mi_addr[3]_i_2 + (.I0(M_AXI_AADDR_I1__0), + .I1(S_AXI_AADDR_Q[3]), + .I2(size_mask_q[3]), + .I3(next_mi_addr[3]), + .I4(first_split__2), + .I5(first_step_q[3]), + .O(\next_mi_addr[3]_i_2_n_0 )); + LUT6 #( + .INIT(64'h1BBBE444E444E444)) + \next_mi_addr[3]_i_3 + (.I0(M_AXI_AADDR_I1__0), + .I1(S_AXI_AADDR_Q[2]), + .I2(size_mask_q[2]), + .I3(next_mi_addr[2]), + .I4(first_split__2), + .I5(first_step_q[2]), + .O(\next_mi_addr[3]_i_3_n_0 )); + LUT6 #( + .INIT(64'h1BBBE444E444E444)) + \next_mi_addr[3]_i_4 + (.I0(M_AXI_AADDR_I1__0), + .I1(S_AXI_AADDR_Q[1]), + .I2(size_mask_q[1]), + .I3(next_mi_addr[1]), + .I4(first_split__2), + .I5(first_step_q[1]), + .O(\next_mi_addr[3]_i_4_n_0 )); + LUT6 #( + .INIT(64'h1BBBE444E444E444)) + \next_mi_addr[3]_i_5 + (.I0(M_AXI_AADDR_I1__0), + .I1(S_AXI_AADDR_Q[0]), + .I2(size_mask_q[0]), + .I3(next_mi_addr[0]), + .I4(first_split__2), + .I5(first_step_q[0]), + .O(\next_mi_addr[3]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair43" *) + LUT2 #( + .INIT(4'h8)) + \next_mi_addr[3]_i_6 + (.I0(split_ongoing), + .I1(access_is_incr_q), + .O(M_AXI_AADDR_I1__0)); + LUT4 #( + .INIT(16'h569A)) + \next_mi_addr[7]_i_2 + (.I0(m_axi_awaddr[7]), + .I1(first_split__2), + .I2(addr_step_q[7]), + .I3(first_step_q[7]), + .O(\next_mi_addr[7]_i_2_n_0 )); + LUT4 #( + .INIT(16'h569A)) + \next_mi_addr[7]_i_3 + (.I0(m_axi_awaddr[6]), + .I1(first_split__2), + .I2(addr_step_q[6]), + .I3(first_step_q[6]), + .O(\next_mi_addr[7]_i_3_n_0 )); + LUT4 #( + .INIT(16'h569A)) + \next_mi_addr[7]_i_4 + (.I0(m_axi_awaddr[5]), + .I1(first_split__2), + .I2(addr_step_q[5]), + .I3(first_step_q[5]), + .O(\next_mi_addr[7]_i_4_n_0 )); + LUT4 #( + .INIT(16'h569A)) + \next_mi_addr[7]_i_5 + (.I0(m_axi_awaddr[4]), + .I1(first_split__2), + .I2(size_mask_q[0]), + .I3(first_step_q[4]), + .O(\next_mi_addr[7]_i_5_n_0 )); + FDRE \next_mi_addr_reg[0] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[3]_i_1_n_7 ), + .Q(next_mi_addr[0]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \next_mi_addr_reg[10] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[11]_i_1_n_5 ), + .Q(next_mi_addr[10]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \next_mi_addr_reg[11] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[11]_i_1_n_4 ), + .Q(next_mi_addr[11]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + CARRY4 \next_mi_addr_reg[11]_i_1 + (.CI(\next_mi_addr_reg[7]_i_1_n_0 ), + .CO({\next_mi_addr_reg[11]_i_1_n_0 ,\next_mi_addr_reg[11]_i_1_n_1 ,\next_mi_addr_reg[11]_i_1_n_2 ,\next_mi_addr_reg[11]_i_1_n_3 }), + .CYINIT(1'b0), + .DI(m_axi_awaddr[11:8]), + .O({\next_mi_addr_reg[11]_i_1_n_4 ,\next_mi_addr_reg[11]_i_1_n_5 ,\next_mi_addr_reg[11]_i_1_n_6 ,\next_mi_addr_reg[11]_i_1_n_7 }), + .S({\next_mi_addr[11]_i_2_n_0 ,\next_mi_addr[11]_i_3_n_0 ,\next_mi_addr[11]_i_4_n_0 ,\next_mi_addr[11]_i_5_n_0 })); + FDRE \next_mi_addr_reg[12] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[15]_i_1_n_7 ), + .Q(next_mi_addr[12]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \next_mi_addr_reg[13] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[15]_i_1_n_6 ), + .Q(next_mi_addr[13]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \next_mi_addr_reg[14] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[15]_i_1_n_5 ), + .Q(next_mi_addr[14]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \next_mi_addr_reg[15] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[15]_i_1_n_4 ), + .Q(next_mi_addr[15]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + CARRY4 \next_mi_addr_reg[15]_i_1 + (.CI(\next_mi_addr_reg[11]_i_1_n_0 ), + .CO({\next_mi_addr_reg[15]_i_1_n_0 ,\next_mi_addr_reg[15]_i_1_n_1 ,\next_mi_addr_reg[15]_i_1_n_2 ,\next_mi_addr_reg[15]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({\next_mi_addr[15]_i_2_n_0 ,\next_mi_addr[15]_i_3_n_0 ,\next_mi_addr[15]_i_4_n_0 ,\next_mi_addr[15]_i_5_n_0 }), + .O({\next_mi_addr_reg[15]_i_1_n_4 ,\next_mi_addr_reg[15]_i_1_n_5 ,\next_mi_addr_reg[15]_i_1_n_6 ,\next_mi_addr_reg[15]_i_1_n_7 }), + .S({\next_mi_addr[15]_i_6_n_0 ,\next_mi_addr[15]_i_7_n_0 ,\next_mi_addr[15]_i_8_n_0 ,\next_mi_addr[15]_i_9_n_0 })); + FDRE \next_mi_addr_reg[16] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[19]_i_1_n_7 ), + .Q(next_mi_addr[16]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \next_mi_addr_reg[17] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[19]_i_1_n_6 ), + .Q(next_mi_addr[17]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \next_mi_addr_reg[18] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[19]_i_1_n_5 ), + .Q(next_mi_addr[18]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \next_mi_addr_reg[19] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[19]_i_1_n_4 ), + .Q(next_mi_addr[19]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + CARRY4 \next_mi_addr_reg[19]_i_1 + (.CI(\next_mi_addr_reg[15]_i_1_n_0 ), + .CO({\next_mi_addr_reg[19]_i_1_n_0 ,\next_mi_addr_reg[19]_i_1_n_1 ,\next_mi_addr_reg[19]_i_1_n_2 ,\next_mi_addr_reg[19]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\next_mi_addr_reg[19]_i_1_n_4 ,\next_mi_addr_reg[19]_i_1_n_5 ,\next_mi_addr_reg[19]_i_1_n_6 ,\next_mi_addr_reg[19]_i_1_n_7 }), + .S({\next_mi_addr[19]_i_2_n_0 ,\next_mi_addr[19]_i_3_n_0 ,\next_mi_addr[19]_i_4_n_0 ,\next_mi_addr[19]_i_5_n_0 })); + FDRE \next_mi_addr_reg[1] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[3]_i_1_n_6 ), + .Q(next_mi_addr[1]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \next_mi_addr_reg[20] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[23]_i_1_n_7 ), + .Q(next_mi_addr[20]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \next_mi_addr_reg[21] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[23]_i_1_n_6 ), + .Q(next_mi_addr[21]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \next_mi_addr_reg[22] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[23]_i_1_n_5 ), + .Q(next_mi_addr[22]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \next_mi_addr_reg[23] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[23]_i_1_n_4 ), + .Q(next_mi_addr[23]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + CARRY4 \next_mi_addr_reg[23]_i_1 + (.CI(\next_mi_addr_reg[19]_i_1_n_0 ), + .CO({\next_mi_addr_reg[23]_i_1_n_0 ,\next_mi_addr_reg[23]_i_1_n_1 ,\next_mi_addr_reg[23]_i_1_n_2 ,\next_mi_addr_reg[23]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\next_mi_addr_reg[23]_i_1_n_4 ,\next_mi_addr_reg[23]_i_1_n_5 ,\next_mi_addr_reg[23]_i_1_n_6 ,\next_mi_addr_reg[23]_i_1_n_7 }), + .S({\next_mi_addr[23]_i_2_n_0 ,\next_mi_addr[23]_i_3_n_0 ,\next_mi_addr[23]_i_4_n_0 ,\next_mi_addr[23]_i_5_n_0 })); + FDRE \next_mi_addr_reg[24] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[27]_i_1_n_7 ), + .Q(next_mi_addr[24]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \next_mi_addr_reg[25] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[27]_i_1_n_6 ), + .Q(next_mi_addr[25]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \next_mi_addr_reg[26] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[27]_i_1_n_5 ), + .Q(next_mi_addr[26]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \next_mi_addr_reg[27] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[27]_i_1_n_4 ), + .Q(next_mi_addr[27]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + CARRY4 \next_mi_addr_reg[27]_i_1 + (.CI(\next_mi_addr_reg[23]_i_1_n_0 ), + .CO({\next_mi_addr_reg[27]_i_1_n_0 ,\next_mi_addr_reg[27]_i_1_n_1 ,\next_mi_addr_reg[27]_i_1_n_2 ,\next_mi_addr_reg[27]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\next_mi_addr_reg[27]_i_1_n_4 ,\next_mi_addr_reg[27]_i_1_n_5 ,\next_mi_addr_reg[27]_i_1_n_6 ,\next_mi_addr_reg[27]_i_1_n_7 }), + .S({\next_mi_addr[27]_i_2_n_0 ,\next_mi_addr[27]_i_3_n_0 ,\next_mi_addr[27]_i_4_n_0 ,\next_mi_addr[27]_i_5_n_0 })); + FDRE \next_mi_addr_reg[28] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[31]_i_1_n_7 ), + .Q(next_mi_addr[28]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \next_mi_addr_reg[29] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[31]_i_1_n_6 ), + .Q(next_mi_addr[29]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \next_mi_addr_reg[2] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[3]_i_1_n_5 ), + .Q(next_mi_addr[2]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \next_mi_addr_reg[30] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[31]_i_1_n_5 ), + .Q(next_mi_addr[30]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \next_mi_addr_reg[31] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[31]_i_1_n_4 ), + .Q(next_mi_addr[31]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + CARRY4 \next_mi_addr_reg[31]_i_1 + (.CI(\next_mi_addr_reg[27]_i_1_n_0 ), + .CO({\NLW_next_mi_addr_reg[31]_i_1_CO_UNCONNECTED [3],\next_mi_addr_reg[31]_i_1_n_1 ,\next_mi_addr_reg[31]_i_1_n_2 ,\next_mi_addr_reg[31]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\next_mi_addr_reg[31]_i_1_n_4 ,\next_mi_addr_reg[31]_i_1_n_5 ,\next_mi_addr_reg[31]_i_1_n_6 ,\next_mi_addr_reg[31]_i_1_n_7 }), + .S({\next_mi_addr[31]_i_2_n_0 ,\next_mi_addr[31]_i_3_n_0 ,\next_mi_addr[31]_i_4_n_0 ,\next_mi_addr[31]_i_5_n_0 })); + FDRE \next_mi_addr_reg[3] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[3]_i_1_n_4 ), + .Q(next_mi_addr[3]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + CARRY4 \next_mi_addr_reg[3]_i_1 + (.CI(1'b0), + .CO({\next_mi_addr_reg[3]_i_1_n_0 ,\next_mi_addr_reg[3]_i_1_n_1 ,\next_mi_addr_reg[3]_i_1_n_2 ,\next_mi_addr_reg[3]_i_1_n_3 }), + .CYINIT(1'b0), + .DI(m_axi_awaddr[3:0]), + .O({\next_mi_addr_reg[3]_i_1_n_4 ,\next_mi_addr_reg[3]_i_1_n_5 ,\next_mi_addr_reg[3]_i_1_n_6 ,\next_mi_addr_reg[3]_i_1_n_7 }), + .S({\next_mi_addr[3]_i_2_n_0 ,\next_mi_addr[3]_i_3_n_0 ,\next_mi_addr[3]_i_4_n_0 ,\next_mi_addr[3]_i_5_n_0 })); + FDRE \next_mi_addr_reg[4] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[7]_i_1_n_7 ), + .Q(next_mi_addr[4]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \next_mi_addr_reg[5] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[7]_i_1_n_6 ), + .Q(next_mi_addr[5]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \next_mi_addr_reg[6] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[7]_i_1_n_5 ), + .Q(next_mi_addr[6]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \next_mi_addr_reg[7] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[7]_i_1_n_4 ), + .Q(next_mi_addr[7]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + CARRY4 \next_mi_addr_reg[7]_i_1 + (.CI(\next_mi_addr_reg[3]_i_1_n_0 ), + .CO({\next_mi_addr_reg[7]_i_1_n_0 ,\next_mi_addr_reg[7]_i_1_n_1 ,\next_mi_addr_reg[7]_i_1_n_2 ,\next_mi_addr_reg[7]_i_1_n_3 }), + .CYINIT(1'b0), + .DI(m_axi_awaddr[7:4]), + .O({\next_mi_addr_reg[7]_i_1_n_4 ,\next_mi_addr_reg[7]_i_1_n_5 ,\next_mi_addr_reg[7]_i_1_n_6 ,\next_mi_addr_reg[7]_i_1_n_7 }), + .S({\next_mi_addr[7]_i_2_n_0 ,\next_mi_addr[7]_i_3_n_0 ,\next_mi_addr[7]_i_4_n_0 ,\next_mi_addr[7]_i_5_n_0 })); + FDRE \next_mi_addr_reg[8] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[11]_i_1_n_7 ), + .Q(next_mi_addr[8]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \next_mi_addr_reg[9] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[11]_i_1_n_6 ), + .Q(next_mi_addr[9]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \num_transactions_q_reg[0] + (.C(aclk), + .CE(E), + .D(s_axi_awlen[4]), + .Q(num_transactions_q[0]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \num_transactions_q_reg[1] + (.C(aclk), + .CE(E), + .D(s_axi_awlen[5]), + .Q(num_transactions_q[1]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \num_transactions_q_reg[2] + (.C(aclk), + .CE(E), + .D(s_axi_awlen[6]), + .Q(num_transactions_q[2]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \num_transactions_q_reg[3] + (.C(aclk), + .CE(E), + .D(s_axi_awlen[7]), + .Q(num_transactions_q[3]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + LUT1 #( + .INIT(2'h1)) + \pushed_commands[0]_i_1 + (.I0(pushed_commands_reg__0[0]), + .O(p_0_in[0])); + (* SOFT_HLUTNM = "soft_lutpair50" *) + LUT2 #( + .INIT(4'h6)) + \pushed_commands[1]_i_1 + (.I0(pushed_commands_reg__0[0]), + .I1(pushed_commands_reg__0[1]), + .O(p_0_in[1])); + (* SOFT_HLUTNM = "soft_lutpair50" *) + LUT3 #( + .INIT(8'h78)) + \pushed_commands[2]_i_1 + (.I0(pushed_commands_reg__0[0]), + .I1(pushed_commands_reg__0[1]), + .I2(pushed_commands_reg__0[2]), + .O(p_0_in[2])); + LUT2 #( + .INIT(4'hB)) + \pushed_commands[3]_i_1 + (.I0(E), + .I1(aresetn), + .O(\pushed_commands[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair46" *) + LUT4 #( + .INIT(16'h7F80)) + \pushed_commands[3]_i_2 + (.I0(pushed_commands_reg__0[1]), + .I1(pushed_commands_reg__0[0]), + .I2(pushed_commands_reg__0[2]), + .I3(pushed_commands_reg__0[3]), + .O(p_0_in[3])); + FDRE \pushed_commands_reg[0] + (.C(aclk), + .CE(pushed_new_cmd), + .D(p_0_in[0]), + .Q(pushed_commands_reg__0[0]), + .R(\pushed_commands[3]_i_1_n_0 )); + FDRE \pushed_commands_reg[1] + (.C(aclk), + .CE(pushed_new_cmd), + .D(p_0_in[1]), + .Q(pushed_commands_reg__0[1]), + .R(\pushed_commands[3]_i_1_n_0 )); + FDRE \pushed_commands_reg[2] + (.C(aclk), + .CE(pushed_new_cmd), + .D(p_0_in[2]), + .Q(pushed_commands_reg__0[2]), + .R(\pushed_commands[3]_i_1_n_0 )); + FDRE \pushed_commands_reg[3] + (.C(aclk), + .CE(pushed_new_cmd), + .D(p_0_in[3]), + .Q(pushed_commands_reg__0[3]), + .R(\pushed_commands[3]_i_1_n_0 )); + FDRE \queue_id_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\USE_BURSTS.cmd_queue_n_21 ), + .Q(queue_id), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + (* SOFT_HLUTNM = "soft_lutpair49" *) + LUT3 #( + .INIT(8'h01)) + \size_mask_q[0]_i_1 + (.I0(s_axi_awsize[2]), + .I1(s_axi_awsize[0]), + .I2(s_axi_awsize[1]), + .O(size_mask[0])); + (* SOFT_HLUTNM = "soft_lutpair55" *) + LUT2 #( + .INIT(4'h1)) + \size_mask_q[1]_i_1 + (.I0(s_axi_awsize[2]), + .I1(s_axi_awsize[1]), + .O(size_mask[1])); + (* SOFT_HLUTNM = "soft_lutpair51" *) + LUT3 #( + .INIT(8'h07)) + \size_mask_q[2]_i_1 + (.I0(s_axi_awsize[0]), + .I1(s_axi_awsize[1]), + .I2(s_axi_awsize[2]), + .O(size_mask[2])); + (* SOFT_HLUTNM = "soft_lutpair56" *) + LUT1 #( + .INIT(2'h1)) + \size_mask_q[3]_i_1 + (.I0(s_axi_awsize[2]), + .O(size_mask[3])); + (* SOFT_HLUTNM = "soft_lutpair51" *) + LUT3 #( + .INIT(8'h57)) + \size_mask_q[4]_i_1 + (.I0(s_axi_awsize[2]), + .I1(s_axi_awsize[0]), + .I2(s_axi_awsize[1]), + .O(size_mask[4])); + (* SOFT_HLUTNM = "soft_lutpair55" *) + LUT2 #( + .INIT(4'h7)) + \size_mask_q[5]_i_1 + (.I0(s_axi_awsize[2]), + .I1(s_axi_awsize[1]), + .O(size_mask[5])); + (* SOFT_HLUTNM = "soft_lutpair48" *) + LUT3 #( + .INIT(8'h7F)) + \size_mask_q[6]_i_1 + (.I0(s_axi_awsize[2]), + .I1(s_axi_awsize[0]), + .I2(s_axi_awsize[1]), + .O(size_mask[6])); + FDRE \size_mask_q_reg[0] + (.C(aclk), + .CE(E), + .D(size_mask[0]), + .Q(size_mask_q[0]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \size_mask_q_reg[1] + (.C(aclk), + .CE(E), + .D(size_mask[1]), + .Q(size_mask_q[1]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \size_mask_q_reg[2] + (.C(aclk), + .CE(E), + .D(size_mask[2]), + .Q(size_mask_q[2]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \size_mask_q_reg[31] + (.C(aclk), + .CE(E), + .D(1'b1), + .Q(size_mask_q[31]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \size_mask_q_reg[3] + (.C(aclk), + .CE(E), + .D(size_mask[3]), + .Q(size_mask_q[3]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \size_mask_q_reg[4] + (.C(aclk), + .CE(E), + .D(size_mask[4]), + .Q(size_mask_q[4]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \size_mask_q_reg[5] + (.C(aclk), + .CE(E), + .D(size_mask[5]), + .Q(size_mask_q[5]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE \size_mask_q_reg[6] + (.C(aclk), + .CE(E), + .D(size_mask[6]), + .Q(size_mask_q[6]), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); + FDRE split_in_progress_reg + (.C(aclk), + .CE(1'b1), + .D(\USE_BURSTS.cmd_queue_n_22 ), + .Q(split_in_progress_reg_n_0), + .R(1'b0)); + FDRE split_ongoing_reg + (.C(aclk), + .CE(pushed_new_cmd), + .D(\USE_B_CHANNEL.cmd_b_queue_n_6 ), + .Q(split_ongoing), + .R(\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg )); +endmodule + +(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_11_a_axi3_conv" *) +module Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_a_axi3_conv__parameterized0 + (E, + \m_axi_arid[0] , + m_axi_arlen, + m_axi_rready, + s_axi_rvalid, + m_axi_arlock, + s_axi_rlast, + m_axi_araddr, + m_axi_arvalid, + m_axi_arsize, + m_axi_arburst, + m_axi_arcache, + m_axi_arprot, + m_axi_arqos, + aclk, + aresetn_0, + s_axi_arid, + s_axi_arlock, + s_axi_arlen, + aresetn, + s_axi_arsize, + m_axi_rvalid, + s_axi_rready, + m_axi_rlast, + m_axi_arready, + s_axi_arvalid, + areset_d, + \areset_d_reg[1] , + s_axi_araddr, + s_axi_arburst, + s_axi_arcache, + s_axi_arprot, + s_axi_arqos); + output [0:0]E; + output \m_axi_arid[0] ; + output [3:0]m_axi_arlen; + output m_axi_rready; + output s_axi_rvalid; + output [0:0]m_axi_arlock; + output s_axi_rlast; + output [31:0]m_axi_araddr; + output m_axi_arvalid; + output [2:0]m_axi_arsize; + output [1:0]m_axi_arburst; + output [3:0]m_axi_arcache; + output [2:0]m_axi_arprot; + output [3:0]m_axi_arqos; + input aclk; + input aresetn_0; + input [0:0]s_axi_arid; + input [0:0]s_axi_arlock; + input [7:0]s_axi_arlen; + input aresetn; + input [2:0]s_axi_arsize; + input m_axi_rvalid; + input s_axi_rready; + input m_axi_rlast; + input m_axi_arready; + input s_axi_arvalid; + input [1:0]areset_d; + input \areset_d_reg[1] ; + input [31:0]s_axi_araddr; + input [1:0]s_axi_arburst; + input [3:0]s_axi_arcache; + input [2:0]s_axi_arprot; + input [3:0]s_axi_arqos; + + wire [0:0]E; + wire M_AXI_AADDR_I1__0; + wire \S_AXI_AADDR_Q_reg_n_0_[0] ; + wire \S_AXI_AADDR_Q_reg_n_0_[10] ; + wire \S_AXI_AADDR_Q_reg_n_0_[11] ; + wire \S_AXI_AADDR_Q_reg_n_0_[12] ; + wire \S_AXI_AADDR_Q_reg_n_0_[13] ; + wire \S_AXI_AADDR_Q_reg_n_0_[14] ; + wire \S_AXI_AADDR_Q_reg_n_0_[15] ; + wire \S_AXI_AADDR_Q_reg_n_0_[16] ; + wire \S_AXI_AADDR_Q_reg_n_0_[17] ; + wire \S_AXI_AADDR_Q_reg_n_0_[18] ; + wire \S_AXI_AADDR_Q_reg_n_0_[19] ; + wire \S_AXI_AADDR_Q_reg_n_0_[1] ; + wire \S_AXI_AADDR_Q_reg_n_0_[20] ; + wire \S_AXI_AADDR_Q_reg_n_0_[21] ; + wire \S_AXI_AADDR_Q_reg_n_0_[22] ; + wire \S_AXI_AADDR_Q_reg_n_0_[23] ; + wire \S_AXI_AADDR_Q_reg_n_0_[24] ; + wire \S_AXI_AADDR_Q_reg_n_0_[25] ; + wire \S_AXI_AADDR_Q_reg_n_0_[26] ; + wire \S_AXI_AADDR_Q_reg_n_0_[27] ; + wire \S_AXI_AADDR_Q_reg_n_0_[28] ; + wire \S_AXI_AADDR_Q_reg_n_0_[29] ; + wire \S_AXI_AADDR_Q_reg_n_0_[2] ; + wire \S_AXI_AADDR_Q_reg_n_0_[30] ; + wire \S_AXI_AADDR_Q_reg_n_0_[31] ; + wire \S_AXI_AADDR_Q_reg_n_0_[3] ; + wire \S_AXI_AADDR_Q_reg_n_0_[4] ; + wire \S_AXI_AADDR_Q_reg_n_0_[5] ; + wire \S_AXI_AADDR_Q_reg_n_0_[6] ; + wire \S_AXI_AADDR_Q_reg_n_0_[7] ; + wire \S_AXI_AADDR_Q_reg_n_0_[8] ; + wire \S_AXI_AADDR_Q_reg_n_0_[9] ; + wire [3:0]S_AXI_ALEN_Q; + wire \S_AXI_ALOCK_Q_reg_n_0_[0] ; + wire S_AXI_AREADY_I_i_2__0_n_0; + wire \USE_R_CHANNEL.cmd_queue_n_0 ; + wire \USE_R_CHANNEL.cmd_queue_n_1 ; + wire \USE_R_CHANNEL.cmd_queue_n_13 ; + wire \USE_R_CHANNEL.cmd_queue_n_14 ; + wire \USE_R_CHANNEL.cmd_queue_n_16 ; + wire \USE_R_CHANNEL.cmd_queue_n_17 ; + wire \USE_R_CHANNEL.cmd_queue_n_18 ; + wire \USE_R_CHANNEL.cmd_queue_n_19 ; + wire \USE_R_CHANNEL.cmd_queue_n_20 ; + wire \USE_R_CHANNEL.cmd_queue_n_3 ; + wire \USE_R_CHANNEL.cmd_queue_n_4 ; + wire \USE_R_CHANNEL.cmd_queue_n_5 ; + wire \USE_R_CHANNEL.cmd_queue_n_6 ; + wire \USE_R_CHANNEL.cmd_queue_n_7 ; + wire \USE_R_CHANNEL.cmd_queue_n_8 ; + wire access_is_incr; + wire access_is_incr_q; + wire aclk; + wire \addr_step_q[10]_i_1__0_n_0 ; + wire \addr_step_q[11]_i_1__0_n_0 ; + wire \addr_step_q[5]_i_1__0_n_0 ; + wire \addr_step_q[6]_i_1__0_n_0 ; + wire \addr_step_q[7]_i_1__0_n_0 ; + wire \addr_step_q[8]_i_1__0_n_0 ; + wire \addr_step_q[9]_i_1__0_n_0 ; + wire \addr_step_q_reg_n_0_[10] ; + wire \addr_step_q_reg_n_0_[11] ; + wire \addr_step_q_reg_n_0_[5] ; + wire \addr_step_q_reg_n_0_[6] ; + wire \addr_step_q_reg_n_0_[7] ; + wire \addr_step_q_reg_n_0_[8] ; + wire \addr_step_q_reg_n_0_[9] ; + wire allow_split_cmd__1; + wire almost_empty; + wire [1:0]areset_d; + wire \areset_d_reg[1] ; + wire aresetn; + wire aresetn_0; + wire \cmd_depth[0]_i_1__0_n_0 ; + wire [5:0]cmd_depth_reg__0; + wire cmd_empty; + wire cmd_empty_i_1_n_0; + wire cmd_push_block; + wire command_ongoing; + wire first_split__2; + wire [11:4]first_step; + wire \first_step_q[0]_i_1__0_n_0 ; + wire \first_step_q[10]_i_2__0_n_0 ; + wire \first_step_q[11]_i_2__0_n_0 ; + wire \first_step_q[1]_i_1__0_n_0 ; + wire \first_step_q[2]_i_1__0_n_0 ; + wire \first_step_q[3]_i_1__0_n_0 ; + wire \first_step_q[6]_i_2__0_n_0 ; + wire \first_step_q[7]_i_2__0_n_0 ; + wire \first_step_q[8]_i_2__0_n_0 ; + wire \first_step_q[9]_i_2__0_n_0 ; + wire \first_step_q_reg_n_0_[0] ; + wire \first_step_q_reg_n_0_[10] ; + wire \first_step_q_reg_n_0_[11] ; + wire \first_step_q_reg_n_0_[1] ; + wire \first_step_q_reg_n_0_[2] ; + wire \first_step_q_reg_n_0_[3] ; + wire \first_step_q_reg_n_0_[4] ; + wire \first_step_q_reg_n_0_[5] ; + wire \first_step_q_reg_n_0_[6] ; + wire \first_step_q_reg_n_0_[7] ; + wire \first_step_q_reg_n_0_[8] ; + wire \first_step_q_reg_n_0_[9] ; + wire incr_need_to_split__0; + wire [31:0]m_axi_araddr; + wire [1:0]m_axi_arburst; + wire [3:0]m_axi_arcache; + wire \m_axi_arid[0] ; + wire [3:0]m_axi_arlen; + wire [0:0]m_axi_arlock; + wire [2:0]m_axi_arprot; + wire [3:0]m_axi_arqos; + wire m_axi_arready; + wire [2:0]m_axi_arsize; + wire m_axi_arvalid; + wire m_axi_rlast; + wire m_axi_rready; + wire m_axi_rvalid; + wire multiple_id_non_split; + wire multiple_id_non_split_i_2__0_n_0; + wire need_to_split_q; + wire [31:0]next_mi_addr; + wire \next_mi_addr[11]_i_2_n_0 ; + wire \next_mi_addr[11]_i_3_n_0 ; + wire \next_mi_addr[11]_i_4_n_0 ; + wire \next_mi_addr[11]_i_5_n_0 ; + wire \next_mi_addr[15]_i_2__0_n_0 ; + wire \next_mi_addr[15]_i_3__0_n_0 ; + wire \next_mi_addr[15]_i_4__0_n_0 ; + wire \next_mi_addr[15]_i_5__0_n_0 ; + wire \next_mi_addr[15]_i_6__0_n_0 ; + wire \next_mi_addr[15]_i_7__0_n_0 ; + wire \next_mi_addr[15]_i_8__0_n_0 ; + wire \next_mi_addr[15]_i_9__0_n_0 ; + wire \next_mi_addr[19]_i_2__0_n_0 ; + wire \next_mi_addr[19]_i_3__0_n_0 ; + wire \next_mi_addr[19]_i_4__0_n_0 ; + wire \next_mi_addr[19]_i_5__0_n_0 ; + wire \next_mi_addr[23]_i_2__0_n_0 ; + wire \next_mi_addr[23]_i_3__0_n_0 ; + wire \next_mi_addr[23]_i_4__0_n_0 ; + wire \next_mi_addr[23]_i_5__0_n_0 ; + wire \next_mi_addr[27]_i_2__0_n_0 ; + wire \next_mi_addr[27]_i_3__0_n_0 ; + wire \next_mi_addr[27]_i_4__0_n_0 ; + wire \next_mi_addr[27]_i_5__0_n_0 ; + wire \next_mi_addr[31]_i_2__0_n_0 ; + wire \next_mi_addr[31]_i_3__0_n_0 ; + wire \next_mi_addr[31]_i_4__0_n_0 ; + wire \next_mi_addr[31]_i_5__0_n_0 ; + wire \next_mi_addr[3]_i_2__0_n_0 ; + wire \next_mi_addr[3]_i_3__0_n_0 ; + wire \next_mi_addr[3]_i_4__0_n_0 ; + wire \next_mi_addr[3]_i_5__0_n_0 ; + wire \next_mi_addr[7]_i_2_n_0 ; + wire \next_mi_addr[7]_i_3_n_0 ; + wire \next_mi_addr[7]_i_4_n_0 ; + wire \next_mi_addr[7]_i_5_n_0 ; + wire \next_mi_addr_reg[11]_i_1__0_n_0 ; + wire \next_mi_addr_reg[11]_i_1__0_n_1 ; + wire \next_mi_addr_reg[11]_i_1__0_n_2 ; + wire \next_mi_addr_reg[11]_i_1__0_n_3 ; + wire \next_mi_addr_reg[11]_i_1__0_n_4 ; + wire \next_mi_addr_reg[11]_i_1__0_n_5 ; + wire \next_mi_addr_reg[11]_i_1__0_n_6 ; + wire \next_mi_addr_reg[11]_i_1__0_n_7 ; + wire \next_mi_addr_reg[15]_i_1__0_n_0 ; + wire \next_mi_addr_reg[15]_i_1__0_n_1 ; + wire \next_mi_addr_reg[15]_i_1__0_n_2 ; + wire \next_mi_addr_reg[15]_i_1__0_n_3 ; + wire \next_mi_addr_reg[15]_i_1__0_n_4 ; + wire \next_mi_addr_reg[15]_i_1__0_n_5 ; + wire \next_mi_addr_reg[15]_i_1__0_n_6 ; + wire \next_mi_addr_reg[15]_i_1__0_n_7 ; + wire \next_mi_addr_reg[19]_i_1__0_n_0 ; + wire \next_mi_addr_reg[19]_i_1__0_n_1 ; + wire \next_mi_addr_reg[19]_i_1__0_n_2 ; + wire \next_mi_addr_reg[19]_i_1__0_n_3 ; + wire \next_mi_addr_reg[19]_i_1__0_n_4 ; + wire \next_mi_addr_reg[19]_i_1__0_n_5 ; + wire \next_mi_addr_reg[19]_i_1__0_n_6 ; + wire \next_mi_addr_reg[19]_i_1__0_n_7 ; + wire \next_mi_addr_reg[23]_i_1__0_n_0 ; + wire \next_mi_addr_reg[23]_i_1__0_n_1 ; + wire \next_mi_addr_reg[23]_i_1__0_n_2 ; + wire \next_mi_addr_reg[23]_i_1__0_n_3 ; + wire \next_mi_addr_reg[23]_i_1__0_n_4 ; + wire \next_mi_addr_reg[23]_i_1__0_n_5 ; + wire \next_mi_addr_reg[23]_i_1__0_n_6 ; + wire \next_mi_addr_reg[23]_i_1__0_n_7 ; + wire \next_mi_addr_reg[27]_i_1__0_n_0 ; + wire \next_mi_addr_reg[27]_i_1__0_n_1 ; + wire \next_mi_addr_reg[27]_i_1__0_n_2 ; + wire \next_mi_addr_reg[27]_i_1__0_n_3 ; + wire \next_mi_addr_reg[27]_i_1__0_n_4 ; + wire \next_mi_addr_reg[27]_i_1__0_n_5 ; + wire \next_mi_addr_reg[27]_i_1__0_n_6 ; + wire \next_mi_addr_reg[27]_i_1__0_n_7 ; + wire \next_mi_addr_reg[31]_i_1__0_n_1 ; + wire \next_mi_addr_reg[31]_i_1__0_n_2 ; + wire \next_mi_addr_reg[31]_i_1__0_n_3 ; + wire \next_mi_addr_reg[31]_i_1__0_n_4 ; + wire \next_mi_addr_reg[31]_i_1__0_n_5 ; + wire \next_mi_addr_reg[31]_i_1__0_n_6 ; + wire \next_mi_addr_reg[31]_i_1__0_n_7 ; + wire \next_mi_addr_reg[3]_i_1__0_n_0 ; + wire \next_mi_addr_reg[3]_i_1__0_n_1 ; + wire \next_mi_addr_reg[3]_i_1__0_n_2 ; + wire \next_mi_addr_reg[3]_i_1__0_n_3 ; + wire \next_mi_addr_reg[3]_i_1__0_n_4 ; + wire \next_mi_addr_reg[3]_i_1__0_n_5 ; + wire \next_mi_addr_reg[3]_i_1__0_n_6 ; + wire \next_mi_addr_reg[3]_i_1__0_n_7 ; + wire \next_mi_addr_reg[7]_i_1__0_n_0 ; + wire \next_mi_addr_reg[7]_i_1__0_n_1 ; + wire \next_mi_addr_reg[7]_i_1__0_n_2 ; + wire \next_mi_addr_reg[7]_i_1__0_n_3 ; + wire \next_mi_addr_reg[7]_i_1__0_n_4 ; + wire \next_mi_addr_reg[7]_i_1__0_n_5 ; + wire \next_mi_addr_reg[7]_i_1__0_n_6 ; + wire \next_mi_addr_reg[7]_i_1__0_n_7 ; + wire \num_transactions_q_reg_n_0_[0] ; + wire \num_transactions_q_reg_n_0_[1] ; + wire \num_transactions_q_reg_n_0_[2] ; + wire \num_transactions_q_reg_n_0_[3] ; + wire [3:0]p_0_in__0; + wire \pushed_commands[3]_i_1__0_n_0 ; + wire [3:0]pushed_commands_reg__0; + wire pushed_new_cmd; + wire \queue_id_reg_n_0_[0] ; + wire rd_cmd_ready; + wire [31:0]s_axi_araddr; + wire [1:0]s_axi_arburst; + wire [3:0]s_axi_arcache; + wire [0:0]s_axi_arid; + wire [7:0]s_axi_arlen; + wire [0:0]s_axi_arlock; + wire [2:0]s_axi_arprot; + wire [3:0]s_axi_arqos; + wire [2:0]s_axi_arsize; + wire s_axi_arvalid; + wire s_axi_rlast; + wire s_axi_rready; + wire s_axi_rvalid; + wire [31:0]size_mask_q; + wire \size_mask_q[0]_i_1__0_n_0 ; + wire \size_mask_q[1]_i_1__0_n_0 ; + wire \size_mask_q[2]_i_1__0_n_0 ; + wire \size_mask_q[3]_i_1__0_n_0 ; + wire \size_mask_q[4]_i_1__0_n_0 ; + wire \size_mask_q[5]_i_1__0_n_0 ; + wire \size_mask_q[6]_i_1__0_n_0 ; + wire split_in_progress_reg_n_0; + wire split_ongoing; + wire [3:3]\NLW_next_mi_addr_reg[31]_i_1__0_CO_UNCONNECTED ; + + FDRE \S_AXI_AADDR_Q_reg[0] + (.C(aclk), + .CE(E), + .D(s_axi_araddr[0]), + .Q(\S_AXI_AADDR_Q_reg_n_0_[0] ), + .R(aresetn_0)); + FDRE \S_AXI_AADDR_Q_reg[10] + (.C(aclk), + .CE(E), + .D(s_axi_araddr[10]), + .Q(\S_AXI_AADDR_Q_reg_n_0_[10] ), + .R(aresetn_0)); + FDRE \S_AXI_AADDR_Q_reg[11] + (.C(aclk), + .CE(E), + .D(s_axi_araddr[11]), + .Q(\S_AXI_AADDR_Q_reg_n_0_[11] ), + .R(aresetn_0)); + FDRE \S_AXI_AADDR_Q_reg[12] + (.C(aclk), + .CE(E), + .D(s_axi_araddr[12]), + .Q(\S_AXI_AADDR_Q_reg_n_0_[12] ), + .R(aresetn_0)); + FDRE \S_AXI_AADDR_Q_reg[13] + (.C(aclk), + .CE(E), + .D(s_axi_araddr[13]), + .Q(\S_AXI_AADDR_Q_reg_n_0_[13] ), + .R(aresetn_0)); + FDRE \S_AXI_AADDR_Q_reg[14] + (.C(aclk), + .CE(E), + .D(s_axi_araddr[14]), + .Q(\S_AXI_AADDR_Q_reg_n_0_[14] ), + .R(aresetn_0)); + FDRE \S_AXI_AADDR_Q_reg[15] + (.C(aclk), + .CE(E), + .D(s_axi_araddr[15]), + .Q(\S_AXI_AADDR_Q_reg_n_0_[15] ), + .R(aresetn_0)); + FDRE \S_AXI_AADDR_Q_reg[16] + (.C(aclk), + .CE(E), + .D(s_axi_araddr[16]), + .Q(\S_AXI_AADDR_Q_reg_n_0_[16] ), + .R(aresetn_0)); + FDRE \S_AXI_AADDR_Q_reg[17] + (.C(aclk), + .CE(E), + .D(s_axi_araddr[17]), + .Q(\S_AXI_AADDR_Q_reg_n_0_[17] ), + .R(aresetn_0)); + FDRE \S_AXI_AADDR_Q_reg[18] + (.C(aclk), + .CE(E), + .D(s_axi_araddr[18]), + .Q(\S_AXI_AADDR_Q_reg_n_0_[18] ), + .R(aresetn_0)); + FDRE \S_AXI_AADDR_Q_reg[19] + (.C(aclk), + .CE(E), + .D(s_axi_araddr[19]), + .Q(\S_AXI_AADDR_Q_reg_n_0_[19] ), + .R(aresetn_0)); + FDRE \S_AXI_AADDR_Q_reg[1] + (.C(aclk), + .CE(E), + .D(s_axi_araddr[1]), + .Q(\S_AXI_AADDR_Q_reg_n_0_[1] ), + .R(aresetn_0)); + FDRE \S_AXI_AADDR_Q_reg[20] + (.C(aclk), + .CE(E), + .D(s_axi_araddr[20]), + .Q(\S_AXI_AADDR_Q_reg_n_0_[20] ), + .R(aresetn_0)); + FDRE \S_AXI_AADDR_Q_reg[21] + (.C(aclk), + .CE(E), + .D(s_axi_araddr[21]), + .Q(\S_AXI_AADDR_Q_reg_n_0_[21] ), + .R(aresetn_0)); + FDRE \S_AXI_AADDR_Q_reg[22] + (.C(aclk), + .CE(E), + .D(s_axi_araddr[22]), + .Q(\S_AXI_AADDR_Q_reg_n_0_[22] ), + .R(aresetn_0)); + FDRE \S_AXI_AADDR_Q_reg[23] + (.C(aclk), + .CE(E), + .D(s_axi_araddr[23]), + .Q(\S_AXI_AADDR_Q_reg_n_0_[23] ), + .R(aresetn_0)); + FDRE \S_AXI_AADDR_Q_reg[24] + (.C(aclk), .CE(E), .D(s_axi_araddr[24]), - .Q(S_AXI_AADDR_Q[24]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .Q(\S_AXI_AADDR_Q_reg_n_0_[24] ), + .R(aresetn_0)); FDRE \S_AXI_AADDR_Q_reg[25] (.C(aclk), .CE(E), .D(s_axi_araddr[25]), - .Q(S_AXI_AADDR_Q[25]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .Q(\S_AXI_AADDR_Q_reg_n_0_[25] ), + .R(aresetn_0)); FDRE \S_AXI_AADDR_Q_reg[26] (.C(aclk), .CE(E), .D(s_axi_araddr[26]), - .Q(S_AXI_AADDR_Q[26]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .Q(\S_AXI_AADDR_Q_reg_n_0_[26] ), + .R(aresetn_0)); FDRE \S_AXI_AADDR_Q_reg[27] (.C(aclk), .CE(E), .D(s_axi_araddr[27]), - .Q(S_AXI_AADDR_Q[27]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .Q(\S_AXI_AADDR_Q_reg_n_0_[27] ), + .R(aresetn_0)); FDRE \S_AXI_AADDR_Q_reg[28] (.C(aclk), .CE(E), .D(s_axi_araddr[28]), - .Q(S_AXI_AADDR_Q[28]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .Q(\S_AXI_AADDR_Q_reg_n_0_[28] ), + .R(aresetn_0)); FDRE \S_AXI_AADDR_Q_reg[29] (.C(aclk), .CE(E), .D(s_axi_araddr[29]), - .Q(S_AXI_AADDR_Q[29]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .Q(\S_AXI_AADDR_Q_reg_n_0_[29] ), + .R(aresetn_0)); FDRE \S_AXI_AADDR_Q_reg[2] (.C(aclk), .CE(E), .D(s_axi_araddr[2]), - .Q(S_AXI_AADDR_Q[2]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .Q(\S_AXI_AADDR_Q_reg_n_0_[2] ), + .R(aresetn_0)); FDRE \S_AXI_AADDR_Q_reg[30] (.C(aclk), .CE(E), .D(s_axi_araddr[30]), - .Q(S_AXI_AADDR_Q[30]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .Q(\S_AXI_AADDR_Q_reg_n_0_[30] ), + .R(aresetn_0)); FDRE \S_AXI_AADDR_Q_reg[31] (.C(aclk), .CE(E), .D(s_axi_araddr[31]), - .Q(S_AXI_AADDR_Q[31]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .Q(\S_AXI_AADDR_Q_reg_n_0_[31] ), + .R(aresetn_0)); FDRE \S_AXI_AADDR_Q_reg[3] (.C(aclk), .CE(E), .D(s_axi_araddr[3]), - .Q(S_AXI_AADDR_Q[3]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .Q(\S_AXI_AADDR_Q_reg_n_0_[3] ), + .R(aresetn_0)); FDRE \S_AXI_AADDR_Q_reg[4] (.C(aclk), .CE(E), .D(s_axi_araddr[4]), - .Q(S_AXI_AADDR_Q[4]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .Q(\S_AXI_AADDR_Q_reg_n_0_[4] ), + .R(aresetn_0)); FDRE \S_AXI_AADDR_Q_reg[5] (.C(aclk), .CE(E), .D(s_axi_araddr[5]), - .Q(S_AXI_AADDR_Q[5]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .Q(\S_AXI_AADDR_Q_reg_n_0_[5] ), + .R(aresetn_0)); FDRE \S_AXI_AADDR_Q_reg[6] (.C(aclk), .CE(E), .D(s_axi_araddr[6]), - .Q(S_AXI_AADDR_Q[6]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .Q(\S_AXI_AADDR_Q_reg_n_0_[6] ), + .R(aresetn_0)); FDRE \S_AXI_AADDR_Q_reg[7] (.C(aclk), .CE(E), .D(s_axi_araddr[7]), - .Q(S_AXI_AADDR_Q[7]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .Q(\S_AXI_AADDR_Q_reg_n_0_[7] ), + .R(aresetn_0)); FDRE \S_AXI_AADDR_Q_reg[8] (.C(aclk), .CE(E), .D(s_axi_araddr[8]), - .Q(S_AXI_AADDR_Q[8]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .Q(\S_AXI_AADDR_Q_reg_n_0_[8] ), + .R(aresetn_0)); FDRE \S_AXI_AADDR_Q_reg[9] (.C(aclk), .CE(E), .D(s_axi_araddr[9]), - .Q(S_AXI_AADDR_Q[9]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .Q(\S_AXI_AADDR_Q_reg_n_0_[9] ), + .R(aresetn_0)); FDRE \S_AXI_ABURST_Q_reg[0] (.C(aclk), .CE(E), .D(s_axi_arburst[0]), .Q(m_axi_arburst[0]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \S_AXI_ABURST_Q_reg[1] (.C(aclk), .CE(E), .D(s_axi_arburst[1]), .Q(m_axi_arburst[1]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \S_AXI_ACACHE_Q_reg[0] (.C(aclk), .CE(E), .D(s_axi_arcache[0]), .Q(m_axi_arcache[0]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \S_AXI_ACACHE_Q_reg[1] (.C(aclk), .CE(E), .D(s_axi_arcache[1]), .Q(m_axi_arcache[1]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \S_AXI_ACACHE_Q_reg[2] (.C(aclk), .CE(E), .D(s_axi_arcache[2]), .Q(m_axi_arcache[2]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \S_AXI_ACACHE_Q_reg[3] (.C(aclk), .CE(E), .D(s_axi_arcache[3]), .Q(m_axi_arcache[3]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \S_AXI_AID_Q_reg[0] (.C(aclk), .CE(E), .D(s_axi_arid), - .Q(M_AXI_ARID), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .Q(\m_axi_arid[0] ), + .R(aresetn_0)); FDRE \S_AXI_ALEN_Q_reg[0] (.C(aclk), .CE(E), .D(s_axi_arlen[0]), .Q(S_AXI_ALEN_Q[0]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \S_AXI_ALEN_Q_reg[1] (.C(aclk), .CE(E), .D(s_axi_arlen[1]), .Q(S_AXI_ALEN_Q[1]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \S_AXI_ALEN_Q_reg[2] (.C(aclk), .CE(E), .D(s_axi_arlen[2]), .Q(S_AXI_ALEN_Q[2]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \S_AXI_ALEN_Q_reg[3] (.C(aclk), .CE(E), .D(s_axi_arlen[3]), .Q(S_AXI_ALEN_Q[3]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \S_AXI_ALOCK_Q_reg[0] (.C(aclk), .CE(E), .D(s_axi_arlock), .Q(\S_AXI_ALOCK_Q_reg_n_0_[0] ), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \S_AXI_APROT_Q_reg[0] (.C(aclk), .CE(E), .D(s_axi_arprot[0]), .Q(m_axi_arprot[0]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \S_AXI_APROT_Q_reg[1] (.C(aclk), .CE(E), .D(s_axi_arprot[1]), .Q(m_axi_arprot[1]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \S_AXI_APROT_Q_reg[2] (.C(aclk), .CE(E), .D(s_axi_arprot[2]), .Q(m_axi_arprot[2]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \S_AXI_AQOS_Q_reg[0] (.C(aclk), .CE(E), .D(s_axi_arqos[0]), .Q(m_axi_arqos[0]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \S_AXI_AQOS_Q_reg[1] (.C(aclk), .CE(E), .D(s_axi_arqos[1]), .Q(m_axi_arqos[1]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \S_AXI_AQOS_Q_reg[2] (.C(aclk), .CE(E), .D(s_axi_arqos[2]), .Q(m_axi_arqos[2]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \S_AXI_AQOS_Q_reg[3] (.C(aclk), .CE(E), .D(s_axi_arqos[3]), .Q(m_axi_arqos[3]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); + LUT4 #( + .INIT(16'h82FF)) + S_AXI_AREADY_I_i_2__0 + (.I0(\USE_R_CHANNEL.cmd_queue_n_8 ), + .I1(pushed_commands_reg__0[3]), + .I2(\num_transactions_q_reg_n_0_[3] ), + .I3(access_is_incr_q), + .O(S_AXI_AREADY_I_i_2__0_n_0)); FDRE S_AXI_AREADY_I_reg (.C(aclk), .CE(1'b1), .D(\USE_R_CHANNEL.cmd_queue_n_16 ), .Q(E), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \S_AXI_ASIZE_Q_reg[0] (.C(aclk), .CE(E), .D(s_axi_arsize[0]), .Q(m_axi_arsize[0]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \S_AXI_ASIZE_Q_reg[1] (.C(aclk), .CE(E), .D(s_axi_arsize[1]), .Q(m_axi_arsize[1]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \S_AXI_ASIZE_Q_reg[2] (.C(aclk), .CE(E), .D(s_axi_arsize[2]), .Q(m_axi_arsize[2]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_axic_fifo \USE_R_CHANNEL.cmd_queue - (.D({\USE_R_CHANNEL.cmd_queue_n_4 ,\USE_R_CHANNEL.cmd_queue_n_5 ,\USE_R_CHANNEL.cmd_queue_n_6 ,\USE_R_CHANNEL.cmd_queue_n_7 ,\USE_R_CHANNEL.cmd_queue_n_8 }), - .E(\USE_R_CHANNEL.cmd_queue_n_11 ), + .R(aresetn_0)); + Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_axic_fifo__parameterized0 \USE_R_CHANNEL.cmd_queue + (.D({\USE_R_CHANNEL.cmd_queue_n_3 ,\USE_R_CHANNEL.cmd_queue_n_4 ,\USE_R_CHANNEL.cmd_queue_n_5 ,\USE_R_CHANNEL.cmd_queue_n_6 ,\USE_R_CHANNEL.cmd_queue_n_7 }), + .E(pushed_new_cmd), .Q(cmd_depth_reg__0), - .SR(\USE_R_CHANNEL.cmd_queue_n_0 ), - .\S_AXI_AID_Q_reg[0] (M_AXI_ARID), - .\S_AXI_AID_Q_reg[0]_0 (multiple_id_non_split_i_2_n_0), + .\S_AXI_AID_Q_reg[0] (\m_axi_arid[0] ), .S_AXI_AREADY_I_reg(\USE_R_CHANNEL.cmd_queue_n_16 ), .S_AXI_AREADY_I_reg_0(E), .access_is_incr_q(access_is_incr_q), .aclk(aclk), + .allow_split_cmd__1(allow_split_cmd__1), .almost_empty(almost_empty), - .\areset_d_reg[1] (areset_d), - .\areset_d_reg[1]_0 (command_ongoing_i_2_n_0), + .areset_d(areset_d), + .\areset_d_reg[1] (\areset_d_reg[1] ), .aresetn(aresetn), - .\cmd_depth_reg[1] (\cmd_depth[5]_i_4_n_0 ), - .\cmd_depth_reg[3] (\cmd_depth[5]_i_3_n_0 ), + .aresetn_0(aresetn_0), + .\cmd_depth_reg[5] (\USE_R_CHANNEL.cmd_queue_n_14 ), .cmd_empty(cmd_empty), - .cmd_empty0(cmd_empty0), - .cmd_empty_reg(split_in_progress_i_2_n_0), - .cmd_push(cmd_push), .cmd_push_block(cmd_push_block), - .cmd_push_block_reg(\USE_R_CHANNEL.cmd_queue_n_17 ), + .cmd_push_block_reg(\USE_R_CHANNEL.cmd_queue_n_13 ), .command_ongoing(command_ongoing), - .command_ongoing_reg(\USE_R_CHANNEL.cmd_queue_n_19 ), - .din(\USE_R_CHANNEL.cmd_queue_n_1 ), + .command_ongoing_reg(\USE_R_CHANNEL.cmd_queue_n_18 ), + .din(\USE_R_CHANNEL.cmd_queue_n_0 ), .m_axi_arready(m_axi_arready), .m_axi_arvalid(m_axi_arvalid), .m_axi_rlast(m_axi_rlast), .m_axi_rready(m_axi_rready), .m_axi_rvalid(m_axi_rvalid), .multiple_id_non_split(multiple_id_non_split), - .multiple_id_non_split_reg(\USE_R_CHANNEL.cmd_queue_n_20 ), + .multiple_id_non_split_reg(\USE_R_CHANNEL.cmd_queue_n_19 ), .need_to_split_q(need_to_split_q), - .num_transactions_q(num_transactions_q), + .\num_transactions_q_reg[0] (\num_transactions_q_reg_n_0_[0] ), + .\num_transactions_q_reg[1] (\num_transactions_q_reg_n_0_[1] ), + .\num_transactions_q_reg[2] (\num_transactions_q_reg_n_0_[2] ), + .\num_transactions_q_reg[3] (\num_transactions_q_reg_n_0_[3] ), .\pushed_commands_reg[3] (pushed_commands_reg__0), - .pushed_new_cmd(pushed_new_cmd), - .queue_id(queue_id), - .\queue_id_reg[0] (\USE_R_CHANNEL.cmd_queue_n_18 ), + .\pushed_commands_reg[3]_0 (S_AXI_AREADY_I_i_2__0_n_0), + .\queue_id_reg[0] (\USE_R_CHANNEL.cmd_queue_n_17 ), + .\queue_id_reg[0]_0 (\queue_id_reg_n_0_[0] ), .rd_cmd_ready(rd_cmd_ready), .s_axi_arvalid(s_axi_arvalid), .s_axi_rlast(s_axi_rlast), .s_axi_rready(s_axi_rready), .s_axi_rvalid(s_axi_rvalid), - .split_in_progress_reg(\USE_R_CHANNEL.cmd_queue_n_21 ), - .split_in_progress_reg_0(split_in_progress_reg_n_0)); + .split_in_progress_reg(\USE_R_CHANNEL.cmd_queue_n_1 ), + .split_in_progress_reg_0(\USE_R_CHANNEL.cmd_queue_n_20 ), + .split_in_progress_reg_1(split_in_progress_reg_n_0), + .split_in_progress_reg_2(multiple_id_non_split_i_2__0_n_0), + .split_ongoing_reg(\USE_R_CHANNEL.cmd_queue_n_8 )); LUT2 #( .INIT(4'h2)) - access_is_incr_q_i_1 + access_is_incr_q_i_1__0 (.I0(s_axi_arburst[0]), .I1(s_axi_arburst[1]), .O(access_is_incr)); @@ -2039,448 +6625,413 @@ module Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_a_axi3_conv .CE(E), .D(access_is_incr), .Q(access_is_incr_q), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair18" *) + .R(aresetn_0)); + (* SOFT_HLUTNM = "soft_lutpair15" *) LUT3 #( .INIT(8'h08)) - \addr_step_q[10]_i_1 + \addr_step_q[10]_i_1__0 (.I0(s_axi_arsize[1]), .I1(s_axi_arsize[2]), .I2(s_axi_arsize[0]), - .O(addr_step[10])); - (* SOFT_HLUTNM = "soft_lutpair15" *) + .O(\addr_step_q[10]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair14" *) LUT3 #( .INIT(8'h80)) - \addr_step_q[11]_i_1 + \addr_step_q[11]_i_1__0 (.I0(s_axi_arsize[1]), .I1(s_axi_arsize[0]), .I2(s_axi_arsize[2]), - .O(addr_step[11])); - (* SOFT_HLUTNM = "soft_lutpair21" *) + .O(\addr_step_q[11]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair19" *) LUT3 #( .INIT(8'h04)) - \addr_step_q[5]_i_1 + \addr_step_q[5]_i_1__0 (.I0(s_axi_arsize[2]), .I1(s_axi_arsize[0]), .I2(s_axi_arsize[1]), - .O(addr_step[5])); - (* SOFT_HLUTNM = "soft_lutpair15" *) + .O(\addr_step_q[5]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair18" *) LUT3 #( .INIT(8'h04)) - \addr_step_q[6]_i_1 + \addr_step_q[6]_i_1__0 (.I0(s_axi_arsize[0]), .I1(s_axi_arsize[1]), .I2(s_axi_arsize[2]), - .O(addr_step[6])); - (* SOFT_HLUTNM = "soft_lutpair21" *) + .O(\addr_step_q[6]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair19" *) LUT3 #( .INIT(8'h08)) - \addr_step_q[7]_i_1 + \addr_step_q[7]_i_1__0 (.I0(s_axi_arsize[1]), .I1(s_axi_arsize[0]), .I2(s_axi_arsize[2]), - .O(addr_step[7])); - (* SOFT_HLUTNM = "soft_lutpair17" *) + .O(\addr_step_q[7]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair14" *) LUT3 #( .INIT(8'h04)) - \addr_step_q[8]_i_1 + \addr_step_q[8]_i_1__0 (.I0(s_axi_arsize[0]), .I1(s_axi_arsize[2]), .I2(s_axi_arsize[1]), - .O(addr_step[8])); - (* SOFT_HLUTNM = "soft_lutpair13" *) + .O(\addr_step_q[8]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair12" *) LUT3 #( .INIT(8'h08)) - \addr_step_q[9]_i_1 + \addr_step_q[9]_i_1__0 (.I0(s_axi_arsize[2]), .I1(s_axi_arsize[0]), .I2(s_axi_arsize[1]), - .O(addr_step[9])); + .O(\addr_step_q[9]_i_1__0_n_0 )); FDRE \addr_step_q_reg[10] (.C(aclk), .CE(E), - .D(addr_step[10]), - .Q(addr_step_q[10]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .D(\addr_step_q[10]_i_1__0_n_0 ), + .Q(\addr_step_q_reg_n_0_[10] ), + .R(aresetn_0)); FDRE \addr_step_q_reg[11] (.C(aclk), .CE(E), - .D(addr_step[11]), - .Q(addr_step_q[11]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .D(\addr_step_q[11]_i_1__0_n_0 ), + .Q(\addr_step_q_reg_n_0_[11] ), + .R(aresetn_0)); FDRE \addr_step_q_reg[5] (.C(aclk), .CE(E), - .D(addr_step[5]), - .Q(addr_step_q[5]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .D(\addr_step_q[5]_i_1__0_n_0 ), + .Q(\addr_step_q_reg_n_0_[5] ), + .R(aresetn_0)); FDRE \addr_step_q_reg[6] (.C(aclk), .CE(E), - .D(addr_step[6]), - .Q(addr_step_q[6]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .D(\addr_step_q[6]_i_1__0_n_0 ), + .Q(\addr_step_q_reg_n_0_[6] ), + .R(aresetn_0)); FDRE \addr_step_q_reg[7] (.C(aclk), .CE(E), - .D(addr_step[7]), - .Q(addr_step_q[7]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .D(\addr_step_q[7]_i_1__0_n_0 ), + .Q(\addr_step_q_reg_n_0_[7] ), + .R(aresetn_0)); FDRE \addr_step_q_reg[8] (.C(aclk), .CE(E), - .D(addr_step[8]), - .Q(addr_step_q[8]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .D(\addr_step_q[8]_i_1__0_n_0 ), + .Q(\addr_step_q_reg_n_0_[8] ), + .R(aresetn_0)); FDRE \addr_step_q_reg[9] (.C(aclk), .CE(E), - .D(addr_step[9]), - .Q(addr_step_q[9]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \areset_d_reg[0] - (.C(aclk), - .CE(1'b1), - .D(\USE_R_CHANNEL.cmd_queue_n_0 ), - .Q(areset_d[0]), - .R(1'b0)); - FDRE \areset_d_reg[1] - (.C(aclk), - .CE(1'b1), - .D(areset_d[0]), - .Q(areset_d[1]), - .R(1'b0)); + .D(\addr_step_q[9]_i_1__0_n_0 ), + .Q(\addr_step_q_reg_n_0_[9] ), + .R(aresetn_0)); LUT1 #( .INIT(2'h1)) - \cmd_depth[0]_i_1 + \cmd_depth[0]_i_1__0 (.I0(cmd_depth_reg__0[0]), - .O(\cmd_depth[0]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair19" *) - LUT3 #( - .INIT(8'h01)) - \cmd_depth[5]_i_3 - (.I0(cmd_depth_reg__0[3]), - .I1(cmd_depth_reg__0[1]), - .I2(cmd_depth_reg__0[2]), - .O(\cmd_depth[5]_i_3_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair19" *) - LUT3 #( - .INIT(8'h7F)) - \cmd_depth[5]_i_4 - (.I0(cmd_depth_reg__0[1]), - .I1(cmd_depth_reg__0[2]), - .I2(cmd_depth_reg__0[3]), - .O(\cmd_depth[5]_i_4_n_0 )); + .O(\cmd_depth[0]_i_1__0_n_0 )); FDRE \cmd_depth_reg[0] (.C(aclk), - .CE(\USE_R_CHANNEL.cmd_queue_n_11 ), - .D(\cmd_depth[0]_i_1_n_0 ), + .CE(\USE_R_CHANNEL.cmd_queue_n_14 ), + .D(\cmd_depth[0]_i_1__0_n_0 ), .Q(cmd_depth_reg__0[0]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \cmd_depth_reg[1] (.C(aclk), - .CE(\USE_R_CHANNEL.cmd_queue_n_11 ), - .D(\USE_R_CHANNEL.cmd_queue_n_8 ), + .CE(\USE_R_CHANNEL.cmd_queue_n_14 ), + .D(\USE_R_CHANNEL.cmd_queue_n_7 ), .Q(cmd_depth_reg__0[1]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \cmd_depth_reg[2] (.C(aclk), - .CE(\USE_R_CHANNEL.cmd_queue_n_11 ), - .D(\USE_R_CHANNEL.cmd_queue_n_7 ), + .CE(\USE_R_CHANNEL.cmd_queue_n_14 ), + .D(\USE_R_CHANNEL.cmd_queue_n_6 ), .Q(cmd_depth_reg__0[2]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \cmd_depth_reg[3] (.C(aclk), - .CE(\USE_R_CHANNEL.cmd_queue_n_11 ), - .D(\USE_R_CHANNEL.cmd_queue_n_6 ), + .CE(\USE_R_CHANNEL.cmd_queue_n_14 ), + .D(\USE_R_CHANNEL.cmd_queue_n_5 ), .Q(cmd_depth_reg__0[3]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \cmd_depth_reg[4] (.C(aclk), - .CE(\USE_R_CHANNEL.cmd_queue_n_11 ), - .D(\USE_R_CHANNEL.cmd_queue_n_5 ), + .CE(\USE_R_CHANNEL.cmd_queue_n_14 ), + .D(\USE_R_CHANNEL.cmd_queue_n_4 ), .Q(cmd_depth_reg__0[4]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \cmd_depth_reg[5] (.C(aclk), - .CE(\USE_R_CHANNEL.cmd_queue_n_11 ), - .D(\USE_R_CHANNEL.cmd_queue_n_4 ), + .CE(\USE_R_CHANNEL.cmd_queue_n_14 ), + .D(\USE_R_CHANNEL.cmd_queue_n_3 ), .Q(cmd_depth_reg__0[5]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - LUT5 #( - .INIT(32'h00EF0020)) + .R(aresetn_0)); + LUT4 #( + .INIT(16'hCB08)) cmd_empty_i_1 (.I0(almost_empty), - .I1(cmd_push), - .I2(rd_cmd_ready), - .I3(cmd_empty0), - .I4(cmd_empty), + .I1(rd_cmd_ready), + .I2(\USE_R_CHANNEL.cmd_queue_n_1 ), + .I3(cmd_empty), .O(cmd_empty_i_1_n_0)); LUT6 #( .INIT(64'h0000000000000100)) - cmd_empty_i_2 - (.I0(cmd_depth_reg__0[2]), - .I1(cmd_depth_reg__0[1]), - .I2(cmd_depth_reg__0[3]), + cmd_empty_i_2__0 + (.I0(cmd_depth_reg__0[4]), + .I1(cmd_depth_reg__0[3]), + .I2(cmd_depth_reg__0[5]), .I3(cmd_depth_reg__0[0]), - .I4(cmd_depth_reg__0[5]), - .I5(cmd_depth_reg__0[4]), + .I4(cmd_depth_reg__0[1]), + .I5(cmd_depth_reg__0[2]), .O(almost_empty)); FDSE cmd_empty_reg (.C(aclk), .CE(1'b1), .D(cmd_empty_i_1_n_0), .Q(cmd_empty), - .S(\USE_R_CHANNEL.cmd_queue_n_0 )); + .S(aresetn_0)); FDRE cmd_push_block_reg (.C(aclk), .CE(1'b1), - .D(\USE_R_CHANNEL.cmd_queue_n_17 ), + .D(\USE_R_CHANNEL.cmd_queue_n_13 ), .Q(cmd_push_block), .R(1'b0)); - LUT2 #( - .INIT(4'h2)) - command_ongoing_i_2 - (.I0(areset_d[1]), - .I1(areset_d[0]), - .O(command_ongoing_i_2_n_0)); FDRE command_ongoing_reg (.C(aclk), .CE(1'b1), - .D(\USE_R_CHANNEL.cmd_queue_n_19 ), + .D(\USE_R_CHANNEL.cmd_queue_n_18 ), .Q(command_ongoing), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); (* SOFT_HLUTNM = "soft_lutpair11" *) LUT4 #( .INIT(16'h0001)) - \first_step_q[0]_i_1 + \first_step_q[0]_i_1__0 (.I0(s_axi_arsize[1]), .I1(s_axi_arsize[0]), .I2(s_axi_arlen[0]), .I3(s_axi_arsize[2]), - .O(\first_step_q[0]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair22" *) + .O(\first_step_q[0]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair21" *) LUT2 #( .INIT(4'h8)) - \first_step_q[10]_i_1 + \first_step_q[10]_i_1__0 (.I0(s_axi_arsize[2]), - .I1(\first_step_q[10]_i_2_n_0 ), + .I1(\first_step_q[10]_i_2__0_n_0 ), .O(first_step[10])); LUT6 #( .INIT(64'h2AAA800080000000)) - \first_step_q[10]_i_2 + \first_step_q[10]_i_2__0 (.I0(s_axi_arsize[1]), .I1(s_axi_arlen[2]), .I2(s_axi_arlen[0]), .I3(s_axi_arlen[1]), .I4(s_axi_arlen[3]), .I5(s_axi_arsize[0]), - .O(\first_step_q[10]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair26" *) + .O(\first_step_q[10]_i_2__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair23" *) LUT2 #( .INIT(4'h8)) - \first_step_q[11]_i_1 + \first_step_q[11]_i_1__0 (.I0(s_axi_arsize[2]), - .I1(\first_step_q[11]_i_2_n_0 ), + .I1(\first_step_q[11]_i_2__0_n_0 ), .O(first_step[11])); LUT6 #( .INIT(64'h8000000000000000)) - \first_step_q[11]_i_2 + \first_step_q[11]_i_2__0 (.I0(s_axi_arsize[1]), .I1(s_axi_arlen[3]), .I2(s_axi_arlen[1]), .I3(s_axi_arlen[0]), .I4(s_axi_arlen[2]), .I5(s_axi_arsize[0]), - .O(\first_step_q[11]_i_2_n_0 )); + .O(\first_step_q[11]_i_2__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair11" *) LUT5 #( .INIT(32'h00000514)) - \first_step_q[1]_i_1 + \first_step_q[1]_i_1__0 (.I0(s_axi_arsize[1]), .I1(s_axi_arsize[0]), .I2(s_axi_arlen[0]), .I3(s_axi_arlen[1]), .I4(s_axi_arsize[2]), - .O(\first_step_q[1]_i_1_n_0 )); + .O(\first_step_q[1]_i_1__0_n_0 )); LUT6 #( .INIT(64'h00000000000F3C6A)) - \first_step_q[2]_i_1 + \first_step_q[2]_i_1__0 (.I0(s_axi_arlen[2]), .I1(s_axi_arlen[1]), .I2(s_axi_arlen[0]), .I3(s_axi_arsize[0]), .I4(s_axi_arsize[1]), .I5(s_axi_arsize[2]), - .O(\first_step_q[2]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair23" *) + .O(\first_step_q[2]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair16" *) LUT2 #( .INIT(4'h2)) - \first_step_q[3]_i_1 - (.I0(\first_step_q[7]_i_2_n_0 ), + \first_step_q[3]_i_1__0 + (.I0(\first_step_q[7]_i_2__0_n_0 ), .I1(s_axi_arsize[2]), - .O(\first_step_q[3]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair13" *) + .O(\first_step_q[3]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair12" *) LUT5 #( .INIT(32'h01FF0100)) - \first_step_q[4]_i_1 + \first_step_q[4]_i_1__0 (.I0(s_axi_arlen[0]), .I1(s_axi_arsize[0]), .I2(s_axi_arsize[1]), .I3(s_axi_arsize[2]), - .I4(\first_step_q[8]_i_2_n_0 ), + .I4(\first_step_q[8]_i_2__0_n_0 ), .O(first_step[4])); LUT6 #( .INIT(64'h0036FFFF00360000)) - \first_step_q[5]_i_1 + \first_step_q[5]_i_1__0 (.I0(s_axi_arlen[1]), .I1(s_axi_arlen[0]), .I2(s_axi_arsize[0]), .I3(s_axi_arsize[1]), .I4(s_axi_arsize[2]), - .I5(\first_step_q[9]_i_2_n_0 ), + .I5(\first_step_q[9]_i_2__0_n_0 ), .O(first_step[5])); - (* SOFT_HLUTNM = "soft_lutpair22" *) + (* SOFT_HLUTNM = "soft_lutpair21" *) LUT3 #( .INIT(8'hB8)) - \first_step_q[6]_i_1 - (.I0(\first_step_q[6]_i_2_n_0 ), + \first_step_q[6]_i_1__0 + (.I0(\first_step_q[6]_i_2__0_n_0 ), .I1(s_axi_arsize[2]), - .I2(\first_step_q[10]_i_2_n_0 ), + .I2(\first_step_q[10]_i_2__0_n_0 ), .O(first_step[6])); LUT5 #( .INIT(32'h07531642)) - \first_step_q[6]_i_2 + \first_step_q[6]_i_2__0 (.I0(s_axi_arsize[1]), .I1(s_axi_arsize[0]), .I2(s_axi_arlen[0]), .I3(s_axi_arlen[1]), .I4(s_axi_arlen[2]), - .O(\first_step_q[6]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair23" *) + .O(\first_step_q[6]_i_2__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair16" *) LUT3 #( .INIT(8'hB8)) - \first_step_q[7]_i_1 - (.I0(\first_step_q[7]_i_2_n_0 ), + \first_step_q[7]_i_1__0 + (.I0(\first_step_q[7]_i_2__0_n_0 ), .I1(s_axi_arsize[2]), - .I2(\first_step_q[11]_i_2_n_0 ), + .I2(\first_step_q[11]_i_2__0_n_0 ), .O(first_step[7])); LUT6 #( .INIT(64'h07FD53B916EC42A8)) - \first_step_q[7]_i_2 + \first_step_q[7]_i_2__0 (.I0(s_axi_arsize[1]), .I1(s_axi_arsize[0]), .I2(s_axi_arlen[1]), .I3(s_axi_arlen[0]), .I4(s_axi_arlen[2]), .I5(s_axi_arlen[3]), - .O(\first_step_q[7]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair25" *) + .O(\first_step_q[7]_i_2__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair24" *) LUT2 #( .INIT(4'h8)) - \first_step_q[8]_i_1 + \first_step_q[8]_i_1__0 (.I0(s_axi_arsize[2]), - .I1(\first_step_q[8]_i_2_n_0 ), + .I1(\first_step_q[8]_i_2__0_n_0 ), .O(first_step[8])); LUT6 #( .INIT(64'h14EAEA6262C8C840)) - \first_step_q[8]_i_2 + \first_step_q[8]_i_2__0 (.I0(s_axi_arsize[1]), .I1(s_axi_arsize[0]), .I2(s_axi_arlen[3]), .I3(s_axi_arlen[1]), .I4(s_axi_arlen[0]), .I5(s_axi_arlen[2]), - .O(\first_step_q[8]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair26" *) + .O(\first_step_q[8]_i_2__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair24" *) LUT2 #( .INIT(4'h8)) - \first_step_q[9]_i_1 + \first_step_q[9]_i_1__0 (.I0(s_axi_arsize[2]), - .I1(\first_step_q[9]_i_2_n_0 ), + .I1(\first_step_q[9]_i_2__0_n_0 ), .O(first_step[9])); LUT6 #( .INIT(64'h4AA2A2A228808080)) - \first_step_q[9]_i_2 + \first_step_q[9]_i_2__0 (.I0(s_axi_arsize[1]), .I1(s_axi_arsize[0]), .I2(s_axi_arlen[2]), .I3(s_axi_arlen[0]), .I4(s_axi_arlen[1]), .I5(s_axi_arlen[3]), - .O(\first_step_q[9]_i_2_n_0 )); + .O(\first_step_q[9]_i_2__0_n_0 )); FDRE \first_step_q_reg[0] (.C(aclk), .CE(E), - .D(\first_step_q[0]_i_1_n_0 ), - .Q(first_step_q[0]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .D(\first_step_q[0]_i_1__0_n_0 ), + .Q(\first_step_q_reg_n_0_[0] ), + .R(aresetn_0)); FDRE \first_step_q_reg[10] (.C(aclk), .CE(E), .D(first_step[10]), - .Q(first_step_q[10]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .Q(\first_step_q_reg_n_0_[10] ), + .R(aresetn_0)); FDRE \first_step_q_reg[11] (.C(aclk), .CE(E), .D(first_step[11]), - .Q(first_step_q[11]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .Q(\first_step_q_reg_n_0_[11] ), + .R(aresetn_0)); FDRE \first_step_q_reg[1] (.C(aclk), .CE(E), - .D(\first_step_q[1]_i_1_n_0 ), - .Q(first_step_q[1]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .D(\first_step_q[1]_i_1__0_n_0 ), + .Q(\first_step_q_reg_n_0_[1] ), + .R(aresetn_0)); FDRE \first_step_q_reg[2] (.C(aclk), .CE(E), - .D(\first_step_q[2]_i_1_n_0 ), - .Q(first_step_q[2]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .D(\first_step_q[2]_i_1__0_n_0 ), + .Q(\first_step_q_reg_n_0_[2] ), + .R(aresetn_0)); FDRE \first_step_q_reg[3] (.C(aclk), .CE(E), - .D(\first_step_q[3]_i_1_n_0 ), - .Q(first_step_q[3]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .D(\first_step_q[3]_i_1__0_n_0 ), + .Q(\first_step_q_reg_n_0_[3] ), + .R(aresetn_0)); FDRE \first_step_q_reg[4] (.C(aclk), .CE(E), .D(first_step[4]), - .Q(first_step_q[4]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .Q(\first_step_q_reg_n_0_[4] ), + .R(aresetn_0)); FDRE \first_step_q_reg[5] (.C(aclk), .CE(E), .D(first_step[5]), - .Q(first_step_q[5]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .Q(\first_step_q_reg_n_0_[5] ), + .R(aresetn_0)); FDRE \first_step_q_reg[6] (.C(aclk), .CE(E), .D(first_step[6]), - .Q(first_step_q[6]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .Q(\first_step_q_reg_n_0_[6] ), + .R(aresetn_0)); FDRE \first_step_q_reg[7] (.C(aclk), .CE(E), .D(first_step[7]), - .Q(first_step_q[7]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .Q(\first_step_q_reg_n_0_[7] ), + .R(aresetn_0)); FDRE \first_step_q_reg[8] (.C(aclk), .CE(E), .D(first_step[8]), - .Q(first_step_q[8]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .Q(\first_step_q_reg_n_0_[8] ), + .R(aresetn_0)); FDRE \first_step_q_reg[9] (.C(aclk), .CE(E), .D(first_step[9]), - .Q(first_step_q[9]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .Q(\first_step_q_reg_n_0_[9] ), + .R(aresetn_0)); LUT6 #( .INIT(64'h4444444444444440)) incr_need_to_split @@ -2496,335 +7047,335 @@ module Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_a_axi3_conv .CE(E), .D(incr_need_to_split__0), .Q(need_to_split_q), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); LUT5 #( - .INIT(32'h8FFF8000)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[0]_INST_0 - (.I0(size_mask_q[0]), - .I1(next_mi_addr[0]), - .I2(access_is_incr_q), + (.I0(next_mi_addr[0]), + .I1(size_mask_q[0]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[0] ), .I3(split_ongoing), - .I4(S_AXI_AADDR_Q[0]), + .I4(access_is_incr_q), .O(m_axi_araddr[0])); LUT5 #( - .INIT(32'hCAAA0AAA)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[10]_INST_0 - (.I0(S_AXI_AADDR_Q[10]), + (.I0(next_mi_addr[10]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[10]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[10] ), + .I3(split_ongoing), + .I4(access_is_incr_q), .O(m_axi_araddr[10])); LUT5 #( - .INIT(32'hCAAA0AAA)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[11]_INST_0 - (.I0(S_AXI_AADDR_Q[11]), + (.I0(next_mi_addr[11]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[11]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[11] ), + .I3(split_ongoing), + .I4(access_is_incr_q), .O(m_axi_araddr[11])); LUT5 #( - .INIT(32'hCAAA0AAA)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[12]_INST_0 - (.I0(S_AXI_AADDR_Q[12]), + (.I0(next_mi_addr[12]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[12]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[12] ), + .I3(split_ongoing), + .I4(access_is_incr_q), .O(m_axi_araddr[12])); LUT5 #( - .INIT(32'hCAAA0AAA)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[13]_INST_0 - (.I0(S_AXI_AADDR_Q[13]), + (.I0(next_mi_addr[13]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[13]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[13] ), + .I3(split_ongoing), + .I4(access_is_incr_q), .O(m_axi_araddr[13])); LUT5 #( - .INIT(32'hCAAA0AAA)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[14]_INST_0 - (.I0(S_AXI_AADDR_Q[14]), + (.I0(next_mi_addr[14]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[14]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[14] ), + .I3(split_ongoing), + .I4(access_is_incr_q), .O(m_axi_araddr[14])); LUT5 #( - .INIT(32'hCAAA0AAA)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[15]_INST_0 - (.I0(S_AXI_AADDR_Q[15]), + (.I0(next_mi_addr[15]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[15]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[15] ), + .I3(split_ongoing), + .I4(access_is_incr_q), .O(m_axi_araddr[15])); LUT5 #( - .INIT(32'hCAAA0AAA)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[16]_INST_0 - (.I0(S_AXI_AADDR_Q[16]), + (.I0(next_mi_addr[16]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[16]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[16] ), + .I3(split_ongoing), + .I4(access_is_incr_q), .O(m_axi_araddr[16])); LUT5 #( - .INIT(32'hCAAA0AAA)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[17]_INST_0 - (.I0(S_AXI_AADDR_Q[17]), + (.I0(next_mi_addr[17]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[17]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[17] ), + .I3(split_ongoing), + .I4(access_is_incr_q), .O(m_axi_araddr[17])); LUT5 #( - .INIT(32'hCAAA0AAA)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[18]_INST_0 - (.I0(S_AXI_AADDR_Q[18]), + (.I0(next_mi_addr[18]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[18]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[18] ), + .I3(split_ongoing), + .I4(access_is_incr_q), .O(m_axi_araddr[18])); LUT5 #( - .INIT(32'hCAAA0AAA)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[19]_INST_0 - (.I0(S_AXI_AADDR_Q[19]), + (.I0(next_mi_addr[19]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[19]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[19] ), + .I3(split_ongoing), + .I4(access_is_incr_q), .O(m_axi_araddr[19])); LUT5 #( - .INIT(32'h8FFF8000)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[1]_INST_0 - (.I0(size_mask_q[1]), - .I1(next_mi_addr[1]), - .I2(access_is_incr_q), + (.I0(next_mi_addr[1]), + .I1(size_mask_q[1]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[1] ), .I3(split_ongoing), - .I4(S_AXI_AADDR_Q[1]), + .I4(access_is_incr_q), .O(m_axi_araddr[1])); LUT5 #( - .INIT(32'hCAAA0AAA)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[20]_INST_0 - (.I0(S_AXI_AADDR_Q[20]), + (.I0(next_mi_addr[20]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[20]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[20] ), + .I3(split_ongoing), + .I4(access_is_incr_q), .O(m_axi_araddr[20])); LUT5 #( - .INIT(32'hCAAA0AAA)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[21]_INST_0 - (.I0(S_AXI_AADDR_Q[21]), + (.I0(next_mi_addr[21]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[21]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[21] ), + .I3(split_ongoing), + .I4(access_is_incr_q), .O(m_axi_araddr[21])); LUT5 #( - .INIT(32'hCAAA0AAA)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[22]_INST_0 - (.I0(S_AXI_AADDR_Q[22]), + (.I0(next_mi_addr[22]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[22]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[22] ), + .I3(split_ongoing), + .I4(access_is_incr_q), .O(m_axi_araddr[22])); LUT5 #( - .INIT(32'hCAAA0AAA)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[23]_INST_0 - (.I0(S_AXI_AADDR_Q[23]), + (.I0(next_mi_addr[23]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[23]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[23] ), + .I3(split_ongoing), + .I4(access_is_incr_q), .O(m_axi_araddr[23])); LUT5 #( - .INIT(32'hCAAA0AAA)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[24]_INST_0 - (.I0(S_AXI_AADDR_Q[24]), + (.I0(next_mi_addr[24]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[24]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[24] ), + .I3(split_ongoing), + .I4(access_is_incr_q), .O(m_axi_araddr[24])); - (* SOFT_HLUTNM = "soft_lutpair12" *) LUT5 #( - .INIT(32'hCAAA0AAA)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[25]_INST_0 - (.I0(S_AXI_AADDR_Q[25]), + (.I0(next_mi_addr[25]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[25]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[25] ), + .I3(split_ongoing), + .I4(access_is_incr_q), .O(m_axi_araddr[25])); + (* SOFT_HLUTNM = "soft_lutpair10" *) LUT5 #( - .INIT(32'hCAAA0AAA)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[26]_INST_0 - (.I0(S_AXI_AADDR_Q[26]), + (.I0(next_mi_addr[26]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[26]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[26] ), + .I3(split_ongoing), + .I4(access_is_incr_q), .O(m_axi_araddr[26])); LUT5 #( - .INIT(32'hCAAA0AAA)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[27]_INST_0 - (.I0(S_AXI_AADDR_Q[27]), + (.I0(next_mi_addr[27]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[27]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[27] ), + .I3(split_ongoing), + .I4(access_is_incr_q), .O(m_axi_araddr[27])); LUT5 #( - .INIT(32'hCAAA0AAA)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[28]_INST_0 - (.I0(S_AXI_AADDR_Q[28]), + (.I0(next_mi_addr[28]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[28]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[28] ), + .I3(split_ongoing), + .I4(access_is_incr_q), .O(m_axi_araddr[28])); LUT5 #( - .INIT(32'hCAAA0AAA)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[29]_INST_0 - (.I0(S_AXI_AADDR_Q[29]), + (.I0(next_mi_addr[29]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[29]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[29] ), + .I3(split_ongoing), + .I4(access_is_incr_q), .O(m_axi_araddr[29])); LUT5 #( - .INIT(32'h8FFF8000)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[2]_INST_0 - (.I0(size_mask_q[2]), - .I1(next_mi_addr[2]), - .I2(access_is_incr_q), + (.I0(next_mi_addr[2]), + .I1(size_mask_q[2]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[2] ), .I3(split_ongoing), - .I4(S_AXI_AADDR_Q[2]), + .I4(access_is_incr_q), .O(m_axi_araddr[2])); LUT5 #( - .INIT(32'hCAAA0AAA)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[30]_INST_0 - (.I0(S_AXI_AADDR_Q[30]), + (.I0(next_mi_addr[30]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[30]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[30] ), + .I3(split_ongoing), + .I4(access_is_incr_q), .O(m_axi_araddr[30])); LUT5 #( - .INIT(32'hCAAA0AAA)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[31]_INST_0 - (.I0(S_AXI_AADDR_Q[31]), + (.I0(next_mi_addr[31]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[31]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[31] ), + .I3(split_ongoing), + .I4(access_is_incr_q), .O(m_axi_araddr[31])); LUT5 #( - .INIT(32'h8FFF8000)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[3]_INST_0 - (.I0(size_mask_q[3]), - .I1(next_mi_addr[3]), - .I2(access_is_incr_q), + (.I0(next_mi_addr[3]), + .I1(size_mask_q[3]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[3] ), .I3(split_ongoing), - .I4(S_AXI_AADDR_Q[3]), + .I4(access_is_incr_q), .O(m_axi_araddr[3])); LUT5 #( - .INIT(32'h8FFF8000)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[4]_INST_0 - (.I0(size_mask_q[4]), - .I1(next_mi_addr[4]), - .I2(access_is_incr_q), + (.I0(next_mi_addr[4]), + .I1(size_mask_q[4]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[4] ), .I3(split_ongoing), - .I4(S_AXI_AADDR_Q[4]), + .I4(access_is_incr_q), .O(m_axi_araddr[4])); LUT5 #( - .INIT(32'h8FFF8000)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[5]_INST_0 - (.I0(size_mask_q[5]), - .I1(next_mi_addr[5]), - .I2(access_is_incr_q), + (.I0(next_mi_addr[5]), + .I1(size_mask_q[5]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[5] ), .I3(split_ongoing), - .I4(S_AXI_AADDR_Q[5]), + .I4(access_is_incr_q), .O(m_axi_araddr[5])); LUT5 #( - .INIT(32'h8FFF8000)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[6]_INST_0 - (.I0(size_mask_q[6]), - .I1(next_mi_addr[6]), - .I2(access_is_incr_q), + (.I0(next_mi_addr[6]), + .I1(size_mask_q[6]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[6] ), .I3(split_ongoing), - .I4(S_AXI_AADDR_Q[6]), + .I4(access_is_incr_q), .O(m_axi_araddr[6])); LUT5 #( - .INIT(32'hCAAA0AAA)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[7]_INST_0 - (.I0(S_AXI_AADDR_Q[7]), + (.I0(next_mi_addr[7]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[7]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[7] ), + .I3(split_ongoing), + .I4(access_is_incr_q), .O(m_axi_araddr[7])); LUT5 #( - .INIT(32'hCAAA0AAA)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[8]_INST_0 - (.I0(S_AXI_AADDR_Q[8]), + (.I0(next_mi_addr[8]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[8]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[8] ), + .I3(split_ongoing), + .I4(access_is_incr_q), .O(m_axi_araddr[8])); LUT5 #( - .INIT(32'hCAAA0AAA)) + .INIT(32'h88F0F0F0)) \m_axi_araddr[9]_INST_0 - (.I0(S_AXI_AADDR_Q[9]), + (.I0(next_mi_addr[9]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[9]), + .I2(\S_AXI_AADDR_Q_reg_n_0_[9] ), + .I3(split_ongoing), + .I4(access_is_incr_q), .O(m_axi_araddr[9])); LUT6 #( - .INIT(64'hFFFFFFFEAAAAAAAA)) + .INIT(64'hEEEEEEEEEEEEEEEA)) \m_axi_arlen[0]_INST_0 (.I0(S_AXI_ALEN_Q[0]), - .I1(pushed_commands_reg__0[0]), - .I2(pushed_commands_reg__0[1]), + .I1(need_to_split_q), + .I2(pushed_commands_reg__0[2]), .I3(pushed_commands_reg__0[3]), - .I4(pushed_commands_reg__0[2]), - .I5(need_to_split_q), + .I4(pushed_commands_reg__0[1]), + .I5(pushed_commands_reg__0[0]), .O(m_axi_arlen[0])); LUT6 #( - .INIT(64'hFFFFFFFEAAAAAAAA)) + .INIT(64'hEEEEEEEEEEEEEEEA)) \m_axi_arlen[1]_INST_0 (.I0(S_AXI_ALEN_Q[1]), - .I1(pushed_commands_reg__0[0]), - .I2(pushed_commands_reg__0[1]), + .I1(need_to_split_q), + .I2(pushed_commands_reg__0[2]), .I3(pushed_commands_reg__0[3]), - .I4(pushed_commands_reg__0[2]), - .I5(need_to_split_q), + .I4(pushed_commands_reg__0[1]), + .I5(pushed_commands_reg__0[0]), .O(m_axi_arlen[1])); LUT6 #( - .INIT(64'hFFFFFFFEAAAAAAAA)) + .INIT(64'hEEEEEEEEEEEEEEEA)) \m_axi_arlen[2]_INST_0 (.I0(S_AXI_ALEN_Q[2]), - .I1(pushed_commands_reg__0[0]), - .I2(pushed_commands_reg__0[1]), + .I1(need_to_split_q), + .I2(pushed_commands_reg__0[2]), .I3(pushed_commands_reg__0[3]), - .I4(pushed_commands_reg__0[2]), - .I5(need_to_split_q), + .I4(pushed_commands_reg__0[1]), + .I5(pushed_commands_reg__0[0]), .O(m_axi_arlen[2])); LUT6 #( - .INIT(64'hFFFFFFFEAAAAAAAA)) + .INIT(64'hEEEEEEEEEEEEEEEA)) \m_axi_arlen[3]_INST_0 (.I0(S_AXI_ALEN_Q[3]), - .I1(pushed_commands_reg__0[0]), - .I2(pushed_commands_reg__0[1]), + .I1(need_to_split_q), + .I2(pushed_commands_reg__0[2]), .I3(pushed_commands_reg__0[3]), - .I4(pushed_commands_reg__0[2]), - .I5(need_to_split_q), + .I4(pushed_commands_reg__0[1]), + .I5(pushed_commands_reg__0[0]), .O(m_axi_arlen[3])); LUT2 #( .INIT(4'h2)) @@ -2832,955 +7383,3831 @@ module Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_a_axi3_conv (.I0(\S_AXI_ALOCK_Q_reg_n_0_[0] ), .I1(need_to_split_q), .O(m_axi_arlock)); - (* SOFT_HLUTNM = "soft_lutpair10" *) LUT5 #( - .INIT(32'h00006606)) - multiple_id_non_split_i_2 - (.I0(M_AXI_ARID), - .I1(queue_id), - .I2(split_in_progress_reg_n_0), + .INIT(32'h0000FFD7)) + multiple_id_non_split_i_2__0 + (.I0(split_in_progress_reg_n_0), + .I1(\queue_id_reg_n_0_[0] ), + .I2(\m_axi_arid[0] ), .I3(cmd_empty), .I4(need_to_split_q), - .O(multiple_id_non_split_i_2_n_0)); + .O(multiple_id_non_split_i_2__0_n_0)); FDRE multiple_id_non_split_reg (.C(aclk), .CE(1'b1), - .D(\USE_R_CHANNEL.cmd_queue_n_20 ), + .D(\USE_R_CHANNEL.cmd_queue_n_19 ), .Q(multiple_id_non_split), .R(1'b0)); LUT4 #( - .INIT(16'h56A6)) + .INIT(16'h569A)) \next_mi_addr[11]_i_2 (.I0(m_axi_araddr[11]), - .I1(addr_step_q[11]), - .I2(\next_mi_addr[11]_i_6_n_0 ), - .I3(first_step_q[11]), + .I1(first_split__2), + .I2(\addr_step_q_reg_n_0_[11] ), + .I3(\first_step_q_reg_n_0_[11] ), .O(\next_mi_addr[11]_i_2_n_0 )); LUT4 #( - .INIT(16'h56A6)) + .INIT(16'h569A)) \next_mi_addr[11]_i_3 (.I0(m_axi_araddr[10]), - .I1(addr_step_q[10]), - .I2(\next_mi_addr[11]_i_6_n_0 ), - .I3(first_step_q[10]), + .I1(first_split__2), + .I2(\addr_step_q_reg_n_0_[10] ), + .I3(\first_step_q_reg_n_0_[10] ), .O(\next_mi_addr[11]_i_3_n_0 )); LUT4 #( - .INIT(16'h56A6)) + .INIT(16'h569A)) \next_mi_addr[11]_i_4 (.I0(m_axi_araddr[9]), - .I1(addr_step_q[9]), - .I2(\next_mi_addr[11]_i_6_n_0 ), - .I3(first_step_q[9]), + .I1(first_split__2), + .I2(\addr_step_q_reg_n_0_[9] ), + .I3(\first_step_q_reg_n_0_[9] ), .O(\next_mi_addr[11]_i_4_n_0 )); LUT4 #( - .INIT(16'h56A6)) + .INIT(16'h569A)) \next_mi_addr[11]_i_5 (.I0(m_axi_araddr[8]), - .I1(addr_step_q[8]), - .I2(\next_mi_addr[11]_i_6_n_0 ), - .I3(first_step_q[8]), + .I1(first_split__2), + .I2(\addr_step_q_reg_n_0_[8] ), + .I3(\first_step_q_reg_n_0_[8] ), .O(\next_mi_addr[11]_i_5_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair14" *) + (* SOFT_HLUTNM = "soft_lutpair13" *) LUT4 #( .INIT(16'h0001)) - \next_mi_addr[11]_i_6 - (.I0(pushed_commands_reg__0[0]), - .I1(pushed_commands_reg__0[1]), - .I2(pushed_commands_reg__0[3]), - .I3(pushed_commands_reg__0[2]), - .O(\next_mi_addr[11]_i_6_n_0 )); + \next_mi_addr[11]_i_6__0 + (.I0(pushed_commands_reg__0[2]), + .I1(pushed_commands_reg__0[3]), + .I2(pushed_commands_reg__0[1]), + .I3(pushed_commands_reg__0[0]), + .O(first_split__2)); LUT5 #( - .INIT(32'hCAAA0AAA)) - \next_mi_addr[15]_i_2 - (.I0(S_AXI_AADDR_Q[15]), + .INIT(32'h88F0F0F0)) + \next_mi_addr[15]_i_2__0 + (.I0(next_mi_addr[15]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[15]), - .O(\next_mi_addr[15]_i_2_n_0 )); + .I2(\S_AXI_AADDR_Q_reg_n_0_[15] ), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[15]_i_2__0_n_0 )); LUT5 #( - .INIT(32'hCAAA0AAA)) - \next_mi_addr[15]_i_3 - (.I0(S_AXI_AADDR_Q[14]), + .INIT(32'h88F0F0F0)) + \next_mi_addr[15]_i_3__0 + (.I0(next_mi_addr[14]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[14]), - .O(\next_mi_addr[15]_i_3_n_0 )); + .I2(\S_AXI_AADDR_Q_reg_n_0_[14] ), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[15]_i_3__0_n_0 )); LUT5 #( - .INIT(32'hCAAA0AAA)) - \next_mi_addr[15]_i_4 - (.I0(S_AXI_AADDR_Q[13]), + .INIT(32'h88F0F0F0)) + \next_mi_addr[15]_i_4__0 + (.I0(next_mi_addr[13]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[13]), - .O(\next_mi_addr[15]_i_4_n_0 )); + .I2(\S_AXI_AADDR_Q_reg_n_0_[13] ), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[15]_i_4__0_n_0 )); LUT5 #( - .INIT(32'hCAAA0AAA)) - \next_mi_addr[15]_i_5 - (.I0(S_AXI_AADDR_Q[12]), + .INIT(32'h88F0F0F0)) + \next_mi_addr[15]_i_5__0 + (.I0(next_mi_addr[12]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[12]), - .O(\next_mi_addr[15]_i_5_n_0 )); + .I2(\S_AXI_AADDR_Q_reg_n_0_[12] ), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[15]_i_5__0_n_0 )); LUT5 #( - .INIT(32'hCAAA0AAA)) - \next_mi_addr[15]_i_6 - (.I0(S_AXI_AADDR_Q[15]), + .INIT(32'h88F0F0F0)) + \next_mi_addr[15]_i_6__0 + (.I0(next_mi_addr[15]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[15]), - .O(\next_mi_addr[15]_i_6_n_0 )); + .I2(\S_AXI_AADDR_Q_reg_n_0_[15] ), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[15]_i_6__0_n_0 )); LUT5 #( - .INIT(32'hCAAA0AAA)) - \next_mi_addr[15]_i_7 - (.I0(S_AXI_AADDR_Q[14]), + .INIT(32'h88F0F0F0)) + \next_mi_addr[15]_i_7__0 + (.I0(next_mi_addr[14]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[14]), - .O(\next_mi_addr[15]_i_7_n_0 )); + .I2(\S_AXI_AADDR_Q_reg_n_0_[14] ), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[15]_i_7__0_n_0 )); LUT5 #( - .INIT(32'hCAAA0AAA)) - \next_mi_addr[15]_i_8 - (.I0(S_AXI_AADDR_Q[13]), + .INIT(32'h88F0F0F0)) + \next_mi_addr[15]_i_8__0 + (.I0(next_mi_addr[13]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[13]), - .O(\next_mi_addr[15]_i_8_n_0 )); + .I2(\S_AXI_AADDR_Q_reg_n_0_[13] ), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[15]_i_8__0_n_0 )); LUT5 #( - .INIT(32'hCAAA0AAA)) - \next_mi_addr[15]_i_9 - (.I0(S_AXI_AADDR_Q[12]), + .INIT(32'h88F0F0F0)) + \next_mi_addr[15]_i_9__0 + (.I0(next_mi_addr[12]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[12]), - .O(\next_mi_addr[15]_i_9_n_0 )); + .I2(\S_AXI_AADDR_Q_reg_n_0_[12] ), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[15]_i_9__0_n_0 )); LUT5 #( - .INIT(32'hCAAA0AAA)) - \next_mi_addr[19]_i_2 - (.I0(S_AXI_AADDR_Q[19]), + .INIT(32'h88F0F0F0)) + \next_mi_addr[19]_i_2__0 + (.I0(next_mi_addr[19]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[19]), - .O(\next_mi_addr[19]_i_2_n_0 )); + .I2(\S_AXI_AADDR_Q_reg_n_0_[19] ), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[19]_i_2__0_n_0 )); LUT5 #( - .INIT(32'hCAAA0AAA)) - \next_mi_addr[19]_i_3 - (.I0(S_AXI_AADDR_Q[18]), + .INIT(32'h88F0F0F0)) + \next_mi_addr[19]_i_3__0 + (.I0(next_mi_addr[18]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[18]), - .O(\next_mi_addr[19]_i_3_n_0 )); + .I2(\S_AXI_AADDR_Q_reg_n_0_[18] ), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[19]_i_3__0_n_0 )); LUT5 #( - .INIT(32'hCAAA0AAA)) - \next_mi_addr[19]_i_4 - (.I0(S_AXI_AADDR_Q[17]), + .INIT(32'h88F0F0F0)) + \next_mi_addr[19]_i_4__0 + (.I0(next_mi_addr[17]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[17]), - .O(\next_mi_addr[19]_i_4_n_0 )); + .I2(\S_AXI_AADDR_Q_reg_n_0_[17] ), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[19]_i_4__0_n_0 )); LUT5 #( - .INIT(32'hCAAA0AAA)) - \next_mi_addr[19]_i_5 - (.I0(S_AXI_AADDR_Q[16]), + .INIT(32'h88F0F0F0)) + \next_mi_addr[19]_i_5__0 + (.I0(next_mi_addr[16]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[16]), - .O(\next_mi_addr[19]_i_5_n_0 )); + .I2(\S_AXI_AADDR_Q_reg_n_0_[16] ), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[19]_i_5__0_n_0 )); LUT5 #( - .INIT(32'hCAAA0AAA)) - \next_mi_addr[23]_i_2 - (.I0(S_AXI_AADDR_Q[23]), + .INIT(32'h88F0F0F0)) + \next_mi_addr[23]_i_2__0 + (.I0(next_mi_addr[23]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[23]), - .O(\next_mi_addr[23]_i_2_n_0 )); + .I2(\S_AXI_AADDR_Q_reg_n_0_[23] ), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[23]_i_2__0_n_0 )); LUT5 #( - .INIT(32'hCAAA0AAA)) - \next_mi_addr[23]_i_3 - (.I0(S_AXI_AADDR_Q[22]), + .INIT(32'h88F0F0F0)) + \next_mi_addr[23]_i_3__0 + (.I0(next_mi_addr[22]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[22]), - .O(\next_mi_addr[23]_i_3_n_0 )); + .I2(\S_AXI_AADDR_Q_reg_n_0_[22] ), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[23]_i_3__0_n_0 )); LUT5 #( - .INIT(32'hCAAA0AAA)) - \next_mi_addr[23]_i_4 - (.I0(S_AXI_AADDR_Q[21]), + .INIT(32'h88F0F0F0)) + \next_mi_addr[23]_i_4__0 + (.I0(next_mi_addr[21]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[21]), - .O(\next_mi_addr[23]_i_4_n_0 )); + .I2(\S_AXI_AADDR_Q_reg_n_0_[21] ), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[23]_i_4__0_n_0 )); LUT5 #( - .INIT(32'hCAAA0AAA)) - \next_mi_addr[23]_i_5 - (.I0(S_AXI_AADDR_Q[20]), + .INIT(32'h88F0F0F0)) + \next_mi_addr[23]_i_5__0 + (.I0(next_mi_addr[20]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[20]), - .O(\next_mi_addr[23]_i_5_n_0 )); + .I2(\S_AXI_AADDR_Q_reg_n_0_[20] ), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[23]_i_5__0_n_0 )); LUT5 #( - .INIT(32'hCAAA0AAA)) - \next_mi_addr[27]_i_2 - (.I0(S_AXI_AADDR_Q[27]), + .INIT(32'h88F0F0F0)) + \next_mi_addr[27]_i_2__0 + (.I0(next_mi_addr[27]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[27]), - .O(\next_mi_addr[27]_i_2_n_0 )); + .I2(\S_AXI_AADDR_Q_reg_n_0_[27] ), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[27]_i_2__0_n_0 )); LUT5 #( - .INIT(32'hCAAA0AAA)) - \next_mi_addr[27]_i_3 - (.I0(S_AXI_AADDR_Q[26]), + .INIT(32'h88F0F0F0)) + \next_mi_addr[27]_i_3__0 + (.I0(next_mi_addr[26]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[26]), - .O(\next_mi_addr[27]_i_3_n_0 )); + .I2(\S_AXI_AADDR_Q_reg_n_0_[26] ), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[27]_i_3__0_n_0 )); LUT5 #( - .INIT(32'hCAAA0AAA)) - \next_mi_addr[27]_i_4 - (.I0(S_AXI_AADDR_Q[25]), + .INIT(32'h88F0F0F0)) + \next_mi_addr[27]_i_4__0 + (.I0(next_mi_addr[25]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[25]), - .O(\next_mi_addr[27]_i_4_n_0 )); + .I2(\S_AXI_AADDR_Q_reg_n_0_[25] ), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[27]_i_4__0_n_0 )); LUT5 #( - .INIT(32'hCAAA0AAA)) - \next_mi_addr[27]_i_5 - (.I0(S_AXI_AADDR_Q[24]), + .INIT(32'h88F0F0F0)) + \next_mi_addr[27]_i_5__0 + (.I0(next_mi_addr[24]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[24]), - .O(\next_mi_addr[27]_i_5_n_0 )); + .I2(\S_AXI_AADDR_Q_reg_n_0_[24] ), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[27]_i_5__0_n_0 )); LUT5 #( - .INIT(32'hCAAA0AAA)) - \next_mi_addr[31]_i_2 - (.I0(S_AXI_AADDR_Q[31]), + .INIT(32'h88F0F0F0)) + \next_mi_addr[31]_i_2__0 + (.I0(next_mi_addr[31]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[31]), - .O(\next_mi_addr[31]_i_2_n_0 )); + .I2(\S_AXI_AADDR_Q_reg_n_0_[31] ), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[31]_i_2__0_n_0 )); LUT5 #( - .INIT(32'hCAAA0AAA)) - \next_mi_addr[31]_i_3 - (.I0(S_AXI_AADDR_Q[30]), + .INIT(32'h88F0F0F0)) + \next_mi_addr[31]_i_3__0 + (.I0(next_mi_addr[30]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[30]), - .O(\next_mi_addr[31]_i_3_n_0 )); + .I2(\S_AXI_AADDR_Q_reg_n_0_[30] ), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[31]_i_3__0_n_0 )); LUT5 #( - .INIT(32'hCAAA0AAA)) - \next_mi_addr[31]_i_4 - (.I0(S_AXI_AADDR_Q[29]), + .INIT(32'h88F0F0F0)) + \next_mi_addr[31]_i_4__0 + (.I0(next_mi_addr[29]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[29]), - .O(\next_mi_addr[31]_i_4_n_0 )); + .I2(\S_AXI_AADDR_Q_reg_n_0_[29] ), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[31]_i_4__0_n_0 )); LUT5 #( - .INIT(32'hCAAA0AAA)) - \next_mi_addr[31]_i_5 - (.I0(S_AXI_AADDR_Q[28]), + .INIT(32'h88F0F0F0)) + \next_mi_addr[31]_i_5__0 + (.I0(next_mi_addr[28]), .I1(size_mask_q[31]), - .I2(split_ongoing), - .I3(access_is_incr_q), - .I4(next_mi_addr[28]), - .O(\next_mi_addr[31]_i_5_n_0 )); + .I2(\S_AXI_AADDR_Q_reg_n_0_[28] ), + .I3(split_ongoing), + .I4(access_is_incr_q), + .O(\next_mi_addr[31]_i_5__0_n_0 )); LUT6 #( - .INIT(64'h1DDDE222E222E222)) - \next_mi_addr[3]_i_2 - (.I0(S_AXI_AADDR_Q[3]), - .I1(\next_mi_addr[3]_i_6_n_0 ), - .I2(next_mi_addr[3]), - .I3(size_mask_q[3]), - .I4(\next_mi_addr[11]_i_6_n_0 ), - .I5(first_step_q[3]), - .O(\next_mi_addr[3]_i_2_n_0 )); + .INIT(64'h1BBBE444E444E444)) + \next_mi_addr[3]_i_2__0 + (.I0(M_AXI_AADDR_I1__0), + .I1(\S_AXI_AADDR_Q_reg_n_0_[3] ), + .I2(size_mask_q[3]), + .I3(next_mi_addr[3]), + .I4(first_split__2), + .I5(\first_step_q_reg_n_0_[3] ), + .O(\next_mi_addr[3]_i_2__0_n_0 )); LUT6 #( - .INIT(64'h1DDDE222E222E222)) - \next_mi_addr[3]_i_3 - (.I0(S_AXI_AADDR_Q[2]), - .I1(\next_mi_addr[3]_i_6_n_0 ), - .I2(next_mi_addr[2]), - .I3(size_mask_q[2]), - .I4(\next_mi_addr[11]_i_6_n_0 ), - .I5(first_step_q[2]), - .O(\next_mi_addr[3]_i_3_n_0 )); + .INIT(64'h1BBBE444E444E444)) + \next_mi_addr[3]_i_3__0 + (.I0(M_AXI_AADDR_I1__0), + .I1(\S_AXI_AADDR_Q_reg_n_0_[2] ), + .I2(size_mask_q[2]), + .I3(next_mi_addr[2]), + .I4(first_split__2), + .I5(\first_step_q_reg_n_0_[2] ), + .O(\next_mi_addr[3]_i_3__0_n_0 )); LUT6 #( - .INIT(64'h1DDDE222E222E222)) - \next_mi_addr[3]_i_4 - (.I0(S_AXI_AADDR_Q[1]), - .I1(\next_mi_addr[3]_i_6_n_0 ), - .I2(next_mi_addr[1]), - .I3(size_mask_q[1]), - .I4(\next_mi_addr[11]_i_6_n_0 ), - .I5(first_step_q[1]), - .O(\next_mi_addr[3]_i_4_n_0 )); + .INIT(64'h1BBBE444E444E444)) + \next_mi_addr[3]_i_4__0 + (.I0(M_AXI_AADDR_I1__0), + .I1(\S_AXI_AADDR_Q_reg_n_0_[1] ), + .I2(size_mask_q[1]), + .I3(next_mi_addr[1]), + .I4(first_split__2), + .I5(\first_step_q_reg_n_0_[1] ), + .O(\next_mi_addr[3]_i_4__0_n_0 )); LUT6 #( - .INIT(64'h1DDDE222E222E222)) - \next_mi_addr[3]_i_5 - (.I0(S_AXI_AADDR_Q[0]), - .I1(\next_mi_addr[3]_i_6_n_0 ), - .I2(next_mi_addr[0]), - .I3(size_mask_q[0]), - .I4(\next_mi_addr[11]_i_6_n_0 ), - .I5(first_step_q[0]), - .O(\next_mi_addr[3]_i_5_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair12" *) + .INIT(64'h1BBBE444E444E444)) + \next_mi_addr[3]_i_5__0 + (.I0(M_AXI_AADDR_I1__0), + .I1(\S_AXI_AADDR_Q_reg_n_0_[0] ), + .I2(size_mask_q[0]), + .I3(next_mi_addr[0]), + .I4(first_split__2), + .I5(\first_step_q_reg_n_0_[0] ), + .O(\next_mi_addr[3]_i_5__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair10" *) LUT2 #( .INIT(4'h8)) - \next_mi_addr[3]_i_6 - (.I0(access_is_incr_q), - .I1(split_ongoing), - .O(\next_mi_addr[3]_i_6_n_0 )); + \next_mi_addr[3]_i_6__0 + (.I0(split_ongoing), + .I1(access_is_incr_q), + .O(M_AXI_AADDR_I1__0)); LUT4 #( - .INIT(16'h56A6)) + .INIT(16'h569A)) \next_mi_addr[7]_i_2 (.I0(m_axi_araddr[7]), - .I1(addr_step_q[7]), - .I2(\next_mi_addr[11]_i_6_n_0 ), - .I3(first_step_q[7]), + .I1(first_split__2), + .I2(\addr_step_q_reg_n_0_[7] ), + .I3(\first_step_q_reg_n_0_[7] ), .O(\next_mi_addr[7]_i_2_n_0 )); LUT4 #( - .INIT(16'h56A6)) + .INIT(16'h569A)) \next_mi_addr[7]_i_3 (.I0(m_axi_araddr[6]), - .I1(addr_step_q[6]), - .I2(\next_mi_addr[11]_i_6_n_0 ), - .I3(first_step_q[6]), + .I1(first_split__2), + .I2(\addr_step_q_reg_n_0_[6] ), + .I3(\first_step_q_reg_n_0_[6] ), .O(\next_mi_addr[7]_i_3_n_0 )); LUT4 #( - .INIT(16'h56A6)) + .INIT(16'h569A)) \next_mi_addr[7]_i_4 (.I0(m_axi_araddr[5]), - .I1(addr_step_q[5]), - .I2(\next_mi_addr[11]_i_6_n_0 ), - .I3(first_step_q[5]), + .I1(first_split__2), + .I2(\addr_step_q_reg_n_0_[5] ), + .I3(\first_step_q_reg_n_0_[5] ), .O(\next_mi_addr[7]_i_4_n_0 )); LUT4 #( - .INIT(16'h56A6)) + .INIT(16'h569A)) \next_mi_addr[7]_i_5 (.I0(m_axi_araddr[4]), - .I1(size_mask_q[0]), - .I2(\next_mi_addr[11]_i_6_n_0 ), - .I3(first_step_q[4]), + .I1(first_split__2), + .I2(size_mask_q[0]), + .I3(\first_step_q_reg_n_0_[4] ), .O(\next_mi_addr[7]_i_5_n_0 )); FDRE \next_mi_addr_reg[0] (.C(aclk), .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[3]_i_1_n_7 ), + .D(\next_mi_addr_reg[3]_i_1__0_n_7 ), .Q(next_mi_addr[0]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \next_mi_addr_reg[10] (.C(aclk), .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[11]_i_1_n_5 ), + .D(\next_mi_addr_reg[11]_i_1__0_n_5 ), .Q(next_mi_addr[10]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \next_mi_addr_reg[11] (.C(aclk), .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[11]_i_1_n_4 ), + .D(\next_mi_addr_reg[11]_i_1__0_n_4 ), .Q(next_mi_addr[11]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - CARRY4 \next_mi_addr_reg[11]_i_1 - (.CI(\next_mi_addr_reg[7]_i_1_n_0 ), - .CO({\next_mi_addr_reg[11]_i_1_n_0 ,\next_mi_addr_reg[11]_i_1_n_1 ,\next_mi_addr_reg[11]_i_1_n_2 ,\next_mi_addr_reg[11]_i_1_n_3 }), + .R(aresetn_0)); + CARRY4 \next_mi_addr_reg[11]_i_1__0 + (.CI(\next_mi_addr_reg[7]_i_1__0_n_0 ), + .CO({\next_mi_addr_reg[11]_i_1__0_n_0 ,\next_mi_addr_reg[11]_i_1__0_n_1 ,\next_mi_addr_reg[11]_i_1__0_n_2 ,\next_mi_addr_reg[11]_i_1__0_n_3 }), .CYINIT(1'b0), .DI(m_axi_araddr[11:8]), - .O({\next_mi_addr_reg[11]_i_1_n_4 ,\next_mi_addr_reg[11]_i_1_n_5 ,\next_mi_addr_reg[11]_i_1_n_6 ,\next_mi_addr_reg[11]_i_1_n_7 }), + .O({\next_mi_addr_reg[11]_i_1__0_n_4 ,\next_mi_addr_reg[11]_i_1__0_n_5 ,\next_mi_addr_reg[11]_i_1__0_n_6 ,\next_mi_addr_reg[11]_i_1__0_n_7 }), .S({\next_mi_addr[11]_i_2_n_0 ,\next_mi_addr[11]_i_3_n_0 ,\next_mi_addr[11]_i_4_n_0 ,\next_mi_addr[11]_i_5_n_0 })); FDRE \next_mi_addr_reg[12] (.C(aclk), .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[15]_i_1_n_7 ), + .D(\next_mi_addr_reg[15]_i_1__0_n_7 ), .Q(next_mi_addr[12]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \next_mi_addr_reg[13] (.C(aclk), .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[15]_i_1_n_6 ), + .D(\next_mi_addr_reg[15]_i_1__0_n_6 ), .Q(next_mi_addr[13]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \next_mi_addr_reg[14] (.C(aclk), .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[15]_i_1_n_5 ), + .D(\next_mi_addr_reg[15]_i_1__0_n_5 ), .Q(next_mi_addr[14]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \next_mi_addr_reg[15] (.C(aclk), .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[15]_i_1_n_4 ), + .D(\next_mi_addr_reg[15]_i_1__0_n_4 ), .Q(next_mi_addr[15]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - CARRY4 \next_mi_addr_reg[15]_i_1 - (.CI(\next_mi_addr_reg[11]_i_1_n_0 ), - .CO({\next_mi_addr_reg[15]_i_1_n_0 ,\next_mi_addr_reg[15]_i_1_n_1 ,\next_mi_addr_reg[15]_i_1_n_2 ,\next_mi_addr_reg[15]_i_1_n_3 }), + .R(aresetn_0)); + CARRY4 \next_mi_addr_reg[15]_i_1__0 + (.CI(\next_mi_addr_reg[11]_i_1__0_n_0 ), + .CO({\next_mi_addr_reg[15]_i_1__0_n_0 ,\next_mi_addr_reg[15]_i_1__0_n_1 ,\next_mi_addr_reg[15]_i_1__0_n_2 ,\next_mi_addr_reg[15]_i_1__0_n_3 }), .CYINIT(1'b0), - .DI({\next_mi_addr[15]_i_2_n_0 ,\next_mi_addr[15]_i_3_n_0 ,\next_mi_addr[15]_i_4_n_0 ,\next_mi_addr[15]_i_5_n_0 }), - .O({\next_mi_addr_reg[15]_i_1_n_4 ,\next_mi_addr_reg[15]_i_1_n_5 ,\next_mi_addr_reg[15]_i_1_n_6 ,\next_mi_addr_reg[15]_i_1_n_7 }), - .S({\next_mi_addr[15]_i_6_n_0 ,\next_mi_addr[15]_i_7_n_0 ,\next_mi_addr[15]_i_8_n_0 ,\next_mi_addr[15]_i_9_n_0 })); + .DI({\next_mi_addr[15]_i_2__0_n_0 ,\next_mi_addr[15]_i_3__0_n_0 ,\next_mi_addr[15]_i_4__0_n_0 ,\next_mi_addr[15]_i_5__0_n_0 }), + .O({\next_mi_addr_reg[15]_i_1__0_n_4 ,\next_mi_addr_reg[15]_i_1__0_n_5 ,\next_mi_addr_reg[15]_i_1__0_n_6 ,\next_mi_addr_reg[15]_i_1__0_n_7 }), + .S({\next_mi_addr[15]_i_6__0_n_0 ,\next_mi_addr[15]_i_7__0_n_0 ,\next_mi_addr[15]_i_8__0_n_0 ,\next_mi_addr[15]_i_9__0_n_0 })); FDRE \next_mi_addr_reg[16] (.C(aclk), .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[19]_i_1_n_7 ), + .D(\next_mi_addr_reg[19]_i_1__0_n_7 ), .Q(next_mi_addr[16]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \next_mi_addr_reg[17] (.C(aclk), .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[19]_i_1_n_6 ), + .D(\next_mi_addr_reg[19]_i_1__0_n_6 ), .Q(next_mi_addr[17]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \next_mi_addr_reg[18] (.C(aclk), .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[19]_i_1_n_5 ), + .D(\next_mi_addr_reg[19]_i_1__0_n_5 ), .Q(next_mi_addr[18]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \next_mi_addr_reg[19] (.C(aclk), .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[19]_i_1_n_4 ), + .D(\next_mi_addr_reg[19]_i_1__0_n_4 ), .Q(next_mi_addr[19]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - CARRY4 \next_mi_addr_reg[19]_i_1 - (.CI(\next_mi_addr_reg[15]_i_1_n_0 ), - .CO({\next_mi_addr_reg[19]_i_1_n_0 ,\next_mi_addr_reg[19]_i_1_n_1 ,\next_mi_addr_reg[19]_i_1_n_2 ,\next_mi_addr_reg[19]_i_1_n_3 }), + .R(aresetn_0)); + CARRY4 \next_mi_addr_reg[19]_i_1__0 + (.CI(\next_mi_addr_reg[15]_i_1__0_n_0 ), + .CO({\next_mi_addr_reg[19]_i_1__0_n_0 ,\next_mi_addr_reg[19]_i_1__0_n_1 ,\next_mi_addr_reg[19]_i_1__0_n_2 ,\next_mi_addr_reg[19]_i_1__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), - .O({\next_mi_addr_reg[19]_i_1_n_4 ,\next_mi_addr_reg[19]_i_1_n_5 ,\next_mi_addr_reg[19]_i_1_n_6 ,\next_mi_addr_reg[19]_i_1_n_7 }), - .S({\next_mi_addr[19]_i_2_n_0 ,\next_mi_addr[19]_i_3_n_0 ,\next_mi_addr[19]_i_4_n_0 ,\next_mi_addr[19]_i_5_n_0 })); + .O({\next_mi_addr_reg[19]_i_1__0_n_4 ,\next_mi_addr_reg[19]_i_1__0_n_5 ,\next_mi_addr_reg[19]_i_1__0_n_6 ,\next_mi_addr_reg[19]_i_1__0_n_7 }), + .S({\next_mi_addr[19]_i_2__0_n_0 ,\next_mi_addr[19]_i_3__0_n_0 ,\next_mi_addr[19]_i_4__0_n_0 ,\next_mi_addr[19]_i_5__0_n_0 })); FDRE \next_mi_addr_reg[1] (.C(aclk), .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[3]_i_1_n_6 ), + .D(\next_mi_addr_reg[3]_i_1__0_n_6 ), .Q(next_mi_addr[1]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \next_mi_addr_reg[20] (.C(aclk), .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[23]_i_1_n_7 ), + .D(\next_mi_addr_reg[23]_i_1__0_n_7 ), .Q(next_mi_addr[20]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \next_mi_addr_reg[21] (.C(aclk), .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[23]_i_1_n_6 ), + .D(\next_mi_addr_reg[23]_i_1__0_n_6 ), .Q(next_mi_addr[21]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \next_mi_addr_reg[22] (.C(aclk), .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[23]_i_1_n_5 ), + .D(\next_mi_addr_reg[23]_i_1__0_n_5 ), .Q(next_mi_addr[22]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \next_mi_addr_reg[23] (.C(aclk), .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[23]_i_1_n_4 ), + .D(\next_mi_addr_reg[23]_i_1__0_n_4 ), .Q(next_mi_addr[23]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - CARRY4 \next_mi_addr_reg[23]_i_1 - (.CI(\next_mi_addr_reg[19]_i_1_n_0 ), - .CO({\next_mi_addr_reg[23]_i_1_n_0 ,\next_mi_addr_reg[23]_i_1_n_1 ,\next_mi_addr_reg[23]_i_1_n_2 ,\next_mi_addr_reg[23]_i_1_n_3 }), + .R(aresetn_0)); + CARRY4 \next_mi_addr_reg[23]_i_1__0 + (.CI(\next_mi_addr_reg[19]_i_1__0_n_0 ), + .CO({\next_mi_addr_reg[23]_i_1__0_n_0 ,\next_mi_addr_reg[23]_i_1__0_n_1 ,\next_mi_addr_reg[23]_i_1__0_n_2 ,\next_mi_addr_reg[23]_i_1__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), - .O({\next_mi_addr_reg[23]_i_1_n_4 ,\next_mi_addr_reg[23]_i_1_n_5 ,\next_mi_addr_reg[23]_i_1_n_6 ,\next_mi_addr_reg[23]_i_1_n_7 }), - .S({\next_mi_addr[23]_i_2_n_0 ,\next_mi_addr[23]_i_3_n_0 ,\next_mi_addr[23]_i_4_n_0 ,\next_mi_addr[23]_i_5_n_0 })); + .O({\next_mi_addr_reg[23]_i_1__0_n_4 ,\next_mi_addr_reg[23]_i_1__0_n_5 ,\next_mi_addr_reg[23]_i_1__0_n_6 ,\next_mi_addr_reg[23]_i_1__0_n_7 }), + .S({\next_mi_addr[23]_i_2__0_n_0 ,\next_mi_addr[23]_i_3__0_n_0 ,\next_mi_addr[23]_i_4__0_n_0 ,\next_mi_addr[23]_i_5__0_n_0 })); FDRE \next_mi_addr_reg[24] (.C(aclk), .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[27]_i_1_n_7 ), + .D(\next_mi_addr_reg[27]_i_1__0_n_7 ), .Q(next_mi_addr[24]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \next_mi_addr_reg[25] (.C(aclk), .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[27]_i_1_n_6 ), + .D(\next_mi_addr_reg[27]_i_1__0_n_6 ), .Q(next_mi_addr[25]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \next_mi_addr_reg[26] (.C(aclk), .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[27]_i_1_n_5 ), + .D(\next_mi_addr_reg[27]_i_1__0_n_5 ), .Q(next_mi_addr[26]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \next_mi_addr_reg[27] (.C(aclk), .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[27]_i_1_n_4 ), + .D(\next_mi_addr_reg[27]_i_1__0_n_4 ), .Q(next_mi_addr[27]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - CARRY4 \next_mi_addr_reg[27]_i_1 - (.CI(\next_mi_addr_reg[23]_i_1_n_0 ), - .CO({\next_mi_addr_reg[27]_i_1_n_0 ,\next_mi_addr_reg[27]_i_1_n_1 ,\next_mi_addr_reg[27]_i_1_n_2 ,\next_mi_addr_reg[27]_i_1_n_3 }), + .R(aresetn_0)); + CARRY4 \next_mi_addr_reg[27]_i_1__0 + (.CI(\next_mi_addr_reg[23]_i_1__0_n_0 ), + .CO({\next_mi_addr_reg[27]_i_1__0_n_0 ,\next_mi_addr_reg[27]_i_1__0_n_1 ,\next_mi_addr_reg[27]_i_1__0_n_2 ,\next_mi_addr_reg[27]_i_1__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), - .O({\next_mi_addr_reg[27]_i_1_n_4 ,\next_mi_addr_reg[27]_i_1_n_5 ,\next_mi_addr_reg[27]_i_1_n_6 ,\next_mi_addr_reg[27]_i_1_n_7 }), - .S({\next_mi_addr[27]_i_2_n_0 ,\next_mi_addr[27]_i_3_n_0 ,\next_mi_addr[27]_i_4_n_0 ,\next_mi_addr[27]_i_5_n_0 })); + .O({\next_mi_addr_reg[27]_i_1__0_n_4 ,\next_mi_addr_reg[27]_i_1__0_n_5 ,\next_mi_addr_reg[27]_i_1__0_n_6 ,\next_mi_addr_reg[27]_i_1__0_n_7 }), + .S({\next_mi_addr[27]_i_2__0_n_0 ,\next_mi_addr[27]_i_3__0_n_0 ,\next_mi_addr[27]_i_4__0_n_0 ,\next_mi_addr[27]_i_5__0_n_0 })); FDRE \next_mi_addr_reg[28] (.C(aclk), .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[31]_i_1_n_7 ), + .D(\next_mi_addr_reg[31]_i_1__0_n_7 ), .Q(next_mi_addr[28]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \next_mi_addr_reg[29] (.C(aclk), .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[31]_i_1_n_6 ), + .D(\next_mi_addr_reg[31]_i_1__0_n_6 ), .Q(next_mi_addr[29]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \next_mi_addr_reg[2] (.C(aclk), .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[3]_i_1_n_5 ), + .D(\next_mi_addr_reg[3]_i_1__0_n_5 ), .Q(next_mi_addr[2]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \next_mi_addr_reg[30] (.C(aclk), .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[31]_i_1_n_5 ), + .D(\next_mi_addr_reg[31]_i_1__0_n_5 ), .Q(next_mi_addr[30]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); + .R(aresetn_0)); FDRE \next_mi_addr_reg[31] (.C(aclk), .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[31]_i_1_n_4 ), + .D(\next_mi_addr_reg[31]_i_1__0_n_4 ), .Q(next_mi_addr[31]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - CARRY4 \next_mi_addr_reg[31]_i_1 - (.CI(\next_mi_addr_reg[27]_i_1_n_0 ), - .CO({\NLW_next_mi_addr_reg[31]_i_1_CO_UNCONNECTED [3],\next_mi_addr_reg[31]_i_1_n_1 ,\next_mi_addr_reg[31]_i_1_n_2 ,\next_mi_addr_reg[31]_i_1_n_3 }), + .R(aresetn_0)); + CARRY4 \next_mi_addr_reg[31]_i_1__0 + (.CI(\next_mi_addr_reg[27]_i_1__0_n_0 ), + .CO({\NLW_next_mi_addr_reg[31]_i_1__0_CO_UNCONNECTED [3],\next_mi_addr_reg[31]_i_1__0_n_1 ,\next_mi_addr_reg[31]_i_1__0_n_2 ,\next_mi_addr_reg[31]_i_1__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), - .O({\next_mi_addr_reg[31]_i_1_n_4 ,\next_mi_addr_reg[31]_i_1_n_5 ,\next_mi_addr_reg[31]_i_1_n_6 ,\next_mi_addr_reg[31]_i_1_n_7 }), - .S({\next_mi_addr[31]_i_2_n_0 ,\next_mi_addr[31]_i_3_n_0 ,\next_mi_addr[31]_i_4_n_0 ,\next_mi_addr[31]_i_5_n_0 })); + .O({\next_mi_addr_reg[31]_i_1__0_n_4 ,\next_mi_addr_reg[31]_i_1__0_n_5 ,\next_mi_addr_reg[31]_i_1__0_n_6 ,\next_mi_addr_reg[31]_i_1__0_n_7 }), + .S({\next_mi_addr[31]_i_2__0_n_0 ,\next_mi_addr[31]_i_3__0_n_0 ,\next_mi_addr[31]_i_4__0_n_0 ,\next_mi_addr[31]_i_5__0_n_0 })); FDRE \next_mi_addr_reg[3] (.C(aclk), .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[3]_i_1_n_4 ), + .D(\next_mi_addr_reg[3]_i_1__0_n_4 ), .Q(next_mi_addr[3]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - CARRY4 \next_mi_addr_reg[3]_i_1 + .R(aresetn_0)); + CARRY4 \next_mi_addr_reg[3]_i_1__0 (.CI(1'b0), - .CO({\next_mi_addr_reg[3]_i_1_n_0 ,\next_mi_addr_reg[3]_i_1_n_1 ,\next_mi_addr_reg[3]_i_1_n_2 ,\next_mi_addr_reg[3]_i_1_n_3 }), + .CO({\next_mi_addr_reg[3]_i_1__0_n_0 ,\next_mi_addr_reg[3]_i_1__0_n_1 ,\next_mi_addr_reg[3]_i_1__0_n_2 ,\next_mi_addr_reg[3]_i_1__0_n_3 }), .CYINIT(1'b0), .DI(m_axi_araddr[3:0]), - .O({\next_mi_addr_reg[3]_i_1_n_4 ,\next_mi_addr_reg[3]_i_1_n_5 ,\next_mi_addr_reg[3]_i_1_n_6 ,\next_mi_addr_reg[3]_i_1_n_7 }), - .S({\next_mi_addr[3]_i_2_n_0 ,\next_mi_addr[3]_i_3_n_0 ,\next_mi_addr[3]_i_4_n_0 ,\next_mi_addr[3]_i_5_n_0 })); + .O({\next_mi_addr_reg[3]_i_1__0_n_4 ,\next_mi_addr_reg[3]_i_1__0_n_5 ,\next_mi_addr_reg[3]_i_1__0_n_6 ,\next_mi_addr_reg[3]_i_1__0_n_7 }), + .S({\next_mi_addr[3]_i_2__0_n_0 ,\next_mi_addr[3]_i_3__0_n_0 ,\next_mi_addr[3]_i_4__0_n_0 ,\next_mi_addr[3]_i_5__0_n_0 })); FDRE \next_mi_addr_reg[4] (.C(aclk), - .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[7]_i_1_n_7 ), - .Q(next_mi_addr[4]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \next_mi_addr_reg[5] + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[7]_i_1__0_n_7 ), + .Q(next_mi_addr[4]), + .R(aresetn_0)); + FDRE \next_mi_addr_reg[5] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[7]_i_1__0_n_6 ), + .Q(next_mi_addr[5]), + .R(aresetn_0)); + FDRE \next_mi_addr_reg[6] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[7]_i_1__0_n_5 ), + .Q(next_mi_addr[6]), + .R(aresetn_0)); + FDRE \next_mi_addr_reg[7] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[7]_i_1__0_n_4 ), + .Q(next_mi_addr[7]), + .R(aresetn_0)); + CARRY4 \next_mi_addr_reg[7]_i_1__0 + (.CI(\next_mi_addr_reg[3]_i_1__0_n_0 ), + .CO({\next_mi_addr_reg[7]_i_1__0_n_0 ,\next_mi_addr_reg[7]_i_1__0_n_1 ,\next_mi_addr_reg[7]_i_1__0_n_2 ,\next_mi_addr_reg[7]_i_1__0_n_3 }), + .CYINIT(1'b0), + .DI(m_axi_araddr[7:4]), + .O({\next_mi_addr_reg[7]_i_1__0_n_4 ,\next_mi_addr_reg[7]_i_1__0_n_5 ,\next_mi_addr_reg[7]_i_1__0_n_6 ,\next_mi_addr_reg[7]_i_1__0_n_7 }), + .S({\next_mi_addr[7]_i_2_n_0 ,\next_mi_addr[7]_i_3_n_0 ,\next_mi_addr[7]_i_4_n_0 ,\next_mi_addr[7]_i_5_n_0 })); + FDRE \next_mi_addr_reg[8] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[11]_i_1__0_n_7 ), + .Q(next_mi_addr[8]), + .R(aresetn_0)); + FDRE \next_mi_addr_reg[9] + (.C(aclk), + .CE(pushed_new_cmd), + .D(\next_mi_addr_reg[11]_i_1__0_n_6 ), + .Q(next_mi_addr[9]), + .R(aresetn_0)); + FDRE \num_transactions_q_reg[0] + (.C(aclk), + .CE(E), + .D(s_axi_arlen[4]), + .Q(\num_transactions_q_reg_n_0_[0] ), + .R(aresetn_0)); + FDRE \num_transactions_q_reg[1] + (.C(aclk), + .CE(E), + .D(s_axi_arlen[5]), + .Q(\num_transactions_q_reg_n_0_[1] ), + .R(aresetn_0)); + FDRE \num_transactions_q_reg[2] + (.C(aclk), + .CE(E), + .D(s_axi_arlen[6]), + .Q(\num_transactions_q_reg_n_0_[2] ), + .R(aresetn_0)); + FDRE \num_transactions_q_reg[3] + (.C(aclk), + .CE(E), + .D(s_axi_arlen[7]), + .Q(\num_transactions_q_reg_n_0_[3] ), + .R(aresetn_0)); + LUT1 #( + .INIT(2'h1)) + \pushed_commands[0]_i_1__0 + (.I0(pushed_commands_reg__0[0]), + .O(p_0_in__0[0])); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT2 #( + .INIT(4'h6)) + \pushed_commands[1]_i_1__0 + (.I0(pushed_commands_reg__0[0]), + .I1(pushed_commands_reg__0[1]), + .O(p_0_in__0[1])); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT3 #( + .INIT(8'h78)) + \pushed_commands[2]_i_1__0 + (.I0(pushed_commands_reg__0[0]), + .I1(pushed_commands_reg__0[1]), + .I2(pushed_commands_reg__0[2]), + .O(p_0_in__0[2])); + LUT2 #( + .INIT(4'hB)) + \pushed_commands[3]_i_1__0 + (.I0(E), + .I1(aresetn), + .O(\pushed_commands[3]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT4 #( + .INIT(16'h7F80)) + \pushed_commands[3]_i_2__0 + (.I0(pushed_commands_reg__0[1]), + .I1(pushed_commands_reg__0[0]), + .I2(pushed_commands_reg__0[2]), + .I3(pushed_commands_reg__0[3]), + .O(p_0_in__0[3])); + FDRE \pushed_commands_reg[0] + (.C(aclk), + .CE(pushed_new_cmd), + .D(p_0_in__0[0]), + .Q(pushed_commands_reg__0[0]), + .R(\pushed_commands[3]_i_1__0_n_0 )); + FDRE \pushed_commands_reg[1] + (.C(aclk), + .CE(pushed_new_cmd), + .D(p_0_in__0[1]), + .Q(pushed_commands_reg__0[1]), + .R(\pushed_commands[3]_i_1__0_n_0 )); + FDRE \pushed_commands_reg[2] + (.C(aclk), + .CE(pushed_new_cmd), + .D(p_0_in__0[2]), + .Q(pushed_commands_reg__0[2]), + .R(\pushed_commands[3]_i_1__0_n_0 )); + FDRE \pushed_commands_reg[3] + (.C(aclk), + .CE(pushed_new_cmd), + .D(p_0_in__0[3]), + .Q(pushed_commands_reg__0[3]), + .R(\pushed_commands[3]_i_1__0_n_0 )); + FDRE \queue_id_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\USE_R_CHANNEL.cmd_queue_n_17 ), + .Q(\queue_id_reg_n_0_[0] ), + .R(aresetn_0)); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT3 #( + .INIT(8'h01)) + \size_mask_q[0]_i_1__0 + (.I0(s_axi_arsize[2]), + .I1(s_axi_arsize[0]), + .I2(s_axi_arsize[1]), + .O(\size_mask_q[0]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT2 #( + .INIT(4'h1)) + \size_mask_q[1]_i_1__0 + (.I0(s_axi_arsize[2]), + .I1(s_axi_arsize[1]), + .O(\size_mask_q[1]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT3 #( + .INIT(8'h07)) + \size_mask_q[2]_i_1__0 + (.I0(s_axi_arsize[0]), + .I1(s_axi_arsize[1]), + .I2(s_axi_arsize[2]), + .O(\size_mask_q[2]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT1 #( + .INIT(2'h1)) + \size_mask_q[3]_i_1__0 + (.I0(s_axi_arsize[2]), + .O(\size_mask_q[3]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT3 #( + .INIT(8'h57)) + \size_mask_q[4]_i_1__0 + (.I0(s_axi_arsize[2]), + .I1(s_axi_arsize[0]), + .I2(s_axi_arsize[1]), + .O(\size_mask_q[4]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT2 #( + .INIT(4'h7)) + \size_mask_q[5]_i_1__0 + (.I0(s_axi_arsize[2]), + .I1(s_axi_arsize[1]), + .O(\size_mask_q[5]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT3 #( + .INIT(8'h7F)) + \size_mask_q[6]_i_1__0 + (.I0(s_axi_arsize[2]), + .I1(s_axi_arsize[0]), + .I2(s_axi_arsize[1]), + .O(\size_mask_q[6]_i_1__0_n_0 )); + FDRE \size_mask_q_reg[0] + (.C(aclk), + .CE(E), + .D(\size_mask_q[0]_i_1__0_n_0 ), + .Q(size_mask_q[0]), + .R(aresetn_0)); + FDRE \size_mask_q_reg[1] (.C(aclk), - .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[7]_i_1_n_6 ), - .Q(next_mi_addr[5]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \next_mi_addr_reg[6] + .CE(E), + .D(\size_mask_q[1]_i_1__0_n_0 ), + .Q(size_mask_q[1]), + .R(aresetn_0)); + FDRE \size_mask_q_reg[2] (.C(aclk), - .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[7]_i_1_n_5 ), - .Q(next_mi_addr[6]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \next_mi_addr_reg[7] + .CE(E), + .D(\size_mask_q[2]_i_1__0_n_0 ), + .Q(size_mask_q[2]), + .R(aresetn_0)); + FDRE \size_mask_q_reg[31] (.C(aclk), - .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[7]_i_1_n_4 ), - .Q(next_mi_addr[7]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - CARRY4 \next_mi_addr_reg[7]_i_1 - (.CI(\next_mi_addr_reg[3]_i_1_n_0 ), - .CO({\next_mi_addr_reg[7]_i_1_n_0 ,\next_mi_addr_reg[7]_i_1_n_1 ,\next_mi_addr_reg[7]_i_1_n_2 ,\next_mi_addr_reg[7]_i_1_n_3 }), - .CYINIT(1'b0), - .DI(m_axi_araddr[7:4]), - .O({\next_mi_addr_reg[7]_i_1_n_4 ,\next_mi_addr_reg[7]_i_1_n_5 ,\next_mi_addr_reg[7]_i_1_n_6 ,\next_mi_addr_reg[7]_i_1_n_7 }), - .S({\next_mi_addr[7]_i_2_n_0 ,\next_mi_addr[7]_i_3_n_0 ,\next_mi_addr[7]_i_4_n_0 ,\next_mi_addr[7]_i_5_n_0 })); - FDRE \next_mi_addr_reg[8] + .CE(E), + .D(1'b1), + .Q(size_mask_q[31]), + .R(aresetn_0)); + FDRE \size_mask_q_reg[3] (.C(aclk), - .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[11]_i_1_n_7 ), - .Q(next_mi_addr[8]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \next_mi_addr_reg[9] + .CE(E), + .D(\size_mask_q[3]_i_1__0_n_0 ), + .Q(size_mask_q[3]), + .R(aresetn_0)); + FDRE \size_mask_q_reg[4] (.C(aclk), - .CE(pushed_new_cmd), - .D(\next_mi_addr_reg[11]_i_1_n_6 ), - .Q(next_mi_addr[9]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \num_transactions_q_reg[0] + .CE(E), + .D(\size_mask_q[4]_i_1__0_n_0 ), + .Q(size_mask_q[4]), + .R(aresetn_0)); + FDRE \size_mask_q_reg[5] (.C(aclk), .CE(E), - .D(s_axi_arlen[4]), - .Q(num_transactions_q[0]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \num_transactions_q_reg[1] + .D(\size_mask_q[5]_i_1__0_n_0 ), + .Q(size_mask_q[5]), + .R(aresetn_0)); + FDRE \size_mask_q_reg[6] (.C(aclk), .CE(E), - .D(s_axi_arlen[5]), - .Q(num_transactions_q[1]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \num_transactions_q_reg[2] + .D(\size_mask_q[6]_i_1__0_n_0 ), + .Q(size_mask_q[6]), + .R(aresetn_0)); + LUT5 #( + .INIT(32'h44444004)) + split_in_progress_i_2 + (.I0(multiple_id_non_split), + .I1(need_to_split_q), + .I2(\queue_id_reg_n_0_[0] ), + .I3(\m_axi_arid[0] ), + .I4(cmd_empty), + .O(allow_split_cmd__1)); + FDRE split_in_progress_reg + (.C(aclk), + .CE(1'b1), + .D(\USE_R_CHANNEL.cmd_queue_n_20 ), + .Q(split_in_progress_reg_n_0), + .R(1'b0)); + FDRE split_ongoing_reg + (.C(aclk), + .CE(pushed_new_cmd), + .D(\USE_R_CHANNEL.cmd_queue_n_0 ), + .Q(split_ongoing), + .R(aresetn_0)); +endmodule + +module Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi3_conv + (m_axi_awvalid, + M_AXI_ARID, + M_AXI_AWID, + m_axi_awlen, + m_axi_arlen, + s_axi_awready, + s_axi_arready, + m_axi_wvalid, + m_axi_awlock, + m_axi_rready, + s_axi_rvalid, + m_axi_arlock, + s_axi_rlast, + m_axi_wid, + s_axi_bresp, + m_axi_awsize, + m_axi_awburst, + m_axi_awcache, + m_axi_awprot, + m_axi_awqos, + s_axi_wready, + m_axi_wlast, + m_axi_arsize, + m_axi_arburst, + m_axi_arcache, + m_axi_arprot, + m_axi_arqos, + m_axi_awaddr, + m_axi_araddr, + s_axi_bvalid, + m_axi_arvalid, + m_axi_bready, + m_axi_bvalid, + s_axi_bready, + aresetn, + s_axi_awsize, + s_axi_awlen, + s_axi_arsize, + s_axi_arlen, + s_axi_wvalid, + m_axi_rvalid, + s_axi_rready, + m_axi_rlast, + m_axi_arready, + aclk, + s_axi_awid, + s_axi_awaddr, + s_axi_awburst, + s_axi_awlock, + s_axi_awcache, + s_axi_awprot, + s_axi_awqos, + s_axi_arid, + s_axi_araddr, + s_axi_arburst, + s_axi_arlock, + s_axi_arcache, + s_axi_arprot, + s_axi_arqos, + m_axi_awready, + m_axi_wready, + m_axi_bresp, + s_axi_awvalid, + s_axi_arvalid); + output m_axi_awvalid; + output [0:0]M_AXI_ARID; + output [0:0]M_AXI_AWID; + output [3:0]m_axi_awlen; + output [3:0]m_axi_arlen; + output s_axi_awready; + output s_axi_arready; + output m_axi_wvalid; + output [0:0]m_axi_awlock; + output m_axi_rready; + output s_axi_rvalid; + output [0:0]m_axi_arlock; + output s_axi_rlast; + output [0:0]m_axi_wid; + output [1:0]s_axi_bresp; + output [2:0]m_axi_awsize; + output [1:0]m_axi_awburst; + output [3:0]m_axi_awcache; + output [2:0]m_axi_awprot; + output [3:0]m_axi_awqos; + output s_axi_wready; + output m_axi_wlast; + output [2:0]m_axi_arsize; + output [1:0]m_axi_arburst; + output [3:0]m_axi_arcache; + output [2:0]m_axi_arprot; + output [3:0]m_axi_arqos; + output [31:0]m_axi_awaddr; + output [31:0]m_axi_araddr; + output s_axi_bvalid; + output m_axi_arvalid; + output m_axi_bready; + input m_axi_bvalid; + input s_axi_bready; + input aresetn; + input [2:0]s_axi_awsize; + input [7:0]s_axi_awlen; + input [2:0]s_axi_arsize; + input [7:0]s_axi_arlen; + input s_axi_wvalid; + input m_axi_rvalid; + input s_axi_rready; + input m_axi_rlast; + input m_axi_arready; + input aclk; + input [0:0]s_axi_awid; + input [31:0]s_axi_awaddr; + input [1:0]s_axi_awburst; + input [0:0]s_axi_awlock; + input [3:0]s_axi_awcache; + input [2:0]s_axi_awprot; + input [3:0]s_axi_awqos; + input [0:0]s_axi_arid; + input [31:0]s_axi_araddr; + input [1:0]s_axi_arburst; + input [0:0]s_axi_arlock; + input [3:0]s_axi_arcache; + input [2:0]s_axi_arprot; + input [3:0]s_axi_arqos; + input m_axi_awready; + input m_axi_wready; + input [1:0]m_axi_bresp; + input s_axi_awvalid; + input s_axi_arvalid; + + wire [0:0]M_AXI_ARID; + wire [0:0]M_AXI_AWID; + wire \USE_BURSTS.cmd_queue/inst/empty ; + wire \USE_WRITE.write_addr_inst_n_23 ; + wire \USE_WRITE.write_addr_inst_n_6 ; + wire aclk; + wire [1:0]areset_d; + wire aresetn; + wire last_word; + wire [31:0]m_axi_araddr; + wire [1:0]m_axi_arburst; + wire [3:0]m_axi_arcache; + wire [3:0]m_axi_arlen; + wire [0:0]m_axi_arlock; + wire [2:0]m_axi_arprot; + wire [3:0]m_axi_arqos; + wire m_axi_arready; + wire [2:0]m_axi_arsize; + wire m_axi_arvalid; + wire [31:0]m_axi_awaddr; + wire [1:0]m_axi_awburst; + wire [3:0]m_axi_awcache; + wire [3:0]m_axi_awlen; + wire [0:0]m_axi_awlock; + wire [2:0]m_axi_awprot; + wire [3:0]m_axi_awqos; + wire m_axi_awready; + wire [2:0]m_axi_awsize; + wire m_axi_awvalid; + wire m_axi_bready; + wire [1:0]m_axi_bresp; + wire m_axi_bvalid; + wire m_axi_rlast; + wire m_axi_rready; + wire m_axi_rvalid; + wire [0:0]m_axi_wid; + wire m_axi_wlast; + wire m_axi_wready; + wire m_axi_wvalid; + wire [31:0]s_axi_araddr; + wire [1:0]s_axi_arburst; + wire [3:0]s_axi_arcache; + wire [0:0]s_axi_arid; + wire [7:0]s_axi_arlen; + wire [0:0]s_axi_arlock; + wire [2:0]s_axi_arprot; + wire [3:0]s_axi_arqos; + wire s_axi_arready; + wire [2:0]s_axi_arsize; + wire s_axi_arvalid; + wire [31:0]s_axi_awaddr; + wire [1:0]s_axi_awburst; + wire [3:0]s_axi_awcache; + wire [0:0]s_axi_awid; + wire [7:0]s_axi_awlen; + wire [0:0]s_axi_awlock; + wire [2:0]s_axi_awprot; + wire [3:0]s_axi_awqos; + wire s_axi_awready; + wire [2:0]s_axi_awsize; + wire s_axi_awvalid; + wire s_axi_bready; + wire [1:0]s_axi_bresp; + wire s_axi_bvalid; + wire s_axi_rlast; + wire s_axi_rready; + wire s_axi_rvalid; + wire s_axi_wready; + wire s_axi_wvalid; + wire [3:0]wr_cmd_b_repeat; + wire wr_cmd_b_split; + wire [3:0]wr_cmd_length; + wire wr_cmd_ready; + + Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_a_axi3_conv__parameterized0 \USE_READ.USE_SPLIT_R.read_addr_inst + (.E(s_axi_arready), + .aclk(aclk), + .areset_d(areset_d), + .\areset_d_reg[1] (\USE_WRITE.write_addr_inst_n_23 ), + .aresetn(aresetn), + .aresetn_0(\USE_WRITE.write_addr_inst_n_6 ), + .m_axi_araddr(m_axi_araddr), + .m_axi_arburst(m_axi_arburst), + .m_axi_arcache(m_axi_arcache), + .\m_axi_arid[0] (M_AXI_ARID), + .m_axi_arlen(m_axi_arlen), + .m_axi_arlock(m_axi_arlock), + .m_axi_arprot(m_axi_arprot), + .m_axi_arqos(m_axi_arqos), + .m_axi_arready(m_axi_arready), + .m_axi_arsize(m_axi_arsize), + .m_axi_arvalid(m_axi_arvalid), + .m_axi_rlast(m_axi_rlast), + .m_axi_rready(m_axi_rready), + .m_axi_rvalid(m_axi_rvalid), + .s_axi_araddr(s_axi_araddr), + .s_axi_arburst(s_axi_arburst), + .s_axi_arcache(s_axi_arcache), + .s_axi_arid(s_axi_arid), + .s_axi_arlen(s_axi_arlen), + .s_axi_arlock(s_axi_arlock), + .s_axi_arprot(s_axi_arprot), + .s_axi_arqos(s_axi_arqos), + .s_axi_arsize(s_axi_arsize), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_rlast(s_axi_rlast), + .s_axi_rready(s_axi_rready), + .s_axi_rvalid(s_axi_rvalid)); + Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_b_downsizer \USE_WRITE.USE_SPLIT_W.write_resp_inst + (.aclk(aclk), + .aresetn(\USE_WRITE.write_addr_inst_n_6 ), + .dout({wr_cmd_b_split,wr_cmd_b_repeat}), + .last_word(last_word), + .m_axi_bready(m_axi_bready), + .m_axi_bresp(m_axi_bresp), + .m_axi_bvalid(m_axi_bvalid), + .s_axi_bready(s_axi_bready), + .s_axi_bresp(s_axi_bresp), + .s_axi_bvalid(s_axi_bvalid)); + Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_a_axi3_conv \USE_WRITE.write_addr_inst + (.E(s_axi_awready), + .\S_AXI_BRESP_ACC_reg[0] ({wr_cmd_b_split,wr_cmd_b_repeat}), + .aclk(aclk), + .areset_d(areset_d), + .aresetn(aresetn), + .command_ongoing_reg_0(\USE_WRITE.write_addr_inst_n_23 ), + .din({M_AXI_AWID,m_axi_awlen}), + .dout({m_axi_wid,wr_cmd_length}), + .empty(\USE_BURSTS.cmd_queue/inst/empty ), + .last_word(last_word), + .m_axi_awaddr(m_axi_awaddr), + .m_axi_awburst(m_axi_awburst), + .m_axi_awcache(m_axi_awcache), + .m_axi_awlock(m_axi_awlock), + .m_axi_awprot(m_axi_awprot), + .m_axi_awqos(m_axi_awqos), + .m_axi_awready(m_axi_awready), + .m_axi_awsize(m_axi_awsize), + .m_axi_awvalid(m_axi_awvalid), + .m_axi_bvalid(m_axi_bvalid), + .m_axi_wready(m_axi_wready), + .m_axi_wvalid(m_axi_wvalid), + .\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg (\USE_WRITE.write_addr_inst_n_6 ), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awburst(s_axi_awburst), + .s_axi_awcache(s_axi_awcache), + .s_axi_awid(s_axi_awid), + .s_axi_awlen(s_axi_awlen), + .s_axi_awlock(s_axi_awlock), + .s_axi_awprot(s_axi_awprot), + .s_axi_awqos(s_axi_awqos), + .s_axi_awsize(s_axi_awsize), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_bready(s_axi_bready), + .s_axi_wready(s_axi_wready), + .s_axi_wvalid(s_axi_wvalid), + .wr_cmd_ready(wr_cmd_ready)); + Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_w_axi3_conv \USE_WRITE.write_data_inst + (.aclk(aclk), + .aresetn(\USE_WRITE.write_addr_inst_n_6 ), + .dout(wr_cmd_length), + .empty(\USE_BURSTS.cmd_queue/inst/empty ), + .empty_fwft_i_reg(s_axi_wready), + .m_axi_wlast(m_axi_wlast), + .m_axi_wready(m_axi_wready), + .s_axi_wvalid(s_axi_wvalid), + .wr_cmd_ready(wr_cmd_ready)); +endmodule + +(* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) +(* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) +(* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_READ = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *) +(* C_AXI_SUPPORTS_WRITE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_FAMILY = "zynq" *) +(* C_IGNORE_ID = "0" *) (* C_M_AXI_PROTOCOL = "1" *) (* C_S_AXI_PROTOCOL = "0" *) +(* C_TRANSLATION_MODE = "2" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* P_AXI3 = "1" *) +(* P_AXI4 = "0" *) (* P_AXILITE = "2" *) (* P_AXILITE_SIZE = "3'b011" *) +(* P_CONVERSION = "2" *) (* P_DECERR = "2'b11" *) (* P_INCR = "2'b01" *) +(* P_PROTECTION = "1" *) (* P_SLVERR = "2'b10" *) +module Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter + (aclk, + aresetn, + s_axi_awid, + s_axi_awaddr, + s_axi_awlen, + s_axi_awsize, + s_axi_awburst, + s_axi_awlock, + s_axi_awcache, + s_axi_awprot, + s_axi_awregion, + s_axi_awqos, + s_axi_awuser, + s_axi_awvalid, + s_axi_awready, + s_axi_wid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wlast, + s_axi_wuser, + s_axi_wvalid, + s_axi_wready, + s_axi_bid, + s_axi_bresp, + s_axi_buser, + s_axi_bvalid, + s_axi_bready, + s_axi_arid, + s_axi_araddr, + s_axi_arlen, + s_axi_arsize, + s_axi_arburst, + s_axi_arlock, + s_axi_arcache, + s_axi_arprot, + s_axi_arregion, + s_axi_arqos, + s_axi_aruser, + s_axi_arvalid, + s_axi_arready, + s_axi_rid, + s_axi_rdata, + s_axi_rresp, + s_axi_rlast, + s_axi_ruser, + s_axi_rvalid, + s_axi_rready, + m_axi_awid, + m_axi_awaddr, + m_axi_awlen, + m_axi_awsize, + m_axi_awburst, + m_axi_awlock, + m_axi_awcache, + m_axi_awprot, + m_axi_awregion, + m_axi_awqos, + m_axi_awuser, + m_axi_awvalid, + m_axi_awready, + m_axi_wid, + m_axi_wdata, + m_axi_wstrb, + m_axi_wlast, + m_axi_wuser, + m_axi_wvalid, + m_axi_wready, + m_axi_bid, + m_axi_bresp, + m_axi_buser, + m_axi_bvalid, + m_axi_bready, + m_axi_arid, + m_axi_araddr, + m_axi_arlen, + m_axi_arsize, + m_axi_arburst, + m_axi_arlock, + m_axi_arcache, + m_axi_arprot, + m_axi_arregion, + m_axi_arqos, + m_axi_aruser, + m_axi_arvalid, + m_axi_arready, + m_axi_rid, + m_axi_rdata, + m_axi_rresp, + m_axi_rlast, + m_axi_ruser, + m_axi_rvalid, + m_axi_rready); + input aclk; + input aresetn; + input [0:0]s_axi_awid; + input [31:0]s_axi_awaddr; + input [7:0]s_axi_awlen; + input [2:0]s_axi_awsize; + input [1:0]s_axi_awburst; + input [0:0]s_axi_awlock; + input [3:0]s_axi_awcache; + input [2:0]s_axi_awprot; + input [3:0]s_axi_awregion; + input [3:0]s_axi_awqos; + input [0:0]s_axi_awuser; + input s_axi_awvalid; + output s_axi_awready; + input [0:0]s_axi_wid; + input [63:0]s_axi_wdata; + input [7:0]s_axi_wstrb; + input s_axi_wlast; + input [0:0]s_axi_wuser; + input s_axi_wvalid; + output s_axi_wready; + output [0:0]s_axi_bid; + output [1:0]s_axi_bresp; + output [0:0]s_axi_buser; + output s_axi_bvalid; + input s_axi_bready; + input [0:0]s_axi_arid; + input [31:0]s_axi_araddr; + input [7:0]s_axi_arlen; + input [2:0]s_axi_arsize; + input [1:0]s_axi_arburst; + input [0:0]s_axi_arlock; + input [3:0]s_axi_arcache; + input [2:0]s_axi_arprot; + input [3:0]s_axi_arregion; + input [3:0]s_axi_arqos; + input [0:0]s_axi_aruser; + input s_axi_arvalid; + output s_axi_arready; + output [0:0]s_axi_rid; + output [63:0]s_axi_rdata; + output [1:0]s_axi_rresp; + output s_axi_rlast; + output [0:0]s_axi_ruser; + output s_axi_rvalid; + input s_axi_rready; + output [0:0]m_axi_awid; + output [31:0]m_axi_awaddr; + output [3:0]m_axi_awlen; + output [2:0]m_axi_awsize; + output [1:0]m_axi_awburst; + output [1:0]m_axi_awlock; + output [3:0]m_axi_awcache; + output [2:0]m_axi_awprot; + output [3:0]m_axi_awregion; + output [3:0]m_axi_awqos; + output [0:0]m_axi_awuser; + output m_axi_awvalid; + input m_axi_awready; + output [0:0]m_axi_wid; + output [63:0]m_axi_wdata; + output [7:0]m_axi_wstrb; + output m_axi_wlast; + output [0:0]m_axi_wuser; + output m_axi_wvalid; + input m_axi_wready; + input [0:0]m_axi_bid; + input [1:0]m_axi_bresp; + input [0:0]m_axi_buser; + input m_axi_bvalid; + output m_axi_bready; + output [0:0]m_axi_arid; + output [31:0]m_axi_araddr; + output [3:0]m_axi_arlen; + output [2:0]m_axi_arsize; + output [1:0]m_axi_arburst; + output [1:0]m_axi_arlock; + output [3:0]m_axi_arcache; + output [2:0]m_axi_arprot; + output [3:0]m_axi_arregion; + output [3:0]m_axi_arqos; + output [0:0]m_axi_aruser; + output m_axi_arvalid; + input m_axi_arready; + input [0:0]m_axi_rid; + input [63:0]m_axi_rdata; + input [1:0]m_axi_rresp; + input m_axi_rlast; + input [0:0]m_axi_ruser; + input m_axi_rvalid; + output m_axi_rready; + + wire \ ; + wire aclk; + wire aresetn; + wire [31:0]m_axi_araddr; + wire [1:0]m_axi_arburst; + wire [3:0]m_axi_arcache; + wire [0:0]m_axi_arid; + wire [3:0]m_axi_arlen; + wire [0:0]\^m_axi_arlock ; + wire [2:0]m_axi_arprot; + wire [3:0]m_axi_arqos; + wire m_axi_arready; + wire [2:0]m_axi_arsize; + wire m_axi_arvalid; + wire [31:0]m_axi_awaddr; + wire [1:0]m_axi_awburst; + wire [3:0]m_axi_awcache; + wire [0:0]m_axi_awid; + wire [3:0]m_axi_awlen; + wire [0:0]\^m_axi_awlock ; + wire [2:0]m_axi_awprot; + wire [3:0]m_axi_awqos; + wire m_axi_awready; + wire [2:0]m_axi_awsize; + wire m_axi_awvalid; + wire [0:0]m_axi_bid; + wire m_axi_bready; + wire [1:0]m_axi_bresp; + wire m_axi_bvalid; + wire [63:0]m_axi_rdata; + wire [0:0]m_axi_rid; + wire m_axi_rlast; + wire m_axi_rready; + wire [1:0]m_axi_rresp; + wire [0:0]m_axi_ruser; + wire m_axi_rvalid; + wire [0:0]m_axi_wid; + wire m_axi_wlast; + wire m_axi_wready; + wire m_axi_wvalid; + wire [31:0]s_axi_araddr; + wire [1:0]s_axi_arburst; + wire [3:0]s_axi_arcache; + wire [0:0]s_axi_arid; + wire [7:0]s_axi_arlen; + wire [0:0]s_axi_arlock; + wire [2:0]s_axi_arprot; + wire [3:0]s_axi_arqos; + wire s_axi_arready; + wire [2:0]s_axi_arsize; + wire s_axi_arvalid; + wire [31:0]s_axi_awaddr; + wire [1:0]s_axi_awburst; + wire [3:0]s_axi_awcache; + wire [0:0]s_axi_awid; + wire [7:0]s_axi_awlen; + wire [0:0]s_axi_awlock; + wire [2:0]s_axi_awprot; + wire [3:0]s_axi_awqos; + wire s_axi_awready; + wire [2:0]s_axi_awsize; + wire s_axi_awvalid; + wire s_axi_bready; + wire [1:0]s_axi_bresp; + wire s_axi_bvalid; + wire s_axi_rlast; + wire s_axi_rready; + wire s_axi_rvalid; + wire [63:0]s_axi_wdata; + wire s_axi_wready; + wire [7:0]s_axi_wstrb; + wire s_axi_wvalid; + + assign m_axi_arlock[1] = \ ; + assign m_axi_arlock[0] = \^m_axi_arlock [0]; + assign m_axi_arregion[3] = \ ; + assign m_axi_arregion[2] = \ ; + assign m_axi_arregion[1] = \ ; + assign m_axi_arregion[0] = \ ; + assign m_axi_aruser[0] = \ ; + assign m_axi_awlock[1] = \ ; + assign m_axi_awlock[0] = \^m_axi_awlock [0]; + assign m_axi_awregion[3] = \ ; + assign m_axi_awregion[2] = \ ; + assign m_axi_awregion[1] = \ ; + assign m_axi_awregion[0] = \ ; + assign m_axi_awuser[0] = \ ; + assign m_axi_wdata[63:0] = s_axi_wdata; + assign m_axi_wstrb[7:0] = s_axi_wstrb; + assign m_axi_wuser[0] = \ ; + assign s_axi_bid[0] = m_axi_bid; + assign s_axi_buser[0] = \ ; + assign s_axi_rdata[63:0] = m_axi_rdata; + assign s_axi_rid[0] = m_axi_rid; + assign s_axi_rresp[1:0] = m_axi_rresp; + assign s_axi_ruser[0] = m_axi_ruser; + GND GND + (.G(\ )); + Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi3_conv \gen_axi4_axi3.axi3_conv_inst + (.M_AXI_ARID(m_axi_arid), + .M_AXI_AWID(m_axi_awid), + .aclk(aclk), + .aresetn(aresetn), + .m_axi_araddr(m_axi_araddr), + .m_axi_arburst(m_axi_arburst), + .m_axi_arcache(m_axi_arcache), + .m_axi_arlen(m_axi_arlen), + .m_axi_arlock(\^m_axi_arlock ), + .m_axi_arprot(m_axi_arprot), + .m_axi_arqos(m_axi_arqos), + .m_axi_arready(m_axi_arready), + .m_axi_arsize(m_axi_arsize), + .m_axi_arvalid(m_axi_arvalid), + .m_axi_awaddr(m_axi_awaddr), + .m_axi_awburst(m_axi_awburst), + .m_axi_awcache(m_axi_awcache), + .m_axi_awlen(m_axi_awlen), + .m_axi_awlock(\^m_axi_awlock ), + .m_axi_awprot(m_axi_awprot), + .m_axi_awqos(m_axi_awqos), + .m_axi_awready(m_axi_awready), + .m_axi_awsize(m_axi_awsize), + .m_axi_awvalid(m_axi_awvalid), + .m_axi_bready(m_axi_bready), + .m_axi_bresp(m_axi_bresp), + .m_axi_bvalid(m_axi_bvalid), + .m_axi_rlast(m_axi_rlast), + .m_axi_rready(m_axi_rready), + .m_axi_rvalid(m_axi_rvalid), + .m_axi_wid(m_axi_wid), + .m_axi_wlast(m_axi_wlast), + .m_axi_wready(m_axi_wready), + .m_axi_wvalid(m_axi_wvalid), + .s_axi_araddr(s_axi_araddr), + .s_axi_arburst(s_axi_arburst), + .s_axi_arcache(s_axi_arcache), + .s_axi_arid(s_axi_arid), + .s_axi_arlen(s_axi_arlen), + .s_axi_arlock(s_axi_arlock), + .s_axi_arprot(s_axi_arprot), + .s_axi_arqos(s_axi_arqos), + .s_axi_arready(s_axi_arready), + .s_axi_arsize(s_axi_arsize), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awburst(s_axi_awburst), + .s_axi_awcache(s_axi_awcache), + .s_axi_awid(s_axi_awid), + .s_axi_awlen(s_axi_awlen), + .s_axi_awlock(s_axi_awlock), + .s_axi_awprot(s_axi_awprot), + .s_axi_awqos(s_axi_awqos), + .s_axi_awready(s_axi_awready), + .s_axi_awsize(s_axi_awsize), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_bready(s_axi_bready), + .s_axi_bresp(s_axi_bresp), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_rlast(s_axi_rlast), + .s_axi_rready(s_axi_rready), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_wready(s_axi_wready), + .s_axi_wvalid(s_axi_wvalid)); +endmodule + +module Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_b_downsizer + (last_word, + s_axi_bvalid, + s_axi_bresp, + m_axi_bready, + aresetn, + aclk, + dout, + s_axi_bready, + m_axi_bvalid, + m_axi_bresp); + output last_word; + output s_axi_bvalid; + output [1:0]s_axi_bresp; + output m_axi_bready; + input aresetn; + input aclk; + input [4:0]dout; + input s_axi_bready; + input m_axi_bvalid; + input [1:0]m_axi_bresp; + + wire [1:0]S_AXI_BRESP_ACC; + wire aclk; + wire aresetn; + wire [4:0]dout; + wire first_mi_word; + wire last_word; + wire m_axi_bready; + wire [1:0]m_axi_bresp; + wire m_axi_bvalid; + wire [0:0]next_repeat_cnt; + wire p_2_in; + wire \repeat_cnt[1]_i_1_n_0 ; + wire \repeat_cnt[2]_i_1_n_0 ; + wire \repeat_cnt[3]_i_1_n_0 ; + wire \repeat_cnt[3]_i_2_n_0 ; + wire [0:0]repeat_cnt_pre; + wire [3:0]repeat_cnt_reg__0; + wire s_axi_bready; + wire [1:0]s_axi_bresp; + wire s_axi_bvalid; + + FDRE \S_AXI_BRESP_ACC_reg[0] (.C(aclk), - .CE(E), - .D(s_axi_arlen[6]), - .Q(num_transactions_q[2]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \num_transactions_q_reg[3] + .CE(p_2_in), + .D(s_axi_bresp[0]), + .Q(S_AXI_BRESP_ACC[0]), + .R(aresetn)); + FDRE \S_AXI_BRESP_ACC_reg[1] (.C(aclk), - .CE(E), - .D(s_axi_arlen[7]), - .Q(num_transactions_q[3]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - LUT1 #( - .INIT(2'h1)) - \pushed_commands[0]_i_1 - (.I0(pushed_commands_reg__0[0]), - .O(p_0_in[0])); - (* SOFT_HLUTNM = "soft_lutpair16" *) - LUT2 #( - .INIT(4'h6)) - \pushed_commands[1]_i_1 - (.I0(pushed_commands_reg__0[1]), - .I1(pushed_commands_reg__0[0]), - .O(p_0_in[1])); - (* SOFT_HLUTNM = "soft_lutpair16" *) + .CE(p_2_in), + .D(s_axi_bresp[1]), + .Q(S_AXI_BRESP_ACC[1]), + .R(aresetn)); LUT3 #( - .INIT(8'h6A)) - \pushed_commands[2]_i_1 - (.I0(pushed_commands_reg__0[2]), - .I1(pushed_commands_reg__0[0]), - .I2(pushed_commands_reg__0[1]), - .O(p_0_in[2])); - LUT2 #( - .INIT(4'hB)) - \pushed_commands[3]_i_1 - (.I0(E), - .I1(aresetn), - .O(\pushed_commands[3]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair14" *) - LUT4 #( - .INIT(16'h6AAA)) - \pushed_commands[3]_i_2 - (.I0(pushed_commands_reg__0[3]), - .I1(pushed_commands_reg__0[1]), - .I2(pushed_commands_reg__0[0]), - .I3(pushed_commands_reg__0[2]), - .O(p_0_in[3])); - FDRE \pushed_commands_reg[0] + .INIT(8'hB0)) + first_mi_word_i_1 + (.I0(s_axi_bready), + .I1(last_word), + .I2(m_axi_bvalid), + .O(p_2_in)); + FDSE first_mi_word_reg (.C(aclk), - .CE(pushed_new_cmd), - .D(p_0_in[0]), - .Q(pushed_commands_reg__0[0]), - .R(\pushed_commands[3]_i_1_n_0 )); - FDRE \pushed_commands_reg[1] + .CE(p_2_in), + .D(last_word), + .Q(first_mi_word), + .S(aresetn)); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT3 #( + .INIT(8'hA2)) + m_axi_bready_INST_0 + (.I0(m_axi_bvalid), + .I1(last_word), + .I2(s_axi_bready), + .O(m_axi_bready)); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT3 #( + .INIT(8'h1D)) + \repeat_cnt[0]_i_1 + (.I0(repeat_cnt_reg__0[0]), + .I1(first_mi_word), + .I2(dout[0]), + .O(next_repeat_cnt)); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT5 #( + .INIT(32'hCCA533A5)) + \repeat_cnt[1]_i_1 + (.I0(repeat_cnt_reg__0[0]), + .I1(dout[0]), + .I2(repeat_cnt_reg__0[1]), + .I3(first_mi_word), + .I4(dout[1]), + .O(\repeat_cnt[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFAFAFC030505FC03)) + \repeat_cnt[2]_i_1 + (.I0(dout[1]), + .I1(repeat_cnt_reg__0[1]), + .I2(repeat_cnt_pre), + .I3(repeat_cnt_reg__0[2]), + .I4(first_mi_word), + .I5(dout[2]), + .O(\repeat_cnt[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT3 #( + .INIT(8'hB8)) + \repeat_cnt[2]_i_2 + (.I0(dout[0]), + .I1(first_mi_word), + .I2(repeat_cnt_reg__0[0]), + .O(repeat_cnt_pre)); + LUT6 #( + .INIT(64'hFAFAFC030505FC03)) + \repeat_cnt[3]_i_1 + (.I0(dout[2]), + .I1(repeat_cnt_reg__0[2]), + .I2(\repeat_cnt[3]_i_2_n_0 ), + .I3(repeat_cnt_reg__0[3]), + .I4(first_mi_word), + .I5(dout[3]), + .O(\repeat_cnt[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT5 #( + .INIT(32'hFFFACCFA)) + \repeat_cnt[3]_i_2 + (.I0(repeat_cnt_reg__0[0]), + .I1(dout[0]), + .I2(repeat_cnt_reg__0[1]), + .I3(first_mi_word), + .I4(dout[1]), + .O(\repeat_cnt[3]_i_2_n_0 )); + FDRE \repeat_cnt_reg[0] (.C(aclk), - .CE(pushed_new_cmd), - .D(p_0_in[1]), - .Q(pushed_commands_reg__0[1]), - .R(\pushed_commands[3]_i_1_n_0 )); - FDRE \pushed_commands_reg[2] + .CE(p_2_in), + .D(next_repeat_cnt), + .Q(repeat_cnt_reg__0[0]), + .R(aresetn)); + FDRE \repeat_cnt_reg[1] (.C(aclk), - .CE(pushed_new_cmd), - .D(p_0_in[2]), - .Q(pushed_commands_reg__0[2]), - .R(\pushed_commands[3]_i_1_n_0 )); - FDRE \pushed_commands_reg[3] + .CE(p_2_in), + .D(\repeat_cnt[1]_i_1_n_0 ), + .Q(repeat_cnt_reg__0[1]), + .R(aresetn)); + FDRE \repeat_cnt_reg[2] (.C(aclk), - .CE(pushed_new_cmd), - .D(p_0_in[3]), - .Q(pushed_commands_reg__0[3]), - .R(\pushed_commands[3]_i_1_n_0 )); - FDRE \queue_id_reg[0] + .CE(p_2_in), + .D(\repeat_cnt[2]_i_1_n_0 ), + .Q(repeat_cnt_reg__0[2]), + .R(aresetn)); + FDRE \repeat_cnt_reg[3] (.C(aclk), - .CE(1'b1), - .D(\USE_R_CHANNEL.cmd_queue_n_18 ), - .Q(queue_id), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair20" *) - LUT3 #( - .INIT(8'h01)) - \size_mask_q[0]_i_1 - (.I0(s_axi_arsize[2]), - .I1(s_axi_arsize[0]), - .I2(s_axi_arsize[1]), - .O(size_mask[0])); - (* SOFT_HLUTNM = "soft_lutpair24" *) + .CE(p_2_in), + .D(\repeat_cnt[3]_i_1_n_0 ), + .Q(repeat_cnt_reg__0[3]), + .R(aresetn)); + LUT6 #( + .INIT(64'hF2F0F2F2F0F0D0F0)) + \s_axi_bresp[0]_INST_0 + (.I0(dout[4]), + .I1(first_mi_word), + .I2(m_axi_bresp[0]), + .I3(S_AXI_BRESP_ACC[1]), + .I4(m_axi_bresp[1]), + .I5(S_AXI_BRESP_ACC[0]), + .O(s_axi_bresp[0])); + LUT4 #( + .INIT(16'hFF20)) + \s_axi_bresp[1]_INST_0 + (.I0(dout[4]), + .I1(first_mi_word), + .I2(S_AXI_BRESP_ACC[1]), + .I3(m_axi_bresp[1]), + .O(s_axi_bresp[1])); + (* SOFT_HLUTNM = "soft_lutpair27" *) LUT2 #( - .INIT(4'h1)) - \size_mask_q[1]_i_1 - (.I0(s_axi_arsize[2]), - .I1(s_axi_arsize[1]), - .O(size_mask[1])); - (* SOFT_HLUTNM = "soft_lutpair18" *) - LUT3 #( - .INIT(8'h07)) - \size_mask_q[2]_i_1 - (.I0(s_axi_arsize[0]), - .I1(s_axi_arsize[1]), - .I2(s_axi_arsize[2]), - .O(size_mask[2])); - (* SOFT_HLUTNM = "soft_lutpair25" *) - LUT1 #( - .INIT(2'h1)) - \size_mask_q[3]_i_1 - (.I0(s_axi_arsize[2]), - .O(size_mask[3])); - (* SOFT_HLUTNM = "soft_lutpair20" *) + .INIT(4'h8)) + s_axi_bvalid_INST_0 + (.I0(m_axi_bvalid), + .I1(last_word), + .O(s_axi_bvalid)); + LUT6 #( + .INIT(64'h5555555555555557)) + s_axi_bvalid_INST_0_i_1 + (.I0(dout[4]), + .I1(repeat_cnt_reg__0[2]), + .I2(first_mi_word), + .I3(repeat_cnt_reg__0[0]), + .I4(repeat_cnt_reg__0[1]), + .I5(repeat_cnt_reg__0[3]), + .O(last_word)); +endmodule + +module Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_w_axi3_conv + (m_axi_wlast, + wr_cmd_ready, + aresetn, + empty_fwft_i_reg, + aclk, + dout, + empty, + s_axi_wvalid, + m_axi_wready); + output m_axi_wlast; + output wr_cmd_ready; + input aresetn; + input empty_fwft_i_reg; + input aclk; + input [3:0]dout; + input empty; + input s_axi_wvalid; + input m_axi_wready; + + wire aclk; + wire aresetn; + wire [3:0]dout; + wire empty; + wire empty_fwft_i_reg; + wire first_mi_word; + wire [0:0]length_counter; + wire \length_counter_1[1]_i_1_n_0 ; + wire \length_counter_1[2]_i_1_n_0 ; + wire \length_counter_1[3]_i_1_n_0 ; + wire \length_counter_1[3]_i_2_n_0 ; + wire \length_counter_1[4]_i_1_n_0 ; + wire \length_counter_1[5]_i_1_n_0 ; + wire \length_counter_1[5]_i_2_n_0 ; + wire \length_counter_1[6]_i_1_n_0 ; + wire \length_counter_1[7]_i_1_n_0 ; + wire \length_counter_1[7]_i_2_n_0 ; + wire [7:0]length_counter_1_reg; + wire m_axi_wlast; + wire m_axi_wlast_INST_0_i_1_n_0; + wire m_axi_wlast_INST_0_i_2_n_0; + wire m_axi_wlast_INST_0_i_3_n_0; + wire m_axi_wready; + wire [0:0]next_length_counter; + wire s_axi_wvalid; + wire wr_cmd_ready; + + LUT6 #( + .INIT(64'h0080000000000000)) + fifo_gen_inst_i_2 + (.I0(m_axi_wlast_INST_0_i_3_n_0), + .I1(m_axi_wlast_INST_0_i_2_n_0), + .I2(m_axi_wlast_INST_0_i_1_n_0), + .I3(empty), + .I4(s_axi_wvalid), + .I5(m_axi_wready), + .O(wr_cmd_ready)); + FDSE first_mi_word_reg + (.C(aclk), + .CE(empty_fwft_i_reg), + .D(m_axi_wlast), + .Q(first_mi_word), + .S(aresetn)); LUT3 #( - .INIT(8'h57)) - \size_mask_q[4]_i_1 - (.I0(s_axi_arsize[2]), - .I1(s_axi_arsize[0]), - .I2(s_axi_arsize[1]), - .O(size_mask[4])); - (* SOFT_HLUTNM = "soft_lutpair24" *) - LUT2 #( - .INIT(4'h7)) - \size_mask_q[5]_i_1 - (.I0(s_axi_arsize[2]), - .I1(s_axi_arsize[1]), - .O(size_mask[5])); - (* SOFT_HLUTNM = "soft_lutpair17" *) + .INIT(8'h1D)) + \length_counter_1[0]_i_1 + (.I0(length_counter_1_reg[0]), + .I1(first_mi_word), + .I2(dout[0]), + .O(next_length_counter)); + (* SOFT_HLUTNM = "soft_lutpair59" *) + LUT5 #( + .INIT(32'hCCA533A5)) + \length_counter_1[1]_i_1 + (.I0(length_counter_1_reg[0]), + .I1(dout[0]), + .I2(length_counter_1_reg[1]), + .I3(first_mi_word), + .I4(dout[1]), + .O(\length_counter_1[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFAFAFC030505FC03)) + \length_counter_1[2]_i_1 + (.I0(dout[1]), + .I1(length_counter_1_reg[1]), + .I2(length_counter), + .I3(length_counter_1_reg[2]), + .I4(first_mi_word), + .I5(dout[2]), + .O(\length_counter_1[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair59" *) LUT3 #( - .INIT(8'h7F)) - \size_mask_q[6]_i_1 - (.I0(s_axi_arsize[2]), - .I1(s_axi_arsize[0]), - .I2(s_axi_arsize[1]), - .O(size_mask[6])); - FDRE \size_mask_q_reg[0] - (.C(aclk), - .CE(E), - .D(size_mask[0]), - .Q(size_mask_q[0]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \size_mask_q_reg[1] - (.C(aclk), - .CE(E), - .D(size_mask[1]), - .Q(size_mask_q[1]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \size_mask_q_reg[2] + .INIT(8'hB8)) + \length_counter_1[2]_i_2 + (.I0(dout[0]), + .I1(first_mi_word), + .I2(length_counter_1_reg[0]), + .O(length_counter)); + LUT6 #( + .INIT(64'hFAFAFC030505FC03)) + \length_counter_1[3]_i_1 + (.I0(dout[2]), + .I1(length_counter_1_reg[2]), + .I2(\length_counter_1[3]_i_2_n_0 ), + .I3(length_counter_1_reg[3]), + .I4(first_mi_word), + .I5(dout[3]), + .O(\length_counter_1[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair58" *) + LUT5 #( + .INIT(32'hFFFACCFA)) + \length_counter_1[3]_i_2 + (.I0(length_counter_1_reg[0]), + .I1(dout[0]), + .I2(length_counter_1_reg[1]), + .I3(first_mi_word), + .I4(dout[1]), + .O(\length_counter_1[3]_i_2_n_0 )); + LUT5 #( + .INIT(32'h05FC0503)) + \length_counter_1[4]_i_1 + (.I0(dout[3]), + .I1(length_counter_1_reg[3]), + .I2(\length_counter_1[5]_i_2_n_0 ), + .I3(first_mi_word), + .I4(length_counter_1_reg[4]), + .O(\length_counter_1[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0033FEFE00330101)) + \length_counter_1[5]_i_1 + (.I0(length_counter_1_reg[4]), + .I1(\length_counter_1[5]_i_2_n_0 ), + .I2(length_counter_1_reg[3]), + .I3(dout[3]), + .I4(first_mi_word), + .I5(length_counter_1_reg[5]), + .O(\length_counter_1[5]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFCFAFAFFFC)) + \length_counter_1[5]_i_2 + (.I0(dout[1]), + .I1(length_counter_1_reg[1]), + .I2(length_counter), + .I3(length_counter_1_reg[2]), + .I4(first_mi_word), + .I5(dout[2]), + .O(\length_counter_1[5]_i_2_n_0 )); + LUT5 #( + .INIT(32'h33FE3301)) + \length_counter_1[6]_i_1 + (.I0(length_counter_1_reg[5]), + .I1(\length_counter_1[7]_i_2_n_0 ), + .I2(length_counter_1_reg[4]), + .I3(first_mi_word), + .I4(length_counter_1_reg[6]), + .O(\length_counter_1[6]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0F0FFFFE0F0F0001)) + \length_counter_1[7]_i_1 + (.I0(length_counter_1_reg[6]), + .I1(length_counter_1_reg[4]), + .I2(\length_counter_1[7]_i_2_n_0 ), + .I3(length_counter_1_reg[5]), + .I4(first_mi_word), + .I5(length_counter_1_reg[7]), + .O(\length_counter_1[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFCFAFAFFFC)) + \length_counter_1[7]_i_2 + (.I0(dout[2]), + .I1(length_counter_1_reg[2]), + .I2(\length_counter_1[3]_i_2_n_0 ), + .I3(length_counter_1_reg[3]), + .I4(first_mi_word), + .I5(dout[3]), + .O(\length_counter_1[7]_i_2_n_0 )); + FDRE \length_counter_1_reg[0] (.C(aclk), - .CE(E), - .D(size_mask[2]), - .Q(size_mask_q[2]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \size_mask_q_reg[31] + .CE(empty_fwft_i_reg), + .D(next_length_counter), + .Q(length_counter_1_reg[0]), + .R(aresetn)); + FDRE \length_counter_1_reg[1] (.C(aclk), - .CE(E), - .D(1'b1), - .Q(size_mask_q[31]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \size_mask_q_reg[3] + .CE(empty_fwft_i_reg), + .D(\length_counter_1[1]_i_1_n_0 ), + .Q(length_counter_1_reg[1]), + .R(aresetn)); + FDRE \length_counter_1_reg[2] (.C(aclk), - .CE(E), - .D(size_mask[3]), - .Q(size_mask_q[3]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \size_mask_q_reg[4] + .CE(empty_fwft_i_reg), + .D(\length_counter_1[2]_i_1_n_0 ), + .Q(length_counter_1_reg[2]), + .R(aresetn)); + FDRE \length_counter_1_reg[3] (.C(aclk), - .CE(E), - .D(size_mask[4]), - .Q(size_mask_q[4]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \size_mask_q_reg[5] + .CE(empty_fwft_i_reg), + .D(\length_counter_1[3]_i_1_n_0 ), + .Q(length_counter_1_reg[3]), + .R(aresetn)); + FDRE \length_counter_1_reg[4] (.C(aclk), - .CE(E), - .D(size_mask[5]), - .Q(size_mask_q[5]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - FDRE \size_mask_q_reg[6] + .CE(empty_fwft_i_reg), + .D(\length_counter_1[4]_i_1_n_0 ), + .Q(length_counter_1_reg[4]), + .R(aresetn)); + FDRE \length_counter_1_reg[5] (.C(aclk), - .CE(E), - .D(size_mask[6]), - .Q(size_mask_q[6]), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair10" *) - LUT3 #( - .INIT(8'hEB)) - split_in_progress_i_2 - (.I0(cmd_empty), - .I1(M_AXI_ARID), - .I2(queue_id), - .O(split_in_progress_i_2_n_0)); - FDRE split_in_progress_reg + .CE(empty_fwft_i_reg), + .D(\length_counter_1[5]_i_1_n_0 ), + .Q(length_counter_1_reg[5]), + .R(aresetn)); + FDRE \length_counter_1_reg[6] + (.C(aclk), + .CE(empty_fwft_i_reg), + .D(\length_counter_1[6]_i_1_n_0 ), + .Q(length_counter_1_reg[6]), + .R(aresetn)); + FDRE \length_counter_1_reg[7] (.C(aclk), + .CE(empty_fwft_i_reg), + .D(\length_counter_1[7]_i_1_n_0 ), + .Q(length_counter_1_reg[7]), + .R(aresetn)); + LUT3 #( + .INIT(8'h80)) + m_axi_wlast_INST_0 + (.I0(m_axi_wlast_INST_0_i_1_n_0), + .I1(m_axi_wlast_INST_0_i_2_n_0), + .I2(m_axi_wlast_INST_0_i_3_n_0), + .O(m_axi_wlast)); + LUT5 #( + .INIT(32'hFF00FF01)) + m_axi_wlast_INST_0_i_1 + (.I0(length_counter_1_reg[6]), + .I1(length_counter_1_reg[7]), + .I2(length_counter_1_reg[5]), + .I3(first_mi_word), + .I4(length_counter_1_reg[4]), + .O(m_axi_wlast_INST_0_i_1_n_0)); + LUT5 #( + .INIT(32'h00053035)) + m_axi_wlast_INST_0_i_2 + (.I0(length_counter_1_reg[2]), + .I1(dout[2]), + .I2(first_mi_word), + .I3(length_counter_1_reg[3]), + .I4(dout[3]), + .O(m_axi_wlast_INST_0_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair58" *) + LUT5 #( + .INIT(32'h00053035)) + m_axi_wlast_INST_0_i_3 + (.I0(length_counter_1_reg[0]), + .I1(dout[0]), + .I2(first_mi_word), + .I3(length_counter_1_reg[1]), + .I4(dout[1]), + .O(m_axi_wlast_INST_0_i_3_n_0)); +endmodule + +module Arty_Z7_20_auto_pc_0_dmem + (dout_i, + clk, + EN, + din, + \gc0.count_d1_reg[4] , + I55, + \gpregsm1.curr_fwft_state_reg[1] ); + output [4:0]dout_i; + input clk; + input EN; + input [4:0]din; + input [4:0]\gc0.count_d1_reg[4] ; + input [4:0]I55; + input [0:0]\gpregsm1.curr_fwft_state_reg[1] ; + + wire EN; + wire [4:0]I55; + wire clk; + wire [4:0]din; + wire [4:0]dout_i; + wire [4:0]\gc0.count_d1_reg[4] ; + wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ; + wire [4:0]p_0_out; + wire [1:1]NLW_RAM_reg_0_31_0_4_DOC_UNCONNECTED; + wire [1:0]NLW_RAM_reg_0_31_0_4_DOD_UNCONNECTED; + + (* METHODOLOGY_DRC_VIOS = "" *) + RAM32M RAM_reg_0_31_0_4 + (.ADDRA(\gc0.count_d1_reg[4] ), + .ADDRB(\gc0.count_d1_reg[4] ), + .ADDRC(\gc0.count_d1_reg[4] ), + .ADDRD(I55), + .DIA(din[1:0]), + .DIB(din[3:2]), + .DIC({1'b0,din[4]}), + .DID({1'b0,1'b0}), + .DOA(p_0_out[1:0]), + .DOB(p_0_out[3:2]), + .DOC({NLW_RAM_reg_0_31_0_4_DOC_UNCONNECTED[1],p_0_out[4]}), + .DOD(NLW_RAM_reg_0_31_0_4_DOD_UNCONNECTED[1:0]), + .WCLK(clk), + .WE(EN)); + FDRE #( + .INIT(1'b0)) + \gpr1.dout_i_reg[0] + (.C(clk), + .CE(\gpregsm1.curr_fwft_state_reg[1] ), + .D(p_0_out[0]), + .Q(dout_i[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gpr1.dout_i_reg[1] + (.C(clk), + .CE(\gpregsm1.curr_fwft_state_reg[1] ), + .D(p_0_out[1]), + .Q(dout_i[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gpr1.dout_i_reg[2] + (.C(clk), + .CE(\gpregsm1.curr_fwft_state_reg[1] ), + .D(p_0_out[2]), + .Q(dout_i[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gpr1.dout_i_reg[3] + (.C(clk), + .CE(\gpregsm1.curr_fwft_state_reg[1] ), + .D(p_0_out[3]), + .Q(dout_i[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gpr1.dout_i_reg[4] + (.C(clk), + .CE(\gpregsm1.curr_fwft_state_reg[1] ), + .D(p_0_out[4]), + .Q(dout_i[4]), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "dmem" *) +module Arty_Z7_20_auto_pc_0_dmem_20 + (dout_i, + clk, + EN, + din, + \gc0.count_d1_reg[4] , + I54, + \gpregsm1.curr_fwft_state_reg[1] ); + output [4:0]dout_i; + input clk; + input EN; + input [4:0]din; + input [4:0]\gc0.count_d1_reg[4] ; + input [4:0]I54; + input [0:0]\gpregsm1.curr_fwft_state_reg[1] ; + + wire EN; + wire [4:0]I54; + wire clk; + wire [4:0]din; + wire [4:0]dout_i; + wire [4:0]\gc0.count_d1_reg[4] ; + wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ; + wire [4:0]p_0_out; + wire [1:1]NLW_RAM_reg_0_31_0_4_DOC_UNCONNECTED; + wire [1:0]NLW_RAM_reg_0_31_0_4_DOD_UNCONNECTED; + + (* METHODOLOGY_DRC_VIOS = "" *) + RAM32M RAM_reg_0_31_0_4 + (.ADDRA(\gc0.count_d1_reg[4] ), + .ADDRB(\gc0.count_d1_reg[4] ), + .ADDRC(\gc0.count_d1_reg[4] ), + .ADDRD(I54), + .DIA(din[1:0]), + .DIB(din[3:2]), + .DIC({1'b0,din[4]}), + .DID({1'b0,1'b0}), + .DOA(p_0_out[1:0]), + .DOB(p_0_out[3:2]), + .DOC({NLW_RAM_reg_0_31_0_4_DOC_UNCONNECTED[1],p_0_out[4]}), + .DOD(NLW_RAM_reg_0_31_0_4_DOD_UNCONNECTED[1:0]), + .WCLK(clk), + .WE(EN)); + FDRE #( + .INIT(1'b0)) + \gpr1.dout_i_reg[0] + (.C(clk), + .CE(\gpregsm1.curr_fwft_state_reg[1] ), + .D(p_0_out[0]), + .Q(dout_i[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gpr1.dout_i_reg[1] + (.C(clk), + .CE(\gpregsm1.curr_fwft_state_reg[1] ), + .D(p_0_out[1]), + .Q(dout_i[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gpr1.dout_i_reg[2] + (.C(clk), + .CE(\gpregsm1.curr_fwft_state_reg[1] ), + .D(p_0_out[2]), + .Q(dout_i[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gpr1.dout_i_reg[3] + (.C(clk), + .CE(\gpregsm1.curr_fwft_state_reg[1] ), + .D(p_0_out[3]), + .Q(dout_i[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gpr1.dout_i_reg[4] + (.C(clk), + .CE(\gpregsm1.curr_fwft_state_reg[1] ), + .D(p_0_out[4]), + .Q(dout_i[4]), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "dmem" *) +module Arty_Z7_20_auto_pc_0_dmem__parameterized0 + (p_0_out, + dout_i, + \goreg_dm.dout_i_reg[0] , + clk, + din, + E, + Q, + \gc0.count_d1_reg[4] , + \gpregsm1.curr_fwft_state_reg[1] , + out, + \gpregsm1.curr_fwft_state_reg[1]_0 , + rd_en, + dout); + output p_0_out; + output dout_i; + output \goreg_dm.dout_i_reg[0] ; + input clk; + input [0:0]din; + input [0:0]E; + input [4:0]Q; + input [4:0]\gc0.count_d1_reg[4] ; + input \gpregsm1.curr_fwft_state_reg[1] ; + input [0:0]out; + input [1:0]\gpregsm1.curr_fwft_state_reg[1]_0 ; + input rd_en; + input [0:0]dout; + + wire [0:0]E; + wire [4:0]Q; + wire clk; + wire [0:0]din; + wire [0:0]dout; + wire dout_i; + wire [4:0]\gc0.count_d1_reg[4] ; + wire \goreg_dm.dout_i_reg[0] ; + wire \gpregsm1.curr_fwft_state_reg[1] ; + wire [1:0]\gpregsm1.curr_fwft_state_reg[1]_0 ; + wire [0:0]out; + wire p_0_out; + wire rd_en; + wire NLW_RAM_reg_0_31_0_0_SPO_UNCONNECTED; + + RAM32X1D RAM_reg_0_31_0_0 + (.A0(Q[0]), + .A1(Q[1]), + .A2(Q[2]), + .A3(Q[3]), + .A4(Q[4]), + .D(din), + .DPO(p_0_out), + .DPRA0(\gc0.count_d1_reg[4] [0]), + .DPRA1(\gc0.count_d1_reg[4] [1]), + .DPRA2(\gc0.count_d1_reg[4] [2]), + .DPRA3(\gc0.count_d1_reg[4] [3]), + .DPRA4(\gc0.count_d1_reg[4] [4]), + .SPO(NLW_RAM_reg_0_31_0_0_SPO_UNCONNECTED), + .WCLK(clk), + .WE(E)); + LUT6 #( + .INIT(64'hEFEFFFEF20200020)) + \goreg_dm.dout_i[0]_i_1 + (.I0(dout_i), + .I1(out), + .I2(\gpregsm1.curr_fwft_state_reg[1]_0 [1]), + .I3(\gpregsm1.curr_fwft_state_reg[1]_0 [0]), + .I4(rd_en), + .I5(dout), + .O(\goreg_dm.dout_i_reg[0] )); + FDRE #( + .INIT(1'b0)) + \gpr1.dout_i_reg[0] + (.C(clk), .CE(1'b1), - .D(\USE_R_CHANNEL.cmd_queue_n_21 ), - .Q(split_in_progress_reg_n_0), + .D(\gpregsm1.curr_fwft_state_reg[1] ), + .Q(dout_i), .R(1'b0)); - FDRE split_ongoing_reg - (.C(aclk), - .CE(pushed_new_cmd), - .D(\USE_R_CHANNEL.cmd_queue_n_1 ), - .Q(split_ongoing), - .R(\USE_R_CHANNEL.cmd_queue_n_0 )); endmodule -module Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi3_conv - (s_axi_arready, - M_AXI_ARID, - m_axi_arsize, - m_axi_arburst, - m_axi_arcache, - m_axi_arprot, - m_axi_arqos, - m_axi_araddr, - m_axi_arvalid, - s_axi_rvalid, - m_axi_arlen, - m_axi_arlock, - s_axi_rlast, - m_axi_rready, - s_axi_arsize, - s_axi_arlen, - aclk, +module Arty_Z7_20_auto_pc_0_fifo_generator_ramfifo + (empty, + full, + dout, + clk, + rst, + din, + rd_en, + wr_en); + output empty; + output full; + output [4:0]dout; + input clk; + input rst; + input [4:0]din; + input rd_en; + input wr_en; + + wire clk; + wire [4:0]din; + wire [4:0]dout; + wire empty; + wire full; + wire \gntv_or_sync_fifo.gl0.rd_n_12 ; + wire \gntv_or_sync_fifo.gl0.rd_n_4 ; + wire \gntv_or_sync_fifo.gl0.rd_n_6 ; + wire \gntv_or_sync_fifo.gl0.wr_n_0 ; + wire \gntv_or_sync_fifo.gl0.wr_n_3 ; + wire [4:0]p_0_out_0; + wire [4:0]p_11_out; + wire p_17_out; + wire ram_rd_en_i; + wire rd_en; + wire [2:0]rd_pntr_plus1; + wire [2:0]rd_rst_i; + wire rst; + wire rst_full_ff_i; + wire wr_en; + wire [1:1]wr_rst_i; + + Arty_Z7_20_auto_pc_0_rd_logic \gntv_or_sync_fifo.gl0.rd + (.E(ram_rd_en_i), + .Q(rd_pntr_plus1), + .clk(clk), + .empty(empty), + .\gcc0.gc0.count_d1_reg[2] (\gntv_or_sync_fifo.gl0.wr_n_3 ), + .\gcc0.gc0.count_d1_reg[4] (p_11_out), + .\goreg_dm.dout_i_reg[4] (\gntv_or_sync_fifo.gl0.rd_n_6 ), + .\gpr1.dout_i_reg[1] (p_0_out_0), + .out({rd_rst_i[2],rd_rst_i[0]}), + .ram_empty_fb_i_reg(\gntv_or_sync_fifo.gl0.rd_n_4 ), + .ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.rd_n_12 ), + .ram_full_fb_i_reg_0(\gntv_or_sync_fifo.gl0.wr_n_0 ), + .rd_en(rd_en), + .wr_en(wr_en)); + Arty_Z7_20_auto_pc_0_wr_logic \gntv_or_sync_fifo.gl0.wr + (.E(p_17_out), + .Q(p_11_out), + .clk(clk), + .full(full), + .\gc0.count_d1_reg[2] (\gntv_or_sync_fifo.gl0.rd_n_4 ), + .\gc0.count_d1_reg[4] (p_0_out_0), + .\gc0.count_reg[2] (rd_pntr_plus1), + .\gpregsm1.curr_fwft_state_reg[0] (\gntv_or_sync_fifo.gl0.rd_n_12 ), + .\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ({wr_rst_i,rst_full_ff_i}), + .out(\gntv_or_sync_fifo.gl0.wr_n_0 ), + .ram_empty_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_3 ), + .wr_en(wr_en)); + Arty_Z7_20_auto_pc_0_memory \gntv_or_sync_fifo.mem + (.E(\gntv_or_sync_fifo.gl0.rd_n_6 ), + .EN(p_17_out), + .I55(p_11_out), + .clk(clk), + .din(din), + .dout(dout), + .\gc0.count_d1_reg[4] (p_0_out_0), + .\gpregsm1.curr_fwft_state_reg[1] (ram_rd_en_i)); + Arty_Z7_20_auto_pc_0_reset_blk_ramfifo rstblk + (.clk(clk), + .\gc0.count_reg[1] ({rd_rst_i[2],rd_rst_i[0]}), + .out({wr_rst_i,rst_full_ff_i}), + .rst(rst)); +endmodule + +(* ORIG_REF_NAME = "fifo_generator_ramfifo" *) +module Arty_Z7_20_auto_pc_0_fifo_generator_ramfifo_9 + (empty, + full, + dout, + clk, + rst, + din, + rd_en, + wr_en); + output empty; + output full; + output [4:0]dout; + input clk; + input rst; + input [4:0]din; + input rd_en; + input wr_en; + + wire clk; + wire [4:0]din; + wire [4:0]dout; + wire empty; + wire full; + wire \gntv_or_sync_fifo.gl0.rd_n_12 ; + wire \gntv_or_sync_fifo.gl0.rd_n_4 ; + wire \gntv_or_sync_fifo.gl0.rd_n_6 ; + wire \gntv_or_sync_fifo.gl0.wr_n_0 ; + wire \gntv_or_sync_fifo.gl0.wr_n_3 ; + wire [4:0]p_0_out_0; + wire [4:0]p_11_out; + wire p_17_out; + wire ram_rd_en_i; + wire rd_en; + wire [2:0]rd_pntr_plus1; + wire [2:0]rd_rst_i; + wire rst; + wire rst_full_ff_i; + wire wr_en; + wire [1:1]wr_rst_i; + + Arty_Z7_20_auto_pc_0_rd_logic_10 \gntv_or_sync_fifo.gl0.rd + (.E(ram_rd_en_i), + .Q(rd_pntr_plus1), + .clk(clk), + .empty(empty), + .\gcc0.gc0.count_d1_reg[2] (\gntv_or_sync_fifo.gl0.wr_n_3 ), + .\gcc0.gc0.count_d1_reg[4] (p_11_out), + .\goreg_dm.dout_i_reg[4] (\gntv_or_sync_fifo.gl0.rd_n_6 ), + .\gpr1.dout_i_reg[1] (p_0_out_0), + .out({rd_rst_i[2],rd_rst_i[0]}), + .ram_empty_fb_i_reg(\gntv_or_sync_fifo.gl0.rd_n_4 ), + .ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.rd_n_12 ), + .ram_full_fb_i_reg_0(\gntv_or_sync_fifo.gl0.wr_n_0 ), + .rd_en(rd_en), + .wr_en(wr_en)); + Arty_Z7_20_auto_pc_0_wr_logic_11 \gntv_or_sync_fifo.gl0.wr + (.E(p_17_out), + .Q(p_11_out), + .clk(clk), + .full(full), + .\gc0.count_d1_reg[2] (\gntv_or_sync_fifo.gl0.rd_n_4 ), + .\gc0.count_d1_reg[4] (p_0_out_0), + .\gc0.count_reg[2] (rd_pntr_plus1), + .\gpregsm1.curr_fwft_state_reg[0] (\gntv_or_sync_fifo.gl0.rd_n_12 ), + .\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ({wr_rst_i,rst_full_ff_i}), + .out(\gntv_or_sync_fifo.gl0.wr_n_0 ), + .ram_empty_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_3 ), + .wr_en(wr_en)); + Arty_Z7_20_auto_pc_0_memory_12 \gntv_or_sync_fifo.mem + (.E(\gntv_or_sync_fifo.gl0.rd_n_6 ), + .EN(p_17_out), + .I54(p_11_out), + .clk(clk), + .din(din), + .dout(dout), + .\gc0.count_d1_reg[4] (p_0_out_0), + .\gpregsm1.curr_fwft_state_reg[1] (ram_rd_en_i)); + Arty_Z7_20_auto_pc_0_reset_blk_ramfifo_13 rstblk + (.clk(clk), + .\gc0.count_reg[1] ({rd_rst_i[2],rd_rst_i[0]}), + .out({wr_rst_i,rst_full_ff_i}), + .rst(rst)); +endmodule + +(* ORIG_REF_NAME = "fifo_generator_ramfifo" *) +module Arty_Z7_20_auto_pc_0_fifo_generator_ramfifo__parameterized0 + (empty, + full, + dout, + clk, + rst, + din, + rd_en, + wr_en); + output empty; + output full; + output [0:0]dout; + input clk; + input rst; + input [0:0]din; + input rd_en; + input wr_en; + + wire clk; + wire [0:0]din; + wire [0:0]dout; + wire dout_i; + wire empty; + wire full; + wire \gntv_or_sync_fifo.gl0.rd_n_0 ; + wire \gntv_or_sync_fifo.gl0.rd_n_13 ; + wire \gntv_or_sync_fifo.gl0.rd_n_3 ; + wire \gntv_or_sync_fifo.gl0.rd_n_7 ; + wire \gntv_or_sync_fifo.gl0.wr_n_0 ; + wire \gntv_or_sync_fifo.gl0.wr_n_3 ; + wire [0:0]\gr1.gr1_int.rfwft/p_0_in ; + wire p_0_out; + wire [4:0]p_0_out_0; + wire [4:0]p_11_out; + wire p_17_out; + wire rd_en; + wire [2:0]rd_pntr_plus1; + wire [2:0]rd_rst_i; + wire rst; + wire rst_full_ff_i; + wire wr_en; + wire [1:1]wr_rst_i; + + Arty_Z7_20_auto_pc_0_rd_logic_26 \gntv_or_sync_fifo.gl0.rd + (.AR(rd_rst_i[2]), + .Q(rd_pntr_plus1), + .clk(clk), + .dout_i(dout_i), + .empty(empty), + .\gcc0.gc0.count_d1_reg[2] (\gntv_or_sync_fifo.gl0.wr_n_3 ), + .\gcc0.gc0.count_d1_reg[4] (p_11_out), + .\gpr1.dout_i_reg[0] (\gntv_or_sync_fifo.gl0.rd_n_3 ), + .\gpr1.dout_i_reg[0]_0 (p_0_out_0), + .out({\gntv_or_sync_fifo.gl0.rd_n_0 ,\gr1.gr1_int.rfwft/p_0_in }), + .p_0_out(p_0_out), + .ram_empty_fb_i_reg(\gntv_or_sync_fifo.gl0.rd_n_7 ), + .ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.rd_n_13 ), + .ram_full_fb_i_reg_0(\gntv_or_sync_fifo.gl0.wr_n_0 ), + .rd_en(rd_en), + .wr_en(wr_en)); + Arty_Z7_20_auto_pc_0_wr_logic_27 \gntv_or_sync_fifo.gl0.wr + (.E(p_17_out), + .Q(p_11_out), + .clk(clk), + .full(full), + .\gc0.count_d1_reg[2] (\gntv_or_sync_fifo.gl0.rd_n_7 ), + .\gc0.count_d1_reg[4] (p_0_out_0), + .\gc0.count_reg[2] (rd_pntr_plus1), + .\gpregsm1.curr_fwft_state_reg[0] (\gntv_or_sync_fifo.gl0.rd_n_13 ), + .\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ({wr_rst_i,rst_full_ff_i}), + .out(\gntv_or_sync_fifo.gl0.wr_n_0 ), + .ram_empty_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_3 ), + .wr_en(wr_en)); + Arty_Z7_20_auto_pc_0_memory__parameterized0 \gntv_or_sync_fifo.mem + (.E(p_17_out), + .Q(p_11_out), + .clk(clk), + .din(din), + .dout(dout), + .dout_i(dout_i), + .\gc0.count_d1_reg[4] (p_0_out_0), + .\gpregsm1.curr_fwft_state_reg[1] (\gntv_or_sync_fifo.gl0.rd_n_3 ), + .\gpregsm1.curr_fwft_state_reg[1]_0 ({\gntv_or_sync_fifo.gl0.rd_n_0 ,\gr1.gr1_int.rfwft/p_0_in }), + .out(rd_rst_i[0]), + .p_0_out(p_0_out), + .rd_en(rd_en)); + Arty_Z7_20_auto_pc_0_reset_blk_ramfifo_28 rstblk + (.clk(clk), + .\gc0.count_reg[1] ({rd_rst_i[2],rd_rst_i[0]}), + .out({wr_rst_i,rst_full_ff_i}), + .rst(rst)); +endmodule + +module Arty_Z7_20_auto_pc_0_fifo_generator_top + (empty, + full, + dout, + clk, + rst, + din, + rd_en, + wr_en); + output empty; + output full; + output [4:0]dout; + input clk; + input rst; + input [4:0]din; + input rd_en; + input wr_en; + + wire clk; + wire [4:0]din; + wire [4:0]dout; + wire empty; + wire full; + wire rd_en; + wire rst; + wire wr_en; + + Arty_Z7_20_auto_pc_0_fifo_generator_ramfifo \grf.rf + (.clk(clk), + .din(din), + .dout(dout), + .empty(empty), + .full(full), + .rd_en(rd_en), + .rst(rst), + .wr_en(wr_en)); +endmodule + +(* ORIG_REF_NAME = "fifo_generator_top" *) +module Arty_Z7_20_auto_pc_0_fifo_generator_top_8 + (empty, + full, + dout, + clk, + rst, + din, + rd_en, + wr_en); + output empty; + output full; + output [4:0]dout; + input clk; + input rst; + input [4:0]din; + input rd_en; + input wr_en; + + wire clk; + wire [4:0]din; + wire [4:0]dout; + wire empty; + wire full; + wire rd_en; + wire rst; + wire wr_en; + + Arty_Z7_20_auto_pc_0_fifo_generator_ramfifo_9 \grf.rf + (.clk(clk), + .din(din), + .dout(dout), + .empty(empty), + .full(full), + .rd_en(rd_en), + .rst(rst), + .wr_en(wr_en)); +endmodule + +(* ORIG_REF_NAME = "fifo_generator_top" *) +module Arty_Z7_20_auto_pc_0_fifo_generator_top__parameterized0 + (empty, + full, + dout, + clk, + rst, + din, + rd_en, + wr_en); + output empty; + output full; + output [0:0]dout; + input clk; + input rst; + input [0:0]din; + input rd_en; + input wr_en; + + wire clk; + wire [0:0]din; + wire [0:0]dout; + wire empty; + wire full; + wire rd_en; + wire rst; + wire wr_en; + + Arty_Z7_20_auto_pc_0_fifo_generator_ramfifo__parameterized0 \grf.rf + (.clk(clk), + .din(din), + .dout(dout), + .empty(empty), + .full(full), + .rd_en(rd_en), + .rst(rst), + .wr_en(wr_en)); +endmodule + +(* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *) +(* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *) +(* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "64" *) (* C_AXIS_TDEST_WIDTH = "4" *) +(* C_AXIS_TID_WIDTH = "8" *) (* C_AXIS_TKEEP_WIDTH = "4" *) (* C_AXIS_TSTRB_WIDTH = "4" *) +(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *) +(* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *) +(* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "4" *) (* C_AXI_LEN_WIDTH = "8" *) +(* C_AXI_LOCK_WIDTH = "2" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "0" *) +(* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "1" *) (* C_COUNT_TYPE = "0" *) +(* C_DATA_COUNT_WIDTH = "6" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "5" *) +(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *) +(* C_DIN_WIDTH_WACH = "32" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *) +(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "5" *) (* C_ENABLE_RLOCS = "0" *) +(* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *) +(* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) +(* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) +(* C_FAMILY = "zynq" *) (* C_FULL_FLAGS_RST_VAL = "0" *) (* C_HAS_ALMOST_EMPTY = "0" *) +(* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "0" *) (* C_HAS_AXIS_TDEST = "0" *) +(* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *) +(* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "0" *) +(* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *) +(* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_RD_CHANNEL = "0" *) (* C_HAS_AXI_RUSER = "0" *) +(* C_HAS_AXI_WR_CHANNEL = "0" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *) +(* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *) +(* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *) +(* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *) +(* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *) +(* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *) +(* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *) +(* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *) (* C_HAS_SLAVE_CE = "0" *) +(* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *) +(* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *) +(* C_IMPLEMENTATION_TYPE = "0" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *) +(* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) +(* C_IMPLEMENTATION_TYPE_WRCH = "1" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *) +(* C_MEMORY_TYPE = "2" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *) +(* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *) +(* C_PRELOAD_LATENCY = "0" *) (* C_PRELOAD_REGS = "1" *) (* C_PRIM_FIFO_TYPE = "512x36" *) +(* C_PRIM_FIFO_TYPE_AXIS = "512x36" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "512x36" *) +(* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "512x36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) +(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "4" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) +(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) +(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "5" *) (* C_PROG_EMPTY_TYPE = "0" *) +(* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *) +(* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *) +(* C_PROG_FULL_THRESH_ASSERT_VAL = "31" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) +(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) +(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "30" *) (* C_PROG_FULL_TYPE = "0" *) +(* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *) +(* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *) +(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "6" *) +(* C_RD_DEPTH = "32" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "5" *) +(* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *) +(* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *) +(* C_SELECT_XPM = "0" *) (* C_SYNCHRONIZER_STAGE = "3" *) (* C_UNDERFLOW_LOW = "0" *) +(* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *) +(* C_USE_DOUT_RST = "0" *) (* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *) +(* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *) +(* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *) +(* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "1" *) (* C_USE_PIPELINE_REG = "0" *) +(* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *) +(* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "6" *) +(* C_WR_DEPTH = "32" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *) +(* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *) +(* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "5" *) +(* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *) +(* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *) +(* C_WR_RESPONSE_LATENCY = "1" *) +module Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 + (backup, + backup_marker, + clk, + rst, + srst, + wr_clk, + wr_rst, + rd_clk, + rd_rst, + din, + wr_en, + rd_en, + prog_empty_thresh, + prog_empty_thresh_assert, + prog_empty_thresh_negate, + prog_full_thresh, + prog_full_thresh_assert, + prog_full_thresh_negate, + int_clk, + injectdbiterr, + injectsbiterr, + sleep, + dout, + full, + almost_full, + wr_ack, + overflow, + empty, + almost_empty, + valid, + underflow, + data_count, + rd_data_count, + wr_data_count, + prog_full, + prog_empty, + sbiterr, + dbiterr, + wr_rst_busy, + rd_rst_busy, + m_aclk, + s_aclk, + s_aresetn, + m_aclk_en, + s_aclk_en, + s_axi_awid, + s_axi_awaddr, + s_axi_awlen, + s_axi_awsize, + s_axi_awburst, + s_axi_awlock, + s_axi_awcache, + s_axi_awprot, + s_axi_awqos, + s_axi_awregion, + s_axi_awuser, + s_axi_awvalid, + s_axi_awready, + s_axi_wid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wlast, + s_axi_wuser, + s_axi_wvalid, + s_axi_wready, + s_axi_bid, + s_axi_bresp, + s_axi_buser, + s_axi_bvalid, + s_axi_bready, + m_axi_awid, + m_axi_awaddr, + m_axi_awlen, + m_axi_awsize, + m_axi_awburst, + m_axi_awlock, + m_axi_awcache, + m_axi_awprot, + m_axi_awqos, + m_axi_awregion, + m_axi_awuser, + m_axi_awvalid, + m_axi_awready, + m_axi_wid, + m_axi_wdata, + m_axi_wstrb, + m_axi_wlast, + m_axi_wuser, + m_axi_wvalid, + m_axi_wready, + m_axi_bid, + m_axi_bresp, + m_axi_buser, + m_axi_bvalid, + m_axi_bready, s_axi_arid, s_axi_araddr, + s_axi_arlen, + s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arqos, + s_axi_arregion, + s_axi_aruser, + s_axi_arvalid, + s_axi_arready, + s_axi_rid, + s_axi_rdata, + s_axi_rresp, + s_axi_rlast, + s_axi_ruser, + s_axi_rvalid, + s_axi_rready, + m_axi_arid, + m_axi_araddr, + m_axi_arlen, + m_axi_arsize, + m_axi_arburst, + m_axi_arlock, + m_axi_arcache, + m_axi_arprot, + m_axi_arqos, + m_axi_arregion, + m_axi_aruser, + m_axi_arvalid, m_axi_arready, + m_axi_rid, + m_axi_rdata, + m_axi_rresp, m_axi_rlast, - s_axi_rready, + m_axi_ruser, m_axi_rvalid, - aresetn, - s_axi_arvalid); + m_axi_rready, + s_axis_tvalid, + s_axis_tready, + s_axis_tdata, + s_axis_tstrb, + s_axis_tkeep, + s_axis_tlast, + s_axis_tid, + s_axis_tdest, + s_axis_tuser, + m_axis_tvalid, + m_axis_tready, + m_axis_tdata, + m_axis_tstrb, + m_axis_tkeep, + m_axis_tlast, + m_axis_tid, + m_axis_tdest, + m_axis_tuser, + axi_aw_injectsbiterr, + axi_aw_injectdbiterr, + axi_aw_prog_full_thresh, + axi_aw_prog_empty_thresh, + axi_aw_data_count, + axi_aw_wr_data_count, + axi_aw_rd_data_count, + axi_aw_sbiterr, + axi_aw_dbiterr, + axi_aw_overflow, + axi_aw_underflow, + axi_aw_prog_full, + axi_aw_prog_empty, + axi_w_injectsbiterr, + axi_w_injectdbiterr, + axi_w_prog_full_thresh, + axi_w_prog_empty_thresh, + axi_w_data_count, + axi_w_wr_data_count, + axi_w_rd_data_count, + axi_w_sbiterr, + axi_w_dbiterr, + axi_w_overflow, + axi_w_underflow, + axi_w_prog_full, + axi_w_prog_empty, + axi_b_injectsbiterr, + axi_b_injectdbiterr, + axi_b_prog_full_thresh, + axi_b_prog_empty_thresh, + axi_b_data_count, + axi_b_wr_data_count, + axi_b_rd_data_count, + axi_b_sbiterr, + axi_b_dbiterr, + axi_b_overflow, + axi_b_underflow, + axi_b_prog_full, + axi_b_prog_empty, + axi_ar_injectsbiterr, + axi_ar_injectdbiterr, + axi_ar_prog_full_thresh, + axi_ar_prog_empty_thresh, + axi_ar_data_count, + axi_ar_wr_data_count, + axi_ar_rd_data_count, + axi_ar_sbiterr, + axi_ar_dbiterr, + axi_ar_overflow, + axi_ar_underflow, + axi_ar_prog_full, + axi_ar_prog_empty, + axi_r_injectsbiterr, + axi_r_injectdbiterr, + axi_r_prog_full_thresh, + axi_r_prog_empty_thresh, + axi_r_data_count, + axi_r_wr_data_count, + axi_r_rd_data_count, + axi_r_sbiterr, + axi_r_dbiterr, + axi_r_overflow, + axi_r_underflow, + axi_r_prog_full, + axi_r_prog_empty, + axis_injectsbiterr, + axis_injectdbiterr, + axis_prog_full_thresh, + axis_prog_empty_thresh, + axis_data_count, + axis_wr_data_count, + axis_rd_data_count, + axis_sbiterr, + axis_dbiterr, + axis_overflow, + axis_underflow, + axis_prog_full, + axis_prog_empty); + input backup; + input backup_marker; + input clk; + input rst; + input srst; + input wr_clk; + input wr_rst; + input rd_clk; + input rd_rst; + input [4:0]din; + input wr_en; + input rd_en; + input [4:0]prog_empty_thresh; + input [4:0]prog_empty_thresh_assert; + input [4:0]prog_empty_thresh_negate; + input [4:0]prog_full_thresh; + input [4:0]prog_full_thresh_assert; + input [4:0]prog_full_thresh_negate; + input int_clk; + input injectdbiterr; + input injectsbiterr; + input sleep; + output [4:0]dout; + output full; + output almost_full; + output wr_ack; + output overflow; + output empty; + output almost_empty; + output valid; + output underflow; + output [5:0]data_count; + output [5:0]rd_data_count; + output [5:0]wr_data_count; + output prog_full; + output prog_empty; + output sbiterr; + output dbiterr; + output wr_rst_busy; + output rd_rst_busy; + input m_aclk; + input s_aclk; + input s_aresetn; + input m_aclk_en; + input s_aclk_en; + input [3:0]s_axi_awid; + input [31:0]s_axi_awaddr; + input [7:0]s_axi_awlen; + input [2:0]s_axi_awsize; + input [1:0]s_axi_awburst; + input [1:0]s_axi_awlock; + input [3:0]s_axi_awcache; + input [2:0]s_axi_awprot; + input [3:0]s_axi_awqos; + input [3:0]s_axi_awregion; + input [0:0]s_axi_awuser; + input s_axi_awvalid; + output s_axi_awready; + input [3:0]s_axi_wid; + input [63:0]s_axi_wdata; + input [7:0]s_axi_wstrb; + input s_axi_wlast; + input [0:0]s_axi_wuser; + input s_axi_wvalid; + output s_axi_wready; + output [3:0]s_axi_bid; + output [1:0]s_axi_bresp; + output [0:0]s_axi_buser; + output s_axi_bvalid; + input s_axi_bready; + output [3:0]m_axi_awid; + output [31:0]m_axi_awaddr; + output [7:0]m_axi_awlen; + output [2:0]m_axi_awsize; + output [1:0]m_axi_awburst; + output [1:0]m_axi_awlock; + output [3:0]m_axi_awcache; + output [2:0]m_axi_awprot; + output [3:0]m_axi_awqos; + output [3:0]m_axi_awregion; + output [0:0]m_axi_awuser; + output m_axi_awvalid; + input m_axi_awready; + output [3:0]m_axi_wid; + output [63:0]m_axi_wdata; + output [7:0]m_axi_wstrb; + output m_axi_wlast; + output [0:0]m_axi_wuser; + output m_axi_wvalid; + input m_axi_wready; + input [3:0]m_axi_bid; + input [1:0]m_axi_bresp; + input [0:0]m_axi_buser; + input m_axi_bvalid; + output m_axi_bready; + input [3:0]s_axi_arid; + input [31:0]s_axi_araddr; + input [7:0]s_axi_arlen; + input [2:0]s_axi_arsize; + input [1:0]s_axi_arburst; + input [1:0]s_axi_arlock; + input [3:0]s_axi_arcache; + input [2:0]s_axi_arprot; + input [3:0]s_axi_arqos; + input [3:0]s_axi_arregion; + input [0:0]s_axi_aruser; + input s_axi_arvalid; output s_axi_arready; - output [0:0]M_AXI_ARID; + output [3:0]s_axi_rid; + output [63:0]s_axi_rdata; + output [1:0]s_axi_rresp; + output s_axi_rlast; + output [0:0]s_axi_ruser; + output s_axi_rvalid; + input s_axi_rready; + output [3:0]m_axi_arid; + output [31:0]m_axi_araddr; + output [7:0]m_axi_arlen; output [2:0]m_axi_arsize; output [1:0]m_axi_arburst; + output [1:0]m_axi_arlock; output [3:0]m_axi_arcache; output [2:0]m_axi_arprot; output [3:0]m_axi_arqos; - output [31:0]m_axi_araddr; + output [3:0]m_axi_arregion; + output [0:0]m_axi_aruser; output m_axi_arvalid; - output s_axi_rvalid; - output [3:0]m_axi_arlen; - output [0:0]m_axi_arlock; - output s_axi_rlast; - output m_axi_rready; - input [2:0]s_axi_arsize; - input [7:0]s_axi_arlen; - input aclk; - input [0:0]s_axi_arid; - input [31:0]s_axi_araddr; - input [1:0]s_axi_arburst; - input [0:0]s_axi_arlock; - input [3:0]s_axi_arcache; - input [2:0]s_axi_arprot; - input [3:0]s_axi_arqos; input m_axi_arready; + input [3:0]m_axi_rid; + input [63:0]m_axi_rdata; + input [1:0]m_axi_rresp; input m_axi_rlast; - input s_axi_rready; + input [0:0]m_axi_ruser; input m_axi_rvalid; - input aresetn; - input s_axi_arvalid; - - wire [0:0]M_AXI_ARID; - wire aclk; - wire aresetn; - wire [31:0]m_axi_araddr; - wire [1:0]m_axi_arburst; - wire [3:0]m_axi_arcache; - wire [3:0]m_axi_arlen; - wire [0:0]m_axi_arlock; - wire [2:0]m_axi_arprot; - wire [3:0]m_axi_arqos; - wire m_axi_arready; - wire [2:0]m_axi_arsize; - wire m_axi_arvalid; - wire m_axi_rlast; - wire m_axi_rready; - wire m_axi_rvalid; - wire [31:0]s_axi_araddr; - wire [1:0]s_axi_arburst; - wire [3:0]s_axi_arcache; - wire [0:0]s_axi_arid; - wire [7:0]s_axi_arlen; - wire [0:0]s_axi_arlock; - wire [2:0]s_axi_arprot; - wire [3:0]s_axi_arqos; - wire s_axi_arready; - wire [2:0]s_axi_arsize; - wire s_axi_arvalid; - wire s_axi_rlast; - wire s_axi_rready; - wire s_axi_rvalid; + output m_axi_rready; + input s_axis_tvalid; + output s_axis_tready; + input [63:0]s_axis_tdata; + input [3:0]s_axis_tstrb; + input [3:0]s_axis_tkeep; + input s_axis_tlast; + input [7:0]s_axis_tid; + input [3:0]s_axis_tdest; + input [3:0]s_axis_tuser; + output m_axis_tvalid; + input m_axis_tready; + output [63:0]m_axis_tdata; + output [3:0]m_axis_tstrb; + output [3:0]m_axis_tkeep; + output m_axis_tlast; + output [7:0]m_axis_tid; + output [3:0]m_axis_tdest; + output [3:0]m_axis_tuser; + input axi_aw_injectsbiterr; + input axi_aw_injectdbiterr; + input [3:0]axi_aw_prog_full_thresh; + input [3:0]axi_aw_prog_empty_thresh; + output [4:0]axi_aw_data_count; + output [4:0]axi_aw_wr_data_count; + output [4:0]axi_aw_rd_data_count; + output axi_aw_sbiterr; + output axi_aw_dbiterr; + output axi_aw_overflow; + output axi_aw_underflow; + output axi_aw_prog_full; + output axi_aw_prog_empty; + input axi_w_injectsbiterr; + input axi_w_injectdbiterr; + input [9:0]axi_w_prog_full_thresh; + input [9:0]axi_w_prog_empty_thresh; + output [10:0]axi_w_data_count; + output [10:0]axi_w_wr_data_count; + output [10:0]axi_w_rd_data_count; + output axi_w_sbiterr; + output axi_w_dbiterr; + output axi_w_overflow; + output axi_w_underflow; + output axi_w_prog_full; + output axi_w_prog_empty; + input axi_b_injectsbiterr; + input axi_b_injectdbiterr; + input [3:0]axi_b_prog_full_thresh; + input [3:0]axi_b_prog_empty_thresh; + output [4:0]axi_b_data_count; + output [4:0]axi_b_wr_data_count; + output [4:0]axi_b_rd_data_count; + output axi_b_sbiterr; + output axi_b_dbiterr; + output axi_b_overflow; + output axi_b_underflow; + output axi_b_prog_full; + output axi_b_prog_empty; + input axi_ar_injectsbiterr; + input axi_ar_injectdbiterr; + input [3:0]axi_ar_prog_full_thresh; + input [3:0]axi_ar_prog_empty_thresh; + output [4:0]axi_ar_data_count; + output [4:0]axi_ar_wr_data_count; + output [4:0]axi_ar_rd_data_count; + output axi_ar_sbiterr; + output axi_ar_dbiterr; + output axi_ar_overflow; + output axi_ar_underflow; + output axi_ar_prog_full; + output axi_ar_prog_empty; + input axi_r_injectsbiterr; + input axi_r_injectdbiterr; + input [9:0]axi_r_prog_full_thresh; + input [9:0]axi_r_prog_empty_thresh; + output [10:0]axi_r_data_count; + output [10:0]axi_r_wr_data_count; + output [10:0]axi_r_rd_data_count; + output axi_r_sbiterr; + output axi_r_dbiterr; + output axi_r_overflow; + output axi_r_underflow; + output axi_r_prog_full; + output axi_r_prog_empty; + input axis_injectsbiterr; + input axis_injectdbiterr; + input [9:0]axis_prog_full_thresh; + input [9:0]axis_prog_empty_thresh; + output [10:0]axis_data_count; + output [10:0]axis_wr_data_count; + output [10:0]axis_rd_data_count; + output axis_sbiterr; + output axis_dbiterr; + output axis_overflow; + output axis_underflow; + output axis_prog_full; + output axis_prog_empty; - Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_a_axi3_conv \USE_READ.USE_SPLIT_R.read_addr_inst - (.E(s_axi_arready), - .M_AXI_ARID(M_AXI_ARID), - .aclk(aclk), - .aresetn(aresetn), - .m_axi_araddr(m_axi_araddr), - .m_axi_arburst(m_axi_arburst), - .m_axi_arcache(m_axi_arcache), - .m_axi_arlen(m_axi_arlen), - .m_axi_arlock(m_axi_arlock), - .m_axi_arprot(m_axi_arprot), - .m_axi_arqos(m_axi_arqos), - .m_axi_arready(m_axi_arready), - .m_axi_arsize(m_axi_arsize), - .m_axi_arvalid(m_axi_arvalid), - .m_axi_rlast(m_axi_rlast), - .m_axi_rready(m_axi_rready), - .m_axi_rvalid(m_axi_rvalid), - .s_axi_araddr(s_axi_araddr), - .s_axi_arburst(s_axi_arburst), - .s_axi_arcache(s_axi_arcache), - .s_axi_arid(s_axi_arid), - .s_axi_arlen(s_axi_arlen), - .s_axi_arlock(s_axi_arlock), - .s_axi_arprot(s_axi_arprot), - .s_axi_arqos(s_axi_arqos), - .s_axi_arsize(s_axi_arsize), - .s_axi_arvalid(s_axi_arvalid), - .s_axi_rlast(s_axi_rlast), - .s_axi_rready(s_axi_rready), - .s_axi_rvalid(s_axi_rvalid)); + wire \ ; + wire clk; + wire [4:0]din; + wire [4:0]dout; + wire empty; + wire full; + wire rd_en; + wire rst; + wire wr_en; + + assign almost_empty = \ ; + assign almost_full = \ ; + assign axi_ar_data_count[4] = \ ; + assign axi_ar_data_count[3] = \ ; + assign axi_ar_data_count[2] = \ ; + assign axi_ar_data_count[1] = \ ; + assign axi_ar_data_count[0] = \ ; + assign axi_ar_dbiterr = \ ; + assign axi_ar_overflow = \ ; + assign axi_ar_prog_empty = \ ; + assign axi_ar_prog_full = \ ; + assign axi_ar_rd_data_count[4] = \ ; + assign axi_ar_rd_data_count[3] = \ ; + assign axi_ar_rd_data_count[2] = \ ; + assign axi_ar_rd_data_count[1] = \ ; + assign axi_ar_rd_data_count[0] = \ ; + assign axi_ar_sbiterr = \ ; + assign axi_ar_underflow = \ ; + assign axi_ar_wr_data_count[4] = \ ; + assign axi_ar_wr_data_count[3] = \ ; + assign axi_ar_wr_data_count[2] = \ ; + assign axi_ar_wr_data_count[1] = \ ; + assign axi_ar_wr_data_count[0] = \ ; + assign axi_aw_data_count[4] = \ ; + assign axi_aw_data_count[3] = \ ; + assign axi_aw_data_count[2] = \ ; + assign axi_aw_data_count[1] = \ ; + assign axi_aw_data_count[0] = \ ; + assign axi_aw_dbiterr = \ ; + assign axi_aw_overflow = \ ; + assign axi_aw_prog_empty = \ ; + assign axi_aw_prog_full = \ ; + assign axi_aw_rd_data_count[4] = \ ; + assign axi_aw_rd_data_count[3] = \ ; + assign axi_aw_rd_data_count[2] = \ ; + assign axi_aw_rd_data_count[1] = \ ; + assign axi_aw_rd_data_count[0] = \ ; + assign axi_aw_sbiterr = \ ; + assign axi_aw_underflow = \ ; + assign axi_aw_wr_data_count[4] = \ ; + assign axi_aw_wr_data_count[3] = \ ; + assign axi_aw_wr_data_count[2] = \ ; + assign axi_aw_wr_data_count[1] = \ ; + assign axi_aw_wr_data_count[0] = \ ; + assign axi_b_data_count[4] = \ ; + assign axi_b_data_count[3] = \ ; + assign axi_b_data_count[2] = \ ; + assign axi_b_data_count[1] = \ ; + assign axi_b_data_count[0] = \ ; + assign axi_b_dbiterr = \ ; + assign axi_b_overflow = \ ; + assign axi_b_prog_empty = \ ; + assign axi_b_prog_full = \ ; + assign axi_b_rd_data_count[4] = \ ; + assign axi_b_rd_data_count[3] = \ ; + assign axi_b_rd_data_count[2] = \ ; + assign axi_b_rd_data_count[1] = \ ; + assign axi_b_rd_data_count[0] = \ ; + assign axi_b_sbiterr = \ ; + assign axi_b_underflow = \ ; + assign axi_b_wr_data_count[4] = \ ; + assign axi_b_wr_data_count[3] = \ ; + assign axi_b_wr_data_count[2] = \ ; + assign axi_b_wr_data_count[1] = \ ; + assign axi_b_wr_data_count[0] = \ ; + assign axi_r_data_count[10] = \ ; + assign axi_r_data_count[9] = \ ; + assign axi_r_data_count[8] = \ ; + assign axi_r_data_count[7] = \ ; + assign axi_r_data_count[6] = \ ; + assign axi_r_data_count[5] = \ ; + assign axi_r_data_count[4] = \ ; + assign axi_r_data_count[3] = \ ; + assign axi_r_data_count[2] = \ ; + assign axi_r_data_count[1] = \ ; + assign axi_r_data_count[0] = \ ; + assign axi_r_dbiterr = \ ; + assign axi_r_overflow = \ ; + assign axi_r_prog_empty = \ ; + assign axi_r_prog_full = \ ; + assign axi_r_rd_data_count[10] = \ ; + assign axi_r_rd_data_count[9] = \ ; + assign axi_r_rd_data_count[8] = \ ; + assign axi_r_rd_data_count[7] = \ ; + assign axi_r_rd_data_count[6] = \ ; + assign axi_r_rd_data_count[5] = \ ; + assign axi_r_rd_data_count[4] = \ ; + assign axi_r_rd_data_count[3] = \ ; + assign axi_r_rd_data_count[2] = \ ; + assign axi_r_rd_data_count[1] = \ ; + assign axi_r_rd_data_count[0] = \ ; + assign axi_r_sbiterr = \ ; + assign axi_r_underflow = \ ; + assign axi_r_wr_data_count[10] = \ ; + assign axi_r_wr_data_count[9] = \ ; + assign axi_r_wr_data_count[8] = \ ; + assign axi_r_wr_data_count[7] = \ ; + assign axi_r_wr_data_count[6] = \ ; + assign axi_r_wr_data_count[5] = \ ; + assign axi_r_wr_data_count[4] = \ ; + assign axi_r_wr_data_count[3] = \ ; + assign axi_r_wr_data_count[2] = \ ; + assign axi_r_wr_data_count[1] = \ ; + assign axi_r_wr_data_count[0] = \ ; + assign axi_w_data_count[10] = \ ; + assign axi_w_data_count[9] = \ ; + assign axi_w_data_count[8] = \ ; + assign axi_w_data_count[7] = \ ; + assign axi_w_data_count[6] = \ ; + assign axi_w_data_count[5] = \ ; + assign axi_w_data_count[4] = \ ; + assign axi_w_data_count[3] = \ ; + assign axi_w_data_count[2] = \ ; + assign axi_w_data_count[1] = \ ; + assign axi_w_data_count[0] = \ ; + assign axi_w_dbiterr = \ ; + assign axi_w_overflow = \ ; + assign axi_w_prog_empty = \ ; + assign axi_w_prog_full = \ ; + assign axi_w_rd_data_count[10] = \ ; + assign axi_w_rd_data_count[9] = \ ; + assign axi_w_rd_data_count[8] = \ ; + assign axi_w_rd_data_count[7] = \ ; + assign axi_w_rd_data_count[6] = \ ; + assign axi_w_rd_data_count[5] = \ ; + assign axi_w_rd_data_count[4] = \ ; + assign axi_w_rd_data_count[3] = \ ; + assign axi_w_rd_data_count[2] = \ ; + assign axi_w_rd_data_count[1] = \ ; + assign axi_w_rd_data_count[0] = \ ; + assign axi_w_sbiterr = \ ; + assign axi_w_underflow = \ ; + assign axi_w_wr_data_count[10] = \ ; + assign axi_w_wr_data_count[9] = \ ; + assign axi_w_wr_data_count[8] = \ ; + assign axi_w_wr_data_count[7] = \ ; + assign axi_w_wr_data_count[6] = \ ; + assign axi_w_wr_data_count[5] = \ ; + assign axi_w_wr_data_count[4] = \ ; + assign axi_w_wr_data_count[3] = \ ; + assign axi_w_wr_data_count[2] = \ ; + assign axi_w_wr_data_count[1] = \ ; + assign axi_w_wr_data_count[0] = \ ; + assign axis_data_count[10] = \ ; + assign axis_data_count[9] = \ ; + assign axis_data_count[8] = \ ; + assign axis_data_count[7] = \ ; + assign axis_data_count[6] = \ ; + assign axis_data_count[5] = \ ; + assign axis_data_count[4] = \ ; + assign axis_data_count[3] = \ ; + assign axis_data_count[2] = \ ; + assign axis_data_count[1] = \ ; + assign axis_data_count[0] = \ ; + assign axis_dbiterr = \ ; + assign axis_overflow = \ ; + assign axis_prog_empty = \ ; + assign axis_prog_full = \ ; + assign axis_rd_data_count[10] = \ ; + assign axis_rd_data_count[9] = \ ; + assign axis_rd_data_count[8] = \ ; + assign axis_rd_data_count[7] = \ ; + assign axis_rd_data_count[6] = \ ; + assign axis_rd_data_count[5] = \ ; + assign axis_rd_data_count[4] = \ ; + assign axis_rd_data_count[3] = \ ; + assign axis_rd_data_count[2] = \ ; + assign axis_rd_data_count[1] = \ ; + assign axis_rd_data_count[0] = \ ; + assign axis_sbiterr = \ ; + assign axis_underflow = \ ; + assign axis_wr_data_count[10] = \ ; + assign axis_wr_data_count[9] = \ ; + assign axis_wr_data_count[8] = \ ; + assign axis_wr_data_count[7] = \ ; + assign axis_wr_data_count[6] = \ ; + assign axis_wr_data_count[5] = \ ; + assign axis_wr_data_count[4] = \ ; + assign axis_wr_data_count[3] = \ ; + assign axis_wr_data_count[2] = \ ; + assign axis_wr_data_count[1] = \ ; + assign axis_wr_data_count[0] = \ ; + assign data_count[5] = \ ; + assign data_count[4] = \ ; + assign data_count[3] = \ ; + assign data_count[2] = \ ; + assign data_count[1] = \ ; + assign data_count[0] = \ ; + assign dbiterr = \ ; + assign m_axi_araddr[31] = \ ; + assign m_axi_araddr[30] = \ ; + assign m_axi_araddr[29] = \ ; + assign m_axi_araddr[28] = \ ; + assign m_axi_araddr[27] = \ ; + assign m_axi_araddr[26] = \ ; + assign m_axi_araddr[25] = \ ; + assign m_axi_araddr[24] = \ ; + assign m_axi_araddr[23] = \ ; + assign m_axi_araddr[22] = \ ; + assign m_axi_araddr[21] = \ ; + assign m_axi_araddr[20] = \ ; + assign m_axi_araddr[19] = \ ; + assign m_axi_araddr[18] = \ ; + assign m_axi_araddr[17] = \ ; + assign m_axi_araddr[16] = \ ; + assign m_axi_araddr[15] = \ ; + assign m_axi_araddr[14] = \ ; + assign m_axi_araddr[13] = \ ; + assign m_axi_araddr[12] = \ ; + assign m_axi_araddr[11] = \ ; + assign m_axi_araddr[10] = \ ; + assign m_axi_araddr[9] = \ ; + assign m_axi_araddr[8] = \ ; + assign m_axi_araddr[7] = \ ; + assign m_axi_araddr[6] = \ ; + assign m_axi_araddr[5] = \ ; + assign m_axi_araddr[4] = \ ; + assign m_axi_araddr[3] = \ ; + assign m_axi_araddr[2] = \ ; + assign m_axi_araddr[1] = \ ; + assign m_axi_araddr[0] = \ ; + assign m_axi_arburst[1] = \ ; + assign m_axi_arburst[0] = \ ; + assign m_axi_arcache[3] = \ ; + assign m_axi_arcache[2] = \ ; + assign m_axi_arcache[1] = \ ; + assign m_axi_arcache[0] = \ ; + assign m_axi_arid[3] = \ ; + assign m_axi_arid[2] = \ ; + assign m_axi_arid[1] = \ ; + assign m_axi_arid[0] = \ ; + assign m_axi_arlen[7] = \ ; + assign m_axi_arlen[6] = \ ; + assign m_axi_arlen[5] = \ ; + assign m_axi_arlen[4] = \ ; + assign m_axi_arlen[3] = \ ; + assign m_axi_arlen[2] = \ ; + assign m_axi_arlen[1] = \ ; + assign m_axi_arlen[0] = \ ; + assign m_axi_arlock[1] = \ ; + assign m_axi_arlock[0] = \ ; + assign m_axi_arprot[2] = \ ; + assign m_axi_arprot[1] = \ ; + assign m_axi_arprot[0] = \ ; + assign m_axi_arqos[3] = \ ; + assign m_axi_arqos[2] = \ ; + assign m_axi_arqos[1] = \ ; + assign m_axi_arqos[0] = \ ; + assign m_axi_arregion[3] = \ ; + assign m_axi_arregion[2] = \ ; + assign m_axi_arregion[1] = \ ; + assign m_axi_arregion[0] = \ ; + assign m_axi_arsize[2] = \ ; + assign m_axi_arsize[1] = \ ; + assign m_axi_arsize[0] = \ ; + assign m_axi_aruser[0] = \ ; + assign m_axi_arvalid = \ ; + assign m_axi_awaddr[31] = \ ; + assign m_axi_awaddr[30] = \ ; + assign m_axi_awaddr[29] = \ ; + assign m_axi_awaddr[28] = \ ; + assign m_axi_awaddr[27] = \ ; + assign m_axi_awaddr[26] = \ ; + assign m_axi_awaddr[25] = \ ; + assign m_axi_awaddr[24] = \ ; + assign m_axi_awaddr[23] = \ ; + assign m_axi_awaddr[22] = \ ; + assign m_axi_awaddr[21] = \ ; + assign m_axi_awaddr[20] = \ ; + assign m_axi_awaddr[19] = \ ; + assign m_axi_awaddr[18] = \ ; + assign m_axi_awaddr[17] = \ ; + assign m_axi_awaddr[16] = \ ; + assign m_axi_awaddr[15] = \ ; + assign m_axi_awaddr[14] = \ ; + assign m_axi_awaddr[13] = \ ; + assign m_axi_awaddr[12] = \ ; + assign m_axi_awaddr[11] = \ ; + assign m_axi_awaddr[10] = \ ; + assign m_axi_awaddr[9] = \ ; + assign m_axi_awaddr[8] = \ ; + assign m_axi_awaddr[7] = \ ; + assign m_axi_awaddr[6] = \ ; + assign m_axi_awaddr[5] = \ ; + assign m_axi_awaddr[4] = \ ; + assign m_axi_awaddr[3] = \ ; + assign m_axi_awaddr[2] = \ ; + assign m_axi_awaddr[1] = \ ; + assign m_axi_awaddr[0] = \ ; + assign m_axi_awburst[1] = \ ; + assign m_axi_awburst[0] = \ ; + assign m_axi_awcache[3] = \ ; + assign m_axi_awcache[2] = \ ; + assign m_axi_awcache[1] = \ ; + assign m_axi_awcache[0] = \ ; + assign m_axi_awid[3] = \ ; + assign m_axi_awid[2] = \ ; + assign m_axi_awid[1] = \ ; + assign m_axi_awid[0] = \ ; + assign m_axi_awlen[7] = \ ; + assign m_axi_awlen[6] = \ ; + assign m_axi_awlen[5] = \ ; + assign m_axi_awlen[4] = \ ; + assign m_axi_awlen[3] = \ ; + assign m_axi_awlen[2] = \ ; + assign m_axi_awlen[1] = \ ; + assign m_axi_awlen[0] = \ ; + assign m_axi_awlock[1] = \ ; + assign m_axi_awlock[0] = \ ; + assign m_axi_awprot[2] = \ ; + assign m_axi_awprot[1] = \ ; + assign m_axi_awprot[0] = \ ; + assign m_axi_awqos[3] = \ ; + assign m_axi_awqos[2] = \ ; + assign m_axi_awqos[1] = \ ; + assign m_axi_awqos[0] = \ ; + assign m_axi_awregion[3] = \ ; + assign m_axi_awregion[2] = \ ; + assign m_axi_awregion[1] = \ ; + assign m_axi_awregion[0] = \ ; + assign m_axi_awsize[2] = \ ; + assign m_axi_awsize[1] = \ ; + assign m_axi_awsize[0] = \ ; + assign m_axi_awuser[0] = \ ; + assign m_axi_awvalid = \ ; + assign m_axi_bready = \ ; + assign m_axi_rready = \ ; + assign m_axi_wdata[63] = \ ; + assign m_axi_wdata[62] = \ ; + assign m_axi_wdata[61] = \ ; + assign m_axi_wdata[60] = \ ; + assign m_axi_wdata[59] = \ ; + assign m_axi_wdata[58] = \ ; + assign m_axi_wdata[57] = \ ; + assign m_axi_wdata[56] = \ ; + assign m_axi_wdata[55] = \ ; + assign m_axi_wdata[54] = \ ; + assign m_axi_wdata[53] = \ ; + assign m_axi_wdata[52] = \ ; + assign m_axi_wdata[51] = \ ; + assign m_axi_wdata[50] = \ ; + assign m_axi_wdata[49] = \ ; + assign m_axi_wdata[48] = \ ; + assign m_axi_wdata[47] = \ ; + assign m_axi_wdata[46] = \ ; + assign m_axi_wdata[45] = \ ; + assign m_axi_wdata[44] = \ ; + assign m_axi_wdata[43] = \ ; + assign m_axi_wdata[42] = \ ; + assign m_axi_wdata[41] = \ ; + assign m_axi_wdata[40] = \ ; + assign m_axi_wdata[39] = \ ; + assign m_axi_wdata[38] = \ ; + assign m_axi_wdata[37] = \ ; + assign m_axi_wdata[36] = \ ; + assign m_axi_wdata[35] = \ ; + assign m_axi_wdata[34] = \ ; + assign m_axi_wdata[33] = \ ; + assign m_axi_wdata[32] = \ ; + assign m_axi_wdata[31] = \ ; + assign m_axi_wdata[30] = \ ; + assign m_axi_wdata[29] = \ ; + assign m_axi_wdata[28] = \ ; + assign m_axi_wdata[27] = \ ; + assign m_axi_wdata[26] = \ ; + assign m_axi_wdata[25] = \ ; + assign m_axi_wdata[24] = \ ; + assign m_axi_wdata[23] = \ ; + assign m_axi_wdata[22] = \ ; + assign m_axi_wdata[21] = \ ; + assign m_axi_wdata[20] = \ ; + assign m_axi_wdata[19] = \ ; + assign m_axi_wdata[18] = \ ; + assign m_axi_wdata[17] = \ ; + assign m_axi_wdata[16] = \ ; + assign m_axi_wdata[15] = \ ; + assign m_axi_wdata[14] = \ ; + assign m_axi_wdata[13] = \ ; + assign m_axi_wdata[12] = \ ; + assign m_axi_wdata[11] = \ ; + assign m_axi_wdata[10] = \ ; + assign m_axi_wdata[9] = \ ; + assign m_axi_wdata[8] = \ ; + assign m_axi_wdata[7] = \ ; + assign m_axi_wdata[6] = \ ; + assign m_axi_wdata[5] = \ ; + assign m_axi_wdata[4] = \ ; + assign m_axi_wdata[3] = \ ; + assign m_axi_wdata[2] = \ ; + assign m_axi_wdata[1] = \ ; + assign m_axi_wdata[0] = \ ; + assign m_axi_wid[3] = \ ; + assign m_axi_wid[2] = \ ; + assign m_axi_wid[1] = \ ; + assign m_axi_wid[0] = \ ; + assign m_axi_wlast = \ ; + assign m_axi_wstrb[7] = \ ; + assign m_axi_wstrb[6] = \ ; + assign m_axi_wstrb[5] = \ ; + assign m_axi_wstrb[4] = \ ; + assign m_axi_wstrb[3] = \ ; + assign m_axi_wstrb[2] = \ ; + assign m_axi_wstrb[1] = \ ; + assign m_axi_wstrb[0] = \ ; + assign m_axi_wuser[0] = \ ; + assign m_axi_wvalid = \ ; + assign m_axis_tdata[63] = \ ; + assign m_axis_tdata[62] = \ ; + assign m_axis_tdata[61] = \ ; + assign m_axis_tdata[60] = \ ; + assign m_axis_tdata[59] = \ ; + assign m_axis_tdata[58] = \ ; + assign m_axis_tdata[57] = \ ; + assign m_axis_tdata[56] = \ ; + assign m_axis_tdata[55] = \ ; + assign m_axis_tdata[54] = \ ; + assign m_axis_tdata[53] = \ ; + assign m_axis_tdata[52] = \ ; + assign m_axis_tdata[51] = \ ; + assign m_axis_tdata[50] = \ ; + assign m_axis_tdata[49] = \ ; + assign m_axis_tdata[48] = \ ; + assign m_axis_tdata[47] = \ ; + assign m_axis_tdata[46] = \ ; + assign m_axis_tdata[45] = \ ; + assign m_axis_tdata[44] = \ ; + assign m_axis_tdata[43] = \ ; + assign m_axis_tdata[42] = \ ; + assign m_axis_tdata[41] = \ ; + assign m_axis_tdata[40] = \ ; + assign m_axis_tdata[39] = \ ; + assign m_axis_tdata[38] = \ ; + assign m_axis_tdata[37] = \ ; + assign m_axis_tdata[36] = \ ; + assign m_axis_tdata[35] = \ ; + assign m_axis_tdata[34] = \ ; + assign m_axis_tdata[33] = \ ; + assign m_axis_tdata[32] = \ ; + assign m_axis_tdata[31] = \ ; + assign m_axis_tdata[30] = \ ; + assign m_axis_tdata[29] = \ ; + assign m_axis_tdata[28] = \ ; + assign m_axis_tdata[27] = \ ; + assign m_axis_tdata[26] = \ ; + assign m_axis_tdata[25] = \ ; + assign m_axis_tdata[24] = \ ; + assign m_axis_tdata[23] = \ ; + assign m_axis_tdata[22] = \ ; + assign m_axis_tdata[21] = \ ; + assign m_axis_tdata[20] = \ ; + assign m_axis_tdata[19] = \ ; + assign m_axis_tdata[18] = \ ; + assign m_axis_tdata[17] = \ ; + assign m_axis_tdata[16] = \ ; + assign m_axis_tdata[15] = \ ; + assign m_axis_tdata[14] = \ ; + assign m_axis_tdata[13] = \ ; + assign m_axis_tdata[12] = \ ; + assign m_axis_tdata[11] = \ ; + assign m_axis_tdata[10] = \ ; + assign m_axis_tdata[9] = \ ; + assign m_axis_tdata[8] = \ ; + assign m_axis_tdata[7] = \ ; + assign m_axis_tdata[6] = \ ; + assign m_axis_tdata[5] = \ ; + assign m_axis_tdata[4] = \ ; + assign m_axis_tdata[3] = \ ; + assign m_axis_tdata[2] = \ ; + assign m_axis_tdata[1] = \ ; + assign m_axis_tdata[0] = \ ; + assign m_axis_tdest[3] = \ ; + assign m_axis_tdest[2] = \ ; + assign m_axis_tdest[1] = \ ; + assign m_axis_tdest[0] = \ ; + assign m_axis_tid[7] = \ ; + assign m_axis_tid[6] = \ ; + assign m_axis_tid[5] = \ ; + assign m_axis_tid[4] = \ ; + assign m_axis_tid[3] = \ ; + assign m_axis_tid[2] = \ ; + assign m_axis_tid[1] = \ ; + assign m_axis_tid[0] = \ ; + assign m_axis_tkeep[3] = \ ; + assign m_axis_tkeep[2] = \ ; + assign m_axis_tkeep[1] = \ ; + assign m_axis_tkeep[0] = \ ; + assign m_axis_tlast = \ ; + assign m_axis_tstrb[3] = \ ; + assign m_axis_tstrb[2] = \ ; + assign m_axis_tstrb[1] = \ ; + assign m_axis_tstrb[0] = \ ; + assign m_axis_tuser[3] = \ ; + assign m_axis_tuser[2] = \ ; + assign m_axis_tuser[1] = \ ; + assign m_axis_tuser[0] = \ ; + assign m_axis_tvalid = \ ; + assign overflow = \ ; + assign prog_empty = \ ; + assign prog_full = \ ; + assign rd_data_count[5] = \ ; + assign rd_data_count[4] = \ ; + assign rd_data_count[3] = \ ; + assign rd_data_count[2] = \ ; + assign rd_data_count[1] = \ ; + assign rd_data_count[0] = \ ; + assign rd_rst_busy = \ ; + assign s_axi_arready = \ ; + assign s_axi_awready = \ ; + assign s_axi_bid[3] = \ ; + assign s_axi_bid[2] = \ ; + assign s_axi_bid[1] = \ ; + assign s_axi_bid[0] = \ ; + assign s_axi_bresp[1] = \ ; + assign s_axi_bresp[0] = \ ; + assign s_axi_buser[0] = \ ; + assign s_axi_bvalid = \ ; + assign s_axi_rdata[63] = \ ; + assign s_axi_rdata[62] = \ ; + assign s_axi_rdata[61] = \ ; + assign s_axi_rdata[60] = \ ; + assign s_axi_rdata[59] = \ ; + assign s_axi_rdata[58] = \ ; + assign s_axi_rdata[57] = \ ; + assign s_axi_rdata[56] = \ ; + assign s_axi_rdata[55] = \ ; + assign s_axi_rdata[54] = \ ; + assign s_axi_rdata[53] = \ ; + assign s_axi_rdata[52] = \ ; + assign s_axi_rdata[51] = \ ; + assign s_axi_rdata[50] = \ ; + assign s_axi_rdata[49] = \ ; + assign s_axi_rdata[48] = \ ; + assign s_axi_rdata[47] = \ ; + assign s_axi_rdata[46] = \ ; + assign s_axi_rdata[45] = \ ; + assign s_axi_rdata[44] = \ ; + assign s_axi_rdata[43] = \ ; + assign s_axi_rdata[42] = \ ; + assign s_axi_rdata[41] = \ ; + assign s_axi_rdata[40] = \ ; + assign s_axi_rdata[39] = \ ; + assign s_axi_rdata[38] = \ ; + assign s_axi_rdata[37] = \ ; + assign s_axi_rdata[36] = \ ; + assign s_axi_rdata[35] = \ ; + assign s_axi_rdata[34] = \ ; + assign s_axi_rdata[33] = \ ; + assign s_axi_rdata[32] = \ ; + assign s_axi_rdata[31] = \ ; + assign s_axi_rdata[30] = \ ; + assign s_axi_rdata[29] = \ ; + assign s_axi_rdata[28] = \ ; + assign s_axi_rdata[27] = \ ; + assign s_axi_rdata[26] = \ ; + assign s_axi_rdata[25] = \ ; + assign s_axi_rdata[24] = \ ; + assign s_axi_rdata[23] = \ ; + assign s_axi_rdata[22] = \ ; + assign s_axi_rdata[21] = \ ; + assign s_axi_rdata[20] = \ ; + assign s_axi_rdata[19] = \ ; + assign s_axi_rdata[18] = \ ; + assign s_axi_rdata[17] = \ ; + assign s_axi_rdata[16] = \ ; + assign s_axi_rdata[15] = \ ; + assign s_axi_rdata[14] = \ ; + assign s_axi_rdata[13] = \ ; + assign s_axi_rdata[12] = \ ; + assign s_axi_rdata[11] = \ ; + assign s_axi_rdata[10] = \ ; + assign s_axi_rdata[9] = \ ; + assign s_axi_rdata[8] = \ ; + assign s_axi_rdata[7] = \ ; + assign s_axi_rdata[6] = \ ; + assign s_axi_rdata[5] = \ ; + assign s_axi_rdata[4] = \ ; + assign s_axi_rdata[3] = \ ; + assign s_axi_rdata[2] = \ ; + assign s_axi_rdata[1] = \ ; + assign s_axi_rdata[0] = \ ; + assign s_axi_rid[3] = \ ; + assign s_axi_rid[2] = \ ; + assign s_axi_rid[1] = \ ; + assign s_axi_rid[0] = \ ; + assign s_axi_rlast = \ ; + assign s_axi_rresp[1] = \ ; + assign s_axi_rresp[0] = \ ; + assign s_axi_ruser[0] = \ ; + assign s_axi_rvalid = \ ; + assign s_axi_wready = \ ; + assign s_axis_tready = \ ; + assign sbiterr = \ ; + assign underflow = \ ; + assign valid = \ ; + assign wr_ack = \ ; + assign wr_data_count[5] = \ ; + assign wr_data_count[4] = \ ; + assign wr_data_count[3] = \ ; + assign wr_data_count[2] = \ ; + assign wr_data_count[1] = \ ; + assign wr_data_count[0] = \ ; + assign wr_rst_busy = \ ; + GND GND + (.G(\ )); + Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3_synth inst_fifo_gen + (.clk(clk), + .din(din), + .dout(dout), + .empty(empty), + .full(full), + .rd_en(rd_en), + .rst(rst), + .wr_en(wr_en)); endmodule -(* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) -(* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) -(* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_READ = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *) -(* C_AXI_SUPPORTS_WRITE = "0" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_FAMILY = "zynq" *) -(* C_IGNORE_ID = "1" *) (* C_M_AXI_PROTOCOL = "1" *) (* C_S_AXI_PROTOCOL = "0" *) -(* C_TRANSLATION_MODE = "2" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* P_AXI3 = "1" *) -(* P_AXI4 = "0" *) (* P_AXILITE = "2" *) (* P_AXILITE_SIZE = "3'b011" *) -(* P_CONVERSION = "2" *) (* P_DECERR = "2'b11" *) (* P_INCR = "2'b01" *) -(* P_PROTECTION = "1" *) (* P_SLVERR = "2'b10" *) -module Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter - (aclk, - aresetn, +(* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *) +(* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *) +(* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "64" *) (* C_AXIS_TDEST_WIDTH = "4" *) +(* C_AXIS_TID_WIDTH = "8" *) (* C_AXIS_TKEEP_WIDTH = "4" *) (* C_AXIS_TSTRB_WIDTH = "4" *) +(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *) +(* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *) +(* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "4" *) (* C_AXI_LEN_WIDTH = "8" *) +(* C_AXI_LOCK_WIDTH = "2" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "0" *) +(* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "1" *) (* C_COUNT_TYPE = "0" *) +(* C_DATA_COUNT_WIDTH = "6" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "5" *) +(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *) +(* C_DIN_WIDTH_WACH = "32" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *) +(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "5" *) (* C_ENABLE_RLOCS = "0" *) +(* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *) +(* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) +(* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) +(* C_FAMILY = "zynq" *) (* C_FULL_FLAGS_RST_VAL = "0" *) (* C_HAS_ALMOST_EMPTY = "0" *) +(* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "0" *) (* C_HAS_AXIS_TDEST = "0" *) +(* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *) +(* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "0" *) +(* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *) +(* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_RD_CHANNEL = "0" *) (* C_HAS_AXI_RUSER = "0" *) +(* C_HAS_AXI_WR_CHANNEL = "0" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *) +(* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *) +(* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *) +(* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *) +(* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *) +(* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *) +(* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *) +(* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *) (* C_HAS_SLAVE_CE = "0" *) +(* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *) +(* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *) +(* C_IMPLEMENTATION_TYPE = "0" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *) +(* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) +(* C_IMPLEMENTATION_TYPE_WRCH = "1" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *) +(* C_MEMORY_TYPE = "2" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *) +(* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *) +(* C_PRELOAD_LATENCY = "0" *) (* C_PRELOAD_REGS = "1" *) (* C_PRIM_FIFO_TYPE = "512x36" *) +(* C_PRIM_FIFO_TYPE_AXIS = "512x36" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "512x36" *) +(* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "512x36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) +(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "4" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) +(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) +(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "5" *) (* C_PROG_EMPTY_TYPE = "0" *) +(* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *) +(* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *) +(* C_PROG_FULL_THRESH_ASSERT_VAL = "31" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) +(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) +(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "30" *) (* C_PROG_FULL_TYPE = "0" *) +(* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *) +(* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *) +(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "6" *) +(* C_RD_DEPTH = "32" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "5" *) +(* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *) +(* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *) +(* C_SELECT_XPM = "0" *) (* C_SYNCHRONIZER_STAGE = "3" *) (* C_UNDERFLOW_LOW = "0" *) +(* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *) +(* C_USE_DOUT_RST = "0" *) (* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *) +(* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *) +(* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *) +(* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "1" *) (* C_USE_PIPELINE_REG = "0" *) +(* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *) +(* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "6" *) +(* C_WR_DEPTH = "32" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *) +(* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *) +(* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "5" *) +(* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *) +(* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *) +(* C_WR_RESPONSE_LATENCY = "1" *) (* ORIG_REF_NAME = "fifo_generator_v13_1_3" *) +module Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1 + (backup, + backup_marker, + clk, + rst, + srst, + wr_clk, + wr_rst, + rd_clk, + rd_rst, + din, + wr_en, + rd_en, + prog_empty_thresh, + prog_empty_thresh_assert, + prog_empty_thresh_negate, + prog_full_thresh, + prog_full_thresh_assert, + prog_full_thresh_negate, + int_clk, + injectdbiterr, + injectsbiterr, + sleep, + dout, + full, + almost_full, + wr_ack, + overflow, + empty, + almost_empty, + valid, + underflow, + data_count, + rd_data_count, + wr_data_count, + prog_full, + prog_empty, + sbiterr, + dbiterr, + wr_rst_busy, + rd_rst_busy, + m_aclk, + s_aclk, + s_aresetn, + m_aclk_en, + s_aclk_en, s_axi_awid, s_axi_awaddr, s_axi_awlen, @@ -3789,8 +11216,8 @@ module Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converte s_axi_awlock, s_axi_awcache, s_axi_awprot, - s_axi_awregion, s_axi_awqos, + s_axi_awregion, s_axi_awuser, s_axi_awvalid, s_axi_awready, @@ -3806,26 +11233,6 @@ module Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converte s_axi_buser, s_axi_bvalid, s_axi_bready, - s_axi_arid, - s_axi_araddr, - s_axi_arlen, - s_axi_arsize, - s_axi_arburst, - s_axi_arlock, - s_axi_arcache, - s_axi_arprot, - s_axi_arregion, - s_axi_arqos, - s_axi_aruser, - s_axi_arvalid, - s_axi_arready, - s_axi_rid, - s_axi_rdata, - s_axi_rresp, - s_axi_rlast, - s_axi_ruser, - s_axi_rvalid, - s_axi_rready, m_axi_awid, m_axi_awaddr, m_axi_awlen, @@ -3834,8 +11241,8 @@ module Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converte m_axi_awlock, m_axi_awcache, m_axi_awprot, - m_axi_awregion, m_axi_awqos, + m_axi_awregion, m_axi_awuser, m_axi_awvalid, m_axi_awready, @@ -3851,6 +11258,26 @@ module Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converte m_axi_buser, m_axi_bvalid, m_axi_bready, + s_axi_arid, + s_axi_araddr, + s_axi_arlen, + s_axi_arsize, + s_axi_arburst, + s_axi_arlock, + s_axi_arcache, + s_axi_arprot, + s_axi_arqos, + s_axi_arregion, + s_axi_aruser, + s_axi_arvalid, + s_axi_arready, + s_axi_rid, + s_axi_rdata, + s_axi_rresp, + s_axi_rlast, + s_axi_ruser, + s_axi_rvalid, + s_axi_rready, m_axi_arid, m_axi_araddr, m_axi_arlen, @@ -3859,8 +11286,8 @@ module Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converte m_axi_arlock, m_axi_arcache, m_axi_arprot, - m_axi_arregion, m_axi_arqos, + m_axi_arregion, m_axi_aruser, m_axi_arvalid, m_axi_arready, @@ -3870,143 +11297,602 @@ module Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converte m_axi_rlast, m_axi_ruser, m_axi_rvalid, - m_axi_rready); - input aclk; - input aresetn; - input [0:0]s_axi_awid; + m_axi_rready, + s_axis_tvalid, + s_axis_tready, + s_axis_tdata, + s_axis_tstrb, + s_axis_tkeep, + s_axis_tlast, + s_axis_tid, + s_axis_tdest, + s_axis_tuser, + m_axis_tvalid, + m_axis_tready, + m_axis_tdata, + m_axis_tstrb, + m_axis_tkeep, + m_axis_tlast, + m_axis_tid, + m_axis_tdest, + m_axis_tuser, + axi_aw_injectsbiterr, + axi_aw_injectdbiterr, + axi_aw_prog_full_thresh, + axi_aw_prog_empty_thresh, + axi_aw_data_count, + axi_aw_wr_data_count, + axi_aw_rd_data_count, + axi_aw_sbiterr, + axi_aw_dbiterr, + axi_aw_overflow, + axi_aw_underflow, + axi_aw_prog_full, + axi_aw_prog_empty, + axi_w_injectsbiterr, + axi_w_injectdbiterr, + axi_w_prog_full_thresh, + axi_w_prog_empty_thresh, + axi_w_data_count, + axi_w_wr_data_count, + axi_w_rd_data_count, + axi_w_sbiterr, + axi_w_dbiterr, + axi_w_overflow, + axi_w_underflow, + axi_w_prog_full, + axi_w_prog_empty, + axi_b_injectsbiterr, + axi_b_injectdbiterr, + axi_b_prog_full_thresh, + axi_b_prog_empty_thresh, + axi_b_data_count, + axi_b_wr_data_count, + axi_b_rd_data_count, + axi_b_sbiterr, + axi_b_dbiterr, + axi_b_overflow, + axi_b_underflow, + axi_b_prog_full, + axi_b_prog_empty, + axi_ar_injectsbiterr, + axi_ar_injectdbiterr, + axi_ar_prog_full_thresh, + axi_ar_prog_empty_thresh, + axi_ar_data_count, + axi_ar_wr_data_count, + axi_ar_rd_data_count, + axi_ar_sbiterr, + axi_ar_dbiterr, + axi_ar_overflow, + axi_ar_underflow, + axi_ar_prog_full, + axi_ar_prog_empty, + axi_r_injectsbiterr, + axi_r_injectdbiterr, + axi_r_prog_full_thresh, + axi_r_prog_empty_thresh, + axi_r_data_count, + axi_r_wr_data_count, + axi_r_rd_data_count, + axi_r_sbiterr, + axi_r_dbiterr, + axi_r_overflow, + axi_r_underflow, + axi_r_prog_full, + axi_r_prog_empty, + axis_injectsbiterr, + axis_injectdbiterr, + axis_prog_full_thresh, + axis_prog_empty_thresh, + axis_data_count, + axis_wr_data_count, + axis_rd_data_count, + axis_sbiterr, + axis_dbiterr, + axis_overflow, + axis_underflow, + axis_prog_full, + axis_prog_empty); + input backup; + input backup_marker; + input clk; + input rst; + input srst; + input wr_clk; + input wr_rst; + input rd_clk; + input rd_rst; + input [4:0]din; + input wr_en; + input rd_en; + input [4:0]prog_empty_thresh; + input [4:0]prog_empty_thresh_assert; + input [4:0]prog_empty_thresh_negate; + input [4:0]prog_full_thresh; + input [4:0]prog_full_thresh_assert; + input [4:0]prog_full_thresh_negate; + input int_clk; + input injectdbiterr; + input injectsbiterr; + input sleep; + output [4:0]dout; + output full; + output almost_full; + output wr_ack; + output overflow; + output empty; + output almost_empty; + output valid; + output underflow; + output [5:0]data_count; + output [5:0]rd_data_count; + output [5:0]wr_data_count; + output prog_full; + output prog_empty; + output sbiterr; + output dbiterr; + output wr_rst_busy; + output rd_rst_busy; + input m_aclk; + input s_aclk; + input s_aresetn; + input m_aclk_en; + input s_aclk_en; + input [3:0]s_axi_awid; input [31:0]s_axi_awaddr; input [7:0]s_axi_awlen; input [2:0]s_axi_awsize; input [1:0]s_axi_awburst; - input [0:0]s_axi_awlock; + input [1:0]s_axi_awlock; input [3:0]s_axi_awcache; input [2:0]s_axi_awprot; - input [3:0]s_axi_awregion; input [3:0]s_axi_awqos; + input [3:0]s_axi_awregion; input [0:0]s_axi_awuser; input s_axi_awvalid; output s_axi_awready; - input [0:0]s_axi_wid; + input [3:0]s_axi_wid; input [63:0]s_axi_wdata; input [7:0]s_axi_wstrb; input s_axi_wlast; input [0:0]s_axi_wuser; input s_axi_wvalid; output s_axi_wready; - output [0:0]s_axi_bid; + output [3:0]s_axi_bid; output [1:0]s_axi_bresp; output [0:0]s_axi_buser; output s_axi_bvalid; input s_axi_bready; - input [0:0]s_axi_arid; - input [31:0]s_axi_araddr; - input [7:0]s_axi_arlen; - input [2:0]s_axi_arsize; - input [1:0]s_axi_arburst; - input [0:0]s_axi_arlock; - input [3:0]s_axi_arcache; - input [2:0]s_axi_arprot; - input [3:0]s_axi_arregion; - input [3:0]s_axi_arqos; - input [0:0]s_axi_aruser; - input s_axi_arvalid; - output s_axi_arready; - output [0:0]s_axi_rid; - output [63:0]s_axi_rdata; - output [1:0]s_axi_rresp; - output s_axi_rlast; - output [0:0]s_axi_ruser; - output s_axi_rvalid; - input s_axi_rready; - output [0:0]m_axi_awid; + output [3:0]m_axi_awid; output [31:0]m_axi_awaddr; - output [3:0]m_axi_awlen; + output [7:0]m_axi_awlen; output [2:0]m_axi_awsize; output [1:0]m_axi_awburst; output [1:0]m_axi_awlock; output [3:0]m_axi_awcache; output [2:0]m_axi_awprot; - output [3:0]m_axi_awregion; output [3:0]m_axi_awqos; + output [3:0]m_axi_awregion; output [0:0]m_axi_awuser; output m_axi_awvalid; input m_axi_awready; - output [0:0]m_axi_wid; + output [3:0]m_axi_wid; output [63:0]m_axi_wdata; output [7:0]m_axi_wstrb; output m_axi_wlast; output [0:0]m_axi_wuser; output m_axi_wvalid; input m_axi_wready; - input [0:0]m_axi_bid; + input [3:0]m_axi_bid; input [1:0]m_axi_bresp; input [0:0]m_axi_buser; input m_axi_bvalid; output m_axi_bready; - output [0:0]m_axi_arid; + input [3:0]s_axi_arid; + input [31:0]s_axi_araddr; + input [7:0]s_axi_arlen; + input [2:0]s_axi_arsize; + input [1:0]s_axi_arburst; + input [1:0]s_axi_arlock; + input [3:0]s_axi_arcache; + input [2:0]s_axi_arprot; + input [3:0]s_axi_arqos; + input [3:0]s_axi_arregion; + input [0:0]s_axi_aruser; + input s_axi_arvalid; + output s_axi_arready; + output [3:0]s_axi_rid; + output [63:0]s_axi_rdata; + output [1:0]s_axi_rresp; + output s_axi_rlast; + output [0:0]s_axi_ruser; + output s_axi_rvalid; + input s_axi_rready; + output [3:0]m_axi_arid; output [31:0]m_axi_araddr; - output [3:0]m_axi_arlen; + output [7:0]m_axi_arlen; output [2:0]m_axi_arsize; output [1:0]m_axi_arburst; output [1:0]m_axi_arlock; output [3:0]m_axi_arcache; output [2:0]m_axi_arprot; - output [3:0]m_axi_arregion; output [3:0]m_axi_arqos; + output [3:0]m_axi_arregion; output [0:0]m_axi_aruser; output m_axi_arvalid; input m_axi_arready; - input [0:0]m_axi_rid; + input [3:0]m_axi_rid; input [63:0]m_axi_rdata; input [1:0]m_axi_rresp; input m_axi_rlast; input [0:0]m_axi_ruser; input m_axi_rvalid; output m_axi_rready; + input s_axis_tvalid; + output s_axis_tready; + input [63:0]s_axis_tdata; + input [3:0]s_axis_tstrb; + input [3:0]s_axis_tkeep; + input s_axis_tlast; + input [7:0]s_axis_tid; + input [3:0]s_axis_tdest; + input [3:0]s_axis_tuser; + output m_axis_tvalid; + input m_axis_tready; + output [63:0]m_axis_tdata; + output [3:0]m_axis_tstrb; + output [3:0]m_axis_tkeep; + output m_axis_tlast; + output [7:0]m_axis_tid; + output [3:0]m_axis_tdest; + output [3:0]m_axis_tuser; + input axi_aw_injectsbiterr; + input axi_aw_injectdbiterr; + input [3:0]axi_aw_prog_full_thresh; + input [3:0]axi_aw_prog_empty_thresh; + output [4:0]axi_aw_data_count; + output [4:0]axi_aw_wr_data_count; + output [4:0]axi_aw_rd_data_count; + output axi_aw_sbiterr; + output axi_aw_dbiterr; + output axi_aw_overflow; + output axi_aw_underflow; + output axi_aw_prog_full; + output axi_aw_prog_empty; + input axi_w_injectsbiterr; + input axi_w_injectdbiterr; + input [9:0]axi_w_prog_full_thresh; + input [9:0]axi_w_prog_empty_thresh; + output [10:0]axi_w_data_count; + output [10:0]axi_w_wr_data_count; + output [10:0]axi_w_rd_data_count; + output axi_w_sbiterr; + output axi_w_dbiterr; + output axi_w_overflow; + output axi_w_underflow; + output axi_w_prog_full; + output axi_w_prog_empty; + input axi_b_injectsbiterr; + input axi_b_injectdbiterr; + input [3:0]axi_b_prog_full_thresh; + input [3:0]axi_b_prog_empty_thresh; + output [4:0]axi_b_data_count; + output [4:0]axi_b_wr_data_count; + output [4:0]axi_b_rd_data_count; + output axi_b_sbiterr; + output axi_b_dbiterr; + output axi_b_overflow; + output axi_b_underflow; + output axi_b_prog_full; + output axi_b_prog_empty; + input axi_ar_injectsbiterr; + input axi_ar_injectdbiterr; + input [3:0]axi_ar_prog_full_thresh; + input [3:0]axi_ar_prog_empty_thresh; + output [4:0]axi_ar_data_count; + output [4:0]axi_ar_wr_data_count; + output [4:0]axi_ar_rd_data_count; + output axi_ar_sbiterr; + output axi_ar_dbiterr; + output axi_ar_overflow; + output axi_ar_underflow; + output axi_ar_prog_full; + output axi_ar_prog_empty; + input axi_r_injectsbiterr; + input axi_r_injectdbiterr; + input [9:0]axi_r_prog_full_thresh; + input [9:0]axi_r_prog_empty_thresh; + output [10:0]axi_r_data_count; + output [10:0]axi_r_wr_data_count; + output [10:0]axi_r_rd_data_count; + output axi_r_sbiterr; + output axi_r_dbiterr; + output axi_r_overflow; + output axi_r_underflow; + output axi_r_prog_full; + output axi_r_prog_empty; + input axis_injectsbiterr; + input axis_injectdbiterr; + input [9:0]axis_prog_full_thresh; + input [9:0]axis_prog_empty_thresh; + output [10:0]axis_data_count; + output [10:0]axis_wr_data_count; + output [10:0]axis_rd_data_count; + output axis_sbiterr; + output axis_dbiterr; + output axis_overflow; + output axis_underflow; + output axis_prog_full; + output axis_prog_empty; wire \ ; - wire aclk; - wire aresetn; - wire [31:0]m_axi_araddr; - wire [1:0]m_axi_arburst; - wire [3:0]m_axi_arcache; - wire [0:0]m_axi_arid; - wire [3:0]m_axi_arlen; - wire [0:0]\^m_axi_arlock ; - wire [2:0]m_axi_arprot; - wire [3:0]m_axi_arqos; - wire m_axi_arready; - wire [2:0]m_axi_arsize; - wire m_axi_arvalid; - wire [63:0]m_axi_rdata; - wire [0:0]m_axi_rid; - wire m_axi_rlast; - wire m_axi_rready; - wire [1:0]m_axi_rresp; - wire [0:0]m_axi_ruser; - wire m_axi_rvalid; - wire [31:0]s_axi_araddr; - wire [1:0]s_axi_arburst; - wire [3:0]s_axi_arcache; - wire [0:0]s_axi_arid; - wire [7:0]s_axi_arlen; - wire [0:0]s_axi_arlock; - wire [2:0]s_axi_arprot; - wire [3:0]s_axi_arqos; - wire s_axi_arready; - wire [2:0]s_axi_arsize; - wire s_axi_arvalid; - wire s_axi_rlast; - wire s_axi_rready; - wire s_axi_rvalid; + wire clk; + wire [4:0]din; + wire [4:0]dout; + wire empty; + wire full; + wire rd_en; + wire rst; + wire wr_en; + assign almost_empty = \ ; + assign almost_full = \ ; + assign axi_ar_data_count[4] = \ ; + assign axi_ar_data_count[3] = \ ; + assign axi_ar_data_count[2] = \ ; + assign axi_ar_data_count[1] = \ ; + assign axi_ar_data_count[0] = \ ; + assign axi_ar_dbiterr = \ ; + assign axi_ar_overflow = \ ; + assign axi_ar_prog_empty = \ ; + assign axi_ar_prog_full = \ ; + assign axi_ar_rd_data_count[4] = \ ; + assign axi_ar_rd_data_count[3] = \ ; + assign axi_ar_rd_data_count[2] = \ ; + assign axi_ar_rd_data_count[1] = \ ; + assign axi_ar_rd_data_count[0] = \ ; + assign axi_ar_sbiterr = \ ; + assign axi_ar_underflow = \ ; + assign axi_ar_wr_data_count[4] = \ ; + assign axi_ar_wr_data_count[3] = \ ; + assign axi_ar_wr_data_count[2] = \ ; + assign axi_ar_wr_data_count[1] = \ ; + assign axi_ar_wr_data_count[0] = \ ; + assign axi_aw_data_count[4] = \ ; + assign axi_aw_data_count[3] = \ ; + assign axi_aw_data_count[2] = \ ; + assign axi_aw_data_count[1] = \ ; + assign axi_aw_data_count[0] = \ ; + assign axi_aw_dbiterr = \ ; + assign axi_aw_overflow = \ ; + assign axi_aw_prog_empty = \ ; + assign axi_aw_prog_full = \ ; + assign axi_aw_rd_data_count[4] = \ ; + assign axi_aw_rd_data_count[3] = \ ; + assign axi_aw_rd_data_count[2] = \ ; + assign axi_aw_rd_data_count[1] = \ ; + assign axi_aw_rd_data_count[0] = \ ; + assign axi_aw_sbiterr = \ ; + assign axi_aw_underflow = \ ; + assign axi_aw_wr_data_count[4] = \ ; + assign axi_aw_wr_data_count[3] = \ ; + assign axi_aw_wr_data_count[2] = \ ; + assign axi_aw_wr_data_count[1] = \ ; + assign axi_aw_wr_data_count[0] = \ ; + assign axi_b_data_count[4] = \ ; + assign axi_b_data_count[3] = \ ; + assign axi_b_data_count[2] = \ ; + assign axi_b_data_count[1] = \ ; + assign axi_b_data_count[0] = \ ; + assign axi_b_dbiterr = \ ; + assign axi_b_overflow = \ ; + assign axi_b_prog_empty = \ ; + assign axi_b_prog_full = \ ; + assign axi_b_rd_data_count[4] = \ ; + assign axi_b_rd_data_count[3] = \ ; + assign axi_b_rd_data_count[2] = \ ; + assign axi_b_rd_data_count[1] = \ ; + assign axi_b_rd_data_count[0] = \ ; + assign axi_b_sbiterr = \ ; + assign axi_b_underflow = \ ; + assign axi_b_wr_data_count[4] = \ ; + assign axi_b_wr_data_count[3] = \ ; + assign axi_b_wr_data_count[2] = \ ; + assign axi_b_wr_data_count[1] = \ ; + assign axi_b_wr_data_count[0] = \ ; + assign axi_r_data_count[10] = \ ; + assign axi_r_data_count[9] = \ ; + assign axi_r_data_count[8] = \ ; + assign axi_r_data_count[7] = \ ; + assign axi_r_data_count[6] = \ ; + assign axi_r_data_count[5] = \ ; + assign axi_r_data_count[4] = \ ; + assign axi_r_data_count[3] = \ ; + assign axi_r_data_count[2] = \ ; + assign axi_r_data_count[1] = \ ; + assign axi_r_data_count[0] = \ ; + assign axi_r_dbiterr = \ ; + assign axi_r_overflow = \ ; + assign axi_r_prog_empty = \ ; + assign axi_r_prog_full = \ ; + assign axi_r_rd_data_count[10] = \ ; + assign axi_r_rd_data_count[9] = \ ; + assign axi_r_rd_data_count[8] = \ ; + assign axi_r_rd_data_count[7] = \ ; + assign axi_r_rd_data_count[6] = \ ; + assign axi_r_rd_data_count[5] = \ ; + assign axi_r_rd_data_count[4] = \ ; + assign axi_r_rd_data_count[3] = \ ; + assign axi_r_rd_data_count[2] = \ ; + assign axi_r_rd_data_count[1] = \ ; + assign axi_r_rd_data_count[0] = \ ; + assign axi_r_sbiterr = \ ; + assign axi_r_underflow = \ ; + assign axi_r_wr_data_count[10] = \ ; + assign axi_r_wr_data_count[9] = \ ; + assign axi_r_wr_data_count[8] = \ ; + assign axi_r_wr_data_count[7] = \ ; + assign axi_r_wr_data_count[6] = \ ; + assign axi_r_wr_data_count[5] = \ ; + assign axi_r_wr_data_count[4] = \ ; + assign axi_r_wr_data_count[3] = \ ; + assign axi_r_wr_data_count[2] = \ ; + assign axi_r_wr_data_count[1] = \ ; + assign axi_r_wr_data_count[0] = \ ; + assign axi_w_data_count[10] = \ ; + assign axi_w_data_count[9] = \ ; + assign axi_w_data_count[8] = \ ; + assign axi_w_data_count[7] = \ ; + assign axi_w_data_count[6] = \ ; + assign axi_w_data_count[5] = \ ; + assign axi_w_data_count[4] = \ ; + assign axi_w_data_count[3] = \ ; + assign axi_w_data_count[2] = \ ; + assign axi_w_data_count[1] = \ ; + assign axi_w_data_count[0] = \ ; + assign axi_w_dbiterr = \ ; + assign axi_w_overflow = \ ; + assign axi_w_prog_empty = \ ; + assign axi_w_prog_full = \ ; + assign axi_w_rd_data_count[10] = \ ; + assign axi_w_rd_data_count[9] = \ ; + assign axi_w_rd_data_count[8] = \ ; + assign axi_w_rd_data_count[7] = \ ; + assign axi_w_rd_data_count[6] = \ ; + assign axi_w_rd_data_count[5] = \ ; + assign axi_w_rd_data_count[4] = \ ; + assign axi_w_rd_data_count[3] = \ ; + assign axi_w_rd_data_count[2] = \ ; + assign axi_w_rd_data_count[1] = \ ; + assign axi_w_rd_data_count[0] = \ ; + assign axi_w_sbiterr = \ ; + assign axi_w_underflow = \ ; + assign axi_w_wr_data_count[10] = \ ; + assign axi_w_wr_data_count[9] = \ ; + assign axi_w_wr_data_count[8] = \ ; + assign axi_w_wr_data_count[7] = \ ; + assign axi_w_wr_data_count[6] = \ ; + assign axi_w_wr_data_count[5] = \ ; + assign axi_w_wr_data_count[4] = \ ; + assign axi_w_wr_data_count[3] = \ ; + assign axi_w_wr_data_count[2] = \ ; + assign axi_w_wr_data_count[1] = \ ; + assign axi_w_wr_data_count[0] = \ ; + assign axis_data_count[10] = \ ; + assign axis_data_count[9] = \ ; + assign axis_data_count[8] = \ ; + assign axis_data_count[7] = \ ; + assign axis_data_count[6] = \ ; + assign axis_data_count[5] = \ ; + assign axis_data_count[4] = \ ; + assign axis_data_count[3] = \ ; + assign axis_data_count[2] = \ ; + assign axis_data_count[1] = \ ; + assign axis_data_count[0] = \ ; + assign axis_dbiterr = \ ; + assign axis_overflow = \ ; + assign axis_prog_empty = \ ; + assign axis_prog_full = \ ; + assign axis_rd_data_count[10] = \ ; + assign axis_rd_data_count[9] = \ ; + assign axis_rd_data_count[8] = \ ; + assign axis_rd_data_count[7] = \ ; + assign axis_rd_data_count[6] = \ ; + assign axis_rd_data_count[5] = \ ; + assign axis_rd_data_count[4] = \ ; + assign axis_rd_data_count[3] = \ ; + assign axis_rd_data_count[2] = \ ; + assign axis_rd_data_count[1] = \ ; + assign axis_rd_data_count[0] = \ ; + assign axis_sbiterr = \ ; + assign axis_underflow = \ ; + assign axis_wr_data_count[10] = \ ; + assign axis_wr_data_count[9] = \ ; + assign axis_wr_data_count[8] = \ ; + assign axis_wr_data_count[7] = \ ; + assign axis_wr_data_count[6] = \ ; + assign axis_wr_data_count[5] = \ ; + assign axis_wr_data_count[4] = \ ; + assign axis_wr_data_count[3] = \ ; + assign axis_wr_data_count[2] = \ ; + assign axis_wr_data_count[1] = \ ; + assign axis_wr_data_count[0] = \ ; + assign data_count[5] = \ ; + assign data_count[4] = \ ; + assign data_count[3] = \ ; + assign data_count[2] = \ ; + assign data_count[1] = \ ; + assign data_count[0] = \ ; + assign dbiterr = \ ; + assign m_axi_araddr[31] = \ ; + assign m_axi_araddr[30] = \ ; + assign m_axi_araddr[29] = \ ; + assign m_axi_araddr[28] = \ ; + assign m_axi_araddr[27] = \ ; + assign m_axi_araddr[26] = \ ; + assign m_axi_araddr[25] = \ ; + assign m_axi_araddr[24] = \ ; + assign m_axi_araddr[23] = \ ; + assign m_axi_araddr[22] = \ ; + assign m_axi_araddr[21] = \ ; + assign m_axi_araddr[20] = \ ; + assign m_axi_araddr[19] = \ ; + assign m_axi_araddr[18] = \ ; + assign m_axi_araddr[17] = \ ; + assign m_axi_araddr[16] = \ ; + assign m_axi_araddr[15] = \ ; + assign m_axi_araddr[14] = \ ; + assign m_axi_araddr[13] = \ ; + assign m_axi_araddr[12] = \ ; + assign m_axi_araddr[11] = \ ; + assign m_axi_araddr[10] = \ ; + assign m_axi_araddr[9] = \ ; + assign m_axi_araddr[8] = \ ; + assign m_axi_araddr[7] = \ ; + assign m_axi_araddr[6] = \ ; + assign m_axi_araddr[5] = \ ; + assign m_axi_araddr[4] = \ ; + assign m_axi_araddr[3] = \ ; + assign m_axi_araddr[2] = \ ; + assign m_axi_araddr[1] = \ ; + assign m_axi_araddr[0] = \ ; + assign m_axi_arburst[1] = \ ; + assign m_axi_arburst[0] = \ ; + assign m_axi_arcache[3] = \ ; + assign m_axi_arcache[2] = \ ; + assign m_axi_arcache[1] = \ ; + assign m_axi_arcache[0] = \ ; + assign m_axi_arid[3] = \ ; + assign m_axi_arid[2] = \ ; + assign m_axi_arid[1] = \ ; + assign m_axi_arid[0] = \ ; + assign m_axi_arlen[7] = \ ; + assign m_axi_arlen[6] = \ ; + assign m_axi_arlen[5] = \ ; + assign m_axi_arlen[4] = \ ; + assign m_axi_arlen[3] = \ ; + assign m_axi_arlen[2] = \ ; + assign m_axi_arlen[1] = \ ; + assign m_axi_arlen[0] = \ ; assign m_axi_arlock[1] = \ ; - assign m_axi_arlock[0] = \^m_axi_arlock [0]; + assign m_axi_arlock[0] = \ ; + assign m_axi_arprot[2] = \ ; + assign m_axi_arprot[1] = \ ; + assign m_axi_arprot[0] = \ ; + assign m_axi_arqos[3] = \ ; + assign m_axi_arqos[2] = \ ; + assign m_axi_arqos[1] = \ ; + assign m_axi_arqos[0] = \ ; assign m_axi_arregion[3] = \ ; assign m_axi_arregion[2] = \ ; assign m_axi_arregion[1] = \ ; assign m_axi_arregion[0] = \ ; + assign m_axi_arsize[2] = \ ; + assign m_axi_arsize[1] = \ ; + assign m_axi_arsize[0] = \ ; assign m_axi_aruser[0] = \ ; + assign m_axi_arvalid = \ ; assign m_axi_awaddr[31] = \ ; assign m_axi_awaddr[30] = \ ; assign m_axi_awaddr[29] = \ ; @@ -4045,7 +11931,14 @@ module Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converte assign m_axi_awcache[2] = \ ; assign m_axi_awcache[1] = \ ; assign m_axi_awcache[0] = \ ; + assign m_axi_awid[3] = \ ; + assign m_axi_awid[2] = \ ; + assign m_axi_awid[1] = \ ; assign m_axi_awid[0] = \ ; + assign m_axi_awlen[7] = \ ; + assign m_axi_awlen[6] = \ ; + assign m_axi_awlen[5] = \ ; + assign m_axi_awlen[4] = \ ; assign m_axi_awlen[3] = \ ; assign m_axi_awlen[2] = \ ; assign m_axi_awlen[1] = \ ; @@ -4069,6 +11962,7 @@ module Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converte assign m_axi_awuser[0] = \ ; assign m_axi_awvalid = \ ; assign m_axi_bready = \ ; + assign m_axi_rready = \ ; assign m_axi_wdata[63] = \ ; assign m_axi_wdata[62] = \ ; assign m_axi_wdata[61] = \ ; @@ -4133,6 +12027,9 @@ module Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converte assign m_axi_wdata[2] = \ ; assign m_axi_wdata[1] = \ ; assign m_axi_wdata[0] = \ ; + assign m_axi_wid[3] = \ ; + assign m_axi_wid[2] = \ ; + assign m_axi_wid[1] = \ ; assign m_axi_wid[0] = \ ; assign m_axi_wlast = \ ; assign m_axi_wstrb[7] = \ ; @@ -4145,260 +12042,205 @@ module Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converte assign m_axi_wstrb[0] = \ ; assign m_axi_wuser[0] = \ ; assign m_axi_wvalid = \ ; + assign m_axis_tdata[63] = \ ; + assign m_axis_tdata[62] = \ ; + assign m_axis_tdata[61] = \ ; + assign m_axis_tdata[60] = \ ; + assign m_axis_tdata[59] = \ ; + assign m_axis_tdata[58] = \ ; + assign m_axis_tdata[57] = \ ; + assign m_axis_tdata[56] = \ ; + assign m_axis_tdata[55] = \ ; + assign m_axis_tdata[54] = \ ; + assign m_axis_tdata[53] = \ ; + assign m_axis_tdata[52] = \ ; + assign m_axis_tdata[51] = \ ; + assign m_axis_tdata[50] = \ ; + assign m_axis_tdata[49] = \ ; + assign m_axis_tdata[48] = \ ; + assign m_axis_tdata[47] = \ ; + assign m_axis_tdata[46] = \ ; + assign m_axis_tdata[45] = \ ; + assign m_axis_tdata[44] = \ ; + assign m_axis_tdata[43] = \ ; + assign m_axis_tdata[42] = \ ; + assign m_axis_tdata[41] = \ ; + assign m_axis_tdata[40] = \ ; + assign m_axis_tdata[39] = \ ; + assign m_axis_tdata[38] = \ ; + assign m_axis_tdata[37] = \ ; + assign m_axis_tdata[36] = \ ; + assign m_axis_tdata[35] = \ ; + assign m_axis_tdata[34] = \ ; + assign m_axis_tdata[33] = \ ; + assign m_axis_tdata[32] = \ ; + assign m_axis_tdata[31] = \ ; + assign m_axis_tdata[30] = \ ; + assign m_axis_tdata[29] = \ ; + assign m_axis_tdata[28] = \ ; + assign m_axis_tdata[27] = \ ; + assign m_axis_tdata[26] = \ ; + assign m_axis_tdata[25] = \ ; + assign m_axis_tdata[24] = \ ; + assign m_axis_tdata[23] = \ ; + assign m_axis_tdata[22] = \ ; + assign m_axis_tdata[21] = \ ; + assign m_axis_tdata[20] = \ ; + assign m_axis_tdata[19] = \ ; + assign m_axis_tdata[18] = \ ; + assign m_axis_tdata[17] = \ ; + assign m_axis_tdata[16] = \ ; + assign m_axis_tdata[15] = \ ; + assign m_axis_tdata[14] = \ ; + assign m_axis_tdata[13] = \ ; + assign m_axis_tdata[12] = \ ; + assign m_axis_tdata[11] = \ ; + assign m_axis_tdata[10] = \ ; + assign m_axis_tdata[9] = \ ; + assign m_axis_tdata[8] = \ ; + assign m_axis_tdata[7] = \ ; + assign m_axis_tdata[6] = \ ; + assign m_axis_tdata[5] = \ ; + assign m_axis_tdata[4] = \ ; + assign m_axis_tdata[3] = \ ; + assign m_axis_tdata[2] = \ ; + assign m_axis_tdata[1] = \ ; + assign m_axis_tdata[0] = \ ; + assign m_axis_tdest[3] = \ ; + assign m_axis_tdest[2] = \ ; + assign m_axis_tdest[1] = \ ; + assign m_axis_tdest[0] = \ ; + assign m_axis_tid[7] = \ ; + assign m_axis_tid[6] = \ ; + assign m_axis_tid[5] = \ ; + assign m_axis_tid[4] = \ ; + assign m_axis_tid[3] = \ ; + assign m_axis_tid[2] = \ ; + assign m_axis_tid[1] = \ ; + assign m_axis_tid[0] = \ ; + assign m_axis_tkeep[3] = \ ; + assign m_axis_tkeep[2] = \ ; + assign m_axis_tkeep[1] = \ ; + assign m_axis_tkeep[0] = \ ; + assign m_axis_tlast = \ ; + assign m_axis_tstrb[3] = \ ; + assign m_axis_tstrb[2] = \ ; + assign m_axis_tstrb[1] = \ ; + assign m_axis_tstrb[0] = \ ; + assign m_axis_tuser[3] = \ ; + assign m_axis_tuser[2] = \ ; + assign m_axis_tuser[1] = \ ; + assign m_axis_tuser[0] = \ ; + assign m_axis_tvalid = \ ; + assign overflow = \ ; + assign prog_empty = \ ; + assign prog_full = \ ; + assign rd_data_count[5] = \ ; + assign rd_data_count[4] = \ ; + assign rd_data_count[3] = \ ; + assign rd_data_count[2] = \ ; + assign rd_data_count[1] = \ ; + assign rd_data_count[0] = \ ; + assign rd_rst_busy = \ ; + assign s_axi_arready = \ ; assign s_axi_awready = \ ; + assign s_axi_bid[3] = \ ; + assign s_axi_bid[2] = \ ; + assign s_axi_bid[1] = \ ; assign s_axi_bid[0] = \ ; assign s_axi_bresp[1] = \ ; assign s_axi_bresp[0] = \ ; assign s_axi_buser[0] = \ ; assign s_axi_bvalid = \ ; - assign s_axi_rdata[63:0] = m_axi_rdata; - assign s_axi_rid[0] = m_axi_rid; - assign s_axi_rresp[1:0] = m_axi_rresp; - assign s_axi_ruser[0] = m_axi_ruser; - assign s_axi_wready = \ ; - GND GND - (.G(\ )); - Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi3_conv \gen_axi4_axi3.axi3_conv_inst - (.M_AXI_ARID(m_axi_arid), - .aclk(aclk), - .aresetn(aresetn), - .m_axi_araddr(m_axi_araddr), - .m_axi_arburst(m_axi_arburst), - .m_axi_arcache(m_axi_arcache), - .m_axi_arlen(m_axi_arlen), - .m_axi_arlock(\^m_axi_arlock ), - .m_axi_arprot(m_axi_arprot), - .m_axi_arqos(m_axi_arqos), - .m_axi_arready(m_axi_arready), - .m_axi_arsize(m_axi_arsize), - .m_axi_arvalid(m_axi_arvalid), - .m_axi_rlast(m_axi_rlast), - .m_axi_rready(m_axi_rready), - .m_axi_rvalid(m_axi_rvalid), - .s_axi_araddr(s_axi_araddr), - .s_axi_arburst(s_axi_arburst), - .s_axi_arcache(s_axi_arcache), - .s_axi_arid(s_axi_arid), - .s_axi_arlen(s_axi_arlen), - .s_axi_arlock(s_axi_arlock), - .s_axi_arprot(s_axi_arprot), - .s_axi_arqos(s_axi_arqos), - .s_axi_arready(s_axi_arready), - .s_axi_arsize(s_axi_arsize), - .s_axi_arvalid(s_axi_arvalid), - .s_axi_rlast(s_axi_rlast), - .s_axi_rready(s_axi_rready), - .s_axi_rvalid(s_axi_rvalid)); -endmodule - -module Arty_Z7_20_auto_pc_0_dmem - (p_0_out, - dout_i, - \goreg_dm.dout_i_reg[0] , - clk, - din, - E, - \gcc0.gc0.count_d1_reg[4] , - \gc0.count_d1_reg[4] , - ram_empty_fb_i_reg, - \gpregsm1.curr_fwft_state_reg[1] , - rd_en, - out, - dout); - output p_0_out; - output dout_i; - output \goreg_dm.dout_i_reg[0] ; - input clk; - input [0:0]din; - input [0:0]E; - input [4:0]\gcc0.gc0.count_d1_reg[4] ; - input [4:0]\gc0.count_d1_reg[4] ; - input ram_empty_fb_i_reg; - input [1:0]\gpregsm1.curr_fwft_state_reg[1] ; - input rd_en; - input [0:0]out; - input [0:0]dout; - - wire [0:0]E; - wire clk; - wire [0:0]din; - wire [0:0]dout; - wire dout_i; - wire [4:0]\gc0.count_d1_reg[4] ; - wire [4:0]\gcc0.gc0.count_d1_reg[4] ; - wire \goreg_dm.dout_i_reg[0] ; - wire [1:0]\gpregsm1.curr_fwft_state_reg[1] ; - wire [0:0]out; - wire p_0_out; - wire ram_empty_fb_i_reg; - wire rd_en; - wire NLW_RAM_reg_0_31_0_0_SPO_UNCONNECTED; - - RAM32X1D RAM_reg_0_31_0_0 - (.A0(\gcc0.gc0.count_d1_reg[4] [0]), - .A1(\gcc0.gc0.count_d1_reg[4] [1]), - .A2(\gcc0.gc0.count_d1_reg[4] [2]), - .A3(\gcc0.gc0.count_d1_reg[4] [3]), - .A4(\gcc0.gc0.count_d1_reg[4] [4]), - .D(din), - .DPO(p_0_out), - .DPRA0(\gc0.count_d1_reg[4] [0]), - .DPRA1(\gc0.count_d1_reg[4] [1]), - .DPRA2(\gc0.count_d1_reg[4] [2]), - .DPRA3(\gc0.count_d1_reg[4] [3]), - .DPRA4(\gc0.count_d1_reg[4] [4]), - .SPO(NLW_RAM_reg_0_31_0_0_SPO_UNCONNECTED), - .WCLK(clk), - .WE(E)); - LUT6 #( - .INIT(64'hFFFFAEFF0000A200)) - \goreg_dm.dout_i[0]_i_1 - (.I0(dout_i), - .I1(\gpregsm1.curr_fwft_state_reg[1] [0]), - .I2(rd_en), - .I3(\gpregsm1.curr_fwft_state_reg[1] [1]), - .I4(out), - .I5(dout), - .O(\goreg_dm.dout_i_reg[0] )); - FDRE #( - .INIT(1'b0)) - \gpr1.dout_i_reg[0] - (.C(clk), - .CE(1'b1), - .D(ram_empty_fb_i_reg), - .Q(dout_i), - .R(1'b0)); -endmodule - -module Arty_Z7_20_auto_pc_0_fifo_generator_ramfifo - (empty, - full, - dout, - rd_en, - clk, - rst, - din, - wr_en); - output empty; - output full; - output [0:0]dout; - input rd_en; - input clk; - input rst; - input [0:0]din; - input wr_en; - - wire clk; - wire [0:0]din; - wire [0:0]dout; - wire dout_i; - wire empty; - wire full; - wire \gntv_or_sync_fifo.gl0.rd_n_1 ; - wire \gntv_or_sync_fifo.gl0.rd_n_11 ; - wire \gntv_or_sync_fifo.gl0.rd_n_12 ; - wire \gntv_or_sync_fifo.gl0.rd_n_4 ; - wire \gntv_or_sync_fifo.gl0.wr_n_0 ; - wire \gntv_or_sync_fifo.gl0.wr_n_7 ; - wire [0:0]\gr1.gr1_int.rfwft/p_0_in ; - wire \gwss.wsts/ram_full_comb ; - wire p_0_out; - wire [4:0]p_0_out_0; - wire [4:0]p_11_out; - wire [4:0]p_12_out; - wire p_17_out; - wire p_2_out; - wire rd_en; - wire [4:0]rd_pntr_plus1; - wire [2:0]rd_rst_i; - wire rst; - wire rst_full_ff_i; - wire wr_en; - wire [1:1]wr_rst_i; - - Arty_Z7_20_auto_pc_0_rd_logic \gntv_or_sync_fifo.gl0.rd - (.AR(rd_rst_i[2]), - .Q(rd_pntr_plus1), - .aempty_fwft_i_reg({\gntv_or_sync_fifo.gl0.rd_n_1 ,\gr1.gr1_int.rfwft/p_0_in }), - .clk(clk), - .dout_i(dout_i), - .empty(empty), - .\gcc0.gc0.count_d1_reg[4] (p_11_out), - .\gcc0.gc0.count_reg[4] (p_12_out), - .\gpr1.dout_i_reg[0] (\gntv_or_sync_fifo.gl0.rd_n_4 ), - .out(p_2_out), - .p_0_out(p_0_out), - .ram_empty_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_7 ), - .ram_empty_i_reg(\gntv_or_sync_fifo.gl0.rd_n_12 ), - .ram_full_comb(\gwss.wsts/ram_full_comb ), - .ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_0 ), - .ram_full_i_reg(\gntv_or_sync_fifo.gl0.rd_n_11 ), - .ram_full_i_reg_0(p_0_out_0), - .rd_en(rd_en), - .wr_en(wr_en)); - Arty_Z7_20_auto_pc_0_wr_logic \gntv_or_sync_fifo.gl0.wr - (.E(p_17_out), - .Q(p_12_out), - .clk(clk), - .full(full), - .\gc0.count_reg[4] (rd_pntr_plus1), - .\gcc0.gc0.count_d1_reg[1] (\gntv_or_sync_fifo.gl0.rd_n_11 ), - .\gpregsm1.curr_fwft_state_reg[1] (\gntv_or_sync_fifo.gl0.rd_n_12 ), - .\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ({wr_rst_i,rst_full_ff_i}), - .out(\gntv_or_sync_fifo.gl0.wr_n_0 ), - .ram_empty_fb_i_reg(p_2_out), - .ram_empty_i_reg(\gntv_or_sync_fifo.gl0.wr_n_7 ), - .ram_empty_i_reg_0(p_11_out), - .ram_full_comb(\gwss.wsts/ram_full_comb ), - .wr_en(wr_en)); - Arty_Z7_20_auto_pc_0_memory \gntv_or_sync_fifo.mem - (.E(p_17_out), - .clk(clk), - .din(din), - .dout(dout), - .dout_i(dout_i), - .\gc0.count_d1_reg[4] (p_0_out_0), - .\gcc0.gc0.count_d1_reg[4] (p_11_out), - .\gpregsm1.curr_fwft_state_reg[1] ({\gntv_or_sync_fifo.gl0.rd_n_1 ,\gr1.gr1_int.rfwft/p_0_in }), - .out(rd_rst_i[0]), - .p_0_out(p_0_out), - .ram_empty_fb_i_reg(\gntv_or_sync_fifo.gl0.rd_n_4 ), - .rd_en(rd_en)); - Arty_Z7_20_auto_pc_0_reset_blk_ramfifo rstblk - (.clk(clk), - .\gc0.count_reg[1] ({rd_rst_i[2],rd_rst_i[0]}), - .out({wr_rst_i,rst_full_ff_i}), - .rst(rst)); -endmodule - -module Arty_Z7_20_auto_pc_0_fifo_generator_top - (empty, - full, - dout, - rd_en, - clk, - rst, - din, - wr_en); - output empty; - output full; - output [0:0]dout; - input rd_en; - input clk; - input rst; - input [0:0]din; - input wr_en; - - wire clk; - wire [0:0]din; - wire [0:0]dout; - wire empty; - wire full; - wire rd_en; - wire rst; - wire wr_en; - - Arty_Z7_20_auto_pc_0_fifo_generator_ramfifo \grf.rf + assign s_axi_rdata[63] = \ ; + assign s_axi_rdata[62] = \ ; + assign s_axi_rdata[61] = \ ; + assign s_axi_rdata[60] = \ ; + assign s_axi_rdata[59] = \ ; + assign s_axi_rdata[58] = \ ; + assign s_axi_rdata[57] = \ ; + assign s_axi_rdata[56] = \ ; + assign s_axi_rdata[55] = \ ; + assign s_axi_rdata[54] = \ ; + assign s_axi_rdata[53] = \ ; + assign s_axi_rdata[52] = \ ; + assign s_axi_rdata[51] = \ ; + assign s_axi_rdata[50] = \ ; + assign s_axi_rdata[49] = \ ; + assign s_axi_rdata[48] = \ ; + assign s_axi_rdata[47] = \ ; + assign s_axi_rdata[46] = \ ; + assign s_axi_rdata[45] = \ ; + assign s_axi_rdata[44] = \ ; + assign s_axi_rdata[43] = \ ; + assign s_axi_rdata[42] = \ ; + assign s_axi_rdata[41] = \ ; + assign s_axi_rdata[40] = \ ; + assign s_axi_rdata[39] = \ ; + assign s_axi_rdata[38] = \ ; + assign s_axi_rdata[37] = \ ; + assign s_axi_rdata[36] = \ ; + assign s_axi_rdata[35] = \ ; + assign s_axi_rdata[34] = \ ; + assign s_axi_rdata[33] = \ ; + assign s_axi_rdata[32] = \ ; + assign s_axi_rdata[31] = \ ; + assign s_axi_rdata[30] = \ ; + assign s_axi_rdata[29] = \ ; + assign s_axi_rdata[28] = \ ; + assign s_axi_rdata[27] = \ ; + assign s_axi_rdata[26] = \ ; + assign s_axi_rdata[25] = \ ; + assign s_axi_rdata[24] = \ ; + assign s_axi_rdata[23] = \ ; + assign s_axi_rdata[22] = \ ; + assign s_axi_rdata[21] = \ ; + assign s_axi_rdata[20] = \ ; + assign s_axi_rdata[19] = \ ; + assign s_axi_rdata[18] = \ ; + assign s_axi_rdata[17] = \ ; + assign s_axi_rdata[16] = \ ; + assign s_axi_rdata[15] = \ ; + assign s_axi_rdata[14] = \ ; + assign s_axi_rdata[13] = \ ; + assign s_axi_rdata[12] = \ ; + assign s_axi_rdata[11] = \ ; + assign s_axi_rdata[10] = \ ; + assign s_axi_rdata[9] = \ ; + assign s_axi_rdata[8] = \ ; + assign s_axi_rdata[7] = \ ; + assign s_axi_rdata[6] = \ ; + assign s_axi_rdata[5] = \ ; + assign s_axi_rdata[4] = \ ; + assign s_axi_rdata[3] = \ ; + assign s_axi_rdata[2] = \ ; + assign s_axi_rdata[1] = \ ; + assign s_axi_rdata[0] = \ ; + assign s_axi_rid[3] = \ ; + assign s_axi_rid[2] = \ ; + assign s_axi_rid[1] = \ ; + assign s_axi_rid[0] = \ ; + assign s_axi_rlast = \ ; + assign s_axi_rresp[1] = \ ; + assign s_axi_rresp[0] = \ ; + assign s_axi_ruser[0] = \ ; + assign s_axi_rvalid = \ ; + assign s_axi_wready = \ ; + assign s_axis_tready = \ ; + assign sbiterr = \ ; + assign underflow = \ ; + assign valid = \ ; + assign wr_ack = \ ; + assign wr_data_count[5] = \ ; + assign wr_data_count[4] = \ ; + assign wr_data_count[3] = \ ; + assign wr_data_count[2] = \ ; + assign wr_data_count[1] = \ ; + assign wr_data_count[0] = \ ; + assign wr_rst_busy = \ ; + GND GND + (.G(\ )); + Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3_synth_7 inst_fifo_gen (.clk(clk), .din(din), .dout(dout), @@ -4476,8 +12318,8 @@ endmodule (* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "5" *) (* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *) (* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *) -(* C_WR_RESPONSE_LATENCY = "1" *) -module Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 +(* C_WR_RESPONSE_LATENCY = "1" *) (* ORIG_REF_NAME = "fifo_generator_v13_1_3" *) +module Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0 (backup, backup_marker, clk, @@ -5555,671 +13397,2336 @@ module Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 assign wr_rst_busy = \ ; GND GND (.G(\ )); - Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3_synth inst_fifo_gen + Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3_synth__parameterized0 inst_fifo_gen + (.clk(clk), + .din(din), + .dout(dout), + .empty(empty), + .full(full), + .rd_en(rd_en), + .rst(rst), + .wr_en(wr_en)); +endmodule + +module Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3_synth + (empty, + full, + dout, + clk, + rst, + din, + rd_en, + wr_en); + output empty; + output full; + output [4:0]dout; + input clk; + input rst; + input [4:0]din; + input rd_en; + input wr_en; + + wire clk; + wire [4:0]din; + wire [4:0]dout; + wire empty; + wire full; + wire rd_en; + wire rst; + wire wr_en; + + Arty_Z7_20_auto_pc_0_fifo_generator_top \gconvfifo.rf + (.clk(clk), + .din(din), + .dout(dout), + .empty(empty), + .full(full), + .rd_en(rd_en), + .rst(rst), + .wr_en(wr_en)); +endmodule + +(* ORIG_REF_NAME = "fifo_generator_v13_1_3_synth" *) +module Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3_synth_7 + (empty, + full, + dout, + clk, + rst, + din, + rd_en, + wr_en); + output empty; + output full; + output [4:0]dout; + input clk; + input rst; + input [4:0]din; + input rd_en; + input wr_en; + + wire clk; + wire [4:0]din; + wire [4:0]dout; + wire empty; + wire full; + wire rd_en; + wire rst; + wire wr_en; + + Arty_Z7_20_auto_pc_0_fifo_generator_top_8 \gconvfifo.rf + (.clk(clk), + .din(din), + .dout(dout), + .empty(empty), + .full(full), + .rd_en(rd_en), + .rst(rst), + .wr_en(wr_en)); +endmodule + +(* ORIG_REF_NAME = "fifo_generator_v13_1_3_synth" *) +module Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3_synth__parameterized0 + (empty, + full, + dout, + clk, + rst, + din, + rd_en, + wr_en); + output empty; + output full; + output [0:0]dout; + input clk; + input rst; + input [0:0]din; + input rd_en; + input wr_en; + + wire clk; + wire [0:0]din; + wire [0:0]dout; + wire empty; + wire full; + wire rd_en; + wire rst; + wire wr_en; + + Arty_Z7_20_auto_pc_0_fifo_generator_top__parameterized0 \gconvfifo.rf (.clk(clk), .din(din), .dout(dout), .empty(empty), - .full(full), - .rd_en(rd_en), - .rst(rst), + .full(full), + .rd_en(rd_en), + .rst(rst), + .wr_en(wr_en)); +endmodule + +module Arty_Z7_20_auto_pc_0_memory + (dout, + E, + clk, + EN, + din, + \gc0.count_d1_reg[4] , + I55, + \gpregsm1.curr_fwft_state_reg[1] ); + output [4:0]dout; + input [0:0]E; + input clk; + input EN; + input [4:0]din; + input [4:0]\gc0.count_d1_reg[4] ; + input [4:0]I55; + input [0:0]\gpregsm1.curr_fwft_state_reg[1] ; + + wire [0:0]E; + wire EN; + wire [4:0]I55; + wire clk; + wire [4:0]din; + wire [4:0]dout; + wire [4:0]dout_i; + wire [4:0]\gc0.count_d1_reg[4] ; + wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ; + + Arty_Z7_20_auto_pc_0_dmem \gdm.dm_gen.dm + (.EN(EN), + .I55(I55), + .clk(clk), + .din(din), + .dout_i(dout_i), + .\gc0.count_d1_reg[4] (\gc0.count_d1_reg[4] ), + .\gpregsm1.curr_fwft_state_reg[1] (\gpregsm1.curr_fwft_state_reg[1] )); + FDRE #( + .INIT(1'b0)) + \goreg_dm.dout_i_reg[0] + (.C(clk), + .CE(E), + .D(dout_i[0]), + .Q(dout[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \goreg_dm.dout_i_reg[1] + (.C(clk), + .CE(E), + .D(dout_i[1]), + .Q(dout[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \goreg_dm.dout_i_reg[2] + (.C(clk), + .CE(E), + .D(dout_i[2]), + .Q(dout[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \goreg_dm.dout_i_reg[3] + (.C(clk), + .CE(E), + .D(dout_i[3]), + .Q(dout[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \goreg_dm.dout_i_reg[4] + (.C(clk), + .CE(E), + .D(dout_i[4]), + .Q(dout[4]), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "memory" *) +module Arty_Z7_20_auto_pc_0_memory_12 + (dout, + E, + clk, + EN, + din, + \gc0.count_d1_reg[4] , + I54, + \gpregsm1.curr_fwft_state_reg[1] ); + output [4:0]dout; + input [0:0]E; + input clk; + input EN; + input [4:0]din; + input [4:0]\gc0.count_d1_reg[4] ; + input [4:0]I54; + input [0:0]\gpregsm1.curr_fwft_state_reg[1] ; + + wire [0:0]E; + wire EN; + wire [4:0]I54; + wire clk; + wire [4:0]din; + wire [4:0]dout; + wire [4:0]dout_i; + wire [4:0]\gc0.count_d1_reg[4] ; + wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ; + + Arty_Z7_20_auto_pc_0_dmem_20 \gdm.dm_gen.dm + (.EN(EN), + .I54(I54), + .clk(clk), + .din(din), + .dout_i(dout_i), + .\gc0.count_d1_reg[4] (\gc0.count_d1_reg[4] ), + .\gpregsm1.curr_fwft_state_reg[1] (\gpregsm1.curr_fwft_state_reg[1] )); + FDRE #( + .INIT(1'b0)) + \goreg_dm.dout_i_reg[0] + (.C(clk), + .CE(E), + .D(dout_i[0]), + .Q(dout[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \goreg_dm.dout_i_reg[1] + (.C(clk), + .CE(E), + .D(dout_i[1]), + .Q(dout[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \goreg_dm.dout_i_reg[2] + (.C(clk), + .CE(E), + .D(dout_i[2]), + .Q(dout[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \goreg_dm.dout_i_reg[3] + (.C(clk), + .CE(E), + .D(dout_i[3]), + .Q(dout[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \goreg_dm.dout_i_reg[4] + (.C(clk), + .CE(E), + .D(dout_i[4]), + .Q(dout[4]), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "memory" *) +module Arty_Z7_20_auto_pc_0_memory__parameterized0 + (p_0_out, + dout_i, + dout, + clk, + din, + E, + Q, + \gc0.count_d1_reg[4] , + \gpregsm1.curr_fwft_state_reg[1] , + out, + \gpregsm1.curr_fwft_state_reg[1]_0 , + rd_en); + output p_0_out; + output dout_i; + output [0:0]dout; + input clk; + input [0:0]din; + input [0:0]E; + input [4:0]Q; + input [4:0]\gc0.count_d1_reg[4] ; + input \gpregsm1.curr_fwft_state_reg[1] ; + input [0:0]out; + input [1:0]\gpregsm1.curr_fwft_state_reg[1]_0 ; + input rd_en; + + wire [0:0]E; + wire [4:0]Q; + wire clk; + wire [0:0]din; + wire [0:0]dout; + wire dout_i; + wire [4:0]\gc0.count_d1_reg[4] ; + wire \gdm.dm_gen.dm_n_2 ; + wire \gpregsm1.curr_fwft_state_reg[1] ; + wire [1:0]\gpregsm1.curr_fwft_state_reg[1]_0 ; + wire [0:0]out; + wire p_0_out; + wire rd_en; + + Arty_Z7_20_auto_pc_0_dmem__parameterized0 \gdm.dm_gen.dm + (.E(E), + .Q(Q), + .clk(clk), + .din(din), + .dout(dout), + .dout_i(dout_i), + .\gc0.count_d1_reg[4] (\gc0.count_d1_reg[4] ), + .\goreg_dm.dout_i_reg[0] (\gdm.dm_gen.dm_n_2 ), + .\gpregsm1.curr_fwft_state_reg[1] (\gpregsm1.curr_fwft_state_reg[1] ), + .\gpregsm1.curr_fwft_state_reg[1]_0 (\gpregsm1.curr_fwft_state_reg[1]_0 ), + .out(out), + .p_0_out(p_0_out), + .rd_en(rd_en)); + FDRE #( + .INIT(1'b0)) + \goreg_dm.dout_i_reg[0] + (.C(clk), + .CE(1'b1), + .D(\gdm.dm_gen.dm_n_2 ), + .Q(dout), + .R(1'b0)); +endmodule + +module Arty_Z7_20_auto_pc_0_rd_bin_cntr + (Q, + ram_empty_fb_i_reg, + ram_empty_fb_i_reg_0, + \gpr1.dout_i_reg[1] , + wr_en, + ram_full_fb_i_reg, + out, + \gcc0.gc0.count_d1_reg[4] , + \gpregsm1.curr_fwft_state_reg[0] , + \gcc0.gc0.count_d1_reg[2] , + E, + clk, + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ); + output [2:0]Q; + output ram_empty_fb_i_reg; + output ram_empty_fb_i_reg_0; + output [4:0]\gpr1.dout_i_reg[1] ; + input wr_en; + input ram_full_fb_i_reg; + input out; + input [4:0]\gcc0.gc0.count_d1_reg[4] ; + input \gpregsm1.curr_fwft_state_reg[0] ; + input \gcc0.gc0.count_d1_reg[2] ; + input [0:0]E; + input clk; + input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ; + + wire [0:0]E; + wire [2:0]Q; + wire clk; + wire \gcc0.gc0.count_d1_reg[2] ; + wire [4:0]\gcc0.gc0.count_d1_reg[4] ; + wire [4:0]\gpr1.dout_i_reg[1] ; + wire \gpregsm1.curr_fwft_state_reg[0] ; + wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ; + wire out; + wire [4:0]plusOp; + wire ram_empty_fb_i_i_2_n_0; + wire ram_empty_fb_i_i_6_n_0; + wire ram_empty_fb_i_reg; + wire ram_empty_fb_i_reg_0; + wire ram_full_fb_i_reg; + wire [4:3]rd_pntr_plus1; + wire wr_en; + + LUT1 #( + .INIT(2'h1)) + \gc0.count[0]_i_1 + (.I0(Q[0]), + .O(plusOp[0])); + (* SOFT_HLUTNM = "soft_lutpair37" *) + LUT2 #( + .INIT(4'h6)) + \gc0.count[1]_i_1 + (.I0(Q[0]), + .I1(Q[1]), + .O(plusOp[1])); + (* SOFT_HLUTNM = "soft_lutpair37" *) + LUT3 #( + .INIT(8'h78)) + \gc0.count[2]_i_1 + (.I0(Q[1]), + .I1(Q[0]), + .I2(Q[2]), + .O(plusOp[2])); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT4 #( + .INIT(16'h7F80)) + \gc0.count[3]_i_1 + (.I0(Q[2]), + .I1(Q[0]), + .I2(Q[1]), + .I3(rd_pntr_plus1[3]), + .O(plusOp[3])); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \gc0.count[4]_i_1 + (.I0(rd_pntr_plus1[3]), + .I1(Q[1]), + .I2(Q[0]), + .I3(Q[2]), + .I4(rd_pntr_plus1[4]), + .O(plusOp[4])); + FDCE #( + .INIT(1'b0)) + \gc0.count_d1_reg[0] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), + .D(Q[0]), + .Q(\gpr1.dout_i_reg[1] [0])); + FDCE #( + .INIT(1'b0)) + \gc0.count_d1_reg[1] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), + .D(Q[1]), + .Q(\gpr1.dout_i_reg[1] [1])); + FDCE #( + .INIT(1'b0)) + \gc0.count_d1_reg[2] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), + .D(Q[2]), + .Q(\gpr1.dout_i_reg[1] [2])); + FDCE #( + .INIT(1'b0)) + \gc0.count_d1_reg[3] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), + .D(rd_pntr_plus1[3]), + .Q(\gpr1.dout_i_reg[1] [3])); + FDCE #( + .INIT(1'b0)) + \gc0.count_d1_reg[4] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), + .D(rd_pntr_plus1[4]), + .Q(\gpr1.dout_i_reg[1] [4])); + FDPE #( + .INIT(1'b1)) + \gc0.count_reg[0] + (.C(clk), + .CE(E), + .D(plusOp[0]), + .PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), + .Q(Q[0])); + FDCE #( + .INIT(1'b0)) + \gc0.count_reg[1] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), + .D(plusOp[1]), + .Q(Q[1])); + FDCE #( + .INIT(1'b0)) + \gc0.count_reg[2] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), + .D(plusOp[2]), + .Q(Q[2])); + FDCE #( + .INIT(1'b0)) + \gc0.count_reg[3] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), + .D(plusOp[3]), + .Q(rd_pntr_plus1[3])); + FDCE #( + .INIT(1'b0)) + \gc0.count_reg[4] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), + .D(plusOp[4]), + .Q(rd_pntr_plus1[4])); + LUT5 #( + .INIT(32'hFFA2F3A2)) + ram_empty_fb_i_i_1 + (.I0(ram_empty_fb_i_i_2_n_0), + .I1(wr_en), + .I2(ram_full_fb_i_reg), + .I3(out), + .I4(ram_empty_fb_i_reg_0), + .O(ram_empty_fb_i_reg)); + LUT6 #( + .INIT(64'h9009000000000000)) + ram_empty_fb_i_i_2 + (.I0(rd_pntr_plus1[3]), + .I1(\gcc0.gc0.count_d1_reg[4] [3]), + .I2(rd_pntr_plus1[4]), + .I3(\gcc0.gc0.count_d1_reg[4] [4]), + .I4(\gpregsm1.curr_fwft_state_reg[0] ), + .I5(\gcc0.gc0.count_d1_reg[2] ), + .O(ram_empty_fb_i_i_2_n_0)); + LUT5 #( + .INIT(32'hBEFFFFBE)) + ram_empty_fb_i_i_3 + (.I0(ram_empty_fb_i_i_6_n_0), + .I1(\gpr1.dout_i_reg[1] [2]), + .I2(\gcc0.gc0.count_d1_reg[4] [2]), + .I3(\gpr1.dout_i_reg[1] [1]), + .I4(\gcc0.gc0.count_d1_reg[4] [1]), + .O(ram_empty_fb_i_reg_0)); + LUT6 #( + .INIT(64'h6FF6FFFFFFFF6FF6)) + ram_empty_fb_i_i_6 + (.I0(\gpr1.dout_i_reg[1] [4]), + .I1(\gcc0.gc0.count_d1_reg[4] [4]), + .I2(\gpr1.dout_i_reg[1] [3]), + .I3(\gcc0.gc0.count_d1_reg[4] [3]), + .I4(\gcc0.gc0.count_d1_reg[4] [0]), + .I5(\gpr1.dout_i_reg[1] [0]), + .O(ram_empty_fb_i_i_6_n_0)); +endmodule + +(* ORIG_REF_NAME = "rd_bin_cntr" *) +module Arty_Z7_20_auto_pc_0_rd_bin_cntr_25 + (Q, + ram_empty_fb_i_reg, + ram_empty_fb_i_reg_0, + \gpr1.dout_i_reg[1] , + wr_en, + ram_full_fb_i_reg, + out, + \gcc0.gc0.count_d1_reg[4] , + \gpregsm1.curr_fwft_state_reg[0] , + \gcc0.gc0.count_d1_reg[2] , + E, + clk, + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ); + output [2:0]Q; + output ram_empty_fb_i_reg; + output ram_empty_fb_i_reg_0; + output [4:0]\gpr1.dout_i_reg[1] ; + input wr_en; + input ram_full_fb_i_reg; + input out; + input [4:0]\gcc0.gc0.count_d1_reg[4] ; + input \gpregsm1.curr_fwft_state_reg[0] ; + input \gcc0.gc0.count_d1_reg[2] ; + input [0:0]E; + input clk; + input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ; + + wire [0:0]E; + wire [2:0]Q; + wire clk; + wire \gcc0.gc0.count_d1_reg[2] ; + wire [4:0]\gcc0.gc0.count_d1_reg[4] ; + wire [4:0]\gpr1.dout_i_reg[1] ; + wire \gpregsm1.curr_fwft_state_reg[0] ; + wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ; + wire out; + wire [4:0]plusOp; + wire ram_empty_fb_i_i_2_n_0; + wire ram_empty_fb_i_i_6_n_0; + wire ram_empty_fb_i_reg; + wire ram_empty_fb_i_reg_0; + wire ram_full_fb_i_reg; + wire [4:3]rd_pntr_plus1; + wire wr_en; + + LUT1 #( + .INIT(2'h1)) + \gc0.count[0]_i_1 + (.I0(Q[0]), + .O(plusOp[0])); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT2 #( + .INIT(4'h6)) + \gc0.count[1]_i_1 + (.I0(Q[0]), + .I1(Q[1]), + .O(plusOp[1])); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT3 #( + .INIT(8'h78)) + \gc0.count[2]_i_1 + (.I0(Q[1]), + .I1(Q[0]), + .I2(Q[2]), + .O(plusOp[2])); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT4 #( + .INIT(16'h7F80)) + \gc0.count[3]_i_1 + (.I0(Q[2]), + .I1(Q[0]), + .I2(Q[1]), + .I3(rd_pntr_plus1[3]), + .O(plusOp[3])); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \gc0.count[4]_i_1 + (.I0(rd_pntr_plus1[3]), + .I1(Q[1]), + .I2(Q[0]), + .I3(Q[2]), + .I4(rd_pntr_plus1[4]), + .O(plusOp[4])); + FDCE #( + .INIT(1'b0)) + \gc0.count_d1_reg[0] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), + .D(Q[0]), + .Q(\gpr1.dout_i_reg[1] [0])); + FDCE #( + .INIT(1'b0)) + \gc0.count_d1_reg[1] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), + .D(Q[1]), + .Q(\gpr1.dout_i_reg[1] [1])); + FDCE #( + .INIT(1'b0)) + \gc0.count_d1_reg[2] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), + .D(Q[2]), + .Q(\gpr1.dout_i_reg[1] [2])); + FDCE #( + .INIT(1'b0)) + \gc0.count_d1_reg[3] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), + .D(rd_pntr_plus1[3]), + .Q(\gpr1.dout_i_reg[1] [3])); + FDCE #( + .INIT(1'b0)) + \gc0.count_d1_reg[4] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), + .D(rd_pntr_plus1[4]), + .Q(\gpr1.dout_i_reg[1] [4])); + FDPE #( + .INIT(1'b1)) + \gc0.count_reg[0] + (.C(clk), + .CE(E), + .D(plusOp[0]), + .PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), + .Q(Q[0])); + FDCE #( + .INIT(1'b0)) + \gc0.count_reg[1] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), + .D(plusOp[1]), + .Q(Q[1])); + FDCE #( + .INIT(1'b0)) + \gc0.count_reg[2] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), + .D(plusOp[2]), + .Q(Q[2])); + FDCE #( + .INIT(1'b0)) + \gc0.count_reg[3] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), + .D(plusOp[3]), + .Q(rd_pntr_plus1[3])); + FDCE #( + .INIT(1'b0)) + \gc0.count_reg[4] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), + .D(plusOp[4]), + .Q(rd_pntr_plus1[4])); + LUT5 #( + .INIT(32'hFFA2F3A2)) + ram_empty_fb_i_i_1 + (.I0(ram_empty_fb_i_i_2_n_0), + .I1(wr_en), + .I2(ram_full_fb_i_reg), + .I3(out), + .I4(ram_empty_fb_i_reg_0), + .O(ram_empty_fb_i_reg)); + LUT6 #( + .INIT(64'h9009000000000000)) + ram_empty_fb_i_i_2 + (.I0(rd_pntr_plus1[3]), + .I1(\gcc0.gc0.count_d1_reg[4] [3]), + .I2(rd_pntr_plus1[4]), + .I3(\gcc0.gc0.count_d1_reg[4] [4]), + .I4(\gpregsm1.curr_fwft_state_reg[0] ), + .I5(\gcc0.gc0.count_d1_reg[2] ), + .O(ram_empty_fb_i_i_2_n_0)); + LUT5 #( + .INIT(32'hBEFFFFBE)) + ram_empty_fb_i_i_3 + (.I0(ram_empty_fb_i_i_6_n_0), + .I1(\gpr1.dout_i_reg[1] [2]), + .I2(\gcc0.gc0.count_d1_reg[4] [2]), + .I3(\gpr1.dout_i_reg[1] [1]), + .I4(\gcc0.gc0.count_d1_reg[4] [1]), + .O(ram_empty_fb_i_reg_0)); + LUT6 #( + .INIT(64'h6FF6FFFFFFFF6FF6)) + ram_empty_fb_i_i_6 + (.I0(\gpr1.dout_i_reg[1] [4]), + .I1(\gcc0.gc0.count_d1_reg[4] [4]), + .I2(\gpr1.dout_i_reg[1] [3]), + .I3(\gcc0.gc0.count_d1_reg[4] [3]), + .I4(\gcc0.gc0.count_d1_reg[4] [0]), + .I5(\gpr1.dout_i_reg[1] [0]), + .O(ram_empty_fb_i_i_6_n_0)); +endmodule + +(* ORIG_REF_NAME = "rd_bin_cntr" *) +module Arty_Z7_20_auto_pc_0_rd_bin_cntr_39 + (Q, + ram_empty_fb_i_reg, + ram_empty_fb_i_reg_0, + \gpr1.dout_i_reg[0] , + wr_en, + ram_full_fb_i_reg, + out, + \gcc0.gc0.count_d1_reg[4] , + \gpregsm1.curr_fwft_state_reg[0] , + \gcc0.gc0.count_d1_reg[2] , + E, + clk, + AR); + output [2:0]Q; + output ram_empty_fb_i_reg; + output ram_empty_fb_i_reg_0; + output [4:0]\gpr1.dout_i_reg[0] ; + input wr_en; + input ram_full_fb_i_reg; + input out; + input [4:0]\gcc0.gc0.count_d1_reg[4] ; + input \gpregsm1.curr_fwft_state_reg[0] ; + input \gcc0.gc0.count_d1_reg[2] ; + input [0:0]E; + input clk; + input [0:0]AR; + + wire [0:0]AR; + wire [0:0]E; + wire [2:0]Q; + wire clk; + wire \gcc0.gc0.count_d1_reg[2] ; + wire [4:0]\gcc0.gc0.count_d1_reg[4] ; + wire [4:0]\gpr1.dout_i_reg[0] ; + wire \gpregsm1.curr_fwft_state_reg[0] ; + wire out; + wire [4:0]plusOp; + wire ram_empty_fb_i_i_2_n_0; + wire ram_empty_fb_i_i_6_n_0; + wire ram_empty_fb_i_reg; + wire ram_empty_fb_i_reg_0; + wire ram_full_fb_i_reg; + wire [4:3]rd_pntr_plus1; + wire wr_en; + + LUT1 #( + .INIT(2'h1)) + \gc0.count[0]_i_1 + (.I0(Q[0]), + .O(plusOp[0])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT2 #( + .INIT(4'h6)) + \gc0.count[1]_i_1 + (.I0(Q[0]), + .I1(Q[1]), + .O(plusOp[1])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT3 #( + .INIT(8'h78)) + \gc0.count[2]_i_1 + (.I0(Q[1]), + .I1(Q[0]), + .I2(Q[2]), + .O(plusOp[2])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'h7F80)) + \gc0.count[3]_i_1 + (.I0(Q[2]), + .I1(Q[0]), + .I2(Q[1]), + .I3(rd_pntr_plus1[3]), + .O(plusOp[3])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \gc0.count[4]_i_1 + (.I0(rd_pntr_plus1[3]), + .I1(Q[1]), + .I2(Q[0]), + .I3(Q[2]), + .I4(rd_pntr_plus1[4]), + .O(plusOp[4])); + FDCE #( + .INIT(1'b0)) + \gc0.count_d1_reg[0] + (.C(clk), + .CE(E), + .CLR(AR), + .D(Q[0]), + .Q(\gpr1.dout_i_reg[0] [0])); + FDCE #( + .INIT(1'b0)) + \gc0.count_d1_reg[1] + (.C(clk), + .CE(E), + .CLR(AR), + .D(Q[1]), + .Q(\gpr1.dout_i_reg[0] [1])); + FDCE #( + .INIT(1'b0)) + \gc0.count_d1_reg[2] + (.C(clk), + .CE(E), + .CLR(AR), + .D(Q[2]), + .Q(\gpr1.dout_i_reg[0] [2])); + FDCE #( + .INIT(1'b0)) + \gc0.count_d1_reg[3] + (.C(clk), + .CE(E), + .CLR(AR), + .D(rd_pntr_plus1[3]), + .Q(\gpr1.dout_i_reg[0] [3])); + FDCE #( + .INIT(1'b0)) + \gc0.count_d1_reg[4] + (.C(clk), + .CE(E), + .CLR(AR), + .D(rd_pntr_plus1[4]), + .Q(\gpr1.dout_i_reg[0] [4])); + FDPE #( + .INIT(1'b1)) + \gc0.count_reg[0] + (.C(clk), + .CE(E), + .D(plusOp[0]), + .PRE(AR), + .Q(Q[0])); + FDCE #( + .INIT(1'b0)) + \gc0.count_reg[1] + (.C(clk), + .CE(E), + .CLR(AR), + .D(plusOp[1]), + .Q(Q[1])); + FDCE #( + .INIT(1'b0)) + \gc0.count_reg[2] + (.C(clk), + .CE(E), + .CLR(AR), + .D(plusOp[2]), + .Q(Q[2])); + FDCE #( + .INIT(1'b0)) + \gc0.count_reg[3] + (.C(clk), + .CE(E), + .CLR(AR), + .D(plusOp[3]), + .Q(rd_pntr_plus1[3])); + FDCE #( + .INIT(1'b0)) + \gc0.count_reg[4] + (.C(clk), + .CE(E), + .CLR(AR), + .D(plusOp[4]), + .Q(rd_pntr_plus1[4])); + LUT5 #( + .INIT(32'hFFA2F3A2)) + ram_empty_fb_i_i_1 + (.I0(ram_empty_fb_i_i_2_n_0), + .I1(wr_en), + .I2(ram_full_fb_i_reg), + .I3(out), + .I4(ram_empty_fb_i_reg_0), + .O(ram_empty_fb_i_reg)); + LUT6 #( + .INIT(64'h9009000000000000)) + ram_empty_fb_i_i_2 + (.I0(rd_pntr_plus1[3]), + .I1(\gcc0.gc0.count_d1_reg[4] [3]), + .I2(rd_pntr_plus1[4]), + .I3(\gcc0.gc0.count_d1_reg[4] [4]), + .I4(\gpregsm1.curr_fwft_state_reg[0] ), + .I5(\gcc0.gc0.count_d1_reg[2] ), + .O(ram_empty_fb_i_i_2_n_0)); + LUT5 #( + .INIT(32'hBEFFFFBE)) + ram_empty_fb_i_i_3 + (.I0(ram_empty_fb_i_i_6_n_0), + .I1(\gpr1.dout_i_reg[0] [2]), + .I2(\gcc0.gc0.count_d1_reg[4] [2]), + .I3(\gpr1.dout_i_reg[0] [1]), + .I4(\gcc0.gc0.count_d1_reg[4] [1]), + .O(ram_empty_fb_i_reg_0)); + LUT6 #( + .INIT(64'h6FF6FFFFFFFF6FF6)) + ram_empty_fb_i_i_6 + (.I0(\gpr1.dout_i_reg[0] [4]), + .I1(\gcc0.gc0.count_d1_reg[4] [4]), + .I2(\gpr1.dout_i_reg[0] [3]), + .I3(\gcc0.gc0.count_d1_reg[4] [3]), + .I4(\gcc0.gc0.count_d1_reg[4] [0]), + .I5(\gpr1.dout_i_reg[0] [0]), + .O(ram_empty_fb_i_i_6_n_0)); +endmodule + +module Arty_Z7_20_auto_pc_0_rd_fwft + (empty, + E, + ram_empty_fb_i_reg, + \goreg_dm.dout_i_reg[4] , + ram_full_fb_i_reg, + clk, + out, + rd_en, + ram_empty_fb_i_reg_0); + output empty; + output [0:0]E; + output ram_empty_fb_i_reg; + output [0:0]\goreg_dm.dout_i_reg[4] ; + output ram_full_fb_i_reg; + input clk; + input [1:0]out; + input rd_en; + input ram_empty_fb_i_reg_0; + + wire [0:0]E; + (* DONT_TOUCH *) wire aempty_fwft_fb_i; + (* DONT_TOUCH *) wire aempty_fwft_i; + wire aempty_fwft_i0; + wire clk; + (* DONT_TOUCH *) wire [1:0]curr_fwft_state; + (* DONT_TOUCH *) wire empty_fwft_fb_i; + (* DONT_TOUCH *) wire empty_fwft_fb_o_i; + wire empty_fwft_fb_o_i0; + (* DONT_TOUCH *) wire empty_fwft_i; + wire empty_fwft_i0; + wire [0:0]\goreg_dm.dout_i_reg[4] ; + wire [1:0]next_fwft_state; + wire [1:0]out; + wire ram_empty_fb_i_reg; + wire ram_empty_fb_i_reg_0; + wire ram_full_fb_i_reg; + wire rd_en; + (* DONT_TOUCH *) wire user_valid; + + assign empty = empty_fwft_i; + LUT5 #( + .INIT(32'hFAEF8000)) + aempty_fwft_fb_i_i_1 + (.I0(ram_empty_fb_i_reg_0), + .I1(rd_en), + .I2(curr_fwft_state[0]), + .I3(curr_fwft_state[1]), + .I4(aempty_fwft_fb_i), + .O(aempty_fwft_i0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + aempty_fwft_fb_i_reg + (.C(clk), + .CE(1'b1), + .D(aempty_fwft_i0), + .PRE(out[1]), + .Q(aempty_fwft_fb_i)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + aempty_fwft_i_reg + (.C(clk), + .CE(1'b1), + .D(aempty_fwft_i0), + .PRE(out[1]), + .Q(aempty_fwft_i)); + LUT4 #( + .INIT(16'hB2A2)) + empty_fwft_fb_i_i_1 + (.I0(empty_fwft_fb_i), + .I1(curr_fwft_state[1]), + .I2(curr_fwft_state[0]), + .I3(rd_en), + .O(empty_fwft_i0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + empty_fwft_fb_i_reg + (.C(clk), + .CE(1'b1), + .D(empty_fwft_i0), + .PRE(out[1]), + .Q(empty_fwft_fb_i)); + LUT4 #( + .INIT(16'hB2A2)) + empty_fwft_fb_o_i_i_1 + (.I0(empty_fwft_fb_o_i), + .I1(curr_fwft_state[1]), + .I2(curr_fwft_state[0]), + .I3(rd_en), + .O(empty_fwft_fb_o_i0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + empty_fwft_fb_o_i_reg + (.C(clk), + .CE(1'b1), + .D(empty_fwft_fb_o_i0), + .PRE(out[1]), + .Q(empty_fwft_fb_o_i)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + empty_fwft_i_reg + (.C(clk), + .CE(1'b1), + .D(empty_fwft_i0), + .PRE(out[1]), + .Q(empty_fwft_i)); + LUT4 #( + .INIT(16'h00DF)) + \gc0.count_d1[4]_i_1 + (.I0(curr_fwft_state[1]), + .I1(rd_en), + .I2(curr_fwft_state[0]), + .I3(ram_empty_fb_i_reg_0), + .O(E)); + LUT4 #( + .INIT(16'h4404)) + \goreg_dm.dout_i[4]_i_1 + (.I0(out[0]), + .I1(curr_fwft_state[1]), + .I2(curr_fwft_state[0]), + .I3(rd_en), + .O(\goreg_dm.dout_i_reg[4] )); + LUT3 #( + .INIT(8'hAE)) + \gpregsm1.curr_fwft_state[0]_i_1 + (.I0(curr_fwft_state[1]), + .I1(curr_fwft_state[0]), + .I2(rd_en), + .O(next_fwft_state[0])); + LUT4 #( + .INIT(16'h20FF)) + \gpregsm1.curr_fwft_state[1]_i_1 + (.I0(curr_fwft_state[1]), + .I1(rd_en), + .I2(curr_fwft_state[0]), + .I3(ram_empty_fb_i_reg_0), + .O(next_fwft_state[1])); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDCE #( + .INIT(1'b0)) + \gpregsm1.curr_fwft_state_reg[0] + (.C(clk), + .CE(1'b1), + .CLR(out[1]), + .D(next_fwft_state[0]), + .Q(curr_fwft_state[0])); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDCE #( + .INIT(1'b0)) + \gpregsm1.curr_fwft_state_reg[1] + (.C(clk), + .CE(1'b1), + .CLR(out[1]), + .D(next_fwft_state[1]), + .Q(curr_fwft_state[1])); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDCE #( + .INIT(1'b0)) + \gpregsm1.user_valid_reg + (.C(clk), + .CE(1'b1), + .CLR(out[1]), + .D(next_fwft_state[0]), + .Q(user_valid)); + LUT3 #( + .INIT(8'hDF)) + ram_empty_fb_i_i_4 + (.I0(curr_fwft_state[0]), + .I1(rd_en), + .I2(curr_fwft_state[1]), + .O(ram_empty_fb_i_reg)); + LUT4 #( + .INIT(16'hFF08)) + ram_full_fb_i_i_3 + (.I0(curr_fwft_state[0]), + .I1(curr_fwft_state[1]), + .I2(rd_en), + .I3(ram_empty_fb_i_reg_0), + .O(ram_full_fb_i_reg)); +endmodule + +(* ORIG_REF_NAME = "rd_fwft" *) +module Arty_Z7_20_auto_pc_0_rd_fwft_23 + (empty, + E, + ram_empty_fb_i_reg, + \goreg_dm.dout_i_reg[4] , + ram_full_fb_i_reg, + clk, + out, + rd_en, + ram_empty_fb_i_reg_0); + output empty; + output [0:0]E; + output ram_empty_fb_i_reg; + output [0:0]\goreg_dm.dout_i_reg[4] ; + output ram_full_fb_i_reg; + input clk; + input [1:0]out; + input rd_en; + input ram_empty_fb_i_reg_0; + + wire [0:0]E; + (* DONT_TOUCH *) wire aempty_fwft_fb_i; + (* DONT_TOUCH *) wire aempty_fwft_i; + wire aempty_fwft_i0; + wire clk; + (* DONT_TOUCH *) wire [1:0]curr_fwft_state; + (* DONT_TOUCH *) wire empty_fwft_fb_i; + (* DONT_TOUCH *) wire empty_fwft_fb_o_i; + wire empty_fwft_fb_o_i0; + (* DONT_TOUCH *) wire empty_fwft_i; + wire empty_fwft_i0; + wire [0:0]\goreg_dm.dout_i_reg[4] ; + wire [1:0]next_fwft_state; + wire [1:0]out; + wire ram_empty_fb_i_reg; + wire ram_empty_fb_i_reg_0; + wire ram_full_fb_i_reg; + wire rd_en; + (* DONT_TOUCH *) wire user_valid; + + assign empty = empty_fwft_i; + LUT5 #( + .INIT(32'hFAEF8000)) + aempty_fwft_fb_i_i_1 + (.I0(ram_empty_fb_i_reg_0), + .I1(rd_en), + .I2(curr_fwft_state[0]), + .I3(curr_fwft_state[1]), + .I4(aempty_fwft_fb_i), + .O(aempty_fwft_i0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + aempty_fwft_fb_i_reg + (.C(clk), + .CE(1'b1), + .D(aempty_fwft_i0), + .PRE(out[1]), + .Q(aempty_fwft_fb_i)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + aempty_fwft_i_reg + (.C(clk), + .CE(1'b1), + .D(aempty_fwft_i0), + .PRE(out[1]), + .Q(aempty_fwft_i)); + LUT4 #( + .INIT(16'hB2A2)) + empty_fwft_fb_i_i_1 + (.I0(empty_fwft_fb_i), + .I1(curr_fwft_state[1]), + .I2(curr_fwft_state[0]), + .I3(rd_en), + .O(empty_fwft_i0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + empty_fwft_fb_i_reg + (.C(clk), + .CE(1'b1), + .D(empty_fwft_i0), + .PRE(out[1]), + .Q(empty_fwft_fb_i)); + LUT4 #( + .INIT(16'hB2A2)) + empty_fwft_fb_o_i_i_1 + (.I0(empty_fwft_fb_o_i), + .I1(curr_fwft_state[1]), + .I2(curr_fwft_state[0]), + .I3(rd_en), + .O(empty_fwft_fb_o_i0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + empty_fwft_fb_o_i_reg + (.C(clk), + .CE(1'b1), + .D(empty_fwft_fb_o_i0), + .PRE(out[1]), + .Q(empty_fwft_fb_o_i)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + empty_fwft_i_reg + (.C(clk), + .CE(1'b1), + .D(empty_fwft_i0), + .PRE(out[1]), + .Q(empty_fwft_i)); + LUT4 #( + .INIT(16'h00DF)) + \gc0.count_d1[4]_i_1 + (.I0(curr_fwft_state[1]), + .I1(rd_en), + .I2(curr_fwft_state[0]), + .I3(ram_empty_fb_i_reg_0), + .O(E)); + LUT4 #( + .INIT(16'h4404)) + \goreg_dm.dout_i[4]_i_1 + (.I0(out[0]), + .I1(curr_fwft_state[1]), + .I2(curr_fwft_state[0]), + .I3(rd_en), + .O(\goreg_dm.dout_i_reg[4] )); + LUT3 #( + .INIT(8'hAE)) + \gpregsm1.curr_fwft_state[0]_i_1 + (.I0(curr_fwft_state[1]), + .I1(curr_fwft_state[0]), + .I2(rd_en), + .O(next_fwft_state[0])); + LUT4 #( + .INIT(16'h20FF)) + \gpregsm1.curr_fwft_state[1]_i_1 + (.I0(curr_fwft_state[1]), + .I1(rd_en), + .I2(curr_fwft_state[0]), + .I3(ram_empty_fb_i_reg_0), + .O(next_fwft_state[1])); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDCE #( + .INIT(1'b0)) + \gpregsm1.curr_fwft_state_reg[0] + (.C(clk), + .CE(1'b1), + .CLR(out[1]), + .D(next_fwft_state[0]), + .Q(curr_fwft_state[0])); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDCE #( + .INIT(1'b0)) + \gpregsm1.curr_fwft_state_reg[1] + (.C(clk), + .CE(1'b1), + .CLR(out[1]), + .D(next_fwft_state[1]), + .Q(curr_fwft_state[1])); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDCE #( + .INIT(1'b0)) + \gpregsm1.user_valid_reg + (.C(clk), + .CE(1'b1), + .CLR(out[1]), + .D(next_fwft_state[0]), + .Q(user_valid)); + LUT3 #( + .INIT(8'hDF)) + ram_empty_fb_i_i_4 + (.I0(curr_fwft_state[0]), + .I1(rd_en), + .I2(curr_fwft_state[1]), + .O(ram_empty_fb_i_reg)); + LUT4 #( + .INIT(16'hFF08)) + ram_full_fb_i_i_3 + (.I0(curr_fwft_state[0]), + .I1(curr_fwft_state[1]), + .I2(rd_en), + .I3(ram_empty_fb_i_reg_0), + .O(ram_full_fb_i_reg)); +endmodule + +(* ORIG_REF_NAME = "rd_fwft" *) +module Arty_Z7_20_auto_pc_0_rd_fwft_37 + (out, + empty, + \gpr1.dout_i_reg[0] , + E, + ram_empty_fb_i_reg, + ram_full_fb_i_reg, + clk, + AR, + p_0_out, + rd_en, + ram_empty_fb_i_reg_0, + dout_i); + output [1:0]out; + output empty; + output \gpr1.dout_i_reg[0] ; + output [0:0]E; + output ram_empty_fb_i_reg; + output ram_full_fb_i_reg; + input clk; + input [0:0]AR; + input p_0_out; + input rd_en; + input ram_empty_fb_i_reg_0; + input dout_i; + + wire [0:0]AR; + wire [0:0]E; + (* DONT_TOUCH *) wire aempty_fwft_fb_i; + (* DONT_TOUCH *) wire aempty_fwft_i; + wire aempty_fwft_i0; + wire clk; + (* DONT_TOUCH *) wire [1:0]curr_fwft_state; + wire dout_i; + (* DONT_TOUCH *) wire empty_fwft_fb_i; + (* DONT_TOUCH *) wire empty_fwft_fb_o_i; + wire empty_fwft_fb_o_i0; + (* DONT_TOUCH *) wire empty_fwft_i; + wire empty_fwft_i0; + wire \gpr1.dout_i_reg[0] ; + wire [1:0]next_fwft_state; + wire p_0_out; + wire ram_empty_fb_i_reg; + wire ram_empty_fb_i_reg_0; + wire ram_full_fb_i_reg; + wire rd_en; + (* DONT_TOUCH *) wire user_valid; + + assign empty = empty_fwft_i; + assign out[1:0] = curr_fwft_state; + LUT5 #( + .INIT(32'hFAEF8000)) + aempty_fwft_fb_i_i_1 + (.I0(ram_empty_fb_i_reg_0), + .I1(rd_en), + .I2(curr_fwft_state[0]), + .I3(curr_fwft_state[1]), + .I4(aempty_fwft_fb_i), + .O(aempty_fwft_i0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + aempty_fwft_fb_i_reg + (.C(clk), + .CE(1'b1), + .D(aempty_fwft_i0), + .PRE(AR), + .Q(aempty_fwft_fb_i)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + aempty_fwft_i_reg + (.C(clk), + .CE(1'b1), + .D(aempty_fwft_i0), + .PRE(AR), + .Q(aempty_fwft_i)); + LUT4 #( + .INIT(16'hB2A2)) + empty_fwft_fb_i_i_1 + (.I0(empty_fwft_fb_i), + .I1(curr_fwft_state[1]), + .I2(curr_fwft_state[0]), + .I3(rd_en), + .O(empty_fwft_i0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + empty_fwft_fb_i_reg + (.C(clk), + .CE(1'b1), + .D(empty_fwft_i0), + .PRE(AR), + .Q(empty_fwft_fb_i)); + LUT4 #( + .INIT(16'hB2A2)) + empty_fwft_fb_o_i_i_1 + (.I0(empty_fwft_fb_o_i), + .I1(curr_fwft_state[1]), + .I2(curr_fwft_state[0]), + .I3(rd_en), + .O(empty_fwft_fb_o_i0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + empty_fwft_fb_o_i_reg + (.C(clk), + .CE(1'b1), + .D(empty_fwft_fb_o_i0), + .PRE(AR), + .Q(empty_fwft_fb_o_i)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + empty_fwft_i_reg + (.C(clk), + .CE(1'b1), + .D(empty_fwft_i0), + .PRE(AR), + .Q(empty_fwft_i)); + LUT4 #( + .INIT(16'h00DF)) + \gc0.count_d1[4]_i_1 + (.I0(curr_fwft_state[1]), + .I1(rd_en), + .I2(curr_fwft_state[0]), + .I3(ram_empty_fb_i_reg_0), + .O(E)); + LUT6 #( + .INIT(64'hFFFFAEAA0000A2AA)) + \gpr1.dout_i[0]_i_1 + (.I0(p_0_out), + .I1(curr_fwft_state[1]), + .I2(rd_en), + .I3(curr_fwft_state[0]), + .I4(ram_empty_fb_i_reg_0), + .I5(dout_i), + .O(\gpr1.dout_i_reg[0] )); + LUT3 #( + .INIT(8'hAE)) + \gpregsm1.curr_fwft_state[0]_i_1 + (.I0(curr_fwft_state[1]), + .I1(curr_fwft_state[0]), + .I2(rd_en), + .O(next_fwft_state[0])); + LUT4 #( + .INIT(16'h20FF)) + \gpregsm1.curr_fwft_state[1]_i_1 + (.I0(curr_fwft_state[1]), + .I1(rd_en), + .I2(curr_fwft_state[0]), + .I3(ram_empty_fb_i_reg_0), + .O(next_fwft_state[1])); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDCE #( + .INIT(1'b0)) + \gpregsm1.curr_fwft_state_reg[0] + (.C(clk), + .CE(1'b1), + .CLR(AR), + .D(next_fwft_state[0]), + .Q(curr_fwft_state[0])); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDCE #( + .INIT(1'b0)) + \gpregsm1.curr_fwft_state_reg[1] + (.C(clk), + .CE(1'b1), + .CLR(AR), + .D(next_fwft_state[1]), + .Q(curr_fwft_state[1])); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDCE #( + .INIT(1'b0)) + \gpregsm1.user_valid_reg + (.C(clk), + .CE(1'b1), + .CLR(AR), + .D(next_fwft_state[0]), + .Q(user_valid)); + LUT3 #( + .INIT(8'hDF)) + ram_empty_fb_i_i_4 + (.I0(curr_fwft_state[0]), + .I1(rd_en), + .I2(curr_fwft_state[1]), + .O(ram_empty_fb_i_reg)); + LUT4 #( + .INIT(16'hFF08)) + ram_full_fb_i_i_3 + (.I0(curr_fwft_state[0]), + .I1(curr_fwft_state[1]), + .I2(rd_en), + .I3(ram_empty_fb_i_reg_0), + .O(ram_full_fb_i_reg)); +endmodule + +module Arty_Z7_20_auto_pc_0_rd_logic + (empty, + Q, + ram_empty_fb_i_reg, + E, + \goreg_dm.dout_i_reg[4] , + \gpr1.dout_i_reg[1] , + ram_full_fb_i_reg, + clk, + out, + rd_en, + wr_en, + ram_full_fb_i_reg_0, + \gcc0.gc0.count_d1_reg[4] , + \gcc0.gc0.count_d1_reg[2] ); + output empty; + output [2:0]Q; + output ram_empty_fb_i_reg; + output [0:0]E; + output [0:0]\goreg_dm.dout_i_reg[4] ; + output [4:0]\gpr1.dout_i_reg[1] ; + output ram_full_fb_i_reg; + input clk; + input [1:0]out; + input rd_en; + input wr_en; + input ram_full_fb_i_reg_0; + input [4:0]\gcc0.gc0.count_d1_reg[4] ; + input \gcc0.gc0.count_d1_reg[2] ; + + wire [0:0]E; + wire [2:0]Q; + wire clk; + wire empty; + wire \gcc0.gc0.count_d1_reg[2] ; + wire [4:0]\gcc0.gc0.count_d1_reg[4] ; + wire [0:0]\goreg_dm.dout_i_reg[4] ; + wire [4:0]\gpr1.dout_i_reg[1] ; + wire \gr1.gr1_int.rfwft_n_2 ; + wire [1:0]out; + wire p_2_out; + wire ram_empty_fb_i_reg; + wire ram_full_fb_i_reg; + wire ram_full_fb_i_reg_0; + wire rd_en; + wire rpntr_n_3; + wire wr_en; + + Arty_Z7_20_auto_pc_0_rd_fwft \gr1.gr1_int.rfwft + (.E(E), + .clk(clk), + .empty(empty), + .\goreg_dm.dout_i_reg[4] (\goreg_dm.dout_i_reg[4] ), + .out(out), + .ram_empty_fb_i_reg(\gr1.gr1_int.rfwft_n_2 ), + .ram_empty_fb_i_reg_0(p_2_out), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_en(rd_en)); + Arty_Z7_20_auto_pc_0_rd_status_flags_ss \grss.rsts + (.clk(clk), + .\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (out[1]), + .out(p_2_out), + .ram_full_fb_i_reg(rpntr_n_3)); + Arty_Z7_20_auto_pc_0_rd_bin_cntr rpntr + (.E(E), + .Q(Q), + .clk(clk), + .\gcc0.gc0.count_d1_reg[2] (\gcc0.gc0.count_d1_reg[2] ), + .\gcc0.gc0.count_d1_reg[4] (\gcc0.gc0.count_d1_reg[4] ), + .\gpr1.dout_i_reg[1] (\gpr1.dout_i_reg[1] ), + .\gpregsm1.curr_fwft_state_reg[0] (\gr1.gr1_int.rfwft_n_2 ), + .\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (out[1]), + .out(p_2_out), + .ram_empty_fb_i_reg(rpntr_n_3), + .ram_empty_fb_i_reg_0(ram_empty_fb_i_reg), + .ram_full_fb_i_reg(ram_full_fb_i_reg_0), .wr_en(wr_en)); endmodule -module Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3_synth +(* ORIG_REF_NAME = "rd_logic" *) +module Arty_Z7_20_auto_pc_0_rd_logic_10 (empty, - full, - dout, - rd_en, - clk, - rst, - din, - wr_en); + Q, + ram_empty_fb_i_reg, + E, + \goreg_dm.dout_i_reg[4] , + \gpr1.dout_i_reg[1] , + ram_full_fb_i_reg, + clk, + out, + rd_en, + wr_en, + ram_full_fb_i_reg_0, + \gcc0.gc0.count_d1_reg[4] , + \gcc0.gc0.count_d1_reg[2] ); output empty; - output full; - output [0:0]dout; - input rd_en; + output [2:0]Q; + output ram_empty_fb_i_reg; + output [0:0]E; + output [0:0]\goreg_dm.dout_i_reg[4] ; + output [4:0]\gpr1.dout_i_reg[1] ; + output ram_full_fb_i_reg; input clk; - input rst; - input [0:0]din; + input [1:0]out; + input rd_en; input wr_en; + input ram_full_fb_i_reg_0; + input [4:0]\gcc0.gc0.count_d1_reg[4] ; + input \gcc0.gc0.count_d1_reg[2] ; + wire [0:0]E; + wire [2:0]Q; wire clk; - wire [0:0]din; - wire [0:0]dout; wire empty; - wire full; + wire \gcc0.gc0.count_d1_reg[2] ; + wire [4:0]\gcc0.gc0.count_d1_reg[4] ; + wire [0:0]\goreg_dm.dout_i_reg[4] ; + wire [4:0]\gpr1.dout_i_reg[1] ; + wire \gr1.gr1_int.rfwft_n_2 ; + wire [1:0]out; + wire p_2_out; + wire ram_empty_fb_i_reg; + wire ram_full_fb_i_reg; + wire ram_full_fb_i_reg_0; wire rd_en; - wire rst; + wire rpntr_n_3; wire wr_en; - Arty_Z7_20_auto_pc_0_fifo_generator_top \gconvfifo.rf - (.clk(clk), - .din(din), - .dout(dout), + Arty_Z7_20_auto_pc_0_rd_fwft_23 \gr1.gr1_int.rfwft + (.E(E), + .clk(clk), .empty(empty), - .full(full), - .rd_en(rd_en), - .rst(rst), + .\goreg_dm.dout_i_reg[4] (\goreg_dm.dout_i_reg[4] ), + .out(out), + .ram_empty_fb_i_reg(\gr1.gr1_int.rfwft_n_2 ), + .ram_empty_fb_i_reg_0(p_2_out), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_en(rd_en)); + Arty_Z7_20_auto_pc_0_rd_status_flags_ss_24 \grss.rsts + (.clk(clk), + .\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (out[1]), + .out(p_2_out), + .ram_full_fb_i_reg(rpntr_n_3)); + Arty_Z7_20_auto_pc_0_rd_bin_cntr_25 rpntr + (.E(E), + .Q(Q), + .clk(clk), + .\gcc0.gc0.count_d1_reg[2] (\gcc0.gc0.count_d1_reg[2] ), + .\gcc0.gc0.count_d1_reg[4] (\gcc0.gc0.count_d1_reg[4] ), + .\gpr1.dout_i_reg[1] (\gpr1.dout_i_reg[1] ), + .\gpregsm1.curr_fwft_state_reg[0] (\gr1.gr1_int.rfwft_n_2 ), + .\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (out[1]), + .out(p_2_out), + .ram_empty_fb_i_reg(rpntr_n_3), + .ram_empty_fb_i_reg_0(ram_empty_fb_i_reg), + .ram_full_fb_i_reg(ram_full_fb_i_reg_0), .wr_en(wr_en)); endmodule -module Arty_Z7_20_auto_pc_0_memory - (p_0_out, - dout_i, - dout, - clk, - din, - E, - \gcc0.gc0.count_d1_reg[4] , - \gc0.count_d1_reg[4] , +(* ORIG_REF_NAME = "rd_logic" *) +module Arty_Z7_20_auto_pc_0_rd_logic_26 + (out, + empty, + \gpr1.dout_i_reg[0] , + Q, ram_empty_fb_i_reg, - \gpregsm1.curr_fwft_state_reg[1] , + \gpr1.dout_i_reg[0]_0 , + ram_full_fb_i_reg, + clk, + AR, + p_0_out, rd_en, - out); - output p_0_out; - output dout_i; - output [0:0]dout; + dout_i, + wr_en, + ram_full_fb_i_reg_0, + \gcc0.gc0.count_d1_reg[4] , + \gcc0.gc0.count_d1_reg[2] ); + output [1:0]out; + output empty; + output \gpr1.dout_i_reg[0] ; + output [2:0]Q; + output ram_empty_fb_i_reg; + output [4:0]\gpr1.dout_i_reg[0]_0 ; + output ram_full_fb_i_reg; input clk; - input [0:0]din; - input [0:0]E; - input [4:0]\gcc0.gc0.count_d1_reg[4] ; - input [4:0]\gc0.count_d1_reg[4] ; - input ram_empty_fb_i_reg; - input [1:0]\gpregsm1.curr_fwft_state_reg[1] ; + input [0:0]AR; + input p_0_out; input rd_en; - input [0:0]out; + input dout_i; + input wr_en; + input ram_full_fb_i_reg_0; + input [4:0]\gcc0.gc0.count_d1_reg[4] ; + input \gcc0.gc0.count_d1_reg[2] ; - wire [0:0]E; + wire [0:0]AR; + wire [2:0]Q; wire clk; - wire [0:0]din; - wire [0:0]dout; wire dout_i; - wire [4:0]\gc0.count_d1_reg[4] ; + wire empty; + wire \gcc0.gc0.count_d1_reg[2] ; wire [4:0]\gcc0.gc0.count_d1_reg[4] ; - wire \gdm.dm_gen.dm_n_2 ; - wire [1:0]\gpregsm1.curr_fwft_state_reg[1] ; - wire [0:0]out; + wire \gntv_or_sync_fifo.mem/ram_rd_en_i ; + wire \gpr1.dout_i_reg[0] ; + wire [4:0]\gpr1.dout_i_reg[0]_0 ; + wire \gr1.gr1_int.rfwft_n_5 ; + wire [1:0]out; wire p_0_out; + wire p_2_out; wire ram_empty_fb_i_reg; + wire ram_full_fb_i_reg; + wire ram_full_fb_i_reg_0; wire rd_en; + wire rpntr_n_3; + wire wr_en; - Arty_Z7_20_auto_pc_0_dmem \gdm.dm_gen.dm - (.E(E), + Arty_Z7_20_auto_pc_0_rd_fwft_37 \gr1.gr1_int.rfwft + (.AR(AR), + .E(\gntv_or_sync_fifo.mem/ram_rd_en_i ), .clk(clk), - .din(din), - .dout(dout), .dout_i(dout_i), - .\gc0.count_d1_reg[4] (\gc0.count_d1_reg[4] ), - .\gcc0.gc0.count_d1_reg[4] (\gcc0.gc0.count_d1_reg[4] ), - .\goreg_dm.dout_i_reg[0] (\gdm.dm_gen.dm_n_2 ), - .\gpregsm1.curr_fwft_state_reg[1] (\gpregsm1.curr_fwft_state_reg[1] ), + .empty(empty), + .\gpr1.dout_i_reg[0] (\gpr1.dout_i_reg[0] ), .out(out), .p_0_out(p_0_out), - .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_empty_fb_i_reg(\gr1.gr1_int.rfwft_n_5 ), + .ram_empty_fb_i_reg_0(p_2_out), + .ram_full_fb_i_reg(ram_full_fb_i_reg), .rd_en(rd_en)); - FDRE #( - .INIT(1'b0)) - \goreg_dm.dout_i_reg[0] - (.C(clk), - .CE(1'b1), - .D(\gdm.dm_gen.dm_n_2 ), - .Q(dout), - .R(1'b0)); + Arty_Z7_20_auto_pc_0_rd_status_flags_ss_38 \grss.rsts + (.AR(AR), + .clk(clk), + .out(p_2_out), + .ram_full_fb_i_reg(rpntr_n_3)); + Arty_Z7_20_auto_pc_0_rd_bin_cntr_39 rpntr + (.AR(AR), + .E(\gntv_or_sync_fifo.mem/ram_rd_en_i ), + .Q(Q), + .clk(clk), + .\gcc0.gc0.count_d1_reg[2] (\gcc0.gc0.count_d1_reg[2] ), + .\gcc0.gc0.count_d1_reg[4] (\gcc0.gc0.count_d1_reg[4] ), + .\gpr1.dout_i_reg[0] (\gpr1.dout_i_reg[0]_0 ), + .\gpregsm1.curr_fwft_state_reg[0] (\gr1.gr1_int.rfwft_n_5 ), + .out(p_2_out), + .ram_empty_fb_i_reg(rpntr_n_3), + .ram_empty_fb_i_reg_0(ram_empty_fb_i_reg), + .ram_full_fb_i_reg(ram_full_fb_i_reg_0), + .wr_en(wr_en)); endmodule -module Arty_Z7_20_auto_pc_0_rd_bin_cntr - (Q, - ram_full_comb, - ram_full_i_reg, - ram_full_i_reg_0, +module Arty_Z7_20_auto_pc_0_rd_status_flags_ss + (out, ram_full_fb_i_reg, - E, - \gcc0.gc0.count_d1_reg[4] , - wr_en, - \gcc0.gc0.count_reg[4] , clk, - AR); - output [4:0]Q; - output ram_full_comb; - output ram_full_i_reg; - output [4:0]ram_full_i_reg_0; + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ); + output out; input ram_full_fb_i_reg; - input [0:0]E; - input [4:0]\gcc0.gc0.count_d1_reg[4] ; - input wr_en; - input [4:0]\gcc0.gc0.count_reg[4] ; input clk; - input [0:0]AR; + input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ; - wire [0:0]AR; - wire [0:0]E; - wire [4:0]Q; wire clk; - wire [4:0]\gcc0.gc0.count_d1_reg[4] ; - wire [4:0]\gcc0.gc0.count_reg[4] ; - wire [4:0]plusOp; - wire ram_empty_fb_i_i_6_n_0; - wire ram_full_comb; - wire ram_full_fb_i_i_2_n_0; - wire ram_full_fb_i_i_3_n_0; - wire ram_full_fb_i_i_4_n_0; + wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ; + (* DONT_TOUCH *) wire ram_empty_fb_i; + (* DONT_TOUCH *) wire ram_empty_i; wire ram_full_fb_i_reg; - wire ram_full_i_reg; - wire [4:0]ram_full_i_reg_0; - wire wr_en; - LUT1 #( - .INIT(2'h1)) - \gc0.count[0]_i_1 - (.I0(Q[0]), - .O(plusOp[0])); - (* SOFT_HLUTNM = "soft_lutpair1" *) - LUT2 #( - .INIT(4'h6)) - \gc0.count[1]_i_1 - (.I0(Q[1]), - .I1(Q[0]), - .O(plusOp[1])); - (* SOFT_HLUTNM = "soft_lutpair1" *) - LUT3 #( - .INIT(8'h78)) - \gc0.count[2]_i_1 - (.I0(Q[1]), - .I1(Q[0]), - .I2(Q[2]), - .O(plusOp[2])); - (* SOFT_HLUTNM = "soft_lutpair0" *) - LUT4 #( - .INIT(16'h6AAA)) - \gc0.count[3]_i_1 - (.I0(Q[3]), - .I1(Q[1]), - .I2(Q[0]), - .I3(Q[2]), - .O(plusOp[3])); - (* SOFT_HLUTNM = "soft_lutpair0" *) - LUT5 #( - .INIT(32'h6AAAAAAA)) - \gc0.count[4]_i_1 - (.I0(Q[4]), - .I1(Q[2]), - .I2(Q[0]), - .I3(Q[1]), - .I4(Q[3]), - .O(plusOp[4])); - FDCE #( - .INIT(1'b0)) - \gc0.count_d1_reg[0] - (.C(clk), - .CE(E), - .CLR(AR), - .D(Q[0]), - .Q(ram_full_i_reg_0[0])); - FDCE #( - .INIT(1'b0)) - \gc0.count_d1_reg[1] + assign out = ram_empty_fb_i; + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + ram_empty_fb_i_reg (.C(clk), - .CE(E), - .CLR(AR), - .D(Q[1]), - .Q(ram_full_i_reg_0[1])); - FDCE #( - .INIT(1'b0)) - \gc0.count_d1_reg[2] + .CE(1'b1), + .D(ram_full_fb_i_reg), + .PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), + .Q(ram_empty_fb_i)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + ram_empty_i_reg (.C(clk), - .CE(E), - .CLR(AR), - .D(Q[2]), - .Q(ram_full_i_reg_0[2])); - FDCE #( - .INIT(1'b0)) - \gc0.count_d1_reg[3] + .CE(1'b1), + .D(ram_full_fb_i_reg), + .PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), + .Q(ram_empty_i)); +endmodule + +(* ORIG_REF_NAME = "rd_status_flags_ss" *) +module Arty_Z7_20_auto_pc_0_rd_status_flags_ss_24 + (out, + ram_full_fb_i_reg, + clk, + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ); + output out; + input ram_full_fb_i_reg; + input clk; + input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ; + + wire clk; + wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ; + (* DONT_TOUCH *) wire ram_empty_fb_i; + (* DONT_TOUCH *) wire ram_empty_i; + wire ram_full_fb_i_reg; + + assign out = ram_empty_fb_i; + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + ram_empty_fb_i_reg (.C(clk), - .CE(E), - .CLR(AR), - .D(Q[3]), - .Q(ram_full_i_reg_0[3])); - FDCE #( - .INIT(1'b0)) - \gc0.count_d1_reg[4] + .CE(1'b1), + .D(ram_full_fb_i_reg), + .PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), + .Q(ram_empty_fb_i)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + ram_empty_i_reg (.C(clk), - .CE(E), - .CLR(AR), - .D(Q[4]), - .Q(ram_full_i_reg_0[4])); + .CE(1'b1), + .D(ram_full_fb_i_reg), + .PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), + .Q(ram_empty_i)); +endmodule + +(* ORIG_REF_NAME = "rd_status_flags_ss" *) +module Arty_Z7_20_auto_pc_0_rd_status_flags_ss_38 + (out, + ram_full_fb_i_reg, + clk, + AR); + output out; + input ram_full_fb_i_reg; + input clk; + input [0:0]AR; + + wire [0:0]AR; + wire clk; + (* DONT_TOUCH *) wire ram_empty_fb_i; + (* DONT_TOUCH *) wire ram_empty_i; + wire ram_full_fb_i_reg; + + assign out = ram_empty_fb_i; + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) - \gc0.count_reg[0] + ram_empty_fb_i_reg (.C(clk), - .CE(E), - .D(plusOp[0]), + .CE(1'b1), + .D(ram_full_fb_i_reg), .PRE(AR), - .Q(Q[0])); - FDCE #( - .INIT(1'b0)) - \gc0.count_reg[1] - (.C(clk), - .CE(E), - .CLR(AR), - .D(plusOp[1]), - .Q(Q[1])); - FDCE #( - .INIT(1'b0)) - \gc0.count_reg[2] - (.C(clk), - .CE(E), - .CLR(AR), - .D(plusOp[2]), - .Q(Q[2])); - FDCE #( - .INIT(1'b0)) - \gc0.count_reg[3] - (.C(clk), - .CE(E), - .CLR(AR), - .D(plusOp[3]), - .Q(Q[3])); - FDCE #( - .INIT(1'b0)) - \gc0.count_reg[4] + .Q(ram_empty_fb_i)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + ram_empty_i_reg (.C(clk), - .CE(E), - .CLR(AR), - .D(plusOp[4]), - .Q(Q[4])); - LUT5 #( - .INIT(32'h00009009)) - ram_empty_fb_i_i_3 - (.I0(\gcc0.gc0.count_d1_reg[4] [1]), - .I1(ram_full_i_reg_0[1]), - .I2(\gcc0.gc0.count_d1_reg[4] [2]), - .I3(ram_full_i_reg_0[2]), - .I4(ram_empty_fb_i_i_6_n_0), - .O(ram_full_i_reg)); - LUT6 #( - .INIT(64'h6FF6FFFFFFFF6FF6)) - ram_empty_fb_i_i_6 - (.I0(ram_full_i_reg_0[0]), - .I1(\gcc0.gc0.count_d1_reg[4] [0]), - .I2(\gcc0.gc0.count_d1_reg[4] [4]), - .I3(ram_full_i_reg_0[4]), - .I4(\gcc0.gc0.count_d1_reg[4] [3]), - .I5(ram_full_i_reg_0[3]), - .O(ram_empty_fb_i_i_6_n_0)); - LUT4 #( - .INIT(16'h08AA)) - ram_full_fb_i_i_1 - (.I0(ram_full_fb_i_i_2_n_0), - .I1(ram_full_fb_i_reg), - .I2(ram_full_i_reg), - .I3(E), - .O(ram_full_comb)); - LUT6 #( - .INIT(64'hABAAAAAAAAAAABAA)) - ram_full_fb_i_i_2 - (.I0(ram_full_fb_i_reg), - .I1(ram_full_fb_i_i_3_n_0), - .I2(ram_full_fb_i_i_4_n_0), - .I3(wr_en), - .I4(ram_full_i_reg_0[4]), - .I5(\gcc0.gc0.count_reg[4] [4]), - .O(ram_full_fb_i_i_2_n_0)); - LUT4 #( - .INIT(16'h6FF6)) - ram_full_fb_i_i_3 - (.I0(ram_full_i_reg_0[2]), - .I1(\gcc0.gc0.count_reg[4] [2]), - .I2(ram_full_i_reg_0[3]), - .I3(\gcc0.gc0.count_reg[4] [3]), - .O(ram_full_fb_i_i_3_n_0)); - LUT4 #( - .INIT(16'h6FF6)) - ram_full_fb_i_i_4 - (.I0(ram_full_i_reg_0[0]), - .I1(\gcc0.gc0.count_reg[4] [0]), - .I2(ram_full_i_reg_0[1]), - .I3(\gcc0.gc0.count_reg[4] [1]), - .O(ram_full_fb_i_i_4_n_0)); + .CE(1'b1), + .D(ram_full_fb_i_reg), + .PRE(AR), + .Q(ram_empty_i)); endmodule -module Arty_Z7_20_auto_pc_0_rd_fwft +module Arty_Z7_20_auto_pc_0_reset_blk_ramfifo (out, - empty, - E, - \gpr1.dout_i_reg[0] , - ram_empty_i_reg, + \gc0.count_reg[1] , clk, - AR, - ram_empty_fb_i_reg, - rd_en, - p_0_out, - dout_i); + rst); output [1:0]out; - output empty; - output [0:0]E; - output \gpr1.dout_i_reg[0] ; - output ram_empty_i_reg; + output [1:0]\gc0.count_reg[1] ; input clk; - input [0:0]AR; - input ram_empty_fb_i_reg; - input rd_en; - input p_0_out; - input dout_i; + input rst; - wire [0:0]AR; - wire [0:0]E; - (* DONT_TOUCH *) wire aempty_fwft_fb_i; - (* DONT_TOUCH *) wire aempty_fwft_i; - wire aempty_fwft_i0; wire clk; - (* DONT_TOUCH *) wire [1:0]curr_fwft_state; - wire dout_i; - (* DONT_TOUCH *) wire empty_fwft_fb_i; - (* DONT_TOUCH *) wire empty_fwft_fb_o_i; - wire empty_fwft_fb_o_i0; - (* DONT_TOUCH *) wire empty_fwft_i; - wire empty_fwft_i0; - wire \gpr1.dout_i_reg[0] ; - wire \gpregsm1.curr_fwft_state[1]_i_1_n_0 ; - wire [0:0]next_fwft_state; - wire p_0_out; - wire ram_empty_fb_i_reg; - wire ram_empty_i_reg; - wire rd_en; - (* DONT_TOUCH *) wire user_valid; + wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ; + wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ; + wire p_6_out; + wire p_7_out; + wire p_8_out; + wire p_9_out; + wire rd_rst_asreg; + (* DONT_TOUCH *) wire [2:0]rd_rst_reg; + wire rst; + (* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1; + (* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2; + (* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1; + (* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2; + wire wr_rst_asreg; + (* DONT_TOUCH *) wire [2:0]wr_rst_reg; - assign empty = empty_fwft_i; - assign out[1:0] = curr_fwft_state; - LUT5 #( - .INIT(32'hEA88A8AA)) - aempty_fwft_fb_i_i_1 - (.I0(aempty_fwft_fb_i), - .I1(ram_empty_fb_i_reg), - .I2(rd_en), - .I3(curr_fwft_state[0]), - .I4(curr_fwft_state[1]), - .O(aempty_fwft_i0)); + assign \gc0.count_reg[1] [1] = rd_rst_reg[2]; + assign \gc0.count_reg[1] [0] = rd_rst_reg[0]; + assign out[1:0] = wr_rst_reg[1:0]; + Arty_Z7_20_auto_pc_0_synchronizer_ff \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst + (.clk(clk), + .in0(rd_rst_asreg), + .out(p_6_out)); + Arty_Z7_20_auto_pc_0_synchronizer_ff_1 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst + (.clk(clk), + .in0(wr_rst_asreg), + .out(p_7_out)); + Arty_Z7_20_auto_pc_0_synchronizer_ff_2 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst + (.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ), + .\Q_reg_reg[0]_0 (p_8_out), + .clk(clk), + .in0(rd_rst_asreg), + .out(p_6_out)); + Arty_Z7_20_auto_pc_0_synchronizer_ff_3 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst + (.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ), + .\Q_reg_reg[0]_0 (p_9_out), + .clk(clk), + .in0(wr_rst_asreg), + .out(p_7_out)); + Arty_Z7_20_auto_pc_0_synchronizer_ff_4 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst + (.\Q_reg_reg[0]_0 (p_8_out), + .clk(clk)); + Arty_Z7_20_auto_pc_0_synchronizer_ff_5 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst + (.\Q_reg_reg[0]_0 (p_9_out), + .clk(clk)); + FDPE #( + .INIT(1'b1)) + \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg + (.C(clk), + .CE(1'b1), + .D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ), + .PRE(rst_rd_reg2), + .Q(rd_rst_asreg)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] + (.C(clk), + .CE(1'b1), + .D(1'b0), + .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ), + .Q(rd_rst_reg[0])); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] + (.C(clk), + .CE(1'b1), + .D(1'b0), + .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ), + .Q(rd_rst_reg[1])); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) - aempty_fwft_fb_i_reg + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] + (.C(clk), + .CE(1'b1), + .D(1'b0), + .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ), + .Q(rd_rst_reg[2])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDPE #( + .INIT(1'b0)) + \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg + (.C(clk), + .CE(1'b1), + .D(1'b0), + .PRE(rst), + .Q(rst_rd_reg1)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDPE #( + .INIT(1'b0)) + \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg + (.C(clk), + .CE(1'b1), + .D(rst_rd_reg1), + .PRE(rst), + .Q(rst_rd_reg2)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDPE #( + .INIT(1'b0)) + \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg + (.C(clk), + .CE(1'b1), + .D(1'b0), + .PRE(rst), + .Q(rst_wr_reg1)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDPE #( + .INIT(1'b0)) + \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg + (.C(clk), + .CE(1'b1), + .D(rst_wr_reg1), + .PRE(rst), + .Q(rst_wr_reg2)); + FDPE #( + .INIT(1'b1)) + \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg (.C(clk), .CE(1'b1), - .D(aempty_fwft_i0), - .PRE(AR), - .Q(aempty_fwft_fb_i)); + .D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ), + .PRE(rst_wr_reg2), + .Q(wr_rst_asreg)); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) - aempty_fwft_i_reg + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] (.C(clk), .CE(1'b1), - .D(aempty_fwft_i0), - .PRE(AR), - .Q(aempty_fwft_i)); - LUT4 #( - .INIT(16'hF320)) - empty_fwft_fb_i_i_1 - (.I0(rd_en), - .I1(curr_fwft_state[1]), - .I2(curr_fwft_state[0]), - .I3(empty_fwft_fb_i), - .O(empty_fwft_i0)); + .D(1'b0), + .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ), + .Q(wr_rst_reg[0])); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) - empty_fwft_fb_i_reg + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] (.C(clk), .CE(1'b1), - .D(empty_fwft_i0), - .PRE(AR), - .Q(empty_fwft_fb_i)); - LUT4 #( - .INIT(16'hF320)) - empty_fwft_fb_o_i_i_1 - (.I0(rd_en), - .I1(curr_fwft_state[1]), - .I2(curr_fwft_state[0]), - .I3(empty_fwft_fb_o_i), - .O(empty_fwft_fb_o_i0)); + .D(1'b0), + .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ), + .Q(wr_rst_reg[1])); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) - empty_fwft_fb_o_i_reg + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2] (.C(clk), .CE(1'b1), - .D(empty_fwft_fb_o_i0), - .PRE(AR), - .Q(empty_fwft_fb_o_i)); - (* DONT_TOUCH *) - (* KEEP = "yes" *) - (* equivalent_register_removal = "no" *) + .D(1'b0), + .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ), + .Q(wr_rst_reg[2])); +endmodule + +(* ORIG_REF_NAME = "reset_blk_ramfifo" *) +module Arty_Z7_20_auto_pc_0_reset_blk_ramfifo_13 + (out, + \gc0.count_reg[1] , + clk, + rst); + output [1:0]out; + output [1:0]\gc0.count_reg[1] ; + input clk; + input rst; + + wire clk; + wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ; + wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ; + wire p_6_out; + wire p_7_out; + wire p_8_out; + wire p_9_out; + wire rd_rst_asreg; + (* DONT_TOUCH *) wire [2:0]rd_rst_reg; + wire rst; + (* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1; + (* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2; + (* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1; + (* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2; + wire wr_rst_asreg; + (* DONT_TOUCH *) wire [2:0]wr_rst_reg; + + assign \gc0.count_reg[1] [1] = rd_rst_reg[2]; + assign \gc0.count_reg[1] [0] = rd_rst_reg[0]; + assign out[1:0] = wr_rst_reg[1:0]; + Arty_Z7_20_auto_pc_0_synchronizer_ff_14 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst + (.clk(clk), + .in0(rd_rst_asreg), + .out(p_6_out)); + Arty_Z7_20_auto_pc_0_synchronizer_ff_15 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst + (.clk(clk), + .in0(wr_rst_asreg), + .out(p_7_out)); + Arty_Z7_20_auto_pc_0_synchronizer_ff_16 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst + (.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ), + .\Q_reg_reg[0]_0 (p_8_out), + .clk(clk), + .in0(rd_rst_asreg), + .out(p_6_out)); + Arty_Z7_20_auto_pc_0_synchronizer_ff_17 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst + (.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ), + .\Q_reg_reg[0]_0 (p_9_out), + .clk(clk), + .in0(wr_rst_asreg), + .out(p_7_out)); + Arty_Z7_20_auto_pc_0_synchronizer_ff_18 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst + (.\Q_reg_reg[0]_0 (p_8_out), + .clk(clk)); + Arty_Z7_20_auto_pc_0_synchronizer_ff_19 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst + (.\Q_reg_reg[0]_0 (p_9_out), + .clk(clk)); FDPE #( .INIT(1'b1)) - empty_fwft_i_reg + \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg (.C(clk), .CE(1'b1), - .D(empty_fwft_i0), - .PRE(AR), - .Q(empty_fwft_i)); - LUT4 #( - .INIT(16'h4555)) - \gc0.count_d1[4]_i_1 - (.I0(ram_empty_fb_i_reg), - .I1(rd_en), - .I2(curr_fwft_state[0]), - .I3(curr_fwft_state[1]), - .O(E)); - LUT6 #( - .INIT(64'hEFEEEEEE20222222)) - \gpr1.dout_i[0]_i_1 - (.I0(p_0_out), - .I1(ram_empty_fb_i_reg), - .I2(rd_en), - .I3(curr_fwft_state[0]), - .I4(curr_fwft_state[1]), - .I5(dout_i), - .O(\gpr1.dout_i_reg[0] )); - LUT3 #( - .INIT(8'hAE)) - \gpregsm1.curr_fwft_state[0]_i_1 - (.I0(curr_fwft_state[1]), - .I1(curr_fwft_state[0]), - .I2(rd_en), - .O(next_fwft_state)); - LUT4 #( - .INIT(16'h40FF)) - \gpregsm1.curr_fwft_state[1]_i_1 - (.I0(rd_en), - .I1(curr_fwft_state[0]), - .I2(curr_fwft_state[1]), - .I3(ram_empty_fb_i_reg), - .O(\gpregsm1.curr_fwft_state[1]_i_1_n_0 )); + .D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ), + .PRE(rst_rd_reg2), + .Q(rd_rst_asreg)); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) - FDCE #( - .INIT(1'b0)) - \gpregsm1.curr_fwft_state_reg[0] + FDPE #( + .INIT(1'b1)) + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] (.C(clk), .CE(1'b1), - .CLR(AR), - .D(next_fwft_state), - .Q(curr_fwft_state[0])); + .D(1'b0), + .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ), + .Q(rd_rst_reg[0])); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) - FDCE #( - .INIT(1'b0)) - \gpregsm1.curr_fwft_state_reg[1] + FDPE #( + .INIT(1'b1)) + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (.C(clk), .CE(1'b1), - .CLR(AR), - .D(\gpregsm1.curr_fwft_state[1]_i_1_n_0 ), - .Q(curr_fwft_state[1])); + .D(1'b0), + .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ), + .Q(rd_rst_reg[1])); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) - FDCE #( - .INIT(1'b0)) - \gpregsm1.user_valid_reg + FDPE #( + .INIT(1'b1)) + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (.C(clk), .CE(1'b1), - .CLR(AR), - .D(next_fwft_state), - .Q(user_valid)); - LUT3 #( - .INIT(8'h08)) - ram_empty_fb_i_i_5 - (.I0(curr_fwft_state[1]), - .I1(curr_fwft_state[0]), - .I2(rd_en), - .O(ram_empty_i_reg)); -endmodule - -module Arty_Z7_20_auto_pc_0_rd_logic - (out, - aempty_fwft_i_reg, - empty, - \gpr1.dout_i_reg[0] , - Q, - ram_full_comb, - ram_full_i_reg, - ram_empty_i_reg, - ram_full_i_reg_0, - ram_empty_fb_i_reg, - clk, - AR, - rd_en, - p_0_out, - dout_i, - ram_full_fb_i_reg, - \gcc0.gc0.count_d1_reg[4] , - wr_en, - \gcc0.gc0.count_reg[4] ); - output out; - output [1:0]aempty_fwft_i_reg; - output empty; - output \gpr1.dout_i_reg[0] ; - output [4:0]Q; - output ram_full_comb; - output ram_full_i_reg; - output ram_empty_i_reg; - output [4:0]ram_full_i_reg_0; - input ram_empty_fb_i_reg; - input clk; - input [0:0]AR; - input rd_en; - input p_0_out; - input dout_i; - input ram_full_fb_i_reg; - input [4:0]\gcc0.gc0.count_d1_reg[4] ; - input wr_en; - input [4:0]\gcc0.gc0.count_reg[4] ; - - wire [0:0]AR; - wire [4:0]Q; - wire [1:0]aempty_fwft_i_reg; - wire clk; - wire dout_i; - wire empty; - wire [4:0]\gcc0.gc0.count_d1_reg[4] ; - wire [4:0]\gcc0.gc0.count_reg[4] ; - wire \gpr1.dout_i_reg[0] ; - wire \gr1.gr1_int.rfwft_n_3 ; - wire out; - wire p_0_out; - wire ram_empty_fb_i_reg; - wire ram_empty_i_reg; - wire ram_full_comb; - wire ram_full_fb_i_reg; - wire ram_full_i_reg; - wire [4:0]ram_full_i_reg_0; - wire rd_en; - wire wr_en; - - Arty_Z7_20_auto_pc_0_rd_fwft \gr1.gr1_int.rfwft - (.AR(AR), - .E(\gr1.gr1_int.rfwft_n_3 ), - .clk(clk), - .dout_i(dout_i), - .empty(empty), - .\gpr1.dout_i_reg[0] (\gpr1.dout_i_reg[0] ), - .out(aempty_fwft_i_reg), - .p_0_out(p_0_out), - .ram_empty_fb_i_reg(out), - .ram_empty_i_reg(ram_empty_i_reg), - .rd_en(rd_en)); - Arty_Z7_20_auto_pc_0_rd_status_flags_ss \grss.rsts - (.AR(AR), - .clk(clk), - .out(out), - .ram_empty_fb_i_reg_0(ram_empty_fb_i_reg)); - Arty_Z7_20_auto_pc_0_rd_bin_cntr rpntr - (.AR(AR), - .E(\gr1.gr1_int.rfwft_n_3 ), - .Q(Q), - .clk(clk), - .\gcc0.gc0.count_d1_reg[4] (\gcc0.gc0.count_d1_reg[4] ), - .\gcc0.gc0.count_reg[4] (\gcc0.gc0.count_reg[4] ), - .ram_full_comb(ram_full_comb), - .ram_full_fb_i_reg(ram_full_fb_i_reg), - .ram_full_i_reg(ram_full_i_reg), - .ram_full_i_reg_0(ram_full_i_reg_0), - .wr_en(wr_en)); -endmodule - -module Arty_Z7_20_auto_pc_0_rd_status_flags_ss - (out, - ram_empty_fb_i_reg_0, - clk, - AR); - output out; - input ram_empty_fb_i_reg_0; - input clk; - input [0:0]AR; - - wire [0:0]AR; - wire clk; - (* DONT_TOUCH *) wire ram_empty_fb_i; - wire ram_empty_fb_i_reg_0; - (* DONT_TOUCH *) wire ram_empty_i; - - assign out = ram_empty_fb_i; + .D(1'b0), + .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ), + .Q(rd_rst_reg[2])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDPE #( + .INIT(1'b0)) + \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg + (.C(clk), + .CE(1'b1), + .D(1'b0), + .PRE(rst), + .Q(rst_rd_reg1)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDPE #( + .INIT(1'b0)) + \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg + (.C(clk), + .CE(1'b1), + .D(rst_rd_reg1), + .PRE(rst), + .Q(rst_rd_reg2)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDPE #( + .INIT(1'b0)) + \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg + (.C(clk), + .CE(1'b1), + .D(1'b0), + .PRE(rst), + .Q(rst_wr_reg1)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDPE #( + .INIT(1'b0)) + \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg + (.C(clk), + .CE(1'b1), + .D(rst_wr_reg1), + .PRE(rst), + .Q(rst_wr_reg2)); + FDPE #( + .INIT(1'b1)) + \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg + (.C(clk), + .CE(1'b1), + .D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ), + .PRE(rst_wr_reg2), + .Q(wr_rst_asreg)); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) - ram_empty_fb_i_reg + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] (.C(clk), .CE(1'b1), - .D(ram_empty_fb_i_reg_0), - .PRE(AR), - .Q(ram_empty_fb_i)); + .D(1'b0), + .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ), + .Q(wr_rst_reg[0])); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDPE #( .INIT(1'b1)) - ram_empty_i_reg + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] (.C(clk), .CE(1'b1), - .D(ram_empty_fb_i_reg_0), - .PRE(AR), - .Q(ram_empty_i)); + .D(1'b0), + .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ), + .Q(wr_rst_reg[1])); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2] + (.C(clk), + .CE(1'b1), + .D(1'b0), + .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ), + .Q(wr_rst_reg[2])); endmodule -module Arty_Z7_20_auto_pc_0_reset_blk_ramfifo +(* ORIG_REF_NAME = "reset_blk_ramfifo" *) +module Arty_Z7_20_auto_pc_0_reset_blk_ramfifo_28 (out, \gc0.count_reg[1] , clk, @@ -6249,30 +15756,30 @@ module Arty_Z7_20_auto_pc_0_reset_blk_ramfifo assign \gc0.count_reg[1] [1] = rd_rst_reg[2]; assign \gc0.count_reg[1] [0] = rd_rst_reg[0]; assign out[1:0] = wr_rst_reg[1:0]; - Arty_Z7_20_auto_pc_0_synchronizer_ff \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst + Arty_Z7_20_auto_pc_0_synchronizer_ff_29 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst (.clk(clk), .in0(rd_rst_asreg), .out(p_6_out)); - Arty_Z7_20_auto_pc_0_synchronizer_ff_0 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst + Arty_Z7_20_auto_pc_0_synchronizer_ff_30 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst (.clk(clk), .in0(wr_rst_asreg), .out(p_7_out)); - Arty_Z7_20_auto_pc_0_synchronizer_ff_1 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst + Arty_Z7_20_auto_pc_0_synchronizer_ff_31 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst (.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ), .\Q_reg_reg[0]_0 (p_8_out), .clk(clk), .in0(rd_rst_asreg), .out(p_6_out)); - Arty_Z7_20_auto_pc_0_synchronizer_ff_2 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst + Arty_Z7_20_auto_pc_0_synchronizer_ff_32 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst (.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ), .\Q_reg_reg[0]_0 (p_9_out), .clk(clk), .in0(wr_rst_asreg), .out(p_7_out)); - Arty_Z7_20_auto_pc_0_synchronizer_ff_3 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst + Arty_Z7_20_auto_pc_0_synchronizer_ff_33 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst (.\Q_reg_reg[0]_0 (p_8_out), .clk(clk)); - Arty_Z7_20_auto_pc_0_synchronizer_ff_4 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst + Arty_Z7_20_auto_pc_0_synchronizer_ff_34 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst (.\Q_reg_reg[0]_0 (p_9_out), .clk(clk)); FDPE #( @@ -6319,91 +15826,430 @@ module Arty_Z7_20_auto_pc_0_reset_blk_ramfifo (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) - FDPE #( + FDPE #( + .INIT(1'b0)) + \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg + (.C(clk), + .CE(1'b1), + .D(1'b0), + .PRE(rst), + .Q(rst_rd_reg1)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDPE #( + .INIT(1'b0)) + \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg + (.C(clk), + .CE(1'b1), + .D(rst_rd_reg1), + .PRE(rst), + .Q(rst_rd_reg2)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDPE #( + .INIT(1'b0)) + \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg + (.C(clk), + .CE(1'b1), + .D(1'b0), + .PRE(rst), + .Q(rst_wr_reg1)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDPE #( + .INIT(1'b0)) + \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg + (.C(clk), + .CE(1'b1), + .D(rst_wr_reg1), + .PRE(rst), + .Q(rst_wr_reg2)); + FDPE #( + .INIT(1'b1)) + \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg + (.C(clk), + .CE(1'b1), + .D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ), + .PRE(rst_wr_reg2), + .Q(wr_rst_asreg)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] + (.C(clk), + .CE(1'b1), + .D(1'b0), + .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ), + .Q(wr_rst_reg[0])); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] + (.C(clk), + .CE(1'b1), + .D(1'b0), + .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ), + .Q(wr_rst_reg[1])); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2] + (.C(clk), + .CE(1'b1), + .D(1'b0), + .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ), + .Q(wr_rst_reg[2])); +endmodule + +module Arty_Z7_20_auto_pc_0_synchronizer_ff + (out, + in0, + clk); + output out; + input [0:0]in0; + input clk; + + (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; + wire clk; + wire [0:0]in0; + + assign out = Q_reg; + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[0] + (.C(clk), + .CE(1'b1), + .D(in0), + .Q(Q_reg), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "synchronizer_ff" *) +module Arty_Z7_20_auto_pc_0_synchronizer_ff_1 + (out, + in0, + clk); + output out; + input [0:0]in0; + input clk; + + (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; + wire clk; + wire [0:0]in0; + + assign out = Q_reg; + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[0] + (.C(clk), + .CE(1'b1), + .D(in0), + .Q(Q_reg), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "synchronizer_ff" *) +module Arty_Z7_20_auto_pc_0_synchronizer_ff_14 + (out, + in0, + clk); + output out; + input [0:0]in0; + input clk; + + (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; + wire clk; + wire [0:0]in0; + + assign out = Q_reg; + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[0] + (.C(clk), + .CE(1'b1), + .D(in0), + .Q(Q_reg), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "synchronizer_ff" *) +module Arty_Z7_20_auto_pc_0_synchronizer_ff_15 + (out, + in0, + clk); + output out; + input [0:0]in0; + input clk; + + (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; + wire clk; + wire [0:0]in0; + + assign out = Q_reg; + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( .INIT(1'b0)) - \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg + \Q_reg_reg[0] (.C(clk), .CE(1'b1), - .D(1'b0), - .PRE(rst), - .Q(rst_rd_reg1)); + .D(in0), + .Q(Q_reg), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "synchronizer_ff" *) +module Arty_Z7_20_auto_pc_0_synchronizer_ff_16 + (\Q_reg_reg[0]_0 , + AS, + out, + clk, + in0); + output \Q_reg_reg[0]_0 ; + output [0:0]AS; + input out; + input clk; + input [0:0]in0; + + wire [0:0]AS; + (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; + wire clk; + wire [0:0]in0; + wire out; + + assign \Q_reg_reg[0]_0 = Q_reg; (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) - FDPE #( + FDRE #( .INIT(1'b0)) - \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg + \Q_reg_reg[0] (.C(clk), .CE(1'b1), - .D(rst_rd_reg1), - .PRE(rst), - .Q(rst_rd_reg2)); + .D(out), + .Q(Q_reg), + .R(1'b0)); + LUT2 #( + .INIT(4'h2)) + \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 + (.I0(in0), + .I1(Q_reg), + .O(AS)); +endmodule + +(* ORIG_REF_NAME = "synchronizer_ff" *) +module Arty_Z7_20_auto_pc_0_synchronizer_ff_17 + (\Q_reg_reg[0]_0 , + AS, + out, + clk, + in0); + output \Q_reg_reg[0]_0 ; + output [0:0]AS; + input out; + input clk; + input [0:0]in0; + + wire [0:0]AS; + (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; + wire clk; + wire [0:0]in0; + wire out; + + assign \Q_reg_reg[0]_0 = Q_reg; (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) - FDPE #( + FDRE #( .INIT(1'b0)) - \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg + \Q_reg_reg[0] (.C(clk), .CE(1'b1), - .D(1'b0), - .PRE(rst), - .Q(rst_wr_reg1)); + .D(out), + .Q(Q_reg), + .R(1'b0)); + LUT2 #( + .INIT(4'h2)) + \ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1 + (.I0(in0), + .I1(Q_reg), + .O(AS)); +endmodule + +(* ORIG_REF_NAME = "synchronizer_ff" *) +module Arty_Z7_20_auto_pc_0_synchronizer_ff_18 + (\Q_reg_reg[0]_0 , + clk); + input \Q_reg_reg[0]_0 ; + input clk; + + (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; + wire \Q_reg_reg[0]_0 ; + wire clk; + (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) - FDPE #( + FDRE #( .INIT(1'b0)) - \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg + \Q_reg_reg[0] (.C(clk), .CE(1'b1), - .D(rst_wr_reg1), - .PRE(rst), - .Q(rst_wr_reg2)); - FDPE #( - .INIT(1'b1)) - \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg + .D(\Q_reg_reg[0]_0 ), + .Q(Q_reg), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "synchronizer_ff" *) +module Arty_Z7_20_auto_pc_0_synchronizer_ff_19 + (\Q_reg_reg[0]_0 , + clk); + input \Q_reg_reg[0]_0 ; + input clk; + + (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; + wire \Q_reg_reg[0]_0 ; + wire clk; + + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[0] (.C(clk), .CE(1'b1), - .D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ), - .PRE(rst_wr_reg2), - .Q(wr_rst_asreg)); - (* DONT_TOUCH *) + .D(\Q_reg_reg[0]_0 ), + .Q(Q_reg), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "synchronizer_ff" *) +module Arty_Z7_20_auto_pc_0_synchronizer_ff_2 + (\Q_reg_reg[0]_0 , + AS, + out, + clk, + in0); + output \Q_reg_reg[0]_0 ; + output [0:0]AS; + input out; + input clk; + input [0:0]in0; + + wire [0:0]AS; + (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; + wire clk; + wire [0:0]in0; + wire out; + + assign \Q_reg_reg[0]_0 = Q_reg; + (* ASYNC_REG *) (* KEEP = "yes" *) - (* equivalent_register_removal = "no" *) - FDPE #( - .INIT(1'b1)) - \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[0] (.C(clk), .CE(1'b1), - .D(1'b0), - .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ), - .Q(wr_rst_reg[0])); - (* DONT_TOUCH *) + .D(out), + .Q(Q_reg), + .R(1'b0)); + LUT2 #( + .INIT(4'h2)) + \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 + (.I0(in0), + .I1(Q_reg), + .O(AS)); +endmodule + +(* ORIG_REF_NAME = "synchronizer_ff" *) +module Arty_Z7_20_auto_pc_0_synchronizer_ff_29 + (out, + in0, + clk); + output out; + input [0:0]in0; + input clk; + + (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; + wire clk; + wire [0:0]in0; + + assign out = Q_reg; + (* ASYNC_REG *) (* KEEP = "yes" *) - (* equivalent_register_removal = "no" *) - FDPE #( - .INIT(1'b1)) - \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[0] (.C(clk), .CE(1'b1), - .D(1'b0), - .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ), - .Q(wr_rst_reg[1])); - (* DONT_TOUCH *) + .D(in0), + .Q(Q_reg), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "synchronizer_ff" *) +module Arty_Z7_20_auto_pc_0_synchronizer_ff_3 + (\Q_reg_reg[0]_0 , + AS, + out, + clk, + in0); + output \Q_reg_reg[0]_0 ; + output [0:0]AS; + input out; + input clk; + input [0:0]in0; + + wire [0:0]AS; + (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; + wire clk; + wire [0:0]in0; + wire out; + + assign \Q_reg_reg[0]_0 = Q_reg; + (* ASYNC_REG *) (* KEEP = "yes" *) - (* equivalent_register_removal = "no" *) - FDPE #( - .INIT(1'b1)) - \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2] + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[0] (.C(clk), .CE(1'b1), - .D(1'b0), - .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ), - .Q(wr_rst_reg[2])); + .D(out), + .Q(Q_reg), + .R(1'b0)); + LUT2 #( + .INIT(4'h2)) + \ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1 + (.I0(in0), + .I1(Q_reg), + .O(AS)); endmodule -module Arty_Z7_20_auto_pc_0_synchronizer_ff +(* ORIG_REF_NAME = "synchronizer_ff" *) +module Arty_Z7_20_auto_pc_0_synchronizer_ff_30 (out, in0, clk); @@ -6430,19 +16276,25 @@ module Arty_Z7_20_auto_pc_0_synchronizer_ff endmodule (* ORIG_REF_NAME = "synchronizer_ff" *) -module Arty_Z7_20_auto_pc_0_synchronizer_ff_0 - (out, - in0, - clk); - output out; - input [0:0]in0; +module Arty_Z7_20_auto_pc_0_synchronizer_ff_31 + (\Q_reg_reg[0]_0 , + AS, + out, + clk, + in0); + output \Q_reg_reg[0]_0 ; + output [0:0]AS; + input out; input clk; + input [0:0]in0; + wire [0:0]AS; (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; wire clk; wire [0:0]in0; + wire out; - assign out = Q_reg; + assign \Q_reg_reg[0]_0 = Q_reg; (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) @@ -6451,13 +16303,19 @@ module Arty_Z7_20_auto_pc_0_synchronizer_ff_0 \Q_reg_reg[0] (.C(clk), .CE(1'b1), - .D(in0), + .D(out), .Q(Q_reg), .R(1'b0)); + LUT2 #( + .INIT(4'h2)) + \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 + (.I0(in0), + .I1(Q_reg), + .O(AS)); endmodule (* ORIG_REF_NAME = "synchronizer_ff" *) -module Arty_Z7_20_auto_pc_0_synchronizer_ff_1 +module Arty_Z7_20_auto_pc_0_synchronizer_ff_32 (\Q_reg_reg[0]_0 , AS, out, @@ -6489,121 +16347,548 @@ module Arty_Z7_20_auto_pc_0_synchronizer_ff_1 .R(1'b0)); LUT2 #( .INIT(4'h2)) - \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 + \ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1 (.I0(in0), .I1(Q_reg), .O(AS)); endmodule -(* ORIG_REF_NAME = "synchronizer_ff" *) -module Arty_Z7_20_auto_pc_0_synchronizer_ff_2 - (\Q_reg_reg[0]_0 , - AS, +(* ORIG_REF_NAME = "synchronizer_ff" *) +module Arty_Z7_20_auto_pc_0_synchronizer_ff_33 + (\Q_reg_reg[0]_0 , + clk); + input \Q_reg_reg[0]_0 ; + input clk; + + (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; + wire \Q_reg_reg[0]_0 ; + wire clk; + + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[0] + (.C(clk), + .CE(1'b1), + .D(\Q_reg_reg[0]_0 ), + .Q(Q_reg), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "synchronizer_ff" *) +module Arty_Z7_20_auto_pc_0_synchronizer_ff_34 + (\Q_reg_reg[0]_0 , + clk); + input \Q_reg_reg[0]_0 ; + input clk; + + (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; + wire \Q_reg_reg[0]_0 ; + wire clk; + + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[0] + (.C(clk), + .CE(1'b1), + .D(\Q_reg_reg[0]_0 ), + .Q(Q_reg), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "synchronizer_ff" *) +module Arty_Z7_20_auto_pc_0_synchronizer_ff_4 + (\Q_reg_reg[0]_0 , + clk); + input \Q_reg_reg[0]_0 ; + input clk; + + (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; + wire \Q_reg_reg[0]_0 ; + wire clk; + + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[0] + (.C(clk), + .CE(1'b1), + .D(\Q_reg_reg[0]_0 ), + .Q(Q_reg), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "synchronizer_ff" *) +module Arty_Z7_20_auto_pc_0_synchronizer_ff_5 + (\Q_reg_reg[0]_0 , + clk); + input \Q_reg_reg[0]_0 ; + input clk; + + (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; + wire \Q_reg_reg[0]_0 ; + wire clk; + + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[0] + (.C(clk), + .CE(1'b1), + .D(\Q_reg_reg[0]_0 ), + .Q(Q_reg), + .R(1'b0)); +endmodule + +module Arty_Z7_20_auto_pc_0_wr_bin_cntr + (ram_full_comb, + ram_empty_fb_i_reg, + Q, + \gpregsm1.curr_fwft_state_reg[0] , + out, + \gc0.count_d1_reg[2] , + \gc0.count_reg[2] , + wr_en, + \gc0.count_d1_reg[4] , + E, + clk, + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ); + output ram_full_comb; + output ram_empty_fb_i_reg; + output [4:0]Q; + input \gpregsm1.curr_fwft_state_reg[0] ; + input out; + input \gc0.count_d1_reg[2] ; + input [2:0]\gc0.count_reg[2] ; + input wr_en; + input [4:0]\gc0.count_d1_reg[4] ; + input [0:0]E; + input clk; + input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ; + + wire [0:0]E; + wire [4:0]Q; + wire clk; + wire \gc0.count_d1_reg[2] ; + wire [4:0]\gc0.count_d1_reg[4] ; + wire [2:0]\gc0.count_reg[2] ; + wire \gpregsm1.curr_fwft_state_reg[0] ; + wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ; + wire out; + wire [4:0]p_12_out; + wire [4:0]plusOp__0; + wire ram_empty_fb_i_reg; + wire ram_full_comb; + wire ram_full_fb_i_i_2_n_0; + wire ram_full_fb_i_i_4_n_0; + wire ram_full_fb_i_i_5_n_0; + wire wr_en; + + LUT1 #( + .INIT(2'h1)) + \gcc0.gc0.count[0]_i_1 + (.I0(p_12_out[0]), + .O(plusOp__0[0])); + LUT2 #( + .INIT(4'h6)) + \gcc0.gc0.count[1]_i_1 + (.I0(p_12_out[0]), + .I1(p_12_out[1]), + .O(plusOp__0[1])); + (* SOFT_HLUTNM = "soft_lutpair39" *) + LUT3 #( + .INIT(8'h78)) + \gcc0.gc0.count[2]_i_1 + (.I0(p_12_out[1]), + .I1(p_12_out[0]), + .I2(p_12_out[2]), + .O(plusOp__0[2])); + (* SOFT_HLUTNM = "soft_lutpair38" *) + LUT4 #( + .INIT(16'h7F80)) + \gcc0.gc0.count[3]_i_1 + (.I0(p_12_out[2]), + .I1(p_12_out[0]), + .I2(p_12_out[1]), + .I3(p_12_out[3]), + .O(plusOp__0[3])); + (* SOFT_HLUTNM = "soft_lutpair38" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \gcc0.gc0.count[4]_i_1 + (.I0(p_12_out[3]), + .I1(p_12_out[1]), + .I2(p_12_out[0]), + .I3(p_12_out[2]), + .I4(p_12_out[4]), + .O(plusOp__0[4])); + FDCE #( + .INIT(1'b0)) + \gcc0.gc0.count_d1_reg[0] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(p_12_out[0]), + .Q(Q[0])); + FDCE #( + .INIT(1'b0)) + \gcc0.gc0.count_d1_reg[1] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(p_12_out[1]), + .Q(Q[1])); + FDCE #( + .INIT(1'b0)) + \gcc0.gc0.count_d1_reg[2] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(p_12_out[2]), + .Q(Q[2])); + FDCE #( + .INIT(1'b0)) + \gcc0.gc0.count_d1_reg[3] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(p_12_out[3]), + .Q(Q[3])); + FDCE #( + .INIT(1'b0)) + \gcc0.gc0.count_d1_reg[4] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(p_12_out[4]), + .Q(Q[4])); + FDPE #( + .INIT(1'b1)) + \gcc0.gc0.count_reg[0] + (.C(clk), + .CE(E), + .D(plusOp__0[0]), + .PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .Q(p_12_out[0])); + FDCE #( + .INIT(1'b0)) + \gcc0.gc0.count_reg[1] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(plusOp__0[1]), + .Q(p_12_out[1])); + FDCE #( + .INIT(1'b0)) + \gcc0.gc0.count_reg[2] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(plusOp__0[2]), + .Q(p_12_out[2])); + FDCE #( + .INIT(1'b0)) + \gcc0.gc0.count_reg[3] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(plusOp__0[3]), + .Q(p_12_out[3])); + FDCE #( + .INIT(1'b0)) + \gcc0.gc0.count_reg[4] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(plusOp__0[4]), + .Q(p_12_out[4])); + LUT6 #( + .INIT(64'h9009000000009009)) + ram_empty_fb_i_i_5 + (.I0(Q[2]), + .I1(\gc0.count_reg[2] [2]), + .I2(Q[1]), + .I3(\gc0.count_reg[2] [1]), + .I4(\gc0.count_reg[2] [0]), + .I5(Q[0]), + .O(ram_empty_fb_i_reg)); + LUT4 #( + .INIT(16'hF8C8)) + ram_full_fb_i_i_1 + (.I0(ram_full_fb_i_i_2_n_0), + .I1(\gpregsm1.curr_fwft_state_reg[0] ), + .I2(out), + .I3(\gc0.count_d1_reg[2] ), + .O(ram_full_comb)); + LUT5 #( + .INIT(32'h80000080)) + ram_full_fb_i_i_2 + (.I0(ram_full_fb_i_i_4_n_0), + .I1(ram_full_fb_i_i_5_n_0), + .I2(wr_en), + .I3(\gc0.count_d1_reg[4] [4]), + .I4(p_12_out[4]), + .O(ram_full_fb_i_i_2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ram_full_fb_i_i_4 + (.I0(p_12_out[2]), + .I1(\gc0.count_d1_reg[4] [2]), + .I2(p_12_out[3]), + .I3(\gc0.count_d1_reg[4] [3]), + .O(ram_full_fb_i_i_4_n_0)); + (* SOFT_HLUTNM = "soft_lutpair39" *) + LUT4 #( + .INIT(16'h9009)) + ram_full_fb_i_i_5 + (.I0(p_12_out[0]), + .I1(\gc0.count_d1_reg[4] [0]), + .I2(p_12_out[1]), + .I3(\gc0.count_d1_reg[4] [1]), + .O(ram_full_fb_i_i_5_n_0)); +endmodule + +(* ORIG_REF_NAME = "wr_bin_cntr" *) +module Arty_Z7_20_auto_pc_0_wr_bin_cntr_22 + (ram_full_comb, + ram_empty_fb_i_reg, + Q, + \gpregsm1.curr_fwft_state_reg[0] , out, + \gc0.count_d1_reg[2] , + \gc0.count_reg[2] , + wr_en, + \gc0.count_d1_reg[4] , + E, clk, - in0); - output \Q_reg_reg[0]_0 ; - output [0:0]AS; + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ); + output ram_full_comb; + output ram_empty_fb_i_reg; + output [4:0]Q; + input \gpregsm1.curr_fwft_state_reg[0] ; input out; + input \gc0.count_d1_reg[2] ; + input [2:0]\gc0.count_reg[2] ; + input wr_en; + input [4:0]\gc0.count_d1_reg[4] ; + input [0:0]E; input clk; - input [0:0]in0; + input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ; - wire [0:0]AS; - (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; + wire [0:0]E; + wire [4:0]Q; wire clk; - wire [0:0]in0; + wire \gc0.count_d1_reg[2] ; + wire [4:0]\gc0.count_d1_reg[4] ; + wire [2:0]\gc0.count_reg[2] ; + wire \gpregsm1.curr_fwft_state_reg[0] ; + wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ; wire out; + wire [4:0]p_12_out; + wire [4:0]plusOp__0; + wire ram_empty_fb_i_reg; + wire ram_full_comb; + wire ram_full_fb_i_i_2_n_0; + wire ram_full_fb_i_i_4_n_0; + wire ram_full_fb_i_i_5_n_0; + wire wr_en; - assign \Q_reg_reg[0]_0 = Q_reg; - (* ASYNC_REG *) - (* KEEP = "yes" *) - (* msgon = "true" *) - FDRE #( + LUT1 #( + .INIT(2'h1)) + \gcc0.gc0.count[0]_i_1 + (.I0(p_12_out[0]), + .O(plusOp__0[0])); + LUT2 #( + .INIT(4'h6)) + \gcc0.gc0.count[1]_i_1 + (.I0(p_12_out[0]), + .I1(p_12_out[1]), + .O(plusOp__0[1])); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT3 #( + .INIT(8'h78)) + \gcc0.gc0.count[2]_i_1 + (.I0(p_12_out[1]), + .I1(p_12_out[0]), + .I2(p_12_out[2]), + .O(plusOp__0[2])); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT4 #( + .INIT(16'h7F80)) + \gcc0.gc0.count[3]_i_1 + (.I0(p_12_out[2]), + .I1(p_12_out[0]), + .I2(p_12_out[1]), + .I3(p_12_out[3]), + .O(plusOp__0[3])); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \gcc0.gc0.count[4]_i_1 + (.I0(p_12_out[3]), + .I1(p_12_out[1]), + .I2(p_12_out[0]), + .I3(p_12_out[2]), + .I4(p_12_out[4]), + .O(plusOp__0[4])); + FDCE #( .INIT(1'b0)) - \Q_reg_reg[0] + \gcc0.gc0.count_d1_reg[0] (.C(clk), - .CE(1'b1), - .D(out), - .Q(Q_reg), - .R(1'b0)); - LUT2 #( - .INIT(4'h2)) - \ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1 - (.I0(in0), - .I1(Q_reg), - .O(AS)); -endmodule - -(* ORIG_REF_NAME = "synchronizer_ff" *) -module Arty_Z7_20_auto_pc_0_synchronizer_ff_3 - (\Q_reg_reg[0]_0 , - clk); - input \Q_reg_reg[0]_0 ; - input clk; - - (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; - wire \Q_reg_reg[0]_0 ; - wire clk; - - (* ASYNC_REG *) - (* KEEP = "yes" *) - (* msgon = "true" *) - FDRE #( + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(p_12_out[0]), + .Q(Q[0])); + FDCE #( .INIT(1'b0)) - \Q_reg_reg[0] + \gcc0.gc0.count_d1_reg[1] (.C(clk), - .CE(1'b1), - .D(\Q_reg_reg[0]_0 ), - .Q(Q_reg), - .R(1'b0)); -endmodule - -(* ORIG_REF_NAME = "synchronizer_ff" *) -module Arty_Z7_20_auto_pc_0_synchronizer_ff_4 - (\Q_reg_reg[0]_0 , - clk); - input \Q_reg_reg[0]_0 ; - input clk; - - (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; - wire \Q_reg_reg[0]_0 ; - wire clk; - - (* ASYNC_REG *) - (* KEEP = "yes" *) - (* msgon = "true" *) - FDRE #( + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(p_12_out[1]), + .Q(Q[1])); + FDCE #( .INIT(1'b0)) - \Q_reg_reg[0] + \gcc0.gc0.count_d1_reg[2] (.C(clk), - .CE(1'b1), - .D(\Q_reg_reg[0]_0 ), - .Q(Q_reg), - .R(1'b0)); + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(p_12_out[2]), + .Q(Q[2])); + FDCE #( + .INIT(1'b0)) + \gcc0.gc0.count_d1_reg[3] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(p_12_out[3]), + .Q(Q[3])); + FDCE #( + .INIT(1'b0)) + \gcc0.gc0.count_d1_reg[4] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(p_12_out[4]), + .Q(Q[4])); + FDPE #( + .INIT(1'b1)) + \gcc0.gc0.count_reg[0] + (.C(clk), + .CE(E), + .D(plusOp__0[0]), + .PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .Q(p_12_out[0])); + FDCE #( + .INIT(1'b0)) + \gcc0.gc0.count_reg[1] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(plusOp__0[1]), + .Q(p_12_out[1])); + FDCE #( + .INIT(1'b0)) + \gcc0.gc0.count_reg[2] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(plusOp__0[2]), + .Q(p_12_out[2])); + FDCE #( + .INIT(1'b0)) + \gcc0.gc0.count_reg[3] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(plusOp__0[3]), + .Q(p_12_out[3])); + FDCE #( + .INIT(1'b0)) + \gcc0.gc0.count_reg[4] + (.C(clk), + .CE(E), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(plusOp__0[4]), + .Q(p_12_out[4])); + LUT6 #( + .INIT(64'h9009000000009009)) + ram_empty_fb_i_i_5 + (.I0(Q[2]), + .I1(\gc0.count_reg[2] [2]), + .I2(Q[1]), + .I3(\gc0.count_reg[2] [1]), + .I4(\gc0.count_reg[2] [0]), + .I5(Q[0]), + .O(ram_empty_fb_i_reg)); + LUT4 #( + .INIT(16'hF8C8)) + ram_full_fb_i_i_1 + (.I0(ram_full_fb_i_i_2_n_0), + .I1(\gpregsm1.curr_fwft_state_reg[0] ), + .I2(out), + .I3(\gc0.count_d1_reg[2] ), + .O(ram_full_comb)); + LUT5 #( + .INIT(32'h80000080)) + ram_full_fb_i_i_2 + (.I0(ram_full_fb_i_i_4_n_0), + .I1(ram_full_fb_i_i_5_n_0), + .I2(wr_en), + .I3(\gc0.count_d1_reg[4] [4]), + .I4(p_12_out[4]), + .O(ram_full_fb_i_i_2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ram_full_fb_i_i_4 + (.I0(p_12_out[2]), + .I1(\gc0.count_d1_reg[4] [2]), + .I2(p_12_out[3]), + .I3(\gc0.count_d1_reg[4] [3]), + .O(ram_full_fb_i_i_4_n_0)); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT4 #( + .INIT(16'h9009)) + ram_full_fb_i_i_5 + (.I0(p_12_out[0]), + .I1(\gc0.count_d1_reg[4] [0]), + .I2(p_12_out[1]), + .I3(\gc0.count_d1_reg[4] [1]), + .O(ram_full_fb_i_i_5_n_0)); endmodule -module Arty_Z7_20_auto_pc_0_wr_bin_cntr - (Q, - ram_empty_i_reg, - ram_empty_i_reg_0, +(* ORIG_REF_NAME = "wr_bin_cntr" *) +module Arty_Z7_20_auto_pc_0_wr_bin_cntr_36 + (ram_full_comb, ram_empty_fb_i_reg, - \gcc0.gc0.count_d1_reg[1]_0 , - wr_en, + Q, + \gpregsm1.curr_fwft_state_reg[0] , out, - \gc0.count_reg[4] , - \gpregsm1.curr_fwft_state_reg[1] , + \gc0.count_d1_reg[2] , + \gc0.count_reg[2] , + wr_en, + \gc0.count_d1_reg[4] , E, clk, \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ); + output ram_full_comb; + output ram_empty_fb_i_reg; output [4:0]Q; - output ram_empty_i_reg; - output [4:0]ram_empty_i_reg_0; - input ram_empty_fb_i_reg; - input \gcc0.gc0.count_d1_reg[1]_0 ; - input wr_en; + input \gpregsm1.curr_fwft_state_reg[0] ; input out; - input [4:0]\gc0.count_reg[4] ; - input \gpregsm1.curr_fwft_state_reg[1] ; + input \gc0.count_d1_reg[2] ; + input [2:0]\gc0.count_reg[2] ; + input wr_en; + input [4:0]\gc0.count_d1_reg[4] ; input [0:0]E; input clk; input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ; @@ -6611,57 +16896,58 @@ module Arty_Z7_20_auto_pc_0_wr_bin_cntr wire [0:0]E; wire [4:0]Q; wire clk; - wire [4:0]\gc0.count_reg[4] ; - wire \gcc0.gc0.count_d1_reg[1]_0 ; - wire \gpregsm1.curr_fwft_state_reg[1] ; + wire \gc0.count_d1_reg[2] ; + wire [4:0]\gc0.count_d1_reg[4] ; + wire [2:0]\gc0.count_reg[2] ; + wire \gpregsm1.curr_fwft_state_reg[0] ; wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ; wire out; + wire [4:0]p_12_out; wire [4:0]plusOp__0; - wire ram_empty_fb_i_i_2_n_0; - wire ram_empty_fb_i_i_4_n_0; wire ram_empty_fb_i_reg; - wire ram_empty_i_reg; - wire [4:0]ram_empty_i_reg_0; + wire ram_full_comb; + wire ram_full_fb_i_i_2_n_0; + wire ram_full_fb_i_i_4_n_0; + wire ram_full_fb_i_i_5_n_0; wire wr_en; LUT1 #( .INIT(2'h1)) \gcc0.gc0.count[0]_i_1 - (.I0(Q[0]), + (.I0(p_12_out[0]), .O(plusOp__0[0])); - (* SOFT_HLUTNM = "soft_lutpair3" *) LUT2 #( .INIT(4'h6)) \gcc0.gc0.count[1]_i_1 - (.I0(Q[1]), - .I1(Q[0]), + (.I0(p_12_out[0]), + .I1(p_12_out[1]), .O(plusOp__0[1])); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT3 #( .INIT(8'h78)) \gcc0.gc0.count[2]_i_1 - (.I0(Q[1]), - .I1(Q[0]), - .I2(Q[2]), + (.I0(p_12_out[1]), + .I1(p_12_out[0]), + .I2(p_12_out[2]), .O(plusOp__0[2])); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT4 #( - .INIT(16'h6AAA)) + .INIT(16'h7F80)) \gcc0.gc0.count[3]_i_1 - (.I0(Q[3]), - .I1(Q[1]), - .I2(Q[0]), - .I3(Q[2]), + (.I0(p_12_out[2]), + .I1(p_12_out[0]), + .I2(p_12_out[1]), + .I3(p_12_out[3]), .O(plusOp__0[3])); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT5 #( - .INIT(32'h6AAAAAAA)) + .INIT(32'h7FFF8000)) \gcc0.gc0.count[4]_i_1 - (.I0(Q[4]), - .I1(Q[2]), - .I2(Q[0]), - .I3(Q[1]), - .I4(Q[3]), + (.I0(p_12_out[3]), + .I1(p_12_out[1]), + .I2(p_12_out[0]), + .I3(p_12_out[2]), + .I4(p_12_out[4]), .O(plusOp__0[4])); FDCE #( .INIT(1'b0)) @@ -6669,40 +16955,40 @@ module Arty_Z7_20_auto_pc_0_wr_bin_cntr (.C(clk), .CE(E), .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), - .D(Q[0]), - .Q(ram_empty_i_reg_0[0])); + .D(p_12_out[0]), + .Q(Q[0])); FDCE #( .INIT(1'b0)) \gcc0.gc0.count_d1_reg[1] (.C(clk), .CE(E), .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), - .D(Q[1]), - .Q(ram_empty_i_reg_0[1])); + .D(p_12_out[1]), + .Q(Q[1])); FDCE #( .INIT(1'b0)) \gcc0.gc0.count_d1_reg[2] (.C(clk), .CE(E), .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), - .D(Q[2]), - .Q(ram_empty_i_reg_0[2])); + .D(p_12_out[2]), + .Q(Q[2])); FDCE #( .INIT(1'b0)) \gcc0.gc0.count_d1_reg[3] (.C(clk), .CE(E), .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), - .D(Q[3]), - .Q(ram_empty_i_reg_0[3])); + .D(p_12_out[3]), + .Q(Q[3])); FDCE #( .INIT(1'b0)) \gcc0.gc0.count_d1_reg[4] (.C(clk), .CE(E), .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), - .D(Q[4]), - .Q(ram_empty_i_reg_0[4])); + .D(p_12_out[4]), + .Q(Q[4])); FDPE #( .INIT(1'b1)) \gcc0.gc0.count_reg[0] @@ -6710,7 +16996,7 @@ module Arty_Z7_20_auto_pc_0_wr_bin_cntr .CE(E), .D(plusOp__0[0]), .PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), - .Q(Q[0])); + .Q(p_12_out[0])); FDCE #( .INIT(1'b0)) \gcc0.gc0.count_reg[1] @@ -6718,7 +17004,7 @@ module Arty_Z7_20_auto_pc_0_wr_bin_cntr .CE(E), .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), .D(plusOp__0[1]), - .Q(Q[1])); + .Q(p_12_out[1])); FDCE #( .INIT(1'b0)) \gcc0.gc0.count_reg[2] @@ -6726,7 +17012,7 @@ module Arty_Z7_20_auto_pc_0_wr_bin_cntr .CE(E), .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), .D(plusOp__0[2]), - .Q(Q[2])); + .Q(p_12_out[2])); FDCE #( .INIT(1'b0)) \gcc0.gc0.count_reg[3] @@ -6734,7 +17020,7 @@ module Arty_Z7_20_auto_pc_0_wr_bin_cntr .CE(E), .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), .D(plusOp__0[3]), - .Q(Q[3])); + .Q(p_12_out[3])); FDCE #( .INIT(1'b0)) \gcc0.gc0.count_reg[4] @@ -6742,80 +17028,90 @@ module Arty_Z7_20_auto_pc_0_wr_bin_cntr .CE(E), .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), .D(plusOp__0[4]), - .Q(Q[4])); - LUT5 #( - .INIT(32'hEEEE0CEE)) - ram_empty_fb_i_i_1 - (.I0(ram_empty_fb_i_i_2_n_0), - .I1(ram_empty_fb_i_reg), - .I2(\gcc0.gc0.count_d1_reg[1]_0 ), - .I3(wr_en), - .I4(out), - .O(ram_empty_i_reg)); - LUT6 #( - .INIT(64'h0000000082000082)) - ram_empty_fb_i_i_2 - (.I0(ram_empty_fb_i_i_4_n_0), - .I1(ram_empty_i_reg_0[4]), - .I2(\gc0.count_reg[4] [4]), - .I3(ram_empty_i_reg_0[3]), - .I4(\gc0.count_reg[4] [3]), - .I5(\gpregsm1.curr_fwft_state_reg[1] ), - .O(ram_empty_fb_i_i_2_n_0)); + .Q(p_12_out[4])); LUT6 #( .INIT(64'h9009000000009009)) - ram_empty_fb_i_i_4 - (.I0(ram_empty_i_reg_0[0]), - .I1(\gc0.count_reg[4] [0]), - .I2(\gc0.count_reg[4] [2]), - .I3(ram_empty_i_reg_0[2]), - .I4(\gc0.count_reg[4] [1]), - .I5(ram_empty_i_reg_0[1]), - .O(ram_empty_fb_i_i_4_n_0)); + ram_empty_fb_i_i_5 + (.I0(Q[2]), + .I1(\gc0.count_reg[2] [2]), + .I2(Q[1]), + .I3(\gc0.count_reg[2] [1]), + .I4(\gc0.count_reg[2] [0]), + .I5(Q[0]), + .O(ram_empty_fb_i_reg)); + LUT4 #( + .INIT(16'hF8C8)) + ram_full_fb_i_i_1 + (.I0(ram_full_fb_i_i_2_n_0), + .I1(\gpregsm1.curr_fwft_state_reg[0] ), + .I2(out), + .I3(\gc0.count_d1_reg[2] ), + .O(ram_full_comb)); + LUT5 #( + .INIT(32'h80000080)) + ram_full_fb_i_i_2 + (.I0(ram_full_fb_i_i_4_n_0), + .I1(ram_full_fb_i_i_5_n_0), + .I2(wr_en), + .I3(\gc0.count_d1_reg[4] [4]), + .I4(p_12_out[4]), + .O(ram_full_fb_i_i_2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ram_full_fb_i_i_4 + (.I0(p_12_out[2]), + .I1(\gc0.count_d1_reg[4] [2]), + .I2(p_12_out[3]), + .I3(\gc0.count_d1_reg[4] [3]), + .O(ram_full_fb_i_i_4_n_0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'h9009)) + ram_full_fb_i_i_5 + (.I0(p_12_out[0]), + .I1(\gc0.count_d1_reg[4] [0]), + .I2(p_12_out[1]), + .I3(\gc0.count_d1_reg[4] [1]), + .O(ram_full_fb_i_i_5_n_0)); endmodule module Arty_Z7_20_auto_pc_0_wr_logic (out, full, - Q, - ram_empty_i_reg, - ram_empty_i_reg_0, E, - ram_full_comb, + ram_empty_fb_i_reg, + Q, clk, \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] , - ram_empty_fb_i_reg, - \gcc0.gc0.count_d1_reg[1] , wr_en, - \gc0.count_reg[4] , - \gpregsm1.curr_fwft_state_reg[1] ); + \gpregsm1.curr_fwft_state_reg[0] , + \gc0.count_d1_reg[2] , + \gc0.count_reg[2] , + \gc0.count_d1_reg[4] ); output out; output full; - output [4:0]Q; - output ram_empty_i_reg; - output [4:0]ram_empty_i_reg_0; output [0:0]E; - input ram_full_comb; + output ram_empty_fb_i_reg; + output [4:0]Q; input clk; input [1:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ; - input ram_empty_fb_i_reg; - input \gcc0.gc0.count_d1_reg[1] ; input wr_en; - input [4:0]\gc0.count_reg[4] ; - input \gpregsm1.curr_fwft_state_reg[1] ; + input \gpregsm1.curr_fwft_state_reg[0] ; + input \gc0.count_d1_reg[2] ; + input [2:0]\gc0.count_reg[2] ; + input [4:0]\gc0.count_d1_reg[4] ; wire [0:0]E; wire [4:0]Q; wire clk; wire full; - wire [4:0]\gc0.count_reg[4] ; - wire \gcc0.gc0.count_d1_reg[1] ; - wire \gpregsm1.curr_fwft_state_reg[1] ; + wire \gc0.count_d1_reg[2] ; + wire [4:0]\gc0.count_d1_reg[4] ; + wire [2:0]\gc0.count_reg[2] ; + wire \gpregsm1.curr_fwft_state_reg[0] ; wire [1:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ; wire out; wire ram_empty_fb_i_reg; - wire ram_empty_i_reg; - wire [4:0]ram_empty_i_reg_0; wire ram_full_comb; wire wr_en; @@ -6831,14 +17127,142 @@ module Arty_Z7_20_auto_pc_0_wr_logic (.E(E), .Q(Q), .clk(clk), - .\gc0.count_reg[4] (\gc0.count_reg[4] ), - .\gcc0.gc0.count_d1_reg[1]_0 (\gcc0.gc0.count_d1_reg[1] ), - .\gpregsm1.curr_fwft_state_reg[1] (\gpregsm1.curr_fwft_state_reg[1] ), + .\gc0.count_d1_reg[2] (\gc0.count_d1_reg[2] ), + .\gc0.count_d1_reg[4] (\gc0.count_d1_reg[4] ), + .\gc0.count_reg[2] (\gc0.count_reg[2] ), + .\gpregsm1.curr_fwft_state_reg[0] (\gpregsm1.curr_fwft_state_reg[0] ), + .\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] [1]), + .out(out), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_full_comb(ram_full_comb), + .wr_en(wr_en)); +endmodule + +(* ORIG_REF_NAME = "wr_logic" *) +module Arty_Z7_20_auto_pc_0_wr_logic_11 + (out, + full, + E, + ram_empty_fb_i_reg, + Q, + clk, + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] , + wr_en, + \gpregsm1.curr_fwft_state_reg[0] , + \gc0.count_d1_reg[2] , + \gc0.count_reg[2] , + \gc0.count_d1_reg[4] ); + output out; + output full; + output [0:0]E; + output ram_empty_fb_i_reg; + output [4:0]Q; + input clk; + input [1:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ; + input wr_en; + input \gpregsm1.curr_fwft_state_reg[0] ; + input \gc0.count_d1_reg[2] ; + input [2:0]\gc0.count_reg[2] ; + input [4:0]\gc0.count_d1_reg[4] ; + + wire [0:0]E; + wire [4:0]Q; + wire clk; + wire full; + wire \gc0.count_d1_reg[2] ; + wire [4:0]\gc0.count_d1_reg[4] ; + wire [2:0]\gc0.count_reg[2] ; + wire \gpregsm1.curr_fwft_state_reg[0] ; + wire [1:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ; + wire out; + wire ram_empty_fb_i_reg; + wire ram_full_comb; + wire wr_en; + + Arty_Z7_20_auto_pc_0_wr_status_flags_ss_21 \gwss.wsts + (.E(E), + .clk(clk), + .full(full), + .\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] (\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] [0]), + .out(out), + .ram_full_comb(ram_full_comb), + .wr_en(wr_en)); + Arty_Z7_20_auto_pc_0_wr_bin_cntr_22 wpntr + (.E(E), + .Q(Q), + .clk(clk), + .\gc0.count_d1_reg[2] (\gc0.count_d1_reg[2] ), + .\gc0.count_d1_reg[4] (\gc0.count_d1_reg[4] ), + .\gc0.count_reg[2] (\gc0.count_reg[2] ), + .\gpregsm1.curr_fwft_state_reg[0] (\gpregsm1.curr_fwft_state_reg[0] ), + .\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] [1]), + .out(out), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_full_comb(ram_full_comb), + .wr_en(wr_en)); +endmodule + +(* ORIG_REF_NAME = "wr_logic" *) +module Arty_Z7_20_auto_pc_0_wr_logic_27 + (out, + full, + E, + ram_empty_fb_i_reg, + Q, + clk, + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] , + wr_en, + \gpregsm1.curr_fwft_state_reg[0] , + \gc0.count_d1_reg[2] , + \gc0.count_reg[2] , + \gc0.count_d1_reg[4] ); + output out; + output full; + output [0:0]E; + output ram_empty_fb_i_reg; + output [4:0]Q; + input clk; + input [1:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ; + input wr_en; + input \gpregsm1.curr_fwft_state_reg[0] ; + input \gc0.count_d1_reg[2] ; + input [2:0]\gc0.count_reg[2] ; + input [4:0]\gc0.count_d1_reg[4] ; + + wire [0:0]E; + wire [4:0]Q; + wire clk; + wire full; + wire \gc0.count_d1_reg[2] ; + wire [4:0]\gc0.count_d1_reg[4] ; + wire [2:0]\gc0.count_reg[2] ; + wire \gpregsm1.curr_fwft_state_reg[0] ; + wire [1:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ; + wire out; + wire ram_empty_fb_i_reg; + wire ram_full_comb; + wire wr_en; + + Arty_Z7_20_auto_pc_0_wr_status_flags_ss_35 \gwss.wsts + (.E(E), + .clk(clk), + .full(full), + .\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] (\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] [0]), + .out(out), + .ram_full_comb(ram_full_comb), + .wr_en(wr_en)); + Arty_Z7_20_auto_pc_0_wr_bin_cntr_36 wpntr + (.E(E), + .Q(Q), + .clk(clk), + .\gc0.count_d1_reg[2] (\gc0.count_d1_reg[2] ), + .\gc0.count_d1_reg[4] (\gc0.count_d1_reg[4] ), + .\gc0.count_reg[2] (\gc0.count_reg[2] ), + .\gpregsm1.curr_fwft_state_reg[0] (\gpregsm1.curr_fwft_state_reg[0] ), .\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] [1]), .out(out), .ram_empty_fb_i_reg(ram_empty_fb_i_reg), - .ram_empty_i_reg(ram_empty_i_reg), - .ram_empty_i_reg_0(ram_empty_i_reg_0), + .ram_full_comb(ram_full_comb), .wr_en(wr_en)); endmodule @@ -6909,6 +17333,144 @@ module Arty_Z7_20_auto_pc_0_wr_status_flags_ss .D(ram_full_comb), .Q(ram_full_i)); endmodule + +(* ORIG_REF_NAME = "wr_status_flags_ss" *) +module Arty_Z7_20_auto_pc_0_wr_status_flags_ss_21 + (out, + full, + E, + ram_full_comb, + clk, + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] , + wr_en); + output out; + output full; + output [0:0]E; + input ram_full_comb; + input clk; + input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ; + input wr_en; + + wire [0:0]E; + wire clk; + wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ; + (* DONT_TOUCH *) wire ram_afull_fb; + (* DONT_TOUCH *) wire ram_afull_i; + wire ram_full_comb; + (* DONT_TOUCH *) wire ram_full_fb_i; + (* DONT_TOUCH *) wire ram_full_i; + wire wr_en; + + assign full = ram_full_i; + assign out = ram_full_fb_i; + LUT2 #( + .INIT(4'h2)) + \gcc0.gc0.count_d1[4]_i_1 + (.I0(wr_en), + .I1(ram_full_fb_i), + .O(E)); + LUT1 #( + .INIT(2'h2)) + i_0 + (.I0(1'b0), + .O(ram_afull_i)); + LUT1 #( + .INIT(2'h2)) + i_1 + (.I0(1'b0), + .O(ram_afull_fb)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDCE #( + .INIT(1'b0)) + ram_full_fb_i_reg + (.C(clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ), + .D(ram_full_comb), + .Q(ram_full_fb_i)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDCE #( + .INIT(1'b0)) + ram_full_i_reg + (.C(clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ), + .D(ram_full_comb), + .Q(ram_full_i)); +endmodule + +(* ORIG_REF_NAME = "wr_status_flags_ss" *) +module Arty_Z7_20_auto_pc_0_wr_status_flags_ss_35 + (out, + full, + E, + ram_full_comb, + clk, + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] , + wr_en); + output out; + output full; + output [0:0]E; + input ram_full_comb; + input clk; + input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ; + input wr_en; + + wire [0:0]E; + wire clk; + wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ; + (* DONT_TOUCH *) wire ram_afull_fb; + (* DONT_TOUCH *) wire ram_afull_i; + wire ram_full_comb; + (* DONT_TOUCH *) wire ram_full_fb_i; + (* DONT_TOUCH *) wire ram_full_i; + wire wr_en; + + assign full = ram_full_i; + assign out = ram_full_fb_i; + LUT2 #( + .INIT(4'h2)) + \gcc0.gc0.count_d1[4]_i_1 + (.I0(wr_en), + .I1(ram_full_fb_i), + .O(E)); + LUT1 #( + .INIT(2'h2)) + i_0 + (.I0(1'b0), + .O(ram_afull_i)); + LUT1 #( + .INIT(2'h2)) + i_1 + (.I0(1'b0), + .O(ram_afull_fb)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDCE #( + .INIT(1'b0)) + ram_full_fb_i_reg + (.C(clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ), + .D(ram_full_comb), + .Q(ram_full_fb_i)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDCE #( + .INIT(1'b0)) + ram_full_i_reg + (.C(clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ), + .D(ram_full_comb), + .Q(ram_full_i)); +endmodule `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0_sim_netlist.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0_sim_netlist.vhdl index 13d2de3..fc1346e 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0_sim_netlist.vhdl +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0_sim_netlist.vhdl @@ -1,7 +1,7 @@ -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 --- Date : Fri Feb 24 16:07:07 2017 +-- Date : Sat Mar 04 18:58:36 2017 -- Host : WK73 running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim -rename_top Arty_Z7_20_auto_pc_0 -prefix -- Arty_Z7_20_auto_pc_0_ Arty_Z7_20_auto_pc_0_sim_netlist.vhdl @@ -14,676 +14,826 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_auto_pc_0_dmem is +entity Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_b_downsizer is port ( - p_0_out : out STD_LOGIC; - dout_i : out STD_LOGIC; - \goreg_dm.dout_i_reg[0]\ : out STD_LOGIC; - clk : in STD_LOGIC; - din : in STD_LOGIC_VECTOR ( 0 to 0 ); - E : in STD_LOGIC_VECTOR ( 0 to 0 ); - \gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); - \gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); - ram_empty_fb_i_reg : in STD_LOGIC; - \gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); - rd_en : in STD_LOGIC; - \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - dout : in STD_LOGIC_VECTOR ( 0 to 0 ) + last_word : out STD_LOGIC; + s_axi_bvalid : out STD_LOGIC; + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_bready : out STD_LOGIC; + aresetn : in STD_LOGIC; + aclk : in STD_LOGIC; + dout : in STD_LOGIC_VECTOR ( 4 downto 0 ); + s_axi_bready : in STD_LOGIC; + m_axi_bvalid : in STD_LOGIC; + m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ) ); -end Arty_Z7_20_auto_pc_0_dmem; +end Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_b_downsizer; -architecture STRUCTURE of Arty_Z7_20_auto_pc_0_dmem is - signal \^dout_i\ : STD_LOGIC; - signal NLW_RAM_reg_0_31_0_0_SPO_UNCONNECTED : STD_LOGIC; +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_b_downsizer is + signal S_AXI_BRESP_ACC : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal first_mi_word : STD_LOGIC; + signal \^last_word\ : STD_LOGIC; + signal next_repeat_cnt : STD_LOGIC_VECTOR ( 0 to 0 ); + signal p_2_in : STD_LOGIC; + signal \repeat_cnt[1]_i_1_n_0\ : STD_LOGIC; + signal \repeat_cnt[2]_i_1_n_0\ : STD_LOGIC; + signal \repeat_cnt[3]_i_1_n_0\ : STD_LOGIC; + signal \repeat_cnt[3]_i_2_n_0\ : STD_LOGIC; + signal repeat_cnt_pre : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \repeat_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair27"; + attribute SOFT_HLUTNM of \repeat_cnt[0]_i_1\ : label is "soft_lutpair26"; + attribute SOFT_HLUTNM of \repeat_cnt[1]_i_1\ : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of \repeat_cnt[2]_i_2\ : label is "soft_lutpair26"; + attribute SOFT_HLUTNM of \repeat_cnt[3]_i_2\ : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of s_axi_bvalid_INST_0 : label is "soft_lutpair27"; begin - dout_i <= \^dout_i\; -RAM_reg_0_31_0_0: unisim.vcomponents.RAM32X1D + last_word <= \^last_word\; + s_axi_bresp(1 downto 0) <= \^s_axi_bresp\(1 downto 0); +\S_AXI_BRESP_ACC_reg[0]\: unisim.vcomponents.FDRE port map ( - A0 => \gcc0.gc0.count_d1_reg[4]\(0), - A1 => \gcc0.gc0.count_d1_reg[4]\(1), - A2 => \gcc0.gc0.count_d1_reg[4]\(2), - A3 => \gcc0.gc0.count_d1_reg[4]\(3), - A4 => \gcc0.gc0.count_d1_reg[4]\(4), - D => din(0), - DPO => p_0_out, - DPRA0 => \gc0.count_d1_reg[4]\(0), - DPRA1 => \gc0.count_d1_reg[4]\(1), - DPRA2 => \gc0.count_d1_reg[4]\(2), - DPRA3 => \gc0.count_d1_reg[4]\(3), - DPRA4 => \gc0.count_d1_reg[4]\(4), - SPO => NLW_RAM_reg_0_31_0_0_SPO_UNCONNECTED, - WCLK => clk, - WE => E(0) + C => aclk, + CE => p_2_in, + D => \^s_axi_bresp\(0), + Q => S_AXI_BRESP_ACC(0), + R => aresetn ); -\goreg_dm.dout_i[0]_i_1\: unisim.vcomponents.LUT6 +\S_AXI_BRESP_ACC_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_2_in, + D => \^s_axi_bresp\(1), + Q => S_AXI_BRESP_ACC(1), + R => aresetn + ); +first_mi_word_i_1: unisim.vcomponents.LUT3 generic map( - INIT => X"FFFFAEFF0000A200" + INIT => X"B0" ) port map ( - I0 => \^dout_i\, - I1 => \gpregsm1.curr_fwft_state_reg[1]\(0), - I2 => rd_en, - I3 => \gpregsm1.curr_fwft_state_reg[1]\(1), - I4 => \out\(0), - I5 => dout(0), - O => \goreg_dm.dout_i_reg[0]\ + I0 => s_axi_bready, + I1 => \^last_word\, + I2 => m_axi_bvalid, + O => p_2_in ); -\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE +first_mi_word_reg: unisim.vcomponents.FDSE + port map ( + C => aclk, + CE => p_2_in, + D => \^last_word\, + Q => first_mi_word, + S => aresetn + ); +m_axi_bready_INST_0: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"A2" ) port map ( - C => clk, - CE => '1', - D => ram_empty_fb_i_reg, - Q => \^dout_i\, - R => '0' + I0 => m_axi_bvalid, + I1 => \^last_word\, + I2 => s_axi_bready, + O => m_axi_bready ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_auto_pc_0_rd_bin_cntr is - port ( - Q : out STD_LOGIC_VECTOR ( 4 downto 0 ); - ram_full_comb : out STD_LOGIC; - ram_full_i_reg : out STD_LOGIC; - ram_full_i_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 ); - ram_full_fb_i_reg : in STD_LOGIC; - E : in STD_LOGIC_VECTOR ( 0 to 0 ); - \gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); - wr_en : in STD_LOGIC; - \gcc0.gc0.count_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); - clk : in STD_LOGIC; - AR : in STD_LOGIC_VECTOR ( 0 to 0 ) - ); -end Arty_Z7_20_auto_pc_0_rd_bin_cntr; - -architecture STRUCTURE of Arty_Z7_20_auto_pc_0_rd_bin_cntr is - signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal plusOp : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal ram_empty_fb_i_i_6_n_0 : STD_LOGIC; - signal ram_full_fb_i_i_2_n_0 : STD_LOGIC; - signal ram_full_fb_i_i_3_n_0 : STD_LOGIC; - signal ram_full_fb_i_i_4_n_0 : STD_LOGIC; - signal \^ram_full_i_reg\ : STD_LOGIC; - signal \^ram_full_i_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair1"; - attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair1"; - attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair0"; - attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair0"; -begin - Q(4 downto 0) <= \^q\(4 downto 0); - ram_full_i_reg <= \^ram_full_i_reg\; - ram_full_i_reg_0(4 downto 0) <= \^ram_full_i_reg_0\(4 downto 0); -\gc0.count[0]_i_1\: unisim.vcomponents.LUT1 +\repeat_cnt[0]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"1" + INIT => X"1D" ) port map ( - I0 => \^q\(0), - O => plusOp(0) + I0 => \repeat_cnt_reg__0\(0), + I1 => first_mi_word, + I2 => dout(0), + O => next_repeat_cnt(0) ); -\gc0.count[1]_i_1\: unisim.vcomponents.LUT2 +\repeat_cnt[1]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"6" + INIT => X"CCA533A5" ) port map ( - I0 => \^q\(1), - I1 => \^q\(0), - O => plusOp(1) - ); -\gc0.count[2]_i_1\: unisim.vcomponents.LUT3 + I0 => \repeat_cnt_reg__0\(0), + I1 => dout(0), + I2 => \repeat_cnt_reg__0\(1), + I3 => first_mi_word, + I4 => dout(1), + O => \repeat_cnt[1]_i_1_n_0\ + ); +\repeat_cnt[2]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"78" + INIT => X"FAFAFC030505FC03" ) port map ( - I0 => \^q\(1), - I1 => \^q\(0), - I2 => \^q\(2), - O => plusOp(2) - ); -\gc0.count[3]_i_1\: unisim.vcomponents.LUT4 + I0 => dout(1), + I1 => \repeat_cnt_reg__0\(1), + I2 => repeat_cnt_pre(0), + I3 => \repeat_cnt_reg__0\(2), + I4 => first_mi_word, + I5 => dout(2), + O => \repeat_cnt[2]_i_1_n_0\ + ); +\repeat_cnt[2]_i_2\: unisim.vcomponents.LUT3 generic map( - INIT => X"6AAA" + INIT => X"B8" ) port map ( - I0 => \^q\(3), - I1 => \^q\(1), - I2 => \^q\(0), - I3 => \^q\(2), - O => plusOp(3) + I0 => dout(0), + I1 => first_mi_word, + I2 => \repeat_cnt_reg__0\(0), + O => repeat_cnt_pre(0) ); -\gc0.count[4]_i_1\: unisim.vcomponents.LUT5 +\repeat_cnt[3]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"6AAAAAAA" + INIT => X"FAFAFC030505FC03" ) port map ( - I0 => \^q\(4), - I1 => \^q\(2), - I2 => \^q\(0), - I3 => \^q\(1), - I4 => \^q\(3), - O => plusOp(4) - ); -\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE + I0 => dout(2), + I1 => \repeat_cnt_reg__0\(2), + I2 => \repeat_cnt[3]_i_2_n_0\, + I3 => \repeat_cnt_reg__0\(3), + I4 => first_mi_word, + I5 => dout(3), + O => \repeat_cnt[3]_i_1_n_0\ + ); +\repeat_cnt[3]_i_2\: unisim.vcomponents.LUT5 generic map( - INIT => '0' + INIT => X"FFFACCFA" ) port map ( - C => clk, - CE => E(0), - CLR => AR(0), - D => \^q\(0), - Q => \^ram_full_i_reg_0\(0) + I0 => \repeat_cnt_reg__0\(0), + I1 => dout(0), + I2 => \repeat_cnt_reg__0\(1), + I3 => first_mi_word, + I4 => dout(1), + O => \repeat_cnt[3]_i_2_n_0\ + ); +\repeat_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_2_in, + D => next_repeat_cnt(0), + Q => \repeat_cnt_reg__0\(0), + R => aresetn ); -\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE +\repeat_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_2_in, + D => \repeat_cnt[1]_i_1_n_0\, + Q => \repeat_cnt_reg__0\(1), + R => aresetn + ); +\repeat_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_2_in, + D => \repeat_cnt[2]_i_1_n_0\, + Q => \repeat_cnt_reg__0\(2), + R => aresetn + ); +\repeat_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_2_in, + D => \repeat_cnt[3]_i_1_n_0\, + Q => \repeat_cnt_reg__0\(3), + R => aresetn + ); +\s_axi_bresp[0]_INST_0\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"F2F0F2F2F0F0D0F0" ) port map ( - C => clk, - CE => E(0), - CLR => AR(0), - D => \^q\(1), - Q => \^ram_full_i_reg_0\(1) - ); -\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE + I0 => dout(4), + I1 => first_mi_word, + I2 => m_axi_bresp(0), + I3 => S_AXI_BRESP_ACC(1), + I4 => m_axi_bresp(1), + I5 => S_AXI_BRESP_ACC(0), + O => \^s_axi_bresp\(0) + ); +\s_axi_bresp[1]_INST_0\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"FF20" ) port map ( - C => clk, - CE => E(0), - CLR => AR(0), - D => \^q\(2), - Q => \^ram_full_i_reg_0\(2) + I0 => dout(4), + I1 => first_mi_word, + I2 => S_AXI_BRESP_ACC(1), + I3 => m_axi_bresp(1), + O => \^s_axi_bresp\(1) ); -\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE +s_axi_bvalid_INST_0: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => clk, - CE => E(0), - CLR => AR(0), - D => \^q\(3), - Q => \^ram_full_i_reg_0\(3) + I0 => m_axi_bvalid, + I1 => \^last_word\, + O => s_axi_bvalid ); -\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE +s_axi_bvalid_INST_0_i_1: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"5555555555555557" ) port map ( - C => clk, - CE => E(0), - CLR => AR(0), - D => \^q\(4), - Q => \^ram_full_i_reg_0\(4) + I0 => dout(4), + I1 => \repeat_cnt_reg__0\(2), + I2 => first_mi_word, + I3 => \repeat_cnt_reg__0\(0), + I4 => \repeat_cnt_reg__0\(1), + I5 => \repeat_cnt_reg__0\(3), + O => \^last_word\ ); -\gc0.count_reg[0]\: unisim.vcomponents.FDPE +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_w_axi3_conv is + port ( + m_axi_wlast : out STD_LOGIC; + wr_cmd_ready : out STD_LOGIC; + aresetn : in STD_LOGIC; + empty_fwft_i_reg : in STD_LOGIC; + aclk : in STD_LOGIC; + dout : in STD_LOGIC_VECTOR ( 3 downto 0 ); + empty : in STD_LOGIC; + s_axi_wvalid : in STD_LOGIC; + m_axi_wready : in STD_LOGIC + ); +end Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_w_axi3_conv; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_w_axi3_conv is + signal first_mi_word : STD_LOGIC; + signal length_counter : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \length_counter_1[1]_i_1_n_0\ : STD_LOGIC; + signal \length_counter_1[2]_i_1_n_0\ : STD_LOGIC; + signal \length_counter_1[3]_i_1_n_0\ : STD_LOGIC; + signal \length_counter_1[3]_i_2_n_0\ : STD_LOGIC; + signal \length_counter_1[4]_i_1_n_0\ : STD_LOGIC; + signal \length_counter_1[5]_i_1_n_0\ : STD_LOGIC; + signal \length_counter_1[5]_i_2_n_0\ : STD_LOGIC; + signal \length_counter_1[6]_i_1_n_0\ : STD_LOGIC; + signal \length_counter_1[7]_i_1_n_0\ : STD_LOGIC; + signal \length_counter_1[7]_i_2_n_0\ : STD_LOGIC; + signal length_counter_1_reg : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \^m_axi_wlast\ : STD_LOGIC; + signal m_axi_wlast_INST_0_i_1_n_0 : STD_LOGIC; + signal m_axi_wlast_INST_0_i_2_n_0 : STD_LOGIC; + signal m_axi_wlast_INST_0_i_3_n_0 : STD_LOGIC; + signal next_length_counter : STD_LOGIC_VECTOR ( 0 to 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \length_counter_1[1]_i_1\ : label is "soft_lutpair59"; + attribute SOFT_HLUTNM of \length_counter_1[2]_i_2\ : label is "soft_lutpair59"; + attribute SOFT_HLUTNM of \length_counter_1[3]_i_2\ : label is "soft_lutpair58"; + attribute SOFT_HLUTNM of m_axi_wlast_INST_0_i_3 : label is "soft_lutpair58"; +begin + m_axi_wlast <= \^m_axi_wlast\; +fifo_gen_inst_i_2: unisim.vcomponents.LUT6 generic map( - INIT => '1' + INIT => X"0080000000000000" ) port map ( - C => clk, - CE => E(0), - D => plusOp(0), - PRE => AR(0), - Q => \^q\(0) + I0 => m_axi_wlast_INST_0_i_3_n_0, + I1 => m_axi_wlast_INST_0_i_2_n_0, + I2 => m_axi_wlast_INST_0_i_1_n_0, + I3 => empty, + I4 => s_axi_wvalid, + I5 => m_axi_wready, + O => wr_cmd_ready ); -\gc0.count_reg[1]\: unisim.vcomponents.FDCE +first_mi_word_reg: unisim.vcomponents.FDSE + port map ( + C => aclk, + CE => empty_fwft_i_reg, + D => \^m_axi_wlast\, + Q => first_mi_word, + S => aresetn + ); +\length_counter_1[0]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"1D" ) port map ( - C => clk, - CE => E(0), - CLR => AR(0), - D => plusOp(1), - Q => \^q\(1) + I0 => length_counter_1_reg(0), + I1 => first_mi_word, + I2 => dout(0), + O => next_length_counter(0) ); -\gc0.count_reg[2]\: unisim.vcomponents.FDCE +\length_counter_1[1]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => '0' + INIT => X"CCA533A5" ) port map ( - C => clk, - CE => E(0), - CLR => AR(0), - D => plusOp(2), - Q => \^q\(2) - ); -\gc0.count_reg[3]\: unisim.vcomponents.FDCE + I0 => length_counter_1_reg(0), + I1 => dout(0), + I2 => length_counter_1_reg(1), + I3 => first_mi_word, + I4 => dout(1), + O => \length_counter_1[1]_i_1_n_0\ + ); +\length_counter_1[2]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FAFAFC030505FC03" ) port map ( - C => clk, - CE => E(0), - CLR => AR(0), - D => plusOp(3), - Q => \^q\(3) - ); -\gc0.count_reg[4]\: unisim.vcomponents.FDCE + I0 => dout(1), + I1 => length_counter_1_reg(1), + I2 => length_counter(0), + I3 => length_counter_1_reg(2), + I4 => first_mi_word, + I5 => dout(2), + O => \length_counter_1[2]_i_1_n_0\ + ); +\length_counter_1[2]_i_2\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => clk, - CE => E(0), - CLR => AR(0), - D => plusOp(4), - Q => \^q\(4) + I0 => dout(0), + I1 => first_mi_word, + I2 => length_counter_1_reg(0), + O => length_counter(0) ); -ram_empty_fb_i_i_3: unisim.vcomponents.LUT5 +\length_counter_1[3]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"00009009" + INIT => X"FAFAFC030505FC03" ) port map ( - I0 => \gcc0.gc0.count_d1_reg[4]\(1), - I1 => \^ram_full_i_reg_0\(1), - I2 => \gcc0.gc0.count_d1_reg[4]\(2), - I3 => \^ram_full_i_reg_0\(2), - I4 => ram_empty_fb_i_i_6_n_0, - O => \^ram_full_i_reg\ - ); -ram_empty_fb_i_i_6: unisim.vcomponents.LUT6 + I0 => dout(2), + I1 => length_counter_1_reg(2), + I2 => \length_counter_1[3]_i_2_n_0\, + I3 => length_counter_1_reg(3), + I4 => first_mi_word, + I5 => dout(3), + O => \length_counter_1[3]_i_1_n_0\ + ); +\length_counter_1[3]_i_2\: unisim.vcomponents.LUT5 generic map( - INIT => X"6FF6FFFFFFFF6FF6" + INIT => X"FFFACCFA" ) port map ( - I0 => \^ram_full_i_reg_0\(0), - I1 => \gcc0.gc0.count_d1_reg[4]\(0), - I2 => \gcc0.gc0.count_d1_reg[4]\(4), - I3 => \^ram_full_i_reg_0\(4), - I4 => \gcc0.gc0.count_d1_reg[4]\(3), - I5 => \^ram_full_i_reg_0\(3), - O => ram_empty_fb_i_i_6_n_0 - ); -ram_full_fb_i_i_1: unisim.vcomponents.LUT4 + I0 => length_counter_1_reg(0), + I1 => dout(0), + I2 => length_counter_1_reg(1), + I3 => first_mi_word, + I4 => dout(1), + O => \length_counter_1[3]_i_2_n_0\ + ); +\length_counter_1[4]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"08AA" + INIT => X"05FC0503" ) port map ( - I0 => ram_full_fb_i_i_2_n_0, - I1 => ram_full_fb_i_reg, - I2 => \^ram_full_i_reg\, - I3 => E(0), - O => ram_full_comb - ); -ram_full_fb_i_i_2: unisim.vcomponents.LUT6 + I0 => dout(3), + I1 => length_counter_1_reg(3), + I2 => \length_counter_1[5]_i_2_n_0\, + I3 => first_mi_word, + I4 => length_counter_1_reg(4), + O => \length_counter_1[4]_i_1_n_0\ + ); +\length_counter_1[5]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"ABAAAAAAAAAAABAA" + INIT => X"0033FEFE00330101" ) port map ( - I0 => ram_full_fb_i_reg, - I1 => ram_full_fb_i_i_3_n_0, - I2 => ram_full_fb_i_i_4_n_0, - I3 => wr_en, - I4 => \^ram_full_i_reg_0\(4), - I5 => \gcc0.gc0.count_reg[4]\(4), - O => ram_full_fb_i_i_2_n_0 - ); -ram_full_fb_i_i_3: unisim.vcomponents.LUT4 + I0 => length_counter_1_reg(4), + I1 => \length_counter_1[5]_i_2_n_0\, + I2 => length_counter_1_reg(3), + I3 => dout(3), + I4 => first_mi_word, + I5 => length_counter_1_reg(5), + O => \length_counter_1[5]_i_1_n_0\ + ); +\length_counter_1[5]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"6FF6" + INIT => X"FFFFFFFCFAFAFFFC" ) port map ( - I0 => \^ram_full_i_reg_0\(2), - I1 => \gcc0.gc0.count_reg[4]\(2), - I2 => \^ram_full_i_reg_0\(3), - I3 => \gcc0.gc0.count_reg[4]\(3), - O => ram_full_fb_i_i_3_n_0 - ); -ram_full_fb_i_i_4: unisim.vcomponents.LUT4 + I0 => dout(1), + I1 => length_counter_1_reg(1), + I2 => length_counter(0), + I3 => length_counter_1_reg(2), + I4 => first_mi_word, + I5 => dout(2), + O => \length_counter_1[5]_i_2_n_0\ + ); +\length_counter_1[6]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"6FF6" + INIT => X"33FE3301" ) port map ( - I0 => \^ram_full_i_reg_0\(0), - I1 => \gcc0.gc0.count_reg[4]\(0), - I2 => \^ram_full_i_reg_0\(1), - I3 => \gcc0.gc0.count_reg[4]\(1), - O => ram_full_fb_i_i_4_n_0 + I0 => length_counter_1_reg(5), + I1 => \length_counter_1[7]_i_2_n_0\, + I2 => length_counter_1_reg(4), + I3 => first_mi_word, + I4 => length_counter_1_reg(6), + O => \length_counter_1[6]_i_1_n_0\ + ); +\length_counter_1[7]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0F0FFFFE0F0F0001" + ) + port map ( + I0 => length_counter_1_reg(6), + I1 => length_counter_1_reg(4), + I2 => \length_counter_1[7]_i_2_n_0\, + I3 => length_counter_1_reg(5), + I4 => first_mi_word, + I5 => length_counter_1_reg(7), + O => \length_counter_1[7]_i_1_n_0\ + ); +\length_counter_1[7]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFCFAFAFFFC" + ) + port map ( + I0 => dout(2), + I1 => length_counter_1_reg(2), + I2 => \length_counter_1[3]_i_2_n_0\, + I3 => length_counter_1_reg(3), + I4 => first_mi_word, + I5 => dout(3), + O => \length_counter_1[7]_i_2_n_0\ + ); +\length_counter_1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => empty_fwft_i_reg, + D => next_length_counter(0), + Q => length_counter_1_reg(0), + R => aresetn ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_auto_pc_0_rd_fwft is - port ( - \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); - empty : out STD_LOGIC; - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - \gpr1.dout_i_reg[0]\ : out STD_LOGIC; - ram_empty_i_reg : out STD_LOGIC; - clk : in STD_LOGIC; - AR : in STD_LOGIC_VECTOR ( 0 to 0 ); - ram_empty_fb_i_reg : in STD_LOGIC; - rd_en : in STD_LOGIC; - p_0_out : in STD_LOGIC; - dout_i : in STD_LOGIC - ); -end Arty_Z7_20_auto_pc_0_rd_fwft; - -architecture STRUCTURE of Arty_Z7_20_auto_pc_0_rd_fwft is - signal aempty_fwft_fb_i : STD_LOGIC; - attribute DONT_TOUCH : boolean; - attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true; - signal aempty_fwft_i : STD_LOGIC; - attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true; - signal aempty_fwft_i0 : STD_LOGIC; - signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 ); - attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true; - signal empty_fwft_fb_i : STD_LOGIC; - attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true; - signal empty_fwft_fb_o_i : STD_LOGIC; - attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true; - signal empty_fwft_fb_o_i0 : STD_LOGIC; - signal empty_fwft_i : STD_LOGIC; - attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true; - signal empty_fwft_i0 : STD_LOGIC; - signal \gpregsm1.curr_fwft_state[1]_i_1_n_0\ : STD_LOGIC; - signal next_fwft_state : STD_LOGIC_VECTOR ( 0 to 0 ); - signal user_valid : STD_LOGIC; - attribute DONT_TOUCH of user_valid : signal is std.standard.true; - attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true; - attribute KEEP : string; - attribute KEEP of aempty_fwft_fb_i_reg : label is "yes"; - attribute equivalent_register_removal : string; - attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no"; - attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true; - attribute KEEP of aempty_fwft_i_reg : label is "yes"; - attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no"; - attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true; - attribute KEEP of empty_fwft_fb_i_reg : label is "yes"; - attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no"; - attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true; - attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes"; - attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no"; - attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true; - attribute KEEP of empty_fwft_i_reg : label is "yes"; - attribute equivalent_register_removal of empty_fwft_i_reg : label is "no"; - attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true; - attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes"; - attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no"; - attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true; - attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes"; - attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no"; - attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true; - attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes"; - attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no"; -begin - empty <= empty_fwft_i; - \out\(1 downto 0) <= curr_fwft_state(1 downto 0); -aempty_fwft_fb_i_i_1: unisim.vcomponents.LUT5 - generic map( - INIT => X"EA88A8AA" - ) - port map ( - I0 => aempty_fwft_fb_i, - I1 => ram_empty_fb_i_reg, - I2 => rd_en, - I3 => curr_fwft_state(0), - I4 => curr_fwft_state(1), - O => aempty_fwft_i0 +\length_counter_1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => empty_fwft_i_reg, + D => \length_counter_1[1]_i_1_n_0\, + Q => length_counter_1_reg(1), + R => aresetn ); -aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE - generic map( - INIT => '1' - ) - port map ( - C => clk, - CE => '1', - D => aempty_fwft_i0, - PRE => AR(0), - Q => aempty_fwft_fb_i +\length_counter_1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => empty_fwft_i_reg, + D => \length_counter_1[2]_i_1_n_0\, + Q => length_counter_1_reg(2), + R => aresetn ); -aempty_fwft_i_reg: unisim.vcomponents.FDPE +\length_counter_1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => empty_fwft_i_reg, + D => \length_counter_1[3]_i_1_n_0\, + Q => length_counter_1_reg(3), + R => aresetn + ); +\length_counter_1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => empty_fwft_i_reg, + D => \length_counter_1[4]_i_1_n_0\, + Q => length_counter_1_reg(4), + R => aresetn + ); +\length_counter_1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => empty_fwft_i_reg, + D => \length_counter_1[5]_i_1_n_0\, + Q => length_counter_1_reg(5), + R => aresetn + ); +\length_counter_1_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => empty_fwft_i_reg, + D => \length_counter_1[6]_i_1_n_0\, + Q => length_counter_1_reg(6), + R => aresetn + ); +\length_counter_1_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => empty_fwft_i_reg, + D => \length_counter_1[7]_i_1_n_0\, + Q => length_counter_1_reg(7), + R => aresetn + ); +m_axi_wlast_INST_0: unisim.vcomponents.LUT3 generic map( - INIT => '1' + INIT => X"80" ) port map ( - C => clk, - CE => '1', - D => aempty_fwft_i0, - PRE => AR(0), - Q => aempty_fwft_i + I0 => m_axi_wlast_INST_0_i_1_n_0, + I1 => m_axi_wlast_INST_0_i_2_n_0, + I2 => m_axi_wlast_INST_0_i_3_n_0, + O => \^m_axi_wlast\ ); -empty_fwft_fb_i_i_1: unisim.vcomponents.LUT4 +m_axi_wlast_INST_0_i_1: unisim.vcomponents.LUT5 generic map( - INIT => X"F320" + INIT => X"FF00FF01" ) port map ( - I0 => rd_en, - I1 => curr_fwft_state(1), - I2 => curr_fwft_state(0), - I3 => empty_fwft_fb_i, - O => empty_fwft_i0 - ); -empty_fwft_fb_i_reg: unisim.vcomponents.FDPE + I0 => length_counter_1_reg(6), + I1 => length_counter_1_reg(7), + I2 => length_counter_1_reg(5), + I3 => first_mi_word, + I4 => length_counter_1_reg(4), + O => m_axi_wlast_INST_0_i_1_n_0 + ); +m_axi_wlast_INST_0_i_2: unisim.vcomponents.LUT5 generic map( - INIT => '1' + INIT => X"00053035" ) port map ( - C => clk, - CE => '1', - D => empty_fwft_i0, - PRE => AR(0), - Q => empty_fwft_fb_i - ); -empty_fwft_fb_o_i_i_1: unisim.vcomponents.LUT4 + I0 => length_counter_1_reg(2), + I1 => dout(2), + I2 => first_mi_word, + I3 => length_counter_1_reg(3), + I4 => dout(3), + O => m_axi_wlast_INST_0_i_2_n_0 + ); +m_axi_wlast_INST_0_i_3: unisim.vcomponents.LUT5 generic map( - INIT => X"F320" + INIT => X"00053035" ) port map ( - I0 => rd_en, - I1 => curr_fwft_state(1), - I2 => curr_fwft_state(0), - I3 => empty_fwft_fb_o_i, - O => empty_fwft_fb_o_i0 + I0 => length_counter_1_reg(0), + I1 => dout(0), + I2 => first_mi_word, + I3 => length_counter_1_reg(1), + I4 => dout(1), + O => m_axi_wlast_INST_0_i_3_n_0 ); -empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_dmem is + port ( + dout_i : out STD_LOGIC_VECTOR ( 4 downto 0 ); + clk : in STD_LOGIC; + EN : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + I55 : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); +end Arty_Z7_20_auto_pc_0_dmem; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_dmem is + signal p_0_out : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_RAM_reg_0_31_0_4_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); + signal NLW_RAM_reg_0_31_0_4_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute METHODOLOGY_DRC_VIOS : string; + attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_31_0_4 : label is ""; +begin +RAM_reg_0_31_0_4: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), + ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), + ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), + ADDRD(4 downto 0) => I55(4 downto 0), + DIA(1 downto 0) => din(1 downto 0), + DIB(1 downto 0) => din(3 downto 2), + DIC(1) => '0', + DIC(0) => din(4), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => p_0_out(1 downto 0), + DOB(1 downto 0) => p_0_out(3 downto 2), + DOC(1) => NLW_RAM_reg_0_31_0_4_DOC_UNCONNECTED(1), + DOC(0) => p_0_out(4), + DOD(1 downto 0) => NLW_RAM_reg_0_31_0_4_DOD_UNCONNECTED(1 downto 0), + WCLK => clk, + WE => EN + ); +\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => '1' + INIT => '0' ) port map ( C => clk, - CE => '1', - D => empty_fwft_fb_o_i0, - PRE => AR(0), - Q => empty_fwft_fb_o_i + CE => \gpregsm1.curr_fwft_state_reg[1]\(0), + D => p_0_out(0), + Q => dout_i(0), + R => '0' ); -empty_fwft_i_reg: unisim.vcomponents.FDPE +\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE generic map( - INIT => '1' + INIT => '0' ) port map ( C => clk, - CE => '1', - D => empty_fwft_i0, - PRE => AR(0), - Q => empty_fwft_i + CE => \gpregsm1.curr_fwft_state_reg[1]\(0), + D => p_0_out(1), + Q => dout_i(1), + R => '0' ); -\gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT4 +\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE generic map( - INIT => X"4555" + INIT => '0' ) port map ( - I0 => ram_empty_fb_i_reg, - I1 => rd_en, - I2 => curr_fwft_state(0), - I3 => curr_fwft_state(1), - O => E(0) + C => clk, + CE => \gpregsm1.curr_fwft_state_reg[1]\(0), + D => p_0_out(2), + Q => dout_i(2), + R => '0' ); -\gpr1.dout_i[0]_i_1\: unisim.vcomponents.LUT6 +\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE generic map( - INIT => X"EFEEEEEE20222222" + INIT => '0' ) port map ( - I0 => p_0_out, - I1 => ram_empty_fb_i_reg, - I2 => rd_en, - I3 => curr_fwft_state(0), - I4 => curr_fwft_state(1), - I5 => dout_i, - O => \gpr1.dout_i_reg[0]\ + C => clk, + CE => \gpregsm1.curr_fwft_state_reg[1]\(0), + D => p_0_out(3), + Q => dout_i(3), + R => '0' ); -\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3 +\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE generic map( - INIT => X"AE" + INIT => '0' ) port map ( - I0 => curr_fwft_state(1), - I1 => curr_fwft_state(0), - I2 => rd_en, - O => next_fwft_state(0) + C => clk, + CE => \gpregsm1.curr_fwft_state_reg[1]\(0), + D => p_0_out(4), + Q => dout_i(4), + R => '0' ); -\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4 +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_dmem_20 is + port ( + dout_i : out STD_LOGIC_VECTOR ( 4 downto 0 ); + clk : in STD_LOGIC; + EN : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + I54 : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_dmem_20 : entity is "dmem"; +end Arty_Z7_20_auto_pc_0_dmem_20; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_dmem_20 is + signal p_0_out : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_RAM_reg_0_31_0_4_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); + signal NLW_RAM_reg_0_31_0_4_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute METHODOLOGY_DRC_VIOS : string; + attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_31_0_4 : label is ""; +begin +RAM_reg_0_31_0_4: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), + ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), + ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), + ADDRD(4 downto 0) => I54(4 downto 0), + DIA(1 downto 0) => din(1 downto 0), + DIB(1 downto 0) => din(3 downto 2), + DIC(1) => '0', + DIC(0) => din(4), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => p_0_out(1 downto 0), + DOB(1 downto 0) => p_0_out(3 downto 2), + DOC(1) => NLW_RAM_reg_0_31_0_4_DOC_UNCONNECTED(1), + DOC(0) => p_0_out(4), + DOD(1 downto 0) => NLW_RAM_reg_0_31_0_4_DOD_UNCONNECTED(1 downto 0), + WCLK => clk, + WE => EN + ); +\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => X"40FF" + INIT => '0' ) port map ( - I0 => rd_en, - I1 => curr_fwft_state(0), - I2 => curr_fwft_state(1), - I3 => ram_empty_fb_i_reg, - O => \gpregsm1.curr_fwft_state[1]_i_1_n_0\ + C => clk, + CE => \gpregsm1.curr_fwft_state_reg[1]\(0), + D => p_0_out(0), + Q => dout_i(0), + R => '0' ); -\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE +\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, - CE => '1', - CLR => AR(0), - D => next_fwft_state(0), - Q => curr_fwft_state(0) + CE => \gpregsm1.curr_fwft_state_reg[1]\(0), + D => p_0_out(1), + Q => dout_i(1), + R => '0' ); -\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE +\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, - CE => '1', - CLR => AR(0), - D => \gpregsm1.curr_fwft_state[1]_i_1_n_0\, - Q => curr_fwft_state(1) + CE => \gpregsm1.curr_fwft_state_reg[1]\(0), + D => p_0_out(2), + Q => dout_i(2), + R => '0' ); -\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE +\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, - CE => '1', - CLR => AR(0), - D => next_fwft_state(0), - Q => user_valid + CE => \gpregsm1.curr_fwft_state_reg[1]\(0), + D => p_0_out(3), + Q => dout_i(3), + R => '0' ); -ram_empty_fb_i_i_5: unisim.vcomponents.LUT3 +\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE generic map( - INIT => X"08" + INIT => '0' ) port map ( - I0 => curr_fwft_state(1), - I1 => curr_fwft_state(0), - I2 => rd_en, - O => ram_empty_i_reg + C => clk, + CE => \gpregsm1.curr_fwft_state_reg[1]\(0), + D => p_0_out(4), + Q => dout_i(4), + R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_auto_pc_0_rd_status_flags_ss is +entity \Arty_Z7_20_auto_pc_0_dmem__parameterized0\ is port ( - \out\ : out STD_LOGIC; - ram_empty_fb_i_reg_0 : in STD_LOGIC; + p_0_out : out STD_LOGIC; + dout_i : out STD_LOGIC; + \goreg_dm.dout_i_reg[0]\ : out STD_LOGIC; clk : in STD_LOGIC; - AR : in STD_LOGIC_VECTOR ( 0 to 0 ) + din : in STD_LOGIC_VECTOR ( 0 to 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gpregsm1.curr_fwft_state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + rd_en : in STD_LOGIC; + dout : in STD_LOGIC_VECTOR ( 0 to 0 ) ); -end Arty_Z7_20_auto_pc_0_rd_status_flags_ss; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_auto_pc_0_dmem__parameterized0\ : entity is "dmem"; +end \Arty_Z7_20_auto_pc_0_dmem__parameterized0\; -architecture STRUCTURE of Arty_Z7_20_auto_pc_0_rd_status_flags_ss is - signal ram_empty_fb_i : STD_LOGIC; - attribute DONT_TOUCH : boolean; - attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true; - signal ram_empty_i : STD_LOGIC; - attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true; - attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true; - attribute KEEP : string; - attribute KEEP of ram_empty_fb_i_reg : label is "yes"; - attribute equivalent_register_removal : string; - attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no"; - attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true; - attribute KEEP of ram_empty_i_reg : label is "yes"; - attribute equivalent_register_removal of ram_empty_i_reg : label is "no"; +architecture STRUCTURE of \Arty_Z7_20_auto_pc_0_dmem__parameterized0\ is + signal \^dout_i\ : STD_LOGIC; + signal NLW_RAM_reg_0_31_0_0_SPO_UNCONNECTED : STD_LOGIC; begin - \out\ <= ram_empty_fb_i; -ram_empty_fb_i_reg: unisim.vcomponents.FDPE - generic map( - INIT => '1' - ) - port map ( - C => clk, - CE => '1', - D => ram_empty_fb_i_reg_0, - PRE => AR(0), - Q => ram_empty_fb_i - ); -ram_empty_i_reg: unisim.vcomponents.FDPE + dout_i <= \^dout_i\; +RAM_reg_0_31_0_0: unisim.vcomponents.RAM32X1D + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => Q(2), + A3 => Q(3), + A4 => Q(4), + D => din(0), + DPO => p_0_out, + DPRA0 => \gc0.count_d1_reg[4]\(0), + DPRA1 => \gc0.count_d1_reg[4]\(1), + DPRA2 => \gc0.count_d1_reg[4]\(2), + DPRA3 => \gc0.count_d1_reg[4]\(3), + DPRA4 => \gc0.count_d1_reg[4]\(4), + SPO => NLW_RAM_reg_0_31_0_0_SPO_UNCONNECTED, + WCLK => clk, + WE => E(0) + ); +\goreg_dm.dout_i[0]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '1' + INIT => X"EFEFFFEF20200020" ) port map ( - C => clk, - CE => '1', - D => ram_empty_fb_i_reg_0, - PRE => AR(0), - Q => ram_empty_i + I0 => \^dout_i\, + I1 => \out\(0), + I2 => \gpregsm1.curr_fwft_state_reg[1]_0\(1), + I3 => \gpregsm1.curr_fwft_state_reg[1]_0\(0), + I4 => rd_en, + I5 => dout(0), + O => \goreg_dm.dout_i_reg[0]\ ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_auto_pc_0_synchronizer_ff is - port ( - \out\ : out STD_LOGIC; - in0 : in STD_LOGIC_VECTOR ( 0 to 0 ); - clk : in STD_LOGIC - ); -end Arty_Z7_20_auto_pc_0_synchronizer_ff; - -architecture STRUCTURE of Arty_Z7_20_auto_pc_0_synchronizer_ff is - signal Q_reg : STD_LOGIC; - attribute async_reg : string; - attribute async_reg of Q_reg : signal is "true"; - attribute msgon : string; - attribute msgon of Q_reg : signal is "true"; - attribute ASYNC_REG_boolean : boolean; - attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; - attribute KEEP : string; - attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; - attribute msgon of \Q_reg_reg[0]\ : label is "true"; -begin - \out\ <= Q_reg; -\Q_reg_reg[0]\: unisim.vcomponents.FDRE +\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => '1', - D => in0(0), - Q => Q_reg, + D => \gpregsm1.curr_fwft_state_reg[1]\, + Q => \^dout_i\, R => '0' ); end STRUCTURE; @@ -691,268 +841,311 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_auto_pc_0_synchronizer_ff_0 is +entity Arty_Z7_20_auto_pc_0_rd_bin_cntr is port ( - \out\ : out STD_LOGIC; - in0 : in STD_LOGIC_VECTOR ( 0 to 0 ); - clk : in STD_LOGIC + Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); + ram_empty_fb_i_reg : out STD_LOGIC; + ram_empty_fb_i_reg_0 : out STD_LOGIC; + \gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + wr_en : in STD_LOGIC; + ram_full_fb_i_reg : in STD_LOGIC; + \out\ : in STD_LOGIC; + \gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC; + \gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + clk : in STD_LOGIC; + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_synchronizer_ff_0 : entity is "synchronizer_ff"; -end Arty_Z7_20_auto_pc_0_synchronizer_ff_0; +end Arty_Z7_20_auto_pc_0_rd_bin_cntr; -architecture STRUCTURE of Arty_Z7_20_auto_pc_0_synchronizer_ff_0 is - signal Q_reg : STD_LOGIC; - attribute async_reg : string; - attribute async_reg of Q_reg : signal is "true"; - attribute msgon : string; - attribute msgon of Q_reg : signal is "true"; - attribute ASYNC_REG_boolean : boolean; - attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; - attribute KEEP : string; - attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; - attribute msgon of \Q_reg_reg[0]\ : label is "true"; +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_rd_bin_cntr is + signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \^gpr1.dout_i_reg[1]\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal plusOp : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal ram_empty_fb_i_i_2_n_0 : STD_LOGIC; + signal ram_empty_fb_i_i_6_n_0 : STD_LOGIC; + signal \^ram_empty_fb_i_reg_0\ : STD_LOGIC; + signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 4 downto 3 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair37"; + attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair37"; + attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair36"; + attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair36"; begin - \out\ <= Q_reg; -\Q_reg_reg[0]\: unisim.vcomponents.FDRE + Q(2 downto 0) <= \^q\(2 downto 0); + \gpr1.dout_i_reg[1]\(4 downto 0) <= \^gpr1.dout_i_reg[1]\(4 downto 0); + ram_empty_fb_i_reg_0 <= \^ram_empty_fb_i_reg_0\; +\gc0.count[0]_i_1\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"1" ) port map ( - C => clk, - CE => '1', - D => in0(0), - Q => Q_reg, - R => '0' + I0 => \^q\(0), + O => plusOp(0) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_auto_pc_0_synchronizer_ff_1 is - port ( - \Q_reg_reg[0]_0\ : out STD_LOGIC; - AS : out STD_LOGIC_VECTOR ( 0 to 0 ); - \out\ : in STD_LOGIC; - clk : in STD_LOGIC; - in0 : in STD_LOGIC_VECTOR ( 0 to 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_synchronizer_ff_1 : entity is "synchronizer_ff"; -end Arty_Z7_20_auto_pc_0_synchronizer_ff_1; - -architecture STRUCTURE of Arty_Z7_20_auto_pc_0_synchronizer_ff_1 is - signal Q_reg : STD_LOGIC; - attribute async_reg : string; - attribute async_reg of Q_reg : signal is "true"; - attribute msgon : string; - attribute msgon of Q_reg : signal is "true"; - attribute ASYNC_REG_boolean : boolean; - attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; - attribute KEEP : string; - attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; - attribute msgon of \Q_reg_reg[0]\ : label is "true"; -begin - \Q_reg_reg[0]_0\ <= Q_reg; -\Q_reg_reg[0]\: unisim.vcomponents.FDRE +\gc0.count[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^q\(0), + I1 => \^q\(1), + O => plusOp(1) + ); +\gc0.count[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \^q\(1), + I1 => \^q\(0), + I2 => \^q\(2), + O => plusOp(2) + ); +\gc0.count[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \^q\(2), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => rd_pntr_plus1(3), + O => plusOp(3) + ); +\gc0.count[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => rd_pntr_plus1(3), + I1 => \^q\(1), + I2 => \^q\(0), + I3 => \^q\(2), + I4 => rd_pntr_plus1(4), + O => plusOp(4) + ); +\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => clk, - CE => '1', - D => \out\, - Q => Q_reg, - R => '0' + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), + D => \^q\(0), + Q => \^gpr1.dout_i_reg[1]\(0) ); -\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2 +\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => in0(0), - I1 => Q_reg, - O => AS(0) + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), + D => \^q\(1), + Q => \^gpr1.dout_i_reg[1]\(1) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_auto_pc_0_synchronizer_ff_2 is - port ( - \Q_reg_reg[0]_0\ : out STD_LOGIC; - AS : out STD_LOGIC_VECTOR ( 0 to 0 ); - \out\ : in STD_LOGIC; - clk : in STD_LOGIC; - in0 : in STD_LOGIC_VECTOR ( 0 to 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_synchronizer_ff_2 : entity is "synchronizer_ff"; -end Arty_Z7_20_auto_pc_0_synchronizer_ff_2; - -architecture STRUCTURE of Arty_Z7_20_auto_pc_0_synchronizer_ff_2 is - signal Q_reg : STD_LOGIC; - attribute async_reg : string; - attribute async_reg of Q_reg : signal is "true"; - attribute msgon : string; - attribute msgon of Q_reg : signal is "true"; - attribute ASYNC_REG_boolean : boolean; - attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; - attribute KEEP : string; - attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; - attribute msgon of \Q_reg_reg[0]\ : label is "true"; -begin - \Q_reg_reg[0]_0\ <= Q_reg; -\Q_reg_reg[0]\: unisim.vcomponents.FDRE +\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => clk, - CE => '1', - D => \out\, - Q => Q_reg, - R => '0' + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), + D => \^q\(2), + Q => \^gpr1.dout_i_reg[1]\(2) ); -\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2 +\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => in0(0), - I1 => Q_reg, - O => AS(0) + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), + D => rd_pntr_plus1(3), + Q => \^gpr1.dout_i_reg[1]\(3) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_auto_pc_0_synchronizer_ff_3 is - port ( - \Q_reg_reg[0]_0\ : in STD_LOGIC; - clk : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_synchronizer_ff_3 : entity is "synchronizer_ff"; -end Arty_Z7_20_auto_pc_0_synchronizer_ff_3; - -architecture STRUCTURE of Arty_Z7_20_auto_pc_0_synchronizer_ff_3 is - signal Q_reg : STD_LOGIC; - attribute async_reg : string; - attribute async_reg of Q_reg : signal is "true"; - attribute msgon : string; - attribute msgon of Q_reg : signal is "true"; - attribute ASYNC_REG_boolean : boolean; - attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; - attribute KEEP : string; - attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; - attribute msgon of \Q_reg_reg[0]\ : label is "true"; -begin -\Q_reg_reg[0]\: unisim.vcomponents.FDRE +\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => clk, - CE => '1', - D => \Q_reg_reg[0]_0\, - Q => Q_reg, - R => '0' + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), + D => rd_pntr_plus1(4), + Q => \^gpr1.dout_i_reg[1]\(4) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_auto_pc_0_synchronizer_ff_4 is - port ( - \Q_reg_reg[0]_0\ : in STD_LOGIC; - clk : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_synchronizer_ff_4 : entity is "synchronizer_ff"; -end Arty_Z7_20_auto_pc_0_synchronizer_ff_4; - -architecture STRUCTURE of Arty_Z7_20_auto_pc_0_synchronizer_ff_4 is - signal Q_reg : STD_LOGIC; - attribute async_reg : string; - attribute async_reg of Q_reg : signal is "true"; - attribute msgon : string; - attribute msgon of Q_reg : signal is "true"; - attribute ASYNC_REG_boolean : boolean; - attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; - attribute KEEP : string; - attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; - attribute msgon of \Q_reg_reg[0]\ : label is "true"; -begin -\Q_reg_reg[0]\: unisim.vcomponents.FDRE +\gc0.count_reg[0]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => E(0), + D => plusOp(0), + PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), + Q => \^q\(0) + ); +\gc0.count_reg[1]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => clk, - CE => '1', - D => \Q_reg_reg[0]_0\, - Q => Q_reg, - R => '0' + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), + D => plusOp(1), + Q => \^q\(1) + ); +\gc0.count_reg[2]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), + D => plusOp(2), + Q => \^q\(2) + ); +\gc0.count_reg[3]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), + D => plusOp(3), + Q => rd_pntr_plus1(3) + ); +\gc0.count_reg[4]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), + D => plusOp(4), + Q => rd_pntr_plus1(4) + ); +ram_empty_fb_i_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFA2F3A2" + ) + port map ( + I0 => ram_empty_fb_i_i_2_n_0, + I1 => wr_en, + I2 => ram_full_fb_i_reg, + I3 => \out\, + I4 => \^ram_empty_fb_i_reg_0\, + O => ram_empty_fb_i_reg + ); +ram_empty_fb_i_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000000000" + ) + port map ( + I0 => rd_pntr_plus1(3), + I1 => \gcc0.gc0.count_d1_reg[4]\(3), + I2 => rd_pntr_plus1(4), + I3 => \gcc0.gc0.count_d1_reg[4]\(4), + I4 => \gpregsm1.curr_fwft_state_reg[0]\, + I5 => \gcc0.gc0.count_d1_reg[2]\, + O => ram_empty_fb_i_i_2_n_0 + ); +ram_empty_fb_i_i_3: unisim.vcomponents.LUT5 + generic map( + INIT => X"BEFFFFBE" + ) + port map ( + I0 => ram_empty_fb_i_i_6_n_0, + I1 => \^gpr1.dout_i_reg[1]\(2), + I2 => \gcc0.gc0.count_d1_reg[4]\(2), + I3 => \^gpr1.dout_i_reg[1]\(1), + I4 => \gcc0.gc0.count_d1_reg[4]\(1), + O => \^ram_empty_fb_i_reg_0\ + ); +ram_empty_fb_i_i_6: unisim.vcomponents.LUT6 + generic map( + INIT => X"6FF6FFFFFFFF6FF6" + ) + port map ( + I0 => \^gpr1.dout_i_reg[1]\(4), + I1 => \gcc0.gc0.count_d1_reg[4]\(4), + I2 => \^gpr1.dout_i_reg[1]\(3), + I3 => \gcc0.gc0.count_d1_reg[4]\(3), + I4 => \gcc0.gc0.count_d1_reg[4]\(0), + I5 => \^gpr1.dout_i_reg[1]\(0), + O => ram_empty_fb_i_i_6_n_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_auto_pc_0_wr_bin_cntr is +entity Arty_Z7_20_auto_pc_0_rd_bin_cntr_25 is port ( - Q : out STD_LOGIC_VECTOR ( 4 downto 0 ); - ram_empty_i_reg : out STD_LOGIC; - ram_empty_i_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 ); - ram_empty_fb_i_reg : in STD_LOGIC; - \gcc0.gc0.count_d1_reg[1]_0\ : in STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); + ram_empty_fb_i_reg : out STD_LOGIC; + ram_empty_fb_i_reg_0 : out STD_LOGIC; + \gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); wr_en : in STD_LOGIC; + ram_full_fb_i_reg : in STD_LOGIC; \out\ : in STD_LOGIC; - \gc0.count_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); - \gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC; + \gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC; + \gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); clk : in STD_LOGIC; - \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) ); -end Arty_Z7_20_auto_pc_0_wr_bin_cntr; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_rd_bin_cntr_25 : entity is "rd_bin_cntr"; +end Arty_Z7_20_auto_pc_0_rd_bin_cntr_25; -architecture STRUCTURE of Arty_Z7_20_auto_pc_0_wr_bin_cntr is - signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal \plusOp__0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_rd_bin_cntr_25 is + signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \^gpr1.dout_i_reg[1]\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal plusOp : STD_LOGIC_VECTOR ( 4 downto 0 ); signal ram_empty_fb_i_i_2_n_0 : STD_LOGIC; - signal ram_empty_fb_i_i_4_n_0 : STD_LOGIC; - signal \^ram_empty_i_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal ram_empty_fb_i_i_6_n_0 : STD_LOGIC; + signal \^ram_empty_fb_i_reg_0\ : STD_LOGIC; + signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 4 downto 3 ); attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \gcc0.gc0.count[1]_i_1\ : label is "soft_lutpair3"; - attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair3"; - attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair2"; - attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair29"; + attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair29"; + attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair28"; + attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair28"; begin - Q(4 downto 0) <= \^q\(4 downto 0); - ram_empty_i_reg_0(4 downto 0) <= \^ram_empty_i_reg_0\(4 downto 0); -\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1 + Q(2 downto 0) <= \^q\(2 downto 0); + \gpr1.dout_i_reg[1]\(4 downto 0) <= \^gpr1.dout_i_reg[1]\(4 downto 0); + ram_empty_fb_i_reg_0 <= \^ram_empty_fb_i_reg_0\; +\gc0.count[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(0), - O => \plusOp__0\(0) + O => plusOp(0) ); -\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2 +\gc0.count[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( - I0 => \^q\(1), - I1 => \^q\(0), - O => \plusOp__0\(1) + I0 => \^q\(0), + I1 => \^q\(1), + O => plusOp(1) ); -\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3 +\gc0.count[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) @@ -960,892 +1153,7539 @@ begin I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), - O => \plusOp__0\(2) + O => plusOp(2) ); -\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4 +\gc0.count[3]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"6AAA" + INIT => X"7F80" ) port map ( - I0 => \^q\(3), - I1 => \^q\(1), - I2 => \^q\(0), - I3 => \^q\(2), - O => \plusOp__0\(3) + I0 => \^q\(2), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => rd_pntr_plus1(3), + O => plusOp(3) ); -\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5 +\gc0.count[4]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"6AAAAAAA" + INIT => X"7FFF8000" ) port map ( - I0 => \^q\(4), - I1 => \^q\(2), + I0 => rd_pntr_plus1(3), + I1 => \^q\(1), I2 => \^q\(0), - I3 => \^q\(1), - I4 => \^q\(3), - O => \plusOp__0\(4) + I3 => \^q\(2), + I4 => rd_pntr_plus1(4), + O => plusOp(4) ); -\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE +\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), - CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), D => \^q\(0), - Q => \^ram_empty_i_reg_0\(0) + Q => \^gpr1.dout_i_reg[1]\(0) ); -\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE +\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), - CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), D => \^q\(1), - Q => \^ram_empty_i_reg_0\(1) + Q => \^gpr1.dout_i_reg[1]\(1) ); -\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE +\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), - CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), D => \^q\(2), - Q => \^ram_empty_i_reg_0\(2) + Q => \^gpr1.dout_i_reg[1]\(2) ); -\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE +\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), - CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), - D => \^q\(3), - Q => \^ram_empty_i_reg_0\(3) + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), + D => rd_pntr_plus1(3), + Q => \^gpr1.dout_i_reg[1]\(3) ); -\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE +\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), - CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), - D => \^q\(4), - Q => \^ram_empty_i_reg_0\(4) + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), + D => rd_pntr_plus1(4), + Q => \^gpr1.dout_i_reg[1]\(4) ); -\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDPE +\gc0.count_reg[0]\: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => clk, CE => E(0), - D => \plusOp__0\(0), - PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => plusOp(0), + PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), Q => \^q\(0) ); -\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDCE +\gc0.count_reg[1]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), - CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), - D => \plusOp__0\(1), + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), + D => plusOp(1), Q => \^q\(1) ); -\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDCE +\gc0.count_reg[2]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), - CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), - D => \plusOp__0\(2), + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), + D => plusOp(2), Q => \^q\(2) ); -\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDCE +\gc0.count_reg[3]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), - CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), - D => \plusOp__0\(3), - Q => \^q\(3) + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), + D => plusOp(3), + Q => rd_pntr_plus1(3) ); -\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDCE +\gc0.count_reg[4]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), - CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), - D => \plusOp__0\(4), - Q => \^q\(4) + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), + D => plusOp(4), + Q => rd_pntr_plus1(4) ); ram_empty_fb_i_i_1: unisim.vcomponents.LUT5 generic map( - INIT => X"EEEE0CEE" + INIT => X"FFA2F3A2" ) port map ( I0 => ram_empty_fb_i_i_2_n_0, - I1 => ram_empty_fb_i_reg, - I2 => \gcc0.gc0.count_d1_reg[1]_0\, - I3 => wr_en, - I4 => \out\, - O => ram_empty_i_reg + I1 => wr_en, + I2 => ram_full_fb_i_reg, + I3 => \out\, + I4 => \^ram_empty_fb_i_reg_0\, + O => ram_empty_fb_i_reg ); ram_empty_fb_i_i_2: unisim.vcomponents.LUT6 generic map( - INIT => X"0000000082000082" + INIT => X"9009000000000000" ) port map ( - I0 => ram_empty_fb_i_i_4_n_0, - I1 => \^ram_empty_i_reg_0\(4), - I2 => \gc0.count_reg[4]\(4), - I3 => \^ram_empty_i_reg_0\(3), - I4 => \gc0.count_reg[4]\(3), - I5 => \gpregsm1.curr_fwft_state_reg[1]\, + I0 => rd_pntr_plus1(3), + I1 => \gcc0.gc0.count_d1_reg[4]\(3), + I2 => rd_pntr_plus1(4), + I3 => \gcc0.gc0.count_d1_reg[4]\(4), + I4 => \gpregsm1.curr_fwft_state_reg[0]\, + I5 => \gcc0.gc0.count_d1_reg[2]\, O => ram_empty_fb_i_i_2_n_0 ); -ram_empty_fb_i_i_4: unisim.vcomponents.LUT6 +ram_empty_fb_i_i_3: unisim.vcomponents.LUT5 generic map( - INIT => X"9009000000009009" + INIT => X"BEFFFFBE" + ) + port map ( + I0 => ram_empty_fb_i_i_6_n_0, + I1 => \^gpr1.dout_i_reg[1]\(2), + I2 => \gcc0.gc0.count_d1_reg[4]\(2), + I3 => \^gpr1.dout_i_reg[1]\(1), + I4 => \gcc0.gc0.count_d1_reg[4]\(1), + O => \^ram_empty_fb_i_reg_0\ + ); +ram_empty_fb_i_i_6: unisim.vcomponents.LUT6 + generic map( + INIT => X"6FF6FFFFFFFF6FF6" ) port map ( - I0 => \^ram_empty_i_reg_0\(0), - I1 => \gc0.count_reg[4]\(0), - I2 => \gc0.count_reg[4]\(2), - I3 => \^ram_empty_i_reg_0\(2), - I4 => \gc0.count_reg[4]\(1), - I5 => \^ram_empty_i_reg_0\(1), - O => ram_empty_fb_i_i_4_n_0 + I0 => \^gpr1.dout_i_reg[1]\(4), + I1 => \gcc0.gc0.count_d1_reg[4]\(4), + I2 => \^gpr1.dout_i_reg[1]\(3), + I3 => \gcc0.gc0.count_d1_reg[4]\(3), + I4 => \gcc0.gc0.count_d1_reg[4]\(0), + I5 => \^gpr1.dout_i_reg[1]\(0), + O => ram_empty_fb_i_i_6_n_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_auto_pc_0_wr_status_flags_ss is +entity Arty_Z7_20_auto_pc_0_rd_bin_cntr_39 is port ( - \out\ : out STD_LOGIC; - full : out STD_LOGIC; - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - ram_full_comb : in STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); + ram_empty_fb_i_reg : out STD_LOGIC; + ram_empty_fb_i_reg_0 : out STD_LOGIC; + \gpr1.dout_i_reg[0]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + wr_en : in STD_LOGIC; + ram_full_fb_i_reg : in STD_LOGIC; + \out\ : in STD_LOGIC; + \gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC; + \gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); clk : in STD_LOGIC; - \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - wr_en : in STD_LOGIC + AR : in STD_LOGIC_VECTOR ( 0 to 0 ) ); -end Arty_Z7_20_auto_pc_0_wr_status_flags_ss; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_rd_bin_cntr_39 : entity is "rd_bin_cntr"; +end Arty_Z7_20_auto_pc_0_rd_bin_cntr_39; -architecture STRUCTURE of Arty_Z7_20_auto_pc_0_wr_status_flags_ss is - signal ram_afull_fb : STD_LOGIC; - attribute DONT_TOUCH : boolean; - attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true; - signal ram_afull_i : STD_LOGIC; - attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true; - signal ram_full_fb_i : STD_LOGIC; - attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true; - signal ram_full_i : STD_LOGIC; - attribute DONT_TOUCH of ram_full_i : signal is std.standard.true; - attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true; - attribute KEEP : string; - attribute KEEP of ram_full_fb_i_reg : label is "yes"; - attribute equivalent_register_removal : string; - attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no"; - attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true; - attribute KEEP of ram_full_i_reg : label is "yes"; - attribute equivalent_register_removal of ram_full_i_reg : label is "no"; +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_rd_bin_cntr_39 is + signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \^gpr1.dout_i_reg[0]\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal plusOp : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal ram_empty_fb_i_i_2_n_0 : STD_LOGIC; + signal ram_empty_fb_i_i_6_n_0 : STD_LOGIC; + signal \^ram_empty_fb_i_reg_0\ : STD_LOGIC; + signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 4 downto 3 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair0"; begin - full <= ram_full_i; - \out\ <= ram_full_fb_i; -\gcc0.gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT2 + Q(2 downto 0) <= \^q\(2 downto 0); + \gpr1.dout_i_reg[0]\(4 downto 0) <= \^gpr1.dout_i_reg[0]\(4 downto 0); + ram_empty_fb_i_reg_0 <= \^ram_empty_fb_i_reg_0\; +\gc0.count[0]_i_1\: unisim.vcomponents.LUT1 generic map( - INIT => X"2" + INIT => X"1" ) port map ( - I0 => wr_en, - I1 => ram_full_fb_i, - O => E(0) + I0 => \^q\(0), + O => plusOp(0) ); -i_0: unisim.vcomponents.LUT1 +\gc0.count[1]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"6" ) port map ( - I0 => '0', - O => ram_afull_i - ); -i_1: unisim.vcomponents.LUT1 + I0 => \^q\(0), + I1 => \^q\(1), + O => plusOp(1) + ); +\gc0.count[2]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"2" + INIT => X"78" ) port map ( - I0 => '0', - O => ram_afull_fb + I0 => \^q\(1), + I1 => \^q\(0), + I2 => \^q\(2), + O => plusOp(2) ); -ram_full_fb_i_reg: unisim.vcomponents.FDCE +\gc0.count[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \^q\(2), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => rd_pntr_plus1(3), + O => plusOp(3) + ); +\gc0.count[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => rd_pntr_plus1(3), + I1 => \^q\(1), + I2 => \^q\(0), + I3 => \^q\(2), + I4 => rd_pntr_plus1(4), + O => plusOp(4) + ); +\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => clk, - CE => '1', - CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0), - D => ram_full_comb, - Q => ram_full_fb_i + CE => E(0), + CLR => AR(0), + D => \^q\(0), + Q => \^gpr1.dout_i_reg[0]\(0) ); -ram_full_i_reg: unisim.vcomponents.FDCE +\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => clk, - CE => '1', - CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0), - D => ram_full_comb, - Q => ram_full_i + CE => E(0), + CLR => AR(0), + D => \^q\(1), + Q => \^gpr1.dout_i_reg[0]\(1) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_auto_pc_0_memory is - port ( - p_0_out : out STD_LOGIC; - dout_i : out STD_LOGIC; - dout : out STD_LOGIC_VECTOR ( 0 to 0 ); - clk : in STD_LOGIC; - din : in STD_LOGIC_VECTOR ( 0 to 0 ); - E : in STD_LOGIC_VECTOR ( 0 to 0 ); - \gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); - \gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); - ram_empty_fb_i_reg : in STD_LOGIC; - \gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); - rd_en : in STD_LOGIC; - \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ) - ); -end Arty_Z7_20_auto_pc_0_memory; - -architecture STRUCTURE of Arty_Z7_20_auto_pc_0_memory is - signal \^dout\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC; -begin - dout(0) <= \^dout\(0); -\gdm.dm_gen.dm\: entity work.Arty_Z7_20_auto_pc_0_dmem - port map ( - E(0) => E(0), - clk => clk, - din(0) => din(0), - dout(0) => \^dout\(0), - dout_i => dout_i, - \gc0.count_d1_reg[4]\(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), - \gcc0.gc0.count_d1_reg[4]\(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0), - \goreg_dm.dout_i_reg[0]\ => \gdm.dm_gen.dm_n_2\, - \gpregsm1.curr_fwft_state_reg[1]\(1 downto 0) => \gpregsm1.curr_fwft_state_reg[1]\(1 downto 0), - \out\(0) => \out\(0), - p_0_out => p_0_out, - ram_empty_fb_i_reg => ram_empty_fb_i_reg, - rd_en => rd_en +\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => AR(0), + D => \^q\(2), + Q => \^gpr1.dout_i_reg[0]\(2) ); -\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE +\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => clk, - CE => '1', - D => \gdm.dm_gen.dm_n_2\, - Q => \^dout\(0), - R => '0' + CE => E(0), + CLR => AR(0), + D => rd_pntr_plus1(3), + Q => \^gpr1.dout_i_reg[0]\(3) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_auto_pc_0_rd_logic is - port ( - \out\ : out STD_LOGIC; - aempty_fwft_i_reg : out STD_LOGIC_VECTOR ( 1 downto 0 ); - empty : out STD_LOGIC; - \gpr1.dout_i_reg[0]\ : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 4 downto 0 ); - ram_full_comb : out STD_LOGIC; - ram_full_i_reg : out STD_LOGIC; - ram_empty_i_reg : out STD_LOGIC; - ram_full_i_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 ); - ram_empty_fb_i_reg : in STD_LOGIC; - clk : in STD_LOGIC; - AR : in STD_LOGIC_VECTOR ( 0 to 0 ); - rd_en : in STD_LOGIC; - p_0_out : in STD_LOGIC; - dout_i : in STD_LOGIC; - ram_full_fb_i_reg : in STD_LOGIC; - \gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); - wr_en : in STD_LOGIC; - \gcc0.gc0.count_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ) - ); -end Arty_Z7_20_auto_pc_0_rd_logic; - -architecture STRUCTURE of Arty_Z7_20_auto_pc_0_rd_logic is - signal \gr1.gr1_int.rfwft_n_3\ : STD_LOGIC; - signal \^out\ : STD_LOGIC; -begin - \out\ <= \^out\; -\gr1.gr1_int.rfwft\: entity work.Arty_Z7_20_auto_pc_0_rd_fwft - port map ( - AR(0) => AR(0), - E(0) => \gr1.gr1_int.rfwft_n_3\, - clk => clk, - dout_i => dout_i, - empty => empty, - \gpr1.dout_i_reg[0]\ => \gpr1.dout_i_reg[0]\, - \out\(1 downto 0) => aempty_fwft_i_reg(1 downto 0), - p_0_out => p_0_out, - ram_empty_fb_i_reg => \^out\, - ram_empty_i_reg => ram_empty_i_reg, - rd_en => rd_en +\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => AR(0), + D => rd_pntr_plus1(4), + Q => \^gpr1.dout_i_reg[0]\(4) ); -\grss.rsts\: entity work.Arty_Z7_20_auto_pc_0_rd_status_flags_ss - port map ( - AR(0) => AR(0), - clk => clk, - \out\ => \^out\, - ram_empty_fb_i_reg_0 => ram_empty_fb_i_reg +\gc0.count_reg[0]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => E(0), + D => plusOp(0), + PRE => AR(0), + Q => \^q\(0) ); -rpntr: entity work.Arty_Z7_20_auto_pc_0_rd_bin_cntr - port map ( - AR(0) => AR(0), - E(0) => \gr1.gr1_int.rfwft_n_3\, - Q(4 downto 0) => Q(4 downto 0), - clk => clk, - \gcc0.gc0.count_d1_reg[4]\(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0), - \gcc0.gc0.count_reg[4]\(4 downto 0) => \gcc0.gc0.count_reg[4]\(4 downto 0), - ram_full_comb => ram_full_comb, - ram_full_fb_i_reg => ram_full_fb_i_reg, - ram_full_i_reg => ram_full_i_reg, - ram_full_i_reg_0(4 downto 0) => ram_full_i_reg_0(4 downto 0), - wr_en => wr_en +\gc0.count_reg[1]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => AR(0), + D => plusOp(1), + Q => \^q\(1) + ); +\gc0.count_reg[2]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => AR(0), + D => plusOp(2), + Q => \^q\(2) + ); +\gc0.count_reg[3]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => AR(0), + D => plusOp(3), + Q => rd_pntr_plus1(3) + ); +\gc0.count_reg[4]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => AR(0), + D => plusOp(4), + Q => rd_pntr_plus1(4) + ); +ram_empty_fb_i_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFA2F3A2" + ) + port map ( + I0 => ram_empty_fb_i_i_2_n_0, + I1 => wr_en, + I2 => ram_full_fb_i_reg, + I3 => \out\, + I4 => \^ram_empty_fb_i_reg_0\, + O => ram_empty_fb_i_reg + ); +ram_empty_fb_i_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000000000" + ) + port map ( + I0 => rd_pntr_plus1(3), + I1 => \gcc0.gc0.count_d1_reg[4]\(3), + I2 => rd_pntr_plus1(4), + I3 => \gcc0.gc0.count_d1_reg[4]\(4), + I4 => \gpregsm1.curr_fwft_state_reg[0]\, + I5 => \gcc0.gc0.count_d1_reg[2]\, + O => ram_empty_fb_i_i_2_n_0 + ); +ram_empty_fb_i_i_3: unisim.vcomponents.LUT5 + generic map( + INIT => X"BEFFFFBE" + ) + port map ( + I0 => ram_empty_fb_i_i_6_n_0, + I1 => \^gpr1.dout_i_reg[0]\(2), + I2 => \gcc0.gc0.count_d1_reg[4]\(2), + I3 => \^gpr1.dout_i_reg[0]\(1), + I4 => \gcc0.gc0.count_d1_reg[4]\(1), + O => \^ram_empty_fb_i_reg_0\ + ); +ram_empty_fb_i_i_6: unisim.vcomponents.LUT6 + generic map( + INIT => X"6FF6FFFFFFFF6FF6" + ) + port map ( + I0 => \^gpr1.dout_i_reg[0]\(4), + I1 => \gcc0.gc0.count_d1_reg[4]\(4), + I2 => \^gpr1.dout_i_reg[0]\(3), + I3 => \gcc0.gc0.count_d1_reg[4]\(3), + I4 => \gcc0.gc0.count_d1_reg[4]\(0), + I5 => \^gpr1.dout_i_reg[0]\(0), + O => ram_empty_fb_i_i_6_n_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_auto_pc_0_reset_blk_ramfifo is +entity Arty_Z7_20_auto_pc_0_rd_fwft is port ( - \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); - \gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + empty : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + ram_empty_fb_i_reg : out STD_LOGIC; + \goreg_dm.dout_i_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + ram_full_fb_i_reg : out STD_LOGIC; clk : in STD_LOGIC; - rst : in STD_LOGIC + \out\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + rd_en : in STD_LOGIC; + ram_empty_fb_i_reg_0 : in STD_LOGIC ); -end Arty_Z7_20_auto_pc_0_reset_blk_ramfifo; +end Arty_Z7_20_auto_pc_0_rd_fwft; -architecture STRUCTURE of Arty_Z7_20_auto_pc_0_reset_blk_ramfifo is - signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC; - signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC; - signal p_6_out : STD_LOGIC; - signal p_7_out : STD_LOGIC; - signal p_8_out : STD_LOGIC; - signal p_9_out : STD_LOGIC; - signal rd_rst_asreg : STD_LOGIC; - signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 ); +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_rd_fwft is + signal aempty_fwft_fb_i : STD_LOGIC; attribute DONT_TOUCH : boolean; - attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true; - signal rst_rd_reg1 : STD_LOGIC; - attribute async_reg : string; - attribute async_reg of rst_rd_reg1 : signal is "true"; - attribute msgon : string; - attribute msgon of rst_rd_reg1 : signal is "true"; - signal rst_rd_reg2 : STD_LOGIC; - attribute async_reg of rst_rd_reg2 : signal is "true"; - attribute msgon of rst_rd_reg2 : signal is "true"; - signal rst_wr_reg1 : STD_LOGIC; - attribute async_reg of rst_wr_reg1 : signal is "true"; - attribute msgon of rst_wr_reg1 : signal is "true"; - signal rst_wr_reg2 : STD_LOGIC; - attribute async_reg of rst_wr_reg2 : signal is "true"; - attribute msgon of rst_wr_reg2 : signal is "true"; - signal wr_rst_asreg : STD_LOGIC; - signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 ); - attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true; - attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true; + attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true; + signal aempty_fwft_i : STD_LOGIC; + attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true; + signal aempty_fwft_i0 : STD_LOGIC; + signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true; + signal empty_fwft_fb_i : STD_LOGIC; + attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true; + signal empty_fwft_fb_o_i : STD_LOGIC; + attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true; + signal empty_fwft_fb_o_i0 : STD_LOGIC; + signal empty_fwft_i : STD_LOGIC; + attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true; + signal empty_fwft_i0 : STD_LOGIC; + signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal user_valid : STD_LOGIC; + attribute DONT_TOUCH of user_valid : signal is std.standard.true; + attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true; attribute KEEP : string; - attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes"; + attribute KEEP of aempty_fwft_fb_i_reg : label is "yes"; attribute equivalent_register_removal : string; - attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no"; - attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true; - attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes"; - attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no"; - attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true; - attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes"; - attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no"; - attribute ASYNC_REG_boolean : boolean; - attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true; - attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes"; - attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true"; - attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true; - attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes"; - attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true"; - attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true; - attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes"; - attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true"; - attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true; - attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes"; - attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true"; - attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true; - attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes"; - attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no"; - attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true; - attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes"; - attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no"; - attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true; - attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes"; - attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no"; + attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no"; + attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true; + attribute KEEP of aempty_fwft_i_reg : label is "yes"; + attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no"; + attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true; + attribute KEEP of empty_fwft_fb_i_reg : label is "yes"; + attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no"; + attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true; + attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes"; + attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no"; + attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true; + attribute KEEP of empty_fwft_i_reg : label is "yes"; + attribute equivalent_register_removal of empty_fwft_i_reg : label is "no"; + attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true; + attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes"; + attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no"; + attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true; + attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes"; + attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no"; + attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true; + attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes"; + attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no"; begin - \gc0.count_reg[1]\(1) <= rd_rst_reg(2); - \gc0.count_reg[1]\(0) <= rd_rst_reg(0); - \out\(1 downto 0) <= wr_rst_reg(1 downto 0); -\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.Arty_Z7_20_auto_pc_0_synchronizer_ff - port map ( - clk => clk, - in0(0) => rd_rst_asreg, - \out\ => p_6_out - ); -\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.Arty_Z7_20_auto_pc_0_synchronizer_ff_0 - port map ( - clk => clk, - in0(0) => wr_rst_asreg, - \out\ => p_7_out - ); -\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.Arty_Z7_20_auto_pc_0_synchronizer_ff_1 - port map ( - AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\, - \Q_reg_reg[0]_0\ => p_8_out, - clk => clk, - in0(0) => rd_rst_asreg, - \out\ => p_6_out - ); -\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.Arty_Z7_20_auto_pc_0_synchronizer_ff_2 - port map ( - AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\, - \Q_reg_reg[0]_0\ => p_9_out, - clk => clk, - in0(0) => wr_rst_asreg, - \out\ => p_7_out - ); -\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.Arty_Z7_20_auto_pc_0_synchronizer_ff_3 - port map ( - \Q_reg_reg[0]_0\ => p_8_out, - clk => clk - ); -\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.Arty_Z7_20_auto_pc_0_synchronizer_ff_4 - port map ( - \Q_reg_reg[0]_0\ => p_9_out, - clk => clk + empty <= empty_fwft_i; +aempty_fwft_fb_i_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FAEF8000" + ) + port map ( + I0 => ram_empty_fb_i_reg_0, + I1 => rd_en, + I2 => curr_fwft_state(0), + I3 => curr_fwft_state(1), + I4 => aempty_fwft_fb_i, + O => aempty_fwft_i0 ); -\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE +aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => clk, CE => '1', - D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\, - PRE => rst_rd_reg2, - Q => rd_rst_asreg + D => aempty_fwft_i0, + PRE => \out\(1), + Q => aempty_fwft_fb_i ); -\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE +aempty_fwft_i_reg: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => clk, CE => '1', - D => '0', - PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\, - Q => rd_rst_reg(0) + D => aempty_fwft_i0, + PRE => \out\(1), + Q => aempty_fwft_i ); -\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE +empty_fwft_fb_i_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"B2A2" + ) + port map ( + I0 => empty_fwft_fb_i, + I1 => curr_fwft_state(1), + I2 => curr_fwft_state(0), + I3 => rd_en, + O => empty_fwft_i0 + ); +empty_fwft_fb_i_reg: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => clk, CE => '1', - D => '0', - PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\, - Q => rd_rst_reg(1) + D => empty_fwft_i0, + PRE => \out\(1), + Q => empty_fwft_fb_i ); -\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE +empty_fwft_fb_o_i_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"B2A2" + ) + port map ( + I0 => empty_fwft_fb_o_i, + I1 => curr_fwft_state(1), + I2 => curr_fwft_state(0), + I3 => rd_en, + O => empty_fwft_fb_o_i0 + ); +empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => clk, CE => '1', - D => '0', - PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\, - Q => rd_rst_reg(2) + D => empty_fwft_fb_o_i0, + PRE => \out\(1), + Q => empty_fwft_fb_o_i ); -\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE +empty_fwft_i_reg: unisim.vcomponents.FDPE generic map( - INIT => '0' + INIT => '1' ) port map ( C => clk, CE => '1', - D => '0', - PRE => rst, - Q => rst_rd_reg1 + D => empty_fwft_i0, + PRE => \out\(1), + Q => empty_fwft_i ); -\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE +\gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"00DF" ) port map ( - C => clk, - CE => '1', - D => rst_rd_reg1, - PRE => rst, - Q => rst_rd_reg2 + I0 => curr_fwft_state(1), + I1 => rd_en, + I2 => curr_fwft_state(0), + I3 => ram_empty_fb_i_reg_0, + O => E(0) ); -\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE +\goreg_dm.dout_i[4]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"4404" ) port map ( - C => clk, - CE => '1', - D => '0', - PRE => rst, - Q => rst_wr_reg1 + I0 => \out\(0), + I1 => curr_fwft_state(1), + I2 => curr_fwft_state(0), + I3 => rd_en, + O => \goreg_dm.dout_i_reg[4]\(0) ); -\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE +\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"AE" ) port map ( - C => clk, - CE => '1', - D => rst_wr_reg1, - PRE => rst, - Q => rst_wr_reg2 + I0 => curr_fwft_state(1), + I1 => curr_fwft_state(0), + I2 => rd_en, + O => next_fwft_state(0) ); -\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE +\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => '1' + INIT => X"20FF" ) port map ( - C => clk, - CE => '1', - D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\, - PRE => rst_wr_reg2, - Q => wr_rst_asreg + I0 => curr_fwft_state(1), + I1 => rd_en, + I2 => curr_fwft_state(0), + I3 => ram_empty_fb_i_reg_0, + O => next_fwft_state(1) ); -\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE +\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE generic map( - INIT => '1' + INIT => '0' ) port map ( C => clk, CE => '1', - D => '0', - PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\, - Q => wr_rst_reg(0) + CLR => \out\(1), + D => next_fwft_state(0), + Q => curr_fwft_state(0) ); -\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE +\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE generic map( - INIT => '1' + INIT => '0' ) port map ( C => clk, CE => '1', - D => '0', - PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\, - Q => wr_rst_reg(1) + CLR => \out\(1), + D => next_fwft_state(1), + Q => curr_fwft_state(1) ); -\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE +\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE generic map( - INIT => '1' + INIT => '0' ) port map ( C => clk, CE => '1', - D => '0', - PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\, - Q => wr_rst_reg(2) + CLR => \out\(1), + D => next_fwft_state(0), + Q => user_valid + ); +ram_empty_fb_i_i_4: unisim.vcomponents.LUT3 + generic map( + INIT => X"DF" + ) + port map ( + I0 => curr_fwft_state(0), + I1 => rd_en, + I2 => curr_fwft_state(1), + O => ram_empty_fb_i_reg + ); +ram_full_fb_i_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF08" + ) + port map ( + I0 => curr_fwft_state(0), + I1 => curr_fwft_state(1), + I2 => rd_en, + I3 => ram_empty_fb_i_reg_0, + O => ram_full_fb_i_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_auto_pc_0_wr_logic is +entity Arty_Z7_20_auto_pc_0_rd_fwft_23 is port ( - \out\ : out STD_LOGIC; - full : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 4 downto 0 ); - ram_empty_i_reg : out STD_LOGIC; - ram_empty_i_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 ); + empty : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); - ram_full_comb : in STD_LOGIC; + ram_empty_fb_i_reg : out STD_LOGIC; + \goreg_dm.dout_i_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + ram_full_fb_i_reg : out STD_LOGIC; clk : in STD_LOGIC; - \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); - ram_empty_fb_i_reg : in STD_LOGIC; - \gcc0.gc0.count_d1_reg[1]\ : in STD_LOGIC; - wr_en : in STD_LOGIC; - \gc0.count_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); - \gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC + \out\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + rd_en : in STD_LOGIC; + ram_empty_fb_i_reg_0 : in STD_LOGIC ); -end Arty_Z7_20_auto_pc_0_wr_logic; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_rd_fwft_23 : entity is "rd_fwft"; +end Arty_Z7_20_auto_pc_0_rd_fwft_23; -architecture STRUCTURE of Arty_Z7_20_auto_pc_0_wr_logic is - signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \^out\ : STD_LOGIC; +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_rd_fwft_23 is + signal aempty_fwft_fb_i : STD_LOGIC; + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true; + signal aempty_fwft_i : STD_LOGIC; + attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true; + signal aempty_fwft_i0 : STD_LOGIC; + signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true; + signal empty_fwft_fb_i : STD_LOGIC; + attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true; + signal empty_fwft_fb_o_i : STD_LOGIC; + attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true; + signal empty_fwft_fb_o_i0 : STD_LOGIC; + signal empty_fwft_i : STD_LOGIC; + attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true; + signal empty_fwft_i0 : STD_LOGIC; + signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal user_valid : STD_LOGIC; + attribute DONT_TOUCH of user_valid : signal is std.standard.true; + attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of aempty_fwft_fb_i_reg : label is "yes"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no"; + attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true; + attribute KEEP of aempty_fwft_i_reg : label is "yes"; + attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no"; + attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true; + attribute KEEP of empty_fwft_fb_i_reg : label is "yes"; + attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no"; + attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true; + attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes"; + attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no"; + attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true; + attribute KEEP of empty_fwft_i_reg : label is "yes"; + attribute equivalent_register_removal of empty_fwft_i_reg : label is "no"; + attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true; + attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes"; + attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no"; + attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true; + attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes"; + attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no"; + attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true; + attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes"; + attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no"; begin - E(0) <= \^e\(0); - \out\ <= \^out\; -\gwss.wsts\: entity work.Arty_Z7_20_auto_pc_0_wr_status_flags_ss - port map ( - E(0) => \^e\(0), - clk => clk, - full => full, - \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), - \out\ => \^out\, - ram_full_comb => ram_full_comb, - wr_en => wr_en + empty <= empty_fwft_i; +aempty_fwft_fb_i_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FAEF8000" + ) + port map ( + I0 => ram_empty_fb_i_reg_0, + I1 => rd_en, + I2 => curr_fwft_state(0), + I3 => curr_fwft_state(1), + I4 => aempty_fwft_fb_i, + O => aempty_fwft_i0 ); -wpntr: entity work.Arty_Z7_20_auto_pc_0_wr_bin_cntr - port map ( - E(0) => \^e\(0), - Q(4 downto 0) => Q(4 downto 0), - clk => clk, - \gc0.count_reg[4]\(4 downto 0) => \gc0.count_reg[4]\(4 downto 0), - \gcc0.gc0.count_d1_reg[1]_0\ => \gcc0.gc0.count_d1_reg[1]\, - \gpregsm1.curr_fwft_state_reg[1]\ => \gpregsm1.curr_fwft_state_reg[1]\, - \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(1), - \out\ => \^out\, - ram_empty_fb_i_reg => ram_empty_fb_i_reg, - ram_empty_i_reg => ram_empty_i_reg, - ram_empty_i_reg_0(4 downto 0) => ram_empty_i_reg_0(4 downto 0), - wr_en => wr_en +aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => aempty_fwft_i0, + PRE => \out\(1), + Q => aempty_fwft_fb_i + ); +aempty_fwft_i_reg: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => aempty_fwft_i0, + PRE => \out\(1), + Q => aempty_fwft_i + ); +empty_fwft_fb_i_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"B2A2" + ) + port map ( + I0 => empty_fwft_fb_i, + I1 => curr_fwft_state(1), + I2 => curr_fwft_state(0), + I3 => rd_en, + O => empty_fwft_i0 + ); +empty_fwft_fb_i_reg: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => empty_fwft_i0, + PRE => \out\(1), + Q => empty_fwft_fb_i + ); +empty_fwft_fb_o_i_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"B2A2" + ) + port map ( + I0 => empty_fwft_fb_o_i, + I1 => curr_fwft_state(1), + I2 => curr_fwft_state(0), + I3 => rd_en, + O => empty_fwft_fb_o_i0 + ); +empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => empty_fwft_fb_o_i0, + PRE => \out\(1), + Q => empty_fwft_fb_o_i + ); +empty_fwft_i_reg: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => empty_fwft_i0, + PRE => \out\(1), + Q => empty_fwft_i + ); +\gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00DF" + ) + port map ( + I0 => curr_fwft_state(1), + I1 => rd_en, + I2 => curr_fwft_state(0), + I3 => ram_empty_fb_i_reg_0, + O => E(0) + ); +\goreg_dm.dout_i[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4404" + ) + port map ( + I0 => \out\(0), + I1 => curr_fwft_state(1), + I2 => curr_fwft_state(0), + I3 => rd_en, + O => \goreg_dm.dout_i_reg[4]\(0) + ); +\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AE" + ) + port map ( + I0 => curr_fwft_state(1), + I1 => curr_fwft_state(0), + I2 => rd_en, + O => next_fwft_state(0) + ); +\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"20FF" + ) + port map ( + I0 => curr_fwft_state(1), + I1 => rd_en, + I2 => curr_fwft_state(0), + I3 => ram_empty_fb_i_reg_0, + O => next_fwft_state(1) + ); +\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + CLR => \out\(1), + D => next_fwft_state(0), + Q => curr_fwft_state(0) + ); +\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + CLR => \out\(1), + D => next_fwft_state(1), + Q => curr_fwft_state(1) + ); +\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + CLR => \out\(1), + D => next_fwft_state(0), + Q => user_valid + ); +ram_empty_fb_i_i_4: unisim.vcomponents.LUT3 + generic map( + INIT => X"DF" + ) + port map ( + I0 => curr_fwft_state(0), + I1 => rd_en, + I2 => curr_fwft_state(1), + O => ram_empty_fb_i_reg + ); +ram_full_fb_i_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF08" + ) + port map ( + I0 => curr_fwft_state(0), + I1 => curr_fwft_state(1), + I2 => rd_en, + I3 => ram_empty_fb_i_reg_0, + O => ram_full_fb_i_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_auto_pc_0_fifo_generator_ramfifo is +entity Arty_Z7_20_auto_pc_0_rd_fwft_37 is port ( + \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); empty : out STD_LOGIC; - full : out STD_LOGIC; - dout : out STD_LOGIC_VECTOR ( 0 to 0 ); - rd_en : in STD_LOGIC; + \gpr1.dout_i_reg[0]\ : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + ram_empty_fb_i_reg : out STD_LOGIC; + ram_full_fb_i_reg : out STD_LOGIC; clk : in STD_LOGIC; - rst : in STD_LOGIC; - din : in STD_LOGIC_VECTOR ( 0 to 0 ); - wr_en : in STD_LOGIC - ); -end Arty_Z7_20_auto_pc_0_fifo_generator_ramfifo; + AR : in STD_LOGIC_VECTOR ( 0 to 0 ); + p_0_out : in STD_LOGIC; + rd_en : in STD_LOGIC; + ram_empty_fb_i_reg_0 : in STD_LOGIC; + dout_i : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_rd_fwft_37 : entity is "rd_fwft"; +end Arty_Z7_20_auto_pc_0_rd_fwft_37; -architecture STRUCTURE of Arty_Z7_20_auto_pc_0_fifo_generator_ramfifo is - signal dout_i : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.rd_n_1\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.rd_n_11\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.rd_n_12\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.wr_n_0\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.wr_n_7\ : STD_LOGIC; - signal \gr1.gr1_int.rfwft/p_0_in\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \gwss.wsts/ram_full_comb\ : STD_LOGIC; - signal p_0_out : STD_LOGIC; - signal p_0_out_0 : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal p_11_out : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal p_12_out : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal p_17_out : STD_LOGIC; - signal p_2_out : STD_LOGIC; - signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal rst_full_ff_i : STD_LOGIC; - signal wr_rst_i : STD_LOGIC_VECTOR ( 1 to 1 ); +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_rd_fwft_37 is + signal aempty_fwft_fb_i : STD_LOGIC; + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true; + signal aempty_fwft_i : STD_LOGIC; + attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true; + signal aempty_fwft_i0 : STD_LOGIC; + signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true; + signal empty_fwft_fb_i : STD_LOGIC; + attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true; + signal empty_fwft_fb_o_i : STD_LOGIC; + attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true; + signal empty_fwft_fb_o_i0 : STD_LOGIC; + signal empty_fwft_i : STD_LOGIC; + attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true; + signal empty_fwft_i0 : STD_LOGIC; + signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal user_valid : STD_LOGIC; + attribute DONT_TOUCH of user_valid : signal is std.standard.true; + attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of aempty_fwft_fb_i_reg : label is "yes"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no"; + attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true; + attribute KEEP of aempty_fwft_i_reg : label is "yes"; + attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no"; + attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true; + attribute KEEP of empty_fwft_fb_i_reg : label is "yes"; + attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no"; + attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true; + attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes"; + attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no"; + attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true; + attribute KEEP of empty_fwft_i_reg : label is "yes"; + attribute equivalent_register_removal of empty_fwft_i_reg : label is "no"; + attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true; + attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes"; + attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no"; + attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true; + attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes"; + attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no"; + attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true; + attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes"; + attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no"; begin -\gntv_or_sync_fifo.gl0.rd\: entity work.Arty_Z7_20_auto_pc_0_rd_logic - port map ( - AR(0) => rd_rst_i(2), - Q(4 downto 0) => rd_pntr_plus1(4 downto 0), - aempty_fwft_i_reg(1) => \gntv_or_sync_fifo.gl0.rd_n_1\, - aempty_fwft_i_reg(0) => \gr1.gr1_int.rfwft/p_0_in\(0), - clk => clk, - dout_i => dout_i, - empty => empty, - \gcc0.gc0.count_d1_reg[4]\(4 downto 0) => p_11_out(4 downto 0), - \gcc0.gc0.count_reg[4]\(4 downto 0) => p_12_out(4 downto 0), - \gpr1.dout_i_reg[0]\ => \gntv_or_sync_fifo.gl0.rd_n_4\, - \out\ => p_2_out, - p_0_out => p_0_out, - ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_7\, - ram_empty_i_reg => \gntv_or_sync_fifo.gl0.rd_n_12\, - ram_full_comb => \gwss.wsts/ram_full_comb\, - ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_0\, - ram_full_i_reg => \gntv_or_sync_fifo.gl0.rd_n_11\, - ram_full_i_reg_0(4 downto 0) => p_0_out_0(4 downto 0), - rd_en => rd_en, - wr_en => wr_en + empty <= empty_fwft_i; + \out\(1 downto 0) <= curr_fwft_state(1 downto 0); +aempty_fwft_fb_i_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FAEF8000" + ) + port map ( + I0 => ram_empty_fb_i_reg_0, + I1 => rd_en, + I2 => curr_fwft_state(0), + I3 => curr_fwft_state(1), + I4 => aempty_fwft_fb_i, + O => aempty_fwft_i0 ); -\gntv_or_sync_fifo.gl0.wr\: entity work.Arty_Z7_20_auto_pc_0_wr_logic - port map ( - E(0) => p_17_out, - Q(4 downto 0) => p_12_out(4 downto 0), - clk => clk, - full => full, - \gc0.count_reg[4]\(4 downto 0) => rd_pntr_plus1(4 downto 0), - \gcc0.gc0.count_d1_reg[1]\ => \gntv_or_sync_fifo.gl0.rd_n_11\, - \gpregsm1.curr_fwft_state_reg[1]\ => \gntv_or_sync_fifo.gl0.rd_n_12\, - \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(1) => wr_rst_i(1), - \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => rst_full_ff_i, - \out\ => \gntv_or_sync_fifo.gl0.wr_n_0\, - ram_empty_fb_i_reg => p_2_out, - ram_empty_i_reg => \gntv_or_sync_fifo.gl0.wr_n_7\, - ram_empty_i_reg_0(4 downto 0) => p_11_out(4 downto 0), - ram_full_comb => \gwss.wsts/ram_full_comb\, - wr_en => wr_en +aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => aempty_fwft_i0, + PRE => AR(0), + Q => aempty_fwft_fb_i ); -\gntv_or_sync_fifo.mem\: entity work.Arty_Z7_20_auto_pc_0_memory - port map ( - E(0) => p_17_out, - clk => clk, - din(0) => din(0), - dout(0) => dout(0), - dout_i => dout_i, - \gc0.count_d1_reg[4]\(4 downto 0) => p_0_out_0(4 downto 0), - \gcc0.gc0.count_d1_reg[4]\(4 downto 0) => p_11_out(4 downto 0), - \gpregsm1.curr_fwft_state_reg[1]\(1) => \gntv_or_sync_fifo.gl0.rd_n_1\, - \gpregsm1.curr_fwft_state_reg[1]\(0) => \gr1.gr1_int.rfwft/p_0_in\(0), - \out\(0) => rd_rst_i(0), - p_0_out => p_0_out, - ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.rd_n_4\, - rd_en => rd_en +aempty_fwft_i_reg: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => aempty_fwft_i0, + PRE => AR(0), + Q => aempty_fwft_i ); -rstblk: entity work.Arty_Z7_20_auto_pc_0_reset_blk_ramfifo - port map ( - clk => clk, - \gc0.count_reg[1]\(1) => rd_rst_i(2), - \gc0.count_reg[1]\(0) => rd_rst_i(0), - \out\(1) => wr_rst_i(1), - \out\(0) => rst_full_ff_i, - rst => rst +empty_fwft_fb_i_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"B2A2" + ) + port map ( + I0 => empty_fwft_fb_i, + I1 => curr_fwft_state(1), + I2 => curr_fwft_state(0), + I3 => rd_en, + O => empty_fwft_i0 ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_auto_pc_0_fifo_generator_top is - port ( - empty : out STD_LOGIC; - full : out STD_LOGIC; - dout : out STD_LOGIC_VECTOR ( 0 to 0 ); - rd_en : in STD_LOGIC; - clk : in STD_LOGIC; - rst : in STD_LOGIC; - din : in STD_LOGIC_VECTOR ( 0 to 0 ); - wr_en : in STD_LOGIC - ); -end Arty_Z7_20_auto_pc_0_fifo_generator_top; - -architecture STRUCTURE of Arty_Z7_20_auto_pc_0_fifo_generator_top is -begin -\grf.rf\: entity work.Arty_Z7_20_auto_pc_0_fifo_generator_ramfifo - port map ( - clk => clk, - din(0) => din(0), - dout(0) => dout(0), - empty => empty, - full => full, - rd_en => rd_en, - rst => rst, - wr_en => wr_en +empty_fwft_fb_i_reg: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => empty_fwft_i0, + PRE => AR(0), + Q => empty_fwft_fb_i ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3_synth is - port ( - empty : out STD_LOGIC; - full : out STD_LOGIC; - dout : out STD_LOGIC_VECTOR ( 0 to 0 ); - rd_en : in STD_LOGIC; - clk : in STD_LOGIC; - rst : in STD_LOGIC; - din : in STD_LOGIC_VECTOR ( 0 to 0 ); - wr_en : in STD_LOGIC - ); -end Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3_synth; - -architecture STRUCTURE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3_synth is -begin -\gconvfifo.rf\: entity work.Arty_Z7_20_auto_pc_0_fifo_generator_top - port map ( - clk => clk, - din(0) => din(0), - dout(0) => dout(0), - empty => empty, - full => full, - rd_en => rd_en, - rst => rst, - wr_en => wr_en +empty_fwft_fb_o_i_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"B2A2" + ) + port map ( + I0 => empty_fwft_fb_o_i, + I1 => curr_fwft_state(1), + I2 => curr_fwft_state(0), + I3 => rd_en, + O => empty_fwft_fb_o_i0 ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 is - port ( - backup : in STD_LOGIC; - backup_marker : in STD_LOGIC; - clk : in STD_LOGIC; - rst : in STD_LOGIC; - srst : in STD_LOGIC; - wr_clk : in STD_LOGIC; - wr_rst : in STD_LOGIC; - rd_clk : in STD_LOGIC; - rd_rst : in STD_LOGIC; - din : in STD_LOGIC_VECTOR ( 0 to 0 ); - wr_en : in STD_LOGIC; - rd_en : in STD_LOGIC; - prog_empty_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 ); - prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 ); - prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 ); - prog_full_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 ); - prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 ); - prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 ); - int_clk : in STD_LOGIC; - injectdbiterr : in STD_LOGIC; - injectsbiterr : in STD_LOGIC; - sleep : in STD_LOGIC; - dout : out STD_LOGIC_VECTOR ( 0 to 0 ); - full : out STD_LOGIC; - almost_full : out STD_LOGIC; - wr_ack : out STD_LOGIC; - overflow : out STD_LOGIC; +empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => empty_fwft_fb_o_i0, + PRE => AR(0), + Q => empty_fwft_fb_o_i + ); +empty_fwft_i_reg: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => empty_fwft_i0, + PRE => AR(0), + Q => empty_fwft_i + ); +\gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00DF" + ) + port map ( + I0 => curr_fwft_state(1), + I1 => rd_en, + I2 => curr_fwft_state(0), + I3 => ram_empty_fb_i_reg_0, + O => E(0) + ); +\gpr1.dout_i[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFAEAA0000A2AA" + ) + port map ( + I0 => p_0_out, + I1 => curr_fwft_state(1), + I2 => rd_en, + I3 => curr_fwft_state(0), + I4 => ram_empty_fb_i_reg_0, + I5 => dout_i, + O => \gpr1.dout_i_reg[0]\ + ); +\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AE" + ) + port map ( + I0 => curr_fwft_state(1), + I1 => curr_fwft_state(0), + I2 => rd_en, + O => next_fwft_state(0) + ); +\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"20FF" + ) + port map ( + I0 => curr_fwft_state(1), + I1 => rd_en, + I2 => curr_fwft_state(0), + I3 => ram_empty_fb_i_reg_0, + O => next_fwft_state(1) + ); +\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + CLR => AR(0), + D => next_fwft_state(0), + Q => curr_fwft_state(0) + ); +\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + CLR => AR(0), + D => next_fwft_state(1), + Q => curr_fwft_state(1) + ); +\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + CLR => AR(0), + D => next_fwft_state(0), + Q => user_valid + ); +ram_empty_fb_i_i_4: unisim.vcomponents.LUT3 + generic map( + INIT => X"DF" + ) + port map ( + I0 => curr_fwft_state(0), + I1 => rd_en, + I2 => curr_fwft_state(1), + O => ram_empty_fb_i_reg + ); +ram_full_fb_i_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF08" + ) + port map ( + I0 => curr_fwft_state(0), + I1 => curr_fwft_state(1), + I2 => rd_en, + I3 => ram_empty_fb_i_reg_0, + O => ram_full_fb_i_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_rd_status_flags_ss is + port ( + \out\ : out STD_LOGIC; + ram_full_fb_i_reg : in STD_LOGIC; + clk : in STD_LOGIC; + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); +end Arty_Z7_20_auto_pc_0_rd_status_flags_ss; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_rd_status_flags_ss is + signal ram_empty_fb_i : STD_LOGIC; + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true; + signal ram_empty_i : STD_LOGIC; + attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true; + attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of ram_empty_fb_i_reg : label is "yes"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no"; + attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true; + attribute KEEP of ram_empty_i_reg : label is "yes"; + attribute equivalent_register_removal of ram_empty_i_reg : label is "no"; +begin + \out\ <= ram_empty_fb_i; +ram_empty_fb_i_reg: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => ram_full_fb_i_reg, + PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), + Q => ram_empty_fb_i + ); +ram_empty_i_reg: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => ram_full_fb_i_reg, + PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), + Q => ram_empty_i + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_rd_status_flags_ss_24 is + port ( + \out\ : out STD_LOGIC; + ram_full_fb_i_reg : in STD_LOGIC; + clk : in STD_LOGIC; + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_rd_status_flags_ss_24 : entity is "rd_status_flags_ss"; +end Arty_Z7_20_auto_pc_0_rd_status_flags_ss_24; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_rd_status_flags_ss_24 is + signal ram_empty_fb_i : STD_LOGIC; + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true; + signal ram_empty_i : STD_LOGIC; + attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true; + attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of ram_empty_fb_i_reg : label is "yes"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no"; + attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true; + attribute KEEP of ram_empty_i_reg : label is "yes"; + attribute equivalent_register_removal of ram_empty_i_reg : label is "no"; +begin + \out\ <= ram_empty_fb_i; +ram_empty_fb_i_reg: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => ram_full_fb_i_reg, + PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), + Q => ram_empty_fb_i + ); +ram_empty_i_reg: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => ram_full_fb_i_reg, + PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), + Q => ram_empty_i + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_rd_status_flags_ss_38 is + port ( + \out\ : out STD_LOGIC; + ram_full_fb_i_reg : in STD_LOGIC; + clk : in STD_LOGIC; + AR : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_rd_status_flags_ss_38 : entity is "rd_status_flags_ss"; +end Arty_Z7_20_auto_pc_0_rd_status_flags_ss_38; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_rd_status_flags_ss_38 is + signal ram_empty_fb_i : STD_LOGIC; + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true; + signal ram_empty_i : STD_LOGIC; + attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true; + attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of ram_empty_fb_i_reg : label is "yes"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no"; + attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true; + attribute KEEP of ram_empty_i_reg : label is "yes"; + attribute equivalent_register_removal of ram_empty_i_reg : label is "no"; +begin + \out\ <= ram_empty_fb_i; +ram_empty_fb_i_reg: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => ram_full_fb_i_reg, + PRE => AR(0), + Q => ram_empty_fb_i + ); +ram_empty_i_reg: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => ram_full_fb_i_reg, + PRE => AR(0), + Q => ram_empty_i + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_synchronizer_ff is + port ( + \out\ : out STD_LOGIC; + in0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + clk : in STD_LOGIC + ); +end Arty_Z7_20_auto_pc_0_synchronizer_ff; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_synchronizer_ff is + signal Q_reg : STD_LOGIC; + attribute async_reg : string; + attribute async_reg of Q_reg : signal is "true"; + attribute msgon : string; + attribute msgon of Q_reg : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; + attribute msgon of \Q_reg_reg[0]\ : label is "true"; +begin + \out\ <= Q_reg; +\Q_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => in0(0), + Q => Q_reg, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_synchronizer_ff_1 is + port ( + \out\ : out STD_LOGIC; + in0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + clk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_synchronizer_ff_1 : entity is "synchronizer_ff"; +end Arty_Z7_20_auto_pc_0_synchronizer_ff_1; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_synchronizer_ff_1 is + signal Q_reg : STD_LOGIC; + attribute async_reg : string; + attribute async_reg of Q_reg : signal is "true"; + attribute msgon : string; + attribute msgon of Q_reg : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; + attribute msgon of \Q_reg_reg[0]\ : label is "true"; +begin + \out\ <= Q_reg; +\Q_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => in0(0), + Q => Q_reg, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_synchronizer_ff_14 is + port ( + \out\ : out STD_LOGIC; + in0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + clk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_synchronizer_ff_14 : entity is "synchronizer_ff"; +end Arty_Z7_20_auto_pc_0_synchronizer_ff_14; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_synchronizer_ff_14 is + signal Q_reg : STD_LOGIC; + attribute async_reg : string; + attribute async_reg of Q_reg : signal is "true"; + attribute msgon : string; + attribute msgon of Q_reg : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; + attribute msgon of \Q_reg_reg[0]\ : label is "true"; +begin + \out\ <= Q_reg; +\Q_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => in0(0), + Q => Q_reg, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_synchronizer_ff_15 is + port ( + \out\ : out STD_LOGIC; + in0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + clk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_synchronizer_ff_15 : entity is "synchronizer_ff"; +end Arty_Z7_20_auto_pc_0_synchronizer_ff_15; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_synchronizer_ff_15 is + signal Q_reg : STD_LOGIC; + attribute async_reg : string; + attribute async_reg of Q_reg : signal is "true"; + attribute msgon : string; + attribute msgon of Q_reg : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; + attribute msgon of \Q_reg_reg[0]\ : label is "true"; +begin + \out\ <= Q_reg; +\Q_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => in0(0), + Q => Q_reg, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_synchronizer_ff_16 is + port ( + \Q_reg_reg[0]_0\ : out STD_LOGIC; + AS : out STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : in STD_LOGIC; + clk : in STD_LOGIC; + in0 : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_synchronizer_ff_16 : entity is "synchronizer_ff"; +end Arty_Z7_20_auto_pc_0_synchronizer_ff_16; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_synchronizer_ff_16 is + signal Q_reg : STD_LOGIC; + attribute async_reg : string; + attribute async_reg of Q_reg : signal is "true"; + attribute msgon : string; + attribute msgon of Q_reg : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; + attribute msgon of \Q_reg_reg[0]\ : label is "true"; +begin + \Q_reg_reg[0]_0\ <= Q_reg; +\Q_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => \out\, + Q => Q_reg, + R => '0' + ); +\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => in0(0), + I1 => Q_reg, + O => AS(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_synchronizer_ff_17 is + port ( + \Q_reg_reg[0]_0\ : out STD_LOGIC; + AS : out STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : in STD_LOGIC; + clk : in STD_LOGIC; + in0 : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_synchronizer_ff_17 : entity is "synchronizer_ff"; +end Arty_Z7_20_auto_pc_0_synchronizer_ff_17; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_synchronizer_ff_17 is + signal Q_reg : STD_LOGIC; + attribute async_reg : string; + attribute async_reg of Q_reg : signal is "true"; + attribute msgon : string; + attribute msgon of Q_reg : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; + attribute msgon of \Q_reg_reg[0]\ : label is "true"; +begin + \Q_reg_reg[0]_0\ <= Q_reg; +\Q_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => \out\, + Q => Q_reg, + R => '0' + ); +\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => in0(0), + I1 => Q_reg, + O => AS(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_synchronizer_ff_18 is + port ( + \Q_reg_reg[0]_0\ : in STD_LOGIC; + clk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_synchronizer_ff_18 : entity is "synchronizer_ff"; +end Arty_Z7_20_auto_pc_0_synchronizer_ff_18; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_synchronizer_ff_18 is + signal Q_reg : STD_LOGIC; + attribute async_reg : string; + attribute async_reg of Q_reg : signal is "true"; + attribute msgon : string; + attribute msgon of Q_reg : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; + attribute msgon of \Q_reg_reg[0]\ : label is "true"; +begin +\Q_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => \Q_reg_reg[0]_0\, + Q => Q_reg, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_synchronizer_ff_19 is + port ( + \Q_reg_reg[0]_0\ : in STD_LOGIC; + clk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_synchronizer_ff_19 : entity is "synchronizer_ff"; +end Arty_Z7_20_auto_pc_0_synchronizer_ff_19; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_synchronizer_ff_19 is + signal Q_reg : STD_LOGIC; + attribute async_reg : string; + attribute async_reg of Q_reg : signal is "true"; + attribute msgon : string; + attribute msgon of Q_reg : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; + attribute msgon of \Q_reg_reg[0]\ : label is "true"; +begin +\Q_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => \Q_reg_reg[0]_0\, + Q => Q_reg, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_synchronizer_ff_2 is + port ( + \Q_reg_reg[0]_0\ : out STD_LOGIC; + AS : out STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : in STD_LOGIC; + clk : in STD_LOGIC; + in0 : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_synchronizer_ff_2 : entity is "synchronizer_ff"; +end Arty_Z7_20_auto_pc_0_synchronizer_ff_2; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_synchronizer_ff_2 is + signal Q_reg : STD_LOGIC; + attribute async_reg : string; + attribute async_reg of Q_reg : signal is "true"; + attribute msgon : string; + attribute msgon of Q_reg : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; + attribute msgon of \Q_reg_reg[0]\ : label is "true"; +begin + \Q_reg_reg[0]_0\ <= Q_reg; +\Q_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => \out\, + Q => Q_reg, + R => '0' + ); +\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => in0(0), + I1 => Q_reg, + O => AS(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_synchronizer_ff_29 is + port ( + \out\ : out STD_LOGIC; + in0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + clk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_synchronizer_ff_29 : entity is "synchronizer_ff"; +end Arty_Z7_20_auto_pc_0_synchronizer_ff_29; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_synchronizer_ff_29 is + signal Q_reg : STD_LOGIC; + attribute async_reg : string; + attribute async_reg of Q_reg : signal is "true"; + attribute msgon : string; + attribute msgon of Q_reg : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; + attribute msgon of \Q_reg_reg[0]\ : label is "true"; +begin + \out\ <= Q_reg; +\Q_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => in0(0), + Q => Q_reg, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_synchronizer_ff_3 is + port ( + \Q_reg_reg[0]_0\ : out STD_LOGIC; + AS : out STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : in STD_LOGIC; + clk : in STD_LOGIC; + in0 : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_synchronizer_ff_3 : entity is "synchronizer_ff"; +end Arty_Z7_20_auto_pc_0_synchronizer_ff_3; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_synchronizer_ff_3 is + signal Q_reg : STD_LOGIC; + attribute async_reg : string; + attribute async_reg of Q_reg : signal is "true"; + attribute msgon : string; + attribute msgon of Q_reg : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; + attribute msgon of \Q_reg_reg[0]\ : label is "true"; +begin + \Q_reg_reg[0]_0\ <= Q_reg; +\Q_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => \out\, + Q => Q_reg, + R => '0' + ); +\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => in0(0), + I1 => Q_reg, + O => AS(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_synchronizer_ff_30 is + port ( + \out\ : out STD_LOGIC; + in0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + clk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_synchronizer_ff_30 : entity is "synchronizer_ff"; +end Arty_Z7_20_auto_pc_0_synchronizer_ff_30; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_synchronizer_ff_30 is + signal Q_reg : STD_LOGIC; + attribute async_reg : string; + attribute async_reg of Q_reg : signal is "true"; + attribute msgon : string; + attribute msgon of Q_reg : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; + attribute msgon of \Q_reg_reg[0]\ : label is "true"; +begin + \out\ <= Q_reg; +\Q_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => in0(0), + Q => Q_reg, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_synchronizer_ff_31 is + port ( + \Q_reg_reg[0]_0\ : out STD_LOGIC; + AS : out STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : in STD_LOGIC; + clk : in STD_LOGIC; + in0 : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_synchronizer_ff_31 : entity is "synchronizer_ff"; +end Arty_Z7_20_auto_pc_0_synchronizer_ff_31; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_synchronizer_ff_31 is + signal Q_reg : STD_LOGIC; + attribute async_reg : string; + attribute async_reg of Q_reg : signal is "true"; + attribute msgon : string; + attribute msgon of Q_reg : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; + attribute msgon of \Q_reg_reg[0]\ : label is "true"; +begin + \Q_reg_reg[0]_0\ <= Q_reg; +\Q_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => \out\, + Q => Q_reg, + R => '0' + ); +\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => in0(0), + I1 => Q_reg, + O => AS(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_synchronizer_ff_32 is + port ( + \Q_reg_reg[0]_0\ : out STD_LOGIC; + AS : out STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : in STD_LOGIC; + clk : in STD_LOGIC; + in0 : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_synchronizer_ff_32 : entity is "synchronizer_ff"; +end Arty_Z7_20_auto_pc_0_synchronizer_ff_32; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_synchronizer_ff_32 is + signal Q_reg : STD_LOGIC; + attribute async_reg : string; + attribute async_reg of Q_reg : signal is "true"; + attribute msgon : string; + attribute msgon of Q_reg : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; + attribute msgon of \Q_reg_reg[0]\ : label is "true"; +begin + \Q_reg_reg[0]_0\ <= Q_reg; +\Q_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => \out\, + Q => Q_reg, + R => '0' + ); +\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => in0(0), + I1 => Q_reg, + O => AS(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_synchronizer_ff_33 is + port ( + \Q_reg_reg[0]_0\ : in STD_LOGIC; + clk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_synchronizer_ff_33 : entity is "synchronizer_ff"; +end Arty_Z7_20_auto_pc_0_synchronizer_ff_33; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_synchronizer_ff_33 is + signal Q_reg : STD_LOGIC; + attribute async_reg : string; + attribute async_reg of Q_reg : signal is "true"; + attribute msgon : string; + attribute msgon of Q_reg : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; + attribute msgon of \Q_reg_reg[0]\ : label is "true"; +begin +\Q_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => \Q_reg_reg[0]_0\, + Q => Q_reg, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_synchronizer_ff_34 is + port ( + \Q_reg_reg[0]_0\ : in STD_LOGIC; + clk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_synchronizer_ff_34 : entity is "synchronizer_ff"; +end Arty_Z7_20_auto_pc_0_synchronizer_ff_34; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_synchronizer_ff_34 is + signal Q_reg : STD_LOGIC; + attribute async_reg : string; + attribute async_reg of Q_reg : signal is "true"; + attribute msgon : string; + attribute msgon of Q_reg : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; + attribute msgon of \Q_reg_reg[0]\ : label is "true"; +begin +\Q_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => \Q_reg_reg[0]_0\, + Q => Q_reg, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_synchronizer_ff_4 is + port ( + \Q_reg_reg[0]_0\ : in STD_LOGIC; + clk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_synchronizer_ff_4 : entity is "synchronizer_ff"; +end Arty_Z7_20_auto_pc_0_synchronizer_ff_4; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_synchronizer_ff_4 is + signal Q_reg : STD_LOGIC; + attribute async_reg : string; + attribute async_reg of Q_reg : signal is "true"; + attribute msgon : string; + attribute msgon of Q_reg : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; + attribute msgon of \Q_reg_reg[0]\ : label is "true"; +begin +\Q_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => \Q_reg_reg[0]_0\, + Q => Q_reg, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_synchronizer_ff_5 is + port ( + \Q_reg_reg[0]_0\ : in STD_LOGIC; + clk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_synchronizer_ff_5 : entity is "synchronizer_ff"; +end Arty_Z7_20_auto_pc_0_synchronizer_ff_5; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_synchronizer_ff_5 is + signal Q_reg : STD_LOGIC; + attribute async_reg : string; + attribute async_reg of Q_reg : signal is "true"; + attribute msgon : string; + attribute msgon of Q_reg : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; + attribute msgon of \Q_reg_reg[0]\ : label is "true"; +begin +\Q_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => \Q_reg_reg[0]_0\, + Q => Q_reg, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_wr_bin_cntr is + port ( + ram_full_comb : out STD_LOGIC; + ram_empty_fb_i_reg : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 4 downto 0 ); + \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC; + \out\ : in STD_LOGIC; + \gc0.count_d1_reg[2]\ : in STD_LOGIC; + \gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + wr_en : in STD_LOGIC; + \gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + clk : in STD_LOGIC; + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); +end Arty_Z7_20_auto_pc_0_wr_bin_cntr; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_wr_bin_cntr is + signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal p_12_out : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \plusOp__0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal ram_full_fb_i_i_2_n_0 : STD_LOGIC; + signal ram_full_fb_i_i_4_n_0 : STD_LOGIC; + signal ram_full_fb_i_i_5_n_0 : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair39"; + attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair38"; + attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair38"; + attribute SOFT_HLUTNM of ram_full_fb_i_i_5 : label is "soft_lutpair39"; +begin + Q(4 downto 0) <= \^q\(4 downto 0); +\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => p_12_out(0), + O => \plusOp__0\(0) + ); +\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => p_12_out(0), + I1 => p_12_out(1), + O => \plusOp__0\(1) + ); +\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => p_12_out(1), + I1 => p_12_out(0), + I2 => p_12_out(2), + O => \plusOp__0\(2) + ); +\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => p_12_out(2), + I1 => p_12_out(0), + I2 => p_12_out(1), + I3 => p_12_out(3), + O => \plusOp__0\(3) + ); +\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => p_12_out(3), + I1 => p_12_out(1), + I2 => p_12_out(0), + I3 => p_12_out(2), + I4 => p_12_out(4), + O => \plusOp__0\(4) + ); +\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => p_12_out(0), + Q => \^q\(0) + ); +\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => p_12_out(1), + Q => \^q\(1) + ); +\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => p_12_out(2), + Q => \^q\(2) + ); +\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => p_12_out(3), + Q => \^q\(3) + ); +\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => p_12_out(4), + Q => \^q\(4) + ); +\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => E(0), + D => \plusOp__0\(0), + PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + Q => p_12_out(0) + ); +\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \plusOp__0\(1), + Q => p_12_out(1) + ); +\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \plusOp__0\(2), + Q => p_12_out(2) + ); +\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \plusOp__0\(3), + Q => p_12_out(3) + ); +\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \plusOp__0\(4), + Q => p_12_out(4) + ); +ram_empty_fb_i_i_5: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^q\(2), + I1 => \gc0.count_reg[2]\(2), + I2 => \^q\(1), + I3 => \gc0.count_reg[2]\(1), + I4 => \gc0.count_reg[2]\(0), + I5 => \^q\(0), + O => ram_empty_fb_i_reg + ); +ram_full_fb_i_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"F8C8" + ) + port map ( + I0 => ram_full_fb_i_i_2_n_0, + I1 => \gpregsm1.curr_fwft_state_reg[0]\, + I2 => \out\, + I3 => \gc0.count_d1_reg[2]\, + O => ram_full_comb + ); +ram_full_fb_i_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000080" + ) + port map ( + I0 => ram_full_fb_i_i_4_n_0, + I1 => ram_full_fb_i_i_5_n_0, + I2 => wr_en, + I3 => \gc0.count_d1_reg[4]\(4), + I4 => p_12_out(4), + O => ram_full_fb_i_i_2_n_0 + ); +ram_full_fb_i_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => p_12_out(2), + I1 => \gc0.count_d1_reg[4]\(2), + I2 => p_12_out(3), + I3 => \gc0.count_d1_reg[4]\(3), + O => ram_full_fb_i_i_4_n_0 + ); +ram_full_fb_i_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => p_12_out(0), + I1 => \gc0.count_d1_reg[4]\(0), + I2 => p_12_out(1), + I3 => \gc0.count_d1_reg[4]\(1), + O => ram_full_fb_i_i_5_n_0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_wr_bin_cntr_22 is + port ( + ram_full_comb : out STD_LOGIC; + ram_empty_fb_i_reg : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 4 downto 0 ); + \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC; + \out\ : in STD_LOGIC; + \gc0.count_d1_reg[2]\ : in STD_LOGIC; + \gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + wr_en : in STD_LOGIC; + \gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + clk : in STD_LOGIC; + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_wr_bin_cntr_22 : entity is "wr_bin_cntr"; +end Arty_Z7_20_auto_pc_0_wr_bin_cntr_22; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_wr_bin_cntr_22 is + signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal p_12_out : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \plusOp__0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal ram_full_fb_i_i_2_n_0 : STD_LOGIC; + signal ram_full_fb_i_i_4_n_0 : STD_LOGIC; + signal ram_full_fb_i_i_5_n_0 : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair31"; + attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair30"; + attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair30"; + attribute SOFT_HLUTNM of ram_full_fb_i_i_5 : label is "soft_lutpair31"; +begin + Q(4 downto 0) <= \^q\(4 downto 0); +\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => p_12_out(0), + O => \plusOp__0\(0) + ); +\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => p_12_out(0), + I1 => p_12_out(1), + O => \plusOp__0\(1) + ); +\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => p_12_out(1), + I1 => p_12_out(0), + I2 => p_12_out(2), + O => \plusOp__0\(2) + ); +\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => p_12_out(2), + I1 => p_12_out(0), + I2 => p_12_out(1), + I3 => p_12_out(3), + O => \plusOp__0\(3) + ); +\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => p_12_out(3), + I1 => p_12_out(1), + I2 => p_12_out(0), + I3 => p_12_out(2), + I4 => p_12_out(4), + O => \plusOp__0\(4) + ); +\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => p_12_out(0), + Q => \^q\(0) + ); +\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => p_12_out(1), + Q => \^q\(1) + ); +\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => p_12_out(2), + Q => \^q\(2) + ); +\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => p_12_out(3), + Q => \^q\(3) + ); +\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => p_12_out(4), + Q => \^q\(4) + ); +\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => E(0), + D => \plusOp__0\(0), + PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + Q => p_12_out(0) + ); +\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \plusOp__0\(1), + Q => p_12_out(1) + ); +\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \plusOp__0\(2), + Q => p_12_out(2) + ); +\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \plusOp__0\(3), + Q => p_12_out(3) + ); +\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \plusOp__0\(4), + Q => p_12_out(4) + ); +ram_empty_fb_i_i_5: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^q\(2), + I1 => \gc0.count_reg[2]\(2), + I2 => \^q\(1), + I3 => \gc0.count_reg[2]\(1), + I4 => \gc0.count_reg[2]\(0), + I5 => \^q\(0), + O => ram_empty_fb_i_reg + ); +ram_full_fb_i_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"F8C8" + ) + port map ( + I0 => ram_full_fb_i_i_2_n_0, + I1 => \gpregsm1.curr_fwft_state_reg[0]\, + I2 => \out\, + I3 => \gc0.count_d1_reg[2]\, + O => ram_full_comb + ); +ram_full_fb_i_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000080" + ) + port map ( + I0 => ram_full_fb_i_i_4_n_0, + I1 => ram_full_fb_i_i_5_n_0, + I2 => wr_en, + I3 => \gc0.count_d1_reg[4]\(4), + I4 => p_12_out(4), + O => ram_full_fb_i_i_2_n_0 + ); +ram_full_fb_i_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => p_12_out(2), + I1 => \gc0.count_d1_reg[4]\(2), + I2 => p_12_out(3), + I3 => \gc0.count_d1_reg[4]\(3), + O => ram_full_fb_i_i_4_n_0 + ); +ram_full_fb_i_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => p_12_out(0), + I1 => \gc0.count_d1_reg[4]\(0), + I2 => p_12_out(1), + I3 => \gc0.count_d1_reg[4]\(1), + O => ram_full_fb_i_i_5_n_0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_wr_bin_cntr_36 is + port ( + ram_full_comb : out STD_LOGIC; + ram_empty_fb_i_reg : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 4 downto 0 ); + \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC; + \out\ : in STD_LOGIC; + \gc0.count_d1_reg[2]\ : in STD_LOGIC; + \gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + wr_en : in STD_LOGIC; + \gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + clk : in STD_LOGIC; + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_wr_bin_cntr_36 : entity is "wr_bin_cntr"; +end Arty_Z7_20_auto_pc_0_wr_bin_cntr_36; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_wr_bin_cntr_36 is + signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal p_12_out : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \plusOp__0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal ram_full_fb_i_i_2_n_0 : STD_LOGIC; + signal ram_full_fb_i_i_4_n_0 : STD_LOGIC; + signal ram_full_fb_i_i_5_n_0 : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of ram_full_fb_i_i_5 : label is "soft_lutpair3"; +begin + Q(4 downto 0) <= \^q\(4 downto 0); +\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => p_12_out(0), + O => \plusOp__0\(0) + ); +\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => p_12_out(0), + I1 => p_12_out(1), + O => \plusOp__0\(1) + ); +\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => p_12_out(1), + I1 => p_12_out(0), + I2 => p_12_out(2), + O => \plusOp__0\(2) + ); +\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => p_12_out(2), + I1 => p_12_out(0), + I2 => p_12_out(1), + I3 => p_12_out(3), + O => \plusOp__0\(3) + ); +\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => p_12_out(3), + I1 => p_12_out(1), + I2 => p_12_out(0), + I3 => p_12_out(2), + I4 => p_12_out(4), + O => \plusOp__0\(4) + ); +\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => p_12_out(0), + Q => \^q\(0) + ); +\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => p_12_out(1), + Q => \^q\(1) + ); +\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => p_12_out(2), + Q => \^q\(2) + ); +\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => p_12_out(3), + Q => \^q\(3) + ); +\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => p_12_out(4), + Q => \^q\(4) + ); +\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => E(0), + D => \plusOp__0\(0), + PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + Q => p_12_out(0) + ); +\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \plusOp__0\(1), + Q => p_12_out(1) + ); +\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \plusOp__0\(2), + Q => p_12_out(2) + ); +\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \plusOp__0\(3), + Q => p_12_out(3) + ); +\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \plusOp__0\(4), + Q => p_12_out(4) + ); +ram_empty_fb_i_i_5: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^q\(2), + I1 => \gc0.count_reg[2]\(2), + I2 => \^q\(1), + I3 => \gc0.count_reg[2]\(1), + I4 => \gc0.count_reg[2]\(0), + I5 => \^q\(0), + O => ram_empty_fb_i_reg + ); +ram_full_fb_i_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"F8C8" + ) + port map ( + I0 => ram_full_fb_i_i_2_n_0, + I1 => \gpregsm1.curr_fwft_state_reg[0]\, + I2 => \out\, + I3 => \gc0.count_d1_reg[2]\, + O => ram_full_comb + ); +ram_full_fb_i_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000080" + ) + port map ( + I0 => ram_full_fb_i_i_4_n_0, + I1 => ram_full_fb_i_i_5_n_0, + I2 => wr_en, + I3 => \gc0.count_d1_reg[4]\(4), + I4 => p_12_out(4), + O => ram_full_fb_i_i_2_n_0 + ); +ram_full_fb_i_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => p_12_out(2), + I1 => \gc0.count_d1_reg[4]\(2), + I2 => p_12_out(3), + I3 => \gc0.count_d1_reg[4]\(3), + O => ram_full_fb_i_i_4_n_0 + ); +ram_full_fb_i_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => p_12_out(0), + I1 => \gc0.count_d1_reg[4]\(0), + I2 => p_12_out(1), + I3 => \gc0.count_d1_reg[4]\(1), + O => ram_full_fb_i_i_5_n_0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_wr_status_flags_ss is + port ( + \out\ : out STD_LOGIC; + full : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + ram_full_comb : in STD_LOGIC; + clk : in STD_LOGIC; + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + wr_en : in STD_LOGIC + ); +end Arty_Z7_20_auto_pc_0_wr_status_flags_ss; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_wr_status_flags_ss is + signal ram_afull_fb : STD_LOGIC; + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true; + signal ram_afull_i : STD_LOGIC; + attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true; + signal ram_full_fb_i : STD_LOGIC; + attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true; + signal ram_full_i : STD_LOGIC; + attribute DONT_TOUCH of ram_full_i : signal is std.standard.true; + attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of ram_full_fb_i_reg : label is "yes"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no"; + attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true; + attribute KEEP of ram_full_i_reg : label is "yes"; + attribute equivalent_register_removal of ram_full_i_reg : label is "no"; +begin + full <= ram_full_i; + \out\ <= ram_full_fb_i; +\gcc0.gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => wr_en, + I1 => ram_full_fb_i, + O => E(0) + ); +i_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => ram_afull_i + ); +i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => ram_afull_fb + ); +ram_full_fb_i_reg: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0), + D => ram_full_comb, + Q => ram_full_fb_i + ); +ram_full_i_reg: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0), + D => ram_full_comb, + Q => ram_full_i + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_wr_status_flags_ss_21 is + port ( + \out\ : out STD_LOGIC; + full : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + ram_full_comb : in STD_LOGIC; + clk : in STD_LOGIC; + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + wr_en : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_wr_status_flags_ss_21 : entity is "wr_status_flags_ss"; +end Arty_Z7_20_auto_pc_0_wr_status_flags_ss_21; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_wr_status_flags_ss_21 is + signal ram_afull_fb : STD_LOGIC; + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true; + signal ram_afull_i : STD_LOGIC; + attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true; + signal ram_full_fb_i : STD_LOGIC; + attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true; + signal ram_full_i : STD_LOGIC; + attribute DONT_TOUCH of ram_full_i : signal is std.standard.true; + attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of ram_full_fb_i_reg : label is "yes"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no"; + attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true; + attribute KEEP of ram_full_i_reg : label is "yes"; + attribute equivalent_register_removal of ram_full_i_reg : label is "no"; +begin + full <= ram_full_i; + \out\ <= ram_full_fb_i; +\gcc0.gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => wr_en, + I1 => ram_full_fb_i, + O => E(0) + ); +i_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => ram_afull_i + ); +i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => ram_afull_fb + ); +ram_full_fb_i_reg: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0), + D => ram_full_comb, + Q => ram_full_fb_i + ); +ram_full_i_reg: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0), + D => ram_full_comb, + Q => ram_full_i + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_wr_status_flags_ss_35 is + port ( + \out\ : out STD_LOGIC; + full : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + ram_full_comb : in STD_LOGIC; + clk : in STD_LOGIC; + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + wr_en : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_wr_status_flags_ss_35 : entity is "wr_status_flags_ss"; +end Arty_Z7_20_auto_pc_0_wr_status_flags_ss_35; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_wr_status_flags_ss_35 is + signal ram_afull_fb : STD_LOGIC; + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true; + signal ram_afull_i : STD_LOGIC; + attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true; + signal ram_full_fb_i : STD_LOGIC; + attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true; + signal ram_full_i : STD_LOGIC; + attribute DONT_TOUCH of ram_full_i : signal is std.standard.true; + attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of ram_full_fb_i_reg : label is "yes"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no"; + attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true; + attribute KEEP of ram_full_i_reg : label is "yes"; + attribute equivalent_register_removal of ram_full_i_reg : label is "no"; +begin + full <= ram_full_i; + \out\ <= ram_full_fb_i; +\gcc0.gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => wr_en, + I1 => ram_full_fb_i, + O => E(0) + ); +i_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => ram_afull_i + ); +i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => ram_afull_fb + ); +ram_full_fb_i_reg: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0), + D => ram_full_comb, + Q => ram_full_fb_i + ); +ram_full_i_reg: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0), + D => ram_full_comb, + Q => ram_full_i + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_memory is + port ( + dout : out STD_LOGIC_VECTOR ( 4 downto 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + clk : in STD_LOGIC; + EN : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + I55 : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); +end Arty_Z7_20_auto_pc_0_memory; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_memory is + signal dout_i : STD_LOGIC_VECTOR ( 4 downto 0 ); +begin +\gdm.dm_gen.dm\: entity work.Arty_Z7_20_auto_pc_0_dmem + port map ( + EN => EN, + I55(4 downto 0) => I55(4 downto 0), + clk => clk, + din(4 downto 0) => din(4 downto 0), + dout_i(4 downto 0) => dout_i(4 downto 0), + \gc0.count_d1_reg[4]\(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), + \gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0) + ); +\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + D => dout_i(0), + Q => dout(0), + R => '0' + ); +\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + D => dout_i(1), + Q => dout(1), + R => '0' + ); +\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + D => dout_i(2), + Q => dout(2), + R => '0' + ); +\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + D => dout_i(3), + Q => dout(3), + R => '0' + ); +\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + D => dout_i(4), + Q => dout(4), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_memory_12 is + port ( + dout : out STD_LOGIC_VECTOR ( 4 downto 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + clk : in STD_LOGIC; + EN : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + I54 : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_memory_12 : entity is "memory"; +end Arty_Z7_20_auto_pc_0_memory_12; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_memory_12 is + signal dout_i : STD_LOGIC_VECTOR ( 4 downto 0 ); +begin +\gdm.dm_gen.dm\: entity work.Arty_Z7_20_auto_pc_0_dmem_20 + port map ( + EN => EN, + I54(4 downto 0) => I54(4 downto 0), + clk => clk, + din(4 downto 0) => din(4 downto 0), + dout_i(4 downto 0) => dout_i(4 downto 0), + \gc0.count_d1_reg[4]\(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), + \gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0) + ); +\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + D => dout_i(0), + Q => dout(0), + R => '0' + ); +\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + D => dout_i(1), + Q => dout(1), + R => '0' + ); +\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + D => dout_i(2), + Q => dout(2), + R => '0' + ); +\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + D => dout_i(3), + Q => dout(3), + R => '0' + ); +\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => E(0), + D => dout_i(4), + Q => dout(4), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_auto_pc_0_memory__parameterized0\ is + port ( + p_0_out : out STD_LOGIC; + dout_i : out STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 0 to 0 ); + clk : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 0 to 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gpregsm1.curr_fwft_state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + rd_en : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_auto_pc_0_memory__parameterized0\ : entity is "memory"; +end \Arty_Z7_20_auto_pc_0_memory__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_auto_pc_0_memory__parameterized0\ is + signal \^dout\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC; +begin + dout(0) <= \^dout\(0); +\gdm.dm_gen.dm\: entity work.\Arty_Z7_20_auto_pc_0_dmem__parameterized0\ + port map ( + E(0) => E(0), + Q(4 downto 0) => Q(4 downto 0), + clk => clk, + din(0) => din(0), + dout(0) => \^dout\(0), + dout_i => dout_i, + \gc0.count_d1_reg[4]\(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), + \goreg_dm.dout_i_reg[0]\ => \gdm.dm_gen.dm_n_2\, + \gpregsm1.curr_fwft_state_reg[1]\ => \gpregsm1.curr_fwft_state_reg[1]\, + \gpregsm1.curr_fwft_state_reg[1]_0\(1 downto 0) => \gpregsm1.curr_fwft_state_reg[1]_0\(1 downto 0), + \out\(0) => \out\(0), + p_0_out => p_0_out, + rd_en => rd_en + ); +\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => \gdm.dm_gen.dm_n_2\, + Q => \^dout\(0), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_rd_logic is + port ( + empty : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); + ram_empty_fb_i_reg : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \goreg_dm.dout_i_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + ram_full_fb_i_reg : out STD_LOGIC; + clk : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + rd_en : in STD_LOGIC; + wr_en : in STD_LOGIC; + ram_full_fb_i_reg_0 : in STD_LOGIC; + \gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC + ); +end Arty_Z7_20_auto_pc_0_rd_logic; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_rd_logic is + signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \gr1.gr1_int.rfwft_n_2\ : STD_LOGIC; + signal p_2_out : STD_LOGIC; + signal rpntr_n_3 : STD_LOGIC; +begin + E(0) <= \^e\(0); +\gr1.gr1_int.rfwft\: entity work.Arty_Z7_20_auto_pc_0_rd_fwft + port map ( + E(0) => \^e\(0), + clk => clk, + empty => empty, + \goreg_dm.dout_i_reg[4]\(0) => \goreg_dm.dout_i_reg[4]\(0), + \out\(1 downto 0) => \out\(1 downto 0), + ram_empty_fb_i_reg => \gr1.gr1_int.rfwft_n_2\, + ram_empty_fb_i_reg_0 => p_2_out, + ram_full_fb_i_reg => ram_full_fb_i_reg, + rd_en => rd_en + ); +\grss.rsts\: entity work.Arty_Z7_20_auto_pc_0_rd_status_flags_ss + port map ( + clk => clk, + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1), + \out\ => p_2_out, + ram_full_fb_i_reg => rpntr_n_3 + ); +rpntr: entity work.Arty_Z7_20_auto_pc_0_rd_bin_cntr + port map ( + E(0) => \^e\(0), + Q(2 downto 0) => Q(2 downto 0), + clk => clk, + \gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\, + \gcc0.gc0.count_d1_reg[4]\(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0), + \gpr1.dout_i_reg[1]\(4 downto 0) => \gpr1.dout_i_reg[1]\(4 downto 0), + \gpregsm1.curr_fwft_state_reg[0]\ => \gr1.gr1_int.rfwft_n_2\, + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1), + \out\ => p_2_out, + ram_empty_fb_i_reg => rpntr_n_3, + ram_empty_fb_i_reg_0 => ram_empty_fb_i_reg, + ram_full_fb_i_reg => ram_full_fb_i_reg_0, + wr_en => wr_en + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_rd_logic_10 is + port ( + empty : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); + ram_empty_fb_i_reg : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \goreg_dm.dout_i_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + ram_full_fb_i_reg : out STD_LOGIC; + clk : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + rd_en : in STD_LOGIC; + wr_en : in STD_LOGIC; + ram_full_fb_i_reg_0 : in STD_LOGIC; + \gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_rd_logic_10 : entity is "rd_logic"; +end Arty_Z7_20_auto_pc_0_rd_logic_10; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_rd_logic_10 is + signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \gr1.gr1_int.rfwft_n_2\ : STD_LOGIC; + signal p_2_out : STD_LOGIC; + signal rpntr_n_3 : STD_LOGIC; +begin + E(0) <= \^e\(0); +\gr1.gr1_int.rfwft\: entity work.Arty_Z7_20_auto_pc_0_rd_fwft_23 + port map ( + E(0) => \^e\(0), + clk => clk, + empty => empty, + \goreg_dm.dout_i_reg[4]\(0) => \goreg_dm.dout_i_reg[4]\(0), + \out\(1 downto 0) => \out\(1 downto 0), + ram_empty_fb_i_reg => \gr1.gr1_int.rfwft_n_2\, + ram_empty_fb_i_reg_0 => p_2_out, + ram_full_fb_i_reg => ram_full_fb_i_reg, + rd_en => rd_en + ); +\grss.rsts\: entity work.Arty_Z7_20_auto_pc_0_rd_status_flags_ss_24 + port map ( + clk => clk, + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1), + \out\ => p_2_out, + ram_full_fb_i_reg => rpntr_n_3 + ); +rpntr: entity work.Arty_Z7_20_auto_pc_0_rd_bin_cntr_25 + port map ( + E(0) => \^e\(0), + Q(2 downto 0) => Q(2 downto 0), + clk => clk, + \gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\, + \gcc0.gc0.count_d1_reg[4]\(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0), + \gpr1.dout_i_reg[1]\(4 downto 0) => \gpr1.dout_i_reg[1]\(4 downto 0), + \gpregsm1.curr_fwft_state_reg[0]\ => \gr1.gr1_int.rfwft_n_2\, + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1), + \out\ => p_2_out, + ram_empty_fb_i_reg => rpntr_n_3, + ram_empty_fb_i_reg_0 => ram_empty_fb_i_reg, + ram_full_fb_i_reg => ram_full_fb_i_reg_0, + wr_en => wr_en + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_rd_logic_26 is + port ( + \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + empty : out STD_LOGIC; + \gpr1.dout_i_reg[0]\ : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); + ram_empty_fb_i_reg : out STD_LOGIC; + \gpr1.dout_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + ram_full_fb_i_reg : out STD_LOGIC; + clk : in STD_LOGIC; + AR : in STD_LOGIC_VECTOR ( 0 to 0 ); + p_0_out : in STD_LOGIC; + rd_en : in STD_LOGIC; + dout_i : in STD_LOGIC; + wr_en : in STD_LOGIC; + ram_full_fb_i_reg_0 : in STD_LOGIC; + \gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_rd_logic_26 : entity is "rd_logic"; +end Arty_Z7_20_auto_pc_0_rd_logic_26; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_rd_logic_26 is + signal \gntv_or_sync_fifo.mem/ram_rd_en_i\ : STD_LOGIC; + signal \gr1.gr1_int.rfwft_n_5\ : STD_LOGIC; + signal p_2_out : STD_LOGIC; + signal rpntr_n_3 : STD_LOGIC; +begin +\gr1.gr1_int.rfwft\: entity work.Arty_Z7_20_auto_pc_0_rd_fwft_37 + port map ( + AR(0) => AR(0), + E(0) => \gntv_or_sync_fifo.mem/ram_rd_en_i\, + clk => clk, + dout_i => dout_i, + empty => empty, + \gpr1.dout_i_reg[0]\ => \gpr1.dout_i_reg[0]\, + \out\(1 downto 0) => \out\(1 downto 0), + p_0_out => p_0_out, + ram_empty_fb_i_reg => \gr1.gr1_int.rfwft_n_5\, + ram_empty_fb_i_reg_0 => p_2_out, + ram_full_fb_i_reg => ram_full_fb_i_reg, + rd_en => rd_en + ); +\grss.rsts\: entity work.Arty_Z7_20_auto_pc_0_rd_status_flags_ss_38 + port map ( + AR(0) => AR(0), + clk => clk, + \out\ => p_2_out, + ram_full_fb_i_reg => rpntr_n_3 + ); +rpntr: entity work.Arty_Z7_20_auto_pc_0_rd_bin_cntr_39 + port map ( + AR(0) => AR(0), + E(0) => \gntv_or_sync_fifo.mem/ram_rd_en_i\, + Q(2 downto 0) => Q(2 downto 0), + clk => clk, + \gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\, + \gcc0.gc0.count_d1_reg[4]\(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0), + \gpr1.dout_i_reg[0]\(4 downto 0) => \gpr1.dout_i_reg[0]_0\(4 downto 0), + \gpregsm1.curr_fwft_state_reg[0]\ => \gr1.gr1_int.rfwft_n_5\, + \out\ => p_2_out, + ram_empty_fb_i_reg => rpntr_n_3, + ram_empty_fb_i_reg_0 => ram_empty_fb_i_reg, + ram_full_fb_i_reg => ram_full_fb_i_reg_0, + wr_en => wr_en + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_reset_blk_ramfifo is + port ( + \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + clk : in STD_LOGIC; + rst : in STD_LOGIC + ); +end Arty_Z7_20_auto_pc_0_reset_blk_ramfifo; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_reset_blk_ramfifo is + signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC; + signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC; + signal p_6_out : STD_LOGIC; + signal p_7_out : STD_LOGIC; + signal p_8_out : STD_LOGIC; + signal p_9_out : STD_LOGIC; + signal rd_rst_asreg : STD_LOGIC; + signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true; + signal rst_rd_reg1 : STD_LOGIC; + attribute async_reg : string; + attribute async_reg of rst_rd_reg1 : signal is "true"; + attribute msgon : string; + attribute msgon of rst_rd_reg1 : signal is "true"; + signal rst_rd_reg2 : STD_LOGIC; + attribute async_reg of rst_rd_reg2 : signal is "true"; + attribute msgon of rst_rd_reg2 : signal is "true"; + signal rst_wr_reg1 : STD_LOGIC; + attribute async_reg of rst_wr_reg1 : signal is "true"; + attribute msgon of rst_wr_reg1 : signal is "true"; + signal rst_wr_reg2 : STD_LOGIC; + attribute async_reg of rst_wr_reg2 : signal is "true"; + attribute msgon of rst_wr_reg2 : signal is "true"; + signal wr_rst_asreg : STD_LOGIC; + signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true; + attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no"; + attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes"; + attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no"; + attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes"; + attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes"; + attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true"; + attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes"; + attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true"; + attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes"; + attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true"; + attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes"; + attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true"; + attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes"; + attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no"; + attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes"; + attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no"; + attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes"; + attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no"; +begin + \gc0.count_reg[1]\(1) <= rd_rst_reg(2); + \gc0.count_reg[1]\(0) <= rd_rst_reg(0); + \out\(1 downto 0) <= wr_rst_reg(1 downto 0); +\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.Arty_Z7_20_auto_pc_0_synchronizer_ff + port map ( + clk => clk, + in0(0) => rd_rst_asreg, + \out\ => p_6_out + ); +\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.Arty_Z7_20_auto_pc_0_synchronizer_ff_1 + port map ( + clk => clk, + in0(0) => wr_rst_asreg, + \out\ => p_7_out + ); +\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.Arty_Z7_20_auto_pc_0_synchronizer_ff_2 + port map ( + AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\, + \Q_reg_reg[0]_0\ => p_8_out, + clk => clk, + in0(0) => rd_rst_asreg, + \out\ => p_6_out + ); +\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.Arty_Z7_20_auto_pc_0_synchronizer_ff_3 + port map ( + AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\, + \Q_reg_reg[0]_0\ => p_9_out, + clk => clk, + in0(0) => wr_rst_asreg, + \out\ => p_7_out + ); +\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.Arty_Z7_20_auto_pc_0_synchronizer_ff_4 + port map ( + \Q_reg_reg[0]_0\ => p_8_out, + clk => clk + ); +\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.Arty_Z7_20_auto_pc_0_synchronizer_ff_5 + port map ( + \Q_reg_reg[0]_0\ => p_9_out, + clk => clk + ); +\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\, + PRE => rst_rd_reg2, + Q => rd_rst_asreg + ); +\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => '0', + PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\, + Q => rd_rst_reg(0) + ); +\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => '0', + PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\, + Q => rd_rst_reg(1) + ); +\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => '0', + PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\, + Q => rd_rst_reg(2) + ); +\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => '0', + PRE => rst, + Q => rst_rd_reg1 + ); +\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => rst_rd_reg1, + PRE => rst, + Q => rst_rd_reg2 + ); +\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => '0', + PRE => rst, + Q => rst_wr_reg1 + ); +\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => rst_wr_reg1, + PRE => rst, + Q => rst_wr_reg2 + ); +\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\, + PRE => rst_wr_reg2, + Q => wr_rst_asreg + ); +\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => '0', + PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\, + Q => wr_rst_reg(0) + ); +\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => '0', + PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\, + Q => wr_rst_reg(1) + ); +\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => '0', + PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\, + Q => wr_rst_reg(2) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_reset_blk_ramfifo_13 is + port ( + \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + clk : in STD_LOGIC; + rst : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_reset_blk_ramfifo_13 : entity is "reset_blk_ramfifo"; +end Arty_Z7_20_auto_pc_0_reset_blk_ramfifo_13; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_reset_blk_ramfifo_13 is + signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC; + signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC; + signal p_6_out : STD_LOGIC; + signal p_7_out : STD_LOGIC; + signal p_8_out : STD_LOGIC; + signal p_9_out : STD_LOGIC; + signal rd_rst_asreg : STD_LOGIC; + signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true; + signal rst_rd_reg1 : STD_LOGIC; + attribute async_reg : string; + attribute async_reg of rst_rd_reg1 : signal is "true"; + attribute msgon : string; + attribute msgon of rst_rd_reg1 : signal is "true"; + signal rst_rd_reg2 : STD_LOGIC; + attribute async_reg of rst_rd_reg2 : signal is "true"; + attribute msgon of rst_rd_reg2 : signal is "true"; + signal rst_wr_reg1 : STD_LOGIC; + attribute async_reg of rst_wr_reg1 : signal is "true"; + attribute msgon of rst_wr_reg1 : signal is "true"; + signal rst_wr_reg2 : STD_LOGIC; + attribute async_reg of rst_wr_reg2 : signal is "true"; + attribute msgon of rst_wr_reg2 : signal is "true"; + signal wr_rst_asreg : STD_LOGIC; + signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true; + attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no"; + attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes"; + attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no"; + attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes"; + attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes"; + attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true"; + attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes"; + attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true"; + attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes"; + attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true"; + attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes"; + attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true"; + attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes"; + attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no"; + attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes"; + attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no"; + attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes"; + attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no"; +begin + \gc0.count_reg[1]\(1) <= rd_rst_reg(2); + \gc0.count_reg[1]\(0) <= rd_rst_reg(0); + \out\(1 downto 0) <= wr_rst_reg(1 downto 0); +\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.Arty_Z7_20_auto_pc_0_synchronizer_ff_14 + port map ( + clk => clk, + in0(0) => rd_rst_asreg, + \out\ => p_6_out + ); +\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.Arty_Z7_20_auto_pc_0_synchronizer_ff_15 + port map ( + clk => clk, + in0(0) => wr_rst_asreg, + \out\ => p_7_out + ); +\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.Arty_Z7_20_auto_pc_0_synchronizer_ff_16 + port map ( + AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\, + \Q_reg_reg[0]_0\ => p_8_out, + clk => clk, + in0(0) => rd_rst_asreg, + \out\ => p_6_out + ); +\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.Arty_Z7_20_auto_pc_0_synchronizer_ff_17 + port map ( + AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\, + \Q_reg_reg[0]_0\ => p_9_out, + clk => clk, + in0(0) => wr_rst_asreg, + \out\ => p_7_out + ); +\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.Arty_Z7_20_auto_pc_0_synchronizer_ff_18 + port map ( + \Q_reg_reg[0]_0\ => p_8_out, + clk => clk + ); +\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.Arty_Z7_20_auto_pc_0_synchronizer_ff_19 + port map ( + \Q_reg_reg[0]_0\ => p_9_out, + clk => clk + ); +\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\, + PRE => rst_rd_reg2, + Q => rd_rst_asreg + ); +\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => '0', + PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\, + Q => rd_rst_reg(0) + ); +\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => '0', + PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\, + Q => rd_rst_reg(1) + ); +\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => '0', + PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\, + Q => rd_rst_reg(2) + ); +\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => '0', + PRE => rst, + Q => rst_rd_reg1 + ); +\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => rst_rd_reg1, + PRE => rst, + Q => rst_rd_reg2 + ); +\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => '0', + PRE => rst, + Q => rst_wr_reg1 + ); +\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => rst_wr_reg1, + PRE => rst, + Q => rst_wr_reg2 + ); +\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\, + PRE => rst_wr_reg2, + Q => wr_rst_asreg + ); +\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => '0', + PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\, + Q => wr_rst_reg(0) + ); +\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => '0', + PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\, + Q => wr_rst_reg(1) + ); +\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => '0', + PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\, + Q => wr_rst_reg(2) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_reset_blk_ramfifo_28 is + port ( + \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + clk : in STD_LOGIC; + rst : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_reset_blk_ramfifo_28 : entity is "reset_blk_ramfifo"; +end Arty_Z7_20_auto_pc_0_reset_blk_ramfifo_28; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_reset_blk_ramfifo_28 is + signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC; + signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC; + signal p_6_out : STD_LOGIC; + signal p_7_out : STD_LOGIC; + signal p_8_out : STD_LOGIC; + signal p_9_out : STD_LOGIC; + signal rd_rst_asreg : STD_LOGIC; + signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true; + signal rst_rd_reg1 : STD_LOGIC; + attribute async_reg : string; + attribute async_reg of rst_rd_reg1 : signal is "true"; + attribute msgon : string; + attribute msgon of rst_rd_reg1 : signal is "true"; + signal rst_rd_reg2 : STD_LOGIC; + attribute async_reg of rst_rd_reg2 : signal is "true"; + attribute msgon of rst_rd_reg2 : signal is "true"; + signal rst_wr_reg1 : STD_LOGIC; + attribute async_reg of rst_wr_reg1 : signal is "true"; + attribute msgon of rst_wr_reg1 : signal is "true"; + signal rst_wr_reg2 : STD_LOGIC; + attribute async_reg of rst_wr_reg2 : signal is "true"; + attribute msgon of rst_wr_reg2 : signal is "true"; + signal wr_rst_asreg : STD_LOGIC; + signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true; + attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no"; + attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes"; + attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no"; + attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes"; + attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes"; + attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true"; + attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes"; + attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true"; + attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes"; + attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true"; + attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes"; + attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true"; + attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes"; + attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no"; + attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes"; + attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no"; + attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes"; + attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no"; +begin + \gc0.count_reg[1]\(1) <= rd_rst_reg(2); + \gc0.count_reg[1]\(0) <= rd_rst_reg(0); + \out\(1 downto 0) <= wr_rst_reg(1 downto 0); +\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.Arty_Z7_20_auto_pc_0_synchronizer_ff_29 + port map ( + clk => clk, + in0(0) => rd_rst_asreg, + \out\ => p_6_out + ); +\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.Arty_Z7_20_auto_pc_0_synchronizer_ff_30 + port map ( + clk => clk, + in0(0) => wr_rst_asreg, + \out\ => p_7_out + ); +\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.Arty_Z7_20_auto_pc_0_synchronizer_ff_31 + port map ( + AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\, + \Q_reg_reg[0]_0\ => p_8_out, + clk => clk, + in0(0) => rd_rst_asreg, + \out\ => p_6_out + ); +\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.Arty_Z7_20_auto_pc_0_synchronizer_ff_32 + port map ( + AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\, + \Q_reg_reg[0]_0\ => p_9_out, + clk => clk, + in0(0) => wr_rst_asreg, + \out\ => p_7_out + ); +\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.Arty_Z7_20_auto_pc_0_synchronizer_ff_33 + port map ( + \Q_reg_reg[0]_0\ => p_8_out, + clk => clk + ); +\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.Arty_Z7_20_auto_pc_0_synchronizer_ff_34 + port map ( + \Q_reg_reg[0]_0\ => p_9_out, + clk => clk + ); +\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\, + PRE => rst_rd_reg2, + Q => rd_rst_asreg + ); +\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => '0', + PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\, + Q => rd_rst_reg(0) + ); +\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => '0', + PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\, + Q => rd_rst_reg(1) + ); +\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => '0', + PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\, + Q => rd_rst_reg(2) + ); +\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => '0', + PRE => rst, + Q => rst_rd_reg1 + ); +\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => rst_rd_reg1, + PRE => rst, + Q => rst_rd_reg2 + ); +\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => '0', + PRE => rst, + Q => rst_wr_reg1 + ); +\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => '1', + D => rst_wr_reg1, + PRE => rst, + Q => rst_wr_reg2 + ); +\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\, + PRE => rst_wr_reg2, + Q => wr_rst_asreg + ); +\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => '0', + PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\, + Q => wr_rst_reg(0) + ); +\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => '0', + PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\, + Q => wr_rst_reg(1) + ); +\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => '0', + PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\, + Q => wr_rst_reg(2) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_wr_logic is + port ( + \out\ : out STD_LOGIC; + full : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + ram_empty_fb_i_reg : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 4 downto 0 ); + clk : in STD_LOGIC; + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + wr_en : in STD_LOGIC; + \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC; + \gc0.count_d1_reg[2]\ : in STD_LOGIC; + \gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ) + ); +end Arty_Z7_20_auto_pc_0_wr_logic; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_wr_logic is + signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^out\ : STD_LOGIC; + signal ram_full_comb : STD_LOGIC; +begin + E(0) <= \^e\(0); + \out\ <= \^out\; +\gwss.wsts\: entity work.Arty_Z7_20_auto_pc_0_wr_status_flags_ss + port map ( + E(0) => \^e\(0), + clk => clk, + full => full, + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + \out\ => \^out\, + ram_full_comb => ram_full_comb, + wr_en => wr_en + ); +wpntr: entity work.Arty_Z7_20_auto_pc_0_wr_bin_cntr + port map ( + E(0) => \^e\(0), + Q(4 downto 0) => Q(4 downto 0), + clk => clk, + \gc0.count_d1_reg[2]\ => \gc0.count_d1_reg[2]\, + \gc0.count_d1_reg[4]\(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), + \gc0.count_reg[2]\(2 downto 0) => \gc0.count_reg[2]\(2 downto 0), + \gpregsm1.curr_fwft_state_reg[0]\ => \gpregsm1.curr_fwft_state_reg[0]\, + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(1), + \out\ => \^out\, + ram_empty_fb_i_reg => ram_empty_fb_i_reg, + ram_full_comb => ram_full_comb, + wr_en => wr_en + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_wr_logic_11 is + port ( + \out\ : out STD_LOGIC; + full : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + ram_empty_fb_i_reg : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 4 downto 0 ); + clk : in STD_LOGIC; + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + wr_en : in STD_LOGIC; + \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC; + \gc0.count_d1_reg[2]\ : in STD_LOGIC; + \gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_wr_logic_11 : entity is "wr_logic"; +end Arty_Z7_20_auto_pc_0_wr_logic_11; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_wr_logic_11 is + signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^out\ : STD_LOGIC; + signal ram_full_comb : STD_LOGIC; +begin + E(0) <= \^e\(0); + \out\ <= \^out\; +\gwss.wsts\: entity work.Arty_Z7_20_auto_pc_0_wr_status_flags_ss_21 + port map ( + E(0) => \^e\(0), + clk => clk, + full => full, + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + \out\ => \^out\, + ram_full_comb => ram_full_comb, + wr_en => wr_en + ); +wpntr: entity work.Arty_Z7_20_auto_pc_0_wr_bin_cntr_22 + port map ( + E(0) => \^e\(0), + Q(4 downto 0) => Q(4 downto 0), + clk => clk, + \gc0.count_d1_reg[2]\ => \gc0.count_d1_reg[2]\, + \gc0.count_d1_reg[4]\(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), + \gc0.count_reg[2]\(2 downto 0) => \gc0.count_reg[2]\(2 downto 0), + \gpregsm1.curr_fwft_state_reg[0]\ => \gpregsm1.curr_fwft_state_reg[0]\, + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(1), + \out\ => \^out\, + ram_empty_fb_i_reg => ram_empty_fb_i_reg, + ram_full_comb => ram_full_comb, + wr_en => wr_en + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_wr_logic_27 is + port ( + \out\ : out STD_LOGIC; + full : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + ram_empty_fb_i_reg : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 4 downto 0 ); + clk : in STD_LOGIC; + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + wr_en : in STD_LOGIC; + \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC; + \gc0.count_d1_reg[2]\ : in STD_LOGIC; + \gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_wr_logic_27 : entity is "wr_logic"; +end Arty_Z7_20_auto_pc_0_wr_logic_27; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_wr_logic_27 is + signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^out\ : STD_LOGIC; + signal ram_full_comb : STD_LOGIC; +begin + E(0) <= \^e\(0); + \out\ <= \^out\; +\gwss.wsts\: entity work.Arty_Z7_20_auto_pc_0_wr_status_flags_ss_35 + port map ( + E(0) => \^e\(0), + clk => clk, + full => full, + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + \out\ => \^out\, + ram_full_comb => ram_full_comb, + wr_en => wr_en + ); +wpntr: entity work.Arty_Z7_20_auto_pc_0_wr_bin_cntr_36 + port map ( + E(0) => \^e\(0), + Q(4 downto 0) => Q(4 downto 0), + clk => clk, + \gc0.count_d1_reg[2]\ => \gc0.count_d1_reg[2]\, + \gc0.count_d1_reg[4]\(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), + \gc0.count_reg[2]\(2 downto 0) => \gc0.count_reg[2]\(2 downto 0), + \gpregsm1.curr_fwft_state_reg[0]\ => \gpregsm1.curr_fwft_state_reg[0]\, + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(1), + \out\ => \^out\, + ram_empty_fb_i_reg => ram_empty_fb_i_reg, + ram_full_comb => ram_full_comb, + wr_en => wr_en + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_fifo_generator_ramfifo is + port ( + empty : out STD_LOGIC; + full : out STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 4 downto 0 ); + clk : in STD_LOGIC; + rst : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 4 downto 0 ); + rd_en : in STD_LOGIC; + wr_en : in STD_LOGIC + ); +end Arty_Z7_20_auto_pc_0_fifo_generator_ramfifo; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_fifo_generator_ramfifo is + signal \gntv_or_sync_fifo.gl0.rd_n_12\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.wr_n_0\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC; + signal p_0_out_0 : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal p_11_out : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal p_17_out : STD_LOGIC; + signal ram_rd_en_i : STD_LOGIC; + signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal rst_full_ff_i : STD_LOGIC; + signal wr_rst_i : STD_LOGIC_VECTOR ( 1 to 1 ); +begin +\gntv_or_sync_fifo.gl0.rd\: entity work.Arty_Z7_20_auto_pc_0_rd_logic + port map ( + E(0) => ram_rd_en_i, + Q(2 downto 0) => rd_pntr_plus1(2 downto 0), + clk => clk, + empty => empty, + \gcc0.gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.wr_n_3\, + \gcc0.gc0.count_d1_reg[4]\(4 downto 0) => p_11_out(4 downto 0), + \goreg_dm.dout_i_reg[4]\(0) => \gntv_or_sync_fifo.gl0.rd_n_6\, + \gpr1.dout_i_reg[1]\(4 downto 0) => p_0_out_0(4 downto 0), + \out\(1) => rd_rst_i(2), + \out\(0) => rd_rst_i(0), + ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.rd_n_4\, + ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.rd_n_12\, + ram_full_fb_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_0\, + rd_en => rd_en, + wr_en => wr_en + ); +\gntv_or_sync_fifo.gl0.wr\: entity work.Arty_Z7_20_auto_pc_0_wr_logic + port map ( + E(0) => p_17_out, + Q(4 downto 0) => p_11_out(4 downto 0), + clk => clk, + full => full, + \gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.rd_n_4\, + \gc0.count_d1_reg[4]\(4 downto 0) => p_0_out_0(4 downto 0), + \gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0), + \gpregsm1.curr_fwft_state_reg[0]\ => \gntv_or_sync_fifo.gl0.rd_n_12\, + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(1) => wr_rst_i(1), + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => rst_full_ff_i, + \out\ => \gntv_or_sync_fifo.gl0.wr_n_0\, + ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\, + wr_en => wr_en + ); +\gntv_or_sync_fifo.mem\: entity work.Arty_Z7_20_auto_pc_0_memory + port map ( + E(0) => \gntv_or_sync_fifo.gl0.rd_n_6\, + EN => p_17_out, + I55(4 downto 0) => p_11_out(4 downto 0), + clk => clk, + din(4 downto 0) => din(4 downto 0), + dout(4 downto 0) => dout(4 downto 0), + \gc0.count_d1_reg[4]\(4 downto 0) => p_0_out_0(4 downto 0), + \gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i + ); +rstblk: entity work.Arty_Z7_20_auto_pc_0_reset_blk_ramfifo + port map ( + clk => clk, + \gc0.count_reg[1]\(1) => rd_rst_i(2), + \gc0.count_reg[1]\(0) => rd_rst_i(0), + \out\(1) => wr_rst_i(1), + \out\(0) => rst_full_ff_i, + rst => rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_fifo_generator_ramfifo_9 is + port ( + empty : out STD_LOGIC; + full : out STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 4 downto 0 ); + clk : in STD_LOGIC; + rst : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 4 downto 0 ); + rd_en : in STD_LOGIC; + wr_en : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_fifo_generator_ramfifo_9 : entity is "fifo_generator_ramfifo"; +end Arty_Z7_20_auto_pc_0_fifo_generator_ramfifo_9; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_fifo_generator_ramfifo_9 is + signal \gntv_or_sync_fifo.gl0.rd_n_12\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.wr_n_0\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC; + signal p_0_out_0 : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal p_11_out : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal p_17_out : STD_LOGIC; + signal ram_rd_en_i : STD_LOGIC; + signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal rst_full_ff_i : STD_LOGIC; + signal wr_rst_i : STD_LOGIC_VECTOR ( 1 to 1 ); +begin +\gntv_or_sync_fifo.gl0.rd\: entity work.Arty_Z7_20_auto_pc_0_rd_logic_10 + port map ( + E(0) => ram_rd_en_i, + Q(2 downto 0) => rd_pntr_plus1(2 downto 0), + clk => clk, + empty => empty, + \gcc0.gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.wr_n_3\, + \gcc0.gc0.count_d1_reg[4]\(4 downto 0) => p_11_out(4 downto 0), + \goreg_dm.dout_i_reg[4]\(0) => \gntv_or_sync_fifo.gl0.rd_n_6\, + \gpr1.dout_i_reg[1]\(4 downto 0) => p_0_out_0(4 downto 0), + \out\(1) => rd_rst_i(2), + \out\(0) => rd_rst_i(0), + ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.rd_n_4\, + ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.rd_n_12\, + ram_full_fb_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_0\, + rd_en => rd_en, + wr_en => wr_en + ); +\gntv_or_sync_fifo.gl0.wr\: entity work.Arty_Z7_20_auto_pc_0_wr_logic_11 + port map ( + E(0) => p_17_out, + Q(4 downto 0) => p_11_out(4 downto 0), + clk => clk, + full => full, + \gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.rd_n_4\, + \gc0.count_d1_reg[4]\(4 downto 0) => p_0_out_0(4 downto 0), + \gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0), + \gpregsm1.curr_fwft_state_reg[0]\ => \gntv_or_sync_fifo.gl0.rd_n_12\, + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(1) => wr_rst_i(1), + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => rst_full_ff_i, + \out\ => \gntv_or_sync_fifo.gl0.wr_n_0\, + ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\, + wr_en => wr_en + ); +\gntv_or_sync_fifo.mem\: entity work.Arty_Z7_20_auto_pc_0_memory_12 + port map ( + E(0) => \gntv_or_sync_fifo.gl0.rd_n_6\, + EN => p_17_out, + I54(4 downto 0) => p_11_out(4 downto 0), + clk => clk, + din(4 downto 0) => din(4 downto 0), + dout(4 downto 0) => dout(4 downto 0), + \gc0.count_d1_reg[4]\(4 downto 0) => p_0_out_0(4 downto 0), + \gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i + ); +rstblk: entity work.Arty_Z7_20_auto_pc_0_reset_blk_ramfifo_13 + port map ( + clk => clk, + \gc0.count_reg[1]\(1) => rd_rst_i(2), + \gc0.count_reg[1]\(0) => rd_rst_i(0), + \out\(1) => wr_rst_i(1), + \out\(0) => rst_full_ff_i, + rst => rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_auto_pc_0_fifo_generator_ramfifo__parameterized0\ is + port ( + empty : out STD_LOGIC; + full : out STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 0 to 0 ); + clk : in STD_LOGIC; + rst : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 0 to 0 ); + rd_en : in STD_LOGIC; + wr_en : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_auto_pc_0_fifo_generator_ramfifo__parameterized0\ : entity is "fifo_generator_ramfifo"; +end \Arty_Z7_20_auto_pc_0_fifo_generator_ramfifo__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_auto_pc_0_fifo_generator_ramfifo__parameterized0\ is + signal dout_i : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd_n_0\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd_n_13\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd_n_3\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.wr_n_0\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC; + signal \gr1.gr1_int.rfwft/p_0_in\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal p_0_out : STD_LOGIC; + signal p_0_out_0 : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal p_11_out : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal p_17_out : STD_LOGIC; + signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal rst_full_ff_i : STD_LOGIC; + signal wr_rst_i : STD_LOGIC_VECTOR ( 1 to 1 ); +begin +\gntv_or_sync_fifo.gl0.rd\: entity work.Arty_Z7_20_auto_pc_0_rd_logic_26 + port map ( + AR(0) => rd_rst_i(2), + Q(2 downto 0) => rd_pntr_plus1(2 downto 0), + clk => clk, + dout_i => dout_i, + empty => empty, + \gcc0.gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.wr_n_3\, + \gcc0.gc0.count_d1_reg[4]\(4 downto 0) => p_11_out(4 downto 0), + \gpr1.dout_i_reg[0]\ => \gntv_or_sync_fifo.gl0.rd_n_3\, + \gpr1.dout_i_reg[0]_0\(4 downto 0) => p_0_out_0(4 downto 0), + \out\(1) => \gntv_or_sync_fifo.gl0.rd_n_0\, + \out\(0) => \gr1.gr1_int.rfwft/p_0_in\(0), + p_0_out => p_0_out, + ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.rd_n_7\, + ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.rd_n_13\, + ram_full_fb_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_0\, + rd_en => rd_en, + wr_en => wr_en + ); +\gntv_or_sync_fifo.gl0.wr\: entity work.Arty_Z7_20_auto_pc_0_wr_logic_27 + port map ( + E(0) => p_17_out, + Q(4 downto 0) => p_11_out(4 downto 0), + clk => clk, + full => full, + \gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.rd_n_7\, + \gc0.count_d1_reg[4]\(4 downto 0) => p_0_out_0(4 downto 0), + \gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0), + \gpregsm1.curr_fwft_state_reg[0]\ => \gntv_or_sync_fifo.gl0.rd_n_13\, + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(1) => wr_rst_i(1), + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => rst_full_ff_i, + \out\ => \gntv_or_sync_fifo.gl0.wr_n_0\, + ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\, + wr_en => wr_en + ); +\gntv_or_sync_fifo.mem\: entity work.\Arty_Z7_20_auto_pc_0_memory__parameterized0\ + port map ( + E(0) => p_17_out, + Q(4 downto 0) => p_11_out(4 downto 0), + clk => clk, + din(0) => din(0), + dout(0) => dout(0), + dout_i => dout_i, + \gc0.count_d1_reg[4]\(4 downto 0) => p_0_out_0(4 downto 0), + \gpregsm1.curr_fwft_state_reg[1]\ => \gntv_or_sync_fifo.gl0.rd_n_3\, + \gpregsm1.curr_fwft_state_reg[1]_0\(1) => \gntv_or_sync_fifo.gl0.rd_n_0\, + \gpregsm1.curr_fwft_state_reg[1]_0\(0) => \gr1.gr1_int.rfwft/p_0_in\(0), + \out\(0) => rd_rst_i(0), + p_0_out => p_0_out, + rd_en => rd_en + ); +rstblk: entity work.Arty_Z7_20_auto_pc_0_reset_blk_ramfifo_28 + port map ( + clk => clk, + \gc0.count_reg[1]\(1) => rd_rst_i(2), + \gc0.count_reg[1]\(0) => rd_rst_i(0), + \out\(1) => wr_rst_i(1), + \out\(0) => rst_full_ff_i, + rst => rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_fifo_generator_top is + port ( + empty : out STD_LOGIC; + full : out STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 4 downto 0 ); + clk : in STD_LOGIC; + rst : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 4 downto 0 ); + rd_en : in STD_LOGIC; + wr_en : in STD_LOGIC + ); +end Arty_Z7_20_auto_pc_0_fifo_generator_top; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_fifo_generator_top is +begin +\grf.rf\: entity work.Arty_Z7_20_auto_pc_0_fifo_generator_ramfifo + port map ( + clk => clk, + din(4 downto 0) => din(4 downto 0), + dout(4 downto 0) => dout(4 downto 0), + empty => empty, + full => full, + rd_en => rd_en, + rst => rst, + wr_en => wr_en + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_fifo_generator_top_8 is + port ( + empty : out STD_LOGIC; + full : out STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 4 downto 0 ); + clk : in STD_LOGIC; + rst : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 4 downto 0 ); + rd_en : in STD_LOGIC; + wr_en : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_fifo_generator_top_8 : entity is "fifo_generator_top"; +end Arty_Z7_20_auto_pc_0_fifo_generator_top_8; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_fifo_generator_top_8 is +begin +\grf.rf\: entity work.Arty_Z7_20_auto_pc_0_fifo_generator_ramfifo_9 + port map ( + clk => clk, + din(4 downto 0) => din(4 downto 0), + dout(4 downto 0) => dout(4 downto 0), + empty => empty, + full => full, + rd_en => rd_en, + rst => rst, + wr_en => wr_en + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_auto_pc_0_fifo_generator_top__parameterized0\ is + port ( + empty : out STD_LOGIC; + full : out STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 0 to 0 ); + clk : in STD_LOGIC; + rst : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 0 to 0 ); + rd_en : in STD_LOGIC; + wr_en : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_auto_pc_0_fifo_generator_top__parameterized0\ : entity is "fifo_generator_top"; +end \Arty_Z7_20_auto_pc_0_fifo_generator_top__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_auto_pc_0_fifo_generator_top__parameterized0\ is +begin +\grf.rf\: entity work.\Arty_Z7_20_auto_pc_0_fifo_generator_ramfifo__parameterized0\ + port map ( + clk => clk, + din(0) => din(0), + dout(0) => dout(0), + empty => empty, + full => full, + rd_en => rd_en, + rst => rst, + wr_en => wr_en + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3_synth is + port ( + empty : out STD_LOGIC; + full : out STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 4 downto 0 ); + clk : in STD_LOGIC; + rst : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 4 downto 0 ); + rd_en : in STD_LOGIC; + wr_en : in STD_LOGIC + ); +end Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3_synth; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3_synth is +begin +\gconvfifo.rf\: entity work.Arty_Z7_20_auto_pc_0_fifo_generator_top + port map ( + clk => clk, + din(4 downto 0) => din(4 downto 0), + dout(4 downto 0) => dout(4 downto 0), + empty => empty, + full => full, + rd_en => rd_en, + rst => rst, + wr_en => wr_en + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3_synth_7 is + port ( + empty : out STD_LOGIC; + full : out STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 4 downto 0 ); + clk : in STD_LOGIC; + rst : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 4 downto 0 ); + rd_en : in STD_LOGIC; + wr_en : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3_synth_7 : entity is "fifo_generator_v13_1_3_synth"; +end Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3_synth_7; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3_synth_7 is +begin +\gconvfifo.rf\: entity work.Arty_Z7_20_auto_pc_0_fifo_generator_top_8 + port map ( + clk => clk, + din(4 downto 0) => din(4 downto 0), + dout(4 downto 0) => dout(4 downto 0), + empty => empty, + full => full, + rd_en => rd_en, + rst => rst, + wr_en => wr_en + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3_synth__parameterized0\ is + port ( + empty : out STD_LOGIC; + full : out STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 0 to 0 ); + clk : in STD_LOGIC; + rst : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 0 to 0 ); + rd_en : in STD_LOGIC; + wr_en : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3_synth__parameterized0\ : entity is "fifo_generator_v13_1_3_synth"; +end \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3_synth__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3_synth__parameterized0\ is +begin +\gconvfifo.rf\: entity work.\Arty_Z7_20_auto_pc_0_fifo_generator_top__parameterized0\ + port map ( + clk => clk, + din(0) => din(0), + dout(0) => dout(0), + empty => empty, + full => full, + rd_en => rd_en, + rst => rst, + wr_en => wr_en + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 is + port ( + backup : in STD_LOGIC; + backup_marker : in STD_LOGIC; + clk : in STD_LOGIC; + rst : in STD_LOGIC; + srst : in STD_LOGIC; + wr_clk : in STD_LOGIC; + wr_rst : in STD_LOGIC; + rd_clk : in STD_LOGIC; + rd_rst : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 4 downto 0 ); + wr_en : in STD_LOGIC; + rd_en : in STD_LOGIC; + prog_empty_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 ); + prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 ); + prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 ); + prog_full_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 ); + prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 ); + prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 ); + int_clk : in STD_LOGIC; + injectdbiterr : in STD_LOGIC; + injectsbiterr : in STD_LOGIC; + sleep : in STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 4 downto 0 ); + full : out STD_LOGIC; + almost_full : out STD_LOGIC; + wr_ack : out STD_LOGIC; + overflow : out STD_LOGIC; + empty : out STD_LOGIC; + almost_empty : out STD_LOGIC; + valid : out STD_LOGIC; + underflow : out STD_LOGIC; + data_count : out STD_LOGIC_VECTOR ( 5 downto 0 ); + rd_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 ); + wr_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 ); + prog_full : out STD_LOGIC; + prog_empty : out STD_LOGIC; + sbiterr : out STD_LOGIC; + dbiterr : out STD_LOGIC; + wr_rst_busy : out STD_LOGIC; + rd_rst_busy : out STD_LOGIC; + m_aclk : in STD_LOGIC; + s_aclk : in STD_LOGIC; + s_aresetn : in STD_LOGIC; + m_aclk_en : in STD_LOGIC; + s_aclk_en : in STD_LOGIC; + s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wid : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_wlast : in STD_LOGIC; + s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + m_axi_awid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awvalid : out STD_LOGIC; + m_axi_awready : in STD_LOGIC; + m_axi_wid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_wlast : out STD_LOGIC; + m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_wvalid : out STD_LOGIC; + m_axi_wready : in STD_LOGIC; + m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_bvalid : in STD_LOGIC; + m_axi_bready : out STD_LOGIC; + s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_arvalid : in STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rlast : out STD_LOGIC; + s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rvalid : out STD_LOGIC; + s_axi_rready : in STD_LOGIC; + m_axi_arid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_arvalid : out STD_LOGIC; + m_axi_arready : in STD_LOGIC; + m_axi_rid : in STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_rlast : in STD_LOGIC; + m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rvalid : in STD_LOGIC; + m_axi_rready : out STD_LOGIC; + s_axis_tvalid : in STD_LOGIC; + s_axis_tready : out STD_LOGIC; + s_axis_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axis_tstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axis_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axis_tlast : in STD_LOGIC; + s_axis_tid : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axis_tdest : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axis_tvalid : out STD_LOGIC; + m_axis_tready : in STD_LOGIC; + m_axis_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axis_tstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axis_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axis_tlast : out STD_LOGIC; + m_axis_tid : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axis_tdest : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 ); + axi_aw_injectsbiterr : in STD_LOGIC; + axi_aw_injectdbiterr : in STD_LOGIC; + axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); + axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); + axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); + axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); + axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); + axi_aw_sbiterr : out STD_LOGIC; + axi_aw_dbiterr : out STD_LOGIC; + axi_aw_overflow : out STD_LOGIC; + axi_aw_underflow : out STD_LOGIC; + axi_aw_prog_full : out STD_LOGIC; + axi_aw_prog_empty : out STD_LOGIC; + axi_w_injectsbiterr : in STD_LOGIC; + axi_w_injectdbiterr : in STD_LOGIC; + axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); + axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); + axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); + axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); + axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); + axi_w_sbiterr : out STD_LOGIC; + axi_w_dbiterr : out STD_LOGIC; + axi_w_overflow : out STD_LOGIC; + axi_w_underflow : out STD_LOGIC; + axi_w_prog_full : out STD_LOGIC; + axi_w_prog_empty : out STD_LOGIC; + axi_b_injectsbiterr : in STD_LOGIC; + axi_b_injectdbiterr : in STD_LOGIC; + axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); + axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); + axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); + axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); + axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); + axi_b_sbiterr : out STD_LOGIC; + axi_b_dbiterr : out STD_LOGIC; + axi_b_overflow : out STD_LOGIC; + axi_b_underflow : out STD_LOGIC; + axi_b_prog_full : out STD_LOGIC; + axi_b_prog_empty : out STD_LOGIC; + axi_ar_injectsbiterr : in STD_LOGIC; + axi_ar_injectdbiterr : in STD_LOGIC; + axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); + axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); + axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); + axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); + axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); + axi_ar_sbiterr : out STD_LOGIC; + axi_ar_dbiterr : out STD_LOGIC; + axi_ar_overflow : out STD_LOGIC; + axi_ar_underflow : out STD_LOGIC; + axi_ar_prog_full : out STD_LOGIC; + axi_ar_prog_empty : out STD_LOGIC; + axi_r_injectsbiterr : in STD_LOGIC; + axi_r_injectdbiterr : in STD_LOGIC; + axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); + axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); + axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); + axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); + axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); + axi_r_sbiterr : out STD_LOGIC; + axi_r_dbiterr : out STD_LOGIC; + axi_r_overflow : out STD_LOGIC; + axi_r_underflow : out STD_LOGIC; + axi_r_prog_full : out STD_LOGIC; + axi_r_prog_empty : out STD_LOGIC; + axis_injectsbiterr : in STD_LOGIC; + axis_injectdbiterr : in STD_LOGIC; + axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); + axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); + axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); + axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); + axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); + axis_sbiterr : out STD_LOGIC; + axis_dbiterr : out STD_LOGIC; + axis_overflow : out STD_LOGIC; + axis_underflow : out STD_LOGIC; + axis_prog_full : out STD_LOGIC; + axis_prog_empty : out STD_LOGIC + ); + attribute C_ADD_NGC_CONSTRAINT : integer; + attribute C_ADD_NGC_CONSTRAINT of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_APPLICATION_TYPE_AXIS : integer; + attribute C_APPLICATION_TYPE_AXIS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_APPLICATION_TYPE_RACH : integer; + attribute C_APPLICATION_TYPE_RACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_APPLICATION_TYPE_RDCH : integer; + attribute C_APPLICATION_TYPE_RDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_APPLICATION_TYPE_WACH : integer; + attribute C_APPLICATION_TYPE_WACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_APPLICATION_TYPE_WDCH : integer; + attribute C_APPLICATION_TYPE_WDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_APPLICATION_TYPE_WRCH : integer; + attribute C_APPLICATION_TYPE_WRCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_AXIS_TDATA_WIDTH : integer; + attribute C_AXIS_TDATA_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 64; + attribute C_AXIS_TDEST_WIDTH : integer; + attribute C_AXIS_TDEST_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 4; + attribute C_AXIS_TID_WIDTH : integer; + attribute C_AXIS_TID_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 8; + attribute C_AXIS_TKEEP_WIDTH : integer; + attribute C_AXIS_TKEEP_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 4; + attribute C_AXIS_TSTRB_WIDTH : integer; + attribute C_AXIS_TSTRB_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 4; + attribute C_AXIS_TUSER_WIDTH : integer; + attribute C_AXIS_TUSER_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 4; + attribute C_AXIS_TYPE : integer; + attribute C_AXIS_TYPE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_AXI_ADDR_WIDTH : integer; + attribute C_AXI_ADDR_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 32; + attribute C_AXI_ARUSER_WIDTH : integer; + attribute C_AXI_ARUSER_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_AXI_AWUSER_WIDTH : integer; + attribute C_AXI_AWUSER_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_AXI_BUSER_WIDTH : integer; + attribute C_AXI_BUSER_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_AXI_DATA_WIDTH : integer; + attribute C_AXI_DATA_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 64; + attribute C_AXI_ID_WIDTH : integer; + attribute C_AXI_ID_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 4; + attribute C_AXI_LEN_WIDTH : integer; + attribute C_AXI_LEN_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 8; + attribute C_AXI_LOCK_WIDTH : integer; + attribute C_AXI_LOCK_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 2; + attribute C_AXI_RUSER_WIDTH : integer; + attribute C_AXI_RUSER_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_AXI_TYPE : integer; + attribute C_AXI_TYPE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_AXI_WUSER_WIDTH : integer; + attribute C_AXI_WUSER_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_COMMON_CLOCK : integer; + attribute C_COMMON_CLOCK of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_COUNT_TYPE : integer; + attribute C_COUNT_TYPE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_DATA_COUNT_WIDTH : integer; + attribute C_DATA_COUNT_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 6; + attribute C_DEFAULT_VALUE : string; + attribute C_DEFAULT_VALUE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is "BlankString"; + attribute C_DIN_WIDTH : integer; + attribute C_DIN_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 5; + attribute C_DIN_WIDTH_AXIS : integer; + attribute C_DIN_WIDTH_AXIS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_DIN_WIDTH_RACH : integer; + attribute C_DIN_WIDTH_RACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 32; + attribute C_DIN_WIDTH_RDCH : integer; + attribute C_DIN_WIDTH_RDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 64; + attribute C_DIN_WIDTH_WACH : integer; + attribute C_DIN_WIDTH_WACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 32; + attribute C_DIN_WIDTH_WDCH : integer; + attribute C_DIN_WIDTH_WDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 64; + attribute C_DIN_WIDTH_WRCH : integer; + attribute C_DIN_WIDTH_WRCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 2; + attribute C_DOUT_RST_VAL : string; + attribute C_DOUT_RST_VAL of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is "0"; + attribute C_DOUT_WIDTH : integer; + attribute C_DOUT_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 5; + attribute C_ENABLE_RLOCS : integer; + attribute C_ENABLE_RLOCS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_ENABLE_RST_SYNC : integer; + attribute C_ENABLE_RST_SYNC of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_EN_SAFETY_CKT : integer; + attribute C_EN_SAFETY_CKT of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_ERROR_INJECTION_TYPE : integer; + attribute C_ERROR_INJECTION_TYPE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_ERROR_INJECTION_TYPE_AXIS : integer; + attribute C_ERROR_INJECTION_TYPE_AXIS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_ERROR_INJECTION_TYPE_RACH : integer; + attribute C_ERROR_INJECTION_TYPE_RACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_ERROR_INJECTION_TYPE_RDCH : integer; + attribute C_ERROR_INJECTION_TYPE_RDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_ERROR_INJECTION_TYPE_WACH : integer; + attribute C_ERROR_INJECTION_TYPE_WACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_ERROR_INJECTION_TYPE_WDCH : integer; + attribute C_ERROR_INJECTION_TYPE_WDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_ERROR_INJECTION_TYPE_WRCH : integer; + attribute C_ERROR_INJECTION_TYPE_WRCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_FAMILY : string; + attribute C_FAMILY of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is "zynq"; + attribute C_FULL_FLAGS_RST_VAL : integer; + attribute C_FULL_FLAGS_RST_VAL of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_ALMOST_EMPTY : integer; + attribute C_HAS_ALMOST_EMPTY of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_ALMOST_FULL : integer; + attribute C_HAS_ALMOST_FULL of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXIS_TDATA : integer; + attribute C_HAS_AXIS_TDATA of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXIS_TDEST : integer; + attribute C_HAS_AXIS_TDEST of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXIS_TID : integer; + attribute C_HAS_AXIS_TID of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXIS_TKEEP : integer; + attribute C_HAS_AXIS_TKEEP of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXIS_TLAST : integer; + attribute C_HAS_AXIS_TLAST of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXIS_TREADY : integer; + attribute C_HAS_AXIS_TREADY of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_HAS_AXIS_TSTRB : integer; + attribute C_HAS_AXIS_TSTRB of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXIS_TUSER : integer; + attribute C_HAS_AXIS_TUSER of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXI_ARUSER : integer; + attribute C_HAS_AXI_ARUSER of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXI_AWUSER : integer; + attribute C_HAS_AXI_AWUSER of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXI_BUSER : integer; + attribute C_HAS_AXI_BUSER of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXI_ID : integer; + attribute C_HAS_AXI_ID of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXI_RD_CHANNEL : integer; + attribute C_HAS_AXI_RD_CHANNEL of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXI_RUSER : integer; + attribute C_HAS_AXI_RUSER of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXI_WR_CHANNEL : integer; + attribute C_HAS_AXI_WR_CHANNEL of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXI_WUSER : integer; + attribute C_HAS_AXI_WUSER of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_BACKUP : integer; + attribute C_HAS_BACKUP of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_DATA_COUNT : integer; + attribute C_HAS_DATA_COUNT of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_DATA_COUNTS_AXIS : integer; + attribute C_HAS_DATA_COUNTS_AXIS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_DATA_COUNTS_RACH : integer; + attribute C_HAS_DATA_COUNTS_RACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_DATA_COUNTS_RDCH : integer; + attribute C_HAS_DATA_COUNTS_RDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_DATA_COUNTS_WACH : integer; + attribute C_HAS_DATA_COUNTS_WACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_DATA_COUNTS_WDCH : integer; + attribute C_HAS_DATA_COUNTS_WDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_DATA_COUNTS_WRCH : integer; + attribute C_HAS_DATA_COUNTS_WRCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_INT_CLK : integer; + attribute C_HAS_INT_CLK of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_MASTER_CE : integer; + attribute C_HAS_MASTER_CE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_MEMINIT_FILE : integer; + attribute C_HAS_MEMINIT_FILE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_OVERFLOW : integer; + attribute C_HAS_OVERFLOW of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_PROG_FLAGS_AXIS : integer; + attribute C_HAS_PROG_FLAGS_AXIS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_PROG_FLAGS_RACH : integer; + attribute C_HAS_PROG_FLAGS_RACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_PROG_FLAGS_RDCH : integer; + attribute C_HAS_PROG_FLAGS_RDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_PROG_FLAGS_WACH : integer; + attribute C_HAS_PROG_FLAGS_WACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_PROG_FLAGS_WDCH : integer; + attribute C_HAS_PROG_FLAGS_WDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_PROG_FLAGS_WRCH : integer; + attribute C_HAS_PROG_FLAGS_WRCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_RD_DATA_COUNT : integer; + attribute C_HAS_RD_DATA_COUNT of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_RD_RST : integer; + attribute C_HAS_RD_RST of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_RST : integer; + attribute C_HAS_RST of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_HAS_SLAVE_CE : integer; + attribute C_HAS_SLAVE_CE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_SRST : integer; + attribute C_HAS_SRST of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_UNDERFLOW : integer; + attribute C_HAS_UNDERFLOW of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_VALID : integer; + attribute C_HAS_VALID of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_WR_ACK : integer; + attribute C_HAS_WR_ACK of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_WR_DATA_COUNT : integer; + attribute C_HAS_WR_DATA_COUNT of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_WR_RST : integer; + attribute C_HAS_WR_RST of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_IMPLEMENTATION_TYPE : integer; + attribute C_IMPLEMENTATION_TYPE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_IMPLEMENTATION_TYPE_AXIS : integer; + attribute C_IMPLEMENTATION_TYPE_AXIS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_IMPLEMENTATION_TYPE_RACH : integer; + attribute C_IMPLEMENTATION_TYPE_RACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_IMPLEMENTATION_TYPE_RDCH : integer; + attribute C_IMPLEMENTATION_TYPE_RDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_IMPLEMENTATION_TYPE_WACH : integer; + attribute C_IMPLEMENTATION_TYPE_WACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_IMPLEMENTATION_TYPE_WDCH : integer; + attribute C_IMPLEMENTATION_TYPE_WDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_IMPLEMENTATION_TYPE_WRCH : integer; + attribute C_IMPLEMENTATION_TYPE_WRCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_INIT_WR_PNTR_VAL : integer; + attribute C_INIT_WR_PNTR_VAL of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_INTERFACE_TYPE : integer; + attribute C_INTERFACE_TYPE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_MEMORY_TYPE : integer; + attribute C_MEMORY_TYPE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 2; + attribute C_MIF_FILE_NAME : string; + attribute C_MIF_FILE_NAME of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is "BlankString"; + attribute C_MSGON_VAL : integer; + attribute C_MSGON_VAL of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_OPTIMIZATION_MODE : integer; + attribute C_OPTIMIZATION_MODE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_OVERFLOW_LOW : integer; + attribute C_OVERFLOW_LOW of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_POWER_SAVING_MODE : integer; + attribute C_POWER_SAVING_MODE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PRELOAD_LATENCY : integer; + attribute C_PRELOAD_LATENCY of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PRELOAD_REGS : integer; + attribute C_PRELOAD_REGS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_PRIM_FIFO_TYPE : string; + attribute C_PRIM_FIFO_TYPE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is "512x36"; + attribute C_PRIM_FIFO_TYPE_AXIS : string; + attribute C_PRIM_FIFO_TYPE_AXIS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is "512x36"; + attribute C_PRIM_FIFO_TYPE_RACH : string; + attribute C_PRIM_FIFO_TYPE_RACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is "512x36"; + attribute C_PRIM_FIFO_TYPE_RDCH : string; + attribute C_PRIM_FIFO_TYPE_RDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is "512x36"; + attribute C_PRIM_FIFO_TYPE_WACH : string; + attribute C_PRIM_FIFO_TYPE_WACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is "512x36"; + attribute C_PRIM_FIFO_TYPE_WDCH : string; + attribute C_PRIM_FIFO_TYPE_WDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is "512x36"; + attribute C_PRIM_FIFO_TYPE_WRCH : string; + attribute C_PRIM_FIFO_TYPE_WRCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is "512x36"; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 4; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1022; + attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer; + attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 5; + attribute C_PROG_EMPTY_TYPE : integer; + attribute C_PROG_EMPTY_TYPE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_EMPTY_TYPE_AXIS : integer; + attribute C_PROG_EMPTY_TYPE_AXIS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_EMPTY_TYPE_RACH : integer; + attribute C_PROG_EMPTY_TYPE_RACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_EMPTY_TYPE_RDCH : integer; + attribute C_PROG_EMPTY_TYPE_RDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_EMPTY_TYPE_WACH : integer; + attribute C_PROG_EMPTY_TYPE_WACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_EMPTY_TYPE_WDCH : integer; + attribute C_PROG_EMPTY_TYPE_WDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_EMPTY_TYPE_WRCH : integer; + attribute C_PROG_EMPTY_TYPE_WRCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 31; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1023; + attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer; + attribute C_PROG_FULL_THRESH_NEGATE_VAL of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 30; + attribute C_PROG_FULL_TYPE : integer; + attribute C_PROG_FULL_TYPE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_FULL_TYPE_AXIS : integer; + attribute C_PROG_FULL_TYPE_AXIS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_FULL_TYPE_RACH : integer; + attribute C_PROG_FULL_TYPE_RACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_FULL_TYPE_RDCH : integer; + attribute C_PROG_FULL_TYPE_RDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_FULL_TYPE_WACH : integer; + attribute C_PROG_FULL_TYPE_WACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_FULL_TYPE_WDCH : integer; + attribute C_PROG_FULL_TYPE_WDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_FULL_TYPE_WRCH : integer; + attribute C_PROG_FULL_TYPE_WRCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_RACH_TYPE : integer; + attribute C_RACH_TYPE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_RDCH_TYPE : integer; + attribute C_RDCH_TYPE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_RD_DATA_COUNT_WIDTH : integer; + attribute C_RD_DATA_COUNT_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 6; + attribute C_RD_DEPTH : integer; + attribute C_RD_DEPTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 32; + attribute C_RD_FREQ : integer; + attribute C_RD_FREQ of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_RD_PNTR_WIDTH : integer; + attribute C_RD_PNTR_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 5; + attribute C_REG_SLICE_MODE_AXIS : integer; + attribute C_REG_SLICE_MODE_AXIS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_REG_SLICE_MODE_RACH : integer; + attribute C_REG_SLICE_MODE_RACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_REG_SLICE_MODE_RDCH : integer; + attribute C_REG_SLICE_MODE_RDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_REG_SLICE_MODE_WACH : integer; + attribute C_REG_SLICE_MODE_WACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_REG_SLICE_MODE_WDCH : integer; + attribute C_REG_SLICE_MODE_WDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_REG_SLICE_MODE_WRCH : integer; + attribute C_REG_SLICE_MODE_WRCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_SELECT_XPM : integer; + attribute C_SELECT_XPM of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_SYNCHRONIZER_STAGE : integer; + attribute C_SYNCHRONIZER_STAGE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 3; + attribute C_UNDERFLOW_LOW : integer; + attribute C_UNDERFLOW_LOW of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_COMMON_OVERFLOW : integer; + attribute C_USE_COMMON_OVERFLOW of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_COMMON_UNDERFLOW : integer; + attribute C_USE_COMMON_UNDERFLOW of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_DEFAULT_SETTINGS : integer; + attribute C_USE_DEFAULT_SETTINGS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_DOUT_RST : integer; + attribute C_USE_DOUT_RST of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_ECC : integer; + attribute C_USE_ECC of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_ECC_AXIS : integer; + attribute C_USE_ECC_AXIS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_ECC_RACH : integer; + attribute C_USE_ECC_RACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_ECC_RDCH : integer; + attribute C_USE_ECC_RDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_ECC_WACH : integer; + attribute C_USE_ECC_WACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_ECC_WDCH : integer; + attribute C_USE_ECC_WDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_ECC_WRCH : integer; + attribute C_USE_ECC_WRCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_EMBEDDED_REG : integer; + attribute C_USE_EMBEDDED_REG of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_FIFO16_FLAGS : integer; + attribute C_USE_FIFO16_FLAGS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_FWFT_DATA_COUNT : integer; + attribute C_USE_FWFT_DATA_COUNT of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_USE_PIPELINE_REG : integer; + attribute C_USE_PIPELINE_REG of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_VALID_LOW : integer; + attribute C_VALID_LOW of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_WACH_TYPE : integer; + attribute C_WACH_TYPE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_WDCH_TYPE : integer; + attribute C_WDCH_TYPE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_WRCH_TYPE : integer; + attribute C_WRCH_TYPE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_WR_ACK_LOW : integer; + attribute C_WR_ACK_LOW of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_WR_DATA_COUNT_WIDTH : integer; + attribute C_WR_DATA_COUNT_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 6; + attribute C_WR_DEPTH : integer; + attribute C_WR_DEPTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 32; + attribute C_WR_DEPTH_AXIS : integer; + attribute C_WR_DEPTH_AXIS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1024; + attribute C_WR_DEPTH_RACH : integer; + attribute C_WR_DEPTH_RACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 16; + attribute C_WR_DEPTH_RDCH : integer; + attribute C_WR_DEPTH_RDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1024; + attribute C_WR_DEPTH_WACH : integer; + attribute C_WR_DEPTH_WACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 16; + attribute C_WR_DEPTH_WDCH : integer; + attribute C_WR_DEPTH_WDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1024; + attribute C_WR_DEPTH_WRCH : integer; + attribute C_WR_DEPTH_WRCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 16; + attribute C_WR_FREQ : integer; + attribute C_WR_FREQ of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_WR_PNTR_WIDTH : integer; + attribute C_WR_PNTR_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 5; + attribute C_WR_PNTR_WIDTH_AXIS : integer; + attribute C_WR_PNTR_WIDTH_AXIS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 10; + attribute C_WR_PNTR_WIDTH_RACH : integer; + attribute C_WR_PNTR_WIDTH_RACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 4; + attribute C_WR_PNTR_WIDTH_RDCH : integer; + attribute C_WR_PNTR_WIDTH_RDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 10; + attribute C_WR_PNTR_WIDTH_WACH : integer; + attribute C_WR_PNTR_WIDTH_WACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 4; + attribute C_WR_PNTR_WIDTH_WDCH : integer; + attribute C_WR_PNTR_WIDTH_WDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 10; + attribute C_WR_PNTR_WIDTH_WRCH : integer; + attribute C_WR_PNTR_WIDTH_WRCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 4; + attribute C_WR_RESPONSE_LATENCY : integer; + attribute C_WR_RESPONSE_LATENCY of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; +end Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 is + signal \\ : STD_LOGIC; +begin + almost_empty <= \\; + almost_full <= \\; + axi_ar_data_count(4) <= \\; + axi_ar_data_count(3) <= \\; + axi_ar_data_count(2) <= \\; + axi_ar_data_count(1) <= \\; + axi_ar_data_count(0) <= \\; + axi_ar_dbiterr <= \\; + axi_ar_overflow <= \\; + axi_ar_prog_empty <= \\; + axi_ar_prog_full <= \\; + axi_ar_rd_data_count(4) <= \\; + axi_ar_rd_data_count(3) <= \\; + axi_ar_rd_data_count(2) <= \\; + axi_ar_rd_data_count(1) <= \\; + axi_ar_rd_data_count(0) <= \\; + axi_ar_sbiterr <= \\; + axi_ar_underflow <= \\; + axi_ar_wr_data_count(4) <= \\; + axi_ar_wr_data_count(3) <= \\; + axi_ar_wr_data_count(2) <= \\; + axi_ar_wr_data_count(1) <= \\; + axi_ar_wr_data_count(0) <= \\; + axi_aw_data_count(4) <= \\; + axi_aw_data_count(3) <= \\; + axi_aw_data_count(2) <= \\; + axi_aw_data_count(1) <= \\; + axi_aw_data_count(0) <= \\; + axi_aw_dbiterr <= \\; + axi_aw_overflow <= \\; + axi_aw_prog_empty <= \\; + axi_aw_prog_full <= \\; + axi_aw_rd_data_count(4) <= \\; + axi_aw_rd_data_count(3) <= \\; + axi_aw_rd_data_count(2) <= \\; + axi_aw_rd_data_count(1) <= \\; + axi_aw_rd_data_count(0) <= \\; + axi_aw_sbiterr <= \\; + axi_aw_underflow <= \\; + axi_aw_wr_data_count(4) <= \\; + axi_aw_wr_data_count(3) <= \\; + axi_aw_wr_data_count(2) <= \\; + axi_aw_wr_data_count(1) <= \\; + axi_aw_wr_data_count(0) <= \\; + axi_b_data_count(4) <= \\; + axi_b_data_count(3) <= \\; + axi_b_data_count(2) <= \\; + axi_b_data_count(1) <= \\; + axi_b_data_count(0) <= \\; + axi_b_dbiterr <= \\; + axi_b_overflow <= \\; + axi_b_prog_empty <= \\; + axi_b_prog_full <= \\; + axi_b_rd_data_count(4) <= \\; + axi_b_rd_data_count(3) <= \\; + axi_b_rd_data_count(2) <= \\; + axi_b_rd_data_count(1) <= \\; + axi_b_rd_data_count(0) <= \\; + axi_b_sbiterr <= \\; + axi_b_underflow <= \\; + axi_b_wr_data_count(4) <= \\; + axi_b_wr_data_count(3) <= \\; + axi_b_wr_data_count(2) <= \\; + axi_b_wr_data_count(1) <= \\; + axi_b_wr_data_count(0) <= \\; + axi_r_data_count(10) <= \\; + axi_r_data_count(9) <= \\; + axi_r_data_count(8) <= \\; + axi_r_data_count(7) <= \\; + axi_r_data_count(6) <= \\; + axi_r_data_count(5) <= \\; + axi_r_data_count(4) <= \\; + axi_r_data_count(3) <= \\; + axi_r_data_count(2) <= \\; + axi_r_data_count(1) <= \\; + axi_r_data_count(0) <= \\; + axi_r_dbiterr <= \\; + axi_r_overflow <= \\; + axi_r_prog_empty <= \\; + axi_r_prog_full <= \\; + axi_r_rd_data_count(10) <= \\; + axi_r_rd_data_count(9) <= \\; + axi_r_rd_data_count(8) <= \\; + axi_r_rd_data_count(7) <= \\; + axi_r_rd_data_count(6) <= \\; + axi_r_rd_data_count(5) <= \\; + axi_r_rd_data_count(4) <= \\; + axi_r_rd_data_count(3) <= \\; + axi_r_rd_data_count(2) <= \\; + axi_r_rd_data_count(1) <= \\; + axi_r_rd_data_count(0) <= \\; + axi_r_sbiterr <= \\; + axi_r_underflow <= \\; + axi_r_wr_data_count(10) <= \\; + axi_r_wr_data_count(9) <= \\; + axi_r_wr_data_count(8) <= \\; + axi_r_wr_data_count(7) <= \\; + axi_r_wr_data_count(6) <= \\; + axi_r_wr_data_count(5) <= \\; + axi_r_wr_data_count(4) <= \\; + axi_r_wr_data_count(3) <= \\; + axi_r_wr_data_count(2) <= \\; + axi_r_wr_data_count(1) <= \\; + axi_r_wr_data_count(0) <= \\; + axi_w_data_count(10) <= \\; + axi_w_data_count(9) <= \\; + axi_w_data_count(8) <= \\; + axi_w_data_count(7) <= \\; + axi_w_data_count(6) <= \\; + axi_w_data_count(5) <= \\; + axi_w_data_count(4) <= \\; + axi_w_data_count(3) <= \\; + axi_w_data_count(2) <= \\; + axi_w_data_count(1) <= \\; + axi_w_data_count(0) <= \\; + axi_w_dbiterr <= \\; + axi_w_overflow <= \\; + axi_w_prog_empty <= \\; + axi_w_prog_full <= \\; + axi_w_rd_data_count(10) <= \\; + axi_w_rd_data_count(9) <= \\; + axi_w_rd_data_count(8) <= \\; + axi_w_rd_data_count(7) <= \\; + axi_w_rd_data_count(6) <= \\; + axi_w_rd_data_count(5) <= \\; + axi_w_rd_data_count(4) <= \\; + axi_w_rd_data_count(3) <= \\; + axi_w_rd_data_count(2) <= \\; + axi_w_rd_data_count(1) <= \\; + axi_w_rd_data_count(0) <= \\; + axi_w_sbiterr <= \\; + axi_w_underflow <= \\; + axi_w_wr_data_count(10) <= \\; + axi_w_wr_data_count(9) <= \\; + axi_w_wr_data_count(8) <= \\; + axi_w_wr_data_count(7) <= \\; + axi_w_wr_data_count(6) <= \\; + axi_w_wr_data_count(5) <= \\; + axi_w_wr_data_count(4) <= \\; + axi_w_wr_data_count(3) <= \\; + axi_w_wr_data_count(2) <= \\; + axi_w_wr_data_count(1) <= \\; + axi_w_wr_data_count(0) <= \\; + axis_data_count(10) <= \\; + axis_data_count(9) <= \\; + axis_data_count(8) <= \\; + axis_data_count(7) <= \\; + axis_data_count(6) <= \\; + axis_data_count(5) <= \\; + axis_data_count(4) <= \\; + axis_data_count(3) <= \\; + axis_data_count(2) <= \\; + axis_data_count(1) <= \\; + axis_data_count(0) <= \\; + axis_dbiterr <= \\; + axis_overflow <= \\; + axis_prog_empty <= \\; + axis_prog_full <= \\; + axis_rd_data_count(10) <= \\; + axis_rd_data_count(9) <= \\; + axis_rd_data_count(8) <= \\; + axis_rd_data_count(7) <= \\; + axis_rd_data_count(6) <= \\; + axis_rd_data_count(5) <= \\; + axis_rd_data_count(4) <= \\; + axis_rd_data_count(3) <= \\; + axis_rd_data_count(2) <= \\; + axis_rd_data_count(1) <= \\; + axis_rd_data_count(0) <= \\; + axis_sbiterr <= \\; + axis_underflow <= \\; + axis_wr_data_count(10) <= \\; + axis_wr_data_count(9) <= \\; + axis_wr_data_count(8) <= \\; + axis_wr_data_count(7) <= \\; + axis_wr_data_count(6) <= \\; + axis_wr_data_count(5) <= \\; + axis_wr_data_count(4) <= \\; + axis_wr_data_count(3) <= \\; + axis_wr_data_count(2) <= \\; + axis_wr_data_count(1) <= \\; + axis_wr_data_count(0) <= \\; + data_count(5) <= \\; + data_count(4) <= \\; + data_count(3) <= \\; + data_count(2) <= \\; + data_count(1) <= \\; + data_count(0) <= \\; + dbiterr <= \\; + m_axi_araddr(31) <= \\; + m_axi_araddr(30) <= \\; + m_axi_araddr(29) <= \\; + m_axi_araddr(28) <= \\; + m_axi_araddr(27) <= \\; + m_axi_araddr(26) <= \\; + m_axi_araddr(25) <= \\; + m_axi_araddr(24) <= \\; + m_axi_araddr(23) <= \\; + m_axi_araddr(22) <= \\; + m_axi_araddr(21) <= \\; + m_axi_araddr(20) <= \\; + m_axi_araddr(19) <= \\; + m_axi_araddr(18) <= \\; + m_axi_araddr(17) <= \\; + m_axi_araddr(16) <= \\; + m_axi_araddr(15) <= \\; + m_axi_araddr(14) <= \\; + m_axi_araddr(13) <= \\; + m_axi_araddr(12) <= \\; + m_axi_araddr(11) <= \\; + m_axi_araddr(10) <= \\; + m_axi_araddr(9) <= \\; + m_axi_araddr(8) <= \\; + m_axi_araddr(7) <= \\; + m_axi_araddr(6) <= \\; + m_axi_araddr(5) <= \\; + m_axi_araddr(4) <= \\; + m_axi_araddr(3) <= \\; + m_axi_araddr(2) <= \\; + m_axi_araddr(1) <= \\; + m_axi_araddr(0) <= \\; + m_axi_arburst(1) <= \\; + m_axi_arburst(0) <= \\; + m_axi_arcache(3) <= \\; + m_axi_arcache(2) <= \\; + m_axi_arcache(1) <= \\; + m_axi_arcache(0) <= \\; + m_axi_arid(3) <= \\; + m_axi_arid(2) <= \\; + m_axi_arid(1) <= \\; + m_axi_arid(0) <= \\; + m_axi_arlen(7) <= \\; + m_axi_arlen(6) <= \\; + m_axi_arlen(5) <= \\; + m_axi_arlen(4) <= \\; + m_axi_arlen(3) <= \\; + m_axi_arlen(2) <= \\; + m_axi_arlen(1) <= \\; + m_axi_arlen(0) <= \\; + m_axi_arlock(1) <= \\; + m_axi_arlock(0) <= \\; + m_axi_arprot(2) <= \\; + m_axi_arprot(1) <= \\; + m_axi_arprot(0) <= \\; + m_axi_arqos(3) <= \\; + m_axi_arqos(2) <= \\; + m_axi_arqos(1) <= \\; + m_axi_arqos(0) <= \\; + m_axi_arregion(3) <= \\; + m_axi_arregion(2) <= \\; + m_axi_arregion(1) <= \\; + m_axi_arregion(0) <= \\; + m_axi_arsize(2) <= \\; + m_axi_arsize(1) <= \\; + m_axi_arsize(0) <= \\; + m_axi_aruser(0) <= \\; + m_axi_arvalid <= \\; + m_axi_awaddr(31) <= \\; + m_axi_awaddr(30) <= \\; + m_axi_awaddr(29) <= \\; + m_axi_awaddr(28) <= \\; + m_axi_awaddr(27) <= \\; + m_axi_awaddr(26) <= \\; + m_axi_awaddr(25) <= \\; + m_axi_awaddr(24) <= \\; + m_axi_awaddr(23) <= \\; + m_axi_awaddr(22) <= \\; + m_axi_awaddr(21) <= \\; + m_axi_awaddr(20) <= \\; + m_axi_awaddr(19) <= \\; + m_axi_awaddr(18) <= \\; + m_axi_awaddr(17) <= \\; + m_axi_awaddr(16) <= \\; + m_axi_awaddr(15) <= \\; + m_axi_awaddr(14) <= \\; + m_axi_awaddr(13) <= \\; + m_axi_awaddr(12) <= \\; + m_axi_awaddr(11) <= \\; + m_axi_awaddr(10) <= \\; + m_axi_awaddr(9) <= \\; + m_axi_awaddr(8) <= \\; + m_axi_awaddr(7) <= \\; + m_axi_awaddr(6) <= \\; + m_axi_awaddr(5) <= \\; + m_axi_awaddr(4) <= \\; + m_axi_awaddr(3) <= \\; + m_axi_awaddr(2) <= \\; + m_axi_awaddr(1) <= \\; + m_axi_awaddr(0) <= \\; + m_axi_awburst(1) <= \\; + m_axi_awburst(0) <= \\; + m_axi_awcache(3) <= \\; + m_axi_awcache(2) <= \\; + m_axi_awcache(1) <= \\; + m_axi_awcache(0) <= \\; + m_axi_awid(3) <= \\; + m_axi_awid(2) <= \\; + m_axi_awid(1) <= \\; + m_axi_awid(0) <= \\; + m_axi_awlen(7) <= \\; + m_axi_awlen(6) <= \\; + m_axi_awlen(5) <= \\; + m_axi_awlen(4) <= \\; + m_axi_awlen(3) <= \\; + m_axi_awlen(2) <= \\; + m_axi_awlen(1) <= \\; + m_axi_awlen(0) <= \\; + m_axi_awlock(1) <= \\; + m_axi_awlock(0) <= \\; + m_axi_awprot(2) <= \\; + m_axi_awprot(1) <= \\; + m_axi_awprot(0) <= \\; + m_axi_awqos(3) <= \\; + m_axi_awqos(2) <= \\; + m_axi_awqos(1) <= \\; + m_axi_awqos(0) <= \\; + m_axi_awregion(3) <= \\; + m_axi_awregion(2) <= \\; + m_axi_awregion(1) <= \\; + m_axi_awregion(0) <= \\; + m_axi_awsize(2) <= \\; + m_axi_awsize(1) <= \\; + m_axi_awsize(0) <= \\; + m_axi_awuser(0) <= \\; + m_axi_awvalid <= \\; + m_axi_bready <= \\; + m_axi_rready <= \\; + m_axi_wdata(63) <= \\; + m_axi_wdata(62) <= \\; + m_axi_wdata(61) <= \\; + m_axi_wdata(60) <= \\; + m_axi_wdata(59) <= \\; + m_axi_wdata(58) <= \\; + m_axi_wdata(57) <= \\; + m_axi_wdata(56) <= \\; + m_axi_wdata(55) <= \\; + m_axi_wdata(54) <= \\; + m_axi_wdata(53) <= \\; + m_axi_wdata(52) <= \\; + m_axi_wdata(51) <= \\; + m_axi_wdata(50) <= \\; + m_axi_wdata(49) <= \\; + m_axi_wdata(48) <= \\; + m_axi_wdata(47) <= \\; + m_axi_wdata(46) <= \\; + m_axi_wdata(45) <= \\; + m_axi_wdata(44) <= \\; + m_axi_wdata(43) <= \\; + m_axi_wdata(42) <= \\; + m_axi_wdata(41) <= \\; + m_axi_wdata(40) <= \\; + m_axi_wdata(39) <= \\; + m_axi_wdata(38) <= \\; + m_axi_wdata(37) <= \\; + m_axi_wdata(36) <= \\; + m_axi_wdata(35) <= \\; + m_axi_wdata(34) <= \\; + m_axi_wdata(33) <= \\; + m_axi_wdata(32) <= \\; + m_axi_wdata(31) <= \\; + m_axi_wdata(30) <= \\; + m_axi_wdata(29) <= \\; + m_axi_wdata(28) <= \\; + m_axi_wdata(27) <= \\; + m_axi_wdata(26) <= \\; + m_axi_wdata(25) <= \\; + m_axi_wdata(24) <= \\; + m_axi_wdata(23) <= \\; + m_axi_wdata(22) <= \\; + m_axi_wdata(21) <= \\; + m_axi_wdata(20) <= \\; + m_axi_wdata(19) <= \\; + m_axi_wdata(18) <= \\; + m_axi_wdata(17) <= \\; + m_axi_wdata(16) <= \\; + m_axi_wdata(15) <= \\; + m_axi_wdata(14) <= \\; + m_axi_wdata(13) <= \\; + m_axi_wdata(12) <= \\; + m_axi_wdata(11) <= \\; + m_axi_wdata(10) <= \\; + m_axi_wdata(9) <= \\; + m_axi_wdata(8) <= \\; + m_axi_wdata(7) <= \\; + m_axi_wdata(6) <= \\; + m_axi_wdata(5) <= \\; + m_axi_wdata(4) <= \\; + m_axi_wdata(3) <= \\; + m_axi_wdata(2) <= \\; + m_axi_wdata(1) <= \\; + m_axi_wdata(0) <= \\; + m_axi_wid(3) <= \\; + m_axi_wid(2) <= \\; + m_axi_wid(1) <= \\; + m_axi_wid(0) <= \\; + m_axi_wlast <= \\; + m_axi_wstrb(7) <= \\; + m_axi_wstrb(6) <= \\; + m_axi_wstrb(5) <= \\; + m_axi_wstrb(4) <= \\; + m_axi_wstrb(3) <= \\; + m_axi_wstrb(2) <= \\; + m_axi_wstrb(1) <= \\; + m_axi_wstrb(0) <= \\; + m_axi_wuser(0) <= \\; + m_axi_wvalid <= \\; + m_axis_tdata(63) <= \\; + m_axis_tdata(62) <= \\; + m_axis_tdata(61) <= \\; + m_axis_tdata(60) <= \\; + m_axis_tdata(59) <= \\; + m_axis_tdata(58) <= \\; + m_axis_tdata(57) <= \\; + m_axis_tdata(56) <= \\; + m_axis_tdata(55) <= \\; + m_axis_tdata(54) <= \\; + m_axis_tdata(53) <= \\; + m_axis_tdata(52) <= \\; + m_axis_tdata(51) <= \\; + m_axis_tdata(50) <= \\; + m_axis_tdata(49) <= \\; + m_axis_tdata(48) <= \\; + m_axis_tdata(47) <= \\; + m_axis_tdata(46) <= \\; + m_axis_tdata(45) <= \\; + m_axis_tdata(44) <= \\; + m_axis_tdata(43) <= \\; + m_axis_tdata(42) <= \\; + m_axis_tdata(41) <= \\; + m_axis_tdata(40) <= \\; + m_axis_tdata(39) <= \\; + m_axis_tdata(38) <= \\; + m_axis_tdata(37) <= \\; + m_axis_tdata(36) <= \\; + m_axis_tdata(35) <= \\; + m_axis_tdata(34) <= \\; + m_axis_tdata(33) <= \\; + m_axis_tdata(32) <= \\; + m_axis_tdata(31) <= \\; + m_axis_tdata(30) <= \\; + m_axis_tdata(29) <= \\; + m_axis_tdata(28) <= \\; + m_axis_tdata(27) <= \\; + m_axis_tdata(26) <= \\; + m_axis_tdata(25) <= \\; + m_axis_tdata(24) <= \\; + m_axis_tdata(23) <= \\; + m_axis_tdata(22) <= \\; + m_axis_tdata(21) <= \\; + m_axis_tdata(20) <= \\; + m_axis_tdata(19) <= \\; + m_axis_tdata(18) <= \\; + m_axis_tdata(17) <= \\; + m_axis_tdata(16) <= \\; + m_axis_tdata(15) <= \\; + m_axis_tdata(14) <= \\; + m_axis_tdata(13) <= \\; + m_axis_tdata(12) <= \\; + m_axis_tdata(11) <= \\; + m_axis_tdata(10) <= \\; + m_axis_tdata(9) <= \\; + m_axis_tdata(8) <= \\; + m_axis_tdata(7) <= \\; + m_axis_tdata(6) <= \\; + m_axis_tdata(5) <= \\; + m_axis_tdata(4) <= \\; + m_axis_tdata(3) <= \\; + m_axis_tdata(2) <= \\; + m_axis_tdata(1) <= \\; + m_axis_tdata(0) <= \\; + m_axis_tdest(3) <= \\; + m_axis_tdest(2) <= \\; + m_axis_tdest(1) <= \\; + m_axis_tdest(0) <= \\; + m_axis_tid(7) <= \\; + m_axis_tid(6) <= \\; + m_axis_tid(5) <= \\; + m_axis_tid(4) <= \\; + m_axis_tid(3) <= \\; + m_axis_tid(2) <= \\; + m_axis_tid(1) <= \\; + m_axis_tid(0) <= \\; + m_axis_tkeep(3) <= \\; + m_axis_tkeep(2) <= \\; + m_axis_tkeep(1) <= \\; + m_axis_tkeep(0) <= \\; + m_axis_tlast <= \\; + m_axis_tstrb(3) <= \\; + m_axis_tstrb(2) <= \\; + m_axis_tstrb(1) <= \\; + m_axis_tstrb(0) <= \\; + m_axis_tuser(3) <= \\; + m_axis_tuser(2) <= \\; + m_axis_tuser(1) <= \\; + m_axis_tuser(0) <= \\; + m_axis_tvalid <= \\; + overflow <= \\; + prog_empty <= \\; + prog_full <= \\; + rd_data_count(5) <= \\; + rd_data_count(4) <= \\; + rd_data_count(3) <= \\; + rd_data_count(2) <= \\; + rd_data_count(1) <= \\; + rd_data_count(0) <= \\; + rd_rst_busy <= \\; + s_axi_arready <= \\; + s_axi_awready <= \\; + s_axi_bid(3) <= \\; + s_axi_bid(2) <= \\; + s_axi_bid(1) <= \\; + s_axi_bid(0) <= \\; + s_axi_bresp(1) <= \\; + s_axi_bresp(0) <= \\; + s_axi_buser(0) <= \\; + s_axi_bvalid <= \\; + s_axi_rdata(63) <= \\; + s_axi_rdata(62) <= \\; + s_axi_rdata(61) <= \\; + s_axi_rdata(60) <= \\; + s_axi_rdata(59) <= \\; + s_axi_rdata(58) <= \\; + s_axi_rdata(57) <= \\; + s_axi_rdata(56) <= \\; + s_axi_rdata(55) <= \\; + s_axi_rdata(54) <= \\; + s_axi_rdata(53) <= \\; + s_axi_rdata(52) <= \\; + s_axi_rdata(51) <= \\; + s_axi_rdata(50) <= \\; + s_axi_rdata(49) <= \\; + s_axi_rdata(48) <= \\; + s_axi_rdata(47) <= \\; + s_axi_rdata(46) <= \\; + s_axi_rdata(45) <= \\; + s_axi_rdata(44) <= \\; + s_axi_rdata(43) <= \\; + s_axi_rdata(42) <= \\; + s_axi_rdata(41) <= \\; + s_axi_rdata(40) <= \\; + s_axi_rdata(39) <= \\; + s_axi_rdata(38) <= \\; + s_axi_rdata(37) <= \\; + s_axi_rdata(36) <= \\; + s_axi_rdata(35) <= \\; + s_axi_rdata(34) <= \\; + s_axi_rdata(33) <= \\; + s_axi_rdata(32) <= \\; + s_axi_rdata(31) <= \\; + s_axi_rdata(30) <= \\; + s_axi_rdata(29) <= \\; + s_axi_rdata(28) <= \\; + s_axi_rdata(27) <= \\; + s_axi_rdata(26) <= \\; + s_axi_rdata(25) <= \\; + s_axi_rdata(24) <= \\; + s_axi_rdata(23) <= \\; + s_axi_rdata(22) <= \\; + s_axi_rdata(21) <= \\; + s_axi_rdata(20) <= \\; + s_axi_rdata(19) <= \\; + s_axi_rdata(18) <= \\; + s_axi_rdata(17) <= \\; + s_axi_rdata(16) <= \\; + s_axi_rdata(15) <= \\; + s_axi_rdata(14) <= \\; + s_axi_rdata(13) <= \\; + s_axi_rdata(12) <= \\; + s_axi_rdata(11) <= \\; + s_axi_rdata(10) <= \\; + s_axi_rdata(9) <= \\; + s_axi_rdata(8) <= \\; + s_axi_rdata(7) <= \\; + s_axi_rdata(6) <= \\; + s_axi_rdata(5) <= \\; + s_axi_rdata(4) <= \\; + s_axi_rdata(3) <= \\; + s_axi_rdata(2) <= \\; + s_axi_rdata(1) <= \\; + s_axi_rdata(0) <= \\; + s_axi_rid(3) <= \\; + s_axi_rid(2) <= \\; + s_axi_rid(1) <= \\; + s_axi_rid(0) <= \\; + s_axi_rlast <= \\; + s_axi_rresp(1) <= \\; + s_axi_rresp(0) <= \\; + s_axi_ruser(0) <= \\; + s_axi_rvalid <= \\; + s_axi_wready <= \\; + s_axis_tready <= \\; + sbiterr <= \\; + underflow <= \\; + valid <= \\; + wr_ack <= \\; + wr_data_count(5) <= \\; + wr_data_count(4) <= \\; + wr_data_count(3) <= \\; + wr_data_count(2) <= \\; + wr_data_count(1) <= \\; + wr_data_count(0) <= \\; + wr_rst_busy <= \\; +GND: unisim.vcomponents.GND + port map ( + G => \\ + ); +inst_fifo_gen: entity work.Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3_synth + port map ( + clk => clk, + din(4 downto 0) => din(4 downto 0), + dout(4 downto 0) => dout(4 downto 0), + empty => empty, + full => full, + rd_en => rd_en, + rst => rst, + wr_en => wr_en + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ is + port ( + backup : in STD_LOGIC; + backup_marker : in STD_LOGIC; + clk : in STD_LOGIC; + rst : in STD_LOGIC; + srst : in STD_LOGIC; + wr_clk : in STD_LOGIC; + wr_rst : in STD_LOGIC; + rd_clk : in STD_LOGIC; + rd_rst : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 4 downto 0 ); + wr_en : in STD_LOGIC; + rd_en : in STD_LOGIC; + prog_empty_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 ); + prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 ); + prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 ); + prog_full_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 ); + prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 ); + prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 ); + int_clk : in STD_LOGIC; + injectdbiterr : in STD_LOGIC; + injectsbiterr : in STD_LOGIC; + sleep : in STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 4 downto 0 ); + full : out STD_LOGIC; + almost_full : out STD_LOGIC; + wr_ack : out STD_LOGIC; + overflow : out STD_LOGIC; + empty : out STD_LOGIC; + almost_empty : out STD_LOGIC; + valid : out STD_LOGIC; + underflow : out STD_LOGIC; + data_count : out STD_LOGIC_VECTOR ( 5 downto 0 ); + rd_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 ); + wr_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 ); + prog_full : out STD_LOGIC; + prog_empty : out STD_LOGIC; + sbiterr : out STD_LOGIC; + dbiterr : out STD_LOGIC; + wr_rst_busy : out STD_LOGIC; + rd_rst_busy : out STD_LOGIC; + m_aclk : in STD_LOGIC; + s_aclk : in STD_LOGIC; + s_aresetn : in STD_LOGIC; + m_aclk_en : in STD_LOGIC; + s_aclk_en : in STD_LOGIC; + s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wid : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_wlast : in STD_LOGIC; + s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + m_axi_awid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awvalid : out STD_LOGIC; + m_axi_awready : in STD_LOGIC; + m_axi_wid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_wlast : out STD_LOGIC; + m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_wvalid : out STD_LOGIC; + m_axi_wready : in STD_LOGIC; + m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_bvalid : in STD_LOGIC; + m_axi_bready : out STD_LOGIC; + s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_arvalid : in STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rlast : out STD_LOGIC; + s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rvalid : out STD_LOGIC; + s_axi_rready : in STD_LOGIC; + m_axi_arid : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_arvalid : out STD_LOGIC; + m_axi_arready : in STD_LOGIC; + m_axi_rid : in STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_rlast : in STD_LOGIC; + m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rvalid : in STD_LOGIC; + m_axi_rready : out STD_LOGIC; + s_axis_tvalid : in STD_LOGIC; + s_axis_tready : out STD_LOGIC; + s_axis_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axis_tstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axis_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axis_tlast : in STD_LOGIC; + s_axis_tid : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axis_tdest : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axis_tvalid : out STD_LOGIC; + m_axis_tready : in STD_LOGIC; + m_axis_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axis_tstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axis_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axis_tlast : out STD_LOGIC; + m_axis_tid : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axis_tdest : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 ); + axi_aw_injectsbiterr : in STD_LOGIC; + axi_aw_injectdbiterr : in STD_LOGIC; + axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); + axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); + axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); + axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); + axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); + axi_aw_sbiterr : out STD_LOGIC; + axi_aw_dbiterr : out STD_LOGIC; + axi_aw_overflow : out STD_LOGIC; + axi_aw_underflow : out STD_LOGIC; + axi_aw_prog_full : out STD_LOGIC; + axi_aw_prog_empty : out STD_LOGIC; + axi_w_injectsbiterr : in STD_LOGIC; + axi_w_injectdbiterr : in STD_LOGIC; + axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); + axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); + axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); + axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); + axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); + axi_w_sbiterr : out STD_LOGIC; + axi_w_dbiterr : out STD_LOGIC; + axi_w_overflow : out STD_LOGIC; + axi_w_underflow : out STD_LOGIC; + axi_w_prog_full : out STD_LOGIC; + axi_w_prog_empty : out STD_LOGIC; + axi_b_injectsbiterr : in STD_LOGIC; + axi_b_injectdbiterr : in STD_LOGIC; + axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); + axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); + axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); + axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); + axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); + axi_b_sbiterr : out STD_LOGIC; + axi_b_dbiterr : out STD_LOGIC; + axi_b_overflow : out STD_LOGIC; + axi_b_underflow : out STD_LOGIC; + axi_b_prog_full : out STD_LOGIC; + axi_b_prog_empty : out STD_LOGIC; + axi_ar_injectsbiterr : in STD_LOGIC; + axi_ar_injectdbiterr : in STD_LOGIC; + axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); + axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); + axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); + axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); + axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); + axi_ar_sbiterr : out STD_LOGIC; + axi_ar_dbiterr : out STD_LOGIC; + axi_ar_overflow : out STD_LOGIC; + axi_ar_underflow : out STD_LOGIC; + axi_ar_prog_full : out STD_LOGIC; + axi_ar_prog_empty : out STD_LOGIC; + axi_r_injectsbiterr : in STD_LOGIC; + axi_r_injectdbiterr : in STD_LOGIC; + axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); + axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); + axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); + axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); + axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); + axi_r_sbiterr : out STD_LOGIC; + axi_r_dbiterr : out STD_LOGIC; + axi_r_overflow : out STD_LOGIC; + axi_r_underflow : out STD_LOGIC; + axi_r_prog_full : out STD_LOGIC; + axi_r_prog_empty : out STD_LOGIC; + axis_injectsbiterr : in STD_LOGIC; + axis_injectdbiterr : in STD_LOGIC; + axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); + axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 ); + axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); + axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); + axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 ); + axis_sbiterr : out STD_LOGIC; + axis_dbiterr : out STD_LOGIC; + axis_overflow : out STD_LOGIC; + axis_underflow : out STD_LOGIC; + axis_prog_full : out STD_LOGIC; + axis_prog_empty : out STD_LOGIC + ); + attribute C_ADD_NGC_CONSTRAINT : integer; + attribute C_ADD_NGC_CONSTRAINT of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_APPLICATION_TYPE_AXIS : integer; + attribute C_APPLICATION_TYPE_AXIS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_APPLICATION_TYPE_RACH : integer; + attribute C_APPLICATION_TYPE_RACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_APPLICATION_TYPE_RDCH : integer; + attribute C_APPLICATION_TYPE_RDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_APPLICATION_TYPE_WACH : integer; + attribute C_APPLICATION_TYPE_WACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_APPLICATION_TYPE_WDCH : integer; + attribute C_APPLICATION_TYPE_WDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_APPLICATION_TYPE_WRCH : integer; + attribute C_APPLICATION_TYPE_WRCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_AXIS_TDATA_WIDTH : integer; + attribute C_AXIS_TDATA_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 64; + attribute C_AXIS_TDEST_WIDTH : integer; + attribute C_AXIS_TDEST_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 4; + attribute C_AXIS_TID_WIDTH : integer; + attribute C_AXIS_TID_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 8; + attribute C_AXIS_TKEEP_WIDTH : integer; + attribute C_AXIS_TKEEP_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 4; + attribute C_AXIS_TSTRB_WIDTH : integer; + attribute C_AXIS_TSTRB_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 4; + attribute C_AXIS_TUSER_WIDTH : integer; + attribute C_AXIS_TUSER_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 4; + attribute C_AXIS_TYPE : integer; + attribute C_AXIS_TYPE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_AXI_ADDR_WIDTH : integer; + attribute C_AXI_ADDR_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 32; + attribute C_AXI_ARUSER_WIDTH : integer; + attribute C_AXI_ARUSER_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1; + attribute C_AXI_AWUSER_WIDTH : integer; + attribute C_AXI_AWUSER_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1; + attribute C_AXI_BUSER_WIDTH : integer; + attribute C_AXI_BUSER_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1; + attribute C_AXI_DATA_WIDTH : integer; + attribute C_AXI_DATA_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 64; + attribute C_AXI_ID_WIDTH : integer; + attribute C_AXI_ID_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 4; + attribute C_AXI_LEN_WIDTH : integer; + attribute C_AXI_LEN_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 8; + attribute C_AXI_LOCK_WIDTH : integer; + attribute C_AXI_LOCK_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 2; + attribute C_AXI_RUSER_WIDTH : integer; + attribute C_AXI_RUSER_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1; + attribute C_AXI_TYPE : integer; + attribute C_AXI_TYPE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_AXI_WUSER_WIDTH : integer; + attribute C_AXI_WUSER_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1; + attribute C_COMMON_CLOCK : integer; + attribute C_COMMON_CLOCK of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1; + attribute C_COUNT_TYPE : integer; + attribute C_COUNT_TYPE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_DATA_COUNT_WIDTH : integer; + attribute C_DATA_COUNT_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 6; + attribute C_DEFAULT_VALUE : string; + attribute C_DEFAULT_VALUE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is "BlankString"; + attribute C_DIN_WIDTH : integer; + attribute C_DIN_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 5; + attribute C_DIN_WIDTH_AXIS : integer; + attribute C_DIN_WIDTH_AXIS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1; + attribute C_DIN_WIDTH_RACH : integer; + attribute C_DIN_WIDTH_RACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 32; + attribute C_DIN_WIDTH_RDCH : integer; + attribute C_DIN_WIDTH_RDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 64; + attribute C_DIN_WIDTH_WACH : integer; + attribute C_DIN_WIDTH_WACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 32; + attribute C_DIN_WIDTH_WDCH : integer; + attribute C_DIN_WIDTH_WDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 64; + attribute C_DIN_WIDTH_WRCH : integer; + attribute C_DIN_WIDTH_WRCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 2; + attribute C_DOUT_RST_VAL : string; + attribute C_DOUT_RST_VAL of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is "0"; + attribute C_DOUT_WIDTH : integer; + attribute C_DOUT_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 5; + attribute C_ENABLE_RLOCS : integer; + attribute C_ENABLE_RLOCS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_ENABLE_RST_SYNC : integer; + attribute C_ENABLE_RST_SYNC of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1; + attribute C_EN_SAFETY_CKT : integer; + attribute C_EN_SAFETY_CKT of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_ERROR_INJECTION_TYPE : integer; + attribute C_ERROR_INJECTION_TYPE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_ERROR_INJECTION_TYPE_AXIS : integer; + attribute C_ERROR_INJECTION_TYPE_AXIS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_ERROR_INJECTION_TYPE_RACH : integer; + attribute C_ERROR_INJECTION_TYPE_RACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_ERROR_INJECTION_TYPE_RDCH : integer; + attribute C_ERROR_INJECTION_TYPE_RDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_ERROR_INJECTION_TYPE_WACH : integer; + attribute C_ERROR_INJECTION_TYPE_WACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_ERROR_INJECTION_TYPE_WDCH : integer; + attribute C_ERROR_INJECTION_TYPE_WDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_ERROR_INJECTION_TYPE_WRCH : integer; + attribute C_ERROR_INJECTION_TYPE_WRCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_FAMILY : string; + attribute C_FAMILY of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is "zynq"; + attribute C_FULL_FLAGS_RST_VAL : integer; + attribute C_FULL_FLAGS_RST_VAL of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_ALMOST_EMPTY : integer; + attribute C_HAS_ALMOST_EMPTY of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_ALMOST_FULL : integer; + attribute C_HAS_ALMOST_FULL of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_AXIS_TDATA : integer; + attribute C_HAS_AXIS_TDATA of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_AXIS_TDEST : integer; + attribute C_HAS_AXIS_TDEST of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_AXIS_TID : integer; + attribute C_HAS_AXIS_TID of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_AXIS_TKEEP : integer; + attribute C_HAS_AXIS_TKEEP of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_AXIS_TLAST : integer; + attribute C_HAS_AXIS_TLAST of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_AXIS_TREADY : integer; + attribute C_HAS_AXIS_TREADY of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1; + attribute C_HAS_AXIS_TSTRB : integer; + attribute C_HAS_AXIS_TSTRB of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_AXIS_TUSER : integer; + attribute C_HAS_AXIS_TUSER of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_AXI_ARUSER : integer; + attribute C_HAS_AXI_ARUSER of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_AXI_AWUSER : integer; + attribute C_HAS_AXI_AWUSER of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_AXI_BUSER : integer; + attribute C_HAS_AXI_BUSER of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_AXI_ID : integer; + attribute C_HAS_AXI_ID of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_AXI_RD_CHANNEL : integer; + attribute C_HAS_AXI_RD_CHANNEL of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_AXI_RUSER : integer; + attribute C_HAS_AXI_RUSER of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_AXI_WR_CHANNEL : integer; + attribute C_HAS_AXI_WR_CHANNEL of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_AXI_WUSER : integer; + attribute C_HAS_AXI_WUSER of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_BACKUP : integer; + attribute C_HAS_BACKUP of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_DATA_COUNT : integer; + attribute C_HAS_DATA_COUNT of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_DATA_COUNTS_AXIS : integer; + attribute C_HAS_DATA_COUNTS_AXIS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_DATA_COUNTS_RACH : integer; + attribute C_HAS_DATA_COUNTS_RACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_DATA_COUNTS_RDCH : integer; + attribute C_HAS_DATA_COUNTS_RDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_DATA_COUNTS_WACH : integer; + attribute C_HAS_DATA_COUNTS_WACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_DATA_COUNTS_WDCH : integer; + attribute C_HAS_DATA_COUNTS_WDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_DATA_COUNTS_WRCH : integer; + attribute C_HAS_DATA_COUNTS_WRCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_INT_CLK : integer; + attribute C_HAS_INT_CLK of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_MASTER_CE : integer; + attribute C_HAS_MASTER_CE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_MEMINIT_FILE : integer; + attribute C_HAS_MEMINIT_FILE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_OVERFLOW : integer; + attribute C_HAS_OVERFLOW of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_PROG_FLAGS_AXIS : integer; + attribute C_HAS_PROG_FLAGS_AXIS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_PROG_FLAGS_RACH : integer; + attribute C_HAS_PROG_FLAGS_RACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_PROG_FLAGS_RDCH : integer; + attribute C_HAS_PROG_FLAGS_RDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_PROG_FLAGS_WACH : integer; + attribute C_HAS_PROG_FLAGS_WACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_PROG_FLAGS_WDCH : integer; + attribute C_HAS_PROG_FLAGS_WDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_PROG_FLAGS_WRCH : integer; + attribute C_HAS_PROG_FLAGS_WRCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_RD_DATA_COUNT : integer; + attribute C_HAS_RD_DATA_COUNT of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_RD_RST : integer; + attribute C_HAS_RD_RST of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_RST : integer; + attribute C_HAS_RST of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1; + attribute C_HAS_SLAVE_CE : integer; + attribute C_HAS_SLAVE_CE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_SRST : integer; + attribute C_HAS_SRST of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_UNDERFLOW : integer; + attribute C_HAS_UNDERFLOW of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_VALID : integer; + attribute C_HAS_VALID of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_WR_ACK : integer; + attribute C_HAS_WR_ACK of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_WR_DATA_COUNT : integer; + attribute C_HAS_WR_DATA_COUNT of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_HAS_WR_RST : integer; + attribute C_HAS_WR_RST of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_IMPLEMENTATION_TYPE : integer; + attribute C_IMPLEMENTATION_TYPE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_IMPLEMENTATION_TYPE_AXIS : integer; + attribute C_IMPLEMENTATION_TYPE_AXIS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1; + attribute C_IMPLEMENTATION_TYPE_RACH : integer; + attribute C_IMPLEMENTATION_TYPE_RACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1; + attribute C_IMPLEMENTATION_TYPE_RDCH : integer; + attribute C_IMPLEMENTATION_TYPE_RDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1; + attribute C_IMPLEMENTATION_TYPE_WACH : integer; + attribute C_IMPLEMENTATION_TYPE_WACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1; + attribute C_IMPLEMENTATION_TYPE_WDCH : integer; + attribute C_IMPLEMENTATION_TYPE_WDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1; + attribute C_IMPLEMENTATION_TYPE_WRCH : integer; + attribute C_IMPLEMENTATION_TYPE_WRCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1; + attribute C_INIT_WR_PNTR_VAL : integer; + attribute C_INIT_WR_PNTR_VAL of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_INTERFACE_TYPE : integer; + attribute C_INTERFACE_TYPE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_MEMORY_TYPE : integer; + attribute C_MEMORY_TYPE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 2; + attribute C_MIF_FILE_NAME : string; + attribute C_MIF_FILE_NAME of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is "BlankString"; + attribute C_MSGON_VAL : integer; + attribute C_MSGON_VAL of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1; + attribute C_OPTIMIZATION_MODE : integer; + attribute C_OPTIMIZATION_MODE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_OVERFLOW_LOW : integer; + attribute C_OVERFLOW_LOW of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_POWER_SAVING_MODE : integer; + attribute C_POWER_SAVING_MODE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_PRELOAD_LATENCY : integer; + attribute C_PRELOAD_LATENCY of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_PRELOAD_REGS : integer; + attribute C_PRELOAD_REGS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1; + attribute C_PRIM_FIFO_TYPE : string; + attribute C_PRIM_FIFO_TYPE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is "512x36"; + attribute C_PRIM_FIFO_TYPE_AXIS : string; + attribute C_PRIM_FIFO_TYPE_AXIS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is "512x36"; + attribute C_PRIM_FIFO_TYPE_RACH : string; + attribute C_PRIM_FIFO_TYPE_RACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is "512x36"; + attribute C_PRIM_FIFO_TYPE_RDCH : string; + attribute C_PRIM_FIFO_TYPE_RDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is "512x36"; + attribute C_PRIM_FIFO_TYPE_WACH : string; + attribute C_PRIM_FIFO_TYPE_WACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is "512x36"; + attribute C_PRIM_FIFO_TYPE_WDCH : string; + attribute C_PRIM_FIFO_TYPE_WDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is "512x36"; + attribute C_PRIM_FIFO_TYPE_WRCH : string; + attribute C_PRIM_FIFO_TYPE_WRCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is "512x36"; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 4; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1022; + attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer; + attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 5; + attribute C_PROG_EMPTY_TYPE : integer; + attribute C_PROG_EMPTY_TYPE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_PROG_EMPTY_TYPE_AXIS : integer; + attribute C_PROG_EMPTY_TYPE_AXIS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_PROG_EMPTY_TYPE_RACH : integer; + attribute C_PROG_EMPTY_TYPE_RACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_PROG_EMPTY_TYPE_RDCH : integer; + attribute C_PROG_EMPTY_TYPE_RDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_PROG_EMPTY_TYPE_WACH : integer; + attribute C_PROG_EMPTY_TYPE_WACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_PROG_EMPTY_TYPE_WDCH : integer; + attribute C_PROG_EMPTY_TYPE_WDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_PROG_EMPTY_TYPE_WRCH : integer; + attribute C_PROG_EMPTY_TYPE_WRCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 31; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1023; + attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer; + attribute C_PROG_FULL_THRESH_NEGATE_VAL of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 30; + attribute C_PROG_FULL_TYPE : integer; + attribute C_PROG_FULL_TYPE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_PROG_FULL_TYPE_AXIS : integer; + attribute C_PROG_FULL_TYPE_AXIS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_PROG_FULL_TYPE_RACH : integer; + attribute C_PROG_FULL_TYPE_RACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_PROG_FULL_TYPE_RDCH : integer; + attribute C_PROG_FULL_TYPE_RDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_PROG_FULL_TYPE_WACH : integer; + attribute C_PROG_FULL_TYPE_WACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_PROG_FULL_TYPE_WDCH : integer; + attribute C_PROG_FULL_TYPE_WDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_PROG_FULL_TYPE_WRCH : integer; + attribute C_PROG_FULL_TYPE_WRCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_RACH_TYPE : integer; + attribute C_RACH_TYPE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_RDCH_TYPE : integer; + attribute C_RDCH_TYPE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_RD_DATA_COUNT_WIDTH : integer; + attribute C_RD_DATA_COUNT_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 6; + attribute C_RD_DEPTH : integer; + attribute C_RD_DEPTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 32; + attribute C_RD_FREQ : integer; + attribute C_RD_FREQ of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1; + attribute C_RD_PNTR_WIDTH : integer; + attribute C_RD_PNTR_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 5; + attribute C_REG_SLICE_MODE_AXIS : integer; + attribute C_REG_SLICE_MODE_AXIS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_REG_SLICE_MODE_RACH : integer; + attribute C_REG_SLICE_MODE_RACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_REG_SLICE_MODE_RDCH : integer; + attribute C_REG_SLICE_MODE_RDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_REG_SLICE_MODE_WACH : integer; + attribute C_REG_SLICE_MODE_WACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_REG_SLICE_MODE_WDCH : integer; + attribute C_REG_SLICE_MODE_WDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_REG_SLICE_MODE_WRCH : integer; + attribute C_REG_SLICE_MODE_WRCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_SELECT_XPM : integer; + attribute C_SELECT_XPM of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_SYNCHRONIZER_STAGE : integer; + attribute C_SYNCHRONIZER_STAGE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 3; + attribute C_UNDERFLOW_LOW : integer; + attribute C_UNDERFLOW_LOW of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_USE_COMMON_OVERFLOW : integer; + attribute C_USE_COMMON_OVERFLOW of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_USE_COMMON_UNDERFLOW : integer; + attribute C_USE_COMMON_UNDERFLOW of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_USE_DEFAULT_SETTINGS : integer; + attribute C_USE_DEFAULT_SETTINGS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_USE_DOUT_RST : integer; + attribute C_USE_DOUT_RST of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_USE_ECC : integer; + attribute C_USE_ECC of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_USE_ECC_AXIS : integer; + attribute C_USE_ECC_AXIS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_USE_ECC_RACH : integer; + attribute C_USE_ECC_RACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_USE_ECC_RDCH : integer; + attribute C_USE_ECC_RDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_USE_ECC_WACH : integer; + attribute C_USE_ECC_WACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_USE_ECC_WDCH : integer; + attribute C_USE_ECC_WDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_USE_ECC_WRCH : integer; + attribute C_USE_ECC_WRCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_USE_EMBEDDED_REG : integer; + attribute C_USE_EMBEDDED_REG of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_USE_FIFO16_FLAGS : integer; + attribute C_USE_FIFO16_FLAGS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_USE_FWFT_DATA_COUNT : integer; + attribute C_USE_FWFT_DATA_COUNT of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1; + attribute C_USE_PIPELINE_REG : integer; + attribute C_USE_PIPELINE_REG of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_VALID_LOW : integer; + attribute C_VALID_LOW of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_WACH_TYPE : integer; + attribute C_WACH_TYPE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_WDCH_TYPE : integer; + attribute C_WDCH_TYPE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_WRCH_TYPE : integer; + attribute C_WRCH_TYPE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_WR_ACK_LOW : integer; + attribute C_WR_ACK_LOW of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 0; + attribute C_WR_DATA_COUNT_WIDTH : integer; + attribute C_WR_DATA_COUNT_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 6; + attribute C_WR_DEPTH : integer; + attribute C_WR_DEPTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 32; + attribute C_WR_DEPTH_AXIS : integer; + attribute C_WR_DEPTH_AXIS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1024; + attribute C_WR_DEPTH_RACH : integer; + attribute C_WR_DEPTH_RACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 16; + attribute C_WR_DEPTH_RDCH : integer; + attribute C_WR_DEPTH_RDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1024; + attribute C_WR_DEPTH_WACH : integer; + attribute C_WR_DEPTH_WACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 16; + attribute C_WR_DEPTH_WDCH : integer; + attribute C_WR_DEPTH_WDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1024; + attribute C_WR_DEPTH_WRCH : integer; + attribute C_WR_DEPTH_WRCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 16; + attribute C_WR_FREQ : integer; + attribute C_WR_FREQ of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1; + attribute C_WR_PNTR_WIDTH : integer; + attribute C_WR_PNTR_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 5; + attribute C_WR_PNTR_WIDTH_AXIS : integer; + attribute C_WR_PNTR_WIDTH_AXIS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 10; + attribute C_WR_PNTR_WIDTH_RACH : integer; + attribute C_WR_PNTR_WIDTH_RACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 4; + attribute C_WR_PNTR_WIDTH_RDCH : integer; + attribute C_WR_PNTR_WIDTH_RDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 10; + attribute C_WR_PNTR_WIDTH_WACH : integer; + attribute C_WR_PNTR_WIDTH_WACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 4; + attribute C_WR_PNTR_WIDTH_WDCH : integer; + attribute C_WR_PNTR_WIDTH_WDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 10; + attribute C_WR_PNTR_WIDTH_WRCH : integer; + attribute C_WR_PNTR_WIDTH_WRCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 4; + attribute C_WR_RESPONSE_LATENCY : integer; + attribute C_WR_RESPONSE_LATENCY of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is 1; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ : entity is "fifo_generator_v13_1_3"; +end \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\; + +architecture STRUCTURE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ is + signal \\ : STD_LOGIC; +begin + almost_empty <= \\; + almost_full <= \\; + axi_ar_data_count(4) <= \\; + axi_ar_data_count(3) <= \\; + axi_ar_data_count(2) <= \\; + axi_ar_data_count(1) <= \\; + axi_ar_data_count(0) <= \\; + axi_ar_dbiterr <= \\; + axi_ar_overflow <= \\; + axi_ar_prog_empty <= \\; + axi_ar_prog_full <= \\; + axi_ar_rd_data_count(4) <= \\; + axi_ar_rd_data_count(3) <= \\; + axi_ar_rd_data_count(2) <= \\; + axi_ar_rd_data_count(1) <= \\; + axi_ar_rd_data_count(0) <= \\; + axi_ar_sbiterr <= \\; + axi_ar_underflow <= \\; + axi_ar_wr_data_count(4) <= \\; + axi_ar_wr_data_count(3) <= \\; + axi_ar_wr_data_count(2) <= \\; + axi_ar_wr_data_count(1) <= \\; + axi_ar_wr_data_count(0) <= \\; + axi_aw_data_count(4) <= \\; + axi_aw_data_count(3) <= \\; + axi_aw_data_count(2) <= \\; + axi_aw_data_count(1) <= \\; + axi_aw_data_count(0) <= \\; + axi_aw_dbiterr <= \\; + axi_aw_overflow <= \\; + axi_aw_prog_empty <= \\; + axi_aw_prog_full <= \\; + axi_aw_rd_data_count(4) <= \\; + axi_aw_rd_data_count(3) <= \\; + axi_aw_rd_data_count(2) <= \\; + axi_aw_rd_data_count(1) <= \\; + axi_aw_rd_data_count(0) <= \\; + axi_aw_sbiterr <= \\; + axi_aw_underflow <= \\; + axi_aw_wr_data_count(4) <= \\; + axi_aw_wr_data_count(3) <= \\; + axi_aw_wr_data_count(2) <= \\; + axi_aw_wr_data_count(1) <= \\; + axi_aw_wr_data_count(0) <= \\; + axi_b_data_count(4) <= \\; + axi_b_data_count(3) <= \\; + axi_b_data_count(2) <= \\; + axi_b_data_count(1) <= \\; + axi_b_data_count(0) <= \\; + axi_b_dbiterr <= \\; + axi_b_overflow <= \\; + axi_b_prog_empty <= \\; + axi_b_prog_full <= \\; + axi_b_rd_data_count(4) <= \\; + axi_b_rd_data_count(3) <= \\; + axi_b_rd_data_count(2) <= \\; + axi_b_rd_data_count(1) <= \\; + axi_b_rd_data_count(0) <= \\; + axi_b_sbiterr <= \\; + axi_b_underflow <= \\; + axi_b_wr_data_count(4) <= \\; + axi_b_wr_data_count(3) <= \\; + axi_b_wr_data_count(2) <= \\; + axi_b_wr_data_count(1) <= \\; + axi_b_wr_data_count(0) <= \\; + axi_r_data_count(10) <= \\; + axi_r_data_count(9) <= \\; + axi_r_data_count(8) <= \\; + axi_r_data_count(7) <= \\; + axi_r_data_count(6) <= \\; + axi_r_data_count(5) <= \\; + axi_r_data_count(4) <= \\; + axi_r_data_count(3) <= \\; + axi_r_data_count(2) <= \\; + axi_r_data_count(1) <= \\; + axi_r_data_count(0) <= \\; + axi_r_dbiterr <= \\; + axi_r_overflow <= \\; + axi_r_prog_empty <= \\; + axi_r_prog_full <= \\; + axi_r_rd_data_count(10) <= \\; + axi_r_rd_data_count(9) <= \\; + axi_r_rd_data_count(8) <= \\; + axi_r_rd_data_count(7) <= \\; + axi_r_rd_data_count(6) <= \\; + axi_r_rd_data_count(5) <= \\; + axi_r_rd_data_count(4) <= \\; + axi_r_rd_data_count(3) <= \\; + axi_r_rd_data_count(2) <= \\; + axi_r_rd_data_count(1) <= \\; + axi_r_rd_data_count(0) <= \\; + axi_r_sbiterr <= \\; + axi_r_underflow <= \\; + axi_r_wr_data_count(10) <= \\; + axi_r_wr_data_count(9) <= \\; + axi_r_wr_data_count(8) <= \\; + axi_r_wr_data_count(7) <= \\; + axi_r_wr_data_count(6) <= \\; + axi_r_wr_data_count(5) <= \\; + axi_r_wr_data_count(4) <= \\; + axi_r_wr_data_count(3) <= \\; + axi_r_wr_data_count(2) <= \\; + axi_r_wr_data_count(1) <= \\; + axi_r_wr_data_count(0) <= \\; + axi_w_data_count(10) <= \\; + axi_w_data_count(9) <= \\; + axi_w_data_count(8) <= \\; + axi_w_data_count(7) <= \\; + axi_w_data_count(6) <= \\; + axi_w_data_count(5) <= \\; + axi_w_data_count(4) <= \\; + axi_w_data_count(3) <= \\; + axi_w_data_count(2) <= \\; + axi_w_data_count(1) <= \\; + axi_w_data_count(0) <= \\; + axi_w_dbiterr <= \\; + axi_w_overflow <= \\; + axi_w_prog_empty <= \\; + axi_w_prog_full <= \\; + axi_w_rd_data_count(10) <= \\; + axi_w_rd_data_count(9) <= \\; + axi_w_rd_data_count(8) <= \\; + axi_w_rd_data_count(7) <= \\; + axi_w_rd_data_count(6) <= \\; + axi_w_rd_data_count(5) <= \\; + axi_w_rd_data_count(4) <= \\; + axi_w_rd_data_count(3) <= \\; + axi_w_rd_data_count(2) <= \\; + axi_w_rd_data_count(1) <= \\; + axi_w_rd_data_count(0) <= \\; + axi_w_sbiterr <= \\; + axi_w_underflow <= \\; + axi_w_wr_data_count(10) <= \\; + axi_w_wr_data_count(9) <= \\; + axi_w_wr_data_count(8) <= \\; + axi_w_wr_data_count(7) <= \\; + axi_w_wr_data_count(6) <= \\; + axi_w_wr_data_count(5) <= \\; + axi_w_wr_data_count(4) <= \\; + axi_w_wr_data_count(3) <= \\; + axi_w_wr_data_count(2) <= \\; + axi_w_wr_data_count(1) <= \\; + axi_w_wr_data_count(0) <= \\; + axis_data_count(10) <= \\; + axis_data_count(9) <= \\; + axis_data_count(8) <= \\; + axis_data_count(7) <= \\; + axis_data_count(6) <= \\; + axis_data_count(5) <= \\; + axis_data_count(4) <= \\; + axis_data_count(3) <= \\; + axis_data_count(2) <= \\; + axis_data_count(1) <= \\; + axis_data_count(0) <= \\; + axis_dbiterr <= \\; + axis_overflow <= \\; + axis_prog_empty <= \\; + axis_prog_full <= \\; + axis_rd_data_count(10) <= \\; + axis_rd_data_count(9) <= \\; + axis_rd_data_count(8) <= \\; + axis_rd_data_count(7) <= \\; + axis_rd_data_count(6) <= \\; + axis_rd_data_count(5) <= \\; + axis_rd_data_count(4) <= \\; + axis_rd_data_count(3) <= \\; + axis_rd_data_count(2) <= \\; + axis_rd_data_count(1) <= \\; + axis_rd_data_count(0) <= \\; + axis_sbiterr <= \\; + axis_underflow <= \\; + axis_wr_data_count(10) <= \\; + axis_wr_data_count(9) <= \\; + axis_wr_data_count(8) <= \\; + axis_wr_data_count(7) <= \\; + axis_wr_data_count(6) <= \\; + axis_wr_data_count(5) <= \\; + axis_wr_data_count(4) <= \\; + axis_wr_data_count(3) <= \\; + axis_wr_data_count(2) <= \\; + axis_wr_data_count(1) <= \\; + axis_wr_data_count(0) <= \\; + data_count(5) <= \\; + data_count(4) <= \\; + data_count(3) <= \\; + data_count(2) <= \\; + data_count(1) <= \\; + data_count(0) <= \\; + dbiterr <= \\; + m_axi_araddr(31) <= \\; + m_axi_araddr(30) <= \\; + m_axi_araddr(29) <= \\; + m_axi_araddr(28) <= \\; + m_axi_araddr(27) <= \\; + m_axi_araddr(26) <= \\; + m_axi_araddr(25) <= \\; + m_axi_araddr(24) <= \\; + m_axi_araddr(23) <= \\; + m_axi_araddr(22) <= \\; + m_axi_araddr(21) <= \\; + m_axi_araddr(20) <= \\; + m_axi_araddr(19) <= \\; + m_axi_araddr(18) <= \\; + m_axi_araddr(17) <= \\; + m_axi_araddr(16) <= \\; + m_axi_araddr(15) <= \\; + m_axi_araddr(14) <= \\; + m_axi_araddr(13) <= \\; + m_axi_araddr(12) <= \\; + m_axi_araddr(11) <= \\; + m_axi_araddr(10) <= \\; + m_axi_araddr(9) <= \\; + m_axi_araddr(8) <= \\; + m_axi_araddr(7) <= \\; + m_axi_araddr(6) <= \\; + m_axi_araddr(5) <= \\; + m_axi_araddr(4) <= \\; + m_axi_araddr(3) <= \\; + m_axi_araddr(2) <= \\; + m_axi_araddr(1) <= \\; + m_axi_araddr(0) <= \\; + m_axi_arburst(1) <= \\; + m_axi_arburst(0) <= \\; + m_axi_arcache(3) <= \\; + m_axi_arcache(2) <= \\; + m_axi_arcache(1) <= \\; + m_axi_arcache(0) <= \\; + m_axi_arid(3) <= \\; + m_axi_arid(2) <= \\; + m_axi_arid(1) <= \\; + m_axi_arid(0) <= \\; + m_axi_arlen(7) <= \\; + m_axi_arlen(6) <= \\; + m_axi_arlen(5) <= \\; + m_axi_arlen(4) <= \\; + m_axi_arlen(3) <= \\; + m_axi_arlen(2) <= \\; + m_axi_arlen(1) <= \\; + m_axi_arlen(0) <= \\; + m_axi_arlock(1) <= \\; + m_axi_arlock(0) <= \\; + m_axi_arprot(2) <= \\; + m_axi_arprot(1) <= \\; + m_axi_arprot(0) <= \\; + m_axi_arqos(3) <= \\; + m_axi_arqos(2) <= \\; + m_axi_arqos(1) <= \\; + m_axi_arqos(0) <= \\; + m_axi_arregion(3) <= \\; + m_axi_arregion(2) <= \\; + m_axi_arregion(1) <= \\; + m_axi_arregion(0) <= \\; + m_axi_arsize(2) <= \\; + m_axi_arsize(1) <= \\; + m_axi_arsize(0) <= \\; + m_axi_aruser(0) <= \\; + m_axi_arvalid <= \\; + m_axi_awaddr(31) <= \\; + m_axi_awaddr(30) <= \\; + m_axi_awaddr(29) <= \\; + m_axi_awaddr(28) <= \\; + m_axi_awaddr(27) <= \\; + m_axi_awaddr(26) <= \\; + m_axi_awaddr(25) <= \\; + m_axi_awaddr(24) <= \\; + m_axi_awaddr(23) <= \\; + m_axi_awaddr(22) <= \\; + m_axi_awaddr(21) <= \\; + m_axi_awaddr(20) <= \\; + m_axi_awaddr(19) <= \\; + m_axi_awaddr(18) <= \\; + m_axi_awaddr(17) <= \\; + m_axi_awaddr(16) <= \\; + m_axi_awaddr(15) <= \\; + m_axi_awaddr(14) <= \\; + m_axi_awaddr(13) <= \\; + m_axi_awaddr(12) <= \\; + m_axi_awaddr(11) <= \\; + m_axi_awaddr(10) <= \\; + m_axi_awaddr(9) <= \\; + m_axi_awaddr(8) <= \\; + m_axi_awaddr(7) <= \\; + m_axi_awaddr(6) <= \\; + m_axi_awaddr(5) <= \\; + m_axi_awaddr(4) <= \\; + m_axi_awaddr(3) <= \\; + m_axi_awaddr(2) <= \\; + m_axi_awaddr(1) <= \\; + m_axi_awaddr(0) <= \\; + m_axi_awburst(1) <= \\; + m_axi_awburst(0) <= \\; + m_axi_awcache(3) <= \\; + m_axi_awcache(2) <= \\; + m_axi_awcache(1) <= \\; + m_axi_awcache(0) <= \\; + m_axi_awid(3) <= \\; + m_axi_awid(2) <= \\; + m_axi_awid(1) <= \\; + m_axi_awid(0) <= \\; + m_axi_awlen(7) <= \\; + m_axi_awlen(6) <= \\; + m_axi_awlen(5) <= \\; + m_axi_awlen(4) <= \\; + m_axi_awlen(3) <= \\; + m_axi_awlen(2) <= \\; + m_axi_awlen(1) <= \\; + m_axi_awlen(0) <= \\; + m_axi_awlock(1) <= \\; + m_axi_awlock(0) <= \\; + m_axi_awprot(2) <= \\; + m_axi_awprot(1) <= \\; + m_axi_awprot(0) <= \\; + m_axi_awqos(3) <= \\; + m_axi_awqos(2) <= \\; + m_axi_awqos(1) <= \\; + m_axi_awqos(0) <= \\; + m_axi_awregion(3) <= \\; + m_axi_awregion(2) <= \\; + m_axi_awregion(1) <= \\; + m_axi_awregion(0) <= \\; + m_axi_awsize(2) <= \\; + m_axi_awsize(1) <= \\; + m_axi_awsize(0) <= \\; + m_axi_awuser(0) <= \\; + m_axi_awvalid <= \\; + m_axi_bready <= \\; + m_axi_rready <= \\; + m_axi_wdata(63) <= \\; + m_axi_wdata(62) <= \\; + m_axi_wdata(61) <= \\; + m_axi_wdata(60) <= \\; + m_axi_wdata(59) <= \\; + m_axi_wdata(58) <= \\; + m_axi_wdata(57) <= \\; + m_axi_wdata(56) <= \\; + m_axi_wdata(55) <= \\; + m_axi_wdata(54) <= \\; + m_axi_wdata(53) <= \\; + m_axi_wdata(52) <= \\; + m_axi_wdata(51) <= \\; + m_axi_wdata(50) <= \\; + m_axi_wdata(49) <= \\; + m_axi_wdata(48) <= \\; + m_axi_wdata(47) <= \\; + m_axi_wdata(46) <= \\; + m_axi_wdata(45) <= \\; + m_axi_wdata(44) <= \\; + m_axi_wdata(43) <= \\; + m_axi_wdata(42) <= \\; + m_axi_wdata(41) <= \\; + m_axi_wdata(40) <= \\; + m_axi_wdata(39) <= \\; + m_axi_wdata(38) <= \\; + m_axi_wdata(37) <= \\; + m_axi_wdata(36) <= \\; + m_axi_wdata(35) <= \\; + m_axi_wdata(34) <= \\; + m_axi_wdata(33) <= \\; + m_axi_wdata(32) <= \\; + m_axi_wdata(31) <= \\; + m_axi_wdata(30) <= \\; + m_axi_wdata(29) <= \\; + m_axi_wdata(28) <= \\; + m_axi_wdata(27) <= \\; + m_axi_wdata(26) <= \\; + m_axi_wdata(25) <= \\; + m_axi_wdata(24) <= \\; + m_axi_wdata(23) <= \\; + m_axi_wdata(22) <= \\; + m_axi_wdata(21) <= \\; + m_axi_wdata(20) <= \\; + m_axi_wdata(19) <= \\; + m_axi_wdata(18) <= \\; + m_axi_wdata(17) <= \\; + m_axi_wdata(16) <= \\; + m_axi_wdata(15) <= \\; + m_axi_wdata(14) <= \\; + m_axi_wdata(13) <= \\; + m_axi_wdata(12) <= \\; + m_axi_wdata(11) <= \\; + m_axi_wdata(10) <= \\; + m_axi_wdata(9) <= \\; + m_axi_wdata(8) <= \\; + m_axi_wdata(7) <= \\; + m_axi_wdata(6) <= \\; + m_axi_wdata(5) <= \\; + m_axi_wdata(4) <= \\; + m_axi_wdata(3) <= \\; + m_axi_wdata(2) <= \\; + m_axi_wdata(1) <= \\; + m_axi_wdata(0) <= \\; + m_axi_wid(3) <= \\; + m_axi_wid(2) <= \\; + m_axi_wid(1) <= \\; + m_axi_wid(0) <= \\; + m_axi_wlast <= \\; + m_axi_wstrb(7) <= \\; + m_axi_wstrb(6) <= \\; + m_axi_wstrb(5) <= \\; + m_axi_wstrb(4) <= \\; + m_axi_wstrb(3) <= \\; + m_axi_wstrb(2) <= \\; + m_axi_wstrb(1) <= \\; + m_axi_wstrb(0) <= \\; + m_axi_wuser(0) <= \\; + m_axi_wvalid <= \\; + m_axis_tdata(63) <= \\; + m_axis_tdata(62) <= \\; + m_axis_tdata(61) <= \\; + m_axis_tdata(60) <= \\; + m_axis_tdata(59) <= \\; + m_axis_tdata(58) <= \\; + m_axis_tdata(57) <= \\; + m_axis_tdata(56) <= \\; + m_axis_tdata(55) <= \\; + m_axis_tdata(54) <= \\; + m_axis_tdata(53) <= \\; + m_axis_tdata(52) <= \\; + m_axis_tdata(51) <= \\; + m_axis_tdata(50) <= \\; + m_axis_tdata(49) <= \\; + m_axis_tdata(48) <= \\; + m_axis_tdata(47) <= \\; + m_axis_tdata(46) <= \\; + m_axis_tdata(45) <= \\; + m_axis_tdata(44) <= \\; + m_axis_tdata(43) <= \\; + m_axis_tdata(42) <= \\; + m_axis_tdata(41) <= \\; + m_axis_tdata(40) <= \\; + m_axis_tdata(39) <= \\; + m_axis_tdata(38) <= \\; + m_axis_tdata(37) <= \\; + m_axis_tdata(36) <= \\; + m_axis_tdata(35) <= \\; + m_axis_tdata(34) <= \\; + m_axis_tdata(33) <= \\; + m_axis_tdata(32) <= \\; + m_axis_tdata(31) <= \\; + m_axis_tdata(30) <= \\; + m_axis_tdata(29) <= \\; + m_axis_tdata(28) <= \\; + m_axis_tdata(27) <= \\; + m_axis_tdata(26) <= \\; + m_axis_tdata(25) <= \\; + m_axis_tdata(24) <= \\; + m_axis_tdata(23) <= \\; + m_axis_tdata(22) <= \\; + m_axis_tdata(21) <= \\; + m_axis_tdata(20) <= \\; + m_axis_tdata(19) <= \\; + m_axis_tdata(18) <= \\; + m_axis_tdata(17) <= \\; + m_axis_tdata(16) <= \\; + m_axis_tdata(15) <= \\; + m_axis_tdata(14) <= \\; + m_axis_tdata(13) <= \\; + m_axis_tdata(12) <= \\; + m_axis_tdata(11) <= \\; + m_axis_tdata(10) <= \\; + m_axis_tdata(9) <= \\; + m_axis_tdata(8) <= \\; + m_axis_tdata(7) <= \\; + m_axis_tdata(6) <= \\; + m_axis_tdata(5) <= \\; + m_axis_tdata(4) <= \\; + m_axis_tdata(3) <= \\; + m_axis_tdata(2) <= \\; + m_axis_tdata(1) <= \\; + m_axis_tdata(0) <= \\; + m_axis_tdest(3) <= \\; + m_axis_tdest(2) <= \\; + m_axis_tdest(1) <= \\; + m_axis_tdest(0) <= \\; + m_axis_tid(7) <= \\; + m_axis_tid(6) <= \\; + m_axis_tid(5) <= \\; + m_axis_tid(4) <= \\; + m_axis_tid(3) <= \\; + m_axis_tid(2) <= \\; + m_axis_tid(1) <= \\; + m_axis_tid(0) <= \\; + m_axis_tkeep(3) <= \\; + m_axis_tkeep(2) <= \\; + m_axis_tkeep(1) <= \\; + m_axis_tkeep(0) <= \\; + m_axis_tlast <= \\; + m_axis_tstrb(3) <= \\; + m_axis_tstrb(2) <= \\; + m_axis_tstrb(1) <= \\; + m_axis_tstrb(0) <= \\; + m_axis_tuser(3) <= \\; + m_axis_tuser(2) <= \\; + m_axis_tuser(1) <= \\; + m_axis_tuser(0) <= \\; + m_axis_tvalid <= \\; + overflow <= \\; + prog_empty <= \\; + prog_full <= \\; + rd_data_count(5) <= \\; + rd_data_count(4) <= \\; + rd_data_count(3) <= \\; + rd_data_count(2) <= \\; + rd_data_count(1) <= \\; + rd_data_count(0) <= \\; + rd_rst_busy <= \\; + s_axi_arready <= \\; + s_axi_awready <= \\; + s_axi_bid(3) <= \\; + s_axi_bid(2) <= \\; + s_axi_bid(1) <= \\; + s_axi_bid(0) <= \\; + s_axi_bresp(1) <= \\; + s_axi_bresp(0) <= \\; + s_axi_buser(0) <= \\; + s_axi_bvalid <= \\; + s_axi_rdata(63) <= \\; + s_axi_rdata(62) <= \\; + s_axi_rdata(61) <= \\; + s_axi_rdata(60) <= \\; + s_axi_rdata(59) <= \\; + s_axi_rdata(58) <= \\; + s_axi_rdata(57) <= \\; + s_axi_rdata(56) <= \\; + s_axi_rdata(55) <= \\; + s_axi_rdata(54) <= \\; + s_axi_rdata(53) <= \\; + s_axi_rdata(52) <= \\; + s_axi_rdata(51) <= \\; + s_axi_rdata(50) <= \\; + s_axi_rdata(49) <= \\; + s_axi_rdata(48) <= \\; + s_axi_rdata(47) <= \\; + s_axi_rdata(46) <= \\; + s_axi_rdata(45) <= \\; + s_axi_rdata(44) <= \\; + s_axi_rdata(43) <= \\; + s_axi_rdata(42) <= \\; + s_axi_rdata(41) <= \\; + s_axi_rdata(40) <= \\; + s_axi_rdata(39) <= \\; + s_axi_rdata(38) <= \\; + s_axi_rdata(37) <= \\; + s_axi_rdata(36) <= \\; + s_axi_rdata(35) <= \\; + s_axi_rdata(34) <= \\; + s_axi_rdata(33) <= \\; + s_axi_rdata(32) <= \\; + s_axi_rdata(31) <= \\; + s_axi_rdata(30) <= \\; + s_axi_rdata(29) <= \\; + s_axi_rdata(28) <= \\; + s_axi_rdata(27) <= \\; + s_axi_rdata(26) <= \\; + s_axi_rdata(25) <= \\; + s_axi_rdata(24) <= \\; + s_axi_rdata(23) <= \\; + s_axi_rdata(22) <= \\; + s_axi_rdata(21) <= \\; + s_axi_rdata(20) <= \\; + s_axi_rdata(19) <= \\; + s_axi_rdata(18) <= \\; + s_axi_rdata(17) <= \\; + s_axi_rdata(16) <= \\; + s_axi_rdata(15) <= \\; + s_axi_rdata(14) <= \\; + s_axi_rdata(13) <= \\; + s_axi_rdata(12) <= \\; + s_axi_rdata(11) <= \\; + s_axi_rdata(10) <= \\; + s_axi_rdata(9) <= \\; + s_axi_rdata(8) <= \\; + s_axi_rdata(7) <= \\; + s_axi_rdata(6) <= \\; + s_axi_rdata(5) <= \\; + s_axi_rdata(4) <= \\; + s_axi_rdata(3) <= \\; + s_axi_rdata(2) <= \\; + s_axi_rdata(1) <= \\; + s_axi_rdata(0) <= \\; + s_axi_rid(3) <= \\; + s_axi_rid(2) <= \\; + s_axi_rid(1) <= \\; + s_axi_rid(0) <= \\; + s_axi_rlast <= \\; + s_axi_rresp(1) <= \\; + s_axi_rresp(0) <= \\; + s_axi_ruser(0) <= \\; + s_axi_rvalid <= \\; + s_axi_wready <= \\; + s_axis_tready <= \\; + sbiterr <= \\; + underflow <= \\; + valid <= \\; + wr_ack <= \\; + wr_data_count(5) <= \\; + wr_data_count(4) <= \\; + wr_data_count(3) <= \\; + wr_data_count(2) <= \\; + wr_data_count(1) <= \\; + wr_data_count(0) <= \\; + wr_rst_busy <= \\; +GND: unisim.vcomponents.GND + port map ( + G => \\ + ); +inst_fifo_gen: entity work.Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3_synth_7 + port map ( + clk => clk, + din(4 downto 0) => din(4 downto 0), + dout(4 downto 0) => dout(4 downto 0), + empty => empty, + full => full, + rd_en => rd_en, + rst => rst, + wr_en => wr_en + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ is + port ( + backup : in STD_LOGIC; + backup_marker : in STD_LOGIC; + clk : in STD_LOGIC; + rst : in STD_LOGIC; + srst : in STD_LOGIC; + wr_clk : in STD_LOGIC; + wr_rst : in STD_LOGIC; + rd_clk : in STD_LOGIC; + rd_rst : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 0 to 0 ); + wr_en : in STD_LOGIC; + rd_en : in STD_LOGIC; + prog_empty_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 ); + prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 ); + prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 ); + prog_full_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 ); + prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 ); + prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 ); + int_clk : in STD_LOGIC; + injectdbiterr : in STD_LOGIC; + injectsbiterr : in STD_LOGIC; + sleep : in STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 0 to 0 ); + full : out STD_LOGIC; + almost_full : out STD_LOGIC; + wr_ack : out STD_LOGIC; + overflow : out STD_LOGIC; empty : out STD_LOGIC; almost_empty : out STD_LOGIC; valid : out STD_LOGIC; @@ -2052,412 +8892,414 @@ entity Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 is axis_prog_empty : out STD_LOGIC ); attribute C_ADD_NGC_CONSTRAINT : integer; - attribute C_ADD_NGC_CONSTRAINT of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_ADD_NGC_CONSTRAINT of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_APPLICATION_TYPE_AXIS : integer; - attribute C_APPLICATION_TYPE_AXIS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_APPLICATION_TYPE_AXIS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_APPLICATION_TYPE_RACH : integer; - attribute C_APPLICATION_TYPE_RACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_APPLICATION_TYPE_RACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_APPLICATION_TYPE_RDCH : integer; - attribute C_APPLICATION_TYPE_RDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_APPLICATION_TYPE_RDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_APPLICATION_TYPE_WACH : integer; - attribute C_APPLICATION_TYPE_WACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_APPLICATION_TYPE_WACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_APPLICATION_TYPE_WDCH : integer; - attribute C_APPLICATION_TYPE_WDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_APPLICATION_TYPE_WDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_APPLICATION_TYPE_WRCH : integer; - attribute C_APPLICATION_TYPE_WRCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_APPLICATION_TYPE_WRCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_AXIS_TDATA_WIDTH : integer; - attribute C_AXIS_TDATA_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 64; + attribute C_AXIS_TDATA_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 64; attribute C_AXIS_TDEST_WIDTH : integer; - attribute C_AXIS_TDEST_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 4; + attribute C_AXIS_TDEST_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 4; attribute C_AXIS_TID_WIDTH : integer; - attribute C_AXIS_TID_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 8; + attribute C_AXIS_TID_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 8; attribute C_AXIS_TKEEP_WIDTH : integer; - attribute C_AXIS_TKEEP_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 4; + attribute C_AXIS_TKEEP_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 4; attribute C_AXIS_TSTRB_WIDTH : integer; - attribute C_AXIS_TSTRB_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 4; + attribute C_AXIS_TSTRB_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 4; attribute C_AXIS_TUSER_WIDTH : integer; - attribute C_AXIS_TUSER_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 4; + attribute C_AXIS_TUSER_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 4; attribute C_AXIS_TYPE : integer; - attribute C_AXIS_TYPE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_AXIS_TYPE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_AXI_ADDR_WIDTH : integer; - attribute C_AXI_ADDR_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 32; + attribute C_AXI_ADDR_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 32; attribute C_AXI_ARUSER_WIDTH : integer; - attribute C_AXI_ARUSER_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_AXI_ARUSER_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1; attribute C_AXI_AWUSER_WIDTH : integer; - attribute C_AXI_AWUSER_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_AXI_AWUSER_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1; attribute C_AXI_BUSER_WIDTH : integer; - attribute C_AXI_BUSER_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_AXI_BUSER_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1; attribute C_AXI_DATA_WIDTH : integer; - attribute C_AXI_DATA_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 64; + attribute C_AXI_DATA_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 64; attribute C_AXI_ID_WIDTH : integer; - attribute C_AXI_ID_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 4; + attribute C_AXI_ID_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 4; attribute C_AXI_LEN_WIDTH : integer; - attribute C_AXI_LEN_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 8; + attribute C_AXI_LEN_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 8; attribute C_AXI_LOCK_WIDTH : integer; - attribute C_AXI_LOCK_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 2; + attribute C_AXI_LOCK_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 2; attribute C_AXI_RUSER_WIDTH : integer; - attribute C_AXI_RUSER_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_AXI_RUSER_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1; attribute C_AXI_TYPE : integer; - attribute C_AXI_TYPE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_AXI_TYPE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_AXI_WUSER_WIDTH : integer; - attribute C_AXI_WUSER_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_AXI_WUSER_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1; attribute C_COMMON_CLOCK : integer; - attribute C_COMMON_CLOCK of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_COMMON_CLOCK of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1; attribute C_COUNT_TYPE : integer; - attribute C_COUNT_TYPE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_COUNT_TYPE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_DATA_COUNT_WIDTH : integer; - attribute C_DATA_COUNT_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 6; + attribute C_DATA_COUNT_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 6; attribute C_DEFAULT_VALUE : string; - attribute C_DEFAULT_VALUE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is "BlankString"; + attribute C_DEFAULT_VALUE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is "BlankString"; attribute C_DIN_WIDTH : integer; - attribute C_DIN_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_DIN_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1; attribute C_DIN_WIDTH_AXIS : integer; - attribute C_DIN_WIDTH_AXIS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_DIN_WIDTH_AXIS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1; attribute C_DIN_WIDTH_RACH : integer; - attribute C_DIN_WIDTH_RACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 32; + attribute C_DIN_WIDTH_RACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 32; attribute C_DIN_WIDTH_RDCH : integer; - attribute C_DIN_WIDTH_RDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 64; + attribute C_DIN_WIDTH_RDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 64; attribute C_DIN_WIDTH_WACH : integer; - attribute C_DIN_WIDTH_WACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 32; + attribute C_DIN_WIDTH_WACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 32; attribute C_DIN_WIDTH_WDCH : integer; - attribute C_DIN_WIDTH_WDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 64; + attribute C_DIN_WIDTH_WDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 64; attribute C_DIN_WIDTH_WRCH : integer; - attribute C_DIN_WIDTH_WRCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 2; + attribute C_DIN_WIDTH_WRCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 2; attribute C_DOUT_RST_VAL : string; - attribute C_DOUT_RST_VAL of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is "0"; + attribute C_DOUT_RST_VAL of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is "0"; attribute C_DOUT_WIDTH : integer; - attribute C_DOUT_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_DOUT_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1; attribute C_ENABLE_RLOCS : integer; - attribute C_ENABLE_RLOCS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_ENABLE_RLOCS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_ENABLE_RST_SYNC : integer; - attribute C_ENABLE_RST_SYNC of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_ENABLE_RST_SYNC of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1; attribute C_EN_SAFETY_CKT : integer; - attribute C_EN_SAFETY_CKT of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_EN_SAFETY_CKT of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_ERROR_INJECTION_TYPE : integer; - attribute C_ERROR_INJECTION_TYPE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_ERROR_INJECTION_TYPE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_ERROR_INJECTION_TYPE_AXIS : integer; - attribute C_ERROR_INJECTION_TYPE_AXIS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_ERROR_INJECTION_TYPE_AXIS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_ERROR_INJECTION_TYPE_RACH : integer; - attribute C_ERROR_INJECTION_TYPE_RACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_ERROR_INJECTION_TYPE_RACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_ERROR_INJECTION_TYPE_RDCH : integer; - attribute C_ERROR_INJECTION_TYPE_RDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_ERROR_INJECTION_TYPE_RDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_ERROR_INJECTION_TYPE_WACH : integer; - attribute C_ERROR_INJECTION_TYPE_WACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_ERROR_INJECTION_TYPE_WACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_ERROR_INJECTION_TYPE_WDCH : integer; - attribute C_ERROR_INJECTION_TYPE_WDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_ERROR_INJECTION_TYPE_WDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_ERROR_INJECTION_TYPE_WRCH : integer; - attribute C_ERROR_INJECTION_TYPE_WRCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_ERROR_INJECTION_TYPE_WRCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_FAMILY : string; - attribute C_FAMILY of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is "zynq"; + attribute C_FAMILY of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is "zynq"; attribute C_FULL_FLAGS_RST_VAL : integer; - attribute C_FULL_FLAGS_RST_VAL of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_FULL_FLAGS_RST_VAL of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_ALMOST_EMPTY : integer; - attribute C_HAS_ALMOST_EMPTY of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_ALMOST_EMPTY of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_ALMOST_FULL : integer; - attribute C_HAS_ALMOST_FULL of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_ALMOST_FULL of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_AXIS_TDATA : integer; - attribute C_HAS_AXIS_TDATA of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXIS_TDATA of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_AXIS_TDEST : integer; - attribute C_HAS_AXIS_TDEST of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXIS_TDEST of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_AXIS_TID : integer; - attribute C_HAS_AXIS_TID of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXIS_TID of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_AXIS_TKEEP : integer; - attribute C_HAS_AXIS_TKEEP of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXIS_TKEEP of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_AXIS_TLAST : integer; - attribute C_HAS_AXIS_TLAST of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXIS_TLAST of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_AXIS_TREADY : integer; - attribute C_HAS_AXIS_TREADY of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_HAS_AXIS_TREADY of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1; attribute C_HAS_AXIS_TSTRB : integer; - attribute C_HAS_AXIS_TSTRB of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXIS_TSTRB of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_AXIS_TUSER : integer; - attribute C_HAS_AXIS_TUSER of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXIS_TUSER of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_AXI_ARUSER : integer; - attribute C_HAS_AXI_ARUSER of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXI_ARUSER of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_AXI_AWUSER : integer; - attribute C_HAS_AXI_AWUSER of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXI_AWUSER of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_AXI_BUSER : integer; - attribute C_HAS_AXI_BUSER of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXI_BUSER of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_AXI_ID : integer; - attribute C_HAS_AXI_ID of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXI_ID of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_AXI_RD_CHANNEL : integer; - attribute C_HAS_AXI_RD_CHANNEL of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXI_RD_CHANNEL of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_AXI_RUSER : integer; - attribute C_HAS_AXI_RUSER of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXI_RUSER of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_AXI_WR_CHANNEL : integer; - attribute C_HAS_AXI_WR_CHANNEL of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXI_WR_CHANNEL of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_AXI_WUSER : integer; - attribute C_HAS_AXI_WUSER of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXI_WUSER of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_BACKUP : integer; - attribute C_HAS_BACKUP of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_BACKUP of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_DATA_COUNT : integer; - attribute C_HAS_DATA_COUNT of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_DATA_COUNT of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_DATA_COUNTS_AXIS : integer; - attribute C_HAS_DATA_COUNTS_AXIS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_DATA_COUNTS_AXIS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_DATA_COUNTS_RACH : integer; - attribute C_HAS_DATA_COUNTS_RACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_DATA_COUNTS_RACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_DATA_COUNTS_RDCH : integer; - attribute C_HAS_DATA_COUNTS_RDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_DATA_COUNTS_RDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_DATA_COUNTS_WACH : integer; - attribute C_HAS_DATA_COUNTS_WACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_DATA_COUNTS_WACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_DATA_COUNTS_WDCH : integer; - attribute C_HAS_DATA_COUNTS_WDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_DATA_COUNTS_WDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_DATA_COUNTS_WRCH : integer; - attribute C_HAS_DATA_COUNTS_WRCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_DATA_COUNTS_WRCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_INT_CLK : integer; - attribute C_HAS_INT_CLK of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_INT_CLK of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_MASTER_CE : integer; - attribute C_HAS_MASTER_CE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_MASTER_CE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_MEMINIT_FILE : integer; - attribute C_HAS_MEMINIT_FILE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_MEMINIT_FILE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_OVERFLOW : integer; - attribute C_HAS_OVERFLOW of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_OVERFLOW of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_PROG_FLAGS_AXIS : integer; - attribute C_HAS_PROG_FLAGS_AXIS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_PROG_FLAGS_AXIS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_PROG_FLAGS_RACH : integer; - attribute C_HAS_PROG_FLAGS_RACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_PROG_FLAGS_RACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_PROG_FLAGS_RDCH : integer; - attribute C_HAS_PROG_FLAGS_RDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_PROG_FLAGS_RDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_PROG_FLAGS_WACH : integer; - attribute C_HAS_PROG_FLAGS_WACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_PROG_FLAGS_WACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_PROG_FLAGS_WDCH : integer; - attribute C_HAS_PROG_FLAGS_WDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_PROG_FLAGS_WDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_PROG_FLAGS_WRCH : integer; - attribute C_HAS_PROG_FLAGS_WRCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_PROG_FLAGS_WRCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_RD_DATA_COUNT : integer; - attribute C_HAS_RD_DATA_COUNT of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_RD_DATA_COUNT of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_RD_RST : integer; - attribute C_HAS_RD_RST of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_RD_RST of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_RST : integer; - attribute C_HAS_RST of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_HAS_RST of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1; attribute C_HAS_SLAVE_CE : integer; - attribute C_HAS_SLAVE_CE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_SLAVE_CE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_SRST : integer; - attribute C_HAS_SRST of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_SRST of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_UNDERFLOW : integer; - attribute C_HAS_UNDERFLOW of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_UNDERFLOW of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_VALID : integer; - attribute C_HAS_VALID of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_VALID of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_WR_ACK : integer; - attribute C_HAS_WR_ACK of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_WR_ACK of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_WR_DATA_COUNT : integer; - attribute C_HAS_WR_DATA_COUNT of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_WR_DATA_COUNT of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_HAS_WR_RST : integer; - attribute C_HAS_WR_RST of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_WR_RST of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_IMPLEMENTATION_TYPE : integer; - attribute C_IMPLEMENTATION_TYPE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_IMPLEMENTATION_TYPE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_IMPLEMENTATION_TYPE_AXIS : integer; - attribute C_IMPLEMENTATION_TYPE_AXIS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_IMPLEMENTATION_TYPE_AXIS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1; attribute C_IMPLEMENTATION_TYPE_RACH : integer; - attribute C_IMPLEMENTATION_TYPE_RACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_IMPLEMENTATION_TYPE_RACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1; attribute C_IMPLEMENTATION_TYPE_RDCH : integer; - attribute C_IMPLEMENTATION_TYPE_RDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_IMPLEMENTATION_TYPE_RDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1; attribute C_IMPLEMENTATION_TYPE_WACH : integer; - attribute C_IMPLEMENTATION_TYPE_WACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_IMPLEMENTATION_TYPE_WACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1; attribute C_IMPLEMENTATION_TYPE_WDCH : integer; - attribute C_IMPLEMENTATION_TYPE_WDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_IMPLEMENTATION_TYPE_WDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1; attribute C_IMPLEMENTATION_TYPE_WRCH : integer; - attribute C_IMPLEMENTATION_TYPE_WRCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_IMPLEMENTATION_TYPE_WRCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1; attribute C_INIT_WR_PNTR_VAL : integer; - attribute C_INIT_WR_PNTR_VAL of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_INIT_WR_PNTR_VAL of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_INTERFACE_TYPE : integer; - attribute C_INTERFACE_TYPE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_INTERFACE_TYPE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_MEMORY_TYPE : integer; - attribute C_MEMORY_TYPE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 2; + attribute C_MEMORY_TYPE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 2; attribute C_MIF_FILE_NAME : string; - attribute C_MIF_FILE_NAME of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is "BlankString"; + attribute C_MIF_FILE_NAME of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is "BlankString"; attribute C_MSGON_VAL : integer; - attribute C_MSGON_VAL of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_MSGON_VAL of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1; attribute C_OPTIMIZATION_MODE : integer; - attribute C_OPTIMIZATION_MODE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_OPTIMIZATION_MODE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_OVERFLOW_LOW : integer; - attribute C_OVERFLOW_LOW of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_OVERFLOW_LOW of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_POWER_SAVING_MODE : integer; - attribute C_POWER_SAVING_MODE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_POWER_SAVING_MODE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_PRELOAD_LATENCY : integer; - attribute C_PRELOAD_LATENCY of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PRELOAD_LATENCY of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_PRELOAD_REGS : integer; - attribute C_PRELOAD_REGS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_PRELOAD_REGS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1; attribute C_PRIM_FIFO_TYPE : string; - attribute C_PRIM_FIFO_TYPE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is "512x36"; + attribute C_PRIM_FIFO_TYPE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is "512x36"; attribute C_PRIM_FIFO_TYPE_AXIS : string; - attribute C_PRIM_FIFO_TYPE_AXIS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is "512x36"; + attribute C_PRIM_FIFO_TYPE_AXIS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is "512x36"; attribute C_PRIM_FIFO_TYPE_RACH : string; - attribute C_PRIM_FIFO_TYPE_RACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is "512x36"; + attribute C_PRIM_FIFO_TYPE_RACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is "512x36"; attribute C_PRIM_FIFO_TYPE_RDCH : string; - attribute C_PRIM_FIFO_TYPE_RDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is "512x36"; + attribute C_PRIM_FIFO_TYPE_RDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is "512x36"; attribute C_PRIM_FIFO_TYPE_WACH : string; - attribute C_PRIM_FIFO_TYPE_WACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is "512x36"; + attribute C_PRIM_FIFO_TYPE_WACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is "512x36"; attribute C_PRIM_FIFO_TYPE_WDCH : string; - attribute C_PRIM_FIFO_TYPE_WDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is "512x36"; + attribute C_PRIM_FIFO_TYPE_WDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is "512x36"; attribute C_PRIM_FIFO_TYPE_WRCH : string; - attribute C_PRIM_FIFO_TYPE_WRCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is "512x36"; + attribute C_PRIM_FIFO_TYPE_WRCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is "512x36"; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 4; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 4; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1022; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1022; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1022; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1022; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1022; attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer; - attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1022; attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer; - attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 5; + attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 5; attribute C_PROG_EMPTY_TYPE : integer; - attribute C_PROG_EMPTY_TYPE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_EMPTY_TYPE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_PROG_EMPTY_TYPE_AXIS : integer; - attribute C_PROG_EMPTY_TYPE_AXIS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_EMPTY_TYPE_AXIS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_PROG_EMPTY_TYPE_RACH : integer; - attribute C_PROG_EMPTY_TYPE_RACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_EMPTY_TYPE_RACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_PROG_EMPTY_TYPE_RDCH : integer; - attribute C_PROG_EMPTY_TYPE_RDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_EMPTY_TYPE_RDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_PROG_EMPTY_TYPE_WACH : integer; - attribute C_PROG_EMPTY_TYPE_WACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_EMPTY_TYPE_WACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_PROG_EMPTY_TYPE_WDCH : integer; - attribute C_PROG_EMPTY_TYPE_WDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_EMPTY_TYPE_WDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_PROG_EMPTY_TYPE_WRCH : integer; - attribute C_PROG_EMPTY_TYPE_WRCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_EMPTY_TYPE_WRCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer; - attribute C_PROG_FULL_THRESH_ASSERT_VAL of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 31; + attribute C_PROG_FULL_THRESH_ASSERT_VAL of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 31; attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer; - attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer; - attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer; - attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer; - attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer; - attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1023; attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer; - attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1023; attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer; - attribute C_PROG_FULL_THRESH_NEGATE_VAL of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 30; + attribute C_PROG_FULL_THRESH_NEGATE_VAL of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 30; attribute C_PROG_FULL_TYPE : integer; - attribute C_PROG_FULL_TYPE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_FULL_TYPE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_PROG_FULL_TYPE_AXIS : integer; - attribute C_PROG_FULL_TYPE_AXIS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_FULL_TYPE_AXIS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_PROG_FULL_TYPE_RACH : integer; - attribute C_PROG_FULL_TYPE_RACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_FULL_TYPE_RACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_PROG_FULL_TYPE_RDCH : integer; - attribute C_PROG_FULL_TYPE_RDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_FULL_TYPE_RDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_PROG_FULL_TYPE_WACH : integer; - attribute C_PROG_FULL_TYPE_WACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_FULL_TYPE_WACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_PROG_FULL_TYPE_WDCH : integer; - attribute C_PROG_FULL_TYPE_WDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_FULL_TYPE_WDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_PROG_FULL_TYPE_WRCH : integer; - attribute C_PROG_FULL_TYPE_WRCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_FULL_TYPE_WRCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_RACH_TYPE : integer; - attribute C_RACH_TYPE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_RACH_TYPE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_RDCH_TYPE : integer; - attribute C_RDCH_TYPE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_RDCH_TYPE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_RD_DATA_COUNT_WIDTH : integer; - attribute C_RD_DATA_COUNT_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 6; + attribute C_RD_DATA_COUNT_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 6; attribute C_RD_DEPTH : integer; - attribute C_RD_DEPTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 32; + attribute C_RD_DEPTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 32; attribute C_RD_FREQ : integer; - attribute C_RD_FREQ of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_RD_FREQ of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1; attribute C_RD_PNTR_WIDTH : integer; - attribute C_RD_PNTR_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 5; + attribute C_RD_PNTR_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 5; attribute C_REG_SLICE_MODE_AXIS : integer; - attribute C_REG_SLICE_MODE_AXIS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_REG_SLICE_MODE_AXIS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_REG_SLICE_MODE_RACH : integer; - attribute C_REG_SLICE_MODE_RACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_REG_SLICE_MODE_RACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_REG_SLICE_MODE_RDCH : integer; - attribute C_REG_SLICE_MODE_RDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_REG_SLICE_MODE_RDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_REG_SLICE_MODE_WACH : integer; - attribute C_REG_SLICE_MODE_WACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_REG_SLICE_MODE_WACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_REG_SLICE_MODE_WDCH : integer; - attribute C_REG_SLICE_MODE_WDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_REG_SLICE_MODE_WDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_REG_SLICE_MODE_WRCH : integer; - attribute C_REG_SLICE_MODE_WRCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_REG_SLICE_MODE_WRCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_SELECT_XPM : integer; - attribute C_SELECT_XPM of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_SELECT_XPM of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_SYNCHRONIZER_STAGE : integer; - attribute C_SYNCHRONIZER_STAGE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 3; + attribute C_SYNCHRONIZER_STAGE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 3; attribute C_UNDERFLOW_LOW : integer; - attribute C_UNDERFLOW_LOW of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_UNDERFLOW_LOW of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_USE_COMMON_OVERFLOW : integer; - attribute C_USE_COMMON_OVERFLOW of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_COMMON_OVERFLOW of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_USE_COMMON_UNDERFLOW : integer; - attribute C_USE_COMMON_UNDERFLOW of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_COMMON_UNDERFLOW of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_USE_DEFAULT_SETTINGS : integer; - attribute C_USE_DEFAULT_SETTINGS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_DEFAULT_SETTINGS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_USE_DOUT_RST : integer; - attribute C_USE_DOUT_RST of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_DOUT_RST of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_USE_ECC : integer; - attribute C_USE_ECC of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_ECC of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_USE_ECC_AXIS : integer; - attribute C_USE_ECC_AXIS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_ECC_AXIS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_USE_ECC_RACH : integer; - attribute C_USE_ECC_RACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_ECC_RACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_USE_ECC_RDCH : integer; - attribute C_USE_ECC_RDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_ECC_RDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_USE_ECC_WACH : integer; - attribute C_USE_ECC_WACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_ECC_WACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_USE_ECC_WDCH : integer; - attribute C_USE_ECC_WDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_ECC_WDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_USE_ECC_WRCH : integer; - attribute C_USE_ECC_WRCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_ECC_WRCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_USE_EMBEDDED_REG : integer; - attribute C_USE_EMBEDDED_REG of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_EMBEDDED_REG of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_USE_FIFO16_FLAGS : integer; - attribute C_USE_FIFO16_FLAGS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_FIFO16_FLAGS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_USE_FWFT_DATA_COUNT : integer; - attribute C_USE_FWFT_DATA_COUNT of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_USE_FWFT_DATA_COUNT of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1; attribute C_USE_PIPELINE_REG : integer; - attribute C_USE_PIPELINE_REG of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_PIPELINE_REG of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_VALID_LOW : integer; - attribute C_VALID_LOW of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_VALID_LOW of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_WACH_TYPE : integer; - attribute C_WACH_TYPE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_WACH_TYPE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_WDCH_TYPE : integer; - attribute C_WDCH_TYPE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_WDCH_TYPE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_WRCH_TYPE : integer; - attribute C_WRCH_TYPE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_WRCH_TYPE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_WR_ACK_LOW : integer; - attribute C_WR_ACK_LOW of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_WR_ACK_LOW of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 0; attribute C_WR_DATA_COUNT_WIDTH : integer; - attribute C_WR_DATA_COUNT_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 6; + attribute C_WR_DATA_COUNT_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 6; attribute C_WR_DEPTH : integer; - attribute C_WR_DEPTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 32; + attribute C_WR_DEPTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 32; attribute C_WR_DEPTH_AXIS : integer; - attribute C_WR_DEPTH_AXIS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1024; + attribute C_WR_DEPTH_AXIS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1024; attribute C_WR_DEPTH_RACH : integer; - attribute C_WR_DEPTH_RACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 16; + attribute C_WR_DEPTH_RACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 16; attribute C_WR_DEPTH_RDCH : integer; - attribute C_WR_DEPTH_RDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1024; + attribute C_WR_DEPTH_RDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1024; attribute C_WR_DEPTH_WACH : integer; - attribute C_WR_DEPTH_WACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 16; + attribute C_WR_DEPTH_WACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 16; attribute C_WR_DEPTH_WDCH : integer; - attribute C_WR_DEPTH_WDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1024; + attribute C_WR_DEPTH_WDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1024; attribute C_WR_DEPTH_WRCH : integer; - attribute C_WR_DEPTH_WRCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 16; + attribute C_WR_DEPTH_WRCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 16; attribute C_WR_FREQ : integer; - attribute C_WR_FREQ of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_WR_FREQ of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1; attribute C_WR_PNTR_WIDTH : integer; - attribute C_WR_PNTR_WIDTH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 5; + attribute C_WR_PNTR_WIDTH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 5; attribute C_WR_PNTR_WIDTH_AXIS : integer; - attribute C_WR_PNTR_WIDTH_AXIS of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 10; + attribute C_WR_PNTR_WIDTH_AXIS of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 10; attribute C_WR_PNTR_WIDTH_RACH : integer; - attribute C_WR_PNTR_WIDTH_RACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 4; + attribute C_WR_PNTR_WIDTH_RACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 4; attribute C_WR_PNTR_WIDTH_RDCH : integer; - attribute C_WR_PNTR_WIDTH_RDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 10; + attribute C_WR_PNTR_WIDTH_RDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 10; attribute C_WR_PNTR_WIDTH_WACH : integer; - attribute C_WR_PNTR_WIDTH_WACH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 4; + attribute C_WR_PNTR_WIDTH_WACH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 4; attribute C_WR_PNTR_WIDTH_WDCH : integer; - attribute C_WR_PNTR_WIDTH_WDCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 10; + attribute C_WR_PNTR_WIDTH_WDCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 10; attribute C_WR_PNTR_WIDTH_WRCH : integer; - attribute C_WR_PNTR_WIDTH_WRCH of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 4; + attribute C_WR_PNTR_WIDTH_WRCH of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 4; attribute C_WR_RESPONSE_LATENCY : integer; - attribute C_WR_RESPONSE_LATENCY of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 : entity is 1; -end Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3; + attribute C_WR_RESPONSE_LATENCY of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is 1; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ : entity is "fifo_generator_v13_1_3"; +end \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\; -architecture STRUCTURE of Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 is +architecture STRUCTURE of \Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ is signal \\ : STD_LOGIC; begin almost_empty <= \\; @@ -3064,88 +9906,2256 @@ begin wr_rst_busy <= \\; GND: unisim.vcomponents.GND port map ( - G => \\ + G => \\ + ); +inst_fifo_gen: entity work.\Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3_synth__parameterized0\ + port map ( + clk => clk, + din(0) => din(0), + dout(0) => dout(0), + empty => empty, + full => full, + rd_en => rd_en, + rst => rst, + wr_en => wr_en + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen is + port ( + \S_AXI_BRESP_ACC_reg[0]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + full : out STD_LOGIC; + din : out STD_LOGIC_VECTOR ( 0 to 0 ); + D : out STD_LOGIC_VECTOR ( 4 downto 0 ); + m_axi_awvalid : out STD_LOGIC; + multiple_id_non_split_reg : out STD_LOGIC; + multiple_id_non_split_reg_0 : out STD_LOGIC; + split_ongoing_reg : out STD_LOGIC; + cmd_b_push_block_reg : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \USE_B_CHANNEL.cmd_b_empty_reg\ : out STD_LOGIC; + \pushed_commands_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \allow_split_cmd__1\ : out STD_LOGIC; + S_AXI_AREADY_I_reg : out STD_LOGIC; + cmd_push_block_reg : out STD_LOGIC; + command_ongoing_reg : out STD_LOGIC; + aclk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + \num_transactions_q_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 5 downto 0 ); + cmd_b_push_block : in STD_LOGIC; + m_axi_bvalid : in STD_LOGIC; + last_word : in STD_LOGIC; + s_axi_bready : in STD_LOGIC; + cmd_empty : in STD_LOGIC; + wr_cmd_ready : in STD_LOGIC; + almost_empty : in STD_LOGIC; + aresetn : in STD_LOGIC; + split_in_progress_reg : in STD_LOGIC; + queue_id : in STD_LOGIC; + \S_AXI_AID_Q_reg[0]\ : in STD_LOGIC; + cmd_b_empty : in STD_LOGIC; + need_to_split_q : in STD_LOGIC; + access_is_incr_q : in STD_LOGIC; + \pushed_commands_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_AREADY_I_reg_0 : in STD_LOGIC; + almost_b_empty : in STD_LOGIC; + m_axi_awready : in STD_LOGIC; + command_ongoing : in STD_LOGIC; + ram_full_i_reg : in STD_LOGIC; + cmd_push_block : in STD_LOGIC; + multiple_id_non_split : in STD_LOGIC; + \pushed_commands_reg[3]_0\ : in STD_LOGIC; + s_axi_awvalid : in STD_LOGIC; + \areset_d_reg[0]\ : in STD_LOGIC; + areset_d : in STD_LOGIC_VECTOR ( 0 to 0 ); + \areset_d_reg[1]\ : in STD_LOGIC + ); +end Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen is + signal \USE_B_CHANNEL.cmd_b_depth[4]_i_2_n_0\ : STD_LOGIC; + signal \USE_B_CHANNEL.cmd_b_depth[5]_i_3_n_0\ : STD_LOGIC; + signal \^allow_split_cmd__1\ : STD_LOGIC; + signal \^din\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal empty : STD_LOGIC; + signal \fifo_gen_inst_i_2__1_n_0\ : STD_LOGIC; + signal \^full\ : STD_LOGIC; + signal \^m_axi_awvalid\ : STD_LOGIC; + signal multiple_id_non_split_i_3_n_0 : STD_LOGIC; + signal \^multiple_id_non_split_reg_0\ : STD_LOGIC; + signal \^pushed_commands_reg[0]\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^split_ongoing_reg\ : STD_LOGIC; + signal wr_cmd_b_ready : STD_LOGIC; + signal NLW_fifo_gen_inst_almost_empty_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_almost_full_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axis_overflow_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axis_underflow_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_overflow_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_prog_empty_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_prog_full_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_underflow_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_valid_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_wr_ack_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_fifo_gen_inst_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_fifo_gen_inst_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_gen_inst_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_fifo_gen_inst_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \USE_B_CHANNEL.cmd_b_depth[2]_i_1\ : label is "soft_lutpair41"; + attribute SOFT_HLUTNM of \USE_B_CHANNEL.cmd_b_depth[3]_i_1\ : label is "soft_lutpair41"; + attribute SOFT_HLUTNM of \USE_B_CHANNEL.cmd_b_empty_i_1\ : label is "soft_lutpair40"; + attribute SOFT_HLUTNM of cmd_b_push_block_i_1 : label is "soft_lutpair42"; + attribute C_ADD_NGC_CONSTRAINT : integer; + attribute C_ADD_NGC_CONSTRAINT of fifo_gen_inst : label is 0; + attribute C_APPLICATION_TYPE_AXIS : integer; + attribute C_APPLICATION_TYPE_AXIS of fifo_gen_inst : label is 0; + attribute C_APPLICATION_TYPE_RACH : integer; + attribute C_APPLICATION_TYPE_RACH of fifo_gen_inst : label is 0; + attribute C_APPLICATION_TYPE_RDCH : integer; + attribute C_APPLICATION_TYPE_RDCH of fifo_gen_inst : label is 0; + attribute C_APPLICATION_TYPE_WACH : integer; + attribute C_APPLICATION_TYPE_WACH of fifo_gen_inst : label is 0; + attribute C_APPLICATION_TYPE_WDCH : integer; + attribute C_APPLICATION_TYPE_WDCH of fifo_gen_inst : label is 0; + attribute C_APPLICATION_TYPE_WRCH : integer; + attribute C_APPLICATION_TYPE_WRCH of fifo_gen_inst : label is 0; + attribute C_AXIS_TDATA_WIDTH : integer; + attribute C_AXIS_TDATA_WIDTH of fifo_gen_inst : label is 64; + attribute C_AXIS_TDEST_WIDTH : integer; + attribute C_AXIS_TDEST_WIDTH of fifo_gen_inst : label is 4; + attribute C_AXIS_TID_WIDTH : integer; + attribute C_AXIS_TID_WIDTH of fifo_gen_inst : label is 8; + attribute C_AXIS_TKEEP_WIDTH : integer; + attribute C_AXIS_TKEEP_WIDTH of fifo_gen_inst : label is 4; + attribute C_AXIS_TSTRB_WIDTH : integer; + attribute C_AXIS_TSTRB_WIDTH of fifo_gen_inst : label is 4; + attribute C_AXIS_TUSER_WIDTH : integer; + attribute C_AXIS_TUSER_WIDTH of fifo_gen_inst : label is 4; + attribute C_AXIS_TYPE : integer; + attribute C_AXIS_TYPE of fifo_gen_inst : label is 0; + attribute C_AXI_ADDR_WIDTH : integer; + attribute C_AXI_ADDR_WIDTH of fifo_gen_inst : label is 32; + attribute C_AXI_ARUSER_WIDTH : integer; + attribute C_AXI_ARUSER_WIDTH of fifo_gen_inst : label is 1; + attribute C_AXI_AWUSER_WIDTH : integer; + attribute C_AXI_AWUSER_WIDTH of fifo_gen_inst : label is 1; + attribute C_AXI_BUSER_WIDTH : integer; + attribute C_AXI_BUSER_WIDTH of fifo_gen_inst : label is 1; + attribute C_AXI_DATA_WIDTH : integer; + attribute C_AXI_DATA_WIDTH of fifo_gen_inst : label is 64; + attribute C_AXI_ID_WIDTH : integer; + attribute C_AXI_ID_WIDTH of fifo_gen_inst : label is 4; + attribute C_AXI_LEN_WIDTH : integer; + attribute C_AXI_LEN_WIDTH of fifo_gen_inst : label is 8; + attribute C_AXI_LOCK_WIDTH : integer; + attribute C_AXI_LOCK_WIDTH of fifo_gen_inst : label is 2; + attribute C_AXI_RUSER_WIDTH : integer; + attribute C_AXI_RUSER_WIDTH of fifo_gen_inst : label is 1; + attribute C_AXI_TYPE : integer; + attribute C_AXI_TYPE of fifo_gen_inst : label is 0; + attribute C_AXI_WUSER_WIDTH : integer; + attribute C_AXI_WUSER_WIDTH of fifo_gen_inst : label is 1; + attribute C_COMMON_CLOCK : integer; + attribute C_COMMON_CLOCK of fifo_gen_inst : label is 1; + attribute C_COUNT_TYPE : integer; + attribute C_COUNT_TYPE of fifo_gen_inst : label is 0; + attribute C_DATA_COUNT_WIDTH : integer; + attribute C_DATA_COUNT_WIDTH of fifo_gen_inst : label is 6; + attribute C_DEFAULT_VALUE : string; + attribute C_DEFAULT_VALUE of fifo_gen_inst : label is "BlankString"; + attribute C_DIN_WIDTH : integer; + attribute C_DIN_WIDTH of fifo_gen_inst : label is 5; + attribute C_DIN_WIDTH_AXIS : integer; + attribute C_DIN_WIDTH_AXIS of fifo_gen_inst : label is 1; + attribute C_DIN_WIDTH_RACH : integer; + attribute C_DIN_WIDTH_RACH of fifo_gen_inst : label is 32; + attribute C_DIN_WIDTH_RDCH : integer; + attribute C_DIN_WIDTH_RDCH of fifo_gen_inst : label is 64; + attribute C_DIN_WIDTH_WACH : integer; + attribute C_DIN_WIDTH_WACH of fifo_gen_inst : label is 32; + attribute C_DIN_WIDTH_WDCH : integer; + attribute C_DIN_WIDTH_WDCH of fifo_gen_inst : label is 64; + attribute C_DIN_WIDTH_WRCH : integer; + attribute C_DIN_WIDTH_WRCH of fifo_gen_inst : label is 2; + attribute C_DOUT_RST_VAL : string; + attribute C_DOUT_RST_VAL of fifo_gen_inst : label is "0"; + attribute C_DOUT_WIDTH : integer; + attribute C_DOUT_WIDTH of fifo_gen_inst : label is 5; + attribute C_ENABLE_RLOCS : integer; + attribute C_ENABLE_RLOCS of fifo_gen_inst : label is 0; + attribute C_ENABLE_RST_SYNC : integer; + attribute C_ENABLE_RST_SYNC of fifo_gen_inst : label is 1; + attribute C_EN_SAFETY_CKT : integer; + attribute C_EN_SAFETY_CKT of fifo_gen_inst : label is 0; + attribute C_ERROR_INJECTION_TYPE : integer; + attribute C_ERROR_INJECTION_TYPE of fifo_gen_inst : label is 0; + attribute C_ERROR_INJECTION_TYPE_AXIS : integer; + attribute C_ERROR_INJECTION_TYPE_AXIS of fifo_gen_inst : label is 0; + attribute C_ERROR_INJECTION_TYPE_RACH : integer; + attribute C_ERROR_INJECTION_TYPE_RACH of fifo_gen_inst : label is 0; + attribute C_ERROR_INJECTION_TYPE_RDCH : integer; + attribute C_ERROR_INJECTION_TYPE_RDCH of fifo_gen_inst : label is 0; + attribute C_ERROR_INJECTION_TYPE_WACH : integer; + attribute C_ERROR_INJECTION_TYPE_WACH of fifo_gen_inst : label is 0; + attribute C_ERROR_INJECTION_TYPE_WDCH : integer; + attribute C_ERROR_INJECTION_TYPE_WDCH of fifo_gen_inst : label is 0; + attribute C_ERROR_INJECTION_TYPE_WRCH : integer; + attribute C_ERROR_INJECTION_TYPE_WRCH of fifo_gen_inst : label is 0; + attribute C_FAMILY : string; + attribute C_FAMILY of fifo_gen_inst : label is "zynq"; + attribute C_FULL_FLAGS_RST_VAL : integer; + attribute C_FULL_FLAGS_RST_VAL of fifo_gen_inst : label is 0; + attribute C_HAS_ALMOST_EMPTY : integer; + attribute C_HAS_ALMOST_EMPTY of fifo_gen_inst : label is 0; + attribute C_HAS_ALMOST_FULL : integer; + attribute C_HAS_ALMOST_FULL of fifo_gen_inst : label is 0; + attribute C_HAS_AXIS_TDATA : integer; + attribute C_HAS_AXIS_TDATA of fifo_gen_inst : label is 0; + attribute C_HAS_AXIS_TDEST : integer; + attribute C_HAS_AXIS_TDEST of fifo_gen_inst : label is 0; + attribute C_HAS_AXIS_TID : integer; + attribute C_HAS_AXIS_TID of fifo_gen_inst : label is 0; + attribute C_HAS_AXIS_TKEEP : integer; + attribute C_HAS_AXIS_TKEEP of fifo_gen_inst : label is 0; + attribute C_HAS_AXIS_TLAST : integer; + attribute C_HAS_AXIS_TLAST of fifo_gen_inst : label is 0; + attribute C_HAS_AXIS_TREADY : integer; + attribute C_HAS_AXIS_TREADY of fifo_gen_inst : label is 1; + attribute C_HAS_AXIS_TSTRB : integer; + attribute C_HAS_AXIS_TSTRB of fifo_gen_inst : label is 0; + attribute C_HAS_AXIS_TUSER : integer; + attribute C_HAS_AXIS_TUSER of fifo_gen_inst : label is 0; + attribute C_HAS_AXI_ARUSER : integer; + attribute C_HAS_AXI_ARUSER of fifo_gen_inst : label is 0; + attribute C_HAS_AXI_AWUSER : integer; + attribute C_HAS_AXI_AWUSER of fifo_gen_inst : label is 0; + attribute C_HAS_AXI_BUSER : integer; + attribute C_HAS_AXI_BUSER of fifo_gen_inst : label is 0; + attribute C_HAS_AXI_ID : integer; + attribute C_HAS_AXI_ID of fifo_gen_inst : label is 0; + attribute C_HAS_AXI_RD_CHANNEL : integer; + attribute C_HAS_AXI_RD_CHANNEL of fifo_gen_inst : label is 0; + attribute C_HAS_AXI_RUSER : integer; + attribute C_HAS_AXI_RUSER of fifo_gen_inst : label is 0; + attribute C_HAS_AXI_WR_CHANNEL : integer; + attribute C_HAS_AXI_WR_CHANNEL of fifo_gen_inst : label is 0; + attribute C_HAS_AXI_WUSER : integer; + attribute C_HAS_AXI_WUSER of fifo_gen_inst : label is 0; + attribute C_HAS_BACKUP : integer; + attribute C_HAS_BACKUP of fifo_gen_inst : label is 0; + attribute C_HAS_DATA_COUNT : integer; + attribute C_HAS_DATA_COUNT of fifo_gen_inst : label is 0; + attribute C_HAS_DATA_COUNTS_AXIS : integer; + attribute C_HAS_DATA_COUNTS_AXIS of fifo_gen_inst : label is 0; + attribute C_HAS_DATA_COUNTS_RACH : integer; + attribute C_HAS_DATA_COUNTS_RACH of fifo_gen_inst : label is 0; + attribute C_HAS_DATA_COUNTS_RDCH : integer; + attribute C_HAS_DATA_COUNTS_RDCH of fifo_gen_inst : label is 0; + attribute C_HAS_DATA_COUNTS_WACH : integer; + attribute C_HAS_DATA_COUNTS_WACH of fifo_gen_inst : label is 0; + attribute C_HAS_DATA_COUNTS_WDCH : integer; + attribute C_HAS_DATA_COUNTS_WDCH of fifo_gen_inst : label is 0; + attribute C_HAS_DATA_COUNTS_WRCH : integer; + attribute C_HAS_DATA_COUNTS_WRCH of fifo_gen_inst : label is 0; + attribute C_HAS_INT_CLK : integer; + attribute C_HAS_INT_CLK of fifo_gen_inst : label is 0; + attribute C_HAS_MASTER_CE : integer; + attribute C_HAS_MASTER_CE of fifo_gen_inst : label is 0; + attribute C_HAS_MEMINIT_FILE : integer; + attribute C_HAS_MEMINIT_FILE of fifo_gen_inst : label is 0; + attribute C_HAS_OVERFLOW : integer; + attribute C_HAS_OVERFLOW of fifo_gen_inst : label is 0; + attribute C_HAS_PROG_FLAGS_AXIS : integer; + attribute C_HAS_PROG_FLAGS_AXIS of fifo_gen_inst : label is 0; + attribute C_HAS_PROG_FLAGS_RACH : integer; + attribute C_HAS_PROG_FLAGS_RACH of fifo_gen_inst : label is 0; + attribute C_HAS_PROG_FLAGS_RDCH : integer; + attribute C_HAS_PROG_FLAGS_RDCH of fifo_gen_inst : label is 0; + attribute C_HAS_PROG_FLAGS_WACH : integer; + attribute C_HAS_PROG_FLAGS_WACH of fifo_gen_inst : label is 0; + attribute C_HAS_PROG_FLAGS_WDCH : integer; + attribute C_HAS_PROG_FLAGS_WDCH of fifo_gen_inst : label is 0; + attribute C_HAS_PROG_FLAGS_WRCH : integer; + attribute C_HAS_PROG_FLAGS_WRCH of fifo_gen_inst : label is 0; + attribute C_HAS_RD_DATA_COUNT : integer; + attribute C_HAS_RD_DATA_COUNT of fifo_gen_inst : label is 0; + attribute C_HAS_RD_RST : integer; + attribute C_HAS_RD_RST of fifo_gen_inst : label is 0; + attribute C_HAS_RST : integer; + attribute C_HAS_RST of fifo_gen_inst : label is 1; + attribute C_HAS_SLAVE_CE : integer; + attribute C_HAS_SLAVE_CE of fifo_gen_inst : label is 0; + attribute C_HAS_SRST : integer; + attribute C_HAS_SRST of fifo_gen_inst : label is 0; + attribute C_HAS_UNDERFLOW : integer; + attribute C_HAS_UNDERFLOW of fifo_gen_inst : label is 0; + attribute C_HAS_VALID : integer; + attribute C_HAS_VALID of fifo_gen_inst : label is 0; + attribute C_HAS_WR_ACK : integer; + attribute C_HAS_WR_ACK of fifo_gen_inst : label is 0; + attribute C_HAS_WR_DATA_COUNT : integer; + attribute C_HAS_WR_DATA_COUNT of fifo_gen_inst : label is 0; + attribute C_HAS_WR_RST : integer; + attribute C_HAS_WR_RST of fifo_gen_inst : label is 0; + attribute C_IMPLEMENTATION_TYPE : integer; + attribute C_IMPLEMENTATION_TYPE of fifo_gen_inst : label is 0; + attribute C_IMPLEMENTATION_TYPE_AXIS : integer; + attribute C_IMPLEMENTATION_TYPE_AXIS of fifo_gen_inst : label is 1; + attribute C_IMPLEMENTATION_TYPE_RACH : integer; + attribute C_IMPLEMENTATION_TYPE_RACH of fifo_gen_inst : label is 1; + attribute C_IMPLEMENTATION_TYPE_RDCH : integer; + attribute C_IMPLEMENTATION_TYPE_RDCH of fifo_gen_inst : label is 1; + attribute C_IMPLEMENTATION_TYPE_WACH : integer; + attribute C_IMPLEMENTATION_TYPE_WACH of fifo_gen_inst : label is 1; + attribute C_IMPLEMENTATION_TYPE_WDCH : integer; + attribute C_IMPLEMENTATION_TYPE_WDCH of fifo_gen_inst : label is 1; + attribute C_IMPLEMENTATION_TYPE_WRCH : integer; + attribute C_IMPLEMENTATION_TYPE_WRCH of fifo_gen_inst : label is 1; + attribute C_INIT_WR_PNTR_VAL : integer; + attribute C_INIT_WR_PNTR_VAL of fifo_gen_inst : label is 0; + attribute C_INTERFACE_TYPE : integer; + attribute C_INTERFACE_TYPE of fifo_gen_inst : label is 0; + attribute C_MEMORY_TYPE : integer; + attribute C_MEMORY_TYPE of fifo_gen_inst : label is 2; + attribute C_MIF_FILE_NAME : string; + attribute C_MIF_FILE_NAME of fifo_gen_inst : label is "BlankString"; + attribute C_MSGON_VAL : integer; + attribute C_MSGON_VAL of fifo_gen_inst : label is 1; + attribute C_OPTIMIZATION_MODE : integer; + attribute C_OPTIMIZATION_MODE of fifo_gen_inst : label is 0; + attribute C_OVERFLOW_LOW : integer; + attribute C_OVERFLOW_LOW of fifo_gen_inst : label is 0; + attribute C_POWER_SAVING_MODE : integer; + attribute C_POWER_SAVING_MODE of fifo_gen_inst : label is 0; + attribute C_PRELOAD_LATENCY : integer; + attribute C_PRELOAD_LATENCY of fifo_gen_inst : label is 0; + attribute C_PRELOAD_REGS : integer; + attribute C_PRELOAD_REGS of fifo_gen_inst : label is 1; + attribute C_PRIM_FIFO_TYPE : string; + attribute C_PRIM_FIFO_TYPE of fifo_gen_inst : label is "512x36"; + attribute C_PRIM_FIFO_TYPE_AXIS : string; + attribute C_PRIM_FIFO_TYPE_AXIS of fifo_gen_inst : label is "512x36"; + attribute C_PRIM_FIFO_TYPE_RACH : string; + attribute C_PRIM_FIFO_TYPE_RACH of fifo_gen_inst : label is "512x36"; + attribute C_PRIM_FIFO_TYPE_RDCH : string; + attribute C_PRIM_FIFO_TYPE_RDCH of fifo_gen_inst : label is "512x36"; + attribute C_PRIM_FIFO_TYPE_WACH : string; + attribute C_PRIM_FIFO_TYPE_WACH of fifo_gen_inst : label is "512x36"; + attribute C_PRIM_FIFO_TYPE_WDCH : string; + attribute C_PRIM_FIFO_TYPE_WDCH of fifo_gen_inst : label is "512x36"; + attribute C_PRIM_FIFO_TYPE_WRCH : string; + attribute C_PRIM_FIFO_TYPE_WRCH of fifo_gen_inst : label is "512x36"; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of fifo_gen_inst : label is 4; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of fifo_gen_inst : label is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of fifo_gen_inst : label is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of fifo_gen_inst : label is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of fifo_gen_inst : label is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of fifo_gen_inst : label is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of fifo_gen_inst : label is 1022; + attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer; + attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of fifo_gen_inst : label is 5; + attribute C_PROG_EMPTY_TYPE : integer; + attribute C_PROG_EMPTY_TYPE of fifo_gen_inst : label is 0; + attribute C_PROG_EMPTY_TYPE_AXIS : integer; + attribute C_PROG_EMPTY_TYPE_AXIS of fifo_gen_inst : label is 0; + attribute C_PROG_EMPTY_TYPE_RACH : integer; + attribute C_PROG_EMPTY_TYPE_RACH of fifo_gen_inst : label is 0; + attribute C_PROG_EMPTY_TYPE_RDCH : integer; + attribute C_PROG_EMPTY_TYPE_RDCH of fifo_gen_inst : label is 0; + attribute C_PROG_EMPTY_TYPE_WACH : integer; + attribute C_PROG_EMPTY_TYPE_WACH of fifo_gen_inst : label is 0; + attribute C_PROG_EMPTY_TYPE_WDCH : integer; + attribute C_PROG_EMPTY_TYPE_WDCH of fifo_gen_inst : label is 0; + attribute C_PROG_EMPTY_TYPE_WRCH : integer; + attribute C_PROG_EMPTY_TYPE_WRCH of fifo_gen_inst : label is 0; + attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL of fifo_gen_inst : label is 31; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of fifo_gen_inst : label is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of fifo_gen_inst : label is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of fifo_gen_inst : label is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of fifo_gen_inst : label is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of fifo_gen_inst : label is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of fifo_gen_inst : label is 1023; + attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer; + attribute C_PROG_FULL_THRESH_NEGATE_VAL of fifo_gen_inst : label is 30; + attribute C_PROG_FULL_TYPE : integer; + attribute C_PROG_FULL_TYPE of fifo_gen_inst : label is 0; + attribute C_PROG_FULL_TYPE_AXIS : integer; + attribute C_PROG_FULL_TYPE_AXIS of fifo_gen_inst : label is 0; + attribute C_PROG_FULL_TYPE_RACH : integer; + attribute C_PROG_FULL_TYPE_RACH of fifo_gen_inst : label is 0; + attribute C_PROG_FULL_TYPE_RDCH : integer; + attribute C_PROG_FULL_TYPE_RDCH of fifo_gen_inst : label is 0; + attribute C_PROG_FULL_TYPE_WACH : integer; + attribute C_PROG_FULL_TYPE_WACH of fifo_gen_inst : label is 0; + attribute C_PROG_FULL_TYPE_WDCH : integer; + attribute C_PROG_FULL_TYPE_WDCH of fifo_gen_inst : label is 0; + attribute C_PROG_FULL_TYPE_WRCH : integer; + attribute C_PROG_FULL_TYPE_WRCH of fifo_gen_inst : label is 0; + attribute C_RACH_TYPE : integer; + attribute C_RACH_TYPE of fifo_gen_inst : label is 0; + attribute C_RDCH_TYPE : integer; + attribute C_RDCH_TYPE of fifo_gen_inst : label is 0; + attribute C_RD_DATA_COUNT_WIDTH : integer; + attribute C_RD_DATA_COUNT_WIDTH of fifo_gen_inst : label is 6; + attribute C_RD_DEPTH : integer; + attribute C_RD_DEPTH of fifo_gen_inst : label is 32; + attribute C_RD_FREQ : integer; + attribute C_RD_FREQ of fifo_gen_inst : label is 1; + attribute C_RD_PNTR_WIDTH : integer; + attribute C_RD_PNTR_WIDTH of fifo_gen_inst : label is 5; + attribute C_REG_SLICE_MODE_AXIS : integer; + attribute C_REG_SLICE_MODE_AXIS of fifo_gen_inst : label is 0; + attribute C_REG_SLICE_MODE_RACH : integer; + attribute C_REG_SLICE_MODE_RACH of fifo_gen_inst : label is 0; + attribute C_REG_SLICE_MODE_RDCH : integer; + attribute C_REG_SLICE_MODE_RDCH of fifo_gen_inst : label is 0; + attribute C_REG_SLICE_MODE_WACH : integer; + attribute C_REG_SLICE_MODE_WACH of fifo_gen_inst : label is 0; + attribute C_REG_SLICE_MODE_WDCH : integer; + attribute C_REG_SLICE_MODE_WDCH of fifo_gen_inst : label is 0; + attribute C_REG_SLICE_MODE_WRCH : integer; + attribute C_REG_SLICE_MODE_WRCH of fifo_gen_inst : label is 0; + attribute C_SELECT_XPM : integer; + attribute C_SELECT_XPM of fifo_gen_inst : label is 0; + attribute C_SYNCHRONIZER_STAGE : integer; + attribute C_SYNCHRONIZER_STAGE of fifo_gen_inst : label is 3; + attribute C_UNDERFLOW_LOW : integer; + attribute C_UNDERFLOW_LOW of fifo_gen_inst : label is 0; + attribute C_USE_COMMON_OVERFLOW : integer; + attribute C_USE_COMMON_OVERFLOW of fifo_gen_inst : label is 0; + attribute C_USE_COMMON_UNDERFLOW : integer; + attribute C_USE_COMMON_UNDERFLOW of fifo_gen_inst : label is 0; + attribute C_USE_DEFAULT_SETTINGS : integer; + attribute C_USE_DEFAULT_SETTINGS of fifo_gen_inst : label is 0; + attribute C_USE_DOUT_RST : integer; + attribute C_USE_DOUT_RST of fifo_gen_inst : label is 0; + attribute C_USE_ECC : integer; + attribute C_USE_ECC of fifo_gen_inst : label is 0; + attribute C_USE_ECC_AXIS : integer; + attribute C_USE_ECC_AXIS of fifo_gen_inst : label is 0; + attribute C_USE_ECC_RACH : integer; + attribute C_USE_ECC_RACH of fifo_gen_inst : label is 0; + attribute C_USE_ECC_RDCH : integer; + attribute C_USE_ECC_RDCH of fifo_gen_inst : label is 0; + attribute C_USE_ECC_WACH : integer; + attribute C_USE_ECC_WACH of fifo_gen_inst : label is 0; + attribute C_USE_ECC_WDCH : integer; + attribute C_USE_ECC_WDCH of fifo_gen_inst : label is 0; + attribute C_USE_ECC_WRCH : integer; + attribute C_USE_ECC_WRCH of fifo_gen_inst : label is 0; + attribute C_USE_EMBEDDED_REG : integer; + attribute C_USE_EMBEDDED_REG of fifo_gen_inst : label is 0; + attribute C_USE_FIFO16_FLAGS : integer; + attribute C_USE_FIFO16_FLAGS of fifo_gen_inst : label is 0; + attribute C_USE_FWFT_DATA_COUNT : integer; + attribute C_USE_FWFT_DATA_COUNT of fifo_gen_inst : label is 1; + attribute C_USE_PIPELINE_REG : integer; + attribute C_USE_PIPELINE_REG of fifo_gen_inst : label is 0; + attribute C_VALID_LOW : integer; + attribute C_VALID_LOW of fifo_gen_inst : label is 0; + attribute C_WACH_TYPE : integer; + attribute C_WACH_TYPE of fifo_gen_inst : label is 0; + attribute C_WDCH_TYPE : integer; + attribute C_WDCH_TYPE of fifo_gen_inst : label is 0; + attribute C_WRCH_TYPE : integer; + attribute C_WRCH_TYPE of fifo_gen_inst : label is 0; + attribute C_WR_ACK_LOW : integer; + attribute C_WR_ACK_LOW of fifo_gen_inst : label is 0; + attribute C_WR_DATA_COUNT_WIDTH : integer; + attribute C_WR_DATA_COUNT_WIDTH of fifo_gen_inst : label is 6; + attribute C_WR_DEPTH : integer; + attribute C_WR_DEPTH of fifo_gen_inst : label is 32; + attribute C_WR_DEPTH_AXIS : integer; + attribute C_WR_DEPTH_AXIS of fifo_gen_inst : label is 1024; + attribute C_WR_DEPTH_RACH : integer; + attribute C_WR_DEPTH_RACH of fifo_gen_inst : label is 16; + attribute C_WR_DEPTH_RDCH : integer; + attribute C_WR_DEPTH_RDCH of fifo_gen_inst : label is 1024; + attribute C_WR_DEPTH_WACH : integer; + attribute C_WR_DEPTH_WACH of fifo_gen_inst : label is 16; + attribute C_WR_DEPTH_WDCH : integer; + attribute C_WR_DEPTH_WDCH of fifo_gen_inst : label is 1024; + attribute C_WR_DEPTH_WRCH : integer; + attribute C_WR_DEPTH_WRCH of fifo_gen_inst : label is 16; + attribute C_WR_FREQ : integer; + attribute C_WR_FREQ of fifo_gen_inst : label is 1; + attribute C_WR_PNTR_WIDTH : integer; + attribute C_WR_PNTR_WIDTH of fifo_gen_inst : label is 5; + attribute C_WR_PNTR_WIDTH_AXIS : integer; + attribute C_WR_PNTR_WIDTH_AXIS of fifo_gen_inst : label is 10; + attribute C_WR_PNTR_WIDTH_RACH : integer; + attribute C_WR_PNTR_WIDTH_RACH of fifo_gen_inst : label is 4; + attribute C_WR_PNTR_WIDTH_RDCH : integer; + attribute C_WR_PNTR_WIDTH_RDCH of fifo_gen_inst : label is 10; + attribute C_WR_PNTR_WIDTH_WACH : integer; + attribute C_WR_PNTR_WIDTH_WACH of fifo_gen_inst : label is 4; + attribute C_WR_PNTR_WIDTH_WDCH : integer; + attribute C_WR_PNTR_WIDTH_WDCH of fifo_gen_inst : label is 10; + attribute C_WR_PNTR_WIDTH_WRCH : integer; + attribute C_WR_PNTR_WIDTH_WRCH of fifo_gen_inst : label is 4; + attribute C_WR_RESPONSE_LATENCY : integer; + attribute C_WR_RESPONSE_LATENCY of fifo_gen_inst : label is 1; + attribute SOFT_HLUTNM of \fifo_gen_inst_i_2__1\ : label is "soft_lutpair40"; + attribute SOFT_HLUTNM of split_ongoing_i_1 : label is "soft_lutpair42"; +begin + \allow_split_cmd__1\ <= \^allow_split_cmd__1\; + din(0) <= \^din\(0); + full <= \^full\; + m_axi_awvalid <= \^m_axi_awvalid\; + multiple_id_non_split_reg_0 <= \^multiple_id_non_split_reg_0\; + \pushed_commands_reg[0]\(0) <= \^pushed_commands_reg[0]\(0); + split_ongoing_reg <= \^split_ongoing_reg\; +S_AXI_AREADY_I_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"0F88FFFF0F880F88" + ) + port map ( + I0 => \^pushed_commands_reg[0]\(0), + I1 => \pushed_commands_reg[3]_0\, + I2 => s_axi_awvalid, + I3 => S_AXI_AREADY_I_reg_0, + I4 => \areset_d_reg[0]\, + I5 => areset_d(0), + O => S_AXI_AREADY_I_reg + ); +\USE_B_CHANNEL.cmd_b_depth[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"69" + ) + port map ( + I0 => Q(0), + I1 => \USE_B_CHANNEL.cmd_b_depth[4]_i_2_n_0\, + I2 => Q(1), + O => D(0) + ); +\USE_B_CHANNEL.cmd_b_depth[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"78E1" + ) + port map ( + I0 => Q(0), + I1 => \USE_B_CHANNEL.cmd_b_depth[4]_i_2_n_0\, + I2 => Q(2), + I3 => Q(1), + O => D(1) + ); +\USE_B_CHANNEL.cmd_b_depth[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7F80FE01" + ) + port map ( + I0 => \USE_B_CHANNEL.cmd_b_depth[4]_i_2_n_0\, + I1 => Q(0), + I2 => Q(1), + I3 => Q(3), + I4 => Q(2), + O => D(2) + ); +\USE_B_CHANNEL.cmd_b_depth[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFF8000FFFE0001" + ) + port map ( + I0 => Q(1), + I1 => Q(0), + I2 => \USE_B_CHANNEL.cmd_b_depth[4]_i_2_n_0\, + I3 => Q(2), + I4 => Q(4), + I5 => Q(3), + O => D(3) + ); +\USE_B_CHANNEL.cmd_b_depth[4]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4444444404444444" + ) + port map ( + I0 => cmd_b_push_block, + I1 => \^m_axi_awvalid\, + I2 => m_axi_bvalid, + I3 => last_word, + I4 => s_axi_bready, + I5 => empty, + O => \USE_B_CHANNEL.cmd_b_depth[4]_i_2_n_0\ + ); +\USE_B_CHANNEL.cmd_b_depth[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2D22222222222222" + ) + port map ( + I0 => \^m_axi_awvalid\, + I1 => cmd_b_push_block, + I2 => empty, + I3 => s_axi_bready, + I4 => last_word, + I5 => m_axi_bvalid, + O => E(0) + ); +\USE_B_CHANNEL.cmd_b_depth[5]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7F80FE01" + ) + port map ( + I0 => Q(2), + I1 => \USE_B_CHANNEL.cmd_b_depth[5]_i_3_n_0\, + I2 => Q(3), + I3 => Q(5), + I4 => Q(4), + O => D(4) + ); +\USE_B_CHANNEL.cmd_b_depth[5]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5454545454D55454" + ) + port map ( + I0 => Q(2), + I1 => Q(1), + I2 => Q(0), + I3 => cmd_b_push_block, + I4 => \^m_axi_awvalid\, + I5 => wr_cmd_b_ready, + O => \USE_B_CHANNEL.cmd_b_depth[5]_i_3_n_0\ + ); +\USE_B_CHANNEL.cmd_b_empty_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F2DDD000" + ) + port map ( + I0 => \^m_axi_awvalid\, + I1 => cmd_b_push_block, + I2 => almost_b_empty, + I3 => wr_cmd_b_ready, + I4 => cmd_b_empty, + O => \USE_B_CHANNEL.cmd_b_empty_reg\ + ); +cmd_b_push_block_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"00E0" + ) + port map ( + I0 => \^m_axi_awvalid\, + I1 => cmd_b_push_block, + I2 => aresetn, + I3 => S_AXI_AREADY_I_reg_0, + O => cmd_b_push_block_reg + ); +cmd_push_block_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"08C8" + ) + port map ( + I0 => cmd_push_block, + I1 => aresetn, + I2 => \^m_axi_awvalid\, + I3 => m_axi_awready, + O => cmd_push_block_reg + ); +command_ongoing_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF7770000F000" + ) + port map ( + I0 => \^pushed_commands_reg[0]\(0), + I1 => \pushed_commands_reg[3]_0\, + I2 => s_axi_awvalid, + I3 => S_AXI_AREADY_I_reg_0, + I4 => \areset_d_reg[1]\, + I5 => command_ongoing, + O => command_ongoing_reg + ); +fifo_gen_inst: entity work.Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 + port map ( + almost_empty => NLW_fifo_gen_inst_almost_empty_UNCONNECTED, + almost_full => NLW_fifo_gen_inst_almost_full_UNCONNECTED, + axi_ar_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED(4 downto 0), + axi_ar_dbiterr => NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED, + axi_ar_injectdbiterr => '0', + axi_ar_injectsbiterr => '0', + axi_ar_overflow => NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED, + axi_ar_prog_empty => NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED, + axi_ar_prog_empty_thresh(3 downto 0) => B"0000", + axi_ar_prog_full => NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED, + axi_ar_prog_full_thresh(3 downto 0) => B"0000", + axi_ar_rd_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED(4 downto 0), + axi_ar_sbiterr => NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED, + axi_ar_underflow => NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED, + axi_ar_wr_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED(4 downto 0), + axi_aw_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED(4 downto 0), + axi_aw_dbiterr => NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED, + axi_aw_injectdbiterr => '0', + axi_aw_injectsbiterr => '0', + axi_aw_overflow => NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED, + axi_aw_prog_empty => NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED, + axi_aw_prog_empty_thresh(3 downto 0) => B"0000", + axi_aw_prog_full => NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED, + axi_aw_prog_full_thresh(3 downto 0) => B"0000", + axi_aw_rd_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED(4 downto 0), + axi_aw_sbiterr => NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED, + axi_aw_underflow => NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED, + axi_aw_wr_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED(4 downto 0), + axi_b_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED(4 downto 0), + axi_b_dbiterr => NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED, + axi_b_injectdbiterr => '0', + axi_b_injectsbiterr => '0', + axi_b_overflow => NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED, + axi_b_prog_empty => NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED, + axi_b_prog_empty_thresh(3 downto 0) => B"0000", + axi_b_prog_full => NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED, + axi_b_prog_full_thresh(3 downto 0) => B"0000", + axi_b_rd_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED(4 downto 0), + axi_b_sbiterr => NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED, + axi_b_underflow => NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED, + axi_b_wr_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED(4 downto 0), + axi_r_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED(10 downto 0), + axi_r_dbiterr => NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED, + axi_r_injectdbiterr => '0', + axi_r_injectsbiterr => '0', + axi_r_overflow => NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED, + axi_r_prog_empty => NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED, + axi_r_prog_empty_thresh(9 downto 0) => B"0000000000", + axi_r_prog_full => NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED, + axi_r_prog_full_thresh(9 downto 0) => B"0000000000", + axi_r_rd_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED(10 downto 0), + axi_r_sbiterr => NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED, + axi_r_underflow => NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED, + axi_r_wr_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED(10 downto 0), + axi_w_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED(10 downto 0), + axi_w_dbiterr => NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED, + axi_w_injectdbiterr => '0', + axi_w_injectsbiterr => '0', + axi_w_overflow => NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED, + axi_w_prog_empty => NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED, + axi_w_prog_empty_thresh(9 downto 0) => B"0000000000", + axi_w_prog_full => NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED, + axi_w_prog_full_thresh(9 downto 0) => B"0000000000", + axi_w_rd_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED(10 downto 0), + axi_w_sbiterr => NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED, + axi_w_underflow => NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED, + axi_w_wr_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED(10 downto 0), + axis_data_count(10 downto 0) => NLW_fifo_gen_inst_axis_data_count_UNCONNECTED(10 downto 0), + axis_dbiterr => NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED, + axis_injectdbiterr => '0', + axis_injectsbiterr => '0', + axis_overflow => NLW_fifo_gen_inst_axis_overflow_UNCONNECTED, + axis_prog_empty => NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED, + axis_prog_empty_thresh(9 downto 0) => B"0000000000", + axis_prog_full => NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED, + axis_prog_full_thresh(9 downto 0) => B"0000000000", + axis_rd_data_count(10 downto 0) => NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED(10 downto 0), + axis_sbiterr => NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED, + axis_underflow => NLW_fifo_gen_inst_axis_underflow_UNCONNECTED, + axis_wr_data_count(10 downto 0) => NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED(10 downto 0), + backup => '0', + backup_marker => '0', + clk => aclk, + data_count(5 downto 0) => NLW_fifo_gen_inst_data_count_UNCONNECTED(5 downto 0), + dbiterr => NLW_fifo_gen_inst_dbiterr_UNCONNECTED, + din(4) => \^din\(0), + din(3 downto 0) => \num_transactions_q_reg[3]\(3 downto 0), + dout(4 downto 0) => \S_AXI_BRESP_ACC_reg[0]\(4 downto 0), + empty => empty, + full => \^full\, + injectdbiterr => '0', + injectsbiterr => '0', + int_clk => '0', + m_aclk => '0', + m_aclk_en => '0', + m_axi_araddr(31 downto 0) => NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED(31 downto 0), + m_axi_arburst(1 downto 0) => NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED(1 downto 0), + m_axi_arcache(3 downto 0) => NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED(3 downto 0), + m_axi_arid(3 downto 0) => NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED(3 downto 0), + m_axi_arlen(7 downto 0) => NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED(7 downto 0), + m_axi_arlock(1 downto 0) => NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED(1 downto 0), + m_axi_arprot(2 downto 0) => NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED(2 downto 0), + m_axi_arqos(3 downto 0) => NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED(3 downto 0), + m_axi_arready => '0', + m_axi_arregion(3 downto 0) => NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED(3 downto 0), + m_axi_arsize(2 downto 0) => NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED(2 downto 0), + m_axi_aruser(0) => NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED(0), + m_axi_arvalid => NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED, + m_axi_awaddr(31 downto 0) => NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED(31 downto 0), + m_axi_awburst(1 downto 0) => NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED(1 downto 0), + m_axi_awcache(3 downto 0) => NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED(3 downto 0), + m_axi_awid(3 downto 0) => NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED(3 downto 0), + m_axi_awlen(7 downto 0) => NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED(7 downto 0), + m_axi_awlock(1 downto 0) => NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED(1 downto 0), + m_axi_awprot(2 downto 0) => NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED(2 downto 0), + m_axi_awqos(3 downto 0) => NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED(3 downto 0), + m_axi_awready => '0', + m_axi_awregion(3 downto 0) => NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED(3 downto 0), + m_axi_awsize(2 downto 0) => NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED(2 downto 0), + m_axi_awuser(0) => NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED(0), + m_axi_awvalid => NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED, + m_axi_bid(3 downto 0) => B"0000", + m_axi_bready => NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED, + m_axi_bresp(1 downto 0) => B"00", + m_axi_buser(0) => '0', + m_axi_bvalid => '0', + m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + m_axi_rid(3 downto 0) => B"0000", + m_axi_rlast => '0', + m_axi_rready => NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED, + m_axi_rresp(1 downto 0) => B"00", + m_axi_ruser(0) => '0', + m_axi_rvalid => '0', + m_axi_wdata(63 downto 0) => NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED(63 downto 0), + m_axi_wid(3 downto 0) => NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED(3 downto 0), + m_axi_wlast => NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED, + m_axi_wready => '0', + m_axi_wstrb(7 downto 0) => NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED(7 downto 0), + m_axi_wuser(0) => NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED(0), + m_axi_wvalid => NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED, + m_axis_tdata(63 downto 0) => NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED(63 downto 0), + m_axis_tdest(3 downto 0) => NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED(3 downto 0), + m_axis_tid(7 downto 0) => NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED(7 downto 0), + m_axis_tkeep(3 downto 0) => NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED(3 downto 0), + m_axis_tlast => NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED, + m_axis_tready => '0', + m_axis_tstrb(3 downto 0) => NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED(3 downto 0), + m_axis_tuser(3 downto 0) => NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED(3 downto 0), + m_axis_tvalid => NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED, + overflow => NLW_fifo_gen_inst_overflow_UNCONNECTED, + prog_empty => NLW_fifo_gen_inst_prog_empty_UNCONNECTED, + prog_empty_thresh(4 downto 0) => B"00000", + prog_empty_thresh_assert(4 downto 0) => B"00000", + prog_empty_thresh_negate(4 downto 0) => B"00000", + prog_full => NLW_fifo_gen_inst_prog_full_UNCONNECTED, + prog_full_thresh(4 downto 0) => B"00000", + prog_full_thresh_assert(4 downto 0) => B"00000", + prog_full_thresh_negate(4 downto 0) => B"00000", + rd_clk => '0', + rd_data_count(5 downto 0) => NLW_fifo_gen_inst_rd_data_count_UNCONNECTED(5 downto 0), + rd_en => wr_cmd_b_ready, + rd_rst => '0', + rd_rst_busy => NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED, + rst => SR(0), + s_aclk => '0', + s_aclk_en => '0', + s_aresetn => '0', + s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", + s_axi_arburst(1 downto 0) => B"00", + s_axi_arcache(3 downto 0) => B"0000", + s_axi_arid(3 downto 0) => B"0000", + s_axi_arlen(7 downto 0) => B"00000000", + s_axi_arlock(1 downto 0) => B"00", + s_axi_arprot(2 downto 0) => B"000", + s_axi_arqos(3 downto 0) => B"0000", + s_axi_arready => NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED, + s_axi_arregion(3 downto 0) => B"0000", + s_axi_arsize(2 downto 0) => B"000", + s_axi_aruser(0) => '0', + s_axi_arvalid => '0', + s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", + s_axi_awburst(1 downto 0) => B"00", + s_axi_awcache(3 downto 0) => B"0000", + s_axi_awid(3 downto 0) => B"0000", + s_axi_awlen(7 downto 0) => B"00000000", + s_axi_awlock(1 downto 0) => B"00", + s_axi_awprot(2 downto 0) => B"000", + s_axi_awqos(3 downto 0) => B"0000", + s_axi_awready => NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED, + s_axi_awregion(3 downto 0) => B"0000", + s_axi_awsize(2 downto 0) => B"000", + s_axi_awuser(0) => '0', + s_axi_awvalid => '0', + s_axi_bid(3 downto 0) => NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED(3 downto 0), + s_axi_bready => '0', + s_axi_bresp(1 downto 0) => NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED(1 downto 0), + s_axi_buser(0) => NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED(0), + s_axi_bvalid => NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED, + s_axi_rdata(63 downto 0) => NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED(63 downto 0), + s_axi_rid(3 downto 0) => NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED(3 downto 0), + s_axi_rlast => NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED, + s_axi_rready => '0', + s_axi_rresp(1 downto 0) => NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED(1 downto 0), + s_axi_ruser(0) => NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED(0), + s_axi_rvalid => NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED, + s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + s_axi_wid(3 downto 0) => B"0000", + s_axi_wlast => '0', + s_axi_wready => NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED, + s_axi_wstrb(7 downto 0) => B"00000000", + s_axi_wuser(0) => '0', + s_axi_wvalid => '0', + s_axis_tdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + s_axis_tdest(3 downto 0) => B"0000", + s_axis_tid(7 downto 0) => B"00000000", + s_axis_tkeep(3 downto 0) => B"0000", + s_axis_tlast => '0', + s_axis_tready => NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED, + s_axis_tstrb(3 downto 0) => B"0000", + s_axis_tuser(3 downto 0) => B"0000", + s_axis_tvalid => '0', + sbiterr => NLW_fifo_gen_inst_sbiterr_UNCONNECTED, + sleep => '0', + srst => '0', + underflow => NLW_fifo_gen_inst_underflow_UNCONNECTED, + valid => NLW_fifo_gen_inst_valid_UNCONNECTED, + wr_ack => NLW_fifo_gen_inst_wr_ack_UNCONNECTED, + wr_clk => '0', + wr_data_count(5 downto 0) => NLW_fifo_gen_inst_wr_data_count_UNCONNECTED(5 downto 0), + wr_en => \fifo_gen_inst_i_2__1_n_0\, + wr_rst => '0', + wr_rst_busy => NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED + ); +\fifo_gen_inst_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"08808888" + ) + port map ( + I0 => need_to_split_q, + I1 => access_is_incr_q, + I2 => \num_transactions_q_reg[3]\(3), + I3 => \pushed_commands_reg[3]\(3), + I4 => \^split_ongoing_reg\, + O => \^din\(0) + ); +\fifo_gen_inst_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^m_axi_awvalid\, + I1 => cmd_b_push_block, + O => \fifo_gen_inst_i_2__1_n_0\ + ); +fifo_gen_inst_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"4000" + ) + port map ( + I0 => empty, + I1 => s_axi_bready, + I2 => last_word, + I3 => m_axi_bvalid, + O => wr_cmd_b_ready + ); +fifo_gen_inst_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \num_transactions_q_reg[3]\(0), + I1 => \pushed_commands_reg[3]\(0), + I2 => \pushed_commands_reg[3]\(2), + I3 => \num_transactions_q_reg[3]\(2), + I4 => \pushed_commands_reg[3]\(1), + I5 => \num_transactions_q_reg[3]\(1), + O => \^split_ongoing_reg\ + ); +m_axi_awvalid_INST_0: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAA00002220" + ) + port map ( + I0 => command_ongoing, + I1 => \^full\, + I2 => \^allow_split_cmd__1\, + I3 => \^multiple_id_non_split_reg_0\, + I4 => ram_full_i_reg, + I5 => cmd_push_block, + O => \^m_axi_awvalid\ + ); +m_axi_awvalid_INST_0_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"4444400440044004" + ) + port map ( + I0 => multiple_id_non_split, + I1 => need_to_split_q, + I2 => queue_id, + I3 => \S_AXI_AID_Q_reg[0]\, + I4 => cmd_b_empty, + I5 => cmd_empty, + O => \^allow_split_cmd__1\ + ); +m_axi_awvalid_INST_0_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FFD7D7D7" + ) + port map ( + I0 => split_in_progress_reg, + I1 => queue_id, + I2 => \S_AXI_AID_Q_reg[0]\, + I3 => cmd_b_empty, + I4 => cmd_empty, + I5 => need_to_split_q, + O => \^multiple_id_non_split_reg_0\ + ); +multiple_id_non_split_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"A888FFFF" + ) + port map ( + I0 => multiple_id_non_split_i_3_n_0, + I1 => cmd_empty, + I2 => wr_cmd_ready, + I3 => almost_empty, + I4 => aresetn, + O => multiple_id_non_split_reg + ); +multiple_id_non_split_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"BAAAAAAAAAAAAAAA" + ) + port map ( + I0 => cmd_b_empty, + I1 => empty, + I2 => s_axi_bready, + I3 => last_word, + I4 => m_axi_bvalid, + I5 => almost_b_empty, + O => multiple_id_non_split_i_3_n_0 + ); +split_ongoing_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^m_axi_awvalid\, + I1 => m_axi_awready, + O => \^pushed_commands_reg[0]\(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen_6 is + port ( + dout : out STD_LOGIC_VECTOR ( 4 downto 0 ); + full : out STD_LOGIC; + empty : out STD_LOGIC; + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + din : out STD_LOGIC_VECTOR ( 3 downto 0 ); + wr_en : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 4 downto 0 ); + m_axi_wvalid : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wready : out STD_LOGIC; + \queue_id_reg[0]\ : out STD_LOGIC; + split_in_progress_reg : out STD_LOGIC; + multiple_id_non_split_reg : out STD_LOGIC; + aclk : in STD_LOGIC; + \S_AXI_AID_Q_reg[0]\ : in STD_LOGIC; + wr_cmd_ready : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 5 downto 0 ); + split_in_progress_reg_0 : in STD_LOGIC; + \allow_split_cmd__1\ : in STD_LOGIC; + ram_full_i_reg : in STD_LOGIC; + command_ongoing : in STD_LOGIC; + cmd_push_block : in STD_LOGIC; + \S_AXI_ALEN_Q_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + need_to_split_q : in STD_LOGIC; + \pushed_commands_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wvalid : in STD_LOGIC; + m_axi_wready : in STD_LOGIC; + aresetn : in STD_LOGIC; + queue_id : in STD_LOGIC; + split_in_progress_reg_1 : in STD_LOGIC; + cmd_empty_reg : in STD_LOGIC; + multiple_id_non_split : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen_6 : entity is "axi_data_fifo_v2_1_10_fifo_gen"; +end Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen_6; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen_6 is + signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \cmd_depth[4]_i_2_n_0\ : STD_LOGIC; + signal \cmd_depth[5]_i_3_n_0\ : STD_LOGIC; + signal \^din\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^empty\ : STD_LOGIC; + signal \^full\ : STD_LOGIC; + signal \^wr_en\ : STD_LOGIC; + signal NLW_fifo_gen_inst_almost_empty_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_almost_full_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axis_overflow_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axis_underflow_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_overflow_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_prog_empty_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_prog_full_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_underflow_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_valid_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_wr_ack_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED : STD_LOGIC; + signal NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_fifo_gen_inst_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_fifo_gen_inst_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_gen_inst_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_fifo_gen_inst_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \cmd_depth[2]_i_1\ : label is "soft_lutpair32"; + attribute SOFT_HLUTNM of \cmd_depth[3]_i_1\ : label is "soft_lutpair32"; + attribute SOFT_HLUTNM of \cmd_depth[4]_i_2\ : label is "soft_lutpair35"; + attribute SOFT_HLUTNM of \cmd_depth[5]_i_1\ : label is "soft_lutpair33"; + attribute C_ADD_NGC_CONSTRAINT : integer; + attribute C_ADD_NGC_CONSTRAINT of fifo_gen_inst : label is 0; + attribute C_APPLICATION_TYPE_AXIS : integer; + attribute C_APPLICATION_TYPE_AXIS of fifo_gen_inst : label is 0; + attribute C_APPLICATION_TYPE_RACH : integer; + attribute C_APPLICATION_TYPE_RACH of fifo_gen_inst : label is 0; + attribute C_APPLICATION_TYPE_RDCH : integer; + attribute C_APPLICATION_TYPE_RDCH of fifo_gen_inst : label is 0; + attribute C_APPLICATION_TYPE_WACH : integer; + attribute C_APPLICATION_TYPE_WACH of fifo_gen_inst : label is 0; + attribute C_APPLICATION_TYPE_WDCH : integer; + attribute C_APPLICATION_TYPE_WDCH of fifo_gen_inst : label is 0; + attribute C_APPLICATION_TYPE_WRCH : integer; + attribute C_APPLICATION_TYPE_WRCH of fifo_gen_inst : label is 0; + attribute C_AXIS_TDATA_WIDTH : integer; + attribute C_AXIS_TDATA_WIDTH of fifo_gen_inst : label is 64; + attribute C_AXIS_TDEST_WIDTH : integer; + attribute C_AXIS_TDEST_WIDTH of fifo_gen_inst : label is 4; + attribute C_AXIS_TID_WIDTH : integer; + attribute C_AXIS_TID_WIDTH of fifo_gen_inst : label is 8; + attribute C_AXIS_TKEEP_WIDTH : integer; + attribute C_AXIS_TKEEP_WIDTH of fifo_gen_inst : label is 4; + attribute C_AXIS_TSTRB_WIDTH : integer; + attribute C_AXIS_TSTRB_WIDTH of fifo_gen_inst : label is 4; + attribute C_AXIS_TUSER_WIDTH : integer; + attribute C_AXIS_TUSER_WIDTH of fifo_gen_inst : label is 4; + attribute C_AXIS_TYPE : integer; + attribute C_AXIS_TYPE of fifo_gen_inst : label is 0; + attribute C_AXI_ADDR_WIDTH : integer; + attribute C_AXI_ADDR_WIDTH of fifo_gen_inst : label is 32; + attribute C_AXI_ARUSER_WIDTH : integer; + attribute C_AXI_ARUSER_WIDTH of fifo_gen_inst : label is 1; + attribute C_AXI_AWUSER_WIDTH : integer; + attribute C_AXI_AWUSER_WIDTH of fifo_gen_inst : label is 1; + attribute C_AXI_BUSER_WIDTH : integer; + attribute C_AXI_BUSER_WIDTH of fifo_gen_inst : label is 1; + attribute C_AXI_DATA_WIDTH : integer; + attribute C_AXI_DATA_WIDTH of fifo_gen_inst : label is 64; + attribute C_AXI_ID_WIDTH : integer; + attribute C_AXI_ID_WIDTH of fifo_gen_inst : label is 4; + attribute C_AXI_LEN_WIDTH : integer; + attribute C_AXI_LEN_WIDTH of fifo_gen_inst : label is 8; + attribute C_AXI_LOCK_WIDTH : integer; + attribute C_AXI_LOCK_WIDTH of fifo_gen_inst : label is 2; + attribute C_AXI_RUSER_WIDTH : integer; + attribute C_AXI_RUSER_WIDTH of fifo_gen_inst : label is 1; + attribute C_AXI_TYPE : integer; + attribute C_AXI_TYPE of fifo_gen_inst : label is 0; + attribute C_AXI_WUSER_WIDTH : integer; + attribute C_AXI_WUSER_WIDTH of fifo_gen_inst : label is 1; + attribute C_COMMON_CLOCK : integer; + attribute C_COMMON_CLOCK of fifo_gen_inst : label is 1; + attribute C_COUNT_TYPE : integer; + attribute C_COUNT_TYPE of fifo_gen_inst : label is 0; + attribute C_DATA_COUNT_WIDTH : integer; + attribute C_DATA_COUNT_WIDTH of fifo_gen_inst : label is 6; + attribute C_DEFAULT_VALUE : string; + attribute C_DEFAULT_VALUE of fifo_gen_inst : label is "BlankString"; + attribute C_DIN_WIDTH : integer; + attribute C_DIN_WIDTH of fifo_gen_inst : label is 5; + attribute C_DIN_WIDTH_AXIS : integer; + attribute C_DIN_WIDTH_AXIS of fifo_gen_inst : label is 1; + attribute C_DIN_WIDTH_RACH : integer; + attribute C_DIN_WIDTH_RACH of fifo_gen_inst : label is 32; + attribute C_DIN_WIDTH_RDCH : integer; + attribute C_DIN_WIDTH_RDCH of fifo_gen_inst : label is 64; + attribute C_DIN_WIDTH_WACH : integer; + attribute C_DIN_WIDTH_WACH of fifo_gen_inst : label is 32; + attribute C_DIN_WIDTH_WDCH : integer; + attribute C_DIN_WIDTH_WDCH of fifo_gen_inst : label is 64; + attribute C_DIN_WIDTH_WRCH : integer; + attribute C_DIN_WIDTH_WRCH of fifo_gen_inst : label is 2; + attribute C_DOUT_RST_VAL : string; + attribute C_DOUT_RST_VAL of fifo_gen_inst : label is "0"; + attribute C_DOUT_WIDTH : integer; + attribute C_DOUT_WIDTH of fifo_gen_inst : label is 5; + attribute C_ENABLE_RLOCS : integer; + attribute C_ENABLE_RLOCS of fifo_gen_inst : label is 0; + attribute C_ENABLE_RST_SYNC : integer; + attribute C_ENABLE_RST_SYNC of fifo_gen_inst : label is 1; + attribute C_EN_SAFETY_CKT : integer; + attribute C_EN_SAFETY_CKT of fifo_gen_inst : label is 0; + attribute C_ERROR_INJECTION_TYPE : integer; + attribute C_ERROR_INJECTION_TYPE of fifo_gen_inst : label is 0; + attribute C_ERROR_INJECTION_TYPE_AXIS : integer; + attribute C_ERROR_INJECTION_TYPE_AXIS of fifo_gen_inst : label is 0; + attribute C_ERROR_INJECTION_TYPE_RACH : integer; + attribute C_ERROR_INJECTION_TYPE_RACH of fifo_gen_inst : label is 0; + attribute C_ERROR_INJECTION_TYPE_RDCH : integer; + attribute C_ERROR_INJECTION_TYPE_RDCH of fifo_gen_inst : label is 0; + attribute C_ERROR_INJECTION_TYPE_WACH : integer; + attribute C_ERROR_INJECTION_TYPE_WACH of fifo_gen_inst : label is 0; + attribute C_ERROR_INJECTION_TYPE_WDCH : integer; + attribute C_ERROR_INJECTION_TYPE_WDCH of fifo_gen_inst : label is 0; + attribute C_ERROR_INJECTION_TYPE_WRCH : integer; + attribute C_ERROR_INJECTION_TYPE_WRCH of fifo_gen_inst : label is 0; + attribute C_FAMILY : string; + attribute C_FAMILY of fifo_gen_inst : label is "zynq"; + attribute C_FULL_FLAGS_RST_VAL : integer; + attribute C_FULL_FLAGS_RST_VAL of fifo_gen_inst : label is 0; + attribute C_HAS_ALMOST_EMPTY : integer; + attribute C_HAS_ALMOST_EMPTY of fifo_gen_inst : label is 0; + attribute C_HAS_ALMOST_FULL : integer; + attribute C_HAS_ALMOST_FULL of fifo_gen_inst : label is 0; + attribute C_HAS_AXIS_TDATA : integer; + attribute C_HAS_AXIS_TDATA of fifo_gen_inst : label is 0; + attribute C_HAS_AXIS_TDEST : integer; + attribute C_HAS_AXIS_TDEST of fifo_gen_inst : label is 0; + attribute C_HAS_AXIS_TID : integer; + attribute C_HAS_AXIS_TID of fifo_gen_inst : label is 0; + attribute C_HAS_AXIS_TKEEP : integer; + attribute C_HAS_AXIS_TKEEP of fifo_gen_inst : label is 0; + attribute C_HAS_AXIS_TLAST : integer; + attribute C_HAS_AXIS_TLAST of fifo_gen_inst : label is 0; + attribute C_HAS_AXIS_TREADY : integer; + attribute C_HAS_AXIS_TREADY of fifo_gen_inst : label is 1; + attribute C_HAS_AXIS_TSTRB : integer; + attribute C_HAS_AXIS_TSTRB of fifo_gen_inst : label is 0; + attribute C_HAS_AXIS_TUSER : integer; + attribute C_HAS_AXIS_TUSER of fifo_gen_inst : label is 0; + attribute C_HAS_AXI_ARUSER : integer; + attribute C_HAS_AXI_ARUSER of fifo_gen_inst : label is 0; + attribute C_HAS_AXI_AWUSER : integer; + attribute C_HAS_AXI_AWUSER of fifo_gen_inst : label is 0; + attribute C_HAS_AXI_BUSER : integer; + attribute C_HAS_AXI_BUSER of fifo_gen_inst : label is 0; + attribute C_HAS_AXI_ID : integer; + attribute C_HAS_AXI_ID of fifo_gen_inst : label is 0; + attribute C_HAS_AXI_RD_CHANNEL : integer; + attribute C_HAS_AXI_RD_CHANNEL of fifo_gen_inst : label is 0; + attribute C_HAS_AXI_RUSER : integer; + attribute C_HAS_AXI_RUSER of fifo_gen_inst : label is 0; + attribute C_HAS_AXI_WR_CHANNEL : integer; + attribute C_HAS_AXI_WR_CHANNEL of fifo_gen_inst : label is 0; + attribute C_HAS_AXI_WUSER : integer; + attribute C_HAS_AXI_WUSER of fifo_gen_inst : label is 0; + attribute C_HAS_BACKUP : integer; + attribute C_HAS_BACKUP of fifo_gen_inst : label is 0; + attribute C_HAS_DATA_COUNT : integer; + attribute C_HAS_DATA_COUNT of fifo_gen_inst : label is 0; + attribute C_HAS_DATA_COUNTS_AXIS : integer; + attribute C_HAS_DATA_COUNTS_AXIS of fifo_gen_inst : label is 0; + attribute C_HAS_DATA_COUNTS_RACH : integer; + attribute C_HAS_DATA_COUNTS_RACH of fifo_gen_inst : label is 0; + attribute C_HAS_DATA_COUNTS_RDCH : integer; + attribute C_HAS_DATA_COUNTS_RDCH of fifo_gen_inst : label is 0; + attribute C_HAS_DATA_COUNTS_WACH : integer; + attribute C_HAS_DATA_COUNTS_WACH of fifo_gen_inst : label is 0; + attribute C_HAS_DATA_COUNTS_WDCH : integer; + attribute C_HAS_DATA_COUNTS_WDCH of fifo_gen_inst : label is 0; + attribute C_HAS_DATA_COUNTS_WRCH : integer; + attribute C_HAS_DATA_COUNTS_WRCH of fifo_gen_inst : label is 0; + attribute C_HAS_INT_CLK : integer; + attribute C_HAS_INT_CLK of fifo_gen_inst : label is 0; + attribute C_HAS_MASTER_CE : integer; + attribute C_HAS_MASTER_CE of fifo_gen_inst : label is 0; + attribute C_HAS_MEMINIT_FILE : integer; + attribute C_HAS_MEMINIT_FILE of fifo_gen_inst : label is 0; + attribute C_HAS_OVERFLOW : integer; + attribute C_HAS_OVERFLOW of fifo_gen_inst : label is 0; + attribute C_HAS_PROG_FLAGS_AXIS : integer; + attribute C_HAS_PROG_FLAGS_AXIS of fifo_gen_inst : label is 0; + attribute C_HAS_PROG_FLAGS_RACH : integer; + attribute C_HAS_PROG_FLAGS_RACH of fifo_gen_inst : label is 0; + attribute C_HAS_PROG_FLAGS_RDCH : integer; + attribute C_HAS_PROG_FLAGS_RDCH of fifo_gen_inst : label is 0; + attribute C_HAS_PROG_FLAGS_WACH : integer; + attribute C_HAS_PROG_FLAGS_WACH of fifo_gen_inst : label is 0; + attribute C_HAS_PROG_FLAGS_WDCH : integer; + attribute C_HAS_PROG_FLAGS_WDCH of fifo_gen_inst : label is 0; + attribute C_HAS_PROG_FLAGS_WRCH : integer; + attribute C_HAS_PROG_FLAGS_WRCH of fifo_gen_inst : label is 0; + attribute C_HAS_RD_DATA_COUNT : integer; + attribute C_HAS_RD_DATA_COUNT of fifo_gen_inst : label is 0; + attribute C_HAS_RD_RST : integer; + attribute C_HAS_RD_RST of fifo_gen_inst : label is 0; + attribute C_HAS_RST : integer; + attribute C_HAS_RST of fifo_gen_inst : label is 1; + attribute C_HAS_SLAVE_CE : integer; + attribute C_HAS_SLAVE_CE of fifo_gen_inst : label is 0; + attribute C_HAS_SRST : integer; + attribute C_HAS_SRST of fifo_gen_inst : label is 0; + attribute C_HAS_UNDERFLOW : integer; + attribute C_HAS_UNDERFLOW of fifo_gen_inst : label is 0; + attribute C_HAS_VALID : integer; + attribute C_HAS_VALID of fifo_gen_inst : label is 0; + attribute C_HAS_WR_ACK : integer; + attribute C_HAS_WR_ACK of fifo_gen_inst : label is 0; + attribute C_HAS_WR_DATA_COUNT : integer; + attribute C_HAS_WR_DATA_COUNT of fifo_gen_inst : label is 0; + attribute C_HAS_WR_RST : integer; + attribute C_HAS_WR_RST of fifo_gen_inst : label is 0; + attribute C_IMPLEMENTATION_TYPE : integer; + attribute C_IMPLEMENTATION_TYPE of fifo_gen_inst : label is 0; + attribute C_IMPLEMENTATION_TYPE_AXIS : integer; + attribute C_IMPLEMENTATION_TYPE_AXIS of fifo_gen_inst : label is 1; + attribute C_IMPLEMENTATION_TYPE_RACH : integer; + attribute C_IMPLEMENTATION_TYPE_RACH of fifo_gen_inst : label is 1; + attribute C_IMPLEMENTATION_TYPE_RDCH : integer; + attribute C_IMPLEMENTATION_TYPE_RDCH of fifo_gen_inst : label is 1; + attribute C_IMPLEMENTATION_TYPE_WACH : integer; + attribute C_IMPLEMENTATION_TYPE_WACH of fifo_gen_inst : label is 1; + attribute C_IMPLEMENTATION_TYPE_WDCH : integer; + attribute C_IMPLEMENTATION_TYPE_WDCH of fifo_gen_inst : label is 1; + attribute C_IMPLEMENTATION_TYPE_WRCH : integer; + attribute C_IMPLEMENTATION_TYPE_WRCH of fifo_gen_inst : label is 1; + attribute C_INIT_WR_PNTR_VAL : integer; + attribute C_INIT_WR_PNTR_VAL of fifo_gen_inst : label is 0; + attribute C_INTERFACE_TYPE : integer; + attribute C_INTERFACE_TYPE of fifo_gen_inst : label is 0; + attribute C_MEMORY_TYPE : integer; + attribute C_MEMORY_TYPE of fifo_gen_inst : label is 2; + attribute C_MIF_FILE_NAME : string; + attribute C_MIF_FILE_NAME of fifo_gen_inst : label is "BlankString"; + attribute C_MSGON_VAL : integer; + attribute C_MSGON_VAL of fifo_gen_inst : label is 1; + attribute C_OPTIMIZATION_MODE : integer; + attribute C_OPTIMIZATION_MODE of fifo_gen_inst : label is 0; + attribute C_OVERFLOW_LOW : integer; + attribute C_OVERFLOW_LOW of fifo_gen_inst : label is 0; + attribute C_POWER_SAVING_MODE : integer; + attribute C_POWER_SAVING_MODE of fifo_gen_inst : label is 0; + attribute C_PRELOAD_LATENCY : integer; + attribute C_PRELOAD_LATENCY of fifo_gen_inst : label is 0; + attribute C_PRELOAD_REGS : integer; + attribute C_PRELOAD_REGS of fifo_gen_inst : label is 1; + attribute C_PRIM_FIFO_TYPE : string; + attribute C_PRIM_FIFO_TYPE of fifo_gen_inst : label is "512x36"; + attribute C_PRIM_FIFO_TYPE_AXIS : string; + attribute C_PRIM_FIFO_TYPE_AXIS of fifo_gen_inst : label is "512x36"; + attribute C_PRIM_FIFO_TYPE_RACH : string; + attribute C_PRIM_FIFO_TYPE_RACH of fifo_gen_inst : label is "512x36"; + attribute C_PRIM_FIFO_TYPE_RDCH : string; + attribute C_PRIM_FIFO_TYPE_RDCH of fifo_gen_inst : label is "512x36"; + attribute C_PRIM_FIFO_TYPE_WACH : string; + attribute C_PRIM_FIFO_TYPE_WACH of fifo_gen_inst : label is "512x36"; + attribute C_PRIM_FIFO_TYPE_WDCH : string; + attribute C_PRIM_FIFO_TYPE_WDCH of fifo_gen_inst : label is "512x36"; + attribute C_PRIM_FIFO_TYPE_WRCH : string; + attribute C_PRIM_FIFO_TYPE_WRCH of fifo_gen_inst : label is "512x36"; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of fifo_gen_inst : label is 4; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of fifo_gen_inst : label is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of fifo_gen_inst : label is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of fifo_gen_inst : label is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of fifo_gen_inst : label is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of fifo_gen_inst : label is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of fifo_gen_inst : label is 1022; + attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer; + attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of fifo_gen_inst : label is 5; + attribute C_PROG_EMPTY_TYPE : integer; + attribute C_PROG_EMPTY_TYPE of fifo_gen_inst : label is 0; + attribute C_PROG_EMPTY_TYPE_AXIS : integer; + attribute C_PROG_EMPTY_TYPE_AXIS of fifo_gen_inst : label is 0; + attribute C_PROG_EMPTY_TYPE_RACH : integer; + attribute C_PROG_EMPTY_TYPE_RACH of fifo_gen_inst : label is 0; + attribute C_PROG_EMPTY_TYPE_RDCH : integer; + attribute C_PROG_EMPTY_TYPE_RDCH of fifo_gen_inst : label is 0; + attribute C_PROG_EMPTY_TYPE_WACH : integer; + attribute C_PROG_EMPTY_TYPE_WACH of fifo_gen_inst : label is 0; + attribute C_PROG_EMPTY_TYPE_WDCH : integer; + attribute C_PROG_EMPTY_TYPE_WDCH of fifo_gen_inst : label is 0; + attribute C_PROG_EMPTY_TYPE_WRCH : integer; + attribute C_PROG_EMPTY_TYPE_WRCH of fifo_gen_inst : label is 0; + attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL of fifo_gen_inst : label is 31; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of fifo_gen_inst : label is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of fifo_gen_inst : label is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of fifo_gen_inst : label is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of fifo_gen_inst : label is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of fifo_gen_inst : label is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of fifo_gen_inst : label is 1023; + attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer; + attribute C_PROG_FULL_THRESH_NEGATE_VAL of fifo_gen_inst : label is 30; + attribute C_PROG_FULL_TYPE : integer; + attribute C_PROG_FULL_TYPE of fifo_gen_inst : label is 0; + attribute C_PROG_FULL_TYPE_AXIS : integer; + attribute C_PROG_FULL_TYPE_AXIS of fifo_gen_inst : label is 0; + attribute C_PROG_FULL_TYPE_RACH : integer; + attribute C_PROG_FULL_TYPE_RACH of fifo_gen_inst : label is 0; + attribute C_PROG_FULL_TYPE_RDCH : integer; + attribute C_PROG_FULL_TYPE_RDCH of fifo_gen_inst : label is 0; + attribute C_PROG_FULL_TYPE_WACH : integer; + attribute C_PROG_FULL_TYPE_WACH of fifo_gen_inst : label is 0; + attribute C_PROG_FULL_TYPE_WDCH : integer; + attribute C_PROG_FULL_TYPE_WDCH of fifo_gen_inst : label is 0; + attribute C_PROG_FULL_TYPE_WRCH : integer; + attribute C_PROG_FULL_TYPE_WRCH of fifo_gen_inst : label is 0; + attribute C_RACH_TYPE : integer; + attribute C_RACH_TYPE of fifo_gen_inst : label is 0; + attribute C_RDCH_TYPE : integer; + attribute C_RDCH_TYPE of fifo_gen_inst : label is 0; + attribute C_RD_DATA_COUNT_WIDTH : integer; + attribute C_RD_DATA_COUNT_WIDTH of fifo_gen_inst : label is 6; + attribute C_RD_DEPTH : integer; + attribute C_RD_DEPTH of fifo_gen_inst : label is 32; + attribute C_RD_FREQ : integer; + attribute C_RD_FREQ of fifo_gen_inst : label is 1; + attribute C_RD_PNTR_WIDTH : integer; + attribute C_RD_PNTR_WIDTH of fifo_gen_inst : label is 5; + attribute C_REG_SLICE_MODE_AXIS : integer; + attribute C_REG_SLICE_MODE_AXIS of fifo_gen_inst : label is 0; + attribute C_REG_SLICE_MODE_RACH : integer; + attribute C_REG_SLICE_MODE_RACH of fifo_gen_inst : label is 0; + attribute C_REG_SLICE_MODE_RDCH : integer; + attribute C_REG_SLICE_MODE_RDCH of fifo_gen_inst : label is 0; + attribute C_REG_SLICE_MODE_WACH : integer; + attribute C_REG_SLICE_MODE_WACH of fifo_gen_inst : label is 0; + attribute C_REG_SLICE_MODE_WDCH : integer; + attribute C_REG_SLICE_MODE_WDCH of fifo_gen_inst : label is 0; + attribute C_REG_SLICE_MODE_WRCH : integer; + attribute C_REG_SLICE_MODE_WRCH of fifo_gen_inst : label is 0; + attribute C_SELECT_XPM : integer; + attribute C_SELECT_XPM of fifo_gen_inst : label is 0; + attribute C_SYNCHRONIZER_STAGE : integer; + attribute C_SYNCHRONIZER_STAGE of fifo_gen_inst : label is 3; + attribute C_UNDERFLOW_LOW : integer; + attribute C_UNDERFLOW_LOW of fifo_gen_inst : label is 0; + attribute C_USE_COMMON_OVERFLOW : integer; + attribute C_USE_COMMON_OVERFLOW of fifo_gen_inst : label is 0; + attribute C_USE_COMMON_UNDERFLOW : integer; + attribute C_USE_COMMON_UNDERFLOW of fifo_gen_inst : label is 0; + attribute C_USE_DEFAULT_SETTINGS : integer; + attribute C_USE_DEFAULT_SETTINGS of fifo_gen_inst : label is 0; + attribute C_USE_DOUT_RST : integer; + attribute C_USE_DOUT_RST of fifo_gen_inst : label is 0; + attribute C_USE_ECC : integer; + attribute C_USE_ECC of fifo_gen_inst : label is 0; + attribute C_USE_ECC_AXIS : integer; + attribute C_USE_ECC_AXIS of fifo_gen_inst : label is 0; + attribute C_USE_ECC_RACH : integer; + attribute C_USE_ECC_RACH of fifo_gen_inst : label is 0; + attribute C_USE_ECC_RDCH : integer; + attribute C_USE_ECC_RDCH of fifo_gen_inst : label is 0; + attribute C_USE_ECC_WACH : integer; + attribute C_USE_ECC_WACH of fifo_gen_inst : label is 0; + attribute C_USE_ECC_WDCH : integer; + attribute C_USE_ECC_WDCH of fifo_gen_inst : label is 0; + attribute C_USE_ECC_WRCH : integer; + attribute C_USE_ECC_WRCH of fifo_gen_inst : label is 0; + attribute C_USE_EMBEDDED_REG : integer; + attribute C_USE_EMBEDDED_REG of fifo_gen_inst : label is 0; + attribute C_USE_FIFO16_FLAGS : integer; + attribute C_USE_FIFO16_FLAGS of fifo_gen_inst : label is 0; + attribute C_USE_FWFT_DATA_COUNT : integer; + attribute C_USE_FWFT_DATA_COUNT of fifo_gen_inst : label is 1; + attribute C_USE_PIPELINE_REG : integer; + attribute C_USE_PIPELINE_REG of fifo_gen_inst : label is 0; + attribute C_VALID_LOW : integer; + attribute C_VALID_LOW of fifo_gen_inst : label is 0; + attribute C_WACH_TYPE : integer; + attribute C_WACH_TYPE of fifo_gen_inst : label is 0; + attribute C_WDCH_TYPE : integer; + attribute C_WDCH_TYPE of fifo_gen_inst : label is 0; + attribute C_WRCH_TYPE : integer; + attribute C_WRCH_TYPE of fifo_gen_inst : label is 0; + attribute C_WR_ACK_LOW : integer; + attribute C_WR_ACK_LOW of fifo_gen_inst : label is 0; + attribute C_WR_DATA_COUNT_WIDTH : integer; + attribute C_WR_DATA_COUNT_WIDTH of fifo_gen_inst : label is 6; + attribute C_WR_DEPTH : integer; + attribute C_WR_DEPTH of fifo_gen_inst : label is 32; + attribute C_WR_DEPTH_AXIS : integer; + attribute C_WR_DEPTH_AXIS of fifo_gen_inst : label is 1024; + attribute C_WR_DEPTH_RACH : integer; + attribute C_WR_DEPTH_RACH of fifo_gen_inst : label is 16; + attribute C_WR_DEPTH_RDCH : integer; + attribute C_WR_DEPTH_RDCH of fifo_gen_inst : label is 1024; + attribute C_WR_DEPTH_WACH : integer; + attribute C_WR_DEPTH_WACH of fifo_gen_inst : label is 16; + attribute C_WR_DEPTH_WDCH : integer; + attribute C_WR_DEPTH_WDCH of fifo_gen_inst : label is 1024; + attribute C_WR_DEPTH_WRCH : integer; + attribute C_WR_DEPTH_WRCH of fifo_gen_inst : label is 16; + attribute C_WR_FREQ : integer; + attribute C_WR_FREQ of fifo_gen_inst : label is 1; + attribute C_WR_PNTR_WIDTH : integer; + attribute C_WR_PNTR_WIDTH of fifo_gen_inst : label is 5; + attribute C_WR_PNTR_WIDTH_AXIS : integer; + attribute C_WR_PNTR_WIDTH_AXIS of fifo_gen_inst : label is 10; + attribute C_WR_PNTR_WIDTH_RACH : integer; + attribute C_WR_PNTR_WIDTH_RACH of fifo_gen_inst : label is 4; + attribute C_WR_PNTR_WIDTH_RDCH : integer; + attribute C_WR_PNTR_WIDTH_RDCH of fifo_gen_inst : label is 10; + attribute C_WR_PNTR_WIDTH_WACH : integer; + attribute C_WR_PNTR_WIDTH_WACH of fifo_gen_inst : label is 4; + attribute C_WR_PNTR_WIDTH_WDCH : integer; + attribute C_WR_PNTR_WIDTH_WDCH of fifo_gen_inst : label is 10; + attribute C_WR_PNTR_WIDTH_WRCH : integer; + attribute C_WR_PNTR_WIDTH_WRCH of fifo_gen_inst : label is 4; + attribute C_WR_RESPONSE_LATENCY : integer; + attribute C_WR_RESPONSE_LATENCY of fifo_gen_inst : label is 1; + attribute SOFT_HLUTNM of m_axi_wvalid_INST_0 : label is "soft_lutpair34"; + attribute SOFT_HLUTNM of \queue_id[0]_i_1\ : label is "soft_lutpair35"; + attribute SOFT_HLUTNM of s_axi_wready_INST_0 : label is "soft_lutpair34"; + attribute SOFT_HLUTNM of split_in_progress_i_1 : label is "soft_lutpair33"; +begin + SR(0) <= \^sr\(0); + din(3 downto 0) <= \^din\(3 downto 0); + empty <= \^empty\; + full <= \^full\; + wr_en <= \^wr_en\; +S_AXI_AREADY_I_i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => aresetn, + O => \^sr\(0) + ); +\cmd_depth[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"69" + ) + port map ( + I0 => Q(0), + I1 => \cmd_depth[4]_i_2_n_0\, + I2 => Q(1), + O => D(0) + ); +\cmd_depth[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"78E1" + ) + port map ( + I0 => Q(0), + I1 => \cmd_depth[4]_i_2_n_0\, + I2 => Q(2), + I3 => Q(1), + O => D(1) + ); +\cmd_depth[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7F80FE01" + ) + port map ( + I0 => \cmd_depth[4]_i_2_n_0\, + I1 => Q(0), + I2 => Q(1), + I3 => Q(3), + I4 => Q(2), + O => D(2) + ); +\cmd_depth[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFF8000FFFE0001" + ) + port map ( + I0 => Q(1), + I1 => Q(0), + I2 => \cmd_depth[4]_i_2_n_0\, + I3 => Q(2), + I4 => Q(4), + I5 => Q(3), + O => D(3) + ); +\cmd_depth[4]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^wr_en\, + I1 => wr_cmd_ready, + O => \cmd_depth[4]_i_2_n_0\ + ); +\cmd_depth[5]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^wr_en\, + I1 => wr_cmd_ready, + O => E(0) + ); +\cmd_depth[5]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"78E1" + ) + port map ( + I0 => \cmd_depth[5]_i_3_n_0\, + I1 => Q(3), + I2 => Q(5), + I3 => Q(4), + O => D(4) + ); +\cmd_depth[5]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5D55555555554544" + ) + port map ( + I0 => Q(3), + I1 => Q(2), + I2 => wr_cmd_ready, + I3 => \^wr_en\, + I4 => Q(0), + I5 => Q(1), + O => \cmd_depth[5]_i_3_n_0\ + ); +fifo_gen_inst: entity work.\Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__1\ + port map ( + almost_empty => NLW_fifo_gen_inst_almost_empty_UNCONNECTED, + almost_full => NLW_fifo_gen_inst_almost_full_UNCONNECTED, + axi_ar_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED(4 downto 0), + axi_ar_dbiterr => NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED, + axi_ar_injectdbiterr => '0', + axi_ar_injectsbiterr => '0', + axi_ar_overflow => NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED, + axi_ar_prog_empty => NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED, + axi_ar_prog_empty_thresh(3 downto 0) => B"0000", + axi_ar_prog_full => NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED, + axi_ar_prog_full_thresh(3 downto 0) => B"0000", + axi_ar_rd_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED(4 downto 0), + axi_ar_sbiterr => NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED, + axi_ar_underflow => NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED, + axi_ar_wr_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED(4 downto 0), + axi_aw_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED(4 downto 0), + axi_aw_dbiterr => NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED, + axi_aw_injectdbiterr => '0', + axi_aw_injectsbiterr => '0', + axi_aw_overflow => NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED, + axi_aw_prog_empty => NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED, + axi_aw_prog_empty_thresh(3 downto 0) => B"0000", + axi_aw_prog_full => NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED, + axi_aw_prog_full_thresh(3 downto 0) => B"0000", + axi_aw_rd_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED(4 downto 0), + axi_aw_sbiterr => NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED, + axi_aw_underflow => NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED, + axi_aw_wr_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED(4 downto 0), + axi_b_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED(4 downto 0), + axi_b_dbiterr => NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED, + axi_b_injectdbiterr => '0', + axi_b_injectsbiterr => '0', + axi_b_overflow => NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED, + axi_b_prog_empty => NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED, + axi_b_prog_empty_thresh(3 downto 0) => B"0000", + axi_b_prog_full => NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED, + axi_b_prog_full_thresh(3 downto 0) => B"0000", + axi_b_rd_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED(4 downto 0), + axi_b_sbiterr => NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED, + axi_b_underflow => NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED, + axi_b_wr_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED(4 downto 0), + axi_r_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED(10 downto 0), + axi_r_dbiterr => NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED, + axi_r_injectdbiterr => '0', + axi_r_injectsbiterr => '0', + axi_r_overflow => NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED, + axi_r_prog_empty => NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED, + axi_r_prog_empty_thresh(9 downto 0) => B"0000000000", + axi_r_prog_full => NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED, + axi_r_prog_full_thresh(9 downto 0) => B"0000000000", + axi_r_rd_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED(10 downto 0), + axi_r_sbiterr => NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED, + axi_r_underflow => NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED, + axi_r_wr_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED(10 downto 0), + axi_w_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED(10 downto 0), + axi_w_dbiterr => NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED, + axi_w_injectdbiterr => '0', + axi_w_injectsbiterr => '0', + axi_w_overflow => NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED, + axi_w_prog_empty => NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED, + axi_w_prog_empty_thresh(9 downto 0) => B"0000000000", + axi_w_prog_full => NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED, + axi_w_prog_full_thresh(9 downto 0) => B"0000000000", + axi_w_rd_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED(10 downto 0), + axi_w_sbiterr => NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED, + axi_w_underflow => NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED, + axi_w_wr_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED(10 downto 0), + axis_data_count(10 downto 0) => NLW_fifo_gen_inst_axis_data_count_UNCONNECTED(10 downto 0), + axis_dbiterr => NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED, + axis_injectdbiterr => '0', + axis_injectsbiterr => '0', + axis_overflow => NLW_fifo_gen_inst_axis_overflow_UNCONNECTED, + axis_prog_empty => NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED, + axis_prog_empty_thresh(9 downto 0) => B"0000000000", + axis_prog_full => NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED, + axis_prog_full_thresh(9 downto 0) => B"0000000000", + axis_rd_data_count(10 downto 0) => NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED(10 downto 0), + axis_sbiterr => NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED, + axis_underflow => NLW_fifo_gen_inst_axis_underflow_UNCONNECTED, + axis_wr_data_count(10 downto 0) => NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED(10 downto 0), + backup => '0', + backup_marker => '0', + clk => aclk, + data_count(5 downto 0) => NLW_fifo_gen_inst_data_count_UNCONNECTED(5 downto 0), + dbiterr => NLW_fifo_gen_inst_dbiterr_UNCONNECTED, + din(4) => \S_AXI_AID_Q_reg[0]\, + din(3 downto 0) => \^din\(3 downto 0), + dout(4 downto 0) => dout(4 downto 0), + empty => \^empty\, + full => \^full\, + injectdbiterr => '0', + injectsbiterr => '0', + int_clk => '0', + m_aclk => '0', + m_aclk_en => '0', + m_axi_araddr(31 downto 0) => NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED(31 downto 0), + m_axi_arburst(1 downto 0) => NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED(1 downto 0), + m_axi_arcache(3 downto 0) => NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED(3 downto 0), + m_axi_arid(3 downto 0) => NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED(3 downto 0), + m_axi_arlen(7 downto 0) => NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED(7 downto 0), + m_axi_arlock(1 downto 0) => NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED(1 downto 0), + m_axi_arprot(2 downto 0) => NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED(2 downto 0), + m_axi_arqos(3 downto 0) => NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED(3 downto 0), + m_axi_arready => '0', + m_axi_arregion(3 downto 0) => NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED(3 downto 0), + m_axi_arsize(2 downto 0) => NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED(2 downto 0), + m_axi_aruser(0) => NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED(0), + m_axi_arvalid => NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED, + m_axi_awaddr(31 downto 0) => NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED(31 downto 0), + m_axi_awburst(1 downto 0) => NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED(1 downto 0), + m_axi_awcache(3 downto 0) => NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED(3 downto 0), + m_axi_awid(3 downto 0) => NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED(3 downto 0), + m_axi_awlen(7 downto 0) => NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED(7 downto 0), + m_axi_awlock(1 downto 0) => NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED(1 downto 0), + m_axi_awprot(2 downto 0) => NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED(2 downto 0), + m_axi_awqos(3 downto 0) => NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED(3 downto 0), + m_axi_awready => '0', + m_axi_awregion(3 downto 0) => NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED(3 downto 0), + m_axi_awsize(2 downto 0) => NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED(2 downto 0), + m_axi_awuser(0) => NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED(0), + m_axi_awvalid => NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED, + m_axi_bid(3 downto 0) => B"0000", + m_axi_bready => NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED, + m_axi_bresp(1 downto 0) => B"00", + m_axi_buser(0) => '0', + m_axi_bvalid => '0', + m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + m_axi_rid(3 downto 0) => B"0000", + m_axi_rlast => '0', + m_axi_rready => NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED, + m_axi_rresp(1 downto 0) => B"00", + m_axi_ruser(0) => '0', + m_axi_rvalid => '0', + m_axi_wdata(63 downto 0) => NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED(63 downto 0), + m_axi_wid(3 downto 0) => NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED(3 downto 0), + m_axi_wlast => NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED, + m_axi_wready => '0', + m_axi_wstrb(7 downto 0) => NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED(7 downto 0), + m_axi_wuser(0) => NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED(0), + m_axi_wvalid => NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED, + m_axis_tdata(63 downto 0) => NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED(63 downto 0), + m_axis_tdest(3 downto 0) => NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED(3 downto 0), + m_axis_tid(7 downto 0) => NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED(7 downto 0), + m_axis_tkeep(3 downto 0) => NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED(3 downto 0), + m_axis_tlast => NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED, + m_axis_tready => '0', + m_axis_tstrb(3 downto 0) => NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED(3 downto 0), + m_axis_tuser(3 downto 0) => NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED(3 downto 0), + m_axis_tvalid => NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED, + overflow => NLW_fifo_gen_inst_overflow_UNCONNECTED, + prog_empty => NLW_fifo_gen_inst_prog_empty_UNCONNECTED, + prog_empty_thresh(4 downto 0) => B"00000", + prog_empty_thresh_assert(4 downto 0) => B"00000", + prog_empty_thresh_negate(4 downto 0) => B"00000", + prog_full => NLW_fifo_gen_inst_prog_full_UNCONNECTED, + prog_full_thresh(4 downto 0) => B"00000", + prog_full_thresh_assert(4 downto 0) => B"00000", + prog_full_thresh_negate(4 downto 0) => B"00000", + rd_clk => '0', + rd_data_count(5 downto 0) => NLW_fifo_gen_inst_rd_data_count_UNCONNECTED(5 downto 0), + rd_en => wr_cmd_ready, + rd_rst => '0', + rd_rst_busy => NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED, + rst => \^sr\(0), + s_aclk => '0', + s_aclk_en => '0', + s_aresetn => '0', + s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", + s_axi_arburst(1 downto 0) => B"00", + s_axi_arcache(3 downto 0) => B"0000", + s_axi_arid(3 downto 0) => B"0000", + s_axi_arlen(7 downto 0) => B"00000000", + s_axi_arlock(1 downto 0) => B"00", + s_axi_arprot(2 downto 0) => B"000", + s_axi_arqos(3 downto 0) => B"0000", + s_axi_arready => NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED, + s_axi_arregion(3 downto 0) => B"0000", + s_axi_arsize(2 downto 0) => B"000", + s_axi_aruser(0) => '0', + s_axi_arvalid => '0', + s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", + s_axi_awburst(1 downto 0) => B"00", + s_axi_awcache(3 downto 0) => B"0000", + s_axi_awid(3 downto 0) => B"0000", + s_axi_awlen(7 downto 0) => B"00000000", + s_axi_awlock(1 downto 0) => B"00", + s_axi_awprot(2 downto 0) => B"000", + s_axi_awqos(3 downto 0) => B"0000", + s_axi_awready => NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED, + s_axi_awregion(3 downto 0) => B"0000", + s_axi_awsize(2 downto 0) => B"000", + s_axi_awuser(0) => '0', + s_axi_awvalid => '0', + s_axi_bid(3 downto 0) => NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED(3 downto 0), + s_axi_bready => '0', + s_axi_bresp(1 downto 0) => NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED(1 downto 0), + s_axi_buser(0) => NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED(0), + s_axi_bvalid => NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED, + s_axi_rdata(63 downto 0) => NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED(63 downto 0), + s_axi_rid(3 downto 0) => NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED(3 downto 0), + s_axi_rlast => NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED, + s_axi_rready => '0', + s_axi_rresp(1 downto 0) => NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED(1 downto 0), + s_axi_ruser(0) => NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED(0), + s_axi_rvalid => NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED, + s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + s_axi_wid(3 downto 0) => B"0000", + s_axi_wlast => '0', + s_axi_wready => NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED, + s_axi_wstrb(7 downto 0) => B"00000000", + s_axi_wuser(0) => '0', + s_axi_wvalid => '0', + s_axis_tdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + s_axis_tdest(3 downto 0) => B"0000", + s_axis_tid(7 downto 0) => B"00000000", + s_axis_tkeep(3 downto 0) => B"0000", + s_axis_tlast => '0', + s_axis_tready => NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED, + s_axis_tstrb(3 downto 0) => B"0000", + s_axis_tuser(3 downto 0) => B"0000", + s_axis_tvalid => '0', + sbiterr => NLW_fifo_gen_inst_sbiterr_UNCONNECTED, + sleep => '0', + srst => '0', + underflow => NLW_fifo_gen_inst_underflow_UNCONNECTED, + valid => NLW_fifo_gen_inst_valid_UNCONNECTED, + wr_ack => NLW_fifo_gen_inst_wr_ack_UNCONNECTED, + wr_clk => '0', + wr_data_count(5 downto 0) => NLW_fifo_gen_inst_wr_data_count_UNCONNECTED(5 downto 0), + wr_en => \^wr_en\, + wr_rst => '0', + wr_rst_busy => NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED + ); +fifo_gen_inst_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000540000" + ) + port map ( + I0 => \^full\, + I1 => split_in_progress_reg_0, + I2 => \allow_split_cmd__1\, + I3 => ram_full_i_reg, + I4 => command_ongoing, + I5 => cmd_push_block, + O => \^wr_en\ + ); +\m_axi_awlen[0]_INST_0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EEEEEEEEEEEEEEEA" + ) + port map ( + I0 => \S_AXI_ALEN_Q_reg[3]\(0), + I1 => need_to_split_q, + I2 => \pushed_commands_reg[3]\(2), + I3 => \pushed_commands_reg[3]\(3), + I4 => \pushed_commands_reg[3]\(1), + I5 => \pushed_commands_reg[3]\(0), + O => \^din\(0) + ); +\m_axi_awlen[1]_INST_0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EEEEEEEEEEEEEEEA" + ) + port map ( + I0 => \S_AXI_ALEN_Q_reg[3]\(1), + I1 => need_to_split_q, + I2 => \pushed_commands_reg[3]\(2), + I3 => \pushed_commands_reg[3]\(3), + I4 => \pushed_commands_reg[3]\(1), + I5 => \pushed_commands_reg[3]\(0), + O => \^din\(1) + ); +\m_axi_awlen[2]_INST_0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EEEEEEEEEEEEEEEA" + ) + port map ( + I0 => \S_AXI_ALEN_Q_reg[3]\(2), + I1 => need_to_split_q, + I2 => \pushed_commands_reg[3]\(2), + I3 => \pushed_commands_reg[3]\(3), + I4 => \pushed_commands_reg[3]\(1), + I5 => \pushed_commands_reg[3]\(0), + O => \^din\(2) + ); +\m_axi_awlen[3]_INST_0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EEEEEEEEEEEEEEEA" + ) + port map ( + I0 => \S_AXI_ALEN_Q_reg[3]\(3), + I1 => need_to_split_q, + I2 => \pushed_commands_reg[3]\(2), + I3 => \pushed_commands_reg[3]\(3), + I4 => \pushed_commands_reg[3]\(1), + I5 => \pushed_commands_reg[3]\(0), + O => \^din\(3) + ); +m_axi_wvalid_INST_0: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => s_axi_wvalid, + I1 => \^empty\, + O => m_axi_wvalid + ); +multiple_id_non_split_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000BEAAAAAA" + ) + port map ( + I0 => multiple_id_non_split, + I1 => queue_id, + I2 => \S_AXI_AID_Q_reg[0]\, + I3 => \^wr_en\, + I4 => split_in_progress_reg_0, + I5 => cmd_empty_reg, + O => multiple_id_non_split_reg + ); +\queue_id[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \S_AXI_AID_Q_reg[0]\, + I1 => \^wr_en\, + I2 => queue_id, + O => \queue_id_reg[0]\ ); -inst_fifo_gen: entity work.Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3_synth - port map ( - clk => clk, - din(0) => din(0), - dout(0) => dout(0), - empty => empty, - full => full, - rd_en => rd_en, - rst => rst, - wr_en => wr_en +s_axi_wready_INST_0: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => \^empty\, + I1 => s_axi_wvalid, + I2 => m_axi_wready, + O => s_axi_wready + ); +split_in_progress_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"00EA" + ) + port map ( + I0 => split_in_progress_reg_1, + I1 => \^wr_en\, + I2 => \allow_split_cmd__1\, + I3 => cmd_empty_reg, + O => split_in_progress_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen is +entity \Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen__parameterized0\ is port ( - SR : out STD_LOGIC_VECTOR ( 0 to 0 ); din : out STD_LOGIC_VECTOR ( 0 to 0 ); wr_en : out STD_LOGIC; rd_en : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 4 downto 0 ); - \cmd_depth_reg[1]\ : out STD_LOGIC; - \pushed_commands_reg[0]\ : out STD_LOGIC; - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_arvalid : out STD_LOGIC; + split_ongoing_reg : out STD_LOGIC; + m_axi_rready : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rlast : out STD_LOGIC; - m_axi_rready : out STD_LOGIC; - S_AXI_AREADY_I_reg : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); cmd_push_block_reg : out STD_LOGIC; + \cmd_depth_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_arvalid : out STD_LOGIC; + S_AXI_AREADY_I_reg : out STD_LOGIC; \queue_id_reg[0]\ : out STD_LOGIC; command_ongoing_reg : out STD_LOGIC; multiple_id_non_split_reg : out STD_LOGIC; split_in_progress_reg : out STD_LOGIC; aclk : in STD_LOGIC; + aresetn_0 : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 5 downto 0 ); - need_to_split_q : in STD_LOGIC; cmd_push_block : in STD_LOGIC; command_ongoing : in STD_LOGIC; - m_axi_arready : in STD_LOGIC; - \cmd_depth_reg[3]\ : in STD_LOGIC; - \cmd_depth_reg[1]_0\ : in STD_LOGIC; - m_axi_rlast : in STD_LOGIC; - s_axi_rready : in STD_LOGIC; - m_axi_rvalid : in STD_LOGIC; - multiple_id_non_split : in STD_LOGIC; + almost_empty : in STD_LOGIC; cmd_empty : in STD_LOGIC; - \S_AXI_AID_Q_reg[0]\ : in STD_LOGIC; - queue_id : in STD_LOGIC; - split_in_progress_reg_0 : in STD_LOGIC; aresetn : in STD_LOGIC; - almost_empty : in STD_LOGIC; + need_to_split_q : in STD_LOGIC; access_is_incr_q : in STD_LOGIC; - num_transactions_q : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \num_transactions_q_reg[3]\ : in STD_LOGIC; \pushed_commands_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); - \areset_d_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); - S_AXI_AREADY_I_reg_0 : in STD_LOGIC; + m_axi_rvalid : in STD_LOGIC; + s_axi_rready : in STD_LOGIC; + m_axi_rlast : in STD_LOGIC; + m_axi_arready : in STD_LOGIC; + multiple_id_non_split : in STD_LOGIC; + \S_AXI_AID_Q_reg[0]\ : in STD_LOGIC; + \queue_id_reg[0]_0\ : in STD_LOGIC; + split_in_progress_reg_0 : in STD_LOGIC; + \num_transactions_q_reg[0]\ : in STD_LOGIC; + \num_transactions_q_reg[2]\ : in STD_LOGIC; + \num_transactions_q_reg[1]\ : in STD_LOGIC; + \pushed_commands_reg[3]_0\ : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; - \areset_d_reg[1]_0\ : in STD_LOGIC; - \S_AXI_AID_Q_reg[0]_0\ : in STD_LOGIC; - cmd_empty_reg : in STD_LOGIC + S_AXI_AREADY_I_reg_0 : in STD_LOGIC; + areset_d : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \areset_d_reg[1]\ : in STD_LOGIC; + split_in_progress_reg_1 : in STD_LOGIC; + \allow_split_cmd__1\ : in STD_LOGIC ); -end Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen__parameterized0\ : entity is "axi_data_fifo_v2_1_10_fifo_gen"; +end \Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen__parameterized0\; -architecture STRUCTURE of Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen is - signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal S_AXI_AREADY_I_i_3_n_0 : STD_LOGIC; - signal S_AXI_AREADY_I_i_4_n_0 : STD_LOGIC; - signal \^cmd_depth_reg[1]\ : STD_LOGIC; +architecture STRUCTURE of \Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen__parameterized0\ is + signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \cmd_depth[4]_i_2__0_n_0\ : STD_LOGIC; + signal \cmd_depth[5]_i_3__0_n_0\ : STD_LOGIC; signal \^din\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal empty : STD_LOGIC; signal full : STD_LOGIC; signal m_axi_arvalid_INST_0_i_1_n_0 : STD_LOGIC; - signal \^pushed_commands_reg[0]\ : STD_LOGIC; + signal \multiple_id_non_split_i_3__0_n_0\ : STD_LOGIC; signal rd_cmd_split : STD_LOGIC; signal \^rd_en\ : STD_LOGIC; - signal split_in_progress : STD_LOGIC; - signal split_in_progress_i_3_n_0 : STD_LOGIC; + signal \^split_ongoing_reg\ : STD_LOGIC; signal \^wr_en\ : STD_LOGIC; signal NLW_fifo_gen_inst_almost_empty_UNCONNECTED : STD_LOGIC; signal NLW_fifo_gen_inst_almost_full_UNCONNECTED : STD_LOGIC; @@ -3271,12 +12281,12 @@ architecture STRUCTURE of Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen is signal NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_fifo_gen_inst_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of S_AXI_AREADY_I_i_1 : label is "soft_lutpair7"; - attribute SOFT_HLUTNM of \cmd_depth[2]_i_1\ : label is "soft_lutpair6"; - attribute SOFT_HLUTNM of \cmd_depth[3]_i_1\ : label is "soft_lutpair6"; - attribute SOFT_HLUTNM of \cmd_depth[5]_i_1\ : label is "soft_lutpair4"; - attribute SOFT_HLUTNM of cmd_empty_i_3 : label is "soft_lutpair8"; - attribute SOFT_HLUTNM of cmd_push_block_i_1 : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of \cmd_depth[1]_i_1__0\ : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of \cmd_depth[2]_i_1__0\ : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of \cmd_depth[3]_i_1__0\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \cmd_depth[4]_i_2__0\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \cmd_depth[5]_i_1__0\ : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of \cmd_depth[5]_i_3__0\ : label is "soft_lutpair5"; attribute C_ADD_NGC_CONSTRAINT : integer; attribute C_ADD_NGC_CONSTRAINT of fifo_gen_inst : label is 0; attribute C_APPLICATION_TYPE_AXIS : integer; @@ -3681,718 +12691,3940 @@ architecture STRUCTURE of Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen is attribute C_WR_PNTR_WIDTH_WRCH of fifo_gen_inst : label is 4; attribute C_WR_RESPONSE_LATENCY : integer; attribute C_WR_RESPONSE_LATENCY of fifo_gen_inst : label is 1; - attribute SOFT_HLUTNM of fifo_gen_inst_i_2 : label is "soft_lutpair5"; - attribute SOFT_HLUTNM of fifo_gen_inst_i_3 : label is "soft_lutpair4"; - attribute SOFT_HLUTNM of m_axi_arvalid_INST_0 : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of \fifo_gen_inst_i_2__0\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \fifo_gen_inst_i_3__0\ : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of m_axi_arvalid_INST_0 : label is "soft_lutpair6"; attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair9"; attribute SOFT_HLUTNM of s_axi_rvalid_INST_0 : label is "soft_lutpair9"; - attribute SOFT_HLUTNM of split_ongoing_i_1 : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \split_ongoing_i_1__0\ : label is "soft_lutpair4"; +begin + E(0) <= \^e\(0); + din(0) <= \^din\(0); + rd_en <= \^rd_en\; + split_ongoing_reg <= \^split_ongoing_reg\; + wr_en <= \^wr_en\; +\S_AXI_AREADY_I_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0F88FFFF0F880F88" + ) + port map ( + I0 => \^e\(0), + I1 => \pushed_commands_reg[3]_0\, + I2 => s_axi_arvalid, + I3 => S_AXI_AREADY_I_reg_0, + I4 => areset_d(0), + I5 => areset_d(1), + O => S_AXI_AREADY_I_reg + ); +\cmd_depth[1]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"69" + ) + port map ( + I0 => Q(0), + I1 => \cmd_depth[4]_i_2__0_n_0\, + I2 => Q(1), + O => D(0) + ); +\cmd_depth[2]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"78E1" + ) + port map ( + I0 => Q(0), + I1 => \cmd_depth[4]_i_2__0_n_0\, + I2 => Q(2), + I3 => Q(1), + O => D(1) + ); +\cmd_depth[3]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7F80FE01" + ) + port map ( + I0 => \cmd_depth[4]_i_2__0_n_0\, + I1 => Q(0), + I2 => Q(1), + I3 => Q(3), + I4 => Q(2), + O => D(2) + ); +\cmd_depth[4]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFF8000FFFE0001" + ) + port map ( + I0 => Q(1), + I1 => Q(0), + I2 => \cmd_depth[4]_i_2__0_n_0\, + I3 => Q(2), + I4 => Q(4), + I5 => Q(3), + O => D(3) + ); +\cmd_depth[4]_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000040" + ) + port map ( + I0 => cmd_push_block, + I1 => command_ongoing, + I2 => m_axi_arvalid_INST_0_i_1_n_0, + I3 => full, + I4 => \^rd_en\, + O => \cmd_depth[4]_i_2__0_n_0\ + ); +\cmd_depth[5]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAAA6AAA" + ) + port map ( + I0 => \^wr_en\, + I1 => s_axi_rready, + I2 => m_axi_rvalid, + I3 => m_axi_rlast, + I4 => empty, + O => \cmd_depth_reg[5]\(0) + ); +\cmd_depth[5]_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"78E1" + ) + port map ( + I0 => \cmd_depth[5]_i_3__0_n_0\, + I1 => Q(3), + I2 => Q(5), + I3 => Q(4), + O => D(4) + ); +\cmd_depth[5]_i_3__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D5555554" + ) + port map ( + I0 => Q(3), + I1 => Q(2), + I2 => \cmd_depth[4]_i_2__0_n_0\, + I3 => Q(0), + I4 => Q(1), + O => \cmd_depth[5]_i_3__0_n_0\ + ); +\cmd_push_block_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"55000000FF080000" + ) + port map ( + I0 => command_ongoing, + I1 => m_axi_arvalid_INST_0_i_1_n_0, + I2 => full, + I3 => cmd_push_block, + I4 => aresetn, + I5 => m_axi_arready, + O => cmd_push_block_reg + ); +\command_ongoing_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF7770000F000" + ) + port map ( + I0 => \^e\(0), + I1 => \pushed_commands_reg[3]_0\, + I2 => s_axi_arvalid, + I3 => S_AXI_AREADY_I_reg_0, + I4 => \areset_d_reg[1]\, + I5 => command_ongoing, + O => command_ongoing_reg + ); +fifo_gen_inst: entity work.\Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3__parameterized0\ + port map ( + almost_empty => NLW_fifo_gen_inst_almost_empty_UNCONNECTED, + almost_full => NLW_fifo_gen_inst_almost_full_UNCONNECTED, + axi_ar_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED(4 downto 0), + axi_ar_dbiterr => NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED, + axi_ar_injectdbiterr => '0', + axi_ar_injectsbiterr => '0', + axi_ar_overflow => NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED, + axi_ar_prog_empty => NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED, + axi_ar_prog_empty_thresh(3 downto 0) => B"0000", + axi_ar_prog_full => NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED, + axi_ar_prog_full_thresh(3 downto 0) => B"0000", + axi_ar_rd_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED(4 downto 0), + axi_ar_sbiterr => NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED, + axi_ar_underflow => NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED, + axi_ar_wr_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED(4 downto 0), + axi_aw_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED(4 downto 0), + axi_aw_dbiterr => NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED, + axi_aw_injectdbiterr => '0', + axi_aw_injectsbiterr => '0', + axi_aw_overflow => NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED, + axi_aw_prog_empty => NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED, + axi_aw_prog_empty_thresh(3 downto 0) => B"0000", + axi_aw_prog_full => NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED, + axi_aw_prog_full_thresh(3 downto 0) => B"0000", + axi_aw_rd_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED(4 downto 0), + axi_aw_sbiterr => NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED, + axi_aw_underflow => NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED, + axi_aw_wr_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED(4 downto 0), + axi_b_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED(4 downto 0), + axi_b_dbiterr => NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED, + axi_b_injectdbiterr => '0', + axi_b_injectsbiterr => '0', + axi_b_overflow => NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED, + axi_b_prog_empty => NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED, + axi_b_prog_empty_thresh(3 downto 0) => B"0000", + axi_b_prog_full => NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED, + axi_b_prog_full_thresh(3 downto 0) => B"0000", + axi_b_rd_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED(4 downto 0), + axi_b_sbiterr => NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED, + axi_b_underflow => NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED, + axi_b_wr_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED(4 downto 0), + axi_r_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED(10 downto 0), + axi_r_dbiterr => NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED, + axi_r_injectdbiterr => '0', + axi_r_injectsbiterr => '0', + axi_r_overflow => NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED, + axi_r_prog_empty => NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED, + axi_r_prog_empty_thresh(9 downto 0) => B"0000000000", + axi_r_prog_full => NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED, + axi_r_prog_full_thresh(9 downto 0) => B"0000000000", + axi_r_rd_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED(10 downto 0), + axi_r_sbiterr => NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED, + axi_r_underflow => NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED, + axi_r_wr_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED(10 downto 0), + axi_w_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED(10 downto 0), + axi_w_dbiterr => NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED, + axi_w_injectdbiterr => '0', + axi_w_injectsbiterr => '0', + axi_w_overflow => NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED, + axi_w_prog_empty => NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED, + axi_w_prog_empty_thresh(9 downto 0) => B"0000000000", + axi_w_prog_full => NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED, + axi_w_prog_full_thresh(9 downto 0) => B"0000000000", + axi_w_rd_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED(10 downto 0), + axi_w_sbiterr => NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED, + axi_w_underflow => NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED, + axi_w_wr_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED(10 downto 0), + axis_data_count(10 downto 0) => NLW_fifo_gen_inst_axis_data_count_UNCONNECTED(10 downto 0), + axis_dbiterr => NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED, + axis_injectdbiterr => '0', + axis_injectsbiterr => '0', + axis_overflow => NLW_fifo_gen_inst_axis_overflow_UNCONNECTED, + axis_prog_empty => NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED, + axis_prog_empty_thresh(9 downto 0) => B"0000000000", + axis_prog_full => NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED, + axis_prog_full_thresh(9 downto 0) => B"0000000000", + axis_rd_data_count(10 downto 0) => NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED(10 downto 0), + axis_sbiterr => NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED, + axis_underflow => NLW_fifo_gen_inst_axis_underflow_UNCONNECTED, + axis_wr_data_count(10 downto 0) => NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED(10 downto 0), + backup => '0', + backup_marker => '0', + clk => aclk, + data_count(5 downto 0) => NLW_fifo_gen_inst_data_count_UNCONNECTED(5 downto 0), + dbiterr => NLW_fifo_gen_inst_dbiterr_UNCONNECTED, + din(0) => \^din\(0), + dout(0) => rd_cmd_split, + empty => empty, + full => full, + injectdbiterr => '0', + injectsbiterr => '0', + int_clk => '0', + m_aclk => '0', + m_aclk_en => '0', + m_axi_araddr(31 downto 0) => NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED(31 downto 0), + m_axi_arburst(1 downto 0) => NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED(1 downto 0), + m_axi_arcache(3 downto 0) => NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED(3 downto 0), + m_axi_arid(3 downto 0) => NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED(3 downto 0), + m_axi_arlen(7 downto 0) => NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED(7 downto 0), + m_axi_arlock(1 downto 0) => NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED(1 downto 0), + m_axi_arprot(2 downto 0) => NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED(2 downto 0), + m_axi_arqos(3 downto 0) => NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED(3 downto 0), + m_axi_arready => '0', + m_axi_arregion(3 downto 0) => NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED(3 downto 0), + m_axi_arsize(2 downto 0) => NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED(2 downto 0), + m_axi_aruser(0) => NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED(0), + m_axi_arvalid => NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED, + m_axi_awaddr(31 downto 0) => NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED(31 downto 0), + m_axi_awburst(1 downto 0) => NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED(1 downto 0), + m_axi_awcache(3 downto 0) => NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED(3 downto 0), + m_axi_awid(3 downto 0) => NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED(3 downto 0), + m_axi_awlen(7 downto 0) => NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED(7 downto 0), + m_axi_awlock(1 downto 0) => NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED(1 downto 0), + m_axi_awprot(2 downto 0) => NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED(2 downto 0), + m_axi_awqos(3 downto 0) => NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED(3 downto 0), + m_axi_awready => '0', + m_axi_awregion(3 downto 0) => NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED(3 downto 0), + m_axi_awsize(2 downto 0) => NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED(2 downto 0), + m_axi_awuser(0) => NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED(0), + m_axi_awvalid => NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED, + m_axi_bid(3 downto 0) => B"0000", + m_axi_bready => NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED, + m_axi_bresp(1 downto 0) => B"00", + m_axi_buser(0) => '0', + m_axi_bvalid => '0', + m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + m_axi_rid(3 downto 0) => B"0000", + m_axi_rlast => '0', + m_axi_rready => NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED, + m_axi_rresp(1 downto 0) => B"00", + m_axi_ruser(0) => '0', + m_axi_rvalid => '0', + m_axi_wdata(63 downto 0) => NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED(63 downto 0), + m_axi_wid(3 downto 0) => NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED(3 downto 0), + m_axi_wlast => NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED, + m_axi_wready => '0', + m_axi_wstrb(7 downto 0) => NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED(7 downto 0), + m_axi_wuser(0) => NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED(0), + m_axi_wvalid => NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED, + m_axis_tdata(63 downto 0) => NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED(63 downto 0), + m_axis_tdest(3 downto 0) => NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED(3 downto 0), + m_axis_tid(7 downto 0) => NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED(7 downto 0), + m_axis_tkeep(3 downto 0) => NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED(3 downto 0), + m_axis_tlast => NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED, + m_axis_tready => '0', + m_axis_tstrb(3 downto 0) => NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED(3 downto 0), + m_axis_tuser(3 downto 0) => NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED(3 downto 0), + m_axis_tvalid => NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED, + overflow => NLW_fifo_gen_inst_overflow_UNCONNECTED, + prog_empty => NLW_fifo_gen_inst_prog_empty_UNCONNECTED, + prog_empty_thresh(4 downto 0) => B"00000", + prog_empty_thresh_assert(4 downto 0) => B"00000", + prog_empty_thresh_negate(4 downto 0) => B"00000", + prog_full => NLW_fifo_gen_inst_prog_full_UNCONNECTED, + prog_full_thresh(4 downto 0) => B"00000", + prog_full_thresh_assert(4 downto 0) => B"00000", + prog_full_thresh_negate(4 downto 0) => B"00000", + rd_clk => '0', + rd_data_count(5 downto 0) => NLW_fifo_gen_inst_rd_data_count_UNCONNECTED(5 downto 0), + rd_en => \^rd_en\, + rd_rst => '0', + rd_rst_busy => NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED, + rst => aresetn_0, + s_aclk => '0', + s_aclk_en => '0', + s_aresetn => '0', + s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", + s_axi_arburst(1 downto 0) => B"00", + s_axi_arcache(3 downto 0) => B"0000", + s_axi_arid(3 downto 0) => B"0000", + s_axi_arlen(7 downto 0) => B"00000000", + s_axi_arlock(1 downto 0) => B"00", + s_axi_arprot(2 downto 0) => B"000", + s_axi_arqos(3 downto 0) => B"0000", + s_axi_arready => NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED, + s_axi_arregion(3 downto 0) => B"0000", + s_axi_arsize(2 downto 0) => B"000", + s_axi_aruser(0) => '0', + s_axi_arvalid => '0', + s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", + s_axi_awburst(1 downto 0) => B"00", + s_axi_awcache(3 downto 0) => B"0000", + s_axi_awid(3 downto 0) => B"0000", + s_axi_awlen(7 downto 0) => B"00000000", + s_axi_awlock(1 downto 0) => B"00", + s_axi_awprot(2 downto 0) => B"000", + s_axi_awqos(3 downto 0) => B"0000", + s_axi_awready => NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED, + s_axi_awregion(3 downto 0) => B"0000", + s_axi_awsize(2 downto 0) => B"000", + s_axi_awuser(0) => '0', + s_axi_awvalid => '0', + s_axi_bid(3 downto 0) => NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED(3 downto 0), + s_axi_bready => '0', + s_axi_bresp(1 downto 0) => NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED(1 downto 0), + s_axi_buser(0) => NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED(0), + s_axi_bvalid => NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED, + s_axi_rdata(63 downto 0) => NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED(63 downto 0), + s_axi_rid(3 downto 0) => NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED(3 downto 0), + s_axi_rlast => NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED, + s_axi_rready => '0', + s_axi_rresp(1 downto 0) => NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED(1 downto 0), + s_axi_ruser(0) => NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED(0), + s_axi_rvalid => NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED, + s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + s_axi_wid(3 downto 0) => B"0000", + s_axi_wlast => '0', + s_axi_wready => NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED, + s_axi_wstrb(7 downto 0) => B"00000000", + s_axi_wuser(0) => '0', + s_axi_wvalid => '0', + s_axis_tdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + s_axis_tdest(3 downto 0) => B"0000", + s_axis_tid(7 downto 0) => B"00000000", + s_axis_tkeep(3 downto 0) => B"0000", + s_axis_tlast => '0', + s_axis_tready => NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED, + s_axis_tstrb(3 downto 0) => B"0000", + s_axis_tuser(3 downto 0) => B"0000", + s_axis_tvalid => '0', + sbiterr => NLW_fifo_gen_inst_sbiterr_UNCONNECTED, + sleep => '0', + srst => '0', + underflow => NLW_fifo_gen_inst_underflow_UNCONNECTED, + valid => NLW_fifo_gen_inst_valid_UNCONNECTED, + wr_ack => NLW_fifo_gen_inst_wr_ack_UNCONNECTED, + wr_clk => '0', + wr_data_count(5 downto 0) => NLW_fifo_gen_inst_wr_data_count_UNCONNECTED(5 downto 0), + wr_en => \^wr_en\, + wr_rst => '0', + wr_rst_busy => NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED + ); +\fifo_gen_inst_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"08808888" + ) + port map ( + I0 => need_to_split_q, + I1 => access_is_incr_q, + I2 => \num_transactions_q_reg[3]\, + I3 => \pushed_commands_reg[3]\(3), + I4 => \^split_ongoing_reg\, + O => \^din\(0) + ); +\fifo_gen_inst_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0040" + ) + port map ( + I0 => full, + I1 => m_axi_arvalid_INST_0_i_1_n_0, + I2 => command_ongoing, + I3 => cmd_push_block, + O => \^wr_en\ + ); +\fifo_gen_inst_i_3__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0080" + ) + port map ( + I0 => s_axi_rready, + I1 => m_axi_rvalid, + I2 => m_axi_rlast, + I3 => empty, + O => \^rd_en\ + ); +\fifo_gen_inst_i_4__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \num_transactions_q_reg[0]\, + I1 => \pushed_commands_reg[3]\(0), + I2 => \pushed_commands_reg[3]\(2), + I3 => \num_transactions_q_reg[2]\, + I4 => \pushed_commands_reg[3]\(1), + I5 => \num_transactions_q_reg[1]\, + O => \^split_ongoing_reg\ + ); +m_axi_arvalid_INST_0: unisim.vcomponents.LUT4 + generic map( + INIT => X"AA08" + ) + port map ( + I0 => command_ongoing, + I1 => m_axi_arvalid_INST_0_i_1_n_0, + I2 => full, + I3 => cmd_push_block, + O => m_axi_arvalid + ); +m_axi_arvalid_INST_0_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"7770707777737377" + ) + port map ( + I0 => multiple_id_non_split, + I1 => need_to_split_q, + I2 => cmd_empty, + I3 => \S_AXI_AID_Q_reg[0]\, + I4 => \queue_id_reg[0]_0\, + I5 => split_in_progress_reg_0, + O => m_axi_arvalid_INST_0_i_1_n_0 + ); +m_axi_rready_INST_0: unisim.vcomponents.LUT3 + generic map( + INIT => X"0D" + ) + port map ( + I0 => m_axi_rvalid, + I1 => s_axi_rready, + I2 => empty, + O => m_axi_rready + ); +\multiple_id_non_split_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000BEAAAAAA" + ) + port map ( + I0 => multiple_id_non_split, + I1 => \queue_id_reg[0]_0\, + I2 => \S_AXI_AID_Q_reg[0]\, + I3 => \^wr_en\, + I4 => split_in_progress_reg_1, + I5 => \multiple_id_non_split_i_3__0_n_0\, + O => multiple_id_non_split_reg + ); +\multiple_id_non_split_i_3__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F8FF" + ) + port map ( + I0 => almost_empty, + I1 => \^rd_en\, + I2 => cmd_empty, + I3 => aresetn, + O => \multiple_id_non_split_i_3__0_n_0\ + ); +\queue_id[0]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \S_AXI_AID_Q_reg[0]\, + I1 => \^wr_en\, + I2 => \queue_id_reg[0]_0\, + O => \queue_id_reg[0]\ + ); +s_axi_rlast_INST_0: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => m_axi_rlast, + I1 => rd_cmd_split, + O => s_axi_rlast + ); +s_axi_rvalid_INST_0: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => m_axi_rvalid, + I1 => empty, + O => s_axi_rvalid + ); +\split_in_progress_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00EA" + ) + port map ( + I0 => split_in_progress_reg_0, + I1 => \^wr_en\, + I2 => \allow_split_cmd__1\, + I3 => \multiple_id_non_split_i_3__0_n_0\, + O => split_in_progress_reg + ); +\split_ongoing_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AA080000" + ) + port map ( + I0 => command_ongoing, + I1 => m_axi_arvalid_INST_0_i_1_n_0, + I2 => full, + I3 => cmd_push_block, + I4 => m_axi_arready, + O => \^e\(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_axic_fifo is + port ( + dout : out STD_LOGIC_VECTOR ( 4 downto 0 ); + full : out STD_LOGIC; + empty : out STD_LOGIC; + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + din : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \cmd_depth_reg[5]\ : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 4 downto 0 ); + m_axi_wvalid : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wready : out STD_LOGIC; + \queue_id_reg[0]\ : out STD_LOGIC; + split_in_progress_reg : out STD_LOGIC; + multiple_id_non_split_reg : out STD_LOGIC; + aclk : in STD_LOGIC; + \S_AXI_AID_Q_reg[0]\ : in STD_LOGIC; + wr_cmd_ready : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 5 downto 0 ); + split_in_progress_reg_0 : in STD_LOGIC; + \allow_split_cmd__1\ : in STD_LOGIC; + ram_full_i_reg : in STD_LOGIC; + command_ongoing : in STD_LOGIC; + cmd_push_block : in STD_LOGIC; + \S_AXI_ALEN_Q_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + need_to_split_q : in STD_LOGIC; + \pushed_commands_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wvalid : in STD_LOGIC; + m_axi_wready : in STD_LOGIC; + aresetn : in STD_LOGIC; + queue_id : in STD_LOGIC; + split_in_progress_reg_1 : in STD_LOGIC; + cmd_empty_reg : in STD_LOGIC; + multiple_id_non_split : in STD_LOGIC + ); +end Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_axic_fifo; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_axic_fifo is +begin +inst: entity work.Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen_6 + port map ( + D(4 downto 0) => D(4 downto 0), + E(0) => E(0), + Q(5 downto 0) => Q(5 downto 0), + SR(0) => SR(0), + \S_AXI_AID_Q_reg[0]\ => \S_AXI_AID_Q_reg[0]\, + \S_AXI_ALEN_Q_reg[3]\(3 downto 0) => \S_AXI_ALEN_Q_reg[3]\(3 downto 0), + aclk => aclk, + \allow_split_cmd__1\ => \allow_split_cmd__1\, + aresetn => aresetn, + cmd_empty_reg => cmd_empty_reg, + cmd_push_block => cmd_push_block, + command_ongoing => command_ongoing, + din(3 downto 0) => din(3 downto 0), + dout(4 downto 0) => dout(4 downto 0), + empty => empty, + full => full, + m_axi_wready => m_axi_wready, + m_axi_wvalid => m_axi_wvalid, + multiple_id_non_split => multiple_id_non_split, + multiple_id_non_split_reg => multiple_id_non_split_reg, + need_to_split_q => need_to_split_q, + \pushed_commands_reg[3]\(3 downto 0) => \pushed_commands_reg[3]\(3 downto 0), + queue_id => queue_id, + \queue_id_reg[0]\ => \queue_id_reg[0]\, + ram_full_i_reg => ram_full_i_reg, + s_axi_wready => s_axi_wready, + s_axi_wvalid => s_axi_wvalid, + split_in_progress_reg => split_in_progress_reg, + split_in_progress_reg_0 => split_in_progress_reg_0, + split_in_progress_reg_1 => split_in_progress_reg_1, + wr_cmd_ready => wr_cmd_ready, + wr_en => \cmd_depth_reg[5]\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_axic_fifo_0 is + port ( + \S_AXI_BRESP_ACC_reg[0]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + full : out STD_LOGIC; + din : out STD_LOGIC_VECTOR ( 0 to 0 ); + D : out STD_LOGIC_VECTOR ( 4 downto 0 ); + m_axi_awvalid : out STD_LOGIC; + multiple_id_non_split_reg : out STD_LOGIC; + multiple_id_non_split_reg_0 : out STD_LOGIC; + split_ongoing_reg : out STD_LOGIC; + cmd_b_push_block_reg : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \USE_B_CHANNEL.cmd_b_empty_reg\ : out STD_LOGIC; + \pushed_commands_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \allow_split_cmd__1\ : out STD_LOGIC; + S_AXI_AREADY_I_reg : out STD_LOGIC; + cmd_push_block_reg : out STD_LOGIC; + command_ongoing_reg : out STD_LOGIC; + aclk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + \num_transactions_q_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 5 downto 0 ); + cmd_b_push_block : in STD_LOGIC; + m_axi_bvalid : in STD_LOGIC; + last_word : in STD_LOGIC; + s_axi_bready : in STD_LOGIC; + cmd_empty : in STD_LOGIC; + wr_cmd_ready : in STD_LOGIC; + almost_empty : in STD_LOGIC; + aresetn : in STD_LOGIC; + split_in_progress_reg : in STD_LOGIC; + queue_id : in STD_LOGIC; + \S_AXI_AID_Q_reg[0]\ : in STD_LOGIC; + cmd_b_empty : in STD_LOGIC; + need_to_split_q : in STD_LOGIC; + access_is_incr_q : in STD_LOGIC; + \pushed_commands_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_AREADY_I_reg_0 : in STD_LOGIC; + almost_b_empty : in STD_LOGIC; + m_axi_awready : in STD_LOGIC; + command_ongoing : in STD_LOGIC; + ram_full_i_reg : in STD_LOGIC; + cmd_push_block : in STD_LOGIC; + multiple_id_non_split : in STD_LOGIC; + \pushed_commands_reg[3]_0\ : in STD_LOGIC; + s_axi_awvalid : in STD_LOGIC; + \areset_d_reg[0]\ : in STD_LOGIC; + areset_d : in STD_LOGIC_VECTOR ( 0 to 0 ); + \areset_d_reg[1]\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_axic_fifo_0 : entity is "axi_data_fifo_v2_1_10_axic_fifo"; +end Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_axic_fifo_0; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_axic_fifo_0 is +begin +inst: entity work.Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen + port map ( + D(4 downto 0) => D(4 downto 0), + E(0) => E(0), + Q(5 downto 0) => Q(5 downto 0), + SR(0) => SR(0), + \S_AXI_AID_Q_reg[0]\ => \S_AXI_AID_Q_reg[0]\, + S_AXI_AREADY_I_reg => S_AXI_AREADY_I_reg, + S_AXI_AREADY_I_reg_0 => S_AXI_AREADY_I_reg_0, + \S_AXI_BRESP_ACC_reg[0]\(4 downto 0) => \S_AXI_BRESP_ACC_reg[0]\(4 downto 0), + \USE_B_CHANNEL.cmd_b_empty_reg\ => \USE_B_CHANNEL.cmd_b_empty_reg\, + access_is_incr_q => access_is_incr_q, + aclk => aclk, + \allow_split_cmd__1\ => \allow_split_cmd__1\, + almost_b_empty => almost_b_empty, + almost_empty => almost_empty, + areset_d(0) => areset_d(0), + \areset_d_reg[0]\ => \areset_d_reg[0]\, + \areset_d_reg[1]\ => \areset_d_reg[1]\, + aresetn => aresetn, + cmd_b_empty => cmd_b_empty, + cmd_b_push_block => cmd_b_push_block, + cmd_b_push_block_reg => cmd_b_push_block_reg, + cmd_empty => cmd_empty, + cmd_push_block => cmd_push_block, + cmd_push_block_reg => cmd_push_block_reg, + command_ongoing => command_ongoing, + command_ongoing_reg => command_ongoing_reg, + din(0) => din(0), + full => full, + last_word => last_word, + m_axi_awready => m_axi_awready, + m_axi_awvalid => m_axi_awvalid, + m_axi_bvalid => m_axi_bvalid, + multiple_id_non_split => multiple_id_non_split, + multiple_id_non_split_reg => multiple_id_non_split_reg, + multiple_id_non_split_reg_0 => multiple_id_non_split_reg_0, + need_to_split_q => need_to_split_q, + \num_transactions_q_reg[3]\(3 downto 0) => \num_transactions_q_reg[3]\(3 downto 0), + \pushed_commands_reg[0]\(0) => \pushed_commands_reg[0]\(0), + \pushed_commands_reg[3]\(3 downto 0) => \pushed_commands_reg[3]\(3 downto 0), + \pushed_commands_reg[3]_0\ => \pushed_commands_reg[3]_0\, + queue_id => queue_id, + ram_full_i_reg => ram_full_i_reg, + s_axi_awvalid => s_axi_awvalid, + s_axi_bready => s_axi_bready, + split_in_progress_reg => split_in_progress_reg, + split_ongoing_reg => split_ongoing_reg, + wr_cmd_ready => wr_cmd_ready + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_axic_fifo__parameterized0\ is + port ( + din : out STD_LOGIC_VECTOR ( 0 to 0 ); + split_in_progress_reg : out STD_LOGIC; + rd_cmd_ready : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 4 downto 0 ); + split_ongoing_reg : out STD_LOGIC; + m_axi_rready : out STD_LOGIC; + s_axi_rvalid : out STD_LOGIC; + s_axi_rlast : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + cmd_push_block_reg : out STD_LOGIC; + \cmd_depth_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_arvalid : out STD_LOGIC; + S_AXI_AREADY_I_reg : out STD_LOGIC; + \queue_id_reg[0]\ : out STD_LOGIC; + command_ongoing_reg : out STD_LOGIC; + multiple_id_non_split_reg : out STD_LOGIC; + split_in_progress_reg_0 : out STD_LOGIC; + aclk : in STD_LOGIC; + aresetn_0 : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 5 downto 0 ); + cmd_push_block : in STD_LOGIC; + command_ongoing : in STD_LOGIC; + almost_empty : in STD_LOGIC; + cmd_empty : in STD_LOGIC; + aresetn : in STD_LOGIC; + need_to_split_q : in STD_LOGIC; + access_is_incr_q : in STD_LOGIC; + \num_transactions_q_reg[3]\ : in STD_LOGIC; + \pushed_commands_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_rvalid : in STD_LOGIC; + s_axi_rready : in STD_LOGIC; + m_axi_rlast : in STD_LOGIC; + m_axi_arready : in STD_LOGIC; + multiple_id_non_split : in STD_LOGIC; + \S_AXI_AID_Q_reg[0]\ : in STD_LOGIC; + \queue_id_reg[0]_0\ : in STD_LOGIC; + split_in_progress_reg_1 : in STD_LOGIC; + \num_transactions_q_reg[0]\ : in STD_LOGIC; + \num_transactions_q_reg[2]\ : in STD_LOGIC; + \num_transactions_q_reg[1]\ : in STD_LOGIC; + \pushed_commands_reg[3]_0\ : in STD_LOGIC; + s_axi_arvalid : in STD_LOGIC; + S_AXI_AREADY_I_reg_0 : in STD_LOGIC; + areset_d : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \areset_d_reg[1]\ : in STD_LOGIC; + split_in_progress_reg_2 : in STD_LOGIC; + \allow_split_cmd__1\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_axic_fifo__parameterized0\ : entity is "axi_data_fifo_v2_1_10_axic_fifo"; +end \Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_axic_fifo__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_axic_fifo__parameterized0\ is +begin +inst: entity work.\Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen__parameterized0\ + port map ( + D(4 downto 0) => D(4 downto 0), + E(0) => E(0), + Q(5 downto 0) => Q(5 downto 0), + \S_AXI_AID_Q_reg[0]\ => \S_AXI_AID_Q_reg[0]\, + S_AXI_AREADY_I_reg => S_AXI_AREADY_I_reg, + S_AXI_AREADY_I_reg_0 => S_AXI_AREADY_I_reg_0, + access_is_incr_q => access_is_incr_q, + aclk => aclk, + \allow_split_cmd__1\ => \allow_split_cmd__1\, + almost_empty => almost_empty, + areset_d(1 downto 0) => areset_d(1 downto 0), + \areset_d_reg[1]\ => \areset_d_reg[1]\, + aresetn => aresetn, + aresetn_0 => aresetn_0, + \cmd_depth_reg[5]\(0) => \cmd_depth_reg[5]\(0), + cmd_empty => cmd_empty, + cmd_push_block => cmd_push_block, + cmd_push_block_reg => cmd_push_block_reg, + command_ongoing => command_ongoing, + command_ongoing_reg => command_ongoing_reg, + din(0) => din(0), + m_axi_arready => m_axi_arready, + m_axi_arvalid => m_axi_arvalid, + m_axi_rlast => m_axi_rlast, + m_axi_rready => m_axi_rready, + m_axi_rvalid => m_axi_rvalid, + multiple_id_non_split => multiple_id_non_split, + multiple_id_non_split_reg => multiple_id_non_split_reg, + need_to_split_q => need_to_split_q, + \num_transactions_q_reg[0]\ => \num_transactions_q_reg[0]\, + \num_transactions_q_reg[1]\ => \num_transactions_q_reg[1]\, + \num_transactions_q_reg[2]\ => \num_transactions_q_reg[2]\, + \num_transactions_q_reg[3]\ => \num_transactions_q_reg[3]\, + \pushed_commands_reg[3]\(3 downto 0) => \pushed_commands_reg[3]\(3 downto 0), + \pushed_commands_reg[3]_0\ => \pushed_commands_reg[3]_0\, + \queue_id_reg[0]\ => \queue_id_reg[0]\, + \queue_id_reg[0]_0\ => \queue_id_reg[0]_0\, + rd_en => rd_cmd_ready, + s_axi_arvalid => s_axi_arvalid, + s_axi_rlast => s_axi_rlast, + s_axi_rready => s_axi_rready, + s_axi_rvalid => s_axi_rvalid, + split_in_progress_reg => split_in_progress_reg_0, + split_in_progress_reg_0 => split_in_progress_reg_1, + split_in_progress_reg_1 => split_in_progress_reg_2, + split_ongoing_reg => split_ongoing_reg, + wr_en => split_in_progress_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_a_axi3_conv is + port ( + dout : out STD_LOGIC_VECTOR ( 4 downto 0 ); + empty : out STD_LOGIC; + \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : out STD_LOGIC; + din : out STD_LOGIC_VECTOR ( 4 downto 0 ); + \S_AXI_BRESP_ACC_reg[0]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + areset_d : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awvalid : out STD_LOGIC; + m_axi_wvalid : out STD_LOGIC; + m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); + command_ongoing_reg_0 : out STD_LOGIC; + m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_wready : out STD_LOGIC; + m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + aclk : in STD_LOGIC; + wr_cmd_ready : in STD_LOGIC; + s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_bvalid : in STD_LOGIC; + last_word : in STD_LOGIC; + s_axi_bready : in STD_LOGIC; + aresetn : in STD_LOGIC; + s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_wvalid : in STD_LOGIC; + m_axi_awready : in STD_LOGIC; + m_axi_wready : in STD_LOGIC; + s_axi_awvalid : in STD_LOGIC; + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ) + ); +end Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_a_axi3_conv; + +architecture STRUCTURE of Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_a_axi3_conv is + signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \M_AXI_AADDR_I1__0\ : STD_LOGIC; + signal S_AXI_AADDR_Q : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal S_AXI_ALEN_Q : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \S_AXI_ALOCK_Q_reg_n_0_[0]\ : STD_LOGIC; + signal S_AXI_AREADY_I_i_3_n_0 : STD_LOGIC; + signal \USE_BURSTS.cmd_queue_n_12\ : STD_LOGIC; + signal \USE_BURSTS.cmd_queue_n_13\ : STD_LOGIC; + signal \USE_BURSTS.cmd_queue_n_14\ : STD_LOGIC; + signal \USE_BURSTS.cmd_queue_n_15\ : STD_LOGIC; + signal \USE_BURSTS.cmd_queue_n_16\ : STD_LOGIC; + signal \USE_BURSTS.cmd_queue_n_17\ : STD_LOGIC; + signal \USE_BURSTS.cmd_queue_n_19\ : STD_LOGIC; + signal \USE_BURSTS.cmd_queue_n_21\ : STD_LOGIC; + signal \USE_BURSTS.cmd_queue_n_22\ : STD_LOGIC; + signal \USE_BURSTS.cmd_queue_n_23\ : STD_LOGIC; + signal \USE_B_CHANNEL.cmd_b_depth[0]_i_1_n_0\ : STD_LOGIC; + signal \USE_B_CHANNEL.cmd_b_depth_reg__0\ : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \USE_B_CHANNEL.cmd_b_queue_n_10\ : STD_LOGIC; + signal \USE_B_CHANNEL.cmd_b_queue_n_11\ : STD_LOGIC; + signal \USE_B_CHANNEL.cmd_b_queue_n_13\ : STD_LOGIC; + signal \USE_B_CHANNEL.cmd_b_queue_n_14\ : STD_LOGIC; + signal \USE_B_CHANNEL.cmd_b_queue_n_15\ : STD_LOGIC; + signal \USE_B_CHANNEL.cmd_b_queue_n_16\ : STD_LOGIC; + signal \USE_B_CHANNEL.cmd_b_queue_n_17\ : STD_LOGIC; + signal \USE_B_CHANNEL.cmd_b_queue_n_18\ : STD_LOGIC; + signal \USE_B_CHANNEL.cmd_b_queue_n_21\ : STD_LOGIC; + signal \USE_B_CHANNEL.cmd_b_queue_n_22\ : STD_LOGIC; + signal \USE_B_CHANNEL.cmd_b_queue_n_23\ : STD_LOGIC; + signal \USE_B_CHANNEL.cmd_b_queue_n_6\ : STD_LOGIC; + signal \USE_B_CHANNEL.cmd_b_queue_n_7\ : STD_LOGIC; + signal \USE_B_CHANNEL.cmd_b_queue_n_8\ : STD_LOGIC; + signal \USE_B_CHANNEL.cmd_b_queue_n_9\ : STD_LOGIC; + signal access_is_incr : STD_LOGIC; + signal access_is_incr_q : STD_LOGIC; + signal addr_step : STD_LOGIC_VECTOR ( 11 downto 5 ); + signal addr_step_q : STD_LOGIC_VECTOR ( 11 downto 5 ); + signal \allow_split_cmd__1\ : STD_LOGIC; + signal almost_b_empty : STD_LOGIC; + signal almost_empty : STD_LOGIC; + signal \^areset_d\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal cmd_b_empty : STD_LOGIC; + signal cmd_b_push_block : STD_LOGIC; + signal \cmd_depth[0]_i_1_n_0\ : STD_LOGIC; + signal \cmd_depth_reg__0\ : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal cmd_empty : STD_LOGIC; + signal cmd_empty_i_1_n_0 : STD_LOGIC; + signal cmd_push_block : STD_LOGIC; + signal command_ongoing : STD_LOGIC; + signal \^command_ongoing_reg_0\ : STD_LOGIC; + signal \^din\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \first_split__2\ : STD_LOGIC; + signal first_step : STD_LOGIC_VECTOR ( 11 downto 4 ); + signal first_step_q : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \first_step_q[0]_i_1_n_0\ : STD_LOGIC; + signal \first_step_q[10]_i_2_n_0\ : STD_LOGIC; + signal \first_step_q[11]_i_2_n_0\ : STD_LOGIC; + signal \first_step_q[1]_i_1_n_0\ : STD_LOGIC; + signal \first_step_q[2]_i_1_n_0\ : STD_LOGIC; + signal \first_step_q[3]_i_1_n_0\ : STD_LOGIC; + signal \first_step_q[6]_i_2_n_0\ : STD_LOGIC; + signal \first_step_q[7]_i_2_n_0\ : STD_LOGIC; + signal \first_step_q[8]_i_2_n_0\ : STD_LOGIC; + signal \first_step_q[9]_i_2_n_0\ : STD_LOGIC; + signal \incr_need_to_split__0\ : STD_LOGIC; + signal \inst/full\ : STD_LOGIC; + signal \inst/full_0\ : STD_LOGIC; + signal \^m_axi_awaddr\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal multiple_id_non_split : STD_LOGIC; + signal need_to_split_q : STD_LOGIC; + signal next_mi_addr : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \next_mi_addr[11]_i_2_n_0\ : STD_LOGIC; + signal \next_mi_addr[11]_i_3_n_0\ : STD_LOGIC; + signal \next_mi_addr[11]_i_4_n_0\ : STD_LOGIC; + signal \next_mi_addr[11]_i_5_n_0\ : STD_LOGIC; + signal \next_mi_addr[15]_i_2_n_0\ : STD_LOGIC; + signal \next_mi_addr[15]_i_3_n_0\ : STD_LOGIC; + signal \next_mi_addr[15]_i_4_n_0\ : STD_LOGIC; + signal \next_mi_addr[15]_i_5_n_0\ : STD_LOGIC; + signal \next_mi_addr[15]_i_6_n_0\ : STD_LOGIC; + signal \next_mi_addr[15]_i_7_n_0\ : STD_LOGIC; + signal \next_mi_addr[15]_i_8_n_0\ : STD_LOGIC; + signal \next_mi_addr[15]_i_9_n_0\ : STD_LOGIC; + signal \next_mi_addr[19]_i_2_n_0\ : STD_LOGIC; + signal \next_mi_addr[19]_i_3_n_0\ : STD_LOGIC; + signal \next_mi_addr[19]_i_4_n_0\ : STD_LOGIC; + signal \next_mi_addr[19]_i_5_n_0\ : STD_LOGIC; + signal \next_mi_addr[23]_i_2_n_0\ : STD_LOGIC; + signal \next_mi_addr[23]_i_3_n_0\ : STD_LOGIC; + signal \next_mi_addr[23]_i_4_n_0\ : STD_LOGIC; + signal \next_mi_addr[23]_i_5_n_0\ : STD_LOGIC; + signal \next_mi_addr[27]_i_2_n_0\ : STD_LOGIC; + signal \next_mi_addr[27]_i_3_n_0\ : STD_LOGIC; + signal \next_mi_addr[27]_i_4_n_0\ : STD_LOGIC; + signal \next_mi_addr[27]_i_5_n_0\ : STD_LOGIC; + signal \next_mi_addr[31]_i_2_n_0\ : STD_LOGIC; + signal \next_mi_addr[31]_i_3_n_0\ : STD_LOGIC; + signal \next_mi_addr[31]_i_4_n_0\ : STD_LOGIC; + signal \next_mi_addr[31]_i_5_n_0\ : STD_LOGIC; + signal \next_mi_addr[3]_i_2_n_0\ : STD_LOGIC; + signal \next_mi_addr[3]_i_3_n_0\ : STD_LOGIC; + signal \next_mi_addr[3]_i_4_n_0\ : STD_LOGIC; + signal \next_mi_addr[3]_i_5_n_0\ : STD_LOGIC; + signal \next_mi_addr[7]_i_2_n_0\ : STD_LOGIC; + signal \next_mi_addr[7]_i_3_n_0\ : STD_LOGIC; + signal \next_mi_addr[7]_i_4_n_0\ : STD_LOGIC; + signal \next_mi_addr[7]_i_5_n_0\ : STD_LOGIC; + signal \next_mi_addr_reg[11]_i_1_n_0\ : STD_LOGIC; + signal \next_mi_addr_reg[11]_i_1_n_1\ : STD_LOGIC; + signal \next_mi_addr_reg[11]_i_1_n_2\ : STD_LOGIC; + signal \next_mi_addr_reg[11]_i_1_n_3\ : STD_LOGIC; + signal \next_mi_addr_reg[11]_i_1_n_4\ : STD_LOGIC; + signal \next_mi_addr_reg[11]_i_1_n_5\ : STD_LOGIC; + signal \next_mi_addr_reg[11]_i_1_n_6\ : STD_LOGIC; + signal \next_mi_addr_reg[11]_i_1_n_7\ : STD_LOGIC; + signal \next_mi_addr_reg[15]_i_1_n_0\ : STD_LOGIC; + signal \next_mi_addr_reg[15]_i_1_n_1\ : STD_LOGIC; + signal \next_mi_addr_reg[15]_i_1_n_2\ : STD_LOGIC; + signal \next_mi_addr_reg[15]_i_1_n_3\ : STD_LOGIC; + signal \next_mi_addr_reg[15]_i_1_n_4\ : STD_LOGIC; + signal \next_mi_addr_reg[15]_i_1_n_5\ : STD_LOGIC; + signal \next_mi_addr_reg[15]_i_1_n_6\ : STD_LOGIC; + signal \next_mi_addr_reg[15]_i_1_n_7\ : STD_LOGIC; + signal \next_mi_addr_reg[19]_i_1_n_0\ : STD_LOGIC; + signal \next_mi_addr_reg[19]_i_1_n_1\ : STD_LOGIC; + signal \next_mi_addr_reg[19]_i_1_n_2\ : STD_LOGIC; + signal \next_mi_addr_reg[19]_i_1_n_3\ : STD_LOGIC; + signal \next_mi_addr_reg[19]_i_1_n_4\ : STD_LOGIC; + signal \next_mi_addr_reg[19]_i_1_n_5\ : STD_LOGIC; + signal \next_mi_addr_reg[19]_i_1_n_6\ : STD_LOGIC; + signal \next_mi_addr_reg[19]_i_1_n_7\ : STD_LOGIC; + signal \next_mi_addr_reg[23]_i_1_n_0\ : STD_LOGIC; + signal \next_mi_addr_reg[23]_i_1_n_1\ : STD_LOGIC; + signal \next_mi_addr_reg[23]_i_1_n_2\ : STD_LOGIC; + signal \next_mi_addr_reg[23]_i_1_n_3\ : STD_LOGIC; + signal \next_mi_addr_reg[23]_i_1_n_4\ : STD_LOGIC; + signal \next_mi_addr_reg[23]_i_1_n_5\ : STD_LOGIC; + signal \next_mi_addr_reg[23]_i_1_n_6\ : STD_LOGIC; + signal \next_mi_addr_reg[23]_i_1_n_7\ : STD_LOGIC; + signal \next_mi_addr_reg[27]_i_1_n_0\ : STD_LOGIC; + signal \next_mi_addr_reg[27]_i_1_n_1\ : STD_LOGIC; + signal \next_mi_addr_reg[27]_i_1_n_2\ : STD_LOGIC; + signal \next_mi_addr_reg[27]_i_1_n_3\ : STD_LOGIC; + signal \next_mi_addr_reg[27]_i_1_n_4\ : STD_LOGIC; + signal \next_mi_addr_reg[27]_i_1_n_5\ : STD_LOGIC; + signal \next_mi_addr_reg[27]_i_1_n_6\ : STD_LOGIC; + signal \next_mi_addr_reg[27]_i_1_n_7\ : STD_LOGIC; + signal \next_mi_addr_reg[31]_i_1_n_1\ : STD_LOGIC; + signal \next_mi_addr_reg[31]_i_1_n_2\ : STD_LOGIC; + signal \next_mi_addr_reg[31]_i_1_n_3\ : STD_LOGIC; + signal \next_mi_addr_reg[31]_i_1_n_4\ : STD_LOGIC; + signal \next_mi_addr_reg[31]_i_1_n_5\ : STD_LOGIC; + signal \next_mi_addr_reg[31]_i_1_n_6\ : STD_LOGIC; + signal \next_mi_addr_reg[31]_i_1_n_7\ : STD_LOGIC; + signal \next_mi_addr_reg[3]_i_1_n_0\ : STD_LOGIC; + signal \next_mi_addr_reg[3]_i_1_n_1\ : STD_LOGIC; + signal \next_mi_addr_reg[3]_i_1_n_2\ : STD_LOGIC; + signal \next_mi_addr_reg[3]_i_1_n_3\ : STD_LOGIC; + signal \next_mi_addr_reg[3]_i_1_n_4\ : STD_LOGIC; + signal \next_mi_addr_reg[3]_i_1_n_5\ : STD_LOGIC; + signal \next_mi_addr_reg[3]_i_1_n_6\ : STD_LOGIC; + signal \next_mi_addr_reg[3]_i_1_n_7\ : STD_LOGIC; + signal \next_mi_addr_reg[7]_i_1_n_0\ : STD_LOGIC; + signal \next_mi_addr_reg[7]_i_1_n_1\ : STD_LOGIC; + signal \next_mi_addr_reg[7]_i_1_n_2\ : STD_LOGIC; + signal \next_mi_addr_reg[7]_i_1_n_3\ : STD_LOGIC; + signal \next_mi_addr_reg[7]_i_1_n_4\ : STD_LOGIC; + signal \next_mi_addr_reg[7]_i_1_n_5\ : STD_LOGIC; + signal \next_mi_addr_reg[7]_i_1_n_6\ : STD_LOGIC; + signal \next_mi_addr_reg[7]_i_1_n_7\ : STD_LOGIC; + signal \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : STD_LOGIC; + signal num_transactions_q : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal p_0_in : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \pushed_commands[3]_i_1_n_0\ : STD_LOGIC; + signal \pushed_commands_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal pushed_new_cmd : STD_LOGIC; + signal queue_id : STD_LOGIC; + signal size_mask : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal size_mask_q : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal split_in_progress_reg_n_0 : STD_LOGIC; + signal split_ongoing : STD_LOGIC; + signal \NLW_next_mi_addr_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \addr_step_q[10]_i_1\ : label is "soft_lutpair49"; + attribute SOFT_HLUTNM of \addr_step_q[11]_i_1\ : label is "soft_lutpair47"; + attribute SOFT_HLUTNM of \addr_step_q[5]_i_1\ : label is "soft_lutpair52"; + attribute SOFT_HLUTNM of \addr_step_q[6]_i_1\ : label is "soft_lutpair47"; + attribute SOFT_HLUTNM of \addr_step_q[7]_i_1\ : label is "soft_lutpair52"; + attribute SOFT_HLUTNM of \addr_step_q[8]_i_1\ : label is "soft_lutpair48"; + attribute SOFT_HLUTNM of \addr_step_q[9]_i_1\ : label is "soft_lutpair45"; + attribute SOFT_HLUTNM of \first_step_q[0]_i_1\ : label is "soft_lutpair44"; + attribute SOFT_HLUTNM of \first_step_q[10]_i_1\ : label is "soft_lutpair53"; + attribute SOFT_HLUTNM of \first_step_q[11]_i_1\ : label is "soft_lutpair57"; + attribute SOFT_HLUTNM of \first_step_q[1]_i_1\ : label is "soft_lutpair45"; + attribute SOFT_HLUTNM of \first_step_q[3]_i_1\ : label is "soft_lutpair54"; + attribute SOFT_HLUTNM of \first_step_q[4]_i_1\ : label is "soft_lutpair44"; + attribute SOFT_HLUTNM of \first_step_q[6]_i_1\ : label is "soft_lutpair53"; + attribute SOFT_HLUTNM of \first_step_q[7]_i_1\ : label is "soft_lutpair54"; + attribute SOFT_HLUTNM of \first_step_q[8]_i_1\ : label is "soft_lutpair56"; + attribute SOFT_HLUTNM of \first_step_q[9]_i_1\ : label is "soft_lutpair57"; + attribute SOFT_HLUTNM of \m_axi_awaddr[28]_INST_0\ : label is "soft_lutpair43"; + attribute SOFT_HLUTNM of \next_mi_addr[11]_i_6\ : label is "soft_lutpair46"; + attribute SOFT_HLUTNM of \next_mi_addr[3]_i_6\ : label is "soft_lutpair43"; + attribute SOFT_HLUTNM of \pushed_commands[1]_i_1\ : label is "soft_lutpair50"; + attribute SOFT_HLUTNM of \pushed_commands[2]_i_1\ : label is "soft_lutpair50"; + attribute SOFT_HLUTNM of \pushed_commands[3]_i_2\ : label is "soft_lutpair46"; + attribute SOFT_HLUTNM of \size_mask_q[0]_i_1\ : label is "soft_lutpair49"; + attribute SOFT_HLUTNM of \size_mask_q[1]_i_1\ : label is "soft_lutpair55"; + attribute SOFT_HLUTNM of \size_mask_q[2]_i_1\ : label is "soft_lutpair51"; + attribute SOFT_HLUTNM of \size_mask_q[3]_i_1\ : label is "soft_lutpair56"; + attribute SOFT_HLUTNM of \size_mask_q[4]_i_1\ : label is "soft_lutpair51"; + attribute SOFT_HLUTNM of \size_mask_q[5]_i_1\ : label is "soft_lutpair55"; + attribute SOFT_HLUTNM of \size_mask_q[6]_i_1\ : label is "soft_lutpair48"; begin - SR(0) <= \^sr\(0); - \cmd_depth_reg[1]\ <= \^cmd_depth_reg[1]\; - din(0) <= \^din\(0); - \pushed_commands_reg[0]\ <= \^pushed_commands_reg[0]\; - rd_en <= \^rd_en\; - wr_en <= \^wr_en\; -S_AXI_AREADY_I_i_1: unisim.vcomponents.LUT1 + E(0) <= \^e\(0); + areset_d(1 downto 0) <= \^areset_d\(1 downto 0); + command_ongoing_reg_0 <= \^command_ongoing_reg_0\; + din(4 downto 0) <= \^din\(4 downto 0); + m_axi_awaddr(31 downto 0) <= \^m_axi_awaddr\(31 downto 0); + \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ <= \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\; +\S_AXI_AADDR_Q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(0), + Q => S_AXI_AADDR_Q(0), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(10), + Q => S_AXI_AADDR_Q(10), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(11), + Q => S_AXI_AADDR_Q(11), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(12), + Q => S_AXI_AADDR_Q(12), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(13), + Q => S_AXI_AADDR_Q(13), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(14), + Q => S_AXI_AADDR_Q(14), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(15), + Q => S_AXI_AADDR_Q(15), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(16), + Q => S_AXI_AADDR_Q(16), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(17), + Q => S_AXI_AADDR_Q(17), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(18), + Q => S_AXI_AADDR_Q(18), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(19), + Q => S_AXI_AADDR_Q(19), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(1), + Q => S_AXI_AADDR_Q(1), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(20), + Q => S_AXI_AADDR_Q(20), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(21), + Q => S_AXI_AADDR_Q(21), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(22), + Q => S_AXI_AADDR_Q(22), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(23), + Q => S_AXI_AADDR_Q(23), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(24), + Q => S_AXI_AADDR_Q(24), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(25), + Q => S_AXI_AADDR_Q(25), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[26]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(26), + Q => S_AXI_AADDR_Q(26), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[27]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(27), + Q => S_AXI_AADDR_Q(27), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[28]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(28), + Q => S_AXI_AADDR_Q(28), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[29]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(29), + Q => S_AXI_AADDR_Q(29), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(2), + Q => S_AXI_AADDR_Q(2), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(30), + Q => S_AXI_AADDR_Q(30), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(31), + Q => S_AXI_AADDR_Q(31), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(3), + Q => S_AXI_AADDR_Q(3), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(4), + Q => S_AXI_AADDR_Q(4), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(5), + Q => S_AXI_AADDR_Q(5), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(6), + Q => S_AXI_AADDR_Q(6), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(7), + Q => S_AXI_AADDR_Q(7), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(8), + Q => S_AXI_AADDR_Q(8), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AADDR_Q_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awaddr(9), + Q => S_AXI_AADDR_Q(9), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_ABURST_Q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awburst(0), + Q => m_axi_awburst(0), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_ABURST_Q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awburst(1), + Q => m_axi_awburst(1), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_ACACHE_Q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awcache(0), + Q => m_axi_awcache(0), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_ACACHE_Q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awcache(1), + Q => m_axi_awcache(1), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_ACACHE_Q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awcache(2), + Q => m_axi_awcache(2), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_ACACHE_Q_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awcache(3), + Q => m_axi_awcache(3), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AID_Q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awid(0), + Q => \^din\(4), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_ALEN_Q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awlen(0), + Q => S_AXI_ALEN_Q(0), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_ALEN_Q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awlen(1), + Q => S_AXI_ALEN_Q(1), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_ALEN_Q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awlen(2), + Q => S_AXI_ALEN_Q(2), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_ALEN_Q_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awlen(3), + Q => S_AXI_ALEN_Q(3), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_ALOCK_Q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awlock(0), + Q => \S_AXI_ALOCK_Q_reg_n_0_[0]\, + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_APROT_Q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awprot(0), + Q => m_axi_awprot(0), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_APROT_Q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awprot(1), + Q => m_axi_awprot(1), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_APROT_Q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awprot(2), + Q => m_axi_awprot(2), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AQOS_Q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awqos(0), + Q => m_axi_awqos(0), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AQOS_Q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awqos(1), + Q => m_axi_awqos(1), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AQOS_Q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awqos(2), + Q => m_axi_awqos(2), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_AQOS_Q_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awqos(3), + Q => m_axi_awqos(3), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +S_AXI_AREADY_I_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"82FF" + ) + port map ( + I0 => \USE_B_CHANNEL.cmd_b_queue_n_15\, + I1 => \pushed_commands_reg__0\(3), + I2 => num_transactions_q(3), + I3 => access_is_incr_q, + O => S_AXI_AREADY_I_i_3_n_0 + ); +S_AXI_AREADY_I_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \USE_B_CHANNEL.cmd_b_queue_n_21\, + Q => \^e\(0), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_ASIZE_Q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awsize(0), + Q => m_axi_awsize(0), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_ASIZE_Q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awsize(1), + Q => m_axi_awsize(1), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\S_AXI_ASIZE_Q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awsize(2), + Q => m_axi_awsize(2), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\USE_BURSTS.cmd_queue\: entity work.Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_axic_fifo + port map ( + D(4) => \USE_BURSTS.cmd_queue_n_13\, + D(3) => \USE_BURSTS.cmd_queue_n_14\, + D(2) => \USE_BURSTS.cmd_queue_n_15\, + D(1) => \USE_BURSTS.cmd_queue_n_16\, + D(0) => \USE_BURSTS.cmd_queue_n_17\, + E(0) => \USE_BURSTS.cmd_queue_n_19\, + Q(5 downto 0) => \cmd_depth_reg__0\(5 downto 0), + SR(0) => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\, + \S_AXI_AID_Q_reg[0]\ => \^din\(4), + \S_AXI_ALEN_Q_reg[3]\(3 downto 0) => S_AXI_ALEN_Q(3 downto 0), + aclk => aclk, + \allow_split_cmd__1\ => \allow_split_cmd__1\, + aresetn => aresetn, + \cmd_depth_reg[5]\ => \USE_BURSTS.cmd_queue_n_12\, + cmd_empty_reg => \USE_B_CHANNEL.cmd_b_queue_n_13\, + cmd_push_block => cmd_push_block, + command_ongoing => command_ongoing, + din(3 downto 0) => \^din\(3 downto 0), + dout(4 downto 0) => dout(4 downto 0), + empty => empty, + full => \inst/full\, + m_axi_wready => m_axi_wready, + m_axi_wvalid => m_axi_wvalid, + multiple_id_non_split => multiple_id_non_split, + multiple_id_non_split_reg => \USE_BURSTS.cmd_queue_n_23\, + need_to_split_q => need_to_split_q, + \pushed_commands_reg[3]\(3 downto 0) => \pushed_commands_reg__0\(3 downto 0), + queue_id => queue_id, + \queue_id_reg[0]\ => \USE_BURSTS.cmd_queue_n_21\, + ram_full_i_reg => \inst/full_0\, + s_axi_wready => s_axi_wready, + s_axi_wvalid => s_axi_wvalid, + split_in_progress_reg => \USE_BURSTS.cmd_queue_n_22\, + split_in_progress_reg_0 => \USE_B_CHANNEL.cmd_b_queue_n_14\, + split_in_progress_reg_1 => split_in_progress_reg_n_0, + wr_cmd_ready => wr_cmd_ready + ); +\USE_B_CHANNEL.cmd_b_depth[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \USE_B_CHANNEL.cmd_b_depth_reg__0\(0), + O => \USE_B_CHANNEL.cmd_b_depth[0]_i_1_n_0\ + ); +\USE_B_CHANNEL.cmd_b_depth_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \USE_B_CHANNEL.cmd_b_queue_n_17\, + D => \USE_B_CHANNEL.cmd_b_depth[0]_i_1_n_0\, + Q => \USE_B_CHANNEL.cmd_b_depth_reg__0\(0), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\USE_B_CHANNEL.cmd_b_depth_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \USE_B_CHANNEL.cmd_b_queue_n_17\, + D => \USE_B_CHANNEL.cmd_b_queue_n_11\, + Q => \USE_B_CHANNEL.cmd_b_depth_reg__0\(1), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\USE_B_CHANNEL.cmd_b_depth_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \USE_B_CHANNEL.cmd_b_queue_n_17\, + D => \USE_B_CHANNEL.cmd_b_queue_n_10\, + Q => \USE_B_CHANNEL.cmd_b_depth_reg__0\(2), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\USE_B_CHANNEL.cmd_b_depth_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \USE_B_CHANNEL.cmd_b_queue_n_17\, + D => \USE_B_CHANNEL.cmd_b_queue_n_9\, + Q => \USE_B_CHANNEL.cmd_b_depth_reg__0\(3), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\USE_B_CHANNEL.cmd_b_depth_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \USE_B_CHANNEL.cmd_b_queue_n_17\, + D => \USE_B_CHANNEL.cmd_b_queue_n_8\, + Q => \USE_B_CHANNEL.cmd_b_depth_reg__0\(4), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\USE_B_CHANNEL.cmd_b_depth_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \USE_B_CHANNEL.cmd_b_queue_n_17\, + D => \USE_B_CHANNEL.cmd_b_queue_n_7\, + Q => \USE_B_CHANNEL.cmd_b_depth_reg__0\(5), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\USE_B_CHANNEL.cmd_b_empty_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000100" + ) + port map ( + I0 => \USE_B_CHANNEL.cmd_b_depth_reg__0\(4), + I1 => \USE_B_CHANNEL.cmd_b_depth_reg__0\(3), + I2 => \USE_B_CHANNEL.cmd_b_depth_reg__0\(5), + I3 => \USE_B_CHANNEL.cmd_b_depth_reg__0\(0), + I4 => \USE_B_CHANNEL.cmd_b_depth_reg__0\(1), + I5 => \USE_B_CHANNEL.cmd_b_depth_reg__0\(2), + O => almost_b_empty + ); +\USE_B_CHANNEL.cmd_b_empty_reg\: unisim.vcomponents.FDSE + port map ( + C => aclk, + CE => '1', + D => \USE_B_CHANNEL.cmd_b_queue_n_18\, + Q => cmd_b_empty, + S => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\USE_B_CHANNEL.cmd_b_queue\: entity work.Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_axic_fifo_0 + port map ( + D(4) => \USE_B_CHANNEL.cmd_b_queue_n_7\, + D(3) => \USE_B_CHANNEL.cmd_b_queue_n_8\, + D(2) => \USE_B_CHANNEL.cmd_b_queue_n_9\, + D(1) => \USE_B_CHANNEL.cmd_b_queue_n_10\, + D(0) => \USE_B_CHANNEL.cmd_b_queue_n_11\, + E(0) => \USE_B_CHANNEL.cmd_b_queue_n_17\, + Q(5 downto 0) => \USE_B_CHANNEL.cmd_b_depth_reg__0\(5 downto 0), + SR(0) => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\, + \S_AXI_AID_Q_reg[0]\ => \^din\(4), + S_AXI_AREADY_I_reg => \USE_B_CHANNEL.cmd_b_queue_n_21\, + S_AXI_AREADY_I_reg_0 => \^e\(0), + \S_AXI_BRESP_ACC_reg[0]\(4 downto 0) => \S_AXI_BRESP_ACC_reg[0]\(4 downto 0), + \USE_B_CHANNEL.cmd_b_empty_reg\ => \USE_B_CHANNEL.cmd_b_queue_n_18\, + access_is_incr_q => access_is_incr_q, + aclk => aclk, + \allow_split_cmd__1\ => \allow_split_cmd__1\, + almost_b_empty => almost_b_empty, + almost_empty => almost_empty, + areset_d(0) => \^areset_d\(1), + \areset_d_reg[0]\ => \^areset_d\(0), + \areset_d_reg[1]\ => \^command_ongoing_reg_0\, + aresetn => aresetn, + cmd_b_empty => cmd_b_empty, + cmd_b_push_block => cmd_b_push_block, + cmd_b_push_block_reg => \USE_B_CHANNEL.cmd_b_queue_n_16\, + cmd_empty => cmd_empty, + cmd_push_block => cmd_push_block, + cmd_push_block_reg => \USE_B_CHANNEL.cmd_b_queue_n_22\, + command_ongoing => command_ongoing, + command_ongoing_reg => \USE_B_CHANNEL.cmd_b_queue_n_23\, + din(0) => \USE_B_CHANNEL.cmd_b_queue_n_6\, + full => \inst/full_0\, + last_word => last_word, + m_axi_awready => m_axi_awready, + m_axi_awvalid => m_axi_awvalid, + m_axi_bvalid => m_axi_bvalid, + multiple_id_non_split => multiple_id_non_split, + multiple_id_non_split_reg => \USE_B_CHANNEL.cmd_b_queue_n_13\, + multiple_id_non_split_reg_0 => \USE_B_CHANNEL.cmd_b_queue_n_14\, + need_to_split_q => need_to_split_q, + \num_transactions_q_reg[3]\(3 downto 0) => num_transactions_q(3 downto 0), + \pushed_commands_reg[0]\(0) => pushed_new_cmd, + \pushed_commands_reg[3]\(3 downto 0) => \pushed_commands_reg__0\(3 downto 0), + \pushed_commands_reg[3]_0\ => S_AXI_AREADY_I_i_3_n_0, + queue_id => queue_id, + ram_full_i_reg => \inst/full\, + s_axi_awvalid => s_axi_awvalid, + s_axi_bready => s_axi_bready, + split_in_progress_reg => split_in_progress_reg_n_0, + split_ongoing_reg => \USE_B_CHANNEL.cmd_b_queue_n_15\, + wr_cmd_ready => wr_cmd_ready + ); +access_is_incr_q_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => s_axi_awburst(0), + I1 => s_axi_awburst(1), + O => access_is_incr + ); +access_is_incr_q_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => access_is_incr, + Q => access_is_incr_q, + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\addr_step_q[10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => s_axi_awsize(1), + I1 => s_axi_awsize(2), + I2 => s_axi_awsize(0), + O => addr_step(10) + ); +\addr_step_q[11]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => s_axi_awsize(1), + I1 => s_axi_awsize(0), + I2 => s_axi_awsize(2), + O => addr_step(11) + ); +\addr_step_q[5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => s_axi_awsize(2), + I1 => s_axi_awsize(0), + I2 => s_axi_awsize(1), + O => addr_step(5) + ); +\addr_step_q[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => s_axi_awsize(0), + I1 => s_axi_awsize(1), + I2 => s_axi_awsize(2), + O => addr_step(6) + ); +\addr_step_q[7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => s_axi_awsize(1), + I1 => s_axi_awsize(0), + I2 => s_axi_awsize(2), + O => addr_step(7) + ); +\addr_step_q[8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => s_axi_awsize(0), + I1 => s_axi_awsize(2), + I2 => s_axi_awsize(1), + O => addr_step(8) + ); +\addr_step_q[9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => s_axi_awsize(2), + I1 => s_axi_awsize(0), + I2 => s_axi_awsize(1), + O => addr_step(9) + ); +\addr_step_q_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => addr_step(10), + Q => addr_step_q(10), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\addr_step_q_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => addr_step(11), + Q => addr_step_q(11), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\addr_step_q_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => addr_step(5), + Q => addr_step_q(5), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\addr_step_q_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => addr_step(6), + Q => addr_step_q(6), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\addr_step_q_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => addr_step(7), + Q => addr_step_q(7), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\addr_step_q_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => addr_step(8), + Q => addr_step_q(8), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\addr_step_q_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => addr_step(9), + Q => addr_step_q(9), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\areset_d_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\, + Q => \^areset_d\(0), + R => '0' + ); +\areset_d_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \^areset_d\(0), + Q => \^areset_d\(1), + R => '0' + ); +cmd_b_push_block_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \USE_B_CHANNEL.cmd_b_queue_n_16\, + Q => cmd_b_push_block, + R => '0' + ); +\cmd_depth[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \cmd_depth_reg__0\(0), + O => \cmd_depth[0]_i_1_n_0\ + ); +\cmd_depth_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \USE_BURSTS.cmd_queue_n_19\, + D => \cmd_depth[0]_i_1_n_0\, + Q => \cmd_depth_reg__0\(0), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\cmd_depth_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \USE_BURSTS.cmd_queue_n_19\, + D => \USE_BURSTS.cmd_queue_n_17\, + Q => \cmd_depth_reg__0\(1), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\cmd_depth_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \USE_BURSTS.cmd_queue_n_19\, + D => \USE_BURSTS.cmd_queue_n_16\, + Q => \cmd_depth_reg__0\(2), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\cmd_depth_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \USE_BURSTS.cmd_queue_n_19\, + D => \USE_BURSTS.cmd_queue_n_15\, + Q => \cmd_depth_reg__0\(3), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\cmd_depth_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \USE_BURSTS.cmd_queue_n_19\, + D => \USE_BURSTS.cmd_queue_n_14\, + Q => \cmd_depth_reg__0\(4), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\cmd_depth_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \USE_BURSTS.cmd_queue_n_19\, + D => \USE_BURSTS.cmd_queue_n_13\, + Q => \cmd_depth_reg__0\(5), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +cmd_empty_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"CB08" + ) + port map ( + I0 => almost_empty, + I1 => wr_cmd_ready, + I2 => \USE_BURSTS.cmd_queue_n_12\, + I3 => cmd_empty, + O => cmd_empty_i_1_n_0 + ); +cmd_empty_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000100" + ) + port map ( + I0 => \cmd_depth_reg__0\(4), + I1 => \cmd_depth_reg__0\(3), + I2 => \cmd_depth_reg__0\(5), + I3 => \cmd_depth_reg__0\(0), + I4 => \cmd_depth_reg__0\(1), + I5 => \cmd_depth_reg__0\(2), + O => almost_empty + ); +cmd_empty_reg: unisim.vcomponents.FDSE + port map ( + C => aclk, + CE => '1', + D => cmd_empty_i_1_n_0, + Q => cmd_empty, + S => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +cmd_push_block_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \USE_B_CHANNEL.cmd_b_queue_n_22\, + Q => cmd_push_block, + R => '0' + ); +command_ongoing_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^areset_d\(1), + I1 => \^areset_d\(0), + O => \^command_ongoing_reg_0\ + ); +command_ongoing_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \USE_B_CHANNEL.cmd_b_queue_n_23\, + Q => command_ongoing, + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\first_step_q[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => s_axi_awsize(1), + I1 => s_axi_awsize(0), + I2 => s_axi_awlen(0), + I3 => s_axi_awsize(2), + O => \first_step_q[0]_i_1_n_0\ + ); +\first_step_q[10]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => s_axi_awsize(2), + I1 => \first_step_q[10]_i_2_n_0\, + O => first_step(10) + ); +\first_step_q[10]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2AAA800080000000" + ) + port map ( + I0 => s_axi_awsize(1), + I1 => s_axi_awlen(2), + I2 => s_axi_awlen(0), + I3 => s_axi_awlen(1), + I4 => s_axi_awlen(3), + I5 => s_axi_awsize(0), + O => \first_step_q[10]_i_2_n_0\ + ); +\first_step_q[11]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => s_axi_awsize(2), + I1 => \first_step_q[11]_i_2_n_0\, + O => first_step(11) + ); +\first_step_q[11]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => s_axi_awsize(1), + I1 => s_axi_awlen(3), + I2 => s_axi_awlen(1), + I3 => s_axi_awlen(0), + I4 => s_axi_awlen(2), + I5 => s_axi_awsize(0), + O => \first_step_q[11]_i_2_n_0\ + ); +\first_step_q[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000514" + ) + port map ( + I0 => s_axi_awsize(1), + I1 => s_axi_awsize(0), + I2 => s_axi_awlen(0), + I3 => s_axi_awlen(1), + I4 => s_axi_awsize(2), + O => \first_step_q[1]_i_1_n_0\ + ); +\first_step_q[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000000F3C6A" + ) + port map ( + I0 => s_axi_awlen(2), + I1 => s_axi_awlen(1), + I2 => s_axi_awlen(0), + I3 => s_axi_awsize(0), + I4 => s_axi_awsize(1), + I5 => s_axi_awsize(2), + O => \first_step_q[2]_i_1_n_0\ + ); +\first_step_q[3]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \first_step_q[7]_i_2_n_0\, + I1 => s_axi_awsize(2), + O => \first_step_q[3]_i_1_n_0\ + ); +\first_step_q[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01FF0100" + ) + port map ( + I0 => s_axi_awlen(0), + I1 => s_axi_awsize(0), + I2 => s_axi_awsize(1), + I3 => s_axi_awsize(2), + I4 => \first_step_q[8]_i_2_n_0\, + O => first_step(4) + ); +\first_step_q[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0036FFFF00360000" + ) + port map ( + I0 => s_axi_awlen(1), + I1 => s_axi_awlen(0), + I2 => s_axi_awsize(0), + I3 => s_axi_awsize(1), + I4 => s_axi_awsize(2), + I5 => \first_step_q[9]_i_2_n_0\, + O => first_step(5) + ); +\first_step_q[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \first_step_q[6]_i_2_n_0\, + I1 => s_axi_awsize(2), + I2 => \first_step_q[10]_i_2_n_0\, + O => first_step(6) + ); +\first_step_q[6]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"07531642" + ) + port map ( + I0 => s_axi_awsize(1), + I1 => s_axi_awsize(0), + I2 => s_axi_awlen(0), + I3 => s_axi_awlen(1), + I4 => s_axi_awlen(2), + O => \first_step_q[6]_i_2_n_0\ + ); +\first_step_q[7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \first_step_q[7]_i_2_n_0\, + I1 => s_axi_awsize(2), + I2 => \first_step_q[11]_i_2_n_0\, + O => first_step(7) + ); +\first_step_q[7]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"07FD53B916EC42A8" + ) + port map ( + I0 => s_axi_awsize(1), + I1 => s_axi_awsize(0), + I2 => s_axi_awlen(1), + I3 => s_axi_awlen(0), + I4 => s_axi_awlen(2), + I5 => s_axi_awlen(3), + O => \first_step_q[7]_i_2_n_0\ + ); +\first_step_q[8]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => s_axi_awsize(2), + I1 => \first_step_q[8]_i_2_n_0\, + O => first_step(8) + ); +\first_step_q[8]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"14EAEA6262C8C840" + ) + port map ( + I0 => s_axi_awsize(1), + I1 => s_axi_awsize(0), + I2 => s_axi_awlen(3), + I3 => s_axi_awlen(1), + I4 => s_axi_awlen(0), + I5 => s_axi_awlen(2), + O => \first_step_q[8]_i_2_n_0\ + ); +\first_step_q[9]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => s_axi_awsize(2), + I1 => \first_step_q[9]_i_2_n_0\, + O => first_step(9) + ); +\first_step_q[9]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4AA2A2A228808080" + ) + port map ( + I0 => s_axi_awsize(1), + I1 => s_axi_awsize(0), + I2 => s_axi_awlen(2), + I3 => s_axi_awlen(0), + I4 => s_axi_awlen(1), + I5 => s_axi_awlen(3), + O => \first_step_q[9]_i_2_n_0\ + ); +\first_step_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => \first_step_q[0]_i_1_n_0\, + Q => first_step_q(0), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\first_step_q_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => first_step(10), + Q => first_step_q(10), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\first_step_q_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => first_step(11), + Q => first_step_q(11), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\first_step_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => \first_step_q[1]_i_1_n_0\, + Q => first_step_q(1), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\first_step_q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => \first_step_q[2]_i_1_n_0\, + Q => first_step_q(2), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\first_step_q_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => \first_step_q[3]_i_1_n_0\, + Q => first_step_q(3), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\first_step_q_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => first_step(4), + Q => first_step_q(4), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\first_step_q_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => first_step(5), + Q => first_step_q(5), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\first_step_q_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => first_step(6), + Q => first_step_q(6), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\first_step_q_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => first_step(7), + Q => first_step_q(7), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\first_step_q_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => first_step(8), + Q => first_step_q(8), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\first_step_q_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => first_step(9), + Q => first_step_q(9), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +incr_need_to_split: unisim.vcomponents.LUT6 + generic map( + INIT => X"4444444444444440" + ) + port map ( + I0 => s_axi_awburst(1), + I1 => s_axi_awburst(0), + I2 => s_axi_awlen(5), + I3 => s_axi_awlen(4), + I4 => s_axi_awlen(6), + I5 => s_axi_awlen(7), + O => \incr_need_to_split__0\ + ); +incr_need_to_split_q_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => \incr_need_to_split__0\, + Q => need_to_split_q, + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(0), + I1 => size_mask_q(0), + I2 => S_AXI_AADDR_Q(0), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(0) + ); +\m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(10), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(10), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(10) + ); +\m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(11), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(11), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(11) + ); +\m_axi_awaddr[12]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(12), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(12), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(12) + ); +\m_axi_awaddr[13]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(13), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(13), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(13) + ); +\m_axi_awaddr[14]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(14), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(14), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(14) + ); +\m_axi_awaddr[15]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(15), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(15), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(15) + ); +\m_axi_awaddr[16]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(16), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(16), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(16) + ); +\m_axi_awaddr[17]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(17), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(17), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(17) + ); +\m_axi_awaddr[18]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(18), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(18), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(18) + ); +\m_axi_awaddr[19]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(19), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(19), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(19) + ); +\m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(1), + I1 => size_mask_q(1), + I2 => S_AXI_AADDR_Q(1), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(1) + ); +\m_axi_awaddr[20]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(20), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(20), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(20) + ); +\m_axi_awaddr[21]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(21), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(21), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(21) + ); +\m_axi_awaddr[22]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(22), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(22), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(22) + ); +\m_axi_awaddr[23]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(23), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(23), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(23) + ); +\m_axi_awaddr[24]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(24), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(24), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(24) + ); +\m_axi_awaddr[25]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(25), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(25), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(25) + ); +\m_axi_awaddr[26]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(26), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(26), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(26) + ); +\m_axi_awaddr[27]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(27), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(27), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(27) + ); +\m_axi_awaddr[28]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(28), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(28), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(28) + ); +\m_axi_awaddr[29]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(29), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(29), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(29) + ); +\m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(2), + I1 => size_mask_q(2), + I2 => S_AXI_AADDR_Q(2), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(2) + ); +\m_axi_awaddr[30]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(30), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(30), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(30) + ); +\m_axi_awaddr[31]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(31), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(31), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(31) + ); +\m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(3), + I1 => size_mask_q(3), + I2 => S_AXI_AADDR_Q(3), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(3) + ); +\m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(4), + I1 => size_mask_q(4), + I2 => S_AXI_AADDR_Q(4), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(4) + ); +\m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(5), + I1 => size_mask_q(5), + I2 => S_AXI_AADDR_Q(5), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(5) + ); +\m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(6), + I1 => size_mask_q(6), + I2 => S_AXI_AADDR_Q(6), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(6) + ); +\m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(7), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(7), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(7) + ); +\m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(8), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(8), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(8) + ); +\m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(9), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(9), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \^m_axi_awaddr\(9) + ); +\m_axi_awlock[0]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \S_AXI_ALOCK_Q_reg_n_0_[0]\, + I1 => need_to_split_q, + O => m_axi_awlock(0) + ); +multiple_id_non_split_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \USE_BURSTS.cmd_queue_n_23\, + Q => multiple_id_non_split, + R => '0' + ); +\next_mi_addr[11]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"569A" + ) + port map ( + I0 => \^m_axi_awaddr\(11), + I1 => \first_split__2\, + I2 => addr_step_q(11), + I3 => first_step_q(11), + O => \next_mi_addr[11]_i_2_n_0\ + ); +\next_mi_addr[11]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"569A" + ) + port map ( + I0 => \^m_axi_awaddr\(10), + I1 => \first_split__2\, + I2 => addr_step_q(10), + I3 => first_step_q(10), + O => \next_mi_addr[11]_i_3_n_0\ + ); +\next_mi_addr[11]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"569A" + ) + port map ( + I0 => \^m_axi_awaddr\(9), + I1 => \first_split__2\, + I2 => addr_step_q(9), + I3 => first_step_q(9), + O => \next_mi_addr[11]_i_4_n_0\ + ); +\next_mi_addr[11]_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"569A" + ) + port map ( + I0 => \^m_axi_awaddr\(8), + I1 => \first_split__2\, + I2 => addr_step_q(8), + I3 => first_step_q(8), + O => \next_mi_addr[11]_i_5_n_0\ + ); +\next_mi_addr[11]_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => \pushed_commands_reg__0\(2), + I1 => \pushed_commands_reg__0\(3), + I2 => \pushed_commands_reg__0\(1), + I3 => \pushed_commands_reg__0\(0), + O => \first_split__2\ + ); +\next_mi_addr[15]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(15), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(15), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[15]_i_2_n_0\ + ); +\next_mi_addr[15]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(14), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(14), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[15]_i_3_n_0\ + ); +\next_mi_addr[15]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(13), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(13), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[15]_i_4_n_0\ + ); +\next_mi_addr[15]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(12), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(12), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[15]_i_5_n_0\ + ); +\next_mi_addr[15]_i_6\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(15), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(15), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[15]_i_6_n_0\ + ); +\next_mi_addr[15]_i_7\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(14), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(14), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[15]_i_7_n_0\ + ); +\next_mi_addr[15]_i_8\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(13), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(13), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[15]_i_8_n_0\ + ); +\next_mi_addr[15]_i_9\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(12), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(12), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[15]_i_9_n_0\ + ); +\next_mi_addr[19]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(19), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(19), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[19]_i_2_n_0\ + ); +\next_mi_addr[19]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(18), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(18), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[19]_i_3_n_0\ + ); +\next_mi_addr[19]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(17), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(17), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[19]_i_4_n_0\ + ); +\next_mi_addr[19]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(16), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(16), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[19]_i_5_n_0\ + ); +\next_mi_addr[23]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(23), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(23), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[23]_i_2_n_0\ + ); +\next_mi_addr[23]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(22), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(22), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[23]_i_3_n_0\ + ); +\next_mi_addr[23]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(21), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(21), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[23]_i_4_n_0\ + ); +\next_mi_addr[23]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88F0F0F0" + ) + port map ( + I0 => next_mi_addr(20), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(20), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[23]_i_5_n_0\ + ); +\next_mi_addr[27]_i_2\: unisim.vcomponents.LUT5 generic map( - INIT => X"1" + INIT => X"88F0F0F0" ) port map ( - I0 => aresetn, - O => \^sr\(0) + I0 => next_mi_addr(27), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(27), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[27]_i_2_n_0\ ); -S_AXI_AREADY_I_i_2: unisim.vcomponents.LUT6 +\next_mi_addr[27]_i_3\: unisim.vcomponents.LUT5 generic map( - INIT => X"444444F4FFFF44F4" + INIT => X"88F0F0F0" ) port map ( - I0 => \areset_d_reg[1]\(0), - I1 => \areset_d_reg[1]\(1), - I2 => \^pushed_commands_reg[0]\, - I3 => S_AXI_AREADY_I_i_3_n_0, - I4 => S_AXI_AREADY_I_reg_0, - I5 => s_axi_arvalid, - O => S_AXI_AREADY_I_reg + I0 => next_mi_addr(26), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(26), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[27]_i_3_n_0\ ); -S_AXI_AREADY_I_i_3: unisim.vcomponents.LUT6 +\next_mi_addr[27]_i_4\: unisim.vcomponents.LUT5 generic map( - INIT => X"8AA8AAAAAAAA8AA8" + INIT => X"88F0F0F0" ) port map ( - I0 => access_is_incr_q, - I1 => S_AXI_AREADY_I_i_4_n_0, - I2 => num_transactions_q(3), - I3 => \pushed_commands_reg[3]\(3), - I4 => num_transactions_q(1), - I5 => \pushed_commands_reg[3]\(1), - O => S_AXI_AREADY_I_i_3_n_0 + I0 => next_mi_addr(25), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(25), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[27]_i_4_n_0\ ); -S_AXI_AREADY_I_i_4: unisim.vcomponents.LUT4 +\next_mi_addr[27]_i_5\: unisim.vcomponents.LUT5 generic map( - INIT => X"6FF6" + INIT => X"88F0F0F0" ) port map ( - I0 => num_transactions_q(0), - I1 => \pushed_commands_reg[3]\(0), - I2 => num_transactions_q(2), - I3 => \pushed_commands_reg[3]\(2), - O => S_AXI_AREADY_I_i_4_n_0 + I0 => next_mi_addr(24), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(24), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[27]_i_5_n_0\ ); -\cmd_depth[1]_i_1\: unisim.vcomponents.LUT3 +\next_mi_addr[31]_i_2\: unisim.vcomponents.LUT5 generic map( - INIT => X"69" + INIT => X"88F0F0F0" ) port map ( - I0 => \^cmd_depth_reg[1]\, - I1 => Q(0), - I2 => Q(1), - O => D(0) + I0 => next_mi_addr(31), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(31), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[31]_i_2_n_0\ ); -\cmd_depth[2]_i_1\: unisim.vcomponents.LUT4 +\next_mi_addr[31]_i_3\: unisim.vcomponents.LUT5 generic map( - INIT => X"6AA9" + INIT => X"88F0F0F0" ) port map ( - I0 => Q(2), - I1 => Q(1), - I2 => \^cmd_depth_reg[1]\, - I3 => Q(0), - O => D(1) + I0 => next_mi_addr(30), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(30), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[31]_i_3_n_0\ ); -\cmd_depth[3]_i_1\: unisim.vcomponents.LUT5 +\next_mi_addr[31]_i_4\: unisim.vcomponents.LUT5 generic map( - INIT => X"6AAAAAA9" + INIT => X"88F0F0F0" ) port map ( - I0 => Q(3), - I1 => Q(1), - I2 => Q(0), - I3 => \^cmd_depth_reg[1]\, - I4 => Q(2), - O => D(2) + I0 => next_mi_addr(29), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(29), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[31]_i_4_n_0\ ); -\cmd_depth[4]_i_1\: unisim.vcomponents.LUT6 +\next_mi_addr[31]_i_5\: unisim.vcomponents.LUT5 generic map( - INIT => X"6AAAAAAAAAAAAAA9" + INIT => X"88F0F0F0" ) port map ( - I0 => Q(4), - I1 => Q(2), - I2 => Q(1), - I3 => Q(3), - I4 => \^cmd_depth_reg[1]\, - I5 => Q(0), - O => D(3) + I0 => next_mi_addr(28), + I1 => size_mask_q(31), + I2 => S_AXI_AADDR_Q(28), + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[31]_i_5_n_0\ ); -\cmd_depth[5]_i_1\: unisim.vcomponents.LUT5 +\next_mi_addr[3]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FF7F0080" + INIT => X"1BBBE444E444E444" ) port map ( - I0 => m_axi_rlast, - I1 => s_axi_rready, - I2 => m_axi_rvalid, - I3 => empty, - I4 => \^wr_en\, - O => E(0) + I0 => \M_AXI_AADDR_I1__0\, + I1 => S_AXI_AADDR_Q(3), + I2 => size_mask_q(3), + I3 => next_mi_addr(3), + I4 => \first_split__2\, + I5 => first_step_q(3), + O => \next_mi_addr[3]_i_2_n_0\ ); -\cmd_depth[5]_i_2\: unisim.vcomponents.LUT6 +\next_mi_addr[3]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"AAA9AAAA6AA96AAA" + INIT => X"1BBBE444E444E444" ) port map ( - I0 => Q(5), - I1 => Q(4), - I2 => Q(0), - I3 => \^cmd_depth_reg[1]\, - I4 => \cmd_depth_reg[3]\, - I5 => \cmd_depth_reg[1]_0\, - O => D(4) + I0 => \M_AXI_AADDR_I1__0\, + I1 => S_AXI_AADDR_Q(2), + I2 => size_mask_q(2), + I3 => next_mi_addr(2), + I4 => \first_split__2\, + I5 => first_step_q(2), + O => \next_mi_addr[3]_i_3_n_0\ ); -cmd_empty_i_3: unisim.vcomponents.LUT5 +\next_mi_addr[3]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"00000010" + INIT => X"1BBBE444E444E444" ) port map ( - I0 => m_axi_arvalid_INST_0_i_1_n_0, - I1 => full, - I2 => command_ongoing, - I3 => cmd_push_block, - I4 => \^rd_en\, - O => \^cmd_depth_reg[1]\ + I0 => \M_AXI_AADDR_I1__0\, + I1 => S_AXI_AADDR_Q(1), + I2 => size_mask_q(1), + I3 => next_mi_addr(1), + I4 => \first_split__2\, + I5 => first_step_q(1), + O => \next_mi_addr[3]_i_4_n_0\ ); -cmd_push_block_i_1: unisim.vcomponents.LUT5 +\next_mi_addr[3]_i_5\: unisim.vcomponents.LUT6 generic map( - INIT => X"0000AE00" + INIT => X"1BBBE444E444E444" ) port map ( - I0 => cmd_push_block, - I1 => \^wr_en\, - I2 => m_axi_arready, - I3 => aresetn, - I4 => \^pushed_commands_reg[0]\, - O => cmd_push_block_reg + I0 => \M_AXI_AADDR_I1__0\, + I1 => S_AXI_AADDR_Q(0), + I2 => size_mask_q(0), + I3 => next_mi_addr(0), + I4 => \first_split__2\, + I5 => first_step_q(0), + O => \next_mi_addr[3]_i_5_n_0\ + ); +\next_mi_addr[3]_i_6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => split_ongoing, + I1 => access_is_incr_q, + O => \M_AXI_AADDR_I1__0\ + ); +\next_mi_addr[7]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"569A" + ) + port map ( + I0 => \^m_axi_awaddr\(7), + I1 => \first_split__2\, + I2 => addr_step_q(7), + I3 => first_step_q(7), + O => \next_mi_addr[7]_i_2_n_0\ + ); +\next_mi_addr[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"569A" + ) + port map ( + I0 => \^m_axi_awaddr\(6), + I1 => \first_split__2\, + I2 => addr_step_q(6), + I3 => first_step_q(6), + O => \next_mi_addr[7]_i_3_n_0\ + ); +\next_mi_addr[7]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"569A" + ) + port map ( + I0 => \^m_axi_awaddr\(5), + I1 => \first_split__2\, + I2 => addr_step_q(5), + I3 => first_step_q(5), + O => \next_mi_addr[7]_i_4_n_0\ + ); +\next_mi_addr[7]_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"569A" + ) + port map ( + I0 => \^m_axi_awaddr\(4), + I1 => \first_split__2\, + I2 => size_mask_q(0), + I3 => first_step_q(4), + O => \next_mi_addr[7]_i_5_n_0\ + ); +\next_mi_addr_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[3]_i_1_n_7\, + Q => next_mi_addr(0), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\next_mi_addr_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[11]_i_1_n_5\, + Q => next_mi_addr(10), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\next_mi_addr_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[11]_i_1_n_4\, + Q => next_mi_addr(11), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\next_mi_addr_reg[11]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \next_mi_addr_reg[7]_i_1_n_0\, + CO(3) => \next_mi_addr_reg[11]_i_1_n_0\, + CO(2) => \next_mi_addr_reg[11]_i_1_n_1\, + CO(1) => \next_mi_addr_reg[11]_i_1_n_2\, + CO(0) => \next_mi_addr_reg[11]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => \^m_axi_awaddr\(11 downto 8), + O(3) => \next_mi_addr_reg[11]_i_1_n_4\, + O(2) => \next_mi_addr_reg[11]_i_1_n_5\, + O(1) => \next_mi_addr_reg[11]_i_1_n_6\, + O(0) => \next_mi_addr_reg[11]_i_1_n_7\, + S(3) => \next_mi_addr[11]_i_2_n_0\, + S(2) => \next_mi_addr[11]_i_3_n_0\, + S(1) => \next_mi_addr[11]_i_4_n_0\, + S(0) => \next_mi_addr[11]_i_5_n_0\ + ); +\next_mi_addr_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[15]_i_1_n_7\, + Q => next_mi_addr(12), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\next_mi_addr_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[15]_i_1_n_6\, + Q => next_mi_addr(13), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\next_mi_addr_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[15]_i_1_n_5\, + Q => next_mi_addr(14), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\next_mi_addr_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[15]_i_1_n_4\, + Q => next_mi_addr(15), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\next_mi_addr_reg[15]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \next_mi_addr_reg[11]_i_1_n_0\, + CO(3) => \next_mi_addr_reg[15]_i_1_n_0\, + CO(2) => \next_mi_addr_reg[15]_i_1_n_1\, + CO(1) => \next_mi_addr_reg[15]_i_1_n_2\, + CO(0) => \next_mi_addr_reg[15]_i_1_n_3\, + CYINIT => '0', + DI(3) => \next_mi_addr[15]_i_2_n_0\, + DI(2) => \next_mi_addr[15]_i_3_n_0\, + DI(1) => \next_mi_addr[15]_i_4_n_0\, + DI(0) => \next_mi_addr[15]_i_5_n_0\, + O(3) => \next_mi_addr_reg[15]_i_1_n_4\, + O(2) => \next_mi_addr_reg[15]_i_1_n_5\, + O(1) => \next_mi_addr_reg[15]_i_1_n_6\, + O(0) => \next_mi_addr_reg[15]_i_1_n_7\, + S(3) => \next_mi_addr[15]_i_6_n_0\, + S(2) => \next_mi_addr[15]_i_7_n_0\, + S(1) => \next_mi_addr[15]_i_8_n_0\, + S(0) => \next_mi_addr[15]_i_9_n_0\ + ); +\next_mi_addr_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[19]_i_1_n_7\, + Q => next_mi_addr(16), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\next_mi_addr_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[19]_i_1_n_6\, + Q => next_mi_addr(17), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\next_mi_addr_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[19]_i_1_n_5\, + Q => next_mi_addr(18), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\next_mi_addr_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[19]_i_1_n_4\, + Q => next_mi_addr(19), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\next_mi_addr_reg[19]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \next_mi_addr_reg[15]_i_1_n_0\, + CO(3) => \next_mi_addr_reg[19]_i_1_n_0\, + CO(2) => \next_mi_addr_reg[19]_i_1_n_1\, + CO(1) => \next_mi_addr_reg[19]_i_1_n_2\, + CO(0) => \next_mi_addr_reg[19]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \next_mi_addr_reg[19]_i_1_n_4\, + O(2) => \next_mi_addr_reg[19]_i_1_n_5\, + O(1) => \next_mi_addr_reg[19]_i_1_n_6\, + O(0) => \next_mi_addr_reg[19]_i_1_n_7\, + S(3) => \next_mi_addr[19]_i_2_n_0\, + S(2) => \next_mi_addr[19]_i_3_n_0\, + S(1) => \next_mi_addr[19]_i_4_n_0\, + S(0) => \next_mi_addr[19]_i_5_n_0\ + ); +\next_mi_addr_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[3]_i_1_n_6\, + Q => next_mi_addr(1), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ ); -command_ongoing_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFFDDD0000F000" - ) - port map ( - I0 => \^pushed_commands_reg[0]\, - I1 => S_AXI_AREADY_I_i_3_n_0, - I2 => S_AXI_AREADY_I_reg_0, - I3 => s_axi_arvalid, - I4 => \areset_d_reg[1]_0\, - I5 => command_ongoing, - O => command_ongoing_reg +\next_mi_addr_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[23]_i_1_n_7\, + Q => next_mi_addr(20), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ ); -fifo_gen_inst: entity work.Arty_Z7_20_auto_pc_0_fifo_generator_v13_1_3 +\next_mi_addr_reg[21]\: unisim.vcomponents.FDRE port map ( - almost_empty => NLW_fifo_gen_inst_almost_empty_UNCONNECTED, - almost_full => NLW_fifo_gen_inst_almost_full_UNCONNECTED, - axi_ar_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED(4 downto 0), - axi_ar_dbiterr => NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED, - axi_ar_injectdbiterr => '0', - axi_ar_injectsbiterr => '0', - axi_ar_overflow => NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED, - axi_ar_prog_empty => NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED, - axi_ar_prog_empty_thresh(3 downto 0) => B"0000", - axi_ar_prog_full => NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED, - axi_ar_prog_full_thresh(3 downto 0) => B"0000", - axi_ar_rd_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED(4 downto 0), - axi_ar_sbiterr => NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED, - axi_ar_underflow => NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED, - axi_ar_wr_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED(4 downto 0), - axi_aw_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED(4 downto 0), - axi_aw_dbiterr => NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED, - axi_aw_injectdbiterr => '0', - axi_aw_injectsbiterr => '0', - axi_aw_overflow => NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED, - axi_aw_prog_empty => NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED, - axi_aw_prog_empty_thresh(3 downto 0) => B"0000", - axi_aw_prog_full => NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED, - axi_aw_prog_full_thresh(3 downto 0) => B"0000", - axi_aw_rd_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED(4 downto 0), - axi_aw_sbiterr => NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED, - axi_aw_underflow => NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED, - axi_aw_wr_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED(4 downto 0), - axi_b_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED(4 downto 0), - axi_b_dbiterr => NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED, - axi_b_injectdbiterr => '0', - axi_b_injectsbiterr => '0', - axi_b_overflow => NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED, - axi_b_prog_empty => NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED, - axi_b_prog_empty_thresh(3 downto 0) => B"0000", - axi_b_prog_full => NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED, - axi_b_prog_full_thresh(3 downto 0) => B"0000", - axi_b_rd_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED(4 downto 0), - axi_b_sbiterr => NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED, - axi_b_underflow => NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED, - axi_b_wr_data_count(4 downto 0) => NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED(4 downto 0), - axi_r_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED(10 downto 0), - axi_r_dbiterr => NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED, - axi_r_injectdbiterr => '0', - axi_r_injectsbiterr => '0', - axi_r_overflow => NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED, - axi_r_prog_empty => NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED, - axi_r_prog_empty_thresh(9 downto 0) => B"0000000000", - axi_r_prog_full => NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED, - axi_r_prog_full_thresh(9 downto 0) => B"0000000000", - axi_r_rd_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED(10 downto 0), - axi_r_sbiterr => NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED, - axi_r_underflow => NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED, - axi_r_wr_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED(10 downto 0), - axi_w_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED(10 downto 0), - axi_w_dbiterr => NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED, - axi_w_injectdbiterr => '0', - axi_w_injectsbiterr => '0', - axi_w_overflow => NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED, - axi_w_prog_empty => NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED, - axi_w_prog_empty_thresh(9 downto 0) => B"0000000000", - axi_w_prog_full => NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED, - axi_w_prog_full_thresh(9 downto 0) => B"0000000000", - axi_w_rd_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED(10 downto 0), - axi_w_sbiterr => NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED, - axi_w_underflow => NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED, - axi_w_wr_data_count(10 downto 0) => NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED(10 downto 0), - axis_data_count(10 downto 0) => NLW_fifo_gen_inst_axis_data_count_UNCONNECTED(10 downto 0), - axis_dbiterr => NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED, - axis_injectdbiterr => '0', - axis_injectsbiterr => '0', - axis_overflow => NLW_fifo_gen_inst_axis_overflow_UNCONNECTED, - axis_prog_empty => NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED, - axis_prog_empty_thresh(9 downto 0) => B"0000000000", - axis_prog_full => NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED, - axis_prog_full_thresh(9 downto 0) => B"0000000000", - axis_rd_data_count(10 downto 0) => NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED(10 downto 0), - axis_sbiterr => NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED, - axis_underflow => NLW_fifo_gen_inst_axis_underflow_UNCONNECTED, - axis_wr_data_count(10 downto 0) => NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED(10 downto 0), - backup => '0', - backup_marker => '0', - clk => aclk, - data_count(5 downto 0) => NLW_fifo_gen_inst_data_count_UNCONNECTED(5 downto 0), - dbiterr => NLW_fifo_gen_inst_dbiterr_UNCONNECTED, - din(0) => \^din\(0), - dout(0) => rd_cmd_split, - empty => empty, - full => full, - injectdbiterr => '0', - injectsbiterr => '0', - int_clk => '0', - m_aclk => '0', - m_aclk_en => '0', - m_axi_araddr(31 downto 0) => NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED(31 downto 0), - m_axi_arburst(1 downto 0) => NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED(1 downto 0), - m_axi_arcache(3 downto 0) => NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED(3 downto 0), - m_axi_arid(3 downto 0) => NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED(3 downto 0), - m_axi_arlen(7 downto 0) => NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED(7 downto 0), - m_axi_arlock(1 downto 0) => NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED(1 downto 0), - m_axi_arprot(2 downto 0) => NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED(2 downto 0), - m_axi_arqos(3 downto 0) => NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED(3 downto 0), - m_axi_arready => '0', - m_axi_arregion(3 downto 0) => NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED(3 downto 0), - m_axi_arsize(2 downto 0) => NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED(2 downto 0), - m_axi_aruser(0) => NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED(0), - m_axi_arvalid => NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED, - m_axi_awaddr(31 downto 0) => NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED(31 downto 0), - m_axi_awburst(1 downto 0) => NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED(1 downto 0), - m_axi_awcache(3 downto 0) => NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED(3 downto 0), - m_axi_awid(3 downto 0) => NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED(3 downto 0), - m_axi_awlen(7 downto 0) => NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED(7 downto 0), - m_axi_awlock(1 downto 0) => NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED(1 downto 0), - m_axi_awprot(2 downto 0) => NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED(2 downto 0), - m_axi_awqos(3 downto 0) => NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED(3 downto 0), - m_axi_awready => '0', - m_axi_awregion(3 downto 0) => NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED(3 downto 0), - m_axi_awsize(2 downto 0) => NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED(2 downto 0), - m_axi_awuser(0) => NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED(0), - m_axi_awvalid => NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED, - m_axi_bid(3 downto 0) => B"0000", - m_axi_bready => NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED, - m_axi_bresp(1 downto 0) => B"00", - m_axi_buser(0) => '0', - m_axi_bvalid => '0', - m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", - m_axi_rid(3 downto 0) => B"0000", - m_axi_rlast => '0', - m_axi_rready => NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED, - m_axi_rresp(1 downto 0) => B"00", - m_axi_ruser(0) => '0', - m_axi_rvalid => '0', - m_axi_wdata(63 downto 0) => NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED(63 downto 0), - m_axi_wid(3 downto 0) => NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED(3 downto 0), - m_axi_wlast => NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED, - m_axi_wready => '0', - m_axi_wstrb(7 downto 0) => NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED(7 downto 0), - m_axi_wuser(0) => NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED(0), - m_axi_wvalid => NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED, - m_axis_tdata(63 downto 0) => NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED(63 downto 0), - m_axis_tdest(3 downto 0) => NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED(3 downto 0), - m_axis_tid(7 downto 0) => NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED(7 downto 0), - m_axis_tkeep(3 downto 0) => NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED(3 downto 0), - m_axis_tlast => NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED, - m_axis_tready => '0', - m_axis_tstrb(3 downto 0) => NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED(3 downto 0), - m_axis_tuser(3 downto 0) => NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED(3 downto 0), - m_axis_tvalid => NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED, - overflow => NLW_fifo_gen_inst_overflow_UNCONNECTED, - prog_empty => NLW_fifo_gen_inst_prog_empty_UNCONNECTED, - prog_empty_thresh(4 downto 0) => B"00000", - prog_empty_thresh_assert(4 downto 0) => B"00000", - prog_empty_thresh_negate(4 downto 0) => B"00000", - prog_full => NLW_fifo_gen_inst_prog_full_UNCONNECTED, - prog_full_thresh(4 downto 0) => B"00000", - prog_full_thresh_assert(4 downto 0) => B"00000", - prog_full_thresh_negate(4 downto 0) => B"00000", - rd_clk => '0', - rd_data_count(5 downto 0) => NLW_fifo_gen_inst_rd_data_count_UNCONNECTED(5 downto 0), - rd_en => \^rd_en\, - rd_rst => '0', - rd_rst_busy => NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED, - rst => \^sr\(0), - s_aclk => '0', - s_aclk_en => '0', - s_aresetn => '0', - s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", - s_axi_arburst(1 downto 0) => B"00", - s_axi_arcache(3 downto 0) => B"0000", - s_axi_arid(3 downto 0) => B"0000", - s_axi_arlen(7 downto 0) => B"00000000", - s_axi_arlock(1 downto 0) => B"00", - s_axi_arprot(2 downto 0) => B"000", - s_axi_arqos(3 downto 0) => B"0000", - s_axi_arready => NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED, - s_axi_arregion(3 downto 0) => B"0000", - s_axi_arsize(2 downto 0) => B"000", - s_axi_aruser(0) => '0', - s_axi_arvalid => '0', - s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", - s_axi_awburst(1 downto 0) => B"00", - s_axi_awcache(3 downto 0) => B"0000", - s_axi_awid(3 downto 0) => B"0000", - s_axi_awlen(7 downto 0) => B"00000000", - s_axi_awlock(1 downto 0) => B"00", - s_axi_awprot(2 downto 0) => B"000", - s_axi_awqos(3 downto 0) => B"0000", - s_axi_awready => NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED, - s_axi_awregion(3 downto 0) => B"0000", - s_axi_awsize(2 downto 0) => B"000", - s_axi_awuser(0) => '0', - s_axi_awvalid => '0', - s_axi_bid(3 downto 0) => NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED(3 downto 0), - s_axi_bready => '0', - s_axi_bresp(1 downto 0) => NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED(1 downto 0), - s_axi_buser(0) => NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED(0), - s_axi_bvalid => NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED, - s_axi_rdata(63 downto 0) => NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED(63 downto 0), - s_axi_rid(3 downto 0) => NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED(3 downto 0), - s_axi_rlast => NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED, - s_axi_rready => '0', - s_axi_rresp(1 downto 0) => NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED(1 downto 0), - s_axi_ruser(0) => NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED(0), - s_axi_rvalid => NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED, - s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", - s_axi_wid(3 downto 0) => B"0000", - s_axi_wlast => '0', - s_axi_wready => NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED, - s_axi_wstrb(7 downto 0) => B"00000000", - s_axi_wuser(0) => '0', - s_axi_wvalid => '0', - s_axis_tdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", - s_axis_tdest(3 downto 0) => B"0000", - s_axis_tid(7 downto 0) => B"00000000", - s_axis_tkeep(3 downto 0) => B"0000", - s_axis_tlast => '0', - s_axis_tready => NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED, - s_axis_tstrb(3 downto 0) => B"0000", - s_axis_tuser(3 downto 0) => B"0000", - s_axis_tvalid => '0', - sbiterr => NLW_fifo_gen_inst_sbiterr_UNCONNECTED, - sleep => '0', - srst => '0', - underflow => NLW_fifo_gen_inst_underflow_UNCONNECTED, - valid => NLW_fifo_gen_inst_valid_UNCONNECTED, - wr_ack => NLW_fifo_gen_inst_wr_ack_UNCONNECTED, - wr_clk => '0', - wr_data_count(5 downto 0) => NLW_fifo_gen_inst_wr_data_count_UNCONNECTED(5 downto 0), - wr_en => \^wr_en\, - wr_rst => '0', - wr_rst_busy => NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[23]_i_1_n_6\, + Q => next_mi_addr(21), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\next_mi_addr_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[23]_i_1_n_5\, + Q => next_mi_addr(22), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ ); -fifo_gen_inst_i_1: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => S_AXI_AREADY_I_i_3_n_0, - I1 => need_to_split_q, - O => \^din\(0) +\next_mi_addr_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[23]_i_1_n_4\, + Q => next_mi_addr(23), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ ); -fifo_gen_inst_i_2: unisim.vcomponents.LUT4 - generic map( - INIT => X"0010" - ) - port map ( - I0 => m_axi_arvalid_INST_0_i_1_n_0, - I1 => cmd_push_block, - I2 => command_ongoing, - I3 => full, - O => \^wr_en\ +\next_mi_addr_reg[23]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \next_mi_addr_reg[19]_i_1_n_0\, + CO(3) => \next_mi_addr_reg[23]_i_1_n_0\, + CO(2) => \next_mi_addr_reg[23]_i_1_n_1\, + CO(1) => \next_mi_addr_reg[23]_i_1_n_2\, + CO(0) => \next_mi_addr_reg[23]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \next_mi_addr_reg[23]_i_1_n_4\, + O(2) => \next_mi_addr_reg[23]_i_1_n_5\, + O(1) => \next_mi_addr_reg[23]_i_1_n_6\, + O(0) => \next_mi_addr_reg[23]_i_1_n_7\, + S(3) => \next_mi_addr[23]_i_2_n_0\, + S(2) => \next_mi_addr[23]_i_3_n_0\, + S(1) => \next_mi_addr[23]_i_4_n_0\, + S(0) => \next_mi_addr[23]_i_5_n_0\ ); -fifo_gen_inst_i_3: unisim.vcomponents.LUT4 +\next_mi_addr_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[27]_i_1_n_7\, + Q => next_mi_addr(24), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\next_mi_addr_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[27]_i_1_n_6\, + Q => next_mi_addr(25), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\next_mi_addr_reg[26]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[27]_i_1_n_5\, + Q => next_mi_addr(26), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\next_mi_addr_reg[27]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[27]_i_1_n_4\, + Q => next_mi_addr(27), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\next_mi_addr_reg[27]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \next_mi_addr_reg[23]_i_1_n_0\, + CO(3) => \next_mi_addr_reg[27]_i_1_n_0\, + CO(2) => \next_mi_addr_reg[27]_i_1_n_1\, + CO(1) => \next_mi_addr_reg[27]_i_1_n_2\, + CO(0) => \next_mi_addr_reg[27]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \next_mi_addr_reg[27]_i_1_n_4\, + O(2) => \next_mi_addr_reg[27]_i_1_n_5\, + O(1) => \next_mi_addr_reg[27]_i_1_n_6\, + O(0) => \next_mi_addr_reg[27]_i_1_n_7\, + S(3) => \next_mi_addr[27]_i_2_n_0\, + S(2) => \next_mi_addr[27]_i_3_n_0\, + S(1) => \next_mi_addr[27]_i_4_n_0\, + S(0) => \next_mi_addr[27]_i_5_n_0\ + ); +\next_mi_addr_reg[28]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[31]_i_1_n_7\, + Q => next_mi_addr(28), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\next_mi_addr_reg[29]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[31]_i_1_n_6\, + Q => next_mi_addr(29), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\next_mi_addr_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[3]_i_1_n_5\, + Q => next_mi_addr(2), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\next_mi_addr_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[31]_i_1_n_5\, + Q => next_mi_addr(30), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\next_mi_addr_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[31]_i_1_n_4\, + Q => next_mi_addr(31), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\next_mi_addr_reg[31]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \next_mi_addr_reg[27]_i_1_n_0\, + CO(3) => \NLW_next_mi_addr_reg[31]_i_1_CO_UNCONNECTED\(3), + CO(2) => \next_mi_addr_reg[31]_i_1_n_1\, + CO(1) => \next_mi_addr_reg[31]_i_1_n_2\, + CO(0) => \next_mi_addr_reg[31]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \next_mi_addr_reg[31]_i_1_n_4\, + O(2) => \next_mi_addr_reg[31]_i_1_n_5\, + O(1) => \next_mi_addr_reg[31]_i_1_n_6\, + O(0) => \next_mi_addr_reg[31]_i_1_n_7\, + S(3) => \next_mi_addr[31]_i_2_n_0\, + S(2) => \next_mi_addr[31]_i_3_n_0\, + S(1) => \next_mi_addr[31]_i_4_n_0\, + S(0) => \next_mi_addr[31]_i_5_n_0\ + ); +\next_mi_addr_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[3]_i_1_n_4\, + Q => next_mi_addr(3), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\next_mi_addr_reg[3]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \next_mi_addr_reg[3]_i_1_n_0\, + CO(2) => \next_mi_addr_reg[3]_i_1_n_1\, + CO(1) => \next_mi_addr_reg[3]_i_1_n_2\, + CO(0) => \next_mi_addr_reg[3]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => \^m_axi_awaddr\(3 downto 0), + O(3) => \next_mi_addr_reg[3]_i_1_n_4\, + O(2) => \next_mi_addr_reg[3]_i_1_n_5\, + O(1) => \next_mi_addr_reg[3]_i_1_n_6\, + O(0) => \next_mi_addr_reg[3]_i_1_n_7\, + S(3) => \next_mi_addr[3]_i_2_n_0\, + S(2) => \next_mi_addr[3]_i_3_n_0\, + S(1) => \next_mi_addr[3]_i_4_n_0\, + S(0) => \next_mi_addr[3]_i_5_n_0\ + ); +\next_mi_addr_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[7]_i_1_n_7\, + Q => next_mi_addr(4), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\next_mi_addr_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[7]_i_1_n_6\, + Q => next_mi_addr(5), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\next_mi_addr_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[7]_i_1_n_5\, + Q => next_mi_addr(6), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\next_mi_addr_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[7]_i_1_n_4\, + Q => next_mi_addr(7), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\next_mi_addr_reg[7]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \next_mi_addr_reg[3]_i_1_n_0\, + CO(3) => \next_mi_addr_reg[7]_i_1_n_0\, + CO(2) => \next_mi_addr_reg[7]_i_1_n_1\, + CO(1) => \next_mi_addr_reg[7]_i_1_n_2\, + CO(0) => \next_mi_addr_reg[7]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => \^m_axi_awaddr\(7 downto 4), + O(3) => \next_mi_addr_reg[7]_i_1_n_4\, + O(2) => \next_mi_addr_reg[7]_i_1_n_5\, + O(1) => \next_mi_addr_reg[7]_i_1_n_6\, + O(0) => \next_mi_addr_reg[7]_i_1_n_7\, + S(3) => \next_mi_addr[7]_i_2_n_0\, + S(2) => \next_mi_addr[7]_i_3_n_0\, + S(1) => \next_mi_addr[7]_i_4_n_0\, + S(0) => \next_mi_addr[7]_i_5_n_0\ + ); +\next_mi_addr_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[11]_i_1_n_7\, + Q => next_mi_addr(8), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\next_mi_addr_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \next_mi_addr_reg[11]_i_1_n_6\, + Q => next_mi_addr(9), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\num_transactions_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awlen(4), + Q => num_transactions_q(0), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\num_transactions_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awlen(5), + Q => num_transactions_q(1), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\num_transactions_q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awlen(6), + Q => num_transactions_q(2), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\num_transactions_q_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => s_axi_awlen(7), + Q => num_transactions_q(3), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\pushed_commands[0]_i_1\: unisim.vcomponents.LUT1 generic map( - INIT => X"4000" - ) - port map ( - I0 => empty, - I1 => m_axi_rvalid, - I2 => s_axi_rready, - I3 => m_axi_rlast, - O => \^rd_en\ + INIT => X"1" + ) + port map ( + I0 => \pushed_commands_reg__0\(0), + O => p_0_in(0) ); -m_axi_arvalid_INST_0: unisim.vcomponents.LUT4 +\pushed_commands[1]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"AA02" + INIT => X"6" ) port map ( - I0 => command_ongoing, - I1 => full, - I2 => m_axi_arvalid_INST_0_i_1_n_0, - I3 => cmd_push_block, - O => m_axi_arvalid + I0 => \pushed_commands_reg__0\(0), + I1 => \pushed_commands_reg__0\(1), + O => p_0_in(1) ); -m_axi_arvalid_INST_0_i_1: unisim.vcomponents.LUT6 +\pushed_commands[2]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"ABBA0330ABBA0000" + INIT => X"78" ) port map ( - I0 => multiple_id_non_split, - I1 => cmd_empty, - I2 => \S_AXI_AID_Q_reg[0]\, - I3 => queue_id, - I4 => need_to_split_q, - I5 => split_in_progress_reg_0, - O => m_axi_arvalid_INST_0_i_1_n_0 + I0 => \pushed_commands_reg__0\(0), + I1 => \pushed_commands_reg__0\(1), + I2 => \pushed_commands_reg__0\(2), + O => p_0_in(2) ); -m_axi_rready_INST_0: unisim.vcomponents.LUT3 +\pushed_commands[3]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"0D" + INIT => X"B" ) port map ( - I0 => m_axi_rvalid, - I1 => s_axi_rready, - I2 => empty, - O => m_axi_rready + I0 => \^e\(0), + I1 => aresetn, + O => \pushed_commands[3]_i_1_n_0\ ); -multiple_id_non_split_i_1: unisim.vcomponents.LUT6 +\pushed_commands[3]_i_2\: unisim.vcomponents.LUT4 generic map( - INIT => X"00000000AAAAAEAA" + INIT => X"7F80" ) port map ( - I0 => multiple_id_non_split, - I1 => \S_AXI_AID_Q_reg[0]_0\, - I2 => cmd_push_block, - I3 => command_ongoing, - I4 => full, - I5 => split_in_progress, - O => multiple_id_non_split_reg + I0 => \pushed_commands_reg__0\(1), + I1 => \pushed_commands_reg__0\(0), + I2 => \pushed_commands_reg__0\(2), + I3 => \pushed_commands_reg__0\(3), + O => p_0_in(3) + ); +\pushed_commands_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => p_0_in(0), + Q => \pushed_commands_reg__0\(0), + R => \pushed_commands[3]_i_1_n_0\ + ); +\pushed_commands_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => p_0_in(1), + Q => \pushed_commands_reg__0\(1), + R => \pushed_commands[3]_i_1_n_0\ + ); +\pushed_commands_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => p_0_in(2), + Q => \pushed_commands_reg__0\(2), + R => \pushed_commands[3]_i_1_n_0\ + ); +\pushed_commands_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => p_0_in(3), + Q => \pushed_commands_reg__0\(3), + R => \pushed_commands[3]_i_1_n_0\ + ); +\queue_id_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \USE_BURSTS.cmd_queue_n_21\, + Q => queue_id, + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ ); -multiple_id_non_split_i_3: unisim.vcomponents.LUT4 +\size_mask_q[0]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"FF8F" + INIT => X"01" ) port map ( - I0 => almost_empty, - I1 => \^rd_en\, - I2 => aresetn, - I3 => cmd_empty, - O => split_in_progress + I0 => s_axi_awsize(2), + I1 => s_axi_awsize(0), + I2 => s_axi_awsize(1), + O => size_mask(0) ); -\queue_id[0]_i_1\: unisim.vcomponents.LUT3 +\size_mask_q[1]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"B8" + INIT => X"1" ) port map ( - I0 => \S_AXI_AID_Q_reg[0]\, - I1 => \^wr_en\, - I2 => queue_id, - O => \queue_id_reg[0]\ + I0 => s_axi_awsize(2), + I1 => s_axi_awsize(1), + O => size_mask(1) ); -s_axi_rlast_INST_0: unisim.vcomponents.LUT2 +\size_mask_q[2]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"2" + INIT => X"07" ) port map ( - I0 => m_axi_rlast, - I1 => rd_cmd_split, - O => s_axi_rlast + I0 => s_axi_awsize(0), + I1 => s_axi_awsize(1), + I2 => s_axi_awsize(2), + O => size_mask(2) ); -s_axi_rvalid_INST_0: unisim.vcomponents.LUT2 +\size_mask_q[3]_i_1\: unisim.vcomponents.LUT1 generic map( - INIT => X"2" + INIT => X"1" ) port map ( - I0 => m_axi_rvalid, - I1 => empty, - O => s_axi_rvalid + I0 => s_axi_awsize(2), + O => size_mask(3) ); -split_in_progress_i_1: unisim.vcomponents.LUT6 +\size_mask_q[4]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"00000000AAAAAEAA" + INIT => X"57" ) port map ( - I0 => split_in_progress_reg_0, - I1 => cmd_empty_reg, - I2 => multiple_id_non_split, - I3 => need_to_split_q, - I4 => split_in_progress_i_3_n_0, - I5 => split_in_progress, - O => split_in_progress_reg + I0 => s_axi_awsize(2), + I1 => s_axi_awsize(0), + I2 => s_axi_awsize(1), + O => size_mask(4) ); -split_in_progress_i_3: unisim.vcomponents.LUT3 +\size_mask_q[5]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"FB" + INIT => X"7" ) port map ( - I0 => full, - I1 => command_ongoing, - I2 => cmd_push_block, - O => split_in_progress_i_3_n_0 + I0 => s_axi_awsize(2), + I1 => s_axi_awsize(1), + O => size_mask(5) ); -split_ongoing_i_1: unisim.vcomponents.LUT5 +\size_mask_q[6]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"F1000000" + INIT => X"7F" ) port map ( - I0 => full, - I1 => m_axi_arvalid_INST_0_i_1_n_0, - I2 => cmd_push_block, - I3 => command_ongoing, - I4 => m_axi_arready, - O => \^pushed_commands_reg[0]\ + I0 => s_axi_awsize(2), + I1 => s_axi_awsize(0), + I2 => s_axi_awsize(1), + O => size_mask(6) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_axic_fifo is - port ( - SR : out STD_LOGIC_VECTOR ( 0 to 0 ); - din : out STD_LOGIC_VECTOR ( 0 to 0 ); - cmd_push : out STD_LOGIC; - rd_cmd_ready : out STD_LOGIC; - D : out STD_LOGIC_VECTOR ( 4 downto 0 ); - cmd_empty0 : out STD_LOGIC; - pushed_new_cmd : out STD_LOGIC; - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_arvalid : out STD_LOGIC; - s_axi_rvalid : out STD_LOGIC; - s_axi_rlast : out STD_LOGIC; - m_axi_rready : out STD_LOGIC; - S_AXI_AREADY_I_reg : out STD_LOGIC; - cmd_push_block_reg : out STD_LOGIC; - \queue_id_reg[0]\ : out STD_LOGIC; - command_ongoing_reg : out STD_LOGIC; - multiple_id_non_split_reg : out STD_LOGIC; - split_in_progress_reg : out STD_LOGIC; - aclk : in STD_LOGIC; - Q : in STD_LOGIC_VECTOR ( 5 downto 0 ); - need_to_split_q : in STD_LOGIC; - cmd_push_block : in STD_LOGIC; - command_ongoing : in STD_LOGIC; - m_axi_arready : in STD_LOGIC; - \cmd_depth_reg[3]\ : in STD_LOGIC; - \cmd_depth_reg[1]\ : in STD_LOGIC; - m_axi_rlast : in STD_LOGIC; - s_axi_rready : in STD_LOGIC; - m_axi_rvalid : in STD_LOGIC; - multiple_id_non_split : in STD_LOGIC; - cmd_empty : in STD_LOGIC; - \S_AXI_AID_Q_reg[0]\ : in STD_LOGIC; - queue_id : in STD_LOGIC; - split_in_progress_reg_0 : in STD_LOGIC; - aresetn : in STD_LOGIC; - almost_empty : in STD_LOGIC; - access_is_incr_q : in STD_LOGIC; - num_transactions_q : in STD_LOGIC_VECTOR ( 3 downto 0 ); - \pushed_commands_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); - \areset_d_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); - S_AXI_AREADY_I_reg_0 : in STD_LOGIC; - s_axi_arvalid : in STD_LOGIC; - \areset_d_reg[1]_0\ : in STD_LOGIC; - \S_AXI_AID_Q_reg[0]_0\ : in STD_LOGIC; - cmd_empty_reg : in STD_LOGIC - ); -end Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_axic_fifo; - -architecture STRUCTURE of Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_axic_fifo is -begin -inst: entity work.Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_fifo_gen +\size_mask_q_reg[0]\: unisim.vcomponents.FDRE port map ( - D(4 downto 0) => D(4 downto 0), - E(0) => E(0), - Q(5 downto 0) => Q(5 downto 0), - SR(0) => SR(0), - \S_AXI_AID_Q_reg[0]\ => \S_AXI_AID_Q_reg[0]\, - \S_AXI_AID_Q_reg[0]_0\ => \S_AXI_AID_Q_reg[0]_0\, - S_AXI_AREADY_I_reg => S_AXI_AREADY_I_reg, - S_AXI_AREADY_I_reg_0 => S_AXI_AREADY_I_reg_0, - access_is_incr_q => access_is_incr_q, - aclk => aclk, - almost_empty => almost_empty, - \areset_d_reg[1]\(1 downto 0) => \areset_d_reg[1]\(1 downto 0), - \areset_d_reg[1]_0\ => \areset_d_reg[1]_0\, - aresetn => aresetn, - \cmd_depth_reg[1]\ => cmd_empty0, - \cmd_depth_reg[1]_0\ => \cmd_depth_reg[1]\, - \cmd_depth_reg[3]\ => \cmd_depth_reg[3]\, - cmd_empty => cmd_empty, - cmd_empty_reg => cmd_empty_reg, - cmd_push_block => cmd_push_block, - cmd_push_block_reg => cmd_push_block_reg, - command_ongoing => command_ongoing, - command_ongoing_reg => command_ongoing_reg, - din(0) => din(0), - m_axi_arready => m_axi_arready, - m_axi_arvalid => m_axi_arvalid, - m_axi_rlast => m_axi_rlast, - m_axi_rready => m_axi_rready, - m_axi_rvalid => m_axi_rvalid, - multiple_id_non_split => multiple_id_non_split, - multiple_id_non_split_reg => multiple_id_non_split_reg, - need_to_split_q => need_to_split_q, - num_transactions_q(3 downto 0) => num_transactions_q(3 downto 0), - \pushed_commands_reg[0]\ => pushed_new_cmd, - \pushed_commands_reg[3]\(3 downto 0) => \pushed_commands_reg[3]\(3 downto 0), - queue_id => queue_id, - \queue_id_reg[0]\ => \queue_id_reg[0]\, - rd_en => rd_cmd_ready, - s_axi_arvalid => s_axi_arvalid, - s_axi_rlast => s_axi_rlast, - s_axi_rready => s_axi_rready, - s_axi_rvalid => s_axi_rvalid, - split_in_progress_reg => split_in_progress_reg, - split_in_progress_reg_0 => split_in_progress_reg_0, - wr_en => cmd_push + C => aclk, + CE => \^e\(0), + D => size_mask(0), + Q => size_mask_q(0), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\size_mask_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => size_mask(1), + Q => size_mask_q(1), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\size_mask_q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => size_mask(2), + Q => size_mask_q(2), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\size_mask_q_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => '1', + Q => size_mask_q(31), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\size_mask_q_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => size_mask(3), + Q => size_mask_q(3), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\size_mask_q_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => size_mask(4), + Q => size_mask_q(4), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\size_mask_q_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => size_mask(5), + Q => size_mask_q(5), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +\size_mask_q_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => size_mask(6), + Q => size_mask_q(6), + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ + ); +split_in_progress_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \USE_BURSTS.cmd_queue_n_22\, + Q => split_in_progress_reg_n_0, + R => '0' + ); +split_ongoing_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => pushed_new_cmd, + D => \USE_B_CHANNEL.cmd_b_queue_n_6\, + Q => split_ongoing, + R => \^ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_a_axi3_conv is +entity \Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_a_axi3_conv__parameterized0\ is port ( E : out STD_LOGIC_VECTOR ( 0 to 0 ); - M_AXI_ARID : out STD_LOGIC_VECTOR ( 0 to 0 ); + \m_axi_arid[0]\ : out STD_LOGIC; + m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_rready : out STD_LOGIC; + s_axi_rvalid : out STD_LOGIC; + m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rlast : out STD_LOGIC; + m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_arvalid : out STD_LOGIC; m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); - m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); - m_axi_arvalid : out STD_LOGIC; - s_axi_rvalid : out STD_LOGIC; - m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); - m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_rlast : out STD_LOGIC; - m_axi_rready : out STD_LOGIC; - s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); - s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); aclk : in STD_LOGIC; + aresetn_0 : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + aresetn : in STD_LOGIC; + s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_rvalid : in STD_LOGIC; + s_axi_rready : in STD_LOGIC; + m_axi_rlast : in STD_LOGIC; + m_axi_arready : in STD_LOGIC; + s_axi_arvalid : in STD_LOGIC; + areset_d : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \areset_d_reg[1]\ : in STD_LOGIC; s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); - s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); - m_axi_arready : in STD_LOGIC; - m_axi_rlast : in STD_LOGIC; - s_axi_rready : in STD_LOGIC; - m_axi_rvalid : in STD_LOGIC; - aresetn : in STD_LOGIC; - s_axi_arvalid : in STD_LOGIC + s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ) ); -end Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_a_axi3_conv; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_a_axi3_conv__parameterized0\ : entity is "axi_protocol_converter_v2_1_11_a_axi3_conv"; +end \Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_a_axi3_conv__parameterized0\; -architecture STRUCTURE of Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_a_axi3_conv is +architecture STRUCTURE of \Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_a_axi3_conv__parameterized0\ is signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \^m_axi_arid\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal S_AXI_AADDR_Q : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \M_AXI_AADDR_I1__0\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[0]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[10]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[11]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[12]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[13]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[14]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[15]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[16]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[17]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[18]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[19]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[1]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[20]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[21]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[22]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[23]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[24]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[25]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[26]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[27]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[28]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[29]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[2]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[30]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[31]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[3]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[4]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[5]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[6]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[7]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[8]\ : STD_LOGIC; + signal \S_AXI_AADDR_Q_reg_n_0_[9]\ : STD_LOGIC; signal S_AXI_ALEN_Q : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \S_AXI_ALOCK_Q_reg_n_0_[0]\ : STD_LOGIC; + signal \S_AXI_AREADY_I_i_2__0_n_0\ : STD_LOGIC; signal \USE_R_CHANNEL.cmd_queue_n_0\ : STD_LOGIC; signal \USE_R_CHANNEL.cmd_queue_n_1\ : STD_LOGIC; - signal \USE_R_CHANNEL.cmd_queue_n_11\ : STD_LOGIC; + signal \USE_R_CHANNEL.cmd_queue_n_13\ : STD_LOGIC; + signal \USE_R_CHANNEL.cmd_queue_n_14\ : STD_LOGIC; signal \USE_R_CHANNEL.cmd_queue_n_16\ : STD_LOGIC; signal \USE_R_CHANNEL.cmd_queue_n_17\ : STD_LOGIC; signal \USE_R_CHANNEL.cmd_queue_n_18\ : STD_LOGIC; signal \USE_R_CHANNEL.cmd_queue_n_19\ : STD_LOGIC; signal \USE_R_CHANNEL.cmd_queue_n_20\ : STD_LOGIC; - signal \USE_R_CHANNEL.cmd_queue_n_21\ : STD_LOGIC; + signal \USE_R_CHANNEL.cmd_queue_n_3\ : STD_LOGIC; signal \USE_R_CHANNEL.cmd_queue_n_4\ : STD_LOGIC; signal \USE_R_CHANNEL.cmd_queue_n_5\ : STD_LOGIC; signal \USE_R_CHANNEL.cmd_queue_n_6\ : STD_LOGIC; @@ -4400,447 +16632,469 @@ architecture STRUCTURE of Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_a_ signal \USE_R_CHANNEL.cmd_queue_n_8\ : STD_LOGIC; signal access_is_incr : STD_LOGIC; signal access_is_incr_q : STD_LOGIC; - signal addr_step : STD_LOGIC_VECTOR ( 11 downto 5 ); - signal addr_step_q : STD_LOGIC_VECTOR ( 11 downto 5 ); + signal \addr_step_q[10]_i_1__0_n_0\ : STD_LOGIC; + signal \addr_step_q[11]_i_1__0_n_0\ : STD_LOGIC; + signal \addr_step_q[5]_i_1__0_n_0\ : STD_LOGIC; + signal \addr_step_q[6]_i_1__0_n_0\ : STD_LOGIC; + signal \addr_step_q[7]_i_1__0_n_0\ : STD_LOGIC; + signal \addr_step_q[8]_i_1__0_n_0\ : STD_LOGIC; + signal \addr_step_q[9]_i_1__0_n_0\ : STD_LOGIC; + signal \addr_step_q_reg_n_0_[10]\ : STD_LOGIC; + signal \addr_step_q_reg_n_0_[11]\ : STD_LOGIC; + signal \addr_step_q_reg_n_0_[5]\ : STD_LOGIC; + signal \addr_step_q_reg_n_0_[6]\ : STD_LOGIC; + signal \addr_step_q_reg_n_0_[7]\ : STD_LOGIC; + signal \addr_step_q_reg_n_0_[8]\ : STD_LOGIC; + signal \addr_step_q_reg_n_0_[9]\ : STD_LOGIC; + signal \allow_split_cmd__1\ : STD_LOGIC; signal almost_empty : STD_LOGIC; - signal areset_d : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal \cmd_depth[0]_i_1_n_0\ : STD_LOGIC; - signal \cmd_depth[5]_i_3_n_0\ : STD_LOGIC; - signal \cmd_depth[5]_i_4_n_0\ : STD_LOGIC; + signal \cmd_depth[0]_i_1__0_n_0\ : STD_LOGIC; signal \cmd_depth_reg__0\ : STD_LOGIC_VECTOR ( 5 downto 0 ); signal cmd_empty : STD_LOGIC; - signal cmd_empty0 : STD_LOGIC; signal cmd_empty_i_1_n_0 : STD_LOGIC; - signal cmd_push : STD_LOGIC; signal cmd_push_block : STD_LOGIC; signal command_ongoing : STD_LOGIC; - signal command_ongoing_i_2_n_0 : STD_LOGIC; + signal \first_split__2\ : STD_LOGIC; signal first_step : STD_LOGIC_VECTOR ( 11 downto 4 ); - signal first_step_q : STD_LOGIC_VECTOR ( 11 downto 0 ); - signal \first_step_q[0]_i_1_n_0\ : STD_LOGIC; - signal \first_step_q[10]_i_2_n_0\ : STD_LOGIC; - signal \first_step_q[11]_i_2_n_0\ : STD_LOGIC; - signal \first_step_q[1]_i_1_n_0\ : STD_LOGIC; - signal \first_step_q[2]_i_1_n_0\ : STD_LOGIC; - signal \first_step_q[3]_i_1_n_0\ : STD_LOGIC; - signal \first_step_q[6]_i_2_n_0\ : STD_LOGIC; - signal \first_step_q[7]_i_2_n_0\ : STD_LOGIC; - signal \first_step_q[8]_i_2_n_0\ : STD_LOGIC; - signal \first_step_q[9]_i_2_n_0\ : STD_LOGIC; + signal \first_step_q[0]_i_1__0_n_0\ : STD_LOGIC; + signal \first_step_q[10]_i_2__0_n_0\ : STD_LOGIC; + signal \first_step_q[11]_i_2__0_n_0\ : STD_LOGIC; + signal \first_step_q[1]_i_1__0_n_0\ : STD_LOGIC; + signal \first_step_q[2]_i_1__0_n_0\ : STD_LOGIC; + signal \first_step_q[3]_i_1__0_n_0\ : STD_LOGIC; + signal \first_step_q[6]_i_2__0_n_0\ : STD_LOGIC; + signal \first_step_q[7]_i_2__0_n_0\ : STD_LOGIC; + signal \first_step_q[8]_i_2__0_n_0\ : STD_LOGIC; + signal \first_step_q[9]_i_2__0_n_0\ : STD_LOGIC; + signal \first_step_q_reg_n_0_[0]\ : STD_LOGIC; + signal \first_step_q_reg_n_0_[10]\ : STD_LOGIC; + signal \first_step_q_reg_n_0_[11]\ : STD_LOGIC; + signal \first_step_q_reg_n_0_[1]\ : STD_LOGIC; + signal \first_step_q_reg_n_0_[2]\ : STD_LOGIC; + signal \first_step_q_reg_n_0_[3]\ : STD_LOGIC; + signal \first_step_q_reg_n_0_[4]\ : STD_LOGIC; + signal \first_step_q_reg_n_0_[5]\ : STD_LOGIC; + signal \first_step_q_reg_n_0_[6]\ : STD_LOGIC; + signal \first_step_q_reg_n_0_[7]\ : STD_LOGIC; + signal \first_step_q_reg_n_0_[8]\ : STD_LOGIC; + signal \first_step_q_reg_n_0_[9]\ : STD_LOGIC; signal \incr_need_to_split__0\ : STD_LOGIC; signal \^m_axi_araddr\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \^m_axi_arid[0]\ : STD_LOGIC; signal multiple_id_non_split : STD_LOGIC; - signal multiple_id_non_split_i_2_n_0 : STD_LOGIC; + signal \multiple_id_non_split_i_2__0_n_0\ : STD_LOGIC; signal need_to_split_q : STD_LOGIC; signal next_mi_addr : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \next_mi_addr[11]_i_2_n_0\ : STD_LOGIC; signal \next_mi_addr[11]_i_3_n_0\ : STD_LOGIC; signal \next_mi_addr[11]_i_4_n_0\ : STD_LOGIC; signal \next_mi_addr[11]_i_5_n_0\ : STD_LOGIC; - signal \next_mi_addr[11]_i_6_n_0\ : STD_LOGIC; - signal \next_mi_addr[15]_i_2_n_0\ : STD_LOGIC; - signal \next_mi_addr[15]_i_3_n_0\ : STD_LOGIC; - signal \next_mi_addr[15]_i_4_n_0\ : STD_LOGIC; - signal \next_mi_addr[15]_i_5_n_0\ : STD_LOGIC; - signal \next_mi_addr[15]_i_6_n_0\ : STD_LOGIC; - signal \next_mi_addr[15]_i_7_n_0\ : STD_LOGIC; - signal \next_mi_addr[15]_i_8_n_0\ : STD_LOGIC; - signal \next_mi_addr[15]_i_9_n_0\ : STD_LOGIC; - signal \next_mi_addr[19]_i_2_n_0\ : STD_LOGIC; - signal \next_mi_addr[19]_i_3_n_0\ : STD_LOGIC; - signal \next_mi_addr[19]_i_4_n_0\ : STD_LOGIC; - signal \next_mi_addr[19]_i_5_n_0\ : STD_LOGIC; - signal \next_mi_addr[23]_i_2_n_0\ : STD_LOGIC; - signal \next_mi_addr[23]_i_3_n_0\ : STD_LOGIC; - signal \next_mi_addr[23]_i_4_n_0\ : STD_LOGIC; - signal \next_mi_addr[23]_i_5_n_0\ : STD_LOGIC; - signal \next_mi_addr[27]_i_2_n_0\ : STD_LOGIC; - signal \next_mi_addr[27]_i_3_n_0\ : STD_LOGIC; - signal \next_mi_addr[27]_i_4_n_0\ : STD_LOGIC; - signal \next_mi_addr[27]_i_5_n_0\ : STD_LOGIC; - signal \next_mi_addr[31]_i_2_n_0\ : STD_LOGIC; - signal \next_mi_addr[31]_i_3_n_0\ : STD_LOGIC; - signal \next_mi_addr[31]_i_4_n_0\ : STD_LOGIC; - signal \next_mi_addr[31]_i_5_n_0\ : STD_LOGIC; - signal \next_mi_addr[3]_i_2_n_0\ : STD_LOGIC; - signal \next_mi_addr[3]_i_3_n_0\ : STD_LOGIC; - signal \next_mi_addr[3]_i_4_n_0\ : STD_LOGIC; - signal \next_mi_addr[3]_i_5_n_0\ : STD_LOGIC; - signal \next_mi_addr[3]_i_6_n_0\ : STD_LOGIC; + signal \next_mi_addr[15]_i_2__0_n_0\ : STD_LOGIC; + signal \next_mi_addr[15]_i_3__0_n_0\ : STD_LOGIC; + signal \next_mi_addr[15]_i_4__0_n_0\ : STD_LOGIC; + signal \next_mi_addr[15]_i_5__0_n_0\ : STD_LOGIC; + signal \next_mi_addr[15]_i_6__0_n_0\ : STD_LOGIC; + signal \next_mi_addr[15]_i_7__0_n_0\ : STD_LOGIC; + signal \next_mi_addr[15]_i_8__0_n_0\ : STD_LOGIC; + signal \next_mi_addr[15]_i_9__0_n_0\ : STD_LOGIC; + signal \next_mi_addr[19]_i_2__0_n_0\ : STD_LOGIC; + signal \next_mi_addr[19]_i_3__0_n_0\ : STD_LOGIC; + signal \next_mi_addr[19]_i_4__0_n_0\ : STD_LOGIC; + signal \next_mi_addr[19]_i_5__0_n_0\ : STD_LOGIC; + signal \next_mi_addr[23]_i_2__0_n_0\ : STD_LOGIC; + signal \next_mi_addr[23]_i_3__0_n_0\ : STD_LOGIC; + signal \next_mi_addr[23]_i_4__0_n_0\ : STD_LOGIC; + signal \next_mi_addr[23]_i_5__0_n_0\ : STD_LOGIC; + signal \next_mi_addr[27]_i_2__0_n_0\ : STD_LOGIC; + signal \next_mi_addr[27]_i_3__0_n_0\ : STD_LOGIC; + signal \next_mi_addr[27]_i_4__0_n_0\ : STD_LOGIC; + signal \next_mi_addr[27]_i_5__0_n_0\ : STD_LOGIC; + signal \next_mi_addr[31]_i_2__0_n_0\ : STD_LOGIC; + signal \next_mi_addr[31]_i_3__0_n_0\ : STD_LOGIC; + signal \next_mi_addr[31]_i_4__0_n_0\ : STD_LOGIC; + signal \next_mi_addr[31]_i_5__0_n_0\ : STD_LOGIC; + signal \next_mi_addr[3]_i_2__0_n_0\ : STD_LOGIC; + signal \next_mi_addr[3]_i_3__0_n_0\ : STD_LOGIC; + signal \next_mi_addr[3]_i_4__0_n_0\ : STD_LOGIC; + signal \next_mi_addr[3]_i_5__0_n_0\ : STD_LOGIC; signal \next_mi_addr[7]_i_2_n_0\ : STD_LOGIC; signal \next_mi_addr[7]_i_3_n_0\ : STD_LOGIC; signal \next_mi_addr[7]_i_4_n_0\ : STD_LOGIC; signal \next_mi_addr[7]_i_5_n_0\ : STD_LOGIC; - signal \next_mi_addr_reg[11]_i_1_n_0\ : STD_LOGIC; - signal \next_mi_addr_reg[11]_i_1_n_1\ : STD_LOGIC; - signal \next_mi_addr_reg[11]_i_1_n_2\ : STD_LOGIC; - signal \next_mi_addr_reg[11]_i_1_n_3\ : STD_LOGIC; - signal \next_mi_addr_reg[11]_i_1_n_4\ : STD_LOGIC; - signal \next_mi_addr_reg[11]_i_1_n_5\ : STD_LOGIC; - signal \next_mi_addr_reg[11]_i_1_n_6\ : STD_LOGIC; - signal \next_mi_addr_reg[11]_i_1_n_7\ : STD_LOGIC; - signal \next_mi_addr_reg[15]_i_1_n_0\ : STD_LOGIC; - signal \next_mi_addr_reg[15]_i_1_n_1\ : STD_LOGIC; - signal \next_mi_addr_reg[15]_i_1_n_2\ : STD_LOGIC; - signal \next_mi_addr_reg[15]_i_1_n_3\ : STD_LOGIC; - signal \next_mi_addr_reg[15]_i_1_n_4\ : STD_LOGIC; - signal \next_mi_addr_reg[15]_i_1_n_5\ : STD_LOGIC; - signal \next_mi_addr_reg[15]_i_1_n_6\ : STD_LOGIC; - signal \next_mi_addr_reg[15]_i_1_n_7\ : STD_LOGIC; - signal \next_mi_addr_reg[19]_i_1_n_0\ : STD_LOGIC; - signal \next_mi_addr_reg[19]_i_1_n_1\ : STD_LOGIC; - signal \next_mi_addr_reg[19]_i_1_n_2\ : STD_LOGIC; - signal \next_mi_addr_reg[19]_i_1_n_3\ : STD_LOGIC; - signal \next_mi_addr_reg[19]_i_1_n_4\ : STD_LOGIC; - signal \next_mi_addr_reg[19]_i_1_n_5\ : STD_LOGIC; - signal \next_mi_addr_reg[19]_i_1_n_6\ : STD_LOGIC; - signal \next_mi_addr_reg[19]_i_1_n_7\ : STD_LOGIC; - signal \next_mi_addr_reg[23]_i_1_n_0\ : STD_LOGIC; - signal \next_mi_addr_reg[23]_i_1_n_1\ : STD_LOGIC; - signal \next_mi_addr_reg[23]_i_1_n_2\ : STD_LOGIC; - signal \next_mi_addr_reg[23]_i_1_n_3\ : STD_LOGIC; - signal \next_mi_addr_reg[23]_i_1_n_4\ : STD_LOGIC; - signal \next_mi_addr_reg[23]_i_1_n_5\ : STD_LOGIC; - signal \next_mi_addr_reg[23]_i_1_n_6\ : STD_LOGIC; - signal \next_mi_addr_reg[23]_i_1_n_7\ : STD_LOGIC; - signal \next_mi_addr_reg[27]_i_1_n_0\ : STD_LOGIC; - signal \next_mi_addr_reg[27]_i_1_n_1\ : STD_LOGIC; - signal \next_mi_addr_reg[27]_i_1_n_2\ : STD_LOGIC; - signal \next_mi_addr_reg[27]_i_1_n_3\ : STD_LOGIC; - signal \next_mi_addr_reg[27]_i_1_n_4\ : STD_LOGIC; - signal \next_mi_addr_reg[27]_i_1_n_5\ : STD_LOGIC; - signal \next_mi_addr_reg[27]_i_1_n_6\ : STD_LOGIC; - signal \next_mi_addr_reg[27]_i_1_n_7\ : STD_LOGIC; - signal \next_mi_addr_reg[31]_i_1_n_1\ : STD_LOGIC; - signal \next_mi_addr_reg[31]_i_1_n_2\ : STD_LOGIC; - signal \next_mi_addr_reg[31]_i_1_n_3\ : STD_LOGIC; - signal \next_mi_addr_reg[31]_i_1_n_4\ : STD_LOGIC; - signal \next_mi_addr_reg[31]_i_1_n_5\ : STD_LOGIC; - signal \next_mi_addr_reg[31]_i_1_n_6\ : STD_LOGIC; - signal \next_mi_addr_reg[31]_i_1_n_7\ : STD_LOGIC; - signal \next_mi_addr_reg[3]_i_1_n_0\ : STD_LOGIC; - signal \next_mi_addr_reg[3]_i_1_n_1\ : STD_LOGIC; - signal \next_mi_addr_reg[3]_i_1_n_2\ : STD_LOGIC; - signal \next_mi_addr_reg[3]_i_1_n_3\ : STD_LOGIC; - signal \next_mi_addr_reg[3]_i_1_n_4\ : STD_LOGIC; - signal \next_mi_addr_reg[3]_i_1_n_5\ : STD_LOGIC; - signal \next_mi_addr_reg[3]_i_1_n_6\ : STD_LOGIC; - signal \next_mi_addr_reg[3]_i_1_n_7\ : STD_LOGIC; - signal \next_mi_addr_reg[7]_i_1_n_0\ : STD_LOGIC; - signal \next_mi_addr_reg[7]_i_1_n_1\ : STD_LOGIC; - signal \next_mi_addr_reg[7]_i_1_n_2\ : STD_LOGIC; - signal \next_mi_addr_reg[7]_i_1_n_3\ : STD_LOGIC; - signal \next_mi_addr_reg[7]_i_1_n_4\ : STD_LOGIC; - signal \next_mi_addr_reg[7]_i_1_n_5\ : STD_LOGIC; - signal \next_mi_addr_reg[7]_i_1_n_6\ : STD_LOGIC; - signal \next_mi_addr_reg[7]_i_1_n_7\ : STD_LOGIC; - signal num_transactions_q : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal p_0_in : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal \pushed_commands[3]_i_1_n_0\ : STD_LOGIC; + signal \next_mi_addr_reg[11]_i_1__0_n_0\ : STD_LOGIC; + signal \next_mi_addr_reg[11]_i_1__0_n_1\ : STD_LOGIC; + signal \next_mi_addr_reg[11]_i_1__0_n_2\ : STD_LOGIC; + signal \next_mi_addr_reg[11]_i_1__0_n_3\ : STD_LOGIC; + signal \next_mi_addr_reg[11]_i_1__0_n_4\ : STD_LOGIC; + signal \next_mi_addr_reg[11]_i_1__0_n_5\ : STD_LOGIC; + signal \next_mi_addr_reg[11]_i_1__0_n_6\ : STD_LOGIC; + signal \next_mi_addr_reg[11]_i_1__0_n_7\ : STD_LOGIC; + signal \next_mi_addr_reg[15]_i_1__0_n_0\ : STD_LOGIC; + signal \next_mi_addr_reg[15]_i_1__0_n_1\ : STD_LOGIC; + signal \next_mi_addr_reg[15]_i_1__0_n_2\ : STD_LOGIC; + signal \next_mi_addr_reg[15]_i_1__0_n_3\ : STD_LOGIC; + signal \next_mi_addr_reg[15]_i_1__0_n_4\ : STD_LOGIC; + signal \next_mi_addr_reg[15]_i_1__0_n_5\ : STD_LOGIC; + signal \next_mi_addr_reg[15]_i_1__0_n_6\ : STD_LOGIC; + signal \next_mi_addr_reg[15]_i_1__0_n_7\ : STD_LOGIC; + signal \next_mi_addr_reg[19]_i_1__0_n_0\ : STD_LOGIC; + signal \next_mi_addr_reg[19]_i_1__0_n_1\ : STD_LOGIC; + signal \next_mi_addr_reg[19]_i_1__0_n_2\ : STD_LOGIC; + signal \next_mi_addr_reg[19]_i_1__0_n_3\ : STD_LOGIC; + signal \next_mi_addr_reg[19]_i_1__0_n_4\ : STD_LOGIC; + signal \next_mi_addr_reg[19]_i_1__0_n_5\ : STD_LOGIC; + signal \next_mi_addr_reg[19]_i_1__0_n_6\ : STD_LOGIC; + signal \next_mi_addr_reg[19]_i_1__0_n_7\ : STD_LOGIC; + signal \next_mi_addr_reg[23]_i_1__0_n_0\ : STD_LOGIC; + signal \next_mi_addr_reg[23]_i_1__0_n_1\ : STD_LOGIC; + signal \next_mi_addr_reg[23]_i_1__0_n_2\ : STD_LOGIC; + signal \next_mi_addr_reg[23]_i_1__0_n_3\ : STD_LOGIC; + signal \next_mi_addr_reg[23]_i_1__0_n_4\ : STD_LOGIC; + signal \next_mi_addr_reg[23]_i_1__0_n_5\ : STD_LOGIC; + signal \next_mi_addr_reg[23]_i_1__0_n_6\ : STD_LOGIC; + signal \next_mi_addr_reg[23]_i_1__0_n_7\ : STD_LOGIC; + signal \next_mi_addr_reg[27]_i_1__0_n_0\ : STD_LOGIC; + signal \next_mi_addr_reg[27]_i_1__0_n_1\ : STD_LOGIC; + signal \next_mi_addr_reg[27]_i_1__0_n_2\ : STD_LOGIC; + signal \next_mi_addr_reg[27]_i_1__0_n_3\ : STD_LOGIC; + signal \next_mi_addr_reg[27]_i_1__0_n_4\ : STD_LOGIC; + signal \next_mi_addr_reg[27]_i_1__0_n_5\ : STD_LOGIC; + signal \next_mi_addr_reg[27]_i_1__0_n_6\ : STD_LOGIC; + signal \next_mi_addr_reg[27]_i_1__0_n_7\ : STD_LOGIC; + signal \next_mi_addr_reg[31]_i_1__0_n_1\ : STD_LOGIC; + signal \next_mi_addr_reg[31]_i_1__0_n_2\ : STD_LOGIC; + signal \next_mi_addr_reg[31]_i_1__0_n_3\ : STD_LOGIC; + signal \next_mi_addr_reg[31]_i_1__0_n_4\ : STD_LOGIC; + signal \next_mi_addr_reg[31]_i_1__0_n_5\ : STD_LOGIC; + signal \next_mi_addr_reg[31]_i_1__0_n_6\ : STD_LOGIC; + signal \next_mi_addr_reg[31]_i_1__0_n_7\ : STD_LOGIC; + signal \next_mi_addr_reg[3]_i_1__0_n_0\ : STD_LOGIC; + signal \next_mi_addr_reg[3]_i_1__0_n_1\ : STD_LOGIC; + signal \next_mi_addr_reg[3]_i_1__0_n_2\ : STD_LOGIC; + signal \next_mi_addr_reg[3]_i_1__0_n_3\ : STD_LOGIC; + signal \next_mi_addr_reg[3]_i_1__0_n_4\ : STD_LOGIC; + signal \next_mi_addr_reg[3]_i_1__0_n_5\ : STD_LOGIC; + signal \next_mi_addr_reg[3]_i_1__0_n_6\ : STD_LOGIC; + signal \next_mi_addr_reg[3]_i_1__0_n_7\ : STD_LOGIC; + signal \next_mi_addr_reg[7]_i_1__0_n_0\ : STD_LOGIC; + signal \next_mi_addr_reg[7]_i_1__0_n_1\ : STD_LOGIC; + signal \next_mi_addr_reg[7]_i_1__0_n_2\ : STD_LOGIC; + signal \next_mi_addr_reg[7]_i_1__0_n_3\ : STD_LOGIC; + signal \next_mi_addr_reg[7]_i_1__0_n_4\ : STD_LOGIC; + signal \next_mi_addr_reg[7]_i_1__0_n_5\ : STD_LOGIC; + signal \next_mi_addr_reg[7]_i_1__0_n_6\ : STD_LOGIC; + signal \next_mi_addr_reg[7]_i_1__0_n_7\ : STD_LOGIC; + signal \num_transactions_q_reg_n_0_[0]\ : STD_LOGIC; + signal \num_transactions_q_reg_n_0_[1]\ : STD_LOGIC; + signal \num_transactions_q_reg_n_0_[2]\ : STD_LOGIC; + signal \num_transactions_q_reg_n_0_[3]\ : STD_LOGIC; + signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \pushed_commands[3]_i_1__0_n_0\ : STD_LOGIC; signal \pushed_commands_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal pushed_new_cmd : STD_LOGIC; - signal queue_id : STD_LOGIC; + signal \queue_id_reg_n_0_[0]\ : STD_LOGIC; signal rd_cmd_ready : STD_LOGIC; - signal size_mask : STD_LOGIC_VECTOR ( 6 downto 0 ); signal size_mask_q : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal split_in_progress_i_2_n_0 : STD_LOGIC; + signal \size_mask_q[0]_i_1__0_n_0\ : STD_LOGIC; + signal \size_mask_q[1]_i_1__0_n_0\ : STD_LOGIC; + signal \size_mask_q[2]_i_1__0_n_0\ : STD_LOGIC; + signal \size_mask_q[3]_i_1__0_n_0\ : STD_LOGIC; + signal \size_mask_q[4]_i_1__0_n_0\ : STD_LOGIC; + signal \size_mask_q[5]_i_1__0_n_0\ : STD_LOGIC; + signal \size_mask_q[6]_i_1__0_n_0\ : STD_LOGIC; signal split_in_progress_reg_n_0 : STD_LOGIC; signal split_ongoing : STD_LOGIC; - signal \NLW_next_mi_addr_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_next_mi_addr_reg[31]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \addr_step_q[10]_i_1\ : label is "soft_lutpair18"; - attribute SOFT_HLUTNM of \addr_step_q[11]_i_1\ : label is "soft_lutpair15"; - attribute SOFT_HLUTNM of \addr_step_q[5]_i_1\ : label is "soft_lutpair21"; - attribute SOFT_HLUTNM of \addr_step_q[6]_i_1\ : label is "soft_lutpair15"; - attribute SOFT_HLUTNM of \addr_step_q[7]_i_1\ : label is "soft_lutpair21"; - attribute SOFT_HLUTNM of \addr_step_q[8]_i_1\ : label is "soft_lutpair17"; - attribute SOFT_HLUTNM of \addr_step_q[9]_i_1\ : label is "soft_lutpair13"; - attribute SOFT_HLUTNM of \cmd_depth[5]_i_3\ : label is "soft_lutpair19"; - attribute SOFT_HLUTNM of \cmd_depth[5]_i_4\ : label is "soft_lutpair19"; - attribute SOFT_HLUTNM of \first_step_q[0]_i_1\ : label is "soft_lutpair11"; - attribute SOFT_HLUTNM of \first_step_q[10]_i_1\ : label is "soft_lutpair22"; - attribute SOFT_HLUTNM of \first_step_q[11]_i_1\ : label is "soft_lutpair26"; - attribute SOFT_HLUTNM of \first_step_q[1]_i_1\ : label is "soft_lutpair11"; - attribute SOFT_HLUTNM of \first_step_q[3]_i_1\ : label is "soft_lutpair23"; - attribute SOFT_HLUTNM of \first_step_q[4]_i_1\ : label is "soft_lutpair13"; - attribute SOFT_HLUTNM of \first_step_q[6]_i_1\ : label is "soft_lutpair22"; - attribute SOFT_HLUTNM of \first_step_q[7]_i_1\ : label is "soft_lutpair23"; - attribute SOFT_HLUTNM of \first_step_q[8]_i_1\ : label is "soft_lutpair25"; - attribute SOFT_HLUTNM of \first_step_q[9]_i_1\ : label is "soft_lutpair26"; - attribute SOFT_HLUTNM of \m_axi_araddr[25]_INST_0\ : label is "soft_lutpair12"; - attribute SOFT_HLUTNM of multiple_id_non_split_i_2 : label is "soft_lutpair10"; - attribute SOFT_HLUTNM of \next_mi_addr[11]_i_6\ : label is "soft_lutpair14"; - attribute SOFT_HLUTNM of \next_mi_addr[3]_i_6\ : label is "soft_lutpair12"; - attribute SOFT_HLUTNM of \pushed_commands[1]_i_1\ : label is "soft_lutpair16"; - attribute SOFT_HLUTNM of \pushed_commands[2]_i_1\ : label is "soft_lutpair16"; - attribute SOFT_HLUTNM of \pushed_commands[3]_i_2\ : label is "soft_lutpair14"; - attribute SOFT_HLUTNM of \size_mask_q[0]_i_1\ : label is "soft_lutpair20"; - attribute SOFT_HLUTNM of \size_mask_q[1]_i_1\ : label is "soft_lutpair24"; - attribute SOFT_HLUTNM of \size_mask_q[2]_i_1\ : label is "soft_lutpair18"; - attribute SOFT_HLUTNM of \size_mask_q[3]_i_1\ : label is "soft_lutpair25"; - attribute SOFT_HLUTNM of \size_mask_q[4]_i_1\ : label is "soft_lutpair20"; - attribute SOFT_HLUTNM of \size_mask_q[5]_i_1\ : label is "soft_lutpair24"; - attribute SOFT_HLUTNM of \size_mask_q[6]_i_1\ : label is "soft_lutpair17"; - attribute SOFT_HLUTNM of split_in_progress_i_2 : label is "soft_lutpair10"; + attribute SOFT_HLUTNM of \addr_step_q[10]_i_1__0\ : label is "soft_lutpair15"; + attribute SOFT_HLUTNM of \addr_step_q[11]_i_1__0\ : label is "soft_lutpair14"; + attribute SOFT_HLUTNM of \addr_step_q[5]_i_1__0\ : label is "soft_lutpair19"; + attribute SOFT_HLUTNM of \addr_step_q[6]_i_1__0\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \addr_step_q[7]_i_1__0\ : label is "soft_lutpair19"; + attribute SOFT_HLUTNM of \addr_step_q[8]_i_1__0\ : label is "soft_lutpair14"; + attribute SOFT_HLUTNM of \addr_step_q[9]_i_1__0\ : label is "soft_lutpair12"; + attribute SOFT_HLUTNM of \first_step_q[0]_i_1__0\ : label is "soft_lutpair11"; + attribute SOFT_HLUTNM of \first_step_q[10]_i_1__0\ : label is "soft_lutpair21"; + attribute SOFT_HLUTNM of \first_step_q[11]_i_1__0\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \first_step_q[1]_i_1__0\ : label is "soft_lutpair11"; + attribute SOFT_HLUTNM of \first_step_q[3]_i_1__0\ : label is "soft_lutpair16"; + attribute SOFT_HLUTNM of \first_step_q[4]_i_1__0\ : label is "soft_lutpair12"; + attribute SOFT_HLUTNM of \first_step_q[6]_i_1__0\ : label is "soft_lutpair21"; + attribute SOFT_HLUTNM of \first_step_q[7]_i_1__0\ : label is "soft_lutpair16"; + attribute SOFT_HLUTNM of \first_step_q[8]_i_1__0\ : label is "soft_lutpair24"; + attribute SOFT_HLUTNM of \first_step_q[9]_i_1__0\ : label is "soft_lutpair24"; + attribute SOFT_HLUTNM of \m_axi_araddr[26]_INST_0\ : label is "soft_lutpair10"; + attribute SOFT_HLUTNM of \next_mi_addr[11]_i_6__0\ : label is "soft_lutpair13"; + attribute SOFT_HLUTNM of \next_mi_addr[3]_i_6__0\ : label is "soft_lutpair10"; + attribute SOFT_HLUTNM of \pushed_commands[1]_i_1__0\ : label is "soft_lutpair20"; + attribute SOFT_HLUTNM of \pushed_commands[2]_i_1__0\ : label is "soft_lutpair20"; + attribute SOFT_HLUTNM of \pushed_commands[3]_i_2__0\ : label is "soft_lutpair13"; + attribute SOFT_HLUTNM of \size_mask_q[0]_i_1__0\ : label is "soft_lutpair17"; + attribute SOFT_HLUTNM of \size_mask_q[1]_i_1__0\ : label is "soft_lutpair22"; + attribute SOFT_HLUTNM of \size_mask_q[2]_i_1__0\ : label is "soft_lutpair17"; + attribute SOFT_HLUTNM of \size_mask_q[3]_i_1__0\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \size_mask_q[4]_i_1__0\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \size_mask_q[5]_i_1__0\ : label is "soft_lutpair22"; + attribute SOFT_HLUTNM of \size_mask_q[6]_i_1__0\ : label is "soft_lutpair15"; begin E(0) <= \^e\(0); - M_AXI_ARID(0) <= \^m_axi_arid\(0); m_axi_araddr(31 downto 0) <= \^m_axi_araddr\(31 downto 0); + \m_axi_arid[0]\ <= \^m_axi_arid[0]\; \S_AXI_AADDR_Q_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(0), - Q => S_AXI_AADDR_Q(0), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[0]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(10), - Q => S_AXI_AADDR_Q(10), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[10]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(11), - Q => S_AXI_AADDR_Q(11), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[11]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(12), - Q => S_AXI_AADDR_Q(12), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[12]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(13), - Q => S_AXI_AADDR_Q(13), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[13]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(14), - Q => S_AXI_AADDR_Q(14), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[14]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(15), - Q => S_AXI_AADDR_Q(15), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[15]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(16), - Q => S_AXI_AADDR_Q(16), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[16]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(17), - Q => S_AXI_AADDR_Q(17), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[17]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(18), - Q => S_AXI_AADDR_Q(18), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[18]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(19), - Q => S_AXI_AADDR_Q(19), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[19]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(1), - Q => S_AXI_AADDR_Q(1), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[1]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(20), - Q => S_AXI_AADDR_Q(20), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[20]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(21), - Q => S_AXI_AADDR_Q(21), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[21]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(22), - Q => S_AXI_AADDR_Q(22), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[22]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(23), - Q => S_AXI_AADDR_Q(23), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[23]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(24), - Q => S_AXI_AADDR_Q(24), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[24]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(25), - Q => S_AXI_AADDR_Q(25), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[25]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(26), - Q => S_AXI_AADDR_Q(26), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[26]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(27), - Q => S_AXI_AADDR_Q(27), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[27]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(28), - Q => S_AXI_AADDR_Q(28), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[28]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(29), - Q => S_AXI_AADDR_Q(29), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[29]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(2), - Q => S_AXI_AADDR_Q(2), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[2]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(30), - Q => S_AXI_AADDR_Q(30), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[30]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(31), - Q => S_AXI_AADDR_Q(31), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[31]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(3), - Q => S_AXI_AADDR_Q(3), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[3]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(4), - Q => S_AXI_AADDR_Q(4), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[4]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(5), - Q => S_AXI_AADDR_Q(5), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[5]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(6), - Q => S_AXI_AADDR_Q(6), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[6]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(7), - Q => S_AXI_AADDR_Q(7), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[7]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(8), - Q => S_AXI_AADDR_Q(8), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[8]\, + R => aresetn_0 ); \S_AXI_AADDR_Q_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_araddr(9), - Q => S_AXI_AADDR_Q(9), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \S_AXI_AADDR_Q_reg_n_0_[9]\, + R => aresetn_0 ); \S_AXI_ABURST_Q_reg[0]\: unisim.vcomponents.FDRE port map ( @@ -4848,7 +17102,7 @@ begin CE => \^e\(0), D => s_axi_arburst(0), Q => m_axi_arburst(0), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \S_AXI_ABURST_Q_reg[1]\: unisim.vcomponents.FDRE port map ( @@ -4856,7 +17110,7 @@ begin CE => \^e\(0), D => s_axi_arburst(1), Q => m_axi_arburst(1), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \S_AXI_ACACHE_Q_reg[0]\: unisim.vcomponents.FDRE port map ( @@ -4864,7 +17118,7 @@ begin CE => \^e\(0), D => s_axi_arcache(0), Q => m_axi_arcache(0), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \S_AXI_ACACHE_Q_reg[1]\: unisim.vcomponents.FDRE port map ( @@ -4872,7 +17126,7 @@ begin CE => \^e\(0), D => s_axi_arcache(1), Q => m_axi_arcache(1), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \S_AXI_ACACHE_Q_reg[2]\: unisim.vcomponents.FDRE port map ( @@ -4880,7 +17134,7 @@ begin CE => \^e\(0), D => s_axi_arcache(2), Q => m_axi_arcache(2), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \S_AXI_ACACHE_Q_reg[3]\: unisim.vcomponents.FDRE port map ( @@ -4888,15 +17142,15 @@ begin CE => \^e\(0), D => s_axi_arcache(3), Q => m_axi_arcache(3), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \S_AXI_AID_Q_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_arid(0), - Q => \^m_axi_arid\(0), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \^m_axi_arid[0]\, + R => aresetn_0 ); \S_AXI_ALEN_Q_reg[0]\: unisim.vcomponents.FDRE port map ( @@ -4904,7 +17158,7 @@ begin CE => \^e\(0), D => s_axi_arlen(0), Q => S_AXI_ALEN_Q(0), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \S_AXI_ALEN_Q_reg[1]\: unisim.vcomponents.FDRE port map ( @@ -4912,7 +17166,7 @@ begin CE => \^e\(0), D => s_axi_arlen(1), Q => S_AXI_ALEN_Q(1), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \S_AXI_ALEN_Q_reg[2]\: unisim.vcomponents.FDRE port map ( @@ -4920,7 +17174,7 @@ begin CE => \^e\(0), D => s_axi_arlen(2), Q => S_AXI_ALEN_Q(2), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \S_AXI_ALEN_Q_reg[3]\: unisim.vcomponents.FDRE port map ( @@ -4928,7 +17182,7 @@ begin CE => \^e\(0), D => s_axi_arlen(3), Q => S_AXI_ALEN_Q(3), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \S_AXI_ALOCK_Q_reg[0]\: unisim.vcomponents.FDRE port map ( @@ -4936,7 +17190,7 @@ begin CE => \^e\(0), D => s_axi_arlock(0), Q => \S_AXI_ALOCK_Q_reg_n_0_[0]\, - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \S_AXI_APROT_Q_reg[0]\: unisim.vcomponents.FDRE port map ( @@ -4944,7 +17198,7 @@ begin CE => \^e\(0), D => s_axi_arprot(0), Q => m_axi_arprot(0), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \S_AXI_APROT_Q_reg[1]\: unisim.vcomponents.FDRE port map ( @@ -4952,7 +17206,7 @@ begin CE => \^e\(0), D => s_axi_arprot(1), Q => m_axi_arprot(1), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \S_AXI_APROT_Q_reg[2]\: unisim.vcomponents.FDRE port map ( @@ -4960,7 +17214,7 @@ begin CE => \^e\(0), D => s_axi_arprot(2), Q => m_axi_arprot(2), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \S_AXI_AQOS_Q_reg[0]\: unisim.vcomponents.FDRE port map ( @@ -4968,7 +17222,7 @@ begin CE => \^e\(0), D => s_axi_arqos(0), Q => m_axi_arqos(0), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \S_AXI_AQOS_Q_reg[1]\: unisim.vcomponents.FDRE port map ( @@ -4976,7 +17230,7 @@ begin CE => \^e\(0), D => s_axi_arqos(1), Q => m_axi_arqos(1), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \S_AXI_AQOS_Q_reg[2]\: unisim.vcomponents.FDRE port map ( @@ -4984,7 +17238,7 @@ begin CE => \^e\(0), D => s_axi_arqos(2), Q => m_axi_arqos(2), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \S_AXI_AQOS_Q_reg[3]\: unisim.vcomponents.FDRE port map ( @@ -4992,7 +17246,18 @@ begin CE => \^e\(0), D => s_axi_arqos(3), Q => m_axi_arqos(3), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 + ); +\S_AXI_AREADY_I_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"82FF" + ) + port map ( + I0 => \USE_R_CHANNEL.cmd_queue_n_8\, + I1 => \pushed_commands_reg__0\(3), + I2 => \num_transactions_q_reg_n_0_[3]\, + I3 => access_is_incr_q, + O => \S_AXI_AREADY_I_i_2__0_n_0\ ); S_AXI_AREADY_I_reg: unisim.vcomponents.FDRE port map ( @@ -5000,7 +17265,7 @@ S_AXI_AREADY_I_reg: unisim.vcomponents.FDRE CE => '1', D => \USE_R_CHANNEL.cmd_queue_n_16\, Q => \^e\(0), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \S_AXI_ASIZE_Q_reg[0]\: unisim.vcomponents.FDRE port map ( @@ -5008,7 +17273,7 @@ S_AXI_AREADY_I_reg: unisim.vcomponents.FDRE CE => \^e\(0), D => s_axi_arsize(0), Q => m_axi_arsize(0), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \S_AXI_ASIZE_Q_reg[1]\: unisim.vcomponents.FDRE port map ( @@ -5016,7 +17281,7 @@ S_AXI_AREADY_I_reg: unisim.vcomponents.FDRE CE => \^e\(0), D => s_axi_arsize(1), Q => m_axi_arsize(1), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \S_AXI_ASIZE_Q_reg[2]\: unisim.vcomponents.FDRE port map ( @@ -5024,61 +17289,63 @@ S_AXI_AREADY_I_reg: unisim.vcomponents.FDRE CE => \^e\(0), D => s_axi_arsize(2), Q => m_axi_arsize(2), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); -\USE_R_CHANNEL.cmd_queue\: entity work.Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_axic_fifo +\USE_R_CHANNEL.cmd_queue\: entity work.\Arty_Z7_20_auto_pc_0_axi_data_fifo_v2_1_10_axic_fifo__parameterized0\ port map ( - D(4) => \USE_R_CHANNEL.cmd_queue_n_4\, - D(3) => \USE_R_CHANNEL.cmd_queue_n_5\, - D(2) => \USE_R_CHANNEL.cmd_queue_n_6\, - D(1) => \USE_R_CHANNEL.cmd_queue_n_7\, - D(0) => \USE_R_CHANNEL.cmd_queue_n_8\, - E(0) => \USE_R_CHANNEL.cmd_queue_n_11\, + D(4) => \USE_R_CHANNEL.cmd_queue_n_3\, + D(3) => \USE_R_CHANNEL.cmd_queue_n_4\, + D(2) => \USE_R_CHANNEL.cmd_queue_n_5\, + D(1) => \USE_R_CHANNEL.cmd_queue_n_6\, + D(0) => \USE_R_CHANNEL.cmd_queue_n_7\, + E(0) => pushed_new_cmd, Q(5 downto 0) => \cmd_depth_reg__0\(5 downto 0), - SR(0) => \USE_R_CHANNEL.cmd_queue_n_0\, - \S_AXI_AID_Q_reg[0]\ => \^m_axi_arid\(0), - \S_AXI_AID_Q_reg[0]_0\ => multiple_id_non_split_i_2_n_0, + \S_AXI_AID_Q_reg[0]\ => \^m_axi_arid[0]\, S_AXI_AREADY_I_reg => \USE_R_CHANNEL.cmd_queue_n_16\, S_AXI_AREADY_I_reg_0 => \^e\(0), access_is_incr_q => access_is_incr_q, aclk => aclk, + \allow_split_cmd__1\ => \allow_split_cmd__1\, almost_empty => almost_empty, - \areset_d_reg[1]\(1 downto 0) => areset_d(1 downto 0), - \areset_d_reg[1]_0\ => command_ongoing_i_2_n_0, + areset_d(1 downto 0) => areset_d(1 downto 0), + \areset_d_reg[1]\ => \areset_d_reg[1]\, aresetn => aresetn, - \cmd_depth_reg[1]\ => \cmd_depth[5]_i_4_n_0\, - \cmd_depth_reg[3]\ => \cmd_depth[5]_i_3_n_0\, + aresetn_0 => aresetn_0, + \cmd_depth_reg[5]\(0) => \USE_R_CHANNEL.cmd_queue_n_14\, cmd_empty => cmd_empty, - cmd_empty0 => cmd_empty0, - cmd_empty_reg => split_in_progress_i_2_n_0, - cmd_push => cmd_push, cmd_push_block => cmd_push_block, - cmd_push_block_reg => \USE_R_CHANNEL.cmd_queue_n_17\, + cmd_push_block_reg => \USE_R_CHANNEL.cmd_queue_n_13\, command_ongoing => command_ongoing, - command_ongoing_reg => \USE_R_CHANNEL.cmd_queue_n_19\, - din(0) => \USE_R_CHANNEL.cmd_queue_n_1\, + command_ongoing_reg => \USE_R_CHANNEL.cmd_queue_n_18\, + din(0) => \USE_R_CHANNEL.cmd_queue_n_0\, m_axi_arready => m_axi_arready, m_axi_arvalid => m_axi_arvalid, m_axi_rlast => m_axi_rlast, m_axi_rready => m_axi_rready, m_axi_rvalid => m_axi_rvalid, multiple_id_non_split => multiple_id_non_split, - multiple_id_non_split_reg => \USE_R_CHANNEL.cmd_queue_n_20\, + multiple_id_non_split_reg => \USE_R_CHANNEL.cmd_queue_n_19\, need_to_split_q => need_to_split_q, - num_transactions_q(3 downto 0) => num_transactions_q(3 downto 0), + \num_transactions_q_reg[0]\ => \num_transactions_q_reg_n_0_[0]\, + \num_transactions_q_reg[1]\ => \num_transactions_q_reg_n_0_[1]\, + \num_transactions_q_reg[2]\ => \num_transactions_q_reg_n_0_[2]\, + \num_transactions_q_reg[3]\ => \num_transactions_q_reg_n_0_[3]\, \pushed_commands_reg[3]\(3 downto 0) => \pushed_commands_reg__0\(3 downto 0), - pushed_new_cmd => pushed_new_cmd, - queue_id => queue_id, - \queue_id_reg[0]\ => \USE_R_CHANNEL.cmd_queue_n_18\, + \pushed_commands_reg[3]_0\ => \S_AXI_AREADY_I_i_2__0_n_0\, + \queue_id_reg[0]\ => \USE_R_CHANNEL.cmd_queue_n_17\, + \queue_id_reg[0]_0\ => \queue_id_reg_n_0_[0]\, rd_cmd_ready => rd_cmd_ready, s_axi_arvalid => s_axi_arvalid, s_axi_rlast => s_axi_rlast, s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid, - split_in_progress_reg => \USE_R_CHANNEL.cmd_queue_n_21\, - split_in_progress_reg_0 => split_in_progress_reg_n_0 + split_in_progress_reg => \USE_R_CHANNEL.cmd_queue_n_1\, + split_in_progress_reg_0 => \USE_R_CHANNEL.cmd_queue_n_20\, + split_in_progress_reg_1 => split_in_progress_reg_n_0, + split_in_progress_reg_2 => \multiple_id_non_split_i_2__0_n_0\, + split_ongoing_reg => \USE_R_CHANNEL.cmd_queue_n_8\ ); -access_is_incr_q_i_1: unisim.vcomponents.LUT2 +\access_is_incr_q_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) @@ -5093,9 +17360,9 @@ access_is_incr_q_reg: unisim.vcomponents.FDRE CE => \^e\(0), D => access_is_incr, Q => access_is_incr_q, - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); -\addr_step_q[10]_i_1\: unisim.vcomponents.LUT3 +\addr_step_q[10]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"08" ) @@ -5103,9 +17370,9 @@ access_is_incr_q_reg: unisim.vcomponents.FDRE I0 => s_axi_arsize(1), I1 => s_axi_arsize(2), I2 => s_axi_arsize(0), - O => addr_step(10) + O => \addr_step_q[10]_i_1__0_n_0\ ); -\addr_step_q[11]_i_1\: unisim.vcomponents.LUT3 +\addr_step_q[11]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) @@ -5113,9 +17380,9 @@ access_is_incr_q_reg: unisim.vcomponents.FDRE I0 => s_axi_arsize(1), I1 => s_axi_arsize(0), I2 => s_axi_arsize(2), - O => addr_step(11) + O => \addr_step_q[11]_i_1__0_n_0\ ); -\addr_step_q[5]_i_1\: unisim.vcomponents.LUT3 +\addr_step_q[5]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) @@ -5123,9 +17390,9 @@ access_is_incr_q_reg: unisim.vcomponents.FDRE I0 => s_axi_arsize(2), I1 => s_axi_arsize(0), I2 => s_axi_arsize(1), - O => addr_step(5) + O => \addr_step_q[5]_i_1__0_n_0\ ); -\addr_step_q[6]_i_1\: unisim.vcomponents.LUT3 +\addr_step_q[6]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) @@ -5133,9 +17400,9 @@ access_is_incr_q_reg: unisim.vcomponents.FDRE I0 => s_axi_arsize(0), I1 => s_axi_arsize(1), I2 => s_axi_arsize(2), - O => addr_step(6) + O => \addr_step_q[6]_i_1__0_n_0\ ); -\addr_step_q[7]_i_1\: unisim.vcomponents.LUT3 +\addr_step_q[7]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"08" ) @@ -5143,9 +17410,9 @@ access_is_incr_q_reg: unisim.vcomponents.FDRE I0 => s_axi_arsize(1), I1 => s_axi_arsize(0), I2 => s_axi_arsize(2), - O => addr_step(7) + O => \addr_step_q[7]_i_1__0_n_0\ ); -\addr_step_q[8]_i_1\: unisim.vcomponents.LUT3 +\addr_step_q[8]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) @@ -5153,9 +17420,9 @@ access_is_incr_q_reg: unisim.vcomponents.FDRE I0 => s_axi_arsize(0), I1 => s_axi_arsize(2), I2 => s_axi_arsize(1), - O => addr_step(8) + O => \addr_step_q[8]_i_1__0_n_0\ ); -\addr_step_q[9]_i_1\: unisim.vcomponents.LUT3 +\addr_step_q[9]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"08" ) @@ -5163,179 +17430,142 @@ access_is_incr_q_reg: unisim.vcomponents.FDRE I0 => s_axi_arsize(2), I1 => s_axi_arsize(0), I2 => s_axi_arsize(1), - O => addr_step(9) + O => \addr_step_q[9]_i_1__0_n_0\ ); \addr_step_q_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), - D => addr_step(10), - Q => addr_step_q(10), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + D => \addr_step_q[10]_i_1__0_n_0\, + Q => \addr_step_q_reg_n_0_[10]\, + R => aresetn_0 ); \addr_step_q_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), - D => addr_step(11), - Q => addr_step_q(11), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + D => \addr_step_q[11]_i_1__0_n_0\, + Q => \addr_step_q_reg_n_0_[11]\, + R => aresetn_0 ); \addr_step_q_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), - D => addr_step(5), - Q => addr_step_q(5), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + D => \addr_step_q[5]_i_1__0_n_0\, + Q => \addr_step_q_reg_n_0_[5]\, + R => aresetn_0 ); \addr_step_q_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), - D => addr_step(6), - Q => addr_step_q(6), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + D => \addr_step_q[6]_i_1__0_n_0\, + Q => \addr_step_q_reg_n_0_[6]\, + R => aresetn_0 ); \addr_step_q_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), - D => addr_step(7), - Q => addr_step_q(7), - R => \USE_R_CHANNEL.cmd_queue_n_0\ - ); -\addr_step_q_reg[8]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => \^e\(0), - D => addr_step(8), - Q => addr_step_q(8), - R => \USE_R_CHANNEL.cmd_queue_n_0\ - ); -\addr_step_q_reg[9]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => \^e\(0), - D => addr_step(9), - Q => addr_step_q(9), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + D => \addr_step_q[7]_i_1__0_n_0\, + Q => \addr_step_q_reg_n_0_[7]\, + R => aresetn_0 ); -\areset_d_reg[0]\: unisim.vcomponents.FDRE +\addr_step_q_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, - CE => '1', - D => \USE_R_CHANNEL.cmd_queue_n_0\, - Q => areset_d(0), - R => '0' + CE => \^e\(0), + D => \addr_step_q[8]_i_1__0_n_0\, + Q => \addr_step_q_reg_n_0_[8]\, + R => aresetn_0 ); -\areset_d_reg[1]\: unisim.vcomponents.FDRE +\addr_step_q_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, - CE => '1', - D => areset_d(0), - Q => areset_d(1), - R => '0' + CE => \^e\(0), + D => \addr_step_q[9]_i_1__0_n_0\, + Q => \addr_step_q_reg_n_0_[9]\, + R => aresetn_0 ); -\cmd_depth[0]_i_1\: unisim.vcomponents.LUT1 +\cmd_depth[0]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cmd_depth_reg__0\(0), - O => \cmd_depth[0]_i_1_n_0\ - ); -\cmd_depth[5]_i_3\: unisim.vcomponents.LUT3 - generic map( - INIT => X"01" - ) - port map ( - I0 => \cmd_depth_reg__0\(3), - I1 => \cmd_depth_reg__0\(1), - I2 => \cmd_depth_reg__0\(2), - O => \cmd_depth[5]_i_3_n_0\ - ); -\cmd_depth[5]_i_4\: unisim.vcomponents.LUT3 - generic map( - INIT => X"7F" - ) - port map ( - I0 => \cmd_depth_reg__0\(1), - I1 => \cmd_depth_reg__0\(2), - I2 => \cmd_depth_reg__0\(3), - O => \cmd_depth[5]_i_4_n_0\ + O => \cmd_depth[0]_i_1__0_n_0\ ); \cmd_depth_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, - CE => \USE_R_CHANNEL.cmd_queue_n_11\, - D => \cmd_depth[0]_i_1_n_0\, + CE => \USE_R_CHANNEL.cmd_queue_n_14\, + D => \cmd_depth[0]_i_1__0_n_0\, Q => \cmd_depth_reg__0\(0), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \cmd_depth_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, - CE => \USE_R_CHANNEL.cmd_queue_n_11\, - D => \USE_R_CHANNEL.cmd_queue_n_8\, + CE => \USE_R_CHANNEL.cmd_queue_n_14\, + D => \USE_R_CHANNEL.cmd_queue_n_7\, Q => \cmd_depth_reg__0\(1), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \cmd_depth_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, - CE => \USE_R_CHANNEL.cmd_queue_n_11\, - D => \USE_R_CHANNEL.cmd_queue_n_7\, + CE => \USE_R_CHANNEL.cmd_queue_n_14\, + D => \USE_R_CHANNEL.cmd_queue_n_6\, Q => \cmd_depth_reg__0\(2), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \cmd_depth_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, - CE => \USE_R_CHANNEL.cmd_queue_n_11\, - D => \USE_R_CHANNEL.cmd_queue_n_6\, + CE => \USE_R_CHANNEL.cmd_queue_n_14\, + D => \USE_R_CHANNEL.cmd_queue_n_5\, Q => \cmd_depth_reg__0\(3), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \cmd_depth_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, - CE => \USE_R_CHANNEL.cmd_queue_n_11\, - D => \USE_R_CHANNEL.cmd_queue_n_5\, + CE => \USE_R_CHANNEL.cmd_queue_n_14\, + D => \USE_R_CHANNEL.cmd_queue_n_4\, Q => \cmd_depth_reg__0\(4), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \cmd_depth_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, - CE => \USE_R_CHANNEL.cmd_queue_n_11\, - D => \USE_R_CHANNEL.cmd_queue_n_4\, + CE => \USE_R_CHANNEL.cmd_queue_n_14\, + D => \USE_R_CHANNEL.cmd_queue_n_3\, Q => \cmd_depth_reg__0\(5), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); -cmd_empty_i_1: unisim.vcomponents.LUT5 +cmd_empty_i_1: unisim.vcomponents.LUT4 generic map( - INIT => X"00EF0020" + INIT => X"CB08" ) port map ( I0 => almost_empty, - I1 => cmd_push, - I2 => rd_cmd_ready, - I3 => cmd_empty0, - I4 => cmd_empty, + I1 => rd_cmd_ready, + I2 => \USE_R_CHANNEL.cmd_queue_n_1\, + I3 => cmd_empty, O => cmd_empty_i_1_n_0 ); -cmd_empty_i_2: unisim.vcomponents.LUT6 +\cmd_empty_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000100" ) port map ( - I0 => \cmd_depth_reg__0\(2), - I1 => \cmd_depth_reg__0\(1), - I2 => \cmd_depth_reg__0\(3), + I0 => \cmd_depth_reg__0\(4), + I1 => \cmd_depth_reg__0\(3), + I2 => \cmd_depth_reg__0\(5), I3 => \cmd_depth_reg__0\(0), - I4 => \cmd_depth_reg__0\(5), - I5 => \cmd_depth_reg__0\(4), + I4 => \cmd_depth_reg__0\(1), + I5 => \cmd_depth_reg__0\(2), O => almost_empty ); cmd_empty_reg: unisim.vcomponents.FDSE @@ -5344,34 +17574,25 @@ cmd_empty_reg: unisim.vcomponents.FDSE CE => '1', D => cmd_empty_i_1_n_0, Q => cmd_empty, - S => \USE_R_CHANNEL.cmd_queue_n_0\ + S => aresetn_0 ); cmd_push_block_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', - D => \USE_R_CHANNEL.cmd_queue_n_17\, + D => \USE_R_CHANNEL.cmd_queue_n_13\, Q => cmd_push_block, R => '0' ); -command_ongoing_i_2: unisim.vcomponents.LUT2 - generic map( - INIT => X"2" - ) - port map ( - I0 => areset_d(1), - I1 => areset_d(0), - O => command_ongoing_i_2_n_0 - ); command_ongoing_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', - D => \USE_R_CHANNEL.cmd_queue_n_19\, + D => \USE_R_CHANNEL.cmd_queue_n_18\, Q => command_ongoing, - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); -\first_step_q[0]_i_1\: unisim.vcomponents.LUT4 +\first_step_q[0]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) @@ -5380,18 +17601,18 @@ command_ongoing_reg: unisim.vcomponents.FDRE I1 => s_axi_arsize(0), I2 => s_axi_arlen(0), I3 => s_axi_arsize(2), - O => \first_step_q[0]_i_1_n_0\ + O => \first_step_q[0]_i_1__0_n_0\ ); -\first_step_q[10]_i_1\: unisim.vcomponents.LUT2 +\first_step_q[10]_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => s_axi_arsize(2), - I1 => \first_step_q[10]_i_2_n_0\, + I1 => \first_step_q[10]_i_2__0_n_0\, O => first_step(10) ); -\first_step_q[10]_i_2\: unisim.vcomponents.LUT6 +\first_step_q[10]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"2AAA800080000000" ) @@ -5402,18 +17623,18 @@ command_ongoing_reg: unisim.vcomponents.FDRE I3 => s_axi_arlen(1), I4 => s_axi_arlen(3), I5 => s_axi_arsize(0), - O => \first_step_q[10]_i_2_n_0\ + O => \first_step_q[10]_i_2__0_n_0\ ); -\first_step_q[11]_i_1\: unisim.vcomponents.LUT2 +\first_step_q[11]_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => s_axi_arsize(2), - I1 => \first_step_q[11]_i_2_n_0\, + I1 => \first_step_q[11]_i_2__0_n_0\, O => first_step(11) ); -\first_step_q[11]_i_2\: unisim.vcomponents.LUT6 +\first_step_q[11]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) @@ -5424,9 +17645,9 @@ command_ongoing_reg: unisim.vcomponents.FDRE I3 => s_axi_arlen(0), I4 => s_axi_arlen(2), I5 => s_axi_arsize(0), - O => \first_step_q[11]_i_2_n_0\ + O => \first_step_q[11]_i_2__0_n_0\ ); -\first_step_q[1]_i_1\: unisim.vcomponents.LUT5 +\first_step_q[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"00000514" ) @@ -5436,9 +17657,9 @@ command_ongoing_reg: unisim.vcomponents.FDRE I2 => s_axi_arlen(0), I3 => s_axi_arlen(1), I4 => s_axi_arsize(2), - O => \first_step_q[1]_i_1_n_0\ + O => \first_step_q[1]_i_1__0_n_0\ ); -\first_step_q[2]_i_1\: unisim.vcomponents.LUT6 +\first_step_q[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000000F3C6A" ) @@ -5449,18 +17670,18 @@ command_ongoing_reg: unisim.vcomponents.FDRE I3 => s_axi_arsize(0), I4 => s_axi_arsize(1), I5 => s_axi_arsize(2), - O => \first_step_q[2]_i_1_n_0\ + O => \first_step_q[2]_i_1__0_n_0\ ); -\first_step_q[3]_i_1\: unisim.vcomponents.LUT2 +\first_step_q[3]_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( - I0 => \first_step_q[7]_i_2_n_0\, + I0 => \first_step_q[7]_i_2__0_n_0\, I1 => s_axi_arsize(2), - O => \first_step_q[3]_i_1_n_0\ + O => \first_step_q[3]_i_1__0_n_0\ ); -\first_step_q[4]_i_1\: unisim.vcomponents.LUT5 +\first_step_q[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"01FF0100" ) @@ -5469,10 +17690,10 @@ command_ongoing_reg: unisim.vcomponents.FDRE I1 => s_axi_arsize(0), I2 => s_axi_arsize(1), I3 => s_axi_arsize(2), - I4 => \first_step_q[8]_i_2_n_0\, + I4 => \first_step_q[8]_i_2__0_n_0\, O => first_step(4) ); -\first_step_q[5]_i_1\: unisim.vcomponents.LUT6 +\first_step_q[5]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0036FFFF00360000" ) @@ -5482,20 +17703,20 @@ command_ongoing_reg: unisim.vcomponents.FDRE I2 => s_axi_arsize(0), I3 => s_axi_arsize(1), I4 => s_axi_arsize(2), - I5 => \first_step_q[9]_i_2_n_0\, + I5 => \first_step_q[9]_i_2__0_n_0\, O => first_step(5) ); -\first_step_q[6]_i_1\: unisim.vcomponents.LUT3 +\first_step_q[6]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( - I0 => \first_step_q[6]_i_2_n_0\, + I0 => \first_step_q[6]_i_2__0_n_0\, I1 => s_axi_arsize(2), - I2 => \first_step_q[10]_i_2_n_0\, + I2 => \first_step_q[10]_i_2__0_n_0\, O => first_step(6) ); -\first_step_q[6]_i_2\: unisim.vcomponents.LUT5 +\first_step_q[6]_i_2__0\: unisim.vcomponents.LUT5 generic map( INIT => X"07531642" ) @@ -5505,19 +17726,19 @@ command_ongoing_reg: unisim.vcomponents.FDRE I2 => s_axi_arlen(0), I3 => s_axi_arlen(1), I4 => s_axi_arlen(2), - O => \first_step_q[6]_i_2_n_0\ + O => \first_step_q[6]_i_2__0_n_0\ ); -\first_step_q[7]_i_1\: unisim.vcomponents.LUT3 +\first_step_q[7]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( - I0 => \first_step_q[7]_i_2_n_0\, + I0 => \first_step_q[7]_i_2__0_n_0\, I1 => s_axi_arsize(2), - I2 => \first_step_q[11]_i_2_n_0\, + I2 => \first_step_q[11]_i_2__0_n_0\, O => first_step(7) ); -\first_step_q[7]_i_2\: unisim.vcomponents.LUT6 +\first_step_q[7]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"07FD53B916EC42A8" ) @@ -5528,18 +17749,18 @@ command_ongoing_reg: unisim.vcomponents.FDRE I3 => s_axi_arlen(0), I4 => s_axi_arlen(2), I5 => s_axi_arlen(3), - O => \first_step_q[7]_i_2_n_0\ + O => \first_step_q[7]_i_2__0_n_0\ ); -\first_step_q[8]_i_1\: unisim.vcomponents.LUT2 +\first_step_q[8]_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => s_axi_arsize(2), - I1 => \first_step_q[8]_i_2_n_0\, + I1 => \first_step_q[8]_i_2__0_n_0\, O => first_step(8) ); -\first_step_q[8]_i_2\: unisim.vcomponents.LUT6 +\first_step_q[8]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"14EAEA6262C8C840" ) @@ -5550,18 +17771,18 @@ command_ongoing_reg: unisim.vcomponents.FDRE I3 => s_axi_arlen(1), I4 => s_axi_arlen(0), I5 => s_axi_arlen(2), - O => \first_step_q[8]_i_2_n_0\ + O => \first_step_q[8]_i_2__0_n_0\ ); -\first_step_q[9]_i_1\: unisim.vcomponents.LUT2 +\first_step_q[9]_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => s_axi_arsize(2), - I1 => \first_step_q[9]_i_2_n_0\, + I1 => \first_step_q[9]_i_2__0_n_0\, O => first_step(9) ); -\first_step_q[9]_i_2\: unisim.vcomponents.LUT6 +\first_step_q[9]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"4AA2A2A228808080" ) @@ -5572,103 +17793,103 @@ command_ongoing_reg: unisim.vcomponents.FDRE I3 => s_axi_arlen(0), I4 => s_axi_arlen(1), I5 => s_axi_arlen(3), - O => \first_step_q[9]_i_2_n_0\ + O => \first_step_q[9]_i_2__0_n_0\ ); \first_step_q_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), - D => \first_step_q[0]_i_1_n_0\, - Q => first_step_q(0), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + D => \first_step_q[0]_i_1__0_n_0\, + Q => \first_step_q_reg_n_0_[0]\, + R => aresetn_0 ); \first_step_q_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => first_step(10), - Q => first_step_q(10), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \first_step_q_reg_n_0_[10]\, + R => aresetn_0 ); \first_step_q_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => first_step(11), - Q => first_step_q(11), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \first_step_q_reg_n_0_[11]\, + R => aresetn_0 ); \first_step_q_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), - D => \first_step_q[1]_i_1_n_0\, - Q => first_step_q(1), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + D => \first_step_q[1]_i_1__0_n_0\, + Q => \first_step_q_reg_n_0_[1]\, + R => aresetn_0 ); \first_step_q_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), - D => \first_step_q[2]_i_1_n_0\, - Q => first_step_q(2), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + D => \first_step_q[2]_i_1__0_n_0\, + Q => \first_step_q_reg_n_0_[2]\, + R => aresetn_0 ); \first_step_q_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), - D => \first_step_q[3]_i_1_n_0\, - Q => first_step_q(3), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + D => \first_step_q[3]_i_1__0_n_0\, + Q => \first_step_q_reg_n_0_[3]\, + R => aresetn_0 ); \first_step_q_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => first_step(4), - Q => first_step_q(4), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \first_step_q_reg_n_0_[4]\, + R => aresetn_0 ); \first_step_q_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => first_step(5), - Q => first_step_q(5), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \first_step_q_reg_n_0_[5]\, + R => aresetn_0 ); \first_step_q_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => first_step(6), - Q => first_step_q(6), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \first_step_q_reg_n_0_[6]\, + R => aresetn_0 ); \first_step_q_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => first_step(7), - Q => first_step_q(7), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \first_step_q_reg_n_0_[7]\, + R => aresetn_0 ); \first_step_q_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => first_step(8), - Q => first_step_q(8), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \first_step_q_reg_n_0_[8]\, + R => aresetn_0 ); \first_step_q_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => first_step(9), - Q => first_step_q(9), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \first_step_q_reg_n_0_[9]\, + R => aresetn_0 ); incr_need_to_split: unisim.vcomponents.LUT6 generic map( @@ -5689,442 +17910,442 @@ incr_need_to_split_q_reg: unisim.vcomponents.FDRE CE => \^e\(0), D => \incr_need_to_split__0\, Q => need_to_split_q, - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"8FFF8000" + INIT => X"88F0F0F0" ) port map ( - I0 => size_mask_q(0), - I1 => next_mi_addr(0), - I2 => access_is_incr_q, + I0 => next_mi_addr(0), + I1 => size_mask_q(0), + I2 => \S_AXI_AADDR_Q_reg_n_0_[0]\, I3 => split_ongoing, - I4 => S_AXI_AADDR_Q(0), + I4 => access_is_incr_q, O => \^m_axi_araddr\(0) ); \m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(10), + I0 => next_mi_addr(10), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(10), + I2 => \S_AXI_AADDR_Q_reg_n_0_[10]\, + I3 => split_ongoing, + I4 => access_is_incr_q, O => \^m_axi_araddr\(10) ); \m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(11), + I0 => next_mi_addr(11), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(11), + I2 => \S_AXI_AADDR_Q_reg_n_0_[11]\, + I3 => split_ongoing, + I4 => access_is_incr_q, O => \^m_axi_araddr\(11) ); \m_axi_araddr[12]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(12), + I0 => next_mi_addr(12), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(12), + I2 => \S_AXI_AADDR_Q_reg_n_0_[12]\, + I3 => split_ongoing, + I4 => access_is_incr_q, O => \^m_axi_araddr\(12) ); \m_axi_araddr[13]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(13), + I0 => next_mi_addr(13), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(13), + I2 => \S_AXI_AADDR_Q_reg_n_0_[13]\, + I3 => split_ongoing, + I4 => access_is_incr_q, O => \^m_axi_araddr\(13) ); \m_axi_araddr[14]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(14), + I0 => next_mi_addr(14), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(14), + I2 => \S_AXI_AADDR_Q_reg_n_0_[14]\, + I3 => split_ongoing, + I4 => access_is_incr_q, O => \^m_axi_araddr\(14) ); \m_axi_araddr[15]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(15), + I0 => next_mi_addr(15), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(15), + I2 => \S_AXI_AADDR_Q_reg_n_0_[15]\, + I3 => split_ongoing, + I4 => access_is_incr_q, O => \^m_axi_araddr\(15) ); \m_axi_araddr[16]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(16), + I0 => next_mi_addr(16), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(16), + I2 => \S_AXI_AADDR_Q_reg_n_0_[16]\, + I3 => split_ongoing, + I4 => access_is_incr_q, O => \^m_axi_araddr\(16) ); \m_axi_araddr[17]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(17), + I0 => next_mi_addr(17), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(17), + I2 => \S_AXI_AADDR_Q_reg_n_0_[17]\, + I3 => split_ongoing, + I4 => access_is_incr_q, O => \^m_axi_araddr\(17) ); \m_axi_araddr[18]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(18), + I0 => next_mi_addr(18), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(18), + I2 => \S_AXI_AADDR_Q_reg_n_0_[18]\, + I3 => split_ongoing, + I4 => access_is_incr_q, O => \^m_axi_araddr\(18) ); \m_axi_araddr[19]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(19), + I0 => next_mi_addr(19), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(19), + I2 => \S_AXI_AADDR_Q_reg_n_0_[19]\, + I3 => split_ongoing, + I4 => access_is_incr_q, O => \^m_axi_araddr\(19) ); \m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"8FFF8000" + INIT => X"88F0F0F0" ) port map ( - I0 => size_mask_q(1), - I1 => next_mi_addr(1), - I2 => access_is_incr_q, + I0 => next_mi_addr(1), + I1 => size_mask_q(1), + I2 => \S_AXI_AADDR_Q_reg_n_0_[1]\, I3 => split_ongoing, - I4 => S_AXI_AADDR_Q(1), + I4 => access_is_incr_q, O => \^m_axi_araddr\(1) ); \m_axi_araddr[20]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(20), + I0 => next_mi_addr(20), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(20), + I2 => \S_AXI_AADDR_Q_reg_n_0_[20]\, + I3 => split_ongoing, + I4 => access_is_incr_q, O => \^m_axi_araddr\(20) ); \m_axi_araddr[21]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(21), + I0 => next_mi_addr(21), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(21), + I2 => \S_AXI_AADDR_Q_reg_n_0_[21]\, + I3 => split_ongoing, + I4 => access_is_incr_q, O => \^m_axi_araddr\(21) ); \m_axi_araddr[22]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(22), + I0 => next_mi_addr(22), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(22), + I2 => \S_AXI_AADDR_Q_reg_n_0_[22]\, + I3 => split_ongoing, + I4 => access_is_incr_q, O => \^m_axi_araddr\(22) ); \m_axi_araddr[23]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(23), + I0 => next_mi_addr(23), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(23), + I2 => \S_AXI_AADDR_Q_reg_n_0_[23]\, + I3 => split_ongoing, + I4 => access_is_incr_q, O => \^m_axi_araddr\(23) ); \m_axi_araddr[24]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(24), + I0 => next_mi_addr(24), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(24), + I2 => \S_AXI_AADDR_Q_reg_n_0_[24]\, + I3 => split_ongoing, + I4 => access_is_incr_q, O => \^m_axi_araddr\(24) ); \m_axi_araddr[25]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(25), + I0 => next_mi_addr(25), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(25), + I2 => \S_AXI_AADDR_Q_reg_n_0_[25]\, + I3 => split_ongoing, + I4 => access_is_incr_q, O => \^m_axi_araddr\(25) ); \m_axi_araddr[26]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(26), + I0 => next_mi_addr(26), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(26), + I2 => \S_AXI_AADDR_Q_reg_n_0_[26]\, + I3 => split_ongoing, + I4 => access_is_incr_q, O => \^m_axi_araddr\(26) ); \m_axi_araddr[27]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(27), + I0 => next_mi_addr(27), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(27), + I2 => \S_AXI_AADDR_Q_reg_n_0_[27]\, + I3 => split_ongoing, + I4 => access_is_incr_q, O => \^m_axi_araddr\(27) ); \m_axi_araddr[28]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(28), + I0 => next_mi_addr(28), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(28), + I2 => \S_AXI_AADDR_Q_reg_n_0_[28]\, + I3 => split_ongoing, + I4 => access_is_incr_q, O => \^m_axi_araddr\(28) ); \m_axi_araddr[29]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(29), + I0 => next_mi_addr(29), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(29), + I2 => \S_AXI_AADDR_Q_reg_n_0_[29]\, + I3 => split_ongoing, + I4 => access_is_incr_q, O => \^m_axi_araddr\(29) ); \m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"8FFF8000" + INIT => X"88F0F0F0" ) port map ( - I0 => size_mask_q(2), - I1 => next_mi_addr(2), - I2 => access_is_incr_q, + I0 => next_mi_addr(2), + I1 => size_mask_q(2), + I2 => \S_AXI_AADDR_Q_reg_n_0_[2]\, I3 => split_ongoing, - I4 => S_AXI_AADDR_Q(2), + I4 => access_is_incr_q, O => \^m_axi_araddr\(2) ); \m_axi_araddr[30]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(30), + I0 => next_mi_addr(30), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(30), + I2 => \S_AXI_AADDR_Q_reg_n_0_[30]\, + I3 => split_ongoing, + I4 => access_is_incr_q, O => \^m_axi_araddr\(30) ); \m_axi_araddr[31]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(31), + I0 => next_mi_addr(31), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(31), + I2 => \S_AXI_AADDR_Q_reg_n_0_[31]\, + I3 => split_ongoing, + I4 => access_is_incr_q, O => \^m_axi_araddr\(31) ); \m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"8FFF8000" + INIT => X"88F0F0F0" ) port map ( - I0 => size_mask_q(3), - I1 => next_mi_addr(3), - I2 => access_is_incr_q, + I0 => next_mi_addr(3), + I1 => size_mask_q(3), + I2 => \S_AXI_AADDR_Q_reg_n_0_[3]\, I3 => split_ongoing, - I4 => S_AXI_AADDR_Q(3), + I4 => access_is_incr_q, O => \^m_axi_araddr\(3) ); \m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"8FFF8000" + INIT => X"88F0F0F0" ) port map ( - I0 => size_mask_q(4), - I1 => next_mi_addr(4), - I2 => access_is_incr_q, + I0 => next_mi_addr(4), + I1 => size_mask_q(4), + I2 => \S_AXI_AADDR_Q_reg_n_0_[4]\, I3 => split_ongoing, - I4 => S_AXI_AADDR_Q(4), + I4 => access_is_incr_q, O => \^m_axi_araddr\(4) ); \m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"8FFF8000" + INIT => X"88F0F0F0" ) port map ( - I0 => size_mask_q(5), - I1 => next_mi_addr(5), - I2 => access_is_incr_q, + I0 => next_mi_addr(5), + I1 => size_mask_q(5), + I2 => \S_AXI_AADDR_Q_reg_n_0_[5]\, I3 => split_ongoing, - I4 => S_AXI_AADDR_Q(5), + I4 => access_is_incr_q, O => \^m_axi_araddr\(5) ); \m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"8FFF8000" + INIT => X"88F0F0F0" ) port map ( - I0 => size_mask_q(6), - I1 => next_mi_addr(6), - I2 => access_is_incr_q, + I0 => next_mi_addr(6), + I1 => size_mask_q(6), + I2 => \S_AXI_AADDR_Q_reg_n_0_[6]\, I3 => split_ongoing, - I4 => S_AXI_AADDR_Q(6), + I4 => access_is_incr_q, O => \^m_axi_araddr\(6) ); \m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(7), + I0 => next_mi_addr(7), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(7), + I2 => \S_AXI_AADDR_Q_reg_n_0_[7]\, + I3 => split_ongoing, + I4 => access_is_incr_q, O => \^m_axi_araddr\(7) ); \m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(8), + I0 => next_mi_addr(8), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(8), + I2 => \S_AXI_AADDR_Q_reg_n_0_[8]\, + I3 => split_ongoing, + I4 => access_is_incr_q, O => \^m_axi_araddr\(8) ); \m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(9), + I0 => next_mi_addr(9), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(9), + I2 => \S_AXI_AADDR_Q_reg_n_0_[9]\, + I3 => split_ongoing, + I4 => access_is_incr_q, O => \^m_axi_araddr\(9) ); \m_axi_arlen[0]_INST_0\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFEAAAAAAAA" + INIT => X"EEEEEEEEEEEEEEEA" ) port map ( I0 => S_AXI_ALEN_Q(0), - I1 => \pushed_commands_reg__0\(0), - I2 => \pushed_commands_reg__0\(1), + I1 => need_to_split_q, + I2 => \pushed_commands_reg__0\(2), I3 => \pushed_commands_reg__0\(3), - I4 => \pushed_commands_reg__0\(2), - I5 => need_to_split_q, + I4 => \pushed_commands_reg__0\(1), + I5 => \pushed_commands_reg__0\(0), O => m_axi_arlen(0) ); \m_axi_arlen[1]_INST_0\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFEAAAAAAAA" + INIT => X"EEEEEEEEEEEEEEEA" ) port map ( I0 => S_AXI_ALEN_Q(1), - I1 => \pushed_commands_reg__0\(0), - I2 => \pushed_commands_reg__0\(1), + I1 => need_to_split_q, + I2 => \pushed_commands_reg__0\(2), I3 => \pushed_commands_reg__0\(3), - I4 => \pushed_commands_reg__0\(2), - I5 => need_to_split_q, + I4 => \pushed_commands_reg__0\(1), + I5 => \pushed_commands_reg__0\(0), O => m_axi_arlen(1) ); \m_axi_arlen[2]_INST_0\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFEAAAAAAAA" + INIT => X"EEEEEEEEEEEEEEEA" ) port map ( I0 => S_AXI_ALEN_Q(2), - I1 => \pushed_commands_reg__0\(0), - I2 => \pushed_commands_reg__0\(1), + I1 => need_to_split_q, + I2 => \pushed_commands_reg__0\(2), I3 => \pushed_commands_reg__0\(3), - I4 => \pushed_commands_reg__0\(2), - I5 => need_to_split_q, + I4 => \pushed_commands_reg__0\(1), + I5 => \pushed_commands_reg__0\(0), O => m_axi_arlen(2) ); \m_axi_arlen[3]_INST_0\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFEAAAAAAAA" + INIT => X"EEEEEEEEEEEEEEEA" ) port map ( I0 => S_AXI_ALEN_Q(3), - I1 => \pushed_commands_reg__0\(0), - I2 => \pushed_commands_reg__0\(1), + I1 => need_to_split_q, + I2 => \pushed_commands_reg__0\(2), I3 => \pushed_commands_reg__0\(3), - I4 => \pushed_commands_reg__0\(2), - I5 => need_to_split_q, + I4 => \pushed_commands_reg__0\(1), + I5 => \pushed_commands_reg__0\(0), O => m_axi_arlen(3) ); \m_axi_arlock[0]_INST_0\: unisim.vcomponents.LUT2 @@ -6136,511 +18357,511 @@ incr_need_to_split_q_reg: unisim.vcomponents.FDRE I1 => need_to_split_q, O => m_axi_arlock(0) ); -multiple_id_non_split_i_2: unisim.vcomponents.LUT5 +\multiple_id_non_split_i_2__0\: unisim.vcomponents.LUT5 generic map( - INIT => X"00006606" + INIT => X"0000FFD7" ) port map ( - I0 => \^m_axi_arid\(0), - I1 => queue_id, - I2 => split_in_progress_reg_n_0, + I0 => split_in_progress_reg_n_0, + I1 => \queue_id_reg_n_0_[0]\, + I2 => \^m_axi_arid[0]\, I3 => cmd_empty, I4 => need_to_split_q, - O => multiple_id_non_split_i_2_n_0 + O => \multiple_id_non_split_i_2__0_n_0\ ); multiple_id_non_split_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', - D => \USE_R_CHANNEL.cmd_queue_n_20\, + D => \USE_R_CHANNEL.cmd_queue_n_19\, Q => multiple_id_non_split, R => '0' ); \next_mi_addr[11]_i_2\: unisim.vcomponents.LUT4 generic map( - INIT => X"56A6" + INIT => X"569A" ) port map ( I0 => \^m_axi_araddr\(11), - I1 => addr_step_q(11), - I2 => \next_mi_addr[11]_i_6_n_0\, - I3 => first_step_q(11), + I1 => \first_split__2\, + I2 => \addr_step_q_reg_n_0_[11]\, + I3 => \first_step_q_reg_n_0_[11]\, O => \next_mi_addr[11]_i_2_n_0\ ); \next_mi_addr[11]_i_3\: unisim.vcomponents.LUT4 generic map( - INIT => X"56A6" + INIT => X"569A" ) port map ( I0 => \^m_axi_araddr\(10), - I1 => addr_step_q(10), - I2 => \next_mi_addr[11]_i_6_n_0\, - I3 => first_step_q(10), + I1 => \first_split__2\, + I2 => \addr_step_q_reg_n_0_[10]\, + I3 => \first_step_q_reg_n_0_[10]\, O => \next_mi_addr[11]_i_3_n_0\ ); \next_mi_addr[11]_i_4\: unisim.vcomponents.LUT4 generic map( - INIT => X"56A6" + INIT => X"569A" ) port map ( I0 => \^m_axi_araddr\(9), - I1 => addr_step_q(9), - I2 => \next_mi_addr[11]_i_6_n_0\, - I3 => first_step_q(9), + I1 => \first_split__2\, + I2 => \addr_step_q_reg_n_0_[9]\, + I3 => \first_step_q_reg_n_0_[9]\, O => \next_mi_addr[11]_i_4_n_0\ ); \next_mi_addr[11]_i_5\: unisim.vcomponents.LUT4 generic map( - INIT => X"56A6" + INIT => X"569A" ) port map ( I0 => \^m_axi_araddr\(8), - I1 => addr_step_q(8), - I2 => \next_mi_addr[11]_i_6_n_0\, - I3 => first_step_q(8), + I1 => \first_split__2\, + I2 => \addr_step_q_reg_n_0_[8]\, + I3 => \first_step_q_reg_n_0_[8]\, O => \next_mi_addr[11]_i_5_n_0\ ); -\next_mi_addr[11]_i_6\: unisim.vcomponents.LUT4 +\next_mi_addr[11]_i_6__0\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( - I0 => \pushed_commands_reg__0\(0), - I1 => \pushed_commands_reg__0\(1), - I2 => \pushed_commands_reg__0\(3), - I3 => \pushed_commands_reg__0\(2), - O => \next_mi_addr[11]_i_6_n_0\ + I0 => \pushed_commands_reg__0\(2), + I1 => \pushed_commands_reg__0\(3), + I2 => \pushed_commands_reg__0\(1), + I3 => \pushed_commands_reg__0\(0), + O => \first_split__2\ ); -\next_mi_addr[15]_i_2\: unisim.vcomponents.LUT5 +\next_mi_addr[15]_i_2__0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(15), + I0 => next_mi_addr(15), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(15), - O => \next_mi_addr[15]_i_2_n_0\ + I2 => \S_AXI_AADDR_Q_reg_n_0_[15]\, + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[15]_i_2__0_n_0\ ); -\next_mi_addr[15]_i_3\: unisim.vcomponents.LUT5 +\next_mi_addr[15]_i_3__0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(14), + I0 => next_mi_addr(14), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(14), - O => \next_mi_addr[15]_i_3_n_0\ + I2 => \S_AXI_AADDR_Q_reg_n_0_[14]\, + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[15]_i_3__0_n_0\ ); -\next_mi_addr[15]_i_4\: unisim.vcomponents.LUT5 +\next_mi_addr[15]_i_4__0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(13), + I0 => next_mi_addr(13), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(13), - O => \next_mi_addr[15]_i_4_n_0\ + I2 => \S_AXI_AADDR_Q_reg_n_0_[13]\, + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[15]_i_4__0_n_0\ ); -\next_mi_addr[15]_i_5\: unisim.vcomponents.LUT5 +\next_mi_addr[15]_i_5__0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(12), + I0 => next_mi_addr(12), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(12), - O => \next_mi_addr[15]_i_5_n_0\ + I2 => \S_AXI_AADDR_Q_reg_n_0_[12]\, + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[15]_i_5__0_n_0\ ); -\next_mi_addr[15]_i_6\: unisim.vcomponents.LUT5 +\next_mi_addr[15]_i_6__0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(15), + I0 => next_mi_addr(15), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(15), - O => \next_mi_addr[15]_i_6_n_0\ + I2 => \S_AXI_AADDR_Q_reg_n_0_[15]\, + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[15]_i_6__0_n_0\ ); -\next_mi_addr[15]_i_7\: unisim.vcomponents.LUT5 +\next_mi_addr[15]_i_7__0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(14), + I0 => next_mi_addr(14), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(14), - O => \next_mi_addr[15]_i_7_n_0\ + I2 => \S_AXI_AADDR_Q_reg_n_0_[14]\, + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[15]_i_7__0_n_0\ ); -\next_mi_addr[15]_i_8\: unisim.vcomponents.LUT5 +\next_mi_addr[15]_i_8__0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(13), + I0 => next_mi_addr(13), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(13), - O => \next_mi_addr[15]_i_8_n_0\ + I2 => \S_AXI_AADDR_Q_reg_n_0_[13]\, + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[15]_i_8__0_n_0\ ); -\next_mi_addr[15]_i_9\: unisim.vcomponents.LUT5 +\next_mi_addr[15]_i_9__0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(12), + I0 => next_mi_addr(12), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(12), - O => \next_mi_addr[15]_i_9_n_0\ + I2 => \S_AXI_AADDR_Q_reg_n_0_[12]\, + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[15]_i_9__0_n_0\ ); -\next_mi_addr[19]_i_2\: unisim.vcomponents.LUT5 +\next_mi_addr[19]_i_2__0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(19), + I0 => next_mi_addr(19), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(19), - O => \next_mi_addr[19]_i_2_n_0\ + I2 => \S_AXI_AADDR_Q_reg_n_0_[19]\, + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[19]_i_2__0_n_0\ ); -\next_mi_addr[19]_i_3\: unisim.vcomponents.LUT5 +\next_mi_addr[19]_i_3__0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(18), + I0 => next_mi_addr(18), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(18), - O => \next_mi_addr[19]_i_3_n_0\ + I2 => \S_AXI_AADDR_Q_reg_n_0_[18]\, + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[19]_i_3__0_n_0\ ); -\next_mi_addr[19]_i_4\: unisim.vcomponents.LUT5 +\next_mi_addr[19]_i_4__0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(17), + I0 => next_mi_addr(17), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(17), - O => \next_mi_addr[19]_i_4_n_0\ + I2 => \S_AXI_AADDR_Q_reg_n_0_[17]\, + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[19]_i_4__0_n_0\ ); -\next_mi_addr[19]_i_5\: unisim.vcomponents.LUT5 +\next_mi_addr[19]_i_5__0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(16), + I0 => next_mi_addr(16), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(16), - O => \next_mi_addr[19]_i_5_n_0\ + I2 => \S_AXI_AADDR_Q_reg_n_0_[16]\, + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[19]_i_5__0_n_0\ ); -\next_mi_addr[23]_i_2\: unisim.vcomponents.LUT5 +\next_mi_addr[23]_i_2__0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(23), + I0 => next_mi_addr(23), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(23), - O => \next_mi_addr[23]_i_2_n_0\ + I2 => \S_AXI_AADDR_Q_reg_n_0_[23]\, + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[23]_i_2__0_n_0\ ); -\next_mi_addr[23]_i_3\: unisim.vcomponents.LUT5 +\next_mi_addr[23]_i_3__0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(22), + I0 => next_mi_addr(22), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(22), - O => \next_mi_addr[23]_i_3_n_0\ + I2 => \S_AXI_AADDR_Q_reg_n_0_[22]\, + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[23]_i_3__0_n_0\ ); -\next_mi_addr[23]_i_4\: unisim.vcomponents.LUT5 +\next_mi_addr[23]_i_4__0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(21), + I0 => next_mi_addr(21), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(21), - O => \next_mi_addr[23]_i_4_n_0\ + I2 => \S_AXI_AADDR_Q_reg_n_0_[21]\, + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[23]_i_4__0_n_0\ ); -\next_mi_addr[23]_i_5\: unisim.vcomponents.LUT5 +\next_mi_addr[23]_i_5__0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(20), + I0 => next_mi_addr(20), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(20), - O => \next_mi_addr[23]_i_5_n_0\ + I2 => \S_AXI_AADDR_Q_reg_n_0_[20]\, + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[23]_i_5__0_n_0\ ); -\next_mi_addr[27]_i_2\: unisim.vcomponents.LUT5 +\next_mi_addr[27]_i_2__0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(27), + I0 => next_mi_addr(27), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(27), - O => \next_mi_addr[27]_i_2_n_0\ + I2 => \S_AXI_AADDR_Q_reg_n_0_[27]\, + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[27]_i_2__0_n_0\ ); -\next_mi_addr[27]_i_3\: unisim.vcomponents.LUT5 +\next_mi_addr[27]_i_3__0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(26), + I0 => next_mi_addr(26), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(26), - O => \next_mi_addr[27]_i_3_n_0\ + I2 => \S_AXI_AADDR_Q_reg_n_0_[26]\, + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[27]_i_3__0_n_0\ ); -\next_mi_addr[27]_i_4\: unisim.vcomponents.LUT5 +\next_mi_addr[27]_i_4__0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(25), - I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(25), - O => \next_mi_addr[27]_i_4_n_0\ + I0 => next_mi_addr(25), + I1 => size_mask_q(31), + I2 => \S_AXI_AADDR_Q_reg_n_0_[25]\, + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[27]_i_4__0_n_0\ ); -\next_mi_addr[27]_i_5\: unisim.vcomponents.LUT5 +\next_mi_addr[27]_i_5__0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(24), + I0 => next_mi_addr(24), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(24), - O => \next_mi_addr[27]_i_5_n_0\ + I2 => \S_AXI_AADDR_Q_reg_n_0_[24]\, + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[27]_i_5__0_n_0\ ); -\next_mi_addr[31]_i_2\: unisim.vcomponents.LUT5 +\next_mi_addr[31]_i_2__0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(31), + I0 => next_mi_addr(31), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(31), - O => \next_mi_addr[31]_i_2_n_0\ + I2 => \S_AXI_AADDR_Q_reg_n_0_[31]\, + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[31]_i_2__0_n_0\ ); -\next_mi_addr[31]_i_3\: unisim.vcomponents.LUT5 +\next_mi_addr[31]_i_3__0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(30), + I0 => next_mi_addr(30), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(30), - O => \next_mi_addr[31]_i_3_n_0\ + I2 => \S_AXI_AADDR_Q_reg_n_0_[30]\, + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[31]_i_3__0_n_0\ ); -\next_mi_addr[31]_i_4\: unisim.vcomponents.LUT5 +\next_mi_addr[31]_i_4__0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(29), + I0 => next_mi_addr(29), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(29), - O => \next_mi_addr[31]_i_4_n_0\ + I2 => \S_AXI_AADDR_Q_reg_n_0_[29]\, + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[31]_i_4__0_n_0\ ); -\next_mi_addr[31]_i_5\: unisim.vcomponents.LUT5 +\next_mi_addr[31]_i_5__0\: unisim.vcomponents.LUT5 generic map( - INIT => X"CAAA0AAA" + INIT => X"88F0F0F0" ) port map ( - I0 => S_AXI_AADDR_Q(28), + I0 => next_mi_addr(28), I1 => size_mask_q(31), - I2 => split_ongoing, - I3 => access_is_incr_q, - I4 => next_mi_addr(28), - O => \next_mi_addr[31]_i_5_n_0\ + I2 => \S_AXI_AADDR_Q_reg_n_0_[28]\, + I3 => split_ongoing, + I4 => access_is_incr_q, + O => \next_mi_addr[31]_i_5__0_n_0\ ); -\next_mi_addr[3]_i_2\: unisim.vcomponents.LUT6 +\next_mi_addr[3]_i_2__0\: unisim.vcomponents.LUT6 generic map( - INIT => X"1DDDE222E222E222" + INIT => X"1BBBE444E444E444" ) port map ( - I0 => S_AXI_AADDR_Q(3), - I1 => \next_mi_addr[3]_i_6_n_0\, - I2 => next_mi_addr(3), - I3 => size_mask_q(3), - I4 => \next_mi_addr[11]_i_6_n_0\, - I5 => first_step_q(3), - O => \next_mi_addr[3]_i_2_n_0\ - ); -\next_mi_addr[3]_i_3\: unisim.vcomponents.LUT6 + I0 => \M_AXI_AADDR_I1__0\, + I1 => \S_AXI_AADDR_Q_reg_n_0_[3]\, + I2 => size_mask_q(3), + I3 => next_mi_addr(3), + I4 => \first_split__2\, + I5 => \first_step_q_reg_n_0_[3]\, + O => \next_mi_addr[3]_i_2__0_n_0\ + ); +\next_mi_addr[3]_i_3__0\: unisim.vcomponents.LUT6 generic map( - INIT => X"1DDDE222E222E222" + INIT => X"1BBBE444E444E444" ) port map ( - I0 => S_AXI_AADDR_Q(2), - I1 => \next_mi_addr[3]_i_6_n_0\, - I2 => next_mi_addr(2), - I3 => size_mask_q(2), - I4 => \next_mi_addr[11]_i_6_n_0\, - I5 => first_step_q(2), - O => \next_mi_addr[3]_i_3_n_0\ - ); -\next_mi_addr[3]_i_4\: unisim.vcomponents.LUT6 + I0 => \M_AXI_AADDR_I1__0\, + I1 => \S_AXI_AADDR_Q_reg_n_0_[2]\, + I2 => size_mask_q(2), + I3 => next_mi_addr(2), + I4 => \first_split__2\, + I5 => \first_step_q_reg_n_0_[2]\, + O => \next_mi_addr[3]_i_3__0_n_0\ + ); +\next_mi_addr[3]_i_4__0\: unisim.vcomponents.LUT6 generic map( - INIT => X"1DDDE222E222E222" + INIT => X"1BBBE444E444E444" ) port map ( - I0 => S_AXI_AADDR_Q(1), - I1 => \next_mi_addr[3]_i_6_n_0\, - I2 => next_mi_addr(1), - I3 => size_mask_q(1), - I4 => \next_mi_addr[11]_i_6_n_0\, - I5 => first_step_q(1), - O => \next_mi_addr[3]_i_4_n_0\ - ); -\next_mi_addr[3]_i_5\: unisim.vcomponents.LUT6 + I0 => \M_AXI_AADDR_I1__0\, + I1 => \S_AXI_AADDR_Q_reg_n_0_[1]\, + I2 => size_mask_q(1), + I3 => next_mi_addr(1), + I4 => \first_split__2\, + I5 => \first_step_q_reg_n_0_[1]\, + O => \next_mi_addr[3]_i_4__0_n_0\ + ); +\next_mi_addr[3]_i_5__0\: unisim.vcomponents.LUT6 generic map( - INIT => X"1DDDE222E222E222" + INIT => X"1BBBE444E444E444" ) port map ( - I0 => S_AXI_AADDR_Q(0), - I1 => \next_mi_addr[3]_i_6_n_0\, - I2 => next_mi_addr(0), - I3 => size_mask_q(0), - I4 => \next_mi_addr[11]_i_6_n_0\, - I5 => first_step_q(0), - O => \next_mi_addr[3]_i_5_n_0\ - ); -\next_mi_addr[3]_i_6\: unisim.vcomponents.LUT2 + I0 => \M_AXI_AADDR_I1__0\, + I1 => \S_AXI_AADDR_Q_reg_n_0_[0]\, + I2 => size_mask_q(0), + I3 => next_mi_addr(0), + I4 => \first_split__2\, + I5 => \first_step_q_reg_n_0_[0]\, + O => \next_mi_addr[3]_i_5__0_n_0\ + ); +\next_mi_addr[3]_i_6__0\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( - I0 => access_is_incr_q, - I1 => split_ongoing, - O => \next_mi_addr[3]_i_6_n_0\ + I0 => split_ongoing, + I1 => access_is_incr_q, + O => \M_AXI_AADDR_I1__0\ ); \next_mi_addr[7]_i_2\: unisim.vcomponents.LUT4 generic map( - INIT => X"56A6" + INIT => X"569A" ) port map ( I0 => \^m_axi_araddr\(7), - I1 => addr_step_q(7), - I2 => \next_mi_addr[11]_i_6_n_0\, - I3 => first_step_q(7), + I1 => \first_split__2\, + I2 => \addr_step_q_reg_n_0_[7]\, + I3 => \first_step_q_reg_n_0_[7]\, O => \next_mi_addr[7]_i_2_n_0\ ); \next_mi_addr[7]_i_3\: unisim.vcomponents.LUT4 generic map( - INIT => X"56A6" + INIT => X"569A" ) port map ( I0 => \^m_axi_araddr\(6), - I1 => addr_step_q(6), - I2 => \next_mi_addr[11]_i_6_n_0\, - I3 => first_step_q(6), + I1 => \first_split__2\, + I2 => \addr_step_q_reg_n_0_[6]\, + I3 => \first_step_q_reg_n_0_[6]\, O => \next_mi_addr[7]_i_3_n_0\ ); \next_mi_addr[7]_i_4\: unisim.vcomponents.LUT4 generic map( - INIT => X"56A6" + INIT => X"569A" ) port map ( I0 => \^m_axi_araddr\(5), - I1 => addr_step_q(5), - I2 => \next_mi_addr[11]_i_6_n_0\, - I3 => first_step_q(5), + I1 => \first_split__2\, + I2 => \addr_step_q_reg_n_0_[5]\, + I3 => \first_step_q_reg_n_0_[5]\, O => \next_mi_addr[7]_i_4_n_0\ ); \next_mi_addr[7]_i_5\: unisim.vcomponents.LUT4 generic map( - INIT => X"56A6" + INIT => X"569A" ) port map ( I0 => \^m_axi_araddr\(4), - I1 => size_mask_q(0), - I2 => \next_mi_addr[11]_i_6_n_0\, - I3 => first_step_q(4), + I1 => \first_split__2\, + I2 => size_mask_q(0), + I3 => \first_step_q_reg_n_0_[4]\, O => \next_mi_addr[7]_i_5_n_0\ ); \next_mi_addr_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[3]_i_1_n_7\, + D => \next_mi_addr_reg[3]_i_1__0_n_7\, Q => next_mi_addr(0), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \next_mi_addr_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[11]_i_1_n_5\, + D => \next_mi_addr_reg[11]_i_1__0_n_5\, Q => next_mi_addr(10), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \next_mi_addr_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[11]_i_1_n_4\, + D => \next_mi_addr_reg[11]_i_1__0_n_4\, Q => next_mi_addr(11), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); -\next_mi_addr_reg[11]_i_1\: unisim.vcomponents.CARRY4 +\next_mi_addr_reg[11]_i_1__0\: unisim.vcomponents.CARRY4 port map ( - CI => \next_mi_addr_reg[7]_i_1_n_0\, - CO(3) => \next_mi_addr_reg[11]_i_1_n_0\, - CO(2) => \next_mi_addr_reg[11]_i_1_n_1\, - CO(1) => \next_mi_addr_reg[11]_i_1_n_2\, - CO(0) => \next_mi_addr_reg[11]_i_1_n_3\, + CI => \next_mi_addr_reg[7]_i_1__0_n_0\, + CO(3) => \next_mi_addr_reg[11]_i_1__0_n_0\, + CO(2) => \next_mi_addr_reg[11]_i_1__0_n_1\, + CO(1) => \next_mi_addr_reg[11]_i_1__0_n_2\, + CO(0) => \next_mi_addr_reg[11]_i_1__0_n_3\, CYINIT => '0', DI(3 downto 0) => \^m_axi_araddr\(11 downto 8), - O(3) => \next_mi_addr_reg[11]_i_1_n_4\, - O(2) => \next_mi_addr_reg[11]_i_1_n_5\, - O(1) => \next_mi_addr_reg[11]_i_1_n_6\, - O(0) => \next_mi_addr_reg[11]_i_1_n_7\, + O(3) => \next_mi_addr_reg[11]_i_1__0_n_4\, + O(2) => \next_mi_addr_reg[11]_i_1__0_n_5\, + O(1) => \next_mi_addr_reg[11]_i_1__0_n_6\, + O(0) => \next_mi_addr_reg[11]_i_1__0_n_7\, S(3) => \next_mi_addr[11]_i_2_n_0\, S(2) => \next_mi_addr[11]_i_3_n_0\, S(1) => \next_mi_addr[11]_i_4_n_0\, @@ -6650,342 +18871,342 @@ multiple_id_non_split_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[15]_i_1_n_7\, + D => \next_mi_addr_reg[15]_i_1__0_n_7\, Q => next_mi_addr(12), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \next_mi_addr_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[15]_i_1_n_6\, + D => \next_mi_addr_reg[15]_i_1__0_n_6\, Q => next_mi_addr(13), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \next_mi_addr_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[15]_i_1_n_5\, + D => \next_mi_addr_reg[15]_i_1__0_n_5\, Q => next_mi_addr(14), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \next_mi_addr_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[15]_i_1_n_4\, + D => \next_mi_addr_reg[15]_i_1__0_n_4\, Q => next_mi_addr(15), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); -\next_mi_addr_reg[15]_i_1\: unisim.vcomponents.CARRY4 +\next_mi_addr_reg[15]_i_1__0\: unisim.vcomponents.CARRY4 port map ( - CI => \next_mi_addr_reg[11]_i_1_n_0\, - CO(3) => \next_mi_addr_reg[15]_i_1_n_0\, - CO(2) => \next_mi_addr_reg[15]_i_1_n_1\, - CO(1) => \next_mi_addr_reg[15]_i_1_n_2\, - CO(0) => \next_mi_addr_reg[15]_i_1_n_3\, + CI => \next_mi_addr_reg[11]_i_1__0_n_0\, + CO(3) => \next_mi_addr_reg[15]_i_1__0_n_0\, + CO(2) => \next_mi_addr_reg[15]_i_1__0_n_1\, + CO(1) => \next_mi_addr_reg[15]_i_1__0_n_2\, + CO(0) => \next_mi_addr_reg[15]_i_1__0_n_3\, CYINIT => '0', - DI(3) => \next_mi_addr[15]_i_2_n_0\, - DI(2) => \next_mi_addr[15]_i_3_n_0\, - DI(1) => \next_mi_addr[15]_i_4_n_0\, - DI(0) => \next_mi_addr[15]_i_5_n_0\, - O(3) => \next_mi_addr_reg[15]_i_1_n_4\, - O(2) => \next_mi_addr_reg[15]_i_1_n_5\, - O(1) => \next_mi_addr_reg[15]_i_1_n_6\, - O(0) => \next_mi_addr_reg[15]_i_1_n_7\, - S(3) => \next_mi_addr[15]_i_6_n_0\, - S(2) => \next_mi_addr[15]_i_7_n_0\, - S(1) => \next_mi_addr[15]_i_8_n_0\, - S(0) => \next_mi_addr[15]_i_9_n_0\ + DI(3) => \next_mi_addr[15]_i_2__0_n_0\, + DI(2) => \next_mi_addr[15]_i_3__0_n_0\, + DI(1) => \next_mi_addr[15]_i_4__0_n_0\, + DI(0) => \next_mi_addr[15]_i_5__0_n_0\, + O(3) => \next_mi_addr_reg[15]_i_1__0_n_4\, + O(2) => \next_mi_addr_reg[15]_i_1__0_n_5\, + O(1) => \next_mi_addr_reg[15]_i_1__0_n_6\, + O(0) => \next_mi_addr_reg[15]_i_1__0_n_7\, + S(3) => \next_mi_addr[15]_i_6__0_n_0\, + S(2) => \next_mi_addr[15]_i_7__0_n_0\, + S(1) => \next_mi_addr[15]_i_8__0_n_0\, + S(0) => \next_mi_addr[15]_i_9__0_n_0\ ); \next_mi_addr_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[19]_i_1_n_7\, + D => \next_mi_addr_reg[19]_i_1__0_n_7\, Q => next_mi_addr(16), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \next_mi_addr_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[19]_i_1_n_6\, + D => \next_mi_addr_reg[19]_i_1__0_n_6\, Q => next_mi_addr(17), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \next_mi_addr_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[19]_i_1_n_5\, + D => \next_mi_addr_reg[19]_i_1__0_n_5\, Q => next_mi_addr(18), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \next_mi_addr_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[19]_i_1_n_4\, + D => \next_mi_addr_reg[19]_i_1__0_n_4\, Q => next_mi_addr(19), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); -\next_mi_addr_reg[19]_i_1\: unisim.vcomponents.CARRY4 +\next_mi_addr_reg[19]_i_1__0\: unisim.vcomponents.CARRY4 port map ( - CI => \next_mi_addr_reg[15]_i_1_n_0\, - CO(3) => \next_mi_addr_reg[19]_i_1_n_0\, - CO(2) => \next_mi_addr_reg[19]_i_1_n_1\, - CO(1) => \next_mi_addr_reg[19]_i_1_n_2\, - CO(0) => \next_mi_addr_reg[19]_i_1_n_3\, + CI => \next_mi_addr_reg[15]_i_1__0_n_0\, + CO(3) => \next_mi_addr_reg[19]_i_1__0_n_0\, + CO(2) => \next_mi_addr_reg[19]_i_1__0_n_1\, + CO(1) => \next_mi_addr_reg[19]_i_1__0_n_2\, + CO(0) => \next_mi_addr_reg[19]_i_1__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", - O(3) => \next_mi_addr_reg[19]_i_1_n_4\, - O(2) => \next_mi_addr_reg[19]_i_1_n_5\, - O(1) => \next_mi_addr_reg[19]_i_1_n_6\, - O(0) => \next_mi_addr_reg[19]_i_1_n_7\, - S(3) => \next_mi_addr[19]_i_2_n_0\, - S(2) => \next_mi_addr[19]_i_3_n_0\, - S(1) => \next_mi_addr[19]_i_4_n_0\, - S(0) => \next_mi_addr[19]_i_5_n_0\ + O(3) => \next_mi_addr_reg[19]_i_1__0_n_4\, + O(2) => \next_mi_addr_reg[19]_i_1__0_n_5\, + O(1) => \next_mi_addr_reg[19]_i_1__0_n_6\, + O(0) => \next_mi_addr_reg[19]_i_1__0_n_7\, + S(3) => \next_mi_addr[19]_i_2__0_n_0\, + S(2) => \next_mi_addr[19]_i_3__0_n_0\, + S(1) => \next_mi_addr[19]_i_4__0_n_0\, + S(0) => \next_mi_addr[19]_i_5__0_n_0\ ); \next_mi_addr_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[3]_i_1_n_6\, + D => \next_mi_addr_reg[3]_i_1__0_n_6\, Q => next_mi_addr(1), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \next_mi_addr_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[23]_i_1_n_7\, + D => \next_mi_addr_reg[23]_i_1__0_n_7\, Q => next_mi_addr(20), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \next_mi_addr_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[23]_i_1_n_6\, + D => \next_mi_addr_reg[23]_i_1__0_n_6\, Q => next_mi_addr(21), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \next_mi_addr_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[23]_i_1_n_5\, + D => \next_mi_addr_reg[23]_i_1__0_n_5\, Q => next_mi_addr(22), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \next_mi_addr_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[23]_i_1_n_4\, + D => \next_mi_addr_reg[23]_i_1__0_n_4\, Q => next_mi_addr(23), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); -\next_mi_addr_reg[23]_i_1\: unisim.vcomponents.CARRY4 +\next_mi_addr_reg[23]_i_1__0\: unisim.vcomponents.CARRY4 port map ( - CI => \next_mi_addr_reg[19]_i_1_n_0\, - CO(3) => \next_mi_addr_reg[23]_i_1_n_0\, - CO(2) => \next_mi_addr_reg[23]_i_1_n_1\, - CO(1) => \next_mi_addr_reg[23]_i_1_n_2\, - CO(0) => \next_mi_addr_reg[23]_i_1_n_3\, + CI => \next_mi_addr_reg[19]_i_1__0_n_0\, + CO(3) => \next_mi_addr_reg[23]_i_1__0_n_0\, + CO(2) => \next_mi_addr_reg[23]_i_1__0_n_1\, + CO(1) => \next_mi_addr_reg[23]_i_1__0_n_2\, + CO(0) => \next_mi_addr_reg[23]_i_1__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", - O(3) => \next_mi_addr_reg[23]_i_1_n_4\, - O(2) => \next_mi_addr_reg[23]_i_1_n_5\, - O(1) => \next_mi_addr_reg[23]_i_1_n_6\, - O(0) => \next_mi_addr_reg[23]_i_1_n_7\, - S(3) => \next_mi_addr[23]_i_2_n_0\, - S(2) => \next_mi_addr[23]_i_3_n_0\, - S(1) => \next_mi_addr[23]_i_4_n_0\, - S(0) => \next_mi_addr[23]_i_5_n_0\ + O(3) => \next_mi_addr_reg[23]_i_1__0_n_4\, + O(2) => \next_mi_addr_reg[23]_i_1__0_n_5\, + O(1) => \next_mi_addr_reg[23]_i_1__0_n_6\, + O(0) => \next_mi_addr_reg[23]_i_1__0_n_7\, + S(3) => \next_mi_addr[23]_i_2__0_n_0\, + S(2) => \next_mi_addr[23]_i_3__0_n_0\, + S(1) => \next_mi_addr[23]_i_4__0_n_0\, + S(0) => \next_mi_addr[23]_i_5__0_n_0\ ); \next_mi_addr_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[27]_i_1_n_7\, + D => \next_mi_addr_reg[27]_i_1__0_n_7\, Q => next_mi_addr(24), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \next_mi_addr_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[27]_i_1_n_6\, + D => \next_mi_addr_reg[27]_i_1__0_n_6\, Q => next_mi_addr(25), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \next_mi_addr_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[27]_i_1_n_5\, + D => \next_mi_addr_reg[27]_i_1__0_n_5\, Q => next_mi_addr(26), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \next_mi_addr_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[27]_i_1_n_4\, + D => \next_mi_addr_reg[27]_i_1__0_n_4\, Q => next_mi_addr(27), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); -\next_mi_addr_reg[27]_i_1\: unisim.vcomponents.CARRY4 +\next_mi_addr_reg[27]_i_1__0\: unisim.vcomponents.CARRY4 port map ( - CI => \next_mi_addr_reg[23]_i_1_n_0\, - CO(3) => \next_mi_addr_reg[27]_i_1_n_0\, - CO(2) => \next_mi_addr_reg[27]_i_1_n_1\, - CO(1) => \next_mi_addr_reg[27]_i_1_n_2\, - CO(0) => \next_mi_addr_reg[27]_i_1_n_3\, + CI => \next_mi_addr_reg[23]_i_1__0_n_0\, + CO(3) => \next_mi_addr_reg[27]_i_1__0_n_0\, + CO(2) => \next_mi_addr_reg[27]_i_1__0_n_1\, + CO(1) => \next_mi_addr_reg[27]_i_1__0_n_2\, + CO(0) => \next_mi_addr_reg[27]_i_1__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", - O(3) => \next_mi_addr_reg[27]_i_1_n_4\, - O(2) => \next_mi_addr_reg[27]_i_1_n_5\, - O(1) => \next_mi_addr_reg[27]_i_1_n_6\, - O(0) => \next_mi_addr_reg[27]_i_1_n_7\, - S(3) => \next_mi_addr[27]_i_2_n_0\, - S(2) => \next_mi_addr[27]_i_3_n_0\, - S(1) => \next_mi_addr[27]_i_4_n_0\, - S(0) => \next_mi_addr[27]_i_5_n_0\ + O(3) => \next_mi_addr_reg[27]_i_1__0_n_4\, + O(2) => \next_mi_addr_reg[27]_i_1__0_n_5\, + O(1) => \next_mi_addr_reg[27]_i_1__0_n_6\, + O(0) => \next_mi_addr_reg[27]_i_1__0_n_7\, + S(3) => \next_mi_addr[27]_i_2__0_n_0\, + S(2) => \next_mi_addr[27]_i_3__0_n_0\, + S(1) => \next_mi_addr[27]_i_4__0_n_0\, + S(0) => \next_mi_addr[27]_i_5__0_n_0\ ); \next_mi_addr_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[31]_i_1_n_7\, + D => \next_mi_addr_reg[31]_i_1__0_n_7\, Q => next_mi_addr(28), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \next_mi_addr_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[31]_i_1_n_6\, + D => \next_mi_addr_reg[31]_i_1__0_n_6\, Q => next_mi_addr(29), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \next_mi_addr_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[3]_i_1_n_5\, + D => \next_mi_addr_reg[3]_i_1__0_n_5\, Q => next_mi_addr(2), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \next_mi_addr_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[31]_i_1_n_5\, + D => \next_mi_addr_reg[31]_i_1__0_n_5\, Q => next_mi_addr(30), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \next_mi_addr_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[31]_i_1_n_4\, + D => \next_mi_addr_reg[31]_i_1__0_n_4\, Q => next_mi_addr(31), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); -\next_mi_addr_reg[31]_i_1\: unisim.vcomponents.CARRY4 +\next_mi_addr_reg[31]_i_1__0\: unisim.vcomponents.CARRY4 port map ( - CI => \next_mi_addr_reg[27]_i_1_n_0\, - CO(3) => \NLW_next_mi_addr_reg[31]_i_1_CO_UNCONNECTED\(3), - CO(2) => \next_mi_addr_reg[31]_i_1_n_1\, - CO(1) => \next_mi_addr_reg[31]_i_1_n_2\, - CO(0) => \next_mi_addr_reg[31]_i_1_n_3\, + CI => \next_mi_addr_reg[27]_i_1__0_n_0\, + CO(3) => \NLW_next_mi_addr_reg[31]_i_1__0_CO_UNCONNECTED\(3), + CO(2) => \next_mi_addr_reg[31]_i_1__0_n_1\, + CO(1) => \next_mi_addr_reg[31]_i_1__0_n_2\, + CO(0) => \next_mi_addr_reg[31]_i_1__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", - O(3) => \next_mi_addr_reg[31]_i_1_n_4\, - O(2) => \next_mi_addr_reg[31]_i_1_n_5\, - O(1) => \next_mi_addr_reg[31]_i_1_n_6\, - O(0) => \next_mi_addr_reg[31]_i_1_n_7\, - S(3) => \next_mi_addr[31]_i_2_n_0\, - S(2) => \next_mi_addr[31]_i_3_n_0\, - S(1) => \next_mi_addr[31]_i_4_n_0\, - S(0) => \next_mi_addr[31]_i_5_n_0\ + O(3) => \next_mi_addr_reg[31]_i_1__0_n_4\, + O(2) => \next_mi_addr_reg[31]_i_1__0_n_5\, + O(1) => \next_mi_addr_reg[31]_i_1__0_n_6\, + O(0) => \next_mi_addr_reg[31]_i_1__0_n_7\, + S(3) => \next_mi_addr[31]_i_2__0_n_0\, + S(2) => \next_mi_addr[31]_i_3__0_n_0\, + S(1) => \next_mi_addr[31]_i_4__0_n_0\, + S(0) => \next_mi_addr[31]_i_5__0_n_0\ ); \next_mi_addr_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[3]_i_1_n_4\, + D => \next_mi_addr_reg[3]_i_1__0_n_4\, Q => next_mi_addr(3), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); -\next_mi_addr_reg[3]_i_1\: unisim.vcomponents.CARRY4 +\next_mi_addr_reg[3]_i_1__0\: unisim.vcomponents.CARRY4 port map ( CI => '0', - CO(3) => \next_mi_addr_reg[3]_i_1_n_0\, - CO(2) => \next_mi_addr_reg[3]_i_1_n_1\, - CO(1) => \next_mi_addr_reg[3]_i_1_n_2\, - CO(0) => \next_mi_addr_reg[3]_i_1_n_3\, + CO(3) => \next_mi_addr_reg[3]_i_1__0_n_0\, + CO(2) => \next_mi_addr_reg[3]_i_1__0_n_1\, + CO(1) => \next_mi_addr_reg[3]_i_1__0_n_2\, + CO(0) => \next_mi_addr_reg[3]_i_1__0_n_3\, CYINIT => '0', DI(3 downto 0) => \^m_axi_araddr\(3 downto 0), - O(3) => \next_mi_addr_reg[3]_i_1_n_4\, - O(2) => \next_mi_addr_reg[3]_i_1_n_5\, - O(1) => \next_mi_addr_reg[3]_i_1_n_6\, - O(0) => \next_mi_addr_reg[3]_i_1_n_7\, - S(3) => \next_mi_addr[3]_i_2_n_0\, - S(2) => \next_mi_addr[3]_i_3_n_0\, - S(1) => \next_mi_addr[3]_i_4_n_0\, - S(0) => \next_mi_addr[3]_i_5_n_0\ + O(3) => \next_mi_addr_reg[3]_i_1__0_n_4\, + O(2) => \next_mi_addr_reg[3]_i_1__0_n_5\, + O(1) => \next_mi_addr_reg[3]_i_1__0_n_6\, + O(0) => \next_mi_addr_reg[3]_i_1__0_n_7\, + S(3) => \next_mi_addr[3]_i_2__0_n_0\, + S(2) => \next_mi_addr[3]_i_3__0_n_0\, + S(1) => \next_mi_addr[3]_i_4__0_n_0\, + S(0) => \next_mi_addr[3]_i_5__0_n_0\ ); \next_mi_addr_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[7]_i_1_n_7\, + D => \next_mi_addr_reg[7]_i_1__0_n_7\, Q => next_mi_addr(4), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \next_mi_addr_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[7]_i_1_n_6\, + D => \next_mi_addr_reg[7]_i_1__0_n_6\, Q => next_mi_addr(5), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \next_mi_addr_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[7]_i_1_n_5\, + D => \next_mi_addr_reg[7]_i_1__0_n_5\, Q => next_mi_addr(6), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \next_mi_addr_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[7]_i_1_n_4\, + D => \next_mi_addr_reg[7]_i_1__0_n_4\, Q => next_mi_addr(7), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); -\next_mi_addr_reg[7]_i_1\: unisim.vcomponents.CARRY4 +\next_mi_addr_reg[7]_i_1__0\: unisim.vcomponents.CARRY4 port map ( - CI => \next_mi_addr_reg[3]_i_1_n_0\, - CO(3) => \next_mi_addr_reg[7]_i_1_n_0\, - CO(2) => \next_mi_addr_reg[7]_i_1_n_1\, - CO(1) => \next_mi_addr_reg[7]_i_1_n_2\, - CO(0) => \next_mi_addr_reg[7]_i_1_n_3\, + CI => \next_mi_addr_reg[3]_i_1__0_n_0\, + CO(3) => \next_mi_addr_reg[7]_i_1__0_n_0\, + CO(2) => \next_mi_addr_reg[7]_i_1__0_n_1\, + CO(1) => \next_mi_addr_reg[7]_i_1__0_n_2\, + CO(0) => \next_mi_addr_reg[7]_i_1__0_n_3\, CYINIT => '0', DI(3 downto 0) => \^m_axi_araddr\(7 downto 4), - O(3) => \next_mi_addr_reg[7]_i_1_n_4\, - O(2) => \next_mi_addr_reg[7]_i_1_n_5\, - O(1) => \next_mi_addr_reg[7]_i_1_n_6\, - O(0) => \next_mi_addr_reg[7]_i_1_n_7\, + O(3) => \next_mi_addr_reg[7]_i_1__0_n_4\, + O(2) => \next_mi_addr_reg[7]_i_1__0_n_5\, + O(1) => \next_mi_addr_reg[7]_i_1__0_n_6\, + O(0) => \next_mi_addr_reg[7]_i_1__0_n_7\, S(3) => \next_mi_addr[7]_i_2_n_0\, S(2) => \next_mi_addr[7]_i_3_n_0\, S(1) => \next_mi_addr[7]_i_4_n_0\, @@ -6995,138 +19216,138 @@ multiple_id_non_split_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[11]_i_1_n_7\, + D => \next_mi_addr_reg[11]_i_1__0_n_7\, Q => next_mi_addr(8), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \next_mi_addr_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \next_mi_addr_reg[11]_i_1_n_6\, + D => \next_mi_addr_reg[11]_i_1__0_n_6\, Q => next_mi_addr(9), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \num_transactions_q_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_arlen(4), - Q => num_transactions_q(0), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \num_transactions_q_reg_n_0_[0]\, + R => aresetn_0 ); \num_transactions_q_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_arlen(5), - Q => num_transactions_q(1), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \num_transactions_q_reg_n_0_[1]\, + R => aresetn_0 ); \num_transactions_q_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_arlen(6), - Q => num_transactions_q(2), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \num_transactions_q_reg_n_0_[2]\, + R => aresetn_0 ); \num_transactions_q_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), D => s_axi_arlen(7), - Q => num_transactions_q(3), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + Q => \num_transactions_q_reg_n_0_[3]\, + R => aresetn_0 ); -\pushed_commands[0]_i_1\: unisim.vcomponents.LUT1 +\pushed_commands[0]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \pushed_commands_reg__0\(0), - O => p_0_in(0) + O => \p_0_in__0\(0) ); -\pushed_commands[1]_i_1\: unisim.vcomponents.LUT2 +\pushed_commands[1]_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( - I0 => \pushed_commands_reg__0\(1), - I1 => \pushed_commands_reg__0\(0), - O => p_0_in(1) + I0 => \pushed_commands_reg__0\(0), + I1 => \pushed_commands_reg__0\(1), + O => \p_0_in__0\(1) ); -\pushed_commands[2]_i_1\: unisim.vcomponents.LUT3 +\pushed_commands[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => X"6A" + INIT => X"78" ) port map ( - I0 => \pushed_commands_reg__0\(2), - I1 => \pushed_commands_reg__0\(0), - I2 => \pushed_commands_reg__0\(1), - O => p_0_in(2) + I0 => \pushed_commands_reg__0\(0), + I1 => \pushed_commands_reg__0\(1), + I2 => \pushed_commands_reg__0\(2), + O => \p_0_in__0\(2) ); -\pushed_commands[3]_i_1\: unisim.vcomponents.LUT2 +\pushed_commands[3]_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^e\(0), I1 => aresetn, - O => \pushed_commands[3]_i_1_n_0\ + O => \pushed_commands[3]_i_1__0_n_0\ ); -\pushed_commands[3]_i_2\: unisim.vcomponents.LUT4 +\pushed_commands[3]_i_2__0\: unisim.vcomponents.LUT4 generic map( - INIT => X"6AAA" + INIT => X"7F80" ) port map ( - I0 => \pushed_commands_reg__0\(3), - I1 => \pushed_commands_reg__0\(1), - I2 => \pushed_commands_reg__0\(0), - I3 => \pushed_commands_reg__0\(2), - O => p_0_in(3) + I0 => \pushed_commands_reg__0\(1), + I1 => \pushed_commands_reg__0\(0), + I2 => \pushed_commands_reg__0\(2), + I3 => \pushed_commands_reg__0\(3), + O => \p_0_in__0\(3) ); \pushed_commands_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => p_0_in(0), + D => \p_0_in__0\(0), Q => \pushed_commands_reg__0\(0), - R => \pushed_commands[3]_i_1_n_0\ + R => \pushed_commands[3]_i_1__0_n_0\ ); \pushed_commands_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => p_0_in(1), + D => \p_0_in__0\(1), Q => \pushed_commands_reg__0\(1), - R => \pushed_commands[3]_i_1_n_0\ + R => \pushed_commands[3]_i_1__0_n_0\ ); \pushed_commands_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => p_0_in(2), + D => \p_0_in__0\(2), Q => \pushed_commands_reg__0\(2), - R => \pushed_commands[3]_i_1_n_0\ + R => \pushed_commands[3]_i_1__0_n_0\ ); \pushed_commands_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => p_0_in(3), + D => \p_0_in__0\(3), Q => \pushed_commands_reg__0\(3), - R => \pushed_commands[3]_i_1_n_0\ + R => \pushed_commands[3]_i_1__0_n_0\ ); \queue_id_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', - D => \USE_R_CHANNEL.cmd_queue_n_18\, - Q => queue_id, - R => \USE_R_CHANNEL.cmd_queue_n_0\ + D => \USE_R_CHANNEL.cmd_queue_n_17\, + Q => \queue_id_reg_n_0_[0]\, + R => aresetn_0 ); -\size_mask_q[0]_i_1\: unisim.vcomponents.LUT3 +\size_mask_q[0]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"01" ) @@ -7134,18 +19355,18 @@ multiple_id_non_split_reg: unisim.vcomponents.FDRE I0 => s_axi_arsize(2), I1 => s_axi_arsize(0), I2 => s_axi_arsize(1), - O => size_mask(0) + O => \size_mask_q[0]_i_1__0_n_0\ ); -\size_mask_q[1]_i_1\: unisim.vcomponents.LUT2 +\size_mask_q[1]_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => s_axi_arsize(2), I1 => s_axi_arsize(1), - O => size_mask(1) + O => \size_mask_q[1]_i_1__0_n_0\ ); -\size_mask_q[2]_i_1\: unisim.vcomponents.LUT3 +\size_mask_q[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"07" ) @@ -7153,17 +19374,17 @@ multiple_id_non_split_reg: unisim.vcomponents.FDRE I0 => s_axi_arsize(0), I1 => s_axi_arsize(1), I2 => s_axi_arsize(2), - O => size_mask(2) + O => \size_mask_q[2]_i_1__0_n_0\ ); -\size_mask_q[3]_i_1\: unisim.vcomponents.LUT1 +\size_mask_q[3]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => s_axi_arsize(2), - O => size_mask(3) + O => \size_mask_q[3]_i_1__0_n_0\ ); -\size_mask_q[4]_i_1\: unisim.vcomponents.LUT3 +\size_mask_q[4]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"57" ) @@ -7171,18 +19392,18 @@ multiple_id_non_split_reg: unisim.vcomponents.FDRE I0 => s_axi_arsize(2), I1 => s_axi_arsize(0), I2 => s_axi_arsize(1), - O => size_mask(4) + O => \size_mask_q[4]_i_1__0_n_0\ ); -\size_mask_q[5]_i_1\: unisim.vcomponents.LUT2 +\size_mask_q[5]_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => s_axi_arsize(2), I1 => s_axi_arsize(1), - O => size_mask(5) + O => \size_mask_q[5]_i_1__0_n_0\ ); -\size_mask_q[6]_i_1\: unisim.vcomponents.LUT3 +\size_mask_q[6]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) @@ -7190,31 +19411,31 @@ multiple_id_non_split_reg: unisim.vcomponents.FDRE I0 => s_axi_arsize(2), I1 => s_axi_arsize(0), I2 => s_axi_arsize(1), - O => size_mask(6) + O => \size_mask_q[6]_i_1__0_n_0\ ); \size_mask_q_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), - D => size_mask(0), + D => \size_mask_q[0]_i_1__0_n_0\, Q => size_mask_q(0), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \size_mask_q_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), - D => size_mask(1), + D => \size_mask_q[1]_i_1__0_n_0\, Q => size_mask_q(1), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \size_mask_q_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), - D => size_mask(2), + D => \size_mask_q[2]_i_1__0_n_0\, Q => size_mask_q(2), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \size_mask_q_reg[31]\: unisim.vcomponents.FDRE port map ( @@ -7222,55 +19443,57 @@ multiple_id_non_split_reg: unisim.vcomponents.FDRE CE => \^e\(0), D => '1', Q => size_mask_q(31), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \size_mask_q_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), - D => size_mask(3), + D => \size_mask_q[3]_i_1__0_n_0\, Q => size_mask_q(3), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \size_mask_q_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), - D => size_mask(4), + D => \size_mask_q[4]_i_1__0_n_0\, Q => size_mask_q(4), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \size_mask_q_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), - D => size_mask(5), + D => \size_mask_q[5]_i_1__0_n_0\, Q => size_mask_q(5), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); \size_mask_q_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^e\(0), - D => size_mask(6), + D => \size_mask_q[6]_i_1__0_n_0\, Q => size_mask_q(6), - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); -split_in_progress_i_2: unisim.vcomponents.LUT3 +split_in_progress_i_2: unisim.vcomponents.LUT5 generic map( - INIT => X"EB" + INIT => X"44444004" ) port map ( - I0 => cmd_empty, - I1 => \^m_axi_arid\(0), - I2 => queue_id, - O => split_in_progress_i_2_n_0 + I0 => multiple_id_non_split, + I1 => need_to_split_q, + I2 => \queue_id_reg_n_0_[0]\, + I3 => \^m_axi_arid[0]\, + I4 => cmd_empty, + O => \allow_split_cmd__1\ ); split_in_progress_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', - D => \USE_R_CHANNEL.cmd_queue_n_21\, + D => \USE_R_CHANNEL.cmd_queue_n_20\, Q => split_in_progress_reg_n_0, R => '0' ); @@ -7278,9 +19501,9 @@ split_ongoing_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => pushed_new_cmd, - D => \USE_R_CHANNEL.cmd_queue_n_1\, + D => \USE_R_CHANNEL.cmd_queue_n_0\, Q => split_ongoing, - R => \USE_R_CHANNEL.cmd_queue_n_0\ + R => aresetn_0 ); end STRUCTURE; library IEEE; @@ -7289,23 +19512,58 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi3_conv is port ( - s_axi_arready : out STD_LOGIC; + m_axi_awvalid : out STD_LOGIC; M_AXI_ARID : out STD_LOGIC_VECTOR ( 0 to 0 ); + M_AXI_AWID : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awready : out STD_LOGIC; + s_axi_arready : out STD_LOGIC; + m_axi_wvalid : out STD_LOGIC; + m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rready : out STD_LOGIC; + s_axi_rvalid : out STD_LOGIC; + m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rlast : out STD_LOGIC; + m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wready : out STD_LOGIC; + m_axi_wlast : out STD_LOGIC; m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_bvalid : out STD_LOGIC; m_axi_arvalid : out STD_LOGIC; - s_axi_rvalid : out STD_LOGIC; - m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); - m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_rlast : out STD_LOGIC; - m_axi_rready : out STD_LOGIC; + m_axi_bready : out STD_LOGIC; + m_axi_bvalid : in STD_LOGIC; + s_axi_bready : in STD_LOGIC; + aresetn : in STD_LOGIC; + s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_wvalid : in STD_LOGIC; + m_axi_rvalid : in STD_LOGIC; + s_axi_rready : in STD_LOGIC; + m_axi_rlast : in STD_LOGIC; + m_axi_arready : in STD_LOGIC; aclk : in STD_LOGIC; + s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); @@ -7313,26 +19571,39 @@ entity Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi3_conv is s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); - m_axi_arready : in STD_LOGIC; - m_axi_rlast : in STD_LOGIC; - s_axi_rready : in STD_LOGIC; - m_axi_rvalid : in STD_LOGIC; - aresetn : in STD_LOGIC; + m_axi_awready : in STD_LOGIC; + m_axi_wready : in STD_LOGIC; + m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awvalid : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC ); end Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi3_conv; architecture STRUCTURE of Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi3_conv is + signal \USE_BURSTS.cmd_queue/inst/empty\ : STD_LOGIC; + signal \USE_WRITE.write_addr_inst_n_23\ : STD_LOGIC; + signal \USE_WRITE.write_addr_inst_n_6\ : STD_LOGIC; + signal areset_d : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal last_word : STD_LOGIC; + signal \^s_axi_wready\ : STD_LOGIC; + signal wr_cmd_b_repeat : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal wr_cmd_b_split : STD_LOGIC; + signal wr_cmd_length : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal wr_cmd_ready : STD_LOGIC; begin -\USE_READ.USE_SPLIT_R.read_addr_inst\: entity work.Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_a_axi3_conv + s_axi_wready <= \^s_axi_wready\; +\USE_READ.USE_SPLIT_R.read_addr_inst\: entity work.\Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_a_axi3_conv__parameterized0\ port map ( E(0) => s_axi_arready, - M_AXI_ARID(0) => M_AXI_ARID(0), aclk => aclk, + areset_d(1 downto 0) => areset_d(1 downto 0), + \areset_d_reg[1]\ => \USE_WRITE.write_addr_inst_n_23\, aresetn => aresetn, + aresetn_0 => \USE_WRITE.write_addr_inst_n_6\, m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0), m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0), m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0), + \m_axi_arid[0]\ => M_AXI_ARID(0), m_axi_arlen(3 downto 0) => m_axi_arlen(3 downto 0), m_axi_arlock(0) => m_axi_arlock(0), m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0), @@ -7357,6 +19628,75 @@ begin s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid ); +\USE_WRITE.USE_SPLIT_W.write_resp_inst\: entity work.Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_b_downsizer + port map ( + aclk => aclk, + aresetn => \USE_WRITE.write_addr_inst_n_6\, + dout(4) => wr_cmd_b_split, + dout(3 downto 0) => wr_cmd_b_repeat(3 downto 0), + last_word => last_word, + m_axi_bready => m_axi_bready, + m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), + m_axi_bvalid => m_axi_bvalid, + s_axi_bready => s_axi_bready, + s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0), + s_axi_bvalid => s_axi_bvalid + ); +\USE_WRITE.write_addr_inst\: entity work.Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_a_axi3_conv + port map ( + E(0) => s_axi_awready, + \S_AXI_BRESP_ACC_reg[0]\(4) => wr_cmd_b_split, + \S_AXI_BRESP_ACC_reg[0]\(3 downto 0) => wr_cmd_b_repeat(3 downto 0), + aclk => aclk, + areset_d(1 downto 0) => areset_d(1 downto 0), + aresetn => aresetn, + command_ongoing_reg_0 => \USE_WRITE.write_addr_inst_n_23\, + din(4) => M_AXI_AWID(0), + din(3 downto 0) => m_axi_awlen(3 downto 0), + dout(4) => m_axi_wid(0), + dout(3 downto 0) => wr_cmd_length(3 downto 0), + empty => \USE_BURSTS.cmd_queue/inst/empty\, + last_word => last_word, + m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0), + m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0), + m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0), + m_axi_awlock(0) => m_axi_awlock(0), + m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0), + m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0), + m_axi_awready => m_axi_awready, + m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0), + m_axi_awvalid => m_axi_awvalid, + m_axi_bvalid => m_axi_bvalid, + m_axi_wready => m_axi_wready, + m_axi_wvalid => m_axi_wvalid, + \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ => \USE_WRITE.write_addr_inst_n_6\, + s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), + s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), + s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0), + s_axi_awid(0) => s_axi_awid(0), + s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0), + s_axi_awlock(0) => s_axi_awlock(0), + s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), + s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0), + s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0), + s_axi_awvalid => s_axi_awvalid, + s_axi_bready => s_axi_bready, + s_axi_wready => \^s_axi_wready\, + s_axi_wvalid => s_axi_wvalid, + wr_cmd_ready => wr_cmd_ready + ); +\USE_WRITE.write_data_inst\: entity work.Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_w_axi3_conv + port map ( + aclk => aclk, + aresetn => \USE_WRITE.write_addr_inst_n_6\, + dout(3 downto 0) => wr_cmd_length(3 downto 0), + empty => \USE_BURSTS.cmd_queue/inst/empty\, + empty_fwft_i_reg => \^s_axi_wready\, + m_axi_wlast => m_axi_wlast, + m_axi_wready => m_axi_wready, + s_axi_wvalid => s_axi_wvalid, + wr_cmd_ready => wr_cmd_ready + ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; @@ -7476,13 +19816,13 @@ entity Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converte attribute C_AXI_SUPPORTS_USER_SIGNALS : integer; attribute C_AXI_SUPPORTS_USER_SIGNALS of Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 0; attribute C_AXI_SUPPORTS_WRITE : integer; - attribute C_AXI_SUPPORTS_WRITE of Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 0; + attribute C_AXI_SUPPORTS_WRITE of Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1; attribute C_AXI_WUSER_WIDTH : integer; attribute C_AXI_WUSER_WIDTH of Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1; attribute C_FAMILY : string; attribute C_FAMILY of Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is "zynq"; attribute C_IGNORE_ID : integer; - attribute C_IGNORE_ID of Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1; + attribute C_IGNORE_ID of Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 0; attribute C_M_AXI_PROTOCOL : integer; attribute C_M_AXI_PROTOCOL of Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1; attribute C_S_AXI_PROTOCOL : integer; @@ -7514,15 +19854,22 @@ end Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter; architecture STRUCTURE of Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter is signal \\ : STD_LOGIC; signal \^m_axi_arlock\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^m_axi_awlock\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^m_axi_bid\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^m_axi_rdata\ : STD_LOGIC_VECTOR ( 63 downto 0 ); signal \^m_axi_rid\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^m_axi_rresp\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_axi_ruser\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 7 downto 0 ); begin + \^m_axi_bid\(0) <= m_axi_bid(0); \^m_axi_rdata\(63 downto 0) <= m_axi_rdata(63 downto 0); \^m_axi_rid\(0) <= m_axi_rid(0); \^m_axi_rresp\(1 downto 0) <= m_axi_rresp(1 downto 0); \^m_axi_ruser\(0) <= m_axi_ruser(0); + \^s_axi_wdata\(63 downto 0) <= s_axi_wdata(63 downto 0); + \^s_axi_wstrb\(7 downto 0) <= s_axi_wstrb(7 downto 0); m_axi_arlock(1) <= \\; m_axi_arlock(0) <= \^m_axi_arlock\(0); m_axi_arregion(3) <= \\; @@ -7530,155 +19877,22 @@ begin m_axi_arregion(1) <= \\; m_axi_arregion(0) <= \\; m_axi_aruser(0) <= \\; - m_axi_awaddr(31) <= \\; - m_axi_awaddr(30) <= \\; - m_axi_awaddr(29) <= \\; - m_axi_awaddr(28) <= \\; - m_axi_awaddr(27) <= \\; - m_axi_awaddr(26) <= \\; - m_axi_awaddr(25) <= \\; - m_axi_awaddr(24) <= \\; - m_axi_awaddr(23) <= \\; - m_axi_awaddr(22) <= \\; - m_axi_awaddr(21) <= \\; - m_axi_awaddr(20) <= \\; - m_axi_awaddr(19) <= \\; - m_axi_awaddr(18) <= \\; - m_axi_awaddr(17) <= \\; - m_axi_awaddr(16) <= \\; - m_axi_awaddr(15) <= \\; - m_axi_awaddr(14) <= \\; - m_axi_awaddr(13) <= \\; - m_axi_awaddr(12) <= \\; - m_axi_awaddr(11) <= \\; - m_axi_awaddr(10) <= \\; - m_axi_awaddr(9) <= \\; - m_axi_awaddr(8) <= \\; - m_axi_awaddr(7) <= \\; - m_axi_awaddr(6) <= \\; - m_axi_awaddr(5) <= \\; - m_axi_awaddr(4) <= \\; - m_axi_awaddr(3) <= \\; - m_axi_awaddr(2) <= \\; - m_axi_awaddr(1) <= \\; - m_axi_awaddr(0) <= \\; - m_axi_awburst(1) <= \\; - m_axi_awburst(0) <= \\; - m_axi_awcache(3) <= \\; - m_axi_awcache(2) <= \\; - m_axi_awcache(1) <= \\; - m_axi_awcache(0) <= \\; - m_axi_awid(0) <= \\; - m_axi_awlen(3) <= \\; - m_axi_awlen(2) <= \\; - m_axi_awlen(1) <= \\; - m_axi_awlen(0) <= \\; m_axi_awlock(1) <= \\; - m_axi_awlock(0) <= \\; - m_axi_awprot(2) <= \\; - m_axi_awprot(1) <= \\; - m_axi_awprot(0) <= \\; - m_axi_awqos(3) <= \\; - m_axi_awqos(2) <= \\; - m_axi_awqos(1) <= \\; - m_axi_awqos(0) <= \\; + m_axi_awlock(0) <= \^m_axi_awlock\(0); m_axi_awregion(3) <= \\; m_axi_awregion(2) <= \\; m_axi_awregion(1) <= \\; m_axi_awregion(0) <= \\; - m_axi_awsize(2) <= \\; - m_axi_awsize(1) <= \\; - m_axi_awsize(0) <= \\; m_axi_awuser(0) <= \\; - m_axi_awvalid <= \\; - m_axi_bready <= \\; - m_axi_wdata(63) <= \\; - m_axi_wdata(62) <= \\; - m_axi_wdata(61) <= \\; - m_axi_wdata(60) <= \\; - m_axi_wdata(59) <= \\; - m_axi_wdata(58) <= \\; - m_axi_wdata(57) <= \\; - m_axi_wdata(56) <= \\; - m_axi_wdata(55) <= \\; - m_axi_wdata(54) <= \\; - m_axi_wdata(53) <= \\; - m_axi_wdata(52) <= \\; - m_axi_wdata(51) <= \\; - m_axi_wdata(50) <= \\; - m_axi_wdata(49) <= \\; - m_axi_wdata(48) <= \\; - m_axi_wdata(47) <= \\; - m_axi_wdata(46) <= \\; - m_axi_wdata(45) <= \\; - m_axi_wdata(44) <= \\; - m_axi_wdata(43) <= \\; - m_axi_wdata(42) <= \\; - m_axi_wdata(41) <= \\; - m_axi_wdata(40) <= \\; - m_axi_wdata(39) <= \\; - m_axi_wdata(38) <= \\; - m_axi_wdata(37) <= \\; - m_axi_wdata(36) <= \\; - m_axi_wdata(35) <= \\; - m_axi_wdata(34) <= \\; - m_axi_wdata(33) <= \\; - m_axi_wdata(32) <= \\; - m_axi_wdata(31) <= \\; - m_axi_wdata(30) <= \\; - m_axi_wdata(29) <= \\; - m_axi_wdata(28) <= \\; - m_axi_wdata(27) <= \\; - m_axi_wdata(26) <= \\; - m_axi_wdata(25) <= \\; - m_axi_wdata(24) <= \\; - m_axi_wdata(23) <= \\; - m_axi_wdata(22) <= \\; - m_axi_wdata(21) <= \\; - m_axi_wdata(20) <= \\; - m_axi_wdata(19) <= \\; - m_axi_wdata(18) <= \\; - m_axi_wdata(17) <= \\; - m_axi_wdata(16) <= \\; - m_axi_wdata(15) <= \\; - m_axi_wdata(14) <= \\; - m_axi_wdata(13) <= \\; - m_axi_wdata(12) <= \\; - m_axi_wdata(11) <= \\; - m_axi_wdata(10) <= \\; - m_axi_wdata(9) <= \\; - m_axi_wdata(8) <= \\; - m_axi_wdata(7) <= \\; - m_axi_wdata(6) <= \\; - m_axi_wdata(5) <= \\; - m_axi_wdata(4) <= \\; - m_axi_wdata(3) <= \\; - m_axi_wdata(2) <= \\; - m_axi_wdata(1) <= \\; - m_axi_wdata(0) <= \\; - m_axi_wid(0) <= \\; - m_axi_wlast <= \\; - m_axi_wstrb(7) <= \\; - m_axi_wstrb(6) <= \\; - m_axi_wstrb(5) <= \\; - m_axi_wstrb(4) <= \\; - m_axi_wstrb(3) <= \\; - m_axi_wstrb(2) <= \\; - m_axi_wstrb(1) <= \\; - m_axi_wstrb(0) <= \\; + m_axi_wdata(63 downto 0) <= \^s_axi_wdata\(63 downto 0); + m_axi_wstrb(7 downto 0) <= \^s_axi_wstrb\(7 downto 0); m_axi_wuser(0) <= \\; - m_axi_wvalid <= \\; - s_axi_awready <= \\; - s_axi_bid(0) <= \\; - s_axi_bresp(1) <= \\; - s_axi_bresp(0) <= \\; + s_axi_bid(0) <= \^m_axi_bid\(0); s_axi_buser(0) <= \\; - s_axi_bvalid <= \\; s_axi_rdata(63 downto 0) <= \^m_axi_rdata\(63 downto 0); s_axi_rid(0) <= \^m_axi_rid\(0); s_axi_rresp(1 downto 0) <= \^m_axi_rresp\(1 downto 0); s_axi_ruser(0) <= \^m_axi_ruser\(0); - s_axi_wready <= \\; GND: unisim.vcomponents.GND port map ( G => \\ @@ -7686,6 +19900,7 @@ GND: unisim.vcomponents.GND \gen_axi4_axi3.axi3_conv_inst\: entity work.Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi3_conv port map ( M_AXI_ARID(0) => m_axi_arid(0), + M_AXI_AWID(0) => m_axi_awid(0), aclk => aclk, aresetn => aresetn, m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0), @@ -7698,9 +19913,26 @@ GND: unisim.vcomponents.GND m_axi_arready => m_axi_arready, m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0), m_axi_arvalid => m_axi_arvalid, + m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0), + m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0), + m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0), + m_axi_awlen(3 downto 0) => m_axi_awlen(3 downto 0), + m_axi_awlock(0) => \^m_axi_awlock\(0), + m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0), + m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0), + m_axi_awready => m_axi_awready, + m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0), + m_axi_awvalid => m_axi_awvalid, + m_axi_bready => m_axi_bready, + m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), + m_axi_bvalid => m_axi_bvalid, m_axi_rlast => m_axi_rlast, m_axi_rready => m_axi_rready, m_axi_rvalid => m_axi_rvalid, + m_axi_wid(0) => m_axi_wid(0), + m_axi_wlast => m_axi_wlast, + m_axi_wready => m_axi_wready, + m_axi_wvalid => m_axi_wvalid, s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0), @@ -7712,9 +19944,25 @@ GND: unisim.vcomponents.GND s_axi_arready => s_axi_arready, s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0), s_axi_arvalid => s_axi_arvalid, + s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), + s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), + s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0), + s_axi_awid(0) => s_axi_awid(0), + s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0), + s_axi_awlock(0) => s_axi_awlock(0), + s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), + s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0), + s_axi_awready => s_axi_awready, + s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0), + s_axi_awvalid => s_axi_awvalid, + s_axi_bready => s_axi_bready, + s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0), + s_axi_bvalid => s_axi_bvalid, s_axi_rlast => s_axi_rlast, s_axi_rready => s_axi_rready, - s_axi_rvalid => s_axi_rvalid + s_axi_rvalid => s_axi_rvalid, + s_axi_wready => s_axi_wready, + s_axi_wvalid => s_axi_wvalid ); end STRUCTURE; library IEEE; @@ -7725,6 +19973,28 @@ entity Arty_Z7_20_auto_pc_0 is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; + s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_wlast : in STD_LOGIC; + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); @@ -7736,11 +20006,34 @@ entity Arty_Z7_20_auto_pc_0 is s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; + s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; + m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awvalid : out STD_LOGIC; + m_axi_awready : in STD_LOGIC; + m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_wlast : out STD_LOGIC; + m_axi_wvalid : out STD_LOGIC; + m_axi_wready : in STD_LOGIC; + m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_bvalid : in STD_LOGIC; + m_axi_bready : out STD_LOGIC; + m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); @@ -7751,6 +20044,7 @@ entity Arty_Z7_20_auto_pc_0 is m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; + m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rlast : in STD_LOGIC; @@ -7768,35 +20062,12 @@ entity Arty_Z7_20_auto_pc_0 is end Arty_Z7_20_auto_pc_0; architecture STRUCTURE of Arty_Z7_20_auto_pc_0 is - signal NLW_inst_m_axi_awvalid_UNCONNECTED : STD_LOGIC; - signal NLW_inst_m_axi_bready_UNCONNECTED : STD_LOGIC; - signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC; - signal NLW_inst_m_axi_wvalid_UNCONNECTED : STD_LOGIC; - signal NLW_inst_s_axi_awready_UNCONNECTED : STD_LOGIC; - signal NLW_inst_s_axi_bvalid_UNCONNECTED : STD_LOGIC; - signal NLW_inst_s_axi_wready_UNCONNECTED : STD_LOGIC; - signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal NLW_inst_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); - signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); attribute C_AXI_ADDR_WIDTH : integer; attribute C_AXI_ADDR_WIDTH of inst : label is 32; @@ -7817,19 +20088,20 @@ architecture STRUCTURE of Arty_Z7_20_auto_pc_0 is attribute C_AXI_SUPPORTS_USER_SIGNALS : integer; attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0; attribute C_AXI_SUPPORTS_WRITE : integer; - attribute C_AXI_SUPPORTS_WRITE of inst : label is 0; + attribute C_AXI_SUPPORTS_WRITE of inst : label is 1; attribute C_AXI_WUSER_WIDTH : integer; attribute C_AXI_WUSER_WIDTH of inst : label is 1; attribute C_FAMILY : string; attribute C_FAMILY of inst : label is "zynq"; attribute C_IGNORE_ID : integer; - attribute C_IGNORE_ID of inst : label is 1; + attribute C_IGNORE_ID of inst : label is 0; attribute C_M_AXI_PROTOCOL : integer; attribute C_M_AXI_PROTOCOL of inst : label is 1; attribute C_S_AXI_PROTOCOL : integer; attribute C_S_AXI_PROTOCOL of inst : label is 0; attribute C_TRANSLATION_MODE : integer; attribute C_TRANSLATION_MODE of inst : label is 2; + attribute DowngradeIPIdentifiedWarnings of inst : label is "yes"; attribute P_AXI3 : integer; attribute P_AXI3 of inst : label is 1; attribute P_AXI4 : integer; @@ -7848,7 +20120,6 @@ architecture STRUCTURE of Arty_Z7_20_auto_pc_0 is attribute P_PROTECTION of inst : label is 1; attribute P_SLVERR : string; attribute P_SLVERR of inst : label is "2'b10"; - attribute downgradeipidentifiedwarnings of inst : label is "yes"; begin inst: entity work.Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter port map ( @@ -7857,7 +20128,7 @@ inst: entity work.Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protoc m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0), m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0), m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0), - m_axi_arid(0) => NLW_inst_m_axi_arid_UNCONNECTED(0), + m_axi_arid(0) => m_axi_arid(0), m_axi_arlen(3 downto 0) => m_axi_arlen(3 downto 0), m_axi_arlock(1 downto 0) => m_axi_arlock(1 downto 0), m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0), @@ -7867,42 +20138,42 @@ inst: entity work.Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protoc m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0), m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0), m_axi_arvalid => m_axi_arvalid, - m_axi_awaddr(31 downto 0) => NLW_inst_m_axi_awaddr_UNCONNECTED(31 downto 0), - m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0), - m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0), - m_axi_awid(0) => NLW_inst_m_axi_awid_UNCONNECTED(0), - m_axi_awlen(3 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(3 downto 0), - m_axi_awlock(1 downto 0) => NLW_inst_m_axi_awlock_UNCONNECTED(1 downto 0), - m_axi_awprot(2 downto 0) => NLW_inst_m_axi_awprot_UNCONNECTED(2 downto 0), - m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0), - m_axi_awready => '0', + m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0), + m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0), + m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0), + m_axi_awid(0) => m_axi_awid(0), + m_axi_awlen(3 downto 0) => m_axi_awlen(3 downto 0), + m_axi_awlock(1 downto 0) => m_axi_awlock(1 downto 0), + m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0), + m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0), + m_axi_awready => m_axi_awready, m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0), - m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0), + m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0), m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0), - m_axi_awvalid => NLW_inst_m_axi_awvalid_UNCONNECTED, - m_axi_bid(0) => '0', - m_axi_bready => NLW_inst_m_axi_bready_UNCONNECTED, - m_axi_bresp(1 downto 0) => B"00", + m_axi_awvalid => m_axi_awvalid, + m_axi_bid(0) => m_axi_bid(0), + m_axi_bready => m_axi_bready, + m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), m_axi_buser(0) => '0', - m_axi_bvalid => '0', + m_axi_bvalid => m_axi_bvalid, m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0), - m_axi_rid(0) => '0', + m_axi_rid(0) => m_axi_rid(0), m_axi_rlast => m_axi_rlast, m_axi_rready => m_axi_rready, m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0), m_axi_ruser(0) => '0', m_axi_rvalid => m_axi_rvalid, - m_axi_wdata(63 downto 0) => NLW_inst_m_axi_wdata_UNCONNECTED(63 downto 0), - m_axi_wid(0) => NLW_inst_m_axi_wid_UNCONNECTED(0), - m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED, - m_axi_wready => '0', - m_axi_wstrb(7 downto 0) => NLW_inst_m_axi_wstrb_UNCONNECTED(7 downto 0), + m_axi_wdata(63 downto 0) => m_axi_wdata(63 downto 0), + m_axi_wid(0) => m_axi_wid(0), + m_axi_wlast => m_axi_wlast, + m_axi_wready => m_axi_wready, + m_axi_wstrb(7 downto 0) => m_axi_wstrb(7 downto 0), m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0), - m_axi_wvalid => NLW_inst_m_axi_wvalid_UNCONNECTED, + m_axi_wvalid => m_axi_wvalid, s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0), - s_axi_arid(0) => '0', + s_axi_arid(0) => s_axi_arid(0), s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0), s_axi_arlock(0) => s_axi_arlock(0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), @@ -7912,37 +20183,37 @@ inst: entity work.Arty_Z7_20_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protoc s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0), s_axi_aruser(0) => '0', s_axi_arvalid => s_axi_arvalid, - s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", - s_axi_awburst(1 downto 0) => B"01", - s_axi_awcache(3 downto 0) => B"0000", - s_axi_awid(0) => '0', - s_axi_awlen(7 downto 0) => B"00000000", - s_axi_awlock(0) => '0', - s_axi_awprot(2 downto 0) => B"000", - s_axi_awqos(3 downto 0) => B"0000", - s_axi_awready => NLW_inst_s_axi_awready_UNCONNECTED, - s_axi_awregion(3 downto 0) => B"0000", - s_axi_awsize(2 downto 0) => B"000", + s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), + s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), + s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0), + s_axi_awid(0) => s_axi_awid(0), + s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0), + s_axi_awlock(0) => s_axi_awlock(0), + s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), + s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0), + s_axi_awready => s_axi_awready, + s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0), + s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0), s_axi_awuser(0) => '0', - s_axi_awvalid => '0', - s_axi_bid(0) => NLW_inst_s_axi_bid_UNCONNECTED(0), - s_axi_bready => '0', - s_axi_bresp(1 downto 0) => NLW_inst_s_axi_bresp_UNCONNECTED(1 downto 0), + s_axi_awvalid => s_axi_awvalid, + s_axi_bid(0) => s_axi_bid(0), + s_axi_bready => s_axi_bready, + s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0), s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0), - s_axi_bvalid => NLW_inst_s_axi_bvalid_UNCONNECTED, + s_axi_bvalid => s_axi_bvalid, s_axi_rdata(63 downto 0) => s_axi_rdata(63 downto 0), - s_axi_rid(0) => NLW_inst_s_axi_rid_UNCONNECTED(0), + s_axi_rid(0) => s_axi_rid(0), s_axi_rlast => s_axi_rlast, s_axi_rready => s_axi_rready, s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0), s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0), s_axi_rvalid => s_axi_rvalid, - s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + s_axi_wdata(63 downto 0) => s_axi_wdata(63 downto 0), s_axi_wid(0) => '0', - s_axi_wlast => '1', - s_axi_wready => NLW_inst_s_axi_wready_UNCONNECTED, - s_axi_wstrb(7 downto 0) => B"11111111", + s_axi_wlast => s_axi_wlast, + s_axi_wready => s_axi_wready, + s_axi_wstrb(7 downto 0) => s_axi_wstrb(7 downto 0), s_axi_wuser(0) => '0', - s_axi_wvalid => '0' + s_axi_wvalid => s_axi_wvalid ); end STRUCTURE; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0_stub.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0_stub.v index d2920f8..7796bec 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0_stub.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0_stub.v @@ -1,7 +1,7 @@ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -// Date : Fri Feb 24 16:07:07 2017 +// Date : Sat Mar 04 18:58:36 2017 // Host : WK73 running 64-bit Service Pack 1 (build 7601) // Command : write_verilog -force -mode synth_stub -rename_top Arty_Z7_20_auto_pc_0 -prefix // Arty_Z7_20_auto_pc_0_ Arty_Z7_20_auto_pc_0_stub.v @@ -14,15 +14,44 @@ // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. (* X_CORE_INFO = "axi_protocol_converter_v2_1_11_axi_protocol_converter,Vivado 2016.4" *) -module Arty_Z7_20_auto_pc_0(aclk, aresetn, s_axi_araddr, s_axi_arlen, - s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arregion, - s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rlast, - s_axi_rvalid, s_axi_rready, m_axi_araddr, m_axi_arlen, m_axi_arsize, m_axi_arburst, - m_axi_arlock, m_axi_arcache, m_axi_arprot, m_axi_arqos, m_axi_arvalid, m_axi_arready, +module Arty_Z7_20_auto_pc_0(aclk, aresetn, s_axi_awid, s_axi_awaddr, + s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot, + s_axi_awregion, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, + s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, + s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, + s_axi_arcache, s_axi_arprot, s_axi_arregion, s_axi_arqos, s_axi_arvalid, s_axi_arready, + s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awid, + m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst, m_axi_awlock, m_axi_awcache, + m_axi_awprot, m_axi_awqos, m_axi_awvalid, m_axi_awready, m_axi_wid, m_axi_wdata, m_axi_wstrb, + m_axi_wlast, m_axi_wvalid, m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_bready, + m_axi_arid, m_axi_araddr, m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, + m_axi_arcache, m_axi_arprot, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata, m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready) -/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[63:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_araddr[31:0],m_axi_arlen[3:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[1:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[63:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready" */; +/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[0:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[63:0],s_axi_wstrb[7:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[0:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[0:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[0:0],s_axi_rdata[63:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awid[0:0],m_axi_awaddr[31:0],m_axi_awlen[3:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[1:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awqos[3:0],m_axi_awvalid,m_axi_awready,m_axi_wid[0:0],m_axi_wdata[63:0],m_axi_wstrb[7:0],m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bid[0:0],m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_arid[0:0],m_axi_araddr[31:0],m_axi_arlen[3:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[1:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rid[0:0],m_axi_rdata[63:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready" */; input aclk; input aresetn; + input [0:0]s_axi_awid; + input [31:0]s_axi_awaddr; + input [7:0]s_axi_awlen; + input [2:0]s_axi_awsize; + input [1:0]s_axi_awburst; + input [0:0]s_axi_awlock; + input [3:0]s_axi_awcache; + input [2:0]s_axi_awprot; + input [3:0]s_axi_awregion; + input [3:0]s_axi_awqos; + input s_axi_awvalid; + output s_axi_awready; + input [63:0]s_axi_wdata; + input [7:0]s_axi_wstrb; + input s_axi_wlast; + input s_axi_wvalid; + output s_axi_wready; + output [0:0]s_axi_bid; + output [1:0]s_axi_bresp; + output s_axi_bvalid; + input s_axi_bready; + input [0:0]s_axi_arid; input [31:0]s_axi_araddr; input [7:0]s_axi_arlen; input [2:0]s_axi_arsize; @@ -34,11 +63,34 @@ module Arty_Z7_20_auto_pc_0(aclk, aresetn, s_axi_araddr, s_axi_arlen, input [3:0]s_axi_arqos; input s_axi_arvalid; output s_axi_arready; + output [0:0]s_axi_rid; output [63:0]s_axi_rdata; output [1:0]s_axi_rresp; output s_axi_rlast; output s_axi_rvalid; input s_axi_rready; + output [0:0]m_axi_awid; + output [31:0]m_axi_awaddr; + output [3:0]m_axi_awlen; + output [2:0]m_axi_awsize; + output [1:0]m_axi_awburst; + output [1:0]m_axi_awlock; + output [3:0]m_axi_awcache; + output [2:0]m_axi_awprot; + output [3:0]m_axi_awqos; + output m_axi_awvalid; + input m_axi_awready; + output [0:0]m_axi_wid; + output [63:0]m_axi_wdata; + output [7:0]m_axi_wstrb; + output m_axi_wlast; + output m_axi_wvalid; + input m_axi_wready; + input [0:0]m_axi_bid; + input [1:0]m_axi_bresp; + input m_axi_bvalid; + output m_axi_bready; + output [0:0]m_axi_arid; output [31:0]m_axi_araddr; output [3:0]m_axi_arlen; output [2:0]m_axi_arsize; @@ -49,6 +101,7 @@ module Arty_Z7_20_auto_pc_0(aclk, aresetn, s_axi_araddr, s_axi_arlen, output [3:0]m_axi_arqos; output m_axi_arvalid; input m_axi_arready; + input [0:0]m_axi_rid; input [63:0]m_axi_rdata; input [1:0]m_axi_rresp; input m_axi_rlast; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0_stub.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0_stub.vhdl index f367107..c97ac89 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0_stub.vhdl +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/Arty_Z7_20_auto_pc_0_stub.vhdl @@ -1,7 +1,7 @@ -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 --- Date : Fri Feb 24 16:07:07 2017 +-- Date : Sat Mar 04 18:58:36 2017 -- Host : WK73 running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode synth_stub -rename_top Arty_Z7_20_auto_pc_0 -prefix -- Arty_Z7_20_auto_pc_0_ Arty_Z7_20_auto_pc_0_stub.vhdl @@ -16,6 +16,28 @@ entity Arty_Z7_20_auto_pc_0 is Port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; + s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_wlast : in STD_LOGIC; + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); @@ -27,11 +49,34 @@ entity Arty_Z7_20_auto_pc_0 is s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; + s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; + m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awvalid : out STD_LOGIC; + m_axi_awready : in STD_LOGIC; + m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_wlast : out STD_LOGIC; + m_axi_wvalid : out STD_LOGIC; + m_axi_wready : in STD_LOGIC; + m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_bvalid : in STD_LOGIC; + m_axi_bready : out STD_LOGIC; + m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); @@ -42,6 +87,7 @@ entity Arty_Z7_20_auto_pc_0 is m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; + m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rlast : in STD_LOGIC; @@ -55,7 +101,7 @@ architecture stub of Arty_Z7_20_auto_pc_0 is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[63:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_araddr[31:0],m_axi_arlen[3:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[1:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[63:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready"; +attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awid[0:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[63:0],s_axi_wstrb[7:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[0:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[0:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[0:0],s_axi_rdata[63:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awid[0:0],m_axi_awaddr[31:0],m_axi_awlen[3:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[1:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awqos[3:0],m_axi_awvalid,m_axi_awready,m_axi_wid[0:0],m_axi_wdata[63:0],m_axi_wstrb[7:0],m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bid[0:0],m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_arid[0:0],m_axi_araddr[31:0],m_axi_arlen[3:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[1:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rid[0:0],m_axi_rdata[63:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "axi_protocol_converter_v2_1_11_axi_protocol_converter,Vivado 2016.4"; begin diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/sim/Arty_Z7_20_auto_pc_0.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/sim/Arty_Z7_20_auto_pc_0.v index e697a4c..22ead25 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/sim/Arty_Z7_20_auto_pc_0.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/sim/Arty_Z7_20_auto_pc_0.v @@ -56,6 +56,28 @@ module Arty_Z7_20_auto_pc_0 ( aclk, aresetn, + s_axi_awid, + s_axi_awaddr, + s_axi_awlen, + s_axi_awsize, + s_axi_awburst, + s_axi_awlock, + s_axi_awcache, + s_axi_awprot, + s_axi_awregion, + s_axi_awqos, + s_axi_awvalid, + s_axi_awready, + s_axi_wdata, + s_axi_wstrb, + s_axi_wlast, + s_axi_wvalid, + s_axi_wready, + s_axi_bid, + s_axi_bresp, + s_axi_bvalid, + s_axi_bready, + s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, @@ -67,11 +89,34 @@ module Arty_Z7_20_auto_pc_0 ( s_axi_arqos, s_axi_arvalid, s_axi_arready, + s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, + m_axi_awid, + m_axi_awaddr, + m_axi_awlen, + m_axi_awsize, + m_axi_awburst, + m_axi_awlock, + m_axi_awcache, + m_axi_awprot, + m_axi_awqos, + m_axi_awvalid, + m_axi_awready, + m_axi_wid, + m_axi_wdata, + m_axi_wstrb, + m_axi_wlast, + m_axi_wvalid, + m_axi_wready, + m_axi_bid, + m_axi_bresp, + m_axi_bvalid, + m_axi_bready, + m_axi_arid, m_axi_araddr, m_axi_arlen, m_axi_arsize, @@ -82,6 +127,7 @@ module Arty_Z7_20_auto_pc_0 ( m_axi_arqos, m_axi_arvalid, m_axi_arready, + m_axi_rid, m_axi_rdata, m_axi_rresp, m_axi_rlast, @@ -93,6 +139,50 @@ module Arty_Z7_20_auto_pc_0 ( input wire aclk; (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *) input wire aresetn; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) +input wire [0 : 0] s_axi_awid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) +input wire [31 : 0] s_axi_awaddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) +input wire [7 : 0] s_axi_awlen; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) +input wire [2 : 0] s_axi_awsize; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) +input wire [1 : 0] s_axi_awburst; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) +input wire [0 : 0] s_axi_awlock; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) +input wire [3 : 0] s_axi_awcache; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) +input wire [2 : 0] s_axi_awprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *) +input wire [3 : 0] s_axi_awregion; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *) +input wire [3 : 0] s_axi_awqos; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) +input wire s_axi_awvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) +output wire s_axi_awready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) +input wire [63 : 0] s_axi_wdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) +input wire [7 : 0] s_axi_wstrb; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) +input wire s_axi_wlast; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) +input wire s_axi_wvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) +output wire s_axi_wready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) +output wire [0 : 0] s_axi_bid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) +output wire [1 : 0] s_axi_bresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) +output wire s_axi_bvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) +input wire s_axi_bready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) +input wire [0 : 0] s_axi_arid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input wire [31 : 0] s_axi_araddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) @@ -115,6 +205,8 @@ input wire [3 : 0] s_axi_arqos; input wire s_axi_arvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output wire s_axi_arready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) +output wire [0 : 0] s_axi_rid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output wire [63 : 0] s_axi_rdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) @@ -125,6 +217,50 @@ output wire s_axi_rlast; output wire s_axi_rvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input wire s_axi_rready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *) +output wire [0 : 0] m_axi_awid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) +output wire [31 : 0] m_axi_awaddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *) +output wire [3 : 0] m_axi_awlen; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *) +output wire [2 : 0] m_axi_awsize; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *) +output wire [1 : 0] m_axi_awburst; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *) +output wire [1 : 0] m_axi_awlock; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *) +output wire [3 : 0] m_axi_awcache; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) +output wire [2 : 0] m_axi_awprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *) +output wire [3 : 0] m_axi_awqos; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) +output wire m_axi_awvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) +input wire m_axi_awready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WID" *) +output wire [0 : 0] m_axi_wid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) +output wire [63 : 0] m_axi_wdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) +output wire [7 : 0] m_axi_wstrb; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *) +output wire m_axi_wlast; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) +output wire m_axi_wvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) +input wire m_axi_wready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *) +input wire [0 : 0] m_axi_bid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) +input wire [1 : 0] m_axi_bresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) +input wire m_axi_bvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) +output wire m_axi_bready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *) +output wire [0 : 0] m_axi_arid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output wire [31 : 0] m_axi_araddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *) @@ -145,6 +281,8 @@ output wire [3 : 0] m_axi_arqos; output wire m_axi_arvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input wire m_axi_arready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *) +input wire [0 : 0] m_axi_rid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input wire [63 : 0] m_axi_rdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) @@ -160,11 +298,11 @@ output wire m_axi_rready; .C_FAMILY("zynq"), .C_M_AXI_PROTOCOL(1), .C_S_AXI_PROTOCOL(0), - .C_IGNORE_ID(1), + .C_IGNORE_ID(0), .C_AXI_ID_WIDTH(1), .C_AXI_ADDR_WIDTH(32), .C_AXI_DATA_WIDTH(64), - .C_AXI_SUPPORTS_WRITE(0), + .C_AXI_SUPPORTS_WRITE(1), .C_AXI_SUPPORTS_READ(1), .C_AXI_SUPPORTS_USER_SIGNALS(0), .C_AXI_AWUSER_WIDTH(1), @@ -176,32 +314,32 @@ output wire m_axi_rready; ) inst ( .aclk(aclk), .aresetn(aresetn), - .s_axi_awid(1'H0), - .s_axi_awaddr(32'H00000000), - .s_axi_awlen(8'H00), - .s_axi_awsize(3'H0), - .s_axi_awburst(2'H1), - .s_axi_awlock(1'H0), - .s_axi_awcache(4'H0), - .s_axi_awprot(3'H0), - .s_axi_awregion(4'H0), - .s_axi_awqos(4'H0), + .s_axi_awid(s_axi_awid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awlen(s_axi_awlen), + .s_axi_awsize(s_axi_awsize), + .s_axi_awburst(s_axi_awburst), + .s_axi_awlock(s_axi_awlock), + .s_axi_awcache(s_axi_awcache), + .s_axi_awprot(s_axi_awprot), + .s_axi_awregion(s_axi_awregion), + .s_axi_awqos(s_axi_awqos), .s_axi_awuser(1'H0), - .s_axi_awvalid(1'H0), - .s_axi_awready(), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_awready(s_axi_awready), .s_axi_wid(1'H0), - .s_axi_wdata(64'H0000000000000000), - .s_axi_wstrb(8'HFF), - .s_axi_wlast(1'H1), + .s_axi_wdata(s_axi_wdata), + .s_axi_wstrb(s_axi_wstrb), + .s_axi_wlast(s_axi_wlast), .s_axi_wuser(1'H0), - .s_axi_wvalid(1'H0), - .s_axi_wready(), - .s_axi_bid(), - .s_axi_bresp(), + .s_axi_wvalid(s_axi_wvalid), + .s_axi_wready(s_axi_wready), + .s_axi_bid(s_axi_bid), + .s_axi_bresp(s_axi_bresp), .s_axi_buser(), - .s_axi_bvalid(), - .s_axi_bready(1'H0), - .s_axi_arid(1'H0), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_bready(s_axi_bready), + .s_axi_arid(s_axi_arid), .s_axi_araddr(s_axi_araddr), .s_axi_arlen(s_axi_arlen), .s_axi_arsize(s_axi_arsize), @@ -214,39 +352,39 @@ output wire m_axi_rready; .s_axi_aruser(1'H0), .s_axi_arvalid(s_axi_arvalid), .s_axi_arready(s_axi_arready), - .s_axi_rid(), + .s_axi_rid(s_axi_rid), .s_axi_rdata(s_axi_rdata), .s_axi_rresp(s_axi_rresp), .s_axi_rlast(s_axi_rlast), .s_axi_ruser(), .s_axi_rvalid(s_axi_rvalid), .s_axi_rready(s_axi_rready), - .m_axi_awid(), - .m_axi_awaddr(), - .m_axi_awlen(), - .m_axi_awsize(), - .m_axi_awburst(), - .m_axi_awlock(), - .m_axi_awcache(), - .m_axi_awprot(), + .m_axi_awid(m_axi_awid), + .m_axi_awaddr(m_axi_awaddr), + .m_axi_awlen(m_axi_awlen), + .m_axi_awsize(m_axi_awsize), + .m_axi_awburst(m_axi_awburst), + .m_axi_awlock(m_axi_awlock), + .m_axi_awcache(m_axi_awcache), + .m_axi_awprot(m_axi_awprot), .m_axi_awregion(), - .m_axi_awqos(), + .m_axi_awqos(m_axi_awqos), .m_axi_awuser(), - .m_axi_awvalid(), - .m_axi_awready(1'H0), - .m_axi_wid(), - .m_axi_wdata(), - .m_axi_wstrb(), - .m_axi_wlast(), + .m_axi_awvalid(m_axi_awvalid), + .m_axi_awready(m_axi_awready), + .m_axi_wid(m_axi_wid), + .m_axi_wdata(m_axi_wdata), + .m_axi_wstrb(m_axi_wstrb), + .m_axi_wlast(m_axi_wlast), .m_axi_wuser(), - .m_axi_wvalid(), - .m_axi_wready(1'H0), - .m_axi_bid(1'H0), - .m_axi_bresp(2'H0), + .m_axi_wvalid(m_axi_wvalid), + .m_axi_wready(m_axi_wready), + .m_axi_bid(m_axi_bid), + .m_axi_bresp(m_axi_bresp), .m_axi_buser(1'H0), - .m_axi_bvalid(1'H0), - .m_axi_bready(), - .m_axi_arid(), + .m_axi_bvalid(m_axi_bvalid), + .m_axi_bready(m_axi_bready), + .m_axi_arid(m_axi_arid), .m_axi_araddr(m_axi_araddr), .m_axi_arlen(m_axi_arlen), .m_axi_arsize(m_axi_arsize), @@ -259,7 +397,7 @@ output wire m_axi_rready; .m_axi_aruser(), .m_axi_arvalid(m_axi_arvalid), .m_axi_arready(m_axi_arready), - .m_axi_rid(1'H0), + .m_axi_rid(m_axi_rid), .m_axi_rdata(m_axi_rdata), .m_axi_rresp(m_axi_rresp), .m_axi_rlast(m_axi_rlast), diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/synth/Arty_Z7_20_auto_pc_0.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/synth/Arty_Z7_20_auto_pc_0.v index 072fc08..5dc6e2c 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/synth/Arty_Z7_20_auto_pc_0.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_0/synth/Arty_Z7_20_auto_pc_0.v @@ -52,12 +52,34 @@ (* X_CORE_INFO = "axi_protocol_converter_v2_1_11_axi_protocol_converter,Vivado 2016.4" *) (* CHECK_LICENSE_TYPE = "Arty_Z7_20_auto_pc_0,axi_protocol_converter_v2_1_11_axi_protocol_converter,{}" *) -(* CORE_GENERATION_INFO = "Arty_Z7_20_auto_pc_0,axi_protocol_converter_v2_1_11_axi_protocol_converter,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=11,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=1,C_S_AXI_PROTOCOL=0,C_IGNORE_ID=1,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_SUPPORTS_WRITE=0,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_W\ +(* CORE_GENERATION_INFO = "Arty_Z7_20_auto_pc_0,axi_protocol_converter_v2_1_11_axi_protocol_converter,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=11,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=1,C_S_AXI_PROTOCOL=0,C_IGNORE_ID=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_W\ IDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) module Arty_Z7_20_auto_pc_0 ( aclk, aresetn, + s_axi_awid, + s_axi_awaddr, + s_axi_awlen, + s_axi_awsize, + s_axi_awburst, + s_axi_awlock, + s_axi_awcache, + s_axi_awprot, + s_axi_awregion, + s_axi_awqos, + s_axi_awvalid, + s_axi_awready, + s_axi_wdata, + s_axi_wstrb, + s_axi_wlast, + s_axi_wvalid, + s_axi_wready, + s_axi_bid, + s_axi_bresp, + s_axi_bvalid, + s_axi_bready, + s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, @@ -69,11 +91,34 @@ module Arty_Z7_20_auto_pc_0 ( s_axi_arqos, s_axi_arvalid, s_axi_arready, + s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, + m_axi_awid, + m_axi_awaddr, + m_axi_awlen, + m_axi_awsize, + m_axi_awburst, + m_axi_awlock, + m_axi_awcache, + m_axi_awprot, + m_axi_awqos, + m_axi_awvalid, + m_axi_awready, + m_axi_wid, + m_axi_wdata, + m_axi_wstrb, + m_axi_wlast, + m_axi_wvalid, + m_axi_wready, + m_axi_bid, + m_axi_bresp, + m_axi_bvalid, + m_axi_bready, + m_axi_arid, m_axi_araddr, m_axi_arlen, m_axi_arsize, @@ -84,6 +129,7 @@ module Arty_Z7_20_auto_pc_0 ( m_axi_arqos, m_axi_arvalid, m_axi_arready, + m_axi_rid, m_axi_rdata, m_axi_rresp, m_axi_rlast, @@ -95,6 +141,50 @@ module Arty_Z7_20_auto_pc_0 ( input wire aclk; (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *) input wire aresetn; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) +input wire [0 : 0] s_axi_awid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) +input wire [31 : 0] s_axi_awaddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) +input wire [7 : 0] s_axi_awlen; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) +input wire [2 : 0] s_axi_awsize; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) +input wire [1 : 0] s_axi_awburst; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) +input wire [0 : 0] s_axi_awlock; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) +input wire [3 : 0] s_axi_awcache; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) +input wire [2 : 0] s_axi_awprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *) +input wire [3 : 0] s_axi_awregion; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *) +input wire [3 : 0] s_axi_awqos; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) +input wire s_axi_awvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) +output wire s_axi_awready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) +input wire [63 : 0] s_axi_wdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) +input wire [7 : 0] s_axi_wstrb; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) +input wire s_axi_wlast; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) +input wire s_axi_wvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) +output wire s_axi_wready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) +output wire [0 : 0] s_axi_bid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) +output wire [1 : 0] s_axi_bresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) +output wire s_axi_bvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) +input wire s_axi_bready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) +input wire [0 : 0] s_axi_arid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input wire [31 : 0] s_axi_araddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) @@ -117,6 +207,8 @@ input wire [3 : 0] s_axi_arqos; input wire s_axi_arvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output wire s_axi_arready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) +output wire [0 : 0] s_axi_rid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output wire [63 : 0] s_axi_rdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) @@ -127,6 +219,50 @@ output wire s_axi_rlast; output wire s_axi_rvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input wire s_axi_rready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *) +output wire [0 : 0] m_axi_awid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) +output wire [31 : 0] m_axi_awaddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *) +output wire [3 : 0] m_axi_awlen; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *) +output wire [2 : 0] m_axi_awsize; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *) +output wire [1 : 0] m_axi_awburst; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *) +output wire [1 : 0] m_axi_awlock; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *) +output wire [3 : 0] m_axi_awcache; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) +output wire [2 : 0] m_axi_awprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *) +output wire [3 : 0] m_axi_awqos; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) +output wire m_axi_awvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) +input wire m_axi_awready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WID" *) +output wire [0 : 0] m_axi_wid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) +output wire [63 : 0] m_axi_wdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) +output wire [7 : 0] m_axi_wstrb; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *) +output wire m_axi_wlast; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) +output wire m_axi_wvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) +input wire m_axi_wready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *) +input wire [0 : 0] m_axi_bid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) +input wire [1 : 0] m_axi_bresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) +input wire m_axi_bvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) +output wire m_axi_bready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *) +output wire [0 : 0] m_axi_arid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output wire [31 : 0] m_axi_araddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *) @@ -147,6 +283,8 @@ output wire [3 : 0] m_axi_arqos; output wire m_axi_arvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input wire m_axi_arready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *) +input wire [0 : 0] m_axi_rid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input wire [63 : 0] m_axi_rdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) @@ -162,11 +300,11 @@ output wire m_axi_rready; .C_FAMILY("zynq"), .C_M_AXI_PROTOCOL(1), .C_S_AXI_PROTOCOL(0), - .C_IGNORE_ID(1), + .C_IGNORE_ID(0), .C_AXI_ID_WIDTH(1), .C_AXI_ADDR_WIDTH(32), .C_AXI_DATA_WIDTH(64), - .C_AXI_SUPPORTS_WRITE(0), + .C_AXI_SUPPORTS_WRITE(1), .C_AXI_SUPPORTS_READ(1), .C_AXI_SUPPORTS_USER_SIGNALS(0), .C_AXI_AWUSER_WIDTH(1), @@ -178,32 +316,32 @@ output wire m_axi_rready; ) inst ( .aclk(aclk), .aresetn(aresetn), - .s_axi_awid(1'H0), - .s_axi_awaddr(32'H00000000), - .s_axi_awlen(8'H00), - .s_axi_awsize(3'H0), - .s_axi_awburst(2'H1), - .s_axi_awlock(1'H0), - .s_axi_awcache(4'H0), - .s_axi_awprot(3'H0), - .s_axi_awregion(4'H0), - .s_axi_awqos(4'H0), + .s_axi_awid(s_axi_awid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awlen(s_axi_awlen), + .s_axi_awsize(s_axi_awsize), + .s_axi_awburst(s_axi_awburst), + .s_axi_awlock(s_axi_awlock), + .s_axi_awcache(s_axi_awcache), + .s_axi_awprot(s_axi_awprot), + .s_axi_awregion(s_axi_awregion), + .s_axi_awqos(s_axi_awqos), .s_axi_awuser(1'H0), - .s_axi_awvalid(1'H0), - .s_axi_awready(), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_awready(s_axi_awready), .s_axi_wid(1'H0), - .s_axi_wdata(64'H0000000000000000), - .s_axi_wstrb(8'HFF), - .s_axi_wlast(1'H1), + .s_axi_wdata(s_axi_wdata), + .s_axi_wstrb(s_axi_wstrb), + .s_axi_wlast(s_axi_wlast), .s_axi_wuser(1'H0), - .s_axi_wvalid(1'H0), - .s_axi_wready(), - .s_axi_bid(), - .s_axi_bresp(), + .s_axi_wvalid(s_axi_wvalid), + .s_axi_wready(s_axi_wready), + .s_axi_bid(s_axi_bid), + .s_axi_bresp(s_axi_bresp), .s_axi_buser(), - .s_axi_bvalid(), - .s_axi_bready(1'H0), - .s_axi_arid(1'H0), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_bready(s_axi_bready), + .s_axi_arid(s_axi_arid), .s_axi_araddr(s_axi_araddr), .s_axi_arlen(s_axi_arlen), .s_axi_arsize(s_axi_arsize), @@ -216,39 +354,39 @@ output wire m_axi_rready; .s_axi_aruser(1'H0), .s_axi_arvalid(s_axi_arvalid), .s_axi_arready(s_axi_arready), - .s_axi_rid(), + .s_axi_rid(s_axi_rid), .s_axi_rdata(s_axi_rdata), .s_axi_rresp(s_axi_rresp), .s_axi_rlast(s_axi_rlast), .s_axi_ruser(), .s_axi_rvalid(s_axi_rvalid), .s_axi_rready(s_axi_rready), - .m_axi_awid(), - .m_axi_awaddr(), - .m_axi_awlen(), - .m_axi_awsize(), - .m_axi_awburst(), - .m_axi_awlock(), - .m_axi_awcache(), - .m_axi_awprot(), + .m_axi_awid(m_axi_awid), + .m_axi_awaddr(m_axi_awaddr), + .m_axi_awlen(m_axi_awlen), + .m_axi_awsize(m_axi_awsize), + .m_axi_awburst(m_axi_awburst), + .m_axi_awlock(m_axi_awlock), + .m_axi_awcache(m_axi_awcache), + .m_axi_awprot(m_axi_awprot), .m_axi_awregion(), - .m_axi_awqos(), + .m_axi_awqos(m_axi_awqos), .m_axi_awuser(), - .m_axi_awvalid(), - .m_axi_awready(1'H0), - .m_axi_wid(), - .m_axi_wdata(), - .m_axi_wstrb(), - .m_axi_wlast(), + .m_axi_awvalid(m_axi_awvalid), + .m_axi_awready(m_axi_awready), + .m_axi_wid(m_axi_wid), + .m_axi_wdata(m_axi_wdata), + .m_axi_wstrb(m_axi_wstrb), + .m_axi_wlast(m_axi_wlast), .m_axi_wuser(), - .m_axi_wvalid(), - .m_axi_wready(1'H0), - .m_axi_bid(1'H0), - .m_axi_bresp(2'H0), + .m_axi_wvalid(m_axi_wvalid), + .m_axi_wready(m_axi_wready), + .m_axi_bid(m_axi_bid), + .m_axi_bresp(m_axi_bresp), .m_axi_buser(1'H0), - .m_axi_bvalid(1'H0), - .m_axi_bready(), - .m_axi_arid(), + .m_axi_bvalid(m_axi_bvalid), + .m_axi_bready(m_axi_bready), + .m_axi_arid(m_axi_arid), .m_axi_araddr(m_axi_araddr), .m_axi_arlen(m_axi_arlen), .m_axi_arsize(m_axi_arsize), @@ -261,7 +399,7 @@ output wire m_axi_rready; .m_axi_aruser(), .m_axi_arvalid(m_axi_arvalid), .m_axi_arready(m_axi_arready), - .m_axi_rid(1'H0), + .m_axi_rid(m_axi_rid), .m_axi_rdata(m_axi_rdata), .m_axi_rresp(m_axi_rresp), .m_axi_rlast(m_axi_rlast), diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_1/Arty_Z7_20_auto_pc_1.dcp b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_1/Arty_Z7_20_auto_pc_1.dcp index 91a93df..92d0af5 100644 Binary files a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_1/Arty_Z7_20_auto_pc_1.dcp and b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_1/Arty_Z7_20_auto_pc_1.dcp differ diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_1/Arty_Z7_20_auto_pc_1.xml b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_1/Arty_Z7_20_auto_pc_1.xml index 9d28fc9..f64ca99 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_1/Arty_Z7_20_auto_pc_1.xml +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_auto_pc_1/Arty_Z7_20_auto_pc_1.xml @@ -1087,7 +1087,7 @@ GENtimestamp - Mon Feb 27 18:05:27 UTC 2017 + Mon Mar 06 19:44:20 UTC 2017 boundaryCRC @@ -1117,7 +1117,7 @@ GENtimestamp - Mon Feb 27 18:05:27 UTC 2017 + Mon Mar 06 19:44:20 UTC 2017 boundaryCRC @@ -1148,7 +1148,7 @@ GENtimestamp - Mon Feb 27 18:05:27 UTC 2017 + Mon Mar 06 19:44:20 UTC 2017 boundaryCRC @@ -1194,7 +1194,7 @@ GENtimestamp - Mon Feb 27 18:05:27 UTC 2017 + Mon Mar 06 19:44:19 UTC 2017 boundaryCRC @@ -1225,7 +1225,7 @@ GENtimestamp - Mon Feb 27 18:05:27 UTC 2017 + Mon Mar 06 19:44:20 UTC 2017 boundaryCRC @@ -1255,7 +1255,7 @@ GENtimestamp - Mon Feb 27 18:05:34 UTC 2017 + Mon Mar 06 19:44:26 UTC 2017 boundaryCRC diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0.dcp b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0.dcp new file mode 100644 index 0000000..1e385d3 Binary files /dev/null and b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0.dcp differ diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0.xci b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0.xci new file mode 100644 index 0000000..35c0a73 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0.xci @@ -0,0 +1,135 @@ + + + xilinx.com + xci + unknown + 1.0 + + + Arty_Z7_20_axi_gpio_0_0 + + + 1 + 9 + 0 + 0 + 0 + Arty_Z7_20_processing_system7_0_0_FCLK_CLK0 + 32 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + Arty_Z7_20_processing_system7_0_0_FCLK_CLK0 + 100000000 + 0.000 + 0 + 1 + 1 + 0 + 0x00000000 + 0x00000000 + zynq + 1 + 1 + 1 + 1 + 0xFFFFFFFF + 0xFFFFFFFF + 0 + 1 + 1 + 0 + 0x00000000 + 0x00000000 + 1 + 1 + 1 + 1 + 0xFFFFFFFF + 0xFFFFFFFF + Arty_Z7_20_axi_gpio_0_0 + Custom + Custom + false + zynq + digilentinc.com:arty-z7-20:part0:1.0 + xc7z020 + clg400 + VHDL + + MIXED + -1 + + TRUE + TRUE + IP_Integrator + 13 + TRUE + . + + ../../ipshared + 2016.4 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0.xdc b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0.xdc new file mode 100644 index 0000000..a7e9895 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0.xdc @@ -0,0 +1,50 @@ + +# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + + +set_false_path -to [get_pins -hier *cdc_to*/D] + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0.xml b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0.xml new file mode 100644 index 0000000..08fdd90 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0.xml @@ -0,0 +1,1949 @@ + + + xilinx.com + customized_ip + Arty_Z7_20_axi_gpio_0_0 + 1.0 + + + S_AXI + S_AXI + + + + + + + + + ARADDR + + + s_axi_araddr + + + + + ARREADY + + + s_axi_arready + + + + + ARVALID + + + s_axi_arvalid + + + + + AWADDR + + + s_axi_awaddr + + + + + AWREADY + + + s_axi_awready + + + + + AWVALID + + + s_axi_awvalid + + + + + BREADY + + + s_axi_bready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + RDATA + + + s_axi_rdata + + + + + RREADY + + + s_axi_rready + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + WDATA + + + s_axi_wdata + + + + + WREADY + + + s_axi_wready + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + + DATA_WIDTH + 32 + + + PROTOCOL + AXI4LITE + + + FREQ_HZ + 100000000 + + + ID_WIDTH + 0 + + + ADDR_WIDTH + 9 + + + AWUSER_WIDTH + 0 + + + ARUSER_WIDTH + 0 + + + WUSER_WIDTH + 0 + + + RUSER_WIDTH + 0 + + + BUSER_WIDTH + 0 + + + READ_WRITE_MODE + READ_WRITE + + + HAS_BURST + 0 + + + HAS_LOCK + 0 + + + HAS_PROT + 0 + + + HAS_CACHE + 0 + + + HAS_QOS + 0 + + + HAS_REGION + 0 + + + HAS_WSTRB + 1 + + + HAS_BRESP + 1 + + + HAS_RRESP + 1 + + + SUPPORTS_NARROW_BURST + 0 + + + NUM_READ_OUTSTANDING + 1 + + + NUM_WRITE_OUTSTANDING + 1 + + + MAX_BURST_LENGTH + 1 + + + PHASE + 0.000 + + + CLK_DOMAIN + Arty_Z7_20_processing_system7_0_0_FCLK_CLK0 + + + NUM_READ_THREADS + 1 + + + NUM_WRITE_THREADS + 1 + + + RUSER_BITS_PER_BYTE + 0 + + + WUSER_BITS_PER_BYTE + 0 + + + + + S_AXI_ACLK + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + S_AXI + + + ASSOCIATED_RESET + s_axi_aresetn + + + FREQ_HZ + 100000000 + + + PHASE + 0.000 + + + CLK_DOMAIN + Arty_Z7_20_processing_system7_0_0_FCLK_CLK0 + + + + + S_AXI_ARESETN + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + IP2INTC_IRQ + IP2Intc_irq + + + + + + + INTERRUPT + + + ip2intc_irpt + + + + + + SENSITIVITY + LEVEL_HIGH + + + PortWidth + 1 + + + + + + true + + + + + + GPIO + GPIO + + + + + + + TRI_I + + + gpio_io_i + + + + + TRI_O + + + gpio_io_o + + + + + TRI_T + + + gpio_io_t + + + + + + BOARD.ASSOCIATED_PARAM + GPIO_BOARD_INTERFACE + + + + required + + + + + + + + + true + + + + + + GPIO2 + GPIO2 + + + + + + + TRI_I + + + gpio2_io_i + + + + + TRI_O + + + gpio2_io_o + + + + + TRI_T + + + gpio2_io_t + + + + + + BOARD.ASSOCIATED_PARAM + GPIO2_BOARD_INTERFACE + + + + required + + + + + + + + + true + + + + + + + + S_AXI + S_AXI_MEM + Memory Map for S_AXI + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + GPIO_DATA + Channel-1 GPIO DATA + Channel-1 AXI GPIO Data register + 0x0 + 1 + true + read-write + + 0x0 + + + Channel-1 GPIO DATA + Channel-1 GPIO DATA + AXI GPIO Data Register. +For each I/O bit programmed as input + R - Reads value on the input pin. + W - No effect. +For each I/O bit programmed as output + R - Reads value on GPIO_O pins + W - Writes value to the corresponding AXI GPIO + data register bit and output pin + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + GPIO_TRI + Channel-1 GPIO TRI + Channel-1 AXI GPIO 3-State Control register + 0x4 + 1 + true + read-write + + 0x0 + + + Channel-1 GPIO TRI + Channel-1 GPIO DATA + AXI GPIO 3-State Control Register +Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + GPIO2_DATA + Channel-2 GPIO DATA + Channel-2 AXI GPIO Data register + 0x8 + 1 + true + read-write + + 0x0 + + + Channel-2 GPIO DATA + Channel-2 GPIO DATA + AXI GPIO Data Register. +For each I/O bit programmed as input + R - Reads value on the input pin. + W - No effect. +For each I/O bit programmed as output + R - Reads value on GPIO_O pins + W - Writes value to the corresponding AXI GPIO + data register bit and output pin + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + GPIO2_TRI + Channel-2 GPIO TRI + Channel-2 AXI GPIO 3-State Control register + 0xC + 1 + true + read-write + + 0x0 + + + Channel-2 GPIO TRI + Channel-2 GPIO DATA + AXI GPIO 3-State Control Register +Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + GIER + Global Interrupt Enable register + Global Interrupt Enable register + 0x11C + 32 + true + read-write + + 0x0 + + + Global Interrupt Enable + Global Interrupt Enable + Master enable for the device interrupt output + 0 - Disabled + 1 - Enabled + + 31 + 1 + true + read-write + + 0 + 0 + + false + + + + IP_IER + IP Interrupt Enable register + IP Interrupt Enable register + 0x128 + 32 + true + read-write + + 0x0 + + + Channel-1 Interrupt Enable + Channel-1 Interrupt Enable + Enable Channel 1 Interrupt + 0 - Disabled (masked) + 1 - Enabled + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + Channel-2 Interrupt Enable + Channel-2 Interrupt Enable + Enable Channel 2 Interrupt + 0 - Disabled (masked) + 1 - Enabled + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + IP_ISR + IP Interrupt Status register + IP Interrupt Status register + 0x120 + 32 + true + read-write + + 0x0 + + + Channel-1 Interrupt Status + Channel-1 Interrupt Status + Channel 1 Interrupt Status + 0 - No Channel 1 input interrupt + 1 - Channel 1 input interrupt + + 0 + 1 + true + read-write + oneToToggle + + 0 + 0 + + false + + + Channel-2 Interrupt Status + Channel-2 Interrupt Status + Channel 2 Interrupt Status + 0 - No Channel 2 input interrupt + 1 - Channel 2 input interrupt + + 1 + 1 + true + read-write + oneToToggle + + 0 + 0 + + false + + + + + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + + xilinx_vhdlsynthesis_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset + + + xilinx_vhdlsynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset + + + xilinx_vhdlsynthesis_xilinx_com_ip_interrupt_control_3_1__ref_view_fileset + + + xilinx_vhdlsynthesis_view_fileset + + + + GENtimestamp + Fri Feb 24 23:57:46 UTC 2017 + + + boundaryCRC + f110757b + + + boundaryCRCversion + 1 + + + customizationCRC + e0690686 + + + customizationCRCversion + 6 + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Sun Mar 05 02:51:37 UTC 2017 + + + boundaryCRC + f110757b + + + boundaryCRCversion + 1 + + + customizationCRC + e0690686 + + + customizationCRCversion + 6 + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_interrupt_control_3_1__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + GENtimestamp + Fri Feb 24 23:57:46 UTC 2017 + + + boundaryCRC + f110757b + + + boundaryCRCversion + 1 + + + customizationCRC + 9088ea02 + + + customizationCRCversion + 6 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Sun Mar 05 02:51:37 UTC 2017 + + + boundaryCRC + f110757b + + + boundaryCRCversion + 1 + + + customizationCRC + 9088ea02 + + + customizationCRCversion + 6 + + + + + xilinx_implementation + Implementation + :vivado.xilinx.com:implementation + + xilinx_implementation_view_fileset + + + + GENtimestamp + Sun Mar 05 02:51:37 UTC 2017 + + + boundaryCRC + f110757b + + + boundaryCRCversion + 1 + + + customizationCRC + e0690686 + + + customizationCRCversion + 6 + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Sun Mar 05 02:57:36 UTC 2017 + + + boundaryCRC + f110757b + + + boundaryCRCversion + 1 + + + customizationCRC + e0690686 + + + customizationCRCversion + 6 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + s_axi_awaddr + + in + + 8 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 8 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + ip2intc_irpt + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + true + + + + + + gpio_io_i + + in + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + gpio_io_o + + out + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + true + + + + + + gpio_io_t + + out + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + false + + + + + + gpio2_io_i + + in + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + true + + + + + + gpio2_io_o + + out + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + false + + + + + + gpio2_io_t + + out + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + false + + + + + + + + C_FAMILY + zynq + + + C_S_AXI_ADDR_WIDTH + C S Axi Addr Width + 9 + + + C_S_AXI_DATA_WIDTH + C S Axi Data Width + 32 + + + C_GPIO_WIDTH + GPIO Width + 1 + + + C_GPIO2_WIDTH + GPIO2 Data Width + 1 + + + C_ALL_INPUTS + All Inputs + 0 + + + C_ALL_INPUTS_2 + All Inputs + 1 + + + C_ALL_OUTPUTS + All Outputs + 1 + + + C_ALL_OUTPUTS_2 + All Outputs + 0 + + + C_INTERRUPT_PRESENT + Enable Interrupt + 1 + + + C_DOUT_DEFAULT + Default DOUT value + 0x00000000 + + + C_TRI_DEFAULT + Default tri state value + 0xFFFFFFFF + + + C_IS_DUAL + Enable Dual channel + 1 + + + C_DOUT_DEFAULT_2 + Default DOUT value2 + 0x00000000 + + + C_TRI_DEFAULT_2 + Default tri state value2 + 0xFFFFFFFF + + + + + + choice_list_a63df46c + Custom + btns_4bits + leds_4bits + rgb_led + shield_dp0_dp13 + shield_dp26_dp41 + sws_2bits + + + choice_pairs_4873554b + 0 + 1 + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset + + ../../ipshared/0ba0/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd + vhdlSource + axi_lite_ipif_v3_0_4 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset + + ../../ipshared/52cb/hdl/lib_cdc_v1_0_rfs.vhd + vhdlSource + lib_cdc_v1_0_2 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_interrupt_control_3_1__ref_view_fileset + + ../../ipshared/e956/hdl/interrupt_control_v3_1_vh_rfs.vhd + vhdlSource + interrupt_control_v3_1_4 + + + + + + + + + + + xilinx_vhdlsynthesis_view_fileset + + Arty_Z7_20_axi_gpio_0_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + Arty_Z7_20_axi_gpio_0_0.xdc + xdc + + + ../../ipshared/4f16/hdl/axi_gpio_v2_0_vh_rfs.vhd + vhdlSource + axi_gpio_v2_0_13 + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/Arty_Z7_20_axi_gpio_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset + + ../../ipshared/0ba0/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + axi_lite_ipif_v3_0_4 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset + + ../../ipshared/52cb/hdl/lib_cdc_v1_0_rfs.vhd + vhdlSource + USED_IN_ipstatic + lib_cdc_v1_0_2 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_interrupt_control_3_1__ref_view_fileset + + ../../ipshared/e956/hdl/interrupt_control_v3_1_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + interrupt_control_v3_1_4 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + ../../ipshared/4f16/hdl/axi_gpio_v2_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + axi_gpio_v2_0_13 + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/Arty_Z7_20_axi_gpio_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_implementation_view_fileset + + Arty_Z7_20_axi_gpio_0_0_board.xdc + xdc + USED_IN_board + USED_IN_implementation + USED_IN_synthesis + + + + xilinx_externalfiles_view_fileset + + Arty_Z7_20_axi_gpio_0_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + Arty_Z7_20_axi_gpio_0_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Arty_Z7_20_axi_gpio_0_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Arty_Z7_20_axi_gpio_0_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Arty_Z7_20_axi_gpio_0_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + Advanced eXtensible Interface General Purpose Input/Output (AXI GPIO) core provides a general purpose input/output interface to the AXI interface. + + + C_TRI_DEFAULT + Default Tri State Value + 0xFFFFFFFF + + + + false + + + + + + C_GPIO_WIDTH + GPIO Width + 1 + + + + true + + + + + + C_GPIO2_WIDTH + GPIO Width + 1 + + + + true + + + + + + C_IS_DUAL + Enable Dual Channel + 1 + + + + true + + + + + + C_ALL_INPUTS + All Inputs + 0 + + + + true + + + + + + C_TRI_DEFAULT_2 + Default Tri State Value + 0xFFFFFFFF + + + + false + + + + + + C_DOUT_DEFAULT_2 + Default Output Value + 0x00000000 + + + + false + + + + + + C_DOUT_DEFAULT + Default Output Value + 0x00000000 + + + + true + + + + + + C_ALL_INPUTS_2 + All Inputs + 1 + + + + true + + + + + + C_INTERRUPT_PRESENT + Enable Interrupt + 1 + + + + true + + + + + + Component_Name + Arty_Z7_20_axi_gpio_0_0 + + + + true + + + + + + USE_BOARD_FLOW + Generate Board based IO Constraints + false + + + + true + + + + + + GPIO_BOARD_INTERFACE + Custom + + + + true + + + + + + GPIO2_BOARD_INTERFACE + Custom + + + + true + + + + + + C_ALL_OUTPUTS + All Outputs + 1 + + + + true + + + + + + C_ALL_OUTPUTS_2 + All Outputs + 0 + + + + false + + + + + + + + AXI GPIO + 13 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2016.4 + + + + + + + + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0_board.xdc b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0_board.xdc new file mode 100644 index 0000000..3422a8e --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0_board.xdc @@ -0,0 +1,2 @@ +#--------------------Physical Constraints----------------- + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0_ooc.xdc b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0_ooc.xdc new file mode 100644 index 0000000..907e9e9 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0_ooc.xdc @@ -0,0 +1,62 @@ + +################################################################################ +# (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +################################################################################ + +# This XDC is used only for OOC mode of synthesis, implementation +# User should update the correct clock period before proceeding further +# This constraints file contains default clock frequencies to be used during +# out-of-context flows such as OOC Synthesis and Hierarchical Designs. +# For best results the frequencies should be modified# to match the target +# frequencies. + + + create_clock -name s_axi_clk -period 10 [get_ports s_axi_aclk] +## set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_aclk] + +################################################################################ diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0_sim_netlist.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0_sim_netlist.v new file mode 100644 index 0000000..dfd5331 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0_sim_netlist.v @@ -0,0 +1,2792 @@ +// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +// Date : Sat Mar 04 18:57:36 2017 +// Host : WK73 running 64-bit Service Pack 1 (build 7601) +// Command : write_verilog -force -mode funcsim +// c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0_sim_netlist.v +// Design : Arty_Z7_20_axi_gpio_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg400-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "Arty_Z7_20_axi_gpio_0_0,axi_gpio,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_gpio,Vivado 2016.4" *) +(* NotValidForBitStream *) +module Arty_Z7_20_axi_gpio_0_0 + (s_axi_aclk, + s_axi_aresetn, + s_axi_awaddr, + s_axi_awvalid, + s_axi_awready, + s_axi_wdata, + s_axi_wstrb, + s_axi_wvalid, + s_axi_wready, + s_axi_bresp, + s_axi_bvalid, + s_axi_bready, + s_axi_araddr, + s_axi_arvalid, + s_axi_arready, + s_axi_rdata, + s_axi_rresp, + s_axi_rvalid, + s_axi_rready, + ip2intc_irpt, + gpio_io_o, + gpio2_io_i); + (* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK" *) input s_axi_aclk; + (* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST" *) input s_axi_aresetn; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [8:0]s_axi_awaddr; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [8:0]s_axi_araddr; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready; + (* x_interface_info = "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT" *) output ip2intc_irpt; + (* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_O" *) output [0:0]gpio_io_o; + (* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I" *) input [0:0]gpio2_io_i; + + wire [0:0]gpio2_io_i; + wire [0:0]gpio_io_o; + wire ip2intc_irpt; + wire s_axi_aclk; + wire [8:0]s_axi_araddr; + wire s_axi_aresetn; + wire s_axi_arready; + wire s_axi_arvalid; + wire [8:0]s_axi_awaddr; + wire s_axi_awready; + wire s_axi_awvalid; + wire s_axi_bready; + wire [1:0]s_axi_bresp; + wire s_axi_bvalid; + wire [31:0]s_axi_rdata; + wire s_axi_rready; + wire [1:0]s_axi_rresp; + wire s_axi_rvalid; + wire [31:0]s_axi_wdata; + wire s_axi_wready; + wire [3:0]s_axi_wstrb; + wire s_axi_wvalid; + wire [0:0]NLW_U0_gpio2_io_o_UNCONNECTED; + wire [0:0]NLW_U0_gpio2_io_t_UNCONNECTED; + wire [0:0]NLW_U0_gpio_io_t_UNCONNECTED; + + (* C_ALL_INPUTS = "0" *) + (* C_ALL_INPUTS_2 = "1" *) + (* C_ALL_OUTPUTS = "1" *) + (* C_ALL_OUTPUTS_2 = "0" *) + (* C_DOUT_DEFAULT = "0" *) + (* C_DOUT_DEFAULT_2 = "0" *) + (* C_FAMILY = "zynq" *) + (* C_GPIO2_WIDTH = "1" *) + (* C_GPIO_WIDTH = "1" *) + (* C_INTERRUPT_PRESENT = "1" *) + (* C_IS_DUAL = "1" *) + (* C_S_AXI_ADDR_WIDTH = "9" *) + (* C_S_AXI_DATA_WIDTH = "32" *) + (* C_TRI_DEFAULT = "-1" *) + (* C_TRI_DEFAULT_2 = "-1" *) + (* downgradeipidentifiedwarnings = "yes" *) + (* ip_group = "LOGICORE" *) + Arty_Z7_20_axi_gpio_0_0_axi_gpio U0 + (.gpio2_io_i(gpio2_io_i), + .gpio2_io_o(NLW_U0_gpio2_io_o_UNCONNECTED[0]), + .gpio2_io_t(NLW_U0_gpio2_io_t_UNCONNECTED[0]), + .gpio_io_i(1'b0), + .gpio_io_o(gpio_io_o), + .gpio_io_t(NLW_U0_gpio_io_t_UNCONNECTED[0]), + .ip2intc_irpt(ip2intc_irpt), + .s_axi_aclk(s_axi_aclk), + .s_axi_araddr(s_axi_araddr), + .s_axi_aresetn(s_axi_aresetn), + .s_axi_arready(s_axi_arready), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awready(s_axi_awready), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_bready(s_axi_bready), + .s_axi_bresp(s_axi_bresp), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_rdata(s_axi_rdata), + .s_axi_rready(s_axi_rready), + .s_axi_rresp(s_axi_rresp), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_wdata(s_axi_wdata), + .s_axi_wready(s_axi_wready), + .s_axi_wstrb(s_axi_wstrb), + .s_axi_wvalid(s_axi_wvalid)); +endmodule + +(* ORIG_REF_NAME = "GPIO_Core" *) +module Arty_Z7_20_axi_gpio_0_0_GPIO_Core + (GPIO_xferAck_i, + gpio_xferAck_Reg, + gpio2_Data_In, + gpio_Data_In, + GPIO_intr, + GPIO2_intr, + GPIO2_DBus_i, + GPIO_DBus_i, + gpio2_io_t, + gpio_io_t, + gpio_io_o, + gpio2_io_o, + ip2bus_rdack_i, + rst, + s_axi_aclk, + \Dual.gpio2_Data_In_reg[0]_0 , + \Dual.gpio_Data_In_reg[0]_0 , + bus2ip_rnw_i_reg, + bus2ip_rnw_i_reg_0, + bus2ip_rnw_i_reg_1, + bus2ip_rnw_i_reg_2, + bus2ip_cs, + bus2ip_rnw, + intr2bus_rdack, + ip2Bus_RdAck_intr_reg_hole, + gpio_io_i, + gpio2_io_i); + output GPIO_xferAck_i; + output gpio_xferAck_Reg; + output gpio2_Data_In; + output gpio_Data_In; + output GPIO_intr; + output GPIO2_intr; + output [0:0]GPIO2_DBus_i; + output [0:0]GPIO_DBus_i; + output [0:0]gpio2_io_t; + output [0:0]gpio_io_t; + output [0:0]gpio_io_o; + output [0:0]gpio2_io_o; + output ip2bus_rdack_i; + input rst; + input s_axi_aclk; + input \Dual.gpio2_Data_In_reg[0]_0 ; + input \Dual.gpio_Data_In_reg[0]_0 ; + input bus2ip_rnw_i_reg; + input bus2ip_rnw_i_reg_0; + input bus2ip_rnw_i_reg_1; + input bus2ip_rnw_i_reg_2; + input [0:0]bus2ip_cs; + input bus2ip_rnw; + input intr2bus_rdack; + input ip2Bus_RdAck_intr_reg_hole; + input [0:0]gpio_io_i; + input [0:0]gpio2_io_i; + + wire \Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg_n_0_[0] ; + wire \Dual.gpio2_Data_In_reg[0]_0 ; + wire \Dual.gpio_Data_In_reg[0]_0 ; + wire [0:0]GPIO2_DBus_i; + wire GPIO2_intr; + wire [0:0]GPIO_DBus_i; + wire GPIO_intr; + wire GPIO_xferAck_i; + wire [0:0]bus2ip_cs; + wire bus2ip_rnw; + wire bus2ip_rnw_i_reg; + wire bus2ip_rnw_i_reg_0; + wire bus2ip_rnw_i_reg_1; + wire bus2ip_rnw_i_reg_2; + wire gpio2_Data_In; + wire gpio2_data_in_xor; + wire [0:0]gpio2_io_i; + wire gpio2_io_i_d2; + wire [0:0]gpio2_io_o; + wire [0:0]gpio2_io_t; + wire gpio_Data_In; + wire gpio_data_in_xor; + wire [0:0]gpio_io_i; + wire gpio_io_i_d2; + wire [0:0]gpio_io_o; + wire [0:0]gpio_io_t; + wire gpio_xferAck_Reg; + wire iGPIO_xferAck; + wire intr2bus_rdack; + wire ip2Bus_RdAck_intr_reg_hole; + wire ip2bus_rdack_i; + wire l; + wire rst; + wire s_axi_aclk; + + Arty_Z7_20_axi_gpio_0_0_cdc_sync \Dual.INPUT_DOUBLE_REGS4 + (.gpio_Data_In(gpio_Data_In), + .gpio_data_in_xor(gpio_data_in_xor), + .gpio_io_i(gpio_io_i), + .s_axi_aclk(s_axi_aclk), + .scndry_vect_out(gpio_io_i_d2)); + Arty_Z7_20_axi_gpio_0_0_cdc_sync_0 \Dual.INPUT_DOUBLE_REGS5 + (.gpio2_Data_In(gpio2_Data_In), + .gpio2_data_in_xor(gpio2_data_in_xor), + .gpio2_io_i(gpio2_io_i), + .s_axi_aclk(s_axi_aclk), + .scndry_vect_out(gpio2_io_i_d2)); + FDRE \Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[31] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Dual.gpio2_Data_In_reg[0]_0 ), + .Q(GPIO2_DBus_i), + .R(1'b0)); + FDRE \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[31] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Dual.gpio_Data_In_reg[0]_0 ), + .Q(GPIO_DBus_i), + .R(1'b0)); + FDRE \Dual.gen_interrupt_dual.GPIO2_intr_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg_n_0_[0] ), + .Q(GPIO2_intr), + .R(rst)); + FDRE \Dual.gen_interrupt_dual.GPIO_intr_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(l), + .Q(GPIO_intr), + .R(rst)); + FDRE \Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[0] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio2_data_in_xor), + .Q(\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg_n_0_[0] ), + .R(rst)); + FDRE \Dual.gen_interrupt_dual.gpio_data_in_xor_reg_reg[0] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_data_in_xor), + .Q(l), + .R(rst)); + FDRE \Dual.gpio2_Data_In_reg[0] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio2_io_i_d2), + .Q(gpio2_Data_In), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \Dual.gpio2_Data_Out_reg[0] + (.C(s_axi_aclk), + .CE(1'b1), + .D(bus2ip_rnw_i_reg_2), + .Q(gpio2_io_o), + .R(rst)); + FDSE #( + .INIT(1'b1)) + \Dual.gpio2_OE_reg[0] + (.C(s_axi_aclk), + .CE(1'b1), + .D(bus2ip_rnw_i_reg), + .Q(gpio2_io_t), + .S(rst)); + FDRE \Dual.gpio_Data_In_reg[0] + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i_d2), + .Q(gpio_Data_In), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \Dual.gpio_Data_Out_reg[0] + (.C(s_axi_aclk), + .CE(1'b1), + .D(bus2ip_rnw_i_reg_1), + .Q(gpio_io_o), + .R(rst)); + FDSE #( + .INIT(1'b1)) + \Dual.gpio_OE_reg[0] + (.C(s_axi_aclk), + .CE(1'b1), + .D(bus2ip_rnw_i_reg_0), + .Q(gpio_io_t), + .S(rst)); + FDRE gpio_xferAck_Reg_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(GPIO_xferAck_i), + .Q(gpio_xferAck_Reg), + .R(rst)); + LUT3 #( + .INIT(8'h02)) + iGPIO_xferAck_i_1 + (.I0(bus2ip_cs), + .I1(gpio_xferAck_Reg), + .I2(GPIO_xferAck_i), + .O(iGPIO_xferAck)); + FDRE iGPIO_xferAck_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(iGPIO_xferAck), + .Q(GPIO_xferAck_i), + .R(rst)); + LUT4 #( + .INIT(16'hFFF8)) + ip2bus_rdack_i_D1_i_1 + (.I0(GPIO_xferAck_i), + .I1(bus2ip_rnw), + .I2(intr2bus_rdack), + .I3(ip2Bus_RdAck_intr_reg_hole), + .O(ip2bus_rdack_i)); +endmodule + +(* ORIG_REF_NAME = "address_decoder" *) +module Arty_Z7_20_axi_gpio_0_0_address_decoder + (\ip2bus_data_i_D1_reg[31] , + iGPIO_xferAck_reg, + ipif_glbl_irpt_enable_reg_reg, + D, + irpt_wrack, + interrupt_wrce_strb, + intr2bus_rdack0, + irpt_rdack, + p_3_out, + intr_rd_ce_or_reduce, + \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg , + intr_wr_ce_or_reduce, + \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] , + s_axi_arready, + s_axi_wready, + \Dual.gpio2_OE_reg[0] , + \Dual.gpio_OE_reg[0] , + \Dual.gpio_Data_Out_reg[0] , + \Dual.gpio2_Data_Out_reg[0] , + ipif_glbl_irpt_enable_reg_reg_0, + \Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[31] , + \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[31] , + Q, + s_axi_aclk, + \bus2ip_addr_i_reg[8] , + bus2ip_rnw_i_reg, + gpio_xferAck_Reg, + GPIO_xferAck_i, + \ip_irpt_enable_reg_reg[0] , + \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] , + GPIO2_DBus_i, + GPIO_DBus_i, + irpt_wrack_d1, + irpt_rdack_d1, + ipif_glbl_irpt_enable_reg, + p_1_in, + \ip_irpt_enable_reg_reg[1] , + ip2Bus_RdAck_intr_reg_hole_d1, + ip2Bus_WrAck_intr_reg_hole_d1, + ip2bus_rdack_i_D1, + is_read, + \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] , + ip2bus_wrack_i_D1, + is_write_reg, + s_axi_wdata, + gpio2_io_t, + gpio_io_t, + gpio_io_o, + gpio2_io_o, + gpio2_Data_In, + gpio_Data_In, + s_axi_aresetn); + output \ip2bus_data_i_D1_reg[31] ; + output iGPIO_xferAck_reg; + output ipif_glbl_irpt_enable_reg_reg; + output [2:0]D; + output irpt_wrack; + output interrupt_wrce_strb; + output intr2bus_rdack0; + output irpt_rdack; + output p_3_out; + output intr_rd_ce_or_reduce; + output \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ; + output intr_wr_ce_or_reduce; + output \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ; + output s_axi_arready; + output s_axi_wready; + output \Dual.gpio2_OE_reg[0] ; + output \Dual.gpio_OE_reg[0] ; + output \Dual.gpio_Data_Out_reg[0] ; + output \Dual.gpio2_Data_Out_reg[0] ; + output ipif_glbl_irpt_enable_reg_reg_0; + output \Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[31] ; + output \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[31] ; + input Q; + input s_axi_aclk; + input [6:0]\bus2ip_addr_i_reg[8] ; + input bus2ip_rnw_i_reg; + input gpio_xferAck_Reg; + input GPIO_xferAck_i; + input \ip_irpt_enable_reg_reg[0] ; + input \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ; + input [0:0]GPIO2_DBus_i; + input [0:0]GPIO_DBus_i; + input irpt_wrack_d1; + input irpt_rdack_d1; + input ipif_glbl_irpt_enable_reg; + input p_1_in; + input \ip_irpt_enable_reg_reg[1] ; + input ip2Bus_RdAck_intr_reg_hole_d1; + input ip2Bus_WrAck_intr_reg_hole_d1; + input ip2bus_rdack_i_D1; + input is_read; + input [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ; + input ip2bus_wrack_i_D1; + input is_write_reg; + input [1:0]s_axi_wdata; + input [0:0]gpio2_io_t; + input [0:0]gpio_io_t; + input [0:0]gpio_io_o; + input [0:0]gpio2_io_o; + input gpio2_Data_In; + input gpio_Data_In; + input s_axi_aresetn; + + wire Bus_RNW_reg_i_1_n_0; + wire [2:0]D; + wire \Dual.READ_REG2_GEN[0].GPIO2_DBus_i[31]_i_2_n_0 ; + wire \Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[31] ; + wire \Dual.READ_REG_GEN[0].GPIO_DBus_i[31]_i_2_n_0 ; + wire \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[31] ; + wire \Dual.gpio2_Data_Out_reg[0] ; + wire \Dual.gpio2_OE_reg[0] ; + wire \Dual.gpio_Data_Out[0]_i_2_n_0 ; + wire \Dual.gpio_Data_Out_reg[0] ; + wire \Dual.gpio_OE_reg[0] ; + wire \GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1_n_0 ; + wire \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0 ; + wire \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 ; + wire \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0 ; + wire \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ; + wire \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19] ; + wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ; + wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ; + wire \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ; + wire [0:0]GPIO2_DBus_i; + wire [0:0]GPIO_DBus_i; + wire GPIO_xferAck_i; + wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ; + wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ; + wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ; + wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_2_n_0 ; + wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ; + wire Q; + wire [6:0]\bus2ip_addr_i_reg[8] ; + wire bus2ip_rnw_i_reg; + wire gpio2_Data_In; + wire [0:0]gpio2_io_o; + wire [0:0]gpio2_io_t; + wire gpio_Data_In; + wire [0:0]gpio_io_o; + wire [0:0]gpio_io_t; + wire gpio_xferAck_Reg; + wire iGPIO_xferAck_reg; + wire interrupt_wrce_strb; + wire intr2bus_rdack0; + wire intr_rd_ce_or_reduce; + wire intr_wr_ce_or_reduce; + wire ip2Bus_RdAck_intr_reg_hole_d1; + wire ip2Bus_WrAck_intr_reg_hole_d1; + wire \ip2bus_data_i_D1[31]_i_2_n_0 ; + wire \ip2bus_data_i_D1_reg[31] ; + wire ip2bus_rdack_i_D1; + wire ip2bus_wrack_i_D1; + wire \ip_irpt_enable_reg_reg[0] ; + wire \ip_irpt_enable_reg_reg[1] ; + wire ipif_glbl_irpt_enable_reg; + wire ipif_glbl_irpt_enable_reg_reg; + wire ipif_glbl_irpt_enable_reg_reg_0; + wire irpt_rdack; + wire irpt_rdack_d1; + wire irpt_wrack; + wire irpt_wrack_d1; + wire is_read; + wire is_write_reg; + wire p_10_in; + wire p_10_out; + wire p_11_in; + wire p_11_out; + wire p_12_in; + wire p_12_out; + wire p_13_in; + wire p_13_out; + wire p_14_in; + wire p_14_out; + wire p_15_in; + wire p_15_out; + wire p_16_in; + wire p_1_in; + wire p_2_in; + wire p_3_in; + wire p_3_out; + wire p_4_in; + wire p_4_out; + wire p_5_in; + wire p_5_out; + wire p_6_out; + wire p_7_in; + wire p_7_out; + wire p_8_in; + wire p_8_out; + wire p_9_in; + wire pselect_hit_i_1; + wire s_axi_aclk; + wire s_axi_aresetn; + wire s_axi_arready; + wire [1:0]s_axi_wdata; + wire s_axi_wready; + + LUT3 #( + .INIT(8'hB8)) + Bus_RNW_reg_i_1 + (.I0(bus2ip_rnw_i_reg), + .I1(Q), + .I2(ipif_glbl_irpt_enable_reg_reg), + .O(Bus_RNW_reg_i_1_n_0)); + FDRE Bus_RNW_reg_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(Bus_RNW_reg_i_1_n_0), + .Q(ipif_glbl_irpt_enable_reg_reg), + .R(1'b0)); + LUT6 #( + .INIT(64'h00000000FFEF0020)) + \Dual.READ_REG2_GEN[0].GPIO2_DBus_i[31]_i_1 + (.I0(gpio2_Data_In), + .I1(\bus2ip_addr_i_reg[8] [0]), + .I2(\bus2ip_addr_i_reg[8] [1]), + .I3(\Dual.gpio_Data_Out[0]_i_2_n_0 ), + .I4(gpio2_io_t), + .I5(\Dual.READ_REG2_GEN[0].GPIO2_DBus_i[31]_i_2_n_0 ), + .O(\Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[31] )); + LUT6 #( + .INIT(64'hFFFFFFDFFFFFFFFF)) + \Dual.READ_REG2_GEN[0].GPIO2_DBus_i[31]_i_2 + (.I0(bus2ip_rnw_i_reg), + .I1(\bus2ip_addr_i_reg[8] [6]), + .I2(\bus2ip_addr_i_reg[8] [1]), + .I3(GPIO_xferAck_i), + .I4(gpio_xferAck_Reg), + .I5(iGPIO_xferAck_reg), + .O(\Dual.READ_REG2_GEN[0].GPIO2_DBus_i[31]_i_2_n_0 )); + LUT6 #( + .INIT(64'h00000000FFFE0002)) + \Dual.READ_REG_GEN[0].GPIO_DBus_i[31]_i_1 + (.I0(gpio_Data_In), + .I1(\bus2ip_addr_i_reg[8] [1]), + .I2(\bus2ip_addr_i_reg[8] [0]), + .I3(\Dual.gpio_Data_Out[0]_i_2_n_0 ), + .I4(gpio_io_t), + .I5(\Dual.READ_REG_GEN[0].GPIO_DBus_i[31]_i_2_n_0 ), + .O(\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[31] )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFBFF)) + \Dual.READ_REG_GEN[0].GPIO_DBus_i[31]_i_2 + (.I0(\bus2ip_addr_i_reg[8] [6]), + .I1(bus2ip_rnw_i_reg), + .I2(\bus2ip_addr_i_reg[8] [1]), + .I3(iGPIO_xferAck_reg), + .I4(gpio_xferAck_Reg), + .I5(GPIO_xferAck_i), + .O(\Dual.READ_REG_GEN[0].GPIO_DBus_i[31]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \Dual.gpio2_Data_Out[0]_i_1 + (.I0(s_axi_wdata[0]), + .I1(bus2ip_rnw_i_reg), + .I2(\bus2ip_addr_i_reg[8] [0]), + .I3(\bus2ip_addr_i_reg[8] [1]), + .I4(\Dual.gpio_Data_Out[0]_i_2_n_0 ), + .I5(gpio2_io_o), + .O(\Dual.gpio2_Data_Out_reg[0] )); + LUT6 #( + .INIT(64'hFEFFFFFF02000000)) + \Dual.gpio2_OE[0]_i_1 + (.I0(s_axi_wdata[0]), + .I1(\Dual.gpio_Data_Out[0]_i_2_n_0 ), + .I2(bus2ip_rnw_i_reg), + .I3(\bus2ip_addr_i_reg[8] [0]), + .I4(\bus2ip_addr_i_reg[8] [1]), + .I5(gpio2_io_t), + .O(\Dual.gpio2_OE_reg[0] )); + LUT6 #( + .INIT(64'hFFFFFFFE00000002)) + \Dual.gpio_Data_Out[0]_i_1 + (.I0(s_axi_wdata[0]), + .I1(bus2ip_rnw_i_reg), + .I2(\bus2ip_addr_i_reg[8] [1]), + .I3(\bus2ip_addr_i_reg[8] [0]), + .I4(\Dual.gpio_Data_Out[0]_i_2_n_0 ), + .I5(gpio_io_o), + .O(\Dual.gpio_Data_Out_reg[0] )); + LUT2 #( + .INIT(4'hB)) + \Dual.gpio_Data_Out[0]_i_2 + (.I0(\bus2ip_addr_i_reg[8] [6]), + .I1(iGPIO_xferAck_reg), + .O(\Dual.gpio_Data_Out[0]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \Dual.gpio_OE[0]_i_1 + (.I0(s_axi_wdata[0]), + .I1(\Dual.gpio_Data_Out[0]_i_2_n_0 ), + .I2(bus2ip_rnw_i_reg), + .I3(\bus2ip_addr_i_reg[8] [0]), + .I4(\bus2ip_addr_i_reg[8] [1]), + .I5(gpio_io_t), + .O(\Dual.gpio_OE_reg[0] )); + LUT6 #( + .INIT(64'h0040000000000000)) + \GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1 + (.I0(\bus2ip_addr_i_reg[8] [3]), + .I1(\bus2ip_addr_i_reg[8] [2]), + .I2(\bus2ip_addr_i_reg[8] [1]), + .I3(\bus2ip_addr_i_reg[8] [0]), + .I4(\bus2ip_addr_i_reg[8] [6]), + .I5(Q), + .O(\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1_n_0 )); + FDRE \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10] + (.C(s_axi_aclk), + .CE(Q), + .D(\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1_n_0 ), + .Q(p_10_in), + .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0800000000000000)) + \GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1 + (.I0(\bus2ip_addr_i_reg[8] [1]), + .I1(\bus2ip_addr_i_reg[8] [0]), + .I2(\bus2ip_addr_i_reg[8] [3]), + .I3(Q), + .I4(\bus2ip_addr_i_reg[8] [6]), + .I5(\bus2ip_addr_i_reg[8] [2]), + .O(p_8_out)); + FDRE \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] + (.C(s_axi_aclk), + .CE(Q), + .D(p_8_out), + .Q(p_9_in), + .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000000000000800)) + \GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1 + (.I0(Q), + .I1(\bus2ip_addr_i_reg[8] [6]), + .I2(\bus2ip_addr_i_reg[8] [2]), + .I3(\bus2ip_addr_i_reg[8] [3]), + .I4(\bus2ip_addr_i_reg[8] [1]), + .I5(\bus2ip_addr_i_reg[8] [0]), + .O(p_7_out)); + FDRE \GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12] + (.C(s_axi_aclk), + .CE(Q), + .D(p_7_out), + .Q(p_8_in), + .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000080000000000)) + \GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1 + (.I0(Q), + .I1(\bus2ip_addr_i_reg[8] [6]), + .I2(\bus2ip_addr_i_reg[8] [2]), + .I3(\bus2ip_addr_i_reg[8] [3]), + .I4(\bus2ip_addr_i_reg[8] [1]), + .I5(\bus2ip_addr_i_reg[8] [0]), + .O(p_6_out)); + FDRE \GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13] + (.C(s_axi_aclk), + .CE(Q), + .D(p_6_out), + .Q(p_7_in), + .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000400000000000)) + \GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1 + (.I0(\bus2ip_addr_i_reg[8] [2]), + .I1(\bus2ip_addr_i_reg[8] [3]), + .I2(Q), + .I3(\bus2ip_addr_i_reg[8] [6]), + .I4(\bus2ip_addr_i_reg[8] [0]), + .I5(\bus2ip_addr_i_reg[8] [1]), + .O(p_5_out)); + FDRE \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] + (.C(s_axi_aclk), + .CE(Q), + .D(p_5_out), + .Q(\ip2bus_data_i_D1_reg[31] ), + .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0800000000000000)) + \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1 + (.I0(Q), + .I1(\bus2ip_addr_i_reg[8] [6]), + .I2(\bus2ip_addr_i_reg[8] [2]), + .I3(\bus2ip_addr_i_reg[8] [3]), + .I4(\bus2ip_addr_i_reg[8] [1]), + .I5(\bus2ip_addr_i_reg[8] [0]), + .O(p_4_out)); + FDRE \GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15] + (.C(s_axi_aclk), + .CE(Q), + .D(p_4_out), + .Q(p_5_in), + .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000000000008000)) + \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1 + (.I0(Q), + .I1(\bus2ip_addr_i_reg[8] [6]), + .I2(\bus2ip_addr_i_reg[8] [2]), + .I3(\bus2ip_addr_i_reg[8] [3]), + .I4(\bus2ip_addr_i_reg[8] [1]), + .I5(\bus2ip_addr_i_reg[8] [0]), + .O(\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0 )); + FDRE \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16] + (.C(s_axi_aclk), + .CE(Q), + .D(\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0 ), + .Q(p_4_in), + .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000800000000000)) + \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1 + (.I0(Q), + .I1(\bus2ip_addr_i_reg[8] [6]), + .I2(\bus2ip_addr_i_reg[8] [2]), + .I3(\bus2ip_addr_i_reg[8] [3]), + .I4(\bus2ip_addr_i_reg[8] [1]), + .I5(\bus2ip_addr_i_reg[8] [0]), + .O(\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 )); + FDRE \GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17] + (.C(s_axi_aclk), + .CE(Q), + .D(\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 ), + .Q(p_3_in), + .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0080000000000000)) + \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1 + (.I0(\bus2ip_addr_i_reg[8] [3]), + .I1(\bus2ip_addr_i_reg[8] [2]), + .I2(\bus2ip_addr_i_reg[8] [1]), + .I3(\bus2ip_addr_i_reg[8] [0]), + .I4(\bus2ip_addr_i_reg[8] [6]), + .I5(Q), + .O(\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0 )); + FDRE \GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18] + (.C(s_axi_aclk), + .CE(Q), + .D(\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0 ), + .Q(p_2_in), + .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); + LUT3 #( + .INIT(8'hEF)) + \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1 + (.I0(s_axi_wready), + .I1(s_axi_arready), + .I2(s_axi_aresetn), + .O(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); + LUT6 #( + .INIT(64'h8000000000000000)) + \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_2 + (.I0(Q), + .I1(\bus2ip_addr_i_reg[8] [6]), + .I2(\bus2ip_addr_i_reg[8] [2]), + .I3(\bus2ip_addr_i_reg[8] [3]), + .I4(\bus2ip_addr_i_reg[8] [1]), + .I5(\bus2ip_addr_i_reg[8] [0]), + .O(p_15_out)); + FDRE \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg[19] + (.C(s_axi_aclk), + .CE(Q), + .D(p_15_out), + .Q(\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19] ), + .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000000000000008)) + \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1 + (.I0(Q), + .I1(\bus2ip_addr_i_reg[8] [6]), + .I2(\bus2ip_addr_i_reg[8] [2]), + .I3(\bus2ip_addr_i_reg[8] [1]), + .I4(\bus2ip_addr_i_reg[8] [0]), + .I5(\bus2ip_addr_i_reg[8] [3]), + .O(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 )); + FDRE \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] + (.C(s_axi_aclk), + .CE(Q), + .D(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ), + .Q(p_16_in), + .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000000000080000)) + \GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1 + (.I0(Q), + .I1(\bus2ip_addr_i_reg[8] [6]), + .I2(\bus2ip_addr_i_reg[8] [2]), + .I3(\bus2ip_addr_i_reg[8] [1]), + .I4(\bus2ip_addr_i_reg[8] [0]), + .I5(\bus2ip_addr_i_reg[8] [3]), + .O(p_14_out)); + FDRE \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] + (.C(s_axi_aclk), + .CE(Q), + .D(p_14_out), + .Q(p_15_in), + .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000100000000000)) + \GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1 + (.I0(\bus2ip_addr_i_reg[8] [3]), + .I1(\bus2ip_addr_i_reg[8] [2]), + .I2(Q), + .I3(\bus2ip_addr_i_reg[8] [6]), + .I4(\bus2ip_addr_i_reg[8] [0]), + .I5(\bus2ip_addr_i_reg[8] [1]), + .O(p_13_out)); + FDRE \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] + (.C(s_axi_aclk), + .CE(Q), + .D(p_13_out), + .Q(p_14_in), + .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000000008000000)) + \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1 + (.I0(Q), + .I1(\bus2ip_addr_i_reg[8] [6]), + .I2(\bus2ip_addr_i_reg[8] [2]), + .I3(\bus2ip_addr_i_reg[8] [1]), + .I4(\bus2ip_addr_i_reg[8] [0]), + .I5(\bus2ip_addr_i_reg[8] [3]), + .O(p_12_out)); + FDRE \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] + (.C(s_axi_aclk), + .CE(Q), + .D(p_12_out), + .Q(p_13_in), + .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0100000000000000)) + \GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1 + (.I0(\bus2ip_addr_i_reg[8] [1]), + .I1(\bus2ip_addr_i_reg[8] [0]), + .I2(\bus2ip_addr_i_reg[8] [3]), + .I3(Q), + .I4(\bus2ip_addr_i_reg[8] [6]), + .I5(\bus2ip_addr_i_reg[8] [2]), + .O(p_11_out)); + FDRE \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8] + (.C(s_axi_aclk), + .CE(Q), + .D(p_11_out), + .Q(p_12_in), + .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0400000000000000)) + \GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1 + (.I0(\bus2ip_addr_i_reg[8] [1]), + .I1(\bus2ip_addr_i_reg[8] [0]), + .I2(\bus2ip_addr_i_reg[8] [3]), + .I3(Q), + .I4(\bus2ip_addr_i_reg[8] [6]), + .I5(\bus2ip_addr_i_reg[8] [2]), + .O(p_10_out)); + FDRE \GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9] + (.C(s_axi_aclk), + .CE(Q), + .D(p_10_out), + .Q(p_11_in), + .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'hEF)) + \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2 + (.I0(irpt_wrack_d1), + .I1(ipif_glbl_irpt_enable_reg_reg), + .I2(p_8_in), + .O(\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] )); + LUT6 #( + .INIT(64'hAAAAAAA8AAAAAAAA)) + \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_i_1 + (.I0(ipif_glbl_irpt_enable_reg_reg), + .I1(\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19] ), + .I2(p_4_in), + .I3(p_3_in), + .I4(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ), + .I5(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ), + .O(intr_rd_ce_or_reduce)); + LUT5 #( + .INIT(32'h0000FD00)) + \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_i_1 + (.I0(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ), + .I1(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ), + .I2(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_2_n_0 ), + .I3(ipif_glbl_irpt_enable_reg_reg), + .I4(ip2Bus_RdAck_intr_reg_hole_d1), + .O(p_3_out)); + LUT6 #( + .INIT(64'h5555555455555555)) + \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_1 + (.I0(ipif_glbl_irpt_enable_reg_reg), + .I1(\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19] ), + .I2(p_4_in), + .I3(p_3_in), + .I4(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ), + .I5(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ), + .O(intr_wr_ce_or_reduce)); + LUT4 #( + .INIT(16'hFFFE)) + \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2 + (.I0(p_16_in), + .I1(p_14_in), + .I2(p_10_in), + .I3(p_5_in), + .O(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 )); + LUT6 #( + .INIT(64'h0000000000000001)) + \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3 + (.I0(p_12_in), + .I1(p_11_in), + .I2(p_2_in), + .I3(p_15_in), + .I4(p_7_in), + .I5(p_13_in), + .O(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 )); + LUT5 #( + .INIT(32'h000000FD)) + \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_1 + (.I0(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ), + .I1(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ), + .I2(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_2_n_0 ), + .I3(ipif_glbl_irpt_enable_reg_reg), + .I4(ip2Bus_WrAck_intr_reg_hole_d1), + .O(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg )); + LUT3 #( + .INIT(8'hFE)) + \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_2 + (.I0(p_3_in), + .I1(p_4_in), + .I2(\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19] ), + .O(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_2_n_0 )); + LUT6 #( + .INIT(64'h0000000000000100)) + \MEM_DECODE_GEN[0].cs_out_i[0]_i_1 + (.I0(\bus2ip_addr_i_reg[8] [3]), + .I1(\bus2ip_addr_i_reg[8] [2]), + .I2(\bus2ip_addr_i_reg[8] [6]), + .I3(Q), + .I4(\bus2ip_addr_i_reg[8] [4]), + .I5(\bus2ip_addr_i_reg[8] [5]), + .O(pselect_hit_i_1)); + FDRE \MEM_DECODE_GEN[0].cs_out_i_reg[0] + (.C(s_axi_aclk), + .CE(Q), + .D(pselect_hit_i_1), + .Q(iGPIO_xferAck_reg), + .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h0000F0E0)) + intr2bus_rdack_i_1 + (.I0(\ip2bus_data_i_D1_reg[31] ), + .I1(p_8_in), + .I2(ipif_glbl_irpt_enable_reg_reg), + .I3(p_9_in), + .I4(irpt_rdack_d1), + .O(intr2bus_rdack0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h00000F0E)) + intr2bus_wrack_i_1 + (.I0(p_9_in), + .I1(p_8_in), + .I2(ipif_glbl_irpt_enable_reg_reg), + .I3(\ip2bus_data_i_D1_reg[31] ), + .I4(irpt_wrack_d1), + .O(interrupt_wrce_strb)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h10000000)) + \ip2bus_data_i_D1[0]_i_1 + (.I0(p_8_in), + .I1(\ip2bus_data_i_D1_reg[31] ), + .I2(ipif_glbl_irpt_enable_reg_reg), + .I3(p_9_in), + .I4(ipif_glbl_irpt_enable_reg), + .O(D[2])); + LUT5 #( + .INIT(32'h8C808080)) + \ip2bus_data_i_D1[30]_i_1 + (.I0(p_1_in), + .I1(ipif_glbl_irpt_enable_reg_reg), + .I2(p_8_in), + .I3(\ip_irpt_enable_reg_reg[1] ), + .I4(\ip2bus_data_i_D1_reg[31] ), + .O(D[1])); + LUT6 #( + .INIT(64'hFFFFFFFFF8000800)) + \ip2bus_data_i_D1[31]_i_1 + (.I0(\ip2bus_data_i_D1_reg[31] ), + .I1(\ip_irpt_enable_reg_reg[0] ), + .I2(p_8_in), + .I3(ipif_glbl_irpt_enable_reg_reg), + .I4(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ), + .I5(\ip2bus_data_i_D1[31]_i_2_n_0 ), + .O(D[0])); + LUT6 #( + .INIT(64'hAABAAAAAAA8AAAAA)) + \ip2bus_data_i_D1[31]_i_2 + (.I0(GPIO2_DBus_i), + .I1(\bus2ip_addr_i_reg[8] [1]), + .I2(bus2ip_rnw_i_reg), + .I3(\bus2ip_addr_i_reg[8] [6]), + .I4(iGPIO_xferAck_reg), + .I5(GPIO_DBus_i), + .O(\ip2bus_data_i_D1[31]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFB08)) + ipif_glbl_irpt_enable_reg_i_1 + (.I0(s_axi_wdata[1]), + .I1(p_9_in), + .I2(ipif_glbl_irpt_enable_reg_reg), + .I3(ipif_glbl_irpt_enable_reg), + .O(ipif_glbl_irpt_enable_reg_reg_0)); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT4 #( + .INIT(16'hCCC8)) + irpt_rdack_d1_i_1 + (.I0(p_9_in), + .I1(ipif_glbl_irpt_enable_reg_reg), + .I2(p_8_in), + .I3(\ip2bus_data_i_D1_reg[31] ), + .O(irpt_rdack)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'h3332)) + irpt_wrack_d1_i_1 + (.I0(\ip2bus_data_i_D1_reg[31] ), + .I1(ipif_glbl_irpt_enable_reg_reg), + .I2(p_8_in), + .I3(p_9_in), + .O(irpt_wrack)); + LUT6 #( + .INIT(64'hAAAAAAAAAAAEAAAA)) + s_axi_arready_INST_0 + (.I0(ip2bus_rdack_i_D1), + .I1(is_read), + .I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]), + .I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]), + .I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]), + .I5(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]), + .O(s_axi_arready)); + LUT6 #( + .INIT(64'hAAAAAAAAAAAEAAAA)) + s_axi_wready_INST_0 + (.I0(ip2bus_wrack_i_D1), + .I1(is_write_reg), + .I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]), + .I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]), + .I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]), + .I5(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]), + .O(s_axi_wready)); +endmodule + +(* C_ALL_INPUTS = "0" *) (* C_ALL_INPUTS_2 = "1" *) (* C_ALL_OUTPUTS = "1" *) +(* C_ALL_OUTPUTS_2 = "0" *) (* C_DOUT_DEFAULT = "0" *) (* C_DOUT_DEFAULT_2 = "0" *) +(* C_FAMILY = "zynq" *) (* C_GPIO2_WIDTH = "1" *) (* C_GPIO_WIDTH = "1" *) +(* C_INTERRUPT_PRESENT = "1" *) (* C_IS_DUAL = "1" *) (* C_S_AXI_ADDR_WIDTH = "9" *) +(* C_S_AXI_DATA_WIDTH = "32" *) (* C_TRI_DEFAULT = "-1" *) (* C_TRI_DEFAULT_2 = "-1" *) +(* ORIG_REF_NAME = "axi_gpio" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_group = "LOGICORE" *) +module Arty_Z7_20_axi_gpio_0_0_axi_gpio + (s_axi_aclk, + s_axi_aresetn, + s_axi_awaddr, + s_axi_awvalid, + s_axi_awready, + s_axi_wdata, + s_axi_wstrb, + s_axi_wvalid, + s_axi_wready, + s_axi_bresp, + s_axi_bvalid, + s_axi_bready, + s_axi_araddr, + s_axi_arvalid, + s_axi_arready, + s_axi_rdata, + s_axi_rresp, + s_axi_rvalid, + s_axi_rready, + ip2intc_irpt, + gpio_io_i, + gpio_io_o, + gpio_io_t, + gpio2_io_i, + gpio2_io_o, + gpio2_io_t); + (* max_fanout = "10000" *) (* sigis = "Clk" *) input s_axi_aclk; + (* max_fanout = "10000" *) (* sigis = "Rst" *) input s_axi_aresetn; + input [8:0]s_axi_awaddr; + input s_axi_awvalid; + output s_axi_awready; + input [31:0]s_axi_wdata; + input [3:0]s_axi_wstrb; + input s_axi_wvalid; + output s_axi_wready; + output [1:0]s_axi_bresp; + output s_axi_bvalid; + input s_axi_bready; + input [8:0]s_axi_araddr; + input s_axi_arvalid; + output s_axi_arready; + output [31:0]s_axi_rdata; + output [1:0]s_axi_rresp; + output s_axi_rvalid; + input s_axi_rready; + (* sigis = "INTR_LEVEL_HIGH" *) output ip2intc_irpt; + input [0:0]gpio_io_i; + output [0:0]gpio_io_o; + output [0:0]gpio_io_t; + input [0:0]gpio2_io_i; + output [0:0]gpio2_io_o; + output [0:0]gpio2_io_t; + + wire \ ; + wire AXI_LITE_IPIF_I_n_15; + wire AXI_LITE_IPIF_I_n_18; + wire AXI_LITE_IPIF_I_n_21; + wire AXI_LITE_IPIF_I_n_22; + wire AXI_LITE_IPIF_I_n_23; + wire AXI_LITE_IPIF_I_n_24; + wire AXI_LITE_IPIF_I_n_25; + wire AXI_LITE_IPIF_I_n_26; + wire AXI_LITE_IPIF_I_n_27; + wire [31:31]GPIO2_DBus_i; + wire GPIO2_intr; + wire [31:31]GPIO_DBus_i; + wire GPIO_intr; + wire GPIO_xferAck_i; + wire \INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_1 ; + wire \INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_8 ; + wire \INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_9 ; + wire IP2INTC_Irpt_i; + wire \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ; + wire \I_SLAVE_ATTACHMENT/I_DECODER/p_6_in ; + wire \I_SLAVE_ATTACHMENT/rst ; + wire [1:1]bus2ip_cs; + wire bus2ip_reset_i_1_n_0; + wire bus2ip_rnw; + wire gpio2_Data_In; + wire [0:0]gpio2_io_i; + wire [0:0]gpio2_io_o; + wire [0:0]gpio2_io_t; + wire gpio_Data_In; + wire [0:0]gpio_io_i; + wire [0:0]gpio_io_o; + wire [0:0]gpio_io_t; + wire gpio_xferAck_Reg; + wire interrupt_wrce_strb; + wire intr2bus_rdack; + wire intr2bus_rdack0; + wire intr2bus_wrack; + wire intr_rd_ce_or_reduce; + wire intr_wr_ce_or_reduce; + wire ip2Bus_RdAck_intr_reg_hole; + wire ip2Bus_RdAck_intr_reg_hole_d1; + wire ip2Bus_WrAck_intr_reg_hole; + wire ip2Bus_WrAck_intr_reg_hole_d1; + wire [31:31]ip2bus_data_i; + wire [0:31]ip2bus_data_i_D1; + wire ip2bus_rdack_i; + wire ip2bus_rdack_i_D1; + wire ip2bus_wrack_i; + wire ip2bus_wrack_i_D1; + wire ip2intc_irpt; + wire ipif_glbl_irpt_enable_reg; + wire irpt_rdack; + wire irpt_rdack_d1; + wire irpt_wrack; + wire irpt_wrack_d1; + wire [0:30]p_0_out; + wire p_1_in; + wire p_3_out; + (* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Clk" *) wire s_axi_aclk; + wire [8:0]s_axi_araddr; + (* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Rst" *) wire s_axi_aresetn; + wire s_axi_arready; + wire s_axi_arvalid; + wire [8:0]s_axi_awaddr; + wire s_axi_awvalid; + wire s_axi_bready; + wire s_axi_bvalid; + wire [31:0]\^s_axi_rdata ; + wire s_axi_rready; + wire s_axi_rvalid; + wire [31:0]s_axi_wdata; + wire s_axi_wready; + wire s_axi_wvalid; + + assign s_axi_awready = s_axi_wready; + assign s_axi_bresp[1] = \ ; + assign s_axi_bresp[0] = \ ; + assign s_axi_rdata[31] = \^s_axi_rdata [31]; + assign s_axi_rdata[30] = \ ; + assign s_axi_rdata[29] = \ ; + assign s_axi_rdata[28] = \ ; + assign s_axi_rdata[27] = \ ; + assign s_axi_rdata[26] = \ ; + assign s_axi_rdata[25] = \ ; + assign s_axi_rdata[24] = \ ; + assign s_axi_rdata[23] = \ ; + assign s_axi_rdata[22] = \ ; + assign s_axi_rdata[21] = \ ; + assign s_axi_rdata[20] = \ ; + assign s_axi_rdata[19] = \ ; + assign s_axi_rdata[18] = \ ; + assign s_axi_rdata[17] = \ ; + assign s_axi_rdata[16] = \ ; + assign s_axi_rdata[15] = \ ; + assign s_axi_rdata[14] = \ ; + assign s_axi_rdata[13] = \ ; + assign s_axi_rdata[12] = \ ; + assign s_axi_rdata[11] = \ ; + assign s_axi_rdata[10] = \ ; + assign s_axi_rdata[9] = \ ; + assign s_axi_rdata[8] = \ ; + assign s_axi_rdata[7] = \ ; + assign s_axi_rdata[6] = \ ; + assign s_axi_rdata[5] = \ ; + assign s_axi_rdata[4] = \ ; + assign s_axi_rdata[3] = \ ; + assign s_axi_rdata[2] = \ ; + assign s_axi_rdata[1:0] = \^s_axi_rdata [1:0]; + assign s_axi_rresp[1] = \ ; + assign s_axi_rresp[0] = \ ; + Arty_Z7_20_axi_gpio_0_0_axi_lite_ipif AXI_LITE_IPIF_I + (.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ), + .D({p_0_out[0],p_0_out[30],ip2bus_data_i}), + .\Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[31] (AXI_LITE_IPIF_I_n_26), + .\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[31] (AXI_LITE_IPIF_I_n_27), + .\Dual.gpio2_Data_Out_reg[0] (AXI_LITE_IPIF_I_n_24), + .\Dual.gpio2_OE_reg[0] (AXI_LITE_IPIF_I_n_21), + .\Dual.gpio_Data_Out_reg[0] (AXI_LITE_IPIF_I_n_23), + .\Dual.gpio_OE_reg[0] (AXI_LITE_IPIF_I_n_22), + .\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] (\INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_1 ), + .\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] (AXI_LITE_IPIF_I_n_18), + .GPIO2_DBus_i(GPIO2_DBus_i), + .GPIO_DBus_i(GPIO_DBus_i), + .GPIO_xferAck_i(GPIO_xferAck_i), + .\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg (AXI_LITE_IPIF_I_n_15), + .Q({ip2bus_data_i_D1[0],ip2bus_data_i_D1[30],ip2bus_data_i_D1[31]}), + .bus2ip_cs(bus2ip_cs), + .bus2ip_rnw(bus2ip_rnw), + .gpio2_Data_In(gpio2_Data_In), + .gpio2_io_o(gpio2_io_o), + .gpio2_io_t(gpio2_io_t), + .gpio_Data_In(gpio_Data_In), + .gpio_io_o(gpio_io_o), + .gpio_io_t(gpio_io_t), + .gpio_xferAck_Reg(gpio_xferAck_Reg), + .interrupt_wrce_strb(interrupt_wrce_strb), + .intr2bus_rdack0(intr2bus_rdack0), + .intr2bus_wrack(intr2bus_wrack), + .intr_rd_ce_or_reduce(intr_rd_ce_or_reduce), + .intr_wr_ce_or_reduce(intr_wr_ce_or_reduce), + .ip2Bus_RdAck_intr_reg_hole_d1(ip2Bus_RdAck_intr_reg_hole_d1), + .ip2Bus_WrAck_intr_reg_hole(ip2Bus_WrAck_intr_reg_hole), + .ip2Bus_WrAck_intr_reg_hole_d1(ip2Bus_WrAck_intr_reg_hole_d1), + .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1), + .ip2bus_wrack_i(ip2bus_wrack_i), + .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1), + .\ip_irpt_enable_reg_reg[0] (\INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_8 ), + .\ip_irpt_enable_reg_reg[1] (\INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_9 ), + .ipif_glbl_irpt_enable_reg(ipif_glbl_irpt_enable_reg), + .ipif_glbl_irpt_enable_reg_reg(AXI_LITE_IPIF_I_n_25), + .irpt_rdack(irpt_rdack), + .irpt_rdack_d1(irpt_rdack_d1), + .irpt_wrack(irpt_wrack), + .irpt_wrack_d1(irpt_wrack_d1), + .p_1_in(p_1_in), + .p_3_out(p_3_out), + .p_6_in(\I_SLAVE_ATTACHMENT/I_DECODER/p_6_in ), + .rst(\I_SLAVE_ATTACHMENT/rst ), + .s_axi_aclk(s_axi_aclk), + .s_axi_araddr(s_axi_araddr[8:2]), + .s_axi_aresetn(s_axi_aresetn), + .s_axi_arready(s_axi_arready), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_awaddr(s_axi_awaddr[8:2]), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_bready(s_axi_bready), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_rdata({\^s_axi_rdata [31],\^s_axi_rdata [1:0]}), + .s_axi_rready(s_axi_rready), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_wdata({s_axi_wdata[31],s_axi_wdata[0]}), + .s_axi_wready(s_axi_wready), + .s_axi_wvalid(s_axi_wvalid)); + GND GND + (.G(\ )); + Arty_Z7_20_axi_gpio_0_0_interrupt_control \INTR_CTRLR_GEN.INTERRUPT_CONTROL_I + (.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ), + .\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] (AXI_LITE_IPIF_I_n_25), + .\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 (\INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_1 ), + .GPIO2_intr(GPIO2_intr), + .GPIO_intr(GPIO_intr), + .IP2INTC_Irpt_i(IP2INTC_Irpt_i), + .interrupt_wrce_strb(interrupt_wrce_strb), + .intr2bus_rdack(intr2bus_rdack), + .intr2bus_rdack0(intr2bus_rdack0), + .intr2bus_wrack(intr2bus_wrack), + .\ip_irpt_enable_reg_reg[0]_0 (\INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_8 ), + .\ip_irpt_enable_reg_reg[1]_0 (\INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_9 ), + .ipif_glbl_irpt_enable_reg(ipif_glbl_irpt_enable_reg), + .irpt_rdack(irpt_rdack), + .irpt_rdack_d1(irpt_rdack_d1), + .irpt_wrack(irpt_wrack), + .irpt_wrack_d1(irpt_wrack_d1), + .irpt_wrack_d1_reg_0(AXI_LITE_IPIF_I_n_18), + .p_1_in(p_1_in), + .p_6_in(\I_SLAVE_ATTACHMENT/I_DECODER/p_6_in ), + .rst(\I_SLAVE_ATTACHMENT/rst ), + .s_axi_aclk(s_axi_aclk), + .s_axi_wdata(s_axi_wdata[1:0])); + FDRE \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(intr_rd_ce_or_reduce), + .Q(ip2Bus_RdAck_intr_reg_hole_d1), + .R(\I_SLAVE_ATTACHMENT/rst )); + FDRE \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(p_3_out), + .Q(ip2Bus_RdAck_intr_reg_hole), + .R(\I_SLAVE_ATTACHMENT/rst )); + FDRE \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(intr_wr_ce_or_reduce), + .Q(ip2Bus_WrAck_intr_reg_hole_d1), + .R(\I_SLAVE_ATTACHMENT/rst )); + FDRE \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(AXI_LITE_IPIF_I_n_15), + .Q(ip2Bus_WrAck_intr_reg_hole), + .R(\I_SLAVE_ATTACHMENT/rst )); + (* sigis = "INTR_LEVEL_HIGH" *) + FDRE \INTR_CTRLR_GEN.ip2intc_irpt_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(IP2INTC_Irpt_i), + .Q(ip2intc_irpt), + .R(\I_SLAVE_ATTACHMENT/rst )); + LUT1 #( + .INIT(2'h1)) + bus2ip_reset_i_1 + (.I0(s_axi_aresetn), + .O(bus2ip_reset_i_1_n_0)); + FDRE bus2ip_reset_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(bus2ip_reset_i_1_n_0), + .Q(\I_SLAVE_ATTACHMENT/rst ), + .R(1'b0)); + Arty_Z7_20_axi_gpio_0_0_GPIO_Core gpio_core_1 + (.\Dual.gpio2_Data_In_reg[0]_0 (AXI_LITE_IPIF_I_n_26), + .\Dual.gpio_Data_In_reg[0]_0 (AXI_LITE_IPIF_I_n_27), + .GPIO2_DBus_i(GPIO2_DBus_i), + .GPIO2_intr(GPIO2_intr), + .GPIO_DBus_i(GPIO_DBus_i), + .GPIO_intr(GPIO_intr), + .GPIO_xferAck_i(GPIO_xferAck_i), + .bus2ip_cs(bus2ip_cs), + .bus2ip_rnw(bus2ip_rnw), + .bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_21), + .bus2ip_rnw_i_reg_0(AXI_LITE_IPIF_I_n_22), + .bus2ip_rnw_i_reg_1(AXI_LITE_IPIF_I_n_23), + .bus2ip_rnw_i_reg_2(AXI_LITE_IPIF_I_n_24), + .gpio2_Data_In(gpio2_Data_In), + .gpio2_io_i(gpio2_io_i), + .gpio2_io_o(gpio2_io_o), + .gpio2_io_t(gpio2_io_t), + .gpio_Data_In(gpio_Data_In), + .gpio_io_i(gpio_io_i), + .gpio_io_o(gpio_io_o), + .gpio_io_t(gpio_io_t), + .gpio_xferAck_Reg(gpio_xferAck_Reg), + .intr2bus_rdack(intr2bus_rdack), + .ip2Bus_RdAck_intr_reg_hole(ip2Bus_RdAck_intr_reg_hole), + .ip2bus_rdack_i(ip2bus_rdack_i), + .rst(\I_SLAVE_ATTACHMENT/rst ), + .s_axi_aclk(s_axi_aclk)); + FDRE \ip2bus_data_i_D1_reg[0] + (.C(s_axi_aclk), + .CE(1'b1), + .D(p_0_out[0]), + .Q(ip2bus_data_i_D1[0]), + .R(\I_SLAVE_ATTACHMENT/rst )); + FDRE \ip2bus_data_i_D1_reg[30] + (.C(s_axi_aclk), + .CE(1'b1), + .D(p_0_out[30]), + .Q(ip2bus_data_i_D1[30]), + .R(\I_SLAVE_ATTACHMENT/rst )); + FDRE \ip2bus_data_i_D1_reg[31] + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_data_i), + .Q(ip2bus_data_i_D1[31]), + .R(\I_SLAVE_ATTACHMENT/rst )); + FDRE ip2bus_rdack_i_D1_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_rdack_i), + .Q(ip2bus_rdack_i_D1), + .R(\I_SLAVE_ATTACHMENT/rst )); + FDRE ip2bus_wrack_i_D1_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(ip2bus_wrack_i), + .Q(ip2bus_wrack_i_D1), + .R(\I_SLAVE_ATTACHMENT/rst )); +endmodule + +(* ORIG_REF_NAME = "axi_lite_ipif" *) +module Arty_Z7_20_axi_gpio_0_0_axi_lite_ipif + (p_6_in, + bus2ip_rnw, + bus2ip_cs, + Bus_RNW_reg, + s_axi_rvalid, + s_axi_bvalid, + D, + irpt_wrack, + interrupt_wrce_strb, + intr2bus_rdack0, + irpt_rdack, + p_3_out, + intr_rd_ce_or_reduce, + \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg , + intr_wr_ce_or_reduce, + ip2bus_wrack_i, + \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] , + s_axi_arready, + s_axi_wready, + \Dual.gpio2_OE_reg[0] , + \Dual.gpio_OE_reg[0] , + \Dual.gpio_Data_Out_reg[0] , + \Dual.gpio2_Data_Out_reg[0] , + ipif_glbl_irpt_enable_reg_reg, + \Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[31] , + \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[31] , + s_axi_rdata, + s_axi_aclk, + rst, + gpio_xferAck_Reg, + GPIO_xferAck_i, + \ip_irpt_enable_reg_reg[0] , + \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] , + GPIO2_DBus_i, + GPIO_DBus_i, + irpt_wrack_d1, + irpt_rdack_d1, + ipif_glbl_irpt_enable_reg, + p_1_in, + \ip_irpt_enable_reg_reg[1] , + ip2Bus_RdAck_intr_reg_hole_d1, + ip2Bus_WrAck_intr_reg_hole_d1, + intr2bus_wrack, + ip2Bus_WrAck_intr_reg_hole, + s_axi_arvalid, + s_axi_awvalid, + s_axi_wvalid, + s_axi_araddr, + s_axi_awaddr, + s_axi_rready, + s_axi_bready, + ip2bus_rdack_i_D1, + ip2bus_wrack_i_D1, + s_axi_wdata, + gpio2_io_t, + gpio_io_t, + gpio_io_o, + gpio2_io_o, + gpio2_Data_In, + gpio_Data_In, + s_axi_aresetn, + Q); + output p_6_in; + output bus2ip_rnw; + output [0:0]bus2ip_cs; + output Bus_RNW_reg; + output s_axi_rvalid; + output s_axi_bvalid; + output [2:0]D; + output irpt_wrack; + output interrupt_wrce_strb; + output intr2bus_rdack0; + output irpt_rdack; + output p_3_out; + output intr_rd_ce_or_reduce; + output \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ; + output intr_wr_ce_or_reduce; + output ip2bus_wrack_i; + output \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ; + output s_axi_arready; + output s_axi_wready; + output \Dual.gpio2_OE_reg[0] ; + output \Dual.gpio_OE_reg[0] ; + output \Dual.gpio_Data_Out_reg[0] ; + output \Dual.gpio2_Data_Out_reg[0] ; + output ipif_glbl_irpt_enable_reg_reg; + output \Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[31] ; + output \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[31] ; + output [2:0]s_axi_rdata; + input s_axi_aclk; + input rst; + input gpio_xferAck_Reg; + input GPIO_xferAck_i; + input \ip_irpt_enable_reg_reg[0] ; + input \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ; + input [0:0]GPIO2_DBus_i; + input [0:0]GPIO_DBus_i; + input irpt_wrack_d1; + input irpt_rdack_d1; + input ipif_glbl_irpt_enable_reg; + input p_1_in; + input \ip_irpt_enable_reg_reg[1] ; + input ip2Bus_RdAck_intr_reg_hole_d1; + input ip2Bus_WrAck_intr_reg_hole_d1; + input intr2bus_wrack; + input ip2Bus_WrAck_intr_reg_hole; + input s_axi_arvalid; + input s_axi_awvalid; + input s_axi_wvalid; + input [6:0]s_axi_araddr; + input [6:0]s_axi_awaddr; + input s_axi_rready; + input s_axi_bready; + input ip2bus_rdack_i_D1; + input ip2bus_wrack_i_D1; + input [1:0]s_axi_wdata; + input [0:0]gpio2_io_t; + input [0:0]gpio_io_t; + input [0:0]gpio_io_o; + input [0:0]gpio2_io_o; + input gpio2_Data_In; + input gpio_Data_In; + input s_axi_aresetn; + input [2:0]Q; + + wire Bus_RNW_reg; + wire [2:0]D; + wire \Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[31] ; + wire \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[31] ; + wire \Dual.gpio2_Data_Out_reg[0] ; + wire \Dual.gpio2_OE_reg[0] ; + wire \Dual.gpio_Data_Out_reg[0] ; + wire \Dual.gpio_OE_reg[0] ; + wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ; + wire \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ; + wire [0:0]GPIO2_DBus_i; + wire [0:0]GPIO_DBus_i; + wire GPIO_xferAck_i; + wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ; + wire [2:0]Q; + wire [0:0]bus2ip_cs; + wire bus2ip_rnw; + wire gpio2_Data_In; + wire [0:0]gpio2_io_o; + wire [0:0]gpio2_io_t; + wire gpio_Data_In; + wire [0:0]gpio_io_o; + wire [0:0]gpio_io_t; + wire gpio_xferAck_Reg; + wire interrupt_wrce_strb; + wire intr2bus_rdack0; + wire intr2bus_wrack; + wire intr_rd_ce_or_reduce; + wire intr_wr_ce_or_reduce; + wire ip2Bus_RdAck_intr_reg_hole_d1; + wire ip2Bus_WrAck_intr_reg_hole; + wire ip2Bus_WrAck_intr_reg_hole_d1; + wire ip2bus_rdack_i_D1; + wire ip2bus_wrack_i; + wire ip2bus_wrack_i_D1; + wire \ip_irpt_enable_reg_reg[0] ; + wire \ip_irpt_enable_reg_reg[1] ; + wire ipif_glbl_irpt_enable_reg; + wire ipif_glbl_irpt_enable_reg_reg; + wire irpt_rdack; + wire irpt_rdack_d1; + wire irpt_wrack; + wire irpt_wrack_d1; + wire p_1_in; + wire p_3_out; + wire p_6_in; + wire rst; + wire s_axi_aclk; + wire [6:0]s_axi_araddr; + wire s_axi_aresetn; + wire s_axi_arready; + wire s_axi_arvalid; + wire [6:0]s_axi_awaddr; + wire s_axi_awvalid; + wire s_axi_bready; + wire s_axi_bvalid; + wire [2:0]s_axi_rdata; + wire s_axi_rready; + wire s_axi_rvalid; + wire [1:0]s_axi_wdata; + wire s_axi_wready; + wire s_axi_wvalid; + + Arty_Z7_20_axi_gpio_0_0_slave_attachment I_SLAVE_ATTACHMENT + (.D(D), + .\Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[31] (\Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[31] ), + .\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[31] (\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[31] ), + .\Dual.gpio2_Data_Out_reg[0] (\Dual.gpio2_Data_Out_reg[0] ), + .\Dual.gpio2_OE_reg[0] (bus2ip_rnw), + .\Dual.gpio2_OE_reg[0]_0 (\Dual.gpio2_OE_reg[0] ), + .\Dual.gpio_Data_Out_reg[0] (\Dual.gpio_Data_Out_reg[0] ), + .\Dual.gpio_OE_reg[0] (\Dual.gpio_OE_reg[0] ), + .\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] (\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ), + .\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] (\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ), + .GPIO2_DBus_i(GPIO2_DBus_i), + .GPIO_DBus_i(GPIO_DBus_i), + .GPIO_xferAck_i(GPIO_xferAck_i), + .\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg (\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ), + .Q(Q), + .gpio2_Data_In(gpio2_Data_In), + .gpio2_io_o(gpio2_io_o), + .gpio2_io_t(gpio2_io_t), + .gpio_Data_In(gpio_Data_In), + .gpio_io_o(gpio_io_o), + .gpio_io_t(gpio_io_t), + .gpio_xferAck_Reg(gpio_xferAck_Reg), + .iGPIO_xferAck_reg(bus2ip_cs), + .interrupt_wrce_strb(interrupt_wrce_strb), + .intr2bus_rdack0(intr2bus_rdack0), + .intr2bus_wrack(intr2bus_wrack), + .intr_rd_ce_or_reduce(intr_rd_ce_or_reduce), + .intr_wr_ce_or_reduce(intr_wr_ce_or_reduce), + .ip2Bus_RdAck_intr_reg_hole_d1(ip2Bus_RdAck_intr_reg_hole_d1), + .ip2Bus_WrAck_intr_reg_hole(ip2Bus_WrAck_intr_reg_hole), + .ip2Bus_WrAck_intr_reg_hole_d1(ip2Bus_WrAck_intr_reg_hole_d1), + .\ip2bus_data_i_D1_reg[31] (p_6_in), + .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1), + .ip2bus_wrack_i(ip2bus_wrack_i), + .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1), + .\ip_irpt_enable_reg_reg[0] (\ip_irpt_enable_reg_reg[0] ), + .\ip_irpt_enable_reg_reg[1] (\ip_irpt_enable_reg_reg[1] ), + .ipif_glbl_irpt_enable_reg(ipif_glbl_irpt_enable_reg), + .ipif_glbl_irpt_enable_reg_reg(Bus_RNW_reg), + .ipif_glbl_irpt_enable_reg_reg_0(ipif_glbl_irpt_enable_reg_reg), + .irpt_rdack(irpt_rdack), + .irpt_rdack_d1(irpt_rdack_d1), + .irpt_wrack(irpt_wrack), + .irpt_wrack_d1(irpt_wrack_d1), + .p_1_in(p_1_in), + .p_3_out(p_3_out), + .rst(rst), + .s_axi_aclk(s_axi_aclk), + .s_axi_araddr(s_axi_araddr), + .s_axi_aresetn(s_axi_aresetn), + .s_axi_arready(s_axi_arready), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_bready(s_axi_bready), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_rdata(s_axi_rdata), + .s_axi_rready(s_axi_rready), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_wdata(s_axi_wdata), + .s_axi_wready(s_axi_wready), + .s_axi_wvalid(s_axi_wvalid)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_gpio_0_0_cdc_sync + (gpio_data_in_xor, + scndry_vect_out, + gpio_Data_In, + gpio_io_i, + s_axi_aclk); + output gpio_data_in_xor; + output [0:0]scndry_vect_out; + input gpio_Data_In; + input [0:0]gpio_io_i; + input s_axi_aclk; + + wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2_n_0 ; + wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3_n_0 ; + wire Q; + wire gpio_Data_In; + wire gpio_data_in_xor; + wire [0:0]gpio_io_i; + wire s_axi_aclk; + wire [0:0]scndry_vect_out; + + LUT2 #( + .INIT(4'h6)) + \Dual.gen_interrupt_dual.gpio_data_in_xor_reg[0]_i_1 + (.I0(gpio_Data_In), + .I1(scndry_vect_out), + .O(gpio_data_in_xor)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(Q), + .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2_n_0 ), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2_n_0 ), + .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3_n_0 ), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3_n_0 ), + .Q(scndry_vect_out), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio_io_i), + .Q(Q), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_gpio_0_0_cdc_sync_0 + (gpio2_data_in_xor, + scndry_vect_out, + gpio2_Data_In, + gpio2_io_i, + s_axi_aclk); + output gpio2_data_in_xor; + output [0:0]scndry_vect_out; + input gpio2_Data_In; + input [0:0]gpio2_io_i; + input s_axi_aclk; + + wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2_n_0 ; + wire \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3_n_0 ; + wire Q; + wire gpio2_Data_In; + wire gpio2_data_in_xor; + wire [0:0]gpio2_io_i; + wire s_axi_aclk; + wire [0:0]scndry_vect_out; + + LUT2 #( + .INIT(4'h6)) + \Dual.gen_interrupt_dual.gpio2_data_in_xor_reg[0]_i_1 + (.I0(gpio2_Data_In), + .I1(scndry_vect_out), + .O(gpio2_data_in_xor)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 + (.C(s_axi_aclk), + .CE(1'b1), + .D(Q), + .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2_n_0 ), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 + (.C(s_axi_aclk), + .CE(1'b1), + .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2_n_0 ), + .Q(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3_n_0 ), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 + (.C(s_axi_aclk), + .CE(1'b1), + .D(\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3_n_0 ), + .Q(scndry_vect_out), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_aclk), + .CE(1'b1), + .D(gpio2_io_i), + .Q(Q), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "interrupt_control" *) +module Arty_Z7_20_axi_gpio_0_0_interrupt_control + (irpt_wrack_d1, + \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 , + p_1_in, + intr2bus_wrack, + irpt_rdack_d1, + intr2bus_rdack, + ipif_glbl_irpt_enable_reg, + IP2INTC_Irpt_i, + \ip_irpt_enable_reg_reg[0]_0 , + \ip_irpt_enable_reg_reg[1]_0 , + rst, + irpt_wrack, + s_axi_aclk, + GPIO_intr, + GPIO2_intr, + interrupt_wrce_strb, + irpt_rdack, + intr2bus_rdack0, + \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] , + irpt_wrack_d1_reg_0, + s_axi_wdata, + p_6_in, + Bus_RNW_reg); + output irpt_wrack_d1; + output \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ; + output p_1_in; + output intr2bus_wrack; + output irpt_rdack_d1; + output intr2bus_rdack; + output ipif_glbl_irpt_enable_reg; + output IP2INTC_Irpt_i; + output \ip_irpt_enable_reg_reg[0]_0 ; + output \ip_irpt_enable_reg_reg[1]_0 ; + input rst; + input irpt_wrack; + input s_axi_aclk; + input GPIO_intr; + input GPIO2_intr; + input interrupt_wrce_strb; + input irpt_rdack; + input intr2bus_rdack0; + input \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ; + input irpt_wrack_d1_reg_0; + input [1:0]s_axi_wdata; + input p_6_in; + input Bus_RNW_reg; + + wire Bus_RNW_reg; + wire \DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0 ; + wire \DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0 ; + wire \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ; + wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0 ; + wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ; + wire \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1_n_0 ; + wire GPIO2_intr; + wire GPIO_intr; + wire IP2INTC_Irpt_i; + wire interrupt_wrce_strb; + wire intr2bus_rdack; + wire intr2bus_rdack0; + wire intr2bus_wrack; + wire \ip_irpt_enable_reg[0]_i_1_n_0 ; + wire \ip_irpt_enable_reg[1]_i_1_n_0 ; + wire \ip_irpt_enable_reg_reg[0]_0 ; + wire \ip_irpt_enable_reg_reg[1]_0 ; + wire ipif_glbl_irpt_enable_reg; + wire irpt_dly1; + wire irpt_dly2; + wire irpt_rdack; + wire irpt_rdack_d1; + wire irpt_wrack; + wire irpt_wrack_d1; + wire irpt_wrack_d1_reg_0; + wire p_1_in; + wire p_6_in; + wire rst; + wire s_axi_aclk; + wire [1:0]s_axi_wdata; + + FDSE \DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly1_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(GPIO_intr), + .Q(irpt_dly1), + .S(rst)); + FDSE \DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly2_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(irpt_dly1), + .Q(irpt_dly2), + .S(rst)); + FDSE \DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly1_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(GPIO2_intr), + .Q(\DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0 ), + .S(rst)); + FDSE \DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly2_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(\DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0 ), + .Q(\DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0 ), + .S(rst)); + LUT5 #( + .INIT(32'hBAFF7530)) + \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1 + (.I0(irpt_wrack_d1_reg_0), + .I1(irpt_dly2), + .I2(irpt_dly1), + .I3(s_axi_wdata[0]), + .I4(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ), + .O(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0 )); + FDRE \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0 ), + .Q(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ), + .R(rst)); + LUT5 #( + .INIT(32'hBAFF7530)) + \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1 + (.I0(irpt_wrack_d1_reg_0), + .I1(\DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0 ), + .I2(\DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0 ), + .I3(s_axi_wdata[1]), + .I4(p_1_in), + .O(\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1_n_0 )); + FDRE \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1_n_0 ), + .Q(p_1_in), + .R(rst)); + LUT5 #( + .INIT(32'hAA808080)) + \INTR_CTRLR_GEN.ip2intc_irpt_i_1 + (.I0(ipif_glbl_irpt_enable_reg), + .I1(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ), + .I2(\ip_irpt_enable_reg_reg[0]_0 ), + .I3(p_1_in), + .I4(\ip_irpt_enable_reg_reg[1]_0 ), + .O(IP2INTC_Irpt_i)); + FDRE intr2bus_rdack_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(intr2bus_rdack0), + .Q(intr2bus_rdack), + .R(rst)); + FDRE intr2bus_wrack_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(interrupt_wrce_strb), + .Q(intr2bus_wrack), + .R(rst)); + LUT4 #( + .INIT(16'hFB08)) + \ip_irpt_enable_reg[0]_i_1 + (.I0(s_axi_wdata[0]), + .I1(p_6_in), + .I2(Bus_RNW_reg), + .I3(\ip_irpt_enable_reg_reg[0]_0 ), + .O(\ip_irpt_enable_reg[0]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFB08)) + \ip_irpt_enable_reg[1]_i_1 + (.I0(s_axi_wdata[1]), + .I1(p_6_in), + .I2(Bus_RNW_reg), + .I3(\ip_irpt_enable_reg_reg[1]_0 ), + .O(\ip_irpt_enable_reg[1]_i_1_n_0 )); + FDRE \ip_irpt_enable_reg_reg[0] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\ip_irpt_enable_reg[0]_i_1_n_0 ), + .Q(\ip_irpt_enable_reg_reg[0]_0 ), + .R(rst)); + FDRE \ip_irpt_enable_reg_reg[1] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\ip_irpt_enable_reg[1]_i_1_n_0 ), + .Q(\ip_irpt_enable_reg_reg[1]_0 ), + .R(rst)); + FDRE ipif_glbl_irpt_enable_reg_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ), + .Q(ipif_glbl_irpt_enable_reg), + .R(rst)); + FDRE irpt_rdack_d1_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(irpt_rdack), + .Q(irpt_rdack_d1), + .R(rst)); + FDRE irpt_wrack_d1_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(irpt_wrack), + .Q(irpt_wrack_d1), + .R(rst)); +endmodule + +(* ORIG_REF_NAME = "slave_attachment" *) +module Arty_Z7_20_axi_gpio_0_0_slave_attachment + (\ip2bus_data_i_D1_reg[31] , + \Dual.gpio2_OE_reg[0] , + iGPIO_xferAck_reg, + ipif_glbl_irpt_enable_reg_reg, + s_axi_rvalid, + s_axi_bvalid, + D, + irpt_wrack, + interrupt_wrce_strb, + intr2bus_rdack0, + irpt_rdack, + p_3_out, + intr_rd_ce_or_reduce, + \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg , + intr_wr_ce_or_reduce, + ip2bus_wrack_i, + \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] , + s_axi_arready, + s_axi_wready, + \Dual.gpio2_OE_reg[0]_0 , + \Dual.gpio_OE_reg[0] , + \Dual.gpio_Data_Out_reg[0] , + \Dual.gpio2_Data_Out_reg[0] , + ipif_glbl_irpt_enable_reg_reg_0, + \Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[31] , + \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[31] , + s_axi_rdata, + s_axi_aclk, + rst, + gpio_xferAck_Reg, + GPIO_xferAck_i, + \ip_irpt_enable_reg_reg[0] , + \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] , + GPIO2_DBus_i, + GPIO_DBus_i, + irpt_wrack_d1, + irpt_rdack_d1, + ipif_glbl_irpt_enable_reg, + p_1_in, + \ip_irpt_enable_reg_reg[1] , + ip2Bus_RdAck_intr_reg_hole_d1, + ip2Bus_WrAck_intr_reg_hole_d1, + intr2bus_wrack, + ip2Bus_WrAck_intr_reg_hole, + s_axi_arvalid, + s_axi_awvalid, + s_axi_wvalid, + s_axi_araddr, + s_axi_awaddr, + s_axi_rready, + s_axi_bready, + ip2bus_rdack_i_D1, + ip2bus_wrack_i_D1, + s_axi_wdata, + gpio2_io_t, + gpio_io_t, + gpio_io_o, + gpio2_io_o, + gpio2_Data_In, + gpio_Data_In, + s_axi_aresetn, + Q); + output \ip2bus_data_i_D1_reg[31] ; + output \Dual.gpio2_OE_reg[0] ; + output iGPIO_xferAck_reg; + output ipif_glbl_irpt_enable_reg_reg; + output s_axi_rvalid; + output s_axi_bvalid; + output [2:0]D; + output irpt_wrack; + output interrupt_wrce_strb; + output intr2bus_rdack0; + output irpt_rdack; + output p_3_out; + output intr_rd_ce_or_reduce; + output \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ; + output intr_wr_ce_or_reduce; + output ip2bus_wrack_i; + output \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ; + output s_axi_arready; + output s_axi_wready; + output \Dual.gpio2_OE_reg[0]_0 ; + output \Dual.gpio_OE_reg[0] ; + output \Dual.gpio_Data_Out_reg[0] ; + output \Dual.gpio2_Data_Out_reg[0] ; + output ipif_glbl_irpt_enable_reg_reg_0; + output \Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[31] ; + output \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[31] ; + output [2:0]s_axi_rdata; + input s_axi_aclk; + input rst; + input gpio_xferAck_Reg; + input GPIO_xferAck_i; + input \ip_irpt_enable_reg_reg[0] ; + input \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ; + input [0:0]GPIO2_DBus_i; + input [0:0]GPIO_DBus_i; + input irpt_wrack_d1; + input irpt_rdack_d1; + input ipif_glbl_irpt_enable_reg; + input p_1_in; + input \ip_irpt_enable_reg_reg[1] ; + input ip2Bus_RdAck_intr_reg_hole_d1; + input ip2Bus_WrAck_intr_reg_hole_d1; + input intr2bus_wrack; + input ip2Bus_WrAck_intr_reg_hole; + input s_axi_arvalid; + input s_axi_awvalid; + input s_axi_wvalid; + input [6:0]s_axi_araddr; + input [6:0]s_axi_awaddr; + input s_axi_rready; + input s_axi_bready; + input ip2bus_rdack_i_D1; + input ip2bus_wrack_i_D1; + input [1:0]s_axi_wdata; + input [0:0]gpio2_io_t; + input [0:0]gpio_io_t; + input [0:0]gpio_io_o; + input [0:0]gpio2_io_o; + input gpio2_Data_In; + input gpio_Data_In; + input s_axi_aresetn; + input [2:0]Q; + + wire [2:0]D; + wire \Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[31] ; + wire \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[31] ; + wire \Dual.gpio2_Data_Out_reg[0] ; + wire \Dual.gpio2_OE_reg[0] ; + wire \Dual.gpio2_OE_reg[0]_0 ; + wire \Dual.gpio_Data_Out_reg[0] ; + wire \Dual.gpio_OE_reg[0] ; + wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ; + wire \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ; + wire [0:0]GPIO2_DBus_i; + wire [0:0]GPIO_DBus_i; + wire GPIO_xferAck_i; + wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ; + wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ; + wire [2:0]Q; + wire [0:6]bus2ip_addr; + wire \bus2ip_addr_i[8]_i_1_n_0 ; + wire bus2ip_rnw_i06_out; + wire clear; + wire gpio2_Data_In; + wire [0:0]gpio2_io_o; + wire [0:0]gpio2_io_t; + wire gpio_Data_In; + wire [0:0]gpio_io_o; + wire [0:0]gpio_io_t; + wire gpio_xferAck_Reg; + wire iGPIO_xferAck_reg; + wire interrupt_wrce_strb; + wire intr2bus_rdack0; + wire intr2bus_wrack; + wire intr_rd_ce_or_reduce; + wire intr_wr_ce_or_reduce; + wire ip2Bus_RdAck_intr_reg_hole_d1; + wire ip2Bus_WrAck_intr_reg_hole; + wire ip2Bus_WrAck_intr_reg_hole_d1; + wire \ip2bus_data_i_D1_reg[31] ; + wire ip2bus_rdack_i_D1; + wire ip2bus_wrack_i; + wire ip2bus_wrack_i_D1; + wire \ip_irpt_enable_reg_reg[0] ; + wire \ip_irpt_enable_reg_reg[1] ; + wire ipif_glbl_irpt_enable_reg; + wire ipif_glbl_irpt_enable_reg_reg; + wire ipif_glbl_irpt_enable_reg_reg_0; + wire irpt_rdack; + wire irpt_rdack_d1; + wire irpt_wrack; + wire irpt_wrack_d1; + wire is_read; + wire is_read_i_1_n_0; + wire is_write; + wire is_write_i_1_n_0; + wire is_write_reg_n_0; + wire [1:0]p_0_out__0; + wire p_1_in; + wire [8:2]p_1_in__0; + wire p_3_out; + wire [3:0]plusOp; + wire rst; + wire s_axi_aclk; + wire [6:0]s_axi_araddr; + wire s_axi_aresetn; + wire s_axi_arready; + wire s_axi_arvalid; + wire [6:0]s_axi_awaddr; + wire s_axi_awvalid; + wire s_axi_bready; + wire s_axi_bvalid; + wire s_axi_bvalid_i_i_1_n_0; + wire [2:0]s_axi_rdata; + wire \s_axi_rdata_i[0]_i_1_n_0 ; + wire \s_axi_rdata_i[1]_i_1_n_0 ; + wire \s_axi_rdata_i[31]_i_1_n_0 ; + wire s_axi_rready; + wire s_axi_rvalid; + wire s_axi_rvalid_i_i_1_n_0; + wire [1:0]s_axi_wdata; + wire s_axi_wready; + wire s_axi_wvalid; + wire start2; + wire start2_i_1_n_0; + wire [1:0]state; + wire state1__2; + wire \state[1]_i_3_n_0 ; + + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT1 #( + .INIT(2'h1)) + \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1 + (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]), + .O(plusOp[0])); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h6)) + \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1 + (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]), + .I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]), + .O(plusOp[1])); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1 + (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]), + .I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]), + .I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]), + .O(plusOp[2])); + LUT2 #( + .INIT(4'h9)) + \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1 + (.I0(state[0]), + .I1(state[1]), + .O(clear)); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT4 #( + .INIT(16'h7F80)) + \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2 + (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]), + .I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]), + .I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]), + .I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]), + .O(plusOp[3])); + FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0] + (.C(s_axi_aclk), + .CE(1'b1), + .D(plusOp[0]), + .Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]), + .R(clear)); + FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1] + (.C(s_axi_aclk), + .CE(1'b1), + .D(plusOp[1]), + .Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]), + .R(clear)); + FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2] + (.C(s_axi_aclk), + .CE(1'b1), + .D(plusOp[2]), + .Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]), + .R(clear)); + FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] + (.C(s_axi_aclk), + .CE(1'b1), + .D(plusOp[3]), + .Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]), + .R(clear)); + Arty_Z7_20_axi_gpio_0_0_address_decoder I_DECODER + (.D(D), + .\Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[31] (\Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[31] ), + .\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[31] (\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[31] ), + .\Dual.gpio2_Data_Out_reg[0] (\Dual.gpio2_Data_Out_reg[0] ), + .\Dual.gpio2_OE_reg[0] (\Dual.gpio2_OE_reg[0]_0 ), + .\Dual.gpio_Data_Out_reg[0] (\Dual.gpio_Data_Out_reg[0] ), + .\Dual.gpio_OE_reg[0] (\Dual.gpio_OE_reg[0] ), + .\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] (\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ), + .\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] (\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ), + .GPIO2_DBus_i(GPIO2_DBus_i), + .GPIO_DBus_i(GPIO_DBus_i), + .GPIO_xferAck_i(GPIO_xferAck_i), + .\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] (\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ), + .\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg (\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ), + .Q(start2), + .\bus2ip_addr_i_reg[8] ({bus2ip_addr[0],bus2ip_addr[1],bus2ip_addr[2],bus2ip_addr[3],bus2ip_addr[4],bus2ip_addr[5],bus2ip_addr[6]}), + .bus2ip_rnw_i_reg(\Dual.gpio2_OE_reg[0] ), + .gpio2_Data_In(gpio2_Data_In), + .gpio2_io_o(gpio2_io_o), + .gpio2_io_t(gpio2_io_t), + .gpio_Data_In(gpio_Data_In), + .gpio_io_o(gpio_io_o), + .gpio_io_t(gpio_io_t), + .gpio_xferAck_Reg(gpio_xferAck_Reg), + .iGPIO_xferAck_reg(iGPIO_xferAck_reg), + .interrupt_wrce_strb(interrupt_wrce_strb), + .intr2bus_rdack0(intr2bus_rdack0), + .intr_rd_ce_or_reduce(intr_rd_ce_or_reduce), + .intr_wr_ce_or_reduce(intr_wr_ce_or_reduce), + .ip2Bus_RdAck_intr_reg_hole_d1(ip2Bus_RdAck_intr_reg_hole_d1), + .ip2Bus_WrAck_intr_reg_hole_d1(ip2Bus_WrAck_intr_reg_hole_d1), + .\ip2bus_data_i_D1_reg[31] (\ip2bus_data_i_D1_reg[31] ), + .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1), + .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1), + .\ip_irpt_enable_reg_reg[0] (\ip_irpt_enable_reg_reg[0] ), + .\ip_irpt_enable_reg_reg[1] (\ip_irpt_enable_reg_reg[1] ), + .ipif_glbl_irpt_enable_reg(ipif_glbl_irpt_enable_reg), + .ipif_glbl_irpt_enable_reg_reg(ipif_glbl_irpt_enable_reg_reg), + .ipif_glbl_irpt_enable_reg_reg_0(ipif_glbl_irpt_enable_reg_reg_0), + .irpt_rdack(irpt_rdack), + .irpt_rdack_d1(irpt_rdack_d1), + .irpt_wrack(irpt_wrack), + .irpt_wrack_d1(irpt_wrack_d1), + .is_read(is_read), + .is_write_reg(is_write_reg_n_0), + .p_1_in(p_1_in), + .p_3_out(p_3_out), + .s_axi_aclk(s_axi_aclk), + .s_axi_aresetn(s_axi_aresetn), + .s_axi_arready(s_axi_arready), + .s_axi_wdata(s_axi_wdata), + .s_axi_wready(s_axi_wready)); + LUT5 #( + .INIT(32'hCCCACCCC)) + \bus2ip_addr_i[2]_i_1 + (.I0(s_axi_araddr[0]), + .I1(s_axi_awaddr[0]), + .I2(state[0]), + .I3(state[1]), + .I4(s_axi_arvalid), + .O(p_1_in__0[2])); + LUT5 #( + .INIT(32'hCCCACCCC)) + \bus2ip_addr_i[3]_i_1 + (.I0(s_axi_araddr[1]), + .I1(s_axi_awaddr[1]), + .I2(state[0]), + .I3(state[1]), + .I4(s_axi_arvalid), + .O(p_1_in__0[3])); + LUT5 #( + .INIT(32'hCCCACCCC)) + \bus2ip_addr_i[4]_i_1 + (.I0(s_axi_araddr[2]), + .I1(s_axi_awaddr[2]), + .I2(state[0]), + .I3(state[1]), + .I4(s_axi_arvalid), + .O(p_1_in__0[4])); + LUT5 #( + .INIT(32'hCCCACCCC)) + \bus2ip_addr_i[5]_i_1 + (.I0(s_axi_araddr[3]), + .I1(s_axi_awaddr[3]), + .I2(state[0]), + .I3(state[1]), + .I4(s_axi_arvalid), + .O(p_1_in__0[5])); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT5 #( + .INIT(32'hCCCACCCC)) + \bus2ip_addr_i[6]_i_1 + (.I0(s_axi_araddr[4]), + .I1(s_axi_awaddr[4]), + .I2(state[0]), + .I3(state[1]), + .I4(s_axi_arvalid), + .O(p_1_in__0[6])); + LUT5 #( + .INIT(32'hCCCACCCC)) + \bus2ip_addr_i[7]_i_1 + (.I0(s_axi_araddr[5]), + .I1(s_axi_awaddr[5]), + .I2(state[0]), + .I3(state[1]), + .I4(s_axi_arvalid), + .O(p_1_in__0[7])); + LUT5 #( + .INIT(32'h000000EA)) + \bus2ip_addr_i[8]_i_1 + (.I0(s_axi_arvalid), + .I1(s_axi_awvalid), + .I2(s_axi_wvalid), + .I3(state[1]), + .I4(state[0]), + .O(\bus2ip_addr_i[8]_i_1_n_0 )); + LUT5 #( + .INIT(32'hCCCACCCC)) + \bus2ip_addr_i[8]_i_2 + (.I0(s_axi_araddr[6]), + .I1(s_axi_awaddr[6]), + .I2(state[0]), + .I3(state[1]), + .I4(s_axi_arvalid), + .O(p_1_in__0[8])); + FDRE \bus2ip_addr_i_reg[2] + (.C(s_axi_aclk), + .CE(\bus2ip_addr_i[8]_i_1_n_0 ), + .D(p_1_in__0[2]), + .Q(bus2ip_addr[6]), + .R(rst)); + FDRE \bus2ip_addr_i_reg[3] + (.C(s_axi_aclk), + .CE(\bus2ip_addr_i[8]_i_1_n_0 ), + .D(p_1_in__0[3]), + .Q(bus2ip_addr[5]), + .R(rst)); + FDRE \bus2ip_addr_i_reg[4] + (.C(s_axi_aclk), + .CE(\bus2ip_addr_i[8]_i_1_n_0 ), + .D(p_1_in__0[4]), + .Q(bus2ip_addr[4]), + .R(rst)); + FDRE \bus2ip_addr_i_reg[5] + (.C(s_axi_aclk), + .CE(\bus2ip_addr_i[8]_i_1_n_0 ), + .D(p_1_in__0[5]), + .Q(bus2ip_addr[3]), + .R(rst)); + FDRE \bus2ip_addr_i_reg[6] + (.C(s_axi_aclk), + .CE(\bus2ip_addr_i[8]_i_1_n_0 ), + .D(p_1_in__0[6]), + .Q(bus2ip_addr[2]), + .R(rst)); + FDRE \bus2ip_addr_i_reg[7] + (.C(s_axi_aclk), + .CE(\bus2ip_addr_i[8]_i_1_n_0 ), + .D(p_1_in__0[7]), + .Q(bus2ip_addr[1]), + .R(rst)); + FDRE \bus2ip_addr_i_reg[8] + (.C(s_axi_aclk), + .CE(\bus2ip_addr_i[8]_i_1_n_0 ), + .D(p_1_in__0[8]), + .Q(bus2ip_addr[0]), + .R(rst)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT3 #( + .INIT(8'h10)) + bus2ip_rnw_i_i_1 + (.I0(state[0]), + .I1(state[1]), + .I2(s_axi_arvalid), + .O(bus2ip_rnw_i06_out)); + FDRE bus2ip_rnw_i_reg + (.C(s_axi_aclk), + .CE(\bus2ip_addr_i[8]_i_1_n_0 ), + .D(bus2ip_rnw_i06_out), + .Q(\Dual.gpio2_OE_reg[0] ), + .R(rst)); + LUT4 #( + .INIT(16'hFFF4)) + ip2bus_wrack_i_D1_i_1 + (.I0(\Dual.gpio2_OE_reg[0] ), + .I1(GPIO_xferAck_i), + .I2(intr2bus_wrack), + .I3(ip2Bus_WrAck_intr_reg_hole), + .O(ip2bus_wrack_i)); + LUT5 #( + .INIT(32'h3FFA000A)) + is_read_i_1 + (.I0(s_axi_arvalid), + .I1(state1__2), + .I2(state[0]), + .I3(state[1]), + .I4(is_read), + .O(is_read_i_1_n_0)); + FDRE is_read_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(is_read_i_1_n_0), + .Q(is_read), + .R(rst)); + LUT6 #( + .INIT(64'h0040FFFF00400000)) + is_write_i_1 + (.I0(s_axi_arvalid), + .I1(s_axi_awvalid), + .I2(s_axi_wvalid), + .I3(state[1]), + .I4(is_write), + .I5(is_write_reg_n_0), + .O(is_write_i_1_n_0)); + LUT6 #( + .INIT(64'hF88800000000FFFF)) + is_write_i_2 + (.I0(s_axi_rvalid), + .I1(s_axi_rready), + .I2(s_axi_bvalid), + .I3(s_axi_bready), + .I4(state[0]), + .I5(state[1]), + .O(is_write)); + FDRE is_write_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(is_write_i_1_n_0), + .Q(is_write_reg_n_0), + .R(rst)); + LUT5 #( + .INIT(32'h08FF0808)) + s_axi_bvalid_i_i_1 + (.I0(s_axi_wready), + .I1(state[1]), + .I2(state[0]), + .I3(s_axi_bready), + .I4(s_axi_bvalid), + .O(s_axi_bvalid_i_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + s_axi_bvalid_i_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_axi_bvalid_i_i_1_n_0), + .Q(s_axi_bvalid), + .R(rst)); + LUT4 #( + .INIT(16'hFB08)) + \s_axi_rdata_i[0]_i_1 + (.I0(Q[0]), + .I1(state[0]), + .I2(state[1]), + .I3(s_axi_rdata[0]), + .O(\s_axi_rdata_i[0]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFB08)) + \s_axi_rdata_i[1]_i_1 + (.I0(Q[1]), + .I1(state[0]), + .I2(state[1]), + .I3(s_axi_rdata[1]), + .O(\s_axi_rdata_i[1]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFB08)) + \s_axi_rdata_i[31]_i_1 + (.I0(Q[2]), + .I1(state[0]), + .I2(state[1]), + .I3(s_axi_rdata[2]), + .O(\s_axi_rdata_i[31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[0] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\s_axi_rdata_i[0]_i_1_n_0 ), + .Q(s_axi_rdata[0]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[1] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\s_axi_rdata_i[1]_i_1_n_0 ), + .Q(s_axi_rdata[1]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[31] + (.C(s_axi_aclk), + .CE(1'b1), + .D(\s_axi_rdata_i[31]_i_1_n_0 ), + .Q(s_axi_rdata[2]), + .R(rst)); + LUT5 #( + .INIT(32'h08FF0808)) + s_axi_rvalid_i_i_1 + (.I0(s_axi_arready), + .I1(state[0]), + .I2(state[1]), + .I3(s_axi_rready), + .I4(s_axi_rvalid), + .O(s_axi_rvalid_i_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + s_axi_rvalid_i_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(s_axi_rvalid_i_i_1_n_0), + .Q(s_axi_rvalid), + .R(rst)); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT5 #( + .INIT(32'h000000F8)) + start2_i_1 + (.I0(s_axi_awvalid), + .I1(s_axi_wvalid), + .I2(s_axi_arvalid), + .I3(state[1]), + .I4(state[0]), + .O(start2_i_1_n_0)); + FDRE start2_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(start2_i_1_n_0), + .Q(start2), + .R(rst)); + LUT5 #( + .INIT(32'h77FC44FC)) + \state[0]_i_1 + (.I0(state1__2), + .I1(state[0]), + .I2(s_axi_arvalid), + .I3(state[1]), + .I4(s_axi_wready), + .O(p_0_out__0[0])); + LUT5 #( + .INIT(32'h5FFC50FC)) + \state[1]_i_1 + (.I0(state1__2), + .I1(\state[1]_i_3_n_0 ), + .I2(state[1]), + .I3(state[0]), + .I4(s_axi_arready), + .O(p_0_out__0[1])); + LUT4 #( + .INIT(16'hF888)) + \state[1]_i_2 + (.I0(s_axi_bready), + .I1(s_axi_bvalid), + .I2(s_axi_rready), + .I3(s_axi_rvalid), + .O(state1__2)); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h08)) + \state[1]_i_3 + (.I0(s_axi_wvalid), + .I1(s_axi_awvalid), + .I2(s_axi_arvalid), + .O(\state[1]_i_3_n_0 )); + FDRE \state_reg[0] + (.C(s_axi_aclk), + .CE(1'b1), + .D(p_0_out__0[0]), + .Q(state[0]), + .R(rst)); + FDRE \state_reg[1] + (.C(s_axi_aclk), + .CE(1'b1), + .D(p_0_out__0[1]), + .Q(state[1]), + .R(rst)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0_sim_netlist.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0_sim_netlist.vhdl new file mode 100644 index 0000000..6999c39 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0_sim_netlist.vhdl @@ -0,0 +1,2817 @@ +-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +-- Date : Sat Mar 04 18:57:36 2017 +-- Host : WK73 running 64-bit Service Pack 1 (build 7601) +-- Command : write_vhdl -force -mode funcsim +-- c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0_sim_netlist.vhdl +-- Design : Arty_Z7_20_axi_gpio_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg400-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_gpio_0_0_address_decoder is + port ( + \ip2bus_data_i_D1_reg[31]\ : out STD_LOGIC; + iGPIO_xferAck_reg : out STD_LOGIC; + ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + irpt_wrack : out STD_LOGIC; + interrupt_wrce_strb : out STD_LOGIC; + intr2bus_rdack0 : out STD_LOGIC; + irpt_rdack : out STD_LOGIC; + p_3_out : out STD_LOGIC; + intr_rd_ce_or_reduce : out STD_LOGIC; + \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC; + intr_wr_ce_or_reduce : out STD_LOGIC; + \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\ : out STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_wready : out STD_LOGIC; + \Dual.gpio2_OE_reg[0]\ : out STD_LOGIC; + \Dual.gpio_OE_reg[0]\ : out STD_LOGIC; + \Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC; + \Dual.gpio2_Data_Out_reg[0]\ : out STD_LOGIC; + ipif_glbl_irpt_enable_reg_reg_0 : out STD_LOGIC; + \Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[31]\ : out STD_LOGIC; + \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[31]\ : out STD_LOGIC; + Q : in STD_LOGIC; + s_axi_aclk : in STD_LOGIC; + \bus2ip_addr_i_reg[8]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); + bus2ip_rnw_i_reg : in STD_LOGIC; + gpio_xferAck_Reg : in STD_LOGIC; + GPIO_xferAck_i : in STD_LOGIC; + \ip_irpt_enable_reg_reg[0]\ : in STD_LOGIC; + \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ : in STD_LOGIC; + GPIO2_DBus_i : in STD_LOGIC_VECTOR ( 0 to 0 ); + GPIO_DBus_i : in STD_LOGIC_VECTOR ( 0 to 0 ); + irpt_wrack_d1 : in STD_LOGIC; + irpt_rdack_d1 : in STD_LOGIC; + ipif_glbl_irpt_enable_reg : in STD_LOGIC; + p_1_in : in STD_LOGIC; + \ip_irpt_enable_reg_reg[1]\ : in STD_LOGIC; + ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC; + ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC; + ip2bus_rdack_i_D1 : in STD_LOGIC; + is_read : in STD_LOGIC; + \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + ip2bus_wrack_i_D1 : in STD_LOGIC; + is_write_reg : in STD_LOGIC; + s_axi_wdata : in STD_LOGIC_VECTOR ( 1 downto 0 ); + gpio2_io_t : in STD_LOGIC_VECTOR ( 0 to 0 ); + gpio_io_t : in STD_LOGIC_VECTOR ( 0 to 0 ); + gpio_io_o : in STD_LOGIC_VECTOR ( 0 to 0 ); + gpio2_io_o : in STD_LOGIC_VECTOR ( 0 to 0 ); + gpio2_Data_In : in STD_LOGIC; + gpio_Data_In : in STD_LOGIC; + s_axi_aresetn : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_gpio_0_0_address_decoder : entity is "address_decoder"; +end Arty_Z7_20_axi_gpio_0_0_address_decoder; + +architecture STRUCTURE of Arty_Z7_20_axi_gpio_0_0_address_decoder is + signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC; + signal \Dual.READ_REG2_GEN[0].GPIO2_DBus_i[31]_i_2_n_0\ : STD_LOGIC; + signal \Dual.READ_REG_GEN[0].GPIO_DBus_i[31]_i_2_n_0\ : STD_LOGIC; + signal \Dual.gpio_Data_Out[0]_i_2_n_0\ : STD_LOGIC; + signal \GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1_n_0\ : STD_LOGIC; + signal \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\ : STD_LOGIC; + signal \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\ : STD_LOGIC; + signal \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\ : STD_LOGIC; + signal \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ : STD_LOGIC; + signal \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\ : STD_LOGIC; + signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\ : STD_LOGIC; + signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\ : STD_LOGIC; + signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\ : STD_LOGIC; + signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_2_n_0\ : STD_LOGIC; + signal \^igpio_xferack_reg\ : STD_LOGIC; + signal \ip2bus_data_i_D1[31]_i_2_n_0\ : STD_LOGIC; + signal \^ip2bus_data_i_d1_reg[31]\ : STD_LOGIC; + signal \^ipif_glbl_irpt_enable_reg_reg\ : STD_LOGIC; + signal p_10_in : STD_LOGIC; + signal p_10_out : STD_LOGIC; + signal p_11_in : STD_LOGIC; + signal p_11_out : STD_LOGIC; + signal p_12_in : STD_LOGIC; + signal p_12_out : STD_LOGIC; + signal p_13_in : STD_LOGIC; + signal p_13_out : STD_LOGIC; + signal p_14_in : STD_LOGIC; + signal p_14_out : STD_LOGIC; + signal p_15_in : STD_LOGIC; + signal p_15_out : STD_LOGIC; + signal p_16_in : STD_LOGIC; + signal p_2_in : STD_LOGIC; + signal p_3_in : STD_LOGIC; + signal p_4_in : STD_LOGIC; + signal p_4_out : STD_LOGIC; + signal p_5_in : STD_LOGIC; + signal p_5_out : STD_LOGIC; + signal p_6_out : STD_LOGIC; + signal p_7_in : STD_LOGIC; + signal p_7_out : STD_LOGIC; + signal p_8_in : STD_LOGIC; + signal p_8_out : STD_LOGIC; + signal p_9_in : STD_LOGIC; + signal pselect_hit_i_1 : STD_LOGIC; + signal \^s_axi_arready\ : STD_LOGIC; + signal \^s_axi_wready\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of intr2bus_rdack_i_1 : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of intr2bus_wrack_i_1 : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \ip2bus_data_i_D1[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of irpt_rdack_d1_i_1 : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of irpt_wrack_d1_i_1 : label is "soft_lutpair0"; +begin + iGPIO_xferAck_reg <= \^igpio_xferack_reg\; + \ip2bus_data_i_D1_reg[31]\ <= \^ip2bus_data_i_d1_reg[31]\; + ipif_glbl_irpt_enable_reg_reg <= \^ipif_glbl_irpt_enable_reg_reg\; + s_axi_arready <= \^s_axi_arready\; + s_axi_wready <= \^s_axi_wready\; +Bus_RNW_reg_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => bus2ip_rnw_i_reg, + I1 => Q, + I2 => \^ipif_glbl_irpt_enable_reg_reg\, + O => Bus_RNW_reg_i_1_n_0 + ); +Bus_RNW_reg_reg: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => Bus_RNW_reg_i_1_n_0, + Q => \^ipif_glbl_irpt_enable_reg_reg\, + R => '0' + ); +\Dual.READ_REG2_GEN[0].GPIO2_DBus_i[31]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FFEF0020" + ) + port map ( + I0 => gpio2_Data_In, + I1 => \bus2ip_addr_i_reg[8]\(0), + I2 => \bus2ip_addr_i_reg[8]\(1), + I3 => \Dual.gpio_Data_Out[0]_i_2_n_0\, + I4 => gpio2_io_t(0), + I5 => \Dual.READ_REG2_GEN[0].GPIO2_DBus_i[31]_i_2_n_0\, + O => \Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[31]\ + ); +\Dual.READ_REG2_GEN[0].GPIO2_DBus_i[31]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFDFFFFFFFFF" + ) + port map ( + I0 => bus2ip_rnw_i_reg, + I1 => \bus2ip_addr_i_reg[8]\(6), + I2 => \bus2ip_addr_i_reg[8]\(1), + I3 => GPIO_xferAck_i, + I4 => gpio_xferAck_Reg, + I5 => \^igpio_xferack_reg\, + O => \Dual.READ_REG2_GEN[0].GPIO2_DBus_i[31]_i_2_n_0\ + ); +\Dual.READ_REG_GEN[0].GPIO_DBus_i[31]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FFFE0002" + ) + port map ( + I0 => gpio_Data_In, + I1 => \bus2ip_addr_i_reg[8]\(1), + I2 => \bus2ip_addr_i_reg[8]\(0), + I3 => \Dual.gpio_Data_Out[0]_i_2_n_0\, + I4 => gpio_io_t(0), + I5 => \Dual.READ_REG_GEN[0].GPIO_DBus_i[31]_i_2_n_0\, + O => \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[31]\ + ); +\Dual.READ_REG_GEN[0].GPIO_DBus_i[31]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFBFF" + ) + port map ( + I0 => \bus2ip_addr_i_reg[8]\(6), + I1 => bus2ip_rnw_i_reg, + I2 => \bus2ip_addr_i_reg[8]\(1), + I3 => \^igpio_xferack_reg\, + I4 => gpio_xferAck_Reg, + I5 => GPIO_xferAck_i, + O => \Dual.READ_REG_GEN[0].GPIO_DBus_i[31]_i_2_n_0\ + ); +\Dual.gpio2_Data_Out[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFEFF00000200" + ) + port map ( + I0 => s_axi_wdata(0), + I1 => bus2ip_rnw_i_reg, + I2 => \bus2ip_addr_i_reg[8]\(0), + I3 => \bus2ip_addr_i_reg[8]\(1), + I4 => \Dual.gpio_Data_Out[0]_i_2_n_0\, + I5 => gpio2_io_o(0), + O => \Dual.gpio2_Data_Out_reg[0]\ + ); +\Dual.gpio2_OE[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FEFFFFFF02000000" + ) + port map ( + I0 => s_axi_wdata(0), + I1 => \Dual.gpio_Data_Out[0]_i_2_n_0\, + I2 => bus2ip_rnw_i_reg, + I3 => \bus2ip_addr_i_reg[8]\(0), + I4 => \bus2ip_addr_i_reg[8]\(1), + I5 => gpio2_io_t(0), + O => \Dual.gpio2_OE_reg[0]\ + ); +\Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFE00000002" + ) + port map ( + I0 => s_axi_wdata(0), + I1 => bus2ip_rnw_i_reg, + I2 => \bus2ip_addr_i_reg[8]\(1), + I3 => \bus2ip_addr_i_reg[8]\(0), + I4 => \Dual.gpio_Data_Out[0]_i_2_n_0\, + I5 => gpio_io_o(0), + O => \Dual.gpio_Data_Out_reg[0]\ + ); +\Dual.gpio_Data_Out[0]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \bus2ip_addr_i_reg[8]\(6), + I1 => \^igpio_xferack_reg\, + O => \Dual.gpio_Data_Out[0]_i_2_n_0\ + ); +\Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFEFF00000200" + ) + port map ( + I0 => s_axi_wdata(0), + I1 => \Dual.gpio_Data_Out[0]_i_2_n_0\, + I2 => bus2ip_rnw_i_reg, + I3 => \bus2ip_addr_i_reg[8]\(0), + I4 => \bus2ip_addr_i_reg[8]\(1), + I5 => gpio_io_t(0), + O => \Dual.gpio_OE_reg[0]\ + ); +\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0040000000000000" + ) + port map ( + I0 => \bus2ip_addr_i_reg[8]\(3), + I1 => \bus2ip_addr_i_reg[8]\(2), + I2 => \bus2ip_addr_i_reg[8]\(1), + I3 => \bus2ip_addr_i_reg[8]\(0), + I4 => \bus2ip_addr_i_reg[8]\(6), + I5 => Q, + O => \GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1_n_0\ + ); +\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => Q, + D => \GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1_n_0\, + Q => p_10_in, + R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ + ); +\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0800000000000000" + ) + port map ( + I0 => \bus2ip_addr_i_reg[8]\(1), + I1 => \bus2ip_addr_i_reg[8]\(0), + I2 => \bus2ip_addr_i_reg[8]\(3), + I3 => Q, + I4 => \bus2ip_addr_i_reg[8]\(6), + I5 => \bus2ip_addr_i_reg[8]\(2), + O => p_8_out + ); +\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => Q, + D => p_8_out, + Q => p_9_in, + R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ + ); +\GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000800" + ) + port map ( + I0 => Q, + I1 => \bus2ip_addr_i_reg[8]\(6), + I2 => \bus2ip_addr_i_reg[8]\(2), + I3 => \bus2ip_addr_i_reg[8]\(3), + I4 => \bus2ip_addr_i_reg[8]\(1), + I5 => \bus2ip_addr_i_reg[8]\(0), + O => p_7_out + ); +\GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => Q, + D => p_7_out, + Q => p_8_in, + R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ + ); +\GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000080000000000" + ) + port map ( + I0 => Q, + I1 => \bus2ip_addr_i_reg[8]\(6), + I2 => \bus2ip_addr_i_reg[8]\(2), + I3 => \bus2ip_addr_i_reg[8]\(3), + I4 => \bus2ip_addr_i_reg[8]\(1), + I5 => \bus2ip_addr_i_reg[8]\(0), + O => p_6_out + ); +\GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => Q, + D => p_6_out, + Q => p_7_in, + R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ + ); +\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000400000000000" + ) + port map ( + I0 => \bus2ip_addr_i_reg[8]\(2), + I1 => \bus2ip_addr_i_reg[8]\(3), + I2 => Q, + I3 => \bus2ip_addr_i_reg[8]\(6), + I4 => \bus2ip_addr_i_reg[8]\(0), + I5 => \bus2ip_addr_i_reg[8]\(1), + O => p_5_out + ); +\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => Q, + D => p_5_out, + Q => \^ip2bus_data_i_d1_reg[31]\, + R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ + ); +\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0800000000000000" + ) + port map ( + I0 => Q, + I1 => \bus2ip_addr_i_reg[8]\(6), + I2 => \bus2ip_addr_i_reg[8]\(2), + I3 => \bus2ip_addr_i_reg[8]\(3), + I4 => \bus2ip_addr_i_reg[8]\(1), + I5 => \bus2ip_addr_i_reg[8]\(0), + O => p_4_out + ); +\GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => Q, + D => p_4_out, + Q => p_5_in, + R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ + ); +\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000008000" + ) + port map ( + I0 => Q, + I1 => \bus2ip_addr_i_reg[8]\(6), + I2 => \bus2ip_addr_i_reg[8]\(2), + I3 => \bus2ip_addr_i_reg[8]\(3), + I4 => \bus2ip_addr_i_reg[8]\(1), + I5 => \bus2ip_addr_i_reg[8]\(0), + O => \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\ + ); +\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => Q, + D => \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\, + Q => p_4_in, + R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ + ); +\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000800000000000" + ) + port map ( + I0 => Q, + I1 => \bus2ip_addr_i_reg[8]\(6), + I2 => \bus2ip_addr_i_reg[8]\(2), + I3 => \bus2ip_addr_i_reg[8]\(3), + I4 => \bus2ip_addr_i_reg[8]\(1), + I5 => \bus2ip_addr_i_reg[8]\(0), + O => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\ + ); +\GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => Q, + D => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\, + Q => p_3_in, + R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ + ); +\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0080000000000000" + ) + port map ( + I0 => \bus2ip_addr_i_reg[8]\(3), + I1 => \bus2ip_addr_i_reg[8]\(2), + I2 => \bus2ip_addr_i_reg[8]\(1), + I3 => \bus2ip_addr_i_reg[8]\(0), + I4 => \bus2ip_addr_i_reg[8]\(6), + I5 => Q, + O => \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\ + ); +\GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => Q, + D => \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\, + Q => p_2_in, + R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ + ); +\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"EF" + ) + port map ( + I0 => \^s_axi_wready\, + I1 => \^s_axi_arready\, + I2 => s_axi_aresetn, + O => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ + ); +\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => Q, + I1 => \bus2ip_addr_i_reg[8]\(6), + I2 => \bus2ip_addr_i_reg[8]\(2), + I3 => \bus2ip_addr_i_reg[8]\(3), + I4 => \bus2ip_addr_i_reg[8]\(1), + I5 => \bus2ip_addr_i_reg[8]\(0), + O => p_15_out + ); +\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => Q, + D => p_15_out, + Q => \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\, + R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ + ); +\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000008" + ) + port map ( + I0 => Q, + I1 => \bus2ip_addr_i_reg[8]\(6), + I2 => \bus2ip_addr_i_reg[8]\(2), + I3 => \bus2ip_addr_i_reg[8]\(1), + I4 => \bus2ip_addr_i_reg[8]\(0), + I5 => \bus2ip_addr_i_reg[8]\(3), + O => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\ + ); +\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => Q, + D => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\, + Q => p_16_in, + R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ + ); +\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000080000" + ) + port map ( + I0 => Q, + I1 => \bus2ip_addr_i_reg[8]\(6), + I2 => \bus2ip_addr_i_reg[8]\(2), + I3 => \bus2ip_addr_i_reg[8]\(1), + I4 => \bus2ip_addr_i_reg[8]\(0), + I5 => \bus2ip_addr_i_reg[8]\(3), + O => p_14_out + ); +\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => Q, + D => p_14_out, + Q => p_15_in, + R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ + ); +\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000100000000000" + ) + port map ( + I0 => \bus2ip_addr_i_reg[8]\(3), + I1 => \bus2ip_addr_i_reg[8]\(2), + I2 => Q, + I3 => \bus2ip_addr_i_reg[8]\(6), + I4 => \bus2ip_addr_i_reg[8]\(0), + I5 => \bus2ip_addr_i_reg[8]\(1), + O => p_13_out + ); +\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => Q, + D => p_13_out, + Q => p_14_in, + R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ + ); +\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000008000000" + ) + port map ( + I0 => Q, + I1 => \bus2ip_addr_i_reg[8]\(6), + I2 => \bus2ip_addr_i_reg[8]\(2), + I3 => \bus2ip_addr_i_reg[8]\(1), + I4 => \bus2ip_addr_i_reg[8]\(0), + I5 => \bus2ip_addr_i_reg[8]\(3), + O => p_12_out + ); +\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => Q, + D => p_12_out, + Q => p_13_in, + R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ + ); +\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0100000000000000" + ) + port map ( + I0 => \bus2ip_addr_i_reg[8]\(1), + I1 => \bus2ip_addr_i_reg[8]\(0), + I2 => \bus2ip_addr_i_reg[8]\(3), + I3 => Q, + I4 => \bus2ip_addr_i_reg[8]\(6), + I5 => \bus2ip_addr_i_reg[8]\(2), + O => p_11_out + ); +\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => Q, + D => p_11_out, + Q => p_12_in, + R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ + ); +\GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0400000000000000" + ) + port map ( + I0 => \bus2ip_addr_i_reg[8]\(1), + I1 => \bus2ip_addr_i_reg[8]\(0), + I2 => \bus2ip_addr_i_reg[8]\(3), + I3 => Q, + I4 => \bus2ip_addr_i_reg[8]\(6), + I5 => \bus2ip_addr_i_reg[8]\(2), + O => p_10_out + ); +\GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => Q, + D => p_10_out, + Q => p_11_in, + R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ + ); +\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"EF" + ) + port map ( + I0 => irpt_wrack_d1, + I1 => \^ipif_glbl_irpt_enable_reg_reg\, + I2 => p_8_in, + O => \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\ + ); +\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAA8AAAAAAAA" + ) + port map ( + I0 => \^ipif_glbl_irpt_enable_reg_reg\, + I1 => \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\, + I2 => p_4_in, + I3 => p_3_in, + I4 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\, + I5 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\, + O => intr_rd_ce_or_reduce + ); +\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000FD00" + ) + port map ( + I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\, + I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\, + I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_2_n_0\, + I3 => \^ipif_glbl_irpt_enable_reg_reg\, + I4 => ip2Bus_RdAck_intr_reg_hole_d1, + O => p_3_out + ); +\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5555555455555555" + ) + port map ( + I0 => \^ipif_glbl_irpt_enable_reg_reg\, + I1 => \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\, + I2 => p_4_in, + I3 => p_3_in, + I4 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\, + I5 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\, + O => intr_wr_ce_or_reduce + ); +\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => p_16_in, + I1 => p_14_in, + I2 => p_10_in, + I3 => p_5_in, + O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\ + ); +\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000001" + ) + port map ( + I0 => p_12_in, + I1 => p_11_in, + I2 => p_2_in, + I3 => p_15_in, + I4 => p_7_in, + I5 => p_13_in, + O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\ + ); +\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000FD" + ) + port map ( + I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\, + I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\, + I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_2_n_0\, + I3 => \^ipif_glbl_irpt_enable_reg_reg\, + I4 => ip2Bus_WrAck_intr_reg_hole_d1, + O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ + ); +\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => p_3_in, + I1 => p_4_in, + I2 => \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\, + O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_2_n_0\ + ); +\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000100" + ) + port map ( + I0 => \bus2ip_addr_i_reg[8]\(3), + I1 => \bus2ip_addr_i_reg[8]\(2), + I2 => \bus2ip_addr_i_reg[8]\(6), + I3 => Q, + I4 => \bus2ip_addr_i_reg[8]\(4), + I5 => \bus2ip_addr_i_reg[8]\(5), + O => pselect_hit_i_1 + ); +\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => Q, + D => pselect_hit_i_1, + Q => \^igpio_xferack_reg\, + R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ + ); +intr2bus_rdack_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000F0E0" + ) + port map ( + I0 => \^ip2bus_data_i_d1_reg[31]\, + I1 => p_8_in, + I2 => \^ipif_glbl_irpt_enable_reg_reg\, + I3 => p_9_in, + I4 => irpt_rdack_d1, + O => intr2bus_rdack0 + ); +intr2bus_wrack_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000F0E" + ) + port map ( + I0 => p_9_in, + I1 => p_8_in, + I2 => \^ipif_glbl_irpt_enable_reg_reg\, + I3 => \^ip2bus_data_i_d1_reg[31]\, + I4 => irpt_wrack_d1, + O => interrupt_wrce_strb + ); +\ip2bus_data_i_D1[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"10000000" + ) + port map ( + I0 => p_8_in, + I1 => \^ip2bus_data_i_d1_reg[31]\, + I2 => \^ipif_glbl_irpt_enable_reg_reg\, + I3 => p_9_in, + I4 => ipif_glbl_irpt_enable_reg, + O => D(2) + ); +\ip2bus_data_i_D1[30]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"8C808080" + ) + port map ( + I0 => p_1_in, + I1 => \^ipif_glbl_irpt_enable_reg_reg\, + I2 => p_8_in, + I3 => \ip_irpt_enable_reg_reg[1]\, + I4 => \^ip2bus_data_i_d1_reg[31]\, + O => D(1) + ); +\ip2bus_data_i_D1[31]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFF8000800" + ) + port map ( + I0 => \^ip2bus_data_i_d1_reg[31]\, + I1 => \ip_irpt_enable_reg_reg[0]\, + I2 => p_8_in, + I3 => \^ipif_glbl_irpt_enable_reg_reg\, + I4 => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\, + I5 => \ip2bus_data_i_D1[31]_i_2_n_0\, + O => D(0) + ); +\ip2bus_data_i_D1[31]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AABAAAAAAA8AAAAA" + ) + port map ( + I0 => GPIO2_DBus_i(0), + I1 => \bus2ip_addr_i_reg[8]\(1), + I2 => bus2ip_rnw_i_reg, + I3 => \bus2ip_addr_i_reg[8]\(6), + I4 => \^igpio_xferack_reg\, + I5 => GPIO_DBus_i(0), + O => \ip2bus_data_i_D1[31]_i_2_n_0\ + ); +ipif_glbl_irpt_enable_reg_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_wdata(1), + I1 => p_9_in, + I2 => \^ipif_glbl_irpt_enable_reg_reg\, + I3 => ipif_glbl_irpt_enable_reg, + O => ipif_glbl_irpt_enable_reg_reg_0 + ); +irpt_rdack_d1_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"CCC8" + ) + port map ( + I0 => p_9_in, + I1 => \^ipif_glbl_irpt_enable_reg_reg\, + I2 => p_8_in, + I3 => \^ip2bus_data_i_d1_reg[31]\, + O => irpt_rdack + ); +irpt_wrack_d1_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"3332" + ) + port map ( + I0 => \^ip2bus_data_i_d1_reg[31]\, + I1 => \^ipif_glbl_irpt_enable_reg_reg\, + I2 => p_8_in, + I3 => p_9_in, + O => irpt_wrack + ); +s_axi_arready_INST_0: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAAAAEAAAA" + ) + port map ( + I0 => ip2bus_rdack_i_D1, + I1 => is_read, + I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2), + I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1), + I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3), + I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0), + O => \^s_axi_arready\ + ); +s_axi_wready_INST_0: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAAAAEAAAA" + ) + port map ( + I0 => ip2bus_wrack_i_D1, + I1 => is_write_reg, + I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2), + I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1), + I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3), + I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0), + O => \^s_axi_wready\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_gpio_0_0_cdc_sync is + port ( + gpio_data_in_xor : out STD_LOGIC; + scndry_vect_out : out STD_LOGIC_VECTOR ( 0 to 0 ); + gpio_Data_In : in STD_LOGIC; + gpio_io_i : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_gpio_0_0_cdc_sync : entity is "cdc_sync"; +end Arty_Z7_20_axi_gpio_0_0_cdc_sync; + +architecture STRUCTURE of Arty_Z7_20_axi_gpio_0_0_cdc_sync is + signal \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2_n_0\ : STD_LOGIC; + signal \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3_n_0\ : STD_LOGIC; + signal Q : STD_LOGIC; + signal \^scndry_vect_out\ : STD_LOGIC_VECTOR ( 0 to 0 ); + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; +begin + scndry_vect_out(0) <= \^scndry_vect_out\(0); +\Dual.gen_interrupt_dual.gpio_data_in_xor_reg[0]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => gpio_Data_In, + I1 => \^scndry_vect_out\(0), + O => gpio_data_in_xor + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => Q, + Q => \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2_n_0\, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2_n_0\, + Q => \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3_n_0\, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3_n_0\, + Q => \^scndry_vect_out\(0), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i(0), + Q => Q, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_gpio_0_0_cdc_sync_0 is + port ( + gpio2_data_in_xor : out STD_LOGIC; + scndry_vect_out : out STD_LOGIC_VECTOR ( 0 to 0 ); + gpio2_Data_In : in STD_LOGIC; + gpio2_io_i : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_gpio_0_0_cdc_sync_0 : entity is "cdc_sync"; +end Arty_Z7_20_axi_gpio_0_0_cdc_sync_0; + +architecture STRUCTURE of Arty_Z7_20_axi_gpio_0_0_cdc_sync_0 is + signal \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2_n_0\ : STD_LOGIC; + signal \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3_n_0\ : STD_LOGIC; + signal Q : STD_LOGIC; + signal \^scndry_vect_out\ : STD_LOGIC_VECTOR ( 0 to 0 ); + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; +begin + scndry_vect_out(0) <= \^scndry_vect_out\(0); +\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg[0]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => gpio2_Data_In, + I1 => \^scndry_vect_out\(0), + O => gpio2_data_in_xor + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => Q, + Q => \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2_n_0\, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2_n_0\, + Q => \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3_n_0\, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3_n_0\, + Q => \^scndry_vect_out\(0), + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio2_io_i(0), + Q => Q, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_gpio_0_0_interrupt_control is + port ( + irpt_wrack_d1 : out STD_LOGIC; + \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ : out STD_LOGIC; + p_1_in : out STD_LOGIC; + intr2bus_wrack : out STD_LOGIC; + irpt_rdack_d1 : out STD_LOGIC; + intr2bus_rdack : out STD_LOGIC; + ipif_glbl_irpt_enable_reg : out STD_LOGIC; + IP2INTC_Irpt_i : out STD_LOGIC; + \ip_irpt_enable_reg_reg[0]_0\ : out STD_LOGIC; + \ip_irpt_enable_reg_reg[1]_0\ : out STD_LOGIC; + rst : in STD_LOGIC; + irpt_wrack : in STD_LOGIC; + s_axi_aclk : in STD_LOGIC; + GPIO_intr : in STD_LOGIC; + GPIO2_intr : in STD_LOGIC; + interrupt_wrce_strb : in STD_LOGIC; + irpt_rdack : in STD_LOGIC; + intr2bus_rdack0 : in STD_LOGIC; + \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\ : in STD_LOGIC; + irpt_wrack_d1_reg_0 : in STD_LOGIC; + s_axi_wdata : in STD_LOGIC_VECTOR ( 1 downto 0 ); + p_6_in : in STD_LOGIC; + Bus_RNW_reg : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_gpio_0_0_interrupt_control : entity is "interrupt_control"; +end Arty_Z7_20_axi_gpio_0_0_interrupt_control; + +architecture STRUCTURE of Arty_Z7_20_axi_gpio_0_0_interrupt_control is + signal \DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\ : STD_LOGIC; + signal \DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\ : STD_LOGIC; + signal \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\ : STD_LOGIC; + signal \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\ : STD_LOGIC; + signal \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1_n_0\ : STD_LOGIC; + signal \ip_irpt_enable_reg[0]_i_1_n_0\ : STD_LOGIC; + signal \ip_irpt_enable_reg[1]_i_1_n_0\ : STD_LOGIC; + signal \^ip_irpt_enable_reg_reg[0]_0\ : STD_LOGIC; + signal \^ip_irpt_enable_reg_reg[1]_0\ : STD_LOGIC; + signal \^ipif_glbl_irpt_enable_reg\ : STD_LOGIC; + signal irpt_dly1 : STD_LOGIC; + signal irpt_dly2 : STD_LOGIC; + signal \^p_1_in\ : STD_LOGIC; +begin + \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ <= \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\; + \ip_irpt_enable_reg_reg[0]_0\ <= \^ip_irpt_enable_reg_reg[0]_0\; + \ip_irpt_enable_reg_reg[1]_0\ <= \^ip_irpt_enable_reg_reg[1]_0\; + ipif_glbl_irpt_enable_reg <= \^ipif_glbl_irpt_enable_reg\; + p_1_in <= \^p_1_in\; +\DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly1_reg\: unisim.vcomponents.FDSE + port map ( + C => s_axi_aclk, + CE => '1', + D => GPIO_intr, + Q => irpt_dly1, + S => rst + ); +\DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly2_reg\: unisim.vcomponents.FDSE + port map ( + C => s_axi_aclk, + CE => '1', + D => irpt_dly1, + Q => irpt_dly2, + S => rst + ); +\DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly1_reg\: unisim.vcomponents.FDSE + port map ( + C => s_axi_aclk, + CE => '1', + D => GPIO2_intr, + Q => \DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\, + S => rst + ); +\DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly2_reg\: unisim.vcomponents.FDSE + port map ( + C => s_axi_aclk, + CE => '1', + D => \DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\, + Q => \DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\, + S => rst + ); +\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BAFF7530" + ) + port map ( + I0 => irpt_wrack_d1_reg_0, + I1 => irpt_dly2, + I2 => irpt_dly1, + I3 => s_axi_wdata(0), + I4 => \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\, + O => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\ + ); +\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\, + Q => \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\, + R => rst + ); +\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BAFF7530" + ) + port map ( + I0 => irpt_wrack_d1_reg_0, + I1 => \DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\, + I2 => \DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\, + I3 => s_axi_wdata(1), + I4 => \^p_1_in\, + O => \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1_n_0\ + ); +\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1_n_0\, + Q => \^p_1_in\, + R => rst + ); +\INTR_CTRLR_GEN.ip2intc_irpt_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AA808080" + ) + port map ( + I0 => \^ipif_glbl_irpt_enable_reg\, + I1 => \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\, + I2 => \^ip_irpt_enable_reg_reg[0]_0\, + I3 => \^p_1_in\, + I4 => \^ip_irpt_enable_reg_reg[1]_0\, + O => IP2INTC_Irpt_i + ); +intr2bus_rdack_reg: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => intr2bus_rdack0, + Q => intr2bus_rdack, + R => rst + ); +intr2bus_wrack_reg: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => interrupt_wrce_strb, + Q => intr2bus_wrack, + R => rst + ); +\ip_irpt_enable_reg[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_wdata(0), + I1 => p_6_in, + I2 => Bus_RNW_reg, + I3 => \^ip_irpt_enable_reg_reg[0]_0\, + O => \ip_irpt_enable_reg[0]_i_1_n_0\ + ); +\ip_irpt_enable_reg[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => s_axi_wdata(1), + I1 => p_6_in, + I2 => Bus_RNW_reg, + I3 => \^ip_irpt_enable_reg_reg[1]_0\, + O => \ip_irpt_enable_reg[1]_i_1_n_0\ + ); +\ip_irpt_enable_reg_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \ip_irpt_enable_reg[0]_i_1_n_0\, + Q => \^ip_irpt_enable_reg_reg[0]_0\, + R => rst + ); +\ip_irpt_enable_reg_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \ip_irpt_enable_reg[1]_i_1_n_0\, + Q => \^ip_irpt_enable_reg_reg[1]_0\, + R => rst + ); +ipif_glbl_irpt_enable_reg_reg: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\, + Q => \^ipif_glbl_irpt_enable_reg\, + R => rst + ); +irpt_rdack_d1_reg: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => irpt_rdack, + Q => irpt_rdack_d1, + R => rst + ); +irpt_wrack_d1_reg: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => irpt_wrack, + Q => irpt_wrack_d1, + R => rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_gpio_0_0_GPIO_Core is + port ( + GPIO_xferAck_i : out STD_LOGIC; + gpio_xferAck_Reg : out STD_LOGIC; + gpio2_Data_In : out STD_LOGIC; + gpio_Data_In : out STD_LOGIC; + GPIO_intr : out STD_LOGIC; + GPIO2_intr : out STD_LOGIC; + GPIO2_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 ); + GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 ); + gpio2_io_t : out STD_LOGIC_VECTOR ( 0 to 0 ); + gpio_io_t : out STD_LOGIC_VECTOR ( 0 to 0 ); + gpio_io_o : out STD_LOGIC_VECTOR ( 0 to 0 ); + gpio2_io_o : out STD_LOGIC_VECTOR ( 0 to 0 ); + ip2bus_rdack_i : out STD_LOGIC; + rst : in STD_LOGIC; + s_axi_aclk : in STD_LOGIC; + \Dual.gpio2_Data_In_reg[0]_0\ : in STD_LOGIC; + \Dual.gpio_Data_In_reg[0]_0\ : in STD_LOGIC; + bus2ip_rnw_i_reg : in STD_LOGIC; + bus2ip_rnw_i_reg_0 : in STD_LOGIC; + bus2ip_rnw_i_reg_1 : in STD_LOGIC; + bus2ip_rnw_i_reg_2 : in STD_LOGIC; + bus2ip_cs : in STD_LOGIC_VECTOR ( 0 to 0 ); + bus2ip_rnw : in STD_LOGIC; + intr2bus_rdack : in STD_LOGIC; + ip2Bus_RdAck_intr_reg_hole : in STD_LOGIC; + gpio_io_i : in STD_LOGIC_VECTOR ( 0 to 0 ); + gpio2_io_i : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_gpio_0_0_GPIO_Core : entity is "GPIO_Core"; +end Arty_Z7_20_axi_gpio_0_0_GPIO_Core; + +architecture STRUCTURE of Arty_Z7_20_axi_gpio_0_0_GPIO_Core is + signal \Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg_n_0_[0]\ : STD_LOGIC; + signal \^gpio_xferack_i\ : STD_LOGIC; + signal \^gpio2_data_in\ : STD_LOGIC; + signal gpio2_data_in_xor : STD_LOGIC; + signal gpio2_io_i_d2 : STD_LOGIC; + signal \^gpio_data_in\ : STD_LOGIC; + signal gpio_data_in_xor : STD_LOGIC; + signal gpio_io_i_d2 : STD_LOGIC; + signal \^gpio_xferack_reg\ : STD_LOGIC; + signal iGPIO_xferAck : STD_LOGIC; + signal l : STD_LOGIC; +begin + GPIO_xferAck_i <= \^gpio_xferack_i\; + gpio2_Data_In <= \^gpio2_data_in\; + gpio_Data_In <= \^gpio_data_in\; + gpio_xferAck_Reg <= \^gpio_xferack_reg\; +\Dual.INPUT_DOUBLE_REGS4\: entity work.Arty_Z7_20_axi_gpio_0_0_cdc_sync + port map ( + gpio_Data_In => \^gpio_data_in\, + gpio_data_in_xor => gpio_data_in_xor, + gpio_io_i(0) => gpio_io_i(0), + s_axi_aclk => s_axi_aclk, + scndry_vect_out(0) => gpio_io_i_d2 + ); +\Dual.INPUT_DOUBLE_REGS5\: entity work.Arty_Z7_20_axi_gpio_0_0_cdc_sync_0 + port map ( + gpio2_Data_In => \^gpio2_data_in\, + gpio2_data_in_xor => gpio2_data_in_xor, + gpio2_io_i(0) => gpio2_io_i(0), + s_axi_aclk => s_axi_aclk, + scndry_vect_out(0) => gpio2_io_i_d2 + ); +\Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Dual.gpio2_Data_In_reg[0]_0\, + Q => GPIO2_DBus_i(0), + R => '0' + ); +\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Dual.gpio_Data_In_reg[0]_0\, + Q => GPIO_DBus_i(0), + R => '0' + ); +\Dual.gen_interrupt_dual.GPIO2_intr_reg\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg_n_0_[0]\, + Q => GPIO2_intr, + R => rst + ); +\Dual.gen_interrupt_dual.GPIO_intr_reg\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => l, + Q => GPIO_intr, + R => rst + ); +\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio2_data_in_xor, + Q => \Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg_n_0_[0]\, + R => rst + ); +\Dual.gen_interrupt_dual.gpio_data_in_xor_reg_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_data_in_xor, + Q => l, + R => rst + ); +\Dual.gpio2_Data_In_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio2_io_i_d2, + Q => \^gpio2_data_in\, + R => '0' + ); +\Dual.gpio2_Data_Out_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => bus2ip_rnw_i_reg_2, + Q => gpio2_io_o(0), + R => rst + ); +\Dual.gpio2_OE_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => bus2ip_rnw_i_reg, + Q => gpio2_io_t(0), + S => rst + ); +\Dual.gpio_Data_In_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => gpio_io_i_d2, + Q => \^gpio_data_in\, + R => '0' + ); +\Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => bus2ip_rnw_i_reg_1, + Q => gpio_io_o(0), + R => rst + ); +\Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => bus2ip_rnw_i_reg_0, + Q => gpio_io_t(0), + S => rst + ); +gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \^gpio_xferack_i\, + Q => \^gpio_xferack_reg\, + R => rst + ); +iGPIO_xferAck_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"02" + ) + port map ( + I0 => bus2ip_cs(0), + I1 => \^gpio_xferack_reg\, + I2 => \^gpio_xferack_i\, + O => iGPIO_xferAck + ); +iGPIO_xferAck_reg: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => iGPIO_xferAck, + Q => \^gpio_xferack_i\, + R => rst + ); +ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFF8" + ) + port map ( + I0 => \^gpio_xferack_i\, + I1 => bus2ip_rnw, + I2 => intr2bus_rdack, + I3 => ip2Bus_RdAck_intr_reg_hole, + O => ip2bus_rdack_i + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_gpio_0_0_slave_attachment is + port ( + \ip2bus_data_i_D1_reg[31]\ : out STD_LOGIC; + \Dual.gpio2_OE_reg[0]\ : out STD_LOGIC; + iGPIO_xferAck_reg : out STD_LOGIC; + ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC; + s_axi_rvalid : out STD_LOGIC; + s_axi_bvalid : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + irpt_wrack : out STD_LOGIC; + interrupt_wrce_strb : out STD_LOGIC; + intr2bus_rdack0 : out STD_LOGIC; + irpt_rdack : out STD_LOGIC; + p_3_out : out STD_LOGIC; + intr_rd_ce_or_reduce : out STD_LOGIC; + \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC; + intr_wr_ce_or_reduce : out STD_LOGIC; + ip2bus_wrack_i : out STD_LOGIC; + \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\ : out STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_wready : out STD_LOGIC; + \Dual.gpio2_OE_reg[0]_0\ : out STD_LOGIC; + \Dual.gpio_OE_reg[0]\ : out STD_LOGIC; + \Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC; + \Dual.gpio2_Data_Out_reg[0]\ : out STD_LOGIC; + ipif_glbl_irpt_enable_reg_reg_0 : out STD_LOGIC; + \Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[31]\ : out STD_LOGIC; + \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[31]\ : out STD_LOGIC; + s_axi_rdata : out STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_aclk : in STD_LOGIC; + rst : in STD_LOGIC; + gpio_xferAck_Reg : in STD_LOGIC; + GPIO_xferAck_i : in STD_LOGIC; + \ip_irpt_enable_reg_reg[0]\ : in STD_LOGIC; + \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ : in STD_LOGIC; + GPIO2_DBus_i : in STD_LOGIC_VECTOR ( 0 to 0 ); + GPIO_DBus_i : in STD_LOGIC_VECTOR ( 0 to 0 ); + irpt_wrack_d1 : in STD_LOGIC; + irpt_rdack_d1 : in STD_LOGIC; + ipif_glbl_irpt_enable_reg : in STD_LOGIC; + p_1_in : in STD_LOGIC; + \ip_irpt_enable_reg_reg[1]\ : in STD_LOGIC; + ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC; + ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC; + intr2bus_wrack : in STD_LOGIC; + ip2Bus_WrAck_intr_reg_hole : in STD_LOGIC; + s_axi_arvalid : in STD_LOGIC; + s_axi_awvalid : in STD_LOGIC; + s_axi_wvalid : in STD_LOGIC; + s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 ); + s_axi_rready : in STD_LOGIC; + s_axi_bready : in STD_LOGIC; + ip2bus_rdack_i_D1 : in STD_LOGIC; + ip2bus_wrack_i_D1 : in STD_LOGIC; + s_axi_wdata : in STD_LOGIC_VECTOR ( 1 downto 0 ); + gpio2_io_t : in STD_LOGIC_VECTOR ( 0 to 0 ); + gpio_io_t : in STD_LOGIC_VECTOR ( 0 to 0 ); + gpio_io_o : in STD_LOGIC_VECTOR ( 0 to 0 ); + gpio2_io_o : in STD_LOGIC_VECTOR ( 0 to 0 ); + gpio2_Data_In : in STD_LOGIC; + gpio_Data_In : in STD_LOGIC; + s_axi_aresetn : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 2 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_gpio_0_0_slave_attachment : entity is "slave_attachment"; +end Arty_Z7_20_axi_gpio_0_0_slave_attachment; + +architecture STRUCTURE of Arty_Z7_20_axi_gpio_0_0_slave_attachment is + signal \^dual.gpio2_oe_reg[0]\ : STD_LOGIC; + signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 6 ); + signal \bus2ip_addr_i[8]_i_1_n_0\ : STD_LOGIC; + signal bus2ip_rnw_i06_out : STD_LOGIC; + signal clear : STD_LOGIC; + signal is_read : STD_LOGIC; + signal is_read_i_1_n_0 : STD_LOGIC; + signal is_write : STD_LOGIC; + signal is_write_i_1_n_0 : STD_LOGIC; + signal is_write_reg_n_0 : STD_LOGIC; + signal \p_0_out__0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 8 downto 2 ); + signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^s_axi_arready\ : STD_LOGIC; + signal \^s_axi_bvalid\ : STD_LOGIC; + signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC; + signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \s_axi_rdata_i[0]_i_1_n_0\ : STD_LOGIC; + signal \s_axi_rdata_i[1]_i_1_n_0\ : STD_LOGIC; + signal \s_axi_rdata_i[31]_i_1_n_0\ : STD_LOGIC; + signal \^s_axi_rvalid\ : STD_LOGIC; + signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC; + signal \^s_axi_wready\ : STD_LOGIC; + signal start2 : STD_LOGIC; + signal start2_i_1_n_0 : STD_LOGIC; + signal state : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \state1__2\ : STD_LOGIC; + signal \state[1]_i_3_n_0\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \bus2ip_addr_i[6]_i_1\ : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair4"; +begin + \Dual.gpio2_OE_reg[0]\ <= \^dual.gpio2_oe_reg[0]\; + s_axi_arready <= \^s_axi_arready\; + s_axi_bvalid <= \^s_axi_bvalid\; + s_axi_rdata(2 downto 0) <= \^s_axi_rdata\(2 downto 0); + s_axi_rvalid <= \^s_axi_rvalid\; + s_axi_wready <= \^s_axi_wready\; +\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), + O => plusOp(0) + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), + I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), + O => plusOp(1) + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), + I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), + I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), + O => plusOp(2) + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => state(0), + I1 => state(1), + O => clear + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), + I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), + I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), + I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3), + O => plusOp(3) + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => plusOp(0), + Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), + R => clear + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => plusOp(1), + Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), + R => clear + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => plusOp(2), + Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), + R => clear + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => plusOp(3), + Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3), + R => clear + ); +I_DECODER: entity work.Arty_Z7_20_axi_gpio_0_0_address_decoder + port map ( + D(2 downto 0) => D(2 downto 0), + \Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[31]\ => \Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[31]\, + \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[31]\ => \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[31]\, + \Dual.gpio2_Data_Out_reg[0]\ => \Dual.gpio2_Data_Out_reg[0]\, + \Dual.gpio2_OE_reg[0]\ => \Dual.gpio2_OE_reg[0]_0\, + \Dual.gpio_Data_Out_reg[0]\ => \Dual.gpio_Data_Out_reg[0]\, + \Dual.gpio_OE_reg[0]\ => \Dual.gpio_OE_reg[0]\, + \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\, + \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\ => \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\, + GPIO2_DBus_i(0) => GPIO2_DBus_i(0), + GPIO_DBus_i(0) => GPIO_DBus_i(0), + GPIO_xferAck_i => GPIO_xferAck_i, + \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0), + \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\, + Q => start2, + \bus2ip_addr_i_reg[8]\(6) => bus2ip_addr(0), + \bus2ip_addr_i_reg[8]\(5) => bus2ip_addr(1), + \bus2ip_addr_i_reg[8]\(4) => bus2ip_addr(2), + \bus2ip_addr_i_reg[8]\(3) => bus2ip_addr(3), + \bus2ip_addr_i_reg[8]\(2) => bus2ip_addr(4), + \bus2ip_addr_i_reg[8]\(1) => bus2ip_addr(5), + \bus2ip_addr_i_reg[8]\(0) => bus2ip_addr(6), + bus2ip_rnw_i_reg => \^dual.gpio2_oe_reg[0]\, + gpio2_Data_In => gpio2_Data_In, + gpio2_io_o(0) => gpio2_io_o(0), + gpio2_io_t(0) => gpio2_io_t(0), + gpio_Data_In => gpio_Data_In, + gpio_io_o(0) => gpio_io_o(0), + gpio_io_t(0) => gpio_io_t(0), + gpio_xferAck_Reg => gpio_xferAck_Reg, + iGPIO_xferAck_reg => iGPIO_xferAck_reg, + interrupt_wrce_strb => interrupt_wrce_strb, + intr2bus_rdack0 => intr2bus_rdack0, + intr_rd_ce_or_reduce => intr_rd_ce_or_reduce, + intr_wr_ce_or_reduce => intr_wr_ce_or_reduce, + ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1, + ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1, + \ip2bus_data_i_D1_reg[31]\ => \ip2bus_data_i_D1_reg[31]\, + ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1, + ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1, + \ip_irpt_enable_reg_reg[0]\ => \ip_irpt_enable_reg_reg[0]\, + \ip_irpt_enable_reg_reg[1]\ => \ip_irpt_enable_reg_reg[1]\, + ipif_glbl_irpt_enable_reg => ipif_glbl_irpt_enable_reg, + ipif_glbl_irpt_enable_reg_reg => ipif_glbl_irpt_enable_reg_reg, + ipif_glbl_irpt_enable_reg_reg_0 => ipif_glbl_irpt_enable_reg_reg_0, + irpt_rdack => irpt_rdack, + irpt_rdack_d1 => irpt_rdack_d1, + irpt_wrack => irpt_wrack, + irpt_wrack_d1 => irpt_wrack_d1, + is_read => is_read, + is_write_reg => is_write_reg_n_0, + p_1_in => p_1_in, + p_3_out => p_3_out, + s_axi_aclk => s_axi_aclk, + s_axi_aresetn => s_axi_aresetn, + s_axi_arready => \^s_axi_arready\, + s_axi_wdata(1 downto 0) => s_axi_wdata(1 downto 0), + s_axi_wready => \^s_axi_wready\ + ); +\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"CCCACCCC" + ) + port map ( + I0 => s_axi_araddr(0), + I1 => s_axi_awaddr(0), + I2 => state(0), + I3 => state(1), + I4 => s_axi_arvalid, + O => \p_1_in__0\(2) + ); +\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"CCCACCCC" + ) + port map ( + I0 => s_axi_araddr(1), + I1 => s_axi_awaddr(1), + I2 => state(0), + I3 => state(1), + I4 => s_axi_arvalid, + O => \p_1_in__0\(3) + ); +\bus2ip_addr_i[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"CCCACCCC" + ) + port map ( + I0 => s_axi_araddr(2), + I1 => s_axi_awaddr(2), + I2 => state(0), + I3 => state(1), + I4 => s_axi_arvalid, + O => \p_1_in__0\(4) + ); +\bus2ip_addr_i[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"CCCACCCC" + ) + port map ( + I0 => s_axi_araddr(3), + I1 => s_axi_awaddr(3), + I2 => state(0), + I3 => state(1), + I4 => s_axi_arvalid, + O => \p_1_in__0\(5) + ); +\bus2ip_addr_i[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"CCCACCCC" + ) + port map ( + I0 => s_axi_araddr(4), + I1 => s_axi_awaddr(4), + I2 => state(0), + I3 => state(1), + I4 => s_axi_arvalid, + O => \p_1_in__0\(6) + ); +\bus2ip_addr_i[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"CCCACCCC" + ) + port map ( + I0 => s_axi_araddr(5), + I1 => s_axi_awaddr(5), + I2 => state(0), + I3 => state(1), + I4 => s_axi_arvalid, + O => \p_1_in__0\(7) + ); +\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000EA" + ) + port map ( + I0 => s_axi_arvalid, + I1 => s_axi_awvalid, + I2 => s_axi_wvalid, + I3 => state(1), + I4 => state(0), + O => \bus2ip_addr_i[8]_i_1_n_0\ + ); +\bus2ip_addr_i[8]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"CCCACCCC" + ) + port map ( + I0 => s_axi_araddr(6), + I1 => s_axi_awaddr(6), + I2 => state(0), + I3 => state(1), + I4 => s_axi_arvalid, + O => \p_1_in__0\(8) + ); +\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => \bus2ip_addr_i[8]_i_1_n_0\, + D => \p_1_in__0\(2), + Q => bus2ip_addr(6), + R => rst + ); +\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => \bus2ip_addr_i[8]_i_1_n_0\, + D => \p_1_in__0\(3), + Q => bus2ip_addr(5), + R => rst + ); +\bus2ip_addr_i_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => \bus2ip_addr_i[8]_i_1_n_0\, + D => \p_1_in__0\(4), + Q => bus2ip_addr(4), + R => rst + ); +\bus2ip_addr_i_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => \bus2ip_addr_i[8]_i_1_n_0\, + D => \p_1_in__0\(5), + Q => bus2ip_addr(3), + R => rst + ); +\bus2ip_addr_i_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => \bus2ip_addr_i[8]_i_1_n_0\, + D => \p_1_in__0\(6), + Q => bus2ip_addr(2), + R => rst + ); +\bus2ip_addr_i_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => \bus2ip_addr_i[8]_i_1_n_0\, + D => \p_1_in__0\(7), + Q => bus2ip_addr(1), + R => rst + ); +\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => \bus2ip_addr_i[8]_i_1_n_0\, + D => \p_1_in__0\(8), + Q => bus2ip_addr(0), + R => rst + ); +bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"10" + ) + port map ( + I0 => state(0), + I1 => state(1), + I2 => s_axi_arvalid, + O => bus2ip_rnw_i06_out + ); +bus2ip_rnw_i_reg: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => \bus2ip_addr_i[8]_i_1_n_0\, + D => bus2ip_rnw_i06_out, + Q => \^dual.gpio2_oe_reg[0]\, + R => rst + ); +ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFF4" + ) + port map ( + I0 => \^dual.gpio2_oe_reg[0]\, + I1 => GPIO_xferAck_i, + I2 => intr2bus_wrack, + I3 => ip2Bus_WrAck_intr_reg_hole, + O => ip2bus_wrack_i + ); +is_read_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"3FFA000A" + ) + port map ( + I0 => s_axi_arvalid, + I1 => \state1__2\, + I2 => state(0), + I3 => state(1), + I4 => is_read, + O => is_read_i_1_n_0 + ); +is_read_reg: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => is_read_i_1_n_0, + Q => is_read, + R => rst + ); +is_write_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0040FFFF00400000" + ) + port map ( + I0 => s_axi_arvalid, + I1 => s_axi_awvalid, + I2 => s_axi_wvalid, + I3 => state(1), + I4 => is_write, + I5 => is_write_reg_n_0, + O => is_write_i_1_n_0 + ); +is_write_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"F88800000000FFFF" + ) + port map ( + I0 => \^s_axi_rvalid\, + I1 => s_axi_rready, + I2 => \^s_axi_bvalid\, + I3 => s_axi_bready, + I4 => state(0), + I5 => state(1), + O => is_write + ); +is_write_reg: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => is_write_i_1_n_0, + Q => is_write_reg_n_0, + R => rst + ); +s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"08FF0808" + ) + port map ( + I0 => \^s_axi_wready\, + I1 => state(1), + I2 => state(0), + I3 => s_axi_bready, + I4 => \^s_axi_bvalid\, + O => s_axi_bvalid_i_i_1_n_0 + ); +s_axi_bvalid_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_axi_bvalid_i_i_1_n_0, + Q => \^s_axi_bvalid\, + R => rst + ); +\s_axi_rdata_i[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => Q(0), + I1 => state(0), + I2 => state(1), + I3 => \^s_axi_rdata\(0), + O => \s_axi_rdata_i[0]_i_1_n_0\ + ); +\s_axi_rdata_i[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => Q(1), + I1 => state(0), + I2 => state(1), + I3 => \^s_axi_rdata\(1), + O => \s_axi_rdata_i[1]_i_1_n_0\ + ); +\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => Q(2), + I1 => state(0), + I2 => state(1), + I3 => \^s_axi_rdata\(2), + O => \s_axi_rdata_i[31]_i_1_n_0\ + ); +\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => \s_axi_rdata_i[0]_i_1_n_0\, + Q => \^s_axi_rdata\(0), + R => rst + ); +\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => \s_axi_rdata_i[1]_i_1_n_0\, + Q => \^s_axi_rdata\(1), + R => rst + ); +\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => \s_axi_rdata_i[31]_i_1_n_0\, + Q => \^s_axi_rdata\(2), + R => rst + ); +s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"08FF0808" + ) + port map ( + I0 => \^s_axi_arready\, + I1 => state(0), + I2 => state(1), + I3 => s_axi_rready, + I4 => \^s_axi_rvalid\, + O => s_axi_rvalid_i_i_1_n_0 + ); +s_axi_rvalid_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_aclk, + CE => '1', + D => s_axi_rvalid_i_i_1_n_0, + Q => \^s_axi_rvalid\, + R => rst + ); +start2_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000F8" + ) + port map ( + I0 => s_axi_awvalid, + I1 => s_axi_wvalid, + I2 => s_axi_arvalid, + I3 => state(1), + I4 => state(0), + O => start2_i_1_n_0 + ); +start2_reg: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => start2_i_1_n_0, + Q => start2, + R => rst + ); +\state[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"77FC44FC" + ) + port map ( + I0 => \state1__2\, + I1 => state(0), + I2 => s_axi_arvalid, + I3 => state(1), + I4 => \^s_axi_wready\, + O => \p_0_out__0\(0) + ); +\state[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"5FFC50FC" + ) + port map ( + I0 => \state1__2\, + I1 => \state[1]_i_3_n_0\, + I2 => state(1), + I3 => state(0), + I4 => \^s_axi_arready\, + O => \p_0_out__0\(1) + ); +\state[1]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F888" + ) + port map ( + I0 => s_axi_bready, + I1 => \^s_axi_bvalid\, + I2 => s_axi_rready, + I3 => \^s_axi_rvalid\, + O => \state1__2\ + ); +\state[1]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => s_axi_wvalid, + I1 => s_axi_awvalid, + I2 => s_axi_arvalid, + O => \state[1]_i_3_n_0\ + ); +\state_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \p_0_out__0\(0), + Q => state(0), + R => rst + ); +\state_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => \p_0_out__0\(1), + Q => state(1), + R => rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_gpio_0_0_axi_lite_ipif is + port ( + p_6_in : out STD_LOGIC; + bus2ip_rnw : out STD_LOGIC; + bus2ip_cs : out STD_LOGIC_VECTOR ( 0 to 0 ); + Bus_RNW_reg : out STD_LOGIC; + s_axi_rvalid : out STD_LOGIC; + s_axi_bvalid : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + irpt_wrack : out STD_LOGIC; + interrupt_wrce_strb : out STD_LOGIC; + intr2bus_rdack0 : out STD_LOGIC; + irpt_rdack : out STD_LOGIC; + p_3_out : out STD_LOGIC; + intr_rd_ce_or_reduce : out STD_LOGIC; + \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC; + intr_wr_ce_or_reduce : out STD_LOGIC; + ip2bus_wrack_i : out STD_LOGIC; + \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\ : out STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_wready : out STD_LOGIC; + \Dual.gpio2_OE_reg[0]\ : out STD_LOGIC; + \Dual.gpio_OE_reg[0]\ : out STD_LOGIC; + \Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC; + \Dual.gpio2_Data_Out_reg[0]\ : out STD_LOGIC; + ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC; + \Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[31]\ : out STD_LOGIC; + \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[31]\ : out STD_LOGIC; + s_axi_rdata : out STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_aclk : in STD_LOGIC; + rst : in STD_LOGIC; + gpio_xferAck_Reg : in STD_LOGIC; + GPIO_xferAck_i : in STD_LOGIC; + \ip_irpt_enable_reg_reg[0]\ : in STD_LOGIC; + \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ : in STD_LOGIC; + GPIO2_DBus_i : in STD_LOGIC_VECTOR ( 0 to 0 ); + GPIO_DBus_i : in STD_LOGIC_VECTOR ( 0 to 0 ); + irpt_wrack_d1 : in STD_LOGIC; + irpt_rdack_d1 : in STD_LOGIC; + ipif_glbl_irpt_enable_reg : in STD_LOGIC; + p_1_in : in STD_LOGIC; + \ip_irpt_enable_reg_reg[1]\ : in STD_LOGIC; + ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC; + ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC; + intr2bus_wrack : in STD_LOGIC; + ip2Bus_WrAck_intr_reg_hole : in STD_LOGIC; + s_axi_arvalid : in STD_LOGIC; + s_axi_awvalid : in STD_LOGIC; + s_axi_wvalid : in STD_LOGIC; + s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 ); + s_axi_rready : in STD_LOGIC; + s_axi_bready : in STD_LOGIC; + ip2bus_rdack_i_D1 : in STD_LOGIC; + ip2bus_wrack_i_D1 : in STD_LOGIC; + s_axi_wdata : in STD_LOGIC_VECTOR ( 1 downto 0 ); + gpio2_io_t : in STD_LOGIC_VECTOR ( 0 to 0 ); + gpio_io_t : in STD_LOGIC_VECTOR ( 0 to 0 ); + gpio_io_o : in STD_LOGIC_VECTOR ( 0 to 0 ); + gpio2_io_o : in STD_LOGIC_VECTOR ( 0 to 0 ); + gpio2_Data_In : in STD_LOGIC; + gpio_Data_In : in STD_LOGIC; + s_axi_aresetn : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 2 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_gpio_0_0_axi_lite_ipif : entity is "axi_lite_ipif"; +end Arty_Z7_20_axi_gpio_0_0_axi_lite_ipif; + +architecture STRUCTURE of Arty_Z7_20_axi_gpio_0_0_axi_lite_ipif is +begin +I_SLAVE_ATTACHMENT: entity work.Arty_Z7_20_axi_gpio_0_0_slave_attachment + port map ( + D(2 downto 0) => D(2 downto 0), + \Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[31]\ => \Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[31]\, + \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[31]\ => \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[31]\, + \Dual.gpio2_Data_Out_reg[0]\ => \Dual.gpio2_Data_Out_reg[0]\, + \Dual.gpio2_OE_reg[0]\ => bus2ip_rnw, + \Dual.gpio2_OE_reg[0]_0\ => \Dual.gpio2_OE_reg[0]\, + \Dual.gpio_Data_Out_reg[0]\ => \Dual.gpio_Data_Out_reg[0]\, + \Dual.gpio_OE_reg[0]\ => \Dual.gpio_OE_reg[0]\, + \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\, + \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\ => \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\, + GPIO2_DBus_i(0) => GPIO2_DBus_i(0), + GPIO_DBus_i(0) => GPIO_DBus_i(0), + GPIO_xferAck_i => GPIO_xferAck_i, + \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\, + Q(2 downto 0) => Q(2 downto 0), + gpio2_Data_In => gpio2_Data_In, + gpio2_io_o(0) => gpio2_io_o(0), + gpio2_io_t(0) => gpio2_io_t(0), + gpio_Data_In => gpio_Data_In, + gpio_io_o(0) => gpio_io_o(0), + gpio_io_t(0) => gpio_io_t(0), + gpio_xferAck_Reg => gpio_xferAck_Reg, + iGPIO_xferAck_reg => bus2ip_cs(0), + interrupt_wrce_strb => interrupt_wrce_strb, + intr2bus_rdack0 => intr2bus_rdack0, + intr2bus_wrack => intr2bus_wrack, + intr_rd_ce_or_reduce => intr_rd_ce_or_reduce, + intr_wr_ce_or_reduce => intr_wr_ce_or_reduce, + ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1, + ip2Bus_WrAck_intr_reg_hole => ip2Bus_WrAck_intr_reg_hole, + ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1, + \ip2bus_data_i_D1_reg[31]\ => p_6_in, + ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1, + ip2bus_wrack_i => ip2bus_wrack_i, + ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1, + \ip_irpt_enable_reg_reg[0]\ => \ip_irpt_enable_reg_reg[0]\, + \ip_irpt_enable_reg_reg[1]\ => \ip_irpt_enable_reg_reg[1]\, + ipif_glbl_irpt_enable_reg => ipif_glbl_irpt_enable_reg, + ipif_glbl_irpt_enable_reg_reg => Bus_RNW_reg, + ipif_glbl_irpt_enable_reg_reg_0 => ipif_glbl_irpt_enable_reg_reg, + irpt_rdack => irpt_rdack, + irpt_rdack_d1 => irpt_rdack_d1, + irpt_wrack => irpt_wrack, + irpt_wrack_d1 => irpt_wrack_d1, + p_1_in => p_1_in, + p_3_out => p_3_out, + rst => rst, + s_axi_aclk => s_axi_aclk, + s_axi_araddr(6 downto 0) => s_axi_araddr(6 downto 0), + s_axi_aresetn => s_axi_aresetn, + s_axi_arready => s_axi_arready, + s_axi_arvalid => s_axi_arvalid, + s_axi_awaddr(6 downto 0) => s_axi_awaddr(6 downto 0), + s_axi_awvalid => s_axi_awvalid, + s_axi_bready => s_axi_bready, + s_axi_bvalid => s_axi_bvalid, + s_axi_rdata(2 downto 0) => s_axi_rdata(2 downto 0), + s_axi_rready => s_axi_rready, + s_axi_rvalid => s_axi_rvalid, + s_axi_wdata(1 downto 0) => s_axi_wdata(1 downto 0), + s_axi_wready => s_axi_wready, + s_axi_wvalid => s_axi_wvalid + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_gpio_0_0_axi_gpio is + port ( + s_axi_aclk : in STD_LOGIC; + s_axi_aresetn : in STD_LOGIC; + s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_arvalid : in STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rvalid : out STD_LOGIC; + s_axi_rready : in STD_LOGIC; + ip2intc_irpt : out STD_LOGIC; + gpio_io_i : in STD_LOGIC_VECTOR ( 0 to 0 ); + gpio_io_o : out STD_LOGIC_VECTOR ( 0 to 0 ); + gpio_io_t : out STD_LOGIC_VECTOR ( 0 to 0 ); + gpio2_io_i : in STD_LOGIC_VECTOR ( 0 to 0 ); + gpio2_io_o : out STD_LOGIC_VECTOR ( 0 to 0 ); + gpio2_io_t : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute C_ALL_INPUTS : integer; + attribute C_ALL_INPUTS of Arty_Z7_20_axi_gpio_0_0_axi_gpio : entity is 0; + attribute C_ALL_INPUTS_2 : integer; + attribute C_ALL_INPUTS_2 of Arty_Z7_20_axi_gpio_0_0_axi_gpio : entity is 1; + attribute C_ALL_OUTPUTS : integer; + attribute C_ALL_OUTPUTS of Arty_Z7_20_axi_gpio_0_0_axi_gpio : entity is 1; + attribute C_ALL_OUTPUTS_2 : integer; + attribute C_ALL_OUTPUTS_2 of Arty_Z7_20_axi_gpio_0_0_axi_gpio : entity is 0; + attribute C_DOUT_DEFAULT : integer; + attribute C_DOUT_DEFAULT of Arty_Z7_20_axi_gpio_0_0_axi_gpio : entity is 0; + attribute C_DOUT_DEFAULT_2 : integer; + attribute C_DOUT_DEFAULT_2 of Arty_Z7_20_axi_gpio_0_0_axi_gpio : entity is 0; + attribute C_FAMILY : string; + attribute C_FAMILY of Arty_Z7_20_axi_gpio_0_0_axi_gpio : entity is "zynq"; + attribute C_GPIO2_WIDTH : integer; + attribute C_GPIO2_WIDTH of Arty_Z7_20_axi_gpio_0_0_axi_gpio : entity is 1; + attribute C_GPIO_WIDTH : integer; + attribute C_GPIO_WIDTH of Arty_Z7_20_axi_gpio_0_0_axi_gpio : entity is 1; + attribute C_INTERRUPT_PRESENT : integer; + attribute C_INTERRUPT_PRESENT of Arty_Z7_20_axi_gpio_0_0_axi_gpio : entity is 1; + attribute C_IS_DUAL : integer; + attribute C_IS_DUAL of Arty_Z7_20_axi_gpio_0_0_axi_gpio : entity is 1; + attribute C_S_AXI_ADDR_WIDTH : integer; + attribute C_S_AXI_ADDR_WIDTH of Arty_Z7_20_axi_gpio_0_0_axi_gpio : entity is 9; + attribute C_S_AXI_DATA_WIDTH : integer; + attribute C_S_AXI_DATA_WIDTH of Arty_Z7_20_axi_gpio_0_0_axi_gpio : entity is 32; + attribute C_TRI_DEFAULT : integer; + attribute C_TRI_DEFAULT of Arty_Z7_20_axi_gpio_0_0_axi_gpio : entity is -1; + attribute C_TRI_DEFAULT_2 : integer; + attribute C_TRI_DEFAULT_2 of Arty_Z7_20_axi_gpio_0_0_axi_gpio : entity is -1; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_gpio_0_0_axi_gpio : entity is "axi_gpio"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of Arty_Z7_20_axi_gpio_0_0_axi_gpio : entity is "yes"; + attribute ip_group : string; + attribute ip_group of Arty_Z7_20_axi_gpio_0_0_axi_gpio : entity is "LOGICORE"; +end Arty_Z7_20_axi_gpio_0_0_axi_gpio; + +architecture STRUCTURE of Arty_Z7_20_axi_gpio_0_0_axi_gpio is + signal \\ : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_15 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_18 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_21 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_22 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_23 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_24 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_25 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_26 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_27 : STD_LOGIC; + signal GPIO2_DBus_i : STD_LOGIC_VECTOR ( 31 to 31 ); + signal GPIO2_intr : STD_LOGIC; + signal GPIO_DBus_i : STD_LOGIC_VECTOR ( 31 to 31 ); + signal GPIO_intr : STD_LOGIC; + signal GPIO_xferAck_i : STD_LOGIC; + signal \INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_1\ : STD_LOGIC; + signal \INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_8\ : STD_LOGIC; + signal \INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_9\ : STD_LOGIC; + signal IP2INTC_Irpt_i : STD_LOGIC; + signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC; + signal \I_SLAVE_ATTACHMENT/I_DECODER/p_6_in\ : STD_LOGIC; + signal \I_SLAVE_ATTACHMENT/rst\ : STD_LOGIC; + signal bus2ip_cs : STD_LOGIC_VECTOR ( 1 to 1 ); + signal bus2ip_reset_i_1_n_0 : STD_LOGIC; + signal bus2ip_rnw : STD_LOGIC; + signal gpio2_Data_In : STD_LOGIC; + signal \^gpio2_io_o\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^gpio2_io_t\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal gpio_Data_In : STD_LOGIC; + signal \^gpio_io_o\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^gpio_io_t\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal gpio_xferAck_Reg : STD_LOGIC; + signal interrupt_wrce_strb : STD_LOGIC; + signal intr2bus_rdack : STD_LOGIC; + signal intr2bus_rdack0 : STD_LOGIC; + signal intr2bus_wrack : STD_LOGIC; + signal intr_rd_ce_or_reduce : STD_LOGIC; + signal intr_wr_ce_or_reduce : STD_LOGIC; + signal ip2Bus_RdAck_intr_reg_hole : STD_LOGIC; + signal ip2Bus_RdAck_intr_reg_hole_d1 : STD_LOGIC; + signal ip2Bus_WrAck_intr_reg_hole : STD_LOGIC; + signal ip2Bus_WrAck_intr_reg_hole_d1 : STD_LOGIC; + signal ip2bus_data_i : STD_LOGIC_VECTOR ( 31 to 31 ); + signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 0 to 31 ); + signal ip2bus_rdack_i : STD_LOGIC; + signal ip2bus_rdack_i_D1 : STD_LOGIC; + signal ip2bus_wrack_i : STD_LOGIC; + signal ip2bus_wrack_i_D1 : STD_LOGIC; + signal ipif_glbl_irpt_enable_reg : STD_LOGIC; + signal irpt_rdack : STD_LOGIC; + signal irpt_rdack_d1 : STD_LOGIC; + signal irpt_wrack : STD_LOGIC; + signal irpt_wrack_d1 : STD_LOGIC; + signal p_0_out : STD_LOGIC_VECTOR ( 0 to 30 ); + signal p_1_in : STD_LOGIC; + signal p_3_out : STD_LOGIC; + signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \^s_axi_wready\ : STD_LOGIC; + attribute sigis : string; + attribute sigis of \INTR_CTRLR_GEN.ip2intc_irpt_reg\ : label is "INTR_LEVEL_HIGH"; +begin + gpio2_io_o(0) <= \^gpio2_io_o\(0); + gpio2_io_t(0) <= \^gpio2_io_t\(0); + gpio_io_o(0) <= \^gpio_io_o\(0); + gpio_io_t(0) <= \^gpio_io_t\(0); + s_axi_awready <= \^s_axi_wready\; + s_axi_bresp(1) <= \\; + s_axi_bresp(0) <= \\; + s_axi_rdata(31) <= \^s_axi_rdata\(31); + s_axi_rdata(30) <= \\; + s_axi_rdata(29) <= \\; + s_axi_rdata(28) <= \\; + s_axi_rdata(27) <= \\; + s_axi_rdata(26) <= \\; + s_axi_rdata(25) <= \\; + s_axi_rdata(24) <= \\; + s_axi_rdata(23) <= \\; + s_axi_rdata(22) <= \\; + s_axi_rdata(21) <= \\; + s_axi_rdata(20) <= \\; + s_axi_rdata(19) <= \\; + s_axi_rdata(18) <= \\; + s_axi_rdata(17) <= \\; + s_axi_rdata(16) <= \\; + s_axi_rdata(15) <= \\; + s_axi_rdata(14) <= \\; + s_axi_rdata(13) <= \\; + s_axi_rdata(12) <= \\; + s_axi_rdata(11) <= \\; + s_axi_rdata(10) <= \\; + s_axi_rdata(9) <= \\; + s_axi_rdata(8) <= \\; + s_axi_rdata(7) <= \\; + s_axi_rdata(6) <= \\; + s_axi_rdata(5) <= \\; + s_axi_rdata(4) <= \\; + s_axi_rdata(3) <= \\; + s_axi_rdata(2) <= \\; + s_axi_rdata(1 downto 0) <= \^s_axi_rdata\(1 downto 0); + s_axi_rresp(1) <= \\; + s_axi_rresp(0) <= \\; + s_axi_wready <= \^s_axi_wready\; +AXI_LITE_IPIF_I: entity work.Arty_Z7_20_axi_gpio_0_0_axi_lite_ipif + port map ( + Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\, + D(2) => p_0_out(0), + D(1) => p_0_out(30), + D(0) => ip2bus_data_i(31), + \Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[31]\ => AXI_LITE_IPIF_I_n_26, + \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[31]\ => AXI_LITE_IPIF_I_n_27, + \Dual.gpio2_Data_Out_reg[0]\ => AXI_LITE_IPIF_I_n_24, + \Dual.gpio2_OE_reg[0]\ => AXI_LITE_IPIF_I_n_21, + \Dual.gpio_Data_Out_reg[0]\ => AXI_LITE_IPIF_I_n_23, + \Dual.gpio_OE_reg[0]\ => AXI_LITE_IPIF_I_n_22, + \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ => \INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_1\, + \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\ => AXI_LITE_IPIF_I_n_18, + GPIO2_DBus_i(0) => GPIO2_DBus_i(31), + GPIO_DBus_i(0) => GPIO_DBus_i(31), + GPIO_xferAck_i => GPIO_xferAck_i, + \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => AXI_LITE_IPIF_I_n_15, + Q(2) => ip2bus_data_i_D1(0), + Q(1) => ip2bus_data_i_D1(30), + Q(0) => ip2bus_data_i_D1(31), + bus2ip_cs(0) => bus2ip_cs(1), + bus2ip_rnw => bus2ip_rnw, + gpio2_Data_In => gpio2_Data_In, + gpio2_io_o(0) => \^gpio2_io_o\(0), + gpio2_io_t(0) => \^gpio2_io_t\(0), + gpio_Data_In => gpio_Data_In, + gpio_io_o(0) => \^gpio_io_o\(0), + gpio_io_t(0) => \^gpio_io_t\(0), + gpio_xferAck_Reg => gpio_xferAck_Reg, + interrupt_wrce_strb => interrupt_wrce_strb, + intr2bus_rdack0 => intr2bus_rdack0, + intr2bus_wrack => intr2bus_wrack, + intr_rd_ce_or_reduce => intr_rd_ce_or_reduce, + intr_wr_ce_or_reduce => intr_wr_ce_or_reduce, + ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1, + ip2Bus_WrAck_intr_reg_hole => ip2Bus_WrAck_intr_reg_hole, + ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1, + ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1, + ip2bus_wrack_i => ip2bus_wrack_i, + ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1, + \ip_irpt_enable_reg_reg[0]\ => \INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_8\, + \ip_irpt_enable_reg_reg[1]\ => \INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_9\, + ipif_glbl_irpt_enable_reg => ipif_glbl_irpt_enable_reg, + ipif_glbl_irpt_enable_reg_reg => AXI_LITE_IPIF_I_n_25, + irpt_rdack => irpt_rdack, + irpt_rdack_d1 => irpt_rdack_d1, + irpt_wrack => irpt_wrack, + irpt_wrack_d1 => irpt_wrack_d1, + p_1_in => p_1_in, + p_3_out => p_3_out, + p_6_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_6_in\, + rst => \I_SLAVE_ATTACHMENT/rst\, + s_axi_aclk => s_axi_aclk, + s_axi_araddr(6 downto 0) => s_axi_araddr(8 downto 2), + s_axi_aresetn => s_axi_aresetn, + s_axi_arready => s_axi_arready, + s_axi_arvalid => s_axi_arvalid, + s_axi_awaddr(6 downto 0) => s_axi_awaddr(8 downto 2), + s_axi_awvalid => s_axi_awvalid, + s_axi_bready => s_axi_bready, + s_axi_bvalid => s_axi_bvalid, + s_axi_rdata(2) => \^s_axi_rdata\(31), + s_axi_rdata(1 downto 0) => \^s_axi_rdata\(1 downto 0), + s_axi_rready => s_axi_rready, + s_axi_rvalid => s_axi_rvalid, + s_axi_wdata(1) => s_axi_wdata(31), + s_axi_wdata(0) => s_axi_wdata(0), + s_axi_wready => \^s_axi_wready\, + s_axi_wvalid => s_axi_wvalid + ); +GND: unisim.vcomponents.GND + port map ( + G => \\ + ); +\INTR_CTRLR_GEN.INTERRUPT_CONTROL_I\: entity work.Arty_Z7_20_axi_gpio_0_0_interrupt_control + port map ( + Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\, + \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\ => AXI_LITE_IPIF_I_n_25, + \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ => \INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_1\, + GPIO2_intr => GPIO2_intr, + GPIO_intr => GPIO_intr, + IP2INTC_Irpt_i => IP2INTC_Irpt_i, + interrupt_wrce_strb => interrupt_wrce_strb, + intr2bus_rdack => intr2bus_rdack, + intr2bus_rdack0 => intr2bus_rdack0, + intr2bus_wrack => intr2bus_wrack, + \ip_irpt_enable_reg_reg[0]_0\ => \INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_8\, + \ip_irpt_enable_reg_reg[1]_0\ => \INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_9\, + ipif_glbl_irpt_enable_reg => ipif_glbl_irpt_enable_reg, + irpt_rdack => irpt_rdack, + irpt_rdack_d1 => irpt_rdack_d1, + irpt_wrack => irpt_wrack, + irpt_wrack_d1 => irpt_wrack_d1, + irpt_wrack_d1_reg_0 => AXI_LITE_IPIF_I_n_18, + p_1_in => p_1_in, + p_6_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_6_in\, + rst => \I_SLAVE_ATTACHMENT/rst\, + s_axi_aclk => s_axi_aclk, + s_axi_wdata(1 downto 0) => s_axi_wdata(1 downto 0) + ); +\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_reg\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => intr_rd_ce_or_reduce, + Q => ip2Bus_RdAck_intr_reg_hole_d1, + R => \I_SLAVE_ATTACHMENT/rst\ + ); +\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => p_3_out, + Q => ip2Bus_RdAck_intr_reg_hole, + R => \I_SLAVE_ATTACHMENT/rst\ + ); +\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_reg\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => intr_wr_ce_or_reduce, + Q => ip2Bus_WrAck_intr_reg_hole_d1, + R => \I_SLAVE_ATTACHMENT/rst\ + ); +\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => AXI_LITE_IPIF_I_n_15, + Q => ip2Bus_WrAck_intr_reg_hole, + R => \I_SLAVE_ATTACHMENT/rst\ + ); +\INTR_CTRLR_GEN.ip2intc_irpt_reg\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => IP2INTC_Irpt_i, + Q => ip2intc_irpt, + R => \I_SLAVE_ATTACHMENT/rst\ + ); +bus2ip_reset_i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => s_axi_aresetn, + O => bus2ip_reset_i_1_n_0 + ); +bus2ip_reset_reg: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => bus2ip_reset_i_1_n_0, + Q => \I_SLAVE_ATTACHMENT/rst\, + R => '0' + ); +gpio_core_1: entity work.Arty_Z7_20_axi_gpio_0_0_GPIO_Core + port map ( + \Dual.gpio2_Data_In_reg[0]_0\ => AXI_LITE_IPIF_I_n_26, + \Dual.gpio_Data_In_reg[0]_0\ => AXI_LITE_IPIF_I_n_27, + GPIO2_DBus_i(0) => GPIO2_DBus_i(31), + GPIO2_intr => GPIO2_intr, + GPIO_DBus_i(0) => GPIO_DBus_i(31), + GPIO_intr => GPIO_intr, + GPIO_xferAck_i => GPIO_xferAck_i, + bus2ip_cs(0) => bus2ip_cs(1), + bus2ip_rnw => bus2ip_rnw, + bus2ip_rnw_i_reg => AXI_LITE_IPIF_I_n_21, + bus2ip_rnw_i_reg_0 => AXI_LITE_IPIF_I_n_22, + bus2ip_rnw_i_reg_1 => AXI_LITE_IPIF_I_n_23, + bus2ip_rnw_i_reg_2 => AXI_LITE_IPIF_I_n_24, + gpio2_Data_In => gpio2_Data_In, + gpio2_io_i(0) => gpio2_io_i(0), + gpio2_io_o(0) => \^gpio2_io_o\(0), + gpio2_io_t(0) => \^gpio2_io_t\(0), + gpio_Data_In => gpio_Data_In, + gpio_io_i(0) => gpio_io_i(0), + gpio_io_o(0) => \^gpio_io_o\(0), + gpio_io_t(0) => \^gpio_io_t\(0), + gpio_xferAck_Reg => gpio_xferAck_Reg, + intr2bus_rdack => intr2bus_rdack, + ip2Bus_RdAck_intr_reg_hole => ip2Bus_RdAck_intr_reg_hole, + ip2bus_rdack_i => ip2bus_rdack_i, + rst => \I_SLAVE_ATTACHMENT/rst\, + s_axi_aclk => s_axi_aclk + ); +\ip2bus_data_i_D1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => p_0_out(0), + Q => ip2bus_data_i_D1(0), + R => \I_SLAVE_ATTACHMENT/rst\ + ); +\ip2bus_data_i_D1_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => p_0_out(30), + Q => ip2bus_data_i_D1(30), + R => \I_SLAVE_ATTACHMENT/rst\ + ); +\ip2bus_data_i_D1_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_data_i(31), + Q => ip2bus_data_i_D1(31), + R => \I_SLAVE_ATTACHMENT/rst\ + ); +ip2bus_rdack_i_D1_reg: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_rdack_i, + Q => ip2bus_rdack_i_D1, + R => \I_SLAVE_ATTACHMENT/rst\ + ); +ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => ip2bus_wrack_i, + Q => ip2bus_wrack_i_D1, + R => \I_SLAVE_ATTACHMENT/rst\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_gpio_0_0 is + port ( + s_axi_aclk : in STD_LOGIC; + s_axi_aresetn : in STD_LOGIC; + s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_arvalid : in STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rvalid : out STD_LOGIC; + s_axi_rready : in STD_LOGIC; + ip2intc_irpt : out STD_LOGIC; + gpio_io_o : out STD_LOGIC_VECTOR ( 0 to 0 ); + gpio2_io_i : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of Arty_Z7_20_axi_gpio_0_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of Arty_Z7_20_axi_gpio_0_0 : entity is "Arty_Z7_20_axi_gpio_0_0,axi_gpio,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of Arty_Z7_20_axi_gpio_0_0 : entity is "yes"; + attribute x_core_info : string; + attribute x_core_info of Arty_Z7_20_axi_gpio_0_0 : entity is "axi_gpio,Vivado 2016.4"; +end Arty_Z7_20_axi_gpio_0_0; + +architecture STRUCTURE of Arty_Z7_20_axi_gpio_0_0 is + signal NLW_U0_gpio2_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_U0_gpio2_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_U0_gpio_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + attribute C_ALL_INPUTS : integer; + attribute C_ALL_INPUTS of U0 : label is 0; + attribute C_ALL_INPUTS_2 : integer; + attribute C_ALL_INPUTS_2 of U0 : label is 1; + attribute C_ALL_OUTPUTS : integer; + attribute C_ALL_OUTPUTS of U0 : label is 1; + attribute C_ALL_OUTPUTS_2 : integer; + attribute C_ALL_OUTPUTS_2 of U0 : label is 0; + attribute C_DOUT_DEFAULT : integer; + attribute C_DOUT_DEFAULT of U0 : label is 0; + attribute C_DOUT_DEFAULT_2 : integer; + attribute C_DOUT_DEFAULT_2 of U0 : label is 0; + attribute C_FAMILY : string; + attribute C_FAMILY of U0 : label is "zynq"; + attribute C_GPIO2_WIDTH : integer; + attribute C_GPIO2_WIDTH of U0 : label is 1; + attribute C_GPIO_WIDTH : integer; + attribute C_GPIO_WIDTH of U0 : label is 1; + attribute C_INTERRUPT_PRESENT : integer; + attribute C_INTERRUPT_PRESENT of U0 : label is 1; + attribute C_IS_DUAL : integer; + attribute C_IS_DUAL of U0 : label is 1; + attribute C_S_AXI_ADDR_WIDTH : integer; + attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9; + attribute C_S_AXI_DATA_WIDTH : integer; + attribute C_S_AXI_DATA_WIDTH of U0 : label is 32; + attribute C_TRI_DEFAULT : integer; + attribute C_TRI_DEFAULT of U0 : label is -1; + attribute C_TRI_DEFAULT_2 : integer; + attribute C_TRI_DEFAULT_2 of U0 : label is -1; + attribute downgradeipidentifiedwarnings of U0 : label is "yes"; + attribute ip_group : string; + attribute ip_group of U0 : label is "LOGICORE"; +begin +U0: entity work.Arty_Z7_20_axi_gpio_0_0_axi_gpio + port map ( + gpio2_io_i(0) => gpio2_io_i(0), + gpio2_io_o(0) => NLW_U0_gpio2_io_o_UNCONNECTED(0), + gpio2_io_t(0) => NLW_U0_gpio2_io_t_UNCONNECTED(0), + gpio_io_i(0) => '0', + gpio_io_o(0) => gpio_io_o(0), + gpio_io_t(0) => NLW_U0_gpio_io_t_UNCONNECTED(0), + ip2intc_irpt => ip2intc_irpt, + s_axi_aclk => s_axi_aclk, + s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0), + s_axi_aresetn => s_axi_aresetn, + s_axi_arready => s_axi_arready, + s_axi_arvalid => s_axi_arvalid, + s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0), + s_axi_awready => s_axi_awready, + s_axi_awvalid => s_axi_awvalid, + s_axi_bready => s_axi_bready, + s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0), + s_axi_bvalid => s_axi_bvalid, + s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), + s_axi_rready => s_axi_rready, + s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0), + s_axi_rvalid => s_axi_rvalid, + s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), + s_axi_wready => s_axi_wready, + s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0), + s_axi_wvalid => s_axi_wvalid + ); +end STRUCTURE; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0_stub.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0_stub.v new file mode 100644 index 0000000..728f5ea --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0_stub.v @@ -0,0 +1,44 @@ +// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +// Date : Sat Mar 04 18:57:35 2017 +// Host : WK73 running 64-bit Service Pack 1 (build 7601) +// Command : write_verilog -force -mode synth_stub +// c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0_stub.v +// Design : Arty_Z7_20_axi_gpio_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg400-1 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "axi_gpio,Vivado 2016.4" *) +module Arty_Z7_20_axi_gpio_0_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr, + s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, + s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready, + s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, ip2intc_irpt, gpio_io_o, gpio2_io_i) +/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,ip2intc_irpt,gpio_io_o[0:0],gpio2_io_i[0:0]" */; + input s_axi_aclk; + input s_axi_aresetn; + input [8:0]s_axi_awaddr; + input s_axi_awvalid; + output s_axi_awready; + input [31:0]s_axi_wdata; + input [3:0]s_axi_wstrb; + input s_axi_wvalid; + output s_axi_wready; + output [1:0]s_axi_bresp; + output s_axi_bvalid; + input s_axi_bready; + input [8:0]s_axi_araddr; + input s_axi_arvalid; + output s_axi_arready; + output [31:0]s_axi_rdata; + output [1:0]s_axi_rresp; + output s_axi_rvalid; + input s_axi_rready; + output ip2intc_irpt; + output [0:0]gpio_io_o; + input [0:0]gpio2_io_i; +endmodule diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0_stub.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0_stub.vhdl new file mode 100644 index 0000000..1453f25 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0_stub.vhdl @@ -0,0 +1,51 @@ +-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +-- Date : Sat Mar 04 18:57:36 2017 +-- Host : WK73 running 64-bit Service Pack 1 (build 7601) +-- Command : write_vhdl -force -mode synth_stub +-- c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/Arty_Z7_20_axi_gpio_0_0_stub.vhdl +-- Design : Arty_Z7_20_axi_gpio_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg400-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Arty_Z7_20_axi_gpio_0_0 is + Port ( + s_axi_aclk : in STD_LOGIC; + s_axi_aresetn : in STD_LOGIC; + s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_arvalid : in STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rvalid : out STD_LOGIC; + s_axi_rready : in STD_LOGIC; + ip2intc_irpt : out STD_LOGIC; + gpio_io_o : out STD_LOGIC_VECTOR ( 0 to 0 ); + gpio2_io_i : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + +end Arty_Z7_20_axi_gpio_0_0; + +architecture stub of Arty_Z7_20_axi_gpio_0_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,ip2intc_irpt,gpio_io_o[0:0],gpio2_io_i[0:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2016.4"; +begin +end; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/sim/Arty_Z7_20_axi_gpio_0_0.vhd b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/sim/Arty_Z7_20_axi_gpio_0_0.vhd new file mode 100644 index 0000000..099d772 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/sim/Arty_Z7_20_axi_gpio_0_0.vhd @@ -0,0 +1,203 @@ +-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axi_gpio:2.0 +-- IP Revision: 13 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY axi_gpio_v2_0_13; +USE axi_gpio_v2_0_13.axi_gpio; + +ENTITY Arty_Z7_20_axi_gpio_0_0 IS + PORT ( + s_axi_aclk : IN STD_LOGIC; + s_axi_aresetn : IN STD_LOGIC; + s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_awvalid : IN STD_LOGIC; + s_axi_awready : OUT STD_LOGIC; + s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + s_axi_wvalid : IN STD_LOGIC; + s_axi_wready : OUT STD_LOGIC; + s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_bvalid : OUT STD_LOGIC; + s_axi_bready : IN STD_LOGIC; + s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_arvalid : IN STD_LOGIC; + s_axi_arready : OUT STD_LOGIC; + s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_rvalid : OUT STD_LOGIC; + s_axi_rready : IN STD_LOGIC; + ip2intc_irpt : OUT STD_LOGIC; + gpio_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gpio2_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0) + ); +END Arty_Z7_20_axi_gpio_0_0; + +ARCHITECTURE Arty_Z7_20_axi_gpio_0_0_arch OF Arty_Z7_20_axi_gpio_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF Arty_Z7_20_axi_gpio_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT axi_gpio IS + GENERIC ( + C_FAMILY : STRING; + C_S_AXI_ADDR_WIDTH : INTEGER; + C_S_AXI_DATA_WIDTH : INTEGER; + C_GPIO_WIDTH : INTEGER; + C_GPIO2_WIDTH : INTEGER; + C_ALL_INPUTS : INTEGER; + C_ALL_INPUTS_2 : INTEGER; + C_ALL_OUTPUTS : INTEGER; + C_ALL_OUTPUTS_2 : INTEGER; + C_INTERRUPT_PRESENT : INTEGER; + C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0); + C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0); + C_IS_DUAL : INTEGER; + C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + PORT ( + s_axi_aclk : IN STD_LOGIC; + s_axi_aresetn : IN STD_LOGIC; + s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_awvalid : IN STD_LOGIC; + s_axi_awready : OUT STD_LOGIC; + s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + s_axi_wvalid : IN STD_LOGIC; + s_axi_wready : OUT STD_LOGIC; + s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_bvalid : OUT STD_LOGIC; + s_axi_bready : IN STD_LOGIC; + s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_arvalid : IN STD_LOGIC; + s_axi_arready : OUT STD_LOGIC; + s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_rvalid : OUT STD_LOGIC; + s_axi_rready : IN STD_LOGIC; + ip2intc_irpt : OUT STD_LOGIC; + gpio_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + gpio_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gpio_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gpio2_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + gpio2_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gpio2_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); + END COMPONENT axi_gpio; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; + ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT"; + ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O"; + ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I"; +BEGIN + U0 : axi_gpio + GENERIC MAP ( + C_FAMILY => "zynq", + C_S_AXI_ADDR_WIDTH => 9, + C_S_AXI_DATA_WIDTH => 32, + C_GPIO_WIDTH => 1, + C_GPIO2_WIDTH => 1, + C_ALL_INPUTS => 0, + C_ALL_INPUTS_2 => 1, + C_ALL_OUTPUTS => 1, + C_ALL_OUTPUTS_2 => 0, + C_INTERRUPT_PRESENT => 1, + C_DOUT_DEFAULT => X"00000000", + C_TRI_DEFAULT => X"FFFFFFFF", + C_IS_DUAL => 1, + C_DOUT_DEFAULT_2 => X"00000000", + C_TRI_DEFAULT_2 => X"FFFFFFFF" + ) + PORT MAP ( + s_axi_aclk => s_axi_aclk, + s_axi_aresetn => s_axi_aresetn, + s_axi_awaddr => s_axi_awaddr, + s_axi_awvalid => s_axi_awvalid, + s_axi_awready => s_axi_awready, + s_axi_wdata => s_axi_wdata, + s_axi_wstrb => s_axi_wstrb, + s_axi_wvalid => s_axi_wvalid, + s_axi_wready => s_axi_wready, + s_axi_bresp => s_axi_bresp, + s_axi_bvalid => s_axi_bvalid, + s_axi_bready => s_axi_bready, + s_axi_araddr => s_axi_araddr, + s_axi_arvalid => s_axi_arvalid, + s_axi_arready => s_axi_arready, + s_axi_rdata => s_axi_rdata, + s_axi_rresp => s_axi_rresp, + s_axi_rvalid => s_axi_rvalid, + s_axi_rready => s_axi_rready, + ip2intc_irpt => ip2intc_irpt, + gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), + gpio_io_o => gpio_io_o, + gpio2_io_i => gpio2_io_i + ); +END Arty_Z7_20_axi_gpio_0_0_arch; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/synth/Arty_Z7_20_axi_gpio_0_0.vhd b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/synth/Arty_Z7_20_axi_gpio_0_0.vhd new file mode 100644 index 0000000..5533aff --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_0_0/synth/Arty_Z7_20_axi_gpio_0_0.vhd @@ -0,0 +1,209 @@ +-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:axi_gpio:2.0 +-- IP Revision: 13 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY axi_gpio_v2_0_13; +USE axi_gpio_v2_0_13.axi_gpio; + +ENTITY Arty_Z7_20_axi_gpio_0_0 IS + PORT ( + s_axi_aclk : IN STD_LOGIC; + s_axi_aresetn : IN STD_LOGIC; + s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_awvalid : IN STD_LOGIC; + s_axi_awready : OUT STD_LOGIC; + s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + s_axi_wvalid : IN STD_LOGIC; + s_axi_wready : OUT STD_LOGIC; + s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_bvalid : OUT STD_LOGIC; + s_axi_bready : IN STD_LOGIC; + s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_arvalid : IN STD_LOGIC; + s_axi_arready : OUT STD_LOGIC; + s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_rvalid : OUT STD_LOGIC; + s_axi_rready : IN STD_LOGIC; + ip2intc_irpt : OUT STD_LOGIC; + gpio_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gpio2_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0) + ); +END Arty_Z7_20_axi_gpio_0_0; + +ARCHITECTURE Arty_Z7_20_axi_gpio_0_0_arch OF Arty_Z7_20_axi_gpio_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF Arty_Z7_20_axi_gpio_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT axi_gpio IS + GENERIC ( + C_FAMILY : STRING; + C_S_AXI_ADDR_WIDTH : INTEGER; + C_S_AXI_DATA_WIDTH : INTEGER; + C_GPIO_WIDTH : INTEGER; + C_GPIO2_WIDTH : INTEGER; + C_ALL_INPUTS : INTEGER; + C_ALL_INPUTS_2 : INTEGER; + C_ALL_OUTPUTS : INTEGER; + C_ALL_OUTPUTS_2 : INTEGER; + C_INTERRUPT_PRESENT : INTEGER; + C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0); + C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0); + C_IS_DUAL : INTEGER; + C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + PORT ( + s_axi_aclk : IN STD_LOGIC; + s_axi_aresetn : IN STD_LOGIC; + s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_awvalid : IN STD_LOGIC; + s_axi_awready : OUT STD_LOGIC; + s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + s_axi_wvalid : IN STD_LOGIC; + s_axi_wready : OUT STD_LOGIC; + s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_bvalid : OUT STD_LOGIC; + s_axi_bready : IN STD_LOGIC; + s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_arvalid : IN STD_LOGIC; + s_axi_arready : OUT STD_LOGIC; + s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_rvalid : OUT STD_LOGIC; + s_axi_rready : IN STD_LOGIC; + ip2intc_irpt : OUT STD_LOGIC; + gpio_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + gpio_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gpio_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gpio2_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + gpio2_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + gpio2_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); + END COMPONENT axi_gpio; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF Arty_Z7_20_axi_gpio_0_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2016.4"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF Arty_Z7_20_axi_gpio_0_0_arch : ARCHITECTURE IS "Arty_Z7_20_axi_gpio_0_0,axi_gpio,{}"; + ATTRIBUTE CORE_GENERATION_INFO : STRING; + ATTRIBUTE CORE_GENERATION_INFO OF Arty_Z7_20_axi_gpio_0_0_arch: ARCHITECTURE IS "Arty_Z7_20_axi_gpio_0_0,axi_gpio,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=13,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=1,C_GPIO2_WIDTH=1,C_ALL_INPUTS=0,C_ALL_INPUTS_2=1,C_ALL_OUTPUTS=1,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=1,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=1,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; + ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT"; + ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O"; + ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I"; +BEGIN + U0 : axi_gpio + GENERIC MAP ( + C_FAMILY => "zynq", + C_S_AXI_ADDR_WIDTH => 9, + C_S_AXI_DATA_WIDTH => 32, + C_GPIO_WIDTH => 1, + C_GPIO2_WIDTH => 1, + C_ALL_INPUTS => 0, + C_ALL_INPUTS_2 => 1, + C_ALL_OUTPUTS => 1, + C_ALL_OUTPUTS_2 => 0, + C_INTERRUPT_PRESENT => 1, + C_DOUT_DEFAULT => X"00000000", + C_TRI_DEFAULT => X"FFFFFFFF", + C_IS_DUAL => 1, + C_DOUT_DEFAULT_2 => X"00000000", + C_TRI_DEFAULT_2 => X"FFFFFFFF" + ) + PORT MAP ( + s_axi_aclk => s_axi_aclk, + s_axi_aresetn => s_axi_aresetn, + s_axi_awaddr => s_axi_awaddr, + s_axi_awvalid => s_axi_awvalid, + s_axi_awready => s_axi_awready, + s_axi_wdata => s_axi_wdata, + s_axi_wstrb => s_axi_wstrb, + s_axi_wvalid => s_axi_wvalid, + s_axi_wready => s_axi_wready, + s_axi_bresp => s_axi_bresp, + s_axi_bvalid => s_axi_bvalid, + s_axi_bready => s_axi_bready, + s_axi_araddr => s_axi_araddr, + s_axi_arvalid => s_axi_arvalid, + s_axi_arready => s_axi_arready, + s_axi_rdata => s_axi_rdata, + s_axi_rresp => s_axi_rresp, + s_axi_rvalid => s_axi_rvalid, + s_axi_rready => s_axi_rready, + ip2intc_irpt => ip2intc_irpt, + gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), + gpio_io_o => gpio_io_o, + gpio2_io_i => gpio2_io_i + ); +END Arty_Z7_20_axi_gpio_0_0_arch; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0.dcp b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0.dcp index dc21573..0344541 100644 Binary files a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0.dcp and b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0.dcp differ diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0.xci b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0.xci index 023390d..a7539cf 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0.xci +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0.xci @@ -1,136 +1,174 @@ - - xilinx.com - xci - unknown - 1.0 - - - Arty_Z7_20_axi_gpio_shield_1_0 - - - 1 - 9 - 0 - 0 - 0 - Arty_Z7_20_processing_system7_0_0_FCLK_CLK0 - 32 - 100000000 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 1 - 2 - 1 - 2 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - Arty_Z7_20_processing_system7_0_0_FCLK_CLK0 - 100000000 - 0.000 - 0 - 0 - 0 - 0 - 0x00000000 - 0x00000000 - zynq - 32 - 14 - 1 - 0 - 0xFFFFFFFF - 0xFFFFFFFF - 0 - 0 - 0 - 0 - 0x00000000 - 0x00000000 - 32 - 14 - 1 - 0 - 0xFFFFFFFF - 0xFFFFFFFF - Arty_Z7_20_axi_gpio_shield_1_0 - Custom - shield_dp0_dp13 - false - zynq - digilentinc.com:arty-z7-20:part0:1.0 - xc7z020 - clg400 - VHDL - - MIXED - -1 - - TRUE - TRUE - IP_Integrator - 13 - TRUE - . - - ../../ipshared - 2016.4 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + xilinx.com + xci + unknown + 1.0 + + + Arty_Z7_20_axi_gpio_shield_1_0 + + + 1 + 9 + 0 + 0 + 0 + Arty_Z7_20_processing_system7_0_0_FCLK_CLK0 + 32 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 2 + 1 + 2 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + Arty_Z7_20_processing_system7_0_0_FCLK_CLK0 + 100000000 + 0.000 + 0 + 0 + 0 + 0 + 0x00000000 + 0x00000000 + zynq + 32 + 14 + 0 + 0 + 0xFFFFFFFF + 0xFFFFFFFF + 0 + 0 + 0 + 0 + 0x00000000 + 0x00000000 + 32 + 14 + 0 + 0 + 0xFFFFFFFF + 0xFFFFFFFF + Arty_Z7_20_axi_gpio_shield_1_0 + Custom + shield_dp0_dp13 + false + zynq + digilentinc.com:arty-z7-20:part0:1.0 + xc7z020 + clg400 + VHDL + + MIXED + -1 + + TRUE + TRUE + IP_Integrator + 13 + TRUE + . + + ../../ipshared + 2016.4 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0.xml b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0.xml index e568606..8eb92e2 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0.xml +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0.xml @@ -365,7 +365,7 @@ - true + false @@ -767,7 +767,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output boundaryCRC - 13d6007c + 6f5c945e boundaryCRCversion @@ -775,7 +775,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output customizationCRC - 20d0d5e8 + 19eab8e4 customizationCRCversion @@ -794,11 +794,11 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output GENtimestamp - Fri Feb 24 23:57:47 UTC 2017 + Sun Mar 05 02:51:00 UTC 2017 boundaryCRC - 13d6007c + 6f5c945e boundaryCRCversion @@ -806,7 +806,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output customizationCRC - 20d0d5e8 + 19eab8e4 customizationCRCversion @@ -838,7 +838,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output boundaryCRC - 13d6007c + 6f5c945e boundaryCRCversion @@ -846,7 +846,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output customizationCRC - bb5be442 + 94d1e327 customizationCRCversion @@ -865,11 +865,11 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output GENtimestamp - Fri Feb 24 23:57:47 UTC 2017 + Sun Mar 05 02:51:00 UTC 2017 boundaryCRC - 13d6007c + 6f5c945e boundaryCRCversion @@ -877,7 +877,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output customizationCRC - bb5be442 + 94d1e327 customizationCRCversion @@ -895,11 +895,11 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output GENtimestamp - Fri Feb 24 23:57:47 UTC 2017 + Sun Mar 05 02:51:00 UTC 2017 boundaryCRC - 13d6007c + 6f5c945e boundaryCRCversion @@ -907,7 +907,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output customizationCRC - 20d0d5e8 + 19eab8e4 customizationCRCversion @@ -925,11 +925,11 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output GENtimestamp - Fri Feb 24 23:59:44 UTC 2017 + Sun Mar 05 02:53:03 UTC 2017 boundaryCRC - 13d6007c + 6f5c945e boundaryCRCversion @@ -937,7 +937,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output customizationCRC - 20d0d5e8 + 19eab8e4 customizationCRCversion @@ -1270,7 +1270,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output - true + false @@ -1474,7 +1474,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output C_INTERRUPT_PRESENT Enable Interrupt - 1 + 0 C_DOUT_DEFAULT @@ -1818,7 +1818,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output C_INTERRUPT_PRESENT Enable Interrupt - 1 + 0 diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0_sim_netlist.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0_sim_netlist.v index 64673e7..d7b3acd 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0_sim_netlist.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -// Date : Fri Feb 24 15:59:43 2017 +// Date : Sat Mar 04 18:53:03 2017 // Host : WK73 running 64-bit Service Pack 1 (build 7601) // Command : write_verilog -force -mode funcsim -// c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0_sim_netlist.v +// C:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0_sim_netlist.v // Design : Arty_Z7_20_axi_gpio_shield_1_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -34,7 +34,6 @@ module Arty_Z7_20_axi_gpio_shield_1_0 s_axi_rresp, s_axi_rvalid, s_axi_rready, - ip2intc_irpt, gpio_io_i, gpio_io_o, gpio_io_t); @@ -57,7 +56,6 @@ module Arty_Z7_20_axi_gpio_shield_1_0 (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp; (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid; (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready; - (* x_interface_info = "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT" *) output ip2intc_irpt; (* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_I" *) input [13:0]gpio_io_i; (* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_O" *) output [13:0]gpio_io_o; (* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_T" *) output [13:0]gpio_io_t; @@ -65,7 +63,6 @@ module Arty_Z7_20_axi_gpio_shield_1_0 wire [13:0]gpio_io_i; wire [13:0]gpio_io_o; wire [13:0]gpio_io_t; - wire ip2intc_irpt; wire s_axi_aclk; wire [8:0]s_axi_araddr; wire s_axi_aresetn; @@ -85,6 +82,7 @@ module Arty_Z7_20_axi_gpio_shield_1_0 wire s_axi_wready; wire [3:0]s_axi_wstrb; wire s_axi_wvalid; + wire NLW_U0_ip2intc_irpt_UNCONNECTED; wire [31:0]NLW_U0_gpio2_io_o_UNCONNECTED; wire [31:0]NLW_U0_gpio2_io_t_UNCONNECTED; @@ -97,7 +95,7 @@ module Arty_Z7_20_axi_gpio_shield_1_0 (* C_FAMILY = "zynq" *) (* C_GPIO2_WIDTH = "32" *) (* C_GPIO_WIDTH = "14" *) - (* C_INTERRUPT_PRESENT = "1" *) + (* C_INTERRUPT_PRESENT = "0" *) (* C_IS_DUAL = "0" *) (* C_S_AXI_ADDR_WIDTH = "9" *) (* C_S_AXI_DATA_WIDTH = "32" *) @@ -112,7 +110,7 @@ module Arty_Z7_20_axi_gpio_shield_1_0 .gpio_io_i(gpio_io_i), .gpio_io_o(gpio_io_o), .gpio_io_t(gpio_io_t), - .ip2intc_irpt(ip2intc_irpt), + .ip2intc_irpt(NLW_U0_ip2intc_irpt_UNCONNECTED), .s_axi_aclk(s_axi_aclk), .s_axi_araddr(s_axi_araddr), .s_axi_aresetn(s_axi_aresetn), @@ -136,323 +134,191 @@ endmodule (* ORIG_REF_NAME = "GPIO_Core" *) module Arty_Z7_20_axi_gpio_shield_1_0_GPIO_Core - (ip2bus_data, + (D, GPIO_xferAck_i, gpio_xferAck_Reg, - GPIO_intr, - Q, + ip2bus_rdack_i, + ip2bus_wrack_i_D1_reg, gpio_io_o, gpio_io_t, - Read_Reg_Rst, - \Not_Dual.gpio_OE_reg[13]_0 , + Q, + bus2ip_rnw_i_reg, + \Not_Dual.gpio_Data_In_reg[13]_0 , s_axi_aclk, - \Not_Dual.gpio_OE_reg[12]_0 , - \Not_Dual.gpio_OE_reg[11]_0 , - \Not_Dual.gpio_OE_reg[10]_0 , - \Not_Dual.gpio_OE_reg[9]_0 , - \Not_Dual.gpio_OE_reg[8]_0 , - \Not_Dual.gpio_OE_reg[7]_0 , - \Not_Dual.gpio_OE_reg[6]_0 , - \Not_Dual.gpio_OE_reg[5]_0 , - \Not_Dual.gpio_OE_reg[4]_0 , - \Not_Dual.gpio_OE_reg[3]_0 , - \Not_Dual.gpio_OE_reg[2]_0 , - \Not_Dual.gpio_OE_reg[1]_0 , + \Not_Dual.gpio_Data_In_reg[12]_0 , + \Not_Dual.gpio_Data_In_reg[11]_0 , + \Not_Dual.gpio_Data_In_reg[10]_0 , + \Not_Dual.gpio_Data_In_reg[9]_0 , + \Not_Dual.gpio_Data_In_reg[8]_0 , + \Not_Dual.gpio_Data_In_reg[7]_0 , + \Not_Dual.gpio_Data_In_reg[6]_0 , + \Not_Dual.gpio_Data_In_reg[5]_0 , + \Not_Dual.gpio_Data_In_reg[4]_0 , + \Not_Dual.gpio_Data_In_reg[3]_0 , + \Not_Dual.gpio_Data_In_reg[2]_0 , + \Not_Dual.gpio_Data_In_reg[1]_0 , GPIO_DBus_i, - bus2ip_reset, + SS, + bus2ip_rnw, bus2ip_cs, gpio_io_i, E, - D, - bus2ip_rnw_i_reg); - output [13:0]ip2bus_data; + \MEM_DECODE_GEN[0].cs_out_i_reg[0] , + rst_reg); + output [13:0]D; output GPIO_xferAck_i; output gpio_xferAck_Reg; - output GPIO_intr; - output [13:0]Q; + output ip2bus_rdack_i; + output ip2bus_wrack_i_D1_reg; output [13:0]gpio_io_o; output [13:0]gpio_io_t; - input Read_Reg_Rst; - input \Not_Dual.gpio_OE_reg[13]_0 ; + output [13:0]Q; + input bus2ip_rnw_i_reg; + input \Not_Dual.gpio_Data_In_reg[13]_0 ; input s_axi_aclk; - input \Not_Dual.gpio_OE_reg[12]_0 ; - input \Not_Dual.gpio_OE_reg[11]_0 ; - input \Not_Dual.gpio_OE_reg[10]_0 ; - input \Not_Dual.gpio_OE_reg[9]_0 ; - input \Not_Dual.gpio_OE_reg[8]_0 ; - input \Not_Dual.gpio_OE_reg[7]_0 ; - input \Not_Dual.gpio_OE_reg[6]_0 ; - input \Not_Dual.gpio_OE_reg[5]_0 ; - input \Not_Dual.gpio_OE_reg[4]_0 ; - input \Not_Dual.gpio_OE_reg[3]_0 ; - input \Not_Dual.gpio_OE_reg[2]_0 ; - input \Not_Dual.gpio_OE_reg[1]_0 ; + input \Not_Dual.gpio_Data_In_reg[12]_0 ; + input \Not_Dual.gpio_Data_In_reg[11]_0 ; + input \Not_Dual.gpio_Data_In_reg[10]_0 ; + input \Not_Dual.gpio_Data_In_reg[9]_0 ; + input \Not_Dual.gpio_Data_In_reg[8]_0 ; + input \Not_Dual.gpio_Data_In_reg[7]_0 ; + input \Not_Dual.gpio_Data_In_reg[6]_0 ; + input \Not_Dual.gpio_Data_In_reg[5]_0 ; + input \Not_Dual.gpio_Data_In_reg[4]_0 ; + input \Not_Dual.gpio_Data_In_reg[3]_0 ; + input \Not_Dual.gpio_Data_In_reg[2]_0 ; + input \Not_Dual.gpio_Data_In_reg[1]_0 ; input [0:0]GPIO_DBus_i; - input bus2ip_reset; - input [0:0]bus2ip_cs; + input [0:0]SS; + input bus2ip_rnw; + input bus2ip_cs; input [13:0]gpio_io_i; input [0:0]E; - input [13:0]D; - input [0:0]bus2ip_rnw_i_reg; + input [13:0]\MEM_DECODE_GEN[0].cs_out_i_reg[0] ; + input [0:0]rst_reg; wire [13:0]D; wire [0:0]E; wire [0:0]GPIO_DBus_i; - wire GPIO_intr; wire GPIO_xferAck_i; - wire \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0 ; - wire \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3_n_0 ; - wire \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0] ; - wire \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[11] ; - wire \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[13] ; - wire \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1] ; - wire \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[8] ; - wire \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[9] ; - wire \Not_Dual.gpio_OE_reg[10]_0 ; - wire \Not_Dual.gpio_OE_reg[11]_0 ; - wire \Not_Dual.gpio_OE_reg[12]_0 ; - wire \Not_Dual.gpio_OE_reg[13]_0 ; - wire \Not_Dual.gpio_OE_reg[1]_0 ; - wire \Not_Dual.gpio_OE_reg[2]_0 ; - wire \Not_Dual.gpio_OE_reg[3]_0 ; - wire \Not_Dual.gpio_OE_reg[4]_0 ; - wire \Not_Dual.gpio_OE_reg[5]_0 ; - wire \Not_Dual.gpio_OE_reg[6]_0 ; - wire \Not_Dual.gpio_OE_reg[7]_0 ; - wire \Not_Dual.gpio_OE_reg[8]_0 ; - wire \Not_Dual.gpio_OE_reg[9]_0 ; + wire [13:0]\MEM_DECODE_GEN[0].cs_out_i_reg[0] ; + wire \Not_Dual.gpio_Data_In_reg[10]_0 ; + wire \Not_Dual.gpio_Data_In_reg[11]_0 ; + wire \Not_Dual.gpio_Data_In_reg[12]_0 ; + wire \Not_Dual.gpio_Data_In_reg[13]_0 ; + wire \Not_Dual.gpio_Data_In_reg[1]_0 ; + wire \Not_Dual.gpio_Data_In_reg[2]_0 ; + wire \Not_Dual.gpio_Data_In_reg[3]_0 ; + wire \Not_Dual.gpio_Data_In_reg[4]_0 ; + wire \Not_Dual.gpio_Data_In_reg[5]_0 ; + wire \Not_Dual.gpio_Data_In_reg[6]_0 ; + wire \Not_Dual.gpio_Data_In_reg[7]_0 ; + wire \Not_Dual.gpio_Data_In_reg[8]_0 ; + wire \Not_Dual.gpio_Data_In_reg[9]_0 ; wire [13:0]Q; - wire Read_Reg_Rst; - wire [0:0]bus2ip_cs; - wire bus2ip_reset; - wire [0:0]bus2ip_rnw_i_reg; - wire [0:13]gpio_data_in_xor; + wire [0:0]SS; + wire bus2ip_cs; + wire bus2ip_rnw; + wire bus2ip_rnw_i_reg; wire [13:0]gpio_io_i; wire [0:13]gpio_io_i_d2; wire [13:0]gpio_io_o; wire [13:0]gpio_io_t; wire gpio_xferAck_Reg; wire iGPIO_xferAck; - wire [13:0]ip2bus_data; - wire or_ints; - wire p_11_in; - wire p_1_in; - wire p_2_in; - wire p_3_in; - wire p_4_in; - wire p_5_in; - wire p_6_in; - wire p_9_in; + wire ip2bus_rdack_i; + wire ip2bus_wrack_i_D1_reg; + wire [0:0]rst_reg; wire s_axi_aclk; - LUT6 #( - .INIT(64'hFFFFFFFFFFFFFFFE)) - \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_1 - (.I0(\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0 ), - .I1(\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3_n_0 ), - .I2(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[8] ), - .I3(p_6_in), - .I4(p_9_in), - .I5(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[9] ), - .O(or_ints)); - LUT6 #( - .INIT(64'hFFFFFFFFFFFFFFFE)) - \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2 - (.I0(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1] ), - .I1(p_1_in), - .I2(p_4_in), - .I3(p_5_in), - .I4(p_2_in), - .I5(p_3_in), - .O(\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0 )); - LUT4 #( - .INIT(16'hFFFE)) - \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3 - (.I0(p_11_in), - .I1(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[11] ), - .I2(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0] ), - .I3(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[13] ), - .O(\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3_n_0 )); - FDRE \Not_Dual.GEN_INTERRUPT.GPIO_intr_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(or_ints), - .Q(GPIO_intr), - .R(bus2ip_reset)); - FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[0] - (.C(s_axi_aclk), - .CE(1'b1), - .D(gpio_data_in_xor[0]), - .Q(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0] ), - .R(bus2ip_reset)); - FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[10] - (.C(s_axi_aclk), - .CE(1'b1), - .D(gpio_data_in_xor[10]), - .Q(p_9_in), - .R(bus2ip_reset)); - FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[11] - (.C(s_axi_aclk), - .CE(1'b1), - .D(gpio_data_in_xor[11]), - .Q(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[11] ), - .R(bus2ip_reset)); - FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[12] - (.C(s_axi_aclk), - .CE(1'b1), - .D(gpio_data_in_xor[12]), - .Q(p_11_in), - .R(bus2ip_reset)); - FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[13] - (.C(s_axi_aclk), - .CE(1'b1), - .D(gpio_data_in_xor[13]), - .Q(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[13] ), - .R(bus2ip_reset)); - FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[1] - (.C(s_axi_aclk), - .CE(1'b1), - .D(gpio_data_in_xor[1]), - .Q(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1] ), - .R(bus2ip_reset)); - FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[2] - (.C(s_axi_aclk), - .CE(1'b1), - .D(gpio_data_in_xor[2]), - .Q(p_1_in), - .R(bus2ip_reset)); - FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[3] - (.C(s_axi_aclk), - .CE(1'b1), - .D(gpio_data_in_xor[3]), - .Q(p_2_in), - .R(bus2ip_reset)); - FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[4] - (.C(s_axi_aclk), - .CE(1'b1), - .D(gpio_data_in_xor[4]), - .Q(p_3_in), - .R(bus2ip_reset)); - FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[5] - (.C(s_axi_aclk), - .CE(1'b1), - .D(gpio_data_in_xor[5]), - .Q(p_4_in), - .R(bus2ip_reset)); - FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[6] - (.C(s_axi_aclk), - .CE(1'b1), - .D(gpio_data_in_xor[6]), - .Q(p_5_in), - .R(bus2ip_reset)); - FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[7] - (.C(s_axi_aclk), - .CE(1'b1), - .D(gpio_data_in_xor[7]), - .Q(p_6_in), - .R(bus2ip_reset)); - FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[8] - (.C(s_axi_aclk), - .CE(1'b1), - .D(gpio_data_in_xor[8]), - .Q(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[8] ), - .R(bus2ip_reset)); - FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[9] - (.C(s_axi_aclk), - .CE(1'b1), - .D(gpio_data_in_xor[9]), - .Q(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[9] ), - .R(bus2ip_reset)); Arty_Z7_20_axi_gpio_shield_1_0_cdc_sync \Not_Dual.INPUT_DOUBLE_REGS3 - (.D({gpio_data_in_xor[0],gpio_data_in_xor[1],gpio_data_in_xor[2],gpio_data_in_xor[3],gpio_data_in_xor[4],gpio_data_in_xor[5],gpio_data_in_xor[6],gpio_data_in_xor[7],gpio_data_in_xor[8],gpio_data_in_xor[9],gpio_data_in_xor[10],gpio_data_in_xor[11],gpio_data_in_xor[12],gpio_data_in_xor[13]}), - .Q(Q), - .gpio_io_i(gpio_io_i), + (.gpio_io_i(gpio_io_i), .s_axi_aclk(s_axi_aclk), .scndry_vect_out({gpio_io_i_d2[0],gpio_io_i_d2[1],gpio_io_i_d2[2],gpio_io_i_d2[3],gpio_io_i_d2[4],gpio_io_i_d2[5],gpio_io_i_d2[6],gpio_io_i_d2[7],gpio_io_i_d2[8],gpio_io_i_d2[9],gpio_io_i_d2[10],gpio_io_i_d2[11],gpio_io_i_d2[12],gpio_io_i_d2[13]})); FDRE \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[18] (.C(s_axi_aclk), .CE(1'b1), .D(GPIO_DBus_i), - .Q(ip2bus_data[13]), - .R(Read_Reg_Rst)); + .Q(D[13]), + .R(bus2ip_rnw_i_reg)); FDRE \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28] (.C(s_axi_aclk), .CE(1'b1), - .D(\Not_Dual.gpio_OE_reg[10]_0 ), - .Q(ip2bus_data[3]), - .R(Read_Reg_Rst)); + .D(\Not_Dual.gpio_Data_In_reg[10]_0 ), + .Q(D[3]), + .R(bus2ip_rnw_i_reg)); FDRE \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29] (.C(s_axi_aclk), .CE(1'b1), - .D(\Not_Dual.gpio_OE_reg[11]_0 ), - .Q(ip2bus_data[2]), - .R(Read_Reg_Rst)); + .D(\Not_Dual.gpio_Data_In_reg[11]_0 ), + .Q(D[2]), + .R(bus2ip_rnw_i_reg)); FDRE \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30] (.C(s_axi_aclk), .CE(1'b1), - .D(\Not_Dual.gpio_OE_reg[12]_0 ), - .Q(ip2bus_data[1]), - .R(Read_Reg_Rst)); + .D(\Not_Dual.gpio_Data_In_reg[12]_0 ), + .Q(D[1]), + .R(bus2ip_rnw_i_reg)); FDRE \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[31] (.C(s_axi_aclk), .CE(1'b1), - .D(\Not_Dual.gpio_OE_reg[13]_0 ), - .Q(ip2bus_data[0]), - .R(Read_Reg_Rst)); + .D(\Not_Dual.gpio_Data_In_reg[13]_0 ), + .Q(D[0]), + .R(bus2ip_rnw_i_reg)); FDRE \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[19] (.C(s_axi_aclk), .CE(1'b1), - .D(\Not_Dual.gpio_OE_reg[1]_0 ), - .Q(ip2bus_data[12]), - .R(Read_Reg_Rst)); + .D(\Not_Dual.gpio_Data_In_reg[1]_0 ), + .Q(D[12]), + .R(bus2ip_rnw_i_reg)); FDRE \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[20] (.C(s_axi_aclk), .CE(1'b1), - .D(\Not_Dual.gpio_OE_reg[2]_0 ), - .Q(ip2bus_data[11]), - .R(Read_Reg_Rst)); + .D(\Not_Dual.gpio_Data_In_reg[2]_0 ), + .Q(D[11]), + .R(bus2ip_rnw_i_reg)); FDRE \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[21] (.C(s_axi_aclk), .CE(1'b1), - .D(\Not_Dual.gpio_OE_reg[3]_0 ), - .Q(ip2bus_data[10]), - .R(Read_Reg_Rst)); + .D(\Not_Dual.gpio_Data_In_reg[3]_0 ), + .Q(D[10]), + .R(bus2ip_rnw_i_reg)); FDRE \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[22] (.C(s_axi_aclk), .CE(1'b1), - .D(\Not_Dual.gpio_OE_reg[4]_0 ), - .Q(ip2bus_data[9]), - .R(Read_Reg_Rst)); + .D(\Not_Dual.gpio_Data_In_reg[4]_0 ), + .Q(D[9]), + .R(bus2ip_rnw_i_reg)); FDRE \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[23] (.C(s_axi_aclk), .CE(1'b1), - .D(\Not_Dual.gpio_OE_reg[5]_0 ), - .Q(ip2bus_data[8]), - .R(Read_Reg_Rst)); + .D(\Not_Dual.gpio_Data_In_reg[5]_0 ), + .Q(D[8]), + .R(bus2ip_rnw_i_reg)); FDRE \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[24] (.C(s_axi_aclk), .CE(1'b1), - .D(\Not_Dual.gpio_OE_reg[6]_0 ), - .Q(ip2bus_data[7]), - .R(Read_Reg_Rst)); + .D(\Not_Dual.gpio_Data_In_reg[6]_0 ), + .Q(D[7]), + .R(bus2ip_rnw_i_reg)); FDRE \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25] (.C(s_axi_aclk), .CE(1'b1), - .D(\Not_Dual.gpio_OE_reg[7]_0 ), - .Q(ip2bus_data[6]), - .R(Read_Reg_Rst)); + .D(\Not_Dual.gpio_Data_In_reg[7]_0 ), + .Q(D[6]), + .R(bus2ip_rnw_i_reg)); FDRE \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26] (.C(s_axi_aclk), .CE(1'b1), - .D(\Not_Dual.gpio_OE_reg[8]_0 ), - .Q(ip2bus_data[5]), - .R(Read_Reg_Rst)); + .D(\Not_Dual.gpio_Data_In_reg[8]_0 ), + .Q(D[5]), + .R(bus2ip_rnw_i_reg)); FDRE \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27] (.C(s_axi_aclk), .CE(1'b1), - .D(\Not_Dual.gpio_OE_reg[9]_0 ), - .Q(ip2bus_data[4]), - .R(Read_Reg_Rst)); + .D(\Not_Dual.gpio_Data_In_reg[9]_0 ), + .Q(D[4]), + .R(bus2ip_rnw_i_reg)); FDRE \Not_Dual.gpio_Data_In_reg[0] (.C(s_axi_aclk), .CE(1'b1), @@ -542,381 +408,345 @@ module Arty_Z7_20_axi_gpio_shield_1_0_GPIO_Core \Not_Dual.gpio_Data_Out_reg[0] (.C(s_axi_aclk), .CE(E), - .D(D[13]), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [13]), .Q(gpio_io_o[13]), - .R(bus2ip_reset)); + .R(SS)); FDRE #( .INIT(1'b0)) \Not_Dual.gpio_Data_Out_reg[10] (.C(s_axi_aclk), .CE(E), - .D(D[3]), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [3]), .Q(gpio_io_o[3]), - .R(bus2ip_reset)); + .R(SS)); FDRE #( .INIT(1'b0)) \Not_Dual.gpio_Data_Out_reg[11] (.C(s_axi_aclk), .CE(E), - .D(D[2]), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [2]), .Q(gpio_io_o[2]), - .R(bus2ip_reset)); + .R(SS)); FDRE #( .INIT(1'b0)) \Not_Dual.gpio_Data_Out_reg[12] (.C(s_axi_aclk), .CE(E), - .D(D[1]), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [1]), .Q(gpio_io_o[1]), - .R(bus2ip_reset)); + .R(SS)); FDRE #( .INIT(1'b0)) \Not_Dual.gpio_Data_Out_reg[13] (.C(s_axi_aclk), .CE(E), - .D(D[0]), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [0]), .Q(gpio_io_o[0]), - .R(bus2ip_reset)); + .R(SS)); FDRE #( .INIT(1'b0)) \Not_Dual.gpio_Data_Out_reg[1] (.C(s_axi_aclk), .CE(E), - .D(D[12]), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [12]), .Q(gpio_io_o[12]), - .R(bus2ip_reset)); + .R(SS)); FDRE #( .INIT(1'b0)) \Not_Dual.gpio_Data_Out_reg[2] (.C(s_axi_aclk), .CE(E), - .D(D[11]), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [11]), .Q(gpio_io_o[11]), - .R(bus2ip_reset)); + .R(SS)); FDRE #( .INIT(1'b0)) \Not_Dual.gpio_Data_Out_reg[3] (.C(s_axi_aclk), .CE(E), - .D(D[10]), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [10]), .Q(gpio_io_o[10]), - .R(bus2ip_reset)); + .R(SS)); FDRE #( .INIT(1'b0)) \Not_Dual.gpio_Data_Out_reg[4] (.C(s_axi_aclk), .CE(E), - .D(D[9]), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [9]), .Q(gpio_io_o[9]), - .R(bus2ip_reset)); + .R(SS)); FDRE #( .INIT(1'b0)) \Not_Dual.gpio_Data_Out_reg[5] (.C(s_axi_aclk), .CE(E), - .D(D[8]), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [8]), .Q(gpio_io_o[8]), - .R(bus2ip_reset)); + .R(SS)); FDRE #( .INIT(1'b0)) \Not_Dual.gpio_Data_Out_reg[6] (.C(s_axi_aclk), .CE(E), - .D(D[7]), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [7]), .Q(gpio_io_o[7]), - .R(bus2ip_reset)); + .R(SS)); FDRE #( .INIT(1'b0)) \Not_Dual.gpio_Data_Out_reg[7] (.C(s_axi_aclk), .CE(E), - .D(D[6]), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [6]), .Q(gpio_io_o[6]), - .R(bus2ip_reset)); + .R(SS)); FDRE #( .INIT(1'b0)) \Not_Dual.gpio_Data_Out_reg[8] (.C(s_axi_aclk), .CE(E), - .D(D[5]), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [5]), .Q(gpio_io_o[5]), - .R(bus2ip_reset)); + .R(SS)); FDRE #( .INIT(1'b0)) \Not_Dual.gpio_Data_Out_reg[9] (.C(s_axi_aclk), .CE(E), - .D(D[4]), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [4]), .Q(gpio_io_o[4]), - .R(bus2ip_reset)); + .R(SS)); FDSE #( .INIT(1'b1)) \Not_Dual.gpio_OE_reg[0] (.C(s_axi_aclk), - .CE(bus2ip_rnw_i_reg), - .D(D[13]), + .CE(rst_reg), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [13]), .Q(gpio_io_t[13]), - .S(bus2ip_reset)); + .S(SS)); FDSE #( .INIT(1'b1)) \Not_Dual.gpio_OE_reg[10] (.C(s_axi_aclk), - .CE(bus2ip_rnw_i_reg), - .D(D[3]), + .CE(rst_reg), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [3]), .Q(gpio_io_t[3]), - .S(bus2ip_reset)); + .S(SS)); FDSE #( .INIT(1'b1)) \Not_Dual.gpio_OE_reg[11] (.C(s_axi_aclk), - .CE(bus2ip_rnw_i_reg), - .D(D[2]), + .CE(rst_reg), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [2]), .Q(gpio_io_t[2]), - .S(bus2ip_reset)); + .S(SS)); FDSE #( .INIT(1'b1)) \Not_Dual.gpio_OE_reg[12] (.C(s_axi_aclk), - .CE(bus2ip_rnw_i_reg), - .D(D[1]), + .CE(rst_reg), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [1]), .Q(gpio_io_t[1]), - .S(bus2ip_reset)); + .S(SS)); FDSE #( .INIT(1'b1)) \Not_Dual.gpio_OE_reg[13] (.C(s_axi_aclk), - .CE(bus2ip_rnw_i_reg), - .D(D[0]), + .CE(rst_reg), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [0]), .Q(gpio_io_t[0]), - .S(bus2ip_reset)); + .S(SS)); FDSE #( .INIT(1'b1)) \Not_Dual.gpio_OE_reg[1] (.C(s_axi_aclk), - .CE(bus2ip_rnw_i_reg), - .D(D[12]), + .CE(rst_reg), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [12]), .Q(gpio_io_t[12]), - .S(bus2ip_reset)); + .S(SS)); FDSE #( .INIT(1'b1)) \Not_Dual.gpio_OE_reg[2] (.C(s_axi_aclk), - .CE(bus2ip_rnw_i_reg), - .D(D[11]), + .CE(rst_reg), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [11]), .Q(gpio_io_t[11]), - .S(bus2ip_reset)); + .S(SS)); FDSE #( .INIT(1'b1)) \Not_Dual.gpio_OE_reg[3] (.C(s_axi_aclk), - .CE(bus2ip_rnw_i_reg), - .D(D[10]), + .CE(rst_reg), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [10]), .Q(gpio_io_t[10]), - .S(bus2ip_reset)); + .S(SS)); FDSE #( .INIT(1'b1)) \Not_Dual.gpio_OE_reg[4] (.C(s_axi_aclk), - .CE(bus2ip_rnw_i_reg), - .D(D[9]), + .CE(rst_reg), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [9]), .Q(gpio_io_t[9]), - .S(bus2ip_reset)); + .S(SS)); FDSE #( .INIT(1'b1)) \Not_Dual.gpio_OE_reg[5] (.C(s_axi_aclk), - .CE(bus2ip_rnw_i_reg), - .D(D[8]), + .CE(rst_reg), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [8]), .Q(gpio_io_t[8]), - .S(bus2ip_reset)); + .S(SS)); FDSE #( .INIT(1'b1)) \Not_Dual.gpio_OE_reg[6] (.C(s_axi_aclk), - .CE(bus2ip_rnw_i_reg), - .D(D[7]), + .CE(rst_reg), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [7]), .Q(gpio_io_t[7]), - .S(bus2ip_reset)); + .S(SS)); FDSE #( .INIT(1'b1)) \Not_Dual.gpio_OE_reg[7] (.C(s_axi_aclk), - .CE(bus2ip_rnw_i_reg), - .D(D[6]), + .CE(rst_reg), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [6]), .Q(gpio_io_t[6]), - .S(bus2ip_reset)); + .S(SS)); FDSE #( .INIT(1'b1)) \Not_Dual.gpio_OE_reg[8] (.C(s_axi_aclk), - .CE(bus2ip_rnw_i_reg), - .D(D[5]), + .CE(rst_reg), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [5]), .Q(gpio_io_t[5]), - .S(bus2ip_reset)); + .S(SS)); FDSE #( .INIT(1'b1)) \Not_Dual.gpio_OE_reg[9] (.C(s_axi_aclk), - .CE(bus2ip_rnw_i_reg), - .D(D[4]), + .CE(rst_reg), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [4]), .Q(gpio_io_t[4]), - .S(bus2ip_reset)); + .S(SS)); FDRE gpio_xferAck_Reg_reg (.C(s_axi_aclk), .CE(1'b1), .D(GPIO_xferAck_i), .Q(gpio_xferAck_Reg), - .R(bus2ip_reset)); + .R(SS)); + (* SOFT_HLUTNM = "soft_lutpair4" *) LUT3 #( - .INIT(8'h10)) + .INIT(8'h02)) iGPIO_xferAck_i_1 - (.I0(gpio_xferAck_Reg), - .I1(GPIO_xferAck_i), - .I2(bus2ip_cs), + (.I0(bus2ip_cs), + .I1(gpio_xferAck_Reg), + .I2(GPIO_xferAck_i), .O(iGPIO_xferAck)); FDRE iGPIO_xferAck_reg (.C(s_axi_aclk), .CE(1'b1), .D(iGPIO_xferAck), .Q(GPIO_xferAck_i), - .R(bus2ip_reset)); + .R(SS)); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h8)) + ip2bus_rdack_i_D1_i_1 + (.I0(GPIO_xferAck_i), + .I1(bus2ip_rnw), + .O(ip2bus_rdack_i)); + LUT2 #( + .INIT(4'h2)) + ip2bus_wrack_i_D1_i_1 + (.I0(GPIO_xferAck_i), + .I1(bus2ip_rnw), + .O(ip2bus_wrack_i_D1_reg)); endmodule (* ORIG_REF_NAME = "address_decoder" *) module Arty_Z7_20_axi_gpio_shield_1_0_address_decoder - (\ip2bus_data_i_D1_reg[0] , - \Not_Dual.gpio_Data_Out_reg[13] , - \ip_irpt_enable_reg_reg[0] , + (\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 , + E, + \Not_Dual.gpio_OE_reg[0] , s_axi_arready, s_axi_wready, - D, - \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[31] , - \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30] , - \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29] , - \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28] , - \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27] , - \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26] , - \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25] , - \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[24] , - \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[23] , - \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[22] , - \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[21] , - \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[20] , - \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[19] , GPIO_DBus_i, - E, - \Not_Dual.gpio_Data_Out_reg[0] , - \ip2bus_data_i_D1_reg[0]_0 , - intr2bus_rdack0, - irpt_rdack, - irpt_wrack, - interrupt_wrce_strb, - Read_Reg_Rst, - \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg , - intr_rd_ce_or_reduce, - \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg , - intr_wr_ce_or_reduce, - \ip_irpt_enable_reg_reg[0]_0 , - ipif_glbl_irpt_enable_reg_reg, - start2, + \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[19] , + \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[20] , + \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[21] , + \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[22] , + \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[23] , + \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[24] , + \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25] , + \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26] , + \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27] , + \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28] , + \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29] , + \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30] , + \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[31] , + D, + \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[18] , s_axi_aclk, - s_axi_aresetn, + rst_reg, + bus2ip_rnw_i_reg, Q, - is_read, ip2bus_rdack_i_D1, - is_write_reg, + is_read, + \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] , ip2bus_wrack_i_D1, - s_axi_wdata, - \bus2ip_addr_i_reg[8] , - gpio_io_t, + is_write_reg, \Not_Dual.gpio_Data_In_reg[0] , - bus2ip_rnw_i_reg, - bus2ip_reset, - p_0_in, - irpt_rdack_d1, - irpt_wrack_d1, - ip2bus_data, - p_3_in, - p_1_in, - GPIO_xferAck_i, + gpio_io_t, + s_axi_wdata, + start2_reg, + s_axi_aresetn, gpio_xferAck_Reg, - ip2Bus_RdAck_intr_reg_hole_d1, - ip2Bus_WrAck_intr_reg_hole_d1); - output \ip2bus_data_i_D1_reg[0] ; - output \Not_Dual.gpio_Data_Out_reg[13] ; - output \ip_irpt_enable_reg_reg[0] ; + GPIO_xferAck_i); + output \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ; + output [0:0]E; + output [0:0]\Not_Dual.gpio_OE_reg[0] ; output s_axi_arready; output s_axi_wready; - output [13:0]D; - output \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[31] ; - output \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30] ; - output \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29] ; - output \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28] ; - output \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27] ; - output \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26] ; - output \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25] ; - output \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[24] ; - output \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[23] ; - output \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[22] ; - output \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[21] ; - output \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[20] ; - output \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[19] ; output [0:0]GPIO_DBus_i; - output [0:0]E; - output [0:0]\Not_Dual.gpio_Data_Out_reg[0] ; - output [1:0]\ip2bus_data_i_D1_reg[0]_0 ; - output intr2bus_rdack0; - output irpt_rdack; - output irpt_wrack; - output interrupt_wrce_strb; - output Read_Reg_Rst; - output \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ; - output intr_rd_ce_or_reduce; - output \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ; - output intr_wr_ce_or_reduce; - output \ip_irpt_enable_reg_reg[0]_0 ; - output ipif_glbl_irpt_enable_reg_reg; - input start2; + output \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[19] ; + output \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[20] ; + output \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[21] ; + output \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[22] ; + output \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[23] ; + output \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[24] ; + output \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25] ; + output \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26] ; + output \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27] ; + output \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28] ; + output \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29] ; + output \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30] ; + output \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[31] ; + output [13:0]D; + output \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[18] ; input s_axi_aclk; - input s_axi_aresetn; - input [3:0]Q; - input is_read; + input rst_reg; + input bus2ip_rnw_i_reg; + input [2:0]Q; input ip2bus_rdack_i_D1; - input is_write_reg; + input is_read; + input [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ; input ip2bus_wrack_i_D1; - input [27:0]s_axi_wdata; - input [6:0]\bus2ip_addr_i_reg[8] ; - input [13:0]gpio_io_t; + input is_write_reg; input [13:0]\Not_Dual.gpio_Data_In_reg[0] ; - input bus2ip_rnw_i_reg; - input bus2ip_reset; - input [0:0]p_0_in; - input irpt_rdack_d1; - input irpt_wrack_d1; - input [0:0]ip2bus_data; - input [0:0]p_3_in; - input [0:0]p_1_in; - input GPIO_xferAck_i; + input [13:0]gpio_io_t; + input [27:0]s_axi_wdata; + input start2_reg; + input s_axi_aresetn; input gpio_xferAck_Reg; - input ip2Bus_RdAck_intr_reg_hole_d1; - input ip2Bus_WrAck_intr_reg_hole_d1; + input GPIO_xferAck_i; - wire Bus_RNW_reg_i_1_n_0; wire [13:0]D; wire [0:0]E; - wire \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0 ; - wire \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 ; - wire \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0 ; - wire \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ; - wire \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19] ; - wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ; wire [0:0]GPIO_DBus_i; wire GPIO_xferAck_i; - wire \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ; - wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ; - wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ; - wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ; - wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ; + wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ; + wire \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ; + wire \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ; + wire \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[18] ; wire \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28] ; wire \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29] ; wire \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30] ; @@ -931,806 +761,344 @@ module Arty_Z7_20_axi_gpio_shield_1_0_address_decoder wire \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26] ; wire \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27] ; wire [13:0]\Not_Dual.gpio_Data_In_reg[0] ; - wire [0:0]\Not_Dual.gpio_Data_Out_reg[0] ; - wire \Not_Dual.gpio_Data_Out_reg[13] ; - wire [3:0]Q; - wire Read_Reg_Rst; - wire [6:0]\bus2ip_addr_i_reg[8] ; - wire bus2ip_reset; + wire [0:0]\Not_Dual.gpio_OE_reg[0] ; + wire [2:0]Q; wire bus2ip_rnw_i_reg; wire [13:0]gpio_io_t; wire gpio_xferAck_Reg; - wire interrupt_wrce_strb; - wire intr2bus_rdack0; - wire intr_rd_ce_or_reduce; - wire intr_wr_ce_or_reduce; - wire ip2Bus_RdAck_intr_reg_hole_d1; - wire ip2Bus_WrAck_intr_reg_hole_d1; - wire [0:0]ip2bus_data; - wire \ip2bus_data_i_D1_reg[0] ; - wire [1:0]\ip2bus_data_i_D1_reg[0]_0 ; wire ip2bus_rdack_i_D1; wire ip2bus_wrack_i_D1; - wire \ip_irpt_enable_reg_reg[0] ; - wire \ip_irpt_enable_reg_reg[0]_0 ; - wire ipif_glbl_irpt_enable_reg_reg; - wire irpt_rdack; - wire irpt_rdack_d1; - wire irpt_wrack; - wire irpt_wrack_d1; wire is_read; wire is_write_reg; - wire [0:0]p_0_in; - wire p_10_in; - wire p_10_out; - wire p_11_in; - wire p_11_out; - wire p_12_in; - wire p_12_out; - wire p_13_in; - wire p_13_out; - wire p_14_in; - wire p_14_out; - wire p_15_in; - wire p_15_out; - wire p_16_in; - wire [0:0]p_1_in; - wire p_2_in; - wire [0:0]p_3_in; - wire p_3_in_0; - wire p_4_in; - wire p_4_out; - wire p_5_in; - wire p_5_out; - wire p_6_in; - wire p_6_out; - wire p_7_in; - wire p_7_out; - wire p_8_out; - wire p_9_in; - wire p_9_out; - wire pselect_hit_i_1; + wire rst_reg; wire s_axi_aclk; wire s_axi_aresetn; wire s_axi_arready; wire [27:0]s_axi_wdata; wire s_axi_wready; - wire start2; + wire start2_reg; - LUT3 #( - .INIT(8'hB8)) - Bus_RNW_reg_i_1 - (.I0(bus2ip_rnw_i_reg), - .I1(start2), - .I2(\ip_irpt_enable_reg_reg[0] ), - .O(Bus_RNW_reg_i_1_n_0)); - FDRE Bus_RNW_reg_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(Bus_RNW_reg_i_1_n_0), - .Q(\ip_irpt_enable_reg_reg[0] ), - .R(1'b0)); - LUT6 #( - .INIT(64'h0040000000000000)) - \GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1 - (.I0(\bus2ip_addr_i_reg[8] [3]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\bus2ip_addr_i_reg[8] [2]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(p_9_out)); - FDRE \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10] - (.C(s_axi_aclk), - .CE(start2), - .D(p_9_out), - .Q(p_10_in), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT6 #( - .INIT(64'h4000000000000000)) - \GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1 - (.I0(\bus2ip_addr_i_reg[8] [3]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\bus2ip_addr_i_reg[8] [2]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(p_8_out)); - FDRE \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] - (.C(s_axi_aclk), - .CE(start2), - .D(p_8_out), - .Q(p_9_in), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0004000000000000)) - \GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1 - (.I0(\bus2ip_addr_i_reg[8] [1]), - .I1(\bus2ip_addr_i_reg[8] [3]), - .I2(\bus2ip_addr_i_reg[8] [2]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(p_7_out)); - FDRE \GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12] - (.C(s_axi_aclk), - .CE(start2), - .D(p_7_out), - .Q(\ip2bus_data_i_D1_reg[0] ), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0400000000000000)) - \GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1 - (.I0(\bus2ip_addr_i_reg[8] [1]), - .I1(\bus2ip_addr_i_reg[8] [3]), - .I2(\bus2ip_addr_i_reg[8] [2]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(p_6_out)); - FDRE \GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13] - (.C(s_axi_aclk), - .CE(start2), - .D(p_6_out), - .Q(p_7_in), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0008000000000000)) - \GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1 - (.I0(\bus2ip_addr_i_reg[8] [1]), - .I1(\bus2ip_addr_i_reg[8] [3]), - .I2(\bus2ip_addr_i_reg[8] [2]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(p_5_out)); - FDRE \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] - (.C(s_axi_aclk), - .CE(start2), - .D(p_5_out), - .Q(p_6_in), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0800000000000000)) - \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1 - (.I0(\bus2ip_addr_i_reg[8] [1]), - .I1(\bus2ip_addr_i_reg[8] [3]), - .I2(\bus2ip_addr_i_reg[8] [2]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(p_4_out)); - FDRE \GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15] - (.C(s_axi_aclk), - .CE(start2), - .D(p_4_out), - .Q(p_5_in), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0008000000000000)) - \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1 - (.I0(\bus2ip_addr_i_reg[8] [3]), - .I1(\bus2ip_addr_i_reg[8] [2]), - .I2(\bus2ip_addr_i_reg[8] [1]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0 )); - FDRE \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16] - (.C(s_axi_aclk), - .CE(start2), - .D(\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0 ), - .Q(p_4_in), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0800000000000000)) - \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1 - (.I0(\bus2ip_addr_i_reg[8] [3]), - .I1(\bus2ip_addr_i_reg[8] [2]), - .I2(\bus2ip_addr_i_reg[8] [1]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 )); - FDRE \GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17] - (.C(s_axi_aclk), - .CE(start2), - .D(\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 ), - .Q(p_3_in_0), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0080000000000000)) - \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1 - (.I0(\bus2ip_addr_i_reg[8] [3]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\bus2ip_addr_i_reg[8] [2]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0 )); - FDRE \GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18] - (.C(s_axi_aclk), - .CE(start2), - .D(\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0 ), - .Q(p_2_in), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT3 #( - .INIT(8'hFD)) - \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1 - (.I0(s_axi_aresetn), - .I1(s_axi_arready), - .I2(s_axi_wready), - .O(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT6 #( - .INIT(64'h8000000000000000)) - \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_2 - (.I0(\bus2ip_addr_i_reg[8] [3]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\bus2ip_addr_i_reg[8] [2]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(p_15_out)); - FDRE \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg[19] - (.C(s_axi_aclk), - .CE(start2), - .D(p_15_out), - .Q(\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19] ), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0001000000000000)) - \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1 - (.I0(\bus2ip_addr_i_reg[8] [1]), - .I1(\bus2ip_addr_i_reg[8] [2]), - .I2(\bus2ip_addr_i_reg[8] [3]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 )); - FDRE \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] - (.C(s_axi_aclk), - .CE(start2), - .D(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ), - .Q(p_16_in), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0100000000000000)) - \GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1 - (.I0(\bus2ip_addr_i_reg[8] [1]), - .I1(\bus2ip_addr_i_reg[8] [2]), - .I2(\bus2ip_addr_i_reg[8] [3]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(p_14_out)); - FDRE \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] - (.C(s_axi_aclk), - .CE(start2), - .D(p_14_out), - .Q(p_15_in), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0002000000000000)) - \GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1 - (.I0(\bus2ip_addr_i_reg[8] [1]), - .I1(\bus2ip_addr_i_reg[8] [2]), - .I2(\bus2ip_addr_i_reg[8] [3]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(p_13_out)); - FDRE \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] - (.C(s_axi_aclk), - .CE(start2), - .D(p_13_out), - .Q(p_14_in), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0200000000000000)) - \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1 - (.I0(\bus2ip_addr_i_reg[8] [1]), - .I1(\bus2ip_addr_i_reg[8] [2]), - .I2(\bus2ip_addr_i_reg[8] [3]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(p_12_out)); - FDRE \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] - (.C(s_axi_aclk), - .CE(start2), - .D(p_12_out), - .Q(p_13_in), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0004000000000000)) - \GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1 - (.I0(\bus2ip_addr_i_reg[8] [3]), - .I1(\bus2ip_addr_i_reg[8] [2]), - .I2(\bus2ip_addr_i_reg[8] [1]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(p_11_out)); - FDRE \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8] - (.C(s_axi_aclk), - .CE(start2), - .D(p_11_out), - .Q(p_12_in), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0400000000000000)) - \GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1 - (.I0(\bus2ip_addr_i_reg[8] [3]), - .I1(\bus2ip_addr_i_reg[8] [2]), - .I2(\bus2ip_addr_i_reg[8] [1]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(p_10_out)); - FDRE \GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9] - (.C(s_axi_aclk), - .CE(start2), - .D(p_10_out), - .Q(p_11_in), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair0" *) - LUT4 #( - .INIT(16'hFE00)) - \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_i_1 - (.I0(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ), - .I1(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ), - .I2(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ), - .I3(\ip_irpt_enable_reg_reg[0] ), - .O(intr_rd_ce_or_reduce)); - (* SOFT_HLUTNM = "soft_lutpair1" *) - LUT5 #( - .INIT(32'h00FE0000)) - \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_i_1 - (.I0(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ), - .I1(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ), - .I2(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ), - .I3(ip2Bus_RdAck_intr_reg_hole_d1), - .I4(\ip_irpt_enable_reg_reg[0] ), - .O(\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg )); - (* SOFT_HLUTNM = "soft_lutpair1" *) - LUT4 #( - .INIT(16'h00FE)) - \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_1 - (.I0(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ), - .I1(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ), - .I2(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ), - .I3(\ip_irpt_enable_reg_reg[0] ), - .O(intr_wr_ce_or_reduce)); LUT5 #( - .INIT(32'hFFFFFFFE)) - \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2 - (.I0(p_16_in), - .I1(p_2_in), - .I2(\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19] ), - .I3(p_14_in), - .I4(p_15_in), - .O(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 )); - LUT4 #( - .INIT(16'hFFFE)) - \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3 - (.I0(p_12_in), - .I1(p_13_in), - .I2(p_10_in), - .I3(p_11_in), - .O(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 )); - LUT4 #( - .INIT(16'hFFFE)) - \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4 - (.I0(p_5_in), - .I1(p_7_in), - .I2(p_3_in_0), - .I3(p_4_in), - .O(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair0" *) - LUT5 #( - .INIT(32'h000000FE)) - \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_1 - (.I0(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ), - .I1(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ), - .I2(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ), - .I3(\ip_irpt_enable_reg_reg[0] ), - .I4(ip2Bus_WrAck_intr_reg_hole_d1), - .O(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg )); - LUT6 #( - .INIT(64'h0000000000000002)) + .INIT(32'h000000E0)) \MEM_DECODE_GEN[0].cs_out_i[0]_i_1 - (.I0(start2), - .I1(\bus2ip_addr_i_reg[8] [6]), - .I2(\bus2ip_addr_i_reg[8] [4]), - .I3(\bus2ip_addr_i_reg[8] [5]), - .I4(\bus2ip_addr_i_reg[8] [3]), - .I5(\bus2ip_addr_i_reg[8] [2]), - .O(pselect_hit_i_1)); + (.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I1(start2_reg), + .I2(s_axi_aresetn), + .I3(s_axi_arready), + .I4(s_axi_wready), + .O(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 )); FDRE \MEM_DECODE_GEN[0].cs_out_i_reg[0] (.C(s_axi_aclk), - .CE(start2), - .D(pselect_hit_i_1), - .Q(\Not_Dual.gpio_Data_Out_reg[13] ), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); + .CE(1'b1), + .D(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ), + .Q(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .R(1'b0)); LUT6 #( - .INIT(64'h000A0000000C0000)) + .INIT(64'h000000E000000020)) \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i[18]_i_1 - (.I0(gpio_io_t[13]), - .I1(\Not_Dual.gpio_Data_In_reg[0] [13]), - .I2(\bus2ip_addr_i_reg[8] [6]), - .I3(\bus2ip_addr_i_reg[8] [1]), - .I4(\Not_Dual.gpio_Data_Out_reg[13] ), - .I5(\bus2ip_addr_i_reg[8] [0]), + (.I0(\Not_Dual.gpio_Data_In_reg[0] [13]), + .I1(Q[0]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[1]), + .I5(gpio_io_t[13]), .O(GPIO_DBus_i)); LUT6 #( - .INIT(64'h000A0000000C0000)) + .INIT(64'h000000E000000020)) \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i[28]_i_1 - (.I0(gpio_io_t[3]), - .I1(\Not_Dual.gpio_Data_In_reg[0] [3]), - .I2(\bus2ip_addr_i_reg[8] [6]), - .I3(\bus2ip_addr_i_reg[8] [1]), - .I4(\Not_Dual.gpio_Data_Out_reg[13] ), - .I5(\bus2ip_addr_i_reg[8] [0]), + (.I0(\Not_Dual.gpio_Data_In_reg[0] [3]), + .I1(Q[0]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[1]), + .I5(gpio_io_t[3]), .O(\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28] )); LUT6 #( - .INIT(64'h000A0000000C0000)) + .INIT(64'h000000E000000020)) \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i[29]_i_1 - (.I0(gpio_io_t[2]), - .I1(\Not_Dual.gpio_Data_In_reg[0] [2]), - .I2(\bus2ip_addr_i_reg[8] [6]), - .I3(\bus2ip_addr_i_reg[8] [1]), - .I4(\Not_Dual.gpio_Data_Out_reg[13] ), - .I5(\bus2ip_addr_i_reg[8] [0]), + (.I0(\Not_Dual.gpio_Data_In_reg[0] [2]), + .I1(Q[0]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[1]), + .I5(gpio_io_t[2]), .O(\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29] )); LUT6 #( - .INIT(64'h000A0000000C0000)) + .INIT(64'h000000E000000020)) \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i[30]_i_1 - (.I0(gpio_io_t[1]), - .I1(\Not_Dual.gpio_Data_In_reg[0] [1]), - .I2(\bus2ip_addr_i_reg[8] [6]), - .I3(\bus2ip_addr_i_reg[8] [1]), - .I4(\Not_Dual.gpio_Data_Out_reg[13] ), - .I5(\bus2ip_addr_i_reg[8] [0]), + (.I0(\Not_Dual.gpio_Data_In_reg[0] [1]), + .I1(Q[0]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[1]), + .I5(gpio_io_t[1]), .O(\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30] )); LUT4 #( - .INIT(16'hFFDF)) + .INIT(16'hFFF7)) \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i[31]_i_1 - (.I0(\Not_Dual.gpio_Data_Out_reg[13] ), - .I1(GPIO_xferAck_i), - .I2(bus2ip_rnw_i_reg), - .I3(gpio_xferAck_Reg), - .O(Read_Reg_Rst)); + (.I0(bus2ip_rnw_i_reg), + .I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I2(gpio_xferAck_Reg), + .I3(GPIO_xferAck_i), + .O(\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[18] )); LUT6 #( - .INIT(64'h000A0000000C0000)) + .INIT(64'h000000E000000020)) \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i[31]_i_2 - (.I0(gpio_io_t[0]), - .I1(\Not_Dual.gpio_Data_In_reg[0] [0]), - .I2(\bus2ip_addr_i_reg[8] [6]), - .I3(\bus2ip_addr_i_reg[8] [1]), - .I4(\Not_Dual.gpio_Data_Out_reg[13] ), - .I5(\bus2ip_addr_i_reg[8] [0]), + (.I0(\Not_Dual.gpio_Data_In_reg[0] [0]), + .I1(Q[0]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[1]), + .I5(gpio_io_t[0]), .O(\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[31] )); LUT6 #( - .INIT(64'h000A0000000C0000)) + .INIT(64'h000000E000000020)) \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i[19]_i_1 - (.I0(gpio_io_t[12]), - .I1(\Not_Dual.gpio_Data_In_reg[0] [12]), - .I2(\bus2ip_addr_i_reg[8] [6]), - .I3(\bus2ip_addr_i_reg[8] [1]), - .I4(\Not_Dual.gpio_Data_Out_reg[13] ), - .I5(\bus2ip_addr_i_reg[8] [0]), + (.I0(\Not_Dual.gpio_Data_In_reg[0] [12]), + .I1(Q[0]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[1]), + .I5(gpio_io_t[12]), .O(\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[19] )); LUT6 #( - .INIT(64'h000A0000000C0000)) + .INIT(64'h000000E000000020)) \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i[20]_i_1 - (.I0(gpio_io_t[11]), - .I1(\Not_Dual.gpio_Data_In_reg[0] [11]), - .I2(\bus2ip_addr_i_reg[8] [6]), - .I3(\bus2ip_addr_i_reg[8] [1]), - .I4(\Not_Dual.gpio_Data_Out_reg[13] ), - .I5(\bus2ip_addr_i_reg[8] [0]), + (.I0(\Not_Dual.gpio_Data_In_reg[0] [11]), + .I1(Q[0]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[1]), + .I5(gpio_io_t[11]), .O(\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[20] )); LUT6 #( - .INIT(64'h000A0000000C0000)) + .INIT(64'h000000E000000020)) \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i[21]_i_1 - (.I0(gpio_io_t[10]), - .I1(\Not_Dual.gpio_Data_In_reg[0] [10]), - .I2(\bus2ip_addr_i_reg[8] [6]), - .I3(\bus2ip_addr_i_reg[8] [1]), - .I4(\Not_Dual.gpio_Data_Out_reg[13] ), - .I5(\bus2ip_addr_i_reg[8] [0]), + (.I0(\Not_Dual.gpio_Data_In_reg[0] [10]), + .I1(Q[0]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[1]), + .I5(gpio_io_t[10]), .O(\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[21] )); LUT6 #( - .INIT(64'h000A0000000C0000)) + .INIT(64'h000000E000000020)) \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i[22]_i_1 - (.I0(gpio_io_t[9]), - .I1(\Not_Dual.gpio_Data_In_reg[0] [9]), - .I2(\bus2ip_addr_i_reg[8] [6]), - .I3(\bus2ip_addr_i_reg[8] [1]), - .I4(\Not_Dual.gpio_Data_Out_reg[13] ), - .I5(\bus2ip_addr_i_reg[8] [0]), + (.I0(\Not_Dual.gpio_Data_In_reg[0] [9]), + .I1(Q[0]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[1]), + .I5(gpio_io_t[9]), .O(\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[22] )); LUT6 #( - .INIT(64'h000A0000000C0000)) + .INIT(64'h000000E000000020)) \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i[23]_i_1 - (.I0(gpio_io_t[8]), - .I1(\Not_Dual.gpio_Data_In_reg[0] [8]), - .I2(\bus2ip_addr_i_reg[8] [6]), - .I3(\bus2ip_addr_i_reg[8] [1]), - .I4(\Not_Dual.gpio_Data_Out_reg[13] ), - .I5(\bus2ip_addr_i_reg[8] [0]), + (.I0(\Not_Dual.gpio_Data_In_reg[0] [8]), + .I1(Q[0]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[1]), + .I5(gpio_io_t[8]), .O(\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[23] )); LUT6 #( - .INIT(64'h000A0000000C0000)) + .INIT(64'h000000E000000020)) \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i[24]_i_1 - (.I0(gpio_io_t[7]), - .I1(\Not_Dual.gpio_Data_In_reg[0] [7]), - .I2(\bus2ip_addr_i_reg[8] [6]), - .I3(\bus2ip_addr_i_reg[8] [1]), - .I4(\Not_Dual.gpio_Data_Out_reg[13] ), - .I5(\bus2ip_addr_i_reg[8] [0]), + (.I0(\Not_Dual.gpio_Data_In_reg[0] [7]), + .I1(Q[0]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[1]), + .I5(gpio_io_t[7]), .O(\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[24] )); LUT6 #( - .INIT(64'h000A0000000C0000)) + .INIT(64'h000000E000000020)) \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i[25]_i_1 - (.I0(gpio_io_t[6]), - .I1(\Not_Dual.gpio_Data_In_reg[0] [6]), - .I2(\bus2ip_addr_i_reg[8] [6]), - .I3(\bus2ip_addr_i_reg[8] [1]), - .I4(\Not_Dual.gpio_Data_Out_reg[13] ), - .I5(\bus2ip_addr_i_reg[8] [0]), + (.I0(\Not_Dual.gpio_Data_In_reg[0] [6]), + .I1(Q[0]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[1]), + .I5(gpio_io_t[6]), .O(\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25] )); LUT6 #( - .INIT(64'h000A0000000C0000)) + .INIT(64'h000000E000000020)) \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i[26]_i_1 - (.I0(gpio_io_t[5]), - .I1(\Not_Dual.gpio_Data_In_reg[0] [5]), - .I2(\bus2ip_addr_i_reg[8] [6]), - .I3(\bus2ip_addr_i_reg[8] [1]), - .I4(\Not_Dual.gpio_Data_Out_reg[13] ), - .I5(\bus2ip_addr_i_reg[8] [0]), + (.I0(\Not_Dual.gpio_Data_In_reg[0] [5]), + .I1(Q[0]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[1]), + .I5(gpio_io_t[5]), .O(\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26] )); LUT6 #( - .INIT(64'h000A0000000C0000)) + .INIT(64'h000000E000000020)) \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i[27]_i_1 - (.I0(gpio_io_t[4]), - .I1(\Not_Dual.gpio_Data_In_reg[0] [4]), - .I2(\bus2ip_addr_i_reg[8] [6]), - .I3(\bus2ip_addr_i_reg[8] [1]), - .I4(\Not_Dual.gpio_Data_Out_reg[13] ), - .I5(\bus2ip_addr_i_reg[8] [0]), + (.I0(\Not_Dual.gpio_Data_In_reg[0] [4]), + .I1(Q[0]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[1]), + .I5(gpio_io_t[4]), .O(\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27] )); LUT6 #( - .INIT(64'hFFFFFFFF00000100)) + .INIT(64'hAAAAAAAAAAAAABAA)) \Not_Dual.gpio_Data_Out[0]_i_1 - (.I0(bus2ip_rnw_i_reg), - .I1(\bus2ip_addr_i_reg[8] [6]), - .I2(\bus2ip_addr_i_reg[8] [1]), - .I3(\Not_Dual.gpio_Data_Out_reg[13] ), - .I4(\bus2ip_addr_i_reg[8] [0]), - .I5(bus2ip_reset), - .O(\Not_Dual.gpio_Data_Out_reg[0] )); + (.I0(rst_reg), + .I1(bus2ip_rnw_i_reg), + .I2(Q[0]), + .I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I4(Q[2]), + .I5(Q[1]), + .O(E)); LUT4 #( - .INIT(16'hBA8A)) + .INIT(16'hCCAC)) \Not_Dual.gpio_Data_Out[0]_i_2 - (.I0(s_axi_wdata[27]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\Not_Dual.gpio_Data_Out_reg[13] ), - .I3(s_axi_wdata[13]), + (.I0(s_axi_wdata[13]), + .I1(s_axi_wdata[27]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[1]), .O(D[13])); LUT4 #( - .INIT(16'hBA8A)) + .INIT(16'hCCAC)) \Not_Dual.gpio_Data_Out[10]_i_1 - (.I0(s_axi_wdata[17]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\Not_Dual.gpio_Data_Out_reg[13] ), - .I3(s_axi_wdata[3]), + (.I0(s_axi_wdata[3]), + .I1(s_axi_wdata[17]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[1]), .O(D[3])); LUT4 #( - .INIT(16'hBA8A)) + .INIT(16'hCCAC)) \Not_Dual.gpio_Data_Out[11]_i_1 - (.I0(s_axi_wdata[16]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\Not_Dual.gpio_Data_Out_reg[13] ), - .I3(s_axi_wdata[2]), + (.I0(s_axi_wdata[2]), + .I1(s_axi_wdata[16]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[1]), .O(D[2])); LUT4 #( - .INIT(16'hBA8A)) + .INIT(16'hCCAC)) \Not_Dual.gpio_Data_Out[12]_i_1 - (.I0(s_axi_wdata[15]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\Not_Dual.gpio_Data_Out_reg[13] ), - .I3(s_axi_wdata[1]), + (.I0(s_axi_wdata[1]), + .I1(s_axi_wdata[15]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[1]), .O(D[1])); LUT4 #( - .INIT(16'hBA8A)) + .INIT(16'hCCAC)) \Not_Dual.gpio_Data_Out[13]_i_1 - (.I0(s_axi_wdata[14]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\Not_Dual.gpio_Data_Out_reg[13] ), - .I3(s_axi_wdata[0]), + (.I0(s_axi_wdata[0]), + .I1(s_axi_wdata[14]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[1]), .O(D[0])); LUT4 #( - .INIT(16'hBA8A)) + .INIT(16'hCCAC)) \Not_Dual.gpio_Data_Out[1]_i_1 - (.I0(s_axi_wdata[26]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\Not_Dual.gpio_Data_Out_reg[13] ), - .I3(s_axi_wdata[12]), + (.I0(s_axi_wdata[12]), + .I1(s_axi_wdata[26]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[1]), .O(D[12])); LUT4 #( - .INIT(16'hBA8A)) + .INIT(16'hCCAC)) \Not_Dual.gpio_Data_Out[2]_i_1 - (.I0(s_axi_wdata[25]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\Not_Dual.gpio_Data_Out_reg[13] ), - .I3(s_axi_wdata[11]), + (.I0(s_axi_wdata[11]), + .I1(s_axi_wdata[25]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[1]), .O(D[11])); LUT4 #( - .INIT(16'hBA8A)) + .INIT(16'hCCAC)) \Not_Dual.gpio_Data_Out[3]_i_1 - (.I0(s_axi_wdata[24]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\Not_Dual.gpio_Data_Out_reg[13] ), - .I3(s_axi_wdata[10]), + (.I0(s_axi_wdata[10]), + .I1(s_axi_wdata[24]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[1]), .O(D[10])); LUT4 #( - .INIT(16'hBA8A)) + .INIT(16'hCCAC)) \Not_Dual.gpio_Data_Out[4]_i_1 - (.I0(s_axi_wdata[23]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\Not_Dual.gpio_Data_Out_reg[13] ), - .I3(s_axi_wdata[9]), + (.I0(s_axi_wdata[9]), + .I1(s_axi_wdata[23]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[1]), .O(D[9])); LUT4 #( - .INIT(16'hBA8A)) + .INIT(16'hCCAC)) \Not_Dual.gpio_Data_Out[5]_i_1 - (.I0(s_axi_wdata[22]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\Not_Dual.gpio_Data_Out_reg[13] ), - .I3(s_axi_wdata[8]), + (.I0(s_axi_wdata[8]), + .I1(s_axi_wdata[22]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[1]), .O(D[8])); LUT4 #( - .INIT(16'hBA8A)) + .INIT(16'hCCAC)) \Not_Dual.gpio_Data_Out[6]_i_1 - (.I0(s_axi_wdata[21]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\Not_Dual.gpio_Data_Out_reg[13] ), - .I3(s_axi_wdata[7]), + (.I0(s_axi_wdata[7]), + .I1(s_axi_wdata[21]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[1]), .O(D[7])); LUT4 #( - .INIT(16'hBA8A)) + .INIT(16'hCCAC)) \Not_Dual.gpio_Data_Out[7]_i_1 - (.I0(s_axi_wdata[20]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\Not_Dual.gpio_Data_Out_reg[13] ), - .I3(s_axi_wdata[6]), + (.I0(s_axi_wdata[6]), + .I1(s_axi_wdata[20]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[1]), .O(D[6])); LUT4 #( - .INIT(16'hBA8A)) + .INIT(16'hCCAC)) \Not_Dual.gpio_Data_Out[8]_i_1 - (.I0(s_axi_wdata[19]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\Not_Dual.gpio_Data_Out_reg[13] ), - .I3(s_axi_wdata[5]), + (.I0(s_axi_wdata[5]), + .I1(s_axi_wdata[19]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[1]), .O(D[5])); LUT4 #( - .INIT(16'hBA8A)) + .INIT(16'hCCAC)) \Not_Dual.gpio_Data_Out[9]_i_1 - (.I0(s_axi_wdata[18]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\Not_Dual.gpio_Data_Out_reg[13] ), - .I3(s_axi_wdata[4]), + (.I0(s_axi_wdata[4]), + .I1(s_axi_wdata[18]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[1]), .O(D[4])); LUT6 #( - .INIT(64'hFFFFFFFF01000000)) + .INIT(64'hAAAAAAAAAABAAAAA)) \Not_Dual.gpio_OE[0]_i_1 - (.I0(bus2ip_rnw_i_reg), - .I1(\bus2ip_addr_i_reg[8] [6]), - .I2(\bus2ip_addr_i_reg[8] [1]), - .I3(\Not_Dual.gpio_Data_Out_reg[13] ), - .I4(\bus2ip_addr_i_reg[8] [0]), - .I5(bus2ip_reset), - .O(E)); - (* SOFT_HLUTNM = "soft_lutpair2" *) - LUT5 #( - .INIT(32'h44444440)) - intr2bus_rdack_i_1 - (.I0(irpt_rdack_d1), - .I1(\ip_irpt_enable_reg_reg[0] ), - .I2(p_9_in), - .I3(\ip2bus_data_i_D1_reg[0] ), - .I4(p_6_in), - .O(intr2bus_rdack0)); - LUT5 #( - .INIT(32'h000000FE)) - intr2bus_wrack_i_1 - (.I0(p_9_in), - .I1(\ip2bus_data_i_D1_reg[0] ), - .I2(p_6_in), - .I3(\ip_irpt_enable_reg_reg[0] ), - .I4(irpt_wrack_d1), - .O(interrupt_wrce_strb)); - (* SOFT_HLUTNM = "soft_lutpair3" *) - LUT5 #( - .INIT(32'h00000080)) - \ip2bus_data_i_D1[0]_i_1 - (.I0(p_0_in), - .I1(p_9_in), - .I2(\ip_irpt_enable_reg_reg[0] ), - .I3(p_6_in), - .I4(\ip2bus_data_i_D1_reg[0] ), - .O(\ip2bus_data_i_D1_reg[0]_0 [1])); - LUT6 #( - .INIT(64'hEEEEAAAAFAAAAAAA)) - \ip2bus_data_i_D1[31]_i_1 - (.I0(ip2bus_data), - .I1(p_3_in), - .I2(p_1_in), - .I3(p_6_in), - .I4(\ip_irpt_enable_reg_reg[0] ), - .I5(\ip2bus_data_i_D1_reg[0] ), - .O(\ip2bus_data_i_D1_reg[0]_0 [0])); - LUT4 #( - .INIT(16'hFB08)) - \ip_irpt_enable_reg[0]_i_1 - (.I0(s_axi_wdata[0]), - .I1(p_6_in), - .I2(\ip_irpt_enable_reg_reg[0] ), - .I3(p_1_in), - .O(\ip_irpt_enable_reg_reg[0]_0 )); - LUT4 #( - .INIT(16'hFB08)) - ipif_glbl_irpt_enable_reg_i_1 - (.I0(s_axi_wdata[27]), - .I1(p_9_in), - .I2(\ip_irpt_enable_reg_reg[0] ), - .I3(p_0_in), - .O(ipif_glbl_irpt_enable_reg_reg)); - (* SOFT_HLUTNM = "soft_lutpair2" *) - LUT4 #( - .INIT(16'hFE00)) - irpt_rdack_d1_i_1 - (.I0(p_9_in), - .I1(\ip2bus_data_i_D1_reg[0] ), - .I2(p_6_in), - .I3(\ip_irpt_enable_reg_reg[0] ), - .O(irpt_rdack)); - (* SOFT_HLUTNM = "soft_lutpair3" *) - LUT4 #( - .INIT(16'h00FE)) - irpt_wrack_d1_i_1 - (.I0(p_9_in), - .I1(\ip2bus_data_i_D1_reg[0] ), - .I2(p_6_in), - .I3(\ip_irpt_enable_reg_reg[0] ), - .O(irpt_wrack)); + (.I0(rst_reg), + .I1(bus2ip_rnw_i_reg), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[0]), + .I5(Q[1]), + .O(\Not_Dual.gpio_OE_reg[0] )); LUT6 #( - .INIT(64'hFFFFFFFF00020000)) + .INIT(64'hAAAAAAAAAAAEAAAA)) s_axi_arready_INST_0 - (.I0(Q[3]), - .I1(Q[2]), - .I2(Q[1]), - .I3(Q[0]), - .I4(is_read), - .I5(ip2bus_rdack_i_D1), + (.I0(ip2bus_rdack_i_D1), + .I1(is_read), + .I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]), + .I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]), + .I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]), + .I5(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]), .O(s_axi_arready)); LUT6 #( - .INIT(64'hFFFFFFFF00020000)) + .INIT(64'hAAAAAAAAAAAEAAAA)) s_axi_wready_INST_0 - (.I0(Q[3]), - .I1(Q[2]), - .I2(Q[1]), - .I3(Q[0]), - .I4(is_write_reg), - .I5(ip2bus_wrack_i_D1), + (.I0(ip2bus_wrack_i_D1), + .I1(is_write_reg), + .I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]), + .I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]), + .I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]), + .I5(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]), .O(s_axi_wready)); endmodule (* C_ALL_INPUTS = "0" *) (* C_ALL_INPUTS_2 = "0" *) (* C_ALL_OUTPUTS = "0" *) (* C_ALL_OUTPUTS_2 = "0" *) (* C_DOUT_DEFAULT = "0" *) (* C_DOUT_DEFAULT_2 = "0" *) (* C_FAMILY = "zynq" *) (* C_GPIO2_WIDTH = "32" *) (* C_GPIO_WIDTH = "14" *) -(* C_INTERRUPT_PRESENT = "1" *) (* C_IS_DUAL = "0" *) (* C_S_AXI_ADDR_WIDTH = "9" *) +(* C_INTERRUPT_PRESENT = "0" *) (* C_IS_DUAL = "0" *) (* C_S_AXI_ADDR_WIDTH = "9" *) (* C_S_AXI_DATA_WIDTH = "32" *) (* C_TRI_DEFAULT = "-1" *) (* C_TRI_DEFAULT_2 = "-1" *) (* ORIG_REF_NAME = "axi_gpio" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_group = "LOGICORE" *) module Arty_Z7_20_axi_gpio_shield_1_0_axi_gpio @@ -1789,66 +1157,39 @@ module Arty_Z7_20_axi_gpio_shield_1_0_axi_gpio wire \ ; wire \ ; + wire AXI_LITE_IPIF_I_n_10; + wire AXI_LITE_IPIF_I_n_11; + wire AXI_LITE_IPIF_I_n_12; + wire AXI_LITE_IPIF_I_n_13; + wire AXI_LITE_IPIF_I_n_14; + wire AXI_LITE_IPIF_I_n_15; + wire AXI_LITE_IPIF_I_n_16; + wire AXI_LITE_IPIF_I_n_17; + wire AXI_LITE_IPIF_I_n_18; + wire AXI_LITE_IPIF_I_n_19; + wire AXI_LITE_IPIF_I_n_20; + wire AXI_LITE_IPIF_I_n_21; wire AXI_LITE_IPIF_I_n_22; - wire AXI_LITE_IPIF_I_n_23; - wire AXI_LITE_IPIF_I_n_24; - wire AXI_LITE_IPIF_I_n_25; - wire AXI_LITE_IPIF_I_n_26; - wire AXI_LITE_IPIF_I_n_27; - wire AXI_LITE_IPIF_I_n_28; - wire AXI_LITE_IPIF_I_n_29; - wire AXI_LITE_IPIF_I_n_30; - wire AXI_LITE_IPIF_I_n_31; - wire AXI_LITE_IPIF_I_n_32; - wire AXI_LITE_IPIF_I_n_33; - wire AXI_LITE_IPIF_I_n_34; - wire AXI_LITE_IPIF_I_n_36; wire AXI_LITE_IPIF_I_n_37; - wire AXI_LITE_IPIF_I_n_45; - wire AXI_LITE_IPIF_I_n_47; - wire AXI_LITE_IPIF_I_n_49; - wire AXI_LITE_IPIF_I_n_50; + wire AXI_LITE_IPIF_I_n_6; + wire AXI_LITE_IPIF_I_n_7; wire [0:13]DBus_Reg; wire [18:18]GPIO_DBus_i; - wire GPIO_intr; wire GPIO_xferAck_i; - wire IP2INTC_Irpt_i; - wire \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ; - wire \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in ; - wire Read_Reg_Rst; - wire [1:1]bus2ip_cs; + wire bus2ip_cs; wire bus2ip_reset; - wire bus2ip_reset_i_1_n_0; wire bus2ip_rnw; wire [0:13]gpio_Data_In; + wire gpio_core_1_n_17; wire [13:0]gpio_io_i; wire [13:0]gpio_io_o; wire [13:0]gpio_io_t; wire gpio_xferAck_Reg; - wire interrupt_wrce_strb; - wire intr2bus_rdack0; - wire intr_rd_ce_or_reduce; - wire intr_wr_ce_or_reduce; - wire ip2Bus_RdAck_intr_reg_hole; - wire ip2Bus_RdAck_intr_reg_hole_d1; - wire ip2Bus_WrAck_intr_reg_hole; - wire ip2Bus_WrAck_intr_reg_hole_d1; wire [18:31]ip2bus_data; - wire [31:31]ip2bus_data_i; - wire [0:31]ip2bus_data_i_D1; + wire [18:31]ip2bus_data_i_D1; wire ip2bus_rdack_i; wire ip2bus_rdack_i_D1; - wire ip2bus_wrack_i; wire ip2bus_wrack_i_D1; - wire ip2intc_irpt; - wire irpt_rdack; - wire irpt_rdack_d1; - wire irpt_wrack; - wire irpt_wrack_d1; - wire [31:31]p_0_in; - wire [0:0]p_0_out; - wire [0:0]p_1_in; - wire [0:0]p_3_in; (* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Clk" *) wire s_axi_aclk; wire [8:0]s_axi_araddr; (* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Rst" *) wire s_axi_aresetn; @@ -1858,7 +1199,7 @@ module Arty_Z7_20_axi_gpio_shield_1_0_axi_gpio wire s_axi_awvalid; wire s_axi_bready; wire s_axi_bvalid; - wire [31:0]\^s_axi_rdata ; + wire [13:0]\^s_axi_rdata ; wire s_axi_rready; wire s_axi_rvalid; wire [31:0]s_axi_wdata; @@ -1929,10 +1270,11 @@ module Arty_Z7_20_axi_gpio_shield_1_0_axi_gpio assign gpio2_io_t[2] = \ ; assign gpio2_io_t[1] = \ ; assign gpio2_io_t[0] = \ ; + assign ip2intc_irpt = \ ; assign s_axi_awready = s_axi_wready; assign s_axi_bresp[1] = \ ; assign s_axi_bresp[0] = \ ; - assign s_axi_rdata[31] = \^s_axi_rdata [31]; + assign s_axi_rdata[31] = \ ; assign s_axi_rdata[30] = \ ; assign s_axi_rdata[29] = \ ; assign s_axi_rdata[28] = \ ; @@ -1954,65 +1296,44 @@ module Arty_Z7_20_axi_gpio_shield_1_0_axi_gpio assign s_axi_rresp[1] = \ ; assign s_axi_rresp[0] = \ ; Arty_Z7_20_axi_gpio_shield_1_0_axi_lite_ipif AXI_LITE_IPIF_I - (.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ), - .D({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3],DBus_Reg[4],DBus_Reg[5],DBus_Reg[6],DBus_Reg[7],DBus_Reg[8],DBus_Reg[9],DBus_Reg[10],DBus_Reg[11],DBus_Reg[12],DBus_Reg[13]}), - .E(AXI_LITE_IPIF_I_n_36), + (.D({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3],DBus_Reg[4],DBus_Reg[5],DBus_Reg[6],DBus_Reg[7],DBus_Reg[8],DBus_Reg[9],DBus_Reg[10],DBus_Reg[11],DBus_Reg[12],DBus_Reg[13]}), + .E(AXI_LITE_IPIF_I_n_6), .GPIO_DBus_i(GPIO_DBus_i), .GPIO_xferAck_i(GPIO_xferAck_i), - .\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg (AXI_LITE_IPIF_I_n_45), - .\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg (AXI_LITE_IPIF_I_n_47), - .\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28] (AXI_LITE_IPIF_I_n_25), - .\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29] (AXI_LITE_IPIF_I_n_24), - .\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30] (AXI_LITE_IPIF_I_n_23), + .\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[18] (AXI_LITE_IPIF_I_n_37), + .\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28] (AXI_LITE_IPIF_I_n_19), + .\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29] (AXI_LITE_IPIF_I_n_20), + .\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30] (AXI_LITE_IPIF_I_n_21), .\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[31] (AXI_LITE_IPIF_I_n_22), - .\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[19] (AXI_LITE_IPIF_I_n_34), - .\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[20] (AXI_LITE_IPIF_I_n_33), - .\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[21] (AXI_LITE_IPIF_I_n_32), - .\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[22] (AXI_LITE_IPIF_I_n_31), - .\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[23] (AXI_LITE_IPIF_I_n_30), - .\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[24] (AXI_LITE_IPIF_I_n_29), - .\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25] (AXI_LITE_IPIF_I_n_28), - .\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26] (AXI_LITE_IPIF_I_n_27), - .\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27] (AXI_LITE_IPIF_I_n_26), - .\Not_Dual.gpio_Data_Out_reg[0] (AXI_LITE_IPIF_I_n_37), + .\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[19] (AXI_LITE_IPIF_I_n_10), + .\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[20] (AXI_LITE_IPIF_I_n_11), + .\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[21] (AXI_LITE_IPIF_I_n_12), + .\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[22] (AXI_LITE_IPIF_I_n_13), + .\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[23] (AXI_LITE_IPIF_I_n_14), + .\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[24] (AXI_LITE_IPIF_I_n_15), + .\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25] (AXI_LITE_IPIF_I_n_16), + .\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26] (AXI_LITE_IPIF_I_n_17), + .\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27] (AXI_LITE_IPIF_I_n_18), + .\Not_Dual.gpio_OE_reg[0] (AXI_LITE_IPIF_I_n_7), .Q({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3],gpio_Data_In[4],gpio_Data_In[5],gpio_Data_In[6],gpio_Data_In[7],gpio_Data_In[8],gpio_Data_In[9],gpio_Data_In[10],gpio_Data_In[11],gpio_Data_In[12],gpio_Data_In[13]}), - .Read_Reg_Rst(Read_Reg_Rst), .bus2ip_cs(bus2ip_cs), .bus2ip_reset(bus2ip_reset), .bus2ip_rnw(bus2ip_rnw), .gpio_io_t(gpio_io_t), .gpio_xferAck_Reg(gpio_xferAck_Reg), - .interrupt_wrce_strb(interrupt_wrce_strb), - .intr2bus_rdack0(intr2bus_rdack0), - .intr_rd_ce_or_reduce(intr_rd_ce_or_reduce), - .intr_wr_ce_or_reduce(intr_wr_ce_or_reduce), - .ip2Bus_RdAck_intr_reg_hole_d1(ip2Bus_RdAck_intr_reg_hole_d1), - .ip2Bus_WrAck_intr_reg_hole_d1(ip2Bus_WrAck_intr_reg_hole_d1), - .ip2bus_data(ip2bus_data[31]), - .\ip2bus_data_i_D1_reg[0] ({p_0_out,ip2bus_data_i}), - .\ip2bus_data_i_D1_reg[0]_0 ({ip2bus_data_i_D1[0],ip2bus_data_i_D1[18],ip2bus_data_i_D1[19],ip2bus_data_i_D1[20],ip2bus_data_i_D1[21],ip2bus_data_i_D1[22],ip2bus_data_i_D1[23],ip2bus_data_i_D1[24],ip2bus_data_i_D1[25],ip2bus_data_i_D1[26],ip2bus_data_i_D1[27],ip2bus_data_i_D1[28],ip2bus_data_i_D1[29],ip2bus_data_i_D1[30],ip2bus_data_i_D1[31]}), + .\ip2bus_data_i_D1_reg[18] ({ip2bus_data_i_D1[18],ip2bus_data_i_D1[19],ip2bus_data_i_D1[20],ip2bus_data_i_D1[21],ip2bus_data_i_D1[22],ip2bus_data_i_D1[23],ip2bus_data_i_D1[24],ip2bus_data_i_D1[25],ip2bus_data_i_D1[26],ip2bus_data_i_D1[27],ip2bus_data_i_D1[28],ip2bus_data_i_D1[29],ip2bus_data_i_D1[30],ip2bus_data_i_D1[31]}), .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1), .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1), - .\ip_irpt_enable_reg_reg[0] (AXI_LITE_IPIF_I_n_49), - .ipif_glbl_irpt_enable_reg_reg(AXI_LITE_IPIF_I_n_50), - .irpt_rdack(irpt_rdack), - .irpt_rdack_d1(irpt_rdack_d1), - .irpt_wrack(irpt_wrack), - .irpt_wrack_d1(irpt_wrack_d1), - .p_0_in(p_0_in), - .p_1_in(p_1_in), - .p_3_in(p_3_in), - .p_8_in(\I_SLAVE_ATTACHMENT/I_DECODER/p_8_in ), .s_axi_aclk(s_axi_aclk), - .s_axi_araddr(s_axi_araddr[8:2]), + .s_axi_araddr({s_axi_araddr[8],s_axi_araddr[3:2]}), .s_axi_aresetn(s_axi_aresetn), .s_axi_arready(s_axi_arready), .s_axi_arvalid(s_axi_arvalid), - .s_axi_awaddr(s_axi_awaddr[8:2]), + .s_axi_awaddr({s_axi_awaddr[8],s_axi_awaddr[3:2]}), .s_axi_awvalid(s_axi_awvalid), .s_axi_bready(s_axi_bready), .s_axi_bvalid(s_axi_bvalid), - .s_axi_rdata({\^s_axi_rdata [31],\^s_axi_rdata [13:0]}), + .s_axi_rdata(\^s_axi_rdata ), .s_axi_rready(s_axi_rready), .s_axi_rvalid(s_axi_rvalid), .s_axi_wdata({s_axi_wdata[31:18],s_axi_wdata[13:0]}), @@ -2020,111 +1341,40 @@ module Arty_Z7_20_axi_gpio_shield_1_0_axi_gpio .s_axi_wvalid(s_axi_wvalid)); GND GND (.G(\ )); - Arty_Z7_20_axi_gpio_shield_1_0_interrupt_control \INTR_CTRLR_GEN.INTERRUPT_CONTROL_I - (.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ), - .\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] (AXI_LITE_IPIF_I_n_50), - .\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] (AXI_LITE_IPIF_I_n_49), - .GPIO_intr(GPIO_intr), + VCC VCC + (.P(\ )); + Arty_Z7_20_axi_gpio_shield_1_0_GPIO_Core gpio_core_1 + (.D({ip2bus_data[18],ip2bus_data[19],ip2bus_data[20],ip2bus_data[21],ip2bus_data[22],ip2bus_data[23],ip2bus_data[24],ip2bus_data[25],ip2bus_data[26],ip2bus_data[27],ip2bus_data[28],ip2bus_data[29],ip2bus_data[30],ip2bus_data[31]}), + .E(AXI_LITE_IPIF_I_n_6), + .GPIO_DBus_i(GPIO_DBus_i), .GPIO_xferAck_i(GPIO_xferAck_i), - .IP2INTC_Irpt_i(IP2INTC_Irpt_i), - .bus2ip_reset(bus2ip_reset), + .\MEM_DECODE_GEN[0].cs_out_i_reg[0] ({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3],DBus_Reg[4],DBus_Reg[5],DBus_Reg[6],DBus_Reg[7],DBus_Reg[8],DBus_Reg[9],DBus_Reg[10],DBus_Reg[11],DBus_Reg[12],DBus_Reg[13]}), + .\Not_Dual.gpio_Data_In_reg[10]_0 (AXI_LITE_IPIF_I_n_19), + .\Not_Dual.gpio_Data_In_reg[11]_0 (AXI_LITE_IPIF_I_n_20), + .\Not_Dual.gpio_Data_In_reg[12]_0 (AXI_LITE_IPIF_I_n_21), + .\Not_Dual.gpio_Data_In_reg[13]_0 (AXI_LITE_IPIF_I_n_22), + .\Not_Dual.gpio_Data_In_reg[1]_0 (AXI_LITE_IPIF_I_n_10), + .\Not_Dual.gpio_Data_In_reg[2]_0 (AXI_LITE_IPIF_I_n_11), + .\Not_Dual.gpio_Data_In_reg[3]_0 (AXI_LITE_IPIF_I_n_12), + .\Not_Dual.gpio_Data_In_reg[4]_0 (AXI_LITE_IPIF_I_n_13), + .\Not_Dual.gpio_Data_In_reg[5]_0 (AXI_LITE_IPIF_I_n_14), + .\Not_Dual.gpio_Data_In_reg[6]_0 (AXI_LITE_IPIF_I_n_15), + .\Not_Dual.gpio_Data_In_reg[7]_0 (AXI_LITE_IPIF_I_n_16), + .\Not_Dual.gpio_Data_In_reg[8]_0 (AXI_LITE_IPIF_I_n_17), + .\Not_Dual.gpio_Data_In_reg[9]_0 (AXI_LITE_IPIF_I_n_18), + .Q({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3],gpio_Data_In[4],gpio_Data_In[5],gpio_Data_In[6],gpio_Data_In[7],gpio_Data_In[8],gpio_Data_In[9],gpio_Data_In[10],gpio_Data_In[11],gpio_Data_In[12],gpio_Data_In[13]}), + .SS(bus2ip_reset), + .bus2ip_cs(bus2ip_cs), .bus2ip_rnw(bus2ip_rnw), - .interrupt_wrce_strb(interrupt_wrce_strb), - .intr2bus_rdack0(intr2bus_rdack0), - .ip2Bus_RdAck_intr_reg_hole(ip2Bus_RdAck_intr_reg_hole), - .ip2Bus_WrAck_intr_reg_hole(ip2Bus_WrAck_intr_reg_hole), + .bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_37), + .gpio_io_i(gpio_io_i), + .gpio_io_o(gpio_io_o), + .gpio_io_t(gpio_io_t), + .gpio_xferAck_Reg(gpio_xferAck_Reg), .ip2bus_rdack_i(ip2bus_rdack_i), - .ip2bus_wrack_i(ip2bus_wrack_i), - .irpt_rdack(irpt_rdack), - .irpt_rdack_d1(irpt_rdack_d1), - .irpt_wrack(irpt_wrack), - .irpt_wrack_d1(irpt_wrack_d1), - .p_0_in(p_0_in), - .p_1_in(p_1_in), - .p_3_in(p_3_in), - .p_8_in(\I_SLAVE_ATTACHMENT/I_DECODER/p_8_in ), - .s_axi_aclk(s_axi_aclk), - .s_axi_wdata(s_axi_wdata[0])); - FDRE \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(intr_rd_ce_or_reduce), - .Q(ip2Bus_RdAck_intr_reg_hole_d1), - .R(bus2ip_reset)); - FDRE \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(AXI_LITE_IPIF_I_n_45), - .Q(ip2Bus_RdAck_intr_reg_hole), - .R(bus2ip_reset)); - FDRE \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(intr_wr_ce_or_reduce), - .Q(ip2Bus_WrAck_intr_reg_hole_d1), - .R(bus2ip_reset)); - FDRE \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(AXI_LITE_IPIF_I_n_47), - .Q(ip2Bus_WrAck_intr_reg_hole), - .R(bus2ip_reset)); - (* sigis = "INTR_LEVEL_HIGH" *) - FDRE \INTR_CTRLR_GEN.ip2intc_irpt_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(IP2INTC_Irpt_i), - .Q(ip2intc_irpt), - .R(bus2ip_reset)); - VCC VCC - (.P(\ )); - LUT1 #( - .INIT(2'h1)) - bus2ip_reset_i_1 - (.I0(s_axi_aresetn), - .O(bus2ip_reset_i_1_n_0)); - FDRE bus2ip_reset_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(bus2ip_reset_i_1_n_0), - .Q(bus2ip_reset), - .R(1'b0)); - Arty_Z7_20_axi_gpio_shield_1_0_GPIO_Core gpio_core_1 - (.D({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3],DBus_Reg[4],DBus_Reg[5],DBus_Reg[6],DBus_Reg[7],DBus_Reg[8],DBus_Reg[9],DBus_Reg[10],DBus_Reg[11],DBus_Reg[12],DBus_Reg[13]}), - .E(AXI_LITE_IPIF_I_n_37), - .GPIO_DBus_i(GPIO_DBus_i), - .GPIO_intr(GPIO_intr), - .GPIO_xferAck_i(GPIO_xferAck_i), - .\Not_Dual.gpio_OE_reg[10]_0 (AXI_LITE_IPIF_I_n_25), - .\Not_Dual.gpio_OE_reg[11]_0 (AXI_LITE_IPIF_I_n_24), - .\Not_Dual.gpio_OE_reg[12]_0 (AXI_LITE_IPIF_I_n_23), - .\Not_Dual.gpio_OE_reg[13]_0 (AXI_LITE_IPIF_I_n_22), - .\Not_Dual.gpio_OE_reg[1]_0 (AXI_LITE_IPIF_I_n_34), - .\Not_Dual.gpio_OE_reg[2]_0 (AXI_LITE_IPIF_I_n_33), - .\Not_Dual.gpio_OE_reg[3]_0 (AXI_LITE_IPIF_I_n_32), - .\Not_Dual.gpio_OE_reg[4]_0 (AXI_LITE_IPIF_I_n_31), - .\Not_Dual.gpio_OE_reg[5]_0 (AXI_LITE_IPIF_I_n_30), - .\Not_Dual.gpio_OE_reg[6]_0 (AXI_LITE_IPIF_I_n_29), - .\Not_Dual.gpio_OE_reg[7]_0 (AXI_LITE_IPIF_I_n_28), - .\Not_Dual.gpio_OE_reg[8]_0 (AXI_LITE_IPIF_I_n_27), - .\Not_Dual.gpio_OE_reg[9]_0 (AXI_LITE_IPIF_I_n_26), - .Q({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3],gpio_Data_In[4],gpio_Data_In[5],gpio_Data_In[6],gpio_Data_In[7],gpio_Data_In[8],gpio_Data_In[9],gpio_Data_In[10],gpio_Data_In[11],gpio_Data_In[12],gpio_Data_In[13]}), - .Read_Reg_Rst(Read_Reg_Rst), - .bus2ip_cs(bus2ip_cs), - .bus2ip_reset(bus2ip_reset), - .bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_36), - .gpio_io_i(gpio_io_i), - .gpio_io_o(gpio_io_o), - .gpio_io_t(gpio_io_t), - .gpio_xferAck_Reg(gpio_xferAck_Reg), - .ip2bus_data({ip2bus_data[18],ip2bus_data[19],ip2bus_data[20],ip2bus_data[21],ip2bus_data[22],ip2bus_data[23],ip2bus_data[24],ip2bus_data[25],ip2bus_data[26],ip2bus_data[27],ip2bus_data[28],ip2bus_data[29],ip2bus_data[30],ip2bus_data[31]}), + .ip2bus_wrack_i_D1_reg(gpio_core_1_n_17), + .rst_reg(AXI_LITE_IPIF_I_n_7), .s_axi_aclk(s_axi_aclk)); - FDRE \ip2bus_data_i_D1_reg[0] - (.C(s_axi_aclk), - .CE(1'b1), - .D(p_0_out), - .Q(ip2bus_data_i_D1[0]), - .R(bus2ip_reset)); FDRE \ip2bus_data_i_D1_reg[18] (.C(s_axi_aclk), .CE(1'b1), @@ -2206,7 +1456,7 @@ module Arty_Z7_20_axi_gpio_shield_1_0_axi_gpio FDRE \ip2bus_data_i_D1_reg[31] (.C(s_axi_aclk), .CE(1'b1), - .D(ip2bus_data_i), + .D(ip2bus_data[31]), .Q(ip2bus_data_i_D1[31]), .R(bus2ip_reset)); FDRE ip2bus_rdack_i_D1_reg @@ -2218,149 +1468,105 @@ module Arty_Z7_20_axi_gpio_shield_1_0_axi_gpio FDRE ip2bus_wrack_i_D1_reg (.C(s_axi_aclk), .CE(1'b1), - .D(ip2bus_wrack_i), + .D(gpio_core_1_n_17), .Q(ip2bus_wrack_i_D1), .R(bus2ip_reset)); endmodule (* ORIG_REF_NAME = "axi_lite_ipif" *) module Arty_Z7_20_axi_gpio_shield_1_0_axi_lite_ipif - (p_8_in, + (bus2ip_reset, bus2ip_rnw, bus2ip_cs, - Bus_RNW_reg, s_axi_rvalid, s_axi_bvalid, s_axi_arready, + E, + \Not_Dual.gpio_OE_reg[0] , s_axi_wready, - D, - \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[31] , - \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30] , - \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29] , - \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28] , - \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27] , - \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26] , - \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25] , - \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[24] , - \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[23] , - \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[22] , - \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[21] , - \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[20] , - \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[19] , GPIO_DBus_i, - E, - \Not_Dual.gpio_Data_Out_reg[0] , - \ip2bus_data_i_D1_reg[0] , - intr2bus_rdack0, - irpt_rdack, - irpt_wrack, - interrupt_wrce_strb, - Read_Reg_Rst, - \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg , - intr_rd_ce_or_reduce, - \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg , - intr_wr_ce_or_reduce, - \ip_irpt_enable_reg_reg[0] , - ipif_glbl_irpt_enable_reg_reg, + \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[19] , + \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[20] , + \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[21] , + \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[22] , + \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[23] , + \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[24] , + \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25] , + \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26] , + \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27] , + \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28] , + \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29] , + \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30] , + \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[31] , + D, + \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[18] , s_axi_rdata, - bus2ip_reset, s_axi_aclk, s_axi_arvalid, + s_axi_awvalid, + s_axi_wvalid, + s_axi_araddr, + s_axi_awaddr, s_axi_aresetn, + s_axi_rready, + s_axi_bready, ip2bus_rdack_i_D1, ip2bus_wrack_i_D1, - s_axi_bready, - s_axi_rready, - s_axi_awaddr, - s_axi_araddr, - s_axi_awvalid, - s_axi_wvalid, - s_axi_wdata, - gpio_io_t, Q, - p_0_in, - irpt_rdack_d1, - irpt_wrack_d1, - ip2bus_data, - p_3_in, - p_1_in, - GPIO_xferAck_i, + gpio_io_t, + s_axi_wdata, gpio_xferAck_Reg, - ip2Bus_RdAck_intr_reg_hole_d1, - ip2Bus_WrAck_intr_reg_hole_d1, - \ip2bus_data_i_D1_reg[0]_0 ); - output p_8_in; + GPIO_xferAck_i, + \ip2bus_data_i_D1_reg[18] ); + output bus2ip_reset; output bus2ip_rnw; - output [0:0]bus2ip_cs; - output Bus_RNW_reg; + output bus2ip_cs; output s_axi_rvalid; output s_axi_bvalid; output s_axi_arready; + output [0:0]E; + output [0:0]\Not_Dual.gpio_OE_reg[0] ; output s_axi_wready; - output [13:0]D; - output \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[31] ; - output \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30] ; - output \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29] ; - output \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28] ; - output \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27] ; - output \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26] ; - output \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25] ; - output \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[24] ; - output \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[23] ; - output \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[22] ; - output \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[21] ; - output \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[20] ; - output \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[19] ; output [0:0]GPIO_DBus_i; - output [0:0]E; - output [0:0]\Not_Dual.gpio_Data_Out_reg[0] ; - output [1:0]\ip2bus_data_i_D1_reg[0] ; - output intr2bus_rdack0; - output irpt_rdack; - output irpt_wrack; - output interrupt_wrce_strb; - output Read_Reg_Rst; - output \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ; - output intr_rd_ce_or_reduce; - output \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ; - output intr_wr_ce_or_reduce; - output \ip_irpt_enable_reg_reg[0] ; - output ipif_glbl_irpt_enable_reg_reg; - output [14:0]s_axi_rdata; - input bus2ip_reset; + output \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[19] ; + output \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[20] ; + output \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[21] ; + output \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[22] ; + output \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[23] ; + output \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[24] ; + output \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25] ; + output \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26] ; + output \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27] ; + output \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28] ; + output \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29] ; + output \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30] ; + output \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[31] ; + output [13:0]D; + output \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[18] ; + output [13:0]s_axi_rdata; input s_axi_aclk; input s_axi_arvalid; + input s_axi_awvalid; + input s_axi_wvalid; + input [2:0]s_axi_araddr; + input [2:0]s_axi_awaddr; input s_axi_aresetn; + input s_axi_rready; + input s_axi_bready; input ip2bus_rdack_i_D1; input ip2bus_wrack_i_D1; - input s_axi_bready; - input s_axi_rready; - input [6:0]s_axi_awaddr; - input [6:0]s_axi_araddr; - input s_axi_awvalid; - input s_axi_wvalid; - input [27:0]s_axi_wdata; - input [13:0]gpio_io_t; input [13:0]Q; - input [0:0]p_0_in; - input irpt_rdack_d1; - input irpt_wrack_d1; - input [0:0]ip2bus_data; - input [0:0]p_3_in; - input [0:0]p_1_in; - input GPIO_xferAck_i; + input [13:0]gpio_io_t; + input [27:0]s_axi_wdata; input gpio_xferAck_Reg; - input ip2Bus_RdAck_intr_reg_hole_d1; - input ip2Bus_WrAck_intr_reg_hole_d1; - input [14:0]\ip2bus_data_i_D1_reg[0]_0 ; + input GPIO_xferAck_i; + input [13:0]\ip2bus_data_i_D1_reg[18] ; - wire Bus_RNW_reg; wire [13:0]D; wire [0:0]E; wire [0:0]GPIO_DBus_i; wire GPIO_xferAck_i; - wire \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ; - wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ; + wire \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[18] ; wire \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28] ; wire \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29] ; wire \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30] ; @@ -2374,45 +1580,26 @@ module Arty_Z7_20_axi_gpio_shield_1_0_axi_lite_ipif wire \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25] ; wire \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26] ; wire \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27] ; - wire [0:0]\Not_Dual.gpio_Data_Out_reg[0] ; + wire [0:0]\Not_Dual.gpio_OE_reg[0] ; wire [13:0]Q; - wire Read_Reg_Rst; - wire [0:0]bus2ip_cs; + wire bus2ip_cs; wire bus2ip_reset; wire bus2ip_rnw; wire [13:0]gpio_io_t; wire gpio_xferAck_Reg; - wire interrupt_wrce_strb; - wire intr2bus_rdack0; - wire intr_rd_ce_or_reduce; - wire intr_wr_ce_or_reduce; - wire ip2Bus_RdAck_intr_reg_hole_d1; - wire ip2Bus_WrAck_intr_reg_hole_d1; - wire [0:0]ip2bus_data; - wire [1:0]\ip2bus_data_i_D1_reg[0] ; - wire [14:0]\ip2bus_data_i_D1_reg[0]_0 ; + wire [13:0]\ip2bus_data_i_D1_reg[18] ; wire ip2bus_rdack_i_D1; wire ip2bus_wrack_i_D1; - wire \ip_irpt_enable_reg_reg[0] ; - wire ipif_glbl_irpt_enable_reg_reg; - wire irpt_rdack; - wire irpt_rdack_d1; - wire irpt_wrack; - wire irpt_wrack_d1; - wire [0:0]p_0_in; - wire [0:0]p_1_in; - wire [0:0]p_3_in; - wire p_8_in; wire s_axi_aclk; - wire [6:0]s_axi_araddr; + wire [2:0]s_axi_araddr; wire s_axi_aresetn; wire s_axi_arready; wire s_axi_arvalid; - wire [6:0]s_axi_awaddr; + wire [2:0]s_axi_awaddr; wire s_axi_awvalid; wire s_axi_bready; wire s_axi_bvalid; - wire [14:0]s_axi_rdata; + wire [13:0]s_axi_rdata; wire s_axi_rready; wire s_axi_rvalid; wire [27:0]s_axi_wdata; @@ -2424,8 +1611,8 @@ module Arty_Z7_20_axi_gpio_shield_1_0_axi_lite_ipif .E(E), .GPIO_DBus_i(GPIO_DBus_i), .GPIO_xferAck_i(GPIO_xferAck_i), - .\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg (\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ), - .\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg (\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ), + .\MEM_DECODE_GEN[0].cs_out_i_reg[0] (bus2ip_cs), + .\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[18] (\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[18] ), .\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28] (\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28] ), .\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29] (\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29] ), .\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30] (\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30] ), @@ -2439,36 +1626,15 @@ module Arty_Z7_20_axi_gpio_shield_1_0_axi_lite_ipif .\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25] (\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25] ), .\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26] (\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26] ), .\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27] (\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27] ), - .\Not_Dual.gpio_Data_Out_reg[0] (\Not_Dual.gpio_Data_Out_reg[0] ), - .\Not_Dual.gpio_Data_Out_reg[13] (bus2ip_cs), - .\Not_Dual.gpio_OE_reg[0] (bus2ip_rnw), + .\Not_Dual.gpio_Data_Out_reg[0] (bus2ip_rnw), + .\Not_Dual.gpio_OE_reg[0] (\Not_Dual.gpio_OE_reg[0] ), .Q(Q), - .Read_Reg_Rst(Read_Reg_Rst), - .bus2ip_reset(bus2ip_reset), + .SR(bus2ip_reset), .gpio_io_t(gpio_io_t), .gpio_xferAck_Reg(gpio_xferAck_Reg), - .interrupt_wrce_strb(interrupt_wrce_strb), - .intr2bus_rdack0(intr2bus_rdack0), - .intr_rd_ce_or_reduce(intr_rd_ce_or_reduce), - .intr_wr_ce_or_reduce(intr_wr_ce_or_reduce), - .ip2Bus_RdAck_intr_reg_hole_d1(ip2Bus_RdAck_intr_reg_hole_d1), - .ip2Bus_WrAck_intr_reg_hole_d1(ip2Bus_WrAck_intr_reg_hole_d1), - .ip2bus_data(ip2bus_data), - .\ip2bus_data_i_D1_reg[0] (p_8_in), - .\ip2bus_data_i_D1_reg[0]_0 (\ip2bus_data_i_D1_reg[0] ), - .\ip2bus_data_i_D1_reg[0]_1 (\ip2bus_data_i_D1_reg[0]_0 ), + .\ip2bus_data_i_D1_reg[18] (\ip2bus_data_i_D1_reg[18] ), .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1), .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1), - .\ip_irpt_enable_reg_reg[0] (Bus_RNW_reg), - .\ip_irpt_enable_reg_reg[0]_0 (\ip_irpt_enable_reg_reg[0] ), - .ipif_glbl_irpt_enable_reg_reg(ipif_glbl_irpt_enable_reg_reg), - .irpt_rdack(irpt_rdack), - .irpt_rdack_d1(irpt_rdack_d1), - .irpt_wrack(irpt_wrack), - .irpt_wrack_d1(irpt_wrack_d1), - .p_0_in(p_0_in), - .p_1_in(p_1_in), - .p_3_in(p_3_in), .s_axi_aclk(s_axi_aclk), .s_axi_araddr(s_axi_araddr), .s_axi_aresetn(s_axi_aresetn), @@ -2488,19 +1654,13 @@ endmodule (* ORIG_REF_NAME = "cdc_sync" *) module Arty_Z7_20_axi_gpio_shield_1_0_cdc_sync - (D, - scndry_vect_out, - Q, + (scndry_vect_out, gpio_io_i, s_axi_aclk); - output [13:0]D; output [13:0]scndry_vect_out; - input [13:0]Q; input [13:0]gpio_io_i; input s_axi_aclk; - wire [13:0]D; - wire [13:0]Q; wire [13:0]gpio_io_i; wire s_axi_aclk; wire s_level_out_bus_d1_cdc_to_0; @@ -3163,407 +2323,104 @@ module Arty_Z7_20_axi_gpio_shield_1_0_cdc_sync .D(gpio_io_i[9]), .Q(s_level_out_bus_d1_cdc_to_9), .R(1'b0)); - LUT2 #( - .INIT(4'h6)) - \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[0]_i_1 - (.I0(Q[13]), - .I1(scndry_vect_out[13]), - .O(D[13])); - LUT2 #( - .INIT(4'h6)) - \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[10]_i_1 - (.I0(Q[3]), - .I1(scndry_vect_out[3]), - .O(D[3])); - LUT2 #( - .INIT(4'h6)) - \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[11]_i_1 - (.I0(Q[2]), - .I1(scndry_vect_out[2]), - .O(D[2])); - LUT2 #( - .INIT(4'h6)) - \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[12]_i_1 - (.I0(Q[1]), - .I1(scndry_vect_out[1]), - .O(D[1])); - LUT2 #( - .INIT(4'h6)) - \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[13]_i_1 - (.I0(Q[0]), - .I1(scndry_vect_out[0]), - .O(D[0])); - LUT2 #( - .INIT(4'h6)) - \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[1]_i_1 - (.I0(Q[12]), - .I1(scndry_vect_out[12]), - .O(D[12])); - LUT2 #( - .INIT(4'h6)) - \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[2]_i_1 - (.I0(Q[11]), - .I1(scndry_vect_out[11]), - .O(D[11])); - LUT2 #( - .INIT(4'h6)) - \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[3]_i_1 - (.I0(Q[10]), - .I1(scndry_vect_out[10]), - .O(D[10])); - LUT2 #( - .INIT(4'h6)) - \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[4]_i_1 - (.I0(Q[9]), - .I1(scndry_vect_out[9]), - .O(D[9])); - LUT2 #( - .INIT(4'h6)) - \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[5]_i_1 - (.I0(Q[8]), - .I1(scndry_vect_out[8]), - .O(D[8])); - LUT2 #( - .INIT(4'h6)) - \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[6]_i_1 - (.I0(Q[7]), - .I1(scndry_vect_out[7]), - .O(D[7])); - LUT2 #( - .INIT(4'h6)) - \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[7]_i_1 - (.I0(Q[6]), - .I1(scndry_vect_out[6]), - .O(D[6])); - LUT2 #( - .INIT(4'h6)) - \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[8]_i_1 - (.I0(Q[5]), - .I1(scndry_vect_out[5]), - .O(D[5])); - LUT2 #( - .INIT(4'h6)) - \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[9]_i_1 - (.I0(Q[4]), - .I1(scndry_vect_out[4]), - .O(D[4])); -endmodule - -(* ORIG_REF_NAME = "interrupt_control" *) -module Arty_Z7_20_axi_gpio_shield_1_0_interrupt_control - (irpt_wrack_d1, - p_3_in, - irpt_rdack_d1, - p_1_in, - p_0_in, - IP2INTC_Irpt_i, - ip2bus_wrack_i, - ip2bus_rdack_i, - bus2ip_reset, - irpt_wrack, - s_axi_aclk, - GPIO_intr, - interrupt_wrce_strb, - irpt_rdack, - intr2bus_rdack0, - \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] , - \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] , - p_8_in, - s_axi_wdata, - Bus_RNW_reg, - ip2Bus_WrAck_intr_reg_hole, - bus2ip_rnw, - GPIO_xferAck_i, - ip2Bus_RdAck_intr_reg_hole); - output irpt_wrack_d1; - output [0:0]p_3_in; - output irpt_rdack_d1; - output [0:0]p_1_in; - output [0:0]p_0_in; - output IP2INTC_Irpt_i; - output ip2bus_wrack_i; - output ip2bus_rdack_i; - input bus2ip_reset; - input irpt_wrack; - input s_axi_aclk; - input GPIO_intr; - input interrupt_wrce_strb; - input irpt_rdack; - input intr2bus_rdack0; - input \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] ; - input \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ; - input p_8_in; - input [0:0]s_axi_wdata; - input Bus_RNW_reg; - input ip2Bus_WrAck_intr_reg_hole; - input bus2ip_rnw; - input GPIO_xferAck_i; - input ip2Bus_RdAck_intr_reg_hole; - - wire Bus_RNW_reg; - wire \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ; - wire \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] ; - wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0 ; - wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0 ; - wire GPIO_intr; - wire GPIO_xferAck_i; - wire IP2INTC_Irpt_i; - wire bus2ip_reset; - wire bus2ip_rnw; - wire interrupt_wrce_strb; - wire intr2bus_rdack; - wire intr2bus_rdack0; - wire intr2bus_wrack; - wire ip2Bus_RdAck_intr_reg_hole; - wire ip2Bus_WrAck_intr_reg_hole; - wire ip2bus_rdack_i; - wire ip2bus_wrack_i; - wire irpt_dly1; - wire irpt_dly2; - wire irpt_rdack; - wire irpt_rdack_d1; - wire irpt_wrack; - wire irpt_wrack_d1; - wire [0:0]p_0_in; - wire [0:0]p_1_in; - wire [0:0]p_3_in; - wire p_8_in; - wire s_axi_aclk; - wire [0:0]s_axi_wdata; - - FDSE \DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly1_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(GPIO_intr), - .Q(irpt_dly1), - .S(bus2ip_reset)); - FDSE \DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly2_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(irpt_dly1), - .Q(irpt_dly2), - .S(bus2ip_reset)); - LUT6 #( - .INIT(64'hF4F4F4F44FF4F4F4)) - \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1 - (.I0(irpt_dly2), - .I1(irpt_dly1), - .I2(p_3_in), - .I3(p_8_in), - .I4(s_axi_wdata), - .I5(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0 ), - .O(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0 )); - LUT2 #( - .INIT(4'hE)) - \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2 - (.I0(irpt_wrack_d1), - .I1(Bus_RNW_reg), - .O(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0 )); - FDRE \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] - (.C(s_axi_aclk), - .CE(1'b1), - .D(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0 ), - .Q(p_3_in), - .R(bus2ip_reset)); - LUT3 #( - .INIT(8'h80)) - \INTR_CTRLR_GEN.ip2intc_irpt_i_1 - (.I0(p_3_in), - .I1(p_1_in), - .I2(p_0_in), - .O(IP2INTC_Irpt_i)); - FDRE intr2bus_rdack_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(intr2bus_rdack0), - .Q(intr2bus_rdack), - .R(bus2ip_reset)); - FDRE intr2bus_wrack_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(interrupt_wrce_strb), - .Q(intr2bus_wrack), - .R(bus2ip_reset)); - LUT4 #( - .INIT(16'hFEEE)) - ip2bus_rdack_i_D1_i_1 - (.I0(ip2Bus_RdAck_intr_reg_hole), - .I1(intr2bus_rdack), - .I2(bus2ip_rnw), - .I3(GPIO_xferAck_i), - .O(ip2bus_rdack_i)); - LUT4 #( - .INIT(16'hEFEE)) - ip2bus_wrack_i_D1_i_1 - (.I0(ip2Bus_WrAck_intr_reg_hole), - .I1(intr2bus_wrack), - .I2(bus2ip_rnw), - .I3(GPIO_xferAck_i), - .O(ip2bus_wrack_i)); - FDRE \ip_irpt_enable_reg_reg[0] - (.C(s_axi_aclk), - .CE(1'b1), - .D(\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] ), - .Q(p_1_in), - .R(bus2ip_reset)); - FDRE ipif_glbl_irpt_enable_reg_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ), - .Q(p_0_in), - .R(bus2ip_reset)); - FDRE irpt_rdack_d1_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(irpt_rdack), - .Q(irpt_rdack_d1), - .R(bus2ip_reset)); - FDRE irpt_wrack_d1_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(irpt_wrack), - .Q(irpt_wrack_d1), - .R(bus2ip_reset)); endmodule (* ORIG_REF_NAME = "slave_attachment" *) module Arty_Z7_20_axi_gpio_shield_1_0_slave_attachment - (\ip2bus_data_i_D1_reg[0] , - \Not_Dual.gpio_OE_reg[0] , - \Not_Dual.gpio_Data_Out_reg[13] , - \ip_irpt_enable_reg_reg[0] , + (SR, + \Not_Dual.gpio_Data_Out_reg[0] , + \MEM_DECODE_GEN[0].cs_out_i_reg[0] , s_axi_rvalid, s_axi_bvalid, s_axi_arready, + E, + \Not_Dual.gpio_OE_reg[0] , s_axi_wready, - D, - \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[31] , - \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30] , - \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29] , - \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28] , - \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27] , - \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26] , - \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25] , - \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[24] , - \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[23] , - \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[22] , - \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[21] , - \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[20] , - \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[19] , GPIO_DBus_i, - E, - \Not_Dual.gpio_Data_Out_reg[0] , - \ip2bus_data_i_D1_reg[0]_0 , - intr2bus_rdack0, - irpt_rdack, - irpt_wrack, - interrupt_wrce_strb, - Read_Reg_Rst, - \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg , - intr_rd_ce_or_reduce, - \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg , - intr_wr_ce_or_reduce, - \ip_irpt_enable_reg_reg[0]_0 , - ipif_glbl_irpt_enable_reg_reg, + \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[19] , + \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[20] , + \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[21] , + \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[22] , + \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[23] , + \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[24] , + \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25] , + \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26] , + \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27] , + \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28] , + \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29] , + \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30] , + \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[31] , + D, + \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[18] , s_axi_rdata, - bus2ip_reset, s_axi_aclk, s_axi_arvalid, + s_axi_awvalid, + s_axi_wvalid, + s_axi_araddr, + s_axi_awaddr, s_axi_aresetn, + s_axi_rready, + s_axi_bready, ip2bus_rdack_i_D1, ip2bus_wrack_i_D1, - s_axi_bready, - s_axi_rready, - s_axi_awaddr, - s_axi_araddr, - s_axi_awvalid, - s_axi_wvalid, - s_axi_wdata, - gpio_io_t, Q, - p_0_in, - irpt_rdack_d1, - irpt_wrack_d1, - ip2bus_data, - p_3_in, - p_1_in, - GPIO_xferAck_i, + gpio_io_t, + s_axi_wdata, gpio_xferAck_Reg, - ip2Bus_RdAck_intr_reg_hole_d1, - ip2Bus_WrAck_intr_reg_hole_d1, - \ip2bus_data_i_D1_reg[0]_1 ); - output \ip2bus_data_i_D1_reg[0] ; - output \Not_Dual.gpio_OE_reg[0] ; - output \Not_Dual.gpio_Data_Out_reg[13] ; - output \ip_irpt_enable_reg_reg[0] ; + GPIO_xferAck_i, + \ip2bus_data_i_D1_reg[18] ); + output SR; + output \Not_Dual.gpio_Data_Out_reg[0] ; + output \MEM_DECODE_GEN[0].cs_out_i_reg[0] ; output s_axi_rvalid; output s_axi_bvalid; output s_axi_arready; + output [0:0]E; + output [0:0]\Not_Dual.gpio_OE_reg[0] ; output s_axi_wready; - output [13:0]D; - output \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[31] ; - output \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30] ; - output \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29] ; - output \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28] ; - output \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27] ; - output \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26] ; - output \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25] ; - output \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[24] ; - output \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[23] ; - output \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[22] ; - output \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[21] ; - output \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[20] ; - output \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[19] ; output [0:0]GPIO_DBus_i; - output [0:0]E; - output [0:0]\Not_Dual.gpio_Data_Out_reg[0] ; - output [1:0]\ip2bus_data_i_D1_reg[0]_0 ; - output intr2bus_rdack0; - output irpt_rdack; - output irpt_wrack; - output interrupt_wrce_strb; - output Read_Reg_Rst; - output \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ; - output intr_rd_ce_or_reduce; - output \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ; - output intr_wr_ce_or_reduce; - output \ip_irpt_enable_reg_reg[0]_0 ; - output ipif_glbl_irpt_enable_reg_reg; - output [14:0]s_axi_rdata; - input bus2ip_reset; + output \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[19] ; + output \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[20] ; + output \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[21] ; + output \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[22] ; + output \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[23] ; + output \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[24] ; + output \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25] ; + output \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26] ; + output \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27] ; + output \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28] ; + output \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29] ; + output \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30] ; + output \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[31] ; + output [13:0]D; + output \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[18] ; + output [13:0]s_axi_rdata; input s_axi_aclk; input s_axi_arvalid; + input s_axi_awvalid; + input s_axi_wvalid; + input [2:0]s_axi_araddr; + input [2:0]s_axi_awaddr; input s_axi_aresetn; + input s_axi_rready; + input s_axi_bready; input ip2bus_rdack_i_D1; input ip2bus_wrack_i_D1; - input s_axi_bready; - input s_axi_rready; - input [6:0]s_axi_awaddr; - input [6:0]s_axi_araddr; - input s_axi_awvalid; - input s_axi_wvalid; - input [27:0]s_axi_wdata; - input [13:0]gpio_io_t; input [13:0]Q; - input [0:0]p_0_in; - input irpt_rdack_d1; - input irpt_wrack_d1; - input [0:0]ip2bus_data; - input [0:0]p_3_in; - input [0:0]p_1_in; - input GPIO_xferAck_i; + input [13:0]gpio_io_t; + input [27:0]s_axi_wdata; input gpio_xferAck_Reg; - input ip2Bus_RdAck_intr_reg_hole_d1; - input ip2Bus_WrAck_intr_reg_hole_d1; - input [14:0]\ip2bus_data_i_D1_reg[0]_1 ; + input GPIO_xferAck_i; + input [13:0]\ip2bus_data_i_D1_reg[18] ; wire [13:0]D; wire [0:0]E; wire [0:0]GPIO_DBus_i; wire GPIO_xferAck_i; wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ; - wire \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ; - wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ; + wire \MEM_DECODE_GEN[0].cs_out_i_reg[0] ; + wire \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[18] ; wire \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28] ; wire \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29] ; wire \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30] ; @@ -3577,59 +2434,42 @@ module Arty_Z7_20_axi_gpio_shield_1_0_slave_attachment wire \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25] ; wire \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26] ; wire \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27] ; - wire [0:0]\Not_Dual.gpio_Data_Out_reg[0] ; - wire \Not_Dual.gpio_Data_Out_reg[13] ; - wire \Not_Dual.gpio_OE_reg[0] ; + wire \Not_Dual.gpio_Data_Out_reg[0] ; + wire [0:0]\Not_Dual.gpio_OE_reg[0] ; wire [13:0]Q; - wire Read_Reg_Rst; + wire SR; wire [0:6]bus2ip_addr; - wire bus2ip_reset; + wire \bus2ip_addr_i[2]_i_1_n_0 ; + wire \bus2ip_addr_i[3]_i_1_n_0 ; + wire \bus2ip_addr_i[8]_i_1_n_0 ; + wire \bus2ip_addr_i[8]_i_2_n_0 ; wire bus2ip_rnw_i06_out; wire clear; wire [13:0]gpio_io_t; wire gpio_xferAck_Reg; - wire interrupt_wrce_strb; - wire intr2bus_rdack0; - wire intr_rd_ce_or_reduce; - wire intr_wr_ce_or_reduce; - wire ip2Bus_RdAck_intr_reg_hole_d1; - wire ip2Bus_WrAck_intr_reg_hole_d1; - wire [0:0]ip2bus_data; - wire \ip2bus_data_i_D1_reg[0] ; - wire [1:0]\ip2bus_data_i_D1_reg[0]_0 ; - wire [14:0]\ip2bus_data_i_D1_reg[0]_1 ; + wire [13:0]\ip2bus_data_i_D1_reg[18] ; wire ip2bus_rdack_i_D1; wire ip2bus_wrack_i_D1; - wire \ip_irpt_enable_reg_reg[0] ; - wire \ip_irpt_enable_reg_reg[0]_0 ; - wire ipif_glbl_irpt_enable_reg_reg; - wire irpt_rdack; - wire irpt_rdack_d1; - wire irpt_wrack; - wire irpt_wrack_d1; wire is_read; wire is_read_i_1_n_0; wire is_write; wire is_write_i_1_n_0; wire is_write_reg_n_0; - wire [0:0]p_0_in; - wire [1:0]p_0_out__0; - wire [0:0]p_1_in; - wire [8:2]p_1_in__0; - wire [0:0]p_3_in; + wire [1:0]p_0_out; + wire p_1_in; wire [3:0]plusOp; wire s_axi_aclk; - wire [6:0]s_axi_araddr; + wire [2:0]s_axi_araddr; wire s_axi_aresetn; wire s_axi_arready; wire s_axi_arvalid; - wire [6:0]s_axi_awaddr; + wire [2:0]s_axi_awaddr; wire s_axi_awvalid; wire s_axi_bready; wire s_axi_bvalid; wire s_axi_bvalid_i_i_1_n_0; - wire [14:0]s_axi_rdata; - wire s_axi_rdata_i; + wire [13:0]s_axi_rdata; + wire \s_axi_rdata_i[13]_i_1_n_0 ; wire s_axi_rready; wire s_axi_rvalid; wire s_axi_rvalid_i_i_1_n_0; @@ -3639,43 +2479,43 @@ module Arty_Z7_20_axi_gpio_shield_1_0_slave_attachment wire start2; wire start2_i_1_n_0; wire [1:0]state; - wire \state[1]_i_2_n_0 ; + wire state1__2; wire \state[1]_i_3_n_0 ; - (* SOFT_HLUTNM = "soft_lutpair6" *) + (* SOFT_HLUTNM = "soft_lutpair3" *) LUT1 #( .INIT(2'h1)) \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1 (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]), .O(plusOp[0])); - (* SOFT_HLUTNM = "soft_lutpair6" *) + (* SOFT_HLUTNM = "soft_lutpair3" *) LUT2 #( .INIT(4'h6)) \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1 (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]), .I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]), .O(plusOp[1])); - (* SOFT_HLUTNM = "soft_lutpair5" *) + (* SOFT_HLUTNM = "soft_lutpair2" *) LUT3 #( .INIT(8'h78)) \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1 - (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]), - .I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]), + (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]), + .I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]), .I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]), .O(plusOp[2])); LUT2 #( .INIT(4'h9)) \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1 - (.I0(state[1]), - .I1(state[0]), + (.I0(state[0]), + .I1(state[1]), .O(clear)); - (* SOFT_HLUTNM = "soft_lutpair5" *) + (* SOFT_HLUTNM = "soft_lutpair2" *) LUT4 #( .INIT(16'h7F80)) \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2 - (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]), + (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]), .I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]), - .I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]), + .I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]), .I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]), .O(plusOp[3])); FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0] @@ -3707,8 +2547,9 @@ module Arty_Z7_20_axi_gpio_shield_1_0_slave_attachment .E(E), .GPIO_DBus_i(GPIO_DBus_i), .GPIO_xferAck_i(GPIO_xferAck_i), - .\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg (\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ), - .\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg (\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ), + .\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] (\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ), + .\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 (\MEM_DECODE_GEN[0].cs_out_i_reg[0] ), + .\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[18] (\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[18] ), .\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28] (\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28] ), .\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29] (\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29] ), .\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30] (\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30] ), @@ -3723,171 +2564,98 @@ module Arty_Z7_20_axi_gpio_shield_1_0_slave_attachment .\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26] (\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26] ), .\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27] (\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27] ), .\Not_Dual.gpio_Data_In_reg[0] (Q), - .\Not_Dual.gpio_Data_Out_reg[0] (\Not_Dual.gpio_Data_Out_reg[0] ), - .\Not_Dual.gpio_Data_Out_reg[13] (\Not_Dual.gpio_Data_Out_reg[13] ), - .Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ), - .Read_Reg_Rst(Read_Reg_Rst), - .\bus2ip_addr_i_reg[8] ({bus2ip_addr[0],bus2ip_addr[1],bus2ip_addr[2],bus2ip_addr[3],bus2ip_addr[4],bus2ip_addr[5],bus2ip_addr[6]}), - .bus2ip_reset(bus2ip_reset), - .bus2ip_rnw_i_reg(\Not_Dual.gpio_OE_reg[0] ), + .\Not_Dual.gpio_OE_reg[0] (\Not_Dual.gpio_OE_reg[0] ), + .Q({bus2ip_addr[0],bus2ip_addr[5],bus2ip_addr[6]}), + .bus2ip_rnw_i_reg(\Not_Dual.gpio_Data_Out_reg[0] ), .gpio_io_t(gpio_io_t), .gpio_xferAck_Reg(gpio_xferAck_Reg), - .interrupt_wrce_strb(interrupt_wrce_strb), - .intr2bus_rdack0(intr2bus_rdack0), - .intr_rd_ce_or_reduce(intr_rd_ce_or_reduce), - .intr_wr_ce_or_reduce(intr_wr_ce_or_reduce), - .ip2Bus_RdAck_intr_reg_hole_d1(ip2Bus_RdAck_intr_reg_hole_d1), - .ip2Bus_WrAck_intr_reg_hole_d1(ip2Bus_WrAck_intr_reg_hole_d1), - .ip2bus_data(ip2bus_data), - .\ip2bus_data_i_D1_reg[0] (\ip2bus_data_i_D1_reg[0] ), - .\ip2bus_data_i_D1_reg[0]_0 (\ip2bus_data_i_D1_reg[0]_0 ), .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1), .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1), - .\ip_irpt_enable_reg_reg[0] (\ip_irpt_enable_reg_reg[0] ), - .\ip_irpt_enable_reg_reg[0]_0 (\ip_irpt_enable_reg_reg[0]_0 ), - .ipif_glbl_irpt_enable_reg_reg(ipif_glbl_irpt_enable_reg_reg), - .irpt_rdack(irpt_rdack), - .irpt_rdack_d1(irpt_rdack_d1), - .irpt_wrack(irpt_wrack), - .irpt_wrack_d1(irpt_wrack_d1), .is_read(is_read), .is_write_reg(is_write_reg_n_0), - .p_0_in(p_0_in), - .p_1_in(p_1_in), - .p_3_in(p_3_in), + .rst_reg(SR), .s_axi_aclk(s_axi_aclk), .s_axi_aresetn(s_axi_aresetn), .s_axi_arready(s_axi_arready), .s_axi_wdata(s_axi_wdata), .s_axi_wready(s_axi_wready), - .start2(start2)); + .start2_reg(start2)); LUT5 #( - .INIT(32'hABAAA8AA)) + .INIT(32'hCCCACCCC)) \bus2ip_addr_i[2]_i_1 - (.I0(s_axi_awaddr[0]), - .I1(state[1]), + (.I0(s_axi_araddr[0]), + .I1(s_axi_awaddr[0]), .I2(state[0]), - .I3(s_axi_arvalid), - .I4(s_axi_araddr[0]), - .O(p_1_in__0[2])); + .I3(state[1]), + .I4(s_axi_arvalid), + .O(\bus2ip_addr_i[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair0" *) LUT5 #( - .INIT(32'hABAAA8AA)) + .INIT(32'hCCCACCCC)) \bus2ip_addr_i[3]_i_1 - (.I0(s_axi_awaddr[1]), - .I1(state[1]), - .I2(state[0]), - .I3(s_axi_arvalid), - .I4(s_axi_araddr[1]), - .O(p_1_in__0[3])); - (* SOFT_HLUTNM = "soft_lutpair4" *) - LUT5 #( - .INIT(32'hABAAA8AA)) - \bus2ip_addr_i[4]_i_1 - (.I0(s_axi_awaddr[2]), - .I1(state[1]), - .I2(state[0]), - .I3(s_axi_arvalid), - .I4(s_axi_araddr[2]), - .O(p_1_in__0[4])); - LUT5 #( - .INIT(32'hABAAA8AA)) - \bus2ip_addr_i[5]_i_1 - (.I0(s_axi_awaddr[3]), - .I1(state[1]), - .I2(state[0]), - .I3(s_axi_arvalid), - .I4(s_axi_araddr[3]), - .O(p_1_in__0[5])); - LUT5 #( - .INIT(32'hABAAA8AA)) - \bus2ip_addr_i[6]_i_1 - (.I0(s_axi_awaddr[4]), - .I1(state[1]), + (.I0(s_axi_araddr[1]), + .I1(s_axi_awaddr[1]), .I2(state[0]), - .I3(s_axi_arvalid), - .I4(s_axi_araddr[4]), - .O(p_1_in__0[6])); - LUT5 #( - .INIT(32'hABAAA8AA)) - \bus2ip_addr_i[7]_i_1 - (.I0(s_axi_awaddr[5]), - .I1(state[1]), - .I2(state[0]), - .I3(s_axi_arvalid), - .I4(s_axi_araddr[5]), - .O(p_1_in__0[7])); + .I3(state[1]), + .I4(s_axi_arvalid), + .O(\bus2ip_addr_i[3]_i_1_n_0 )); LUT5 #( - .INIT(32'hABAAA8AA)) + .INIT(32'h000000EA)) \bus2ip_addr_i[8]_i_1 - (.I0(s_axi_awaddr[6]), - .I1(state[1]), + (.I0(s_axi_arvalid), + .I1(s_axi_awvalid), + .I2(s_axi_wvalid), + .I3(state[1]), + .I4(state[0]), + .O(\bus2ip_addr_i[8]_i_1_n_0 )); + LUT5 #( + .INIT(32'hCCCACCCC)) + \bus2ip_addr_i[8]_i_2 + (.I0(s_axi_araddr[2]), + .I1(s_axi_awaddr[2]), .I2(state[0]), - .I3(s_axi_arvalid), - .I4(s_axi_araddr[6]), - .O(p_1_in__0[8])); + .I3(state[1]), + .I4(s_axi_arvalid), + .O(\bus2ip_addr_i[8]_i_2_n_0 )); FDRE \bus2ip_addr_i_reg[2] (.C(s_axi_aclk), - .CE(start2_i_1_n_0), - .D(p_1_in__0[2]), + .CE(\bus2ip_addr_i[8]_i_1_n_0 ), + .D(\bus2ip_addr_i[2]_i_1_n_0 ), .Q(bus2ip_addr[6]), - .R(bus2ip_reset)); + .R(SR)); FDRE \bus2ip_addr_i_reg[3] (.C(s_axi_aclk), - .CE(start2_i_1_n_0), - .D(p_1_in__0[3]), + .CE(\bus2ip_addr_i[8]_i_1_n_0 ), + .D(\bus2ip_addr_i[3]_i_1_n_0 ), .Q(bus2ip_addr[5]), - .R(bus2ip_reset)); - FDRE \bus2ip_addr_i_reg[4] - (.C(s_axi_aclk), - .CE(start2_i_1_n_0), - .D(p_1_in__0[4]), - .Q(bus2ip_addr[4]), - .R(bus2ip_reset)); - FDRE \bus2ip_addr_i_reg[5] - (.C(s_axi_aclk), - .CE(start2_i_1_n_0), - .D(p_1_in__0[5]), - .Q(bus2ip_addr[3]), - .R(bus2ip_reset)); - FDRE \bus2ip_addr_i_reg[6] - (.C(s_axi_aclk), - .CE(start2_i_1_n_0), - .D(p_1_in__0[6]), - .Q(bus2ip_addr[2]), - .R(bus2ip_reset)); - FDRE \bus2ip_addr_i_reg[7] - (.C(s_axi_aclk), - .CE(start2_i_1_n_0), - .D(p_1_in__0[7]), - .Q(bus2ip_addr[1]), - .R(bus2ip_reset)); + .R(SR)); FDRE \bus2ip_addr_i_reg[8] (.C(s_axi_aclk), - .CE(start2_i_1_n_0), - .D(p_1_in__0[8]), + .CE(\bus2ip_addr_i[8]_i_1_n_0 ), + .D(\bus2ip_addr_i[8]_i_2_n_0 ), .Q(bus2ip_addr[0]), - .R(bus2ip_reset)); - (* SOFT_HLUTNM = "soft_lutpair4" *) + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair0" *) LUT3 #( - .INIT(8'h02)) + .INIT(8'h10)) bus2ip_rnw_i_i_1 - (.I0(s_axi_arvalid), - .I1(state[0]), - .I2(state[1]), + (.I0(state[0]), + .I1(state[1]), + .I2(s_axi_arvalid), .O(bus2ip_rnw_i06_out)); FDRE bus2ip_rnw_i_reg (.C(s_axi_aclk), - .CE(start2_i_1_n_0), + .CE(\bus2ip_addr_i[8]_i_1_n_0 ), .D(bus2ip_rnw_i06_out), - .Q(\Not_Dual.gpio_OE_reg[0] ), - .R(bus2ip_reset)); + .Q(\Not_Dual.gpio_Data_Out_reg[0] ), + .R(SR)); LUT5 #( .INIT(32'h3FFA000A)) is_read_i_1 (.I0(s_axi_arvalid), - .I1(\state[1]_i_2_n_0 ), - .I2(state[1]), - .I3(state[0]), + .I1(state1__2), + .I2(state[0]), + .I3(state[1]), .I4(is_read), .O(is_read_i_1_n_0)); FDRE is_read_reg @@ -3895,33 +2663,44 @@ module Arty_Z7_20_axi_gpio_shield_1_0_slave_attachment .CE(1'b1), .D(is_read_i_1_n_0), .Q(is_read), - .R(bus2ip_reset)); + .R(SR)); LUT6 #( - .INIT(64'h1000FFFF10000000)) + .INIT(64'h0040FFFF00400000)) is_write_i_1 - (.I0(state[1]), - .I1(s_axi_arvalid), + (.I0(s_axi_arvalid), + .I1(s_axi_awvalid), .I2(s_axi_wvalid), - .I3(s_axi_awvalid), + .I3(state[1]), .I4(is_write), .I5(is_write_reg_n_0), .O(is_write_i_1_n_0)); LUT6 #( .INIT(64'hF88800000000FFFF)) is_write_i_2 - (.I0(s_axi_bready), - .I1(s_axi_bvalid), - .I2(s_axi_rready), - .I3(s_axi_rvalid), - .I4(state[1]), - .I5(state[0]), + (.I0(s_axi_rvalid), + .I1(s_axi_rready), + .I2(s_axi_bvalid), + .I3(s_axi_bready), + .I4(state[0]), + .I5(state[1]), .O(is_write)); FDRE is_write_reg (.C(s_axi_aclk), .CE(1'b1), .D(is_write_i_1_n_0), .Q(is_write_reg_n_0), - .R(bus2ip_reset)); + .R(SR)); + LUT1 #( + .INIT(2'h1)) + rst_i_1 + (.I0(s_axi_aresetn), + .O(p_1_in)); + FDRE rst_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(p_1_in), + .Q(SR), + .R(1'b0)); LUT5 #( .INIT(32'h08FF0808)) s_axi_bvalid_i_i_1 @@ -3938,133 +2717,125 @@ module Arty_Z7_20_axi_gpio_shield_1_0_slave_attachment .CE(1'b1), .D(s_axi_bvalid_i_i_1_n_0), .Q(s_axi_bvalid), - .R(bus2ip_reset)); + .R(SR)); LUT2 #( .INIT(4'h2)) - \s_axi_rdata_i[31]_i_1 + \s_axi_rdata_i[13]_i_1 (.I0(state[0]), .I1(state[1]), - .O(s_axi_rdata_i)); + .O(\s_axi_rdata_i[13]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[0] (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [0]), + .CE(\s_axi_rdata_i[13]_i_1_n_0 ), + .D(\ip2bus_data_i_D1_reg[18] [0]), .Q(s_axi_rdata[0]), - .R(bus2ip_reset)); + .R(SR)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[10] (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [10]), + .CE(\s_axi_rdata_i[13]_i_1_n_0 ), + .D(\ip2bus_data_i_D1_reg[18] [10]), .Q(s_axi_rdata[10]), - .R(bus2ip_reset)); + .R(SR)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[11] (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [11]), + .CE(\s_axi_rdata_i[13]_i_1_n_0 ), + .D(\ip2bus_data_i_D1_reg[18] [11]), .Q(s_axi_rdata[11]), - .R(bus2ip_reset)); + .R(SR)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[12] (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [12]), + .CE(\s_axi_rdata_i[13]_i_1_n_0 ), + .D(\ip2bus_data_i_D1_reg[18] [12]), .Q(s_axi_rdata[12]), - .R(bus2ip_reset)); + .R(SR)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[13] (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [13]), + .CE(\s_axi_rdata_i[13]_i_1_n_0 ), + .D(\ip2bus_data_i_D1_reg[18] [13]), .Q(s_axi_rdata[13]), - .R(bus2ip_reset)); + .R(SR)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[1] (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [1]), + .CE(\s_axi_rdata_i[13]_i_1_n_0 ), + .D(\ip2bus_data_i_D1_reg[18] [1]), .Q(s_axi_rdata[1]), - .R(bus2ip_reset)); + .R(SR)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[2] (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [2]), + .CE(\s_axi_rdata_i[13]_i_1_n_0 ), + .D(\ip2bus_data_i_D1_reg[18] [2]), .Q(s_axi_rdata[2]), - .R(bus2ip_reset)); - FDRE #( - .INIT(1'b0)) - \s_axi_rdata_i_reg[31] - (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [14]), - .Q(s_axi_rdata[14]), - .R(bus2ip_reset)); + .R(SR)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[3] (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [3]), + .CE(\s_axi_rdata_i[13]_i_1_n_0 ), + .D(\ip2bus_data_i_D1_reg[18] [3]), .Q(s_axi_rdata[3]), - .R(bus2ip_reset)); + .R(SR)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[4] (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [4]), + .CE(\s_axi_rdata_i[13]_i_1_n_0 ), + .D(\ip2bus_data_i_D1_reg[18] [4]), .Q(s_axi_rdata[4]), - .R(bus2ip_reset)); + .R(SR)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[5] (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [5]), + .CE(\s_axi_rdata_i[13]_i_1_n_0 ), + .D(\ip2bus_data_i_D1_reg[18] [5]), .Q(s_axi_rdata[5]), - .R(bus2ip_reset)); + .R(SR)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[6] (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [6]), + .CE(\s_axi_rdata_i[13]_i_1_n_0 ), + .D(\ip2bus_data_i_D1_reg[18] [6]), .Q(s_axi_rdata[6]), - .R(bus2ip_reset)); + .R(SR)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[7] (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [7]), + .CE(\s_axi_rdata_i[13]_i_1_n_0 ), + .D(\ip2bus_data_i_D1_reg[18] [7]), .Q(s_axi_rdata[7]), - .R(bus2ip_reset)); + .R(SR)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[8] (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [8]), + .CE(\s_axi_rdata_i[13]_i_1_n_0 ), + .D(\ip2bus_data_i_D1_reg[18] [8]), .Q(s_axi_rdata[8]), - .R(bus2ip_reset)); + .R(SR)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[9] (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [9]), + .CE(\s_axi_rdata_i[13]_i_1_n_0 ), + .D(\ip2bus_data_i_D1_reg[18] [9]), .Q(s_axi_rdata[9]), - .R(bus2ip_reset)); + .R(SR)); LUT5 #( .INIT(32'h08FF0808)) s_axi_rvalid_i_i_1 @@ -4081,41 +2852,41 @@ module Arty_Z7_20_axi_gpio_shield_1_0_slave_attachment .CE(1'b1), .D(s_axi_rvalid_i_i_1_n_0), .Q(s_axi_rvalid), - .R(bus2ip_reset)); + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair1" *) LUT5 #( .INIT(32'h000000F8)) start2_i_1 (.I0(s_axi_awvalid), .I1(s_axi_wvalid), .I2(s_axi_arvalid), - .I3(state[0]), - .I4(state[1]), + .I3(state[1]), + .I4(state[0]), .O(start2_i_1_n_0)); FDRE start2_reg (.C(s_axi_aclk), .CE(1'b1), .D(start2_i_1_n_0), .Q(start2), - .R(bus2ip_reset)); + .R(SR)); LUT5 #( - .INIT(32'h0FFFAACC)) + .INIT(32'h77FC44FC)) \state[0]_i_1 - (.I0(s_axi_wready), - .I1(s_axi_arvalid), - .I2(\state[1]_i_2_n_0 ), + (.I0(state1__2), + .I1(state[0]), + .I2(s_axi_arvalid), .I3(state[1]), - .I4(state[0]), - .O(p_0_out__0[0])); - LUT6 #( - .INIT(64'h2E2E2E2ECCCCFFCC)) + .I4(s_axi_wready), + .O(p_0_out[0])); + LUT5 #( + .INIT(32'h5FFC50FC)) \state[1]_i_1 - (.I0(s_axi_arready), - .I1(state[1]), - .I2(\state[1]_i_2_n_0 ), - .I3(\state[1]_i_3_n_0 ), - .I4(s_axi_arvalid), - .I5(state[0]), - .O(p_0_out__0[1])); + (.I0(state1__2), + .I1(\state[1]_i_3_n_0 ), + .I2(state[1]), + .I3(state[0]), + .I4(s_axi_arready), + .O(p_0_out[1])); LUT4 #( .INIT(16'hF888)) \state[1]_i_2 @@ -4123,25 +2894,27 @@ module Arty_Z7_20_axi_gpio_shield_1_0_slave_attachment .I1(s_axi_bvalid), .I2(s_axi_rready), .I3(s_axi_rvalid), - .O(\state[1]_i_2_n_0 )); - LUT2 #( - .INIT(4'h8)) + .O(state1__2)); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT3 #( + .INIT(8'h08)) \state[1]_i_3 - (.I0(s_axi_awvalid), - .I1(s_axi_wvalid), + (.I0(s_axi_wvalid), + .I1(s_axi_awvalid), + .I2(s_axi_arvalid), .O(\state[1]_i_3_n_0 )); FDRE \state_reg[0] (.C(s_axi_aclk), .CE(1'b1), - .D(p_0_out__0[0]), + .D(p_0_out[0]), .Q(state[0]), - .R(bus2ip_reset)); + .R(SR)); FDRE \state_reg[1] (.C(s_axi_aclk), .CE(1'b1), - .D(p_0_out__0[1]), + .D(p_0_out[1]), .Q(state[1]), - .R(bus2ip_reset)); + .R(SR)); endmodule `ifndef GLBL `define GLBL diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0_sim_netlist.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0_sim_netlist.vhdl index 338d6ca..6d79e73 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0_sim_netlist.vhdl +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 --- Date : Fri Feb 24 15:59:44 2017 +-- Date : Sat Mar 04 18:53:03 2017 -- Host : WK73 running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim --- c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0_sim_netlist.vhdl +-- C:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0_sim_netlist.vhdl -- Design : Arty_Z7_20_axi_gpio_shield_1_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. @@ -16,1082 +16,474 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20_axi_gpio_shield_1_0_address_decoder is port ( - \ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC; - \Not_Dual.gpio_Data_Out_reg[13]\ : out STD_LOGIC; - \ip_irpt_enable_reg_reg[0]\ : out STD_LOGIC; + \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arready : out STD_LOGIC; s_axi_wready : out STD_LOGIC; - D : out STD_LOGIC_VECTOR ( 13 downto 0 ); - \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[31]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[24]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[23]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[22]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[21]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[20]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[19]\ : out STD_LOGIC; GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 ); - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - \Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - \ip2bus_data_i_D1_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); - intr2bus_rdack0 : out STD_LOGIC; - irpt_rdack : out STD_LOGIC; - irpt_wrack : out STD_LOGIC; - interrupt_wrce_strb : out STD_LOGIC; - Read_Reg_Rst : out STD_LOGIC; - \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ : out STD_LOGIC; - intr_rd_ce_or_reduce : out STD_LOGIC; - \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC; - intr_wr_ce_or_reduce : out STD_LOGIC; - \ip_irpt_enable_reg_reg[0]_0\ : out STD_LOGIC; - ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC; - start2 : in STD_LOGIC; + \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[19]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[20]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[21]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[22]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[23]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[24]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[31]\ : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 13 downto 0 ); + \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[18]\ : out STD_LOGIC; s_axi_aclk : in STD_LOGIC; - s_axi_aresetn : in STD_LOGIC; - Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); - is_read : in STD_LOGIC; + rst_reg : in STD_LOGIC; + bus2ip_rnw_i_reg : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); ip2bus_rdack_i_D1 : in STD_LOGIC; - is_write_reg : in STD_LOGIC; + is_read : in STD_LOGIC; + \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); ip2bus_wrack_i_D1 : in STD_LOGIC; - s_axi_wdata : in STD_LOGIC_VECTOR ( 27 downto 0 ); - \bus2ip_addr_i_reg[8]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); - gpio_io_t : in STD_LOGIC_VECTOR ( 13 downto 0 ); + is_write_reg : in STD_LOGIC; \Not_Dual.gpio_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 13 downto 0 ); - bus2ip_rnw_i_reg : in STD_LOGIC; - bus2ip_reset : in STD_LOGIC; - p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); - irpt_rdack_d1 : in STD_LOGIC; - irpt_wrack_d1 : in STD_LOGIC; - ip2bus_data : in STD_LOGIC_VECTOR ( 0 to 0 ); - p_3_in : in STD_LOGIC_VECTOR ( 0 to 0 ); - p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 ); - GPIO_xferAck_i : in STD_LOGIC; + gpio_io_t : in STD_LOGIC_VECTOR ( 13 downto 0 ); + s_axi_wdata : in STD_LOGIC_VECTOR ( 27 downto 0 ); + start2_reg : in STD_LOGIC; + s_axi_aresetn : in STD_LOGIC; gpio_xferAck_Reg : in STD_LOGIC; - ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC; - ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC + GPIO_xferAck_i : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of Arty_Z7_20_axi_gpio_shield_1_0_address_decoder : entity is "address_decoder"; end Arty_Z7_20_axi_gpio_shield_1_0_address_decoder; architecture STRUCTURE of Arty_Z7_20_axi_gpio_shield_1_0_address_decoder is - signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC; - signal \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\ : STD_LOGIC; - signal \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\ : STD_LOGIC; - signal \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\ : STD_LOGIC; - signal \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ : STD_LOGIC; - signal \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\ : STD_LOGIC; - signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\ : STD_LOGIC; - signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\ : STD_LOGIC; - signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\ : STD_LOGIC; - signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\ : STD_LOGIC; - signal \^not_dual.gpio_data_out_reg[13]\ : STD_LOGIC; - signal \^ip2bus_data_i_d1_reg[0]\ : STD_LOGIC; - signal \^ip_irpt_enable_reg_reg[0]\ : STD_LOGIC; - signal p_10_in : STD_LOGIC; - signal p_10_out : STD_LOGIC; - signal p_11_in : STD_LOGIC; - signal p_11_out : STD_LOGIC; - signal p_12_in : STD_LOGIC; - signal p_12_out : STD_LOGIC; - signal p_13_in : STD_LOGIC; - signal p_13_out : STD_LOGIC; - signal p_14_in : STD_LOGIC; - signal p_14_out : STD_LOGIC; - signal p_15_in : STD_LOGIC; - signal p_15_out : STD_LOGIC; - signal p_16_in : STD_LOGIC; - signal p_2_in : STD_LOGIC; - signal p_3_in_0 : STD_LOGIC; - signal p_4_in : STD_LOGIC; - signal p_4_out : STD_LOGIC; - signal p_5_in : STD_LOGIC; - signal p_5_out : STD_LOGIC; - signal p_6_in : STD_LOGIC; - signal p_6_out : STD_LOGIC; - signal p_7_in : STD_LOGIC; - signal p_7_out : STD_LOGIC; - signal p_8_out : STD_LOGIC; - signal p_9_in : STD_LOGIC; - signal p_9_out : STD_LOGIC; - signal pselect_hit_i_1 : STD_LOGIC; + signal \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\ : STD_LOGIC; + signal \^mem_decode_gen[0].cs_out_i_reg[0]_0\ : STD_LOGIC; signal \^s_axi_arready\ : STD_LOGIC; signal \^s_axi_wready\ : STD_LOGIC; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_i_1\ : label is "soft_lutpair0"; - attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_i_1\ : label is "soft_lutpair1"; - attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_1\ : label is "soft_lutpair1"; - attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_1\ : label is "soft_lutpair0"; - attribute SOFT_HLUTNM of intr2bus_rdack_i_1 : label is "soft_lutpair2"; - attribute SOFT_HLUTNM of \ip2bus_data_i_D1[0]_i_1\ : label is "soft_lutpair3"; - attribute SOFT_HLUTNM of irpt_rdack_d1_i_1 : label is "soft_lutpair2"; - attribute SOFT_HLUTNM of irpt_wrack_d1_i_1 : label is "soft_lutpair3"; begin - \Not_Dual.gpio_Data_Out_reg[13]\ <= \^not_dual.gpio_data_out_reg[13]\; - \ip2bus_data_i_D1_reg[0]\ <= \^ip2bus_data_i_d1_reg[0]\; - \ip_irpt_enable_reg_reg[0]\ <= \^ip_irpt_enable_reg_reg[0]\; + \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ <= \^mem_decode_gen[0].cs_out_i_reg[0]_0\; s_axi_arready <= \^s_axi_arready\; s_axi_wready <= \^s_axi_wready\; -Bus_RNW_reg_i_1: unisim.vcomponents.LUT3 +\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"B8" + INIT => X"000000E0" ) port map ( - I0 => bus2ip_rnw_i_reg, - I1 => start2, - I2 => \^ip_irpt_enable_reg_reg[0]\, - O => Bus_RNW_reg_i_1_n_0 + I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I1 => start2_reg, + I2 => s_axi_aresetn, + I3 => \^s_axi_arready\, + I4 => \^s_axi_wready\, + O => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\ ); -Bus_RNW_reg_reg: unisim.vcomponents.FDRE +\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => Bus_RNW_reg_i_1_n_0, - Q => \^ip_irpt_enable_reg_reg[0]\, + D => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\, + Q => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, R => '0' ); -\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0040000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(3), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \bus2ip_addr_i_reg[8]\(2), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => p_9_out - ); -\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => p_9_out, - Q => p_10_in, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"4000000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(3), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \bus2ip_addr_i_reg[8]\(2), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => p_8_out - ); -\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => p_8_out, - Q => p_9_in, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0004000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(1), - I1 => \bus2ip_addr_i_reg[8]\(3), - I2 => \bus2ip_addr_i_reg[8]\(2), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => p_7_out - ); -\GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => p_7_out, - Q => \^ip2bus_data_i_d1_reg[0]\, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0400000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(1), - I1 => \bus2ip_addr_i_reg[8]\(3), - I2 => \bus2ip_addr_i_reg[8]\(2), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => p_6_out - ); -\GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => p_6_out, - Q => p_7_in, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0008000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(1), - I1 => \bus2ip_addr_i_reg[8]\(3), - I2 => \bus2ip_addr_i_reg[8]\(2), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => p_5_out - ); -\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => p_5_out, - Q => p_6_in, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0800000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(1), - I1 => \bus2ip_addr_i_reg[8]\(3), - I2 => \bus2ip_addr_i_reg[8]\(2), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => p_4_out - ); -\GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => p_4_out, - Q => p_5_in, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0008000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(3), - I1 => \bus2ip_addr_i_reg[8]\(2), - I2 => \bus2ip_addr_i_reg[8]\(1), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\, - Q => p_4_in, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0800000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(3), - I1 => \bus2ip_addr_i_reg[8]\(2), - I2 => \bus2ip_addr_i_reg[8]\(1), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\, - Q => p_3_in_0, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0080000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(3), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \bus2ip_addr_i_reg[8]\(2), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\, - Q => p_2_in, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"FD" - ) - port map ( - I0 => s_axi_aresetn, - I1 => \^s_axi_arready\, - I2 => \^s_axi_wready\, - O => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"8000000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(3), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \bus2ip_addr_i_reg[8]\(2), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => p_15_out - ); -\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg[19]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => p_15_out, - Q => \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0001000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(1), - I1 => \bus2ip_addr_i_reg[8]\(2), - I2 => \bus2ip_addr_i_reg[8]\(3), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\, - Q => p_16_in, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0100000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(1), - I1 => \bus2ip_addr_i_reg[8]\(2), - I2 => \bus2ip_addr_i_reg[8]\(3), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => p_14_out - ); -\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => p_14_out, - Q => p_15_in, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0002000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(1), - I1 => \bus2ip_addr_i_reg[8]\(2), - I2 => \bus2ip_addr_i_reg[8]\(3), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => p_13_out - ); -\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => p_13_out, - Q => p_14_in, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0200000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(1), - I1 => \bus2ip_addr_i_reg[8]\(2), - I2 => \bus2ip_addr_i_reg[8]\(3), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => p_12_out - ); -\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => p_12_out, - Q => p_13_in, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0004000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(3), - I1 => \bus2ip_addr_i_reg[8]\(2), - I2 => \bus2ip_addr_i_reg[8]\(1), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => p_11_out - ); -\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => p_11_out, - Q => p_12_in, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0400000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(3), - I1 => \bus2ip_addr_i_reg[8]\(2), - I2 => \bus2ip_addr_i_reg[8]\(1), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => p_10_out - ); -\GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => p_10_out, - Q => p_11_in, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"FE00" - ) - port map ( - I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\, - I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\, - I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\, - I3 => \^ip_irpt_enable_reg_reg[0]\, - O => intr_rd_ce_or_reduce - ); -\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"00FE0000" - ) - port map ( - I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\, - I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\, - I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\, - I3 => ip2Bus_RdAck_intr_reg_hole_d1, - I4 => \^ip_irpt_enable_reg_reg[0]\, - O => \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ - ); -\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"00FE" - ) - port map ( - I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\, - I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\, - I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\, - I3 => \^ip_irpt_enable_reg_reg[0]\, - O => intr_wr_ce_or_reduce - ); -\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFFFFFFE" - ) - port map ( - I0 => p_16_in, - I1 => p_2_in, - I2 => \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\, - I3 => p_14_in, - I4 => p_15_in, - O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\ - ); -\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3\: unisim.vcomponents.LUT4 - generic map( - INIT => X"FFFE" - ) - port map ( - I0 => p_12_in, - I1 => p_13_in, - I2 => p_10_in, - I3 => p_11_in, - O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\ - ); -\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4\: unisim.vcomponents.LUT4 - generic map( - INIT => X"FFFE" - ) - port map ( - I0 => p_5_in, - I1 => p_7_in, - I2 => p_3_in_0, - I3 => p_4_in, - O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\ - ); -\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"000000FE" - ) - port map ( - I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\, - I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\, - I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\, - I3 => \^ip_irpt_enable_reg_reg[0]\, - I4 => ip2Bus_WrAck_intr_reg_hole_d1, - O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ - ); -\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000000000000002" - ) - port map ( - I0 => start2, - I1 => \bus2ip_addr_i_reg[8]\(6), - I2 => \bus2ip_addr_i_reg[8]\(4), - I3 => \bus2ip_addr_i_reg[8]\(5), - I4 => \bus2ip_addr_i_reg[8]\(3), - I5 => \bus2ip_addr_i_reg[8]\(2), - O => pselect_hit_i_1 - ); -\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => pselect_hit_i_1, - Q => \^not_dual.gpio_data_out_reg[13]\, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i[18]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000A0000000C0000" + INIT => X"000000E000000020" ) port map ( - I0 => gpio_io_t(13), - I1 => \Not_Dual.gpio_Data_In_reg[0]\(13), - I2 => \bus2ip_addr_i_reg[8]\(6), - I3 => \bus2ip_addr_i_reg[8]\(1), - I4 => \^not_dual.gpio_data_out_reg[13]\, - I5 => \bus2ip_addr_i_reg[8]\(0), + I0 => \Not_Dual.gpio_Data_In_reg[0]\(13), + I1 => Q(0), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(1), + I5 => gpio_io_t(13), O => GPIO_DBus_i(0) ); \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i[28]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000A0000000C0000" + INIT => X"000000E000000020" ) port map ( - I0 => gpio_io_t(3), - I1 => \Not_Dual.gpio_Data_In_reg[0]\(3), - I2 => \bus2ip_addr_i_reg[8]\(6), - I3 => \bus2ip_addr_i_reg[8]\(1), - I4 => \^not_dual.gpio_data_out_reg[13]\, - I5 => \bus2ip_addr_i_reg[8]\(0), + I0 => \Not_Dual.gpio_Data_In_reg[0]\(3), + I1 => Q(0), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(1), + I5 => gpio_io_t(3), O => \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28]\ ); \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i[29]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000A0000000C0000" + INIT => X"000000E000000020" ) port map ( - I0 => gpio_io_t(2), - I1 => \Not_Dual.gpio_Data_In_reg[0]\(2), - I2 => \bus2ip_addr_i_reg[8]\(6), - I3 => \bus2ip_addr_i_reg[8]\(1), - I4 => \^not_dual.gpio_data_out_reg[13]\, - I5 => \bus2ip_addr_i_reg[8]\(0), + I0 => \Not_Dual.gpio_Data_In_reg[0]\(2), + I1 => Q(0), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(1), + I5 => gpio_io_t(2), O => \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29]\ ); \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i[30]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000A0000000C0000" + INIT => X"000000E000000020" ) port map ( - I0 => gpio_io_t(1), - I1 => \Not_Dual.gpio_Data_In_reg[0]\(1), - I2 => \bus2ip_addr_i_reg[8]\(6), - I3 => \bus2ip_addr_i_reg[8]\(1), - I4 => \^not_dual.gpio_data_out_reg[13]\, - I5 => \bus2ip_addr_i_reg[8]\(0), + I0 => \Not_Dual.gpio_Data_In_reg[0]\(1), + I1 => Q(0), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(1), + I5 => gpio_io_t(1), O => \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30]\ ); \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i[31]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"FFDF" + INIT => X"FFF7" ) port map ( - I0 => \^not_dual.gpio_data_out_reg[13]\, - I1 => GPIO_xferAck_i, - I2 => bus2ip_rnw_i_reg, - I3 => gpio_xferAck_Reg, - O => Read_Reg_Rst + I0 => bus2ip_rnw_i_reg, + I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I2 => gpio_xferAck_Reg, + I3 => GPIO_xferAck_i, + O => \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[18]\ ); \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i[31]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"000A0000000C0000" + INIT => X"000000E000000020" ) port map ( - I0 => gpio_io_t(0), - I1 => \Not_Dual.gpio_Data_In_reg[0]\(0), - I2 => \bus2ip_addr_i_reg[8]\(6), - I3 => \bus2ip_addr_i_reg[8]\(1), - I4 => \^not_dual.gpio_data_out_reg[13]\, - I5 => \bus2ip_addr_i_reg[8]\(0), + I0 => \Not_Dual.gpio_Data_In_reg[0]\(0), + I1 => Q(0), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(1), + I5 => gpio_io_t(0), O => \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[31]\ ); \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i[19]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000A0000000C0000" + INIT => X"000000E000000020" ) port map ( - I0 => gpio_io_t(12), - I1 => \Not_Dual.gpio_Data_In_reg[0]\(12), - I2 => \bus2ip_addr_i_reg[8]\(6), - I3 => \bus2ip_addr_i_reg[8]\(1), - I4 => \^not_dual.gpio_data_out_reg[13]\, - I5 => \bus2ip_addr_i_reg[8]\(0), + I0 => \Not_Dual.gpio_Data_In_reg[0]\(12), + I1 => Q(0), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(1), + I5 => gpio_io_t(12), O => \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[19]\ ); \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i[20]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000A0000000C0000" + INIT => X"000000E000000020" ) port map ( - I0 => gpio_io_t(11), - I1 => \Not_Dual.gpio_Data_In_reg[0]\(11), - I2 => \bus2ip_addr_i_reg[8]\(6), - I3 => \bus2ip_addr_i_reg[8]\(1), - I4 => \^not_dual.gpio_data_out_reg[13]\, - I5 => \bus2ip_addr_i_reg[8]\(0), + I0 => \Not_Dual.gpio_Data_In_reg[0]\(11), + I1 => Q(0), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(1), + I5 => gpio_io_t(11), O => \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[20]\ ); \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i[21]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000A0000000C0000" + INIT => X"000000E000000020" ) port map ( - I0 => gpio_io_t(10), - I1 => \Not_Dual.gpio_Data_In_reg[0]\(10), - I2 => \bus2ip_addr_i_reg[8]\(6), - I3 => \bus2ip_addr_i_reg[8]\(1), - I4 => \^not_dual.gpio_data_out_reg[13]\, - I5 => \bus2ip_addr_i_reg[8]\(0), + I0 => \Not_Dual.gpio_Data_In_reg[0]\(10), + I1 => Q(0), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(1), + I5 => gpio_io_t(10), O => \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[21]\ ); \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i[22]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000A0000000C0000" + INIT => X"000000E000000020" ) port map ( - I0 => gpio_io_t(9), - I1 => \Not_Dual.gpio_Data_In_reg[0]\(9), - I2 => \bus2ip_addr_i_reg[8]\(6), - I3 => \bus2ip_addr_i_reg[8]\(1), - I4 => \^not_dual.gpio_data_out_reg[13]\, - I5 => \bus2ip_addr_i_reg[8]\(0), + I0 => \Not_Dual.gpio_Data_In_reg[0]\(9), + I1 => Q(0), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(1), + I5 => gpio_io_t(9), O => \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[22]\ ); \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i[23]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000A0000000C0000" + INIT => X"000000E000000020" ) port map ( - I0 => gpio_io_t(8), - I1 => \Not_Dual.gpio_Data_In_reg[0]\(8), - I2 => \bus2ip_addr_i_reg[8]\(6), - I3 => \bus2ip_addr_i_reg[8]\(1), - I4 => \^not_dual.gpio_data_out_reg[13]\, - I5 => \bus2ip_addr_i_reg[8]\(0), + I0 => \Not_Dual.gpio_Data_In_reg[0]\(8), + I1 => Q(0), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(1), + I5 => gpio_io_t(8), O => \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[23]\ ); \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i[24]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000A0000000C0000" + INIT => X"000000E000000020" ) port map ( - I0 => gpio_io_t(7), - I1 => \Not_Dual.gpio_Data_In_reg[0]\(7), - I2 => \bus2ip_addr_i_reg[8]\(6), - I3 => \bus2ip_addr_i_reg[8]\(1), - I4 => \^not_dual.gpio_data_out_reg[13]\, - I5 => \bus2ip_addr_i_reg[8]\(0), + I0 => \Not_Dual.gpio_Data_In_reg[0]\(7), + I1 => Q(0), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(1), + I5 => gpio_io_t(7), O => \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[24]\ ); \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i[25]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000A0000000C0000" + INIT => X"000000E000000020" ) port map ( - I0 => gpio_io_t(6), - I1 => \Not_Dual.gpio_Data_In_reg[0]\(6), - I2 => \bus2ip_addr_i_reg[8]\(6), - I3 => \bus2ip_addr_i_reg[8]\(1), - I4 => \^not_dual.gpio_data_out_reg[13]\, - I5 => \bus2ip_addr_i_reg[8]\(0), + I0 => \Not_Dual.gpio_Data_In_reg[0]\(6), + I1 => Q(0), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(1), + I5 => gpio_io_t(6), O => \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25]\ ); \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i[26]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000A0000000C0000" + INIT => X"000000E000000020" ) port map ( - I0 => gpio_io_t(5), - I1 => \Not_Dual.gpio_Data_In_reg[0]\(5), - I2 => \bus2ip_addr_i_reg[8]\(6), - I3 => \bus2ip_addr_i_reg[8]\(1), - I4 => \^not_dual.gpio_data_out_reg[13]\, - I5 => \bus2ip_addr_i_reg[8]\(0), + I0 => \Not_Dual.gpio_Data_In_reg[0]\(5), + I1 => Q(0), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(1), + I5 => gpio_io_t(5), O => \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26]\ ); \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i[27]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000A0000000C0000" + INIT => X"000000E000000020" ) port map ( - I0 => gpio_io_t(4), - I1 => \Not_Dual.gpio_Data_In_reg[0]\(4), - I2 => \bus2ip_addr_i_reg[8]\(6), - I3 => \bus2ip_addr_i_reg[8]\(1), - I4 => \^not_dual.gpio_data_out_reg[13]\, - I5 => \bus2ip_addr_i_reg[8]\(0), + I0 => \Not_Dual.gpio_Data_In_reg[0]\(4), + I1 => Q(0), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(1), + I5 => gpio_io_t(4), O => \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27]\ ); \Not_Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFF00000100" + INIT => X"AAAAAAAAAAAAABAA" ) port map ( - I0 => bus2ip_rnw_i_reg, - I1 => \bus2ip_addr_i_reg[8]\(6), - I2 => \bus2ip_addr_i_reg[8]\(1), - I3 => \^not_dual.gpio_data_out_reg[13]\, - I4 => \bus2ip_addr_i_reg[8]\(0), - I5 => bus2ip_reset, - O => \Not_Dual.gpio_Data_Out_reg[0]\(0) + I0 => rst_reg, + I1 => bus2ip_rnw_i_reg, + I2 => Q(0), + I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I4 => Q(2), + I5 => Q(1), + O => E(0) ); \Not_Dual.gpio_Data_Out[0]_i_2\: unisim.vcomponents.LUT4 generic map( - INIT => X"BA8A" + INIT => X"CCAC" ) port map ( - I0 => s_axi_wdata(27), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \^not_dual.gpio_data_out_reg[13]\, - I3 => s_axi_wdata(13), + I0 => s_axi_wdata(13), + I1 => s_axi_wdata(27), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(1), O => D(13) ); \Not_Dual.gpio_Data_Out[10]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"BA8A" + INIT => X"CCAC" ) port map ( - I0 => s_axi_wdata(17), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \^not_dual.gpio_data_out_reg[13]\, - I3 => s_axi_wdata(3), + I0 => s_axi_wdata(3), + I1 => s_axi_wdata(17), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(1), O => D(3) ); \Not_Dual.gpio_Data_Out[11]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"BA8A" + INIT => X"CCAC" ) port map ( - I0 => s_axi_wdata(16), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \^not_dual.gpio_data_out_reg[13]\, - I3 => s_axi_wdata(2), + I0 => s_axi_wdata(2), + I1 => s_axi_wdata(16), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(1), O => D(2) ); \Not_Dual.gpio_Data_Out[12]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"BA8A" + INIT => X"CCAC" ) port map ( - I0 => s_axi_wdata(15), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \^not_dual.gpio_data_out_reg[13]\, - I3 => s_axi_wdata(1), + I0 => s_axi_wdata(1), + I1 => s_axi_wdata(15), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(1), O => D(1) ); \Not_Dual.gpio_Data_Out[13]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"BA8A" + INIT => X"CCAC" ) port map ( - I0 => s_axi_wdata(14), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \^not_dual.gpio_data_out_reg[13]\, - I3 => s_axi_wdata(0), + I0 => s_axi_wdata(0), + I1 => s_axi_wdata(14), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(1), O => D(0) ); \Not_Dual.gpio_Data_Out[1]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"BA8A" + INIT => X"CCAC" ) port map ( - I0 => s_axi_wdata(26), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \^not_dual.gpio_data_out_reg[13]\, - I3 => s_axi_wdata(12), + I0 => s_axi_wdata(12), + I1 => s_axi_wdata(26), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(1), O => D(12) ); \Not_Dual.gpio_Data_Out[2]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"BA8A" + INIT => X"CCAC" ) port map ( - I0 => s_axi_wdata(25), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \^not_dual.gpio_data_out_reg[13]\, - I3 => s_axi_wdata(11), + I0 => s_axi_wdata(11), + I1 => s_axi_wdata(25), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(1), O => D(11) ); \Not_Dual.gpio_Data_Out[3]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"BA8A" + INIT => X"CCAC" ) port map ( - I0 => s_axi_wdata(24), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \^not_dual.gpio_data_out_reg[13]\, - I3 => s_axi_wdata(10), + I0 => s_axi_wdata(10), + I1 => s_axi_wdata(24), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(1), O => D(10) ); \Not_Dual.gpio_Data_Out[4]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"BA8A" + INIT => X"CCAC" ) port map ( - I0 => s_axi_wdata(23), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \^not_dual.gpio_data_out_reg[13]\, - I3 => s_axi_wdata(9), + I0 => s_axi_wdata(9), + I1 => s_axi_wdata(23), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(1), O => D(9) ); \Not_Dual.gpio_Data_Out[5]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"BA8A" + INIT => X"CCAC" ) port map ( - I0 => s_axi_wdata(22), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \^not_dual.gpio_data_out_reg[13]\, - I3 => s_axi_wdata(8), + I0 => s_axi_wdata(8), + I1 => s_axi_wdata(22), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(1), O => D(8) ); \Not_Dual.gpio_Data_Out[6]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"BA8A" + INIT => X"CCAC" ) port map ( - I0 => s_axi_wdata(21), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \^not_dual.gpio_data_out_reg[13]\, - I3 => s_axi_wdata(7), + I0 => s_axi_wdata(7), + I1 => s_axi_wdata(21), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(1), O => D(7) ); \Not_Dual.gpio_Data_Out[7]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"BA8A" + INIT => X"CCAC" ) port map ( - I0 => s_axi_wdata(20), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \^not_dual.gpio_data_out_reg[13]\, - I3 => s_axi_wdata(6), + I0 => s_axi_wdata(6), + I1 => s_axi_wdata(20), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(1), O => D(6) ); \Not_Dual.gpio_Data_Out[8]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"BA8A" + INIT => X"CCAC" ) port map ( - I0 => s_axi_wdata(19), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \^not_dual.gpio_data_out_reg[13]\, - I3 => s_axi_wdata(5), + I0 => s_axi_wdata(5), + I1 => s_axi_wdata(19), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(1), O => D(5) ); \Not_Dual.gpio_Data_Out[9]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"BA8A" + INIT => X"CCAC" ) port map ( - I0 => s_axi_wdata(18), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \^not_dual.gpio_data_out_reg[13]\, - I3 => s_axi_wdata(4), + I0 => s_axi_wdata(4), + I1 => s_axi_wdata(18), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(1), O => D(4) ); \Not_Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFF01000000" - ) - port map ( - I0 => bus2ip_rnw_i_reg, - I1 => \bus2ip_addr_i_reg[8]\(6), - I2 => \bus2ip_addr_i_reg[8]\(1), - I3 => \^not_dual.gpio_data_out_reg[13]\, - I4 => \bus2ip_addr_i_reg[8]\(0), - I5 => bus2ip_reset, - O => E(0) - ); -intr2bus_rdack_i_1: unisim.vcomponents.LUT5 - generic map( - INIT => X"44444440" - ) - port map ( - I0 => irpt_rdack_d1, - I1 => \^ip_irpt_enable_reg_reg[0]\, - I2 => p_9_in, - I3 => \^ip2bus_data_i_d1_reg[0]\, - I4 => p_6_in, - O => intr2bus_rdack0 - ); -intr2bus_wrack_i_1: unisim.vcomponents.LUT5 - generic map( - INIT => X"000000FE" - ) - port map ( - I0 => p_9_in, - I1 => \^ip2bus_data_i_d1_reg[0]\, - I2 => p_6_in, - I3 => \^ip_irpt_enable_reg_reg[0]\, - I4 => irpt_wrack_d1, - O => interrupt_wrce_strb - ); -\ip2bus_data_i_D1[0]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"00000080" - ) - port map ( - I0 => p_0_in(0), - I1 => p_9_in, - I2 => \^ip_irpt_enable_reg_reg[0]\, - I3 => p_6_in, - I4 => \^ip2bus_data_i_d1_reg[0]\, - O => \ip2bus_data_i_D1_reg[0]_0\(1) - ); -\ip2bus_data_i_D1[31]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"EEEEAAAAFAAAAAAA" - ) - port map ( - I0 => ip2bus_data(0), - I1 => p_3_in(0), - I2 => p_1_in(0), - I3 => p_6_in, - I4 => \^ip_irpt_enable_reg_reg[0]\, - I5 => \^ip2bus_data_i_d1_reg[0]\, - O => \ip2bus_data_i_D1_reg[0]_0\(0) - ); -\ip_irpt_enable_reg[0]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"FB08" - ) - port map ( - I0 => s_axi_wdata(0), - I1 => p_6_in, - I2 => \^ip_irpt_enable_reg_reg[0]\, - I3 => p_1_in(0), - O => \ip_irpt_enable_reg_reg[0]_0\ - ); -ipif_glbl_irpt_enable_reg_i_1: unisim.vcomponents.LUT4 - generic map( - INIT => X"FB08" - ) - port map ( - I0 => s_axi_wdata(27), - I1 => p_9_in, - I2 => \^ip_irpt_enable_reg_reg[0]\, - I3 => p_0_in(0), - O => ipif_glbl_irpt_enable_reg_reg - ); -irpt_rdack_d1_i_1: unisim.vcomponents.LUT4 - generic map( - INIT => X"FE00" - ) - port map ( - I0 => p_9_in, - I1 => \^ip2bus_data_i_d1_reg[0]\, - I2 => p_6_in, - I3 => \^ip_irpt_enable_reg_reg[0]\, - O => irpt_rdack - ); -irpt_wrack_d1_i_1: unisim.vcomponents.LUT4 - generic map( - INIT => X"00FE" + INIT => X"AAAAAAAAAABAAAAA" ) port map ( - I0 => p_9_in, - I1 => \^ip2bus_data_i_d1_reg[0]\, - I2 => p_6_in, - I3 => \^ip_irpt_enable_reg_reg[0]\, - O => irpt_wrack + I0 => rst_reg, + I1 => bus2ip_rnw_i_reg, + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(0), + I5 => Q(1), + O => \Not_Dual.gpio_OE_reg[0]\(0) ); s_axi_arready_INST_0: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFF00020000" + INIT => X"AAAAAAAAAAAEAAAA" ) port map ( - I0 => Q(3), - I1 => Q(2), - I2 => Q(1), - I3 => Q(0), - I4 => is_read, - I5 => ip2bus_rdack_i_D1, + I0 => ip2bus_rdack_i_D1, + I1 => is_read, + I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2), + I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1), + I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3), + I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0), O => \^s_axi_arready\ ); s_axi_wready_INST_0: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFF00020000" + INIT => X"AAAAAAAAAAAEAAAA" ) port map ( - I0 => Q(3), - I1 => Q(2), - I2 => Q(1), - I3 => Q(0), - I4 => is_write_reg, - I5 => ip2bus_wrack_i_D1, + I0 => ip2bus_wrack_i_D1, + I1 => is_write_reg, + I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2), + I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1), + I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3), + I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0), O => \^s_axi_wready\ ); end STRUCTURE; @@ -1101,9 +493,7 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20_axi_gpio_shield_1_0_cdc_sync is port ( - D : out STD_LOGIC_VECTOR ( 13 downto 0 ); scndry_vect_out : out STD_LOGIC_VECTOR ( 13 downto 0 ); - Q : in STD_LOGIC_VECTOR ( 13 downto 0 ); gpio_io_i : in STD_LOGIC_VECTOR ( 13 downto 0 ); s_axi_aclk : in STD_LOGIC ); @@ -1154,7 +544,6 @@ architecture STRUCTURE of Arty_Z7_20_axi_gpio_shield_1_0_cdc_sync is signal s_level_out_bus_d3_7 : STD_LOGIC; signal s_level_out_bus_d3_8 : STD_LOGIC; signal s_level_out_bus_d3_9 : STD_LOGIC; - signal \^scndry_vect_out\ : STD_LOGIC_VECTOR ( 13 downto 0 ); attribute ASYNC_REG : boolean; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM : string; @@ -1327,7 +716,6 @@ architecture STRUCTURE of Arty_Z7_20_axi_gpio_shield_1_0_cdc_sync is attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; begin - scndry_vect_out(13 downto 0) <= \^scndry_vect_out\(13 downto 0); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE generic map( INIT => '0' @@ -1644,7 +1032,7 @@ begin C => s_axi_aclk, CE => '1', D => s_level_out_bus_d3_0, - Q => \^scndry_vect_out\(0), + Q => scndry_vect_out(0), R => '0' ); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE @@ -1655,7 +1043,7 @@ begin C => s_axi_aclk, CE => '1', D => s_level_out_bus_d3_10, - Q => \^scndry_vect_out\(10), + Q => scndry_vect_out(10), R => '0' ); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE @@ -1666,7 +1054,7 @@ begin C => s_axi_aclk, CE => '1', D => s_level_out_bus_d3_11, - Q => \^scndry_vect_out\(11), + Q => scndry_vect_out(11), R => '0' ); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE @@ -1677,7 +1065,7 @@ begin C => s_axi_aclk, CE => '1', D => s_level_out_bus_d3_12, - Q => \^scndry_vect_out\(12), + Q => scndry_vect_out(12), R => '0' ); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE @@ -1688,7 +1076,7 @@ begin C => s_axi_aclk, CE => '1', D => s_level_out_bus_d3_13, - Q => \^scndry_vect_out\(13), + Q => scndry_vect_out(13), R => '0' ); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE @@ -1699,7 +1087,7 @@ begin C => s_axi_aclk, CE => '1', D => s_level_out_bus_d3_1, - Q => \^scndry_vect_out\(1), + Q => scndry_vect_out(1), R => '0' ); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE @@ -1710,7 +1098,7 @@ begin C => s_axi_aclk, CE => '1', D => s_level_out_bus_d3_2, - Q => \^scndry_vect_out\(2), + Q => scndry_vect_out(2), R => '0' ); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE @@ -1721,7 +1109,7 @@ begin C => s_axi_aclk, CE => '1', D => s_level_out_bus_d3_3, - Q => \^scndry_vect_out\(3), + Q => scndry_vect_out(3), R => '0' ); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE @@ -1732,7 +1120,7 @@ begin C => s_axi_aclk, CE => '1', D => s_level_out_bus_d3_4, - Q => \^scndry_vect_out\(4), + Q => scndry_vect_out(4), R => '0' ); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE @@ -1743,7 +1131,7 @@ begin C => s_axi_aclk, CE => '1', D => s_level_out_bus_d3_5, - Q => \^scndry_vect_out\(5), + Q => scndry_vect_out(5), R => '0' ); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE @@ -1754,7 +1142,7 @@ begin C => s_axi_aclk, CE => '1', D => s_level_out_bus_d3_6, - Q => \^scndry_vect_out\(6), + Q => scndry_vect_out(6), R => '0' ); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE @@ -1765,7 +1153,7 @@ begin C => s_axi_aclk, CE => '1', D => s_level_out_bus_d3_7, - Q => \^scndry_vect_out\(7), + Q => scndry_vect_out(7), R => '0' ); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE @@ -1776,7 +1164,7 @@ begin C => s_axi_aclk, CE => '1', D => s_level_out_bus_d3_8, - Q => \^scndry_vect_out\(8), + Q => scndry_vect_out(8), R => '0' ); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE @@ -1787,7 +1175,7 @@ begin C => s_axi_aclk, CE => '1', D => s_level_out_bus_d3_9, - Q => \^scndry_vect_out\(9), + Q => scndry_vect_out(9), R => '0' ); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE @@ -1944,310 +1332,6 @@ begin Q => s_level_out_bus_d1_cdc_to_9, R => '0' ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[0]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => Q(13), - I1 => \^scndry_vect_out\(13), - O => D(13) - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[10]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => Q(3), - I1 => \^scndry_vect_out\(3), - O => D(3) - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[11]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => Q(2), - I1 => \^scndry_vect_out\(2), - O => D(2) - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[12]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => Q(1), - I1 => \^scndry_vect_out\(1), - O => D(1) - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[13]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => Q(0), - I1 => \^scndry_vect_out\(0), - O => D(0) - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[1]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => Q(12), - I1 => \^scndry_vect_out\(12), - O => D(12) - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[2]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => Q(11), - I1 => \^scndry_vect_out\(11), - O => D(11) - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[3]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => Q(10), - I1 => \^scndry_vect_out\(10), - O => D(10) - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[4]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => Q(9), - I1 => \^scndry_vect_out\(9), - O => D(9) - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[5]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => Q(8), - I1 => \^scndry_vect_out\(8), - O => D(8) - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[6]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => Q(7), - I1 => \^scndry_vect_out\(7), - O => D(7) - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[7]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => Q(6), - I1 => \^scndry_vect_out\(6), - O => D(6) - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[8]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => Q(5), - I1 => \^scndry_vect_out\(5), - O => D(5) - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[9]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => Q(4), - I1 => \^scndry_vect_out\(4), - O => D(4) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_gpio_shield_1_0_interrupt_control is - port ( - irpt_wrack_d1 : out STD_LOGIC; - p_3_in : out STD_LOGIC_VECTOR ( 0 to 0 ); - irpt_rdack_d1 : out STD_LOGIC; - p_1_in : out STD_LOGIC_VECTOR ( 0 to 0 ); - p_0_in : out STD_LOGIC_VECTOR ( 0 to 0 ); - IP2INTC_Irpt_i : out STD_LOGIC; - ip2bus_wrack_i : out STD_LOGIC; - ip2bus_rdack_i : out STD_LOGIC; - bus2ip_reset : in STD_LOGIC; - irpt_wrack : in STD_LOGIC; - s_axi_aclk : in STD_LOGIC; - GPIO_intr : in STD_LOGIC; - interrupt_wrce_strb : in STD_LOGIC; - irpt_rdack : in STD_LOGIC; - intr2bus_rdack0 : in STD_LOGIC; - \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\ : in STD_LOGIC; - \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\ : in STD_LOGIC; - p_8_in : in STD_LOGIC; - s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 ); - Bus_RNW_reg : in STD_LOGIC; - ip2Bus_WrAck_intr_reg_hole : in STD_LOGIC; - bus2ip_rnw : in STD_LOGIC; - GPIO_xferAck_i : in STD_LOGIC; - ip2Bus_RdAck_intr_reg_hole : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_gpio_shield_1_0_interrupt_control : entity is "interrupt_control"; -end Arty_Z7_20_axi_gpio_shield_1_0_interrupt_control; - -architecture STRUCTURE of Arty_Z7_20_axi_gpio_shield_1_0_interrupt_control is - signal \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\ : STD_LOGIC; - signal \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0\ : STD_LOGIC; - signal intr2bus_rdack : STD_LOGIC; - signal intr2bus_wrack : STD_LOGIC; - signal irpt_dly1 : STD_LOGIC; - signal irpt_dly2 : STD_LOGIC; - signal \^irpt_wrack_d1\ : STD_LOGIC; - signal \^p_0_in\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \^p_1_in\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \^p_3_in\ : STD_LOGIC_VECTOR ( 0 to 0 ); -begin - irpt_wrack_d1 <= \^irpt_wrack_d1\; - p_0_in(0) <= \^p_0_in\(0); - p_1_in(0) <= \^p_1_in\(0); - p_3_in(0) <= \^p_3_in\(0); -\DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly1_reg\: unisim.vcomponents.FDSE - port map ( - C => s_axi_aclk, - CE => '1', - D => GPIO_intr, - Q => irpt_dly1, - S => bus2ip_reset - ); -\DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly2_reg\: unisim.vcomponents.FDSE - port map ( - C => s_axi_aclk, - CE => '1', - D => irpt_dly1, - Q => irpt_dly2, - S => bus2ip_reset - ); -\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"F4F4F4F44FF4F4F4" - ) - port map ( - I0 => irpt_dly2, - I1 => irpt_dly1, - I2 => \^p_3_in\(0), - I3 => p_8_in, - I4 => s_axi_wdata(0), - I5 => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0\, - O => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\ - ); -\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2\: unisim.vcomponents.LUT2 - generic map( - INIT => X"E" - ) - port map ( - I0 => \^irpt_wrack_d1\, - I1 => Bus_RNW_reg, - O => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0\ - ); -\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\, - Q => \^p_3_in\(0), - R => bus2ip_reset - ); -\INTR_CTRLR_GEN.ip2intc_irpt_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"80" - ) - port map ( - I0 => \^p_3_in\(0), - I1 => \^p_1_in\(0), - I2 => \^p_0_in\(0), - O => IP2INTC_Irpt_i - ); -intr2bus_rdack_reg: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => intr2bus_rdack0, - Q => intr2bus_rdack, - R => bus2ip_reset - ); -intr2bus_wrack_reg: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => interrupt_wrce_strb, - Q => intr2bus_wrack, - R => bus2ip_reset - ); -ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT4 - generic map( - INIT => X"FEEE" - ) - port map ( - I0 => ip2Bus_RdAck_intr_reg_hole, - I1 => intr2bus_rdack, - I2 => bus2ip_rnw, - I3 => GPIO_xferAck_i, - O => ip2bus_rdack_i - ); -ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT4 - generic map( - INIT => X"EFEE" - ) - port map ( - I0 => ip2Bus_WrAck_intr_reg_hole, - I1 => intr2bus_wrack, - I2 => bus2ip_rnw, - I3 => GPIO_xferAck_i, - O => ip2bus_wrack_i - ); -\ip_irpt_enable_reg_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\, - Q => \^p_1_in\(0), - R => bus2ip_reset - ); -ipif_glbl_irpt_enable_reg_reg: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\, - Q => \^p_0_in\(0), - R => bus2ip_reset - ); -irpt_rdack_d1_reg: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => irpt_rdack, - Q => irpt_rdack_d1, - R => bus2ip_reset - ); -irpt_wrack_d1_reg: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => irpt_wrack, - Q => \^irpt_wrack_d1\, - R => bus2ip_reset - ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; @@ -2255,35 +1339,37 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20_axi_gpio_shield_1_0_GPIO_Core is port ( - ip2bus_data : out STD_LOGIC_VECTOR ( 13 downto 0 ); + D : out STD_LOGIC_VECTOR ( 13 downto 0 ); GPIO_xferAck_i : out STD_LOGIC; gpio_xferAck_Reg : out STD_LOGIC; - GPIO_intr : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 13 downto 0 ); + ip2bus_rdack_i : out STD_LOGIC; + ip2bus_wrack_i_D1_reg : out STD_LOGIC; gpio_io_o : out STD_LOGIC_VECTOR ( 13 downto 0 ); gpio_io_t : out STD_LOGIC_VECTOR ( 13 downto 0 ); - Read_Reg_Rst : in STD_LOGIC; - \Not_Dual.gpio_OE_reg[13]_0\ : in STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 13 downto 0 ); + bus2ip_rnw_i_reg : in STD_LOGIC; + \Not_Dual.gpio_Data_In_reg[13]_0\ : in STD_LOGIC; s_axi_aclk : in STD_LOGIC; - \Not_Dual.gpio_OE_reg[12]_0\ : in STD_LOGIC; - \Not_Dual.gpio_OE_reg[11]_0\ : in STD_LOGIC; - \Not_Dual.gpio_OE_reg[10]_0\ : in STD_LOGIC; - \Not_Dual.gpio_OE_reg[9]_0\ : in STD_LOGIC; - \Not_Dual.gpio_OE_reg[8]_0\ : in STD_LOGIC; - \Not_Dual.gpio_OE_reg[7]_0\ : in STD_LOGIC; - \Not_Dual.gpio_OE_reg[6]_0\ : in STD_LOGIC; - \Not_Dual.gpio_OE_reg[5]_0\ : in STD_LOGIC; - \Not_Dual.gpio_OE_reg[4]_0\ : in STD_LOGIC; - \Not_Dual.gpio_OE_reg[3]_0\ : in STD_LOGIC; - \Not_Dual.gpio_OE_reg[2]_0\ : in STD_LOGIC; - \Not_Dual.gpio_OE_reg[1]_0\ : in STD_LOGIC; + \Not_Dual.gpio_Data_In_reg[12]_0\ : in STD_LOGIC; + \Not_Dual.gpio_Data_In_reg[11]_0\ : in STD_LOGIC; + \Not_Dual.gpio_Data_In_reg[10]_0\ : in STD_LOGIC; + \Not_Dual.gpio_Data_In_reg[9]_0\ : in STD_LOGIC; + \Not_Dual.gpio_Data_In_reg[8]_0\ : in STD_LOGIC; + \Not_Dual.gpio_Data_In_reg[7]_0\ : in STD_LOGIC; + \Not_Dual.gpio_Data_In_reg[6]_0\ : in STD_LOGIC; + \Not_Dual.gpio_Data_In_reg[5]_0\ : in STD_LOGIC; + \Not_Dual.gpio_Data_In_reg[4]_0\ : in STD_LOGIC; + \Not_Dual.gpio_Data_In_reg[3]_0\ : in STD_LOGIC; + \Not_Dual.gpio_Data_In_reg[2]_0\ : in STD_LOGIC; + \Not_Dual.gpio_Data_In_reg[1]_0\ : in STD_LOGIC; GPIO_DBus_i : in STD_LOGIC_VECTOR ( 0 to 0 ); - bus2ip_reset : in STD_LOGIC; - bus2ip_cs : in STD_LOGIC_VECTOR ( 0 to 0 ); + SS : in STD_LOGIC_VECTOR ( 0 to 0 ); + bus2ip_rnw : in STD_LOGIC; + bus2ip_cs : in STD_LOGIC; gpio_io_i : in STD_LOGIC_VECTOR ( 13 downto 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ); - D : in STD_LOGIC_VECTOR ( 13 downto 0 ); - bus2ip_rnw_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ) + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : in STD_LOGIC_VECTOR ( 13 downto 0 ); + rst_reg : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of Arty_Z7_20_axi_gpio_shield_1_0_GPIO_Core : entity is "GPIO_Core"; @@ -2291,206 +1377,17 @@ end Arty_Z7_20_axi_gpio_shield_1_0_GPIO_Core; architecture STRUCTURE of Arty_Z7_20_axi_gpio_shield_1_0_GPIO_Core is signal \^gpio_xferack_i\ : STD_LOGIC; - signal \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0\ : STD_LOGIC; - signal \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3_n_0\ : STD_LOGIC; - signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0]\ : STD_LOGIC; - signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[11]\ : STD_LOGIC; - signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[13]\ : STD_LOGIC; - signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1]\ : STD_LOGIC; - signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[8]\ : STD_LOGIC; - signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[9]\ : STD_LOGIC; - signal \^q\ : STD_LOGIC_VECTOR ( 13 downto 0 ); - signal gpio_data_in_xor : STD_LOGIC_VECTOR ( 0 to 13 ); signal gpio_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 13 ); signal \^gpio_xferack_reg\ : STD_LOGIC; signal iGPIO_xferAck : STD_LOGIC; - signal or_ints : STD_LOGIC; - signal p_11_in : STD_LOGIC; - signal p_1_in : STD_LOGIC; - signal p_2_in : STD_LOGIC; - signal p_3_in : STD_LOGIC; - signal p_4_in : STD_LOGIC; - signal p_5_in : STD_LOGIC; - signal p_6_in : STD_LOGIC; - signal p_9_in : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of iGPIO_xferAck_i_1 : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of ip2bus_rdack_i_D1_i_1 : label is "soft_lutpair4"; begin GPIO_xferAck_i <= \^gpio_xferack_i\; - Q(13 downto 0) <= \^q\(13 downto 0); gpio_xferAck_Reg <= \^gpio_xferack_reg\; -\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFFFFFFFFFFFFE" - ) - port map ( - I0 => \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0\, - I1 => \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3_n_0\, - I2 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[8]\, - I3 => p_6_in, - I4 => p_9_in, - I5 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[9]\, - O => or_ints - ); -\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFFFFFFFFFFFFE" - ) - port map ( - I0 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1]\, - I1 => p_1_in, - I2 => p_4_in, - I3 => p_5_in, - I4 => p_2_in, - I5 => p_3_in, - O => \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0\ - ); -\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3\: unisim.vcomponents.LUT4 - generic map( - INIT => X"FFFE" - ) - port map ( - I0 => p_11_in, - I1 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[11]\, - I2 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0]\, - I3 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[13]\, - O => \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3_n_0\ - ); -\Not_Dual.GEN_INTERRUPT.GPIO_intr_reg\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => or_ints, - Q => GPIO_intr, - R => bus2ip_reset - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => gpio_data_in_xor(0), - Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0]\, - R => bus2ip_reset - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[10]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => gpio_data_in_xor(10), - Q => p_9_in, - R => bus2ip_reset - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[11]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => gpio_data_in_xor(11), - Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[11]\, - R => bus2ip_reset - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[12]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => gpio_data_in_xor(12), - Q => p_11_in, - R => bus2ip_reset - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[13]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => gpio_data_in_xor(13), - Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[13]\, - R => bus2ip_reset - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => gpio_data_in_xor(1), - Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1]\, - R => bus2ip_reset - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => gpio_data_in_xor(2), - Q => p_1_in, - R => bus2ip_reset - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => gpio_data_in_xor(3), - Q => p_2_in, - R => bus2ip_reset - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => gpio_data_in_xor(4), - Q => p_3_in, - R => bus2ip_reset - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => gpio_data_in_xor(5), - Q => p_4_in, - R => bus2ip_reset - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => gpio_data_in_xor(6), - Q => p_5_in, - R => bus2ip_reset - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => gpio_data_in_xor(7), - Q => p_6_in, - R => bus2ip_reset - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[8]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => gpio_data_in_xor(8), - Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[8]\, - R => bus2ip_reset - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[9]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => gpio_data_in_xor(9), - Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[9]\, - R => bus2ip_reset - ); \Not_Dual.INPUT_DOUBLE_REGS3\: entity work.Arty_Z7_20_axi_gpio_shield_1_0_cdc_sync port map ( - D(13) => gpio_data_in_xor(0), - D(12) => gpio_data_in_xor(1), - D(11) => gpio_data_in_xor(2), - D(10) => gpio_data_in_xor(3), - D(9) => gpio_data_in_xor(4), - D(8) => gpio_data_in_xor(5), - D(7) => gpio_data_in_xor(6), - D(6) => gpio_data_in_xor(7), - D(5) => gpio_data_in_xor(8), - D(4) => gpio_data_in_xor(9), - D(3) => gpio_data_in_xor(10), - D(2) => gpio_data_in_xor(11), - D(1) => gpio_data_in_xor(12), - D(0) => gpio_data_in_xor(13), - Q(13 downto 0) => \^q\(13 downto 0), gpio_io_i(13 downto 0) => gpio_io_i(13 downto 0), s_axi_aclk => s_axi_aclk, scndry_vect_out(13) => gpio_io_i_d2(0), @@ -2513,119 +1410,119 @@ begin C => s_axi_aclk, CE => '1', D => GPIO_DBus_i(0), - Q => ip2bus_data(13), - R => Read_Reg_Rst + Q => D(13), + R => bus2ip_rnw_i_reg ); \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \Not_Dual.gpio_OE_reg[10]_0\, - Q => ip2bus_data(3), - R => Read_Reg_Rst + D => \Not_Dual.gpio_Data_In_reg[10]_0\, + Q => D(3), + R => bus2ip_rnw_i_reg ); \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \Not_Dual.gpio_OE_reg[11]_0\, - Q => ip2bus_data(2), - R => Read_Reg_Rst + D => \Not_Dual.gpio_Data_In_reg[11]_0\, + Q => D(2), + R => bus2ip_rnw_i_reg ); \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \Not_Dual.gpio_OE_reg[12]_0\, - Q => ip2bus_data(1), - R => Read_Reg_Rst + D => \Not_Dual.gpio_Data_In_reg[12]_0\, + Q => D(1), + R => bus2ip_rnw_i_reg ); \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \Not_Dual.gpio_OE_reg[13]_0\, - Q => ip2bus_data(0), - R => Read_Reg_Rst + D => \Not_Dual.gpio_Data_In_reg[13]_0\, + Q => D(0), + R => bus2ip_rnw_i_reg ); \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \Not_Dual.gpio_OE_reg[1]_0\, - Q => ip2bus_data(12), - R => Read_Reg_Rst + D => \Not_Dual.gpio_Data_In_reg[1]_0\, + Q => D(12), + R => bus2ip_rnw_i_reg ); \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \Not_Dual.gpio_OE_reg[2]_0\, - Q => ip2bus_data(11), - R => Read_Reg_Rst + D => \Not_Dual.gpio_Data_In_reg[2]_0\, + Q => D(11), + R => bus2ip_rnw_i_reg ); \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \Not_Dual.gpio_OE_reg[3]_0\, - Q => ip2bus_data(10), - R => Read_Reg_Rst + D => \Not_Dual.gpio_Data_In_reg[3]_0\, + Q => D(10), + R => bus2ip_rnw_i_reg ); \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \Not_Dual.gpio_OE_reg[4]_0\, - Q => ip2bus_data(9), - R => Read_Reg_Rst + D => \Not_Dual.gpio_Data_In_reg[4]_0\, + Q => D(9), + R => bus2ip_rnw_i_reg ); \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \Not_Dual.gpio_OE_reg[5]_0\, - Q => ip2bus_data(8), - R => Read_Reg_Rst + D => \Not_Dual.gpio_Data_In_reg[5]_0\, + Q => D(8), + R => bus2ip_rnw_i_reg ); \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \Not_Dual.gpio_OE_reg[6]_0\, - Q => ip2bus_data(7), - R => Read_Reg_Rst + D => \Not_Dual.gpio_Data_In_reg[6]_0\, + Q => D(7), + R => bus2ip_rnw_i_reg ); \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \Not_Dual.gpio_OE_reg[7]_0\, - Q => ip2bus_data(6), - R => Read_Reg_Rst + D => \Not_Dual.gpio_Data_In_reg[7]_0\, + Q => D(6), + R => bus2ip_rnw_i_reg ); \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \Not_Dual.gpio_OE_reg[8]_0\, - Q => ip2bus_data(5), - R => Read_Reg_Rst + D => \Not_Dual.gpio_Data_In_reg[8]_0\, + Q => D(5), + R => bus2ip_rnw_i_reg ); \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \Not_Dual.gpio_OE_reg[9]_0\, - Q => ip2bus_data(4), - R => Read_Reg_Rst + D => \Not_Dual.gpio_Data_In_reg[9]_0\, + Q => D(4), + R => bus2ip_rnw_i_reg ); \Not_Dual.gpio_Data_In_reg[0]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => gpio_io_i_d2(0), - Q => \^q\(13), + Q => Q(13), R => '0' ); \Not_Dual.gpio_Data_In_reg[10]\: unisim.vcomponents.FDRE @@ -2633,7 +1530,7 @@ begin C => s_axi_aclk, CE => '1', D => gpio_io_i_d2(10), - Q => \^q\(3), + Q => Q(3), R => '0' ); \Not_Dual.gpio_Data_In_reg[11]\: unisim.vcomponents.FDRE @@ -2641,7 +1538,7 @@ begin C => s_axi_aclk, CE => '1', D => gpio_io_i_d2(11), - Q => \^q\(2), + Q => Q(2), R => '0' ); \Not_Dual.gpio_Data_In_reg[12]\: unisim.vcomponents.FDRE @@ -2649,7 +1546,7 @@ begin C => s_axi_aclk, CE => '1', D => gpio_io_i_d2(12), - Q => \^q\(1), + Q => Q(1), R => '0' ); \Not_Dual.gpio_Data_In_reg[13]\: unisim.vcomponents.FDRE @@ -2657,7 +1554,7 @@ begin C => s_axi_aclk, CE => '1', D => gpio_io_i_d2(13), - Q => \^q\(0), + Q => Q(0), R => '0' ); \Not_Dual.gpio_Data_In_reg[1]\: unisim.vcomponents.FDRE @@ -2665,7 +1562,7 @@ begin C => s_axi_aclk, CE => '1', D => gpio_io_i_d2(1), - Q => \^q\(12), + Q => Q(12), R => '0' ); \Not_Dual.gpio_Data_In_reg[2]\: unisim.vcomponents.FDRE @@ -2673,7 +1570,7 @@ begin C => s_axi_aclk, CE => '1', D => gpio_io_i_d2(2), - Q => \^q\(11), + Q => Q(11), R => '0' ); \Not_Dual.gpio_Data_In_reg[3]\: unisim.vcomponents.FDRE @@ -2681,7 +1578,7 @@ begin C => s_axi_aclk, CE => '1', D => gpio_io_i_d2(3), - Q => \^q\(10), + Q => Q(10), R => '0' ); \Not_Dual.gpio_Data_In_reg[4]\: unisim.vcomponents.FDRE @@ -2689,7 +1586,7 @@ begin C => s_axi_aclk, CE => '1', D => gpio_io_i_d2(4), - Q => \^q\(9), + Q => Q(9), R => '0' ); \Not_Dual.gpio_Data_In_reg[5]\: unisim.vcomponents.FDRE @@ -2697,7 +1594,7 @@ begin C => s_axi_aclk, CE => '1', D => gpio_io_i_d2(5), - Q => \^q\(8), + Q => Q(8), R => '0' ); \Not_Dual.gpio_Data_In_reg[6]\: unisim.vcomponents.FDRE @@ -2705,7 +1602,7 @@ begin C => s_axi_aclk, CE => '1', D => gpio_io_i_d2(6), - Q => \^q\(7), + Q => Q(7), R => '0' ); \Not_Dual.gpio_Data_In_reg[7]\: unisim.vcomponents.FDRE @@ -2713,7 +1610,7 @@ begin C => s_axi_aclk, CE => '1', D => gpio_io_i_d2(7), - Q => \^q\(6), + Q => Q(6), R => '0' ); \Not_Dual.gpio_Data_In_reg[8]\: unisim.vcomponents.FDRE @@ -2721,7 +1618,7 @@ begin C => s_axi_aclk, CE => '1', D => gpio_io_i_d2(8), - Q => \^q\(5), + Q => Q(5), R => '0' ); \Not_Dual.gpio_Data_In_reg[9]\: unisim.vcomponents.FDRE @@ -2729,7 +1626,7 @@ begin C => s_axi_aclk, CE => '1', D => gpio_io_i_d2(9), - Q => \^q\(4), + Q => Q(4), R => '0' ); \Not_Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE @@ -2739,9 +1636,9 @@ begin port map ( C => s_axi_aclk, CE => E(0), - D => D(13), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(13), Q => gpio_io_o(13), - R => bus2ip_reset + R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[10]\: unisim.vcomponents.FDRE generic map( @@ -2750,9 +1647,9 @@ begin port map ( C => s_axi_aclk, CE => E(0), - D => D(3), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(3), Q => gpio_io_o(3), - R => bus2ip_reset + R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[11]\: unisim.vcomponents.FDRE generic map( @@ -2761,9 +1658,9 @@ begin port map ( C => s_axi_aclk, CE => E(0), - D => D(2), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(2), Q => gpio_io_o(2), - R => bus2ip_reset + R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[12]\: unisim.vcomponents.FDRE generic map( @@ -2772,9 +1669,9 @@ begin port map ( C => s_axi_aclk, CE => E(0), - D => D(1), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(1), Q => gpio_io_o(1), - R => bus2ip_reset + R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[13]\: unisim.vcomponents.FDRE generic map( @@ -2783,9 +1680,9 @@ begin port map ( C => s_axi_aclk, CE => E(0), - D => D(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(0), Q => gpio_io_o(0), - R => bus2ip_reset + R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[1]\: unisim.vcomponents.FDRE generic map( @@ -2794,9 +1691,9 @@ begin port map ( C => s_axi_aclk, CE => E(0), - D => D(12), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(12), Q => gpio_io_o(12), - R => bus2ip_reset + R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[2]\: unisim.vcomponents.FDRE generic map( @@ -2805,9 +1702,9 @@ begin port map ( C => s_axi_aclk, CE => E(0), - D => D(11), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(11), Q => gpio_io_o(11), - R => bus2ip_reset + R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[3]\: unisim.vcomponents.FDRE generic map( @@ -2816,9 +1713,9 @@ begin port map ( C => s_axi_aclk, CE => E(0), - D => D(10), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(10), Q => gpio_io_o(10), - R => bus2ip_reset + R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[4]\: unisim.vcomponents.FDRE generic map( @@ -2827,9 +1724,9 @@ begin port map ( C => s_axi_aclk, CE => E(0), - D => D(9), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(9), Q => gpio_io_o(9), - R => bus2ip_reset + R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[5]\: unisim.vcomponents.FDRE generic map( @@ -2838,9 +1735,9 @@ begin port map ( C => s_axi_aclk, CE => E(0), - D => D(8), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(8), Q => gpio_io_o(8), - R => bus2ip_reset + R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[6]\: unisim.vcomponents.FDRE generic map( @@ -2849,9 +1746,9 @@ begin port map ( C => s_axi_aclk, CE => E(0), - D => D(7), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(7), Q => gpio_io_o(7), - R => bus2ip_reset + R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[7]\: unisim.vcomponents.FDRE generic map( @@ -2860,9 +1757,9 @@ begin port map ( C => s_axi_aclk, CE => E(0), - D => D(6), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(6), Q => gpio_io_o(6), - R => bus2ip_reset + R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[8]\: unisim.vcomponents.FDRE generic map( @@ -2871,9 +1768,9 @@ begin port map ( C => s_axi_aclk, CE => E(0), - D => D(5), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(5), Q => gpio_io_o(5), - R => bus2ip_reset + R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[9]\: unisim.vcomponents.FDRE generic map( @@ -2882,9 +1779,9 @@ begin port map ( C => s_axi_aclk, CE => E(0), - D => D(4), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(4), Q => gpio_io_o(4), - R => bus2ip_reset + R => SS(0) ); \Not_Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE generic map( @@ -2892,10 +1789,10 @@ begin ) port map ( C => s_axi_aclk, - CE => bus2ip_rnw_i_reg(0), - D => D(13), + CE => rst_reg(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(13), Q => gpio_io_t(13), - S => bus2ip_reset + S => SS(0) ); \Not_Dual.gpio_OE_reg[10]\: unisim.vcomponents.FDSE generic map( @@ -2903,10 +1800,10 @@ begin ) port map ( C => s_axi_aclk, - CE => bus2ip_rnw_i_reg(0), - D => D(3), + CE => rst_reg(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(3), Q => gpio_io_t(3), - S => bus2ip_reset + S => SS(0) ); \Not_Dual.gpio_OE_reg[11]\: unisim.vcomponents.FDSE generic map( @@ -2914,10 +1811,10 @@ begin ) port map ( C => s_axi_aclk, - CE => bus2ip_rnw_i_reg(0), - D => D(2), + CE => rst_reg(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(2), Q => gpio_io_t(2), - S => bus2ip_reset + S => SS(0) ); \Not_Dual.gpio_OE_reg[12]\: unisim.vcomponents.FDSE generic map( @@ -2925,10 +1822,10 @@ begin ) port map ( C => s_axi_aclk, - CE => bus2ip_rnw_i_reg(0), - D => D(1), + CE => rst_reg(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(1), Q => gpio_io_t(1), - S => bus2ip_reset + S => SS(0) ); \Not_Dual.gpio_OE_reg[13]\: unisim.vcomponents.FDSE generic map( @@ -2936,10 +1833,10 @@ begin ) port map ( C => s_axi_aclk, - CE => bus2ip_rnw_i_reg(0), - D => D(0), + CE => rst_reg(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(0), Q => gpio_io_t(0), - S => bus2ip_reset + S => SS(0) ); \Not_Dual.gpio_OE_reg[1]\: unisim.vcomponents.FDSE generic map( @@ -2947,10 +1844,10 @@ begin ) port map ( C => s_axi_aclk, - CE => bus2ip_rnw_i_reg(0), - D => D(12), + CE => rst_reg(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(12), Q => gpio_io_t(12), - S => bus2ip_reset + S => SS(0) ); \Not_Dual.gpio_OE_reg[2]\: unisim.vcomponents.FDSE generic map( @@ -2958,10 +1855,10 @@ begin ) port map ( C => s_axi_aclk, - CE => bus2ip_rnw_i_reg(0), - D => D(11), + CE => rst_reg(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(11), Q => gpio_io_t(11), - S => bus2ip_reset + S => SS(0) ); \Not_Dual.gpio_OE_reg[3]\: unisim.vcomponents.FDSE generic map( @@ -2969,10 +1866,10 @@ begin ) port map ( C => s_axi_aclk, - CE => bus2ip_rnw_i_reg(0), - D => D(10), + CE => rst_reg(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(10), Q => gpio_io_t(10), - S => bus2ip_reset + S => SS(0) ); \Not_Dual.gpio_OE_reg[4]\: unisim.vcomponents.FDSE generic map( @@ -2980,10 +1877,10 @@ begin ) port map ( C => s_axi_aclk, - CE => bus2ip_rnw_i_reg(0), - D => D(9), + CE => rst_reg(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(9), Q => gpio_io_t(9), - S => bus2ip_reset + S => SS(0) ); \Not_Dual.gpio_OE_reg[5]\: unisim.vcomponents.FDSE generic map( @@ -2991,10 +1888,10 @@ begin ) port map ( C => s_axi_aclk, - CE => bus2ip_rnw_i_reg(0), - D => D(8), + CE => rst_reg(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(8), Q => gpio_io_t(8), - S => bus2ip_reset + S => SS(0) ); \Not_Dual.gpio_OE_reg[6]\: unisim.vcomponents.FDSE generic map( @@ -3002,10 +1899,10 @@ begin ) port map ( C => s_axi_aclk, - CE => bus2ip_rnw_i_reg(0), - D => D(7), + CE => rst_reg(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(7), Q => gpio_io_t(7), - S => bus2ip_reset + S => SS(0) ); \Not_Dual.gpio_OE_reg[7]\: unisim.vcomponents.FDSE generic map( @@ -3013,10 +1910,10 @@ begin ) port map ( C => s_axi_aclk, - CE => bus2ip_rnw_i_reg(0), - D => D(6), + CE => rst_reg(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(6), Q => gpio_io_t(6), - S => bus2ip_reset + S => SS(0) ); \Not_Dual.gpio_OE_reg[8]\: unisim.vcomponents.FDSE generic map( @@ -3024,10 +1921,10 @@ begin ) port map ( C => s_axi_aclk, - CE => bus2ip_rnw_i_reg(0), - D => D(5), + CE => rst_reg(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(5), Q => gpio_io_t(5), - S => bus2ip_reset + S => SS(0) ); \Not_Dual.gpio_OE_reg[9]\: unisim.vcomponents.FDSE generic map( @@ -3035,10 +1932,10 @@ begin ) port map ( C => s_axi_aclk, - CE => bus2ip_rnw_i_reg(0), - D => D(4), + CE => rst_reg(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(4), Q => gpio_io_t(4), - S => bus2ip_reset + S => SS(0) ); gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE port map ( @@ -3046,16 +1943,16 @@ gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE CE => '1', D => \^gpio_xferack_i\, Q => \^gpio_xferack_reg\, - R => bus2ip_reset + R => SS(0) ); iGPIO_xferAck_i_1: unisim.vcomponents.LUT3 generic map( - INIT => X"10" + INIT => X"02" ) port map ( - I0 => \^gpio_xferack_reg\, - I1 => \^gpio_xferack_i\, - I2 => bus2ip_cs(0), + I0 => bus2ip_cs, + I1 => \^gpio_xferack_reg\, + I2 => \^gpio_xferack_i\, O => iGPIO_xferAck ); iGPIO_xferAck_reg: unisim.vcomponents.FDRE @@ -3064,7 +1961,25 @@ iGPIO_xferAck_reg: unisim.vcomponents.FDRE CE => '1', D => iGPIO_xferAck, Q => \^gpio_xferack_i\, - R => bus2ip_reset + R => SS(0) + ); +ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^gpio_xferack_i\, + I1 => bus2ip_rnw, + O => ip2bus_rdack_i + ); +ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^gpio_xferack_i\, + I1 => bus2ip_rnw, + O => ip2bus_wrack_i_D1_reg ); end STRUCTURE; library IEEE; @@ -3073,70 +1988,49 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20_axi_gpio_shield_1_0_slave_attachment is port ( - \ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC; - \Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC; - \Not_Dual.gpio_Data_Out_reg[13]\ : out STD_LOGIC; - \ip_irpt_enable_reg_reg[0]\ : out STD_LOGIC; + SR : out STD_LOGIC; + \Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC; + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_bvalid : out STD_LOGIC; s_axi_arready : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wready : out STD_LOGIC; - D : out STD_LOGIC_VECTOR ( 13 downto 0 ); - \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[31]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[24]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[23]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[22]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[21]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[20]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[19]\ : out STD_LOGIC; GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 ); - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - \Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - \ip2bus_data_i_D1_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); - intr2bus_rdack0 : out STD_LOGIC; - irpt_rdack : out STD_LOGIC; - irpt_wrack : out STD_LOGIC; - interrupt_wrce_strb : out STD_LOGIC; - Read_Reg_Rst : out STD_LOGIC; - \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ : out STD_LOGIC; - intr_rd_ce_or_reduce : out STD_LOGIC; - \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC; - intr_wr_ce_or_reduce : out STD_LOGIC; - \ip_irpt_enable_reg_reg[0]_0\ : out STD_LOGIC; - ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC; - s_axi_rdata : out STD_LOGIC_VECTOR ( 14 downto 0 ); - bus2ip_reset : in STD_LOGIC; + \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[19]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[20]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[21]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[22]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[23]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[24]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[31]\ : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 13 downto 0 ); + \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[18]\ : out STD_LOGIC; + s_axi_rdata : out STD_LOGIC_VECTOR ( 13 downto 0 ); s_axi_aclk : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; + s_axi_awvalid : in STD_LOGIC; + s_axi_wvalid : in STD_LOGIC; + s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_aresetn : in STD_LOGIC; + s_axi_rready : in STD_LOGIC; + s_axi_bready : in STD_LOGIC; ip2bus_rdack_i_D1 : in STD_LOGIC; ip2bus_wrack_i_D1 : in STD_LOGIC; - s_axi_bready : in STD_LOGIC; - s_axi_rready : in STD_LOGIC; - s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 ); - s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 ); - s_axi_awvalid : in STD_LOGIC; - s_axi_wvalid : in STD_LOGIC; - s_axi_wdata : in STD_LOGIC_VECTOR ( 27 downto 0 ); - gpio_io_t : in STD_LOGIC_VECTOR ( 13 downto 0 ); Q : in STD_LOGIC_VECTOR ( 13 downto 0 ); - p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); - irpt_rdack_d1 : in STD_LOGIC; - irpt_wrack_d1 : in STD_LOGIC; - ip2bus_data : in STD_LOGIC_VECTOR ( 0 to 0 ); - p_3_in : in STD_LOGIC_VECTOR ( 0 to 0 ); - p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 ); - GPIO_xferAck_i : in STD_LOGIC; + gpio_io_t : in STD_LOGIC_VECTOR ( 13 downto 0 ); + s_axi_wdata : in STD_LOGIC_VECTOR ( 27 downto 0 ); gpio_xferAck_Reg : in STD_LOGIC; - ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC; - ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC; - \ip2bus_data_i_D1_reg[0]_1\ : in STD_LOGIC_VECTOR ( 14 downto 0 ) + GPIO_xferAck_i : in STD_LOGIC; + \ip2bus_data_i_D1_reg[18]\ : in STD_LOGIC_VECTOR ( 13 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of Arty_Z7_20_axi_gpio_shield_1_0_slave_attachment : entity is "slave_attachment"; @@ -3144,8 +2038,13 @@ end Arty_Z7_20_axi_gpio_shield_1_0_slave_attachment; architecture STRUCTURE of Arty_Z7_20_axi_gpio_shield_1_0_slave_attachment is signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal \^not_dual.gpio_oe_reg[0]\ : STD_LOGIC; + signal \^not_dual.gpio_data_out_reg[0]\ : STD_LOGIC; + signal \^sr\ : STD_LOGIC; signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 6 ); + signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC; + signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC; + signal \bus2ip_addr_i[8]_i_1_n_0\ : STD_LOGIC; + signal \bus2ip_addr_i[8]_i_2_n_0\ : STD_LOGIC; signal bus2ip_rnw_i06_out : STD_LOGIC; signal clear : STD_LOGIC; signal is_read : STD_LOGIC; @@ -3153,30 +2052,33 @@ architecture STRUCTURE of Arty_Z7_20_axi_gpio_shield_1_0_slave_attachment is signal is_write : STD_LOGIC; signal is_write_i_1_n_0 : STD_LOGIC; signal is_write_reg_n_0 : STD_LOGIC; - signal \p_0_out__0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 8 downto 2 ); + signal p_0_out : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal p_1_in : STD_LOGIC; signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^s_axi_arready\ : STD_LOGIC; signal \^s_axi_bvalid\ : STD_LOGIC; signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC; - signal s_axi_rdata_i : STD_LOGIC; + signal \s_axi_rdata_i[13]_i_1_n_0\ : STD_LOGIC; signal \^s_axi_rvalid\ : STD_LOGIC; signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC; signal \^s_axi_wready\ : STD_LOGIC; signal start2 : STD_LOGIC; signal start2_i_1_n_0 : STD_LOGIC; signal state : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal \state[1]_i_2_n_0\ : STD_LOGIC; + signal \state1__2\ : STD_LOGIC; signal \state[1]_i_3_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair6"; - attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair6"; - attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair5"; - attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair5"; - attribute SOFT_HLUTNM of \bus2ip_addr_i[4]_i_1\ : label is "soft_lutpair4"; - attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \bus2ip_addr_i[3]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair1"; begin - \Not_Dual.gpio_OE_reg[0]\ <= \^not_dual.gpio_oe_reg[0]\; + \Not_Dual.gpio_Data_Out_reg[0]\ <= \^not_dual.gpio_data_out_reg[0]\; + SR <= \^sr\; s_axi_arready <= \^s_axi_arready\; s_axi_bvalid <= \^s_axi_bvalid\; s_axi_rvalid <= \^s_axi_rvalid\; @@ -3203,8 +2105,8 @@ begin INIT => X"78" ) port map ( - I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), - I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), + I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), + I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), O => plusOp(2) ); @@ -3213,8 +2115,8 @@ begin INIT => X"9" ) port map ( - I0 => state(1), - I1 => state(0), + I0 => state(0), + I1 => state(1), O => clear ); \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4 @@ -3222,9 +2124,9 @@ begin INIT => X"7F80" ) port map ( - I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), + I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), - I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), + I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3), O => plusOp(3) ); @@ -3266,8 +2168,9 @@ I_DECODER: entity work.Arty_Z7_20_axi_gpio_shield_1_0_address_decoder E(0) => E(0), GPIO_DBus_i(0) => GPIO_DBus_i(0), GPIO_xferAck_i => GPIO_xferAck_i, - \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\, - \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\, + \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\, + \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[18]\ => \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[18]\, \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28]\ => \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28]\, \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29]\ => \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29]\, \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30]\ => \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30]\, @@ -3282,208 +2185,114 @@ I_DECODER: entity work.Arty_Z7_20_axi_gpio_shield_1_0_address_decoder \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26]\ => \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26]\, \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27]\ => \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27]\, \Not_Dual.gpio_Data_In_reg[0]\(13 downto 0) => Q(13 downto 0), - \Not_Dual.gpio_Data_Out_reg[0]\(0) => \Not_Dual.gpio_Data_Out_reg[0]\(0), - \Not_Dual.gpio_Data_Out_reg[13]\ => \Not_Dual.gpio_Data_Out_reg[13]\, - Q(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0), - Read_Reg_Rst => Read_Reg_Rst, - \bus2ip_addr_i_reg[8]\(6) => bus2ip_addr(0), - \bus2ip_addr_i_reg[8]\(5) => bus2ip_addr(1), - \bus2ip_addr_i_reg[8]\(4) => bus2ip_addr(2), - \bus2ip_addr_i_reg[8]\(3) => bus2ip_addr(3), - \bus2ip_addr_i_reg[8]\(2) => bus2ip_addr(4), - \bus2ip_addr_i_reg[8]\(1) => bus2ip_addr(5), - \bus2ip_addr_i_reg[8]\(0) => bus2ip_addr(6), - bus2ip_reset => bus2ip_reset, - bus2ip_rnw_i_reg => \^not_dual.gpio_oe_reg[0]\, + \Not_Dual.gpio_OE_reg[0]\(0) => \Not_Dual.gpio_OE_reg[0]\(0), + Q(2) => bus2ip_addr(0), + Q(1) => bus2ip_addr(5), + Q(0) => bus2ip_addr(6), + bus2ip_rnw_i_reg => \^not_dual.gpio_data_out_reg[0]\, gpio_io_t(13 downto 0) => gpio_io_t(13 downto 0), gpio_xferAck_Reg => gpio_xferAck_Reg, - interrupt_wrce_strb => interrupt_wrce_strb, - intr2bus_rdack0 => intr2bus_rdack0, - intr_rd_ce_or_reduce => intr_rd_ce_or_reduce, - intr_wr_ce_or_reduce => intr_wr_ce_or_reduce, - ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1, - ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1, - ip2bus_data(0) => ip2bus_data(0), - \ip2bus_data_i_D1_reg[0]\ => \ip2bus_data_i_D1_reg[0]\, - \ip2bus_data_i_D1_reg[0]_0\(1 downto 0) => \ip2bus_data_i_D1_reg[0]_0\(1 downto 0), ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1, ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1, - \ip_irpt_enable_reg_reg[0]\ => \ip_irpt_enable_reg_reg[0]\, - \ip_irpt_enable_reg_reg[0]_0\ => \ip_irpt_enable_reg_reg[0]_0\, - ipif_glbl_irpt_enable_reg_reg => ipif_glbl_irpt_enable_reg_reg, - irpt_rdack => irpt_rdack, - irpt_rdack_d1 => irpt_rdack_d1, - irpt_wrack => irpt_wrack, - irpt_wrack_d1 => irpt_wrack_d1, is_read => is_read, is_write_reg => is_write_reg_n_0, - p_0_in(0) => p_0_in(0), - p_1_in(0) => p_1_in(0), - p_3_in(0) => p_3_in(0), + rst_reg => \^sr\, s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_arready => \^s_axi_arready\, s_axi_wdata(27 downto 0) => s_axi_wdata(27 downto 0), s_axi_wready => \^s_axi_wready\, - start2 => start2 + start2_reg => start2 ); \bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"ABAAA8AA" + INIT => X"CCCACCCC" ) port map ( - I0 => s_axi_awaddr(0), - I1 => state(1), + I0 => s_axi_araddr(0), + I1 => s_axi_awaddr(0), I2 => state(0), - I3 => s_axi_arvalid, - I4 => s_axi_araddr(0), - O => \p_1_in__0\(2) + I3 => state(1), + I4 => s_axi_arvalid, + O => \bus2ip_addr_i[2]_i_1_n_0\ ); \bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"ABAAA8AA" - ) - port map ( - I0 => s_axi_awaddr(1), - I1 => state(1), - I2 => state(0), - I3 => s_axi_arvalid, - I4 => s_axi_araddr(1), - O => \p_1_in__0\(3) - ); -\bus2ip_addr_i[4]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"ABAAA8AA" - ) - port map ( - I0 => s_axi_awaddr(2), - I1 => state(1), - I2 => state(0), - I3 => s_axi_arvalid, - I4 => s_axi_araddr(2), - O => \p_1_in__0\(4) - ); -\bus2ip_addr_i[5]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"ABAAA8AA" - ) - port map ( - I0 => s_axi_awaddr(3), - I1 => state(1), - I2 => state(0), - I3 => s_axi_arvalid, - I4 => s_axi_araddr(3), - O => \p_1_in__0\(5) - ); -\bus2ip_addr_i[6]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"ABAAA8AA" + INIT => X"CCCACCCC" ) port map ( - I0 => s_axi_awaddr(4), - I1 => state(1), + I0 => s_axi_araddr(1), + I1 => s_axi_awaddr(1), I2 => state(0), - I3 => s_axi_arvalid, - I4 => s_axi_araddr(4), - O => \p_1_in__0\(6) + I3 => state(1), + I4 => s_axi_arvalid, + O => \bus2ip_addr_i[3]_i_1_n_0\ ); -\bus2ip_addr_i[7]_i_1\: unisim.vcomponents.LUT5 +\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"ABAAA8AA" + INIT => X"000000EA" ) port map ( - I0 => s_axi_awaddr(5), - I1 => state(1), - I2 => state(0), - I3 => s_axi_arvalid, - I4 => s_axi_araddr(5), - O => \p_1_in__0\(7) + I0 => s_axi_arvalid, + I1 => s_axi_awvalid, + I2 => s_axi_wvalid, + I3 => state(1), + I4 => state(0), + O => \bus2ip_addr_i[8]_i_1_n_0\ ); -\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5 +\bus2ip_addr_i[8]_i_2\: unisim.vcomponents.LUT5 generic map( - INIT => X"ABAAA8AA" + INIT => X"CCCACCCC" ) port map ( - I0 => s_axi_awaddr(6), - I1 => state(1), + I0 => s_axi_araddr(2), + I1 => s_axi_awaddr(2), I2 => state(0), - I3 => s_axi_arvalid, - I4 => s_axi_araddr(6), - O => \p_1_in__0\(8) + I3 => state(1), + I4 => s_axi_arvalid, + O => \bus2ip_addr_i[8]_i_2_n_0\ ); \bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, - CE => start2_i_1_n_0, - D => \p_1_in__0\(2), + CE => \bus2ip_addr_i[8]_i_1_n_0\, + D => \bus2ip_addr_i[2]_i_1_n_0\, Q => bus2ip_addr(6), - R => bus2ip_reset + R => \^sr\ ); \bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, - CE => start2_i_1_n_0, - D => \p_1_in__0\(3), + CE => \bus2ip_addr_i[8]_i_1_n_0\, + D => \bus2ip_addr_i[3]_i_1_n_0\, Q => bus2ip_addr(5), - R => bus2ip_reset - ); -\bus2ip_addr_i_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2_i_1_n_0, - D => \p_1_in__0\(4), - Q => bus2ip_addr(4), - R => bus2ip_reset - ); -\bus2ip_addr_i_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2_i_1_n_0, - D => \p_1_in__0\(5), - Q => bus2ip_addr(3), - R => bus2ip_reset - ); -\bus2ip_addr_i_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2_i_1_n_0, - D => \p_1_in__0\(6), - Q => bus2ip_addr(2), - R => bus2ip_reset - ); -\bus2ip_addr_i_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2_i_1_n_0, - D => \p_1_in__0\(7), - Q => bus2ip_addr(1), - R => bus2ip_reset + R => \^sr\ ); \bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, - CE => start2_i_1_n_0, - D => \p_1_in__0\(8), + CE => \bus2ip_addr_i[8]_i_1_n_0\, + D => \bus2ip_addr_i[8]_i_2_n_0\, Q => bus2ip_addr(0), - R => bus2ip_reset + R => \^sr\ ); bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3 generic map( - INIT => X"02" + INIT => X"10" ) port map ( - I0 => s_axi_arvalid, - I1 => state(0), - I2 => state(1), + I0 => state(0), + I1 => state(1), + I2 => s_axi_arvalid, O => bus2ip_rnw_i06_out ); bus2ip_rnw_i_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, - CE => start2_i_1_n_0, + CE => \bus2ip_addr_i[8]_i_1_n_0\, D => bus2ip_rnw_i06_out, - Q => \^not_dual.gpio_oe_reg[0]\, - R => bus2ip_reset + Q => \^not_dual.gpio_data_out_reg[0]\, + R => \^sr\ ); is_read_i_1: unisim.vcomponents.LUT5 generic map( @@ -3491,9 +2300,9 @@ is_read_i_1: unisim.vcomponents.LUT5 ) port map ( I0 => s_axi_arvalid, - I1 => \state[1]_i_2_n_0\, - I2 => state(1), - I3 => state(0), + I1 => \state1__2\, + I2 => state(0), + I3 => state(1), I4 => is_read, O => is_read_i_1_n_0 ); @@ -3503,17 +2312,17 @@ is_read_reg: unisim.vcomponents.FDRE CE => '1', D => is_read_i_1_n_0, Q => is_read, - R => bus2ip_reset + R => \^sr\ ); is_write_i_1: unisim.vcomponents.LUT6 generic map( - INIT => X"1000FFFF10000000" + INIT => X"0040FFFF00400000" ) port map ( - I0 => state(1), - I1 => s_axi_arvalid, + I0 => s_axi_arvalid, + I1 => s_axi_awvalid, I2 => s_axi_wvalid, - I3 => s_axi_awvalid, + I3 => state(1), I4 => is_write, I5 => is_write_reg_n_0, O => is_write_i_1_n_0 @@ -3523,12 +2332,12 @@ is_write_i_2: unisim.vcomponents.LUT6 INIT => X"F88800000000FFFF" ) port map ( - I0 => s_axi_bready, - I1 => \^s_axi_bvalid\, - I2 => s_axi_rready, - I3 => \^s_axi_rvalid\, - I4 => state(1), - I5 => state(0), + I0 => \^s_axi_rvalid\, + I1 => s_axi_rready, + I2 => \^s_axi_bvalid\, + I3 => s_axi_bready, + I4 => state(0), + I5 => state(1), O => is_write ); is_write_reg: unisim.vcomponents.FDRE @@ -3537,7 +2346,23 @@ is_write_reg: unisim.vcomponents.FDRE CE => '1', D => is_write_i_1_n_0, Q => is_write_reg_n_0, - R => bus2ip_reset + R => \^sr\ + ); +rst_i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => s_axi_aresetn, + O => p_1_in + ); +rst_reg: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => p_1_in, + Q => \^sr\, + R => '0' ); s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5 generic map( @@ -3560,16 +2385,16 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE CE => '1', D => s_axi_bvalid_i_i_1_n_0, Q => \^s_axi_bvalid\, - R => bus2ip_reset + R => \^sr\ ); -\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2 +\s_axi_rdata_i[13]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => state(0), I1 => state(1), - O => s_axi_rdata_i + O => \s_axi_rdata_i[13]_i_1_n_0\ ); \s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE generic map( @@ -3577,10 +2402,10 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(0), + CE => \s_axi_rdata_i[13]_i_1_n_0\, + D => \ip2bus_data_i_D1_reg[18]\(0), Q => s_axi_rdata(0), - R => bus2ip_reset + R => \^sr\ ); \s_axi_rdata_i_reg[10]\: unisim.vcomponents.FDRE generic map( @@ -3588,10 +2413,10 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(10), + CE => \s_axi_rdata_i[13]_i_1_n_0\, + D => \ip2bus_data_i_D1_reg[18]\(10), Q => s_axi_rdata(10), - R => bus2ip_reset + R => \^sr\ ); \s_axi_rdata_i_reg[11]\: unisim.vcomponents.FDRE generic map( @@ -3599,10 +2424,10 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(11), + CE => \s_axi_rdata_i[13]_i_1_n_0\, + D => \ip2bus_data_i_D1_reg[18]\(11), Q => s_axi_rdata(11), - R => bus2ip_reset + R => \^sr\ ); \s_axi_rdata_i_reg[12]\: unisim.vcomponents.FDRE generic map( @@ -3610,10 +2435,10 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(12), + CE => \s_axi_rdata_i[13]_i_1_n_0\, + D => \ip2bus_data_i_D1_reg[18]\(12), Q => s_axi_rdata(12), - R => bus2ip_reset + R => \^sr\ ); \s_axi_rdata_i_reg[13]\: unisim.vcomponents.FDRE generic map( @@ -3621,10 +2446,10 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(13), + CE => \s_axi_rdata_i[13]_i_1_n_0\, + D => \ip2bus_data_i_D1_reg[18]\(13), Q => s_axi_rdata(13), - R => bus2ip_reset + R => \^sr\ ); \s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE generic map( @@ -3632,10 +2457,10 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(1), + CE => \s_axi_rdata_i[13]_i_1_n_0\, + D => \ip2bus_data_i_D1_reg[18]\(1), Q => s_axi_rdata(1), - R => bus2ip_reset + R => \^sr\ ); \s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE generic map( @@ -3643,21 +2468,10 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(2), + CE => \s_axi_rdata_i[13]_i_1_n_0\, + D => \ip2bus_data_i_D1_reg[18]\(2), Q => s_axi_rdata(2), - R => bus2ip_reset - ); -\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(14), - Q => s_axi_rdata(14), - R => bus2ip_reset + R => \^sr\ ); \s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE generic map( @@ -3665,10 +2479,10 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(3), + CE => \s_axi_rdata_i[13]_i_1_n_0\, + D => \ip2bus_data_i_D1_reg[18]\(3), Q => s_axi_rdata(3), - R => bus2ip_reset + R => \^sr\ ); \s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE generic map( @@ -3676,10 +2490,10 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(4), + CE => \s_axi_rdata_i[13]_i_1_n_0\, + D => \ip2bus_data_i_D1_reg[18]\(4), Q => s_axi_rdata(4), - R => bus2ip_reset + R => \^sr\ ); \s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE generic map( @@ -3687,10 +2501,10 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(5), + CE => \s_axi_rdata_i[13]_i_1_n_0\, + D => \ip2bus_data_i_D1_reg[18]\(5), Q => s_axi_rdata(5), - R => bus2ip_reset + R => \^sr\ ); \s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE generic map( @@ -3698,10 +2512,10 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(6), + CE => \s_axi_rdata_i[13]_i_1_n_0\, + D => \ip2bus_data_i_D1_reg[18]\(6), Q => s_axi_rdata(6), - R => bus2ip_reset + R => \^sr\ ); \s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE generic map( @@ -3709,10 +2523,10 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(7), + CE => \s_axi_rdata_i[13]_i_1_n_0\, + D => \ip2bus_data_i_D1_reg[18]\(7), Q => s_axi_rdata(7), - R => bus2ip_reset + R => \^sr\ ); \s_axi_rdata_i_reg[8]\: unisim.vcomponents.FDRE generic map( @@ -3720,10 +2534,10 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(8), + CE => \s_axi_rdata_i[13]_i_1_n_0\, + D => \ip2bus_data_i_D1_reg[18]\(8), Q => s_axi_rdata(8), - R => bus2ip_reset + R => \^sr\ ); \s_axi_rdata_i_reg[9]\: unisim.vcomponents.FDRE generic map( @@ -3731,10 +2545,10 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(9), + CE => \s_axi_rdata_i[13]_i_1_n_0\, + D => \ip2bus_data_i_D1_reg[18]\(9), Q => s_axi_rdata(9), - R => bus2ip_reset + R => \^sr\ ); s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5 generic map( @@ -3757,7 +2571,7 @@ s_axi_rvalid_i_reg: unisim.vcomponents.FDRE CE => '1', D => s_axi_rvalid_i_i_1_n_0, Q => \^s_axi_rvalid\, - R => bus2ip_reset + R => \^sr\ ); start2_i_1: unisim.vcomponents.LUT5 generic map( @@ -3767,8 +2581,8 @@ start2_i_1: unisim.vcomponents.LUT5 I0 => s_axi_awvalid, I1 => s_axi_wvalid, I2 => s_axi_arvalid, - I3 => state(0), - I4 => state(1), + I3 => state(1), + I4 => state(0), O => start2_i_1_n_0 ); start2_reg: unisim.vcomponents.FDRE @@ -3777,32 +2591,31 @@ start2_reg: unisim.vcomponents.FDRE CE => '1', D => start2_i_1_n_0, Q => start2, - R => bus2ip_reset + R => \^sr\ ); \state[0]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"0FFFAACC" + INIT => X"77FC44FC" ) port map ( - I0 => \^s_axi_wready\, - I1 => s_axi_arvalid, - I2 => \state[1]_i_2_n_0\, + I0 => \state1__2\, + I1 => state(0), + I2 => s_axi_arvalid, I3 => state(1), - I4 => state(0), - O => \p_0_out__0\(0) + I4 => \^s_axi_wready\, + O => p_0_out(0) ); -\state[1]_i_1\: unisim.vcomponents.LUT6 +\state[1]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"2E2E2E2ECCCCFFCC" + INIT => X"5FFC50FC" ) port map ( - I0 => \^s_axi_arready\, - I1 => state(1), - I2 => \state[1]_i_2_n_0\, - I3 => \state[1]_i_3_n_0\, - I4 => s_axi_arvalid, - I5 => state(0), - O => \p_0_out__0\(1) + I0 => \state1__2\, + I1 => \state[1]_i_3_n_0\, + I2 => state(1), + I3 => state(0), + I4 => \^s_axi_arready\, + O => p_0_out(1) ); \state[1]_i_2\: unisim.vcomponents.LUT4 generic map( @@ -3813,32 +2626,33 @@ start2_reg: unisim.vcomponents.FDRE I1 => \^s_axi_bvalid\, I2 => s_axi_rready, I3 => \^s_axi_rvalid\, - O => \state[1]_i_2_n_0\ + O => \state1__2\ ); -\state[1]_i_3\: unisim.vcomponents.LUT2 +\state[1]_i_3\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"08" ) port map ( - I0 => s_axi_awvalid, - I1 => s_axi_wvalid, + I0 => s_axi_wvalid, + I1 => s_axi_awvalid, + I2 => s_axi_arvalid, O => \state[1]_i_3_n_0\ ); \state_reg[0]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \p_0_out__0\(0), + D => p_0_out(0), Q => state(0), - R => bus2ip_reset + R => \^sr\ ); \state_reg[1]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \p_0_out__0\(1), + D => p_0_out(1), Q => state(1), - R => bus2ip_reset + R => \^sr\ ); end STRUCTURE; library IEEE; @@ -3847,70 +2661,49 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20_axi_gpio_shield_1_0_axi_lite_ipif is port ( - p_8_in : out STD_LOGIC; + bus2ip_reset : out STD_LOGIC; bus2ip_rnw : out STD_LOGIC; - bus2ip_cs : out STD_LOGIC_VECTOR ( 0 to 0 ); - Bus_RNW_reg : out STD_LOGIC; + bus2ip_cs : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_bvalid : out STD_LOGIC; s_axi_arready : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wready : out STD_LOGIC; - D : out STD_LOGIC_VECTOR ( 13 downto 0 ); - \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[31]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[24]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[23]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[22]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[21]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[20]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[19]\ : out STD_LOGIC; GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 ); - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - \Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - \ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); - intr2bus_rdack0 : out STD_LOGIC; - irpt_rdack : out STD_LOGIC; - irpt_wrack : out STD_LOGIC; - interrupt_wrce_strb : out STD_LOGIC; - Read_Reg_Rst : out STD_LOGIC; - \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ : out STD_LOGIC; - intr_rd_ce_or_reduce : out STD_LOGIC; - \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC; - intr_wr_ce_or_reduce : out STD_LOGIC; - \ip_irpt_enable_reg_reg[0]\ : out STD_LOGIC; - ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC; - s_axi_rdata : out STD_LOGIC_VECTOR ( 14 downto 0 ); - bus2ip_reset : in STD_LOGIC; + \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[19]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[20]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[21]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[22]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[23]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[24]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[31]\ : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 13 downto 0 ); + \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[18]\ : out STD_LOGIC; + s_axi_rdata : out STD_LOGIC_VECTOR ( 13 downto 0 ); s_axi_aclk : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; + s_axi_awvalid : in STD_LOGIC; + s_axi_wvalid : in STD_LOGIC; + s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_aresetn : in STD_LOGIC; + s_axi_rready : in STD_LOGIC; + s_axi_bready : in STD_LOGIC; ip2bus_rdack_i_D1 : in STD_LOGIC; ip2bus_wrack_i_D1 : in STD_LOGIC; - s_axi_bready : in STD_LOGIC; - s_axi_rready : in STD_LOGIC; - s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 ); - s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 ); - s_axi_awvalid : in STD_LOGIC; - s_axi_wvalid : in STD_LOGIC; - s_axi_wdata : in STD_LOGIC_VECTOR ( 27 downto 0 ); - gpio_io_t : in STD_LOGIC_VECTOR ( 13 downto 0 ); Q : in STD_LOGIC_VECTOR ( 13 downto 0 ); - p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); - irpt_rdack_d1 : in STD_LOGIC; - irpt_wrack_d1 : in STD_LOGIC; - ip2bus_data : in STD_LOGIC_VECTOR ( 0 to 0 ); - p_3_in : in STD_LOGIC_VECTOR ( 0 to 0 ); - p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 ); - GPIO_xferAck_i : in STD_LOGIC; + gpio_io_t : in STD_LOGIC_VECTOR ( 13 downto 0 ); + s_axi_wdata : in STD_LOGIC_VECTOR ( 27 downto 0 ); gpio_xferAck_Reg : in STD_LOGIC; - ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC; - ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC; - \ip2bus_data_i_D1_reg[0]_0\ : in STD_LOGIC_VECTOR ( 14 downto 0 ) + GPIO_xferAck_i : in STD_LOGIC; + \ip2bus_data_i_D1_reg[18]\ : in STD_LOGIC_VECTOR ( 13 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of Arty_Z7_20_axi_gpio_shield_1_0_axi_lite_ipif : entity is "axi_lite_ipif"; @@ -3924,8 +2717,8 @@ I_SLAVE_ATTACHMENT: entity work.Arty_Z7_20_axi_gpio_shield_1_0_slave_attachment E(0) => E(0), GPIO_DBus_i(0) => GPIO_DBus_i(0), GPIO_xferAck_i => GPIO_xferAck_i, - \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\, - \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\, + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\ => bus2ip_cs, + \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[18]\ => \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[18]\, \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28]\ => \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28]\, \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29]\ => \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29]\, \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30]\ => \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30]\, @@ -3939,46 +2732,25 @@ I_SLAVE_ATTACHMENT: entity work.Arty_Z7_20_axi_gpio_shield_1_0_slave_attachment \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25]\ => \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25]\, \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26]\ => \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26]\, \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27]\ => \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27]\, - \Not_Dual.gpio_Data_Out_reg[0]\(0) => \Not_Dual.gpio_Data_Out_reg[0]\(0), - \Not_Dual.gpio_Data_Out_reg[13]\ => bus2ip_cs(0), - \Not_Dual.gpio_OE_reg[0]\ => bus2ip_rnw, + \Not_Dual.gpio_Data_Out_reg[0]\ => bus2ip_rnw, + \Not_Dual.gpio_OE_reg[0]\(0) => \Not_Dual.gpio_OE_reg[0]\(0), Q(13 downto 0) => Q(13 downto 0), - Read_Reg_Rst => Read_Reg_Rst, - bus2ip_reset => bus2ip_reset, + SR => bus2ip_reset, gpio_io_t(13 downto 0) => gpio_io_t(13 downto 0), gpio_xferAck_Reg => gpio_xferAck_Reg, - interrupt_wrce_strb => interrupt_wrce_strb, - intr2bus_rdack0 => intr2bus_rdack0, - intr_rd_ce_or_reduce => intr_rd_ce_or_reduce, - intr_wr_ce_or_reduce => intr_wr_ce_or_reduce, - ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1, - ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1, - ip2bus_data(0) => ip2bus_data(0), - \ip2bus_data_i_D1_reg[0]\ => p_8_in, - \ip2bus_data_i_D1_reg[0]_0\(1 downto 0) => \ip2bus_data_i_D1_reg[0]\(1 downto 0), - \ip2bus_data_i_D1_reg[0]_1\(14 downto 0) => \ip2bus_data_i_D1_reg[0]_0\(14 downto 0), + \ip2bus_data_i_D1_reg[18]\(13 downto 0) => \ip2bus_data_i_D1_reg[18]\(13 downto 0), ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1, ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1, - \ip_irpt_enable_reg_reg[0]\ => Bus_RNW_reg, - \ip_irpt_enable_reg_reg[0]_0\ => \ip_irpt_enable_reg_reg[0]\, - ipif_glbl_irpt_enable_reg_reg => ipif_glbl_irpt_enable_reg_reg, - irpt_rdack => irpt_rdack, - irpt_rdack_d1 => irpt_rdack_d1, - irpt_wrack => irpt_wrack, - irpt_wrack_d1 => irpt_wrack_d1, - p_0_in(0) => p_0_in(0), - p_1_in(0) => p_1_in(0), - p_3_in(0) => p_3_in(0), s_axi_aclk => s_axi_aclk, - s_axi_araddr(6 downto 0) => s_axi_araddr(6 downto 0), + s_axi_araddr(2 downto 0) => s_axi_araddr(2 downto 0), s_axi_aresetn => s_axi_aresetn, s_axi_arready => s_axi_arready, s_axi_arvalid => s_axi_arvalid, - s_axi_awaddr(6 downto 0) => s_axi_awaddr(6 downto 0), + s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0), s_axi_awvalid => s_axi_awvalid, s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, - s_axi_rdata(14 downto 0) => s_axi_rdata(14 downto 0), + s_axi_rdata(13 downto 0) => s_axi_rdata(13 downto 0), s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid, s_axi_wdata(27 downto 0) => s_axi_wdata(27 downto 0), @@ -4038,7 +2810,7 @@ entity Arty_Z7_20_axi_gpio_shield_1_0_axi_gpio is attribute C_GPIO_WIDTH : integer; attribute C_GPIO_WIDTH of Arty_Z7_20_axi_gpio_shield_1_0_axi_gpio : entity is 14; attribute C_INTERRUPT_PRESENT : integer; - attribute C_INTERRUPT_PRESENT of Arty_Z7_20_axi_gpio_shield_1_0_axi_gpio : entity is 1; + attribute C_INTERRUPT_PRESENT of Arty_Z7_20_axi_gpio_shield_1_0_axi_gpio : entity is 0; attribute C_IS_DUAL : integer; attribute C_IS_DUAL of Arty_Z7_20_axi_gpio_shield_1_0_axi_gpio : entity is 0; attribute C_S_AXI_ADDR_WIDTH : integer; @@ -4060,67 +2832,39 @@ end Arty_Z7_20_axi_gpio_shield_1_0_axi_gpio; architecture STRUCTURE of Arty_Z7_20_axi_gpio_shield_1_0_axi_gpio is signal \\ : STD_LOGIC; signal \\ : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_10 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_11 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_12 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_13 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_14 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_15 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_16 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_17 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_18 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_19 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_20 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_21 : STD_LOGIC; signal AXI_LITE_IPIF_I_n_22 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_23 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_24 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_25 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_26 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_27 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_28 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_29 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_30 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_31 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_32 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_33 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_34 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_36 : STD_LOGIC; signal AXI_LITE_IPIF_I_n_37 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_45 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_47 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_49 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_50 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_6 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_7 : STD_LOGIC; signal DBus_Reg : STD_LOGIC_VECTOR ( 0 to 13 ); signal GPIO_DBus_i : STD_LOGIC_VECTOR ( 18 to 18 ); - signal GPIO_intr : STD_LOGIC; signal GPIO_xferAck_i : STD_LOGIC; - signal IP2INTC_Irpt_i : STD_LOGIC; - signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC; - signal \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in\ : STD_LOGIC; - signal Read_Reg_Rst : STD_LOGIC; - signal bus2ip_cs : STD_LOGIC_VECTOR ( 1 to 1 ); + signal bus2ip_cs : STD_LOGIC; signal bus2ip_reset : STD_LOGIC; - signal bus2ip_reset_i_1_n_0 : STD_LOGIC; signal bus2ip_rnw : STD_LOGIC; signal gpio_Data_In : STD_LOGIC_VECTOR ( 0 to 13 ); + signal gpio_core_1_n_17 : STD_LOGIC; signal \^gpio_io_t\ : STD_LOGIC_VECTOR ( 13 downto 0 ); signal gpio_xferAck_Reg : STD_LOGIC; - signal interrupt_wrce_strb : STD_LOGIC; - signal intr2bus_rdack0 : STD_LOGIC; - signal intr_rd_ce_or_reduce : STD_LOGIC; - signal intr_wr_ce_or_reduce : STD_LOGIC; - signal ip2Bus_RdAck_intr_reg_hole : STD_LOGIC; - signal ip2Bus_RdAck_intr_reg_hole_d1 : STD_LOGIC; - signal ip2Bus_WrAck_intr_reg_hole : STD_LOGIC; - signal ip2Bus_WrAck_intr_reg_hole_d1 : STD_LOGIC; signal ip2bus_data : STD_LOGIC_VECTOR ( 18 to 31 ); - signal ip2bus_data_i : STD_LOGIC_VECTOR ( 31 to 31 ); - signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 0 to 31 ); + signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 18 to 31 ); signal ip2bus_rdack_i : STD_LOGIC; signal ip2bus_rdack_i_D1 : STD_LOGIC; - signal ip2bus_wrack_i : STD_LOGIC; signal ip2bus_wrack_i_D1 : STD_LOGIC; - signal irpt_rdack : STD_LOGIC; - signal irpt_rdack_d1 : STD_LOGIC; - signal irpt_wrack : STD_LOGIC; - signal irpt_wrack_d1 : STD_LOGIC; - signal p_0_in : STD_LOGIC_VECTOR ( 31 to 31 ); - signal p_0_out : STD_LOGIC_VECTOR ( 0 to 0 ); - signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 ); - signal p_3_in : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 13 downto 0 ); signal \^s_axi_wready\ : STD_LOGIC; - attribute sigis : string; - attribute sigis of \INTR_CTRLR_GEN.ip2intc_irpt_reg\ : label is "INTR_LEVEL_HIGH"; begin gpio2_io_o(31) <= \\; gpio2_io_o(30) <= \\; @@ -4187,10 +2931,11 @@ begin gpio2_io_t(1) <= \\; gpio2_io_t(0) <= \\; gpio_io_t(13 downto 0) <= \^gpio_io_t\(13 downto 0); + ip2intc_irpt <= \\; s_axi_awready <= \^s_axi_wready\; s_axi_bresp(1) <= \\; s_axi_bresp(0) <= \\; - s_axi_rdata(31) <= \^s_axi_rdata\(31); + s_axi_rdata(31) <= \\; s_axi_rdata(30) <= \\; s_axi_rdata(29) <= \\; s_axi_rdata(28) <= \\; @@ -4214,7 +2959,6 @@ begin s_axi_wready <= \^s_axi_wready\; AXI_LITE_IPIF_I: entity work.Arty_Z7_20_axi_gpio_shield_1_0_axi_lite_ipif port map ( - Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\, D(13) => DBus_Reg(0), D(12) => DBus_Reg(1), D(11) => DBus_Reg(2), @@ -4229,25 +2973,24 @@ AXI_LITE_IPIF_I: entity work.Arty_Z7_20_axi_gpio_shield_1_0_axi_lite_ipif D(2) => DBus_Reg(11), D(1) => DBus_Reg(12), D(0) => DBus_Reg(13), - E(0) => AXI_LITE_IPIF_I_n_36, + E(0) => AXI_LITE_IPIF_I_n_6, GPIO_DBus_i(0) => GPIO_DBus_i(18), GPIO_xferAck_i => GPIO_xferAck_i, - \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ => AXI_LITE_IPIF_I_n_45, - \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => AXI_LITE_IPIF_I_n_47, - \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28]\ => AXI_LITE_IPIF_I_n_25, - \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29]\ => AXI_LITE_IPIF_I_n_24, - \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30]\ => AXI_LITE_IPIF_I_n_23, + \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[18]\ => AXI_LITE_IPIF_I_n_37, + \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[28]\ => AXI_LITE_IPIF_I_n_19, + \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[29]\ => AXI_LITE_IPIF_I_n_20, + \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[30]\ => AXI_LITE_IPIF_I_n_21, \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[31]\ => AXI_LITE_IPIF_I_n_22, - \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[19]\ => AXI_LITE_IPIF_I_n_34, - \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[20]\ => AXI_LITE_IPIF_I_n_33, - \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[21]\ => AXI_LITE_IPIF_I_n_32, - \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[22]\ => AXI_LITE_IPIF_I_n_31, - \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[23]\ => AXI_LITE_IPIF_I_n_30, - \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[24]\ => AXI_LITE_IPIF_I_n_29, - \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25]\ => AXI_LITE_IPIF_I_n_28, - \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26]\ => AXI_LITE_IPIF_I_n_27, - \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27]\ => AXI_LITE_IPIF_I_n_26, - \Not_Dual.gpio_Data_Out_reg[0]\(0) => AXI_LITE_IPIF_I_n_37, + \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[19]\ => AXI_LITE_IPIF_I_n_10, + \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[20]\ => AXI_LITE_IPIF_I_n_11, + \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[21]\ => AXI_LITE_IPIF_I_n_12, + \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[22]\ => AXI_LITE_IPIF_I_n_13, + \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[23]\ => AXI_LITE_IPIF_I_n_14, + \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[24]\ => AXI_LITE_IPIF_I_n_15, + \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[25]\ => AXI_LITE_IPIF_I_n_16, + \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[26]\ => AXI_LITE_IPIF_I_n_17, + \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[27]\ => AXI_LITE_IPIF_I_n_18, + \Not_Dual.gpio_OE_reg[0]\(0) => AXI_LITE_IPIF_I_n_7, Q(13) => gpio_Data_In(0), Q(12) => gpio_Data_In(1), Q(11) => gpio_Data_In(2), @@ -4262,58 +3005,38 @@ AXI_LITE_IPIF_I: entity work.Arty_Z7_20_axi_gpio_shield_1_0_axi_lite_ipif Q(2) => gpio_Data_In(11), Q(1) => gpio_Data_In(12), Q(0) => gpio_Data_In(13), - Read_Reg_Rst => Read_Reg_Rst, - bus2ip_cs(0) => bus2ip_cs(1), + bus2ip_cs => bus2ip_cs, bus2ip_reset => bus2ip_reset, bus2ip_rnw => bus2ip_rnw, gpio_io_t(13 downto 0) => \^gpio_io_t\(13 downto 0), gpio_xferAck_Reg => gpio_xferAck_Reg, - interrupt_wrce_strb => interrupt_wrce_strb, - intr2bus_rdack0 => intr2bus_rdack0, - intr_rd_ce_or_reduce => intr_rd_ce_or_reduce, - intr_wr_ce_or_reduce => intr_wr_ce_or_reduce, - ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1, - ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1, - ip2bus_data(0) => ip2bus_data(31), - \ip2bus_data_i_D1_reg[0]\(1) => p_0_out(0), - \ip2bus_data_i_D1_reg[0]\(0) => ip2bus_data_i(31), - \ip2bus_data_i_D1_reg[0]_0\(14) => ip2bus_data_i_D1(0), - \ip2bus_data_i_D1_reg[0]_0\(13) => ip2bus_data_i_D1(18), - \ip2bus_data_i_D1_reg[0]_0\(12) => ip2bus_data_i_D1(19), - \ip2bus_data_i_D1_reg[0]_0\(11) => ip2bus_data_i_D1(20), - \ip2bus_data_i_D1_reg[0]_0\(10) => ip2bus_data_i_D1(21), - \ip2bus_data_i_D1_reg[0]_0\(9) => ip2bus_data_i_D1(22), - \ip2bus_data_i_D1_reg[0]_0\(8) => ip2bus_data_i_D1(23), - \ip2bus_data_i_D1_reg[0]_0\(7) => ip2bus_data_i_D1(24), - \ip2bus_data_i_D1_reg[0]_0\(6) => ip2bus_data_i_D1(25), - \ip2bus_data_i_D1_reg[0]_0\(5) => ip2bus_data_i_D1(26), - \ip2bus_data_i_D1_reg[0]_0\(4) => ip2bus_data_i_D1(27), - \ip2bus_data_i_D1_reg[0]_0\(3) => ip2bus_data_i_D1(28), - \ip2bus_data_i_D1_reg[0]_0\(2) => ip2bus_data_i_D1(29), - \ip2bus_data_i_D1_reg[0]_0\(1) => ip2bus_data_i_D1(30), - \ip2bus_data_i_D1_reg[0]_0\(0) => ip2bus_data_i_D1(31), + \ip2bus_data_i_D1_reg[18]\(13) => ip2bus_data_i_D1(18), + \ip2bus_data_i_D1_reg[18]\(12) => ip2bus_data_i_D1(19), + \ip2bus_data_i_D1_reg[18]\(11) => ip2bus_data_i_D1(20), + \ip2bus_data_i_D1_reg[18]\(10) => ip2bus_data_i_D1(21), + \ip2bus_data_i_D1_reg[18]\(9) => ip2bus_data_i_D1(22), + \ip2bus_data_i_D1_reg[18]\(8) => ip2bus_data_i_D1(23), + \ip2bus_data_i_D1_reg[18]\(7) => ip2bus_data_i_D1(24), + \ip2bus_data_i_D1_reg[18]\(6) => ip2bus_data_i_D1(25), + \ip2bus_data_i_D1_reg[18]\(5) => ip2bus_data_i_D1(26), + \ip2bus_data_i_D1_reg[18]\(4) => ip2bus_data_i_D1(27), + \ip2bus_data_i_D1_reg[18]\(3) => ip2bus_data_i_D1(28), + \ip2bus_data_i_D1_reg[18]\(2) => ip2bus_data_i_D1(29), + \ip2bus_data_i_D1_reg[18]\(1) => ip2bus_data_i_D1(30), + \ip2bus_data_i_D1_reg[18]\(0) => ip2bus_data_i_D1(31), ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1, ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1, - \ip_irpt_enable_reg_reg[0]\ => AXI_LITE_IPIF_I_n_49, - ipif_glbl_irpt_enable_reg_reg => AXI_LITE_IPIF_I_n_50, - irpt_rdack => irpt_rdack, - irpt_rdack_d1 => irpt_rdack_d1, - irpt_wrack => irpt_wrack, - irpt_wrack_d1 => irpt_wrack_d1, - p_0_in(0) => p_0_in(31), - p_1_in(0) => p_1_in(0), - p_3_in(0) => p_3_in(0), - p_8_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in\, s_axi_aclk => s_axi_aclk, - s_axi_araddr(6 downto 0) => s_axi_araddr(8 downto 2), + s_axi_araddr(2) => s_axi_araddr(8), + s_axi_araddr(1 downto 0) => s_axi_araddr(3 downto 2), s_axi_aresetn => s_axi_aresetn, s_axi_arready => s_axi_arready, s_axi_arvalid => s_axi_arvalid, - s_axi_awaddr(6 downto 0) => s_axi_awaddr(8 downto 2), + s_axi_awaddr(2) => s_axi_awaddr(8), + s_axi_awaddr(1 downto 0) => s_axi_awaddr(3 downto 2), s_axi_awvalid => s_axi_awvalid, s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, - s_axi_rdata(14) => \^s_axi_rdata\(31), s_axi_rdata(13 downto 0) => \^s_axi_rdata\(13 downto 0), s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid, @@ -4326,126 +3049,56 @@ GND: unisim.vcomponents.GND port map ( G => \\ ); -\INTR_CTRLR_GEN.INTERRUPT_CONTROL_I\: entity work.Arty_Z7_20_axi_gpio_shield_1_0_interrupt_control - port map ( - Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\, - \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\ => AXI_LITE_IPIF_I_n_50, - \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\ => AXI_LITE_IPIF_I_n_49, - GPIO_intr => GPIO_intr, - GPIO_xferAck_i => GPIO_xferAck_i, - IP2INTC_Irpt_i => IP2INTC_Irpt_i, - bus2ip_reset => bus2ip_reset, - bus2ip_rnw => bus2ip_rnw, - interrupt_wrce_strb => interrupt_wrce_strb, - intr2bus_rdack0 => intr2bus_rdack0, - ip2Bus_RdAck_intr_reg_hole => ip2Bus_RdAck_intr_reg_hole, - ip2Bus_WrAck_intr_reg_hole => ip2Bus_WrAck_intr_reg_hole, - ip2bus_rdack_i => ip2bus_rdack_i, - ip2bus_wrack_i => ip2bus_wrack_i, - irpt_rdack => irpt_rdack, - irpt_rdack_d1 => irpt_rdack_d1, - irpt_wrack => irpt_wrack, - irpt_wrack_d1 => irpt_wrack_d1, - p_0_in(0) => p_0_in(31), - p_1_in(0) => p_1_in(0), - p_3_in(0) => p_3_in(0), - p_8_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in\, - s_axi_aclk => s_axi_aclk, - s_axi_wdata(0) => s_axi_wdata(0) - ); -\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_reg\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => intr_rd_ce_or_reduce, - Q => ip2Bus_RdAck_intr_reg_hole_d1, - R => bus2ip_reset - ); -\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => AXI_LITE_IPIF_I_n_45, - Q => ip2Bus_RdAck_intr_reg_hole, - R => bus2ip_reset - ); -\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_reg\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => intr_wr_ce_or_reduce, - Q => ip2Bus_WrAck_intr_reg_hole_d1, - R => bus2ip_reset - ); -\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => AXI_LITE_IPIF_I_n_47, - Q => ip2Bus_WrAck_intr_reg_hole, - R => bus2ip_reset - ); -\INTR_CTRLR_GEN.ip2intc_irpt_reg\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => IP2INTC_Irpt_i, - Q => ip2intc_irpt, - R => bus2ip_reset - ); VCC: unisim.vcomponents.VCC port map ( P => \\ ); -bus2ip_reset_i_1: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => s_axi_aresetn, - O => bus2ip_reset_i_1_n_0 - ); -bus2ip_reset_reg: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => bus2ip_reset_i_1_n_0, - Q => bus2ip_reset, - R => '0' - ); gpio_core_1: entity work.Arty_Z7_20_axi_gpio_shield_1_0_GPIO_Core port map ( - D(13) => DBus_Reg(0), - D(12) => DBus_Reg(1), - D(11) => DBus_Reg(2), - D(10) => DBus_Reg(3), - D(9) => DBus_Reg(4), - D(8) => DBus_Reg(5), - D(7) => DBus_Reg(6), - D(6) => DBus_Reg(7), - D(5) => DBus_Reg(8), - D(4) => DBus_Reg(9), - D(3) => DBus_Reg(10), - D(2) => DBus_Reg(11), - D(1) => DBus_Reg(12), - D(0) => DBus_Reg(13), - E(0) => AXI_LITE_IPIF_I_n_37, + D(13) => ip2bus_data(18), + D(12) => ip2bus_data(19), + D(11) => ip2bus_data(20), + D(10) => ip2bus_data(21), + D(9) => ip2bus_data(22), + D(8) => ip2bus_data(23), + D(7) => ip2bus_data(24), + D(6) => ip2bus_data(25), + D(5) => ip2bus_data(26), + D(4) => ip2bus_data(27), + D(3) => ip2bus_data(28), + D(2) => ip2bus_data(29), + D(1) => ip2bus_data(30), + D(0) => ip2bus_data(31), + E(0) => AXI_LITE_IPIF_I_n_6, GPIO_DBus_i(0) => GPIO_DBus_i(18), - GPIO_intr => GPIO_intr, GPIO_xferAck_i => GPIO_xferAck_i, - \Not_Dual.gpio_OE_reg[10]_0\ => AXI_LITE_IPIF_I_n_25, - \Not_Dual.gpio_OE_reg[11]_0\ => AXI_LITE_IPIF_I_n_24, - \Not_Dual.gpio_OE_reg[12]_0\ => AXI_LITE_IPIF_I_n_23, - \Not_Dual.gpio_OE_reg[13]_0\ => AXI_LITE_IPIF_I_n_22, - \Not_Dual.gpio_OE_reg[1]_0\ => AXI_LITE_IPIF_I_n_34, - \Not_Dual.gpio_OE_reg[2]_0\ => AXI_LITE_IPIF_I_n_33, - \Not_Dual.gpio_OE_reg[3]_0\ => AXI_LITE_IPIF_I_n_32, - \Not_Dual.gpio_OE_reg[4]_0\ => AXI_LITE_IPIF_I_n_31, - \Not_Dual.gpio_OE_reg[5]_0\ => AXI_LITE_IPIF_I_n_30, - \Not_Dual.gpio_OE_reg[6]_0\ => AXI_LITE_IPIF_I_n_29, - \Not_Dual.gpio_OE_reg[7]_0\ => AXI_LITE_IPIF_I_n_28, - \Not_Dual.gpio_OE_reg[8]_0\ => AXI_LITE_IPIF_I_n_27, - \Not_Dual.gpio_OE_reg[9]_0\ => AXI_LITE_IPIF_I_n_26, + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(13) => DBus_Reg(0), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(12) => DBus_Reg(1), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(11) => DBus_Reg(2), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(10) => DBus_Reg(3), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(9) => DBus_Reg(4), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(8) => DBus_Reg(5), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(7) => DBus_Reg(6), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(6) => DBus_Reg(7), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(5) => DBus_Reg(8), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(4) => DBus_Reg(9), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(3) => DBus_Reg(10), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(2) => DBus_Reg(11), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(1) => DBus_Reg(12), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(0) => DBus_Reg(13), + \Not_Dual.gpio_Data_In_reg[10]_0\ => AXI_LITE_IPIF_I_n_19, + \Not_Dual.gpio_Data_In_reg[11]_0\ => AXI_LITE_IPIF_I_n_20, + \Not_Dual.gpio_Data_In_reg[12]_0\ => AXI_LITE_IPIF_I_n_21, + \Not_Dual.gpio_Data_In_reg[13]_0\ => AXI_LITE_IPIF_I_n_22, + \Not_Dual.gpio_Data_In_reg[1]_0\ => AXI_LITE_IPIF_I_n_10, + \Not_Dual.gpio_Data_In_reg[2]_0\ => AXI_LITE_IPIF_I_n_11, + \Not_Dual.gpio_Data_In_reg[3]_0\ => AXI_LITE_IPIF_I_n_12, + \Not_Dual.gpio_Data_In_reg[4]_0\ => AXI_LITE_IPIF_I_n_13, + \Not_Dual.gpio_Data_In_reg[5]_0\ => AXI_LITE_IPIF_I_n_14, + \Not_Dual.gpio_Data_In_reg[6]_0\ => AXI_LITE_IPIF_I_n_15, + \Not_Dual.gpio_Data_In_reg[7]_0\ => AXI_LITE_IPIF_I_n_16, + \Not_Dual.gpio_Data_In_reg[8]_0\ => AXI_LITE_IPIF_I_n_17, + \Not_Dual.gpio_Data_In_reg[9]_0\ => AXI_LITE_IPIF_I_n_18, Q(13) => gpio_Data_In(0), Q(12) => gpio_Data_In(1), Q(11) => gpio_Data_In(2), @@ -4460,38 +3113,19 @@ gpio_core_1: entity work.Arty_Z7_20_axi_gpio_shield_1_0_GPIO_Core Q(2) => gpio_Data_In(11), Q(1) => gpio_Data_In(12), Q(0) => gpio_Data_In(13), - Read_Reg_Rst => Read_Reg_Rst, - bus2ip_cs(0) => bus2ip_cs(1), - bus2ip_reset => bus2ip_reset, - bus2ip_rnw_i_reg(0) => AXI_LITE_IPIF_I_n_36, + SS(0) => bus2ip_reset, + bus2ip_cs => bus2ip_cs, + bus2ip_rnw => bus2ip_rnw, + bus2ip_rnw_i_reg => AXI_LITE_IPIF_I_n_37, gpio_io_i(13 downto 0) => gpio_io_i(13 downto 0), gpio_io_o(13 downto 0) => gpio_io_o(13 downto 0), gpio_io_t(13 downto 0) => \^gpio_io_t\(13 downto 0), gpio_xferAck_Reg => gpio_xferAck_Reg, - ip2bus_data(13) => ip2bus_data(18), - ip2bus_data(12) => ip2bus_data(19), - ip2bus_data(11) => ip2bus_data(20), - ip2bus_data(10) => ip2bus_data(21), - ip2bus_data(9) => ip2bus_data(22), - ip2bus_data(8) => ip2bus_data(23), - ip2bus_data(7) => ip2bus_data(24), - ip2bus_data(6) => ip2bus_data(25), - ip2bus_data(5) => ip2bus_data(26), - ip2bus_data(4) => ip2bus_data(27), - ip2bus_data(3) => ip2bus_data(28), - ip2bus_data(2) => ip2bus_data(29), - ip2bus_data(1) => ip2bus_data(30), - ip2bus_data(0) => ip2bus_data(31), + ip2bus_rdack_i => ip2bus_rdack_i, + ip2bus_wrack_i_D1_reg => gpio_core_1_n_17, + rst_reg(0) => AXI_LITE_IPIF_I_n_7, s_axi_aclk => s_axi_aclk ); -\ip2bus_data_i_D1_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => p_0_out(0), - Q => ip2bus_data_i_D1(0), - R => bus2ip_reset - ); \ip2bus_data_i_D1_reg[18]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, @@ -4600,7 +3234,7 @@ gpio_core_1: entity work.Arty_Z7_20_axi_gpio_shield_1_0_GPIO_Core port map ( C => s_axi_aclk, CE => '1', - D => ip2bus_data_i(31), + D => ip2bus_data(31), Q => ip2bus_data_i_D1(31), R => bus2ip_reset ); @@ -4616,7 +3250,7 @@ ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => ip2bus_wrack_i, + D => gpio_core_1_n_17, Q => ip2bus_wrack_i_D1, R => bus2ip_reset ); @@ -4646,7 +3280,6 @@ entity Arty_Z7_20_axi_gpio_shield_1_0 is s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; - ip2intc_irpt : out STD_LOGIC; gpio_io_i : in STD_LOGIC_VECTOR ( 13 downto 0 ); gpio_io_o : out STD_LOGIC_VECTOR ( 13 downto 0 ); gpio_io_t : out STD_LOGIC_VECTOR ( 13 downto 0 ) @@ -4662,6 +3295,7 @@ entity Arty_Z7_20_axi_gpio_shield_1_0 is end Arty_Z7_20_axi_gpio_shield_1_0; architecture STRUCTURE of Arty_Z7_20_axi_gpio_shield_1_0 is + signal NLW_U0_ip2intc_irpt_UNCONNECTED : STD_LOGIC; signal NLW_U0_gpio2_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_U0_gpio2_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute C_ALL_INPUTS : integer; @@ -4683,7 +3317,7 @@ architecture STRUCTURE of Arty_Z7_20_axi_gpio_shield_1_0 is attribute C_GPIO_WIDTH : integer; attribute C_GPIO_WIDTH of U0 : label is 14; attribute C_INTERRUPT_PRESENT : integer; - attribute C_INTERRUPT_PRESENT of U0 : label is 1; + attribute C_INTERRUPT_PRESENT of U0 : label is 0; attribute C_IS_DUAL : integer; attribute C_IS_DUAL of U0 : label is 0; attribute C_S_AXI_ADDR_WIDTH : integer; @@ -4706,7 +3340,7 @@ U0: entity work.Arty_Z7_20_axi_gpio_shield_1_0_axi_gpio gpio_io_i(13 downto 0) => gpio_io_i(13 downto 0), gpio_io_o(13 downto 0) => gpio_io_o(13 downto 0), gpio_io_t(13 downto 0) => gpio_io_t(13 downto 0), - ip2intc_irpt => ip2intc_irpt, + ip2intc_irpt => NLW_U0_ip2intc_irpt_UNCONNECTED, s_axi_aclk => s_axi_aclk, s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0), s_axi_aresetn => s_axi_aresetn, diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0_stub.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0_stub.v index 4e406f4..a9ea8a5 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0_stub.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -// Date : Fri Feb 24 15:59:43 2017 +// Date : Sat Mar 04 18:53:03 2017 // Host : WK73 running 64-bit Service Pack 1 (build 7601) // Command : write_verilog -force -mode synth_stub -// c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0_stub.v +// C:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0_stub.v // Design : Arty_Z7_20_axi_gpio_shield_1_0 // Purpose : Stub declaration of top-level module interface // Device : xc7z020clg400-1 @@ -17,9 +17,8 @@ module Arty_Z7_20_axi_gpio_shield_1_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready, - s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, ip2intc_irpt, gpio_io_i, gpio_io_o, - gpio_io_t) -/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,ip2intc_irpt,gpio_io_i[13:0],gpio_io_o[13:0],gpio_io_t[13:0]" */; + s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_i, gpio_io_o, gpio_io_t) +/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[13:0],gpio_io_o[13:0],gpio_io_t[13:0]" */; input s_axi_aclk; input s_axi_aresetn; input [8:0]s_axi_awaddr; @@ -39,7 +38,6 @@ module Arty_Z7_20_axi_gpio_shield_1_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr, output [1:0]s_axi_rresp; output s_axi_rvalid; input s_axi_rready; - output ip2intc_irpt; input [13:0]gpio_io_i; output [13:0]gpio_io_o; output [13:0]gpio_io_t; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0_stub.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0_stub.vhdl index 3d78dbc..0b11961 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0_stub.vhdl +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 --- Date : Fri Feb 24 15:59:43 2017 +-- Date : Sat Mar 04 18:53:03 2017 -- Host : WK73 running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode synth_stub --- c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0_stub.vhdl +-- C:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/Arty_Z7_20_axi_gpio_shield_1_0_stub.vhdl -- Design : Arty_Z7_20_axi_gpio_shield_1_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7z020clg400-1 @@ -33,7 +33,6 @@ entity Arty_Z7_20_axi_gpio_shield_1_0 is s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; - ip2intc_irpt : out STD_LOGIC; gpio_io_i : in STD_LOGIC_VECTOR ( 13 downto 0 ); gpio_io_o : out STD_LOGIC_VECTOR ( 13 downto 0 ); gpio_io_t : out STD_LOGIC_VECTOR ( 13 downto 0 ) @@ -45,7 +44,7 @@ architecture stub of Arty_Z7_20_axi_gpio_shield_1_0 is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,ip2intc_irpt,gpio_io_i[13:0],gpio_io_o[13:0],gpio_io_t[13:0]"; +attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[13:0],gpio_io_o[13:0],gpio_io_t[13:0]"; attribute x_core_info : string; attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2016.4"; begin diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/sim/Arty_Z7_20_axi_gpio_shield_1_0.vhd b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/sim/Arty_Z7_20_axi_gpio_shield_1_0.vhd index f757aea..b54e8ea 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/sim/Arty_Z7_20_axi_gpio_shield_1_0.vhd +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/sim/Arty_Z7_20_axi_gpio_shield_1_0.vhd @@ -77,7 +77,6 @@ ENTITY Arty_Z7_20_axi_gpio_shield_1_0 IS s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; - ip2intc_irpt : OUT STD_LOGIC; gpio_io_i : IN STD_LOGIC_VECTOR(13 DOWNTO 0); gpio_io_o : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); gpio_io_t : OUT STD_LOGIC_VECTOR(13 DOWNTO 0) @@ -154,7 +153,6 @@ ARCHITECTURE Arty_Z7_20_axi_gpio_shield_1_0_arch OF Arty_Z7_20_axi_gpio_shield_1 ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; - ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT"; ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I"; ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O"; ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T"; @@ -170,7 +168,7 @@ BEGIN C_ALL_INPUTS_2 => 0, C_ALL_OUTPUTS => 0, C_ALL_OUTPUTS_2 => 0, - C_INTERRUPT_PRESENT => 1, + C_INTERRUPT_PRESENT => 0, C_DOUT_DEFAULT => X"00000000", C_TRI_DEFAULT => X"FFFFFFFF", C_IS_DUAL => 0, @@ -197,7 +195,6 @@ BEGIN s_axi_rresp => s_axi_rresp, s_axi_rvalid => s_axi_rvalid, s_axi_rready => s_axi_rready, - ip2intc_irpt => ip2intc_irpt, gpio_io_i => gpio_io_i, gpio_io_o => gpio_io_o, gpio_io_t => gpio_io_t, diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/synth/Arty_Z7_20_axi_gpio_shield_1_0.vhd b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/synth/Arty_Z7_20_axi_gpio_shield_1_0.vhd index b63a5e4..f67d481 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/synth/Arty_Z7_20_axi_gpio_shield_1_0.vhd +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_1_0/synth/Arty_Z7_20_axi_gpio_shield_1_0.vhd @@ -77,7 +77,6 @@ ENTITY Arty_Z7_20_axi_gpio_shield_1_0 IS s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; - ip2intc_irpt : OUT STD_LOGIC; gpio_io_i : IN STD_LOGIC_VECTOR(13 DOWNTO 0); gpio_io_o : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); gpio_io_t : OUT STD_LOGIC_VECTOR(13 DOWNTO 0) @@ -139,7 +138,7 @@ ARCHITECTURE Arty_Z7_20_axi_gpio_shield_1_0_arch OF Arty_Z7_20_axi_gpio_shield_1 ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF Arty_Z7_20_axi_gpio_shield_1_0_arch : ARCHITECTURE IS "Arty_Z7_20_axi_gpio_shield_1_0,axi_gpio,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; - ATTRIBUTE CORE_GENERATION_INFO OF Arty_Z7_20_axi_gpio_shield_1_0_arch: ARCHITECTURE IS "Arty_Z7_20_axi_gpio_shield_1_0,axi_gpio,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=13,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=14,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=1,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}"; + ATTRIBUTE CORE_GENERATION_INFO OF Arty_Z7_20_axi_gpio_shield_1_0_arch: ARCHITECTURE IS "Arty_Z7_20_axi_gpio_shield_1_0,axi_gpio,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=13,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=14,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST"; @@ -160,7 +159,6 @@ ARCHITECTURE Arty_Z7_20_axi_gpio_shield_1_0_arch OF Arty_Z7_20_axi_gpio_shield_1 ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; - ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT"; ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I"; ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O"; ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T"; @@ -176,7 +174,7 @@ BEGIN C_ALL_INPUTS_2 => 0, C_ALL_OUTPUTS => 0, C_ALL_OUTPUTS_2 => 0, - C_INTERRUPT_PRESENT => 1, + C_INTERRUPT_PRESENT => 0, C_DOUT_DEFAULT => X"00000000", C_TRI_DEFAULT => X"FFFFFFFF", C_IS_DUAL => 0, @@ -203,7 +201,6 @@ BEGIN s_axi_rresp => s_axi_rresp, s_axi_rvalid => s_axi_rvalid, s_axi_rready => s_axi_rready, - ip2intc_irpt => ip2intc_irpt, gpio_io_i => gpio_io_i, gpio_io_o => gpio_io_o, gpio_io_t => gpio_io_t, diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0.dcp b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0.dcp index 8d88eec..437d1e1 100644 Binary files a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0.dcp and b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0.dcp differ diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0.xci b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0.xci index 1d4b191..ff34b0c 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0.xci +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0.xci @@ -1,135 +1,172 @@ - - xilinx.com - xci - unknown - 1.0 - - - Arty_Z7_20_axi_gpio_shield_2_0 - - - 1 - 9 - 0 - 0 - 0 - Arty_Z7_20_processing_system7_0_0_FCLK_CLK0 - 32 - 100000000 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 1 - 2 - 1 - 2 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - Arty_Z7_20_processing_system7_0_0_FCLK_CLK0 - 100000000 - 0.000 - 0 - 0 - 0 - 0 - 0x00000000 - 0x00000000 - zynq - 32 - 16 - 1 - 0 - 0xFFFFFFFF - 0xFFFFFFFF - 0 - 0 - 0 - 0 - 0x00000000 - 0x00000000 - 32 - 16 - 1 - 0 - 0xFFFFFFFF - 0xFFFFFFFF - Arty_Z7_20_axi_gpio_shield_2_0 - Custom - shield_dp26_dp41 - true - zynq - digilentinc.com:arty-z7-20:part0:1.0 - xc7z020 - clg400 - VHDL - - MIXED - -1 - - TRUE - TRUE - IP_Integrator - 13 - TRUE - . - - ../../ipshared - 2016.4 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + xilinx.com + xci + unknown + 1.0 + + + Arty_Z7_20_axi_gpio_shield_2_0 + + + 1 + 9 + 0 + 0 + 0 + Arty_Z7_20_processing_system7_0_0_FCLK_CLK0 + 32 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 2 + 1 + 2 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + Arty_Z7_20_processing_system7_0_0_FCLK_CLK0 + 100000000 + 0.000 + 0 + 0 + 0 + 0 + 0x00000000 + 0x00000000 + zynq + 32 + 16 + 0 + 0 + 0xFFFFFFFF + 0xFFFFFFFF + 0 + 0 + 0 + 0 + 0x00000000 + 0x00000000 + 32 + 16 + 0 + 0 + 0xFFFFFFFF + 0xFFFFFFFF + Arty_Z7_20_axi_gpio_shield_2_0 + Custom + shield_dp26_dp41 + true + zynq + digilentinc.com:arty-z7-20:part0:1.0 + xc7z020 + clg400 + VHDL + + MIXED + -1 + + TRUE + TRUE + IP_Integrator + 13 + TRUE + . + + ../../ipshared + 2016.4 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0.xml b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0.xml index a52037f..2d76c2d 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0.xml +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0.xml @@ -365,7 +365,7 @@ - true + false @@ -767,7 +767,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output boundaryCRC - eeee2639 + 5e1a8bdd boundaryCRCversion @@ -775,7 +775,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output customizationCRC - 065d483b + 3f672537 customizationCRCversion @@ -794,11 +794,11 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output GENtimestamp - Fri Feb 24 23:57:48 UTC 2017 + Sun Mar 05 02:51:00 UTC 2017 boundaryCRC - eeee2639 + 5e1a8bdd boundaryCRCversion @@ -806,7 +806,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output customizationCRC - 065d483b + 3f672537 customizationCRCversion @@ -838,7 +838,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output boundaryCRC - eeee2639 + 5e1a8bdd boundaryCRCversion @@ -846,7 +846,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output customizationCRC - ef75244a + c0ff232f customizationCRCversion @@ -865,11 +865,11 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output GENtimestamp - Fri Feb 24 23:57:48 UTC 2017 + Sun Mar 05 02:51:00 UTC 2017 boundaryCRC - eeee2639 + 5e1a8bdd boundaryCRCversion @@ -877,7 +877,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output customizationCRC - ef75244a + c0ff232f customizationCRCversion @@ -895,11 +895,11 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output GENtimestamp - Fri Feb 24 23:57:48 UTC 2017 + Sun Mar 05 02:51:01 UTC 2017 boundaryCRC - eeee2639 + 5e1a8bdd boundaryCRCversion @@ -907,7 +907,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output customizationCRC - 065d483b + 3f672537 customizationCRCversion @@ -925,11 +925,11 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output GENtimestamp - Sat Feb 25 00:00:40 UTC 2017 + Sun Mar 05 02:53:03 UTC 2017 boundaryCRC - eeee2639 + 5e1a8bdd boundaryCRCversion @@ -937,7 +937,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output customizationCRC - 065d483b + 3f672537 customizationCRCversion @@ -1270,7 +1270,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output - true + false @@ -1474,7 +1474,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output C_INTERRUPT_PRESENT Enable Interrupt - 1 + 0 C_DOUT_DEFAULT @@ -1818,7 +1818,7 @@ Each I/O pin of the AXI GPIO is individually programmable as an input or output C_INTERRUPT_PRESENT Enable Interrupt - 1 + 0 diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0_sim_netlist.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0_sim_netlist.v index f082683..6956823 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0_sim_netlist.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -// Date : Fri Feb 24 16:00:40 2017 +// Date : Sat Mar 04 18:53:03 2017 // Host : WK73 running 64-bit Service Pack 1 (build 7601) // Command : write_verilog -force -mode funcsim -// c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0_sim_netlist.v +// C:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0_sim_netlist.v // Design : Arty_Z7_20_axi_gpio_shield_2_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -34,7 +34,6 @@ module Arty_Z7_20_axi_gpio_shield_2_0 s_axi_rresp, s_axi_rvalid, s_axi_rready, - ip2intc_irpt, gpio_io_i, gpio_io_o, gpio_io_t); @@ -57,7 +56,6 @@ module Arty_Z7_20_axi_gpio_shield_2_0 (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp; (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid; (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready; - (* x_interface_info = "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT" *) output ip2intc_irpt; (* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_I" *) input [15:0]gpio_io_i; (* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_O" *) output [15:0]gpio_io_o; (* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_T" *) output [15:0]gpio_io_t; @@ -65,7 +63,6 @@ module Arty_Z7_20_axi_gpio_shield_2_0 wire [15:0]gpio_io_i; wire [15:0]gpio_io_o; wire [15:0]gpio_io_t; - wire ip2intc_irpt; wire s_axi_aclk; wire [8:0]s_axi_araddr; wire s_axi_aresetn; @@ -85,6 +82,7 @@ module Arty_Z7_20_axi_gpio_shield_2_0 wire s_axi_wready; wire [3:0]s_axi_wstrb; wire s_axi_wvalid; + wire NLW_U0_ip2intc_irpt_UNCONNECTED; wire [31:0]NLW_U0_gpio2_io_o_UNCONNECTED; wire [31:0]NLW_U0_gpio2_io_t_UNCONNECTED; @@ -97,7 +95,7 @@ module Arty_Z7_20_axi_gpio_shield_2_0 (* C_FAMILY = "zynq" *) (* C_GPIO2_WIDTH = "32" *) (* C_GPIO_WIDTH = "16" *) - (* C_INTERRUPT_PRESENT = "1" *) + (* C_INTERRUPT_PRESENT = "0" *) (* C_IS_DUAL = "0" *) (* C_S_AXI_ADDR_WIDTH = "9" *) (* C_S_AXI_DATA_WIDTH = "32" *) @@ -112,7 +110,7 @@ module Arty_Z7_20_axi_gpio_shield_2_0 .gpio_io_i(gpio_io_i), .gpio_io_o(gpio_io_o), .gpio_io_t(gpio_io_t), - .ip2intc_irpt(ip2intc_irpt), + .ip2intc_irpt(NLW_U0_ip2intc_irpt_UNCONNECTED), .s_axi_aclk(s_axi_aclk), .s_axi_araddr(s_axi_araddr), .s_axi_aresetn(s_axi_aresetn), @@ -136,357 +134,209 @@ endmodule (* ORIG_REF_NAME = "GPIO_Core" *) module Arty_Z7_20_axi_gpio_shield_2_0_GPIO_Core - (ip2bus_data, + (D, GPIO_xferAck_i, gpio_xferAck_Reg, - GPIO_intr, - Q, + ip2bus_rdack_i, + ip2bus_wrack_i_D1_reg, gpio_io_o, gpio_io_t, - Read_Reg_Rst, - \Not_Dual.gpio_OE_reg[15]_0 , + Q, + bus2ip_rnw_i_reg, + \Not_Dual.gpio_Data_In_reg[15]_0 , s_axi_aclk, - \Not_Dual.gpio_OE_reg[14]_0 , - \Not_Dual.gpio_OE_reg[13]_0 , - \Not_Dual.gpio_OE_reg[12]_0 , - \Not_Dual.gpio_OE_reg[11]_0 , - \Not_Dual.gpio_OE_reg[10]_0 , - \Not_Dual.gpio_OE_reg[9]_0 , - \Not_Dual.gpio_OE_reg[8]_0 , - \Not_Dual.gpio_OE_reg[7]_0 , - \Not_Dual.gpio_OE_reg[6]_0 , - \Not_Dual.gpio_OE_reg[5]_0 , - \Not_Dual.gpio_OE_reg[4]_0 , - \Not_Dual.gpio_OE_reg[3]_0 , - \Not_Dual.gpio_OE_reg[2]_0 , - \Not_Dual.gpio_OE_reg[1]_0 , + \Not_Dual.gpio_Data_In_reg[14]_0 , + \Not_Dual.gpio_Data_In_reg[13]_0 , + \Not_Dual.gpio_Data_In_reg[12]_0 , + \Not_Dual.gpio_Data_In_reg[11]_0 , + \Not_Dual.gpio_Data_In_reg[10]_0 , + \Not_Dual.gpio_Data_In_reg[9]_0 , + \Not_Dual.gpio_Data_In_reg[8]_0 , + \Not_Dual.gpio_Data_In_reg[7]_0 , + \Not_Dual.gpio_Data_In_reg[6]_0 , + \Not_Dual.gpio_Data_In_reg[5]_0 , + \Not_Dual.gpio_Data_In_reg[4]_0 , + \Not_Dual.gpio_Data_In_reg[3]_0 , + \Not_Dual.gpio_Data_In_reg[2]_0 , + \Not_Dual.gpio_Data_In_reg[1]_0 , GPIO_DBus_i, - bus2ip_reset, + SS, + bus2ip_rnw, bus2ip_cs, gpio_io_i, E, - D, - bus2ip_rnw_i_reg); - output [15:0]ip2bus_data; + \MEM_DECODE_GEN[0].cs_out_i_reg[0] , + rst_reg); + output [15:0]D; output GPIO_xferAck_i; output gpio_xferAck_Reg; - output GPIO_intr; - output [15:0]Q; + output ip2bus_rdack_i; + output ip2bus_wrack_i_D1_reg; output [15:0]gpio_io_o; output [15:0]gpio_io_t; - input Read_Reg_Rst; - input \Not_Dual.gpio_OE_reg[15]_0 ; + output [15:0]Q; + input bus2ip_rnw_i_reg; + input \Not_Dual.gpio_Data_In_reg[15]_0 ; input s_axi_aclk; - input \Not_Dual.gpio_OE_reg[14]_0 ; - input \Not_Dual.gpio_OE_reg[13]_0 ; - input \Not_Dual.gpio_OE_reg[12]_0 ; - input \Not_Dual.gpio_OE_reg[11]_0 ; - input \Not_Dual.gpio_OE_reg[10]_0 ; - input \Not_Dual.gpio_OE_reg[9]_0 ; - input \Not_Dual.gpio_OE_reg[8]_0 ; - input \Not_Dual.gpio_OE_reg[7]_0 ; - input \Not_Dual.gpio_OE_reg[6]_0 ; - input \Not_Dual.gpio_OE_reg[5]_0 ; - input \Not_Dual.gpio_OE_reg[4]_0 ; - input \Not_Dual.gpio_OE_reg[3]_0 ; - input \Not_Dual.gpio_OE_reg[2]_0 ; - input \Not_Dual.gpio_OE_reg[1]_0 ; + input \Not_Dual.gpio_Data_In_reg[14]_0 ; + input \Not_Dual.gpio_Data_In_reg[13]_0 ; + input \Not_Dual.gpio_Data_In_reg[12]_0 ; + input \Not_Dual.gpio_Data_In_reg[11]_0 ; + input \Not_Dual.gpio_Data_In_reg[10]_0 ; + input \Not_Dual.gpio_Data_In_reg[9]_0 ; + input \Not_Dual.gpio_Data_In_reg[8]_0 ; + input \Not_Dual.gpio_Data_In_reg[7]_0 ; + input \Not_Dual.gpio_Data_In_reg[6]_0 ; + input \Not_Dual.gpio_Data_In_reg[5]_0 ; + input \Not_Dual.gpio_Data_In_reg[4]_0 ; + input \Not_Dual.gpio_Data_In_reg[3]_0 ; + input \Not_Dual.gpio_Data_In_reg[2]_0 ; + input \Not_Dual.gpio_Data_In_reg[1]_0 ; input [0:0]GPIO_DBus_i; - input bus2ip_reset; - input [0:0]bus2ip_cs; + input [0:0]SS; + input bus2ip_rnw; + input bus2ip_cs; input [15:0]gpio_io_i; input [0:0]E; - input [15:0]D; - input [0:0]bus2ip_rnw_i_reg; + input [15:0]\MEM_DECODE_GEN[0].cs_out_i_reg[0] ; + input [0:0]rst_reg; wire [15:0]D; wire [0:0]E; wire [0:0]GPIO_DBus_i; - wire GPIO_intr; wire GPIO_xferAck_i; - wire \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0 ; - wire \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3_n_0 ; - wire \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0] ; - wire \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[11] ; - wire \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[15] ; - wire \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1] ; - wire \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[8] ; - wire \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[9] ; - wire \Not_Dual.gpio_OE_reg[10]_0 ; - wire \Not_Dual.gpio_OE_reg[11]_0 ; - wire \Not_Dual.gpio_OE_reg[12]_0 ; - wire \Not_Dual.gpio_OE_reg[13]_0 ; - wire \Not_Dual.gpio_OE_reg[14]_0 ; - wire \Not_Dual.gpio_OE_reg[15]_0 ; - wire \Not_Dual.gpio_OE_reg[1]_0 ; - wire \Not_Dual.gpio_OE_reg[2]_0 ; - wire \Not_Dual.gpio_OE_reg[3]_0 ; - wire \Not_Dual.gpio_OE_reg[4]_0 ; - wire \Not_Dual.gpio_OE_reg[5]_0 ; - wire \Not_Dual.gpio_OE_reg[6]_0 ; - wire \Not_Dual.gpio_OE_reg[7]_0 ; - wire \Not_Dual.gpio_OE_reg[8]_0 ; - wire \Not_Dual.gpio_OE_reg[9]_0 ; + wire [15:0]\MEM_DECODE_GEN[0].cs_out_i_reg[0] ; + wire \Not_Dual.gpio_Data_In_reg[10]_0 ; + wire \Not_Dual.gpio_Data_In_reg[11]_0 ; + wire \Not_Dual.gpio_Data_In_reg[12]_0 ; + wire \Not_Dual.gpio_Data_In_reg[13]_0 ; + wire \Not_Dual.gpio_Data_In_reg[14]_0 ; + wire \Not_Dual.gpio_Data_In_reg[15]_0 ; + wire \Not_Dual.gpio_Data_In_reg[1]_0 ; + wire \Not_Dual.gpio_Data_In_reg[2]_0 ; + wire \Not_Dual.gpio_Data_In_reg[3]_0 ; + wire \Not_Dual.gpio_Data_In_reg[4]_0 ; + wire \Not_Dual.gpio_Data_In_reg[5]_0 ; + wire \Not_Dual.gpio_Data_In_reg[6]_0 ; + wire \Not_Dual.gpio_Data_In_reg[7]_0 ; + wire \Not_Dual.gpio_Data_In_reg[8]_0 ; + wire \Not_Dual.gpio_Data_In_reg[9]_0 ; wire [15:0]Q; - wire Read_Reg_Rst; - wire [0:0]bus2ip_cs; - wire bus2ip_reset; - wire [0:0]bus2ip_rnw_i_reg; - wire [0:15]gpio_data_in_xor; + wire [0:0]SS; + wire bus2ip_cs; + wire bus2ip_rnw; + wire bus2ip_rnw_i_reg; wire [15:0]gpio_io_i; wire [0:15]gpio_io_i_d2; wire [15:0]gpio_io_o; wire [15:0]gpio_io_t; wire gpio_xferAck_Reg; wire iGPIO_xferAck; - wire [15:0]ip2bus_data; - wire or_ints; - wire p_11_in; - wire p_12_in; - wire p_13_in; - wire p_1_in; - wire p_2_in; - wire p_3_in; - wire p_4_in; - wire p_5_in; - wire p_6_in; - wire p_9_in; + wire ip2bus_rdack_i; + wire ip2bus_wrack_i_D1_reg; + wire [0:0]rst_reg; wire s_axi_aclk; - LUT6 #( - .INIT(64'hFFFFFFFFFFFFFFFE)) - \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_1 - (.I0(p_12_in), - .I1(p_11_in), - .I2(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[15] ), - .I3(p_13_in), - .I4(\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0 ), - .I5(\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3_n_0 ), - .O(or_ints)); - LUT6 #( - .INIT(64'hFFFFFFFFFFFFFFFE)) - \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2 - (.I0(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1] ), - .I1(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0] ), - .I2(p_2_in), - .I3(p_1_in), - .I4(p_3_in), - .I5(p_4_in), - .O(\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0 )); - LUT6 #( - .INIT(64'hFFFFFFFFFFFFFFFE)) - \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3 - (.I0(p_6_in), - .I1(p_5_in), - .I2(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[9] ), - .I3(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[8] ), - .I4(p_9_in), - .I5(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[11] ), - .O(\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3_n_0 )); - FDRE \Not_Dual.GEN_INTERRUPT.GPIO_intr_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(or_ints), - .Q(GPIO_intr), - .R(bus2ip_reset)); - FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[0] - (.C(s_axi_aclk), - .CE(1'b1), - .D(gpio_data_in_xor[0]), - .Q(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0] ), - .R(bus2ip_reset)); - FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[10] - (.C(s_axi_aclk), - .CE(1'b1), - .D(gpio_data_in_xor[10]), - .Q(p_9_in), - .R(bus2ip_reset)); - FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[11] - (.C(s_axi_aclk), - .CE(1'b1), - .D(gpio_data_in_xor[11]), - .Q(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[11] ), - .R(bus2ip_reset)); - FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[12] - (.C(s_axi_aclk), - .CE(1'b1), - .D(gpio_data_in_xor[12]), - .Q(p_11_in), - .R(bus2ip_reset)); - FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[13] - (.C(s_axi_aclk), - .CE(1'b1), - .D(gpio_data_in_xor[13]), - .Q(p_12_in), - .R(bus2ip_reset)); - FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[14] - (.C(s_axi_aclk), - .CE(1'b1), - .D(gpio_data_in_xor[14]), - .Q(p_13_in), - .R(bus2ip_reset)); - FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[15] - (.C(s_axi_aclk), - .CE(1'b1), - .D(gpio_data_in_xor[15]), - .Q(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[15] ), - .R(bus2ip_reset)); - FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[1] - (.C(s_axi_aclk), - .CE(1'b1), - .D(gpio_data_in_xor[1]), - .Q(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1] ), - .R(bus2ip_reset)); - FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[2] - (.C(s_axi_aclk), - .CE(1'b1), - .D(gpio_data_in_xor[2]), - .Q(p_1_in), - .R(bus2ip_reset)); - FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[3] - (.C(s_axi_aclk), - .CE(1'b1), - .D(gpio_data_in_xor[3]), - .Q(p_2_in), - .R(bus2ip_reset)); - FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[4] - (.C(s_axi_aclk), - .CE(1'b1), - .D(gpio_data_in_xor[4]), - .Q(p_3_in), - .R(bus2ip_reset)); - FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[5] - (.C(s_axi_aclk), - .CE(1'b1), - .D(gpio_data_in_xor[5]), - .Q(p_4_in), - .R(bus2ip_reset)); - FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[6] - (.C(s_axi_aclk), - .CE(1'b1), - .D(gpio_data_in_xor[6]), - .Q(p_5_in), - .R(bus2ip_reset)); - FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[7] - (.C(s_axi_aclk), - .CE(1'b1), - .D(gpio_data_in_xor[7]), - .Q(p_6_in), - .R(bus2ip_reset)); - FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[8] - (.C(s_axi_aclk), - .CE(1'b1), - .D(gpio_data_in_xor[8]), - .Q(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[8] ), - .R(bus2ip_reset)); - FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[9] - (.C(s_axi_aclk), - .CE(1'b1), - .D(gpio_data_in_xor[9]), - .Q(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[9] ), - .R(bus2ip_reset)); Arty_Z7_20_axi_gpio_shield_2_0_cdc_sync \Not_Dual.INPUT_DOUBLE_REGS3 - (.D({gpio_data_in_xor[0],gpio_data_in_xor[1],gpio_data_in_xor[2],gpio_data_in_xor[3],gpio_data_in_xor[4],gpio_data_in_xor[5],gpio_data_in_xor[6],gpio_data_in_xor[7],gpio_data_in_xor[8],gpio_data_in_xor[9],gpio_data_in_xor[10],gpio_data_in_xor[11],gpio_data_in_xor[12],gpio_data_in_xor[13],gpio_data_in_xor[14],gpio_data_in_xor[15]}), - .Q(Q), - .gpio_io_i(gpio_io_i), + (.gpio_io_i(gpio_io_i), .s_axi_aclk(s_axi_aclk), .scndry_vect_out({gpio_io_i_d2[0],gpio_io_i_d2[1],gpio_io_i_d2[2],gpio_io_i_d2[3],gpio_io_i_d2[4],gpio_io_i_d2[5],gpio_io_i_d2[6],gpio_io_i_d2[7],gpio_io_i_d2[8],gpio_io_i_d2[9],gpio_io_i_d2[10],gpio_io_i_d2[11],gpio_io_i_d2[12],gpio_io_i_d2[13],gpio_io_i_d2[14],gpio_io_i_d2[15]})); FDRE \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[16] (.C(s_axi_aclk), .CE(1'b1), .D(GPIO_DBus_i), - .Q(ip2bus_data[15]), - .R(Read_Reg_Rst)); + .Q(D[15]), + .R(bus2ip_rnw_i_reg)); FDRE \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] (.C(s_axi_aclk), .CE(1'b1), - .D(\Not_Dual.gpio_OE_reg[10]_0 ), - .Q(ip2bus_data[5]), - .R(Read_Reg_Rst)); + .D(\Not_Dual.gpio_Data_In_reg[10]_0 ), + .Q(D[5]), + .R(bus2ip_rnw_i_reg)); FDRE \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] (.C(s_axi_aclk), .CE(1'b1), - .D(\Not_Dual.gpio_OE_reg[11]_0 ), - .Q(ip2bus_data[4]), - .R(Read_Reg_Rst)); + .D(\Not_Dual.gpio_Data_In_reg[11]_0 ), + .Q(D[4]), + .R(bus2ip_rnw_i_reg)); FDRE \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] (.C(s_axi_aclk), .CE(1'b1), - .D(\Not_Dual.gpio_OE_reg[12]_0 ), - .Q(ip2bus_data[3]), - .R(Read_Reg_Rst)); + .D(\Not_Dual.gpio_Data_In_reg[12]_0 ), + .Q(D[3]), + .R(bus2ip_rnw_i_reg)); FDRE \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] (.C(s_axi_aclk), .CE(1'b1), - .D(\Not_Dual.gpio_OE_reg[13]_0 ), - .Q(ip2bus_data[2]), - .R(Read_Reg_Rst)); + .D(\Not_Dual.gpio_Data_In_reg[13]_0 ), + .Q(D[2]), + .R(bus2ip_rnw_i_reg)); FDRE \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] (.C(s_axi_aclk), .CE(1'b1), - .D(\Not_Dual.gpio_OE_reg[14]_0 ), - .Q(ip2bus_data[1]), - .R(Read_Reg_Rst)); + .D(\Not_Dual.gpio_Data_In_reg[14]_0 ), + .Q(D[1]), + .R(bus2ip_rnw_i_reg)); FDRE \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31] (.C(s_axi_aclk), .CE(1'b1), - .D(\Not_Dual.gpio_OE_reg[15]_0 ), - .Q(ip2bus_data[0]), - .R(Read_Reg_Rst)); + .D(\Not_Dual.gpio_Data_In_reg[15]_0 ), + .Q(D[0]), + .R(bus2ip_rnw_i_reg)); FDRE \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] (.C(s_axi_aclk), .CE(1'b1), - .D(\Not_Dual.gpio_OE_reg[1]_0 ), - .Q(ip2bus_data[14]), - .R(Read_Reg_Rst)); + .D(\Not_Dual.gpio_Data_In_reg[1]_0 ), + .Q(D[14]), + .R(bus2ip_rnw_i_reg)); FDRE \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] (.C(s_axi_aclk), .CE(1'b1), - .D(\Not_Dual.gpio_OE_reg[2]_0 ), - .Q(ip2bus_data[13]), - .R(Read_Reg_Rst)); + .D(\Not_Dual.gpio_Data_In_reg[2]_0 ), + .Q(D[13]), + .R(bus2ip_rnw_i_reg)); FDRE \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] (.C(s_axi_aclk), .CE(1'b1), - .D(\Not_Dual.gpio_OE_reg[3]_0 ), - .Q(ip2bus_data[12]), - .R(Read_Reg_Rst)); + .D(\Not_Dual.gpio_Data_In_reg[3]_0 ), + .Q(D[12]), + .R(bus2ip_rnw_i_reg)); FDRE \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] (.C(s_axi_aclk), .CE(1'b1), - .D(\Not_Dual.gpio_OE_reg[4]_0 ), - .Q(ip2bus_data[11]), - .R(Read_Reg_Rst)); + .D(\Not_Dual.gpio_Data_In_reg[4]_0 ), + .Q(D[11]), + .R(bus2ip_rnw_i_reg)); FDRE \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] (.C(s_axi_aclk), .CE(1'b1), - .D(\Not_Dual.gpio_OE_reg[5]_0 ), - .Q(ip2bus_data[10]), - .R(Read_Reg_Rst)); + .D(\Not_Dual.gpio_Data_In_reg[5]_0 ), + .Q(D[10]), + .R(bus2ip_rnw_i_reg)); FDRE \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] (.C(s_axi_aclk), .CE(1'b1), - .D(\Not_Dual.gpio_OE_reg[6]_0 ), - .Q(ip2bus_data[9]), - .R(Read_Reg_Rst)); + .D(\Not_Dual.gpio_Data_In_reg[6]_0 ), + .Q(D[9]), + .R(bus2ip_rnw_i_reg)); FDRE \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] (.C(s_axi_aclk), .CE(1'b1), - .D(\Not_Dual.gpio_OE_reg[7]_0 ), - .Q(ip2bus_data[8]), - .R(Read_Reg_Rst)); + .D(\Not_Dual.gpio_Data_In_reg[7]_0 ), + .Q(D[8]), + .R(bus2ip_rnw_i_reg)); FDRE \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] (.C(s_axi_aclk), .CE(1'b1), - .D(\Not_Dual.gpio_OE_reg[8]_0 ), - .Q(ip2bus_data[7]), - .R(Read_Reg_Rst)); + .D(\Not_Dual.gpio_Data_In_reg[8]_0 ), + .Q(D[7]), + .R(bus2ip_rnw_i_reg)); FDRE \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] (.C(s_axi_aclk), .CE(1'b1), - .D(\Not_Dual.gpio_OE_reg[9]_0 ), - .Q(ip2bus_data[6]), - .R(Read_Reg_Rst)); + .D(\Not_Dual.gpio_Data_In_reg[9]_0 ), + .Q(D[6]), + .R(bus2ip_rnw_i_reg)); FDRE \Not_Dual.gpio_Data_In_reg[0] (.C(s_axi_aclk), .CE(1'b1), @@ -588,417 +438,381 @@ module Arty_Z7_20_axi_gpio_shield_2_0_GPIO_Core \Not_Dual.gpio_Data_Out_reg[0] (.C(s_axi_aclk), .CE(E), - .D(D[15]), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [15]), .Q(gpio_io_o[15]), - .R(bus2ip_reset)); + .R(SS)); FDRE #( .INIT(1'b0)) \Not_Dual.gpio_Data_Out_reg[10] (.C(s_axi_aclk), .CE(E), - .D(D[5]), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [5]), .Q(gpio_io_o[5]), - .R(bus2ip_reset)); + .R(SS)); FDRE #( .INIT(1'b0)) \Not_Dual.gpio_Data_Out_reg[11] (.C(s_axi_aclk), .CE(E), - .D(D[4]), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [4]), .Q(gpio_io_o[4]), - .R(bus2ip_reset)); + .R(SS)); FDRE #( .INIT(1'b0)) \Not_Dual.gpio_Data_Out_reg[12] (.C(s_axi_aclk), .CE(E), - .D(D[3]), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [3]), .Q(gpio_io_o[3]), - .R(bus2ip_reset)); + .R(SS)); FDRE #( .INIT(1'b0)) \Not_Dual.gpio_Data_Out_reg[13] (.C(s_axi_aclk), .CE(E), - .D(D[2]), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [2]), .Q(gpio_io_o[2]), - .R(bus2ip_reset)); + .R(SS)); FDRE #( .INIT(1'b0)) \Not_Dual.gpio_Data_Out_reg[14] (.C(s_axi_aclk), .CE(E), - .D(D[1]), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [1]), .Q(gpio_io_o[1]), - .R(bus2ip_reset)); + .R(SS)); FDRE #( .INIT(1'b0)) \Not_Dual.gpio_Data_Out_reg[15] (.C(s_axi_aclk), .CE(E), - .D(D[0]), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [0]), .Q(gpio_io_o[0]), - .R(bus2ip_reset)); + .R(SS)); FDRE #( .INIT(1'b0)) \Not_Dual.gpio_Data_Out_reg[1] (.C(s_axi_aclk), .CE(E), - .D(D[14]), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [14]), .Q(gpio_io_o[14]), - .R(bus2ip_reset)); + .R(SS)); FDRE #( .INIT(1'b0)) \Not_Dual.gpio_Data_Out_reg[2] (.C(s_axi_aclk), .CE(E), - .D(D[13]), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [13]), .Q(gpio_io_o[13]), - .R(bus2ip_reset)); + .R(SS)); FDRE #( .INIT(1'b0)) \Not_Dual.gpio_Data_Out_reg[3] (.C(s_axi_aclk), .CE(E), - .D(D[12]), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [12]), .Q(gpio_io_o[12]), - .R(bus2ip_reset)); + .R(SS)); FDRE #( .INIT(1'b0)) \Not_Dual.gpio_Data_Out_reg[4] (.C(s_axi_aclk), .CE(E), - .D(D[11]), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [11]), .Q(gpio_io_o[11]), - .R(bus2ip_reset)); + .R(SS)); FDRE #( .INIT(1'b0)) \Not_Dual.gpio_Data_Out_reg[5] (.C(s_axi_aclk), .CE(E), - .D(D[10]), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [10]), .Q(gpio_io_o[10]), - .R(bus2ip_reset)); + .R(SS)); FDRE #( .INIT(1'b0)) \Not_Dual.gpio_Data_Out_reg[6] (.C(s_axi_aclk), .CE(E), - .D(D[9]), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [9]), .Q(gpio_io_o[9]), - .R(bus2ip_reset)); + .R(SS)); FDRE #( .INIT(1'b0)) \Not_Dual.gpio_Data_Out_reg[7] (.C(s_axi_aclk), .CE(E), - .D(D[8]), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [8]), .Q(gpio_io_o[8]), - .R(bus2ip_reset)); + .R(SS)); FDRE #( .INIT(1'b0)) \Not_Dual.gpio_Data_Out_reg[8] (.C(s_axi_aclk), .CE(E), - .D(D[7]), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [7]), .Q(gpio_io_o[7]), - .R(bus2ip_reset)); + .R(SS)); FDRE #( .INIT(1'b0)) \Not_Dual.gpio_Data_Out_reg[9] (.C(s_axi_aclk), .CE(E), - .D(D[6]), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [6]), .Q(gpio_io_o[6]), - .R(bus2ip_reset)); + .R(SS)); FDSE #( .INIT(1'b1)) \Not_Dual.gpio_OE_reg[0] (.C(s_axi_aclk), - .CE(bus2ip_rnw_i_reg), - .D(D[15]), + .CE(rst_reg), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [15]), .Q(gpio_io_t[15]), - .S(bus2ip_reset)); + .S(SS)); FDSE #( .INIT(1'b1)) \Not_Dual.gpio_OE_reg[10] (.C(s_axi_aclk), - .CE(bus2ip_rnw_i_reg), - .D(D[5]), + .CE(rst_reg), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [5]), .Q(gpio_io_t[5]), - .S(bus2ip_reset)); + .S(SS)); FDSE #( .INIT(1'b1)) \Not_Dual.gpio_OE_reg[11] (.C(s_axi_aclk), - .CE(bus2ip_rnw_i_reg), - .D(D[4]), + .CE(rst_reg), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [4]), .Q(gpio_io_t[4]), - .S(bus2ip_reset)); + .S(SS)); FDSE #( .INIT(1'b1)) \Not_Dual.gpio_OE_reg[12] (.C(s_axi_aclk), - .CE(bus2ip_rnw_i_reg), - .D(D[3]), + .CE(rst_reg), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [3]), .Q(gpio_io_t[3]), - .S(bus2ip_reset)); + .S(SS)); FDSE #( .INIT(1'b1)) \Not_Dual.gpio_OE_reg[13] (.C(s_axi_aclk), - .CE(bus2ip_rnw_i_reg), - .D(D[2]), + .CE(rst_reg), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [2]), .Q(gpio_io_t[2]), - .S(bus2ip_reset)); + .S(SS)); FDSE #( .INIT(1'b1)) \Not_Dual.gpio_OE_reg[14] (.C(s_axi_aclk), - .CE(bus2ip_rnw_i_reg), - .D(D[1]), + .CE(rst_reg), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [1]), .Q(gpio_io_t[1]), - .S(bus2ip_reset)); + .S(SS)); FDSE #( .INIT(1'b1)) \Not_Dual.gpio_OE_reg[15] (.C(s_axi_aclk), - .CE(bus2ip_rnw_i_reg), - .D(D[0]), + .CE(rst_reg), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [0]), .Q(gpio_io_t[0]), - .S(bus2ip_reset)); + .S(SS)); FDSE #( .INIT(1'b1)) \Not_Dual.gpio_OE_reg[1] (.C(s_axi_aclk), - .CE(bus2ip_rnw_i_reg), - .D(D[14]), + .CE(rst_reg), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [14]), .Q(gpio_io_t[14]), - .S(bus2ip_reset)); + .S(SS)); FDSE #( .INIT(1'b1)) \Not_Dual.gpio_OE_reg[2] (.C(s_axi_aclk), - .CE(bus2ip_rnw_i_reg), - .D(D[13]), + .CE(rst_reg), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [13]), .Q(gpio_io_t[13]), - .S(bus2ip_reset)); + .S(SS)); FDSE #( .INIT(1'b1)) \Not_Dual.gpio_OE_reg[3] (.C(s_axi_aclk), - .CE(bus2ip_rnw_i_reg), - .D(D[12]), + .CE(rst_reg), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [12]), .Q(gpio_io_t[12]), - .S(bus2ip_reset)); + .S(SS)); FDSE #( .INIT(1'b1)) \Not_Dual.gpio_OE_reg[4] (.C(s_axi_aclk), - .CE(bus2ip_rnw_i_reg), - .D(D[11]), + .CE(rst_reg), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [11]), .Q(gpio_io_t[11]), - .S(bus2ip_reset)); + .S(SS)); FDSE #( .INIT(1'b1)) \Not_Dual.gpio_OE_reg[5] (.C(s_axi_aclk), - .CE(bus2ip_rnw_i_reg), - .D(D[10]), + .CE(rst_reg), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [10]), .Q(gpio_io_t[10]), - .S(bus2ip_reset)); + .S(SS)); FDSE #( .INIT(1'b1)) \Not_Dual.gpio_OE_reg[6] (.C(s_axi_aclk), - .CE(bus2ip_rnw_i_reg), - .D(D[9]), + .CE(rst_reg), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [9]), .Q(gpio_io_t[9]), - .S(bus2ip_reset)); + .S(SS)); FDSE #( .INIT(1'b1)) \Not_Dual.gpio_OE_reg[7] (.C(s_axi_aclk), - .CE(bus2ip_rnw_i_reg), - .D(D[8]), + .CE(rst_reg), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [8]), .Q(gpio_io_t[8]), - .S(bus2ip_reset)); + .S(SS)); FDSE #( .INIT(1'b1)) \Not_Dual.gpio_OE_reg[8] (.C(s_axi_aclk), - .CE(bus2ip_rnw_i_reg), - .D(D[7]), + .CE(rst_reg), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [7]), .Q(gpio_io_t[7]), - .S(bus2ip_reset)); + .S(SS)); FDSE #( .INIT(1'b1)) \Not_Dual.gpio_OE_reg[9] (.C(s_axi_aclk), - .CE(bus2ip_rnw_i_reg), - .D(D[6]), + .CE(rst_reg), + .D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [6]), .Q(gpio_io_t[6]), - .S(bus2ip_reset)); + .S(SS)); FDRE gpio_xferAck_Reg_reg (.C(s_axi_aclk), .CE(1'b1), .D(GPIO_xferAck_i), .Q(gpio_xferAck_Reg), - .R(bus2ip_reset)); + .R(SS)); + (* SOFT_HLUTNM = "soft_lutpair4" *) LUT3 #( - .INIT(8'h10)) + .INIT(8'h02)) iGPIO_xferAck_i_1 - (.I0(gpio_xferAck_Reg), - .I1(GPIO_xferAck_i), - .I2(bus2ip_cs), + (.I0(bus2ip_cs), + .I1(gpio_xferAck_Reg), + .I2(GPIO_xferAck_i), .O(iGPIO_xferAck)); FDRE iGPIO_xferAck_reg (.C(s_axi_aclk), .CE(1'b1), .D(iGPIO_xferAck), .Q(GPIO_xferAck_i), - .R(bus2ip_reset)); + .R(SS)); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h8)) + ip2bus_rdack_i_D1_i_1 + (.I0(GPIO_xferAck_i), + .I1(bus2ip_rnw), + .O(ip2bus_rdack_i)); + LUT2 #( + .INIT(4'h2)) + ip2bus_wrack_i_D1_i_1 + (.I0(GPIO_xferAck_i), + .I1(bus2ip_rnw), + .O(ip2bus_wrack_i_D1_reg)); endmodule (* ORIG_REF_NAME = "address_decoder" *) module Arty_Z7_20_axi_gpio_shield_2_0_address_decoder - (\ip2bus_data_i_D1_reg[0] , - \Not_Dual.gpio_Data_Out_reg[15] , - \ip_irpt_enable_reg_reg[0] , + (\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 , + E, + \Not_Dual.gpio_OE_reg[0] , s_axi_arready, s_axi_wready, - D, - \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31] , - \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] , - \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] , - \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] , - \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] , - \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] , - \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] , - \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] , - \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] , - \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] , - \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] , - \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] , - \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] , - \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] , - \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] , GPIO_DBus_i, - E, - \Not_Dual.gpio_Data_Out_reg[0] , - \ip2bus_data_i_D1_reg[0]_0 , - intr2bus_rdack0, - irpt_rdack, - irpt_wrack, - interrupt_wrce_strb, - Read_Reg_Rst, - \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg , - intr_rd_ce_or_reduce, - \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg , - intr_wr_ce_or_reduce, - \ip_irpt_enable_reg_reg[0]_0 , - ipif_glbl_irpt_enable_reg_reg, - start2, + \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] , + \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] , + \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] , + \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] , + \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] , + \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] , + \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] , + \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] , + \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] , + \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] , + \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] , + \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] , + \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] , + \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] , + \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31] , + D, + \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[16] , s_axi_aclk, - s_axi_aresetn, + rst_reg, + bus2ip_rnw_i_reg, Q, - is_read, ip2bus_rdack_i_D1, - is_write_reg, + is_read, + \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] , ip2bus_wrack_i_D1, - s_axi_wdata, - \bus2ip_addr_i_reg[8] , - gpio_io_t, + is_write_reg, \Not_Dual.gpio_Data_In_reg[0] , - bus2ip_rnw_i_reg, - bus2ip_reset, - p_0_in, - irpt_rdack_d1, - irpt_wrack_d1, - ip2bus_data, - p_3_in, - p_1_in, - GPIO_xferAck_i, + gpio_io_t, + s_axi_wdata, + start2_reg, + s_axi_aresetn, gpio_xferAck_Reg, - ip2Bus_RdAck_intr_reg_hole_d1, - ip2Bus_WrAck_intr_reg_hole_d1); - output \ip2bus_data_i_D1_reg[0] ; - output \Not_Dual.gpio_Data_Out_reg[15] ; - output \ip_irpt_enable_reg_reg[0] ; + GPIO_xferAck_i); + output \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ; + output [0:0]E; + output [0:0]\Not_Dual.gpio_OE_reg[0] ; output s_axi_arready; output s_axi_wready; - output [15:0]D; - output \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31] ; - output \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] ; - output \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] ; - output \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] ; - output \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] ; - output \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] ; - output \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] ; - output \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] ; - output \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] ; - output \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] ; - output \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] ; - output \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] ; - output \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] ; - output \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] ; - output \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] ; output [0:0]GPIO_DBus_i; - output [0:0]E; - output [0:0]\Not_Dual.gpio_Data_Out_reg[0] ; - output [1:0]\ip2bus_data_i_D1_reg[0]_0 ; - output intr2bus_rdack0; - output irpt_rdack; - output irpt_wrack; - output interrupt_wrce_strb; - output Read_Reg_Rst; - output \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ; - output intr_rd_ce_or_reduce; - output \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ; - output intr_wr_ce_or_reduce; - output \ip_irpt_enable_reg_reg[0]_0 ; - output ipif_glbl_irpt_enable_reg_reg; - input start2; + output \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] ; + output \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] ; + output \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] ; + output \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] ; + output \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] ; + output \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] ; + output \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] ; + output \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] ; + output \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] ; + output \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] ; + output \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] ; + output \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] ; + output \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] ; + output \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] ; + output \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31] ; + output [15:0]D; + output \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[16] ; input s_axi_aclk; - input s_axi_aresetn; - input [3:0]Q; - input is_read; + input rst_reg; + input bus2ip_rnw_i_reg; + input [2:0]Q; input ip2bus_rdack_i_D1; - input is_write_reg; + input is_read; + input [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ; input ip2bus_wrack_i_D1; - input [31:0]s_axi_wdata; - input [6:0]\bus2ip_addr_i_reg[8] ; - input [15:0]gpio_io_t; + input is_write_reg; input [15:0]\Not_Dual.gpio_Data_In_reg[0] ; - input bus2ip_rnw_i_reg; - input bus2ip_reset; - input [0:0]p_0_in; - input irpt_rdack_d1; - input irpt_wrack_d1; - input [0:0]ip2bus_data; - input [0:0]p_3_in; - input [0:0]p_1_in; - input GPIO_xferAck_i; + input [15:0]gpio_io_t; + input [31:0]s_axi_wdata; + input start2_reg; + input s_axi_aresetn; input gpio_xferAck_Reg; - input ip2Bus_RdAck_intr_reg_hole_d1; - input ip2Bus_WrAck_intr_reg_hole_d1; + input GPIO_xferAck_i; - wire Bus_RNW_reg_i_1_n_0; wire [15:0]D; wire [0:0]E; - wire \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0 ; - wire \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 ; - wire \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0 ; - wire \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ; - wire \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19] ; - wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ; wire [0:0]GPIO_DBus_i; wire GPIO_xferAck_i; - wire \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ; - wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ; - wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ; - wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ; - wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ; + wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ; + wire \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ; + wire \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ; + wire \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[16] ; wire \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] ; wire \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] ; wire \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] ; @@ -1015,842 +829,380 @@ module Arty_Z7_20_axi_gpio_shield_2_0_address_decoder wire \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] ; wire \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] ; wire [15:0]\Not_Dual.gpio_Data_In_reg[0] ; - wire [0:0]\Not_Dual.gpio_Data_Out_reg[0] ; - wire \Not_Dual.gpio_Data_Out_reg[15] ; - wire [3:0]Q; - wire Read_Reg_Rst; - wire [6:0]\bus2ip_addr_i_reg[8] ; - wire bus2ip_reset; + wire [0:0]\Not_Dual.gpio_OE_reg[0] ; + wire [2:0]Q; wire bus2ip_rnw_i_reg; wire [15:0]gpio_io_t; wire gpio_xferAck_Reg; - wire interrupt_wrce_strb; - wire intr2bus_rdack0; - wire intr_rd_ce_or_reduce; - wire intr_wr_ce_or_reduce; - wire ip2Bus_RdAck_intr_reg_hole_d1; - wire ip2Bus_WrAck_intr_reg_hole_d1; - wire [0:0]ip2bus_data; - wire \ip2bus_data_i_D1_reg[0] ; - wire [1:0]\ip2bus_data_i_D1_reg[0]_0 ; wire ip2bus_rdack_i_D1; wire ip2bus_wrack_i_D1; - wire \ip_irpt_enable_reg_reg[0] ; - wire \ip_irpt_enable_reg_reg[0]_0 ; - wire ipif_glbl_irpt_enable_reg_reg; - wire irpt_rdack; - wire irpt_rdack_d1; - wire irpt_wrack; - wire irpt_wrack_d1; wire is_read; wire is_write_reg; - wire [0:0]p_0_in; - wire p_10_in; - wire p_10_out; - wire p_11_in; - wire p_11_out; - wire p_12_in; - wire p_12_out; - wire p_13_in; - wire p_13_out; - wire p_14_in; - wire p_14_out; - wire p_15_in; - wire p_15_out; - wire p_16_in; - wire [0:0]p_1_in; - wire p_2_in; - wire [0:0]p_3_in; - wire p_3_in_0; - wire p_4_in; - wire p_4_out; - wire p_5_in; - wire p_5_out; - wire p_6_in; - wire p_6_out; - wire p_7_in; - wire p_7_out; - wire p_8_out; - wire p_9_in; - wire p_9_out; - wire pselect_hit_i_1; + wire rst_reg; wire s_axi_aclk; wire s_axi_aresetn; wire s_axi_arready; wire [31:0]s_axi_wdata; wire s_axi_wready; - wire start2; + wire start2_reg; - LUT3 #( - .INIT(8'hB8)) - Bus_RNW_reg_i_1 - (.I0(bus2ip_rnw_i_reg), - .I1(start2), - .I2(\ip_irpt_enable_reg_reg[0] ), - .O(Bus_RNW_reg_i_1_n_0)); - FDRE Bus_RNW_reg_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(Bus_RNW_reg_i_1_n_0), - .Q(\ip_irpt_enable_reg_reg[0] ), - .R(1'b0)); - LUT6 #( - .INIT(64'h0040000000000000)) - \GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1 - (.I0(\bus2ip_addr_i_reg[8] [3]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\bus2ip_addr_i_reg[8] [2]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(p_9_out)); - FDRE \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10] - (.C(s_axi_aclk), - .CE(start2), - .D(p_9_out), - .Q(p_10_in), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT6 #( - .INIT(64'h4000000000000000)) - \GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1 - (.I0(\bus2ip_addr_i_reg[8] [3]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\bus2ip_addr_i_reg[8] [2]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(p_8_out)); - FDRE \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] - (.C(s_axi_aclk), - .CE(start2), - .D(p_8_out), - .Q(p_9_in), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0004000000000000)) - \GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1 - (.I0(\bus2ip_addr_i_reg[8] [1]), - .I1(\bus2ip_addr_i_reg[8] [3]), - .I2(\bus2ip_addr_i_reg[8] [2]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(p_7_out)); - FDRE \GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12] - (.C(s_axi_aclk), - .CE(start2), - .D(p_7_out), - .Q(\ip2bus_data_i_D1_reg[0] ), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0400000000000000)) - \GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1 - (.I0(\bus2ip_addr_i_reg[8] [1]), - .I1(\bus2ip_addr_i_reg[8] [3]), - .I2(\bus2ip_addr_i_reg[8] [2]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(p_6_out)); - FDRE \GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13] - (.C(s_axi_aclk), - .CE(start2), - .D(p_6_out), - .Q(p_7_in), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0008000000000000)) - \GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1 - (.I0(\bus2ip_addr_i_reg[8] [1]), - .I1(\bus2ip_addr_i_reg[8] [3]), - .I2(\bus2ip_addr_i_reg[8] [2]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(p_5_out)); - FDRE \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] - (.C(s_axi_aclk), - .CE(start2), - .D(p_5_out), - .Q(p_6_in), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0800000000000000)) - \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1 - (.I0(\bus2ip_addr_i_reg[8] [1]), - .I1(\bus2ip_addr_i_reg[8] [3]), - .I2(\bus2ip_addr_i_reg[8] [2]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(p_4_out)); - FDRE \GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15] - (.C(s_axi_aclk), - .CE(start2), - .D(p_4_out), - .Q(p_5_in), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0008000000000000)) - \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1 - (.I0(\bus2ip_addr_i_reg[8] [3]), - .I1(\bus2ip_addr_i_reg[8] [2]), - .I2(\bus2ip_addr_i_reg[8] [1]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0 )); - FDRE \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16] - (.C(s_axi_aclk), - .CE(start2), - .D(\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0 ), - .Q(p_4_in), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0800000000000000)) - \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1 - (.I0(\bus2ip_addr_i_reg[8] [3]), - .I1(\bus2ip_addr_i_reg[8] [2]), - .I2(\bus2ip_addr_i_reg[8] [1]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 )); - FDRE \GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17] - (.C(s_axi_aclk), - .CE(start2), - .D(\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 ), - .Q(p_3_in_0), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0080000000000000)) - \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1 - (.I0(\bus2ip_addr_i_reg[8] [3]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\bus2ip_addr_i_reg[8] [2]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0 )); - FDRE \GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18] - (.C(s_axi_aclk), - .CE(start2), - .D(\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0 ), - .Q(p_2_in), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT3 #( - .INIT(8'hFD)) - \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1 - (.I0(s_axi_aresetn), - .I1(s_axi_arready), - .I2(s_axi_wready), - .O(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT6 #( - .INIT(64'h8000000000000000)) - \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_2 - (.I0(\bus2ip_addr_i_reg[8] [3]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\bus2ip_addr_i_reg[8] [2]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(p_15_out)); - FDRE \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg[19] - (.C(s_axi_aclk), - .CE(start2), - .D(p_15_out), - .Q(\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19] ), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0001000000000000)) - \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1 - (.I0(\bus2ip_addr_i_reg[8] [1]), - .I1(\bus2ip_addr_i_reg[8] [2]), - .I2(\bus2ip_addr_i_reg[8] [3]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 )); - FDRE \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] - (.C(s_axi_aclk), - .CE(start2), - .D(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ), - .Q(p_16_in), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0100000000000000)) - \GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1 - (.I0(\bus2ip_addr_i_reg[8] [1]), - .I1(\bus2ip_addr_i_reg[8] [2]), - .I2(\bus2ip_addr_i_reg[8] [3]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(p_14_out)); - FDRE \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] - (.C(s_axi_aclk), - .CE(start2), - .D(p_14_out), - .Q(p_15_in), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0002000000000000)) - \GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1 - (.I0(\bus2ip_addr_i_reg[8] [1]), - .I1(\bus2ip_addr_i_reg[8] [2]), - .I2(\bus2ip_addr_i_reg[8] [3]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(p_13_out)); - FDRE \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] - (.C(s_axi_aclk), - .CE(start2), - .D(p_13_out), - .Q(p_14_in), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0200000000000000)) - \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1 - (.I0(\bus2ip_addr_i_reg[8] [1]), - .I1(\bus2ip_addr_i_reg[8] [2]), - .I2(\bus2ip_addr_i_reg[8] [3]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(p_12_out)); - FDRE \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] - (.C(s_axi_aclk), - .CE(start2), - .D(p_12_out), - .Q(p_13_in), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0004000000000000)) - \GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1 - (.I0(\bus2ip_addr_i_reg[8] [3]), - .I1(\bus2ip_addr_i_reg[8] [2]), - .I2(\bus2ip_addr_i_reg[8] [1]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(p_11_out)); - FDRE \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8] - (.C(s_axi_aclk), - .CE(start2), - .D(p_11_out), - .Q(p_12_in), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0400000000000000)) - \GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1 - (.I0(\bus2ip_addr_i_reg[8] [3]), - .I1(\bus2ip_addr_i_reg[8] [2]), - .I2(\bus2ip_addr_i_reg[8] [1]), - .I3(\bus2ip_addr_i_reg[8] [0]), - .I4(\bus2ip_addr_i_reg[8] [6]), - .I5(start2), - .O(p_10_out)); - FDRE \GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9] - (.C(s_axi_aclk), - .CE(start2), - .D(p_10_out), - .Q(p_11_in), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair0" *) - LUT4 #( - .INIT(16'hFE00)) - \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_i_1 - (.I0(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ), - .I1(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ), - .I2(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ), - .I3(\ip_irpt_enable_reg_reg[0] ), - .O(intr_rd_ce_or_reduce)); - (* SOFT_HLUTNM = "soft_lutpair1" *) - LUT5 #( - .INIT(32'h00FE0000)) - \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_i_1 - (.I0(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ), - .I1(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ), - .I2(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ), - .I3(ip2Bus_RdAck_intr_reg_hole_d1), - .I4(\ip_irpt_enable_reg_reg[0] ), - .O(\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg )); - (* SOFT_HLUTNM = "soft_lutpair1" *) - LUT4 #( - .INIT(16'h00FE)) - \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_1 - (.I0(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ), - .I1(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ), - .I2(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ), - .I3(\ip_irpt_enable_reg_reg[0] ), - .O(intr_wr_ce_or_reduce)); - LUT5 #( - .INIT(32'hFFFFFFFE)) - \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2 - (.I0(p_16_in), - .I1(p_2_in), - .I2(\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19] ), - .I3(p_14_in), - .I4(p_15_in), - .O(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 )); - LUT4 #( - .INIT(16'hFFFE)) - \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3 - (.I0(p_12_in), - .I1(p_13_in), - .I2(p_10_in), - .I3(p_11_in), - .O(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 )); - LUT4 #( - .INIT(16'hFFFE)) - \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4 - (.I0(p_5_in), - .I1(p_7_in), - .I2(p_3_in_0), - .I3(p_4_in), - .O(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair0" *) LUT5 #( - .INIT(32'h000000FE)) - \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_1 - (.I0(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ), - .I1(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ), - .I2(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ), - .I3(\ip_irpt_enable_reg_reg[0] ), - .I4(ip2Bus_WrAck_intr_reg_hole_d1), - .O(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg )); - LUT6 #( - .INIT(64'h0000000000000002)) + .INIT(32'h000000E0)) \MEM_DECODE_GEN[0].cs_out_i[0]_i_1 - (.I0(start2), - .I1(\bus2ip_addr_i_reg[8] [6]), - .I2(\bus2ip_addr_i_reg[8] [4]), - .I3(\bus2ip_addr_i_reg[8] [5]), - .I4(\bus2ip_addr_i_reg[8] [3]), - .I5(\bus2ip_addr_i_reg[8] [2]), - .O(pselect_hit_i_1)); + (.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I1(start2_reg), + .I2(s_axi_aresetn), + .I3(s_axi_arready), + .I4(s_axi_wready), + .O(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 )); FDRE \MEM_DECODE_GEN[0].cs_out_i_reg[0] (.C(s_axi_aclk), - .CE(start2), - .D(pselect_hit_i_1), - .Q(\Not_Dual.gpio_Data_Out_reg[15] ), - .R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 )); + .CE(1'b1), + .D(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ), + .Q(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .R(1'b0)); LUT6 #( - .INIT(64'h000A0000000C0000)) + .INIT(64'h000000E000000020)) \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i[16]_i_1 - (.I0(gpio_io_t[15]), - .I1(\Not_Dual.gpio_Data_In_reg[0] [15]), - .I2(\bus2ip_addr_i_reg[8] [6]), - .I3(\bus2ip_addr_i_reg[8] [1]), - .I4(\Not_Dual.gpio_Data_Out_reg[15] ), - .I5(\bus2ip_addr_i_reg[8] [0]), + (.I0(\Not_Dual.gpio_Data_In_reg[0] [15]), + .I1(Q[0]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[1]), + .I5(gpio_io_t[15]), .O(GPIO_DBus_i)); LUT6 #( - .INIT(64'h000A0000000C0000)) + .INIT(64'h000000E000000020)) \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i[26]_i_1 - (.I0(gpio_io_t[5]), - .I1(\Not_Dual.gpio_Data_In_reg[0] [5]), - .I2(\bus2ip_addr_i_reg[8] [6]), - .I3(\bus2ip_addr_i_reg[8] [1]), - .I4(\Not_Dual.gpio_Data_Out_reg[15] ), - .I5(\bus2ip_addr_i_reg[8] [0]), + (.I0(\Not_Dual.gpio_Data_In_reg[0] [5]), + .I1(Q[0]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[1]), + .I5(gpio_io_t[5]), .O(\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] )); LUT6 #( - .INIT(64'h000A0000000C0000)) + .INIT(64'h000000E000000020)) \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i[27]_i_1 - (.I0(gpio_io_t[4]), - .I1(\Not_Dual.gpio_Data_In_reg[0] [4]), - .I2(\bus2ip_addr_i_reg[8] [6]), - .I3(\bus2ip_addr_i_reg[8] [1]), - .I4(\Not_Dual.gpio_Data_Out_reg[15] ), - .I5(\bus2ip_addr_i_reg[8] [0]), + (.I0(\Not_Dual.gpio_Data_In_reg[0] [4]), + .I1(Q[0]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[1]), + .I5(gpio_io_t[4]), .O(\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] )); LUT6 #( - .INIT(64'h000A0000000C0000)) + .INIT(64'h000000E000000020)) \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i[28]_i_1 - (.I0(gpio_io_t[3]), - .I1(\Not_Dual.gpio_Data_In_reg[0] [3]), - .I2(\bus2ip_addr_i_reg[8] [6]), - .I3(\bus2ip_addr_i_reg[8] [1]), - .I4(\Not_Dual.gpio_Data_Out_reg[15] ), - .I5(\bus2ip_addr_i_reg[8] [0]), + (.I0(\Not_Dual.gpio_Data_In_reg[0] [3]), + .I1(Q[0]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[1]), + .I5(gpio_io_t[3]), .O(\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] )); LUT6 #( - .INIT(64'h000A0000000C0000)) + .INIT(64'h000000E000000020)) \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i[29]_i_1 - (.I0(gpio_io_t[2]), - .I1(\Not_Dual.gpio_Data_In_reg[0] [2]), - .I2(\bus2ip_addr_i_reg[8] [6]), - .I3(\bus2ip_addr_i_reg[8] [1]), - .I4(\Not_Dual.gpio_Data_Out_reg[15] ), - .I5(\bus2ip_addr_i_reg[8] [0]), + (.I0(\Not_Dual.gpio_Data_In_reg[0] [2]), + .I1(Q[0]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[1]), + .I5(gpio_io_t[2]), .O(\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] )); LUT6 #( - .INIT(64'h000A0000000C0000)) + .INIT(64'h000000E000000020)) \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i[30]_i_1 - (.I0(gpio_io_t[1]), - .I1(\Not_Dual.gpio_Data_In_reg[0] [1]), - .I2(\bus2ip_addr_i_reg[8] [6]), - .I3(\bus2ip_addr_i_reg[8] [1]), - .I4(\Not_Dual.gpio_Data_Out_reg[15] ), - .I5(\bus2ip_addr_i_reg[8] [0]), + (.I0(\Not_Dual.gpio_Data_In_reg[0] [1]), + .I1(Q[0]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[1]), + .I5(gpio_io_t[1]), .O(\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] )); LUT4 #( - .INIT(16'hFFDF)) + .INIT(16'hFFF7)) \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i[31]_i_1 - (.I0(\Not_Dual.gpio_Data_Out_reg[15] ), - .I1(GPIO_xferAck_i), - .I2(bus2ip_rnw_i_reg), - .I3(gpio_xferAck_Reg), - .O(Read_Reg_Rst)); + (.I0(bus2ip_rnw_i_reg), + .I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I2(gpio_xferAck_Reg), + .I3(GPIO_xferAck_i), + .O(\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[16] )); LUT6 #( - .INIT(64'h000A0000000C0000)) + .INIT(64'h000000E000000020)) \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i[31]_i_2 - (.I0(gpio_io_t[0]), - .I1(\Not_Dual.gpio_Data_In_reg[0] [0]), - .I2(\bus2ip_addr_i_reg[8] [6]), - .I3(\bus2ip_addr_i_reg[8] [1]), - .I4(\Not_Dual.gpio_Data_Out_reg[15] ), - .I5(\bus2ip_addr_i_reg[8] [0]), + (.I0(\Not_Dual.gpio_Data_In_reg[0] [0]), + .I1(Q[0]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[1]), + .I5(gpio_io_t[0]), .O(\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31] )); LUT6 #( - .INIT(64'h000A0000000C0000)) + .INIT(64'h000000E000000020)) \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i[17]_i_1 - (.I0(gpio_io_t[14]), - .I1(\Not_Dual.gpio_Data_In_reg[0] [14]), - .I2(\bus2ip_addr_i_reg[8] [6]), - .I3(\bus2ip_addr_i_reg[8] [1]), - .I4(\Not_Dual.gpio_Data_Out_reg[15] ), - .I5(\bus2ip_addr_i_reg[8] [0]), + (.I0(\Not_Dual.gpio_Data_In_reg[0] [14]), + .I1(Q[0]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[1]), + .I5(gpio_io_t[14]), .O(\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] )); LUT6 #( - .INIT(64'h000A0000000C0000)) + .INIT(64'h000000E000000020)) \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i[18]_i_1 - (.I0(gpio_io_t[13]), - .I1(\Not_Dual.gpio_Data_In_reg[0] [13]), - .I2(\bus2ip_addr_i_reg[8] [6]), - .I3(\bus2ip_addr_i_reg[8] [1]), - .I4(\Not_Dual.gpio_Data_Out_reg[15] ), - .I5(\bus2ip_addr_i_reg[8] [0]), + (.I0(\Not_Dual.gpio_Data_In_reg[0] [13]), + .I1(Q[0]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[1]), + .I5(gpio_io_t[13]), .O(\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] )); LUT6 #( - .INIT(64'h000A0000000C0000)) + .INIT(64'h000000E000000020)) \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i[19]_i_1 - (.I0(gpio_io_t[12]), - .I1(\Not_Dual.gpio_Data_In_reg[0] [12]), - .I2(\bus2ip_addr_i_reg[8] [6]), - .I3(\bus2ip_addr_i_reg[8] [1]), - .I4(\Not_Dual.gpio_Data_Out_reg[15] ), - .I5(\bus2ip_addr_i_reg[8] [0]), + (.I0(\Not_Dual.gpio_Data_In_reg[0] [12]), + .I1(Q[0]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[1]), + .I5(gpio_io_t[12]), .O(\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] )); LUT6 #( - .INIT(64'h000A0000000C0000)) + .INIT(64'h000000E000000020)) \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i[20]_i_1 - (.I0(gpio_io_t[11]), - .I1(\Not_Dual.gpio_Data_In_reg[0] [11]), - .I2(\bus2ip_addr_i_reg[8] [6]), - .I3(\bus2ip_addr_i_reg[8] [1]), - .I4(\Not_Dual.gpio_Data_Out_reg[15] ), - .I5(\bus2ip_addr_i_reg[8] [0]), + (.I0(\Not_Dual.gpio_Data_In_reg[0] [11]), + .I1(Q[0]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[1]), + .I5(gpio_io_t[11]), .O(\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] )); LUT6 #( - .INIT(64'h000A0000000C0000)) + .INIT(64'h000000E000000020)) \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i[21]_i_1 - (.I0(gpio_io_t[10]), - .I1(\Not_Dual.gpio_Data_In_reg[0] [10]), - .I2(\bus2ip_addr_i_reg[8] [6]), - .I3(\bus2ip_addr_i_reg[8] [1]), - .I4(\Not_Dual.gpio_Data_Out_reg[15] ), - .I5(\bus2ip_addr_i_reg[8] [0]), + (.I0(\Not_Dual.gpio_Data_In_reg[0] [10]), + .I1(Q[0]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[1]), + .I5(gpio_io_t[10]), .O(\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] )); LUT6 #( - .INIT(64'h000A0000000C0000)) + .INIT(64'h000000E000000020)) \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i[22]_i_1 - (.I0(gpio_io_t[9]), - .I1(\Not_Dual.gpio_Data_In_reg[0] [9]), - .I2(\bus2ip_addr_i_reg[8] [6]), - .I3(\bus2ip_addr_i_reg[8] [1]), - .I4(\Not_Dual.gpio_Data_Out_reg[15] ), - .I5(\bus2ip_addr_i_reg[8] [0]), + (.I0(\Not_Dual.gpio_Data_In_reg[0] [9]), + .I1(Q[0]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[1]), + .I5(gpio_io_t[9]), .O(\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] )); LUT6 #( - .INIT(64'h000A0000000C0000)) + .INIT(64'h000000E000000020)) \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i[23]_i_1 - (.I0(gpio_io_t[8]), - .I1(\Not_Dual.gpio_Data_In_reg[0] [8]), - .I2(\bus2ip_addr_i_reg[8] [6]), - .I3(\bus2ip_addr_i_reg[8] [1]), - .I4(\Not_Dual.gpio_Data_Out_reg[15] ), - .I5(\bus2ip_addr_i_reg[8] [0]), + (.I0(\Not_Dual.gpio_Data_In_reg[0] [8]), + .I1(Q[0]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[1]), + .I5(gpio_io_t[8]), .O(\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] )); LUT6 #( - .INIT(64'h000A0000000C0000)) + .INIT(64'h000000E000000020)) \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i[24]_i_1 - (.I0(gpio_io_t[7]), - .I1(\Not_Dual.gpio_Data_In_reg[0] [7]), - .I2(\bus2ip_addr_i_reg[8] [6]), - .I3(\bus2ip_addr_i_reg[8] [1]), - .I4(\Not_Dual.gpio_Data_Out_reg[15] ), - .I5(\bus2ip_addr_i_reg[8] [0]), + (.I0(\Not_Dual.gpio_Data_In_reg[0] [7]), + .I1(Q[0]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[1]), + .I5(gpio_io_t[7]), .O(\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] )); LUT6 #( - .INIT(64'h000A0000000C0000)) + .INIT(64'h000000E000000020)) \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i[25]_i_1 - (.I0(gpio_io_t[6]), - .I1(\Not_Dual.gpio_Data_In_reg[0] [6]), - .I2(\bus2ip_addr_i_reg[8] [6]), - .I3(\bus2ip_addr_i_reg[8] [1]), - .I4(\Not_Dual.gpio_Data_Out_reg[15] ), - .I5(\bus2ip_addr_i_reg[8] [0]), + (.I0(\Not_Dual.gpio_Data_In_reg[0] [6]), + .I1(Q[0]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[1]), + .I5(gpio_io_t[6]), .O(\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] )); LUT6 #( - .INIT(64'hFFFFFFFF00000100)) + .INIT(64'hAAAAAAAAAAAAABAA)) \Not_Dual.gpio_Data_Out[0]_i_1 - (.I0(bus2ip_rnw_i_reg), - .I1(\bus2ip_addr_i_reg[8] [6]), - .I2(\bus2ip_addr_i_reg[8] [1]), - .I3(\Not_Dual.gpio_Data_Out_reg[15] ), - .I4(\bus2ip_addr_i_reg[8] [0]), - .I5(bus2ip_reset), - .O(\Not_Dual.gpio_Data_Out_reg[0] )); + (.I0(rst_reg), + .I1(bus2ip_rnw_i_reg), + .I2(Q[0]), + .I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I4(Q[2]), + .I5(Q[1]), + .O(E)); LUT4 #( - .INIT(16'hBA8A)) + .INIT(16'hCCAC)) \Not_Dual.gpio_Data_Out[0]_i_2 - (.I0(s_axi_wdata[31]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\Not_Dual.gpio_Data_Out_reg[15] ), - .I3(s_axi_wdata[15]), + (.I0(s_axi_wdata[15]), + .I1(s_axi_wdata[31]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[1]), .O(D[15])); LUT4 #( - .INIT(16'hBA8A)) + .INIT(16'hCCAC)) \Not_Dual.gpio_Data_Out[10]_i_1 - (.I0(s_axi_wdata[21]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\Not_Dual.gpio_Data_Out_reg[15] ), - .I3(s_axi_wdata[5]), + (.I0(s_axi_wdata[5]), + .I1(s_axi_wdata[21]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[1]), .O(D[5])); LUT4 #( - .INIT(16'hBA8A)) + .INIT(16'hCCAC)) \Not_Dual.gpio_Data_Out[11]_i_1 - (.I0(s_axi_wdata[20]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\Not_Dual.gpio_Data_Out_reg[15] ), - .I3(s_axi_wdata[4]), + (.I0(s_axi_wdata[4]), + .I1(s_axi_wdata[20]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[1]), .O(D[4])); LUT4 #( - .INIT(16'hBA8A)) + .INIT(16'hCCAC)) \Not_Dual.gpio_Data_Out[12]_i_1 - (.I0(s_axi_wdata[19]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\Not_Dual.gpio_Data_Out_reg[15] ), - .I3(s_axi_wdata[3]), + (.I0(s_axi_wdata[3]), + .I1(s_axi_wdata[19]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[1]), .O(D[3])); LUT4 #( - .INIT(16'hBA8A)) + .INIT(16'hCCAC)) \Not_Dual.gpio_Data_Out[13]_i_1 - (.I0(s_axi_wdata[18]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\Not_Dual.gpio_Data_Out_reg[15] ), - .I3(s_axi_wdata[2]), + (.I0(s_axi_wdata[2]), + .I1(s_axi_wdata[18]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[1]), .O(D[2])); LUT4 #( - .INIT(16'hBA8A)) + .INIT(16'hCCAC)) \Not_Dual.gpio_Data_Out[14]_i_1 - (.I0(s_axi_wdata[17]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\Not_Dual.gpio_Data_Out_reg[15] ), - .I3(s_axi_wdata[1]), + (.I0(s_axi_wdata[1]), + .I1(s_axi_wdata[17]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[1]), .O(D[1])); LUT4 #( - .INIT(16'hBA8A)) + .INIT(16'hCCAC)) \Not_Dual.gpio_Data_Out[15]_i_1 - (.I0(s_axi_wdata[16]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\Not_Dual.gpio_Data_Out_reg[15] ), - .I3(s_axi_wdata[0]), + (.I0(s_axi_wdata[0]), + .I1(s_axi_wdata[16]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[1]), .O(D[0])); LUT4 #( - .INIT(16'hBA8A)) + .INIT(16'hCCAC)) \Not_Dual.gpio_Data_Out[1]_i_1 - (.I0(s_axi_wdata[30]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\Not_Dual.gpio_Data_Out_reg[15] ), - .I3(s_axi_wdata[14]), + (.I0(s_axi_wdata[14]), + .I1(s_axi_wdata[30]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[1]), .O(D[14])); LUT4 #( - .INIT(16'hBA8A)) + .INIT(16'hCCAC)) \Not_Dual.gpio_Data_Out[2]_i_1 - (.I0(s_axi_wdata[29]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\Not_Dual.gpio_Data_Out_reg[15] ), - .I3(s_axi_wdata[13]), + (.I0(s_axi_wdata[13]), + .I1(s_axi_wdata[29]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[1]), .O(D[13])); LUT4 #( - .INIT(16'hBA8A)) + .INIT(16'hCCAC)) \Not_Dual.gpio_Data_Out[3]_i_1 - (.I0(s_axi_wdata[28]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\Not_Dual.gpio_Data_Out_reg[15] ), - .I3(s_axi_wdata[12]), + (.I0(s_axi_wdata[12]), + .I1(s_axi_wdata[28]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[1]), .O(D[12])); LUT4 #( - .INIT(16'hBA8A)) + .INIT(16'hCCAC)) \Not_Dual.gpio_Data_Out[4]_i_1 - (.I0(s_axi_wdata[27]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\Not_Dual.gpio_Data_Out_reg[15] ), - .I3(s_axi_wdata[11]), + (.I0(s_axi_wdata[11]), + .I1(s_axi_wdata[27]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[1]), .O(D[11])); LUT4 #( - .INIT(16'hBA8A)) + .INIT(16'hCCAC)) \Not_Dual.gpio_Data_Out[5]_i_1 - (.I0(s_axi_wdata[26]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\Not_Dual.gpio_Data_Out_reg[15] ), - .I3(s_axi_wdata[10]), + (.I0(s_axi_wdata[10]), + .I1(s_axi_wdata[26]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[1]), .O(D[10])); LUT4 #( - .INIT(16'hBA8A)) + .INIT(16'hCCAC)) \Not_Dual.gpio_Data_Out[6]_i_1 - (.I0(s_axi_wdata[25]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\Not_Dual.gpio_Data_Out_reg[15] ), - .I3(s_axi_wdata[9]), + (.I0(s_axi_wdata[9]), + .I1(s_axi_wdata[25]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[1]), .O(D[9])); LUT4 #( - .INIT(16'hBA8A)) + .INIT(16'hCCAC)) \Not_Dual.gpio_Data_Out[7]_i_1 - (.I0(s_axi_wdata[24]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\Not_Dual.gpio_Data_Out_reg[15] ), - .I3(s_axi_wdata[8]), + (.I0(s_axi_wdata[8]), + .I1(s_axi_wdata[24]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[1]), .O(D[8])); LUT4 #( - .INIT(16'hBA8A)) + .INIT(16'hCCAC)) \Not_Dual.gpio_Data_Out[8]_i_1 - (.I0(s_axi_wdata[23]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\Not_Dual.gpio_Data_Out_reg[15] ), - .I3(s_axi_wdata[7]), + (.I0(s_axi_wdata[7]), + .I1(s_axi_wdata[23]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[1]), .O(D[7])); LUT4 #( - .INIT(16'hBA8A)) + .INIT(16'hCCAC)) \Not_Dual.gpio_Data_Out[9]_i_1 - (.I0(s_axi_wdata[22]), - .I1(\bus2ip_addr_i_reg[8] [1]), - .I2(\Not_Dual.gpio_Data_Out_reg[15] ), - .I3(s_axi_wdata[6]), + (.I0(s_axi_wdata[6]), + .I1(s_axi_wdata[22]), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[1]), .O(D[6])); LUT6 #( - .INIT(64'hFFFFFFFF01000000)) + .INIT(64'hAAAAAAAAAABAAAAA)) \Not_Dual.gpio_OE[0]_i_1 - (.I0(bus2ip_rnw_i_reg), - .I1(\bus2ip_addr_i_reg[8] [6]), - .I2(\bus2ip_addr_i_reg[8] [1]), - .I3(\Not_Dual.gpio_Data_Out_reg[15] ), - .I4(\bus2ip_addr_i_reg[8] [0]), - .I5(bus2ip_reset), - .O(E)); - LUT5 #( - .INIT(32'h44444440)) - intr2bus_rdack_i_1 - (.I0(irpt_rdack_d1), - .I1(\ip_irpt_enable_reg_reg[0] ), - .I2(p_9_in), - .I3(\ip2bus_data_i_D1_reg[0] ), - .I4(p_6_in), - .O(intr2bus_rdack0)); - (* SOFT_HLUTNM = "soft_lutpair2" *) - LUT5 #( - .INIT(32'h000000FE)) - intr2bus_wrack_i_1 - (.I0(p_9_in), - .I1(\ip2bus_data_i_D1_reg[0] ), - .I2(p_6_in), - .I3(\ip_irpt_enable_reg_reg[0] ), - .I4(irpt_wrack_d1), - .O(interrupt_wrce_strb)); - (* SOFT_HLUTNM = "soft_lutpair3" *) - LUT5 #( - .INIT(32'h00000080)) - \ip2bus_data_i_D1[0]_i_1 - (.I0(p_0_in), - .I1(p_9_in), - .I2(\ip_irpt_enable_reg_reg[0] ), - .I3(p_6_in), - .I4(\ip2bus_data_i_D1_reg[0] ), - .O(\ip2bus_data_i_D1_reg[0]_0 [1])); + (.I0(rst_reg), + .I1(bus2ip_rnw_i_reg), + .I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ), + .I3(Q[2]), + .I4(Q[0]), + .I5(Q[1]), + .O(\Not_Dual.gpio_OE_reg[0] )); LUT6 #( - .INIT(64'hEEEEAAAAFAAAAAAA)) - \ip2bus_data_i_D1[31]_i_1 - (.I0(ip2bus_data), - .I1(p_3_in), - .I2(p_1_in), - .I3(p_6_in), - .I4(\ip_irpt_enable_reg_reg[0] ), - .I5(\ip2bus_data_i_D1_reg[0] ), - .O(\ip2bus_data_i_D1_reg[0]_0 [0])); - LUT4 #( - .INIT(16'hFB08)) - \ip_irpt_enable_reg[0]_i_1 - (.I0(s_axi_wdata[0]), - .I1(p_6_in), - .I2(\ip_irpt_enable_reg_reg[0] ), - .I3(p_1_in), - .O(\ip_irpt_enable_reg_reg[0]_0 )); - LUT4 #( - .INIT(16'hFB08)) - ipif_glbl_irpt_enable_reg_i_1 - (.I0(s_axi_wdata[31]), - .I1(p_9_in), - .I2(\ip_irpt_enable_reg_reg[0] ), - .I3(p_0_in), - .O(ipif_glbl_irpt_enable_reg_reg)); - (* SOFT_HLUTNM = "soft_lutpair2" *) - LUT4 #( - .INIT(16'hFE00)) - irpt_rdack_d1_i_1 - (.I0(p_9_in), - .I1(\ip2bus_data_i_D1_reg[0] ), - .I2(p_6_in), - .I3(\ip_irpt_enable_reg_reg[0] ), - .O(irpt_rdack)); - (* SOFT_HLUTNM = "soft_lutpair3" *) - LUT4 #( - .INIT(16'h00FE)) - irpt_wrack_d1_i_1 - (.I0(p_9_in), - .I1(\ip2bus_data_i_D1_reg[0] ), - .I2(p_6_in), - .I3(\ip_irpt_enable_reg_reg[0] ), - .O(irpt_wrack)); - LUT6 #( - .INIT(64'hFFFFFFFF00020000)) + .INIT(64'hAAAAAAAAAAAEAAAA)) s_axi_arready_INST_0 - (.I0(Q[3]), - .I1(Q[2]), - .I2(Q[1]), - .I3(Q[0]), - .I4(is_read), - .I5(ip2bus_rdack_i_D1), + (.I0(ip2bus_rdack_i_D1), + .I1(is_read), + .I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]), + .I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]), + .I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]), + .I5(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]), .O(s_axi_arready)); LUT6 #( - .INIT(64'hFFFFFFFF00020000)) + .INIT(64'hAAAAAAAAAAAEAAAA)) s_axi_wready_INST_0 - (.I0(Q[3]), - .I1(Q[2]), - .I2(Q[1]), - .I3(Q[0]), - .I4(is_write_reg), - .I5(ip2bus_wrack_i_D1), + (.I0(ip2bus_wrack_i_D1), + .I1(is_write_reg), + .I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]), + .I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]), + .I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]), + .I5(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]), .O(s_axi_wready)); endmodule (* C_ALL_INPUTS = "0" *) (* C_ALL_INPUTS_2 = "0" *) (* C_ALL_OUTPUTS = "0" *) (* C_ALL_OUTPUTS_2 = "0" *) (* C_DOUT_DEFAULT = "0" *) (* C_DOUT_DEFAULT_2 = "0" *) (* C_FAMILY = "zynq" *) (* C_GPIO2_WIDTH = "32" *) (* C_GPIO_WIDTH = "16" *) -(* C_INTERRUPT_PRESENT = "1" *) (* C_IS_DUAL = "0" *) (* C_S_AXI_ADDR_WIDTH = "9" *) +(* C_INTERRUPT_PRESENT = "0" *) (* C_IS_DUAL = "0" *) (* C_S_AXI_ADDR_WIDTH = "9" *) (* C_S_AXI_DATA_WIDTH = "32" *) (* C_TRI_DEFAULT = "-1" *) (* C_TRI_DEFAULT_2 = "-1" *) (* ORIG_REF_NAME = "axi_gpio" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_group = "LOGICORE" *) module Arty_Z7_20_axi_gpio_shield_2_0_axi_gpio @@ -1909,68 +1261,41 @@ module Arty_Z7_20_axi_gpio_shield_2_0_axi_gpio wire \ ; wire \ ; + wire AXI_LITE_IPIF_I_n_10; + wire AXI_LITE_IPIF_I_n_11; + wire AXI_LITE_IPIF_I_n_12; + wire AXI_LITE_IPIF_I_n_13; + wire AXI_LITE_IPIF_I_n_14; + wire AXI_LITE_IPIF_I_n_15; + wire AXI_LITE_IPIF_I_n_16; + wire AXI_LITE_IPIF_I_n_17; + wire AXI_LITE_IPIF_I_n_18; + wire AXI_LITE_IPIF_I_n_19; + wire AXI_LITE_IPIF_I_n_20; + wire AXI_LITE_IPIF_I_n_21; + wire AXI_LITE_IPIF_I_n_22; + wire AXI_LITE_IPIF_I_n_23; wire AXI_LITE_IPIF_I_n_24; - wire AXI_LITE_IPIF_I_n_25; - wire AXI_LITE_IPIF_I_n_26; - wire AXI_LITE_IPIF_I_n_27; - wire AXI_LITE_IPIF_I_n_28; - wire AXI_LITE_IPIF_I_n_29; - wire AXI_LITE_IPIF_I_n_30; - wire AXI_LITE_IPIF_I_n_31; - wire AXI_LITE_IPIF_I_n_32; - wire AXI_LITE_IPIF_I_n_33; - wire AXI_LITE_IPIF_I_n_34; - wire AXI_LITE_IPIF_I_n_35; - wire AXI_LITE_IPIF_I_n_36; - wire AXI_LITE_IPIF_I_n_37; - wire AXI_LITE_IPIF_I_n_38; - wire AXI_LITE_IPIF_I_n_40; wire AXI_LITE_IPIF_I_n_41; - wire AXI_LITE_IPIF_I_n_49; - wire AXI_LITE_IPIF_I_n_51; - wire AXI_LITE_IPIF_I_n_53; - wire AXI_LITE_IPIF_I_n_54; + wire AXI_LITE_IPIF_I_n_6; + wire AXI_LITE_IPIF_I_n_7; wire [0:15]DBus_Reg; wire [16:16]GPIO_DBus_i; - wire GPIO_intr; wire GPIO_xferAck_i; - wire IP2INTC_Irpt_i; - wire \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ; - wire \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in ; - wire Read_Reg_Rst; - wire [1:1]bus2ip_cs; + wire bus2ip_cs; wire bus2ip_reset; - wire bus2ip_reset_i_1_n_0; wire bus2ip_rnw; wire [0:15]gpio_Data_In; + wire gpio_core_1_n_19; wire [15:0]gpio_io_i; wire [15:0]gpio_io_o; wire [15:0]gpio_io_t; wire gpio_xferAck_Reg; - wire interrupt_wrce_strb; - wire intr2bus_rdack0; - wire intr_rd_ce_or_reduce; - wire intr_wr_ce_or_reduce; - wire ip2Bus_RdAck_intr_reg_hole; - wire ip2Bus_RdAck_intr_reg_hole_d1; - wire ip2Bus_WrAck_intr_reg_hole; - wire ip2Bus_WrAck_intr_reg_hole_d1; wire [16:31]ip2bus_data; - wire [31:31]ip2bus_data_i; - wire [0:31]ip2bus_data_i_D1; + wire [16:31]ip2bus_data_i_D1; wire ip2bus_rdack_i; wire ip2bus_rdack_i_D1; - wire ip2bus_wrack_i; wire ip2bus_wrack_i_D1; - wire ip2intc_irpt; - wire irpt_rdack; - wire irpt_rdack_d1; - wire irpt_wrack; - wire irpt_wrack_d1; - wire [31:31]p_0_in; - wire [0:0]p_0_out; - wire [0:0]p_1_in; - wire [0:0]p_3_in; (* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Clk" *) wire s_axi_aclk; wire [8:0]s_axi_araddr; (* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Rst" *) wire s_axi_aresetn; @@ -1980,7 +1305,7 @@ module Arty_Z7_20_axi_gpio_shield_2_0_axi_gpio wire s_axi_awvalid; wire s_axi_bready; wire s_axi_bvalid; - wire [31:0]\^s_axi_rdata ; + wire [15:0]\^s_axi_rdata ; wire s_axi_rready; wire s_axi_rvalid; wire [31:0]s_axi_wdata; @@ -2051,10 +1376,11 @@ module Arty_Z7_20_axi_gpio_shield_2_0_axi_gpio assign gpio2_io_t[2] = \ ; assign gpio2_io_t[1] = \ ; assign gpio2_io_t[0] = \ ; + assign ip2intc_irpt = \ ; assign s_axi_awready = s_axi_wready; assign s_axi_bresp[1] = \ ; assign s_axi_bresp[0] = \ ; - assign s_axi_rdata[31] = \^s_axi_rdata [31]; + assign s_axi_rdata[31] = \ ; assign s_axi_rdata[30] = \ ; assign s_axi_rdata[29] = \ ; assign s_axi_rdata[28] = \ ; @@ -2074,67 +1400,46 @@ module Arty_Z7_20_axi_gpio_shield_2_0_axi_gpio assign s_axi_rresp[1] = \ ; assign s_axi_rresp[0] = \ ; Arty_Z7_20_axi_gpio_shield_2_0_axi_lite_ipif AXI_LITE_IPIF_I - (.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ), - .D({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3],DBus_Reg[4],DBus_Reg[5],DBus_Reg[6],DBus_Reg[7],DBus_Reg[8],DBus_Reg[9],DBus_Reg[10],DBus_Reg[11],DBus_Reg[12],DBus_Reg[13],DBus_Reg[14],DBus_Reg[15]}), - .E(AXI_LITE_IPIF_I_n_40), + (.D({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3],DBus_Reg[4],DBus_Reg[5],DBus_Reg[6],DBus_Reg[7],DBus_Reg[8],DBus_Reg[9],DBus_Reg[10],DBus_Reg[11],DBus_Reg[12],DBus_Reg[13],DBus_Reg[14],DBus_Reg[15]}), + .E(AXI_LITE_IPIF_I_n_6), .GPIO_DBus_i(GPIO_DBus_i), .GPIO_xferAck_i(GPIO_xferAck_i), - .\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg (AXI_LITE_IPIF_I_n_49), - .\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg (AXI_LITE_IPIF_I_n_51), - .\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] (AXI_LITE_IPIF_I_n_29), - .\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] (AXI_LITE_IPIF_I_n_28), - .\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] (AXI_LITE_IPIF_I_n_27), - .\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] (AXI_LITE_IPIF_I_n_26), - .\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] (AXI_LITE_IPIF_I_n_25), + .\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[16] (AXI_LITE_IPIF_I_n_41), + .\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] (AXI_LITE_IPIF_I_n_19), + .\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] (AXI_LITE_IPIF_I_n_20), + .\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] (AXI_LITE_IPIF_I_n_21), + .\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] (AXI_LITE_IPIF_I_n_22), + .\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] (AXI_LITE_IPIF_I_n_23), .\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31] (AXI_LITE_IPIF_I_n_24), - .\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] (AXI_LITE_IPIF_I_n_38), - .\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] (AXI_LITE_IPIF_I_n_37), - .\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] (AXI_LITE_IPIF_I_n_36), - .\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] (AXI_LITE_IPIF_I_n_35), - .\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] (AXI_LITE_IPIF_I_n_34), - .\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] (AXI_LITE_IPIF_I_n_33), - .\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] (AXI_LITE_IPIF_I_n_32), - .\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] (AXI_LITE_IPIF_I_n_31), - .\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] (AXI_LITE_IPIF_I_n_30), - .\Not_Dual.gpio_Data_Out_reg[0] (AXI_LITE_IPIF_I_n_41), + .\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] (AXI_LITE_IPIF_I_n_10), + .\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] (AXI_LITE_IPIF_I_n_11), + .\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] (AXI_LITE_IPIF_I_n_12), + .\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] (AXI_LITE_IPIF_I_n_13), + .\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] (AXI_LITE_IPIF_I_n_14), + .\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] (AXI_LITE_IPIF_I_n_15), + .\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] (AXI_LITE_IPIF_I_n_16), + .\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] (AXI_LITE_IPIF_I_n_17), + .\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] (AXI_LITE_IPIF_I_n_18), + .\Not_Dual.gpio_OE_reg[0] (AXI_LITE_IPIF_I_n_7), .Q({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3],gpio_Data_In[4],gpio_Data_In[5],gpio_Data_In[6],gpio_Data_In[7],gpio_Data_In[8],gpio_Data_In[9],gpio_Data_In[10],gpio_Data_In[11],gpio_Data_In[12],gpio_Data_In[13],gpio_Data_In[14],gpio_Data_In[15]}), - .Read_Reg_Rst(Read_Reg_Rst), .bus2ip_cs(bus2ip_cs), .bus2ip_reset(bus2ip_reset), .bus2ip_rnw(bus2ip_rnw), .gpio_io_t(gpio_io_t), .gpio_xferAck_Reg(gpio_xferAck_Reg), - .interrupt_wrce_strb(interrupt_wrce_strb), - .intr2bus_rdack0(intr2bus_rdack0), - .intr_rd_ce_or_reduce(intr_rd_ce_or_reduce), - .intr_wr_ce_or_reduce(intr_wr_ce_or_reduce), - .ip2Bus_RdAck_intr_reg_hole_d1(ip2Bus_RdAck_intr_reg_hole_d1), - .ip2Bus_WrAck_intr_reg_hole_d1(ip2Bus_WrAck_intr_reg_hole_d1), - .ip2bus_data(ip2bus_data[31]), - .\ip2bus_data_i_D1_reg[0] ({p_0_out,ip2bus_data_i}), - .\ip2bus_data_i_D1_reg[0]_0 ({ip2bus_data_i_D1[0],ip2bus_data_i_D1[16],ip2bus_data_i_D1[17],ip2bus_data_i_D1[18],ip2bus_data_i_D1[19],ip2bus_data_i_D1[20],ip2bus_data_i_D1[21],ip2bus_data_i_D1[22],ip2bus_data_i_D1[23],ip2bus_data_i_D1[24],ip2bus_data_i_D1[25],ip2bus_data_i_D1[26],ip2bus_data_i_D1[27],ip2bus_data_i_D1[28],ip2bus_data_i_D1[29],ip2bus_data_i_D1[30],ip2bus_data_i_D1[31]}), + .\ip2bus_data_i_D1_reg[16] ({ip2bus_data_i_D1[16],ip2bus_data_i_D1[17],ip2bus_data_i_D1[18],ip2bus_data_i_D1[19],ip2bus_data_i_D1[20],ip2bus_data_i_D1[21],ip2bus_data_i_D1[22],ip2bus_data_i_D1[23],ip2bus_data_i_D1[24],ip2bus_data_i_D1[25],ip2bus_data_i_D1[26],ip2bus_data_i_D1[27],ip2bus_data_i_D1[28],ip2bus_data_i_D1[29],ip2bus_data_i_D1[30],ip2bus_data_i_D1[31]}), .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1), .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1), - .\ip_irpt_enable_reg_reg[0] (AXI_LITE_IPIF_I_n_53), - .ipif_glbl_irpt_enable_reg_reg(AXI_LITE_IPIF_I_n_54), - .irpt_rdack(irpt_rdack), - .irpt_rdack_d1(irpt_rdack_d1), - .irpt_wrack(irpt_wrack), - .irpt_wrack_d1(irpt_wrack_d1), - .p_0_in(p_0_in), - .p_1_in(p_1_in), - .p_3_in(p_3_in), - .p_8_in(\I_SLAVE_ATTACHMENT/I_DECODER/p_8_in ), .s_axi_aclk(s_axi_aclk), - .s_axi_araddr(s_axi_araddr[8:2]), + .s_axi_araddr({s_axi_araddr[8],s_axi_araddr[3:2]}), .s_axi_aresetn(s_axi_aresetn), .s_axi_arready(s_axi_arready), .s_axi_arvalid(s_axi_arvalid), - .s_axi_awaddr(s_axi_awaddr[8:2]), + .s_axi_awaddr({s_axi_awaddr[8],s_axi_awaddr[3:2]}), .s_axi_awvalid(s_axi_awvalid), .s_axi_bready(s_axi_bready), .s_axi_bvalid(s_axi_bvalid), - .s_axi_rdata({\^s_axi_rdata [31],\^s_axi_rdata [15:0]}), + .s_axi_rdata(\^s_axi_rdata ), .s_axi_rready(s_axi_rready), .s_axi_rvalid(s_axi_rvalid), .s_axi_wdata(s_axi_wdata), @@ -2142,113 +1447,42 @@ module Arty_Z7_20_axi_gpio_shield_2_0_axi_gpio .s_axi_wvalid(s_axi_wvalid)); GND GND (.G(\ )); - Arty_Z7_20_axi_gpio_shield_2_0_interrupt_control \INTR_CTRLR_GEN.INTERRUPT_CONTROL_I - (.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ), - .\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] (AXI_LITE_IPIF_I_n_54), - .\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] (AXI_LITE_IPIF_I_n_53), - .GPIO_intr(GPIO_intr), - .GPIO_xferAck_i(GPIO_xferAck_i), - .IP2INTC_Irpt_i(IP2INTC_Irpt_i), - .bus2ip_reset(bus2ip_reset), - .bus2ip_rnw(bus2ip_rnw), - .interrupt_wrce_strb(interrupt_wrce_strb), - .intr2bus_rdack0(intr2bus_rdack0), - .ip2Bus_RdAck_intr_reg_hole(ip2Bus_RdAck_intr_reg_hole), - .ip2Bus_WrAck_intr_reg_hole(ip2Bus_WrAck_intr_reg_hole), - .ip2bus_rdack_i(ip2bus_rdack_i), - .ip2bus_wrack_i(ip2bus_wrack_i), - .irpt_rdack(irpt_rdack), - .irpt_rdack_d1(irpt_rdack_d1), - .irpt_wrack(irpt_wrack), - .irpt_wrack_d1(irpt_wrack_d1), - .p_0_in(p_0_in), - .p_1_in(p_1_in), - .p_3_in(p_3_in), - .p_8_in(\I_SLAVE_ATTACHMENT/I_DECODER/p_8_in ), - .s_axi_aclk(s_axi_aclk), - .s_axi_wdata(s_axi_wdata[0])); - FDRE \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(intr_rd_ce_or_reduce), - .Q(ip2Bus_RdAck_intr_reg_hole_d1), - .R(bus2ip_reset)); - FDRE \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(AXI_LITE_IPIF_I_n_49), - .Q(ip2Bus_RdAck_intr_reg_hole), - .R(bus2ip_reset)); - FDRE \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(intr_wr_ce_or_reduce), - .Q(ip2Bus_WrAck_intr_reg_hole_d1), - .R(bus2ip_reset)); - FDRE \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(AXI_LITE_IPIF_I_n_51), - .Q(ip2Bus_WrAck_intr_reg_hole), - .R(bus2ip_reset)); - (* sigis = "INTR_LEVEL_HIGH" *) - FDRE \INTR_CTRLR_GEN.ip2intc_irpt_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(IP2INTC_Irpt_i), - .Q(ip2intc_irpt), - .R(bus2ip_reset)); VCC VCC (.P(\ )); - LUT1 #( - .INIT(2'h1)) - bus2ip_reset_i_1 - (.I0(s_axi_aresetn), - .O(bus2ip_reset_i_1_n_0)); - FDRE bus2ip_reset_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(bus2ip_reset_i_1_n_0), - .Q(bus2ip_reset), - .R(1'b0)); Arty_Z7_20_axi_gpio_shield_2_0_GPIO_Core gpio_core_1 - (.D({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3],DBus_Reg[4],DBus_Reg[5],DBus_Reg[6],DBus_Reg[7],DBus_Reg[8],DBus_Reg[9],DBus_Reg[10],DBus_Reg[11],DBus_Reg[12],DBus_Reg[13],DBus_Reg[14],DBus_Reg[15]}), - .E(AXI_LITE_IPIF_I_n_41), + (.D({ip2bus_data[16],ip2bus_data[17],ip2bus_data[18],ip2bus_data[19],ip2bus_data[20],ip2bus_data[21],ip2bus_data[22],ip2bus_data[23],ip2bus_data[24],ip2bus_data[25],ip2bus_data[26],ip2bus_data[27],ip2bus_data[28],ip2bus_data[29],ip2bus_data[30],ip2bus_data[31]}), + .E(AXI_LITE_IPIF_I_n_6), .GPIO_DBus_i(GPIO_DBus_i), - .GPIO_intr(GPIO_intr), .GPIO_xferAck_i(GPIO_xferAck_i), - .\Not_Dual.gpio_OE_reg[10]_0 (AXI_LITE_IPIF_I_n_29), - .\Not_Dual.gpio_OE_reg[11]_0 (AXI_LITE_IPIF_I_n_28), - .\Not_Dual.gpio_OE_reg[12]_0 (AXI_LITE_IPIF_I_n_27), - .\Not_Dual.gpio_OE_reg[13]_0 (AXI_LITE_IPIF_I_n_26), - .\Not_Dual.gpio_OE_reg[14]_0 (AXI_LITE_IPIF_I_n_25), - .\Not_Dual.gpio_OE_reg[15]_0 (AXI_LITE_IPIF_I_n_24), - .\Not_Dual.gpio_OE_reg[1]_0 (AXI_LITE_IPIF_I_n_38), - .\Not_Dual.gpio_OE_reg[2]_0 (AXI_LITE_IPIF_I_n_37), - .\Not_Dual.gpio_OE_reg[3]_0 (AXI_LITE_IPIF_I_n_36), - .\Not_Dual.gpio_OE_reg[4]_0 (AXI_LITE_IPIF_I_n_35), - .\Not_Dual.gpio_OE_reg[5]_0 (AXI_LITE_IPIF_I_n_34), - .\Not_Dual.gpio_OE_reg[6]_0 (AXI_LITE_IPIF_I_n_33), - .\Not_Dual.gpio_OE_reg[7]_0 (AXI_LITE_IPIF_I_n_32), - .\Not_Dual.gpio_OE_reg[8]_0 (AXI_LITE_IPIF_I_n_31), - .\Not_Dual.gpio_OE_reg[9]_0 (AXI_LITE_IPIF_I_n_30), + .\MEM_DECODE_GEN[0].cs_out_i_reg[0] ({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3],DBus_Reg[4],DBus_Reg[5],DBus_Reg[6],DBus_Reg[7],DBus_Reg[8],DBus_Reg[9],DBus_Reg[10],DBus_Reg[11],DBus_Reg[12],DBus_Reg[13],DBus_Reg[14],DBus_Reg[15]}), + .\Not_Dual.gpio_Data_In_reg[10]_0 (AXI_LITE_IPIF_I_n_19), + .\Not_Dual.gpio_Data_In_reg[11]_0 (AXI_LITE_IPIF_I_n_20), + .\Not_Dual.gpio_Data_In_reg[12]_0 (AXI_LITE_IPIF_I_n_21), + .\Not_Dual.gpio_Data_In_reg[13]_0 (AXI_LITE_IPIF_I_n_22), + .\Not_Dual.gpio_Data_In_reg[14]_0 (AXI_LITE_IPIF_I_n_23), + .\Not_Dual.gpio_Data_In_reg[15]_0 (AXI_LITE_IPIF_I_n_24), + .\Not_Dual.gpio_Data_In_reg[1]_0 (AXI_LITE_IPIF_I_n_10), + .\Not_Dual.gpio_Data_In_reg[2]_0 (AXI_LITE_IPIF_I_n_11), + .\Not_Dual.gpio_Data_In_reg[3]_0 (AXI_LITE_IPIF_I_n_12), + .\Not_Dual.gpio_Data_In_reg[4]_0 (AXI_LITE_IPIF_I_n_13), + .\Not_Dual.gpio_Data_In_reg[5]_0 (AXI_LITE_IPIF_I_n_14), + .\Not_Dual.gpio_Data_In_reg[6]_0 (AXI_LITE_IPIF_I_n_15), + .\Not_Dual.gpio_Data_In_reg[7]_0 (AXI_LITE_IPIF_I_n_16), + .\Not_Dual.gpio_Data_In_reg[8]_0 (AXI_LITE_IPIF_I_n_17), + .\Not_Dual.gpio_Data_In_reg[9]_0 (AXI_LITE_IPIF_I_n_18), .Q({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3],gpio_Data_In[4],gpio_Data_In[5],gpio_Data_In[6],gpio_Data_In[7],gpio_Data_In[8],gpio_Data_In[9],gpio_Data_In[10],gpio_Data_In[11],gpio_Data_In[12],gpio_Data_In[13],gpio_Data_In[14],gpio_Data_In[15]}), - .Read_Reg_Rst(Read_Reg_Rst), + .SS(bus2ip_reset), .bus2ip_cs(bus2ip_cs), - .bus2ip_reset(bus2ip_reset), - .bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_40), + .bus2ip_rnw(bus2ip_rnw), + .bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_41), .gpio_io_i(gpio_io_i), .gpio_io_o(gpio_io_o), .gpio_io_t(gpio_io_t), .gpio_xferAck_Reg(gpio_xferAck_Reg), - .ip2bus_data({ip2bus_data[16],ip2bus_data[17],ip2bus_data[18],ip2bus_data[19],ip2bus_data[20],ip2bus_data[21],ip2bus_data[22],ip2bus_data[23],ip2bus_data[24],ip2bus_data[25],ip2bus_data[26],ip2bus_data[27],ip2bus_data[28],ip2bus_data[29],ip2bus_data[30],ip2bus_data[31]}), + .ip2bus_rdack_i(ip2bus_rdack_i), + .ip2bus_wrack_i_D1_reg(gpio_core_1_n_19), + .rst_reg(AXI_LITE_IPIF_I_n_7), .s_axi_aclk(s_axi_aclk)); - FDRE \ip2bus_data_i_D1_reg[0] - (.C(s_axi_aclk), - .CE(1'b1), - .D(p_0_out), - .Q(ip2bus_data_i_D1[0]), - .R(bus2ip_reset)); FDRE \ip2bus_data_i_D1_reg[16] (.C(s_axi_aclk), .CE(1'b1), @@ -2342,7 +1576,7 @@ module Arty_Z7_20_axi_gpio_shield_2_0_axi_gpio FDRE \ip2bus_data_i_D1_reg[31] (.C(s_axi_aclk), .CE(1'b1), - .D(ip2bus_data_i), + .D(ip2bus_data[31]), .Q(ip2bus_data_i_D1[31]), .R(bus2ip_reset)); FDRE ip2bus_rdack_i_D1_reg @@ -2354,153 +1588,109 @@ module Arty_Z7_20_axi_gpio_shield_2_0_axi_gpio FDRE ip2bus_wrack_i_D1_reg (.C(s_axi_aclk), .CE(1'b1), - .D(ip2bus_wrack_i), + .D(gpio_core_1_n_19), .Q(ip2bus_wrack_i_D1), .R(bus2ip_reset)); endmodule (* ORIG_REF_NAME = "axi_lite_ipif" *) module Arty_Z7_20_axi_gpio_shield_2_0_axi_lite_ipif - (p_8_in, + (bus2ip_reset, bus2ip_rnw, bus2ip_cs, - Bus_RNW_reg, s_axi_rvalid, s_axi_bvalid, s_axi_arready, + E, + \Not_Dual.gpio_OE_reg[0] , s_axi_wready, - D, - \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31] , - \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] , - \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] , - \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] , - \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] , - \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] , - \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] , - \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] , - \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] , - \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] , - \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] , - \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] , - \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] , - \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] , - \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] , GPIO_DBus_i, - E, - \Not_Dual.gpio_Data_Out_reg[0] , - \ip2bus_data_i_D1_reg[0] , - intr2bus_rdack0, - irpt_rdack, - irpt_wrack, - interrupt_wrce_strb, - Read_Reg_Rst, - \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg , - intr_rd_ce_or_reduce, - \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg , - intr_wr_ce_or_reduce, - \ip_irpt_enable_reg_reg[0] , - ipif_glbl_irpt_enable_reg_reg, + \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] , + \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] , + \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] , + \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] , + \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] , + \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] , + \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] , + \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] , + \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] , + \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] , + \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] , + \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] , + \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] , + \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] , + \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31] , + D, + \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[16] , s_axi_rdata, - bus2ip_reset, s_axi_aclk, s_axi_arvalid, + s_axi_awvalid, + s_axi_wvalid, + s_axi_araddr, + s_axi_awaddr, s_axi_aresetn, + s_axi_rready, + s_axi_bready, ip2bus_rdack_i_D1, ip2bus_wrack_i_D1, - s_axi_bready, - s_axi_rready, - s_axi_awaddr, - s_axi_araddr, - s_axi_awvalid, - s_axi_wvalid, - s_axi_wdata, - gpio_io_t, Q, - p_0_in, - irpt_rdack_d1, - irpt_wrack_d1, - ip2bus_data, - p_3_in, - p_1_in, - GPIO_xferAck_i, + gpio_io_t, + s_axi_wdata, gpio_xferAck_Reg, - ip2Bus_RdAck_intr_reg_hole_d1, - ip2Bus_WrAck_intr_reg_hole_d1, - \ip2bus_data_i_D1_reg[0]_0 ); - output p_8_in; + GPIO_xferAck_i, + \ip2bus_data_i_D1_reg[16] ); + output bus2ip_reset; output bus2ip_rnw; - output [0:0]bus2ip_cs; - output Bus_RNW_reg; + output bus2ip_cs; output s_axi_rvalid; output s_axi_bvalid; output s_axi_arready; + output [0:0]E; + output [0:0]\Not_Dual.gpio_OE_reg[0] ; output s_axi_wready; - output [15:0]D; - output \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31] ; - output \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] ; - output \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] ; - output \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] ; - output \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] ; - output \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] ; - output \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] ; - output \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] ; - output \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] ; - output \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] ; - output \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] ; - output \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] ; - output \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] ; - output \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] ; - output \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] ; output [0:0]GPIO_DBus_i; - output [0:0]E; - output [0:0]\Not_Dual.gpio_Data_Out_reg[0] ; - output [1:0]\ip2bus_data_i_D1_reg[0] ; - output intr2bus_rdack0; - output irpt_rdack; - output irpt_wrack; - output interrupt_wrce_strb; - output Read_Reg_Rst; - output \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ; - output intr_rd_ce_or_reduce; - output \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ; - output intr_wr_ce_or_reduce; - output \ip_irpt_enable_reg_reg[0] ; - output ipif_glbl_irpt_enable_reg_reg; - output [16:0]s_axi_rdata; - input bus2ip_reset; + output \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] ; + output \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] ; + output \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] ; + output \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] ; + output \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] ; + output \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] ; + output \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] ; + output \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] ; + output \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] ; + output \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] ; + output \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] ; + output \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] ; + output \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] ; + output \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] ; + output \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31] ; + output [15:0]D; + output \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[16] ; + output [15:0]s_axi_rdata; input s_axi_aclk; input s_axi_arvalid; + input s_axi_awvalid; + input s_axi_wvalid; + input [2:0]s_axi_araddr; + input [2:0]s_axi_awaddr; input s_axi_aresetn; + input s_axi_rready; + input s_axi_bready; input ip2bus_rdack_i_D1; input ip2bus_wrack_i_D1; - input s_axi_bready; - input s_axi_rready; - input [6:0]s_axi_awaddr; - input [6:0]s_axi_araddr; - input s_axi_awvalid; - input s_axi_wvalid; - input [31:0]s_axi_wdata; - input [15:0]gpio_io_t; input [15:0]Q; - input [0:0]p_0_in; - input irpt_rdack_d1; - input irpt_wrack_d1; - input [0:0]ip2bus_data; - input [0:0]p_3_in; - input [0:0]p_1_in; - input GPIO_xferAck_i; + input [15:0]gpio_io_t; + input [31:0]s_axi_wdata; input gpio_xferAck_Reg; - input ip2Bus_RdAck_intr_reg_hole_d1; - input ip2Bus_WrAck_intr_reg_hole_d1; - input [16:0]\ip2bus_data_i_D1_reg[0]_0 ; + input GPIO_xferAck_i; + input [15:0]\ip2bus_data_i_D1_reg[16] ; - wire Bus_RNW_reg; wire [15:0]D; wire [0:0]E; wire [0:0]GPIO_DBus_i; wire GPIO_xferAck_i; - wire \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ; - wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ; + wire \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[16] ; wire \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] ; wire \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] ; wire \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] ; @@ -2516,45 +1706,26 @@ module Arty_Z7_20_axi_gpio_shield_2_0_axi_lite_ipif wire \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] ; wire \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] ; wire \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] ; - wire [0:0]\Not_Dual.gpio_Data_Out_reg[0] ; + wire [0:0]\Not_Dual.gpio_OE_reg[0] ; wire [15:0]Q; - wire Read_Reg_Rst; - wire [0:0]bus2ip_cs; + wire bus2ip_cs; wire bus2ip_reset; wire bus2ip_rnw; wire [15:0]gpio_io_t; wire gpio_xferAck_Reg; - wire interrupt_wrce_strb; - wire intr2bus_rdack0; - wire intr_rd_ce_or_reduce; - wire intr_wr_ce_or_reduce; - wire ip2Bus_RdAck_intr_reg_hole_d1; - wire ip2Bus_WrAck_intr_reg_hole_d1; - wire [0:0]ip2bus_data; - wire [1:0]\ip2bus_data_i_D1_reg[0] ; - wire [16:0]\ip2bus_data_i_D1_reg[0]_0 ; + wire [15:0]\ip2bus_data_i_D1_reg[16] ; wire ip2bus_rdack_i_D1; wire ip2bus_wrack_i_D1; - wire \ip_irpt_enable_reg_reg[0] ; - wire ipif_glbl_irpt_enable_reg_reg; - wire irpt_rdack; - wire irpt_rdack_d1; - wire irpt_wrack; - wire irpt_wrack_d1; - wire [0:0]p_0_in; - wire [0:0]p_1_in; - wire [0:0]p_3_in; - wire p_8_in; wire s_axi_aclk; - wire [6:0]s_axi_araddr; + wire [2:0]s_axi_araddr; wire s_axi_aresetn; wire s_axi_arready; wire s_axi_arvalid; - wire [6:0]s_axi_awaddr; + wire [2:0]s_axi_awaddr; wire s_axi_awvalid; wire s_axi_bready; wire s_axi_bvalid; - wire [16:0]s_axi_rdata; + wire [15:0]s_axi_rdata; wire s_axi_rready; wire s_axi_rvalid; wire [31:0]s_axi_wdata; @@ -2566,8 +1737,8 @@ module Arty_Z7_20_axi_gpio_shield_2_0_axi_lite_ipif .E(E), .GPIO_DBus_i(GPIO_DBus_i), .GPIO_xferAck_i(GPIO_xferAck_i), - .\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg (\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ), - .\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg (\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ), + .\MEM_DECODE_GEN[0].cs_out_i_reg[0] (bus2ip_cs), + .\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[16] (\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[16] ), .\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] (\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] ), .\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] (\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] ), .\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] (\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] ), @@ -2583,36 +1754,15 @@ module Arty_Z7_20_axi_gpio_shield_2_0_axi_lite_ipif .\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] (\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] ), .\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] (\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] ), .\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] (\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] ), - .\Not_Dual.gpio_Data_Out_reg[0] (\Not_Dual.gpio_Data_Out_reg[0] ), - .\Not_Dual.gpio_Data_Out_reg[15] (bus2ip_cs), - .\Not_Dual.gpio_OE_reg[0] (bus2ip_rnw), + .\Not_Dual.gpio_Data_Out_reg[0] (bus2ip_rnw), + .\Not_Dual.gpio_OE_reg[0] (\Not_Dual.gpio_OE_reg[0] ), .Q(Q), - .Read_Reg_Rst(Read_Reg_Rst), - .bus2ip_reset(bus2ip_reset), + .SR(bus2ip_reset), .gpio_io_t(gpio_io_t), .gpio_xferAck_Reg(gpio_xferAck_Reg), - .interrupt_wrce_strb(interrupt_wrce_strb), - .intr2bus_rdack0(intr2bus_rdack0), - .intr_rd_ce_or_reduce(intr_rd_ce_or_reduce), - .intr_wr_ce_or_reduce(intr_wr_ce_or_reduce), - .ip2Bus_RdAck_intr_reg_hole_d1(ip2Bus_RdAck_intr_reg_hole_d1), - .ip2Bus_WrAck_intr_reg_hole_d1(ip2Bus_WrAck_intr_reg_hole_d1), - .ip2bus_data(ip2bus_data), - .\ip2bus_data_i_D1_reg[0] (p_8_in), - .\ip2bus_data_i_D1_reg[0]_0 (\ip2bus_data_i_D1_reg[0] ), - .\ip2bus_data_i_D1_reg[0]_1 (\ip2bus_data_i_D1_reg[0]_0 ), + .\ip2bus_data_i_D1_reg[16] (\ip2bus_data_i_D1_reg[16] ), .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1), .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1), - .\ip_irpt_enable_reg_reg[0] (Bus_RNW_reg), - .\ip_irpt_enable_reg_reg[0]_0 (\ip_irpt_enable_reg_reg[0] ), - .ipif_glbl_irpt_enable_reg_reg(ipif_glbl_irpt_enable_reg_reg), - .irpt_rdack(irpt_rdack), - .irpt_rdack_d1(irpt_rdack_d1), - .irpt_wrack(irpt_wrack), - .irpt_wrack_d1(irpt_wrack_d1), - .p_0_in(p_0_in), - .p_1_in(p_1_in), - .p_3_in(p_3_in), .s_axi_aclk(s_axi_aclk), .s_axi_araddr(s_axi_araddr), .s_axi_aresetn(s_axi_aresetn), @@ -2632,19 +1782,13 @@ endmodule (* ORIG_REF_NAME = "cdc_sync" *) module Arty_Z7_20_axi_gpio_shield_2_0_cdc_sync - (D, - scndry_vect_out, - Q, + (scndry_vect_out, gpio_io_i, s_axi_aclk); - output [15:0]D; output [15:0]scndry_vect_out; - input [15:0]Q; input [15:0]gpio_io_i; input s_axi_aclk; - wire [15:0]D; - wire [15:0]Q; wire [15:0]gpio_io_i; wire s_axi_aclk; wire s_level_out_bus_d1_cdc_to_0; @@ -3401,423 +2545,108 @@ module Arty_Z7_20_axi_gpio_shield_2_0_cdc_sync .D(gpio_io_i[9]), .Q(s_level_out_bus_d1_cdc_to_9), .R(1'b0)); - LUT2 #( - .INIT(4'h6)) - \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[0]_i_1 - (.I0(Q[15]), - .I1(scndry_vect_out[15]), - .O(D[15])); - LUT2 #( - .INIT(4'h6)) - \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[10]_i_1 - (.I0(Q[5]), - .I1(scndry_vect_out[5]), - .O(D[5])); - LUT2 #( - .INIT(4'h6)) - \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[11]_i_1 - (.I0(Q[4]), - .I1(scndry_vect_out[4]), - .O(D[4])); - LUT2 #( - .INIT(4'h6)) - \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[12]_i_1 - (.I0(Q[3]), - .I1(scndry_vect_out[3]), - .O(D[3])); - LUT2 #( - .INIT(4'h6)) - \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[13]_i_1 - (.I0(Q[2]), - .I1(scndry_vect_out[2]), - .O(D[2])); - LUT2 #( - .INIT(4'h6)) - \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[14]_i_1 - (.I0(Q[1]), - .I1(scndry_vect_out[1]), - .O(D[1])); - LUT2 #( - .INIT(4'h6)) - \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[15]_i_1 - (.I0(Q[0]), - .I1(scndry_vect_out[0]), - .O(D[0])); - LUT2 #( - .INIT(4'h6)) - \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[1]_i_1 - (.I0(Q[14]), - .I1(scndry_vect_out[14]), - .O(D[14])); - LUT2 #( - .INIT(4'h6)) - \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[2]_i_1 - (.I0(Q[13]), - .I1(scndry_vect_out[13]), - .O(D[13])); - LUT2 #( - .INIT(4'h6)) - \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[3]_i_1 - (.I0(Q[12]), - .I1(scndry_vect_out[12]), - .O(D[12])); - LUT2 #( - .INIT(4'h6)) - \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[4]_i_1 - (.I0(Q[11]), - .I1(scndry_vect_out[11]), - .O(D[11])); - LUT2 #( - .INIT(4'h6)) - \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[5]_i_1 - (.I0(Q[10]), - .I1(scndry_vect_out[10]), - .O(D[10])); - LUT2 #( - .INIT(4'h6)) - \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[6]_i_1 - (.I0(Q[9]), - .I1(scndry_vect_out[9]), - .O(D[9])); - LUT2 #( - .INIT(4'h6)) - \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[7]_i_1 - (.I0(Q[8]), - .I1(scndry_vect_out[8]), - .O(D[8])); - LUT2 #( - .INIT(4'h6)) - \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[8]_i_1 - (.I0(Q[7]), - .I1(scndry_vect_out[7]), - .O(D[7])); - LUT2 #( - .INIT(4'h6)) - \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[9]_i_1 - (.I0(Q[6]), - .I1(scndry_vect_out[6]), - .O(D[6])); -endmodule - -(* ORIG_REF_NAME = "interrupt_control" *) -module Arty_Z7_20_axi_gpio_shield_2_0_interrupt_control - (irpt_wrack_d1, - p_3_in, - irpt_rdack_d1, - p_1_in, - p_0_in, - IP2INTC_Irpt_i, - ip2bus_wrack_i, - ip2bus_rdack_i, - bus2ip_reset, - irpt_wrack, - s_axi_aclk, - GPIO_intr, - interrupt_wrce_strb, - irpt_rdack, - intr2bus_rdack0, - \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] , - \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] , - p_8_in, - s_axi_wdata, - Bus_RNW_reg, - ip2Bus_WrAck_intr_reg_hole, - bus2ip_rnw, - GPIO_xferAck_i, - ip2Bus_RdAck_intr_reg_hole); - output irpt_wrack_d1; - output [0:0]p_3_in; - output irpt_rdack_d1; - output [0:0]p_1_in; - output [0:0]p_0_in; - output IP2INTC_Irpt_i; - output ip2bus_wrack_i; - output ip2bus_rdack_i; - input bus2ip_reset; - input irpt_wrack; - input s_axi_aclk; - input GPIO_intr; - input interrupt_wrce_strb; - input irpt_rdack; - input intr2bus_rdack0; - input \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] ; - input \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ; - input p_8_in; - input [0:0]s_axi_wdata; - input Bus_RNW_reg; - input ip2Bus_WrAck_intr_reg_hole; - input bus2ip_rnw; - input GPIO_xferAck_i; - input ip2Bus_RdAck_intr_reg_hole; - - wire Bus_RNW_reg; - wire \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ; - wire \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] ; - wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0 ; - wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0 ; - wire GPIO_intr; - wire GPIO_xferAck_i; - wire IP2INTC_Irpt_i; - wire bus2ip_reset; - wire bus2ip_rnw; - wire interrupt_wrce_strb; - wire intr2bus_rdack; - wire intr2bus_rdack0; - wire intr2bus_wrack; - wire ip2Bus_RdAck_intr_reg_hole; - wire ip2Bus_WrAck_intr_reg_hole; - wire ip2bus_rdack_i; - wire ip2bus_wrack_i; - wire irpt_dly1; - wire irpt_dly2; - wire irpt_rdack; - wire irpt_rdack_d1; - wire irpt_wrack; - wire irpt_wrack_d1; - wire [0:0]p_0_in; - wire [0:0]p_1_in; - wire [0:0]p_3_in; - wire p_8_in; - wire s_axi_aclk; - wire [0:0]s_axi_wdata; - - FDSE \DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly1_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(GPIO_intr), - .Q(irpt_dly1), - .S(bus2ip_reset)); - FDSE \DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly2_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(irpt_dly1), - .Q(irpt_dly2), - .S(bus2ip_reset)); - LUT6 #( - .INIT(64'hF4F4F4F44FF4F4F4)) - \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1 - (.I0(irpt_dly2), - .I1(irpt_dly1), - .I2(p_3_in), - .I3(p_8_in), - .I4(s_axi_wdata), - .I5(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0 ), - .O(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0 )); - LUT2 #( - .INIT(4'hE)) - \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2 - (.I0(irpt_wrack_d1), - .I1(Bus_RNW_reg), - .O(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0 )); - FDRE \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] - (.C(s_axi_aclk), - .CE(1'b1), - .D(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0 ), - .Q(p_3_in), - .R(bus2ip_reset)); - LUT3 #( - .INIT(8'h80)) - \INTR_CTRLR_GEN.ip2intc_irpt_i_1 - (.I0(p_3_in), - .I1(p_1_in), - .I2(p_0_in), - .O(IP2INTC_Irpt_i)); - FDRE intr2bus_rdack_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(intr2bus_rdack0), - .Q(intr2bus_rdack), - .R(bus2ip_reset)); - FDRE intr2bus_wrack_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(interrupt_wrce_strb), - .Q(intr2bus_wrack), - .R(bus2ip_reset)); - LUT4 #( - .INIT(16'hFEEE)) - ip2bus_rdack_i_D1_i_1 - (.I0(ip2Bus_RdAck_intr_reg_hole), - .I1(intr2bus_rdack), - .I2(bus2ip_rnw), - .I3(GPIO_xferAck_i), - .O(ip2bus_rdack_i)); - LUT4 #( - .INIT(16'hEFEE)) - ip2bus_wrack_i_D1_i_1 - (.I0(ip2Bus_WrAck_intr_reg_hole), - .I1(intr2bus_wrack), - .I2(bus2ip_rnw), - .I3(GPIO_xferAck_i), - .O(ip2bus_wrack_i)); - FDRE \ip_irpt_enable_reg_reg[0] - (.C(s_axi_aclk), - .CE(1'b1), - .D(\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] ), - .Q(p_1_in), - .R(bus2ip_reset)); - FDRE ipif_glbl_irpt_enable_reg_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ), - .Q(p_0_in), - .R(bus2ip_reset)); - FDRE irpt_rdack_d1_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(irpt_rdack), - .Q(irpt_rdack_d1), - .R(bus2ip_reset)); - FDRE irpt_wrack_d1_reg - (.C(s_axi_aclk), - .CE(1'b1), - .D(irpt_wrack), - .Q(irpt_wrack_d1), - .R(bus2ip_reset)); endmodule (* ORIG_REF_NAME = "slave_attachment" *) module Arty_Z7_20_axi_gpio_shield_2_0_slave_attachment - (\ip2bus_data_i_D1_reg[0] , - \Not_Dual.gpio_OE_reg[0] , - \Not_Dual.gpio_Data_Out_reg[15] , - \ip_irpt_enable_reg_reg[0] , + (SR, + \Not_Dual.gpio_Data_Out_reg[0] , + \MEM_DECODE_GEN[0].cs_out_i_reg[0] , s_axi_rvalid, s_axi_bvalid, s_axi_arready, + E, + \Not_Dual.gpio_OE_reg[0] , s_axi_wready, - D, - \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31] , - \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] , - \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] , - \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] , - \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] , - \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] , - \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] , - \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] , - \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] , - \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] , - \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] , - \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] , - \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] , - \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] , - \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] , GPIO_DBus_i, - E, - \Not_Dual.gpio_Data_Out_reg[0] , - \ip2bus_data_i_D1_reg[0]_0 , - intr2bus_rdack0, - irpt_rdack, - irpt_wrack, - interrupt_wrce_strb, - Read_Reg_Rst, - \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg , - intr_rd_ce_or_reduce, - \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg , - intr_wr_ce_or_reduce, - \ip_irpt_enable_reg_reg[0]_0 , - ipif_glbl_irpt_enable_reg_reg, + \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] , + \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] , + \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] , + \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] , + \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] , + \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] , + \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] , + \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] , + \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] , + \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] , + \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] , + \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] , + \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] , + \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] , + \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31] , + D, + \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[16] , s_axi_rdata, - bus2ip_reset, s_axi_aclk, s_axi_arvalid, + s_axi_awvalid, + s_axi_wvalid, + s_axi_araddr, + s_axi_awaddr, s_axi_aresetn, + s_axi_rready, + s_axi_bready, ip2bus_rdack_i_D1, ip2bus_wrack_i_D1, - s_axi_bready, - s_axi_rready, - s_axi_awaddr, - s_axi_araddr, - s_axi_awvalid, - s_axi_wvalid, - s_axi_wdata, - gpio_io_t, Q, - p_0_in, - irpt_rdack_d1, - irpt_wrack_d1, - ip2bus_data, - p_3_in, - p_1_in, - GPIO_xferAck_i, + gpio_io_t, + s_axi_wdata, gpio_xferAck_Reg, - ip2Bus_RdAck_intr_reg_hole_d1, - ip2Bus_WrAck_intr_reg_hole_d1, - \ip2bus_data_i_D1_reg[0]_1 ); - output \ip2bus_data_i_D1_reg[0] ; - output \Not_Dual.gpio_OE_reg[0] ; - output \Not_Dual.gpio_Data_Out_reg[15] ; - output \ip_irpt_enable_reg_reg[0] ; + GPIO_xferAck_i, + \ip2bus_data_i_D1_reg[16] ); + output SR; + output \Not_Dual.gpio_Data_Out_reg[0] ; + output \MEM_DECODE_GEN[0].cs_out_i_reg[0] ; output s_axi_rvalid; output s_axi_bvalid; output s_axi_arready; + output [0:0]E; + output [0:0]\Not_Dual.gpio_OE_reg[0] ; output s_axi_wready; - output [15:0]D; - output \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31] ; - output \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] ; - output \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] ; - output \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] ; - output \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] ; - output \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] ; - output \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] ; - output \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] ; - output \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] ; - output \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] ; - output \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] ; - output \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] ; - output \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] ; - output \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] ; - output \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] ; output [0:0]GPIO_DBus_i; - output [0:0]E; - output [0:0]\Not_Dual.gpio_Data_Out_reg[0] ; - output [1:0]\ip2bus_data_i_D1_reg[0]_0 ; - output intr2bus_rdack0; - output irpt_rdack; - output irpt_wrack; - output interrupt_wrce_strb; - output Read_Reg_Rst; - output \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ; - output intr_rd_ce_or_reduce; - output \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ; - output intr_wr_ce_or_reduce; - output \ip_irpt_enable_reg_reg[0]_0 ; - output ipif_glbl_irpt_enable_reg_reg; - output [16:0]s_axi_rdata; - input bus2ip_reset; + output \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] ; + output \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] ; + output \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] ; + output \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] ; + output \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] ; + output \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] ; + output \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] ; + output \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] ; + output \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] ; + output \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] ; + output \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] ; + output \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] ; + output \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] ; + output \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] ; + output \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31] ; + output [15:0]D; + output \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[16] ; + output [15:0]s_axi_rdata; input s_axi_aclk; input s_axi_arvalid; + input s_axi_awvalid; + input s_axi_wvalid; + input [2:0]s_axi_araddr; + input [2:0]s_axi_awaddr; input s_axi_aresetn; + input s_axi_rready; + input s_axi_bready; input ip2bus_rdack_i_D1; input ip2bus_wrack_i_D1; - input s_axi_bready; - input s_axi_rready; - input [6:0]s_axi_awaddr; - input [6:0]s_axi_araddr; - input s_axi_awvalid; - input s_axi_wvalid; - input [31:0]s_axi_wdata; - input [15:0]gpio_io_t; input [15:0]Q; - input [0:0]p_0_in; - input irpt_rdack_d1; - input irpt_wrack_d1; - input [0:0]ip2bus_data; - input [0:0]p_3_in; - input [0:0]p_1_in; - input GPIO_xferAck_i; + input [15:0]gpio_io_t; + input [31:0]s_axi_wdata; input gpio_xferAck_Reg; - input ip2Bus_RdAck_intr_reg_hole_d1; - input ip2Bus_WrAck_intr_reg_hole_d1; - input [16:0]\ip2bus_data_i_D1_reg[0]_1 ; + input GPIO_xferAck_i; + input [15:0]\ip2bus_data_i_D1_reg[16] ; wire [15:0]D; wire [0:0]E; wire [0:0]GPIO_DBus_i; wire GPIO_xferAck_i; wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ; - wire \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ; - wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ; + wire \MEM_DECODE_GEN[0].cs_out_i_reg[0] ; + wire \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[16] ; wire \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] ; wire \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] ; wire \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] ; @@ -3833,59 +2662,42 @@ module Arty_Z7_20_axi_gpio_shield_2_0_slave_attachment wire \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] ; wire \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] ; wire \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] ; - wire [0:0]\Not_Dual.gpio_Data_Out_reg[0] ; - wire \Not_Dual.gpio_Data_Out_reg[15] ; - wire \Not_Dual.gpio_OE_reg[0] ; + wire \Not_Dual.gpio_Data_Out_reg[0] ; + wire [0:0]\Not_Dual.gpio_OE_reg[0] ; wire [15:0]Q; - wire Read_Reg_Rst; + wire SR; wire [0:6]bus2ip_addr; - wire bus2ip_reset; + wire \bus2ip_addr_i[2]_i_1_n_0 ; + wire \bus2ip_addr_i[3]_i_1_n_0 ; + wire \bus2ip_addr_i[8]_i_1_n_0 ; + wire \bus2ip_addr_i[8]_i_2_n_0 ; wire bus2ip_rnw_i06_out; wire clear; wire [15:0]gpio_io_t; wire gpio_xferAck_Reg; - wire interrupt_wrce_strb; - wire intr2bus_rdack0; - wire intr_rd_ce_or_reduce; - wire intr_wr_ce_or_reduce; - wire ip2Bus_RdAck_intr_reg_hole_d1; - wire ip2Bus_WrAck_intr_reg_hole_d1; - wire [0:0]ip2bus_data; - wire \ip2bus_data_i_D1_reg[0] ; - wire [1:0]\ip2bus_data_i_D1_reg[0]_0 ; - wire [16:0]\ip2bus_data_i_D1_reg[0]_1 ; + wire [15:0]\ip2bus_data_i_D1_reg[16] ; wire ip2bus_rdack_i_D1; wire ip2bus_wrack_i_D1; - wire \ip_irpt_enable_reg_reg[0] ; - wire \ip_irpt_enable_reg_reg[0]_0 ; - wire ipif_glbl_irpt_enable_reg_reg; - wire irpt_rdack; - wire irpt_rdack_d1; - wire irpt_wrack; - wire irpt_wrack_d1; wire is_read; wire is_read_i_1_n_0; wire is_write; wire is_write_i_1_n_0; wire is_write_reg_n_0; - wire [0:0]p_0_in; - wire [1:0]p_0_out__0; - wire [0:0]p_1_in; - wire [8:2]p_1_in__0; - wire [0:0]p_3_in; + wire [1:0]p_0_out; + wire p_1_in; wire [3:0]plusOp; wire s_axi_aclk; - wire [6:0]s_axi_araddr; + wire [2:0]s_axi_araddr; wire s_axi_aresetn; wire s_axi_arready; wire s_axi_arvalid; - wire [6:0]s_axi_awaddr; + wire [2:0]s_axi_awaddr; wire s_axi_awvalid; wire s_axi_bready; wire s_axi_bvalid; wire s_axi_bvalid_i_i_1_n_0; - wire [16:0]s_axi_rdata; - wire s_axi_rdata_i; + wire [15:0]s_axi_rdata; + wire \s_axi_rdata_i[15]_i_1_n_0 ; wire s_axi_rready; wire s_axi_rvalid; wire s_axi_rvalid_i_i_1_n_0; @@ -3895,43 +2707,43 @@ module Arty_Z7_20_axi_gpio_shield_2_0_slave_attachment wire start2; wire start2_i_1_n_0; wire [1:0]state; - wire \state[1]_i_2_n_0 ; + wire state1__2; wire \state[1]_i_3_n_0 ; - (* SOFT_HLUTNM = "soft_lutpair6" *) + (* SOFT_HLUTNM = "soft_lutpair3" *) LUT1 #( .INIT(2'h1)) \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1 (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]), .O(plusOp[0])); - (* SOFT_HLUTNM = "soft_lutpair6" *) + (* SOFT_HLUTNM = "soft_lutpair3" *) LUT2 #( .INIT(4'h6)) \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1 (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]), .I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]), .O(plusOp[1])); - (* SOFT_HLUTNM = "soft_lutpair5" *) + (* SOFT_HLUTNM = "soft_lutpair2" *) LUT3 #( .INIT(8'h78)) \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1 - (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]), - .I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]), + (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]), + .I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]), .I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]), .O(plusOp[2])); LUT2 #( .INIT(4'h9)) \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1 - (.I0(state[1]), - .I1(state[0]), + (.I0(state[0]), + .I1(state[1]), .O(clear)); - (* SOFT_HLUTNM = "soft_lutpair5" *) + (* SOFT_HLUTNM = "soft_lutpair2" *) LUT4 #( .INIT(16'h7F80)) \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2 - (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]), + (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]), .I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]), - .I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]), + .I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]), .I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]), .O(plusOp[3])); FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0] @@ -3963,8 +2775,9 @@ module Arty_Z7_20_axi_gpio_shield_2_0_slave_attachment .E(E), .GPIO_DBus_i(GPIO_DBus_i), .GPIO_xferAck_i(GPIO_xferAck_i), - .\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg (\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ), - .\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg (\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ), + .\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] (\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ), + .\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 (\MEM_DECODE_GEN[0].cs_out_i_reg[0] ), + .\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[16] (\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[16] ), .\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] (\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] ), .\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] (\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] ), .\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] (\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] ), @@ -3981,171 +2794,98 @@ module Arty_Z7_20_axi_gpio_shield_2_0_slave_attachment .\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] (\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] ), .\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] (\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] ), .\Not_Dual.gpio_Data_In_reg[0] (Q), - .\Not_Dual.gpio_Data_Out_reg[0] (\Not_Dual.gpio_Data_Out_reg[0] ), - .\Not_Dual.gpio_Data_Out_reg[15] (\Not_Dual.gpio_Data_Out_reg[15] ), - .Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ), - .Read_Reg_Rst(Read_Reg_Rst), - .\bus2ip_addr_i_reg[8] ({bus2ip_addr[0],bus2ip_addr[1],bus2ip_addr[2],bus2ip_addr[3],bus2ip_addr[4],bus2ip_addr[5],bus2ip_addr[6]}), - .bus2ip_reset(bus2ip_reset), - .bus2ip_rnw_i_reg(\Not_Dual.gpio_OE_reg[0] ), + .\Not_Dual.gpio_OE_reg[0] (\Not_Dual.gpio_OE_reg[0] ), + .Q({bus2ip_addr[0],bus2ip_addr[5],bus2ip_addr[6]}), + .bus2ip_rnw_i_reg(\Not_Dual.gpio_Data_Out_reg[0] ), .gpio_io_t(gpio_io_t), .gpio_xferAck_Reg(gpio_xferAck_Reg), - .interrupt_wrce_strb(interrupt_wrce_strb), - .intr2bus_rdack0(intr2bus_rdack0), - .intr_rd_ce_or_reduce(intr_rd_ce_or_reduce), - .intr_wr_ce_or_reduce(intr_wr_ce_or_reduce), - .ip2Bus_RdAck_intr_reg_hole_d1(ip2Bus_RdAck_intr_reg_hole_d1), - .ip2Bus_WrAck_intr_reg_hole_d1(ip2Bus_WrAck_intr_reg_hole_d1), - .ip2bus_data(ip2bus_data), - .\ip2bus_data_i_D1_reg[0] (\ip2bus_data_i_D1_reg[0] ), - .\ip2bus_data_i_D1_reg[0]_0 (\ip2bus_data_i_D1_reg[0]_0 ), .ip2bus_rdack_i_D1(ip2bus_rdack_i_D1), .ip2bus_wrack_i_D1(ip2bus_wrack_i_D1), - .\ip_irpt_enable_reg_reg[0] (\ip_irpt_enable_reg_reg[0] ), - .\ip_irpt_enable_reg_reg[0]_0 (\ip_irpt_enable_reg_reg[0]_0 ), - .ipif_glbl_irpt_enable_reg_reg(ipif_glbl_irpt_enable_reg_reg), - .irpt_rdack(irpt_rdack), - .irpt_rdack_d1(irpt_rdack_d1), - .irpt_wrack(irpt_wrack), - .irpt_wrack_d1(irpt_wrack_d1), .is_read(is_read), .is_write_reg(is_write_reg_n_0), - .p_0_in(p_0_in), - .p_1_in(p_1_in), - .p_3_in(p_3_in), + .rst_reg(SR), .s_axi_aclk(s_axi_aclk), .s_axi_aresetn(s_axi_aresetn), .s_axi_arready(s_axi_arready), .s_axi_wdata(s_axi_wdata), .s_axi_wready(s_axi_wready), - .start2(start2)); + .start2_reg(start2)); LUT5 #( - .INIT(32'hABAAA8AA)) + .INIT(32'hCCCACCCC)) \bus2ip_addr_i[2]_i_1 - (.I0(s_axi_awaddr[0]), - .I1(state[1]), + (.I0(s_axi_araddr[0]), + .I1(s_axi_awaddr[0]), .I2(state[0]), - .I3(s_axi_arvalid), - .I4(s_axi_araddr[0]), - .O(p_1_in__0[2])); + .I3(state[1]), + .I4(s_axi_arvalid), + .O(\bus2ip_addr_i[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair0" *) LUT5 #( - .INIT(32'hABAAA8AA)) + .INIT(32'hCCCACCCC)) \bus2ip_addr_i[3]_i_1 - (.I0(s_axi_awaddr[1]), - .I1(state[1]), - .I2(state[0]), - .I3(s_axi_arvalid), - .I4(s_axi_araddr[1]), - .O(p_1_in__0[3])); - (* SOFT_HLUTNM = "soft_lutpair4" *) - LUT5 #( - .INIT(32'hABAAA8AA)) - \bus2ip_addr_i[4]_i_1 - (.I0(s_axi_awaddr[2]), - .I1(state[1]), - .I2(state[0]), - .I3(s_axi_arvalid), - .I4(s_axi_araddr[2]), - .O(p_1_in__0[4])); - LUT5 #( - .INIT(32'hABAAA8AA)) - \bus2ip_addr_i[5]_i_1 - (.I0(s_axi_awaddr[3]), - .I1(state[1]), + (.I0(s_axi_araddr[1]), + .I1(s_axi_awaddr[1]), .I2(state[0]), - .I3(s_axi_arvalid), - .I4(s_axi_araddr[3]), - .O(p_1_in__0[5])); - LUT5 #( - .INIT(32'hABAAA8AA)) - \bus2ip_addr_i[6]_i_1 - (.I0(s_axi_awaddr[4]), - .I1(state[1]), - .I2(state[0]), - .I3(s_axi_arvalid), - .I4(s_axi_araddr[4]), - .O(p_1_in__0[6])); - LUT5 #( - .INIT(32'hABAAA8AA)) - \bus2ip_addr_i[7]_i_1 - (.I0(s_axi_awaddr[5]), - .I1(state[1]), - .I2(state[0]), - .I3(s_axi_arvalid), - .I4(s_axi_araddr[5]), - .O(p_1_in__0[7])); + .I3(state[1]), + .I4(s_axi_arvalid), + .O(\bus2ip_addr_i[3]_i_1_n_0 )); LUT5 #( - .INIT(32'hABAAA8AA)) + .INIT(32'h000000EA)) \bus2ip_addr_i[8]_i_1 - (.I0(s_axi_awaddr[6]), - .I1(state[1]), + (.I0(s_axi_arvalid), + .I1(s_axi_awvalid), + .I2(s_axi_wvalid), + .I3(state[1]), + .I4(state[0]), + .O(\bus2ip_addr_i[8]_i_1_n_0 )); + LUT5 #( + .INIT(32'hCCCACCCC)) + \bus2ip_addr_i[8]_i_2 + (.I0(s_axi_araddr[2]), + .I1(s_axi_awaddr[2]), .I2(state[0]), - .I3(s_axi_arvalid), - .I4(s_axi_araddr[6]), - .O(p_1_in__0[8])); + .I3(state[1]), + .I4(s_axi_arvalid), + .O(\bus2ip_addr_i[8]_i_2_n_0 )); FDRE \bus2ip_addr_i_reg[2] (.C(s_axi_aclk), - .CE(start2_i_1_n_0), - .D(p_1_in__0[2]), + .CE(\bus2ip_addr_i[8]_i_1_n_0 ), + .D(\bus2ip_addr_i[2]_i_1_n_0 ), .Q(bus2ip_addr[6]), - .R(bus2ip_reset)); + .R(SR)); FDRE \bus2ip_addr_i_reg[3] (.C(s_axi_aclk), - .CE(start2_i_1_n_0), - .D(p_1_in__0[3]), + .CE(\bus2ip_addr_i[8]_i_1_n_0 ), + .D(\bus2ip_addr_i[3]_i_1_n_0 ), .Q(bus2ip_addr[5]), - .R(bus2ip_reset)); - FDRE \bus2ip_addr_i_reg[4] - (.C(s_axi_aclk), - .CE(start2_i_1_n_0), - .D(p_1_in__0[4]), - .Q(bus2ip_addr[4]), - .R(bus2ip_reset)); - FDRE \bus2ip_addr_i_reg[5] - (.C(s_axi_aclk), - .CE(start2_i_1_n_0), - .D(p_1_in__0[5]), - .Q(bus2ip_addr[3]), - .R(bus2ip_reset)); - FDRE \bus2ip_addr_i_reg[6] - (.C(s_axi_aclk), - .CE(start2_i_1_n_0), - .D(p_1_in__0[6]), - .Q(bus2ip_addr[2]), - .R(bus2ip_reset)); - FDRE \bus2ip_addr_i_reg[7] - (.C(s_axi_aclk), - .CE(start2_i_1_n_0), - .D(p_1_in__0[7]), - .Q(bus2ip_addr[1]), - .R(bus2ip_reset)); + .R(SR)); FDRE \bus2ip_addr_i_reg[8] (.C(s_axi_aclk), - .CE(start2_i_1_n_0), - .D(p_1_in__0[8]), + .CE(\bus2ip_addr_i[8]_i_1_n_0 ), + .D(\bus2ip_addr_i[8]_i_2_n_0 ), .Q(bus2ip_addr[0]), - .R(bus2ip_reset)); - (* SOFT_HLUTNM = "soft_lutpair4" *) + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair0" *) LUT3 #( - .INIT(8'h02)) + .INIT(8'h10)) bus2ip_rnw_i_i_1 - (.I0(s_axi_arvalid), - .I1(state[0]), - .I2(state[1]), + (.I0(state[0]), + .I1(state[1]), + .I2(s_axi_arvalid), .O(bus2ip_rnw_i06_out)); FDRE bus2ip_rnw_i_reg (.C(s_axi_aclk), - .CE(start2_i_1_n_0), + .CE(\bus2ip_addr_i[8]_i_1_n_0 ), .D(bus2ip_rnw_i06_out), - .Q(\Not_Dual.gpio_OE_reg[0] ), - .R(bus2ip_reset)); + .Q(\Not_Dual.gpio_Data_Out_reg[0] ), + .R(SR)); LUT5 #( .INIT(32'h3FFA000A)) is_read_i_1 (.I0(s_axi_arvalid), - .I1(\state[1]_i_2_n_0 ), - .I2(state[1]), - .I3(state[0]), + .I1(state1__2), + .I2(state[0]), + .I3(state[1]), .I4(is_read), .O(is_read_i_1_n_0)); FDRE is_read_reg @@ -4153,33 +2893,44 @@ module Arty_Z7_20_axi_gpio_shield_2_0_slave_attachment .CE(1'b1), .D(is_read_i_1_n_0), .Q(is_read), - .R(bus2ip_reset)); + .R(SR)); LUT6 #( - .INIT(64'h1000FFFF10000000)) + .INIT(64'h0040FFFF00400000)) is_write_i_1 - (.I0(state[1]), - .I1(s_axi_arvalid), + (.I0(s_axi_arvalid), + .I1(s_axi_awvalid), .I2(s_axi_wvalid), - .I3(s_axi_awvalid), + .I3(state[1]), .I4(is_write), .I5(is_write_reg_n_0), .O(is_write_i_1_n_0)); LUT6 #( .INIT(64'hF88800000000FFFF)) is_write_i_2 - (.I0(s_axi_bready), - .I1(s_axi_bvalid), - .I2(s_axi_rready), - .I3(s_axi_rvalid), - .I4(state[1]), - .I5(state[0]), + (.I0(s_axi_rvalid), + .I1(s_axi_rready), + .I2(s_axi_bvalid), + .I3(s_axi_bready), + .I4(state[0]), + .I5(state[1]), .O(is_write)); FDRE is_write_reg (.C(s_axi_aclk), .CE(1'b1), .D(is_write_i_1_n_0), .Q(is_write_reg_n_0), - .R(bus2ip_reset)); + .R(SR)); + LUT1 #( + .INIT(2'h1)) + rst_i_1 + (.I0(s_axi_aresetn), + .O(p_1_in)); + FDRE rst_reg + (.C(s_axi_aclk), + .CE(1'b1), + .D(p_1_in), + .Q(SR), + .R(1'b0)); LUT5 #( .INIT(32'h08FF0808)) s_axi_bvalid_i_i_1 @@ -4196,149 +2947,141 @@ module Arty_Z7_20_axi_gpio_shield_2_0_slave_attachment .CE(1'b1), .D(s_axi_bvalid_i_i_1_n_0), .Q(s_axi_bvalid), - .R(bus2ip_reset)); + .R(SR)); LUT2 #( .INIT(4'h2)) - \s_axi_rdata_i[31]_i_1 + \s_axi_rdata_i[15]_i_1 (.I0(state[0]), .I1(state[1]), - .O(s_axi_rdata_i)); + .O(\s_axi_rdata_i[15]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[0] (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [0]), + .CE(\s_axi_rdata_i[15]_i_1_n_0 ), + .D(\ip2bus_data_i_D1_reg[16] [0]), .Q(s_axi_rdata[0]), - .R(bus2ip_reset)); + .R(SR)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[10] (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [10]), + .CE(\s_axi_rdata_i[15]_i_1_n_0 ), + .D(\ip2bus_data_i_D1_reg[16] [10]), .Q(s_axi_rdata[10]), - .R(bus2ip_reset)); + .R(SR)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[11] (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [11]), + .CE(\s_axi_rdata_i[15]_i_1_n_0 ), + .D(\ip2bus_data_i_D1_reg[16] [11]), .Q(s_axi_rdata[11]), - .R(bus2ip_reset)); + .R(SR)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[12] (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [12]), + .CE(\s_axi_rdata_i[15]_i_1_n_0 ), + .D(\ip2bus_data_i_D1_reg[16] [12]), .Q(s_axi_rdata[12]), - .R(bus2ip_reset)); + .R(SR)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[13] (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [13]), + .CE(\s_axi_rdata_i[15]_i_1_n_0 ), + .D(\ip2bus_data_i_D1_reg[16] [13]), .Q(s_axi_rdata[13]), - .R(bus2ip_reset)); + .R(SR)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[14] (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [14]), + .CE(\s_axi_rdata_i[15]_i_1_n_0 ), + .D(\ip2bus_data_i_D1_reg[16] [14]), .Q(s_axi_rdata[14]), - .R(bus2ip_reset)); + .R(SR)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[15] (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [15]), + .CE(\s_axi_rdata_i[15]_i_1_n_0 ), + .D(\ip2bus_data_i_D1_reg[16] [15]), .Q(s_axi_rdata[15]), - .R(bus2ip_reset)); + .R(SR)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[1] (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [1]), + .CE(\s_axi_rdata_i[15]_i_1_n_0 ), + .D(\ip2bus_data_i_D1_reg[16] [1]), .Q(s_axi_rdata[1]), - .R(bus2ip_reset)); + .R(SR)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[2] (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [2]), + .CE(\s_axi_rdata_i[15]_i_1_n_0 ), + .D(\ip2bus_data_i_D1_reg[16] [2]), .Q(s_axi_rdata[2]), - .R(bus2ip_reset)); - FDRE #( - .INIT(1'b0)) - \s_axi_rdata_i_reg[31] - (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [16]), - .Q(s_axi_rdata[16]), - .R(bus2ip_reset)); + .R(SR)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[3] (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [3]), + .CE(\s_axi_rdata_i[15]_i_1_n_0 ), + .D(\ip2bus_data_i_D1_reg[16] [3]), .Q(s_axi_rdata[3]), - .R(bus2ip_reset)); + .R(SR)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[4] (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [4]), + .CE(\s_axi_rdata_i[15]_i_1_n_0 ), + .D(\ip2bus_data_i_D1_reg[16] [4]), .Q(s_axi_rdata[4]), - .R(bus2ip_reset)); + .R(SR)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[5] (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [5]), + .CE(\s_axi_rdata_i[15]_i_1_n_0 ), + .D(\ip2bus_data_i_D1_reg[16] [5]), .Q(s_axi_rdata[5]), - .R(bus2ip_reset)); + .R(SR)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[6] (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [6]), + .CE(\s_axi_rdata_i[15]_i_1_n_0 ), + .D(\ip2bus_data_i_D1_reg[16] [6]), .Q(s_axi_rdata[6]), - .R(bus2ip_reset)); + .R(SR)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[7] (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [7]), + .CE(\s_axi_rdata_i[15]_i_1_n_0 ), + .D(\ip2bus_data_i_D1_reg[16] [7]), .Q(s_axi_rdata[7]), - .R(bus2ip_reset)); + .R(SR)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[8] (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [8]), + .CE(\s_axi_rdata_i[15]_i_1_n_0 ), + .D(\ip2bus_data_i_D1_reg[16] [8]), .Q(s_axi_rdata[8]), - .R(bus2ip_reset)); + .R(SR)); FDRE #( .INIT(1'b0)) \s_axi_rdata_i_reg[9] (.C(s_axi_aclk), - .CE(s_axi_rdata_i), - .D(\ip2bus_data_i_D1_reg[0]_1 [9]), + .CE(\s_axi_rdata_i[15]_i_1_n_0 ), + .D(\ip2bus_data_i_D1_reg[16] [9]), .Q(s_axi_rdata[9]), - .R(bus2ip_reset)); + .R(SR)); LUT5 #( .INIT(32'h08FF0808)) s_axi_rvalid_i_i_1 @@ -4355,41 +3098,41 @@ module Arty_Z7_20_axi_gpio_shield_2_0_slave_attachment .CE(1'b1), .D(s_axi_rvalid_i_i_1_n_0), .Q(s_axi_rvalid), - .R(bus2ip_reset)); + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair1" *) LUT5 #( .INIT(32'h000000F8)) start2_i_1 (.I0(s_axi_awvalid), .I1(s_axi_wvalid), .I2(s_axi_arvalid), - .I3(state[0]), - .I4(state[1]), + .I3(state[1]), + .I4(state[0]), .O(start2_i_1_n_0)); FDRE start2_reg (.C(s_axi_aclk), .CE(1'b1), .D(start2_i_1_n_0), .Q(start2), - .R(bus2ip_reset)); + .R(SR)); LUT5 #( - .INIT(32'h0FFFAACC)) + .INIT(32'h77FC44FC)) \state[0]_i_1 - (.I0(s_axi_wready), - .I1(s_axi_arvalid), - .I2(\state[1]_i_2_n_0 ), + (.I0(state1__2), + .I1(state[0]), + .I2(s_axi_arvalid), .I3(state[1]), - .I4(state[0]), - .O(p_0_out__0[0])); - LUT6 #( - .INIT(64'h2E2E2E2ECCCCFFCC)) + .I4(s_axi_wready), + .O(p_0_out[0])); + LUT5 #( + .INIT(32'h5FFC50FC)) \state[1]_i_1 - (.I0(s_axi_arready), - .I1(state[1]), - .I2(\state[1]_i_2_n_0 ), - .I3(\state[1]_i_3_n_0 ), - .I4(s_axi_arvalid), - .I5(state[0]), - .O(p_0_out__0[1])); + (.I0(state1__2), + .I1(\state[1]_i_3_n_0 ), + .I2(state[1]), + .I3(state[0]), + .I4(s_axi_arready), + .O(p_0_out[1])); LUT4 #( .INIT(16'hF888)) \state[1]_i_2 @@ -4397,25 +3140,27 @@ module Arty_Z7_20_axi_gpio_shield_2_0_slave_attachment .I1(s_axi_bvalid), .I2(s_axi_rready), .I3(s_axi_rvalid), - .O(\state[1]_i_2_n_0 )); - LUT2 #( - .INIT(4'h8)) + .O(state1__2)); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT3 #( + .INIT(8'h08)) \state[1]_i_3 - (.I0(s_axi_awvalid), - .I1(s_axi_wvalid), + (.I0(s_axi_wvalid), + .I1(s_axi_awvalid), + .I2(s_axi_arvalid), .O(\state[1]_i_3_n_0 )); FDRE \state_reg[0] (.C(s_axi_aclk), .CE(1'b1), - .D(p_0_out__0[0]), + .D(p_0_out[0]), .Q(state[0]), - .R(bus2ip_reset)); + .R(SR)); FDRE \state_reg[1] (.C(s_axi_aclk), .CE(1'b1), - .D(p_0_out__0[1]), + .D(p_0_out[1]), .Q(state[1]), - .R(bus2ip_reset)); + .R(SR)); endmodule `ifndef GLBL `define GLBL diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0_sim_netlist.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0_sim_netlist.vhdl index 9f6e774..ed300f7 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0_sim_netlist.vhdl +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 --- Date : Fri Feb 24 16:00:40 2017 +-- Date : Sat Mar 04 18:53:03 2017 -- Host : WK73 running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim --- c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0_sim_netlist.vhdl +-- C:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0_sim_netlist.vhdl -- Design : Arty_Z7_20_axi_gpio_shield_2_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. @@ -16,1132 +16,524 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20_axi_gpio_shield_2_0_address_decoder is port ( - \ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC; - \Not_Dual.gpio_Data_Out_reg[15]\ : out STD_LOGIC; - \ip_irpt_enable_reg_reg[0]\ : out STD_LOGIC; + \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arready : out STD_LOGIC; s_axi_wready : out STD_LOGIC; - D : out STD_LOGIC_VECTOR ( 15 downto 0 ); - \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]\ : out STD_LOGIC; GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 ); - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - \Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - \ip2bus_data_i_D1_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); - intr2bus_rdack0 : out STD_LOGIC; - irpt_rdack : out STD_LOGIC; - irpt_wrack : out STD_LOGIC; - interrupt_wrce_strb : out STD_LOGIC; - Read_Reg_Rst : out STD_LOGIC; - \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ : out STD_LOGIC; - intr_rd_ce_or_reduce : out STD_LOGIC; - \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC; - intr_wr_ce_or_reduce : out STD_LOGIC; - \ip_irpt_enable_reg_reg[0]_0\ : out STD_LOGIC; - ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC; - start2 : in STD_LOGIC; + \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31]\ : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 15 downto 0 ); + \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[16]\ : out STD_LOGIC; s_axi_aclk : in STD_LOGIC; - s_axi_aresetn : in STD_LOGIC; - Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); - is_read : in STD_LOGIC; + rst_reg : in STD_LOGIC; + bus2ip_rnw_i_reg : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); ip2bus_rdack_i_D1 : in STD_LOGIC; - is_write_reg : in STD_LOGIC; + is_read : in STD_LOGIC; + \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); ip2bus_wrack_i_D1 : in STD_LOGIC; - s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - \bus2ip_addr_i_reg[8]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); - gpio_io_t : in STD_LOGIC_VECTOR ( 15 downto 0 ); + is_write_reg : in STD_LOGIC; \Not_Dual.gpio_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); - bus2ip_rnw_i_reg : in STD_LOGIC; - bus2ip_reset : in STD_LOGIC; - p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); - irpt_rdack_d1 : in STD_LOGIC; - irpt_wrack_d1 : in STD_LOGIC; - ip2bus_data : in STD_LOGIC_VECTOR ( 0 to 0 ); - p_3_in : in STD_LOGIC_VECTOR ( 0 to 0 ); - p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 ); - GPIO_xferAck_i : in STD_LOGIC; + gpio_io_t : in STD_LOGIC_VECTOR ( 15 downto 0 ); + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + start2_reg : in STD_LOGIC; + s_axi_aresetn : in STD_LOGIC; gpio_xferAck_Reg : in STD_LOGIC; - ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC; - ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC + GPIO_xferAck_i : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of Arty_Z7_20_axi_gpio_shield_2_0_address_decoder : entity is "address_decoder"; end Arty_Z7_20_axi_gpio_shield_2_0_address_decoder; architecture STRUCTURE of Arty_Z7_20_axi_gpio_shield_2_0_address_decoder is - signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC; - signal \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\ : STD_LOGIC; - signal \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\ : STD_LOGIC; - signal \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\ : STD_LOGIC; - signal \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ : STD_LOGIC; - signal \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\ : STD_LOGIC; - signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\ : STD_LOGIC; - signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\ : STD_LOGIC; - signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\ : STD_LOGIC; - signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\ : STD_LOGIC; - signal \^not_dual.gpio_data_out_reg[15]\ : STD_LOGIC; - signal \^ip2bus_data_i_d1_reg[0]\ : STD_LOGIC; - signal \^ip_irpt_enable_reg_reg[0]\ : STD_LOGIC; - signal p_10_in : STD_LOGIC; - signal p_10_out : STD_LOGIC; - signal p_11_in : STD_LOGIC; - signal p_11_out : STD_LOGIC; - signal p_12_in : STD_LOGIC; - signal p_12_out : STD_LOGIC; - signal p_13_in : STD_LOGIC; - signal p_13_out : STD_LOGIC; - signal p_14_in : STD_LOGIC; - signal p_14_out : STD_LOGIC; - signal p_15_in : STD_LOGIC; - signal p_15_out : STD_LOGIC; - signal p_16_in : STD_LOGIC; - signal p_2_in : STD_LOGIC; - signal p_3_in_0 : STD_LOGIC; - signal p_4_in : STD_LOGIC; - signal p_4_out : STD_LOGIC; - signal p_5_in : STD_LOGIC; - signal p_5_out : STD_LOGIC; - signal p_6_in : STD_LOGIC; - signal p_6_out : STD_LOGIC; - signal p_7_in : STD_LOGIC; - signal p_7_out : STD_LOGIC; - signal p_8_out : STD_LOGIC; - signal p_9_in : STD_LOGIC; - signal p_9_out : STD_LOGIC; - signal pselect_hit_i_1 : STD_LOGIC; + signal \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\ : STD_LOGIC; + signal \^mem_decode_gen[0].cs_out_i_reg[0]_0\ : STD_LOGIC; signal \^s_axi_arready\ : STD_LOGIC; signal \^s_axi_wready\ : STD_LOGIC; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_i_1\ : label is "soft_lutpair0"; - attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_i_1\ : label is "soft_lutpair1"; - attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_1\ : label is "soft_lutpair1"; - attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_1\ : label is "soft_lutpair0"; - attribute SOFT_HLUTNM of intr2bus_wrack_i_1 : label is "soft_lutpair2"; - attribute SOFT_HLUTNM of \ip2bus_data_i_D1[0]_i_1\ : label is "soft_lutpair3"; - attribute SOFT_HLUTNM of irpt_rdack_d1_i_1 : label is "soft_lutpair2"; - attribute SOFT_HLUTNM of irpt_wrack_d1_i_1 : label is "soft_lutpair3"; begin - \Not_Dual.gpio_Data_Out_reg[15]\ <= \^not_dual.gpio_data_out_reg[15]\; - \ip2bus_data_i_D1_reg[0]\ <= \^ip2bus_data_i_d1_reg[0]\; - \ip_irpt_enable_reg_reg[0]\ <= \^ip_irpt_enable_reg_reg[0]\; + \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ <= \^mem_decode_gen[0].cs_out_i_reg[0]_0\; s_axi_arready <= \^s_axi_arready\; s_axi_wready <= \^s_axi_wready\; -Bus_RNW_reg_i_1: unisim.vcomponents.LUT3 +\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"B8" + INIT => X"000000E0" ) port map ( - I0 => bus2ip_rnw_i_reg, - I1 => start2, - I2 => \^ip_irpt_enable_reg_reg[0]\, - O => Bus_RNW_reg_i_1_n_0 + I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I1 => start2_reg, + I2 => s_axi_aresetn, + I3 => \^s_axi_arready\, + I4 => \^s_axi_wready\, + O => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\ ); -Bus_RNW_reg_reg: unisim.vcomponents.FDRE +\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => Bus_RNW_reg_i_1_n_0, - Q => \^ip_irpt_enable_reg_reg[0]\, + D => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\, + Q => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, R => '0' ); -\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0040000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(3), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \bus2ip_addr_i_reg[8]\(2), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => p_9_out - ); -\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => p_9_out, - Q => p_10_in, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"4000000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(3), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \bus2ip_addr_i_reg[8]\(2), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => p_8_out - ); -\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => p_8_out, - Q => p_9_in, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0004000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(1), - I1 => \bus2ip_addr_i_reg[8]\(3), - I2 => \bus2ip_addr_i_reg[8]\(2), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => p_7_out - ); -\GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => p_7_out, - Q => \^ip2bus_data_i_d1_reg[0]\, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0400000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(1), - I1 => \bus2ip_addr_i_reg[8]\(3), - I2 => \bus2ip_addr_i_reg[8]\(2), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => p_6_out - ); -\GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => p_6_out, - Q => p_7_in, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0008000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(1), - I1 => \bus2ip_addr_i_reg[8]\(3), - I2 => \bus2ip_addr_i_reg[8]\(2), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => p_5_out - ); -\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => p_5_out, - Q => p_6_in, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0800000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(1), - I1 => \bus2ip_addr_i_reg[8]\(3), - I2 => \bus2ip_addr_i_reg[8]\(2), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => p_4_out - ); -\GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => p_4_out, - Q => p_5_in, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0008000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(3), - I1 => \bus2ip_addr_i_reg[8]\(2), - I2 => \bus2ip_addr_i_reg[8]\(1), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\, - Q => p_4_in, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0800000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(3), - I1 => \bus2ip_addr_i_reg[8]\(2), - I2 => \bus2ip_addr_i_reg[8]\(1), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\, - Q => p_3_in_0, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0080000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(3), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \bus2ip_addr_i_reg[8]\(2), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\, - Q => p_2_in, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"FD" - ) - port map ( - I0 => s_axi_aresetn, - I1 => \^s_axi_arready\, - I2 => \^s_axi_wready\, - O => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"8000000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(3), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \bus2ip_addr_i_reg[8]\(2), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => p_15_out - ); -\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg[19]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => p_15_out, - Q => \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0001000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(1), - I1 => \bus2ip_addr_i_reg[8]\(2), - I2 => \bus2ip_addr_i_reg[8]\(3), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\, - Q => p_16_in, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0100000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(1), - I1 => \bus2ip_addr_i_reg[8]\(2), - I2 => \bus2ip_addr_i_reg[8]\(3), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => p_14_out - ); -\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => p_14_out, - Q => p_15_in, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0002000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(1), - I1 => \bus2ip_addr_i_reg[8]\(2), - I2 => \bus2ip_addr_i_reg[8]\(3), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => p_13_out - ); -\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => p_13_out, - Q => p_14_in, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0200000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(1), - I1 => \bus2ip_addr_i_reg[8]\(2), - I2 => \bus2ip_addr_i_reg[8]\(3), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => p_12_out - ); -\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => p_12_out, - Q => p_13_in, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0004000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(3), - I1 => \bus2ip_addr_i_reg[8]\(2), - I2 => \bus2ip_addr_i_reg[8]\(1), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => p_11_out - ); -\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => p_11_out, - Q => p_12_in, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0400000000000000" - ) - port map ( - I0 => \bus2ip_addr_i_reg[8]\(3), - I1 => \bus2ip_addr_i_reg[8]\(2), - I2 => \bus2ip_addr_i_reg[8]\(1), - I3 => \bus2ip_addr_i_reg[8]\(0), - I4 => \bus2ip_addr_i_reg[8]\(6), - I5 => start2, - O => p_10_out - ); -\GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => p_10_out, - Q => p_11_in, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); -\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"FE00" - ) - port map ( - I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\, - I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\, - I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\, - I3 => \^ip_irpt_enable_reg_reg[0]\, - O => intr_rd_ce_or_reduce - ); -\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"00FE0000" - ) - port map ( - I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\, - I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\, - I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\, - I3 => ip2Bus_RdAck_intr_reg_hole_d1, - I4 => \^ip_irpt_enable_reg_reg[0]\, - O => \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ - ); -\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"00FE" - ) - port map ( - I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\, - I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\, - I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\, - I3 => \^ip_irpt_enable_reg_reg[0]\, - O => intr_wr_ce_or_reduce - ); -\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFFFFFFE" - ) - port map ( - I0 => p_16_in, - I1 => p_2_in, - I2 => \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\, - I3 => p_14_in, - I4 => p_15_in, - O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\ - ); -\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3\: unisim.vcomponents.LUT4 - generic map( - INIT => X"FFFE" - ) - port map ( - I0 => p_12_in, - I1 => p_13_in, - I2 => p_10_in, - I3 => p_11_in, - O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\ - ); -\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4\: unisim.vcomponents.LUT4 - generic map( - INIT => X"FFFE" - ) - port map ( - I0 => p_5_in, - I1 => p_7_in, - I2 => p_3_in_0, - I3 => p_4_in, - O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\ - ); -\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"000000FE" - ) - port map ( - I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\, - I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\, - I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\, - I3 => \^ip_irpt_enable_reg_reg[0]\, - I4 => ip2Bus_WrAck_intr_reg_hole_d1, - O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ - ); -\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000000000000002" - ) - port map ( - I0 => start2, - I1 => \bus2ip_addr_i_reg[8]\(6), - I2 => \bus2ip_addr_i_reg[8]\(4), - I3 => \bus2ip_addr_i_reg[8]\(5), - I4 => \bus2ip_addr_i_reg[8]\(3), - I5 => \bus2ip_addr_i_reg[8]\(2), - O => pselect_hit_i_1 - ); -\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2, - D => pselect_hit_i_1, - Q => \^not_dual.gpio_data_out_reg[15]\, - R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ - ); \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i[16]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000A0000000C0000" + INIT => X"000000E000000020" ) port map ( - I0 => gpio_io_t(15), - I1 => \Not_Dual.gpio_Data_In_reg[0]\(15), - I2 => \bus2ip_addr_i_reg[8]\(6), - I3 => \bus2ip_addr_i_reg[8]\(1), - I4 => \^not_dual.gpio_data_out_reg[15]\, - I5 => \bus2ip_addr_i_reg[8]\(0), + I0 => \Not_Dual.gpio_Data_In_reg[0]\(15), + I1 => Q(0), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(1), + I5 => gpio_io_t(15), O => GPIO_DBus_i(0) ); \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i[26]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000A0000000C0000" + INIT => X"000000E000000020" ) port map ( - I0 => gpio_io_t(5), - I1 => \Not_Dual.gpio_Data_In_reg[0]\(5), - I2 => \bus2ip_addr_i_reg[8]\(6), - I3 => \bus2ip_addr_i_reg[8]\(1), - I4 => \^not_dual.gpio_data_out_reg[15]\, - I5 => \bus2ip_addr_i_reg[8]\(0), + I0 => \Not_Dual.gpio_Data_In_reg[0]\(5), + I1 => Q(0), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(1), + I5 => gpio_io_t(5), O => \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\ ); \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i[27]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000A0000000C0000" + INIT => X"000000E000000020" ) port map ( - I0 => gpio_io_t(4), - I1 => \Not_Dual.gpio_Data_In_reg[0]\(4), - I2 => \bus2ip_addr_i_reg[8]\(6), - I3 => \bus2ip_addr_i_reg[8]\(1), - I4 => \^not_dual.gpio_data_out_reg[15]\, - I5 => \bus2ip_addr_i_reg[8]\(0), + I0 => \Not_Dual.gpio_Data_In_reg[0]\(4), + I1 => Q(0), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(1), + I5 => gpio_io_t(4), O => \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\ ); \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i[28]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000A0000000C0000" + INIT => X"000000E000000020" ) port map ( - I0 => gpio_io_t(3), - I1 => \Not_Dual.gpio_Data_In_reg[0]\(3), - I2 => \bus2ip_addr_i_reg[8]\(6), - I3 => \bus2ip_addr_i_reg[8]\(1), - I4 => \^not_dual.gpio_data_out_reg[15]\, - I5 => \bus2ip_addr_i_reg[8]\(0), + I0 => \Not_Dual.gpio_Data_In_reg[0]\(3), + I1 => Q(0), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(1), + I5 => gpio_io_t(3), O => \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\ ); \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i[29]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000A0000000C0000" + INIT => X"000000E000000020" ) port map ( - I0 => gpio_io_t(2), - I1 => \Not_Dual.gpio_Data_In_reg[0]\(2), - I2 => \bus2ip_addr_i_reg[8]\(6), - I3 => \bus2ip_addr_i_reg[8]\(1), - I4 => \^not_dual.gpio_data_out_reg[15]\, - I5 => \bus2ip_addr_i_reg[8]\(0), + I0 => \Not_Dual.gpio_Data_In_reg[0]\(2), + I1 => Q(0), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(1), + I5 => gpio_io_t(2), O => \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]\ ); \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i[30]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000A0000000C0000" + INIT => X"000000E000000020" ) port map ( - I0 => gpio_io_t(1), - I1 => \Not_Dual.gpio_Data_In_reg[0]\(1), - I2 => \bus2ip_addr_i_reg[8]\(6), - I3 => \bus2ip_addr_i_reg[8]\(1), - I4 => \^not_dual.gpio_data_out_reg[15]\, - I5 => \bus2ip_addr_i_reg[8]\(0), + I0 => \Not_Dual.gpio_Data_In_reg[0]\(1), + I1 => Q(0), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(1), + I5 => gpio_io_t(1), O => \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]\ ); \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i[31]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"FFDF" + INIT => X"FFF7" ) port map ( - I0 => \^not_dual.gpio_data_out_reg[15]\, - I1 => GPIO_xferAck_i, - I2 => bus2ip_rnw_i_reg, - I3 => gpio_xferAck_Reg, - O => Read_Reg_Rst + I0 => bus2ip_rnw_i_reg, + I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I2 => gpio_xferAck_Reg, + I3 => GPIO_xferAck_i, + O => \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[16]\ ); \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i[31]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"000A0000000C0000" + INIT => X"000000E000000020" ) port map ( - I0 => gpio_io_t(0), - I1 => \Not_Dual.gpio_Data_In_reg[0]\(0), - I2 => \bus2ip_addr_i_reg[8]\(6), - I3 => \bus2ip_addr_i_reg[8]\(1), - I4 => \^not_dual.gpio_data_out_reg[15]\, - I5 => \bus2ip_addr_i_reg[8]\(0), + I0 => \Not_Dual.gpio_Data_In_reg[0]\(0), + I1 => Q(0), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(1), + I5 => gpio_io_t(0), O => \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31]\ ); \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i[17]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000A0000000C0000" + INIT => X"000000E000000020" ) port map ( - I0 => gpio_io_t(14), - I1 => \Not_Dual.gpio_Data_In_reg[0]\(14), - I2 => \bus2ip_addr_i_reg[8]\(6), - I3 => \bus2ip_addr_i_reg[8]\(1), - I4 => \^not_dual.gpio_data_out_reg[15]\, - I5 => \bus2ip_addr_i_reg[8]\(0), + I0 => \Not_Dual.gpio_Data_In_reg[0]\(14), + I1 => Q(0), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(1), + I5 => gpio_io_t(14), O => \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]\ ); \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i[18]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000A0000000C0000" + INIT => X"000000E000000020" ) port map ( - I0 => gpio_io_t(13), - I1 => \Not_Dual.gpio_Data_In_reg[0]\(13), - I2 => \bus2ip_addr_i_reg[8]\(6), - I3 => \bus2ip_addr_i_reg[8]\(1), - I4 => \^not_dual.gpio_data_out_reg[15]\, - I5 => \bus2ip_addr_i_reg[8]\(0), + I0 => \Not_Dual.gpio_Data_In_reg[0]\(13), + I1 => Q(0), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(1), + I5 => gpio_io_t(13), O => \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]\ ); \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i[19]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000A0000000C0000" + INIT => X"000000E000000020" ) port map ( - I0 => gpio_io_t(12), - I1 => \Not_Dual.gpio_Data_In_reg[0]\(12), - I2 => \bus2ip_addr_i_reg[8]\(6), - I3 => \bus2ip_addr_i_reg[8]\(1), - I4 => \^not_dual.gpio_data_out_reg[15]\, - I5 => \bus2ip_addr_i_reg[8]\(0), + I0 => \Not_Dual.gpio_Data_In_reg[0]\(12), + I1 => Q(0), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(1), + I5 => gpio_io_t(12), O => \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]\ ); \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i[20]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000A0000000C0000" + INIT => X"000000E000000020" ) port map ( - I0 => gpio_io_t(11), - I1 => \Not_Dual.gpio_Data_In_reg[0]\(11), - I2 => \bus2ip_addr_i_reg[8]\(6), - I3 => \bus2ip_addr_i_reg[8]\(1), - I4 => \^not_dual.gpio_data_out_reg[15]\, - I5 => \bus2ip_addr_i_reg[8]\(0), + I0 => \Not_Dual.gpio_Data_In_reg[0]\(11), + I1 => Q(0), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(1), + I5 => gpio_io_t(11), O => \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]\ ); \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i[21]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000A0000000C0000" + INIT => X"000000E000000020" ) port map ( - I0 => gpio_io_t(10), - I1 => \Not_Dual.gpio_Data_In_reg[0]\(10), - I2 => \bus2ip_addr_i_reg[8]\(6), - I3 => \bus2ip_addr_i_reg[8]\(1), - I4 => \^not_dual.gpio_data_out_reg[15]\, - I5 => \bus2ip_addr_i_reg[8]\(0), + I0 => \Not_Dual.gpio_Data_In_reg[0]\(10), + I1 => Q(0), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(1), + I5 => gpio_io_t(10), O => \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]\ ); \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i[22]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000A0000000C0000" + INIT => X"000000E000000020" ) port map ( - I0 => gpio_io_t(9), - I1 => \Not_Dual.gpio_Data_In_reg[0]\(9), - I2 => \bus2ip_addr_i_reg[8]\(6), - I3 => \bus2ip_addr_i_reg[8]\(1), - I4 => \^not_dual.gpio_data_out_reg[15]\, - I5 => \bus2ip_addr_i_reg[8]\(0), + I0 => \Not_Dual.gpio_Data_In_reg[0]\(9), + I1 => Q(0), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(1), + I5 => gpio_io_t(9), O => \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]\ ); \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i[23]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000A0000000C0000" + INIT => X"000000E000000020" ) port map ( - I0 => gpio_io_t(8), - I1 => \Not_Dual.gpio_Data_In_reg[0]\(8), - I2 => \bus2ip_addr_i_reg[8]\(6), - I3 => \bus2ip_addr_i_reg[8]\(1), - I4 => \^not_dual.gpio_data_out_reg[15]\, - I5 => \bus2ip_addr_i_reg[8]\(0), + I0 => \Not_Dual.gpio_Data_In_reg[0]\(8), + I1 => Q(0), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(1), + I5 => gpio_io_t(8), O => \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\ ); \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i[24]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000A0000000C0000" + INIT => X"000000E000000020" ) port map ( - I0 => gpio_io_t(7), - I1 => \Not_Dual.gpio_Data_In_reg[0]\(7), - I2 => \bus2ip_addr_i_reg[8]\(6), - I3 => \bus2ip_addr_i_reg[8]\(1), - I4 => \^not_dual.gpio_data_out_reg[15]\, - I5 => \bus2ip_addr_i_reg[8]\(0), + I0 => \Not_Dual.gpio_Data_In_reg[0]\(7), + I1 => Q(0), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(1), + I5 => gpio_io_t(7), O => \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\ ); \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i[25]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000A0000000C0000" + INIT => X"000000E000000020" ) port map ( - I0 => gpio_io_t(6), - I1 => \Not_Dual.gpio_Data_In_reg[0]\(6), - I2 => \bus2ip_addr_i_reg[8]\(6), - I3 => \bus2ip_addr_i_reg[8]\(1), - I4 => \^not_dual.gpio_data_out_reg[15]\, - I5 => \bus2ip_addr_i_reg[8]\(0), + I0 => \Not_Dual.gpio_Data_In_reg[0]\(6), + I1 => Q(0), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(1), + I5 => gpio_io_t(6), O => \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\ ); \Not_Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFF00000100" + INIT => X"AAAAAAAAAAAAABAA" ) port map ( - I0 => bus2ip_rnw_i_reg, - I1 => \bus2ip_addr_i_reg[8]\(6), - I2 => \bus2ip_addr_i_reg[8]\(1), - I3 => \^not_dual.gpio_data_out_reg[15]\, - I4 => \bus2ip_addr_i_reg[8]\(0), - I5 => bus2ip_reset, - O => \Not_Dual.gpio_Data_Out_reg[0]\(0) + I0 => rst_reg, + I1 => bus2ip_rnw_i_reg, + I2 => Q(0), + I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I4 => Q(2), + I5 => Q(1), + O => E(0) ); \Not_Dual.gpio_Data_Out[0]_i_2\: unisim.vcomponents.LUT4 generic map( - INIT => X"BA8A" + INIT => X"CCAC" ) port map ( - I0 => s_axi_wdata(31), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \^not_dual.gpio_data_out_reg[15]\, - I3 => s_axi_wdata(15), + I0 => s_axi_wdata(15), + I1 => s_axi_wdata(31), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(1), O => D(15) ); \Not_Dual.gpio_Data_Out[10]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"BA8A" + INIT => X"CCAC" ) port map ( - I0 => s_axi_wdata(21), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \^not_dual.gpio_data_out_reg[15]\, - I3 => s_axi_wdata(5), + I0 => s_axi_wdata(5), + I1 => s_axi_wdata(21), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(1), O => D(5) ); \Not_Dual.gpio_Data_Out[11]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"BA8A" + INIT => X"CCAC" ) port map ( - I0 => s_axi_wdata(20), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \^not_dual.gpio_data_out_reg[15]\, - I3 => s_axi_wdata(4), + I0 => s_axi_wdata(4), + I1 => s_axi_wdata(20), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(1), O => D(4) ); \Not_Dual.gpio_Data_Out[12]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"BA8A" + INIT => X"CCAC" ) port map ( - I0 => s_axi_wdata(19), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \^not_dual.gpio_data_out_reg[15]\, - I3 => s_axi_wdata(3), + I0 => s_axi_wdata(3), + I1 => s_axi_wdata(19), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(1), O => D(3) ); \Not_Dual.gpio_Data_Out[13]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"BA8A" + INIT => X"CCAC" ) port map ( - I0 => s_axi_wdata(18), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \^not_dual.gpio_data_out_reg[15]\, - I3 => s_axi_wdata(2), + I0 => s_axi_wdata(2), + I1 => s_axi_wdata(18), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(1), O => D(2) ); \Not_Dual.gpio_Data_Out[14]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"BA8A" + INIT => X"CCAC" ) port map ( - I0 => s_axi_wdata(17), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \^not_dual.gpio_data_out_reg[15]\, - I3 => s_axi_wdata(1), + I0 => s_axi_wdata(1), + I1 => s_axi_wdata(17), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(1), O => D(1) ); \Not_Dual.gpio_Data_Out[15]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"BA8A" + INIT => X"CCAC" ) port map ( - I0 => s_axi_wdata(16), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \^not_dual.gpio_data_out_reg[15]\, - I3 => s_axi_wdata(0), + I0 => s_axi_wdata(0), + I1 => s_axi_wdata(16), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(1), O => D(0) ); \Not_Dual.gpio_Data_Out[1]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"BA8A" + INIT => X"CCAC" ) port map ( - I0 => s_axi_wdata(30), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \^not_dual.gpio_data_out_reg[15]\, - I3 => s_axi_wdata(14), + I0 => s_axi_wdata(14), + I1 => s_axi_wdata(30), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(1), O => D(14) ); \Not_Dual.gpio_Data_Out[2]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"BA8A" + INIT => X"CCAC" ) port map ( - I0 => s_axi_wdata(29), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \^not_dual.gpio_data_out_reg[15]\, - I3 => s_axi_wdata(13), + I0 => s_axi_wdata(13), + I1 => s_axi_wdata(29), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(1), O => D(13) ); \Not_Dual.gpio_Data_Out[3]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"BA8A" + INIT => X"CCAC" ) port map ( - I0 => s_axi_wdata(28), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \^not_dual.gpio_data_out_reg[15]\, - I3 => s_axi_wdata(12), + I0 => s_axi_wdata(12), + I1 => s_axi_wdata(28), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(1), O => D(12) ); \Not_Dual.gpio_Data_Out[4]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"BA8A" + INIT => X"CCAC" ) port map ( - I0 => s_axi_wdata(27), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \^not_dual.gpio_data_out_reg[15]\, - I3 => s_axi_wdata(11), + I0 => s_axi_wdata(11), + I1 => s_axi_wdata(27), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(1), O => D(11) ); \Not_Dual.gpio_Data_Out[5]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"BA8A" + INIT => X"CCAC" ) port map ( - I0 => s_axi_wdata(26), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \^not_dual.gpio_data_out_reg[15]\, - I3 => s_axi_wdata(10), + I0 => s_axi_wdata(10), + I1 => s_axi_wdata(26), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(1), O => D(10) ); \Not_Dual.gpio_Data_Out[6]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"BA8A" + INIT => X"CCAC" ) port map ( - I0 => s_axi_wdata(25), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \^not_dual.gpio_data_out_reg[15]\, - I3 => s_axi_wdata(9), + I0 => s_axi_wdata(9), + I1 => s_axi_wdata(25), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(1), O => D(9) ); \Not_Dual.gpio_Data_Out[7]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"BA8A" + INIT => X"CCAC" ) port map ( - I0 => s_axi_wdata(24), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \^not_dual.gpio_data_out_reg[15]\, - I3 => s_axi_wdata(8), + I0 => s_axi_wdata(8), + I1 => s_axi_wdata(24), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(1), O => D(8) ); \Not_Dual.gpio_Data_Out[8]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"BA8A" + INIT => X"CCAC" ) port map ( - I0 => s_axi_wdata(23), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \^not_dual.gpio_data_out_reg[15]\, - I3 => s_axi_wdata(7), + I0 => s_axi_wdata(7), + I1 => s_axi_wdata(23), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(1), O => D(7) ); \Not_Dual.gpio_Data_Out[9]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"BA8A" + INIT => X"CCAC" ) port map ( - I0 => s_axi_wdata(22), - I1 => \bus2ip_addr_i_reg[8]\(1), - I2 => \^not_dual.gpio_data_out_reg[15]\, - I3 => s_axi_wdata(6), + I0 => s_axi_wdata(6), + I1 => s_axi_wdata(22), + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(1), O => D(6) ); \Not_Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFF01000000" - ) - port map ( - I0 => bus2ip_rnw_i_reg, - I1 => \bus2ip_addr_i_reg[8]\(6), - I2 => \bus2ip_addr_i_reg[8]\(1), - I3 => \^not_dual.gpio_data_out_reg[15]\, - I4 => \bus2ip_addr_i_reg[8]\(0), - I5 => bus2ip_reset, - O => E(0) - ); -intr2bus_rdack_i_1: unisim.vcomponents.LUT5 - generic map( - INIT => X"44444440" - ) - port map ( - I0 => irpt_rdack_d1, - I1 => \^ip_irpt_enable_reg_reg[0]\, - I2 => p_9_in, - I3 => \^ip2bus_data_i_d1_reg[0]\, - I4 => p_6_in, - O => intr2bus_rdack0 - ); -intr2bus_wrack_i_1: unisim.vcomponents.LUT5 - generic map( - INIT => X"000000FE" - ) - port map ( - I0 => p_9_in, - I1 => \^ip2bus_data_i_d1_reg[0]\, - I2 => p_6_in, - I3 => \^ip_irpt_enable_reg_reg[0]\, - I4 => irpt_wrack_d1, - O => interrupt_wrce_strb - ); -\ip2bus_data_i_D1[0]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"00000080" - ) - port map ( - I0 => p_0_in(0), - I1 => p_9_in, - I2 => \^ip_irpt_enable_reg_reg[0]\, - I3 => p_6_in, - I4 => \^ip2bus_data_i_d1_reg[0]\, - O => \ip2bus_data_i_D1_reg[0]_0\(1) - ); -\ip2bus_data_i_D1[31]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"EEEEAAAAFAAAAAAA" - ) - port map ( - I0 => ip2bus_data(0), - I1 => p_3_in(0), - I2 => p_1_in(0), - I3 => p_6_in, - I4 => \^ip_irpt_enable_reg_reg[0]\, - I5 => \^ip2bus_data_i_d1_reg[0]\, - O => \ip2bus_data_i_D1_reg[0]_0\(0) - ); -\ip_irpt_enable_reg[0]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"FB08" - ) - port map ( - I0 => s_axi_wdata(0), - I1 => p_6_in, - I2 => \^ip_irpt_enable_reg_reg[0]\, - I3 => p_1_in(0), - O => \ip_irpt_enable_reg_reg[0]_0\ - ); -ipif_glbl_irpt_enable_reg_i_1: unisim.vcomponents.LUT4 - generic map( - INIT => X"FB08" - ) - port map ( - I0 => s_axi_wdata(31), - I1 => p_9_in, - I2 => \^ip_irpt_enable_reg_reg[0]\, - I3 => p_0_in(0), - O => ipif_glbl_irpt_enable_reg_reg - ); -irpt_rdack_d1_i_1: unisim.vcomponents.LUT4 - generic map( - INIT => X"FE00" - ) - port map ( - I0 => p_9_in, - I1 => \^ip2bus_data_i_d1_reg[0]\, - I2 => p_6_in, - I3 => \^ip_irpt_enable_reg_reg[0]\, - O => irpt_rdack - ); -irpt_wrack_d1_i_1: unisim.vcomponents.LUT4 - generic map( - INIT => X"00FE" + INIT => X"AAAAAAAAAABAAAAA" ) port map ( - I0 => p_9_in, - I1 => \^ip2bus_data_i_d1_reg[0]\, - I2 => p_6_in, - I3 => \^ip_irpt_enable_reg_reg[0]\, - O => irpt_wrack + I0 => rst_reg, + I1 => bus2ip_rnw_i_reg, + I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, + I3 => Q(2), + I4 => Q(0), + I5 => Q(1), + O => \Not_Dual.gpio_OE_reg[0]\(0) ); s_axi_arready_INST_0: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFF00020000" + INIT => X"AAAAAAAAAAAEAAAA" ) port map ( - I0 => Q(3), - I1 => Q(2), - I2 => Q(1), - I3 => Q(0), - I4 => is_read, - I5 => ip2bus_rdack_i_D1, + I0 => ip2bus_rdack_i_D1, + I1 => is_read, + I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2), + I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1), + I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3), + I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0), O => \^s_axi_arready\ ); s_axi_wready_INST_0: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFF00020000" + INIT => X"AAAAAAAAAAAEAAAA" ) port map ( - I0 => Q(3), - I1 => Q(2), - I2 => Q(1), - I3 => Q(0), - I4 => is_write_reg, - I5 => ip2bus_wrack_i_D1, + I0 => ip2bus_wrack_i_D1, + I1 => is_write_reg, + I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2), + I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1), + I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3), + I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0), O => \^s_axi_wready\ ); end STRUCTURE; @@ -1151,9 +543,7 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20_axi_gpio_shield_2_0_cdc_sync is port ( - D : out STD_LOGIC_VECTOR ( 15 downto 0 ); scndry_vect_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); - Q : in STD_LOGIC_VECTOR ( 15 downto 0 ); gpio_io_i : in STD_LOGIC_VECTOR ( 15 downto 0 ); s_axi_aclk : in STD_LOGIC ); @@ -1210,7 +600,6 @@ architecture STRUCTURE of Arty_Z7_20_axi_gpio_shield_2_0_cdc_sync is signal s_level_out_bus_d3_7 : STD_LOGIC; signal s_level_out_bus_d3_8 : STD_LOGIC; signal s_level_out_bus_d3_9 : STD_LOGIC; - signal \^scndry_vect_out\ : STD_LOGIC_VECTOR ( 15 downto 0 ); attribute ASYNC_REG : boolean; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM : string; @@ -1407,7 +796,6 @@ architecture STRUCTURE of Arty_Z7_20_axi_gpio_shield_2_0_cdc_sync is attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; begin - scndry_vect_out(15 downto 0) <= \^scndry_vect_out\(15 downto 0); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE generic map( INIT => '0' @@ -1768,7 +1156,7 @@ begin C => s_axi_aclk, CE => '1', D => s_level_out_bus_d3_0, - Q => \^scndry_vect_out\(0), + Q => scndry_vect_out(0), R => '0' ); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE @@ -1779,7 +1167,7 @@ begin C => s_axi_aclk, CE => '1', D => s_level_out_bus_d3_10, - Q => \^scndry_vect_out\(10), + Q => scndry_vect_out(10), R => '0' ); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE @@ -1790,7 +1178,7 @@ begin C => s_axi_aclk, CE => '1', D => s_level_out_bus_d3_11, - Q => \^scndry_vect_out\(11), + Q => scndry_vect_out(11), R => '0' ); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE @@ -1801,7 +1189,7 @@ begin C => s_axi_aclk, CE => '1', D => s_level_out_bus_d3_12, - Q => \^scndry_vect_out\(12), + Q => scndry_vect_out(12), R => '0' ); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE @@ -1812,7 +1200,7 @@ begin C => s_axi_aclk, CE => '1', D => s_level_out_bus_d3_13, - Q => \^scndry_vect_out\(13), + Q => scndry_vect_out(13), R => '0' ); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE @@ -1823,7 +1211,7 @@ begin C => s_axi_aclk, CE => '1', D => s_level_out_bus_d3_14, - Q => \^scndry_vect_out\(14), + Q => scndry_vect_out(14), R => '0' ); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE @@ -1834,7 +1222,7 @@ begin C => s_axi_aclk, CE => '1', D => s_level_out_bus_d3_15, - Q => \^scndry_vect_out\(15), + Q => scndry_vect_out(15), R => '0' ); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE @@ -1845,7 +1233,7 @@ begin C => s_axi_aclk, CE => '1', D => s_level_out_bus_d3_1, - Q => \^scndry_vect_out\(1), + Q => scndry_vect_out(1), R => '0' ); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE @@ -1856,7 +1244,7 @@ begin C => s_axi_aclk, CE => '1', D => s_level_out_bus_d3_2, - Q => \^scndry_vect_out\(2), + Q => scndry_vect_out(2), R => '0' ); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE @@ -1867,7 +1255,7 @@ begin C => s_axi_aclk, CE => '1', D => s_level_out_bus_d3_3, - Q => \^scndry_vect_out\(3), + Q => scndry_vect_out(3), R => '0' ); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE @@ -1878,7 +1266,7 @@ begin C => s_axi_aclk, CE => '1', D => s_level_out_bus_d3_4, - Q => \^scndry_vect_out\(4), + Q => scndry_vect_out(4), R => '0' ); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE @@ -1889,7 +1277,7 @@ begin C => s_axi_aclk, CE => '1', D => s_level_out_bus_d3_5, - Q => \^scndry_vect_out\(5), + Q => scndry_vect_out(5), R => '0' ); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE @@ -1900,7 +1288,7 @@ begin C => s_axi_aclk, CE => '1', D => s_level_out_bus_d3_6, - Q => \^scndry_vect_out\(6), + Q => scndry_vect_out(6), R => '0' ); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE @@ -1911,7 +1299,7 @@ begin C => s_axi_aclk, CE => '1', D => s_level_out_bus_d3_7, - Q => \^scndry_vect_out\(7), + Q => scndry_vect_out(7), R => '0' ); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE @@ -1922,7 +1310,7 @@ begin C => s_axi_aclk, CE => '1', D => s_level_out_bus_d3_8, - Q => \^scndry_vect_out\(8), + Q => scndry_vect_out(8), R => '0' ); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE @@ -1933,7 +1321,7 @@ begin C => s_axi_aclk, CE => '1', D => s_level_out_bus_d3_9, - Q => \^scndry_vect_out\(9), + Q => scndry_vect_out(9), R => '0' ); \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE @@ -2112,328 +1500,6 @@ begin Q => s_level_out_bus_d1_cdc_to_9, R => '0' ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[0]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => Q(15), - I1 => \^scndry_vect_out\(15), - O => D(15) - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[10]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => Q(5), - I1 => \^scndry_vect_out\(5), - O => D(5) - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[11]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => Q(4), - I1 => \^scndry_vect_out\(4), - O => D(4) - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[12]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => Q(3), - I1 => \^scndry_vect_out\(3), - O => D(3) - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[13]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => Q(2), - I1 => \^scndry_vect_out\(2), - O => D(2) - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[14]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => Q(1), - I1 => \^scndry_vect_out\(1), - O => D(1) - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[15]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => Q(0), - I1 => \^scndry_vect_out\(0), - O => D(0) - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[1]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => Q(14), - I1 => \^scndry_vect_out\(14), - O => D(14) - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[2]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => Q(13), - I1 => \^scndry_vect_out\(13), - O => D(13) - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[3]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => Q(12), - I1 => \^scndry_vect_out\(12), - O => D(12) - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[4]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => Q(11), - I1 => \^scndry_vect_out\(11), - O => D(11) - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[5]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => Q(10), - I1 => \^scndry_vect_out\(10), - O => D(10) - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[6]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => Q(9), - I1 => \^scndry_vect_out\(9), - O => D(9) - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[7]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => Q(8), - I1 => \^scndry_vect_out\(8), - O => D(8) - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[8]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => Q(7), - I1 => \^scndry_vect_out\(7), - O => D(7) - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[9]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => Q(6), - I1 => \^scndry_vect_out\(6), - O => D(6) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_gpio_shield_2_0_interrupt_control is - port ( - irpt_wrack_d1 : out STD_LOGIC; - p_3_in : out STD_LOGIC_VECTOR ( 0 to 0 ); - irpt_rdack_d1 : out STD_LOGIC; - p_1_in : out STD_LOGIC_VECTOR ( 0 to 0 ); - p_0_in : out STD_LOGIC_VECTOR ( 0 to 0 ); - IP2INTC_Irpt_i : out STD_LOGIC; - ip2bus_wrack_i : out STD_LOGIC; - ip2bus_rdack_i : out STD_LOGIC; - bus2ip_reset : in STD_LOGIC; - irpt_wrack : in STD_LOGIC; - s_axi_aclk : in STD_LOGIC; - GPIO_intr : in STD_LOGIC; - interrupt_wrce_strb : in STD_LOGIC; - irpt_rdack : in STD_LOGIC; - intr2bus_rdack0 : in STD_LOGIC; - \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\ : in STD_LOGIC; - \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\ : in STD_LOGIC; - p_8_in : in STD_LOGIC; - s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 ); - Bus_RNW_reg : in STD_LOGIC; - ip2Bus_WrAck_intr_reg_hole : in STD_LOGIC; - bus2ip_rnw : in STD_LOGIC; - GPIO_xferAck_i : in STD_LOGIC; - ip2Bus_RdAck_intr_reg_hole : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_gpio_shield_2_0_interrupt_control : entity is "interrupt_control"; -end Arty_Z7_20_axi_gpio_shield_2_0_interrupt_control; - -architecture STRUCTURE of Arty_Z7_20_axi_gpio_shield_2_0_interrupt_control is - signal \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\ : STD_LOGIC; - signal \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0\ : STD_LOGIC; - signal intr2bus_rdack : STD_LOGIC; - signal intr2bus_wrack : STD_LOGIC; - signal irpt_dly1 : STD_LOGIC; - signal irpt_dly2 : STD_LOGIC; - signal \^irpt_wrack_d1\ : STD_LOGIC; - signal \^p_0_in\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \^p_1_in\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \^p_3_in\ : STD_LOGIC_VECTOR ( 0 to 0 ); -begin - irpt_wrack_d1 <= \^irpt_wrack_d1\; - p_0_in(0) <= \^p_0_in\(0); - p_1_in(0) <= \^p_1_in\(0); - p_3_in(0) <= \^p_3_in\(0); -\DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly1_reg\: unisim.vcomponents.FDSE - port map ( - C => s_axi_aclk, - CE => '1', - D => GPIO_intr, - Q => irpt_dly1, - S => bus2ip_reset - ); -\DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly2_reg\: unisim.vcomponents.FDSE - port map ( - C => s_axi_aclk, - CE => '1', - D => irpt_dly1, - Q => irpt_dly2, - S => bus2ip_reset - ); -\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"F4F4F4F44FF4F4F4" - ) - port map ( - I0 => irpt_dly2, - I1 => irpt_dly1, - I2 => \^p_3_in\(0), - I3 => p_8_in, - I4 => s_axi_wdata(0), - I5 => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0\, - O => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\ - ); -\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2\: unisim.vcomponents.LUT2 - generic map( - INIT => X"E" - ) - port map ( - I0 => \^irpt_wrack_d1\, - I1 => Bus_RNW_reg, - O => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0\ - ); -\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\, - Q => \^p_3_in\(0), - R => bus2ip_reset - ); -\INTR_CTRLR_GEN.ip2intc_irpt_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"80" - ) - port map ( - I0 => \^p_3_in\(0), - I1 => \^p_1_in\(0), - I2 => \^p_0_in\(0), - O => IP2INTC_Irpt_i - ); -intr2bus_rdack_reg: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => intr2bus_rdack0, - Q => intr2bus_rdack, - R => bus2ip_reset - ); -intr2bus_wrack_reg: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => interrupt_wrce_strb, - Q => intr2bus_wrack, - R => bus2ip_reset - ); -ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT4 - generic map( - INIT => X"FEEE" - ) - port map ( - I0 => ip2Bus_RdAck_intr_reg_hole, - I1 => intr2bus_rdack, - I2 => bus2ip_rnw, - I3 => GPIO_xferAck_i, - O => ip2bus_rdack_i - ); -ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT4 - generic map( - INIT => X"EFEE" - ) - port map ( - I0 => ip2Bus_WrAck_intr_reg_hole, - I1 => intr2bus_wrack, - I2 => bus2ip_rnw, - I3 => GPIO_xferAck_i, - O => ip2bus_wrack_i - ); -\ip_irpt_enable_reg_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\, - Q => \^p_1_in\(0), - R => bus2ip_reset - ); -ipif_glbl_irpt_enable_reg_reg: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\, - Q => \^p_0_in\(0), - R => bus2ip_reset - ); -irpt_rdack_d1_reg: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => irpt_rdack, - Q => irpt_rdack_d1, - R => bus2ip_reset - ); -irpt_wrack_d1_reg: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => irpt_wrack, - Q => \^irpt_wrack_d1\, - R => bus2ip_reset - ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; @@ -2441,37 +1507,39 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20_axi_gpio_shield_2_0_GPIO_Core is port ( - ip2bus_data : out STD_LOGIC_VECTOR ( 15 downto 0 ); + D : out STD_LOGIC_VECTOR ( 15 downto 0 ); GPIO_xferAck_i : out STD_LOGIC; gpio_xferAck_Reg : out STD_LOGIC; - GPIO_intr : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 15 downto 0 ); + ip2bus_rdack_i : out STD_LOGIC; + ip2bus_wrack_i_D1_reg : out STD_LOGIC; gpio_io_o : out STD_LOGIC_VECTOR ( 15 downto 0 ); gpio_io_t : out STD_LOGIC_VECTOR ( 15 downto 0 ); - Read_Reg_Rst : in STD_LOGIC; - \Not_Dual.gpio_OE_reg[15]_0\ : in STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 15 downto 0 ); + bus2ip_rnw_i_reg : in STD_LOGIC; + \Not_Dual.gpio_Data_In_reg[15]_0\ : in STD_LOGIC; s_axi_aclk : in STD_LOGIC; - \Not_Dual.gpio_OE_reg[14]_0\ : in STD_LOGIC; - \Not_Dual.gpio_OE_reg[13]_0\ : in STD_LOGIC; - \Not_Dual.gpio_OE_reg[12]_0\ : in STD_LOGIC; - \Not_Dual.gpio_OE_reg[11]_0\ : in STD_LOGIC; - \Not_Dual.gpio_OE_reg[10]_0\ : in STD_LOGIC; - \Not_Dual.gpio_OE_reg[9]_0\ : in STD_LOGIC; - \Not_Dual.gpio_OE_reg[8]_0\ : in STD_LOGIC; - \Not_Dual.gpio_OE_reg[7]_0\ : in STD_LOGIC; - \Not_Dual.gpio_OE_reg[6]_0\ : in STD_LOGIC; - \Not_Dual.gpio_OE_reg[5]_0\ : in STD_LOGIC; - \Not_Dual.gpio_OE_reg[4]_0\ : in STD_LOGIC; - \Not_Dual.gpio_OE_reg[3]_0\ : in STD_LOGIC; - \Not_Dual.gpio_OE_reg[2]_0\ : in STD_LOGIC; - \Not_Dual.gpio_OE_reg[1]_0\ : in STD_LOGIC; + \Not_Dual.gpio_Data_In_reg[14]_0\ : in STD_LOGIC; + \Not_Dual.gpio_Data_In_reg[13]_0\ : in STD_LOGIC; + \Not_Dual.gpio_Data_In_reg[12]_0\ : in STD_LOGIC; + \Not_Dual.gpio_Data_In_reg[11]_0\ : in STD_LOGIC; + \Not_Dual.gpio_Data_In_reg[10]_0\ : in STD_LOGIC; + \Not_Dual.gpio_Data_In_reg[9]_0\ : in STD_LOGIC; + \Not_Dual.gpio_Data_In_reg[8]_0\ : in STD_LOGIC; + \Not_Dual.gpio_Data_In_reg[7]_0\ : in STD_LOGIC; + \Not_Dual.gpio_Data_In_reg[6]_0\ : in STD_LOGIC; + \Not_Dual.gpio_Data_In_reg[5]_0\ : in STD_LOGIC; + \Not_Dual.gpio_Data_In_reg[4]_0\ : in STD_LOGIC; + \Not_Dual.gpio_Data_In_reg[3]_0\ : in STD_LOGIC; + \Not_Dual.gpio_Data_In_reg[2]_0\ : in STD_LOGIC; + \Not_Dual.gpio_Data_In_reg[1]_0\ : in STD_LOGIC; GPIO_DBus_i : in STD_LOGIC_VECTOR ( 0 to 0 ); - bus2ip_reset : in STD_LOGIC; - bus2ip_cs : in STD_LOGIC_VECTOR ( 0 to 0 ); + SS : in STD_LOGIC_VECTOR ( 0 to 0 ); + bus2ip_rnw : in STD_LOGIC; + bus2ip_cs : in STD_LOGIC; gpio_io_i : in STD_LOGIC_VECTOR ( 15 downto 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ); - D : in STD_LOGIC_VECTOR ( 15 downto 0 ); - bus2ip_rnw_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ) + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + rst_reg : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of Arty_Z7_20_axi_gpio_shield_2_0_GPIO_Core : entity is "GPIO_Core"; @@ -2479,228 +1547,17 @@ end Arty_Z7_20_axi_gpio_shield_2_0_GPIO_Core; architecture STRUCTURE of Arty_Z7_20_axi_gpio_shield_2_0_GPIO_Core is signal \^gpio_xferack_i\ : STD_LOGIC; - signal \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0\ : STD_LOGIC; - signal \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3_n_0\ : STD_LOGIC; - signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0]\ : STD_LOGIC; - signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[11]\ : STD_LOGIC; - signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[15]\ : STD_LOGIC; - signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1]\ : STD_LOGIC; - signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[8]\ : STD_LOGIC; - signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[9]\ : STD_LOGIC; - signal \^q\ : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal gpio_data_in_xor : STD_LOGIC_VECTOR ( 0 to 15 ); signal gpio_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 15 ); signal \^gpio_xferack_reg\ : STD_LOGIC; signal iGPIO_xferAck : STD_LOGIC; - signal or_ints : STD_LOGIC; - signal p_11_in : STD_LOGIC; - signal p_12_in : STD_LOGIC; - signal p_13_in : STD_LOGIC; - signal p_1_in : STD_LOGIC; - signal p_2_in : STD_LOGIC; - signal p_3_in : STD_LOGIC; - signal p_4_in : STD_LOGIC; - signal p_5_in : STD_LOGIC; - signal p_6_in : STD_LOGIC; - signal p_9_in : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of iGPIO_xferAck_i_1 : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of ip2bus_rdack_i_D1_i_1 : label is "soft_lutpair4"; begin GPIO_xferAck_i <= \^gpio_xferack_i\; - Q(15 downto 0) <= \^q\(15 downto 0); gpio_xferAck_Reg <= \^gpio_xferack_reg\; -\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFFFFFFFFFFFFE" - ) - port map ( - I0 => p_12_in, - I1 => p_11_in, - I2 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[15]\, - I3 => p_13_in, - I4 => \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0\, - I5 => \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3_n_0\, - O => or_ints - ); -\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFFFFFFFFFFFFE" - ) - port map ( - I0 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1]\, - I1 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0]\, - I2 => p_2_in, - I3 => p_1_in, - I4 => p_3_in, - I5 => p_4_in, - O => \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0\ - ); -\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFFFFFFFFFFFFE" - ) - port map ( - I0 => p_6_in, - I1 => p_5_in, - I2 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[9]\, - I3 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[8]\, - I4 => p_9_in, - I5 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[11]\, - O => \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3_n_0\ - ); -\Not_Dual.GEN_INTERRUPT.GPIO_intr_reg\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => or_ints, - Q => GPIO_intr, - R => bus2ip_reset - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => gpio_data_in_xor(0), - Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0]\, - R => bus2ip_reset - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[10]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => gpio_data_in_xor(10), - Q => p_9_in, - R => bus2ip_reset - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[11]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => gpio_data_in_xor(11), - Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[11]\, - R => bus2ip_reset - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[12]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => gpio_data_in_xor(12), - Q => p_11_in, - R => bus2ip_reset - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[13]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => gpio_data_in_xor(13), - Q => p_12_in, - R => bus2ip_reset - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[14]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => gpio_data_in_xor(14), - Q => p_13_in, - R => bus2ip_reset - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[15]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => gpio_data_in_xor(15), - Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[15]\, - R => bus2ip_reset - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => gpio_data_in_xor(1), - Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1]\, - R => bus2ip_reset - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => gpio_data_in_xor(2), - Q => p_1_in, - R => bus2ip_reset - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => gpio_data_in_xor(3), - Q => p_2_in, - R => bus2ip_reset - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => gpio_data_in_xor(4), - Q => p_3_in, - R => bus2ip_reset - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => gpio_data_in_xor(5), - Q => p_4_in, - R => bus2ip_reset - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => gpio_data_in_xor(6), - Q => p_5_in, - R => bus2ip_reset - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => gpio_data_in_xor(7), - Q => p_6_in, - R => bus2ip_reset - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[8]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => gpio_data_in_xor(8), - Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[8]\, - R => bus2ip_reset - ); -\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[9]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => gpio_data_in_xor(9), - Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[9]\, - R => bus2ip_reset - ); \Not_Dual.INPUT_DOUBLE_REGS3\: entity work.Arty_Z7_20_axi_gpio_shield_2_0_cdc_sync port map ( - D(15) => gpio_data_in_xor(0), - D(14) => gpio_data_in_xor(1), - D(13) => gpio_data_in_xor(2), - D(12) => gpio_data_in_xor(3), - D(11) => gpio_data_in_xor(4), - D(10) => gpio_data_in_xor(5), - D(9) => gpio_data_in_xor(6), - D(8) => gpio_data_in_xor(7), - D(7) => gpio_data_in_xor(8), - D(6) => gpio_data_in_xor(9), - D(5) => gpio_data_in_xor(10), - D(4) => gpio_data_in_xor(11), - D(3) => gpio_data_in_xor(12), - D(2) => gpio_data_in_xor(13), - D(1) => gpio_data_in_xor(14), - D(0) => gpio_data_in_xor(15), - Q(15 downto 0) => \^q\(15 downto 0), gpio_io_i(15 downto 0) => gpio_io_i(15 downto 0), s_axi_aclk => s_axi_aclk, scndry_vect_out(15) => gpio_io_i_d2(0), @@ -2725,135 +1582,135 @@ begin C => s_axi_aclk, CE => '1', D => GPIO_DBus_i(0), - Q => ip2bus_data(15), - R => Read_Reg_Rst + Q => D(15), + R => bus2ip_rnw_i_reg ); \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \Not_Dual.gpio_OE_reg[10]_0\, - Q => ip2bus_data(5), - R => Read_Reg_Rst + D => \Not_Dual.gpio_Data_In_reg[10]_0\, + Q => D(5), + R => bus2ip_rnw_i_reg ); \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \Not_Dual.gpio_OE_reg[11]_0\, - Q => ip2bus_data(4), - R => Read_Reg_Rst + D => \Not_Dual.gpio_Data_In_reg[11]_0\, + Q => D(4), + R => bus2ip_rnw_i_reg ); \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \Not_Dual.gpio_OE_reg[12]_0\, - Q => ip2bus_data(3), - R => Read_Reg_Rst + D => \Not_Dual.gpio_Data_In_reg[12]_0\, + Q => D(3), + R => bus2ip_rnw_i_reg ); \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \Not_Dual.gpio_OE_reg[13]_0\, - Q => ip2bus_data(2), - R => Read_Reg_Rst + D => \Not_Dual.gpio_Data_In_reg[13]_0\, + Q => D(2), + R => bus2ip_rnw_i_reg ); \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \Not_Dual.gpio_OE_reg[14]_0\, - Q => ip2bus_data(1), - R => Read_Reg_Rst + D => \Not_Dual.gpio_Data_In_reg[14]_0\, + Q => D(1), + R => bus2ip_rnw_i_reg ); \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \Not_Dual.gpio_OE_reg[15]_0\, - Q => ip2bus_data(0), - R => Read_Reg_Rst + D => \Not_Dual.gpio_Data_In_reg[15]_0\, + Q => D(0), + R => bus2ip_rnw_i_reg ); \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \Not_Dual.gpio_OE_reg[1]_0\, - Q => ip2bus_data(14), - R => Read_Reg_Rst + D => \Not_Dual.gpio_Data_In_reg[1]_0\, + Q => D(14), + R => bus2ip_rnw_i_reg ); \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \Not_Dual.gpio_OE_reg[2]_0\, - Q => ip2bus_data(13), - R => Read_Reg_Rst + D => \Not_Dual.gpio_Data_In_reg[2]_0\, + Q => D(13), + R => bus2ip_rnw_i_reg ); \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \Not_Dual.gpio_OE_reg[3]_0\, - Q => ip2bus_data(12), - R => Read_Reg_Rst + D => \Not_Dual.gpio_Data_In_reg[3]_0\, + Q => D(12), + R => bus2ip_rnw_i_reg ); \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \Not_Dual.gpio_OE_reg[4]_0\, - Q => ip2bus_data(11), - R => Read_Reg_Rst + D => \Not_Dual.gpio_Data_In_reg[4]_0\, + Q => D(11), + R => bus2ip_rnw_i_reg ); \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \Not_Dual.gpio_OE_reg[5]_0\, - Q => ip2bus_data(10), - R => Read_Reg_Rst + D => \Not_Dual.gpio_Data_In_reg[5]_0\, + Q => D(10), + R => bus2ip_rnw_i_reg ); \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \Not_Dual.gpio_OE_reg[6]_0\, - Q => ip2bus_data(9), - R => Read_Reg_Rst + D => \Not_Dual.gpio_Data_In_reg[6]_0\, + Q => D(9), + R => bus2ip_rnw_i_reg ); \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \Not_Dual.gpio_OE_reg[7]_0\, - Q => ip2bus_data(8), - R => Read_Reg_Rst + D => \Not_Dual.gpio_Data_In_reg[7]_0\, + Q => D(8), + R => bus2ip_rnw_i_reg ); \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \Not_Dual.gpio_OE_reg[8]_0\, - Q => ip2bus_data(7), - R => Read_Reg_Rst + D => \Not_Dual.gpio_Data_In_reg[8]_0\, + Q => D(7), + R => bus2ip_rnw_i_reg ); \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \Not_Dual.gpio_OE_reg[9]_0\, - Q => ip2bus_data(6), - R => Read_Reg_Rst + D => \Not_Dual.gpio_Data_In_reg[9]_0\, + Q => D(6), + R => bus2ip_rnw_i_reg ); \Not_Dual.gpio_Data_In_reg[0]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => gpio_io_i_d2(0), - Q => \^q\(15), + Q => Q(15), R => '0' ); \Not_Dual.gpio_Data_In_reg[10]\: unisim.vcomponents.FDRE @@ -2861,7 +1718,7 @@ begin C => s_axi_aclk, CE => '1', D => gpio_io_i_d2(10), - Q => \^q\(5), + Q => Q(5), R => '0' ); \Not_Dual.gpio_Data_In_reg[11]\: unisim.vcomponents.FDRE @@ -2869,7 +1726,7 @@ begin C => s_axi_aclk, CE => '1', D => gpio_io_i_d2(11), - Q => \^q\(4), + Q => Q(4), R => '0' ); \Not_Dual.gpio_Data_In_reg[12]\: unisim.vcomponents.FDRE @@ -2877,7 +1734,7 @@ begin C => s_axi_aclk, CE => '1', D => gpio_io_i_d2(12), - Q => \^q\(3), + Q => Q(3), R => '0' ); \Not_Dual.gpio_Data_In_reg[13]\: unisim.vcomponents.FDRE @@ -2885,7 +1742,7 @@ begin C => s_axi_aclk, CE => '1', D => gpio_io_i_d2(13), - Q => \^q\(2), + Q => Q(2), R => '0' ); \Not_Dual.gpio_Data_In_reg[14]\: unisim.vcomponents.FDRE @@ -2893,7 +1750,7 @@ begin C => s_axi_aclk, CE => '1', D => gpio_io_i_d2(14), - Q => \^q\(1), + Q => Q(1), R => '0' ); \Not_Dual.gpio_Data_In_reg[15]\: unisim.vcomponents.FDRE @@ -2901,7 +1758,7 @@ begin C => s_axi_aclk, CE => '1', D => gpio_io_i_d2(15), - Q => \^q\(0), + Q => Q(0), R => '0' ); \Not_Dual.gpio_Data_In_reg[1]\: unisim.vcomponents.FDRE @@ -2909,7 +1766,7 @@ begin C => s_axi_aclk, CE => '1', D => gpio_io_i_d2(1), - Q => \^q\(14), + Q => Q(14), R => '0' ); \Not_Dual.gpio_Data_In_reg[2]\: unisim.vcomponents.FDRE @@ -2917,7 +1774,7 @@ begin C => s_axi_aclk, CE => '1', D => gpio_io_i_d2(2), - Q => \^q\(13), + Q => Q(13), R => '0' ); \Not_Dual.gpio_Data_In_reg[3]\: unisim.vcomponents.FDRE @@ -2925,7 +1782,7 @@ begin C => s_axi_aclk, CE => '1', D => gpio_io_i_d2(3), - Q => \^q\(12), + Q => Q(12), R => '0' ); \Not_Dual.gpio_Data_In_reg[4]\: unisim.vcomponents.FDRE @@ -2933,7 +1790,7 @@ begin C => s_axi_aclk, CE => '1', D => gpio_io_i_d2(4), - Q => \^q\(11), + Q => Q(11), R => '0' ); \Not_Dual.gpio_Data_In_reg[5]\: unisim.vcomponents.FDRE @@ -2941,7 +1798,7 @@ begin C => s_axi_aclk, CE => '1', D => gpio_io_i_d2(5), - Q => \^q\(10), + Q => Q(10), R => '0' ); \Not_Dual.gpio_Data_In_reg[6]\: unisim.vcomponents.FDRE @@ -2949,7 +1806,7 @@ begin C => s_axi_aclk, CE => '1', D => gpio_io_i_d2(6), - Q => \^q\(9), + Q => Q(9), R => '0' ); \Not_Dual.gpio_Data_In_reg[7]\: unisim.vcomponents.FDRE @@ -2957,7 +1814,7 @@ begin C => s_axi_aclk, CE => '1', D => gpio_io_i_d2(7), - Q => \^q\(8), + Q => Q(8), R => '0' ); \Not_Dual.gpio_Data_In_reg[8]\: unisim.vcomponents.FDRE @@ -2965,7 +1822,7 @@ begin C => s_axi_aclk, CE => '1', D => gpio_io_i_d2(8), - Q => \^q\(7), + Q => Q(7), R => '0' ); \Not_Dual.gpio_Data_In_reg[9]\: unisim.vcomponents.FDRE @@ -2973,7 +1830,7 @@ begin C => s_axi_aclk, CE => '1', D => gpio_io_i_d2(9), - Q => \^q\(6), + Q => Q(6), R => '0' ); \Not_Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE @@ -2983,9 +1840,9 @@ begin port map ( C => s_axi_aclk, CE => E(0), - D => D(15), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(15), Q => gpio_io_o(15), - R => bus2ip_reset + R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[10]\: unisim.vcomponents.FDRE generic map( @@ -2994,9 +1851,9 @@ begin port map ( C => s_axi_aclk, CE => E(0), - D => D(5), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(5), Q => gpio_io_o(5), - R => bus2ip_reset + R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[11]\: unisim.vcomponents.FDRE generic map( @@ -3005,9 +1862,9 @@ begin port map ( C => s_axi_aclk, CE => E(0), - D => D(4), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(4), Q => gpio_io_o(4), - R => bus2ip_reset + R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[12]\: unisim.vcomponents.FDRE generic map( @@ -3016,9 +1873,9 @@ begin port map ( C => s_axi_aclk, CE => E(0), - D => D(3), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(3), Q => gpio_io_o(3), - R => bus2ip_reset + R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[13]\: unisim.vcomponents.FDRE generic map( @@ -3027,9 +1884,9 @@ begin port map ( C => s_axi_aclk, CE => E(0), - D => D(2), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(2), Q => gpio_io_o(2), - R => bus2ip_reset + R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[14]\: unisim.vcomponents.FDRE generic map( @@ -3038,9 +1895,9 @@ begin port map ( C => s_axi_aclk, CE => E(0), - D => D(1), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(1), Q => gpio_io_o(1), - R => bus2ip_reset + R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[15]\: unisim.vcomponents.FDRE generic map( @@ -3049,9 +1906,9 @@ begin port map ( C => s_axi_aclk, CE => E(0), - D => D(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(0), Q => gpio_io_o(0), - R => bus2ip_reset + R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[1]\: unisim.vcomponents.FDRE generic map( @@ -3060,9 +1917,9 @@ begin port map ( C => s_axi_aclk, CE => E(0), - D => D(14), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(14), Q => gpio_io_o(14), - R => bus2ip_reset + R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[2]\: unisim.vcomponents.FDRE generic map( @@ -3071,9 +1928,9 @@ begin port map ( C => s_axi_aclk, CE => E(0), - D => D(13), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(13), Q => gpio_io_o(13), - R => bus2ip_reset + R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[3]\: unisim.vcomponents.FDRE generic map( @@ -3082,9 +1939,9 @@ begin port map ( C => s_axi_aclk, CE => E(0), - D => D(12), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(12), Q => gpio_io_o(12), - R => bus2ip_reset + R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[4]\: unisim.vcomponents.FDRE generic map( @@ -3093,9 +1950,9 @@ begin port map ( C => s_axi_aclk, CE => E(0), - D => D(11), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(11), Q => gpio_io_o(11), - R => bus2ip_reset + R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[5]\: unisim.vcomponents.FDRE generic map( @@ -3104,9 +1961,9 @@ begin port map ( C => s_axi_aclk, CE => E(0), - D => D(10), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(10), Q => gpio_io_o(10), - R => bus2ip_reset + R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[6]\: unisim.vcomponents.FDRE generic map( @@ -3115,9 +1972,9 @@ begin port map ( C => s_axi_aclk, CE => E(0), - D => D(9), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(9), Q => gpio_io_o(9), - R => bus2ip_reset + R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[7]\: unisim.vcomponents.FDRE generic map( @@ -3126,9 +1983,9 @@ begin port map ( C => s_axi_aclk, CE => E(0), - D => D(8), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(8), Q => gpio_io_o(8), - R => bus2ip_reset + R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[8]\: unisim.vcomponents.FDRE generic map( @@ -3137,9 +1994,9 @@ begin port map ( C => s_axi_aclk, CE => E(0), - D => D(7), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(7), Q => gpio_io_o(7), - R => bus2ip_reset + R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[9]\: unisim.vcomponents.FDRE generic map( @@ -3148,9 +2005,9 @@ begin port map ( C => s_axi_aclk, CE => E(0), - D => D(6), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(6), Q => gpio_io_o(6), - R => bus2ip_reset + R => SS(0) ); \Not_Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE generic map( @@ -3158,10 +2015,10 @@ begin ) port map ( C => s_axi_aclk, - CE => bus2ip_rnw_i_reg(0), - D => D(15), + CE => rst_reg(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(15), Q => gpio_io_t(15), - S => bus2ip_reset + S => SS(0) ); \Not_Dual.gpio_OE_reg[10]\: unisim.vcomponents.FDSE generic map( @@ -3169,10 +2026,10 @@ begin ) port map ( C => s_axi_aclk, - CE => bus2ip_rnw_i_reg(0), - D => D(5), + CE => rst_reg(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(5), Q => gpio_io_t(5), - S => bus2ip_reset + S => SS(0) ); \Not_Dual.gpio_OE_reg[11]\: unisim.vcomponents.FDSE generic map( @@ -3180,10 +2037,10 @@ begin ) port map ( C => s_axi_aclk, - CE => bus2ip_rnw_i_reg(0), - D => D(4), + CE => rst_reg(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(4), Q => gpio_io_t(4), - S => bus2ip_reset + S => SS(0) ); \Not_Dual.gpio_OE_reg[12]\: unisim.vcomponents.FDSE generic map( @@ -3191,10 +2048,10 @@ begin ) port map ( C => s_axi_aclk, - CE => bus2ip_rnw_i_reg(0), - D => D(3), + CE => rst_reg(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(3), Q => gpio_io_t(3), - S => bus2ip_reset + S => SS(0) ); \Not_Dual.gpio_OE_reg[13]\: unisim.vcomponents.FDSE generic map( @@ -3202,10 +2059,10 @@ begin ) port map ( C => s_axi_aclk, - CE => bus2ip_rnw_i_reg(0), - D => D(2), + CE => rst_reg(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(2), Q => gpio_io_t(2), - S => bus2ip_reset + S => SS(0) ); \Not_Dual.gpio_OE_reg[14]\: unisim.vcomponents.FDSE generic map( @@ -3213,10 +2070,10 @@ begin ) port map ( C => s_axi_aclk, - CE => bus2ip_rnw_i_reg(0), - D => D(1), + CE => rst_reg(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(1), Q => gpio_io_t(1), - S => bus2ip_reset + S => SS(0) ); \Not_Dual.gpio_OE_reg[15]\: unisim.vcomponents.FDSE generic map( @@ -3224,10 +2081,10 @@ begin ) port map ( C => s_axi_aclk, - CE => bus2ip_rnw_i_reg(0), - D => D(0), + CE => rst_reg(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(0), Q => gpio_io_t(0), - S => bus2ip_reset + S => SS(0) ); \Not_Dual.gpio_OE_reg[1]\: unisim.vcomponents.FDSE generic map( @@ -3235,10 +2092,10 @@ begin ) port map ( C => s_axi_aclk, - CE => bus2ip_rnw_i_reg(0), - D => D(14), + CE => rst_reg(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(14), Q => gpio_io_t(14), - S => bus2ip_reset + S => SS(0) ); \Not_Dual.gpio_OE_reg[2]\: unisim.vcomponents.FDSE generic map( @@ -3246,10 +2103,10 @@ begin ) port map ( C => s_axi_aclk, - CE => bus2ip_rnw_i_reg(0), - D => D(13), + CE => rst_reg(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(13), Q => gpio_io_t(13), - S => bus2ip_reset + S => SS(0) ); \Not_Dual.gpio_OE_reg[3]\: unisim.vcomponents.FDSE generic map( @@ -3257,10 +2114,10 @@ begin ) port map ( C => s_axi_aclk, - CE => bus2ip_rnw_i_reg(0), - D => D(12), + CE => rst_reg(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(12), Q => gpio_io_t(12), - S => bus2ip_reset + S => SS(0) ); \Not_Dual.gpio_OE_reg[4]\: unisim.vcomponents.FDSE generic map( @@ -3268,10 +2125,10 @@ begin ) port map ( C => s_axi_aclk, - CE => bus2ip_rnw_i_reg(0), - D => D(11), + CE => rst_reg(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(11), Q => gpio_io_t(11), - S => bus2ip_reset + S => SS(0) ); \Not_Dual.gpio_OE_reg[5]\: unisim.vcomponents.FDSE generic map( @@ -3279,10 +2136,10 @@ begin ) port map ( C => s_axi_aclk, - CE => bus2ip_rnw_i_reg(0), - D => D(10), + CE => rst_reg(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(10), Q => gpio_io_t(10), - S => bus2ip_reset + S => SS(0) ); \Not_Dual.gpio_OE_reg[6]\: unisim.vcomponents.FDSE generic map( @@ -3290,10 +2147,10 @@ begin ) port map ( C => s_axi_aclk, - CE => bus2ip_rnw_i_reg(0), - D => D(9), + CE => rst_reg(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(9), Q => gpio_io_t(9), - S => bus2ip_reset + S => SS(0) ); \Not_Dual.gpio_OE_reg[7]\: unisim.vcomponents.FDSE generic map( @@ -3301,10 +2158,10 @@ begin ) port map ( C => s_axi_aclk, - CE => bus2ip_rnw_i_reg(0), - D => D(8), + CE => rst_reg(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(8), Q => gpio_io_t(8), - S => bus2ip_reset + S => SS(0) ); \Not_Dual.gpio_OE_reg[8]\: unisim.vcomponents.FDSE generic map( @@ -3312,10 +2169,10 @@ begin ) port map ( C => s_axi_aclk, - CE => bus2ip_rnw_i_reg(0), - D => D(7), + CE => rst_reg(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(7), Q => gpio_io_t(7), - S => bus2ip_reset + S => SS(0) ); \Not_Dual.gpio_OE_reg[9]\: unisim.vcomponents.FDSE generic map( @@ -3323,10 +2180,10 @@ begin ) port map ( C => s_axi_aclk, - CE => bus2ip_rnw_i_reg(0), - D => D(6), + CE => rst_reg(0), + D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(6), Q => gpio_io_t(6), - S => bus2ip_reset + S => SS(0) ); gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE port map ( @@ -3334,16 +2191,16 @@ gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE CE => '1', D => \^gpio_xferack_i\, Q => \^gpio_xferack_reg\, - R => bus2ip_reset + R => SS(0) ); iGPIO_xferAck_i_1: unisim.vcomponents.LUT3 generic map( - INIT => X"10" + INIT => X"02" ) port map ( - I0 => \^gpio_xferack_reg\, - I1 => \^gpio_xferack_i\, - I2 => bus2ip_cs(0), + I0 => bus2ip_cs, + I1 => \^gpio_xferack_reg\, + I2 => \^gpio_xferack_i\, O => iGPIO_xferAck ); iGPIO_xferAck_reg: unisim.vcomponents.FDRE @@ -3352,7 +2209,25 @@ iGPIO_xferAck_reg: unisim.vcomponents.FDRE CE => '1', D => iGPIO_xferAck, Q => \^gpio_xferack_i\, - R => bus2ip_reset + R => SS(0) + ); +ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^gpio_xferack_i\, + I1 => bus2ip_rnw, + O => ip2bus_rdack_i + ); +ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^gpio_xferack_i\, + I1 => bus2ip_rnw, + O => ip2bus_wrack_i_D1_reg ); end STRUCTURE; library IEEE; @@ -3361,72 +2236,51 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20_axi_gpio_shield_2_0_slave_attachment is port ( - \ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC; - \Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC; - \Not_Dual.gpio_Data_Out_reg[15]\ : out STD_LOGIC; - \ip_irpt_enable_reg_reg[0]\ : out STD_LOGIC; + SR : out STD_LOGIC; + \Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC; + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_bvalid : out STD_LOGIC; s_axi_arready : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wready : out STD_LOGIC; - D : out STD_LOGIC_VECTOR ( 15 downto 0 ); - \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]\ : out STD_LOGIC; GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 ); - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - \Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - \ip2bus_data_i_D1_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); - intr2bus_rdack0 : out STD_LOGIC; - irpt_rdack : out STD_LOGIC; - irpt_wrack : out STD_LOGIC; - interrupt_wrce_strb : out STD_LOGIC; - Read_Reg_Rst : out STD_LOGIC; - \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ : out STD_LOGIC; - intr_rd_ce_or_reduce : out STD_LOGIC; - \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC; - intr_wr_ce_or_reduce : out STD_LOGIC; - \ip_irpt_enable_reg_reg[0]_0\ : out STD_LOGIC; - ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC; - s_axi_rdata : out STD_LOGIC_VECTOR ( 16 downto 0 ); - bus2ip_reset : in STD_LOGIC; + \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31]\ : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 15 downto 0 ); + \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[16]\ : out STD_LOGIC; + s_axi_rdata : out STD_LOGIC_VECTOR ( 15 downto 0 ); s_axi_aclk : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; + s_axi_awvalid : in STD_LOGIC; + s_axi_wvalid : in STD_LOGIC; + s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_aresetn : in STD_LOGIC; + s_axi_rready : in STD_LOGIC; + s_axi_bready : in STD_LOGIC; ip2bus_rdack_i_D1 : in STD_LOGIC; ip2bus_wrack_i_D1 : in STD_LOGIC; - s_axi_bready : in STD_LOGIC; - s_axi_rready : in STD_LOGIC; - s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 ); - s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 ); - s_axi_awvalid : in STD_LOGIC; - s_axi_wvalid : in STD_LOGIC; - s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - gpio_io_t : in STD_LOGIC_VECTOR ( 15 downto 0 ); Q : in STD_LOGIC_VECTOR ( 15 downto 0 ); - p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); - irpt_rdack_d1 : in STD_LOGIC; - irpt_wrack_d1 : in STD_LOGIC; - ip2bus_data : in STD_LOGIC_VECTOR ( 0 to 0 ); - p_3_in : in STD_LOGIC_VECTOR ( 0 to 0 ); - p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 ); - GPIO_xferAck_i : in STD_LOGIC; + gpio_io_t : in STD_LOGIC_VECTOR ( 15 downto 0 ); + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); gpio_xferAck_Reg : in STD_LOGIC; - ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC; - ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC; - \ip2bus_data_i_D1_reg[0]_1\ : in STD_LOGIC_VECTOR ( 16 downto 0 ) + GPIO_xferAck_i : in STD_LOGIC; + \ip2bus_data_i_D1_reg[16]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of Arty_Z7_20_axi_gpio_shield_2_0_slave_attachment : entity is "slave_attachment"; @@ -3434,8 +2288,13 @@ end Arty_Z7_20_axi_gpio_shield_2_0_slave_attachment; architecture STRUCTURE of Arty_Z7_20_axi_gpio_shield_2_0_slave_attachment is signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal \^not_dual.gpio_oe_reg[0]\ : STD_LOGIC; + signal \^not_dual.gpio_data_out_reg[0]\ : STD_LOGIC; + signal \^sr\ : STD_LOGIC; signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 6 ); + signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC; + signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC; + signal \bus2ip_addr_i[8]_i_1_n_0\ : STD_LOGIC; + signal \bus2ip_addr_i[8]_i_2_n_0\ : STD_LOGIC; signal bus2ip_rnw_i06_out : STD_LOGIC; signal clear : STD_LOGIC; signal is_read : STD_LOGIC; @@ -3443,30 +2302,33 @@ architecture STRUCTURE of Arty_Z7_20_axi_gpio_shield_2_0_slave_attachment is signal is_write : STD_LOGIC; signal is_write_i_1_n_0 : STD_LOGIC; signal is_write_reg_n_0 : STD_LOGIC; - signal \p_0_out__0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 8 downto 2 ); + signal p_0_out : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal p_1_in : STD_LOGIC; signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^s_axi_arready\ : STD_LOGIC; signal \^s_axi_bvalid\ : STD_LOGIC; signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC; - signal s_axi_rdata_i : STD_LOGIC; + signal \s_axi_rdata_i[15]_i_1_n_0\ : STD_LOGIC; signal \^s_axi_rvalid\ : STD_LOGIC; signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC; signal \^s_axi_wready\ : STD_LOGIC; signal start2 : STD_LOGIC; signal start2_i_1_n_0 : STD_LOGIC; signal state : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal \state[1]_i_2_n_0\ : STD_LOGIC; + signal \state1__2\ : STD_LOGIC; signal \state[1]_i_3_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair6"; - attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair6"; - attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair5"; - attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair5"; - attribute SOFT_HLUTNM of \bus2ip_addr_i[4]_i_1\ : label is "soft_lutpair4"; - attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \bus2ip_addr_i[3]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair1"; begin - \Not_Dual.gpio_OE_reg[0]\ <= \^not_dual.gpio_oe_reg[0]\; + \Not_Dual.gpio_Data_Out_reg[0]\ <= \^not_dual.gpio_data_out_reg[0]\; + SR <= \^sr\; s_axi_arready <= \^s_axi_arready\; s_axi_bvalid <= \^s_axi_bvalid\; s_axi_rvalid <= \^s_axi_rvalid\; @@ -3493,8 +2355,8 @@ begin INIT => X"78" ) port map ( - I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), - I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), + I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), + I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), O => plusOp(2) ); @@ -3503,8 +2365,8 @@ begin INIT => X"9" ) port map ( - I0 => state(1), - I1 => state(0), + I0 => state(0), + I1 => state(1), O => clear ); \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4 @@ -3512,9 +2374,9 @@ begin INIT => X"7F80" ) port map ( - I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), + I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), - I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), + I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3), O => plusOp(3) ); @@ -3556,8 +2418,9 @@ I_DECODER: entity work.Arty_Z7_20_axi_gpio_shield_2_0_address_decoder E(0) => E(0), GPIO_DBus_i(0) => GPIO_DBus_i(0), GPIO_xferAck_i => GPIO_xferAck_i, - \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\, - \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\, + \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\, + \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[16]\ => \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[16]\, \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\ => \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\, \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\ => \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\, \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\ => \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\, @@ -3574,208 +2437,114 @@ I_DECODER: entity work.Arty_Z7_20_axi_gpio_shield_2_0_address_decoder \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\ => \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\, \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\ => \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\, \Not_Dual.gpio_Data_In_reg[0]\(15 downto 0) => Q(15 downto 0), - \Not_Dual.gpio_Data_Out_reg[0]\(0) => \Not_Dual.gpio_Data_Out_reg[0]\(0), - \Not_Dual.gpio_Data_Out_reg[15]\ => \Not_Dual.gpio_Data_Out_reg[15]\, - Q(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0), - Read_Reg_Rst => Read_Reg_Rst, - \bus2ip_addr_i_reg[8]\(6) => bus2ip_addr(0), - \bus2ip_addr_i_reg[8]\(5) => bus2ip_addr(1), - \bus2ip_addr_i_reg[8]\(4) => bus2ip_addr(2), - \bus2ip_addr_i_reg[8]\(3) => bus2ip_addr(3), - \bus2ip_addr_i_reg[8]\(2) => bus2ip_addr(4), - \bus2ip_addr_i_reg[8]\(1) => bus2ip_addr(5), - \bus2ip_addr_i_reg[8]\(0) => bus2ip_addr(6), - bus2ip_reset => bus2ip_reset, - bus2ip_rnw_i_reg => \^not_dual.gpio_oe_reg[0]\, + \Not_Dual.gpio_OE_reg[0]\(0) => \Not_Dual.gpio_OE_reg[0]\(0), + Q(2) => bus2ip_addr(0), + Q(1) => bus2ip_addr(5), + Q(0) => bus2ip_addr(6), + bus2ip_rnw_i_reg => \^not_dual.gpio_data_out_reg[0]\, gpio_io_t(15 downto 0) => gpio_io_t(15 downto 0), gpio_xferAck_Reg => gpio_xferAck_Reg, - interrupt_wrce_strb => interrupt_wrce_strb, - intr2bus_rdack0 => intr2bus_rdack0, - intr_rd_ce_or_reduce => intr_rd_ce_or_reduce, - intr_wr_ce_or_reduce => intr_wr_ce_or_reduce, - ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1, - ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1, - ip2bus_data(0) => ip2bus_data(0), - \ip2bus_data_i_D1_reg[0]\ => \ip2bus_data_i_D1_reg[0]\, - \ip2bus_data_i_D1_reg[0]_0\(1 downto 0) => \ip2bus_data_i_D1_reg[0]_0\(1 downto 0), ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1, ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1, - \ip_irpt_enable_reg_reg[0]\ => \ip_irpt_enable_reg_reg[0]\, - \ip_irpt_enable_reg_reg[0]_0\ => \ip_irpt_enable_reg_reg[0]_0\, - ipif_glbl_irpt_enable_reg_reg => ipif_glbl_irpt_enable_reg_reg, - irpt_rdack => irpt_rdack, - irpt_rdack_d1 => irpt_rdack_d1, - irpt_wrack => irpt_wrack, - irpt_wrack_d1 => irpt_wrack_d1, is_read => is_read, is_write_reg => is_write_reg_n_0, - p_0_in(0) => p_0_in(0), - p_1_in(0) => p_1_in(0), - p_3_in(0) => p_3_in(0), + rst_reg => \^sr\, s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_arready => \^s_axi_arready\, s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), s_axi_wready => \^s_axi_wready\, - start2 => start2 + start2_reg => start2 ); \bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"ABAAA8AA" + INIT => X"CCCACCCC" ) port map ( - I0 => s_axi_awaddr(0), - I1 => state(1), + I0 => s_axi_araddr(0), + I1 => s_axi_awaddr(0), I2 => state(0), - I3 => s_axi_arvalid, - I4 => s_axi_araddr(0), - O => \p_1_in__0\(2) + I3 => state(1), + I4 => s_axi_arvalid, + O => \bus2ip_addr_i[2]_i_1_n_0\ ); \bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"ABAAA8AA" - ) - port map ( - I0 => s_axi_awaddr(1), - I1 => state(1), - I2 => state(0), - I3 => s_axi_arvalid, - I4 => s_axi_araddr(1), - O => \p_1_in__0\(3) - ); -\bus2ip_addr_i[4]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"ABAAA8AA" - ) - port map ( - I0 => s_axi_awaddr(2), - I1 => state(1), - I2 => state(0), - I3 => s_axi_arvalid, - I4 => s_axi_araddr(2), - O => \p_1_in__0\(4) - ); -\bus2ip_addr_i[5]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"ABAAA8AA" - ) - port map ( - I0 => s_axi_awaddr(3), - I1 => state(1), - I2 => state(0), - I3 => s_axi_arvalid, - I4 => s_axi_araddr(3), - O => \p_1_in__0\(5) - ); -\bus2ip_addr_i[6]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"ABAAA8AA" + INIT => X"CCCACCCC" ) port map ( - I0 => s_axi_awaddr(4), - I1 => state(1), + I0 => s_axi_araddr(1), + I1 => s_axi_awaddr(1), I2 => state(0), - I3 => s_axi_arvalid, - I4 => s_axi_araddr(4), - O => \p_1_in__0\(6) + I3 => state(1), + I4 => s_axi_arvalid, + O => \bus2ip_addr_i[3]_i_1_n_0\ ); -\bus2ip_addr_i[7]_i_1\: unisim.vcomponents.LUT5 +\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"ABAAA8AA" + INIT => X"000000EA" ) port map ( - I0 => s_axi_awaddr(5), - I1 => state(1), - I2 => state(0), - I3 => s_axi_arvalid, - I4 => s_axi_araddr(5), - O => \p_1_in__0\(7) + I0 => s_axi_arvalid, + I1 => s_axi_awvalid, + I2 => s_axi_wvalid, + I3 => state(1), + I4 => state(0), + O => \bus2ip_addr_i[8]_i_1_n_0\ ); -\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5 +\bus2ip_addr_i[8]_i_2\: unisim.vcomponents.LUT5 generic map( - INIT => X"ABAAA8AA" + INIT => X"CCCACCCC" ) port map ( - I0 => s_axi_awaddr(6), - I1 => state(1), + I0 => s_axi_araddr(2), + I1 => s_axi_awaddr(2), I2 => state(0), - I3 => s_axi_arvalid, - I4 => s_axi_araddr(6), - O => \p_1_in__0\(8) + I3 => state(1), + I4 => s_axi_arvalid, + O => \bus2ip_addr_i[8]_i_2_n_0\ ); \bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, - CE => start2_i_1_n_0, - D => \p_1_in__0\(2), + CE => \bus2ip_addr_i[8]_i_1_n_0\, + D => \bus2ip_addr_i[2]_i_1_n_0\, Q => bus2ip_addr(6), - R => bus2ip_reset + R => \^sr\ ); \bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, - CE => start2_i_1_n_0, - D => \p_1_in__0\(3), + CE => \bus2ip_addr_i[8]_i_1_n_0\, + D => \bus2ip_addr_i[3]_i_1_n_0\, Q => bus2ip_addr(5), - R => bus2ip_reset - ); -\bus2ip_addr_i_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2_i_1_n_0, - D => \p_1_in__0\(4), - Q => bus2ip_addr(4), - R => bus2ip_reset - ); -\bus2ip_addr_i_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2_i_1_n_0, - D => \p_1_in__0\(5), - Q => bus2ip_addr(3), - R => bus2ip_reset - ); -\bus2ip_addr_i_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2_i_1_n_0, - D => \p_1_in__0\(6), - Q => bus2ip_addr(2), - R => bus2ip_reset - ); -\bus2ip_addr_i_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => start2_i_1_n_0, - D => \p_1_in__0\(7), - Q => bus2ip_addr(1), - R => bus2ip_reset + R => \^sr\ ); \bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, - CE => start2_i_1_n_0, - D => \p_1_in__0\(8), + CE => \bus2ip_addr_i[8]_i_1_n_0\, + D => \bus2ip_addr_i[8]_i_2_n_0\, Q => bus2ip_addr(0), - R => bus2ip_reset + R => \^sr\ ); bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3 generic map( - INIT => X"02" + INIT => X"10" ) port map ( - I0 => s_axi_arvalid, - I1 => state(0), - I2 => state(1), + I0 => state(0), + I1 => state(1), + I2 => s_axi_arvalid, O => bus2ip_rnw_i06_out ); bus2ip_rnw_i_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, - CE => start2_i_1_n_0, + CE => \bus2ip_addr_i[8]_i_1_n_0\, D => bus2ip_rnw_i06_out, - Q => \^not_dual.gpio_oe_reg[0]\, - R => bus2ip_reset + Q => \^not_dual.gpio_data_out_reg[0]\, + R => \^sr\ ); is_read_i_1: unisim.vcomponents.LUT5 generic map( @@ -3783,9 +2552,9 @@ is_read_i_1: unisim.vcomponents.LUT5 ) port map ( I0 => s_axi_arvalid, - I1 => \state[1]_i_2_n_0\, - I2 => state(1), - I3 => state(0), + I1 => \state1__2\, + I2 => state(0), + I3 => state(1), I4 => is_read, O => is_read_i_1_n_0 ); @@ -3795,17 +2564,17 @@ is_read_reg: unisim.vcomponents.FDRE CE => '1', D => is_read_i_1_n_0, Q => is_read, - R => bus2ip_reset + R => \^sr\ ); is_write_i_1: unisim.vcomponents.LUT6 generic map( - INIT => X"1000FFFF10000000" + INIT => X"0040FFFF00400000" ) port map ( - I0 => state(1), - I1 => s_axi_arvalid, + I0 => s_axi_arvalid, + I1 => s_axi_awvalid, I2 => s_axi_wvalid, - I3 => s_axi_awvalid, + I3 => state(1), I4 => is_write, I5 => is_write_reg_n_0, O => is_write_i_1_n_0 @@ -3815,12 +2584,12 @@ is_write_i_2: unisim.vcomponents.LUT6 INIT => X"F88800000000FFFF" ) port map ( - I0 => s_axi_bready, - I1 => \^s_axi_bvalid\, - I2 => s_axi_rready, - I3 => \^s_axi_rvalid\, - I4 => state(1), - I5 => state(0), + I0 => \^s_axi_rvalid\, + I1 => s_axi_rready, + I2 => \^s_axi_bvalid\, + I3 => s_axi_bready, + I4 => state(0), + I5 => state(1), O => is_write ); is_write_reg: unisim.vcomponents.FDRE @@ -3829,7 +2598,23 @@ is_write_reg: unisim.vcomponents.FDRE CE => '1', D => is_write_i_1_n_0, Q => is_write_reg_n_0, - R => bus2ip_reset + R => \^sr\ + ); +rst_i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => s_axi_aresetn, + O => p_1_in + ); +rst_reg: unisim.vcomponents.FDRE + port map ( + C => s_axi_aclk, + CE => '1', + D => p_1_in, + Q => \^sr\, + R => '0' ); s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5 generic map( @@ -3852,16 +2637,16 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE CE => '1', D => s_axi_bvalid_i_i_1_n_0, Q => \^s_axi_bvalid\, - R => bus2ip_reset + R => \^sr\ ); -\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2 +\s_axi_rdata_i[15]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => state(0), I1 => state(1), - O => s_axi_rdata_i + O => \s_axi_rdata_i[15]_i_1_n_0\ ); \s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE generic map( @@ -3869,10 +2654,10 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(0), + CE => \s_axi_rdata_i[15]_i_1_n_0\, + D => \ip2bus_data_i_D1_reg[16]\(0), Q => s_axi_rdata(0), - R => bus2ip_reset + R => \^sr\ ); \s_axi_rdata_i_reg[10]\: unisim.vcomponents.FDRE generic map( @@ -3880,10 +2665,10 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(10), + CE => \s_axi_rdata_i[15]_i_1_n_0\, + D => \ip2bus_data_i_D1_reg[16]\(10), Q => s_axi_rdata(10), - R => bus2ip_reset + R => \^sr\ ); \s_axi_rdata_i_reg[11]\: unisim.vcomponents.FDRE generic map( @@ -3891,10 +2676,10 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(11), + CE => \s_axi_rdata_i[15]_i_1_n_0\, + D => \ip2bus_data_i_D1_reg[16]\(11), Q => s_axi_rdata(11), - R => bus2ip_reset + R => \^sr\ ); \s_axi_rdata_i_reg[12]\: unisim.vcomponents.FDRE generic map( @@ -3902,10 +2687,10 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(12), + CE => \s_axi_rdata_i[15]_i_1_n_0\, + D => \ip2bus_data_i_D1_reg[16]\(12), Q => s_axi_rdata(12), - R => bus2ip_reset + R => \^sr\ ); \s_axi_rdata_i_reg[13]\: unisim.vcomponents.FDRE generic map( @@ -3913,10 +2698,10 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(13), + CE => \s_axi_rdata_i[15]_i_1_n_0\, + D => \ip2bus_data_i_D1_reg[16]\(13), Q => s_axi_rdata(13), - R => bus2ip_reset + R => \^sr\ ); \s_axi_rdata_i_reg[14]\: unisim.vcomponents.FDRE generic map( @@ -3924,10 +2709,10 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(14), + CE => \s_axi_rdata_i[15]_i_1_n_0\, + D => \ip2bus_data_i_D1_reg[16]\(14), Q => s_axi_rdata(14), - R => bus2ip_reset + R => \^sr\ ); \s_axi_rdata_i_reg[15]\: unisim.vcomponents.FDRE generic map( @@ -3935,10 +2720,10 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(15), + CE => \s_axi_rdata_i[15]_i_1_n_0\, + D => \ip2bus_data_i_D1_reg[16]\(15), Q => s_axi_rdata(15), - R => bus2ip_reset + R => \^sr\ ); \s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE generic map( @@ -3946,10 +2731,10 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(1), + CE => \s_axi_rdata_i[15]_i_1_n_0\, + D => \ip2bus_data_i_D1_reg[16]\(1), Q => s_axi_rdata(1), - R => bus2ip_reset + R => \^sr\ ); \s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE generic map( @@ -3957,21 +2742,10 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(2), + CE => \s_axi_rdata_i[15]_i_1_n_0\, + D => \ip2bus_data_i_D1_reg[16]\(2), Q => s_axi_rdata(2), - R => bus2ip_reset - ); -\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(16), - Q => s_axi_rdata(16), - R => bus2ip_reset + R => \^sr\ ); \s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE generic map( @@ -3979,10 +2753,10 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(3), + CE => \s_axi_rdata_i[15]_i_1_n_0\, + D => \ip2bus_data_i_D1_reg[16]\(3), Q => s_axi_rdata(3), - R => bus2ip_reset + R => \^sr\ ); \s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE generic map( @@ -3990,10 +2764,10 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(4), + CE => \s_axi_rdata_i[15]_i_1_n_0\, + D => \ip2bus_data_i_D1_reg[16]\(4), Q => s_axi_rdata(4), - R => bus2ip_reset + R => \^sr\ ); \s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE generic map( @@ -4001,10 +2775,10 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(5), + CE => \s_axi_rdata_i[15]_i_1_n_0\, + D => \ip2bus_data_i_D1_reg[16]\(5), Q => s_axi_rdata(5), - R => bus2ip_reset + R => \^sr\ ); \s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE generic map( @@ -4012,10 +2786,10 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(6), + CE => \s_axi_rdata_i[15]_i_1_n_0\, + D => \ip2bus_data_i_D1_reg[16]\(6), Q => s_axi_rdata(6), - R => bus2ip_reset + R => \^sr\ ); \s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE generic map( @@ -4023,10 +2797,10 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(7), + CE => \s_axi_rdata_i[15]_i_1_n_0\, + D => \ip2bus_data_i_D1_reg[16]\(7), Q => s_axi_rdata(7), - R => bus2ip_reset + R => \^sr\ ); \s_axi_rdata_i_reg[8]\: unisim.vcomponents.FDRE generic map( @@ -4034,10 +2808,10 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(8), + CE => \s_axi_rdata_i[15]_i_1_n_0\, + D => \ip2bus_data_i_D1_reg[16]\(8), Q => s_axi_rdata(8), - R => bus2ip_reset + R => \^sr\ ); \s_axi_rdata_i_reg[9]\: unisim.vcomponents.FDRE generic map( @@ -4045,10 +2819,10 @@ s_axi_bvalid_i_reg: unisim.vcomponents.FDRE ) port map ( C => s_axi_aclk, - CE => s_axi_rdata_i, - D => \ip2bus_data_i_D1_reg[0]_1\(9), + CE => \s_axi_rdata_i[15]_i_1_n_0\, + D => \ip2bus_data_i_D1_reg[16]\(9), Q => s_axi_rdata(9), - R => bus2ip_reset + R => \^sr\ ); s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5 generic map( @@ -4071,7 +2845,7 @@ s_axi_rvalid_i_reg: unisim.vcomponents.FDRE CE => '1', D => s_axi_rvalid_i_i_1_n_0, Q => \^s_axi_rvalid\, - R => bus2ip_reset + R => \^sr\ ); start2_i_1: unisim.vcomponents.LUT5 generic map( @@ -4081,8 +2855,8 @@ start2_i_1: unisim.vcomponents.LUT5 I0 => s_axi_awvalid, I1 => s_axi_wvalid, I2 => s_axi_arvalid, - I3 => state(0), - I4 => state(1), + I3 => state(1), + I4 => state(0), O => start2_i_1_n_0 ); start2_reg: unisim.vcomponents.FDRE @@ -4091,32 +2865,31 @@ start2_reg: unisim.vcomponents.FDRE CE => '1', D => start2_i_1_n_0, Q => start2, - R => bus2ip_reset + R => \^sr\ ); \state[0]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"0FFFAACC" + INIT => X"77FC44FC" ) port map ( - I0 => \^s_axi_wready\, - I1 => s_axi_arvalid, - I2 => \state[1]_i_2_n_0\, + I0 => \state1__2\, + I1 => state(0), + I2 => s_axi_arvalid, I3 => state(1), - I4 => state(0), - O => \p_0_out__0\(0) + I4 => \^s_axi_wready\, + O => p_0_out(0) ); -\state[1]_i_1\: unisim.vcomponents.LUT6 +\state[1]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"2E2E2E2ECCCCFFCC" + INIT => X"5FFC50FC" ) port map ( - I0 => \^s_axi_arready\, - I1 => state(1), - I2 => \state[1]_i_2_n_0\, - I3 => \state[1]_i_3_n_0\, - I4 => s_axi_arvalid, - I5 => state(0), - O => \p_0_out__0\(1) + I0 => \state1__2\, + I1 => \state[1]_i_3_n_0\, + I2 => state(1), + I3 => state(0), + I4 => \^s_axi_arready\, + O => p_0_out(1) ); \state[1]_i_2\: unisim.vcomponents.LUT4 generic map( @@ -4127,32 +2900,33 @@ start2_reg: unisim.vcomponents.FDRE I1 => \^s_axi_bvalid\, I2 => s_axi_rready, I3 => \^s_axi_rvalid\, - O => \state[1]_i_2_n_0\ + O => \state1__2\ ); -\state[1]_i_3\: unisim.vcomponents.LUT2 +\state[1]_i_3\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"08" ) port map ( - I0 => s_axi_awvalid, - I1 => s_axi_wvalid, + I0 => s_axi_wvalid, + I1 => s_axi_awvalid, + I2 => s_axi_arvalid, O => \state[1]_i_3_n_0\ ); \state_reg[0]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \p_0_out__0\(0), + D => p_0_out(0), Q => state(0), - R => bus2ip_reset + R => \^sr\ ); \state_reg[1]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => \p_0_out__0\(1), + D => p_0_out(1), Q => state(1), - R => bus2ip_reset + R => \^sr\ ); end STRUCTURE; library IEEE; @@ -4161,72 +2935,51 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20_axi_gpio_shield_2_0_axi_lite_ipif is port ( - p_8_in : out STD_LOGIC; + bus2ip_reset : out STD_LOGIC; bus2ip_rnw : out STD_LOGIC; - bus2ip_cs : out STD_LOGIC_VECTOR ( 0 to 0 ); - Bus_RNW_reg : out STD_LOGIC; + bus2ip_cs : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_bvalid : out STD_LOGIC; s_axi_arready : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wready : out STD_LOGIC; - D : out STD_LOGIC_VECTOR ( 15 downto 0 ); - \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]\ : out STD_LOGIC; - \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]\ : out STD_LOGIC; GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 ); - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - \Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - \ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); - intr2bus_rdack0 : out STD_LOGIC; - irpt_rdack : out STD_LOGIC; - irpt_wrack : out STD_LOGIC; - interrupt_wrce_strb : out STD_LOGIC; - Read_Reg_Rst : out STD_LOGIC; - \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ : out STD_LOGIC; - intr_rd_ce_or_reduce : out STD_LOGIC; - \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC; - intr_wr_ce_or_reduce : out STD_LOGIC; - \ip_irpt_enable_reg_reg[0]\ : out STD_LOGIC; - ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC; - s_axi_rdata : out STD_LOGIC_VECTOR ( 16 downto 0 ); - bus2ip_reset : in STD_LOGIC; + \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]\ : out STD_LOGIC; + \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31]\ : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 15 downto 0 ); + \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[16]\ : out STD_LOGIC; + s_axi_rdata : out STD_LOGIC_VECTOR ( 15 downto 0 ); s_axi_aclk : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; + s_axi_awvalid : in STD_LOGIC; + s_axi_wvalid : in STD_LOGIC; + s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_aresetn : in STD_LOGIC; + s_axi_rready : in STD_LOGIC; + s_axi_bready : in STD_LOGIC; ip2bus_rdack_i_D1 : in STD_LOGIC; ip2bus_wrack_i_D1 : in STD_LOGIC; - s_axi_bready : in STD_LOGIC; - s_axi_rready : in STD_LOGIC; - s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 ); - s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 ); - s_axi_awvalid : in STD_LOGIC; - s_axi_wvalid : in STD_LOGIC; - s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - gpio_io_t : in STD_LOGIC_VECTOR ( 15 downto 0 ); Q : in STD_LOGIC_VECTOR ( 15 downto 0 ); - p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); - irpt_rdack_d1 : in STD_LOGIC; - irpt_wrack_d1 : in STD_LOGIC; - ip2bus_data : in STD_LOGIC_VECTOR ( 0 to 0 ); - p_3_in : in STD_LOGIC_VECTOR ( 0 to 0 ); - p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 ); - GPIO_xferAck_i : in STD_LOGIC; + gpio_io_t : in STD_LOGIC_VECTOR ( 15 downto 0 ); + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); gpio_xferAck_Reg : in STD_LOGIC; - ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC; - ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC; - \ip2bus_data_i_D1_reg[0]_0\ : in STD_LOGIC_VECTOR ( 16 downto 0 ) + GPIO_xferAck_i : in STD_LOGIC; + \ip2bus_data_i_D1_reg[16]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of Arty_Z7_20_axi_gpio_shield_2_0_axi_lite_ipif : entity is "axi_lite_ipif"; @@ -4240,8 +2993,8 @@ I_SLAVE_ATTACHMENT: entity work.Arty_Z7_20_axi_gpio_shield_2_0_slave_attachment E(0) => E(0), GPIO_DBus_i(0) => GPIO_DBus_i(0), GPIO_xferAck_i => GPIO_xferAck_i, - \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\, - \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\, + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\ => bus2ip_cs, + \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[16]\ => \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[16]\, \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\ => \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\, \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\ => \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\, \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\ => \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\, @@ -4257,46 +3010,25 @@ I_SLAVE_ATTACHMENT: entity work.Arty_Z7_20_axi_gpio_shield_2_0_slave_attachment \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\ => \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\, \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\ => \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\, \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\ => \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\, - \Not_Dual.gpio_Data_Out_reg[0]\(0) => \Not_Dual.gpio_Data_Out_reg[0]\(0), - \Not_Dual.gpio_Data_Out_reg[15]\ => bus2ip_cs(0), - \Not_Dual.gpio_OE_reg[0]\ => bus2ip_rnw, + \Not_Dual.gpio_Data_Out_reg[0]\ => bus2ip_rnw, + \Not_Dual.gpio_OE_reg[0]\(0) => \Not_Dual.gpio_OE_reg[0]\(0), Q(15 downto 0) => Q(15 downto 0), - Read_Reg_Rst => Read_Reg_Rst, - bus2ip_reset => bus2ip_reset, + SR => bus2ip_reset, gpio_io_t(15 downto 0) => gpio_io_t(15 downto 0), gpio_xferAck_Reg => gpio_xferAck_Reg, - interrupt_wrce_strb => interrupt_wrce_strb, - intr2bus_rdack0 => intr2bus_rdack0, - intr_rd_ce_or_reduce => intr_rd_ce_or_reduce, - intr_wr_ce_or_reduce => intr_wr_ce_or_reduce, - ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1, - ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1, - ip2bus_data(0) => ip2bus_data(0), - \ip2bus_data_i_D1_reg[0]\ => p_8_in, - \ip2bus_data_i_D1_reg[0]_0\(1 downto 0) => \ip2bus_data_i_D1_reg[0]\(1 downto 0), - \ip2bus_data_i_D1_reg[0]_1\(16 downto 0) => \ip2bus_data_i_D1_reg[0]_0\(16 downto 0), + \ip2bus_data_i_D1_reg[16]\(15 downto 0) => \ip2bus_data_i_D1_reg[16]\(15 downto 0), ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1, ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1, - \ip_irpt_enable_reg_reg[0]\ => Bus_RNW_reg, - \ip_irpt_enable_reg_reg[0]_0\ => \ip_irpt_enable_reg_reg[0]\, - ipif_glbl_irpt_enable_reg_reg => ipif_glbl_irpt_enable_reg_reg, - irpt_rdack => irpt_rdack, - irpt_rdack_d1 => irpt_rdack_d1, - irpt_wrack => irpt_wrack, - irpt_wrack_d1 => irpt_wrack_d1, - p_0_in(0) => p_0_in(0), - p_1_in(0) => p_1_in(0), - p_3_in(0) => p_3_in(0), s_axi_aclk => s_axi_aclk, - s_axi_araddr(6 downto 0) => s_axi_araddr(6 downto 0), + s_axi_araddr(2 downto 0) => s_axi_araddr(2 downto 0), s_axi_aresetn => s_axi_aresetn, s_axi_arready => s_axi_arready, s_axi_arvalid => s_axi_arvalid, - s_axi_awaddr(6 downto 0) => s_axi_awaddr(6 downto 0), + s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0), s_axi_awvalid => s_axi_awvalid, s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, - s_axi_rdata(16 downto 0) => s_axi_rdata(16 downto 0), + s_axi_rdata(15 downto 0) => s_axi_rdata(15 downto 0), s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid, s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), @@ -4356,7 +3088,7 @@ entity Arty_Z7_20_axi_gpio_shield_2_0_axi_gpio is attribute C_GPIO_WIDTH : integer; attribute C_GPIO_WIDTH of Arty_Z7_20_axi_gpio_shield_2_0_axi_gpio : entity is 16; attribute C_INTERRUPT_PRESENT : integer; - attribute C_INTERRUPT_PRESENT of Arty_Z7_20_axi_gpio_shield_2_0_axi_gpio : entity is 1; + attribute C_INTERRUPT_PRESENT of Arty_Z7_20_axi_gpio_shield_2_0_axi_gpio : entity is 0; attribute C_IS_DUAL : integer; attribute C_IS_DUAL of Arty_Z7_20_axi_gpio_shield_2_0_axi_gpio : entity is 0; attribute C_S_AXI_ADDR_WIDTH : integer; @@ -4378,69 +3110,41 @@ end Arty_Z7_20_axi_gpio_shield_2_0_axi_gpio; architecture STRUCTURE of Arty_Z7_20_axi_gpio_shield_2_0_axi_gpio is signal \\ : STD_LOGIC; signal \\ : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_10 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_11 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_12 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_13 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_14 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_15 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_16 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_17 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_18 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_19 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_20 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_21 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_22 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_23 : STD_LOGIC; signal AXI_LITE_IPIF_I_n_24 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_25 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_26 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_27 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_28 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_29 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_30 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_31 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_32 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_33 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_34 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_35 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_36 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_37 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_38 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_40 : STD_LOGIC; signal AXI_LITE_IPIF_I_n_41 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_49 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_51 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_53 : STD_LOGIC; - signal AXI_LITE_IPIF_I_n_54 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_6 : STD_LOGIC; + signal AXI_LITE_IPIF_I_n_7 : STD_LOGIC; signal DBus_Reg : STD_LOGIC_VECTOR ( 0 to 15 ); signal GPIO_DBus_i : STD_LOGIC_VECTOR ( 16 to 16 ); - signal GPIO_intr : STD_LOGIC; signal GPIO_xferAck_i : STD_LOGIC; - signal IP2INTC_Irpt_i : STD_LOGIC; - signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC; - signal \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in\ : STD_LOGIC; - signal Read_Reg_Rst : STD_LOGIC; - signal bus2ip_cs : STD_LOGIC_VECTOR ( 1 to 1 ); + signal bus2ip_cs : STD_LOGIC; signal bus2ip_reset : STD_LOGIC; - signal bus2ip_reset_i_1_n_0 : STD_LOGIC; signal bus2ip_rnw : STD_LOGIC; signal gpio_Data_In : STD_LOGIC_VECTOR ( 0 to 15 ); + signal gpio_core_1_n_19 : STD_LOGIC; signal \^gpio_io_t\ : STD_LOGIC_VECTOR ( 15 downto 0 ); signal gpio_xferAck_Reg : STD_LOGIC; - signal interrupt_wrce_strb : STD_LOGIC; - signal intr2bus_rdack0 : STD_LOGIC; - signal intr_rd_ce_or_reduce : STD_LOGIC; - signal intr_wr_ce_or_reduce : STD_LOGIC; - signal ip2Bus_RdAck_intr_reg_hole : STD_LOGIC; - signal ip2Bus_RdAck_intr_reg_hole_d1 : STD_LOGIC; - signal ip2Bus_WrAck_intr_reg_hole : STD_LOGIC; - signal ip2Bus_WrAck_intr_reg_hole_d1 : STD_LOGIC; signal ip2bus_data : STD_LOGIC_VECTOR ( 16 to 31 ); - signal ip2bus_data_i : STD_LOGIC_VECTOR ( 31 to 31 ); - signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 0 to 31 ); + signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 16 to 31 ); signal ip2bus_rdack_i : STD_LOGIC; signal ip2bus_rdack_i_D1 : STD_LOGIC; - signal ip2bus_wrack_i : STD_LOGIC; signal ip2bus_wrack_i_D1 : STD_LOGIC; - signal irpt_rdack : STD_LOGIC; - signal irpt_rdack_d1 : STD_LOGIC; - signal irpt_wrack : STD_LOGIC; - signal irpt_wrack_d1 : STD_LOGIC; - signal p_0_in : STD_LOGIC_VECTOR ( 31 to 31 ); - signal p_0_out : STD_LOGIC_VECTOR ( 0 to 0 ); - signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 ); - signal p_3_in : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \^s_axi_wready\ : STD_LOGIC; - attribute sigis : string; - attribute sigis of \INTR_CTRLR_GEN.ip2intc_irpt_reg\ : label is "INTR_LEVEL_HIGH"; begin gpio2_io_o(31) <= \\; gpio2_io_o(30) <= \\; @@ -4507,10 +3211,11 @@ begin gpio2_io_t(1) <= \\; gpio2_io_t(0) <= \\; gpio_io_t(15 downto 0) <= \^gpio_io_t\(15 downto 0); + ip2intc_irpt <= \\; s_axi_awready <= \^s_axi_wready\; s_axi_bresp(1) <= \\; s_axi_bresp(0) <= \\; - s_axi_rdata(31) <= \^s_axi_rdata\(31); + s_axi_rdata(31) <= \\; s_axi_rdata(30) <= \\; s_axi_rdata(29) <= \\; s_axi_rdata(28) <= \\; @@ -4532,7 +3237,6 @@ begin s_axi_wready <= \^s_axi_wready\; AXI_LITE_IPIF_I: entity work.Arty_Z7_20_axi_gpio_shield_2_0_axi_lite_ipif port map ( - Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\, D(15) => DBus_Reg(0), D(14) => DBus_Reg(1), D(13) => DBus_Reg(2), @@ -4549,27 +3253,26 @@ AXI_LITE_IPIF_I: entity work.Arty_Z7_20_axi_gpio_shield_2_0_axi_lite_ipif D(2) => DBus_Reg(13), D(1) => DBus_Reg(14), D(0) => DBus_Reg(15), - E(0) => AXI_LITE_IPIF_I_n_40, + E(0) => AXI_LITE_IPIF_I_n_6, GPIO_DBus_i(0) => GPIO_DBus_i(16), GPIO_xferAck_i => GPIO_xferAck_i, - \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ => AXI_LITE_IPIF_I_n_49, - \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => AXI_LITE_IPIF_I_n_51, - \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\ => AXI_LITE_IPIF_I_n_29, - \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\ => AXI_LITE_IPIF_I_n_28, - \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\ => AXI_LITE_IPIF_I_n_27, - \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]\ => AXI_LITE_IPIF_I_n_26, - \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]\ => AXI_LITE_IPIF_I_n_25, + \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[16]\ => AXI_LITE_IPIF_I_n_41, + \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\ => AXI_LITE_IPIF_I_n_19, + \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\ => AXI_LITE_IPIF_I_n_20, + \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\ => AXI_LITE_IPIF_I_n_21, + \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]\ => AXI_LITE_IPIF_I_n_22, + \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]\ => AXI_LITE_IPIF_I_n_23, \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31]\ => AXI_LITE_IPIF_I_n_24, - \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]\ => AXI_LITE_IPIF_I_n_38, - \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]\ => AXI_LITE_IPIF_I_n_37, - \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]\ => AXI_LITE_IPIF_I_n_36, - \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]\ => AXI_LITE_IPIF_I_n_35, - \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]\ => AXI_LITE_IPIF_I_n_34, - \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]\ => AXI_LITE_IPIF_I_n_33, - \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\ => AXI_LITE_IPIF_I_n_32, - \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\ => AXI_LITE_IPIF_I_n_31, - \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\ => AXI_LITE_IPIF_I_n_30, - \Not_Dual.gpio_Data_Out_reg[0]\(0) => AXI_LITE_IPIF_I_n_41, + \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]\ => AXI_LITE_IPIF_I_n_10, + \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]\ => AXI_LITE_IPIF_I_n_11, + \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]\ => AXI_LITE_IPIF_I_n_12, + \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]\ => AXI_LITE_IPIF_I_n_13, + \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]\ => AXI_LITE_IPIF_I_n_14, + \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]\ => AXI_LITE_IPIF_I_n_15, + \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\ => AXI_LITE_IPIF_I_n_16, + \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\ => AXI_LITE_IPIF_I_n_17, + \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\ => AXI_LITE_IPIF_I_n_18, + \Not_Dual.gpio_OE_reg[0]\(0) => AXI_LITE_IPIF_I_n_7, Q(15) => gpio_Data_In(0), Q(14) => gpio_Data_In(1), Q(13) => gpio_Data_In(2), @@ -4586,60 +3289,40 @@ AXI_LITE_IPIF_I: entity work.Arty_Z7_20_axi_gpio_shield_2_0_axi_lite_ipif Q(2) => gpio_Data_In(13), Q(1) => gpio_Data_In(14), Q(0) => gpio_Data_In(15), - Read_Reg_Rst => Read_Reg_Rst, - bus2ip_cs(0) => bus2ip_cs(1), + bus2ip_cs => bus2ip_cs, bus2ip_reset => bus2ip_reset, bus2ip_rnw => bus2ip_rnw, gpio_io_t(15 downto 0) => \^gpio_io_t\(15 downto 0), gpio_xferAck_Reg => gpio_xferAck_Reg, - interrupt_wrce_strb => interrupt_wrce_strb, - intr2bus_rdack0 => intr2bus_rdack0, - intr_rd_ce_or_reduce => intr_rd_ce_or_reduce, - intr_wr_ce_or_reduce => intr_wr_ce_or_reduce, - ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1, - ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1, - ip2bus_data(0) => ip2bus_data(31), - \ip2bus_data_i_D1_reg[0]\(1) => p_0_out(0), - \ip2bus_data_i_D1_reg[0]\(0) => ip2bus_data_i(31), - \ip2bus_data_i_D1_reg[0]_0\(16) => ip2bus_data_i_D1(0), - \ip2bus_data_i_D1_reg[0]_0\(15) => ip2bus_data_i_D1(16), - \ip2bus_data_i_D1_reg[0]_0\(14) => ip2bus_data_i_D1(17), - \ip2bus_data_i_D1_reg[0]_0\(13) => ip2bus_data_i_D1(18), - \ip2bus_data_i_D1_reg[0]_0\(12) => ip2bus_data_i_D1(19), - \ip2bus_data_i_D1_reg[0]_0\(11) => ip2bus_data_i_D1(20), - \ip2bus_data_i_D1_reg[0]_0\(10) => ip2bus_data_i_D1(21), - \ip2bus_data_i_D1_reg[0]_0\(9) => ip2bus_data_i_D1(22), - \ip2bus_data_i_D1_reg[0]_0\(8) => ip2bus_data_i_D1(23), - \ip2bus_data_i_D1_reg[0]_0\(7) => ip2bus_data_i_D1(24), - \ip2bus_data_i_D1_reg[0]_0\(6) => ip2bus_data_i_D1(25), - \ip2bus_data_i_D1_reg[0]_0\(5) => ip2bus_data_i_D1(26), - \ip2bus_data_i_D1_reg[0]_0\(4) => ip2bus_data_i_D1(27), - \ip2bus_data_i_D1_reg[0]_0\(3) => ip2bus_data_i_D1(28), - \ip2bus_data_i_D1_reg[0]_0\(2) => ip2bus_data_i_D1(29), - \ip2bus_data_i_D1_reg[0]_0\(1) => ip2bus_data_i_D1(30), - \ip2bus_data_i_D1_reg[0]_0\(0) => ip2bus_data_i_D1(31), + \ip2bus_data_i_D1_reg[16]\(15) => ip2bus_data_i_D1(16), + \ip2bus_data_i_D1_reg[16]\(14) => ip2bus_data_i_D1(17), + \ip2bus_data_i_D1_reg[16]\(13) => ip2bus_data_i_D1(18), + \ip2bus_data_i_D1_reg[16]\(12) => ip2bus_data_i_D1(19), + \ip2bus_data_i_D1_reg[16]\(11) => ip2bus_data_i_D1(20), + \ip2bus_data_i_D1_reg[16]\(10) => ip2bus_data_i_D1(21), + \ip2bus_data_i_D1_reg[16]\(9) => ip2bus_data_i_D1(22), + \ip2bus_data_i_D1_reg[16]\(8) => ip2bus_data_i_D1(23), + \ip2bus_data_i_D1_reg[16]\(7) => ip2bus_data_i_D1(24), + \ip2bus_data_i_D1_reg[16]\(6) => ip2bus_data_i_D1(25), + \ip2bus_data_i_D1_reg[16]\(5) => ip2bus_data_i_D1(26), + \ip2bus_data_i_D1_reg[16]\(4) => ip2bus_data_i_D1(27), + \ip2bus_data_i_D1_reg[16]\(3) => ip2bus_data_i_D1(28), + \ip2bus_data_i_D1_reg[16]\(2) => ip2bus_data_i_D1(29), + \ip2bus_data_i_D1_reg[16]\(1) => ip2bus_data_i_D1(30), + \ip2bus_data_i_D1_reg[16]\(0) => ip2bus_data_i_D1(31), ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1, ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1, - \ip_irpt_enable_reg_reg[0]\ => AXI_LITE_IPIF_I_n_53, - ipif_glbl_irpt_enable_reg_reg => AXI_LITE_IPIF_I_n_54, - irpt_rdack => irpt_rdack, - irpt_rdack_d1 => irpt_rdack_d1, - irpt_wrack => irpt_wrack, - irpt_wrack_d1 => irpt_wrack_d1, - p_0_in(0) => p_0_in(31), - p_1_in(0) => p_1_in(0), - p_3_in(0) => p_3_in(0), - p_8_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in\, s_axi_aclk => s_axi_aclk, - s_axi_araddr(6 downto 0) => s_axi_araddr(8 downto 2), + s_axi_araddr(2) => s_axi_araddr(8), + s_axi_araddr(1 downto 0) => s_axi_araddr(3 downto 2), s_axi_aresetn => s_axi_aresetn, s_axi_arready => s_axi_arready, s_axi_arvalid => s_axi_arvalid, - s_axi_awaddr(6 downto 0) => s_axi_awaddr(8 downto 2), + s_axi_awaddr(2) => s_axi_awaddr(8), + s_axi_awaddr(1 downto 0) => s_axi_awaddr(3 downto 2), s_axi_awvalid => s_axi_awvalid, s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, - s_axi_rdata(16) => \^s_axi_rdata\(31), s_axi_rdata(15 downto 0) => \^s_axi_rdata\(15 downto 0), s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid, @@ -4651,130 +3334,62 @@ GND: unisim.vcomponents.GND port map ( G => \\ ); -\INTR_CTRLR_GEN.INTERRUPT_CONTROL_I\: entity work.Arty_Z7_20_axi_gpio_shield_2_0_interrupt_control - port map ( - Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\, - \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\ => AXI_LITE_IPIF_I_n_54, - \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\ => AXI_LITE_IPIF_I_n_53, - GPIO_intr => GPIO_intr, - GPIO_xferAck_i => GPIO_xferAck_i, - IP2INTC_Irpt_i => IP2INTC_Irpt_i, - bus2ip_reset => bus2ip_reset, - bus2ip_rnw => bus2ip_rnw, - interrupt_wrce_strb => interrupt_wrce_strb, - intr2bus_rdack0 => intr2bus_rdack0, - ip2Bus_RdAck_intr_reg_hole => ip2Bus_RdAck_intr_reg_hole, - ip2Bus_WrAck_intr_reg_hole => ip2Bus_WrAck_intr_reg_hole, - ip2bus_rdack_i => ip2bus_rdack_i, - ip2bus_wrack_i => ip2bus_wrack_i, - irpt_rdack => irpt_rdack, - irpt_rdack_d1 => irpt_rdack_d1, - irpt_wrack => irpt_wrack, - irpt_wrack_d1 => irpt_wrack_d1, - p_0_in(0) => p_0_in(31), - p_1_in(0) => p_1_in(0), - p_3_in(0) => p_3_in(0), - p_8_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in\, - s_axi_aclk => s_axi_aclk, - s_axi_wdata(0) => s_axi_wdata(0) - ); -\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_reg\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => intr_rd_ce_or_reduce, - Q => ip2Bus_RdAck_intr_reg_hole_d1, - R => bus2ip_reset - ); -\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => AXI_LITE_IPIF_I_n_49, - Q => ip2Bus_RdAck_intr_reg_hole, - R => bus2ip_reset - ); -\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_reg\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => intr_wr_ce_or_reduce, - Q => ip2Bus_WrAck_intr_reg_hole_d1, - R => bus2ip_reset - ); -\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => AXI_LITE_IPIF_I_n_51, - Q => ip2Bus_WrAck_intr_reg_hole, - R => bus2ip_reset - ); -\INTR_CTRLR_GEN.ip2intc_irpt_reg\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => IP2INTC_Irpt_i, - Q => ip2intc_irpt, - R => bus2ip_reset - ); VCC: unisim.vcomponents.VCC port map ( P => \\ ); -bus2ip_reset_i_1: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => s_axi_aresetn, - O => bus2ip_reset_i_1_n_0 - ); -bus2ip_reset_reg: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => bus2ip_reset_i_1_n_0, - Q => bus2ip_reset, - R => '0' - ); gpio_core_1: entity work.Arty_Z7_20_axi_gpio_shield_2_0_GPIO_Core port map ( - D(15) => DBus_Reg(0), - D(14) => DBus_Reg(1), - D(13) => DBus_Reg(2), - D(12) => DBus_Reg(3), - D(11) => DBus_Reg(4), - D(10) => DBus_Reg(5), - D(9) => DBus_Reg(6), - D(8) => DBus_Reg(7), - D(7) => DBus_Reg(8), - D(6) => DBus_Reg(9), - D(5) => DBus_Reg(10), - D(4) => DBus_Reg(11), - D(3) => DBus_Reg(12), - D(2) => DBus_Reg(13), - D(1) => DBus_Reg(14), - D(0) => DBus_Reg(15), - E(0) => AXI_LITE_IPIF_I_n_41, + D(15) => ip2bus_data(16), + D(14) => ip2bus_data(17), + D(13) => ip2bus_data(18), + D(12) => ip2bus_data(19), + D(11) => ip2bus_data(20), + D(10) => ip2bus_data(21), + D(9) => ip2bus_data(22), + D(8) => ip2bus_data(23), + D(7) => ip2bus_data(24), + D(6) => ip2bus_data(25), + D(5) => ip2bus_data(26), + D(4) => ip2bus_data(27), + D(3) => ip2bus_data(28), + D(2) => ip2bus_data(29), + D(1) => ip2bus_data(30), + D(0) => ip2bus_data(31), + E(0) => AXI_LITE_IPIF_I_n_6, GPIO_DBus_i(0) => GPIO_DBus_i(16), - GPIO_intr => GPIO_intr, GPIO_xferAck_i => GPIO_xferAck_i, - \Not_Dual.gpio_OE_reg[10]_0\ => AXI_LITE_IPIF_I_n_29, - \Not_Dual.gpio_OE_reg[11]_0\ => AXI_LITE_IPIF_I_n_28, - \Not_Dual.gpio_OE_reg[12]_0\ => AXI_LITE_IPIF_I_n_27, - \Not_Dual.gpio_OE_reg[13]_0\ => AXI_LITE_IPIF_I_n_26, - \Not_Dual.gpio_OE_reg[14]_0\ => AXI_LITE_IPIF_I_n_25, - \Not_Dual.gpio_OE_reg[15]_0\ => AXI_LITE_IPIF_I_n_24, - \Not_Dual.gpio_OE_reg[1]_0\ => AXI_LITE_IPIF_I_n_38, - \Not_Dual.gpio_OE_reg[2]_0\ => AXI_LITE_IPIF_I_n_37, - \Not_Dual.gpio_OE_reg[3]_0\ => AXI_LITE_IPIF_I_n_36, - \Not_Dual.gpio_OE_reg[4]_0\ => AXI_LITE_IPIF_I_n_35, - \Not_Dual.gpio_OE_reg[5]_0\ => AXI_LITE_IPIF_I_n_34, - \Not_Dual.gpio_OE_reg[6]_0\ => AXI_LITE_IPIF_I_n_33, - \Not_Dual.gpio_OE_reg[7]_0\ => AXI_LITE_IPIF_I_n_32, - \Not_Dual.gpio_OE_reg[8]_0\ => AXI_LITE_IPIF_I_n_31, - \Not_Dual.gpio_OE_reg[9]_0\ => AXI_LITE_IPIF_I_n_30, + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(15) => DBus_Reg(0), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(14) => DBus_Reg(1), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(13) => DBus_Reg(2), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(12) => DBus_Reg(3), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(11) => DBus_Reg(4), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(10) => DBus_Reg(5), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(9) => DBus_Reg(6), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(8) => DBus_Reg(7), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(7) => DBus_Reg(8), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(6) => DBus_Reg(9), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(5) => DBus_Reg(10), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(4) => DBus_Reg(11), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(3) => DBus_Reg(12), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(2) => DBus_Reg(13), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(1) => DBus_Reg(14), + \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(0) => DBus_Reg(15), + \Not_Dual.gpio_Data_In_reg[10]_0\ => AXI_LITE_IPIF_I_n_19, + \Not_Dual.gpio_Data_In_reg[11]_0\ => AXI_LITE_IPIF_I_n_20, + \Not_Dual.gpio_Data_In_reg[12]_0\ => AXI_LITE_IPIF_I_n_21, + \Not_Dual.gpio_Data_In_reg[13]_0\ => AXI_LITE_IPIF_I_n_22, + \Not_Dual.gpio_Data_In_reg[14]_0\ => AXI_LITE_IPIF_I_n_23, + \Not_Dual.gpio_Data_In_reg[15]_0\ => AXI_LITE_IPIF_I_n_24, + \Not_Dual.gpio_Data_In_reg[1]_0\ => AXI_LITE_IPIF_I_n_10, + \Not_Dual.gpio_Data_In_reg[2]_0\ => AXI_LITE_IPIF_I_n_11, + \Not_Dual.gpio_Data_In_reg[3]_0\ => AXI_LITE_IPIF_I_n_12, + \Not_Dual.gpio_Data_In_reg[4]_0\ => AXI_LITE_IPIF_I_n_13, + \Not_Dual.gpio_Data_In_reg[5]_0\ => AXI_LITE_IPIF_I_n_14, + \Not_Dual.gpio_Data_In_reg[6]_0\ => AXI_LITE_IPIF_I_n_15, + \Not_Dual.gpio_Data_In_reg[7]_0\ => AXI_LITE_IPIF_I_n_16, + \Not_Dual.gpio_Data_In_reg[8]_0\ => AXI_LITE_IPIF_I_n_17, + \Not_Dual.gpio_Data_In_reg[9]_0\ => AXI_LITE_IPIF_I_n_18, Q(15) => gpio_Data_In(0), Q(14) => gpio_Data_In(1), Q(13) => gpio_Data_In(2), @@ -4791,40 +3406,19 @@ gpio_core_1: entity work.Arty_Z7_20_axi_gpio_shield_2_0_GPIO_Core Q(2) => gpio_Data_In(13), Q(1) => gpio_Data_In(14), Q(0) => gpio_Data_In(15), - Read_Reg_Rst => Read_Reg_Rst, - bus2ip_cs(0) => bus2ip_cs(1), - bus2ip_reset => bus2ip_reset, - bus2ip_rnw_i_reg(0) => AXI_LITE_IPIF_I_n_40, + SS(0) => bus2ip_reset, + bus2ip_cs => bus2ip_cs, + bus2ip_rnw => bus2ip_rnw, + bus2ip_rnw_i_reg => AXI_LITE_IPIF_I_n_41, gpio_io_i(15 downto 0) => gpio_io_i(15 downto 0), gpio_io_o(15 downto 0) => gpio_io_o(15 downto 0), gpio_io_t(15 downto 0) => \^gpio_io_t\(15 downto 0), gpio_xferAck_Reg => gpio_xferAck_Reg, - ip2bus_data(15) => ip2bus_data(16), - ip2bus_data(14) => ip2bus_data(17), - ip2bus_data(13) => ip2bus_data(18), - ip2bus_data(12) => ip2bus_data(19), - ip2bus_data(11) => ip2bus_data(20), - ip2bus_data(10) => ip2bus_data(21), - ip2bus_data(9) => ip2bus_data(22), - ip2bus_data(8) => ip2bus_data(23), - ip2bus_data(7) => ip2bus_data(24), - ip2bus_data(6) => ip2bus_data(25), - ip2bus_data(5) => ip2bus_data(26), - ip2bus_data(4) => ip2bus_data(27), - ip2bus_data(3) => ip2bus_data(28), - ip2bus_data(2) => ip2bus_data(29), - ip2bus_data(1) => ip2bus_data(30), - ip2bus_data(0) => ip2bus_data(31), + ip2bus_rdack_i => ip2bus_rdack_i, + ip2bus_wrack_i_D1_reg => gpio_core_1_n_19, + rst_reg(0) => AXI_LITE_IPIF_I_n_7, s_axi_aclk => s_axi_aclk ); -\ip2bus_data_i_D1_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => s_axi_aclk, - CE => '1', - D => p_0_out(0), - Q => ip2bus_data_i_D1(0), - R => bus2ip_reset - ); \ip2bus_data_i_D1_reg[16]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, @@ -4949,7 +3543,7 @@ gpio_core_1: entity work.Arty_Z7_20_axi_gpio_shield_2_0_GPIO_Core port map ( C => s_axi_aclk, CE => '1', - D => ip2bus_data_i(31), + D => ip2bus_data(31), Q => ip2bus_data_i_D1(31), R => bus2ip_reset ); @@ -4965,7 +3559,7 @@ ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', - D => ip2bus_wrack_i, + D => gpio_core_1_n_19, Q => ip2bus_wrack_i_D1, R => bus2ip_reset ); @@ -4995,7 +3589,6 @@ entity Arty_Z7_20_axi_gpio_shield_2_0 is s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; - ip2intc_irpt : out STD_LOGIC; gpio_io_i : in STD_LOGIC_VECTOR ( 15 downto 0 ); gpio_io_o : out STD_LOGIC_VECTOR ( 15 downto 0 ); gpio_io_t : out STD_LOGIC_VECTOR ( 15 downto 0 ) @@ -5011,6 +3604,7 @@ entity Arty_Z7_20_axi_gpio_shield_2_0 is end Arty_Z7_20_axi_gpio_shield_2_0; architecture STRUCTURE of Arty_Z7_20_axi_gpio_shield_2_0 is + signal NLW_U0_ip2intc_irpt_UNCONNECTED : STD_LOGIC; signal NLW_U0_gpio2_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_U0_gpio2_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute C_ALL_INPUTS : integer; @@ -5032,7 +3626,7 @@ architecture STRUCTURE of Arty_Z7_20_axi_gpio_shield_2_0 is attribute C_GPIO_WIDTH : integer; attribute C_GPIO_WIDTH of U0 : label is 16; attribute C_INTERRUPT_PRESENT : integer; - attribute C_INTERRUPT_PRESENT of U0 : label is 1; + attribute C_INTERRUPT_PRESENT of U0 : label is 0; attribute C_IS_DUAL : integer; attribute C_IS_DUAL of U0 : label is 0; attribute C_S_AXI_ADDR_WIDTH : integer; @@ -5055,7 +3649,7 @@ U0: entity work.Arty_Z7_20_axi_gpio_shield_2_0_axi_gpio gpio_io_i(15 downto 0) => gpio_io_i(15 downto 0), gpio_io_o(15 downto 0) => gpio_io_o(15 downto 0), gpio_io_t(15 downto 0) => gpio_io_t(15 downto 0), - ip2intc_irpt => ip2intc_irpt, + ip2intc_irpt => NLW_U0_ip2intc_irpt_UNCONNECTED, s_axi_aclk => s_axi_aclk, s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0), s_axi_aresetn => s_axi_aresetn, diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0_stub.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0_stub.v index 3f756b5..eb25039 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0_stub.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -// Date : Fri Feb 24 16:00:40 2017 +// Date : Sat Mar 04 18:53:03 2017 // Host : WK73 running 64-bit Service Pack 1 (build 7601) // Command : write_verilog -force -mode synth_stub -// c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0_stub.v +// C:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0_stub.v // Design : Arty_Z7_20_axi_gpio_shield_2_0 // Purpose : Stub declaration of top-level module interface // Device : xc7z020clg400-1 @@ -17,9 +17,8 @@ module Arty_Z7_20_axi_gpio_shield_2_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready, - s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, ip2intc_irpt, gpio_io_i, gpio_io_o, - gpio_io_t) -/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,ip2intc_irpt,gpio_io_i[15:0],gpio_io_o[15:0],gpio_io_t[15:0]" */; + s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_i, gpio_io_o, gpio_io_t) +/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[15:0],gpio_io_o[15:0],gpio_io_t[15:0]" */; input s_axi_aclk; input s_axi_aresetn; input [8:0]s_axi_awaddr; @@ -39,7 +38,6 @@ module Arty_Z7_20_axi_gpio_shield_2_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr, output [1:0]s_axi_rresp; output s_axi_rvalid; input s_axi_rready; - output ip2intc_irpt; input [15:0]gpio_io_i; output [15:0]gpio_io_o; output [15:0]gpio_io_t; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0_stub.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0_stub.vhdl index 8b1db76..2810387 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0_stub.vhdl +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 --- Date : Fri Feb 24 16:00:40 2017 +-- Date : Sat Mar 04 18:53:03 2017 -- Host : WK73 running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode synth_stub --- c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0_stub.vhdl +-- C:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/Arty_Z7_20_axi_gpio_shield_2_0_stub.vhdl -- Design : Arty_Z7_20_axi_gpio_shield_2_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7z020clg400-1 @@ -33,7 +33,6 @@ entity Arty_Z7_20_axi_gpio_shield_2_0 is s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; - ip2intc_irpt : out STD_LOGIC; gpio_io_i : in STD_LOGIC_VECTOR ( 15 downto 0 ); gpio_io_o : out STD_LOGIC_VECTOR ( 15 downto 0 ); gpio_io_t : out STD_LOGIC_VECTOR ( 15 downto 0 ) @@ -45,7 +44,7 @@ architecture stub of Arty_Z7_20_axi_gpio_shield_2_0 is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,ip2intc_irpt,gpio_io_i[15:0],gpio_io_o[15:0],gpio_io_t[15:0]"; +attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[15:0],gpio_io_o[15:0],gpio_io_t[15:0]"; attribute x_core_info : string; attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2016.4"; begin diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/sim/Arty_Z7_20_axi_gpio_shield_2_0.vhd b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/sim/Arty_Z7_20_axi_gpio_shield_2_0.vhd index c238742..1ee057f 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/sim/Arty_Z7_20_axi_gpio_shield_2_0.vhd +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/sim/Arty_Z7_20_axi_gpio_shield_2_0.vhd @@ -77,7 +77,6 @@ ENTITY Arty_Z7_20_axi_gpio_shield_2_0 IS s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; - ip2intc_irpt : OUT STD_LOGIC; gpio_io_i : IN STD_LOGIC_VECTOR(15 DOWNTO 0); gpio_io_o : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); gpio_io_t : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) @@ -154,7 +153,6 @@ ARCHITECTURE Arty_Z7_20_axi_gpio_shield_2_0_arch OF Arty_Z7_20_axi_gpio_shield_2 ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; - ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT"; ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I"; ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O"; ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T"; @@ -170,7 +168,7 @@ BEGIN C_ALL_INPUTS_2 => 0, C_ALL_OUTPUTS => 0, C_ALL_OUTPUTS_2 => 0, - C_INTERRUPT_PRESENT => 1, + C_INTERRUPT_PRESENT => 0, C_DOUT_DEFAULT => X"00000000", C_TRI_DEFAULT => X"FFFFFFFF", C_IS_DUAL => 0, @@ -197,7 +195,6 @@ BEGIN s_axi_rresp => s_axi_rresp, s_axi_rvalid => s_axi_rvalid, s_axi_rready => s_axi_rready, - ip2intc_irpt => ip2intc_irpt, gpio_io_i => gpio_io_i, gpio_io_o => gpio_io_o, gpio_io_t => gpio_io_t, diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/synth/Arty_Z7_20_axi_gpio_shield_2_0.vhd b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/synth/Arty_Z7_20_axi_gpio_shield_2_0.vhd index a6c8446..fa64b81 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/synth/Arty_Z7_20_axi_gpio_shield_2_0.vhd +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_gpio_shield_2_0/synth/Arty_Z7_20_axi_gpio_shield_2_0.vhd @@ -77,7 +77,6 @@ ENTITY Arty_Z7_20_axi_gpio_shield_2_0 IS s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; - ip2intc_irpt : OUT STD_LOGIC; gpio_io_i : IN STD_LOGIC_VECTOR(15 DOWNTO 0); gpio_io_o : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); gpio_io_t : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) @@ -139,7 +138,7 @@ ARCHITECTURE Arty_Z7_20_axi_gpio_shield_2_0_arch OF Arty_Z7_20_axi_gpio_shield_2 ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF Arty_Z7_20_axi_gpio_shield_2_0_arch : ARCHITECTURE IS "Arty_Z7_20_axi_gpio_shield_2_0,axi_gpio,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; - ATTRIBUTE CORE_GENERATION_INFO OF Arty_Z7_20_axi_gpio_shield_2_0_arch: ARCHITECTURE IS "Arty_Z7_20_axi_gpio_shield_2_0,axi_gpio,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=13,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=16,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=1,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}"; + ATTRIBUTE CORE_GENERATION_INFO OF Arty_Z7_20_axi_gpio_shield_2_0_arch: ARCHITECTURE IS "Arty_Z7_20_axi_gpio_shield_2_0,axi_gpio,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=13,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=16,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST"; @@ -160,7 +159,6 @@ ARCHITECTURE Arty_Z7_20_axi_gpio_shield_2_0_arch OF Arty_Z7_20_axi_gpio_shield_2 ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; - ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT"; ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I"; ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O"; ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T"; @@ -176,7 +174,7 @@ BEGIN C_ALL_INPUTS_2 => 0, C_ALL_OUTPUTS => 0, C_ALL_OUTPUTS_2 => 0, - C_INTERRUPT_PRESENT => 1, + C_INTERRUPT_PRESENT => 0, C_DOUT_DEFAULT => X"00000000", C_TRI_DEFAULT => X"FFFFFFFF", C_IS_DUAL => 0, @@ -203,7 +201,6 @@ BEGIN s_axi_rresp => s_axi_rresp, s_axi_rvalid => s_axi_rvalid, s_axi_rready => s_axi_rready, - ip2intc_irpt => ip2intc_irpt, gpio_io_i => gpio_io_i, gpio_io_o => gpio_io_o, gpio_io_t => gpio_io_t, diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_mem_intercon_0/Arty_Z7_20_axi_mem_intercon_0.xci b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_mem_intercon_0/Arty_Z7_20_axi_mem_intercon_0.xci index 02dba47..a8ddef7 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_mem_intercon_0/Arty_Z7_20_axi_mem_intercon_0.xci +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_mem_intercon_0/Arty_Z7_20_axi_mem_intercon_0.xci @@ -1,358 +1,368 @@ - - xilinx.com - xci - unknown - 1.0 - - - Arty_Z7_20_axi_mem_intercon_0 - - - Arty_Z7_20_axi_mem_intercon_0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 2 - 2 - 0 - 0 - 2 - 4 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 2 - 32 - zynq - digilentinc.com:arty-z7-20:part0:1.0 - xc7z020 - clg400 - VHDL - - MIXED - -1 - - TRUE - TRUE - IP_Integrator_AppCore - 12 - TRUE - . - - ../../ipshared - 2016.4 - GLOBAL - - - - - - - - - - - - + + xilinx.com + xci + unknown + 1.0 + + + Arty_Z7_20_axi_mem_intercon_0 + + + Arty_Z7_20_axi_mem_intercon_0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 0 + 0 + 2 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 32 + zynq + digilentinc.com:arty-z7-20:part0:1.0 + xc7z020 + clg400 + VHDL + + MIXED + -1 + + TRUE + TRUE + IP_Integrator_AppCore + 12 + TRUE + . + + ../../ipshared + 2016.4 + GLOBAL + + + + + + + + + + + + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_mem_intercon_0/Arty_Z7_20_axi_mem_intercon_0.xml b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_mem_intercon_0/Arty_Z7_20_axi_mem_intercon_0.xml index 7af1812..2385f81 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_mem_intercon_0/Arty_Z7_20_axi_mem_intercon_0.xml +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_mem_intercon_0/Arty_Z7_20_axi_mem_intercon_0.xml @@ -1,1644 +1,2951 @@ - - xilinx.com - customized_ip - Arty_Z7_20_axi_mem_intercon_0 - 1.0 - - - choice_list_40181835 - 32 - 64 - 128 - 256 - 512 - 1024 - - - choice_list_661c4a03 - 2 - 4 - 8 - 16 - 32 - 64 - - - choice_pairs_4873554b - 0 - 1 - - - choice_pairs_76d086ea - 0 - 1 - 2 - - - choice_pairs_ab2668a2 - 0 - 1 - 2 - - - choice_pairs_b6c9535e - 0 - 1 - 3 - 4 - - - The AXI Interconnect IP connects one or more AXI memory-mapped master devices to one or more AXI memory mapped slave devices - - - NUM_SI - Number of Slave Interfaces - 1 - - - NUM_MI - Number of Master Interfaces - 1 - - - STRATEGY - Interconnect Optimization Strategy - 0 - - - ENABLE_ADVANCED_OPTIONS - Enable Advanced Configuration Options - 0 - - - ENABLE_PROTOCOL_CHECKERS - Enable Protocol Checkers and mark interfaces for debug - 0 - - - XBAR_DATA_WIDTH - Data Width of the AXI Crossbar - 32 - - - PCHK_WAITS - Maximum number of idle cycles for READY monitoring - 0 - - - PCHK_MAX_RD_BURSTS - Maximum outstanding READ Transactions per ID - 2 - - - PCHK_MAX_WR_BURSTS - Maximum outstanding WRITE Transactions per ID - 2 - - - SYNCHRONIZATION_STAGES - Synchronization Stages - 2 - - - M00_HAS_REGSLICE - Enable Register Slice on interface M00_AXI - 0 - - - M01_HAS_REGSLICE - Enable Register Slice on interface M01_AXI - 0 - - - M02_HAS_REGSLICE - Enable Register Slice on interface M02_AXI - 0 - - - M03_HAS_REGSLICE - Enable Register Slice on interface M03_AXI - 0 - - - M04_HAS_REGSLICE - Enable Register Slice on interface M04_AXI - 0 - - - M05_HAS_REGSLICE - Enable Register Slice on interface M05_AXI - 0 - - - M06_HAS_REGSLICE - Enable Register Slice on interface M06_AXI - 0 - - - M07_HAS_REGSLICE - Enable Register Slice on interface M07_AXI - 0 - - - M08_HAS_REGSLICE - Enable Register Slice on interface M08_AXI - 0 - - - M09_HAS_REGSLICE - Enable Register Slice on interface M09_AXI - 0 - - - M10_HAS_REGSLICE - Enable Register Slice on interface M10_AXI - 0 - - - M11_HAS_REGSLICE - Enable Register Slice on interface M11_AXI - 0 - - - M12_HAS_REGSLICE - Enable Register Slice on interface M12_AXI - 0 - - - M13_HAS_REGSLICE - Enable Register Slice on interface M13_AXI - 0 - - - M14_HAS_REGSLICE - Enable Register Slice on interface M14_AXI - 0 - - - M15_HAS_REGSLICE - Enable Register Slice on interface M15_AXI - 0 - - - M16_HAS_REGSLICE - Enable Register Slice on interface M16_AXI - 0 - - - M17_HAS_REGSLICE - Enable Register Slice on interface M17_AXI - 0 - - - M18_HAS_REGSLICE - Enable Register Slice on interface M18_AXI - 0 - - - M19_HAS_REGSLICE - Enable Register Slice on interface M19_AXI - 0 - - - M20_HAS_REGSLICE - Enable Register Slice on interface M20_AXI - 0 - - - M21_HAS_REGSLICE - Enable Register Slice on interface M21_AXI - 0 - - - M22_HAS_REGSLICE - Enable Register Slice on interface M22_AXI - 0 - - - M23_HAS_REGSLICE - Enable Register Slice on interface M23_AXI - 0 - - - M24_HAS_REGSLICE - Enable Register Slice on interface M24_AXI - 0 - - - M25_HAS_REGSLICE - Enable Register Slice on interface M25_AXI - 0 - - - M26_HAS_REGSLICE - Enable Register Slice on interface M26_AXI - 0 - - - M27_HAS_REGSLICE - Enable Register Slice on interface M27_AXI - 0 - - - M28_HAS_REGSLICE - Enable Register Slice on interface M28_AXI - 0 - - - M29_HAS_REGSLICE - Enable Register Slice on interface M29_AXI - 0 - - - M30_HAS_REGSLICE - Enable Register Slice on interface M30_AXI - 0 - - - M31_HAS_REGSLICE - Enable Register Slice on interface M31_AXI - 0 - - - M32_HAS_REGSLICE - Enable Register Slice on interface M32_AXI - 0 - - - M33_HAS_REGSLICE - Enable Register Slice on interface M33_AXI - 0 - - - M34_HAS_REGSLICE - Enable Register Slice on interface M34_AXI - 0 - - - M35_HAS_REGSLICE - Enable Register Slice on interface M35_AXI - 0 - - - M36_HAS_REGSLICE - Enable Register Slice on interface M36_AXI - 0 - - - M37_HAS_REGSLICE - Enable Register Slice on interface M37_AXI - 0 - - - M38_HAS_REGSLICE - Enable Register Slice on interface M38_AXI - 0 - - - M39_HAS_REGSLICE - Enable Register Slice on interface M39_AXI - 0 - - - M40_HAS_REGSLICE - Enable Register Slice on interface M40_AXI - 0 - - - M41_HAS_REGSLICE - Enable Register Slice on interface M41_AXI - 0 - - - M42_HAS_REGSLICE - Enable Register Slice on interface M42_AXI - 0 - - - M43_HAS_REGSLICE - Enable Register Slice on interface M43_AXI - 0 - - - M44_HAS_REGSLICE - Enable Register Slice on interface M44_AXI - 0 - - - M45_HAS_REGSLICE - Enable Register Slice on interface M45_AXI - 0 - - - M46_HAS_REGSLICE - Enable Register Slice on interface M46_AXI - 0 - - - M47_HAS_REGSLICE - Enable Register Slice on interface M47_AXI - 0 - - - M48_HAS_REGSLICE - Enable Register Slice on interface M48_AXI - 0 - - - M49_HAS_REGSLICE - Enable Register Slice on interface M49_AXI - 0 - - - M50_HAS_REGSLICE - Enable Register Slice on interface M50_AXI - 0 - - - M51_HAS_REGSLICE - Enable Register Slice on interface M51_AXI - 0 - - - M52_HAS_REGSLICE - Enable Register Slice on interface M52_AXI - 0 - - - M53_HAS_REGSLICE - Enable Register Slice on interface M53_AXI - 0 - - - M54_HAS_REGSLICE - Enable Register Slice on interface M54_AXI - 0 - - - M55_HAS_REGSLICE - Enable Register Slice on interface M55_AXI - 0 - - - M56_HAS_REGSLICE - Enable Register Slice on interface M56_AXI - 0 - - - M57_HAS_REGSLICE - Enable Register Slice on interface M57_AXI - 0 - - - M58_HAS_REGSLICE - Enable Register Slice on interface M58_AXI - 0 - - - M59_HAS_REGSLICE - Enable Register Slice on interface M59_AXI - 0 - - - M60_HAS_REGSLICE - Enable Register Slice on interface M60_AXI - 0 - - - M61_HAS_REGSLICE - Enable Register Slice on interface M61_AXI - 0 - - - M62_HAS_REGSLICE - Enable Register Slice on interface M62_AXI - 0 - - - M63_HAS_REGSLICE - Enable Register Slice on interface M63_AXI - 0 - - - M00_HAS_DATA_FIFO - Enable Data FIFO on interface M00_AXI - 0 - - - M01_HAS_DATA_FIFO - Enable Data FIFO on interface M01_AXI - 0 - - - M02_HAS_DATA_FIFO - Enable Data FIFO on interface M02_AXI - 0 - - - M03_HAS_DATA_FIFO - Enable Data FIFO on interface M03_AXI - 0 - - - M04_HAS_DATA_FIFO - Enable Data FIFO on interface M04_AXI - 0 - - - M05_HAS_DATA_FIFO - Enable Data FIFO on interface M05_AXI - 0 - - - M06_HAS_DATA_FIFO - Enable Data FIFO on interface M06_AXI - 0 - - - M07_HAS_DATA_FIFO - Enable Data FIFO on interface M07_AXI - 0 - - - M08_HAS_DATA_FIFO - Enable Data FIFO on interface M08_AXI - 0 - - - M09_HAS_DATA_FIFO - Enable Data FIFO on interface M09_AXI - 0 - - - M10_HAS_DATA_FIFO - Enable Data FIFO on interface M10_AXI - 0 - - - M11_HAS_DATA_FIFO - Enable Data FIFO on interface M11_AXI - 0 - - - M12_HAS_DATA_FIFO - Enable Data FIFO on interface M12_AXI - 0 - - - M13_HAS_DATA_FIFO - Enable Data FIFO on interface M13_AXI - 0 - - - M14_HAS_DATA_FIFO - Enable Data FIFO on interface M14_AXI - 0 - - - M15_HAS_DATA_FIFO - Enable Data FIFO on interface M15_AXI - 0 - - - M16_HAS_DATA_FIFO - Enable Data FIFO on interface M16_AXI - 0 - - - M17_HAS_DATA_FIFO - Enable Data FIFO on interface M17_AXI - 0 - - - M18_HAS_DATA_FIFO - Enable Data FIFO on interface M18_AXI - 0 - - - M19_HAS_DATA_FIFO - Enable Data FIFO on interface M19_AXI - 0 - - - M20_HAS_DATA_FIFO - Enable Data FIFO on interface M20_AXI - 0 - - - M21_HAS_DATA_FIFO - Enable Data FIFO on interface M21_AXI - 0 - - - M22_HAS_DATA_FIFO - Enable Data FIFO on interface M22_AXI - 0 - - - M23_HAS_DATA_FIFO - Enable Data FIFO on interface M23_AXI - 0 - - - M24_HAS_DATA_FIFO - Enable Data FIFO on interface M24_AXI - 0 - - - M25_HAS_DATA_FIFO - Enable Data FIFO on interface M25_AXI - 0 - - - M26_HAS_DATA_FIFO - Enable Data FIFO on interface M26_AXI - 0 - - - M27_HAS_DATA_FIFO - Enable Data FIFO on interface M27_AXI - 0 - - - M28_HAS_DATA_FIFO - Enable Data FIFO on interface M28_AXI - 0 - - - M29_HAS_DATA_FIFO - Enable Data FIFO on interface M29_AXI - 0 - - - M30_HAS_DATA_FIFO - Enable Data FIFO on interface M30_AXI - 0 - - - M31_HAS_DATA_FIFO - Enable Data FIFO on interface M31_AXI - 0 - - - M32_HAS_DATA_FIFO - Enable Data FIFO on interface M32_AXI - 0 - - - M33_HAS_DATA_FIFO - Enable Data FIFO on interface M33_AXI - 0 - - - M34_HAS_DATA_FIFO - Enable Data FIFO on interface M34_AXI - 0 - - - M35_HAS_DATA_FIFO - Enable Data FIFO on interface M35_AXI - 0 - - - M36_HAS_DATA_FIFO - Enable Data FIFO on interface M36_AXI - 0 - - - M37_HAS_DATA_FIFO - Enable Data FIFO on interface M37_AXI - 0 - - - M38_HAS_DATA_FIFO - Enable Data FIFO on interface M38_AXI - 0 - - - M39_HAS_DATA_FIFO - Enable Data FIFO on interface M39_AXI - 0 - - - M40_HAS_DATA_FIFO - Enable Data FIFO on interface M40_AXI - 0 - - - M41_HAS_DATA_FIFO - Enable Data FIFO on interface M41_AXI - 0 - - - M42_HAS_DATA_FIFO - Enable Data FIFO on interface M42_AXI - 0 - - - M43_HAS_DATA_FIFO - Enable Data FIFO on interface M43_AXI - 0 - - - M44_HAS_DATA_FIFO - Enable Data FIFO on interface M44_AXI - 0 - - - M45_HAS_DATA_FIFO - Enable Data FIFO on interface M45_AXI - 0 - - - M46_HAS_DATA_FIFO - Enable Data FIFO on interface M46_AXI - 0 - - - M47_HAS_DATA_FIFO - Enable Data FIFO on interface M47_AXI - 0 - - - M48_HAS_DATA_FIFO - Enable Data FIFO on interface M48_AXI - 0 - - - M49_HAS_DATA_FIFO - Enable Data FIFO on interface M49_AXI - 0 - - - M50_HAS_DATA_FIFO - Enable Data FIFO on interface M50_AXI - 0 - - - M51_HAS_DATA_FIFO - Enable Data FIFO on interface M51_AXI - 0 - - - M52_HAS_DATA_FIFO - Enable Data FIFO on interface M52_AXI - 0 - - - M53_HAS_DATA_FIFO - Enable Data FIFO on interface M53_AXI - 0 - - - M54_HAS_DATA_FIFO - Enable Data FIFO on interface M54_AXI - 0 - - - M55_HAS_DATA_FIFO - Enable Data FIFO on interface M55_AXI - 0 - - - M56_HAS_DATA_FIFO - Enable Data FIFO on interface M56_AXI - 0 - - - M57_HAS_DATA_FIFO - Enable Data FIFO on interface M57_AXI - 0 - - - M58_HAS_DATA_FIFO - Enable Data FIFO on interface M58_AXI - 0 - - - M59_HAS_DATA_FIFO - Enable Data FIFO on interface M59_AXI - 0 - - - M60_HAS_DATA_FIFO - Enable Data FIFO on interface M60_AXI - 0 - - - M61_HAS_DATA_FIFO - Enable Data FIFO on interface M61_AXI - 0 - - - M62_HAS_DATA_FIFO - Enable Data FIFO on interface M62_AXI - 0 - - - M63_HAS_DATA_FIFO - Enable Data FIFO on interface M63_AXI - 0 - - - S00_HAS_REGSLICE - Enable Register Slice on interface S00_AXI - 4 - - - S01_HAS_REGSLICE - Enable Register Slice on interface S01_AXI - 0 - - - S02_HAS_REGSLICE - Enable Register Slice on interface S02_AXI - 0 - - - S03_HAS_REGSLICE - Enable Register Slice on interface S03_AXI - 0 - - - S04_HAS_REGSLICE - Enable Register Slice on interface S04_AXI - 0 - - - S05_HAS_REGSLICE - Enable Register Slice on interface S05_AXI - 0 - - - S06_HAS_REGSLICE - Enable Register Slice on interface S06_AXI - 0 - - - S07_HAS_REGSLICE - Enable Register Slice on interface S07_AXI - 0 - - - S08_HAS_REGSLICE - Enable Register Slice on interface S08_AXI - 0 - - - S09_HAS_REGSLICE - Enable Register Slice on interface S09_AXI - 0 - - - S10_HAS_REGSLICE - Enable Register Slice on interface S10_AXI - 0 - - - S11_HAS_REGSLICE - Enable Register Slice on interface S11_AXI - 0 - - - S12_HAS_REGSLICE - Enable Register Slice on interface S12_AXI - 0 - - - S13_HAS_REGSLICE - Enable Register Slice on interface S13_AXI - 0 - - - S14_HAS_REGSLICE - Enable Register Slice on interface S14_AXI - 0 - - - S15_HAS_REGSLICE - Enable Register Slice on interface S15_AXI - 0 - - - S00_HAS_DATA_FIFO - Enable Data FIFO on interface S00_AXI - 2 - - - S01_HAS_DATA_FIFO - Enable Data FIFO on interface S01_AXI - 0 - - - S02_HAS_DATA_FIFO - Enable Data FIFO on interface S02_AXI - 0 - - - S03_HAS_DATA_FIFO - Enable Data FIFO on interface S03_AXI - 0 - - - S04_HAS_DATA_FIFO - Enable Data FIFO on interface S04_AXI - 0 - - - S05_HAS_DATA_FIFO - Enable Data FIFO on interface S05_AXI - 0 - - - S06_HAS_DATA_FIFO - Enable Data FIFO on interface S06_AXI - 0 - - - S07_HAS_DATA_FIFO - Enable Data FIFO on interface S07_AXI - 0 - - - S08_HAS_DATA_FIFO - Enable Data FIFO on interface S08_AXI - 0 - - - S09_HAS_DATA_FIFO - Enable Data FIFO on interface S09_AXI - 0 - - - S10_HAS_DATA_FIFO - Enable Data FIFO on interface S10_AXI - 0 - - - S11_HAS_DATA_FIFO - Enable Data FIFO on interface S11_AXI - 0 - - - S12_HAS_DATA_FIFO - Enable Data FIFO on interface S12_AXI - 0 - - - S13_HAS_DATA_FIFO - Enable Data FIFO on interface S13_AXI - 0 - - - S14_HAS_DATA_FIFO - Enable Data FIFO on interface S14_AXI - 0 - - - S15_HAS_DATA_FIFO - Enable Data FIFO on interface S15_AXI - 0 - - - M00_ISSUANCE - Incicates whether M00_AXI connects to a secure slave - 0 - - - M01_ISSUANCE - Incicates whether M01_AXI connects to a secure slave - 0 - - - M02_ISSUANCE - Incicates whether M02_AXI connects to a secure slave - 0 - - - M03_ISSUANCE - Incicates whether M03_AXI connects to a secure slave - 0 - - - M04_ISSUANCE - Incicates whether M04_AXI connects to a secure slave - 0 - - - M05_ISSUANCE - Incicates whether M05_AXI connects to a secure slave - 0 - - - M06_ISSUANCE - Incicates whether M06_AXI connects to a secure slave - 0 - - - M07_ISSUANCE - Incicates whether M07_AXI connects to a secure slave - 0 - - - M08_ISSUANCE - Incicates whether M08_AXI connects to a secure slave - 0 - - - M09_ISSUANCE - Incicates whether M09_AXI connects to a secure slave - 0 - - - M10_ISSUANCE - Incicates whether M10_AXI connects to a secure slave - 0 - - - M11_ISSUANCE - Incicates whether M11_AXI connects to a secure slave - 0 - - - M12_ISSUANCE - Incicates whether M12_AXI connects to a secure slave - 0 - - - M13_ISSUANCE - Incicates whether M13_AXI connects to a secure slave - 0 - - - M14_ISSUANCE - Incicates whether M14_AXI connects to a secure slave - 0 - - - M15_ISSUANCE - Incicates whether M15_AXI connects to a secure slave - 0 - - - M16_ISSUANCE - Incicates whether M16_AXI connects to a secure slave - 0 - - - M17_ISSUANCE - Incicates whether M17_AXI connects to a secure slave - 0 - - - M18_ISSUANCE - Incicates whether M18_AXI connects to a secure slave - 0 - - - M19_ISSUANCE - Incicates whether M19_AXI connects to a secure slave - 0 - - - M20_ISSUANCE - Incicates whether M20_AXI connects to a secure slave - 0 - - - M21_ISSUANCE - Incicates whether M21_AXI connects to a secure slave - 0 - - - M22_ISSUANCE - Incicates whether M22_AXI connects to a secure slave - 0 - - - M23_ISSUANCE - Incicates whether M23_AXI connects to a secure slave - 0 - - - M24_ISSUANCE - Incicates whether M24_AXI connects to a secure slave - 0 - - - M25_ISSUANCE - Incicates whether M25_AXI connects to a secure slave - 0 - - - M26_ISSUANCE - Incicates whether M26_AXI connects to a secure slave - 0 - - - M27_ISSUANCE - Incicates whether M27_AXI connects to a secure slave - 0 - - - M28_ISSUANCE - Incicates whether M28_AXI connects to a secure slave - 0 - - - M29_ISSUANCE - Incicates whether M29_AXI connects to a secure slave - 0 - - - M30_ISSUANCE - Incicates whether M30_AXI connects to a secure slave - 0 - - - M31_ISSUANCE - Incicates whether M31_AXI connects to a secure slave - 0 - - - M32_ISSUANCE - Incicates whether M32_AXI connects to a secure slave - 0 - - - M33_ISSUANCE - Incicates whether M33_AXI connects to a secure slave - 0 - - - M34_ISSUANCE - Incicates whether M34_AXI connects to a secure slave - 0 - - - M35_ISSUANCE - Incicates whether M35_AXI connects to a secure slave - 0 - - - M36_ISSUANCE - Incicates whether M36_AXI connects to a secure slave - 0 - - - M37_ISSUANCE - Incicates whether M37_AXI connects to a secure slave - 0 - - - M38_ISSUANCE - Incicates whether M38_AXI connects to a secure slave - 0 - - - M39_ISSUANCE - Incicates whether M39_AXI connects to a secure slave - 0 - - - M40_ISSUANCE - Incicates whether M40_AXI connects to a secure slave - 0 - - - M41_ISSUANCE - Incicates whether M41_AXI connects to a secure slave - 0 - - - M42_ISSUANCE - Incicates whether M42_AXI connects to a secure slave - 0 - - - M43_ISSUANCE - Incicates whether M43_AXI connects to a secure slave - 0 - - - M44_ISSUANCE - Incicates whether M44_AXI connects to a secure slave - 0 - - - M45_ISSUANCE - Incicates whether M45_AXI connects to a secure slave - 0 - - - M46_ISSUANCE - Incicates whether M46_AXI connects to a secure slave - 0 - - - M47_ISSUANCE - Incicates whether M47_AXI connects to a secure slave - 0 - - - M48_ISSUANCE - Incicates whether M48_AXI connects to a secure slave - 0 - - - M49_ISSUANCE - Incicates whether M49_AXI connects to a secure slave - 0 - - - M50_ISSUANCE - Incicates whether M50_AXI connects to a secure slave - 0 - - - M51_ISSUANCE - Incicates whether M51_AXI connects to a secure slave - 0 - - - M52_ISSUANCE - Incicates whether M52_AXI connects to a secure slave - 0 - - - M53_ISSUANCE - Incicates whether M53_AXI connects to a secure slave - 0 - - - M54_ISSUANCE - Incicates whether M54_AXI connects to a secure slave - 0 - - - M55_ISSUANCE - Incicates whether M55_AXI connects to a secure slave - 0 - - - M56_ISSUANCE - Incicates whether M56_AXI connects to a secure slave - 0 - - - M57_ISSUANCE - Incicates whether M57_AXI connects to a secure slave - 0 - - - M58_ISSUANCE - Incicates whether M58_AXI connects to a secure slave - 0 - - - M59_ISSUANCE - Incicates whether M59_AXI connects to a secure slave - 0 - - - M60_ISSUANCE - Incicates whether M60_AXI connects to a secure slave - 0 - - - M61_ISSUANCE - Incicates whether M61_AXI connects to a secure slave - 0 - - - M62_ISSUANCE - Incicates whether M62_AXI connects to a secure slave - 0 - - - M63_ISSUANCE - Incicates whether M63_AXI connects to a secure slave - 0 - - - M00_SECURE - Incicates whether M00_AXI connects to a secure slave - 0 - - - M01_SECURE - Incicates whether M01_AXI connects to a secure slave - 0 - - - M02_SECURE - Incicates whether M02_AXI connects to a secure slave - 0 - - - M03_SECURE - Incicates whether M03_AXI connects to a secure slave - 0 - - - M04_SECURE - Incicates whether M04_AXI connects to a secure slave - 0 - - - M05_SECURE - Incicates whether M05_AXI connects to a secure slave - 0 - - - M06_SECURE - Incicates whether M06_AXI connects to a secure slave - 0 - - - M07_SECURE - Incicates whether M07_AXI connects to a secure slave - 0 - - - M08_SECURE - Incicates whether M08_AXI connects to a secure slave - 0 - - - M09_SECURE - Incicates whether M09_AXI connects to a secure slave - 0 - - - M10_SECURE - Incicates whether M10_AXI connects to a secure slave - 0 - - - M11_SECURE - Incicates whether M11_AXI connects to a secure slave - 0 - - - M12_SECURE - Incicates whether M12_AXI connects to a secure slave - 0 - - - M13_SECURE - Incicates whether M13_AXI connects to a secure slave - 0 - - - M14_SECURE - Incicates whether M14_AXI connects to a secure slave - 0 - - - M15_SECURE - Incicates whether M15_AXI connects to a secure slave - 0 - - - M16_SECURE - Incicates whether M16_AXI connects to a secure slave - 0 - - - M17_SECURE - Incicates whether M17_AXI connects to a secure slave - 0 - - - M18_SECURE - Incicates whether M18_AXI connects to a secure slave - 0 - - - M19_SECURE - Incicates whether M19_AXI connects to a secure slave - 0 - - - M20_SECURE - Incicates whether M20_AXI connects to a secure slave - 0 - - - M21_SECURE - Incicates whether M21_AXI connects to a secure slave - 0 - - - M22_SECURE - Incicates whether M22_AXI connects to a secure slave - 0 - - - M23_SECURE - Incicates whether M23_AXI connects to a secure slave - 0 - - - M24_SECURE - Incicates whether M24_AXI connects to a secure slave - 0 - - - M25_SECURE - Incicates whether M25_AXI connects to a secure slave - 0 - - - M26_SECURE - Incicates whether M26_AXI connects to a secure slave - 0 - - - M27_SECURE - Incicates whether M27_AXI connects to a secure slave - 0 - - - M28_SECURE - Incicates whether M28_AXI connects to a secure slave - 0 - - - M29_SECURE - Incicates whether M29_AXI connects to a secure slave - 0 - - - M30_SECURE - Incicates whether M30_AXI connects to a secure slave - 0 - - - M31_SECURE - Incicates whether M31_AXI connects to a secure slave - 0 - - - M32_SECURE - Incicates whether M32_AXI connects to a secure slave - 0 - - - M33_SECURE - Incicates whether M33_AXI connects to a secure slave - 0 - - - M34_SECURE - Incicates whether M34_AXI connects to a secure slave - 0 - - - M35_SECURE - Incicates whether M35_AXI connects to a secure slave - 0 - - - M36_SECURE - Incicates whether M36_AXI connects to a secure slave - 0 - - - M37_SECURE - Incicates whether M37_AXI connects to a secure slave - 0 - - - M38_SECURE - Incicates whether M38_AXI connects to a secure slave - 0 - - - M39_SECURE - Incicates whether M39_AXI connects to a secure slave - 0 - - - M40_SECURE - Incicates whether M40_AXI connects to a secure slave - 0 - - - M41_SECURE - Incicates whether M41_AXI connects to a secure slave - 0 - - - M42_SECURE - Incicates whether M42_AXI connects to a secure slave - 0 - - - M43_SECURE - Incicates whether M43_AXI connects to a secure slave - 0 - - - M44_SECURE - Incicates whether M44_AXI connects to a secure slave - 0 - - - M45_SECURE - Incicates whether M45_AXI connects to a secure slave - 0 - - - M46_SECURE - Incicates whether M46_AXI connects to a secure slave - 0 - - - M47_SECURE - Incicates whether M47_AXI connects to a secure slave - 0 - - - M48_SECURE - Incicates whether M48_AXI connects to a secure slave - 0 - - - M49_SECURE - Incicates whether M49_AXI connects to a secure slave - 0 - - - M50_SECURE - Incicates whether M50_AXI connects to a secure slave - 0 - - - M51_SECURE - Incicates whether M51_AXI connects to a secure slave - 0 - - - M52_SECURE - Incicates whether M52_AXI connects to a secure slave - 0 - - - M53_SECURE - Incicates whether M53_AXI connects to a secure slave - 0 - - - M54_SECURE - Incicates whether M54_AXI connects to a secure slave - 0 - - - M55_SECURE - Incicates whether M55_AXI connects to a secure slave - 0 - - - M56_SECURE - Incicates whether M56_AXI connects to a secure slave - 0 - - - M57_SECURE - Incicates whether M57_AXI connects to a secure slave - 0 - - - M58_SECURE - Incicates whether M58_AXI connects to a secure slave - 0 - - - M59_SECURE - Incicates whether M59_AXI connects to a secure slave - 0 - - - M60_SECURE - Incicates whether M60_AXI connects to a secure slave - 0 - - - M61_SECURE - Incicates whether M61_AXI connects to a secure slave - 0 - - - M62_SECURE - Incicates whether M62_AXI connects to a secure slave - 0 - - - M63_SECURE - Incicates whether M63_AXI connects to a secure slave - 0 - - - S00_ARB_PRIORITY - Controls S00_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S01_ARB_PRIORITY - Controls S01_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S02_ARB_PRIORITY - Controls S02_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S03_ARB_PRIORITY - Controls S03_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S04_ARB_PRIORITY - Controls S04_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S05_ARB_PRIORITY - Controls S05_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S06_ARB_PRIORITY - Controls S06_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S07_ARB_PRIORITY - Controls S07_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S08_ARB_PRIORITY - Controls S08_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S09_ARB_PRIORITY - Controls S09_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S10_ARB_PRIORITY - Controls S10_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S11_ARB_PRIORITY - Controls S11_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S12_ARB_PRIORITY - Controls S12_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S13_ARB_PRIORITY - Controls S13_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S14_ARB_PRIORITY - Controls S14_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S15_ARB_PRIORITY - Controls S15_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - Component_Name - Arty_Z7_20_axi_mem_intercon_0 - - - - - AXI Interconnect - 12 - - - - - - - - 2016.4 - - - - + + xilinx.com + customized_ip + Arty_Z7_20_axi_mem_intercon_0 + 1.0 + + + choice_list_40181835 + 32 + 64 + 128 + 256 + 512 + 1024 + + + choice_list_661c4a03 + 2 + 4 + 8 + 16 + 32 + 64 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_76d086ea + 0 + 1 + 2 + + + choice_pairs_ab2668a2 + 0 + 1 + 2 + + + choice_pairs_b6c9535e + 0 + 1 + 3 + 4 + + + The AXI Interconnect IP connects one or more AXI memory-mapped master devices to one or more AXI memory mapped slave devices + + + NUM_SI + Number of Slave Interfaces + 2 + + + NUM_MI + Number of Master Interfaces + 1 + + + STRATEGY + Interconnect Optimization Strategy + 0 + + + ENABLE_ADVANCED_OPTIONS + Enable Advanced Configuration Options + 0 + + + ENABLE_PROTOCOL_CHECKERS + Enable Protocol Checkers and mark interfaces for debug + 0 + + + XBAR_DATA_WIDTH + Data Width of the AXI Crossbar + 32 + + + PCHK_WAITS + Maximum number of idle cycles for READY monitoring + 0 + + + PCHK_MAX_RD_BURSTS + Maximum outstanding READ Transactions per ID + 2 + + + PCHK_MAX_WR_BURSTS + Maximum outstanding WRITE Transactions per ID + 2 + + + SYNCHRONIZATION_STAGES + Synchronization Stages + 2 + + + M00_HAS_REGSLICE + Enable Register Slice on interface M00_AXI + 0 + + + M01_HAS_REGSLICE + Enable Register Slice on interface M01_AXI + 0 + + + M02_HAS_REGSLICE + Enable Register Slice on interface M02_AXI + 0 + + + M03_HAS_REGSLICE + Enable Register Slice on interface M03_AXI + 0 + + + M04_HAS_REGSLICE + Enable Register Slice on interface M04_AXI + 0 + + + M05_HAS_REGSLICE + Enable Register Slice on interface M05_AXI + 0 + + + M06_HAS_REGSLICE + Enable Register Slice on interface M06_AXI + 0 + + + M07_HAS_REGSLICE + Enable Register Slice on interface M07_AXI + 0 + + + M08_HAS_REGSLICE + Enable Register Slice on interface M08_AXI + 0 + + + M09_HAS_REGSLICE + Enable Register Slice on interface M09_AXI + 0 + + + M10_HAS_REGSLICE + Enable Register Slice on interface M10_AXI + 0 + + + M11_HAS_REGSLICE + Enable Register Slice on interface M11_AXI + 0 + + + M12_HAS_REGSLICE + Enable Register Slice on interface M12_AXI + 0 + + + M13_HAS_REGSLICE + Enable Register Slice on interface M13_AXI + 0 + + + M14_HAS_REGSLICE + Enable Register Slice on interface M14_AXI + 0 + + + M15_HAS_REGSLICE + Enable Register Slice on interface M15_AXI + 0 + + + M16_HAS_REGSLICE + Enable Register Slice on interface M16_AXI + 0 + + + M17_HAS_REGSLICE + Enable Register Slice on interface M17_AXI + 0 + + + M18_HAS_REGSLICE + Enable Register Slice on interface M18_AXI + 0 + + + M19_HAS_REGSLICE + Enable Register Slice on interface M19_AXI + 0 + + + M20_HAS_REGSLICE + Enable Register Slice on interface M20_AXI + 0 + + + M21_HAS_REGSLICE + Enable Register Slice on interface M21_AXI + 0 + + + M22_HAS_REGSLICE + Enable Register Slice on interface M22_AXI + 0 + + + M23_HAS_REGSLICE + Enable Register Slice on interface M23_AXI + 0 + + + M24_HAS_REGSLICE + Enable Register Slice on interface M24_AXI + 0 + + + M25_HAS_REGSLICE + Enable Register Slice on interface M25_AXI + 0 + + + M26_HAS_REGSLICE + Enable Register Slice on interface M26_AXI + 0 + + + M27_HAS_REGSLICE + Enable Register Slice on interface M27_AXI + 0 + + + M28_HAS_REGSLICE + Enable Register Slice on interface M28_AXI + 0 + + + M29_HAS_REGSLICE + Enable Register Slice on interface M29_AXI + 0 + + + M30_HAS_REGSLICE + Enable Register Slice on interface M30_AXI + 0 + + + M31_HAS_REGSLICE + Enable Register Slice on interface M31_AXI + 0 + + + M32_HAS_REGSLICE + Enable Register Slice on interface M32_AXI + 0 + + + M33_HAS_REGSLICE + Enable Register Slice on interface M33_AXI + 0 + + + M34_HAS_REGSLICE + Enable Register Slice on interface M34_AXI + 0 + + + M35_HAS_REGSLICE + Enable Register Slice on interface M35_AXI + 0 + + + M36_HAS_REGSLICE + Enable Register Slice on interface M36_AXI + 0 + + + M37_HAS_REGSLICE + Enable Register Slice on interface M37_AXI + 0 + + + M38_HAS_REGSLICE + Enable Register Slice on interface M38_AXI + 0 + + + M39_HAS_REGSLICE + Enable Register Slice on interface M39_AXI + 0 + + + M40_HAS_REGSLICE + Enable Register Slice on interface M40_AXI + 0 + + + M41_HAS_REGSLICE + Enable Register Slice on interface M41_AXI + 0 + + + M42_HAS_REGSLICE + Enable Register Slice on interface M42_AXI + 0 + + + M43_HAS_REGSLICE + Enable Register Slice on interface M43_AXI + 0 + + + M44_HAS_REGSLICE + Enable Register Slice on interface M44_AXI + 0 + + + M45_HAS_REGSLICE + Enable Register Slice on interface M45_AXI + 0 + + + M46_HAS_REGSLICE + Enable Register Slice on interface M46_AXI + 0 + + + M47_HAS_REGSLICE + Enable Register Slice on interface M47_AXI + 0 + + + M48_HAS_REGSLICE + Enable Register Slice on interface M48_AXI + 0 + + + M49_HAS_REGSLICE + Enable Register Slice on interface M49_AXI + 0 + + + M50_HAS_REGSLICE + Enable Register Slice on interface M50_AXI + 0 + + + M51_HAS_REGSLICE + Enable Register Slice on interface M51_AXI + 0 + + + M52_HAS_REGSLICE + Enable Register Slice on interface M52_AXI + 0 + + + M53_HAS_REGSLICE + Enable Register Slice on interface M53_AXI + 0 + + + M54_HAS_REGSLICE + Enable Register Slice on interface M54_AXI + 0 + + + M55_HAS_REGSLICE + Enable Register Slice on interface M55_AXI + 0 + + + M56_HAS_REGSLICE + Enable Register Slice on interface M56_AXI + 0 + + + M57_HAS_REGSLICE + Enable Register Slice on interface M57_AXI + 0 + + + M58_HAS_REGSLICE + Enable Register Slice on interface M58_AXI + 0 + + + M59_HAS_REGSLICE + Enable Register Slice on interface M59_AXI + 0 + + + M60_HAS_REGSLICE + Enable Register Slice on interface M60_AXI + 0 + + + M61_HAS_REGSLICE + Enable Register Slice on interface M61_AXI + 0 + + + M62_HAS_REGSLICE + Enable Register Slice on interface M62_AXI + 0 + + + M63_HAS_REGSLICE + Enable Register Slice on interface M63_AXI + 0 + + + M00_HAS_DATA_FIFO + Enable Data FIFO on interface M00_AXI + 0 + + + M01_HAS_DATA_FIFO + Enable Data FIFO on interface M01_AXI + 0 + + + M02_HAS_DATA_FIFO + Enable Data FIFO on interface M02_AXI + 0 + + + M03_HAS_DATA_FIFO + Enable Data FIFO on interface M03_AXI + 0 + + + M04_HAS_DATA_FIFO + Enable Data FIFO on interface M04_AXI + 0 + + + M05_HAS_DATA_FIFO + Enable Data FIFO on interface M05_AXI + 0 + + + M06_HAS_DATA_FIFO + Enable Data FIFO on interface M06_AXI + 0 + + + M07_HAS_DATA_FIFO + Enable Data FIFO on interface M07_AXI + 0 + + + M08_HAS_DATA_FIFO + Enable Data FIFO on interface M08_AXI + 0 + + + M09_HAS_DATA_FIFO + Enable Data FIFO on interface M09_AXI + 0 + + + M10_HAS_DATA_FIFO + Enable Data FIFO on interface M10_AXI + 0 + + + M11_HAS_DATA_FIFO + Enable Data FIFO on interface M11_AXI + 0 + + + M12_HAS_DATA_FIFO + Enable Data FIFO on interface M12_AXI + 0 + + + M13_HAS_DATA_FIFO + Enable Data FIFO on interface M13_AXI + 0 + + + M14_HAS_DATA_FIFO + Enable Data FIFO on interface M14_AXI + 0 + + + M15_HAS_DATA_FIFO + Enable Data FIFO on interface M15_AXI + 0 + + + M16_HAS_DATA_FIFO + Enable Data FIFO on interface M16_AXI + 0 + + + M17_HAS_DATA_FIFO + Enable Data FIFO on interface M17_AXI + 0 + + + M18_HAS_DATA_FIFO + Enable Data FIFO on interface M18_AXI + 0 + + + M19_HAS_DATA_FIFO + Enable Data FIFO on interface M19_AXI + 0 + + + M20_HAS_DATA_FIFO + Enable Data FIFO on interface M20_AXI + 0 + + + M21_HAS_DATA_FIFO + Enable Data FIFO on interface M21_AXI + 0 + + + M22_HAS_DATA_FIFO + Enable Data FIFO on interface M22_AXI + 0 + + + M23_HAS_DATA_FIFO + Enable Data FIFO on interface M23_AXI + 0 + + + M24_HAS_DATA_FIFO + Enable Data FIFO on interface M24_AXI + 0 + + + M25_HAS_DATA_FIFO + Enable Data FIFO on interface M25_AXI + 0 + + + M26_HAS_DATA_FIFO + Enable Data FIFO on interface M26_AXI + 0 + + + M27_HAS_DATA_FIFO + Enable Data FIFO on interface M27_AXI + 0 + + + M28_HAS_DATA_FIFO + Enable Data FIFO on interface M28_AXI + 0 + + + M29_HAS_DATA_FIFO + Enable Data FIFO on interface M29_AXI + 0 + + + M30_HAS_DATA_FIFO + Enable Data FIFO on interface M30_AXI + 0 + + + M31_HAS_DATA_FIFO + Enable Data FIFO on interface M31_AXI + 0 + + + M32_HAS_DATA_FIFO + Enable Data FIFO on interface M32_AXI + 0 + + + M33_HAS_DATA_FIFO + Enable Data FIFO on interface M33_AXI + 0 + + + M34_HAS_DATA_FIFO + Enable Data FIFO on interface M34_AXI + 0 + + + M35_HAS_DATA_FIFO + Enable Data FIFO on interface M35_AXI + 0 + + + M36_HAS_DATA_FIFO + Enable Data FIFO on interface M36_AXI + 0 + + + M37_HAS_DATA_FIFO + Enable Data FIFO on interface M37_AXI + 0 + + + M38_HAS_DATA_FIFO + Enable Data FIFO on interface M38_AXI + 0 + + + M39_HAS_DATA_FIFO + Enable Data FIFO on interface M39_AXI + 0 + + + M40_HAS_DATA_FIFO + Enable Data FIFO on interface M40_AXI + 0 + + + M41_HAS_DATA_FIFO + Enable Data FIFO on interface M41_AXI + 0 + + + M42_HAS_DATA_FIFO + Enable Data FIFO on interface M42_AXI + 0 + + + M43_HAS_DATA_FIFO + Enable Data FIFO on interface M43_AXI + 0 + + + M44_HAS_DATA_FIFO + Enable Data FIFO on interface M44_AXI + 0 + + + M45_HAS_DATA_FIFO + Enable Data FIFO on interface M45_AXI + 0 + + + M46_HAS_DATA_FIFO + Enable Data FIFO on interface M46_AXI + 0 + + + M47_HAS_DATA_FIFO + Enable Data FIFO on interface M47_AXI + 0 + + + M48_HAS_DATA_FIFO + Enable Data FIFO on interface M48_AXI + 0 + + + M49_HAS_DATA_FIFO + Enable Data FIFO on interface M49_AXI + 0 + + + M50_HAS_DATA_FIFO + Enable Data FIFO on interface M50_AXI + 0 + + + M51_HAS_DATA_FIFO + Enable Data FIFO on interface M51_AXI + 0 + + + M52_HAS_DATA_FIFO + Enable Data FIFO on interface M52_AXI + 0 + + + M53_HAS_DATA_FIFO + Enable Data FIFO on interface M53_AXI + 0 + + + M54_HAS_DATA_FIFO + Enable Data FIFO on interface M54_AXI + 0 + + + M55_HAS_DATA_FIFO + Enable Data FIFO on interface M55_AXI + 0 + + + M56_HAS_DATA_FIFO + Enable Data FIFO on interface M56_AXI + 0 + + + M57_HAS_DATA_FIFO + Enable Data FIFO on interface M57_AXI + 0 + + + M58_HAS_DATA_FIFO + Enable Data FIFO on interface M58_AXI + 0 + + + M59_HAS_DATA_FIFO + Enable Data FIFO on interface M59_AXI + 0 + + + M60_HAS_DATA_FIFO + Enable Data FIFO on interface M60_AXI + 0 + + + M61_HAS_DATA_FIFO + Enable Data FIFO on interface M61_AXI + 0 + + + M62_HAS_DATA_FIFO + Enable Data FIFO on interface M62_AXI + 0 + + + M63_HAS_DATA_FIFO + Enable Data FIFO on interface M63_AXI + 0 + + + S00_HAS_REGSLICE + Enable Register Slice on interface S00_AXI + 4 + + + S01_HAS_REGSLICE + Enable Register Slice on interface S01_AXI + 0 + + + S02_HAS_REGSLICE + Enable Register Slice on interface S02_AXI + 0 + + + S03_HAS_REGSLICE + Enable Register Slice on interface S03_AXI + 0 + + + S04_HAS_REGSLICE + Enable Register Slice on interface S04_AXI + 0 + + + S05_HAS_REGSLICE + Enable Register Slice on interface S05_AXI + 0 + + + S06_HAS_REGSLICE + Enable Register Slice on interface S06_AXI + 0 + + + S07_HAS_REGSLICE + Enable Register Slice on interface S07_AXI + 0 + + + S08_HAS_REGSLICE + Enable Register Slice on interface S08_AXI + 0 + + + S09_HAS_REGSLICE + Enable Register Slice on interface S09_AXI + 0 + + + S10_HAS_REGSLICE + Enable Register Slice on interface S10_AXI + 0 + + + S11_HAS_REGSLICE + Enable Register Slice on interface S11_AXI + 0 + + + S12_HAS_REGSLICE + Enable Register Slice on interface S12_AXI + 0 + + + S13_HAS_REGSLICE + Enable Register Slice on interface S13_AXI + 0 + + + S14_HAS_REGSLICE + Enable Register Slice on interface S14_AXI + 0 + + + S15_HAS_REGSLICE + Enable Register Slice on interface S15_AXI + 0 + + + S00_HAS_DATA_FIFO + Enable Data FIFO on interface S00_AXI + 2 + + + S01_HAS_DATA_FIFO + Enable Data FIFO on interface S01_AXI + 0 + + + S02_HAS_DATA_FIFO + Enable Data FIFO on interface S02_AXI + 0 + + + S03_HAS_DATA_FIFO + Enable Data FIFO on interface S03_AXI + 0 + + + S04_HAS_DATA_FIFO + Enable Data FIFO on interface S04_AXI + 0 + + + S05_HAS_DATA_FIFO + Enable Data FIFO on interface S05_AXI + 0 + + + S06_HAS_DATA_FIFO + Enable Data FIFO on interface S06_AXI + 0 + + + S07_HAS_DATA_FIFO + Enable Data FIFO on interface S07_AXI + 0 + + + S08_HAS_DATA_FIFO + Enable Data FIFO on interface S08_AXI + 0 + + + S09_HAS_DATA_FIFO + Enable Data FIFO on interface S09_AXI + 0 + + + S10_HAS_DATA_FIFO + Enable Data FIFO on interface S10_AXI + 0 + + + S11_HAS_DATA_FIFO + Enable Data FIFO on interface S11_AXI + 0 + + + S12_HAS_DATA_FIFO + Enable Data FIFO on interface S12_AXI + 0 + + + S13_HAS_DATA_FIFO + Enable Data FIFO on interface S13_AXI + 0 + + + S14_HAS_DATA_FIFO + Enable Data FIFO on interface S14_AXI + 0 + + + S15_HAS_DATA_FIFO + Enable Data FIFO on interface S15_AXI + 0 + + + M00_ISSUANCE + Incicates whether M00_AXI connects to a secure slave + 0 + + + M01_ISSUANCE + Incicates whether M01_AXI connects to a secure slave + 0 + + + M02_ISSUANCE + Incicates whether M02_AXI connects to a secure slave + 0 + + + M03_ISSUANCE + Incicates whether M03_AXI connects to a secure slave + 0 + + + M04_ISSUANCE + Incicates whether M04_AXI connects to a secure slave + 0 + + + M05_ISSUANCE + Incicates whether M05_AXI connects to a secure slave + 0 + + + M06_ISSUANCE + Incicates whether M06_AXI connects to a secure slave + 0 + + + M07_ISSUANCE + Incicates whether M07_AXI connects to a secure slave + 0 + + + M08_ISSUANCE + Incicates whether M08_AXI connects to a secure slave + 0 + + + M09_ISSUANCE + Incicates whether M09_AXI connects to a secure slave + 0 + + + M10_ISSUANCE + Incicates whether M10_AXI connects to a secure slave + 0 + + + M11_ISSUANCE + Incicates whether M11_AXI connects to a secure slave + 0 + + + M12_ISSUANCE + Incicates whether M12_AXI connects to a secure slave + 0 + + + M13_ISSUANCE + Incicates whether M13_AXI connects to a secure slave + 0 + + + M14_ISSUANCE + Incicates whether M14_AXI connects to a secure slave + 0 + + + M15_ISSUANCE + Incicates whether M15_AXI connects to a secure slave + 0 + + + M16_ISSUANCE + Incicates whether M16_AXI connects to a secure slave + 0 + + + M17_ISSUANCE + Incicates whether M17_AXI connects to a secure slave + 0 + + + M18_ISSUANCE + Incicates whether M18_AXI connects to a secure slave + 0 + + + M19_ISSUANCE + Incicates whether M19_AXI connects to a secure slave + 0 + + + M20_ISSUANCE + Incicates whether M20_AXI connects to a secure slave + 0 + + + M21_ISSUANCE + Incicates whether M21_AXI connects to a secure slave + 0 + + + M22_ISSUANCE + Incicates whether M22_AXI connects to a secure slave + 0 + + + M23_ISSUANCE + Incicates whether M23_AXI connects to a secure slave + 0 + + + M24_ISSUANCE + Incicates whether M24_AXI connects to a secure slave + 0 + + + M25_ISSUANCE + Incicates whether M25_AXI connects to a secure slave + 0 + + + M26_ISSUANCE + Incicates whether M26_AXI connects to a secure slave + 0 + + + M27_ISSUANCE + Incicates whether M27_AXI connects to a secure slave + 0 + + + M28_ISSUANCE + Incicates whether M28_AXI connects to a secure slave + 0 + + + M29_ISSUANCE + Incicates whether M29_AXI connects to a secure slave + 0 + + + M30_ISSUANCE + Incicates whether M30_AXI connects to a secure slave + 0 + + + M31_ISSUANCE + Incicates whether M31_AXI connects to a secure slave + 0 + + + M32_ISSUANCE + Incicates whether M32_AXI connects to a secure slave + 0 + + + M33_ISSUANCE + Incicates whether M33_AXI connects to a secure slave + 0 + + + M34_ISSUANCE + Incicates whether M34_AXI connects to a secure slave + 0 + + + M35_ISSUANCE + Incicates whether M35_AXI connects to a secure slave + 0 + + + M36_ISSUANCE + Incicates whether M36_AXI connects to a secure slave + 0 + + + M37_ISSUANCE + Incicates whether M37_AXI connects to a secure slave + 0 + + + M38_ISSUANCE + Incicates whether M38_AXI connects to a secure slave + 0 + + + M39_ISSUANCE + Incicates whether M39_AXI connects to a secure slave + 0 + + + M40_ISSUANCE + Incicates whether M40_AXI connects to a secure slave + 0 + + + M41_ISSUANCE + Incicates whether M41_AXI connects to a secure slave + 0 + + + M42_ISSUANCE + Incicates whether M42_AXI connects to a secure slave + 0 + + + M43_ISSUANCE + Incicates whether M43_AXI connects to a secure slave + 0 + + + M44_ISSUANCE + Incicates whether M44_AXI connects to a secure slave + 0 + + + M45_ISSUANCE + Incicates whether M45_AXI connects to a secure slave + 0 + + + M46_ISSUANCE + Incicates whether M46_AXI connects to a secure slave + 0 + + + M47_ISSUANCE + Incicates whether M47_AXI connects to a secure slave + 0 + + + M48_ISSUANCE + Incicates whether M48_AXI connects to a secure slave + 0 + + + M49_ISSUANCE + Incicates whether M49_AXI connects to a secure slave + 0 + + + M50_ISSUANCE + Incicates whether M50_AXI connects to a secure slave + 0 + + + M51_ISSUANCE + Incicates whether M51_AXI connects to a secure slave + 0 + + + M52_ISSUANCE + Incicates whether M52_AXI connects to a secure slave + 0 + + + M53_ISSUANCE + Incicates whether M53_AXI connects to a secure slave + 0 + + + M54_ISSUANCE + Incicates whether M54_AXI connects to a secure slave + 0 + + + M55_ISSUANCE + Incicates whether M55_AXI connects to a secure slave + 0 + + + M56_ISSUANCE + Incicates whether M56_AXI connects to a secure slave + 0 + + + M57_ISSUANCE + Incicates whether M57_AXI connects to a secure slave + 0 + + + M58_ISSUANCE + Incicates whether M58_AXI connects to a secure slave + 0 + + + M59_ISSUANCE + Incicates whether M59_AXI connects to a secure slave + 0 + + + M60_ISSUANCE + Incicates whether M60_AXI connects to a secure slave + 0 + + + M61_ISSUANCE + Incicates whether M61_AXI connects to a secure slave + 0 + + + M62_ISSUANCE + Incicates whether M62_AXI connects to a secure slave + 0 + + + M63_ISSUANCE + Incicates whether M63_AXI connects to a secure slave + 0 + + + M00_SECURE + Incicates whether M00_AXI connects to a secure slave + 0 + + + M01_SECURE + Incicates whether M01_AXI connects to a secure slave + 0 + + + M02_SECURE + Incicates whether M02_AXI connects to a secure slave + 0 + + + M03_SECURE + Incicates whether M03_AXI connects to a secure slave + 0 + + + M04_SECURE + Incicates whether M04_AXI connects to a secure slave + 0 + + + M05_SECURE + Incicates whether M05_AXI connects to a secure slave + 0 + + + M06_SECURE + Incicates whether M06_AXI connects to a secure slave + 0 + + + M07_SECURE + Incicates whether M07_AXI connects to a secure slave + 0 + + + M08_SECURE + Incicates whether M08_AXI connects to a secure slave + 0 + + + M09_SECURE + Incicates whether M09_AXI connects to a secure slave + 0 + + + M10_SECURE + Incicates whether M10_AXI connects to a secure slave + 0 + + + M11_SECURE + Incicates whether M11_AXI connects to a secure slave + 0 + + + M12_SECURE + Incicates whether M12_AXI connects to a secure slave + 0 + + + M13_SECURE + Incicates whether M13_AXI connects to a secure slave + 0 + + + M14_SECURE + Incicates whether M14_AXI connects to a secure slave + 0 + + + M15_SECURE + Incicates whether M15_AXI connects to a secure slave + 0 + + + M16_SECURE + Incicates whether M16_AXI connects to a secure slave + 0 + + + M17_SECURE + Incicates whether M17_AXI connects to a secure slave + 0 + + + M18_SECURE + Incicates whether M18_AXI connects to a secure slave + 0 + + + M19_SECURE + Incicates whether M19_AXI connects to a secure slave + 0 + + + M20_SECURE + Incicates whether M20_AXI connects to a secure slave + 0 + + + M21_SECURE + Incicates whether M21_AXI connects to a secure slave + 0 + + + M22_SECURE + Incicates whether M22_AXI connects to a secure slave + 0 + + + M23_SECURE + Incicates whether M23_AXI connects to a secure slave + 0 + + + M24_SECURE + Incicates whether M24_AXI connects to a secure slave + 0 + + + M25_SECURE + Incicates whether M25_AXI connects to a secure slave + 0 + + + M26_SECURE + Incicates whether M26_AXI connects to a secure slave + 0 + + + M27_SECURE + Incicates whether M27_AXI connects to a secure slave + 0 + + + M28_SECURE + Incicates whether M28_AXI connects to a secure slave + 0 + + + M29_SECURE + Incicates whether M29_AXI connects to a secure slave + 0 + + + M30_SECURE + Incicates whether M30_AXI connects to a secure slave + 0 + + + M31_SECURE + Incicates whether M31_AXI connects to a secure slave + 0 + + + M32_SECURE + Incicates whether M32_AXI connects to a secure slave + 0 + + + M33_SECURE + Incicates whether M33_AXI connects to a secure slave + 0 + + + M34_SECURE + Incicates whether M34_AXI connects to a secure slave + 0 + + + M35_SECURE + Incicates whether M35_AXI connects to a secure slave + 0 + + + M36_SECURE + Incicates whether M36_AXI connects to a secure slave + 0 + + + M37_SECURE + Incicates whether M37_AXI connects to a secure slave + 0 + + + M38_SECURE + Incicates whether M38_AXI connects to a secure slave + 0 + + + M39_SECURE + Incicates whether M39_AXI connects to a secure slave + 0 + + + M40_SECURE + Incicates whether M40_AXI connects to a secure slave + 0 + + + M41_SECURE + Incicates whether M41_AXI connects to a secure slave + 0 + + + M42_SECURE + Incicates whether M42_AXI connects to a secure slave + 0 + + + M43_SECURE + Incicates whether M43_AXI connects to a secure slave + 0 + + + M44_SECURE + Incicates whether M44_AXI connects to a secure slave + 0 + + + M45_SECURE + Incicates whether M45_AXI connects to a secure slave + 0 + + + M46_SECURE + Incicates whether M46_AXI connects to a secure slave + 0 + + + M47_SECURE + Incicates whether M47_AXI connects to a secure slave + 0 + + + M48_SECURE + Incicates whether M48_AXI connects to a secure slave + 0 + + + M49_SECURE + Incicates whether M49_AXI connects to a secure slave + 0 + + + M50_SECURE + Incicates whether M50_AXI connects to a secure slave + 0 + + + M51_SECURE + Incicates whether M51_AXI connects to a secure slave + 0 + + + M52_SECURE + Incicates whether M52_AXI connects to a secure slave + 0 + + + M53_SECURE + Incicates whether M53_AXI connects to a secure slave + 0 + + + M54_SECURE + Incicates whether M54_AXI connects to a secure slave + 0 + + + M55_SECURE + Incicates whether M55_AXI connects to a secure slave + 0 + + + M56_SECURE + Incicates whether M56_AXI connects to a secure slave + 0 + + + M57_SECURE + Incicates whether M57_AXI connects to a secure slave + 0 + + + M58_SECURE + Incicates whether M58_AXI connects to a secure slave + 0 + + + M59_SECURE + Incicates whether M59_AXI connects to a secure slave + 0 + + + M60_SECURE + Incicates whether M60_AXI connects to a secure slave + 0 + + + M61_SECURE + Incicates whether M61_AXI connects to a secure slave + 0 + + + M62_SECURE + Incicates whether M62_AXI connects to a secure slave + 0 + + + M63_SECURE + Incicates whether M63_AXI connects to a secure slave + 0 + + + S00_ARB_PRIORITY + Controls S00_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S01_ARB_PRIORITY + Controls S01_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S02_ARB_PRIORITY + Controls S02_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S03_ARB_PRIORITY + Controls S03_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S04_ARB_PRIORITY + Controls S04_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S05_ARB_PRIORITY + Controls S05_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S06_ARB_PRIORITY + Controls S06_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S07_ARB_PRIORITY + Controls S07_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S08_ARB_PRIORITY + Controls S08_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S09_ARB_PRIORITY + Controls S09_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S10_ARB_PRIORITY + Controls S10_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S11_ARB_PRIORITY + Controls S11_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S12_ARB_PRIORITY + Controls S12_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S13_ARB_PRIORITY + Controls S13_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S14_ARB_PRIORITY + Controls S14_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S15_ARB_PRIORITY + Controls S15_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + Component_Name + Arty_Z7_20_axi_mem_intercon_0 + + + + + AXI Interconnect + 12 + + + + + + + + + 2016.4 + + + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0.dcp b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0.dcp index 3cd7f28..ef6650f 100644 Binary files a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0.dcp and b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0.dcp differ diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0.xci b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0.xci index 2cbdaf2..fb94654 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0.xci +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0.xci @@ -11,7 +11,7 @@ 1 Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 - 142857132 + 118181816 1 1 1 @@ -24,7 +24,7 @@ 1 Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 - 142857132 + 118181816 0.000 32 0 @@ -32,7 +32,7 @@ 0 Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 64 - 142857132 + 118181816 0 0 0 @@ -43,7 +43,7 @@ 1 0 0 - 16 + 32 1 8 1 @@ -56,15 +56,15 @@ 0 Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 - 142857132 + 118181816 0.000 32 0 0 0 - + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 64 - 100000000 + 118181816 1 0 0 @@ -75,7 +75,7 @@ 0 1 0 - 8 + 32 2 1 1 @@ -87,25 +87,25 @@ 0 0 - - 100000000 + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 + 118181816 0.000 1 - - 100000000 + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 + 118181816 1 1 1 0 undef 0.000 - 4 + 1 0 0 1 - - 100000000 + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 + 118181816 0.000 9 0 @@ -166,7 +166,7 @@ 1 0 0 - 0 + 1 0 1 0 @@ -174,9 +174,9 @@ 0 1 0 - 4096 + 2048 4 - 16 + 32 1 32 1 @@ -186,17 +186,17 @@ 64 32 32 - 1 + 3 1 - 0 + 2 1 1 - 512 + 2048 4 - 8 + 32 1 0 - 32 + 8 1 9 32 @@ -231,7 +231,7 @@ 1 0 0 - 0 + 1 0 1 0 @@ -241,20 +241,20 @@ 0 1 0 - 4096 + 2048 4 - 16 + 32 1 - 1 + 3 1 - 0 + 2 1 1 - 512 + 2048 4 - 8 + 32 1 - 32 + 8 1 0 2 @@ -312,7 +312,7 @@ - + @@ -323,7 +323,9 @@ + + @@ -339,9 +341,19 @@ + + + + + + + + + + @@ -370,12 +382,17 @@ + + + + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0.xdc b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0.xdc index 8554767..c161fb0 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0.xdc +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0.xdc @@ -60,3 +60,8 @@ set_false_path -to [get_pins -leaf -of_objects [get_cells -hier *cdc_tig* -filte set_false_path -to [get_pins -hierarchical -filter {NAME =~*MM2S*LB_BUILT_IN*/*rstbt*/*PRE}] + + set_false_path -to [get_pins -hierarchical -filter {NAME =~*S2MM*LB_BUILT_IN*/*rstbt*/*PRE}] + set_false_path -from [get_cells -hierarchical -filter {NAME =~*S2MM*LB_BUILT_IN*/*rstbt*/*rst_reg_reg && IS_SEQUENTIAL}] + set_false_path -from [get_cells -hierarchical -filter {NAME =~*S2MM*LB_BUILT_IN*/*rstbt*/*rst_reg[*]}] + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0.xml b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0.xml index a23f480..6bde6be 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0.xml +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0.xml @@ -516,7 +516,7 @@ FREQ_HZ - 142857132 + 118181816 ID_WIDTH @@ -592,7 +592,7 @@ MAX_BURST_LENGTH - 16 + 32 PHASE @@ -783,7 +783,7 @@ FREQ_HZ - 100000000 + 118181816 ID_WIDTH @@ -859,7 +859,7 @@ MAX_BURST_LENGTH - 8 + 32 PHASE @@ -867,7 +867,7 @@ CLK_DOMAIN - + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 NUM_READ_THREADS @@ -889,7 +889,7 @@ - false + true @@ -984,7 +984,7 @@ FREQ_HZ - 142857132 + 118181816 PHASE @@ -1065,7 +1065,7 @@ TDATA_NUM_BYTES - 4 + 1 TDEST_WIDTH @@ -1097,7 +1097,7 @@ FREQ_HZ - 100000000 + 118181816 PHASE @@ -1105,7 +1105,7 @@ CLK_DOMAIN - + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 LAYERED_METADATA @@ -1115,7 +1115,7 @@ - false + true @@ -1181,7 +1181,7 @@ - false + true @@ -1209,7 +1209,7 @@ FREQ_HZ - 142857132 + 118181816 PHASE @@ -1248,7 +1248,7 @@ FREQ_HZ - 100000000 + 118181816 PHASE @@ -1256,7 +1256,7 @@ CLK_DOMAIN - + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 ASSOCIATED_RESET @@ -1326,7 +1326,7 @@ FREQ_HZ - 142857132 + 118181816 PHASE @@ -1365,7 +1365,7 @@ FREQ_HZ - 100000000 + 118181816 PHASE @@ -1373,7 +1373,7 @@ CLK_DOMAIN - + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 ASSOCIATED_RESET @@ -1572,7 +1572,7 @@ - false + true @@ -2065,7 +2065,7 @@ - false + true @@ -2546,7 +2546,7 @@ - false + true @@ -4774,7 +4774,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re boundaryCRC - 289e09ca + 8521cd50 boundaryCRCversion @@ -4782,7 +4782,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re customizationCRC - c2d532f3 + 51024e51 customizationCRCversion @@ -4801,11 +4801,11 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re GENtimestamp - Fri Feb 24 23:57:49 UTC 2017 + Mon Mar 06 19:44:17 UTC 2017 boundaryCRC - 289e09ca + 8521cd50 boundaryCRCversion @@ -4813,7 +4813,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re customizationCRC - c2d532f3 + 51024e51 customizationCRCversion @@ -4859,7 +4859,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re boundaryCRC - 289e09ca + 8521cd50 boundaryCRCversion @@ -4867,7 +4867,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re customizationCRC - a091f06f + 0ee5ae47 customizationCRCversion @@ -4886,11 +4886,11 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re GENtimestamp - Fri Feb 24 23:57:49 UTC 2017 + Mon Mar 06 19:44:17 UTC 2017 boundaryCRC - 289e09ca + 8521cd50 boundaryCRCversion @@ -4898,7 +4898,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re customizationCRC - a091f06f + 0ee5ae47 customizationCRCversion @@ -4916,11 +4916,11 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re GENtimestamp - Sat Feb 25 00:08:17 UTC 2017 + Mon Mar 06 19:51:47 UTC 2017 boundaryCRC - 289e09ca + 8521cd50 boundaryCRCversion @@ -4928,7 +4928,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re customizationCRC - c2d532f3 + 51024e51 customizationCRCversion @@ -5041,7 +5041,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - false + true @@ -5064,7 +5064,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - false + true @@ -5460,7 +5460,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - false + true @@ -5484,7 +5484,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - false + true @@ -6437,7 +6437,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - false + true @@ -6461,7 +6461,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - false + true @@ -6485,7 +6485,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - false + true @@ -6509,7 +6509,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - false + true @@ -6533,7 +6533,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - false + true @@ -6557,7 +6557,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - false + true @@ -6577,7 +6577,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - false + true @@ -6600,7 +6600,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - false + true @@ -6624,7 +6624,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - false + true @@ -6648,7 +6648,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - false + true @@ -6668,7 +6668,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - false + true @@ -6688,7 +6688,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - false + true @@ -6711,7 +6711,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - false + true @@ -6738,7 +6738,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - false + true @@ -6761,7 +6761,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - false + true @@ -6781,7 +6781,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - false + true @@ -6811,7 +6811,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re in - 31 + 7 0 @@ -6828,7 +6828,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - false + true @@ -6838,7 +6838,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re in - 3 + 0 0 @@ -6849,13 +6849,13 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - 0xF + 0x1 - false + true @@ -6882,7 +6882,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - false + true @@ -6905,7 +6905,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - false + true @@ -6925,7 +6925,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - false + true @@ -6948,7 +6948,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - false + true @@ -6988,7 +6988,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - false + true @@ -7045,7 +7045,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re C_NUM_FSTORES - 1 + 3 C_USE_FSYNC @@ -7109,7 +7109,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re C_MM2S_LINEBUFFER_DEPTH - 4096 + 2048 C_MM2S_LINEBUFFER_THRESH @@ -7117,7 +7117,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re C_MM2S_MAX_BURST_LENGTH - 16 + 32 C_M_AXI_MM2S_ADDR_WIDTH @@ -7137,11 +7137,11 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re C_INCLUDE_S2MM - 0 + 1 C_S2MM_GENLOCK_MODE - 0 + 2 C_S2MM_GENLOCK_NUM_MASTERS @@ -7165,7 +7165,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re C_S2MM_LINEBUFFER_DEPTH - 512 + 2048 C_S2MM_LINEBUFFER_THRESH @@ -7173,7 +7173,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re C_S2MM_MAX_BURST_LENGTH - 8 + 32 C_M_AXI_S2MM_ADDR_WIDTH @@ -7185,7 +7185,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re C_S_AXIS_S2MM_TDATA_WIDTH - 32 + 8 C_S_AXIS_S2MM_TUSER_BITS @@ -7382,6 +7382,19 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re 128 256 + + choice_list_c20e298b + 128 + 256 + 512 + 1024 + 2048 + 4096 + 8192 + 16384 + 32768 + 65536 + choice_list_f28fe37e 1 @@ -7853,7 +7866,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - false + true @@ -7861,11 +7874,11 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re c_s_axis_s2mm_tdata_width Stream Data Width - 32 + 8 - false + true @@ -7877,7 +7890,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - false + true @@ -7921,7 +7934,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re c_num_fstores Frame Buffers - 1 + 3 @@ -7961,7 +7974,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - false + true @@ -8029,11 +8042,11 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re c_s2mm_genlock_mode GenLock Mode - 0 + 2 - false + true @@ -8045,7 +8058,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - false + true @@ -8053,7 +8066,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re c_mm2s_linebuffer_depth Line Buffer Depth - 4096 + 2048 @@ -8077,11 +8090,11 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re c_s2mm_linebuffer_depth Line Buffer Depth - 512 + 2048 - false + true @@ -8113,7 +8126,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re c_mm2s_max_burst_length Read Burst Size - 16 + 32 @@ -8173,11 +8186,11 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re c_s2mm_max_burst_length Write Burst Size - 8 + 32 - false + true @@ -8185,7 +8198,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re c_include_s2mm Enable Channel - 0 + 1 @@ -8500,7 +8513,7 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re - + @@ -8511,7 +8524,9 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re + + @@ -8527,9 +8542,19 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re + + + + + + + + + + @@ -8558,12 +8583,17 @@ Note: Frame Delay must be less than or equal to Frame Buffers or an undefined re + + + + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_clocks.xdc b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_clocks.xdc index 96e86e1..ed9cbe8 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_clocks.xdc +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_clocks.xdc @@ -51,3 +51,5 @@ + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_ooc.xdc b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_ooc.xdc index 2caf2b7..f6f65b3 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_ooc.xdc +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_ooc.xdc @@ -55,3 +55,7 @@ ## set_property HD.CLK_SRC BUFGCTRL_X0Y1 [get_ports m_axi_mm2s_aclk] create_clock -name m_axis_mm2s_aclk -period 20 [get_ports m_axis_mm2s_aclk] ## set_property HD.CLK_SRC BUFGCTRL_X0Y4 [get_ports m_axis_mm2s_aclk] + create_clock -name m_axi_s2mm_aclk -period 10 [get_ports m_axi_s2mm_aclk] +## set_property HD.CLK_SRC BUFGCTRL_X0Y2 [get_ports m_axi_s2mm_aclk] + create_clock -name s_axis_s2mm_aclk -period 20 [get_ports s_axis_s2mm_aclk] +## set_property HD.CLK_SRC BUFGCTRL_X0Y5 [get_ports s_axis_s2mm_aclk] diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_sim_netlist.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_sim_netlist.v index c900eb1..652fa29 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_sim_netlist.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -// Date : Fri Feb 24 16:08:16 2017 +// Date : Mon Mar 06 11:51:46 2017 // Host : WK73 running 64-bit Service Pack 1 (build 7601) // Command : write_verilog -force -mode funcsim -// c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_sim_netlist.v +// C:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_sim_netlist.v // Design : Arty_Z7_20_axi_vdma_0_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -18,6 +18,8 @@ module Arty_Z7_20_axi_vdma_0_0 (s_axi_lite_aclk, m_axi_mm2s_aclk, m_axis_mm2s_aclk, + m_axi_s2mm_aclk, + s_axis_s2mm_aclk, axi_resetn, s_axi_lite_awvalid, s_axi_lite_awready, @@ -36,6 +38,8 @@ module Arty_Z7_20_axi_vdma_0_0 s_axi_lite_rdata, s_axi_lite_rresp, mm2s_frame_ptr_out, + s2mm_frame_ptr_in, + s2mm_frame_ptr_out, m_axi_mm2s_araddr, m_axi_mm2s_arlen, m_axi_mm2s_arsize, @@ -55,10 +59,35 @@ module Arty_Z7_20_axi_vdma_0_0 m_axis_mm2s_tvalid, m_axis_mm2s_tready, m_axis_mm2s_tlast, - mm2s_introut); + m_axi_s2mm_awaddr, + m_axi_s2mm_awlen, + m_axi_s2mm_awsize, + m_axi_s2mm_awburst, + m_axi_s2mm_awprot, + m_axi_s2mm_awcache, + m_axi_s2mm_awvalid, + m_axi_s2mm_awready, + m_axi_s2mm_wdata, + m_axi_s2mm_wstrb, + m_axi_s2mm_wlast, + m_axi_s2mm_wvalid, + m_axi_s2mm_wready, + m_axi_s2mm_bresp, + m_axi_s2mm_bvalid, + m_axi_s2mm_bready, + s_axis_s2mm_tdata, + s_axis_s2mm_tkeep, + s_axis_s2mm_tuser, + s_axis_s2mm_tvalid, + s_axis_s2mm_tready, + s_axis_s2mm_tlast, + mm2s_introut, + s2mm_introut); (* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK" *) input s_axi_lite_aclk; (* x_interface_info = "xilinx.com:signal:clock:1.0 M_AXI_MM2S_ACLK CLK" *) input m_axi_mm2s_aclk; (* x_interface_info = "xilinx.com:signal:clock:1.0 M_AXIS_MM2S_ACLK CLK" *) input m_axis_mm2s_aclk; + (* x_interface_info = "xilinx.com:signal:clock:1.0 M_AXI_S2MM_ACLK CLK" *) input m_axi_s2mm_aclk; + (* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXIS_S2MM_ACLK CLK" *) input s_axis_s2mm_aclk; (* x_interface_info = "xilinx.com:signal:reset:1.0 AXI_RESETN RST" *) input axi_resetn; (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID" *) input s_axi_lite_awvalid; (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY" *) output s_axi_lite_awready; @@ -77,6 +106,8 @@ module Arty_Z7_20_axi_vdma_0_0 (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA" *) output [31:0]s_axi_lite_rdata; (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP" *) output [1:0]s_axi_lite_rresp; (* x_interface_info = "xilinx.com:signal:video_frame_ptr:1.0 MM2S_FRAME_PTR_OUT FRAME_PTR" *) output [5:0]mm2s_frame_ptr_out; + (* x_interface_info = "xilinx.com:signal:video_frame_ptr:1.0 S2MM_FRAME_PTR_IN_0 FRAME_PTR" *) input [5:0]s2mm_frame_ptr_in; + (* x_interface_info = "xilinx.com:signal:video_frame_ptr:1.0 S2MM_FRAME_PTR_OUT FRAME_PTR" *) output [5:0]s2mm_frame_ptr_out; (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR" *) output [31:0]m_axi_mm2s_araddr; (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN" *) output [7:0]m_axi_mm2s_arlen; (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE" *) output [2:0]m_axi_mm2s_arsize; @@ -96,7 +127,30 @@ module Arty_Z7_20_axi_vdma_0_0 (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID" *) output m_axis_mm2s_tvalid; (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY" *) input m_axis_mm2s_tready; (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST" *) output m_axis_mm2s_tlast; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR" *) output [31:0]m_axi_s2mm_awaddr; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN" *) output [7:0]m_axi_s2mm_awlen; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE" *) output [2:0]m_axi_s2mm_awsize; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST" *) output [1:0]m_axi_s2mm_awburst; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT" *) output [2:0]m_axi_s2mm_awprot; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE" *) output [3:0]m_axi_s2mm_awcache; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID" *) output m_axi_s2mm_awvalid; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY" *) input m_axi_s2mm_awready; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA" *) output [63:0]m_axi_s2mm_wdata; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB" *) output [7:0]m_axi_s2mm_wstrb; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST" *) output m_axi_s2mm_wlast; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID" *) output m_axi_s2mm_wvalid; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY" *) input m_axi_s2mm_wready; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP" *) input [1:0]m_axi_s2mm_bresp; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID" *) input m_axi_s2mm_bvalid; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY" *) output m_axi_s2mm_bready; + (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA" *) input [7:0]s_axis_s2mm_tdata; + (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP" *) input [0:0]s_axis_s2mm_tkeep; + (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TUSER" *) input [0:0]s_axis_s2mm_tuser; + (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID" *) input s_axis_s2mm_tvalid; + (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY" *) output s_axis_s2mm_tready; + (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST" *) input s_axis_s2mm_tlast; (* x_interface_info = "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT" *) output mm2s_introut; + (* x_interface_info = "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT" *) output s2mm_introut; wire axi_resetn; wire m_axi_mm2s_aclk; @@ -113,6 +167,23 @@ module Arty_Z7_20_axi_vdma_0_0 wire m_axi_mm2s_rready; wire [1:0]m_axi_mm2s_rresp; wire m_axi_mm2s_rvalid; + wire m_axi_s2mm_aclk; + wire [31:0]m_axi_s2mm_awaddr; + wire [1:0]m_axi_s2mm_awburst; + wire [3:0]m_axi_s2mm_awcache; + wire [7:0]m_axi_s2mm_awlen; + wire [2:0]m_axi_s2mm_awprot; + wire m_axi_s2mm_awready; + wire [2:0]m_axi_s2mm_awsize; + wire m_axi_s2mm_awvalid; + wire m_axi_s2mm_bready; + wire [1:0]m_axi_s2mm_bresp; + wire m_axi_s2mm_bvalid; + wire [63:0]m_axi_s2mm_wdata; + wire m_axi_s2mm_wlast; + wire m_axi_s2mm_wready; + wire [7:0]m_axi_s2mm_wstrb; + wire m_axi_s2mm_wvalid; wire m_axis_mm2s_aclk; wire [31:0]m_axis_mm2s_tdata; wire [3:0]m_axis_mm2s_tkeep; @@ -122,6 +193,9 @@ module Arty_Z7_20_axi_vdma_0_0 wire m_axis_mm2s_tvalid; wire [5:0]mm2s_frame_ptr_out; wire mm2s_introut; + wire [5:0]s2mm_frame_ptr_in; + wire [5:0]s2mm_frame_ptr_out; + wire s2mm_introut; wire s_axi_lite_aclk; wire [8:0]s_axi_lite_araddr; wire s_axi_lite_arready; @@ -139,10 +213,13 @@ module Arty_Z7_20_axi_vdma_0_0 wire [31:0]s_axi_lite_wdata; wire s_axi_lite_wready; wire s_axi_lite_wvalid; - wire NLW_U0_m_axi_s2mm_awvalid_UNCONNECTED; - wire NLW_U0_m_axi_s2mm_bready_UNCONNECTED; - wire NLW_U0_m_axi_s2mm_wlast_UNCONNECTED; - wire NLW_U0_m_axi_s2mm_wvalid_UNCONNECTED; + wire s_axis_s2mm_aclk; + wire [7:0]s_axis_s2mm_tdata; + wire [0:0]s_axis_s2mm_tkeep; + wire s_axis_s2mm_tlast; + wire s_axis_s2mm_tready; + wire [0:0]s_axis_s2mm_tuser; + wire s_axis_s2mm_tvalid; wire NLW_U0_m_axi_sg_arvalid_UNCONNECTED; wire NLW_U0_m_axi_sg_rready_UNCONNECTED; wire NLW_U0_mm2s_buffer_almost_empty_UNCONNECTED; @@ -153,26 +230,15 @@ module Arty_Z7_20_axi_vdma_0_0 wire NLW_U0_s2mm_buffer_almost_full_UNCONNECTED; wire NLW_U0_s2mm_buffer_full_UNCONNECTED; wire NLW_U0_s2mm_fsync_out_UNCONNECTED; - wire NLW_U0_s2mm_introut_UNCONNECTED; wire NLW_U0_s2mm_prmry_reset_out_n_UNCONNECTED; wire NLW_U0_s2mm_prmtr_update_UNCONNECTED; - wire NLW_U0_s_axis_s2mm_tready_UNCONNECTED; wire [63:0]NLW_U0_axi_vdma_tstvec_UNCONNECTED; - wire [31:0]NLW_U0_m_axi_s2mm_awaddr_UNCONNECTED; - wire [1:0]NLW_U0_m_axi_s2mm_awburst_UNCONNECTED; - wire [3:0]NLW_U0_m_axi_s2mm_awcache_UNCONNECTED; - wire [7:0]NLW_U0_m_axi_s2mm_awlen_UNCONNECTED; - wire [2:0]NLW_U0_m_axi_s2mm_awprot_UNCONNECTED; - wire [2:0]NLW_U0_m_axi_s2mm_awsize_UNCONNECTED; - wire [63:0]NLW_U0_m_axi_s2mm_wdata_UNCONNECTED; - wire [7:0]NLW_U0_m_axi_s2mm_wstrb_UNCONNECTED; wire [31:0]NLW_U0_m_axi_sg_araddr_UNCONNECTED; wire [1:0]NLW_U0_m_axi_sg_arburst_UNCONNECTED; wire [3:0]NLW_U0_m_axi_sg_arcache_UNCONNECTED; wire [7:0]NLW_U0_m_axi_sg_arlen_UNCONNECTED; wire [2:0]NLW_U0_m_axi_sg_arprot_UNCONNECTED; wire [2:0]NLW_U0_m_axi_sg_arsize_UNCONNECTED; - wire [5:0]NLW_U0_s2mm_frame_ptr_out_UNCONNECTED; (* C_DLYTMR_RESOLUTION = "125" *) (* C_DYNAMIC_RESOLUTION = "1" *) @@ -200,7 +266,7 @@ module Arty_Z7_20_axi_vdma_0_0 (* C_INCLUDE_MM2S = "1" *) (* C_INCLUDE_MM2S_DRE = "0" *) (* C_INCLUDE_MM2S_SF = "0" *) - (* C_INCLUDE_S2MM = "0" *) + (* C_INCLUDE_S2MM = "1" *) (* C_INCLUDE_S2MM_DRE = "0" *) (* C_INCLUDE_S2MM_SF = "1" *) (* C_INCLUDE_SG = "0" *) @@ -208,9 +274,9 @@ module Arty_Z7_20_axi_vdma_0_0 (* C_MM2S_GENLOCK_MODE = "0" *) (* C_MM2S_GENLOCK_NUM_MASTERS = "1" *) (* C_MM2S_GENLOCK_REPEAT_EN = "0" *) - (* C_MM2S_LINEBUFFER_DEPTH = "4096" *) + (* C_MM2S_LINEBUFFER_DEPTH = "2048" *) (* C_MM2S_LINEBUFFER_THRESH = "4" *) - (* C_MM2S_MAX_BURST_LENGTH = "16" *) + (* C_MM2S_MAX_BURST_LENGTH = "32" *) (* C_MM2S_SOF_ENABLE = "1" *) (* C_M_AXIS_MM2S_TDATA_WIDTH = "32" *) (* C_M_AXIS_MM2S_TUSER_BITS = "1" *) @@ -220,17 +286,17 @@ module Arty_Z7_20_axi_vdma_0_0 (* C_M_AXI_S2MM_DATA_WIDTH = "64" *) (* C_M_AXI_SG_ADDR_WIDTH = "32" *) (* C_M_AXI_SG_DATA_WIDTH = "32" *) - (* C_NUM_FSTORES = "1" *) + (* C_NUM_FSTORES = "3" *) (* C_PRMRY_IS_ACLK_ASYNC = "1" *) - (* C_S2MM_GENLOCK_MODE = "0" *) + (* C_S2MM_GENLOCK_MODE = "2" *) (* C_S2MM_GENLOCK_NUM_MASTERS = "1" *) (* C_S2MM_GENLOCK_REPEAT_EN = "1" *) - (* C_S2MM_LINEBUFFER_DEPTH = "512" *) + (* C_S2MM_LINEBUFFER_DEPTH = "2048" *) (* C_S2MM_LINEBUFFER_THRESH = "4" *) - (* C_S2MM_MAX_BURST_LENGTH = "8" *) + (* C_S2MM_MAX_BURST_LENGTH = "32" *) (* C_S2MM_SOF_ENABLE = "1" *) (* C_SELECT_XPM = "0" *) - (* C_S_AXIS_S2MM_TDATA_WIDTH = "32" *) + (* C_S_AXIS_S2MM_TDATA_WIDTH = "8" *) (* C_S_AXIS_S2MM_TUSER_BITS = "1" *) (* C_S_AXI_LITE_ADDR_WIDTH = "9" *) (* C_S_AXI_LITE_DATA_WIDTH = "32" *) @@ -258,23 +324,23 @@ module Arty_Z7_20_axi_vdma_0_0 .m_axi_mm2s_rready(m_axi_mm2s_rready), .m_axi_mm2s_rresp(m_axi_mm2s_rresp), .m_axi_mm2s_rvalid(m_axi_mm2s_rvalid), - .m_axi_s2mm_aclk(1'b0), - .m_axi_s2mm_awaddr(NLW_U0_m_axi_s2mm_awaddr_UNCONNECTED[31:0]), - .m_axi_s2mm_awburst(NLW_U0_m_axi_s2mm_awburst_UNCONNECTED[1:0]), - .m_axi_s2mm_awcache(NLW_U0_m_axi_s2mm_awcache_UNCONNECTED[3:0]), - .m_axi_s2mm_awlen(NLW_U0_m_axi_s2mm_awlen_UNCONNECTED[7:0]), - .m_axi_s2mm_awprot(NLW_U0_m_axi_s2mm_awprot_UNCONNECTED[2:0]), - .m_axi_s2mm_awready(1'b0), - .m_axi_s2mm_awsize(NLW_U0_m_axi_s2mm_awsize_UNCONNECTED[2:0]), - .m_axi_s2mm_awvalid(NLW_U0_m_axi_s2mm_awvalid_UNCONNECTED), - .m_axi_s2mm_bready(NLW_U0_m_axi_s2mm_bready_UNCONNECTED), - .m_axi_s2mm_bresp({1'b0,1'b0}), - .m_axi_s2mm_bvalid(1'b0), - .m_axi_s2mm_wdata(NLW_U0_m_axi_s2mm_wdata_UNCONNECTED[63:0]), - .m_axi_s2mm_wlast(NLW_U0_m_axi_s2mm_wlast_UNCONNECTED), - .m_axi_s2mm_wready(1'b0), - .m_axi_s2mm_wstrb(NLW_U0_m_axi_s2mm_wstrb_UNCONNECTED[7:0]), - .m_axi_s2mm_wvalid(NLW_U0_m_axi_s2mm_wvalid_UNCONNECTED), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .m_axi_s2mm_awaddr(m_axi_s2mm_awaddr), + .m_axi_s2mm_awburst(m_axi_s2mm_awburst), + .m_axi_s2mm_awcache(m_axi_s2mm_awcache), + .m_axi_s2mm_awlen(m_axi_s2mm_awlen), + .m_axi_s2mm_awprot(m_axi_s2mm_awprot), + .m_axi_s2mm_awready(m_axi_s2mm_awready), + .m_axi_s2mm_awsize(m_axi_s2mm_awsize), + .m_axi_s2mm_awvalid(m_axi_s2mm_awvalid), + .m_axi_s2mm_bready(m_axi_s2mm_bready), + .m_axi_s2mm_bresp(m_axi_s2mm_bresp), + .m_axi_s2mm_bvalid(m_axi_s2mm_bvalid), + .m_axi_s2mm_wdata(m_axi_s2mm_wdata), + .m_axi_s2mm_wlast(m_axi_s2mm_wlast), + .m_axi_s2mm_wready(m_axi_s2mm_wready), + .m_axi_s2mm_wstrb(m_axi_s2mm_wstrb), + .m_axi_s2mm_wvalid(m_axi_s2mm_wvalid), .m_axi_sg_aclk(1'b0), .m_axi_sg_araddr(NLW_U0_m_axi_sg_araddr_UNCONNECTED[31:0]), .m_axi_sg_arburst(NLW_U0_m_axi_sg_arburst_UNCONNECTED[1:0]), @@ -307,11 +373,11 @@ module Arty_Z7_20_axi_vdma_0_0 .mm2s_prmtr_update(NLW_U0_mm2s_prmtr_update_UNCONNECTED), .s2mm_buffer_almost_full(NLW_U0_s2mm_buffer_almost_full_UNCONNECTED), .s2mm_buffer_full(NLW_U0_s2mm_buffer_full_UNCONNECTED), - .s2mm_frame_ptr_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s2mm_frame_ptr_out(NLW_U0_s2mm_frame_ptr_out_UNCONNECTED[5:0]), + .s2mm_frame_ptr_in(s2mm_frame_ptr_in), + .s2mm_frame_ptr_out(s2mm_frame_ptr_out), .s2mm_fsync(1'b0), .s2mm_fsync_out(NLW_U0_s2mm_fsync_out_UNCONNECTED), - .s2mm_introut(NLW_U0_s2mm_introut_UNCONNECTED), + .s2mm_introut(s2mm_introut), .s2mm_prmry_reset_out_n(NLW_U0_s2mm_prmry_reset_out_n_UNCONNECTED), .s2mm_prmtr_update(NLW_U0_s2mm_prmtr_update_UNCONNECTED), .s_axi_lite_aclk(s_axi_lite_aclk), @@ -331,108 +397,223 @@ module Arty_Z7_20_axi_vdma_0_0 .s_axi_lite_wdata(s_axi_lite_wdata), .s_axi_lite_wready(s_axi_lite_wready), .s_axi_lite_wvalid(s_axi_lite_wvalid), - .s_axis_s2mm_aclk(1'b0), - .s_axis_s2mm_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .s_axis_s2mm_tkeep({1'b1,1'b1,1'b1,1'b1}), - .s_axis_s2mm_tlast(1'b0), - .s_axis_s2mm_tready(NLW_U0_s_axis_s2mm_tready_UNCONNECTED), - .s_axis_s2mm_tuser(1'b0), - .s_axis_s2mm_tvalid(1'b0)); + .s_axis_s2mm_aclk(s_axis_s2mm_aclk), + .s_axis_s2mm_tdata(s_axis_s2mm_tdata), + .s_axis_s2mm_tkeep(s_axis_s2mm_tkeep), + .s_axis_s2mm_tlast(s_axis_s2mm_tlast), + .s_axis_s2mm_tready(s_axis_s2mm_tready), + .s_axis_s2mm_tuser(s_axis_s2mm_tuser), + .s_axis_s2mm_tvalid(s_axis_s2mm_tvalid)); endmodule (* ORIG_REF_NAME = "axi_datamover" *) module Arty_Z7_20_axi_vdma_0_0_axi_datamover - (m_axi_mm2s_arburst, + (sig_rst2all_stop_request, + m_axi_mm2s_arburst, m_axi_mm2s_arvalid, - mm2s_halt_cmplt, - sig_rst2all_stop_request, - \sig_user_skid_reg_reg[0] , - dm2linebuf_mm2s_tvalid, + lsig_0ffset_cntr, + m_axi_s2mm_awburst, + m_axi_s2mm_awvalid, + m_axi_s2mm_wvalid, + \sig_data_skid_reg_reg[7] , + DI, + sig_rst2all_stop_request_0, + m_axi_s2mm_wlast, + RD_EN, E, + datamover_idle_reg, + mm2s_halt_cmplt, + p_9_out, Q, - m_axi_mm2s_rready, - dm2linebuf_mm2s_tdata, - interr_i_reg, - slverr_i_reg, + \GEN_STS_GRTR_THAN_8.ovrflo_err_reg , + s_axis_cmd_tvalid_reg, + CO, + datamover_idle_reg_0, + s2mm_halt_cmplt, decerr_i_reg, + FIFO_Full_reg, + slverr_i_reg, + interr_i_reg, + decerr_i_reg_0, + slverr_i_reg_0, + interr_i_reg_0, + \gcc0.gc0.count_d1_reg[0] , m_axi_mm2s_araddr, m_axi_mm2s_arlen, m_axi_mm2s_arsize, + m_axi_s2mm_awaddr, + m_axi_s2mm_awlen, + m_axi_s2mm_awsize, + m_axi_s2mm_wdata, + \gpr1.dout_i_reg[1] , + \gpr1.dout_i_reg[1]_0 , + m_axi_mm2s_rready, + DIN, + \sig_user_skid_reg_reg[0] , + dm2linebuf_mm2s_tdata, + m_axi_s2mm_bready, m_axi_mm2s_aclk, m_axi_mm2s_rdata, out, halt_i_reg, - p_55_out, - m_axi_mm2s_rlast, - m_axi_mm2s_rvalid, - m_axi_mm2s_rresp, + m_axi_s2mm_aclk, + s_soft_reset_i_reg, + halt_i_reg_0, + prmry_resetn_i_reg, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , + DOUT, + EMPTY, cmnd_wr, mm2s_halt, - p_57_out, - sts_tready_reg, - p_8_out, - fifo_wren__0, + p_71_out, + datamover_idle, + s2mm_halt, + s2mm_soft_reset, + dma_err, + cmnd_wr_1, + \hsize_vid_reg[15] , + \hsize_vid_reg[2] , + S, + s2mm_dmacr, + datamover_idle_2, + m_axi_mm2s_rlast, m_axi_mm2s_arready, - in); + m_axi_s2mm_awready, + m_axi_s2mm_wready, + in, + \s_axis_cmd_tdata_reg[63] , + m_axi_s2mm_bresp, + p_0_out, + p_56_out, + p_58_out, + sts_tready_reg, + m_axi_mm2s_rvalid, + m_axi_mm2s_rresp, + s_axis_s2mm_cmd_tvalid, + m_axi_s2mm_bvalid, + m_axis_s2mm_sts_tready); + output sig_rst2all_stop_request; output [0:0]m_axi_mm2s_arburst; output m_axi_mm2s_arvalid; - output mm2s_halt_cmplt; - output sig_rst2all_stop_request; - output [0:0]\sig_user_skid_reg_reg[0] ; - output dm2linebuf_mm2s_tvalid; + output lsig_0ffset_cntr; + output [0:0]m_axi_s2mm_awburst; + output m_axi_s2mm_awvalid; + output m_axi_s2mm_wvalid; + output \sig_data_skid_reg_reg[7] ; + output [10:0]DI; + output sig_rst2all_stop_request_0; + output m_axi_s2mm_wlast; + output RD_EN; output [0:0]E; + output datamover_idle_reg; + output mm2s_halt_cmplt; + output p_9_out; output [0:0]Q; - output m_axi_mm2s_rready; - output [31:0]dm2linebuf_mm2s_tdata; - output interr_i_reg; - output slverr_i_reg; + output [0:0]\GEN_STS_GRTR_THAN_8.ovrflo_err_reg ; + output [0:0]s_axis_cmd_tvalid_reg; + output [0:0]CO; + output datamover_idle_reg_0; + output s2mm_halt_cmplt; output decerr_i_reg; + output [0:0]FIFO_Full_reg; + output slverr_i_reg; + output interr_i_reg; + output decerr_i_reg_0; + output slverr_i_reg_0; + output interr_i_reg_0; + output [0:0]\gcc0.gc0.count_d1_reg[0] ; output [31:0]m_axi_mm2s_araddr; - output [3:0]m_axi_mm2s_arlen; + output [4:0]m_axi_mm2s_arlen; output [1:0]m_axi_mm2s_arsize; + output [31:0]m_axi_s2mm_awaddr; + output [5:0]m_axi_s2mm_awlen; + output [1:0]m_axi_s2mm_awsize; + output [63:0]m_axi_s2mm_wdata; + output [2:0]\gpr1.dout_i_reg[1] ; + output [2:0]\gpr1.dout_i_reg[1]_0 ; + output m_axi_mm2s_rready; + output [0:0]DIN; + output \sig_user_skid_reg_reg[0] ; + output [31:0]dm2linebuf_mm2s_tdata; + output m_axi_s2mm_bready; input m_axi_mm2s_aclk; input [63:0]m_axi_mm2s_rdata; input out; input halt_i_reg; - input p_55_out; - input m_axi_mm2s_rlast; - input m_axi_mm2s_rvalid; - input [1:0]m_axi_mm2s_rresp; + input m_axi_s2mm_aclk; + input s_soft_reset_i_reg; + input halt_i_reg_0; + input prmry_resetn_i_reg; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + input [8:0]DOUT; + input EMPTY; input cmnd_wr; input mm2s_halt; - input p_57_out; - input sts_tready_reg; - input p_8_out; - input fifo_wren__0; + input [0:0]p_71_out; + input datamover_idle; + input s2mm_halt; + input s2mm_soft_reset; + input dma_err; + input cmnd_wr_1; + input [12:0]\hsize_vid_reg[15] ; + input [0:0]\hsize_vid_reg[2] ; + input [0:0]S; + input [0:0]s2mm_dmacr; + input datamover_idle_2; + input m_axi_mm2s_rlast; input m_axi_mm2s_arready; + input m_axi_s2mm_awready; + input m_axi_s2mm_wready; input [48:0]in; + input [48:0]\s_axis_cmd_tdata_reg[63] ; + input [1:0]m_axi_s2mm_bresp; + input [10:0]p_0_out; + input p_56_out; + input p_58_out; + input sts_tready_reg; + input m_axi_mm2s_rvalid; + input [1:0]m_axi_mm2s_rresp; + input s_axis_s2mm_cmd_tvalid; + input m_axi_s2mm_bvalid; + input m_axis_s2mm_sts_tready; + wire [0:0]CO; + wire [10:0]DI; + wire [0:0]DIN; + wire [8:0]DOUT; wire [0:0]E; - wire [4:4]\GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/gsym_dc.dc/count_reg ; - wire \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_11 ; - wire \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_47 ; - wire \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_48 ; - wire \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_49 ; - wire \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_50 ; - wire \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_54 ; - wire \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_55 ; - wire \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_6 ; - wire \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_7 ; - wire \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_8 ; - wire \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_9 ; + wire EMPTY; + wire [0:0]FIFO_Full_reg; + wire [0:0]\GEN_STS_GRTR_THAN_8.ovrflo_err_reg ; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; wire [0:0]Q; + wire RD_EN; + wire [0:0]S; wire cmnd_wr; + wire cmnd_wr_1; + wire datamover_idle; + wire datamover_idle_2; + wire datamover_idle_reg; + wire datamover_idle_reg_0; wire decerr_i_reg; + wire decerr_i_reg_0; wire [31:0]dm2linebuf_mm2s_tdata; - wire dm2linebuf_mm2s_tvalid; - wire fifo_wren__0; + wire dma_err; + wire [0:0]\gcc0.gc0.count_d1_reg[0] ; + wire [2:0]\gpr1.dout_i_reg[1] ; + wire [2:0]\gpr1.dout_i_reg[1]_0 ; wire halt_i_reg; + wire halt_i_reg_0; + wire [12:0]\hsize_vid_reg[15] ; + wire [0:0]\hsize_vid_reg[2] ; wire [48:0]in; wire interr_i_reg; + wire interr_i_reg_0; + wire lsig_0ffset_cntr; wire m_axi_mm2s_aclk; wire [31:0]m_axi_mm2s_araddr; wire [0:0]m_axi_mm2s_arburst; - wire [3:0]m_axi_mm2s_arlen; + wire [4:0]m_axi_mm2s_arlen; wire m_axi_mm2s_arready; wire [1:0]m_axi_mm2s_arsize; wire m_axi_mm2s_arvalid; @@ -441,43 +622,57 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover wire m_axi_mm2s_rready; wire [1:0]m_axi_mm2s_rresp; wire m_axi_mm2s_rvalid; + wire m_axi_s2mm_aclk; + wire [31:0]m_axi_s2mm_awaddr; + wire [0:0]m_axi_s2mm_awburst; + wire [5:0]m_axi_s2mm_awlen; + wire m_axi_s2mm_awready; + wire [1:0]m_axi_s2mm_awsize; + wire m_axi_s2mm_awvalid; + wire m_axi_s2mm_bready; + wire [1:0]m_axi_s2mm_bresp; + wire m_axi_s2mm_bvalid; + wire [63:0]m_axi_s2mm_wdata; + wire m_axi_s2mm_wlast; + wire m_axi_s2mm_wready; + wire m_axi_s2mm_wvalid; + wire m_axis_s2mm_sts_tready; wire mm2s_halt; wire mm2s_halt_cmplt; wire out; - wire p_0_out_carry__0_n_3; - wire p_0_out_carry__0_n_6; - wire p_0_out_carry__0_n_7; - wire p_0_out_carry_n_0; - wire p_0_out_carry_n_1; - wire p_0_out_carry_n_2; - wire p_0_out_carry_n_3; - wire p_0_out_carry_n_4; - wire p_0_out_carry_n_5; - wire p_0_out_carry_n_6; - wire p_0_out_carry_n_7; - wire p_55_out; - wire p_57_out; - wire p_8_out; + wire [10:0]p_0_out; + wire p_56_out; + wire p_58_out; + wire [0:0]p_71_out; + wire p_9_out; + wire prmry_resetn_i_reg; + wire [0:0]s2mm_dmacr; + wire s2mm_halt; + wire s2mm_halt_cmplt; + wire s2mm_soft_reset; + wire [48:0]\s_axis_cmd_tdata_reg[63] ; + wire [0:0]s_axis_cmd_tvalid_reg; + wire s_axis_s2mm_cmd_tvalid; + wire s_soft_reset_i_reg; + wire \sig_data_skid_reg_reg[7] ; wire sig_rst2all_stop_request; - wire [0:0]\sig_user_skid_reg_reg[0] ; + wire sig_rst2all_stop_request_0; + wire \sig_user_skid_reg_reg[0] ; wire slverr_i_reg; + wire slverr_i_reg_0; wire sts_tready_reg; - wire [3:1]NLW_p_0_out_carry__0_CO_UNCONNECTED; - wire [3:2]NLW_p_0_out_carry__0_O_UNCONNECTED; Arty_Z7_20_axi_vdma_0_0_axi_datamover_mm2s_full_wrap \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER - (.D({p_0_out_carry__0_n_6,p_0_out_carry__0_n_7,p_0_out_carry_n_4,p_0_out_carry_n_5,p_0_out_carry_n_6,p_0_out_carry_n_7}), - .DI({\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_6 ,\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_7 ,\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_8 ,\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_9 }), + (.DIN(DIN), .E(E), - .FIFO_Full_reg(Q), - .Q({\GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/gsym_dc.dc/count_reg ,\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_11 }), - .S({\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_47 ,\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_48 ,\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_49 ,\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_50 }), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] (lsig_0ffset_cntr), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), + .Q(FIFO_Full_reg), .cmnd_wr(cmnd_wr), - .\count_reg[6] ({\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_54 ,\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_55 }), + .datamover_idle(datamover_idle), + .datamover_idle_reg(datamover_idle_reg), .decerr_i_reg(decerr_i_reg), .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), - .dm2linebuf_mm2s_tvalid(dm2linebuf_mm2s_tvalid), - .fifo_wren__0(fifo_wren__0), .halt_i_reg(halt_i_reg), .in(in), .interr_i_reg(interr_i_reg), @@ -496,29 +691,63 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover .mm2s_halt(mm2s_halt), .mm2s_halt_cmplt(mm2s_halt_cmplt), .out(out), - .p_55_out(p_55_out), - .p_57_out(p_57_out), - .p_8_out(p_8_out), + .p_56_out(p_56_out), + .p_58_out(p_58_out), + .p_71_out(p_71_out), + .prmry_resetn_i_reg(prmry_resetn_i_reg), .sig_rst2all_stop_request(sig_rst2all_stop_request), .\sig_user_skid_reg_reg[0] (\sig_user_skid_reg_reg[0] ), .slverr_i_reg(slverr_i_reg), .sts_tready_reg(sts_tready_reg)); - (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) - CARRY4 p_0_out_carry - (.CI(1'b0), - .CO({p_0_out_carry_n_0,p_0_out_carry_n_1,p_0_out_carry_n_2,p_0_out_carry_n_3}), - .CYINIT(\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_11 ), - .DI({\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_6 ,\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_7 ,\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_8 ,\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_9 }), - .O({p_0_out_carry_n_4,p_0_out_carry_n_5,p_0_out_carry_n_6,p_0_out_carry_n_7}), - .S({\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_47 ,\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_48 ,\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_49 ,\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_50 })); - (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) - CARRY4 p_0_out_carry__0 - (.CI(p_0_out_carry_n_0), - .CO({NLW_p_0_out_carry__0_CO_UNCONNECTED[3:1],p_0_out_carry__0_n_3}), - .CYINIT(1'b0), - .DI({1'b0,1'b0,1'b0,\GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/gsym_dc.dc/count_reg }), - .O({NLW_p_0_out_carry__0_O_UNCONNECTED[3:2],p_0_out_carry__0_n_6,p_0_out_carry__0_n_7}), - .S({1'b0,1'b0,\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_54 ,\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_55 })); + Arty_Z7_20_axi_vdma_0_0_axi_datamover_s2mm_full_wrap \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER + (.CO(CO), + .DI(DI), + .DOUT(DOUT), + .E(\gcc0.gc0.count_d1_reg[0] ), + .EMPTY(EMPTY), + .\GEN_STS_GRTR_THAN_8.ovrflo_err_reg (\GEN_STS_GRTR_THAN_8.ovrflo_err_reg ), + .Q(Q), + .RD_EN(RD_EN), + .S(S), + .cmnd_wr_1(cmnd_wr_1), + .datamover_idle_2(datamover_idle_2), + .datamover_idle_reg(datamover_idle_reg_0), + .decerr_i_reg(decerr_i_reg_0), + .dma_err(dma_err), + .\gpr1.dout_i_reg[1] (\gpr1.dout_i_reg[1] ), + .\gpr1.dout_i_reg[1]_0 (\gpr1.dout_i_reg[1]_0 ), + .halt_i_reg(halt_i_reg_0), + .\hsize_vid_reg[15] (\hsize_vid_reg[15] ), + .\hsize_vid_reg[2] (\hsize_vid_reg[2] ), + .interr_i_reg(interr_i_reg_0), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .m_axi_s2mm_awaddr(m_axi_s2mm_awaddr), + .m_axi_s2mm_awburst(m_axi_s2mm_awburst), + .m_axi_s2mm_awlen(m_axi_s2mm_awlen), + .m_axi_s2mm_awready(m_axi_s2mm_awready), + .m_axi_s2mm_awsize(m_axi_s2mm_awsize), + .m_axi_s2mm_awvalid(m_axi_s2mm_awvalid), + .m_axi_s2mm_bready(m_axi_s2mm_bready), + .m_axi_s2mm_bresp(m_axi_s2mm_bresp), + .m_axi_s2mm_bvalid(m_axi_s2mm_bvalid), + .m_axi_s2mm_wdata(m_axi_s2mm_wdata), + .m_axi_s2mm_wlast(m_axi_s2mm_wlast), + .m_axi_s2mm_wready(m_axi_s2mm_wready), + .m_axi_s2mm_wvalid(m_axi_s2mm_wvalid), + .m_axis_s2mm_sts_tready(m_axis_s2mm_sts_tready), + .p_0_out(p_0_out), + .p_9_out(p_9_out), + .s2mm_dmacr(s2mm_dmacr), + .s2mm_halt(s2mm_halt), + .s2mm_halt_cmplt(s2mm_halt_cmplt), + .s2mm_soft_reset(s2mm_soft_reset), + .\s_axis_cmd_tdata_reg[63] (\s_axis_cmd_tdata_reg[63] ), + .s_axis_cmd_tvalid_reg(s_axis_cmd_tvalid_reg), + .s_axis_s2mm_cmd_tvalid(s_axis_s2mm_cmd_tvalid), + .s_soft_reset_i_reg(s_soft_reset_i_reg), + .\sig_data_skid_reg_reg[7] (\sig_data_skid_reg_reg[7] ), + .sig_rst2all_stop_request_0(sig_rst2all_stop_request_0), + .slverr_i_reg(slverr_i_reg_0)); endmodule (* ORIG_REF_NAME = "axi_datamover_addr_cntl" *) @@ -526,53 +755,52 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl (out, \sig_addr_posted_cntr_reg[2] , sig_init_reg2, - sig_addr_reg_empty, - sig_addr2rsc_calc_error, m_axi_mm2s_arburst, m_axi_mm2s_arvalid, sig_wr_fifo, + sig_halt_cmplt_reg, m_axi_mm2s_araddr, m_axi_mm2s_arlen, m_axi_mm2s_arsize, SR, sig_init_reg, m_axi_mm2s_aclk, - sig_mstr2addr_cmd_valid, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_data2addr_stop_req, sig_sf_allow_addr_req, + sig_data2addr_stop_req, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, m_axi_mm2s_arready, + sig_mstr2addr_cmd_valid, + sig_halt_reg_dly3, in); output out; output \sig_addr_posted_cntr_reg[2] ; output sig_init_reg2; - output sig_addr_reg_empty; - output sig_addr2rsc_calc_error; output [0:0]m_axi_mm2s_arburst; output m_axi_mm2s_arvalid; output sig_wr_fifo; + output sig_halt_cmplt_reg; output [31:0]m_axi_mm2s_araddr; - output [3:0]m_axi_mm2s_arlen; + output [4:0]m_axi_mm2s_arlen; output [1:0]m_axi_mm2s_arsize; input [0:0]SR; input sig_init_reg; input m_axi_mm2s_aclk; - input sig_mstr2addr_cmd_valid; - input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - input sig_data2addr_stop_req; input sig_sf_allow_addr_req; + input sig_data2addr_stop_req; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; input m_axi_mm2s_arready; - input [37:0]in; + input sig_mstr2addr_cmd_valid; + input sig_halt_reg_dly3; + input [38:0]in; wire \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ; - wire \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_3 ; - wire \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_4 ; + wire \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_43 ; wire [0:0]SR; - wire [37:0]in; + wire [38:0]in; wire m_axi_mm2s_aclk; wire [31:0]m_axi_mm2s_araddr; wire [0:0]m_axi_mm2s_arburst; - wire [3:0]m_axi_mm2s_arlen; + wire [4:0]m_axi_mm2s_arlen; wire m_axi_mm2s_arready; wire [1:0]m_axi_mm2s_arsize; wire m_axi_mm2s_arvalid; @@ -582,12 +810,15 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl wire sig_addr_reg_full; wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; wire sig_data2addr_stop_req; + wire sig_halt_cmplt_reg; + wire sig_halt_reg_dly3; wire sig_init_reg; wire sig_init_reg2; wire sig_mstr2addr_cmd_valid; wire \sig_next_addr_reg[31]_i_1_n_0 ; (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_posted_to_axi; (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_posted_to_axi_2; + wire sig_push_addr_reg1_out; wire sig_sf_allow_addr_req; wire sig_wr_fifo; @@ -597,23 +828,23 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl (.SR(SR), .in(in), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .out({p_1_out[50],p_1_out[47],p_1_out[45:44],p_1_out[39:4]}), + .out({p_1_out[50],p_1_out[47],p_1_out[45:44],p_1_out[40:4]}), .sel(sig_wr_fifo), .sig_addr_reg_empty(sig_addr_reg_empty), - .sig_addr_valid_reg_reg(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_4 ), - .sig_calc_error_reg_reg(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .sig_addr_valid_reg_reg(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), .sig_data2addr_stop_req(sig_data2addr_stop_req), .sig_init_reg(sig_init_reg), .sig_init_reg2(sig_init_reg2), .sig_mstr2addr_cmd_valid(sig_mstr2addr_cmd_valid), - .sig_posted_to_axi_reg(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_3 ), + .sig_posted_to_axi_2_reg(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_43 ), + .sig_push_addr_reg1_out(sig_push_addr_reg1_out), .sig_sf_allow_addr_req(sig_sf_allow_addr_req)); FDSE #( .INIT(1'b0)) sig_addr_reg_empty_reg (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(1'b0), .Q(sig_addr_reg_empty), .S(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -621,39 +852,47 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) sig_addr_reg_full_reg (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), - .D(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), + .D(sig_push_addr_reg1_out), .Q(sig_addr_reg_full), .R(\sig_next_addr_reg[31]_i_1_n_0 )); FDRE #( .INIT(1'b0)) sig_addr_valid_reg_reg (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), - .D(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_4 ), + .CE(sig_push_addr_reg1_out), + .D(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), .Q(m_axi_mm2s_arvalid), .R(\sig_next_addr_reg[31]_i_1_n_0 )); FDRE #( .INIT(1'b0)) sig_calc_error_reg_reg (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[50]), .Q(sig_addr2rsc_calc_error), .R(\sig_next_addr_reg[31]_i_1_n_0 )); LUT4 #( - .INIT(16'h08FF)) + .INIT(16'h1FFF)) + sig_halt_cmplt_i_2 + (.I0(sig_addr2rsc_calc_error), + .I1(sig_addr_reg_empty), + .I2(sig_halt_reg_dly3), + .I3(sig_data2addr_stop_req), + .O(sig_halt_cmplt_reg)); + LUT4 #( + .INIT(16'h40FF)) \sig_next_addr_reg[31]_i_1 - (.I0(m_axi_mm2s_arready), + (.I0(sig_addr2rsc_calc_error), .I1(sig_addr_reg_full), - .I2(sig_addr2rsc_calc_error), + .I2(m_axi_mm2s_arready), .I3(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), .O(\sig_next_addr_reg[31]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \sig_next_addr_reg_reg[0] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[4]), .Q(m_axi_mm2s_araddr[0]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -661,7 +900,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[10] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[14]), .Q(m_axi_mm2s_araddr[10]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -669,7 +908,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[11] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[15]), .Q(m_axi_mm2s_araddr[11]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -677,7 +916,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[12] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[16]), .Q(m_axi_mm2s_araddr[12]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -685,7 +924,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[13] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[17]), .Q(m_axi_mm2s_araddr[13]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -693,7 +932,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[14] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[18]), .Q(m_axi_mm2s_araddr[14]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -701,7 +940,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[15] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[19]), .Q(m_axi_mm2s_araddr[15]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -709,7 +948,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[16] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[20]), .Q(m_axi_mm2s_araddr[16]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -717,7 +956,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[17] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[21]), .Q(m_axi_mm2s_araddr[17]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -725,7 +964,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[18] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[22]), .Q(m_axi_mm2s_araddr[18]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -733,7 +972,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[19] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[23]), .Q(m_axi_mm2s_araddr[19]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -741,7 +980,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[1] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[5]), .Q(m_axi_mm2s_araddr[1]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -749,7 +988,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[20] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[24]), .Q(m_axi_mm2s_araddr[20]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -757,7 +996,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[21] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[25]), .Q(m_axi_mm2s_araddr[21]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -765,7 +1004,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[22] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[26]), .Q(m_axi_mm2s_araddr[22]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -773,7 +1012,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[23] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[27]), .Q(m_axi_mm2s_araddr[23]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -781,7 +1020,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[24] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[28]), .Q(m_axi_mm2s_araddr[24]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -789,7 +1028,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[25] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[29]), .Q(m_axi_mm2s_araddr[25]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -797,7 +1036,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[26] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[30]), .Q(m_axi_mm2s_araddr[26]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -805,7 +1044,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[27] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[31]), .Q(m_axi_mm2s_araddr[27]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -813,7 +1052,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[28] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[32]), .Q(m_axi_mm2s_araddr[28]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -821,7 +1060,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[29] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[33]), .Q(m_axi_mm2s_araddr[29]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -829,7 +1068,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[2] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[6]), .Q(m_axi_mm2s_araddr[2]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -837,7 +1076,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[30] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[34]), .Q(m_axi_mm2s_araddr[30]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -845,7 +1084,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[31] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[35]), .Q(m_axi_mm2s_araddr[31]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -853,7 +1092,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[3] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[7]), .Q(m_axi_mm2s_araddr[3]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -861,7 +1100,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[4] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[8]), .Q(m_axi_mm2s_araddr[4]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -869,7 +1108,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[5] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[9]), .Q(m_axi_mm2s_araddr[5]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -877,7 +1116,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[6] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[10]), .Q(m_axi_mm2s_araddr[6]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -885,7 +1124,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[7] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[11]), .Q(m_axi_mm2s_araddr[7]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -893,7 +1132,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[8] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[12]), .Q(m_axi_mm2s_araddr[8]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -901,7 +1140,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_addr_reg_reg[9] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[13]), .Q(m_axi_mm2s_araddr[9]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -909,7 +1148,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_burst_reg_reg[0] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[47]), .Q(m_axi_mm2s_arburst), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -917,7 +1156,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_len_reg_reg[0] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[36]), .Q(m_axi_mm2s_arlen[0]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -925,7 +1164,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_len_reg_reg[1] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[37]), .Q(m_axi_mm2s_arlen[1]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -933,7 +1172,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_len_reg_reg[2] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[38]), .Q(m_axi_mm2s_arlen[2]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -941,15 +1180,23 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_len_reg_reg[3] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[39]), .Q(m_axi_mm2s_arlen[3]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_len_reg_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(sig_push_addr_reg1_out), + .D(p_1_out[40]), + .Q(m_axi_mm2s_arlen[4]), + .R(\sig_next_addr_reg[31]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \sig_next_size_reg_reg[0] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[44]), .Q(m_axi_mm2s_arsize[0]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -957,7 +1204,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl .INIT(1'b0)) \sig_next_size_reg_reg[1] (.C(m_axi_mm2s_aclk), - .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1 ), + .CE(sig_push_addr_reg1_out), .D(p_1_out[45]), .Q(m_axi_mm2s_arsize[1]), .R(\sig_next_addr_reg[31]_i_1_n_0 )); @@ -968,7 +1215,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl sig_posted_to_axi_2_reg (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_3 ), + .D(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_43 ), .Q(sig_posted_to_axi_2), .R(1'b0)); (* KEEP = "yes" *) @@ -978,75 +1225,547 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl sig_posted_to_axi_reg (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_3 ), + .D(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_43 ), .Q(sig_posted_to_axi), .R(1'b0)); endmodule +(* ORIG_REF_NAME = "axi_datamover_addr_cntl" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl__parameterized0 + (out, + \INFERRED_GEN.cnt_i_reg[0] , + sig_addr_reg_empty, + sig_addr2wsc_calc_error, + m_axi_s2mm_awburst, + m_axi_s2mm_awvalid, + sig_init_done, + sig_inhibit_rdy_n, + sig_clr_cmd2addr_valid3_out__0, + m_axi_s2mm_awaddr, + m_axi_s2mm_awlen, + m_axi_s2mm_awsize, + sig_stream_rst, + m_axi_s2mm_aclk, + sig_init_reg_reg, + m_axi_s2mm_awready, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_halt_reg, + p_22_out, + in); + output out; + output \INFERRED_GEN.cnt_i_reg[0] ; + output sig_addr_reg_empty; + output sig_addr2wsc_calc_error; + output [0:0]m_axi_s2mm_awburst; + output m_axi_s2mm_awvalid; + output sig_init_done; + output sig_inhibit_rdy_n; + output sig_clr_cmd2addr_valid3_out__0; + output [31:0]m_axi_s2mm_awaddr; + output [5:0]m_axi_s2mm_awlen; + output [1:0]m_axi_s2mm_awsize; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input sig_init_reg_reg; + input m_axi_s2mm_awready; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_halt_reg; + input p_22_out; + input [39:0]in; + + wire \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ; + wire \INFERRED_GEN.cnt_i_reg[0] ; + wire [39:0]in; + wire m_axi_s2mm_aclk; + wire [31:0]m_axi_s2mm_awaddr; + wire [0:0]m_axi_s2mm_awburst; + wire [5:0]m_axi_s2mm_awlen; + wire m_axi_s2mm_awready; + wire [1:0]m_axi_s2mm_awsize; + wire m_axi_s2mm_awvalid; + wire p_0_in; + wire [50:4]p_1_out; + wire p_22_out; + wire sig_addr2wsc_calc_error; + wire sig_addr_reg_empty; + wire sig_addr_reg_full; + wire sig_clr_cmd2addr_valid3_out__0; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_halt_reg; + wire sig_inhibit_rdy_n; + wire sig_init_done; + wire sig_init_reg_reg; + wire \sig_next_addr_reg[31]_i_1__0_n_0 ; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_posted_to_axi; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_posted_to_axi_2; + wire sig_stream_rst; + + assign out = sig_posted_to_axi; + Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized9 \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO + (.\INFERRED_GEN.cnt_i_reg[0] (\INFERRED_GEN.cnt_i_reg[0] ), + .\INFERRED_GEN.cnt_i_reg[0]_0 (sig_inhibit_rdy_n), + .in(in), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out({p_1_out[50],p_1_out[47],p_1_out[45:44],p_1_out[41:4]}), + .p_0_in(p_0_in), + .p_22_out(p_22_out), + .sig_addr_reg_empty_reg(sig_addr_reg_empty), + .sig_calc_error_reg_reg(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .sig_clr_cmd2addr_valid3_out__0(sig_clr_cmd2addr_valid3_out__0), + .sig_halt_reg(sig_halt_reg), + .sig_init_done(sig_init_done), + .sig_init_reg_reg(sig_init_reg_reg), + .sig_stream_rst(sig_stream_rst)); + FDSE #( + .INIT(1'b0)) + sig_addr_reg_empty_reg + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(1'b0), + .Q(sig_addr_reg_empty), + .S(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + sig_addr_reg_full_reg + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .Q(sig_addr_reg_full), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + sig_addr_valid_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_0_in), + .Q(m_axi_s2mm_awvalid), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + sig_calc_error_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[50]), + .Q(sig_addr2wsc_calc_error), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + LUT4 #( + .INIT(16'h08FF)) + \sig_next_addr_reg[31]_i_1__0 + (.I0(m_axi_s2mm_awready), + .I1(sig_addr_reg_full), + .I2(sig_addr2wsc_calc_error), + .I3(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .O(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[4]), + .Q(m_axi_s2mm_awaddr[0]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[14]), + .Q(m_axi_s2mm_awaddr[10]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[15]), + .Q(m_axi_s2mm_awaddr[11]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[16]), + .Q(m_axi_s2mm_awaddr[12]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[13] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[17]), + .Q(m_axi_s2mm_awaddr[13]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[14] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[18]), + .Q(m_axi_s2mm_awaddr[14]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[15] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[19]), + .Q(m_axi_s2mm_awaddr[15]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[16] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[20]), + .Q(m_axi_s2mm_awaddr[16]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[17] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[21]), + .Q(m_axi_s2mm_awaddr[17]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[18] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[22]), + .Q(m_axi_s2mm_awaddr[18]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[19] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[23]), + .Q(m_axi_s2mm_awaddr[19]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[5]), + .Q(m_axi_s2mm_awaddr[1]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[20] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[24]), + .Q(m_axi_s2mm_awaddr[20]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[21] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[25]), + .Q(m_axi_s2mm_awaddr[21]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[22] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[26]), + .Q(m_axi_s2mm_awaddr[22]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[23] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[27]), + .Q(m_axi_s2mm_awaddr[23]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[24] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[28]), + .Q(m_axi_s2mm_awaddr[24]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[25] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[29]), + .Q(m_axi_s2mm_awaddr[25]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[26] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[30]), + .Q(m_axi_s2mm_awaddr[26]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[27] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[31]), + .Q(m_axi_s2mm_awaddr[27]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[28] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[32]), + .Q(m_axi_s2mm_awaddr[28]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[29] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[33]), + .Q(m_axi_s2mm_awaddr[29]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[6]), + .Q(m_axi_s2mm_awaddr[2]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[30] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[34]), + .Q(m_axi_s2mm_awaddr[30]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[31] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[35]), + .Q(m_axi_s2mm_awaddr[31]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[7]), + .Q(m_axi_s2mm_awaddr[3]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[8]), + .Q(m_axi_s2mm_awaddr[4]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[9]), + .Q(m_axi_s2mm_awaddr[5]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[10]), + .Q(m_axi_s2mm_awaddr[6]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[11]), + .Q(m_axi_s2mm_awaddr[7]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[12]), + .Q(m_axi_s2mm_awaddr[8]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_addr_reg_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[13]), + .Q(m_axi_s2mm_awaddr[9]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_burst_reg_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[47]), + .Q(m_axi_s2mm_awburst), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_len_reg_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[36]), + .Q(m_axi_s2mm_awlen[0]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_len_reg_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[37]), + .Q(m_axi_s2mm_awlen[1]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_len_reg_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[38]), + .Q(m_axi_s2mm_awlen[2]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_len_reg_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[39]), + .Q(m_axi_s2mm_awlen[3]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_len_reg_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[40]), + .Q(m_axi_s2mm_awlen[4]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_len_reg_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[41]), + .Q(m_axi_s2mm_awlen[5]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_size_reg_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[44]), + .Q(m_axi_s2mm_awsize[0]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_next_size_reg_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .D(p_1_out[45]), + .Q(m_axi_s2mm_awsize[1]), + .R(\sig_next_addr_reg[31]_i_1__0_n_0 )); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + sig_posted_to_axi_2_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .Q(sig_posted_to_axi_2), + .R(sig_stream_rst)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + sig_posted_to_axi_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45 ), + .Q(sig_posted_to_axi), + .R(sig_stream_rst)); +endmodule + (* ORIG_REF_NAME = "axi_datamover_cmd_status" *) module Arty_Z7_20_axi_vdma_0_0_axi_datamover_cmd_status (\INFERRED_GEN.cnt_i_reg[1] , - sig_init_done, - sig_init_done_0, - sig_inhibit_rdy_n, + sig_calc_error_reg_reg, Q, E, - FIFO_Full_reg, - out, - sig_calc_error_reg_reg, sig_rd_sts_slverr_reg_reg, - interr_i_reg, - slverr_i_reg, + sig_inhibit_rdy_n, decerr_i_reg, + FIFO_Full_reg, + slverr_i_reg, + interr_i_reg, + out, SR, m_axi_mm2s_aclk, - sig_mmap_reset_reg_reg, - sig_mmap_reset_reg_reg_0, - sig_calc_error_pushed_reg, + in, sig_sm_halt_reg, sig_input_reg_empty, - sig_calc_error_pushed, - p_55_out, cmnd_wr, mm2s_halt, - p_57_out, sig_rsc2stat_status_valid, - sts_tready_reg, - in, sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_calc_error_pushed_reg, + sig_calc_error_pushed, + p_56_out, + p_58_out, + sts_tready_reg, \s_axis_cmd_tdata_reg[63] , - sig_rd_sts_slverr_reg_reg_0); + sig_rd_sts_slverr_reg_reg_0, + sig_init_reg2, + sig_init_reg); output \INFERRED_GEN.cnt_i_reg[1] ; - output sig_init_done; - output sig_init_done_0; - output sig_inhibit_rdy_n; + output sig_calc_error_reg_reg; output [0:0]Q; output [0:0]E; - output [0:0]FIFO_Full_reg; - output [49:0]out; - output sig_calc_error_reg_reg; output sig_rd_sts_slverr_reg_reg; - output interr_i_reg; - output slverr_i_reg; + output sig_inhibit_rdy_n; output decerr_i_reg; + output [0:0]FIFO_Full_reg; + output slverr_i_reg; + output interr_i_reg; + output [49:0]out; input [0:0]SR; input m_axi_mm2s_aclk; - input sig_mmap_reset_reg_reg; - input sig_mmap_reset_reg_reg_0; - input sig_calc_error_pushed_reg; + input [0:0]in; input sig_sm_halt_reg; input sig_input_reg_empty; - input sig_calc_error_pushed; - input p_55_out; input cmnd_wr; input mm2s_halt; - input p_57_out; input sig_rsc2stat_status_valid; - input sts_tready_reg; - input [0:0]in; input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_calc_error_pushed_reg; + input sig_calc_error_pushed; + input p_56_out; + input p_58_out; + input sts_tready_reg; input [48:0]\s_axis_cmd_tdata_reg[63] ; input [2:0]sig_rd_sts_slverr_reg_reg_0; + input sig_init_reg2; + input sig_init_reg; wire [0:0]E; wire [0:0]FIFO_Full_reg; @@ -1060,19 +1779,17 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_cmd_status wire m_axi_mm2s_aclk; wire mm2s_halt; wire [49:0]out; - wire p_55_out; - wire p_57_out; + wire p_56_out; + wire p_58_out; wire [48:0]\s_axis_cmd_tdata_reg[63] ; wire sig_calc_error_pushed; wire sig_calc_error_pushed_reg; wire sig_calc_error_reg_reg; wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; wire sig_inhibit_rdy_n; - wire sig_init_done; - wire sig_init_done_0; + wire sig_init_reg; + wire sig_init_reg2; wire sig_input_reg_empty; - wire sig_mmap_reset_reg_reg; - wire sig_mmap_reset_reg_reg_0; wire sig_rd_sts_slverr_reg_reg; wire [2:0]sig_rd_sts_slverr_reg_reg_0; wire sig_rsc2stat_status_valid; @@ -1088,16 +1805,16 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_cmd_status .decerr_i_reg(decerr_i_reg), .interr_i_reg(interr_i_reg), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .p_57_out(p_57_out), + .p_58_out(p_58_out), .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .sig_init_done_0(sig_init_done_0), - .sig_mmap_reset_reg_reg(sig_mmap_reset_reg_reg_0), + .sig_init_reg(sig_init_reg), + .sig_init_reg2(sig_init_reg2), .sig_rd_sts_slverr_reg_reg(sig_rd_sts_slverr_reg_reg), .sig_rd_sts_slverr_reg_reg_0(sig_rd_sts_slverr_reg_reg_0), .sig_rsc2stat_status_valid(sig_rsc2stat_status_valid), .slverr_i_reg(slverr_i_reg), .sts_tready_reg(sts_tready_reg)); - Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo I_CMD_FIFO + Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo_22 I_CMD_FIFO (.E(E), .Q(Q), .SR(SR), @@ -1106,53 +1823,297 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_cmd_status .m_axi_mm2s_aclk(m_axi_mm2s_aclk), .mm2s_halt(mm2s_halt), .out(out), - .p_55_out(p_55_out), + .p_56_out(p_56_out), .\s_axis_cmd_tdata_reg[63] (\s_axis_cmd_tdata_reg[63] ), .sig_calc_error_pushed(sig_calc_error_pushed), .sig_calc_error_pushed_reg(sig_calc_error_pushed_reg), .sig_calc_error_reg_reg(sig_calc_error_reg_reg), - .sig_init_done(sig_init_done), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_init_reg(sig_init_reg), + .sig_init_reg2(sig_init_reg2), .sig_input_reg_empty(sig_input_reg_empty), - .sig_mmap_reset_reg_reg(sig_mmap_reset_reg_reg), .sig_sm_halt_reg(sig_sm_halt_reg)); endmodule -(* ORIG_REF_NAME = "axi_datamover_fifo" *) -module Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo +(* ORIG_REF_NAME = "axi_datamover_cmd_status" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_cmd_status__parameterized0 (sig_init_done, + sig_init_done_0, + sig_calc_error_reg_reg, Q, - E, + p_9_out, + FIFO_Full_reg, + s_axis_cmd_tvalid_reg, + CO, + \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg , + decerr_i_reg, + slverr_i_reg, + interr_i_reg, + sig_dqual_reg_empty_reg, out, - sig_calc_error_reg_reg, - SR, - m_axi_mm2s_aclk, - sig_mmap_reset_reg_reg, - sig_calc_error_pushed_reg, - sig_sm_halt_reg, + \GEN_STS_GRTR_THAN_8.ovrflo_err_reg , + sig_stream_rst, + m_axi_s2mm_aclk, + sig_init_reg_reg, + sig_init_reg_reg_0, + sig_psm_halt, sig_input_reg_empty, - sig_calc_error_pushed, - p_55_out, - cmnd_wr, - mm2s_halt, - in, + p_10_out, + s2mm_halt, + s2mm_soft_reset, + dma_err, + cmnd_wr_1, + \hsize_vid_reg[15] , + \hsize_vid_reg[2] , + S, + sig_wsc2stat_status_valid, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + s_axis_s2mm_cmd_tvalid, + m_axis_s2mm_sts_tready, + \s_axis_cmd_tdata_reg[63] , + in); + output sig_init_done; + output sig_init_done_0; + output sig_calc_error_reg_reg; + output [0:0]Q; + output p_9_out; + output [0:0]FIFO_Full_reg; + output [0:0]s_axis_cmd_tvalid_reg; + output [0:0]CO; + output \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ; + output decerr_i_reg; + output slverr_i_reg; + output interr_i_reg; + output sig_dqual_reg_empty_reg; + output [49:0]out; + output [0:0]\GEN_STS_GRTR_THAN_8.ovrflo_err_reg ; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input sig_init_reg_reg; + input sig_init_reg_reg_0; + input sig_psm_halt; + input sig_input_reg_empty; + input p_10_out; + input s2mm_halt; + input s2mm_soft_reset; + input dma_err; + input cmnd_wr_1; + input [12:0]\hsize_vid_reg[15] ; + input [0:0]\hsize_vid_reg[2] ; + input [0:0]S; + input sig_wsc2stat_status_valid; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input s_axis_s2mm_cmd_tvalid; + input m_axis_s2mm_sts_tready; + input [48:0]\s_axis_cmd_tdata_reg[63] ; + input [16:0]in; + + wire [0:0]CO; + wire [0:0]FIFO_Full_reg; + wire \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ; + wire [0:0]\GEN_STS_GRTR_THAN_8.ovrflo_err_reg ; + wire [0:0]Q; + wire [0:0]S; + wire cmnd_wr_1; + wire decerr_i_reg; + wire dma_err; + wire [12:0]\hsize_vid_reg[15] ; + wire [0:0]\hsize_vid_reg[2] ; + wire [16:0]in; + wire interr_i_reg; + wire m_axi_s2mm_aclk; + wire m_axis_s2mm_sts_tready; + wire [49:0]out; + wire p_10_out; + wire p_9_out; + wire s2mm_halt; + wire s2mm_soft_reset; + wire [48:0]\s_axis_cmd_tdata_reg[63] ; + wire [0:0]s_axis_cmd_tvalid_reg; + wire s_axis_s2mm_cmd_tvalid; + wire sig_calc_error_reg_reg; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_dqual_reg_empty_reg; + wire sig_init_done; + wire sig_init_done_0; + wire sig_init_reg_reg; + wire sig_init_reg_reg_0; + wire sig_input_reg_empty; + wire sig_psm_halt; + wire sig_stream_rst; + wire sig_wsc2stat_status_valid; + wire slverr_i_reg; + + Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized4 \GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO + (.CO(CO), + .\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg (\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ), + .\GEN_STS_GRTR_THAN_8.ovrflo_err_reg (\GEN_STS_GRTR_THAN_8.ovrflo_err_reg ), + .Q(FIFO_Full_reg), + .S(S), + .decerr_i_reg(decerr_i_reg), + .dma_err(dma_err), + .\hsize_vid_reg[15] (\hsize_vid_reg[15] ), + .\hsize_vid_reg[2] (\hsize_vid_reg[2] ), + .in(in), + .interr_i_reg(interr_i_reg), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .m_axis_s2mm_sts_tready(m_axis_s2mm_sts_tready), + .p_9_out(p_9_out), + .s2mm_halt(s2mm_halt), + .s2mm_soft_reset(s2mm_soft_reset), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_dqual_reg_empty_reg(sig_dqual_reg_empty_reg), + .sig_init_done_0(sig_init_done_0), + .sig_init_reg_reg(sig_init_reg_reg_0), + .sig_stream_rst(sig_stream_rst), + .sig_wsc2stat_status_valid(sig_wsc2stat_status_valid), + .slverr_i_reg(slverr_i_reg)); + Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo I_CMD_FIFO + (.Q(Q), + .cmnd_wr_1(cmnd_wr_1), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out), + .p_10_out(p_10_out), + .s2mm_halt(s2mm_halt), + .\s_axis_cmd_tdata_reg[63] (\s_axis_cmd_tdata_reg[63] ), + .s_axis_cmd_tvalid_reg(s_axis_cmd_tvalid_reg), + .s_axis_s2mm_cmd_tvalid(s_axis_s2mm_cmd_tvalid), + .sig_calc_error_reg_reg(sig_calc_error_reg_reg), + .sig_init_done(sig_init_done), + .sig_init_reg_reg(sig_init_reg_reg), + .sig_input_reg_empty(sig_input_reg_empty), + .sig_psm_halt(sig_psm_halt), + .sig_stream_rst(sig_stream_rst)); +endmodule + +(* ORIG_REF_NAME = "axi_datamover_fifo" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo + (sig_init_done, + sig_calc_error_reg_reg, + Q, + s_axis_cmd_tvalid_reg, + out, + sig_stream_rst, + m_axi_s2mm_aclk, + sig_init_reg_reg, + sig_psm_halt, + sig_input_reg_empty, + p_10_out, + cmnd_wr_1, + s2mm_halt, + s_axis_s2mm_cmd_tvalid, \s_axis_cmd_tdata_reg[63] ); output sig_init_done; + output sig_calc_error_reg_reg; output [0:0]Q; - output [0:0]E; + output [0:0]s_axis_cmd_tvalid_reg; output [49:0]out; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input sig_init_reg_reg; + input sig_psm_halt; + input sig_input_reg_empty; + input p_10_out; + input cmnd_wr_1; + input s2mm_halt; + input s_axis_s2mm_cmd_tvalid; + input [48:0]\s_axis_cmd_tdata_reg[63] ; + + wire [0:0]Q; + wire cmnd_wr_1; + wire m_axi_s2mm_aclk; + wire [49:0]out; + wire p_10_out; + wire s2mm_halt; + wire [48:0]\s_axis_cmd_tdata_reg[63] ; + wire [0:0]s_axis_cmd_tvalid_reg; + wire s_axis_s2mm_cmd_tvalid; + wire sig_calc_error_reg_reg; + wire sig_inhibit_rdy_n; + wire sig_inhibit_rdy_n_i_1_n_0; + wire sig_init_done; + wire sig_init_reg_reg; + wire sig_input_reg_empty; + wire sig_psm_halt; + wire sig_stream_rst; + + Arty_Z7_20_axi_vdma_0_0_srl_fifo_f \USE_SRL_FIFO.I_SYNC_FIFO + (.Q(Q), + .cmnd_wr_1(cmnd_wr_1), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out), + .p_10_out(p_10_out), + .s2mm_halt(s2mm_halt), + .\s_axis_cmd_tdata_reg[63] (\s_axis_cmd_tdata_reg[63] ), + .s_axis_cmd_tvalid_reg(s_axis_cmd_tvalid_reg), + .s_axis_s2mm_cmd_tvalid(s_axis_s2mm_cmd_tvalid), + .sig_calc_error_reg_reg(sig_calc_error_reg_reg), + .sig_inhibit_rdy_n(sig_inhibit_rdy_n), + .sig_input_reg_empty(sig_input_reg_empty), + .sig_psm_halt(sig_psm_halt), + .sig_stream_rst(sig_stream_rst)); + LUT2 #( + .INIT(4'hE)) + sig_inhibit_rdy_n_i_1 + (.I0(sig_init_done), + .I1(sig_inhibit_rdy_n), + .O(sig_inhibit_rdy_n_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + sig_inhibit_rdy_n_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_inhibit_rdy_n_i_1_n_0), + .Q(sig_inhibit_rdy_n), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + sig_init_done_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_init_reg_reg), + .Q(sig_init_done), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "axi_datamover_fifo" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo_22 + (sig_calc_error_reg_reg, + Q, + E, + out, + SR, + m_axi_mm2s_aclk, + in, + sig_sm_halt_reg, + sig_input_reg_empty, + cmnd_wr, + mm2s_halt, + sig_calc_error_pushed_reg, + sig_calc_error_pushed, + p_56_out, + \s_axis_cmd_tdata_reg[63] , + sig_init_reg2, + sig_init_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg); output sig_calc_error_reg_reg; + output [0:0]Q; + output [0:0]E; + output [49:0]out; input [0:0]SR; input m_axi_mm2s_aclk; - input sig_mmap_reset_reg_reg; - input sig_calc_error_pushed_reg; + input [0:0]in; input sig_sm_halt_reg; input sig_input_reg_empty; - input sig_calc_error_pushed; - input p_55_out; input cmnd_wr; input mm2s_halt; - input [0:0]in; + input sig_calc_error_pushed_reg; + input sig_calc_error_pushed; + input p_56_out; input [48:0]\s_axis_cmd_tdata_reg[63] ; + input sig_init_reg2; + input sig_init_reg; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; wire [0:0]E; wire [0:0]Q; @@ -1162,19 +2123,22 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo wire m_axi_mm2s_aclk; wire mm2s_halt; wire [49:0]out; - wire p_55_out; + wire p_56_out; wire [48:0]\s_axis_cmd_tdata_reg[63] ; wire sig_calc_error_pushed; wire sig_calc_error_pushed_reg; wire sig_calc_error_reg_reg; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; wire sig_inhibit_rdy_n; - wire sig_inhibit_rdy_n_i_1__3_n_0; + wire sig_inhibit_rdy_n_i_1_n_0; wire sig_init_done; + wire sig_init_done_i_1_n_0; + wire sig_init_reg; + wire sig_init_reg2; wire sig_input_reg_empty; - wire sig_mmap_reset_reg_reg; wire sig_sm_halt_reg; - Arty_Z7_20_axi_vdma_0_0_srl_fifo_f \USE_SRL_FIFO.I_SYNC_FIFO + Arty_Z7_20_axi_vdma_0_0_srl_fifo_f_23 \USE_SRL_FIFO.I_SYNC_FIFO (.E(E), .Q(Q), .SR(SR), @@ -1183,7 +2147,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo .m_axi_mm2s_aclk(m_axi_mm2s_aclk), .mm2s_halt(mm2s_halt), .out(out), - .p_55_out(p_55_out), + .p_56_out(p_56_out), .\s_axis_cmd_tdata_reg[63] (\s_axis_cmd_tdata_reg[63] ), .sig_calc_error_pushed(sig_calc_error_pushed), .sig_calc_error_pushed_reg(sig_calc_error_pushed_reg), @@ -1193,24 +2157,32 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo .sig_sm_halt_reg(sig_sm_halt_reg)); LUT2 #( .INIT(4'hE)) - sig_inhibit_rdy_n_i_1__3 + sig_inhibit_rdy_n_i_1 (.I0(sig_init_done), .I1(sig_inhibit_rdy_n), - .O(sig_inhibit_rdy_n_i_1__3_n_0)); + .O(sig_inhibit_rdy_n_i_1_n_0)); FDRE #( .INIT(1'b0)) sig_inhibit_rdy_n_reg (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(sig_inhibit_rdy_n_i_1__3_n_0), + .D(sig_inhibit_rdy_n_i_1_n_0), .Q(sig_inhibit_rdy_n), .R(SR)); + LUT4 #( + .INIT(16'h0080)) + sig_init_done_i_1 + (.I0(sig_init_reg2), + .I1(sig_init_reg), + .I2(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I3(sig_init_done), + .O(sig_init_done_i_1_n_0)); FDRE #( .INIT(1'b0)) sig_init_done_reg (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(sig_mmap_reset_reg_reg), + .D(sig_init_done_i_1_n_0), .Q(sig_init_done), .R(1'b0)); endmodule @@ -1218,37 +2190,37 @@ endmodule (* ORIG_REF_NAME = "axi_datamover_fifo" *) module Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized0 (\INFERRED_GEN.cnt_i_reg[1] , - sig_init_done_0, + sig_rd_sts_slverr_reg_reg, \INFERRED_GEN.cnt_i_reg[1]_0 , + decerr_i_reg, Q, - sig_rd_sts_slverr_reg_reg, - interr_i_reg, slverr_i_reg, - decerr_i_reg, + interr_i_reg, SR, m_axi_mm2s_aclk, - sig_mmap_reset_reg_reg, - p_57_out, sig_rsc2stat_status_valid, - sts_tready_reg, sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_rd_sts_slverr_reg_reg_0); + p_58_out, + sts_tready_reg, + sig_rd_sts_slverr_reg_reg_0, + sig_init_reg2, + sig_init_reg); output \INFERRED_GEN.cnt_i_reg[1] ; - output sig_init_done_0; + output sig_rd_sts_slverr_reg_reg; output \INFERRED_GEN.cnt_i_reg[1]_0 ; + output decerr_i_reg; output [0:0]Q; - output sig_rd_sts_slverr_reg_reg; - output interr_i_reg; output slverr_i_reg; - output decerr_i_reg; + output interr_i_reg; input [0:0]SR; input m_axi_mm2s_aclk; - input sig_mmap_reset_reg_reg; - input p_57_out; input sig_rsc2stat_status_valid; - input sts_tready_reg; input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input p_58_out; + input sts_tready_reg; input [2:0]sig_rd_sts_slverr_reg_reg_0; + input sig_init_reg2; + input sig_init_reg; wire \INFERRED_GEN.cnt_i_reg[1] ; wire \INFERRED_GEN.cnt_i_reg[1]_0 ; @@ -1257,11 +2229,13 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized0 wire decerr_i_reg; wire interr_i_reg; wire m_axi_mm2s_aclk; - wire p_57_out; + wire p_58_out; wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; wire sig_inhibit_rdy_n_i_1_n_0; - wire sig_init_done_0; - wire sig_mmap_reset_reg_reg; + wire sig_init_done; + wire sig_init_done_i_1_n_0; + wire sig_init_reg; + wire sig_init_reg2; wire sig_rd_sts_slverr_reg_reg; wire [2:0]sig_rd_sts_slverr_reg_reg_0; wire sig_rsc2stat_status_valid; @@ -1275,7 +2249,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized0 .decerr_i_reg(decerr_i_reg), .interr_i_reg(interr_i_reg), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .p_57_out(p_57_out), + .p_58_out(p_58_out), .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), .sig_inhibit_rdy_n_reg(\INFERRED_GEN.cnt_i_reg[1]_0 ), .sig_rd_sts_slverr_reg_reg(sig_rd_sts_slverr_reg_reg), @@ -1286,7 +2260,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized0 LUT2 #( .INIT(4'hE)) sig_inhibit_rdy_n_i_1 - (.I0(sig_init_done_0), + (.I0(sig_init_done), .I1(\INFERRED_GEN.cnt_i_reg[1]_0 ), .O(sig_inhibit_rdy_n_i_1_n_0)); FDRE #( @@ -1297,67 +2271,75 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized0 .D(sig_inhibit_rdy_n_i_1_n_0), .Q(\INFERRED_GEN.cnt_i_reg[1]_0 ), .R(SR)); + LUT4 #( + .INIT(16'h0080)) + sig_init_done_i_1 + (.I0(sig_init_reg2), + .I1(sig_init_reg), + .I2(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I3(sig_init_done), + .O(sig_init_done_i_1_n_0)); FDRE #( .INIT(1'b0)) sig_init_done_reg (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(sig_mmap_reset_reg_reg), - .Q(sig_init_done_0), + .D(sig_init_done_i_1_n_0), + .Q(sig_init_done), .R(1'b0)); endmodule (* ORIG_REF_NAME = "axi_datamover_fifo" *) module Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized1 (sig_init_reg2, - sig_calc_error_reg_reg, - sel, - sig_posted_to_axi_reg, sig_addr_valid_reg_reg, out, + sig_posted_to_axi_2_reg, + sel, + sig_push_addr_reg1_out, SR, sig_init_reg, m_axi_mm2s_aclk, - sig_mstr2addr_cmd_valid, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_data2addr_stop_req, sig_addr_reg_empty, sig_sf_allow_addr_req, + sig_data2addr_stop_req, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_mstr2addr_cmd_valid, in); output sig_init_reg2; - output sig_calc_error_reg_reg; - output sel; - output sig_posted_to_axi_reg; output sig_addr_valid_reg_reg; - output [39:0]out; + output [40:0]out; + output sig_posted_to_axi_2_reg; + output sel; + output sig_push_addr_reg1_out; input [0:0]SR; input sig_init_reg; input m_axi_mm2s_aclk; - input sig_mstr2addr_cmd_valid; - input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - input sig_data2addr_stop_req; input sig_addr_reg_empty; input sig_sf_allow_addr_req; - input [37:0]in; + input sig_data2addr_stop_req; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_mstr2addr_cmd_valid; + input [38:0]in; wire [0:0]SR; - wire [37:0]in; + wire [38:0]in; wire m_axi_mm2s_aclk; - wire [39:0]out; + wire [40:0]out; wire sel; wire sig_addr_reg_empty; wire sig_addr_valid_reg_reg; - wire sig_calc_error_reg_reg; wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; wire sig_data2addr_stop_req; wire sig_inhibit_rdy_n; - wire sig_inhibit_rdy_n_i_1__0_n_0; + wire sig_inhibit_rdy_n_i_1_n_0; wire sig_init_done; - wire sig_init_done_i_1__1_n_0; + wire sig_init_done_i_1_n_0; wire sig_init_reg; wire sig_init_reg2; wire sig_mstr2addr_cmd_valid; - wire sig_posted_to_axi_reg; + wire sig_posted_to_axi_2_reg; + wire sig_push_addr_reg1_out; wire sig_sf_allow_addr_req; Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized1 \USE_SRL_FIFO.I_SYNC_FIFO @@ -1366,43 +2348,43 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized1 .m_axi_mm2s_aclk(m_axi_mm2s_aclk), .out(out), .sig_addr_reg_empty(sig_addr_reg_empty), + .sig_addr_reg_empty_reg(sig_push_addr_reg1_out), .sig_addr_valid_reg_reg(sig_addr_valid_reg_reg), - .sig_calc_error_reg_reg(sig_calc_error_reg_reg), - .sig_calc_error_reg_reg_0(sel), + .sig_calc_error_reg_reg(sel), .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), .sig_data2addr_stop_req(sig_data2addr_stop_req), .sig_inhibit_rdy_n(sig_inhibit_rdy_n), .sig_mstr2addr_cmd_valid(sig_mstr2addr_cmd_valid), - .sig_posted_to_axi_reg(sig_posted_to_axi_reg), + .sig_posted_to_axi_2_reg(sig_posted_to_axi_2_reg), .sig_sf_allow_addr_req(sig_sf_allow_addr_req)); LUT2 #( .INIT(4'hE)) - sig_inhibit_rdy_n_i_1__0 + sig_inhibit_rdy_n_i_1 (.I0(sig_init_done), .I1(sig_inhibit_rdy_n), - .O(sig_inhibit_rdy_n_i_1__0_n_0)); + .O(sig_inhibit_rdy_n_i_1_n_0)); FDRE #( .INIT(1'b0)) sig_inhibit_rdy_n_reg (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(sig_inhibit_rdy_n_i_1__0_n_0), + .D(sig_inhibit_rdy_n_i_1_n_0), .Q(sig_inhibit_rdy_n), .R(SR)); LUT4 #( .INIT(16'h0080)) - sig_init_done_i_1__1 - (.I0(sig_init_reg), - .I1(sig_init_reg2), + sig_init_done_i_1 + (.I0(sig_init_reg2), + .I1(sig_init_reg), .I2(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), .I3(sig_init_done), - .O(sig_init_done_i_1__1_n_0)); + .O(sig_init_done_i_1_n_0)); FDRE #( .INIT(1'b0)) sig_init_done_reg (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(sig_init_done_i_1__1_n_0), + .D(sig_init_done_i_1_n_0), .Q(sig_init_done), .R(1'b0)); FDSE #( @@ -1415,115 +2397,313 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized1 .S(SR)); endmodule +(* ORIG_REF_NAME = "axi_datamover_fifo" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized10 + (\INFERRED_GEN.cnt_i_reg[0] , + sig_init_done, + sig_last_dbeat_reg, + sig_push_dqual_reg, + sig_ld_new_cmd_reg_reg, + sig_next_calc_error_reg_reg, + sig_good_mmap_dbeat12_out__0, + D, + \INFERRED_GEN.cnt_i_reg[0]_0 , + E, + out, + sig_dqual_reg_empty_reg, + sig_clr_cmd2data_valid4_out__0, + sig_stream_rst, + m_axi_s2mm_aclk, + sig_init_reg_reg, + sig_first_dbeat1__0, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_single_dbeat, + sig_last_dbeat_reg_0, + sig_ld_new_cmd_reg, + sig_next_calc_error_reg, + \sig_dbeat_cntr_reg[1] , + sig_dqual_reg_full_reg, + Q, + \sig_dbeat_cntr_reg[4] , + p_11_out, + \sig_dbeat_cntr_reg[2] , + \sig_dbeat_cntr_reg[3] , + sig_next_sequential_reg, + sig_dqual_reg_empty, + sig_halt_reg, + sig_m_valid_out_reg, + sig_s_ready_out_reg, + sig_wdc_status_going_full, + sig_inhibit_rdy_n_reg_0, + sig_wsc2stat_status_valid, + sig_addr_posted_cntr, + sig_halt_reg_dly3, + sig_last_mmap_dbeat_reg, + sig_posted_to_axi_reg, + sig_xfer_calc_err_reg_reg); + output \INFERRED_GEN.cnt_i_reg[0] ; + output sig_init_done; + output sig_last_dbeat_reg; + output sig_push_dqual_reg; + output sig_ld_new_cmd_reg_reg; + output sig_next_calc_error_reg_reg; + output sig_good_mmap_dbeat12_out__0; + output [7:0]D; + output \INFERRED_GEN.cnt_i_reg[0]_0 ; + output [0:0]E; + output [2:0]out; + output sig_dqual_reg_empty_reg; + output sig_clr_cmd2data_valid4_out__0; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input sig_init_reg_reg; + input sig_first_dbeat1__0; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_single_dbeat; + input sig_last_dbeat_reg_0; + input sig_ld_new_cmd_reg; + input sig_next_calc_error_reg; + input \sig_dbeat_cntr_reg[1] ; + input sig_dqual_reg_full_reg; + input [7:0]Q; + input \sig_dbeat_cntr_reg[4] ; + input p_11_out; + input \sig_dbeat_cntr_reg[2] ; + input \sig_dbeat_cntr_reg[3] ; + input sig_next_sequential_reg; + input sig_dqual_reg_empty; + input sig_halt_reg; + input sig_m_valid_out_reg; + input sig_s_ready_out_reg; + input sig_wdc_status_going_full; + input sig_inhibit_rdy_n_reg_0; + input sig_wsc2stat_status_valid; + input [2:0]sig_addr_posted_cntr; + input sig_halt_reg_dly3; + input sig_last_mmap_dbeat_reg; + input sig_posted_to_axi_reg; + input [8:0]sig_xfer_calc_err_reg_reg; + + wire [7:0]D; + wire [0:0]E; + wire \INFERRED_GEN.cnt_i_reg[0] ; + wire \INFERRED_GEN.cnt_i_reg[0]_0 ; + wire [7:0]Q; + wire m_axi_s2mm_aclk; + wire [2:0]out; + wire p_11_out; + wire [2:0]sig_addr_posted_cntr; + wire sig_clr_cmd2data_valid4_out__0; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire \sig_dbeat_cntr_reg[1] ; + wire \sig_dbeat_cntr_reg[2] ; + wire \sig_dbeat_cntr_reg[3] ; + wire \sig_dbeat_cntr_reg[4] ; + wire sig_dqual_reg_empty; + wire sig_dqual_reg_empty_reg; + wire sig_dqual_reg_full_reg; + wire sig_first_dbeat1__0; + wire sig_good_mmap_dbeat12_out__0; + wire sig_halt_reg; + wire sig_halt_reg_dly3; + wire sig_inhibit_rdy_n_i_1_n_0; + wire sig_inhibit_rdy_n_reg_0; + wire sig_init_done; + wire sig_init_reg_reg; + wire sig_last_dbeat_reg; + wire sig_last_dbeat_reg_0; + wire sig_last_mmap_dbeat_reg; + wire sig_ld_new_cmd_reg; + wire sig_ld_new_cmd_reg_reg; + wire sig_m_valid_out_reg; + wire sig_next_calc_error_reg; + wire sig_next_calc_error_reg_reg; + wire sig_next_sequential_reg; + wire sig_posted_to_axi_reg; + wire sig_push_dqual_reg; + wire sig_s_ready_out_reg; + wire sig_single_dbeat; + wire sig_stream_rst; + wire sig_wdc_status_going_full; + wire sig_wsc2stat_status_valid; + wire [8:0]sig_xfer_calc_err_reg_reg; + + Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized10 \USE_SRL_FIFO.I_SYNC_FIFO + (.D(D), + .E(E), + .\INFERRED_GEN.cnt_i_reg[0] (\INFERRED_GEN.cnt_i_reg[0] ), + .Q(Q), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out), + .p_11_out(p_11_out), + .sig_addr_posted_cntr(sig_addr_posted_cntr), + .sig_clr_cmd2data_valid4_out__0(sig_clr_cmd2data_valid4_out__0), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .\sig_dbeat_cntr_reg[1] (\sig_dbeat_cntr_reg[1] ), + .\sig_dbeat_cntr_reg[2] (\sig_dbeat_cntr_reg[2] ), + .\sig_dbeat_cntr_reg[3] (\sig_dbeat_cntr_reg[3] ), + .\sig_dbeat_cntr_reg[4] (\sig_dbeat_cntr_reg[4] ), + .sig_dqual_reg_empty(sig_dqual_reg_empty), + .sig_dqual_reg_empty_reg(sig_push_dqual_reg), + .sig_dqual_reg_empty_reg_0(sig_good_mmap_dbeat12_out__0), + .sig_dqual_reg_empty_reg_1(sig_dqual_reg_empty_reg), + .sig_dqual_reg_full_reg(sig_dqual_reg_full_reg), + .sig_first_dbeat1__0(sig_first_dbeat1__0), + .sig_halt_reg(sig_halt_reg), + .sig_halt_reg_dly3(sig_halt_reg_dly3), + .sig_inhibit_rdy_n_reg(\INFERRED_GEN.cnt_i_reg[0]_0 ), + .sig_inhibit_rdy_n_reg_0(sig_inhibit_rdy_n_reg_0), + .sig_last_dbeat_reg(sig_last_dbeat_reg), + .sig_last_dbeat_reg_0(sig_last_dbeat_reg_0), + .sig_last_mmap_dbeat_reg(sig_last_mmap_dbeat_reg), + .sig_ld_new_cmd_reg(sig_ld_new_cmd_reg), + .sig_ld_new_cmd_reg_reg(sig_ld_new_cmd_reg_reg), + .sig_m_valid_out_reg(sig_m_valid_out_reg), + .sig_next_calc_error_reg(sig_next_calc_error_reg), + .sig_next_calc_error_reg_reg(sig_next_calc_error_reg_reg), + .sig_next_sequential_reg(sig_next_sequential_reg), + .sig_posted_to_axi_reg(sig_posted_to_axi_reg), + .sig_s_ready_out_reg(sig_s_ready_out_reg), + .sig_single_dbeat(sig_single_dbeat), + .sig_stream_rst(sig_stream_rst), + .sig_wdc_status_going_full(sig_wdc_status_going_full), + .sig_wsc2stat_status_valid(sig_wsc2stat_status_valid), + .sig_xfer_calc_err_reg_reg(sig_xfer_calc_err_reg_reg)); + LUT2 #( + .INIT(4'hE)) + sig_inhibit_rdy_n_i_1 + (.I0(sig_init_done), + .I1(\INFERRED_GEN.cnt_i_reg[0]_0 ), + .O(sig_inhibit_rdy_n_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + sig_inhibit_rdy_n_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_inhibit_rdy_n_i_1_n_0), + .Q(\INFERRED_GEN.cnt_i_reg[0]_0 ), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + sig_init_done_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_init_reg_reg), + .Q(sig_init_done), + .R(1'b0)); +endmodule + (* ORIG_REF_NAME = "axi_datamover_fifo" *) module Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized2 - (sig_init_done, + (D, sig_push_dqual_reg, + sig_next_cmd_cmplt_reg_reg, + sig_dqual_reg_empty_reg, sel, - E, - D, out, - sig_good_mmap_dbeat7_out__0, - sig_ld_new_cmd_reg_reg, sig_last_dbeat_reg, - sig_next_cmd_cmplt_reg_reg, + E, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram , SR, m_axi_mm2s_aclk, - sig_mmap_reset_reg_reg, - sig_mstr2data_cmd_valid, - \sig_dbeat_cntr_reg[2] , Q, + \sig_dbeat_cntr_reg[0] , + m_axi_mm2s_rlast, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_mstr2data_cmd_valid, + \sig_dbeat_cntr_reg[3] , + \sig_dbeat_cntr_reg[5] , sig_next_sequential_reg, sig_last_dbeat, sig_dqual_reg_empty, - m_axi_mm2s_rvalid, - sig_halt_reg_reg, - ram_full_i_reg, - sig_advance_pipe9_out__1, sig_rsc2stat_status_valid, FIFO_Full_reg, sig_inhibit_rdy_n, - sig_next_calc_error_reg, - sig_addr_posted_cntr, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_ld_new_cmd_reg, - sig_dbeat_cntr_eq_1, + sig_next_calc_error_reg_reg, + \sig_addr_posted_cntr_reg[2] , + \sig_addr_posted_cntr_reg[1] , + \sig_addr_posted_cntr_reg[0] , + ram_full_i_reg, + sig_halt_reg_reg, + m_axi_mm2s_rvalid, sig_dqual_reg_full, - m_axi_mm2s_rlast, - \sig_dbeat_cntr_reg[3] , - \sig_dbeat_cntr_reg[4] , - in); - output sig_init_done; + sig_data2rsc_valid, + in, + sig_init_reg2, + sig_init_reg); + output [7:0]D; output sig_push_dqual_reg; + output sig_next_cmd_cmplt_reg_reg; + output sig_dqual_reg_empty_reg; output sel; - output [0:0]E; - output [7:0]D; output [3:0]out; - output sig_good_mmap_dbeat7_out__0; - output sig_ld_new_cmd_reg_reg; output sig_last_dbeat_reg; - output sig_next_cmd_cmplt_reg_reg; + output [0:0]E; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; input [0:0]SR; input m_axi_mm2s_aclk; - input sig_mmap_reset_reg_reg; - input sig_mstr2data_cmd_valid; - input \sig_dbeat_cntr_reg[2] ; input [7:0]Q; + input \sig_dbeat_cntr_reg[0] ; + input m_axi_mm2s_rlast; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_mstr2data_cmd_valid; + input \sig_dbeat_cntr_reg[3] ; + input \sig_dbeat_cntr_reg[5] ; input sig_next_sequential_reg; input sig_last_dbeat; input sig_dqual_reg_empty; - input m_axi_mm2s_rvalid; - input sig_halt_reg_reg; - input ram_full_i_reg; - input sig_advance_pipe9_out__1; input sig_rsc2stat_status_valid; input FIFO_Full_reg; input sig_inhibit_rdy_n; - input sig_next_calc_error_reg; - input [2:0]sig_addr_posted_cntr; - input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - input sig_ld_new_cmd_reg; - input sig_dbeat_cntr_eq_1; + input sig_next_calc_error_reg_reg; + input \sig_addr_posted_cntr_reg[2] ; + input \sig_addr_posted_cntr_reg[1] ; + input \sig_addr_posted_cntr_reg[0] ; + input ram_full_i_reg; + input sig_halt_reg_reg; + input m_axi_mm2s_rvalid; input sig_dqual_reg_full; - input m_axi_mm2s_rlast; - input \sig_dbeat_cntr_reg[3] ; - input \sig_dbeat_cntr_reg[4] ; - input [7:0]in; + input sig_data2rsc_valid; + input [8:0]in; + input sig_init_reg2; + input sig_init_reg; wire [7:0]D; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; wire [0:0]E; wire FIFO_Full_reg; wire [7:0]Q; wire [0:0]SR; - wire [7:0]in; + wire [8:0]in; wire m_axi_mm2s_aclk; wire m_axi_mm2s_rlast; wire m_axi_mm2s_rvalid; wire [3:0]out; wire ram_full_i_reg; wire sel; - wire [2:0]sig_addr_posted_cntr; - wire sig_advance_pipe9_out__1; + wire \sig_addr_posted_cntr_reg[0] ; + wire \sig_addr_posted_cntr_reg[1] ; + wire \sig_addr_posted_cntr_reg[2] ; wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - wire sig_dbeat_cntr_eq_1; - wire \sig_dbeat_cntr_reg[2] ; + wire sig_data2rsc_valid; + wire \sig_dbeat_cntr_reg[0] ; wire \sig_dbeat_cntr_reg[3] ; - wire \sig_dbeat_cntr_reg[4] ; + wire \sig_dbeat_cntr_reg[5] ; wire sig_dqual_reg_empty; + wire sig_dqual_reg_empty_reg; wire sig_dqual_reg_full; - wire sig_good_mmap_dbeat7_out__0; wire sig_halt_reg_reg; wire sig_inhibit_rdy_n; wire sig_inhibit_rdy_n_0; - wire sig_inhibit_rdy_n_i_1__1_n_0; + wire sig_inhibit_rdy_n_i_1_n_0; wire sig_init_done; + wire sig_init_done_i_1_n_0; + wire sig_init_reg; + wire sig_init_reg2; wire sig_last_dbeat; wire sig_last_dbeat_reg; - wire sig_ld_new_cmd_reg; - wire sig_ld_new_cmd_reg_reg; - wire sig_mmap_reset_reg_reg; wire sig_mstr2data_cmd_valid; - wire sig_next_calc_error_reg; + wire sig_next_calc_error_reg_reg; wire sig_next_cmd_cmplt_reg_reg; wire sig_next_sequential_reg; wire sig_push_dqual_reg; @@ -1531,6 +2711,7 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized2 Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized2 \USE_SRL_FIFO.I_SYNC_FIFO (.D(D), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ), .E(E), .FIFO_Full_reg(FIFO_Full_reg), .Q(Q), @@ -1541,21844 +2722,59530 @@ module Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized2 .m_axi_mm2s_rvalid(m_axi_mm2s_rvalid), .out(out), .ram_full_i_reg(ram_full_i_reg), - .sig_addr_posted_cntr(sig_addr_posted_cntr), - .sig_advance_pipe9_out__1(sig_advance_pipe9_out__1), + .\sig_addr_posted_cntr_reg[0] (\sig_addr_posted_cntr_reg[0] ), + .\sig_addr_posted_cntr_reg[1] (\sig_addr_posted_cntr_reg[1] ), + .\sig_addr_posted_cntr_reg[2] (\sig_addr_posted_cntr_reg[2] ), .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .sig_dbeat_cntr_eq_1(sig_dbeat_cntr_eq_1), - .\sig_dbeat_cntr_reg[2] (\sig_dbeat_cntr_reg[2] ), + .sig_data2rsc_valid(sig_data2rsc_valid), + .\sig_dbeat_cntr_reg[0] (\sig_dbeat_cntr_reg[0] ), .\sig_dbeat_cntr_reg[3] (\sig_dbeat_cntr_reg[3] ), - .\sig_dbeat_cntr_reg[4] (\sig_dbeat_cntr_reg[4] ), + .\sig_dbeat_cntr_reg[5] (\sig_dbeat_cntr_reg[5] ), .sig_dqual_reg_empty(sig_dqual_reg_empty), .sig_dqual_reg_empty_reg(sig_push_dqual_reg), - .sig_dqual_reg_empty_reg_0(sig_good_mmap_dbeat7_out__0), + .sig_dqual_reg_empty_reg_0(sig_dqual_reg_empty_reg), .sig_dqual_reg_full(sig_dqual_reg_full), .sig_halt_reg_reg(sig_halt_reg_reg), .sig_inhibit_rdy_n(sig_inhibit_rdy_n), .sig_inhibit_rdy_n_0(sig_inhibit_rdy_n_0), .sig_last_dbeat(sig_last_dbeat), .sig_last_dbeat_reg(sig_last_dbeat_reg), - .sig_ld_new_cmd_reg(sig_ld_new_cmd_reg), - .sig_ld_new_cmd_reg_reg(sig_ld_new_cmd_reg_reg), .sig_mstr2data_cmd_valid(sig_mstr2data_cmd_valid), - .sig_next_calc_error_reg(sig_next_calc_error_reg), .sig_next_calc_error_reg_reg(sel), + .sig_next_calc_error_reg_reg_0(sig_next_calc_error_reg_reg), .sig_next_cmd_cmplt_reg_reg(sig_next_cmd_cmplt_reg_reg), .sig_next_sequential_reg(sig_next_sequential_reg), .sig_rsc2stat_status_valid(sig_rsc2stat_status_valid)); LUT2 #( .INIT(4'hE)) - sig_inhibit_rdy_n_i_1__1 + sig_inhibit_rdy_n_i_1 (.I0(sig_init_done), .I1(sig_inhibit_rdy_n_0), - .O(sig_inhibit_rdy_n_i_1__1_n_0)); + .O(sig_inhibit_rdy_n_i_1_n_0)); FDRE #( .INIT(1'b0)) sig_inhibit_rdy_n_reg (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(sig_inhibit_rdy_n_i_1__1_n_0), + .D(sig_inhibit_rdy_n_i_1_n_0), .Q(sig_inhibit_rdy_n_0), .R(SR)); + LUT4 #( + .INIT(16'h0080)) + sig_init_done_i_1 + (.I0(sig_init_reg2), + .I1(sig_init_reg), + .I2(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I3(sig_init_done), + .O(sig_init_done_i_1_n_0)); FDRE #( .INIT(1'b0)) sig_init_done_reg (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(sig_mmap_reset_reg_reg), + .D(sig_init_done_i_1_n_0), .Q(sig_init_done), .R(1'b0)); endmodule (* ORIG_REF_NAME = "axi_datamover_fifo" *) module Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized3 - (p_0_out, - FIFO_Full_reg, + (FIFO_Full_reg, \INFERRED_GEN.cnt_i_reg[1] , - sig_init_done, - \INFERRED_GEN.cnt_i_reg[1]_0 , + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , Q, + \INFERRED_GEN.cnt_i_reg[1]_0 , in, m_axi_mm2s_aclk, - sig_stream_rst, - sig_mmap_reset_reg_reg, - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram , - sig_mstr2sf_cmd_valid); - output [0:0]p_0_out; + SR, + lsig_cmd_loaded, + prmry_resetn_i_reg, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 , + DOBDO, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg , + sig_mstr2sf_cmd_valid, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1 , + sig_init_reg2, + sig_init_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg); output FIFO_Full_reg; output \INFERRED_GEN.cnt_i_reg[1] ; - output sig_init_done; - output \INFERRED_GEN.cnt_i_reg[1]_0 ; + output \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; output [0:0]Q; + output \INFERRED_GEN.cnt_i_reg[1]_0 ; input [0:0]in; input m_axi_mm2s_aclk; - input sig_stream_rst; - input sig_mmap_reset_reg_reg; - input \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; + input [0:0]SR; + input lsig_cmd_loaded; + input prmry_resetn_i_reg; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; + input [0:0]DOBDO; + input \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; input sig_mstr2sf_cmd_valid; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1 ; + input sig_init_reg2; + input sig_init_reg; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; + wire [0:0]DOBDO; wire FIFO_Full_reg; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1 ; + wire \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; wire \INFERRED_GEN.cnt_i_reg[1] ; wire \INFERRED_GEN.cnt_i_reg[1]_0 ; wire [0:0]Q; + wire [0:0]SR; wire [0:0]in; + wire lsig_cmd_loaded; wire m_axi_mm2s_aclk; - wire [0:0]p_0_out; - wire sig_inhibit_rdy_n_i_1__2_n_0; + wire prmry_resetn_i_reg; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_inhibit_rdy_n_i_1_n_0; wire sig_init_done; - wire sig_mmap_reset_reg_reg; + wire sig_init_done_i_1_n_0; + wire sig_init_reg; + wire sig_init_reg2; wire sig_mstr2sf_cmd_valid; - wire sig_stream_rst; Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized3 \USE_SRL_FIFO.I_SYNC_FIFO - (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ), + (.DOBDO(DOBDO), .FIFO_Full_reg(FIFO_Full_reg), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1 (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1 ), + .\INCLUDE_UNPACKING.lsig_cmd_loaded_reg (\INCLUDE_UNPACKING.lsig_cmd_loaded_reg ), .\INFERRED_GEN.cnt_i_reg[1] (\INFERRED_GEN.cnt_i_reg[1] ), .Q(Q), + .SR(SR), .in(in), + .lsig_cmd_loaded(lsig_cmd_loaded), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .p_0_out(p_0_out), + .prmry_resetn_i_reg(prmry_resetn_i_reg), .sig_inhibit_rdy_n_reg(\INFERRED_GEN.cnt_i_reg[1]_0 ), - .sig_mstr2sf_cmd_valid(sig_mstr2sf_cmd_valid), - .sig_stream_rst(sig_stream_rst)); + .sig_mstr2sf_cmd_valid(sig_mstr2sf_cmd_valid)); LUT2 #( .INIT(4'hE)) - sig_inhibit_rdy_n_i_1__2 + sig_inhibit_rdy_n_i_1 (.I0(sig_init_done), .I1(\INFERRED_GEN.cnt_i_reg[1]_0 ), - .O(sig_inhibit_rdy_n_i_1__2_n_0)); + .O(sig_inhibit_rdy_n_i_1_n_0)); FDRE #( .INIT(1'b0)) sig_inhibit_rdy_n_reg (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(sig_inhibit_rdy_n_i_1__2_n_0), + .D(sig_inhibit_rdy_n_i_1_n_0), .Q(\INFERRED_GEN.cnt_i_reg[1]_0 ), - .R(sig_stream_rst)); + .R(SR)); + LUT4 #( + .INIT(16'h0080)) + sig_init_done_i_1 + (.I0(sig_init_reg2), + .I1(sig_init_reg), + .I2(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I3(sig_init_done), + .O(sig_init_done_i_1_n_0)); FDRE #( .INIT(1'b0)) sig_init_done_reg (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(sig_mmap_reset_reg_reg), + .D(sig_init_done_i_1_n_0), .Q(sig_init_done), .R(1'b0)); endmodule -(* ORIG_REF_NAME = "axi_datamover_mm2s_full_wrap" *) -module Arty_Z7_20_axi_vdma_0_0_axi_datamover_mm2s_full_wrap - (m_axi_mm2s_arburst, - m_axi_mm2s_arvalid, - mm2s_halt_cmplt, - sig_rst2all_stop_request, - \sig_user_skid_reg_reg[0] , - dm2linebuf_mm2s_tvalid, - DI, +(* ORIG_REF_NAME = "axi_datamover_fifo" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized4 + (sig_init_done_0, + p_9_out, Q, - E, - FIFO_Full_reg, - m_axi_mm2s_rready, - dm2linebuf_mm2s_tdata, - S, - interr_i_reg, - slverr_i_reg, + CO, + \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg , decerr_i_reg, - \count_reg[6] , - m_axi_mm2s_araddr, - m_axi_mm2s_arlen, - m_axi_mm2s_arsize, - m_axi_mm2s_aclk, - m_axi_mm2s_rdata, - out, - halt_i_reg, - p_55_out, - m_axi_mm2s_rlast, - m_axi_mm2s_rvalid, - m_axi_mm2s_rresp, - cmnd_wr, - mm2s_halt, - p_57_out, - sts_tready_reg, - p_8_out, - fifo_wren__0, - m_axi_mm2s_arready, - in, - D); - output [0:0]m_axi_mm2s_arburst; - output m_axi_mm2s_arvalid; - output mm2s_halt_cmplt; - output sig_rst2all_stop_request; - output [0:0]\sig_user_skid_reg_reg[0] ; - output dm2linebuf_mm2s_tvalid; - output [3:0]DI; - output [1:0]Q; - output [0:0]E; - output [0:0]FIFO_Full_reg; - output m_axi_mm2s_rready; - output [31:0]dm2linebuf_mm2s_tdata; - output [3:0]S; - output interr_i_reg; - output slverr_i_reg; + slverr_i_reg, + interr_i_reg, + sig_dqual_reg_empty_reg, + \GEN_STS_GRTR_THAN_8.ovrflo_err_reg , + sig_stream_rst, + m_axi_s2mm_aclk, + sig_init_reg_reg, + s2mm_halt, + s2mm_soft_reset, + dma_err, + \hsize_vid_reg[15] , + \hsize_vid_reg[2] , + S, + sig_wsc2stat_status_valid, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + m_axis_s2mm_sts_tready, + in); + output sig_init_done_0; + output p_9_out; + output [0:0]Q; + output [0:0]CO; + output \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ; output decerr_i_reg; - output [1:0]\count_reg[6] ; - output [31:0]m_axi_mm2s_araddr; - output [3:0]m_axi_mm2s_arlen; - output [1:0]m_axi_mm2s_arsize; - input m_axi_mm2s_aclk; - input [63:0]m_axi_mm2s_rdata; - input out; - input halt_i_reg; - input p_55_out; - input m_axi_mm2s_rlast; - input m_axi_mm2s_rvalid; - input [1:0]m_axi_mm2s_rresp; - input cmnd_wr; - input mm2s_halt; - input p_57_out; - input sts_tready_reg; - input p_8_out; - input fifo_wren__0; - input m_axi_mm2s_arready; - input [48:0]in; - input [5:0]D; + output slverr_i_reg; + output interr_i_reg; + output sig_dqual_reg_empty_reg; + output [0:0]\GEN_STS_GRTR_THAN_8.ovrflo_err_reg ; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input sig_init_reg_reg; + input s2mm_halt; + input s2mm_soft_reset; + input dma_err; + input [12:0]\hsize_vid_reg[15] ; + input [0:0]\hsize_vid_reg[2] ; + input [0:0]S; + input sig_wsc2stat_status_valid; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input m_axis_s2mm_sts_tready; + input [16:0]in; - wire [5:0]D; - wire [3:0]DI; - wire [0:0]E; - wire [0:0]FIFO_Full_reg; - wire \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/sig_wr_fifo ; - wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_init_done ; - wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_wr_fifo ; - wire \GEN_INCLUDE_MM2S_SF.I_RD_SF_n_2 ; - wire \GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_inhibit_rdy_n ; - wire \GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_init_done ; - wire I_ADDR_CNTL_n_0; - wire \I_CMD_FIFO/sig_init_done ; - wire \I_CMD_FIFO/sig_rd_empty ; - wire I_CMD_STATUS_n_0; - wire I_CMD_STATUS_n_57; - wire I_CMD_STATUS_n_58; - wire I_MSTR_PCC_n_3; - wire I_MSTR_PCC_n_4; - wire I_MSTR_PCC_n_48; - wire I_MSTR_PCC_n_49; - wire I_MSTR_PCC_n_5; - wire I_MSTR_PCC_n_50; - wire I_MSTR_PCC_n_51; - wire I_MSTR_PCC_n_52; - wire I_MSTR_PCC_n_6; - wire I_RD_DATA_CNTL_n_0; - wire I_RD_DATA_CNTL_n_15; - wire I_RD_DATA_CNTL_n_5; - wire I_RESET_n_4; - wire \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_inhibit_rdy_n ; - wire \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_done ; - wire \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg ; - wire \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg2 ; - wire \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_wr_fifo ; - wire [1:0]Q; - wire [3:0]S; - wire cmnd_wr; - wire [1:0]\count_reg[6] ; + wire [0:0]CO; + wire \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ; + wire [0:0]\GEN_STS_GRTR_THAN_8.ovrflo_err_reg ; + wire [0:0]Q; + wire [0:0]S; wire decerr_i_reg; - wire [31:0]dm2linebuf_mm2s_tdata; - wire dm2linebuf_mm2s_tvalid; - wire fifo_wren__0; - wire halt_i_reg; - wire [48:0]in; + wire dma_err; + wire [12:0]\hsize_vid_reg[15] ; + wire [0:0]\hsize_vid_reg[2] ; + wire [16:0]in; wire interr_i_reg; - wire m_axi_mm2s_aclk; - wire [31:0]m_axi_mm2s_araddr; - wire [0:0]m_axi_mm2s_arburst; - wire [3:0]m_axi_mm2s_arlen; - wire m_axi_mm2s_arready; - wire [1:0]m_axi_mm2s_arsize; - wire m_axi_mm2s_arvalid; - wire [63:0]m_axi_mm2s_rdata; - wire m_axi_mm2s_rlast; - wire m_axi_mm2s_rready; - wire [1:0]m_axi_mm2s_rresp; - wire m_axi_mm2s_rvalid; - wire mm2s_halt; - wire mm2s_halt_cmplt; - wire mm2s_strm_wvalid0__1; - wire out; - wire p_55_out; - wire p_57_out; - wire p_8_out; - wire sig_addr2data_addr_posted; - wire sig_addr2rsc_calc_error; - wire sig_addr_reg_empty; - wire sig_advance_pipe9_out__1; - wire sig_calc_error_pushed; - wire sig_calc_error_reg; - wire [63:0]sig_cmd2mstr_command; + wire m_axi_s2mm_aclk; + wire m_axis_s2mm_sts_tready; + wire p_9_out; + wire s2mm_halt; + wire s2mm_soft_reset; wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - wire sig_data2addr_stop_req; - wire sig_data2rsc_calc_err; - wire sig_data2rsc_slverr; - wire sig_data2sf_cmd_cmplt; - wire [7:7]sig_data_fifo_wr_cnt; - wire sig_input_reg_empty; - wire [31:3]sig_mstr2addr_addr; - wire [0:0]sig_mstr2addr_burst; - wire sig_mstr2addr_cmd_valid; - wire sig_mstr2data_cmd_cmplt; - wire sig_mstr2data_cmd_valid; - wire sig_mstr2data_eof; - wire sig_mstr2data_sequential; - wire sig_mstr2sf_cmd_valid; - wire sig_push_rd_sts_reg; - wire sig_rd_sts_decerr_reg0; - wire sig_rd_sts_reg_full0; - wire sig_rdc2sf_wlast; - wire sig_rsc2data_ready; - wire [6:4]sig_rsc2stat_status; - wire sig_rsc2stat_status_valid; - wire sig_rst2all_stop_request; - wire sig_sf_allow_addr_req; - wire sig_sm_halt_reg; + wire sig_dqual_reg_empty_reg; + wire sig_inhibit_rdy_n; + wire sig_inhibit_rdy_n_i_1_n_0; + wire sig_init_done_0; + wire sig_init_reg_reg; wire sig_stream_rst; - wire [0:0]\sig_user_skid_reg_reg[0] ; - wire [2:0]sig_xfer_addr_reg; + wire sig_wsc2stat_status_valid; wire slverr_i_reg; - wire sts_tready_reg; - Arty_Z7_20_axi_vdma_0_0_axi_datamover_rd_sf \GEN_INCLUDE_MM2S_SF.I_RD_SF - (.D(D), - .DI(DI), - .DIBDI({sig_data2sf_cmd_cmplt,sig_rdc2sf_wlast}), - .\INFERRED_GEN.cnt_i_reg[1] (\GEN_INCLUDE_MM2S_SF.I_RD_SF_n_2 ), + Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized4 \USE_SRL_FIFO.I_SYNC_FIFO + (.CO(CO), + .\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg (\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ), + .\GEN_STS_GRTR_THAN_8.ovrflo_err_reg (\GEN_STS_GRTR_THAN_8.ovrflo_err_reg ), .Q(Q), .S(S), - .\count_reg[6] (\count_reg[6] ), - .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), - .dm2linebuf_mm2s_tvalid(dm2linebuf_mm2s_tvalid), - .fifo_wren__0(fifo_wren__0), - .in(sig_xfer_addr_reg[2]), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axi_mm2s_rdata(m_axi_mm2s_rdata), - .m_axi_mm2s_rvalid(m_axi_mm2s_rvalid), - .mm2s_strm_wvalid0__1(mm2s_strm_wvalid0__1), - .out(sig_data_fifo_wr_cnt), - .p_8_out(p_8_out), - .sig_advance_pipe9_out__1(sig_advance_pipe9_out__1), - .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .sig_inhibit_rdy_n(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_inhibit_rdy_n ), - .sig_init_done(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_done ), - .sig_last_mmap_dbeat_reg_reg(I_RD_DATA_CNTL_n_0), - .sig_mmap_reset_reg_reg(I_MSTR_PCC_n_51), - .sig_mstr2sf_cmd_valid(sig_mstr2sf_cmd_valid), - .sig_posted_to_axi_2_reg(I_ADDR_CNTL_n_0), - .sig_sf_allow_addr_req(sig_sf_allow_addr_req), - .sig_stream_rst(sig_stream_rst), - .\sig_user_skid_reg_reg[0] (\sig_user_skid_reg_reg[0] ), - .sig_wr_fifo(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_wr_fifo )); - Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl I_ADDR_CNTL - (.SR(sig_stream_rst), - .in({sig_calc_error_reg,sig_mstr2addr_burst,I_MSTR_PCC_n_3,I_MSTR_PCC_n_4,I_MSTR_PCC_n_5,I_MSTR_PCC_n_6,sig_mstr2addr_addr,sig_xfer_addr_reg}), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axi_mm2s_araddr(m_axi_mm2s_araddr), - .m_axi_mm2s_arburst(m_axi_mm2s_arburst), - .m_axi_mm2s_arlen(m_axi_mm2s_arlen), - .m_axi_mm2s_arready(m_axi_mm2s_arready), - .m_axi_mm2s_arsize(m_axi_mm2s_arsize), - .m_axi_mm2s_arvalid(m_axi_mm2s_arvalid), - .out(I_ADDR_CNTL_n_0), - .sig_addr2rsc_calc_error(sig_addr2rsc_calc_error), - .\sig_addr_posted_cntr_reg[2] (sig_addr2data_addr_posted), - .sig_addr_reg_empty(sig_addr_reg_empty), - .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .sig_data2addr_stop_req(sig_data2addr_stop_req), - .sig_init_reg(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg ), - .sig_init_reg2(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg2 ), - .sig_mstr2addr_cmd_valid(sig_mstr2addr_cmd_valid), - .sig_sf_allow_addr_req(sig_sf_allow_addr_req), - .sig_wr_fifo(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/sig_wr_fifo )); - Arty_Z7_20_axi_vdma_0_0_axi_datamover_cmd_status I_CMD_STATUS - (.E(E), - .FIFO_Full_reg(FIFO_Full_reg), - .\INFERRED_GEN.cnt_i_reg[1] (I_CMD_STATUS_n_0), - .Q(\I_CMD_FIFO/sig_rd_empty ), - .SR(sig_stream_rst), - .cmnd_wr(cmnd_wr), .decerr_i_reg(decerr_i_reg), - .in(sig_calc_error_reg), + .dma_err(dma_err), + .\hsize_vid_reg[15] (\hsize_vid_reg[15] ), + .\hsize_vid_reg[2] (\hsize_vid_reg[2] ), + .in(in), .interr_i_reg(interr_i_reg), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .mm2s_halt(mm2s_halt), - .out({sig_cmd2mstr_command[63:32],sig_cmd2mstr_command[30],sig_cmd2mstr_command[23],sig_cmd2mstr_command[15:0]}), - .p_55_out(p_55_out), - .p_57_out(p_57_out), - .\s_axis_cmd_tdata_reg[63] (in), - .sig_calc_error_pushed(sig_calc_error_pushed), - .sig_calc_error_pushed_reg(I_MSTR_PCC_n_52), - .sig_calc_error_reg_reg(I_CMD_STATUS_n_57), - .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .sig_inhibit_rdy_n(\GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_inhibit_rdy_n ), - .sig_init_done(\I_CMD_FIFO/sig_init_done ), - .sig_init_done_0(\GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_init_done ), - .sig_input_reg_empty(sig_input_reg_empty), - .sig_mmap_reset_reg_reg(I_MSTR_PCC_n_48), - .sig_mmap_reset_reg_reg_0(I_MSTR_PCC_n_49), - .sig_rd_sts_slverr_reg_reg(I_CMD_STATUS_n_58), - .sig_rd_sts_slverr_reg_reg_0(sig_rsc2stat_status), - .sig_rsc2stat_status_valid(sig_rsc2stat_status_valid), - .sig_sm_halt_reg(sig_sm_halt_reg), - .slverr_i_reg(slverr_i_reg), - .sts_tready_reg(sts_tready_reg)); - Arty_Z7_20_axi_vdma_0_0_axi_datamover_pcc I_MSTR_PCC - (.FIFO_Full_reg(I_MSTR_PCC_n_52), - .FIFO_Full_reg_0(\GEN_INCLUDE_MM2S_SF.I_RD_SF_n_2 ), - .\INFERRED_GEN.cnt_i_reg[2] (I_CMD_STATUS_n_57), - .Q(\I_CMD_FIFO/sig_rd_empty ), - .SR(sig_stream_rst), - .in({sig_calc_error_reg,sig_mstr2addr_burst,I_MSTR_PCC_n_3,I_MSTR_PCC_n_4,I_MSTR_PCC_n_5,I_MSTR_PCC_n_6,sig_mstr2addr_addr,sig_xfer_addr_reg}), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .out({sig_cmd2mstr_command[63:32],sig_cmd2mstr_command[30],sig_cmd2mstr_command[23],sig_cmd2mstr_command[15:0]}), - .sig_calc_error_pushed(sig_calc_error_pushed), - .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .sig_inhibit_rdy_n(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_inhibit_rdy_n ), - .sig_init_done(\I_CMD_FIFO/sig_init_done ), - .sig_init_done_2(\GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_init_done ), - .sig_init_done_3(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_init_done ), - .sig_init_done_4(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_done ), - .sig_init_done_reg(I_MSTR_PCC_n_48), - .sig_init_done_reg_0(I_MSTR_PCC_n_49), - .sig_init_done_reg_1(I_MSTR_PCC_n_50), - .sig_init_done_reg_2(I_MSTR_PCC_n_51), - .sig_init_reg(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg ), - .sig_init_reg2(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg2 ), - .sig_input_reg_empty(sig_input_reg_empty), - .sig_mstr2addr_cmd_valid(sig_mstr2addr_cmd_valid), - .sig_mstr2data_cmd_valid(sig_mstr2data_cmd_valid), - .sig_mstr2sf_cmd_valid(sig_mstr2sf_cmd_valid), - .sig_next_cmd_cmplt_reg_reg({sig_mstr2data_cmd_cmplt,sig_mstr2data_sequential,sig_mstr2data_eof}), - .sig_sm_halt_reg(sig_sm_halt_reg), - .sig_wr_fifo(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_wr_fifo ), - .sig_wr_fifo_0(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/sig_wr_fifo ), - .sig_wr_fifo_1(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_wr_fifo )); - Arty_Z7_20_axi_vdma_0_0_axi_datamover_rddata_cntl I_RD_DATA_CNTL - (.DIBDI({sig_data2sf_cmd_cmplt,sig_rdc2sf_wlast}), - .FIFO_Full_reg(I_CMD_STATUS_n_0), - .SR(sig_stream_rst), - .in({sig_calc_error_reg,sig_mstr2data_cmd_cmplt,sig_mstr2data_sequential,sig_mstr2data_eof,I_MSTR_PCC_n_3,I_MSTR_PCC_n_4,I_MSTR_PCC_n_5,I_MSTR_PCC_n_6}), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axi_mm2s_rlast(m_axi_mm2s_rlast), - .m_axi_mm2s_rready(m_axi_mm2s_rready), - .m_axi_mm2s_rresp(m_axi_mm2s_rresp), - .m_axi_mm2s_rvalid(m_axi_mm2s_rvalid), - .mm2s_halt_cmplt(mm2s_halt_cmplt), - .mm2s_strm_wvalid0__1(mm2s_strm_wvalid0__1), - .out(sig_data_fifo_wr_cnt), - .sig_addr2rsc_calc_error(sig_addr2rsc_calc_error), - .\sig_addr_posted_cntr_reg[2]_0 (I_RD_DATA_CNTL_n_0), - .sig_addr_reg_empty(sig_addr_reg_empty), - .sig_advance_pipe9_out__1(sig_advance_pipe9_out__1), - .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .sig_data2addr_stop_req(sig_data2addr_stop_req), - .sig_data2rsc_calc_err(sig_data2rsc_calc_err), - .sig_data2rsc_slverr(sig_data2rsc_slverr), - .sig_halt_cmplt_reg(I_RD_DATA_CNTL_n_15), - .sig_inhibit_rdy_n(\GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_inhibit_rdy_n ), - .sig_init_done(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_init_done ), - .sig_mmap_reset_reg_reg(I_MSTR_PCC_n_50), - .sig_mstr2data_cmd_valid(sig_mstr2data_cmd_valid), - .sig_posted_to_axi_reg(sig_addr2data_addr_posted), - .sig_push_rd_sts_reg(sig_push_rd_sts_reg), - .sig_rd_sts_decerr_reg0(sig_rd_sts_decerr_reg0), - .sig_rd_sts_decerr_reg_reg(sig_rsc2stat_status[5]), - .sig_rd_sts_reg_empty_reg(I_RD_DATA_CNTL_n_5), - .sig_rd_sts_reg_full0(sig_rd_sts_reg_full0), - .sig_rsc2data_ready(sig_rsc2data_ready), - .sig_rsc2stat_status_valid(sig_rsc2stat_status_valid), - .sig_s_h_halt_reg_reg(I_RESET_n_4), - .sig_wr_fifo(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_wr_fifo )); - Arty_Z7_20_axi_vdma_0_0_axi_datamover_rd_status_cntl I_RD_STATUS_CNTLR - (.m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .sig_coelsc_reg_full_reg(I_RD_DATA_CNTL_n_5), - .sig_data2rsc_calc_err(sig_data2rsc_calc_err), - .sig_data2rsc_slverr(sig_data2rsc_slverr), - .sig_inhibit_rdy_n_reg(I_CMD_STATUS_n_58), - .sig_push_rd_sts_reg(sig_push_rd_sts_reg), - .sig_rd_sts_decerr_reg0(sig_rd_sts_decerr_reg0), - .sig_rd_sts_reg_full0(sig_rd_sts_reg_full0), - .sig_rd_sts_slverr_reg_reg_0(sig_rsc2stat_status), - .sig_rsc2data_ready(sig_rsc2data_ready), - .sig_rsc2stat_status_valid(sig_rsc2stat_status_valid)); - Arty_Z7_20_axi_vdma_0_0_axi_datamover_reset I_RESET - (.SR(sig_stream_rst), - .halt_i_reg(halt_i_reg), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .mm2s_halt_cmplt(mm2s_halt_cmplt), - .out(out), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .m_axis_s2mm_sts_tready(m_axis_s2mm_sts_tready), + .p_9_out(p_9_out), + .s2mm_halt(s2mm_halt), + .s2mm_soft_reset(s2mm_soft_reset), .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .sig_data2addr_stop_req(sig_data2addr_stop_req), - .sig_halt_reg_reg(I_RESET_n_4), - .sig_halt_reg_reg_0(I_RD_DATA_CNTL_n_15), - .sig_rst2all_stop_request(sig_rst2all_stop_request)); + .sig_dqual_reg_empty_reg(sig_dqual_reg_empty_reg), + .sig_inhibit_rdy_n(sig_inhibit_rdy_n), + .sig_stream_rst(sig_stream_rst), + .sig_wsc2stat_status_valid(sig_wsc2stat_status_valid), + .slverr_i_reg(slverr_i_reg)); + LUT2 #( + .INIT(4'hE)) + sig_inhibit_rdy_n_i_1 + (.I0(sig_init_done_0), + .I1(sig_inhibit_rdy_n), + .O(sig_inhibit_rdy_n_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + sig_inhibit_rdy_n_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_inhibit_rdy_n_i_1_n_0), + .Q(sig_inhibit_rdy_n), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + sig_init_done_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_init_reg_reg), + .Q(sig_init_done_0), + .R(1'b0)); endmodule -(* ORIG_REF_NAME = "axi_datamover_pcc" *) -module Arty_Z7_20_axi_vdma_0_0_axi_datamover_pcc - (sig_init_reg, - in, - sig_sm_halt_reg, - sig_input_reg_empty, - sig_mstr2sf_cmd_valid, - sig_mstr2data_cmd_valid, - sig_mstr2addr_cmd_valid, - sig_calc_error_pushed, - sig_next_cmd_cmplt_reg_reg, - sig_init_done_reg, +(* ORIG_REF_NAME = "axi_datamover_fifo" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized5 + (sig_init_reg2_reg, + \GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg , + \GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg , + D, + \INFERRED_GEN.cnt_i_reg[2] , + E, + m_axi_s2mm_bready, + sig_input_cache_type_reg0, + SR, sig_init_done_reg_0, sig_init_done_reg_1, sig_init_done_reg_2, - FIFO_Full_reg, - SR, - m_axi_mm2s_aclk, + sig_init_done_reg_3, + sig_stream_rst, + m_axi_s2mm_aclk, + in, out, - \INFERRED_GEN.cnt_i_reg[2] , + sig_posted_to_axi_reg, Q, - sig_wr_fifo, - sig_wr_fifo_0, - sig_wr_fifo_1, - FIFO_Full_reg_0, - sig_inhibit_rdy_n, + sig_push_coelsc_reg, + m_axi_s2mm_bvalid, + \INFERRED_GEN.cnt_i_reg[3] , + sig_halt_reg, + sig_psm_pop_input_cmd, + sig_csm_pop_child_cmd, sig_init_reg2, sig_cmd_stat_rst_user_reg_n_cdc_from_reg, sig_init_done, + sig_init_done_0, + sig_init_done_1, sig_init_done_2, - sig_init_done_3, - sig_init_done_4); - output sig_init_reg; - output [37:0]in; - output sig_sm_halt_reg; - output sig_input_reg_empty; - output sig_mstr2sf_cmd_valid; - output sig_mstr2data_cmd_valid; - output sig_mstr2addr_cmd_valid; - output sig_calc_error_pushed; - output [2:0]sig_next_cmd_cmplt_reg_reg; - output sig_init_done_reg; + m_axi_s2mm_bresp); + output sig_init_reg2_reg; + output \GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg ; + output \GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg ; + output [2:0]D; + output [0:0]\INFERRED_GEN.cnt_i_reg[2] ; + output [0:0]E; + output m_axi_s2mm_bready; + output sig_input_cache_type_reg0; + output [0:0]SR; output sig_init_done_reg_0; output sig_init_done_reg_1; output sig_init_done_reg_2; - output FIFO_Full_reg; - input [0:0]SR; - input m_axi_mm2s_aclk; - input [49:0]out; - input \INFERRED_GEN.cnt_i_reg[2] ; - input [0:0]Q; - input sig_wr_fifo; - input sig_wr_fifo_0; - input sig_wr_fifo_1; - input FIFO_Full_reg_0; - input sig_inhibit_rdy_n; + output sig_init_done_reg_3; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input [1:0]in; + input [0:0]out; + input sig_posted_to_axi_reg; + input [3:0]Q; + input sig_push_coelsc_reg; + input m_axi_s2mm_bvalid; + input \INFERRED_GEN.cnt_i_reg[3] ; + input sig_halt_reg; + input sig_psm_pop_input_cmd; + input sig_csm_pop_child_cmd; input sig_init_reg2; input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; input sig_init_done; + input sig_init_done_0; + input sig_init_done_1; input sig_init_done_2; - input sig_init_done_3; - input sig_init_done_4; + input [1:0]m_axi_s2mm_bresp; - wire FIFO_Full_reg; - wire FIFO_Full_reg_0; - wire \FSM_sequential_sig_pcc_sm_state[0]_i_1_n_0 ; - wire \FSM_sequential_sig_pcc_sm_state[0]_i_2_n_0 ; - wire \FSM_sequential_sig_pcc_sm_state[1]_i_1_n_0 ; - wire \FSM_sequential_sig_pcc_sm_state[1]_i_2_n_0 ; - wire \FSM_sequential_sig_pcc_sm_state[2]_i_1_n_0 ; - wire \INFERRED_GEN.cnt_i_reg[2] ; - wire [0:0]Q; + wire [2:0]D; + wire [0:0]E; + wire \GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg ; + wire \GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg ; + wire [0:0]\INFERRED_GEN.cnt_i_reg[2] ; + wire \INFERRED_GEN.cnt_i_reg[3] ; + wire [3:0]Q; wire [0:0]SR; - wire [37:0]in; - wire m_axi_mm2s_aclk; - wire [49:0]out; - wire [15:0]p_1_in; - wire p_1_in_0; - wire [8:0]sel0; - wire sig_addr_aligned_im0; - wire sig_addr_aligned_ireg1; - wire \sig_addr_cntr_im0_msh[0]_i_1_n_0 ; - wire \sig_addr_cntr_im0_msh[0]_i_3_n_0 ; - wire \sig_addr_cntr_im0_msh[0]_i_4_n_0 ; - wire \sig_addr_cntr_im0_msh[0]_i_5_n_0 ; - wire \sig_addr_cntr_im0_msh[0]_i_6_n_0 ; - wire \sig_addr_cntr_im0_msh[0]_i_7_n_0 ; - wire \sig_addr_cntr_im0_msh[12]_i_2_n_0 ; - wire \sig_addr_cntr_im0_msh[12]_i_3_n_0 ; - wire \sig_addr_cntr_im0_msh[12]_i_4_n_0 ; - wire \sig_addr_cntr_im0_msh[12]_i_5_n_0 ; - wire \sig_addr_cntr_im0_msh[4]_i_2_n_0 ; - wire \sig_addr_cntr_im0_msh[4]_i_3_n_0 ; - wire \sig_addr_cntr_im0_msh[4]_i_4_n_0 ; - wire \sig_addr_cntr_im0_msh[4]_i_5_n_0 ; - wire \sig_addr_cntr_im0_msh[8]_i_2_n_0 ; - wire \sig_addr_cntr_im0_msh[8]_i_3_n_0 ; - wire \sig_addr_cntr_im0_msh[8]_i_4_n_0 ; - wire \sig_addr_cntr_im0_msh[8]_i_5_n_0 ; - wire [15:0]sig_addr_cntr_im0_msh_reg; - wire \sig_addr_cntr_im0_msh_reg[0]_i_2_n_0 ; - wire \sig_addr_cntr_im0_msh_reg[0]_i_2_n_1 ; - wire \sig_addr_cntr_im0_msh_reg[0]_i_2_n_2 ; - wire \sig_addr_cntr_im0_msh_reg[0]_i_2_n_3 ; - wire \sig_addr_cntr_im0_msh_reg[0]_i_2_n_4 ; - wire \sig_addr_cntr_im0_msh_reg[0]_i_2_n_5 ; - wire \sig_addr_cntr_im0_msh_reg[0]_i_2_n_6 ; - wire \sig_addr_cntr_im0_msh_reg[0]_i_2_n_7 ; - wire \sig_addr_cntr_im0_msh_reg[12]_i_1_n_1 ; - wire \sig_addr_cntr_im0_msh_reg[12]_i_1_n_2 ; - wire \sig_addr_cntr_im0_msh_reg[12]_i_1_n_3 ; - wire \sig_addr_cntr_im0_msh_reg[12]_i_1_n_4 ; - wire \sig_addr_cntr_im0_msh_reg[12]_i_1_n_5 ; - wire \sig_addr_cntr_im0_msh_reg[12]_i_1_n_6 ; - wire \sig_addr_cntr_im0_msh_reg[12]_i_1_n_7 ; - wire \sig_addr_cntr_im0_msh_reg[4]_i_1_n_0 ; - wire \sig_addr_cntr_im0_msh_reg[4]_i_1_n_1 ; - wire \sig_addr_cntr_im0_msh_reg[4]_i_1_n_2 ; - wire \sig_addr_cntr_im0_msh_reg[4]_i_1_n_3 ; - wire \sig_addr_cntr_im0_msh_reg[4]_i_1_n_4 ; - wire \sig_addr_cntr_im0_msh_reg[4]_i_1_n_5 ; - wire \sig_addr_cntr_im0_msh_reg[4]_i_1_n_6 ; - wire \sig_addr_cntr_im0_msh_reg[4]_i_1_n_7 ; - wire \sig_addr_cntr_im0_msh_reg[8]_i_1_n_0 ; - wire \sig_addr_cntr_im0_msh_reg[8]_i_1_n_1 ; - wire \sig_addr_cntr_im0_msh_reg[8]_i_1_n_2 ; - wire \sig_addr_cntr_im0_msh_reg[8]_i_1_n_3 ; - wire \sig_addr_cntr_im0_msh_reg[8]_i_1_n_4 ; - wire \sig_addr_cntr_im0_msh_reg[8]_i_1_n_5 ; - wire \sig_addr_cntr_im0_msh_reg[8]_i_1_n_6 ; - wire \sig_addr_cntr_im0_msh_reg[8]_i_1_n_7 ; - wire [7:0]sig_addr_cntr_incr_ireg2; - wire \sig_addr_cntr_incr_ireg2[0]_i_1_n_0 ; - wire \sig_addr_cntr_incr_ireg2[1]_i_1_n_0 ; - wire \sig_addr_cntr_incr_ireg2[2]_i_1_n_0 ; - wire \sig_addr_cntr_incr_ireg2[3]_i_1_n_0 ; - wire \sig_addr_cntr_incr_ireg2[4]_i_1_n_0 ; - wire \sig_addr_cntr_incr_ireg2[5]_i_1_n_0 ; - wire \sig_addr_cntr_incr_ireg2[6]_i_1_n_0 ; - wire \sig_addr_cntr_incr_ireg2[7]_i_1_n_0 ; - wire \sig_addr_cntr_lsh_im0[15]_i_1_n_0 ; - wire \sig_addr_cntr_lsh_im0_reg_n_0_[0] ; - wire \sig_addr_cntr_lsh_im0_reg_n_0_[10] ; - wire \sig_addr_cntr_lsh_im0_reg_n_0_[11] ; - wire \sig_addr_cntr_lsh_im0_reg_n_0_[12] ; - wire \sig_addr_cntr_lsh_im0_reg_n_0_[13] ; - wire \sig_addr_cntr_lsh_im0_reg_n_0_[14] ; - wire \sig_addr_cntr_lsh_im0_reg_n_0_[1] ; - wire \sig_addr_cntr_lsh_im0_reg_n_0_[2] ; - wire \sig_addr_cntr_lsh_im0_reg_n_0_[3] ; - wire \sig_addr_cntr_lsh_im0_reg_n_0_[4] ; - wire \sig_addr_cntr_lsh_im0_reg_n_0_[5] ; - wire \sig_addr_cntr_lsh_im0_reg_n_0_[6] ; - wire \sig_addr_cntr_lsh_im0_reg_n_0_[7] ; - wire \sig_addr_cntr_lsh_im0_reg_n_0_[8] ; - wire \sig_addr_cntr_lsh_im0_reg_n_0_[9] ; - wire [31:0]sig_addr_cntr_lsh_kh; - wire [6:0]sig_adjusted_addr_incr_im1; - wire \sig_adjusted_addr_incr_ireg2[1]_i_2_n_0 ; - wire \sig_adjusted_addr_incr_ireg2[2]_i_2_n_0 ; - wire \sig_adjusted_addr_incr_ireg2[3]_i_2_n_0 ; - wire \sig_adjusted_addr_incr_ireg2[6]_i_2_n_0 ; - wire \sig_adjusted_addr_incr_ireg2_reg_n_0_[0] ; - wire \sig_adjusted_addr_incr_ireg2_reg_n_0_[1] ; - wire \sig_adjusted_addr_incr_ireg2_reg_n_0_[2] ; - wire \sig_adjusted_addr_incr_ireg2_reg_n_0_[3] ; - wire \sig_adjusted_addr_incr_ireg2_reg_n_0_[4] ; - wire \sig_adjusted_addr_incr_ireg2_reg_n_0_[5] ; - wire \sig_adjusted_addr_incr_ireg2_reg_n_0_[6] ; - wire sig_brst_cnt_eq_one_im0; - wire sig_brst_cnt_eq_one_ireg1; - wire sig_brst_cnt_eq_one_ireg1_i_2_n_0; - wire sig_brst_cnt_eq_zero_im0; - wire sig_brst_cnt_eq_zero_ireg1; - wire sig_brst_cnt_eq_zero_ireg1_i_2_n_0; - wire [15:0]sig_btt_cntr_im00; - wire sig_btt_cntr_im00_carry__0_i_1_n_0; - wire sig_btt_cntr_im00_carry__0_i_2_n_0; - wire sig_btt_cntr_im00_carry__0_i_3_n_0; - wire sig_btt_cntr_im00_carry__0_i_4_n_0; - wire sig_btt_cntr_im00_carry__0_n_0; - wire sig_btt_cntr_im00_carry__0_n_1; - wire sig_btt_cntr_im00_carry__0_n_2; - wire sig_btt_cntr_im00_carry__0_n_3; - wire sig_btt_cntr_im00_carry__1_i_1_n_0; - wire sig_btt_cntr_im00_carry__1_i_2_n_0; - wire sig_btt_cntr_im00_carry__1_i_3_n_0; - wire sig_btt_cntr_im00_carry__1_i_4_n_0; - wire sig_btt_cntr_im00_carry__1_n_0; - wire sig_btt_cntr_im00_carry__1_n_1; - wire sig_btt_cntr_im00_carry__1_n_2; - wire sig_btt_cntr_im00_carry__1_n_3; - wire sig_btt_cntr_im00_carry__2_i_1_n_0; - wire sig_btt_cntr_im00_carry__2_i_2_n_0; - wire sig_btt_cntr_im00_carry__2_i_3_n_0; - wire sig_btt_cntr_im00_carry__2_i_4_n_0; - wire sig_btt_cntr_im00_carry__2_n_1; - wire sig_btt_cntr_im00_carry__2_n_2; - wire sig_btt_cntr_im00_carry__2_n_3; - wire sig_btt_cntr_im00_carry_i_1_n_0; - wire sig_btt_cntr_im00_carry_i_2_n_0; - wire sig_btt_cntr_im00_carry_i_3_n_0; - wire sig_btt_cntr_im00_carry_i_4_n_0; - wire sig_btt_cntr_im00_carry_n_0; - wire sig_btt_cntr_im00_carry_n_1; - wire sig_btt_cntr_im00_carry_n_2; - wire sig_btt_cntr_im00_carry_n_3; - wire \sig_btt_cntr_im0[0]_i_1_n_0 ; - wire \sig_btt_cntr_im0[10]_i_1_n_0 ; - wire \sig_btt_cntr_im0[11]_i_1_n_0 ; - wire \sig_btt_cntr_im0[12]_i_1_n_0 ; - wire \sig_btt_cntr_im0[13]_i_1_n_0 ; - wire \sig_btt_cntr_im0[14]_i_1_n_0 ; - wire \sig_btt_cntr_im0[15]_i_1_n_0 ; - wire \sig_btt_cntr_im0[1]_i_1_n_0 ; - wire \sig_btt_cntr_im0[2]_i_1_n_0 ; - wire \sig_btt_cntr_im0[3]_i_1_n_0 ; - wire \sig_btt_cntr_im0[4]_i_1_n_0 ; - wire \sig_btt_cntr_im0[5]_i_1_n_0 ; - wire \sig_btt_cntr_im0[6]_i_1_n_0 ; - wire \sig_btt_cntr_im0[7]_i_1_n_0 ; - wire \sig_btt_cntr_im0[8]_i_1_n_0 ; - wire \sig_btt_cntr_im0[9]_i_1_n_0 ; - wire sig_btt_eq_b2mbaa_im0; - wire sig_btt_eq_b2mbaa_ireg1; - wire sig_btt_eq_b2mbaa_ireg1_i_2_n_0; - wire sig_btt_eq_b2mbaa_ireg1_i_3_n_0; - wire sig_btt_eq_b2mbaa_ireg1_i_4_n_0; - wire sig_btt_lt_b2mbaa_im0; - wire sig_btt_lt_b2mbaa_im01; - wire sig_btt_lt_b2mbaa_im01_carry_i_1_n_0; - wire sig_btt_lt_b2mbaa_im01_carry_i_2_n_0; - wire sig_btt_lt_b2mbaa_im01_carry_i_3_n_0; - wire sig_btt_lt_b2mbaa_im01_carry_i_4_n_0; - wire sig_btt_lt_b2mbaa_im01_carry_i_5_n_0; - wire sig_btt_lt_b2mbaa_im01_carry_i_6_n_0; - wire sig_btt_lt_b2mbaa_im01_carry_i_7_n_0; - wire sig_btt_lt_b2mbaa_im01_carry_i_8_n_0; - wire sig_btt_lt_b2mbaa_im01_carry_n_1; - wire sig_btt_lt_b2mbaa_im01_carry_n_2; - wire sig_btt_lt_b2mbaa_im01_carry_n_3; - wire sig_btt_lt_b2mbaa_ireg1; - wire [6:0]sig_btt_residue_slice_im0; - wire \sig_byte_change_minus1_im2/i__n_0 ; - wire [7:0]sig_bytes_to_mbaa_ireg1; - wire \sig_bytes_to_mbaa_ireg1[1]_i_1_n_0 ; - wire \sig_bytes_to_mbaa_ireg1[2]_i_1_n_0 ; - wire \sig_bytes_to_mbaa_ireg1[3]_i_1_n_0 ; - wire \sig_bytes_to_mbaa_ireg1[4]_i_1_n_0 ; - wire \sig_bytes_to_mbaa_ireg1[5]_i_1_n_0 ; - wire \sig_bytes_to_mbaa_ireg1[6]_i_1_n_0 ; - wire \sig_bytes_to_mbaa_ireg1[7]_i_1_n_0 ; - wire \sig_bytes_to_mbaa_ireg1[7]_i_2_n_0 ; - wire sig_calc_error_pushed; - wire sig_calc_error_pushed_i_1_n_0; - wire sig_cmd2addr_valid_i_1_n_0; - wire sig_cmd2data_valid_i_1_n_0; - wire sig_cmd2dre_valid_i_1_n_0; + wire [1:0]in; + wire m_axi_s2mm_aclk; + wire m_axi_s2mm_bready; + wire [1:0]m_axi_s2mm_bresp; + wire m_axi_s2mm_bvalid; + wire [0:0]out; wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - wire sig_first_xfer_im0; - wire sig_first_xfer_im0_i_1_n_0; + wire sig_csm_pop_child_cmd; + wire sig_halt_reg; wire sig_inhibit_rdy_n; + wire sig_inhibit_rdy_n_i_1_n_0; wire sig_init_done; + wire sig_init_done_0; + wire sig_init_done_1; wire sig_init_done_2; wire sig_init_done_3; - wire sig_init_done_4; - wire sig_init_done_reg; + wire sig_init_done_i_1_n_0; wire sig_init_done_reg_0; wire sig_init_done_reg_1; wire sig_init_done_reg_2; - wire sig_init_reg; + wire sig_init_done_reg_3; wire sig_init_reg2; + wire sig_init_reg2_reg; wire sig_input_cache_type_reg0; - wire sig_input_reg_empty; - wire sig_input_reg_empty_i_1_n_0; - wire sig_last_xfer_valid_im1; - wire sig_ld_xfer_reg; - wire sig_ld_xfer_reg_i_1_n_0; - wire sig_ld_xfer_reg_tmp; - wire sig_ld_xfer_reg_tmp_i_1_n_0; - wire sig_mstr2addr_cmd_valid; - wire sig_mstr2data_cmd_valid; - wire sig_mstr2sf_cmd_valid; - wire sig_mstr2sf_eof; - wire [2:0]sig_next_cmd_cmplt_reg_reg; - wire sig_no_btt_residue_im0; - wire sig_no_btt_residue_ireg1; - wire sig_no_btt_residue_ireg1_i_2_n_0; - wire sig_parent_done; - wire sig_parent_done_i_1_n_0; - (* RTL_KEEP = "yes" *) wire [2:0]sig_pcc_sm_state; - wire sig_pop_xfer_reg0_out; - wire [15:0]sig_predict_addr_lsh_im2; - wire [15:15]sig_predict_addr_lsh_ireg3; - wire \sig_predict_addr_lsh_ireg3[11]_i_2_n_0 ; - wire \sig_predict_addr_lsh_ireg3[11]_i_3_n_0 ; - wire \sig_predict_addr_lsh_ireg3[11]_i_4_n_0 ; - wire \sig_predict_addr_lsh_ireg3[11]_i_5_n_0 ; - wire \sig_predict_addr_lsh_ireg3[15]_i_2_n_0 ; - wire \sig_predict_addr_lsh_ireg3[15]_i_3_n_0 ; - wire \sig_predict_addr_lsh_ireg3[15]_i_4_n_0 ; - wire \sig_predict_addr_lsh_ireg3[15]_i_5_n_0 ; - wire \sig_predict_addr_lsh_ireg3[3]_i_2_n_0 ; - wire \sig_predict_addr_lsh_ireg3[3]_i_3_n_0 ; - wire \sig_predict_addr_lsh_ireg3[3]_i_4_n_0 ; - wire \sig_predict_addr_lsh_ireg3[3]_i_5_n_0 ; - wire \sig_predict_addr_lsh_ireg3[7]_i_2_n_0 ; - wire \sig_predict_addr_lsh_ireg3[7]_i_3_n_0 ; - wire \sig_predict_addr_lsh_ireg3[7]_i_4_n_0 ; - wire \sig_predict_addr_lsh_ireg3[7]_i_5_n_0 ; - wire \sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_0 ; - wire \sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_1 ; - wire \sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_2 ; - wire \sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_3 ; - wire \sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_1 ; - wire \sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_2 ; - wire \sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_3 ; - wire \sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_0 ; - wire \sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_1 ; - wire \sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_2 ; - wire \sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_3 ; - wire \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_0 ; - wire \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_1 ; - wire \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_2 ; - wire \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_3 ; - wire \sig_predict_addr_lsh_ireg3_reg_n_0_[0] ; - wire \sig_predict_addr_lsh_ireg3_reg_n_0_[10] ; - wire \sig_predict_addr_lsh_ireg3_reg_n_0_[11] ; - wire \sig_predict_addr_lsh_ireg3_reg_n_0_[12] ; - wire \sig_predict_addr_lsh_ireg3_reg_n_0_[13] ; - wire \sig_predict_addr_lsh_ireg3_reg_n_0_[14] ; - wire \sig_predict_addr_lsh_ireg3_reg_n_0_[1] ; - wire \sig_predict_addr_lsh_ireg3_reg_n_0_[2] ; - wire \sig_predict_addr_lsh_ireg3_reg_n_0_[3] ; - wire \sig_predict_addr_lsh_ireg3_reg_n_0_[4] ; - wire \sig_predict_addr_lsh_ireg3_reg_n_0_[5] ; - wire \sig_predict_addr_lsh_ireg3_reg_n_0_[6] ; - wire \sig_predict_addr_lsh_ireg3_reg_n_0_[7] ; - wire \sig_predict_addr_lsh_ireg3_reg_n_0_[8] ; - wire \sig_predict_addr_lsh_ireg3_reg_n_0_[9] ; - wire sig_push_input_reg11_out; - wire sig_sm_halt_ns; - wire sig_sm_halt_reg; - wire sig_sm_ld_calc1_reg; - wire sig_sm_ld_calc1_reg_ns; - wire sig_sm_ld_calc2_reg; - wire sig_sm_ld_calc2_reg_ns; - wire sig_sm_ld_calc3_reg; - wire sig_sm_ld_calc3_reg_ns; - wire sig_sm_ld_xfer_reg_ns; - wire sig_sm_pop_input_reg; - wire sig_sm_pop_input_reg_ns; - wire sig_wr_fifo; - wire sig_wr_fifo_0; - wire sig_wr_fifo_1; - wire sig_xfer_reg_empty; - wire sig_xfer_reg_empty_i_1_n_0; - wire [3:3]\NLW_sig_addr_cntr_im0_msh_reg[12]_i_1_CO_UNCONNECTED ; - wire [3:3]NLW_sig_btt_cntr_im00_carry__2_CO_UNCONNECTED; - wire [3:0]NLW_sig_btt_lt_b2mbaa_im01_carry_O_UNCONNECTED; - wire [3:3]\NLW_sig_predict_addr_lsh_ireg3_reg[15]_i_1_CO_UNCONNECTED ; + wire sig_posted_to_axi_reg; + wire sig_psm_pop_input_cmd; + wire sig_push_coelsc_reg; + wire sig_stream_rst; - LUT6 #( - .INIT(64'hDD3F00FFDD3F33FF)) - \FSM_sequential_sig_pcc_sm_state[0]_i_1 - (.I0(sig_pop_xfer_reg0_out), - .I1(sig_pcc_sm_state[1]), - .I2(\FSM_sequential_sig_pcc_sm_state[0]_i_2_n_0 ), - .I3(sig_pcc_sm_state[0]), - .I4(sig_pcc_sm_state[2]), - .I5(sig_push_input_reg11_out), - .O(\FSM_sequential_sig_pcc_sm_state[0]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair85" *) - LUT2 #( - .INIT(4'h1)) - \FSM_sequential_sig_pcc_sm_state[0]_i_2 - (.I0(sig_parent_done), - .I1(sig_calc_error_pushed), - .O(\FSM_sequential_sig_pcc_sm_state[0]_i_2_n_0 )); - LUT6 #( - .INIT(64'hA8A0A8A00AA000A0)) - \FSM_sequential_sig_pcc_sm_state[1]_i_1 - (.I0(\FSM_sequential_sig_pcc_sm_state[1]_i_2_n_0 ), - .I1(sig_pop_xfer_reg0_out), - .I2(sig_pcc_sm_state[1]), - .I3(sig_pcc_sm_state[0]), - .I4(sig_push_input_reg11_out), - .I5(sig_pcc_sm_state[2]), - .O(\FSM_sequential_sig_pcc_sm_state[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair252" *) LUT4 #( - .INIT(16'hFFF7)) - \FSM_sequential_sig_pcc_sm_state[1]_i_2 - (.I0(sig_pcc_sm_state[2]), - .I1(sig_parent_done), - .I2(sig_calc_error_pushed), - .I3(sig_pcc_sm_state[0]), - .O(\FSM_sequential_sig_pcc_sm_state[1]_i_2_n_0 )); - LUT6 #( - .INIT(64'hCF450000CF45CF44)) - \FSM_sequential_sig_pcc_sm_state[1]_i_3 - (.I0(sig_mstr2addr_cmd_valid), - .I1(sig_wr_fifo), - .I2(sig_mstr2data_cmd_valid), - .I3(sig_wr_fifo_0), - .I4(sig_wr_fifo_1), - .I5(sig_mstr2sf_cmd_valid), - .O(sig_pop_xfer_reg0_out)); + .INIT(16'h0080)) + \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/sig_init_done_i_1 + (.I0(sig_init_reg2_reg), + .I1(sig_init_reg2), + .I2(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I3(sig_init_done), + .O(sig_init_done_reg_0)); + (* SOFT_HLUTNM = "soft_lutpair253" *) LUT4 #( - .INIT(16'hECAA)) - \FSM_sequential_sig_pcc_sm_state[2]_i_1 - (.I0(sig_pcc_sm_state[2]), - .I1(sig_pcc_sm_state[0]), - .I2(sig_calc_error_pushed), - .I3(sig_pcc_sm_state[1]), - .O(\FSM_sequential_sig_pcc_sm_state[2]_i_1_n_0 )); - (* KEEP = "yes" *) - FDRE \FSM_sequential_sig_pcc_sm_state_reg[0] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\FSM_sequential_sig_pcc_sm_state[0]_i_1_n_0 ), - .Q(sig_pcc_sm_state[0]), - .R(sig_init_reg)); - (* KEEP = "yes" *) - FDRE \FSM_sequential_sig_pcc_sm_state_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\FSM_sequential_sig_pcc_sm_state[1]_i_1_n_0 ), - .Q(sig_pcc_sm_state[1]), - .R(sig_init_reg)); - (* KEEP = "yes" *) - FDRE \FSM_sequential_sig_pcc_sm_state_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\FSM_sequential_sig_pcc_sm_state[2]_i_1_n_0 ), - .Q(sig_pcc_sm_state[2]), - .R(sig_init_reg)); - (* SOFT_HLUTNM = "soft_lutpair85" *) + .INIT(16'h0080)) + \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_init_done_i_1 + (.I0(sig_init_reg2_reg), + .I1(sig_init_reg2), + .I2(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I3(sig_init_done_0), + .O(sig_init_done_reg_1)); + (* SOFT_HLUTNM = "soft_lutpair252" *) LUT4 #( - .INIT(16'h0004)) - \INFERRED_GEN.cnt_i[2]_i_2__0 - (.I0(sig_calc_error_pushed), - .I1(sig_input_reg_empty), - .I2(sig_sm_halt_reg), - .I3(Q), - .O(FIFO_Full_reg)); - (* SOFT_HLUTNM = "soft_lutpair93" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][10]_srl4_i_1 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[6] ), - .I1(sig_addr_cntr_lsh_kh[6]), - .I2(in[36]), - .O(in[6])); - (* SOFT_HLUTNM = "soft_lutpair94" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][11]_srl4_i_1 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[7] ), - .I1(sig_addr_cntr_lsh_kh[7]), - .I2(in[36]), - .O(in[7])); - (* SOFT_HLUTNM = "soft_lutpair95" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][12]_srl4_i_1 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[8] ), - .I1(sig_addr_cntr_lsh_kh[8]), - .I2(in[36]), - .O(in[8])); - (* SOFT_HLUTNM = "soft_lutpair94" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][13]_srl4_i_1 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[9] ), - .I1(sig_addr_cntr_lsh_kh[9]), - .I2(in[36]), - .O(in[9])); - (* SOFT_HLUTNM = "soft_lutpair96" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][14]_srl4_i_1 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[10] ), - .I1(sig_addr_cntr_lsh_kh[10]), - .I2(in[36]), - .O(in[10])); - (* SOFT_HLUTNM = "soft_lutpair97" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][15]_srl4_i_1 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[11] ), - .I1(sig_addr_cntr_lsh_kh[11]), - .I2(in[36]), - .O(in[11])); - (* SOFT_HLUTNM = "soft_lutpair91" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][16]_srl4_i_1 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[12] ), - .I1(sig_addr_cntr_lsh_kh[12]), - .I2(in[36]), - .O(in[12])); - (* SOFT_HLUTNM = "soft_lutpair98" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][17]_srl4_i_1 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[13] ), - .I1(sig_addr_cntr_lsh_kh[13]), - .I2(in[36]), - .O(in[13])); - (* SOFT_HLUTNM = "soft_lutpair99" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][18]_srl4_i_1 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[14] ), - .I1(sig_addr_cntr_lsh_kh[14]), - .I2(in[36]), - .O(in[14])); - (* SOFT_HLUTNM = "soft_lutpair98" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][19]_srl4_i_1 - (.I0(p_1_in_0), - .I1(sig_addr_cntr_lsh_kh[15]), - .I2(in[36]), - .O(in[15])); - (* SOFT_HLUTNM = "soft_lutpair97" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][20]_srl4_i_1 - (.I0(sig_addr_cntr_im0_msh_reg[0]), - .I1(sig_addr_cntr_lsh_kh[16]), - .I2(in[36]), - .O(in[16])); - (* SOFT_HLUTNM = "soft_lutpair100" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][21]_srl4_i_1 - (.I0(sig_addr_cntr_im0_msh_reg[1]), - .I1(sig_addr_cntr_lsh_kh[17]), - .I2(in[36]), - .O(in[17])); - (* SOFT_HLUTNM = "soft_lutpair96" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][22]_srl4_i_1 - (.I0(sig_addr_cntr_im0_msh_reg[2]), - .I1(sig_addr_cntr_lsh_kh[18]), - .I2(in[36]), - .O(in[18])); - (* SOFT_HLUTNM = "soft_lutpair88" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][23]_srl4_i_1 - (.I0(sig_addr_cntr_im0_msh_reg[3]), - .I1(sig_addr_cntr_lsh_kh[19]), - .I2(in[36]), - .O(in[19])); - (* SOFT_HLUTNM = "soft_lutpair89" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][24]_srl4_i_1 - (.I0(sig_addr_cntr_im0_msh_reg[4]), - .I1(sig_addr_cntr_lsh_kh[20]), - .I2(in[36]), - .O(in[20])); - (* SOFT_HLUTNM = "soft_lutpair92" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][25]_srl4_i_1 - (.I0(sig_addr_cntr_im0_msh_reg[5]), - .I1(sig_addr_cntr_lsh_kh[21]), - .I2(in[36]), - .O(in[21])); - (* SOFT_HLUTNM = "soft_lutpair90" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][26]_srl4_i_1 - (.I0(sig_addr_cntr_im0_msh_reg[6]), - .I1(sig_addr_cntr_lsh_kh[22]), - .I2(in[36]), - .O(in[22])); - (* SOFT_HLUTNM = "soft_lutpair101" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][27]_srl4_i_1 - (.I0(sig_addr_cntr_im0_msh_reg[7]), - .I1(sig_addr_cntr_lsh_kh[23]), - .I2(in[36]), - .O(in[23])); - (* SOFT_HLUTNM = "soft_lutpair102" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][28]_srl4_i_1 - (.I0(sig_addr_cntr_im0_msh_reg[8]), - .I1(sig_addr_cntr_lsh_kh[24]), - .I2(in[36]), - .O(in[24])); - (* SOFT_HLUTNM = "soft_lutpair101" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][29]_srl4_i_1 - (.I0(sig_addr_cntr_im0_msh_reg[9]), - .I1(sig_addr_cntr_lsh_kh[25]), - .I2(in[36]), - .O(in[25])); - (* SOFT_HLUTNM = "soft_lutpair102" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][30]_srl4_i_1 - (.I0(sig_addr_cntr_im0_msh_reg[10]), - .I1(sig_addr_cntr_lsh_kh[26]), - .I2(in[36]), - .O(in[26])); - (* SOFT_HLUTNM = "soft_lutpair100" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][31]_srl4_i_1 - (.I0(sig_addr_cntr_im0_msh_reg[11]), - .I1(sig_addr_cntr_lsh_kh[27]), - .I2(in[36]), - .O(in[27])); + .INIT(16'h0080)) + \GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_init_done_i_1 + (.I0(sig_init_reg2_reg), + .I1(sig_init_reg2), + .I2(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I3(sig_init_done_1), + .O(sig_init_done_reg_2)); + (* SOFT_HLUTNM = "soft_lutpair253" *) + LUT4 #( + .INIT(16'h0080)) + \I_CMD_FIFO/sig_init_done_i_1 + (.I0(sig_init_reg2_reg), + .I1(sig_init_reg2), + .I2(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I3(sig_init_done_2), + .O(sig_init_done_reg_3)); + Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized5 \USE_SRL_FIFO.I_SYNC_FIFO + (.D(D), + .E(E), + .\GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg (\GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg ), + .\GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg (\GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg ), + .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ), + .\INFERRED_GEN.cnt_i_reg[3] (\INFERRED_GEN.cnt_i_reg[3] ), + .Q(Q), + .in(in), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .m_axi_s2mm_bready(m_axi_s2mm_bready), + .m_axi_s2mm_bresp(m_axi_s2mm_bresp), + .m_axi_s2mm_bvalid(m_axi_s2mm_bvalid), + .out(out), + .sig_halt_reg(sig_halt_reg), + .sig_inhibit_rdy_n(sig_inhibit_rdy_n), + .sig_posted_to_axi_reg(sig_posted_to_axi_reg), + .sig_push_coelsc_reg(sig_push_coelsc_reg), + .sig_stream_rst(sig_stream_rst)); LUT2 #( - .INIT(4'h8)) - \INFERRED_GEN.data_reg[3][32]_srl4_i_1 - (.I0(sig_mstr2sf_eof), - .I1(sig_last_xfer_valid_im1), - .O(sig_next_cmd_cmplt_reg_reg[0])); - (* SOFT_HLUTNM = "soft_lutpair99" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][32]_srl4_i_1__0 - (.I0(sig_addr_cntr_im0_msh_reg[12]), - .I1(sig_addr_cntr_lsh_kh[28]), - .I2(in[36]), - .O(in[28])); - LUT6 #( - .INIT(64'h8F808F808F808080)) - \INFERRED_GEN.data_reg[3][32]_srl4_i_2 - (.I0(sig_addr_aligned_ireg1), - .I1(sig_brst_cnt_eq_one_ireg1), - .I2(sig_no_btt_residue_ireg1), - .I3(sig_brst_cnt_eq_zero_ireg1), - .I4(sig_btt_eq_b2mbaa_ireg1), - .I5(sig_btt_lt_b2mbaa_ireg1), - .O(sig_last_xfer_valid_im1)); - LUT6 #( - .INIT(64'h001FFF1FFF1FFF1F)) - \INFERRED_GEN.data_reg[3][33]_srl4_i_1 - (.I0(sig_btt_lt_b2mbaa_ireg1), - .I1(sig_btt_eq_b2mbaa_ireg1), - .I2(sig_brst_cnt_eq_zero_ireg1), - .I3(sig_no_btt_residue_ireg1), - .I4(sig_brst_cnt_eq_one_ireg1), - .I5(sig_addr_aligned_ireg1), - .O(sig_next_cmd_cmplt_reg_reg[1])); - (* SOFT_HLUTNM = "soft_lutpair87" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][33]_srl4_i_1__0 - (.I0(sig_addr_cntr_im0_msh_reg[13]), - .I1(sig_addr_cntr_lsh_kh[29]), - .I2(in[36]), - .O(in[29])); - (* SOFT_HLUTNM = "soft_lutpair81" *) + .INIT(4'hE)) + sig_child_error_reg_i_1 + (.I0(sig_init_reg2_reg), + .I1(sig_csm_pop_child_cmd), + .O(SR)); LUT2 #( .INIT(4'hE)) - \INFERRED_GEN.data_reg[3][34]_srl4_i_1 - (.I0(sig_last_xfer_valid_im1), - .I1(in[37]), - .O(sig_next_cmd_cmplt_reg_reg[2])); - (* SOFT_HLUTNM = "soft_lutpair93" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][34]_srl4_i_1__0 - (.I0(sig_addr_cntr_im0_msh_reg[14]), - .I1(sig_addr_cntr_lsh_kh[30]), - .I2(in[36]), - .O(in[30])); - (* SOFT_HLUTNM = "soft_lutpair95" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][35]_srl4_i_1 - (.I0(sig_addr_cntr_im0_msh_reg[15]), - .I1(sig_addr_cntr_lsh_kh[31]), - .I2(in[36]), - .O(in[31])); - LUT4 #( - .INIT(16'hFE01)) - \INFERRED_GEN.data_reg[3][36]_srl4_i_1 - (.I0(\sig_adjusted_addr_incr_ireg2_reg_n_0_[2] ), - .I1(\sig_adjusted_addr_incr_ireg2_reg_n_0_[0] ), - .I2(\sig_adjusted_addr_incr_ireg2_reg_n_0_[1] ), - .I3(\sig_adjusted_addr_incr_ireg2_reg_n_0_[3] ), - .O(in[32])); - (* SOFT_HLUTNM = "soft_lutpair76" *) - LUT5 #( - .INIT(32'hFFFE0001)) - \INFERRED_GEN.data_reg[3][37]_srl4_i_1 - (.I0(\sig_adjusted_addr_incr_ireg2_reg_n_0_[3] ), - .I1(\sig_adjusted_addr_incr_ireg2_reg_n_0_[1] ), - .I2(\sig_adjusted_addr_incr_ireg2_reg_n_0_[0] ), - .I3(\sig_adjusted_addr_incr_ireg2_reg_n_0_[2] ), - .I4(\sig_adjusted_addr_incr_ireg2_reg_n_0_[4] ), - .O(in[33])); - LUT6 #( - .INIT(64'hFFFFFFFE00000001)) - \INFERRED_GEN.data_reg[3][38]_srl4_i_1 - (.I0(\sig_adjusted_addr_incr_ireg2_reg_n_0_[4] ), - .I1(\sig_adjusted_addr_incr_ireg2_reg_n_0_[2] ), - .I2(\sig_adjusted_addr_incr_ireg2_reg_n_0_[0] ), - .I3(\sig_adjusted_addr_incr_ireg2_reg_n_0_[1] ), - .I4(\sig_adjusted_addr_incr_ireg2_reg_n_0_[3] ), - .I5(\sig_adjusted_addr_incr_ireg2_reg_n_0_[5] ), - .O(in[34])); - LUT3 #( - .INIT(8'hE1)) - \INFERRED_GEN.data_reg[3][39]_srl4_i_1 - (.I0(\sig_adjusted_addr_incr_ireg2_reg_n_0_[5] ), - .I1(\sig_byte_change_minus1_im2/i__n_0 ), - .I2(\sig_adjusted_addr_incr_ireg2_reg_n_0_[6] ), - .O(in[35])); - (* SOFT_HLUTNM = "soft_lutpair87" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][4]_srl4_i_2 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), - .I1(sig_addr_cntr_lsh_kh[0]), - .I2(in[36]), - .O(in[0])); - (* SOFT_HLUTNM = "soft_lutpair88" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][5]_srl4_i_1 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), - .I1(sig_addr_cntr_lsh_kh[1]), - .I2(in[36]), - .O(in[1])); - (* SOFT_HLUTNM = "soft_lutpair89" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][6]_srl4_i_1 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), - .I1(sig_addr_cntr_lsh_kh[2]), - .I2(in[36]), - .O(in[2])); - (* SOFT_HLUTNM = "soft_lutpair90" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][7]_srl4_i_1__1 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[3] ), - .I1(sig_addr_cntr_lsh_kh[3]), - .I2(in[36]), - .O(in[3])); - (* SOFT_HLUTNM = "soft_lutpair91" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][8]_srl4_i_1 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[4] ), - .I1(sig_addr_cntr_lsh_kh[4]), - .I2(in[36]), - .O(in[4])); - (* SOFT_HLUTNM = "soft_lutpair92" *) - LUT3 #( - .INIT(8'hAC)) - \INFERRED_GEN.data_reg[3][9]_srl4_i_1 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[5] ), - .I1(sig_addr_cntr_lsh_kh[5]), - .I2(in[36]), - .O(in[5])); - LUT6 #( - .INIT(64'h0000000000000100)) - sig_addr_aligned_ireg1_i_1 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[6] ), - .I1(\sig_addr_cntr_lsh_im0_reg_n_0_[4] ), - .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[5] ), - .I3(\sig_bytes_to_mbaa_ireg1[7]_i_2_n_0 ), - .I4(\sig_addr_cntr_lsh_im0_reg_n_0_[3] ), - .I5(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), - .O(sig_addr_aligned_im0)); + sig_inhibit_rdy_n_i_1 + (.I0(sig_init_done_3), + .I1(sig_inhibit_rdy_n), + .O(sig_inhibit_rdy_n_i_1_n_0)); FDRE #( .INIT(1'b0)) - sig_addr_aligned_ireg1_reg - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc1_reg), - .D(sig_addr_aligned_im0), - .Q(sig_addr_aligned_ireg1), - .R(sig_init_reg)); + sig_inhibit_rdy_n_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_inhibit_rdy_n_i_1_n_0), + .Q(sig_inhibit_rdy_n), + .R(sig_stream_rst)); + (* SOFT_HLUTNM = "soft_lutpair254" *) LUT4 #( - .INIT(16'hAAEA)) - \sig_addr_cntr_im0_msh[0]_i_1 - (.I0(sig_push_input_reg11_out), - .I1(p_1_in_0), - .I2(sig_pop_xfer_reg0_out), - .I3(sig_predict_addr_lsh_ireg3), - .O(\sig_addr_cntr_im0_msh[0]_i_1_n_0 )); - LUT6 #( - .INIT(64'hFFFFFFEF00000020)) - \sig_addr_cntr_im0_msh[0]_i_3 - (.I0(out[34]), - .I1(in[37]), - .I2(sig_input_reg_empty), - .I3(sig_sm_halt_reg), - .I4(Q), - .I5(sig_addr_cntr_im0_msh_reg[0]), - .O(\sig_addr_cntr_im0_msh[0]_i_3_n_0 )); - LUT6 #( - .INIT(64'hFFFFFFEF00000020)) - \sig_addr_cntr_im0_msh[0]_i_4 - (.I0(out[37]), - .I1(in[37]), - .I2(sig_input_reg_empty), - .I3(sig_sm_halt_reg), - .I4(Q), - .I5(sig_addr_cntr_im0_msh_reg[3]), - .O(\sig_addr_cntr_im0_msh[0]_i_4_n_0 )); - LUT6 #( - .INIT(64'hFFFFFFEF00000020)) - \sig_addr_cntr_im0_msh[0]_i_5 - (.I0(out[36]), - .I1(in[37]), - .I2(sig_input_reg_empty), - .I3(sig_sm_halt_reg), - .I4(Q), - .I5(sig_addr_cntr_im0_msh_reg[2]), - .O(\sig_addr_cntr_im0_msh[0]_i_5_n_0 )); - LUT6 #( - .INIT(64'hFFFFFFEF00000020)) - \sig_addr_cntr_im0_msh[0]_i_6 - (.I0(out[35]), - .I1(in[37]), - .I2(sig_input_reg_empty), - .I3(sig_sm_halt_reg), - .I4(Q), - .I5(sig_addr_cntr_im0_msh_reg[1]), - .O(\sig_addr_cntr_im0_msh[0]_i_6_n_0 )); - LUT6 #( - .INIT(64'h55555555555C5555)) - \sig_addr_cntr_im0_msh[0]_i_7 - (.I0(sig_addr_cntr_im0_msh_reg[0]), - .I1(out[34]), - .I2(Q), - .I3(sig_sm_halt_reg), - .I4(sig_input_reg_empty), - .I5(in[37]), - .O(\sig_addr_cntr_im0_msh[0]_i_7_n_0 )); - LUT6 #( - .INIT(64'hFFFFFFEF00000020)) - \sig_addr_cntr_im0_msh[12]_i_2 - (.I0(out[49]), - .I1(in[37]), - .I2(sig_input_reg_empty), - .I3(sig_sm_halt_reg), - .I4(Q), - .I5(sig_addr_cntr_im0_msh_reg[15]), - .O(\sig_addr_cntr_im0_msh[12]_i_2_n_0 )); - LUT6 #( - .INIT(64'hFFFFFFEF00000020)) - \sig_addr_cntr_im0_msh[12]_i_3 - (.I0(out[48]), - .I1(in[37]), - .I2(sig_input_reg_empty), - .I3(sig_sm_halt_reg), - .I4(Q), - .I5(sig_addr_cntr_im0_msh_reg[14]), - .O(\sig_addr_cntr_im0_msh[12]_i_3_n_0 )); - LUT6 #( - .INIT(64'hFFFFFFEF00000020)) - \sig_addr_cntr_im0_msh[12]_i_4 - (.I0(out[47]), - .I1(in[37]), - .I2(sig_input_reg_empty), - .I3(sig_sm_halt_reg), - .I4(Q), - .I5(sig_addr_cntr_im0_msh_reg[13]), - .O(\sig_addr_cntr_im0_msh[12]_i_4_n_0 )); - LUT6 #( - .INIT(64'hFFFFFFEF00000020)) - \sig_addr_cntr_im0_msh[12]_i_5 - (.I0(out[46]), - .I1(in[37]), - .I2(sig_input_reg_empty), - .I3(sig_sm_halt_reg), - .I4(Q), - .I5(sig_addr_cntr_im0_msh_reg[12]), - .O(\sig_addr_cntr_im0_msh[12]_i_5_n_0 )); - LUT6 #( - .INIT(64'hFFFFFFEF00000020)) - \sig_addr_cntr_im0_msh[4]_i_2 - (.I0(out[41]), - .I1(in[37]), - .I2(sig_input_reg_empty), - .I3(sig_sm_halt_reg), - .I4(Q), - .I5(sig_addr_cntr_im0_msh_reg[7]), - .O(\sig_addr_cntr_im0_msh[4]_i_2_n_0 )); - LUT6 #( - .INIT(64'hFFFFFFEF00000020)) - \sig_addr_cntr_im0_msh[4]_i_3 - (.I0(out[40]), - .I1(in[37]), - .I2(sig_input_reg_empty), - .I3(sig_sm_halt_reg), - .I4(Q), - .I5(sig_addr_cntr_im0_msh_reg[6]), - .O(\sig_addr_cntr_im0_msh[4]_i_3_n_0 )); - LUT6 #( - .INIT(64'hFFFFFFEF00000020)) - \sig_addr_cntr_im0_msh[4]_i_4 - (.I0(out[39]), - .I1(in[37]), - .I2(sig_input_reg_empty), - .I3(sig_sm_halt_reg), - .I4(Q), - .I5(sig_addr_cntr_im0_msh_reg[5]), - .O(\sig_addr_cntr_im0_msh[4]_i_4_n_0 )); - LUT6 #( - .INIT(64'hFFFFFFEF00000020)) - \sig_addr_cntr_im0_msh[4]_i_5 - (.I0(out[38]), - .I1(in[37]), - .I2(sig_input_reg_empty), - .I3(sig_sm_halt_reg), - .I4(Q), - .I5(sig_addr_cntr_im0_msh_reg[4]), - .O(\sig_addr_cntr_im0_msh[4]_i_5_n_0 )); - LUT6 #( - .INIT(64'hFFFFFFEF00000020)) - \sig_addr_cntr_im0_msh[8]_i_2 - (.I0(out[45]), - .I1(in[37]), - .I2(sig_input_reg_empty), - .I3(sig_sm_halt_reg), - .I4(Q), - .I5(sig_addr_cntr_im0_msh_reg[11]), - .O(\sig_addr_cntr_im0_msh[8]_i_2_n_0 )); - LUT6 #( - .INIT(64'hFFFFFFEF00000020)) - \sig_addr_cntr_im0_msh[8]_i_3 - (.I0(out[44]), - .I1(in[37]), - .I2(sig_input_reg_empty), - .I3(sig_sm_halt_reg), - .I4(Q), - .I5(sig_addr_cntr_im0_msh_reg[10]), - .O(\sig_addr_cntr_im0_msh[8]_i_3_n_0 )); - LUT6 #( - .INIT(64'hFFFFFFEF00000020)) - \sig_addr_cntr_im0_msh[8]_i_4 - (.I0(out[43]), - .I1(in[37]), - .I2(sig_input_reg_empty), - .I3(sig_sm_halt_reg), - .I4(Q), - .I5(sig_addr_cntr_im0_msh_reg[9]), - .O(\sig_addr_cntr_im0_msh[8]_i_4_n_0 )); - LUT6 #( - .INIT(64'hFFFFFFEF00000020)) - \sig_addr_cntr_im0_msh[8]_i_5 - (.I0(out[42]), - .I1(in[37]), - .I2(sig_input_reg_empty), - .I3(sig_sm_halt_reg), - .I4(Q), - .I5(sig_addr_cntr_im0_msh_reg[8]), - .O(\sig_addr_cntr_im0_msh[8]_i_5_n_0 )); + .INIT(16'h0080)) + sig_init_done_i_1 + (.I0(sig_init_reg2_reg), + .I1(sig_init_reg2), + .I2(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I3(sig_init_done_3), + .O(sig_init_done_i_1_n_0)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_im0_msh_reg[0] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), - .D(\sig_addr_cntr_im0_msh_reg[0]_i_2_n_7 ), - .Q(sig_addr_cntr_im0_msh_reg[0]), - .R(sig_init_reg)); - CARRY4 \sig_addr_cntr_im0_msh_reg[0]_i_2 - (.CI(1'b0), - .CO({\sig_addr_cntr_im0_msh_reg[0]_i_2_n_0 ,\sig_addr_cntr_im0_msh_reg[0]_i_2_n_1 ,\sig_addr_cntr_im0_msh_reg[0]_i_2_n_2 ,\sig_addr_cntr_im0_msh_reg[0]_i_2_n_3 }), - .CYINIT(1'b0), - .DI({1'b0,1'b0,1'b0,\sig_addr_cntr_im0_msh[0]_i_3_n_0 }), - .O({\sig_addr_cntr_im0_msh_reg[0]_i_2_n_4 ,\sig_addr_cntr_im0_msh_reg[0]_i_2_n_5 ,\sig_addr_cntr_im0_msh_reg[0]_i_2_n_6 ,\sig_addr_cntr_im0_msh_reg[0]_i_2_n_7 }), - .S({\sig_addr_cntr_im0_msh[0]_i_4_n_0 ,\sig_addr_cntr_im0_msh[0]_i_5_n_0 ,\sig_addr_cntr_im0_msh[0]_i_6_n_0 ,\sig_addr_cntr_im0_msh[0]_i_7_n_0 })); + sig_init_done_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_init_done_i_1_n_0), + .Q(sig_init_done_3), + .R(1'b0)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_im0_msh_reg[10] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), - .D(\sig_addr_cntr_im0_msh_reg[8]_i_1_n_5 ), - .Q(sig_addr_cntr_im0_msh_reg[10]), - .R(sig_init_reg)); + sig_init_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_stream_rst), + .Q(sig_init_reg2_reg), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair254" *) + LUT2 #( + .INIT(4'hE)) + \sig_input_addr_reg[31]_i_1 + (.I0(sig_init_reg2_reg), + .I1(sig_psm_pop_input_cmd), + .O(sig_input_cache_type_reg0)); +endmodule + +(* ORIG_REF_NAME = "axi_datamover_fifo" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized6 + (p_0_in, + out, + sig_push_to_wsc_reg, + D, + sel, + \INFERRED_GEN.cnt_i_reg[1] , + sig_push_coelsc_reg, + E, + p_4_out, + sig_stream_rst, + m_axi_s2mm_aclk, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_data2wsc_valid, + sig_set_push2wsc, + Q, + \INFERRED_GEN.cnt_i_reg[3] , + sig_coelsc_reg_empty, + in, + \GEN_INDET_BTT.lsig_eop_reg_reg , + sig_init_reg_reg, + sig_init_reg2); + output p_0_in; + output [15:0]out; + output sig_push_to_wsc_reg; + output [2:0]D; + output sel; + output \INFERRED_GEN.cnt_i_reg[1] ; + output sig_push_coelsc_reg; + output [0:0]E; + output p_4_out; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_data2wsc_valid; + input sig_set_push2wsc; + input [3:0]Q; + input [0:0]\INFERRED_GEN.cnt_i_reg[3] ; + input sig_coelsc_reg_empty; + input [0:0]in; + input [15:0]\GEN_INDET_BTT.lsig_eop_reg_reg ; + input sig_init_reg_reg; + input sig_init_reg2; + + wire [2:0]D; + wire [0:0]E; + wire [15:0]\GEN_INDET_BTT.lsig_eop_reg_reg ; + wire \INFERRED_GEN.cnt_i_reg[1] ; + wire [0:0]\INFERRED_GEN.cnt_i_reg[3] ; + wire [3:0]Q; + wire [0:0]in; + wire m_axi_s2mm_aclk; + wire [15:0]out; + wire p_0_in; + wire p_4_out; + wire sel; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_coelsc_reg_empty; + wire sig_data2wsc_valid; + wire sig_inhibit_rdy_n; + wire sig_inhibit_rdy_n_i_1_n_0; + wire sig_init_done; + wire sig_init_done_i_1_n_0; + wire sig_init_reg2; + wire sig_init_reg_reg; + wire sig_push_coelsc_reg; + wire sig_push_to_wsc_reg; + wire sig_set_push2wsc; + wire sig_stream_rst; + + Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized6 \USE_SRL_FIFO.I_SYNC_FIFO + (.D(D), + .E(E), + .\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg (sel), + .\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg_0 (sig_push_coelsc_reg), + .\GEN_INDET_BTT.lsig_eop_reg_reg (\GEN_INDET_BTT.lsig_eop_reg_reg ), + .\INFERRED_GEN.cnt_i_reg[1] (\INFERRED_GEN.cnt_i_reg[1] ), + .\INFERRED_GEN.cnt_i_reg[3] (\INFERRED_GEN.cnt_i_reg[3] ), + .Q(Q), + .in(in), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out), + .p_0_in(p_0_in), + .p_4_out(p_4_out), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_coelsc_reg_empty(sig_coelsc_reg_empty), + .sig_data2wsc_valid(sig_data2wsc_valid), + .sig_inhibit_rdy_n(sig_inhibit_rdy_n), + .sig_push_to_wsc_reg(sig_push_to_wsc_reg), + .sig_set_push2wsc(sig_set_push2wsc), + .sig_stream_rst(sig_stream_rst)); + LUT2 #( + .INIT(4'hE)) + sig_inhibit_rdy_n_i_1 + (.I0(sig_init_done), + .I1(sig_inhibit_rdy_n), + .O(sig_inhibit_rdy_n_i_1_n_0)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_im0_msh_reg[11] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), - .D(\sig_addr_cntr_im0_msh_reg[8]_i_1_n_4 ), - .Q(sig_addr_cntr_im0_msh_reg[11]), - .R(sig_init_reg)); + sig_inhibit_rdy_n_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_inhibit_rdy_n_i_1_n_0), + .Q(sig_inhibit_rdy_n), + .R(sig_stream_rst)); + LUT4 #( + .INIT(16'h0080)) + sig_init_done_i_1 + (.I0(sig_init_reg_reg), + .I1(sig_init_reg2), + .I2(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I3(sig_init_done), + .O(sig_init_done_i_1_n_0)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_im0_msh_reg[12] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), - .D(\sig_addr_cntr_im0_msh_reg[12]_i_1_n_7 ), - .Q(sig_addr_cntr_im0_msh_reg[12]), - .R(sig_init_reg)); - CARRY4 \sig_addr_cntr_im0_msh_reg[12]_i_1 - (.CI(\sig_addr_cntr_im0_msh_reg[8]_i_1_n_0 ), - .CO({\NLW_sig_addr_cntr_im0_msh_reg[12]_i_1_CO_UNCONNECTED [3],\sig_addr_cntr_im0_msh_reg[12]_i_1_n_1 ,\sig_addr_cntr_im0_msh_reg[12]_i_1_n_2 ,\sig_addr_cntr_im0_msh_reg[12]_i_1_n_3 }), - .CYINIT(1'b0), - .DI({1'b0,1'b0,1'b0,1'b0}), - .O({\sig_addr_cntr_im0_msh_reg[12]_i_1_n_4 ,\sig_addr_cntr_im0_msh_reg[12]_i_1_n_5 ,\sig_addr_cntr_im0_msh_reg[12]_i_1_n_6 ,\sig_addr_cntr_im0_msh_reg[12]_i_1_n_7 }), - .S({\sig_addr_cntr_im0_msh[12]_i_2_n_0 ,\sig_addr_cntr_im0_msh[12]_i_3_n_0 ,\sig_addr_cntr_im0_msh[12]_i_4_n_0 ,\sig_addr_cntr_im0_msh[12]_i_5_n_0 })); + sig_init_done_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_init_done_i_1_n_0), + .Q(sig_init_done), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "axi_datamover_fifo" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized7 + (\INFERRED_GEN.cnt_i_reg[0] , + sig_init_reg2, + Q, + out, + \INFERRED_GEN.cnt_i_reg[0]_0 , + \GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg , + sig_sm_pop_cmd_fifo_ns, + sig_sm_ld_dre_cmd_ns, + D, + sig_stream_rst, + m_axi_s2mm_aclk, + sig_init_reg, + sig_need_cmd_flush, + p_7_out, + sig_sm_pop_cmd_fifo, + p_9_out_0, + lsig_cmd_fetch_pause, + E, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_good_tlast_dbeat37_out__0, + in, + \FSM_sequential_sig_cmdcntl_sm_state_reg[0] , + \FSM_sequential_sig_cmdcntl_sm_state_reg[2] , + sig_cmd_empty_reg); + output \INFERRED_GEN.cnt_i_reg[0] ; + output sig_init_reg2; + output [0:0]Q; + output [19:0]out; + output \INFERRED_GEN.cnt_i_reg[0]_0 ; + output \GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg ; + output sig_sm_pop_cmd_fifo_ns; + output sig_sm_ld_dre_cmd_ns; + output [2:0]D; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input sig_init_reg; + input sig_need_cmd_flush; + input p_7_out; + input sig_sm_pop_cmd_fifo; + input p_9_out_0; + input lsig_cmd_fetch_pause; + input [0:0]E; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_good_tlast_dbeat37_out__0; + input [21:0]in; + input \FSM_sequential_sig_cmdcntl_sm_state_reg[0] ; + input [2:0]\FSM_sequential_sig_cmdcntl_sm_state_reg[2] ; + input sig_cmd_empty_reg; + + wire [2:0]D; + wire [0:0]E; + wire \FSM_sequential_sig_cmdcntl_sm_state_reg[0] ; + wire [2:0]\FSM_sequential_sig_cmdcntl_sm_state_reg[2] ; + wire \GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg ; + wire \INFERRED_GEN.cnt_i_reg[0] ; + wire \INFERRED_GEN.cnt_i_reg[0]_0 ; + wire [0:0]Q; + wire [21:0]in; + wire lsig_cmd_fetch_pause; + wire m_axi_s2mm_aclk; + wire [19:0]out; + wire p_7_out; + wire p_9_out_0; + wire sig_cmd_empty_reg; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_good_tlast_dbeat37_out__0; + wire sig_inhibit_rdy_n_i_1_n_0; + wire sig_init_done; + wire sig_init_done_i_1_n_0; + wire sig_init_reg; + wire sig_init_reg2; + wire sig_need_cmd_flush; + wire sig_sm_ld_dre_cmd_ns; + wire sig_sm_pop_cmd_fifo; + wire sig_sm_pop_cmd_fifo_ns; + wire sig_stream_rst; + + Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized7 \USE_SRL_FIFO.I_SYNC_FIFO + (.D(D), + .E(E), + .\FSM_sequential_sig_cmdcntl_sm_state_reg[0] (\FSM_sequential_sig_cmdcntl_sm_state_reg[0] ), + .\FSM_sequential_sig_cmdcntl_sm_state_reg[2] (\FSM_sequential_sig_cmdcntl_sm_state_reg[2] ), + .\GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg (\GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg ), + .\INFERRED_GEN.cnt_i_reg[0] (\INFERRED_GEN.cnt_i_reg[0] ), + .Q(Q), + .in(in), + .lsig_cmd_fetch_pause(lsig_cmd_fetch_pause), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out), + .p_7_out(p_7_out), + .p_9_out_0(p_9_out_0), + .sig_cmd_empty_reg(sig_cmd_empty_reg), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_good_tlast_dbeat37_out__0(sig_good_tlast_dbeat37_out__0), + .sig_inhibit_rdy_n_reg(\INFERRED_GEN.cnt_i_reg[0]_0 ), + .sig_need_cmd_flush(sig_need_cmd_flush), + .sig_sm_ld_dre_cmd_ns(sig_sm_ld_dre_cmd_ns), + .sig_sm_pop_cmd_fifo(sig_sm_pop_cmd_fifo), + .sig_sm_pop_cmd_fifo_ns(sig_sm_pop_cmd_fifo_ns), + .sig_stream_rst(sig_stream_rst)); + LUT2 #( + .INIT(4'hE)) + sig_inhibit_rdy_n_i_1 + (.I0(sig_init_done), + .I1(\INFERRED_GEN.cnt_i_reg[0]_0 ), + .O(sig_inhibit_rdy_n_i_1_n_0)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_im0_msh_reg[13] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), - .D(\sig_addr_cntr_im0_msh_reg[12]_i_1_n_6 ), - .Q(sig_addr_cntr_im0_msh_reg[13]), - .R(sig_init_reg)); + sig_inhibit_rdy_n_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_inhibit_rdy_n_i_1_n_0), + .Q(\INFERRED_GEN.cnt_i_reg[0]_0 ), + .R(sig_stream_rst)); + LUT4 #( + .INIT(16'h0080)) + sig_init_done_i_1 + (.I0(sig_init_reg), + .I1(sig_init_reg2), + .I2(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I3(sig_init_done), + .O(sig_init_done_i_1_n_0)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_im0_msh_reg[14] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), - .D(\sig_addr_cntr_im0_msh_reg[12]_i_1_n_5 ), - .Q(sig_addr_cntr_im0_msh_reg[14]), - .R(sig_init_reg)); - FDRE #( + sig_init_done_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_init_done_i_1_n_0), + .Q(sig_init_done), + .R(1'b0)); + FDSE #( .INIT(1'b0)) - \sig_addr_cntr_im0_msh_reg[15] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), - .D(\sig_addr_cntr_im0_msh_reg[12]_i_1_n_4 ), - .Q(sig_addr_cntr_im0_msh_reg[15]), - .R(sig_init_reg)); + sig_init_reg2_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_init_reg), + .Q(sig_init_reg2), + .S(sig_stream_rst)); +endmodule + +(* ORIG_REF_NAME = "axi_datamover_fifo" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized8 + (\INFERRED_GEN.cnt_i_reg[1] , + SS, + \INCLUDE_PACKING.lsig_first_dbeat_reg , + \sig_byte_cntr_reg[0] , + sig_dre2ibtt_tlast, + sig_cmd_full_reg, + sig_cmd_empty_reg, + sig_good_tlast_dbeat37_out__0, + SR, + E, + Q, + sig_s_ready_dup4_reg, + \sig_byte_cntr_reg[7] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] , + sig_inhibit_rdy_n, + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] , + \GEN_INDET_BTT.lsig_absorb2tlast_reg , + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] , + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] , + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] , + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] , + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] , + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] , + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] , + sig_eop_sent, + \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg , + m_axi_s2mm_aclk, + sig_stream_rst, + sig_eop_sent_reg, + \INCLUDE_PACKING.lsig_first_dbeat_reg_0 , + sig_cmd_full, + sig_sm_ld_dre_cmd, + p_7_out, + sig_strm_tlast, + sig_m_valid_out_reg, + lsig_absorb2tlast, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_last_reg_out_reg, + sig_eop_halt_xfer, + sig_ibtt2dre_tready, + out, + sig_clr_dbc_reg, + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 , + slice_insert_valid, + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 , + p_0_in, + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 , + lsig_cmd_fetch_pause, + sig_need_cmd_flush, + sig_sm_pop_cmd_fifo, + in); + output \INFERRED_GEN.cnt_i_reg[1] ; + output [0:0]SS; + output \INCLUDE_PACKING.lsig_first_dbeat_reg ; + output \sig_byte_cntr_reg[0] ; + output sig_dre2ibtt_tlast; + output sig_cmd_full_reg; + output sig_cmd_empty_reg; + output sig_good_tlast_dbeat37_out__0; + output [0:0]SR; + output [0:0]E; + output [0:0]Q; + output sig_s_ready_dup4_reg; + output [0:0]\sig_byte_cntr_reg[7] ; + output \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ; + output \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] ; + output sig_inhibit_rdy_n; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] ; + output [0:0]\GEN_INDET_BTT.lsig_absorb2tlast_reg ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] ; + output sig_eop_sent; + output \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg ; + input m_axi_s2mm_aclk; + input sig_stream_rst; + input sig_eop_sent_reg; + input \INCLUDE_PACKING.lsig_first_dbeat_reg_0 ; + input sig_cmd_full; + input sig_sm_ld_dre_cmd; + input p_7_out; + input sig_strm_tlast; + input sig_m_valid_out_reg; + input lsig_absorb2tlast; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_last_reg_out_reg; + input sig_eop_halt_xfer; + input sig_ibtt2dre_tready; + input out; + input sig_clr_dbc_reg; + input [1:0]\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1] ; + input [1:0]\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ; + input slice_insert_valid; + input \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ; + input p_0_in; + input \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ; + input lsig_cmd_fetch_pause; + input sig_need_cmd_flush; + input sig_sm_pop_cmd_fifo; + input [1:0]in; + + wire [0:0]E; + wire \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg ; + wire [0:0]\GEN_INDET_BTT.lsig_absorb2tlast_reg ; + wire [1:0]\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ; + wire [1:0]\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ; + wire \INCLUDE_PACKING.lsig_first_dbeat_reg ; + wire \INCLUDE_PACKING.lsig_first_dbeat_reg_0 ; + wire \INFERRED_GEN.cnt_i_reg[1] ; + wire [0:0]Q; + wire [0:0]SR; + wire [0:0]SS; + wire [1:0]in; + wire lsig_absorb2tlast; + wire lsig_cmd_fetch_pause; + wire m_axi_s2mm_aclk; + wire out; + wire p_0_in; + wire p_7_out; + wire \sig_byte_cntr_reg[0] ; + wire [0:0]\sig_byte_cntr_reg[7] ; + wire sig_clr_dbc_reg; + wire sig_cmd_empty_reg; + wire sig_cmd_full; + wire sig_cmd_full_reg; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_dre2ibtt_tlast; + wire sig_eop_halt_xfer; + wire sig_eop_sent; + wire sig_eop_sent_reg; + wire sig_good_tlast_dbeat37_out__0; + wire sig_ibtt2dre_tready; + wire sig_inhibit_rdy_n; + wire sig_inhibit_rdy_n_i_1_n_0; + wire sig_init_done; + wire sig_init_done_i_1_n_0; + wire sig_init_reg; + wire sig_init_reg2; + wire sig_last_reg_out_reg; + wire sig_m_valid_out_reg; + wire sig_need_cmd_flush; + wire sig_s_ready_dup4_reg; + wire sig_sm_ld_dre_cmd; + wire sig_sm_pop_cmd_fifo; + wire sig_stream_rst; + wire sig_strm_tlast; + wire slice_insert_valid; + + Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized8 \USE_SRL_FIFO.I_SYNC_FIFO + (.E(E), + .\GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg (\GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg ), + .\GEN_INDET_BTT.lsig_absorb2tlast_reg (\GEN_INDET_BTT.lsig_absorb2tlast_reg ), + .\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1] (\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] (\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] (\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] (\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] (\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] (\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] (\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] (\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] (\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ), + .\INCLUDE_PACKING.lsig_first_dbeat_reg (\INCLUDE_PACKING.lsig_first_dbeat_reg ), + .\INCLUDE_PACKING.lsig_first_dbeat_reg_0 (\INCLUDE_PACKING.lsig_first_dbeat_reg_0 ), + .\INFERRED_GEN.cnt_i_reg[1] (\INFERRED_GEN.cnt_i_reg[1] ), + .\INFERRED_GEN.cnt_i_reg[4] (SS), + .Q(Q), + .SR(SR), + .in(in), + .lsig_absorb2tlast(lsig_absorb2tlast), + .lsig_cmd_fetch_pause(lsig_cmd_fetch_pause), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out), + .p_0_in(p_0_in), + .p_7_out(p_7_out), + .\sig_byte_cntr_reg[0] (\sig_byte_cntr_reg[0] ), + .\sig_byte_cntr_reg[7] (\sig_byte_cntr_reg[7] ), + .sig_clr_dbc_reg(sig_clr_dbc_reg), + .sig_cmd_empty_reg(sig_cmd_empty_reg), + .sig_cmd_full(sig_cmd_full), + .sig_cmd_full_reg(sig_cmd_full_reg), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_dre2ibtt_tlast(sig_dre2ibtt_tlast), + .sig_eop_halt_xfer(sig_eop_halt_xfer), + .sig_eop_sent(sig_eop_sent), + .sig_eop_sent_reg(sig_eop_sent_reg), + .sig_good_tlast_dbeat37_out__0(sig_good_tlast_dbeat37_out__0), + .sig_ibtt2dre_tready(sig_ibtt2dre_tready), + .sig_inhibit_rdy_n_reg(sig_inhibit_rdy_n), + .sig_last_reg_out_reg(sig_last_reg_out_reg), + .sig_m_valid_out_reg(sig_m_valid_out_reg), + .sig_need_cmd_flush(sig_need_cmd_flush), + .sig_s_ready_dup4_reg(sig_s_ready_dup4_reg), + .sig_sm_ld_dre_cmd(sig_sm_ld_dre_cmd), + .sig_sm_pop_cmd_fifo(sig_sm_pop_cmd_fifo), + .sig_strm_tlast(sig_strm_tlast), + .slice_insert_valid(slice_insert_valid)); + LUT2 #( + .INIT(4'hE)) + sig_inhibit_rdy_n_i_1 + (.I0(sig_init_done), + .I1(sig_inhibit_rdy_n), + .O(sig_inhibit_rdy_n_i_1_n_0)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_im0_msh_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), - .D(\sig_addr_cntr_im0_msh_reg[0]_i_2_n_6 ), - .Q(sig_addr_cntr_im0_msh_reg[1]), - .R(sig_init_reg)); + sig_inhibit_rdy_n_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_inhibit_rdy_n_i_1_n_0), + .Q(sig_inhibit_rdy_n), + .R(SS)); + LUT5 #( + .INIT(32'h00080000)) + sig_init_done_i_1 + (.I0(sig_init_reg), + .I1(sig_init_reg2), + .I2(sig_init_done), + .I3(sig_eop_sent_reg), + .I4(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .O(sig_init_done_i_1_n_0)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_im0_msh_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), - .D(\sig_addr_cntr_im0_msh_reg[0]_i_2_n_5 ), - .Q(sig_addr_cntr_im0_msh_reg[2]), - .R(sig_init_reg)); - FDRE #( + sig_init_done_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_init_done_i_1_n_0), + .Q(sig_init_done), + .R(1'b0)); + FDSE #( .INIT(1'b0)) - \sig_addr_cntr_im0_msh_reg[3] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), - .D(\sig_addr_cntr_im0_msh_reg[0]_i_2_n_4 ), - .Q(sig_addr_cntr_im0_msh_reg[3]), - .R(sig_init_reg)); - FDRE #( + sig_init_reg2_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_init_reg), + .Q(sig_init_reg2), + .S(SS)); + FDSE #( .INIT(1'b0)) - \sig_addr_cntr_im0_msh_reg[4] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), - .D(\sig_addr_cntr_im0_msh_reg[4]_i_1_n_7 ), - .Q(sig_addr_cntr_im0_msh_reg[4]), - .R(sig_init_reg)); - CARRY4 \sig_addr_cntr_im0_msh_reg[4]_i_1 - (.CI(\sig_addr_cntr_im0_msh_reg[0]_i_2_n_0 ), - .CO({\sig_addr_cntr_im0_msh_reg[4]_i_1_n_0 ,\sig_addr_cntr_im0_msh_reg[4]_i_1_n_1 ,\sig_addr_cntr_im0_msh_reg[4]_i_1_n_2 ,\sig_addr_cntr_im0_msh_reg[4]_i_1_n_3 }), - .CYINIT(1'b0), - .DI({1'b0,1'b0,1'b0,1'b0}), - .O({\sig_addr_cntr_im0_msh_reg[4]_i_1_n_4 ,\sig_addr_cntr_im0_msh_reg[4]_i_1_n_5 ,\sig_addr_cntr_im0_msh_reg[4]_i_1_n_6 ,\sig_addr_cntr_im0_msh_reg[4]_i_1_n_7 }), - .S({\sig_addr_cntr_im0_msh[4]_i_2_n_0 ,\sig_addr_cntr_im0_msh[4]_i_3_n_0 ,\sig_addr_cntr_im0_msh[4]_i_4_n_0 ,\sig_addr_cntr_im0_msh[4]_i_5_n_0 })); + sig_init_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_eop_sent_reg), + .Q(sig_init_reg), + .S(sig_stream_rst)); +endmodule + +(* ORIG_REF_NAME = "axi_datamover_fifo" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized9 + (\INFERRED_GEN.cnt_i_reg[0] , + sig_init_done, + p_0_in, + out, + sig_calc_error_reg_reg, + \INFERRED_GEN.cnt_i_reg[0]_0 , + sig_clr_cmd2addr_valid3_out__0, + sig_stream_rst, + m_axi_s2mm_aclk, + sig_init_reg_reg, + sig_halt_reg, + sig_addr_reg_empty_reg, + p_22_out, + in); + output \INFERRED_GEN.cnt_i_reg[0] ; + output sig_init_done; + output p_0_in; + output [41:0]out; + output sig_calc_error_reg_reg; + output \INFERRED_GEN.cnt_i_reg[0]_0 ; + output sig_clr_cmd2addr_valid3_out__0; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input sig_init_reg_reg; + input sig_halt_reg; + input sig_addr_reg_empty_reg; + input p_22_out; + input [39:0]in; + + wire \INFERRED_GEN.cnt_i_reg[0] ; + wire \INFERRED_GEN.cnt_i_reg[0]_0 ; + wire [39:0]in; + wire m_axi_s2mm_aclk; + wire [41:0]out; + wire p_0_in; + wire p_22_out; + wire sig_addr_reg_empty_reg; + wire sig_calc_error_reg_reg; + wire sig_clr_cmd2addr_valid3_out__0; + wire sig_halt_reg; + wire sig_inhibit_rdy_n_i_1_n_0; + wire sig_init_done; + wire sig_init_reg_reg; + wire sig_stream_rst; + + Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized9 \USE_SRL_FIFO.I_SYNC_FIFO + (.\INFERRED_GEN.cnt_i_reg[0] (\INFERRED_GEN.cnt_i_reg[0] ), + .in(in), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out), + .p_0_in(p_0_in), + .p_22_out(p_22_out), + .sig_addr_reg_empty_reg(sig_addr_reg_empty_reg), + .sig_calc_error_reg_reg(sig_calc_error_reg_reg), + .sig_clr_cmd2addr_valid3_out__0(sig_clr_cmd2addr_valid3_out__0), + .sig_halt_reg(sig_halt_reg), + .sig_inhibit_rdy_n_reg(\INFERRED_GEN.cnt_i_reg[0]_0 ), + .sig_stream_rst(sig_stream_rst)); + LUT2 #( + .INIT(4'hE)) + sig_inhibit_rdy_n_i_1 + (.I0(sig_init_done), + .I1(\INFERRED_GEN.cnt_i_reg[0]_0 ), + .O(sig_inhibit_rdy_n_i_1_n_0)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_im0_msh_reg[5] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), - .D(\sig_addr_cntr_im0_msh_reg[4]_i_1_n_6 ), - .Q(sig_addr_cntr_im0_msh_reg[5]), - .R(sig_init_reg)); + sig_inhibit_rdy_n_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_inhibit_rdy_n_i_1_n_0), + .Q(\INFERRED_GEN.cnt_i_reg[0]_0 ), + .R(sig_stream_rst)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_im0_msh_reg[6] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), - .D(\sig_addr_cntr_im0_msh_reg[4]_i_1_n_5 ), - .Q(sig_addr_cntr_im0_msh_reg[6]), - .R(sig_init_reg)); - FDRE #( - .INIT(1'b0)) - \sig_addr_cntr_im0_msh_reg[7] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), - .D(\sig_addr_cntr_im0_msh_reg[4]_i_1_n_4 ), - .Q(sig_addr_cntr_im0_msh_reg[7]), - .R(sig_init_reg)); - FDRE #( - .INIT(1'b0)) - \sig_addr_cntr_im0_msh_reg[8] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), - .D(\sig_addr_cntr_im0_msh_reg[8]_i_1_n_7 ), - .Q(sig_addr_cntr_im0_msh_reg[8]), - .R(sig_init_reg)); - CARRY4 \sig_addr_cntr_im0_msh_reg[8]_i_1 - (.CI(\sig_addr_cntr_im0_msh_reg[4]_i_1_n_0 ), - .CO({\sig_addr_cntr_im0_msh_reg[8]_i_1_n_0 ,\sig_addr_cntr_im0_msh_reg[8]_i_1_n_1 ,\sig_addr_cntr_im0_msh_reg[8]_i_1_n_2 ,\sig_addr_cntr_im0_msh_reg[8]_i_1_n_3 }), - .CYINIT(1'b0), - .DI({1'b0,1'b0,1'b0,1'b0}), - .O({\sig_addr_cntr_im0_msh_reg[8]_i_1_n_4 ,\sig_addr_cntr_im0_msh_reg[8]_i_1_n_5 ,\sig_addr_cntr_im0_msh_reg[8]_i_1_n_6 ,\sig_addr_cntr_im0_msh_reg[8]_i_1_n_7 }), - .S({\sig_addr_cntr_im0_msh[8]_i_2_n_0 ,\sig_addr_cntr_im0_msh[8]_i_3_n_0 ,\sig_addr_cntr_im0_msh[8]_i_4_n_0 ,\sig_addr_cntr_im0_msh[8]_i_5_n_0 })); - FDRE #( - .INIT(1'b0)) - \sig_addr_cntr_im0_msh_reg[9] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), - .D(\sig_addr_cntr_im0_msh_reg[8]_i_1_n_6 ), - .Q(sig_addr_cntr_im0_msh_reg[9]), - .R(sig_init_reg)); - (* SOFT_HLUTNM = "soft_lutpair84" *) - LUT4 #( - .INIT(16'hB888)) - \sig_addr_cntr_incr_ireg2[0]_i_1 - (.I0(sig_btt_residue_slice_im0[0]), - .I1(sig_btt_lt_b2mbaa_ireg1), - .I2(sig_first_xfer_im0), - .I3(sig_bytes_to_mbaa_ireg1[0]), - .O(\sig_addr_cntr_incr_ireg2[0]_i_1_n_0 )); - LUT4 #( - .INIT(16'hB888)) - \sig_addr_cntr_incr_ireg2[1]_i_1 - (.I0(sig_btt_residue_slice_im0[1]), - .I1(sig_btt_lt_b2mbaa_ireg1), - .I2(sig_first_xfer_im0), - .I3(sig_bytes_to_mbaa_ireg1[1]), - .O(\sig_addr_cntr_incr_ireg2[1]_i_1_n_0 )); - LUT4 #( - .INIT(16'hB888)) - \sig_addr_cntr_incr_ireg2[2]_i_1 - (.I0(sig_btt_residue_slice_im0[2]), - .I1(sig_btt_lt_b2mbaa_ireg1), - .I2(sig_first_xfer_im0), - .I3(sig_bytes_to_mbaa_ireg1[2]), - .O(\sig_addr_cntr_incr_ireg2[2]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair79" *) - LUT4 #( - .INIT(16'hB888)) - \sig_addr_cntr_incr_ireg2[3]_i_1 - (.I0(sig_btt_residue_slice_im0[3]), - .I1(sig_btt_lt_b2mbaa_ireg1), - .I2(sig_first_xfer_im0), - .I3(sig_bytes_to_mbaa_ireg1[3]), - .O(\sig_addr_cntr_incr_ireg2[3]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair80" *) - LUT4 #( - .INIT(16'hB888)) - \sig_addr_cntr_incr_ireg2[4]_i_1 - (.I0(sig_btt_residue_slice_im0[4]), - .I1(sig_btt_lt_b2mbaa_ireg1), - .I2(sig_first_xfer_im0), - .I3(sig_bytes_to_mbaa_ireg1[4]), - .O(\sig_addr_cntr_incr_ireg2[4]_i_1_n_0 )); - LUT4 #( - .INIT(16'hB888)) - \sig_addr_cntr_incr_ireg2[5]_i_1 - (.I0(sig_btt_residue_slice_im0[5]), - .I1(sig_btt_lt_b2mbaa_ireg1), - .I2(sig_first_xfer_im0), - .I3(sig_bytes_to_mbaa_ireg1[5]), - .O(\sig_addr_cntr_incr_ireg2[5]_i_1_n_0 )); - LUT4 #( - .INIT(16'hB888)) - \sig_addr_cntr_incr_ireg2[6]_i_1 - (.I0(sig_btt_residue_slice_im0[6]), - .I1(sig_btt_lt_b2mbaa_ireg1), - .I2(sig_first_xfer_im0), - .I3(sig_bytes_to_mbaa_ireg1[6]), - .O(\sig_addr_cntr_incr_ireg2[6]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair84" *) - LUT3 #( - .INIT(8'h0D)) - \sig_addr_cntr_incr_ireg2[7]_i_1 - (.I0(sig_first_xfer_im0), - .I1(sig_bytes_to_mbaa_ireg1[7]), - .I2(sig_btt_lt_b2mbaa_ireg1), - .O(\sig_addr_cntr_incr_ireg2[7]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \sig_addr_cntr_incr_ireg2_reg[0] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc2_reg), - .D(\sig_addr_cntr_incr_ireg2[0]_i_1_n_0 ), - .Q(sig_addr_cntr_incr_ireg2[0]), - .R(sig_init_reg)); - FDRE #( - .INIT(1'b0)) - \sig_addr_cntr_incr_ireg2_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc2_reg), - .D(\sig_addr_cntr_incr_ireg2[1]_i_1_n_0 ), - .Q(sig_addr_cntr_incr_ireg2[1]), - .R(sig_init_reg)); - FDRE #( - .INIT(1'b0)) - \sig_addr_cntr_incr_ireg2_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc2_reg), - .D(\sig_addr_cntr_incr_ireg2[2]_i_1_n_0 ), - .Q(sig_addr_cntr_incr_ireg2[2]), + sig_init_done_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_init_reg_reg), + .Q(sig_init_done), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "axi_datamover_ibttcc" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_ibttcc + (p_10_out, + p_32_out, + sig_psm_pop_input_cmd, + sig_csm_pop_child_cmd, + p_9_out_0, + sig_psm_halt, + sig_input_reg_empty, + in, + sig_next_cmd_cmplt_reg_reg, + sig_child_qual_error_reg, + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] , + sig_child_qual_first_of_2, + \sig_xfer_addr_reg_reg[2]_0 , + sig_adjusted_addr_incr, + p_22_out, + p_11_out, + \sig_child_addr_cntr_lsh_reg[3]_0 , + \sig_child_addr_cntr_lsh_reg[7]_0 , + sig_init_reg, + m_axi_s2mm_aclk, + SR, + sig_input_cache_type_reg0, + out, + sig_xfer_cmd_cmplt_reg0, + \gpr1.dout_i_reg[10] , + sig_psm_halt_reg_0, + O, + \gpr1.dout_i_reg[7] , + \gpr1.dout_i_reg[9] , + S, + \gpr1.dout_i_reg[7]_0 , + \gpr1.dout_i_reg[8] , + Q, + sig_csm_state_ns1, + sig_sf2pcc_xfer_valid, + sig_clr_cmd2addr_valid3_out__0, + sig_clr_cmd2data_valid4_out__0, + sig_inhibit_rdy_n, + FIFO_Full_reg, + CO, + \gpr1.dout_i_reg[8]_0 , + FIFO_Full_reg_0, + sig_inhibit_rdy_n_0, + FIFO_Full_reg_1, + sig_inhibit_rdy_n_1, + D); + output p_10_out; + output p_32_out; + output sig_psm_pop_input_cmd; + output sig_csm_pop_child_cmd; + output p_9_out_0; + output sig_psm_halt; + output sig_input_reg_empty; + output [39:0]in; + output [1:0]sig_next_cmd_cmplt_reg_reg; + output sig_child_qual_error_reg; + output [21:0]\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] ; + output sig_child_qual_first_of_2; + output [2:0]\sig_xfer_addr_reg_reg[2]_0 ; + output [8:0]sig_adjusted_addr_incr; + output p_22_out; + output p_11_out; + output [3:0]\sig_child_addr_cntr_lsh_reg[3]_0 ; + output [3:0]\sig_child_addr_cntr_lsh_reg[7]_0 ; + input sig_init_reg; + input m_axi_s2mm_aclk; + input [0:0]SR; + input sig_input_cache_type_reg0; + input [49:0]out; + input sig_xfer_cmd_cmplt_reg0; + input \gpr1.dout_i_reg[10] ; + input sig_psm_halt_reg_0; + input [3:0]O; + input [3:0]\gpr1.dout_i_reg[7] ; + input [9:0]\gpr1.dout_i_reg[9] ; + input [3:0]S; + input [3:0]\gpr1.dout_i_reg[7]_0 ; + input [0:0]\gpr1.dout_i_reg[8] ; + input [0:0]Q; + input sig_csm_state_ns1; + input sig_sf2pcc_xfer_valid; + input sig_clr_cmd2addr_valid3_out__0; + input sig_clr_cmd2data_valid4_out__0; + input sig_inhibit_rdy_n; + input FIFO_Full_reg; + input [0:0]CO; + input [0:0]\gpr1.dout_i_reg[8]_0 ; + input FIFO_Full_reg_0; + input sig_inhibit_rdy_n_0; + input FIFO_Full_reg_1; + input sig_inhibit_rdy_n_1; + input [2:0]D; + + wire [0:0]CO; + wire [2:0]D; + wire FIFO_Full_reg; + wire FIFO_Full_reg_0; + wire FIFO_Full_reg_1; + wire \FSM_sequential_sig_csm_state[0]_i_2_n_0 ; + wire \FSM_sequential_sig_csm_state[0]_i_3_n_0 ; + wire \FSM_sequential_sig_csm_state[1]_i_1_n_0 ; + wire \FSM_sequential_sig_csm_state[2]_i_1_n_0 ; + wire \FSM_sequential_sig_csm_state_reg[0]_i_1_n_0 ; + wire \FSM_sequential_sig_psm_state[0]_i_1_n_0 ; + wire \FSM_sequential_sig_psm_state[0]_i_2_n_0 ; + wire \FSM_sequential_sig_psm_state[1]_i_1_n_0 ; + wire \FSM_sequential_sig_psm_state[2]_i_1_n_0 ; + wire \FSM_sequential_sig_psm_state[2]_i_3_n_0 ; + wire [21:0]\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] ; + wire [3:0]O; + wire [0:0]Q; + wire [3:0]S; + wire [0:0]SR; + wire [15:0]data; + wire \gpr1.dout_i_reg[10] ; + wire [3:0]\gpr1.dout_i_reg[7] ; + wire [3:0]\gpr1.dout_i_reg[7]_0 ; + wire [0:0]\gpr1.dout_i_reg[8] ; + wire [0:0]\gpr1.dout_i_reg[8]_0 ; + wire [9:0]\gpr1.dout_i_reg[9] ; + wire [39:0]in; + wire m_axi_s2mm_aclk; + wire [49:0]out; + wire p_10_out; + wire p_11_out; + wire p_1_in; + wire [15:0]p_1_in__0; + wire p_22_out; + wire p_32_out; + wire p_9_out_0; + wire [6:0]sel0; + wire sig_addr_aligned__6; + wire [8:0]sig_adjusted_addr_incr; + wire [15:0]sig_btt_cntr0; + wire sig_btt_cntr0_carry__0_i_1_n_0; + wire sig_btt_cntr0_carry__0_i_2_n_0; + wire sig_btt_cntr0_carry__0_i_3_n_0; + wire sig_btt_cntr0_carry__0_i_4_n_0; + wire sig_btt_cntr0_carry__0_n_0; + wire sig_btt_cntr0_carry__0_n_1; + wire sig_btt_cntr0_carry__0_n_2; + wire sig_btt_cntr0_carry__0_n_3; + wire sig_btt_cntr0_carry__1_i_1_n_0; + wire sig_btt_cntr0_carry__1_i_2_n_0; + wire sig_btt_cntr0_carry__1_i_3_n_0; + wire sig_btt_cntr0_carry__1_i_4_n_0; + wire sig_btt_cntr0_carry__1_n_0; + wire sig_btt_cntr0_carry__1_n_1; + wire sig_btt_cntr0_carry__1_n_2; + wire sig_btt_cntr0_carry__1_n_3; + wire sig_btt_cntr0_carry__2_i_1_n_0; + wire sig_btt_cntr0_carry__2_i_2_n_0; + wire sig_btt_cntr0_carry__2_i_3_n_0; + wire sig_btt_cntr0_carry__2_i_4_n_0; + wire sig_btt_cntr0_carry__2_n_1; + wire sig_btt_cntr0_carry__2_n_2; + wire sig_btt_cntr0_carry__2_n_3; + wire sig_btt_cntr0_carry_i_1_n_0; + wire sig_btt_cntr0_carry_i_2_n_0; + wire sig_btt_cntr0_carry_i_3_n_0; + wire sig_btt_cntr0_carry_i_4_n_0; + wire sig_btt_cntr0_carry_n_0; + wire sig_btt_cntr0_carry_n_1; + wire sig_btt_cntr0_carry_n_2; + wire sig_btt_cntr0_carry_n_3; + wire \sig_btt_cntr[15]_i_1_n_0 ; + wire sig_btt_eq_b2mbaa2; + wire sig_btt_eq_b2mbaa2_carry_i_1_n_0; + wire sig_btt_eq_b2mbaa2_carry_i_2_n_0; + wire sig_btt_eq_b2mbaa2_carry_i_3_n_0; + wire sig_btt_eq_b2mbaa2_carry_n_2; + wire sig_btt_eq_b2mbaa2_carry_n_3; + wire sig_btt_lt_b2mbaa2; + wire sig_btt_lt_b2mbaa2_carry__0_i_1_n_0; + wire sig_btt_lt_b2mbaa2_carry__0_i_2_n_0; + wire sig_btt_lt_b2mbaa2_carry_i_10_n_0; + wire sig_btt_lt_b2mbaa2_carry_i_1_n_0; + wire sig_btt_lt_b2mbaa2_carry_i_2_n_0; + wire sig_btt_lt_b2mbaa2_carry_i_3_n_0; + wire sig_btt_lt_b2mbaa2_carry_i_4_n_0; + wire sig_btt_lt_b2mbaa2_carry_i_5_n_0; + wire sig_btt_lt_b2mbaa2_carry_i_6_n_0; + wire sig_btt_lt_b2mbaa2_carry_i_7_n_0; + wire sig_btt_lt_b2mbaa2_carry_i_8_n_0; + wire sig_btt_lt_b2mbaa2_carry_i_9_n_0; + wire sig_btt_lt_b2mbaa2_carry_n_0; + wire sig_btt_lt_b2mbaa2_carry_n_1; + wire sig_btt_lt_b2mbaa2_carry_n_2; + wire sig_btt_lt_b2mbaa2_carry_n_3; + wire [8:0]sig_btt_residue_slice; + wire sig_byte_change_minus1_carry__0_n_0; + wire sig_byte_change_minus1_carry__0_n_1; + wire sig_byte_change_minus1_carry__0_n_2; + wire sig_byte_change_minus1_carry__0_n_3; + wire sig_byte_change_minus1_carry_n_0; + wire sig_byte_change_minus1_carry_n_1; + wire sig_byte_change_minus1_carry_n_2; + wire sig_byte_change_minus1_carry_n_3; + wire [8:8]sig_bytes_to_mbaa; + wire [7:0]sig_bytes_to_mbaa__8; + wire \sig_child_addr_cntr_lsh[0]_i_1_n_0 ; + wire \sig_child_addr_cntr_lsh[12]_i_2_n_0 ; + wire \sig_child_addr_cntr_lsh[12]_i_3_n_0 ; + wire \sig_child_addr_cntr_lsh[12]_i_4_n_0 ; + wire \sig_child_addr_cntr_lsh[12]_i_5_n_0 ; + wire \sig_child_addr_cntr_lsh[8]_i_3_n_0 ; + wire \sig_child_addr_cntr_lsh[8]_i_4_n_0 ; + wire \sig_child_addr_cntr_lsh[8]_i_5_n_0 ; + wire \sig_child_addr_cntr_lsh[8]_i_6_n_0 ; + wire [14:3]sig_child_addr_cntr_lsh_reg; + wire \sig_child_addr_cntr_lsh_reg[12]_i_1_n_1 ; + wire \sig_child_addr_cntr_lsh_reg[12]_i_1_n_2 ; + wire \sig_child_addr_cntr_lsh_reg[12]_i_1_n_3 ; + wire \sig_child_addr_cntr_lsh_reg[12]_i_1_n_4 ; + wire \sig_child_addr_cntr_lsh_reg[12]_i_1_n_5 ; + wire \sig_child_addr_cntr_lsh_reg[12]_i_1_n_6 ; + wire \sig_child_addr_cntr_lsh_reg[12]_i_1_n_7 ; + wire [3:0]\sig_child_addr_cntr_lsh_reg[3]_0 ; + wire [3:0]\sig_child_addr_cntr_lsh_reg[7]_0 ; + wire \sig_child_addr_cntr_lsh_reg[8]_i_1_n_0 ; + wire \sig_child_addr_cntr_lsh_reg[8]_i_1_n_1 ; + wire \sig_child_addr_cntr_lsh_reg[8]_i_1_n_2 ; + wire \sig_child_addr_cntr_lsh_reg[8]_i_1_n_3 ; + wire \sig_child_addr_cntr_lsh_reg[8]_i_1_n_4 ; + wire \sig_child_addr_cntr_lsh_reg[8]_i_1_n_5 ; + wire \sig_child_addr_cntr_lsh_reg[8]_i_1_n_6 ; + wire \sig_child_addr_cntr_lsh_reg[8]_i_1_n_7 ; + wire \sig_child_addr_cntr_msh[0]_i_1_n_0 ; + wire \sig_child_addr_cntr_msh[0]_i_3_n_0 ; + wire \sig_child_addr_cntr_msh[0]_i_4_n_0 ; + wire \sig_child_addr_cntr_msh[0]_i_5_n_0 ; + wire \sig_child_addr_cntr_msh[0]_i_6_n_0 ; + wire \sig_child_addr_cntr_msh[0]_i_7_n_0 ; + wire \sig_child_addr_cntr_msh[12]_i_2_n_0 ; + wire \sig_child_addr_cntr_msh[12]_i_3_n_0 ; + wire \sig_child_addr_cntr_msh[12]_i_4_n_0 ; + wire \sig_child_addr_cntr_msh[12]_i_5_n_0 ; + wire \sig_child_addr_cntr_msh[4]_i_2_n_0 ; + wire \sig_child_addr_cntr_msh[4]_i_3_n_0 ; + wire \sig_child_addr_cntr_msh[4]_i_4_n_0 ; + wire \sig_child_addr_cntr_msh[4]_i_5_n_0 ; + wire \sig_child_addr_cntr_msh[8]_i_2_n_0 ; + wire \sig_child_addr_cntr_msh[8]_i_3_n_0 ; + wire \sig_child_addr_cntr_msh[8]_i_4_n_0 ; + wire \sig_child_addr_cntr_msh[8]_i_5_n_0 ; + wire [15:0]sig_child_addr_cntr_msh_reg; + wire \sig_child_addr_cntr_msh_reg[0]_i_2_n_0 ; + wire \sig_child_addr_cntr_msh_reg[0]_i_2_n_1 ; + wire \sig_child_addr_cntr_msh_reg[0]_i_2_n_2 ; + wire \sig_child_addr_cntr_msh_reg[0]_i_2_n_3 ; + wire \sig_child_addr_cntr_msh_reg[0]_i_2_n_4 ; + wire \sig_child_addr_cntr_msh_reg[0]_i_2_n_5 ; + wire \sig_child_addr_cntr_msh_reg[0]_i_2_n_6 ; + wire \sig_child_addr_cntr_msh_reg[0]_i_2_n_7 ; + wire \sig_child_addr_cntr_msh_reg[12]_i_1_n_1 ; + wire \sig_child_addr_cntr_msh_reg[12]_i_1_n_2 ; + wire \sig_child_addr_cntr_msh_reg[12]_i_1_n_3 ; + wire \sig_child_addr_cntr_msh_reg[12]_i_1_n_4 ; + wire \sig_child_addr_cntr_msh_reg[12]_i_1_n_5 ; + wire \sig_child_addr_cntr_msh_reg[12]_i_1_n_6 ; + wire \sig_child_addr_cntr_msh_reg[12]_i_1_n_7 ; + wire \sig_child_addr_cntr_msh_reg[4]_i_1_n_0 ; + wire \sig_child_addr_cntr_msh_reg[4]_i_1_n_1 ; + wire \sig_child_addr_cntr_msh_reg[4]_i_1_n_2 ; + wire \sig_child_addr_cntr_msh_reg[4]_i_1_n_3 ; + wire \sig_child_addr_cntr_msh_reg[4]_i_1_n_4 ; + wire \sig_child_addr_cntr_msh_reg[4]_i_1_n_5 ; + wire \sig_child_addr_cntr_msh_reg[4]_i_1_n_6 ; + wire \sig_child_addr_cntr_msh_reg[4]_i_1_n_7 ; + wire \sig_child_addr_cntr_msh_reg[8]_i_1_n_0 ; + wire \sig_child_addr_cntr_msh_reg[8]_i_1_n_1 ; + wire \sig_child_addr_cntr_msh_reg[8]_i_1_n_2 ; + wire \sig_child_addr_cntr_msh_reg[8]_i_1_n_3 ; + wire \sig_child_addr_cntr_msh_reg[8]_i_1_n_4 ; + wire \sig_child_addr_cntr_msh_reg[8]_i_1_n_5 ; + wire \sig_child_addr_cntr_msh_reg[8]_i_1_n_6 ; + wire \sig_child_addr_cntr_msh_reg[8]_i_1_n_7 ; + wire sig_child_addr_lsh_rollover_reg; + wire sig_child_addr_lsh_rollover_reg_i_10_n_0; + wire sig_child_addr_lsh_rollover_reg_i_11_n_0; + wire sig_child_addr_lsh_rollover_reg_i_12_n_0; + wire sig_child_addr_lsh_rollover_reg_i_14_n_0; + wire sig_child_addr_lsh_rollover_reg_i_15_n_0; + wire sig_child_addr_lsh_rollover_reg_i_16_n_0; + wire sig_child_addr_lsh_rollover_reg_i_17_n_0; + wire sig_child_addr_lsh_rollover_reg_i_18_n_0; + wire sig_child_addr_lsh_rollover_reg_i_19_n_0; + wire sig_child_addr_lsh_rollover_reg_i_1_n_0; + wire sig_child_addr_lsh_rollover_reg_i_20_n_0; + wire sig_child_addr_lsh_rollover_reg_i_21_n_0; + wire sig_child_addr_lsh_rollover_reg_i_4_n_0; + wire sig_child_addr_lsh_rollover_reg_i_5_n_0; + wire sig_child_addr_lsh_rollover_reg_i_6_n_0; + wire sig_child_addr_lsh_rollover_reg_i_7_n_0; + wire sig_child_addr_lsh_rollover_reg_i_9_n_0; + wire sig_child_addr_lsh_rollover_reg_reg_i_13_n_0; + wire sig_child_addr_lsh_rollover_reg_reg_i_13_n_1; + wire sig_child_addr_lsh_rollover_reg_reg_i_13_n_2; + wire sig_child_addr_lsh_rollover_reg_reg_i_13_n_3; + wire sig_child_addr_lsh_rollover_reg_reg_i_2_n_1; + wire sig_child_addr_lsh_rollover_reg_reg_i_2_n_2; + wire sig_child_addr_lsh_rollover_reg_reg_i_2_n_3; + wire sig_child_addr_lsh_rollover_reg_reg_i_3_n_0; + wire sig_child_addr_lsh_rollover_reg_reg_i_3_n_1; + wire sig_child_addr_lsh_rollover_reg_reg_i_3_n_2; + wire sig_child_addr_lsh_rollover_reg_reg_i_3_n_3; + wire sig_child_addr_lsh_rollover_reg_reg_i_8_n_0; + wire sig_child_addr_lsh_rollover_reg_reg_i_8_n_1; + wire sig_child_addr_lsh_rollover_reg_reg_i_8_n_2; + wire sig_child_addr_lsh_rollover_reg_reg_i_8_n_3; + wire \sig_child_addr_reg_reg_n_0_[0] ; + wire \sig_child_addr_reg_reg_n_0_[10] ; + wire \sig_child_addr_reg_reg_n_0_[11] ; + wire \sig_child_addr_reg_reg_n_0_[12] ; + wire \sig_child_addr_reg_reg_n_0_[13] ; + wire \sig_child_addr_reg_reg_n_0_[14] ; + wire \sig_child_addr_reg_reg_n_0_[15] ; + wire \sig_child_addr_reg_reg_n_0_[1] ; + wire \sig_child_addr_reg_reg_n_0_[2] ; + wire \sig_child_addr_reg_reg_n_0_[3] ; + wire \sig_child_addr_reg_reg_n_0_[4] ; + wire \sig_child_addr_reg_reg_n_0_[5] ; + wire \sig_child_addr_reg_reg_n_0_[6] ; + wire \sig_child_addr_reg_reg_n_0_[7] ; + wire \sig_child_addr_reg_reg_n_0_[8] ; + wire \sig_child_addr_reg_reg_n_0_[9] ; + wire sig_child_burst_type_reg; + wire sig_child_cmd_reg_full; + wire sig_child_error_reg; + wire sig_child_qual_burst_type; + wire sig_child_qual_burst_type_i_1_n_0; + wire sig_child_qual_error_reg; + wire sig_child_qual_error_reg_i_1_n_0; + wire sig_child_qual_first_of_2; + wire sig_child_qual_first_of_2_i_1_n_0; + wire sig_clr_cmd2addr_valid3_out__0; + wire sig_clr_cmd2data_valid4_out__0; + wire sig_cmd2addr_valid_i_1_n_0; + wire sig_cmd2data_valid_i_1_n_0; + wire sig_csm_ld_xfer; + wire sig_csm_ld_xfer_ns; + wire sig_csm_pop_child_cmd; + wire sig_csm_pop_child_cmd_ns; + wire sig_csm_pop_sf_fifo_ns; + (* RTL_KEEP = "yes" *) wire [2:0]sig_csm_state; + wire sig_csm_state_ns1; + wire sig_csm_state_ns18_out; + wire sig_first_realigner_cmd; + wire sig_first_realigner_cmd_i_1_n_0; + wire sig_inhibit_rdy_n; + wire sig_inhibit_rdy_n_0; + wire sig_inhibit_rdy_n_1; + wire sig_init_reg; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire [31:0]sig_input_addr_reg; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire [31:0]sig_input_addr_reg1; + wire \sig_input_addr_reg[31]_i_2_n_0 ; + wire sig_input_burst_type_reg; + wire sig_input_cache_type_reg0; + wire sig_input_eof_reg; + wire sig_input_reg_empty; + wire sig_needed_2_realign_cmds; + wire sig_needed_2_realign_cmds_i_1_n_0; + wire [1:0]sig_next_cmd_cmplt_reg_reg; + wire [15:15]sig_predict_child_addr_lsh; + wire sig_psm_halt; + wire sig_psm_halt_ns; + wire sig_psm_halt_reg_0; + wire sig_psm_ld_calc1; + wire sig_psm_ld_calc1_ns; + wire sig_psm_ld_chcmd_reg; + wire sig_psm_ld_chcmd_reg_ns; + wire sig_psm_ld_realigner_reg; + wire sig_psm_ld_realigner_reg_ns; + wire sig_psm_pop_input_cmd; + wire sig_psm_pop_input_cmd_i_2_n_0; + wire sig_psm_pop_input_cmd_ns; + (* RTL_KEEP = "yes" *) wire [2:0]sig_psm_state; + wire sig_psm_state_ns2__0; + wire sig_realign_cmd_cmplt_reg_i_1_n_0; + wire sig_realign_eof_reg0; + wire sig_realign_reg_empty; + wire [2:0]sig_realign_strt_offset; + wire sig_realign_tag_reg0; + wire [15:0]sig_realigner_btt; + wire [15:0]sig_realigner_btt2; + wire \sig_realigner_btt2[15]_i_1_n_0 ; + wire \sig_realigner_btt2[15]_i_4_n_0 ; + wire \sig_realigner_btt2[15]_i_5_n_0 ; + wire \sig_realigner_btt2[2]_i_3_n_0 ; + wire \sig_realigner_btt2[5]_i_3_n_0 ; + wire \sig_realigner_btt2[8]_i_3_n_0 ; + wire sig_sf2pcc_xfer_valid; + wire sig_skip_align2mbaa; + wire sig_skip_align2mbaa_s_h; + wire sig_skip_align2mbaa_s_h_i_1_n_0; + wire [2:0]\sig_xfer_addr_reg_reg[2]_0 ; + wire sig_xfer_cache_reg0; + wire sig_xfer_cmd_cmplt_reg0; + wire \sig_xfer_len_reg[0]_i_1_n_0 ; + wire \sig_xfer_len_reg[1]_i_1_n_0 ; + wire \sig_xfer_len_reg[2]_i_1_n_0 ; + wire [3:3]NLW_sig_btt_cntr0_carry__2_CO_UNCONNECTED; + wire [3:3]NLW_sig_btt_eq_b2mbaa2_carry_CO_UNCONNECTED; + wire [3:0]NLW_sig_btt_eq_b2mbaa2_carry_O_UNCONNECTED; + wire [3:0]NLW_sig_btt_lt_b2mbaa2_carry_O_UNCONNECTED; + wire [3:1]NLW_sig_btt_lt_b2mbaa2_carry__0_CO_UNCONNECTED; + wire [3:0]NLW_sig_btt_lt_b2mbaa2_carry__0_O_UNCONNECTED; + wire [3:0]NLW_sig_byte_change_minus1_carry__1_CO_UNCONNECTED; + wire [3:1]NLW_sig_byte_change_minus1_carry__1_O_UNCONNECTED; + wire [3:3]\NLW_sig_child_addr_cntr_lsh_reg[12]_i_1_CO_UNCONNECTED ; + wire [3:3]\NLW_sig_child_addr_cntr_msh_reg[12]_i_1_CO_UNCONNECTED ; + wire [3:0]NLW_sig_child_addr_lsh_rollover_reg_reg_i_13_O_UNCONNECTED; + wire [3:3]NLW_sig_child_addr_lsh_rollover_reg_reg_i_2_CO_UNCONNECTED; + wire [2:0]NLW_sig_child_addr_lsh_rollover_reg_reg_i_2_O_UNCONNECTED; + wire [3:0]NLW_sig_child_addr_lsh_rollover_reg_reg_i_3_O_UNCONNECTED; + wire [3:0]NLW_sig_child_addr_lsh_rollover_reg_reg_i_8_O_UNCONNECTED; + + LUT5 #( + .INIT(32'hF0FF1F1F)) + \FSM_sequential_sig_csm_state[0]_i_2 + (.I0(p_11_out), + .I1(p_22_out), + .I2(sig_csm_state[1]), + .I3(sig_child_cmd_reg_full), + .I4(sig_csm_state[0]), + .O(\FSM_sequential_sig_csm_state[0]_i_2_n_0 )); + LUT6 #( + .INIT(64'h3330BBBB33308888)) + \FSM_sequential_sig_csm_state[0]_i_3 + (.I0(sig_csm_state_ns1), + .I1(sig_csm_state[1]), + .I2(p_11_out), + .I3(p_22_out), + .I4(sig_csm_state[0]), + .I5(sig_sf2pcc_xfer_valid), + .O(\FSM_sequential_sig_csm_state[0]_i_3_n_0 )); + LUT6 #( + .INIT(64'h33333333B0808080)) + \FSM_sequential_sig_csm_state[1]_i_1 + (.I0(sig_csm_state_ns18_out), + .I1(sig_csm_state[2]), + .I2(sig_csm_state[0]), + .I3(sig_child_cmd_reg_full), + .I4(sig_child_error_reg), + .I5(sig_csm_state[1]), + .O(\FSM_sequential_sig_csm_state[1]_i_1_n_0 )); + LUT2 #( + .INIT(4'h1)) + \FSM_sequential_sig_csm_state[1]_i_2 + (.I0(p_22_out), + .I1(p_11_out), + .O(sig_csm_state_ns18_out)); + LUT6 #( + .INIT(64'h04040404CCFCCCCC)) + \FSM_sequential_sig_csm_state[2]_i_1 + (.I0(sig_csm_state_ns1), + .I1(sig_csm_state[2]), + .I2(sig_csm_state[0]), + .I3(sig_child_error_reg), + .I4(sig_child_cmd_reg_full), + .I5(sig_csm_state[1]), + .O(\FSM_sequential_sig_csm_state[2]_i_1_n_0 )); + (* KEEP = "yes" *) + FDRE \FSM_sequential_sig_csm_state_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\FSM_sequential_sig_csm_state_reg[0]_i_1_n_0 ), + .Q(sig_csm_state[0]), .R(sig_init_reg)); - FDRE #( - .INIT(1'b0)) - \sig_addr_cntr_incr_ireg2_reg[3] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc2_reg), - .D(\sig_addr_cntr_incr_ireg2[3]_i_1_n_0 ), - .Q(sig_addr_cntr_incr_ireg2[3]), + MUXF7 \FSM_sequential_sig_csm_state_reg[0]_i_1 + (.I0(\FSM_sequential_sig_csm_state[0]_i_2_n_0 ), + .I1(\FSM_sequential_sig_csm_state[0]_i_3_n_0 ), + .O(\FSM_sequential_sig_csm_state_reg[0]_i_1_n_0 ), + .S(sig_csm_state[2])); + (* KEEP = "yes" *) + FDRE \FSM_sequential_sig_csm_state_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\FSM_sequential_sig_csm_state[1]_i_1_n_0 ), + .Q(sig_csm_state[1]), .R(sig_init_reg)); - FDRE #( - .INIT(1'b0)) - \sig_addr_cntr_incr_ireg2_reg[4] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc2_reg), - .D(\sig_addr_cntr_incr_ireg2[4]_i_1_n_0 ), - .Q(sig_addr_cntr_incr_ireg2[4]), + (* KEEP = "yes" *) + FDRE \FSM_sequential_sig_csm_state_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\FSM_sequential_sig_csm_state[2]_i_1_n_0 ), + .Q(sig_csm_state[2]), .R(sig_init_reg)); - FDRE #( - .INIT(1'b0)) - \sig_addr_cntr_incr_ireg2_reg[5] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc2_reg), - .D(\sig_addr_cntr_incr_ireg2[5]_i_1_n_0 ), - .Q(sig_addr_cntr_incr_ireg2[5]), + LUT5 #( + .INIT(32'h11114151)) + \FSM_sequential_sig_psm_state[0]_i_1 + (.I0(\FSM_sequential_sig_psm_state[0]_i_2_n_0 ), + .I1(sig_psm_state[2]), + .I2(sig_psm_state[0]), + .I3(\sig_input_addr_reg[31]_i_2_n_0 ), + .I4(sig_psm_state[1]), + .O(\FSM_sequential_sig_psm_state[0]_i_1_n_0 )); + LUT5 #( + .INIT(32'h30550000)) + \FSM_sequential_sig_psm_state[0]_i_2 + (.I0(sig_realign_reg_empty), + .I1(sig_child_cmd_reg_full), + .I2(p_10_out), + .I3(sig_psm_state[0]), + .I4(sig_psm_state[1]), + .O(\FSM_sequential_sig_psm_state[0]_i_2_n_0 )); + LUT5 #( + .INIT(32'h45504050)) + \FSM_sequential_sig_psm_state[1]_i_1 + (.I0(sig_psm_state[2]), + .I1(sig_child_cmd_reg_full), + .I2(sig_psm_state[1]), + .I3(sig_psm_state[0]), + .I4(\sig_input_addr_reg[31]_i_2_n_0 ), + .O(\FSM_sequential_sig_psm_state[1]_i_1_n_0 )); + LUT5 #( + .INIT(32'hFF1F0000)) + \FSM_sequential_sig_psm_state[2]_i_1 + (.I0(sig_psm_state_ns2__0), + .I1(sig_skip_align2mbaa_s_h), + .I2(sig_psm_state[1]), + .I3(p_10_out), + .I4(\FSM_sequential_sig_psm_state[2]_i_3_n_0 ), + .O(\FSM_sequential_sig_psm_state[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEAA00000000)) + \FSM_sequential_sig_psm_state[2]_i_2 + (.I0(p_10_out), + .I1(sig_btt_eq_b2mbaa2), + .I2(sig_btt_lt_b2mbaa2), + .I3(\sig_realigner_btt2[15]_i_4_n_0 ), + .I4(sig_addr_aligned__6), + .I5(sig_first_realigner_cmd), + .O(sig_psm_state_ns2__0)); + LUT5 #( + .INIT(32'h04303430)) + \FSM_sequential_sig_psm_state[2]_i_3 + (.I0(sig_child_cmd_reg_full), + .I1(sig_psm_state[1]), + .I2(sig_psm_state[2]), + .I3(sig_psm_state[0]), + .I4(sig_realign_reg_empty), + .O(\FSM_sequential_sig_psm_state[2]_i_3_n_0 )); + (* KEEP = "yes" *) + FDRE \FSM_sequential_sig_psm_state_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\FSM_sequential_sig_psm_state[0]_i_1_n_0 ), + .Q(sig_psm_state[0]), .R(sig_init_reg)); - FDRE #( - .INIT(1'b0)) - \sig_addr_cntr_incr_ireg2_reg[6] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc2_reg), - .D(\sig_addr_cntr_incr_ireg2[6]_i_1_n_0 ), - .Q(sig_addr_cntr_incr_ireg2[6]), + (* KEEP = "yes" *) + FDRE \FSM_sequential_sig_psm_state_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\FSM_sequential_sig_psm_state[1]_i_1_n_0 ), + .Q(sig_psm_state[1]), .R(sig_init_reg)); - FDRE #( - .INIT(1'b0)) - \sig_addr_cntr_incr_ireg2_reg[7] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc2_reg), - .D(\sig_addr_cntr_incr_ireg2[7]_i_1_n_0 ), - .Q(sig_addr_cntr_incr_ireg2[7]), + (* KEEP = "yes" *) + FDRE \FSM_sequential_sig_psm_state_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\FSM_sequential_sig_psm_state[2]_i_1_n_0 ), + .Q(sig_psm_state[2]), .R(sig_init_reg)); + LUT1 #( + .INIT(2'h2)) + i_0 + (.I0(1'b0), + .O(sig_input_addr_reg1[31])); + LUT1 #( + .INIT(2'h2)) + i_1 + (.I0(1'b0), + .O(sig_input_addr_reg1[30])); + LUT1 #( + .INIT(2'h2)) + i_10 + (.I0(1'b0), + .O(sig_input_addr_reg1[21])); + LUT1 #( + .INIT(2'h2)) + i_11 + (.I0(1'b0), + .O(sig_input_addr_reg1[20])); + LUT1 #( + .INIT(2'h2)) + i_12 + (.I0(1'b0), + .O(sig_input_addr_reg1[19])); + LUT1 #( + .INIT(2'h2)) + i_13 + (.I0(1'b0), + .O(sig_input_addr_reg1[18])); + LUT1 #( + .INIT(2'h2)) + i_14 + (.I0(1'b0), + .O(sig_input_addr_reg1[17])); + LUT1 #( + .INIT(2'h2)) + i_15 + (.I0(1'b0), + .O(sig_input_addr_reg1[16])); + LUT1 #( + .INIT(2'h2)) + i_16 + (.I0(1'b0), + .O(sig_input_addr_reg1[15])); + LUT1 #( + .INIT(2'h2)) + i_17 + (.I0(1'b0), + .O(sig_input_addr_reg1[14])); + LUT1 #( + .INIT(2'h2)) + i_18 + (.I0(1'b0), + .O(sig_input_addr_reg1[13])); + LUT1 #( + .INIT(2'h2)) + i_19 + (.I0(1'b0), + .O(sig_input_addr_reg1[12])); + LUT1 #( + .INIT(2'h2)) + i_2 + (.I0(1'b0), + .O(sig_input_addr_reg1[29])); + LUT1 #( + .INIT(2'h2)) + i_20 + (.I0(1'b0), + .O(sig_input_addr_reg1[11])); + LUT1 #( + .INIT(2'h2)) + i_21 + (.I0(1'b0), + .O(sig_input_addr_reg1[10])); + LUT1 #( + .INIT(2'h2)) + i_22 + (.I0(1'b0), + .O(sig_input_addr_reg1[9])); + LUT1 #( + .INIT(2'h2)) + i_23 + (.I0(1'b0), + .O(sig_input_addr_reg1[8])); + LUT1 #( + .INIT(2'h2)) + i_24 + (.I0(1'b0), + .O(sig_input_addr_reg1[7])); + LUT1 #( + .INIT(2'h2)) + i_25 + (.I0(1'b0), + .O(sig_input_addr_reg1[6])); + LUT1 #( + .INIT(2'h2)) + i_26 + (.I0(1'b0), + .O(sig_input_addr_reg1[5])); + LUT1 #( + .INIT(2'h2)) + i_27 + (.I0(1'b0), + .O(sig_input_addr_reg1[4])); + LUT1 #( + .INIT(2'h2)) + i_28 + (.I0(1'b0), + .O(sig_input_addr_reg1[3])); + LUT1 #( + .INIT(2'h2)) + i_29 + (.I0(1'b0), + .O(sig_input_addr_reg1[2])); + LUT1 #( + .INIT(2'h2)) + i_3 + (.I0(1'b0), + .O(sig_input_addr_reg1[28])); + LUT1 #( + .INIT(2'h2)) + i_30 + (.I0(1'b0), + .O(sig_input_addr_reg1[1])); + LUT1 #( + .INIT(2'h2)) + i_31 + (.I0(1'b0), + .O(sig_input_addr_reg1[0])); + LUT1 #( + .INIT(2'h2)) + i_4 + (.I0(1'b0), + .O(sig_input_addr_reg1[27])); + LUT1 #( + .INIT(2'h2)) + i_5 + (.I0(1'b0), + .O(sig_input_addr_reg1[26])); + LUT1 #( + .INIT(2'h2)) + i_6 + (.I0(1'b0), + .O(sig_input_addr_reg1[25])); + LUT1 #( + .INIT(2'h2)) + i_7 + (.I0(1'b0), + .O(sig_input_addr_reg1[24])); + LUT1 #( + .INIT(2'h2)) + i_8 + (.I0(1'b0), + .O(sig_input_addr_reg1[23])); + LUT1 #( + .INIT(2'h2)) + i_9 + (.I0(1'b0), + .O(sig_input_addr_reg1[22])); + CARRY4 sig_btt_cntr0_carry + (.CI(1'b0), + .CO({sig_btt_cntr0_carry_n_0,sig_btt_cntr0_carry_n_1,sig_btt_cntr0_carry_n_2,sig_btt_cntr0_carry_n_3}), + .CYINIT(1'b1), + .DI(sig_btt_residue_slice[3:0]), + .O(sig_btt_cntr0[3:0]), + .S({sig_btt_cntr0_carry_i_1_n_0,sig_btt_cntr0_carry_i_2_n_0,sig_btt_cntr0_carry_i_3_n_0,sig_btt_cntr0_carry_i_4_n_0})); + CARRY4 sig_btt_cntr0_carry__0 + (.CI(sig_btt_cntr0_carry_n_0), + .CO({sig_btt_cntr0_carry__0_n_0,sig_btt_cntr0_carry__0_n_1,sig_btt_cntr0_carry__0_n_2,sig_btt_cntr0_carry__0_n_3}), + .CYINIT(1'b0), + .DI(sig_btt_residue_slice[7:4]), + .O(sig_btt_cntr0[7:4]), + .S({sig_btt_cntr0_carry__0_i_1_n_0,sig_btt_cntr0_carry__0_i_2_n_0,sig_btt_cntr0_carry__0_i_3_n_0,sig_btt_cntr0_carry__0_i_4_n_0})); + LUT2 #( + .INIT(4'h9)) + sig_btt_cntr0_carry__0_i_1 + (.I0(sig_btt_residue_slice[7]), + .I1(sig_realigner_btt2[7]), + .O(sig_btt_cntr0_carry__0_i_1_n_0)); + LUT2 #( + .INIT(4'h9)) + sig_btt_cntr0_carry__0_i_2 + (.I0(sig_btt_residue_slice[6]), + .I1(sig_realigner_btt2[6]), + .O(sig_btt_cntr0_carry__0_i_2_n_0)); + LUT2 #( + .INIT(4'h9)) + sig_btt_cntr0_carry__0_i_3 + (.I0(sig_btt_residue_slice[5]), + .I1(sig_realigner_btt2[5]), + .O(sig_btt_cntr0_carry__0_i_3_n_0)); + LUT2 #( + .INIT(4'h9)) + sig_btt_cntr0_carry__0_i_4 + (.I0(sig_btt_residue_slice[4]), + .I1(sig_realigner_btt2[4]), + .O(sig_btt_cntr0_carry__0_i_4_n_0)); + CARRY4 sig_btt_cntr0_carry__1 + (.CI(sig_btt_cntr0_carry__0_n_0), + .CO({sig_btt_cntr0_carry__1_n_0,sig_btt_cntr0_carry__1_n_1,sig_btt_cntr0_carry__1_n_2,sig_btt_cntr0_carry__1_n_3}), + .CYINIT(1'b0), + .DI({sel0[2:0],sig_btt_residue_slice[8]}), + .O(sig_btt_cntr0[11:8]), + .S({sig_btt_cntr0_carry__1_i_1_n_0,sig_btt_cntr0_carry__1_i_2_n_0,sig_btt_cntr0_carry__1_i_3_n_0,sig_btt_cntr0_carry__1_i_4_n_0})); + LUT2 #( + .INIT(4'h9)) + sig_btt_cntr0_carry__1_i_1 + (.I0(sel0[2]), + .I1(sig_realigner_btt2[11]), + .O(sig_btt_cntr0_carry__1_i_1_n_0)); + LUT2 #( + .INIT(4'h9)) + sig_btt_cntr0_carry__1_i_2 + (.I0(sel0[1]), + .I1(sig_realigner_btt2[10]), + .O(sig_btt_cntr0_carry__1_i_2_n_0)); + LUT2 #( + .INIT(4'h9)) + sig_btt_cntr0_carry__1_i_3 + (.I0(sel0[0]), + .I1(sig_realigner_btt2[9]), + .O(sig_btt_cntr0_carry__1_i_3_n_0)); + LUT2 #( + .INIT(4'h9)) + sig_btt_cntr0_carry__1_i_4 + (.I0(sig_btt_residue_slice[8]), + .I1(sig_realigner_btt2[8]), + .O(sig_btt_cntr0_carry__1_i_4_n_0)); + CARRY4 sig_btt_cntr0_carry__2 + (.CI(sig_btt_cntr0_carry__1_n_0), + .CO({NLW_sig_btt_cntr0_carry__2_CO_UNCONNECTED[3],sig_btt_cntr0_carry__2_n_1,sig_btt_cntr0_carry__2_n_2,sig_btt_cntr0_carry__2_n_3}), + .CYINIT(1'b0), + .DI({1'b0,sel0[5:3]}), + .O(sig_btt_cntr0[15:12]), + .S({sig_btt_cntr0_carry__2_i_1_n_0,sig_btt_cntr0_carry__2_i_2_n_0,sig_btt_cntr0_carry__2_i_3_n_0,sig_btt_cntr0_carry__2_i_4_n_0})); + LUT2 #( + .INIT(4'h9)) + sig_btt_cntr0_carry__2_i_1 + (.I0(sel0[6]), + .I1(sig_realigner_btt2[15]), + .O(sig_btt_cntr0_carry__2_i_1_n_0)); + LUT2 #( + .INIT(4'h9)) + sig_btt_cntr0_carry__2_i_2 + (.I0(sel0[5]), + .I1(sig_realigner_btt2[14]), + .O(sig_btt_cntr0_carry__2_i_2_n_0)); + LUT2 #( + .INIT(4'h9)) + sig_btt_cntr0_carry__2_i_3 + (.I0(sel0[4]), + .I1(sig_realigner_btt2[13]), + .O(sig_btt_cntr0_carry__2_i_3_n_0)); + LUT2 #( + .INIT(4'h9)) + sig_btt_cntr0_carry__2_i_4 + (.I0(sel0[3]), + .I1(sig_realigner_btt2[12]), + .O(sig_btt_cntr0_carry__2_i_4_n_0)); + LUT2 #( + .INIT(4'h9)) + sig_btt_cntr0_carry_i_1 + (.I0(sig_btt_residue_slice[3]), + .I1(sig_realigner_btt2[3]), + .O(sig_btt_cntr0_carry_i_1_n_0)); + LUT2 #( + .INIT(4'h9)) + sig_btt_cntr0_carry_i_2 + (.I0(sig_btt_residue_slice[2]), + .I1(sig_realigner_btt2[2]), + .O(sig_btt_cntr0_carry_i_2_n_0)); + LUT2 #( + .INIT(4'h9)) + sig_btt_cntr0_carry_i_3 + (.I0(sig_btt_residue_slice[1]), + .I1(sig_realigner_btt2[1]), + .O(sig_btt_cntr0_carry_i_3_n_0)); + LUT2 #( + .INIT(4'h9)) + sig_btt_cntr0_carry_i_4 + (.I0(sig_btt_residue_slice[0]), + .I1(sig_realigner_btt2[0]), + .O(sig_btt_cntr0_carry_i_4_n_0)); LUT6 #( .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_addr_cntr_lsh_im0[0]_i_1 - (.I0(out[18]), - .I1(\sig_predict_addr_lsh_ireg3_reg_n_0_[0] ), - .I2(in[37]), + \sig_btt_cntr[0]_i_1 + (.I0(out[0]), + .I1(sig_btt_cntr0[0]), + .I2(Q), .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(p_1_in[0])); + .I4(sig_psm_halt), + .I5(p_10_out), + .O(p_1_in__0[0])); LUT6 #( .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_addr_cntr_lsh_im0[10]_i_1 - (.I0(out[28]), - .I1(\sig_predict_addr_lsh_ireg3_reg_n_0_[10] ), - .I2(in[37]), + \sig_btt_cntr[10]_i_1 + (.I0(out[10]), + .I1(sig_btt_cntr0[10]), + .I2(Q), .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(p_1_in[10])); + .I4(sig_psm_halt), + .I5(p_10_out), + .O(p_1_in__0[10])); LUT6 #( .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_addr_cntr_lsh_im0[11]_i_1 - (.I0(out[29]), - .I1(\sig_predict_addr_lsh_ireg3_reg_n_0_[11] ), - .I2(in[37]), + \sig_btt_cntr[11]_i_1 + (.I0(out[11]), + .I1(sig_btt_cntr0[11]), + .I2(Q), .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(p_1_in[11])); + .I4(sig_psm_halt), + .I5(p_10_out), + .O(p_1_in__0[11])); LUT6 #( .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_addr_cntr_lsh_im0[12]_i_1 - (.I0(out[30]), - .I1(\sig_predict_addr_lsh_ireg3_reg_n_0_[12] ), - .I2(in[37]), + \sig_btt_cntr[12]_i_1 + (.I0(out[12]), + .I1(sig_btt_cntr0[12]), + .I2(Q), .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(p_1_in[12])); + .I4(sig_psm_halt), + .I5(p_10_out), + .O(p_1_in__0[12])); LUT6 #( .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_addr_cntr_lsh_im0[13]_i_1 - (.I0(out[31]), - .I1(\sig_predict_addr_lsh_ireg3_reg_n_0_[13] ), - .I2(in[37]), + \sig_btt_cntr[13]_i_1 + (.I0(out[13]), + .I1(sig_btt_cntr0[13]), + .I2(Q), .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(p_1_in[13])); + .I4(sig_psm_halt), + .I5(p_10_out), + .O(p_1_in__0[13])); LUT6 #( .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_addr_cntr_lsh_im0[14]_i_1 - (.I0(out[32]), - .I1(\sig_predict_addr_lsh_ireg3_reg_n_0_[14] ), - .I2(in[37]), + \sig_btt_cntr[14]_i_1 + (.I0(out[14]), + .I1(sig_btt_cntr0[14]), + .I2(Q), .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(p_1_in[14])); + .I4(sig_psm_halt), + .I5(p_10_out), + .O(p_1_in__0[14])); LUT5 #( .INIT(32'hFFFF0010)) - \sig_addr_cntr_lsh_im0[15]_i_1 - (.I0(Q), - .I1(sig_sm_halt_reg), + \sig_btt_cntr[15]_i_1 + (.I0(p_10_out), + .I1(sig_psm_halt), .I2(sig_input_reg_empty), - .I3(in[37]), - .I4(sig_pop_xfer_reg0_out), - .O(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 )); + .I3(Q), + .I4(sig_psm_ld_realigner_reg), + .O(\sig_btt_cntr[15]_i_1_n_0 )); LUT6 #( .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_addr_cntr_lsh_im0[15]_i_2 - (.I0(out[33]), - .I1(sig_predict_addr_lsh_ireg3), - .I2(in[37]), + \sig_btt_cntr[15]_i_2__0 + (.I0(out[15]), + .I1(sig_btt_cntr0[15]), + .I2(Q), .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(p_1_in[15])); + .I4(sig_psm_halt), + .I5(p_10_out), + .O(p_1_in__0[15])); LUT6 #( .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_addr_cntr_lsh_im0[1]_i_1 - (.I0(out[19]), - .I1(\sig_predict_addr_lsh_ireg3_reg_n_0_[1] ), - .I2(in[37]), + \sig_btt_cntr[1]_i_1 + (.I0(out[1]), + .I1(sig_btt_cntr0[1]), + .I2(Q), .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(p_1_in[1])); + .I4(sig_psm_halt), + .I5(p_10_out), + .O(p_1_in__0[1])); LUT6 #( .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_addr_cntr_lsh_im0[2]_i_1 - (.I0(out[20]), - .I1(\sig_predict_addr_lsh_ireg3_reg_n_0_[2] ), - .I2(in[37]), + \sig_btt_cntr[2]_i_1 + (.I0(out[2]), + .I1(sig_btt_cntr0[2]), + .I2(Q), .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(p_1_in[2])); + .I4(sig_psm_halt), + .I5(p_10_out), + .O(p_1_in__0[2])); LUT6 #( .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_addr_cntr_lsh_im0[3]_i_1 - (.I0(out[21]), - .I1(\sig_predict_addr_lsh_ireg3_reg_n_0_[3] ), - .I2(in[37]), + \sig_btt_cntr[3]_i_1 + (.I0(out[3]), + .I1(sig_btt_cntr0[3]), + .I2(Q), .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(p_1_in[3])); + .I4(sig_psm_halt), + .I5(p_10_out), + .O(p_1_in__0[3])); LUT6 #( .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_addr_cntr_lsh_im0[4]_i_1 - (.I0(out[22]), - .I1(\sig_predict_addr_lsh_ireg3_reg_n_0_[4] ), - .I2(in[37]), + \sig_btt_cntr[4]_i_1 + (.I0(out[4]), + .I1(sig_btt_cntr0[4]), + .I2(Q), .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(p_1_in[4])); + .I4(sig_psm_halt), + .I5(p_10_out), + .O(p_1_in__0[4])); LUT6 #( .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_addr_cntr_lsh_im0[5]_i_1 - (.I0(out[23]), - .I1(\sig_predict_addr_lsh_ireg3_reg_n_0_[5] ), - .I2(in[37]), + \sig_btt_cntr[5]_i_1 + (.I0(out[5]), + .I1(sig_btt_cntr0[5]), + .I2(Q), .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(p_1_in[5])); + .I4(sig_psm_halt), + .I5(p_10_out), + .O(p_1_in__0[5])); LUT6 #( .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_addr_cntr_lsh_im0[6]_i_1 - (.I0(out[24]), - .I1(\sig_predict_addr_lsh_ireg3_reg_n_0_[6] ), - .I2(in[37]), + \sig_btt_cntr[6]_i_1 + (.I0(out[6]), + .I1(sig_btt_cntr0[6]), + .I2(Q), .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(p_1_in[6])); + .I4(sig_psm_halt), + .I5(p_10_out), + .O(p_1_in__0[6])); LUT6 #( .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_addr_cntr_lsh_im0[7]_i_1 - (.I0(out[25]), - .I1(\sig_predict_addr_lsh_ireg3_reg_n_0_[7] ), - .I2(in[37]), + \sig_btt_cntr[7]_i_1 + (.I0(out[7]), + .I1(sig_btt_cntr0[7]), + .I2(Q), .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(p_1_in[7])); + .I4(sig_psm_halt), + .I5(p_10_out), + .O(p_1_in__0[7])); LUT6 #( .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_addr_cntr_lsh_im0[8]_i_1 - (.I0(out[26]), - .I1(\sig_predict_addr_lsh_ireg3_reg_n_0_[8] ), - .I2(in[37]), + \sig_btt_cntr[8]_i_1 + (.I0(out[8]), + .I1(sig_btt_cntr0[8]), + .I2(Q), .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(p_1_in[8])); + .I4(sig_psm_halt), + .I5(p_10_out), + .O(p_1_in__0[8])); LUT6 #( .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_addr_cntr_lsh_im0[9]_i_1 - (.I0(out[27]), - .I1(\sig_predict_addr_lsh_ireg3_reg_n_0_[9] ), - .I2(in[37]), + \sig_btt_cntr[9]_i_1 + (.I0(out[9]), + .I1(sig_btt_cntr0[9]), + .I2(Q), .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(p_1_in[9])); + .I4(sig_psm_halt), + .I5(p_10_out), + .O(p_1_in__0[9])); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_im0_reg[0] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(p_1_in[0]), - .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), + \sig_btt_cntr_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(\sig_btt_cntr[15]_i_1_n_0 ), + .D(p_1_in__0[0]), + .Q(sig_btt_residue_slice[0]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_im0_reg[10] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(p_1_in[10]), - .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[10] ), + \sig_btt_cntr_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(\sig_btt_cntr[15]_i_1_n_0 ), + .D(p_1_in__0[10]), + .Q(sel0[1]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_im0_reg[11] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(p_1_in[11]), - .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[11] ), + \sig_btt_cntr_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(\sig_btt_cntr[15]_i_1_n_0 ), + .D(p_1_in__0[11]), + .Q(sel0[2]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_im0_reg[12] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(p_1_in[12]), - .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[12] ), + \sig_btt_cntr_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(\sig_btt_cntr[15]_i_1_n_0 ), + .D(p_1_in__0[12]), + .Q(sel0[3]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_im0_reg[13] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(p_1_in[13]), - .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[13] ), + \sig_btt_cntr_reg[13] + (.C(m_axi_s2mm_aclk), + .CE(\sig_btt_cntr[15]_i_1_n_0 ), + .D(p_1_in__0[13]), + .Q(sel0[4]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_im0_reg[14] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(p_1_in[14]), - .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[14] ), + \sig_btt_cntr_reg[14] + (.C(m_axi_s2mm_aclk), + .CE(\sig_btt_cntr[15]_i_1_n_0 ), + .D(p_1_in__0[14]), + .Q(sel0[5]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_im0_reg[15] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(p_1_in[15]), - .Q(p_1_in_0), + \sig_btt_cntr_reg[15] + (.C(m_axi_s2mm_aclk), + .CE(\sig_btt_cntr[15]_i_1_n_0 ), + .D(p_1_in__0[15]), + .Q(sel0[6]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_im0_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(p_1_in[1]), - .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), + \sig_btt_cntr_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(\sig_btt_cntr[15]_i_1_n_0 ), + .D(p_1_in__0[1]), + .Q(sig_btt_residue_slice[1]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_im0_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(p_1_in[2]), - .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), + \sig_btt_cntr_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(\sig_btt_cntr[15]_i_1_n_0 ), + .D(p_1_in__0[2]), + .Q(sig_btt_residue_slice[2]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_im0_reg[3] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(p_1_in[3]), - .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[3] ), + \sig_btt_cntr_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(\sig_btt_cntr[15]_i_1_n_0 ), + .D(p_1_in__0[3]), + .Q(sig_btt_residue_slice[3]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_im0_reg[4] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(p_1_in[4]), - .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[4] ), + \sig_btt_cntr_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(\sig_btt_cntr[15]_i_1_n_0 ), + .D(p_1_in__0[4]), + .Q(sig_btt_residue_slice[4]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_im0_reg[5] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(p_1_in[5]), - .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[5] ), + \sig_btt_cntr_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(\sig_btt_cntr[15]_i_1_n_0 ), + .D(p_1_in__0[5]), + .Q(sig_btt_residue_slice[5]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_im0_reg[6] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(p_1_in[6]), - .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[6] ), + \sig_btt_cntr_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(\sig_btt_cntr[15]_i_1_n_0 ), + .D(p_1_in__0[6]), + .Q(sig_btt_residue_slice[6]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_im0_reg[7] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(p_1_in[7]), - .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[7] ), + \sig_btt_cntr_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(\sig_btt_cntr[15]_i_1_n_0 ), + .D(p_1_in__0[7]), + .Q(sig_btt_residue_slice[7]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_im0_reg[8] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(p_1_in[8]), - .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[8] ), + \sig_btt_cntr_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(\sig_btt_cntr[15]_i_1_n_0 ), + .D(p_1_in__0[8]), + .Q(sig_btt_residue_slice[8]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_im0_reg[9] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(p_1_in[9]), - .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[9] ), + \sig_btt_cntr_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(\sig_btt_cntr[15]_i_1_n_0 ), + .D(p_1_in__0[9]), + .Q(sel0[0]), .R(sig_init_reg)); + CARRY4 sig_btt_eq_b2mbaa2_carry + (.CI(1'b0), + .CO({NLW_sig_btt_eq_b2mbaa2_carry_CO_UNCONNECTED[3],sig_btt_eq_b2mbaa2,sig_btt_eq_b2mbaa2_carry_n_2,sig_btt_eq_b2mbaa2_carry_n_3}), + .CYINIT(1'b1), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(NLW_sig_btt_eq_b2mbaa2_carry_O_UNCONNECTED[3:0]), + .S({1'b0,sig_btt_eq_b2mbaa2_carry_i_1_n_0,sig_btt_eq_b2mbaa2_carry_i_2_n_0,sig_btt_eq_b2mbaa2_carry_i_3_n_0})); + LUT6 #( + .INIT(64'h9009000000009009)) + sig_btt_eq_b2mbaa2_carry_i_1 + (.I0(sig_btt_residue_slice[6]), + .I1(sig_bytes_to_mbaa__8[6]), + .I2(sig_bytes_to_mbaa), + .I3(sig_btt_residue_slice[8]), + .I4(sig_bytes_to_mbaa__8[7]), + .I5(sig_btt_residue_slice[7]), + .O(sig_btt_eq_b2mbaa2_carry_i_1_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + sig_btt_eq_b2mbaa2_carry_i_2 + (.I0(sig_btt_residue_slice[3]), + .I1(sig_bytes_to_mbaa__8[3]), + .I2(sig_bytes_to_mbaa__8[5]), + .I3(sig_btt_residue_slice[5]), + .I4(sig_bytes_to_mbaa__8[4]), + .I5(sig_btt_residue_slice[4]), + .O(sig_btt_eq_b2mbaa2_carry_i_2_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + sig_btt_eq_b2mbaa2_carry_i_3 + (.I0(sig_btt_residue_slice[0]), + .I1(sig_bytes_to_mbaa__8[0]), + .I2(sig_bytes_to_mbaa__8[2]), + .I3(sig_btt_residue_slice[2]), + .I4(sig_bytes_to_mbaa__8[1]), + .I5(sig_btt_residue_slice[1]), + .O(sig_btt_eq_b2mbaa2_carry_i_3_n_0)); + LUT2 #( + .INIT(4'h2)) + sig_btt_eq_b2mbaa2_carry_i_4 + (.I0(sig_input_addr_reg[0]), + .I1(sig_addr_aligned__6), + .O(sig_bytes_to_mbaa__8[0])); + LUT3 #( + .INIT(8'h06)) + sig_btt_eq_b2mbaa2_carry_i_5 + (.I0(sig_input_addr_reg[1]), + .I1(sig_input_addr_reg[0]), + .I2(sig_addr_aligned__6), + .O(sig_bytes_to_mbaa__8[1])); + CARRY4 sig_btt_lt_b2mbaa2_carry + (.CI(1'b0), + .CO({sig_btt_lt_b2mbaa2_carry_n_0,sig_btt_lt_b2mbaa2_carry_n_1,sig_btt_lt_b2mbaa2_carry_n_2,sig_btt_lt_b2mbaa2_carry_n_3}), + .CYINIT(1'b0), + .DI({sig_btt_lt_b2mbaa2_carry_i_1_n_0,sig_btt_lt_b2mbaa2_carry_i_2_n_0,sig_btt_lt_b2mbaa2_carry_i_3_n_0,sig_btt_lt_b2mbaa2_carry_i_4_n_0}), + .O(NLW_sig_btt_lt_b2mbaa2_carry_O_UNCONNECTED[3:0]), + .S({sig_btt_lt_b2mbaa2_carry_i_5_n_0,sig_btt_lt_b2mbaa2_carry_i_6_n_0,sig_btt_lt_b2mbaa2_carry_i_7_n_0,sig_btt_lt_b2mbaa2_carry_i_8_n_0})); + CARRY4 sig_btt_lt_b2mbaa2_carry__0 + (.CI(sig_btt_lt_b2mbaa2_carry_n_0), + .CO({NLW_sig_btt_lt_b2mbaa2_carry__0_CO_UNCONNECTED[3:1],sig_btt_lt_b2mbaa2}), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,sig_btt_lt_b2mbaa2_carry__0_i_1_n_0}), + .O(NLW_sig_btt_lt_b2mbaa2_carry__0_O_UNCONNECTED[3:0]), + .S({1'b0,1'b0,1'b0,sig_btt_lt_b2mbaa2_carry__0_i_2_n_0})); + LUT2 #( + .INIT(4'h2)) + sig_btt_lt_b2mbaa2_carry__0_i_1 + (.I0(sig_bytes_to_mbaa), + .I1(sig_btt_residue_slice[8]), + .O(sig_btt_lt_b2mbaa2_carry__0_i_1_n_0)); + LUT2 #( + .INIT(4'h9)) + sig_btt_lt_b2mbaa2_carry__0_i_2 + (.I0(sig_btt_residue_slice[8]), + .I1(sig_bytes_to_mbaa), + .O(sig_btt_lt_b2mbaa2_carry__0_i_2_n_0)); + LUT6 #( + .INIT(64'h0000000017033017)) + sig_btt_lt_b2mbaa2_carry_i_1 + (.I0(sig_btt_residue_slice[6]), + .I1(sig_btt_residue_slice[7]), + .I2(sig_input_addr_reg[7]), + .I3(sig_btt_lt_b2mbaa2_carry_i_9_n_0), + .I4(sig_input_addr_reg[6]), + .I5(sig_addr_aligned__6), + .O(sig_btt_lt_b2mbaa2_carry_i_1_n_0)); + LUT4 #( + .INIT(16'h0001)) + sig_btt_lt_b2mbaa2_carry_i_10 + (.I0(sig_input_addr_reg[2]), + .I1(sig_input_addr_reg[0]), + .I2(sig_input_addr_reg[1]), + .I3(sig_input_addr_reg[3]), + .O(sig_btt_lt_b2mbaa2_carry_i_10_n_0)); + LUT4 #( + .INIT(16'h0056)) + sig_btt_lt_b2mbaa2_carry_i_11 + (.I0(sig_input_addr_reg[2]), + .I1(sig_input_addr_reg[0]), + .I2(sig_input_addr_reg[1]), + .I3(sig_addr_aligned__6), + .O(sig_bytes_to_mbaa__8[2])); + LUT6 #( + .INIT(64'h0000000017033017)) + sig_btt_lt_b2mbaa2_carry_i_2 + (.I0(sig_btt_residue_slice[4]), + .I1(sig_btt_residue_slice[5]), + .I2(sig_input_addr_reg[5]), + .I3(sig_btt_lt_b2mbaa2_carry_i_10_n_0), + .I4(sig_input_addr_reg[4]), + .I5(sig_addr_aligned__6), + .O(sig_btt_lt_b2mbaa2_carry_i_2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + sig_btt_lt_b2mbaa2_carry_i_3 + (.I0(sig_bytes_to_mbaa__8[2]), + .I1(sig_btt_residue_slice[2]), + .I2(sig_btt_residue_slice[3]), + .I3(sig_bytes_to_mbaa__8[3]), + .O(sig_btt_lt_b2mbaa2_carry_i_3_n_0)); + LUT5 #( + .INIT(32'h00001730)) + sig_btt_lt_b2mbaa2_carry_i_4 + (.I0(sig_btt_residue_slice[0]), + .I1(sig_btt_residue_slice[1]), + .I2(sig_input_addr_reg[1]), + .I3(sig_input_addr_reg[0]), + .I4(sig_addr_aligned__6), + .O(sig_btt_lt_b2mbaa2_carry_i_4_n_0)); + LUT6 #( + .INIT(64'h0000214255558418)) + sig_btt_lt_b2mbaa2_carry_i_5 + (.I0(sig_btt_residue_slice[6]), + .I1(sig_input_addr_reg[7]), + .I2(sig_btt_lt_b2mbaa2_carry_i_9_n_0), + .I3(sig_input_addr_reg[6]), + .I4(sig_addr_aligned__6), + .I5(sig_btt_residue_slice[7]), + .O(sig_btt_lt_b2mbaa2_carry_i_5_n_0)); + LUT6 #( + .INIT(64'h0000214255558418)) + sig_btt_lt_b2mbaa2_carry_i_6 + (.I0(sig_btt_residue_slice[4]), + .I1(sig_input_addr_reg[5]), + .I2(sig_btt_lt_b2mbaa2_carry_i_10_n_0), + .I3(sig_input_addr_reg[4]), + .I4(sig_addr_aligned__6), + .I5(sig_btt_residue_slice[5]), + .O(sig_btt_lt_b2mbaa2_carry_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + sig_btt_lt_b2mbaa2_carry_i_7 + (.I0(sig_bytes_to_mbaa__8[2]), + .I1(sig_btt_residue_slice[2]), + .I2(sig_bytes_to_mbaa__8[3]), + .I3(sig_btt_residue_slice[3]), + .O(sig_btt_lt_b2mbaa2_carry_i_7_n_0)); + LUT5 #( + .INIT(32'h00245581)) + sig_btt_lt_b2mbaa2_carry_i_8 + (.I0(sig_btt_residue_slice[0]), + .I1(sig_input_addr_reg[1]), + .I2(sig_input_addr_reg[0]), + .I3(sig_addr_aligned__6), + .I4(sig_btt_residue_slice[1]), + .O(sig_btt_lt_b2mbaa2_carry_i_8_n_0)); + LUT6 #( + .INIT(64'h0000000000000001)) + sig_btt_lt_b2mbaa2_carry_i_9 + (.I0(sig_input_addr_reg[4]), + .I1(sig_input_addr_reg[2]), + .I2(sig_input_addr_reg[0]), + .I3(sig_input_addr_reg[1]), + .I4(sig_input_addr_reg[3]), + .I5(sig_input_addr_reg[5]), + .O(sig_btt_lt_b2mbaa2_carry_i_9_n_0)); + CARRY4 sig_byte_change_minus1_carry + (.CI(1'b0), + .CO({sig_byte_change_minus1_carry_n_0,sig_byte_change_minus1_carry_n_1,sig_byte_change_minus1_carry_n_2,sig_byte_change_minus1_carry_n_3}), + .CYINIT(1'b0), + .DI({1'b0,\gpr1.dout_i_reg[9] [2:0]}), + .O(sig_adjusted_addr_incr[3:0]), + .S(S)); + CARRY4 sig_byte_change_minus1_carry__0 + (.CI(sig_byte_change_minus1_carry_n_0), + .CO({sig_byte_change_minus1_carry__0_n_0,sig_byte_change_minus1_carry__0_n_1,sig_byte_change_minus1_carry__0_n_2,sig_byte_change_minus1_carry__0_n_3}), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(sig_adjusted_addr_incr[7:4]), + .S(\gpr1.dout_i_reg[7]_0 )); + CARRY4 sig_byte_change_minus1_carry__1 + (.CI(sig_byte_change_minus1_carry__0_n_0), + .CO(NLW_sig_byte_change_minus1_carry__1_CO_UNCONNECTED[3:0]), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({NLW_sig_byte_change_minus1_carry__1_O_UNCONNECTED[3:1],sig_adjusted_addr_incr[8]}), + .S({1'b0,1'b0,1'b0,\gpr1.dout_i_reg[8] })); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[0] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[18]), - .Q(sig_addr_cntr_lsh_kh[0]), + sig_calc_error_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_psm_halt_reg_0), + .Q(p_10_out), .R(sig_init_reg)); + LUT3 #( + .INIT(8'hEA)) + \sig_child_addr_cntr_lsh[0]_i_1 + (.I0(sig_csm_pop_child_cmd), + .I1(sig_csm_ld_xfer), + .I2(sig_child_qual_burst_type), + .O(\sig_child_addr_cntr_lsh[0]_i_1_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \sig_child_addr_cntr_lsh[0]_i_10 + (.I0(\gpr1.dout_i_reg[9] [0]), + .I1(\sig_xfer_addr_reg_reg[2]_0 [0]), + .I2(sig_csm_pop_child_cmd), + .I3(\sig_child_addr_reg_reg_n_0_[0] ), + .O(\sig_child_addr_cntr_lsh_reg[3]_0 [0])); + LUT4 #( + .INIT(16'hF606)) + \sig_child_addr_cntr_lsh[0]_i_7 + (.I0(\gpr1.dout_i_reg[9] [3]), + .I1(sig_child_addr_cntr_lsh_reg[3]), + .I2(sig_csm_pop_child_cmd), + .I3(\sig_child_addr_reg_reg_n_0_[3] ), + .O(\sig_child_addr_cntr_lsh_reg[3]_0 [3])); + LUT4 #( + .INIT(16'hF606)) + \sig_child_addr_cntr_lsh[0]_i_8 + (.I0(\gpr1.dout_i_reg[9] [2]), + .I1(\sig_xfer_addr_reg_reg[2]_0 [2]), + .I2(sig_csm_pop_child_cmd), + .I3(\sig_child_addr_reg_reg_n_0_[2] ), + .O(\sig_child_addr_cntr_lsh_reg[3]_0 [2])); + LUT4 #( + .INIT(16'hF606)) + \sig_child_addr_cntr_lsh[0]_i_9 + (.I0(\gpr1.dout_i_reg[9] [1]), + .I1(\sig_xfer_addr_reg_reg[2]_0 [1]), + .I2(sig_csm_pop_child_cmd), + .I3(\sig_child_addr_reg_reg_n_0_[1] ), + .O(\sig_child_addr_cntr_lsh_reg[3]_0 [1])); + LUT3 #( + .INIT(8'hB8)) + \sig_child_addr_cntr_lsh[12]_i_2 + (.I0(\sig_child_addr_reg_reg_n_0_[15] ), + .I1(sig_csm_pop_child_cmd), + .I2(p_1_in), + .O(\sig_child_addr_cntr_lsh[12]_i_2_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \sig_child_addr_cntr_lsh[12]_i_3 + (.I0(\sig_child_addr_reg_reg_n_0_[14] ), + .I1(sig_csm_pop_child_cmd), + .I2(sig_child_addr_cntr_lsh_reg[14]), + .O(\sig_child_addr_cntr_lsh[12]_i_3_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \sig_child_addr_cntr_lsh[12]_i_4 + (.I0(\sig_child_addr_reg_reg_n_0_[13] ), + .I1(sig_csm_pop_child_cmd), + .I2(sig_child_addr_cntr_lsh_reg[13]), + .O(\sig_child_addr_cntr_lsh[12]_i_4_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \sig_child_addr_cntr_lsh[12]_i_5 + (.I0(\sig_child_addr_reg_reg_n_0_[12] ), + .I1(sig_csm_pop_child_cmd), + .I2(sig_child_addr_cntr_lsh_reg[12]), + .O(\sig_child_addr_cntr_lsh[12]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \sig_child_addr_cntr_lsh[4]_i_6 + (.I0(\gpr1.dout_i_reg[9] [7]), + .I1(sig_child_addr_cntr_lsh_reg[7]), + .I2(sig_csm_pop_child_cmd), + .I3(\sig_child_addr_reg_reg_n_0_[7] ), + .O(\sig_child_addr_cntr_lsh_reg[7]_0 [3])); + LUT4 #( + .INIT(16'hF606)) + \sig_child_addr_cntr_lsh[4]_i_7 + (.I0(\gpr1.dout_i_reg[9] [6]), + .I1(sig_child_addr_cntr_lsh_reg[6]), + .I2(sig_csm_pop_child_cmd), + .I3(\sig_child_addr_reg_reg_n_0_[6] ), + .O(\sig_child_addr_cntr_lsh_reg[7]_0 [2])); + LUT4 #( + .INIT(16'hF606)) + \sig_child_addr_cntr_lsh[4]_i_8 + (.I0(\gpr1.dout_i_reg[9] [5]), + .I1(sig_child_addr_cntr_lsh_reg[5]), + .I2(sig_csm_pop_child_cmd), + .I3(\sig_child_addr_reg_reg_n_0_[5] ), + .O(\sig_child_addr_cntr_lsh_reg[7]_0 [1])); + LUT4 #( + .INIT(16'hF606)) + \sig_child_addr_cntr_lsh[4]_i_9 + (.I0(\gpr1.dout_i_reg[9] [4]), + .I1(sig_child_addr_cntr_lsh_reg[4]), + .I2(sig_csm_pop_child_cmd), + .I3(\sig_child_addr_reg_reg_n_0_[4] ), + .O(\sig_child_addr_cntr_lsh_reg[7]_0 [0])); + LUT3 #( + .INIT(8'hB8)) + \sig_child_addr_cntr_lsh[8]_i_3 + (.I0(\sig_child_addr_reg_reg_n_0_[11] ), + .I1(sig_csm_pop_child_cmd), + .I2(sig_child_addr_cntr_lsh_reg[11]), + .O(\sig_child_addr_cntr_lsh[8]_i_3_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \sig_child_addr_cntr_lsh[8]_i_4 + (.I0(\sig_child_addr_reg_reg_n_0_[10] ), + .I1(sig_csm_pop_child_cmd), + .I2(sig_child_addr_cntr_lsh_reg[10]), + .O(\sig_child_addr_cntr_lsh[8]_i_4_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \sig_child_addr_cntr_lsh[8]_i_5 + (.I0(\sig_child_addr_reg_reg_n_0_[9] ), + .I1(sig_csm_pop_child_cmd), + .I2(sig_child_addr_cntr_lsh_reg[9]), + .O(\sig_child_addr_cntr_lsh[8]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \sig_child_addr_cntr_lsh[8]_i_6 + (.I0(\gpr1.dout_i_reg[9] [8]), + .I1(sig_child_addr_cntr_lsh_reg[8]), + .I2(sig_csm_pop_child_cmd), + .I3(\sig_child_addr_reg_reg_n_0_[8] ), + .O(\sig_child_addr_cntr_lsh[8]_i_6_n_0 )); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[10] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[28]), - .Q(sig_addr_cntr_lsh_kh[10]), + \sig_child_addr_cntr_lsh_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_lsh[0]_i_1_n_0 ), + .D(O[0]), + .Q(\sig_xfer_addr_reg_reg[2]_0 [0]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[11] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[29]), - .Q(sig_addr_cntr_lsh_kh[11]), + \sig_child_addr_cntr_lsh_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_lsh[0]_i_1_n_0 ), + .D(\sig_child_addr_cntr_lsh_reg[8]_i_1_n_5 ), + .Q(sig_child_addr_cntr_lsh_reg[10]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[12] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[30]), - .Q(sig_addr_cntr_lsh_kh[12]), + \sig_child_addr_cntr_lsh_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_lsh[0]_i_1_n_0 ), + .D(\sig_child_addr_cntr_lsh_reg[8]_i_1_n_4 ), + .Q(sig_child_addr_cntr_lsh_reg[11]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[13] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[31]), - .Q(sig_addr_cntr_lsh_kh[13]), + \sig_child_addr_cntr_lsh_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_lsh[0]_i_1_n_0 ), + .D(\sig_child_addr_cntr_lsh_reg[12]_i_1_n_7 ), + .Q(sig_child_addr_cntr_lsh_reg[12]), .R(sig_init_reg)); + CARRY4 \sig_child_addr_cntr_lsh_reg[12]_i_1 + (.CI(\sig_child_addr_cntr_lsh_reg[8]_i_1_n_0 ), + .CO({\NLW_sig_child_addr_cntr_lsh_reg[12]_i_1_CO_UNCONNECTED [3],\sig_child_addr_cntr_lsh_reg[12]_i_1_n_1 ,\sig_child_addr_cntr_lsh_reg[12]_i_1_n_2 ,\sig_child_addr_cntr_lsh_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\sig_child_addr_cntr_lsh_reg[12]_i_1_n_4 ,\sig_child_addr_cntr_lsh_reg[12]_i_1_n_5 ,\sig_child_addr_cntr_lsh_reg[12]_i_1_n_6 ,\sig_child_addr_cntr_lsh_reg[12]_i_1_n_7 }), + .S({\sig_child_addr_cntr_lsh[12]_i_2_n_0 ,\sig_child_addr_cntr_lsh[12]_i_3_n_0 ,\sig_child_addr_cntr_lsh[12]_i_4_n_0 ,\sig_child_addr_cntr_lsh[12]_i_5_n_0 })); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[14] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[32]), - .Q(sig_addr_cntr_lsh_kh[14]), + \sig_child_addr_cntr_lsh_reg[13] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_lsh[0]_i_1_n_0 ), + .D(\sig_child_addr_cntr_lsh_reg[12]_i_1_n_6 ), + .Q(sig_child_addr_cntr_lsh_reg[13]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[15] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[33]), - .Q(sig_addr_cntr_lsh_kh[15]), + \sig_child_addr_cntr_lsh_reg[14] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_lsh[0]_i_1_n_0 ), + .D(\sig_child_addr_cntr_lsh_reg[12]_i_1_n_5 ), + .Q(sig_child_addr_cntr_lsh_reg[14]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[16] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[34]), - .Q(sig_addr_cntr_lsh_kh[16]), + \sig_child_addr_cntr_lsh_reg[15] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_lsh[0]_i_1_n_0 ), + .D(\sig_child_addr_cntr_lsh_reg[12]_i_1_n_4 ), + .Q(p_1_in), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[17] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[35]), - .Q(sig_addr_cntr_lsh_kh[17]), + \sig_child_addr_cntr_lsh_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_lsh[0]_i_1_n_0 ), + .D(O[1]), + .Q(\sig_xfer_addr_reg_reg[2]_0 [1]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[18] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[36]), - .Q(sig_addr_cntr_lsh_kh[18]), + \sig_child_addr_cntr_lsh_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_lsh[0]_i_1_n_0 ), + .D(O[2]), + .Q(\sig_xfer_addr_reg_reg[2]_0 [2]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[19] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[37]), - .Q(sig_addr_cntr_lsh_kh[19]), + \sig_child_addr_cntr_lsh_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_lsh[0]_i_1_n_0 ), + .D(O[3]), + .Q(sig_child_addr_cntr_lsh_reg[3]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[19]), - .Q(sig_addr_cntr_lsh_kh[1]), + \sig_child_addr_cntr_lsh_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_lsh[0]_i_1_n_0 ), + .D(\gpr1.dout_i_reg[7] [0]), + .Q(sig_child_addr_cntr_lsh_reg[4]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[20] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[38]), - .Q(sig_addr_cntr_lsh_kh[20]), + \sig_child_addr_cntr_lsh_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_lsh[0]_i_1_n_0 ), + .D(\gpr1.dout_i_reg[7] [1]), + .Q(sig_child_addr_cntr_lsh_reg[5]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[21] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[39]), - .Q(sig_addr_cntr_lsh_kh[21]), + \sig_child_addr_cntr_lsh_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_lsh[0]_i_1_n_0 ), + .D(\gpr1.dout_i_reg[7] [2]), + .Q(sig_child_addr_cntr_lsh_reg[6]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[22] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[40]), - .Q(sig_addr_cntr_lsh_kh[22]), + \sig_child_addr_cntr_lsh_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_lsh[0]_i_1_n_0 ), + .D(\gpr1.dout_i_reg[7] [3]), + .Q(sig_child_addr_cntr_lsh_reg[7]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[23] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[41]), - .Q(sig_addr_cntr_lsh_kh[23]), + \sig_child_addr_cntr_lsh_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_lsh[0]_i_1_n_0 ), + .D(\sig_child_addr_cntr_lsh_reg[8]_i_1_n_7 ), + .Q(sig_child_addr_cntr_lsh_reg[8]), .R(sig_init_reg)); + CARRY4 \sig_child_addr_cntr_lsh_reg[8]_i_1 + (.CI(CO), + .CO({\sig_child_addr_cntr_lsh_reg[8]_i_1_n_0 ,\sig_child_addr_cntr_lsh_reg[8]_i_1_n_1 ,\sig_child_addr_cntr_lsh_reg[8]_i_1_n_2 ,\sig_child_addr_cntr_lsh_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,\gpr1.dout_i_reg[8]_0 }), + .O({\sig_child_addr_cntr_lsh_reg[8]_i_1_n_4 ,\sig_child_addr_cntr_lsh_reg[8]_i_1_n_5 ,\sig_child_addr_cntr_lsh_reg[8]_i_1_n_6 ,\sig_child_addr_cntr_lsh_reg[8]_i_1_n_7 }), + .S({\sig_child_addr_cntr_lsh[8]_i_3_n_0 ,\sig_child_addr_cntr_lsh[8]_i_4_n_0 ,\sig_child_addr_cntr_lsh[8]_i_5_n_0 ,\sig_child_addr_cntr_lsh[8]_i_6_n_0 })); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[24] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[42]), - .Q(sig_addr_cntr_lsh_kh[24]), + \sig_child_addr_cntr_lsh_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_lsh[0]_i_1_n_0 ), + .D(\sig_child_addr_cntr_lsh_reg[8]_i_1_n_6 ), + .Q(sig_child_addr_cntr_lsh_reg[9]), + .R(sig_init_reg)); + LUT4 #( + .INIT(16'hEAAA)) + \sig_child_addr_cntr_msh[0]_i_1 + (.I0(sig_csm_pop_child_cmd), + .I1(sig_child_qual_burst_type), + .I2(sig_csm_ld_xfer), + .I3(sig_child_addr_lsh_rollover_reg), + .O(\sig_child_addr_cntr_msh[0]_i_1_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \sig_child_addr_cntr_msh[0]_i_3 + (.I0(data[0]), + .I1(sig_csm_pop_child_cmd), + .I2(sig_child_addr_cntr_msh_reg[0]), + .O(\sig_child_addr_cntr_msh[0]_i_3_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \sig_child_addr_cntr_msh[0]_i_4 + (.I0(data[3]), + .I1(sig_csm_pop_child_cmd), + .I2(sig_child_addr_cntr_msh_reg[3]), + .O(\sig_child_addr_cntr_msh[0]_i_4_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \sig_child_addr_cntr_msh[0]_i_5 + (.I0(data[2]), + .I1(sig_csm_pop_child_cmd), + .I2(sig_child_addr_cntr_msh_reg[2]), + .O(\sig_child_addr_cntr_msh[0]_i_5_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \sig_child_addr_cntr_msh[0]_i_6 + (.I0(data[1]), + .I1(sig_csm_pop_child_cmd), + .I2(sig_child_addr_cntr_msh_reg[1]), + .O(\sig_child_addr_cntr_msh[0]_i_6_n_0 )); + LUT3 #( + .INIT(8'hC5)) + \sig_child_addr_cntr_msh[0]_i_7 + (.I0(sig_child_addr_cntr_msh_reg[0]), + .I1(data[0]), + .I2(sig_csm_pop_child_cmd), + .O(\sig_child_addr_cntr_msh[0]_i_7_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \sig_child_addr_cntr_msh[12]_i_2 + (.I0(data[15]), + .I1(sig_csm_pop_child_cmd), + .I2(sig_child_addr_cntr_msh_reg[15]), + .O(\sig_child_addr_cntr_msh[12]_i_2_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \sig_child_addr_cntr_msh[12]_i_3 + (.I0(data[14]), + .I1(sig_csm_pop_child_cmd), + .I2(sig_child_addr_cntr_msh_reg[14]), + .O(\sig_child_addr_cntr_msh[12]_i_3_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \sig_child_addr_cntr_msh[12]_i_4 + (.I0(data[13]), + .I1(sig_csm_pop_child_cmd), + .I2(sig_child_addr_cntr_msh_reg[13]), + .O(\sig_child_addr_cntr_msh[12]_i_4_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \sig_child_addr_cntr_msh[12]_i_5 + (.I0(data[12]), + .I1(sig_csm_pop_child_cmd), + .I2(sig_child_addr_cntr_msh_reg[12]), + .O(\sig_child_addr_cntr_msh[12]_i_5_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \sig_child_addr_cntr_msh[4]_i_2 + (.I0(data[7]), + .I1(sig_csm_pop_child_cmd), + .I2(sig_child_addr_cntr_msh_reg[7]), + .O(\sig_child_addr_cntr_msh[4]_i_2_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \sig_child_addr_cntr_msh[4]_i_3 + (.I0(data[6]), + .I1(sig_csm_pop_child_cmd), + .I2(sig_child_addr_cntr_msh_reg[6]), + .O(\sig_child_addr_cntr_msh[4]_i_3_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \sig_child_addr_cntr_msh[4]_i_4 + (.I0(data[5]), + .I1(sig_csm_pop_child_cmd), + .I2(sig_child_addr_cntr_msh_reg[5]), + .O(\sig_child_addr_cntr_msh[4]_i_4_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \sig_child_addr_cntr_msh[4]_i_5 + (.I0(data[4]), + .I1(sig_csm_pop_child_cmd), + .I2(sig_child_addr_cntr_msh_reg[4]), + .O(\sig_child_addr_cntr_msh[4]_i_5_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \sig_child_addr_cntr_msh[8]_i_2 + (.I0(data[11]), + .I1(sig_csm_pop_child_cmd), + .I2(sig_child_addr_cntr_msh_reg[11]), + .O(\sig_child_addr_cntr_msh[8]_i_2_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \sig_child_addr_cntr_msh[8]_i_3 + (.I0(data[10]), + .I1(sig_csm_pop_child_cmd), + .I2(sig_child_addr_cntr_msh_reg[10]), + .O(\sig_child_addr_cntr_msh[8]_i_3_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \sig_child_addr_cntr_msh[8]_i_4 + (.I0(data[9]), + .I1(sig_csm_pop_child_cmd), + .I2(sig_child_addr_cntr_msh_reg[9]), + .O(\sig_child_addr_cntr_msh[8]_i_4_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \sig_child_addr_cntr_msh[8]_i_5 + (.I0(data[8]), + .I1(sig_csm_pop_child_cmd), + .I2(sig_child_addr_cntr_msh_reg[8]), + .O(\sig_child_addr_cntr_msh[8]_i_5_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_child_addr_cntr_msh_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_msh[0]_i_1_n_0 ), + .D(\sig_child_addr_cntr_msh_reg[0]_i_2_n_7 ), + .Q(sig_child_addr_cntr_msh_reg[0]), .R(sig_init_reg)); + CARRY4 \sig_child_addr_cntr_msh_reg[0]_i_2 + (.CI(1'b0), + .CO({\sig_child_addr_cntr_msh_reg[0]_i_2_n_0 ,\sig_child_addr_cntr_msh_reg[0]_i_2_n_1 ,\sig_child_addr_cntr_msh_reg[0]_i_2_n_2 ,\sig_child_addr_cntr_msh_reg[0]_i_2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,\sig_child_addr_cntr_msh[0]_i_3_n_0 }), + .O({\sig_child_addr_cntr_msh_reg[0]_i_2_n_4 ,\sig_child_addr_cntr_msh_reg[0]_i_2_n_5 ,\sig_child_addr_cntr_msh_reg[0]_i_2_n_6 ,\sig_child_addr_cntr_msh_reg[0]_i_2_n_7 }), + .S({\sig_child_addr_cntr_msh[0]_i_4_n_0 ,\sig_child_addr_cntr_msh[0]_i_5_n_0 ,\sig_child_addr_cntr_msh[0]_i_6_n_0 ,\sig_child_addr_cntr_msh[0]_i_7_n_0 })); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[25] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[43]), - .Q(sig_addr_cntr_lsh_kh[25]), + \sig_child_addr_cntr_msh_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_msh[0]_i_1_n_0 ), + .D(\sig_child_addr_cntr_msh_reg[8]_i_1_n_5 ), + .Q(sig_child_addr_cntr_msh_reg[10]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[26] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[44]), - .Q(sig_addr_cntr_lsh_kh[26]), + \sig_child_addr_cntr_msh_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_msh[0]_i_1_n_0 ), + .D(\sig_child_addr_cntr_msh_reg[8]_i_1_n_4 ), + .Q(sig_child_addr_cntr_msh_reg[11]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[27] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[45]), - .Q(sig_addr_cntr_lsh_kh[27]), + \sig_child_addr_cntr_msh_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_msh[0]_i_1_n_0 ), + .D(\sig_child_addr_cntr_msh_reg[12]_i_1_n_7 ), + .Q(sig_child_addr_cntr_msh_reg[12]), .R(sig_init_reg)); + CARRY4 \sig_child_addr_cntr_msh_reg[12]_i_1 + (.CI(\sig_child_addr_cntr_msh_reg[8]_i_1_n_0 ), + .CO({\NLW_sig_child_addr_cntr_msh_reg[12]_i_1_CO_UNCONNECTED [3],\sig_child_addr_cntr_msh_reg[12]_i_1_n_1 ,\sig_child_addr_cntr_msh_reg[12]_i_1_n_2 ,\sig_child_addr_cntr_msh_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\sig_child_addr_cntr_msh_reg[12]_i_1_n_4 ,\sig_child_addr_cntr_msh_reg[12]_i_1_n_5 ,\sig_child_addr_cntr_msh_reg[12]_i_1_n_6 ,\sig_child_addr_cntr_msh_reg[12]_i_1_n_7 }), + .S({\sig_child_addr_cntr_msh[12]_i_2_n_0 ,\sig_child_addr_cntr_msh[12]_i_3_n_0 ,\sig_child_addr_cntr_msh[12]_i_4_n_0 ,\sig_child_addr_cntr_msh[12]_i_5_n_0 })); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[28] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[46]), - .Q(sig_addr_cntr_lsh_kh[28]), + \sig_child_addr_cntr_msh_reg[13] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_msh[0]_i_1_n_0 ), + .D(\sig_child_addr_cntr_msh_reg[12]_i_1_n_6 ), + .Q(sig_child_addr_cntr_msh_reg[13]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[29] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[47]), - .Q(sig_addr_cntr_lsh_kh[29]), + \sig_child_addr_cntr_msh_reg[14] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_msh[0]_i_1_n_0 ), + .D(\sig_child_addr_cntr_msh_reg[12]_i_1_n_5 ), + .Q(sig_child_addr_cntr_msh_reg[14]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[20]), - .Q(sig_addr_cntr_lsh_kh[2]), + \sig_child_addr_cntr_msh_reg[15] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_msh[0]_i_1_n_0 ), + .D(\sig_child_addr_cntr_msh_reg[12]_i_1_n_4 ), + .Q(sig_child_addr_cntr_msh_reg[15]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[30] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[48]), - .Q(sig_addr_cntr_lsh_kh[30]), + \sig_child_addr_cntr_msh_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_msh[0]_i_1_n_0 ), + .D(\sig_child_addr_cntr_msh_reg[0]_i_2_n_6 ), + .Q(sig_child_addr_cntr_msh_reg[1]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[31] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[49]), - .Q(sig_addr_cntr_lsh_kh[31]), + \sig_child_addr_cntr_msh_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_msh[0]_i_1_n_0 ), + .D(\sig_child_addr_cntr_msh_reg[0]_i_2_n_5 ), + .Q(sig_child_addr_cntr_msh_reg[2]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[3] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[21]), - .Q(sig_addr_cntr_lsh_kh[3]), + \sig_child_addr_cntr_msh_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_msh[0]_i_1_n_0 ), + .D(\sig_child_addr_cntr_msh_reg[0]_i_2_n_4 ), + .Q(sig_child_addr_cntr_msh_reg[3]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[4] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[22]), - .Q(sig_addr_cntr_lsh_kh[4]), + \sig_child_addr_cntr_msh_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_msh[0]_i_1_n_0 ), + .D(\sig_child_addr_cntr_msh_reg[4]_i_1_n_7 ), + .Q(sig_child_addr_cntr_msh_reg[4]), .R(sig_init_reg)); + CARRY4 \sig_child_addr_cntr_msh_reg[4]_i_1 + (.CI(\sig_child_addr_cntr_msh_reg[0]_i_2_n_0 ), + .CO({\sig_child_addr_cntr_msh_reg[4]_i_1_n_0 ,\sig_child_addr_cntr_msh_reg[4]_i_1_n_1 ,\sig_child_addr_cntr_msh_reg[4]_i_1_n_2 ,\sig_child_addr_cntr_msh_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\sig_child_addr_cntr_msh_reg[4]_i_1_n_4 ,\sig_child_addr_cntr_msh_reg[4]_i_1_n_5 ,\sig_child_addr_cntr_msh_reg[4]_i_1_n_6 ,\sig_child_addr_cntr_msh_reg[4]_i_1_n_7 }), + .S({\sig_child_addr_cntr_msh[4]_i_2_n_0 ,\sig_child_addr_cntr_msh[4]_i_3_n_0 ,\sig_child_addr_cntr_msh[4]_i_4_n_0 ,\sig_child_addr_cntr_msh[4]_i_5_n_0 })); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[5] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[23]), - .Q(sig_addr_cntr_lsh_kh[5]), + \sig_child_addr_cntr_msh_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_msh[0]_i_1_n_0 ), + .D(\sig_child_addr_cntr_msh_reg[4]_i_1_n_6 ), + .Q(sig_child_addr_cntr_msh_reg[5]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[6] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[24]), - .Q(sig_addr_cntr_lsh_kh[6]), + \sig_child_addr_cntr_msh_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_msh[0]_i_1_n_0 ), + .D(\sig_child_addr_cntr_msh_reg[4]_i_1_n_5 ), + .Q(sig_child_addr_cntr_msh_reg[6]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[7] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[25]), - .Q(sig_addr_cntr_lsh_kh[7]), + \sig_child_addr_cntr_msh_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_msh[0]_i_1_n_0 ), + .D(\sig_child_addr_cntr_msh_reg[4]_i_1_n_4 ), + .Q(sig_child_addr_cntr_msh_reg[7]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[8] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[26]), - .Q(sig_addr_cntr_lsh_kh[8]), + \sig_child_addr_cntr_msh_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_msh[0]_i_1_n_0 ), + .D(\sig_child_addr_cntr_msh_reg[8]_i_1_n_7 ), + .Q(sig_child_addr_cntr_msh_reg[8]), .R(sig_init_reg)); + CARRY4 \sig_child_addr_cntr_msh_reg[8]_i_1 + (.CI(\sig_child_addr_cntr_msh_reg[4]_i_1_n_0 ), + .CO({\sig_child_addr_cntr_msh_reg[8]_i_1_n_0 ,\sig_child_addr_cntr_msh_reg[8]_i_1_n_1 ,\sig_child_addr_cntr_msh_reg[8]_i_1_n_2 ,\sig_child_addr_cntr_msh_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\sig_child_addr_cntr_msh_reg[8]_i_1_n_4 ,\sig_child_addr_cntr_msh_reg[8]_i_1_n_5 ,\sig_child_addr_cntr_msh_reg[8]_i_1_n_6 ,\sig_child_addr_cntr_msh_reg[8]_i_1_n_7 }), + .S({\sig_child_addr_cntr_msh[8]_i_2_n_0 ,\sig_child_addr_cntr_msh[8]_i_3_n_0 ,\sig_child_addr_cntr_msh[8]_i_4_n_0 ,\sig_child_addr_cntr_msh[8]_i_5_n_0 })); FDRE #( .INIT(1'b0)) - \sig_addr_cntr_lsh_kh_reg[9] - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), - .D(out[27]), - .Q(sig_addr_cntr_lsh_kh[9]), + \sig_child_addr_cntr_msh_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(\sig_child_addr_cntr_msh[0]_i_1_n_0 ), + .D(\sig_child_addr_cntr_msh_reg[8]_i_1_n_6 ), + .Q(sig_child_addr_cntr_msh_reg[9]), .R(sig_init_reg)); - (* SOFT_HLUTNM = "soft_lutpair77" *) - LUT5 #( - .INIT(32'h07F7F808)) - \sig_adjusted_addr_incr_ireg2[0]_i_1 - (.I0(sig_bytes_to_mbaa_ireg1[0]), - .I1(sig_first_xfer_im0), - .I2(sig_btt_lt_b2mbaa_ireg1), - .I3(sig_btt_residue_slice_im0[0]), - .I4(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), - .O(sig_adjusted_addr_incr_im1[0])); - LUT6 #( - .INIT(64'h9699966696669666)) - \sig_adjusted_addr_incr_ireg2[1]_i_1 - (.I0(\sig_adjusted_addr_incr_ireg2[1]_i_2_n_0 ), - .I1(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), - .I2(sig_btt_residue_slice_im0[1]), - .I3(sig_btt_lt_b2mbaa_ireg1), - .I4(sig_first_xfer_im0), - .I5(sig_bytes_to_mbaa_ireg1[1]), - .O(sig_adjusted_addr_incr_im1[1])); - (* SOFT_HLUTNM = "soft_lutpair77" *) - LUT5 #( - .INIT(32'hAA800080)) - \sig_adjusted_addr_incr_ireg2[1]_i_2 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), - .I1(sig_bytes_to_mbaa_ireg1[0]), - .I2(sig_first_xfer_im0), - .I3(sig_btt_lt_b2mbaa_ireg1), - .I4(sig_btt_residue_slice_im0[0]), - .O(\sig_adjusted_addr_incr_ireg2[1]_i_2_n_0 )); - LUT6 #( - .INIT(64'h9699966696669666)) - \sig_adjusted_addr_incr_ireg2[2]_i_1 - (.I0(\sig_adjusted_addr_incr_ireg2[2]_i_2_n_0 ), - .I1(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), - .I2(sig_btt_residue_slice_im0[2]), - .I3(sig_btt_lt_b2mbaa_ireg1), - .I4(sig_first_xfer_im0), - .I5(sig_bytes_to_mbaa_ireg1[2]), - .O(sig_adjusted_addr_incr_im1[2])); - LUT6 #( - .INIT(64'hFFEAAAEAAA800080)) - \sig_adjusted_addr_incr_ireg2[2]_i_2 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), - .I1(sig_bytes_to_mbaa_ireg1[1]), - .I2(sig_first_xfer_im0), - .I3(sig_btt_lt_b2mbaa_ireg1), - .I4(sig_btt_residue_slice_im0[1]), - .I5(\sig_adjusted_addr_incr_ireg2[1]_i_2_n_0 ), - .O(\sig_adjusted_addr_incr_ireg2[2]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair79" *) - LUT5 #( - .INIT(32'h556AAA6A)) - \sig_adjusted_addr_incr_ireg2[3]_i_1 - (.I0(\sig_adjusted_addr_incr_ireg2[3]_i_2_n_0 ), - .I1(sig_bytes_to_mbaa_ireg1[3]), - .I2(sig_first_xfer_im0), - .I3(sig_btt_lt_b2mbaa_ireg1), - .I4(sig_btt_residue_slice_im0[3]), - .O(sig_adjusted_addr_incr_im1[3])); - LUT6 #( - .INIT(64'hFFEAAAEAAA800080)) - \sig_adjusted_addr_incr_ireg2[3]_i_2 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), - .I1(sig_bytes_to_mbaa_ireg1[2]), - .I2(sig_first_xfer_im0), - .I3(sig_btt_lt_b2mbaa_ireg1), - .I4(sig_btt_residue_slice_im0[2]), - .I5(\sig_adjusted_addr_incr_ireg2[2]_i_2_n_0 ), - .O(\sig_adjusted_addr_incr_ireg2[3]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair80" *) - LUT5 #( - .INIT(32'h556AAA6A)) - \sig_adjusted_addr_incr_ireg2[4]_i_1 - (.I0(\sig_adjusted_addr_incr_ireg2[6]_i_2_n_0 ), - .I1(sig_bytes_to_mbaa_ireg1[4]), - .I2(sig_first_xfer_im0), - .I3(sig_btt_lt_b2mbaa_ireg1), - .I4(sig_btt_residue_slice_im0[4]), - .O(sig_adjusted_addr_incr_im1[4])); - LUT6 #( - .INIT(64'h757F7F7F8A808080)) - \sig_adjusted_addr_incr_ireg2[5]_i_1 - (.I0(\sig_adjusted_addr_incr_ireg2[6]_i_2_n_0 ), - .I1(sig_btt_residue_slice_im0[4]), - .I2(sig_btt_lt_b2mbaa_ireg1), - .I3(sig_first_xfer_im0), - .I4(sig_bytes_to_mbaa_ireg1[4]), - .I5(\sig_addr_cntr_incr_ireg2[5]_i_1_n_0 ), - .O(sig_adjusted_addr_incr_im1[5])); - LUT4 #( - .INIT(16'h7F80)) - \sig_adjusted_addr_incr_ireg2[6]_i_1 - (.I0(\sig_addr_cntr_incr_ireg2[4]_i_1_n_0 ), - .I1(\sig_adjusted_addr_incr_ireg2[6]_i_2_n_0 ), - .I2(\sig_addr_cntr_incr_ireg2[5]_i_1_n_0 ), - .I3(\sig_addr_cntr_incr_ireg2[6]_i_1_n_0 ), - .O(sig_adjusted_addr_incr_im1[6])); - LUT4 #( - .INIT(16'hA880)) - \sig_adjusted_addr_incr_ireg2[6]_i_2 - (.I0(\sig_addr_cntr_incr_ireg2[3]_i_1_n_0 ), - .I1(\sig_adjusted_addr_incr_ireg2[2]_i_2_n_0 ), - .I2(\sig_addr_cntr_incr_ireg2[2]_i_1_n_0 ), - .I3(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), - .O(\sig_adjusted_addr_incr_ireg2[6]_i_2_n_0 )); + LUT2 #( + .INIT(4'h2)) + sig_child_addr_lsh_rollover_reg_i_1 + (.I0(p_1_in), + .I1(sig_predict_child_addr_lsh), + .O(sig_child_addr_lsh_rollover_reg_i_1_n_0)); + LUT1 #( + .INIT(2'h2)) + sig_child_addr_lsh_rollover_reg_i_10 + (.I0(sig_child_addr_cntr_lsh_reg[10]), + .O(sig_child_addr_lsh_rollover_reg_i_10_n_0)); + LUT1 #( + .INIT(2'h2)) + sig_child_addr_lsh_rollover_reg_i_11 + (.I0(sig_child_addr_cntr_lsh_reg[9]), + .O(sig_child_addr_lsh_rollover_reg_i_11_n_0)); + LUT2 #( + .INIT(4'h6)) + sig_child_addr_lsh_rollover_reg_i_12 + (.I0(sig_child_addr_cntr_lsh_reg[8]), + .I1(\gpr1.dout_i_reg[9] [8]), + .O(sig_child_addr_lsh_rollover_reg_i_12_n_0)); + LUT2 #( + .INIT(4'h6)) + sig_child_addr_lsh_rollover_reg_i_14 + (.I0(sig_child_addr_cntr_lsh_reg[7]), + .I1(\gpr1.dout_i_reg[9] [7]), + .O(sig_child_addr_lsh_rollover_reg_i_14_n_0)); + LUT2 #( + .INIT(4'h6)) + sig_child_addr_lsh_rollover_reg_i_15 + (.I0(sig_child_addr_cntr_lsh_reg[6]), + .I1(\gpr1.dout_i_reg[9] [6]), + .O(sig_child_addr_lsh_rollover_reg_i_15_n_0)); + LUT2 #( + .INIT(4'h6)) + sig_child_addr_lsh_rollover_reg_i_16 + (.I0(sig_child_addr_cntr_lsh_reg[5]), + .I1(\gpr1.dout_i_reg[9] [5]), + .O(sig_child_addr_lsh_rollover_reg_i_16_n_0)); + LUT2 #( + .INIT(4'h6)) + sig_child_addr_lsh_rollover_reg_i_17 + (.I0(sig_child_addr_cntr_lsh_reg[4]), + .I1(\gpr1.dout_i_reg[9] [4]), + .O(sig_child_addr_lsh_rollover_reg_i_17_n_0)); + LUT2 #( + .INIT(4'h6)) + sig_child_addr_lsh_rollover_reg_i_18 + (.I0(sig_child_addr_cntr_lsh_reg[3]), + .I1(\gpr1.dout_i_reg[9] [3]), + .O(sig_child_addr_lsh_rollover_reg_i_18_n_0)); + LUT2 #( + .INIT(4'h6)) + sig_child_addr_lsh_rollover_reg_i_19 + (.I0(\sig_xfer_addr_reg_reg[2]_0 [2]), + .I1(\gpr1.dout_i_reg[9] [2]), + .O(sig_child_addr_lsh_rollover_reg_i_19_n_0)); + LUT2 #( + .INIT(4'h6)) + sig_child_addr_lsh_rollover_reg_i_20 + (.I0(\sig_xfer_addr_reg_reg[2]_0 [1]), + .I1(\gpr1.dout_i_reg[9] [1]), + .O(sig_child_addr_lsh_rollover_reg_i_20_n_0)); + LUT2 #( + .INIT(4'h6)) + sig_child_addr_lsh_rollover_reg_i_21 + (.I0(\sig_xfer_addr_reg_reg[2]_0 [0]), + .I1(\gpr1.dout_i_reg[9] [0]), + .O(sig_child_addr_lsh_rollover_reg_i_21_n_0)); + LUT1 #( + .INIT(2'h2)) + sig_child_addr_lsh_rollover_reg_i_4 + (.I0(p_1_in), + .O(sig_child_addr_lsh_rollover_reg_i_4_n_0)); + LUT1 #( + .INIT(2'h2)) + sig_child_addr_lsh_rollover_reg_i_5 + (.I0(sig_child_addr_cntr_lsh_reg[14]), + .O(sig_child_addr_lsh_rollover_reg_i_5_n_0)); + LUT1 #( + .INIT(2'h2)) + sig_child_addr_lsh_rollover_reg_i_6 + (.I0(sig_child_addr_cntr_lsh_reg[13]), + .O(sig_child_addr_lsh_rollover_reg_i_6_n_0)); + LUT1 #( + .INIT(2'h2)) + sig_child_addr_lsh_rollover_reg_i_7 + (.I0(sig_child_addr_cntr_lsh_reg[12]), + .O(sig_child_addr_lsh_rollover_reg_i_7_n_0)); + LUT1 #( + .INIT(2'h2)) + sig_child_addr_lsh_rollover_reg_i_9 + (.I0(sig_child_addr_cntr_lsh_reg[11]), + .O(sig_child_addr_lsh_rollover_reg_i_9_n_0)); FDRE #( .INIT(1'b0)) - \sig_adjusted_addr_incr_ireg2_reg[0] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc2_reg), - .D(sig_adjusted_addr_incr_im1[0]), - .Q(\sig_adjusted_addr_incr_ireg2_reg_n_0_[0] ), + sig_child_addr_lsh_rollover_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_child_addr_lsh_rollover_reg_i_1_n_0), + .Q(sig_child_addr_lsh_rollover_reg), .R(sig_init_reg)); + CARRY4 sig_child_addr_lsh_rollover_reg_reg_i_13 + (.CI(1'b0), + .CO({sig_child_addr_lsh_rollover_reg_reg_i_13_n_0,sig_child_addr_lsh_rollover_reg_reg_i_13_n_1,sig_child_addr_lsh_rollover_reg_reg_i_13_n_2,sig_child_addr_lsh_rollover_reg_reg_i_13_n_3}), + .CYINIT(1'b0), + .DI({sig_child_addr_cntr_lsh_reg[3],\sig_xfer_addr_reg_reg[2]_0 }), + .O(NLW_sig_child_addr_lsh_rollover_reg_reg_i_13_O_UNCONNECTED[3:0]), + .S({sig_child_addr_lsh_rollover_reg_i_18_n_0,sig_child_addr_lsh_rollover_reg_i_19_n_0,sig_child_addr_lsh_rollover_reg_i_20_n_0,sig_child_addr_lsh_rollover_reg_i_21_n_0})); + CARRY4 sig_child_addr_lsh_rollover_reg_reg_i_2 + (.CI(sig_child_addr_lsh_rollover_reg_reg_i_3_n_0), + .CO({NLW_sig_child_addr_lsh_rollover_reg_reg_i_2_CO_UNCONNECTED[3],sig_child_addr_lsh_rollover_reg_reg_i_2_n_1,sig_child_addr_lsh_rollover_reg_reg_i_2_n_2,sig_child_addr_lsh_rollover_reg_reg_i_2_n_3}), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({sig_predict_child_addr_lsh,NLW_sig_child_addr_lsh_rollover_reg_reg_i_2_O_UNCONNECTED[2:0]}), + .S({sig_child_addr_lsh_rollover_reg_i_4_n_0,sig_child_addr_lsh_rollover_reg_i_5_n_0,sig_child_addr_lsh_rollover_reg_i_6_n_0,sig_child_addr_lsh_rollover_reg_i_7_n_0})); + CARRY4 sig_child_addr_lsh_rollover_reg_reg_i_3 + (.CI(sig_child_addr_lsh_rollover_reg_reg_i_8_n_0), + .CO({sig_child_addr_lsh_rollover_reg_reg_i_3_n_0,sig_child_addr_lsh_rollover_reg_reg_i_3_n_1,sig_child_addr_lsh_rollover_reg_reg_i_3_n_2,sig_child_addr_lsh_rollover_reg_reg_i_3_n_3}), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,sig_child_addr_cntr_lsh_reg[8]}), + .O(NLW_sig_child_addr_lsh_rollover_reg_reg_i_3_O_UNCONNECTED[3:0]), + .S({sig_child_addr_lsh_rollover_reg_i_9_n_0,sig_child_addr_lsh_rollover_reg_i_10_n_0,sig_child_addr_lsh_rollover_reg_i_11_n_0,sig_child_addr_lsh_rollover_reg_i_12_n_0})); + CARRY4 sig_child_addr_lsh_rollover_reg_reg_i_8 + (.CI(sig_child_addr_lsh_rollover_reg_reg_i_13_n_0), + .CO({sig_child_addr_lsh_rollover_reg_reg_i_8_n_0,sig_child_addr_lsh_rollover_reg_reg_i_8_n_1,sig_child_addr_lsh_rollover_reg_reg_i_8_n_2,sig_child_addr_lsh_rollover_reg_reg_i_8_n_3}), + .CYINIT(1'b0), + .DI(sig_child_addr_cntr_lsh_reg[7:4]), + .O(NLW_sig_child_addr_lsh_rollover_reg_reg_i_8_O_UNCONNECTED[3:0]), + .S({sig_child_addr_lsh_rollover_reg_i_14_n_0,sig_child_addr_lsh_rollover_reg_i_15_n_0,sig_child_addr_lsh_rollover_reg_i_16_n_0,sig_child_addr_lsh_rollover_reg_i_17_n_0})); FDRE #( .INIT(1'b0)) - \sig_adjusted_addr_incr_ireg2_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc2_reg), - .D(sig_adjusted_addr_incr_im1[1]), - .Q(\sig_adjusted_addr_incr_ireg2_reg_n_0_[1] ), - .R(sig_init_reg)); + \sig_child_addr_reg_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[0]), + .Q(\sig_child_addr_reg_reg_n_0_[0] ), + .R(SR)); FDRE #( .INIT(1'b0)) - \sig_adjusted_addr_incr_ireg2_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc2_reg), - .D(sig_adjusted_addr_incr_im1[2]), - .Q(\sig_adjusted_addr_incr_ireg2_reg_n_0_[2] ), - .R(sig_init_reg)); + \sig_child_addr_reg_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[10]), + .Q(\sig_child_addr_reg_reg_n_0_[10] ), + .R(SR)); FDRE #( .INIT(1'b0)) - \sig_adjusted_addr_incr_ireg2_reg[3] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc2_reg), - .D(sig_adjusted_addr_incr_im1[3]), - .Q(\sig_adjusted_addr_incr_ireg2_reg_n_0_[3] ), - .R(sig_init_reg)); + \sig_child_addr_reg_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[11]), + .Q(\sig_child_addr_reg_reg_n_0_[11] ), + .R(SR)); FDRE #( .INIT(1'b0)) - \sig_adjusted_addr_incr_ireg2_reg[4] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc2_reg), - .D(sig_adjusted_addr_incr_im1[4]), - .Q(\sig_adjusted_addr_incr_ireg2_reg_n_0_[4] ), - .R(sig_init_reg)); + \sig_child_addr_reg_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[12]), + .Q(\sig_child_addr_reg_reg_n_0_[12] ), + .R(SR)); FDRE #( .INIT(1'b0)) - \sig_adjusted_addr_incr_ireg2_reg[5] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc2_reg), - .D(sig_adjusted_addr_incr_im1[5]), - .Q(\sig_adjusted_addr_incr_ireg2_reg_n_0_[5] ), - .R(sig_init_reg)); + \sig_child_addr_reg_reg[13] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[13]), + .Q(\sig_child_addr_reg_reg_n_0_[13] ), + .R(SR)); FDRE #( .INIT(1'b0)) - \sig_adjusted_addr_incr_ireg2_reg[6] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc2_reg), - .D(sig_adjusted_addr_incr_im1[6]), - .Q(\sig_adjusted_addr_incr_ireg2_reg_n_0_[6] ), - .R(sig_init_reg)); - LUT6 #( - .INIT(64'h0000000000000002)) - sig_brst_cnt_eq_one_ireg1_i_1 - (.I0(sel0[0]), - .I1(sig_brst_cnt_eq_one_ireg1_i_2_n_0), - .I2(sel0[8]), - .I3(sel0[7]), - .I4(sel0[5]), - .I5(sel0[6]), - .O(sig_brst_cnt_eq_one_im0)); - (* SOFT_HLUTNM = "soft_lutpair86" *) - LUT4 #( - .INIT(16'hFFFE)) - sig_brst_cnt_eq_one_ireg1_i_2 - (.I0(sel0[3]), - .I1(sel0[4]), - .I2(sel0[1]), - .I3(sel0[2]), - .O(sig_brst_cnt_eq_one_ireg1_i_2_n_0)); + \sig_child_addr_reg_reg[14] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[14]), + .Q(\sig_child_addr_reg_reg_n_0_[14] ), + .R(SR)); FDRE #( .INIT(1'b0)) - sig_brst_cnt_eq_one_ireg1_reg - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc1_reg), - .D(sig_brst_cnt_eq_one_im0), - .Q(sig_brst_cnt_eq_one_ireg1), - .R(sig_init_reg)); - LUT6 #( - .INIT(64'h0000000000000001)) - sig_brst_cnt_eq_zero_ireg1_i_1 - (.I0(sel0[7]), - .I1(sig_brst_cnt_eq_zero_ireg1_i_2_n_0), - .I2(sel0[6]), - .I3(sel0[8]), - .I4(sel0[4]), - .I5(sel0[5]), - .O(sig_brst_cnt_eq_zero_im0)); - (* SOFT_HLUTNM = "soft_lutpair86" *) - LUT4 #( - .INIT(16'hFFFE)) - sig_brst_cnt_eq_zero_ireg1_i_2 - (.I0(sel0[2]), - .I1(sel0[3]), - .I2(sel0[0]), - .I3(sel0[1]), - .O(sig_brst_cnt_eq_zero_ireg1_i_2_n_0)); + \sig_child_addr_reg_reg[15] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[15]), + .Q(\sig_child_addr_reg_reg_n_0_[15] ), + .R(SR)); FDRE #( .INIT(1'b0)) - sig_brst_cnt_eq_zero_ireg1_reg - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc1_reg), - .D(sig_brst_cnt_eq_zero_im0), - .Q(sig_brst_cnt_eq_zero_ireg1), - .R(sig_init_reg)); - CARRY4 sig_btt_cntr_im00_carry - (.CI(1'b0), - .CO({sig_btt_cntr_im00_carry_n_0,sig_btt_cntr_im00_carry_n_1,sig_btt_cntr_im00_carry_n_2,sig_btt_cntr_im00_carry_n_3}), - .CYINIT(1'b1), - .DI(sig_btt_residue_slice_im0[3:0]), - .O(sig_btt_cntr_im00[3:0]), - .S({sig_btt_cntr_im00_carry_i_1_n_0,sig_btt_cntr_im00_carry_i_2_n_0,sig_btt_cntr_im00_carry_i_3_n_0,sig_btt_cntr_im00_carry_i_4_n_0})); - CARRY4 sig_btt_cntr_im00_carry__0 - (.CI(sig_btt_cntr_im00_carry_n_0), - .CO({sig_btt_cntr_im00_carry__0_n_0,sig_btt_cntr_im00_carry__0_n_1,sig_btt_cntr_im00_carry__0_n_2,sig_btt_cntr_im00_carry__0_n_3}), - .CYINIT(1'b0), - .DI({sel0[0],sig_btt_residue_slice_im0[6:4]}), - .O(sig_btt_cntr_im00[7:4]), - .S({sig_btt_cntr_im00_carry__0_i_1_n_0,sig_btt_cntr_im00_carry__0_i_2_n_0,sig_btt_cntr_im00_carry__0_i_3_n_0,sig_btt_cntr_im00_carry__0_i_4_n_0})); - LUT2 #( - .INIT(4'h9)) - sig_btt_cntr_im00_carry__0_i_1 - (.I0(sel0[0]), - .I1(sig_addr_cntr_incr_ireg2[7]), - .O(sig_btt_cntr_im00_carry__0_i_1_n_0)); - LUT2 #( - .INIT(4'h9)) - sig_btt_cntr_im00_carry__0_i_2 - (.I0(sig_btt_residue_slice_im0[6]), - .I1(sig_addr_cntr_incr_ireg2[6]), - .O(sig_btt_cntr_im00_carry__0_i_2_n_0)); - LUT2 #( - .INIT(4'h9)) - sig_btt_cntr_im00_carry__0_i_3 - (.I0(sig_btt_residue_slice_im0[5]), - .I1(sig_addr_cntr_incr_ireg2[5]), - .O(sig_btt_cntr_im00_carry__0_i_3_n_0)); - LUT2 #( - .INIT(4'h9)) - sig_btt_cntr_im00_carry__0_i_4 - (.I0(sig_btt_residue_slice_im0[4]), - .I1(sig_addr_cntr_incr_ireg2[4]), - .O(sig_btt_cntr_im00_carry__0_i_4_n_0)); - CARRY4 sig_btt_cntr_im00_carry__1 - (.CI(sig_btt_cntr_im00_carry__0_n_0), - .CO({sig_btt_cntr_im00_carry__1_n_0,sig_btt_cntr_im00_carry__1_n_1,sig_btt_cntr_im00_carry__1_n_2,sig_btt_cntr_im00_carry__1_n_3}), - .CYINIT(1'b0), - .DI(sel0[4:1]), - .O(sig_btt_cntr_im00[11:8]), - .S({sig_btt_cntr_im00_carry__1_i_1_n_0,sig_btt_cntr_im00_carry__1_i_2_n_0,sig_btt_cntr_im00_carry__1_i_3_n_0,sig_btt_cntr_im00_carry__1_i_4_n_0})); - LUT1 #( - .INIT(2'h1)) - sig_btt_cntr_im00_carry__1_i_1 - (.I0(sel0[4]), - .O(sig_btt_cntr_im00_carry__1_i_1_n_0)); - LUT1 #( - .INIT(2'h1)) - sig_btt_cntr_im00_carry__1_i_2 - (.I0(sel0[3]), - .O(sig_btt_cntr_im00_carry__1_i_2_n_0)); - LUT1 #( - .INIT(2'h1)) - sig_btt_cntr_im00_carry__1_i_3 - (.I0(sel0[2]), - .O(sig_btt_cntr_im00_carry__1_i_3_n_0)); - LUT1 #( - .INIT(2'h1)) - sig_btt_cntr_im00_carry__1_i_4 - (.I0(sel0[1]), - .O(sig_btt_cntr_im00_carry__1_i_4_n_0)); - CARRY4 sig_btt_cntr_im00_carry__2 - (.CI(sig_btt_cntr_im00_carry__1_n_0), - .CO({NLW_sig_btt_cntr_im00_carry__2_CO_UNCONNECTED[3],sig_btt_cntr_im00_carry__2_n_1,sig_btt_cntr_im00_carry__2_n_2,sig_btt_cntr_im00_carry__2_n_3}), - .CYINIT(1'b0), - .DI({1'b0,sel0[7:5]}), - .O(sig_btt_cntr_im00[15:12]), - .S({sig_btt_cntr_im00_carry__2_i_1_n_0,sig_btt_cntr_im00_carry__2_i_2_n_0,sig_btt_cntr_im00_carry__2_i_3_n_0,sig_btt_cntr_im00_carry__2_i_4_n_0})); - LUT1 #( - .INIT(2'h1)) - sig_btt_cntr_im00_carry__2_i_1 - (.I0(sel0[8]), - .O(sig_btt_cntr_im00_carry__2_i_1_n_0)); - LUT1 #( - .INIT(2'h1)) - sig_btt_cntr_im00_carry__2_i_2 - (.I0(sel0[7]), - .O(sig_btt_cntr_im00_carry__2_i_2_n_0)); - LUT1 #( - .INIT(2'h1)) - sig_btt_cntr_im00_carry__2_i_3 - (.I0(sel0[6]), - .O(sig_btt_cntr_im00_carry__2_i_3_n_0)); - LUT1 #( - .INIT(2'h1)) - sig_btt_cntr_im00_carry__2_i_4 - (.I0(sel0[5]), - .O(sig_btt_cntr_im00_carry__2_i_4_n_0)); - LUT2 #( - .INIT(4'h9)) - sig_btt_cntr_im00_carry_i_1 - (.I0(sig_btt_residue_slice_im0[3]), - .I1(sig_addr_cntr_incr_ireg2[3]), - .O(sig_btt_cntr_im00_carry_i_1_n_0)); - LUT2 #( - .INIT(4'h9)) - sig_btt_cntr_im00_carry_i_2 - (.I0(sig_btt_residue_slice_im0[2]), - .I1(sig_addr_cntr_incr_ireg2[2]), - .O(sig_btt_cntr_im00_carry_i_2_n_0)); - LUT2 #( - .INIT(4'h9)) - sig_btt_cntr_im00_carry_i_3 - (.I0(sig_btt_residue_slice_im0[1]), - .I1(sig_addr_cntr_incr_ireg2[1]), - .O(sig_btt_cntr_im00_carry_i_3_n_0)); - LUT2 #( - .INIT(4'h9)) - sig_btt_cntr_im00_carry_i_4 - (.I0(sig_btt_residue_slice_im0[0]), - .I1(sig_addr_cntr_incr_ireg2[0]), - .O(sig_btt_cntr_im00_carry_i_4_n_0)); - LUT6 #( - .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_btt_cntr_im0[0]_i_1 - (.I0(out[0]), - .I1(sig_btt_cntr_im00[0]), - .I2(in[37]), - .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(\sig_btt_cntr_im0[0]_i_1_n_0 )); - LUT6 #( - .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_btt_cntr_im0[10]_i_1 - (.I0(out[10]), - .I1(sig_btt_cntr_im00[10]), - .I2(in[37]), - .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(\sig_btt_cntr_im0[10]_i_1_n_0 )); - LUT6 #( - .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_btt_cntr_im0[11]_i_1 - (.I0(out[11]), - .I1(sig_btt_cntr_im00[11]), - .I2(in[37]), - .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(\sig_btt_cntr_im0[11]_i_1_n_0 )); - LUT6 #( - .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_btt_cntr_im0[12]_i_1 - (.I0(out[12]), - .I1(sig_btt_cntr_im00[12]), - .I2(in[37]), - .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(\sig_btt_cntr_im0[12]_i_1_n_0 )); - LUT6 #( - .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_btt_cntr_im0[13]_i_1 - (.I0(out[13]), - .I1(sig_btt_cntr_im00[13]), - .I2(in[37]), - .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(\sig_btt_cntr_im0[13]_i_1_n_0 )); - LUT6 #( - .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_btt_cntr_im0[14]_i_1 - (.I0(out[14]), - .I1(sig_btt_cntr_im00[14]), - .I2(in[37]), - .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(\sig_btt_cntr_im0[14]_i_1_n_0 )); - LUT6 #( - .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_btt_cntr_im0[15]_i_1 - (.I0(out[15]), - .I1(sig_btt_cntr_im00[15]), - .I2(in[37]), - .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(\sig_btt_cntr_im0[15]_i_1_n_0 )); - LUT6 #( - .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_btt_cntr_im0[1]_i_1 - (.I0(out[1]), - .I1(sig_btt_cntr_im00[1]), - .I2(in[37]), - .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(\sig_btt_cntr_im0[1]_i_1_n_0 )); - LUT6 #( - .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_btt_cntr_im0[2]_i_1 - (.I0(out[2]), - .I1(sig_btt_cntr_im00[2]), - .I2(in[37]), - .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(\sig_btt_cntr_im0[2]_i_1_n_0 )); - LUT6 #( - .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_btt_cntr_im0[3]_i_1 - (.I0(out[3]), - .I1(sig_btt_cntr_im00[3]), - .I2(in[37]), - .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(\sig_btt_cntr_im0[3]_i_1_n_0 )); - LUT6 #( - .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_btt_cntr_im0[4]_i_1 - (.I0(out[4]), - .I1(sig_btt_cntr_im00[4]), - .I2(in[37]), - .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(\sig_btt_cntr_im0[4]_i_1_n_0 )); - LUT6 #( - .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_btt_cntr_im0[5]_i_1 - (.I0(out[5]), - .I1(sig_btt_cntr_im00[5]), - .I2(in[37]), - .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(\sig_btt_cntr_im0[5]_i_1_n_0 )); - LUT6 #( - .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_btt_cntr_im0[6]_i_1 - (.I0(out[6]), - .I1(sig_btt_cntr_im00[6]), - .I2(in[37]), - .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(\sig_btt_cntr_im0[6]_i_1_n_0 )); - LUT6 #( - .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_btt_cntr_im0[7]_i_1 - (.I0(out[7]), - .I1(sig_btt_cntr_im00[7]), - .I2(in[37]), - .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(\sig_btt_cntr_im0[7]_i_1_n_0 )); - LUT6 #( - .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_btt_cntr_im0[8]_i_1 - (.I0(out[8]), - .I1(sig_btt_cntr_im00[8]), - .I2(in[37]), - .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(\sig_btt_cntr_im0[8]_i_1_n_0 )); - LUT6 #( - .INIT(64'hCCCCCCCCCCCCCACC)) - \sig_btt_cntr_im0[9]_i_1 - (.I0(out[9]), - .I1(sig_btt_cntr_im00[9]), - .I2(in[37]), - .I3(sig_input_reg_empty), - .I4(sig_sm_halt_reg), - .I5(Q), - .O(\sig_btt_cntr_im0[9]_i_1_n_0 )); + \sig_child_addr_reg_reg[16] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[16]), + .Q(data[0]), + .R(SR)); FDRE #( .INIT(1'b0)) - \sig_btt_cntr_im0_reg[0] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(\sig_btt_cntr_im0[0]_i_1_n_0 ), - .Q(sig_btt_residue_slice_im0[0]), - .R(sig_init_reg)); + \sig_child_addr_reg_reg[17] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[17]), + .Q(data[1]), + .R(SR)); FDRE #( .INIT(1'b0)) - \sig_btt_cntr_im0_reg[10] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(\sig_btt_cntr_im0[10]_i_1_n_0 ), - .Q(sel0[3]), - .R(sig_init_reg)); + \sig_child_addr_reg_reg[18] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[18]), + .Q(data[2]), + .R(SR)); FDRE #( .INIT(1'b0)) - \sig_btt_cntr_im0_reg[11] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(\sig_btt_cntr_im0[11]_i_1_n_0 ), - .Q(sel0[4]), - .R(sig_init_reg)); + \sig_child_addr_reg_reg[19] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[19]), + .Q(data[3]), + .R(SR)); FDRE #( .INIT(1'b0)) - \sig_btt_cntr_im0_reg[12] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(\sig_btt_cntr_im0[12]_i_1_n_0 ), - .Q(sel0[5]), - .R(sig_init_reg)); + \sig_child_addr_reg_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[1]), + .Q(\sig_child_addr_reg_reg_n_0_[1] ), + .R(SR)); FDRE #( .INIT(1'b0)) - \sig_btt_cntr_im0_reg[13] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(\sig_btt_cntr_im0[13]_i_1_n_0 ), - .Q(sel0[6]), - .R(sig_init_reg)); + \sig_child_addr_reg_reg[20] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[20]), + .Q(data[4]), + .R(SR)); FDRE #( .INIT(1'b0)) - \sig_btt_cntr_im0_reg[14] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(\sig_btt_cntr_im0[14]_i_1_n_0 ), - .Q(sel0[7]), - .R(sig_init_reg)); + \sig_child_addr_reg_reg[21] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[21]), + .Q(data[5]), + .R(SR)); FDRE #( .INIT(1'b0)) - \sig_btt_cntr_im0_reg[15] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(\sig_btt_cntr_im0[15]_i_1_n_0 ), - .Q(sel0[8]), - .R(sig_init_reg)); + \sig_child_addr_reg_reg[22] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[22]), + .Q(data[6]), + .R(SR)); FDRE #( .INIT(1'b0)) - \sig_btt_cntr_im0_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(\sig_btt_cntr_im0[1]_i_1_n_0 ), - .Q(sig_btt_residue_slice_im0[1]), - .R(sig_init_reg)); + \sig_child_addr_reg_reg[23] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[23]), + .Q(data[7]), + .R(SR)); FDRE #( .INIT(1'b0)) - \sig_btt_cntr_im0_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(\sig_btt_cntr_im0[2]_i_1_n_0 ), - .Q(sig_btt_residue_slice_im0[2]), - .R(sig_init_reg)); + \sig_child_addr_reg_reg[24] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[24]), + .Q(data[8]), + .R(SR)); FDRE #( .INIT(1'b0)) - \sig_btt_cntr_im0_reg[3] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(\sig_btt_cntr_im0[3]_i_1_n_0 ), - .Q(sig_btt_residue_slice_im0[3]), - .R(sig_init_reg)); + \sig_child_addr_reg_reg[25] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[25]), + .Q(data[9]), + .R(SR)); FDRE #( .INIT(1'b0)) - \sig_btt_cntr_im0_reg[4] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(\sig_btt_cntr_im0[4]_i_1_n_0 ), - .Q(sig_btt_residue_slice_im0[4]), - .R(sig_init_reg)); + \sig_child_addr_reg_reg[26] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[26]), + .Q(data[10]), + .R(SR)); FDRE #( .INIT(1'b0)) - \sig_btt_cntr_im0_reg[5] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(\sig_btt_cntr_im0[5]_i_1_n_0 ), - .Q(sig_btt_residue_slice_im0[5]), - .R(sig_init_reg)); + \sig_child_addr_reg_reg[27] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[27]), + .Q(data[11]), + .R(SR)); FDRE #( .INIT(1'b0)) - \sig_btt_cntr_im0_reg[6] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(\sig_btt_cntr_im0[6]_i_1_n_0 ), - .Q(sig_btt_residue_slice_im0[6]), - .R(sig_init_reg)); + \sig_child_addr_reg_reg[28] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[28]), + .Q(data[12]), + .R(SR)); FDRE #( .INIT(1'b0)) - \sig_btt_cntr_im0_reg[7] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(\sig_btt_cntr_im0[7]_i_1_n_0 ), - .Q(sel0[0]), - .R(sig_init_reg)); + \sig_child_addr_reg_reg[29] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[29]), + .Q(data[13]), + .R(SR)); FDRE #( .INIT(1'b0)) - \sig_btt_cntr_im0_reg[8] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(\sig_btt_cntr_im0[8]_i_1_n_0 ), - .Q(sel0[1]), + \sig_child_addr_reg_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[2]), + .Q(\sig_child_addr_reg_reg_n_0_[2] ), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \sig_child_addr_reg_reg[30] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[30]), + .Q(data[14]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \sig_child_addr_reg_reg[31] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[31]), + .Q(data[15]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \sig_child_addr_reg_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[3]), + .Q(\sig_child_addr_reg_reg_n_0_[3] ), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \sig_child_addr_reg_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[4]), + .Q(\sig_child_addr_reg_reg_n_0_[4] ), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \sig_child_addr_reg_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[5]), + .Q(\sig_child_addr_reg_reg_n_0_[5] ), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \sig_child_addr_reg_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[6]), + .Q(\sig_child_addr_reg_reg_n_0_[6] ), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \sig_child_addr_reg_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[7]), + .Q(\sig_child_addr_reg_reg_n_0_[7] ), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \sig_child_addr_reg_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[8]), + .Q(\sig_child_addr_reg_reg_n_0_[8] ), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \sig_child_addr_reg_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_addr_reg[9]), + .Q(\sig_child_addr_reg_reg_n_0_[9] ), + .R(SR)); + FDRE #( + .INIT(1'b0)) + sig_child_burst_type_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_input_burst_type_reg), + .Q(sig_child_burst_type_reg), + .R(SR)); + FDRE #( + .INIT(1'b0)) + sig_child_cmd_reg_full_reg + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_psm_ld_chcmd_reg), + .Q(sig_child_cmd_reg_full), + .R(SR)); + FDRE #( + .INIT(1'b0)) + sig_child_error_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(p_10_out), + .Q(sig_child_error_reg), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair224" *) + LUT3 #( + .INIT(8'hB8)) + sig_child_qual_burst_type_i_1 + (.I0(sig_child_burst_type_reg), + .I1(sig_csm_pop_child_cmd), + .I2(sig_child_qual_burst_type), + .O(sig_child_qual_burst_type_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + sig_child_qual_burst_type_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_child_qual_burst_type_i_1_n_0), + .Q(sig_child_qual_burst_type), .R(sig_init_reg)); + (* SOFT_HLUTNM = "soft_lutpair224" *) + LUT3 #( + .INIT(8'hB8)) + sig_child_qual_error_reg_i_1 + (.I0(sig_child_error_reg), + .I1(sig_csm_pop_child_cmd), + .I2(sig_child_qual_error_reg), + .O(sig_child_qual_error_reg_i_1_n_0)); FDRE #( .INIT(1'b0)) - \sig_btt_cntr_im0_reg[9] - (.C(m_axi_mm2s_aclk), - .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), - .D(\sig_btt_cntr_im0[9]_i_1_n_0 ), - .Q(sel0[2]), + sig_child_qual_error_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_child_qual_error_reg_i_1_n_0), + .Q(sig_child_qual_error_reg), .R(sig_init_reg)); LUT6 #( - .INIT(64'h8008008000000000)) - sig_btt_eq_b2mbaa_ireg1_i_1 - (.I0(sig_btt_eq_b2mbaa_ireg1_i_2_n_0), - .I1(sig_btt_eq_b2mbaa_ireg1_i_3_n_0), - .I2(sig_btt_residue_slice_im0[6]), - .I3(sig_btt_eq_b2mbaa_ireg1_i_4_n_0), - .I4(\sig_addr_cntr_lsh_im0_reg_n_0_[6] ), - .I5(sig_brst_cnt_eq_zero_im0), - .O(sig_btt_eq_b2mbaa_im0)); - LUT6 #( - .INIT(64'h0210084020048001)) - sig_btt_eq_b2mbaa_ireg1_i_2 - (.I0(sig_btt_residue_slice_im0[0]), - .I1(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), - .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), - .I3(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), - .I4(sig_btt_residue_slice_im0[2]), - .I5(sig_btt_residue_slice_im0[1]), - .O(sig_btt_eq_b2mbaa_ireg1_i_2_n_0)); - LUT6 #( - .INIT(64'h9009000000009009)) - sig_btt_eq_b2mbaa_ireg1_i_3 - (.I0(sig_btt_residue_slice_im0[3]), - .I1(\sig_bytes_to_mbaa_ireg1[3]_i_1_n_0 ), - .I2(\sig_bytes_to_mbaa_ireg1[5]_i_1_n_0 ), - .I3(sig_btt_residue_slice_im0[5]), - .I4(\sig_bytes_to_mbaa_ireg1[4]_i_1_n_0 ), - .I5(sig_btt_residue_slice_im0[4]), - .O(sig_btt_eq_b2mbaa_ireg1_i_3_n_0)); - LUT6 #( - .INIT(64'h0000000000000001)) - sig_btt_eq_b2mbaa_ireg1_i_4 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[4] ), - .I1(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), - .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), - .I3(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), - .I4(\sig_addr_cntr_lsh_im0_reg_n_0_[3] ), - .I5(\sig_addr_cntr_lsh_im0_reg_n_0_[5] ), - .O(sig_btt_eq_b2mbaa_ireg1_i_4_n_0)); + .INIT(64'h0000000000E2E2E2)) + sig_child_qual_first_of_2_i_1 + (.I0(sig_child_qual_first_of_2), + .I1(sig_csm_pop_child_cmd), + .I2(sig_needed_2_realign_cmds), + .I3(p_32_out), + .I4(\gpr1.dout_i_reg[9] [9]), + .I5(sig_init_reg), + .O(sig_child_qual_first_of_2_i_1_n_0)); FDRE #( .INIT(1'b0)) - sig_btt_eq_b2mbaa_ireg1_reg - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc1_reg), - .D(sig_btt_eq_b2mbaa_im0), - .Q(sig_btt_eq_b2mbaa_ireg1), + sig_child_qual_first_of_2_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_child_qual_first_of_2_i_1_n_0), + .Q(sig_child_qual_first_of_2), + .R(1'b0)); + LUT5 #( + .INIT(32'h0000CFAA)) + sig_cmd2addr_valid_i_1 + (.I0(sig_csm_ld_xfer), + .I1(FIFO_Full_reg_1), + .I2(sig_inhibit_rdy_n_1), + .I3(p_22_out), + .I4(sig_init_reg), + .O(sig_cmd2addr_valid_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + sig_cmd2addr_valid_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_cmd2addr_valid_i_1_n_0), + .Q(p_22_out), + .R(1'b0)); + LUT5 #( + .INIT(32'h0000CFAA)) + sig_cmd2data_valid_i_1 + (.I0(sig_csm_ld_xfer), + .I1(FIFO_Full_reg_0), + .I2(sig_inhibit_rdy_n_0), + .I3(p_11_out), + .I4(sig_init_reg), + .O(sig_cmd2data_valid_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + sig_cmd2data_valid_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_cmd2data_valid_i_1_n_0), + .Q(p_11_out), + .R(1'b0)); + LUT5 #( + .INIT(32'h00010008)) + sig_csm_ld_xfer_i_1 + (.I0(sig_csm_state[2]), + .I1(sig_csm_state[0]), + .I2(p_22_out), + .I3(p_11_out), + .I4(sig_csm_state[1]), + .O(sig_csm_ld_xfer_ns)); + FDRE #( + .INIT(1'b0)) + sig_csm_ld_xfer_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_csm_ld_xfer_ns), + .Q(sig_csm_ld_xfer), .R(sig_init_reg)); - CARRY4 sig_btt_lt_b2mbaa_im01_carry - (.CI(1'b0), - .CO({sig_btt_lt_b2mbaa_im01,sig_btt_lt_b2mbaa_im01_carry_n_1,sig_btt_lt_b2mbaa_im01_carry_n_2,sig_btt_lt_b2mbaa_im01_carry_n_3}), - .CYINIT(1'b0), - .DI({sig_btt_lt_b2mbaa_im01_carry_i_1_n_0,sig_btt_lt_b2mbaa_im01_carry_i_2_n_0,sig_btt_lt_b2mbaa_im01_carry_i_3_n_0,sig_btt_lt_b2mbaa_im01_carry_i_4_n_0}), - .O(NLW_sig_btt_lt_b2mbaa_im01_carry_O_UNCONNECTED[3:0]), - .S({sig_btt_lt_b2mbaa_im01_carry_i_5_n_0,sig_btt_lt_b2mbaa_im01_carry_i_6_n_0,sig_btt_lt_b2mbaa_im01_carry_i_7_n_0,sig_btt_lt_b2mbaa_im01_carry_i_8_n_0})); - LUT3 #( - .INIT(8'h71)) - sig_btt_lt_b2mbaa_im01_carry_i_1 - (.I0(sig_btt_residue_slice_im0[6]), - .I1(\sig_addr_cntr_lsh_im0_reg_n_0_[6] ), - .I2(sig_btt_eq_b2mbaa_ireg1_i_4_n_0), - .O(sig_btt_lt_b2mbaa_im01_carry_i_1_n_0)); - LUT4 #( - .INIT(16'h2F02)) - sig_btt_lt_b2mbaa_im01_carry_i_2 - (.I0(\sig_bytes_to_mbaa_ireg1[4]_i_1_n_0 ), - .I1(sig_btt_residue_slice_im0[4]), - .I2(sig_btt_residue_slice_im0[5]), - .I3(\sig_bytes_to_mbaa_ireg1[5]_i_1_n_0 ), - .O(sig_btt_lt_b2mbaa_im01_carry_i_2_n_0)); - LUT6 #( - .INIT(64'h0101011337373770)) - sig_btt_lt_b2mbaa_im01_carry_i_3 - (.I0(sig_btt_residue_slice_im0[2]), - .I1(sig_btt_residue_slice_im0[3]), - .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), - .I3(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), - .I4(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), - .I5(\sig_addr_cntr_lsh_im0_reg_n_0_[3] ), - .O(sig_btt_lt_b2mbaa_im01_carry_i_3_n_0)); - LUT4 #( - .INIT(16'h1370)) - sig_btt_lt_b2mbaa_im01_carry_i_4 - (.I0(sig_btt_residue_slice_im0[0]), - .I1(sig_btt_residue_slice_im0[1]), - .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), - .I3(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), - .O(sig_btt_lt_b2mbaa_im01_carry_i_4_n_0)); - LUT3 #( - .INIT(8'h86)) - sig_btt_lt_b2mbaa_im01_carry_i_5 - (.I0(sig_btt_residue_slice_im0[6]), - .I1(\sig_addr_cntr_lsh_im0_reg_n_0_[6] ), - .I2(sig_btt_eq_b2mbaa_ireg1_i_4_n_0), - .O(sig_btt_lt_b2mbaa_im01_carry_i_5_n_0)); - LUT4 #( - .INIT(16'h9009)) - sig_btt_lt_b2mbaa_im01_carry_i_6 - (.I0(\sig_bytes_to_mbaa_ireg1[4]_i_1_n_0 ), - .I1(sig_btt_residue_slice_im0[4]), - .I2(\sig_bytes_to_mbaa_ireg1[5]_i_1_n_0 ), - .I3(sig_btt_residue_slice_im0[5]), - .O(sig_btt_lt_b2mbaa_im01_carry_i_6_n_0)); - LUT6 #( - .INIT(64'h0001666866680001)) - sig_btt_lt_b2mbaa_im01_carry_i_7 - (.I0(sig_btt_residue_slice_im0[2]), - .I1(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), - .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), - .I3(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), - .I4(\sig_addr_cntr_lsh_im0_reg_n_0_[3] ), - .I5(sig_btt_residue_slice_im0[3]), - .O(sig_btt_lt_b2mbaa_im01_carry_i_7_n_0)); LUT4 #( - .INIT(16'h1881)) - sig_btt_lt_b2mbaa_im01_carry_i_8 - (.I0(sig_btt_residue_slice_im0[0]), - .I1(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), - .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), - .I3(sig_btt_residue_slice_im0[1]), - .O(sig_btt_lt_b2mbaa_im01_carry_i_8_n_0)); - LUT2 #( - .INIT(4'h8)) - sig_btt_lt_b2mbaa_ireg1_i_1 - (.I0(sig_btt_lt_b2mbaa_im01), - .I1(sig_brst_cnt_eq_zero_im0), - .O(sig_btt_lt_b2mbaa_im0)); + .INIT(16'h0040)) + sig_csm_pop_child_cmd_i_1 + (.I0(sig_csm_state[1]), + .I1(sig_child_cmd_reg_full), + .I2(sig_csm_state[0]), + .I3(sig_csm_state[2]), + .O(sig_csm_pop_child_cmd_ns)); FDRE #( .INIT(1'b0)) - sig_btt_lt_b2mbaa_ireg1_reg - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc1_reg), - .D(sig_btt_lt_b2mbaa_im0), - .Q(sig_btt_lt_b2mbaa_ireg1), + sig_csm_pop_child_cmd_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_csm_pop_child_cmd_ns), + .Q(sig_csm_pop_child_cmd), .R(sig_init_reg)); - (* SOFT_HLUTNM = "soft_lutpair76" *) LUT5 #( - .INIT(32'hFFFFFFFE)) - \sig_byte_change_minus1_im2/i_ - (.I0(\sig_adjusted_addr_incr_ireg2_reg_n_0_[3] ), - .I1(\sig_adjusted_addr_incr_ireg2_reg_n_0_[1] ), - .I2(\sig_adjusted_addr_incr_ireg2_reg_n_0_[0] ), - .I3(\sig_adjusted_addr_incr_ireg2_reg_n_0_[2] ), - .I4(\sig_adjusted_addr_incr_ireg2_reg_n_0_[4] ), - .O(\sig_byte_change_minus1_im2/i__n_0 )); - LUT2 #( - .INIT(4'h6)) - \sig_bytes_to_mbaa_ireg1[1]_i_1 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), - .I1(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), - .O(\sig_bytes_to_mbaa_ireg1[1]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair103" *) - LUT3 #( - .INIT(8'h1E)) - \sig_bytes_to_mbaa_ireg1[2]_i_1 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), - .I1(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), - .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), - .O(\sig_bytes_to_mbaa_ireg1[2]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair78" *) - LUT4 #( - .INIT(16'h01FE)) - \sig_bytes_to_mbaa_ireg1[3]_i_1 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), - .I1(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), - .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), - .I3(\sig_addr_cntr_lsh_im0_reg_n_0_[3] ), - .O(\sig_bytes_to_mbaa_ireg1[3]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair78" *) - LUT5 #( - .INIT(32'h0001FFFE)) - \sig_bytes_to_mbaa_ireg1[4]_i_1 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[3] ), - .I1(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), - .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), - .I3(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), - .I4(\sig_addr_cntr_lsh_im0_reg_n_0_[4] ), - .O(\sig_bytes_to_mbaa_ireg1[4]_i_1_n_0 )); - LUT6 #( - .INIT(64'h00000001FFFFFFFE)) - \sig_bytes_to_mbaa_ireg1[5]_i_1 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[4] ), - .I1(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), - .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), - .I3(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), - .I4(\sig_addr_cntr_lsh_im0_reg_n_0_[3] ), - .I5(\sig_addr_cntr_lsh_im0_reg_n_0_[5] ), - .O(\sig_bytes_to_mbaa_ireg1[5]_i_1_n_0 )); - LUT6 #( - .INIT(64'h00000010FFFFFFEF)) - \sig_bytes_to_mbaa_ireg1[6]_i_1 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[5] ), - .I1(\sig_addr_cntr_lsh_im0_reg_n_0_[3] ), - .I2(\sig_bytes_to_mbaa_ireg1[7]_i_2_n_0 ), - .I3(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), - .I4(\sig_addr_cntr_lsh_im0_reg_n_0_[4] ), - .I5(\sig_addr_cntr_lsh_im0_reg_n_0_[6] ), - .O(\sig_bytes_to_mbaa_ireg1[6]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0000000000000010)) - \sig_bytes_to_mbaa_ireg1[7]_i_1 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[5] ), - .I1(\sig_addr_cntr_lsh_im0_reg_n_0_[3] ), - .I2(\sig_bytes_to_mbaa_ireg1[7]_i_2_n_0 ), - .I3(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), - .I4(\sig_addr_cntr_lsh_im0_reg_n_0_[4] ), - .I5(\sig_addr_cntr_lsh_im0_reg_n_0_[6] ), - .O(\sig_bytes_to_mbaa_ireg1[7]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair103" *) - LUT2 #( - .INIT(4'h1)) - \sig_bytes_to_mbaa_ireg1[7]_i_2 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), - .I1(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), - .O(\sig_bytes_to_mbaa_ireg1[7]_i_2_n_0 )); + .INIT(32'h01000000)) + sig_csm_pop_sf_fifo_i_1 + (.I0(sig_csm_state[1]), + .I1(p_11_out), + .I2(p_22_out), + .I3(sig_csm_state[0]), + .I4(sig_csm_state[2]), + .O(sig_csm_pop_sf_fifo_ns)); FDRE #( .INIT(1'b0)) - \sig_bytes_to_mbaa_ireg1_reg[0] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc1_reg), - .D(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), - .Q(sig_bytes_to_mbaa_ireg1[0]), + sig_csm_pop_sf_fifo_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_csm_pop_sf_fifo_ns), + .Q(p_32_out), .R(sig_init_reg)); + LUT4 #( + .INIT(16'h00F2)) + sig_first_realigner_cmd_i_1 + (.I0(sig_first_realigner_cmd), + .I1(sig_psm_ld_realigner_reg), + .I2(\sig_input_addr_reg[31]_i_2_n_0 ), + .I3(sig_init_reg), + .O(sig_first_realigner_cmd_i_1_n_0)); FDRE #( .INIT(1'b0)) - \sig_bytes_to_mbaa_ireg1_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc1_reg), - .D(\sig_bytes_to_mbaa_ireg1[1]_i_1_n_0 ), - .Q(sig_bytes_to_mbaa_ireg1[1]), - .R(sig_init_reg)); + sig_first_realigner_cmd_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_first_realigner_cmd_i_1_n_0), + .Q(sig_first_realigner_cmd), + .R(1'b0)); + LUT4 #( + .INIT(16'h0004)) + \sig_input_addr_reg[31]_i_2 + (.I0(Q), + .I1(sig_input_reg_empty), + .I2(sig_psm_halt), + .I3(p_10_out), + .O(\sig_input_addr_reg[31]_i_2_n_0 )); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) - \sig_bytes_to_mbaa_ireg1_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc1_reg), - .D(\sig_bytes_to_mbaa_ireg1[2]_i_1_n_0 ), - .Q(sig_bytes_to_mbaa_ireg1[2]), - .R(sig_init_reg)); + \sig_input_addr_reg_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[18]), + .Q(sig_input_addr_reg[0]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) - \sig_bytes_to_mbaa_ireg1_reg[3] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc1_reg), - .D(\sig_bytes_to_mbaa_ireg1[3]_i_1_n_0 ), - .Q(sig_bytes_to_mbaa_ireg1[3]), - .R(sig_init_reg)); + \sig_input_addr_reg_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[28]), + .Q(sig_input_addr_reg[10]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) - \sig_bytes_to_mbaa_ireg1_reg[4] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc1_reg), - .D(\sig_bytes_to_mbaa_ireg1[4]_i_1_n_0 ), - .Q(sig_bytes_to_mbaa_ireg1[4]), - .R(sig_init_reg)); + \sig_input_addr_reg_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[29]), + .Q(sig_input_addr_reg[11]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) - \sig_bytes_to_mbaa_ireg1_reg[5] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc1_reg), - .D(\sig_bytes_to_mbaa_ireg1[5]_i_1_n_0 ), - .Q(sig_bytes_to_mbaa_ireg1[5]), - .R(sig_init_reg)); + \sig_input_addr_reg_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[30]), + .Q(sig_input_addr_reg[12]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) - \sig_bytes_to_mbaa_ireg1_reg[6] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc1_reg), - .D(\sig_bytes_to_mbaa_ireg1[6]_i_1_n_0 ), - .Q(sig_bytes_to_mbaa_ireg1[6]), - .R(sig_init_reg)); + \sig_input_addr_reg_reg[13] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[31]), + .Q(sig_input_addr_reg[13]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) - \sig_bytes_to_mbaa_ireg1_reg[7] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc1_reg), - .D(\sig_bytes_to_mbaa_ireg1[7]_i_1_n_0 ), - .Q(sig_bytes_to_mbaa_ireg1[7]), - .R(sig_init_reg)); - (* SOFT_HLUTNM = "soft_lutpair81" *) - LUT4 #( - .INIT(16'hFF80)) - sig_calc_error_pushed_i_1 - (.I0(in[37]), - .I1(sig_xfer_reg_empty), - .I2(sig_ld_xfer_reg), - .I3(sig_calc_error_pushed), - .O(sig_calc_error_pushed_i_1_n_0)); + \sig_input_addr_reg_reg[14] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[32]), + .Q(sig_input_addr_reg[14]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) - sig_calc_error_pushed_reg - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(sig_calc_error_pushed_i_1_n_0), - .Q(sig_calc_error_pushed), - .R(sig_init_reg)); + \sig_input_addr_reg_reg[15] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[33]), + .Q(sig_input_addr_reg[15]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) - sig_calc_error_reg_reg - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\INFERRED_GEN.cnt_i_reg[2] ), - .Q(in[37]), - .R(sig_init_reg)); - LUT6 #( - .INIT(64'h000000000000AAAE)) - sig_cmd2addr_valid_i_1 - (.I0(sig_mstr2addr_cmd_valid), - .I1(sig_pcc_sm_state[2]), - .I2(sig_pcc_sm_state[0]), - .I3(sig_pcc_sm_state[1]), - .I4(sig_wr_fifo_0), - .I5(sig_init_reg), - .O(sig_cmd2addr_valid_i_1_n_0)); + \sig_input_addr_reg_reg[16] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[34]), + .Q(sig_input_addr_reg[16]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) - sig_cmd2addr_valid_reg - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(sig_cmd2addr_valid_i_1_n_0), - .Q(sig_mstr2addr_cmd_valid), - .R(1'b0)); - LUT6 #( - .INIT(64'h000000000000AAAE)) - sig_cmd2data_valid_i_1 - (.I0(sig_mstr2data_cmd_valid), - .I1(sig_pcc_sm_state[2]), - .I2(sig_pcc_sm_state[0]), - .I3(sig_pcc_sm_state[1]), - .I4(sig_wr_fifo), - .I5(sig_init_reg), - .O(sig_cmd2data_valid_i_1_n_0)); + \sig_input_addr_reg_reg[17] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[35]), + .Q(sig_input_addr_reg[17]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) - sig_cmd2data_valid_reg - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(sig_cmd2data_valid_i_1_n_0), - .Q(sig_mstr2data_cmd_valid), - .R(1'b0)); - LUT6 #( - .INIT(64'h00000000F808F8F8)) - sig_cmd2dre_valid_i_1 - (.I0(sig_sm_ld_xfer_reg_ns), - .I1(sig_first_xfer_im0), - .I2(sig_mstr2sf_cmd_valid), - .I3(FIFO_Full_reg_0), - .I4(sig_inhibit_rdy_n), - .I5(sig_init_reg), - .O(sig_cmd2dre_valid_i_1_n_0)); - LUT3 #( - .INIT(8'h02)) - sig_cmd2dre_valid_i_2 - (.I0(sig_pcc_sm_state[2]), - .I1(sig_pcc_sm_state[0]), - .I2(sig_pcc_sm_state[1]), - .O(sig_sm_ld_xfer_reg_ns)); + \sig_input_addr_reg_reg[18] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[36]), + .Q(sig_input_addr_reg[18]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) - sig_cmd2dre_valid_reg - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(sig_cmd2dre_valid_i_1_n_0), - .Q(sig_mstr2sf_cmd_valid), - .R(1'b0)); - LUT4 #( - .INIT(16'h000E)) - sig_first_xfer_im0_i_1 - (.I0(sig_first_xfer_im0), - .I1(sig_push_input_reg11_out), - .I2(sig_pop_xfer_reg0_out), - .I3(sig_init_reg), - .O(sig_first_xfer_im0_i_1_n_0)); + \sig_input_addr_reg_reg[19] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[37]), + .Q(sig_input_addr_reg[19]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) - sig_first_xfer_im0_reg - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(sig_first_xfer_im0_i_1_n_0), - .Q(sig_first_xfer_im0), - .R(1'b0)); - (* SOFT_HLUTNM = "soft_lutpair82" *) - LUT4 #( - .INIT(16'h0080)) - sig_init_done_i_1 - (.I0(sig_init_reg), - .I1(sig_init_reg2), - .I2(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .I3(sig_init_done), - .O(sig_init_done_reg)); - (* SOFT_HLUTNM = "soft_lutpair82" *) - LUT4 #( - .INIT(16'h0080)) - sig_init_done_i_1__0 - (.I0(sig_init_reg), - .I1(sig_init_reg2), - .I2(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .I3(sig_init_done_2), - .O(sig_init_done_reg_0)); - (* SOFT_HLUTNM = "soft_lutpair83" *) - LUT4 #( - .INIT(16'h0080)) - sig_init_done_i_1__2 - (.I0(sig_init_reg), - .I1(sig_init_reg2), - .I2(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .I3(sig_init_done_3), - .O(sig_init_done_reg_1)); - (* SOFT_HLUTNM = "soft_lutpair83" *) - LUT4 #( - .INIT(16'h0080)) - sig_init_done_i_1__3 - (.I0(sig_init_reg), - .I1(sig_init_reg2), - .I2(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .I3(sig_init_done_4), - .O(sig_init_done_reg_2)); - LUT3 #( - .INIT(8'hFE)) - sig_input_burst_type_reg_i_1 - (.I0(sig_calc_error_pushed), - .I1(sig_init_reg), - .I2(sig_sm_pop_input_reg), - .O(sig_input_cache_type_reg0)); - LUT4 #( - .INIT(16'h0004)) - sig_input_burst_type_reg_i_2 - (.I0(in[37]), - .I1(sig_input_reg_empty), - .I2(sig_sm_halt_reg), - .I3(Q), - .O(sig_push_input_reg11_out)); + \sig_input_addr_reg_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[19]), + .Q(sig_input_addr_reg[1]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_input_addr_reg_reg[20] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[38]), + .Q(sig_input_addr_reg[20]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_input_addr_reg_reg[21] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[39]), + .Q(sig_input_addr_reg[21]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_input_addr_reg_reg[22] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[40]), + .Q(sig_input_addr_reg[22]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_input_addr_reg_reg[23] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[41]), + .Q(sig_input_addr_reg[23]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_input_addr_reg_reg[24] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[42]), + .Q(sig_input_addr_reg[24]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_input_addr_reg_reg[25] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[43]), + .Q(sig_input_addr_reg[25]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_input_addr_reg_reg[26] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[44]), + .Q(sig_input_addr_reg[26]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_input_addr_reg_reg[27] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[45]), + .Q(sig_input_addr_reg[27]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_input_addr_reg_reg[28] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[46]), + .Q(sig_input_addr_reg[28]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_input_addr_reg_reg[29] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[47]), + .Q(sig_input_addr_reg[29]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_input_addr_reg_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[20]), + .Q(sig_input_addr_reg[2]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_input_addr_reg_reg[30] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[48]), + .Q(sig_input_addr_reg[30]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_input_addr_reg_reg[31] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[49]), + .Q(sig_input_addr_reg[31]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_input_addr_reg_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[21]), + .Q(sig_input_addr_reg[3]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_input_addr_reg_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[22]), + .Q(sig_input_addr_reg[4]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_input_addr_reg_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[23]), + .Q(sig_input_addr_reg[5]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_input_addr_reg_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[24]), + .Q(sig_input_addr_reg[6]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_input_addr_reg_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[25]), + .Q(sig_input_addr_reg[7]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_input_addr_reg_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[26]), + .Q(sig_input_addr_reg[8]), + .R(sig_input_cache_type_reg0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_input_addr_reg_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(out[27]), + .Q(sig_input_addr_reg[9]), + .R(sig_input_cache_type_reg0)); FDRE #( .INIT(1'b0)) sig_input_burst_type_reg_reg - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), .D(out[16]), - .Q(in[36]), + .Q(sig_input_burst_type_reg), .R(sig_input_cache_type_reg0)); FDRE #( .INIT(1'b0)) sig_input_eof_reg_reg - (.C(m_axi_mm2s_aclk), - .CE(sig_push_input_reg11_out), + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), .D(out[17]), - .Q(sig_mstr2sf_eof), + .Q(sig_input_eof_reg), .R(sig_input_cache_type_reg0)); - LUT5 #( - .INIT(32'hFFFFFFF2)) - sig_input_reg_empty_i_1 - (.I0(sig_input_reg_empty), - .I1(sig_push_input_reg11_out), - .I2(sig_sm_pop_input_reg), - .I3(sig_init_reg), - .I4(sig_calc_error_pushed), - .O(sig_input_reg_empty_i_1_n_0)); - FDRE #( + FDSE #( .INIT(1'b0)) sig_input_reg_empty_reg - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(sig_input_reg_empty_i_1_n_0), + (.C(m_axi_s2mm_aclk), + .CE(\sig_input_addr_reg[31]_i_2_n_0 ), + .D(1'b0), .Q(sig_input_reg_empty), - .R(1'b0)); - LUT6 #( - .INIT(64'h000000000002FF02)) - sig_ld_xfer_reg_i_1 - (.I0(sig_pcc_sm_state[2]), - .I1(sig_pcc_sm_state[0]), - .I2(sig_pcc_sm_state[1]), - .I3(sig_ld_xfer_reg), - .I4(sig_xfer_reg_empty), - .I5(sig_init_reg), - .O(sig_ld_xfer_reg_i_1_n_0)); + .S(sig_input_cache_type_reg0)); + LUT1 #( + .INIT(2'h1)) + sig_needed_2_realign_cmds_i_1 + (.I0(sig_skip_align2mbaa_s_h), + .O(sig_needed_2_realign_cmds_i_1_n_0)); FDRE #( .INIT(1'b0)) - sig_ld_xfer_reg_reg - (.C(m_axi_mm2s_aclk), + sig_needed_2_realign_cmds_reg + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_chcmd_reg), + .D(sig_needed_2_realign_cmds_i_1_n_0), + .Q(sig_needed_2_realign_cmds), + .R(SR)); + LUT2 #( + .INIT(4'h1)) + sig_psm_halt_i_1 + (.I0(sig_psm_state[0]), + .I1(sig_psm_state[1]), + .O(sig_psm_halt_ns)); + FDSE #( + .INIT(1'b0)) + sig_psm_halt_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(sig_ld_xfer_reg_i_1_n_0), - .Q(sig_ld_xfer_reg), - .R(1'b0)); - LUT6 #( - .INIT(64'h000000000000AAAE)) - sig_ld_xfer_reg_tmp_i_1 - (.I0(sig_ld_xfer_reg_tmp), - .I1(sig_pcc_sm_state[2]), - .I2(sig_pcc_sm_state[0]), - .I3(sig_pcc_sm_state[1]), - .I4(sig_pop_xfer_reg0_out), - .I5(sig_init_reg), - .O(sig_ld_xfer_reg_tmp_i_1_n_0)); + .D(sig_psm_halt_ns), + .Q(sig_psm_halt), + .S(sig_init_reg)); + LUT4 #( + .INIT(16'h1000)) + sig_psm_ld_calc1_i_1 + (.I0(sig_psm_state[0]), + .I1(sig_psm_state[2]), + .I2(sig_psm_state[1]), + .I3(sig_realign_reg_empty), + .O(sig_psm_ld_calc1_ns)); FDRE #( .INIT(1'b0)) - sig_ld_xfer_reg_tmp_reg - (.C(m_axi_mm2s_aclk), + sig_psm_ld_calc1_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(sig_ld_xfer_reg_tmp_i_1_n_0), - .Q(sig_ld_xfer_reg_tmp), - .R(1'b0)); + .D(sig_psm_ld_calc1_ns), + .Q(sig_psm_ld_calc1), + .R(sig_init_reg)); + LUT4 #( + .INIT(16'h1000)) + sig_psm_ld_chcmd_reg_i_1 + (.I0(sig_child_cmd_reg_full), + .I1(sig_psm_state[2]), + .I2(sig_psm_state[0]), + .I3(sig_psm_state[1]), + .O(sig_psm_ld_chcmd_reg_ns)); FDRE #( .INIT(1'b0)) - sig_mmap_reset_reg_reg - (.C(m_axi_mm2s_aclk), + sig_psm_ld_chcmd_reg_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(SR), - .Q(sig_init_reg), - .R(1'b0)); - LUT4 #( - .INIT(16'h0001)) - sig_no_btt_residue_ireg1_i_1 - (.I0(sig_btt_residue_slice_im0[6]), - .I1(sig_btt_residue_slice_im0[4]), - .I2(sig_btt_residue_slice_im0[5]), - .I3(sig_no_btt_residue_ireg1_i_2_n_0), - .O(sig_no_btt_residue_im0)); + .D(sig_psm_ld_chcmd_reg_ns), + .Q(sig_psm_ld_chcmd_reg), + .R(sig_init_reg)); LUT4 #( - .INIT(16'hFFFE)) - sig_no_btt_residue_ireg1_i_2 - (.I0(sig_btt_residue_slice_im0[2]), - .I1(sig_btt_residue_slice_im0[3]), - .I2(sig_btt_residue_slice_im0[0]), - .I3(sig_btt_residue_slice_im0[1]), - .O(sig_no_btt_residue_ireg1_i_2_n_0)); + .INIT(16'h0820)) + sig_psm_ld_realigner_reg_i_1 + (.I0(sig_realign_reg_empty), + .I1(sig_psm_state[2]), + .I2(sig_psm_state[1]), + .I3(sig_psm_state[0]), + .O(sig_psm_ld_realigner_reg_ns)); FDRE #( .INIT(1'b0)) - sig_no_btt_residue_ireg1_reg - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc1_reg), - .D(sig_no_btt_residue_im0), - .Q(sig_no_btt_residue_ireg1), + sig_psm_ld_realigner_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_psm_ld_realigner_reg_ns), + .Q(sig_psm_ld_realigner_reg), .R(sig_init_reg)); LUT5 #( - .INIT(32'h000000E2)) - sig_parent_done_i_1 - (.I0(sig_parent_done), - .I1(sig_ld_xfer_reg_tmp), - .I2(sig_last_xfer_valid_im1), - .I3(sig_push_input_reg11_out), - .I4(sig_init_reg), - .O(sig_parent_done_i_1_n_0)); + .INIT(32'hAA800080)) + sig_psm_pop_input_cmd_i_1 + (.I0(sig_psm_state[0]), + .I1(sig_realign_reg_empty), + .I2(sig_psm_state[2]), + .I3(sig_psm_state[1]), + .I4(sig_psm_pop_input_cmd_i_2_n_0), + .O(sig_psm_pop_input_cmd_ns)); + LUT5 #( + .INIT(32'h00000054)) + sig_psm_pop_input_cmd_i_2 + (.I0(sig_child_cmd_reg_full), + .I1(sig_skip_align2mbaa_s_h), + .I2(sig_psm_state_ns2__0), + .I3(p_10_out), + .I4(sig_psm_state[2]), + .O(sig_psm_pop_input_cmd_i_2_n_0)); FDRE #( .INIT(1'b0)) - sig_parent_done_reg - (.C(m_axi_mm2s_aclk), + sig_psm_pop_input_cmd_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(sig_parent_done_i_1_n_0), - .Q(sig_parent_done), - .R(1'b0)); - LUT1 #( - .INIT(2'h2)) - \sig_predict_addr_lsh_ireg3[11]_i_2 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[11] ), - .O(\sig_predict_addr_lsh_ireg3[11]_i_2_n_0 )); - LUT1 #( - .INIT(2'h2)) - \sig_predict_addr_lsh_ireg3[11]_i_3 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[10] ), - .O(\sig_predict_addr_lsh_ireg3[11]_i_3_n_0 )); - LUT1 #( - .INIT(2'h2)) - \sig_predict_addr_lsh_ireg3[11]_i_4 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[9] ), - .O(\sig_predict_addr_lsh_ireg3[11]_i_4_n_0 )); - LUT1 #( - .INIT(2'h2)) - \sig_predict_addr_lsh_ireg3[11]_i_5 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[8] ), - .O(\sig_predict_addr_lsh_ireg3[11]_i_5_n_0 )); - LUT1 #( - .INIT(2'h2)) - \sig_predict_addr_lsh_ireg3[15]_i_2 - (.I0(p_1_in_0), - .O(\sig_predict_addr_lsh_ireg3[15]_i_2_n_0 )); - LUT1 #( - .INIT(2'h2)) - \sig_predict_addr_lsh_ireg3[15]_i_3 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[14] ), - .O(\sig_predict_addr_lsh_ireg3[15]_i_3_n_0 )); - LUT1 #( - .INIT(2'h2)) - \sig_predict_addr_lsh_ireg3[15]_i_4 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[13] ), - .O(\sig_predict_addr_lsh_ireg3[15]_i_4_n_0 )); - LUT1 #( - .INIT(2'h2)) - \sig_predict_addr_lsh_ireg3[15]_i_5 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[12] ), - .O(\sig_predict_addr_lsh_ireg3[15]_i_5_n_0 )); - LUT2 #( - .INIT(4'h6)) - \sig_predict_addr_lsh_ireg3[3]_i_2 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[3] ), - .I1(sig_addr_cntr_incr_ireg2[3]), - .O(\sig_predict_addr_lsh_ireg3[3]_i_2_n_0 )); - LUT2 #( - .INIT(4'h6)) - \sig_predict_addr_lsh_ireg3[3]_i_3 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), - .I1(sig_addr_cntr_incr_ireg2[2]), - .O(\sig_predict_addr_lsh_ireg3[3]_i_3_n_0 )); - LUT2 #( - .INIT(4'h6)) - \sig_predict_addr_lsh_ireg3[3]_i_4 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), - .I1(sig_addr_cntr_incr_ireg2[1]), - .O(\sig_predict_addr_lsh_ireg3[3]_i_4_n_0 )); - LUT2 #( - .INIT(4'h6)) - \sig_predict_addr_lsh_ireg3[3]_i_5 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), - .I1(sig_addr_cntr_incr_ireg2[0]), - .O(\sig_predict_addr_lsh_ireg3[3]_i_5_n_0 )); - LUT2 #( - .INIT(4'h6)) - \sig_predict_addr_lsh_ireg3[7]_i_2 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[7] ), - .I1(sig_addr_cntr_incr_ireg2[7]), - .O(\sig_predict_addr_lsh_ireg3[7]_i_2_n_0 )); - LUT2 #( - .INIT(4'h6)) - \sig_predict_addr_lsh_ireg3[7]_i_3 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[6] ), - .I1(sig_addr_cntr_incr_ireg2[6]), - .O(\sig_predict_addr_lsh_ireg3[7]_i_3_n_0 )); - LUT2 #( - .INIT(4'h6)) - \sig_predict_addr_lsh_ireg3[7]_i_4 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[5] ), - .I1(sig_addr_cntr_incr_ireg2[5]), - .O(\sig_predict_addr_lsh_ireg3[7]_i_4_n_0 )); - LUT2 #( - .INIT(4'h6)) - \sig_predict_addr_lsh_ireg3[7]_i_5 - (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[4] ), - .I1(sig_addr_cntr_incr_ireg2[4]), - .O(\sig_predict_addr_lsh_ireg3[7]_i_5_n_0 )); + .D(sig_psm_pop_input_cmd_ns), + .Q(sig_psm_pop_input_cmd), + .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_predict_addr_lsh_ireg3_reg[0] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc3_reg), - .D(sig_predict_addr_lsh_im2[0]), - .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[0] ), - .R(sig_init_reg)); + \sig_realign_btt_reg_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_realigner_reg), + .D(sig_realigner_btt2[0]), + .Q(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [0]), + .R(sig_realign_tag_reg0)); FDRE #( .INIT(1'b0)) - \sig_predict_addr_lsh_ireg3_reg[10] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc3_reg), - .D(sig_predict_addr_lsh_im2[10]), - .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[10] ), - .R(sig_init_reg)); + \sig_realign_btt_reg_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_realigner_reg), + .D(sig_realigner_btt2[10]), + .Q(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [10]), + .R(sig_realign_tag_reg0)); FDRE #( .INIT(1'b0)) - \sig_predict_addr_lsh_ireg3_reg[11] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc3_reg), - .D(sig_predict_addr_lsh_im2[11]), - .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[11] ), - .R(sig_init_reg)); - CARRY4 \sig_predict_addr_lsh_ireg3_reg[11]_i_1 - (.CI(\sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_0 ), - .CO({\sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_0 ,\sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_1 ,\sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_2 ,\sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_3 }), - .CYINIT(1'b0), - .DI({\sig_addr_cntr_lsh_im0_reg_n_0_[11] ,\sig_addr_cntr_lsh_im0_reg_n_0_[10] ,\sig_addr_cntr_lsh_im0_reg_n_0_[9] ,\sig_addr_cntr_lsh_im0_reg_n_0_[8] }), - .O(sig_predict_addr_lsh_im2[11:8]), - .S({\sig_predict_addr_lsh_ireg3[11]_i_2_n_0 ,\sig_predict_addr_lsh_ireg3[11]_i_3_n_0 ,\sig_predict_addr_lsh_ireg3[11]_i_4_n_0 ,\sig_predict_addr_lsh_ireg3[11]_i_5_n_0 })); + \sig_realign_btt_reg_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_realigner_reg), + .D(sig_realigner_btt2[11]), + .Q(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [11]), + .R(sig_realign_tag_reg0)); FDRE #( .INIT(1'b0)) - \sig_predict_addr_lsh_ireg3_reg[12] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc3_reg), - .D(sig_predict_addr_lsh_im2[12]), - .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[12] ), - .R(sig_init_reg)); + \sig_realign_btt_reg_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_realigner_reg), + .D(sig_realigner_btt2[12]), + .Q(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [12]), + .R(sig_realign_tag_reg0)); FDRE #( .INIT(1'b0)) - \sig_predict_addr_lsh_ireg3_reg[13] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc3_reg), - .D(sig_predict_addr_lsh_im2[13]), - .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[13] ), - .R(sig_init_reg)); + \sig_realign_btt_reg_reg[13] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_realigner_reg), + .D(sig_realigner_btt2[13]), + .Q(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [13]), + .R(sig_realign_tag_reg0)); FDRE #( .INIT(1'b0)) - \sig_predict_addr_lsh_ireg3_reg[14] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc3_reg), - .D(sig_predict_addr_lsh_im2[14]), - .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[14] ), - .R(sig_init_reg)); + \sig_realign_btt_reg_reg[14] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_realigner_reg), + .D(sig_realigner_btt2[14]), + .Q(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [14]), + .R(sig_realign_tag_reg0)); FDRE #( .INIT(1'b0)) - \sig_predict_addr_lsh_ireg3_reg[15] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc3_reg), - .D(sig_predict_addr_lsh_im2[15]), - .Q(sig_predict_addr_lsh_ireg3), - .R(sig_init_reg)); - CARRY4 \sig_predict_addr_lsh_ireg3_reg[15]_i_1 - (.CI(\sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_0 ), - .CO({\NLW_sig_predict_addr_lsh_ireg3_reg[15]_i_1_CO_UNCONNECTED [3],\sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_1 ,\sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_2 ,\sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_3 }), - .CYINIT(1'b0), - .DI({1'b0,\sig_addr_cntr_lsh_im0_reg_n_0_[14] ,\sig_addr_cntr_lsh_im0_reg_n_0_[13] ,\sig_addr_cntr_lsh_im0_reg_n_0_[12] }), - .O(sig_predict_addr_lsh_im2[15:12]), - .S({\sig_predict_addr_lsh_ireg3[15]_i_2_n_0 ,\sig_predict_addr_lsh_ireg3[15]_i_3_n_0 ,\sig_predict_addr_lsh_ireg3[15]_i_4_n_0 ,\sig_predict_addr_lsh_ireg3[15]_i_5_n_0 })); + \sig_realign_btt_reg_reg[15] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_realigner_reg), + .D(sig_realigner_btt2[15]), + .Q(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [15]), + .R(sig_realign_tag_reg0)); FDRE #( .INIT(1'b0)) - \sig_predict_addr_lsh_ireg3_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc3_reg), - .D(sig_predict_addr_lsh_im2[1]), - .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[1] ), - .R(sig_init_reg)); + \sig_realign_btt_reg_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_realigner_reg), + .D(sig_realigner_btt2[1]), + .Q(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [1]), + .R(sig_realign_tag_reg0)); FDRE #( .INIT(1'b0)) - \sig_predict_addr_lsh_ireg3_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc3_reg), - .D(sig_predict_addr_lsh_im2[2]), - .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[2] ), - .R(sig_init_reg)); + \sig_realign_btt_reg_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_realigner_reg), + .D(sig_realigner_btt2[2]), + .Q(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [2]), + .R(sig_realign_tag_reg0)); FDRE #( .INIT(1'b0)) - \sig_predict_addr_lsh_ireg3_reg[3] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc3_reg), - .D(sig_predict_addr_lsh_im2[3]), - .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[3] ), - .R(sig_init_reg)); - CARRY4 \sig_predict_addr_lsh_ireg3_reg[3]_i_1 - (.CI(1'b0), - .CO({\sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_0 ,\sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_1 ,\sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_2 ,\sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_3 }), - .CYINIT(1'b0), - .DI({\sig_addr_cntr_lsh_im0_reg_n_0_[3] ,\sig_addr_cntr_lsh_im0_reg_n_0_[2] ,\sig_addr_cntr_lsh_im0_reg_n_0_[1] ,\sig_addr_cntr_lsh_im0_reg_n_0_[0] }), - .O(sig_predict_addr_lsh_im2[3:0]), - .S({\sig_predict_addr_lsh_ireg3[3]_i_2_n_0 ,\sig_predict_addr_lsh_ireg3[3]_i_3_n_0 ,\sig_predict_addr_lsh_ireg3[3]_i_4_n_0 ,\sig_predict_addr_lsh_ireg3[3]_i_5_n_0 })); + \sig_realign_btt_reg_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_realigner_reg), + .D(sig_realigner_btt2[3]), + .Q(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [3]), + .R(sig_realign_tag_reg0)); FDRE #( .INIT(1'b0)) - \sig_predict_addr_lsh_ireg3_reg[4] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc3_reg), - .D(sig_predict_addr_lsh_im2[4]), - .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[4] ), - .R(sig_init_reg)); + \sig_realign_btt_reg_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_realigner_reg), + .D(sig_realigner_btt2[4]), + .Q(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [4]), + .R(sig_realign_tag_reg0)); FDRE #( .INIT(1'b0)) - \sig_predict_addr_lsh_ireg3_reg[5] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc3_reg), - .D(sig_predict_addr_lsh_im2[5]), - .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[5] ), - .R(sig_init_reg)); + \sig_realign_btt_reg_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_realigner_reg), + .D(sig_realigner_btt2[5]), + .Q(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [5]), + .R(sig_realign_tag_reg0)); FDRE #( .INIT(1'b0)) - \sig_predict_addr_lsh_ireg3_reg[6] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc3_reg), - .D(sig_predict_addr_lsh_im2[6]), - .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[6] ), + \sig_realign_btt_reg_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_realigner_reg), + .D(sig_realigner_btt2[6]), + .Q(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [6]), + .R(sig_realign_tag_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_realign_btt_reg_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_realigner_reg), + .D(sig_realigner_btt2[7]), + .Q(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [7]), + .R(sig_realign_tag_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_realign_btt_reg_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_realigner_reg), + .D(sig_realigner_btt2[8]), + .Q(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [8]), + .R(sig_realign_tag_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_realign_btt_reg_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_realigner_reg), + .D(sig_realigner_btt2[9]), + .Q(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [9]), + .R(sig_realign_tag_reg0)); + FDRE #( + .INIT(1'b0)) + sig_realign_calc_err_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_realigner_reg), + .D(p_10_out), + .Q(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [18]), + .R(sig_realign_tag_reg0)); + (* SOFT_HLUTNM = "soft_lutpair221" *) + LUT3 #( + .INIT(8'hEF)) + sig_realign_cmd_cmplt_reg_i_1 + (.I0(sig_psm_state_ns2__0), + .I1(p_10_out), + .I2(sig_first_realigner_cmd), + .O(sig_realign_cmd_cmplt_reg_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + sig_realign_cmd_cmplt_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_realigner_reg), + .D(sig_realign_cmd_cmplt_reg_i_1_n_0), + .Q(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [17]), + .R(sig_realign_tag_reg0)); + (* SOFT_HLUTNM = "soft_lutpair221" *) + LUT3 #( + .INIT(8'hA2)) + sig_realign_eof_reg_i_1 + (.I0(sig_input_eof_reg), + .I1(sig_first_realigner_cmd), + .I2(sig_psm_state_ns2__0), + .O(sig_realign_eof_reg0)); + FDRE #( + .INIT(1'b0)) + sig_realign_eof_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_realigner_reg), + .D(sig_realign_eof_reg0), + .Q(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [16]), + .R(sig_realign_tag_reg0)); + FDSE #( + .INIT(1'b0)) + sig_realign_reg_empty_reg + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_realigner_reg), + .D(1'b0), + .Q(sig_realign_reg_empty), + .S(sig_realign_tag_reg0)); + LUT5 #( + .INIT(32'hAAAAAEAA)) + sig_realign_reg_full_i_1 + (.I0(sig_init_reg), + .I1(p_9_out_0), + .I2(sig_psm_ld_realigner_reg), + .I3(sig_inhibit_rdy_n), + .I4(FIFO_Full_reg), + .O(sig_realign_tag_reg0)); + FDRE #( + .INIT(1'b0)) + sig_realign_reg_full_reg + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_realigner_reg), + .D(sig_psm_ld_realigner_reg), + .Q(p_9_out_0), + .R(sig_realign_tag_reg0)); + LUT2 #( + .INIT(4'h8)) + \sig_realign_strt_offset_reg[0]_i_1 + (.I0(sig_psm_ld_calc1), + .I1(sig_input_addr_reg[0]), + .O(sig_realign_strt_offset[0])); + LUT2 #( + .INIT(4'h8)) + \sig_realign_strt_offset_reg[1]_i_1 + (.I0(sig_psm_ld_calc1), + .I1(sig_input_addr_reg[1]), + .O(sig_realign_strt_offset[1])); + LUT2 #( + .INIT(4'h8)) + \sig_realign_strt_offset_reg[2]_i_1 + (.I0(sig_psm_ld_calc1), + .I1(sig_input_addr_reg[2]), + .O(sig_realign_strt_offset[2])); + FDRE #( + .INIT(1'b0)) + \sig_realign_strt_offset_reg_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_realigner_reg), + .D(sig_realign_strt_offset[0]), + .Q(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [19]), + .R(sig_realign_tag_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_realign_strt_offset_reg_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_realigner_reg), + .D(sig_realign_strt_offset[1]), + .Q(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [20]), + .R(sig_realign_tag_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_realign_strt_offset_reg_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(sig_psm_ld_realigner_reg), + .D(sig_realign_strt_offset[2]), + .Q(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [21]), + .R(sig_realign_tag_reg0)); + LUT4 #( + .INIT(16'h22F0)) + \sig_realigner_btt2[0]_i_1 + (.I0(sig_input_addr_reg[0]), + .I1(sig_addr_aligned__6), + .I2(sig_btt_residue_slice[0]), + .I3(\sig_realigner_btt2[8]_i_3_n_0 ), + .O(sig_realigner_btt[0])); + (* SOFT_HLUTNM = "soft_lutpair222" *) + LUT3 #( + .INIT(8'hD0)) + \sig_realigner_btt2[10]_i_1 + (.I0(sig_first_realigner_cmd), + .I1(sig_skip_align2mbaa), + .I2(sel0[1]), + .O(sig_realigner_btt[10])); + (* SOFT_HLUTNM = "soft_lutpair223" *) + LUT3 #( + .INIT(8'hD0)) + \sig_realigner_btt2[11]_i_1 + (.I0(sig_first_realigner_cmd), + .I1(sig_skip_align2mbaa), + .I2(sel0[2]), + .O(sig_realigner_btt[11])); + (* SOFT_HLUTNM = "soft_lutpair223" *) + LUT3 #( + .INIT(8'hD0)) + \sig_realigner_btt2[12]_i_1 + (.I0(sig_first_realigner_cmd), + .I1(sig_skip_align2mbaa), + .I2(sel0[3]), + .O(sig_realigner_btt[12])); + (* SOFT_HLUTNM = "soft_lutpair222" *) + LUT3 #( + .INIT(8'hD0)) + \sig_realigner_btt2[13]_i_1 + (.I0(sig_first_realigner_cmd), + .I1(sig_skip_align2mbaa), + .I2(sel0[4]), + .O(sig_realigner_btt[13])); + LUT3 #( + .INIT(8'hD0)) + \sig_realigner_btt2[14]_i_1 + (.I0(sig_first_realigner_cmd), + .I1(sig_skip_align2mbaa), + .I2(sel0[5]), + .O(sig_realigner_btt[14])); + LUT6 #( + .INIT(64'hFFFFFFFF20202000)) + \sig_realigner_btt2[15]_i_1 + (.I0(sig_first_realigner_cmd), + .I1(sig_skip_align2mbaa), + .I2(\sig_realigner_btt2[15]_i_4_n_0 ), + .I3(sig_btt_lt_b2mbaa2), + .I4(sig_btt_eq_b2mbaa2), + .I5(sig_init_reg), + .O(\sig_realigner_btt2[15]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair220" *) + LUT3 #( + .INIT(8'hD0)) + \sig_realigner_btt2[15]_i_2 + (.I0(sig_first_realigner_cmd), + .I1(sig_skip_align2mbaa), + .I2(sel0[6]), + .O(sig_realigner_btt[15])); + LUT5 #( + .INIT(32'hFFFFEEEA)) + \sig_realigner_btt2[15]_i_3 + (.I0(sig_addr_aligned__6), + .I1(\sig_realigner_btt2[15]_i_4_n_0 ), + .I2(sig_btt_lt_b2mbaa2), + .I3(sig_btt_eq_b2mbaa2), + .I4(p_10_out), + .O(sig_skip_align2mbaa)); + LUT5 #( + .INIT(32'h00010000)) + \sig_realigner_btt2[15]_i_4 + (.I0(\sig_realigner_btt2[15]_i_5_n_0 ), + .I1(sel0[5]), + .I2(sel0[4]), + .I3(sel0[6]), + .I4(sig_first_realigner_cmd), + .O(\sig_realigner_btt2[15]_i_4_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \sig_realigner_btt2[15]_i_5 + (.I0(sel0[2]), + .I1(sel0[3]), + .I2(sel0[0]), + .I3(sel0[1]), + .O(\sig_realigner_btt2[15]_i_5_n_0 )); + LUT5 #( + .INIT(32'h0606FF00)) + \sig_realigner_btt2[1]_i_1 + (.I0(sig_input_addr_reg[1]), + .I1(sig_input_addr_reg[0]), + .I2(sig_addr_aligned__6), + .I3(sig_btt_residue_slice[1]), + .I4(\sig_realigner_btt2[8]_i_3_n_0 ), + .O(sig_realigner_btt[1])); + LUT6 #( + .INIT(64'h00560056FFFF0000)) + \sig_realigner_btt2[2]_i_1 + (.I0(sig_input_addr_reg[2]), + .I1(sig_input_addr_reg[0]), + .I2(sig_input_addr_reg[1]), + .I3(sig_addr_aligned__6), + .I4(sig_btt_residue_slice[2]), + .I5(\sig_realigner_btt2[8]_i_3_n_0 ), + .O(sig_realigner_btt[2])); + LUT5 #( + .INIT(32'h00000001)) + \sig_realigner_btt2[2]_i_2 + (.I0(sig_input_addr_reg[5]), + .I1(sig_input_addr_reg[4]), + .I2(sig_input_addr_reg[6]), + .I3(sig_input_addr_reg[7]), + .I4(\sig_realigner_btt2[2]_i_3_n_0 ), + .O(sig_addr_aligned__6)); + LUT4 #( + .INIT(16'hFFFE)) + \sig_realigner_btt2[2]_i_3 + (.I0(sig_input_addr_reg[2]), + .I1(sig_input_addr_reg[3]), + .I2(sig_input_addr_reg[0]), + .I3(sig_input_addr_reg[1]), + .O(\sig_realigner_btt2[2]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair218" *) + LUT3 #( + .INIT(8'hAC)) + \sig_realigner_btt2[3]_i_1 + (.I0(sig_bytes_to_mbaa__8[3]), + .I1(sig_btt_residue_slice[3]), + .I2(\sig_realigner_btt2[8]_i_3_n_0 ), + .O(sig_realigner_btt[3])); + LUT5 #( + .INIT(32'h00005556)) + \sig_realigner_btt2[3]_i_2 + (.I0(sig_input_addr_reg[3]), + .I1(sig_input_addr_reg[1]), + .I2(sig_input_addr_reg[0]), + .I3(sig_input_addr_reg[2]), + .I4(sig_addr_aligned__6), + .O(sig_bytes_to_mbaa__8[3])); + (* SOFT_HLUTNM = "soft_lutpair219" *) + LUT3 #( + .INIT(8'hAC)) + \sig_realigner_btt2[4]_i_1 + (.I0(sig_bytes_to_mbaa__8[4]), + .I1(sig_btt_residue_slice[4]), + .I2(\sig_realigner_btt2[8]_i_3_n_0 ), + .O(sig_realigner_btt[4])); + LUT6 #( + .INIT(64'h0000000055555556)) + \sig_realigner_btt2[4]_i_2 + (.I0(sig_input_addr_reg[4]), + .I1(sig_input_addr_reg[2]), + .I2(sig_input_addr_reg[0]), + .I3(sig_input_addr_reg[1]), + .I4(sig_input_addr_reg[3]), + .I5(sig_addr_aligned__6), + .O(sig_bytes_to_mbaa__8[4])); + (* SOFT_HLUTNM = "soft_lutpair218" *) + LUT3 #( + .INIT(8'hAC)) + \sig_realigner_btt2[5]_i_1 + (.I0(sig_bytes_to_mbaa__8[5]), + .I1(sig_btt_residue_slice[5]), + .I2(\sig_realigner_btt2[8]_i_3_n_0 ), + .O(sig_realigner_btt[5])); + LUT3 #( + .INIT(8'h09)) + \sig_realigner_btt2[5]_i_2 + (.I0(sig_input_addr_reg[5]), + .I1(\sig_realigner_btt2[5]_i_3_n_0 ), + .I2(sig_addr_aligned__6), + .O(sig_bytes_to_mbaa__8[5])); + LUT5 #( + .INIT(32'h00000001)) + \sig_realigner_btt2[5]_i_3 + (.I0(sig_input_addr_reg[3]), + .I1(sig_input_addr_reg[1]), + .I2(sig_input_addr_reg[0]), + .I3(sig_input_addr_reg[2]), + .I4(sig_input_addr_reg[4]), + .O(\sig_realigner_btt2[5]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair217" *) + LUT3 #( + .INIT(8'hAC)) + \sig_realigner_btt2[6]_i_1 + (.I0(sig_bytes_to_mbaa__8[6]), + .I1(sig_btt_residue_slice[6]), + .I2(\sig_realigner_btt2[8]_i_3_n_0 ), + .O(sig_realigner_btt[6])); + LUT3 #( + .INIT(8'h09)) + \sig_realigner_btt2[6]_i_2 + (.I0(sig_input_addr_reg[6]), + .I1(sig_btt_lt_b2mbaa2_carry_i_9_n_0), + .I2(sig_addr_aligned__6), + .O(sig_bytes_to_mbaa__8[6])); + (* SOFT_HLUTNM = "soft_lutpair219" *) + LUT3 #( + .INIT(8'hAC)) + \sig_realigner_btt2[7]_i_1 + (.I0(sig_bytes_to_mbaa__8[7]), + .I1(sig_btt_residue_slice[7]), + .I2(\sig_realigner_btt2[8]_i_3_n_0 ), + .O(sig_realigner_btt[7])); + LUT4 #( + .INIT(16'h0059)) + \sig_realigner_btt2[7]_i_2 + (.I0(sig_input_addr_reg[7]), + .I1(sig_btt_lt_b2mbaa2_carry_i_9_n_0), + .I2(sig_input_addr_reg[6]), + .I3(sig_addr_aligned__6), + .O(sig_bytes_to_mbaa__8[7])); + (* SOFT_HLUTNM = "soft_lutpair217" *) + LUT3 #( + .INIT(8'hAC)) + \sig_realigner_btt2[8]_i_1 + (.I0(sig_bytes_to_mbaa), + .I1(sig_btt_residue_slice[8]), + .I2(\sig_realigner_btt2[8]_i_3_n_0 ), + .O(sig_realigner_btt[8])); + LUT4 #( + .INIT(16'hFF04)) + \sig_realigner_btt2[8]_i_2 + (.I0(sig_input_addr_reg[7]), + .I1(sig_btt_lt_b2mbaa2_carry_i_9_n_0), + .I2(sig_input_addr_reg[6]), + .I3(sig_addr_aligned__6), + .O(sig_bytes_to_mbaa)); + LUT6 #( + .INIT(64'h0000005700000000)) + \sig_realigner_btt2[8]_i_3 + (.I0(\sig_realigner_btt2[15]_i_4_n_0 ), + .I1(sig_btt_lt_b2mbaa2), + .I2(sig_btt_eq_b2mbaa2), + .I3(sig_addr_aligned__6), + .I4(p_10_out), + .I5(sig_first_realigner_cmd), + .O(\sig_realigner_btt2[8]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair220" *) + LUT3 #( + .INIT(8'hD0)) + \sig_realigner_btt2[9]_i_1 + (.I0(sig_first_realigner_cmd), + .I1(sig_skip_align2mbaa), + .I2(sel0[0]), + .O(sig_realigner_btt[9])); + FDRE #( + .INIT(1'b0)) + \sig_realigner_btt2_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_realigner_btt[0]), + .Q(sig_realigner_btt2[0]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_predict_addr_lsh_ireg3_reg[7] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc3_reg), - .D(sig_predict_addr_lsh_im2[7]), - .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[7] ), + \sig_realigner_btt2_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_realigner_btt[10]), + .Q(sig_realigner_btt2[10]), + .R(\sig_realigner_btt2[15]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_realigner_btt2_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_realigner_btt[11]), + .Q(sig_realigner_btt2[11]), + .R(\sig_realigner_btt2[15]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_realigner_btt2_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_realigner_btt[12]), + .Q(sig_realigner_btt2[12]), + .R(\sig_realigner_btt2[15]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_realigner_btt2_reg[13] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_realigner_btt[13]), + .Q(sig_realigner_btt2[13]), + .R(\sig_realigner_btt2[15]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_realigner_btt2_reg[14] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_realigner_btt[14]), + .Q(sig_realigner_btt2[14]), + .R(\sig_realigner_btt2[15]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_realigner_btt2_reg[15] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_realigner_btt[15]), + .Q(sig_realigner_btt2[15]), + .R(\sig_realigner_btt2[15]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_realigner_btt2_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_realigner_btt[1]), + .Q(sig_realigner_btt2[1]), .R(sig_init_reg)); - CARRY4 \sig_predict_addr_lsh_ireg3_reg[7]_i_1 - (.CI(\sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_0 ), - .CO({\sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_0 ,\sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_1 ,\sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_2 ,\sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_3 }), - .CYINIT(1'b0), - .DI({\sig_addr_cntr_lsh_im0_reg_n_0_[7] ,\sig_addr_cntr_lsh_im0_reg_n_0_[6] ,\sig_addr_cntr_lsh_im0_reg_n_0_[5] ,\sig_addr_cntr_lsh_im0_reg_n_0_[4] }), - .O(sig_predict_addr_lsh_im2[7:4]), - .S({\sig_predict_addr_lsh_ireg3[7]_i_2_n_0 ,\sig_predict_addr_lsh_ireg3[7]_i_3_n_0 ,\sig_predict_addr_lsh_ireg3[7]_i_4_n_0 ,\sig_predict_addr_lsh_ireg3[7]_i_5_n_0 })); FDRE #( .INIT(1'b0)) - \sig_predict_addr_lsh_ireg3_reg[8] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc3_reg), - .D(sig_predict_addr_lsh_im2[8]), - .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[8] ), + \sig_realigner_btt2_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_realigner_btt[2]), + .Q(sig_realigner_btt2[2]), .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - \sig_predict_addr_lsh_ireg3_reg[9] - (.C(m_axi_mm2s_aclk), - .CE(sig_sm_ld_calc3_reg), - .D(sig_predict_addr_lsh_im2[9]), - .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[9] ), + \sig_realigner_btt2_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_realigner_btt[3]), + .Q(sig_realigner_btt2[3]), .R(sig_init_reg)); - LUT4 #( - .INIT(16'hA181)) - sig_sm_halt_reg_i_1 - (.I0(sig_pcc_sm_state[2]), - .I1(sig_pcc_sm_state[0]), - .I2(sig_pcc_sm_state[1]), - .I3(sig_calc_error_pushed), - .O(sig_sm_halt_ns)); - FDSE #( + FDRE #( .INIT(1'b0)) - sig_sm_halt_reg_reg - (.C(m_axi_mm2s_aclk), + \sig_realigner_btt2_reg[4] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(sig_sm_halt_ns), - .Q(sig_sm_halt_reg), - .S(sig_init_reg)); - LUT6 #( - .INIT(64'h0008000800083008)) - sig_sm_ld_calc1_reg_i_1 - (.I0(sig_push_input_reg11_out), - .I1(sig_pcc_sm_state[0]), - .I2(sig_pcc_sm_state[2]), - .I3(sig_pcc_sm_state[1]), - .I4(sig_parent_done), - .I5(sig_calc_error_pushed), - .O(sig_sm_ld_calc1_reg_ns)); + .D(sig_realigner_btt[4]), + .Q(sig_realigner_btt2[4]), + .R(sig_init_reg)); FDRE #( .INIT(1'b0)) - sig_sm_ld_calc1_reg_reg - (.C(m_axi_mm2s_aclk), + \sig_realigner_btt2_reg[5] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(sig_sm_ld_calc1_reg_ns), - .Q(sig_sm_ld_calc1_reg), + .D(sig_realigner_btt[5]), + .Q(sig_realigner_btt2[5]), .R(sig_init_reg)); - LUT3 #( - .INIT(8'h02)) - sig_sm_ld_calc2_reg_i_1 - (.I0(sig_pcc_sm_state[1]), - .I1(sig_pcc_sm_state[2]), - .I2(sig_pcc_sm_state[0]), - .O(sig_sm_ld_calc2_reg_ns)); FDRE #( .INIT(1'b0)) - sig_sm_ld_calc2_reg_reg - (.C(m_axi_mm2s_aclk), + \sig_realigner_btt2_reg[6] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(sig_sm_ld_calc2_reg_ns), - .Q(sig_sm_ld_calc2_reg), + .D(sig_realigner_btt[6]), + .Q(sig_realigner_btt2[6]), .R(sig_init_reg)); - LUT3 #( - .INIT(8'h40)) - sig_sm_ld_calc3_reg_i_1 - (.I0(sig_pcc_sm_state[2]), - .I1(sig_pcc_sm_state[0]), - .I2(sig_pcc_sm_state[1]), - .O(sig_sm_ld_calc3_reg_ns)); FDRE #( .INIT(1'b0)) - sig_sm_ld_calc3_reg_reg - (.C(m_axi_mm2s_aclk), + \sig_realigner_btt2_reg[7] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(sig_sm_ld_calc3_reg_ns), - .Q(sig_sm_ld_calc3_reg), + .D(sig_realigner_btt[7]), + .Q(sig_realigner_btt2[7]), .R(sig_init_reg)); - LUT5 #( - .INIT(32'h00200000)) - sig_sm_pop_input_reg_i_1 - (.I0(sig_pcc_sm_state[2]), - .I1(sig_pcc_sm_state[0]), - .I2(sig_parent_done), - .I3(sig_calc_error_pushed), - .I4(sig_pcc_sm_state[1]), - .O(sig_sm_pop_input_reg_ns)); FDRE #( .INIT(1'b0)) - sig_sm_pop_input_reg_reg - (.C(m_axi_mm2s_aclk), + \sig_realigner_btt2_reg[8] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(sig_sm_pop_input_reg_ns), - .Q(sig_sm_pop_input_reg), + .D(sig_realigner_btt[8]), + .Q(sig_realigner_btt2[8]), .R(sig_init_reg)); - LUT4 #( - .INIT(16'hFF2E)) - sig_xfer_reg_empty_i_1 - (.I0(sig_pop_xfer_reg0_out), - .I1(sig_xfer_reg_empty), - .I2(sig_ld_xfer_reg), - .I3(sig_init_reg), - .O(sig_xfer_reg_empty_i_1_n_0)); FDRE #( .INIT(1'b0)) - sig_xfer_reg_empty_reg - (.C(m_axi_mm2s_aclk), + \sig_realigner_btt2_reg[9] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(sig_xfer_reg_empty_i_1_n_0), - .Q(sig_xfer_reg_empty), + .D(sig_realigner_btt[9]), + .Q(sig_realigner_btt2[9]), + .R(\sig_realigner_btt2[15]_i_1_n_0 )); + LUT5 #( + .INIT(32'h0000CC0A)) + sig_skip_align2mbaa_s_h_i_1 + (.I0(sig_skip_align2mbaa_s_h), + .I1(sig_skip_align2mbaa), + .I2(sig_psm_ld_chcmd_reg), + .I3(sig_psm_ld_realigner_reg), + .I4(sig_init_reg), + .O(sig_skip_align2mbaa_s_h_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + sig_skip_align2mbaa_s_h_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_skip_align2mbaa_s_h_i_1_n_0), + .Q(sig_skip_align2mbaa_s_h), .R(1'b0)); + LUT6 #( + .INIT(64'hAAAAAAAAFAFFBABA)) + \sig_xfer_addr_reg[31]_i_1 + (.I0(sig_init_reg), + .I1(p_11_out), + .I2(sig_clr_cmd2addr_valid3_out__0), + .I3(p_22_out), + .I4(sig_clr_cmd2data_valid4_out__0), + .I5(sig_csm_ld_xfer), + .O(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(\sig_xfer_addr_reg_reg[2]_0 [0]), + .Q(in[0]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_child_addr_cntr_lsh_reg[10]), + .Q(in[10]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_child_addr_cntr_lsh_reg[11]), + .Q(in[11]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_child_addr_cntr_lsh_reg[12]), + .Q(in[12]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[13] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_child_addr_cntr_lsh_reg[13]), + .Q(in[13]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[14] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_child_addr_cntr_lsh_reg[14]), + .Q(in[14]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[15] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(p_1_in), + .Q(in[15]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[16] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_child_addr_cntr_msh_reg[0]), + .Q(in[16]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[17] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_child_addr_cntr_msh_reg[1]), + .Q(in[17]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[18] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_child_addr_cntr_msh_reg[2]), + .Q(in[18]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[19] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_child_addr_cntr_msh_reg[3]), + .Q(in[19]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(\sig_xfer_addr_reg_reg[2]_0 [1]), + .Q(in[1]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[20] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_child_addr_cntr_msh_reg[4]), + .Q(in[20]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[21] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_child_addr_cntr_msh_reg[5]), + .Q(in[21]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[22] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_child_addr_cntr_msh_reg[6]), + .Q(in[22]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[23] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_child_addr_cntr_msh_reg[7]), + .Q(in[23]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[24] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_child_addr_cntr_msh_reg[8]), + .Q(in[24]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[25] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_child_addr_cntr_msh_reg[9]), + .Q(in[25]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[26] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_child_addr_cntr_msh_reg[10]), + .Q(in[26]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[27] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_child_addr_cntr_msh_reg[11]), + .Q(in[27]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[28] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_child_addr_cntr_msh_reg[12]), + .Q(in[28]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[29] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_child_addr_cntr_msh_reg[13]), + .Q(in[29]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(\sig_xfer_addr_reg_reg[2]_0 [2]), + .Q(in[2]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[30] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_child_addr_cntr_msh_reg[14]), + .Q(in[30]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[31] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_child_addr_cntr_msh_reg[15]), + .Q(in[31]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_child_addr_cntr_lsh_reg[3]), + .Q(in[3]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_child_addr_cntr_lsh_reg[4]), + .Q(in[4]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_child_addr_cntr_lsh_reg[5]), + .Q(in[5]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_child_addr_cntr_lsh_reg[6]), + .Q(in[6]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_child_addr_cntr_lsh_reg[7]), + .Q(in[7]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_child_addr_cntr_lsh_reg[8]), + .Q(in[8]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_addr_reg_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_child_addr_cntr_lsh_reg[9]), + .Q(in[9]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + sig_xfer_calc_err_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_child_qual_error_reg), + .Q(in[39]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + sig_xfer_cmd_cmplt_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_xfer_cmd_cmplt_reg0), + .Q(sig_next_cmd_cmplt_reg_reg[1]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + sig_xfer_is_seq_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(\gpr1.dout_i_reg[10] ), + .Q(sig_next_cmd_cmplt_reg_reg[0]), + .R(sig_xfer_cache_reg0)); + (* SOFT_HLUTNM = "soft_lutpair216" *) + LUT4 #( + .INIT(16'hFE01)) + \sig_xfer_len_reg[0]_i_1 + (.I0(sig_adjusted_addr_incr[2]), + .I1(sig_adjusted_addr_incr[0]), + .I2(sig_adjusted_addr_incr[1]), + .I3(sig_adjusted_addr_incr[3]), + .O(\sig_xfer_len_reg[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair216" *) + LUT5 #( + .INIT(32'hFFFE0001)) + \sig_xfer_len_reg[1]_i_1 + (.I0(sig_adjusted_addr_incr[3]), + .I1(sig_adjusted_addr_incr[1]), + .I2(sig_adjusted_addr_incr[0]), + .I3(sig_adjusted_addr_incr[2]), + .I4(sig_adjusted_addr_incr[4]), + .O(\sig_xfer_len_reg[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFE00000001)) + \sig_xfer_len_reg[2]_i_1 + (.I0(sig_adjusted_addr_incr[4]), + .I1(sig_adjusted_addr_incr[2]), + .I2(sig_adjusted_addr_incr[0]), + .I3(sig_adjusted_addr_incr[1]), + .I4(sig_adjusted_addr_incr[3]), + .I5(sig_adjusted_addr_incr[5]), + .O(\sig_xfer_len_reg[2]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_xfer_len_reg_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(\sig_xfer_len_reg[0]_i_1_n_0 ), + .Q(in[32]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_len_reg_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(\sig_xfer_len_reg[1]_i_1_n_0 ), + .Q(in[33]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_len_reg_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(\sig_xfer_len_reg[2]_i_1_n_0 ), + .Q(in[34]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_len_reg_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(D[0]), + .Q(in[35]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_len_reg_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(D[1]), + .Q(in[36]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + \sig_xfer_len_reg_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(D[2]), + .Q(in[37]), + .R(sig_xfer_cache_reg0)); + FDRE #( + .INIT(1'b0)) + sig_xfer_type_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(sig_csm_ld_xfer), + .D(sig_child_qual_burst_type), + .Q(in[38]), + .R(sig_xfer_cache_reg0)); endmodule -(* ORIG_REF_NAME = "axi_datamover_rd_sf" *) -module Arty_Z7_20_axi_vdma_0_0_axi_datamover_rd_sf +(* ORIG_REF_NAME = "axi_datamover_indet_btt" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_indet_btt (out, - sig_wr_fifo, - \INFERRED_GEN.cnt_i_reg[1] , - sig_init_done, - sig_inhibit_rdy_n, - sig_sf_allow_addr_req, - \sig_user_skid_reg_reg[0] , - dm2linebuf_mm2s_tvalid, + \GEN_INDET_BTT.lsig_eop_reg_reg , + sig_ibtt2wdc_tlast, + sig_clr_dbc_reg, DI, - Q, - dm2linebuf_mm2s_tdata, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_1 , + D, + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 , + p_0_in, + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 , + sig_xfer_is_seq_reg_reg, + \sig_child_addr_cntr_lsh_reg[11] , + \gcc0.gc0.count_d1_reg[0] , S, - \count_reg[6] , - m_axi_mm2s_aclk, + \sig_xfer_len_reg_reg[4] , + \sig_xfer_len_reg_reg[5] , + \GEN_INDET_BTT.lsig_byte_cntr_reg[15] , + \GEN_INDET_BTT.lsig_byte_cntr_reg[6] , + \GEN_INDET_BTT.lsig_byte_cntr_reg[3] , + \GEN_INDET_BTT.lsig_eop_reg_reg_0 , + sig_xfer_is_seq_reg_reg_0, + sig_xfer_cmd_cmplt_reg0, + sig_sf2pcc_xfer_valid, + sig_ibtt2dre_tready, + sig_csm_state_ns1, + \gpr1.dout_i_reg[1] , + \gpr1.dout_i_reg[1]_0 , + O, + CO, + \sig_child_addr_cntr_lsh_reg[7] , + m_axi_s2mm_aclk, sig_stream_rst, - m_axi_mm2s_rdata, - DIBDI, - in, - sig_mmap_reset_reg_reg, - sig_mstr2sf_cmd_valid, - sig_last_mmap_dbeat_reg_reg, - sig_posted_to_axi_2_reg, - p_8_out, + E, + sig_dre2ibtt_tlast, + sig_dre2ibtt_eop, + \INCLUDE_PACKING.lsig_first_dbeat_reg_0 , + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[0] , + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[0]_0 , sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - fifo_wren__0, - mm2s_strm_wvalid0__1, - m_axi_mm2s_rvalid, - sig_advance_pipe9_out__1, - D); + p_32_out, + sig_adjusted_addr_incr, + \INFERRED_GEN.cnt_i_reg[4] , + Q, + sig_csm_pop_child_cmd, + sig_wdc2ibtt_tready, + lsig_end_of_cmd_reg, + lsig_eop_reg, + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[0]_1 , + sig_child_qual_first_of_2, + sig_child_qual_error_reg, + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] , + sig_init_reg, + \gpr1.dout_i_reg[3] , + \gpr1.dout_i_reg[7] , + sig_child_addr_cntr_lsh_reg, + sig_m_valid_out_reg, + sig_m_valid_out_reg_0, + sig_m_valid_out_reg_1, + sig_m_valid_out_reg_2, + sig_m_valid_out_reg_3, + sig_m_valid_out_reg_4, + sig_m_valid_out_reg_5, + sig_m_valid_out_reg_6, + SR, + p_0_out, + \sig_strb_reg_out_reg[0] , + sig_dre2ibtt_tstrb); output out; - output sig_wr_fifo; - output \INFERRED_GEN.cnt_i_reg[1] ; - output sig_init_done; - output sig_inhibit_rdy_n; - output sig_sf_allow_addr_req; - output [0:0]\sig_user_skid_reg_reg[0] ; - output dm2linebuf_mm2s_tvalid; - output [3:0]DI; - output [1:0]Q; - output [31:0]dm2linebuf_mm2s_tdata; + output \GEN_INDET_BTT.lsig_eop_reg_reg ; + output sig_ibtt2wdc_tlast; + output sig_clr_dbc_reg; + output [10:0]DI; + output \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ; + output [1:0]\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_1 ; + output [2:0]D; + output \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ; + output \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ; + output \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ; + output \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ; + output \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ; + output \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ; + output p_0_in; + output \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ; + output [9:0]sig_xfer_is_seq_reg_reg; + output [0:0]\sig_child_addr_cntr_lsh_reg[11] ; + output [0:0]\gcc0.gc0.count_d1_reg[0] ; output [3:0]S; - output [1:0]\count_reg[6] ; - input m_axi_mm2s_aclk; + output [3:0]\sig_xfer_len_reg_reg[4] ; + output [0:0]\sig_xfer_len_reg_reg[5] ; + output [0:0]\GEN_INDET_BTT.lsig_byte_cntr_reg[15] ; + output [0:0]\GEN_INDET_BTT.lsig_byte_cntr_reg[6] ; + output [64:0]\GEN_INDET_BTT.lsig_byte_cntr_reg[3] ; + output \GEN_INDET_BTT.lsig_eop_reg_reg_0 ; + output sig_xfer_is_seq_reg_reg_0; + output sig_xfer_cmd_cmplt_reg0; + output sig_sf2pcc_xfer_valid; + output sig_ibtt2dre_tready; + output sig_csm_state_ns1; + output [2:0]\gpr1.dout_i_reg[1] ; + output [2:0]\gpr1.dout_i_reg[1]_0 ; + output [3:0]O; + output [0:0]CO; + output [3:0]\sig_child_addr_cntr_lsh_reg[7] ; + input m_axi_s2mm_aclk; input sig_stream_rst; - input [63:0]m_axi_mm2s_rdata; - input [1:0]DIBDI; - input [0:0]in; - input sig_mmap_reset_reg_reg; - input sig_mstr2sf_cmd_valid; - input sig_last_mmap_dbeat_reg_reg; - input sig_posted_to_axi_2_reg; - input p_8_out; + input [0:0]E; + input sig_dre2ibtt_tlast; + input sig_dre2ibtt_eop; + input \INCLUDE_PACKING.lsig_first_dbeat_reg_0 ; + input \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[0] ; + input \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[0]_0 ; input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - input fifo_wren__0; - input mm2s_strm_wvalid0__1; - input m_axi_mm2s_rvalid; - input sig_advance_pipe9_out__1; - input [5:0]D; + input p_32_out; + input [8:0]sig_adjusted_addr_incr; + input [0:0]\INFERRED_GEN.cnt_i_reg[4] ; + input [7:0]Q; + input sig_csm_pop_child_cmd; + input sig_wdc2ibtt_tready; + input lsig_end_of_cmd_reg; + input lsig_eop_reg; + input \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[0]_1 ; + input sig_child_qual_first_of_2; + input sig_child_qual_error_reg; + input [2:0]\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] ; + input sig_init_reg; + input [3:0]\gpr1.dout_i_reg[3] ; + input [3:0]\gpr1.dout_i_reg[7] ; + input [2:0]sig_child_addr_cntr_lsh_reg; + input [1:0]sig_m_valid_out_reg; + input [1:0]sig_m_valid_out_reg_0; + input [1:0]sig_m_valid_out_reg_1; + input [1:0]sig_m_valid_out_reg_2; + input [1:0]sig_m_valid_out_reg_3; + input [1:0]sig_m_valid_out_reg_4; + input [1:0]sig_m_valid_out_reg_5; + input [1:0]sig_m_valid_out_reg_6; + input [1:0]SR; + input [10:0]p_0_out; + input [0:0]\sig_strb_reg_out_reg[0] ; + input sig_dre2ibtt_tstrb; - wire [5:0]D; - wire [3:0]DI; - wire [1:0]DIBDI; - wire \INFERRED_GEN.cnt_i_reg[1] ; - wire I_DATA_FIFO_n_41; - wire I_DATA_FIFO_n_42; - wire I_DATA_FIFO_n_43; - wire I_DATA_FIFO_n_44; - wire [1:0]Q; + wire [0:0]CO; + wire [2:0]D; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_6_n_0 ; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_7_n_0 ; + wire [10:0]DI; + wire [0:0]E; + wire [0:0]\GEN_INDET_BTT.lsig_byte_cntr_reg[15] ; + wire [64:0]\GEN_INDET_BTT.lsig_byte_cntr_reg[3] ; + wire [0:0]\GEN_INDET_BTT.lsig_byte_cntr_reg[6] ; + wire \GEN_INDET_BTT.lsig_eop_reg_reg ; + wire \GEN_INDET_BTT.lsig_eop_reg_reg_0 ; + wire \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[0] ; + wire \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[0]_0 ; + wire \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[0]_1 ; + wire [2:0]\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][0]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][1]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][2]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][3]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][4]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][5]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][6]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][7]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg_n_0_[0][0] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg_n_0_[0][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][0]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][1]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][2]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][3]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][4]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][5]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][6]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][7]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg_n_0_[1][0] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg_n_0_[1][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][0]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][1]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][2]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][3]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][4]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][5]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][6]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][7]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg_n_0_[2][0] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg_n_0_[2][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][0]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][1]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][2]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][3]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][4]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][5]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][6]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][7]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg_n_0_[3][0] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg_n_0_[3][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][0]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][1]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][2]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][3]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][4]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][5]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][6]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][7]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg_n_0_[4][0] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg_n_0_[4][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][0]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][1]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][2]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][3]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][4]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][5]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][6]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][7]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg_n_0_[5][0] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg_n_0_[5][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][0]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][1]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][2]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][3]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][4]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][5]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][6]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][7]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg_n_0_[6][0] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg_n_0_[6][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][0]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][1]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][2]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][3]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][4]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][5]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][6]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][7]_i_1_n_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg_n_0_[7][0] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg_n_0_[7][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr[2]_i_1_n_0 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ; + wire [1:0]\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_1 ; + wire \INCLUDE_PACKING.lsig_first_dbeat_reg_0 ; + wire [0:0]\INFERRED_GEN.cnt_i_reg[4] ; + wire I_DATA_FIFO_n_66; + wire I_DATA_FIFO_n_69; + wire [3:0]O; + wire [7:0]Q; wire [3:0]S; - wire [1:0]\count_reg[6] ; - wire [31:0]dm2linebuf_mm2s_tdata; - wire dm2linebuf_mm2s_tvalid; - wire fifo_wren__0; - wire [0:0]in; - wire lsig_0ffset_cntr; - wire lsig_cmd_loaded; - wire m_axi_mm2s_aclk; - wire [63:0]m_axi_mm2s_rdata; - wire m_axi_mm2s_rvalid; - wire mm2s_strm_wvalid0__1; + wire [1:0]SR; + wire [0:0]\gcc0.gc0.count_d1_reg[0] ; + wire [2:0]\gpr1.dout_i_reg[1] ; + wire [2:0]\gpr1.dout_i_reg[1]_0 ; + wire [3:0]\gpr1.dout_i_reg[3] ; + wire [3:0]\gpr1.dout_i_reg[7] ; + wire hold_ff_q; + wire [2:2]lsig_0ffset_cntr; + wire [2:0]lsig_0ffset_to_to_use__2; + wire [63:0]lsig_combined_data; + wire lsig_end_of_cmd_reg; + wire lsig_eop_reg; + wire \lsig_flag_slice_reg[0]_7 ; + wire \lsig_flag_slice_reg[1]_6 ; + wire \lsig_flag_slice_reg[2]_5 ; + wire \lsig_flag_slice_reg[3]_4 ; + wire \lsig_flag_slice_reg[4]_3 ; + wire \lsig_flag_slice_reg[5]_2 ; + wire \lsig_flag_slice_reg[6]_1 ; + wire \lsig_flag_slice_reg[7]_0 ; + wire lsig_packer_full; + wire lsig_set_packer_full__1; + wire m_axi_s2mm_aclk; wire out; - wire [7:7]p_0_out; - wire p_8_out; - wire sig_advance_pipe9_out__1; + wire p_0_in; + wire [4:0]p_0_in__1; + wire [10:0]p_0_out; + wire p_2_in; + wire p_32_out; + wire p_4_out; + wire [8:0]sig_adjusted_addr_incr; + wire \sig_burst_dbeat_cntr[2]_i_1_n_0 ; + wire \sig_burst_dbeat_cntr[4]_i_1_n_0 ; + wire [4:0]sig_burst_dbeat_cntr_reg__0; + wire \sig_byte_cntr[3]_i_3_n_0 ; + wire \sig_byte_cntr[3]_i_4_n_0 ; + wire \sig_byte_cntr[3]_i_5_n_0 ; + wire \sig_byte_cntr[3]_i_6_n_0 ; + wire \sig_byte_cntr[7]_i_3_n_0 ; + wire \sig_byte_cntr[7]_i_4_n_0 ; + wire \sig_byte_cntr[7]_i_5_n_0 ; + wire \sig_byte_cntr[7]_i_6_n_0 ; + wire \sig_byte_cntr[8]_i_4_n_0 ; + wire \sig_byte_cntr_reg[3]_i_1_n_0 ; + wire \sig_byte_cntr_reg[3]_i_1_n_1 ; + wire \sig_byte_cntr_reg[3]_i_1_n_2 ; + wire \sig_byte_cntr_reg[3]_i_1_n_3 ; + wire \sig_byte_cntr_reg[3]_i_1_n_4 ; + wire \sig_byte_cntr_reg[3]_i_1_n_5 ; + wire \sig_byte_cntr_reg[3]_i_1_n_6 ; + wire \sig_byte_cntr_reg[3]_i_1_n_7 ; + wire \sig_byte_cntr_reg[7]_i_2_n_0 ; + wire \sig_byte_cntr_reg[7]_i_2_n_1 ; + wire \sig_byte_cntr_reg[7]_i_2_n_2 ; + wire \sig_byte_cntr_reg[7]_i_2_n_3 ; + wire \sig_byte_cntr_reg[7]_i_2_n_4 ; + wire \sig_byte_cntr_reg[7]_i_2_n_5 ; + wire \sig_byte_cntr_reg[7]_i_2_n_6 ; + wire \sig_byte_cntr_reg[7]_i_2_n_7 ; + wire \sig_byte_cntr_reg[8]_i_3_n_7 ; + wire [2:0]sig_child_addr_cntr_lsh_reg; + wire [0:0]\sig_child_addr_cntr_lsh_reg[11] ; + wire [3:0]\sig_child_addr_cntr_lsh_reg[7] ; + wire sig_child_qual_error_reg; + wire sig_child_qual_first_of_2; + wire sig_clr_dbc_reg; + wire sig_clr_dbeat_cntr0_out; wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - wire sig_inhibit_rdy_n; - wire sig_init_done; - wire sig_last_mmap_dbeat_reg_reg; - wire sig_mmap_reset_reg_reg; - wire sig_mstr2sf_cmd_valid; - wire sig_ok_to_post_rd_addr_i_3_n_0; - wire sig_posted_to_axi_2_reg; - wire sig_rd_empty; - wire sig_sf_allow_addr_req; + wire sig_csm_pop_child_cmd; + wire sig_csm_state_ns1; + wire [65:64]sig_data_fifo_data_in__0; + wire [65:0]sig_data_fifo_data_out; + wire sig_data_fifo_dvalid; + wire sig_dbc_max__3; + wire sig_dre2ibtt_eop; + wire sig_dre2ibtt_tlast; + wire sig_dre2ibtt_tstrb; + wire sig_ibtt2dre_tready; + wire sig_ibtt2wdc_tlast; + wire sig_incr_dbeat_cntr; + wire sig_init_reg; + wire [1:0]sig_m_valid_out_reg; + wire [1:0]sig_m_valid_out_reg_0; + wire [1:0]sig_m_valid_out_reg_1; + wire [1:0]sig_m_valid_out_reg_2; + wire [1:0]sig_m_valid_out_reg_3; + wire [1:0]sig_m_valid_out_reg_4; + wire [1:0]sig_m_valid_out_reg_5; + wire [1:0]sig_m_valid_out_reg_6; + wire sig_sf2pcc_xfer_valid; + wire [0:0]\sig_strb_reg_out_reg[0] ; wire sig_stream_rst; - wire \sig_token_cntr[0]_i_1_n_0 ; - wire \sig_token_cntr[1]_i_1_n_0 ; - wire \sig_token_cntr[2]_i_1_n_0 ; - wire \sig_token_cntr[3]_i_1_n_0 ; - wire \sig_token_cntr[3]_i_2_n_0 ; - wire [3:0]sig_token_cntr_reg__0; - wire [0:0]\sig_user_skid_reg_reg[0] ; - wire sig_wr_fifo; + wire sig_wdc2ibtt_tready; + wire sig_xfer_cmd_cmplt_reg0; + wire [9:0]sig_xfer_is_seq_reg_reg; + wire sig_xfer_is_seq_reg_reg_0; + wire [3:0]\sig_xfer_len_reg_reg[4] ; + wire [0:0]\sig_xfer_len_reg_reg[5] ; + wire [3:0]\NLW_sig_byte_cntr_reg[8]_i_3_CO_UNCONNECTED ; + wire [3:1]\NLW_sig_byte_cntr_reg[8]_i_3_O_UNCONNECTED ; + LUT5 #( + .INIT(32'hFFFFFFFE)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_4 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg_n_0_[3][0] ), + .I1(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg_n_0_[4][0] ), + .I2(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg_n_0_[2][0] ), + .I3(\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg_n_0_[1][0] ), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_6_n_0 ), + .O(sig_data_fifo_data_in__0[65])); + LUT5 #( + .INIT(32'hFFFFFFFE)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_5 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg_n_0_[3][1] ), + .I1(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg_n_0_[4][1] ), + .I2(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg_n_0_[2][1] ), + .I3(\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg_n_0_[1][1] ), + .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_7_n_0 ), + .O(sig_data_fifo_data_in__0[64])); + LUT4 #( + .INIT(16'hFFFE)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_6 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg_n_0_[6][0] ), + .I1(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg_n_0_[5][0] ), + .I2(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg_n_0_[0][0] ), + .I3(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg_n_0_[7][0] ), + .O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_6_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_7 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg_n_0_[6][1] ), + .I1(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg_n_0_[5][1] ), + .I2(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg_n_0_[0][1] ), + .I3(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg_n_0_[7][1] ), + .O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_7_n_0 )); + Arty_Z7_20_axi_vdma_0_0_axi_datamover_skid_buf \ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF + (.E(E), + .\GEN_INDET_BTT.lsig_byte_cntr_reg[15] (\GEN_INDET_BTT.lsig_byte_cntr_reg[15] ), + .\GEN_INDET_BTT.lsig_byte_cntr_reg[3] (\GEN_INDET_BTT.lsig_byte_cntr_reg[3] ), + .\GEN_INDET_BTT.lsig_byte_cntr_reg[6] (\GEN_INDET_BTT.lsig_byte_cntr_reg[6] ), + .\GEN_INDET_BTT.lsig_eop_reg_reg (\GEN_INDET_BTT.lsig_eop_reg_reg ), + .\GEN_INDET_BTT.lsig_eop_reg_reg_0 (\GEN_INDET_BTT.lsig_eop_reg_reg_0 ), + .\gpregsm1.user_valid_reg (p_4_out), + .\gpregsm1.user_valid_reg_0 (I_DATA_FIFO_n_66), + .hold_ff_q(hold_ff_q), + .lsig_end_of_cmd_reg(lsig_end_of_cmd_reg), + .lsig_eop_reg(lsig_eop_reg), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_data_fifo_data_out(sig_data_fifo_data_out), + .sig_data_fifo_dvalid(sig_data_fifo_dvalid), + .sig_ibtt2wdc_tlast(sig_ibtt2wdc_tlast), + .sig_init_reg(sig_init_reg), + .sig_stream_rst(sig_stream_rst), + .sig_wdc2ibtt_tready(sig_wdc2ibtt_tready)); + (* SOFT_HLUTNM = "soft_lutpair214" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][0]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ), + .I1(Q[0]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair211" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][1]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ), + .I1(Q[1]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair211" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][2]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ), + .I1(Q[2]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair212" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][3]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ), + .I1(Q[3]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair212" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][4]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ), + .I1(Q[4]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair213" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][5]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ), + .I1(Q[5]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair213" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][6]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ), + .I1(Q[6]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair214" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][7]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ), + .I1(Q[7]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][7]_i_1_n_0 )); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[0]_7 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][0]_i_1_n_0 ), + .Q(lsig_combined_data[0]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][1] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[0]_7 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][1]_i_1_n_0 ), + .Q(lsig_combined_data[1]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][2] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[0]_7 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][2]_i_1_n_0 ), + .Q(lsig_combined_data[2]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][3] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[0]_7 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][3]_i_1_n_0 ), + .Q(lsig_combined_data[3]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][4] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[0]_7 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][4]_i_1_n_0 ), + .Q(lsig_combined_data[4]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][5] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[0]_7 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][5]_i_1_n_0 ), + .Q(lsig_combined_data[5]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][6] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[0]_7 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][6]_i_1_n_0 ), + .Q(lsig_combined_data[6]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][7] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[0]_7 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][7]_i_1_n_0 ), + .Q(lsig_combined_data[7]), + .R(sig_stream_rst)); + LUT6 #( + .INIT(64'h0000015100000000)) + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg[0][1]_i_3 + (.I0(lsig_0ffset_to_to_use__2[0]), + .I1(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_1 [1]), + .I2(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ), + .I3(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [1]), + .I4(lsig_0ffset_to_to_use__2[2]), + .I5(\INFERRED_GEN.cnt_i_reg[4] ), + .O(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 )); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][0] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[0]_7 ), + .D(sig_m_valid_out_reg_6[0]), + .Q(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg_n_0_[0][0] ), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[0]_7 ), + .D(sig_m_valid_out_reg_6[1]), + .Q(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg_n_0_[0][1] ), + .R(sig_stream_rst)); + (* SOFT_HLUTNM = "soft_lutpair210" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][0]_i_1 + (.I0(p_0_in), + .I1(Q[0]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair207" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][1]_i_1 + (.I0(p_0_in), + .I1(Q[1]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair207" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][2]_i_1 + (.I0(p_0_in), + .I1(Q[2]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair208" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][3]_i_1 + (.I0(p_0_in), + .I1(Q[3]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair208" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][4]_i_1 + (.I0(p_0_in), + .I1(Q[4]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair209" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][5]_i_1 + (.I0(p_0_in), + .I1(Q[5]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair209" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][6]_i_1 + (.I0(p_0_in), + .I1(Q[6]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair210" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][7]_i_1 + (.I0(p_0_in), + .I1(Q[7]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][7]_i_1_n_0 )); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[1]_6 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][0]_i_1_n_0 ), + .Q(lsig_combined_data[8]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][1] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[1]_6 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][1]_i_1_n_0 ), + .Q(lsig_combined_data[9]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][2] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[1]_6 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][2]_i_1_n_0 ), + .Q(lsig_combined_data[10]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][3] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[1]_6 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][3]_i_1_n_0 ), + .Q(lsig_combined_data[11]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][4] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[1]_6 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][4]_i_1_n_0 ), + .Q(lsig_combined_data[12]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][5] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[1]_6 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][5]_i_1_n_0 ), + .Q(lsig_combined_data[13]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][6] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[1]_6 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][6]_i_1_n_0 ), + .Q(lsig_combined_data[14]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][7] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[1]_6 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][7]_i_1_n_0 ), + .Q(lsig_combined_data[15]), + .R(sig_stream_rst)); + LUT6 #( + .INIT(64'h001D000000000000)) + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg[1][1]_i_3 + (.I0(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_1 [1]), + .I1(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ), + .I2(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [1]), + .I3(lsig_0ffset_to_to_use__2[2]), + .I4(lsig_0ffset_to_to_use__2[0]), + .I5(\INFERRED_GEN.cnt_i_reg[4] ), + .O(p_0_in)); + LUT3 #( + .INIT(8'hB8)) + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg[1][1]_i_4 + (.I0(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [2]), + .I1(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ), + .I2(lsig_0ffset_cntr), + .O(lsig_0ffset_to_to_use__2[2])); + (* SOFT_HLUTNM = "soft_lutpair182" *) + LUT3 #( + .INIT(8'hB8)) + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg[1][1]_i_5 + (.I0(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [0]), + .I1(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ), + .I2(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_1 [0]), + .O(lsig_0ffset_to_to_use__2[0])); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][0] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[1]_6 ), + .D(sig_m_valid_out_reg[0]), + .Q(\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg_n_0_[1][0] ), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[1]_6 ), + .D(sig_m_valid_out_reg[1]), + .Q(\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg_n_0_[1][1] ), + .R(sig_stream_rst)); + (* SOFT_HLUTNM = "soft_lutpair206" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][0]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ), + .I1(Q[0]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair203" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][1]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ), + .I1(Q[1]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair203" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][2]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ), + .I1(Q[2]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair204" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][3]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ), + .I1(Q[3]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair204" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][4]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ), + .I1(Q[4]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair205" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][5]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ), + .I1(Q[5]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair205" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][6]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ), + .I1(Q[6]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair206" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][7]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ), + .I1(Q[7]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][7]_i_1_n_0 )); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[2]_5 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][0]_i_1_n_0 ), + .Q(lsig_combined_data[16]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][1] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[2]_5 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][1]_i_1_n_0 ), + .Q(lsig_combined_data[17]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][2] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[2]_5 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][2]_i_1_n_0 ), + .Q(lsig_combined_data[18]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][3] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[2]_5 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][3]_i_1_n_0 ), + .Q(lsig_combined_data[19]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][4] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[2]_5 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][4]_i_1_n_0 ), + .Q(lsig_combined_data[20]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][5] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[2]_5 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][5]_i_1_n_0 ), + .Q(lsig_combined_data[21]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][6] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[2]_5 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][6]_i_1_n_0 ), + .Q(lsig_combined_data[22]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][7] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[2]_5 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][7]_i_1_n_0 ), + .Q(lsig_combined_data[23]), + .R(sig_stream_rst)); + LUT6 #( + .INIT(64'h0000540400000000)) + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg[2][1]_i_3 + (.I0(lsig_0ffset_to_to_use__2[0]), + .I1(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_1 [1]), + .I2(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ), + .I3(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [1]), + .I4(lsig_0ffset_to_to_use__2[2]), + .I5(\INFERRED_GEN.cnt_i_reg[4] ), + .O(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 )); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][0] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[2]_5 ), + .D(sig_m_valid_out_reg_0[0]), + .Q(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg_n_0_[2][0] ), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[2]_5 ), + .D(sig_m_valid_out_reg_0[1]), + .Q(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg_n_0_[2][1] ), + .R(sig_stream_rst)); + (* SOFT_HLUTNM = "soft_lutpair202" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][0]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ), + .I1(Q[0]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair198" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][1]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ), + .I1(Q[1]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair198" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][2]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ), + .I1(Q[2]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair199" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][3]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ), + .I1(Q[3]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair199" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][4]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ), + .I1(Q[4]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair201" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][5]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ), + .I1(Q[5]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair201" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][6]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ), + .I1(Q[6]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair202" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][7]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ), + .I1(Q[7]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][7]_i_1_n_0 )); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[3]_4 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][0]_i_1_n_0 ), + .Q(lsig_combined_data[24]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][1] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[3]_4 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][1]_i_1_n_0 ), + .Q(lsig_combined_data[25]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][2] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[3]_4 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][2]_i_1_n_0 ), + .Q(lsig_combined_data[26]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][3] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[3]_4 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][3]_i_1_n_0 ), + .Q(lsig_combined_data[27]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][4] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[3]_4 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][4]_i_1_n_0 ), + .Q(lsig_combined_data[28]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][5] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[3]_4 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][5]_i_1_n_0 ), + .Q(lsig_combined_data[29]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][6] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[3]_4 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][6]_i_1_n_0 ), + .Q(lsig_combined_data[30]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][7] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[3]_4 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][7]_i_1_n_0 ), + .Q(lsig_combined_data[31]), + .R(sig_stream_rst)); + LUT6 #( + .INIT(64'h00E2000000000000)) + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg[3][1]_i_3 + (.I0(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_1 [1]), + .I1(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ), + .I2(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [1]), + .I3(lsig_0ffset_to_to_use__2[2]), + .I4(lsig_0ffset_to_to_use__2[0]), + .I5(\INFERRED_GEN.cnt_i_reg[4] ), + .O(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 )); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][0] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[3]_4 ), + .D(sig_m_valid_out_reg_1[0]), + .Q(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg_n_0_[3][0] ), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[3]_4 ), + .D(sig_m_valid_out_reg_1[1]), + .Q(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg_n_0_[3][1] ), + .R(sig_stream_rst)); + (* SOFT_HLUTNM = "soft_lutpair197" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][0]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ), + .I1(Q[0]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair194" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][1]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ), + .I1(Q[1]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair194" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][2]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ), + .I1(Q[2]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair195" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][3]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ), + .I1(Q[3]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair195" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][4]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ), + .I1(Q[4]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair196" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][5]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ), + .I1(Q[5]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair196" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][6]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ), + .I1(Q[6]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair197" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][7]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ), + .I1(Q[7]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][7]_i_1_n_0 )); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[4]_3 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][0]_i_1_n_0 ), + .Q(lsig_combined_data[32]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][1] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[4]_3 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][1]_i_1_n_0 ), + .Q(lsig_combined_data[33]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][2] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[4]_3 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][2]_i_1_n_0 ), + .Q(lsig_combined_data[34]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][3] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[4]_3 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][3]_i_1_n_0 ), + .Q(lsig_combined_data[35]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][4] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[4]_3 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][4]_i_1_n_0 ), + .Q(lsig_combined_data[36]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][5] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[4]_3 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][5]_i_1_n_0 ), + .Q(lsig_combined_data[37]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][6] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[4]_3 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][6]_i_1_n_0 ), + .Q(lsig_combined_data[38]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][7] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[4]_3 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][7]_i_1_n_0 ), + .Q(lsig_combined_data[39]), + .R(sig_stream_rst)); + LUT6 #( + .INIT(64'h0000540400000000)) + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg[4][1]_i_3 + (.I0(lsig_0ffset_to_to_use__2[0]), + .I1(lsig_0ffset_cntr), + .I2(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ), + .I3(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [2]), + .I4(lsig_0ffset_to_to_use__2[1]), + .I5(\INFERRED_GEN.cnt_i_reg[4] ), + .O(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 )); + (* SOFT_HLUTNM = "soft_lutpair182" *) + LUT3 #( + .INIT(8'hB8)) + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg[4][1]_i_4 + (.I0(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [1]), + .I1(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ), + .I2(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_1 [1]), + .O(lsig_0ffset_to_to_use__2[1])); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][0] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[4]_3 ), + .D(sig_m_valid_out_reg_2[0]), + .Q(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg_n_0_[4][0] ), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[4]_3 ), + .D(sig_m_valid_out_reg_2[1]), + .Q(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg_n_0_[4][1] ), + .R(sig_stream_rst)); + (* SOFT_HLUTNM = "soft_lutpair193" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][0]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ), + .I1(Q[0]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair190" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][1]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ), + .I1(Q[1]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair190" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][2]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ), + .I1(Q[2]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair191" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][3]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ), + .I1(Q[3]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair191" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][4]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ), + .I1(Q[4]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair192" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][5]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ), + .I1(Q[5]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair192" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][6]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ), + .I1(Q[6]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair193" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][7]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ), + .I1(Q[7]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][7]_i_1_n_0 )); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[5]_2 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][0]_i_1_n_0 ), + .Q(lsig_combined_data[40]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][1] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[5]_2 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][1]_i_1_n_0 ), + .Q(lsig_combined_data[41]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][2] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[5]_2 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][2]_i_1_n_0 ), + .Q(lsig_combined_data[42]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][3] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[5]_2 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][3]_i_1_n_0 ), + .Q(lsig_combined_data[43]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][4] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[5]_2 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][4]_i_1_n_0 ), + .Q(lsig_combined_data[44]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][5] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[5]_2 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][5]_i_1_n_0 ), + .Q(lsig_combined_data[45]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][6] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[5]_2 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][6]_i_1_n_0 ), + .Q(lsig_combined_data[46]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][7] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[5]_2 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][7]_i_1_n_0 ), + .Q(lsig_combined_data[47]), + .R(sig_stream_rst)); + LUT6 #( + .INIT(64'h00E2000000000000)) + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg[5][1]_i_3 + (.I0(lsig_0ffset_cntr), + .I1(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ), + .I2(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [2]), + .I3(lsig_0ffset_to_to_use__2[1]), + .I4(lsig_0ffset_to_to_use__2[0]), + .I5(\INFERRED_GEN.cnt_i_reg[4] ), + .O(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 )); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][0] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[5]_2 ), + .D(sig_m_valid_out_reg_3[0]), + .Q(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg_n_0_[5][0] ), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[5]_2 ), + .D(sig_m_valid_out_reg_3[1]), + .Q(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg_n_0_[5][1] ), + .R(sig_stream_rst)); + (* SOFT_HLUTNM = "soft_lutpair189" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][0]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ), + .I1(Q[0]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair185" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][1]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ), + .I1(Q[1]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair185" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][2]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ), + .I1(Q[2]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair186" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][3]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ), + .I1(Q[3]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair186" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][4]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ), + .I1(Q[4]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair188" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][5]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ), + .I1(Q[5]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair189" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][6]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ), + .I1(Q[6]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair188" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][7]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ), + .I1(Q[7]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][7]_i_1_n_0 )); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[6]_1 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][0]_i_1_n_0 ), + .Q(lsig_combined_data[48]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][1] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[6]_1 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][1]_i_1_n_0 ), + .Q(lsig_combined_data[49]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][2] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[6]_1 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][2]_i_1_n_0 ), + .Q(lsig_combined_data[50]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][3] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[6]_1 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][3]_i_1_n_0 ), + .Q(lsig_combined_data[51]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][4] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[6]_1 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][4]_i_1_n_0 ), + .Q(lsig_combined_data[52]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][5] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[6]_1 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][5]_i_1_n_0 ), + .Q(lsig_combined_data[53]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][6] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[6]_1 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][6]_i_1_n_0 ), + .Q(lsig_combined_data[54]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][7] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[6]_1 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][7]_i_1_n_0 ), + .Q(lsig_combined_data[55]), + .R(sig_stream_rst)); + LUT6 #( + .INIT(64'h5404000000000000)) + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg[6][1]_i_3 + (.I0(lsig_0ffset_to_to_use__2[0]), + .I1(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_1 [1]), + .I2(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ), + .I3(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [1]), + .I4(lsig_0ffset_to_to_use__2[2]), + .I5(\INFERRED_GEN.cnt_i_reg[4] ), + .O(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 )); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][0] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[6]_1 ), + .D(sig_m_valid_out_reg_4[0]), + .Q(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg_n_0_[6][0] ), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[6]_1 ), + .D(sig_m_valid_out_reg_4[1]), + .Q(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg_n_0_[6][1] ), + .R(sig_stream_rst)); + (* SOFT_HLUTNM = "soft_lutpair184" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][0]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ), + .I1(Q[0]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair183" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][1]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ), + .I1(Q[1]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair184" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][2]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ), + .I1(Q[2]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair187" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][3]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ), + .I1(Q[3]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair200" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][4]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ), + .I1(Q[4]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair200" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][5]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ), + .I1(Q[5]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair187" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][6]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ), + .I1(Q[6]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair183" *) + LUT2 #( + .INIT(4'h8)) + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][7]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ), + .I1(Q[7]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][7]_i_1_n_0 )); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][0] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[7]_0 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][0]_i_1_n_0 ), + .Q(lsig_combined_data[56]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][1] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[7]_0 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][1]_i_1_n_0 ), + .Q(lsig_combined_data[57]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][2] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[7]_0 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][2]_i_1_n_0 ), + .Q(lsig_combined_data[58]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][3] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[7]_0 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][3]_i_1_n_0 ), + .Q(lsig_combined_data[59]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][4] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[7]_0 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][4]_i_1_n_0 ), + .Q(lsig_combined_data[60]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][5] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[7]_0 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][5]_i_1_n_0 ), + .Q(lsig_combined_data[61]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][6] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[7]_0 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][6]_i_1_n_0 ), + .Q(lsig_combined_data[62]), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[7]_0 ), + .D(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][7]_i_1_n_0 ), + .Q(lsig_combined_data[63]), + .R(sig_stream_rst)); + LUT6 #( + .INIT(64'hA808000000000000)) + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg[7][1]_i_3 + (.I0(\INFERRED_GEN.cnt_i_reg[4] ), + .I1(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_1 [1]), + .I2(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ), + .I3(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] [1]), + .I4(lsig_0ffset_to_to_use__2[2]), + .I5(lsig_0ffset_to_to_use__2[0]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 )); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][0] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[7]_0 ), + .D(sig_m_valid_out_reg_5[0]), + .Q(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg_n_0_[7][0] ), + .R(sig_stream_rst)); + FDRE \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] + (.C(m_axi_s2mm_aclk), + .CE(\lsig_flag_slice_reg[7]_0 ), + .D(sig_m_valid_out_reg_5[1]), + .Q(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg_n_0_[7][1] ), + .R(sig_stream_rst)); + LUT6 #( + .INIT(64'hAA3FFFFFAAC00000)) + \INCLUDE_PACKING.lsig_0ffset_cntr[2]_i_1 + (.I0(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[0]_1 ), + .I1(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_1 [0]), + .I2(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_1 [1]), + .I3(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ), + .I4(\INFERRED_GEN.cnt_i_reg[4] ), + .I5(lsig_0ffset_cntr), + .O(\INCLUDE_PACKING.lsig_0ffset_cntr[2]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[0]_0 ), + .Q(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_1 [0]), + .R(sig_stream_rst)); FDRE #( .INIT(1'b0)) - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] - (.C(m_axi_mm2s_aclk), + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(I_DATA_FIFO_n_42), + .D(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[0] ), + .Q(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_1 [1]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\INCLUDE_PACKING.lsig_0ffset_cntr[2]_i_1_n_0 ), .Q(lsig_0ffset_cntr), .R(sig_stream_rst)); + FDSE #( + .INIT(1'b0)) + \INCLUDE_PACKING.lsig_first_dbeat_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\INCLUDE_PACKING.lsig_first_dbeat_reg_0 ), + .Q(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ), + .S(sig_stream_rst)); FDRE #( .INIT(1'b0)) - \INCLUDE_UNPACKING.lsig_cmd_loaded_reg - (.C(m_axi_mm2s_aclk), + \INCLUDE_PACKING.lsig_packer_full_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(I_DATA_FIFO_n_43), - .Q(lsig_cmd_loaded), + .D(I_DATA_FIFO_n_69), + .Q(lsig_packer_full), .R(sig_stream_rst)); - Arty_Z7_20_axi_vdma_0_0_axi_datamover_sfifo_autord I_DATA_FIFO - (.D(D), - .DI(DI), - .DIBDI(DIBDI), - .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] (I_DATA_FIFO_n_42), - .\INCLUDE_UNPACKING.lsig_cmd_loaded_reg (I_DATA_FIFO_n_43), - .\INFERRED_GEN.cnt_i_reg[0] (I_DATA_FIFO_n_44), - .\INFERRED_GEN.cnt_i_reg[2] (sig_rd_empty), - .Q(Q), + Arty_Z7_20_axi_vdma_0_0_axi_datamover_sfifo_autord__parameterized1 I_DATA_FIFO + (.DIBDI(sig_data_fifo_data_in__0), + .E(\lsig_flag_slice_reg[7]_0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] (\lsig_flag_slice_reg[0]_7 ), + .\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] (\lsig_flag_slice_reg[1]_6 ), + .\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] (\lsig_flag_slice_reg[2]_5 ), + .\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] (\lsig_flag_slice_reg[3]_4 ), + .\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] (\lsig_flag_slice_reg[4]_3 ), + .\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] (\lsig_flag_slice_reg[5]_2 ), + .\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] (\lsig_flag_slice_reg[6]_1 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] (\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 (\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 (\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 (\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 (p_0_in), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 (\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] (\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 (\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.lsig_packer_full_reg (I_DATA_FIFO_n_69), + .\gcc0.gc0.count_d1_reg[7] (p_2_in), + .hold_ff_q(hold_ff_q), + .lsig_combined_data(lsig_combined_data), + .lsig_packer_full(lsig_packer_full), + .lsig_set_packer_full__1(lsig_set_packer_full__1), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(I_DATA_FIFO_n_66), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_data_fifo_data_out(sig_data_fifo_data_out), + .sig_data_fifo_dvalid(sig_data_fifo_dvalid), + .sig_s_ready_out_reg(p_4_out), + .sig_stream_rst(sig_stream_rst)); + Arty_Z7_20_axi_vdma_0_0_axi_datamover_sfifo_autord__parameterized0 I_XD_FIFO + (.CO(CO), + .D(D), + .E(\gcc0.gc0.count_d1_reg[0] ), + .O(O), .S(S), - .\count_reg[6] (\count_reg[6] ), - .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), - .dm2linebuf_mm2s_tvalid(dm2linebuf_mm2s_tvalid), - .fifo_wren__0(fifo_wren__0), - .lsig_0ffset_cntr(lsig_0ffset_cntr), - .lsig_cmd_loaded(lsig_cmd_loaded), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axi_mm2s_rdata(m_axi_mm2s_rdata), - .m_axi_mm2s_rvalid(m_axi_mm2s_rvalid), - .mm2s_strm_wvalid0__1(mm2s_strm_wvalid0__1), - .out(out), + .\gpr1.dout_i_reg[1] (\gpr1.dout_i_reg[1] ), + .\gpr1.dout_i_reg[1]_0 (\gpr1.dout_i_reg[1]_0 ), + .\gpr1.dout_i_reg[3] (\gpr1.dout_i_reg[3] ), + .\gpr1.dout_i_reg[7] (\gpr1.dout_i_reg[7] ), + .lsig_packer_full(lsig_packer_full), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), .p_0_out(p_0_out), - .p_8_out(p_8_out), - .sig_advance_pipe9_out__1(sig_advance_pipe9_out__1), + .p_32_out(p_32_out), + .ram_full_i_reg(p_2_in), + .sig_adjusted_addr_incr(sig_adjusted_addr_incr), + .sig_child_addr_cntr_lsh_reg(sig_child_addr_cntr_lsh_reg), + .\sig_child_addr_cntr_lsh_reg[11] (\sig_child_addr_cntr_lsh_reg[11] ), + .\sig_child_addr_cntr_lsh_reg[7] (\sig_child_addr_cntr_lsh_reg[7] ), + .sig_child_qual_error_reg(sig_child_qual_error_reg), + .sig_child_qual_first_of_2(sig_child_qual_first_of_2), + .sig_clr_dbc_reg_reg(sig_clr_dbc_reg), .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .sig_ok_to_post_rd_addr_reg(I_DATA_FIFO_n_41), - .sig_posted_to_axi_2_reg(sig_ok_to_post_rd_addr_i_3_n_0), - .sig_posted_to_axi_2_reg_0(sig_posted_to_axi_2_reg), + .sig_csm_pop_child_cmd(sig_csm_pop_child_cmd), + .sig_csm_state_ns1(sig_csm_state_ns1), + .sig_ibtt2dre_tready(sig_ibtt2dre_tready), + .sig_sf2pcc_xfer_valid(sig_sf2pcc_xfer_valid), .sig_stream_rst(sig_stream_rst), - .\sig_token_cntr_reg[3] (sig_token_cntr_reg__0), - .\sig_user_skid_reg_reg[0] (\sig_user_skid_reg_reg[0] )); - Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized3 \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO - (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (I_DATA_FIFO_n_44), - .FIFO_Full_reg(sig_wr_fifo), - .\INFERRED_GEN.cnt_i_reg[1] (\INFERRED_GEN.cnt_i_reg[1] ), - .\INFERRED_GEN.cnt_i_reg[1]_0 (sig_inhibit_rdy_n), - .Q(sig_rd_empty), - .in(in), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .p_0_out(p_0_out), - .sig_init_done(sig_init_done), - .sig_mmap_reset_reg_reg(sig_mmap_reset_reg_reg), - .sig_mstr2sf_cmd_valid(sig_mstr2sf_cmd_valid), - .sig_stream_rst(sig_stream_rst)); - (* SOFT_HLUTNM = "soft_lutpair70" *) + .sig_xfer_cmd_cmplt_reg0(sig_xfer_cmd_cmplt_reg0), + .sig_xfer_is_seq_reg_reg(sig_xfer_is_seq_reg_reg), + .sig_xfer_is_seq_reg_reg_0(sig_xfer_is_seq_reg_reg_0), + .\sig_xfer_len_reg_reg[4] (\sig_xfer_len_reg_reg[4] ), + .\sig_xfer_len_reg_reg[5] (\sig_xfer_len_reg_reg[5] )); + (* SOFT_HLUTNM = "soft_lutpair215" *) + LUT1 #( + .INIT(2'h1)) + \sig_burst_dbeat_cntr[0]_i_1 + (.I0(sig_burst_dbeat_cntr_reg__0[0]), + .O(p_0_in__1[0])); + (* SOFT_HLUTNM = "soft_lutpair215" *) + LUT2 #( + .INIT(4'h6)) + \sig_burst_dbeat_cntr[1]_i_1 + (.I0(sig_burst_dbeat_cntr_reg__0[0]), + .I1(sig_burst_dbeat_cntr_reg__0[1]), + .O(p_0_in__1[1])); + (* SOFT_HLUTNM = "soft_lutpair181" *) + LUT3 #( + .INIT(8'h78)) + \sig_burst_dbeat_cntr[2]_i_1 + (.I0(sig_burst_dbeat_cntr_reg__0[0]), + .I1(sig_burst_dbeat_cntr_reg__0[1]), + .I2(sig_burst_dbeat_cntr_reg__0[2]), + .O(\sig_burst_dbeat_cntr[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair181" *) + LUT4 #( + .INIT(16'h7F80)) + \sig_burst_dbeat_cntr[3]_i_1 + (.I0(sig_burst_dbeat_cntr_reg__0[1]), + .I1(sig_burst_dbeat_cntr_reg__0[0]), + .I2(sig_burst_dbeat_cntr_reg__0[2]), + .I3(sig_burst_dbeat_cntr_reg__0[3]), + .O(p_0_in__1[3])); LUT5 #( - .INIT(32'h00000203)) - sig_ok_to_post_rd_addr_i_3 - (.I0(sig_posted_to_axi_2_reg), - .I1(sig_token_cntr_reg__0[3]), - .I2(sig_token_cntr_reg__0[2]), - .I3(sig_token_cntr_reg__0[0]), - .I4(sig_token_cntr_reg__0[1]), - .O(sig_ok_to_post_rd_addr_i_3_n_0)); + .INIT(32'hE000FFFF)) + \sig_burst_dbeat_cntr[4]_i_1 + (.I0(sig_dbc_max__3), + .I1(sig_dre2ibtt_tlast), + .I2(\INFERRED_GEN.cnt_i_reg[4] ), + .I3(lsig_set_packer_full__1), + .I4(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .O(\sig_burst_dbeat_cntr[4]_i_1_n_0 )); + LUT2 #( + .INIT(4'h8)) + \sig_burst_dbeat_cntr[4]_i_2 + (.I0(lsig_set_packer_full__1), + .I1(\INFERRED_GEN.cnt_i_reg[4] ), + .O(sig_incr_dbeat_cntr)); + (* SOFT_HLUTNM = "soft_lutpair180" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \sig_burst_dbeat_cntr[4]_i_3 + (.I0(sig_burst_dbeat_cntr_reg__0[2]), + .I1(sig_burst_dbeat_cntr_reg__0[0]), + .I2(sig_burst_dbeat_cntr_reg__0[1]), + .I3(sig_burst_dbeat_cntr_reg__0[3]), + .I4(sig_burst_dbeat_cntr_reg__0[4]), + .O(p_0_in__1[4])); + FDRE #( + .INIT(1'b0)) + \sig_burst_dbeat_cntr_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(sig_incr_dbeat_cntr), + .D(p_0_in__1[0]), + .Q(sig_burst_dbeat_cntr_reg__0[0]), + .R(\sig_burst_dbeat_cntr[4]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_burst_dbeat_cntr_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(sig_incr_dbeat_cntr), + .D(p_0_in__1[1]), + .Q(sig_burst_dbeat_cntr_reg__0[1]), + .R(\sig_burst_dbeat_cntr[4]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_burst_dbeat_cntr_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(sig_incr_dbeat_cntr), + .D(\sig_burst_dbeat_cntr[2]_i_1_n_0 ), + .Q(sig_burst_dbeat_cntr_reg__0[2]), + .R(\sig_burst_dbeat_cntr[4]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_burst_dbeat_cntr_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(sig_incr_dbeat_cntr), + .D(p_0_in__1[3]), + .Q(sig_burst_dbeat_cntr_reg__0[3]), + .R(\sig_burst_dbeat_cntr[4]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_burst_dbeat_cntr_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(sig_incr_dbeat_cntr), + .D(p_0_in__1[4]), + .Q(sig_burst_dbeat_cntr_reg__0[4]), + .R(\sig_burst_dbeat_cntr[4]_i_1_n_0 )); + LUT3 #( + .INIT(8'h2A)) + \sig_byte_cntr[3]_i_3 + (.I0(DI[3]), + .I1(\INFERRED_GEN.cnt_i_reg[4] ), + .I2(sig_clr_dbc_reg), + .O(\sig_byte_cntr[3]_i_3_n_0 )); + LUT3 #( + .INIT(8'h2A)) + \sig_byte_cntr[3]_i_4 + (.I0(DI[2]), + .I1(\INFERRED_GEN.cnt_i_reg[4] ), + .I2(sig_clr_dbc_reg), + .O(\sig_byte_cntr[3]_i_4_n_0 )); + LUT3 #( + .INIT(8'h2A)) + \sig_byte_cntr[3]_i_5 + (.I0(DI[1]), + .I1(\INFERRED_GEN.cnt_i_reg[4] ), + .I2(sig_clr_dbc_reg), + .O(\sig_byte_cntr[3]_i_5_n_0 )); + LUT4 #( + .INIT(16'hD52A)) + \sig_byte_cntr[3]_i_6 + (.I0(DI[0]), + .I1(\INFERRED_GEN.cnt_i_reg[4] ), + .I2(sig_clr_dbc_reg), + .I3(sig_dre2ibtt_tstrb), + .O(\sig_byte_cntr[3]_i_6_n_0 )); + LUT3 #( + .INIT(8'h2A)) + \sig_byte_cntr[7]_i_3 + (.I0(DI[7]), + .I1(\INFERRED_GEN.cnt_i_reg[4] ), + .I2(sig_clr_dbc_reg), + .O(\sig_byte_cntr[7]_i_3_n_0 )); + LUT3 #( + .INIT(8'h2A)) + \sig_byte_cntr[7]_i_4 + (.I0(DI[6]), + .I1(\INFERRED_GEN.cnt_i_reg[4] ), + .I2(sig_clr_dbc_reg), + .O(\sig_byte_cntr[7]_i_4_n_0 )); + LUT3 #( + .INIT(8'h2A)) + \sig_byte_cntr[7]_i_5 + (.I0(DI[5]), + .I1(\INFERRED_GEN.cnt_i_reg[4] ), + .I2(sig_clr_dbc_reg), + .O(\sig_byte_cntr[7]_i_5_n_0 )); + LUT3 #( + .INIT(8'h2A)) + \sig_byte_cntr[7]_i_6 + (.I0(DI[4]), + .I1(\INFERRED_GEN.cnt_i_reg[4] ), + .I2(sig_clr_dbc_reg), + .O(\sig_byte_cntr[7]_i_6_n_0 )); + LUT3 #( + .INIT(8'h2A)) + \sig_byte_cntr[8]_i_4 + (.I0(DI[8]), + .I1(\INFERRED_GEN.cnt_i_reg[4] ), + .I2(sig_clr_dbc_reg), + .O(\sig_byte_cntr[8]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_byte_cntr_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(\INFERRED_GEN.cnt_i_reg[4] ), + .D(\sig_byte_cntr_reg[3]_i_1_n_7 ), + .Q(DI[0]), + .R(SR[0])); + FDRE #( + .INIT(1'b0)) + \sig_byte_cntr_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(\INFERRED_GEN.cnt_i_reg[4] ), + .D(\sig_byte_cntr_reg[3]_i_1_n_6 ), + .Q(DI[1]), + .R(SR[0])); FDRE #( .INIT(1'b0)) - sig_ok_to_post_rd_addr_reg - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(I_DATA_FIFO_n_41), - .Q(sig_sf_allow_addr_req), - .R(1'b0)); - (* SOFT_HLUTNM = "soft_lutpair70" *) - LUT1 #( - .INIT(2'h1)) - \sig_token_cntr[0]_i_1 - (.I0(sig_token_cntr_reg__0[0]), - .O(\sig_token_cntr[0]_i_1_n_0 )); - LUT6 #( - .INIT(64'hFF0000FD55AAAA5D)) - \sig_token_cntr[1]_i_1 - (.I0(sig_last_mmap_dbeat_reg_reg), - .I1(sig_token_cntr_reg__0[3]), - .I2(sig_token_cntr_reg__0[2]), - .I3(sig_token_cntr_reg__0[0]), - .I4(sig_token_cntr_reg__0[1]), - .I5(sig_posted_to_axi_2_reg), - .O(\sig_token_cntr[1]_i_1_n_0 )); - LUT6 #( - .INIT(64'hFF5F00A0F0FA0D0D)) - \sig_token_cntr[2]_i_1 - (.I0(sig_last_mmap_dbeat_reg_reg), - .I1(sig_token_cntr_reg__0[3]), - .I2(sig_token_cntr_reg__0[0]), - .I3(sig_posted_to_axi_2_reg), - .I4(sig_token_cntr_reg__0[2]), - .I5(sig_token_cntr_reg__0[1]), - .O(\sig_token_cntr[2]_i_1_n_0 )); - LUT6 #( - .INIT(64'h55555576AAAAAA8A)) - \sig_token_cntr[3]_i_1 - (.I0(sig_last_mmap_dbeat_reg_reg), - .I1(sig_token_cntr_reg__0[1]), - .I2(sig_token_cntr_reg__0[3]), - .I3(sig_token_cntr_reg__0[2]), - .I4(sig_token_cntr_reg__0[0]), - .I5(sig_posted_to_axi_2_reg), - .O(\sig_token_cntr[3]_i_1_n_0 )); - LUT6 #( - .INIT(64'hBFFF4000FFCC0003)) - \sig_token_cntr[3]_i_2 - (.I0(sig_posted_to_axi_2_reg), - .I1(sig_token_cntr_reg__0[0]), - .I2(sig_last_mmap_dbeat_reg_reg), - .I3(sig_token_cntr_reg__0[1]), - .I4(sig_token_cntr_reg__0[3]), - .I5(sig_token_cntr_reg__0[2]), - .O(\sig_token_cntr[3]_i_2_n_0 )); + \sig_byte_cntr_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(\INFERRED_GEN.cnt_i_reg[4] ), + .D(\sig_byte_cntr_reg[3]_i_1_n_5 ), + .Q(DI[2]), + .R(SR[0])); FDRE #( .INIT(1'b0)) - \sig_token_cntr_reg[0] - (.C(m_axi_mm2s_aclk), - .CE(\sig_token_cntr[3]_i_1_n_0 ), - .D(\sig_token_cntr[0]_i_1_n_0 ), - .Q(sig_token_cntr_reg__0[0]), - .R(sig_stream_rst)); + \sig_byte_cntr_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(\INFERRED_GEN.cnt_i_reg[4] ), + .D(\sig_byte_cntr_reg[3]_i_1_n_4 ), + .Q(DI[3]), + .R(SR[0])); + CARRY4 \sig_byte_cntr_reg[3]_i_1 + (.CI(1'b0), + .CO({\sig_byte_cntr_reg[3]_i_1_n_0 ,\sig_byte_cntr_reg[3]_i_1_n_1 ,\sig_byte_cntr_reg[3]_i_1_n_2 ,\sig_byte_cntr_reg[3]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,\sig_strb_reg_out_reg[0] }), + .O({\sig_byte_cntr_reg[3]_i_1_n_4 ,\sig_byte_cntr_reg[3]_i_1_n_5 ,\sig_byte_cntr_reg[3]_i_1_n_6 ,\sig_byte_cntr_reg[3]_i_1_n_7 }), + .S({\sig_byte_cntr[3]_i_3_n_0 ,\sig_byte_cntr[3]_i_4_n_0 ,\sig_byte_cntr[3]_i_5_n_0 ,\sig_byte_cntr[3]_i_6_n_0 })); + FDRE #( + .INIT(1'b0)) + \sig_byte_cntr_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(\INFERRED_GEN.cnt_i_reg[4] ), + .D(\sig_byte_cntr_reg[7]_i_2_n_7 ), + .Q(DI[4]), + .R(SR[0])); + FDRE #( + .INIT(1'b0)) + \sig_byte_cntr_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(\INFERRED_GEN.cnt_i_reg[4] ), + .D(\sig_byte_cntr_reg[7]_i_2_n_6 ), + .Q(DI[5]), + .R(SR[0])); + FDRE #( + .INIT(1'b0)) + \sig_byte_cntr_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(\INFERRED_GEN.cnt_i_reg[4] ), + .D(\sig_byte_cntr_reg[7]_i_2_n_5 ), + .Q(DI[6]), + .R(SR[0])); + FDRE #( + .INIT(1'b0)) + \sig_byte_cntr_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(\INFERRED_GEN.cnt_i_reg[4] ), + .D(\sig_byte_cntr_reg[7]_i_2_n_4 ), + .Q(DI[7]), + .R(SR[0])); + CARRY4 \sig_byte_cntr_reg[7]_i_2 + (.CI(\sig_byte_cntr_reg[3]_i_1_n_0 ), + .CO({\sig_byte_cntr_reg[7]_i_2_n_0 ,\sig_byte_cntr_reg[7]_i_2_n_1 ,\sig_byte_cntr_reg[7]_i_2_n_2 ,\sig_byte_cntr_reg[7]_i_2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\sig_byte_cntr_reg[7]_i_2_n_4 ,\sig_byte_cntr_reg[7]_i_2_n_5 ,\sig_byte_cntr_reg[7]_i_2_n_6 ,\sig_byte_cntr_reg[7]_i_2_n_7 }), + .S({\sig_byte_cntr[7]_i_3_n_0 ,\sig_byte_cntr[7]_i_4_n_0 ,\sig_byte_cntr[7]_i_5_n_0 ,\sig_byte_cntr[7]_i_6_n_0 })); + FDRE #( + .INIT(1'b0)) + \sig_byte_cntr_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(\INFERRED_GEN.cnt_i_reg[4] ), + .D(\sig_byte_cntr_reg[8]_i_3_n_7 ), + .Q(DI[8]), + .R(SR[1])); + CARRY4 \sig_byte_cntr_reg[8]_i_3 + (.CI(\sig_byte_cntr_reg[7]_i_2_n_0 ), + .CO(\NLW_sig_byte_cntr_reg[8]_i_3_CO_UNCONNECTED [3:0]), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_sig_byte_cntr_reg[8]_i_3_O_UNCONNECTED [3:1],\sig_byte_cntr_reg[8]_i_3_n_7 }), + .S({1'b0,1'b0,1'b0,\sig_byte_cntr[8]_i_4_n_0 })); + LUT4 #( + .INIT(16'hE000)) + sig_clr_dbc_reg_i_1 + (.I0(sig_dbc_max__3), + .I1(sig_dre2ibtt_tlast), + .I2(\INFERRED_GEN.cnt_i_reg[4] ), + .I3(lsig_set_packer_full__1), + .O(sig_clr_dbeat_cntr0_out)); + (* SOFT_HLUTNM = "soft_lutpair180" *) + LUT5 #( + .INIT(32'h80000000)) + sig_clr_dbc_reg_i_2 + (.I0(sig_burst_dbeat_cntr_reg__0[3]), + .I1(sig_burst_dbeat_cntr_reg__0[1]), + .I2(sig_burst_dbeat_cntr_reg__0[0]), + .I3(sig_burst_dbeat_cntr_reg__0[4]), + .I4(sig_burst_dbeat_cntr_reg__0[2]), + .O(sig_dbc_max__3)); + LUT5 #( + .INIT(32'hAAAA8000)) + sig_clr_dbc_reg_i_3 + (.I0(\INFERRED_GEN.cnt_i_reg[4] ), + .I1(lsig_0ffset_to_to_use__2[1]), + .I2(lsig_0ffset_to_to_use__2[0]), + .I3(lsig_0ffset_to_to_use__2[2]), + .I4(sig_dre2ibtt_tlast), + .O(lsig_set_packer_full__1)); FDRE #( .INIT(1'b0)) - \sig_token_cntr_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(\sig_token_cntr[3]_i_1_n_0 ), - .D(\sig_token_cntr[1]_i_1_n_0 ), - .Q(sig_token_cntr_reg__0[1]), + sig_clr_dbc_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_clr_dbeat_cntr0_out), + .Q(sig_clr_dbc_reg), .R(sig_stream_rst)); FDRE #( .INIT(1'b0)) - \sig_token_cntr_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(\sig_token_cntr[3]_i_1_n_0 ), - .D(\sig_token_cntr[2]_i_1_n_0 ), - .Q(sig_token_cntr_reg__0[2]), + sig_dre2ibtt_eop_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_dre2ibtt_eop), + .Q(DI[10]), .R(sig_stream_rst)); - FDSE #( + FDRE #( .INIT(1'b0)) - \sig_token_cntr_reg[3] - (.C(m_axi_mm2s_aclk), - .CE(\sig_token_cntr[3]_i_1_n_0 ), - .D(\sig_token_cntr[3]_i_2_n_0 ), - .Q(sig_token_cntr_reg__0[3]), - .S(sig_stream_rst)); + sig_dre2ibtt_tlast_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_dre2ibtt_tlast), + .Q(DI[9]), + .R(sig_stream_rst)); endmodule -(* ORIG_REF_NAME = "axi_datamover_rd_status_cntl" *) -module Arty_Z7_20_axi_vdma_0_0_axi_datamover_rd_status_cntl - (sig_rsc2stat_status_valid, - sig_rsc2data_ready, - sig_rd_sts_slverr_reg_reg_0, - sig_inhibit_rdy_n_reg, - sig_push_rd_sts_reg, - sig_rd_sts_reg_full0, +(* ORIG_REF_NAME = "axi_datamover_mm2s_full_wrap" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_mm2s_full_wrap + (sig_rst2all_stop_request, + m_axi_mm2s_arburst, + m_axi_mm2s_arvalid, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , + E, + datamover_idle_reg, + mm2s_halt_cmplt, + decerr_i_reg, + Q, + slverr_i_reg, + interr_i_reg, + m_axi_mm2s_araddr, + m_axi_mm2s_arlen, + m_axi_mm2s_arsize, + m_axi_mm2s_rready, + DIN, + \sig_user_skid_reg_reg[0] , + dm2linebuf_mm2s_tdata, m_axi_mm2s_aclk, - sig_coelsc_reg_full_reg, - sig_rd_sts_decerr_reg0, - sig_data2rsc_calc_err, - sig_data2rsc_slverr); - output sig_rsc2stat_status_valid; - output sig_rsc2data_ready; - output [2:0]sig_rd_sts_slverr_reg_reg_0; - input sig_inhibit_rdy_n_reg; - input sig_push_rd_sts_reg; - input sig_rd_sts_reg_full0; - input m_axi_mm2s_aclk; - input sig_coelsc_reg_full_reg; - input sig_rd_sts_decerr_reg0; - input sig_data2rsc_calc_err; - input sig_data2rsc_slverr; - - wire m_axi_mm2s_aclk; - wire sig_coelsc_reg_full_reg; - wire sig_data2rsc_calc_err; - wire sig_data2rsc_slverr; - wire sig_inhibit_rdy_n_reg; - wire sig_push_rd_sts_reg; - wire sig_rd_sts_decerr_reg0; - wire sig_rd_sts_interr_reg0; - wire sig_rd_sts_reg_full0; - wire sig_rd_sts_slverr_reg0; - wire [2:0]sig_rd_sts_slverr_reg_reg_0; - wire sig_rsc2data_ready; - wire sig_rsc2stat_status_valid; - - FDRE #( - .INIT(1'b0)) - sig_rd_sts_decerr_reg_reg - (.C(m_axi_mm2s_aclk), - .CE(sig_push_rd_sts_reg), - .D(sig_rd_sts_decerr_reg0), - .Q(sig_rd_sts_slverr_reg_reg_0[1]), - .R(sig_inhibit_rdy_n_reg)); - LUT2 #( - .INIT(4'hE)) - sig_rd_sts_interr_reg_i_1 - (.I0(sig_rd_sts_slverr_reg_reg_0[0]), - .I1(sig_data2rsc_calc_err), - .O(sig_rd_sts_interr_reg0)); - FDRE #( - .INIT(1'b0)) - sig_rd_sts_interr_reg_reg - (.C(m_axi_mm2s_aclk), - .CE(sig_push_rd_sts_reg), - .D(sig_rd_sts_interr_reg0), - .Q(sig_rd_sts_slverr_reg_reg_0[0]), - .R(sig_inhibit_rdy_n_reg)); - FDSE #( - .INIT(1'b0)) - sig_rd_sts_reg_empty_reg - (.C(m_axi_mm2s_aclk), - .CE(sig_push_rd_sts_reg), - .D(sig_coelsc_reg_full_reg), - .Q(sig_rsc2data_ready), - .S(sig_inhibit_rdy_n_reg)); - FDRE #( - .INIT(1'b0)) - sig_rd_sts_reg_full_reg - (.C(m_axi_mm2s_aclk), - .CE(sig_push_rd_sts_reg), - .D(sig_rd_sts_reg_full0), - .Q(sig_rsc2stat_status_valid), - .R(sig_inhibit_rdy_n_reg)); - LUT2 #( - .INIT(4'hE)) - sig_rd_sts_slverr_reg_i_1 - (.I0(sig_rd_sts_slverr_reg_reg_0[2]), - .I1(sig_data2rsc_slverr), - .O(sig_rd_sts_slverr_reg0)); - FDRE #( - .INIT(1'b0)) - sig_rd_sts_slverr_reg_reg - (.C(m_axi_mm2s_aclk), - .CE(sig_push_rd_sts_reg), - .D(sig_rd_sts_slverr_reg0), - .Q(sig_rd_sts_slverr_reg_reg_0[2]), - .R(sig_inhibit_rdy_n_reg)); -endmodule - -(* ORIG_REF_NAME = "axi_datamover_rddata_cntl" *) -module Arty_Z7_20_axi_vdma_0_0_axi_datamover_rddata_cntl - (\sig_addr_posted_cntr_reg[2]_0 , - sig_data2addr_stop_req, - sig_data2rsc_calc_err, - sig_data2rsc_slverr, - sig_init_done, - sig_rd_sts_reg_empty_reg, - sig_rd_sts_reg_full0, - sig_rd_sts_decerr_reg0, - sig_wr_fifo, - sig_advance_pipe9_out__1, - sig_push_rd_sts_reg, - DIBDI, - mm2s_strm_wvalid0__1, - m_axi_mm2s_rready, - sig_halt_cmplt_reg, - SR, - m_axi_mm2s_aclk, - sig_mmap_reset_reg_reg, - sig_s_h_halt_reg_reg, - sig_rd_sts_decerr_reg_reg, - sig_mstr2data_cmd_valid, - m_axi_mm2s_rlast, - m_axi_mm2s_rvalid, + m_axi_mm2s_rdata, out, - m_axi_mm2s_rresp, - sig_rsc2data_ready, - sig_rsc2stat_status_valid, - FIFO_Full_reg, - sig_inhibit_rdy_n, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_addr2rsc_calc_error, - sig_addr_reg_empty, - mm2s_halt_cmplt, + halt_i_reg, + prmry_resetn_i_reg, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 , + cmnd_wr, + mm2s_halt, + p_71_out, + datamover_idle, + m_axi_mm2s_rlast, + m_axi_mm2s_arready, in, - sig_posted_to_axi_reg); - output \sig_addr_posted_cntr_reg[2]_0 ; - output sig_data2addr_stop_req; - output sig_data2rsc_calc_err; - output sig_data2rsc_slverr; - output sig_init_done; - output sig_rd_sts_reg_empty_reg; - output sig_rd_sts_reg_full0; - output sig_rd_sts_decerr_reg0; - output sig_wr_fifo; - output sig_advance_pipe9_out__1; - output sig_push_rd_sts_reg; - output [1:0]DIBDI; - output mm2s_strm_wvalid0__1; + p_56_out, + p_58_out, + sts_tready_reg, + m_axi_mm2s_rvalid, + m_axi_mm2s_rresp); + output sig_rst2all_stop_request; + output [0:0]m_axi_mm2s_arburst; + output m_axi_mm2s_arvalid; + output \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + output [0:0]E; + output datamover_idle_reg; + output mm2s_halt_cmplt; + output decerr_i_reg; + output [0:0]Q; + output slverr_i_reg; + output interr_i_reg; + output [31:0]m_axi_mm2s_araddr; + output [4:0]m_axi_mm2s_arlen; + output [1:0]m_axi_mm2s_arsize; output m_axi_mm2s_rready; - output sig_halt_cmplt_reg; - input [0:0]SR; + output [0:0]DIN; + output \sig_user_skid_reg_reg[0] ; + output [31:0]dm2linebuf_mm2s_tdata; input m_axi_mm2s_aclk; - input sig_mmap_reset_reg_reg; - input sig_s_h_halt_reg_reg; - input [0:0]sig_rd_sts_decerr_reg_reg; - input sig_mstr2data_cmd_valid; + input [63:0]m_axi_mm2s_rdata; + input out; + input halt_i_reg; + input prmry_resetn_i_reg; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; + input cmnd_wr; + input mm2s_halt; + input [0:0]p_71_out; + input datamover_idle; input m_axi_mm2s_rlast; + input m_axi_mm2s_arready; + input [48:0]in; + input p_56_out; + input p_58_out; + input sts_tready_reg; input m_axi_mm2s_rvalid; - input out; input [1:0]m_axi_mm2s_rresp; - input sig_rsc2data_ready; - input sig_rsc2stat_status_valid; - input FIFO_Full_reg; - input sig_inhibit_rdy_n; - input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - input sig_addr2rsc_calc_error; - input sig_addr_reg_empty; - input mm2s_halt_cmplt; - input [7:0]in; - input sig_posted_to_axi_reg; - wire [1:0]DIBDI; - wire FIFO_Full_reg; - wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_17 ; - wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_18 ; - wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_19 ; - wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_3 ; - wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_4 ; - wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_5 ; - wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_6 ; - wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_7 ; - wire [0:0]SR; - wire [7:0]in; + wire [0:0]DIN; + wire [0:0]E; + wire \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/sig_wr_fifo ; + wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_wr_fifo ; + wire \GEN_INCLUDE_MM2S_SF.I_RD_SF_n_0 ; + wire \GEN_INCLUDE_MM2S_SF.I_RD_SF_n_3 ; + wire \GEN_INCLUDE_MM2S_SF.I_RD_SF_n_6 ; + wire \GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_inhibit_rdy_n ; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; + wire I_ADDR_CNTL_n_0; + wire I_ADDR_CNTL_n_6; + wire \I_CMD_FIFO/sig_rd_empty ; + wire I_CMD_STATUS_n_0; + wire I_CMD_STATUS_n_1; + wire I_CMD_STATUS_n_4; + wire \I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/cntr_en ; + wire \I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_17_out ; + wire I_MSTR_PCC_n_1; + wire I_MSTR_PCC_n_3; + wire I_MSTR_PCC_n_4; + wire I_MSTR_PCC_n_44; + wire I_MSTR_PCC_n_5; + wire I_MSTR_PCC_n_6; + wire I_MSTR_PCC_n_7; + wire I_RD_DATA_CNTL_n_1; + wire I_RD_DATA_CNTL_n_17; + wire I_RD_DATA_CNTL_n_9; + wire \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_inhibit_rdy_n ; + wire \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg ; + wire \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg2 ; + wire \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_wr_fifo ; + wire [0:0]Q; + wire cmnd_wr; + wire datamover_idle; + wire datamover_idle_reg; + wire decerr_i_reg; + wire [31:0]dm2linebuf_mm2s_tdata; + wire halt_i_reg; + wire [48:0]in; + wire interr_i_reg; wire m_axi_mm2s_aclk; + wire [31:0]m_axi_mm2s_araddr; + wire [0:0]m_axi_mm2s_arburst; + wire [4:0]m_axi_mm2s_arlen; + wire m_axi_mm2s_arready; + wire [1:0]m_axi_mm2s_arsize; + wire m_axi_mm2s_arvalid; + wire [63:0]m_axi_mm2s_rdata; wire m_axi_mm2s_rlast; wire m_axi_mm2s_rready; wire [1:0]m_axi_mm2s_rresp; wire m_axi_mm2s_rvalid; + wire mm2s_halt; wire mm2s_halt_cmplt; - wire mm2s_strm_wvalid0__1; wire out; - wire [3:0]p_0_in; - wire sig_addr2rsc_calc_error; + wire p_56_out; + wire p_58_out; + wire [0:0]p_71_out; + wire prmry_resetn_i_reg; + wire sig_addr2data_addr_posted; wire [2:0]sig_addr_posted_cntr; - wire \sig_addr_posted_cntr[0]_i_1_n_0 ; - wire \sig_addr_posted_cntr[1]_i_1_n_0 ; - wire \sig_addr_posted_cntr[2]_i_1_n_0 ; - wire sig_addr_posted_cntr_eq_0__1; - wire \sig_addr_posted_cntr_reg[2]_0 ; - wire sig_addr_reg_empty; - wire sig_advance_pipe9_out__1; - wire sig_cmd_cmplt_last_dbeat; - wire [35:32]sig_cmd_fifo_data_out; + wire sig_calc_error_pushed; + wire [63:0]sig_cmd2mstr_command; wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - wire sig_coelsc_decerr_reg0; - wire sig_coelsc_interr_reg0; - wire sig_coelsc_reg_full_i_1_n_0; - wire sig_coelsc_slverr_reg0; wire sig_data2addr_stop_req; - wire sig_data2rsc_calc_err; wire sig_data2rsc_decerr; - wire sig_data2rsc_slverr; - wire sig_data2rsc_valid; - wire sig_data2rst_stop_cmplt; - wire \sig_dbeat_cntr[5]_i_2_n_0 ; - wire \sig_dbeat_cntr[7]_i_3_n_0 ; - wire \sig_dbeat_cntr[7]_i_4_n_0 ; - wire \sig_dbeat_cntr[7]_i_5_n_0 ; - wire sig_dbeat_cntr_eq_1; - wire [7:0]sig_dbeat_cntr_reg__0; - wire sig_dqual_reg_empty; - wire sig_dqual_reg_full; - wire sig_good_mmap_dbeat7_out__0; - wire sig_halt_cmplt_reg; - wire sig_halt_reg_dly1; - wire sig_halt_reg_dly2; + wire sig_data2sf_cmd_cmplt; + wire [8:8]sig_data_fifo_wr_cnt; wire sig_halt_reg_dly3; - wire sig_inhibit_rdy_n; - wire sig_init_done; - wire sig_last_dbeat; - wire sig_last_mmap_dbeat; - wire sig_ld_new_cmd_reg; - wire sig_mmap_reset_reg_reg; + wire sig_input_reg_empty; + wire [31:3]sig_mstr2addr_addr; + wire [0:0]sig_mstr2addr_burst; + wire sig_mstr2addr_cmd_valid; + wire sig_mstr2data_cmd_cmplt; wire sig_mstr2data_cmd_valid; + wire sig_mstr2data_eof; + wire sig_mstr2data_sequential; + wire sig_mstr2sf_cmd_valid; wire sig_next_calc_error_reg; - wire sig_next_cmd_cmplt_reg; - wire sig_next_eof_reg; - wire sig_next_sequential_reg; - wire sig_posted_to_axi_reg; - wire sig_push_coelsc_reg; - wire sig_push_dqual_reg; wire sig_push_rd_sts_reg; - wire sig_rd_sts_decerr_reg0; - wire [0:0]sig_rd_sts_decerr_reg_reg; - wire sig_rd_sts_reg_empty_reg; + wire sig_rd_sts_interr_reg0; wire sig_rd_sts_reg_full0; + wire sig_rd_sts_slverr_reg0; + wire sig_rdc2sf_wlast; wire sig_rsc2data_ready; + wire [6:4]sig_rsc2stat_status; wire sig_rsc2stat_status_valid; - wire sig_s_h_halt_reg_reg; - wire sig_wr_fifo; + wire sig_rst2all_stop_request; + wire sig_sf_allow_addr_req; + wire sig_sm_halt_reg; + wire sig_stream_rst; + wire \sig_user_skid_reg_reg[0] ; + wire [2:0]sig_xfer_addr_reg; + wire slverr_i_reg; + wire sts_tready_reg; - LUT6 #( - .INIT(64'hFFFF002000200020)) - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_5 - (.I0(sig_data2addr_stop_req), - .I1(sig_next_calc_error_reg), - .I2(sig_dqual_reg_full), - .I3(sig_addr_posted_cntr_eq_0__1), - .I4(sig_next_cmd_cmplt_reg), - .I5(m_axi_mm2s_rlast), - .O(DIBDI[1])); - LUT6 #( - .INIT(64'hFFFF002000200020)) - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_6 - (.I0(sig_data2addr_stop_req), - .I1(sig_next_calc_error_reg), - .I2(sig_dqual_reg_full), - .I3(sig_addr_posted_cntr_eq_0__1), - .I4(sig_next_eof_reg), - .I5(m_axi_mm2s_rlast), - .O(DIBDI[0])); - LUT6 #( - .INIT(64'h0000FE0000000000)) - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_7 - (.I0(sig_addr_posted_cntr[2]), - .I1(sig_addr_posted_cntr[0]), - .I2(sig_addr_posted_cntr[1]), - .I3(sig_dqual_reg_full), - .I4(sig_next_calc_error_reg), - .I5(sig_data2addr_stop_req), - .O(mm2s_strm_wvalid0__1)); - LUT6 #( - .INIT(64'h000000000000FE00)) - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_8 - (.I0(sig_addr_posted_cntr[2]), - .I1(sig_addr_posted_cntr[0]), - .I2(sig_addr_posted_cntr[1]), - .I3(sig_dqual_reg_full), - .I4(sig_next_calc_error_reg), - .I5(sig_data2rsc_valid), - .O(sig_advance_pipe9_out__1)); - Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized2 \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO - (.D({\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_4 ,\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_5 ,\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_6 ,\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_7 ,p_0_in}), - .E(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_3 ), - .FIFO_Full_reg(FIFO_Full_reg), - .Q(sig_dbeat_cntr_reg__0), - .SR(SR), - .in(in), + Arty_Z7_20_axi_vdma_0_0_axi_datamover_rd_sf \GEN_INCLUDE_MM2S_SF.I_RD_SF + (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (sig_data_fifo_wr_cnt), + .DIBDI({sig_data2sf_cmd_cmplt,sig_rdc2sf_wlast}), + .DIN(DIN), + .E(\I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_17_out ), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1 (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .\INFERRED_GEN.cnt_i_reg[1] (\GEN_INCLUDE_MM2S_SF.I_RD_SF_n_3 ), + .SR(sig_stream_rst), + .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), + .\gc1.count_reg[7] (\GEN_INCLUDE_MM2S_SF.I_RD_SF_n_6 ), + .in(sig_xfer_addr_reg[2]), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .m_axi_mm2s_rdata(m_axi_mm2s_rdata), + .out(\GEN_INCLUDE_MM2S_SF.I_RD_SF_n_0 ), + .prmry_resetn_i_reg(prmry_resetn_i_reg), + .ram_full_i_reg(I_RD_DATA_CNTL_n_17), + .ram_full_i_reg_0(\I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/cntr_en ), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_inhibit_rdy_n(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_inhibit_rdy_n ), + .sig_init_reg(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg ), + .sig_init_reg2(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg2 ), + .sig_last_mmap_dbeat_reg_reg(I_RD_DATA_CNTL_n_1), + .sig_mstr2sf_cmd_valid(sig_mstr2sf_cmd_valid), + .sig_posted_to_axi_2_reg(I_ADDR_CNTL_n_0), + .sig_sf_allow_addr_req(sig_sf_allow_addr_req), + .\sig_user_skid_reg_reg[0] (\sig_user_skid_reg_reg[0] ), + .sig_wr_fifo(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_wr_fifo )); + Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl I_ADDR_CNTL + (.SR(sig_stream_rst), + .in({I_MSTR_PCC_n_1,sig_mstr2addr_burst,I_MSTR_PCC_n_3,I_MSTR_PCC_n_4,I_MSTR_PCC_n_5,I_MSTR_PCC_n_6,I_MSTR_PCC_n_7,sig_mstr2addr_addr,sig_xfer_addr_reg}), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .m_axi_mm2s_araddr(m_axi_mm2s_araddr), + .m_axi_mm2s_arburst(m_axi_mm2s_arburst), + .m_axi_mm2s_arlen(m_axi_mm2s_arlen), + .m_axi_mm2s_arready(m_axi_mm2s_arready), + .m_axi_mm2s_arsize(m_axi_mm2s_arsize), + .m_axi_mm2s_arvalid(m_axi_mm2s_arvalid), + .out(I_ADDR_CNTL_n_0), + .\sig_addr_posted_cntr_reg[2] (sig_addr2data_addr_posted), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_data2addr_stop_req(sig_data2addr_stop_req), + .sig_halt_cmplt_reg(I_ADDR_CNTL_n_6), + .sig_halt_reg_dly3(sig_halt_reg_dly3), + .sig_init_reg(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg ), + .sig_init_reg2(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg2 ), + .sig_mstr2addr_cmd_valid(sig_mstr2addr_cmd_valid), + .sig_sf_allow_addr_req(sig_sf_allow_addr_req), + .sig_wr_fifo(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/sig_wr_fifo )); + Arty_Z7_20_axi_vdma_0_0_axi_datamover_cmd_status I_CMD_STATUS + (.E(E), + .FIFO_Full_reg(Q), + .\INFERRED_GEN.cnt_i_reg[1] (I_CMD_STATUS_n_0), + .Q(\I_CMD_FIFO/sig_rd_empty ), + .SR(sig_stream_rst), + .cmnd_wr(cmnd_wr), + .decerr_i_reg(decerr_i_reg), + .in(I_MSTR_PCC_n_1), + .interr_i_reg(interr_i_reg), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .mm2s_halt(mm2s_halt), + .out({sig_cmd2mstr_command[63:32],sig_cmd2mstr_command[30],sig_cmd2mstr_command[23],sig_cmd2mstr_command[15:0]}), + .p_56_out(p_56_out), + .p_58_out(p_58_out), + .\s_axis_cmd_tdata_reg[63] (in), + .sig_calc_error_pushed(sig_calc_error_pushed), + .sig_calc_error_pushed_reg(I_MSTR_PCC_n_44), + .sig_calc_error_reg_reg(I_CMD_STATUS_n_1), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_inhibit_rdy_n(\GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_inhibit_rdy_n ), + .sig_init_reg(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg ), + .sig_init_reg2(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg2 ), + .sig_input_reg_empty(sig_input_reg_empty), + .sig_rd_sts_slverr_reg_reg(I_CMD_STATUS_n_4), + .sig_rd_sts_slverr_reg_reg_0(sig_rsc2stat_status), + .sig_rsc2stat_status_valid(sig_rsc2stat_status_valid), + .sig_sm_halt_reg(sig_sm_halt_reg), + .slverr_i_reg(slverr_i_reg), + .sts_tready_reg(sts_tready_reg)); + Arty_Z7_20_axi_vdma_0_0_axi_datamover_pcc I_MSTR_PCC + (.FIFO_Full_reg(I_MSTR_PCC_n_44), + .FIFO_Full_reg_0(\GEN_INCLUDE_MM2S_SF.I_RD_SF_n_3 ), + .Q(\I_CMD_FIFO/sig_rd_empty ), + .SR(sig_stream_rst), + .in({I_MSTR_PCC_n_1,sig_mstr2addr_burst,I_MSTR_PCC_n_3,I_MSTR_PCC_n_4,I_MSTR_PCC_n_5,I_MSTR_PCC_n_6,I_MSTR_PCC_n_7,sig_mstr2addr_addr,sig_xfer_addr_reg}), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .out({sig_cmd2mstr_command[63:32],sig_cmd2mstr_command[30],sig_cmd2mstr_command[23],sig_cmd2mstr_command[15:0]}), + .sig_calc_error_pushed(sig_calc_error_pushed), + .sig_calc_error_reg_reg_0(I_CMD_STATUS_n_1), + .sig_inhibit_rdy_n(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_inhibit_rdy_n ), + .sig_init_reg(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg ), + .sig_input_reg_empty(sig_input_reg_empty), + .sig_mstr2addr_cmd_valid(sig_mstr2addr_cmd_valid), + .sig_mstr2data_cmd_valid(sig_mstr2data_cmd_valid), + .sig_mstr2data_sequential(sig_mstr2data_sequential), + .sig_mstr2sf_cmd_valid(sig_mstr2sf_cmd_valid), + .sig_next_cmd_cmplt_reg_reg({sig_mstr2data_cmd_cmplt,sig_mstr2data_eof}), + .sig_sm_halt_reg(sig_sm_halt_reg), + .sig_wr_fifo(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_wr_fifo ), + .sig_wr_fifo_0(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_wr_fifo ), + .sig_wr_fifo_1(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/sig_wr_fifo )); + Arty_Z7_20_axi_vdma_0_0_axi_datamover_rddata_cntl I_RD_DATA_CNTL + (.DIBDI({sig_data2sf_cmd_cmplt,sig_rdc2sf_wlast}), + .E(\I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_17_out ), + .FIFO_Full_reg(I_CMD_STATUS_n_0), + .SR(sig_stream_rst), + .\count_reg[0] (\I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/cntr_en ), + .in({I_MSTR_PCC_n_1,sig_mstr2data_cmd_cmplt,sig_mstr2data_sequential,sig_mstr2data_eof,I_MSTR_PCC_n_3,I_MSTR_PCC_n_4,I_MSTR_PCC_n_5,I_MSTR_PCC_n_6,I_MSTR_PCC_n_7}), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), .m_axi_mm2s_rlast(m_axi_mm2s_rlast), + .m_axi_mm2s_rready(m_axi_mm2s_rready), + .m_axi_mm2s_rresp(m_axi_mm2s_rresp), .m_axi_mm2s_rvalid(m_axi_mm2s_rvalid), - .out(sig_cmd_fifo_data_out), - .ram_full_i_reg(out), - .sel(sig_wr_fifo), + .out(\GEN_INCLUDE_MM2S_SF.I_RD_SF_n_0 ), + .ram_empty_fb_i_reg(\GEN_INCLUDE_MM2S_SF.I_RD_SF_n_6 ), + .ram_full_i_reg(I_RD_DATA_CNTL_n_17), + .ram_full_i_reg_0(sig_data_fifo_wr_cnt), .sig_addr_posted_cntr(sig_addr_posted_cntr), - .sig_advance_pipe9_out__1(sig_advance_pipe9_out__1), + .\sig_addr_posted_cntr_reg[2]_0 (I_RD_DATA_CNTL_n_1), .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .sig_dbeat_cntr_eq_1(sig_dbeat_cntr_eq_1), - .\sig_dbeat_cntr_reg[2] (\sig_dbeat_cntr[7]_i_3_n_0 ), - .\sig_dbeat_cntr_reg[3] (\sig_dbeat_cntr[5]_i_2_n_0 ), - .\sig_dbeat_cntr_reg[4] (\sig_dbeat_cntr[7]_i_4_n_0 ), - .sig_dqual_reg_empty(sig_dqual_reg_empty), - .sig_dqual_reg_full(sig_dqual_reg_full), - .sig_good_mmap_dbeat7_out__0(sig_good_mmap_dbeat7_out__0), - .sig_halt_reg_reg(sig_data2addr_stop_req), - .sig_inhibit_rdy_n(sig_inhibit_rdy_n), - .sig_init_done(sig_init_done), - .sig_last_dbeat(sig_last_dbeat), - .sig_last_dbeat_reg(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_18 ), - .sig_ld_new_cmd_reg(sig_ld_new_cmd_reg), - .sig_ld_new_cmd_reg_reg(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_17 ), - .sig_mmap_reset_reg_reg(sig_mmap_reset_reg_reg), + .sig_data2addr_stop_req(sig_data2addr_stop_req), + .sig_data2rsc_decerr(sig_data2rsc_decerr), + .sig_halt_reg_dly3(sig_halt_reg_dly3), + .sig_inhibit_rdy_n(\GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_inhibit_rdy_n ), + .sig_init_reg(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg ), + .sig_init_reg2(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg2 ), .sig_mstr2data_cmd_valid(sig_mstr2data_cmd_valid), .sig_next_calc_error_reg(sig_next_calc_error_reg), - .sig_next_cmd_cmplt_reg_reg(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_19 ), - .sig_next_sequential_reg(sig_next_sequential_reg), - .sig_push_dqual_reg(sig_push_dqual_reg), + .sig_posted_to_axi_reg(sig_addr2data_addr_posted), + .sig_push_rd_sts_reg(sig_push_rd_sts_reg), + .sig_rd_sts_interr_reg0(sig_rd_sts_interr_reg0), + .sig_rd_sts_reg_empty_reg(I_RD_DATA_CNTL_n_9), + .sig_rd_sts_reg_full0(sig_rd_sts_reg_full0), + .sig_rd_sts_slverr_reg0(sig_rd_sts_slverr_reg0), + .sig_rd_sts_slverr_reg_reg({sig_rsc2stat_status[6],sig_rsc2stat_status[4]}), + .sig_rsc2data_ready(sig_rsc2data_ready), + .sig_rsc2stat_status_valid(sig_rsc2stat_status_valid), + .sig_rst2all_stop_request(sig_rst2all_stop_request), + .sig_wr_fifo(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_wr_fifo )); + Arty_Z7_20_axi_vdma_0_0_axi_datamover_rd_status_cntl I_RD_STATUS_CNTLR + (.m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .sig_coelsc_reg_full_reg(I_RD_DATA_CNTL_n_9), + .sig_data2rsc_decerr(sig_data2rsc_decerr), + .sig_inhibit_rdy_n_reg(I_CMD_STATUS_n_4), + .sig_push_rd_sts_reg(sig_push_rd_sts_reg), + .sig_rd_sts_interr_reg0(sig_rd_sts_interr_reg0), + .sig_rd_sts_reg_full0(sig_rd_sts_reg_full0), + .sig_rd_sts_slverr_reg0(sig_rd_sts_slverr_reg0), + .sig_rd_sts_slverr_reg_reg_0(sig_rsc2stat_status), + .sig_rsc2data_ready(sig_rsc2data_ready), .sig_rsc2stat_status_valid(sig_rsc2stat_status_valid)); - LUT6 #( - .INIT(64'h0010001000000010)) - m_axi_mm2s_rready_INST_0 - (.I0(sig_data2rsc_valid), - .I1(sig_next_calc_error_reg), - .I2(sig_dqual_reg_full), - .I3(sig_addr_posted_cntr_eq_0__1), - .I4(out), - .I5(sig_data2addr_stop_req), - .O(m_axi_mm2s_rready)); - (* SOFT_HLUTNM = "soft_lutpair109" *) - LUT3 #( - .INIT(8'h01)) - m_axi_mm2s_rready_INST_0_i_1 - (.I0(sig_addr_posted_cntr[1]), - .I1(sig_addr_posted_cntr[0]), - .I2(sig_addr_posted_cntr[2]), - .O(sig_addr_posted_cntr_eq_0__1)); - (* SOFT_HLUTNM = "soft_lutpair108" *) + Arty_Z7_20_axi_vdma_0_0_axi_datamover_reset_20 I_RESET + (.SR(sig_stream_rst), + .datamover_idle(datamover_idle), + .datamover_idle_reg(datamover_idle_reg), + .halt_i_reg(halt_i_reg), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .mm2s_halt(mm2s_halt), + .mm2s_halt_cmplt(mm2s_halt_cmplt), + .out(out), + .p_71_out(p_71_out), + .sig_addr_posted_cntr(sig_addr_posted_cntr), + .sig_calc_error_reg_reg(I_ADDR_CNTL_n_6), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_next_calc_error_reg(sig_next_calc_error_reg), + .sig_rst2all_stop_request(sig_rst2all_stop_request)); +endmodule + +(* ORIG_REF_NAME = "axi_datamover_mssai_skid_buf" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_mssai_skid_buf + (out, + \sig_data_skid_reg_reg[7]_0 , + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][0] , + sig_dre2ibtt_tstrb, + sig_strm_tlast, + RD_EN, + \sig_byte_cntr_reg[3] , + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][0]_0 , + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][0] , + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][0] , + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][0] , + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][0] , + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][0] , + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][0] , + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][0] , + sig_dre2ibtt_eop_reg_reg, + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7] , + m_axi_s2mm_aclk, + sig_stream_rst, + DOUT, + E, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + EMPTY, + \INFERRED_GEN.cnt_i_reg[4] , + sig_clr_dbc_reg, + sig_init_reg, + \GEN_INDET_BTT.lsig_absorb2tlast_reg , + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 , + sig_eop_halt_xfer, + Q, + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 , + p_0_in, + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ); + output out; + output \sig_data_skid_reg_reg[7]_0 ; + output \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][0] ; + output sig_dre2ibtt_tstrb; + output sig_strm_tlast; + output RD_EN; + output [0:0]\sig_byte_cntr_reg[3] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][0]_0 ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][0] ; + output sig_dre2ibtt_eop_reg_reg; + output [7:0]\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7] ; + input m_axi_s2mm_aclk; + input sig_stream_rst; + input [8:0]DOUT; + input [0:0]E; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input EMPTY; + input \INFERRED_GEN.cnt_i_reg[4] ; + input sig_clr_dbc_reg; + input sig_init_reg; + input \GEN_INDET_BTT.lsig_absorb2tlast_reg ; + input \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ; + input sig_eop_halt_xfer; + input [0:0]Q; + input \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ; + input p_0_in; + input \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ; + + wire [8:0]DOUT; + wire [0:0]E; + wire EMPTY; + wire \GEN_INDET_BTT.lsig_absorb2tlast_reg ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][0]_0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][0] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][0] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][0] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][0] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][0] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ; + wire [7:0]\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][0] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ; + wire \INFERRED_GEN.cnt_i_reg[4] ; + wire [0:0]Q; + wire RD_EN; + wire m_axi_s2mm_aclk; + wire p_0_in; + wire [0:0]\sig_byte_cntr_reg[3] ; + wire sig_clr_dbc_reg; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire [7:0]sig_data_skid_mux_out; + wire [7:0]sig_data_skid_reg; + wire sig_dre2ibtt_eop_reg_reg; + wire sig_dre2ibtt_tstrb; + wire sig_eop_halt_xfer; + wire sig_init_reg; + wire sig_last_reg_out_i_1__1_n_0; + wire sig_last_skid_reg; + wire sig_last_skid_reg_i_1__0_n_0; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_m_valid_dup; + wire sig_m_valid_dup_i_1_n_0; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_m_valid_out; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_s_ready_dup; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_s_ready_dup2; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_s_ready_dup3; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_s_ready_dup4; + wire sig_s_ready_dup_i_1__0_n_0; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_s_ready_out; + wire \sig_strb_reg_out[0]_i_1_n_0 ; + wire sig_strb_skid_reg; + wire \sig_strb_skid_reg[0]_i_1_n_0 ; + wire sig_stream_rst; + wire sig_strm_tlast; + + assign \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][0] = sig_m_valid_out; + assign out = sig_m_valid_dup; + assign \sig_data_skid_reg_reg[7]_0 = sig_s_ready_out; LUT5 #( - .INIT(32'hEA5555A8)) - \sig_addr_posted_cntr[0]_i_1 - (.I0(\sig_addr_posted_cntr_reg[2]_0 ), - .I1(sig_addr_posted_cntr[1]), - .I2(sig_addr_posted_cntr[2]), - .I3(sig_posted_to_axi_reg), - .I4(sig_addr_posted_cntr[0]), - .O(\sig_addr_posted_cntr[0]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair109" *) + .INIT(32'h00080000)) + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg[0][0]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ), + .I1(sig_m_valid_out), + .I2(sig_eop_halt_xfer), + .I3(Q), + .I4(sig_strm_tlast), + .O(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][0]_0 )); LUT5 #( - .INIT(32'hFA04DFA0)) - \sig_addr_posted_cntr[1]_i_1 - (.I0(sig_posted_to_axi_reg), - .I1(sig_addr_posted_cntr[2]), - .I2(sig_addr_posted_cntr[0]), - .I3(sig_addr_posted_cntr[1]), - .I4(\sig_addr_posted_cntr_reg[2]_0 ), - .O(\sig_addr_posted_cntr[1]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair108" *) + .INIT(32'h00080000)) + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg[1][0]_i_1 + (.I0(p_0_in), + .I1(sig_m_valid_out), + .I2(sig_eop_halt_xfer), + .I3(Q), + .I4(sig_strm_tlast), + .O(\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][0] )); LUT5 #( - .INIT(32'hCCC8ECCC)) - \sig_addr_posted_cntr[2]_i_1 - (.I0(sig_posted_to_axi_reg), - .I1(sig_addr_posted_cntr[2]), - .I2(sig_addr_posted_cntr[0]), - .I3(sig_addr_posted_cntr[1]), - .I4(\sig_addr_posted_cntr_reg[2]_0 ), - .O(\sig_addr_posted_cntr[2]_i_1_n_0 )); + .INIT(32'h00080000)) + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg[2][0]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ), + .I1(sig_m_valid_out), + .I2(sig_eop_halt_xfer), + .I3(Q), + .I4(sig_strm_tlast), + .O(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][0] )); + LUT5 #( + .INIT(32'h00080000)) + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg[3][0]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ), + .I1(sig_m_valid_out), + .I2(sig_eop_halt_xfer), + .I3(Q), + .I4(sig_strm_tlast), + .O(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][0] )); + LUT5 #( + .INIT(32'h00080000)) + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg[4][0]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ), + .I1(sig_m_valid_out), + .I2(sig_eop_halt_xfer), + .I3(Q), + .I4(sig_strm_tlast), + .O(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][0] )); + LUT5 #( + .INIT(32'h00080000)) + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg[5][0]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ), + .I1(sig_m_valid_out), + .I2(sig_eop_halt_xfer), + .I3(Q), + .I4(sig_strm_tlast), + .O(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][0] )); + LUT5 #( + .INIT(32'h00080000)) + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg[6][0]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ), + .I1(sig_m_valid_out), + .I2(sig_eop_halt_xfer), + .I3(Q), + .I4(sig_strm_tlast), + .O(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][0] )); + LUT5 #( + .INIT(32'h00080000)) + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg[7][0]_i_1 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ), + .I1(sig_m_valid_out), + .I2(sig_eop_halt_xfer), + .I3(Q), + .I4(sig_strm_tlast), + .O(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][0] )); + LUT2 #( + .INIT(4'h2)) + \gf18e1_inst.sngfifo18e1_i_1 + (.I0(sig_s_ready_out), + .I1(EMPTY), + .O(RD_EN)); + LUT3 #( + .INIT(8'h2A)) + \sig_byte_cntr[3]_i_2 + (.I0(sig_dre2ibtt_tstrb), + .I1(\INFERRED_GEN.cnt_i_reg[4] ), + .I2(sig_clr_dbc_reg), + .O(\sig_byte_cntr_reg[3] )); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[0]_i_1 + (.I0(sig_data_skid_reg[0]), + .I1(DOUT[0]), + .I2(sig_s_ready_dup2), + .O(sig_data_skid_mux_out[0])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[1]_i_1 + (.I0(sig_data_skid_reg[1]), + .I1(DOUT[1]), + .I2(sig_s_ready_dup2), + .O(sig_data_skid_mux_out[1])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[2]_i_1 + (.I0(sig_data_skid_reg[2]), + .I1(DOUT[2]), + .I2(sig_s_ready_dup2), + .O(sig_data_skid_mux_out[2])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[3]_i_1 + (.I0(sig_data_skid_reg[3]), + .I1(DOUT[3]), + .I2(sig_s_ready_dup2), + .O(sig_data_skid_mux_out[3])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[4]_i_1 + (.I0(sig_data_skid_reg[4]), + .I1(DOUT[4]), + .I2(sig_s_ready_dup2), + .O(sig_data_skid_mux_out[4])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[5]_i_1 + (.I0(sig_data_skid_reg[5]), + .I1(DOUT[5]), + .I2(sig_s_ready_dup2), + .O(sig_data_skid_mux_out[5])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[6]_i_1 + (.I0(sig_data_skid_reg[6]), + .I1(DOUT[6]), + .I2(sig_s_ready_dup2), + .O(sig_data_skid_mux_out[6])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[7]_i_2 + (.I0(sig_data_skid_reg[7]), + .I1(DOUT[7]), + .I2(sig_s_ready_dup2), + .O(sig_data_skid_mux_out[7])); FDRE #( .INIT(1'b0)) - \sig_addr_posted_cntr_reg[0] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\sig_addr_posted_cntr[0]_i_1_n_0 ), - .Q(sig_addr_posted_cntr[0]), - .R(SR)); + \sig_data_reg_out_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[0]), + .Q(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7] [0]), + .R(1'b0)); FDRE #( .INIT(1'b0)) - \sig_addr_posted_cntr_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\sig_addr_posted_cntr[1]_i_1_n_0 ), - .Q(sig_addr_posted_cntr[1]), - .R(SR)); + \sig_data_reg_out_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[1]), + .Q(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7] [1]), + .R(1'b0)); FDRE #( .INIT(1'b0)) - \sig_addr_posted_cntr_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\sig_addr_posted_cntr[2]_i_1_n_0 ), - .Q(sig_addr_posted_cntr[2]), - .R(SR)); - (* SOFT_HLUTNM = "soft_lutpair110" *) - LUT4 #( - .INIT(16'hFF80)) - sig_coelsc_decerr_reg_i_1 - (.I0(m_axi_mm2s_rresp[1]), - .I1(m_axi_mm2s_rvalid), - .I2(m_axi_mm2s_rresp[0]), - .I3(sig_data2rsc_decerr), - .O(sig_coelsc_decerr_reg0)); + \sig_data_reg_out_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[2]), + .Q(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7] [2]), + .R(1'b0)); FDRE #( .INIT(1'b0)) - sig_coelsc_decerr_reg_reg - (.C(m_axi_mm2s_aclk), - .CE(sig_push_coelsc_reg), - .D(sig_coelsc_decerr_reg0), - .Q(sig_data2rsc_decerr), - .R(sig_coelsc_reg_full_i_1_n_0)); - (* SOFT_HLUTNM = "soft_lutpair111" *) - LUT2 #( - .INIT(4'hE)) - sig_coelsc_interr_reg_i_1 - (.I0(sig_next_calc_error_reg), - .I1(sig_data2rsc_calc_err), - .O(sig_coelsc_interr_reg0)); + \sig_data_reg_out_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[3]), + .Q(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7] [3]), + .R(1'b0)); FDRE #( .INIT(1'b0)) - sig_coelsc_interr_reg_reg - (.C(m_axi_mm2s_aclk), - .CE(sig_push_coelsc_reg), - .D(sig_coelsc_interr_reg0), - .Q(sig_data2rsc_calc_err), - .R(sig_coelsc_reg_full_i_1_n_0)); - LUT5 #( - .INIT(32'h2A00FFFF)) - sig_coelsc_reg_full_i_1 - (.I0(sig_data2rsc_valid), - .I1(sig_ld_new_cmd_reg), - .I2(sig_next_calc_error_reg), - .I3(sig_rsc2data_ready), - .I4(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .O(sig_coelsc_reg_full_i_1_n_0)); - LUT4 #( - .INIT(16'hF444)) - sig_coelsc_reg_full_i_2 - (.I0(sig_data2rsc_valid), - .I1(sig_good_mmap_dbeat7_out__0), - .I2(sig_ld_new_cmd_reg), - .I3(sig_next_calc_error_reg), - .O(sig_push_coelsc_reg)); - (* SOFT_HLUTNM = "soft_lutpair111" *) - LUT3 #( - .INIT(8'hEA)) - sig_coelsc_reg_full_i_3 - (.I0(sig_next_calc_error_reg), - .I1(sig_next_cmd_cmplt_reg), - .I2(m_axi_mm2s_rlast), - .O(sig_cmd_cmplt_last_dbeat)); + \sig_data_reg_out_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[4]), + .Q(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7] [4]), + .R(1'b0)); FDRE #( .INIT(1'b0)) - sig_coelsc_reg_full_reg - (.C(m_axi_mm2s_aclk), - .CE(sig_push_coelsc_reg), - .D(sig_cmd_cmplt_last_dbeat), - .Q(sig_data2rsc_valid), - .R(sig_coelsc_reg_full_i_1_n_0)); - (* SOFT_HLUTNM = "soft_lutpair110" *) - LUT4 #( - .INIT(16'hFF08)) - sig_coelsc_slverr_reg_i_1 - (.I0(m_axi_mm2s_rresp[1]), - .I1(m_axi_mm2s_rvalid), - .I2(m_axi_mm2s_rresp[0]), - .I3(sig_data2rsc_slverr), - .O(sig_coelsc_slverr_reg0)); + \sig_data_reg_out_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[5]), + .Q(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7] [5]), + .R(1'b0)); FDRE #( .INIT(1'b0)) - sig_coelsc_slverr_reg_reg - (.C(m_axi_mm2s_aclk), - .CE(sig_push_coelsc_reg), - .D(sig_coelsc_slverr_reg0), - .Q(sig_data2rsc_slverr), - .R(sig_coelsc_reg_full_i_1_n_0)); - LUT5 #( - .INIT(32'hFFFFFFFE)) - \sig_dbeat_cntr[5]_i_2 - (.I0(sig_dbeat_cntr_reg__0[3]), - .I1(sig_dbeat_cntr_reg__0[1]), - .I2(sig_dbeat_cntr_reg__0[0]), - .I3(sig_dbeat_cntr_reg__0[2]), - .I4(sig_dbeat_cntr_reg__0[4]), - .O(\sig_dbeat_cntr[5]_i_2_n_0 )); - LUT6 #( - .INIT(64'hAAAAAAAAAAAAAAA8)) - \sig_dbeat_cntr[7]_i_3 - (.I0(sig_good_mmap_dbeat7_out__0), - .I1(sig_dbeat_cntr_reg__0[2]), - .I2(sig_dbeat_cntr_reg__0[3]), - .I3(sig_dbeat_cntr_reg__0[0]), - .I4(sig_dbeat_cntr_reg__0[1]), - .I5(\sig_dbeat_cntr[7]_i_5_n_0 ), - .O(\sig_dbeat_cntr[7]_i_3_n_0 )); - LUT6 #( - .INIT(64'hFFFFFFFFFFFFFFFE)) - \sig_dbeat_cntr[7]_i_4 - (.I0(sig_dbeat_cntr_reg__0[4]), - .I1(sig_dbeat_cntr_reg__0[2]), - .I2(sig_dbeat_cntr_reg__0[0]), - .I3(sig_dbeat_cntr_reg__0[1]), - .I4(sig_dbeat_cntr_reg__0[3]), - .I5(sig_dbeat_cntr_reg__0[5]), - .O(\sig_dbeat_cntr[7]_i_4_n_0 )); - LUT4 #( - .INIT(16'hFFFE)) - \sig_dbeat_cntr[7]_i_5 - (.I0(sig_dbeat_cntr_reg__0[7]), - .I1(sig_dbeat_cntr_reg__0[6]), - .I2(sig_dbeat_cntr_reg__0[4]), - .I3(sig_dbeat_cntr_reg__0[5]), - .O(\sig_dbeat_cntr[7]_i_5_n_0 )); + \sig_data_reg_out_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[6]), + .Q(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7] [6]), + .R(1'b0)); FDRE #( .INIT(1'b0)) - \sig_dbeat_cntr_reg[0] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_3 ), - .D(p_0_in[0]), - .Q(sig_dbeat_cntr_reg__0[0]), - .R(SR)); + \sig_data_reg_out_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[7]), + .Q(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7] [7]), + .R(1'b0)); FDRE #( .INIT(1'b0)) - \sig_dbeat_cntr_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_3 ), - .D(p_0_in[1]), - .Q(sig_dbeat_cntr_reg__0[1]), - .R(SR)); + \sig_data_skid_reg_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(DOUT[0]), + .Q(sig_data_skid_reg[0]), + .R(1'b0)); FDRE #( .INIT(1'b0)) - \sig_dbeat_cntr_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_3 ), - .D(p_0_in[2]), - .Q(sig_dbeat_cntr_reg__0[2]), - .R(SR)); + \sig_data_skid_reg_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(DOUT[1]), + .Q(sig_data_skid_reg[1]), + .R(1'b0)); FDRE #( .INIT(1'b0)) - \sig_dbeat_cntr_reg[3] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_3 ), - .D(p_0_in[3]), - .Q(sig_dbeat_cntr_reg__0[3]), - .R(SR)); + \sig_data_skid_reg_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(DOUT[2]), + .Q(sig_data_skid_reg[2]), + .R(1'b0)); FDRE #( .INIT(1'b0)) - \sig_dbeat_cntr_reg[4] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_3 ), - .D(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_7 ), - .Q(sig_dbeat_cntr_reg__0[4]), - .R(SR)); + \sig_data_skid_reg_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(DOUT[3]), + .Q(sig_data_skid_reg[3]), + .R(1'b0)); FDRE #( .INIT(1'b0)) - \sig_dbeat_cntr_reg[5] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_3 ), - .D(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_6 ), - .Q(sig_dbeat_cntr_reg__0[5]), - .R(SR)); + \sig_data_skid_reg_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(DOUT[4]), + .Q(sig_data_skid_reg[4]), + .R(1'b0)); FDRE #( .INIT(1'b0)) - \sig_dbeat_cntr_reg[6] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_3 ), - .D(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_5 ), - .Q(sig_dbeat_cntr_reg__0[6]), - .R(SR)); + \sig_data_skid_reg_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(DOUT[5]), + .Q(sig_data_skid_reg[5]), + .R(1'b0)); FDRE #( .INIT(1'b0)) - \sig_dbeat_cntr_reg[7] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_3 ), - .D(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_4 ), - .Q(sig_dbeat_cntr_reg__0[7]), - .R(SR)); - FDSE #( - .INIT(1'b0)) - sig_dqual_reg_empty_reg - (.C(m_axi_mm2s_aclk), - .CE(sig_push_dqual_reg), - .D(1'b0), - .Q(sig_dqual_reg_empty), - .S(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_19 )); + \sig_data_skid_reg_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(DOUT[6]), + .Q(sig_data_skid_reg[6]), + .R(1'b0)); FDRE #( .INIT(1'b0)) - sig_dqual_reg_full_reg - (.C(m_axi_mm2s_aclk), - .CE(sig_push_dqual_reg), - .D(sig_push_dqual_reg), - .Q(sig_dqual_reg_full), - .R(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_19 )); - LUT5 #( - .INIT(32'hFFFF8880)) - sig_halt_cmplt_i_1 - (.I0(sig_data2rst_stop_cmplt), - .I1(sig_data2addr_stop_req), - .I2(sig_addr2rsc_calc_error), - .I3(sig_addr_reg_empty), - .I4(mm2s_halt_cmplt), - .O(sig_halt_cmplt_reg)); + \sig_data_skid_reg_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(DOUT[7]), + .Q(sig_data_skid_reg[7]), + .R(1'b0)); + LUT4 #( + .INIT(16'h0200)) + sig_dre2ibtt_eop_reg_i_1 + (.I0(sig_strm_tlast), + .I1(Q), + .I2(sig_eop_halt_xfer), + .I3(sig_m_valid_out), + .O(sig_dre2ibtt_eop_reg_reg)); LUT5 #( - .INIT(32'h8888888A)) - sig_halt_cmplt_i_2 - (.I0(sig_halt_reg_dly3), - .I1(sig_next_calc_error_reg), - .I2(sig_addr_posted_cntr[1]), - .I3(sig_addr_posted_cntr[0]), - .I4(sig_addr_posted_cntr[2]), - .O(sig_data2rst_stop_cmplt)); + .INIT(32'hB8FFB800)) + sig_last_reg_out_i_1__1 + (.I0(DOUT[8]), + .I1(sig_s_ready_dup4), + .I2(sig_last_skid_reg), + .I3(E), + .I4(sig_strm_tlast), + .O(sig_last_reg_out_i_1__1_n_0)); FDRE #( .INIT(1'b0)) - sig_halt_reg_dly1_reg - (.C(m_axi_mm2s_aclk), + sig_last_reg_out_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(sig_data2addr_stop_req), - .Q(sig_halt_reg_dly1), - .R(SR)); + .D(sig_last_reg_out_i_1__1_n_0), + .Q(sig_strm_tlast), + .R(sig_stream_rst)); + LUT4 #( + .INIT(16'hE200)) + sig_last_skid_reg_i_1__0 + (.I0(sig_last_skid_reg), + .I1(sig_s_ready_dup), + .I2(DOUT[8]), + .I3(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .O(sig_last_skid_reg_i_1__0_n_0)); FDRE #( .INIT(1'b0)) - sig_halt_reg_dly2_reg - (.C(m_axi_mm2s_aclk), + sig_last_skid_reg_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(sig_halt_reg_dly1), - .Q(sig_halt_reg_dly2), - .R(SR)); + .D(sig_last_skid_reg_i_1__0_n_0), + .Q(sig_last_skid_reg), + .R(1'b0)); + LUT6 #( + .INIT(64'h0404440444044404)) + sig_m_valid_dup_i_1 + (.I0(sig_init_reg), + .I1(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I2(EMPTY), + .I3(sig_m_valid_dup), + .I4(\GEN_INDET_BTT.lsig_absorb2tlast_reg ), + .I5(sig_s_ready_dup), + .O(sig_m_valid_dup_i_1_n_0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) - sig_halt_reg_dly3_reg - (.C(m_axi_mm2s_aclk), + sig_m_valid_dup_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(sig_halt_reg_dly2), - .Q(sig_halt_reg_dly3), - .R(SR)); + .D(sig_m_valid_dup_i_1_n_0), + .Q(sig_m_valid_dup), + .R(1'b0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) - sig_halt_reg_reg - (.C(m_axi_mm2s_aclk), + sig_m_valid_out_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(sig_s_h_halt_reg_reg), - .Q(sig_data2addr_stop_req), - .R(SR)); - LUT5 #( - .INIT(32'h00000010)) - sig_last_dbeat_i_3 - (.I0(\sig_dbeat_cntr[7]_i_5_n_0 ), - .I1(sig_dbeat_cntr_reg__0[1]), - .I2(sig_dbeat_cntr_reg__0[0]), - .I3(sig_dbeat_cntr_reg__0[3]), - .I4(sig_dbeat_cntr_reg__0[2]), - .O(sig_dbeat_cntr_eq_1)); + .D(sig_m_valid_dup_i_1_n_0), + .Q(sig_m_valid_out), + .R(1'b0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) - sig_last_dbeat_reg - (.C(m_axi_mm2s_aclk), + sig_s_ready_dup2_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_18 ), - .Q(sig_last_dbeat), - .R(SR)); - LUT2 #( - .INIT(4'h8)) - sig_last_mmap_dbeat_reg_i_1 - (.I0(m_axi_mm2s_rlast), - .I1(sig_good_mmap_dbeat7_out__0), - .O(sig_last_mmap_dbeat)); + .D(sig_s_ready_dup_i_1__0_n_0), + .Q(sig_s_ready_dup2), + .R(sig_stream_rst)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) - sig_last_mmap_dbeat_reg_reg - (.C(m_axi_mm2s_aclk), + sig_s_ready_dup3_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(sig_last_mmap_dbeat), - .Q(\sig_addr_posted_cntr_reg[2]_0 ), - .R(SR)); + .D(sig_s_ready_dup_i_1__0_n_0), + .Q(sig_s_ready_dup3), + .R(sig_stream_rst)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) - sig_ld_new_cmd_reg_reg - (.C(m_axi_mm2s_aclk), + sig_s_ready_dup4_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_17 ), - .Q(sig_ld_new_cmd_reg), - .R(1'b0)); + .D(sig_s_ready_dup_i_1__0_n_0), + .Q(sig_s_ready_dup4), + .R(sig_stream_rst)); + LUT5 #( + .INIT(32'hFFFFEEAE)) + sig_s_ready_dup_i_1__0 + (.I0(sig_init_reg), + .I1(sig_s_ready_dup), + .I2(sig_m_valid_dup), + .I3(EMPTY), + .I4(\GEN_INDET_BTT.lsig_absorb2tlast_reg ), + .O(sig_s_ready_dup_i_1__0_n_0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) - sig_next_calc_error_reg_reg - (.C(m_axi_mm2s_aclk), - .CE(sig_push_dqual_reg), - .D(sig_cmd_fifo_data_out[35]), - .Q(sig_next_calc_error_reg), - .R(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_19 )); + sig_s_ready_dup_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_s_ready_dup_i_1__0_n_0), + .Q(sig_s_ready_dup), + .R(sig_stream_rst)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) - sig_next_cmd_cmplt_reg_reg - (.C(m_axi_mm2s_aclk), - .CE(sig_push_dqual_reg), - .D(sig_cmd_fifo_data_out[34]), - .Q(sig_next_cmd_cmplt_reg), - .R(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_19 )); + sig_s_ready_out_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_s_ready_dup_i_1__0_n_0), + .Q(sig_s_ready_out), + .R(sig_stream_rst)); + LUT4 #( + .INIT(16'hEFE0)) + \sig_strb_reg_out[0]_i_1 + (.I0(sig_s_ready_dup3), + .I1(sig_strb_skid_reg), + .I2(E), + .I3(sig_dre2ibtt_tstrb), + .O(\sig_strb_reg_out[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) - sig_next_eof_reg_reg - (.C(m_axi_mm2s_aclk), - .CE(sig_push_dqual_reg), - .D(sig_cmd_fifo_data_out[32]), - .Q(sig_next_eof_reg), - .R(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_19 )); + \sig_strb_reg_out_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\sig_strb_reg_out[0]_i_1_n_0 ), + .Q(sig_dre2ibtt_tstrb), + .R(sig_stream_rst)); + LUT3 #( + .INIT(8'hE0)) + \sig_strb_skid_reg[0]_i_1 + (.I0(sig_strb_skid_reg), + .I1(sig_s_ready_dup), + .I2(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .O(\sig_strb_skid_reg[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) - sig_next_sequential_reg_reg - (.C(m_axi_mm2s_aclk), - .CE(sig_push_dqual_reg), - .D(sig_cmd_fifo_data_out[33]), - .Q(sig_next_sequential_reg), - .R(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_19 )); - LUT2 #( - .INIT(4'hE)) - sig_rd_sts_decerr_reg_i_1 - (.I0(sig_data2rsc_decerr), - .I1(sig_rd_sts_decerr_reg_reg), - .O(sig_rd_sts_decerr_reg0)); - (* SOFT_HLUTNM = "soft_lutpair112" *) - LUT2 #( - .INIT(4'h1)) - sig_rd_sts_reg_empty_i_1 - (.I0(sig_data2rsc_valid), - .I1(sig_data2rsc_calc_err), - .O(sig_rd_sts_reg_empty_reg)); - LUT2 #( - .INIT(4'h8)) - sig_rd_sts_reg_full_i_2 - (.I0(sig_data2rsc_valid), - .I1(sig_rsc2data_ready), - .O(sig_push_rd_sts_reg)); - (* SOFT_HLUTNM = "soft_lutpair112" *) - LUT2 #( - .INIT(4'hE)) - sig_rd_sts_reg_full_i_3 - (.I0(sig_data2rsc_calc_err), - .I1(sig_data2rsc_valid), - .O(sig_rd_sts_reg_full0)); + \sig_strb_skid_reg_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\sig_strb_skid_reg[0]_i_1_n_0 ), + .Q(sig_strb_skid_reg), + .R(1'b0)); endmodule -(* ORIG_REF_NAME = "axi_datamover_reset" *) -module Arty_Z7_20_axi_vdma_0_0_axi_datamover_reset - (sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - mm2s_halt_cmplt, +(* ORIG_REF_NAME = "axi_datamover_pcc" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_pcc + (sig_init_reg, + in, + sig_sm_halt_reg, + sig_input_reg_empty, + sig_calc_error_pushed, + sig_mstr2data_sequential, + FIFO_Full_reg, + sig_mstr2sf_cmd_valid, + sig_mstr2data_cmd_valid, + sig_mstr2addr_cmd_valid, + sig_next_cmd_cmplt_reg_reg, SR, - sig_rst2all_stop_request, - sig_halt_reg_reg, - out, m_axi_mm2s_aclk, - sig_halt_reg_reg_0, - halt_i_reg, - sig_data2addr_stop_req); - output sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - output mm2s_halt_cmplt; - output [0:0]SR; - output sig_rst2all_stop_request; - output sig_halt_reg_reg; - input out; + out, + sig_calc_error_reg_reg_0, + Q, + sig_wr_fifo, + sig_wr_fifo_0, + sig_wr_fifo_1, + FIFO_Full_reg_0, + sig_inhibit_rdy_n); + output sig_init_reg; + output [38:0]in; + output sig_sm_halt_reg; + output sig_input_reg_empty; + output sig_calc_error_pushed; + output sig_mstr2data_sequential; + output FIFO_Full_reg; + output sig_mstr2sf_cmd_valid; + output sig_mstr2data_cmd_valid; + output sig_mstr2addr_cmd_valid; + output [1:0]sig_next_cmd_cmplt_reg_reg; + input [0:0]SR; input m_axi_mm2s_aclk; - input sig_halt_reg_reg_0; - input halt_i_reg; - input sig_data2addr_stop_req; + input [49:0]out; + input sig_calc_error_reg_reg_0; + input [0:0]Q; + input sig_wr_fifo; + input sig_wr_fifo_0; + input sig_wr_fifo_1; + input FIFO_Full_reg_0; + input sig_inhibit_rdy_n; + wire FIFO_Full_reg; + wire FIFO_Full_reg_0; + wire \FSM_sequential_sig_pcc_sm_state[0]_i_1_n_0 ; + wire \FSM_sequential_sig_pcc_sm_state[1]_i_1_n_0 ; + wire \FSM_sequential_sig_pcc_sm_state[1]_i_2_n_0 ; + wire \FSM_sequential_sig_pcc_sm_state[2]_i_1_n_0 ; + wire [0:0]Q; wire [0:0]SR; - wire halt_i_reg; + wire [38:0]in; wire m_axi_mm2s_aclk; - wire mm2s_halt_cmplt; - wire out; - wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - wire sig_data2addr_stop_req; - wire sig_halt_reg_reg; - wire sig_halt_reg_reg_0; - wire sig_rst2all_stop_request; - - LUT1 #( - .INIT(2'h1)) - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_4 - (.I0(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .O(SR)); - FDRE #( - .INIT(1'b0)) - sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0 - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(out), - .Q(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - sig_halt_cmplt_reg - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(sig_halt_reg_reg_0), - .Q(mm2s_halt_cmplt), - .R(SR)); - LUT2 #( - .INIT(4'hE)) - sig_halt_reg_i_1 - (.I0(sig_rst2all_stop_request), - .I1(sig_data2addr_stop_req), - .O(sig_halt_reg_reg)); - FDRE #( - .INIT(1'b0)) - sig_s_h_halt_reg_reg - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(halt_i_reg), - .Q(sig_rst2all_stop_request), - .R(SR)); -endmodule - -(* ORIG_REF_NAME = "axi_datamover_sfifo_autord" *) -module Arty_Z7_20_axi_vdma_0_0_axi_datamover_sfifo_autord - (out, - \sig_user_skid_reg_reg[0] , - dm2linebuf_mm2s_tvalid, - DI, - Q, - dm2linebuf_mm2s_tdata, - sig_ok_to_post_rd_addr_reg, - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , - \INCLUDE_UNPACKING.lsig_cmd_loaded_reg , - \INFERRED_GEN.cnt_i_reg[0] , - S, - \count_reg[6] , - m_axi_mm2s_aclk, - sig_stream_rst, - m_axi_mm2s_rdata, - DIBDI, - lsig_0ffset_cntr, - lsig_cmd_loaded, - \sig_token_cntr_reg[3] , - p_8_out, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_posted_to_axi_2_reg, - sig_posted_to_axi_2_reg_0, - p_0_out, - \INFERRED_GEN.cnt_i_reg[2] , - fifo_wren__0, - mm2s_strm_wvalid0__1, - m_axi_mm2s_rvalid, - sig_advance_pipe9_out__1, - D); - output out; - output [0:0]\sig_user_skid_reg_reg[0] ; - output dm2linebuf_mm2s_tvalid; - output [3:0]DI; - output [1:0]Q; - output [31:0]dm2linebuf_mm2s_tdata; - output sig_ok_to_post_rd_addr_reg; - output \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; - output \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; - output \INFERRED_GEN.cnt_i_reg[0] ; - output [3:0]S; - output [1:0]\count_reg[6] ; - input m_axi_mm2s_aclk; - input sig_stream_rst; - input [63:0]m_axi_mm2s_rdata; - input [1:0]DIBDI; - input lsig_0ffset_cntr; - input lsig_cmd_loaded; - input [3:0]\sig_token_cntr_reg[3] ; - input p_8_out; - input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - input sig_posted_to_axi_2_reg; - input sig_posted_to_axi_2_reg_0; - input [0:0]p_0_out; - input [0:0]\INFERRED_GEN.cnt_i_reg[2] ; - input fifo_wren__0; - input mm2s_strm_wvalid0__1; - input m_axi_mm2s_rvalid; - input sig_advance_pipe9_out__1; - input [5:0]D; - - wire \BLK_MEM.I_SYNC_FIFOGEN_FIFO_n_41 ; - wire [5:0]D; - wire [3:0]DI; - wire [1:0]DIBDI; - wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; - wire \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; - wire \INFERRED_GEN.cnt_i_reg[0] ; - wire [0:0]\INFERRED_GEN.cnt_i_reg[2] ; - wire [1:0]Q; - wire [3:0]S; - wire [1:0]\count_reg[6] ; - wire [31:0]dm2linebuf_mm2s_tdata; - wire dm2linebuf_mm2s_tvalid; - wire fifo_wren__0; - wire hold_ff_q; - wire lsig_0ffset_cntr; - wire lsig_cmd_loaded; - wire m_axi_mm2s_aclk; - wire [63:0]m_axi_mm2s_rdata; - wire m_axi_mm2s_rvalid; - wire mm2s_strm_wvalid0__1; - wire out; - wire [0:0]p_0_out; - wire p_8_out; - wire sig_advance_pipe9_out__1; - wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - wire sig_ok_to_post_rd_addr_reg; - wire sig_posted_to_axi_2_reg; - wire sig_posted_to_axi_2_reg_0; - wire sig_stream_rst; - wire [3:0]\sig_token_cntr_reg[3] ; - wire [0:0]\sig_user_skid_reg_reg[0] ; + wire [49:0]out; + wire [15:0]p_1_in; + wire p_1_in_0; + wire [7:0]sel0; + wire sig_addr_aligned_im0; + wire sig_addr_aligned_ireg1; + wire \sig_addr_cntr_im0_msh[0]_i_1_n_0 ; + wire \sig_addr_cntr_im0_msh[0]_i_3_n_0 ; + wire \sig_addr_cntr_im0_msh[0]_i_4_n_0 ; + wire \sig_addr_cntr_im0_msh[0]_i_5_n_0 ; + wire \sig_addr_cntr_im0_msh[0]_i_6_n_0 ; + wire \sig_addr_cntr_im0_msh[0]_i_7_n_0 ; + wire \sig_addr_cntr_im0_msh[12]_i_2_n_0 ; + wire \sig_addr_cntr_im0_msh[12]_i_3_n_0 ; + wire \sig_addr_cntr_im0_msh[12]_i_4_n_0 ; + wire \sig_addr_cntr_im0_msh[12]_i_5_n_0 ; + wire \sig_addr_cntr_im0_msh[4]_i_2_n_0 ; + wire \sig_addr_cntr_im0_msh[4]_i_3_n_0 ; + wire \sig_addr_cntr_im0_msh[4]_i_4_n_0 ; + wire \sig_addr_cntr_im0_msh[4]_i_5_n_0 ; + wire \sig_addr_cntr_im0_msh[8]_i_2_n_0 ; + wire \sig_addr_cntr_im0_msh[8]_i_3_n_0 ; + wire \sig_addr_cntr_im0_msh[8]_i_4_n_0 ; + wire \sig_addr_cntr_im0_msh[8]_i_5_n_0 ; + wire [15:0]sig_addr_cntr_im0_msh_reg; + wire \sig_addr_cntr_im0_msh_reg[0]_i_2_n_0 ; + wire \sig_addr_cntr_im0_msh_reg[0]_i_2_n_1 ; + wire \sig_addr_cntr_im0_msh_reg[0]_i_2_n_2 ; + wire \sig_addr_cntr_im0_msh_reg[0]_i_2_n_3 ; + wire \sig_addr_cntr_im0_msh_reg[0]_i_2_n_4 ; + wire \sig_addr_cntr_im0_msh_reg[0]_i_2_n_5 ; + wire \sig_addr_cntr_im0_msh_reg[0]_i_2_n_6 ; + wire \sig_addr_cntr_im0_msh_reg[0]_i_2_n_7 ; + wire \sig_addr_cntr_im0_msh_reg[12]_i_1_n_1 ; + wire \sig_addr_cntr_im0_msh_reg[12]_i_1_n_2 ; + wire \sig_addr_cntr_im0_msh_reg[12]_i_1_n_3 ; + wire \sig_addr_cntr_im0_msh_reg[12]_i_1_n_4 ; + wire \sig_addr_cntr_im0_msh_reg[12]_i_1_n_5 ; + wire \sig_addr_cntr_im0_msh_reg[12]_i_1_n_6 ; + wire \sig_addr_cntr_im0_msh_reg[12]_i_1_n_7 ; + wire \sig_addr_cntr_im0_msh_reg[4]_i_1_n_0 ; + wire \sig_addr_cntr_im0_msh_reg[4]_i_1_n_1 ; + wire \sig_addr_cntr_im0_msh_reg[4]_i_1_n_2 ; + wire \sig_addr_cntr_im0_msh_reg[4]_i_1_n_3 ; + wire \sig_addr_cntr_im0_msh_reg[4]_i_1_n_4 ; + wire \sig_addr_cntr_im0_msh_reg[4]_i_1_n_5 ; + wire \sig_addr_cntr_im0_msh_reg[4]_i_1_n_6 ; + wire \sig_addr_cntr_im0_msh_reg[4]_i_1_n_7 ; + wire \sig_addr_cntr_im0_msh_reg[8]_i_1_n_0 ; + wire \sig_addr_cntr_im0_msh_reg[8]_i_1_n_1 ; + wire \sig_addr_cntr_im0_msh_reg[8]_i_1_n_2 ; + wire \sig_addr_cntr_im0_msh_reg[8]_i_1_n_3 ; + wire \sig_addr_cntr_im0_msh_reg[8]_i_1_n_4 ; + wire \sig_addr_cntr_im0_msh_reg[8]_i_1_n_5 ; + wire \sig_addr_cntr_im0_msh_reg[8]_i_1_n_6 ; + wire \sig_addr_cntr_im0_msh_reg[8]_i_1_n_7 ; + wire [8:0]sig_addr_cntr_incr_ireg2; + wire \sig_addr_cntr_incr_ireg2[0]_i_1_n_0 ; + wire \sig_addr_cntr_incr_ireg2[1]_i_1_n_0 ; + wire \sig_addr_cntr_incr_ireg2[2]_i_1_n_0 ; + wire \sig_addr_cntr_incr_ireg2[3]_i_1_n_0 ; + wire \sig_addr_cntr_incr_ireg2[4]_i_1_n_0 ; + wire \sig_addr_cntr_incr_ireg2[5]_i_1_n_0 ; + wire \sig_addr_cntr_incr_ireg2[6]_i_1_n_0 ; + wire \sig_addr_cntr_incr_ireg2[7]_i_1_n_0 ; + wire \sig_addr_cntr_incr_ireg2[8]_i_1_n_0 ; + wire \sig_addr_cntr_lsh_im0[15]_i_1_n_0 ; + wire \sig_addr_cntr_lsh_im0_reg_n_0_[0] ; + wire \sig_addr_cntr_lsh_im0_reg_n_0_[10] ; + wire \sig_addr_cntr_lsh_im0_reg_n_0_[11] ; + wire \sig_addr_cntr_lsh_im0_reg_n_0_[12] ; + wire \sig_addr_cntr_lsh_im0_reg_n_0_[13] ; + wire \sig_addr_cntr_lsh_im0_reg_n_0_[14] ; + wire \sig_addr_cntr_lsh_im0_reg_n_0_[1] ; + wire \sig_addr_cntr_lsh_im0_reg_n_0_[2] ; + wire \sig_addr_cntr_lsh_im0_reg_n_0_[3] ; + wire \sig_addr_cntr_lsh_im0_reg_n_0_[4] ; + wire \sig_addr_cntr_lsh_im0_reg_n_0_[5] ; + wire \sig_addr_cntr_lsh_im0_reg_n_0_[6] ; + wire \sig_addr_cntr_lsh_im0_reg_n_0_[7] ; + wire \sig_addr_cntr_lsh_im0_reg_n_0_[8] ; + wire \sig_addr_cntr_lsh_im0_reg_n_0_[9] ; + wire [31:0]sig_addr_cntr_lsh_kh; + wire [7:0]sig_adjusted_addr_incr_im1; + wire \sig_adjusted_addr_incr_ireg2[3]_i_2_n_0 ; + wire \sig_adjusted_addr_incr_ireg2[3]_i_3_n_0 ; + wire \sig_adjusted_addr_incr_ireg2[3]_i_4_n_0 ; + wire \sig_adjusted_addr_incr_ireg2[3]_i_5_n_0 ; + wire \sig_adjusted_addr_incr_ireg2[7]_i_2_n_0 ; + wire \sig_adjusted_addr_incr_ireg2[7]_i_3_n_0 ; + wire \sig_adjusted_addr_incr_ireg2[7]_i_4_n_0 ; + wire \sig_adjusted_addr_incr_ireg2[7]_i_5_n_0 ; + wire \sig_adjusted_addr_incr_ireg2_reg[3]_i_1_n_0 ; + wire \sig_adjusted_addr_incr_ireg2_reg[3]_i_1_n_1 ; + wire \sig_adjusted_addr_incr_ireg2_reg[3]_i_1_n_2 ; + wire \sig_adjusted_addr_incr_ireg2_reg[3]_i_1_n_3 ; + wire \sig_adjusted_addr_incr_ireg2_reg[7]_i_1_n_1 ; + wire \sig_adjusted_addr_incr_ireg2_reg[7]_i_1_n_2 ; + wire \sig_adjusted_addr_incr_ireg2_reg[7]_i_1_n_3 ; + wire \sig_adjusted_addr_incr_ireg2_reg_n_0_[0] ; + wire \sig_adjusted_addr_incr_ireg2_reg_n_0_[1] ; + wire \sig_adjusted_addr_incr_ireg2_reg_n_0_[2] ; + wire \sig_adjusted_addr_incr_ireg2_reg_n_0_[3] ; + wire \sig_adjusted_addr_incr_ireg2_reg_n_0_[4] ; + wire \sig_adjusted_addr_incr_ireg2_reg_n_0_[5] ; + wire \sig_adjusted_addr_incr_ireg2_reg_n_0_[6] ; + wire \sig_adjusted_addr_incr_ireg2_reg_n_0_[7] ; + wire sig_brst_cnt_eq_one_im0; + wire sig_brst_cnt_eq_one_ireg1; + wire sig_brst_cnt_eq_zero_im0; + wire sig_brst_cnt_eq_zero_ireg1; + wire [15:0]sig_btt_cntr_im00; + wire sig_btt_cntr_im00_carry__0_i_1_n_0; + wire sig_btt_cntr_im00_carry__0_i_2_n_0; + wire sig_btt_cntr_im00_carry__0_i_3_n_0; + wire sig_btt_cntr_im00_carry__0_i_4_n_0; + wire sig_btt_cntr_im00_carry__0_n_0; + wire sig_btt_cntr_im00_carry__0_n_1; + wire sig_btt_cntr_im00_carry__0_n_2; + wire sig_btt_cntr_im00_carry__0_n_3; + wire sig_btt_cntr_im00_carry__1_i_1_n_0; + wire sig_btt_cntr_im00_carry__1_i_2_n_0; + wire sig_btt_cntr_im00_carry__1_i_3_n_0; + wire sig_btt_cntr_im00_carry__1_i_4_n_0; + wire sig_btt_cntr_im00_carry__1_n_0; + wire sig_btt_cntr_im00_carry__1_n_1; + wire sig_btt_cntr_im00_carry__1_n_2; + wire sig_btt_cntr_im00_carry__1_n_3; + wire sig_btt_cntr_im00_carry__2_i_1_n_0; + wire sig_btt_cntr_im00_carry__2_i_2_n_0; + wire sig_btt_cntr_im00_carry__2_i_3_n_0; + wire sig_btt_cntr_im00_carry__2_i_4_n_0; + wire sig_btt_cntr_im00_carry__2_n_1; + wire sig_btt_cntr_im00_carry__2_n_2; + wire sig_btt_cntr_im00_carry__2_n_3; + wire sig_btt_cntr_im00_carry_i_1_n_0; + wire sig_btt_cntr_im00_carry_i_2_n_0; + wire sig_btt_cntr_im00_carry_i_3_n_0; + wire sig_btt_cntr_im00_carry_i_4_n_0; + wire sig_btt_cntr_im00_carry_n_0; + wire sig_btt_cntr_im00_carry_n_1; + wire sig_btt_cntr_im00_carry_n_2; + wire sig_btt_cntr_im00_carry_n_3; + wire \sig_btt_cntr_im0[0]_i_1_n_0 ; + wire \sig_btt_cntr_im0[10]_i_1_n_0 ; + wire \sig_btt_cntr_im0[11]_i_1_n_0 ; + wire \sig_btt_cntr_im0[12]_i_1_n_0 ; + wire \sig_btt_cntr_im0[13]_i_1_n_0 ; + wire \sig_btt_cntr_im0[14]_i_1_n_0 ; + wire \sig_btt_cntr_im0[15]_i_1_n_0 ; + wire \sig_btt_cntr_im0[1]_i_1_n_0 ; + wire \sig_btt_cntr_im0[2]_i_1_n_0 ; + wire \sig_btt_cntr_im0[3]_i_1_n_0 ; + wire \sig_btt_cntr_im0[4]_i_1_n_0 ; + wire \sig_btt_cntr_im0[5]_i_1_n_0 ; + wire \sig_btt_cntr_im0[6]_i_1_n_0 ; + wire \sig_btt_cntr_im0[7]_i_1_n_0 ; + wire \sig_btt_cntr_im0[8]_i_1_n_0 ; + wire \sig_btt_cntr_im0[9]_i_1_n_0 ; + wire sig_btt_eq_b2mbaa_im0; + wire sig_btt_eq_b2mbaa_im01; + wire sig_btt_eq_b2mbaa_im01_carry_i_1_n_0; + wire sig_btt_eq_b2mbaa_im01_carry_i_2_n_0; + wire sig_btt_eq_b2mbaa_im01_carry_i_3_n_0; + wire sig_btt_eq_b2mbaa_im01_carry_i_4_n_0; + wire sig_btt_eq_b2mbaa_im01_carry_n_2; + wire sig_btt_eq_b2mbaa_im01_carry_n_3; + wire sig_btt_eq_b2mbaa_ireg1; + wire sig_btt_lt_b2mbaa_im0; + wire sig_btt_lt_b2mbaa_im01; + wire sig_btt_lt_b2mbaa_im01_carry__0_i_1_n_0; + wire sig_btt_lt_b2mbaa_im01_carry__0_i_2_n_0; + wire sig_btt_lt_b2mbaa_im01_carry_i_1_n_0; + wire sig_btt_lt_b2mbaa_im01_carry_i_2_n_0; + wire sig_btt_lt_b2mbaa_im01_carry_i_3_n_0; + wire sig_btt_lt_b2mbaa_im01_carry_i_4_n_0; + wire sig_btt_lt_b2mbaa_im01_carry_i_5_n_0; + wire sig_btt_lt_b2mbaa_im01_carry_i_6_n_0; + wire sig_btt_lt_b2mbaa_im01_carry_i_7_n_0; + wire sig_btt_lt_b2mbaa_im01_carry_i_8_n_0; + wire sig_btt_lt_b2mbaa_im01_carry_i_9_n_0; + wire sig_btt_lt_b2mbaa_im01_carry_n_0; + wire sig_btt_lt_b2mbaa_im01_carry_n_1; + wire sig_btt_lt_b2mbaa_im01_carry_n_2; + wire sig_btt_lt_b2mbaa_im01_carry_n_3; + wire sig_btt_lt_b2mbaa_ireg1; + wire sig_btt_lt_b2mbaa_ireg1_i_2_n_0; + wire [7:0]sig_btt_residue_slice_im0; + wire \sig_byte_change_minus1_im2/i__n_0 ; + wire [7:0]sig_bytes_to_mbaa_ireg1; + wire \sig_bytes_to_mbaa_ireg1[1]_i_1_n_0 ; + wire \sig_bytes_to_mbaa_ireg1[2]_i_1_n_0 ; + wire \sig_bytes_to_mbaa_ireg1[3]_i_1_n_0 ; + wire \sig_bytes_to_mbaa_ireg1[4]_i_1_n_0 ; + wire \sig_bytes_to_mbaa_ireg1[5]_i_1_n_0 ; + wire \sig_bytes_to_mbaa_ireg1[6]_i_1_n_0 ; + wire \sig_bytes_to_mbaa_ireg1[7]_i_1_n_0 ; + wire \sig_bytes_to_mbaa_ireg1[7]_i_2_n_0 ; + wire sig_calc_error_pushed; + wire sig_calc_error_pushed_i_1_n_0; + wire sig_calc_error_reg0; + wire sig_calc_error_reg_reg_0; + wire sig_cmd2addr_valid_i_1_n_0; + wire sig_cmd2data_valid_i_1_n_0; + wire sig_cmd2dre_valid_i_1_n_0; + wire sig_first_xfer_im0; + wire sig_first_xfer_im0_i_1_n_0; + wire sig_inhibit_rdy_n; + wire sig_init_reg; + wire sig_input_cache_type_reg0; + wire sig_input_reg_empty; + wire sig_input_reg_empty_i_1_n_0; + wire sig_ld_xfer_reg; + wire sig_ld_xfer_reg_i_1_n_0; + wire sig_ld_xfer_reg_tmp; + wire sig_ld_xfer_reg_tmp_i_1_n_0; + wire sig_mstr2addr_cmd_valid; + wire sig_mstr2data_cmd_valid; + wire sig_mstr2data_sequential; + wire sig_mstr2sf_cmd_valid; + wire sig_mstr2sf_eof; + wire [1:0]sig_next_cmd_cmplt_reg_reg; + wire sig_no_btt_residue_im0; + wire sig_no_btt_residue_ireg1; + wire sig_no_btt_residue_ireg1_i_2_n_0; + wire sig_parent_done; + wire sig_parent_done_i_1_n_0; + (* RTL_KEEP = "yes" *) wire [2:0]sig_pcc_sm_state; + wire sig_pop_xfer_reg0_out; + wire [15:0]sig_predict_addr_lsh_im2; + wire [15:15]sig_predict_addr_lsh_ireg3; + wire \sig_predict_addr_lsh_ireg3[11]_i_2_n_0 ; + wire \sig_predict_addr_lsh_ireg3[11]_i_3_n_0 ; + wire \sig_predict_addr_lsh_ireg3[11]_i_4_n_0 ; + wire \sig_predict_addr_lsh_ireg3[11]_i_5_n_0 ; + wire \sig_predict_addr_lsh_ireg3[15]_i_2_n_0 ; + wire \sig_predict_addr_lsh_ireg3[15]_i_3_n_0 ; + wire \sig_predict_addr_lsh_ireg3[15]_i_4_n_0 ; + wire \sig_predict_addr_lsh_ireg3[15]_i_5_n_0 ; + wire \sig_predict_addr_lsh_ireg3[3]_i_2_n_0 ; + wire \sig_predict_addr_lsh_ireg3[3]_i_3_n_0 ; + wire \sig_predict_addr_lsh_ireg3[3]_i_4_n_0 ; + wire \sig_predict_addr_lsh_ireg3[3]_i_5_n_0 ; + wire \sig_predict_addr_lsh_ireg3[7]_i_2_n_0 ; + wire \sig_predict_addr_lsh_ireg3[7]_i_3_n_0 ; + wire \sig_predict_addr_lsh_ireg3[7]_i_4_n_0 ; + wire \sig_predict_addr_lsh_ireg3[7]_i_5_n_0 ; + wire \sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_0 ; + wire \sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_1 ; + wire \sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_2 ; + wire \sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_3 ; + wire \sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_1 ; + wire \sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_2 ; + wire \sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_3 ; + wire \sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_0 ; + wire \sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_1 ; + wire \sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_2 ; + wire \sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_3 ; + wire \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_0 ; + wire \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_1 ; + wire \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_2 ; + wire \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_3 ; + wire \sig_predict_addr_lsh_ireg3_reg_n_0_[0] ; + wire \sig_predict_addr_lsh_ireg3_reg_n_0_[10] ; + wire \sig_predict_addr_lsh_ireg3_reg_n_0_[11] ; + wire \sig_predict_addr_lsh_ireg3_reg_n_0_[12] ; + wire \sig_predict_addr_lsh_ireg3_reg_n_0_[13] ; + wire \sig_predict_addr_lsh_ireg3_reg_n_0_[14] ; + wire \sig_predict_addr_lsh_ireg3_reg_n_0_[1] ; + wire \sig_predict_addr_lsh_ireg3_reg_n_0_[2] ; + wire \sig_predict_addr_lsh_ireg3_reg_n_0_[3] ; + wire \sig_predict_addr_lsh_ireg3_reg_n_0_[4] ; + wire \sig_predict_addr_lsh_ireg3_reg_n_0_[5] ; + wire \sig_predict_addr_lsh_ireg3_reg_n_0_[6] ; + wire \sig_predict_addr_lsh_ireg3_reg_n_0_[7] ; + wire \sig_predict_addr_lsh_ireg3_reg_n_0_[8] ; + wire \sig_predict_addr_lsh_ireg3_reg_n_0_[9] ; + wire sig_sm_halt_ns; + wire sig_sm_halt_reg; + wire sig_sm_ld_calc1_reg; + wire sig_sm_ld_calc1_reg_ns; + wire sig_sm_ld_calc1_reg_ns0_out; + wire sig_sm_ld_calc2_reg; + wire sig_sm_ld_calc2_reg_ns; + wire sig_sm_ld_calc3_reg; + wire sig_sm_ld_calc3_reg_ns; + wire sig_sm_ld_xfer_reg_ns; + wire sig_sm_pop_input_reg; + wire sig_sm_pop_input_reg_ns; + wire sig_wr_fifo; + wire sig_wr_fifo_0; + wire sig_wr_fifo_1; + wire sig_xfer_reg_empty; + wire sig_xfer_reg_empty_i_1_n_0; + wire [3:3]\NLW_sig_addr_cntr_im0_msh_reg[12]_i_1_CO_UNCONNECTED ; + wire [3:3]\NLW_sig_adjusted_addr_incr_ireg2_reg[7]_i_1_CO_UNCONNECTED ; + wire [3:3]NLW_sig_btt_cntr_im00_carry__2_CO_UNCONNECTED; + wire [3:3]NLW_sig_btt_eq_b2mbaa_im01_carry_CO_UNCONNECTED; + wire [3:0]NLW_sig_btt_eq_b2mbaa_im01_carry_O_UNCONNECTED; + wire [3:0]NLW_sig_btt_lt_b2mbaa_im01_carry_O_UNCONNECTED; + wire [3:1]NLW_sig_btt_lt_b2mbaa_im01_carry__0_CO_UNCONNECTED; + wire [3:0]NLW_sig_btt_lt_b2mbaa_im01_carry__0_O_UNCONNECTED; + wire [3:3]\NLW_sig_predict_addr_lsh_ireg3_reg[15]_i_1_CO_UNCONNECTED ; - Arty_Z7_20_axi_vdma_0_0_sync_fifo_fg \BLK_MEM.I_SYNC_FIFOGEN_FIFO - (.D(D), - .DI(DI), - .DIBDI(DIBDI), - .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), - .\INCLUDE_UNPACKING.lsig_cmd_loaded_reg (\INCLUDE_UNPACKING.lsig_cmd_loaded_reg ), - .\INFERRED_GEN.cnt_i_reg[0] (\INFERRED_GEN.cnt_i_reg[0] ), - .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ), - .Q(Q), - .S(S), - .\count_reg[6] (\count_reg[6] ), - .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), - .dm2linebuf_mm2s_tvalid(dm2linebuf_mm2s_tvalid), - .fifo_wren__0(fifo_wren__0), - .hold_ff_q(hold_ff_q), - .hold_ff_q_reg(\BLK_MEM.I_SYNC_FIFOGEN_FIFO_n_41 ), - .lsig_0ffset_cntr(lsig_0ffset_cntr), - .lsig_cmd_loaded(lsig_cmd_loaded), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axi_mm2s_rdata(m_axi_mm2s_rdata), - .m_axi_mm2s_rvalid(m_axi_mm2s_rvalid), - .mm2s_strm_wvalid0__1(mm2s_strm_wvalid0__1), - .out(out), - .p_0_out(p_0_out), - .p_8_out(p_8_out), - .sig_advance_pipe9_out__1(sig_advance_pipe9_out__1), - .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .sig_ok_to_post_rd_addr_reg(sig_ok_to_post_rd_addr_reg), - .sig_posted_to_axi_2_reg(sig_posted_to_axi_2_reg), - .sig_posted_to_axi_2_reg_0(sig_posted_to_axi_2_reg_0), - .sig_stream_rst(sig_stream_rst), - .\sig_token_cntr_reg[3] (\sig_token_cntr_reg[3] ), - .\sig_user_skid_reg_reg[0] (\sig_user_skid_reg_reg[0] )); - FDRE #( - .INIT(1'b0)) - hold_ff_q_reg + LUT6 #( + .INIT(64'hDD3F00FFDD3F33FF)) + \FSM_sequential_sig_pcc_sm_state[0]_i_1 + (.I0(sig_pop_xfer_reg0_out), + .I1(sig_pcc_sm_state[1]), + .I2(sig_sm_ld_calc1_reg_ns0_out), + .I3(sig_pcc_sm_state[0]), + .I4(sig_pcc_sm_state[2]), + .I5(sig_calc_error_reg0), + .O(\FSM_sequential_sig_pcc_sm_state[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair138" *) + LUT2 #( + .INIT(4'h1)) + \FSM_sequential_sig_pcc_sm_state[0]_i_2 + (.I0(sig_parent_done), + .I1(sig_calc_error_pushed), + .O(sig_sm_ld_calc1_reg_ns0_out)); + LUT6 #( + .INIT(64'hA8A0A8A00AA000A0)) + \FSM_sequential_sig_pcc_sm_state[1]_i_1 + (.I0(\FSM_sequential_sig_pcc_sm_state[1]_i_2_n_0 ), + .I1(sig_pop_xfer_reg0_out), + .I2(sig_pcc_sm_state[1]), + .I3(sig_pcc_sm_state[0]), + .I4(sig_calc_error_reg0), + .I5(sig_pcc_sm_state[2]), + .O(\FSM_sequential_sig_pcc_sm_state[1]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFFF7)) + \FSM_sequential_sig_pcc_sm_state[1]_i_2 + (.I0(sig_pcc_sm_state[2]), + .I1(sig_parent_done), + .I2(sig_calc_error_pushed), + .I3(sig_pcc_sm_state[0]), + .O(\FSM_sequential_sig_pcc_sm_state[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'hDD0DDD0D0000DD0C)) + \FSM_sequential_sig_pcc_sm_state[1]_i_3 + (.I0(sig_mstr2sf_cmd_valid), + .I1(sig_wr_fifo), + .I2(sig_mstr2data_cmd_valid), + .I3(sig_wr_fifo_0), + .I4(sig_mstr2addr_cmd_valid), + .I5(sig_wr_fifo_1), + .O(sig_pop_xfer_reg0_out)); + LUT4 #( + .INIT(16'hECAA)) + \FSM_sequential_sig_pcc_sm_state[2]_i_1 + (.I0(sig_pcc_sm_state[2]), + .I1(sig_pcc_sm_state[0]), + .I2(sig_calc_error_pushed), + .I3(sig_pcc_sm_state[1]), + .O(\FSM_sequential_sig_pcc_sm_state[2]_i_1_n_0 )); + (* KEEP = "yes" *) + FDRE \FSM_sequential_sig_pcc_sm_state_reg[0] (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(\BLK_MEM.I_SYNC_FIFOGEN_FIFO_n_41 ), - .Q(hold_ff_q), - .R(1'b0)); -endmodule - -(* C_DLYTMR_RESOLUTION = "125" *) (* C_DYNAMIC_RESOLUTION = "1" *) (* C_ENABLE_DEBUG_ALL = "0" *) -(* C_ENABLE_DEBUG_INFO_0 = "0" *) (* C_ENABLE_DEBUG_INFO_1 = "0" *) (* C_ENABLE_DEBUG_INFO_10 = "0" *) -(* C_ENABLE_DEBUG_INFO_11 = "0" *) (* C_ENABLE_DEBUG_INFO_12 = "0" *) (* C_ENABLE_DEBUG_INFO_13 = "0" *) -(* C_ENABLE_DEBUG_INFO_14 = "1" *) (* C_ENABLE_DEBUG_INFO_15 = "1" *) (* C_ENABLE_DEBUG_INFO_2 = "0" *) -(* C_ENABLE_DEBUG_INFO_3 = "0" *) (* C_ENABLE_DEBUG_INFO_4 = "0" *) (* C_ENABLE_DEBUG_INFO_5 = "0" *) -(* C_ENABLE_DEBUG_INFO_6 = "1" *) (* C_ENABLE_DEBUG_INFO_7 = "1" *) (* C_ENABLE_DEBUG_INFO_8 = "0" *) -(* C_ENABLE_DEBUG_INFO_9 = "0" *) (* C_ENABLE_VIDPRMTR_READS = "1" *) (* C_FAMILY = "zynq" *) -(* C_FLUSH_ON_FSYNC = "1" *) (* C_INCLUDE_INTERNAL_GENLOCK = "1" *) (* C_INCLUDE_MM2S = "1" *) -(* C_INCLUDE_MM2S_DRE = "0" *) (* C_INCLUDE_MM2S_SF = "0" *) (* C_INCLUDE_S2MM = "0" *) -(* C_INCLUDE_S2MM_DRE = "0" *) (* C_INCLUDE_S2MM_SF = "1" *) (* C_INCLUDE_SG = "0" *) -(* C_INSTANCE = "axi_vdma" *) (* C_MM2S_GENLOCK_MODE = "0" *) (* C_MM2S_GENLOCK_NUM_MASTERS = "1" *) -(* C_MM2S_GENLOCK_REPEAT_EN = "0" *) (* C_MM2S_LINEBUFFER_DEPTH = "4096" *) (* C_MM2S_LINEBUFFER_THRESH = "4" *) -(* C_MM2S_MAX_BURST_LENGTH = "16" *) (* C_MM2S_SOF_ENABLE = "1" *) (* C_M_AXIS_MM2S_TDATA_WIDTH = "32" *) -(* C_M_AXIS_MM2S_TUSER_BITS = "1" *) (* C_M_AXI_MM2S_ADDR_WIDTH = "32" *) (* C_M_AXI_MM2S_DATA_WIDTH = "64" *) -(* C_M_AXI_S2MM_ADDR_WIDTH = "32" *) (* C_M_AXI_S2MM_DATA_WIDTH = "64" *) (* C_M_AXI_SG_ADDR_WIDTH = "32" *) -(* C_M_AXI_SG_DATA_WIDTH = "32" *) (* C_NUM_FSTORES = "1" *) (* C_PRMRY_IS_ACLK_ASYNC = "1" *) -(* C_S2MM_GENLOCK_MODE = "0" *) (* C_S2MM_GENLOCK_NUM_MASTERS = "1" *) (* C_S2MM_GENLOCK_REPEAT_EN = "1" *) -(* C_S2MM_LINEBUFFER_DEPTH = "512" *) (* C_S2MM_LINEBUFFER_THRESH = "4" *) (* C_S2MM_MAX_BURST_LENGTH = "8" *) -(* C_S2MM_SOF_ENABLE = "1" *) (* C_SELECT_XPM = "0" *) (* C_S_AXIS_S2MM_TDATA_WIDTH = "32" *) -(* C_S_AXIS_S2MM_TUSER_BITS = "1" *) (* C_S_AXI_LITE_ADDR_WIDTH = "9" *) (* C_S_AXI_LITE_DATA_WIDTH = "32" *) -(* C_USE_FSYNC = "1" *) (* C_USE_MM2S_FSYNC = "0" *) (* C_USE_S2MM_FSYNC = "2" *) -(* ORIG_REF_NAME = "axi_vdma" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_group = "LOGICORE" *) -(* iptype = "PERIPHERAL" *) (* run_ngcbuild = "TRUE" *) -module Arty_Z7_20_axi_vdma_0_0_axi_vdma - (s_axi_lite_aclk, - m_axi_sg_aclk, - m_axi_mm2s_aclk, - m_axis_mm2s_aclk, - m_axi_s2mm_aclk, - s_axis_s2mm_aclk, - axi_resetn, - s_axi_lite_awvalid, - s_axi_lite_awready, - s_axi_lite_awaddr, - s_axi_lite_wvalid, - s_axi_lite_wready, - s_axi_lite_wdata, - s_axi_lite_bresp, - s_axi_lite_bvalid, - s_axi_lite_bready, - s_axi_lite_arvalid, - s_axi_lite_arready, - s_axi_lite_araddr, - s_axi_lite_rvalid, - s_axi_lite_rready, - s_axi_lite_rdata, - s_axi_lite_rresp, - mm2s_fsync, - mm2s_frame_ptr_in, - mm2s_frame_ptr_out, - s2mm_fsync, - s2mm_frame_ptr_in, - s2mm_frame_ptr_out, - mm2s_buffer_empty, - mm2s_buffer_almost_empty, - s2mm_buffer_full, - s2mm_buffer_almost_full, - mm2s_fsync_out, - s2mm_fsync_out, - mm2s_prmtr_update, - s2mm_prmtr_update, - m_axi_sg_araddr, - m_axi_sg_arlen, - m_axi_sg_arsize, - m_axi_sg_arburst, - m_axi_sg_arprot, - m_axi_sg_arcache, - m_axi_sg_arvalid, - m_axi_sg_arready, - m_axi_sg_rdata, - m_axi_sg_rresp, - m_axi_sg_rlast, - m_axi_sg_rvalid, - m_axi_sg_rready, - m_axi_mm2s_araddr, - m_axi_mm2s_arlen, - m_axi_mm2s_arsize, - m_axi_mm2s_arburst, - m_axi_mm2s_arprot, - m_axi_mm2s_arcache, - m_axi_mm2s_arvalid, - m_axi_mm2s_arready, - m_axi_mm2s_rdata, - m_axi_mm2s_rresp, - m_axi_mm2s_rlast, - m_axi_mm2s_rvalid, - m_axi_mm2s_rready, - mm2s_prmry_reset_out_n, - m_axis_mm2s_tdata, - m_axis_mm2s_tkeep, - m_axis_mm2s_tuser, - m_axis_mm2s_tvalid, - m_axis_mm2s_tready, - m_axis_mm2s_tlast, - m_axi_s2mm_awaddr, - m_axi_s2mm_awlen, - m_axi_s2mm_awsize, - m_axi_s2mm_awburst, - m_axi_s2mm_awprot, - m_axi_s2mm_awcache, - m_axi_s2mm_awvalid, - m_axi_s2mm_awready, - m_axi_s2mm_wdata, - m_axi_s2mm_wstrb, - m_axi_s2mm_wlast, - m_axi_s2mm_wvalid, - m_axi_s2mm_wready, - m_axi_s2mm_bresp, - m_axi_s2mm_bvalid, - m_axi_s2mm_bready, - s2mm_prmry_reset_out_n, - s_axis_s2mm_tdata, - s_axis_s2mm_tkeep, - s_axis_s2mm_tuser, - s_axis_s2mm_tvalid, - s_axis_s2mm_tready, - s_axis_s2mm_tlast, - mm2s_introut, - s2mm_introut, - axi_vdma_tstvec); - input s_axi_lite_aclk; - input m_axi_sg_aclk; - input m_axi_mm2s_aclk; - input m_axis_mm2s_aclk; - input m_axi_s2mm_aclk; - input s_axis_s2mm_aclk; - input axi_resetn; - input s_axi_lite_awvalid; - output s_axi_lite_awready; - input [8:0]s_axi_lite_awaddr; - input s_axi_lite_wvalid; - output s_axi_lite_wready; + .D(\FSM_sequential_sig_pcc_sm_state[0]_i_1_n_0 ), + .Q(sig_pcc_sm_state[0]), + .R(sig_init_reg)); + (* KEEP = "yes" *) + FDRE \FSM_sequential_sig_pcc_sm_state_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\FSM_sequential_sig_pcc_sm_state[1]_i_1_n_0 ), + .Q(sig_pcc_sm_state[1]), + .R(sig_init_reg)); + (* KEEP = "yes" *) + FDRE \FSM_sequential_sig_pcc_sm_state_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\FSM_sequential_sig_pcc_sm_state[2]_i_1_n_0 ), + .Q(sig_pcc_sm_state[2]), + .R(sig_init_reg)); + (* SOFT_HLUTNM = "soft_lutpair138" *) + LUT4 #( + .INIT(16'h0010)) + \INFERRED_GEN.cnt_i[2]_i_2 + (.I0(sig_calc_error_pushed), + .I1(sig_sm_halt_reg), + .I2(sig_input_reg_empty), + .I3(Q), + .O(FIFO_Full_reg)); + (* SOFT_HLUTNM = "soft_lutpair156" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][10]_srl4_i_1 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[6] ), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[6]), + .O(in[6])); + (* SOFT_HLUTNM = "soft_lutpair150" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][11]_srl4_i_1 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[7] ), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[7]), + .O(in[7])); + (* SOFT_HLUTNM = "soft_lutpair154" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][12]_srl4_i_1 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[8] ), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[8]), + .O(in[8])); + (* SOFT_HLUTNM = "soft_lutpair145" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][13]_srl4_i_1 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[9] ), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[9]), + .O(in[9])); + (* SOFT_HLUTNM = "soft_lutpair151" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][14]_srl4_i_1 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[10] ), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[10]), + .O(in[10])); + (* SOFT_HLUTNM = "soft_lutpair143" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][15]_srl4_i_1 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[11] ), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[11]), + .O(in[11])); + (* SOFT_HLUTNM = "soft_lutpair144" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][16]_srl4_i_1 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[12] ), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[12]), + .O(in[12])); + (* SOFT_HLUTNM = "soft_lutpair142" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][17]_srl4_i_1 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[13] ), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[13]), + .O(in[13])); + (* SOFT_HLUTNM = "soft_lutpair141" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][18]_srl4_i_1 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[14] ), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[14]), + .O(in[14])); + (* SOFT_HLUTNM = "soft_lutpair140" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][19]_srl4_i_1 + (.I0(p_1_in_0), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[15]), + .O(in[15])); + (* SOFT_HLUTNM = "soft_lutpair146" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][20]_srl4_i_1 + (.I0(sig_addr_cntr_im0_msh_reg[0]), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[16]), + .O(in[16])); + (* SOFT_HLUTNM = "soft_lutpair147" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][21]_srl4_i_1 + (.I0(sig_addr_cntr_im0_msh_reg[1]), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[17]), + .O(in[17])); + (* SOFT_HLUTNM = "soft_lutpair148" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][22]_srl4_i_1 + (.I0(sig_addr_cntr_im0_msh_reg[2]), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[18]), + .O(in[18])); + (* SOFT_HLUTNM = "soft_lutpair149" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][23]_srl4_i_1 + (.I0(sig_addr_cntr_im0_msh_reg[3]), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[19]), + .O(in[19])); + (* SOFT_HLUTNM = "soft_lutpair152" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][24]_srl4_i_1 + (.I0(sig_addr_cntr_im0_msh_reg[4]), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[20]), + .O(in[20])); + (* SOFT_HLUTNM = "soft_lutpair151" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][25]_srl4_i_1 + (.I0(sig_addr_cntr_im0_msh_reg[5]), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[21]), + .O(in[21])); + (* SOFT_HLUTNM = "soft_lutpair149" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][26]_srl4_i_1 + (.I0(sig_addr_cntr_im0_msh_reg[6]), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[22]), + .O(in[22])); + (* SOFT_HLUTNM = "soft_lutpair148" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][27]_srl4_i_1 + (.I0(sig_addr_cntr_im0_msh_reg[7]), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[23]), + .O(in[23])); + (* SOFT_HLUTNM = "soft_lutpair147" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][28]_srl4_i_1 + (.I0(sig_addr_cntr_im0_msh_reg[8]), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[24]), + .O(in[24])); + (* SOFT_HLUTNM = "soft_lutpair146" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][29]_srl4_i_1 + (.I0(sig_addr_cntr_im0_msh_reg[9]), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[25]), + .O(in[25])); + (* SOFT_HLUTNM = "soft_lutpair145" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][30]_srl4_i_1 + (.I0(sig_addr_cntr_im0_msh_reg[10]), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[26]), + .O(in[26])); + (* SOFT_HLUTNM = "soft_lutpair144" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][31]_srl4_i_1 + (.I0(sig_addr_cntr_im0_msh_reg[11]), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[27]), + .O(in[27])); + LUT2 #( + .INIT(4'h2)) + \INFERRED_GEN.data_reg[3][32]_srl4_i_1 + (.I0(sig_mstr2sf_eof), + .I1(sig_mstr2data_sequential), + .O(sig_next_cmd_cmplt_reg_reg[0])); + (* SOFT_HLUTNM = "soft_lutpair143" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][32]_srl4_i_1__0 + (.I0(sig_addr_cntr_im0_msh_reg[12]), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[28]), + .O(in[28])); + LUT6 #( + .INIT(64'h00FFFFFF57575757)) + \INFERRED_GEN.data_reg[3][33]_srl4_i_1 + (.I0(sig_brst_cnt_eq_zero_ireg1), + .I1(sig_btt_eq_b2mbaa_ireg1), + .I2(sig_btt_lt_b2mbaa_ireg1), + .I3(sig_brst_cnt_eq_one_ireg1), + .I4(sig_addr_aligned_ireg1), + .I5(sig_no_btt_residue_ireg1), + .O(sig_mstr2data_sequential)); + (* SOFT_HLUTNM = "soft_lutpair142" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][33]_srl4_i_1__0 + (.I0(sig_addr_cntr_im0_msh_reg[13]), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[29]), + .O(in[29])); + (* SOFT_HLUTNM = "soft_lutpair137" *) + LUT2 #( + .INIT(4'hB)) + \INFERRED_GEN.data_reg[3][34]_srl4_i_1 + (.I0(in[38]), + .I1(sig_mstr2data_sequential), + .O(sig_next_cmd_cmplt_reg_reg[1])); + (* SOFT_HLUTNM = "soft_lutpair141" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][34]_srl4_i_1__0 + (.I0(sig_addr_cntr_im0_msh_reg[14]), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[30]), + .O(in[30])); + (* SOFT_HLUTNM = "soft_lutpair140" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][35]_srl4_i_1 + (.I0(sig_addr_cntr_im0_msh_reg[15]), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[31]), + .O(in[31])); + (* SOFT_HLUTNM = "soft_lutpair134" *) + LUT4 #( + .INIT(16'hFE01)) + \INFERRED_GEN.data_reg[3][36]_srl4_i_1 + (.I0(\sig_adjusted_addr_incr_ireg2_reg_n_0_[2] ), + .I1(\sig_adjusted_addr_incr_ireg2_reg_n_0_[0] ), + .I2(\sig_adjusted_addr_incr_ireg2_reg_n_0_[1] ), + .I3(\sig_adjusted_addr_incr_ireg2_reg_n_0_[3] ), + .O(in[32])); + (* SOFT_HLUTNM = "soft_lutpair134" *) + LUT5 #( + .INIT(32'hFFFE0001)) + \INFERRED_GEN.data_reg[3][37]_srl4_i_1 + (.I0(\sig_adjusted_addr_incr_ireg2_reg_n_0_[3] ), + .I1(\sig_adjusted_addr_incr_ireg2_reg_n_0_[1] ), + .I2(\sig_adjusted_addr_incr_ireg2_reg_n_0_[0] ), + .I3(\sig_adjusted_addr_incr_ireg2_reg_n_0_[2] ), + .I4(\sig_adjusted_addr_incr_ireg2_reg_n_0_[4] ), + .O(in[33])); + LUT6 #( + .INIT(64'hFFFFFFFE00000001)) + \INFERRED_GEN.data_reg[3][38]_srl4_i_1 + (.I0(\sig_adjusted_addr_incr_ireg2_reg_n_0_[4] ), + .I1(\sig_adjusted_addr_incr_ireg2_reg_n_0_[2] ), + .I2(\sig_adjusted_addr_incr_ireg2_reg_n_0_[0] ), + .I3(\sig_adjusted_addr_incr_ireg2_reg_n_0_[1] ), + .I4(\sig_adjusted_addr_incr_ireg2_reg_n_0_[3] ), + .I5(\sig_adjusted_addr_incr_ireg2_reg_n_0_[5] ), + .O(in[34])); + (* SOFT_HLUTNM = "soft_lutpair158" *) + LUT2 #( + .INIT(4'h9)) + \INFERRED_GEN.data_reg[3][39]_srl4_i_1 + (.I0(\sig_byte_change_minus1_im2/i__n_0 ), + .I1(\sig_adjusted_addr_incr_ireg2_reg_n_0_[6] ), + .O(in[35])); + (* SOFT_HLUTNM = "soft_lutpair158" *) + LUT3 #( + .INIT(8'hE1)) + \INFERRED_GEN.data_reg[3][40]_srl4_i_1 + (.I0(\sig_adjusted_addr_incr_ireg2_reg_n_0_[6] ), + .I1(\sig_byte_change_minus1_im2/i__n_0 ), + .I2(\sig_adjusted_addr_incr_ireg2_reg_n_0_[7] ), + .O(in[36])); + (* SOFT_HLUTNM = "soft_lutpair154" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][4]_srl4_i_2 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[0]), + .O(in[0])); + (* SOFT_HLUTNM = "soft_lutpair153" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][5]_srl4_i_1 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[1]), + .O(in[1])); + (* SOFT_HLUTNM = "soft_lutpair152" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][6]_srl4_i_1 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[2]), + .O(in[2])); + (* SOFT_HLUTNM = "soft_lutpair157" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][7]_srl4_i_1__1 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[3] ), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[3]), + .O(in[3])); + (* SOFT_HLUTNM = "soft_lutpair157" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][8]_srl4_i_1 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[4] ), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[4]), + .O(in[4])); + (* SOFT_HLUTNM = "soft_lutpair156" *) + LUT3 #( + .INIT(8'hB8)) + \INFERRED_GEN.data_reg[3][9]_srl4_i_1 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[5] ), + .I1(in[37]), + .I2(sig_addr_cntr_lsh_kh[5]), + .O(in[5])); + (* SOFT_HLUTNM = "soft_lutpair150" *) + LUT3 #( + .INIT(8'h04)) + sig_addr_aligned_ireg1_i_1 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[6] ), + .I1(\sig_bytes_to_mbaa_ireg1[7]_i_2_n_0 ), + .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[7] ), + .O(sig_addr_aligned_im0)); + FDRE #( + .INIT(1'b0)) + sig_addr_aligned_ireg1_reg + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc1_reg), + .D(sig_addr_aligned_im0), + .Q(sig_addr_aligned_ireg1), + .R(sig_init_reg)); + LUT4 #( + .INIT(16'hBAAA)) + \sig_addr_cntr_im0_msh[0]_i_1 + (.I0(sig_calc_error_reg0), + .I1(sig_predict_addr_lsh_ireg3), + .I2(p_1_in_0), + .I3(sig_pop_xfer_reg0_out), + .O(\sig_addr_cntr_im0_msh[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_im0_msh[0]_i_3 + (.I0(out[34]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_addr_cntr_im0_msh_reg[0]), + .O(\sig_addr_cntr_im0_msh[0]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_im0_msh[0]_i_4 + (.I0(out[37]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_addr_cntr_im0_msh_reg[3]), + .O(\sig_addr_cntr_im0_msh[0]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_im0_msh[0]_i_5 + (.I0(out[36]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_addr_cntr_im0_msh_reg[2]), + .O(\sig_addr_cntr_im0_msh[0]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_im0_msh[0]_i_6 + (.I0(out[35]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_addr_cntr_im0_msh_reg[1]), + .O(\sig_addr_cntr_im0_msh[0]_i_6_n_0 )); + LUT6 #( + .INIT(64'h5555555555555C55)) + \sig_addr_cntr_im0_msh[0]_i_7 + (.I0(sig_addr_cntr_im0_msh_reg[0]), + .I1(out[34]), + .I2(Q), + .I3(sig_input_reg_empty), + .I4(sig_sm_halt_reg), + .I5(in[38]), + .O(\sig_addr_cntr_im0_msh[0]_i_7_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_im0_msh[12]_i_2 + (.I0(out[49]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_addr_cntr_im0_msh_reg[15]), + .O(\sig_addr_cntr_im0_msh[12]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_im0_msh[12]_i_3 + (.I0(out[48]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_addr_cntr_im0_msh_reg[14]), + .O(\sig_addr_cntr_im0_msh[12]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_im0_msh[12]_i_4 + (.I0(out[47]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_addr_cntr_im0_msh_reg[13]), + .O(\sig_addr_cntr_im0_msh[12]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_im0_msh[12]_i_5 + (.I0(out[46]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_addr_cntr_im0_msh_reg[12]), + .O(\sig_addr_cntr_im0_msh[12]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_im0_msh[4]_i_2 + (.I0(out[41]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_addr_cntr_im0_msh_reg[7]), + .O(\sig_addr_cntr_im0_msh[4]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_im0_msh[4]_i_3 + (.I0(out[40]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_addr_cntr_im0_msh_reg[6]), + .O(\sig_addr_cntr_im0_msh[4]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_im0_msh[4]_i_4 + (.I0(out[39]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_addr_cntr_im0_msh_reg[5]), + .O(\sig_addr_cntr_im0_msh[4]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_im0_msh[4]_i_5 + (.I0(out[38]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_addr_cntr_im0_msh_reg[4]), + .O(\sig_addr_cntr_im0_msh[4]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_im0_msh[8]_i_2 + (.I0(out[45]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_addr_cntr_im0_msh_reg[11]), + .O(\sig_addr_cntr_im0_msh[8]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_im0_msh[8]_i_3 + (.I0(out[44]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_addr_cntr_im0_msh_reg[10]), + .O(\sig_addr_cntr_im0_msh[8]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_im0_msh[8]_i_4 + (.I0(out[43]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_addr_cntr_im0_msh_reg[9]), + .O(\sig_addr_cntr_im0_msh[8]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_im0_msh[8]_i_5 + (.I0(out[42]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_addr_cntr_im0_msh_reg[8]), + .O(\sig_addr_cntr_im0_msh[8]_i_5_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_im0_msh_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), + .D(\sig_addr_cntr_im0_msh_reg[0]_i_2_n_7 ), + .Q(sig_addr_cntr_im0_msh_reg[0]), + .R(sig_init_reg)); + CARRY4 \sig_addr_cntr_im0_msh_reg[0]_i_2 + (.CI(1'b0), + .CO({\sig_addr_cntr_im0_msh_reg[0]_i_2_n_0 ,\sig_addr_cntr_im0_msh_reg[0]_i_2_n_1 ,\sig_addr_cntr_im0_msh_reg[0]_i_2_n_2 ,\sig_addr_cntr_im0_msh_reg[0]_i_2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,\sig_addr_cntr_im0_msh[0]_i_3_n_0 }), + .O({\sig_addr_cntr_im0_msh_reg[0]_i_2_n_4 ,\sig_addr_cntr_im0_msh_reg[0]_i_2_n_5 ,\sig_addr_cntr_im0_msh_reg[0]_i_2_n_6 ,\sig_addr_cntr_im0_msh_reg[0]_i_2_n_7 }), + .S({\sig_addr_cntr_im0_msh[0]_i_4_n_0 ,\sig_addr_cntr_im0_msh[0]_i_5_n_0 ,\sig_addr_cntr_im0_msh[0]_i_6_n_0 ,\sig_addr_cntr_im0_msh[0]_i_7_n_0 })); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_im0_msh_reg[10] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), + .D(\sig_addr_cntr_im0_msh_reg[8]_i_1_n_5 ), + .Q(sig_addr_cntr_im0_msh_reg[10]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_im0_msh_reg[11] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), + .D(\sig_addr_cntr_im0_msh_reg[8]_i_1_n_4 ), + .Q(sig_addr_cntr_im0_msh_reg[11]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_im0_msh_reg[12] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), + .D(\sig_addr_cntr_im0_msh_reg[12]_i_1_n_7 ), + .Q(sig_addr_cntr_im0_msh_reg[12]), + .R(sig_init_reg)); + CARRY4 \sig_addr_cntr_im0_msh_reg[12]_i_1 + (.CI(\sig_addr_cntr_im0_msh_reg[8]_i_1_n_0 ), + .CO({\NLW_sig_addr_cntr_im0_msh_reg[12]_i_1_CO_UNCONNECTED [3],\sig_addr_cntr_im0_msh_reg[12]_i_1_n_1 ,\sig_addr_cntr_im0_msh_reg[12]_i_1_n_2 ,\sig_addr_cntr_im0_msh_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\sig_addr_cntr_im0_msh_reg[12]_i_1_n_4 ,\sig_addr_cntr_im0_msh_reg[12]_i_1_n_5 ,\sig_addr_cntr_im0_msh_reg[12]_i_1_n_6 ,\sig_addr_cntr_im0_msh_reg[12]_i_1_n_7 }), + .S({\sig_addr_cntr_im0_msh[12]_i_2_n_0 ,\sig_addr_cntr_im0_msh[12]_i_3_n_0 ,\sig_addr_cntr_im0_msh[12]_i_4_n_0 ,\sig_addr_cntr_im0_msh[12]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_im0_msh_reg[13] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), + .D(\sig_addr_cntr_im0_msh_reg[12]_i_1_n_6 ), + .Q(sig_addr_cntr_im0_msh_reg[13]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_im0_msh_reg[14] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), + .D(\sig_addr_cntr_im0_msh_reg[12]_i_1_n_5 ), + .Q(sig_addr_cntr_im0_msh_reg[14]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_im0_msh_reg[15] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), + .D(\sig_addr_cntr_im0_msh_reg[12]_i_1_n_4 ), + .Q(sig_addr_cntr_im0_msh_reg[15]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_im0_msh_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), + .D(\sig_addr_cntr_im0_msh_reg[0]_i_2_n_6 ), + .Q(sig_addr_cntr_im0_msh_reg[1]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_im0_msh_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), + .D(\sig_addr_cntr_im0_msh_reg[0]_i_2_n_5 ), + .Q(sig_addr_cntr_im0_msh_reg[2]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_im0_msh_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), + .D(\sig_addr_cntr_im0_msh_reg[0]_i_2_n_4 ), + .Q(sig_addr_cntr_im0_msh_reg[3]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_im0_msh_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), + .D(\sig_addr_cntr_im0_msh_reg[4]_i_1_n_7 ), + .Q(sig_addr_cntr_im0_msh_reg[4]), + .R(sig_init_reg)); + CARRY4 \sig_addr_cntr_im0_msh_reg[4]_i_1 + (.CI(\sig_addr_cntr_im0_msh_reg[0]_i_2_n_0 ), + .CO({\sig_addr_cntr_im0_msh_reg[4]_i_1_n_0 ,\sig_addr_cntr_im0_msh_reg[4]_i_1_n_1 ,\sig_addr_cntr_im0_msh_reg[4]_i_1_n_2 ,\sig_addr_cntr_im0_msh_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\sig_addr_cntr_im0_msh_reg[4]_i_1_n_4 ,\sig_addr_cntr_im0_msh_reg[4]_i_1_n_5 ,\sig_addr_cntr_im0_msh_reg[4]_i_1_n_6 ,\sig_addr_cntr_im0_msh_reg[4]_i_1_n_7 }), + .S({\sig_addr_cntr_im0_msh[4]_i_2_n_0 ,\sig_addr_cntr_im0_msh[4]_i_3_n_0 ,\sig_addr_cntr_im0_msh[4]_i_4_n_0 ,\sig_addr_cntr_im0_msh[4]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_im0_msh_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), + .D(\sig_addr_cntr_im0_msh_reg[4]_i_1_n_6 ), + .Q(sig_addr_cntr_im0_msh_reg[5]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_im0_msh_reg[6] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), + .D(\sig_addr_cntr_im0_msh_reg[4]_i_1_n_5 ), + .Q(sig_addr_cntr_im0_msh_reg[6]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_im0_msh_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), + .D(\sig_addr_cntr_im0_msh_reg[4]_i_1_n_4 ), + .Q(sig_addr_cntr_im0_msh_reg[7]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_im0_msh_reg[8] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), + .D(\sig_addr_cntr_im0_msh_reg[8]_i_1_n_7 ), + .Q(sig_addr_cntr_im0_msh_reg[8]), + .R(sig_init_reg)); + CARRY4 \sig_addr_cntr_im0_msh_reg[8]_i_1 + (.CI(\sig_addr_cntr_im0_msh_reg[4]_i_1_n_0 ), + .CO({\sig_addr_cntr_im0_msh_reg[8]_i_1_n_0 ,\sig_addr_cntr_im0_msh_reg[8]_i_1_n_1 ,\sig_addr_cntr_im0_msh_reg[8]_i_1_n_2 ,\sig_addr_cntr_im0_msh_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\sig_addr_cntr_im0_msh_reg[8]_i_1_n_4 ,\sig_addr_cntr_im0_msh_reg[8]_i_1_n_5 ,\sig_addr_cntr_im0_msh_reg[8]_i_1_n_6 ,\sig_addr_cntr_im0_msh_reg[8]_i_1_n_7 }), + .S({\sig_addr_cntr_im0_msh[8]_i_2_n_0 ,\sig_addr_cntr_im0_msh[8]_i_3_n_0 ,\sig_addr_cntr_im0_msh[8]_i_4_n_0 ,\sig_addr_cntr_im0_msh[8]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_im0_msh_reg[9] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_im0_msh[0]_i_1_n_0 ), + .D(\sig_addr_cntr_im0_msh_reg[8]_i_1_n_6 ), + .Q(sig_addr_cntr_im0_msh_reg[9]), + .R(sig_init_reg)); + (* SOFT_HLUTNM = "soft_lutpair136" *) + LUT4 #( + .INIT(16'hB888)) + \sig_addr_cntr_incr_ireg2[0]_i_1 + (.I0(sig_btt_residue_slice_im0[0]), + .I1(sig_btt_lt_b2mbaa_ireg1), + .I2(sig_first_xfer_im0), + .I3(sig_bytes_to_mbaa_ireg1[0]), + .O(\sig_addr_cntr_incr_ireg2[0]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sig_addr_cntr_incr_ireg2[1]_i_1 + (.I0(sig_btt_residue_slice_im0[1]), + .I1(sig_btt_lt_b2mbaa_ireg1), + .I2(sig_first_xfer_im0), + .I3(sig_bytes_to_mbaa_ireg1[1]), + .O(\sig_addr_cntr_incr_ireg2[1]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sig_addr_cntr_incr_ireg2[2]_i_1 + (.I0(sig_btt_residue_slice_im0[2]), + .I1(sig_btt_lt_b2mbaa_ireg1), + .I2(sig_first_xfer_im0), + .I3(sig_bytes_to_mbaa_ireg1[2]), + .O(\sig_addr_cntr_incr_ireg2[2]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sig_addr_cntr_incr_ireg2[3]_i_1 + (.I0(sig_btt_residue_slice_im0[3]), + .I1(sig_btt_lt_b2mbaa_ireg1), + .I2(sig_first_xfer_im0), + .I3(sig_bytes_to_mbaa_ireg1[3]), + .O(\sig_addr_cntr_incr_ireg2[3]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sig_addr_cntr_incr_ireg2[4]_i_1 + (.I0(sig_btt_residue_slice_im0[4]), + .I1(sig_btt_lt_b2mbaa_ireg1), + .I2(sig_first_xfer_im0), + .I3(sig_bytes_to_mbaa_ireg1[4]), + .O(\sig_addr_cntr_incr_ireg2[4]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sig_addr_cntr_incr_ireg2[5]_i_1 + (.I0(sig_btt_residue_slice_im0[5]), + .I1(sig_btt_lt_b2mbaa_ireg1), + .I2(sig_first_xfer_im0), + .I3(sig_bytes_to_mbaa_ireg1[5]), + .O(\sig_addr_cntr_incr_ireg2[5]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sig_addr_cntr_incr_ireg2[6]_i_1 + (.I0(sig_btt_residue_slice_im0[6]), + .I1(sig_btt_lt_b2mbaa_ireg1), + .I2(sig_first_xfer_im0), + .I3(sig_bytes_to_mbaa_ireg1[6]), + .O(\sig_addr_cntr_incr_ireg2[6]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sig_addr_cntr_incr_ireg2[7]_i_1 + (.I0(sig_btt_residue_slice_im0[7]), + .I1(sig_btt_lt_b2mbaa_ireg1), + .I2(sig_first_xfer_im0), + .I3(sig_bytes_to_mbaa_ireg1[7]), + .O(\sig_addr_cntr_incr_ireg2[7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair136" *) + LUT3 #( + .INIT(8'h0D)) + \sig_addr_cntr_incr_ireg2[8]_i_1 + (.I0(sig_first_xfer_im0), + .I1(sig_addr_aligned_ireg1), + .I2(sig_btt_lt_b2mbaa_ireg1), + .O(\sig_addr_cntr_incr_ireg2[8]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_incr_ireg2_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc2_reg), + .D(\sig_addr_cntr_incr_ireg2[0]_i_1_n_0 ), + .Q(sig_addr_cntr_incr_ireg2[0]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_incr_ireg2_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc2_reg), + .D(\sig_addr_cntr_incr_ireg2[1]_i_1_n_0 ), + .Q(sig_addr_cntr_incr_ireg2[1]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_incr_ireg2_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc2_reg), + .D(\sig_addr_cntr_incr_ireg2[2]_i_1_n_0 ), + .Q(sig_addr_cntr_incr_ireg2[2]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_incr_ireg2_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc2_reg), + .D(\sig_addr_cntr_incr_ireg2[3]_i_1_n_0 ), + .Q(sig_addr_cntr_incr_ireg2[3]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_incr_ireg2_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc2_reg), + .D(\sig_addr_cntr_incr_ireg2[4]_i_1_n_0 ), + .Q(sig_addr_cntr_incr_ireg2[4]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_incr_ireg2_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc2_reg), + .D(\sig_addr_cntr_incr_ireg2[5]_i_1_n_0 ), + .Q(sig_addr_cntr_incr_ireg2[5]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_incr_ireg2_reg[6] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc2_reg), + .D(\sig_addr_cntr_incr_ireg2[6]_i_1_n_0 ), + .Q(sig_addr_cntr_incr_ireg2[6]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_incr_ireg2_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc2_reg), + .D(\sig_addr_cntr_incr_ireg2[7]_i_1_n_0 ), + .Q(sig_addr_cntr_incr_ireg2[7]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_incr_ireg2_reg[8] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc2_reg), + .D(\sig_addr_cntr_incr_ireg2[8]_i_1_n_0 ), + .Q(sig_addr_cntr_incr_ireg2[8]), + .R(sig_init_reg)); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_lsh_im0[0]_i_1 + (.I0(out[18]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(\sig_predict_addr_lsh_ireg3_reg_n_0_[0] ), + .O(p_1_in[0])); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_lsh_im0[10]_i_1 + (.I0(out[28]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(\sig_predict_addr_lsh_ireg3_reg_n_0_[10] ), + .O(p_1_in[10])); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_lsh_im0[11]_i_1 + (.I0(out[29]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(\sig_predict_addr_lsh_ireg3_reg_n_0_[11] ), + .O(p_1_in[11])); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_lsh_im0[12]_i_1 + (.I0(out[30]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(\sig_predict_addr_lsh_ireg3_reg_n_0_[12] ), + .O(p_1_in[12])); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_lsh_im0[13]_i_1 + (.I0(out[31]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(\sig_predict_addr_lsh_ireg3_reg_n_0_[13] ), + .O(p_1_in[13])); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_lsh_im0[14]_i_1 + (.I0(out[32]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(\sig_predict_addr_lsh_ireg3_reg_n_0_[14] ), + .O(p_1_in[14])); + LUT5 #( + .INIT(32'hFFFF0004)) + \sig_addr_cntr_lsh_im0[15]_i_1 + (.I0(Q), + .I1(sig_input_reg_empty), + .I2(sig_sm_halt_reg), + .I3(in[38]), + .I4(sig_pop_xfer_reg0_out), + .O(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_lsh_im0[15]_i_2 + (.I0(out[33]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_predict_addr_lsh_ireg3), + .O(p_1_in[15])); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_lsh_im0[1]_i_1 + (.I0(out[19]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(\sig_predict_addr_lsh_ireg3_reg_n_0_[1] ), + .O(p_1_in[1])); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_lsh_im0[2]_i_1 + (.I0(out[20]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(\sig_predict_addr_lsh_ireg3_reg_n_0_[2] ), + .O(p_1_in[2])); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_lsh_im0[3]_i_1 + (.I0(out[21]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(\sig_predict_addr_lsh_ireg3_reg_n_0_[3] ), + .O(p_1_in[3])); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_lsh_im0[4]_i_1 + (.I0(out[22]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(\sig_predict_addr_lsh_ireg3_reg_n_0_[4] ), + .O(p_1_in[4])); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_lsh_im0[5]_i_1 + (.I0(out[23]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(\sig_predict_addr_lsh_ireg3_reg_n_0_[5] ), + .O(p_1_in[5])); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_lsh_im0[6]_i_1 + (.I0(out[24]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(\sig_predict_addr_lsh_ireg3_reg_n_0_[6] ), + .O(p_1_in[6])); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_lsh_im0[7]_i_1 + (.I0(out[25]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(\sig_predict_addr_lsh_ireg3_reg_n_0_[7] ), + .O(p_1_in[7])); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_lsh_im0[8]_i_1 + (.I0(out[26]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(\sig_predict_addr_lsh_ireg3_reg_n_0_[8] ), + .O(p_1_in[8])); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_addr_cntr_lsh_im0[9]_i_1 + (.I0(out[27]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(\sig_predict_addr_lsh_ireg3_reg_n_0_[9] ), + .O(p_1_in[9])); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_im0_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(p_1_in[0]), + .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_im0_reg[10] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(p_1_in[10]), + .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[10] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_im0_reg[11] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(p_1_in[11]), + .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[11] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_im0_reg[12] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(p_1_in[12]), + .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[12] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_im0_reg[13] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(p_1_in[13]), + .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[13] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_im0_reg[14] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(p_1_in[14]), + .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[14] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_im0_reg[15] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(p_1_in[15]), + .Q(p_1_in_0), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_im0_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(p_1_in[1]), + .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_im0_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(p_1_in[2]), + .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_im0_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(p_1_in[3]), + .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[3] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_im0_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(p_1_in[4]), + .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[4] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_im0_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(p_1_in[5]), + .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[5] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_im0_reg[6] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(p_1_in[6]), + .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[6] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_im0_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(p_1_in[7]), + .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[7] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_im0_reg[8] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(p_1_in[8]), + .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[8] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_im0_reg[9] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(p_1_in[9]), + .Q(\sig_addr_cntr_lsh_im0_reg_n_0_[9] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[18]), + .Q(sig_addr_cntr_lsh_kh[0]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[10] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[28]), + .Q(sig_addr_cntr_lsh_kh[10]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[11] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[29]), + .Q(sig_addr_cntr_lsh_kh[11]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[12] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[30]), + .Q(sig_addr_cntr_lsh_kh[12]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[13] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[31]), + .Q(sig_addr_cntr_lsh_kh[13]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[14] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[32]), + .Q(sig_addr_cntr_lsh_kh[14]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[15] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[33]), + .Q(sig_addr_cntr_lsh_kh[15]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[16] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[34]), + .Q(sig_addr_cntr_lsh_kh[16]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[17] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[35]), + .Q(sig_addr_cntr_lsh_kh[17]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[18] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[36]), + .Q(sig_addr_cntr_lsh_kh[18]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[19] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[37]), + .Q(sig_addr_cntr_lsh_kh[19]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[19]), + .Q(sig_addr_cntr_lsh_kh[1]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[20] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[38]), + .Q(sig_addr_cntr_lsh_kh[20]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[21] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[39]), + .Q(sig_addr_cntr_lsh_kh[21]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[22] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[40]), + .Q(sig_addr_cntr_lsh_kh[22]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[23] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[41]), + .Q(sig_addr_cntr_lsh_kh[23]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[24] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[42]), + .Q(sig_addr_cntr_lsh_kh[24]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[25] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[43]), + .Q(sig_addr_cntr_lsh_kh[25]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[26] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[44]), + .Q(sig_addr_cntr_lsh_kh[26]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[27] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[45]), + .Q(sig_addr_cntr_lsh_kh[27]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[28] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[46]), + .Q(sig_addr_cntr_lsh_kh[28]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[29] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[47]), + .Q(sig_addr_cntr_lsh_kh[29]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[20]), + .Q(sig_addr_cntr_lsh_kh[2]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[30] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[48]), + .Q(sig_addr_cntr_lsh_kh[30]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[31] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[49]), + .Q(sig_addr_cntr_lsh_kh[31]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[21]), + .Q(sig_addr_cntr_lsh_kh[3]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[22]), + .Q(sig_addr_cntr_lsh_kh[4]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[23]), + .Q(sig_addr_cntr_lsh_kh[5]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[6] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[24]), + .Q(sig_addr_cntr_lsh_kh[6]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[25]), + .Q(sig_addr_cntr_lsh_kh[7]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[8] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[26]), + .Q(sig_addr_cntr_lsh_kh[8]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_addr_cntr_lsh_kh_reg[9] + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[27]), + .Q(sig_addr_cntr_lsh_kh[9]), + .R(sig_init_reg)); + LUT4 #( + .INIT(16'hB888)) + \sig_adjusted_addr_incr_ireg2[3]_i_2 + (.I0(sig_btt_residue_slice_im0[3]), + .I1(sig_btt_lt_b2mbaa_ireg1), + .I2(sig_first_xfer_im0), + .I3(sig_bytes_to_mbaa_ireg1[3]), + .O(\sig_adjusted_addr_incr_ireg2[3]_i_2_n_0 )); + LUT5 #( + .INIT(32'h07F7F808)) + \sig_adjusted_addr_incr_ireg2[3]_i_3 + (.I0(sig_bytes_to_mbaa_ireg1[2]), + .I1(sig_first_xfer_im0), + .I2(sig_btt_lt_b2mbaa_ireg1), + .I3(sig_btt_residue_slice_im0[2]), + .I4(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), + .O(\sig_adjusted_addr_incr_ireg2[3]_i_3_n_0 )); + LUT5 #( + .INIT(32'h07F7F808)) + \sig_adjusted_addr_incr_ireg2[3]_i_4 + (.I0(sig_bytes_to_mbaa_ireg1[1]), + .I1(sig_first_xfer_im0), + .I2(sig_btt_lt_b2mbaa_ireg1), + .I3(sig_btt_residue_slice_im0[1]), + .I4(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), + .O(\sig_adjusted_addr_incr_ireg2[3]_i_4_n_0 )); + LUT5 #( + .INIT(32'h07F7F808)) + \sig_adjusted_addr_incr_ireg2[3]_i_5 + (.I0(sig_bytes_to_mbaa_ireg1[0]), + .I1(sig_first_xfer_im0), + .I2(sig_btt_lt_b2mbaa_ireg1), + .I3(sig_btt_residue_slice_im0[0]), + .I4(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), + .O(\sig_adjusted_addr_incr_ireg2[3]_i_5_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sig_adjusted_addr_incr_ireg2[7]_i_2 + (.I0(sig_btt_residue_slice_im0[7]), + .I1(sig_btt_lt_b2mbaa_ireg1), + .I2(sig_first_xfer_im0), + .I3(sig_bytes_to_mbaa_ireg1[7]), + .O(\sig_adjusted_addr_incr_ireg2[7]_i_2_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sig_adjusted_addr_incr_ireg2[7]_i_3 + (.I0(sig_btt_residue_slice_im0[6]), + .I1(sig_btt_lt_b2mbaa_ireg1), + .I2(sig_first_xfer_im0), + .I3(sig_bytes_to_mbaa_ireg1[6]), + .O(\sig_adjusted_addr_incr_ireg2[7]_i_3_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sig_adjusted_addr_incr_ireg2[7]_i_4 + (.I0(sig_btt_residue_slice_im0[5]), + .I1(sig_btt_lt_b2mbaa_ireg1), + .I2(sig_first_xfer_im0), + .I3(sig_bytes_to_mbaa_ireg1[5]), + .O(\sig_adjusted_addr_incr_ireg2[7]_i_4_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \sig_adjusted_addr_incr_ireg2[7]_i_5 + (.I0(sig_btt_residue_slice_im0[4]), + .I1(sig_btt_lt_b2mbaa_ireg1), + .I2(sig_first_xfer_im0), + .I3(sig_bytes_to_mbaa_ireg1[4]), + .O(\sig_adjusted_addr_incr_ireg2[7]_i_5_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_adjusted_addr_incr_ireg2_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc2_reg), + .D(sig_adjusted_addr_incr_im1[0]), + .Q(\sig_adjusted_addr_incr_ireg2_reg_n_0_[0] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_adjusted_addr_incr_ireg2_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc2_reg), + .D(sig_adjusted_addr_incr_im1[1]), + .Q(\sig_adjusted_addr_incr_ireg2_reg_n_0_[1] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_adjusted_addr_incr_ireg2_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc2_reg), + .D(sig_adjusted_addr_incr_im1[2]), + .Q(\sig_adjusted_addr_incr_ireg2_reg_n_0_[2] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_adjusted_addr_incr_ireg2_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc2_reg), + .D(sig_adjusted_addr_incr_im1[3]), + .Q(\sig_adjusted_addr_incr_ireg2_reg_n_0_[3] ), + .R(sig_init_reg)); + CARRY4 \sig_adjusted_addr_incr_ireg2_reg[3]_i_1 + (.CI(1'b0), + .CO({\sig_adjusted_addr_incr_ireg2_reg[3]_i_1_n_0 ,\sig_adjusted_addr_incr_ireg2_reg[3]_i_1_n_1 ,\sig_adjusted_addr_incr_ireg2_reg[3]_i_1_n_2 ,\sig_adjusted_addr_incr_ireg2_reg[3]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,\sig_addr_cntr_lsh_im0_reg_n_0_[2] ,\sig_addr_cntr_lsh_im0_reg_n_0_[1] ,\sig_addr_cntr_lsh_im0_reg_n_0_[0] }), + .O(sig_adjusted_addr_incr_im1[3:0]), + .S({\sig_adjusted_addr_incr_ireg2[3]_i_2_n_0 ,\sig_adjusted_addr_incr_ireg2[3]_i_3_n_0 ,\sig_adjusted_addr_incr_ireg2[3]_i_4_n_0 ,\sig_adjusted_addr_incr_ireg2[3]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \sig_adjusted_addr_incr_ireg2_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc2_reg), + .D(sig_adjusted_addr_incr_im1[4]), + .Q(\sig_adjusted_addr_incr_ireg2_reg_n_0_[4] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_adjusted_addr_incr_ireg2_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc2_reg), + .D(sig_adjusted_addr_incr_im1[5]), + .Q(\sig_adjusted_addr_incr_ireg2_reg_n_0_[5] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_adjusted_addr_incr_ireg2_reg[6] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc2_reg), + .D(sig_adjusted_addr_incr_im1[6]), + .Q(\sig_adjusted_addr_incr_ireg2_reg_n_0_[6] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_adjusted_addr_incr_ireg2_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc2_reg), + .D(sig_adjusted_addr_incr_im1[7]), + .Q(\sig_adjusted_addr_incr_ireg2_reg_n_0_[7] ), + .R(sig_init_reg)); + CARRY4 \sig_adjusted_addr_incr_ireg2_reg[7]_i_1 + (.CI(\sig_adjusted_addr_incr_ireg2_reg[3]_i_1_n_0 ), + .CO({\NLW_sig_adjusted_addr_incr_ireg2_reg[7]_i_1_CO_UNCONNECTED [3],\sig_adjusted_addr_incr_ireg2_reg[7]_i_1_n_1 ,\sig_adjusted_addr_incr_ireg2_reg[7]_i_1_n_2 ,\sig_adjusted_addr_incr_ireg2_reg[7]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(sig_adjusted_addr_incr_im1[7:4]), + .S({\sig_adjusted_addr_incr_ireg2[7]_i_2_n_0 ,\sig_adjusted_addr_incr_ireg2[7]_i_3_n_0 ,\sig_adjusted_addr_incr_ireg2[7]_i_4_n_0 ,\sig_adjusted_addr_incr_ireg2[7]_i_5_n_0 })); + (* SOFT_HLUTNM = "soft_lutpair135" *) + LUT5 #( + .INIT(32'h00000008)) + sig_brst_cnt_eq_one_ireg1_i_1 + (.I0(sig_btt_lt_b2mbaa_ireg1_i_2_n_0), + .I1(sel0[0]), + .I2(sel0[2]), + .I3(sel0[3]), + .I4(sel0[1]), + .O(sig_brst_cnt_eq_one_im0)); + FDRE #( + .INIT(1'b0)) + sig_brst_cnt_eq_one_ireg1_reg + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc1_reg), + .D(sig_brst_cnt_eq_one_im0), + .Q(sig_brst_cnt_eq_one_ireg1), + .R(sig_init_reg)); + (* SOFT_HLUTNM = "soft_lutpair135" *) + LUT5 #( + .INIT(32'h00000002)) + sig_brst_cnt_eq_zero_ireg1_i_1 + (.I0(sig_btt_lt_b2mbaa_ireg1_i_2_n_0), + .I1(sel0[2]), + .I2(sel0[3]), + .I3(sel0[1]), + .I4(sel0[0]), + .O(sig_brst_cnt_eq_zero_im0)); + FDRE #( + .INIT(1'b0)) + sig_brst_cnt_eq_zero_ireg1_reg + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc1_reg), + .D(sig_brst_cnt_eq_zero_im0), + .Q(sig_brst_cnt_eq_zero_ireg1), + .R(sig_init_reg)); + CARRY4 sig_btt_cntr_im00_carry + (.CI(1'b0), + .CO({sig_btt_cntr_im00_carry_n_0,sig_btt_cntr_im00_carry_n_1,sig_btt_cntr_im00_carry_n_2,sig_btt_cntr_im00_carry_n_3}), + .CYINIT(1'b1), + .DI(sig_btt_residue_slice_im0[3:0]), + .O(sig_btt_cntr_im00[3:0]), + .S({sig_btt_cntr_im00_carry_i_1_n_0,sig_btt_cntr_im00_carry_i_2_n_0,sig_btt_cntr_im00_carry_i_3_n_0,sig_btt_cntr_im00_carry_i_4_n_0})); + CARRY4 sig_btt_cntr_im00_carry__0 + (.CI(sig_btt_cntr_im00_carry_n_0), + .CO({sig_btt_cntr_im00_carry__0_n_0,sig_btt_cntr_im00_carry__0_n_1,sig_btt_cntr_im00_carry__0_n_2,sig_btt_cntr_im00_carry__0_n_3}), + .CYINIT(1'b0), + .DI(sig_btt_residue_slice_im0[7:4]), + .O(sig_btt_cntr_im00[7:4]), + .S({sig_btt_cntr_im00_carry__0_i_1_n_0,sig_btt_cntr_im00_carry__0_i_2_n_0,sig_btt_cntr_im00_carry__0_i_3_n_0,sig_btt_cntr_im00_carry__0_i_4_n_0})); + LUT2 #( + .INIT(4'h9)) + sig_btt_cntr_im00_carry__0_i_1 + (.I0(sig_btt_residue_slice_im0[7]), + .I1(sig_addr_cntr_incr_ireg2[7]), + .O(sig_btt_cntr_im00_carry__0_i_1_n_0)); + LUT2 #( + .INIT(4'h9)) + sig_btt_cntr_im00_carry__0_i_2 + (.I0(sig_btt_residue_slice_im0[6]), + .I1(sig_addr_cntr_incr_ireg2[6]), + .O(sig_btt_cntr_im00_carry__0_i_2_n_0)); + LUT2 #( + .INIT(4'h9)) + sig_btt_cntr_im00_carry__0_i_3 + (.I0(sig_btt_residue_slice_im0[5]), + .I1(sig_addr_cntr_incr_ireg2[5]), + .O(sig_btt_cntr_im00_carry__0_i_3_n_0)); + LUT2 #( + .INIT(4'h9)) + sig_btt_cntr_im00_carry__0_i_4 + (.I0(sig_btt_residue_slice_im0[4]), + .I1(sig_addr_cntr_incr_ireg2[4]), + .O(sig_btt_cntr_im00_carry__0_i_4_n_0)); + CARRY4 sig_btt_cntr_im00_carry__1 + (.CI(sig_btt_cntr_im00_carry__0_n_0), + .CO({sig_btt_cntr_im00_carry__1_n_0,sig_btt_cntr_im00_carry__1_n_1,sig_btt_cntr_im00_carry__1_n_2,sig_btt_cntr_im00_carry__1_n_3}), + .CYINIT(1'b0), + .DI(sel0[3:0]), + .O(sig_btt_cntr_im00[11:8]), + .S({sig_btt_cntr_im00_carry__1_i_1_n_0,sig_btt_cntr_im00_carry__1_i_2_n_0,sig_btt_cntr_im00_carry__1_i_3_n_0,sig_btt_cntr_im00_carry__1_i_4_n_0})); + LUT1 #( + .INIT(2'h1)) + sig_btt_cntr_im00_carry__1_i_1 + (.I0(sel0[3]), + .O(sig_btt_cntr_im00_carry__1_i_1_n_0)); + LUT1 #( + .INIT(2'h1)) + sig_btt_cntr_im00_carry__1_i_2 + (.I0(sel0[2]), + .O(sig_btt_cntr_im00_carry__1_i_2_n_0)); + LUT1 #( + .INIT(2'h1)) + sig_btt_cntr_im00_carry__1_i_3 + (.I0(sel0[1]), + .O(sig_btt_cntr_im00_carry__1_i_3_n_0)); + LUT2 #( + .INIT(4'h9)) + sig_btt_cntr_im00_carry__1_i_4 + (.I0(sel0[0]), + .I1(sig_addr_cntr_incr_ireg2[8]), + .O(sig_btt_cntr_im00_carry__1_i_4_n_0)); + CARRY4 sig_btt_cntr_im00_carry__2 + (.CI(sig_btt_cntr_im00_carry__1_n_0), + .CO({NLW_sig_btt_cntr_im00_carry__2_CO_UNCONNECTED[3],sig_btt_cntr_im00_carry__2_n_1,sig_btt_cntr_im00_carry__2_n_2,sig_btt_cntr_im00_carry__2_n_3}), + .CYINIT(1'b0), + .DI({1'b0,sel0[6:4]}), + .O(sig_btt_cntr_im00[15:12]), + .S({sig_btt_cntr_im00_carry__2_i_1_n_0,sig_btt_cntr_im00_carry__2_i_2_n_0,sig_btt_cntr_im00_carry__2_i_3_n_0,sig_btt_cntr_im00_carry__2_i_4_n_0})); + LUT1 #( + .INIT(2'h1)) + sig_btt_cntr_im00_carry__2_i_1 + (.I0(sel0[7]), + .O(sig_btt_cntr_im00_carry__2_i_1_n_0)); + LUT1 #( + .INIT(2'h1)) + sig_btt_cntr_im00_carry__2_i_2 + (.I0(sel0[6]), + .O(sig_btt_cntr_im00_carry__2_i_2_n_0)); + LUT1 #( + .INIT(2'h1)) + sig_btt_cntr_im00_carry__2_i_3 + (.I0(sel0[5]), + .O(sig_btt_cntr_im00_carry__2_i_3_n_0)); + LUT1 #( + .INIT(2'h1)) + sig_btt_cntr_im00_carry__2_i_4 + (.I0(sel0[4]), + .O(sig_btt_cntr_im00_carry__2_i_4_n_0)); + LUT2 #( + .INIT(4'h9)) + sig_btt_cntr_im00_carry_i_1 + (.I0(sig_btt_residue_slice_im0[3]), + .I1(sig_addr_cntr_incr_ireg2[3]), + .O(sig_btt_cntr_im00_carry_i_1_n_0)); + LUT2 #( + .INIT(4'h9)) + sig_btt_cntr_im00_carry_i_2 + (.I0(sig_btt_residue_slice_im0[2]), + .I1(sig_addr_cntr_incr_ireg2[2]), + .O(sig_btt_cntr_im00_carry_i_2_n_0)); + LUT2 #( + .INIT(4'h9)) + sig_btt_cntr_im00_carry_i_3 + (.I0(sig_btt_residue_slice_im0[1]), + .I1(sig_addr_cntr_incr_ireg2[1]), + .O(sig_btt_cntr_im00_carry_i_3_n_0)); + LUT2 #( + .INIT(4'h9)) + sig_btt_cntr_im00_carry_i_4 + (.I0(sig_btt_residue_slice_im0[0]), + .I1(sig_addr_cntr_incr_ireg2[0]), + .O(sig_btt_cntr_im00_carry_i_4_n_0)); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_btt_cntr_im0[0]_i_1 + (.I0(out[0]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_btt_cntr_im00[0]), + .O(\sig_btt_cntr_im0[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_btt_cntr_im0[10]_i_1 + (.I0(out[10]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_btt_cntr_im00[10]), + .O(\sig_btt_cntr_im0[10]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_btt_cntr_im0[11]_i_1 + (.I0(out[11]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_btt_cntr_im00[11]), + .O(\sig_btt_cntr_im0[11]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_btt_cntr_im0[12]_i_1 + (.I0(out[12]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_btt_cntr_im00[12]), + .O(\sig_btt_cntr_im0[12]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_btt_cntr_im0[13]_i_1 + (.I0(out[13]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_btt_cntr_im00[13]), + .O(\sig_btt_cntr_im0[13]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_btt_cntr_im0[14]_i_1 + (.I0(out[14]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_btt_cntr_im00[14]), + .O(\sig_btt_cntr_im0[14]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_btt_cntr_im0[15]_i_1 + (.I0(out[15]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_btt_cntr_im00[15]), + .O(\sig_btt_cntr_im0[15]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_btt_cntr_im0[1]_i_1 + (.I0(out[1]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_btt_cntr_im00[1]), + .O(\sig_btt_cntr_im0[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_btt_cntr_im0[2]_i_1 + (.I0(out[2]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_btt_cntr_im00[2]), + .O(\sig_btt_cntr_im0[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_btt_cntr_im0[3]_i_1 + (.I0(out[3]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_btt_cntr_im00[3]), + .O(\sig_btt_cntr_im0[3]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_btt_cntr_im0[4]_i_1 + (.I0(out[4]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_btt_cntr_im00[4]), + .O(\sig_btt_cntr_im0[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_btt_cntr_im0[5]_i_1 + (.I0(out[5]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_btt_cntr_im00[5]), + .O(\sig_btt_cntr_im0[5]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_btt_cntr_im0[6]_i_1 + (.I0(out[6]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_btt_cntr_im00[6]), + .O(\sig_btt_cntr_im0[6]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_btt_cntr_im0[7]_i_1 + (.I0(out[7]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_btt_cntr_im00[7]), + .O(\sig_btt_cntr_im0[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_btt_cntr_im0[8]_i_1 + (.I0(out[8]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_btt_cntr_im00[8]), + .O(\sig_btt_cntr_im0[8]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFEFF00000200)) + \sig_btt_cntr_im0[9]_i_1 + (.I0(out[9]), + .I1(in[38]), + .I2(sig_sm_halt_reg), + .I3(sig_input_reg_empty), + .I4(Q), + .I5(sig_btt_cntr_im00[9]), + .O(\sig_btt_cntr_im0[9]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_im0_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(\sig_btt_cntr_im0[0]_i_1_n_0 ), + .Q(sig_btt_residue_slice_im0[0]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_im0_reg[10] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(\sig_btt_cntr_im0[10]_i_1_n_0 ), + .Q(sel0[2]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_im0_reg[11] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(\sig_btt_cntr_im0[11]_i_1_n_0 ), + .Q(sel0[3]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_im0_reg[12] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(\sig_btt_cntr_im0[12]_i_1_n_0 ), + .Q(sel0[4]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_im0_reg[13] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(\sig_btt_cntr_im0[13]_i_1_n_0 ), + .Q(sel0[5]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_im0_reg[14] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(\sig_btt_cntr_im0[14]_i_1_n_0 ), + .Q(sel0[6]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_im0_reg[15] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(\sig_btt_cntr_im0[15]_i_1_n_0 ), + .Q(sel0[7]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_im0_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(\sig_btt_cntr_im0[1]_i_1_n_0 ), + .Q(sig_btt_residue_slice_im0[1]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_im0_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(\sig_btt_cntr_im0[2]_i_1_n_0 ), + .Q(sig_btt_residue_slice_im0[2]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_im0_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(\sig_btt_cntr_im0[3]_i_1_n_0 ), + .Q(sig_btt_residue_slice_im0[3]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_im0_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(\sig_btt_cntr_im0[4]_i_1_n_0 ), + .Q(sig_btt_residue_slice_im0[4]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_im0_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(\sig_btt_cntr_im0[5]_i_1_n_0 ), + .Q(sig_btt_residue_slice_im0[5]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_im0_reg[6] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(\sig_btt_cntr_im0[6]_i_1_n_0 ), + .Q(sig_btt_residue_slice_im0[6]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_im0_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(\sig_btt_cntr_im0[7]_i_1_n_0 ), + .Q(sig_btt_residue_slice_im0[7]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_im0_reg[8] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(\sig_btt_cntr_im0[8]_i_1_n_0 ), + .Q(sel0[0]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_im0_reg[9] + (.C(m_axi_mm2s_aclk), + .CE(\sig_addr_cntr_lsh_im0[15]_i_1_n_0 ), + .D(\sig_btt_cntr_im0[9]_i_1_n_0 ), + .Q(sel0[1]), + .R(sig_init_reg)); + CARRY4 sig_btt_eq_b2mbaa_im01_carry + (.CI(1'b0), + .CO({NLW_sig_btt_eq_b2mbaa_im01_carry_CO_UNCONNECTED[3],sig_btt_eq_b2mbaa_im01,sig_btt_eq_b2mbaa_im01_carry_n_2,sig_btt_eq_b2mbaa_im01_carry_n_3}), + .CYINIT(1'b1), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(NLW_sig_btt_eq_b2mbaa_im01_carry_O_UNCONNECTED[3:0]), + .S({1'b0,sig_btt_eq_b2mbaa_im01_carry_i_1_n_0,sig_btt_eq_b2mbaa_im01_carry_i_2_n_0,sig_btt_eq_b2mbaa_im01_carry_i_3_n_0})); + LUT5 #( + .INIT(32'h28144028)) + sig_btt_eq_b2mbaa_im01_carry_i_1 + (.I0(sig_btt_residue_slice_im0[6]), + .I1(sig_btt_residue_slice_im0[7]), + .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[7] ), + .I3(\sig_bytes_to_mbaa_ireg1[7]_i_2_n_0 ), + .I4(\sig_addr_cntr_lsh_im0_reg_n_0_[6] ), + .O(sig_btt_eq_b2mbaa_im01_carry_i_1_n_0)); + LUT6 #( + .INIT(64'h2222222888888882)) + sig_btt_eq_b2mbaa_im01_carry_i_2 + (.I0(sig_btt_eq_b2mbaa_im01_carry_i_4_n_0), + .I1(\sig_addr_cntr_lsh_im0_reg_n_0_[3] ), + .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), + .I3(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), + .I4(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), + .I5(sig_btt_residue_slice_im0[3]), + .O(sig_btt_eq_b2mbaa_im01_carry_i_2_n_0)); + LUT6 #( + .INIT(64'h0208041020804001)) + sig_btt_eq_b2mbaa_im01_carry_i_3 + (.I0(sig_btt_residue_slice_im0[0]), + .I1(sig_btt_residue_slice_im0[1]), + .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), + .I3(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), + .I4(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), + .I5(sig_btt_residue_slice_im0[2]), + .O(sig_btt_eq_b2mbaa_im01_carry_i_3_n_0)); + LUT5 #( + .INIT(32'h60060960)) + sig_btt_eq_b2mbaa_im01_carry_i_4 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[5] ), + .I1(sig_btt_residue_slice_im0[5]), + .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[4] ), + .I3(sig_btt_lt_b2mbaa_im01_carry_i_9_n_0), + .I4(sig_btt_residue_slice_im0[4]), + .O(sig_btt_eq_b2mbaa_im01_carry_i_4_n_0)); + LUT6 #( + .INIT(64'h0000000200000000)) + sig_btt_eq_b2mbaa_ireg1_i_1 + (.I0(sig_btt_lt_b2mbaa_ireg1_i_2_n_0), + .I1(sel0[2]), + .I2(sel0[3]), + .I3(sel0[1]), + .I4(sel0[0]), + .I5(sig_btt_eq_b2mbaa_im01), + .O(sig_btt_eq_b2mbaa_im0)); + FDRE #( + .INIT(1'b0)) + sig_btt_eq_b2mbaa_ireg1_reg + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc1_reg), + .D(sig_btt_eq_b2mbaa_im0), + .Q(sig_btt_eq_b2mbaa_ireg1), + .R(sig_init_reg)); + CARRY4 sig_btt_lt_b2mbaa_im01_carry + (.CI(1'b0), + .CO({sig_btt_lt_b2mbaa_im01_carry_n_0,sig_btt_lt_b2mbaa_im01_carry_n_1,sig_btt_lt_b2mbaa_im01_carry_n_2,sig_btt_lt_b2mbaa_im01_carry_n_3}), + .CYINIT(1'b0), + .DI({sig_btt_lt_b2mbaa_im01_carry_i_1_n_0,sig_btt_lt_b2mbaa_im01_carry_i_2_n_0,sig_btt_lt_b2mbaa_im01_carry_i_3_n_0,sig_btt_lt_b2mbaa_im01_carry_i_4_n_0}), + .O(NLW_sig_btt_lt_b2mbaa_im01_carry_O_UNCONNECTED[3:0]), + .S({sig_btt_lt_b2mbaa_im01_carry_i_5_n_0,sig_btt_lt_b2mbaa_im01_carry_i_6_n_0,sig_btt_lt_b2mbaa_im01_carry_i_7_n_0,sig_btt_lt_b2mbaa_im01_carry_i_8_n_0})); + CARRY4 sig_btt_lt_b2mbaa_im01_carry__0 + (.CI(sig_btt_lt_b2mbaa_im01_carry_n_0), + .CO({NLW_sig_btt_lt_b2mbaa_im01_carry__0_CO_UNCONNECTED[3:1],sig_btt_lt_b2mbaa_im01}), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,sig_btt_lt_b2mbaa_im01_carry__0_i_1_n_0}), + .O(NLW_sig_btt_lt_b2mbaa_im01_carry__0_O_UNCONNECTED[3:0]), + .S({1'b0,1'b0,1'b0,sig_btt_lt_b2mbaa_im01_carry__0_i_2_n_0})); + LUT3 #( + .INIT(8'h04)) + sig_btt_lt_b2mbaa_im01_carry__0_i_1 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[6] ), + .I1(\sig_bytes_to_mbaa_ireg1[7]_i_2_n_0 ), + .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[7] ), + .O(sig_btt_lt_b2mbaa_im01_carry__0_i_1_n_0)); + LUT3 #( + .INIT(8'hFB)) + sig_btt_lt_b2mbaa_im01_carry__0_i_2 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[6] ), + .I1(\sig_bytes_to_mbaa_ireg1[7]_i_2_n_0 ), + .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[7] ), + .O(sig_btt_lt_b2mbaa_im01_carry__0_i_2_n_0)); + LUT5 #( + .INIT(32'h004D41F3)) + sig_btt_lt_b2mbaa_im01_carry_i_1 + (.I0(sig_btt_residue_slice_im0[6]), + .I1(\sig_bytes_to_mbaa_ireg1[7]_i_2_n_0 ), + .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[6] ), + .I3(sig_btt_residue_slice_im0[7]), + .I4(\sig_addr_cntr_lsh_im0_reg_n_0_[7] ), + .O(sig_btt_lt_b2mbaa_im01_carry_i_1_n_0)); + LUT5 #( + .INIT(32'h004D41F3)) + sig_btt_lt_b2mbaa_im01_carry_i_2 + (.I0(sig_btt_residue_slice_im0[4]), + .I1(sig_btt_lt_b2mbaa_im01_carry_i_9_n_0), + .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[4] ), + .I3(sig_btt_residue_slice_im0[5]), + .I4(\sig_addr_cntr_lsh_im0_reg_n_0_[5] ), + .O(sig_btt_lt_b2mbaa_im01_carry_i_2_n_0)); + LUT6 #( + .INIT(64'h00015554015557FC)) + sig_btt_lt_b2mbaa_im01_carry_i_3 + (.I0(sig_btt_residue_slice_im0[3]), + .I1(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), + .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), + .I3(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), + .I4(\sig_addr_cntr_lsh_im0_reg_n_0_[3] ), + .I5(sig_btt_residue_slice_im0[2]), + .O(sig_btt_lt_b2mbaa_im01_carry_i_3_n_0)); + LUT4 #( + .INIT(16'h1474)) + sig_btt_lt_b2mbaa_im01_carry_i_4 + (.I0(sig_btt_residue_slice_im0[1]), + .I1(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), + .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), + .I3(sig_btt_residue_slice_im0[0]), + .O(sig_btt_lt_b2mbaa_im01_carry_i_4_n_0)); + LUT5 #( + .INIT(32'h60060960)) + sig_btt_lt_b2mbaa_im01_carry_i_5 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[7] ), + .I1(sig_btt_residue_slice_im0[7]), + .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[6] ), + .I3(\sig_bytes_to_mbaa_ireg1[7]_i_2_n_0 ), + .I4(sig_btt_residue_slice_im0[6]), + .O(sig_btt_lt_b2mbaa_im01_carry_i_5_n_0)); + LUT5 #( + .INIT(32'h60060960)) + sig_btt_lt_b2mbaa_im01_carry_i_6 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[5] ), + .I1(sig_btt_residue_slice_im0[5]), + .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[4] ), + .I3(sig_btt_lt_b2mbaa_im01_carry_i_9_n_0), + .I4(sig_btt_residue_slice_im0[4]), + .O(sig_btt_lt_b2mbaa_im01_carry_i_6_n_0)); + LUT6 #( + .INIT(64'h0606066060606009)) + sig_btt_lt_b2mbaa_im01_carry_i_7 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[3] ), + .I1(sig_btt_residue_slice_im0[3]), + .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), + .I3(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), + .I4(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), + .I5(sig_btt_residue_slice_im0[2]), + .O(sig_btt_lt_b2mbaa_im01_carry_i_7_n_0)); + LUT4 #( + .INIT(16'h6009)) + sig_btt_lt_b2mbaa_im01_carry_i_8 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), + .I1(sig_btt_residue_slice_im0[1]), + .I2(sig_btt_residue_slice_im0[0]), + .I3(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), + .O(sig_btt_lt_b2mbaa_im01_carry_i_8_n_0)); + (* SOFT_HLUTNM = "soft_lutpair133" *) + LUT4 #( + .INIT(16'h0001)) + sig_btt_lt_b2mbaa_im01_carry_i_9 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), + .I1(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), + .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), + .I3(\sig_addr_cntr_lsh_im0_reg_n_0_[3] ), + .O(sig_btt_lt_b2mbaa_im01_carry_i_9_n_0)); + LUT6 #( + .INIT(64'h0000000200000000)) + sig_btt_lt_b2mbaa_ireg1_i_1 + (.I0(sig_btt_lt_b2mbaa_ireg1_i_2_n_0), + .I1(sel0[2]), + .I2(sel0[3]), + .I3(sel0[1]), + .I4(sel0[0]), + .I5(sig_btt_lt_b2mbaa_im01), + .O(sig_btt_lt_b2mbaa_im0)); + LUT4 #( + .INIT(16'h0001)) + sig_btt_lt_b2mbaa_ireg1_i_2 + (.I0(sel0[6]), + .I1(sel0[4]), + .I2(sel0[7]), + .I3(sel0[5]), + .O(sig_btt_lt_b2mbaa_ireg1_i_2_n_0)); + FDRE #( + .INIT(1'b0)) + sig_btt_lt_b2mbaa_ireg1_reg + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc1_reg), + .D(sig_btt_lt_b2mbaa_im0), + .Q(sig_btt_lt_b2mbaa_ireg1), + .R(sig_init_reg)); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \sig_byte_change_minus1_im2/i_ + (.I0(\sig_adjusted_addr_incr_ireg2_reg_n_0_[4] ), + .I1(\sig_adjusted_addr_incr_ireg2_reg_n_0_[2] ), + .I2(\sig_adjusted_addr_incr_ireg2_reg_n_0_[0] ), + .I3(\sig_adjusted_addr_incr_ireg2_reg_n_0_[1] ), + .I4(\sig_adjusted_addr_incr_ireg2_reg_n_0_[3] ), + .I5(\sig_adjusted_addr_incr_ireg2_reg_n_0_[5] ), + .O(\sig_byte_change_minus1_im2/i__n_0 )); + (* SOFT_HLUTNM = "soft_lutpair153" *) + LUT2 #( + .INIT(4'h6)) + \sig_bytes_to_mbaa_ireg1[1]_i_1 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), + .I1(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), + .O(\sig_bytes_to_mbaa_ireg1[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair139" *) + LUT3 #( + .INIT(8'h1E)) + \sig_bytes_to_mbaa_ireg1[2]_i_1 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), + .I1(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), + .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), + .O(\sig_bytes_to_mbaa_ireg1[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair139" *) + LUT4 #( + .INIT(16'h01FE)) + \sig_bytes_to_mbaa_ireg1[3]_i_1 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), + .I1(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), + .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), + .I3(\sig_addr_cntr_lsh_im0_reg_n_0_[3] ), + .O(\sig_bytes_to_mbaa_ireg1[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair133" *) + LUT5 #( + .INIT(32'h0001FFFE)) + \sig_bytes_to_mbaa_ireg1[4]_i_1 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), + .I1(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), + .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), + .I3(\sig_addr_cntr_lsh_im0_reg_n_0_[3] ), + .I4(\sig_addr_cntr_lsh_im0_reg_n_0_[4] ), + .O(\sig_bytes_to_mbaa_ireg1[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00000001FFFFFFFE)) + \sig_bytes_to_mbaa_ireg1[5]_i_1 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[3] ), + .I1(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), + .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), + .I3(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), + .I4(\sig_addr_cntr_lsh_im0_reg_n_0_[4] ), + .I5(\sig_addr_cntr_lsh_im0_reg_n_0_[5] ), + .O(\sig_bytes_to_mbaa_ireg1[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair155" *) + LUT2 #( + .INIT(4'h9)) + \sig_bytes_to_mbaa_ireg1[6]_i_1 + (.I0(\sig_bytes_to_mbaa_ireg1[7]_i_2_n_0 ), + .I1(\sig_addr_cntr_lsh_im0_reg_n_0_[6] ), + .O(\sig_bytes_to_mbaa_ireg1[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair155" *) + LUT3 #( + .INIT(8'h2D)) + \sig_bytes_to_mbaa_ireg1[7]_i_1 + (.I0(\sig_bytes_to_mbaa_ireg1[7]_i_2_n_0 ), + .I1(\sig_addr_cntr_lsh_im0_reg_n_0_[6] ), + .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[7] ), + .O(\sig_bytes_to_mbaa_ireg1[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000000000000001)) + \sig_bytes_to_mbaa_ireg1[7]_i_2 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[4] ), + .I1(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), + .I2(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), + .I3(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), + .I4(\sig_addr_cntr_lsh_im0_reg_n_0_[3] ), + .I5(\sig_addr_cntr_lsh_im0_reg_n_0_[5] ), + .O(\sig_bytes_to_mbaa_ireg1[7]_i_2_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_bytes_to_mbaa_ireg1_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc1_reg), + .D(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), + .Q(sig_bytes_to_mbaa_ireg1[0]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_bytes_to_mbaa_ireg1_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc1_reg), + .D(\sig_bytes_to_mbaa_ireg1[1]_i_1_n_0 ), + .Q(sig_bytes_to_mbaa_ireg1[1]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_bytes_to_mbaa_ireg1_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc1_reg), + .D(\sig_bytes_to_mbaa_ireg1[2]_i_1_n_0 ), + .Q(sig_bytes_to_mbaa_ireg1[2]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_bytes_to_mbaa_ireg1_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc1_reg), + .D(\sig_bytes_to_mbaa_ireg1[3]_i_1_n_0 ), + .Q(sig_bytes_to_mbaa_ireg1[3]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_bytes_to_mbaa_ireg1_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc1_reg), + .D(\sig_bytes_to_mbaa_ireg1[4]_i_1_n_0 ), + .Q(sig_bytes_to_mbaa_ireg1[4]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_bytes_to_mbaa_ireg1_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc1_reg), + .D(\sig_bytes_to_mbaa_ireg1[5]_i_1_n_0 ), + .Q(sig_bytes_to_mbaa_ireg1[5]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_bytes_to_mbaa_ireg1_reg[6] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc1_reg), + .D(\sig_bytes_to_mbaa_ireg1[6]_i_1_n_0 ), + .Q(sig_bytes_to_mbaa_ireg1[6]), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_bytes_to_mbaa_ireg1_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc1_reg), + .D(\sig_bytes_to_mbaa_ireg1[7]_i_1_n_0 ), + .Q(sig_bytes_to_mbaa_ireg1[7]), + .R(sig_init_reg)); + (* SOFT_HLUTNM = "soft_lutpair137" *) + LUT4 #( + .INIT(16'hFF80)) + sig_calc_error_pushed_i_1 + (.I0(in[38]), + .I1(sig_ld_xfer_reg), + .I2(sig_xfer_reg_empty), + .I3(sig_calc_error_pushed), + .O(sig_calc_error_pushed_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + sig_calc_error_pushed_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(sig_calc_error_pushed_i_1_n_0), + .Q(sig_calc_error_pushed), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + sig_calc_error_reg_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(sig_calc_error_reg_reg_0), + .Q(in[38]), + .R(sig_init_reg)); + LUT6 #( + .INIT(64'h000000000000AAAE)) + sig_cmd2addr_valid_i_1 + (.I0(sig_mstr2addr_cmd_valid), + .I1(sig_pcc_sm_state[2]), + .I2(sig_pcc_sm_state[0]), + .I3(sig_pcc_sm_state[1]), + .I4(sig_wr_fifo_1), + .I5(sig_init_reg), + .O(sig_cmd2addr_valid_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + sig_cmd2addr_valid_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(sig_cmd2addr_valid_i_1_n_0), + .Q(sig_mstr2addr_cmd_valid), + .R(1'b0)); + LUT6 #( + .INIT(64'h000000000000AAAE)) + sig_cmd2data_valid_i_1 + (.I0(sig_mstr2data_cmd_valid), + .I1(sig_pcc_sm_state[2]), + .I2(sig_pcc_sm_state[0]), + .I3(sig_pcc_sm_state[1]), + .I4(sig_wr_fifo_0), + .I5(sig_init_reg), + .O(sig_cmd2data_valid_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + sig_cmd2data_valid_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(sig_cmd2data_valid_i_1_n_0), + .Q(sig_mstr2data_cmd_valid), + .R(1'b0)); + LUT6 #( + .INIT(64'h00000000F0FF8888)) + sig_cmd2dre_valid_i_1 + (.I0(sig_first_xfer_im0), + .I1(sig_sm_ld_xfer_reg_ns), + .I2(FIFO_Full_reg_0), + .I3(sig_inhibit_rdy_n), + .I4(sig_mstr2sf_cmd_valid), + .I5(sig_init_reg), + .O(sig_cmd2dre_valid_i_1_n_0)); + LUT3 #( + .INIT(8'h02)) + sig_cmd2dre_valid_i_2 + (.I0(sig_pcc_sm_state[2]), + .I1(sig_pcc_sm_state[0]), + .I2(sig_pcc_sm_state[1]), + .O(sig_sm_ld_xfer_reg_ns)); + FDRE #( + .INIT(1'b0)) + sig_cmd2dre_valid_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(sig_cmd2dre_valid_i_1_n_0), + .Q(sig_mstr2sf_cmd_valid), + .R(1'b0)); + LUT4 #( + .INIT(16'h000E)) + sig_first_xfer_im0_i_1 + (.I0(sig_first_xfer_im0), + .I1(sig_calc_error_reg0), + .I2(sig_pop_xfer_reg0_out), + .I3(sig_init_reg), + .O(sig_first_xfer_im0_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + sig_first_xfer_im0_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(sig_first_xfer_im0_i_1_n_0), + .Q(sig_first_xfer_im0), + .R(1'b0)); + LUT3 #( + .INIT(8'hFE)) + sig_input_burst_type_reg_i_1 + (.I0(sig_calc_error_pushed), + .I1(sig_sm_pop_input_reg), + .I2(sig_init_reg), + .O(sig_input_cache_type_reg0)); + LUT4 #( + .INIT(16'h0010)) + sig_input_burst_type_reg_i_2 + (.I0(in[38]), + .I1(sig_sm_halt_reg), + .I2(sig_input_reg_empty), + .I3(Q), + .O(sig_calc_error_reg0)); + FDRE #( + .INIT(1'b0)) + sig_input_burst_type_reg_reg + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[16]), + .Q(in[37]), + .R(sig_input_cache_type_reg0)); + FDRE #( + .INIT(1'b0)) + sig_input_eof_reg_reg + (.C(m_axi_mm2s_aclk), + .CE(sig_calc_error_reg0), + .D(out[17]), + .Q(sig_mstr2sf_eof), + .R(sig_input_cache_type_reg0)); + LUT5 #( + .INIT(32'hFFFFFFF2)) + sig_input_reg_empty_i_1 + (.I0(sig_input_reg_empty), + .I1(sig_calc_error_reg0), + .I2(sig_init_reg), + .I3(sig_sm_pop_input_reg), + .I4(sig_calc_error_pushed), + .O(sig_input_reg_empty_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + sig_input_reg_empty_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(sig_input_reg_empty_i_1_n_0), + .Q(sig_input_reg_empty), + .R(1'b0)); + LUT6 #( + .INIT(64'h0000000000FF0202)) + sig_ld_xfer_reg_i_1 + (.I0(sig_pcc_sm_state[2]), + .I1(sig_pcc_sm_state[0]), + .I2(sig_pcc_sm_state[1]), + .I3(sig_xfer_reg_empty), + .I4(sig_ld_xfer_reg), + .I5(sig_init_reg), + .O(sig_ld_xfer_reg_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + sig_ld_xfer_reg_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(sig_ld_xfer_reg_i_1_n_0), + .Q(sig_ld_xfer_reg), + .R(1'b0)); + LUT6 #( + .INIT(64'h000000000000AAAE)) + sig_ld_xfer_reg_tmp_i_1 + (.I0(sig_ld_xfer_reg_tmp), + .I1(sig_pcc_sm_state[2]), + .I2(sig_pcc_sm_state[0]), + .I3(sig_pcc_sm_state[1]), + .I4(sig_pop_xfer_reg0_out), + .I5(sig_init_reg), + .O(sig_ld_xfer_reg_tmp_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + sig_ld_xfer_reg_tmp_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(sig_ld_xfer_reg_tmp_i_1_n_0), + .Q(sig_ld_xfer_reg_tmp), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + sig_mmap_reset_reg_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(SR), + .Q(sig_init_reg), + .R(1'b0)); + LUT5 #( + .INIT(32'h00000001)) + sig_no_btt_residue_ireg1_i_1 + (.I0(sig_btt_residue_slice_im0[1]), + .I1(sig_btt_residue_slice_im0[4]), + .I2(sig_btt_residue_slice_im0[2]), + .I3(sig_btt_residue_slice_im0[5]), + .I4(sig_no_btt_residue_ireg1_i_2_n_0), + .O(sig_no_btt_residue_im0)); + LUT4 #( + .INIT(16'hFFFE)) + sig_no_btt_residue_ireg1_i_2 + (.I0(sig_btt_residue_slice_im0[3]), + .I1(sig_btt_residue_slice_im0[0]), + .I2(sig_btt_residue_slice_im0[7]), + .I3(sig_btt_residue_slice_im0[6]), + .O(sig_no_btt_residue_ireg1_i_2_n_0)); + FDRE #( + .INIT(1'b0)) + sig_no_btt_residue_ireg1_reg + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc1_reg), + .D(sig_no_btt_residue_im0), + .Q(sig_no_btt_residue_ireg1), + .R(sig_init_reg)); + LUT5 #( + .INIT(32'h0000002E)) + sig_parent_done_i_1 + (.I0(sig_parent_done), + .I1(sig_ld_xfer_reg_tmp), + .I2(sig_mstr2data_sequential), + .I3(sig_calc_error_reg0), + .I4(sig_init_reg), + .O(sig_parent_done_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + sig_parent_done_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(sig_parent_done_i_1_n_0), + .Q(sig_parent_done), + .R(1'b0)); + LUT1 #( + .INIT(2'h2)) + \sig_predict_addr_lsh_ireg3[11]_i_2 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[11] ), + .O(\sig_predict_addr_lsh_ireg3[11]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \sig_predict_addr_lsh_ireg3[11]_i_3 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[10] ), + .O(\sig_predict_addr_lsh_ireg3[11]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \sig_predict_addr_lsh_ireg3[11]_i_4 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[9] ), + .O(\sig_predict_addr_lsh_ireg3[11]_i_4_n_0 )); + LUT2 #( + .INIT(4'h6)) + \sig_predict_addr_lsh_ireg3[11]_i_5 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[8] ), + .I1(sig_addr_cntr_incr_ireg2[8]), + .O(\sig_predict_addr_lsh_ireg3[11]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \sig_predict_addr_lsh_ireg3[15]_i_2 + (.I0(p_1_in_0), + .O(\sig_predict_addr_lsh_ireg3[15]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \sig_predict_addr_lsh_ireg3[15]_i_3 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[14] ), + .O(\sig_predict_addr_lsh_ireg3[15]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \sig_predict_addr_lsh_ireg3[15]_i_4 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[13] ), + .O(\sig_predict_addr_lsh_ireg3[15]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \sig_predict_addr_lsh_ireg3[15]_i_5 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[12] ), + .O(\sig_predict_addr_lsh_ireg3[15]_i_5_n_0 )); + LUT2 #( + .INIT(4'h6)) + \sig_predict_addr_lsh_ireg3[3]_i_2 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[3] ), + .I1(sig_addr_cntr_incr_ireg2[3]), + .O(\sig_predict_addr_lsh_ireg3[3]_i_2_n_0 )); + LUT2 #( + .INIT(4'h6)) + \sig_predict_addr_lsh_ireg3[3]_i_3 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[2] ), + .I1(sig_addr_cntr_incr_ireg2[2]), + .O(\sig_predict_addr_lsh_ireg3[3]_i_3_n_0 )); + LUT2 #( + .INIT(4'h6)) + \sig_predict_addr_lsh_ireg3[3]_i_4 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[1] ), + .I1(sig_addr_cntr_incr_ireg2[1]), + .O(\sig_predict_addr_lsh_ireg3[3]_i_4_n_0 )); + LUT2 #( + .INIT(4'h6)) + \sig_predict_addr_lsh_ireg3[3]_i_5 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[0] ), + .I1(sig_addr_cntr_incr_ireg2[0]), + .O(\sig_predict_addr_lsh_ireg3[3]_i_5_n_0 )); + LUT2 #( + .INIT(4'h6)) + \sig_predict_addr_lsh_ireg3[7]_i_2 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[7] ), + .I1(sig_addr_cntr_incr_ireg2[7]), + .O(\sig_predict_addr_lsh_ireg3[7]_i_2_n_0 )); + LUT2 #( + .INIT(4'h6)) + \sig_predict_addr_lsh_ireg3[7]_i_3 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[6] ), + .I1(sig_addr_cntr_incr_ireg2[6]), + .O(\sig_predict_addr_lsh_ireg3[7]_i_3_n_0 )); + LUT2 #( + .INIT(4'h6)) + \sig_predict_addr_lsh_ireg3[7]_i_4 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[5] ), + .I1(sig_addr_cntr_incr_ireg2[5]), + .O(\sig_predict_addr_lsh_ireg3[7]_i_4_n_0 )); + LUT2 #( + .INIT(4'h6)) + \sig_predict_addr_lsh_ireg3[7]_i_5 + (.I0(\sig_addr_cntr_lsh_im0_reg_n_0_[4] ), + .I1(sig_addr_cntr_incr_ireg2[4]), + .O(\sig_predict_addr_lsh_ireg3[7]_i_5_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_predict_addr_lsh_ireg3_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc3_reg), + .D(sig_predict_addr_lsh_im2[0]), + .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[0] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_predict_addr_lsh_ireg3_reg[10] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc3_reg), + .D(sig_predict_addr_lsh_im2[10]), + .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[10] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_predict_addr_lsh_ireg3_reg[11] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc3_reg), + .D(sig_predict_addr_lsh_im2[11]), + .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[11] ), + .R(sig_init_reg)); + CARRY4 \sig_predict_addr_lsh_ireg3_reg[11]_i_1 + (.CI(\sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_0 ), + .CO({\sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_0 ,\sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_1 ,\sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_2 ,\sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({\sig_addr_cntr_lsh_im0_reg_n_0_[11] ,\sig_addr_cntr_lsh_im0_reg_n_0_[10] ,\sig_addr_cntr_lsh_im0_reg_n_0_[9] ,\sig_addr_cntr_lsh_im0_reg_n_0_[8] }), + .O(sig_predict_addr_lsh_im2[11:8]), + .S({\sig_predict_addr_lsh_ireg3[11]_i_2_n_0 ,\sig_predict_addr_lsh_ireg3[11]_i_3_n_0 ,\sig_predict_addr_lsh_ireg3[11]_i_4_n_0 ,\sig_predict_addr_lsh_ireg3[11]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \sig_predict_addr_lsh_ireg3_reg[12] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc3_reg), + .D(sig_predict_addr_lsh_im2[12]), + .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[12] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_predict_addr_lsh_ireg3_reg[13] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc3_reg), + .D(sig_predict_addr_lsh_im2[13]), + .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[13] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_predict_addr_lsh_ireg3_reg[14] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc3_reg), + .D(sig_predict_addr_lsh_im2[14]), + .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[14] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_predict_addr_lsh_ireg3_reg[15] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc3_reg), + .D(sig_predict_addr_lsh_im2[15]), + .Q(sig_predict_addr_lsh_ireg3), + .R(sig_init_reg)); + CARRY4 \sig_predict_addr_lsh_ireg3_reg[15]_i_1 + (.CI(\sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_0 ), + .CO({\NLW_sig_predict_addr_lsh_ireg3_reg[15]_i_1_CO_UNCONNECTED [3],\sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_1 ,\sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_2 ,\sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,\sig_addr_cntr_lsh_im0_reg_n_0_[14] ,\sig_addr_cntr_lsh_im0_reg_n_0_[13] ,\sig_addr_cntr_lsh_im0_reg_n_0_[12] }), + .O(sig_predict_addr_lsh_im2[15:12]), + .S({\sig_predict_addr_lsh_ireg3[15]_i_2_n_0 ,\sig_predict_addr_lsh_ireg3[15]_i_3_n_0 ,\sig_predict_addr_lsh_ireg3[15]_i_4_n_0 ,\sig_predict_addr_lsh_ireg3[15]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \sig_predict_addr_lsh_ireg3_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc3_reg), + .D(sig_predict_addr_lsh_im2[1]), + .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[1] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_predict_addr_lsh_ireg3_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc3_reg), + .D(sig_predict_addr_lsh_im2[2]), + .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[2] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_predict_addr_lsh_ireg3_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc3_reg), + .D(sig_predict_addr_lsh_im2[3]), + .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[3] ), + .R(sig_init_reg)); + CARRY4 \sig_predict_addr_lsh_ireg3_reg[3]_i_1 + (.CI(1'b0), + .CO({\sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_0 ,\sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_1 ,\sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_2 ,\sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({\sig_addr_cntr_lsh_im0_reg_n_0_[3] ,\sig_addr_cntr_lsh_im0_reg_n_0_[2] ,\sig_addr_cntr_lsh_im0_reg_n_0_[1] ,\sig_addr_cntr_lsh_im0_reg_n_0_[0] }), + .O(sig_predict_addr_lsh_im2[3:0]), + .S({\sig_predict_addr_lsh_ireg3[3]_i_2_n_0 ,\sig_predict_addr_lsh_ireg3[3]_i_3_n_0 ,\sig_predict_addr_lsh_ireg3[3]_i_4_n_0 ,\sig_predict_addr_lsh_ireg3[3]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \sig_predict_addr_lsh_ireg3_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc3_reg), + .D(sig_predict_addr_lsh_im2[4]), + .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[4] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_predict_addr_lsh_ireg3_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc3_reg), + .D(sig_predict_addr_lsh_im2[5]), + .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[5] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_predict_addr_lsh_ireg3_reg[6] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc3_reg), + .D(sig_predict_addr_lsh_im2[6]), + .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[6] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_predict_addr_lsh_ireg3_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc3_reg), + .D(sig_predict_addr_lsh_im2[7]), + .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[7] ), + .R(sig_init_reg)); + CARRY4 \sig_predict_addr_lsh_ireg3_reg[7]_i_1 + (.CI(\sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_0 ), + .CO({\sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_0 ,\sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_1 ,\sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_2 ,\sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({\sig_addr_cntr_lsh_im0_reg_n_0_[7] ,\sig_addr_cntr_lsh_im0_reg_n_0_[6] ,\sig_addr_cntr_lsh_im0_reg_n_0_[5] ,\sig_addr_cntr_lsh_im0_reg_n_0_[4] }), + .O(sig_predict_addr_lsh_im2[7:4]), + .S({\sig_predict_addr_lsh_ireg3[7]_i_2_n_0 ,\sig_predict_addr_lsh_ireg3[7]_i_3_n_0 ,\sig_predict_addr_lsh_ireg3[7]_i_4_n_0 ,\sig_predict_addr_lsh_ireg3[7]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \sig_predict_addr_lsh_ireg3_reg[8] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc3_reg), + .D(sig_predict_addr_lsh_im2[8]), + .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[8] ), + .R(sig_init_reg)); + FDRE #( + .INIT(1'b0)) + \sig_predict_addr_lsh_ireg3_reg[9] + (.C(m_axi_mm2s_aclk), + .CE(sig_sm_ld_calc3_reg), + .D(sig_predict_addr_lsh_im2[9]), + .Q(\sig_predict_addr_lsh_ireg3_reg_n_0_[9] ), + .R(sig_init_reg)); + LUT4 #( + .INIT(16'hA181)) + sig_sm_halt_reg_i_1 + (.I0(sig_pcc_sm_state[2]), + .I1(sig_pcc_sm_state[0]), + .I2(sig_pcc_sm_state[1]), + .I3(sig_calc_error_pushed), + .O(sig_sm_halt_ns)); + FDSE #( + .INIT(1'b0)) + sig_sm_halt_reg_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(sig_sm_halt_ns), + .Q(sig_sm_halt_reg), + .S(sig_init_reg)); + LUT6 #( + .INIT(64'h0008000800083008)) + sig_sm_ld_calc1_reg_i_1 + (.I0(sig_calc_error_reg0), + .I1(sig_pcc_sm_state[0]), + .I2(sig_pcc_sm_state[2]), + .I3(sig_pcc_sm_state[1]), + .I4(sig_parent_done), + .I5(sig_calc_error_pushed), + .O(sig_sm_ld_calc1_reg_ns)); + FDRE #( + .INIT(1'b0)) + sig_sm_ld_calc1_reg_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(sig_sm_ld_calc1_reg_ns), + .Q(sig_sm_ld_calc1_reg), + .R(sig_init_reg)); + LUT3 #( + .INIT(8'h02)) + sig_sm_ld_calc2_reg_i_1 + (.I0(sig_pcc_sm_state[1]), + .I1(sig_pcc_sm_state[2]), + .I2(sig_pcc_sm_state[0]), + .O(sig_sm_ld_calc2_reg_ns)); + FDRE #( + .INIT(1'b0)) + sig_sm_ld_calc2_reg_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(sig_sm_ld_calc2_reg_ns), + .Q(sig_sm_ld_calc2_reg), + .R(sig_init_reg)); + LUT3 #( + .INIT(8'h40)) + sig_sm_ld_calc3_reg_i_1 + (.I0(sig_pcc_sm_state[2]), + .I1(sig_pcc_sm_state[0]), + .I2(sig_pcc_sm_state[1]), + .O(sig_sm_ld_calc3_reg_ns)); + FDRE #( + .INIT(1'b0)) + sig_sm_ld_calc3_reg_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(sig_sm_ld_calc3_reg_ns), + .Q(sig_sm_ld_calc3_reg), + .R(sig_init_reg)); + LUT5 #( + .INIT(32'h00200000)) + sig_sm_pop_input_reg_i_1 + (.I0(sig_pcc_sm_state[2]), + .I1(sig_pcc_sm_state[0]), + .I2(sig_parent_done), + .I3(sig_calc_error_pushed), + .I4(sig_pcc_sm_state[1]), + .O(sig_sm_pop_input_reg_ns)); + FDRE #( + .INIT(1'b0)) + sig_sm_pop_input_reg_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(sig_sm_pop_input_reg_ns), + .Q(sig_sm_pop_input_reg), + .R(sig_init_reg)); + LUT4 #( + .INIT(16'hFF3A)) + sig_xfer_reg_empty_i_1 + (.I0(sig_pop_xfer_reg0_out), + .I1(sig_ld_xfer_reg), + .I2(sig_xfer_reg_empty), + .I3(sig_init_reg), + .O(sig_xfer_reg_empty_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + sig_xfer_reg_empty_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(sig_xfer_reg_empty_i_1_n_0), + .Q(sig_xfer_reg_empty), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "axi_datamover_rd_sf" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_rd_sf + (out, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram , + sig_wr_fifo, + \INFERRED_GEN.cnt_i_reg[1] , + sig_sf_allow_addr_req, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 , + \gc1.count_reg[7] , + sig_inhibit_rdy_n, + DIN, + \sig_user_skid_reg_reg[0] , + dm2linebuf_mm2s_tdata, + m_axi_mm2s_aclk, + E, + SR, + m_axi_mm2s_rdata, + DIBDI, + in, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_posted_to_axi_2_reg, + prmry_resetn_i_reg, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1 , + sig_last_mmap_dbeat_reg_reg, + sig_mstr2sf_cmd_valid, + ram_full_i_reg, + sig_init_reg2, + sig_init_reg, + ram_full_i_reg_0); + output out; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; + output sig_wr_fifo; + output \INFERRED_GEN.cnt_i_reg[1] ; + output sig_sf_allow_addr_req; + output \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; + output \gc1.count_reg[7] ; + output sig_inhibit_rdy_n; + output [0:0]DIN; + output \sig_user_skid_reg_reg[0] ; + output [31:0]dm2linebuf_mm2s_tdata; + input m_axi_mm2s_aclk; + input [0:0]E; + input [0:0]SR; + input [63:0]m_axi_mm2s_rdata; + input [1:0]DIBDI; + input [0:0]in; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_posted_to_axi_2_reg; + input prmry_resetn_i_reg; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1 ; + input sig_last_mmap_dbeat_reg_reg; + input sig_mstr2sf_cmd_valid; + input ram_full_i_reg; + input sig_init_reg2; + input sig_init_reg; + input [0:0]ram_full_i_reg_0; + + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; + wire [1:0]DIBDI; + wire [0:0]DIN; + wire [0:0]E; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1 ; + wire \INFERRED_GEN.cnt_i_reg[1] ; + wire I_DATA_FIFO_n_3; + wire I_DATA_FIFO_n_4; + wire I_DATA_FIFO_n_6; + wire \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO_n_2 ; + wire [0:0]SR; + wire [31:0]dm2linebuf_mm2s_tdata; + wire \gc1.count_reg[7] ; + wire [0:0]in; + wire lsig_cmd_loaded; + wire m_axi_mm2s_aclk; + wire [63:0]m_axi_mm2s_rdata; + wire out; + wire prmry_resetn_i_reg; + wire ram_full_i_reg; + wire [0:0]ram_full_i_reg_0; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire [65:65]sig_data_fifo_data_out; + wire sig_inhibit_rdy_n; + wire sig_init_reg; + wire sig_init_reg2; + wire sig_last_mmap_dbeat_reg_reg; + wire sig_mstr2sf_cmd_valid; + wire sig_ok_to_post_rd_addr_i_4_n_0; + wire sig_posted_to_axi_2_reg; + wire sig_rd_empty; + wire sig_sf_allow_addr_req; + wire \sig_token_cntr[0]_i_1_n_0 ; + wire \sig_token_cntr[1]_i_1_n_0 ; + wire \sig_token_cntr[2]_i_1_n_0 ; + wire \sig_token_cntr[3]_i_1_n_0 ; + wire \sig_token_cntr[3]_i_2_n_0 ; + wire [3:0]sig_token_cntr_reg__0; + wire \sig_user_skid_reg_reg[0] ; + wire sig_wr_fifo; + + FDRE #( + .INIT(1'b0)) + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO_n_2 ), + .Q(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(I_DATA_FIFO_n_4), + .Q(lsig_cmd_loaded), + .R(SR)); + Arty_Z7_20_axi_vdma_0_0_axi_datamover_sfifo_autord I_DATA_FIFO + (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ), + .DIBDI(DIBDI), + .DIN(DIN), + .DOBDO(sig_data_fifo_data_out), + .E(E), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1 ), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .\INCLUDE_UNPACKING.lsig_cmd_loaded_reg (I_DATA_FIFO_n_4), + .\INFERRED_GEN.cnt_i_reg[2] (I_DATA_FIFO_n_6), + .Q(sig_rd_empty), + .SR(SR), + .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), + .\gc1.count_reg[7] (\gc1.count_reg[7] ), + .lsig_cmd_loaded(lsig_cmd_loaded), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .m_axi_mm2s_rdata(m_axi_mm2s_rdata), + .out(out), + .ram_full_i_reg(ram_full_i_reg), + .ram_full_i_reg_0(ram_full_i_reg_0), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_ok_to_post_rd_addr_reg(I_DATA_FIFO_n_3), + .sig_posted_to_axi_2_reg(sig_posted_to_axi_2_reg), + .\sig_token_cntr_reg[0] (sig_ok_to_post_rd_addr_i_4_n_0), + .\sig_token_cntr_reg[3] (sig_token_cntr_reg__0), + .\sig_user_skid_reg_reg[0] (\sig_user_skid_reg_reg[0] )); + Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized3 \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO + (.DOBDO(sig_data_fifo_data_out), + .FIFO_Full_reg(sig_wr_fifo), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] (\OMIT_DRE_CNTL.I_DRE_CNTL_FIFO_n_2 ), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1 (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1 ), + .\INCLUDE_UNPACKING.lsig_cmd_loaded_reg (I_DATA_FIFO_n_6), + .\INFERRED_GEN.cnt_i_reg[1] (\INFERRED_GEN.cnt_i_reg[1] ), + .\INFERRED_GEN.cnt_i_reg[1]_0 (sig_inhibit_rdy_n), + .Q(sig_rd_empty), + .SR(SR), + .in(in), + .lsig_cmd_loaded(lsig_cmd_loaded), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .prmry_resetn_i_reg(prmry_resetn_i_reg), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_init_reg(sig_init_reg), + .sig_init_reg2(sig_init_reg2), + .sig_mstr2sf_cmd_valid(sig_mstr2sf_cmd_valid)); + (* SOFT_HLUTNM = "soft_lutpair127" *) + LUT2 #( + .INIT(4'h1)) + sig_ok_to_post_rd_addr_i_4 + (.I0(sig_token_cntr_reg__0[0]), + .I1(sig_token_cntr_reg__0[1]), + .O(sig_ok_to_post_rd_addr_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + sig_ok_to_post_rd_addr_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(I_DATA_FIFO_n_3), + .Q(sig_sf_allow_addr_req), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair127" *) + LUT1 #( + .INIT(2'h1)) + \sig_token_cntr[0]_i_1 + (.I0(sig_token_cntr_reg__0[0]), + .O(\sig_token_cntr[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAAFF55005500B8FF)) + \sig_token_cntr[1]_i_1 + (.I0(sig_posted_to_axi_2_reg), + .I1(sig_token_cntr_reg__0[2]), + .I2(sig_token_cntr_reg__0[3]), + .I3(sig_last_mmap_dbeat_reg_reg), + .I4(sig_token_cntr_reg__0[1]), + .I5(sig_token_cntr_reg__0[0]), + .O(\sig_token_cntr[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'h99CCCCCCCCCC7433)) + \sig_token_cntr[2]_i_1 + (.I0(sig_posted_to_axi_2_reg), + .I1(sig_token_cntr_reg__0[2]), + .I2(sig_token_cntr_reg__0[3]), + .I3(sig_last_mmap_dbeat_reg_reg), + .I4(sig_token_cntr_reg__0[1]), + .I5(sig_token_cntr_reg__0[0]), + .O(\sig_token_cntr[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'h55565557AAAAAAA8)) + \sig_token_cntr[3]_i_1 + (.I0(sig_posted_to_axi_2_reg), + .I1(sig_token_cntr_reg__0[1]), + .I2(sig_token_cntr_reg__0[0]), + .I3(sig_token_cntr_reg__0[2]), + .I4(sig_token_cntr_reg__0[3]), + .I5(sig_last_mmap_dbeat_reg_reg), + .O(\sig_token_cntr[3]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFF00EE017F80EE01)) + \sig_token_cntr[3]_i_2 + (.I0(sig_token_cntr_reg__0[0]), + .I1(sig_token_cntr_reg__0[1]), + .I2(sig_last_mmap_dbeat_reg_reg), + .I3(sig_token_cntr_reg__0[3]), + .I4(sig_token_cntr_reg__0[2]), + .I5(sig_posted_to_axi_2_reg), + .O(\sig_token_cntr[3]_i_2_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_token_cntr_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(\sig_token_cntr[3]_i_1_n_0 ), + .D(\sig_token_cntr[0]_i_1_n_0 ), + .Q(sig_token_cntr_reg__0[0]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \sig_token_cntr_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(\sig_token_cntr[3]_i_1_n_0 ), + .D(\sig_token_cntr[1]_i_1_n_0 ), + .Q(sig_token_cntr_reg__0[1]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \sig_token_cntr_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(\sig_token_cntr[3]_i_1_n_0 ), + .D(\sig_token_cntr[2]_i_1_n_0 ), + .Q(sig_token_cntr_reg__0[2]), + .R(SR)); + FDSE #( + .INIT(1'b0)) + \sig_token_cntr_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(\sig_token_cntr[3]_i_1_n_0 ), + .D(\sig_token_cntr[3]_i_2_n_0 ), + .Q(sig_token_cntr_reg__0[3]), + .S(SR)); +endmodule + +(* ORIG_REF_NAME = "axi_datamover_rd_status_cntl" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_rd_status_cntl + (sig_rsc2stat_status_valid, + sig_rsc2data_ready, + sig_rd_sts_slverr_reg_reg_0, + sig_inhibit_rdy_n_reg, + sig_push_rd_sts_reg, + sig_rd_sts_reg_full0, + m_axi_mm2s_aclk, + sig_coelsc_reg_full_reg, + sig_rd_sts_interr_reg0, + sig_rd_sts_slverr_reg0, + sig_data2rsc_decerr); + output sig_rsc2stat_status_valid; + output sig_rsc2data_ready; + output [2:0]sig_rd_sts_slverr_reg_reg_0; + input sig_inhibit_rdy_n_reg; + input sig_push_rd_sts_reg; + input sig_rd_sts_reg_full0; + input m_axi_mm2s_aclk; + input sig_coelsc_reg_full_reg; + input sig_rd_sts_interr_reg0; + input sig_rd_sts_slverr_reg0; + input sig_data2rsc_decerr; + + wire m_axi_mm2s_aclk; + wire sig_coelsc_reg_full_reg; + wire sig_data2rsc_decerr; + wire sig_inhibit_rdy_n_reg; + wire sig_push_rd_sts_reg; + wire sig_rd_sts_decerr_reg0; + wire sig_rd_sts_interr_reg0; + wire sig_rd_sts_reg_full0; + wire sig_rd_sts_slverr_reg0; + wire [2:0]sig_rd_sts_slverr_reg_reg_0; + wire sig_rsc2data_ready; + wire sig_rsc2stat_status_valid; + + LUT2 #( + .INIT(4'hE)) + sig_rd_sts_decerr_reg_i_1 + (.I0(sig_rd_sts_slverr_reg_reg_0[1]), + .I1(sig_data2rsc_decerr), + .O(sig_rd_sts_decerr_reg0)); + FDRE #( + .INIT(1'b0)) + sig_rd_sts_decerr_reg_reg + (.C(m_axi_mm2s_aclk), + .CE(sig_push_rd_sts_reg), + .D(sig_rd_sts_decerr_reg0), + .Q(sig_rd_sts_slverr_reg_reg_0[1]), + .R(sig_inhibit_rdy_n_reg)); + FDRE #( + .INIT(1'b0)) + sig_rd_sts_interr_reg_reg + (.C(m_axi_mm2s_aclk), + .CE(sig_push_rd_sts_reg), + .D(sig_rd_sts_interr_reg0), + .Q(sig_rd_sts_slverr_reg_reg_0[0]), + .R(sig_inhibit_rdy_n_reg)); + FDSE #( + .INIT(1'b0)) + sig_rd_sts_reg_empty_reg + (.C(m_axi_mm2s_aclk), + .CE(sig_push_rd_sts_reg), + .D(sig_coelsc_reg_full_reg), + .Q(sig_rsc2data_ready), + .S(sig_inhibit_rdy_n_reg)); + FDRE #( + .INIT(1'b0)) + sig_rd_sts_reg_full_reg + (.C(m_axi_mm2s_aclk), + .CE(sig_push_rd_sts_reg), + .D(sig_rd_sts_reg_full0), + .Q(sig_rsc2stat_status_valid), + .R(sig_inhibit_rdy_n_reg)); + FDRE #( + .INIT(1'b0)) + sig_rd_sts_slverr_reg_reg + (.C(m_axi_mm2s_aclk), + .CE(sig_push_rd_sts_reg), + .D(sig_rd_sts_slverr_reg0), + .Q(sig_rd_sts_slverr_reg_reg_0[2]), + .R(sig_inhibit_rdy_n_reg)); +endmodule + +(* ORIG_REF_NAME = "axi_datamover_rddata_cntl" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_rddata_cntl + (sig_next_calc_error_reg, + \sig_addr_posted_cntr_reg[2]_0 , + sig_data2addr_stop_req, + sig_halt_reg_dly3, + sig_data2rsc_decerr, + sig_addr_posted_cntr, + sig_rd_sts_reg_full0, + sig_rd_sts_reg_empty_reg, + sig_rd_sts_interr_reg0, + sig_rd_sts_slverr_reg0, + sig_wr_fifo, + DIBDI, + \count_reg[0] , + E, + ram_full_i_reg, + m_axi_mm2s_rready, + sig_push_rd_sts_reg, + SR, + m_axi_mm2s_aclk, + m_axi_mm2s_rlast, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_rsc2data_ready, + sig_rd_sts_slverr_reg_reg, + sig_mstr2data_cmd_valid, + sig_rsc2stat_status_valid, + FIFO_Full_reg, + sig_inhibit_rdy_n, + ram_empty_fb_i_reg, + m_axi_mm2s_rvalid, + ram_full_i_reg_0, + out, + m_axi_mm2s_rresp, + in, + sig_init_reg2, + sig_init_reg, + sig_rst2all_stop_request, + sig_posted_to_axi_reg); + output sig_next_calc_error_reg; + output \sig_addr_posted_cntr_reg[2]_0 ; + output sig_data2addr_stop_req; + output sig_halt_reg_dly3; + output sig_data2rsc_decerr; + output [2:0]sig_addr_posted_cntr; + output sig_rd_sts_reg_full0; + output sig_rd_sts_reg_empty_reg; + output sig_rd_sts_interr_reg0; + output sig_rd_sts_slverr_reg0; + output sig_wr_fifo; + output [1:0]DIBDI; + output [0:0]\count_reg[0] ; + output [0:0]E; + output ram_full_i_reg; + output m_axi_mm2s_rready; + output sig_push_rd_sts_reg; + input [0:0]SR; + input m_axi_mm2s_aclk; + input m_axi_mm2s_rlast; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_rsc2data_ready; + input [1:0]sig_rd_sts_slverr_reg_reg; + input sig_mstr2data_cmd_valid; + input sig_rsc2stat_status_valid; + input FIFO_Full_reg; + input sig_inhibit_rdy_n; + input ram_empty_fb_i_reg; + input m_axi_mm2s_rvalid; + input ram_full_i_reg_0; + input out; + input [1:0]m_axi_mm2s_rresp; + input [8:0]in; + input sig_init_reg2; + input sig_init_reg; + input sig_rst2all_stop_request; + input sig_posted_to_axi_reg; + + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_8_n_0 ; + wire [1:0]DIBDI; + wire [0:0]E; + wire FIFO_Full_reg; + wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_0 ; + wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_1 ; + wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_10 ; + wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_16 ; + wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_17 ; + wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_18 ; + wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_2 ; + wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_9 ; + wire [0:0]SR; + wire [0:0]\count_reg[0] ; + wire [8:0]in; + wire m_axi_mm2s_aclk; + wire m_axi_mm2s_rlast; + wire m_axi_mm2s_rready; + wire m_axi_mm2s_rready_INST_0_i_1_n_0; + wire [1:0]m_axi_mm2s_rresp; + wire m_axi_mm2s_rvalid; + wire out; + wire [4:0]p_0_in; + wire ram_empty_fb_i_reg; + wire ram_full_fb_i_i_4_n_0; + wire ram_full_i_reg; + wire ram_full_i_reg_0; + wire [2:0]sig_addr_posted_cntr; + wire \sig_addr_posted_cntr[0]_i_1_n_0 ; + wire \sig_addr_posted_cntr[1]_i_1_n_0 ; + wire \sig_addr_posted_cntr[2]_i_1_n_0 ; + wire \sig_addr_posted_cntr_reg[2]_0 ; + wire sig_cmd_cmplt_last_dbeat; + wire [35:32]sig_cmd_fifo_data_out; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_coelsc_decerr_reg0; + wire sig_coelsc_interr_reg0; + wire sig_coelsc_reg_full_i_1_n_0; + wire sig_coelsc_slverr_reg0; + wire sig_data2addr_stop_req; + wire sig_data2rsc_calc_err; + wire sig_data2rsc_decerr; + wire sig_data2rsc_slverr; + wire sig_data2rsc_valid; + wire \sig_dbeat_cntr[7]_i_3_n_0 ; + wire \sig_dbeat_cntr[7]_i_4_n_0 ; + wire [7:0]sig_dbeat_cntr_reg__0; + wire sig_dqual_reg_empty; + wire sig_dqual_reg_full; + wire sig_halt_reg_dly1; + wire sig_halt_reg_dly2; + wire sig_halt_reg_dly3; + wire sig_halt_reg_i_1_n_0; + wire sig_inhibit_rdy_n; + wire sig_init_reg; + wire sig_init_reg2; + wire sig_last_dbeat; + wire sig_last_dbeat_i_2_n_0; + wire sig_last_mmap_dbeat; + wire sig_ld_new_cmd_reg; + wire sig_ld_new_cmd_reg_i_1_n_0; + wire sig_mstr2data_cmd_valid; + wire sig_next_calc_error_reg; + wire sig_next_cmd_cmplt_reg; + wire sig_next_eof_reg; + wire sig_next_sequential_reg; + wire sig_posted_to_axi_reg; + wire sig_push_coelsc_reg; + wire sig_push_dqual_reg; + wire sig_push_rd_sts_reg; + wire sig_rd_sts_interr_reg0; + wire sig_rd_sts_reg_empty_reg; + wire sig_rd_sts_reg_full0; + wire sig_rd_sts_slverr_reg0; + wire [1:0]sig_rd_sts_slverr_reg_reg; + wire sig_rsc2data_ready; + wire sig_rsc2stat_status_valid; + wire sig_rst2all_stop_request; + wire sig_wr_fifo; + + LUT5 #( + .INIT(32'h000000F2)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_2 + (.I0(m_axi_mm2s_rvalid), + .I1(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_18 ), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_8_n_0 ), + .I3(ram_full_i_reg_0), + .I4(out), + .O(E)); + LUT6 #( + .INIT(64'hFFFF004000400040)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_5 + (.I0(m_axi_mm2s_rready_INST_0_i_1_n_0), + .I1(sig_data2addr_stop_req), + .I2(sig_dqual_reg_full), + .I3(sig_next_calc_error_reg), + .I4(sig_next_cmd_cmplt_reg), + .I5(m_axi_mm2s_rlast), + .O(DIBDI[1])); + LUT6 #( + .INIT(64'hFFFF004000400040)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_6 + (.I0(m_axi_mm2s_rready_INST_0_i_1_n_0), + .I1(sig_data2addr_stop_req), + .I2(sig_dqual_reg_full), + .I3(sig_next_calc_error_reg), + .I4(sig_next_eof_reg), + .I5(m_axi_mm2s_rlast), + .O(DIBDI[0])); + LUT6 #( + .INIT(64'h4040404040404000)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_8 + (.I0(sig_next_calc_error_reg), + .I1(sig_dqual_reg_full), + .I2(sig_data2addr_stop_req), + .I3(sig_addr_posted_cntr[0]), + .I4(sig_addr_posted_cntr[2]), + .I5(sig_addr_posted_cntr[1]), + .O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_8_n_0 )); + Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized2 \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO + (.D({\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_0 ,\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_1 ,\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_2 ,p_0_in}), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_18 ), + .E(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_17 ), + .FIFO_Full_reg(FIFO_Full_reg), + .Q(sig_dbeat_cntr_reg__0), + .SR(SR), + .in(in), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .m_axi_mm2s_rlast(m_axi_mm2s_rlast), + .m_axi_mm2s_rvalid(m_axi_mm2s_rvalid), + .out(sig_cmd_fifo_data_out), + .ram_full_i_reg(ram_full_i_reg_0), + .sel(sig_wr_fifo), + .\sig_addr_posted_cntr_reg[0] (sig_addr_posted_cntr[0]), + .\sig_addr_posted_cntr_reg[1] (sig_addr_posted_cntr[1]), + .\sig_addr_posted_cntr_reg[2] (sig_addr_posted_cntr[2]), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_data2rsc_valid(sig_data2rsc_valid), + .\sig_dbeat_cntr_reg[0] (\sig_dbeat_cntr[7]_i_3_n_0 ), + .\sig_dbeat_cntr_reg[3] (sig_last_dbeat_i_2_n_0), + .\sig_dbeat_cntr_reg[5] (\sig_dbeat_cntr[7]_i_4_n_0 ), + .sig_dqual_reg_empty(sig_dqual_reg_empty), + .sig_dqual_reg_empty_reg(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_10 ), + .sig_dqual_reg_full(sig_dqual_reg_full), + .sig_halt_reg_reg(sig_data2addr_stop_req), + .sig_inhibit_rdy_n(sig_inhibit_rdy_n), + .sig_init_reg(sig_init_reg), + .sig_init_reg2(sig_init_reg2), + .sig_last_dbeat(sig_last_dbeat), + .sig_last_dbeat_reg(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_16 ), + .sig_mstr2data_cmd_valid(sig_mstr2data_cmd_valid), + .sig_next_calc_error_reg_reg(sig_next_calc_error_reg), + .sig_next_cmd_cmplt_reg_reg(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_9 ), + .sig_next_sequential_reg(sig_next_sequential_reg), + .sig_push_dqual_reg(sig_push_dqual_reg), + .sig_rsc2stat_status_valid(sig_rsc2stat_status_valid)); + LUT2 #( + .INIT(4'h6)) + \count[7]_i_1 + (.I0(E), + .I1(ram_empty_fb_i_reg), + .O(\count_reg[0] )); + LUT6 #( + .INIT(64'h0000000000000D00)) + m_axi_mm2s_rready_INST_0 + (.I0(ram_full_i_reg_0), + .I1(sig_data2addr_stop_req), + .I2(sig_data2rsc_valid), + .I3(sig_dqual_reg_full), + .I4(sig_next_calc_error_reg), + .I5(m_axi_mm2s_rready_INST_0_i_1_n_0), + .O(m_axi_mm2s_rready)); + (* SOFT_HLUTNM = "soft_lutpair163" *) + LUT3 #( + .INIT(8'h01)) + m_axi_mm2s_rready_INST_0_i_1 + (.I0(sig_addr_posted_cntr[1]), + .I1(sig_addr_posted_cntr[2]), + .I2(sig_addr_posted_cntr[0]), + .O(m_axi_mm2s_rready_INST_0_i_1_n_0)); + LUT6 #( + .INIT(64'h0010001100100010)) + ram_full_fb_i_i_2 + (.I0(ram_full_i_reg_0), + .I1(ram_full_fb_i_i_4_n_0), + .I2(sig_data2addr_stop_req), + .I3(m_axi_mm2s_rready_INST_0_i_1_n_0), + .I4(sig_data2rsc_valid), + .I5(m_axi_mm2s_rvalid), + .O(ram_full_i_reg)); + (* SOFT_HLUTNM = "soft_lutpair165" *) + LUT2 #( + .INIT(4'hB)) + ram_full_fb_i_i_4 + (.I0(sig_next_calc_error_reg), + .I1(sig_dqual_reg_full), + .O(ram_full_fb_i_i_4_n_0)); + (* SOFT_HLUTNM = "soft_lutpair162" *) + LUT5 #( + .INIT(32'hB9996662)) + \sig_addr_posted_cntr[0]_i_1 + (.I0(sig_posted_to_axi_reg), + .I1(\sig_addr_posted_cntr_reg[2]_0 ), + .I2(sig_addr_posted_cntr[2]), + .I3(sig_addr_posted_cntr[1]), + .I4(sig_addr_posted_cntr[0]), + .O(\sig_addr_posted_cntr[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair163" *) + LUT5 #( + .INIT(32'hAADAA4AA)) + \sig_addr_posted_cntr[1]_i_1 + (.I0(sig_addr_posted_cntr[1]), + .I1(sig_addr_posted_cntr[2]), + .I2(sig_addr_posted_cntr[0]), + .I3(\sig_addr_posted_cntr_reg[2]_0 ), + .I4(sig_posted_to_axi_reg), + .O(\sig_addr_posted_cntr[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair162" *) + LUT5 #( + .INIT(32'hCCECC8CC)) + \sig_addr_posted_cntr[2]_i_1 + (.I0(sig_addr_posted_cntr[1]), + .I1(sig_addr_posted_cntr[2]), + .I2(sig_addr_posted_cntr[0]), + .I3(\sig_addr_posted_cntr_reg[2]_0 ), + .I4(sig_posted_to_axi_reg), + .O(\sig_addr_posted_cntr[2]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_addr_posted_cntr_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\sig_addr_posted_cntr[0]_i_1_n_0 ), + .Q(sig_addr_posted_cntr[0]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \sig_addr_posted_cntr_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\sig_addr_posted_cntr[1]_i_1_n_0 ), + .Q(sig_addr_posted_cntr[1]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \sig_addr_posted_cntr_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\sig_addr_posted_cntr[2]_i_1_n_0 ), + .Q(sig_addr_posted_cntr[2]), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair164" *) + LUT4 #( + .INIT(16'hEAAA)) + sig_coelsc_decerr_reg_i_1 + (.I0(sig_data2rsc_decerr), + .I1(m_axi_mm2s_rvalid), + .I2(m_axi_mm2s_rresp[1]), + .I3(m_axi_mm2s_rresp[0]), + .O(sig_coelsc_decerr_reg0)); + FDRE #( + .INIT(1'b0)) + sig_coelsc_decerr_reg_reg + (.C(m_axi_mm2s_aclk), + .CE(sig_push_coelsc_reg), + .D(sig_coelsc_decerr_reg0), + .Q(sig_data2rsc_decerr), + .R(sig_coelsc_reg_full_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair167" *) + LUT2 #( + .INIT(4'hE)) + sig_coelsc_interr_reg_i_1 + (.I0(sig_data2rsc_calc_err), + .I1(sig_next_calc_error_reg), + .O(sig_coelsc_interr_reg0)); + FDRE #( + .INIT(1'b0)) + sig_coelsc_interr_reg_reg + (.C(m_axi_mm2s_aclk), + .CE(sig_push_coelsc_reg), + .D(sig_coelsc_interr_reg0), + .Q(sig_data2rsc_calc_err), + .R(sig_coelsc_reg_full_i_1_n_0)); + LUT5 #( + .INIT(32'h7000FFFF)) + sig_coelsc_reg_full_i_1 + (.I0(sig_ld_new_cmd_reg), + .I1(sig_next_calc_error_reg), + .I2(sig_data2rsc_valid), + .I3(sig_rsc2data_ready), + .I4(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .O(sig_coelsc_reg_full_i_1_n_0)); + LUT3 #( + .INIT(8'hEA)) + sig_coelsc_reg_full_i_2 + (.I0(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_10 ), + .I1(sig_next_calc_error_reg), + .I2(sig_ld_new_cmd_reg), + .O(sig_push_coelsc_reg)); + (* SOFT_HLUTNM = "soft_lutpair165" *) + LUT3 #( + .INIT(8'hEA)) + sig_coelsc_reg_full_i_3 + (.I0(sig_next_calc_error_reg), + .I1(sig_next_cmd_cmplt_reg), + .I2(m_axi_mm2s_rlast), + .O(sig_cmd_cmplt_last_dbeat)); + FDRE #( + .INIT(1'b0)) + sig_coelsc_reg_full_reg + (.C(m_axi_mm2s_aclk), + .CE(sig_push_coelsc_reg), + .D(sig_cmd_cmplt_last_dbeat), + .Q(sig_data2rsc_valid), + .R(sig_coelsc_reg_full_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair164" *) + LUT4 #( + .INIT(16'hAAEA)) + sig_coelsc_slverr_reg_i_1 + (.I0(sig_data2rsc_slverr), + .I1(m_axi_mm2s_rvalid), + .I2(m_axi_mm2s_rresp[1]), + .I3(m_axi_mm2s_rresp[0]), + .O(sig_coelsc_slverr_reg0)); + FDRE #( + .INIT(1'b0)) + sig_coelsc_slverr_reg_reg + (.C(m_axi_mm2s_aclk), + .CE(sig_push_coelsc_reg), + .D(sig_coelsc_slverr_reg0), + .Q(sig_data2rsc_slverr), + .R(sig_coelsc_reg_full_i_1_n_0)); + LUT4 #( + .INIT(16'h0001)) + \sig_dbeat_cntr[7]_i_3 + (.I0(sig_dbeat_cntr_reg__0[0]), + .I1(sig_dbeat_cntr_reg__0[1]), + .I2(sig_dbeat_cntr_reg__0[3]), + .I3(sig_dbeat_cntr_reg__0[2]), + .O(\sig_dbeat_cntr[7]_i_3_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \sig_dbeat_cntr[7]_i_4 + (.I0(sig_dbeat_cntr_reg__0[5]), + .I1(sig_dbeat_cntr_reg__0[4]), + .I2(sig_dbeat_cntr_reg__0[7]), + .I3(sig_dbeat_cntr_reg__0[6]), + .O(\sig_dbeat_cntr[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_dbeat_cntr_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_17 ), + .D(p_0_in[0]), + .Q(sig_dbeat_cntr_reg__0[0]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \sig_dbeat_cntr_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_17 ), + .D(p_0_in[1]), + .Q(sig_dbeat_cntr_reg__0[1]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \sig_dbeat_cntr_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_17 ), + .D(p_0_in[2]), + .Q(sig_dbeat_cntr_reg__0[2]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \sig_dbeat_cntr_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_17 ), + .D(p_0_in[3]), + .Q(sig_dbeat_cntr_reg__0[3]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \sig_dbeat_cntr_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_17 ), + .D(p_0_in[4]), + .Q(sig_dbeat_cntr_reg__0[4]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \sig_dbeat_cntr_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_17 ), + .D(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_2 ), + .Q(sig_dbeat_cntr_reg__0[5]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \sig_dbeat_cntr_reg[6] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_17 ), + .D(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_1 ), + .Q(sig_dbeat_cntr_reg__0[6]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \sig_dbeat_cntr_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_17 ), + .D(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_0 ), + .Q(sig_dbeat_cntr_reg__0[7]), + .R(SR)); + FDSE #( + .INIT(1'b0)) + sig_dqual_reg_empty_reg + (.C(m_axi_mm2s_aclk), + .CE(sig_push_dqual_reg), + .D(1'b0), + .Q(sig_dqual_reg_empty), + .S(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_9 )); + FDRE #( + .INIT(1'b0)) + sig_dqual_reg_full_reg + (.C(m_axi_mm2s_aclk), + .CE(sig_push_dqual_reg), + .D(sig_push_dqual_reg), + .Q(sig_dqual_reg_full), + .R(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_9 )); + FDRE #( + .INIT(1'b0)) + sig_halt_reg_dly1_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(sig_data2addr_stop_req), + .Q(sig_halt_reg_dly1), + .R(SR)); + FDRE #( + .INIT(1'b0)) + sig_halt_reg_dly2_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(sig_halt_reg_dly1), + .Q(sig_halt_reg_dly2), + .R(SR)); + FDRE #( + .INIT(1'b0)) + sig_halt_reg_dly3_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(sig_halt_reg_dly2), + .Q(sig_halt_reg_dly3), + .R(SR)); + LUT2 #( + .INIT(4'hE)) + sig_halt_reg_i_1 + (.I0(sig_rst2all_stop_request), + .I1(sig_data2addr_stop_req), + .O(sig_halt_reg_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + sig_halt_reg_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(sig_halt_reg_i_1_n_0), + .Q(sig_data2addr_stop_req), + .R(SR)); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFDFF)) + sig_last_dbeat_i_2 + (.I0(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_10 ), + .I1(sig_dbeat_cntr_reg__0[3]), + .I2(sig_dbeat_cntr_reg__0[2]), + .I3(sig_dbeat_cntr_reg__0[0]), + .I4(sig_dbeat_cntr_reg__0[1]), + .I5(\sig_dbeat_cntr[7]_i_4_n_0 ), + .O(sig_last_dbeat_i_2_n_0)); + FDRE #( + .INIT(1'b0)) + sig_last_dbeat_reg + (.C(m_axi_mm2s_aclk), + .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_17 ), + .D(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_16 ), + .Q(sig_last_dbeat), + .R(SR)); + LUT2 #( + .INIT(4'h8)) + sig_last_mmap_dbeat_reg_i_1 + (.I0(m_axi_mm2s_rlast), + .I1(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_10 ), + .O(sig_last_mmap_dbeat)); + FDRE #( + .INIT(1'b0)) + sig_last_mmap_dbeat_reg_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(sig_last_mmap_dbeat), + .Q(\sig_addr_posted_cntr_reg[2]_0 ), + .R(SR)); + LUT3 #( + .INIT(8'h08)) + sig_ld_new_cmd_reg_i_1 + (.I0(sig_push_dqual_reg), + .I1(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I2(sig_ld_new_cmd_reg), + .O(sig_ld_new_cmd_reg_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + sig_ld_new_cmd_reg_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(sig_ld_new_cmd_reg_i_1_n_0), + .Q(sig_ld_new_cmd_reg), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + sig_next_calc_error_reg_reg + (.C(m_axi_mm2s_aclk), + .CE(sig_push_dqual_reg), + .D(sig_cmd_fifo_data_out[35]), + .Q(sig_next_calc_error_reg), + .R(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_9 )); + FDRE #( + .INIT(1'b0)) + sig_next_cmd_cmplt_reg_reg + (.C(m_axi_mm2s_aclk), + .CE(sig_push_dqual_reg), + .D(sig_cmd_fifo_data_out[34]), + .Q(sig_next_cmd_cmplt_reg), + .R(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_9 )); + FDRE #( + .INIT(1'b0)) + sig_next_eof_reg_reg + (.C(m_axi_mm2s_aclk), + .CE(sig_push_dqual_reg), + .D(sig_cmd_fifo_data_out[32]), + .Q(sig_next_eof_reg), + .R(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_9 )); + FDRE #( + .INIT(1'b0)) + sig_next_sequential_reg_reg + (.C(m_axi_mm2s_aclk), + .CE(sig_push_dqual_reg), + .D(sig_cmd_fifo_data_out[33]), + .Q(sig_next_sequential_reg), + .R(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_9 )); + (* SOFT_HLUTNM = "soft_lutpair167" *) + LUT2 #( + .INIT(4'hE)) + sig_rd_sts_interr_reg_i_1 + (.I0(sig_data2rsc_calc_err), + .I1(sig_rd_sts_slverr_reg_reg[0]), + .O(sig_rd_sts_interr_reg0)); + (* SOFT_HLUTNM = "soft_lutpair166" *) + LUT2 #( + .INIT(4'h1)) + sig_rd_sts_reg_empty_i_1 + (.I0(sig_data2rsc_valid), + .I1(sig_data2rsc_calc_err), + .O(sig_rd_sts_reg_empty_reg)); + LUT2 #( + .INIT(4'h8)) + sig_rd_sts_reg_full_i_2 + (.I0(sig_data2rsc_valid), + .I1(sig_rsc2data_ready), + .O(sig_push_rd_sts_reg)); + (* SOFT_HLUTNM = "soft_lutpair166" *) + LUT2 #( + .INIT(4'hE)) + sig_rd_sts_reg_full_i_3 + (.I0(sig_data2rsc_calc_err), + .I1(sig_data2rsc_valid), + .O(sig_rd_sts_reg_full0)); + LUT2 #( + .INIT(4'hE)) + sig_rd_sts_slverr_reg_i_1 + (.I0(sig_data2rsc_slverr), + .I1(sig_rd_sts_slverr_reg_reg[1]), + .O(sig_rd_sts_slverr_reg0)); +endmodule + +(* ORIG_REF_NAME = "axi_datamover_reset" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_reset + (sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_rst2all_stop_request_0, + sig_stream_rst, + sig_halt_reg_reg, + datamover_idle_reg, + s2mm_halt_cmplt, + SR, + \sig_byte_cntr_reg[8] , + s_soft_reset_i_reg, + m_axi_s2mm_aclk, + halt_i_reg, + sig_halt_reg, + s2mm_halt, + s2mm_dmacr, + datamover_idle_2, + lsig_end_of_cmd_reg, + sig_clr_dbc_reg, + sig_wsc2rst_stop_cmplt, + sig_addr_reg_empty, + sig_addr2wsc_calc_error, + sig_data2rst_stop_cmplt); + output sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + output sig_rst2all_stop_request_0; + output sig_stream_rst; + output sig_halt_reg_reg; + output datamover_idle_reg; + output s2mm_halt_cmplt; + output [0:0]SR; + output [0:0]\sig_byte_cntr_reg[8] ; + input s_soft_reset_i_reg; + input m_axi_s2mm_aclk; + input halt_i_reg; + input sig_halt_reg; + input s2mm_halt; + input [0:0]s2mm_dmacr; + input datamover_idle_2; + input lsig_end_of_cmd_reg; + input sig_clr_dbc_reg; + input sig_wsc2rst_stop_cmplt; + input sig_addr_reg_empty; + input sig_addr2wsc_calc_error; + input sig_data2rst_stop_cmplt; + + wire [0:0]SR; + wire datamover_idle_2; + wire datamover_idle_reg; + wire halt_i_reg; + wire lsig_end_of_cmd_reg; + wire m_axi_s2mm_aclk; + wire [0:0]s2mm_dmacr; + wire s2mm_halt; + wire s2mm_halt_cmplt; + wire s_soft_reset_i_reg; + wire sig_addr2wsc_calc_error; + wire sig_addr_reg_empty; + wire [0:0]\sig_byte_cntr_reg[8] ; + wire sig_clr_dbc_reg; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_data2rst_stop_cmplt; + wire sig_halt_cmplt_i_1_n_0; + wire sig_halt_reg; + wire sig_halt_reg_reg; + wire sig_rst2all_stop_request_0; + wire sig_stream_rst; + wire sig_wsc2rst_stop_cmplt; + + (* SOFT_HLUTNM = "soft_lutpair239" *) + LUT2 #( + .INIT(4'hD)) + \GEN_INDET_BTT.lsig_byte_cntr[15]_i_1 + (.I0(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I1(lsig_end_of_cmd_reg), + .O(SR)); + LUT4 #( + .INIT(16'hCF88)) + datamover_idle_i_1__0 + (.I0(s2mm_halt_cmplt), + .I1(s2mm_halt), + .I2(s2mm_dmacr), + .I3(datamover_idle_2), + .O(datamover_idle_reg)); + (* SOFT_HLUTNM = "soft_lutpair239" *) + LUT2 #( + .INIT(4'hD)) + \sig_byte_cntr[8]_i_1 + (.I0(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I1(sig_clr_dbc_reg), + .O(\sig_byte_cntr_reg[8] )); + FDRE #( + .INIT(1'b0)) + sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s_soft_reset_i_reg), + .Q(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .R(1'b0)); + LUT6 #( + .INIT(64'hFFFFFFFFA8000000)) + sig_halt_cmplt_i_1 + (.I0(sig_wsc2rst_stop_cmplt), + .I1(sig_addr_reg_empty), + .I2(sig_addr2wsc_calc_error), + .I3(sig_halt_reg), + .I4(sig_data2rst_stop_cmplt), + .I5(s2mm_halt_cmplt), + .O(sig_halt_cmplt_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + sig_halt_cmplt_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_halt_cmplt_i_1_n_0), + .Q(s2mm_halt_cmplt), + .R(sig_stream_rst)); + LUT2 #( + .INIT(4'hE)) + sig_halt_reg_i_1 + (.I0(sig_rst2all_stop_request_0), + .I1(sig_halt_reg), + .O(sig_halt_reg_reg)); + LUT1 #( + .INIT(2'h1)) + sig_last_reg_out_i_1__0 + (.I0(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .O(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + sig_s_h_halt_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(halt_i_reg), + .Q(sig_rst2all_stop_request_0), + .R(sig_stream_rst)); +endmodule + +(* ORIG_REF_NAME = "axi_datamover_reset" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_reset_20 + (sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_rst2all_stop_request, + SR, + datamover_idle_reg, + mm2s_halt_cmplt, + out, + m_axi_mm2s_aclk, + halt_i_reg, + p_71_out, + mm2s_halt, + datamover_idle, + sig_calc_error_reg_reg, + sig_next_calc_error_reg, + sig_addr_posted_cntr); + output sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + output sig_rst2all_stop_request; + output [0:0]SR; + output datamover_idle_reg; + output mm2s_halt_cmplt; + input out; + input m_axi_mm2s_aclk; + input halt_i_reg; + input [0:0]p_71_out; + input mm2s_halt; + input datamover_idle; + input sig_calc_error_reg_reg; + input sig_next_calc_error_reg; + input [2:0]sig_addr_posted_cntr; + + wire [0:0]SR; + wire datamover_idle; + wire datamover_idle_reg; + wire halt_i_reg; + wire m_axi_mm2s_aclk; + wire mm2s_halt; + wire mm2s_halt_cmplt; + wire out; + wire [0:0]p_71_out; + wire [2:0]sig_addr_posted_cntr; + wire sig_calc_error_reg_reg; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_halt_cmplt_i_1_n_0; + wire sig_next_calc_error_reg; + wire sig_rst2all_stop_request; + + LUT1 #( + .INIT(2'h1)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_4 + (.I0(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .O(SR)); + LUT4 #( + .INIT(16'hF3A0)) + datamover_idle_i_1 + (.I0(mm2s_halt_cmplt), + .I1(p_71_out), + .I2(mm2s_halt), + .I3(datamover_idle), + .O(datamover_idle_reg)); + FDRE #( + .INIT(1'b0)) + sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0 + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(out), + .Q(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .R(1'b0)); + LUT6 #( + .INIT(64'hFFFFFFFF44444445)) + sig_halt_cmplt_i_1 + (.I0(sig_calc_error_reg_reg), + .I1(sig_next_calc_error_reg), + .I2(sig_addr_posted_cntr[0]), + .I3(sig_addr_posted_cntr[2]), + .I4(sig_addr_posted_cntr[1]), + .I5(mm2s_halt_cmplt), + .O(sig_halt_cmplt_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + sig_halt_cmplt_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(sig_halt_cmplt_i_1_n_0), + .Q(mm2s_halt_cmplt), + .R(SR)); + FDRE #( + .INIT(1'b0)) + sig_s_h_halt_reg_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(halt_i_reg), + .Q(sig_rst2all_stop_request), + .R(SR)); +endmodule + +(* ORIG_REF_NAME = "axi_datamover_s2mm_full_wrap" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_s2mm_full_wrap + (m_axi_s2mm_awburst, + m_axi_s2mm_awvalid, + m_axi_s2mm_wvalid, + \sig_data_skid_reg_reg[7] , + DI, + sig_rst2all_stop_request_0, + m_axi_s2mm_wlast, + RD_EN, + p_9_out, + Q, + s_axis_cmd_tvalid_reg, + CO, + datamover_idle_reg, + s2mm_halt_cmplt, + decerr_i_reg, + slverr_i_reg, + interr_i_reg, + E, + \GEN_STS_GRTR_THAN_8.ovrflo_err_reg , + m_axi_s2mm_awaddr, + m_axi_s2mm_awlen, + m_axi_s2mm_awsize, + m_axi_s2mm_wdata, + \gpr1.dout_i_reg[1] , + \gpr1.dout_i_reg[1]_0 , + m_axi_s2mm_bready, + m_axi_s2mm_aclk, + s_soft_reset_i_reg, + halt_i_reg, + DOUT, + EMPTY, + s2mm_halt, + s2mm_soft_reset, + dma_err, + cmnd_wr_1, + \hsize_vid_reg[15] , + \hsize_vid_reg[2] , + S, + s2mm_dmacr, + datamover_idle_2, + m_axi_s2mm_awready, + m_axi_s2mm_wready, + \s_axis_cmd_tdata_reg[63] , + m_axi_s2mm_bresp, + p_0_out, + s_axis_s2mm_cmd_tvalid, + m_axi_s2mm_bvalid, + m_axis_s2mm_sts_tready); + output [0:0]m_axi_s2mm_awburst; + output m_axi_s2mm_awvalid; + output m_axi_s2mm_wvalid; + output \sig_data_skid_reg_reg[7] ; + output [10:0]DI; + output sig_rst2all_stop_request_0; + output m_axi_s2mm_wlast; + output RD_EN; + output p_9_out; + output [0:0]Q; + output [0:0]s_axis_cmd_tvalid_reg; + output [0:0]CO; + output datamover_idle_reg; + output s2mm_halt_cmplt; + output decerr_i_reg; + output slverr_i_reg; + output interr_i_reg; + output [0:0]E; + output [0:0]\GEN_STS_GRTR_THAN_8.ovrflo_err_reg ; + output [31:0]m_axi_s2mm_awaddr; + output [5:0]m_axi_s2mm_awlen; + output [1:0]m_axi_s2mm_awsize; + output [63:0]m_axi_s2mm_wdata; + output [2:0]\gpr1.dout_i_reg[1] ; + output [2:0]\gpr1.dout_i_reg[1]_0 ; + output m_axi_s2mm_bready; + input m_axi_s2mm_aclk; + input s_soft_reset_i_reg; + input halt_i_reg; + input [8:0]DOUT; + input EMPTY; + input s2mm_halt; + input s2mm_soft_reset; + input dma_err; + input cmnd_wr_1; + input [12:0]\hsize_vid_reg[15] ; + input [0:0]\hsize_vid_reg[2] ; + input [0:0]S; + input [0:0]s2mm_dmacr; + input datamover_idle_2; + input m_axi_s2mm_awready; + input m_axi_s2mm_wready; + input [48:0]\s_axis_cmd_tdata_reg[63] ; + input [1:0]m_axi_s2mm_bresp; + input [10:0]p_0_out; + input s_axis_s2mm_cmd_tvalid; + input m_axi_s2mm_bvalid; + input m_axis_s2mm_sts_tready; + + wire [0:0]CO; + wire [10:0]DI; + wire [8:0]DOUT; + wire [0:0]E; + wire EMPTY; + wire \ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/p_0_in2_in ; + wire \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/sig_inhibit_rdy_n ; + wire \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/sig_init_done ; + wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_inhibit_rdy_n ; + wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_init_done ; + wire \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/sig_init_reg ; + wire \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/sig_wr_fifo ; + wire \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_117 ; + wire \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_118 ; + wire \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_129 ; + wire \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_130 ; + wire \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_131 ; + wire \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_132 ; + wire \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_133 ; + wire \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_134 ; + wire \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_135 ; + wire \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_136 ; + wire \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_137 ; + wire \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_15 ; + wire \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_18 ; + wire \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_19 ; + wire \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_20 ; + wire \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_39 ; + wire \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_41 ; + wire \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_42 ; + wire \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_43 ; + wire \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_44 ; + wire \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_45 ; + wire \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_46 ; + wire \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_47 ; + wire \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_48 ; + wire \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_49 ; + wire \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_50 ; + wire \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_51 ; + wire \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_87 ; + wire \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_88 ; + wire \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_89 ; + wire \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_90 ; + wire \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_91 ; + wire \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_92 ; + wire \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_93 ; + wire \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_94 ; + wire \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_1 ; + wire \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_10 ; + wire \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_11 ; + wire \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_15 ; + wire \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_17 ; + wire \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_18 ; + wire \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_19 ; + wire \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_20 ; + wire \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_21 ; + wire \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_22 ; + wire \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_23 ; + wire \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_24 ; + wire \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_25 ; + wire \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_26 ; + wire \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_27 ; + wire \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_28 ; + wire \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_29 ; + wire \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_30 ; + wire \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_31 ; + wire \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_32 ; + wire \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_33 ; + wire \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_4 ; + wire \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_9 ; + wire \GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_init_done ; + wire [0:0]\GEN_STS_GRTR_THAN_8.ovrflo_err_reg ; + wire \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ; + wire \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ; + wire I_ADDR_CNTL_n_1; + wire \I_CMD_FIFO/sig_init_done ; + wire \I_CMD_FIFO/sig_rd_empty ; + wire I_CMD_STATUS_n_12; + wire I_CMD_STATUS_n_2; + wire I_CMD_STATUS_n_8; + wire \I_DRE_CNTL_FIFO/sig_inhibit_rdy_n ; + wire \I_DRE_CNTL_FIFO/sig_init_reg2 ; + wire I_RESET_n_3; + wire I_RESET_n_6; + wire I_RESET_n_7; + wire I_WR_DATA_CNTL_n_0; + wire I_WR_DATA_CNTL_n_25; + wire I_WR_DATA_CNTL_n_4; + wire I_WR_STATUS_CNTLR_n_21; + wire I_WR_STATUS_CNTLR_n_27; + wire I_WR_STATUS_CNTLR_n_28; + wire I_WR_STATUS_CNTLR_n_29; + wire I_WR_STATUS_CNTLR_n_30; + wire [0:0]Q; + wire RD_EN; + wire [0:0]S; + wire cmnd_wr_1; + wire datamover_idle_2; + wire datamover_idle_reg; + wire decerr_i_reg; + wire dma_err; + wire [2:0]\gpr1.dout_i_reg[1] ; + wire [2:0]\gpr1.dout_i_reg[1]_0 ; + wire halt_i_reg; + wire [12:0]\hsize_vid_reg[15] ; + wire [0:0]\hsize_vid_reg[2] ; + wire interr_i_reg; + wire [1:0]lsig_0ffset_cntr; + wire lsig_end_of_cmd_reg; + wire lsig_eop_reg; + wire m_axi_s2mm_aclk; + wire [31:0]m_axi_s2mm_awaddr; + wire [0:0]m_axi_s2mm_awburst; + wire [5:0]m_axi_s2mm_awlen; + wire m_axi_s2mm_awready; + wire [1:0]m_axi_s2mm_awsize; + wire m_axi_s2mm_awvalid; + wire m_axi_s2mm_bready; + wire [1:0]m_axi_s2mm_bresp; + wire m_axi_s2mm_bvalid; + wire [63:0]m_axi_s2mm_wdata; + wire m_axi_s2mm_wlast; + wire m_axi_s2mm_wready; + wire m_axi_s2mm_wvalid; + wire m_axis_s2mm_sts_tready; + wire p_0_in; + wire [10:0]p_0_out; + wire [2:0]p_0_out_1; + wire p_10_out; + wire p_11_out; + wire p_12_out; + wire p_13_out; + wire p_14_out; + wire [5:0]p_19_out; + wire p_1_out; + wire [2:0]p_20_out; + wire p_22_out; + wire [0:0]p_27_out; + wire p_2_out; + wire [31:3]p_30_out; + wire p_32_out; + wire p_3_out; + wire [15:0]p_5_out; + wire p_9_out; + wire p_9_out_0; + wire [0:0]s2mm_dmacr; + wire s2mm_halt; + wire s2mm_halt_cmplt; + wire s2mm_soft_reset; + wire [48:0]\s_axis_cmd_tdata_reg[63] ; + wire [0:0]s_axis_cmd_tvalid_reg; + wire s_axis_s2mm_cmd_tvalid; + wire s_soft_reset_i_reg; + wire sig_addr2data_addr_posted; + wire sig_addr2wsc_calc_error; + wire sig_addr_reg_empty; + wire [8:0]sig_adjusted_addr_incr; + wire [2:0]sig_child_addr_cntr_lsh_reg; + wire sig_child_qual_error_reg; + wire sig_child_qual_first_of_2; + wire sig_child_tag_reg0; + wire sig_clr_cmd2addr_valid3_out__0; + wire sig_clr_cmd2data_valid4_out__0; + wire sig_clr_dbc_reg; + wire [63:0]sig_cmd2mstr_command; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_csm_pop_child_cmd; + wire sig_csm_state_ns1; + wire sig_data2rst_stop_cmplt; + wire sig_data2skid_wvalid; + wire [15:3]sig_data2wsc_bytes_rcvd; + wire sig_data2wsc_calc_err; + wire sig_data2wsc_cmd_cmplt; + wire sig_data2wsc_valid; + wire \sig_data_skid_reg_reg[7] ; + wire sig_dbeat_cntr_eq_0__2; + wire sig_dqual_reg_full; + wire sig_dre2ibtt_eop; + wire [7:0]sig_dre2ibtt_tdata; + wire sig_dre2ibtt_tlast; + wire sig_dre2ibtt_tstrb; + wire sig_good_strm_dbeat38_out__0; + wire sig_halt_reg; + wire sig_halt_reg_dly3; + wire sig_ibtt2dre_tready; + wire [3:3]sig_ibtt2wdc_stbs_asserted; + wire [63:0]sig_ibtt2wdc_tdata; + wire sig_ibtt2wdc_tlast; + wire sig_ibtt2wdc_tvalid; + wire sig_input_cache_type_reg0; + wire sig_input_reg_empty; + wire sig_psm_halt; + wire sig_psm_pop_input_cmd; + wire sig_rst2all_stop_request_0; + wire sig_set_push2wsc; + wire sig_sf2pcc_cmd_cmplt; + wire [8:0]sig_sf2pcc_xfer_bytes; + wire sig_sf2pcc_xfer_valid; + wire [2:0]sig_sf_strt_addr_offset; + wire sig_skid2data_wready; + wire sig_stream_rst; + wire sig_wdc2ibtt_tready; + wire sig_wdc_status_going_full; + wire sig_wsc2rst_stop_cmplt; + wire [31:4]sig_wsc2stat_status; + wire sig_wsc2stat_status_valid; + wire sig_xfer_cmd_cmplt_reg0; + wire slverr_i_reg; + + Arty_Z7_20_axi_vdma_0_0_axi_datamover_indet_btt \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT + (.CO(\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_133 ), + .D({\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_18 ,\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_19 ,\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_20 }), + .DI(DI), + .E(I_WR_DATA_CNTL_n_25), + .\GEN_INDET_BTT.lsig_byte_cntr_reg[15] (\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_50 ), + .\GEN_INDET_BTT.lsig_byte_cntr_reg[3] ({sig_ibtt2wdc_stbs_asserted,sig_ibtt2wdc_tdata}), + .\GEN_INDET_BTT.lsig_byte_cntr_reg[6] (\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_51 ), + .\GEN_INDET_BTT.lsig_eop_reg_reg (sig_ibtt2wdc_tvalid), + .\GEN_INDET_BTT.lsig_eop_reg_reg_0 (\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_117 ), + .\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[0] (\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_11 ), + .\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[0]_0 (\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_15 ), + .\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[0]_1 (\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_33 ), + .\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] (sig_sf_strt_addr_offset), + .\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 (\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_15 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_1 (lsig_0ffset_cntr), + .\INCLUDE_PACKING.lsig_first_dbeat_reg_0 (\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_4 ), + .\INFERRED_GEN.cnt_i_reg[4] (sig_good_strm_dbeat38_out__0), + .O({\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_129 ,\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_130 ,\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_131 ,\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_132 }), + .Q(sig_dre2ibtt_tdata), + .S({\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_41 ,\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_42 ,\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_43 ,\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_44 }), + .SR({I_RESET_n_7,\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_9 }), + .\gcc0.gc0.count_d1_reg[0] (E), + .\gpr1.dout_i_reg[1] (\gpr1.dout_i_reg[1]_0 ), + .\gpr1.dout_i_reg[1]_0 (\gpr1.dout_i_reg[1] ), + .\gpr1.dout_i_reg[3] ({\GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_87 ,\GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_88 ,\GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_89 ,\GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_90 }), + .\gpr1.dout_i_reg[7] ({\GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_91 ,\GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_92 ,\GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_93 ,\GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_94 }), + .lsig_end_of_cmd_reg(lsig_end_of_cmd_reg), + .lsig_eop_reg(lsig_eop_reg), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(\ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/p_0_in2_in ), + .p_0_in(p_0_in), + .p_0_out(p_0_out), + .p_32_out(p_32_out), + .sig_adjusted_addr_incr(sig_adjusted_addr_incr), + .sig_child_addr_cntr_lsh_reg(sig_child_addr_cntr_lsh_reg), + .\sig_child_addr_cntr_lsh_reg[11] (\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_39 ), + .\sig_child_addr_cntr_lsh_reg[7] ({\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_134 ,\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_135 ,\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_136 ,\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_137 }), + .sig_child_qual_error_reg(sig_child_qual_error_reg), + .sig_child_qual_first_of_2(sig_child_qual_first_of_2), + .sig_clr_dbc_reg(sig_clr_dbc_reg), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_csm_pop_child_cmd(sig_csm_pop_child_cmd), + .sig_csm_state_ns1(sig_csm_state_ns1), + .sig_dre2ibtt_eop(sig_dre2ibtt_eop), + .sig_dre2ibtt_tlast(sig_dre2ibtt_tlast), + .sig_dre2ibtt_tstrb(sig_dre2ibtt_tstrb), + .sig_ibtt2dre_tready(sig_ibtt2dre_tready), + .sig_ibtt2wdc_tlast(sig_ibtt2wdc_tlast), + .sig_init_reg(\GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/sig_init_reg ), + .sig_m_valid_out_reg({\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_25 ,\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_26 }), + .sig_m_valid_out_reg_0({\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_23 ,\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_24 }), + .sig_m_valid_out_reg_1({\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_27 ,\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_28 }), + .sig_m_valid_out_reg_2({\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_21 ,\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_22 }), + .sig_m_valid_out_reg_3({\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_29 ,\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_30 }), + .sig_m_valid_out_reg_4({\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_19 ,\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_20 }), + .sig_m_valid_out_reg_5({\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_31 ,\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_32 }), + .sig_m_valid_out_reg_6({\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_17 ,\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_18 }), + .sig_sf2pcc_xfer_valid(sig_sf2pcc_xfer_valid), + .\sig_strb_reg_out_reg[0] (\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_10 ), + .sig_stream_rst(sig_stream_rst), + .sig_wdc2ibtt_tready(sig_wdc2ibtt_tready), + .sig_xfer_cmd_cmplt_reg0(sig_xfer_cmd_cmplt_reg0), + .sig_xfer_is_seq_reg_reg({sig_sf2pcc_cmd_cmplt,sig_sf2pcc_xfer_bytes}), + .sig_xfer_is_seq_reg_reg_0(\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_118 ), + .\sig_xfer_len_reg_reg[4] ({\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_45 ,\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_46 ,\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_47 ,\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_48 }), + .\sig_xfer_len_reg_reg[5] (\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_49 )); + Arty_Z7_20_axi_vdma_0_0_axi_datamover_ibttcc \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC + (.CO(\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_133 ), + .D({\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_18 ,\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_19 ,\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_20 }), + .FIFO_Full_reg(\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_1 ), + .FIFO_Full_reg_0(I_WR_DATA_CNTL_n_0), + .FIFO_Full_reg_1(I_ADDR_CNTL_n_1), + .\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] ({p_0_out_1,p_1_out,p_2_out,p_3_out,p_5_out}), + .O({\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_129 ,\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_130 ,\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_131 ,\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_132 }), + .Q(\I_CMD_FIFO/sig_rd_empty ), + .S({\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_41 ,\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_42 ,\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_43 ,\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_44 }), + .SR(sig_child_tag_reg0), + .\gpr1.dout_i_reg[10] (\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_118 ), + .\gpr1.dout_i_reg[7] ({\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_134 ,\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_135 ,\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_136 ,\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_137 }), + .\gpr1.dout_i_reg[7]_0 ({\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_45 ,\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_46 ,\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_47 ,\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_48 }), + .\gpr1.dout_i_reg[8] (\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_49 ), + .\gpr1.dout_i_reg[8]_0 (\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_39 ), + .\gpr1.dout_i_reg[9] ({sig_sf2pcc_cmd_cmplt,sig_sf2pcc_xfer_bytes}), + .in({p_13_out,p_27_out,p_19_out,p_30_out,p_20_out}), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out({sig_cmd2mstr_command[63:32],sig_cmd2mstr_command[30],sig_cmd2mstr_command[23],sig_cmd2mstr_command[15:0]}), + .p_10_out(p_10_out), + .p_11_out(p_11_out), + .p_22_out(p_22_out), + .p_32_out(p_32_out), + .p_9_out_0(p_9_out_0), + .sig_adjusted_addr_incr(sig_adjusted_addr_incr), + .\sig_child_addr_cntr_lsh_reg[3]_0 ({\GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_87 ,\GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_88 ,\GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_89 ,\GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_90 }), + .\sig_child_addr_cntr_lsh_reg[7]_0 ({\GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_91 ,\GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_92 ,\GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_93 ,\GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_94 }), + .sig_child_qual_error_reg(sig_child_qual_error_reg), + .sig_child_qual_first_of_2(sig_child_qual_first_of_2), + .sig_clr_cmd2addr_valid3_out__0(sig_clr_cmd2addr_valid3_out__0), + .sig_clr_cmd2data_valid4_out__0(sig_clr_cmd2data_valid4_out__0), + .sig_csm_pop_child_cmd(sig_csm_pop_child_cmd), + .sig_csm_state_ns1(sig_csm_state_ns1), + .sig_inhibit_rdy_n(\I_DRE_CNTL_FIFO/sig_inhibit_rdy_n ), + .sig_inhibit_rdy_n_0(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_inhibit_rdy_n ), + .sig_inhibit_rdy_n_1(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/sig_inhibit_rdy_n ), + .sig_init_reg(\GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/sig_init_reg ), + .sig_input_cache_type_reg0(sig_input_cache_type_reg0), + .sig_input_reg_empty(sig_input_reg_empty), + .sig_next_cmd_cmplt_reg_reg({p_12_out,p_14_out}), + .sig_psm_halt(sig_psm_halt), + .sig_psm_halt_reg_0(I_CMD_STATUS_n_2), + .sig_psm_pop_input_cmd(sig_psm_pop_input_cmd), + .sig_sf2pcc_xfer_valid(sig_sf2pcc_xfer_valid), + .\sig_xfer_addr_reg_reg[2]_0 (sig_child_addr_cntr_lsh_reg), + .sig_xfer_cmd_cmplt_reg0(sig_xfer_cmd_cmplt_reg0)); + Arty_Z7_20_axi_vdma_0_0_axi_datamover_s2mm_realign \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER + (.DOUT(DOUT), + .EMPTY(EMPTY), + .\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] ({\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_17 ,\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_18 }), + .\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] ({\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_25 ,\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_26 }), + .\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] ({\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_23 ,\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_24 }), + .\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] ({\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_27 ,\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_28 }), + .\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] ({\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_21 ,\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_22 }), + .\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] ({\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_29 ,\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_30 }), + .\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] ({\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_19 ,\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_20 }), + .\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7] (sig_dre2ibtt_tdata), + .\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] ({\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_31 ,\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_32 }), + .\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] (\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_15 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] (\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_11 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 (lsig_0ffset_cntr), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] (\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_33 ), + .\INCLUDE_PACKING.lsig_first_dbeat_reg (\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_4 ), + .\INCLUDE_PACKING.lsig_first_dbeat_reg_0 (\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_15 ), + .\INFERRED_GEN.cnt_i_reg[0] (\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_1 ), + .Q(sig_sf_strt_addr_offset), + .RD_EN(RD_EN), + .SR(\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_9 ), + .in({p_0_out_1,p_1_out,p_2_out,p_3_out,p_5_out}), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .p_0_in(p_0_in), + .p_9_out_0(p_9_out_0), + .\sig_byte_cntr_reg[0] (sig_good_strm_dbeat38_out__0), + .\sig_byte_cntr_reg[3] (\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_10 ), + .sig_clr_dbc_reg(sig_clr_dbc_reg), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .\sig_data_skid_reg_reg[7] (\sig_data_skid_reg_reg[7] ), + .sig_dre2ibtt_eop(sig_dre2ibtt_eop), + .sig_dre2ibtt_tlast(sig_dre2ibtt_tlast), + .sig_dre2ibtt_tstrb(sig_dre2ibtt_tstrb), + .sig_ibtt2dre_tready(sig_ibtt2dre_tready), + .sig_inhibit_rdy_n(\I_DRE_CNTL_FIFO/sig_inhibit_rdy_n ), + .sig_init_reg(\GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/sig_init_reg ), + .sig_init_reg2(\I_DRE_CNTL_FIFO/sig_init_reg2 ), + .sig_stream_rst(sig_stream_rst)); + Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl__parameterized0 I_ADDR_CNTL + (.\INFERRED_GEN.cnt_i_reg[0] (I_ADDR_CNTL_n_1), + .in({p_13_out,p_27_out,p_19_out,p_30_out,p_20_out}), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .m_axi_s2mm_awaddr(m_axi_s2mm_awaddr), + .m_axi_s2mm_awburst(m_axi_s2mm_awburst), + .m_axi_s2mm_awlen(m_axi_s2mm_awlen), + .m_axi_s2mm_awready(m_axi_s2mm_awready), + .m_axi_s2mm_awsize(m_axi_s2mm_awsize), + .m_axi_s2mm_awvalid(m_axi_s2mm_awvalid), + .out(sig_addr2data_addr_posted), + .p_22_out(p_22_out), + .sig_addr2wsc_calc_error(sig_addr2wsc_calc_error), + .sig_addr_reg_empty(sig_addr_reg_empty), + .sig_clr_cmd2addr_valid3_out__0(sig_clr_cmd2addr_valid3_out__0), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_halt_reg(sig_halt_reg), + .sig_inhibit_rdy_n(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/sig_inhibit_rdy_n ), + .sig_init_done(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/sig_init_done ), + .sig_init_reg_reg(I_WR_STATUS_CNTLR_n_27), + .sig_stream_rst(sig_stream_rst)); + Arty_Z7_20_axi_vdma_0_0_axi_datamover_cmd_status__parameterized0 I_CMD_STATUS + (.CO(CO), + .FIFO_Full_reg(Q), + .\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg (I_CMD_STATUS_n_8), + .\GEN_STS_GRTR_THAN_8.ovrflo_err_reg (\GEN_STS_GRTR_THAN_8.ovrflo_err_reg ), + .Q(\I_CMD_FIFO/sig_rd_empty ), + .S(S), + .cmnd_wr_1(cmnd_wr_1), + .decerr_i_reg(decerr_i_reg), + .dma_err(dma_err), + .\hsize_vid_reg[15] (\hsize_vid_reg[15] ), + .\hsize_vid_reg[2] (\hsize_vid_reg[2] ), + .in({sig_wsc2stat_status[31],sig_wsc2stat_status[23:11],sig_wsc2stat_status[6:4]}), + .interr_i_reg(interr_i_reg), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .m_axis_s2mm_sts_tready(m_axis_s2mm_sts_tready), + .out({sig_cmd2mstr_command[63:32],sig_cmd2mstr_command[30],sig_cmd2mstr_command[23],sig_cmd2mstr_command[15:0]}), + .p_10_out(p_10_out), + .p_9_out(p_9_out), + .s2mm_halt(s2mm_halt), + .s2mm_soft_reset(s2mm_soft_reset), + .\s_axis_cmd_tdata_reg[63] (\s_axis_cmd_tdata_reg[63] ), + .s_axis_cmd_tvalid_reg(s_axis_cmd_tvalid_reg), + .s_axis_s2mm_cmd_tvalid(s_axis_s2mm_cmd_tvalid), + .sig_calc_error_reg_reg(I_CMD_STATUS_n_2), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_dqual_reg_empty_reg(I_CMD_STATUS_n_12), + .sig_init_done(\I_CMD_FIFO/sig_init_done ), + .sig_init_done_0(\GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_init_done ), + .sig_init_reg_reg(I_WR_STATUS_CNTLR_n_30), + .sig_init_reg_reg_0(I_WR_STATUS_CNTLR_n_29), + .sig_input_reg_empty(sig_input_reg_empty), + .sig_psm_halt(sig_psm_halt), + .sig_stream_rst(sig_stream_rst), + .sig_wsc2stat_status_valid(sig_wsc2stat_status_valid), + .slverr_i_reg(slverr_i_reg)); + Arty_Z7_20_axi_vdma_0_0_axi_datamover_reset I_RESET + (.SR(I_RESET_n_6), + .datamover_idle_2(datamover_idle_2), + .datamover_idle_reg(datamover_idle_reg), + .halt_i_reg(halt_i_reg), + .lsig_end_of_cmd_reg(lsig_end_of_cmd_reg), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .s2mm_dmacr(s2mm_dmacr), + .s2mm_halt(s2mm_halt), + .s2mm_halt_cmplt(s2mm_halt_cmplt), + .s_soft_reset_i_reg(s_soft_reset_i_reg), + .sig_addr2wsc_calc_error(sig_addr2wsc_calc_error), + .sig_addr_reg_empty(sig_addr_reg_empty), + .\sig_byte_cntr_reg[8] (I_RESET_n_7), + .sig_clr_dbc_reg(sig_clr_dbc_reg), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_data2rst_stop_cmplt(sig_data2rst_stop_cmplt), + .sig_halt_reg(sig_halt_reg), + .sig_halt_reg_reg(I_RESET_n_3), + .sig_rst2all_stop_request_0(sig_rst2all_stop_request_0), + .sig_stream_rst(sig_stream_rst), + .sig_wsc2rst_stop_cmplt(sig_wsc2rst_stop_cmplt)); + Arty_Z7_20_axi_vdma_0_0_axi_datamover_skid2mm_buf I_S2MM_MMAP_SKID_BUF + (.D(sig_ibtt2wdc_tdata), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .m_axi_s2mm_wdata(m_axi_s2mm_wdata), + .m_axi_s2mm_wlast(m_axi_s2mm_wlast), + .m_axi_s2mm_wready(m_axi_s2mm_wready), + .m_axi_s2mm_wvalid(m_axi_s2mm_wvalid), + .out(sig_skid2data_wready), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_data2skid_wvalid(sig_data2skid_wvalid), + .sig_dbeat_cntr_eq_0__2(sig_dbeat_cntr_eq_0__2), + .sig_dqual_reg_full(sig_dqual_reg_full), + .sig_init_reg(\GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/sig_init_reg ), + .sig_stream_rst(sig_stream_rst)); + Arty_Z7_20_axi_vdma_0_0_axi_datamover_wrdata_cntl I_WR_DATA_CNTL + (.E(I_WR_DATA_CNTL_n_25), + .\INFERRED_GEN.cnt_i_reg[0] (I_WR_DATA_CNTL_n_0), + .SR(I_RESET_n_6), + .in({I_WR_DATA_CNTL_n_4,sig_data2wsc_bytes_rcvd,sig_data2wsc_cmd_cmplt,sig_data2wsc_calc_err}), + .lsig_end_of_cmd_reg(lsig_end_of_cmd_reg), + .lsig_eop_reg(lsig_eop_reg), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(\ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/p_0_in2_in ), + .p_11_out(p_11_out), + .sig_clr_cmd2data_valid4_out__0(sig_clr_cmd2data_valid4_out__0), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0(I_WR_STATUS_CNTLR_n_21), + .sig_data2rst_stop_cmplt(sig_data2rst_stop_cmplt), + .sig_data2skid_wvalid(sig_data2skid_wvalid), + .sig_data2wsc_valid(sig_data2wsc_valid), + .\sig_data_reg_out_reg[67] (sig_ibtt2wdc_stbs_asserted), + .sig_dbeat_cntr_eq_0__2(sig_dbeat_cntr_eq_0__2), + .sig_dqual_reg_full(sig_dqual_reg_full), + .sig_halt_reg(sig_halt_reg), + .sig_halt_reg_dly3(sig_halt_reg_dly3), + .sig_ibtt2wdc_tlast(sig_ibtt2wdc_tlast), + .sig_inhibit_rdy_n(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_inhibit_rdy_n ), + .sig_inhibit_rdy_n_reg(I_CMD_STATUS_n_12), + .sig_init_done(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_init_done ), + .sig_init_reg_reg(I_WR_STATUS_CNTLR_n_28), + .sig_m_valid_out_reg(\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_117 ), + .sig_m_valid_out_reg_0(sig_ibtt2wdc_tvalid), + .sig_m_valid_out_reg_1(\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_50 ), + .sig_m_valid_out_reg_2(\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_51 ), + .sig_posted_to_axi_reg(sig_addr2data_addr_posted), + .sig_s_ready_out_reg(sig_skid2data_wready), + .sig_set_push2wsc(sig_set_push2wsc), + .sig_stream_rst(sig_stream_rst), + .sig_wdc2ibtt_tready(sig_wdc2ibtt_tready), + .sig_wdc_status_going_full(sig_wdc_status_going_full), + .sig_wr_fifo(\GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/sig_wr_fifo ), + .sig_wsc2stat_status_valid(sig_wsc2stat_status_valid), + .sig_xfer_calc_err_reg_reg({p_13_out,p_12_out,p_14_out,p_19_out})); + Arty_Z7_20_axi_vdma_0_0_axi_datamover_wr_status_cntl I_WR_STATUS_CNTLR + (.\GEN_INDET_BTT.lsig_eop_reg_reg ({I_WR_DATA_CNTL_n_4,sig_data2wsc_bytes_rcvd,sig_data2wsc_cmd_cmplt,sig_data2wsc_calc_err}), + .SR(sig_child_tag_reg0), + .in({sig_wsc2stat_status[31],sig_wsc2stat_status[23:11],sig_wsc2stat_status[6:4]}), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .m_axi_s2mm_bready(m_axi_s2mm_bready), + .m_axi_s2mm_bresp(m_axi_s2mm_bresp), + .m_axi_s2mm_bvalid(m_axi_s2mm_bvalid), + .out(sig_addr2data_addr_posted), + .sig_addr2wsc_calc_error(sig_addr2wsc_calc_error), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_csm_pop_child_cmd(sig_csm_pop_child_cmd), + .sig_data2wsc_valid(sig_data2wsc_valid), + .sig_halt_reg(sig_halt_reg), + .sig_halt_reg_dly3(sig_halt_reg_dly3), + .sig_inhibit_rdy_n_reg(I_CMD_STATUS_n_8), + .sig_init_done(\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/sig_init_done ), + .sig_init_done_0(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_init_done ), + .sig_init_done_1(\GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_init_done ), + .sig_init_done_2(\I_CMD_FIFO/sig_init_done ), + .sig_init_done_reg(I_WR_STATUS_CNTLR_n_27), + .sig_init_done_reg_0(I_WR_STATUS_CNTLR_n_28), + .sig_init_done_reg_1(I_WR_STATUS_CNTLR_n_29), + .sig_init_done_reg_2(I_WR_STATUS_CNTLR_n_30), + .sig_init_reg(\GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/sig_init_reg ), + .sig_init_reg2(\I_DRE_CNTL_FIFO/sig_init_reg2 ), + .sig_input_cache_type_reg0(sig_input_cache_type_reg0), + .sig_psm_pop_input_cmd(sig_psm_pop_input_cmd), + .sig_push_to_wsc_reg(I_WR_STATUS_CNTLR_n_21), + .sig_s_h_halt_reg_reg(I_RESET_n_3), + .sig_set_push2wsc(sig_set_push2wsc), + .sig_stream_rst(sig_stream_rst), + .sig_wdc_status_going_full(sig_wdc_status_going_full), + .sig_wr_fifo(\GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/sig_wr_fifo ), + .sig_wsc2rst_stop_cmplt(sig_wsc2rst_stop_cmplt), + .sig_wsc2stat_status_valid(sig_wsc2stat_status_valid)); +endmodule + +(* ORIG_REF_NAME = "axi_datamover_s2mm_realign" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_s2mm_realign + (\sig_data_skid_reg_reg[7] , + \INFERRED_GEN.cnt_i_reg[0] , + sig_init_reg2, + sig_dre2ibtt_tstrb, + \INCLUDE_PACKING.lsig_first_dbeat_reg , + \sig_byte_cntr_reg[0] , + sig_dre2ibtt_tlast, + RD_EN, + sig_dre2ibtt_eop, + SR, + \sig_byte_cntr_reg[3] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] , + Q, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] , + sig_inhibit_rdy_n, + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] , + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] , + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] , + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] , + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] , + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] , + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] , + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] , + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7] , + sig_stream_rst, + m_axi_s2mm_aclk, + sig_init_reg, + \INCLUDE_PACKING.lsig_first_dbeat_reg_0 , + DOUT, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + EMPTY, + sig_ibtt2dre_tready, + sig_clr_dbc_reg, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 , + p_9_out_0, + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 , + p_0_in, + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 , + in); + output \sig_data_skid_reg_reg[7] ; + output \INFERRED_GEN.cnt_i_reg[0] ; + output sig_init_reg2; + output sig_dre2ibtt_tstrb; + output \INCLUDE_PACKING.lsig_first_dbeat_reg ; + output [0:0]\sig_byte_cntr_reg[0] ; + output sig_dre2ibtt_tlast; + output RD_EN; + output sig_dre2ibtt_eop; + output [0:0]SR; + output [0:0]\sig_byte_cntr_reg[3] ; + output \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ; + output [2:0]Q; + output \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] ; + output sig_inhibit_rdy_n; + output [1:0]\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] ; + output [1:0]\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] ; + output [1:0]\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] ; + output [1:0]\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] ; + output [1:0]\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] ; + output [1:0]\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] ; + output [1:0]\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] ; + output [1:0]\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] ; + output \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] ; + output [7:0]\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7] ; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input sig_init_reg; + input \INCLUDE_PACKING.lsig_first_dbeat_reg_0 ; + input [8:0]DOUT; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input EMPTY; + input sig_ibtt2dre_tready; + input sig_clr_dbc_reg; + input [1:0]\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ; + input p_9_out_0; + input \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ; + input p_0_in; + input \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ; + input [21:0]in; + + wire [8:0]DOUT; + wire EMPTY; + wire \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_good_tlast_dbeat37_out__0 ; + wire \GEN_INCLUDE_SCATTER.I_S2MM_SCATTER_n_11 ; + wire \GEN_INCLUDE_SCATTER.I_S2MM_SCATTER_n_30 ; + wire [1:0]\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ; + wire [1:0]\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] ; + wire [1:0]\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ; + wire [1:0]\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ; + wire [1:0]\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ; + wire [1:0]\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ; + wire [1:0]\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ; + wire [7:0]\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7] ; + wire [1:0]\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ; + wire [1:0]\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] ; + wire \INCLUDE_PACKING.lsig_first_dbeat_reg ; + wire \INCLUDE_PACKING.lsig_first_dbeat_reg_0 ; + wire \INFERRED_GEN.cnt_i_reg[0] ; + wire I_DRE_CNTL_FIFO_n_24; + wire I_DRE_CNTL_FIFO_n_27; + wire I_DRE_CNTL_FIFO_n_28; + wire I_DRE_CNTL_FIFO_n_29; + wire [2:0]Q; + wire RD_EN; + wire [0:0]SR; + wire [21:0]in; + wire lsig_cmd_fetch_pause; + wire m_axi_s2mm_aclk; + wire p_0_in; + wire p_7_out; + wire p_9_out_0; + wire [0:0]\sig_byte_cntr_reg[0] ; + wire [0:0]\sig_byte_cntr_reg[3] ; + wire sig_clr_dbc_reg; + wire [28:6]sig_cmd_fifo_data_out; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + (* RTL_KEEP = "yes" *) wire [2:0]sig_cmdcntl_sm_state; + wire \sig_data_skid_reg_reg[7] ; + wire sig_dre2ibtt_eop; + wire sig_dre2ibtt_tlast; + wire sig_dre2ibtt_tstrb; + wire sig_ibtt2dre_tready; + wire sig_inhibit_rdy_n; + wire sig_init_reg; + wire sig_init_reg2; + wire sig_need_cmd_flush; + wire sig_rd_empty; + wire sig_sm_ld_dre_cmd; + wire sig_sm_ld_dre_cmd_ns; + wire sig_sm_pop_cmd_fifo; + wire sig_sm_pop_cmd_fifo_i_2_n_0; + wire sig_sm_pop_cmd_fifo_ns; + wire sig_stream_rst; + + (* KEEP = "yes" *) + FDRE \FSM_sequential_sig_cmdcntl_sm_state_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(I_DRE_CNTL_FIFO_n_29), + .Q(sig_cmdcntl_sm_state[0]), + .R(sig_stream_rst)); + (* KEEP = "yes" *) + FDRE \FSM_sequential_sig_cmdcntl_sm_state_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(I_DRE_CNTL_FIFO_n_28), + .Q(sig_cmdcntl_sm_state[1]), + .R(sig_stream_rst)); + (* KEEP = "yes" *) + FDRE \FSM_sequential_sig_cmdcntl_sm_state_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(I_DRE_CNTL_FIFO_n_27), + .Q(sig_cmdcntl_sm_state[2]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(I_DRE_CNTL_FIFO_n_24), + .Q(lsig_cmd_fetch_pause), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_INCLUDE_SCATTER.I_S2MM_SCATTER_n_30 ), + .Q(sig_need_cmd_flush), + .R(1'b0)); + Arty_Z7_20_axi_vdma_0_0_axi_datamover_s2mm_scatter \GEN_INCLUDE_SCATTER.I_S2MM_SCATTER + (.DOUT(DOUT), + .EMPTY(EMPTY), + .\FSM_sequential_sig_cmdcntl_sm_state_reg[0] (\GEN_INCLUDE_SCATTER.I_S2MM_SCATTER_n_11 ), + .\GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg (\GEN_INCLUDE_SCATTER.I_S2MM_SCATTER_n_30 ), + .\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1] (Q[1:0]), + .\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] (\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] (\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] (\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] (\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] (\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] (\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] (\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7] (\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7] ), + .\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] (\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ), + .\INCLUDE_PACKING.lsig_first_dbeat_reg (\INCLUDE_PACKING.lsig_first_dbeat_reg ), + .\INCLUDE_PACKING.lsig_first_dbeat_reg_0 (\INCLUDE_PACKING.lsig_first_dbeat_reg_0 ), + .Q(sig_rd_empty), + .RD_EN(RD_EN), + .SR(SR), + .lsig_cmd_fetch_pause(lsig_cmd_fetch_pause), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out({sig_cmd_fifo_data_out[23],sig_cmd_fifo_data_out[21:6]}), + .p_0_in(p_0_in), + .p_7_out(p_7_out), + .\sig_byte_cntr_reg[0] (\sig_byte_cntr_reg[0] ), + .\sig_byte_cntr_reg[3] (\sig_byte_cntr_reg[3] ), + .sig_clr_dbc_reg(sig_clr_dbc_reg), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .\sig_data_skid_reg_reg[7] (\sig_data_skid_reg_reg[7] ), + .sig_dre2ibtt_eop_reg_reg(sig_dre2ibtt_eop), + .sig_dre2ibtt_tlast(sig_dre2ibtt_tlast), + .sig_dre2ibtt_tstrb(sig_dre2ibtt_tstrb), + .sig_good_tlast_dbeat37_out__0(\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_good_tlast_dbeat37_out__0 ), + .sig_ibtt2dre_tready(sig_ibtt2dre_tready), + .sig_init_reg(sig_init_reg), + .sig_need_cmd_flush(sig_need_cmd_flush), + .sig_sm_ld_dre_cmd(sig_sm_ld_dre_cmd), + .sig_sm_pop_cmd_fifo(sig_sm_pop_cmd_fifo), + .sig_stream_rst(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(sig_sm_ld_dre_cmd), + .D(sig_cmd_fifo_data_out[26]), + .Q(Q[0]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(sig_sm_ld_dre_cmd), + .D(sig_cmd_fifo_data_out[27]), + .Q(Q[1]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(sig_sm_ld_dre_cmd), + .D(sig_cmd_fifo_data_out[28]), + .Q(Q[2]), + .R(sig_stream_rst)); + LUT3 #( + .INIT(8'h78)) + \INCLUDE_PACKING.lsig_0ffset_cntr[2]_i_2 + (.I0(Q[0]), + .I1(Q[1]), + .I2(Q[2]), + .O(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] )); + Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized7 I_DRE_CNTL_FIFO + (.D({I_DRE_CNTL_FIFO_n_27,I_DRE_CNTL_FIFO_n_28,I_DRE_CNTL_FIFO_n_29}), + .E(sig_sm_ld_dre_cmd), + .\FSM_sequential_sig_cmdcntl_sm_state_reg[0] (sig_sm_pop_cmd_fifo_i_2_n_0), + .\FSM_sequential_sig_cmdcntl_sm_state_reg[2] (sig_cmdcntl_sm_state), + .\GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg (I_DRE_CNTL_FIFO_n_24), + .\INFERRED_GEN.cnt_i_reg[0] (\INFERRED_GEN.cnt_i_reg[0] ), + .\INFERRED_GEN.cnt_i_reg[0]_0 (sig_inhibit_rdy_n), + .Q(sig_rd_empty), + .in(in), + .lsig_cmd_fetch_pause(lsig_cmd_fetch_pause), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out({sig_cmd_fifo_data_out[28:26],sig_cmd_fifo_data_out[23],sig_cmd_fifo_data_out[21:6]}), + .p_7_out(p_7_out), + .p_9_out_0(p_9_out_0), + .sig_cmd_empty_reg(\GEN_INCLUDE_SCATTER.I_S2MM_SCATTER_n_11 ), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_good_tlast_dbeat37_out__0(\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_good_tlast_dbeat37_out__0 ), + .sig_init_reg(sig_init_reg), + .sig_init_reg2(sig_init_reg2), + .sig_need_cmd_flush(sig_need_cmd_flush), + .sig_sm_ld_dre_cmd_ns(sig_sm_ld_dre_cmd_ns), + .sig_sm_pop_cmd_fifo(sig_sm_pop_cmd_fifo), + .sig_sm_pop_cmd_fifo_ns(sig_sm_pop_cmd_fifo_ns), + .sig_stream_rst(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + sig_sm_ld_dre_cmd_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_sm_ld_dre_cmd_ns), + .Q(sig_sm_ld_dre_cmd), + .R(sig_stream_rst)); + LUT2 #( + .INIT(4'h2)) + sig_sm_pop_cmd_fifo_i_2 + (.I0(sig_cmdcntl_sm_state[0]), + .I1(sig_cmdcntl_sm_state[2]), + .O(sig_sm_pop_cmd_fifo_i_2_n_0)); + FDRE #( + .INIT(1'b0)) + sig_sm_pop_cmd_fifo_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_sm_pop_cmd_fifo_ns), + .Q(sig_sm_pop_cmd_fifo), + .R(sig_stream_rst)); +endmodule + +(* ORIG_REF_NAME = "axi_datamover_s2mm_scatter" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_s2mm_scatter + (\sig_data_skid_reg_reg[7] , + sig_dre2ibtt_tstrb, + p_7_out, + \INCLUDE_PACKING.lsig_first_dbeat_reg , + \sig_byte_cntr_reg[0] , + sig_dre2ibtt_tlast, + RD_EN, + sig_good_tlast_dbeat37_out__0, + sig_dre2ibtt_eop_reg_reg, + SR, + \sig_byte_cntr_reg[3] , + \FSM_sequential_sig_cmdcntl_sm_state_reg[0] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] , + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] , + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] , + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] , + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] , + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] , + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] , + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] , + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] , + \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg , + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7] , + m_axi_s2mm_aclk, + out, + sig_stream_rst, + \INCLUDE_PACKING.lsig_first_dbeat_reg_0 , + sig_sm_ld_dre_cmd, + DOUT, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + EMPTY, + sig_ibtt2dre_tready, + sig_clr_dbc_reg, + Q, + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 , + sig_init_reg, + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 , + p_0_in, + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 , + lsig_cmd_fetch_pause, + sig_need_cmd_flush, + sig_sm_pop_cmd_fifo); + output \sig_data_skid_reg_reg[7] ; + output sig_dre2ibtt_tstrb; + output p_7_out; + output \INCLUDE_PACKING.lsig_first_dbeat_reg ; + output \sig_byte_cntr_reg[0] ; + output sig_dre2ibtt_tlast; + output RD_EN; + output sig_good_tlast_dbeat37_out__0; + output sig_dre2ibtt_eop_reg_reg; + output [0:0]SR; + output [0:0]\sig_byte_cntr_reg[3] ; + output \FSM_sequential_sig_cmdcntl_sm_state_reg[0] ; + output \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ; + output \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] ; + output [1:0]\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] ; + output [1:0]\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] ; + output [1:0]\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] ; + output [1:0]\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] ; + output [1:0]\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] ; + output [1:0]\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] ; + output [1:0]\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] ; + output [1:0]\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] ; + output \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg ; + output [7:0]\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7] ; + input m_axi_s2mm_aclk; + input [16:0]out; + input sig_stream_rst; + input \INCLUDE_PACKING.lsig_first_dbeat_reg_0 ; + input sig_sm_ld_dre_cmd; + input [8:0]DOUT; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input EMPTY; + input sig_ibtt2dre_tready; + input sig_clr_dbc_reg; + input [0:0]Q; + input [1:0]\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1] ; + input [1:0]\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ; + input sig_init_reg; + input \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ; + input p_0_in; + input \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ; + input lsig_cmd_fetch_pause; + input sig_need_cmd_flush; + input sig_sm_pop_cmd_fifo; + + wire [8:0]DOUT; + wire EMPTY; + wire \FSM_sequential_sig_cmdcntl_sm_state_reg[0] ; + wire \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg ; + wire \GEN_INDET_BTT.lsig_absorb2tlast_i_1_n_0 ; + wire [1:0]\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1] ; + wire [1:0]\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ; + wire [1:0]\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] ; + wire [1:0]\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ; + wire [1:0]\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ; + wire [1:0]\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ; + wire [1:0]\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ; + wire [1:0]\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ; + wire [7:0]\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7] ; + wire [1:0]\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ; + wire [1:0]\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ; + wire \INCLUDE_PACKING.lsig_first_dbeat_reg ; + wire \INCLUDE_PACKING.lsig_first_dbeat_reg_0 ; + wire I_TSTRB_FIFO_n_0; + wire I_TSTRB_FIFO_n_1; + wire I_TSTRB_FIFO_n_11; + wire I_TSTRB_FIFO_n_5; + wire I_TSTRB_FIFO_n_6; + wire I_TSTRB_FIFO_n_8; + wire I_TSTRB_FIFO_n_9; + wire [0:0]Q; + wire RD_EN; + wire SLICE_INSERTION_n_1; + wire SLICE_INSERTION_n_10; + wire SLICE_INSERTION_n_11; + wire SLICE_INSERTION_n_12; + wire SLICE_INSERTION_n_13; + wire SLICE_INSERTION_n_2; + wire SLICE_INSERTION_n_3; + wire SLICE_INSERTION_n_5; + wire SLICE_INSERTION_n_6; + wire SLICE_INSERTION_n_7; + wire SLICE_INSERTION_n_8; + wire SLICE_INSERTION_n_9; + wire [0:0]SR; + wire ld_btt_cntr_reg1; + wire ld_btt_cntr_reg2; + wire ld_btt_cntr_reg3; + wire lsig_absorb2tlast; + wire lsig_cmd_fetch_pause; + wire m_axi_s2mm_aclk; + wire [16:0]out; + wire p_0_in; + wire p_1_in2_in; + wire p_7_out; + wire [15:0]sel0; + wire [0:0]sig_btt_cntr; + wire sig_btt_cntr03_out; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire [15:0]sig_btt_cntr_dup; + wire [15:0]sig_btt_cntr_prv0; + wire sig_btt_cntr_prv0_carry__0_i_1_n_0; + wire sig_btt_cntr_prv0_carry__0_i_2_n_0; + wire sig_btt_cntr_prv0_carry__0_i_3_n_0; + wire sig_btt_cntr_prv0_carry__0_i_4_n_0; + wire sig_btt_cntr_prv0_carry__0_n_0; + wire sig_btt_cntr_prv0_carry__0_n_1; + wire sig_btt_cntr_prv0_carry__0_n_2; + wire sig_btt_cntr_prv0_carry__0_n_3; + wire sig_btt_cntr_prv0_carry__1_i_1_n_0; + wire sig_btt_cntr_prv0_carry__1_i_2_n_0; + wire sig_btt_cntr_prv0_carry__1_i_3_n_0; + wire sig_btt_cntr_prv0_carry__1_i_4_n_0; + wire sig_btt_cntr_prv0_carry__1_n_0; + wire sig_btt_cntr_prv0_carry__1_n_1; + wire sig_btt_cntr_prv0_carry__1_n_2; + wire sig_btt_cntr_prv0_carry__1_n_3; + wire sig_btt_cntr_prv0_carry__2_i_1_n_0; + wire sig_btt_cntr_prv0_carry__2_i_2_n_0; + wire sig_btt_cntr_prv0_carry__2_i_3_n_0; + wire sig_btt_cntr_prv0_carry__2_i_4_n_0; + wire sig_btt_cntr_prv0_carry__2_n_1; + wire sig_btt_cntr_prv0_carry__2_n_2; + wire sig_btt_cntr_prv0_carry__2_n_3; + wire sig_btt_cntr_prv0_carry_i_1_n_0; + wire sig_btt_cntr_prv0_carry_i_2_n_0; + wire sig_btt_cntr_prv0_carry_i_3_n_0; + wire sig_btt_cntr_prv0_carry_i_4_n_0; + wire sig_btt_cntr_prv0_carry_n_0; + wire sig_btt_cntr_prv0_carry_n_1; + wire sig_btt_cntr_prv0_carry_n_2; + wire sig_btt_cntr_prv0_carry_n_3; + wire \sig_btt_cntr_reg_n_0_[10] ; + wire \sig_btt_cntr_reg_n_0_[11] ; + wire \sig_btt_cntr_reg_n_0_[12] ; + wire \sig_btt_cntr_reg_n_0_[13] ; + wire \sig_btt_cntr_reg_n_0_[14] ; + wire \sig_btt_cntr_reg_n_0_[15] ; + wire \sig_btt_cntr_reg_n_0_[1] ; + wire \sig_btt_cntr_reg_n_0_[2] ; + wire \sig_btt_cntr_reg_n_0_[3] ; + wire \sig_btt_cntr_reg_n_0_[4] ; + wire \sig_btt_cntr_reg_n_0_[5] ; + wire \sig_btt_cntr_reg_n_0_[6] ; + wire \sig_btt_cntr_reg_n_0_[7] ; + wire \sig_btt_cntr_reg_n_0_[8] ; + wire \sig_btt_cntr_reg_n_0_[9] ; + wire sig_btt_eq_0; + wire sig_btt_eq_0_i_1_n_0; + wire sig_btt_eq_0_i_2_n_0; + wire sig_btt_eq_0_i_3_n_0; + wire sig_btt_eq_0_i_4_n_0; + wire sig_btt_eq_0_i_5_n_0; + wire sig_btt_eq_0_i_6_n_0; + wire sig_btt_lteq_max_first_incr; + wire sig_btt_lteq_max_first_incr0_carry__0_n_1; + wire sig_btt_lteq_max_first_incr0_carry__0_n_2; + wire sig_btt_lteq_max_first_incr0_carry__0_n_3; + wire sig_btt_lteq_max_first_incr0_carry_n_0; + wire sig_btt_lteq_max_first_incr0_carry_n_1; + wire sig_btt_lteq_max_first_incr0_carry_n_2; + wire sig_btt_lteq_max_first_incr0_carry_n_3; + wire \sig_byte_cntr_reg[0] ; + wire [0:0]\sig_byte_cntr_reg[3] ; + wire sig_clr_dbc_reg; + wire sig_cmd_full; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_curr_eof_reg; + wire sig_curr_eof_reg_i_1_n_0; + wire \sig_data_skid_reg_reg[7] ; + wire sig_dre2ibtt_eop_reg_reg; + wire sig_dre2ibtt_tlast; + wire sig_dre2ibtt_tstrb; + wire sig_eop_halt_xfer; + wire sig_eop_halt_xfer_i_1_n_0; + wire sig_eop_sent; + wire sig_eop_sent_reg; + wire sig_good_tlast_dbeat37_out__0; + wire sig_ibtt2dre_tready; + wire sig_inhibit_rdy_n; + wire sig_init_reg; + wire \sig_max_first_increment[0]_i_1_n_0 ; + wire \sig_max_first_increment_reg_n_0_[0] ; + wire sig_need_cmd_flush; + wire sig_rd_empty; + wire sig_sm_ld_dre_cmd; + wire sig_sm_pop_cmd_fifo; + wire sig_stream_rst; + wire sig_strm_tlast; + wire sig_strm_tvalid; + wire [2:2]sig_tstrb_fifo_data_out; + wire sig_valid_fifo_ld12_out; + wire [3:2]slice_insert_data; + wire slice_insert_valid; + wire [3:3]NLW_sig_btt_cntr_prv0_carry__2_CO_UNCONNECTED; + wire [3:0]NLW_sig_btt_lteq_max_first_incr0_carry_O_UNCONNECTED; + wire [3:0]NLW_sig_btt_lteq_max_first_incr0_carry__0_O_UNCONNECTED; + + LUT2 #( + .INIT(4'h2)) + \FSM_sequential_sig_cmdcntl_sm_state[0]_i_3 + (.I0(p_7_out), + .I1(Q), + .O(\FSM_sequential_sig_cmdcntl_sm_state_reg[0] )); + LUT6 #( + .INIT(64'h0000F000F040F000)) + \GEN_INDET_BTT.lsig_absorb2tlast_i_1 + (.I0(sig_rd_empty), + .I1(sig_tstrb_fifo_data_out), + .I2(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I3(lsig_absorb2tlast), + .I4(sig_strm_tvalid), + .I5(sig_strm_tlast), + .O(\GEN_INDET_BTT.lsig_absorb2tlast_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_INDET_BTT.lsig_absorb2tlast_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_INDET_BTT.lsig_absorb2tlast_i_1_n_0 ), + .Q(lsig_absorb2tlast), + .R(1'b0)); + Arty_Z7_20_axi_vdma_0_0_axi_datamover_mssai_skid_buf I_MSSAI_SKID_BUF + (.DOUT(DOUT), + .E(I_TSTRB_FIFO_n_9), + .EMPTY(EMPTY), + .\GEN_INDET_BTT.lsig_absorb2tlast_reg (I_TSTRB_FIFO_n_11), + .\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][0] (sig_strm_tvalid), + .\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][0]_0 (\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] [0]), + .\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][0] (\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] [0]), + .\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][0] (\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] [0]), + .\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][0] (\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] [0]), + .\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][0] (\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] [0]), + .\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][0] (\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] [0]), + .\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][0] (\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] [0]), + .\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7] (\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7] ), + .\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][0] (\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] [0]), + .\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ), + .\INFERRED_GEN.cnt_i_reg[4] (\sig_byte_cntr_reg[0] ), + .Q(sig_rd_empty), + .RD_EN(RD_EN), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(p_1_in2_in), + .p_0_in(p_0_in), + .\sig_byte_cntr_reg[3] (\sig_byte_cntr_reg[3] ), + .sig_clr_dbc_reg(sig_clr_dbc_reg), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .\sig_data_skid_reg_reg[7]_0 (\sig_data_skid_reg_reg[7] ), + .sig_dre2ibtt_eop_reg_reg(sig_dre2ibtt_eop_reg_reg), + .sig_dre2ibtt_tstrb(sig_dre2ibtt_tstrb), + .sig_eop_halt_xfer(sig_eop_halt_xfer), + .sig_init_reg(sig_init_reg), + .sig_stream_rst(sig_stream_rst), + .sig_strm_tlast(sig_strm_tlast)); + Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized8 I_TSTRB_FIFO + (.E(I_TSTRB_FIFO_n_9), + .\GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg (\GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg ), + .\GEN_INDET_BTT.lsig_absorb2tlast_reg (sig_tstrb_fifo_data_out), + .\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1] (\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] (\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] [1]), + .\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] (\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] [1]), + .\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] (\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] [1]), + .\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] (\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] [1]), + .\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] (\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] [1]), + .\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] (\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] [1]), + .\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] (\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] [1]), + .\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] (\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] [1]), + .\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ), + .\INCLUDE_PACKING.lsig_first_dbeat_reg (\INCLUDE_PACKING.lsig_first_dbeat_reg ), + .\INCLUDE_PACKING.lsig_first_dbeat_reg_0 (\INCLUDE_PACKING.lsig_first_dbeat_reg_0 ), + .\INFERRED_GEN.cnt_i_reg[1] (I_TSTRB_FIFO_n_0), + .Q(sig_rd_empty), + .SR(I_TSTRB_FIFO_n_8), + .SS(I_TSTRB_FIFO_n_1), + .in(slice_insert_data), + .lsig_absorb2tlast(lsig_absorb2tlast), + .lsig_cmd_fetch_pause(lsig_cmd_fetch_pause), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(p_1_in2_in), + .p_0_in(p_0_in), + .p_7_out(p_7_out), + .\sig_byte_cntr_reg[0] (\sig_byte_cntr_reg[0] ), + .\sig_byte_cntr_reg[7] (SR), + .sig_clr_dbc_reg(sig_clr_dbc_reg), + .sig_cmd_empty_reg(I_TSTRB_FIFO_n_6), + .sig_cmd_full(sig_cmd_full), + .sig_cmd_full_reg(I_TSTRB_FIFO_n_5), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_dre2ibtt_tlast(sig_dre2ibtt_tlast), + .sig_eop_halt_xfer(sig_eop_halt_xfer), + .sig_eop_sent(sig_eop_sent), + .sig_eop_sent_reg(sig_eop_sent_reg), + .sig_good_tlast_dbeat37_out__0(sig_good_tlast_dbeat37_out__0), + .sig_ibtt2dre_tready(sig_ibtt2dre_tready), + .sig_inhibit_rdy_n(sig_inhibit_rdy_n), + .sig_last_reg_out_reg(sig_dre2ibtt_eop_reg_reg), + .sig_m_valid_out_reg(sig_strm_tvalid), + .sig_need_cmd_flush(sig_need_cmd_flush), + .sig_s_ready_dup4_reg(I_TSTRB_FIFO_n_11), + .sig_sm_ld_dre_cmd(sig_sm_ld_dre_cmd), + .sig_sm_pop_cmd_fifo(sig_sm_pop_cmd_fifo), + .sig_stream_rst(sig_stream_rst), + .sig_strm_tlast(sig_strm_tlast), + .slice_insert_valid(slice_insert_valid)); + Arty_Z7_20_axi_vdma_0_0_axi_datamover_slice SLICE_INSERTION + (.CO(sig_btt_lteq_max_first_incr), + .DI(SLICE_INSERTION_n_9), + .E(sig_btt_cntr03_out), + .FIFO_Full_reg(I_TSTRB_FIFO_n_0), + .S({SLICE_INSERTION_n_5,SLICE_INSERTION_n_6,SLICE_INSERTION_n_7,SLICE_INSERTION_n_8}), + .in(slice_insert_data), + .ld_btt_cntr_reg1(ld_btt_cntr_reg1), + .ld_btt_cntr_reg1_reg(SLICE_INSERTION_n_3), + .ld_btt_cntr_reg2(ld_btt_cntr_reg2), + .ld_btt_cntr_reg2_reg(SLICE_INSERTION_n_2), + .ld_btt_cntr_reg3(ld_btt_cntr_reg3), + .ld_btt_cntr_reg3_reg(SLICE_INSERTION_n_1), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(sig_btt_cntr_dup), + .sig_btt_eq_0(sig_btt_eq_0), + .sig_cmd_full(sig_cmd_full), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_curr_eof_reg(sig_curr_eof_reg), + .sig_eop_sent(sig_eop_sent), + .sig_inhibit_rdy_n(sig_inhibit_rdy_n), + .\sig_max_first_increment_reg[0] (\sig_max_first_increment_reg_n_0_[0] ), + .sig_sm_ld_dre_cmd(sig_sm_ld_dre_cmd), + .sig_stream_rst(sig_stream_rst), + .sig_valid_fifo_ld12_out(sig_valid_fifo_ld12_out), + .slice_insert_valid(slice_insert_valid), + .\storage_data_reg[3]_0 ({SLICE_INSERTION_n_10,SLICE_INSERTION_n_11,SLICE_INSERTION_n_12,SLICE_INSERTION_n_13})); + FDRE #( + .INIT(1'b0)) + ld_btt_cntr_reg1_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(SLICE_INSERTION_n_3), + .Q(ld_btt_cntr_reg1), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + ld_btt_cntr_reg2_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(SLICE_INSERTION_n_2), + .Q(ld_btt_cntr_reg2), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + ld_btt_cntr_reg3_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(SLICE_INSERTION_n_1), + .Q(ld_btt_cntr_reg3), + .R(1'b0)); + LUT4 #( + .INIT(16'hCCAC)) + \sig_btt_cntr[0]_i_1__0 + (.I0(out[0]), + .I1(sig_btt_cntr_prv0[0]), + .I2(sig_sm_ld_dre_cmd), + .I3(sig_cmd_full), + .O(sel0[0])); + LUT4 #( + .INIT(16'hCCAC)) + \sig_btt_cntr[10]_i_1__0 + (.I0(out[10]), + .I1(sig_btt_cntr_prv0[10]), + .I2(sig_sm_ld_dre_cmd), + .I3(sig_cmd_full), + .O(sel0[10])); + LUT4 #( + .INIT(16'hCCAC)) + \sig_btt_cntr[11]_i_1__0 + (.I0(out[11]), + .I1(sig_btt_cntr_prv0[11]), + .I2(sig_sm_ld_dre_cmd), + .I3(sig_cmd_full), + .O(sel0[11])); + LUT4 #( + .INIT(16'hCCAC)) + \sig_btt_cntr[12]_i_1__0 + (.I0(out[12]), + .I1(sig_btt_cntr_prv0[12]), + .I2(sig_sm_ld_dre_cmd), + .I3(sig_cmd_full), + .O(sel0[12])); + LUT4 #( + .INIT(16'hCCAC)) + \sig_btt_cntr[13]_i_1__0 + (.I0(out[13]), + .I1(sig_btt_cntr_prv0[13]), + .I2(sig_sm_ld_dre_cmd), + .I3(sig_cmd_full), + .O(sel0[13])); + LUT4 #( + .INIT(16'hCCAC)) + \sig_btt_cntr[14]_i_1__0 + (.I0(out[14]), + .I1(sig_btt_cntr_prv0[14]), + .I2(sig_sm_ld_dre_cmd), + .I3(sig_cmd_full), + .O(sel0[14])); + LUT4 #( + .INIT(16'hCCAC)) + \sig_btt_cntr[15]_i_3 + (.I0(out[15]), + .I1(sig_btt_cntr_prv0[15]), + .I2(sig_sm_ld_dre_cmd), + .I3(sig_cmd_full), + .O(sel0[15])); + LUT4 #( + .INIT(16'hCCAC)) + \sig_btt_cntr[1]_i_1__0 + (.I0(out[1]), + .I1(sig_btt_cntr_prv0[1]), + .I2(sig_sm_ld_dre_cmd), + .I3(sig_cmd_full), + .O(sel0[1])); + LUT4 #( + .INIT(16'hCCAC)) + \sig_btt_cntr[2]_i_1__0 + (.I0(out[2]), + .I1(sig_btt_cntr_prv0[2]), + .I2(sig_sm_ld_dre_cmd), + .I3(sig_cmd_full), + .O(sel0[2])); + LUT4 #( + .INIT(16'hCCAC)) + \sig_btt_cntr[3]_i_1__0 + (.I0(out[3]), + .I1(sig_btt_cntr_prv0[3]), + .I2(sig_sm_ld_dre_cmd), + .I3(sig_cmd_full), + .O(sel0[3])); + LUT4 #( + .INIT(16'hCCAC)) + \sig_btt_cntr[4]_i_1__0 + (.I0(out[4]), + .I1(sig_btt_cntr_prv0[4]), + .I2(sig_sm_ld_dre_cmd), + .I3(sig_cmd_full), + .O(sel0[4])); + LUT4 #( + .INIT(16'hCCAC)) + \sig_btt_cntr[5]_i_1__0 + (.I0(out[5]), + .I1(sig_btt_cntr_prv0[5]), + .I2(sig_sm_ld_dre_cmd), + .I3(sig_cmd_full), + .O(sel0[5])); + LUT4 #( + .INIT(16'hCCAC)) + \sig_btt_cntr[6]_i_1__0 + (.I0(out[6]), + .I1(sig_btt_cntr_prv0[6]), + .I2(sig_sm_ld_dre_cmd), + .I3(sig_cmd_full), + .O(sel0[6])); + LUT4 #( + .INIT(16'hCCAC)) + \sig_btt_cntr[7]_i_1__0 + (.I0(out[7]), + .I1(sig_btt_cntr_prv0[7]), + .I2(sig_sm_ld_dre_cmd), + .I3(sig_cmd_full), + .O(sel0[7])); + LUT4 #( + .INIT(16'hCCAC)) + \sig_btt_cntr[8]_i_1__0 + (.I0(out[8]), + .I1(sig_btt_cntr_prv0[8]), + .I2(sig_sm_ld_dre_cmd), + .I3(sig_cmd_full), + .O(sel0[8])); + LUT4 #( + .INIT(16'hCCAC)) + \sig_btt_cntr[9]_i_1__0 + (.I0(out[9]), + .I1(sig_btt_cntr_prv0[9]), + .I2(sig_sm_ld_dre_cmd), + .I3(sig_cmd_full), + .O(sel0[9])); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_dup_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[0]), + .Q(sig_btt_cntr_dup[0]), + .R(I_TSTRB_FIFO_n_8)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_dup_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[10]), + .Q(sig_btt_cntr_dup[10]), + .R(I_TSTRB_FIFO_n_8)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_dup_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[11]), + .Q(sig_btt_cntr_dup[11]), + .R(I_TSTRB_FIFO_n_8)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_dup_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[12]), + .Q(sig_btt_cntr_dup[12]), + .R(I_TSTRB_FIFO_n_8)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_dup_reg[13] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[13]), + .Q(sig_btt_cntr_dup[13]), + .R(I_TSTRB_FIFO_n_8)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_dup_reg[14] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[14]), + .Q(sig_btt_cntr_dup[14]), + .R(I_TSTRB_FIFO_n_8)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_dup_reg[15] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[15]), + .Q(sig_btt_cntr_dup[15]), + .R(I_TSTRB_FIFO_n_8)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_dup_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[1]), + .Q(sig_btt_cntr_dup[1]), + .R(I_TSTRB_FIFO_n_8)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_dup_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[2]), + .Q(sig_btt_cntr_dup[2]), + .R(I_TSTRB_FIFO_n_8)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_dup_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[3]), + .Q(sig_btt_cntr_dup[3]), + .R(I_TSTRB_FIFO_n_8)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_dup_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[4]), + .Q(sig_btt_cntr_dup[4]), + .R(I_TSTRB_FIFO_n_8)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_dup_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[5]), + .Q(sig_btt_cntr_dup[5]), + .R(I_TSTRB_FIFO_n_8)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_dup_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[6]), + .Q(sig_btt_cntr_dup[6]), + .R(I_TSTRB_FIFO_n_8)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_dup_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[7]), + .Q(sig_btt_cntr_dup[7]), + .R(I_TSTRB_FIFO_n_8)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_dup_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[8]), + .Q(sig_btt_cntr_dup[8]), + .R(I_TSTRB_FIFO_n_8)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_dup_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[9]), + .Q(sig_btt_cntr_dup[9]), + .R(I_TSTRB_FIFO_n_8)); + CARRY4 sig_btt_cntr_prv0_carry + (.CI(1'b0), + .CO({sig_btt_cntr_prv0_carry_n_0,sig_btt_cntr_prv0_carry_n_1,sig_btt_cntr_prv0_carry_n_2,sig_btt_cntr_prv0_carry_n_3}), + .CYINIT(1'b1), + .DI(sig_btt_cntr_dup[3:0]), + .O(sig_btt_cntr_prv0[3:0]), + .S({sig_btt_cntr_prv0_carry_i_1_n_0,sig_btt_cntr_prv0_carry_i_2_n_0,sig_btt_cntr_prv0_carry_i_3_n_0,sig_btt_cntr_prv0_carry_i_4_n_0})); + CARRY4 sig_btt_cntr_prv0_carry__0 + (.CI(sig_btt_cntr_prv0_carry_n_0), + .CO({sig_btt_cntr_prv0_carry__0_n_0,sig_btt_cntr_prv0_carry__0_n_1,sig_btt_cntr_prv0_carry__0_n_2,sig_btt_cntr_prv0_carry__0_n_3}), + .CYINIT(1'b0), + .DI(sig_btt_cntr_dup[7:4]), + .O(sig_btt_cntr_prv0[7:4]), + .S({sig_btt_cntr_prv0_carry__0_i_1_n_0,sig_btt_cntr_prv0_carry__0_i_2_n_0,sig_btt_cntr_prv0_carry__0_i_3_n_0,sig_btt_cntr_prv0_carry__0_i_4_n_0})); + LUT3 #( + .INIT(8'h95)) + sig_btt_cntr_prv0_carry__0_i_1 + (.I0(sig_btt_cntr_dup[7]), + .I1(sig_btt_lteq_max_first_incr), + .I2(\sig_btt_cntr_reg_n_0_[7] ), + .O(sig_btt_cntr_prv0_carry__0_i_1_n_0)); + LUT3 #( + .INIT(8'h95)) + sig_btt_cntr_prv0_carry__0_i_2 + (.I0(sig_btt_cntr_dup[6]), + .I1(sig_btt_lteq_max_first_incr), + .I2(\sig_btt_cntr_reg_n_0_[6] ), + .O(sig_btt_cntr_prv0_carry__0_i_2_n_0)); + LUT3 #( + .INIT(8'h95)) + sig_btt_cntr_prv0_carry__0_i_3 + (.I0(sig_btt_cntr_dup[5]), + .I1(sig_btt_lteq_max_first_incr), + .I2(\sig_btt_cntr_reg_n_0_[5] ), + .O(sig_btt_cntr_prv0_carry__0_i_3_n_0)); + LUT3 #( + .INIT(8'h95)) + sig_btt_cntr_prv0_carry__0_i_4 + (.I0(sig_btt_cntr_dup[4]), + .I1(sig_btt_lteq_max_first_incr), + .I2(\sig_btt_cntr_reg_n_0_[4] ), + .O(sig_btt_cntr_prv0_carry__0_i_4_n_0)); + CARRY4 sig_btt_cntr_prv0_carry__1 + (.CI(sig_btt_cntr_prv0_carry__0_n_0), + .CO({sig_btt_cntr_prv0_carry__1_n_0,sig_btt_cntr_prv0_carry__1_n_1,sig_btt_cntr_prv0_carry__1_n_2,sig_btt_cntr_prv0_carry__1_n_3}), + .CYINIT(1'b0), + .DI(sig_btt_cntr_dup[11:8]), + .O(sig_btt_cntr_prv0[11:8]), + .S({sig_btt_cntr_prv0_carry__1_i_1_n_0,sig_btt_cntr_prv0_carry__1_i_2_n_0,sig_btt_cntr_prv0_carry__1_i_3_n_0,sig_btt_cntr_prv0_carry__1_i_4_n_0})); + LUT3 #( + .INIT(8'h95)) + sig_btt_cntr_prv0_carry__1_i_1 + (.I0(sig_btt_cntr_dup[11]), + .I1(sig_btt_lteq_max_first_incr), + .I2(\sig_btt_cntr_reg_n_0_[11] ), + .O(sig_btt_cntr_prv0_carry__1_i_1_n_0)); + LUT3 #( + .INIT(8'h95)) + sig_btt_cntr_prv0_carry__1_i_2 + (.I0(sig_btt_cntr_dup[10]), + .I1(sig_btt_lteq_max_first_incr), + .I2(\sig_btt_cntr_reg_n_0_[10] ), + .O(sig_btt_cntr_prv0_carry__1_i_2_n_0)); + LUT3 #( + .INIT(8'h95)) + sig_btt_cntr_prv0_carry__1_i_3 + (.I0(sig_btt_cntr_dup[9]), + .I1(sig_btt_lteq_max_first_incr), + .I2(\sig_btt_cntr_reg_n_0_[9] ), + .O(sig_btt_cntr_prv0_carry__1_i_3_n_0)); + LUT3 #( + .INIT(8'h95)) + sig_btt_cntr_prv0_carry__1_i_4 + (.I0(sig_btt_cntr_dup[8]), + .I1(sig_btt_lteq_max_first_incr), + .I2(\sig_btt_cntr_reg_n_0_[8] ), + .O(sig_btt_cntr_prv0_carry__1_i_4_n_0)); + CARRY4 sig_btt_cntr_prv0_carry__2 + (.CI(sig_btt_cntr_prv0_carry__1_n_0), + .CO({NLW_sig_btt_cntr_prv0_carry__2_CO_UNCONNECTED[3],sig_btt_cntr_prv0_carry__2_n_1,sig_btt_cntr_prv0_carry__2_n_2,sig_btt_cntr_prv0_carry__2_n_3}), + .CYINIT(1'b0), + .DI({1'b0,sig_btt_cntr_dup[14:12]}), + .O(sig_btt_cntr_prv0[15:12]), + .S({sig_btt_cntr_prv0_carry__2_i_1_n_0,sig_btt_cntr_prv0_carry__2_i_2_n_0,sig_btt_cntr_prv0_carry__2_i_3_n_0,sig_btt_cntr_prv0_carry__2_i_4_n_0})); + LUT3 #( + .INIT(8'h95)) + sig_btt_cntr_prv0_carry__2_i_1 + (.I0(sig_btt_cntr_dup[15]), + .I1(sig_btt_lteq_max_first_incr), + .I2(\sig_btt_cntr_reg_n_0_[15] ), + .O(sig_btt_cntr_prv0_carry__2_i_1_n_0)); + LUT3 #( + .INIT(8'h95)) + sig_btt_cntr_prv0_carry__2_i_2 + (.I0(sig_btt_cntr_dup[14]), + .I1(sig_btt_lteq_max_first_incr), + .I2(\sig_btt_cntr_reg_n_0_[14] ), + .O(sig_btt_cntr_prv0_carry__2_i_2_n_0)); + LUT3 #( + .INIT(8'h95)) + sig_btt_cntr_prv0_carry__2_i_3 + (.I0(sig_btt_cntr_dup[13]), + .I1(sig_btt_lteq_max_first_incr), + .I2(\sig_btt_cntr_reg_n_0_[13] ), + .O(sig_btt_cntr_prv0_carry__2_i_3_n_0)); + LUT3 #( + .INIT(8'h95)) + sig_btt_cntr_prv0_carry__2_i_4 + (.I0(sig_btt_cntr_dup[12]), + .I1(sig_btt_lteq_max_first_incr), + .I2(\sig_btt_cntr_reg_n_0_[12] ), + .O(sig_btt_cntr_prv0_carry__2_i_4_n_0)); + LUT3 #( + .INIT(8'h95)) + sig_btt_cntr_prv0_carry_i_1 + (.I0(sig_btt_cntr_dup[3]), + .I1(sig_btt_lteq_max_first_incr), + .I2(\sig_btt_cntr_reg_n_0_[3] ), + .O(sig_btt_cntr_prv0_carry_i_1_n_0)); + LUT3 #( + .INIT(8'h95)) + sig_btt_cntr_prv0_carry_i_2 + (.I0(sig_btt_cntr_dup[2]), + .I1(sig_btt_lteq_max_first_incr), + .I2(\sig_btt_cntr_reg_n_0_[2] ), + .O(sig_btt_cntr_prv0_carry_i_2_n_0)); + LUT3 #( + .INIT(8'h95)) + sig_btt_cntr_prv0_carry_i_3 + (.I0(sig_btt_cntr_dup[1]), + .I1(sig_btt_lteq_max_first_incr), + .I2(\sig_btt_cntr_reg_n_0_[1] ), + .O(sig_btt_cntr_prv0_carry_i_3_n_0)); + LUT4 #( + .INIT(16'hA965)) + sig_btt_cntr_prv0_carry_i_4 + (.I0(sig_btt_cntr_dup[0]), + .I1(sig_btt_lteq_max_first_incr), + .I2(\sig_max_first_increment_reg_n_0_[0] ), + .I3(sig_btt_cntr), + .O(sig_btt_cntr_prv0_carry_i_4_n_0)); + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[0]), + .Q(sig_btt_cntr), + .R(I_TSTRB_FIFO_n_8)); + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[10]), + .Q(\sig_btt_cntr_reg_n_0_[10] ), + .R(I_TSTRB_FIFO_n_8)); + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[11]), + .Q(\sig_btt_cntr_reg_n_0_[11] ), + .R(I_TSTRB_FIFO_n_8)); + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[12]), + .Q(\sig_btt_cntr_reg_n_0_[12] ), + .R(I_TSTRB_FIFO_n_8)); + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_reg[13] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[13]), + .Q(\sig_btt_cntr_reg_n_0_[13] ), + .R(I_TSTRB_FIFO_n_8)); + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_reg[14] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[14]), + .Q(\sig_btt_cntr_reg_n_0_[14] ), + .R(I_TSTRB_FIFO_n_8)); + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_reg[15] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[15]), + .Q(\sig_btt_cntr_reg_n_0_[15] ), + .R(I_TSTRB_FIFO_n_8)); + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[1]), + .Q(\sig_btt_cntr_reg_n_0_[1] ), + .R(I_TSTRB_FIFO_n_8)); + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[2]), + .Q(\sig_btt_cntr_reg_n_0_[2] ), + .R(I_TSTRB_FIFO_n_8)); + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[3]), + .Q(\sig_btt_cntr_reg_n_0_[3] ), + .R(I_TSTRB_FIFO_n_8)); + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[4]), + .Q(\sig_btt_cntr_reg_n_0_[4] ), + .R(I_TSTRB_FIFO_n_8)); + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[5]), + .Q(\sig_btt_cntr_reg_n_0_[5] ), + .R(I_TSTRB_FIFO_n_8)); + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[6]), + .Q(\sig_btt_cntr_reg_n_0_[6] ), + .R(I_TSTRB_FIFO_n_8)); + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[7]), + .Q(\sig_btt_cntr_reg_n_0_[7] ), + .R(I_TSTRB_FIFO_n_8)); + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[8]), + .Q(\sig_btt_cntr_reg_n_0_[8] ), + .R(I_TSTRB_FIFO_n_8)); + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \sig_btt_cntr_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(sig_btt_cntr03_out), + .D(sel0[9]), + .Q(\sig_btt_cntr_reg_n_0_[9] ), + .R(I_TSTRB_FIFO_n_8)); + LUT6 #( + .INIT(64'hFFFFFFFF2222222E)) + sig_btt_eq_0_i_1 + (.I0(sig_btt_eq_0), + .I1(sig_btt_cntr03_out), + .I2(sig_btt_eq_0_i_2_n_0), + .I3(sig_btt_eq_0_i_3_n_0), + .I4(sig_btt_eq_0_i_4_n_0), + .I5(I_TSTRB_FIFO_n_8), + .O(sig_btt_eq_0_i_1_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + sig_btt_eq_0_i_2 + (.I0(sel0[5]), + .I1(sel0[4]), + .I2(sel0[7]), + .I3(sel0[6]), + .I4(sig_btt_eq_0_i_5_n_0), + .I5(sig_btt_eq_0_i_6_n_0), + .O(sig_btt_eq_0_i_2_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFEEFA)) + sig_btt_eq_0_i_3 + (.I0(sel0[15]), + .I1(out[14]), + .I2(sig_btt_cntr_prv0[14]), + .I3(sig_curr_eof_reg_i_1_n_0), + .I4(sel0[12]), + .I5(sel0[13]), + .O(sig_btt_eq_0_i_3_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFEEFA)) + sig_btt_eq_0_i_4 + (.I0(sel0[10]), + .I1(out[11]), + .I2(sig_btt_cntr_prv0[11]), + .I3(sig_curr_eof_reg_i_1_n_0), + .I4(sel0[8]), + .I5(sel0[9]), + .O(sig_btt_eq_0_i_4_n_0)); + LUT6 #( + .INIT(64'hFFFFAFAAFCFFACAA)) + sig_btt_eq_0_i_5 + (.I0(sig_btt_cntr_prv0[1]), + .I1(out[1]), + .I2(sig_cmd_full), + .I3(sig_sm_ld_dre_cmd), + .I4(sig_btt_cntr_prv0[0]), + .I5(out[0]), + .O(sig_btt_eq_0_i_5_n_0)); + LUT6 #( + .INIT(64'hFFFFAFAAFCFFACAA)) + sig_btt_eq_0_i_6 + (.I0(sig_btt_cntr_prv0[3]), + .I1(out[3]), + .I2(sig_cmd_full), + .I3(sig_sm_ld_dre_cmd), + .I4(sig_btt_cntr_prv0[2]), + .I5(out[2]), + .O(sig_btt_eq_0_i_6_n_0)); + FDRE #( + .INIT(1'b0)) + sig_btt_eq_0_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_btt_eq_0_i_1_n_0), + .Q(sig_btt_eq_0), + .R(1'b0)); + CARRY4 sig_btt_lteq_max_first_incr0_carry + (.CI(1'b0), + .CO({sig_btt_lteq_max_first_incr0_carry_n_0,sig_btt_lteq_max_first_incr0_carry_n_1,sig_btt_lteq_max_first_incr0_carry_n_2,sig_btt_lteq_max_first_incr0_carry_n_3}), + .CYINIT(1'b1), + .DI({1'b0,1'b0,1'b0,SLICE_INSERTION_n_9}), + .O(NLW_sig_btt_lteq_max_first_incr0_carry_O_UNCONNECTED[3:0]), + .S({SLICE_INSERTION_n_5,SLICE_INSERTION_n_6,SLICE_INSERTION_n_7,SLICE_INSERTION_n_8})); + CARRY4 sig_btt_lteq_max_first_incr0_carry__0 + (.CI(sig_btt_lteq_max_first_incr0_carry_n_0), + .CO({sig_btt_lteq_max_first_incr,sig_btt_lteq_max_first_incr0_carry__0_n_1,sig_btt_lteq_max_first_incr0_carry__0_n_2,sig_btt_lteq_max_first_incr0_carry__0_n_3}), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(NLW_sig_btt_lteq_max_first_incr0_carry__0_O_UNCONNECTED[3:0]), + .S({SLICE_INSERTION_n_10,SLICE_INSERTION_n_11,SLICE_INSERTION_n_12,SLICE_INSERTION_n_13})); + FDRE #( + .INIT(1'b0)) + sig_cmd_empty_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(I_TSTRB_FIFO_n_6), + .Q(p_7_out), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + sig_cmd_full_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(I_TSTRB_FIFO_n_5), + .Q(sig_cmd_full), + .R(1'b0)); + LUT2 #( + .INIT(4'h2)) + sig_curr_eof_reg_i_1 + (.I0(sig_sm_ld_dre_cmd), + .I1(sig_cmd_full), + .O(sig_curr_eof_reg_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + sig_curr_eof_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(sig_curr_eof_reg_i_1_n_0), + .D(out[16]), + .Q(sig_curr_eof_reg), + .R(I_TSTRB_FIFO_n_1)); + LUT3 #( + .INIT(8'hF4)) + sig_eop_halt_xfer_i_1 + (.I0(sig_valid_fifo_ld12_out), + .I1(sig_eop_halt_xfer), + .I2(I_TSTRB_FIFO_n_8), + .O(sig_eop_halt_xfer_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + sig_eop_halt_xfer_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_eop_halt_xfer_i_1_n_0), + .Q(sig_eop_halt_xfer), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + sig_eop_sent_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_eop_sent), + .Q(sig_eop_sent_reg), + .R(I_TSTRB_FIFO_n_1)); + LUT4 #( + .INIT(16'hFFBA)) + \sig_max_first_increment[0]_i_1 + (.I0(sig_valid_fifo_ld12_out), + .I1(sig_cmd_full), + .I2(sig_sm_ld_dre_cmd), + .I3(\sig_max_first_increment_reg_n_0_[0] ), + .O(\sig_max_first_increment[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_max_first_increment_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\sig_max_first_increment[0]_i_1_n_0 ), + .Q(\sig_max_first_increment_reg_n_0_[0] ), + .R(sig_stream_rst)); +endmodule + +(* ORIG_REF_NAME = "axi_datamover_sfifo_autord" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_sfifo_autord + (DOBDO, + out, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram , + sig_ok_to_post_rd_addr_reg, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg , + \gc1.count_reg[7] , + \INFERRED_GEN.cnt_i_reg[2] , + DIN, + \sig_user_skid_reg_reg[0] , + dm2linebuf_mm2s_tdata, + m_axi_mm2s_aclk, + E, + SR, + m_axi_mm2s_rdata, + DIBDI, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_posted_to_axi_2_reg, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , + Q, + lsig_cmd_loaded, + ram_full_i_reg, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 , + \sig_token_cntr_reg[0] , + \sig_token_cntr_reg[3] , + ram_full_i_reg_0); + output [0:0]DOBDO; + output out; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; + output sig_ok_to_post_rd_addr_reg; + output \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + output [0:0]\gc1.count_reg[7] ; + output \INFERRED_GEN.cnt_i_reg[2] ; + output [0:0]DIN; + output \sig_user_skid_reg_reg[0] ; + output [31:0]dm2linebuf_mm2s_tdata; + input m_axi_mm2s_aclk; + input [0:0]E; + input [0:0]SR; + input [63:0]m_axi_mm2s_rdata; + input [1:0]DIBDI; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_posted_to_axi_2_reg; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + input [0:0]Q; + input lsig_cmd_loaded; + input ram_full_i_reg; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; + input \sig_token_cntr_reg[0] ; + input [3:0]\sig_token_cntr_reg[3] ; + input [0:0]ram_full_i_reg_0; + + wire \BLK_MEM.I_SYNC_FIFOGEN_FIFO_n_5 ; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; + wire [1:0]DIBDI; + wire [0:0]DIN; + wire [0:0]DOBDO; + wire [0:0]E; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; + wire \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + wire \INFERRED_GEN.cnt_i_reg[2] ; + wire [0:0]Q; + wire [0:0]SR; + wire [31:0]dm2linebuf_mm2s_tdata; + wire [0:0]\gc1.count_reg[7] ; + wire hold_ff_q; + wire lsig_cmd_loaded; + wire m_axi_mm2s_aclk; + wire [63:0]m_axi_mm2s_rdata; + wire out; + wire ram_full_i_reg; + wire [0:0]ram_full_i_reg_0; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_ok_to_post_rd_addr_reg; + wire sig_posted_to_axi_2_reg; + wire \sig_token_cntr_reg[0] ; + wire [3:0]\sig_token_cntr_reg[3] ; + wire \sig_user_skid_reg_reg[0] ; + + Arty_Z7_20_axi_vdma_0_0_sync_fifo_fg \BLK_MEM.I_SYNC_FIFOGEN_FIFO + (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ), + .DIBDI(DIBDI), + .DIN(DIN), + .DOBDO(DOBDO), + .E(E), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .\INCLUDE_UNPACKING.lsig_cmd_loaded_reg (\INCLUDE_UNPACKING.lsig_cmd_loaded_reg ), + .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ), + .Q(Q), + .SR(SR), + .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), + .\gc1.count_reg[7] (\gc1.count_reg[7] ), + .hold_ff_q(hold_ff_q), + .hold_ff_q_reg(\BLK_MEM.I_SYNC_FIFOGEN_FIFO_n_5 ), + .lsig_cmd_loaded(lsig_cmd_loaded), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .m_axi_mm2s_rdata(m_axi_mm2s_rdata), + .out(out), + .ram_full_i_reg(ram_full_i_reg), + .ram_full_i_reg_0(ram_full_i_reg_0), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_ok_to_post_rd_addr_reg(sig_ok_to_post_rd_addr_reg), + .sig_posted_to_axi_2_reg(sig_posted_to_axi_2_reg), + .\sig_token_cntr_reg[0] (\sig_token_cntr_reg[0] ), + .\sig_token_cntr_reg[3] (\sig_token_cntr_reg[3] ), + .\sig_user_skid_reg_reg[0] (\sig_user_skid_reg_reg[0] )); + FDRE #( + .INIT(1'b0)) + hold_ff_q_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\BLK_MEM.I_SYNC_FIFOGEN_FIFO_n_5 ), + .Q(hold_ff_q), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "axi_datamover_sfifo_autord" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_sfifo_autord__parameterized0 + (D, + sig_xfer_is_seq_reg_reg, + \sig_child_addr_cntr_lsh_reg[11] , + E, + S, + \sig_xfer_len_reg_reg[4] , + \sig_xfer_len_reg_reg[5] , + sig_xfer_is_seq_reg_reg_0, + sig_xfer_cmd_cmplt_reg0, + sig_sf2pcc_xfer_valid, + sig_ibtt2dre_tready, + sig_csm_state_ns1, + \gpr1.dout_i_reg[1] , + \gpr1.dout_i_reg[1]_0 , + O, + CO, + \sig_child_addr_cntr_lsh_reg[7] , + sig_stream_rst, + m_axi_s2mm_aclk, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + p_32_out, + sig_adjusted_addr_incr, + sig_clr_dbc_reg_reg, + sig_csm_pop_child_cmd, + sig_child_qual_first_of_2, + sig_child_qual_error_reg, + lsig_packer_full, + ram_full_i_reg, + \gpr1.dout_i_reg[3] , + \gpr1.dout_i_reg[7] , + sig_child_addr_cntr_lsh_reg, + p_0_out); + output [2:0]D; + output [9:0]sig_xfer_is_seq_reg_reg; + output [0:0]\sig_child_addr_cntr_lsh_reg[11] ; + output [0:0]E; + output [3:0]S; + output [3:0]\sig_xfer_len_reg_reg[4] ; + output [0:0]\sig_xfer_len_reg_reg[5] ; + output sig_xfer_is_seq_reg_reg_0; + output sig_xfer_cmd_cmplt_reg0; + output sig_sf2pcc_xfer_valid; + output sig_ibtt2dre_tready; + output sig_csm_state_ns1; + output [2:0]\gpr1.dout_i_reg[1] ; + output [2:0]\gpr1.dout_i_reg[1]_0 ; + output [3:0]O; + output [0:0]CO; + output [3:0]\sig_child_addr_cntr_lsh_reg[7] ; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input p_32_out; + input [8:0]sig_adjusted_addr_incr; + input sig_clr_dbc_reg_reg; + input sig_csm_pop_child_cmd; + input sig_child_qual_first_of_2; + input sig_child_qual_error_reg; + input lsig_packer_full; + input ram_full_i_reg; + input [3:0]\gpr1.dout_i_reg[3] ; + input [3:0]\gpr1.dout_i_reg[7] ; + input [2:0]sig_child_addr_cntr_lsh_reg; + input [10:0]p_0_out; + + wire [0:0]CO; + wire [2:0]D; + wire [0:0]E; + wire \NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO_n_0 ; + wire [3:0]O; + wire [3:0]S; + wire [2:0]\gpr1.dout_i_reg[1] ; + wire [2:0]\gpr1.dout_i_reg[1]_0 ; + wire [3:0]\gpr1.dout_i_reg[3] ; + wire [3:0]\gpr1.dout_i_reg[7] ; + wire hold_ff_q; + wire lsig_packer_full; + wire m_axi_s2mm_aclk; + wire [10:0]p_0_out; + wire p_32_out; + wire ram_full_i_reg; + wire [8:0]sig_adjusted_addr_incr; + wire [2:0]sig_child_addr_cntr_lsh_reg; + wire [0:0]\sig_child_addr_cntr_lsh_reg[11] ; + wire [3:0]\sig_child_addr_cntr_lsh_reg[7] ; + wire sig_child_qual_error_reg; + wire sig_child_qual_first_of_2; + wire sig_clr_dbc_reg_reg; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_csm_pop_child_cmd; + wire sig_csm_state_ns1; + wire sig_ibtt2dre_tready; + wire sig_sf2pcc_xfer_valid; + wire sig_stream_rst; + wire sig_xfer_cmd_cmplt_reg0; + wire [9:0]sig_xfer_is_seq_reg_reg; + wire sig_xfer_is_seq_reg_reg_0; + wire [3:0]\sig_xfer_len_reg_reg[4] ; + wire [0:0]\sig_xfer_len_reg_reg[5] ; + + Arty_Z7_20_axi_vdma_0_0_sync_fifo_fg__parameterized0 \NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO + (.CO(CO), + .D(D), + .E(E), + .O(O), + .S(S), + .\gpr1.dout_i_reg[1] (\gpr1.dout_i_reg[1] ), + .\gpr1.dout_i_reg[1]_0 (\gpr1.dout_i_reg[1]_0 ), + .\gpr1.dout_i_reg[3] (\gpr1.dout_i_reg[3] ), + .\gpr1.dout_i_reg[7] (\gpr1.dout_i_reg[7] ), + .hold_ff_q(hold_ff_q), + .hold_ff_q_reg(\NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO_n_0 ), + .lsig_packer_full(lsig_packer_full), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .p_0_out(p_0_out), + .p_32_out(p_32_out), + .ram_full_i_reg(ram_full_i_reg), + .sig_adjusted_addr_incr(sig_adjusted_addr_incr), + .sig_child_addr_cntr_lsh_reg(sig_child_addr_cntr_lsh_reg), + .\sig_child_addr_cntr_lsh_reg[11] (\sig_child_addr_cntr_lsh_reg[11] ), + .\sig_child_addr_cntr_lsh_reg[7] (\sig_child_addr_cntr_lsh_reg[7] ), + .sig_child_qual_error_reg(sig_child_qual_error_reg), + .sig_child_qual_first_of_2(sig_child_qual_first_of_2), + .sig_clr_dbc_reg_reg(sig_clr_dbc_reg_reg), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_csm_pop_child_cmd(sig_csm_pop_child_cmd), + .sig_csm_state_ns1(sig_csm_state_ns1), + .sig_ibtt2dre_tready(sig_ibtt2dre_tready), + .sig_sf2pcc_xfer_valid(sig_sf2pcc_xfer_valid), + .sig_stream_rst(sig_stream_rst), + .sig_xfer_cmd_cmplt_reg0(sig_xfer_cmd_cmplt_reg0), + .sig_xfer_is_seq_reg_reg(sig_xfer_is_seq_reg_reg), + .sig_xfer_is_seq_reg_reg_0(sig_xfer_is_seq_reg_reg_0), + .\sig_xfer_len_reg_reg[4] (\sig_xfer_len_reg_reg[4] ), + .\sig_xfer_len_reg_reg[5] (\sig_xfer_len_reg_reg[5] )); + FDRE #( + .INIT(1'b0)) + hold_ff_q_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO_n_0 ), + .Q(hold_ff_q), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "axi_datamover_sfifo_autord" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_sfifo_autord__parameterized1 + (sig_data_fifo_data_out, + out, + \gcc0.gc0.count_d1_reg[7] , + hold_ff_q, + \INCLUDE_PACKING.lsig_packer_full_reg , + E, + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] , + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] , + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] , + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] , + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] , + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] , + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] , + sig_data_fifo_dvalid, + m_axi_s2mm_aclk, + sig_stream_rst, + lsig_combined_data, + DIBDI, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_s_ready_out_reg, + lsig_set_packer_full__1, + lsig_packer_full, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ); + output [65:0]sig_data_fifo_data_out; + output out; + output \gcc0.gc0.count_d1_reg[7] ; + output hold_ff_q; + output \INCLUDE_PACKING.lsig_packer_full_reg ; + output [0:0]E; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] ; + output sig_data_fifo_dvalid; + input m_axi_s2mm_aclk; + input sig_stream_rst; + input [63:0]lsig_combined_data; + input [1:0]DIBDI; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_s_ready_out_reg; + input lsig_set_packer_full__1; + input lsig_packer_full; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ; + + wire \BLK_MEM.I_SYNC_FIFOGEN_FIFO_n_68 ; + wire [1:0]DIBDI; + wire [0:0]E; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ; + wire \INCLUDE_PACKING.lsig_packer_full_reg ; + wire \gcc0.gc0.count_d1_reg[7] ; + wire hold_ff_q; + wire [63:0]lsig_combined_data; + wire lsig_packer_full; + wire lsig_set_packer_full__1; + wire m_axi_s2mm_aclk; + wire out; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire [65:0]sig_data_fifo_data_out; + wire sig_data_fifo_dvalid; + wire sig_s_ready_out_reg; + wire sig_stream_rst; + + Arty_Z7_20_axi_vdma_0_0_sync_fifo_fg__parameterized1 \BLK_MEM.I_SYNC_FIFOGEN_FIFO + (.DIBDI(DIBDI), + .E(E), + .\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] (\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] (\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] (\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] (\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] (\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] (\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] (\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ), + .\INCLUDE_PACKING.lsig_packer_full_reg (\INCLUDE_PACKING.lsig_packer_full_reg ), + .\gcc0.gc0.count_d1_reg[7] (\gcc0.gc0.count_d1_reg[7] ), + .hold_ff_q_reg(\BLK_MEM.I_SYNC_FIFOGEN_FIFO_n_68 ), + .hold_ff_q_reg_0(hold_ff_q), + .lsig_combined_data(lsig_combined_data), + .lsig_packer_full(lsig_packer_full), + .lsig_set_packer_full__1(lsig_set_packer_full__1), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_data_fifo_data_out(sig_data_fifo_data_out), + .sig_data_fifo_dvalid(sig_data_fifo_dvalid), + .sig_s_ready_out_reg(sig_s_ready_out_reg), + .sig_stream_rst(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + hold_ff_q_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\BLK_MEM.I_SYNC_FIFOGEN_FIFO_n_68 ), + .Q(hold_ff_q), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "axi_datamover_skid2mm_buf" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_skid2mm_buf + (out, + m_axi_s2mm_wvalid, + m_axi_s2mm_wlast, + m_axi_s2mm_wdata, + m_axi_s2mm_aclk, + sig_stream_rst, + sig_dqual_reg_full, + sig_dbeat_cntr_eq_0__2, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + m_axi_s2mm_wready, + sig_init_reg, + sig_data2skid_wvalid, + D); + output out; + output m_axi_s2mm_wvalid; + output m_axi_s2mm_wlast; + output [63:0]m_axi_s2mm_wdata; + input m_axi_s2mm_aclk; + input sig_stream_rst; + input sig_dqual_reg_full; + input sig_dbeat_cntr_eq_0__2; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input m_axi_s2mm_wready; + input sig_init_reg; + input sig_data2skid_wvalid; + input [63:0]D; + + wire [63:0]D; + wire m_axi_s2mm_aclk; + wire [63:0]m_axi_s2mm_wdata; + wire m_axi_s2mm_wlast; + wire m_axi_s2mm_wready; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_data2skid_wvalid; + wire \sig_data_reg_out[63]_i_1__0_n_0 ; + wire [63:0]sig_data_skid_mux_out; + wire [63:0]sig_data_skid_reg; + wire sig_dbeat_cntr_eq_0__2; + wire sig_dqual_reg_full; + wire sig_init_reg; + wire sig_last_reg_out_i_2_n_0; + wire sig_last_skid_reg; + wire sig_last_skid_reg_i_1_n_0; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_m_valid_dup; + wire sig_m_valid_dup_i_1__1_n_0; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_m_valid_out; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_s_ready_dup; + wire sig_s_ready_dup_i_1_n_0; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_s_ready_out; + wire sig_stream_rst; + + assign m_axi_s2mm_wvalid = sig_m_valid_out; + assign out = sig_s_ready_out; + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[0]_i_1 + (.I0(sig_data_skid_reg[0]), + .I1(D[0]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[0])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[10]_i_1 + (.I0(sig_data_skid_reg[10]), + .I1(D[10]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[10])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[11]_i_1 + (.I0(sig_data_skid_reg[11]), + .I1(D[11]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[11])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[12]_i_1 + (.I0(sig_data_skid_reg[12]), + .I1(D[12]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[12])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[13]_i_1 + (.I0(sig_data_skid_reg[13]), + .I1(D[13]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[13])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[14]_i_1 + (.I0(sig_data_skid_reg[14]), + .I1(D[14]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[14])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[15]_i_1 + (.I0(sig_data_skid_reg[15]), + .I1(D[15]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[15])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[16]_i_1 + (.I0(sig_data_skid_reg[16]), + .I1(D[16]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[16])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[17]_i_1 + (.I0(sig_data_skid_reg[17]), + .I1(D[17]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[17])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[18]_i_1 + (.I0(sig_data_skid_reg[18]), + .I1(D[18]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[18])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[19]_i_1 + (.I0(sig_data_skid_reg[19]), + .I1(D[19]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[19])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[1]_i_1 + (.I0(sig_data_skid_reg[1]), + .I1(D[1]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[1])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[20]_i_1 + (.I0(sig_data_skid_reg[20]), + .I1(D[20]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[20])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[21]_i_1 + (.I0(sig_data_skid_reg[21]), + .I1(D[21]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[21])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[22]_i_1 + (.I0(sig_data_skid_reg[22]), + .I1(D[22]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[22])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[23]_i_1 + (.I0(sig_data_skid_reg[23]), + .I1(D[23]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[23])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[24]_i_1 + (.I0(sig_data_skid_reg[24]), + .I1(D[24]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[24])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[25]_i_1 + (.I0(sig_data_skid_reg[25]), + .I1(D[25]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[25])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[26]_i_1 + (.I0(sig_data_skid_reg[26]), + .I1(D[26]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[26])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[27]_i_1 + (.I0(sig_data_skid_reg[27]), + .I1(D[27]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[27])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[28]_i_1 + (.I0(sig_data_skid_reg[28]), + .I1(D[28]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[28])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[29]_i_1 + (.I0(sig_data_skid_reg[29]), + .I1(D[29]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[29])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[2]_i_1 + (.I0(sig_data_skid_reg[2]), + .I1(D[2]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[2])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[30]_i_1 + (.I0(sig_data_skid_reg[30]), + .I1(D[30]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[30])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[31]_i_1 + (.I0(sig_data_skid_reg[31]), + .I1(D[31]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[31])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[32]_i_1 + (.I0(sig_data_skid_reg[32]), + .I1(D[32]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[32])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[33]_i_1 + (.I0(sig_data_skid_reg[33]), + .I1(D[33]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[33])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[34]_i_1 + (.I0(sig_data_skid_reg[34]), + .I1(D[34]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[34])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[35]_i_1 + (.I0(sig_data_skid_reg[35]), + .I1(D[35]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[35])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[36]_i_1 + (.I0(sig_data_skid_reg[36]), + .I1(D[36]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[36])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[37]_i_1 + (.I0(sig_data_skid_reg[37]), + .I1(D[37]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[37])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[38]_i_1 + (.I0(sig_data_skid_reg[38]), + .I1(D[38]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[38])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[39]_i_1 + (.I0(sig_data_skid_reg[39]), + .I1(D[39]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[39])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[3]_i_1 + (.I0(sig_data_skid_reg[3]), + .I1(D[3]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[3])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[40]_i_1 + (.I0(sig_data_skid_reg[40]), + .I1(D[40]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[40])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[41]_i_1 + (.I0(sig_data_skid_reg[41]), + .I1(D[41]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[41])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[42]_i_1 + (.I0(sig_data_skid_reg[42]), + .I1(D[42]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[42])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[43]_i_1 + (.I0(sig_data_skid_reg[43]), + .I1(D[43]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[43])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[44]_i_1 + (.I0(sig_data_skid_reg[44]), + .I1(D[44]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[44])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[45]_i_1 + (.I0(sig_data_skid_reg[45]), + .I1(D[45]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[45])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[46]_i_1 + (.I0(sig_data_skid_reg[46]), + .I1(D[46]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[46])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[47]_i_1 + (.I0(sig_data_skid_reg[47]), + .I1(D[47]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[47])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[48]_i_1 + (.I0(sig_data_skid_reg[48]), + .I1(D[48]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[48])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[49]_i_1 + (.I0(sig_data_skid_reg[49]), + .I1(D[49]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[49])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[4]_i_1 + (.I0(sig_data_skid_reg[4]), + .I1(D[4]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[4])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[50]_i_1 + (.I0(sig_data_skid_reg[50]), + .I1(D[50]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[50])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[51]_i_1 + (.I0(sig_data_skid_reg[51]), + .I1(D[51]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[51])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[52]_i_1 + (.I0(sig_data_skid_reg[52]), + .I1(D[52]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[52])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[53]_i_1 + (.I0(sig_data_skid_reg[53]), + .I1(D[53]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[53])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[54]_i_1 + (.I0(sig_data_skid_reg[54]), + .I1(D[54]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[54])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[55]_i_1 + (.I0(sig_data_skid_reg[55]), + .I1(D[55]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[55])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[56]_i_1 + (.I0(sig_data_skid_reg[56]), + .I1(D[56]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[56])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[57]_i_1 + (.I0(sig_data_skid_reg[57]), + .I1(D[57]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[57])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[58]_i_1 + (.I0(sig_data_skid_reg[58]), + .I1(D[58]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[58])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[59]_i_1 + (.I0(sig_data_skid_reg[59]), + .I1(D[59]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[59])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[5]_i_1 + (.I0(sig_data_skid_reg[5]), + .I1(D[5]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[5])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[60]_i_1 + (.I0(sig_data_skid_reg[60]), + .I1(D[60]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[60])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[61]_i_1 + (.I0(sig_data_skid_reg[61]), + .I1(D[61]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[61])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[62]_i_1 + (.I0(sig_data_skid_reg[62]), + .I1(D[62]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[62])); + LUT2 #( + .INIT(4'hB)) + \sig_data_reg_out[63]_i_1__0 + (.I0(m_axi_s2mm_wready), + .I1(sig_m_valid_dup), + .O(\sig_data_reg_out[63]_i_1__0_n_0 )); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[63]_i_2 + (.I0(sig_data_skid_reg[63]), + .I1(D[63]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[63])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[6]_i_1 + (.I0(sig_data_skid_reg[6]), + .I1(D[6]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[6])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[7]_i_1 + (.I0(sig_data_skid_reg[7]), + .I1(D[7]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[7])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[8]_i_1 + (.I0(sig_data_skid_reg[8]), + .I1(D[8]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[8])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[9]_i_1 + (.I0(sig_data_skid_reg[9]), + .I1(D[9]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[9])); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[0]), + .Q(m_axi_s2mm_wdata[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[10]), + .Q(m_axi_s2mm_wdata[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[11]), + .Q(m_axi_s2mm_wdata[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[12]), + .Q(m_axi_s2mm_wdata[12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[13] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[13]), + .Q(m_axi_s2mm_wdata[13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[14] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[14]), + .Q(m_axi_s2mm_wdata[14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[15] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[15]), + .Q(m_axi_s2mm_wdata[15]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[16] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[16]), + .Q(m_axi_s2mm_wdata[16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[17] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[17]), + .Q(m_axi_s2mm_wdata[17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[18] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[18]), + .Q(m_axi_s2mm_wdata[18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[19] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[19]), + .Q(m_axi_s2mm_wdata[19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[1]), + .Q(m_axi_s2mm_wdata[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[20] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[20]), + .Q(m_axi_s2mm_wdata[20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[21] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[21]), + .Q(m_axi_s2mm_wdata[21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[22] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[22]), + .Q(m_axi_s2mm_wdata[22]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[23] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[23]), + .Q(m_axi_s2mm_wdata[23]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[24] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[24]), + .Q(m_axi_s2mm_wdata[24]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[25] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[25]), + .Q(m_axi_s2mm_wdata[25]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[26] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[26]), + .Q(m_axi_s2mm_wdata[26]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[27] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[27]), + .Q(m_axi_s2mm_wdata[27]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[28] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[28]), + .Q(m_axi_s2mm_wdata[28]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[29] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[29]), + .Q(m_axi_s2mm_wdata[29]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[2]), + .Q(m_axi_s2mm_wdata[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[30] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[30]), + .Q(m_axi_s2mm_wdata[30]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[31] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[31]), + .Q(m_axi_s2mm_wdata[31]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[32] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[32]), + .Q(m_axi_s2mm_wdata[32]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[33] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[33]), + .Q(m_axi_s2mm_wdata[33]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[34] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[34]), + .Q(m_axi_s2mm_wdata[34]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[35] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[35]), + .Q(m_axi_s2mm_wdata[35]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[36] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[36]), + .Q(m_axi_s2mm_wdata[36]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[37] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[37]), + .Q(m_axi_s2mm_wdata[37]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[38] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[38]), + .Q(m_axi_s2mm_wdata[38]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[39] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[39]), + .Q(m_axi_s2mm_wdata[39]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[3]), + .Q(m_axi_s2mm_wdata[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[40] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[40]), + .Q(m_axi_s2mm_wdata[40]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[41] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[41]), + .Q(m_axi_s2mm_wdata[41]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[42] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[42]), + .Q(m_axi_s2mm_wdata[42]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[43] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[43]), + .Q(m_axi_s2mm_wdata[43]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[44] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[44]), + .Q(m_axi_s2mm_wdata[44]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[45] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[45]), + .Q(m_axi_s2mm_wdata[45]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[46] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[46]), + .Q(m_axi_s2mm_wdata[46]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[47] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[47]), + .Q(m_axi_s2mm_wdata[47]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[48] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[48]), + .Q(m_axi_s2mm_wdata[48]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[49] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[49]), + .Q(m_axi_s2mm_wdata[49]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[4]), + .Q(m_axi_s2mm_wdata[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[50] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[50]), + .Q(m_axi_s2mm_wdata[50]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[51] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[51]), + .Q(m_axi_s2mm_wdata[51]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[52] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[52]), + .Q(m_axi_s2mm_wdata[52]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[53] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[53]), + .Q(m_axi_s2mm_wdata[53]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[54] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[54]), + .Q(m_axi_s2mm_wdata[54]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[55] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[55]), + .Q(m_axi_s2mm_wdata[55]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[56] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[56]), + .Q(m_axi_s2mm_wdata[56]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[57] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[57]), + .Q(m_axi_s2mm_wdata[57]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[58] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[58]), + .Q(m_axi_s2mm_wdata[58]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[59] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[59]), + .Q(m_axi_s2mm_wdata[59]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[5]), + .Q(m_axi_s2mm_wdata[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[60] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[60]), + .Q(m_axi_s2mm_wdata[60]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[61] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[61]), + .Q(m_axi_s2mm_wdata[61]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[62] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[62]), + .Q(m_axi_s2mm_wdata[62]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[63] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[63]), + .Q(m_axi_s2mm_wdata[63]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[6]), + .Q(m_axi_s2mm_wdata[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[7]), + .Q(m_axi_s2mm_wdata[7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[8]), + .Q(m_axi_s2mm_wdata[8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(\sig_data_reg_out[63]_i_1__0_n_0 ), + .D(sig_data_skid_mux_out[9]), + .Q(m_axi_s2mm_wdata[9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[0]), + .Q(sig_data_skid_reg[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[10]), + .Q(sig_data_skid_reg[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[11]), + .Q(sig_data_skid_reg[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[12]), + .Q(sig_data_skid_reg[12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[13] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[13]), + .Q(sig_data_skid_reg[13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[14] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[14]), + .Q(sig_data_skid_reg[14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[15] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[15]), + .Q(sig_data_skid_reg[15]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[16] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[16]), + .Q(sig_data_skid_reg[16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[17] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[17]), + .Q(sig_data_skid_reg[17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[18] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[18]), + .Q(sig_data_skid_reg[18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[19] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[19]), + .Q(sig_data_skid_reg[19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[1]), + .Q(sig_data_skid_reg[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[20] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[20]), + .Q(sig_data_skid_reg[20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[21] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[21]), + .Q(sig_data_skid_reg[21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[22] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[22]), + .Q(sig_data_skid_reg[22]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[23] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[23]), + .Q(sig_data_skid_reg[23]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[24] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[24]), + .Q(sig_data_skid_reg[24]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[25] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[25]), + .Q(sig_data_skid_reg[25]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[26] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[26]), + .Q(sig_data_skid_reg[26]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[27] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[27]), + .Q(sig_data_skid_reg[27]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[28] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[28]), + .Q(sig_data_skid_reg[28]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[29] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[29]), + .Q(sig_data_skid_reg[29]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[2]), + .Q(sig_data_skid_reg[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[30] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[30]), + .Q(sig_data_skid_reg[30]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[31] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[31]), + .Q(sig_data_skid_reg[31]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[32] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[32]), + .Q(sig_data_skid_reg[32]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[33] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[33]), + .Q(sig_data_skid_reg[33]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[34] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[34]), + .Q(sig_data_skid_reg[34]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[35] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[35]), + .Q(sig_data_skid_reg[35]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[36] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[36]), + .Q(sig_data_skid_reg[36]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[37] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[37]), + .Q(sig_data_skid_reg[37]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[38] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[38]), + .Q(sig_data_skid_reg[38]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[39] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[39]), + .Q(sig_data_skid_reg[39]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[3]), + .Q(sig_data_skid_reg[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[40] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[40]), + .Q(sig_data_skid_reg[40]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[41] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[41]), + .Q(sig_data_skid_reg[41]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[42] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[42]), + .Q(sig_data_skid_reg[42]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[43] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[43]), + .Q(sig_data_skid_reg[43]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[44] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[44]), + .Q(sig_data_skid_reg[44]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[45] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[45]), + .Q(sig_data_skid_reg[45]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[46] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[46]), + .Q(sig_data_skid_reg[46]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[47] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[47]), + .Q(sig_data_skid_reg[47]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[48] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[48]), + .Q(sig_data_skid_reg[48]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[49] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[49]), + .Q(sig_data_skid_reg[49]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[4]), + .Q(sig_data_skid_reg[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[50] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[50]), + .Q(sig_data_skid_reg[50]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[51] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[51]), + .Q(sig_data_skid_reg[51]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[52] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[52]), + .Q(sig_data_skid_reg[52]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[53] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[53]), + .Q(sig_data_skid_reg[53]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[54] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[54]), + .Q(sig_data_skid_reg[54]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[55] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[55]), + .Q(sig_data_skid_reg[55]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[56] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[56]), + .Q(sig_data_skid_reg[56]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[57] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[57]), + .Q(sig_data_skid_reg[57]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[58] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[58]), + .Q(sig_data_skid_reg[58]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[59] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[59]), + .Q(sig_data_skid_reg[59]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[5]), + .Q(sig_data_skid_reg[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[60] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[60]), + .Q(sig_data_skid_reg[60]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[61] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[61]), + .Q(sig_data_skid_reg[61]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[62] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[62]), + .Q(sig_data_skid_reg[62]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[63] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[63]), + .Q(sig_data_skid_reg[63]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[6]), + .Q(sig_data_skid_reg[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[7]), + .Q(sig_data_skid_reg[7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[8]), + .Q(sig_data_skid_reg[8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(D[9]), + .Q(sig_data_skid_reg[9]), + .R(1'b0)); + LUT6 #( + .INIT(64'h8F80FFFF8F800000)) + sig_last_reg_out_i_2 + (.I0(sig_dbeat_cntr_eq_0__2), + .I1(sig_dqual_reg_full), + .I2(sig_s_ready_dup), + .I3(sig_last_skid_reg), + .I4(\sig_data_reg_out[63]_i_1__0_n_0 ), + .I5(m_axi_s2mm_wlast), + .O(sig_last_reg_out_i_2_n_0)); + FDRE #( + .INIT(1'b0)) + sig_last_reg_out_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_last_reg_out_i_2_n_0), + .Q(m_axi_s2mm_wlast), + .R(sig_stream_rst)); + LUT5 #( + .INIT(32'hE2220000)) + sig_last_skid_reg_i_1 + (.I0(sig_last_skid_reg), + .I1(sig_s_ready_dup), + .I2(sig_dqual_reg_full), + .I3(sig_dbeat_cntr_eq_0__2), + .I4(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .O(sig_last_skid_reg_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + sig_last_skid_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_last_skid_reg_i_1_n_0), + .Q(sig_last_skid_reg), + .R(1'b0)); + LUT6 #( + .INIT(64'h4444444400404040)) + sig_m_valid_dup_i_1__1 + (.I0(sig_init_reg), + .I1(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I2(sig_m_valid_dup), + .I3(sig_s_ready_dup), + .I4(m_axi_s2mm_wready), + .I5(sig_data2skid_wvalid), + .O(sig_m_valid_dup_i_1__1_n_0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + sig_m_valid_dup_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_m_valid_dup_i_1__1_n_0), + .Q(sig_m_valid_dup), + .R(1'b0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + sig_m_valid_out_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_m_valid_dup_i_1__1_n_0), + .Q(sig_m_valid_out), + .R(1'b0)); + LUT5 #( + .INIT(32'hFFFFAEEE)) + sig_s_ready_dup_i_1 + (.I0(sig_init_reg), + .I1(sig_s_ready_dup), + .I2(sig_m_valid_dup), + .I3(sig_data2skid_wvalid), + .I4(m_axi_s2mm_wready), + .O(sig_s_ready_dup_i_1_n_0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + sig_s_ready_dup_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_s_ready_dup_i_1_n_0), + .Q(sig_s_ready_dup), + .R(sig_stream_rst)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + sig_s_ready_out_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_s_ready_dup_i_1_n_0), + .Q(sig_s_ready_out), + .R(sig_stream_rst)); +endmodule + +(* ORIG_REF_NAME = "axi_datamover_skid_buf" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_skid_buf + (out, + \gpregsm1.user_valid_reg , + \GEN_INDET_BTT.lsig_eop_reg_reg , + sig_ibtt2wdc_tlast, + \GEN_INDET_BTT.lsig_byte_cntr_reg[15] , + \GEN_INDET_BTT.lsig_byte_cntr_reg[6] , + \GEN_INDET_BTT.lsig_byte_cntr_reg[3] , + \GEN_INDET_BTT.lsig_eop_reg_reg_0 , + m_axi_s2mm_aclk, + sig_stream_rst, + sig_data_fifo_data_out, + E, + sig_wdc2ibtt_tready, + lsig_end_of_cmd_reg, + lsig_eop_reg, + sig_init_reg, + hold_ff_q, + \gpregsm1.user_valid_reg_0 , + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_data_fifo_dvalid); + output out; + output \gpregsm1.user_valid_reg ; + output \GEN_INDET_BTT.lsig_eop_reg_reg ; + output sig_ibtt2wdc_tlast; + output [0:0]\GEN_INDET_BTT.lsig_byte_cntr_reg[15] ; + output [0:0]\GEN_INDET_BTT.lsig_byte_cntr_reg[6] ; + output [64:0]\GEN_INDET_BTT.lsig_byte_cntr_reg[3] ; + output \GEN_INDET_BTT.lsig_eop_reg_reg_0 ; + input m_axi_s2mm_aclk; + input sig_stream_rst; + input [65:0]sig_data_fifo_data_out; + input [0:0]E; + input sig_wdc2ibtt_tready; + input lsig_end_of_cmd_reg; + input lsig_eop_reg; + input sig_init_reg; + input hold_ff_q; + input \gpregsm1.user_valid_reg_0 ; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_data_fifo_dvalid; + + wire [0:0]E; + wire [0:0]\GEN_INDET_BTT.lsig_byte_cntr_reg[15] ; + wire [64:0]\GEN_INDET_BTT.lsig_byte_cntr_reg[3] ; + wire [0:0]\GEN_INDET_BTT.lsig_byte_cntr_reg[6] ; + wire \GEN_INDET_BTT.lsig_eop_reg_reg_0 ; + wire \gpregsm1.user_valid_reg_0 ; + wire hold_ff_q; + wire lsig_end_of_cmd_reg; + wire lsig_eop_reg; + wire m_axi_s2mm_aclk; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire [65:0]sig_data_fifo_data_out; + wire sig_data_fifo_dvalid; + wire \sig_data_reg_out[67]_i_2_n_0 ; + wire [63:0]sig_data_skid_mux_out; + wire [67:0]sig_data_skid_reg; + wire sig_ibtt2wdc_eop; + wire sig_ibtt2wdc_tlast; + wire sig_init_reg; + wire sig_last_skid_mux_out; + wire sig_last_skid_reg; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_m_valid_dup; + wire sig_m_valid_dup_i_1__0_n_0; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_m_valid_out; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_s_ready_dup; + wire sig_s_ready_dup_i_1__1_n_0; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_s_ready_out; + wire [8:8]sig_strb_skid_mux_out; + wire [8:8]sig_strb_skid_reg; + wire sig_stream_rst; + wire sig_wdc2ibtt_tready; + + assign \GEN_INDET_BTT.lsig_eop_reg_reg = sig_m_valid_out; + assign \gpregsm1.user_valid_reg = sig_s_ready_out; + assign out = sig_m_valid_dup; + LUT2 #( + .INIT(4'h8)) + \GEN_INDET_BTT.lsig_byte_cntr[15]_i_2 + (.I0(sig_m_valid_out), + .I1(sig_wdc2ibtt_tready), + .O(\GEN_INDET_BTT.lsig_byte_cntr_reg[15] )); + LUT4 #( + .INIT(16'h70F0)) + \GEN_INDET_BTT.lsig_byte_cntr[6]_i_2 + (.I0(sig_m_valid_out), + .I1(sig_wdc2ibtt_tready), + .I2(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [64]), + .I3(lsig_end_of_cmd_reg), + .O(\GEN_INDET_BTT.lsig_byte_cntr_reg[6] )); + LUT4 #( + .INIT(16'hF780)) + \GEN_INDET_BTT.lsig_eop_reg_i_1 + (.I0(sig_m_valid_out), + .I1(sig_wdc2ibtt_tready), + .I2(sig_ibtt2wdc_eop), + .I3(lsig_eop_reg), + .O(\GEN_INDET_BTT.lsig_eop_reg_reg_0 )); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[0]_i_1__0 + (.I0(sig_data_skid_reg[0]), + .I1(sig_data_fifo_data_out[0]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[0])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[10]_i_1__0 + (.I0(sig_data_skid_reg[10]), + .I1(sig_data_fifo_data_out[10]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[10])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[11]_i_1__0 + (.I0(sig_data_skid_reg[11]), + .I1(sig_data_fifo_data_out[11]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[11])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[12]_i_1__0 + (.I0(sig_data_skid_reg[12]), + .I1(sig_data_fifo_data_out[12]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[12])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[13]_i_1__0 + (.I0(sig_data_skid_reg[13]), + .I1(sig_data_fifo_data_out[13]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[13])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[14]_i_1__0 + (.I0(sig_data_skid_reg[14]), + .I1(sig_data_fifo_data_out[14]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[14])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[15]_i_1__0 + (.I0(sig_data_skid_reg[15]), + .I1(sig_data_fifo_data_out[15]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[15])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[16]_i_1__0 + (.I0(sig_data_skid_reg[16]), + .I1(sig_data_fifo_data_out[16]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[16])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[17]_i_1__0 + (.I0(sig_data_skid_reg[17]), + .I1(sig_data_fifo_data_out[17]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[17])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[18]_i_1__0 + (.I0(sig_data_skid_reg[18]), + .I1(sig_data_fifo_data_out[18]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[18])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[19]_i_1__0 + (.I0(sig_data_skid_reg[19]), + .I1(sig_data_fifo_data_out[19]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[19])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[1]_i_1__0 + (.I0(sig_data_skid_reg[1]), + .I1(sig_data_fifo_data_out[1]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[1])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[20]_i_1__0 + (.I0(sig_data_skid_reg[20]), + .I1(sig_data_fifo_data_out[20]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[20])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[21]_i_1__0 + (.I0(sig_data_skid_reg[21]), + .I1(sig_data_fifo_data_out[21]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[21])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[22]_i_1__0 + (.I0(sig_data_skid_reg[22]), + .I1(sig_data_fifo_data_out[22]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[22])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[23]_i_1__0 + (.I0(sig_data_skid_reg[23]), + .I1(sig_data_fifo_data_out[23]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[23])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[24]_i_1__0 + (.I0(sig_data_skid_reg[24]), + .I1(sig_data_fifo_data_out[24]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[24])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[25]_i_1__0 + (.I0(sig_data_skid_reg[25]), + .I1(sig_data_fifo_data_out[25]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[25])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[26]_i_1__0 + (.I0(sig_data_skid_reg[26]), + .I1(sig_data_fifo_data_out[26]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[26])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[27]_i_1__0 + (.I0(sig_data_skid_reg[27]), + .I1(sig_data_fifo_data_out[27]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[27])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[28]_i_1__0 + (.I0(sig_data_skid_reg[28]), + .I1(sig_data_fifo_data_out[28]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[28])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[29]_i_1__0 + (.I0(sig_data_skid_reg[29]), + .I1(sig_data_fifo_data_out[29]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[29])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[2]_i_1__0 + (.I0(sig_data_skid_reg[2]), + .I1(sig_data_fifo_data_out[2]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[2])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[30]_i_1__0 + (.I0(sig_data_skid_reg[30]), + .I1(sig_data_fifo_data_out[30]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[30])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[31]_i_1__0 + (.I0(sig_data_skid_reg[31]), + .I1(sig_data_fifo_data_out[31]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[31])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[32]_i_1__0 + (.I0(sig_data_skid_reg[32]), + .I1(sig_data_fifo_data_out[32]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[32])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[33]_i_1__0 + (.I0(sig_data_skid_reg[33]), + .I1(sig_data_fifo_data_out[33]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[33])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[34]_i_1__0 + (.I0(sig_data_skid_reg[34]), + .I1(sig_data_fifo_data_out[34]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[34])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[35]_i_1__0 + (.I0(sig_data_skid_reg[35]), + .I1(sig_data_fifo_data_out[35]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[35])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[36]_i_1__0 + (.I0(sig_data_skid_reg[36]), + .I1(sig_data_fifo_data_out[36]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[36])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[37]_i_1__0 + (.I0(sig_data_skid_reg[37]), + .I1(sig_data_fifo_data_out[37]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[37])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[38]_i_1__0 + (.I0(sig_data_skid_reg[38]), + .I1(sig_data_fifo_data_out[38]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[38])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[39]_i_1__0 + (.I0(sig_data_skid_reg[39]), + .I1(sig_data_fifo_data_out[39]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[39])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[3]_i_1__0 + (.I0(sig_data_skid_reg[3]), + .I1(sig_data_fifo_data_out[3]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[3])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[40]_i_1__0 + (.I0(sig_data_skid_reg[40]), + .I1(sig_data_fifo_data_out[40]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[40])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[41]_i_1__0 + (.I0(sig_data_skid_reg[41]), + .I1(sig_data_fifo_data_out[41]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[41])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[42]_i_1__0 + (.I0(sig_data_skid_reg[42]), + .I1(sig_data_fifo_data_out[42]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[42])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[43]_i_1__0 + (.I0(sig_data_skid_reg[43]), + .I1(sig_data_fifo_data_out[43]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[43])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[44]_i_1__0 + (.I0(sig_data_skid_reg[44]), + .I1(sig_data_fifo_data_out[44]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[44])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[45]_i_1__0 + (.I0(sig_data_skid_reg[45]), + .I1(sig_data_fifo_data_out[45]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[45])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[46]_i_1__0 + (.I0(sig_data_skid_reg[46]), + .I1(sig_data_fifo_data_out[46]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[46])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[47]_i_1__0 + (.I0(sig_data_skid_reg[47]), + .I1(sig_data_fifo_data_out[47]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[47])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[48]_i_1__0 + (.I0(sig_data_skid_reg[48]), + .I1(sig_data_fifo_data_out[48]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[48])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[49]_i_1__0 + (.I0(sig_data_skid_reg[49]), + .I1(sig_data_fifo_data_out[49]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[49])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[4]_i_1__0 + (.I0(sig_data_skid_reg[4]), + .I1(sig_data_fifo_data_out[4]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[4])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[50]_i_1__0 + (.I0(sig_data_skid_reg[50]), + .I1(sig_data_fifo_data_out[50]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[50])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[51]_i_1__0 + (.I0(sig_data_skid_reg[51]), + .I1(sig_data_fifo_data_out[51]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[51])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[52]_i_1__0 + (.I0(sig_data_skid_reg[52]), + .I1(sig_data_fifo_data_out[52]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[52])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[53]_i_1__0 + (.I0(sig_data_skid_reg[53]), + .I1(sig_data_fifo_data_out[53]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[53])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[54]_i_1__0 + (.I0(sig_data_skid_reg[54]), + .I1(sig_data_fifo_data_out[54]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[54])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[55]_i_1__0 + (.I0(sig_data_skid_reg[55]), + .I1(sig_data_fifo_data_out[55]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[55])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[56]_i_1__0 + (.I0(sig_data_skid_reg[56]), + .I1(sig_data_fifo_data_out[56]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[56])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[57]_i_1__0 + (.I0(sig_data_skid_reg[57]), + .I1(sig_data_fifo_data_out[57]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[57])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[58]_i_1__0 + (.I0(sig_data_skid_reg[58]), + .I1(sig_data_fifo_data_out[58]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[58])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[59]_i_1__0 + (.I0(sig_data_skid_reg[59]), + .I1(sig_data_fifo_data_out[59]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[59])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[5]_i_1__0 + (.I0(sig_data_skid_reg[5]), + .I1(sig_data_fifo_data_out[5]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[5])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[60]_i_1__0 + (.I0(sig_data_skid_reg[60]), + .I1(sig_data_fifo_data_out[60]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[60])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[61]_i_1__0 + (.I0(sig_data_skid_reg[61]), + .I1(sig_data_fifo_data_out[61]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[61])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[62]_i_1__0 + (.I0(sig_data_skid_reg[62]), + .I1(sig_data_fifo_data_out[62]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[62])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[63]_i_1 + (.I0(sig_data_skid_reg[63]), + .I1(sig_data_fifo_data_out[63]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[63])); + LUT2 #( + .INIT(4'hE)) + \sig_data_reg_out[67]_i_2 + (.I0(sig_data_skid_reg[67]), + .I1(sig_s_ready_dup), + .O(\sig_data_reg_out[67]_i_2_n_0 )); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[6]_i_1__0 + (.I0(sig_data_skid_reg[6]), + .I1(sig_data_fifo_data_out[6]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[6])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[7]_i_1__0 + (.I0(sig_data_skid_reg[7]), + .I1(sig_data_fifo_data_out[7]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[7])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[8]_i_1__0 + (.I0(sig_data_skid_reg[8]), + .I1(sig_data_fifo_data_out[8]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[8])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[9]_i_1__0 + (.I0(sig_data_skid_reg[9]), + .I1(sig_data_fifo_data_out[9]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[9])); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[0]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [0]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[10]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [10]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[11]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [11]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[12]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [12]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[13] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[13]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [13]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[14] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[14]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [14]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[15] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[15]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [15]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[16] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[16]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [16]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[17] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[17]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [17]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[18] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[18]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [18]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[19] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[19]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [19]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[1]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [1]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[20] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[20]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [20]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[21] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[21]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [21]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[22] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[22]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [22]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[23] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[23]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [23]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[24] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[24]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [24]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[25] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[25]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [25]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[26] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[26]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [26]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[27] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[27]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [27]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[28] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[28]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [28]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[29] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[29]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [29]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[2]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [2]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[30] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[30]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [30]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[31] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[31]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [31]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[32] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[32]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [32]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[33] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[33]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [33]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[34] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[34]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [34]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[35] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[35]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [35]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[36] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[36]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [36]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[37] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[37]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [37]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[38] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[38]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [38]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[39] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[39]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [39]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[3]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [3]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[40] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[40]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [40]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[41] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[41]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [41]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[42] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[42]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [42]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[43] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[43]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [43]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[44] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[44]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [44]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[45] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[45]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [45]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[46] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[46]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [46]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[47] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[47]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [47]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[48] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[48]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [48]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[49] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[49]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [49]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[4]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [4]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[50] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[50]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [50]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[51] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[51]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [51]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[52] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[52]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [52]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[53] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[53]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [53]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[54] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[54]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [54]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[55] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[55]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [55]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[56] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[56]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [56]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[57] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[57]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [57]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[58] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[58]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [58]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[59] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[59]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [59]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[5]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [5]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[60] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[60]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [60]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[61] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[61]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [61]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[62] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[62]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [62]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[63] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[63]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [63]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[67] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(\sig_data_reg_out[67]_i_2_n_0 ), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [64]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[6]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [6]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[7]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [7]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[8]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [8]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_data_skid_mux_out[9]), + .Q(\GEN_INDET_BTT.lsig_byte_cntr_reg[3] [9]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[0]), + .Q(sig_data_skid_reg[0]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[10]), + .Q(sig_data_skid_reg[10]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[11]), + .Q(sig_data_skid_reg[11]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[12]), + .Q(sig_data_skid_reg[12]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[13] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[13]), + .Q(sig_data_skid_reg[13]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[14] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[14]), + .Q(sig_data_skid_reg[14]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[15] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[15]), + .Q(sig_data_skid_reg[15]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[16] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[16]), + .Q(sig_data_skid_reg[16]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[17] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[17]), + .Q(sig_data_skid_reg[17]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[18] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[18]), + .Q(sig_data_skid_reg[18]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[19] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[19]), + .Q(sig_data_skid_reg[19]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[1]), + .Q(sig_data_skid_reg[1]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[20] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[20]), + .Q(sig_data_skid_reg[20]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[21] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[21]), + .Q(sig_data_skid_reg[21]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[22] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[22]), + .Q(sig_data_skid_reg[22]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[23] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[23]), + .Q(sig_data_skid_reg[23]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[24] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[24]), + .Q(sig_data_skid_reg[24]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[25] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[25]), + .Q(sig_data_skid_reg[25]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[26] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[26]), + .Q(sig_data_skid_reg[26]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[27] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[27]), + .Q(sig_data_skid_reg[27]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[28] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[28]), + .Q(sig_data_skid_reg[28]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[29] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[29]), + .Q(sig_data_skid_reg[29]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[2]), + .Q(sig_data_skid_reg[2]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[30] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[30]), + .Q(sig_data_skid_reg[30]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[31] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[31]), + .Q(sig_data_skid_reg[31]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[32] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[32]), + .Q(sig_data_skid_reg[32]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[33] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[33]), + .Q(sig_data_skid_reg[33]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[34] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[34]), + .Q(sig_data_skid_reg[34]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[35] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[35]), + .Q(sig_data_skid_reg[35]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[36] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[36]), + .Q(sig_data_skid_reg[36]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[37] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[37]), + .Q(sig_data_skid_reg[37]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[38] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[38]), + .Q(sig_data_skid_reg[38]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[39] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[39]), + .Q(sig_data_skid_reg[39]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[3]), + .Q(sig_data_skid_reg[3]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[40] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[40]), + .Q(sig_data_skid_reg[40]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[41] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[41]), + .Q(sig_data_skid_reg[41]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[42] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[42]), + .Q(sig_data_skid_reg[42]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[43] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[43]), + .Q(sig_data_skid_reg[43]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[44] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[44]), + .Q(sig_data_skid_reg[44]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[45] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[45]), + .Q(sig_data_skid_reg[45]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[46] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[46]), + .Q(sig_data_skid_reg[46]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[47] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[47]), + .Q(sig_data_skid_reg[47]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[48] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[48]), + .Q(sig_data_skid_reg[48]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[49] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[49]), + .Q(sig_data_skid_reg[49]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[4]), + .Q(sig_data_skid_reg[4]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[50] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[50]), + .Q(sig_data_skid_reg[50]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[51] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[51]), + .Q(sig_data_skid_reg[51]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[52] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[52]), + .Q(sig_data_skid_reg[52]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[53] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[53]), + .Q(sig_data_skid_reg[53]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[54] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[54]), + .Q(sig_data_skid_reg[54]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[55] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[55]), + .Q(sig_data_skid_reg[55]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[56] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[56]), + .Q(sig_data_skid_reg[56]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[57] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[57]), + .Q(sig_data_skid_reg[57]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[58] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[58]), + .Q(sig_data_skid_reg[58]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[59] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[59]), + .Q(sig_data_skid_reg[59]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[5]), + .Q(sig_data_skid_reg[5]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[60] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[60]), + .Q(sig_data_skid_reg[60]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[61] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[61]), + .Q(sig_data_skid_reg[61]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[62] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[62]), + .Q(sig_data_skid_reg[62]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[63] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[63]), + .Q(sig_data_skid_reg[63]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[67] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(1'b1), + .Q(sig_data_skid_reg[67]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[6]), + .Q(sig_data_skid_reg[6]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[7]), + .Q(sig_data_skid_reg[7]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[8]), + .Q(sig_data_skid_reg[8]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[9]), + .Q(sig_data_skid_reg[9]), + .R(sig_stream_rst)); + LUT3 #( + .INIT(8'hB8)) + sig_last_reg_out_i_1 + (.I0(sig_data_fifo_data_out[64]), + .I1(sig_s_ready_dup), + .I2(sig_last_skid_reg), + .O(sig_last_skid_mux_out)); + FDRE #( + .INIT(1'b0)) + sig_last_reg_out_reg + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_last_skid_mux_out), + .Q(sig_ibtt2wdc_tlast), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + sig_last_skid_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[64]), + .Q(sig_last_skid_reg), + .R(sig_stream_rst)); + LUT6 #( + .INIT(64'h4444444400404040)) + sig_m_valid_dup_i_1__0 + (.I0(sig_init_reg), + .I1(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I2(sig_m_valid_dup), + .I3(sig_s_ready_dup), + .I4(sig_wdc2ibtt_tready), + .I5(sig_data_fifo_dvalid), + .O(sig_m_valid_dup_i_1__0_n_0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + sig_m_valid_dup_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_m_valid_dup_i_1__0_n_0), + .Q(sig_m_valid_dup), + .R(1'b0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + sig_m_valid_out_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_m_valid_dup_i_1__0_n_0), + .Q(sig_m_valid_out), + .R(1'b0)); + LUT6 #( + .INIT(64'hFFFFFFFFAEAEAEEE)) + sig_s_ready_dup_i_1__1 + (.I0(sig_init_reg), + .I1(sig_s_ready_dup), + .I2(sig_m_valid_dup), + .I3(hold_ff_q), + .I4(\gpregsm1.user_valid_reg_0 ), + .I5(sig_wdc2ibtt_tready), + .O(sig_s_ready_dup_i_1__1_n_0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + sig_s_ready_dup_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_s_ready_dup_i_1__1_n_0), + .Q(sig_s_ready_dup), + .R(sig_stream_rst)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + sig_s_ready_out_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_s_ready_dup_i_1__1_n_0), + .Q(sig_s_ready_out), + .R(sig_stream_rst)); + LUT3 #( + .INIT(8'hCA)) + \sig_strb_reg_out[8]_i_1 + (.I0(sig_strb_skid_reg), + .I1(sig_data_fifo_data_out[65]), + .I2(sig_s_ready_dup), + .O(sig_strb_skid_mux_out)); + FDRE #( + .INIT(1'b0)) + \sig_strb_reg_out_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(sig_strb_skid_mux_out), + .Q(sig_ibtt2wdc_eop), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_strb_skid_reg_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(sig_data_fifo_data_out[65]), + .Q(sig_strb_skid_reg), + .R(sig_stream_rst)); +endmodule + +(* ORIG_REF_NAME = "axi_datamover_slice" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_slice + (slice_insert_valid, + ld_btt_cntr_reg3_reg, + ld_btt_cntr_reg2_reg, + ld_btt_cntr_reg1_reg, + sig_valid_fifo_ld12_out, + S, + DI, + \storage_data_reg[3]_0 , + E, + in, + m_axi_s2mm_aclk, + sig_inhibit_rdy_n, + FIFO_Full_reg, + ld_btt_cntr_reg3, + ld_btt_cntr_reg2, + ld_btt_cntr_reg1, + sig_sm_ld_dre_cmd, + sig_cmd_full, + CO, + sig_eop_sent, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + \sig_max_first_increment_reg[0] , + out, + sig_btt_eq_0, + sig_stream_rst, + sig_curr_eof_reg); + output slice_insert_valid; + output ld_btt_cntr_reg3_reg; + output ld_btt_cntr_reg2_reg; + output ld_btt_cntr_reg1_reg; + output sig_valid_fifo_ld12_out; + output [3:0]S; + output [0:0]DI; + output [3:0]\storage_data_reg[3]_0 ; + output [0:0]E; + output [1:0]in; + input m_axi_s2mm_aclk; + input sig_inhibit_rdy_n; + input FIFO_Full_reg; + input ld_btt_cntr_reg3; + input ld_btt_cntr_reg2; + input ld_btt_cntr_reg1; + input sig_sm_ld_dre_cmd; + input sig_cmd_full; + input [0:0]CO; + input sig_eop_sent; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input \sig_max_first_increment_reg[0] ; + input [15:0]out; + input sig_btt_eq_0; + input sig_stream_rst; + input sig_curr_eof_reg; + + wire [0:0]CO; + wire [0:0]DI; + wire [0:0]E; + wire FIFO_Full_reg; + wire [3:0]S; + wire \areset_d_reg_n_0_[0] ; + wire [1:0]in; + wire ld_btt_cntr_reg1; + wire ld_btt_cntr_reg1_i_2_n_0; + wire ld_btt_cntr_reg1_reg; + wire ld_btt_cntr_reg2; + wire ld_btt_cntr_reg2_reg; + wire ld_btt_cntr_reg3; + wire ld_btt_cntr_reg3_reg; + wire m_axi_s2mm_aclk; + wire m_valid_i_i_1_n_0; + wire [15:0]out; + wire p_1_in; + wire sig_btt_eq_0; + wire sig_cmd_full; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_curr_eof_reg; + wire sig_eop_sent; + wire sig_inhibit_rdy_n; + wire \sig_max_first_increment_reg[0] ; + wire sig_sm_ld_dre_cmd; + wire sig_stream_rst; + wire sig_tstrb_fifo_rdy; + wire sig_tstrb_fifo_valid; + wire sig_valid_fifo_ld12_out; + wire slice_insert_valid; + wire \storage_data[2]_i_1_n_0 ; + wire \storage_data[3]_i_1_n_0 ; + wire [3:0]\storage_data_reg[3]_0 ; + + FDRE \areset_d_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_stream_rst), + .Q(\areset_d_reg_n_0_[0] ), + .R(1'b0)); + FDRE \areset_d_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\areset_d_reg_n_0_[0] ), + .Q(p_1_in), + .R(1'b0)); + LUT4 #( + .INIT(16'h00AE)) + ld_btt_cntr_reg1_i_1 + (.I0(ld_btt_cntr_reg1), + .I1(sig_sm_ld_dre_cmd), + .I2(sig_cmd_full), + .I3(ld_btt_cntr_reg1_i_2_n_0), + .O(ld_btt_cntr_reg1_reg)); + (* SOFT_HLUTNM = "soft_lutpair231" *) + LUT4 #( + .INIT(16'hF8FF)) + ld_btt_cntr_reg1_i_2 + (.I0(CO), + .I1(sig_valid_fifo_ld12_out), + .I2(sig_eop_sent), + .I3(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .O(ld_btt_cntr_reg1_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair230" *) + LUT4 #( + .INIT(16'h00E2)) + ld_btt_cntr_reg2_i_1 + (.I0(ld_btt_cntr_reg2), + .I1(sig_tstrb_fifo_rdy), + .I2(ld_btt_cntr_reg1), + .I3(ld_btt_cntr_reg1_i_2_n_0), + .O(ld_btt_cntr_reg2_reg)); + LUT5 #( + .INIT(32'h0000005D)) + ld_btt_cntr_reg2_i_2 + (.I0(slice_insert_valid), + .I1(sig_inhibit_rdy_n), + .I2(FIFO_Full_reg), + .I3(\areset_d_reg_n_0_[0] ), + .I4(p_1_in), + .O(sig_tstrb_fifo_rdy)); + (* SOFT_HLUTNM = "soft_lutpair230" *) + LUT4 #( + .INIT(16'h00EA)) + ld_btt_cntr_reg3_i_1 + (.I0(ld_btt_cntr_reg3), + .I1(sig_tstrb_fifo_rdy), + .I2(ld_btt_cntr_reg2), + .I3(ld_btt_cntr_reg1_i_2_n_0), + .O(ld_btt_cntr_reg3_reg)); + LUT5 #( + .INIT(32'h0000FFA2)) + m_valid_i_i_1 + (.I0(slice_insert_valid), + .I1(sig_inhibit_rdy_n), + .I2(FIFO_Full_reg), + .I3(sig_tstrb_fifo_valid), + .I4(p_1_in), + .O(m_valid_i_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair232" *) + LUT3 #( + .INIT(8'hBA)) + m_valid_i_i_2 + (.I0(ld_btt_cntr_reg2), + .I1(sig_btt_eq_0), + .I2(ld_btt_cntr_reg3), + .O(sig_tstrb_fifo_valid)); + FDRE m_valid_i_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(m_valid_i_i_1_n_0), + .Q(slice_insert_valid), + .R(1'b0)); + LUT4 #( + .INIT(16'h4F44)) + \sig_btt_cntr[15]_i_2 + (.I0(sig_cmd_full), + .I1(sig_sm_ld_dre_cmd), + .I2(sig_btt_eq_0), + .I3(sig_valid_fifo_ld12_out), + .O(E)); + LUT2 #( + .INIT(4'h1)) + sig_btt_lteq_max_first_incr0_carry__0_i_1 + (.I0(out[14]), + .I1(out[15]), + .O(\storage_data_reg[3]_0 [3])); + LUT2 #( + .INIT(4'h1)) + sig_btt_lteq_max_first_incr0_carry__0_i_2 + (.I0(out[12]), + .I1(out[13]), + .O(\storage_data_reg[3]_0 [2])); + LUT2 #( + .INIT(4'h1)) + sig_btt_lteq_max_first_incr0_carry__0_i_3 + (.I0(out[10]), + .I1(out[11]), + .O(\storage_data_reg[3]_0 [1])); + LUT2 #( + .INIT(4'h1)) + sig_btt_lteq_max_first_incr0_carry__0_i_4 + (.I0(out[8]), + .I1(out[9]), + .O(\storage_data_reg[3]_0 [0])); + LUT3 #( + .INIT(8'h04)) + sig_btt_lteq_max_first_incr0_carry_i_1 + (.I0(out[0]), + .I1(\sig_max_first_increment_reg[0] ), + .I2(out[1]), + .O(DI)); + LUT2 #( + .INIT(4'h1)) + sig_btt_lteq_max_first_incr0_carry_i_2 + (.I0(out[6]), + .I1(out[7]), + .O(S[3])); + LUT2 #( + .INIT(4'h1)) + sig_btt_lteq_max_first_incr0_carry_i_3 + (.I0(out[4]), + .I1(out[5]), + .O(S[2])); + LUT2 #( + .INIT(4'h1)) + sig_btt_lteq_max_first_incr0_carry_i_4 + (.I0(out[2]), + .I1(out[3]), + .O(S[1])); + LUT3 #( + .INIT(8'h09)) + sig_btt_lteq_max_first_incr0_carry_i_5 + (.I0(\sig_max_first_increment_reg[0] ), + .I1(out[0]), + .I2(out[1]), + .O(S[0])); + LUT4 #( + .INIT(16'h8F80)) + \storage_data[2]_i_1 + (.I0(sig_curr_eof_reg), + .I1(CO), + .I2(sig_valid_fifo_ld12_out), + .I3(in[0]), + .O(\storage_data[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair231" *) + LUT3 #( + .INIT(8'hB8)) + \storage_data[3]_i_1 + (.I0(CO), + .I1(sig_valid_fifo_ld12_out), + .I2(in[1]), + .O(\storage_data[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair232" *) + LUT4 #( + .INIT(16'hF200)) + \storage_data[3]_i_2 + (.I0(ld_btt_cntr_reg3), + .I1(sig_btt_eq_0), + .I2(ld_btt_cntr_reg2), + .I3(sig_tstrb_fifo_rdy), + .O(sig_valid_fifo_ld12_out)); + FDRE \storage_data_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\storage_data[2]_i_1_n_0 ), + .Q(in[0]), + .R(1'b0)); + FDRE \storage_data_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\storage_data[3]_i_1_n_0 ), + .Q(in[1]), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "axi_datamover_wr_status_cntl" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_wr_status_cntl + (sig_wsc2stat_status_valid, + in, + sig_wdc_status_going_full, + sig_init_reg, + sig_halt_reg, + sig_push_to_wsc_reg, + sig_wr_fifo, + m_axi_s2mm_bready, + sig_input_cache_type_reg0, + SR, + sig_wsc2rst_stop_cmplt, + sig_init_done_reg, + sig_init_done_reg_0, + sig_init_done_reg_1, + sig_init_done_reg_2, + sig_stream_rst, + m_axi_s2mm_aclk, + sig_inhibit_rdy_n_reg, + sig_s_h_halt_reg_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_data2wsc_valid, + sig_set_push2wsc, + out, + m_axi_s2mm_bvalid, + sig_psm_pop_input_cmd, + sig_csm_pop_child_cmd, + sig_halt_reg_dly3, + sig_addr2wsc_calc_error, + sig_init_reg2, + sig_init_done, + sig_init_done_0, + sig_init_done_1, + sig_init_done_2, + m_axi_s2mm_bresp, + \GEN_INDET_BTT.lsig_eop_reg_reg ); + output sig_wsc2stat_status_valid; + output [16:0]in; + output sig_wdc_status_going_full; + output sig_init_reg; + output sig_halt_reg; + output sig_push_to_wsc_reg; + output sig_wr_fifo; + output m_axi_s2mm_bready; + output sig_input_cache_type_reg0; + output [0:0]SR; + output sig_wsc2rst_stop_cmplt; + output sig_init_done_reg; + output sig_init_done_reg_0; + output sig_init_done_reg_1; + output sig_init_done_reg_2; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input sig_inhibit_rdy_n_reg; + input sig_s_h_halt_reg_reg; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_data2wsc_valid; + input sig_set_push2wsc; + input out; + input m_axi_s2mm_bvalid; + input sig_psm_pop_input_cmd; + input sig_csm_pop_child_cmd; + input sig_halt_reg_dly3; + input sig_addr2wsc_calc_error; + input sig_init_reg2; + input sig_init_done; + input sig_init_done_0; + input sig_init_done_1; + input sig_init_done_2; + input [1:0]m_axi_s2mm_bresp; + input [15:0]\GEN_INDET_BTT.lsig_eop_reg_reg ; + + wire \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_18 ; + wire \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_19 ; + wire \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_20 ; + wire \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_22 ; + wire \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_24 ; + wire [15:0]\GEN_INDET_BTT.lsig_eop_reg_reg ; + wire I_WRESP_STATUS_FIFO_n_1; + wire I_WRESP_STATUS_FIFO_n_2; + wire I_WRESP_STATUS_FIFO_n_3; + wire I_WRESP_STATUS_FIFO_n_4; + wire I_WRESP_STATUS_FIFO_n_5; + wire I_WRESP_STATUS_FIFO_n_7; + wire [0:0]SR; + wire [16:0]in; + wire m_axi_s2mm_aclk; + wire m_axi_s2mm_bready; + wire [1:0]m_axi_s2mm_bresp; + wire m_axi_s2mm_bvalid; + wire out; + wire p_0_in; + wire p_4_out; + wire sig_addr2wsc_calc_error; + wire \sig_addr_posted_cntr[0]_i_1__0_n_0 ; + wire [3:0]sig_addr_posted_cntr_reg; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_coelsc_reg_empty; + wire sig_csm_pop_child_cmd; + wire sig_data2wsc_valid; + wire [22:4]sig_dcntl_sfifo_out; + wire sig_halt_reg; + wire sig_halt_reg_dly3; + wire sig_inhibit_rdy_n_reg; + wire sig_init_done; + wire sig_init_done_0; + wire sig_init_done_1; + wire sig_init_done_2; + wire sig_init_done_reg; + wire sig_init_done_reg_0; + wire sig_init_done_reg_1; + wire sig_init_done_reg_2; + wire sig_init_reg; + wire sig_init_reg2; + wire sig_input_cache_type_reg0; + wire sig_psm_pop_input_cmd; + wire sig_push_coelsc_reg; + wire sig_push_to_wsc_reg; + wire sig_rd_empty; + wire sig_s_h_halt_reg_reg; + wire sig_set_push2wsc; + wire sig_statcnt_gt_eq_thres; + wire sig_stream_rst; + wire \sig_wdc_statcnt[0]_i_1_n_0 ; + wire [3:0]sig_wdc_statcnt_reg__0; + wire sig_wdc_status_going_full; + wire sig_wr_fifo; + wire sig_wsc2rst_stop_cmplt; + wire sig_wsc2stat_status_valid; + + Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized6 \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO + (.D({\GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_18 ,\GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_19 ,\GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_20 }), + .E(\GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_24 ), + .\GEN_INDET_BTT.lsig_eop_reg_reg (\GEN_INDET_BTT.lsig_eop_reg_reg ), + .\INFERRED_GEN.cnt_i_reg[1] (\GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_22 ), + .\INFERRED_GEN.cnt_i_reg[3] (sig_rd_empty), + .Q(sig_wdc_statcnt_reg__0), + .in(in[0]), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out({sig_dcntl_sfifo_out[22:9],sig_dcntl_sfifo_out[5:4]}), + .p_0_in(p_0_in), + .p_4_out(p_4_out), + .sel(sig_wr_fifo), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_coelsc_reg_empty(sig_coelsc_reg_empty), + .sig_data2wsc_valid(sig_data2wsc_valid), + .sig_init_reg2(sig_init_reg2), + .sig_init_reg_reg(sig_init_reg), + .sig_push_coelsc_reg(sig_push_coelsc_reg), + .sig_push_to_wsc_reg(sig_push_to_wsc_reg), + .sig_set_push2wsc(sig_set_push2wsc), + .sig_stream_rst(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \GEN_ENABLE_INDET_BTT.sig_coelsc_bytes_rcvd_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(sig_push_coelsc_reg), + .D(sig_dcntl_sfifo_out[16]), + .Q(in[10]), + .R(sig_inhibit_rdy_n_reg)); + FDRE #( + .INIT(1'b0)) + \GEN_ENABLE_INDET_BTT.sig_coelsc_bytes_rcvd_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(sig_push_coelsc_reg), + .D(sig_dcntl_sfifo_out[17]), + .Q(in[11]), + .R(sig_inhibit_rdy_n_reg)); + FDRE #( + .INIT(1'b0)) + \GEN_ENABLE_INDET_BTT.sig_coelsc_bytes_rcvd_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(sig_push_coelsc_reg), + .D(sig_dcntl_sfifo_out[18]), + .Q(in[12]), + .R(sig_inhibit_rdy_n_reg)); + FDRE #( + .INIT(1'b0)) + \GEN_ENABLE_INDET_BTT.sig_coelsc_bytes_rcvd_reg[13] + (.C(m_axi_s2mm_aclk), + .CE(sig_push_coelsc_reg), + .D(sig_dcntl_sfifo_out[19]), + .Q(in[13]), + .R(sig_inhibit_rdy_n_reg)); + FDRE #( + .INIT(1'b0)) + \GEN_ENABLE_INDET_BTT.sig_coelsc_bytes_rcvd_reg[14] + (.C(m_axi_s2mm_aclk), + .CE(sig_push_coelsc_reg), + .D(sig_dcntl_sfifo_out[20]), + .Q(in[14]), + .R(sig_inhibit_rdy_n_reg)); + FDRE #( + .INIT(1'b0)) + \GEN_ENABLE_INDET_BTT.sig_coelsc_bytes_rcvd_reg[15] + (.C(m_axi_s2mm_aclk), + .CE(sig_push_coelsc_reg), + .D(sig_dcntl_sfifo_out[21]), + .Q(in[15]), + .R(sig_inhibit_rdy_n_reg)); + FDRE #( + .INIT(1'b0)) + \GEN_ENABLE_INDET_BTT.sig_coelsc_bytes_rcvd_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(sig_push_coelsc_reg), + .D(sig_dcntl_sfifo_out[9]), + .Q(in[3]), + .R(sig_inhibit_rdy_n_reg)); + FDRE #( + .INIT(1'b0)) + \GEN_ENABLE_INDET_BTT.sig_coelsc_bytes_rcvd_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(sig_push_coelsc_reg), + .D(sig_dcntl_sfifo_out[10]), + .Q(in[4]), + .R(sig_inhibit_rdy_n_reg)); + FDRE #( + .INIT(1'b0)) + \GEN_ENABLE_INDET_BTT.sig_coelsc_bytes_rcvd_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(sig_push_coelsc_reg), + .D(sig_dcntl_sfifo_out[11]), + .Q(in[5]), + .R(sig_inhibit_rdy_n_reg)); + FDRE #( + .INIT(1'b0)) + \GEN_ENABLE_INDET_BTT.sig_coelsc_bytes_rcvd_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(sig_push_coelsc_reg), + .D(sig_dcntl_sfifo_out[12]), + .Q(in[6]), + .R(sig_inhibit_rdy_n_reg)); + FDRE #( + .INIT(1'b0)) + \GEN_ENABLE_INDET_BTT.sig_coelsc_bytes_rcvd_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(sig_push_coelsc_reg), + .D(sig_dcntl_sfifo_out[13]), + .Q(in[7]), + .R(sig_inhibit_rdy_n_reg)); + FDRE #( + .INIT(1'b0)) + \GEN_ENABLE_INDET_BTT.sig_coelsc_bytes_rcvd_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(sig_push_coelsc_reg), + .D(sig_dcntl_sfifo_out[14]), + .Q(in[8]), + .R(sig_inhibit_rdy_n_reg)); + FDRE #( + .INIT(1'b0)) + \GEN_ENABLE_INDET_BTT.sig_coelsc_bytes_rcvd_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(sig_push_coelsc_reg), + .D(sig_dcntl_sfifo_out[15]), + .Q(in[9]), + .R(sig_inhibit_rdy_n_reg)); + FDRE #( + .INIT(1'b0)) + \GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(sig_push_coelsc_reg), + .D(I_WRESP_STATUS_FIFO_n_1), + .Q(in[1]), + .R(sig_inhibit_rdy_n_reg)); + FDRE #( + .INIT(1'b0)) + \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg + (.C(m_axi_s2mm_aclk), + .CE(sig_push_coelsc_reg), + .D(sig_dcntl_sfifo_out[22]), + .Q(in[16]), + .R(sig_inhibit_rdy_n_reg)); + FDRE #( + .INIT(1'b0)) + \GEN_ENABLE_INDET_BTT.sig_coelsc_interr_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(sig_push_coelsc_reg), + .D(p_4_out), + .Q(in[0]), + .R(sig_inhibit_rdy_n_reg)); + FDSE #( + .INIT(1'b0)) + \GEN_ENABLE_INDET_BTT.sig_coelsc_reg_empty_reg + (.C(m_axi_s2mm_aclk), + .CE(sig_push_coelsc_reg), + .D(p_0_in), + .Q(sig_coelsc_reg_empty), + .S(sig_inhibit_rdy_n_reg)); + FDRE #( + .INIT(1'b0)) + \GEN_ENABLE_INDET_BTT.sig_coelsc_reg_full_reg + (.C(m_axi_s2mm_aclk), + .CE(sig_push_coelsc_reg), + .D(sig_dcntl_sfifo_out[5]), + .Q(sig_wsc2stat_status_valid), + .R(sig_inhibit_rdy_n_reg)); + FDRE #( + .INIT(1'b0)) + \GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(sig_push_coelsc_reg), + .D(I_WRESP_STATUS_FIFO_n_2), + .Q(in[2]), + .R(sig_inhibit_rdy_n_reg)); + Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized5 I_WRESP_STATUS_FIFO + (.D({I_WRESP_STATUS_FIFO_n_3,I_WRESP_STATUS_FIFO_n_4,I_WRESP_STATUS_FIFO_n_5}), + .E(I_WRESP_STATUS_FIFO_n_7), + .\GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg (I_WRESP_STATUS_FIFO_n_1), + .\GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg (I_WRESP_STATUS_FIFO_n_2), + .\INFERRED_GEN.cnt_i_reg[2] (sig_rd_empty), + .\INFERRED_GEN.cnt_i_reg[3] (\GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_22 ), + .Q(sig_addr_posted_cntr_reg), + .SR(SR), + .in(in[2:1]), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .m_axi_s2mm_bready(m_axi_s2mm_bready), + .m_axi_s2mm_bresp(m_axi_s2mm_bresp), + .m_axi_s2mm_bvalid(m_axi_s2mm_bvalid), + .out(sig_dcntl_sfifo_out[4]), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_csm_pop_child_cmd(sig_csm_pop_child_cmd), + .sig_halt_reg(sig_halt_reg), + .sig_init_done(sig_init_done), + .sig_init_done_0(sig_init_done_0), + .sig_init_done_1(sig_init_done_1), + .sig_init_done_2(sig_init_done_2), + .sig_init_done_reg_0(sig_init_done_reg), + .sig_init_done_reg_1(sig_init_done_reg_0), + .sig_init_done_reg_2(sig_init_done_reg_1), + .sig_init_done_reg_3(sig_init_done_reg_2), + .sig_init_reg2(sig_init_reg2), + .sig_init_reg2_reg(sig_init_reg), + .sig_input_cache_type_reg0(sig_input_cache_type_reg0), + .sig_posted_to_axi_reg(out), + .sig_psm_pop_input_cmd(sig_psm_pop_input_cmd), + .sig_push_coelsc_reg(sig_push_coelsc_reg), + .sig_stream_rst(sig_stream_rst)); + LUT1 #( + .INIT(2'h1)) + \sig_addr_posted_cntr[0]_i_1__0 + (.I0(sig_addr_posted_cntr_reg[0]), + .O(\sig_addr_posted_cntr[0]_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_addr_posted_cntr_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(I_WRESP_STATUS_FIFO_n_7), + .D(\sig_addr_posted_cntr[0]_i_1__0_n_0 ), + .Q(sig_addr_posted_cntr_reg[0]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_addr_posted_cntr_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(I_WRESP_STATUS_FIFO_n_7), + .D(I_WRESP_STATUS_FIFO_n_5), + .Q(sig_addr_posted_cntr_reg[1]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_addr_posted_cntr_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(I_WRESP_STATUS_FIFO_n_7), + .D(I_WRESP_STATUS_FIFO_n_4), + .Q(sig_addr_posted_cntr_reg[2]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_addr_posted_cntr_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(I_WRESP_STATUS_FIFO_n_7), + .D(I_WRESP_STATUS_FIFO_n_3), + .Q(sig_addr_posted_cntr_reg[3]), + .R(sig_stream_rst)); + LUT6 #( + .INIT(64'h0000002000000002)) + sig_halt_cmplt_i_2__0 + (.I0(sig_halt_reg_dly3), + .I1(sig_addr_posted_cntr_reg[1]), + .I2(sig_addr_posted_cntr_reg[0]), + .I3(sig_addr_posted_cntr_reg[2]), + .I4(sig_addr_posted_cntr_reg[3]), + .I5(sig_addr2wsc_calc_error), + .O(sig_wsc2rst_stop_cmplt)); + FDRE #( + .INIT(1'b0)) + sig_halt_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_s_h_halt_reg_reg), + .Q(sig_halt_reg), + .R(sig_stream_rst)); + LUT1 #( + .INIT(2'h1)) + \sig_wdc_statcnt[0]_i_1 + (.I0(sig_wdc_statcnt_reg__0[0]), + .O(\sig_wdc_statcnt[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_wdc_statcnt_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_24 ), + .D(\sig_wdc_statcnt[0]_i_1_n_0 ), + .Q(sig_wdc_statcnt_reg__0[0]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_wdc_statcnt_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_24 ), + .D(\GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_20 ), + .Q(sig_wdc_statcnt_reg__0[1]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_wdc_statcnt_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_24 ), + .D(\GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_19 ), + .Q(sig_wdc_statcnt_reg__0[2]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_wdc_statcnt_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_24 ), + .D(\GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_18 ), + .Q(sig_wdc_statcnt_reg__0[3]), + .R(sig_stream_rst)); + LUT2 #( + .INIT(4'hE)) + sig_wdc_status_going_full_i_1 + (.I0(sig_wdc_statcnt_reg__0[3]), + .I1(sig_wdc_statcnt_reg__0[2]), + .O(sig_statcnt_gt_eq_thres)); + FDRE #( + .INIT(1'b0)) + sig_wdc_status_going_full_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_statcnt_gt_eq_thres), + .Q(sig_wdc_status_going_full), + .R(sig_stream_rst)); +endmodule + +(* ORIG_REF_NAME = "axi_datamover_wrdata_cntl" *) +module Arty_Z7_20_axi_vdma_0_0_axi_datamover_wrdata_cntl + (\INFERRED_GEN.cnt_i_reg[0] , + sig_dqual_reg_full, + sig_halt_reg_dly3, + sig_data2wsc_valid, + in, + lsig_eop_reg, + lsig_end_of_cmd_reg, + sig_init_done, + sig_set_push2wsc, + sig_dbeat_cntr_eq_0__2, + E, + sig_wdc2ibtt_tready, + sig_inhibit_rdy_n, + sig_clr_cmd2data_valid4_out__0, + sig_data2skid_wvalid, + sig_data2rst_stop_cmplt, + sig_stream_rst, + m_axi_s2mm_aclk, + sig_halt_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0, + sig_m_valid_out_reg, + sig_init_reg_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_wr_fifo, + out, + sig_m_valid_out_reg_0, + \sig_data_reg_out_reg[67] , + sig_ibtt2wdc_tlast, + p_11_out, + sig_s_ready_out_reg, + sig_wdc_status_going_full, + sig_inhibit_rdy_n_reg, + sig_wsc2stat_status_valid, + sig_posted_to_axi_reg, + sig_xfer_calc_err_reg_reg, + SR, + sig_m_valid_out_reg_1, + sig_m_valid_out_reg_2); + output \INFERRED_GEN.cnt_i_reg[0] ; + output sig_dqual_reg_full; + output sig_halt_reg_dly3; + output sig_data2wsc_valid; + output [15:0]in; + output lsig_eop_reg; + output lsig_end_of_cmd_reg; + output sig_init_done; + output sig_set_push2wsc; + output sig_dbeat_cntr_eq_0__2; + output [0:0]E; + output sig_wdc2ibtt_tready; + output sig_inhibit_rdy_n; + output sig_clr_cmd2data_valid4_out__0; + output sig_data2skid_wvalid; + output sig_data2rst_stop_cmplt; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input sig_halt_reg; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0; + input sig_m_valid_out_reg; + input sig_init_reg_reg; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_wr_fifo; + input out; + input sig_m_valid_out_reg_0; + input [0:0]\sig_data_reg_out_reg[67] ; + input sig_ibtt2wdc_tlast; + input p_11_out; + input sig_s_ready_out_reg; + input sig_wdc_status_going_full; + input sig_inhibit_rdy_n_reg; + input sig_wsc2stat_status_valid; + input sig_posted_to_axi_reg; + input [8:0]sig_xfer_calc_err_reg_reg; + input [0:0]SR; + input [0:0]sig_m_valid_out_reg_1; + input [0:0]sig_m_valid_out_reg_2; + + wire [0:0]E; + wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_16 ; + wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_2 ; + wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_20 ; + wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_4 ; + wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_5 ; + wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_7 ; + wire \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_8 ; + wire \GEN_INDET_BTT.lsig_byte_cntr[10]_i_2_n_0 ; + wire \GEN_INDET_BTT.lsig_byte_cntr[10]_i_3_n_0 ; + wire \GEN_INDET_BTT.lsig_byte_cntr[10]_i_4_n_0 ; + wire \GEN_INDET_BTT.lsig_byte_cntr[10]_i_5_n_0 ; + wire \GEN_INDET_BTT.lsig_byte_cntr[14]_i_2_n_0 ; + wire \GEN_INDET_BTT.lsig_byte_cntr[14]_i_3_n_0 ; + wire \GEN_INDET_BTT.lsig_byte_cntr[14]_i_4_n_0 ; + wire \GEN_INDET_BTT.lsig_byte_cntr[14]_i_5_n_0 ; + wire \GEN_INDET_BTT.lsig_byte_cntr[15]_i_5_n_0 ; + wire \GEN_INDET_BTT.lsig_byte_cntr[3]_i_1_n_0 ; + wire \GEN_INDET_BTT.lsig_byte_cntr[6]_i_3_n_0 ; + wire \GEN_INDET_BTT.lsig_byte_cntr[6]_i_4_n_0 ; + wire \GEN_INDET_BTT.lsig_byte_cntr[6]_i_5_n_0 ; + wire \GEN_INDET_BTT.lsig_byte_cntr[6]_i_6_n_0 ; + wire \GEN_INDET_BTT.lsig_byte_cntr[7]_i_1_n_0 ; + wire \GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_0 ; + wire \GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_1 ; + wire \GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_2 ; + wire \GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_3 ; + wire \GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_4 ; + wire \GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_5 ; + wire \GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_6 ; + wire \GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_7 ; + wire \GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_0 ; + wire \GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_1 ; + wire \GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_2 ; + wire \GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_3 ; + wire \GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_4 ; + wire \GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_5 ; + wire \GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_6 ; + wire \GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_7 ; + wire \GEN_INDET_BTT.lsig_byte_cntr_reg[15]_i_3_n_7 ; + wire \GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_0 ; + wire \GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_1 ; + wire \GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_2 ; + wire \GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_3 ; + wire \GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_4 ; + wire \GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_5 ; + wire \GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_6 ; + wire \GEN_INDET_BTT.lsig_end_of_cmd_reg_i_1_n_0 ; + wire \INFERRED_GEN.cnt_i_reg[0] ; + wire [0:0]SR; + wire [15:0]in; + wire lsig_end_of_cmd_reg; + wire lsig_eop_reg; + wire m_axi_s2mm_aclk; + wire out; + wire [5:0]p_0_in__0; + wire p_11_out; + wire [2:0]sig_addr_posted_cntr; + wire \sig_addr_posted_cntr[0]_i_1_n_0 ; + wire \sig_addr_posted_cntr[1]_i_1_n_0 ; + wire \sig_addr_posted_cntr[2]_i_1_n_0 ; + wire sig_clr_cmd2data_valid4_out__0; + wire [35:33]sig_cmd_fifo_data_out; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0; + wire sig_data2rst_stop_cmplt; + wire sig_data2skid_wvalid; + wire sig_data2wsc_calc_err_i_1_n_0; + wire sig_data2wsc_cmd_cmplt_i_1_n_0; + wire sig_data2wsc_valid; + wire [0:0]\sig_data_reg_out_reg[67] ; + wire \sig_dbeat_cntr[4]_i_2_n_0 ; + wire \sig_dbeat_cntr[5]_i_2_n_0 ; + wire \sig_dbeat_cntr[7]_i_3__0_n_0 ; + wire sig_dbeat_cntr_eq_0__2; + wire [7:0]sig_dbeat_cntr_reg__0; + wire sig_dqual_reg_empty; + wire sig_dqual_reg_full; + wire sig_first_dbeat1__0; + wire sig_good_mmap_dbeat12_out__0; + wire sig_halt_reg; + wire sig_halt_reg_dly1; + wire sig_halt_reg_dly2; + wire sig_halt_reg_dly3; + wire sig_ibtt2wdc_tlast; + wire sig_inhibit_rdy_n; + wire sig_inhibit_rdy_n_reg; + wire sig_init_done; + wire sig_init_reg_reg; + wire sig_last_dbeat_reg_n_0; + wire sig_last_mmap_dbeat; + wire sig_last_mmap_dbeat_reg; + wire sig_last_reg_out_i_4_n_0; + wire sig_ld_new_cmd_reg; + wire sig_m_valid_out_reg; + wire sig_m_valid_out_reg_0; + wire [0:0]sig_m_valid_out_reg_1; + wire [0:0]sig_m_valid_out_reg_2; + wire sig_next_calc_error_reg; + wire sig_next_cmd_cmplt_reg; + wire sig_next_sequential_reg; + wire sig_posted_to_axi_reg; + wire sig_push_dqual_reg; + wire sig_push_err2wsc; + wire sig_push_err2wsc_i_1_n_0; + wire sig_s_ready_out_reg; + wire sig_set_push2wsc; + wire sig_single_dbeat; + wire sig_stream_rst; + wire sig_wdc2ibtt_tready; + wire sig_wdc_status_going_full; + wire sig_wr_fifo; + wire sig_wsc2stat_status_valid; + wire [8:0]sig_xfer_calc_err_reg_reg; + wire [3:0]\NLW_GEN_INDET_BTT.lsig_byte_cntr_reg[15]_i_3_CO_UNCONNECTED ; + wire [3:1]\NLW_GEN_INDET_BTT.lsig_byte_cntr_reg[15]_i_3_O_UNCONNECTED ; + wire [0:0]\NLW_GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_O_UNCONNECTED ; + + Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized10 \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO + (.D({\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_7 ,\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_8 ,p_0_in__0}), + .E(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_16 ), + .\INFERRED_GEN.cnt_i_reg[0] (\INFERRED_GEN.cnt_i_reg[0] ), + .\INFERRED_GEN.cnt_i_reg[0]_0 (sig_inhibit_rdy_n), + .Q(sig_dbeat_cntr_reg__0), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(sig_cmd_fifo_data_out), + .p_11_out(p_11_out), + .sig_addr_posted_cntr(sig_addr_posted_cntr), + .sig_clr_cmd2data_valid4_out__0(sig_clr_cmd2data_valid4_out__0), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .\sig_dbeat_cntr_reg[1] (sig_dbeat_cntr_eq_0__2), + .\sig_dbeat_cntr_reg[2] (\sig_dbeat_cntr[4]_i_2_n_0 ), + .\sig_dbeat_cntr_reg[3] (\sig_dbeat_cntr[5]_i_2_n_0 ), + .\sig_dbeat_cntr_reg[4] (\sig_dbeat_cntr[7]_i_3__0_n_0 ), + .sig_dqual_reg_empty(sig_dqual_reg_empty), + .sig_dqual_reg_empty_reg(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_20 ), + .sig_dqual_reg_full_reg(sig_dqual_reg_full), + .sig_first_dbeat1__0(sig_first_dbeat1__0), + .sig_good_mmap_dbeat12_out__0(sig_good_mmap_dbeat12_out__0), + .sig_halt_reg(sig_halt_reg), + .sig_halt_reg_dly3(sig_halt_reg_dly3), + .sig_inhibit_rdy_n_reg_0(sig_inhibit_rdy_n_reg), + .sig_init_done(sig_init_done), + .sig_init_reg_reg(sig_init_reg_reg), + .sig_last_dbeat_reg(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_2 ), + .sig_last_dbeat_reg_0(sig_last_dbeat_reg_n_0), + .sig_last_mmap_dbeat_reg(sig_last_mmap_dbeat_reg), + .sig_ld_new_cmd_reg(sig_ld_new_cmd_reg), + .sig_ld_new_cmd_reg_reg(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_4 ), + .sig_m_valid_out_reg(sig_m_valid_out_reg_0), + .sig_next_calc_error_reg(sig_next_calc_error_reg), + .sig_next_calc_error_reg_reg(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_5 ), + .sig_next_sequential_reg(sig_next_sequential_reg), + .sig_posted_to_axi_reg(sig_posted_to_axi_reg), + .sig_push_dqual_reg(sig_push_dqual_reg), + .sig_s_ready_out_reg(sig_s_ready_out_reg), + .sig_single_dbeat(sig_single_dbeat), + .sig_stream_rst(sig_stream_rst), + .sig_wdc_status_going_full(sig_wdc_status_going_full), + .sig_wsc2stat_status_valid(sig_wsc2stat_status_valid), + .sig_xfer_calc_err_reg_reg(sig_xfer_calc_err_reg_reg)); + LUT4 #( + .INIT(16'h70F0)) + \GEN_INDET_BTT.lsig_byte_cntr[10]_i_2 + (.I0(sig_m_valid_out_reg_0), + .I1(sig_wdc2ibtt_tready), + .I2(in[9]), + .I3(lsig_end_of_cmd_reg), + .O(\GEN_INDET_BTT.lsig_byte_cntr[10]_i_2_n_0 )); + LUT4 #( + .INIT(16'h70F0)) + \GEN_INDET_BTT.lsig_byte_cntr[10]_i_3 + (.I0(sig_m_valid_out_reg_0), + .I1(sig_wdc2ibtt_tready), + .I2(in[8]), + .I3(lsig_end_of_cmd_reg), + .O(\GEN_INDET_BTT.lsig_byte_cntr[10]_i_3_n_0 )); + LUT4 #( + .INIT(16'h70F0)) + \GEN_INDET_BTT.lsig_byte_cntr[10]_i_4 + (.I0(sig_m_valid_out_reg_0), + .I1(sig_wdc2ibtt_tready), + .I2(in[7]), + .I3(lsig_end_of_cmd_reg), + .O(\GEN_INDET_BTT.lsig_byte_cntr[10]_i_4_n_0 )); + LUT4 #( + .INIT(16'h70F0)) + \GEN_INDET_BTT.lsig_byte_cntr[10]_i_5 + (.I0(sig_m_valid_out_reg_0), + .I1(sig_wdc2ibtt_tready), + .I2(in[6]), + .I3(lsig_end_of_cmd_reg), + .O(\GEN_INDET_BTT.lsig_byte_cntr[10]_i_5_n_0 )); + LUT4 #( + .INIT(16'h70F0)) + \GEN_INDET_BTT.lsig_byte_cntr[14]_i_2 + (.I0(sig_m_valid_out_reg_0), + .I1(sig_wdc2ibtt_tready), + .I2(in[13]), + .I3(lsig_end_of_cmd_reg), + .O(\GEN_INDET_BTT.lsig_byte_cntr[14]_i_2_n_0 )); + LUT4 #( + .INIT(16'h70F0)) + \GEN_INDET_BTT.lsig_byte_cntr[14]_i_3 + (.I0(sig_m_valid_out_reg_0), + .I1(sig_wdc2ibtt_tready), + .I2(in[12]), + .I3(lsig_end_of_cmd_reg), + .O(\GEN_INDET_BTT.lsig_byte_cntr[14]_i_3_n_0 )); + LUT4 #( + .INIT(16'h70F0)) + \GEN_INDET_BTT.lsig_byte_cntr[14]_i_4 + (.I0(sig_m_valid_out_reg_0), + .I1(sig_wdc2ibtt_tready), + .I2(in[11]), + .I3(lsig_end_of_cmd_reg), + .O(\GEN_INDET_BTT.lsig_byte_cntr[14]_i_4_n_0 )); + LUT4 #( + .INIT(16'h70F0)) + \GEN_INDET_BTT.lsig_byte_cntr[14]_i_5 + (.I0(sig_m_valid_out_reg_0), + .I1(sig_wdc2ibtt_tready), + .I2(in[10]), + .I3(lsig_end_of_cmd_reg), + .O(\GEN_INDET_BTT.lsig_byte_cntr[14]_i_5_n_0 )); + LUT5 #( + .INIT(32'hAAAAEAAA)) + \GEN_INDET_BTT.lsig_byte_cntr[15]_i_4 + (.I0(sig_halt_reg), + .I1(sig_s_ready_out_reg), + .I2(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_20 ), + .I3(sig_dqual_reg_full), + .I4(sig_next_calc_error_reg), + .O(sig_wdc2ibtt_tready)); + LUT4 #( + .INIT(16'h70F0)) + \GEN_INDET_BTT.lsig_byte_cntr[15]_i_5 + (.I0(sig_m_valid_out_reg_0), + .I1(sig_wdc2ibtt_tready), + .I2(in[14]), + .I3(lsig_end_of_cmd_reg), + .O(\GEN_INDET_BTT.lsig_byte_cntr[15]_i_5_n_0 )); + LUT5 #( + .INIT(32'h8F0F70F0)) + \GEN_INDET_BTT.lsig_byte_cntr[3]_i_1 + (.I0(sig_m_valid_out_reg_0), + .I1(sig_wdc2ibtt_tready), + .I2(in[2]), + .I3(lsig_end_of_cmd_reg), + .I4(\sig_data_reg_out_reg[67] ), + .O(\GEN_INDET_BTT.lsig_byte_cntr[3]_i_1_n_0 )); + LUT4 #( + .INIT(16'h70F0)) + \GEN_INDET_BTT.lsig_byte_cntr[6]_i_3 + (.I0(sig_m_valid_out_reg_0), + .I1(sig_wdc2ibtt_tready), + .I2(in[5]), + .I3(lsig_end_of_cmd_reg), + .O(\GEN_INDET_BTT.lsig_byte_cntr[6]_i_3_n_0 )); + LUT4 #( + .INIT(16'h70F0)) + \GEN_INDET_BTT.lsig_byte_cntr[6]_i_4 + (.I0(sig_m_valid_out_reg_0), + .I1(sig_wdc2ibtt_tready), + .I2(in[4]), + .I3(lsig_end_of_cmd_reg), + .O(\GEN_INDET_BTT.lsig_byte_cntr[6]_i_4_n_0 )); + LUT4 #( + .INIT(16'h70F0)) + \GEN_INDET_BTT.lsig_byte_cntr[6]_i_5 + (.I0(sig_m_valid_out_reg_0), + .I1(sig_wdc2ibtt_tready), + .I2(in[3]), + .I3(lsig_end_of_cmd_reg), + .O(\GEN_INDET_BTT.lsig_byte_cntr[6]_i_5_n_0 )); + LUT5 #( + .INIT(32'h8F0F70F0)) + \GEN_INDET_BTT.lsig_byte_cntr[6]_i_6 + (.I0(sig_m_valid_out_reg_0), + .I1(sig_wdc2ibtt_tready), + .I2(in[2]), + .I3(lsig_end_of_cmd_reg), + .I4(\sig_data_reg_out_reg[67] ), + .O(\GEN_INDET_BTT.lsig_byte_cntr[6]_i_6_n_0 )); + LUT4 #( + .INIT(16'h70FF)) + \GEN_INDET_BTT.lsig_byte_cntr[7]_i_1 + (.I0(sig_m_valid_out_reg_0), + .I1(sig_wdc2ibtt_tready), + .I2(lsig_end_of_cmd_reg), + .I3(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .O(\GEN_INDET_BTT.lsig_byte_cntr[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_INDET_BTT.lsig_byte_cntr_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(sig_m_valid_out_reg_1), + .D(\GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_4 ), + .Q(in[9]), + .R(SR)); + CARRY4 \GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1 + (.CI(\GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_0 ), + .CO({\GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_0 ,\GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_1 ,\GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_2 ,\GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_4 ,\GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_5 ,\GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_6 ,\GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_7 }), + .S({\GEN_INDET_BTT.lsig_byte_cntr[10]_i_2_n_0 ,\GEN_INDET_BTT.lsig_byte_cntr[10]_i_3_n_0 ,\GEN_INDET_BTT.lsig_byte_cntr[10]_i_4_n_0 ,\GEN_INDET_BTT.lsig_byte_cntr[10]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \GEN_INDET_BTT.lsig_byte_cntr_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(sig_m_valid_out_reg_1), + .D(\GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_7 ), + .Q(in[10]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_INDET_BTT.lsig_byte_cntr_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(sig_m_valid_out_reg_1), + .D(\GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_6 ), + .Q(in[11]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_INDET_BTT.lsig_byte_cntr_reg[13] + (.C(m_axi_s2mm_aclk), + .CE(sig_m_valid_out_reg_1), + .D(\GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_5 ), + .Q(in[12]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_INDET_BTT.lsig_byte_cntr_reg[14] + (.C(m_axi_s2mm_aclk), + .CE(sig_m_valid_out_reg_1), + .D(\GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_4 ), + .Q(in[13]), + .R(SR)); + CARRY4 \GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1 + (.CI(\GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_0 ), + .CO({\GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_0 ,\GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_1 ,\GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_2 ,\GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_4 ,\GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_5 ,\GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_6 ,\GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_7 }), + .S({\GEN_INDET_BTT.lsig_byte_cntr[14]_i_2_n_0 ,\GEN_INDET_BTT.lsig_byte_cntr[14]_i_3_n_0 ,\GEN_INDET_BTT.lsig_byte_cntr[14]_i_4_n_0 ,\GEN_INDET_BTT.lsig_byte_cntr[14]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \GEN_INDET_BTT.lsig_byte_cntr_reg[15] + (.C(m_axi_s2mm_aclk), + .CE(sig_m_valid_out_reg_1), + .D(\GEN_INDET_BTT.lsig_byte_cntr_reg[15]_i_3_n_7 ), + .Q(in[14]), + .R(SR)); + CARRY4 \GEN_INDET_BTT.lsig_byte_cntr_reg[15]_i_3 + (.CI(\GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_0 ), + .CO(\NLW_GEN_INDET_BTT.lsig_byte_cntr_reg[15]_i_3_CO_UNCONNECTED [3:0]), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_GEN_INDET_BTT.lsig_byte_cntr_reg[15]_i_3_O_UNCONNECTED [3:1],\GEN_INDET_BTT.lsig_byte_cntr_reg[15]_i_3_n_7 }), + .S({1'b0,1'b0,1'b0,\GEN_INDET_BTT.lsig_byte_cntr[15]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \GEN_INDET_BTT.lsig_byte_cntr_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(sig_m_valid_out_reg_1), + .D(\GEN_INDET_BTT.lsig_byte_cntr[3]_i_1_n_0 ), + .Q(in[2]), + .R(\GEN_INDET_BTT.lsig_byte_cntr[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_INDET_BTT.lsig_byte_cntr_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(sig_m_valid_out_reg_1), + .D(\GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_6 ), + .Q(in[3]), + .R(\GEN_INDET_BTT.lsig_byte_cntr[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_INDET_BTT.lsig_byte_cntr_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(sig_m_valid_out_reg_1), + .D(\GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_5 ), + .Q(in[4]), + .R(\GEN_INDET_BTT.lsig_byte_cntr[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_INDET_BTT.lsig_byte_cntr_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(sig_m_valid_out_reg_1), + .D(\GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_4 ), + .Q(in[5]), + .R(\GEN_INDET_BTT.lsig_byte_cntr[7]_i_1_n_0 )); + CARRY4 \GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1 + (.CI(1'b0), + .CO({\GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_0 ,\GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_1 ,\GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_2 ,\GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,sig_m_valid_out_reg_2}), + .O({\GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_4 ,\GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_5 ,\GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_6 ,\NLW_GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_O_UNCONNECTED [0]}), + .S({\GEN_INDET_BTT.lsig_byte_cntr[6]_i_3_n_0 ,\GEN_INDET_BTT.lsig_byte_cntr[6]_i_4_n_0 ,\GEN_INDET_BTT.lsig_byte_cntr[6]_i_5_n_0 ,\GEN_INDET_BTT.lsig_byte_cntr[6]_i_6_n_0 })); + FDRE #( + .INIT(1'b0)) + \GEN_INDET_BTT.lsig_byte_cntr_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(sig_m_valid_out_reg_1), + .D(\GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_7 ), + .Q(in[6]), + .R(\GEN_INDET_BTT.lsig_byte_cntr[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_INDET_BTT.lsig_byte_cntr_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(sig_m_valid_out_reg_1), + .D(\GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_6 ), + .Q(in[7]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_INDET_BTT.lsig_byte_cntr_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(sig_m_valid_out_reg_1), + .D(\GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_5 ), + .Q(in[8]), + .R(SR)); + LUT5 #( + .INIT(32'hF7778000)) + \GEN_INDET_BTT.lsig_end_of_cmd_reg_i_1 + (.I0(sig_m_valid_out_reg_0), + .I1(sig_wdc2ibtt_tready), + .I2(sig_next_cmd_cmplt_reg), + .I3(sig_ibtt2wdc_tlast), + .I4(lsig_end_of_cmd_reg), + .O(\GEN_INDET_BTT.lsig_end_of_cmd_reg_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_INDET_BTT.lsig_end_of_cmd_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_INDET_BTT.lsig_end_of_cmd_reg_i_1_n_0 ), + .Q(lsig_end_of_cmd_reg), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \GEN_INDET_BTT.lsig_eop_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_m_valid_out_reg), + .Q(lsig_eop_reg), + .R(sig_stream_rst)); + (* SOFT_HLUTNM = "soft_lutpair246" *) + LUT2 #( + .INIT(4'h2)) + \INFERRED_GEN.data_reg[5][22]_srl6_i_1 + (.I0(lsig_eop_reg), + .I1(sig_next_calc_error_reg), + .O(in[15])); + LUT5 #( + .INIT(32'hD9996664)) + \sig_addr_posted_cntr[0]_i_1 + (.I0(sig_last_mmap_dbeat_reg), + .I1(sig_posted_to_axi_reg), + .I2(sig_addr_posted_cntr[1]), + .I3(sig_addr_posted_cntr[2]), + .I4(sig_addr_posted_cntr[0]), + .O(\sig_addr_posted_cntr[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair244" *) + LUT5 #( + .INIT(32'hF0C2BCF0)) + \sig_addr_posted_cntr[1]_i_1 + (.I0(sig_addr_posted_cntr[2]), + .I1(sig_addr_posted_cntr[0]), + .I2(sig_addr_posted_cntr[1]), + .I3(sig_posted_to_axi_reg), + .I4(sig_last_mmap_dbeat_reg), + .O(\sig_addr_posted_cntr[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair244" *) + LUT5 #( + .INIT(32'hAAA8EAAA)) + \sig_addr_posted_cntr[2]_i_1 + (.I0(sig_addr_posted_cntr[2]), + .I1(sig_addr_posted_cntr[0]), + .I2(sig_addr_posted_cntr[1]), + .I3(sig_posted_to_axi_reg), + .I4(sig_last_mmap_dbeat_reg), + .O(\sig_addr_posted_cntr[2]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_addr_posted_cntr_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\sig_addr_posted_cntr[0]_i_1_n_0 ), + .Q(sig_addr_posted_cntr[0]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_addr_posted_cntr_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\sig_addr_posted_cntr[1]_i_1_n_0 ), + .Q(sig_addr_posted_cntr[1]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_addr_posted_cntr_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\sig_addr_posted_cntr[2]_i_1_n_0 ), + .Q(sig_addr_posted_cntr[2]), + .R(sig_stream_rst)); + LUT5 #( + .INIT(32'hC0C000A0)) + sig_data2wsc_calc_err_i_1 + (.I0(in[0]), + .I1(sig_next_calc_error_reg), + .I2(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I3(sig_wr_fifo), + .I4(sig_set_push2wsc), + .O(sig_data2wsc_calc_err_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + sig_data2wsc_calc_err_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_data2wsc_calc_err_i_1_n_0), + .Q(in[0]), + .R(1'b0)); + LUT5 #( + .INIT(32'hC0C000A0)) + sig_data2wsc_cmd_cmplt_i_1 + (.I0(in[1]), + .I1(sig_next_cmd_cmplt_reg), + .I2(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I3(sig_wr_fifo), + .I4(sig_set_push2wsc), + .O(sig_data2wsc_cmd_cmplt_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + sig_data2wsc_cmd_cmplt_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_data2wsc_cmd_cmplt_i_1_n_0), + .Q(in[1]), + .R(1'b0)); + LUT2 #( + .INIT(4'hB)) + \sig_data_reg_out[67]_i_1 + (.I0(sig_wdc2ibtt_tready), + .I1(out), + .O(E)); + (* SOFT_HLUTNM = "soft_lutpair245" *) + LUT4 #( + .INIT(16'hFFFE)) + \sig_dbeat_cntr[4]_i_2 + (.I0(sig_dbeat_cntr_reg__0[2]), + .I1(sig_dbeat_cntr_reg__0[0]), + .I2(sig_dbeat_cntr_reg__0[1]), + .I3(sig_dbeat_cntr_reg__0[3]), + .O(\sig_dbeat_cntr[4]_i_2_n_0 )); + LUT5 #( + .INIT(32'hFFFFFFFE)) + \sig_dbeat_cntr[5]_i_2 + (.I0(sig_dbeat_cntr_reg__0[3]), + .I1(sig_dbeat_cntr_reg__0[1]), + .I2(sig_dbeat_cntr_reg__0[0]), + .I3(sig_dbeat_cntr_reg__0[2]), + .I4(sig_dbeat_cntr_reg__0[4]), + .O(\sig_dbeat_cntr[5]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \sig_dbeat_cntr[7]_i_3__0 + (.I0(sig_dbeat_cntr_reg__0[4]), + .I1(sig_dbeat_cntr_reg__0[2]), + .I2(sig_dbeat_cntr_reg__0[0]), + .I3(sig_dbeat_cntr_reg__0[1]), + .I4(sig_dbeat_cntr_reg__0[3]), + .I5(sig_dbeat_cntr_reg__0[5]), + .O(\sig_dbeat_cntr[7]_i_3__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \sig_dbeat_cntr_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_16 ), + .D(p_0_in__0[0]), + .Q(sig_dbeat_cntr_reg__0[0]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_dbeat_cntr_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_16 ), + .D(p_0_in__0[1]), + .Q(sig_dbeat_cntr_reg__0[1]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_dbeat_cntr_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_16 ), + .D(p_0_in__0[2]), + .Q(sig_dbeat_cntr_reg__0[2]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_dbeat_cntr_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_16 ), + .D(p_0_in__0[3]), + .Q(sig_dbeat_cntr_reg__0[3]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_dbeat_cntr_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_16 ), + .D(p_0_in__0[4]), + .Q(sig_dbeat_cntr_reg__0[4]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_dbeat_cntr_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_16 ), + .D(p_0_in__0[5]), + .Q(sig_dbeat_cntr_reg__0[5]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_dbeat_cntr_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_16 ), + .D(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_8 ), + .Q(sig_dbeat_cntr_reg__0[6]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \sig_dbeat_cntr_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_16 ), + .D(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_7 ), + .Q(sig_dbeat_cntr_reg__0[7]), + .R(sig_stream_rst)); + FDSE #( + .INIT(1'b0)) + sig_dqual_reg_empty_reg + (.C(m_axi_s2mm_aclk), + .CE(sig_push_dqual_reg), + .D(1'b0), + .Q(sig_dqual_reg_empty), + .S(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_5 )); + FDRE #( + .INIT(1'b0)) + sig_dqual_reg_full_reg + (.C(m_axi_s2mm_aclk), + .CE(sig_push_dqual_reg), + .D(sig_push_dqual_reg), + .Q(sig_dqual_reg_full), + .R(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_5 )); + LUT5 #( + .INIT(32'h8888888A)) + sig_halt_cmplt_i_3 + (.I0(sig_halt_reg_dly3), + .I1(sig_next_calc_error_reg), + .I2(sig_addr_posted_cntr[1]), + .I3(sig_addr_posted_cntr[0]), + .I4(sig_addr_posted_cntr[2]), + .O(sig_data2rst_stop_cmplt)); + FDRE #( + .INIT(1'b0)) + sig_halt_reg_dly1_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_halt_reg), + .Q(sig_halt_reg_dly1), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + sig_halt_reg_dly2_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_halt_reg_dly1), + .Q(sig_halt_reg_dly2), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + sig_halt_reg_dly3_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_halt_reg_dly2), + .Q(sig_halt_reg_dly3), + .R(sig_stream_rst)); + LUT6 #( + .INIT(64'h0000001000000000)) + sig_last_dbeat_i_2__0 + (.I0(sig_dbeat_cntr_reg__0[2]), + .I1(sig_dbeat_cntr_reg__0[3]), + .I2(sig_dbeat_cntr_reg__0[0]), + .I3(sig_dbeat_cntr_reg__0[1]), + .I4(sig_last_reg_out_i_4_n_0), + .I5(sig_good_mmap_dbeat12_out__0), + .O(sig_first_dbeat1__0)); + LUT6 #( + .INIT(64'hFFFFFFFE00000000)) + sig_last_dbeat_i_4 + (.I0(sig_last_reg_out_i_4_n_0), + .I1(sig_dbeat_cntr_reg__0[1]), + .I2(sig_dbeat_cntr_reg__0[0]), + .I3(sig_dbeat_cntr_reg__0[3]), + .I4(sig_dbeat_cntr_reg__0[2]), + .I5(sig_good_mmap_dbeat12_out__0), + .O(sig_single_dbeat)); + FDRE #( + .INIT(1'b0)) + sig_last_dbeat_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_2 ), + .Q(sig_last_dbeat_reg_n_0), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair247" *) + LUT3 #( + .INIT(8'h80)) + sig_last_mmap_dbeat_reg_i_1__0 + (.I0(sig_dqual_reg_full), + .I1(sig_dbeat_cntr_eq_0__2), + .I2(sig_good_mmap_dbeat12_out__0), + .O(sig_last_mmap_dbeat)); + FDRE #( + .INIT(1'b0)) + sig_last_mmap_dbeat_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_last_mmap_dbeat), + .Q(sig_last_mmap_dbeat_reg), + .R(sig_stream_rst)); + (* SOFT_HLUTNM = "soft_lutpair245" *) + LUT5 #( + .INIT(32'h00000001)) + sig_last_reg_out_i_3 + (.I0(sig_last_reg_out_i_4_n_0), + .I1(sig_dbeat_cntr_reg__0[1]), + .I2(sig_dbeat_cntr_reg__0[0]), + .I3(sig_dbeat_cntr_reg__0[3]), + .I4(sig_dbeat_cntr_reg__0[2]), + .O(sig_dbeat_cntr_eq_0__2)); + LUT4 #( + .INIT(16'hFFFE)) + sig_last_reg_out_i_4 + (.I0(sig_dbeat_cntr_reg__0[7]), + .I1(sig_dbeat_cntr_reg__0[6]), + .I2(sig_dbeat_cntr_reg__0[4]), + .I3(sig_dbeat_cntr_reg__0[5]), + .O(sig_last_reg_out_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + sig_ld_new_cmd_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_4 ), + .Q(sig_ld_new_cmd_reg), + .R(1'b0)); + LUT5 #( + .INIT(32'h0000A800)) + sig_m_valid_dup_i_2__0 + (.I0(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_20 ), + .I1(sig_m_valid_out_reg_0), + .I2(sig_halt_reg), + .I3(sig_dqual_reg_full), + .I4(sig_next_calc_error_reg), + .O(sig_data2skid_wvalid)); + FDRE #( + .INIT(1'b0)) + sig_next_calc_error_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(sig_push_dqual_reg), + .D(sig_cmd_fifo_data_out[35]), + .Q(sig_next_calc_error_reg), + .R(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_5 )); + FDRE #( + .INIT(1'b0)) + sig_next_cmd_cmplt_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(sig_push_dqual_reg), + .D(sig_cmd_fifo_data_out[34]), + .Q(sig_next_cmd_cmplt_reg), + .R(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_5 )); + FDRE #( + .INIT(1'b0)) + sig_next_sequential_reg_reg + (.C(m_axi_s2mm_aclk), + .CE(sig_push_dqual_reg), + .D(sig_cmd_fifo_data_out[33]), + .Q(sig_next_sequential_reg), + .R(\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_5 )); + (* SOFT_HLUTNM = "soft_lutpair246" *) + LUT4 #( + .INIT(16'h0080)) + sig_push_err2wsc_i_1 + (.I0(sig_ld_new_cmd_reg), + .I1(sig_next_calc_error_reg), + .I2(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I3(sig_push_err2wsc), + .O(sig_push_err2wsc_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + sig_push_err2wsc_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_push_err2wsc_i_1_n_0), + .Q(sig_push_err2wsc), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair247" *) + LUT3 #( + .INIT(8'hEA)) + sig_push_to_wsc_i_2 + (.I0(sig_push_err2wsc), + .I1(sig_good_mmap_dbeat12_out__0), + .I2(sig_dbeat_cntr_eq_0__2), + .O(sig_set_push2wsc)); + FDRE #( + .INIT(1'b0)) + sig_push_to_wsc_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0), + .Q(sig_data2wsc_valid), + .R(1'b0)); +endmodule + +(* C_DLYTMR_RESOLUTION = "125" *) (* C_DYNAMIC_RESOLUTION = "1" *) (* C_ENABLE_DEBUG_ALL = "0" *) +(* C_ENABLE_DEBUG_INFO_0 = "0" *) (* C_ENABLE_DEBUG_INFO_1 = "0" *) (* C_ENABLE_DEBUG_INFO_10 = "0" *) +(* C_ENABLE_DEBUG_INFO_11 = "0" *) (* C_ENABLE_DEBUG_INFO_12 = "0" *) (* C_ENABLE_DEBUG_INFO_13 = "0" *) +(* C_ENABLE_DEBUG_INFO_14 = "1" *) (* C_ENABLE_DEBUG_INFO_15 = "1" *) (* C_ENABLE_DEBUG_INFO_2 = "0" *) +(* C_ENABLE_DEBUG_INFO_3 = "0" *) (* C_ENABLE_DEBUG_INFO_4 = "0" *) (* C_ENABLE_DEBUG_INFO_5 = "0" *) +(* C_ENABLE_DEBUG_INFO_6 = "1" *) (* C_ENABLE_DEBUG_INFO_7 = "1" *) (* C_ENABLE_DEBUG_INFO_8 = "0" *) +(* C_ENABLE_DEBUG_INFO_9 = "0" *) (* C_ENABLE_VIDPRMTR_READS = "1" *) (* C_FAMILY = "zynq" *) +(* C_FLUSH_ON_FSYNC = "1" *) (* C_INCLUDE_INTERNAL_GENLOCK = "1" *) (* C_INCLUDE_MM2S = "1" *) +(* C_INCLUDE_MM2S_DRE = "0" *) (* C_INCLUDE_MM2S_SF = "0" *) (* C_INCLUDE_S2MM = "1" *) +(* C_INCLUDE_S2MM_DRE = "0" *) (* C_INCLUDE_S2MM_SF = "1" *) (* C_INCLUDE_SG = "0" *) +(* C_INSTANCE = "axi_vdma" *) (* C_MM2S_GENLOCK_MODE = "0" *) (* C_MM2S_GENLOCK_NUM_MASTERS = "1" *) +(* C_MM2S_GENLOCK_REPEAT_EN = "0" *) (* C_MM2S_LINEBUFFER_DEPTH = "2048" *) (* C_MM2S_LINEBUFFER_THRESH = "4" *) +(* C_MM2S_MAX_BURST_LENGTH = "32" *) (* C_MM2S_SOF_ENABLE = "1" *) (* C_M_AXIS_MM2S_TDATA_WIDTH = "32" *) +(* C_M_AXIS_MM2S_TUSER_BITS = "1" *) (* C_M_AXI_MM2S_ADDR_WIDTH = "32" *) (* C_M_AXI_MM2S_DATA_WIDTH = "64" *) +(* C_M_AXI_S2MM_ADDR_WIDTH = "32" *) (* C_M_AXI_S2MM_DATA_WIDTH = "64" *) (* C_M_AXI_SG_ADDR_WIDTH = "32" *) +(* C_M_AXI_SG_DATA_WIDTH = "32" *) (* C_NUM_FSTORES = "3" *) (* C_PRMRY_IS_ACLK_ASYNC = "1" *) +(* C_S2MM_GENLOCK_MODE = "2" *) (* C_S2MM_GENLOCK_NUM_MASTERS = "1" *) (* C_S2MM_GENLOCK_REPEAT_EN = "1" *) +(* C_S2MM_LINEBUFFER_DEPTH = "2048" *) (* C_S2MM_LINEBUFFER_THRESH = "4" *) (* C_S2MM_MAX_BURST_LENGTH = "32" *) +(* C_S2MM_SOF_ENABLE = "1" *) (* C_SELECT_XPM = "0" *) (* C_S_AXIS_S2MM_TDATA_WIDTH = "8" *) +(* C_S_AXIS_S2MM_TUSER_BITS = "1" *) (* C_S_AXI_LITE_ADDR_WIDTH = "9" *) (* C_S_AXI_LITE_DATA_WIDTH = "32" *) +(* C_USE_FSYNC = "1" *) (* C_USE_MM2S_FSYNC = "0" *) (* C_USE_S2MM_FSYNC = "2" *) +(* ORIG_REF_NAME = "axi_vdma" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_group = "LOGICORE" *) +(* iptype = "PERIPHERAL" *) (* run_ngcbuild = "TRUE" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma + (s_axi_lite_aclk, + m_axi_sg_aclk, + m_axi_mm2s_aclk, + m_axis_mm2s_aclk, + m_axi_s2mm_aclk, + s_axis_s2mm_aclk, + axi_resetn, + s_axi_lite_awvalid, + s_axi_lite_awready, + s_axi_lite_awaddr, + s_axi_lite_wvalid, + s_axi_lite_wready, + s_axi_lite_wdata, + s_axi_lite_bresp, + s_axi_lite_bvalid, + s_axi_lite_bready, + s_axi_lite_arvalid, + s_axi_lite_arready, + s_axi_lite_araddr, + s_axi_lite_rvalid, + s_axi_lite_rready, + s_axi_lite_rdata, + s_axi_lite_rresp, + mm2s_fsync, + mm2s_frame_ptr_in, + mm2s_frame_ptr_out, + s2mm_fsync, + s2mm_frame_ptr_in, + s2mm_frame_ptr_out, + mm2s_buffer_empty, + mm2s_buffer_almost_empty, + s2mm_buffer_full, + s2mm_buffer_almost_full, + mm2s_fsync_out, + s2mm_fsync_out, + mm2s_prmtr_update, + s2mm_prmtr_update, + m_axi_sg_araddr, + m_axi_sg_arlen, + m_axi_sg_arsize, + m_axi_sg_arburst, + m_axi_sg_arprot, + m_axi_sg_arcache, + m_axi_sg_arvalid, + m_axi_sg_arready, + m_axi_sg_rdata, + m_axi_sg_rresp, + m_axi_sg_rlast, + m_axi_sg_rvalid, + m_axi_sg_rready, + m_axi_mm2s_araddr, + m_axi_mm2s_arlen, + m_axi_mm2s_arsize, + m_axi_mm2s_arburst, + m_axi_mm2s_arprot, + m_axi_mm2s_arcache, + m_axi_mm2s_arvalid, + m_axi_mm2s_arready, + m_axi_mm2s_rdata, + m_axi_mm2s_rresp, + m_axi_mm2s_rlast, + m_axi_mm2s_rvalid, + m_axi_mm2s_rready, + mm2s_prmry_reset_out_n, + m_axis_mm2s_tdata, + m_axis_mm2s_tkeep, + m_axis_mm2s_tuser, + m_axis_mm2s_tvalid, + m_axis_mm2s_tready, + m_axis_mm2s_tlast, + m_axi_s2mm_awaddr, + m_axi_s2mm_awlen, + m_axi_s2mm_awsize, + m_axi_s2mm_awburst, + m_axi_s2mm_awprot, + m_axi_s2mm_awcache, + m_axi_s2mm_awvalid, + m_axi_s2mm_awready, + m_axi_s2mm_wdata, + m_axi_s2mm_wstrb, + m_axi_s2mm_wlast, + m_axi_s2mm_wvalid, + m_axi_s2mm_wready, + m_axi_s2mm_bresp, + m_axi_s2mm_bvalid, + m_axi_s2mm_bready, + s2mm_prmry_reset_out_n, + s_axis_s2mm_tdata, + s_axis_s2mm_tkeep, + s_axis_s2mm_tuser, + s_axis_s2mm_tvalid, + s_axis_s2mm_tready, + s_axis_s2mm_tlast, + mm2s_introut, + s2mm_introut, + axi_vdma_tstvec); + input s_axi_lite_aclk; + input m_axi_sg_aclk; + input m_axi_mm2s_aclk; + input m_axis_mm2s_aclk; + input m_axi_s2mm_aclk; + input s_axis_s2mm_aclk; + input axi_resetn; + input s_axi_lite_awvalid; + output s_axi_lite_awready; + input [8:0]s_axi_lite_awaddr; + input s_axi_lite_wvalid; + output s_axi_lite_wready; input [31:0]s_axi_lite_wdata; output [1:0]s_axi_lite_bresp; output s_axi_lite_bvalid; - input s_axi_lite_bready; + input s_axi_lite_bready; + input s_axi_lite_arvalid; + output s_axi_lite_arready; + input [8:0]s_axi_lite_araddr; + output s_axi_lite_rvalid; + input s_axi_lite_rready; + output [31:0]s_axi_lite_rdata; + output [1:0]s_axi_lite_rresp; + input mm2s_fsync; + input [5:0]mm2s_frame_ptr_in; + output [5:0]mm2s_frame_ptr_out; + input s2mm_fsync; + input [5:0]s2mm_frame_ptr_in; + output [5:0]s2mm_frame_ptr_out; + output mm2s_buffer_empty; + output mm2s_buffer_almost_empty; + output s2mm_buffer_full; + output s2mm_buffer_almost_full; + output mm2s_fsync_out; + output s2mm_fsync_out; + output mm2s_prmtr_update; + output s2mm_prmtr_update; + output [31:0]m_axi_sg_araddr; + output [7:0]m_axi_sg_arlen; + output [2:0]m_axi_sg_arsize; + output [1:0]m_axi_sg_arburst; + output [2:0]m_axi_sg_arprot; + output [3:0]m_axi_sg_arcache; + output m_axi_sg_arvalid; + input m_axi_sg_arready; + input [31:0]m_axi_sg_rdata; + input [1:0]m_axi_sg_rresp; + input m_axi_sg_rlast; + input m_axi_sg_rvalid; + output m_axi_sg_rready; + output [31:0]m_axi_mm2s_araddr; + output [7:0]m_axi_mm2s_arlen; + output [2:0]m_axi_mm2s_arsize; + output [1:0]m_axi_mm2s_arburst; + output [2:0]m_axi_mm2s_arprot; + output [3:0]m_axi_mm2s_arcache; + output m_axi_mm2s_arvalid; + input m_axi_mm2s_arready; + input [63:0]m_axi_mm2s_rdata; + input [1:0]m_axi_mm2s_rresp; + input m_axi_mm2s_rlast; + input m_axi_mm2s_rvalid; + output m_axi_mm2s_rready; + output mm2s_prmry_reset_out_n; + output [31:0]m_axis_mm2s_tdata; + output [3:0]m_axis_mm2s_tkeep; + output [0:0]m_axis_mm2s_tuser; + output m_axis_mm2s_tvalid; + input m_axis_mm2s_tready; + output m_axis_mm2s_tlast; + output [31:0]m_axi_s2mm_awaddr; + output [7:0]m_axi_s2mm_awlen; + output [2:0]m_axi_s2mm_awsize; + output [1:0]m_axi_s2mm_awburst; + output [2:0]m_axi_s2mm_awprot; + output [3:0]m_axi_s2mm_awcache; + output m_axi_s2mm_awvalid; + input m_axi_s2mm_awready; + output [63:0]m_axi_s2mm_wdata; + output [7:0]m_axi_s2mm_wstrb; + output m_axi_s2mm_wlast; + output m_axi_s2mm_wvalid; + input m_axi_s2mm_wready; + input [1:0]m_axi_s2mm_bresp; + input m_axi_s2mm_bvalid; + output m_axi_s2mm_bready; + output s2mm_prmry_reset_out_n; + input [7:0]s_axis_s2mm_tdata; + input [0:0]s_axis_s2mm_tkeep; + input [0:0]s_axis_s2mm_tuser; + input s_axis_s2mm_tvalid; + output s_axis_s2mm_tready; + input s_axis_s2mm_tlast; + output mm2s_introut; + output s2mm_introut; + output [63:0]axi_vdma_tstvec; + + wire \ ; + wire \ ; + wire AXI_LITE_REG_INTERFACE_I_n_100; + wire AXI_LITE_REG_INTERFACE_I_n_101; + wire AXI_LITE_REG_INTERFACE_I_n_102; + wire AXI_LITE_REG_INTERFACE_I_n_103; + wire AXI_LITE_REG_INTERFACE_I_n_104; + wire AXI_LITE_REG_INTERFACE_I_n_105; + wire AXI_LITE_REG_INTERFACE_I_n_106; + wire AXI_LITE_REG_INTERFACE_I_n_107; + wire AXI_LITE_REG_INTERFACE_I_n_108; + wire AXI_LITE_REG_INTERFACE_I_n_109; + wire AXI_LITE_REG_INTERFACE_I_n_110; + wire AXI_LITE_REG_INTERFACE_I_n_111; + wire AXI_LITE_REG_INTERFACE_I_n_112; + wire AXI_LITE_REG_INTERFACE_I_n_113; + wire AXI_LITE_REG_INTERFACE_I_n_114; + wire AXI_LITE_REG_INTERFACE_I_n_115; + wire AXI_LITE_REG_INTERFACE_I_n_128; + wire AXI_LITE_REG_INTERFACE_I_n_129; + wire AXI_LITE_REG_INTERFACE_I_n_130; + wire AXI_LITE_REG_INTERFACE_I_n_131; + wire AXI_LITE_REG_INTERFACE_I_n_132; + wire AXI_LITE_REG_INTERFACE_I_n_133; + wire AXI_LITE_REG_INTERFACE_I_n_134; + wire AXI_LITE_REG_INTERFACE_I_n_135; + wire AXI_LITE_REG_INTERFACE_I_n_136; + wire AXI_LITE_REG_INTERFACE_I_n_137; + wire AXI_LITE_REG_INTERFACE_I_n_138; + wire AXI_LITE_REG_INTERFACE_I_n_139; + wire AXI_LITE_REG_INTERFACE_I_n_140; + wire AXI_LITE_REG_INTERFACE_I_n_141; + wire AXI_LITE_REG_INTERFACE_I_n_142; + wire AXI_LITE_REG_INTERFACE_I_n_143; + wire AXI_LITE_REG_INTERFACE_I_n_144; + wire AXI_LITE_REG_INTERFACE_I_n_145; + wire AXI_LITE_REG_INTERFACE_I_n_146; + wire AXI_LITE_REG_INTERFACE_I_n_147; + wire AXI_LITE_REG_INTERFACE_I_n_148; + wire AXI_LITE_REG_INTERFACE_I_n_149; + wire AXI_LITE_REG_INTERFACE_I_n_150; + wire AXI_LITE_REG_INTERFACE_I_n_151; + wire AXI_LITE_REG_INTERFACE_I_n_152; + wire AXI_LITE_REG_INTERFACE_I_n_153; + wire AXI_LITE_REG_INTERFACE_I_n_154; + wire AXI_LITE_REG_INTERFACE_I_n_155; + wire AXI_LITE_REG_INTERFACE_I_n_156; + wire AXI_LITE_REG_INTERFACE_I_n_157; + wire AXI_LITE_REG_INTERFACE_I_n_158; + wire AXI_LITE_REG_INTERFACE_I_n_159; + wire AXI_LITE_REG_INTERFACE_I_n_160; + wire AXI_LITE_REG_INTERFACE_I_n_161; + wire AXI_LITE_REG_INTERFACE_I_n_162; + wire AXI_LITE_REG_INTERFACE_I_n_163; + wire AXI_LITE_REG_INTERFACE_I_n_164; + wire AXI_LITE_REG_INTERFACE_I_n_165; + wire AXI_LITE_REG_INTERFACE_I_n_166; + wire AXI_LITE_REG_INTERFACE_I_n_167; + wire AXI_LITE_REG_INTERFACE_I_n_168; + wire AXI_LITE_REG_INTERFACE_I_n_169; + wire AXI_LITE_REG_INTERFACE_I_n_170; + wire AXI_LITE_REG_INTERFACE_I_n_171; + wire AXI_LITE_REG_INTERFACE_I_n_81; + wire AXI_LITE_REG_INTERFACE_I_n_82; + wire AXI_LITE_REG_INTERFACE_I_n_83; + wire AXI_LITE_REG_INTERFACE_I_n_84; + wire AXI_LITE_REG_INTERFACE_I_n_85; + wire AXI_LITE_REG_INTERFACE_I_n_86; + wire AXI_LITE_REG_INTERFACE_I_n_87; + wire AXI_LITE_REG_INTERFACE_I_n_88; + wire AXI_LITE_REG_INTERFACE_I_n_89; + wire AXI_LITE_REG_INTERFACE_I_n_90; + wire AXI_LITE_REG_INTERFACE_I_n_91; + wire AXI_LITE_REG_INTERFACE_I_n_92; + wire AXI_LITE_REG_INTERFACE_I_n_93; + wire AXI_LITE_REG_INTERFACE_I_n_94; + wire AXI_LITE_REG_INTERFACE_I_n_95; + wire AXI_LITE_REG_INTERFACE_I_n_96; + wire AXI_LITE_REG_INTERFACE_I_n_97; + wire AXI_LITE_REG_INTERFACE_I_n_98; + wire AXI_LITE_REG_INTERFACE_I_n_99; + wire \GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/p_in_d1_cdc_from ; + wire \GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/p_in_d1_cdc_from_13 ; + wire \GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/prmry_in_xored ; + wire \GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/prmry_in_xored_7 ; + wire \GEN_CDC_FOR_ASYNC.PRMTR_UPDT_CDC_I/scndry_reset2 ; + wire \GEN_CDC_FOR_ASYNC.SOF_CDC_I/p_in_d1_cdc_from ; + wire \GEN_CDC_FOR_ASYNC.SOF_CDC_I/p_in_d1_cdc_from_14 ; + wire \GEN_CDC_FOR_ASYNC.SOF_CDC_I/prmry_in_xored ; + wire \GEN_CDC_FOR_ASYNC.SOF_CDC_I/prmry_in_xored_12 ; + wire \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I/prmry_reset2 ; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/p_5_out ; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/p_8_out ; + wire \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/lsig_0ffset_cntr ; + wire \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_rd_empty ; + wire \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/sig_rst2all_stop_request ; + wire \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.MM2S_INTRPT_CROSSING_I/prmry_reset2 ; + wire \GEN_RESET_FOR_MM2S.RESET_I/halt_reset ; + wire \GEN_RESET_FOR_MM2S.RESET_I/s_soft_reset_i0 ; + wire \GEN_RESET_FOR_S2MM.RESET_I/halt_i0 ; + wire \GEN_RESET_FOR_S2MM.RESET_I/halt_reset ; + wire \GEN_RESET_FOR_S2MM.RESET_I/run_stop_d1 ; + wire \GEN_RESET_FOR_S2MM.RESET_I/s_soft_reset_i0 ; + wire \GEN_RESET_FOR_S2MM.RESET_I/soft_reset_d1 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF/p_in_d1_cdc_from ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF/prmry_in_xored ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF/prmry_reset2 ; + wire \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_0 ; + wire \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_1 ; + wire \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_2 ; + wire \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_3 ; + wire \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_4 ; + wire \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_5 ; + wire \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_n_0 ; + wire \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_n_1 ; + wire \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_n_2 ; + wire \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_n_3 ; + wire \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_n_5 ; + wire [2:0]\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_0_out ; + wire [2:0]\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_11_out ; + wire [8:0]\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_byte_cntr ; + wire \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_dre2ibtt_eop_reg ; + wire \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_dre2ibtt_tlast_reg ; + wire \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_rd_empty ; + wire \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/sig_rst2all_stop_request ; + wire \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.S2MM_INTRPT_CROSSING_I/prmry_reset2 ; + wire \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.S2MM_INTRPT_CROSSING_I/scndry_reset2 ; + wire \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_31 ; + wire \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_32 ; + wire \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_33 ; + wire \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_34 ; + wire \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_35 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_3 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_6 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_7 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_8 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_217 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_218 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_219 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_220 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_221 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_222 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_223 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_224 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_225 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_226 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_227 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_228 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_231 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_54 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_55 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_56 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_57 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_58 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_62 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_63 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_65 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_67 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_68 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_69 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_70 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_71 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_72 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_73 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_74 ; + wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_75 ; + wire \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.GEN_FOR_ASYNC_FLUSH_SOF.S2MM_PRM_UPDT_CDC_I_n_1 ; + wire \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.GEN_FOR_ASYNC_FLUSH_SOF.SOF_LATE_CDC_I_n_1 ; + wire \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.GEN_FOR_ASYNC_FLUSH_SOF.SOF_LATE_CDC_I_n_2 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_n_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg_n_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_10_n_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_11_n_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_12_n_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_13_n_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_4_n_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_8_n_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_9_n_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_3_n_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_4_n_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_5_n_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_6_n_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_3_n_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_4_n_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_5_n_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_6_n_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]_i_7_n_1 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]_i_7_n_2 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]_i_7_n_3 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[4]_i_2_n_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[4]_i_2_n_1 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[4]_i_2_n_2 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[4]_i_2_n_3 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[8]_i_2_n_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[8]_i_2_n_1 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[8]_i_2_n_2 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[8]_i_2_n_3 ; + wire \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_3 ; + wire \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4 ; + wire \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_5 ; + wire \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_8 ; + wire \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_9 ; + wire \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_15 ; + wire \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_16 ; + wire \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_17 ; + wire \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_53 ; + wire \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_54 ; + wire \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_56 ; + wire \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_57 ; + wire \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_58 ; + wire \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_59 ; + wire \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_60 ; + wire \GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I_n_16 ; + wire \GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I_n_17 ; + wire \GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I_n_20 ; + wire \GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I_n_21 ; + wire \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_59 ; + wire \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_60 ; + wire \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_61 ; + wire \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_62 ; + wire \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_63 ; + wire \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_64 ; + wire \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_65 ; + wire \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_66 ; + wire \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_67 ; + wire \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_68 ; + wire \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_71 ; + wire \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_74 ; + wire \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_75 ; + wire \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_76 ; + wire \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_77 ; + wire \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_78 ; + wire \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_79 ; + wire \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_80 ; + wire \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_81 ; + wire \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_82 ; + wire \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_87 ; + wire \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_88 ; + wire \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_92 ; + wire \GEN_SPRT_FOR_S2MM.S2MM_VID_CDC_I_n_5 ; + wire I_AXI_DMA_INTRPT_n_39; + wire I_AXI_DMA_INTRPT_n_40; + wire \I_CMDSTS/p_12_out ; + wire \I_CMDSTS/p_9_out ; + wire \I_CMDSTS/s_axis_cmd_tvalid0 ; + wire [0:0]\I_DMA_REGISTER/dmacr_i ; + wire \I_DMA_REGISTER/irqdelay_wren_i ; + wire \I_DMA_REGISTER/p_14_out ; + wire \I_DMA_REGISTER/p_15_out ; + wire \I_DMA_REGISTER/reset_counts ; + wire \I_DMA_REGISTER/reset_counts_11 ; + wire I_PRMRY_DATAMOVER_n_191; + wire I_PRMRY_DATAMOVER_n_22; + wire I_PRMRY_DATAMOVER_n_23; + wire I_PRMRY_DATAMOVER_n_28; + wire I_PRMRY_DATAMOVER_n_29; + wire I_PRMRY_DATAMOVER_n_30; + wire I_PRMRY_DATAMOVER_n_32; + wire I_PRMRY_DATAMOVER_n_34; + wire I_PRMRY_DATAMOVER_n_35; + wire I_PRMRY_DATAMOVER_n_36; + wire I_PRMRY_DATAMOVER_n_37; + wire I_PRMRY_DATAMOVER_n_38; + wire I_PRMRY_DATAMOVER_n_39; + wire I_RST_MODULE_n_16; + wire I_RST_MODULE_n_19; + wire I_RST_MODULE_n_22; + wire I_RST_MODULE_n_25; + wire I_RST_MODULE_n_26; + wire I_RST_MODULE_n_27; + wire I_RST_MODULE_n_28; + wire I_RST_MODULE_n_29; + wire I_RST_MODULE_n_30; + wire I_RST_MODULE_n_31; + wire I_RST_MODULE_n_32; + wire I_RST_MODULE_n_33; + wire \I_SM/GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF/prmry_reset2 ; + wire \I_SM/drop_fsync_d_pulse_gen_fsize_less_err_d1 ; + wire \I_SM/fsize_mismatch_err_s1 ; + wire \I_STS_MNGR/datamover_idle ; + wire \I_STS_MNGR/datamover_idle_3 ; + wire \VIDEO_REG_I/p_1_out ; + wire all_lines_xfred; + wire axi_resetn; + wire ch1_delay_cnt_en; + wire ch1_delay_zero; + wire ch2_delay_cnt_en; + wire ch2_delay_zero; + wire ch2_irqthresh_decr_mask_sig; + wire cmnd_wr; + wire cmnd_wr_5; + wire [15:3]crnt_hsize; + wire d_tready_before_fsync; + wire d_tready_before_fsync_clr_flag1; + wire d_tready_sof_late; + wire delay_s2mm_fsync_core_till_mmap_done_flag; + wire [31:0]dm2linebuf_mm2s_tdata; + wire dm2linebuf_mm2s_tlast; + wire dm2linebuf_s2mm_tready; + wire dma_err; + wire dma_err_2; + wire [3:0]dma_irq_mask_i; + wire fifo_empty_i; + wire fifo_rden; + wire initial_frame; + wire initial_frame_0; + wire [7:0]linebuf2dm_s2mm_tdata; + wire linebuf2dm_s2mm_tlast; + wire m_axi_mm2s_aclk; + wire [31:0]m_axi_mm2s_araddr; + wire [0:0]\^m_axi_mm2s_arburst ; + wire [4:0]\^m_axi_mm2s_arlen ; + wire m_axi_mm2s_arready; + wire [1:0]\^m_axi_mm2s_arsize ; + wire m_axi_mm2s_arvalid; + wire [63:0]m_axi_mm2s_rdata; + wire m_axi_mm2s_rlast; + wire m_axi_mm2s_rready; + wire [1:0]m_axi_mm2s_rresp; + wire m_axi_mm2s_rvalid; + wire m_axi_s2mm_aclk; + wire [31:0]m_axi_s2mm_awaddr; + wire [0:0]\^m_axi_s2mm_awburst ; + wire [5:0]\^m_axi_s2mm_awlen ; + wire m_axi_s2mm_awready; + wire [1:0]\^m_axi_s2mm_awsize ; + wire m_axi_s2mm_awvalid; + wire m_axi_s2mm_bready; + wire [1:0]m_axi_s2mm_bresp; + wire m_axi_s2mm_bvalid; + wire [63:0]m_axi_s2mm_wdata; + wire m_axi_s2mm_wlast; + wire m_axi_s2mm_wready; + wire m_axi_s2mm_wvalid; + wire m_axis_mm2s_aclk; + wire [31:0]m_axis_mm2s_tdata; + wire m_axis_mm2s_tlast; + wire m_axis_mm2s_tready; + wire [0:0]m_axis_mm2s_tuser; + wire m_axis_mm2s_tvalid; + wire [8:8]m_axis_s2mm_sts_tdata; + wire m_axis_s2mm_sts_tready; + wire mask_fsync_out_i; + wire mask_fsync_out_i_8; + wire [12:1]minusOp; + wire [3:2]mm2s_axi2ip_rdaddr; + wire [25:0]mm2s_axi2ip_wrce; + wire [31:0]mm2s_axi2ip_wrdata; + wire mm2s_axis_resetn; + wire mm2s_dly_irq_set; + wire mm2s_dm_prmry_resetn; + wire [5:0]mm2s_frame_ptr_in; + wire [5:0]mm2s_frame_ptr_out; + wire mm2s_halt; + wire mm2s_halt_cmplt; + wire mm2s_introut; + wire mm2s_ioc_irq_set; + wire [7:0]mm2s_irqdelay_status; + wire [7:0]mm2s_irqthresh_status; + wire mm2s_prmry_resetn; + wire [15:0]mm2s_reg_module_hsize; + wire [15:0]mm2s_reg_module_stride; + wire [31:0]\mm2s_reg_module_strt_addr[0] ; + wire [31:0]\mm2s_reg_module_strt_addr[1] ; + wire [31:0]\mm2s_reg_module_strt_addr[2] ; + wire [12:0]mm2s_reg_module_vsize; + wire [1:1]num_fstore_minus1; + wire p_0_out; + wire p_10_out; + wire p_11_out; + wire p_13_out; + wire p_15_out; + wire p_17_out; + wire p_19_in; + wire [12:0]p_1_in; + wire p_1_out; + wire p_24_out; + wire p_2_out; + wire p_2_out_1; + wire [4:0]p_31_out; + wire [4:0]p_33_out; + wire p_36_out; + wire p_37_out; + wire p_39_out; + wire [2:0]p_44_out; + wire p_45_out; + wire p_46_out; + wire p_47_out; + wire [12:0]p_49_out; + wire p_4_out; + wire p_4_out_10; + wire p_4_out_6; + wire p_50_out; + wire p_56_out; + wire [63:0]p_57_out; + wire p_58_out; + wire p_67_out; + wire p_6_out; + wire p_70_out; + wire [31:0]p_71_out; + wire p_77_out; + wire p_78_out; + wire [4:0]p_79_out; + wire p_7_out; + wire [4:0]p_80_out; + wire [31:0]p_81_out; + wire [4:0]p_82_out; + wire [4:0]p_83_out; + wire [31:0]p_84_out; + wire p_92_out; + wire [7:0]p_94_out; + wire p_96_out; + wire p_in_d1_cdc_from; + wire prmry_in_xored; + wire prmtr_update_complete; + wire prmtr_update_complete_4; + wire run_stop_reg; + wire [45:10]s2mm_axi2ip_wrce; + wire [31:0]s2mm_axi2ip_wrdata; + wire s2mm_axis_resetn; + wire s2mm_cdc2dmac_fsync; + wire [4:0]s2mm_chnl_current_frame; + wire [12:0]s2mm_crnt_vsize; + wire s2mm_dly_irq_set; + wire s2mm_dm_prmry_resetn; + wire s2mm_dma_interr_set_minus_frame_errors; + wire [31:0]s2mm_dmacr; + wire [0:0]s2mm_dmasr; + wire s2mm_dmasr_halted_s; + wire [4:0]s2mm_frame_number; + wire [5:0]s2mm_frame_ptr_in; + wire [5:0]s2mm_frame_ptr_out; + wire s2mm_fsize_less_err_flag_10; + wire s2mm_fsize_mismatch_err; + wire s2mm_fsize_more_or_sof_late; + wire s2mm_fsize_more_or_sof_late_s; + wire s2mm_fsync_core; + wire s2mm_fsync_out_i; + wire s2mm_fsync_out_m_i; + wire s2mm_ftchcmdsts_idle; + wire [4:0]s2mm_genlock_pair_frame; + wire s2mm_halt; + wire s2mm_halt_cmplt; + wire s2mm_introut; + wire s2mm_ioc_irq_set; + wire s2mm_ip2axi_introut; + wire [7:0]s2mm_irqdelay_status; + wire [7:0]s2mm_irqthresh_status; + wire s2mm_lsize_mismatch_err; + wire s2mm_lsize_more_mismatch_err; + wire [2:0]s2mm_m_frame_ptr_out; + wire s2mm_packet_sof; + wire s2mm_prmry_resetn; + wire [15:0]s2mm_reg_module_hsize; + wire [15:0]s2mm_reg_module_stride; + wire [31:0]\s2mm_reg_module_strt_addr[0] ; + wire [31:0]\s2mm_reg_module_strt_addr[1] ; + wire [31:0]\s2mm_reg_module_strt_addr[2] ; + wire [12:0]s2mm_reg_module_vsize; + wire [2:0]s2mm_s_frame_ptr_in; + wire s2mm_soft_reset; + wire s2mm_stop; + wire s2mm_tstvect_fsync; + wire s2mm_tuser_to_fsync_out; + wire s2mm_valid_frame_sync; + wire s2mm_valid_frame_sync_cmb; + wire s2mm_valid_video_prmtrs; + wire s_axi_lite_aclk; + wire [8:0]s_axi_lite_araddr; + wire s_axi_lite_arready; + wire s_axi_lite_arvalid; + wire [8:0]s_axi_lite_awaddr; + wire s_axi_lite_awready; + wire s_axi_lite_awvalid; + wire s_axi_lite_bready; + wire s_axi_lite_bvalid; + wire [31:0]s_axi_lite_rdata; + wire s_axi_lite_resetn; + wire s_axi_lite_rready; + wire s_axi_lite_rvalid; + wire [31:0]s_axi_lite_wdata; + wire s_axi_lite_wready; + wire s_axi_lite_wvalid; + wire s_axis_fifo_ainit_nosync; + wire s_axis_s2mm_aclk; + wire [63:0]s_axis_s2mm_cmd_tdata; + wire s_axis_s2mm_cmd_tvalid; + wire [7:0]s_axis_s2mm_tdata; + wire s_axis_s2mm_tlast; + wire s_axis_s2mm_tready; + wire [0:0]s_axis_s2mm_tuser; + wire s_axis_s2mm_tuser_d1; + wire s_axis_s2mm_tvalid; + wire s_valid0; + wire s_valid0_9; + wire sig_reset_reg; + wire strm_all_lines_rcvd_no_dwidth; + wire strm_not_finished_no_dwidth; + wire [12:0]vsize_counter_no_dwidth; + wire [1:0]\NLW_GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_DOD_UNCONNECTED ; + wire [1:1]\NLW_GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_DOC_UNCONNECTED ; + wire [1:0]\NLW_GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_DOD_UNCONNECTED ; + wire [3:3]\NLW_GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]_i_7_CO_UNCONNECTED ; + + assign axi_vdma_tstvec[63] = \ ; + assign axi_vdma_tstvec[62] = \ ; + assign axi_vdma_tstvec[61] = \ ; + assign axi_vdma_tstvec[60] = \ ; + assign axi_vdma_tstvec[59] = \ ; + assign axi_vdma_tstvec[58] = \ ; + assign axi_vdma_tstvec[57] = \ ; + assign axi_vdma_tstvec[56] = \ ; + assign axi_vdma_tstvec[55] = \ ; + assign axi_vdma_tstvec[54] = \ ; + assign axi_vdma_tstvec[53] = \ ; + assign axi_vdma_tstvec[52] = \ ; + assign axi_vdma_tstvec[51] = \ ; + assign axi_vdma_tstvec[50] = \ ; + assign axi_vdma_tstvec[49] = \ ; + assign axi_vdma_tstvec[48] = \ ; + assign axi_vdma_tstvec[47] = \ ; + assign axi_vdma_tstvec[46] = \ ; + assign axi_vdma_tstvec[45] = \ ; + assign axi_vdma_tstvec[44] = \ ; + assign axi_vdma_tstvec[43] = \ ; + assign axi_vdma_tstvec[42] = \ ; + assign axi_vdma_tstvec[41] = \ ; + assign axi_vdma_tstvec[40] = \ ; + assign axi_vdma_tstvec[39] = \ ; + assign axi_vdma_tstvec[38] = \ ; + assign axi_vdma_tstvec[37] = \ ; + assign axi_vdma_tstvec[36] = \ ; + assign axi_vdma_tstvec[35] = \ ; + assign axi_vdma_tstvec[34] = \ ; + assign axi_vdma_tstvec[33] = \ ; + assign axi_vdma_tstvec[32] = \ ; + assign axi_vdma_tstvec[31] = \ ; + assign axi_vdma_tstvec[30] = \ ; + assign axi_vdma_tstvec[29] = \ ; + assign axi_vdma_tstvec[28] = \ ; + assign axi_vdma_tstvec[27] = \ ; + assign axi_vdma_tstvec[26] = \ ; + assign axi_vdma_tstvec[25] = \ ; + assign axi_vdma_tstvec[24] = \ ; + assign axi_vdma_tstvec[23] = \ ; + assign axi_vdma_tstvec[22] = \ ; + assign axi_vdma_tstvec[21] = \ ; + assign axi_vdma_tstvec[20] = \ ; + assign axi_vdma_tstvec[19] = \ ; + assign axi_vdma_tstvec[18] = \ ; + assign axi_vdma_tstvec[17] = \ ; + assign axi_vdma_tstvec[16] = \ ; + assign axi_vdma_tstvec[15] = \ ; + assign axi_vdma_tstvec[14] = \ ; + assign axi_vdma_tstvec[13] = \ ; + assign axi_vdma_tstvec[12] = \ ; + assign axi_vdma_tstvec[11] = \ ; + assign axi_vdma_tstvec[10] = \ ; + assign axi_vdma_tstvec[9] = \ ; + assign axi_vdma_tstvec[8] = \ ; + assign axi_vdma_tstvec[7] = \ ; + assign axi_vdma_tstvec[6] = \ ; + assign axi_vdma_tstvec[5] = \ ; + assign axi_vdma_tstvec[4] = \ ; + assign axi_vdma_tstvec[3] = \ ; + assign axi_vdma_tstvec[2] = \ ; + assign axi_vdma_tstvec[1] = \ ; + assign axi_vdma_tstvec[0] = \ ; + assign m_axi_mm2s_arburst[1] = \ ; + assign m_axi_mm2s_arburst[0] = \^m_axi_mm2s_arburst [0]; + assign m_axi_mm2s_arcache[3] = \ ; + assign m_axi_mm2s_arcache[2] = \ ; + assign m_axi_mm2s_arcache[1] = \ ; + assign m_axi_mm2s_arcache[0] = \ ; + assign m_axi_mm2s_arlen[7] = \ ; + assign m_axi_mm2s_arlen[6] = \ ; + assign m_axi_mm2s_arlen[5] = \ ; + assign m_axi_mm2s_arlen[4:0] = \^m_axi_mm2s_arlen [4:0]; + assign m_axi_mm2s_arprot[2] = \ ; + assign m_axi_mm2s_arprot[1] = \ ; + assign m_axi_mm2s_arprot[0] = \ ; + assign m_axi_mm2s_arsize[2] = \ ; + assign m_axi_mm2s_arsize[1:0] = \^m_axi_mm2s_arsize [1:0]; + assign m_axi_s2mm_awburst[1] = \ ; + assign m_axi_s2mm_awburst[0] = \^m_axi_s2mm_awburst [0]; + assign m_axi_s2mm_awcache[3] = \ ; + assign m_axi_s2mm_awcache[2] = \ ; + assign m_axi_s2mm_awcache[1] = \ ; + assign m_axi_s2mm_awcache[0] = \ ; + assign m_axi_s2mm_awlen[7] = \ ; + assign m_axi_s2mm_awlen[6] = \ ; + assign m_axi_s2mm_awlen[5:0] = \^m_axi_s2mm_awlen [5:0]; + assign m_axi_s2mm_awprot[2] = \ ; + assign m_axi_s2mm_awprot[1] = \ ; + assign m_axi_s2mm_awprot[0] = \ ; + assign m_axi_s2mm_awsize[2] = \ ; + assign m_axi_s2mm_awsize[1:0] = \^m_axi_s2mm_awsize [1:0]; + assign m_axi_s2mm_wstrb[7] = \ ; + assign m_axi_s2mm_wstrb[6] = \ ; + assign m_axi_s2mm_wstrb[5] = \ ; + assign m_axi_s2mm_wstrb[4] = \ ; + assign m_axi_s2mm_wstrb[3] = \ ; + assign m_axi_s2mm_wstrb[2] = \ ; + assign m_axi_s2mm_wstrb[1] = \ ; + assign m_axi_s2mm_wstrb[0] = \ ; + assign m_axi_sg_araddr[31] = \ ; + assign m_axi_sg_araddr[30] = \ ; + assign m_axi_sg_araddr[29] = \ ; + assign m_axi_sg_araddr[28] = \ ; + assign m_axi_sg_araddr[27] = \ ; + assign m_axi_sg_araddr[26] = \ ; + assign m_axi_sg_araddr[25] = \ ; + assign m_axi_sg_araddr[24] = \ ; + assign m_axi_sg_araddr[23] = \ ; + assign m_axi_sg_araddr[22] = \ ; + assign m_axi_sg_araddr[21] = \ ; + assign m_axi_sg_araddr[20] = \ ; + assign m_axi_sg_araddr[19] = \ ; + assign m_axi_sg_araddr[18] = \ ; + assign m_axi_sg_araddr[17] = \ ; + assign m_axi_sg_araddr[16] = \ ; + assign m_axi_sg_araddr[15] = \ ; + assign m_axi_sg_araddr[14] = \ ; + assign m_axi_sg_araddr[13] = \ ; + assign m_axi_sg_araddr[12] = \ ; + assign m_axi_sg_araddr[11] = \ ; + assign m_axi_sg_araddr[10] = \ ; + assign m_axi_sg_araddr[9] = \ ; + assign m_axi_sg_araddr[8] = \ ; + assign m_axi_sg_araddr[7] = \ ; + assign m_axi_sg_araddr[6] = \ ; + assign m_axi_sg_araddr[5] = \ ; + assign m_axi_sg_araddr[4] = \ ; + assign m_axi_sg_araddr[3] = \ ; + assign m_axi_sg_araddr[2] = \ ; + assign m_axi_sg_araddr[1] = \ ; + assign m_axi_sg_araddr[0] = \ ; + assign m_axi_sg_arburst[1] = \ ; + assign m_axi_sg_arburst[0] = \ ; + assign m_axi_sg_arcache[3] = \ ; + assign m_axi_sg_arcache[2] = \ ; + assign m_axi_sg_arcache[1] = \ ; + assign m_axi_sg_arcache[0] = \ ; + assign m_axi_sg_arlen[7] = \ ; + assign m_axi_sg_arlen[6] = \ ; + assign m_axi_sg_arlen[5] = \ ; + assign m_axi_sg_arlen[4] = \ ; + assign m_axi_sg_arlen[3] = \ ; + assign m_axi_sg_arlen[2] = \ ; + assign m_axi_sg_arlen[1] = \ ; + assign m_axi_sg_arlen[0] = \ ; + assign m_axi_sg_arprot[2] = \ ; + assign m_axi_sg_arprot[1] = \ ; + assign m_axi_sg_arprot[0] = \ ; + assign m_axi_sg_arsize[2] = \ ; + assign m_axi_sg_arsize[1] = \ ; + assign m_axi_sg_arsize[0] = \ ; + assign m_axi_sg_arvalid = \ ; + assign m_axi_sg_rready = \ ; + assign m_axis_mm2s_tkeep[3] = \ ; + assign m_axis_mm2s_tkeep[2] = \ ; + assign m_axis_mm2s_tkeep[1] = \ ; + assign m_axis_mm2s_tkeep[0] = \ ; + assign mm2s_buffer_almost_empty = \ ; + assign mm2s_buffer_empty = \ ; + assign mm2s_fsync_out = \ ; + assign mm2s_prmry_reset_out_n = \ ; + assign mm2s_prmtr_update = \ ; + assign s2mm_buffer_almost_full = \ ; + assign s2mm_buffer_full = \ ; + assign s2mm_fsync_out = \ ; + assign s2mm_prmry_reset_out_n = \ ; + assign s2mm_prmtr_update = \ ; + assign s_axi_lite_bresp[1] = \ ; + assign s_axi_lite_bresp[0] = \ ; + assign s_axi_lite_rresp[1] = \ ; + assign s_axi_lite_rresp[0] = \ ; + Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_if AXI_LITE_REG_INTERFACE_I + (.D(mm2s_axi2ip_wrdata), + .\DMA_IRQ_MASK_GEN.dma_irq_mask_i_reg[3] (dma_irq_mask_i), + .\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] (s2mm_reg_module_stride), + .\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4] (s2mm_chnl_current_frame), + .\DYNAMIC_MASTER_MODE_FRAME_CNT.genlock_pair_frame_reg[4] (s2mm_genlock_pair_frame), + .\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31] (s2mm_axi2ip_wrdata), + .\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31]_0 (\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_81 ), + .\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] (AXI_LITE_REG_INTERFACE_I_n_81), + .\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]_0 (AXI_LITE_REG_INTERFACE_I_n_128), + .\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[23] (\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_82 ), + .\GEN_FOR_FLUSH.fsize_err_reg (AXI_LITE_REG_INTERFACE_I_n_166), + .\GEN_FOR_FLUSH.fsize_err_reg_0 (\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_62 ), + .\GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg (AXI_LITE_REG_INTERFACE_I_n_168), + .\GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg_0 (\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_64 ), + .\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_reg (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_74 ), + .\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] (mm2s_irqthresh_status), + .\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7] (s2mm_irqthresh_status), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11] (AXI_LITE_REG_INTERFACE_I_n_113), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12] (AXI_LITE_REG_INTERFACE_I_n_111), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15] (AXI_LITE_REG_INTERFACE_I_n_114), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_0 (AXI_LITE_REG_INTERFACE_I_n_115), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31] (AXI_LITE_REG_INTERFACE_I_n_112), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31] ({AXI_LITE_REG_INTERFACE_I_n_129,AXI_LITE_REG_INTERFACE_I_n_130,AXI_LITE_REG_INTERFACE_I_n_131,AXI_LITE_REG_INTERFACE_I_n_132,AXI_LITE_REG_INTERFACE_I_n_133,AXI_LITE_REG_INTERFACE_I_n_134,AXI_LITE_REG_INTERFACE_I_n_135,AXI_LITE_REG_INTERFACE_I_n_136,AXI_LITE_REG_INTERFACE_I_n_137,AXI_LITE_REG_INTERFACE_I_n_138,AXI_LITE_REG_INTERFACE_I_n_139,AXI_LITE_REG_INTERFACE_I_n_140,AXI_LITE_REG_INTERFACE_I_n_141,AXI_LITE_REG_INTERFACE_I_n_142,AXI_LITE_REG_INTERFACE_I_n_143,AXI_LITE_REG_INTERFACE_I_n_144,AXI_LITE_REG_INTERFACE_I_n_145,AXI_LITE_REG_INTERFACE_I_n_146,AXI_LITE_REG_INTERFACE_I_n_147,AXI_LITE_REG_INTERFACE_I_n_148,AXI_LITE_REG_INTERFACE_I_n_149,AXI_LITE_REG_INTERFACE_I_n_150,AXI_LITE_REG_INTERFACE_I_n_151,AXI_LITE_REG_INTERFACE_I_n_152,AXI_LITE_REG_INTERFACE_I_n_153,AXI_LITE_REG_INTERFACE_I_n_154,AXI_LITE_REG_INTERFACE_I_n_155,AXI_LITE_REG_INTERFACE_I_n_156,AXI_LITE_REG_INTERFACE_I_n_157,AXI_LITE_REG_INTERFACE_I_n_158,AXI_LITE_REG_INTERFACE_I_n_159,AXI_LITE_REG_INTERFACE_I_n_160}), + .\GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14] ({\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_74 ,\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_75 ,\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_76 ,\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_77 ,\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_78 ,\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_79 ,\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_80 }), + .\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] (\mm2s_reg_module_strt_addr[0] [31:13]), + .\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 (\s2mm_reg_module_strt_addr[0] ), + .\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 (p_81_out), + .\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] ({\mm2s_reg_module_strt_addr[1] [31:16],\mm2s_reg_module_strt_addr[1] [14:3],\mm2s_reg_module_strt_addr[1] [0]}), + .\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 (\s2mm_reg_module_strt_addr[1] ), + .\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 (p_84_out), + .\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] ({\mm2s_reg_module_strt_addr[2] [31:16],\mm2s_reg_module_strt_addr[2] [14:3],\mm2s_reg_module_strt_addr[2] [0]}), + .\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 (\s2mm_reg_module_strt_addr[2] ), + .\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4] (p_31_out), + .\MM2S_ERR_FOR_IRQ.frm_store_i_reg[4] (p_79_out), + .\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] (mm2s_reg_module_stride[15:13]), + .\M_GEN_DMACR_REGISTER.dmacr_i_reg[14] ({\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_67 ,\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_68 ,\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_69 ,\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_70 ,\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_71 }), + .Q(p_80_out), + .\S2MM_ERR_FOR_IRQ.frm_store_i_reg[4] (p_82_out), + .SR(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.S2MM_INTRPT_CROSSING_I/scndry_reset2 ), + .ch1_dly_irq_set(mm2s_dly_irq_set), + .ch1_irqdelay_status(mm2s_irqdelay_status), + .ch2_dly_irq_set(s2mm_dly_irq_set), + .ch2_irqdelay_status(s2mm_irqdelay_status), + .dly_irq_reg(AXI_LITE_REG_INTERFACE_I_n_164), + .dly_irq_reg_0(AXI_LITE_REG_INTERFACE_I_n_170), + .dly_irq_reg_1(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_58 ), + .dly_irq_reg_2(\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_66 ), + .dma_decerr_reg(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_56 ), + .dma_decerr_reg_0(\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_61 ), + .dma_interr_reg(AXI_LITE_REG_INTERFACE_I_n_165), + .dma_interr_reg_0(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_54 ), + .dma_interr_reg_1(\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_59 ), + .dma_slverr_reg(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_55 ), + .dma_slverr_reg_0(\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_60 ), + .dmacr_i(\I_DMA_REGISTER/dmacr_i ), + .err_irq_reg(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_73 ), + .err_irq_reg_0(\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_87 ), + .fsize_mismatch_err(s2mm_fsize_mismatch_err), + .in0({AXI_LITE_REG_INTERFACE_I_n_82,AXI_LITE_REG_INTERFACE_I_n_83,AXI_LITE_REG_INTERFACE_I_n_84,AXI_LITE_REG_INTERFACE_I_n_85,AXI_LITE_REG_INTERFACE_I_n_86,AXI_LITE_REG_INTERFACE_I_n_87,AXI_LITE_REG_INTERFACE_I_n_88,AXI_LITE_REG_INTERFACE_I_n_89,AXI_LITE_REG_INTERFACE_I_n_90,AXI_LITE_REG_INTERFACE_I_n_91,AXI_LITE_REG_INTERFACE_I_n_92,AXI_LITE_REG_INTERFACE_I_n_93,AXI_LITE_REG_INTERFACE_I_n_94,AXI_LITE_REG_INTERFACE_I_n_95,AXI_LITE_REG_INTERFACE_I_n_96,AXI_LITE_REG_INTERFACE_I_n_97,AXI_LITE_REG_INTERFACE_I_n_98,AXI_LITE_REG_INTERFACE_I_n_99,AXI_LITE_REG_INTERFACE_I_n_100,AXI_LITE_REG_INTERFACE_I_n_101,AXI_LITE_REG_INTERFACE_I_n_102,AXI_LITE_REG_INTERFACE_I_n_103,AXI_LITE_REG_INTERFACE_I_n_104,AXI_LITE_REG_INTERFACE_I_n_105,AXI_LITE_REG_INTERFACE_I_n_106,AXI_LITE_REG_INTERFACE_I_n_107,AXI_LITE_REG_INTERFACE_I_n_108,AXI_LITE_REG_INTERFACE_I_n_109,AXI_LITE_REG_INTERFACE_I_n_110}), + .ioc_irq_reg(AXI_LITE_REG_INTERFACE_I_n_163), + .ioc_irq_reg_0(AXI_LITE_REG_INTERFACE_I_n_169), + .ioc_irq_reg_1(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_57 ), + .ioc_irq_reg_2(\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_65 ), + .lsize_err_reg(AXI_LITE_REG_INTERFACE_I_n_167), + .lsize_err_reg_0(\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_63 ), + .lsize_mismatch_err(s2mm_lsize_mismatch_err), + .lsize_more_err_reg(AXI_LITE_REG_INTERFACE_I_n_171), + .lsize_more_err_reg_0(\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_67 ), + .lsize_more_mismatch_err(s2mm_lsize_more_mismatch_err), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .mm2s_axi2ip_wrce({mm2s_axi2ip_wrce[25:20],mm2s_axi2ip_wrce[10],mm2s_axi2ip_wrce[1:0]}), + .mm2s_introut(mm2s_introut), + .mm2s_ioc_irq_set(mm2s_ioc_irq_set), + .mm2s_prmry_resetn(mm2s_prmry_resetn), + .out(mm2s_axi2ip_rdaddr), + .p_14_out(\I_DMA_REGISTER/p_14_out ), + .p_15_out(\I_DMA_REGISTER/p_15_out ), + .p_70_out(p_70_out), + .p_71_out({p_71_out[31:16],p_71_out[4],p_71_out[0]}), + .p_78_out(p_78_out), + .prmry_reset2(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.MM2S_INTRPT_CROSSING_I/prmry_reset2 ), + .prmry_reset2_0(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.S2MM_INTRPT_CROSSING_I/prmry_reset2 ), + .prmtr_updt_complete_i_reg(AXI_LITE_REG_INTERFACE_I_n_161), + .prmtr_updt_complete_i_reg_0(AXI_LITE_REG_INTERFACE_I_n_162), + .\ptr_ref_i_reg[4] (p_83_out), + .\reg_module_hsize_reg[0] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_75 ), + .\reg_module_hsize_reg[10] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_224 ), + .\reg_module_hsize_reg[11] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_225 ), + .\reg_module_hsize_reg[12] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_226 ), + .\reg_module_hsize_reg[15] (mm2s_reg_module_hsize[15:13]), + .\reg_module_hsize_reg[15]_0 (s2mm_reg_module_hsize), + .\reg_module_hsize_reg[3] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_217 ), + .\reg_module_hsize_reg[4] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_218 ), + .\reg_module_hsize_reg[5] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_219 ), + .\reg_module_hsize_reg[6] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_220 ), + .\reg_module_hsize_reg[7] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_221 ), + .\reg_module_hsize_reg[8] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_222 ), + .\reg_module_hsize_reg[9] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_223 ), + .\reg_module_vsize_reg[12] (s2mm_reg_module_vsize), + .s2mm_axi2ip_wrce({s2mm_axi2ip_wrce[45:40],s2mm_axi2ip_wrce[15],s2mm_axi2ip_wrce[13:12],s2mm_axi2ip_wrce[10]}), + .s2mm_dma_interr_set_minus_frame_errors(s2mm_dma_interr_set_minus_frame_errors), + .s2mm_dmacr({s2mm_dmacr[31:15],s2mm_dmacr[6:3],s2mm_dmacr[1:0]}), + .s2mm_dmasr(s2mm_dmasr), + .s2mm_fsize_more_or_sof_late(s2mm_fsize_more_or_sof_late), + .s2mm_introut(s2mm_introut), + .s2mm_ioc_irq_set(s2mm_ioc_irq_set), + .s2mm_ip2axi_introut(s2mm_ip2axi_introut), + .s2mm_prmry_resetn(s2mm_prmry_resetn), + .s2mm_soft_reset(s2mm_soft_reset), + .s_axi_lite_aclk(s_axi_lite_aclk), + .s_axi_lite_araddr(s_axi_lite_araddr[7:2]), + .s_axi_lite_arready(s_axi_lite_arready), + .s_axi_lite_arvalid(s_axi_lite_arvalid), + .s_axi_lite_awaddr(s_axi_lite_awaddr[7:2]), + .s_axi_lite_awready(s_axi_lite_awready), + .s_axi_lite_awvalid(s_axi_lite_awvalid), + .s_axi_lite_bready(s_axi_lite_bready), + .s_axi_lite_bvalid(s_axi_lite_bvalid), + .s_axi_lite_rdata(s_axi_lite_rdata), + .s_axi_lite_resetn(s_axi_lite_resetn), + .s_axi_lite_rready(s_axi_lite_rready), + .s_axi_lite_rvalid(s_axi_lite_rvalid), + .s_axi_lite_wdata(s_axi_lite_wdata), + .s_axi_lite_wready(s_axi_lite_wready), + .s_axi_lite_wvalid(s_axi_lite_wvalid), + .stop(p_36_out)); + (* METHODOLOGY_DRC_VIOS = "" *) + RAM32M \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5 + (.ADDRA({1'b0,1'b0,\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_0_out }), + .ADDRB({1'b0,1'b0,\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_0_out }), + .ADDRC({1'b0,1'b0,\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_0_out }), + .ADDRD({1'b0,1'b0,\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_11_out }), + .DIA(\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_byte_cntr [1:0]), + .DIB(\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_byte_cntr [3:2]), + .DIC(\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_byte_cntr [5:4]), + .DID({1'b0,1'b0}), + .DOA({\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_0 ,\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_1 }), + .DOB({\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_2 ,\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_3 }), + .DOC({\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_4 ,\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_5 }), + .DOD(\NLW_GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_DOD_UNCONNECTED [1:0]), + .WCLK(m_axi_s2mm_aclk), + .WE(I_PRMRY_DATAMOVER_n_39)); + (* METHODOLOGY_DRC_VIOS = "" *) + RAM32M \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10 + (.ADDRA({1'b0,1'b0,\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_0_out }), + .ADDRB({1'b0,1'b0,\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_0_out }), + .ADDRC({1'b0,1'b0,\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_0_out }), + .ADDRD({1'b0,1'b0,\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_11_out }), + .DIA(\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_byte_cntr [7:6]), + .DIB({\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_dre2ibtt_tlast_reg ,\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_byte_cntr [8]}), + .DIC({1'b0,\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_dre2ibtt_eop_reg }), + .DID({1'b0,1'b0}), + .DOA({\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_n_0 ,\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_n_1 }), + .DOB({\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_n_2 ,\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_n_3 }), + .DOC({\NLW_GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_DOC_UNCONNECTED [1],\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_n_5 }), + .DOD(\NLW_GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_DOD_UNCONNECTED [1:0]), + .WCLK(m_axi_s2mm_aclk), + .WE(I_PRMRY_DATAMOVER_n_39)); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_mngr \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR + (.D(mm2s_axi2ip_wrdata[4]), + .E(I_PRMRY_DATAMOVER_n_22), + .\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2] (p_44_out), + .\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4] (p_31_out), + .\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] (\mm2s_reg_module_strt_addr[0] ), + .\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] (\mm2s_reg_module_strt_addr[1] ), + .\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] (\mm2s_reg_module_strt_addr[2] ), + .\INFERRED_GEN.cnt_i_reg[1] (\GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_31 ), + .\INFERRED_GEN.cnt_i_reg[2] (I_PRMRY_DATAMOVER_n_32), + .\INFERRED_GEN.cnt_i_reg[2]_0 (I_PRMRY_DATAMOVER_n_34), + .\INFERRED_GEN.cnt_i_reg[2]_1 (I_PRMRY_DATAMOVER_n_35), + .\INFERRED_GEN.cnt_i_reg[2]_2 (\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_rd_empty ), + .\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 (p_33_out), + .\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] (mm2s_reg_module_stride), + .Q(p_49_out), + .SR(\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I/prmry_reset2 ), + .cmnd_wr(cmnd_wr), + .datamover_idle(\I_STS_MNGR/datamover_idle ), + .dma_decerr_reg(\GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_35 ), + .dma_decerr_reg_0(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_56 ), + .dma_err(dma_err), + .dma_interr_reg(\GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_33 ), + .dma_interr_reg_0(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_54 ), + .dma_slverr_reg(\GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_34 ), + .dma_slverr_reg_0(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_55 ), + .\dmacr_i_reg[2] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_227 ), + .err_i_reg(I_RST_MODULE_n_26), + .halted_reg(\GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_32 ), + .halted_reg_0(\I_CMDSTS/s_axis_cmd_tvalid0 ), + .initial_frame(initial_frame), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .mask_fsync_out_i(mask_fsync_out_i), + .mm2s_all_lines_xfred(p_0_out), + .mm2s_axi2ip_wrce(mm2s_axi2ip_wrce[1]), + .mm2s_fifo_pipe_empty(p_1_out), + .mm2s_halt(mm2s_halt), + .mm2s_prmry_resetn(mm2s_prmry_resetn), + .p_24_out(p_24_out), + .p_2_out(p_2_out), + .p_37_out(p_37_out), + .p_39_out(p_39_out), + .p_45_out(p_45_out), + .p_46_out(p_46_out), + .p_47_out(p_47_out), + .p_50_out(p_50_out), + .p_56_out(p_56_out), + .p_58_out(p_58_out), + .p_67_out(p_67_out), + .p_70_out(p_70_out), + .p_71_out(p_71_out[1:0]), + .p_77_out(p_77_out), + .prmry_resetn_i_reg(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_228 ), + .prmtr_update_complete(prmtr_update_complete), + .prmtr_updt_complete_i_reg(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_231 ), + .\ptr_ref_i_reg[4] (p_80_out), + .\reg_module_hsize_reg[15] (mm2s_reg_module_hsize), + .\reg_module_vsize_reg[12] (mm2s_reg_module_vsize), + .\sig_addr_cntr_lsh_kh_reg[31] ({p_57_out[63:32],p_57_out[23],p_57_out[15:0]}), + .sig_halt_cmplt_reg(I_PRMRY_DATAMOVER_n_23), + .stop(p_36_out)); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_fsync_gen \GEN_SPRT_FOR_MM2S.MM2S_FSYNC_I + (.Q(mm2s_irqthresh_status), + .SR(\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I/prmry_reset2 ), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .mask_fsync_out_i(mask_fsync_out_i), + .p_24_out(p_24_out), + .p_2_out(p_2_out), + .p_37_out(p_37_out), + .p_46_out(p_46_out), + .p_47_out(p_47_out), + .p_4_out(p_4_out), + .p_71_out({p_71_out[4],p_71_out[0]}), + .p_in_d1_cdc_from(\GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/p_in_d1_cdc_from ), + .prmry_in_xored(\GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/prmry_in_xored ), + .prmry_resetn_i_reg(I_AXI_DMA_INTRPT_n_39)); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_mm2s_linebuf \GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I + (.DIN(dm2linebuf_mm2s_tlast), + .FULL(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/p_5_out ), + .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 (p_7_out), + .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 (\GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_8 ), + .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/p_8_out ), + .\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 (\GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_6 ), + .\INCLUDE_UNPACKING.lsig_cmd_loaded_reg (\GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_7 ), + .Q(p_49_out), + .SR(\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I/prmry_reset2 ), + .WR_EN(I_RST_MODULE_n_25), + .all_lines_xfred(all_lines_xfred), + .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), + .halt_i_reg(I_RST_MODULE_n_29), + .hold_ff_q_reg(I_PRMRY_DATAMOVER_n_191), + .lsig_0ffset_cntr(\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/lsig_0ffset_cntr ), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .m_axis_mm2s_aclk(m_axis_mm2s_aclk), + .m_axis_mm2s_tdata(m_axis_mm2s_tdata), + .m_axis_mm2s_tlast(m_axis_mm2s_tlast), + .m_axis_mm2s_tready(m_axis_mm2s_tready), + .m_axis_mm2s_tuser(m_axis_mm2s_tuser), + .mm2s_all_lines_xfred(p_0_out), + .mm2s_axis_resetn(mm2s_axis_resetn), + .mm2s_fifo_pipe_empty(p_1_out), + .mm2s_halt(mm2s_halt), + .mm2s_prmry_resetn(mm2s_prmry_resetn), + .out(m_axis_mm2s_tvalid), + .p_15_out(p_15_out), + .p_24_out(p_24_out), + .s_valid0(s_valid0), + .scndry_reset2(\GEN_CDC_FOR_ASYNC.PRMTR_UPDT_CDC_I/scndry_reset2 ), + .sig_reset_reg_reg(\GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_3 )); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_module \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I + (.D(mm2s_axi2ip_wrdata), + .E(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_72 ), + .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_227 ), + .\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_63 ), + .\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]_0 (p_11_out), + .\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_62 ), + .\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_65 ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] (mm2s_axi2ip_rdaddr), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]_0 (AXI_LITE_REG_INTERFACE_I_n_114), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[4] (AXI_LITE_REG_INTERFACE_I_n_111), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7] (AXI_LITE_REG_INTERFACE_I_n_112), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_0 (AXI_LITE_REG_INTERFACE_I_n_113), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_1 (AXI_LITE_REG_INTERFACE_I_n_115), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[2] (AXI_LITE_REG_INTERFACE_I_n_161), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12] (AXI_LITE_REG_INTERFACE_I_n_163), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13] (AXI_LITE_REG_INTERFACE_I_n_164), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18] (AXI_LITE_REG_INTERFACE_I_n_81), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] (\GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_33 ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_75 ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_224 ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_225 ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_226 ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_217 ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_218 ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_219 ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_220 ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_221 ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_222 ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_223 ), + .\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] (p_80_out), + .\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] (p_79_out), + .\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_231 ), + .\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] (\mm2s_reg_module_strt_addr[0] ), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] (\mm2s_reg_module_strt_addr[1] ), + .\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] (\mm2s_reg_module_strt_addr[2] ), + .\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_228 ), + .\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0 (p_33_out), + .Q({\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_67 ,\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_68 ,\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_69 ,\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_70 ,\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_71 }), + .SR(\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I/prmry_reset2 ), + .ch1_delay_cnt_en(ch1_delay_cnt_en), + .ch1_delay_zero(ch1_delay_zero), + .ch1_dly_irq_set(mm2s_dly_irq_set), + .decerr_i_reg(\GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_35 ), + .dly_irq_reg(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_58 ), + .dma_err(dma_err), + .dmacr_i(\I_DMA_REGISTER/dmacr_i ), + .\dmacr_i_reg[0] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_74 ), + .\dmacr_i_reg[2] (I_RST_MODULE_n_16), + .err_d1_reg(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_54 ), + .err_d1_reg_0(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_55 ), + .err_d1_reg_1(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_56 ), + .err_irq_reg(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_73 ), + .halt_reset(\GEN_RESET_FOR_MM2S.RESET_I/halt_reset ), + .halted_clr_reg(\GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_32 ), + .\hsize_vid_reg[15] (mm2s_reg_module_hsize), + .in0({AXI_LITE_REG_INTERFACE_I_n_82,AXI_LITE_REG_INTERFACE_I_n_83,AXI_LITE_REG_INTERFACE_I_n_84,AXI_LITE_REG_INTERFACE_I_n_85,AXI_LITE_REG_INTERFACE_I_n_86,AXI_LITE_REG_INTERFACE_I_n_87,AXI_LITE_REG_INTERFACE_I_n_88,AXI_LITE_REG_INTERFACE_I_n_89,AXI_LITE_REG_INTERFACE_I_n_90,AXI_LITE_REG_INTERFACE_I_n_91,AXI_LITE_REG_INTERFACE_I_n_92,AXI_LITE_REG_INTERFACE_I_n_93,AXI_LITE_REG_INTERFACE_I_n_94,AXI_LITE_REG_INTERFACE_I_n_95,AXI_LITE_REG_INTERFACE_I_n_96,AXI_LITE_REG_INTERFACE_I_n_97,AXI_LITE_REG_INTERFACE_I_n_98,AXI_LITE_REG_INTERFACE_I_n_99,AXI_LITE_REG_INTERFACE_I_n_100,AXI_LITE_REG_INTERFACE_I_n_101,AXI_LITE_REG_INTERFACE_I_n_102,AXI_LITE_REG_INTERFACE_I_n_103,AXI_LITE_REG_INTERFACE_I_n_104,AXI_LITE_REG_INTERFACE_I_n_105,AXI_LITE_REG_INTERFACE_I_n_106,AXI_LITE_REG_INTERFACE_I_n_107,AXI_LITE_REG_INTERFACE_I_n_108,AXI_LITE_REG_INTERFACE_I_n_109,AXI_LITE_REG_INTERFACE_I_n_110}), + .initial_frame(initial_frame), + .ioc_irq_reg(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_57 ), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .mask_fsync_out_i(mask_fsync_out_i), + .mm2s_axi2ip_wrce({mm2s_axi2ip_wrce[25:20],mm2s_axi2ip_wrce[10],mm2s_axi2ip_wrce[1:0]}), + .mm2s_halt(mm2s_halt), + .mm2s_halt_cmplt(mm2s_halt_cmplt), + .mm2s_ioc_irq_set(mm2s_ioc_irq_set), + .out(p_81_out), + .p_13_out(p_13_out), + .p_17_out(p_17_out), + .p_24_out(p_24_out), + .p_45_out(p_45_out), + .p_47_out(p_47_out), + .p_50_out(p_50_out), + .p_67_out(p_67_out), + .p_70_out(p_70_out), + .p_71_out({p_71_out[31:16],p_71_out[4],p_71_out[1:0]}), + .p_77_out(p_77_out), + .p_78_out(p_78_out), + .prmry_in(p_39_out), + .prmry_resetn_i_reg(mm2s_prmry_resetn), + .prmtr_update_complete(prmtr_update_complete), + .reset_counts(\I_DMA_REGISTER/reset_counts ), + .reset_counts_reg(I_RST_MODULE_n_31), + .s_axis_cmd_tvalid_reg(\I_CMDSTS/s_axis_cmd_tvalid0 ), + .s_soft_reset_i0(\GEN_RESET_FOR_MM2S.RESET_I/s_soft_reset_i0 ), + .slverr_i_reg(\GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_34 ), + .stop(p_36_out), + .\stride_vid_reg[15] (mm2s_reg_module_stride), + .\vsize_vid_reg[12] (mm2s_reg_module_vsize)); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_sof_gen \GEN_SPRT_FOR_MM2S.MM2S_SOF_I + (.m_axis_mm2s_aclk(m_axis_mm2s_aclk), + .out(mm2s_axis_resetn), + .p_15_out(p_15_out), + .p_in_d1_cdc_from(\GEN_CDC_FOR_ASYNC.SOF_CDC_I/p_in_d1_cdc_from ), + .prmry_in_xored(\GEN_CDC_FOR_ASYNC.SOF_CDC_I/prmry_in_xored ), + .s_valid0(s_valid0), + .scndry_reset2(\GEN_CDC_FOR_ASYNC.PRMTR_UPDT_CDC_I/scndry_reset2 )); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_vid_cdc \GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I + (.\GENLOCK_FOR_MASTER.frame_ptr_out_reg[2] (p_44_out), + .\GEN_LINEBUF_NO_SOF.vsize_counter_reg[4] (\GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_6 ), + .SR(\GEN_CDC_FOR_ASYNC.PRMTR_UPDT_CDC_I/scndry_reset2 ), + .all_lines_xfred(all_lines_xfred), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .m_axis_mm2s_aclk(m_axis_mm2s_aclk), + .mm2s_frame_ptr_in(mm2s_frame_ptr_in), + .mm2s_frame_ptr_out(mm2s_frame_ptr_out), + .p_15_out(p_15_out), + .p_17_out(p_17_out), + .p_in_d1_cdc_from(\GEN_CDC_FOR_ASYNC.SOF_CDC_I/p_in_d1_cdc_from ), + .p_in_d1_cdc_from_0(\GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/p_in_d1_cdc_from ), + .prmry_in_xored(\GEN_CDC_FOR_ASYNC.SOF_CDC_I/prmry_in_xored ), + .prmry_in_xored_1(\GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/prmry_in_xored ), + .prmry_resetn_i_reg(\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I/prmry_reset2 )); + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized22 \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.GEN_FOR_ASYNC_FLUSH_SOF.S2MM_HALTED_CDC_I + (.SR(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF/prmry_reset2 ), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .prmry_reset2(\I_SM/GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF/prmry_reset2 ), + .s2mm_dmasr(s2mm_dmasr), + .s2mm_dmasr_halted_s(s2mm_dmasr_halted_s), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk)); + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized21 \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.GEN_FOR_ASYNC_FLUSH_SOF.S2MM_PRM_UPDT_CDC_I + (.\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_clr_flag1_reg (\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.GEN_FOR_ASYNC_FLUSH_SOF.S2MM_PRM_UPDT_CDC_I_n_1 ), + .SR(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF/prmry_reset2 ), + .d_tready_before_fsync_clr_flag1(d_tready_before_fsync_clr_flag1), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(s2mm_axis_resetn), + .p_in_d1_cdc_from(p_in_d1_cdc_from), + .prmry_in_xored(prmry_in_xored), + .prmry_reset2(\I_SM/GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF/prmry_reset2 ), + .s2mm_dmasr_halted_s(s2mm_dmasr_halted_s), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk)); + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized23 \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.GEN_FOR_ASYNC_FLUSH_SOF.SOF_LATE_CDC_I + (.\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_0 (\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.GEN_FOR_ASYNC_FLUSH_SOF.SOF_LATE_CDC_I_n_1 ), + .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_1 (\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.GEN_FOR_ASYNC_FLUSH_SOF.SOF_LATE_CDC_I_n_2 ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_n_0 ), + .SR(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF/prmry_reset2 ), + .d_tready_before_fsync(d_tready_before_fsync), + .d_tready_before_fsync_clr_flag1(d_tready_before_fsync_clr_flag1), + .d_tready_sof_late(d_tready_sof_late), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .prmry_reset2(\I_SM/GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF/prmry_reset2 ), + .s2mm_fsize_more_or_sof_late(s2mm_fsize_more_or_sof_late), + .s2mm_fsize_more_or_sof_late_s(s2mm_fsize_more_or_sof_late_s), + .s2mm_tuser_to_fsync_out(s2mm_tuser_to_fsync_out), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk)); + FDRE #( + .INIT(1'b0)) + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_clr_flag1_reg + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.GEN_FOR_ASYNC_FLUSH_SOF.S2MM_PRM_UPDT_CDC_I_n_1 ), + .Q(d_tready_before_fsync_clr_flag1), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_reg + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(I_RST_MODULE_n_28), + .Q(d_tready_before_fsync), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_fsize_less_err_flag_10_reg + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(\GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_56 ), + .Q(s2mm_fsize_less_err_flag_10), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_sof_late_err_reg + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(\GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_9 ), + .Q(d_tready_sof_late), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_tuser_to_fsync_out_reg + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(\GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_8 ), + .Q(s2mm_tuser_to_fsync_out), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s_axis_s2mm_tuser_d1_reg + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(p_19_in), + .Q(s_axis_s2mm_tuser_d1), + .R(\I_SM/GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF/prmry_reset2 )); + FDRE #( + .INIT(1'b0)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg + (.C(s_axis_s2mm_aclk), + .CE(strm_all_lines_rcvd_no_dwidth), + .D(strm_not_finished_no_dwidth), + .Q(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_n_0 ), + .R(\GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4 )); + FDSE #( + .INIT(1'b0)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg + (.C(s_axis_s2mm_aclk), + .CE(strm_all_lines_rcvd_no_dwidth), + .D(\GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I_n_16 ), + .Q(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg_n_0 ), + .S(\GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4 )); + LUT1 #( + .INIT(2'h1)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_10 + (.I0(vsize_counter_no_dwidth[12]), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_10_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_11 + (.I0(vsize_counter_no_dwidth[11]), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_11_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_12 + (.I0(vsize_counter_no_dwidth[10]), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_12_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_13 + (.I0(vsize_counter_no_dwidth[9]), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_13_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_4 + (.I0(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_8_n_0 ), + .I1(vsize_counter_no_dwidth[6]), + .I2(vsize_counter_no_dwidth[5]), + .I3(vsize_counter_no_dwidth[8]), + .I4(vsize_counter_no_dwidth[7]), + .I5(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_9_n_0 ), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_4_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_8 + (.I0(vsize_counter_no_dwidth[10]), + .I1(vsize_counter_no_dwidth[9]), + .I2(vsize_counter_no_dwidth[12]), + .I3(vsize_counter_no_dwidth[11]), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_8_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_9 + (.I0(vsize_counter_no_dwidth[2]), + .I1(vsize_counter_no_dwidth[1]), + .I2(vsize_counter_no_dwidth[4]), + .I3(vsize_counter_no_dwidth[3]), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_9_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_3 + (.I0(vsize_counter_no_dwidth[4]), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_3_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_4 + (.I0(vsize_counter_no_dwidth[3]), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_5 + (.I0(vsize_counter_no_dwidth[2]), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_5_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_6 + (.I0(vsize_counter_no_dwidth[1]), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_6_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_3 + (.I0(vsize_counter_no_dwidth[8]), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_3_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_4 + (.I0(vsize_counter_no_dwidth[7]), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_5 + (.I0(vsize_counter_no_dwidth[6]), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_5_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_6 + (.I0(vsize_counter_no_dwidth[5]), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_6_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] + (.C(s_axis_s2mm_aclk), + .CE(strm_all_lines_rcvd_no_dwidth), + .D(p_1_in[0]), + .Q(vsize_counter_no_dwidth[0]), + .R(\GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4 )); + FDRE #( + .INIT(1'b0)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[10] + (.C(s_axis_s2mm_aclk), + .CE(strm_all_lines_rcvd_no_dwidth), + .D(p_1_in[10]), + .Q(vsize_counter_no_dwidth[10]), + .R(\GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4 )); + FDRE #( + .INIT(1'b0)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[11] + (.C(s_axis_s2mm_aclk), + .CE(strm_all_lines_rcvd_no_dwidth), + .D(p_1_in[11]), + .Q(vsize_counter_no_dwidth[11]), + .R(\GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4 )); + FDRE #( + .INIT(1'b0)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] + (.C(s_axis_s2mm_aclk), + .CE(strm_all_lines_rcvd_no_dwidth), + .D(p_1_in[12]), + .Q(vsize_counter_no_dwidth[12]), + .R(\GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4 )); + CARRY4 \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]_i_7 + (.CI(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[8]_i_2_n_0 ), + .CO({\NLW_GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]_i_7_CO_UNCONNECTED [3],\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]_i_7_n_1 ,\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]_i_7_n_2 ,\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]_i_7_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,vsize_counter_no_dwidth[11:9]}), + .O(minusOp[12:9]), + .S({\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_10_n_0 ,\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_11_n_0 ,\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_12_n_0 ,\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_13_n_0 })); + FDRE #( + .INIT(1'b0)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[1] + (.C(s_axis_s2mm_aclk), + .CE(strm_all_lines_rcvd_no_dwidth), + .D(p_1_in[1]), + .Q(vsize_counter_no_dwidth[1]), + .R(\GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4 )); + FDRE #( + .INIT(1'b0)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[2] + (.C(s_axis_s2mm_aclk), + .CE(strm_all_lines_rcvd_no_dwidth), + .D(p_1_in[2]), + .Q(vsize_counter_no_dwidth[2]), + .R(\GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4 )); + FDRE #( + .INIT(1'b0)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[3] + (.C(s_axis_s2mm_aclk), + .CE(strm_all_lines_rcvd_no_dwidth), + .D(p_1_in[3]), + .Q(vsize_counter_no_dwidth[3]), + .R(\GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4 )); + FDRE #( + .INIT(1'b0)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[4] + (.C(s_axis_s2mm_aclk), + .CE(strm_all_lines_rcvd_no_dwidth), + .D(p_1_in[4]), + .Q(vsize_counter_no_dwidth[4]), + .R(\GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4 )); + CARRY4 \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[4]_i_2 + (.CI(1'b0), + .CO({\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[4]_i_2_n_0 ,\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[4]_i_2_n_1 ,\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[4]_i_2_n_2 ,\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[4]_i_2_n_3 }), + .CYINIT(vsize_counter_no_dwidth[0]), + .DI(vsize_counter_no_dwidth[4:1]), + .O(minusOp[4:1]), + .S({\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_3_n_0 ,\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_4_n_0 ,\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_5_n_0 ,\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_6_n_0 })); + FDRE #( + .INIT(1'b0)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[5] + (.C(s_axis_s2mm_aclk), + .CE(strm_all_lines_rcvd_no_dwidth), + .D(p_1_in[5]), + .Q(vsize_counter_no_dwidth[5]), + .R(\GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4 )); + FDRE #( + .INIT(1'b0)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] + (.C(s_axis_s2mm_aclk), + .CE(strm_all_lines_rcvd_no_dwidth), + .D(p_1_in[6]), + .Q(vsize_counter_no_dwidth[6]), + .R(\GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4 )); + FDRE #( + .INIT(1'b0)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[7] + (.C(s_axis_s2mm_aclk), + .CE(strm_all_lines_rcvd_no_dwidth), + .D(p_1_in[7]), + .Q(vsize_counter_no_dwidth[7]), + .R(\GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4 )); + FDRE #( + .INIT(1'b0)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[8] + (.C(s_axis_s2mm_aclk), + .CE(strm_all_lines_rcvd_no_dwidth), + .D(p_1_in[8]), + .Q(vsize_counter_no_dwidth[8]), + .R(\GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4 )); + CARRY4 \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[8]_i_2 + (.CI(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[4]_i_2_n_0 ), + .CO({\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[8]_i_2_n_0 ,\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[8]_i_2_n_1 ,\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[8]_i_2_n_2 ,\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[8]_i_2_n_3 }), + .CYINIT(1'b0), + .DI(vsize_counter_no_dwidth[8:5]), + .O(minusOp[8:5]), + .S({\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_3_n_0 ,\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_4_n_0 ,\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_5_n_0 ,\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_6_n_0 })); + FDRE #( + .INIT(1'b0)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[9] + (.C(s_axis_s2mm_aclk), + .CE(strm_all_lines_rcvd_no_dwidth), + .D(p_1_in[9]), + .Q(vsize_counter_no_dwidth[9]), + .R(\GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4 )); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_skid_buf__parameterized0 \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF + (.\GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_d1_reg (\GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_3 ), + .\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_reg (\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.GEN_FOR_ASYNC_FLUSH_SOF.SOF_LATE_CDC_I_n_2 ), + .\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_sof_late_err_reg (\GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_9 ), + .\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_tuser_to_fsync_out_reg (\GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_5 ), + .\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_tuser_to_fsync_out_reg_0 (\GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_8 ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_n_0 ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 (\GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I_n_20 ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_1 (\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.GEN_FOR_ASYNC_FLUSH_SOF.SOF_LATE_CDC_I_n_1 ), + .M_Data(p_94_out), + .M_Last(p_96_out), + .M_VALID(p_92_out), + .SR(\GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4 ), + .d_tready_before_fsync_clr_flag1(d_tready_before_fsync_clr_flag1), + .d_tready_sof_late(d_tready_sof_late), + .delay_s2mm_fsync_core_till_mmap_done_flag(delay_s2mm_fsync_core_till_mmap_done_flag), + .drop_fsync_d_pulse_gen_fsize_less_err(p_10_out), + .out(s2mm_axis_resetn), + .p_19_in(p_19_in), + .run_stop_reg(run_stop_reg), + .s2mm_fsize_less_err_flag_10(s2mm_fsize_less_err_flag_10), + .s2mm_fsize_more_or_sof_late_s(s2mm_fsize_more_or_sof_late_s), + .s2mm_fsync_out_i(s2mm_fsync_out_i), + .s2mm_tuser_to_fsync_out(s2mm_tuser_to_fsync_out), + .s_axis_fifo_ainit_nosync(s_axis_fifo_ainit_nosync), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk), + .s_axis_s2mm_tdata(s_axis_s2mm_tdata), + .s_axis_s2mm_tlast(s_axis_s2mm_tlast), + .s_axis_s2mm_tready(s_axis_s2mm_tready), + .s_axis_s2mm_tuser(s_axis_s2mm_tuser), + .s_axis_s2mm_tuser_d1(s_axis_s2mm_tuser_d1), + .s_axis_s2mm_tvalid(s_axis_s2mm_tvalid), + .sig_reset_reg(sig_reset_reg)); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_mngr__parameterized0 \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR + (.D(s2mm_axi2ip_wrdata[4]), + .\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] (s2mm_reg_module_stride), + .\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 (s2mm_frame_number), + .E(I_PRMRY_DATAMOVER_n_28), + .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 (s2mm_axis_resetn), + .\GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[2] (s2mm_s_frame_ptr_in), + .\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2] (s2mm_m_frame_ptr_out), + .\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg (\GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_15 ), + .\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_irqthresh_decr_mask_sig_reg (\GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_16 ), + .\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] (crnt_hsize), + .\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] (\s2mm_reg_module_strt_addr[0] ), + .\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] (\s2mm_reg_module_strt_addr[1] ), + .\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] (\s2mm_reg_module_strt_addr[2] ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg (\GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I_n_21 ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[0] (\GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_17 ), + .\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[4] (s2mm_chnl_current_frame), + .\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[4] (s2mm_genlock_pair_frame), + .\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_fsize_less_err_flag_10_reg (\GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_56 ), + .\GEN_STS_GRTR_THAN_8.undrflo_err_reg (\GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_54 ), + .\INFERRED_GEN.cnt_i_reg[2] (I_PRMRY_DATAMOVER_n_36), + .\INFERRED_GEN.cnt_i_reg[2]_0 (I_PRMRY_DATAMOVER_n_37), + .\INFERRED_GEN.cnt_i_reg[2]_1 (I_PRMRY_DATAMOVER_n_38), + .\INFERRED_GEN.cnt_i_reg[2]_2 (\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_rd_empty ), + .Q(s2mm_crnt_vsize), + .S(\GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_53 ), + .\S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg (\GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_60 ), + .\S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg_0 (\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_68 ), + .SR(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF/prmry_reset2 ), + .ch2_delay_cnt_en(ch2_delay_cnt_en), + .ch2_irqthresh_decr_mask_sig(ch2_irqthresh_decr_mask_sig), + .cmnd_wr(cmnd_wr_5), + .datamover_idle(\I_STS_MNGR/datamover_idle_3 ), + .dma_decerr_reg(\GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_59 ), + .dma_decerr_reg_0(\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_61 ), + .dma_err(dma_err_2), + .dma_slverr_reg(\GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_58 ), + .dma_slverr_reg_0(\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_60 ), + .drop_fsync_d_pulse_gen_fsize_less_err(p_10_out), + .drop_fsync_d_pulse_gen_fsize_less_err_d1(\I_SM/drop_fsync_d_pulse_gen_fsize_less_err_d1 ), + .err_i_reg(I_RST_MODULE_n_27), + .fsize_mismatch_err(s2mm_fsize_mismatch_err), + .fsize_mismatch_err_s1(\I_SM/fsize_mismatch_err_s1 ), + .halt_i0(\GEN_RESET_FOR_S2MM.RESET_I/halt_i0 ), + .halt_i_reg(I_RST_MODULE_n_22), + .halted_reg(\GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_57 ), + .halted_reg_0(\VIDEO_REG_I/p_1_out ), + .initial_frame(initial_frame_0), + .lsize_mismatch_err(s2mm_lsize_mismatch_err), + .lsize_more_mismatch_err(s2mm_lsize_more_mismatch_err), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .m_axis_s2mm_sts_tdata(m_axis_s2mm_sts_tdata), + .m_axis_s2mm_sts_tready(m_axis_s2mm_sts_tready), + .mask_fsync_out_i(mask_fsync_out_i_8), + .num_fstore_minus1(num_fstore_minus1), + .out(s2mm_prmry_resetn), + .p_12_out(\I_CMDSTS/p_12_out ), + .p_2_out(p_2_out_1), + .p_9_out(\I_CMDSTS/p_9_out ), + .prmry_reset2(\I_SM/GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF/prmry_reset2 ), + .prmry_resetn_i_reg(\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_71 ), + .prmry_resetn_i_reg_0(\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_88 ), + .prmtr_update_complete(prmtr_update_complete_4), + .prmtr_updt_complete_i_reg(\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_92 ), + .\ptr_ref_i_reg[4] (p_83_out), + .\reg_module_hsize_reg[15] (s2mm_reg_module_hsize), + .\reg_module_vsize_reg[12] (s2mm_reg_module_vsize), + .run_stop_d1(\GEN_RESET_FOR_S2MM.RESET_I/run_stop_d1 ), + .s2mm_axi2ip_wrce(s2mm_axi2ip_wrce[13]), + .s2mm_cdc2dmac_fsync(s2mm_cdc2dmac_fsync), + .s2mm_dma_interr_set_minus_frame_errors(s2mm_dma_interr_set_minus_frame_errors), + .s2mm_dmacr({s2mm_dmacr[15],s2mm_dmacr[3],s2mm_dmacr[1:0]}), + .s2mm_dmasr(s2mm_dmasr), + .s2mm_fsize_less_err_flag_10(s2mm_fsize_less_err_flag_10), + .s2mm_fsync_out_m_i(s2mm_fsync_out_m_i), + .s2mm_ftchcmdsts_idle(s2mm_ftchcmdsts_idle), + .s2mm_halt(s2mm_halt), + .s2mm_packet_sof(s2mm_packet_sof), + .s2mm_soft_reset(s2mm_soft_reset), + .s2mm_stop(s2mm_stop), + .s2mm_tstvect_fsync(s2mm_tstvect_fsync), + .s2mm_valid_frame_sync(s2mm_valid_frame_sync), + .s2mm_valid_frame_sync_cmb(s2mm_valid_frame_sync_cmb), + .s2mm_valid_video_prmtrs(s2mm_valid_video_prmtrs), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk), + .s_axis_s2mm_cmd_tvalid(s_axis_s2mm_cmd_tvalid), + .sig_halt_cmplt_reg(I_PRMRY_DATAMOVER_n_30), + .\sig_input_addr_reg_reg[31] ({s_axis_s2mm_cmd_tdata[63:32],s_axis_s2mm_cmd_tdata[23],s_axis_s2mm_cmd_tdata[15:0]}), + .\sig_user_reg_out_reg[0] (\GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_5 ), + .soft_reset_d1(\GEN_RESET_FOR_S2MM.RESET_I/soft_reset_d1 )); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_fsync_gen__parameterized0 \GEN_SPRT_FOR_S2MM.S2MM_FSYNC_I + (.\GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[4] (s2mm_dmacr[4]), + .Q(s2mm_irqthresh_status), + .SR(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF/prmry_reset2 ), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .mask_fsync_out_i(mask_fsync_out_i_8), + .p_2_out(p_2_out_1), + .p_4_out(p_4_out_6), + .p_in_d1_cdc_from(\GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/p_in_d1_cdc_from_13 ), + .prmry_in_xored(\GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/prmry_in_xored_7 ), + .prmry_resetn_i_reg(I_AXI_DMA_INTRPT_n_40), + .s2mm_cdc2dmac_fsync(s2mm_cdc2dmac_fsync), + .s2mm_valid_video_prmtrs(s2mm_valid_video_prmtrs)); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_s2mm_linebuf \GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I + (.D(p_1_in), + .DIN(p_94_out), + .DOUT({linebuf2dm_s2mm_tlast,linebuf2dm_s2mm_tdata}), + .EMPTY(fifo_empty_i), + .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 (\GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_3 ), + .\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg (\GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_17 ), + .\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_s1_reg (\GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I_n_21 ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg (\GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I_n_17 ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_n_0 ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg (\GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I_n_16 ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg_0 (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg_n_0 ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] (vsize_counter_no_dwidth[0]), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_4_n_0 ), + .M_Last(p_96_out), + .M_VALID(p_92_out), + .Q(s2mm_crnt_vsize), + .RD_EN(fifo_rden), + .SR(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF/prmry_reset2 ), + .delay_s2mm_fsync_core_till_mmap_done_flag(delay_s2mm_fsync_core_till_mmap_done_flag), + .drop_fsync_d_pulse_gen_fsize_less_err_d1(\I_SM/drop_fsync_d_pulse_gen_fsize_less_err_d1 ), + .fsize_mismatch_err_s1(\I_SM/fsize_mismatch_err_s1 ), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .minusOp(minusOp), + .out(s2mm_axis_resetn), + .p_in_d1_cdc_from(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF/p_in_d1_cdc_from ), + .prmry_in_xored(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF/prmry_in_xored ), + .prmry_reset2(\I_SM/GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF/prmry_reset2 ), + .run_stop_reg(run_stop_reg), + .s2mm_dmacr({s2mm_dmacr[6:5],s2mm_dmacr[0]}), + .s2mm_fsync_core(s2mm_fsync_core), + .s2mm_fsync_out_i(s2mm_fsync_out_i), + .s2mm_fsync_out_m_i(s2mm_fsync_out_m_i), + .s2mm_halt(s2mm_halt), + .s2mm_strm_wready(dm2linebuf_s2mm_tready), + .s_axis_fifo_ainit_nosync(s_axis_fifo_ainit_nosync), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk), + .s_valid0(s_valid0_9), + .sig_last_reg_out_reg(\GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I_n_20 ), + .sig_reset_reg(sig_reset_reg), + .\sig_user_reg_out_reg[0] (\GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_5 ), + .strm_not_finished_no_dwidth(strm_not_finished_no_dwidth)); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_module__parameterized0 \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I + (.D(s2mm_axi2ip_wrdata), + .\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] (\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_88 ), + .\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]_0 (s2mm_frame_number), + .\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg (\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_81 ), + .\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg (\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_82 ), + .\GEN_FOR_FLUSH.fsize_err_reg (\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_62 ), + .\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6] (\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_71 ), + .\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6]_0 (p_4_out_10), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[2] (AXI_LITE_REG_INTERFACE_I_n_162), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[11] (AXI_LITE_REG_INTERFACE_I_n_168), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[12] (AXI_LITE_REG_INTERFACE_I_n_169), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[13] (AXI_LITE_REG_INTERFACE_I_n_170), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[15] (AXI_LITE_REG_INTERFACE_I_n_171), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18] (AXI_LITE_REG_INTERFACE_I_n_128), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4] (AXI_LITE_REG_INTERFACE_I_n_165), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4]_0 (\GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_60 ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[7] (AXI_LITE_REG_INTERFACE_I_n_166), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[8] (AXI_LITE_REG_INTERFACE_I_n_167), + .\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] ({AXI_LITE_REG_INTERFACE_I_n_129,AXI_LITE_REG_INTERFACE_I_n_130,AXI_LITE_REG_INTERFACE_I_n_131,AXI_LITE_REG_INTERFACE_I_n_132,AXI_LITE_REG_INTERFACE_I_n_133,AXI_LITE_REG_INTERFACE_I_n_134,AXI_LITE_REG_INTERFACE_I_n_135,AXI_LITE_REG_INTERFACE_I_n_136,AXI_LITE_REG_INTERFACE_I_n_137,AXI_LITE_REG_INTERFACE_I_n_138,AXI_LITE_REG_INTERFACE_I_n_139,AXI_LITE_REG_INTERFACE_I_n_140,AXI_LITE_REG_INTERFACE_I_n_141,AXI_LITE_REG_INTERFACE_I_n_142,AXI_LITE_REG_INTERFACE_I_n_143,AXI_LITE_REG_INTERFACE_I_n_144,AXI_LITE_REG_INTERFACE_I_n_145,AXI_LITE_REG_INTERFACE_I_n_146,AXI_LITE_REG_INTERFACE_I_n_147,AXI_LITE_REG_INTERFACE_I_n_148,AXI_LITE_REG_INTERFACE_I_n_149,AXI_LITE_REG_INTERFACE_I_n_150,AXI_LITE_REG_INTERFACE_I_n_151,AXI_LITE_REG_INTERFACE_I_n_152,AXI_LITE_REG_INTERFACE_I_n_153,AXI_LITE_REG_INTERFACE_I_n_154,AXI_LITE_REG_INTERFACE_I_n_155,AXI_LITE_REG_INTERFACE_I_n_156,AXI_LITE_REG_INTERFACE_I_n_157,AXI_LITE_REG_INTERFACE_I_n_158,AXI_LITE_REG_INTERFACE_I_n_159,AXI_LITE_REG_INTERFACE_I_n_160}), + .\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg (\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_92 ), + .\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4] (p_83_out), + .\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4] (p_82_out), + .\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] (\s2mm_reg_module_strt_addr[0] ), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] (\s2mm_reg_module_strt_addr[1] ), + .\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] (\s2mm_reg_module_strt_addr[2] ), + .Q({\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_74 ,\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_75 ,\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_76 ,\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_77 ,\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_78 ,\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_79 ,\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_80 }), + .\S2MM_ERR_FOR_IRQ.frm_store_i_reg[0] (\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_59 ), + .\S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_0 (\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_60 ), + .\S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_1 (\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_61 ), + .\S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_2 (\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_63 ), + .\S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_3 (\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_67 ), + .SR(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF/prmry_reset2 ), + .ch2_delay_cnt_en(ch2_delay_cnt_en), + .ch2_delay_zero(ch2_delay_zero), + .ch2_dly_irq_set(s2mm_dly_irq_set), + .decerr_i_reg(\GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_59 ), + .dly_irq_reg(\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_66 ), + .\dmacr_i_reg[2] (I_RST_MODULE_n_19), + .err_d1_reg(\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_64 ), + .err_d1_reg_0(\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_68 ), + .err_d1_reg_1(dma_irq_mask_i), + .err_irq_reg(\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_87 ), + .halt_reset(\GEN_RESET_FOR_S2MM.RESET_I/halt_reset ), + .halted_clr_reg(\GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_57 ), + .\hsize_vid_reg[15] (s2mm_reg_module_hsize), + .initial_frame(initial_frame_0), + .ioc_irq_reg(\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_65 ), + .irqdelay_wren_i(\I_DMA_REGISTER/irqdelay_wren_i ), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .mask_fsync_out_i(mask_fsync_out_i_8), + .num_fstore_minus1(num_fstore_minus1), + .out(p_84_out), + .p_14_out(\I_DMA_REGISTER/p_14_out ), + .p_15_out(\I_DMA_REGISTER/p_15_out ), + .p_6_out(p_6_out), + .p_in_d1_cdc_from(p_in_d1_cdc_from), + .prmry_in(s2mm_ftchcmdsts_idle), + .prmry_in_xored(prmry_in_xored), + .prmry_resetn_i_reg(s2mm_prmry_resetn), + .prmtr_update_complete(prmtr_update_complete_4), + .reset_counts(\I_DMA_REGISTER/reset_counts_11 ), + .reset_counts_reg(I_RST_MODULE_n_32), + .s2mm_axi2ip_wrce({s2mm_axi2ip_wrce[45:40],s2mm_axi2ip_wrce[15],s2mm_axi2ip_wrce[13:12],s2mm_axi2ip_wrce[10]}), + .s2mm_cdc2dmac_fsync(s2mm_cdc2dmac_fsync), + .s2mm_dmacr({s2mm_dmacr[31:15],s2mm_dmacr[6:3],s2mm_dmacr[1:0]}), + .s2mm_dmasr(s2mm_dmasr), + .s2mm_halt_cmplt(s2mm_halt_cmplt), + .s2mm_ioc_irq_set(s2mm_ioc_irq_set), + .s2mm_ip2axi_introut(s2mm_ip2axi_introut), + .s2mm_packet_sof(s2mm_packet_sof), + .s2mm_soft_reset(s2mm_soft_reset), + .s2mm_stop(s2mm_stop), + .s2mm_tstvect_fsync(s2mm_tstvect_fsync), + .s2mm_valid_frame_sync(s2mm_valid_frame_sync), + .s2mm_valid_video_prmtrs(s2mm_valid_video_prmtrs), + .s_axis_cmd_tvalid_reg(\VIDEO_REG_I/p_1_out ), + .s_soft_reset_i0(\GEN_RESET_FOR_S2MM.RESET_I/s_soft_reset_i0 ), + .slverr_i_reg(\GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_58 ), + .\stride_vid_reg[15] (s2mm_reg_module_stride), + .\vsize_vid_reg[12] (s2mm_reg_module_vsize)); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_sof_gen_0 \GEN_SPRT_FOR_S2MM.S2MM_SOF_I + (.out(s2mm_axis_resetn), + .p_in_d1_cdc_from(\GEN_CDC_FOR_ASYNC.SOF_CDC_I/p_in_d1_cdc_from_14 ), + .prmry_in_xored(\GEN_CDC_FOR_ASYNC.SOF_CDC_I/prmry_in_xored_12 ), + .prmry_reset2(\I_SM/GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF/prmry_reset2 ), + .s2mm_fsync_out_i(s2mm_fsync_out_i), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk), + .s_valid0(s_valid0_9)); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_vid_cdc_1 \GEN_SPRT_FOR_S2MM.S2MM_VID_CDC_I + (.\DYNAMIC_GENLOCK_FOR_MASTER.frame_ptr_out_reg[2] (s2mm_m_frame_ptr_out), + .E(strm_all_lines_rcvd_no_dwidth), + .\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out (\GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I_n_17 ), + .\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[0] (\GEN_SPRT_FOR_S2MM.S2MM_VID_CDC_I_n_5 ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_4_n_0 ), + .M_Last(p_96_out), + .Q(vsize_counter_no_dwidth[0]), + .SR(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF/prmry_reset2 ), + .\frame_ptr_out_reg[2] (s2mm_s_frame_ptr_in), + .irqdelay_wren_i(\I_DMA_REGISTER/irqdelay_wren_i ), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .p_in_d1_cdc_from(\GEN_CDC_FOR_ASYNC.SOF_CDC_I/p_in_d1_cdc_from_14 ), + .p_in_d1_cdc_from_0(\GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/p_in_d1_cdc_from_13 ), + .p_in_d1_cdc_from_3(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF/p_in_d1_cdc_from ), + .prmry_in_xored(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF/prmry_in_xored ), + .prmry_in_xored_1(\GEN_CDC_FOR_ASYNC.SOF_CDC_I/prmry_in_xored_12 ), + .prmry_in_xored_2(\GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/prmry_in_xored_7 ), + .prmry_reset2(\I_SM/GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF/prmry_reset2 ), + .reset_counts(\I_DMA_REGISTER/reset_counts_11 ), + .s2mm_cdc2dmac_fsync(s2mm_cdc2dmac_fsync), + .s2mm_frame_ptr_in(s2mm_frame_ptr_in), + .s2mm_frame_ptr_out(s2mm_frame_ptr_out), + .s2mm_fsync_core(s2mm_fsync_core), + .s2mm_fsync_out_i(s2mm_fsync_out_i), + .s2mm_packet_sof(s2mm_packet_sof), + .s2mm_valid_frame_sync_cmb(s2mm_valid_frame_sync_cmb), + .s2mm_valid_video_prmtrs(s2mm_valid_video_prmtrs), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk)); + GND GND + (.G(\ )); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_intrpt I_AXI_DMA_INTRPT + (.E(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_72 ), + .\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_65 ), + .\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out_0 (\GEN_SPRT_FOR_S2MM.S2MM_VID_CDC_I_n_5 ), + .\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg (I_AXI_DMA_INTRPT_n_39), + .\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg (\GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_15 ), + .\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg_0 (\GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_16 ), + .\GEN_FSYNC_MODE_S2MM_FLUSH_SOF.mask_fsync_out_i_reg (I_AXI_DMA_INTRPT_n_40), + .\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_reg_0 (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_63 ), + .\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 (mm2s_irqthresh_status), + .\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0 (p_4_out_10), + .\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 (s2mm_irqdelay_status), + .\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 (s2mm_irqthresh_status), + .\MASTER_MODE_FRAME_CNT.tstvect_fsync_reg (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_62 ), + .Q(mm2s_irqdelay_status), + .SR(p_11_out), + .ch1_delay_cnt_en(ch1_delay_cnt_en), + .ch1_delay_zero(ch1_delay_zero), + .ch1_dly_irq_set(mm2s_dly_irq_set), + .ch2_delay_cnt_en(ch2_delay_cnt_en), + .ch2_delay_zero(ch2_delay_zero), + .ch2_dly_irq_set(s2mm_dly_irq_set), + .ch2_irqthresh_decr_mask_sig(ch2_irqthresh_decr_mask_sig), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .mask_fsync_out_i(mask_fsync_out_i), + .mask_fsync_out_i_1(mask_fsync_out_i_8), + .mm2s_ioc_irq_set(mm2s_ioc_irq_set), + .out(mm2s_prmry_resetn), + .p_13_out(p_13_out), + .p_17_out(p_17_out), + .p_4_out(p_4_out), + .p_4_out_0(p_4_out_6), + .p_50_out(p_50_out), + .p_6_out(p_6_out), + .p_71_out(p_71_out[31:16]), + .prmry_resetn_i_reg(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF/prmry_reset2 ), + .prmry_resetn_i_reg_0(s2mm_prmry_resetn), + .prmry_resetn_i_reg_1(\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_71 ), + .prmry_resetn_i_reg_2(\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I/prmry_reset2 ), + .s2mm_dmacr(s2mm_dmacr[31:16]), + .s2mm_ioc_irq_set(s2mm_ioc_irq_set), + .s2mm_packet_sof(s2mm_packet_sof), + .s2mm_tstvect_fsync(s2mm_tstvect_fsync)); + Arty_Z7_20_axi_vdma_0_0_axi_datamover I_PRMRY_DATAMOVER + (.CO(I_PRMRY_DATAMOVER_n_29), + .DI({\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_dre2ibtt_eop_reg ,\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_dre2ibtt_tlast_reg ,\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_byte_cntr }), + .DIN(dm2linebuf_mm2s_tlast), + .DOUT({linebuf2dm_s2mm_tlast,linebuf2dm_s2mm_tdata}), + .E(I_PRMRY_DATAMOVER_n_22), + .EMPTY(fifo_empty_i), + .FIFO_Full_reg(\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_rd_empty ), + .\GEN_STS_GRTR_THAN_8.ovrflo_err_reg (m_axis_s2mm_sts_tdata), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] (\GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_7 ), + .Q(\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_rd_empty ), + .RD_EN(fifo_rden), + .S(\GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_53 ), + .cmnd_wr(cmnd_wr), + .cmnd_wr_1(cmnd_wr_5), + .datamover_idle(\I_STS_MNGR/datamover_idle ), + .datamover_idle_2(\I_STS_MNGR/datamover_idle_3 ), + .datamover_idle_reg(I_PRMRY_DATAMOVER_n_23), + .datamover_idle_reg_0(I_PRMRY_DATAMOVER_n_30), + .decerr_i_reg(I_PRMRY_DATAMOVER_n_32), + .decerr_i_reg_0(I_PRMRY_DATAMOVER_n_36), + .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), + .dma_err(dma_err_2), + .\gcc0.gc0.count_d1_reg[0] (I_PRMRY_DATAMOVER_n_39), + .\gpr1.dout_i_reg[1] (\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_0_out ), + .\gpr1.dout_i_reg[1]_0 (\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_11_out ), + .halt_i_reg(I_RST_MODULE_n_30), + .halt_i_reg_0(I_RST_MODULE_n_33), + .\hsize_vid_reg[15] (crnt_hsize), + .\hsize_vid_reg[2] (\GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_54 ), + .in({p_57_out[63:32],p_57_out[23],p_57_out[15:0]}), + .interr_i_reg(I_PRMRY_DATAMOVER_n_35), + .interr_i_reg_0(I_PRMRY_DATAMOVER_n_38), + .lsig_0ffset_cntr(\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/lsig_0ffset_cntr ), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .m_axi_mm2s_araddr(m_axi_mm2s_araddr), + .m_axi_mm2s_arburst(\^m_axi_mm2s_arburst ), + .m_axi_mm2s_arlen(\^m_axi_mm2s_arlen ), + .m_axi_mm2s_arready(m_axi_mm2s_arready), + .m_axi_mm2s_arsize(\^m_axi_mm2s_arsize ), + .m_axi_mm2s_arvalid(m_axi_mm2s_arvalid), + .m_axi_mm2s_rdata(m_axi_mm2s_rdata), + .m_axi_mm2s_rlast(m_axi_mm2s_rlast), + .m_axi_mm2s_rready(m_axi_mm2s_rready), + .m_axi_mm2s_rresp(m_axi_mm2s_rresp), + .m_axi_mm2s_rvalid(m_axi_mm2s_rvalid), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .m_axi_s2mm_awaddr(m_axi_s2mm_awaddr), + .m_axi_s2mm_awburst(\^m_axi_s2mm_awburst ), + .m_axi_s2mm_awlen(\^m_axi_s2mm_awlen ), + .m_axi_s2mm_awready(m_axi_s2mm_awready), + .m_axi_s2mm_awsize(\^m_axi_s2mm_awsize ), + .m_axi_s2mm_awvalid(m_axi_s2mm_awvalid), + .m_axi_s2mm_bready(m_axi_s2mm_bready), + .m_axi_s2mm_bresp(m_axi_s2mm_bresp), + .m_axi_s2mm_bvalid(m_axi_s2mm_bvalid), + .m_axi_s2mm_wdata(m_axi_s2mm_wdata), + .m_axi_s2mm_wlast(m_axi_s2mm_wlast), + .m_axi_s2mm_wready(m_axi_s2mm_wready), + .m_axi_s2mm_wvalid(m_axi_s2mm_wvalid), + .m_axis_s2mm_sts_tready(m_axis_s2mm_sts_tready), + .mm2s_halt(mm2s_halt), + .mm2s_halt_cmplt(mm2s_halt_cmplt), + .out(mm2s_dm_prmry_resetn), + .p_0_out({\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_n_5 ,\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_n_2 ,\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_n_3 ,\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_n_0 ,\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_n_1 ,\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_4 ,\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_5 ,\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_2 ,\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_3 ,\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_0 ,\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_1 }), + .p_56_out(p_56_out), + .p_58_out(p_58_out), + .p_71_out(p_71_out[0]), + .p_9_out(\I_CMDSTS/p_9_out ), + .prmry_resetn_i_reg(\GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_8 ), + .s2mm_dmacr(s2mm_dmacr[0]), + .s2mm_halt(s2mm_halt), + .s2mm_halt_cmplt(s2mm_halt_cmplt), + .s2mm_soft_reset(s2mm_soft_reset), + .\s_axis_cmd_tdata_reg[63] ({s_axis_s2mm_cmd_tdata[63:32],s_axis_s2mm_cmd_tdata[23],s_axis_s2mm_cmd_tdata[15:0]}), + .s_axis_cmd_tvalid_reg(I_PRMRY_DATAMOVER_n_28), + .s_axis_s2mm_cmd_tvalid(s_axis_s2mm_cmd_tvalid), + .s_soft_reset_i_reg(s2mm_dm_prmry_resetn), + .\sig_data_skid_reg_reg[7] (dm2linebuf_s2mm_tready), + .sig_rst2all_stop_request(\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/sig_rst2all_stop_request ), + .sig_rst2all_stop_request_0(\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/sig_rst2all_stop_request ), + .\sig_user_skid_reg_reg[0] (I_PRMRY_DATAMOVER_n_191), + .slverr_i_reg(I_PRMRY_DATAMOVER_n_34), + .slverr_i_reg_0(I_PRMRY_DATAMOVER_n_37), + .sts_tready_reg(\GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_31 )); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_rst_module I_RST_MODULE + (.CO(I_PRMRY_DATAMOVER_n_29), + .D(mm2s_axi2ip_wrdata[2]), + .\FSM_sequential_dmacntrl_cs_reg[2] (I_RST_MODULE_n_22), + .FULL(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/p_5_out ), + .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 (\GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_3 ), + .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 (p_39_out), + .\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from (s2mm_axis_resetn), + .\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_0 (\GEN_CDC_FOR_ASYNC.PRMTR_UPDT_CDC_I/scndry_reset2 ), + .\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0] (\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I/prmry_reset2 ), + .\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[1] (\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF/prmry_reset2 ), + .\GEN_LINEBUF_NO_SOF.s_axis_fifo_ainit_nosync_reg_reg (I_RST_MODULE_n_29), + .\GEN_LINEBUF_NO_SOF.vsize_counter_reg[12] (mm2s_axis_resetn), + .\GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]_0 (p_7_out), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[2] (s2mm_axi2ip_wrdata[2]), + .\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_reg (I_RST_MODULE_n_28), + .Q(\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_rd_empty ), + .SR(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.S2MM_INTRPT_CROSSING_I/scndry_reset2 ), + .WR_EN(I_RST_MODULE_n_25), + .axi_resetn(axi_resetn), + .\cmnds_queued_reg[0] (s2mm_ftchcmdsts_idle), + .\cmnds_queued_reg[7] (I_RST_MODULE_n_26), + .\cmnds_queued_reg[7]_0 (I_RST_MODULE_n_27), + .d_tready_before_fsync(d_tready_before_fsync), + .d_tready_before_fsync_clr_flag1(d_tready_before_fsync_clr_flag1), + .dma_err(dma_err_2), + .dma_err_4(dma_err), + .\dmacr_i_reg[2] (I_RST_MODULE_n_16), + .\dmacr_i_reg[2]_0 (I_RST_MODULE_n_19), + .halt_i0(\GEN_RESET_FOR_S2MM.RESET_I/halt_i0 ), + .halt_reset(\GEN_RESET_FOR_MM2S.RESET_I/halt_reset ), + .halt_reset_2(\GEN_RESET_FOR_S2MM.RESET_I/halt_reset ), + .hold_ff_q_reg(I_PRMRY_DATAMOVER_n_191), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .m_axis_mm2s_aclk(m_axis_mm2s_aclk), + .mm2s_axi2ip_wrce(mm2s_axi2ip_wrce[0]), + .mm2s_halt(mm2s_halt), + .mm2s_halt_cmplt(mm2s_halt_cmplt), + .out(mm2s_prmry_resetn), + .p_12_out(\I_CMDSTS/p_12_out ), + .p_15_out(p_15_out), + .p_24_out(p_24_out), + .p_71_out(p_71_out[0]), + .p_77_out(p_77_out), + .prmry_in(s_axi_lite_resetn), + .prmry_reset2(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.MM2S_INTRPT_CROSSING_I/prmry_reset2 ), + .prmry_reset2_0(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.S2MM_INTRPT_CROSSING_I/prmry_reset2 ), + .prmry_reset2_1(\I_SM/GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF/prmry_reset2 ), + .reset_counts(\I_DMA_REGISTER/reset_counts ), + .reset_counts_5(\I_DMA_REGISTER/reset_counts_11 ), + .reset_counts_reg(I_RST_MODULE_n_31), + .reset_counts_reg_0(I_RST_MODULE_n_32), + .run_stop_d1(\GEN_RESET_FOR_S2MM.RESET_I/run_stop_d1 ), + .s2mm_axi2ip_wrce(s2mm_axi2ip_wrce[12]), + .s2mm_dmacr(s2mm_dmacr[0]), + .s2mm_dmasr_halted_s(s2mm_dmasr_halted_s), + .s2mm_halt(s2mm_halt), + .s2mm_halt_cmplt(s2mm_halt_cmplt), + .s2mm_soft_reset(s2mm_soft_reset), + .s2mm_stop(s2mm_stop), + .s_axi_lite_aclk(s_axi_lite_aclk), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk), + .s_soft_reset_i0(\GEN_RESET_FOR_MM2S.RESET_I/s_soft_reset_i0 ), + .s_soft_reset_i0_3(\GEN_RESET_FOR_S2MM.RESET_I/s_soft_reset_i0 ), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0(mm2s_dm_prmry_resetn), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0_0(s2mm_dm_prmry_resetn), + .sig_rst2all_stop_request(\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/sig_rst2all_stop_request ), + .sig_rst2all_stop_request_6(\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/sig_rst2all_stop_request ), + .sig_s_h_halt_reg_reg(I_RST_MODULE_n_30), + .sig_s_h_halt_reg_reg_0(I_RST_MODULE_n_33), + .sig_s_ready_out_reg(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/p_8_out ), + .soft_reset_d1(\GEN_RESET_FOR_S2MM.RESET_I/soft_reset_d1 ), + .stop(p_36_out), + .sts_tready_reg(s2mm_prmry_resetn)); + VCC VCC + (.P(\ )); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_afifo_builtin" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_afifo_builtin + (sig_m_valid_out_reg, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg , + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg , + FULL, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 , + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 , + fifo_dout, + m_axi_mm2s_aclk, + s_axis_fifo_ainit_nosync_reg, + m_axis_mm2s_aclk, + out, + lsig_0ffset_cntr, + mm2s_prmry_resetn, + mm2s_halt, + p_24_out, + hold_ff_q_reg, + DIN, + WR_EN, + dm2linebuf_mm2s_tdata); + output sig_m_valid_out_reg; + output \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; + output FULL; + output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ; + output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 ; + output [33:0]fifo_dout; + input m_axi_mm2s_aclk; + input s_axis_fifo_ainit_nosync_reg; + input m_axis_mm2s_aclk; + input out; + input lsig_0ffset_cntr; + input mm2s_prmry_resetn; + input mm2s_halt; + input p_24_out; + input hold_ff_q_reg; + input [15:0]DIN; + input WR_EN; + input [17:0]dm2linebuf_mm2s_tdata; + + wire [15:0]DIN; + wire FULL; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 ; + wire \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + wire WR_EN; + wire [17:0]dm2linebuf_mm2s_tdata; + wire [33:0]fifo_dout; + wire hold_ff_q_reg; + wire lsig_0ffset_cntr; + wire m_axi_mm2s_aclk; + wire m_axis_mm2s_aclk; + wire mm2s_halt; + wire mm2s_prmry_resetn; + wire out; + wire p_24_out; + wire s_axis_fifo_ainit_nosync_reg; + wire sig_m_valid_out_reg; + + Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3 fg_builtin_fifo_inst + (.DIN(DIN), + .FULL(FULL), + .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ), + .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ), + .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 ), + .\INCLUDE_UNPACKING.lsig_cmd_loaded_reg (\INCLUDE_UNPACKING.lsig_cmd_loaded_reg ), + .WR_EN(WR_EN), + .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), + .fifo_dout(fifo_dout), + .hold_ff_q_reg(hold_ff_q_reg), + .lsig_0ffset_cntr(lsig_0ffset_cntr), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .m_axis_mm2s_aclk(m_axis_mm2s_aclk), + .mm2s_halt(mm2s_halt), + .mm2s_prmry_resetn(mm2s_prmry_resetn), + .out(out), + .p_24_out(p_24_out), + .s_axis_fifo_ainit_nosync_reg(s_axis_fifo_ainit_nosync_reg), + .sig_m_valid_out_reg(sig_m_valid_out_reg)); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_afifo_builtin" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_afifo_builtin__parameterized0 + (FULL, + D, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] , + DOUT, + EMPTY, + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg , + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg , + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg , + strm_not_finished_no_dwidth, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] , + s_axis_s2mm_aclk, + sig_reset_reg, + m_axi_s2mm_aclk, + M_VALID, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 , + s2mm_fsync_out_i, + out, + p_3_out, + Q, + \vsize_vid_reg[12] , + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out , + minusOp_1, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 , + s2mm_strm_wready, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] , + DIN, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] , + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] , + minusOp, + RD_EN); + output FULL; + output [12:0]D; + output \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ; + output [8:0]DOUT; + output EMPTY; + output \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg ; + output \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg ; + output \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ; + output strm_not_finished_no_dwidth; + output [12:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] ; + input s_axis_s2mm_aclk; + input sig_reset_reg; + input m_axi_s2mm_aclk; + input M_VALID; + input \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ; + input s2mm_fsync_out_i; + input out; + input p_3_out; + input [6:0]Q; + input [12:0]\vsize_vid_reg[12] ; + input \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ; + input [11:0]minusOp_1; + input \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 ; + input s2mm_strm_wready; + input [0:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] ; + input [8:0]DIN; + input \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ; + input [12:0]\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] ; + input [11:0]minusOp; + input RD_EN; + + wire [12:0]D; + wire [8:0]DIN; + wire [8:0]DOUT; + wire EMPTY; + wire FULL; + wire \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ; + wire [12:0]\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg ; + wire [0:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] ; + wire [12:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ; + wire M_VALID; + wire [6:0]Q; + wire RD_EN; + wire m_axi_s2mm_aclk; + wire [11:0]minusOp; + wire [11:0]minusOp_1; + wire out; + wire p_3_out; + wire s2mm_fsync_out_i; + wire s2mm_strm_wready; + wire s_axis_s2mm_aclk; + wire sig_reset_reg; + wire strm_not_finished_no_dwidth; + wire [12:0]\vsize_vid_reg[12] ; + + Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized0 fg_builtin_fifo_inst + (.D(D), + .DIN(DIN), + .DOUT(DOUT), + .EMPTY(EMPTY), + .FULL(FULL), + .\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out (\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] (\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] (\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 (\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg (\GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ), + .M_VALID(M_VALID), + .Q(Q), + .RD_EN(RD_EN), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .minusOp(minusOp), + .minusOp_1(minusOp_1), + .out(out), + .p_3_out(p_3_out), + .s2mm_fsync_out_i(s2mm_fsync_out_i), + .s2mm_strm_wready(s2mm_strm_wready), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk), + .sig_reset_reg(sig_reset_reg), + .strm_not_finished_no_dwidth(strm_not_finished_no_dwidth), + .\vsize_vid_reg[12] (\vsize_vid_reg[12] )); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_cmdsts_if" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_cmdsts_if + (\cmnds_queued_reg[0] , + err_i_reg_0, + \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg , + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from , + stop_reg, + stop_i, + \INFERRED_GEN.cnt_i_reg[1] , + dma_slverr_reg, + dma_decerr_reg, + \sig_addr_cntr_lsh_kh_reg[31] , + mm2s_prmry_resetn, + m_axi_mm2s_aclk, + SR, + \INFERRED_GEN.cnt_i_reg[2] , + \INFERRED_GEN.cnt_i_reg[2]_0 , + \INFERRED_GEN.cnt_i_reg[2]_1 , + halted_reg, + E, + \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg_0 , + mm2s_halt, + p_71_out, + p_77_out, + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg , + frame_sync_reg, + \INFERRED_GEN.cnt_i_reg[2]_2 , + dma_slverr_reg_0, + dma_decerr_reg_0, + D, + zero_hsize_err, + zero_vsize_err); + output \cmnds_queued_reg[0] ; + output err_i_reg_0; + output \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg ; + output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ; + output stop_reg; + output stop_i; + output \INFERRED_GEN.cnt_i_reg[1] ; + output dma_slverr_reg; + output dma_decerr_reg; + output [48:0]\sig_addr_cntr_lsh_kh_reg[31] ; + input mm2s_prmry_resetn; + input m_axi_mm2s_aclk; + input [0:0]SR; + input \INFERRED_GEN.cnt_i_reg[2] ; + input \INFERRED_GEN.cnt_i_reg[2]_0 ; + input \INFERRED_GEN.cnt_i_reg[2]_1 ; + input [0:0]halted_reg; + input [0:0]E; + input \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg_0 ; + input mm2s_halt; + input [0:0]p_71_out; + input p_77_out; + input \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg ; + input frame_sync_reg; + input [0:0]\INFERRED_GEN.cnt_i_reg[2]_2 ; + input dma_slverr_reg_0; + input dma_decerr_reg_0; + input [48:0]D; + input zero_hsize_err; + input zero_vsize_err; + + wire [48:0]D; + wire [0:0]E; + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg_0 ; + wire \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg ; + wire \INFERRED_GEN.cnt_i_reg[1] ; + wire \INFERRED_GEN.cnt_i_reg[2] ; + wire \INFERRED_GEN.cnt_i_reg[2]_0 ; + wire \INFERRED_GEN.cnt_i_reg[2]_1 ; + wire [0:0]\INFERRED_GEN.cnt_i_reg[2]_2 ; + wire [0:0]SR; + wire \cmnds_queued_reg[0] ; + wire dma_decerr_reg; + wire dma_decerr_reg_0; + wire dma_slverr_reg; + wire dma_slverr_reg_0; + wire err_i_i_1_n_0; + wire err_i_reg_0; + wire frame_sync_reg; + wire [0:0]halted_reg; + wire m_axi_mm2s_aclk; + wire mm2s_halt; + wire mm2s_prmry_resetn; + wire p_54_out; + wire p_55_out; + wire [0:0]p_71_out; + wire p_77_out; + wire [48:0]\sig_addr_cntr_lsh_kh_reg[31] ; + wire stop_i; + wire stop_reg; + wire zero_hsize_err; + wire zero_vsize_err; + + LUT6 #( + .INIT(64'hFFFBFFFFFFFFFFFF)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_6 + (.I0(mm2s_halt), + .I1(p_71_out), + .I2(stop_reg), + .I3(p_77_out), + .I4(\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg ), + .I5(frame_sync_reg), + .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from )); + LUT2 #( + .INIT(4'h2)) + \INFERRED_GEN.cnt_i[1]_i_2__1 + (.I0(\cmnds_queued_reg[0] ), + .I1(\INFERRED_GEN.cnt_i_reg[2]_2 ), + .O(\INFERRED_GEN.cnt_i_reg[1] )); + LUT2 #( + .INIT(4'hE)) + \I_DMA_REGISTER/dma_decerr_i_1 + (.I0(p_55_out), + .I1(dma_decerr_reg_0), + .O(dma_decerr_reg)); + LUT2 #( + .INIT(4'hE)) + \I_DMA_REGISTER/dma_slverr_i_1 + (.I0(p_54_out), + .I1(dma_slverr_reg_0), + .O(dma_slverr_reg)); + FDRE #( + .INIT(1'b0)) + decerr_i_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\INFERRED_GEN.cnt_i_reg[2] ), + .Q(p_55_out), + .R(SR)); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + err_i_i_1 + (.I0(p_54_out), + .I1(zero_hsize_err), + .I2(zero_vsize_err), + .I3(err_i_reg_0), + .I4(p_55_out), + .I5(stop_reg), + .O(err_i_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + err_i_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(err_i_i_1_n_0), + .Q(stop_reg), + .R(SR)); + FDRE #( + .INIT(1'b0)) + interr_i_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\INFERRED_GEN.cnt_i_reg[2]_1 ), + .Q(err_i_reg_0), + .R(SR)); + FDRE \s_axis_cmd_tdata_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[0]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [0]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[10] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[10]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [10]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[11] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[11]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [11]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[12] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[12]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [12]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[13] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[13]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [13]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[14] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[14]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [14]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[15] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[15]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [15]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[1]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [1]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[23] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[16]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [16]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[2]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [2]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[32] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[17]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [17]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[33] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[18]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [18]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[34] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[19]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [19]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[35] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[20]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [20]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[36] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[21]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [21]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[37] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[22]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [22]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[38] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[23]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [23]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[39] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[24]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [24]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[3]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [3]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[40] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[25]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [25]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[41] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[26]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [26]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[42] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[27]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [27]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[43] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[28]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [28]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[44] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[29]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [29]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[45] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[30]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [30]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[46] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[31]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [31]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[47] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[32]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [32]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[48] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[33]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [33]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[49] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[34]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [34]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[4]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [4]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[50] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[35]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [35]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[51] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[36]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [36]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[52] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[37]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [37]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[53] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[38]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [38]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[54] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[39]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [39]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[55] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[40]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [40]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[56] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[41]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [41]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[57] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[42]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [42]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[58] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[43]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [43]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[59] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[44]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [44]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[5]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [5]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[60] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[45]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [45]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[61] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[46]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [46]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[62] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[47]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [47]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[63] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[48]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [48]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[6] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[6]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [6]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[7]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [7]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[8] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[8]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [8]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[9] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(D[9]), + .Q(\sig_addr_cntr_lsh_kh_reg[31] [9]), + .R(halted_reg)); + FDRE s_axis_cmd_tvalid_reg + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg_0 ), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg ), + .R(halted_reg)); + FDRE #( + .INIT(1'b0)) + slverr_i_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\INFERRED_GEN.cnt_i_reg[2]_0 ), + .Q(p_54_out), + .R(SR)); + LUT2 #( + .INIT(4'hE)) + stop_i_1 + (.I0(stop_reg), + .I1(p_77_out), + .O(stop_i)); + FDRE #( + .INIT(1'b0)) + sts_tready_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(mm2s_prmry_resetn), + .Q(\cmnds_queued_reg[0] ), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_cmdsts_if" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_cmdsts_if__parameterized0 + (m_axis_s2mm_sts_tready, + err_i_reg_0, + lsize_mismatch_err, + lsize_more_mismatch_err, + \vert_count_reg[0] , + \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr_reg[4] , + stop_i, + stop_reg, + \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_reg , + dma_slverr_reg, + dma_decerr_reg, + \sig_input_addr_reg_reg[31] , + out, + m_axi_s2mm_aclk, + SR, + \INFERRED_GEN.cnt_i_reg[2] , + \INFERRED_GEN.cnt_i_reg[2]_0 , + \INFERRED_GEN.cnt_i_reg[2]_1 , + p_12_out, + p_9_out, + halted_reg, + E, + \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg , + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out , + flag_to_repeat_after_fsize_less_err, + s2mm_soft_reset, + repeat_frame, + valid_frame_sync_d2, + dma_slverr_reg_0, + dma_decerr_reg_0, + D, + zero_vsize_err, + zero_hsize_err); + output m_axis_s2mm_sts_tready; + output err_i_reg_0; + output lsize_mismatch_err; + output lsize_more_mismatch_err; + output \vert_count_reg[0] ; + output [0:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr_reg[4] ; + output stop_i; + output stop_reg; + output \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_reg ; + output dma_slverr_reg; + output dma_decerr_reg; + output [48:0]\sig_input_addr_reg_reg[31] ; + input out; + input m_axi_s2mm_aclk; + input [0:0]SR; + input \INFERRED_GEN.cnt_i_reg[2] ; + input \INFERRED_GEN.cnt_i_reg[2]_0 ; + input \INFERRED_GEN.cnt_i_reg[2]_1 ; + input p_12_out; + input p_9_out; + input [0:0]halted_reg; + input [0:0]E; + input \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg ; + input \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ; + input flag_to_repeat_after_fsize_less_err; + input s2mm_soft_reset; + input repeat_frame; + input valid_frame_sync_d2; + input dma_slverr_reg_0; + input dma_decerr_reg_0; + input [48:0]D; + input zero_vsize_err; + input zero_hsize_err; + + wire [48:0]D; + wire [0:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr_reg[4] ; + wire \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_reg ; + wire [0:0]E; + wire \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg ; + wire \INFERRED_GEN.cnt_i_reg[2] ; + wire \INFERRED_GEN.cnt_i_reg[2]_0 ; + wire \INFERRED_GEN.cnt_i_reg[2]_1 ; + wire [0:0]SR; + wire dma_decerr_reg; + wire dma_decerr_reg_0; + wire dma_slverr_reg; + wire dma_slverr_reg_0; + wire err_i_i_1__0_n_0; + wire err_i_reg_0; + wire flag_to_repeat_after_fsize_less_err; + wire [0:0]halted_reg; + wire lsize_mismatch_err; + wire lsize_more_mismatch_err; + wire m_axi_s2mm_aclk; + wire m_axis_s2mm_sts_tready; + wire out; + wire p_12_out; + wire p_9_out; + wire repeat_frame; + wire s2mm_dma_decerr_set; + wire s2mm_dma_slverr_set; + wire s2mm_soft_reset; + wire [48:0]\sig_input_addr_reg_reg[31] ; + wire stop_i; + wire stop_reg; + wire valid_frame_sync_d2; + wire \vert_count_reg[0] ; + wire zero_hsize_err; + wire zero_vsize_err; + + LUT5 #( + .INIT(32'hE0E000E0)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_i_1 + (.I0(repeat_frame), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr_reg[4] ), + .I2(out), + .I3(valid_frame_sync_d2), + .I4(flag_to_repeat_after_fsize_less_err), + .O(\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_reg )); + LUT4 #( + .INIT(16'hFFFE)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr[4]_i_2 + (.I0(\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ), + .I1(flag_to_repeat_after_fsize_less_err), + .I2(lsize_mismatch_err), + .I3(lsize_more_mismatch_err), + .O(\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr_reg[4] )); + FDRE #( + .INIT(1'b0)) + \GEN_STS_GRTR_THAN_8.ovrflo_err_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(p_9_out), + .Q(lsize_more_mismatch_err), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_STS_GRTR_THAN_8.undrflo_err_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(p_12_out), + .Q(lsize_mismatch_err), + .R(SR)); + LUT2 #( + .INIT(4'hE)) + \I_DMA_REGISTER/dma_decerr_i_1__0 + (.I0(s2mm_dma_decerr_set), + .I1(dma_decerr_reg_0), + .O(dma_decerr_reg)); + LUT2 #( + .INIT(4'hE)) + \I_DMA_REGISTER/dma_slverr_i_1__0 + (.I0(s2mm_dma_slverr_set), + .I1(dma_slverr_reg_0), + .O(dma_slverr_reg)); + FDRE #( + .INIT(1'b0)) + decerr_i_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\INFERRED_GEN.cnt_i_reg[2] ), + .Q(s2mm_dma_decerr_set), + .R(SR)); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + err_i_i_1__0 + (.I0(s2mm_dma_decerr_set), + .I1(s2mm_dma_slverr_set), + .I2(err_i_reg_0), + .I3(zero_vsize_err), + .I4(zero_hsize_err), + .I5(stop_reg), + .O(err_i_i_1__0_n_0)); + FDRE #( + .INIT(1'b0)) + err_i_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(err_i_i_1__0_n_0), + .Q(stop_reg), + .R(SR)); + FDRE #( + .INIT(1'b0)) + interr_i_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\INFERRED_GEN.cnt_i_reg[2]_1 ), + .Q(err_i_reg_0), + .R(SR)); + FDRE \s_axis_cmd_tdata_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[0]), + .Q(\sig_input_addr_reg_reg[31] [0]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[10]), + .Q(\sig_input_addr_reg_reg[31] [10]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[11]), + .Q(\sig_input_addr_reg_reg[31] [11]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[12]), + .Q(\sig_input_addr_reg_reg[31] [12]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[13] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[13]), + .Q(\sig_input_addr_reg_reg[31] [13]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[14] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[14]), + .Q(\sig_input_addr_reg_reg[31] [14]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[15] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[15]), + .Q(\sig_input_addr_reg_reg[31] [15]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[1]), + .Q(\sig_input_addr_reg_reg[31] [1]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[23] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[16]), + .Q(\sig_input_addr_reg_reg[31] [16]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[2]), + .Q(\sig_input_addr_reg_reg[31] [2]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[32] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[17]), + .Q(\sig_input_addr_reg_reg[31] [17]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[33] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[18]), + .Q(\sig_input_addr_reg_reg[31] [18]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[34] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[19]), + .Q(\sig_input_addr_reg_reg[31] [19]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[35] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[20]), + .Q(\sig_input_addr_reg_reg[31] [20]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[36] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[21]), + .Q(\sig_input_addr_reg_reg[31] [21]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[37] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[22]), + .Q(\sig_input_addr_reg_reg[31] [22]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[38] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[23]), + .Q(\sig_input_addr_reg_reg[31] [23]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[39] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[24]), + .Q(\sig_input_addr_reg_reg[31] [24]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[3]), + .Q(\sig_input_addr_reg_reg[31] [3]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[40] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[25]), + .Q(\sig_input_addr_reg_reg[31] [25]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[41] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[26]), + .Q(\sig_input_addr_reg_reg[31] [26]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[42] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[27]), + .Q(\sig_input_addr_reg_reg[31] [27]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[43] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[28]), + .Q(\sig_input_addr_reg_reg[31] [28]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[44] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[29]), + .Q(\sig_input_addr_reg_reg[31] [29]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[45] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[30]), + .Q(\sig_input_addr_reg_reg[31] [30]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[46] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[31]), + .Q(\sig_input_addr_reg_reg[31] [31]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[47] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[32]), + .Q(\sig_input_addr_reg_reg[31] [32]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[48] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[33]), + .Q(\sig_input_addr_reg_reg[31] [33]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[49] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[34]), + .Q(\sig_input_addr_reg_reg[31] [34]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[4]), + .Q(\sig_input_addr_reg_reg[31] [4]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[50] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[35]), + .Q(\sig_input_addr_reg_reg[31] [35]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[51] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[36]), + .Q(\sig_input_addr_reg_reg[31] [36]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[52] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[37]), + .Q(\sig_input_addr_reg_reg[31] [37]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[53] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[38]), + .Q(\sig_input_addr_reg_reg[31] [38]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[54] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[39]), + .Q(\sig_input_addr_reg_reg[31] [39]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[55] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[40]), + .Q(\sig_input_addr_reg_reg[31] [40]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[56] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[41]), + .Q(\sig_input_addr_reg_reg[31] [41]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[57] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[42]), + .Q(\sig_input_addr_reg_reg[31] [42]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[58] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[43]), + .Q(\sig_input_addr_reg_reg[31] [43]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[59] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[44]), + .Q(\sig_input_addr_reg_reg[31] [44]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[5]), + .Q(\sig_input_addr_reg_reg[31] [5]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[60] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[45]), + .Q(\sig_input_addr_reg_reg[31] [45]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[61] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[46]), + .Q(\sig_input_addr_reg_reg[31] [46]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[62] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[47]), + .Q(\sig_input_addr_reg_reg[31] [47]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[63] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[48]), + .Q(\sig_input_addr_reg_reg[31] [48]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[6]), + .Q(\sig_input_addr_reg_reg[31] [6]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[7]), + .Q(\sig_input_addr_reg_reg[31] [7]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[8]), + .Q(\sig_input_addr_reg_reg[31] [8]), + .R(halted_reg)); + FDRE \s_axis_cmd_tdata_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(D[9]), + .Q(\sig_input_addr_reg_reg[31] [9]), + .R(halted_reg)); + FDRE s_axis_cmd_tvalid_reg + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg ), + .Q(\vert_count_reg[0] ), + .R(halted_reg)); + FDRE #( + .INIT(1'b0)) + slverr_i_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\INFERRED_GEN.cnt_i_reg[2]_0 ), + .Q(s2mm_dma_slverr_set), + .R(SR)); + LUT2 #( + .INIT(4'hE)) + stop_i_1__0 + (.I0(stop_reg), + .I1(s2mm_soft_reset), + .O(stop_i)); + FDRE #( + .INIT(1'b0)) + sts_tready_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(out), + .Q(m_axis_s2mm_sts_tready), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_fsync_gen" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_fsync_gen + (p_24_out, + mask_fsync_out_i, + p_46_out, + prmry_in_xored, + p_4_out, + p_71_out, + SR, + p_37_out, + m_axi_mm2s_aclk, + p_2_out, + prmry_resetn_i_reg, + p_47_out, + p_in_d1_cdc_from, + Q); + output p_24_out; + output mask_fsync_out_i; + output p_46_out; + output prmry_in_xored; + output p_4_out; + input [1:0]p_71_out; + input [0:0]SR; + input p_37_out; + input m_axi_mm2s_aclk; + input p_2_out; + input prmry_resetn_i_reg; + input p_47_out; + input p_in_d1_cdc_from; + input [7:0]Q; + + wire \GEN_FREE_RUN_MODE.mask_fsync_out_i_i_3_n_0 ; + wire [7:0]Q; + wire [0:0]SR; + wire all_idle_d1; + wire all_idle_d2; + wire m_axi_mm2s_aclk; + wire mask_fsync_out_i; + wire p_23_out; + wire p_24_out; + wire p_2_out; + wire p_37_out; + wire p_46_out; + wire p_47_out; + wire p_4_out; + wire [1:0]p_71_out; + wire p_8_out__0; + wire p_in_d1_cdc_from; + wire prmry_in_xored; + wire prmry_resetn_i_reg; + + LUT2 #( + .INIT(4'h6)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__13 + (.I0(p_23_out), + .I1(p_in_d1_cdc_from), + .O(prmry_in_xored)); + FDRE #( + .INIT(1'b0)) + \GEN_FREE_RUN_MODE.all_idle_d1_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(p_37_out), + .Q(all_idle_d1), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_FREE_RUN_MODE.all_idle_d2_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(all_idle_d1), + .Q(all_idle_d2), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_FREE_RUN_MODE.frame_sync_i_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(p_8_out__0), + .Q(p_24_out), + .R(SR)); + FDRE \GEN_FREE_RUN_MODE.frame_sync_out_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(p_2_out), + .Q(p_23_out), + .R(SR)); + LUT6 #( + .INIT(64'h0000000000000010)) + \GEN_FREE_RUN_MODE.mask_fsync_out_i_i_2 + (.I0(Q[6]), + .I1(Q[4]), + .I2(\GEN_FREE_RUN_MODE.mask_fsync_out_i_i_3_n_0 ), + .I3(Q[3]), + .I4(Q[5]), + .I5(Q[7]), + .O(p_4_out)); + LUT6 #( + .INIT(64'h0000000000008000)) + \GEN_FREE_RUN_MODE.mask_fsync_out_i_i_3 + (.I0(Q[0]), + .I1(p_71_out[1]), + .I2(p_24_out), + .I3(p_47_out), + .I4(Q[1]), + .I5(Q[2]), + .O(\GEN_FREE_RUN_MODE.mask_fsync_out_i_i_3_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_FREE_RUN_MODE.mask_fsync_out_i_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(prmry_resetn_i_reg), + .Q(mask_fsync_out_i), + .R(1'b0)); + LUT2 #( + .INIT(4'h8)) + \MASTER_MODE_FRAME_CNT.valid_frame_sync_d1_i_1 + (.I0(p_24_out), + .I1(p_47_out), + .O(p_46_out)); + LUT3 #( + .INIT(8'h40)) + p_8_out + (.I0(all_idle_d2), + .I1(all_idle_d1), + .I2(p_71_out[0]), + .O(p_8_out__0)); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_fsync_gen" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_fsync_gen__parameterized0 + (mask_fsync_out_i, + prmry_in_xored, + p_4_out, + SR, + p_2_out, + m_axi_s2mm_aclk, + prmry_resetn_i_reg, + p_in_d1_cdc_from, + Q, + \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[4] , + s2mm_cdc2dmac_fsync, + s2mm_valid_video_prmtrs); + output mask_fsync_out_i; + output prmry_in_xored; + output p_4_out; + input [0:0]SR; + input p_2_out; + input m_axi_s2mm_aclk; + input prmry_resetn_i_reg; + input p_in_d1_cdc_from; + input [7:0]Q; + input [0:0]\GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[4] ; + input s2mm_cdc2dmac_fsync; + input s2mm_valid_video_prmtrs; + + wire \GEN_FSYNC_MODE_S2MM_FLUSH_SOF.mask_fsync_out_i_i_3_n_0 ; + wire [0:0]\GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[4] ; + wire [7:0]Q; + wire [0:0]SR; + wire m_axi_s2mm_aclk; + wire mask_fsync_out_i; + wire p_2_out; + wire p_4_out; + wire p_in_d1_cdc_from; + wire prmry_in_xored; + wire prmry_resetn_i_reg; + wire s2mm_cdc2dmac_fsync; + wire s2mm_dmac2cdc_fsync_out; + wire s2mm_valid_video_prmtrs; + + LUT2 #( + .INIT(4'h6)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__14 + (.I0(s2mm_dmac2cdc_fsync_out), + .I1(p_in_d1_cdc_from), + .O(prmry_in_xored)); + FDRE \GEN_FSYNC_MODE_S2MM_FLUSH_SOF.frame_sync_out_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(p_2_out), + .Q(s2mm_dmac2cdc_fsync_out), + .R(SR)); + LUT6 #( + .INIT(64'h0000000000000010)) + \GEN_FSYNC_MODE_S2MM_FLUSH_SOF.mask_fsync_out_i_i_2 + (.I0(Q[6]), + .I1(Q[4]), + .I2(\GEN_FSYNC_MODE_S2MM_FLUSH_SOF.mask_fsync_out_i_i_3_n_0 ), + .I3(Q[3]), + .I4(Q[5]), + .I5(Q[7]), + .O(p_4_out)); + LUT6 #( + .INIT(64'h0000000000008000)) + \GEN_FSYNC_MODE_S2MM_FLUSH_SOF.mask_fsync_out_i_i_3 + (.I0(Q[0]), + .I1(\GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[4] ), + .I2(s2mm_cdc2dmac_fsync), + .I3(s2mm_valid_video_prmtrs), + .I4(Q[1]), + .I5(Q[2]), + .O(\GEN_FSYNC_MODE_S2MM_FLUSH_SOF.mask_fsync_out_i_i_3_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_FSYNC_MODE_S2MM_FLUSH_SOF.mask_fsync_out_i_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(prmry_resetn_i_reg), + .Q(mask_fsync_out_i), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_genlock_mngr" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_genlock_mngr + (p_45_out, + \GENLOCK_FOR_MASTER.mstr_reverse_order_reg_0 , + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2] , + SR, + valid_frame_sync_d2, + m_axi_mm2s_aclk, + Q, + num_fstore_minus1, + p_71_out, + mm2s_prmry_resetn, + p_70_out); + output p_45_out; + output \GENLOCK_FOR_MASTER.mstr_reverse_order_reg_0 ; + output [2:0]\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2] ; + input [0:0]SR; + input valid_frame_sync_d2; + input m_axi_mm2s_aclk; + input [4:0]Q; + input [0:0]num_fstore_minus1; + input [0:0]p_71_out; + input mm2s_prmry_resetn; + input p_70_out; + + wire \GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.binary_frame_ptr[0]_i_1_n_0 ; + wire \GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg[1]_inv_n_0 ; + wire \GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg_n_0_[0] ; + wire \GENLOCK_FOR_MASTER.frame_ptr_out[2]_i_1_n_0 ; + wire \GENLOCK_FOR_MASTER.mstr_reverse_order_i_1_n_0 ; + wire \GENLOCK_FOR_MASTER.mstr_reverse_order_reg_0 ; + wire [2:0]\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2] ; + wire \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_6_n_0 ; + wire [4:0]Q; + wire [0:0]SR; + wire [2:0]binary_frame_ptr; + wire [2:2]data0; + wire m_axi_mm2s_aclk; + wire mm2s_prmry_resetn; + wire mstr_reverse_order; + wire mstr_reverse_order_d1; + wire mstr_reverse_order_d2; + wire [0:0]num_fstore_minus1; + wire [1:0]p_0_out; + wire p_45_out; + wire p_70_out; + wire [0:0]p_71_out; + wire [2:1]raw_frame_ptr; + wire valid_frame_sync_d2; + + Arty_Z7_20_axi_vdma_0_0_axi_vdma_greycoder_45 \GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.GREY_CODER_I + (.D(p_0_out), + .Q(binary_frame_ptr)); + LUT1 #( + .INIT(2'h1)) + \GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.binary_frame_ptr[0]_i_1 + (.I0(\GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg_n_0_[0] ), + .O(\GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.binary_frame_ptr[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.binary_frame_ptr_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.binary_frame_ptr[0]_i_1_n_0 ), + .Q(binary_frame_ptr[0]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.binary_frame_ptr_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg[1]_inv_n_0 ), + .Q(binary_frame_ptr[1]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.binary_frame_ptr_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(data0), + .Q(binary_frame_ptr[2]), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair41" *) + LUT4 #( + .INIT(16'h40BF)) + \GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr[1]_inv_i_1 + (.I0(Q[0]), + .I1(mstr_reverse_order), + .I2(num_fstore_minus1), + .I3(Q[1]), + .O(raw_frame_ptr[1])); + LUT5 #( + .INIT(32'h7FFF8000)) + \GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr[2]_i_1 + (.I0(Q[1]), + .I1(Q[0]), + .I2(mstr_reverse_order), + .I3(num_fstore_minus1), + .I4(Q[2]), + .O(raw_frame_ptr[2])); + FDRE #( + .INIT(1'b0)) + \GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(Q[0]), + .Q(\GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg_n_0_[0] ), + .R(SR)); + FDSE #( + .INIT(1'b1)) + \GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg[1]_inv + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(raw_frame_ptr[1]), + .Q(\GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg[1]_inv_n_0 ), + .S(SR)); + FDRE #( + .INIT(1'b0)) + \GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(raw_frame_ptr[2]), + .Q(data0), + .R(SR)); + LUT1 #( + .INIT(2'h1)) + \GENLOCK_FOR_MASTER.frame_ptr_out[2]_i_1 + (.I0(mstr_reverse_order_d2), + .O(\GENLOCK_FOR_MASTER.frame_ptr_out[2]_i_1_n_0 )); + FDRE \GENLOCK_FOR_MASTER.frame_ptr_out_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(p_0_out[0]), + .Q(\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2] [0]), + .R(SR)); + FDRE \GENLOCK_FOR_MASTER.frame_ptr_out_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(p_0_out[1]), + .Q(\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2] [1]), + .R(SR)); + FDRE \GENLOCK_FOR_MASTER.frame_ptr_out_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GENLOCK_FOR_MASTER.frame_ptr_out[2]_i_1_n_0 ), + .Q(\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2] [2]), + .R(SR)); + FDSE #( + .INIT(1'b0)) + \GENLOCK_FOR_MASTER.mstr_reverse_order_d1_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(mstr_reverse_order), + .Q(mstr_reverse_order_d1), + .S(SR)); + FDSE #( + .INIT(1'b0)) + \GENLOCK_FOR_MASTER.mstr_reverse_order_d2_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(mstr_reverse_order_d1), + .Q(mstr_reverse_order_d2), + .S(SR)); + LUT5 #( + .INIT(32'hFFFF6AFF)) + \GENLOCK_FOR_MASTER.mstr_reverse_order_i_1 + (.I0(mstr_reverse_order), + .I1(p_71_out), + .I2(\GENLOCK_FOR_MASTER.mstr_reverse_order_reg_0 ), + .I3(mm2s_prmry_resetn), + .I4(p_70_out), + .O(\GENLOCK_FOR_MASTER.mstr_reverse_order_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GENLOCK_FOR_MASTER.mstr_reverse_order_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GENLOCK_FOR_MASTER.mstr_reverse_order_i_1_n_0 ), + .Q(mstr_reverse_order), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GENLOCK_FOR_MASTER.mstrfrm_tstsync_d1_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(valid_frame_sync_d2), + .Q(p_45_out), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair41" *) + LUT3 #( + .INIT(8'h09)) + \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_4 + (.I0(Q[1]), + .I1(num_fstore_minus1), + .I2(\MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_6_n_0 ), + .O(\GENLOCK_FOR_MASTER.mstr_reverse_order_reg_0 )); + LUT5 #( + .INIT(32'hFFFFFEFF)) + \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_6 + (.I0(Q[4]), + .I1(Q[0]), + .I2(Q[3]), + .I3(valid_frame_sync_d2), + .I4(Q[2]), + .O(\MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_6_n_0 )); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_genlock_mngr" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_genlock_mngr__parameterized0 + (s2mm_valid_frame_sync, + D, + slv_frame_ref_out, + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2] , + SR, + m_axi_s2mm_aclk, + valid_frame_sync_d2, + Q, + \ptr_ref_i_reg[4] , + \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_reg , + s2mm_dmacr, + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] , + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] , + \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[2] , + \num_fstore_minus1_reg[1] , + \DYNAMIC_MASTER_MODE_FRAME_CNT.valid_frame_sync_d2_reg , + \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[0] , + out, + s2mm_dmasr, + \GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[2] ); + output s2mm_valid_frame_sync; + output [4:0]D; + output [2:0]slv_frame_ref_out; + output [2:0]\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2] ; + input [0:0]SR; + input m_axi_s2mm_aclk; + input valid_frame_sync_d2; + input [4:0]Q; + input [4:0]\ptr_ref_i_reg[4] ; + input \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_reg ; + input [1:0]s2mm_dmacr; + input [4:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] ; + input \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] ; + input [2:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[2] ; + input \num_fstore_minus1_reg[1] ; + input \DYNAMIC_MASTER_MODE_FRAME_CNT.valid_frame_sync_d2_reg ; + input \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[0] ; + input out; + input [0:0]s2mm_dmasr; + input [2:0]\GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[2] ; + + wire [4:0]D; + wire \DYNAMIC_GENLOCK_FOR_MASTER.GENLOCK_MUX_I_n_2 ; + wire \DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.binary_frame_ptr[0]_i_1_n_0 ; + wire \DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg[1]_inv_n_0 ; + wire \DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg_n_0_[0] ; + wire \DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg_n_0_[2] ; + wire \DYNAMIC_GENLOCK_FOR_MASTER.frame_ptr_out[2]_i_1_n_0 ; + wire \DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_i_1_n_0 ; + wire \DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out[0]_i_1_n_0 ; + wire \DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out[1]_i_1_n_0 ; + wire \DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out[3]_i_1_n_0 ; + wire \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[0]_i_2_n_0 ; + wire \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[0]_i_3_n_0 ; + wire \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[1]_i_2_n_0 ; + wire \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[2]_i_2_n_0 ; + wire \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[2]_i_3_n_0 ; + wire \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[2]_i_4_n_0 ; + wire \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[3]_i_2_n_0 ; + wire \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_10_n_0 ; + wire \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_4_n_0 ; + wire \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_6_n_0 ; + wire \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_7_n_0 ; + wire \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_9_n_0 ; + wire \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] ; + wire [4:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] ; + wire \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[0] ; + wire [2:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[2] ; + wire \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_reg ; + wire \DYNAMIC_MASTER_MODE_FRAME_CNT.valid_frame_sync_d2_reg ; + wire [2:0]\GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[2] ; + wire [2:0]\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2] ; + wire [4:0]Q; + wire [0:0]SR; + wire [2:0]binary_frame_ptr; + wire data1; + wire data2; + wire [1:0]dm_binary_frame_ptr; + wire dm_mstr_reverse_order_d1; + wire m_axi_s2mm_aclk; + wire mstr_reverse_order; + wire mstr_reverse_order_d1; + wire mstr_reverse_order_d2; + wire \num_fstore_minus1_reg[1] ; + wire out; + wire [1:0]p_0_out; + wire [4:0]\ptr_ref_i_reg[4] ; + wire [2:1]raw_frame_ptr; + wire [1:0]s2mm_dmacr; + wire [0:0]s2mm_dmasr; + wire s2mm_valid_frame_sync; + wire [2:0]slv_frame_ref_out; + wire valid_frame_sync_d2; + + Arty_Z7_20_axi_vdma_0_0_axi_vdma_genlock_mux \DYNAMIC_GENLOCK_FOR_MASTER.GENLOCK_MUX_I + (.D({data1,\DYNAMIC_GENLOCK_FOR_MASTER.GENLOCK_MUX_I_n_2 }), + .\GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[2] (\GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[2] ), + .SR(SR), + .data2(data2), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk)); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_greycoder \DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.GREY_CODER_I + (.D(p_0_out), + .Q(binary_frame_ptr)); + LUT1 #( + .INIT(2'h1)) + \DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.binary_frame_ptr[0]_i_1 + (.I0(\DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg_n_0_[0] ), + .O(\DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.binary_frame_ptr[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.binary_frame_ptr_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.binary_frame_ptr[0]_i_1_n_0 ), + .Q(binary_frame_ptr[0]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.binary_frame_ptr_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg[1]_inv_n_0 ), + .Q(binary_frame_ptr[1]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.binary_frame_ptr_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg_n_0_[2] ), + .Q(binary_frame_ptr[2]), + .R(SR)); + LUT4 #( + .INIT(16'h6555)) + \DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr[1]_inv_i_1 + (.I0(\DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[2] [1]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[2] [0]), + .I2(\num_fstore_minus1_reg[1] ), + .I3(mstr_reverse_order), + .O(raw_frame_ptr[1])); + LUT5 #( + .INIT(32'h6AAAAAAA)) + \DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr[2]_i_1 + (.I0(\DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[2] [2]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[2] [0]), + .I2(\DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[2] [1]), + .I3(\num_fstore_minus1_reg[1] ), + .I4(mstr_reverse_order), + .O(raw_frame_ptr[2])); + FDRE #( + .INIT(1'b0)) + \DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[2] [0]), + .Q(\DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg_n_0_[0] ), + .R(SR)); + FDSE #( + .INIT(1'b1)) + \DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg[1]_inv + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(raw_frame_ptr[1]), + .Q(\DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg[1]_inv_n_0 ), + .S(SR)); + FDRE #( + .INIT(1'b0)) + \DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(raw_frame_ptr[2]), + .Q(\DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg_n_0_[2] ), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \DYNAMIC_GENLOCK_FOR_MASTER.dm_binary_frame_ptr_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\DYNAMIC_GENLOCK_FOR_MASTER.GENLOCK_MUX_I_n_2 ), + .Q(dm_binary_frame_ptr[0]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \DYNAMIC_GENLOCK_FOR_MASTER.dm_binary_frame_ptr_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(data1), + .Q(dm_binary_frame_ptr[1]), + .R(SR)); + FDSE #( + .INIT(1'b0)) + \DYNAMIC_GENLOCK_FOR_MASTER.dm_mstr_reverse_order_d1_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(data2), + .Q(dm_mstr_reverse_order_d1), + .S(SR)); + LUT1 #( + .INIT(2'h1)) + \DYNAMIC_GENLOCK_FOR_MASTER.frame_ptr_out[2]_i_1 + (.I0(mstr_reverse_order_d2), + .O(\DYNAMIC_GENLOCK_FOR_MASTER.frame_ptr_out[2]_i_1_n_0 )); + FDRE \DYNAMIC_GENLOCK_FOR_MASTER.frame_ptr_out_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(p_0_out[0]), + .Q(\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2] [0]), + .R(SR)); + FDRE \DYNAMIC_GENLOCK_FOR_MASTER.frame_ptr_out_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(p_0_out[1]), + .Q(\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2] [1]), + .R(SR)); + FDRE \DYNAMIC_GENLOCK_FOR_MASTER.frame_ptr_out_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\DYNAMIC_GENLOCK_FOR_MASTER.frame_ptr_out[2]_i_1_n_0 ), + .Q(\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2] [2]), + .R(SR)); + FDSE #( + .INIT(1'b0)) + \DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_d1_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(mstr_reverse_order), + .Q(mstr_reverse_order_d1), + .S(SR)); + FDSE #( + .INIT(1'b0)) + \DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_d2_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(mstr_reverse_order_d1), + .Q(mstr_reverse_order_d2), + .S(SR)); + LUT6 #( + .INIT(64'hFFFFFFFFAA69FFFF)) + \DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_i_1 + (.I0(mstr_reverse_order), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[2] [1]), + .I2(\num_fstore_minus1_reg[1] ), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[0] ), + .I4(out), + .I5(s2mm_dmasr), + .O(\DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_i_1_n_0 ), + .Q(mstr_reverse_order), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \DYNAMIC_GENLOCK_FOR_MASTER.mstrfrm_tstsync_d1_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(valid_frame_sync_d2), + .Q(s2mm_valid_frame_sync), + .R(SR)); + LUT3 #( + .INIT(8'h80)) + \DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out[0]_i_1 + (.I0(dm_binary_frame_ptr[0]), + .I1(out), + .I2(\num_fstore_minus1_reg[1] ), + .O(\DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair78" *) + LUT5 #( + .INIT(32'hD2000000)) + \DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out[1]_i_1 + (.I0(dm_mstr_reverse_order_d1), + .I1(dm_binary_frame_ptr[0]), + .I2(dm_binary_frame_ptr[1]), + .I3(out), + .I4(\num_fstore_minus1_reg[1] ), + .O(\DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair78" *) + LUT5 #( + .INIT(32'h80000000)) + \DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out[3]_i_1 + (.I0(dm_binary_frame_ptr[1]), + .I1(dm_binary_frame_ptr[0]), + .I2(dm_mstr_reverse_order_d1), + .I3(out), + .I4(\num_fstore_minus1_reg[1] ), + .O(\DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out[3]_i_1_n_0 )); + FDRE \DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out[0]_i_1_n_0 ), + .Q(slv_frame_ref_out[0]), + .R(1'b0)); + FDRE \DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out[1]_i_1_n_0 ), + .Q(slv_frame_ref_out[1]), + .R(1'b0)); + FDRE \DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out[3]_i_1_n_0 ), + .Q(slv_frame_ref_out[2]), + .R(1'b0)); + LUT6 #( + .INIT(64'hAA0FCCCCAA0FAA0F)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[0]_i_1 + (.I0(Q[0]), + .I1(\ptr_ref_i_reg[4] [0]), + .I2(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[0]_i_2_n_0 ), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_reg ), + .I4(s2mm_dmacr[0]), + .I5(valid_frame_sync_d2), + .O(D[0])); + LUT6 #( + .INIT(64'h6067666667676666)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[0]_i_2 + (.I0(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] [0]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_6_n_0 ), + .I2(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] ), + .I3(s2mm_dmacr[1]), + .I4(valid_frame_sync_d2), + .I5(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[0]_i_3_n_0 ), + .O(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[0]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair79" *) + LUT3 #( + .INIT(8'h01)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[0]_i_3 + (.I0(slv_frame_ref_out[0]), + .I1(slv_frame_ref_out[2]), + .I2(slv_frame_ref_out[1]), + .O(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[0]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAA0FCCCCAA0FAA0F)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[1]_i_1 + (.I0(Q[1]), + .I1(\ptr_ref_i_reg[4] [1]), + .I2(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[1]_i_2_n_0 ), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_reg ), + .I4(s2mm_dmacr[0]), + .I5(valid_frame_sync_d2), + .O(D[1])); + LUT6 #( + .INIT(64'hFAFAFAFAEBEBFFEB)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[1]_i_2 + (.I0(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[2]_i_3_n_0 ), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] [0]), + .I2(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] [1]), + .I3(valid_frame_sync_d2), + .I4(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] ), + .I5(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_6_n_0 ), + .O(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAA0FCCCCAA0FAA0F)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[2]_i_1 + (.I0(Q[2]), + .I1(\ptr_ref_i_reg[4] [2]), + .I2(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[2]_i_2_n_0 ), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_reg ), + .I4(s2mm_dmacr[0]), + .I5(valid_frame_sync_d2), + .O(D[2])); + LUT5 #( + .INIT(32'hFAAFEABF)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[2]_i_2 + (.I0(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[2]_i_3_n_0 ), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] [0]), + .I2(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] [1]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] [2]), + .I4(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_6_n_0 ), + .O(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[2]_i_2_n_0 )); + LUT6 #( + .INIT(64'h000000005D5D555D)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[2]_i_3 + (.I0(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] ), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_7_n_0 ), + .I2(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[2]_i_4_n_0 ), + .I3(\num_fstore_minus1_reg[1] ), + .I4(slv_frame_ref_out[1]), + .I5(\DYNAMIC_MASTER_MODE_FRAME_CNT.valid_frame_sync_d2_reg ), + .O(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[2]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair79" *) + LUT4 #( + .INIT(16'hFFF4)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[2]_i_4 + (.I0(\num_fstore_minus1_reg[1] ), + .I1(slv_frame_ref_out[1]), + .I2(slv_frame_ref_out[0]), + .I3(slv_frame_ref_out[2]), + .O(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[2]_i_4_n_0 )); + LUT6 #( + .INIT(64'hAA0FCCCCAA0FAA0F)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[3]_i_1 + (.I0(Q[3]), + .I1(\ptr_ref_i_reg[4] [3]), + .I2(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[3]_i_2_n_0 ), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_reg ), + .I4(s2mm_dmacr[0]), + .I5(valid_frame_sync_d2), + .O(D[3])); + LUT6 #( + .INIT(64'hB487474747474747)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[3]_i_2 + (.I0(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] [4]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_6_n_0 ), + .I2(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] [3]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] [0]), + .I4(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] [1]), + .I5(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] [2]), + .O(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair80" *) + LUT2 #( + .INIT(4'h1)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_10 + (.I0(slv_frame_ref_out[0]), + .I1(slv_frame_ref_out[1]), + .O(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_10_n_0 )); + LUT6 #( + .INIT(64'hAA0FCCCCAA0FAA0F)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_3 + (.I0(Q[4]), + .I1(\ptr_ref_i_reg[4] [4]), + .I2(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_4_n_0 ), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_reg ), + .I4(s2mm_dmacr[0]), + .I5(valid_frame_sync_d2), + .O(D[4])); + LUT6 #( + .INIT(64'hC333933333333333)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_4 + (.I0(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_6_n_0 ), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] [4]), + .I2(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] [2]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] [1]), + .I4(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] [0]), + .I5(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] [3]), + .O(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_4_n_0 )); + LUT6 #( + .INIT(64'h00000000AAAAAA20)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_6 + (.I0(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_7_n_0 ), + .I1(\num_fstore_minus1_reg[1] ), + .I2(slv_frame_ref_out[1]), + .I3(slv_frame_ref_out[0]), + .I4(slv_frame_ref_out[2]), + .I5(\DYNAMIC_MASTER_MODE_FRAME_CNT.valid_frame_sync_d2_reg ), + .O(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_6_n_0 )); + LUT6 #( + .INIT(64'h1220000000000001)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_7 + (.I0(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] [2]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_9_n_0 ), + .I2(slv_frame_ref_out[2]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_10_n_0 ), + .I4(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] [3]), + .I5(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] [4]), + .O(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_7_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair80" *) + LUT4 #( + .INIT(16'hF69F)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_9 + (.I0(slv_frame_ref_out[1]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] [1]), + .I2(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] [0]), + .I3(slv_frame_ref_out[0]), + .O(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_9_n_0 )); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_genlock_mux" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_genlock_mux + (data2, + D, + SR, + \GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[2] , + m_axi_s2mm_aclk); + output data2; + output [1:0]D; + input [0:0]SR; + input [2:0]\GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[2] ; + input m_axi_s2mm_aclk; + + wire [1:0]D; + wire [2:0]\GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[2] ; + wire [0:0]SR; + wire data2; + wire \frame_ptr_out_reg_n_0_[2] ; + wire m_axi_s2mm_aclk; + wire [1:0]p_3_out; + + (* SOFT_HLUTNM = "soft_lutpair76" *) + LUT2 #( + .INIT(4'h9)) + \DYNAMIC_GENLOCK_FOR_MASTER.dm_binary_frame_ptr[0]_i_1 + (.I0(p_3_out[1]), + .I1(p_3_out[0]), + .O(D[0])); + (* SOFT_HLUTNM = "soft_lutpair76" *) + LUT1 #( + .INIT(2'h1)) + \DYNAMIC_GENLOCK_FOR_MASTER.dm_binary_frame_ptr[1]_i_1 + (.I0(p_3_out[1]), + .O(D[1])); + LUT1 #( + .INIT(2'h1)) + \DYNAMIC_GENLOCK_FOR_MASTER.dm_mstr_reverse_order_d1_i_1 + (.I0(\frame_ptr_out_reg_n_0_[2] ), + .O(data2)); + FDRE \frame_ptr_out_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[2] [0]), + .Q(p_3_out[0]), + .R(SR)); + FDRE \frame_ptr_out_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[2] [1]), + .Q(p_3_out[1]), + .R(SR)); + FDRE \frame_ptr_out_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[2] [2]), + .Q(\frame_ptr_out_reg_n_0_[2] ), + .R(SR)); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_greycoder" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_greycoder + (D, + Q); + output [1:0]D; + input [2:0]Q; + + wire [1:0]D; + wire [2:0]Q; + + (* SOFT_HLUTNM = "soft_lutpair77" *) + LUT2 #( + .INIT(4'h6)) + \DYNAMIC_GENLOCK_FOR_MASTER.frame_ptr_out[0]_i_1 + (.I0(Q[1]), + .I1(Q[0]), + .O(D[0])); + (* SOFT_HLUTNM = "soft_lutpair77" *) + LUT2 #( + .INIT(4'h6)) + \DYNAMIC_GENLOCK_FOR_MASTER.frame_ptr_out[1]_i_1 + (.I0(Q[2]), + .I1(Q[1]), + .O(D[1])); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_greycoder" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_greycoder_45 + (D, + Q); + output [1:0]D; + input [2:0]Q; + + wire [1:0]D; + wire [2:0]Q; + + (* SOFT_HLUTNM = "soft_lutpair40" *) + LUT2 #( + .INIT(4'h6)) + \GENLOCK_FOR_MASTER.frame_ptr_out[0]_i_1 + (.I0(Q[1]), + .I1(Q[0]), + .O(D[0])); + (* SOFT_HLUTNM = "soft_lutpair40" *) + LUT2 #( + .INIT(4'h6)) + \GENLOCK_FOR_MASTER.frame_ptr_out[1]_i_1 + (.I0(Q[2]), + .I1(Q[1]), + .O(D[1])); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_intrpt" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_intrpt + (ch1_delay_cnt_en, + ch1_dly_irq_set, + ch2_delay_cnt_en, + ch2_dly_irq_set, + mm2s_ioc_irq_set, + ch2_irqthresh_decr_mask_sig, + s2mm_ioc_irq_set, + Q, + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 , + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 , + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 , + \GEN_FREE_RUN_MODE.mask_fsync_out_i_reg , + \GEN_FSYNC_MODE_S2MM_FLUSH_SOF.mask_fsync_out_i_reg , + \MASTER_MODE_FRAME_CNT.tstvect_fsync_reg , + m_axi_mm2s_aclk, + SR, + \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg , + m_axi_s2mm_aclk, + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0 , + prmry_resetn_i_reg, + \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg_0 , + ch1_delay_zero, + p_17_out, + p_71_out, + p_13_out, + ch2_delay_zero, + s2mm_packet_sof, + s2mm_dmacr, + p_6_out, + s2mm_tstvect_fsync, + p_50_out, + out, + prmry_resetn_i_reg_0, + p_4_out, + mask_fsync_out_i, + p_4_out_0, + mask_fsync_out_i_1, + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_reg_0 , + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out , + prmry_resetn_i_reg_1, + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out_0 , + prmry_resetn_i_reg_2, + E); + output ch1_delay_cnt_en; + output ch1_dly_irq_set; + output ch2_delay_cnt_en; + output ch2_dly_irq_set; + output mm2s_ioc_irq_set; + output ch2_irqthresh_decr_mask_sig; + output s2mm_ioc_irq_set; + output [7:0]Q; + output [7:0]\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 ; + output [7:0]\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 ; + output [7:0]\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 ; + output \GEN_FREE_RUN_MODE.mask_fsync_out_i_reg ; + output \GEN_FSYNC_MODE_S2MM_FLUSH_SOF.mask_fsync_out_i_reg ; + input \MASTER_MODE_FRAME_CNT.tstvect_fsync_reg ; + input m_axi_mm2s_aclk; + input [0:0]SR; + input \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg ; + input m_axi_s2mm_aclk; + input [0:0]\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0 ; + input [0:0]prmry_resetn_i_reg; + input \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg_0 ; + input ch1_delay_zero; + input p_17_out; + input [15:0]p_71_out; + input p_13_out; + input ch2_delay_zero; + input s2mm_packet_sof; + input [15:0]s2mm_dmacr; + input p_6_out; + input s2mm_tstvect_fsync; + input p_50_out; + input out; + input prmry_resetn_i_reg_0; + input p_4_out; + input mask_fsync_out_i; + input p_4_out_0; + input mask_fsync_out_i_1; + input \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_reg_0 ; + input \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ; + input prmry_resetn_i_reg_1; + input \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out_0 ; + input [0:0]prmry_resetn_i_reg_2; + input [0:0]E; + + wire [0:0]E; + wire \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ; + wire \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out_0 ; + wire \GEN_FREE_RUN_MODE.mask_fsync_out_i_reg ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg_0 ; + wire \GEN_FSYNC_MODE_S2MM_FLUSH_SOF.mask_fsync_out_i_reg ; + wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[1]_i_2_n_0 ; + wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_3_n_0 ; + wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0 ; + wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_1_n_0 ; + wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_4_n_0 ; + wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_3_n_0 ; + wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_4_n_0 ; + wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_6_n_0 ; + wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_7_n_0 ; + wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_reg_0 ; + wire \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_i_1_n_0 ; + wire \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[6]_i_2_n_0 ; + wire \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_4_n_0 ; + wire \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5_n_0 ; + wire \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_6_n_0 ; + wire [7:0]\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[1]_i_2_n_0 ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[6]_i_3_n_0 ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[0] ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[1] ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[2] ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[3] ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[4] ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[5] ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[6] ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_reg_n_0 ; + wire [0:0]\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0 ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_1_n_0 ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_4_n_0 ; + wire [7:0]\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_3_n_0 ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_4_n_0 ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_6_n_0 ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_7_n_0 ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_ioc_irq_set_i_i_1_n_0 ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[0]_i_1_n_0 ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[1]_i_1_n_0 ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[2]_i_1_n_0 ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[3]_i_1_n_0 ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[4]_i_1_n_0 ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[5]_i_1_n_0 ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[6]_i_1_n_0 ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[6]_i_2_n_0 ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_2_n_0 ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_3_n_0 ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_5_n_0 ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_6_n_0 ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_7_n_0 ; + wire [7:0]\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 ; + wire [6:0]L; + wire \MASTER_MODE_FRAME_CNT.tstvect_fsync_reg ; + wire [7:0]Q; + wire [0:0]SR; + wire ch1_delay_cnt_en; + wire ch1_delay_zero; + wire [6:0]ch1_dly_fast_cnt; + wire ch1_dly_fast_incr; + wire ch1_dly_irq_set; + wire ch1_ioc_irq_set_i; + wire ch2_delay_cnt_en; + wire ch2_delay_zero; + wire [6:0]ch2_dly_fast_cnt; + wire ch2_dly_fast_incr; + wire ch2_dly_irq_set; + wire ch2_ioc_irq_set_i; + wire ch2_irqthresh_decr_mask_sig; + wire m_axi_mm2s_aclk; + wire m_axi_s2mm_aclk; + wire mask_fsync_out_i; + wire mask_fsync_out_i_1; + wire mm2s_ioc_irq_set; + wire out; + wire p_12_out; + wire p_13_out; + wire p_17_out; + wire p_26_out; + wire [7:0]p_2_in; + wire p_4_out; + wire p_4_out_0; + wire p_50_out; + wire p_6_out; + wire [15:0]p_71_out; + wire [7:0]plusOp; + wire [7:0]plusOp__0; + wire [0:0]prmry_resetn_i_reg; + wire prmry_resetn_i_reg_0; + wire prmry_resetn_i_reg_1; + wire [0:0]prmry_resetn_i_reg_2; + wire [15:0]s2mm_dmacr; + wire s2mm_ioc_irq_set; + wire s2mm_packet_sof; + wire s2mm_tstvect_fsync; + + LUT4 #( + .INIT(16'h08C8)) + \GEN_FREE_RUN_MODE.mask_fsync_out_i_i_1 + (.I0(p_4_out), + .I1(out), + .I2(mask_fsync_out_i), + .I3(mm2s_ioc_irq_set), + .O(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg )); + LUT4 #( + .INIT(16'h08C8)) + \GEN_FSYNC_MODE_S2MM_FLUSH_SOF.mask_fsync_out_i_i_1 + (.I0(p_4_out_0), + .I1(prmry_resetn_i_reg_0), + .I2(mask_fsync_out_i_1), + .I3(s2mm_ioc_irq_set), + .O(\GEN_FSYNC_MODE_S2MM_FLUSH_SOF.mask_fsync_out_i_reg )); + (* SOFT_HLUTNM = "soft_lutpair97" *) + LUT3 #( + .INIT(8'h32)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[0]_i_1 + (.I0(L[1]), + .I1(L[0]), + .I2(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[1]_i_2_n_0 ), + .O(ch1_dly_fast_cnt[0])); + (* SOFT_HLUTNM = "soft_lutpair97" *) + LUT3 #( + .INIT(8'h98)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[1]_i_1 + (.I0(L[0]), + .I1(L[1]), + .I2(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[1]_i_2_n_0 ), + .O(ch1_dly_fast_cnt[1])); + LUT5 #( + .INIT(32'hFFFFFFFE)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[1]_i_2 + (.I0(L[5]), + .I1(L[3]), + .I2(L[2]), + .I3(L[4]), + .I4(L[6]), + .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[1]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair100" *) + LUT3 #( + .INIT(8'hA9)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[2]_i_1 + (.I0(L[2]), + .I1(L[0]), + .I2(L[1]), + .O(ch1_dly_fast_cnt[2])); + (* SOFT_HLUTNM = "soft_lutpair91" *) + LUT4 #( + .INIT(16'hFE01)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[3]_i_1 + (.I0(L[0]), + .I1(L[1]), + .I2(L[2]), + .I3(L[3]), + .O(ch1_dly_fast_cnt[3])); + (* SOFT_HLUTNM = "soft_lutpair91" *) + LUT5 #( + .INIT(32'hFFFE0001)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[4]_i_1 + (.I0(L[0]), + .I1(L[1]), + .I2(L[3]), + .I3(L[2]), + .I4(L[4]), + .O(ch1_dly_fast_cnt[4])); + LUT6 #( + .INIT(64'hFFFFFFFE00000001)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[5]_i_1 + (.I0(L[0]), + .I1(L[1]), + .I2(L[4]), + .I3(L[2]), + .I4(L[3]), + .I5(L[5]), + .O(ch1_dly_fast_cnt[5])); + LUT6 #( + .INIT(64'hFFFFFFFE00000001)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_2 + (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_3_n_0 ), + .I1(L[5]), + .I2(L[3]), + .I3(L[2]), + .I4(L[4]), + .I5(L[6]), + .O(ch1_dly_fast_cnt[6])); + (* SOFT_HLUTNM = "soft_lutpair100" *) + LUT2 #( + .INIT(4'hE)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_3 + (.I0(L[0]), + .I1(L[1]), + .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_3_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(ch1_dly_fast_cnt[0]), + .Q(L[0]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(ch1_dly_fast_cnt[1]), + .Q(L[1]), + .R(SR)); + FDSE #( + .INIT(1'b0)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(ch1_dly_fast_cnt[2]), + .Q(L[2]), + .S(SR)); + FDSE #( + .INIT(1'b0)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(ch1_dly_fast_cnt[3]), + .Q(L[3]), + .S(SR)); + FDSE #( + .INIT(1'b0)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(ch1_dly_fast_cnt[4]), + .Q(L[4]), + .S(SR)); + FDSE #( + .INIT(1'b0)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(ch1_dly_fast_cnt[5]), + .Q(L[5]), + .S(SR)); + FDSE #( + .INIT(1'b0)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(ch1_dly_fast_cnt[6]), + .Q(L[6]), + .S(SR)); + LUT6 #( + .INIT(64'h0000000000000001)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_i_1 + (.I0(L[6]), + .I1(L[4]), + .I2(L[2]), + .I3(L[3]), + .I4(L[5]), + .I5(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_3_n_0 ), + .O(ch1_dly_fast_incr)); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(ch1_dly_fast_incr), + .Q(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0 ), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\MASTER_MODE_FRAME_CNT.tstvect_fsync_reg ), + .Q(ch1_delay_cnt_en), + .R(1'b0)); + LUT1 #( + .INIT(2'h1)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[0]_i_1 + (.I0(Q[0]), + .O(plusOp[0])); + (* SOFT_HLUTNM = "soft_lutpair98" *) + LUT2 #( + .INIT(4'h6)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[1]_i_1 + (.I0(Q[0]), + .I1(Q[1]), + .O(plusOp[1])); + (* SOFT_HLUTNM = "soft_lutpair98" *) + LUT3 #( + .INIT(8'h78)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[2]_i_1 + (.I0(Q[0]), + .I1(Q[1]), + .I2(Q[2]), + .O(plusOp[2])); + (* SOFT_HLUTNM = "soft_lutpair90" *) + LUT4 #( + .INIT(16'h7F80)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[3]_i_1 + (.I0(Q[2]), + .I1(Q[1]), + .I2(Q[0]), + .I3(Q[3]), + .O(plusOp[3])); + (* SOFT_HLUTNM = "soft_lutpair90" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[4]_i_1 + (.I0(Q[3]), + .I1(Q[0]), + .I2(Q[1]), + .I3(Q[2]), + .I4(Q[4]), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h7FFFFFFF80000000)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[5]_i_1 + (.I0(Q[2]), + .I1(Q[1]), + .I2(Q[0]), + .I3(Q[3]), + .I4(Q[4]), + .I5(Q[5]), + .O(plusOp[5])); + LUT2 #( + .INIT(4'h9)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[6]_i_1 + (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_4_n_0 ), + .I1(Q[6]), + .O(plusOp[6])); + LUT6 #( + .INIT(64'hFFFFFFFFBBBBBFBB)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_1 + (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_reg_0 ), + .I1(ch1_delay_cnt_en), + .I2(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_3_n_0 ), + .I3(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0 ), + .I4(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_4_n_0 ), + .I5(\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ), + .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair92" *) + LUT3 #( + .INIT(8'hD2)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_2 + (.I0(Q[6]), + .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_4_n_0 ), + .I2(Q[7]), + .O(plusOp[7])); + LUT6 #( + .INIT(64'h7FFFFFFFFFFFFFFF)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_4 + (.I0(Q[2]), + .I1(Q[1]), + .I2(Q[0]), + .I3(Q[3]), + .I4(Q[4]), + .I5(Q[5]), + .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0 ), + .D(plusOp[0]), + .Q(Q[0]), + .R(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0 ), + .D(plusOp[1]), + .Q(Q[1]), + .R(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0 ), + .D(plusOp[2]), + .Q(Q[2]), + .R(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0 ), + .D(plusOp[3]), + .Q(Q[3]), + .R(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0 ), + .D(plusOp[4]), + .Q(Q[4]), + .R(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0 ), + .D(plusOp[5]), + .Q(Q[5]), + .R(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[6] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0 ), + .D(plusOp[6]), + .Q(Q[6]), + .R(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0 ), + .D(plusOp[7]), + .Q(Q[7]), + .R(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_1_n_0 )); + LUT5 #( + .INIT(32'h00000010)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_1 + (.I0(ch1_delay_zero), + .I1(p_17_out), + .I2(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0 ), + .I3(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_3_n_0 ), + .I4(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_4_n_0 ), + .O(p_26_out)); + (* SOFT_HLUTNM = "soft_lutpair92" *) + LUT4 #( + .INIT(16'h6FF6)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_3 + (.I0(Q[7]), + .I1(p_71_out[15]), + .I2(Q[6]), + .I3(p_71_out[14]), + .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFBEFFFFBE)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_4 + (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_6_n_0 ), + .I1(Q[1]), + .I2(p_71_out[9]), + .I3(Q[0]), + .I4(p_71_out[8]), + .I5(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_7_n_0 ), + .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_4_n_0 )); + LUT4 #( + .INIT(16'h6FF6)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_6 + (.I0(Q[4]), + .I1(p_71_out[12]), + .I2(Q[3]), + .I3(p_71_out[11]), + .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_6_n_0 )); + LUT4 #( + .INIT(16'h6FF6)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_7 + (.I0(Q[5]), + .I1(p_71_out[13]), + .I2(Q[2]), + .I3(p_71_out[10]), + .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_7_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(p_26_out), + .Q(ch1_dly_irq_set), + .R(SR)); + LUT4 #( + .INIT(16'h0080)) + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_i_1 + (.I0(ch1_ioc_irq_set_i), + .I1(p_50_out), + .I2(out), + .I3(p_13_out), + .O(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_i_1_n_0 )); + LUT5 #( + .INIT(32'h00010000)) + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_i_2 + (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [4]), + .I1(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [5]), + .I2(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [6]), + .I3(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [7]), + .I4(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_6_n_0 ), + .O(ch1_ioc_irq_set_i)); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_i_1_n_0 ), + .Q(mm2s_ioc_irq_set), + .R(1'b0)); + LUT3 #( + .INIT(8'h8B)) + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[0]_i_1 + (.I0(p_71_out[0]), + .I1(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5_n_0 ), + .I2(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [0]), + .O(p_2_in[0])); + LUT4 #( + .INIT(16'hF099)) + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[1]_i_1 + (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [0]), + .I1(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [1]), + .I2(p_71_out[1]), + .I3(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5_n_0 ), + .O(p_2_in[1])); + LUT5 #( + .INIT(32'hFF00A9A9)) + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[2]_i_1 + (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [2]), + .I1(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [1]), + .I2(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [0]), + .I3(p_71_out[2]), + .I4(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5_n_0 ), + .O(p_2_in[2])); + LUT6 #( + .INIT(64'hFFFF0000AAA9AAA9)) + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[3]_i_1 + (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [3]), + .I1(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [0]), + .I2(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [1]), + .I3(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [2]), + .I4(p_71_out[3]), + .I5(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5_n_0 ), + .O(p_2_in[3])); + LUT4 #( + .INIT(16'hF099)) + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[4]_i_1 + (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [4]), + .I1(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[6]_i_2_n_0 ), + .I2(p_71_out[4]), + .I3(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5_n_0 ), + .O(p_2_in[4])); + LUT5 #( + .INIT(32'hFF00A9A9)) + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[5]_i_1 + (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [5]), + .I1(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[6]_i_2_n_0 ), + .I2(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [4]), + .I3(p_71_out[5]), + .I4(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5_n_0 ), + .O(p_2_in[5])); + LUT6 #( + .INIT(64'hFFFF0000AAA9AAA9)) + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[6]_i_1 + (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [6]), + .I1(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [4]), + .I2(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[6]_i_2_n_0 ), + .I3(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [5]), + .I4(p_71_out[6]), + .I5(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5_n_0 ), + .O(p_2_in[6])); + (* SOFT_HLUTNM = "soft_lutpair94" *) + LUT4 #( + .INIT(16'hFFFE)) + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[6]_i_2 + (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [2]), + .I1(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [1]), + .I2(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [0]), + .I3(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [3]), + .O(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[6]_i_2_n_0 )); + LUT5 #( + .INIT(32'hFF00A9A9)) + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_3 + (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [7]), + .I1(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [6]), + .I2(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_4_n_0 ), + .I3(p_71_out[7]), + .I4(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5_n_0 ), + .O(p_2_in[7])); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_4 + (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [4]), + .I1(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [2]), + .I2(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [1]), + .I3(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [0]), + .I4(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [3]), + .I5(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [5]), + .O(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFF00000002)) + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5 + (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_6_n_0 ), + .I1(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [7]), + .I2(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [6]), + .I3(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [5]), + .I4(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [4]), + .I5(p_13_out), + .O(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair94" *) + LUT4 #( + .INIT(16'h0004)) + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_6 + (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [1]), + .I1(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [0]), + .I2(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [3]), + .I3(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [2]), + .O(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_6_n_0 )); + FDSE #( + .INIT(1'b1)) + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(p_2_in[0]), + .Q(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [0]), + .S(prmry_resetn_i_reg_2)); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(p_2_in[1]), + .Q(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [1]), + .R(prmry_resetn_i_reg_2)); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(p_2_in[2]), + .Q(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [2]), + .R(prmry_resetn_i_reg_2)); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(p_2_in[3]), + .Q(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [3]), + .R(prmry_resetn_i_reg_2)); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(p_2_in[4]), + .Q(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [4]), + .R(prmry_resetn_i_reg_2)); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(p_2_in[5]), + .Q(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [5]), + .R(prmry_resetn_i_reg_2)); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[6] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(p_2_in[6]), + .Q(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [6]), + .R(prmry_resetn_i_reg_2)); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(p_2_in[7]), + .Q(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0 [7]), + .R(prmry_resetn_i_reg_2)); + (* SOFT_HLUTNM = "soft_lutpair96" *) + LUT3 #( + .INIT(8'h32)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[0]_i_1 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[1] ), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[0] ), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[1]_i_2_n_0 ), + .O(ch2_dly_fast_cnt[0])); + (* SOFT_HLUTNM = "soft_lutpair96" *) + LUT3 #( + .INIT(8'h98)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[1]_i_1 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[0] ), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[1] ), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[1]_i_2_n_0 ), + .O(ch2_dly_fast_cnt[1])); + LUT5 #( + .INIT(32'hFFFFFFFE)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[1]_i_2 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[5] ), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[3] ), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[2] ), + .I3(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[4] ), + .I4(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[6] ), + .O(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[1]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair101" *) + LUT3 #( + .INIT(8'hA9)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[2]_i_1 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[2] ), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[0] ), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[1] ), + .O(ch2_dly_fast_cnt[2])); + (* SOFT_HLUTNM = "soft_lutpair88" *) + LUT4 #( + .INIT(16'hFE01)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[3]_i_1 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[0] ), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[1] ), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[2] ), + .I3(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[3] ), + .O(ch2_dly_fast_cnt[3])); + (* SOFT_HLUTNM = "soft_lutpair88" *) + LUT5 #( + .INIT(32'hFFFE0001)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[4]_i_1 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[0] ), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[1] ), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[3] ), + .I3(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[2] ), + .I4(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[4] ), + .O(ch2_dly_fast_cnt[4])); + LUT6 #( + .INIT(64'hFFFFFFFE00000001)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[5]_i_1 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[0] ), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[1] ), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[4] ), + .I3(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[2] ), + .I4(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[3] ), + .I5(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[5] ), + .O(ch2_dly_fast_cnt[5])); + LUT6 #( + .INIT(64'hFFFFFFFE00000001)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[6]_i_2 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[6]_i_3_n_0 ), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[5] ), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[3] ), + .I3(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[2] ), + .I4(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[4] ), + .I5(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[6] ), + .O(ch2_dly_fast_cnt[6])); + (* SOFT_HLUTNM = "soft_lutpair101" *) + LUT2 #( + .INIT(4'hE)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[6]_i_3 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[0] ), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[1] ), + .O(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[6]_i_3_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(ch2_dly_fast_cnt[0]), + .Q(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[0] ), + .R(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(ch2_dly_fast_cnt[1]), + .Q(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[1] ), + .R(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0 )); + FDSE #( + .INIT(1'b0)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(ch2_dly_fast_cnt[2]), + .Q(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[2] ), + .S(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0 )); + FDSE #( + .INIT(1'b0)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(ch2_dly_fast_cnt[3]), + .Q(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[3] ), + .S(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0 )); + FDSE #( + .INIT(1'b0)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(ch2_dly_fast_cnt[4]), + .Q(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[4] ), + .S(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0 )); + FDSE #( + .INIT(1'b0)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(ch2_dly_fast_cnt[5]), + .Q(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[5] ), + .S(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0 )); + FDSE #( + .INIT(1'b0)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(ch2_dly_fast_cnt[6]), + .Q(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[6] ), + .S(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0 )); + LUT6 #( + .INIT(64'h0000000000000001)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_i_1 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[6] ), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[4] ), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[2] ), + .I3(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[3] ), + .I4(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[5] ), + .I5(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[6]_i_3_n_0 ), + .O(ch2_dly_fast_incr)); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(ch2_dly_fast_incr), + .Q(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_reg_n_0 ), + .R(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg ), + .Q(ch2_delay_cnt_en), + .R(1'b0)); + LUT1 #( + .INIT(2'h1)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[0]_i_1 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [0]), + .O(plusOp__0[0])); + (* SOFT_HLUTNM = "soft_lutpair99" *) + LUT2 #( + .INIT(4'h6)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[1]_i_1 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [0]), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [1]), + .O(plusOp__0[1])); + (* SOFT_HLUTNM = "soft_lutpair99" *) + LUT3 #( + .INIT(8'h78)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[2]_i_1 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [0]), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [1]), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [2]), + .O(plusOp__0[2])); + (* SOFT_HLUTNM = "soft_lutpair89" *) + LUT4 #( + .INIT(16'h7F80)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[3]_i_1 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [2]), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [1]), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [0]), + .I3(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [3]), + .O(plusOp__0[3])); + (* SOFT_HLUTNM = "soft_lutpair89" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[4]_i_1 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [3]), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [0]), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [1]), + .I3(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [2]), + .I4(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [4]), + .O(plusOp__0[4])); + LUT6 #( + .INIT(64'h7FFFFFFF80000000)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[5]_i_1 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [2]), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [1]), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [0]), + .I3(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [3]), + .I4(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [4]), + .I5(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [5]), + .O(plusOp__0[5])); + LUT2 #( + .INIT(4'h9)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[6]_i_1 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_4_n_0 ), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [6]), + .O(plusOp__0[6])); + LUT6 #( + .INIT(64'hFFFFFFFFBBBBBFBB)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_1 + (.I0(prmry_resetn_i_reg_1), + .I1(ch2_delay_cnt_en), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_3_n_0 ), + .I3(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_reg_n_0 ), + .I4(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_4_n_0 ), + .I5(\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out_0 ), + .O(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair95" *) + LUT3 #( + .INIT(8'hD2)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_2 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [6]), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_4_n_0 ), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [7]), + .O(plusOp__0[7])); + LUT6 #( + .INIT(64'h7FFFFFFFFFFFFFFF)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_4 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [2]), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [1]), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [0]), + .I3(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [3]), + .I4(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [4]), + .I5(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [5]), + .O(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_reg_n_0 ), + .D(plusOp__0[0]), + .Q(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [0]), + .R(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_reg_n_0 ), + .D(plusOp__0[1]), + .Q(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [1]), + .R(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_reg_n_0 ), + .D(plusOp__0[2]), + .Q(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [2]), + .R(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_reg_n_0 ), + .D(plusOp__0[3]), + .Q(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [3]), + .R(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_reg_n_0 ), + .D(plusOp__0[4]), + .Q(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [4]), + .R(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_reg_n_0 ), + .D(plusOp__0[5]), + .Q(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [5]), + .R(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_reg_n_0 ), + .D(plusOp__0[6]), + .Q(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [6]), + .R(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_reg_n_0 ), + .D(plusOp__0[7]), + .Q(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [7]), + .R(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_1_n_0 )); + LUT5 #( + .INIT(32'h00000010)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_1 + (.I0(ch2_delay_zero), + .I1(s2mm_packet_sof), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_reg_n_0 ), + .I3(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_3_n_0 ), + .I4(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_4_n_0 ), + .O(p_12_out)); + (* SOFT_HLUTNM = "soft_lutpair95" *) + LUT4 #( + .INIT(16'h6FF6)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_3 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [7]), + .I1(s2mm_dmacr[15]), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [6]), + .I3(s2mm_dmacr[14]), + .O(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFBEFFFFBE)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_4 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_6_n_0 ), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [1]), + .I2(s2mm_dmacr[9]), + .I3(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [0]), + .I4(s2mm_dmacr[8]), + .I5(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_7_n_0 ), + .O(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_4_n_0 )); + LUT4 #( + .INIT(16'h6FF6)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_6 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [4]), + .I1(s2mm_dmacr[12]), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [3]), + .I3(s2mm_dmacr[11]), + .O(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_6_n_0 )); + LUT4 #( + .INIT(16'h6FF6)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_7 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [5]), + .I1(s2mm_dmacr[13]), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0 [2]), + .I3(s2mm_dmacr[10]), + .O(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_7_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(p_12_out), + .Q(ch2_dly_irq_set), + .R(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0 )); + LUT5 #( + .INIT(32'h00000800)) + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_ioc_irq_set_i_i_1 + (.I0(ch2_ioc_irq_set_i), + .I1(s2mm_tstvect_fsync), + .I2(ch2_irqthresh_decr_mask_sig), + .I3(prmry_resetn_i_reg_0), + .I4(p_6_out), + .O(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_ioc_irq_set_i_i_1_n_0 )); + LUT5 #( + .INIT(32'h00010000)) + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_ioc_irq_set_i_i_2 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [4]), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [5]), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [6]), + .I3(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [7]), + .I4(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_7_n_0 ), + .O(ch2_ioc_irq_set_i)); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_ioc_irq_set_i_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_ioc_irq_set_i_i_1_n_0 ), + .Q(s2mm_ioc_irq_set), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_irqthresh_decr_mask_sig_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg_0 ), + .Q(ch2_irqthresh_decr_mask_sig), + .R(prmry_resetn_i_reg)); + LUT3 #( + .INIT(8'h8B)) + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[0]_i_1 + (.I0(s2mm_dmacr[0]), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_6_n_0 ), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [0]), + .O(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[0]_i_1_n_0 )); + LUT4 #( + .INIT(16'hF099)) + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[1]_i_1 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [0]), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [1]), + .I2(s2mm_dmacr[1]), + .I3(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_6_n_0 ), + .O(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[1]_i_1_n_0 )); + LUT5 #( + .INIT(32'hFF00A9A9)) + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[2]_i_1 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [2]), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [1]), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [0]), + .I3(s2mm_dmacr[2]), + .I4(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_6_n_0 ), + .O(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFF0000AAA9AAA9)) + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[3]_i_1 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [3]), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [0]), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [1]), + .I3(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [2]), + .I4(s2mm_dmacr[3]), + .I5(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_6_n_0 ), + .O(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[3]_i_1_n_0 )); + LUT4 #( + .INIT(16'hF099)) + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[4]_i_1 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [4]), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[6]_i_2_n_0 ), + .I2(s2mm_dmacr[4]), + .I3(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_6_n_0 ), + .O(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[4]_i_1_n_0 )); + LUT5 #( + .INIT(32'hFF00A9A9)) + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[5]_i_1 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [5]), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[6]_i_2_n_0 ), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [4]), + .I3(s2mm_dmacr[5]), + .I4(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_6_n_0 ), + .O(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[5]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFF0000AAA9AAA9)) + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[6]_i_1 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [6]), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [4]), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[6]_i_2_n_0 ), + .I3(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [5]), + .I4(s2mm_dmacr[6]), + .I5(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_6_n_0 ), + .O(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair93" *) + LUT4 #( + .INIT(16'hFFFE)) + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[6]_i_2 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [2]), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [1]), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [0]), + .I3(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [3]), + .O(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[6]_i_2_n_0 )); + LUT3 #( + .INIT(8'hF4)) + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_2 + (.I0(ch2_irqthresh_decr_mask_sig), + .I1(s2mm_tstvect_fsync), + .I2(p_6_out), + .O(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_2_n_0 )); + LUT5 #( + .INIT(32'hFF00A9A9)) + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_3 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [7]), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [6]), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_5_n_0 ), + .I3(s2mm_dmacr[7]), + .I4(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_6_n_0 ), + .O(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_5 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [4]), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [2]), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [1]), + .I3(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [0]), + .I4(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [3]), + .I5(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [5]), + .O(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFF00000002)) + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_6 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_7_n_0 ), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [7]), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [6]), + .I3(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [5]), + .I4(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [4]), + .I5(p_6_out), + .O(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair93" *) + LUT4 #( + .INIT(16'h0004)) + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_7 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [1]), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [0]), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [3]), + .I3(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [2]), + .O(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_7_n_0 )); + FDSE #( + .INIT(1'b1)) + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_2_n_0 ), + .D(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[0]_i_1_n_0 ), + .Q(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [0]), + .S(prmry_resetn_i_reg)); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_2_n_0 ), + .D(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[1]_i_1_n_0 ), + .Q(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [1]), + .R(prmry_resetn_i_reg)); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_2_n_0 ), + .D(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[2]_i_1_n_0 ), + .Q(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [2]), + .R(prmry_resetn_i_reg)); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_2_n_0 ), + .D(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[3]_i_1_n_0 ), + .Q(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [3]), + .R(prmry_resetn_i_reg)); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_2_n_0 ), + .D(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[4]_i_1_n_0 ), + .Q(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [4]), + .R(prmry_resetn_i_reg)); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_2_n_0 ), + .D(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[5]_i_1_n_0 ), + .Q(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [5]), + .R(prmry_resetn_i_reg)); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_2_n_0 ), + .D(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[6]_i_1_n_0 ), + .Q(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [6]), + .R(prmry_resetn_i_reg)); + FDRE #( + .INIT(1'b0)) + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_2_n_0 ), + .D(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_3_n_0 ), + .Q(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0 [7]), + .R(prmry_resetn_i_reg)); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_lite_if" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_lite_if + (D, + out, + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31] , + s_axi_lite_awready, + s_axi_lite_wready, + s_axi_lite_arready, + dmacr_i, + mm2s_axi2ip_wrce, + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] , + in0, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]_0 , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_0 , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1 , + p_15_out, + \dmacr_i_reg[1] , + p_14_out, + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]_0 , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 , + prmtr_updt_complete_i_reg, + prmtr_updt_complete_i_reg_0, + ioc_irq_reg, + dly_irq_reg, + dma_interr_reg, + dma_interr_reg_0, + \GEN_FOR_FLUSH.fsize_err_reg , + lsize_err_reg, + \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg , + ioc_irq_reg_0, + dly_irq_reg_0, + lsize_more_err_reg, + s_axi_lite_bvalid, + s_axi_lite_rvalid, + s_axi_lite_rdata, + s2mm_axi2ip_wrce, + SR, + s_axi_lite_aclk, + prmry_reset2, + m_axi_mm2s_aclk, + prmry_reset2_0, + m_axi_s2mm_aclk, + s_axi_lite_wvalid, + s_axi_lite_awvalid, + s_axi_lite_arvalid, + s_axi_lite_resetn, + p_71_out, + mm2s_prmry_resetn, + stop, + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_reg , + \reg_module_hsize_reg[0] , + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] , + \reg_module_hsize_reg[3] , + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] , + \reg_module_hsize_reg[4] , + \reg_module_hsize_reg[5] , + \reg_module_hsize_reg[6] , + \reg_module_hsize_reg[7] , + \reg_module_hsize_reg[8] , + \reg_module_hsize_reg[9] , + \reg_module_hsize_reg[10] , + \reg_module_hsize_reg[11] , + \reg_module_hsize_reg[12] , + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] , + \reg_module_hsize_reg[15] , + \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] , + p_70_out, + dma_interr_reg_1, + \M_GEN_DMACR_REGISTER.dmacr_i_reg[14] , + dma_slverr_reg, + dma_decerr_reg, + ioc_irq_reg_1, + dly_irq_reg_1, + err_irq_reg, + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] , + ch1_irqdelay_status, + s2mm_dmacr, + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31]_0 , + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[23] , + s2mm_prmry_resetn, + s2mm_dmasr, + \DMA_IRQ_MASK_GEN.dma_irq_mask_i_reg[3] , + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 , + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 , + \reg_module_vsize_reg[12] , + s2mm_soft_reset, + \reg_module_hsize_reg[15]_0 , + \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] , + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 , + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7] , + ch2_irqdelay_status, + dma_interr_reg_2, + dma_slverr_reg_0, + dma_decerr_reg_0, + \GEN_FOR_FLUSH.fsize_err_reg_0 , + lsize_err_reg_0, + \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14] , + \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg_0 , + ioc_irq_reg_2, + dly_irq_reg_2, + err_irq_reg_0, + lsize_more_err_reg_0, + mm2s_ioc_irq_set, + ch1_dly_irq_set, + s2mm_dma_interr_set_minus_frame_errors, + s2mm_fsize_more_or_sof_late, + fsize_mismatch_err, + lsize_mismatch_err, + s2mm_ioc_irq_set, + ch2_dly_irq_set, + lsize_more_mismatch_err, + s_axi_lite_bready, + s_axi_lite_rready, + s_axi_lite_araddr, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 , + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 , + s_axi_lite_wdata, + s_axi_lite_awaddr, + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] , + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4] , + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] , + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4] ); + output [31:0]D; + output [1:0]out; + output [31:0]\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31] ; + output s_axi_lite_awready; + output s_axi_lite_wready; + output s_axi_lite_arready; + output [0:0]dmacr_i; + output [8:0]mm2s_axi2ip_wrce; + output [0:0]\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] ; + output [28:0]in0; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]_0 ; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_0 ; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1 ; + output p_15_out; + output \dmacr_i_reg[1] ; + output p_14_out; + output [0:0]\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]_0 ; + output [31:0]\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 ; + output prmtr_updt_complete_i_reg; + output prmtr_updt_complete_i_reg_0; + output ioc_irq_reg; + output dly_irq_reg; + output dma_interr_reg; + output dma_interr_reg_0; + output \GEN_FOR_FLUSH.fsize_err_reg ; + output lsize_err_reg; + output \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg ; + output ioc_irq_reg_0; + output dly_irq_reg_0; + output lsize_more_err_reg; + output s_axi_lite_bvalid; + output s_axi_lite_rvalid; + output [31:0]s_axi_lite_rdata; + output [7:0]s2mm_axi2ip_wrce; + input [0:0]SR; + input s_axi_lite_aclk; + input prmry_reset2; + input m_axi_mm2s_aclk; + input prmry_reset2_0; + input m_axi_s2mm_aclk; + input s_axi_lite_wvalid; + input s_axi_lite_awvalid; input s_axi_lite_arvalid; + input s_axi_lite_resetn; + input [17:0]p_71_out; + input mm2s_prmry_resetn; + input stop; + input \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_reg ; + input \reg_module_hsize_reg[0] ; + input [28:0]\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] ; + input \reg_module_hsize_reg[3] ; + input [28:0]\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] ; + input \reg_module_hsize_reg[4] ; + input \reg_module_hsize_reg[5] ; + input \reg_module_hsize_reg[6] ; + input \reg_module_hsize_reg[7] ; + input \reg_module_hsize_reg[8] ; + input \reg_module_hsize_reg[9] ; + input \reg_module_hsize_reg[10] ; + input \reg_module_hsize_reg[11] ; + input \reg_module_hsize_reg[12] ; + input [18:0]\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] ; + input [2:0]\reg_module_hsize_reg[15] ; + input [2:0]\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ; + input p_70_out; + input dma_interr_reg_1; + input [4:0]\M_GEN_DMACR_REGISTER.dmacr_i_reg[14] ; + input dma_slverr_reg; + input dma_decerr_reg; + input ioc_irq_reg_1; + input dly_irq_reg_1; + input err_irq_reg; + input [7:0]\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] ; + input [7:0]ch1_irqdelay_status; + input [22:0]s2mm_dmacr; + input \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31]_0 ; + input \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[23] ; + input s2mm_prmry_resetn; + input [0:0]s2mm_dmasr; + input [3:0]\DMA_IRQ_MASK_GEN.dma_irq_mask_i_reg[3] ; + input [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 ; + input [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 ; + input [12:0]\reg_module_vsize_reg[12] ; + input s2mm_soft_reset; + input [15:0]\reg_module_hsize_reg[15]_0 ; + input [15:0]\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ; + input [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 ; + input [7:0]\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7] ; + input [7:0]ch2_irqdelay_status; + input dma_interr_reg_2; + input dma_slverr_reg_0; + input dma_decerr_reg_0; + input \GEN_FOR_FLUSH.fsize_err_reg_0 ; + input lsize_err_reg_0; + input [6:0]\GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14] ; + input \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg_0 ; + input ioc_irq_reg_2; + input dly_irq_reg_2; + input err_irq_reg_0; + input lsize_more_err_reg_0; + input mm2s_ioc_irq_set; + input ch1_dly_irq_set; + input s2mm_dma_interr_set_minus_frame_errors; + input s2mm_fsize_more_or_sof_late; + input fsize_mismatch_err; + input lsize_mismatch_err; + input s2mm_ioc_irq_set; + input ch2_dly_irq_set; + input lsize_more_mismatch_err; + input s_axi_lite_bready; + input s_axi_lite_rready; + input [5:0]s_axi_lite_araddr; + input [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 ; + input [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 ; + input [31:0]s_axi_lite_wdata; + input [5:0]s_axi_lite_awaddr; + input [4:0]\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] ; + input [4:0]\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4] ; + input [4:0]\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] ; + input [4:0]\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4] ; + + wire [3:0]\DMA_IRQ_MASK_GEN.dma_irq_mask_i_reg[3] ; + wire [15:0]\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ; + wire \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31]_0 ; + wire [0:0]\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] ; + wire [0:0]\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]_0 ; + wire \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[23] ; + wire \GEN_FOR_FLUSH.fsize_err_reg ; + wire \GEN_FOR_FLUSH.fsize_err_reg_0 ; + wire \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg ; + wire \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg_0 ; + wire \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_reg ; + wire [7:0]\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] ; + wire [7:0]\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[25]_i_2_n_0 ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0 ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0 ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0 ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0 ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[4]_i_2_n_0 ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]_0 ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_0 ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1 ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.prepare_wrce_pulse_lite_d6_reg_srl6_i_1_n_0 ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.rvalid_out_i_i_1_n_0 ; + wire [31:0]\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 ; + wire [4:0]\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] ; + wire [4:0]\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] ; + wire [6:0]\GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14] ; + wire [18:0]\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] ; + wire [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 ; + wire [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 ; + wire [28:0]\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] ; + wire [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 ; + wire [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 ; + wire [28:0]\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] ; + wire [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 ; + wire [4:0]\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4] ; + wire [4:0]\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4] ; + wire [2:0]\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ; + wire [4:0]\M_GEN_DMACR_REGISTER.dmacr_i_reg[14] ; + wire [0:0]SR; + wire arvalid; + wire [7:2]awaddr; + wire awvalid; + (* async_reg = "true" *) wire [7:2]axi2ip_rdaddr_captured_mm2s_cdc_tig; + wire \axi2ip_rdaddr_captured_reg_n_0_[4] ; + wire \axi2ip_rdaddr_captured_reg_n_0_[5] ; + wire \axi2ip_rdaddr_captured_reg_n_0_[6] ; + wire \axi2ip_rdaddr_captured_reg_n_0_[7] ; + (* async_reg = "true" *) wire [7:2]axi2ip_rdaddr_captured_s2mm_cdc_tig; + wire [7:2]axi2ip_wraddr_captured; + (* async_reg = "true" *) wire [7:2]axi2ip_wraddr_captured_mm2s_cdc_tig; + (* async_reg = "true" *) wire [7:2]axi2ip_wraddr_captured_s2mm_cdc_tig; + wire bvalid_out_i_i_1_n_0; + wire ch1_dly_irq_set; + wire [7:0]ch1_irqdelay_status; + wire ch2_dly_irq_set; + wire [7:0]ch2_irqdelay_status; + wire dly_irq_reg; + wire dly_irq_reg_0; + wire dly_irq_reg_1; + wire dly_irq_reg_2; + wire dma_decerr_reg; + wire dma_decerr_reg_0; + wire dma_interr_reg; + wire dma_interr_reg_0; + wire dma_interr_reg_1; + wire dma_interr_reg_2; + wire dma_slverr_reg; + wire dma_slverr_reg_0; + wire [0:0]dmacr_i; + wire \dmacr_i_reg[1] ; + wire err_irq_reg; + wire err_irq_reg_0; + wire fsize_mismatch_err; + wire [28:0]in0; + wire ioc_irq_reg; + wire ioc_irq_reg_0; + wire ioc_irq_reg_1; + wire ioc_irq_reg_2; + wire [31:0]ip2axi_rddata_captured; + (* async_reg = "true" *) wire [31:0]ip2axi_rddata_captured_mm2s_cdc_tig; + (* async_reg = "true" *) wire [31:0]ip2axi_rddata_captured_s2mm_cdc_tig; + wire ip2axi_rddata_int_inferred_i_33__0_n_0; + wire ip2axi_rddata_int_inferred_i_33_n_0; + wire ip2axi_rddata_int_inferred_i_34__0_n_0; + wire ip2axi_rddata_int_inferred_i_34_n_0; + wire ip2axi_rddata_int_inferred_i_35__0_n_0; + wire ip2axi_rddata_int_inferred_i_36__0_n_0; + wire ip2axi_rddata_int_inferred_i_36_n_0; + wire ip2axi_rddata_int_inferred_i_37__0_n_0; + wire ip2axi_rddata_int_inferred_i_37_n_0; + wire ip2axi_rddata_int_inferred_i_38__0_n_0; + wire ip2axi_rddata_int_inferred_i_38_n_0; + wire ip2axi_rddata_int_inferred_i_39__0_n_0; + wire ip2axi_rddata_int_inferred_i_39_n_0; + wire ip2axi_rddata_int_inferred_i_40__0_n_0; + wire ip2axi_rddata_int_inferred_i_40_n_0; + wire ip2axi_rddata_int_inferred_i_41__0_n_0; + wire ip2axi_rddata_int_inferred_i_41_n_0; + wire ip2axi_rddata_int_inferred_i_42__0_n_0; + wire ip2axi_rddata_int_inferred_i_42_n_0; + wire ip2axi_rddata_int_inferred_i_43__0_n_0; + wire ip2axi_rddata_int_inferred_i_43_n_0; + wire ip2axi_rddata_int_inferred_i_44__0_n_0; + wire ip2axi_rddata_int_inferred_i_44_n_0; + wire ip2axi_rddata_int_inferred_i_45__0_n_0; + wire ip2axi_rddata_int_inferred_i_45_n_0; + wire ip2axi_rddata_int_inferred_i_46__0_n_0; + wire ip2axi_rddata_int_inferred_i_46_n_0; + wire ip2axi_rddata_int_inferred_i_47__0_n_0; + wire ip2axi_rddata_int_inferred_i_47_n_0; + wire ip2axi_rddata_int_inferred_i_48__0_n_0; + wire ip2axi_rddata_int_inferred_i_48_n_0; + wire ip2axi_rddata_int_inferred_i_49__0_n_0; + wire ip2axi_rddata_int_inferred_i_49_n_0; + wire ip2axi_rddata_int_inferred_i_50__0_n_0; + wire ip2axi_rddata_int_inferred_i_50_n_0; + wire ip2axi_rddata_int_inferred_i_51__0_n_0; + wire ip2axi_rddata_int_inferred_i_52__0_n_0; + wire ip2axi_rddata_int_inferred_i_53__0_n_0; + wire ip2axi_rddata_int_inferred_i_54__0_n_0; + wire ip2axi_rddata_int_inferred_i_54_n_0; + wire ip2axi_rddata_int_inferred_i_55__0_n_0; + wire ip2axi_rddata_int_inferred_i_55_n_0; + wire ip2axi_rddata_int_inferred_i_56__0_n_0; + wire ip2axi_rddata_int_inferred_i_56_n_0; + wire ip2axi_rddata_int_inferred_i_57__0_n_0; + wire ip2axi_rddata_int_inferred_i_57_n_0; + wire ip2axi_rddata_int_inferred_i_58__0_n_0; + wire ip2axi_rddata_int_inferred_i_58_n_0; + wire ip2axi_rddata_int_inferred_i_59__0_n_0; + wire ip2axi_rddata_int_inferred_i_60__0_n_0; + wire ip2axi_rddata_int_inferred_i_61__0_n_0; + wire ip2axi_rddata_int_inferred_i_62__0_n_0; + wire ip2axi_rddata_int_inferred_i_63__0_n_0; + wire ip2axi_rddata_int_inferred_i_64__0_n_0; + wire ip2axi_rddata_int_inferred_i_65__0_n_0; + wire ip2axi_rddata_int_inferred_i_66__0_n_0; + wire ip2axi_rddata_int_inferred_i_67__0_n_0; + wire ip2axi_rddata_int_inferred_i_67_n_0; + wire ip2axi_rddata_int_inferred_i_68__0_n_0; + wire ip2axi_rddata_int_inferred_i_69__0_n_0; + wire ip2axi_rddata_int_inferred_i_69_n_0; + wire ip2axi_rddata_int_inferred_i_70__0_n_0; + wire ip2axi_rddata_int_inferred_i_71__0_n_0; + wire ip2axi_rddata_int_inferred_i_71_n_0; + wire ip2axi_rddata_int_inferred_i_72__0_n_0; + wire ip2axi_rddata_int_inferred_i_73__0_n_0; + wire ip2axi_rddata_int_inferred_i_74__0_n_0; + wire ip2axi_rddata_int_inferred_i_75__0_n_0; + wire ip2axi_rddata_int_inferred_i_76__0_n_0; + wire ip2axi_rddata_int_inferred_i_76_n_0; + wire ip2axi_rddata_int_inferred_i_77__0_n_0; + wire ip2axi_rddata_int_inferred_i_78__0_n_0; + wire ip2axi_rddata_int_inferred_i_78_n_0; + wire ip2axi_rddata_int_inferred_i_79__0_n_0; + wire ip2axi_rddata_int_inferred_i_80__0_n_0; + wire ip2axi_rddata_int_inferred_i_81_n_0; + wire ip2axi_rddata_int_inferred_i_82_n_0; + wire ip2axi_rddata_int_inferred_i_83_n_0; + wire ip2axi_rddata_int_inferred_i_84_n_0; + wire ip2axi_rddata_int_inferred_i_85_n_0; + wire ip2axi_rddata_int_inferred_i_86_n_0; + wire ip2axi_rddata_int_inferred_i_87_n_0; + wire ip2axi_rddata_int_inferred_i_88_n_0; + wire ip2axi_rddata_int_inferred_i_89_n_0; + wire ip2axi_rddata_int_inferred_i_90_n_0; + wire lite_wr_addr_phase_finished_data_phase_started; + wire lite_wr_addr_phase_finished_data_phase_started_i_1_n_0; + wire lsize_err_reg; + wire lsize_err_reg_0; + wire lsize_mismatch_err; + wire lsize_more_err_reg; + wire lsize_more_err_reg_0; + wire lsize_more_mismatch_err; + wire m_axi_mm2s_aclk; + wire m_axi_s2mm_aclk; + wire [8:0]mm2s_axi2ip_wrce; + (* async_reg = "true" *) wire [31:0]mm2s_axi2ip_wrdata_cdc_tig; + wire mm2s_ioc_irq_set; + wire [31:0]mm2s_ip2axi_rddata_d1; + wire mm2s_prmry_resetn; + wire p_14_out; + wire p_15_out; + wire [5:0]p_2_in__0; + wire [3:2]p_4_in; + wire p_70_out; + wire [17:0]p_71_out; + wire prepare_wrce; + wire prepare_wrce_d1; + wire prepare_wrce_pulse_lite_d6; + wire prmry_reset2; + wire prmry_reset2_0; + wire prmtr_updt_complete_i_reg; + wire prmtr_updt_complete_i_reg_0; + wire read_has_started_i; + wire read_has_started_i_i_1_n_0; + wire \reg_module_hsize_reg[0] ; + wire \reg_module_hsize_reg[10] ; + wire \reg_module_hsize_reg[11] ; + wire \reg_module_hsize_reg[12] ; + wire [2:0]\reg_module_hsize_reg[15] ; + wire [15:0]\reg_module_hsize_reg[15]_0 ; + wire \reg_module_hsize_reg[3] ; + wire \reg_module_hsize_reg[4] ; + wire \reg_module_hsize_reg[5] ; + wire \reg_module_hsize_reg[6] ; + wire \reg_module_hsize_reg[7] ; + wire \reg_module_hsize_reg[8] ; + wire \reg_module_hsize_reg[9] ; + wire [12:0]\reg_module_vsize_reg[12] ; + wire [7:0]s2mm_axi2ip_wrce; + (* async_reg = "true" *) wire [31:0]s2mm_axi2ip_wrdata_cdc_tig; + wire s2mm_dma_interr_set_minus_frame_errors; + wire [22:0]s2mm_dmacr; + wire [0:0]s2mm_dmasr; + wire s2mm_fsize_more_or_sof_late; + wire s2mm_ioc_irq_set; + wire [31:0]s2mm_ip2axi_rddata_d1; + wire s2mm_prmry_resetn; + wire s2mm_soft_reset; + wire s_axi_lite_aclk; + wire [5:0]s_axi_lite_araddr; + wire s_axi_lite_arready; + wire s_axi_lite_arvalid; + wire [5:0]s_axi_lite_awaddr; + wire s_axi_lite_awready; + wire s_axi_lite_awvalid; + wire s_axi_lite_bready; + wire s_axi_lite_bvalid; + wire [31:0]s_axi_lite_rdata; + wire s_axi_lite_resetn; + wire s_axi_lite_rready; + wire s_axi_lite_rvalid; + wire [31:0]s_axi_lite_wdata; + wire s_axi_lite_wready; + wire s_axi_lite_wvalid; + wire sig_arvalid_arrived_d1; + wire sig_arvalid_arrived_d1_i_1_n_0; + wire sig_arvalid_arrived_d4; + wire sig_arvalid_detected__0; + wire sig_awvalid_arrived_d1; + wire sig_awvalid_arrived_d1_i_1_n_0; + wire sig_awvalid_detected__0; + wire stop; + wire [31:0]wdata; + wire write_has_started; + wire write_has_started_i_1_n_0; + wire wvalid; + + assign D[31:0] = mm2s_axi2ip_wrdata_cdc_tig; + assign \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31] [31:0] = s2mm_axi2ip_wrdata_cdc_tig; + assign out[1:0] = axi2ip_rdaddr_captured_mm2s_cdc_tig[3:2]; + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized6 \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.LITE_WVALID_MM2S_CDC_I + (.D({mm2s_axi2ip_wrdata_cdc_tig[23:16],mm2s_axi2ip_wrdata_cdc_tig[13:12],mm2s_axi2ip_wrdata_cdc_tig[0]}), + .\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] (\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] ), + .\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_reg (\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_reg ), + .SR(SR), + .ch1_dly_irq_set(ch1_dly_irq_set), + .dly_irq_reg(dly_irq_reg), + .dly_irq_reg_0(dly_irq_reg_1), + .dmacr_i(dmacr_i), + .ioc_irq_reg(ioc_irq_reg), + .ioc_irq_reg_0(ioc_irq_reg_1), + .lite_wr_addr_phase_finished_data_phase_started(lite_wr_addr_phase_finished_data_phase_started), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .mm2s_axi2ip_wrce(mm2s_axi2ip_wrce), + .mm2s_ioc_irq_set(mm2s_ioc_irq_set), + .mm2s_prmry_resetn(mm2s_prmry_resetn), + .out(axi2ip_wraddr_captured_mm2s_cdc_tig), + .p_71_out(p_71_out[0]), + .prepare_wrce_d1(prepare_wrce_d1), + .prmry_reset2(prmry_reset2), + .prmtr_updt_complete_i_reg(prmtr_updt_complete_i_reg), + .s_axi_lite_aclk(s_axi_lite_aclk), + .stop(stop), + .wvalid(wvalid)); + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized7 \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.LITE_WVALID_S2MM_CDC_I + (.\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31] (\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31]_0 ), + .\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] (\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]_0 ), + .\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[23] (\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[23] ), + .\GEN_FOR_FLUSH.fsize_err_reg (\GEN_FOR_FLUSH.fsize_err_reg ), + .\GEN_FOR_FLUSH.fsize_err_reg_0 (\GEN_FOR_FLUSH.fsize_err_reg_0 ), + .\GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg (\GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg ), + .\GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg_0 (\GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg_0 ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] ({s2mm_axi2ip_wrdata_cdc_tig[29:15],s2mm_axi2ip_wrdata_cdc_tig[13:11],s2mm_axi2ip_wrdata_cdc_tig[8:7],s2mm_axi2ip_wrdata_cdc_tig[4]}), + .SR(SR), + .ch2_dly_irq_set(ch2_dly_irq_set), + .dly_irq_reg(dly_irq_reg_0), + .dly_irq_reg_0(dly_irq_reg_2), + .dma_interr_reg(dma_interr_reg), + .dma_interr_reg_0(dma_interr_reg_0), + .dma_interr_reg_1(dma_interr_reg_2), + .\dmacr_i_reg[1] (\dmacr_i_reg[1] ), + .fsize_mismatch_err(fsize_mismatch_err), + .ioc_irq_reg(ioc_irq_reg_0), + .ioc_irq_reg_0(ioc_irq_reg_2), + .lite_wr_addr_phase_finished_data_phase_started(lite_wr_addr_phase_finished_data_phase_started), + .lsize_err_reg(lsize_err_reg), + .lsize_err_reg_0(lsize_err_reg_0), + .lsize_mismatch_err(lsize_mismatch_err), + .lsize_more_err_reg(lsize_more_err_reg), + .lsize_more_err_reg_0(lsize_more_err_reg_0), + .lsize_more_mismatch_err(lsize_more_mismatch_err), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(axi2ip_wraddr_captured_s2mm_cdc_tig), + .p_14_out(p_14_out), + .p_15_out(p_15_out), + .prepare_wrce_d1(prepare_wrce_d1), + .prmry_reset2_0(prmry_reset2_0), + .prmtr_updt_complete_i_reg(prmtr_updt_complete_i_reg_0), + .s2mm_axi2ip_wrce(s2mm_axi2ip_wrce), + .s2mm_dma_interr_set_minus_frame_errors(s2mm_dma_interr_set_minus_frame_errors), + .s2mm_dmacr({s2mm_dmacr[20:15],s2mm_dmacr[12:7],s2mm_dmacr[0]}), + .s2mm_fsize_more_or_sof_late(s2mm_fsize_more_or_sof_late), + .s2mm_ioc_irq_set(s2mm_ioc_irq_set), + .s2mm_prmry_resetn(s2mm_prmry_resetn), + .s_axi_lite_aclk(s_axi_lite_aclk), + .wvalid(wvalid)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.arready_out_i_reg + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(sig_arvalid_arrived_d4), + .Q(s_axi_lite_arready), + .R(SR)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(p_4_in[2]), + .Q(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(p_4_in[3]), + .Q(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\axi2ip_rdaddr_captured_reg_n_0_[4] ), + .Q(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\axi2ip_rdaddr_captured_reg_n_0_[5] ), + .Q(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[6] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\axi2ip_rdaddr_captured_reg_n_0_[6] ), + .Q(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\axi2ip_rdaddr_captured_reg_n_0_[7] ), + .Q(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_s2mm_cdc_tig_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(p_4_in[2]), + .Q(axi2ip_rdaddr_captured_s2mm_cdc_tig[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_s2mm_cdc_tig_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(p_4_in[3]), + .Q(axi2ip_rdaddr_captured_s2mm_cdc_tig[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_s2mm_cdc_tig_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\axi2ip_rdaddr_captured_reg_n_0_[4] ), + .Q(axi2ip_rdaddr_captured_s2mm_cdc_tig[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_s2mm_cdc_tig_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\axi2ip_rdaddr_captured_reg_n_0_[5] ), + .Q(axi2ip_rdaddr_captured_s2mm_cdc_tig[5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_s2mm_cdc_tig_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\axi2ip_rdaddr_captured_reg_n_0_[6] ), + .Q(axi2ip_rdaddr_captured_s2mm_cdc_tig[6]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_s2mm_cdc_tig_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\axi2ip_rdaddr_captured_reg_n_0_[7] ), + .Q(axi2ip_rdaddr_captured_s2mm_cdc_tig[7]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(axi2ip_wraddr_captured[2]), + .Q(axi2ip_wraddr_captured_mm2s_cdc_tig[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(axi2ip_wraddr_captured[3]), + .Q(axi2ip_wraddr_captured_mm2s_cdc_tig[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(axi2ip_wraddr_captured[4]), + .Q(axi2ip_wraddr_captured_mm2s_cdc_tig[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(axi2ip_wraddr_captured[5]), + .Q(axi2ip_wraddr_captured_mm2s_cdc_tig[5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[6] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(axi2ip_wraddr_captured[6]), + .Q(axi2ip_wraddr_captured_mm2s_cdc_tig[6]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(axi2ip_wraddr_captured[7]), + .Q(axi2ip_wraddr_captured_mm2s_cdc_tig[7]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(axi2ip_wraddr_captured[2]), + .Q(axi2ip_wraddr_captured_s2mm_cdc_tig[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(axi2ip_wraddr_captured[3]), + .Q(axi2ip_wraddr_captured_s2mm_cdc_tig[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(axi2ip_wraddr_captured[4]), + .Q(axi2ip_wraddr_captured_s2mm_cdc_tig[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(axi2ip_wraddr_captured[5]), + .Q(axi2ip_wraddr_captured_s2mm_cdc_tig[5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(axi2ip_wraddr_captured[6]), + .Q(axi2ip_wraddr_captured_s2mm_cdc_tig[6]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(axi2ip_wraddr_captured[7]), + .Q(axi2ip_wraddr_captured_s2mm_cdc_tig[7]), + .R(1'b0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[0]_i_1 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0 ), + .I1(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] [0]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0 ), + .I3(ip2axi_rddata_captured_mm2s_cdc_tig[0]), + .I4(ip2axi_rddata_captured_s2mm_cdc_tig[0]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0 ), + .O(ip2axi_rddata_captured[0])); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[10]_i_1 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0 ), + .I1(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4] [2]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0 ), + .I3(ip2axi_rddata_captured_mm2s_cdc_tig[10]), + .I4(ip2axi_rddata_captured_s2mm_cdc_tig[10]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0 ), + .O(ip2axi_rddata_captured[10])); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[11]_i_1 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0 ), + .I1(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4] [3]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0 ), + .I3(ip2axi_rddata_captured_mm2s_cdc_tig[11]), + .I4(ip2axi_rddata_captured_s2mm_cdc_tig[11]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0 ), + .O(ip2axi_rddata_captured[11])); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[12]_i_1 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0 ), + .I1(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4] [4]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0 ), + .I3(ip2axi_rddata_captured_mm2s_cdc_tig[12]), + .I4(ip2axi_rddata_captured_s2mm_cdc_tig[12]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0 ), + .O(ip2axi_rddata_captured[12])); + LUT6 #( + .INIT(64'h0AAAAACCCCCAA0CC)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[13]_i_1 + (.I0(ip2axi_rddata_captured_s2mm_cdc_tig[13]), + .I1(ip2axi_rddata_captured_mm2s_cdc_tig[13]), + .I2(\axi2ip_rdaddr_captured_reg_n_0_[4] ), + .I3(\axi2ip_rdaddr_captured_reg_n_0_[5] ), + .I4(\axi2ip_rdaddr_captured_reg_n_0_[6] ), + .I5(\axi2ip_rdaddr_captured_reg_n_0_[7] ), + .O(ip2axi_rddata_captured[13])); + LUT6 #( + .INIT(64'h0AAAAACCCCCAA0CC)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[14]_i_1 + (.I0(ip2axi_rddata_captured_s2mm_cdc_tig[14]), + .I1(ip2axi_rddata_captured_mm2s_cdc_tig[14]), + .I2(\axi2ip_rdaddr_captured_reg_n_0_[4] ), + .I3(\axi2ip_rdaddr_captured_reg_n_0_[5] ), + .I4(\axi2ip_rdaddr_captured_reg_n_0_[6] ), + .I5(\axi2ip_rdaddr_captured_reg_n_0_[7] ), + .O(ip2axi_rddata_captured[14])); + LUT6 #( + .INIT(64'h0AAAAACCCCCAA0CC)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[15]_i_1 + (.I0(ip2axi_rddata_captured_s2mm_cdc_tig[15]), + .I1(ip2axi_rddata_captured_mm2s_cdc_tig[15]), + .I2(\axi2ip_rdaddr_captured_reg_n_0_[4] ), + .I3(\axi2ip_rdaddr_captured_reg_n_0_[5] ), + .I4(\axi2ip_rdaddr_captured_reg_n_0_[6] ), + .I5(\axi2ip_rdaddr_captured_reg_n_0_[7] ), + .O(ip2axi_rddata_captured[15])); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[16]_i_1 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0 ), + .I1(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] [0]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0 ), + .I3(ip2axi_rddata_captured_mm2s_cdc_tig[16]), + .I4(ip2axi_rddata_captured_s2mm_cdc_tig[16]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0 ), + .O(ip2axi_rddata_captured[16])); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[17]_i_1 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0 ), + .I1(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] [1]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0 ), + .I3(ip2axi_rddata_captured_mm2s_cdc_tig[17]), + .I4(ip2axi_rddata_captured_s2mm_cdc_tig[17]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0 ), + .O(ip2axi_rddata_captured[17])); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[18]_i_1 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0 ), + .I1(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] [2]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0 ), + .I3(ip2axi_rddata_captured_mm2s_cdc_tig[18]), + .I4(ip2axi_rddata_captured_s2mm_cdc_tig[18]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0 ), + .O(ip2axi_rddata_captured[18])); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[19]_i_1 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0 ), + .I1(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] [3]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0 ), + .I3(ip2axi_rddata_captured_mm2s_cdc_tig[19]), + .I4(ip2axi_rddata_captured_s2mm_cdc_tig[19]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0 ), + .O(ip2axi_rddata_captured[19])); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[1]_i_1 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0 ), + .I1(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] [1]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0 ), + .I3(ip2axi_rddata_captured_mm2s_cdc_tig[1]), + .I4(ip2axi_rddata_captured_s2mm_cdc_tig[1]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0 ), + .O(ip2axi_rddata_captured[1])); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[20]_i_1 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0 ), + .I1(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] [4]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0 ), + .I3(ip2axi_rddata_captured_mm2s_cdc_tig[20]), + .I4(ip2axi_rddata_captured_s2mm_cdc_tig[20]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0 ), + .O(ip2axi_rddata_captured[20])); + LUT6 #( + .INIT(64'h0AAAAACCCCCAA0CC)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[21]_i_1 + (.I0(ip2axi_rddata_captured_s2mm_cdc_tig[21]), + .I1(ip2axi_rddata_captured_mm2s_cdc_tig[21]), + .I2(\axi2ip_rdaddr_captured_reg_n_0_[4] ), + .I3(\axi2ip_rdaddr_captured_reg_n_0_[5] ), + .I4(\axi2ip_rdaddr_captured_reg_n_0_[6] ), + .I5(\axi2ip_rdaddr_captured_reg_n_0_[7] ), + .O(ip2axi_rddata_captured[21])); + LUT6 #( + .INIT(64'h0AAAAACCCCCAA0CC)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[22]_i_1 + (.I0(ip2axi_rddata_captured_s2mm_cdc_tig[22]), + .I1(ip2axi_rddata_captured_mm2s_cdc_tig[22]), + .I2(\axi2ip_rdaddr_captured_reg_n_0_[4] ), + .I3(\axi2ip_rdaddr_captured_reg_n_0_[5] ), + .I4(\axi2ip_rdaddr_captured_reg_n_0_[6] ), + .I5(\axi2ip_rdaddr_captured_reg_n_0_[7] ), + .O(ip2axi_rddata_captured[22])); + LUT6 #( + .INIT(64'h0AAAAACCCCCAA0CC)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[23]_i_1 + (.I0(ip2axi_rddata_captured_s2mm_cdc_tig[23]), + .I1(ip2axi_rddata_captured_mm2s_cdc_tig[23]), + .I2(\axi2ip_rdaddr_captured_reg_n_0_[4] ), + .I3(\axi2ip_rdaddr_captured_reg_n_0_[5] ), + .I4(\axi2ip_rdaddr_captured_reg_n_0_[6] ), + .I5(\axi2ip_rdaddr_captured_reg_n_0_[7] ), + .O(ip2axi_rddata_captured[23])); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[24]_i_1 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0 ), + .I1(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4] [0]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0 ), + .I3(ip2axi_rddata_captured_mm2s_cdc_tig[24]), + .I4(ip2axi_rddata_captured_s2mm_cdc_tig[24]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0 ), + .O(ip2axi_rddata_captured[24])); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFF888)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[25]_i_1 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0 ), + .I1(ip2axi_rddata_captured_mm2s_cdc_tig[25]), + .I2(ip2axi_rddata_captured_s2mm_cdc_tig[25]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0 ), + .I4(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[25]_i_2_n_0 ), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0 ), + .O(ip2axi_rddata_captured[25])); + LUT6 #( + .INIT(64'h0010000000000000)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[25]_i_2 + (.I0(\axi2ip_rdaddr_captured_reg_n_0_[7] ), + .I1(\axi2ip_rdaddr_captured_reg_n_0_[6] ), + .I2(\axi2ip_rdaddr_captured_reg_n_0_[5] ), + .I3(\axi2ip_rdaddr_captured_reg_n_0_[4] ), + .I4(p_4_in[3]), + .I5(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4] [1]), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[25]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[26]_i_1 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0 ), + .I1(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4] [2]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0 ), + .I3(ip2axi_rddata_captured_mm2s_cdc_tig[26]), + .I4(ip2axi_rddata_captured_s2mm_cdc_tig[26]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0 ), + .O(ip2axi_rddata_captured[26])); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[27]_i_1 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0 ), + .I1(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4] [3]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0 ), + .I3(ip2axi_rddata_captured_mm2s_cdc_tig[27]), + .I4(ip2axi_rddata_captured_s2mm_cdc_tig[27]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0 ), + .O(ip2axi_rddata_captured[27])); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_1 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0 ), + .I1(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4] [4]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0 ), + .I3(ip2axi_rddata_captured_mm2s_cdc_tig[28]), + .I4(ip2axi_rddata_captured_s2mm_cdc_tig[28]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0 ), + .O(ip2axi_rddata_captured[28])); + LUT6 #( + .INIT(64'h0000000000100000)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2 + (.I0(\axi2ip_rdaddr_captured_reg_n_0_[7] ), + .I1(\axi2ip_rdaddr_captured_reg_n_0_[6] ), + .I2(\axi2ip_rdaddr_captured_reg_n_0_[5] ), + .I3(\axi2ip_rdaddr_captured_reg_n_0_[4] ), + .I4(p_4_in[3]), + .I5(p_4_in[2]), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0 )); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[29]_i_1 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0 ), + .I1(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0 ), + .I2(ip2axi_rddata_captured_s2mm_cdc_tig[29]), + .I3(ip2axi_rddata_captured_mm2s_cdc_tig[29]), + .I4(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0 ), + .O(ip2axi_rddata_captured[29])); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[2]_i_1 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0 ), + .I1(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] [2]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0 ), + .I3(ip2axi_rddata_captured_mm2s_cdc_tig[2]), + .I4(ip2axi_rddata_captured_s2mm_cdc_tig[2]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0 ), + .O(ip2axi_rddata_captured[2])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_1 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0 ), + .I1(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0 ), + .I2(ip2axi_rddata_captured_s2mm_cdc_tig[30]), + .I3(ip2axi_rddata_captured_mm2s_cdc_tig[30]), + .I4(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0 ), + .O(ip2axi_rddata_captured[30])); + LUT6 #( + .INIT(64'h0010000000000000)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2 + (.I0(\axi2ip_rdaddr_captured_reg_n_0_[7] ), + .I1(\axi2ip_rdaddr_captured_reg_n_0_[6] ), + .I2(\axi2ip_rdaddr_captured_reg_n_0_[5] ), + .I3(\axi2ip_rdaddr_captured_reg_n_0_[4] ), + .I4(p_4_in[3]), + .I5(p_4_in[2]), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT4 #( + .INIT(16'h38AC)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3 + (.I0(\axi2ip_rdaddr_captured_reg_n_0_[7] ), + .I1(\axi2ip_rdaddr_captured_reg_n_0_[6] ), + .I2(\axi2ip_rdaddr_captured_reg_n_0_[5] ), + .I3(\axi2ip_rdaddr_captured_reg_n_0_[4] ), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT4 #( + .INIT(16'h03E3)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4 + (.I0(\axi2ip_rdaddr_captured_reg_n_0_[4] ), + .I1(\axi2ip_rdaddr_captured_reg_n_0_[5] ), + .I2(\axi2ip_rdaddr_captured_reg_n_0_[6] ), + .I3(\axi2ip_rdaddr_captured_reg_n_0_[7] ), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0 )); + LUT6 #( + .INIT(64'h0AAAAACCCCCAA0CC)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1 + (.I0(ip2axi_rddata_captured_s2mm_cdc_tig[31]), + .I1(ip2axi_rddata_captured_mm2s_cdc_tig[31]), + .I2(\axi2ip_rdaddr_captured_reg_n_0_[4] ), + .I3(\axi2ip_rdaddr_captured_reg_n_0_[5] ), + .I4(\axi2ip_rdaddr_captured_reg_n_0_[6] ), + .I5(\axi2ip_rdaddr_captured_reg_n_0_[7] ), + .O(ip2axi_rddata_captured[31])); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[3]_i_1 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0 ), + .I1(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] [3]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0 ), + .I3(ip2axi_rddata_captured_mm2s_cdc_tig[3]), + .I4(ip2axi_rddata_captured_s2mm_cdc_tig[3]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0 ), + .O(ip2axi_rddata_captured[3])); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFF888)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[4]_i_1 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0 ), + .I1(ip2axi_rddata_captured_mm2s_cdc_tig[4]), + .I2(ip2axi_rddata_captured_s2mm_cdc_tig[4]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0 ), + .I4(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[4]_i_2_n_0 ), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0 ), + .O(ip2axi_rddata_captured[4])); + LUT6 #( + .INIT(64'h0010000000000000)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[4]_i_2 + (.I0(\axi2ip_rdaddr_captured_reg_n_0_[7] ), + .I1(\axi2ip_rdaddr_captured_reg_n_0_[6] ), + .I2(\axi2ip_rdaddr_captured_reg_n_0_[5] ), + .I3(\axi2ip_rdaddr_captured_reg_n_0_[4] ), + .I4(p_4_in[3]), + .I5(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] [4]), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[4]_i_2_n_0 )); + LUT6 #( + .INIT(64'h0AAAAACCCCCAA0CC)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[5]_i_1 + (.I0(ip2axi_rddata_captured_s2mm_cdc_tig[5]), + .I1(ip2axi_rddata_captured_mm2s_cdc_tig[5]), + .I2(\axi2ip_rdaddr_captured_reg_n_0_[4] ), + .I3(\axi2ip_rdaddr_captured_reg_n_0_[5] ), + .I4(\axi2ip_rdaddr_captured_reg_n_0_[6] ), + .I5(\axi2ip_rdaddr_captured_reg_n_0_[7] ), + .O(ip2axi_rddata_captured[5])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[6]_i_1 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0 ), + .I1(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0 ), + .I2(ip2axi_rddata_captured_s2mm_cdc_tig[6]), + .I3(ip2axi_rddata_captured_mm2s_cdc_tig[6]), + .I4(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0 ), + .O(ip2axi_rddata_captured[6])); + LUT6 #( + .INIT(64'h0AAAAACCCCCAA0CC)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[7]_i_1 + (.I0(ip2axi_rddata_captured_s2mm_cdc_tig[7]), + .I1(ip2axi_rddata_captured_mm2s_cdc_tig[7]), + .I2(\axi2ip_rdaddr_captured_reg_n_0_[4] ), + .I3(\axi2ip_rdaddr_captured_reg_n_0_[5] ), + .I4(\axi2ip_rdaddr_captured_reg_n_0_[6] ), + .I5(\axi2ip_rdaddr_captured_reg_n_0_[7] ), + .O(ip2axi_rddata_captured[7])); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[8]_i_1 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0 ), + .I1(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4] [0]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0 ), + .I3(ip2axi_rddata_captured_mm2s_cdc_tig[8]), + .I4(ip2axi_rddata_captured_s2mm_cdc_tig[8]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0 ), + .O(ip2axi_rddata_captured[8])); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[9]_i_1 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0 ), + .I1(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4] [1]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0 ), + .I3(ip2axi_rddata_captured_mm2s_cdc_tig[9]), + .I4(ip2axi_rddata_captured_s2mm_cdc_tig[9]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0 ), + .O(ip2axi_rddata_captured[9])); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[0] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[0]), + .Q(s_axi_lite_rdata[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[10] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[10]), + .Q(s_axi_lite_rdata[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[11] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[11]), + .Q(s_axi_lite_rdata[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[12] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[12]), + .Q(s_axi_lite_rdata[12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[13] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[13]), + .Q(s_axi_lite_rdata[13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[14] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[14]), + .Q(s_axi_lite_rdata[14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[15] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[15]), + .Q(s_axi_lite_rdata[15]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[16] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[16]), + .Q(s_axi_lite_rdata[16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[17] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[17]), + .Q(s_axi_lite_rdata[17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[18] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[18]), + .Q(s_axi_lite_rdata[18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[19] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[19]), + .Q(s_axi_lite_rdata[19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[1] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[1]), + .Q(s_axi_lite_rdata[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[20] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[20]), + .Q(s_axi_lite_rdata[20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[21] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[21]), + .Q(s_axi_lite_rdata[21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[22] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[22]), + .Q(s_axi_lite_rdata[22]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[23] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[23]), + .Q(s_axi_lite_rdata[23]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[24] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[24]), + .Q(s_axi_lite_rdata[24]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[25] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[25]), + .Q(s_axi_lite_rdata[25]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[26] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[26]), + .Q(s_axi_lite_rdata[26]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[27] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[27]), + .Q(s_axi_lite_rdata[27]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[28] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[28]), + .Q(s_axi_lite_rdata[28]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[29] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[29]), + .Q(s_axi_lite_rdata[29]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[2] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[2]), + .Q(s_axi_lite_rdata[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[30] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[30]), + .Q(s_axi_lite_rdata[30]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[31] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[31]), + .Q(s_axi_lite_rdata[31]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[3] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[3]), + .Q(s_axi_lite_rdata[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[4] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[4]), + .Q(s_axi_lite_rdata[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[5] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[5]), + .Q(s_axi_lite_rdata[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[6] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[6]), + .Q(s_axi_lite_rdata[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[7] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[7]), + .Q(s_axi_lite_rdata[7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[8] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[8]), + .Q(s_axi_lite_rdata[8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[9] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(ip2axi_rddata_captured[9]), + .Q(s_axi_lite_rdata[9]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[0] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[0]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[10] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[10]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[10]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[11] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[11]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[11]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[12] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[12]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[12]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[13] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[13]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[13]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[14] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[14]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[14]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[15] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[15]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[15]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[16] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[16]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[16]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[17] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[17]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[17]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[18] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[18]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[18]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[19] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[19]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[19]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[1] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[1]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[20] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[20]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[20]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[21] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[21]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[21]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[22] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[22]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[22]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[23] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[23]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[23]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[24] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[24]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[24]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[25] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[25]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[25]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[26] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[26]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[26]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[27] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[27]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[27]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[28] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[28]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[28]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[29] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[29]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[29]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[2] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[2]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[30] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[30]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[30]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[31] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[31]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[31]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[3] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[3]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[4] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[4]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[5] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[5]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[6] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[6]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[6]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[7] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[7]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[7]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[8] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[8]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[8]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[9] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(mm2s_ip2axi_rddata_d1[9]), + .Q(ip2axi_rddata_captured_mm2s_cdc_tig[9]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[0] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[0]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[10] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[10]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[10]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[11] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[11]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[11]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[12] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[12]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[12]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[13] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[13]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[13]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[14] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[14]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[14]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[15] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[15]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[15]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[16] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[16]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[16]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[17] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[17]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[17]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[18] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[18]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[18]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[19] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[19]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[19]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[1] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[1]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[20] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[20]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[20]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[21] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[21]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[21]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[22] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[22]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[22]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[23] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[23]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[23]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[24] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[24]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[24]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[25] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[25]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[25]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[26] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[26]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[26]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[27] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[27]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[27]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[28] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[28]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[28]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[29] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[29]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[29]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[2] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[2]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[30] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[30]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[30]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[31] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[31]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[31]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[3] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[3]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[4] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[4]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[5] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[5]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[6] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[6]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[6]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[7] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[7]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[7]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[8] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[8]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[8]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[9] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s2mm_ip2axi_rddata_d1[9]), + .Q(ip2axi_rddata_captured_s2mm_cdc_tig[9]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[0]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[10] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[10]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[10]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[11] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[11]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[11]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[12]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[12]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[13]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[13]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[14] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[14]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[14]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[15] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[15]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[15]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[16] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[16]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[16]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[17] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[17]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[17]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[18]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[18]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[19] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[19]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[19]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[1]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[20] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[20]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[20]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[21] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[21]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[21]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[22] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[22]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[22]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[23] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[23]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[23]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[24] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[24]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[24]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[25] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[25]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[25]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[26] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[26]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[26]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[27] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[27]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[27]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[28] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[28]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[28]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[29] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[29]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[29]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[2]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[30] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[30]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[30]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[31] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[31]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[31]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[3]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[4]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[5]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[6] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[6]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[6]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[7]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[7]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[8] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[8]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[8]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[9] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(wdata[9]), + .Q(mm2s_axi2ip_wrdata_cdc_tig[9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [0]), + .Q(mm2s_ip2axi_rddata_d1[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [10]), + .Q(mm2s_ip2axi_rddata_d1[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [11]), + .Q(mm2s_ip2axi_rddata_d1[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [12]), + .Q(mm2s_ip2axi_rddata_d1[12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[13] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [13]), + .Q(mm2s_ip2axi_rddata_d1[13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[14] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [14]), + .Q(mm2s_ip2axi_rddata_d1[14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [15]), + .Q(mm2s_ip2axi_rddata_d1[15]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[16] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [16]), + .Q(mm2s_ip2axi_rddata_d1[16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[17] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [17]), + .Q(mm2s_ip2axi_rddata_d1[17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[18] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [18]), + .Q(mm2s_ip2axi_rddata_d1[18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[19] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [19]), + .Q(mm2s_ip2axi_rddata_d1[19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [1]), + .Q(mm2s_ip2axi_rddata_d1[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[20] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [20]), + .Q(mm2s_ip2axi_rddata_d1[20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[21] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [21]), + .Q(mm2s_ip2axi_rddata_d1[21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[22] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [22]), + .Q(mm2s_ip2axi_rddata_d1[22]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[23] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [23]), + .Q(mm2s_ip2axi_rddata_d1[23]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[24] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [24]), + .Q(mm2s_ip2axi_rddata_d1[24]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[25] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [25]), + .Q(mm2s_ip2axi_rddata_d1[25]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[26] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [26]), + .Q(mm2s_ip2axi_rddata_d1[26]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[27] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [27]), + .Q(mm2s_ip2axi_rddata_d1[27]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[28] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [28]), + .Q(mm2s_ip2axi_rddata_d1[28]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[29] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [29]), + .Q(mm2s_ip2axi_rddata_d1[29]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [2]), + .Q(mm2s_ip2axi_rddata_d1[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[30] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [30]), + .Q(mm2s_ip2axi_rddata_d1[30]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [31]), + .Q(mm2s_ip2axi_rddata_d1[31]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [3]), + .Q(mm2s_ip2axi_rddata_d1[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [4]), + .Q(mm2s_ip2axi_rddata_d1[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [5]), + .Q(mm2s_ip2axi_rddata_d1[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [6]), + .Q(mm2s_ip2axi_rddata_d1[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [7]), + .Q(mm2s_ip2axi_rddata_d1[7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [8]), + .Q(mm2s_ip2axi_rddata_d1[8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 [9]), + .Q(mm2s_ip2axi_rddata_d1[9]), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT2 #( + .INIT(4'h8)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.prepare_wrce_d1_i_1 + (.I0(lite_wr_addr_phase_finished_data_phase_started), + .I1(wvalid), + .O(prepare_wrce)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.prepare_wrce_d1_reg + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(prepare_wrce), + .Q(prepare_wrce_d1), + .R(SR)); + (* srl_name = "U0/\AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.prepare_wrce_pulse_lite_d6_reg_srl6 " *) + SRL16E #( + .INIT(16'h0000)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.prepare_wrce_pulse_lite_d6_reg_srl6 + (.A0(1'b1), + .A1(1'b0), + .A2(1'b1), + .A3(1'b0), + .CE(1'b1), + .CLK(s_axi_lite_aclk), + .D(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.prepare_wrce_pulse_lite_d6_reg_srl6_i_1_n_0 ), + .Q(prepare_wrce_pulse_lite_d6)); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT3 #( + .INIT(8'h08)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.prepare_wrce_pulse_lite_d6_reg_srl6_i_1 + (.I0(wvalid), + .I1(lite_wr_addr_phase_finished_data_phase_started), + .I2(prepare_wrce_d1), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.prepare_wrce_pulse_lite_d6_reg_srl6_i_1_n_0 )); + LUT4 #( + .INIT(16'h0C88)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.rvalid_out_i_i_1 + (.I0(s_axi_lite_arready), + .I1(s_axi_lite_resetn), + .I2(s_axi_lite_rready), + .I3(s_axi_lite_rvalid), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.rvalid_out_i_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.rvalid_out_i_reg + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.rvalid_out_i_i_1_n_0 ), + .Q(s_axi_lite_rvalid), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[0]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[10]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[10]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[11]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[11]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[12]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[12]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[13] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[13]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[13]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[14] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[14]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[14]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[15] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[15]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[15]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[16] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[16]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[16]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[17] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[17]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[17]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[18]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[18]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[19] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[19]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[19]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[1]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[20] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[20]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[20]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[21] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[21]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[21]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[22] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[22]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[22]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[23] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[23]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[23]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[24] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[24]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[24]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[25] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[25]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[25]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[26] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[26]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[26]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[27] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[27]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[27]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[28] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[28]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[28]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[29]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[29]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[2]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[30] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[30]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[30]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[31] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[31]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[31]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[3]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[4]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[5]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[6]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[6]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[7]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[7]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[8]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[8]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(wdata[9]), + .Q(s2mm_axi2ip_wrdata_cdc_tig[9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [0]), + .Q(s2mm_ip2axi_rddata_d1[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [10]), + .Q(s2mm_ip2axi_rddata_d1[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [11]), + .Q(s2mm_ip2axi_rddata_d1[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [12]), + .Q(s2mm_ip2axi_rddata_d1[12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[13] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [13]), + .Q(s2mm_ip2axi_rddata_d1[13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[14] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [14]), + .Q(s2mm_ip2axi_rddata_d1[14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[15] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [15]), + .Q(s2mm_ip2axi_rddata_d1[15]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[16] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [16]), + .Q(s2mm_ip2axi_rddata_d1[16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[17] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [17]), + .Q(s2mm_ip2axi_rddata_d1[17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[18] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [18]), + .Q(s2mm_ip2axi_rddata_d1[18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[19] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [19]), + .Q(s2mm_ip2axi_rddata_d1[19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [1]), + .Q(s2mm_ip2axi_rddata_d1[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[20] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [20]), + .Q(s2mm_ip2axi_rddata_d1[20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[21] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [21]), + .Q(s2mm_ip2axi_rddata_d1[21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[22] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [22]), + .Q(s2mm_ip2axi_rddata_d1[22]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[23] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [23]), + .Q(s2mm_ip2axi_rddata_d1[23]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[24] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [24]), + .Q(s2mm_ip2axi_rddata_d1[24]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[25] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [25]), + .Q(s2mm_ip2axi_rddata_d1[25]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[26] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [26]), + .Q(s2mm_ip2axi_rddata_d1[26]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[27] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [27]), + .Q(s2mm_ip2axi_rddata_d1[27]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[28] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [28]), + .Q(s2mm_ip2axi_rddata_d1[28]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[29] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [29]), + .Q(s2mm_ip2axi_rddata_d1[29]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [2]), + .Q(s2mm_ip2axi_rddata_d1[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[30] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [30]), + .Q(s2mm_ip2axi_rddata_d1[30]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [31]), + .Q(s2mm_ip2axi_rddata_d1[31]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [3]), + .Q(s2mm_ip2axi_rddata_d1[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [4]), + .Q(s2mm_ip2axi_rddata_d1[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [5]), + .Q(s2mm_ip2axi_rddata_d1[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [6]), + .Q(s2mm_ip2axi_rddata_d1[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [7]), + .Q(s2mm_ip2axi_rddata_d1[7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [8]), + .Q(s2mm_ip2axi_rddata_d1[8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 [9]), + .Q(s2mm_ip2axi_rddata_d1[9]), + .R(1'b0)); + (* srl_name = "U0/\AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.sig_arvalid_arrived_d4_reg_srl3 " *) + SRL16E #( + .INIT(16'h0000)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.sig_arvalid_arrived_d4_reg_srl3 + (.A0(1'b0), + .A1(1'b1), + .A2(1'b0), + .A3(1'b0), + .CE(1'b1), + .CLK(s_axi_lite_aclk), + .D(sig_arvalid_arrived_d1), + .Q(sig_arvalid_arrived_d4)); + FDRE #( + .INIT(1'b0)) + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.wready_out_i_reg + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(prepare_wrce_pulse_lite_d6), + .Q(s_axi_lite_wready), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \araddr_reg[2] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_araddr[0]), + .Q(p_2_in__0[0]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \araddr_reg[3] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_araddr[1]), + .Q(p_2_in__0[1]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \araddr_reg[4] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_araddr[2]), + .Q(p_2_in__0[2]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \araddr_reg[5] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_araddr[3]), + .Q(p_2_in__0[3]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \araddr_reg[6] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_araddr[4]), + .Q(p_2_in__0[4]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \araddr_reg[7] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_araddr[5]), + .Q(p_2_in__0[5]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + arvalid_reg + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_arvalid), + .Q(arvalid), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \awaddr_reg[2] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_awaddr[0]), + .Q(awaddr[2]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \awaddr_reg[3] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_awaddr[1]), + .Q(awaddr[3]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \awaddr_reg[4] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_awaddr[2]), + .Q(awaddr[4]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \awaddr_reg[5] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_awaddr[3]), + .Q(awaddr[5]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \awaddr_reg[6] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_awaddr[4]), + .Q(awaddr[6]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \awaddr_reg[7] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_awaddr[5]), + .Q(awaddr[7]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + awready_out_i_reg + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(sig_awvalid_detected__0), + .Q(s_axi_lite_awready), + .R(SR)); + FDRE #( + .INIT(1'b0)) + awvalid_reg + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_awvalid), + .Q(awvalid), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \axi2ip_rdaddr_captured_reg[2] + (.C(s_axi_lite_aclk), + .CE(sig_arvalid_detected__0), + .D(p_2_in__0[0]), + .Q(p_4_in[2]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \axi2ip_rdaddr_captured_reg[3] + (.C(s_axi_lite_aclk), + .CE(sig_arvalid_detected__0), + .D(p_2_in__0[1]), + .Q(p_4_in[3]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \axi2ip_rdaddr_captured_reg[4] + (.C(s_axi_lite_aclk), + .CE(sig_arvalid_detected__0), + .D(p_2_in__0[2]), + .Q(\axi2ip_rdaddr_captured_reg_n_0_[4] ), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \axi2ip_rdaddr_captured_reg[5] + (.C(s_axi_lite_aclk), + .CE(sig_arvalid_detected__0), + .D(p_2_in__0[3]), + .Q(\axi2ip_rdaddr_captured_reg_n_0_[5] ), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \axi2ip_rdaddr_captured_reg[6] + (.C(s_axi_lite_aclk), + .CE(sig_arvalid_detected__0), + .D(p_2_in__0[4]), + .Q(\axi2ip_rdaddr_captured_reg_n_0_[6] ), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \axi2ip_rdaddr_captured_reg[7] + (.C(s_axi_lite_aclk), + .CE(sig_arvalid_detected__0), + .D(p_2_in__0[5]), + .Q(\axi2ip_rdaddr_captured_reg_n_0_[7] ), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \axi2ip_wraddr_captured_reg[2] + (.C(s_axi_lite_aclk), + .CE(sig_awvalid_detected__0), + .D(awaddr[2]), + .Q(axi2ip_wraddr_captured[2]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \axi2ip_wraddr_captured_reg[3] + (.C(s_axi_lite_aclk), + .CE(sig_awvalid_detected__0), + .D(awaddr[3]), + .Q(axi2ip_wraddr_captured[3]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \axi2ip_wraddr_captured_reg[4] + (.C(s_axi_lite_aclk), + .CE(sig_awvalid_detected__0), + .D(awaddr[4]), + .Q(axi2ip_wraddr_captured[4]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \axi2ip_wraddr_captured_reg[5] + (.C(s_axi_lite_aclk), + .CE(sig_awvalid_detected__0), + .D(awaddr[5]), + .Q(axi2ip_wraddr_captured[5]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \axi2ip_wraddr_captured_reg[6] + (.C(s_axi_lite_aclk), + .CE(sig_awvalid_detected__0), + .D(awaddr[6]), + .Q(axi2ip_wraddr_captured[6]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \axi2ip_wraddr_captured_reg[7] + (.C(s_axi_lite_aclk), + .CE(sig_awvalid_detected__0), + .D(awaddr[7]), + .Q(axi2ip_wraddr_captured[7]), + .R(SR)); + LUT4 #( + .INIT(16'h0C88)) + bvalid_out_i_i_1 + (.I0(s_axi_lite_wready), + .I1(s_axi_lite_resetn), + .I2(s_axi_lite_bready), + .I3(s_axi_lite_bvalid), + .O(bvalid_out_i_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + bvalid_out_i_reg + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(bvalid_out_i_i_1_n_0), + .Q(s_axi_lite_bvalid), + .R(1'b0)); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_1 + (.I0(ip2axi_rddata_int_inferred_i_33_n_0), + .I1(ip2axi_rddata_int_inferred_i_34_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [18]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [28]), + .O(in0[28])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_10 + (.I0(ip2axi_rddata_int_inferred_i_44_n_0), + .I1(ip2axi_rddata_int_inferred_i_34_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [9]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [19]), + .O(in0[19])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_10__0 + (.I0(ip2axi_rddata_int_inferred_i_44__0_n_0), + .I1(ip2axi_rddata_int_inferred_i_34__0_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [22]), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [22]), + .I4(ip2axi_rddata_int_inferred_i_35__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [22])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_11 + (.I0(ip2axi_rddata_int_inferred_i_45_n_0), + .I1(ip2axi_rddata_int_inferred_i_34_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [8]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [18]), + .O(in0[18])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_11__0 + (.I0(ip2axi_rddata_int_inferred_i_45__0_n_0), + .I1(ip2axi_rddata_int_inferred_i_34__0_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [21]), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [21]), + .I4(ip2axi_rddata_int_inferred_i_35__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [21])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_12 + (.I0(ip2axi_rddata_int_inferred_i_46_n_0), + .I1(ip2axi_rddata_int_inferred_i_34_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [7]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [17]), + .O(in0[17])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_12__0 + (.I0(ip2axi_rddata_int_inferred_i_46__0_n_0), + .I1(ip2axi_rddata_int_inferred_i_34__0_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [20]), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [20]), + .I4(ip2axi_rddata_int_inferred_i_35__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [20])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_13 + (.I0(ip2axi_rddata_int_inferred_i_47_n_0), + .I1(ip2axi_rddata_int_inferred_i_34_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [6]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [16]), + .O(in0[16])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_13__0 + (.I0(ip2axi_rddata_int_inferred_i_47__0_n_0), + .I1(ip2axi_rddata_int_inferred_i_34__0_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [19]), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [19]), + .I4(ip2axi_rddata_int_inferred_i_35__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [19])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_14 + (.I0(ip2axi_rddata_int_inferred_i_48_n_0), + .I1(ip2axi_rddata_int_inferred_i_34_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [5]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [15]), + .O(in0[15])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_14__0 + (.I0(ip2axi_rddata_int_inferred_i_48__0_n_0), + .I1(ip2axi_rddata_int_inferred_i_34__0_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [18]), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [18]), + .I4(ip2axi_rddata_int_inferred_i_35__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [18])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_15 + (.I0(ip2axi_rddata_int_inferred_i_49_n_0), + .I1(ip2axi_rddata_int_inferred_i_34_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [4]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [14]), + .O(in0[14])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_15__0 + (.I0(ip2axi_rddata_int_inferred_i_49__0_n_0), + .I1(ip2axi_rddata_int_inferred_i_34__0_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [17]), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [17]), + .I4(ip2axi_rddata_int_inferred_i_35__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [17])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_16 + (.I0(ip2axi_rddata_int_inferred_i_50_n_0), + .I1(ip2axi_rddata_int_inferred_i_34_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [3]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [13]), + .O(in0[13])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_16__0 + (.I0(ip2axi_rddata_int_inferred_i_50__0_n_0), + .I1(ip2axi_rddata_int_inferred_i_34__0_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [16]), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [16]), + .I4(ip2axi_rddata_int_inferred_i_35__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [16])); + LUT4 #( + .INIT(16'hFEEE)) + ip2axi_rddata_int_inferred_i_17__0 + (.I0(ip2axi_rddata_int_inferred_i_51__0_n_0), + .I1(ip2axi_rddata_int_inferred_i_52__0_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [15]), + .I3(ip2axi_rddata_int_inferred_i_35__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [15])); + LUT4 #( + .INIT(16'hFEEE)) + ip2axi_rddata_int_inferred_i_18 + (.I0(ip2axi_rddata_int_inferred_i_54_n_0), + .I1(ip2axi_rddata_int_inferred_i_55_n_0), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [12]), + .O(in0[12])); + LUT4 #( + .INIT(16'hFEEE)) + ip2axi_rddata_int_inferred_i_18__0 + (.I0(ip2axi_rddata_int_inferred_i_53__0_n_0), + .I1(ip2axi_rddata_int_inferred_i_54__0_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [14]), + .I3(ip2axi_rddata_int_inferred_i_35__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [14])); + LUT4 #( + .INIT(16'hFEEE)) + ip2axi_rddata_int_inferred_i_19 + (.I0(ip2axi_rddata_int_inferred_i_56_n_0), + .I1(ip2axi_rddata_int_inferred_i_57_n_0), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [11]), + .O(in0[11])); + LUT4 #( + .INIT(16'hFEEE)) + ip2axi_rddata_int_inferred_i_19__0 + (.I0(ip2axi_rddata_int_inferred_i_55__0_n_0), + .I1(ip2axi_rddata_int_inferred_i_56__0_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [13]), + .I3(ip2axi_rddata_int_inferred_i_35__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [13])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_1__0 + (.I0(ip2axi_rddata_int_inferred_i_33__0_n_0), + .I1(ip2axi_rddata_int_inferred_i_34__0_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [31]), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [31]), + .I4(ip2axi_rddata_int_inferred_i_35__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [31])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_2 + (.I0(ip2axi_rddata_int_inferred_i_36_n_0), + .I1(ip2axi_rddata_int_inferred_i_34_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [17]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [27]), + .O(in0[27])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_20 + (.I0(ip2axi_rddata_int_inferred_i_58_n_0), + .I1(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]_0 ), + .I2(\reg_module_hsize_reg[12] ), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [10]), + .O(in0[10])); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFF888)) + ip2axi_rddata_int_inferred_i_20__0 + (.I0(ip2axi_rddata_int_inferred_i_34__0_n_0), + .I1(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [12]), + .I2(ip2axi_rddata_int_inferred_i_35__0_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [12]), + .I4(ip2axi_rddata_int_inferred_i_57__0_n_0), + .I5(ip2axi_rddata_int_inferred_i_58__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [12])); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_21 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]_0 ), + .I1(\reg_module_hsize_reg[11] ), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [9]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [9]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ), + .O(in0[9])); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFF888)) + ip2axi_rddata_int_inferred_i_21__0 + (.I0(ip2axi_rddata_int_inferred_i_34__0_n_0), + .I1(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [11]), + .I2(ip2axi_rddata_int_inferred_i_35__0_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [11]), + .I4(ip2axi_rddata_int_inferred_i_59__0_n_0), + .I5(ip2axi_rddata_int_inferred_i_60__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [11])); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_22 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]_0 ), + .I1(\reg_module_hsize_reg[10] ), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [8]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [8]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ), + .O(in0[8])); + LUT4 #( + .INIT(16'hFEEE)) + ip2axi_rddata_int_inferred_i_22__0 + (.I0(ip2axi_rddata_int_inferred_i_61__0_n_0), + .I1(ip2axi_rddata_int_inferred_i_62__0_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [10]), + .I3(ip2axi_rddata_int_inferred_i_35__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [10])); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_23 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]_0 ), + .I1(\reg_module_hsize_reg[9] ), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [7]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [7]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ), + .O(in0[7])); + LUT4 #( + .INIT(16'hFEEE)) + ip2axi_rddata_int_inferred_i_23__0 + (.I0(ip2axi_rddata_int_inferred_i_63__0_n_0), + .I1(ip2axi_rddata_int_inferred_i_64__0_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [9]), + .I3(ip2axi_rddata_int_inferred_i_35__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [9])); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_24 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]_0 ), + .I1(\reg_module_hsize_reg[8] ), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [6]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [6]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ), + .O(in0[6])); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFF888)) + ip2axi_rddata_int_inferred_i_24__0 + (.I0(ip2axi_rddata_int_inferred_i_34__0_n_0), + .I1(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [8]), + .I2(ip2axi_rddata_int_inferred_i_35__0_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [8]), + .I4(ip2axi_rddata_int_inferred_i_65__0_n_0), + .I5(ip2axi_rddata_int_inferred_i_66__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [8])); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_25 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]_0 ), + .I1(\reg_module_hsize_reg[7] ), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [5]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [5]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ), + .O(in0[5])); + LUT4 #( + .INIT(16'hFEEE)) + ip2axi_rddata_int_inferred_i_25__0 + (.I0(ip2axi_rddata_int_inferred_i_67__0_n_0), + .I1(ip2axi_rddata_int_inferred_i_68__0_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [7]), + .I3(ip2axi_rddata_int_inferred_i_35__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [7])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_26 + (.I0(ip2axi_rddata_int_inferred_i_67_n_0), + .I1(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]_0 ), + .I2(\reg_module_hsize_reg[6] ), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [4]), + .O(in0[4])); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFF888)) + ip2axi_rddata_int_inferred_i_26__0 + (.I0(ip2axi_rddata_int_inferred_i_34__0_n_0), + .I1(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [6]), + .I2(ip2axi_rddata_int_inferred_i_35__0_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [6]), + .I4(ip2axi_rddata_int_inferred_i_69__0_n_0), + .I5(ip2axi_rddata_int_inferred_i_70__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [6])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_27 + (.I0(ip2axi_rddata_int_inferred_i_69_n_0), + .I1(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]_0 ), + .I2(\reg_module_hsize_reg[5] ), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [3]), + .O(in0[3])); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFF888)) + ip2axi_rddata_int_inferred_i_27__0 + (.I0(ip2axi_rddata_int_inferred_i_34__0_n_0), + .I1(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [5]), + .I2(ip2axi_rddata_int_inferred_i_35__0_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [5]), + .I4(ip2axi_rddata_int_inferred_i_71__0_n_0), + .I5(ip2axi_rddata_int_inferred_i_72__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [5])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_28 + (.I0(ip2axi_rddata_int_inferred_i_71_n_0), + .I1(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]_0 ), + .I2(\reg_module_hsize_reg[4] ), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [2]), + .O(in0[2])); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFF888)) + ip2axi_rddata_int_inferred_i_28__0 + (.I0(ip2axi_rddata_int_inferred_i_34__0_n_0), + .I1(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [4]), + .I2(ip2axi_rddata_int_inferred_i_35__0_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [4]), + .I4(ip2axi_rddata_int_inferred_i_73__0_n_0), + .I5(ip2axi_rddata_int_inferred_i_74__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [4])); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_29 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]_0 ), + .I1(\reg_module_hsize_reg[3] ), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [1]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [1]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ), + .O(in0[1])); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFF888)) + ip2axi_rddata_int_inferred_i_29__0 + (.I0(ip2axi_rddata_int_inferred_i_34__0_n_0), + .I1(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [3]), + .I2(ip2axi_rddata_int_inferred_i_35__0_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [3]), + .I4(ip2axi_rddata_int_inferred_i_75__0_n_0), + .I5(ip2axi_rddata_int_inferred_i_76__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [3])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_2__0 + (.I0(ip2axi_rddata_int_inferred_i_36__0_n_0), + .I1(ip2axi_rddata_int_inferred_i_34__0_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [30]), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [30]), + .I4(ip2axi_rddata_int_inferred_i_35__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [30])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_3 + (.I0(ip2axi_rddata_int_inferred_i_37_n_0), + .I1(ip2axi_rddata_int_inferred_i_34_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [16]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [26]), + .O(in0[26])); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFF888)) + ip2axi_rddata_int_inferred_i_30__0 + (.I0(ip2axi_rddata_int_inferred_i_34__0_n_0), + .I1(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [2]), + .I2(ip2axi_rddata_int_inferred_i_35__0_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [2]), + .I4(ip2axi_rddata_int_inferred_i_77__0_n_0), + .I5(ip2axi_rddata_int_inferred_i_78__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [2])); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFF888)) + ip2axi_rddata_int_inferred_i_31__0 + (.I0(ip2axi_rddata_int_inferred_i_34__0_n_0), + .I1(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [1]), + .I2(ip2axi_rddata_int_inferred_i_35__0_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [1]), + .I4(ip2axi_rddata_int_inferred_i_79__0_n_0), + .I5(ip2axi_rddata_int_inferred_i_80__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [1])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_32 + (.I0(ip2axi_rddata_int_inferred_i_76_n_0), + .I1(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]_0 ), + .I2(\reg_module_hsize_reg[0] ), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [0]), + .O(in0[0])); + LUT3 #( + .INIT(8'hFE)) + ip2axi_rddata_int_inferred_i_32__0 + (.I0(ip2axi_rddata_int_inferred_i_81_n_0), + .I1(ip2axi_rddata_int_inferred_i_82_n_0), + .I2(ip2axi_rddata_int_inferred_i_83_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [0])); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_33 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1 ), + .I1(p_71_out[17]), + .I2(ip2axi_rddata_int_inferred_i_78_n_0), + .I3(ch1_irqdelay_status[7]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [28]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ), + .O(ip2axi_rddata_int_inferred_i_33_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_33__0 + (.I0(ip2axi_rddata_int_inferred_i_84_n_0), + .I1(ch2_irqdelay_status[7]), + .I2(ip2axi_rddata_int_inferred_i_85_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [31]), + .I4(s2mm_dmacr[22]), + .I5(ip2axi_rddata_int_inferred_i_86_n_0), + .O(ip2axi_rddata_int_inferred_i_33__0_n_0)); + LUT6 #( + .INIT(64'h1000000000000000)) + ip2axi_rddata_int_inferred_i_34 + (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), + .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), + .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), + .I3(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), + .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), + .I5(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), + .O(ip2axi_rddata_int_inferred_i_34_n_0)); + LUT6 #( + .INIT(64'h0010000000000000)) + ip2axi_rddata_int_inferred_i_34__0 + (.I0(axi2ip_rdaddr_captured_s2mm_cdc_tig[2]), + .I1(axi2ip_rdaddr_captured_s2mm_cdc_tig[3]), + .I2(axi2ip_rdaddr_captured_s2mm_cdc_tig[5]), + .I3(axi2ip_rdaddr_captured_s2mm_cdc_tig[6]), + .I4(axi2ip_rdaddr_captured_s2mm_cdc_tig[4]), + .I5(axi2ip_rdaddr_captured_s2mm_cdc_tig[7]), + .O(ip2axi_rddata_int_inferred_i_34__0_n_0)); + LUT6 #( + .INIT(64'h0000000000000040)) + ip2axi_rddata_int_inferred_i_35 + (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), + .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), + .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), + .I3(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), + .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), + .I5(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 )); + LUT6 #( + .INIT(64'h0000000000800000)) + ip2axi_rddata_int_inferred_i_35__0 + (.I0(axi2ip_rdaddr_captured_s2mm_cdc_tig[7]), + .I1(axi2ip_rdaddr_captured_s2mm_cdc_tig[2]), + .I2(axi2ip_rdaddr_captured_s2mm_cdc_tig[4]), + .I3(axi2ip_rdaddr_captured_s2mm_cdc_tig[6]), + .I4(axi2ip_rdaddr_captured_s2mm_cdc_tig[5]), + .I5(axi2ip_rdaddr_captured_s2mm_cdc_tig[3]), + .O(ip2axi_rddata_int_inferred_i_35__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_36 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1 ), + .I1(p_71_out[16]), + .I2(ip2axi_rddata_int_inferred_i_78_n_0), + .I3(ch1_irqdelay_status[6]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [27]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ), + .O(ip2axi_rddata_int_inferred_i_36_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_36__0 + (.I0(ip2axi_rddata_int_inferred_i_84_n_0), + .I1(ch2_irqdelay_status[6]), + .I2(ip2axi_rddata_int_inferred_i_85_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [30]), + .I4(s2mm_dmacr[21]), + .I5(ip2axi_rddata_int_inferred_i_86_n_0), + .O(ip2axi_rddata_int_inferred_i_36__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_37 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1 ), + .I1(p_71_out[15]), + .I2(ip2axi_rddata_int_inferred_i_78_n_0), + .I3(ch1_irqdelay_status[5]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [26]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ), + .O(ip2axi_rddata_int_inferred_i_37_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_37__0 + (.I0(ip2axi_rddata_int_inferred_i_84_n_0), + .I1(ch2_irqdelay_status[5]), + .I2(ip2axi_rddata_int_inferred_i_85_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [29]), + .I4(s2mm_dmacr[20]), + .I5(ip2axi_rddata_int_inferred_i_86_n_0), + .O(ip2axi_rddata_int_inferred_i_37__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_38 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1 ), + .I1(p_71_out[14]), + .I2(ip2axi_rddata_int_inferred_i_78_n_0), + .I3(ch1_irqdelay_status[4]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [25]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ), + .O(ip2axi_rddata_int_inferred_i_38_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_38__0 + (.I0(ip2axi_rddata_int_inferred_i_84_n_0), + .I1(ch2_irqdelay_status[4]), + .I2(ip2axi_rddata_int_inferred_i_85_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [28]), + .I4(s2mm_dmacr[19]), + .I5(ip2axi_rddata_int_inferred_i_86_n_0), + .O(ip2axi_rddata_int_inferred_i_38__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_39 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1 ), + .I1(p_71_out[13]), + .I2(ip2axi_rddata_int_inferred_i_78_n_0), + .I3(ch1_irqdelay_status[3]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [24]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ), + .O(ip2axi_rddata_int_inferred_i_39_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_39__0 + (.I0(ip2axi_rddata_int_inferred_i_84_n_0), + .I1(ch2_irqdelay_status[3]), + .I2(ip2axi_rddata_int_inferred_i_85_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [27]), + .I4(s2mm_dmacr[18]), + .I5(ip2axi_rddata_int_inferred_i_86_n_0), + .O(ip2axi_rddata_int_inferred_i_39__0_n_0)); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_3__0 + (.I0(ip2axi_rddata_int_inferred_i_37__0_n_0), + .I1(ip2axi_rddata_int_inferred_i_34__0_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [29]), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [29]), + .I4(ip2axi_rddata_int_inferred_i_35__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [29])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_4 + (.I0(ip2axi_rddata_int_inferred_i_38_n_0), + .I1(ip2axi_rddata_int_inferred_i_34_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [15]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [25]), + .O(in0[25])); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_40 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1 ), + .I1(p_71_out[12]), + .I2(ip2axi_rddata_int_inferred_i_78_n_0), + .I3(ch1_irqdelay_status[2]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [23]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ), + .O(ip2axi_rddata_int_inferred_i_40_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_40__0 + (.I0(ip2axi_rddata_int_inferred_i_84_n_0), + .I1(ch2_irqdelay_status[2]), + .I2(ip2axi_rddata_int_inferred_i_85_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [26]), + .I4(s2mm_dmacr[17]), + .I5(ip2axi_rddata_int_inferred_i_86_n_0), + .O(ip2axi_rddata_int_inferred_i_40__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_41 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1 ), + .I1(p_71_out[11]), + .I2(ip2axi_rddata_int_inferred_i_78_n_0), + .I3(ch1_irqdelay_status[1]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [22]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ), + .O(ip2axi_rddata_int_inferred_i_41_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_41__0 + (.I0(ip2axi_rddata_int_inferred_i_84_n_0), + .I1(ch2_irqdelay_status[1]), + .I2(ip2axi_rddata_int_inferred_i_85_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [25]), + .I4(s2mm_dmacr[16]), + .I5(ip2axi_rddata_int_inferred_i_86_n_0), + .O(ip2axi_rddata_int_inferred_i_41__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_42 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1 ), + .I1(p_71_out[10]), + .I2(ip2axi_rddata_int_inferred_i_78_n_0), + .I3(ch1_irqdelay_status[0]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [21]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ), + .O(ip2axi_rddata_int_inferred_i_42_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_42__0 + (.I0(ip2axi_rddata_int_inferred_i_84_n_0), + .I1(ch2_irqdelay_status[0]), + .I2(ip2axi_rddata_int_inferred_i_85_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [24]), + .I4(s2mm_dmacr[15]), + .I5(ip2axi_rddata_int_inferred_i_86_n_0), + .O(ip2axi_rddata_int_inferred_i_42__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_43 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1 ), + .I1(p_71_out[9]), + .I2(ip2axi_rddata_int_inferred_i_78_n_0), + .I3(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] [7]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [20]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ), + .O(ip2axi_rddata_int_inferred_i_43_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_43__0 + (.I0(ip2axi_rddata_int_inferred_i_84_n_0), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7] [7]), + .I2(ip2axi_rddata_int_inferred_i_85_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [23]), + .I4(s2mm_dmacr[14]), + .I5(ip2axi_rddata_int_inferred_i_86_n_0), + .O(ip2axi_rddata_int_inferred_i_43__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_44 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1 ), + .I1(p_71_out[8]), + .I2(ip2axi_rddata_int_inferred_i_78_n_0), + .I3(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] [6]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [19]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ), + .O(ip2axi_rddata_int_inferred_i_44_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_44__0 + (.I0(ip2axi_rddata_int_inferred_i_84_n_0), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7] [6]), + .I2(ip2axi_rddata_int_inferred_i_85_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [22]), + .I4(s2mm_dmacr[13]), + .I5(ip2axi_rddata_int_inferred_i_86_n_0), + .O(ip2axi_rddata_int_inferred_i_44__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_45 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1 ), + .I1(p_71_out[7]), + .I2(ip2axi_rddata_int_inferred_i_78_n_0), + .I3(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] [5]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [18]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ), + .O(ip2axi_rddata_int_inferred_i_45_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_45__0 + (.I0(ip2axi_rddata_int_inferred_i_84_n_0), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7] [5]), + .I2(ip2axi_rddata_int_inferred_i_85_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [21]), + .I4(s2mm_dmacr[12]), + .I5(ip2axi_rddata_int_inferred_i_86_n_0), + .O(ip2axi_rddata_int_inferred_i_45__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_46 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1 ), + .I1(p_71_out[6]), + .I2(ip2axi_rddata_int_inferred_i_78_n_0), + .I3(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] [4]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [17]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ), + .O(ip2axi_rddata_int_inferred_i_46_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_46__0 + (.I0(ip2axi_rddata_int_inferred_i_84_n_0), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7] [4]), + .I2(ip2axi_rddata_int_inferred_i_85_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [20]), + .I4(s2mm_dmacr[11]), + .I5(ip2axi_rddata_int_inferred_i_86_n_0), + .O(ip2axi_rddata_int_inferred_i_46__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_47 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1 ), + .I1(p_71_out[5]), + .I2(ip2axi_rddata_int_inferred_i_78_n_0), + .I3(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] [3]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [16]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ), + .O(ip2axi_rddata_int_inferred_i_47_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_47__0 + (.I0(ip2axi_rddata_int_inferred_i_84_n_0), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7] [3]), + .I2(ip2axi_rddata_int_inferred_i_85_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [19]), + .I4(s2mm_dmacr[10]), + .I5(ip2axi_rddata_int_inferred_i_86_n_0), + .O(ip2axi_rddata_int_inferred_i_47__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_48 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1 ), + .I1(p_71_out[4]), + .I2(ip2axi_rddata_int_inferred_i_78_n_0), + .I3(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] [2]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [15]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ), + .O(ip2axi_rddata_int_inferred_i_48_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_48__0 + (.I0(ip2axi_rddata_int_inferred_i_84_n_0), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7] [2]), + .I2(ip2axi_rddata_int_inferred_i_85_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [18]), + .I4(s2mm_dmacr[9]), + .I5(ip2axi_rddata_int_inferred_i_86_n_0), + .O(ip2axi_rddata_int_inferred_i_48__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_49 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1 ), + .I1(p_71_out[3]), + .I2(ip2axi_rddata_int_inferred_i_78_n_0), + .I3(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] [1]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [14]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ), + .O(ip2axi_rddata_int_inferred_i_49_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_49__0 + (.I0(ip2axi_rddata_int_inferred_i_84_n_0), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7] [1]), + .I2(ip2axi_rddata_int_inferred_i_85_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [17]), + .I4(s2mm_dmacr[8]), + .I5(ip2axi_rddata_int_inferred_i_86_n_0), + .O(ip2axi_rddata_int_inferred_i_49__0_n_0)); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_4__0 + (.I0(ip2axi_rddata_int_inferred_i_38__0_n_0), + .I1(ip2axi_rddata_int_inferred_i_34__0_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [28]), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [28]), + .I4(ip2axi_rddata_int_inferred_i_35__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [28])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_5 + (.I0(ip2axi_rddata_int_inferred_i_39_n_0), + .I1(ip2axi_rddata_int_inferred_i_34_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [14]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [24]), + .O(in0[24])); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_50 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1 ), + .I1(p_71_out[2]), + .I2(ip2axi_rddata_int_inferred_i_78_n_0), + .I3(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] [0]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [13]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ), + .O(ip2axi_rddata_int_inferred_i_50_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_50__0 + (.I0(ip2axi_rddata_int_inferred_i_84_n_0), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7] [0]), + .I2(ip2axi_rddata_int_inferred_i_85_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [16]), + .I4(s2mm_dmacr[7]), + .I5(ip2axi_rddata_int_inferred_i_86_n_0), + .O(ip2axi_rddata_int_inferred_i_50__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_51__0 + (.I0(ip2axi_rddata_int_inferred_i_84_n_0), + .I1(lsize_more_err_reg_0), + .I2(ip2axi_rddata_int_inferred_i_87_n_0), + .I3(\reg_module_hsize_reg[15]_0 [15]), + .I4(s2mm_dmacr[6]), + .I5(ip2axi_rddata_int_inferred_i_86_n_0), + .O(ip2axi_rddata_int_inferred_i_51__0_n_0)); + LUT6 #( + .INIT(64'h0000000000000001)) + ip2axi_rddata_int_inferred_i_52 + (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), + .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), + .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), + .I3(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), + .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), + .I5(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_52__0 + (.I0(ip2axi_rddata_int_inferred_i_88_n_0), + .I1(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [15]), + .I2(ip2axi_rddata_int_inferred_i_85_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [15]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [15]), + .I5(ip2axi_rddata_int_inferred_i_34__0_n_0), + .O(ip2axi_rddata_int_inferred_i_52__0_n_0)); + LUT6 #( + .INIT(64'hA8288808A0208000)) + ip2axi_rddata_int_inferred_i_53 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]_0 ), + .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), + .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [2]), + .I4(\reg_module_hsize_reg[15] [2]), + .I5(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [2]), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_53__0 + (.I0(ip2axi_rddata_int_inferred_i_84_n_0), + .I1(err_irq_reg_0), + .I2(ip2axi_rddata_int_inferred_i_87_n_0), + .I3(\reg_module_hsize_reg[15]_0 [14]), + .I4(\GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14] [6]), + .I5(ip2axi_rddata_int_inferred_i_86_n_0), + .O(ip2axi_rddata_int_inferred_i_53__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_54 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1 ), + .I1(\M_GEN_DMACR_REGISTER.dmacr_i_reg[14] [4]), + .I2(ip2axi_rddata_int_inferred_i_78_n_0), + .I3(err_irq_reg), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [12]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ), + .O(ip2axi_rddata_int_inferred_i_54_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_54__0 + (.I0(ip2axi_rddata_int_inferred_i_88_n_0), + .I1(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [14]), + .I2(ip2axi_rddata_int_inferred_i_85_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [14]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [14]), + .I5(ip2axi_rddata_int_inferred_i_34__0_n_0), + .O(ip2axi_rddata_int_inferred_i_54__0_n_0)); + LUT6 #( + .INIT(64'hA8288808A0208000)) + ip2axi_rddata_int_inferred_i_55 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]_0 ), + .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), + .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [1]), + .I4(\reg_module_hsize_reg[15] [1]), + .I5(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [1]), + .O(ip2axi_rddata_int_inferred_i_55_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_55__0 + (.I0(ip2axi_rddata_int_inferred_i_84_n_0), + .I1(dly_irq_reg_2), + .I2(ip2axi_rddata_int_inferred_i_87_n_0), + .I3(\reg_module_hsize_reg[15]_0 [13]), + .I4(\GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14] [5]), + .I5(ip2axi_rddata_int_inferred_i_86_n_0), + .O(ip2axi_rddata_int_inferred_i_55__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_56 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1 ), + .I1(\M_GEN_DMACR_REGISTER.dmacr_i_reg[14] [3]), + .I2(ip2axi_rddata_int_inferred_i_78_n_0), + .I3(dly_irq_reg_1), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [11]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ), + .O(ip2axi_rddata_int_inferred_i_56_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_56__0 + (.I0(ip2axi_rddata_int_inferred_i_88_n_0), + .I1(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [13]), + .I2(ip2axi_rddata_int_inferred_i_85_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [13]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [13]), + .I5(ip2axi_rddata_int_inferred_i_34__0_n_0), + .O(ip2axi_rddata_int_inferred_i_56__0_n_0)); + LUT6 #( + .INIT(64'hA8288808A0208000)) + ip2axi_rddata_int_inferred_i_57 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]_0 ), + .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), + .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [0]), + .I4(\reg_module_hsize_reg[15] [0]), + .I5(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [0]), + .O(ip2axi_rddata_int_inferred_i_57_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_57__0 + (.I0(ip2axi_rddata_int_inferred_i_84_n_0), + .I1(ioc_irq_reg_2), + .I2(ip2axi_rddata_int_inferred_i_89_n_0), + .I3(\reg_module_vsize_reg[12] [12]), + .I4(\GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14] [4]), + .I5(ip2axi_rddata_int_inferred_i_86_n_0), + .O(ip2axi_rddata_int_inferred_i_57__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_58 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1 ), + .I1(\M_GEN_DMACR_REGISTER.dmacr_i_reg[14] [2]), + .I2(ip2axi_rddata_int_inferred_i_78_n_0), + .I3(ioc_irq_reg_1), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [10]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ), + .O(ip2axi_rddata_int_inferred_i_58_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_58__0 + (.I0(ip2axi_rddata_int_inferred_i_87_n_0), + .I1(\reg_module_hsize_reg[15]_0 [12]), + .I2(ip2axi_rddata_int_inferred_i_88_n_0), + .I3(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [12]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [12]), + .I5(ip2axi_rddata_int_inferred_i_85_n_0), + .O(ip2axi_rddata_int_inferred_i_58__0_n_0)); + LUT4 #( + .INIT(16'h0008)) + ip2axi_rddata_int_inferred_i_59 + (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), + .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), + .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), + .I3(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_59__0 + (.I0(ip2axi_rddata_int_inferred_i_84_n_0), + .I1(\GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg_0 ), + .I2(ip2axi_rddata_int_inferred_i_89_n_0), + .I3(\reg_module_vsize_reg[12] [11]), + .I4(\GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14] [3]), + .I5(ip2axi_rddata_int_inferred_i_86_n_0), + .O(ip2axi_rddata_int_inferred_i_59__0_n_0)); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_5__0 + (.I0(ip2axi_rddata_int_inferred_i_39__0_n_0), + .I1(ip2axi_rddata_int_inferred_i_34__0_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [27]), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [27]), + .I4(ip2axi_rddata_int_inferred_i_35__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [27])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_6 + (.I0(ip2axi_rddata_int_inferred_i_40_n_0), + .I1(ip2axi_rddata_int_inferred_i_34_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [13]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [23]), + .O(in0[23])); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_60__0 + (.I0(ip2axi_rddata_int_inferred_i_87_n_0), + .I1(\reg_module_hsize_reg[15]_0 [11]), + .I2(ip2axi_rddata_int_inferred_i_88_n_0), + .I3(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [11]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [11]), + .I5(ip2axi_rddata_int_inferred_i_85_n_0), + .O(ip2axi_rddata_int_inferred_i_60__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_61__0 + (.I0(ip2axi_rddata_int_inferred_i_86_n_0), + .I1(\GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14] [2]), + .I2(ip2axi_rddata_int_inferred_i_89_n_0), + .I3(\reg_module_vsize_reg[12] [10]), + .I4(\reg_module_hsize_reg[15]_0 [10]), + .I5(ip2axi_rddata_int_inferred_i_87_n_0), + .O(ip2axi_rddata_int_inferred_i_61__0_n_0)); + LUT6 #( + .INIT(64'h0000000000400000)) + ip2axi_rddata_int_inferred_i_62 + (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), + .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), + .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), + .I3(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), + .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), + .I5(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_62__0 + (.I0(ip2axi_rddata_int_inferred_i_88_n_0), + .I1(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [10]), + .I2(ip2axi_rddata_int_inferred_i_85_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [10]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [10]), + .I5(ip2axi_rddata_int_inferred_i_34__0_n_0), + .O(ip2axi_rddata_int_inferred_i_62__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_63__0 + (.I0(ip2axi_rddata_int_inferred_i_86_n_0), + .I1(\GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14] [1]), + .I2(ip2axi_rddata_int_inferred_i_89_n_0), + .I3(\reg_module_vsize_reg[12] [9]), + .I4(\reg_module_hsize_reg[15]_0 [9]), + .I5(ip2axi_rddata_int_inferred_i_87_n_0), + .O(ip2axi_rddata_int_inferred_i_63__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_64__0 + (.I0(ip2axi_rddata_int_inferred_i_88_n_0), + .I1(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [9]), + .I2(ip2axi_rddata_int_inferred_i_85_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [9]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [9]), + .I5(ip2axi_rddata_int_inferred_i_34__0_n_0), + .O(ip2axi_rddata_int_inferred_i_64__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_65__0 + (.I0(ip2axi_rddata_int_inferred_i_84_n_0), + .I1(lsize_err_reg_0), + .I2(ip2axi_rddata_int_inferred_i_89_n_0), + .I3(\reg_module_vsize_reg[12] [8]), + .I4(\GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14] [0]), + .I5(ip2axi_rddata_int_inferred_i_86_n_0), + .O(ip2axi_rddata_int_inferred_i_65__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_66__0 + (.I0(ip2axi_rddata_int_inferred_i_87_n_0), + .I1(\reg_module_hsize_reg[15]_0 [8]), + .I2(ip2axi_rddata_int_inferred_i_88_n_0), + .I3(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [8]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [8]), + .I5(ip2axi_rddata_int_inferred_i_85_n_0), + .O(ip2axi_rddata_int_inferred_i_66__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_67 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1 ), + .I1(\M_GEN_DMACR_REGISTER.dmacr_i_reg[14] [1]), + .I2(ip2axi_rddata_int_inferred_i_78_n_0), + .I3(dma_decerr_reg), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [4]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ), + .O(ip2axi_rddata_int_inferred_i_67_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_67__0 + (.I0(ip2axi_rddata_int_inferred_i_84_n_0), + .I1(\GEN_FOR_FLUSH.fsize_err_reg_0 ), + .I2(ip2axi_rddata_int_inferred_i_89_n_0), + .I3(\reg_module_vsize_reg[12] [7]), + .I4(\reg_module_hsize_reg[15]_0 [7]), + .I5(ip2axi_rddata_int_inferred_i_87_n_0), + .O(ip2axi_rddata_int_inferred_i_67__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_68__0 + (.I0(ip2axi_rddata_int_inferred_i_88_n_0), + .I1(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [7]), + .I2(ip2axi_rddata_int_inferred_i_85_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [7]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [7]), + .I5(ip2axi_rddata_int_inferred_i_34__0_n_0), + .O(ip2axi_rddata_int_inferred_i_68__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_69 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1 ), + .I1(\M_GEN_DMACR_REGISTER.dmacr_i_reg[14] [0]), + .I2(ip2axi_rddata_int_inferred_i_78_n_0), + .I3(dma_slverr_reg), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [3]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ), + .O(ip2axi_rddata_int_inferred_i_69_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_69__0 + (.I0(ip2axi_rddata_int_inferred_i_84_n_0), + .I1(dma_decerr_reg_0), + .I2(ip2axi_rddata_int_inferred_i_89_n_0), + .I3(\reg_module_vsize_reg[12] [6]), + .I4(s2mm_dmacr[5]), + .I5(ip2axi_rddata_int_inferred_i_86_n_0), + .O(ip2axi_rddata_int_inferred_i_69__0_n_0)); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_6__0 + (.I0(ip2axi_rddata_int_inferred_i_40__0_n_0), + .I1(ip2axi_rddata_int_inferred_i_34__0_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [26]), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [26]), + .I4(ip2axi_rddata_int_inferred_i_35__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [26])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_7 + (.I0(ip2axi_rddata_int_inferred_i_41_n_0), + .I1(ip2axi_rddata_int_inferred_i_34_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [12]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [22]), + .O(in0[22])); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_70__0 + (.I0(ip2axi_rddata_int_inferred_i_87_n_0), + .I1(\reg_module_hsize_reg[15]_0 [6]), + .I2(ip2axi_rddata_int_inferred_i_88_n_0), + .I3(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [6]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [6]), + .I5(ip2axi_rddata_int_inferred_i_85_n_0), + .O(ip2axi_rddata_int_inferred_i_70__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_71 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1 ), + .I1(p_71_out[1]), + .I2(ip2axi_rddata_int_inferred_i_78_n_0), + .I3(dma_interr_reg_1), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [2]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ), + .O(ip2axi_rddata_int_inferred_i_71_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_71__0 + (.I0(ip2axi_rddata_int_inferred_i_84_n_0), + .I1(dma_slverr_reg_0), + .I2(ip2axi_rddata_int_inferred_i_89_n_0), + .I3(\reg_module_vsize_reg[12] [5]), + .I4(s2mm_dmacr[4]), + .I5(ip2axi_rddata_int_inferred_i_86_n_0), + .O(ip2axi_rddata_int_inferred_i_71__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_72__0 + (.I0(ip2axi_rddata_int_inferred_i_87_n_0), + .I1(\reg_module_hsize_reg[15]_0 [5]), + .I2(ip2axi_rddata_int_inferred_i_88_n_0), + .I3(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [5]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [5]), + .I5(ip2axi_rddata_int_inferred_i_85_n_0), + .O(ip2axi_rddata_int_inferred_i_72__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_73__0 + (.I0(ip2axi_rddata_int_inferred_i_84_n_0), + .I1(dma_interr_reg_2), + .I2(ip2axi_rddata_int_inferred_i_89_n_0), + .I3(\reg_module_vsize_reg[12] [4]), + .I4(s2mm_dmacr[3]), + .I5(ip2axi_rddata_int_inferred_i_86_n_0), + .O(ip2axi_rddata_int_inferred_i_73__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_74__0 + (.I0(ip2axi_rddata_int_inferred_i_87_n_0), + .I1(\reg_module_hsize_reg[15]_0 [4]), + .I2(ip2axi_rddata_int_inferred_i_88_n_0), + .I3(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [4]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [4]), + .I5(ip2axi_rddata_int_inferred_i_85_n_0), + .O(ip2axi_rddata_int_inferred_i_74__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_75__0 + (.I0(ip2axi_rddata_int_inferred_i_86_n_0), + .I1(s2mm_dmacr[2]), + .I2(ip2axi_rddata_int_inferred_i_90_n_0), + .I3(\DMA_IRQ_MASK_GEN.dma_irq_mask_i_reg[3] [3]), + .I4(\reg_module_vsize_reg[12] [3]), + .I5(ip2axi_rddata_int_inferred_i_89_n_0), + .O(ip2axi_rddata_int_inferred_i_75__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_76 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1 ), + .I1(p_71_out[0]), + .I2(ip2axi_rddata_int_inferred_i_78_n_0), + .I3(p_70_out), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [0]), + .I5(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 ), + .O(ip2axi_rddata_int_inferred_i_76_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_76__0 + (.I0(ip2axi_rddata_int_inferred_i_87_n_0), + .I1(\reg_module_hsize_reg[15]_0 [3]), + .I2(ip2axi_rddata_int_inferred_i_88_n_0), + .I3(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [3]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [3]), + .I5(ip2axi_rddata_int_inferred_i_85_n_0), + .O(ip2axi_rddata_int_inferred_i_76__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_77__0 + (.I0(ip2axi_rddata_int_inferred_i_86_n_0), + .I1(s2mm_soft_reset), + .I2(ip2axi_rddata_int_inferred_i_90_n_0), + .I3(\DMA_IRQ_MASK_GEN.dma_irq_mask_i_reg[3] [2]), + .I4(\reg_module_vsize_reg[12] [2]), + .I5(ip2axi_rddata_int_inferred_i_89_n_0), + .O(ip2axi_rddata_int_inferred_i_77__0_n_0)); + LUT6 #( + .INIT(64'h0000000000010000)) + ip2axi_rddata_int_inferred_i_78 + (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), + .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), + .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), + .I3(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), + .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), + .I5(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), + .O(ip2axi_rddata_int_inferred_i_78_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_78__0 + (.I0(ip2axi_rddata_int_inferred_i_87_n_0), + .I1(\reg_module_hsize_reg[15]_0 [2]), + .I2(ip2axi_rddata_int_inferred_i_88_n_0), + .I3(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [2]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [2]), + .I5(ip2axi_rddata_int_inferred_i_85_n_0), + .O(ip2axi_rddata_int_inferred_i_78__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_79__0 + (.I0(ip2axi_rddata_int_inferred_i_86_n_0), + .I1(s2mm_dmacr[1]), + .I2(ip2axi_rddata_int_inferred_i_90_n_0), + .I3(\DMA_IRQ_MASK_GEN.dma_irq_mask_i_reg[3] [1]), + .I4(\reg_module_vsize_reg[12] [1]), + .I5(ip2axi_rddata_int_inferred_i_89_n_0), + .O(ip2axi_rddata_int_inferred_i_79__0_n_0)); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_7__0 + (.I0(ip2axi_rddata_int_inferred_i_41__0_n_0), + .I1(ip2axi_rddata_int_inferred_i_34__0_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [25]), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [25]), + .I4(ip2axi_rddata_int_inferred_i_35__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [25])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_8 + (.I0(ip2axi_rddata_int_inferred_i_42_n_0), + .I1(ip2axi_rddata_int_inferred_i_34_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [11]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [21]), + .O(in0[21])); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_80__0 + (.I0(ip2axi_rddata_int_inferred_i_87_n_0), + .I1(\reg_module_hsize_reg[15]_0 [1]), + .I2(ip2axi_rddata_int_inferred_i_88_n_0), + .I3(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [1]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [1]), + .I5(ip2axi_rddata_int_inferred_i_85_n_0), + .O(ip2axi_rddata_int_inferred_i_80__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_81 + (.I0(ip2axi_rddata_int_inferred_i_84_n_0), + .I1(s2mm_dmasr), + .I2(ip2axi_rddata_int_inferred_i_90_n_0), + .I3(\DMA_IRQ_MASK_GEN.dma_irq_mask_i_reg[3] [0]), + .I4(s2mm_dmacr[0]), + .I5(ip2axi_rddata_int_inferred_i_86_n_0), + .O(ip2axi_rddata_int_inferred_i_81_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_82 + (.I0(ip2axi_rddata_int_inferred_i_89_n_0), + .I1(\reg_module_vsize_reg[12] [0]), + .I2(ip2axi_rddata_int_inferred_i_87_n_0), + .I3(\reg_module_hsize_reg[15]_0 [0]), + .I4(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [0]), + .I5(ip2axi_rddata_int_inferred_i_88_n_0), + .O(ip2axi_rddata_int_inferred_i_82_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + ip2axi_rddata_int_inferred_i_83 + (.I0(ip2axi_rddata_int_inferred_i_85_n_0), + .I1(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 [0]), + .I2(ip2axi_rddata_int_inferred_i_35__0_n_0), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [0]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [0]), + .I5(ip2axi_rddata_int_inferred_i_34__0_n_0), + .O(ip2axi_rddata_int_inferred_i_83_n_0)); + LUT6 #( + .INIT(64'h0000000000400000)) + ip2axi_rddata_int_inferred_i_84 + (.I0(axi2ip_rdaddr_captured_s2mm_cdc_tig[7]), + .I1(axi2ip_rdaddr_captured_s2mm_cdc_tig[2]), + .I2(axi2ip_rdaddr_captured_s2mm_cdc_tig[4]), + .I3(axi2ip_rdaddr_captured_s2mm_cdc_tig[6]), + .I4(axi2ip_rdaddr_captured_s2mm_cdc_tig[5]), + .I5(axi2ip_rdaddr_captured_s2mm_cdc_tig[3]), + .O(ip2axi_rddata_int_inferred_i_84_n_0)); + LUT6 #( + .INIT(64'h0000000040000000)) + ip2axi_rddata_int_inferred_i_85 + (.I0(axi2ip_rdaddr_captured_s2mm_cdc_tig[4]), + .I1(axi2ip_rdaddr_captured_s2mm_cdc_tig[2]), + .I2(axi2ip_rdaddr_captured_s2mm_cdc_tig[7]), + .I3(axi2ip_rdaddr_captured_s2mm_cdc_tig[3]), + .I4(axi2ip_rdaddr_captured_s2mm_cdc_tig[5]), + .I5(axi2ip_rdaddr_captured_s2mm_cdc_tig[6]), + .O(ip2axi_rddata_int_inferred_i_85_n_0)); + LUT6 #( + .INIT(64'h0000000000100000)) + ip2axi_rddata_int_inferred_i_86 + (.I0(axi2ip_rdaddr_captured_s2mm_cdc_tig[2]), + .I1(axi2ip_rdaddr_captured_s2mm_cdc_tig[3]), + .I2(axi2ip_rdaddr_captured_s2mm_cdc_tig[5]), + .I3(axi2ip_rdaddr_captured_s2mm_cdc_tig[6]), + .I4(axi2ip_rdaddr_captured_s2mm_cdc_tig[4]), + .I5(axi2ip_rdaddr_captured_s2mm_cdc_tig[7]), + .O(ip2axi_rddata_int_inferred_i_86_n_0)); + LUT6 #( + .INIT(64'h0000000000400000)) + ip2axi_rddata_int_inferred_i_87 + (.I0(axi2ip_rdaddr_captured_s2mm_cdc_tig[4]), + .I1(axi2ip_rdaddr_captured_s2mm_cdc_tig[2]), + .I2(axi2ip_rdaddr_captured_s2mm_cdc_tig[7]), + .I3(axi2ip_rdaddr_captured_s2mm_cdc_tig[3]), + .I4(axi2ip_rdaddr_captured_s2mm_cdc_tig[5]), + .I5(axi2ip_rdaddr_captured_s2mm_cdc_tig[6]), + .O(ip2axi_rddata_int_inferred_i_87_n_0)); + LUT6 #( + .INIT(64'h0000000002000000)) + ip2axi_rddata_int_inferred_i_88 + (.I0(axi2ip_rdaddr_captured_s2mm_cdc_tig[7]), + .I1(axi2ip_rdaddr_captured_s2mm_cdc_tig[2]), + .I2(axi2ip_rdaddr_captured_s2mm_cdc_tig[4]), + .I3(axi2ip_rdaddr_captured_s2mm_cdc_tig[3]), + .I4(axi2ip_rdaddr_captured_s2mm_cdc_tig[5]), + .I5(axi2ip_rdaddr_captured_s2mm_cdc_tig[6]), + .O(ip2axi_rddata_int_inferred_i_88_n_0)); + LUT6 #( + .INIT(64'h0000000000020000)) + ip2axi_rddata_int_inferred_i_89 + (.I0(axi2ip_rdaddr_captured_s2mm_cdc_tig[7]), + .I1(axi2ip_rdaddr_captured_s2mm_cdc_tig[2]), + .I2(axi2ip_rdaddr_captured_s2mm_cdc_tig[4]), + .I3(axi2ip_rdaddr_captured_s2mm_cdc_tig[3]), + .I4(axi2ip_rdaddr_captured_s2mm_cdc_tig[5]), + .I5(axi2ip_rdaddr_captured_s2mm_cdc_tig[6]), + .O(ip2axi_rddata_int_inferred_i_89_n_0)); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_8__0 + (.I0(ip2axi_rddata_int_inferred_i_42__0_n_0), + .I1(ip2axi_rddata_int_inferred_i_34__0_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [24]), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [24]), + .I4(ip2axi_rddata_int_inferred_i_35__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [24])); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_9 + (.I0(ip2axi_rddata_int_inferred_i_43_n_0), + .I1(ip2axi_rddata_int_inferred_i_34_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [10]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 ), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [20]), + .O(in0[20])); + LUT6 #( + .INIT(64'h0000000008000000)) + ip2axi_rddata_int_inferred_i_90 + (.I0(axi2ip_rdaddr_captured_s2mm_cdc_tig[4]), + .I1(axi2ip_rdaddr_captured_s2mm_cdc_tig[2]), + .I2(axi2ip_rdaddr_captured_s2mm_cdc_tig[7]), + .I3(axi2ip_rdaddr_captured_s2mm_cdc_tig[3]), + .I4(axi2ip_rdaddr_captured_s2mm_cdc_tig[5]), + .I5(axi2ip_rdaddr_captured_s2mm_cdc_tig[6]), + .O(ip2axi_rddata_int_inferred_i_90_n_0)); + LUT5 #( + .INIT(32'hFFEAEAEA)) + ip2axi_rddata_int_inferred_i_9__0 + (.I0(ip2axi_rddata_int_inferred_i_43__0_n_0), + .I1(ip2axi_rddata_int_inferred_i_34__0_n_0), + .I2(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 [23]), + .I3(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 [23]), + .I4(ip2axi_rddata_int_inferred_i_35__0_n_0), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 [23])); + LUT4 #( + .INIT(16'h00E0)) + lite_wr_addr_phase_finished_data_phase_started_i_1 + (.I0(lite_wr_addr_phase_finished_data_phase_started), + .I1(s_axi_lite_awready), + .I2(s_axi_lite_resetn), + .I3(s_axi_lite_wready), + .O(lite_wr_addr_phase_finished_data_phase_started_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + lite_wr_addr_phase_finished_data_phase_started_reg + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(lite_wr_addr_phase_finished_data_phase_started_i_1_n_0), + .Q(lite_wr_addr_phase_finished_data_phase_started), + .R(1'b0)); + LUT6 #( + .INIT(64'h0000AE00AE00AE00)) + read_has_started_i_i_1 + (.I0(read_has_started_i), + .I1(arvalid), + .I2(sig_arvalid_arrived_d1), + .I3(s_axi_lite_resetn), + .I4(s_axi_lite_rready), + .I5(s_axi_lite_rvalid), + .O(read_has_started_i_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + read_has_started_i_reg + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(read_has_started_i_i_1_n_0), + .Q(read_has_started_i), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT3 #( + .INIT(8'h08)) + sig_arvalid_arrived_d1_i_1 + (.I0(arvalid), + .I1(s_axi_lite_resetn), + .I2(read_has_started_i), + .O(sig_arvalid_arrived_d1_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + sig_arvalid_arrived_d1_reg + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(sig_arvalid_arrived_d1_i_1_n_0), + .Q(sig_arvalid_arrived_d1), + .R(1'b0)); + LUT3 #( + .INIT(8'h02)) + sig_arvalid_detected + (.I0(arvalid), + .I1(sig_arvalid_arrived_d1), + .I2(read_has_started_i), + .O(sig_arvalid_detected__0)); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT3 #( + .INIT(8'h08)) + sig_awvalid_arrived_d1_i_1 + (.I0(awvalid), + .I1(s_axi_lite_resetn), + .I2(write_has_started), + .O(sig_awvalid_arrived_d1_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + sig_awvalid_arrived_d1_reg + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(sig_awvalid_arrived_d1_i_1_n_0), + .Q(sig_awvalid_arrived_d1), + .R(1'b0)); + LUT3 #( + .INIT(8'h02)) + sig_awvalid_detected + (.I0(awvalid), + .I1(sig_awvalid_arrived_d1), + .I2(write_has_started), + .O(sig_awvalid_detected__0)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[0] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[0]), + .Q(wdata[0]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[10] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[10]), + .Q(wdata[10]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[11] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[11]), + .Q(wdata[11]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[12] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[12]), + .Q(wdata[12]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[13] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[13]), + .Q(wdata[13]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[14] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[14]), + .Q(wdata[14]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[15] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[15]), + .Q(wdata[15]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[16] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[16]), + .Q(wdata[16]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[17] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[17]), + .Q(wdata[17]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[18] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[18]), + .Q(wdata[18]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[19] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[19]), + .Q(wdata[19]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[1] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[1]), + .Q(wdata[1]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[20] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[20]), + .Q(wdata[20]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[21] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[21]), + .Q(wdata[21]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[22] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[22]), + .Q(wdata[22]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[23] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[23]), + .Q(wdata[23]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[24] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[24]), + .Q(wdata[24]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[25] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[25]), + .Q(wdata[25]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[26] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[26]), + .Q(wdata[26]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[27] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[27]), + .Q(wdata[27]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[28] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[28]), + .Q(wdata[28]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[29] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[29]), + .Q(wdata[29]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[2] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[2]), + .Q(wdata[2]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[30] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[30]), + .Q(wdata[30]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[31] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[31]), + .Q(wdata[31]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[3] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[3]), + .Q(wdata[3]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[4] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[4]), + .Q(wdata[4]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[5] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[5]), + .Q(wdata[5]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[6] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[6]), + .Q(wdata[6]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[7] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[7]), + .Q(wdata[7]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[8] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[8]), + .Q(wdata[8]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \wdata_reg[9] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wdata[9]), + .Q(wdata[9]), + .R(SR)); + LUT6 #( + .INIT(64'h0000AE00AE00AE00)) + write_has_started_i_1 + (.I0(write_has_started), + .I1(awvalid), + .I2(sig_awvalid_arrived_d1), + .I3(s_axi_lite_resetn), + .I4(s_axi_lite_bready), + .I5(s_axi_lite_bvalid), + .O(write_has_started_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + write_has_started_reg + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(write_has_started_i_1_n_0), + .Q(write_has_started), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + wvalid_reg + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_axi_lite_wvalid), + .Q(wvalid), + .R(SR)); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_mm2s_linebuf" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_mm2s_linebuf + (out, + mm2s_fifo_pipe_empty, + mm2s_all_lines_xfred, + sig_reset_reg_reg, + m_axis_mm2s_tlast, + m_axis_mm2s_tuser, + \GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 , + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg , + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 , + FULL, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 , + s_valid0, + m_axis_mm2s_tdata, + SR, + m_axi_mm2s_aclk, + scndry_reset2, + m_axis_mm2s_aclk, + mm2s_halt, + Q, + halt_i_reg, + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 , + all_lines_xfred, + m_axis_mm2s_tready, + mm2s_axis_resetn, + p_15_out, + lsig_0ffset_cntr, + mm2s_prmry_resetn, + p_24_out, + hold_ff_q_reg, + WR_EN, + dm2linebuf_mm2s_tdata, + DIN); + output out; + output mm2s_fifo_pipe_empty; + output mm2s_all_lines_xfred; + output sig_reset_reg_reg; + output m_axis_mm2s_tlast; + output [0:0]m_axis_mm2s_tuser; + output \GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 ; + output \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ; + output FULL; + output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 ; + output s_valid0; + output [31:0]m_axis_mm2s_tdata; + input [0:0]SR; + input m_axi_mm2s_aclk; + input scndry_reset2; + input m_axis_mm2s_aclk; + input mm2s_halt; + input [12:0]Q; + input halt_i_reg; + input [0:0]\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ; + input all_lines_xfred; + input m_axis_mm2s_tready; + input mm2s_axis_resetn; + input p_15_out; + input lsig_0ffset_cntr; + input mm2s_prmry_resetn; + input p_24_out; + input hold_ff_q_reg; + input WR_EN; + input [31:0]dm2linebuf_mm2s_tdata; + input [0:0]DIN; + + wire [0:0]DIN; + wire FULL; + wire [0:0]\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ; + wire \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I_n_2 ; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_0 ; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_5 ; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 ; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID_n_4 ; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID_n_5 ; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID_n_7 ; + wire \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter[0]_i_1_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter[10]_i_1_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter[11]_i_1_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_10_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_11_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_12_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_3_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_4_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_5_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_8_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_9_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter[1]_i_1_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter[2]_i_1_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter[3]_i_1_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_1_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_3_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_4_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_5_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_6_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter[5]_i_1_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter[6]_i_1_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter[7]_i_1_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_1_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_3_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_4_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_5_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_6_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter[9]_i_1_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]_i_6_n_1 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]_i_6_n_2 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]_i_6_n_3 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]_i_2_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]_i_2_n_1 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]_i_2_n_2 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]_i_2_n_3 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter_reg[8]_i_2_n_0 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter_reg[8]_i_2_n_1 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter_reg[8]_i_2_n_2 ; + wire \GEN_LINEBUF_NO_SOF.vsize_counter_reg[8]_i_2_n_3 ; + wire \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + wire [12:0]Q; + wire [0:0]SR; + wire WR_EN; + wire all_lines_xfred; + (* async_reg = "true" *) wire [12:0]crnt_vsize_cdc_tig; + (* async_reg = "true" *) wire [12:0]crnt_vsize_d1; + (* async_reg = "true" *) wire [10:0]data_count_ae_threshold_cdc_tig; + (* async_reg = "true" *) wire [10:0]data_count_ae_threshold_d1; + wire [31:0]dm2linebuf_mm2s_tdata; + wire [33:0]fifo_dout; + wire halt_i_reg; + wire hold_ff_q_reg; + wire lsig_0ffset_cntr; + wire m_axi_mm2s_aclk; + wire m_axis_fifo_ainit_nosync; + wire m_axis_mm2s_aclk; + wire [31:0]m_axis_mm2s_tdata; + wire m_axis_mm2s_tlast; + wire m_axis_mm2s_tready; + wire [0:0]m_axis_mm2s_tuser; + wire m_axis_tlast_d1; + wire m_axis_tready_d1; + wire m_axis_tvalid_d1; + wire [12:1]minusOp; + wire mm2s_all_lines_xfred; + wire mm2s_axis_resetn; + wire mm2s_fifo_pipe_empty; + wire mm2s_halt; + wire mm2s_prmry_resetn; + wire out; + wire p_15_out; + wire p_24_out; + wire p_4_in; + wire s_axis_fifo_ainit_nosync_reg; + wire s_valid0; + wire scndry_reset2; + wire sig_reset_reg_reg; + wire sof_flag; + wire [12:0]vsize_counter; + wire [3:3]\NLW_GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]_i_6_CO_UNCONNECTED ; + + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized17 \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I + (.\GEN_LINEBUF_NO_SOF.all_lines_xfred_reg (\GEN_LINEBUF_NO_SOF.all_lines_xfred_reg_n_0 ), + .SR(SR), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .m_axis_mm2s_aclk(m_axis_mm2s_aclk), + .mm2s_all_lines_xfred(mm2s_all_lines_xfred), + .scndry_reset2(scndry_reset2)); + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized20 \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I + (.\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tready_d1_reg (\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I_n_2 ), + .SR(SR), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .m_axis_fifo_ainit_nosync(m_axis_fifo_ainit_nosync), + .m_axis_mm2s_aclk(m_axis_mm2s_aclk), + .m_axis_mm2s_tready(m_axis_mm2s_tready), + .mm2s_axis_resetn(mm2s_axis_resetn), + .mm2s_halt(mm2s_halt), + .p_15_out(p_15_out), + .scndry_reset2(scndry_reset2), + .sig_reset_reg_reg(sig_reset_reg_reg)); + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized16 \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I + (.\GEN_LINEBUF_NO_SOF.all_lines_xfred_reg (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID_n_7 ), + .SR(SR), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .m_axis_mm2s_aclk(m_axis_mm2s_aclk), + .mm2s_fifo_pipe_empty(mm2s_fifo_pipe_empty), + .scndry_reset2(scndry_reset2)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[0] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(Q[0]), + .Q(crnt_vsize_cdc_tig[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[10] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(Q[10]), + .Q(crnt_vsize_cdc_tig[10]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[11] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(Q[11]), + .Q(crnt_vsize_cdc_tig[11]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[12] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(Q[12]), + .Q(crnt_vsize_cdc_tig[12]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[1] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(Q[1]), + .Q(crnt_vsize_cdc_tig[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[2] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(Q[2]), + .Q(crnt_vsize_cdc_tig[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[3] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(Q[3]), + .Q(crnt_vsize_cdc_tig[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[4] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(Q[4]), + .Q(crnt_vsize_cdc_tig[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[5] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(Q[5]), + .Q(crnt_vsize_cdc_tig[5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[6] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(Q[6]), + .Q(crnt_vsize_cdc_tig[6]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[7] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(Q[7]), + .Q(crnt_vsize_cdc_tig[7]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[8] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(Q[8]), + .Q(crnt_vsize_cdc_tig[8]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[9] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(Q[9]), + .Q(crnt_vsize_cdc_tig[9]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[0] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(crnt_vsize_cdc_tig[0]), + .Q(crnt_vsize_d1[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[10] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(crnt_vsize_cdc_tig[10]), + .Q(crnt_vsize_d1[10]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[11] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(crnt_vsize_cdc_tig[11]), + .Q(crnt_vsize_d1[11]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[12] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(crnt_vsize_cdc_tig[12]), + .Q(crnt_vsize_d1[12]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[1] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(crnt_vsize_cdc_tig[1]), + .Q(crnt_vsize_d1[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[2] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(crnt_vsize_cdc_tig[2]), + .Q(crnt_vsize_d1[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[3] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(crnt_vsize_cdc_tig[3]), + .Q(crnt_vsize_d1[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[4] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(crnt_vsize_cdc_tig[4]), + .Q(crnt_vsize_d1[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[5] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(crnt_vsize_cdc_tig[5]), + .Q(crnt_vsize_d1[5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[6] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(crnt_vsize_cdc_tig[6]), + .Q(crnt_vsize_d1[6]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[7] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(crnt_vsize_cdc_tig[7]), + .Q(crnt_vsize_d1[7]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[8] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(crnt_vsize_cdc_tig[8]), + .Q(crnt_vsize_d1[8]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[9] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(crnt_vsize_cdc_tig[9]), + .Q(crnt_vsize_d1[9]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[0] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(1'b0), + .Q(data_count_ae_threshold_cdc_tig[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[10] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(1'b0), + .Q(data_count_ae_threshold_cdc_tig[10]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[1] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(1'b0), + .Q(data_count_ae_threshold_cdc_tig[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[2] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(1'b0), + .Q(data_count_ae_threshold_cdc_tig[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[3] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(1'b0), + .Q(data_count_ae_threshold_cdc_tig[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[4] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(1'b0), + .Q(data_count_ae_threshold_cdc_tig[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[5] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(1'b0), + .Q(data_count_ae_threshold_cdc_tig[5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[6] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(1'b0), + .Q(data_count_ae_threshold_cdc_tig[6]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[7] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(1'b0), + .Q(data_count_ae_threshold_cdc_tig[7]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[8] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(1'b0), + .Q(data_count_ae_threshold_cdc_tig[8]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[9] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(1'b0), + .Q(data_count_ae_threshold_cdc_tig[9]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[0] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(data_count_ae_threshold_cdc_tig[0]), + .Q(data_count_ae_threshold_d1[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[10] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(data_count_ae_threshold_cdc_tig[10]), + .Q(data_count_ae_threshold_d1[10]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[1] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(data_count_ae_threshold_cdc_tig[1]), + .Q(data_count_ae_threshold_d1[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[2] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(data_count_ae_threshold_cdc_tig[2]), + .Q(data_count_ae_threshold_d1[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[3] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(data_count_ae_threshold_cdc_tig[3]), + .Q(data_count_ae_threshold_d1[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[4] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(data_count_ae_threshold_cdc_tig[4]), + .Q(data_count_ae_threshold_d1[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[5] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(data_count_ae_threshold_cdc_tig[5]), + .Q(data_count_ae_threshold_d1[5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[6] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(data_count_ae_threshold_cdc_tig[6]), + .Q(data_count_ae_threshold_d1[6]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[7] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(data_count_ae_threshold_cdc_tig[7]), + .Q(data_count_ae_threshold_d1[7]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[8] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(data_count_ae_threshold_cdc_tig[8]), + .Q(data_count_ae_threshold_d1[8]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[9] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(data_count_ae_threshold_cdc_tig[9]), + .Q(data_count_ae_threshold_d1[9]), + .R(1'b0)); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_afifo_builtin \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO + (.DIN({sof_flag,DIN,dm2linebuf_mm2s_tdata[31:18]}), + .FULL(FULL), + .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ), + .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 ), + .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_5 ), + .\INCLUDE_UNPACKING.lsig_cmd_loaded_reg (\INCLUDE_UNPACKING.lsig_cmd_loaded_reg ), + .WR_EN(WR_EN), + .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata[17:0]), + .fifo_dout(fifo_dout), + .hold_ff_q_reg(hold_ff_q_reg), + .lsig_0ffset_cntr(lsig_0ffset_cntr), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .m_axis_mm2s_aclk(m_axis_mm2s_aclk), + .mm2s_halt(mm2s_halt), + .mm2s_prmry_resetn(mm2s_prmry_resetn), + .out(p_4_in), + .p_24_out(p_24_out), + .s_axis_fifo_ainit_nosync_reg(s_axis_fifo_ainit_nosync_reg), + .sig_m_valid_out_reg(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_5 ), + .Q(sof_flag), + .R(1'b0)); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_skid_buf \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID + (.\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 (sig_reset_reg_reg), + .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID_n_7 ), + .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_0 ), + .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tlast_d1_reg (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID_n_4 ), + .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tvalid_d1_reg (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID_n_5 ), + .\GEN_LINEBUF_NO_SOF.all_lines_xfred_reg (\GEN_LINEBUF_NO_SOF.all_lines_xfred_reg_n_0 ), + .fifo_dout(fifo_dout), + .m_axis_fifo_ainit_nosync(m_axis_fifo_ainit_nosync), + .m_axis_mm2s_aclk(m_axis_mm2s_aclk), + .m_axis_mm2s_tdata(m_axis_mm2s_tdata), + .m_axis_mm2s_tlast(m_axis_mm2s_tlast), + .m_axis_mm2s_tready(m_axis_mm2s_tready), + .m_axis_mm2s_tuser(m_axis_mm2s_tuser), + .m_axis_mm2s_tvalid(out), + .mm2s_axis_resetn(mm2s_axis_resetn), + .out(p_4_in), + .p_15_out(p_15_out), + .s_valid0(s_valid0)); + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tlast_d1_reg + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID_n_4 ), + .Q(m_axis_tlast_d1), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tready_d1_reg + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I_n_2 ), + .Q(m_axis_tready_d1), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tvalid_d1_reg + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID_n_5 ), + .Q(m_axis_tvalid_d1), + .R(1'b0)); + FDSE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg + (.C(m_axis_mm2s_aclk), + .CE(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 ), + .D(all_lines_xfred), + .Q(\GEN_LINEBUF_NO_SOF.all_lines_xfred_reg_n_0 ), + .S(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 )); + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.s_axis_fifo_ainit_nosync_reg_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(halt_i_reg), + .Q(s_axis_fifo_ainit_nosync_reg), + .R(1'b0)); + LUT4 #( + .INIT(16'h8B88)) + \GEN_LINEBUF_NO_SOF.vsize_counter[0]_i_1 + (.I0(crnt_vsize_d1[0]), + .I1(p_15_out), + .I2(vsize_counter[0]), + .I3(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 ), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter[0]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \GEN_LINEBUF_NO_SOF.vsize_counter[10]_i_1 + (.I0(crnt_vsize_d1[10]), + .I1(p_15_out), + .I2(minusOp[10]), + .I3(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 ), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter[10]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \GEN_LINEBUF_NO_SOF.vsize_counter[11]_i_1 + (.I0(crnt_vsize_d1[11]), + .I1(p_15_out), + .I2(minusOp[11]), + .I3(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 ), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter[11]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_10 + (.I0(vsize_counter[11]), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_10_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_11 + (.I0(vsize_counter[10]), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_11_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_12 + (.I0(vsize_counter[9]), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_12_n_0 )); + LUT6 #( + .INIT(64'hBBBBBBBBBBBBBBBA)) + \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2 + (.I0(p_15_out), + .I1(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_4_n_0 ), + .I2(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_5_n_0 ), + .I3(vsize_counter[3]), + .I4(vsize_counter[4]), + .I5(vsize_counter[0]), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_3 + (.I0(crnt_vsize_d1[12]), + .I1(p_15_out), + .I2(minusOp[12]), + .I3(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 ), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_3_n_0 )); + LUT3 #( + .INIT(8'h7F)) + \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_4 + (.I0(m_axis_tvalid_d1), + .I1(m_axis_tlast_d1), + .I2(m_axis_tready_d1), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_4_n_0 )); + LUT5 #( + .INIT(32'hFFFFFFFE)) + \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_5 + (.I0(vsize_counter[1]), + .I1(vsize_counter[10]), + .I2(vsize_counter[7]), + .I3(vsize_counter[12]), + .I4(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_8_n_0 ), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_5_n_0 )); + LUT5 #( + .INIT(32'hFFFFFEFF)) + \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_7 + (.I0(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_5_n_0 ), + .I1(vsize_counter[4]), + .I2(vsize_counter[3]), + .I3(vsize_counter[0]), + .I4(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_4_n_0 ), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_8 + (.I0(vsize_counter[11]), + .I1(vsize_counter[6]), + .I2(vsize_counter[2]), + .I3(vsize_counter[8]), + .I4(vsize_counter[5]), + .I5(vsize_counter[9]), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_8_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_9 + (.I0(vsize_counter[12]), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_9_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \GEN_LINEBUF_NO_SOF.vsize_counter[1]_i_1 + (.I0(crnt_vsize_d1[1]), + .I1(p_15_out), + .I2(minusOp[1]), + .I3(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 ), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter[1]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \GEN_LINEBUF_NO_SOF.vsize_counter[2]_i_1 + (.I0(crnt_vsize_d1[2]), + .I1(p_15_out), + .I2(minusOp[2]), + .I3(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 ), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter[2]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \GEN_LINEBUF_NO_SOF.vsize_counter[3]_i_1 + (.I0(crnt_vsize_d1[3]), + .I1(p_15_out), + .I2(minusOp[3]), + .I3(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 ), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter[3]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_1 + (.I0(crnt_vsize_d1[4]), + .I1(p_15_out), + .I2(minusOp[4]), + .I3(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 ), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_3 + (.I0(vsize_counter[4]), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_3_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_4 + (.I0(vsize_counter[3]), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_5 + (.I0(vsize_counter[2]), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_5_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_6 + (.I0(vsize_counter[1]), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_6_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \GEN_LINEBUF_NO_SOF.vsize_counter[5]_i_1 + (.I0(crnt_vsize_d1[5]), + .I1(p_15_out), + .I2(minusOp[5]), + .I3(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 ), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter[5]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \GEN_LINEBUF_NO_SOF.vsize_counter[6]_i_1 + (.I0(crnt_vsize_d1[6]), + .I1(p_15_out), + .I2(minusOp[6]), + .I3(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 ), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter[6]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \GEN_LINEBUF_NO_SOF.vsize_counter[7]_i_1 + (.I0(crnt_vsize_d1[7]), + .I1(p_15_out), + .I2(minusOp[7]), + .I3(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 ), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter[7]_i_1_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_1 + (.I0(crnt_vsize_d1[8]), + .I1(p_15_out), + .I2(minusOp[8]), + .I3(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 ), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_3 + (.I0(vsize_counter[8]), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_3_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_4 + (.I0(vsize_counter[7]), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_5 + (.I0(vsize_counter[6]), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_5_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_6 + (.I0(vsize_counter[5]), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_6_n_0 )); + LUT4 #( + .INIT(16'hB888)) + \GEN_LINEBUF_NO_SOF.vsize_counter[9]_i_1 + (.I0(crnt_vsize_d1[9]), + .I1(p_15_out), + .I2(minusOp[9]), + .I3(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 ), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter[9]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.vsize_counter_reg[0] + (.C(m_axis_mm2s_aclk), + .CE(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 ), + .D(\GEN_LINEBUF_NO_SOF.vsize_counter[0]_i_1_n_0 ), + .Q(vsize_counter[0]), + .R(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 )); + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.vsize_counter_reg[10] + (.C(m_axis_mm2s_aclk), + .CE(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 ), + .D(\GEN_LINEBUF_NO_SOF.vsize_counter[10]_i_1_n_0 ), + .Q(vsize_counter[10]), + .R(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 )); + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.vsize_counter_reg[11] + (.C(m_axis_mm2s_aclk), + .CE(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 ), + .D(\GEN_LINEBUF_NO_SOF.vsize_counter[11]_i_1_n_0 ), + .Q(vsize_counter[11]), + .R(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 )); + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.vsize_counter_reg[12] + (.C(m_axis_mm2s_aclk), + .CE(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 ), + .D(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_3_n_0 ), + .Q(vsize_counter[12]), + .R(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 )); + CARRY4 \GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]_i_6 + (.CI(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[8]_i_2_n_0 ), + .CO({\NLW_GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]_i_6_CO_UNCONNECTED [3],\GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]_i_6_n_1 ,\GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]_i_6_n_2 ,\GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]_i_6_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,vsize_counter[11:9]}), + .O(minusOp[12:9]), + .S({\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_9_n_0 ,\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_10_n_0 ,\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_11_n_0 ,\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_12_n_0 })); + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.vsize_counter_reg[1] + (.C(m_axis_mm2s_aclk), + .CE(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 ), + .D(\GEN_LINEBUF_NO_SOF.vsize_counter[1]_i_1_n_0 ), + .Q(vsize_counter[1]), + .R(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 )); + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.vsize_counter_reg[2] + (.C(m_axis_mm2s_aclk), + .CE(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 ), + .D(\GEN_LINEBUF_NO_SOF.vsize_counter[2]_i_1_n_0 ), + .Q(vsize_counter[2]), + .R(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 )); + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.vsize_counter_reg[3] + (.C(m_axis_mm2s_aclk), + .CE(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 ), + .D(\GEN_LINEBUF_NO_SOF.vsize_counter[3]_i_1_n_0 ), + .Q(vsize_counter[3]), + .R(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 )); + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4] + (.C(m_axis_mm2s_aclk), + .CE(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 ), + .D(\GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_1_n_0 ), + .Q(vsize_counter[4]), + .R(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 )); + CARRY4 \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]_i_2 + (.CI(1'b0), + .CO({\GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]_i_2_n_0 ,\GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]_i_2_n_1 ,\GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]_i_2_n_2 ,\GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]_i_2_n_3 }), + .CYINIT(vsize_counter[0]), + .DI(vsize_counter[4:1]), + .O(minusOp[4:1]), + .S({\GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_3_n_0 ,\GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_4_n_0 ,\GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_5_n_0 ,\GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_6_n_0 })); + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.vsize_counter_reg[5] + (.C(m_axis_mm2s_aclk), + .CE(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 ), + .D(\GEN_LINEBUF_NO_SOF.vsize_counter[5]_i_1_n_0 ), + .Q(vsize_counter[5]), + .R(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 )); + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.vsize_counter_reg[6] + (.C(m_axis_mm2s_aclk), + .CE(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 ), + .D(\GEN_LINEBUF_NO_SOF.vsize_counter[6]_i_1_n_0 ), + .Q(vsize_counter[6]), + .R(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 )); + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.vsize_counter_reg[7] + (.C(m_axis_mm2s_aclk), + .CE(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 ), + .D(\GEN_LINEBUF_NO_SOF.vsize_counter[7]_i_1_n_0 ), + .Q(vsize_counter[7]), + .R(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 )); + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.vsize_counter_reg[8] + (.C(m_axis_mm2s_aclk), + .CE(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 ), + .D(\GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_1_n_0 ), + .Q(vsize_counter[8]), + .R(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 )); + CARRY4 \GEN_LINEBUF_NO_SOF.vsize_counter_reg[8]_i_2 + (.CI(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]_i_2_n_0 ), + .CO({\GEN_LINEBUF_NO_SOF.vsize_counter_reg[8]_i_2_n_0 ,\GEN_LINEBUF_NO_SOF.vsize_counter_reg[8]_i_2_n_1 ,\GEN_LINEBUF_NO_SOF.vsize_counter_reg[8]_i_2_n_2 ,\GEN_LINEBUF_NO_SOF.vsize_counter_reg[8]_i_2_n_3 }), + .CYINIT(1'b0), + .DI(vsize_counter[8:5]), + .O(minusOp[8:5]), + .S({\GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_3_n_0 ,\GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_4_n_0 ,\GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_5_n_0 ,\GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_6_n_0 })); + FDRE #( + .INIT(1'b0)) + \GEN_LINEBUF_NO_SOF.vsize_counter_reg[9] + (.C(m_axis_mm2s_aclk), + .CE(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 ), + .D(\GEN_LINEBUF_NO_SOF.vsize_counter[9]_i_1_n_0 ), + .Q(vsize_counter[9]), + .R(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 )); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_mngr" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_mngr + (cmnd_wr, + p_58_out, + p_37_out, + prmtr_update_complete, + p_45_out, + stop, + p_50_out, + p_56_out, + datamover_idle, + Q, + p_39_out, + p_47_out, + dma_err, + \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 , + p_2_out, + \INFERRED_GEN.cnt_i_reg[1] , + halted_reg, + dma_interr_reg, + dma_slverr_reg, + dma_decerr_reg, + \sig_addr_cntr_lsh_kh_reg[31] , + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2] , + initial_frame, + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4] , + SR, + m_axi_mm2s_aclk, + mm2s_all_lines_xfred, + mm2s_prmry_resetn, + \INFERRED_GEN.cnt_i_reg[2] , + \INFERRED_GEN.cnt_i_reg[2]_0 , + \INFERRED_GEN.cnt_i_reg[2]_1 , + p_71_out, + prmtr_updt_complete_i_reg, + p_46_out, + halted_reg_0, + E, + sig_halt_cmplt_reg, + p_24_out, + mm2s_fifo_pipe_empty, + p_67_out, + \dmacr_i_reg[2] , + p_77_out, + mm2s_halt, + \INFERRED_GEN.cnt_i_reg[2]_2 , + \ptr_ref_i_reg[4] , + p_70_out, + mask_fsync_out_i, + D, + mm2s_axi2ip_wrce, + dma_interr_reg_0, + dma_slverr_reg_0, + dma_decerr_reg_0, + \reg_module_vsize_reg[12] , + \reg_module_hsize_reg[15] , + prmry_resetn_i_reg, + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] , + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] , + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] , + \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] , + err_i_reg); + output cmnd_wr; + output p_58_out; + output p_37_out; + output prmtr_update_complete; + output p_45_out; + output stop; + output p_50_out; + output p_56_out; + output datamover_idle; + output [12:0]Q; + output p_39_out; + output p_47_out; + output dma_err; + output [4:0]\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 ; + output p_2_out; + output \INFERRED_GEN.cnt_i_reg[1] ; + output halted_reg; + output dma_interr_reg; + output dma_slverr_reg; + output dma_decerr_reg; + output [48:0]\sig_addr_cntr_lsh_kh_reg[31] ; + output [2:0]\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2] ; + output initial_frame; + output [4:0]\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4] ; + input [0:0]SR; + input m_axi_mm2s_aclk; + input mm2s_all_lines_xfred; + input mm2s_prmry_resetn; + input \INFERRED_GEN.cnt_i_reg[2] ; + input \INFERRED_GEN.cnt_i_reg[2]_0 ; + input \INFERRED_GEN.cnt_i_reg[2]_1 ; + input [1:0]p_71_out; + input prmtr_updt_complete_i_reg; + input p_46_out; + input [0:0]halted_reg_0; + input [0:0]E; + input sig_halt_cmplt_reg; + input p_24_out; + input mm2s_fifo_pipe_empty; + input p_67_out; + input \dmacr_i_reg[2] ; + input p_77_out; + input mm2s_halt; + input [0:0]\INFERRED_GEN.cnt_i_reg[2]_2 ; + input [4:0]\ptr_ref_i_reg[4] ; + input p_70_out; + input mask_fsync_out_i; + input [0:0]D; + input [0:0]mm2s_axi2ip_wrce; + input dma_interr_reg_0; + input dma_slverr_reg_0; + input dma_decerr_reg_0; + input [12:0]\reg_module_vsize_reg[12] ; + input [15:0]\reg_module_hsize_reg[15] ; + input [0:0]prmry_resetn_i_reg; + input [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] ; + input [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] ; + input [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] ; + input [15:0]\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ; + input [0:0]err_i_reg; + + wire [0:0]D; + wire [0:0]E; + wire [2:0]\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2] ; + wire [4:0]\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4] ; + wire [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] ; + wire [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] ; + wire [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] ; + wire \INFERRED_GEN.cnt_i_reg[1] ; + wire \INFERRED_GEN.cnt_i_reg[2] ; + wire \INFERRED_GEN.cnt_i_reg[2]_0 ; + wire \INFERRED_GEN.cnt_i_reg[2]_1 ; + wire [0:0]\INFERRED_GEN.cnt_i_reg[2]_2 ; + wire I_CMDSTS_n_1; + wire I_CMDSTS_n_3; + wire I_SM_n_25; + wire I_SM_n_26; + wire I_SM_n_27; + wire I_SM_n_28; + wire I_SM_n_29; + wire I_SM_n_30; + wire I_SM_n_31; + wire I_SM_n_32; + wire I_SM_n_33; + wire I_SM_n_34; + wire I_SM_n_35; + wire I_SM_n_36; + wire I_SM_n_37; + wire I_SM_n_38; + wire I_SM_n_39; + wire I_SM_n_40; + wire I_SM_n_41; + wire I_SM_n_42; + wire I_SM_n_43; + wire I_SM_n_44; + wire I_SM_n_45; + wire I_SM_n_46; + wire I_SM_n_47; + wire I_SM_n_48; + wire I_SM_n_49; + wire I_SM_n_50; + wire I_SM_n_51; + wire I_SM_n_52; + wire I_SM_n_53; + wire I_SM_n_54; + wire I_SM_n_55; + wire I_SM_n_56; + wire I_SM_n_57; + wire I_SM_n_58; + wire I_SM_n_59; + wire I_SM_n_60; + wire I_SM_n_61; + wire I_SM_n_62; + wire I_SM_n_63; + wire I_SM_n_64; + wire I_SM_n_65; + wire I_SM_n_66; + wire I_SM_n_67; + wire I_SM_n_68; + wire I_SM_n_69; + wire I_SM_n_70; + wire I_SM_n_71; + wire I_SM_n_72; + wire I_SM_n_73; + wire [4:0]\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 ; + wire \MASTER_MODE_FRAME_CNT.frame_number_i[0]_i_1_n_0 ; + wire \MASTER_MODE_FRAME_CNT.frame_number_i[1]_i_1_n_0 ; + wire \MASTER_MODE_FRAME_CNT.frame_number_i[2]_i_1_n_0 ; + wire \MASTER_MODE_FRAME_CNT.frame_number_i[3]_i_1_n_0 ; + wire \MASTER_MODE_FRAME_CNT.frame_number_i[3]_i_2_n_0 ; + wire \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_3_n_0 ; + wire \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_5_n_0 ; + wire [15:0]\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ; + wire [12:0]Q; + wire [0:0]SR; + wire VIDEO_GENLOCK_I_n_1; + wire VIDEO_REG_I_n_32; + wire VIDEO_REG_I_n_35; + wire VIDEO_REG_I_n_36; + wire VIDEO_REG_I_n_37; + wire VIDEO_REG_I_n_38; + wire VIDEO_REG_I_n_39; + wire VIDEO_REG_I_n_40; + wire VIDEO_REG_I_n_41; + wire VIDEO_REG_I_n_42; + wire VIDEO_REG_I_n_43; + wire VIDEO_REG_I_n_44; + wire VIDEO_REG_I_n_45; + wire VIDEO_REG_I_n_46; + wire VIDEO_REG_I_n_47; + wire VIDEO_REG_I_n_48; + wire VIDEO_REG_I_n_49; + wire VIDEO_REG_I_n_50; + wire VIDEO_REG_I_n_51; + wire VIDEO_REG_I_n_52; + wire VIDEO_REG_I_n_53; + wire VIDEO_REG_I_n_54; + wire VIDEO_REG_I_n_55; + wire VIDEO_REG_I_n_56; + wire VIDEO_REG_I_n_57; + wire VIDEO_REG_I_n_58; + wire VIDEO_REG_I_n_59; + wire VIDEO_REG_I_n_60; + wire VIDEO_REG_I_n_61; + wire VIDEO_REG_I_n_62; + wire VIDEO_REG_I_n_63; + wire VIDEO_REG_I_n_64; + wire VIDEO_REG_I_n_65; + wire VIDEO_REG_I_n_66; + wire VIDEO_REG_I_n_67; + wire VIDEO_REG_I_n_68; + wire cmnd_wr; + wire [15:0]crnt_hsize; + wire datamover_idle; + wire [15:0]dm_address_reg; + wire dma_decerr_reg; + wire dma_decerr_reg_0; + wire dma_err; + wire dma_interr_reg; + wire dma_interr_reg_0; + wire dma_slverr_reg; + wire dma_slverr_reg_0; + wire \dmacr_i_reg[2] ; + wire [0:0]err_i_reg; + wire frame_sync_reg; + wire halted_reg; + wire [0:0]halted_reg_0; + wire halted_set_i0; + wire initial_frame; + wire initial_frame_i_1_n_0; + wire load_new_addr; + wire m_axi_mm2s_aclk; + wire mask_fsync_out_i; + wire mm2s_all_lines_xfred; + wire [0:0]mm2s_axi2ip_wrce; + wire mm2s_fifo_pipe_empty; + wire mm2s_halt; + wire mm2s_prmry_resetn; + wire [1:1]num_fstore_minus1; + wire p_10_out; + wire p_24_out; + wire p_2_out; + wire p_37_out; + wire p_39_out; + wire p_45_out; + wire p_46_out; + wire p_47_out; + wire p_50_out; + wire p_56_out; + wire p_58_out; + wire p_67_out; + wire p_70_out; + wire [1:0]p_71_out; + wire p_77_out; + wire [0:0]prmry_resetn_i_reg; + wire prmtr_update_complete; + wire prmtr_updt_complete_i_reg; + wire [4:0]\ptr_ref_i_reg[4] ; + wire [15:0]\reg_module_hsize_reg[15] ; + wire [12:0]\reg_module_vsize_reg[12] ; + wire [48:0]\sig_addr_cntr_lsh_kh_reg[31] ; + wire sig_halt_cmplt_reg; + wire stop; + wire stop_i; + wire tstvect_fsync_d1; + wire tstvect_fsync_d2; + wire valid_frame_sync_d1; + wire valid_frame_sync_d2; + wire zero_hsize_err; + wire zero_hsize_err0; + wire zero_vsize_err; + wire zero_vsize_err0; + + Arty_Z7_20_axi_vdma_0_0_axi_vdma_cmdsts_if I_CMDSTS + (.D({I_SM_n_25,I_SM_n_26,I_SM_n_27,I_SM_n_28,I_SM_n_29,I_SM_n_30,I_SM_n_31,I_SM_n_32,I_SM_n_33,I_SM_n_34,I_SM_n_35,I_SM_n_36,I_SM_n_37,I_SM_n_38,I_SM_n_39,I_SM_n_40,I_SM_n_41,I_SM_n_42,I_SM_n_43,I_SM_n_44,I_SM_n_45,I_SM_n_46,I_SM_n_47,I_SM_n_48,I_SM_n_49,I_SM_n_50,I_SM_n_51,I_SM_n_52,I_SM_n_53,I_SM_n_54,I_SM_n_55,I_SM_n_56,I_SM_n_57,I_SM_n_58,I_SM_n_59,I_SM_n_60,I_SM_n_61,I_SM_n_62,I_SM_n_63,I_SM_n_64,I_SM_n_65,I_SM_n_66,I_SM_n_67,I_SM_n_68,I_SM_n_69,I_SM_n_70,I_SM_n_71,I_SM_n_72,I_SM_n_73}), + .E(E), + .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from (I_CMDSTS_n_3), + .\GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg (p_56_out), + .\GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg_0 (cmnd_wr), + .\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg (p_47_out), + .\INFERRED_GEN.cnt_i_reg[1] (\INFERRED_GEN.cnt_i_reg[1] ), + .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ), + .\INFERRED_GEN.cnt_i_reg[2]_0 (\INFERRED_GEN.cnt_i_reg[2]_0 ), + .\INFERRED_GEN.cnt_i_reg[2]_1 (\INFERRED_GEN.cnt_i_reg[2]_1 ), + .\INFERRED_GEN.cnt_i_reg[2]_2 (\INFERRED_GEN.cnt_i_reg[2]_2 ), + .SR(SR), + .\cmnds_queued_reg[0] (p_58_out), + .dma_decerr_reg(dma_decerr_reg), + .dma_decerr_reg_0(dma_decerr_reg_0), + .dma_slverr_reg(dma_slverr_reg), + .dma_slverr_reg_0(dma_slverr_reg_0), + .err_i_reg_0(I_CMDSTS_n_1), + .frame_sync_reg(frame_sync_reg), + .halted_reg(halted_reg_0), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .mm2s_halt(mm2s_halt), + .mm2s_prmry_resetn(mm2s_prmry_resetn), + .p_71_out(p_71_out[0]), + .p_77_out(p_77_out), + .\sig_addr_cntr_lsh_kh_reg[31] (\sig_addr_cntr_lsh_kh_reg[31] ), + .stop_i(stop_i), + .stop_reg(dma_err), + .zero_hsize_err(zero_hsize_err), + .zero_vsize_err(zero_vsize_err)); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_sm I_SM + (.CO(VIDEO_REG_I_n_64), + .D({I_SM_n_25,I_SM_n_26,I_SM_n_27,I_SM_n_28,I_SM_n_29,I_SM_n_30,I_SM_n_31,I_SM_n_32,I_SM_n_33,I_SM_n_34,I_SM_n_35,I_SM_n_36,I_SM_n_37,I_SM_n_38,I_SM_n_39,I_SM_n_40,I_SM_n_41,I_SM_n_42,I_SM_n_43,I_SM_n_44,I_SM_n_45,I_SM_n_46,I_SM_n_47,I_SM_n_48,I_SM_n_49,I_SM_n_50,I_SM_n_51,I_SM_n_52,I_SM_n_53,I_SM_n_54,I_SM_n_55,I_SM_n_56,I_SM_n_57,I_SM_n_58,I_SM_n_59,I_SM_n_60,I_SM_n_61,I_SM_n_62,I_SM_n_63,I_SM_n_64,I_SM_n_65,I_SM_n_66,I_SM_n_67,I_SM_n_68,I_SM_n_69,I_SM_n_70,I_SM_n_71,I_SM_n_72,I_SM_n_73}), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] (D), + .\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 (dm_address_reg), + .\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg (p_47_out), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][16] (VIDEO_REG_I_n_35), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][17] (VIDEO_REG_I_n_36), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][18] (VIDEO_REG_I_n_37), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][19] (VIDEO_REG_I_n_38), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][20] (VIDEO_REG_I_n_39), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][21] (VIDEO_REG_I_n_40), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][22] (VIDEO_REG_I_n_41), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][23] (VIDEO_REG_I_n_42), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][24] (VIDEO_REG_I_n_43), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][25] (VIDEO_REG_I_n_44), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][26] (VIDEO_REG_I_n_45), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][27] (VIDEO_REG_I_n_46), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][28] (VIDEO_REG_I_n_47), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][29] (VIDEO_REG_I_n_48), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][30] (VIDEO_REG_I_n_49), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] (VIDEO_REG_I_n_50), + .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2]_2 ), + .O({VIDEO_REG_I_n_52,VIDEO_REG_I_n_53,VIDEO_REG_I_n_54,VIDEO_REG_I_n_55}), + .Q(Q), + .SR(SR), + .datamover_idle(datamover_idle), + .dma_err(dma_err), + .dma_interr_reg(dma_interr_reg), + .dma_interr_reg_0(dma_interr_reg_0), + .\dmacr_i_reg[2] (\dmacr_i_reg[2] ), + .err_i_reg(err_i_reg), + .frame_sync_reg(frame_sync_reg), + .halt_i_reg(I_CMDSTS_n_3), + .halted_set_i0(halted_set_i0), + .\hsize_vid_reg[15] (crnt_hsize), + .interr_i_reg(I_CMDSTS_n_1), + .load_new_addr(load_new_addr), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .mm2s_all_lines_xfred(mm2s_all_lines_xfred), + .mm2s_axi2ip_wrce(mm2s_axi2ip_wrce), + .mm2s_fifo_pipe_empty(mm2s_fifo_pipe_empty), + .mm2s_halt(mm2s_halt), + .mm2s_prmry_resetn(mm2s_prmry_resetn), + .p_24_out(p_24_out), + .p_39_out(p_39_out), + .p_58_out(p_58_out), + .p_71_out(p_71_out[0]), + .p_77_out(p_77_out), + .s_axis_cmd_tvalid_reg(cmnd_wr), + .s_axis_cmd_tvalid_reg_0(p_56_out), + .\stride_vid_reg[11] ({VIDEO_REG_I_n_60,VIDEO_REG_I_n_61,VIDEO_REG_I_n_62,VIDEO_REG_I_n_63}), + .\stride_vid_reg[15] ({VIDEO_REG_I_n_65,VIDEO_REG_I_n_66,VIDEO_REG_I_n_67,VIDEO_REG_I_n_68}), + .\stride_vid_reg[7] ({VIDEO_REG_I_n_56,VIDEO_REG_I_n_57,VIDEO_REG_I_n_58,VIDEO_REG_I_n_59}), + .tstvect_fsync_d1(tstvect_fsync_d1), + .tstvect_fsync_d2(tstvect_fsync_d2), + .zero_hsize_err(zero_hsize_err), + .zero_hsize_err0(zero_hsize_err0), + .zero_vsize_err(zero_vsize_err), + .zero_vsize_err0(zero_vsize_err0)); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_sts_mngr_42 I_STS_MNGR + (.\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 (VIDEO_REG_I_n_32), + .SR(SR), + .datamover_idle(datamover_idle), + .halted_reg(halted_reg), + .halted_set_i0(halted_set_i0), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .mm2s_prmry_resetn(mm2s_prmry_resetn), + .p_37_out(p_37_out), + .p_70_out(p_70_out), + .p_71_out(p_71_out[0]), + .sig_halt_cmplt_reg(sig_halt_cmplt_reg)); + FDRE \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [0]), + .Q(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4] [0]), + .R(SR)); + FDRE \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [1]), + .Q(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4] [1]), + .R(SR)); + FDRE \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [2]), + .Q(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4] [2]), + .R(SR)); + FDRE \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [3]), + .Q(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4] [3]), + .R(SR)); + FDRE \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [4]), + .Q(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4] [4]), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair43" *) + LUT5 #( + .INIT(32'h080808FB)) + \MASTER_MODE_FRAME_CNT.frame_number_i[0]_i_1 + (.I0(\ptr_ref_i_reg[4] [0]), + .I1(valid_frame_sync_d2), + .I2(p_71_out[1]), + .I3(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [0]), + .I4(VIDEO_GENLOCK_I_n_1), + .O(\MASTER_MODE_FRAME_CNT.frame_number_i[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h080808FB08FB0808)) + \MASTER_MODE_FRAME_CNT.frame_number_i[1]_i_1 + (.I0(\ptr_ref_i_reg[4] [1]), + .I1(valid_frame_sync_d2), + .I2(p_71_out[1]), + .I3(VIDEO_GENLOCK_I_n_1), + .I4(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [1]), + .I5(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [0]), + .O(\MASTER_MODE_FRAME_CNT.frame_number_i[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'h08FBFB08FB08FB08)) + \MASTER_MODE_FRAME_CNT.frame_number_i[2]_i_1 + (.I0(\ptr_ref_i_reg[4] [2]), + .I1(valid_frame_sync_d2), + .I2(p_71_out[1]), + .I3(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [2]), + .I4(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [1]), + .I5(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [0]), + .O(\MASTER_MODE_FRAME_CNT.frame_number_i[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'h8BB8B8B8B8B8B8B8)) + \MASTER_MODE_FRAME_CNT.frame_number_i[3]_i_1 + (.I0(\ptr_ref_i_reg[4] [3]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i[3]_i_2_n_0 ), + .I2(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [3]), + .I3(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [0]), + .I4(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [1]), + .I5(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [2]), + .O(\MASTER_MODE_FRAME_CNT.frame_number_i[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair43" *) + LUT2 #( + .INIT(4'h2)) + \MASTER_MODE_FRAME_CNT.frame_number_i[3]_i_2 + (.I0(valid_frame_sync_d2), + .I1(p_71_out[1]), + .O(\MASTER_MODE_FRAME_CNT.frame_number_i[3]_i_2_n_0 )); + LUT6 #( + .INIT(64'h08FBFB08FB08FB08)) + \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_3 + (.I0(\ptr_ref_i_reg[4] [4]), + .I1(valid_frame_sync_d2), + .I2(p_71_out[1]), + .I3(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [4]), + .I4(\MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_5_n_0 ), + .I5(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [3]), + .O(\MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_3_n_0 )); + LUT3 #( + .INIT(8'h80)) + \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_5 + (.I0(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [2]), + .I1(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [1]), + .I2(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [0]), + .O(\MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_5_n_0 )); + FDRE #( + .INIT(1'b0)) + \MASTER_MODE_FRAME_CNT.frame_number_i_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(VIDEO_REG_I_n_51), + .D(\MASTER_MODE_FRAME_CNT.frame_number_i[0]_i_1_n_0 ), + .Q(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [0]), + .R(prmry_resetn_i_reg)); + FDRE #( + .INIT(1'b0)) + \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(VIDEO_REG_I_n_51), + .D(\MASTER_MODE_FRAME_CNT.frame_number_i[1]_i_1_n_0 ), + .Q(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [1]), + .R(prmry_resetn_i_reg)); + FDRE #( + .INIT(1'b0)) + \MASTER_MODE_FRAME_CNT.frame_number_i_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(VIDEO_REG_I_n_51), + .D(\MASTER_MODE_FRAME_CNT.frame_number_i[2]_i_1_n_0 ), + .Q(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [2]), + .R(prmry_resetn_i_reg)); + FDRE #( + .INIT(1'b0)) + \MASTER_MODE_FRAME_CNT.frame_number_i_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(VIDEO_REG_I_n_51), + .D(\MASTER_MODE_FRAME_CNT.frame_number_i[3]_i_1_n_0 ), + .Q(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [3]), + .R(prmry_resetn_i_reg)); + FDRE #( + .INIT(1'b0)) + \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(VIDEO_REG_I_n_51), + .D(\MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_3_n_0 ), + .Q(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [4]), + .R(prmry_resetn_i_reg)); + FDRE \MASTER_MODE_FRAME_CNT.tstvect_fsync_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(p_10_out), + .Q(p_50_out), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \MASTER_MODE_FRAME_CNT.valid_frame_sync_d1_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(p_46_out), + .Q(valid_frame_sync_d1), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \MASTER_MODE_FRAME_CNT.valid_frame_sync_d2_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(valid_frame_sync_d1), + .Q(valid_frame_sync_d2), + .R(SR)); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_genlock_mngr VIDEO_GENLOCK_I + (.\GENLOCK_FOR_MASTER.mstr_reverse_order_reg_0 (VIDEO_GENLOCK_I_n_1), + .\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2] (\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2] ), + .Q(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 ), + .SR(SR), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .mm2s_prmry_resetn(mm2s_prmry_resetn), + .num_fstore_minus1(num_fstore_minus1), + .p_45_out(p_45_out), + .p_70_out(p_70_out), + .p_71_out(p_71_out[1]), + .valid_frame_sync_d2(valid_frame_sync_d2)); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_vidreg_module_43 VIDEO_REG_I + (.CO(VIDEO_REG_I_n_64), + .E(VIDEO_REG_I_n_51), + .\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] (crnt_hsize), + .\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] (\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] ), + .\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] (\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] ), + .\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] (\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] ), + .\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] (\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [1:0]), + .\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]_0 (VIDEO_GENLOCK_I_n_1), + .\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] (\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ), + .O({VIDEO_REG_I_n_52,VIDEO_REG_I_n_53,VIDEO_REG_I_n_54,VIDEO_REG_I_n_55}), + .Q(Q), + .SR(SR), + .all_idle_reg(VIDEO_REG_I_n_32), + .\dm_address_reg[11] ({VIDEO_REG_I_n_60,VIDEO_REG_I_n_61,VIDEO_REG_I_n_62,VIDEO_REG_I_n_63}), + .\dm_address_reg[15] ({VIDEO_REG_I_n_65,VIDEO_REG_I_n_66,VIDEO_REG_I_n_67,VIDEO_REG_I_n_68}), + .\dm_address_reg[15]_0 (dm_address_reg), + .\dm_address_reg[19] (VIDEO_REG_I_n_35), + .\dm_address_reg[19]_0 (VIDEO_REG_I_n_36), + .\dm_address_reg[19]_1 (VIDEO_REG_I_n_37), + .\dm_address_reg[19]_2 (VIDEO_REG_I_n_38), + .\dm_address_reg[23] (VIDEO_REG_I_n_39), + .\dm_address_reg[23]_0 (VIDEO_REG_I_n_40), + .\dm_address_reg[23]_1 (VIDEO_REG_I_n_41), + .\dm_address_reg[23]_2 (VIDEO_REG_I_n_42), + .\dm_address_reg[27] (VIDEO_REG_I_n_43), + .\dm_address_reg[27]_0 (VIDEO_REG_I_n_44), + .\dm_address_reg[27]_1 (VIDEO_REG_I_n_45), + .\dm_address_reg[27]_2 (VIDEO_REG_I_n_46), + .\dm_address_reg[31] (VIDEO_REG_I_n_47), + .\dm_address_reg[31]_0 (VIDEO_REG_I_n_48), + .\dm_address_reg[31]_1 (VIDEO_REG_I_n_49), + .\dm_address_reg[31]_2 (VIDEO_REG_I_n_50), + .\dm_address_reg[7] ({VIDEO_REG_I_n_56,VIDEO_REG_I_n_57,VIDEO_REG_I_n_58,VIDEO_REG_I_n_59}), + .load_new_addr(load_new_addr), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .mask_fsync_out_i(mask_fsync_out_i), + .mm2s_fifo_pipe_empty(mm2s_fifo_pipe_empty), + .mm2s_prmry_resetn(mm2s_prmry_resetn), + .p_10_out(p_10_out), + .p_24_out(p_24_out), + .p_2_out(p_2_out), + .p_39_out(p_39_out), + .p_67_out(p_67_out), + .p_70_out(p_70_out), + .p_71_out(p_71_out[1]), + .prmtr_updt_complete_i_reg(prmtr_updt_complete_i_reg), + .\reg_module_hsize_reg[15] (\reg_module_hsize_reg[15] ), + .\reg_module_vsize_reg[12] (\reg_module_vsize_reg[12] ), + .\stride_vid_reg[0] (prmtr_update_complete), + .\stride_vid_reg[0]_0 (p_47_out), + .tstvect_fsync_d1(tstvect_fsync_d1), + .tstvect_fsync_d2(tstvect_fsync_d2), + .valid_frame_sync_d2(valid_frame_sync_d2), + .zero_hsize_err0(zero_hsize_err0), + .zero_vsize_err0(zero_vsize_err0)); + LUT4 #( + .INIT(16'h00E0)) + initial_frame_i_1 + (.I0(initial_frame), + .I1(p_24_out), + .I2(mm2s_prmry_resetn), + .I3(p_70_out), + .O(initial_frame_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + initial_frame_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(initial_frame_i_1_n_0), + .Q(initial_frame), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \num_fstore_minus1_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(1'b1), + .Q(num_fstore_minus1), + .R(SR)); + FDRE stop_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(stop_i), + .Q(stop), + .R(SR)); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_mngr" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_mngr__parameterized0 + (fsize_mismatch_err, + cmnd_wr, + drop_fsync_d_pulse_gen_fsize_less_err_d1, + fsize_mismatch_err_s1, + m_axis_s2mm_sts_tready, + lsize_mismatch_err, + lsize_more_mismatch_err, + prmtr_update_complete, + s2mm_valid_frame_sync, + s2mm_stop, + s2mm_tstvect_fsync, + num_fstore_minus1, + s_axis_s2mm_cmd_tvalid, + datamover_idle, + halt_i0, + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg , + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_irqthresh_decr_mask_sig_reg , + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[0] , + Q, + \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] , + s2mm_ftchcmdsts_idle, + \DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 , + s2mm_valid_video_prmtrs, + dma_err, + s2mm_dma_interr_set_minus_frame_errors, + S, + \GEN_STS_GRTR_THAN_8.undrflo_err_reg , + p_2_out, + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_fsize_less_err_flag_10_reg , + halted_reg, + dma_slverr_reg, + dma_decerr_reg, + \S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg , + \sig_input_addr_reg_reg[31] , + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2] , + initial_frame, + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[4] , + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[4] , + prmry_reset2, + s_axis_s2mm_aclk, + SR, + m_axi_s2mm_aclk, + s2mm_fsync_out_m_i, + drop_fsync_d_pulse_gen_fsize_less_err, + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg , + out, + \INFERRED_GEN.cnt_i_reg[2] , + \INFERRED_GEN.cnt_i_reg[2]_0 , + \INFERRED_GEN.cnt_i_reg[2]_1 , + p_12_out, + p_9_out, + s2mm_dmacr, + prmtr_updt_complete_i_reg, + s2mm_valid_frame_sync_cmb, + halted_reg_0, + E, + sig_halt_cmplt_reg, + s2mm_cdc2dmac_fsync, + run_stop_d1, + s2mm_soft_reset, + soft_reset_d1, + prmry_resetn_i_reg, + ch2_delay_cnt_en, + s2mm_packet_sof, + ch2_irqthresh_decr_mask_sig, + s2mm_halt, + halt_i_reg, + \INFERRED_GEN.cnt_i_reg[2]_2 , + \ptr_ref_i_reg[4] , + m_axis_s2mm_sts_tdata, + s2mm_dmasr, + mask_fsync_out_i, + s2mm_fsize_less_err_flag_10, + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 , + \sig_user_reg_out_reg[0] , + dma_slverr_reg_0, + dma_decerr_reg_0, + D, + s2mm_axi2ip_wrce, + \S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg_0 , + \reg_module_vsize_reg[12] , + \reg_module_hsize_reg[15] , + prmry_resetn_i_reg_0, + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] , + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] , + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] , + \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] , + \GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[2] , + err_i_reg); + output fsize_mismatch_err; + output cmnd_wr; + output drop_fsync_d_pulse_gen_fsize_less_err_d1; + output fsize_mismatch_err_s1; + output m_axis_s2mm_sts_tready; + output lsize_mismatch_err; + output lsize_more_mismatch_err; + output prmtr_update_complete; + output s2mm_valid_frame_sync; + output s2mm_stop; + output s2mm_tstvect_fsync; + output [0:0]num_fstore_minus1; + output s_axis_s2mm_cmd_tvalid; + output datamover_idle; + output halt_i0; + output \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg ; + output \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_irqthresh_decr_mask_sig_reg ; + output [0:0]\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[0] ; + output [12:0]Q; + output [12:0]\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] ; + output s2mm_ftchcmdsts_idle; + output [4:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 ; + output s2mm_valid_video_prmtrs; + output dma_err; + output s2mm_dma_interr_set_minus_frame_errors; + output [0:0]S; + output [0:0]\GEN_STS_GRTR_THAN_8.undrflo_err_reg ; + output p_2_out; + output \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_fsize_less_err_flag_10_reg ; + output halted_reg; + output dma_slverr_reg; + output dma_decerr_reg; + output \S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg ; + output [48:0]\sig_input_addr_reg_reg[31] ; + output [2:0]\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2] ; + output initial_frame; + output [4:0]\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[4] ; + output [4:0]\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[4] ; + input prmry_reset2; + input s_axis_s2mm_aclk; + input [0:0]SR; + input m_axi_s2mm_aclk; + input s2mm_fsync_out_m_i; + input drop_fsync_d_pulse_gen_fsize_less_err; + input \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg ; + input out; + input \INFERRED_GEN.cnt_i_reg[2] ; + input \INFERRED_GEN.cnt_i_reg[2]_0 ; + input \INFERRED_GEN.cnt_i_reg[2]_1 ; + input p_12_out; + input p_9_out; + input [3:0]s2mm_dmacr; + input prmtr_updt_complete_i_reg; + input s2mm_valid_frame_sync_cmb; + input [0:0]halted_reg_0; + input [0:0]E; + input sig_halt_cmplt_reg; + input s2mm_cdc2dmac_fsync; + input run_stop_d1; + input s2mm_soft_reset; + input soft_reset_d1; + input prmry_resetn_i_reg; + input ch2_delay_cnt_en; + input s2mm_packet_sof; + input ch2_irqthresh_decr_mask_sig; + input s2mm_halt; + input halt_i_reg; + input [0:0]\INFERRED_GEN.cnt_i_reg[2]_2 ; + input [4:0]\ptr_ref_i_reg[4] ; + input [0:0]m_axis_s2mm_sts_tdata; + input [0:0]s2mm_dmasr; + input mask_fsync_out_i; + input s2mm_fsize_less_err_flag_10; + input \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ; + input \sig_user_reg_out_reg[0] ; + input dma_slverr_reg_0; + input dma_decerr_reg_0; + input [0:0]D; + input [0:0]s2mm_axi2ip_wrce; + input \S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg_0 ; + input [12:0]\reg_module_vsize_reg[12] ; + input [15:0]\reg_module_hsize_reg[15] ; + input [0:0]prmry_resetn_i_reg_0; + input [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] ; + input [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] ; + input [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] ; + input [15:0]\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ; + input [2:0]\GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[2] ; + input [0:0]err_i_reg; + + wire [0:0]D; + wire [15:0]\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ; + wire \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[1]_i_3_n_0 ; + wire \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_5_n_0 ; + wire \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_8_n_0 ; + wire [4:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 ; + wire \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr[4]_i_1_n_0 ; + wire [0:0]E; + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ; + wire [2:0]\GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[2] ; + wire [2:0]\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2] ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_irqthresh_decr_mask_sig_reg ; + wire [12:0]\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] ; + wire [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] ; + wire [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] ; + wire [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg ; + wire [0:0]\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[0] ; + wire [4:0]\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[4] ; + wire [4:0]\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[4] ; + wire \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_fsize_less_err_flag_10_reg ; + wire [0:0]\GEN_STS_GRTR_THAN_8.undrflo_err_reg ; + wire \INFERRED_GEN.cnt_i_reg[2] ; + wire \INFERRED_GEN.cnt_i_reg[2]_0 ; + wire \INFERRED_GEN.cnt_i_reg[2]_1 ; + wire [0:0]\INFERRED_GEN.cnt_i_reg[2]_2 ; + wire I_CMDSTS_n_1; + wire I_CMDSTS_n_5; + wire I_CMDSTS_n_8; + wire I_SM_n_31; + wire I_SM_n_32; + wire I_SM_n_33; + wire I_SM_n_34; + wire I_SM_n_35; + wire I_SM_n_37; + wire I_SM_n_38; + wire I_SM_n_39; + wire I_SM_n_40; + wire I_SM_n_41; + wire I_SM_n_42; + wire I_SM_n_43; + wire I_SM_n_44; + wire I_SM_n_45; + wire I_SM_n_46; + wire I_SM_n_47; + wire I_SM_n_48; + wire I_SM_n_49; + wire I_SM_n_50; + wire I_SM_n_51; + wire I_SM_n_52; + wire I_SM_n_53; + wire I_SM_n_54; + wire I_SM_n_55; + wire I_SM_n_56; + wire I_SM_n_57; + wire I_SM_n_58; + wire I_SM_n_59; + wire I_SM_n_60; + wire I_SM_n_61; + wire I_SM_n_62; + wire I_SM_n_63; + wire I_SM_n_64; + wire I_SM_n_65; + wire I_SM_n_66; + wire I_SM_n_67; + wire I_SM_n_68; + wire I_SM_n_69; + wire I_SM_n_70; + wire I_SM_n_71; + wire I_SM_n_72; + wire I_SM_n_73; + wire I_SM_n_74; + wire I_SM_n_75; + wire I_SM_n_76; + wire I_SM_n_77; + wire I_SM_n_78; + wire I_SM_n_79; + wire I_SM_n_80; + wire I_SM_n_81; + wire I_SM_n_82; + wire I_SM_n_83; + wire I_SM_n_84; + wire I_SM_n_85; + wire I_SM_n_86; + wire I_SM_n_88; + wire [12:0]Q; + wire [0:0]S; + wire \S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg ; + wire \S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg_0 ; + wire [0:0]SR; + wire VIDEO_GENLOCK_I_n_1; + wire VIDEO_GENLOCK_I_n_2; + wire VIDEO_GENLOCK_I_n_3; + wire VIDEO_GENLOCK_I_n_4; + wire VIDEO_GENLOCK_I_n_5; + wire VIDEO_REG_I_n_34; + wire VIDEO_REG_I_n_35; + wire VIDEO_REG_I_n_36; + wire VIDEO_REG_I_n_37; + wire VIDEO_REG_I_n_38; + wire VIDEO_REG_I_n_39; + wire VIDEO_REG_I_n_40; + wire VIDEO_REG_I_n_41; + wire VIDEO_REG_I_n_42; + wire VIDEO_REG_I_n_43; + wire VIDEO_REG_I_n_44; + wire VIDEO_REG_I_n_45; + wire VIDEO_REG_I_n_46; + wire VIDEO_REG_I_n_47; + wire VIDEO_REG_I_n_48; + wire VIDEO_REG_I_n_49; + wire VIDEO_REG_I_n_52; + wire VIDEO_REG_I_n_53; + wire VIDEO_REG_I_n_54; + wire VIDEO_REG_I_n_55; + wire VIDEO_REG_I_n_56; + wire VIDEO_REG_I_n_57; + wire VIDEO_REG_I_n_58; + wire VIDEO_REG_I_n_59; + wire VIDEO_REG_I_n_60; + wire VIDEO_REG_I_n_61; + wire VIDEO_REG_I_n_62; + wire VIDEO_REG_I_n_63; + wire VIDEO_REG_I_n_64; + wire VIDEO_REG_I_n_65; + wire VIDEO_REG_I_n_66; + wire VIDEO_REG_I_n_67; + wire VIDEO_REG_I_n_68; + wire ch2_delay_cnt_en; + wire ch2_irqthresh_decr_mask_sig; + wire cmnd_wr; + wire [2:0]crnt_hsize; + wire datamover_idle; + wire [15:0]dm_address_reg; + wire [4:0]dm_prev_frame_number; + wire dma_decerr_reg; + wire dma_decerr_reg_0; + wire dma_err; + wire dma_slverr_reg; + wire dma_slverr_reg_0; + wire drop_fsync_d_pulse_gen_fsize_less_err; + wire drop_fsync_d_pulse_gen_fsize_less_err_d1; + wire [0:0]err_i_reg; + wire flag_to_repeat_after_fsize_less_err; + wire frame_number_i; + wire fsize_mismatch_err; + wire fsize_mismatch_err_s1; + wire halt_i0; + wire halt_i_reg; + wire halted_reg; + wire [0:0]halted_reg_0; + wire halted_set_i0; + wire initial_frame; + wire initial_frame_i_1__0_n_0; + wire load_new_addr; + wire lsize_mismatch_err; + wire lsize_more_mismatch_err; + wire m_axi_s2mm_aclk; + wire [0:0]m_axis_s2mm_sts_tdata; + wire m_axis_s2mm_sts_tready; + wire mask_fsync_out_i; + wire [0:0]num_fstore_minus1; + wire out; + wire p_12_out; + wire p_24_out; + wire p_26_out; + wire p_2_out; + wire p_9_out; + wire prmry_reset2; + wire prmry_resetn_i_reg; + wire [0:0]prmry_resetn_i_reg_0; + wire prmtr_update_complete; + wire prmtr_updt_complete_i_reg; + wire [4:0]\ptr_ref_i_reg[4] ; + wire [15:0]\reg_module_hsize_reg[15] ; + wire [12:0]\reg_module_vsize_reg[12] ; + wire repeat_frame; + wire [4:0]repeat_frame_nmbr; + wire run_stop_d1; + wire [0:0]s2mm_axi2ip_wrce; + wire s2mm_cdc2dmac_fsync; + wire s2mm_dma_interr_set_minus_frame_errors; + wire [3:0]s2mm_dmacr; + wire [0:0]s2mm_dmasr; + wire s2mm_fsize_less_err_flag_10; + wire s2mm_fsync_out_m_i; + wire s2mm_ftchcmdsts_idle; + wire s2mm_halt; + wire s2mm_packet_sof; + wire s2mm_soft_reset; + wire s2mm_stop; + wire s2mm_tstvect_fsync; + wire s2mm_valid_frame_sync; + wire s2mm_valid_frame_sync_cmb; + wire s2mm_valid_video_prmtrs; + wire s_axis_s2mm_aclk; + wire s_axis_s2mm_cmd_tvalid; + wire [4:0]s_h_frame_number; + wire sig_halt_cmplt_reg; + wire [48:0]\sig_input_addr_reg_reg[31] ; + wire \sig_user_reg_out_reg[0] ; + wire [3:0]slv_frame_ref_out; + wire soft_reset_d1; + wire stop_i; + wire tstvect_fsync_d1; + wire tstvect_fsync_d2; + wire valid_frame_sync_d1; + wire valid_frame_sync_d2; + wire zero_hsize_err; + wire zero_hsize_err0; + wire zero_vsize_err; + wire zero_vsize_err0; + + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFF6)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[1]_i_3 + (.I0(\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [1]), + .I1(num_fstore_minus1), + .I2(\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [0]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [2]), + .I4(\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [3]), + .I5(\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [4]), + .O(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[1]_i_3_n_0 )); + LUT4 #( + .INIT(16'h00F8)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_2 + (.I0(repeat_frame), + .I1(s2mm_dmacr[3]), + .I2(valid_frame_sync_d2), + .I3(flag_to_repeat_after_fsize_less_err), + .O(frame_number_i)); + LUT2 #( + .INIT(4'h8)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_5 + (.I0(repeat_frame), + .I1(s2mm_dmacr[3]), + .O(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_5_n_0 )); + LUT2 #( + .INIT(4'h7)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_8 + (.I0(valid_frame_sync_d2), + .I1(s2mm_dmacr[2]), + .O(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_8_n_0 )); + FDRE #( + .INIT(1'b0)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(frame_number_i), + .D(VIDEO_GENLOCK_I_n_5), + .Q(\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [0]), + .R(prmry_resetn_i_reg_0)); + FDRE #( + .INIT(1'b0)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(frame_number_i), + .D(VIDEO_GENLOCK_I_n_4), + .Q(\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [1]), + .R(prmry_resetn_i_reg_0)); + FDRE #( + .INIT(1'b0)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(frame_number_i), + .D(VIDEO_GENLOCK_I_n_3), + .Q(\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [2]), + .R(prmry_resetn_i_reg_0)); + FDRE #( + .INIT(1'b0)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(frame_number_i), + .D(VIDEO_GENLOCK_I_n_2), + .Q(\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [3]), + .R(prmry_resetn_i_reg_0)); + FDRE #( + .INIT(1'b0)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(frame_number_i), + .D(VIDEO_GENLOCK_I_n_1), + .Q(\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [4]), + .R(prmry_resetn_i_reg_0)); + FDRE #( + .INIT(1'b0)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF.flag_to_repeat_after_fsize_less_err_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(I_SM_n_88), + .Q(flag_to_repeat_after_fsize_less_err), + .R(1'b0)); + FDRE \DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [0]), + .Q(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[4] [0]), + .R(SR)); + FDRE \DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [1]), + .Q(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[4] [1]), + .R(SR)); + FDRE \DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [2]), + .Q(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[4] [2]), + .R(SR)); + FDRE \DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [3]), + .Q(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[4] [3]), + .R(SR)); + FDRE \DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [4]), + .Q(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[4] [4]), + .R(SR)); + LUT4 #( + .INIT(16'h0444)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number[4]_i_1 + (.I0(flag_to_repeat_after_fsize_less_err), + .I1(valid_frame_sync_d2), + .I2(s2mm_dmacr[3]), + .I3(repeat_frame), + .O(p_24_out)); + FDRE #( + .INIT(1'b0)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(p_24_out), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [0]), + .Q(dm_prev_frame_number[0]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(p_24_out), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [1]), + .Q(dm_prev_frame_number[1]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(p_24_out), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [2]), + .Q(dm_prev_frame_number[2]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(p_24_out), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [3]), + .Q(dm_prev_frame_number[3]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(p_24_out), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [4]), + .Q(dm_prev_frame_number[4]), + .R(SR)); + FDRE \DYNAMIC_MASTER_MODE_FRAME_CNT.genlock_pair_frame_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(slv_frame_ref_out[0]), + .Q(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[4] [0]), + .R(SR)); + FDRE \DYNAMIC_MASTER_MODE_FRAME_CNT.genlock_pair_frame_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(slv_frame_ref_out[1]), + .Q(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[4] [1]), + .R(SR)); + FDRE \DYNAMIC_MASTER_MODE_FRAME_CNT.genlock_pair_frame_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(slv_frame_ref_out[3]), + .Q(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[4] [2]), + .R(SR)); + FDRE \DYNAMIC_MASTER_MODE_FRAME_CNT.genlock_pair_frame_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(slv_frame_ref_out[3]), + .Q(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[4] [3]), + .R(SR)); + FDRE \DYNAMIC_MASTER_MODE_FRAME_CNT.genlock_pair_frame_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(slv_frame_ref_out[3]), + .Q(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[4] [4]), + .R(SR)); + LUT3 #( + .INIT(8'h4F)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr[4]_i_1 + (.I0(flag_to_repeat_after_fsize_less_err), + .I1(valid_frame_sync_d2), + .I2(out), + .O(\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr[4]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(I_CMDSTS_n_5), + .D(I_SM_n_35), + .Q(repeat_frame_nmbr[0]), + .R(\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr[4]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(I_CMDSTS_n_5), + .D(I_SM_n_34), + .Q(repeat_frame_nmbr[1]), + .R(\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr[4]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(I_CMDSTS_n_5), + .D(I_SM_n_33), + .Q(repeat_frame_nmbr[2]), + .R(\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr[4]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(I_CMDSTS_n_5), + .D(I_SM_n_32), + .Q(repeat_frame_nmbr[3]), + .R(\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr[4]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(I_CMDSTS_n_5), + .D(I_SM_n_31), + .Q(repeat_frame_nmbr[4]), + .R(\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr[4]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(I_CMDSTS_n_8), + .Q(repeat_frame), + .R(1'b0)); + FDRE \DYNAMIC_MASTER_MODE_FRAME_CNT.tstvect_fsync_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(p_26_out), + .Q(s2mm_tstvect_fsync), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.valid_frame_sync_d1_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s2mm_valid_frame_sync_cmb), + .Q(valid_frame_sync_d1), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.valid_frame_sync_d2_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(valid_frame_sync_d1), + .Q(valid_frame_sync_d2), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_cdc2dmac_fsync), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [0]), + .Q(s_h_frame_number[0]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_cdc2dmac_fsync), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [1]), + .Q(s_h_frame_number[1]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_cdc2dmac_fsync), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [2]), + .Q(s_h_frame_number[2]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_cdc2dmac_fsync), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [3]), + .Q(s_h_frame_number[3]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_cdc2dmac_fsync), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [4]), + .Q(s_h_frame_number[4]), + .R(SR)); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_cmdsts_if__parameterized0 I_CMDSTS + (.D({I_SM_n_38,I_SM_n_39,I_SM_n_40,I_SM_n_41,I_SM_n_42,I_SM_n_43,I_SM_n_44,I_SM_n_45,I_SM_n_46,I_SM_n_47,I_SM_n_48,I_SM_n_49,I_SM_n_50,I_SM_n_51,I_SM_n_52,I_SM_n_53,I_SM_n_54,I_SM_n_55,I_SM_n_56,I_SM_n_57,I_SM_n_58,I_SM_n_59,I_SM_n_60,I_SM_n_61,I_SM_n_62,I_SM_n_63,I_SM_n_64,I_SM_n_65,I_SM_n_66,I_SM_n_67,I_SM_n_68,I_SM_n_69,I_SM_n_70,I_SM_n_71,I_SM_n_72,I_SM_n_73,I_SM_n_74,I_SM_n_75,I_SM_n_76,I_SM_n_77,I_SM_n_78,I_SM_n_79,I_SM_n_80,I_SM_n_81,I_SM_n_82,I_SM_n_83,I_SM_n_84,I_SM_n_85,I_SM_n_86}), + .\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr_reg[4] (I_CMDSTS_n_5), + .\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_reg (I_CMDSTS_n_8), + .E(E), + .\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out (fsize_mismatch_err), + .\GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg (cmnd_wr), + .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ), + .\INFERRED_GEN.cnt_i_reg[2]_0 (\INFERRED_GEN.cnt_i_reg[2]_0 ), + .\INFERRED_GEN.cnt_i_reg[2]_1 (\INFERRED_GEN.cnt_i_reg[2]_1 ), + .SR(SR), + .dma_decerr_reg(dma_decerr_reg), + .dma_decerr_reg_0(dma_decerr_reg_0), + .dma_slverr_reg(dma_slverr_reg), + .dma_slverr_reg_0(dma_slverr_reg_0), + .err_i_reg_0(I_CMDSTS_n_1), + .flag_to_repeat_after_fsize_less_err(flag_to_repeat_after_fsize_less_err), + .halted_reg(halted_reg_0), + .lsize_mismatch_err(lsize_mismatch_err), + .lsize_more_mismatch_err(lsize_more_mismatch_err), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .m_axis_s2mm_sts_tready(m_axis_s2mm_sts_tready), + .out(out), + .p_12_out(p_12_out), + .p_9_out(p_9_out), + .repeat_frame(repeat_frame), + .s2mm_soft_reset(s2mm_soft_reset), + .\sig_input_addr_reg_reg[31] (\sig_input_addr_reg_reg[31] ), + .stop_i(stop_i), + .stop_reg(dma_err), + .valid_frame_sync_d2(valid_frame_sync_d2), + .\vert_count_reg[0] (s_axis_s2mm_cmd_tvalid), + .zero_hsize_err(zero_hsize_err), + .zero_vsize_err(zero_vsize_err)); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_sm__parameterized0 I_SM + (.CO(VIDEO_REG_I_n_64), + .D({I_SM_n_31,I_SM_n_32,I_SM_n_33,I_SM_n_34,I_SM_n_35}), + .\DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_reg (I_SM_n_37), + .\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] (\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 ), + .\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF.flag_to_repeat_after_fsize_less_err_reg (I_SM_n_88), + .\DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[4] ({dm_prev_frame_number[4:2],dm_prev_frame_number[0]}), + .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ), + .\GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[4] (s_h_frame_number), + .\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg (fsize_mismatch_err), + .\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0 (\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg ), + .\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_irqthresh_decr_mask_sig_reg (\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_irqthresh_decr_mask_sig_reg ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4] (D), + .\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 (dm_address_reg), + .\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg (s2mm_valid_video_prmtrs), + .\GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg (\GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[0] (\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[0] ), + .\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_fsize_less_err_flag_10_reg (\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_fsize_less_err_flag_10_reg ), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][16] (VIDEO_REG_I_n_34), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][17] (VIDEO_REG_I_n_35), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][18] (VIDEO_REG_I_n_36), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][19] (VIDEO_REG_I_n_37), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][20] (VIDEO_REG_I_n_38), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][21] (VIDEO_REG_I_n_39), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][22] (VIDEO_REG_I_n_40), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][23] (VIDEO_REG_I_n_41), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][24] (VIDEO_REG_I_n_42), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][25] (VIDEO_REG_I_n_43), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][26] (VIDEO_REG_I_n_44), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][27] (VIDEO_REG_I_n_45), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][28] (VIDEO_REG_I_n_46), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][29] (VIDEO_REG_I_n_47), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][30] (VIDEO_REG_I_n_48), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] (VIDEO_REG_I_n_49), + .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2]_2 ), + .O({VIDEO_REG_I_n_52,VIDEO_REG_I_n_53,VIDEO_REG_I_n_54,VIDEO_REG_I_n_55}), + .Q(Q), + .\S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg (\S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg ), + .\S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg_0 (\S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg_0 ), + .SR(SR), + .ch2_delay_cnt_en(ch2_delay_cnt_en), + .ch2_irqthresh_decr_mask_sig(ch2_irqthresh_decr_mask_sig), + .datamover_idle(datamover_idle), + .dma_err(dma_err), + .drop_fsync_d_pulse_gen_fsize_less_err(drop_fsync_d_pulse_gen_fsize_less_err), + .drop_fsync_d_pulse_gen_fsize_less_err_d1(drop_fsync_d_pulse_gen_fsize_less_err_d1), + .err_i_reg(err_i_reg), + .flag_to_repeat_after_fsize_less_err(flag_to_repeat_after_fsize_less_err), + .fsize_mismatch_err_s1(fsize_mismatch_err_s1), + .halt_i0(halt_i0), + .halt_i_reg(halt_i_reg), + .halted_set_i0(halted_set_i0), + .\hsize_vid_reg[15] ({\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] ,crnt_hsize}), + .interr_i_reg(I_CMDSTS_n_1), + .load_new_addr(load_new_addr), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .m_axis_s2mm_sts_tready(m_axis_s2mm_sts_tready), + .out(out), + .prmry_reset2(prmry_reset2), + .prmry_resetn_i_reg(prmry_resetn_i_reg), + .run_stop_d1(run_stop_d1), + .s2mm_axi2ip_wrce(s2mm_axi2ip_wrce), + .s2mm_cdc2dmac_fsync(s2mm_cdc2dmac_fsync), + .s2mm_dma_interr_set_minus_frame_errors(s2mm_dma_interr_set_minus_frame_errors), + .s2mm_dmacr(s2mm_dmacr[1:0]), + .s2mm_fsize_less_err_flag_10(s2mm_fsize_less_err_flag_10), + .s2mm_fsync_out_m_i(s2mm_fsync_out_m_i), + .s2mm_ftchcmdsts_idle(s2mm_ftchcmdsts_idle), + .s2mm_halt(s2mm_halt), + .s2mm_packet_sof(s2mm_packet_sof), + .s2mm_soft_reset(s2mm_soft_reset), + .s2mm_stop(s2mm_stop), + .s2mm_tstvect_fsync(s2mm_tstvect_fsync), + .\s_axis_cmd_tdata_reg[63] ({I_SM_n_38,I_SM_n_39,I_SM_n_40,I_SM_n_41,I_SM_n_42,I_SM_n_43,I_SM_n_44,I_SM_n_45,I_SM_n_46,I_SM_n_47,I_SM_n_48,I_SM_n_49,I_SM_n_50,I_SM_n_51,I_SM_n_52,I_SM_n_53,I_SM_n_54,I_SM_n_55,I_SM_n_56,I_SM_n_57,I_SM_n_58,I_SM_n_59,I_SM_n_60,I_SM_n_61,I_SM_n_62,I_SM_n_63,I_SM_n_64,I_SM_n_65,I_SM_n_66,I_SM_n_67,I_SM_n_68,I_SM_n_69,I_SM_n_70,I_SM_n_71,I_SM_n_72,I_SM_n_73,I_SM_n_74,I_SM_n_75,I_SM_n_76,I_SM_n_77,I_SM_n_78,I_SM_n_79,I_SM_n_80,I_SM_n_81,I_SM_n_82,I_SM_n_83,I_SM_n_84,I_SM_n_85,I_SM_n_86}), + .s_axis_cmd_tvalid_reg(cmnd_wr), + .s_axis_cmd_tvalid_reg_0(s_axis_s2mm_cmd_tvalid), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk), + .\sig_user_reg_out_reg[0] (\sig_user_reg_out_reg[0] ), + .soft_reset_d1(soft_reset_d1), + .\stride_vid_reg[11] ({VIDEO_REG_I_n_60,VIDEO_REG_I_n_61,VIDEO_REG_I_n_62,VIDEO_REG_I_n_63}), + .\stride_vid_reg[15] ({VIDEO_REG_I_n_65,VIDEO_REG_I_n_66,VIDEO_REG_I_n_67,VIDEO_REG_I_n_68}), + .\stride_vid_reg[7] ({VIDEO_REG_I_n_56,VIDEO_REG_I_n_57,VIDEO_REG_I_n_58,VIDEO_REG_I_n_59}), + .tstvect_fsync_d1(tstvect_fsync_d1), + .tstvect_fsync_d2(tstvect_fsync_d2), + .valid_frame_sync_d2(valid_frame_sync_d2), + .zero_hsize_err(zero_hsize_err), + .zero_hsize_err0(zero_hsize_err0), + .zero_vsize_err(zero_vsize_err), + .zero_vsize_err0(zero_vsize_err0)); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_sts_mngr I_STS_MNGR + (.SR(SR), + .datamover_idle(datamover_idle), + .halted_reg(halted_reg), + .halted_set_i0(halted_set_i0), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out), + .s2mm_dmacr(s2mm_dmacr[0]), + .s2mm_dmasr(s2mm_dmasr), + .sig_halt_cmplt_reg(sig_halt_cmplt_reg)); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_genlock_mngr__parameterized0 VIDEO_GENLOCK_I + (.D({VIDEO_GENLOCK_I_n_1,VIDEO_GENLOCK_I_n_2,VIDEO_GENLOCK_I_n_3,VIDEO_GENLOCK_I_n_4,VIDEO_GENLOCK_I_n_5}), + .\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] (\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[1]_i_3_n_0 ), + .\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] (\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 ), + .\DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[0] (I_SM_n_37), + .\DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[2] (dm_prev_frame_number[2:0]), + .\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_reg (\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_5_n_0 ), + .\DYNAMIC_MASTER_MODE_FRAME_CNT.valid_frame_sync_d2_reg (\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_8_n_0 ), + .\GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[2] (\GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[2] ), + .\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2] (\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2] ), + .Q(repeat_frame_nmbr), + .SR(SR), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .\num_fstore_minus1_reg[1] (num_fstore_minus1), + .out(out), + .\ptr_ref_i_reg[4] (\ptr_ref_i_reg[4] ), + .s2mm_dmacr(s2mm_dmacr[2:1]), + .s2mm_dmasr(s2mm_dmasr), + .s2mm_valid_frame_sync(s2mm_valid_frame_sync), + .slv_frame_ref_out({slv_frame_ref_out[3],slv_frame_ref_out[1:0]}), + .valid_frame_sync_d2(valid_frame_sync_d2)); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_vidreg_module VIDEO_REG_I + (.CO(VIDEO_REG_I_n_64), + .\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] (\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ), + .\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] (\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [1:0]), + .\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] (\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] ), + .\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] (\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] ), + .\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] (\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] (Q), + .\GEN_STS_GRTR_THAN_8.undrflo_err_reg (\GEN_STS_GRTR_THAN_8.undrflo_err_reg ), + .O({VIDEO_REG_I_n_52,VIDEO_REG_I_n_53,VIDEO_REG_I_n_54,VIDEO_REG_I_n_55}), + .Q({\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] ,crnt_hsize}), + .S(S), + .SR(SR), + .\dm_address_reg[11] ({VIDEO_REG_I_n_60,VIDEO_REG_I_n_61,VIDEO_REG_I_n_62,VIDEO_REG_I_n_63}), + .\dm_address_reg[15] ({VIDEO_REG_I_n_65,VIDEO_REG_I_n_66,VIDEO_REG_I_n_67,VIDEO_REG_I_n_68}), + .\dm_address_reg[15]_0 (dm_address_reg), + .\dm_address_reg[19] (VIDEO_REG_I_n_34), + .\dm_address_reg[19]_0 (VIDEO_REG_I_n_35), + .\dm_address_reg[19]_1 (VIDEO_REG_I_n_36), + .\dm_address_reg[19]_2 (VIDEO_REG_I_n_37), + .\dm_address_reg[23] (VIDEO_REG_I_n_38), + .\dm_address_reg[23]_0 (VIDEO_REG_I_n_39), + .\dm_address_reg[23]_1 (VIDEO_REG_I_n_40), + .\dm_address_reg[23]_2 (VIDEO_REG_I_n_41), + .\dm_address_reg[27] (VIDEO_REG_I_n_42), + .\dm_address_reg[27]_0 (VIDEO_REG_I_n_43), + .\dm_address_reg[27]_1 (VIDEO_REG_I_n_44), + .\dm_address_reg[27]_2 (VIDEO_REG_I_n_45), + .\dm_address_reg[31] (VIDEO_REG_I_n_46), + .\dm_address_reg[31]_0 (VIDEO_REG_I_n_47), + .\dm_address_reg[31]_1 (VIDEO_REG_I_n_48), + .\dm_address_reg[31]_2 (VIDEO_REG_I_n_49), + .\dm_address_reg[7] ({VIDEO_REG_I_n_56,VIDEO_REG_I_n_57,VIDEO_REG_I_n_58,VIDEO_REG_I_n_59}), + .load_new_addr(load_new_addr), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .m_axis_s2mm_sts_tdata(m_axis_s2mm_sts_tdata), + .mask_fsync_out_i(mask_fsync_out_i), + .out(out), + .p_26_out(p_26_out), + .p_2_out(p_2_out), + .prmtr_update_complete(prmtr_update_complete), + .prmtr_updt_complete_i_reg(prmtr_updt_complete_i_reg), + .\reg_module_hsize_reg[15] (\reg_module_hsize_reg[15] ), + .\reg_module_vsize_reg[12] (\reg_module_vsize_reg[12] ), + .s2mm_cdc2dmac_fsync(s2mm_cdc2dmac_fsync), + .s2mm_dmasr(s2mm_dmasr), + .\stride_vid_reg[0] (s2mm_valid_video_prmtrs), + .tstvect_fsync_d1(tstvect_fsync_d1), + .tstvect_fsync_d2(tstvect_fsync_d2), + .zero_hsize_err0(zero_hsize_err0), + .zero_vsize_err0(zero_vsize_err0)); + LUT4 #( + .INIT(16'h00E0)) + initial_frame_i_1__0 + (.I0(initial_frame), + .I1(s2mm_cdc2dmac_fsync), + .I2(out), + .I3(s2mm_dmasr), + .O(initial_frame_i_1__0_n_0)); + FDRE #( + .INIT(1'b0)) + initial_frame_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(initial_frame_i_1__0_n_0), + .Q(initial_frame), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \num_fstore_minus1_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(1'b1), + .Q(num_fstore_minus1), + .R(SR)); + FDRE stop_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(stop_i), + .Q(s2mm_stop), + .R(SR)); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_reg_if" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_if + (D, + out, + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31] , + mm2s_introut, + s2mm_introut, + s_axi_lite_awready, + s_axi_lite_wready, + s_axi_lite_arready, + dmacr_i, + mm2s_axi2ip_wrce, + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] , + in0, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_0 , + p_15_out, + s2mm_axi2ip_wrce, + p_14_out, + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]_0 , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31] , + prmtr_updt_complete_i_reg, + prmtr_updt_complete_i_reg_0, + ioc_irq_reg, + dly_irq_reg, + dma_interr_reg, + \GEN_FOR_FLUSH.fsize_err_reg , + lsize_err_reg, + \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg , + ioc_irq_reg_0, + dly_irq_reg_0, + lsize_more_err_reg, + s_axi_lite_bvalid, + s_axi_lite_rvalid, + s_axi_lite_rdata, + SR, + s_axi_lite_aclk, + prmry_reset2, + m_axi_mm2s_aclk, + prmry_reset2_0, + m_axi_s2mm_aclk, + p_78_out, + s2mm_ip2axi_introut, + Q, + \ptr_ref_i_reg[4] , + \MM2S_ERR_FOR_IRQ.frm_store_i_reg[4] , + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[4] , + s_axi_lite_wvalid, + s_axi_lite_awvalid, + s_axi_lite_arvalid, + s_axi_lite_resetn, + p_71_out, + mm2s_prmry_resetn, + stop, + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_reg , + \reg_module_hsize_reg[0] , + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] , + \reg_module_hsize_reg[3] , + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] , + \reg_module_hsize_reg[4] , + \reg_module_hsize_reg[5] , + \reg_module_hsize_reg[6] , + \reg_module_hsize_reg[7] , + \reg_module_hsize_reg[8] , + \reg_module_hsize_reg[9] , + \reg_module_hsize_reg[10] , + \reg_module_hsize_reg[11] , + \reg_module_hsize_reg[12] , + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] , + \reg_module_hsize_reg[15] , + \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] , + p_70_out, + dma_interr_reg_0, + \M_GEN_DMACR_REGISTER.dmacr_i_reg[14] , + dma_slverr_reg, + dma_decerr_reg, + ioc_irq_reg_1, + dly_irq_reg_1, + err_irq_reg, + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] , + ch1_irqdelay_status, + s2mm_dmacr, + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31]_0 , + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[23] , + s2mm_prmry_resetn, + s2mm_dmasr, + \DMA_IRQ_MASK_GEN.dma_irq_mask_i_reg[3] , + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 , + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 , + \reg_module_vsize_reg[12] , + s2mm_soft_reset, + \reg_module_hsize_reg[15]_0 , + \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] , + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 , + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7] , + ch2_irqdelay_status, + dma_interr_reg_1, + dma_slverr_reg_0, + dma_decerr_reg_0, + \GEN_FOR_FLUSH.fsize_err_reg_0 , + lsize_err_reg_0, + \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14] , + \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg_0 , + ioc_irq_reg_2, + dly_irq_reg_2, + err_irq_reg_0, + lsize_more_err_reg_0, + mm2s_ioc_irq_set, + ch1_dly_irq_set, + s2mm_dma_interr_set_minus_frame_errors, + s2mm_fsize_more_or_sof_late, + fsize_mismatch_err, + lsize_mismatch_err, + s2mm_ioc_irq_set, + ch2_dly_irq_set, + lsize_more_mismatch_err, + s_axi_lite_bready, + s_axi_lite_rready, + s_axi_lite_araddr, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 , + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 , + s_axi_lite_wdata, + s_axi_lite_awaddr, + \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4] , + \DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4] , + \DYNAMIC_MASTER_MODE_FRAME_CNT.genlock_pair_frame_reg[4] ); + output [31:0]D; + output [1:0]out; + output [31:0]\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31] ; + output mm2s_introut; + output s2mm_introut; + output s_axi_lite_awready; + output s_axi_lite_wready; output s_axi_lite_arready; - input [8:0]s_axi_lite_araddr; + output [0:0]dmacr_i; + output [8:0]mm2s_axi2ip_wrce; + output [0:0]\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] ; + output [28:0]in0; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12] ; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31] ; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11] ; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15] ; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_0 ; + output p_15_out; + output [9:0]s2mm_axi2ip_wrce; + output p_14_out; + output [0:0]\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]_0 ; + output [31:0]\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31] ; + output prmtr_updt_complete_i_reg; + output prmtr_updt_complete_i_reg_0; + output ioc_irq_reg; + output dly_irq_reg; + output dma_interr_reg; + output \GEN_FOR_FLUSH.fsize_err_reg ; + output lsize_err_reg; + output \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg ; + output ioc_irq_reg_0; + output dly_irq_reg_0; + output lsize_more_err_reg; + output s_axi_lite_bvalid; output s_axi_lite_rvalid; - input s_axi_lite_rready; output [31:0]s_axi_lite_rdata; - output [1:0]s_axi_lite_rresp; - input mm2s_fsync; - input [5:0]mm2s_frame_ptr_in; - output [5:0]mm2s_frame_ptr_out; - input s2mm_fsync; - input [5:0]s2mm_frame_ptr_in; - output [5:0]s2mm_frame_ptr_out; - output mm2s_buffer_empty; - output mm2s_buffer_almost_empty; - output s2mm_buffer_full; - output s2mm_buffer_almost_full; - output mm2s_fsync_out; - output s2mm_fsync_out; - output mm2s_prmtr_update; - output s2mm_prmtr_update; - output [31:0]m_axi_sg_araddr; - output [7:0]m_axi_sg_arlen; - output [2:0]m_axi_sg_arsize; - output [1:0]m_axi_sg_arburst; - output [2:0]m_axi_sg_arprot; - output [3:0]m_axi_sg_arcache; - output m_axi_sg_arvalid; - input m_axi_sg_arready; - input [31:0]m_axi_sg_rdata; - input [1:0]m_axi_sg_rresp; - input m_axi_sg_rlast; - input m_axi_sg_rvalid; - output m_axi_sg_rready; - output [31:0]m_axi_mm2s_araddr; - output [7:0]m_axi_mm2s_arlen; - output [2:0]m_axi_mm2s_arsize; - output [1:0]m_axi_mm2s_arburst; - output [2:0]m_axi_mm2s_arprot; - output [3:0]m_axi_mm2s_arcache; - output m_axi_mm2s_arvalid; - input m_axi_mm2s_arready; - input [63:0]m_axi_mm2s_rdata; - input [1:0]m_axi_mm2s_rresp; - input m_axi_mm2s_rlast; - input m_axi_mm2s_rvalid; - output m_axi_mm2s_rready; - output mm2s_prmry_reset_out_n; - output [31:0]m_axis_mm2s_tdata; - output [3:0]m_axis_mm2s_tkeep; - output [0:0]m_axis_mm2s_tuser; - output m_axis_mm2s_tvalid; - input m_axis_mm2s_tready; - output m_axis_mm2s_tlast; - output [31:0]m_axi_s2mm_awaddr; - output [7:0]m_axi_s2mm_awlen; - output [2:0]m_axi_s2mm_awsize; - output [1:0]m_axi_s2mm_awburst; - output [2:0]m_axi_s2mm_awprot; - output [3:0]m_axi_s2mm_awcache; - output m_axi_s2mm_awvalid; - input m_axi_s2mm_awready; - output [63:0]m_axi_s2mm_wdata; - output [7:0]m_axi_s2mm_wstrb; - output m_axi_s2mm_wlast; - output m_axi_s2mm_wvalid; - input m_axi_s2mm_wready; - input [1:0]m_axi_s2mm_bresp; - input m_axi_s2mm_bvalid; - output m_axi_s2mm_bready; - output s2mm_prmry_reset_out_n; - input [31:0]s_axis_s2mm_tdata; - input [3:0]s_axis_s2mm_tkeep; - input [0:0]s_axis_s2mm_tuser; - input s_axis_s2mm_tvalid; - output s_axis_s2mm_tready; - input s_axis_s2mm_tlast; - output mm2s_introut; - output s2mm_introut; - output [63:0]axi_vdma_tstvec; + input [0:0]SR; + input s_axi_lite_aclk; + input prmry_reset2; + input m_axi_mm2s_aclk; + input prmry_reset2_0; + input m_axi_s2mm_aclk; + input p_78_out; + input s2mm_ip2axi_introut; + input [4:0]Q; + input [4:0]\ptr_ref_i_reg[4] ; + input [4:0]\MM2S_ERR_FOR_IRQ.frm_store_i_reg[4] ; + input [4:0]\S2MM_ERR_FOR_IRQ.frm_store_i_reg[4] ; + input s_axi_lite_wvalid; + input s_axi_lite_awvalid; + input s_axi_lite_arvalid; + input s_axi_lite_resetn; + input [17:0]p_71_out; + input mm2s_prmry_resetn; + input stop; + input \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_reg ; + input \reg_module_hsize_reg[0] ; + input [28:0]\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] ; + input \reg_module_hsize_reg[3] ; + input [28:0]\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] ; + input \reg_module_hsize_reg[4] ; + input \reg_module_hsize_reg[5] ; + input \reg_module_hsize_reg[6] ; + input \reg_module_hsize_reg[7] ; + input \reg_module_hsize_reg[8] ; + input \reg_module_hsize_reg[9] ; + input \reg_module_hsize_reg[10] ; + input \reg_module_hsize_reg[11] ; + input \reg_module_hsize_reg[12] ; + input [18:0]\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] ; + input [2:0]\reg_module_hsize_reg[15] ; + input [2:0]\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ; + input p_70_out; + input dma_interr_reg_0; + input [4:0]\M_GEN_DMACR_REGISTER.dmacr_i_reg[14] ; + input dma_slverr_reg; + input dma_decerr_reg; + input ioc_irq_reg_1; + input dly_irq_reg_1; + input err_irq_reg; + input [7:0]\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] ; + input [7:0]ch1_irqdelay_status; + input [22:0]s2mm_dmacr; + input \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31]_0 ; + input \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[23] ; + input s2mm_prmry_resetn; + input [0:0]s2mm_dmasr; + input [3:0]\DMA_IRQ_MASK_GEN.dma_irq_mask_i_reg[3] ; + input [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 ; + input [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 ; + input [12:0]\reg_module_vsize_reg[12] ; + input s2mm_soft_reset; + input [15:0]\reg_module_hsize_reg[15]_0 ; + input [15:0]\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ; + input [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 ; + input [7:0]\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7] ; + input [7:0]ch2_irqdelay_status; + input dma_interr_reg_1; + input dma_slverr_reg_0; + input dma_decerr_reg_0; + input \GEN_FOR_FLUSH.fsize_err_reg_0 ; + input lsize_err_reg_0; + input [6:0]\GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14] ; + input \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg_0 ; + input ioc_irq_reg_2; + input dly_irq_reg_2; + input err_irq_reg_0; + input lsize_more_err_reg_0; + input mm2s_ioc_irq_set; + input ch1_dly_irq_set; + input s2mm_dma_interr_set_minus_frame_errors; + input s2mm_fsize_more_or_sof_late; + input fsize_mismatch_err; + input lsize_mismatch_err; + input s2mm_ioc_irq_set; + input ch2_dly_irq_set; + input lsize_more_mismatch_err; + input s_axi_lite_bready; + input s_axi_lite_rready; + input [5:0]s_axi_lite_araddr; + input [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 ; + input [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 ; + input [31:0]s_axi_lite_wdata; + input [5:0]s_axi_lite_awaddr; + input [4:0]\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4] ; + input [4:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4] ; + input [4:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.genlock_pair_frame_reg[4] ; + + wire [31:0]D; + wire [3:0]\DMA_IRQ_MASK_GEN.dma_irq_mask_i_reg[3] ; + wire [15:0]\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ; + wire [4:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4] ; + wire [4:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.genlock_pair_frame_reg[4] ; + wire [31:0]\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31] ; + wire \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31]_0 ; + wire [0:0]\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] ; + wire [0:0]\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]_0 ; + wire \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[23] ; + wire \GEN_FOR_FLUSH.fsize_err_reg ; + wire \GEN_FOR_FLUSH.fsize_err_reg_0 ; + wire \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg ; + wire \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg_0 ; + wire \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_reg ; + wire [7:0]\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] ; + wire [7:0]\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_0 ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31] ; + wire [31:0]\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31] ; + wire [6:0]\GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14] ; + wire [18:0]\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] ; + wire [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 ; + wire [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 ; + wire [28:0]\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] ; + wire [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 ; + wire [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 ; + wire [28:0]\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] ; + wire [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 ; + wire [4:0]\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4] ; + wire [4:0]\MM2S_ERR_FOR_IRQ.frm_store_i_reg[4] ; + wire [2:0]\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ; + wire [4:0]\M_GEN_DMACR_REGISTER.dmacr_i_reg[14] ; + wire [4:0]Q; + wire [4:0]\S2MM_ERR_FOR_IRQ.frm_store_i_reg[4] ; + wire [0:0]SR; + wire ch1_dly_irq_set; + wire [7:0]ch1_irqdelay_status; + wire ch2_dly_irq_set; + wire [7:0]ch2_irqdelay_status; + wire dly_irq_reg; + wire dly_irq_reg_0; + wire dly_irq_reg_1; + wire dly_irq_reg_2; + wire dma_decerr_reg; + wire dma_decerr_reg_0; + wire dma_interr_reg; + wire dma_interr_reg_0; + wire dma_interr_reg_1; + wire dma_slverr_reg; + wire dma_slverr_reg_0; + wire [0:0]dmacr_i; + wire err_irq_reg; + wire err_irq_reg_0; + wire fsize_mismatch_err; + wire [28:0]in0; + wire ioc_irq_reg; + wire ioc_irq_reg_0; + wire ioc_irq_reg_1; + wire ioc_irq_reg_2; + wire lsize_err_reg; + wire lsize_err_reg_0; + wire lsize_mismatch_err; + wire lsize_more_err_reg; + wire lsize_more_err_reg_0; + wire lsize_more_mismatch_err; + wire m_axi_mm2s_aclk; + wire m_axi_s2mm_aclk; + wire [8:0]mm2s_axi2ip_wrce; + (* async_reg = "true" *) wire [4:0]mm2s_chnl_current_frame_cdc_tig; + (* async_reg = "true" *) wire [4:0]mm2s_genlock_pair_frame_cdc_tig; + wire mm2s_introut; + wire mm2s_ioc_irq_set; + (* async_reg = "true" *) wire [4:0]mm2s_ip2axi_frame_ptr_ref_cdc_tig; + (* async_reg = "true" *) wire [4:0]mm2s_ip2axi_frame_store_cdc_tig; + wire mm2s_prmry_resetn; + wire [1:0]out; + wire p_14_out; + wire p_15_out; + wire p_70_out; + wire [17:0]p_71_out; + wire p_78_out; + wire prmry_reset2; + wire prmry_reset2_0; + wire prmtr_updt_complete_i_reg; + wire prmtr_updt_complete_i_reg_0; + wire [4:0]\ptr_ref_i_reg[4] ; + wire \reg_module_hsize_reg[0] ; + wire \reg_module_hsize_reg[10] ; + wire \reg_module_hsize_reg[11] ; + wire \reg_module_hsize_reg[12] ; + wire [2:0]\reg_module_hsize_reg[15] ; + wire [15:0]\reg_module_hsize_reg[15]_0 ; + wire \reg_module_hsize_reg[3] ; + wire \reg_module_hsize_reg[4] ; + wire \reg_module_hsize_reg[5] ; + wire \reg_module_hsize_reg[6] ; + wire \reg_module_hsize_reg[7] ; + wire \reg_module_hsize_reg[8] ; + wire \reg_module_hsize_reg[9] ; + wire [12:0]\reg_module_vsize_reg[12] ; + wire [9:0]s2mm_axi2ip_wrce; + (* async_reg = "true" *) wire [12:0]s2mm_capture_dm_done_vsize_counter_cdc_tig; + (* async_reg = "true" *) wire [15:0]s2mm_capture_hsize_at_uf_err_cdc_tig; + (* async_reg = "true" *) wire [4:0]s2mm_chnl_current_frame_cdc_tig; + wire s2mm_dma_interr_set_minus_frame_errors; + wire [22:0]s2mm_dmacr; + wire [0:0]s2mm_dmasr; + wire s2mm_fsize_more_or_sof_late; + (* async_reg = "true" *) wire [4:0]s2mm_genlock_pair_frame_cdc_tig; + wire s2mm_introut; + wire s2mm_ioc_irq_set; + (* async_reg = "true" *) wire [4:0]s2mm_ip2axi_frame_ptr_ref_cdc_tig; + (* async_reg = "true" *) wire [4:0]s2mm_ip2axi_frame_store_cdc_tig; + wire s2mm_ip2axi_introut; + wire s2mm_prmry_resetn; + wire s2mm_soft_reset; + wire s_axi_lite_aclk; + wire [5:0]s_axi_lite_araddr; + wire s_axi_lite_arready; + wire s_axi_lite_arvalid; + wire [5:0]s_axi_lite_awaddr; + wire s_axi_lite_awready; + wire s_axi_lite_awvalid; + wire s_axi_lite_bready; + wire s_axi_lite_bvalid; + wire [31:0]s_axi_lite_rdata; + wire s_axi_lite_resetn; + wire s_axi_lite_rready; + wire s_axi_lite_rvalid; + wire [31:0]s_axi_lite_wdata; + wire s_axi_lite_wready; + wire s_axi_lite_wvalid; + wire stop; + + Arty_Z7_20_axi_vdma_0_0_axi_vdma_lite_if \GEN_AXI_LITE_IF.AXI_LITE_IF_I + (.D(D), + .\DMA_IRQ_MASK_GEN.dma_irq_mask_i_reg[3] (\DMA_IRQ_MASK_GEN.dma_irq_mask_i_reg[3] ), + .\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] (\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ), + .\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31] (\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31] ), + .\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31]_0 (\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31]_0 ), + .\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] (\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] ), + .\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]_0 (\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]_0 ), + .\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[23] (\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[23] ), + .\GEN_FOR_FLUSH.fsize_err_reg (\GEN_FOR_FLUSH.fsize_err_reg ), + .\GEN_FOR_FLUSH.fsize_err_reg_0 (\GEN_FOR_FLUSH.fsize_err_reg_0 ), + .\GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg (\GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg ), + .\GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg_0 (\GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg_0 ), + .\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_reg (\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_reg ), + .\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] (\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] ), + .\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7] (\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0 (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]_0 (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_0 (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1 (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_0 ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0 (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0 (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31] ), + .\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] (mm2s_ip2axi_frame_ptr_ref_cdc_tig), + .\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] (mm2s_ip2axi_frame_store_cdc_tig), + .\GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14] (\GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14] ), + .\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] (\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] ), + .\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 (\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0 ), + .\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 (\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1 ), + .\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] (\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] ), + .\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 (\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0 ), + .\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 (\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1 ), + .\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] (\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] ), + .\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 (\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0 ), + .\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4] (s2mm_ip2axi_frame_ptr_ref_cdc_tig), + .\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4] (s2mm_ip2axi_frame_store_cdc_tig), + .\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] (\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ), + .\M_GEN_DMACR_REGISTER.dmacr_i_reg[14] (\M_GEN_DMACR_REGISTER.dmacr_i_reg[14] ), + .SR(SR), + .ch1_dly_irq_set(ch1_dly_irq_set), + .ch1_irqdelay_status(ch1_irqdelay_status), + .ch2_dly_irq_set(ch2_dly_irq_set), + .ch2_irqdelay_status(ch2_irqdelay_status), + .dly_irq_reg(dly_irq_reg), + .dly_irq_reg_0(dly_irq_reg_0), + .dly_irq_reg_1(dly_irq_reg_1), + .dly_irq_reg_2(dly_irq_reg_2), + .dma_decerr_reg(dma_decerr_reg), + .dma_decerr_reg_0(dma_decerr_reg_0), + .dma_interr_reg(dma_interr_reg), + .dma_interr_reg_0(s2mm_axi2ip_wrce[2]), + .dma_interr_reg_1(dma_interr_reg_0), + .dma_interr_reg_2(dma_interr_reg_1), + .dma_slverr_reg(dma_slverr_reg), + .dma_slverr_reg_0(dma_slverr_reg_0), + .dmacr_i(dmacr_i), + .\dmacr_i_reg[1] (s2mm_axi2ip_wrce[1]), + .err_irq_reg(err_irq_reg), + .err_irq_reg_0(err_irq_reg_0), + .fsize_mismatch_err(fsize_mismatch_err), + .in0(in0), + .ioc_irq_reg(ioc_irq_reg), + .ioc_irq_reg_0(ioc_irq_reg_0), + .ioc_irq_reg_1(ioc_irq_reg_1), + .ioc_irq_reg_2(ioc_irq_reg_2), + .lsize_err_reg(lsize_err_reg), + .lsize_err_reg_0(lsize_err_reg_0), + .lsize_mismatch_err(lsize_mismatch_err), + .lsize_more_err_reg(lsize_more_err_reg), + .lsize_more_err_reg_0(lsize_more_err_reg_0), + .lsize_more_mismatch_err(lsize_more_mismatch_err), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .mm2s_axi2ip_wrce(mm2s_axi2ip_wrce), + .mm2s_ioc_irq_set(mm2s_ioc_irq_set), + .mm2s_prmry_resetn(mm2s_prmry_resetn), + .out(out), + .p_14_out(p_14_out), + .p_15_out(p_15_out), + .p_70_out(p_70_out), + .p_71_out(p_71_out), + .prmry_reset2(prmry_reset2), + .prmry_reset2_0(prmry_reset2_0), + .prmtr_updt_complete_i_reg(prmtr_updt_complete_i_reg), + .prmtr_updt_complete_i_reg_0(prmtr_updt_complete_i_reg_0), + .\reg_module_hsize_reg[0] (\reg_module_hsize_reg[0] ), + .\reg_module_hsize_reg[10] (\reg_module_hsize_reg[10] ), + .\reg_module_hsize_reg[11] (\reg_module_hsize_reg[11] ), + .\reg_module_hsize_reg[12] (\reg_module_hsize_reg[12] ), + .\reg_module_hsize_reg[15] (\reg_module_hsize_reg[15] ), + .\reg_module_hsize_reg[15]_0 (\reg_module_hsize_reg[15]_0 ), + .\reg_module_hsize_reg[3] (\reg_module_hsize_reg[3] ), + .\reg_module_hsize_reg[4] (\reg_module_hsize_reg[4] ), + .\reg_module_hsize_reg[5] (\reg_module_hsize_reg[5] ), + .\reg_module_hsize_reg[6] (\reg_module_hsize_reg[6] ), + .\reg_module_hsize_reg[7] (\reg_module_hsize_reg[7] ), + .\reg_module_hsize_reg[8] (\reg_module_hsize_reg[8] ), + .\reg_module_hsize_reg[9] (\reg_module_hsize_reg[9] ), + .\reg_module_vsize_reg[12] (\reg_module_vsize_reg[12] ), + .s2mm_axi2ip_wrce({s2mm_axi2ip_wrce[9:3],s2mm_axi2ip_wrce[0]}), + .s2mm_dma_interr_set_minus_frame_errors(s2mm_dma_interr_set_minus_frame_errors), + .s2mm_dmacr(s2mm_dmacr), + .s2mm_dmasr(s2mm_dmasr), + .s2mm_fsize_more_or_sof_late(s2mm_fsize_more_or_sof_late), + .s2mm_ioc_irq_set(s2mm_ioc_irq_set), + .s2mm_prmry_resetn(s2mm_prmry_resetn), + .s2mm_soft_reset(s2mm_soft_reset), + .s_axi_lite_aclk(s_axi_lite_aclk), + .s_axi_lite_araddr(s_axi_lite_araddr), + .s_axi_lite_arready(s_axi_lite_arready), + .s_axi_lite_arvalid(s_axi_lite_arvalid), + .s_axi_lite_awaddr(s_axi_lite_awaddr), + .s_axi_lite_awready(s_axi_lite_awready), + .s_axi_lite_awvalid(s_axi_lite_awvalid), + .s_axi_lite_bready(s_axi_lite_bready), + .s_axi_lite_bvalid(s_axi_lite_bvalid), + .s_axi_lite_rdata(s_axi_lite_rdata), + .s_axi_lite_resetn(s_axi_lite_resetn), + .s_axi_lite_rready(s_axi_lite_rready), + .s_axi_lite_rvalid(s_axi_lite_rvalid), + .s_axi_lite_wdata(s_axi_lite_wdata), + .s_axi_lite_wready(s_axi_lite_wready), + .s_axi_lite_wvalid(s_axi_lite_wvalid), + .stop(stop)); + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized8 \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.MM2S_INTRPT_CROSSING_I + (.SR(SR), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .mm2s_introut(mm2s_introut), + .p_78_out(p_78_out), + .prmry_reset2(prmry_reset2), + .s_axi_lite_aclk(s_axi_lite_aclk)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[0] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4] [0]), + .Q(mm2s_chnl_current_frame_cdc_tig[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[1] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4] [1]), + .Q(mm2s_chnl_current_frame_cdc_tig[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[2] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4] [2]), + .Q(mm2s_chnl_current_frame_cdc_tig[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[3] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4] [3]), + .Q(mm2s_chnl_current_frame_cdc_tig[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4] [4]), + .Q(mm2s_chnl_current_frame_cdc_tig[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[0] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(mm2s_genlock_pair_frame_cdc_tig[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[1] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(mm2s_genlock_pair_frame_cdc_tig[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[2] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(mm2s_genlock_pair_frame_cdc_tig[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[3] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(mm2s_genlock_pair_frame_cdc_tig[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[4] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(mm2s_genlock_pair_frame_cdc_tig[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[0] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(Q[0]), + .Q(mm2s_ip2axi_frame_ptr_ref_cdc_tig[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[1] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(Q[1]), + .Q(mm2s_ip2axi_frame_ptr_ref_cdc_tig[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[2] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(Q[2]), + .Q(mm2s_ip2axi_frame_ptr_ref_cdc_tig[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[3] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(Q[3]), + .Q(mm2s_ip2axi_frame_ptr_ref_cdc_tig[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(Q[4]), + .Q(mm2s_ip2axi_frame_ptr_ref_cdc_tig[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[0] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\MM2S_ERR_FOR_IRQ.frm_store_i_reg[4] [0]), + .Q(mm2s_ip2axi_frame_store_cdc_tig[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[1] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\MM2S_ERR_FOR_IRQ.frm_store_i_reg[4] [1]), + .Q(mm2s_ip2axi_frame_store_cdc_tig[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[2] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\MM2S_ERR_FOR_IRQ.frm_store_i_reg[4] [2]), + .Q(mm2s_ip2axi_frame_store_cdc_tig[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[3] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\MM2S_ERR_FOR_IRQ.frm_store_i_reg[4] [3]), + .Q(mm2s_ip2axi_frame_store_cdc_tig[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\MM2S_ERR_FOR_IRQ.frm_store_i_reg[4] [4]), + .Q(mm2s_ip2axi_frame_store_cdc_tig[4]), + .R(1'b0)); + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized9 \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.S2MM_INTRPT_CROSSING_I + (.SR(SR), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .prmry_reset2_0(prmry_reset2_0), + .s2mm_introut(s2mm_introut), + .s2mm_ip2axi_introut(s2mm_ip2axi_introut), + .s_axi_lite_aclk(s_axi_lite_aclk)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[0] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(s2mm_capture_dm_done_vsize_counter_cdc_tig[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[10] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(s2mm_capture_dm_done_vsize_counter_cdc_tig[10]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[11] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(s2mm_capture_dm_done_vsize_counter_cdc_tig[11]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[12] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(s2mm_capture_dm_done_vsize_counter_cdc_tig[12]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[1] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(s2mm_capture_dm_done_vsize_counter_cdc_tig[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[2] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(s2mm_capture_dm_done_vsize_counter_cdc_tig[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[3] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(s2mm_capture_dm_done_vsize_counter_cdc_tig[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[4] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(s2mm_capture_dm_done_vsize_counter_cdc_tig[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[5] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(s2mm_capture_dm_done_vsize_counter_cdc_tig[5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[6] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(s2mm_capture_dm_done_vsize_counter_cdc_tig[6]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[7] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(s2mm_capture_dm_done_vsize_counter_cdc_tig[7]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[8] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(s2mm_capture_dm_done_vsize_counter_cdc_tig[8]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[9] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(s2mm_capture_dm_done_vsize_counter_cdc_tig[9]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[0] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(s2mm_capture_hsize_at_uf_err_cdc_tig[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[10] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(s2mm_capture_hsize_at_uf_err_cdc_tig[10]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[11] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(s2mm_capture_hsize_at_uf_err_cdc_tig[11]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[12] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(s2mm_capture_hsize_at_uf_err_cdc_tig[12]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[13] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(s2mm_capture_hsize_at_uf_err_cdc_tig[13]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[14] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(s2mm_capture_hsize_at_uf_err_cdc_tig[14]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[15] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(s2mm_capture_hsize_at_uf_err_cdc_tig[15]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[1] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(s2mm_capture_hsize_at_uf_err_cdc_tig[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[2] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(s2mm_capture_hsize_at_uf_err_cdc_tig[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[3] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(s2mm_capture_hsize_at_uf_err_cdc_tig[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[4] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(s2mm_capture_hsize_at_uf_err_cdc_tig[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[5] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(s2mm_capture_hsize_at_uf_err_cdc_tig[5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[6] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(s2mm_capture_hsize_at_uf_err_cdc_tig[6]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[7] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(s2mm_capture_hsize_at_uf_err_cdc_tig[7]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[8] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(s2mm_capture_hsize_at_uf_err_cdc_tig[8]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[9] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b0), + .Q(s2mm_capture_hsize_at_uf_err_cdc_tig[9]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[0] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4] [0]), + .Q(s2mm_chnl_current_frame_cdc_tig[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[1] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4] [1]), + .Q(s2mm_chnl_current_frame_cdc_tig[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[2] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4] [2]), + .Q(s2mm_chnl_current_frame_cdc_tig[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[3] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4] [3]), + .Q(s2mm_chnl_current_frame_cdc_tig[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[4] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4] [4]), + .Q(s2mm_chnl_current_frame_cdc_tig[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[0] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.genlock_pair_frame_reg[4] [0]), + .Q(s2mm_genlock_pair_frame_cdc_tig[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[1] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.genlock_pair_frame_reg[4] [1]), + .Q(s2mm_genlock_pair_frame_cdc_tig[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[2] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.genlock_pair_frame_reg[4] [2]), + .Q(s2mm_genlock_pair_frame_cdc_tig[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[3] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.genlock_pair_frame_reg[4] [3]), + .Q(s2mm_genlock_pair_frame_cdc_tig[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[4] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.genlock_pair_frame_reg[4] [4]), + .Q(s2mm_genlock_pair_frame_cdc_tig[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[0] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\ptr_ref_i_reg[4] [0]), + .Q(s2mm_ip2axi_frame_ptr_ref_cdc_tig[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[1] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\ptr_ref_i_reg[4] [1]), + .Q(s2mm_ip2axi_frame_ptr_ref_cdc_tig[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[2] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\ptr_ref_i_reg[4] [2]), + .Q(s2mm_ip2axi_frame_ptr_ref_cdc_tig[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[3] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\ptr_ref_i_reg[4] [3]), + .Q(s2mm_ip2axi_frame_ptr_ref_cdc_tig[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\ptr_ref_i_reg[4] [4]), + .Q(s2mm_ip2axi_frame_ptr_ref_cdc_tig[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[0] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\S2MM_ERR_FOR_IRQ.frm_store_i_reg[4] [0]), + .Q(s2mm_ip2axi_frame_store_cdc_tig[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[1] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\S2MM_ERR_FOR_IRQ.frm_store_i_reg[4] [1]), + .Q(s2mm_ip2axi_frame_store_cdc_tig[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[2] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\S2MM_ERR_FOR_IRQ.frm_store_i_reg[4] [2]), + .Q(s2mm_ip2axi_frame_store_cdc_tig[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[3] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\S2MM_ERR_FOR_IRQ.frm_store_i_reg[4] [3]), + .Q(s2mm_ip2axi_frame_store_cdc_tig[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4] + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(\S2MM_ERR_FOR_IRQ.frm_store_i_reg[4] [4]), + .Q(s2mm_ip2axi_frame_store_cdc_tig[4]), + .R(1'b0)); +endmodule - wire \ ; - wire \ ; - wire AXI_LITE_REG_INTERFACE_I_n_40; - wire AXI_LITE_REG_INTERFACE_I_n_48; - wire AXI_LITE_REG_INTERFACE_I_n_49; - wire AXI_LITE_REG_INTERFACE_I_n_50; - wire AXI_LITE_REG_INTERFACE_I_n_51; - wire AXI_LITE_REG_INTERFACE_I_n_52; - wire AXI_LITE_REG_INTERFACE_I_n_53; - wire AXI_LITE_REG_INTERFACE_I_n_54; - wire AXI_LITE_REG_INTERFACE_I_n_55; - wire AXI_LITE_REG_INTERFACE_I_n_56; - wire AXI_LITE_REG_INTERFACE_I_n_57; - wire AXI_LITE_REG_INTERFACE_I_n_58; - wire AXI_LITE_REG_INTERFACE_I_n_59; - wire AXI_LITE_REG_INTERFACE_I_n_60; - wire AXI_LITE_REG_INTERFACE_I_n_61; - wire AXI_LITE_REG_INTERFACE_I_n_62; - wire AXI_LITE_REG_INTERFACE_I_n_63; - wire AXI_LITE_REG_INTERFACE_I_n_64; - wire AXI_LITE_REG_INTERFACE_I_n_65; - wire AXI_LITE_REG_INTERFACE_I_n_66; - wire AXI_LITE_REG_INTERFACE_I_n_67; - wire AXI_LITE_REG_INTERFACE_I_n_68; - wire AXI_LITE_REG_INTERFACE_I_n_69; - wire AXI_LITE_REG_INTERFACE_I_n_70; - wire AXI_LITE_REG_INTERFACE_I_n_71; - wire AXI_LITE_REG_INTERFACE_I_n_72; - wire AXI_LITE_REG_INTERFACE_I_n_73; - wire AXI_LITE_REG_INTERFACE_I_n_74; - wire AXI_LITE_REG_INTERFACE_I_n_75; - wire AXI_LITE_REG_INTERFACE_I_n_76; - wire AXI_LITE_REG_INTERFACE_I_n_77; - wire AXI_LITE_REG_INTERFACE_I_n_78; - wire AXI_LITE_REG_INTERFACE_I_n_79; - wire AXI_LITE_REG_INTERFACE_I_n_80; - wire AXI_LITE_REG_INTERFACE_I_n_81; - wire AXI_LITE_REG_INTERFACE_I_n_82; - wire AXI_LITE_REG_INTERFACE_I_n_83; - wire AXI_LITE_REG_INTERFACE_I_n_84; - wire \GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/p_in_d1_cdc_from ; - wire \GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/prmry_in_xored ; - wire \GEN_CDC_FOR_ASYNC.PRMTR_UPDT_CDC_I/scndry_reset2 ; - wire \GEN_CDC_FOR_ASYNC.SOF_CDC_I/p_in_d1_cdc_from ; - wire \GEN_CDC_FOR_ASYNC.SOF_CDC_I/prmry_in_xored ; - wire \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_rd_empty ; - wire \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/sig_rst2all_stop_request ; - wire \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.MM2S_INTRPT_CROSSING_I/prmry_reset2 ; - wire \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.MM2S_INTRPT_CROSSING_I/scndry_reset2 ; - wire \GEN_RESET_FOR_MM2S.RESET_I/halt_reset ; - wire \GEN_RESET_FOR_MM2S.RESET_I/s_soft_reset_i0 ; - wire \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_34 ; - wire \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_35 ; - wire \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_36 ; - wire \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_37 ; - wire \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_38 ; - wire \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_39 ; - wire \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_8 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_3 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_9 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_157 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_158 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_159 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_160 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_161 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_162 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_163 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_164 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_165 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_166 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_167 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_168 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_169 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_170 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_171 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_172 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_173 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_174 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_175 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_176 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_58 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_59 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_60 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_63 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_64 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_68 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_72 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_76 ; - wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_79 ; - wire I_AXI_DMA_INTRPT_n_21; - wire \I_DMA_REGISTER/different_delay ; - wire \I_DMA_REGISTER/different_thresh ; - wire \I_DMA_REGISTER/reset_counts ; - wire I_PRMRY_DATAMOVER_n_41; - wire I_PRMRY_DATAMOVER_n_42; - wire I_PRMRY_DATAMOVER_n_43; - wire I_PRMRY_DATAMOVER_n_6; - wire I_RST_MODULE_n_13; - wire I_RST_MODULE_n_14; - wire I_RST_MODULE_n_15; - wire I_RST_MODULE_n_16; - wire I_RST_MODULE_n_17; - wire \I_STS_MNGR/datamover_idle ; - wire all_lines_xfred; - wire axi_resetn; +(* ORIG_REF_NAME = "axi_vdma_reg_module" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_module + (p_71_out, + p_77_out, + out, + reset_counts, + p_70_out, + err_d1_reg, + err_d1_reg_0, + err_d1_reg_1, + ioc_irq_reg, + dly_irq_reg, + p_78_out, + p_67_out, + s_soft_reset_i0, + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg , + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6] , + ch1_delay_zero, + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] , + p_13_out, + Q, + E, + err_irq_reg, + \dmacr_i_reg[0] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0] , + \hsize_vid_reg[15] , + \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] , + \vsize_vid_reg[12] , + \stride_vid_reg[15] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] , + \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12] , + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from , + \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4] , + s_axis_cmd_tvalid_reg, + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]_0 , + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg , + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] , + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] , + dmacr_i, + m_axi_mm2s_aclk, + SR, + mm2s_axi2ip_wrce, + D, + \dmacr_i_reg[2] , + in0, + reset_counts_reg, + halted_clr_reg, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] , + slverr_i_reg, + decerr_i_reg, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[2] , + mm2s_halt_cmplt, + halt_reset, + prmry_in, + p_50_out, + ch1_delay_cnt_en, + p_17_out, + ch1_dly_irq_set, + mask_fsync_out_i, + p_47_out, + prmry_resetn_i_reg, + p_24_out, + p_45_out, + mm2s_ioc_irq_set, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_0 , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[4] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_1 , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]_0 , + dma_err, + mm2s_halt, + initial_frame, + stop, + prmtr_update_complete, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18] , + \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0 ); + output [18:0]p_71_out; + output p_77_out; + output [31:0]out; + output reset_counts; + output p_70_out; + output err_d1_reg; + output err_d1_reg_0; + output err_d1_reg_1; + output ioc_irq_reg; + output dly_irq_reg; + output p_78_out; + output p_67_out; + output s_soft_reset_i0; + output \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg ; + output \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6] ; + output ch1_delay_zero; + output \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] ; + output p_13_out; + output [4:0]Q; + output [0:0]E; + output err_irq_reg; + output \dmacr_i_reg[0] ; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0] ; + output [15:0]\hsize_vid_reg[15] ; + output [31:0]\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] ; + output [12:0]\vsize_vid_reg[12] ; + output [15:0]\stride_vid_reg[15] ; + output [31:0]\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] ; + output [31:0]\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] ; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3] ; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4] ; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5] ; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6] ; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7] ; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8] ; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9] ; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10] ; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11] ; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12] ; + output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ; + output [0:0]\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4] ; + output [0:0]s_axis_cmd_tvalid_reg; + output [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]_0 ; + output \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg ; + output [4:0]\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] ; + output [4:0]\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] ; + input [0:0]dmacr_i; + input m_axi_mm2s_aclk; + input [0:0]SR; + input [8:0]mm2s_axi2ip_wrce; + input [31:0]D; + input \dmacr_i_reg[2] ; + input [28:0]in0; + input reset_counts_reg; + input halted_clr_reg; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] ; + input slverr_i_reg; + input decerr_i_reg; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12] ; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13] ; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[2] ; + input mm2s_halt_cmplt; + input halt_reset; + input prmry_in; + input p_50_out; + input ch1_delay_cnt_en; + input p_17_out; + input ch1_dly_irq_set; + input mask_fsync_out_i; + input p_47_out; + input prmry_resetn_i_reg; + input p_24_out; + input p_45_out; + input mm2s_ioc_irq_set; + input [1:0]\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] ; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7] ; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_0 ; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[4] ; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_1 ; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]_0 ; + input dma_err; + input mm2s_halt; + input initial_frame; + input stop; + input prmtr_update_complete; + input [0:0]\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18] ; + input [4:0]\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0 ; + + wire [31:0]D; + wire [0:0]E; + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ; + wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6] ; + wire [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]_0 ; + wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg ; + wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] ; + wire [1:0]\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]_0 ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[4] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_0 ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_1 ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[2] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13] ; + wire [0:0]\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9] ; + wire [4:0]\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] ; + wire [4:0]\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] ; + wire \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg ; + wire \GEN_REG_DIRECT_MODE.REGDIRECT_I_n_79 ; + wire \GEN_REG_DIRECT_MODE.REGDIRECT_I_n_80 ; + wire \GEN_REG_DIRECT_MODE.REGDIRECT_I_n_81 ; + wire [31:0]\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] ; + wire [31:0]\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] ; + wire [31:0]\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] ; + wire I_DMA_REGISTER_n_20; + wire [0:0]\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4] ; + wire [4:0]\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0 ; + wire [4:0]Q; + wire [0:0]SR; wire ch1_delay_cnt_en; - wire ch1_delay_zero__6; - wire ch1_disable_delay2_out; - wire ch1_ioc_irq_set_i__0; - wire cmnd_wr; - wire [31:0]dm2linebuf_mm2s_tdata; - wire dm2linebuf_mm2s_tlast; - wire dm2linebuf_mm2s_tvalid; + wire ch1_delay_zero; + wire ch1_dly_irq_set; + wire decerr_i_reg; + wire dly_irq_reg; wire dma_err; - wire fifo_full_i; - wire fifo_wren__0; + wire [0:0]dmacr_i; + wire \dmacr_i_reg[0] ; + wire \dmacr_i_reg[2] ; + wire err_d1_reg; + wire err_d1_reg_0; + wire err_d1_reg_1; + wire err_irq_reg; + wire halt_reset; + wire halted_clr_reg; + wire [15:0]\hsize_vid_reg[15] ; + wire [28:0]in0; wire initial_frame; + wire ioc_irq_reg; wire m_axi_mm2s_aclk; - wire [31:0]m_axi_mm2s_araddr; - wire [0:0]\^m_axi_mm2s_arburst ; - wire [3:0]\^m_axi_mm2s_arlen ; - wire m_axi_mm2s_arready; - wire [1:0]\^m_axi_mm2s_arsize ; - wire m_axi_mm2s_arvalid; - wire [63:0]m_axi_mm2s_rdata; - wire m_axi_mm2s_rlast; - wire m_axi_mm2s_rready; - wire [1:0]m_axi_mm2s_rresp; - wire m_axi_mm2s_rvalid; - wire m_axis_mm2s_aclk; - wire [31:0]m_axis_mm2s_tdata; - wire m_axis_mm2s_tlast; - wire m_axis_mm2s_tready; - wire [0:0]m_axis_mm2s_tuser; - wire m_axis_mm2s_tvalid; - wire mask_fsync_out_i; - wire [3:2]mm2s_axi2ip_rdaddr; - wire [23:0]mm2s_axi2ip_wrce; - wire [31:0]mm2s_axi2ip_wrdata; - wire mm2s_axis_resetn; - wire mm2s_dly_irq_set; - wire mm2s_dm_prmry_resetn; - wire [5:0]mm2s_frame_ptr_in; - wire [5:0]mm2s_frame_ptr_out; + wire mask_fsync_out_i; + wire [8:0]mm2s_axi2ip_wrce; wire mm2s_halt; wire mm2s_halt_cmplt; - wire mm2s_introut; wire mm2s_ioc_irq_set; - wire [7:0]mm2s_irqdelay_status; - wire [7:0]mm2s_irqthresh_status; - wire mm2s_prmry_resetn; - wire [15:0]mm2s_reg_module_hsize; - wire [15:0]mm2s_reg_module_stride; - wire [31:0]\mm2s_reg_module_strt_addr[0] ; - wire [12:0]mm2s_reg_module_vsize; - wire p_0_in; - wire p_0_out; - wire p_10_out; - wire p_15_out; + wire [31:0]out; + wire p_13_out; wire p_17_out; - wire p_1_out; - wire p_23_out; - wire [0:0]p_2_in; - wire p_2_out; - wire [4:0]p_30_out; - wire [4:0]p_32_out; - wire p_35_out; - wire p_36_out; - wire p_37_out; - wire [0:0]p_43_out; - wire p_44_out; + wire p_24_out; wire p_45_out; - wire p_46_out; - wire [12:0]p_48_out; - wire p_49_out; - wire p_4_out; - wire p_55_out; - wire [63:0]p_56_out; - wire p_57_out; - wire p_64_out; + wire p_47_out; + wire p_50_out; wire p_67_out; - wire [31:0]p_68_out; - wire p_6_out__1; - wire p_75_out; - wire [4:0]p_76_out; - wire [4:0]p_77_out; - wire [31:0]p_78_out; - wire p_7_out; - wire p_8_out; + wire p_70_out; + wire [18:0]p_71_out; + wire p_77_out; + wire p_78_out; + wire prmry_in; + wire prmry_resetn_i_reg; wire prmtr_update_complete; - wire s_axi_lite_aclk; - wire [8:0]s_axi_lite_araddr; - wire s_axi_lite_arready; - wire s_axi_lite_arvalid; - wire [8:0]s_axi_lite_awaddr; - wire s_axi_lite_awready; - wire s_axi_lite_awvalid; - wire s_axi_lite_bready; - wire s_axi_lite_bvalid; - wire [31:0]s_axi_lite_rdata; - wire s_axi_lite_resetn; - wire s_axi_lite_rready; - wire s_axi_lite_rvalid; - wire [31:0]s_axi_lite_wdata; - wire s_axi_lite_wready; - wire s_axi_lite_wvalid; - wire s_valid0; - wire sof_flag; - wire stop_i; + wire reset_counts; + wire reset_counts_reg; + wire [0:0]s_axis_cmd_tvalid_reg; + wire s_soft_reset_i0; + wire slverr_i_reg; + wire stop; + wire [15:0]\stride_vid_reg[15] ; + wire [12:0]\vsize_vid_reg[12] ; - assign axi_vdma_tstvec[63] = \ ; - assign axi_vdma_tstvec[62] = \ ; - assign axi_vdma_tstvec[61] = \ ; - assign axi_vdma_tstvec[60] = \ ; - assign axi_vdma_tstvec[59] = \ ; - assign axi_vdma_tstvec[58] = \ ; - assign axi_vdma_tstvec[57] = \ ; - assign axi_vdma_tstvec[56] = \ ; - assign axi_vdma_tstvec[55] = \ ; - assign axi_vdma_tstvec[54] = \ ; - assign axi_vdma_tstvec[53] = \ ; - assign axi_vdma_tstvec[52] = \ ; - assign axi_vdma_tstvec[51] = \ ; - assign axi_vdma_tstvec[50] = \ ; - assign axi_vdma_tstvec[49] = \ ; - assign axi_vdma_tstvec[48] = \ ; - assign axi_vdma_tstvec[47] = \ ; - assign axi_vdma_tstvec[46] = \ ; - assign axi_vdma_tstvec[45] = \ ; - assign axi_vdma_tstvec[44] = \ ; - assign axi_vdma_tstvec[43] = \ ; - assign axi_vdma_tstvec[42] = \ ; - assign axi_vdma_tstvec[41] = \ ; - assign axi_vdma_tstvec[40] = \ ; - assign axi_vdma_tstvec[39] = \ ; - assign axi_vdma_tstvec[38] = \ ; - assign axi_vdma_tstvec[37] = \ ; - assign axi_vdma_tstvec[36] = \ ; - assign axi_vdma_tstvec[35] = \ ; - assign axi_vdma_tstvec[34] = \ ; - assign axi_vdma_tstvec[33] = \ ; - assign axi_vdma_tstvec[32] = \ ; - assign axi_vdma_tstvec[31] = \ ; - assign axi_vdma_tstvec[30] = \ ; - assign axi_vdma_tstvec[29] = \ ; - assign axi_vdma_tstvec[28] = \ ; - assign axi_vdma_tstvec[27] = \ ; - assign axi_vdma_tstvec[26] = \ ; - assign axi_vdma_tstvec[25] = \ ; - assign axi_vdma_tstvec[24] = \ ; - assign axi_vdma_tstvec[23] = \ ; - assign axi_vdma_tstvec[22] = \ ; - assign axi_vdma_tstvec[21] = \ ; - assign axi_vdma_tstvec[20] = \ ; - assign axi_vdma_tstvec[19] = \ ; - assign axi_vdma_tstvec[18] = \ ; - assign axi_vdma_tstvec[17] = \ ; - assign axi_vdma_tstvec[16] = \ ; - assign axi_vdma_tstvec[15] = \ ; - assign axi_vdma_tstvec[14] = \ ; - assign axi_vdma_tstvec[13] = \ ; - assign axi_vdma_tstvec[12] = \ ; - assign axi_vdma_tstvec[11] = \ ; - assign axi_vdma_tstvec[10] = \ ; - assign axi_vdma_tstvec[9] = \ ; - assign axi_vdma_tstvec[8] = \ ; - assign axi_vdma_tstvec[7] = \ ; - assign axi_vdma_tstvec[6] = \ ; - assign axi_vdma_tstvec[5] = \ ; - assign axi_vdma_tstvec[4] = \ ; - assign axi_vdma_tstvec[3] = \ ; - assign axi_vdma_tstvec[2] = \ ; - assign axi_vdma_tstvec[1] = \ ; - assign axi_vdma_tstvec[0] = \ ; - assign m_axi_mm2s_arburst[1] = \ ; - assign m_axi_mm2s_arburst[0] = \^m_axi_mm2s_arburst [0]; - assign m_axi_mm2s_arcache[3] = \ ; - assign m_axi_mm2s_arcache[2] = \ ; - assign m_axi_mm2s_arcache[1] = \ ; - assign m_axi_mm2s_arcache[0] = \ ; - assign m_axi_mm2s_arlen[7] = \ ; - assign m_axi_mm2s_arlen[6] = \ ; - assign m_axi_mm2s_arlen[5] = \ ; - assign m_axi_mm2s_arlen[4] = \ ; - assign m_axi_mm2s_arlen[3:0] = \^m_axi_mm2s_arlen [3:0]; - assign m_axi_mm2s_arprot[2] = \ ; - assign m_axi_mm2s_arprot[1] = \ ; - assign m_axi_mm2s_arprot[0] = \ ; - assign m_axi_mm2s_arsize[2] = \ ; - assign m_axi_mm2s_arsize[1:0] = \^m_axi_mm2s_arsize [1:0]; - assign m_axi_s2mm_awaddr[31] = \ ; - assign m_axi_s2mm_awaddr[30] = \ ; - assign m_axi_s2mm_awaddr[29] = \ ; - assign m_axi_s2mm_awaddr[28] = \ ; - assign m_axi_s2mm_awaddr[27] = \ ; - assign m_axi_s2mm_awaddr[26] = \ ; - assign m_axi_s2mm_awaddr[25] = \ ; - assign m_axi_s2mm_awaddr[24] = \ ; - assign m_axi_s2mm_awaddr[23] = \ ; - assign m_axi_s2mm_awaddr[22] = \ ; - assign m_axi_s2mm_awaddr[21] = \ ; - assign m_axi_s2mm_awaddr[20] = \ ; - assign m_axi_s2mm_awaddr[19] = \ ; - assign m_axi_s2mm_awaddr[18] = \ ; - assign m_axi_s2mm_awaddr[17] = \ ; - assign m_axi_s2mm_awaddr[16] = \ ; - assign m_axi_s2mm_awaddr[15] = \ ; - assign m_axi_s2mm_awaddr[14] = \ ; - assign m_axi_s2mm_awaddr[13] = \ ; - assign m_axi_s2mm_awaddr[12] = \ ; - assign m_axi_s2mm_awaddr[11] = \ ; - assign m_axi_s2mm_awaddr[10] = \ ; - assign m_axi_s2mm_awaddr[9] = \ ; - assign m_axi_s2mm_awaddr[8] = \ ; - assign m_axi_s2mm_awaddr[7] = \ ; - assign m_axi_s2mm_awaddr[6] = \ ; - assign m_axi_s2mm_awaddr[5] = \ ; - assign m_axi_s2mm_awaddr[4] = \ ; - assign m_axi_s2mm_awaddr[3] = \ ; - assign m_axi_s2mm_awaddr[2] = \ ; - assign m_axi_s2mm_awaddr[1] = \ ; - assign m_axi_s2mm_awaddr[0] = \ ; - assign m_axi_s2mm_awburst[1] = \ ; - assign m_axi_s2mm_awburst[0] = \ ; - assign m_axi_s2mm_awcache[3] = \ ; - assign m_axi_s2mm_awcache[2] = \ ; - assign m_axi_s2mm_awcache[1] = \ ; - assign m_axi_s2mm_awcache[0] = \ ; - assign m_axi_s2mm_awlen[7] = \ ; - assign m_axi_s2mm_awlen[6] = \ ; - assign m_axi_s2mm_awlen[5] = \ ; - assign m_axi_s2mm_awlen[4] = \ ; - assign m_axi_s2mm_awlen[3] = \ ; - assign m_axi_s2mm_awlen[2] = \ ; - assign m_axi_s2mm_awlen[1] = \ ; - assign m_axi_s2mm_awlen[0] = \ ; - assign m_axi_s2mm_awprot[2] = \ ; - assign m_axi_s2mm_awprot[1] = \ ; - assign m_axi_s2mm_awprot[0] = \ ; - assign m_axi_s2mm_awsize[2] = \ ; - assign m_axi_s2mm_awsize[1] = \ ; - assign m_axi_s2mm_awsize[0] = \ ; - assign m_axi_s2mm_awvalid = \ ; - assign m_axi_s2mm_bready = \ ; - assign m_axi_s2mm_wdata[63] = \ ; - assign m_axi_s2mm_wdata[62] = \ ; - assign m_axi_s2mm_wdata[61] = \ ; - assign m_axi_s2mm_wdata[60] = \ ; - assign m_axi_s2mm_wdata[59] = \ ; - assign m_axi_s2mm_wdata[58] = \ ; - assign m_axi_s2mm_wdata[57] = \ ; - assign m_axi_s2mm_wdata[56] = \ ; - assign m_axi_s2mm_wdata[55] = \ ; - assign m_axi_s2mm_wdata[54] = \ ; - assign m_axi_s2mm_wdata[53] = \ ; - assign m_axi_s2mm_wdata[52] = \ ; - assign m_axi_s2mm_wdata[51] = \ ; - assign m_axi_s2mm_wdata[50] = \ ; - assign m_axi_s2mm_wdata[49] = \ ; - assign m_axi_s2mm_wdata[48] = \ ; - assign m_axi_s2mm_wdata[47] = \ ; - assign m_axi_s2mm_wdata[46] = \ ; - assign m_axi_s2mm_wdata[45] = \ ; - assign m_axi_s2mm_wdata[44] = \ ; - assign m_axi_s2mm_wdata[43] = \ ; - assign m_axi_s2mm_wdata[42] = \ ; - assign m_axi_s2mm_wdata[41] = \ ; - assign m_axi_s2mm_wdata[40] = \ ; - assign m_axi_s2mm_wdata[39] = \ ; - assign m_axi_s2mm_wdata[38] = \ ; - assign m_axi_s2mm_wdata[37] = \ ; - assign m_axi_s2mm_wdata[36] = \ ; - assign m_axi_s2mm_wdata[35] = \ ; - assign m_axi_s2mm_wdata[34] = \ ; - assign m_axi_s2mm_wdata[33] = \ ; - assign m_axi_s2mm_wdata[32] = \ ; - assign m_axi_s2mm_wdata[31] = \ ; - assign m_axi_s2mm_wdata[30] = \ ; - assign m_axi_s2mm_wdata[29] = \ ; - assign m_axi_s2mm_wdata[28] = \ ; - assign m_axi_s2mm_wdata[27] = \ ; - assign m_axi_s2mm_wdata[26] = \ ; - assign m_axi_s2mm_wdata[25] = \ ; - assign m_axi_s2mm_wdata[24] = \ ; - assign m_axi_s2mm_wdata[23] = \ ; - assign m_axi_s2mm_wdata[22] = \ ; - assign m_axi_s2mm_wdata[21] = \ ; - assign m_axi_s2mm_wdata[20] = \ ; - assign m_axi_s2mm_wdata[19] = \ ; - assign m_axi_s2mm_wdata[18] = \ ; - assign m_axi_s2mm_wdata[17] = \ ; - assign m_axi_s2mm_wdata[16] = \ ; - assign m_axi_s2mm_wdata[15] = \ ; - assign m_axi_s2mm_wdata[14] = \ ; - assign m_axi_s2mm_wdata[13] = \ ; - assign m_axi_s2mm_wdata[12] = \ ; - assign m_axi_s2mm_wdata[11] = \ ; - assign m_axi_s2mm_wdata[10] = \ ; - assign m_axi_s2mm_wdata[9] = \ ; - assign m_axi_s2mm_wdata[8] = \ ; - assign m_axi_s2mm_wdata[7] = \ ; - assign m_axi_s2mm_wdata[6] = \ ; - assign m_axi_s2mm_wdata[5] = \ ; - assign m_axi_s2mm_wdata[4] = \ ; - assign m_axi_s2mm_wdata[3] = \ ; - assign m_axi_s2mm_wdata[2] = \ ; - assign m_axi_s2mm_wdata[1] = \ ; - assign m_axi_s2mm_wdata[0] = \ ; - assign m_axi_s2mm_wlast = \ ; - assign m_axi_s2mm_wstrb[7] = \ ; - assign m_axi_s2mm_wstrb[6] = \ ; - assign m_axi_s2mm_wstrb[5] = \ ; - assign m_axi_s2mm_wstrb[4] = \ ; - assign m_axi_s2mm_wstrb[3] = \ ; - assign m_axi_s2mm_wstrb[2] = \ ; - assign m_axi_s2mm_wstrb[1] = \ ; - assign m_axi_s2mm_wstrb[0] = \ ; - assign m_axi_s2mm_wvalid = \ ; - assign m_axi_sg_araddr[31] = \ ; - assign m_axi_sg_araddr[30] = \ ; - assign m_axi_sg_araddr[29] = \ ; - assign m_axi_sg_araddr[28] = \ ; - assign m_axi_sg_araddr[27] = \ ; - assign m_axi_sg_araddr[26] = \ ; - assign m_axi_sg_araddr[25] = \ ; - assign m_axi_sg_araddr[24] = \ ; - assign m_axi_sg_araddr[23] = \ ; - assign m_axi_sg_araddr[22] = \ ; - assign m_axi_sg_araddr[21] = \ ; - assign m_axi_sg_araddr[20] = \ ; - assign m_axi_sg_araddr[19] = \ ; - assign m_axi_sg_araddr[18] = \ ; - assign m_axi_sg_araddr[17] = \ ; - assign m_axi_sg_araddr[16] = \ ; - assign m_axi_sg_araddr[15] = \ ; - assign m_axi_sg_araddr[14] = \ ; - assign m_axi_sg_araddr[13] = \ ; - assign m_axi_sg_araddr[12] = \ ; - assign m_axi_sg_araddr[11] = \ ; - assign m_axi_sg_araddr[10] = \ ; - assign m_axi_sg_araddr[9] = \ ; - assign m_axi_sg_araddr[8] = \ ; - assign m_axi_sg_araddr[7] = \ ; - assign m_axi_sg_araddr[6] = \ ; - assign m_axi_sg_araddr[5] = \ ; - assign m_axi_sg_araddr[4] = \ ; - assign m_axi_sg_araddr[3] = \ ; - assign m_axi_sg_araddr[2] = \ ; - assign m_axi_sg_araddr[1] = \ ; - assign m_axi_sg_araddr[0] = \ ; - assign m_axi_sg_arburst[1] = \ ; - assign m_axi_sg_arburst[0] = \ ; - assign m_axi_sg_arcache[3] = \ ; - assign m_axi_sg_arcache[2] = \ ; - assign m_axi_sg_arcache[1] = \ ; - assign m_axi_sg_arcache[0] = \ ; - assign m_axi_sg_arlen[7] = \ ; - assign m_axi_sg_arlen[6] = \ ; - assign m_axi_sg_arlen[5] = \ ; - assign m_axi_sg_arlen[4] = \ ; - assign m_axi_sg_arlen[3] = \ ; - assign m_axi_sg_arlen[2] = \ ; - assign m_axi_sg_arlen[1] = \ ; - assign m_axi_sg_arlen[0] = \ ; - assign m_axi_sg_arprot[2] = \ ; - assign m_axi_sg_arprot[1] = \ ; - assign m_axi_sg_arprot[0] = \ ; - assign m_axi_sg_arsize[2] = \ ; - assign m_axi_sg_arsize[1] = \ ; - assign m_axi_sg_arsize[0] = \ ; - assign m_axi_sg_arvalid = \ ; - assign m_axi_sg_rready = \ ; - assign m_axis_mm2s_tkeep[3] = \ ; - assign m_axis_mm2s_tkeep[2] = \ ; - assign m_axis_mm2s_tkeep[1] = \ ; - assign m_axis_mm2s_tkeep[0] = \ ; - assign mm2s_buffer_almost_empty = \ ; - assign mm2s_buffer_empty = \ ; - assign mm2s_fsync_out = \ ; - assign mm2s_prmry_reset_out_n = \ ; - assign mm2s_prmtr_update = \ ; - assign s2mm_buffer_almost_full = \ ; - assign s2mm_buffer_full = \ ; - assign s2mm_frame_ptr_out[5] = \ ; - assign s2mm_frame_ptr_out[4] = \ ; - assign s2mm_frame_ptr_out[3] = \ ; - assign s2mm_frame_ptr_out[2] = \ ; - assign s2mm_frame_ptr_out[1] = \ ; - assign s2mm_frame_ptr_out[0] = \ ; - assign s2mm_fsync_out = \ ; - assign s2mm_introut = \ ; - assign s2mm_prmry_reset_out_n = \ ; - assign s2mm_prmtr_update = \ ; - assign s_axi_lite_bresp[1] = \ ; - assign s_axi_lite_bresp[0] = \ ; - assign s_axi_lite_rresp[1] = \ ; - assign s_axi_lite_rresp[0] = \ ; - assign s_axis_s2mm_tready = \ ; - Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_if AXI_LITE_REG_INTERFACE_I - (.D(mm2s_axi2ip_wrdata), - .\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg (AXI_LITE_REG_INTERFACE_I_n_40), - .\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] (AXI_LITE_REG_INTERFACE_I_n_49), - .\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg (AXI_LITE_REG_INTERFACE_I_n_48), - .\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7] (mm2s_irqdelay_status), - .\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] (mm2s_irqthresh_status), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5] (p_78_out), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[0] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_79 ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[10] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_166 ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[11] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_167 ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[12] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_168 ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[13] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_169 ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[14] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_170 ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[15] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_171 ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[1] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_157 ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[2] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_158 ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] (\mm2s_reg_module_strt_addr[0] [31:16]), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[3] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_159 ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[4] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_160 ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[5] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_161 ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[6] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_162 ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[7] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_163 ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[8] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_164 ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[9] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_165 ), - .\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4] (p_30_out), - .\MM2S_ERR_FOR_IRQ.frm_store_i_reg[4] (p_76_out), - .Q(p_77_out), - .SR(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.MM2S_INTRPT_CROSSING_I/scndry_reset2 ), - .different_delay(\I_DMA_REGISTER/different_delay ), - .different_thresh(\I_DMA_REGISTER/different_thresh ), - .dly_irq_reg(AXI_LITE_REG_INTERFACE_I_n_84), - .dly_irq_reg_0(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_60 ), - .dma_decerr_reg(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_64 ), - .dma_interr_reg(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_58 ), - .dma_slverr_reg(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_63 ), - .err_irq_reg(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_76 ), - .in0({AXI_LITE_REG_INTERFACE_I_n_50,AXI_LITE_REG_INTERFACE_I_n_51,AXI_LITE_REG_INTERFACE_I_n_52,AXI_LITE_REG_INTERFACE_I_n_53,AXI_LITE_REG_INTERFACE_I_n_54,AXI_LITE_REG_INTERFACE_I_n_55,AXI_LITE_REG_INTERFACE_I_n_56,AXI_LITE_REG_INTERFACE_I_n_57,AXI_LITE_REG_INTERFACE_I_n_58,AXI_LITE_REG_INTERFACE_I_n_59,AXI_LITE_REG_INTERFACE_I_n_60,AXI_LITE_REG_INTERFACE_I_n_61,AXI_LITE_REG_INTERFACE_I_n_62,AXI_LITE_REG_INTERFACE_I_n_63,AXI_LITE_REG_INTERFACE_I_n_64,AXI_LITE_REG_INTERFACE_I_n_65,AXI_LITE_REG_INTERFACE_I_n_66,AXI_LITE_REG_INTERFACE_I_n_67,AXI_LITE_REG_INTERFACE_I_n_68,AXI_LITE_REG_INTERFACE_I_n_69,AXI_LITE_REG_INTERFACE_I_n_70,AXI_LITE_REG_INTERFACE_I_n_71,AXI_LITE_REG_INTERFACE_I_n_72,AXI_LITE_REG_INTERFACE_I_n_73,AXI_LITE_REG_INTERFACE_I_n_74,AXI_LITE_REG_INTERFACE_I_n_75,AXI_LITE_REG_INTERFACE_I_n_76,AXI_LITE_REG_INTERFACE_I_n_77,AXI_LITE_REG_INTERFACE_I_n_78,AXI_LITE_REG_INTERFACE_I_n_79,AXI_LITE_REG_INTERFACE_I_n_80,AXI_LITE_REG_INTERFACE_I_n_81}), - .ioc_irq_reg(AXI_LITE_REG_INTERFACE_I_n_83), - .ioc_irq_reg_0(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_59 ), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .mm2s_axi2ip_wrce({mm2s_axi2ip_wrce[23:20],mm2s_axi2ip_wrce[10],mm2s_axi2ip_wrce[1:0]}), - .mm2s_dly_irq_set(mm2s_dly_irq_set), - .mm2s_introut(mm2s_introut), - .mm2s_ioc_irq_set(mm2s_ioc_irq_set), - .out(mm2s_axi2ip_rdaddr), - .p_67_out(p_67_out), - .p_68_out({p_68_out[31:12],p_68_out[6:4],p_68_out[2:0]}), - .p_75_out(p_75_out), - .prmry_reset2(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.MM2S_INTRPT_CROSSING_I/prmry_reset2 ), - .prmry_resetn_i_reg(mm2s_prmry_resetn), - .prmtr_updt_complete_i_reg(AXI_LITE_REG_INTERFACE_I_n_82), - .s_axi_lite_aclk(s_axi_lite_aclk), - .s_axi_lite_araddr(s_axi_lite_araddr[7:2]), - .s_axi_lite_arready(s_axi_lite_arready), - .s_axi_lite_arvalid(s_axi_lite_arvalid), - .s_axi_lite_awaddr(s_axi_lite_awaddr[7:2]), - .s_axi_lite_awready(s_axi_lite_awready), - .s_axi_lite_awvalid(s_axi_lite_awvalid), - .s_axi_lite_bready(s_axi_lite_bready), - .s_axi_lite_bvalid(s_axi_lite_bvalid), - .s_axi_lite_rdata(s_axi_lite_rdata), - .s_axi_lite_resetn(s_axi_lite_resetn), - .s_axi_lite_rready(s_axi_lite_rready), - .s_axi_lite_rvalid(s_axi_lite_rvalid), - .s_axi_lite_wdata(s_axi_lite_wdata), - .s_axi_lite_wready(s_axi_lite_wready), - .s_axi_lite_wvalid(s_axi_lite_wvalid)); - Arty_Z7_20_axi_vdma_0_0_axi_vdma_mngr \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR - (.D(mm2s_axi2ip_wrdata[4]), - .E(I_PRMRY_DATAMOVER_n_6), - .\GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg (\GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_8 ), - .\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg (\GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_34 ), - .\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4] (p_30_out), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] (\mm2s_reg_module_strt_addr[0] ), - .\INFERRED_GEN.cnt_i_reg[1] (\GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_38 ), - .\INFERRED_GEN.cnt_i_reg[2] (I_PRMRY_DATAMOVER_n_43), - .\INFERRED_GEN.cnt_i_reg[2]_0 (I_PRMRY_DATAMOVER_n_42), - .\INFERRED_GEN.cnt_i_reg[2]_1 (I_PRMRY_DATAMOVER_n_41), - .\INFERRED_GEN.cnt_i_reg[2]_2 (\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_rd_empty ), - .\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 (p_32_out), - .\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] (mm2s_reg_module_stride), - .Q(p_48_out), - .SR(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_176 ), - .ch1_delay_cnt_en(ch1_delay_cnt_en), - .ch1_disable_delay2_out(ch1_disable_delay2_out), - .cmnd_wr(cmnd_wr), - .datamover_idle(\I_STS_MNGR/datamover_idle ), - .dma_decerr_reg(\GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_36 ), - .dma_decerr_reg_0(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_64 ), - .dma_err(dma_err), - .dma_interr_reg(\GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_39 ), - .dma_interr_reg_0(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_58 ), - .dma_slverr_reg(\GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_37 ), - .dma_slverr_reg_0(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_63 ), - .\dmacr_i_reg[0] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_174 ), - .halt_i_reg(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_72 ), - .halt_i_reg_0(I_RST_MODULE_n_15), - .halted_reg(\GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_35 ), - .in0(p_43_out), - .initial_frame(initial_frame), + Arty_Z7_20_axi_vdma_0_0_axi_vdma_regdirect \GEN_REG_DIRECT_MODE.REGDIRECT_I + (.D(D), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]_0 (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]_0 ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[4] (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[4] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7] (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_0 (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_0 ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_1 (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_1 ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[2] (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[2] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0] (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10] (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11] (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12] (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3] (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4] (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5] (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6] (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7] (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8] (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9] (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9] ), + .\GEN_NOSYNCEN_BIT.dmacr_i_reg[15] (I_DMA_REGISTER_n_20), + .\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg (\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg ), + .\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] (\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] ), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] (\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] ), + .\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] (\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] ), + .SR(SR), + .\dmacr_i_reg[0] (p_71_out[0]), + .\dmacr_i_reg[2] (p_77_out), + .halted_reg(p_70_out), + .\hsize_vid_reg[15] (\hsize_vid_reg[15] ), + .in0({\GEN_REG_DIRECT_MODE.REGDIRECT_I_n_79 ,\GEN_REG_DIRECT_MODE.REGDIRECT_I_n_80 ,\GEN_REG_DIRECT_MODE.REGDIRECT_I_n_81 }), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .mask_fsync_out_i(mask_fsync_out_i), - .mm2s_axi2ip_wrce(mm2s_axi2ip_wrce[1]), - .mm2s_halt(mm2s_halt), - .out(mm2s_prmry_resetn), - .p_0_in(p_0_in), - .p_0_out(p_0_out), - .p_17_out(p_17_out), - .p_1_out(p_1_out), - .p_23_out(p_23_out), - .p_2_out(p_2_out), - .p_35_out(p_35_out), - .p_36_out(p_36_out), - .p_37_out(p_37_out), - .p_44_out(p_44_out), - .p_45_out(p_45_out), - .p_46_out(p_46_out), - .p_49_out(p_49_out), - .p_55_out(p_55_out), - .p_57_out(p_57_out), - .p_64_out(p_64_out), + .mm2s_axi2ip_wrce(mm2s_axi2ip_wrce[8:3]), + .p_24_out(p_24_out), .p_67_out(p_67_out), - .p_68_out(p_68_out[2:0]), - .prmry_resetn_i_reg(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_172 ), + .p_71_out(p_71_out[1]), + .prmry_resetn_i_reg(prmry_resetn_i_reg), .prmtr_update_complete(prmtr_update_complete), - .prmtr_updt_complete_i_reg(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_175 ), - .\ptr_ref_i_reg[4] (p_77_out), - .\reg_module_hsize_reg[15] (mm2s_reg_module_hsize), - .\reg_module_vsize_reg[12] (mm2s_reg_module_vsize), - .\sig_addr_cntr_lsh_kh_reg[31] ({p_56_out[63:32],p_56_out[23],p_56_out[15:0]}), - .stop_i(stop_i)); - Arty_Z7_20_axi_vdma_0_0_axi_vdma_fsync_gen \GEN_SPRT_FOR_MM2S.MM2S_FSYNC_I - (.\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] (I_AXI_DMA_INTRPT_n_21), - .SR(p_0_in), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .mask_fsync_out_i(mask_fsync_out_i), - .p_23_out(p_23_out), - .p_2_out(p_2_out), - .p_36_out(p_36_out), - .p_45_out(p_45_out), - .p_46_out(p_46_out), - .p_68_out(p_68_out[0]), - .p_in_d1_cdc_from(\GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/p_in_d1_cdc_from ), - .prmry_in_xored(\GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/prmry_in_xored )); - Arty_Z7_20_axi_vdma_0_0_axi_vdma_mm2s_linebuf \GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I - (.DIN(sof_flag), - .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 (p_7_out), - .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 (mm2s_axis_resetn), - .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 (I_RST_MODULE_n_14), - .\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 (\GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_9 ), - .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] (dm2linebuf_mm2s_tlast), - .Q(p_48_out), - .SR(p_0_in), - .all_lines_xfred(all_lines_xfred), - .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), - .fifo_full_i(fifo_full_i), - .fifo_wren__0(fifo_wren__0), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axis_mm2s_aclk(m_axis_mm2s_aclk), - .m_axis_mm2s_tdata(m_axis_mm2s_tdata), - .m_axis_mm2s_tlast(m_axis_mm2s_tlast), - .m_axis_mm2s_tready(m_axis_mm2s_tready), - .m_axis_mm2s_tuser(m_axis_mm2s_tuser), - .mm2s_halt(mm2s_halt), - .out(m_axis_mm2s_tvalid), - .p_0_out(p_0_out), - .p_15_out(p_15_out), - .p_1_out(p_1_out), - .s_valid0(s_valid0), - .scndry_reset2(\GEN_CDC_FOR_ASYNC.PRMTR_UPDT_CDC_I/scndry_reset2 ), - .sig_reset_reg_reg(\GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_3 )); - Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_module \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I - (.D(mm2s_axi2ip_wrdata), - .E(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_173 ), - .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_72 ), - .\GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg (\GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_8 ), - .\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6] (p_4_out), - .\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_68 ), - .\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0] (p_2_in), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] (mm2s_axi2ip_rdaddr), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7] (AXI_LITE_REG_INTERFACE_I_n_40), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7]_0 (AXI_LITE_REG_INTERFACE_I_n_48), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12] (AXI_LITE_REG_INTERFACE_I_n_83), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13] (AXI_LITE_REG_INTERFACE_I_n_84), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] (\GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_39 ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_79 ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_166 ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_167 ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_168 ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[13] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_169 ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[14] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_170 ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_171 ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[1] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_157 ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[2] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_158 ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_159 ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_160 ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_161 ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_162 ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_163 ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_164 ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_165 ), - .\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] (p_77_out), - .\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] (p_76_out), - .\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_175 ), - .\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] (\mm2s_reg_module_strt_addr[0] ), - .\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_172 ), - .\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0 (p_32_out), - .Q(mm2s_irqthresh_status[0]), - .SR(p_0_in), + .stop(stop), + .\stride_vid_reg[15] (\stride_vid_reg[15] ), + .\vsize_vid_reg[12] (\vsize_vid_reg[12] )); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_register I_DMA_REGISTER + (.D({D[31:12],D[6:4],D[1]}), + .E(E), + .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ), + .\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6] (reset_counts), + .\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]_0 (\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6] ), + .\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]_1 (\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]_0 ), + .\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg (\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg ), + .\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] (\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12] (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13] (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18] (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15] (I_DMA_REGISTER_n_20), + .\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] (\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] ), + .\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4] (\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4] ), + .\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0 (\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0 ), + .Q(Q), + .SR(SR), .ch1_delay_cnt_en(ch1_delay_cnt_en), - .ch1_delay_zero__6(ch1_delay_zero__6), - .ch1_disable_delay2_out(ch1_disable_delay2_out), - .ch1_ioc_irq_set_i__0(ch1_ioc_irq_set_i__0), - .datamover_idle(\I_STS_MNGR/datamover_idle ), - .datamover_idle_reg(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_174 ), - .decerr_i_reg(\GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_36 ), - .different_delay(\I_DMA_REGISTER/different_delay ), - .different_thresh(\I_DMA_REGISTER/different_thresh ), - .dly_irq_reg(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_60 ), + .ch1_delay_zero(ch1_delay_zero), + .ch1_dly_irq_set(ch1_dly_irq_set), + .decerr_i_reg(decerr_i_reg), + .dly_irq_reg_0(dly_irq_reg), .dma_err(dma_err), - .\dmacr_i_reg[2] (I_RST_MODULE_n_13), - .err_d1_reg(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_58 ), - .err_d1_reg_0(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_63 ), - .err_d1_reg_1(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_64 ), - .err_irq_reg(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_76 ), - .halt_reset(\GEN_RESET_FOR_MM2S.RESET_I/halt_reset ), - .halted_clr_reg(\GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_35 ), - .\hsize_vid_reg[15] (mm2s_reg_module_hsize), - .in0({AXI_LITE_REG_INTERFACE_I_n_50,AXI_LITE_REG_INTERFACE_I_n_51,AXI_LITE_REG_INTERFACE_I_n_52,AXI_LITE_REG_INTERFACE_I_n_53,AXI_LITE_REG_INTERFACE_I_n_54,AXI_LITE_REG_INTERFACE_I_n_55,AXI_LITE_REG_INTERFACE_I_n_56,AXI_LITE_REG_INTERFACE_I_n_57,AXI_LITE_REG_INTERFACE_I_n_58,AXI_LITE_REG_INTERFACE_I_n_59,AXI_LITE_REG_INTERFACE_I_n_60,AXI_LITE_REG_INTERFACE_I_n_61,AXI_LITE_REG_INTERFACE_I_n_62,AXI_LITE_REG_INTERFACE_I_n_63,AXI_LITE_REG_INTERFACE_I_n_64,AXI_LITE_REG_INTERFACE_I_n_65,AXI_LITE_REG_INTERFACE_I_n_66,AXI_LITE_REG_INTERFACE_I_n_67,AXI_LITE_REG_INTERFACE_I_n_68,AXI_LITE_REG_INTERFACE_I_n_69,AXI_LITE_REG_INTERFACE_I_n_70,AXI_LITE_REG_INTERFACE_I_n_71,AXI_LITE_REG_INTERFACE_I_n_72,AXI_LITE_REG_INTERFACE_I_n_73,AXI_LITE_REG_INTERFACE_I_n_74,AXI_LITE_REG_INTERFACE_I_n_75,AXI_LITE_REG_INTERFACE_I_n_76,AXI_LITE_REG_INTERFACE_I_n_77,AXI_LITE_REG_INTERFACE_I_n_78,AXI_LITE_REG_INTERFACE_I_n_79,AXI_LITE_REG_INTERFACE_I_n_80,AXI_LITE_REG_INTERFACE_I_n_81}), + .dmacr_i(dmacr_i), + .\dmacr_i_reg[0]_0 (\dmacr_i_reg[0] ), + .\dmacr_i_reg[2]_0 (\dmacr_i_reg[2] ), + .err_d1_reg_0(err_d1_reg), + .err_d1_reg_1(err_d1_reg_0), + .err_d1_reg_2(err_d1_reg_1), + .err_irq_reg_0(err_irq_reg), + .halt_reset(halt_reset), + .halted_clr_reg(halted_clr_reg), .initial_frame(initial_frame), - .ioc_irq_reg(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_59 ), + .ioc_irq_reg_0(ioc_irq_reg), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), .mask_fsync_out_i(mask_fsync_out_i), - .mm2s_axi2ip_wrce({mm2s_axi2ip_wrce[23:20],mm2s_axi2ip_wrce[10],mm2s_axi2ip_wrce[1:0]}), - .mm2s_dly_irq_set(mm2s_dly_irq_set), + .mm2s_axi2ip_wrce(mm2s_axi2ip_wrce[1:0]), .mm2s_halt(mm2s_halt), .mm2s_halt_cmplt(mm2s_halt_cmplt), .mm2s_ioc_irq_set(mm2s_ioc_irq_set), - .out(p_78_out), - .p_0_out(p_0_out), - .p_10_out(p_10_out), - .p_17_out(p_17_out), - .p_23_out(p_23_out), - .p_35_out(p_35_out), - .p_44_out(p_44_out), - .p_46_out(p_46_out), - .p_49_out(p_49_out), - .p_64_out(p_64_out), - .p_67_out(p_67_out), - .p_68_out({p_68_out[31:12],p_68_out[6:4],p_68_out[2:0]}), - .p_6_out__1(p_6_out__1), - .p_75_out(p_75_out), - .prmry_in(p_37_out), - .prmry_resetn_i_reg(AXI_LITE_REG_INTERFACE_I_n_82), - .prmry_resetn_i_reg_0(mm2s_prmry_resetn), - .prmry_resetn_i_reg_1(AXI_LITE_REG_INTERFACE_I_n_49), - .prmtr_update_complete(prmtr_update_complete), - .reset_counts(\I_DMA_REGISTER/reset_counts ), - .reset_counts_reg(I_RST_MODULE_n_16), - .\s_axis_cmd_tdata_reg[63] (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_176 ), - .s_soft_reset_i0(\GEN_RESET_FOR_MM2S.RESET_I/s_soft_reset_i0 ), - .slverr_i_reg(\GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_37 ), - .stop_i(stop_i), - .\stride_vid_reg[15] (mm2s_reg_module_stride), - .\vsize_vid_reg[12] (mm2s_reg_module_vsize)); - Arty_Z7_20_axi_vdma_0_0_axi_vdma_sof_gen \GEN_SPRT_FOR_MM2S.MM2S_SOF_I - (.m_axis_mm2s_aclk(m_axis_mm2s_aclk), - .out(mm2s_axis_resetn), - .p_15_out(p_15_out), - .p_in_d1_cdc_from(\GEN_CDC_FOR_ASYNC.SOF_CDC_I/p_in_d1_cdc_from ), - .prmry_in_xored(\GEN_CDC_FOR_ASYNC.SOF_CDC_I/prmry_in_xored ), - .s_valid0(s_valid0), - .scndry_reset2(\GEN_CDC_FOR_ASYNC.PRMTR_UPDT_CDC_I/scndry_reset2 )); - Arty_Z7_20_axi_vdma_0_0_axi_vdma_vid_cdc \GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I - (.\GEN_LINEBUF_NO_SOF.vsize_counter_reg[4] (\GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_9 ), - .SR(\GEN_CDC_FOR_ASYNC.PRMTR_UPDT_CDC_I/scndry_reset2 ), - .all_lines_xfred(all_lines_xfred), - .in0(p_43_out), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axis_mm2s_aclk(m_axis_mm2s_aclk), - .mm2s_frame_ptr_in(mm2s_frame_ptr_in), - .mm2s_frame_ptr_out(mm2s_frame_ptr_out), - .p_15_out(p_15_out), + .p_13_out(p_13_out), .p_17_out(p_17_out), - .p_in_d1_cdc_from(\GEN_CDC_FOR_ASYNC.SOF_CDC_I/p_in_d1_cdc_from ), - .p_in_d1_cdc_from_0(\GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/p_in_d1_cdc_from ), - .prmry_in_xored(\GEN_CDC_FOR_ASYNC.SOF_CDC_I/prmry_in_xored ), - .prmry_in_xored_1(\GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/prmry_in_xored ), - .prmry_resetn_i_reg(p_0_in)); - GND GND - (.G(\ )); - Arty_Z7_20_axi_vdma_0_0_axi_vdma_intrpt I_AXI_DMA_INTRPT - (.D(p_2_in), - .E(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_173 ), - .\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out (\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_68 ), - .\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg (mm2s_irqthresh_status), - .\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg_0 (I_AXI_DMA_INTRPT_n_21), - .\MASTER_MODE_FRAME_CNT.tstvect_fsync_reg (\GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_34 ), - .Q(mm2s_irqdelay_status), - .SR(p_4_out), - .ch1_delay_cnt_en(ch1_delay_cnt_en), - .ch1_delay_zero__6(ch1_delay_zero__6), - .ch1_ioc_irq_set_i__0(ch1_ioc_irq_set_i__0), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .p_24_out(p_24_out), + .p_45_out(p_45_out), + .p_47_out(p_47_out), + .p_50_out(p_50_out), + .p_71_out(p_71_out), + .p_78_out(p_78_out), + .prmry_in(prmry_in), + .prmry_resetn_i_reg(prmry_resetn_i_reg), + .reset_counts_reg_0(reset_counts_reg), + .s_axis_cmd_tvalid_reg(p_70_out), + .s_axis_cmd_tvalid_reg_0(s_axis_cmd_tvalid_reg), + .s_soft_reset_i0(s_soft_reset_i0), + .slverr_i_reg(slverr_i_reg), + .soft_reset_d1_reg(p_77_out)); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_mux LITE_READ_MUX_I + (.in0({in0[28:13],\GEN_REG_DIRECT_MODE.REGDIRECT_I_n_79 ,in0[12:1],\GEN_REG_DIRECT_MODE.REGDIRECT_I_n_80 ,\GEN_REG_DIRECT_MODE.REGDIRECT_I_n_81 ,in0[0]}), + .out(out)); + FDRE #( + .INIT(1'b0)) + \ptr_ref_i_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[2]), + .D(D[0]), + .Q(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] [0]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \ptr_ref_i_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[2]), + .D(D[1]), + .Q(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] [1]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \ptr_ref_i_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[2]), + .D(D[2]), + .Q(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] [2]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \ptr_ref_i_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[2]), + .D(D[3]), + .Q(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] [3]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \ptr_ref_i_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[2]), + .D(D[4]), + .Q(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] [4]), + .R(SR)); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_reg_module" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_module__parameterized0 + (s2mm_dmacr, + s2mm_soft_reset, + out, + reset_counts, + irqdelay_wren_i, + s2mm_dmasr, + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0] , + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_0 , + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_1 , + \GEN_FOR_FLUSH.fsize_err_reg , + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_2 , + err_d1_reg, + ioc_irq_reg, + dly_irq_reg, + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_3 , + err_d1_reg_0, + s2mm_ip2axi_introut, + s_soft_reset_i0, + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6] , + ch2_delay_zero, + p_6_out, + Q, + \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg , + \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg , + err_d1_reg_1, + err_irq_reg, + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] , + s_axis_cmd_tvalid_reg, + prmry_in_xored, + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6]_0 , + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg , + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4] , + \vsize_vid_reg[12] , + \hsize_vid_reg[15] , + \stride_vid_reg[15] , + \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] , + \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] , + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4] , + m_axi_s2mm_aclk, + SR, + s2mm_axi2ip_wrce, + D, + \dmacr_i_reg[2] , + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] , + reset_counts_reg, + p_15_out, + p_14_out, + halted_clr_reg, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4] , + slverr_i_reg, + decerr_i_reg, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[7] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[8] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[11] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[12] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[13] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[15] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4]_0 , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[2] , + s2mm_halt_cmplt, + halt_reset, + prmry_in, + prmry_resetn_i_reg, + ch2_dly_irq_set, + s2mm_tstvect_fsync, + s2mm_valid_frame_sync, + s2mm_ioc_irq_set, + s2mm_valid_video_prmtrs, + mask_fsync_out_i, + s2mm_stop, + num_fstore_minus1, + initial_frame, + p_in_d1_cdc_from, + ch2_delay_cnt_en, + s2mm_cdc2dmac_fsync, + s2mm_packet_sof, + prmtr_update_complete, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18] , + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]_0 ); + output [22:0]s2mm_dmacr; + output s2mm_soft_reset; + output [31:0]out; + output reset_counts; + output irqdelay_wren_i; + output [0:0]s2mm_dmasr; + output \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0] ; + output \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_0 ; + output \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_1 ; + output \GEN_FOR_FLUSH.fsize_err_reg ; + output \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_2 ; + output err_d1_reg; + output ioc_irq_reg; + output dly_irq_reg; + output \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_3 ; + output err_d1_reg_0; + output s2mm_ip2axi_introut; + output s_soft_reset_i0; + output \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6] ; + output ch2_delay_zero; + output p_6_out; + output [6:0]Q; + output \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg ; + output \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg ; + output [3:0]err_d1_reg_1; + output err_irq_reg; + output [0:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] ; + output [0:0]s_axis_cmd_tvalid_reg; + output prmry_in_xored; + output [0:0]\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6]_0 ; + output \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg ; + output [4:0]\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4] ; + output [12:0]\vsize_vid_reg[12] ; + output [15:0]\hsize_vid_reg[15] ; + output [15:0]\stride_vid_reg[15] ; + output [31:0]\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] ; + output [31:0]\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] ; + output [31:0]\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] ; + output [4:0]\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4] ; + input m_axi_s2mm_aclk; + input [0:0]SR; + input [9:0]s2mm_axi2ip_wrce; + input [31:0]D; + input \dmacr_i_reg[2] ; + input [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] ; + input reset_counts_reg; + input p_15_out; + input p_14_out; + input halted_clr_reg; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4] ; + input slverr_i_reg; + input decerr_i_reg; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[7] ; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[8] ; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[11] ; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[12] ; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[13] ; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[15] ; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4]_0 ; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[2] ; + input s2mm_halt_cmplt; + input halt_reset; + input prmry_in; + input prmry_resetn_i_reg; + input ch2_dly_irq_set; + input s2mm_tstvect_fsync; + input s2mm_valid_frame_sync; + input s2mm_ioc_irq_set; + input s2mm_valid_video_prmtrs; + input mask_fsync_out_i; + input s2mm_stop; + input [0:0]num_fstore_minus1; + input initial_frame; + input p_in_d1_cdc_from; + input ch2_delay_cnt_en; + input s2mm_cdc2dmac_fsync; + input s2mm_packet_sof; + input prmtr_update_complete; + input [0:0]\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18] ; + input [4:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]_0 ; + + wire [31:0]D; + wire [0:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] ; + wire [4:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]_0 ; + wire \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg ; + wire \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg ; + wire \GEN_FOR_FLUSH.fsize_err_reg ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6] ; + wire [0:0]\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6]_0 ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[2] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[11] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[12] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[13] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[15] ; + wire [0:0]\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4]_0 ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[7] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[8] ; + wire [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] ; + wire \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg ; + wire [4:0]\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4] ; + wire [4:0]\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4] ; + wire [31:0]\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] ; + wire [31:0]\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] ; + wire [31:0]\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] ; + wire [6:0]Q; + wire \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0] ; + wire \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_0 ; + wire \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_1 ; + wire \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_2 ; + wire \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_3 ; + wire [0:0]SR; + wire ch2_delay_cnt_en; + wire ch2_delay_zero; + wire ch2_dly_irq_set; + wire decerr_i_reg; + wire dly_irq_reg; + wire \dmacr_i_reg[2] ; + wire err_d1_reg; + wire err_d1_reg_0; + wire [3:0]err_d1_reg_1; + wire err_irq_reg; + wire halt_reset; + wire halted_clr_reg; + wire [15:0]\hsize_vid_reg[15] ; + wire initial_frame; + wire ioc_irq_reg; + wire irqdelay_wren_i; + wire m_axi_s2mm_aclk; + wire mask_fsync_out_i; + wire [0:0]num_fstore_minus1; + wire [31:0]out; + wire p_14_out; + wire p_15_out; + wire p_6_out; + wire p_in_d1_cdc_from; + wire prmry_in; + wire prmry_in_xored; + wire prmry_resetn_i_reg; + wire prmtr_update_complete; + wire reset_counts; + wire reset_counts_reg; + wire [9:0]s2mm_axi2ip_wrce; + wire s2mm_cdc2dmac_fsync; + wire [22:0]s2mm_dmacr; + wire [0:0]s2mm_dmasr; + wire s2mm_halt_cmplt; + wire s2mm_ioc_irq_set; + wire s2mm_ip2axi_introut; + wire s2mm_packet_sof; + wire s2mm_soft_reset; + wire s2mm_stop; + wire s2mm_tstvect_fsync; + wire s2mm_valid_frame_sync; + wire s2mm_valid_video_prmtrs; + wire [0:0]s_axis_cmd_tvalid_reg; + wire s_soft_reset_i0; + wire slverr_i_reg; + wire [15:0]\stride_vid_reg[15] ; + wire [12:0]\vsize_vid_reg[12] ; + + Arty_Z7_20_axi_vdma_0_0_axi_vdma_regdirect__parameterized0 \GEN_REG_DIRECT_MODE.REGDIRECT_I + (.D(D), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[2] (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[2] ), + .\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg (\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg ), + .\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] (\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] ), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] (\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] ), + .\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] (\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] ), + .SR(SR), + .halted_reg(s2mm_dmasr), + .\hsize_vid_reg[15] (\hsize_vid_reg[15] ), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .p_in_d1_cdc_from(p_in_d1_cdc_from), + .prmry_in_xored(prmry_in_xored), + .prmry_resetn_i_reg(prmry_resetn_i_reg), + .prmtr_update_complete(prmtr_update_complete), + .s2mm_axi2ip_wrce(s2mm_axi2ip_wrce[9:4]), + .s2mm_cdc2dmac_fsync(s2mm_cdc2dmac_fsync), + .\stride_vid_reg[15] (\stride_vid_reg[15] ), + .\vsize_vid_reg[12] (\vsize_vid_reg[12] )); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_register__parameterized0 I_DMA_REGISTER + (.D({D[31:8],D[6:0]}), + .\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] (\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] ), + .\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]_0 (\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]_0 ), + .\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg_0 (\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg ), + .\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg_0 (\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg ), + .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from (s2mm_dmasr), + .\GEN_FOR_FLUSH.fsize_err_reg_0 (\GEN_FOR_FLUSH.fsize_err_reg ), + .\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6] (\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6] ), + .\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6]_0 (\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6]_0 ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[11] (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[11] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[12] (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[12] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[13] (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[13] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[15] (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[15] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18] (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4] (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4]_0 (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4]_0 ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[7] (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[7] ), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[8] (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[8] ), + .\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4] (\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4] ), + .Q(Q), + .\S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_0 (\S2MM_ERR_FOR_IRQ.frm_store_i_reg[0] ), + .\S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_1 (\S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_0 ), + .\S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_2 (\S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_1 ), + .\S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_3 (\S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_2 ), + .\S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_4 (\S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_3 ), + .SR(SR), + .ch2_delay_cnt_en(ch2_delay_cnt_en), + .ch2_delay_zero(ch2_delay_zero), + .ch2_dly_irq_set(ch2_dly_irq_set), + .decerr_i_reg(decerr_i_reg), + .dly_irq_reg_0(dly_irq_reg), + .\dmacr_i_reg[2]_0 (\dmacr_i_reg[2] ), + .err_d1_reg_0(err_d1_reg), + .err_d1_reg_1(err_d1_reg_0), + .err_d1_reg_2(err_d1_reg_1), + .err_irq_reg_0(err_irq_reg), + .halt_reset(halt_reset), + .halted_clr_reg(halted_clr_reg), + .initial_frame(initial_frame), + .ioc_irq_reg_0(ioc_irq_reg), + .irqdelay_wren_i(irqdelay_wren_i), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), .mask_fsync_out_i(mask_fsync_out_i), - .mm2s_dly_irq_set(mm2s_dly_irq_set), - .mm2s_ioc_irq_set(mm2s_ioc_irq_set), - .out(mm2s_prmry_resetn), - .p_10_out(p_10_out), - .p_17_out(p_17_out), - .p_23_out(p_23_out), - .p_46_out(p_46_out), - .p_49_out(p_49_out), - .p_68_out({p_68_out[31:17],p_68_out[4]}), - .p_6_out__1(p_6_out__1), - .prmry_resetn_i_reg(p_0_in)); - Arty_Z7_20_axi_vdma_0_0_axi_datamover I_PRMRY_DATAMOVER - (.E(I_PRMRY_DATAMOVER_n_6), - .Q(\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_rd_empty ), - .cmnd_wr(cmnd_wr), - .decerr_i_reg(I_PRMRY_DATAMOVER_n_43), - .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), - .dm2linebuf_mm2s_tvalid(dm2linebuf_mm2s_tvalid), - .fifo_wren__0(fifo_wren__0), - .halt_i_reg(I_RST_MODULE_n_17), - .in({p_56_out[63:32],p_56_out[23],p_56_out[15:0]}), - .interr_i_reg(I_PRMRY_DATAMOVER_n_41), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axi_mm2s_araddr(m_axi_mm2s_araddr), - .m_axi_mm2s_arburst(\^m_axi_mm2s_arburst ), - .m_axi_mm2s_arlen(\^m_axi_mm2s_arlen ), - .m_axi_mm2s_arready(m_axi_mm2s_arready), - .m_axi_mm2s_arsize(\^m_axi_mm2s_arsize ), - .m_axi_mm2s_arvalid(m_axi_mm2s_arvalid), - .m_axi_mm2s_rdata(m_axi_mm2s_rdata), - .m_axi_mm2s_rlast(m_axi_mm2s_rlast), - .m_axi_mm2s_rready(m_axi_mm2s_rready), - .m_axi_mm2s_rresp(m_axi_mm2s_rresp), - .m_axi_mm2s_rvalid(m_axi_mm2s_rvalid), - .mm2s_halt(mm2s_halt), - .mm2s_halt_cmplt(mm2s_halt_cmplt), - .out(mm2s_dm_prmry_resetn), - .p_55_out(p_55_out), - .p_57_out(p_57_out), - .p_8_out(p_8_out), - .sig_rst2all_stop_request(\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/sig_rst2all_stop_request ), - .\sig_user_skid_reg_reg[0] (dm2linebuf_mm2s_tlast), - .slverr_i_reg(I_PRMRY_DATAMOVER_n_42), - .sts_tready_reg(\GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_38 )); - Arty_Z7_20_axi_vdma_0_0_axi_vdma_rst_module I_RST_MODULE - (.D(mm2s_axi2ip_wrdata[2]), - .DIN(sof_flag), - .\FSM_sequential_dmacntrl_cs_reg[1] (p_37_out), - .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 (\GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_3 ), - .\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from (mm2s_axis_resetn), - .\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_0 (\GEN_CDC_FOR_ASYNC.PRMTR_UPDT_CDC_I/scndry_reset2 ), - .\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0] (p_0_in), - .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg (I_RST_MODULE_n_14), - .\GEN_LINEBUF_NO_SOF.vsize_counter_reg[12] (p_7_out), - .SR(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.MM2S_INTRPT_CROSSING_I/scndry_reset2 ), - .axi_resetn(axi_resetn), - .\cmnds_queued_reg[7] (I_RST_MODULE_n_15), - .dm2linebuf_mm2s_tvalid(dm2linebuf_mm2s_tvalid), - .dma_err(dma_err), - .\dmacr_i_reg[2] (I_RST_MODULE_n_13), - .fifo_full_i(fifo_full_i), - .fifo_wren__0(fifo_wren__0), - .halt_reset(\GEN_RESET_FOR_MM2S.RESET_I/halt_reset ), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axis_mm2s_aclk(m_axis_mm2s_aclk), - .mm2s_axi2ip_wrce(mm2s_axi2ip_wrce[0]), - .mm2s_halt(mm2s_halt), - .mm2s_halt_cmplt(mm2s_halt_cmplt), - .out(mm2s_prmry_resetn), + .num_fstore_minus1(num_fstore_minus1), + .p_14_out(p_14_out), .p_15_out(p_15_out), - .p_23_out(p_23_out), - .p_35_out(p_35_out), - .p_68_out({p_68_out[2],p_68_out[0]}), - .p_8_out(p_8_out), - .prmry_in(s_axi_lite_resetn), - .prmry_reset2(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.MM2S_INTRPT_CROSSING_I/prmry_reset2 ), - .reset_counts(\I_DMA_REGISTER/reset_counts ), - .reset_counts_reg(I_RST_MODULE_n_16), - .s_axi_lite_aclk(s_axi_lite_aclk), - .s_soft_reset_i0(\GEN_RESET_FOR_MM2S.RESET_I/s_soft_reset_i0 ), - .sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0(mm2s_dm_prmry_resetn), - .sig_rst2all_stop_request(\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/sig_rst2all_stop_request ), - .sig_s_h_halt_reg_reg(I_RST_MODULE_n_17)); - VCC VCC - (.P(\ )); + .p_6_out(p_6_out), + .prmry_in(prmry_in), + .prmry_resetn_i_reg(prmry_resetn_i_reg), + .reset_counts(reset_counts), + .reset_counts_reg_0(reset_counts_reg), + .s2mm_axi2ip_wrce(s2mm_axi2ip_wrce[3:1]), + .s2mm_cdc2dmac_fsync(s2mm_cdc2dmac_fsync), + .s2mm_dmacr(s2mm_dmacr), + .s2mm_halt_cmplt(s2mm_halt_cmplt), + .s2mm_ioc_irq_set(s2mm_ioc_irq_set), + .s2mm_ip2axi_introut(s2mm_ip2axi_introut), + .s2mm_packet_sof(s2mm_packet_sof), + .s2mm_stop(s2mm_stop), + .s2mm_tstvect_fsync(s2mm_tstvect_fsync), + .s2mm_valid_frame_sync(s2mm_valid_frame_sync), + .s2mm_valid_video_prmtrs(s2mm_valid_video_prmtrs), + .s_axis_cmd_tvalid_reg(s_axis_cmd_tvalid_reg), + .s_soft_reset_i0(s_soft_reset_i0), + .slverr_i_reg(slverr_i_reg), + .soft_reset_d1_reg(s2mm_soft_reset)); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_mux__parameterized0 LITE_READ_MUX_I + (.\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] (\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] ), + .out(out)); + FDRE #( + .INIT(1'b0)) + \ptr_ref_i_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[8]), + .Q(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4] [0]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \ptr_ref_i_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[9]), + .Q(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4] [1]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \ptr_ref_i_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[10]), + .Q(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4] [2]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \ptr_ref_i_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[11]), + .Q(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4] [3]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \ptr_ref_i_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[12]), + .Q(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4] [4]), + .R(SR)); endmodule -(* ORIG_REF_NAME = "axi_vdma_afifo_builtin" *) -module Arty_Z7_20_axi_vdma_0_0_axi_vdma_afifo_builtin - (fifo_full_i, - sig_m_valid_out_reg, - fifo_dout, +(* ORIG_REF_NAME = "axi_vdma_reg_mux" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_mux + (out, + in0); + output [31:0]out; + input [31:0]in0; + + (* DONT_TOUCH *) wire [31:0]ip2axi_rddata_int; + + assign ip2axi_rddata_int = in0[31:0]; + assign out[31:0] = ip2axi_rddata_int; +endmodule + +(* ORIG_REF_NAME = "axi_vdma_reg_mux" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_mux__parameterized0 + (out, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] ); + output [31:0]out; + input [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] ; + + (* DONT_TOUCH *) wire [31:0]ip2axi_rddata_int; + + assign ip2axi_rddata_int = \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [31:0]; + assign out[31:0] = ip2axi_rddata_int; +endmodule + +(* ORIG_REF_NAME = "axi_vdma_regdirect" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_regdirect + (p_67_out, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0] , + \hsize_vid_reg[15] , + \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] , + \vsize_vid_reg[12] , + \stride_vid_reg[15] , + in0, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] , + \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12] , + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg , + SR, + \dmacr_i_reg[0] , m_axi_mm2s_aclk, - s_axis_fifo_ainit_nosync_reg, - m_axis_mm2s_aclk, - fifo_wren__0, - out, - dm2linebuf_mm2s_tdata, - DIN); - output fifo_full_i; - output sig_m_valid_out_reg; - output [33:0]fifo_dout; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[2] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_0 , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[4] , + p_71_out, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_1 , + \dmacr_i_reg[2] , + \GEN_NOSYNCEN_BIT.dmacr_i_reg[15] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]_0 , + stop, + prmry_resetn_i_reg, + halted_reg, + p_24_out, + prmtr_update_complete, + mm2s_axi2ip_wrce, + D); + output p_67_out; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0] ; + output [15:0]\hsize_vid_reg[15] ; + output [31:0]\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] ; + output [12:0]\vsize_vid_reg[12] ; + output [15:0]\stride_vid_reg[15] ; + output [2:0]in0; + output [31:0]\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] ; + output [31:0]\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] ; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3] ; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4] ; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5] ; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6] ; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7] ; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8] ; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9] ; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10] ; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11] ; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12] ; + output \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg ; + input [0:0]SR; + input \dmacr_i_reg[0] ; input m_axi_mm2s_aclk; - input s_axis_fifo_ainit_nosync_reg; - input m_axis_mm2s_aclk; - input fifo_wren__0; - input out; - input [31:0]dm2linebuf_mm2s_tdata; - input [1:0]DIN; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[2] ; + input [1:0]\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] ; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7] ; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_0 ; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[4] ; + input [0:0]p_71_out; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_1 ; + input \dmacr_i_reg[2] ; + input \GEN_NOSYNCEN_BIT.dmacr_i_reg[15] ; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]_0 ; + input stop; + input prmry_resetn_i_reg; + input halted_reg; + input p_24_out; + input prmtr_update_complete; + input [5:0]mm2s_axi2ip_wrce; + input [31:0]D; - wire [1:0]DIN; - wire [31:0]dm2linebuf_mm2s_tdata; - wire [33:0]fifo_dout; - wire fifo_full_i; - wire fifo_wren__0; + wire [31:0]D; + wire [1:0]\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]_0 ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[4] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_0 ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_1 ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[2] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9] ; + wire \GEN_NOSYNCEN_BIT.dmacr_i_reg[15] ; + wire \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg ; + wire [31:0]\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] ; + wire [31:0]\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] ; + wire [31:0]\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] ; + wire [0:0]SR; + wire \dmacr_i_reg[0] ; + wire \dmacr_i_reg[2] ; + wire halted_reg; + wire [15:0]\hsize_vid_reg[15] ; + wire [2:0]in0; + wire ip2axi_rddata_int_inferred_i_51_n_0; + wire ip2axi_rddata_int_inferred_i_74_n_0; + wire ip2axi_rddata_int_inferred_i_75_n_0; + wire ip2axi_rddata_int_inferred_i_79_n_0; + wire ip2axi_rddata_int_inferred_i_80_n_0; wire m_axi_mm2s_aclk; - wire m_axis_mm2s_aclk; - wire out; - wire s_axis_fifo_ainit_nosync_reg; - wire sig_m_valid_out_reg; + wire [5:0]mm2s_axi2ip_wrce; + wire p_24_out; + wire p_66_out; + wire p_67_out; + wire [0:0]p_71_out; + wire prmry_resetn_i_reg; + wire prmtr_update_complete; + wire regdir_idle_i_i_1_n_0; + wire run_stop_d1; + wire stop; + wire [15:0]\stride_vid_reg[15] ; + wire [12:0]\vsize_vid_reg[12] ; - Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3 fg_builtin_fifo_inst - (.DIN(DIN), - .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), - .fifo_dout(fifo_dout), - .fifo_full_i(fifo_full_i), - .fifo_wren__0(fifo_wren__0), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axis_mm2s_aclk(m_axis_mm2s_aclk), - .out(out), - .s_axis_fifo_ainit_nosync_reg(s_axis_fifo_ainit_nosync_reg), - .sig_m_valid_out_reg(sig_m_valid_out_reg)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[0]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [0]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[10] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[10]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [10]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[11] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[11]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [11]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[12] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[12]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [12]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[13] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[13]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [13]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[14] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[14]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [14]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[15] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[15]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [15]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[16] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[16]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [16]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[17] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[17]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [17]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[18] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[18]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [18]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[19] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[19]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [19]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[1]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [1]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[20] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[20]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [20]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[21] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[21]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [21]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[22] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[22]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [22]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[23] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[23]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [23]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[24] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[24]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [24]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[25] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[25]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [25]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[26] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[26]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [26]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[27] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[27]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [27]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[28] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[28]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [28]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[29] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[29]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [29]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[2]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [2]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[30] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[30]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [30]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[31]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [31]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[3]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [3]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[4]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [4]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[5]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [5]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[6] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[6]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [6]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[7]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [7]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[8] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[8]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [8]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[9] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[3]), + .D(D[9]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [9]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[0]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [0]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[10] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[10]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [10]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[11] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[11]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [11]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[12] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[12]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [12]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[13] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[13]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [13]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[14] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[14]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [14]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[15] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[15]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [15]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[16] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[16]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [16]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[17] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[17]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [17]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[18] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[18]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [18]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[19] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[19]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [19]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[1]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [1]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[20] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[20]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [20]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[21] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[21]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [21]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[22] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[22]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [22]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[23] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[23]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [23]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[24] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[24]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [24]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[25] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[25]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [25]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[26] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[26]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [26]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[27] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[27]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [27]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[28] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[28]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [28]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[29] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[29]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [29]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[2]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [2]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[30] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[30]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [30]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[31]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [31]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[3]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [3]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[4]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [4]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[5]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [5]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[6] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[6]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [6]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[7]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [7]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[8] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[8]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [8]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[9] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[4]), + .D(D[9]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [9]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[0]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [0]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[10] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[10]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [10]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[11] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[11]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [11]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[12] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[12]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [12]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[13] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[13]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [13]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[14] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[14]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [14]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[15] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[15]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [15]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[16] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[16]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [16]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[17] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[17]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [17]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[18] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[18]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [18]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[19] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[19]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [19]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[1]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [1]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[20] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[20]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [20]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[21] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[21]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [21]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[22] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[22]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [22]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[23] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[23]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [23]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[24] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[24]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [24]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[25] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[25]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [25]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[26] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[26]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [26]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[27] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[27]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [27]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[28] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[28]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [28]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[29] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[29]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [29]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[2]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [2]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[30] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[30]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [30]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[31]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [31]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[3]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [3]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[4]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [4]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[5]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [5]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[6] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[6]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [6]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[7]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [7]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[8] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[8]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [8]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[9] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[5]), + .D(D[9]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [9]), + .R(SR)); + FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[2]), + .D(D[0]), + .Q(\stride_vid_reg[15] [0]), + .R(SR)); + FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[10] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[2]), + .D(D[10]), + .Q(\stride_vid_reg[15] [10]), + .R(SR)); + FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[11] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[2]), + .D(D[11]), + .Q(\stride_vid_reg[15] [11]), + .R(SR)); + FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[12] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[2]), + .D(D[12]), + .Q(\stride_vid_reg[15] [12]), + .R(SR)); + FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[13] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[2]), + .D(D[13]), + .Q(\stride_vid_reg[15] [13]), + .R(SR)); + FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[14] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[2]), + .D(D[14]), + .Q(\stride_vid_reg[15] [14]), + .R(SR)); + FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[2]), + .D(D[15]), + .Q(\stride_vid_reg[15] [15]), + .R(SR)); + FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[2]), + .D(D[1]), + .Q(\stride_vid_reg[15] [1]), + .R(SR)); + FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[2]), + .D(D[2]), + .Q(\stride_vid_reg[15] [2]), + .R(SR)); + FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[2]), + .D(D[3]), + .Q(\stride_vid_reg[15] [3]), + .R(SR)); + FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[2]), + .D(D[4]), + .Q(\stride_vid_reg[15] [4]), + .R(SR)); + FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[2]), + .D(D[5]), + .Q(\stride_vid_reg[15] [5]), + .R(SR)); + FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[6] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[2]), + .D(D[6]), + .Q(\stride_vid_reg[15] [6]), + .R(SR)); + FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[2]), + .D(D[7]), + .Q(\stride_vid_reg[15] [7]), + .R(SR)); + FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[8] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[2]), + .D(D[8]), + .Q(\stride_vid_reg[15] [8]), + .R(SR)); + FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[9] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[2]), + .D(D[9]), + .Q(\stride_vid_reg[15] [9]), + .R(SR)); + LUT5 #( + .INIT(32'h00302020)) + \VIDEO_REG_I/GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_i_1 + (.I0(p_66_out), + .I1(halted_reg), + .I2(prmry_resetn_i_reg), + .I3(p_24_out), + .I4(prmtr_update_complete), + .O(\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg )); + LUT4 #( + .INIT(16'hFFEA)) + ip2axi_rddata_int_inferred_i_17 + (.I0(ip2axi_rddata_int_inferred_i_51_n_0), + .I1(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_1 ), + .I2(\GEN_NOSYNCEN_BIT.dmacr_i_reg[15] ), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]_0 ), + .O(in0[2])); + LUT5 #( + .INIT(32'hFFFFF888)) + ip2axi_rddata_int_inferred_i_30 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7] ), + .I1(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [2]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_0 ), + .I3(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [2]), + .I4(ip2axi_rddata_int_inferred_i_74_n_0), + .O(in0[1])); + LUT5 #( + .INIT(32'hFFFFF888)) + ip2axi_rddata_int_inferred_i_31 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7] ), + .I1(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [1]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_0 ), + .I3(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [1]), + .I4(ip2axi_rddata_int_inferred_i_75_n_0), + .O(in0[0])); + LUT4 #( + .INIT(16'hF888)) + ip2axi_rddata_int_inferred_i_51 + (.I0(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [15]), + .I1(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_0 ), + .I2(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [15]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7] ), + .O(ip2axi_rddata_int_inferred_i_51_n_0)); + LUT6 #( + .INIT(64'hCAFFCAF0CA0FCA00)) + ip2axi_rddata_int_inferred_i_60 + (.I0(\hsize_vid_reg[15] [12]), + .I1(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [12]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [1]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [0]), + .I4(\vsize_vid_reg[12] [12]), + .I5(\stride_vid_reg[15] [12]), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12] )); + LUT6 #( + .INIT(64'hCAFFCAF0CA0FCA00)) + ip2axi_rddata_int_inferred_i_61 + (.I0(\hsize_vid_reg[15] [11]), + .I1(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [11]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [1]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [0]), + .I4(\vsize_vid_reg[12] [11]), + .I5(\stride_vid_reg[15] [11]), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11] )); + LUT6 #( + .INIT(64'hCAFFCAF0CA0FCA00)) + ip2axi_rddata_int_inferred_i_63 + (.I0(\hsize_vid_reg[15] [10]), + .I1(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [10]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [1]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [0]), + .I4(\vsize_vid_reg[12] [10]), + .I5(\stride_vid_reg[15] [10]), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10] )); + LUT6 #( + .INIT(64'hCAFFCAF0CA0FCA00)) + ip2axi_rddata_int_inferred_i_64 + (.I0(\hsize_vid_reg[15] [9]), + .I1(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [9]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [1]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [0]), + .I4(\vsize_vid_reg[12] [9]), + .I5(\stride_vid_reg[15] [9]), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9] )); + LUT6 #( + .INIT(64'hCAFFCAF0CA0FCA00)) + ip2axi_rddata_int_inferred_i_65 + (.I0(\hsize_vid_reg[15] [8]), + .I1(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [8]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [1]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [0]), + .I4(\vsize_vid_reg[12] [8]), + .I5(\stride_vid_reg[15] [8]), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8] )); + LUT6 #( + .INIT(64'hCAFFCAF0CA0FCA00)) + ip2axi_rddata_int_inferred_i_66 + (.I0(\hsize_vid_reg[15] [7]), + .I1(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [7]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [1]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [0]), + .I4(\vsize_vid_reg[12] [7]), + .I5(\stride_vid_reg[15] [7]), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7] )); + LUT6 #( + .INIT(64'hCAFFCAF0CA0FCA00)) + ip2axi_rddata_int_inferred_i_68 + (.I0(\hsize_vid_reg[15] [6]), + .I1(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [6]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [1]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [0]), + .I4(\vsize_vid_reg[12] [6]), + .I5(\stride_vid_reg[15] [6]), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6] )); + LUT6 #( + .INIT(64'hCAFFCAF0CA0FCA00)) + ip2axi_rddata_int_inferred_i_70 + (.I0(\hsize_vid_reg[15] [5]), + .I1(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [5]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [1]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [0]), + .I4(\vsize_vid_reg[12] [5]), + .I5(\stride_vid_reg[15] [5]), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5] )); + LUT6 #( + .INIT(64'hCAFFCAF0CA0FCA00)) + ip2axi_rddata_int_inferred_i_72 + (.I0(\hsize_vid_reg[15] [4]), + .I1(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [4]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [1]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [0]), + .I4(\vsize_vid_reg[12] [4]), + .I5(\stride_vid_reg[15] [4]), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4] )); + LUT6 #( + .INIT(64'hCAFFCAF0CA0FCA00)) + ip2axi_rddata_int_inferred_i_73 + (.I0(\hsize_vid_reg[15] [3]), + .I1(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [3]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [1]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [0]), + .I4(\vsize_vid_reg[12] [3]), + .I5(\stride_vid_reg[15] [3]), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3] )); + LUT4 #( + .INIT(16'hF888)) + ip2axi_rddata_int_inferred_i_74 + (.I0(ip2axi_rddata_int_inferred_i_79_n_0), + .I1(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[4] ), + .I2(\dmacr_i_reg[2] ), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_1 ), + .O(ip2axi_rddata_int_inferred_i_74_n_0)); + LUT4 #( + .INIT(16'hF888)) + ip2axi_rddata_int_inferred_i_75 + (.I0(ip2axi_rddata_int_inferred_i_80_n_0), + .I1(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[4] ), + .I2(p_71_out), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_1 ), + .O(ip2axi_rddata_int_inferred_i_75_n_0)); + LUT6 #( + .INIT(64'hCAFFCAF0CA0FCA00)) + ip2axi_rddata_int_inferred_i_77 + (.I0(\hsize_vid_reg[15] [0]), + .I1(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [0]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [1]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [0]), + .I4(\vsize_vid_reg[12] [0]), + .I5(\stride_vid_reg[15] [0]), + .O(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0] )); + LUT6 #( + .INIT(64'hCAFFCAF0CA0FCA00)) + ip2axi_rddata_int_inferred_i_79 + (.I0(\hsize_vid_reg[15] [2]), + .I1(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [2]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [1]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [0]), + .I4(\vsize_vid_reg[12] [2]), + .I5(\stride_vid_reg[15] [2]), + .O(ip2axi_rddata_int_inferred_i_79_n_0)); + LUT6 #( + .INIT(64'hCAFFCAF0CA0FCA00)) + ip2axi_rddata_int_inferred_i_80 + (.I0(\hsize_vid_reg[15] [1]), + .I1(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [1]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [1]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [0]), + .I4(\vsize_vid_reg[12] [1]), + .I5(\stride_vid_reg[15] [1]), + .O(ip2axi_rddata_int_inferred_i_80_n_0)); + FDRE #( + .INIT(1'b0)) + prmtr_updt_complete_i_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[2] ), + .Q(p_66_out), + .R(1'b0)); + FDRE \reg_module_hsize_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[1]), + .D(D[0]), + .Q(\hsize_vid_reg[15] [0]), + .R(SR)); + FDRE \reg_module_hsize_reg[10] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[1]), + .D(D[10]), + .Q(\hsize_vid_reg[15] [10]), + .R(SR)); + FDRE \reg_module_hsize_reg[11] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[1]), + .D(D[11]), + .Q(\hsize_vid_reg[15] [11]), + .R(SR)); + FDRE \reg_module_hsize_reg[12] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[1]), + .D(D[12]), + .Q(\hsize_vid_reg[15] [12]), + .R(SR)); + FDRE \reg_module_hsize_reg[13] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[1]), + .D(D[13]), + .Q(\hsize_vid_reg[15] [13]), + .R(SR)); + FDRE \reg_module_hsize_reg[14] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[1]), + .D(D[14]), + .Q(\hsize_vid_reg[15] [14]), + .R(SR)); + FDRE \reg_module_hsize_reg[15] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[1]), + .D(D[15]), + .Q(\hsize_vid_reg[15] [15]), + .R(SR)); + FDRE \reg_module_hsize_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[1]), + .D(D[1]), + .Q(\hsize_vid_reg[15] [1]), + .R(SR)); + FDRE \reg_module_hsize_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[1]), + .D(D[2]), + .Q(\hsize_vid_reg[15] [2]), + .R(SR)); + FDRE \reg_module_hsize_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[1]), + .D(D[3]), + .Q(\hsize_vid_reg[15] [3]), + .R(SR)); + FDRE \reg_module_hsize_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[1]), + .D(D[4]), + .Q(\hsize_vid_reg[15] [4]), + .R(SR)); + FDRE \reg_module_hsize_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[1]), + .D(D[5]), + .Q(\hsize_vid_reg[15] [5]), + .R(SR)); + FDRE \reg_module_hsize_reg[6] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[1]), + .D(D[6]), + .Q(\hsize_vid_reg[15] [6]), + .R(SR)); + FDRE \reg_module_hsize_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[1]), + .D(D[7]), + .Q(\hsize_vid_reg[15] [7]), + .R(SR)); + FDRE \reg_module_hsize_reg[8] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[1]), + .D(D[8]), + .Q(\hsize_vid_reg[15] [8]), + .R(SR)); + FDRE \reg_module_hsize_reg[9] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[1]), + .D(D[9]), + .Q(\hsize_vid_reg[15] [9]), + .R(SR)); + FDRE \reg_module_vsize_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[0]), + .Q(\vsize_vid_reg[12] [0]), + .R(SR)); + FDRE \reg_module_vsize_reg[10] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[10]), + .Q(\vsize_vid_reg[12] [10]), + .R(SR)); + FDRE \reg_module_vsize_reg[11] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[11]), + .Q(\vsize_vid_reg[12] [11]), + .R(SR)); + FDRE \reg_module_vsize_reg[12] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[12]), + .Q(\vsize_vid_reg[12] [12]), + .R(SR)); + FDRE \reg_module_vsize_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[1]), + .Q(\vsize_vid_reg[12] [1]), + .R(SR)); + FDRE \reg_module_vsize_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[2]), + .Q(\vsize_vid_reg[12] [2]), + .R(SR)); + FDRE \reg_module_vsize_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[3]), + .Q(\vsize_vid_reg[12] [3]), + .R(SR)); + FDRE \reg_module_vsize_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[4]), + .Q(\vsize_vid_reg[12] [4]), + .R(SR)); + FDRE \reg_module_vsize_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[5]), + .Q(\vsize_vid_reg[12] [5]), + .R(SR)); + FDRE \reg_module_vsize_reg[6] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[6]), + .Q(\vsize_vid_reg[12] [6]), + .R(SR)); + FDRE \reg_module_vsize_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[7]), + .Q(\vsize_vid_reg[12] [7]), + .R(SR)); + FDRE \reg_module_vsize_reg[8] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[8]), + .Q(\vsize_vid_reg[12] [8]), + .R(SR)); + FDRE \reg_module_vsize_reg[9] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[9]), + .Q(\vsize_vid_reg[12] [9]), + .R(SR)); + LUT6 #( + .INIT(64'hFFFFCF8AFFFFFFFF)) + regdir_idle_i_i_1 + (.I0(p_67_out), + .I1(run_stop_d1), + .I2(\dmacr_i_reg[0] ), + .I3(p_66_out), + .I4(stop), + .I5(prmry_resetn_i_reg), + .O(regdir_idle_i_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + regdir_idle_i_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(regdir_idle_i_i_1_n_0), + .Q(p_67_out), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + run_stop_d1_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\dmacr_i_reg[0] ), + .Q(run_stop_d1), + .R(SR)); endmodule -(* ORIG_REF_NAME = "axi_vdma_cmdsts_if" *) -module Arty_Z7_20_axi_vdma_0_0_axi_vdma_cmdsts_if - (\cmnds_queued_reg[7] , - err_i_reg_0, - \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg , - err_i_reg_1, - dmacntrl_ns14_out, - p_3_in, - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from , - \FSM_sequential_dmacntrl_cs_reg[1] , - dma_decerr_reg, - dma_slverr_reg, - \INFERRED_GEN.cnt_i_reg[1] , - \sig_addr_cntr_lsh_kh_reg[31] , - out, - m_axi_mm2s_aclk, - p_0_in, - \INFERRED_GEN.cnt_i_reg[2] , - \INFERRED_GEN.cnt_i_reg[2]_0 , - \INFERRED_GEN.cnt_i_reg[2]_1 , +(* ORIG_REF_NAME = "axi_vdma_regdirect" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_regdirect__parameterized0 + (prmry_in_xored, + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg , + \vsize_vid_reg[12] , + \hsize_vid_reg[15] , + \stride_vid_reg[15] , + \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] , + \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[2] , + m_axi_s2mm_aclk, + p_in_d1_cdc_from, + halted_reg, + prmry_resetn_i_reg, + prmtr_update_complete, + s2mm_cdc2dmac_fsync, SR, - E, - \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg_0 , - mm2s_halt, - p_68_out, - frame_sync_reg, - \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg , - zero_hsize_err, - zero_vsize_err, - dma_decerr_reg_0, - dma_slverr_reg_0, - \INFERRED_GEN.cnt_i_reg[2]_2 , + s2mm_axi2ip_wrce, D); - output \cmnds_queued_reg[7] ; - output err_i_reg_0; - output \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg ; - output err_i_reg_1; - output dmacntrl_ns14_out; - output p_3_in; - output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ; - output \FSM_sequential_dmacntrl_cs_reg[1] ; - output dma_decerr_reg; - output dma_slverr_reg; - output \INFERRED_GEN.cnt_i_reg[1] ; - output [48:0]\sig_addr_cntr_lsh_kh_reg[31] ; - input out; - input m_axi_mm2s_aclk; - input p_0_in; - input \INFERRED_GEN.cnt_i_reg[2] ; - input \INFERRED_GEN.cnt_i_reg[2]_0 ; - input \INFERRED_GEN.cnt_i_reg[2]_1 ; + output prmry_in_xored; + output \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg ; + output [12:0]\vsize_vid_reg[12] ; + output [15:0]\hsize_vid_reg[15] ; + output [15:0]\stride_vid_reg[15] ; + output [31:0]\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] ; + output [31:0]\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] ; + output [31:0]\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] ; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[2] ; + input m_axi_s2mm_aclk; + input p_in_d1_cdc_from; + input halted_reg; + input prmry_resetn_i_reg; + input prmtr_update_complete; + input s2mm_cdc2dmac_fsync; input [0:0]SR; - input [0:0]E; - input \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg_0 ; - input mm2s_halt; - input [1:0]p_68_out; - input frame_sync_reg; - input \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg ; - input zero_hsize_err; - input zero_vsize_err; - input dma_decerr_reg_0; - input dma_slverr_reg_0; - input [0:0]\INFERRED_GEN.cnt_i_reg[2]_2 ; - input [48:0]D; + input [5:0]s2mm_axi2ip_wrce; + input [31:0]D; - wire [48:0]D; - wire [0:0]E; - wire \FSM_sequential_dmacntrl_cs_reg[1] ; - wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg_0 ; - wire \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg ; - wire \INFERRED_GEN.cnt_i_reg[1] ; - wire \INFERRED_GEN.cnt_i_reg[2] ; - wire \INFERRED_GEN.cnt_i_reg[2]_0 ; - wire \INFERRED_GEN.cnt_i_reg[2]_1 ; - wire [0:0]\INFERRED_GEN.cnt_i_reg[2]_2 ; + wire [31:0]D; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[2] ; + wire \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg ; + wire [31:0]\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] ; + wire [31:0]\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] ; + wire [31:0]\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] ; wire [0:0]SR; - wire \cmnds_queued_reg[7] ; - wire dma_decerr_reg; - wire dma_decerr_reg_0; - wire dma_slverr_reg; - wire dma_slverr_reg_0; - wire dmacntrl_ns14_out; - wire err_i_i_1_n_0; - wire err_i_reg_0; - wire err_i_reg_1; - wire frame_sync_reg; - wire m_axi_mm2s_aclk; - wire mm2s_halt; - wire out; - wire p_0_in; - wire p_3_in; - wire p_53_out; - wire p_54_out; - wire [1:0]p_68_out; - wire [48:0]\sig_addr_cntr_lsh_kh_reg[31] ; - wire zero_hsize_err; - wire zero_vsize_err; + wire halted_reg; + wire [15:0]\hsize_vid_reg[15] ; + wire m_axi_s2mm_aclk; + wire p_in_d1_cdc_from; + wire prmry_in_xored; + wire prmry_resetn_i_reg; + wire prmtr_update_complete; + wire [5:0]s2mm_axi2ip_wrce; + wire s2mm_cdc2dmac_fsync; + wire s2mm_prmtr_updt_complete; + wire [15:0]\stride_vid_reg[15] ; + wire [12:0]\vsize_vid_reg[12] ; - LUT3 #( - .INIT(8'hFE)) - \FSM_sequential_dmacntrl_cs[0]_i_5 - (.I0(err_i_reg_1), - .I1(p_68_out[1]), - .I2(mm2s_halt), - .O(p_3_in)); - (* SOFT_HLUTNM = "soft_lutpair6" *) - LUT5 #( - .INIT(32'hFFFEFFFF)) - \FSM_sequential_dmacntrl_cs[1]_i_3 - (.I0(err_i_reg_1), - .I1(p_68_out[1]), - .I2(mm2s_halt), - .I3(frame_sync_reg), - .I4(p_68_out[0]), - .O(\FSM_sequential_dmacntrl_cs_reg[1] )); - LUT6 #( - .INIT(64'h0000100000000000)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_3 - (.I0(err_i_reg_1), - .I1(p_68_out[1]), - .I2(p_68_out[0]), - .I3(\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg ), - .I4(mm2s_halt), - .I5(frame_sync_reg), - .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from )); - (* SOFT_HLUTNM = "soft_lutpair6" *) - LUT4 #( - .INIT(16'hFFFE)) - \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_i_2 - (.I0(mm2s_halt), - .I1(p_68_out[1]), - .I2(err_i_reg_1), - .I3(frame_sync_reg), - .O(dmacntrl_ns14_out)); + FDRE \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[2]), + .D(D[0]), + .Q(\stride_vid_reg[15] [0]), + .R(SR)); + FDRE \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[2]), + .D(D[10]), + .Q(\stride_vid_reg[15] [10]), + .R(SR)); + FDRE \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[2]), + .D(D[11]), + .Q(\stride_vid_reg[15] [11]), + .R(SR)); + FDRE \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[2]), + .D(D[12]), + .Q(\stride_vid_reg[15] [12]), + .R(SR)); + FDRE \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[13] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[2]), + .D(D[13]), + .Q(\stride_vid_reg[15] [13]), + .R(SR)); + FDRE \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[14] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[2]), + .D(D[14]), + .Q(\stride_vid_reg[15] [14]), + .R(SR)); + FDRE \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[2]), + .D(D[15]), + .Q(\stride_vid_reg[15] [15]), + .R(SR)); + FDRE \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[2]), + .D(D[1]), + .Q(\stride_vid_reg[15] [1]), + .R(SR)); + FDRE \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[2]), + .D(D[2]), + .Q(\stride_vid_reg[15] [2]), + .R(SR)); + FDRE \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[2]), + .D(D[3]), + .Q(\stride_vid_reg[15] [3]), + .R(SR)); + FDRE \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[2]), + .D(D[4]), + .Q(\stride_vid_reg[15] [4]), + .R(SR)); + FDRE \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[2]), + .D(D[5]), + .Q(\stride_vid_reg[15] [5]), + .R(SR)); + FDRE \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[2]), + .D(D[6]), + .Q(\stride_vid_reg[15] [6]), + .R(SR)); + FDRE \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[2]), + .D(D[7]), + .Q(\stride_vid_reg[15] [7]), + .R(SR)); + FDRE \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[2]), + .D(D[8]), + .Q(\stride_vid_reg[15] [8]), + .R(SR)); + FDRE \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[2]), + .D(D[9]), + .Q(\stride_vid_reg[15] [9]), + .R(SR)); LUT2 #( - .INIT(4'h2)) - \INFERRED_GEN.cnt_i[1]_i_2 - (.I0(\cmnds_queued_reg[7] ), - .I1(\INFERRED_GEN.cnt_i_reg[2]_2 ), - .O(\INFERRED_GEN.cnt_i_reg[1] )); + .INIT(4'h6)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__15 + (.I0(s2mm_prmtr_updt_complete), + .I1(p_in_d1_cdc_from), + .O(prmry_in_xored)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[0]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [0]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[10]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [10]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[11]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [11]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[12]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [12]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[13] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[13]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [13]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[14] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[14]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [14]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[15] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[15]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [15]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[16] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[16]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [16]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[17] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[17]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [17]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[18] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[18]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [18]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[19] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[19]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [19]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[1]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [1]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[20] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[20]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [20]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[21] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[21]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [21]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[22] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[22]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [22]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[23] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[23]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [23]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[24] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[24]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [24]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[25] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[25]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [25]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[26] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[26]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [26]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[27] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[27]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [27]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[28] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[28]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [28]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[29] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[29]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [29]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[2]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [2]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[30] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[30]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [30]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[31]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [31]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[3]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [3]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[4]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [4]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[5]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [5]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[6]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [6]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[7]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [7]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[8]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [8]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[3]), + .D(D[9]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [9]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[0]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [0]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[10]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [10]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[11]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [11]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[12]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [12]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[13] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[13]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [13]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[14] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[14]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [14]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[15] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[15]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [15]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[16] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[16]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [16]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[17] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[17]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [17]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[18] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[18]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [18]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[19] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[19]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [19]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[1]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [1]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[20] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[20]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [20]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[21] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[21]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [21]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[22] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[22]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [22]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[23] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[23]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [23]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[24] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[24]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [24]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[25] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[25]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [25]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[26] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[26]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [26]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[27] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[27]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [27]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[28] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[28]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [28]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[29] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[29]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [29]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[2]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [2]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[30] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[30]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [30]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[31]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [31]), + .R(SR)); FDRE #( .INIT(1'b0)) - decerr_i_reg - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\INFERRED_GEN.cnt_i_reg[2] ), - .Q(p_54_out), - .R(p_0_in)); - LUT2 #( - .INIT(4'hE)) - dma_decerr_i_1 - (.I0(p_54_out), - .I1(dma_decerr_reg_0), - .O(dma_decerr_reg)); - LUT2 #( - .INIT(4'hE)) - dma_slverr_i_1 - (.I0(p_53_out), - .I1(dma_slverr_reg_0), - .O(dma_slverr_reg)); - LUT6 #( - .INIT(64'hFFFFFFFFFFFFFFFE)) - err_i_i_1 - (.I0(p_53_out), - .I1(zero_hsize_err), - .I2(zero_vsize_err), - .I3(err_i_reg_0), - .I4(p_54_out), - .I5(err_i_reg_1), - .O(err_i_i_1_n_0)); + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[3]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [3]), + .R(SR)); FDRE #( .INIT(1'b0)) - err_i_reg - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(err_i_i_1_n_0), - .Q(err_i_reg_1), - .R(p_0_in)); + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[4]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [4]), + .R(SR)); FDRE #( .INIT(1'b0)) - interr_i_reg - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\INFERRED_GEN.cnt_i_reg[2]_1 ), - .Q(err_i_reg_0), - .R(p_0_in)); - FDRE \s_axis_cmd_tdata_reg[0] - (.C(m_axi_mm2s_aclk), - .CE(E), + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[5]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [5]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[6]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [6]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[7]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [7]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[8]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [8]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[4]), + .D(D[9]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] [9]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), .D(D[0]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [0]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [0]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[10] - (.C(m_axi_mm2s_aclk), - .CE(E), + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), .D(D[10]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [10]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [10]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[11] - (.C(m_axi_mm2s_aclk), - .CE(E), + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), .D(D[11]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [11]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [11]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[12] - (.C(m_axi_mm2s_aclk), - .CE(E), + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), .D(D[12]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [12]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [12]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[13] - (.C(m_axi_mm2s_aclk), - .CE(E), + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[13] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), .D(D[13]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [13]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [13]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[14] - (.C(m_axi_mm2s_aclk), - .CE(E), + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[14] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), .D(D[14]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [14]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [14]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[15] - (.C(m_axi_mm2s_aclk), - .CE(E), + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[15] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), .D(D[15]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [15]), - .R(SR)); - FDRE \s_axis_cmd_tdata_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(E), - .D(D[1]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [1]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [15]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[23] - (.C(m_axi_mm2s_aclk), - .CE(E), + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[16] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), .D(D[16]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [16]), - .R(SR)); - FDRE \s_axis_cmd_tdata_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(E), - .D(D[2]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [2]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [16]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[32] - (.C(m_axi_mm2s_aclk), - .CE(E), + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[17] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), .D(D[17]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [17]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [17]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[33] - (.C(m_axi_mm2s_aclk), - .CE(E), + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[18] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), .D(D[18]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [18]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [18]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[34] - (.C(m_axi_mm2s_aclk), - .CE(E), + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[19] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), .D(D[19]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [19]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [19]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[35] - (.C(m_axi_mm2s_aclk), - .CE(E), + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), + .D(D[1]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [1]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[20] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), .D(D[20]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [20]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [20]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[36] - (.C(m_axi_mm2s_aclk), - .CE(E), + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[21] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), .D(D[21]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [21]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [21]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[37] - (.C(m_axi_mm2s_aclk), - .CE(E), + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[22] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), .D(D[22]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [22]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [22]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[38] - (.C(m_axi_mm2s_aclk), - .CE(E), + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[23] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), .D(D[23]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [23]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [23]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[39] - (.C(m_axi_mm2s_aclk), - .CE(E), + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[24] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), .D(D[24]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [24]), - .R(SR)); - FDRE \s_axis_cmd_tdata_reg[3] - (.C(m_axi_mm2s_aclk), - .CE(E), - .D(D[3]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [3]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [24]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[40] - (.C(m_axi_mm2s_aclk), - .CE(E), + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[25] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), .D(D[25]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [25]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [25]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[41] - (.C(m_axi_mm2s_aclk), - .CE(E), + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[26] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), .D(D[26]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [26]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [26]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[42] - (.C(m_axi_mm2s_aclk), - .CE(E), + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[27] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), .D(D[27]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [27]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [27]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[43] - (.C(m_axi_mm2s_aclk), - .CE(E), + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[28] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), .D(D[28]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [28]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [28]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[44] - (.C(m_axi_mm2s_aclk), - .CE(E), + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[29] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), .D(D[29]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [29]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [29]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[45] - (.C(m_axi_mm2s_aclk), - .CE(E), + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), + .D(D[2]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [2]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[30] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), .D(D[30]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [30]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [30]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[46] - (.C(m_axi_mm2s_aclk), - .CE(E), + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), .D(D[31]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [31]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [31]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), + .D(D[3]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [3]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), + .D(D[4]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [4]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), + .D(D[5]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [5]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), + .D(D[6]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [6]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), + .D(D[7]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [7]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), + .D(D[8]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [8]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[5]), + .D(D[9]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] [9]), + .R(SR)); + LUT5 #( + .INIT(32'h00203020)) + \VIDEO_REG_I/GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_i_1__0 + (.I0(s2mm_prmtr_updt_complete), + .I1(halted_reg), + .I2(prmry_resetn_i_reg), + .I3(prmtr_update_complete), + .I4(s2mm_cdc2dmac_fsync), + .O(\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg )); + FDRE #( + .INIT(1'b0)) + prmtr_updt_complete_i_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[2] ), + .Q(s2mm_prmtr_updt_complete), + .R(1'b0)); + FDRE \reg_module_hsize_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[1]), + .D(D[0]), + .Q(\hsize_vid_reg[15] [0]), + .R(SR)); + FDRE \reg_module_hsize_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[1]), + .D(D[10]), + .Q(\hsize_vid_reg[15] [10]), + .R(SR)); + FDRE \reg_module_hsize_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[1]), + .D(D[11]), + .Q(\hsize_vid_reg[15] [11]), + .R(SR)); + FDRE \reg_module_hsize_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[1]), + .D(D[12]), + .Q(\hsize_vid_reg[15] [12]), + .R(SR)); + FDRE \reg_module_hsize_reg[13] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[1]), + .D(D[13]), + .Q(\hsize_vid_reg[15] [13]), + .R(SR)); + FDRE \reg_module_hsize_reg[14] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[1]), + .D(D[14]), + .Q(\hsize_vid_reg[15] [14]), + .R(SR)); + FDRE \reg_module_hsize_reg[15] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[1]), + .D(D[15]), + .Q(\hsize_vid_reg[15] [15]), + .R(SR)); + FDRE \reg_module_hsize_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[1]), + .D(D[1]), + .Q(\hsize_vid_reg[15] [1]), + .R(SR)); + FDRE \reg_module_hsize_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[1]), + .D(D[2]), + .Q(\hsize_vid_reg[15] [2]), + .R(SR)); + FDRE \reg_module_hsize_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[1]), + .D(D[3]), + .Q(\hsize_vid_reg[15] [3]), + .R(SR)); + FDRE \reg_module_hsize_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[1]), + .D(D[4]), + .Q(\hsize_vid_reg[15] [4]), + .R(SR)); + FDRE \reg_module_hsize_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[1]), + .D(D[5]), + .Q(\hsize_vid_reg[15] [5]), + .R(SR)); + FDRE \reg_module_hsize_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[1]), + .D(D[6]), + .Q(\hsize_vid_reg[15] [6]), + .R(SR)); + FDRE \reg_module_hsize_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[1]), + .D(D[7]), + .Q(\hsize_vid_reg[15] [7]), + .R(SR)); + FDRE \reg_module_hsize_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[1]), + .D(D[8]), + .Q(\hsize_vid_reg[15] [8]), + .R(SR)); + FDRE \reg_module_hsize_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[1]), + .D(D[9]), + .Q(\hsize_vid_reg[15] [9]), + .R(SR)); + FDRE \reg_module_vsize_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[0]), + .Q(\vsize_vid_reg[12] [0]), + .R(SR)); + FDRE \reg_module_vsize_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[10]), + .Q(\vsize_vid_reg[12] [10]), + .R(SR)); + FDRE \reg_module_vsize_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[11]), + .Q(\vsize_vid_reg[12] [11]), + .R(SR)); + FDRE \reg_module_vsize_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[12]), + .Q(\vsize_vid_reg[12] [12]), + .R(SR)); + FDRE \reg_module_vsize_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[1]), + .Q(\vsize_vid_reg[12] [1]), + .R(SR)); + FDRE \reg_module_vsize_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[2]), + .Q(\vsize_vid_reg[12] [2]), + .R(SR)); + FDRE \reg_module_vsize_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[3]), + .Q(\vsize_vid_reg[12] [3]), + .R(SR)); + FDRE \reg_module_vsize_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[4]), + .Q(\vsize_vid_reg[12] [4]), + .R(SR)); + FDRE \reg_module_vsize_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[5]), + .Q(\vsize_vid_reg[12] [5]), + .R(SR)); + FDRE \reg_module_vsize_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[6]), + .Q(\vsize_vid_reg[12] [6]), + .R(SR)); + FDRE \reg_module_vsize_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[7]), + .Q(\vsize_vid_reg[12] [7]), + .R(SR)); + FDRE \reg_module_vsize_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[8]), + .Q(\vsize_vid_reg[12] [8]), + .R(SR)); + FDRE \reg_module_vsize_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[9]), + .Q(\vsize_vid_reg[12] [9]), + .R(SR)); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_register" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_register + (p_71_out, + soft_reset_d1_reg, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15] , + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6] , + s_axis_cmd_tvalid_reg, + err_d1_reg_0, + err_d1_reg_1, + err_d1_reg_2, + ioc_irq_reg_0, + dly_irq_reg_0, + p_78_out, + s_soft_reset_i0, + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg , + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]_0 , + ch1_delay_zero, + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] , + p_13_out, + Q, + E, + err_irq_reg_0, + \dmacr_i_reg[0]_0 , + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from , + \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4] , + s_axis_cmd_tvalid_reg_0, + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]_1 , + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] , + dmacr_i, + m_axi_mm2s_aclk, + SR, + mm2s_axi2ip_wrce, + D, + \dmacr_i_reg[2]_0 , + reset_counts_reg_0, + halted_clr_reg, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] , + slverr_i_reg, + decerr_i_reg, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13] , + mm2s_halt_cmplt, + halt_reset, + prmry_in, + p_50_out, + ch1_delay_cnt_en, + p_17_out, + ch1_dly_irq_set, + mask_fsync_out_i, + p_47_out, + prmry_resetn_i_reg, + p_24_out, + p_45_out, + mm2s_ioc_irq_set, + dma_err, + mm2s_halt, + initial_frame, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18] , + \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0 ); + output [18:0]p_71_out; + output soft_reset_d1_reg; + output \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15] ; + output \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6] ; + output s_axis_cmd_tvalid_reg; + output err_d1_reg_0; + output err_d1_reg_1; + output err_d1_reg_2; + output ioc_irq_reg_0; + output dly_irq_reg_0; + output p_78_out; + output s_soft_reset_i0; + output \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg ; + output \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]_0 ; + output ch1_delay_zero; + output \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] ; + output p_13_out; + output [4:0]Q; + output [0:0]E; + output err_irq_reg_0; + output \dmacr_i_reg[0]_0 ; + output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ; + output [0:0]\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4] ; + output [0:0]s_axis_cmd_tvalid_reg_0; + output [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]_1 ; + output [4:0]\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] ; + input [0:0]dmacr_i; + input m_axi_mm2s_aclk; + input [0:0]SR; + input [1:0]mm2s_axi2ip_wrce; + input [23:0]D; + input \dmacr_i_reg[2]_0 ; + input reset_counts_reg_0; + input halted_clr_reg; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] ; + input slverr_i_reg; + input decerr_i_reg; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12] ; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13] ; + input mm2s_halt_cmplt; + input halt_reset; + input prmry_in; + input p_50_out; + input ch1_delay_cnt_en; + input p_17_out; + input ch1_dly_irq_set; + input mask_fsync_out_i; + input p_47_out; + input prmry_resetn_i_reg; + input p_24_out; + input p_45_out; + input mm2s_ioc_irq_set; + input dma_err; + input mm2s_halt; + input initial_frame; + input [0:0]\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18] ; + input [4:0]\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0 ; + + wire [23:0]D; + wire [0:0]E; + wire \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_1_n_0 ; + wire \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_2_n_0 ; + wire \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_3_n_0 ; + wire \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_4_n_0 ; + wire \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_5_n_0 ; + wire \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_1_n_0 ; + wire \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_2_n_0 ; + wire \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_3_n_0 ; + wire \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_4_n_0 ; + wire \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_5_n_0 ; + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ; + wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6] ; + wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]_0 ; + wire [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]_1 ; + wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_i_3_n_0 ; + wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg ; + wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] ; + wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_5_n_0 ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13] ; + wire [0:0]\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15] ; + wire [4:0]\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] ; + wire [0:0]\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4] ; + wire [4:0]\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0 ; + wire [4:0]Q; + wire [0:0]SR; + wire ch1_delay_cnt_en; + wire ch1_delay_zero; + wire ch1_dly_irq_set; + wire decerr_i_reg; + wire dly_irq_reg_0; + wire dma_err; + wire [0:0]dmacr_i; + wire \dmacr_i_reg[0]_0 ; + wire \dmacr_i_reg[2]_0 ; + wire err; + wire err_d1; + wire err_d1_reg_0; + wire err_d1_reg_1; + wire err_d1_reg_2; + wire err_irq_i_1_n_0; + wire err_irq_reg_0; + wire halt_reset; + wire halted_clr_reg; + wire initial_frame; + wire introut01_out; + wire introut_i_1_n_0; + wire ioc_irq_reg_0; + wire irqdelay_wren_i; + wire irqthresh_wren_i; + wire m_axi_mm2s_aclk; + wire mask_fsync_out_i; + wire [1:0]mm2s_axi2ip_wrce; + wire mm2s_halt; + wire mm2s_halt_cmplt; + wire mm2s_ioc_irq_set; + wire p_13_out; + wire p_17_out; + wire p_1_in; + wire p_24_out; + wire p_45_out; + wire p_47_out; + wire p_50_out; + wire [18:0]p_71_out; + wire p_78_out; + wire prmry_in; + wire prmry_resetn_i_reg; + wire reset_counts_reg_0; + wire s_axis_cmd_tvalid_reg; + wire [0:0]s_axis_cmd_tvalid_reg_0; + wire s_soft_reset_i0; + wire slverr_i_reg; + wire soft_reset_d1_reg; + + FDRE #( + .INIT(1'b0)) + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[24] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[16]), + .Q(p_71_out[11]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[25] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[17]), + .Q(p_71_out[12]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[47] + FDRE #( + .INIT(1'b0)) + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[26] (.C(m_axi_mm2s_aclk), - .CE(E), - .D(D[32]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [32]), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[18]), + .Q(p_71_out[13]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[48] + FDRE #( + .INIT(1'b0)) + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[27] (.C(m_axi_mm2s_aclk), - .CE(E), - .D(D[33]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [33]), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[19]), + .Q(p_71_out[14]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[49] + FDRE #( + .INIT(1'b0)) + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[28] (.C(m_axi_mm2s_aclk), - .CE(E), - .D(D[34]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [34]), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[20]), + .Q(p_71_out[15]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[4] + FDRE #( + .INIT(1'b0)) + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[29] (.C(m_axi_mm2s_aclk), - .CE(E), - .D(D[4]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [4]), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[21]), + .Q(p_71_out[16]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[50] + FDRE #( + .INIT(1'b0)) + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[30] (.C(m_axi_mm2s_aclk), - .CE(E), - .D(D[35]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [35]), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[22]), + .Q(p_71_out[17]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[51] + FDRE #( + .INIT(1'b0)) + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31] (.C(m_axi_mm2s_aclk), - .CE(E), - .D(D[36]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [36]), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[23]), + .Q(p_71_out[18]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[52] + (* SOFT_HLUTNM = "soft_lutpair46" *) + LUT3 #( + .INIT(8'hA8)) + \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_1 + (.I0(mm2s_axi2ip_wrce[0]), + .I1(\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_2_n_0 ), + .I2(\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_3_n_0 ), + .O(\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_1_n_0 )); + LUT5 #( + .INIT(32'hFFFF6FF6)) + \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_2 + (.I0(D[16]), + .I1(p_71_out[11]), + .I2(D[17]), + .I3(p_71_out[12]), + .I4(\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_4_n_0 ), + .O(\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_2_n_0 )); + LUT5 #( + .INIT(32'hFFFF6FF6)) + \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_3 + (.I0(D[20]), + .I1(p_71_out[15]), + .I2(D[21]), + .I3(p_71_out[16]), + .I4(\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_5_n_0 ), + .O(\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_3_n_0 )); + LUT4 #( + .INIT(16'h6FF6)) + \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_4 + (.I0(p_71_out[18]), + .I1(D[23]), + .I2(p_71_out[17]), + .I3(D[22]), + .O(\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_4_n_0 )); + LUT4 #( + .INIT(16'h6FF6)) + \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_5 + (.I0(p_71_out[14]), + .I1(D[19]), + .I2(p_71_out[13]), + .I3(D[18]), + .O(\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_5_n_0 )); + FDRE #( + .INIT(1'b0)) + \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg (.C(m_axi_mm2s_aclk), - .CE(E), - .D(D[37]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [37]), + .CE(1'b1), + .D(\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_1_n_0 ), + .Q(irqdelay_wren_i), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[53] + FDSE #( + .INIT(1'b0)) + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[16] (.C(m_axi_mm2s_aclk), - .CE(E), - .D(D[38]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [38]), - .R(SR)); - FDRE \s_axis_cmd_tdata_reg[54] + .CE(mm2s_axi2ip_wrce[0]), + .D(D[8]), + .Q(p_71_out[3]), + .S(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18] )); + FDRE #( + .INIT(1'b0)) + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[17] (.C(m_axi_mm2s_aclk), - .CE(E), - .D(D[39]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [39]), - .R(SR)); - FDRE \s_axis_cmd_tdata_reg[55] + .CE(mm2s_axi2ip_wrce[0]), + .D(D[9]), + .Q(p_71_out[4]), + .R(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18] )); + FDRE #( + .INIT(1'b0)) + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[18] (.C(m_axi_mm2s_aclk), - .CE(E), - .D(D[40]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [40]), - .R(SR)); - FDRE \s_axis_cmd_tdata_reg[56] + .CE(mm2s_axi2ip_wrce[0]), + .D(D[10]), + .Q(p_71_out[5]), + .R(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18] )); + FDRE #( + .INIT(1'b0)) + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[19] (.C(m_axi_mm2s_aclk), - .CE(E), - .D(D[41]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [41]), - .R(SR)); - FDRE \s_axis_cmd_tdata_reg[57] + .CE(mm2s_axi2ip_wrce[0]), + .D(D[11]), + .Q(p_71_out[6]), + .R(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18] )); + FDRE #( + .INIT(1'b0)) + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[20] (.C(m_axi_mm2s_aclk), - .CE(E), - .D(D[42]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [42]), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[12]), + .Q(p_71_out[7]), + .R(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18] )); + FDRE #( + .INIT(1'b0)) + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[13]), + .Q(p_71_out[8]), + .R(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18] )); + FDRE #( + .INIT(1'b0)) + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[22] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[14]), + .Q(p_71_out[9]), + .R(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18] )); + FDRE #( + .INIT(1'b0)) + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[23] + (.C(m_axi_mm2s_aclk), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[15]), + .Q(p_71_out[10]), + .R(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18] )); + (* SOFT_HLUTNM = "soft_lutpair46" *) + LUT3 #( + .INIT(8'hA8)) + \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_1 + (.I0(mm2s_axi2ip_wrce[0]), + .I1(\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_2_n_0 ), + .I2(\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_3_n_0 ), + .O(\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_1_n_0 )); + LUT5 #( + .INIT(32'hFFFF6FF6)) + \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_2 + (.I0(D[8]), + .I1(p_71_out[3]), + .I2(D[9]), + .I3(p_71_out[4]), + .I4(\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_4_n_0 ), + .O(\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_2_n_0 )); + LUT5 #( + .INIT(32'hFFFF6FF6)) + \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_3 + (.I0(D[12]), + .I1(p_71_out[7]), + .I2(D[13]), + .I3(p_71_out[8]), + .I4(\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_5_n_0 ), + .O(\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_3_n_0 )); + LUT4 #( + .INIT(16'h6FF6)) + \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_4 + (.I0(p_71_out[10]), + .I1(D[15]), + .I2(p_71_out[9]), + .I3(D[14]), + .O(\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_4_n_0 )); + LUT4 #( + .INIT(16'h6FF6)) + \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_5 + (.I0(p_71_out[6]), + .I1(D[11]), + .I2(p_71_out[5]), + .I3(D[10]), + .O(\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_5_n_0 )); + FDRE #( + .INIT(1'b0)) + \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_1_n_0 ), + .Q(irqthresh_wren_i), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[58] + LUT4 #( + .INIT(16'hFFEF)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_2 + (.I0(soft_reset_d1_reg), + .I1(dma_err), + .I2(p_71_out[0]), + .I3(mm2s_halt), + .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFB)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_1 + (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]_0 ), + .I1(ch1_delay_cnt_en), + .I2(p_24_out), + .I3(irqdelay_wren_i), + .I4(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6] ), + .I5(p_17_out), + .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]_1 )); + LUT4 #( + .INIT(16'h4454)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_i_1 + (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]_0 ), + .I1(p_50_out), + .I2(ch1_delay_cnt_en), + .I3(p_17_out), + .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg )); + LUT3 #( + .INIT(8'hFE)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_i_2 + (.I0(ch1_dly_irq_set), + .I1(ch1_delay_zero), + .I2(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_i_3_n_0 ), + .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]_0 )); + (* SOFT_HLUTNM = "soft_lutpair45" *) + LUT5 #( + .INIT(32'hFFFBFFFF)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_i_3 + (.I0(mask_fsync_out_i), + .I1(p_47_out), + .I2(dly_irq_reg_0), + .I3(s_axis_cmd_tvalid_reg), + .I4(prmry_resetn_i_reg), + .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_i_3_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_3 + (.I0(p_17_out), + .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6] ), + .I2(irqdelay_wren_i), + .I3(p_24_out), + .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] )); + LUT5 #( + .INIT(32'h00010000)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_2 + (.I0(p_71_out[15]), + .I1(p_71_out[16]), + .I2(p_71_out[17]), + .I3(p_71_out[18]), + .I4(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_5_n_0 ), + .O(ch1_delay_zero)); + LUT4 #( + .INIT(16'h0001)) + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_5 + (.I0(p_71_out[12]), + .I1(p_71_out[11]), + .I2(p_71_out[14]), + .I3(p_71_out[13]), + .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF88F8)) + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_i_3 + (.I0(Q[3]), + .I1(ch1_dly_irq_set), + .I2(p_50_out), + .I3(p_45_out), + .I4(irqthresh_wren_i), + .I5(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6] ), + .O(p_13_out)); + LUT5 #( + .INIT(32'hFFFFFEEE)) + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_2 + (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6] ), + .I1(irqthresh_wren_i), + .I2(ch1_dly_irq_set), + .I3(Q[3]), + .I4(p_50_out), + .O(E)); + FDRE #( + .INIT(1'b0)) + \GEN_NOSYNCEN_BIT.dmacr_i_reg[15] (.C(m_axi_mm2s_aclk), - .CE(E), - .D(D[43]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [43]), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[7]), + .Q(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15] ), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[59] + LUT4 #( + .INIT(16'hDFDD)) + \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_1 + (.I0(prmry_resetn_i_reg), + .I1(s_axis_cmd_tvalid_reg), + .I2(initial_frame), + .I3(p_71_out[1]), + .O(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4] )); + LUT3 #( + .INIT(8'h01)) + \MM2S_ERR_FOR_IRQ.frm_store_i[4]_i_1 + (.I0(err_d1_reg_1), + .I1(err_d1_reg_2), + .I2(err_d1_reg_0), + .O(p_1_in)); + FDRE #( + .INIT(1'b0)) + \MM2S_ERR_FOR_IRQ.frm_store_i_reg[0] (.C(m_axi_mm2s_aclk), - .CE(E), - .D(D[44]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [44]), + .CE(p_1_in), + .D(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0 [0]), + .Q(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] [0]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[5] + FDRE #( + .INIT(1'b0)) + \MM2S_ERR_FOR_IRQ.frm_store_i_reg[1] (.C(m_axi_mm2s_aclk), - .CE(E), - .D(D[5]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [5]), + .CE(p_1_in), + .D(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0 [1]), + .Q(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] [1]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[60] + FDRE #( + .INIT(1'b0)) + \MM2S_ERR_FOR_IRQ.frm_store_i_reg[2] (.C(m_axi_mm2s_aclk), - .CE(E), - .D(D[45]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [45]), + .CE(p_1_in), + .D(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0 [2]), + .Q(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] [2]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[61] + FDRE #( + .INIT(1'b0)) + \MM2S_ERR_FOR_IRQ.frm_store_i_reg[3] (.C(m_axi_mm2s_aclk), - .CE(E), - .D(D[46]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [46]), + .CE(p_1_in), + .D(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0 [3]), + .Q(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] [3]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[62] + FDRE #( + .INIT(1'b0)) + \MM2S_ERR_FOR_IRQ.frm_store_i_reg[4] (.C(m_axi_mm2s_aclk), - .CE(E), - .D(D[47]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [47]), + .CE(p_1_in), + .D(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0 [4]), + .Q(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] [4]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[63] + FDRE #( + .INIT(1'b0)) + \M_GEN_DMACR_REGISTER.dmacr_i_reg[12] (.C(m_axi_mm2s_aclk), - .CE(E), - .D(D[48]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [48]), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[4]), + .Q(Q[2]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[6] + FDRE #( + .INIT(1'b0)) + \M_GEN_DMACR_REGISTER.dmacr_i_reg[13] (.C(m_axi_mm2s_aclk), - .CE(E), - .D(D[6]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [6]), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[5]), + .Q(Q[3]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[7] + FDRE #( + .INIT(1'b0)) + \M_GEN_DMACR_REGISTER.dmacr_i_reg[14] (.C(m_axi_mm2s_aclk), - .CE(E), - .D(D[7]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [7]), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[6]), + .Q(Q[4]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[8] + FDRE #( + .INIT(1'b0)) + \M_GEN_DMACR_REGISTER.dmacr_i_reg[4] (.C(m_axi_mm2s_aclk), - .CE(E), - .D(D[8]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [8]), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[1]), + .Q(p_71_out[2]), .R(SR)); - FDRE \s_axis_cmd_tdata_reg[9] + FDRE #( + .INIT(1'b0)) + \M_GEN_DMACR_REGISTER.dmacr_i_reg[5] (.C(m_axi_mm2s_aclk), - .CE(E), - .D(D[9]), - .Q(\sig_addr_cntr_lsh_kh_reg[31] [9]), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[2]), + .Q(Q[0]), .R(SR)); - FDRE s_axis_cmd_tvalid_reg + FDRE #( + .INIT(1'b0)) + \M_GEN_DMACR_REGISTER.dmacr_i_reg[6] (.C(m_axi_mm2s_aclk), - .CE(E), - .D(\GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg_0 ), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg ), + .CE(mm2s_axi2ip_wrce[0]), + .D(D[3]), + .Q(Q[1]), .R(SR)); FDRE #( .INIT(1'b0)) - slverr_i_reg + dly_irq_reg (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(\INFERRED_GEN.cnt_i_reg[2]_0 ), - .Q(p_53_out), - .R(p_0_in)); + .D(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13] ), + .Q(dly_irq_reg_0), + .R(SR)); FDRE #( .INIT(1'b0)) - sts_tready_reg + dma_decerr_reg (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(out), - .Q(\cmnds_queued_reg[7] ), - .R(1'b0)); -endmodule - -(* ORIG_REF_NAME = "axi_vdma_fsync_gen" *) -module Arty_Z7_20_axi_vdma_0_0_axi_vdma_fsync_gen - (p_23_out, - mask_fsync_out_i, - p_45_out, - prmry_in_xored, - SR, - p_36_out, - m_axi_mm2s_aclk, - p_2_out, - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] , - p_46_out, - p_68_out, - p_in_d1_cdc_from); - output p_23_out; - output mask_fsync_out_i; - output p_45_out; - output prmry_in_xored; - input [0:0]SR; - input p_36_out; - input m_axi_mm2s_aclk; - input p_2_out; - input \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] ; - input p_46_out; - input [0:0]p_68_out; - input p_in_d1_cdc_from; - - wire \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] ; - wire [0:0]SR; - wire all_idle_d1; - wire all_idle_d2; - wire m_axi_mm2s_aclk; - wire mask_fsync_out_i; - wire p_22_out; - wire p_23_out; - wire p_2_out; - wire p_36_out; - wire p_45_out; - wire p_46_out; - wire [0:0]p_68_out; - wire p_8_out; - wire p_in_d1_cdc_from; - wire prmry_in_xored; - - LUT2 #( - .INIT(4'h6)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__5 - (.I0(p_22_out), - .I1(p_in_d1_cdc_from), - .O(prmry_in_xored)); + .D(decerr_i_reg), + .Q(err_d1_reg_2), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_FREE_RUN_MODE.all_idle_d1_reg + dma_interr_reg (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(p_36_out), - .Q(all_idle_d1), + .D(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] ), + .Q(err_d1_reg_0), .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_FREE_RUN_MODE.all_idle_d2_reg + dma_slverr_reg (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(all_idle_d1), - .Q(all_idle_d2), + .D(slverr_i_reg), + .Q(err_d1_reg_1), .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair47" *) LUT3 #( - .INIT(8'h40)) - \GEN_FREE_RUN_MODE.frame_sync_i_i_1 - (.I0(all_idle_d2), - .I1(all_idle_d1), - .I2(p_68_out), - .O(p_8_out)); + .INIT(8'hF8)) + \dmacr_i[0]_i_2 + (.I0(mm2s_ioc_irq_set), + .I1(p_71_out[2]), + .I2(soft_reset_d1_reg), + .O(\dmacr_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) - \GEN_FREE_RUN_MODE.frame_sync_i_reg + \dmacr_i_reg[0] (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(p_8_out), - .Q(p_23_out), - .R(SR)); - FDRE \GEN_FREE_RUN_MODE.frame_sync_out_reg + .D(dmacr_i), + .Q(p_71_out[0]), + .R(1'b0)); + FDSE #( + .INIT(1'b0)) + \dmacr_i_reg[1] (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(p_2_out), - .Q(p_22_out), - .R(SR)); + .CE(mm2s_axi2ip_wrce[0]), + .D(D[0]), + .Q(p_71_out[1]), + .S(SR)); FDRE #( .INIT(1'b0)) - \GEN_FREE_RUN_MODE.mask_fsync_out_i_reg + \dmacr_i_reg[2] (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] ), - .Q(mask_fsync_out_i), + .D(\dmacr_i_reg[2]_0 ), + .Q(soft_reset_d1_reg), .R(1'b0)); - LUT2 #( - .INIT(4'h8)) - \MASTER_MODE_FRAME_CNT.valid_frame_sync_d1_i_1 - (.I0(p_23_out), - .I1(p_46_out), - .O(p_45_out)); -endmodule - -(* ORIG_REF_NAME = "axi_vdma_genlock_mngr" *) -module Arty_Z7_20_axi_vdma_0_0_axi_vdma_genlock_mngr - (p_44_out, - in0, - p_0_in, - valid_frame_sync_d2, - m_axi_mm2s_aclk, - p_68_out, - out, - p_67_out, - Q); - output p_44_out; - output [0:0]in0; - input p_0_in; - input valid_frame_sync_d2; - input m_axi_mm2s_aclk; - input [0:0]p_68_out; - input out; - input p_67_out; - input [4:0]Q; - - wire \GENLOCK_FOR_MASTER.mstr_reverse_order_i_1_n_0 ; - wire \GENLOCK_FOR_MASTER.mstr_reverse_order_i_2_n_0 ; - wire [4:0]Q; - wire [0:0]in0; - wire m_axi_mm2s_aclk; - wire mstr_reverse_order; - wire mstr_reverse_order_d1; - wire mstr_reverse_order_d2; - wire out; - wire p_0_in; - wire p_44_out; - wire p_67_out; - wire [0:0]p_68_out; - wire s_frame_ptr_out; - wire valid_frame_sync_d2; - - LUT1 #( - .INIT(2'h1)) - \GENLOCK_FOR_MASTER.frame_ptr_out[0]_i_1 - (.I0(mstr_reverse_order_d2), - .O(s_frame_ptr_out)); - FDRE \GENLOCK_FOR_MASTER.frame_ptr_out_reg[0] + LUT3 #( + .INIT(8'hFE)) + err_d1_i_1 + (.I0(err_d1_reg_0), + .I1(err_d1_reg_2), + .I2(err_d1_reg_1), + .O(err)); + FDRE #( + .INIT(1'b0)) + err_d1_reg (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(s_frame_ptr_out), - .Q(in0), - .R(p_0_in)); - FDSE #( + .D(err), + .Q(err_d1), + .R(SR)); + LUT5 #( + .INIT(32'h5DFF0C0C)) + err_irq_i_1 + (.I0(D[6]), + .I1(err), + .I2(err_d1), + .I3(mm2s_axi2ip_wrce[1]), + .I4(err_irq_reg_0), + .O(err_irq_i_1_n_0)); + FDRE #( .INIT(1'b0)) - \GENLOCK_FOR_MASTER.mstr_reverse_order_d1_reg + err_irq_reg (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(mstr_reverse_order), - .Q(mstr_reverse_order_d1), - .S(p_0_in)); - FDSE #( + .D(err_irq_i_1_n_0), + .Q(err_irq_reg_0), + .R(SR)); + FDRE #( .INIT(1'b0)) - \GENLOCK_FOR_MASTER.mstr_reverse_order_d2_reg + halted_reg (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(mstr_reverse_order_d1), - .Q(mstr_reverse_order_d2), - .S(p_0_in)); - LUT6 #( - .INIT(64'hFFFFFFFF6AAAFFFF)) - \GENLOCK_FOR_MASTER.mstr_reverse_order_i_1 - (.I0(mstr_reverse_order), - .I1(\GENLOCK_FOR_MASTER.mstr_reverse_order_i_2_n_0 ), - .I2(valid_frame_sync_d2), - .I3(p_68_out), - .I4(out), - .I5(p_67_out), - .O(\GENLOCK_FOR_MASTER.mstr_reverse_order_i_1_n_0 )); - LUT5 #( - .INIT(32'h00000001)) - \GENLOCK_FOR_MASTER.mstr_reverse_order_i_2 - (.I0(Q[4]), - .I1(Q[2]), - .I2(Q[1]), - .I3(Q[0]), + .D(halted_clr_reg), + .Q(s_axis_cmd_tvalid_reg), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair47" *) + LUT3 #( + .INIT(8'h08)) + introut_i_1 + (.I0(introut01_out), + .I1(prmry_resetn_i_reg), + .I2(soft_reset_d1_reg), + .O(introut_i_1_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + introut_i_2 + (.I0(err_irq_reg_0), + .I1(Q[4]), + .I2(ioc_irq_reg_0), + .I3(Q[2]), .I4(Q[3]), - .O(\GENLOCK_FOR_MASTER.mstr_reverse_order_i_2_n_0 )); + .I5(dly_irq_reg_0), + .O(introut01_out)); + FDRE introut_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(introut_i_1_n_0), + .Q(p_78_out), + .R(1'b0)); FDRE #( .INIT(1'b0)) - \GENLOCK_FOR_MASTER.mstr_reverse_order_reg + ioc_irq_reg (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(\GENLOCK_FOR_MASTER.mstr_reverse_order_i_1_n_0 ), - .Q(mstr_reverse_order), - .R(1'b0)); + .D(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12] ), + .Q(ioc_irq_reg_0), + .R(SR)); FDRE #( .INIT(1'b0)) - \GENLOCK_FOR_MASTER.mstrfrm_tstsync_d1_reg + reset_counts_reg (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(valid_frame_sync_d2), - .Q(p_44_out), - .R(p_0_in)); + .D(reset_counts_reg_0), + .Q(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6] ), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair45" *) + LUT2 #( + .INIT(4'hB)) + \s_axis_cmd_tdata[63]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(prmry_resetn_i_reg), + .O(s_axis_cmd_tvalid_reg_0)); + LUT4 #( + .INIT(16'hA800)) + s_soft_reset_i_i_1 + (.I0(soft_reset_d1_reg), + .I1(mm2s_halt_cmplt), + .I2(halt_reset), + .I3(prmry_in), + .O(s_soft_reset_i0)); endmodule -(* ORIG_REF_NAME = "axi_vdma_intrpt" *) -module Arty_Z7_20_axi_vdma_0_0_axi_vdma_intrpt - (mm2s_dly_irq_set, - p_10_out, - ch1_delay_cnt_en, - mm2s_ioc_irq_set, +(* ORIG_REF_NAME = "axi_vdma_register" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_register__parameterized0 + (s2mm_dmacr, + soft_reset_d1_reg, + reset_counts, + irqdelay_wren_i, + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from , + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_0 , + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_1 , + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_2 , + \GEN_FOR_FLUSH.fsize_err_reg_0 , + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_3 , + err_d1_reg_0, + ioc_irq_reg_0, + dly_irq_reg_0, + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_4 , + err_d1_reg_1, + s2mm_ip2axi_introut, + s_soft_reset_i0, + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6] , + ch2_delay_zero, + p_6_out, Q, - ch1_ioc_irq_set_i__0, - \GEN_FREE_RUN_MODE.mask_fsync_out_i_reg , - \GEN_FREE_RUN_MODE.mask_fsync_out_i_reg_0 , + \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg_0 , + \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg_0 , + err_d1_reg_2, + err_irq_reg_0, + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] , + s_axis_cmd_tvalid_reg, + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6]_0 , + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4] , + m_axi_s2mm_aclk, SR, - m_axi_mm2s_aclk, - \MASTER_MODE_FRAME_CNT.tstvect_fsync_reg , + s2mm_axi2ip_wrce, D, - p_68_out, - p_6_out__1, - p_23_out, - p_46_out, - ch1_delay_zero__6, - p_17_out, - p_49_out, - out, - mask_fsync_out_i, + \dmacr_i_reg[2]_0 , + reset_counts_reg_0, + p_15_out, + p_14_out, + halted_clr_reg, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4] , + slverr_i_reg, + decerr_i_reg, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[7] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[8] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[11] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[12] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[13] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[15] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4]_0 , + s2mm_halt_cmplt, + halt_reset, + prmry_in, prmry_resetn_i_reg, - E, - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ); - output mm2s_dly_irq_set; - output p_10_out; - output ch1_delay_cnt_en; - output mm2s_ioc_irq_set; - output [7:0]Q; - output ch1_ioc_irq_set_i__0; - output [7:0]\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg ; - output \GEN_FREE_RUN_MODE.mask_fsync_out_i_reg_0 ; + ch2_dly_irq_set, + s2mm_tstvect_fsync, + s2mm_valid_frame_sync, + s2mm_ioc_irq_set, + s2mm_valid_video_prmtrs, + mask_fsync_out_i, + s2mm_stop, + num_fstore_minus1, + initial_frame, + ch2_delay_cnt_en, + s2mm_cdc2dmac_fsync, + s2mm_packet_sof, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18] , + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]_0 ); + output [22:0]s2mm_dmacr; + output soft_reset_d1_reg; + output reset_counts; + output irqdelay_wren_i; + output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ; + output \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_0 ; + output \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_1 ; + output \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_2 ; + output \GEN_FOR_FLUSH.fsize_err_reg_0 ; + output \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_3 ; + output err_d1_reg_0; + output ioc_irq_reg_0; + output dly_irq_reg_0; + output \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_4 ; + output err_d1_reg_1; + output s2mm_ip2axi_introut; + output s_soft_reset_i0; + output \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6] ; + output ch2_delay_zero; + output p_6_out; + output [6:0]Q; + output \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg_0 ; + output \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg_0 ; + output [3:0]err_d1_reg_2; + output err_irq_reg_0; + output [0:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] ; + output [0:0]s_axis_cmd_tvalid_reg; + output [0:0]\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6]_0 ; + output [4:0]\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4] ; + input m_axi_s2mm_aclk; input [0:0]SR; - input m_axi_mm2s_aclk; - input \MASTER_MODE_FRAME_CNT.tstvect_fsync_reg ; - input [0:0]D; - input [15:0]p_68_out; - input p_6_out__1; - input p_23_out; - input p_46_out; - input ch1_delay_zero__6; - input p_17_out; - input p_49_out; - input out; + input [2:0]s2mm_axi2ip_wrce; + input [30:0]D; + input \dmacr_i_reg[2]_0 ; + input reset_counts_reg_0; + input p_15_out; + input p_14_out; + input halted_clr_reg; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4] ; + input slverr_i_reg; + input decerr_i_reg; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[7] ; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[8] ; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[11] ; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[12] ; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[13] ; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[15] ; + input \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4]_0 ; + input s2mm_halt_cmplt; + input halt_reset; + input prmry_in; + input prmry_resetn_i_reg; + input ch2_dly_irq_set; + input s2mm_tstvect_fsync; + input s2mm_valid_frame_sync; + input s2mm_ioc_irq_set; + input s2mm_valid_video_prmtrs; input mask_fsync_out_i; - input [0:0]prmry_resetn_i_reg; - input [0:0]E; - input [0:0]\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ; + input s2mm_stop; + input [0:0]num_fstore_minus1; + input initial_frame; + input ch2_delay_cnt_en; + input s2mm_cdc2dmac_fsync; + input s2mm_packet_sof; + input [0:0]\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18] ; + input [4:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]_0 ; - wire [0:0]D; - wire [0:0]E; - wire [0:0]\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ; - wire \GEN_FREE_RUN_MODE.mask_fsync_out_i_i_2_n_0 ; - wire \GEN_FREE_RUN_MODE.mask_fsync_out_i_i_3_n_0 ; - wire [7:0]\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg ; - wire \GEN_FREE_RUN_MODE.mask_fsync_out_i_reg_0 ; - wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[1]_i_2_n_0 ; - wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_5_n_0 ; - wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0 ; - wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_3_n_0 ; - wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_5_n_0 ; - wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_6_n_0 ; - wire \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_i_1_n_0 ; - wire \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[3]_i_2_n_0 ; - wire \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[4]_i_2_n_0 ; - wire \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[5]_i_2_n_0 ; - wire \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5_n_0 ; - wire \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_7_n_0 ; - wire [6:0]L; - wire \MASTER_MODE_FRAME_CNT.tstvect_fsync_reg ; - wire [7:0]Q; + wire [30:0]D; + wire [0:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] ; + wire [4:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]_0 ; + wire \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_6_n_0 ; + wire \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg_0 ; + wire \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_6_n_0 ; + wire \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg_0 ; + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ; + wire \GEN_FOR_FLUSH.fsize_err_reg_0 ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6] ; + wire [0:0]\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6]_0 ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_5_n_0 ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[11] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[12] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[13] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[15] ; + wire [0:0]\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4]_0 ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[7] ; + wire \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[8] ; + wire [4:0]\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4] ; + wire [6:0]Q; + wire \S2MM_ERR_FOR_IRQ.frm_store_i[4]_i_1_n_0 ; + wire \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_0 ; + wire \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_1 ; + wire \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_2 ; + wire \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_3 ; + wire \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_4 ; wire [0:0]SR; - wire ch1_delay_cnt_en; - wire ch1_delay_zero__6; - wire [6:0]ch1_dly_fast_cnt; - wire ch1_dly_fast_incr; - wire ch1_ioc_irq_set_i__0; - wire m_axi_mm2s_aclk; + wire ch2_delay_cnt_en; + wire ch2_delay_zero; + wire ch2_dly_irq_set; + wire decerr_i_reg; + wire dly_irq_reg_0; + wire [0:0]dmacr_i; + wire \dmacr_i[0]_i_2__0_n_0 ; + wire \dmacr_i_reg[2]_0 ; + wire err; + wire err_d1; + wire err_d1_i_2_n_0; + wire err_d1_reg_0; + wire err_d1_reg_1; + wire [3:0]err_d1_reg_2; + wire err_irq_i_1__0_n_0; + wire err_irq_reg_0; + wire halt_reset; + wire halted_clr_reg; + wire initial_frame; + wire introut07_out; + wire introut_i_1__0_n_0; + wire ioc_irq_reg_0; + wire irqdelay_wren_i; + wire irqthresh_wren_i; + wire m_axi_s2mm_aclk; wire mask_fsync_out_i; - wire mm2s_dly_irq_set; - wire mm2s_ioc_irq_set; - wire out; - wire p_10_out; - wire p_17_out; - wire p_23_out; - wire [7:1]p_2_in; - wire p_46_out; - wire p_49_out; - wire [15:0]p_68_out; - wire p_6_out__1; - wire p_8_in__14; - wire [7:0]plusOp; - wire [0:0]prmry_resetn_i_reg; + wire [0:0]num_fstore_minus1; + wire p_14_out; + wire p_15_out; + wire p_6_out; + wire prmry_in; + wire prmry_resetn_i_reg; + wire reset_counts; + wire reset_counts_reg_0; + wire [2:0]s2mm_axi2ip_wrce; + wire s2mm_cdc2dmac_fsync; + wire s2mm_dlyirq_dsble; + wire [22:0]s2mm_dmacr; + wire s2mm_halt_cmplt; + wire s2mm_ioc_irq_set; + wire s2mm_ip2axi_introut; + wire s2mm_packet_sof; + wire s2mm_stop; + wire s2mm_tstvect_fsync; + wire s2mm_valid_frame_sync; + wire s2mm_valid_video_prmtrs; + wire [0:0]s_axis_cmd_tvalid_reg; + wire s_soft_reset_i0; + wire slverr_i_reg; + wire soft_reset_d1_reg; - LUT6 #( - .INIT(64'h00000100FF000100)) - \GEN_FREE_RUN_MODE.mask_fsync_out_i_i_1 - (.I0(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [7]), - .I1(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [6]), - .I2(\GEN_FREE_RUN_MODE.mask_fsync_out_i_i_2_n_0 ), - .I3(out), - .I4(mask_fsync_out_i), - .I5(mm2s_ioc_irq_set), - .O(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg_0 )); - LUT5 #( - .INIT(32'hFFFFFFFE)) - \GEN_FREE_RUN_MODE.mask_fsync_out_i_i_2 - (.I0(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [3]), - .I1(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [2]), - .I2(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [5]), - .I3(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [4]), - .I4(\GEN_FREE_RUN_MODE.mask_fsync_out_i_i_3_n_0 ), - .O(\GEN_FREE_RUN_MODE.mask_fsync_out_i_i_2_n_0 )); - LUT5 #( - .INIT(32'hDFFFFFFF)) - \GEN_FREE_RUN_MODE.mask_fsync_out_i_i_3 - (.I0(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [0]), - .I1(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [1]), - .I2(p_68_out[0]), - .I3(p_23_out), - .I4(p_46_out), - .O(\GEN_FREE_RUN_MODE.mask_fsync_out_i_i_3_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair43" *) - LUT3 #( - .INIT(8'h32)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[0]_i_1 - (.I0(L[1]), - .I1(L[0]), - .I2(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[1]_i_2_n_0 ), - .O(ch1_dly_fast_cnt[0])); - (* SOFT_HLUTNM = "soft_lutpair43" *) - LUT3 #( - .INIT(8'h98)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[1]_i_1 - (.I0(L[0]), - .I1(L[1]), - .I2(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[1]_i_2_n_0 ), - .O(ch1_dly_fast_cnt[1])); - LUT5 #( - .INIT(32'hFFFFFFFE)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[1]_i_2 - (.I0(L[5]), - .I1(L[3]), - .I2(L[2]), - .I3(L[4]), - .I4(L[6]), - .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[1]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair44" *) - LUT3 #( - .INIT(8'hA9)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[2]_i_1 - (.I0(L[2]), - .I1(L[0]), - .I2(L[1]), - .O(ch1_dly_fast_cnt[2])); - (* SOFT_HLUTNM = "soft_lutpair38" *) - LUT4 #( - .INIT(16'hFE01)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[3]_i_1 - (.I0(L[0]), - .I1(L[1]), - .I2(L[2]), - .I3(L[3]), - .O(ch1_dly_fast_cnt[3])); - (* SOFT_HLUTNM = "soft_lutpair38" *) + FDRE #( + .INIT(1'b0)) + \DMA_IRQ_MASK_GEN.dma_irq_mask_i_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[2]), + .D(D[0]), + .Q(err_d1_reg_2[0]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \DMA_IRQ_MASK_GEN.dma_irq_mask_i_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[2]), + .D(D[1]), + .Q(err_d1_reg_2[1]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \DMA_IRQ_MASK_GEN.dma_irq_mask_i_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[2]), + .D(D[2]), + .Q(err_d1_reg_2[2]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \DMA_IRQ_MASK_GEN.dma_irq_mask_i_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[2]), + .D(D[3]), + .Q(err_d1_reg_2[3]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \DM_GEN_SYNCEN_BIT.dmacr_i_reg[15] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[14]), + .Q(s2mm_dmacr[6]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \DM_GEN_SYNCEN_BIT.dmacr_i_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[3]), + .Q(s2mm_dmacr[2]), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair86" *) LUT5 #( - .INIT(32'hFFFE0001)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[4]_i_1 - (.I0(L[0]), - .I1(L[1]), - .I2(L[3]), - .I3(L[2]), - .I4(L[4]), - .O(ch1_dly_fast_cnt[4])); - LUT6 #( - .INIT(64'hFFFFFFFE00000001)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[5]_i_1 - (.I0(L[0]), - .I1(L[1]), - .I2(L[4]), - .I3(L[2]), - .I4(L[3]), - .I5(L[5]), - .O(ch1_dly_fast_cnt[5])); - LUT6 #( - .INIT(64'hFFFFFFFE00000001)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_2 - (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_5_n_0 ), - .I1(L[5]), - .I2(L[3]), - .I3(L[2]), - .I4(L[4]), - .I5(L[6]), - .O(ch1_dly_fast_cnt[6])); - (* SOFT_HLUTNM = "soft_lutpair44" *) - LUT2 #( - .INIT(4'hE)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_5 - (.I0(L[0]), - .I1(L[1]), - .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_5_n_0 )); + .INIT(32'hDFDFFFDF)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_1 + (.I0(prmry_resetn_i_reg), + .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ), + .I2(num_fstore_minus1), + .I3(s2mm_dmacr[1]), + .I4(initial_frame), + .O(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] )); FDRE #( .INIT(1'b0)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[0] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(ch1_dly_fast_cnt[0]), - .Q(L[0]), + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[24] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[23]), + .Q(s2mm_dmacr[15]), .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(ch1_dly_fast_cnt[1]), - .Q(L[1]), + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[25] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[24]), + .Q(s2mm_dmacr[16]), .R(SR)); - FDSE #( + FDRE #( .INIT(1'b0)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(ch1_dly_fast_cnt[2]), - .Q(L[2]), - .S(SR)); - FDSE #( + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[26] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[25]), + .Q(s2mm_dmacr[17]), + .R(SR)); + FDRE #( .INIT(1'b0)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[3] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(ch1_dly_fast_cnt[3]), - .Q(L[3]), - .S(SR)); - FDSE #( + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[27] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[26]), + .Q(s2mm_dmacr[18]), + .R(SR)); + FDRE #( .INIT(1'b0)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[4] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(ch1_dly_fast_cnt[4]), - .Q(L[4]), - .S(SR)); - FDSE #( + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[28] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[27]), + .Q(s2mm_dmacr[19]), + .R(SR)); + FDRE #( .INIT(1'b0)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[5] - (.C(m_axi_mm2s_aclk), + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[29] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[28]), + .Q(s2mm_dmacr[20]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[30] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[29]), + .Q(s2mm_dmacr[21]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[30]), + .Q(s2mm_dmacr[22]), + .R(SR)); + LUT6 #( + .INIT(64'h8CC8CCCCCCCC8CC8)) + \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_5__0 + (.I0(\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_6_n_0 ), + .I1(s2mm_axi2ip_wrce[0]), + .I2(s2mm_dmacr[22]), + .I3(D[30]), + .I4(s2mm_dmacr[21]), + .I5(D[29]), + .O(\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg_0 )); + LUT2 #( + .INIT(4'h2)) + \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_6 + (.I0(s2mm_dmacr[20]), + .I1(D[28]), + .O(\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_6_n_0 )); + FDRE #( + .INIT(1'b0)) + \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(ch1_dly_fast_cnt[5]), - .Q(L[5]), - .S(SR)); + .D(p_15_out), + .Q(irqdelay_wren_i), + .R(SR)); FDSE #( .INIT(1'b0)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(ch1_dly_fast_cnt[6]), - .Q(L[6]), - .S(SR)); + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[16] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[15]), + .Q(s2mm_dmacr[7]), + .S(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18] )); + FDRE #( + .INIT(1'b0)) + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[17] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[16]), + .Q(s2mm_dmacr[8]), + .R(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18] )); + FDRE #( + .INIT(1'b0)) + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[18] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[17]), + .Q(s2mm_dmacr[9]), + .R(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18] )); + FDRE #( + .INIT(1'b0)) + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[19] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[18]), + .Q(s2mm_dmacr[10]), + .R(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18] )); + FDRE #( + .INIT(1'b0)) + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[20] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[19]), + .Q(s2mm_dmacr[11]), + .R(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18] )); + FDRE #( + .INIT(1'b0)) + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[20]), + .Q(s2mm_dmacr[12]), + .R(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18] )); + FDRE #( + .INIT(1'b0)) + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[22] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[21]), + .Q(s2mm_dmacr[13]), + .R(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18] )); + FDRE #( + .INIT(1'b0)) + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[23] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[22]), + .Q(s2mm_dmacr[14]), + .R(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18] )); LUT6 #( - .INIT(64'h0000000000000001)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_i_1 - (.I0(L[6]), - .I1(L[4]), - .I2(L[2]), - .I3(L[3]), - .I4(L[5]), - .I5(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_5_n_0 ), - .O(ch1_dly_fast_incr)); + .INIT(64'h8CC8CCCCCCCC8CC8)) + \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_5__0 + (.I0(\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_6_n_0 ), + .I1(s2mm_axi2ip_wrce[0]), + .I2(s2mm_dmacr[14]), + .I3(D[22]), + .I4(s2mm_dmacr[13]), + .I5(D[21]), + .O(\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg_0 )); + LUT2 #( + .INIT(4'h2)) + \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_6 + (.I0(s2mm_dmacr[12]), + .I1(D[20]), + .O(\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_6_n_0 )); FDRE #( .INIT(1'b0)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg - (.C(m_axi_mm2s_aclk), + \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(ch1_dly_fast_incr), - .Q(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0 ), + .D(p_14_out), + .Q(irqthresh_wren_i), .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg - (.C(m_axi_mm2s_aclk), + \GEN_FOR_FLUSH.fsize_err_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(\MASTER_MODE_FRAME_CNT.tstvect_fsync_reg ), - .Q(ch1_delay_cnt_en), - .R(1'b0)); - LUT1 #( - .INIT(2'h1)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[0]_i_1 - (.I0(Q[0]), - .O(plusOp[0])); - (* SOFT_HLUTNM = "soft_lutpair45" *) - LUT2 #( - .INIT(4'h6)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[1]_i_1 - (.I0(Q[0]), - .I1(Q[1]), - .O(plusOp[1])); - (* SOFT_HLUTNM = "soft_lutpair45" *) - LUT3 #( - .INIT(8'h78)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[2]_i_1 - (.I0(Q[0]), - .I1(Q[1]), - .I2(Q[2]), - .O(plusOp[2])); - (* SOFT_HLUTNM = "soft_lutpair40" *) + .D(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[7] ), + .Q(\GEN_FOR_FLUSH.fsize_err_reg_0 ), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[11] ), + .Q(err_d1_reg_0), + .R(SR)); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFB)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[6]_i_1 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6] ), + .I1(ch2_delay_cnt_en), + .I2(irqdelay_wren_i), + .I3(s2mm_cdc2dmac_fsync), + .I4(reset_counts), + .I5(s2mm_packet_sof), + .O(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6]_0 )); LUT4 #( - .INIT(16'h7F80)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[3]_i_1 - (.I0(Q[1]), - .I1(Q[0]), - .I2(Q[2]), - .I3(Q[3]), - .O(plusOp[3])); - (* SOFT_HLUTNM = "soft_lutpair40" *) + .INIT(16'hFFEF)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_i_2 + (.I0(ch2_delay_zero), + .I1(s2mm_dlyirq_dsble), + .I2(prmry_resetn_i_reg), + .I3(ch2_dly_irq_set), + .O(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6] )); + LUT4 #( + .INIT(16'hFFEF)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_i_3 + (.I0(dly_irq_reg_0), + .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ), + .I2(s2mm_valid_video_prmtrs), + .I3(mask_fsync_out_i), + .O(s2mm_dlyirq_dsble)); LUT5 #( - .INIT(32'h7FFF8000)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[4]_i_1 - (.I0(Q[2]), - .I1(Q[0]), - .I2(Q[1]), - .I3(Q[3]), - .I4(Q[4]), - .O(plusOp[4])); - LUT6 #( - .INIT(64'h7FFFFFFF80000000)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[5]_i_1 - (.I0(Q[3]), - .I1(Q[1]), - .I2(Q[0]), - .I3(Q[2]), - .I4(Q[4]), - .I5(Q[5]), - .O(plusOp[5])); - (* SOFT_HLUTNM = "soft_lutpair42" *) - LUT2 #( - .INIT(4'h6)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[6]_i_1 - (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_3_n_0 ), - .I1(Q[6]), - .O(plusOp[6])); - (* SOFT_HLUTNM = "soft_lutpair42" *) - LUT3 #( - .INIT(8'h78)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_2 - (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_3_n_0 ), - .I1(Q[6]), - .I2(Q[7]), - .O(plusOp[7])); + .INIT(32'h00010000)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_2 + (.I0(s2mm_dmacr[19]), + .I1(s2mm_dmacr[20]), + .I2(s2mm_dmacr[21]), + .I3(s2mm_dmacr[22]), + .I4(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_5_n_0 ), + .O(ch2_delay_zero)); + LUT4 #( + .INIT(16'h0001)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_5 + (.I0(s2mm_dmacr[16]), + .I1(s2mm_dmacr[15]), + .I2(s2mm_dmacr[18]), + .I3(s2mm_dmacr[17]), + .O(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_5_n_0 )); LUT6 #( - .INIT(64'h8000000000000000)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_3 + .INIT(64'hFFFFFFFFFFFF88F8)) + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_4 (.I0(Q[5]), - .I1(Q[3]), - .I2(Q[1]), - .I3(Q[0]), - .I4(Q[2]), - .I5(Q[4]), - .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_3_n_0 )); + .I1(ch2_dly_irq_set), + .I2(s2mm_tstvect_fsync), + .I3(s2mm_valid_frame_sync), + .I4(reset_counts), + .I5(irqthresh_wren_i), + .O(p_6_out)); + FDRE #( + .INIT(1'b0)) + \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[9]), + .Q(Q[2]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[10]), + .Q(Q[3]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[11]), + .Q(Q[4]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[13] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[12]), + .Q(Q[5]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[13]), + .Q(Q[6]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[4]), + .Q(s2mm_dmacr[3]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[5]), + .Q(s2mm_dmacr[4]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0 ), - .D(plusOp[0]), + \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[6]), + .Q(s2mm_dmacr[5]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[7]), .Q(Q[0]), - .R(\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out )); + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0 ), - .D(plusOp[1]), + \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[8]), .Q(Q[1]), - .R(\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out )); + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0 ), - .D(plusOp[2]), - .Q(Q[2]), - .R(\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out )); + \S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4]_0 ), + .Q(err_d1_reg_1), + .R(SR)); + LUT5 #( + .INIT(32'h00000001)) + \S2MM_ERR_FOR_IRQ.frm_store_i[4]_i_1 + (.I0(\S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_0 ), + .I1(\S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_3 ), + .I2(\S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_4 ), + .I3(\S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_2 ), + .I4(\S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_1 ), + .O(\S2MM_ERR_FOR_IRQ.frm_store_i[4]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(\S2MM_ERR_FOR_IRQ.frm_store_i[4]_i_1_n_0 ), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]_0 [0]), + .Q(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4] [0]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[3] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0 ), - .D(plusOp[3]), - .Q(Q[3]), - .R(\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out )); + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(\S2MM_ERR_FOR_IRQ.frm_store_i[4]_i_1_n_0 ), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]_0 [1]), + .Q(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4] [1]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[4] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0 ), - .D(plusOp[4]), - .Q(Q[4]), - .R(\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out )); + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(\S2MM_ERR_FOR_IRQ.frm_store_i[4]_i_1_n_0 ), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]_0 [2]), + .Q(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4] [2]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[5] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0 ), - .D(plusOp[5]), - .Q(Q[5]), - .R(\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out )); + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(\S2MM_ERR_FOR_IRQ.frm_store_i[4]_i_1_n_0 ), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]_0 [3]), + .Q(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4] [3]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[6] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0 ), - .D(plusOp[6]), - .Q(Q[6]), - .R(\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out )); + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(\S2MM_ERR_FOR_IRQ.frm_store_i[4]_i_1_n_0 ), + .D(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]_0 [4]), + .Q(\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4] [4]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0 ), - .D(plusOp[7]), - .Q(Q[7]), - .R(\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out )); - LUT4 #( - .INIT(16'h1000)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_1 - (.I0(ch1_delay_zero__6), - .I1(p_17_out), - .I2(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0 ), - .I3(p_8_in__14), - .O(p_10_out)); - LUT6 #( - .INIT(64'h9009000000000000)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_3 - (.I0(p_68_out[15]), - .I1(Q[7]), - .I2(p_68_out[14]), - .I3(Q[6]), - .I4(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_5_n_0 ), - .I5(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_6_n_0 ), - .O(p_8_in__14)); - LUT6 #( - .INIT(64'h9009000000009009)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_5 - (.I0(Q[3]), - .I1(p_68_out[11]), - .I2(p_68_out[13]), - .I3(Q[5]), - .I4(p_68_out[12]), - .I5(Q[4]), - .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_5_n_0 )); - LUT6 #( - .INIT(64'h9009000000009009)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_6 - (.I0(Q[0]), - .I1(p_68_out[8]), - .I2(p_68_out[10]), - .I3(Q[2]), - .I4(p_68_out[9]), - .I5(Q[1]), - .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_6_n_0 )); + dly_irq_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[13] ), + .Q(dly_irq_reg_0), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_reg - (.C(m_axi_mm2s_aclk), + dma_decerr_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(p_10_out), - .Q(mm2s_dly_irq_set), + .D(decerr_i_reg), + .Q(\S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_2 ), .R(SR)); - LUT4 #( - .INIT(16'h0080)) - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_i_1 - (.I0(ch1_ioc_irq_set_i__0), - .I1(p_49_out), - .I2(out), - .I3(p_6_out__1), - .O(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_i_1_n_0 )); FDRE #( .INIT(1'b0)) - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_reg - (.C(m_axi_mm2s_aclk), + dma_interr_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_i_1_n_0 ), - .Q(mm2s_ioc_irq_set), - .R(1'b0)); - LUT5 #( - .INIT(32'hAAAAB88B)) - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[1]_i_1 - (.I0(p_68_out[1]), - .I1(ch1_ioc_irq_set_i__0), - .I2(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [0]), - .I3(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [1]), - .I4(p_6_out__1), - .O(p_2_in[1])); + .D(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4] ), + .Q(\S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_0 ), + .R(SR)); + FDRE #( + .INIT(1'b0)) + dma_slverr_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(slverr_i_reg), + .Q(\S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_1 ), + .R(SR)); LUT6 #( - .INIT(64'hAAAAAAAABBB8888B)) - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[2]_i_1 - (.I0(p_68_out[2]), - .I1(ch1_ioc_irq_set_i__0), - .I2(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [1]), - .I3(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [0]), - .I4(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [2]), - .I5(p_6_out__1), - .O(p_2_in[2])); - LUT5 #( - .INIT(32'hAAAAB88B)) - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[3]_i_1 - (.I0(p_68_out[3]), - .I1(ch1_ioc_irq_set_i__0), - .I2(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[3]_i_2_n_0 ), - .I3(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [3]), - .I4(p_6_out__1), - .O(p_2_in[3])); - (* SOFT_HLUTNM = "soft_lutpair41" *) + .INIT(64'h7077700000000000)) + \dmacr_i[0]_i_1__0 + (.I0(s2mm_dmacr[3]), + .I1(s2mm_ioc_irq_set), + .I2(D[0]), + .I3(s2mm_axi2ip_wrce[0]), + .I4(s2mm_dmacr[0]), + .I5(\dmacr_i[0]_i_2__0_n_0 ), + .O(dmacr_i)); + (* SOFT_HLUTNM = "soft_lutpair87" *) LUT3 #( - .INIT(8'hFE)) - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[3]_i_2 - (.I0(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [1]), - .I1(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [0]), - .I2(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [2]), - .O(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[3]_i_2_n_0 )); - LUT5 #( - .INIT(32'hAAAAB88B)) - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[4]_i_1 - (.I0(p_68_out[4]), - .I1(ch1_ioc_irq_set_i__0), - .I2(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[4]_i_2_n_0 ), - .I3(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [4]), - .I4(p_6_out__1), - .O(p_2_in[4])); - (* SOFT_HLUTNM = "soft_lutpair41" *) - LUT4 #( - .INIT(16'hFFFE)) - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[4]_i_2 - (.I0(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [2]), - .I1(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [0]), - .I2(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [1]), - .I3(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [3]), - .O(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[4]_i_2_n_0 )); - LUT5 #( - .INIT(32'hAAAAB88B)) - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[5]_i_1 - (.I0(p_68_out[5]), - .I1(ch1_ioc_irq_set_i__0), - .I2(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[5]_i_2_n_0 ), - .I3(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [5]), - .I4(p_6_out__1), - .O(p_2_in[5])); - (* SOFT_HLUTNM = "soft_lutpair39" *) - LUT5 #( - .INIT(32'hFFFFFFFE)) - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[5]_i_2 - (.I0(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [3]), - .I1(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [1]), - .I2(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [0]), - .I3(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [2]), - .I4(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [4]), - .O(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[5]_i_2_n_0 )); - LUT5 #( - .INIT(32'hAAAAB88B)) - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[6]_i_1 - (.I0(p_68_out[6]), - .I1(ch1_ioc_irq_set_i__0), - .I2(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5_n_0 ), - .I3(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [6]), - .I4(p_6_out__1), - .O(p_2_in[6])); + .INIT(8'h04)) + \dmacr_i[0]_i_2__0 + (.I0(soft_reset_d1_reg), + .I1(prmry_resetn_i_reg), + .I2(s2mm_stop), + .O(\dmacr_i[0]_i_2__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \dmacr_i_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(dmacr_i), + .Q(s2mm_dmacr[0]), + .R(1'b0)); + FDSE #( + .INIT(1'b0)) + \dmacr_i_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(s2mm_axi2ip_wrce[0]), + .D(D[1]), + .Q(s2mm_dmacr[1]), + .S(SR)); + FDRE #( + .INIT(1'b0)) + \dmacr_i_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\dmacr_i_reg[2]_0 ), + .Q(soft_reset_d1_reg), + .R(1'b0)); LUT6 #( - .INIT(64'hAAAAAAAABBB8888B)) - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_3 - (.I0(p_68_out[7]), - .I1(ch1_ioc_irq_set_i__0), - .I2(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [6]), - .I3(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5_n_0 ), - .I4(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [7]), - .I5(p_6_out__1), - .O(p_2_in[7])); - LUT5 #( - .INIT(32'h00000001)) - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_4 - (.I0(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [5]), - .I1(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [4]), - .I2(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [6]), - .I3(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [7]), - .I4(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_7_n_0 ), - .O(ch1_ioc_irq_set_i__0)); + .INIT(64'hEFEEFFFFEFEEEFEE)) + err_d1_i_1__0 + (.I0(err_d1_i_2_n_0), + .I1(err_d1_reg_1), + .I2(err_d1_reg_2[2]), + .I3(err_d1_reg_0), + .I4(err_d1_reg_2[3]), + .I5(\S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_4 ), + .O(err)); LUT6 #( - .INIT(64'hFFFFFFFFFFFFFFFE)) - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5 - (.I0(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [4]), - .I1(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [2]), - .I2(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [0]), - .I3(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [1]), - .I4(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [3]), - .I5(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [5]), - .O(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair39" *) - LUT4 #( - .INIT(16'hFFEF)) - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_7 - (.I0(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [2]), - .I1(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [3]), - .I2(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [0]), - .I3(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [1]), - .O(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_7_n_0 )); - FDSE #( - .INIT(1'b1)) - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0] - (.C(m_axi_mm2s_aclk), - .CE(E), - .D(D), - .Q(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [0]), - .S(prmry_resetn_i_reg)); + .INIT(64'hEEFEEEFEFFFFEEFE)) + err_d1_i_2 + (.I0(\S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_2 ), + .I1(\S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_1 ), + .I2(\S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_3 ), + .I3(err_d1_reg_2[1]), + .I4(\GEN_FOR_FLUSH.fsize_err_reg_0 ), + .I5(err_d1_reg_2[0]), + .O(err_d1_i_2_n_0)); FDRE #( .INIT(1'b0)) - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(E), - .D(p_2_in[1]), - .Q(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [1]), - .R(prmry_resetn_i_reg)); + err_d1_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(err), + .Q(err_d1), + .R(SR)); + LUT5 #( + .INIT(32'h5DFF0C0C)) + err_irq_i_1__0 + (.I0(D[13]), + .I1(err), + .I2(err_d1), + .I3(s2mm_axi2ip_wrce[1]), + .I4(err_irq_reg_0), + .O(err_irq_i_1__0_n_0)); FDRE #( .INIT(1'b0)) - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(E), - .D(p_2_in[2]), - .Q(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [2]), - .R(prmry_resetn_i_reg)); + err_irq_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(err_irq_i_1__0_n_0), + .Q(err_irq_reg_0), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[3] - (.C(m_axi_mm2s_aclk), - .CE(E), - .D(p_2_in[3]), - .Q(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [3]), - .R(prmry_resetn_i_reg)); + halted_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(halted_clr_reg), + .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair87" *) + LUT3 #( + .INIT(8'h08)) + introut_i_1__0 + (.I0(introut07_out), + .I1(prmry_resetn_i_reg), + .I2(soft_reset_d1_reg), + .O(introut_i_1__0_n_0)); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + introut_i_2__0 + (.I0(Q[6]), + .I1(err_irq_reg_0), + .I2(Q[5]), + .I3(dly_irq_reg_0), + .I4(ioc_irq_reg_0), + .I5(Q[4]), + .O(introut07_out)); + FDRE introut_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(introut_i_1__0_n_0), + .Q(s2mm_ip2axi_introut), + .R(1'b0)); FDRE #( .INIT(1'b0)) - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[4] - (.C(m_axi_mm2s_aclk), - .CE(E), - .D(p_2_in[4]), - .Q(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [4]), - .R(prmry_resetn_i_reg)); + ioc_irq_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[12] ), + .Q(ioc_irq_reg_0), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[5] - (.C(m_axi_mm2s_aclk), - .CE(E), - .D(p_2_in[5]), - .Q(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [5]), - .R(prmry_resetn_i_reg)); + lsize_err_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[8] ), + .Q(\S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_3 ), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[6] - (.C(m_axi_mm2s_aclk), - .CE(E), - .D(p_2_in[6]), - .Q(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [6]), - .R(prmry_resetn_i_reg)); + lsize_more_err_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[15] ), + .Q(\S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_4 ), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] - (.C(m_axi_mm2s_aclk), - .CE(E), - .D(p_2_in[7]), - .Q(\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg [7]), - .R(prmry_resetn_i_reg)); + reset_counts_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(reset_counts_reg_0), + .Q(reset_counts), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair86" *) + LUT2 #( + .INIT(4'hB)) + \s_axis_cmd_tdata[63]_i_1__0 + (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ), + .I1(prmry_resetn_i_reg), + .O(s_axis_cmd_tvalid_reg)); + LUT4 #( + .INIT(16'hA800)) + s_soft_reset_i_i_1__0 + (.I0(soft_reset_d1_reg), + .I1(s2mm_halt_cmplt), + .I2(halt_reset), + .I3(prmry_in), + .O(s_soft_reset_i0)); endmodule -(* ORIG_REF_NAME = "axi_vdma_lite_if" *) -module Arty_Z7_20_axi_vdma_0_0_axi_vdma_lite_if - (D, - out, - s_axi_lite_awready, - s_axi_lite_wready, - s_axi_lite_arready, - s_axi_lite_bvalid, - s_axi_lite_rvalid, - \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg , - \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[16] , - \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg , - mm2s_axi2ip_wrce, - \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] , - in0, - prmtr_updt_complete_i_reg, - ioc_irq_reg, - dly_irq_reg, - s_axi_lite_rdata, - SR, - s_axi_lite_aclk, +(* ORIG_REF_NAME = "axi_vdma_reset" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_reset + (in0, + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from , prmry_reset2, + \dmacr_i_reg[2] , + halt_i_reg_0, + sig_mm2s_dm_prmry_resetn, + WR_EN, + \cmnds_queued_reg[7] , + \GEN_LINEBUF_NO_SOF.s_axis_fifo_ainit_nosync_reg_reg , + sig_s_h_halt_reg_reg, + reset_counts_reg, + scndry_out, m_axi_mm2s_aclk, - s_axi_lite_wvalid, - s_axi_lite_awvalid, - s_axi_lite_arvalid, - different_delay, - different_thresh, - prmry_resetn_i_reg, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[0] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[15] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[14] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[13] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[12] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[6] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[5] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[4] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[2] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[1] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[3] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[7] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[8] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[9] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[10] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[11] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] , - s_axi_lite_resetn, - s_axi_lite_bready, - s_axi_lite_rready, - p_68_out, - p_67_out, - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7] , - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] , - err_irq_reg, - dly_irq_reg_0, - ioc_irq_reg_0, - dma_decerr_reg, - dma_slverr_reg, - dma_interr_reg, - mm2s_ioc_irq_set, - mm2s_dly_irq_set, - s_axi_lite_araddr, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 , - s_axi_lite_wdata, - s_axi_lite_awaddr, - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] , - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] ); - output [31:0]D; - output [1:0]out; - output s_axi_lite_awready; - output s_axi_lite_wready; - output s_axi_lite_arready; - output s_axi_lite_bvalid; - output s_axi_lite_rvalid; - output \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg ; - output \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[16] ; - output \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg ; - output [5:0]mm2s_axi2ip_wrce; - output [0:0]\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] ; - output [31:0]in0; - output prmtr_updt_complete_i_reg; - output ioc_irq_reg; - output dly_irq_reg; - output [31:0]s_axi_lite_rdata; - input [0:0]SR; - input s_axi_lite_aclk; - input prmry_reset2; + s_axi_lite_aclk, + m_axis_mm2s_aclk, + p_77_out, + s_soft_reset_i0, + stop, + p_71_out, + mm2s_axi2ip_wrce, + D, + hold_ff_q_reg, + p_24_out, + out, + sig_s_ready_out_reg, + FULL, + dma_err_4, + sig_rst2all_stop_request, + reset_counts, + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 , + prmry_in, + mm2s_halt_cmplt); + output in0; + output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ; + output prmry_reset2; + output \dmacr_i_reg[2] ; + output halt_i_reg_0; + output sig_mm2s_dm_prmry_resetn; + output WR_EN; + output [0:0]\cmnds_queued_reg[7] ; + output \GEN_LINEBUF_NO_SOF.s_axis_fifo_ainit_nosync_reg_reg ; + output sig_s_h_halt_reg_reg; + output reset_counts_reg; + output scndry_out; input m_axi_mm2s_aclk; - input s_axi_lite_wvalid; - input s_axi_lite_awvalid; - input s_axi_lite_arvalid; - input different_delay; - input different_thresh; - input prmry_resetn_i_reg; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[0] ; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[15] ; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[14] ; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[13] ; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[12] ; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[6] ; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[5] ; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[4] ; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[2] ; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[1] ; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[3] ; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[7] ; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[8] ; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[9] ; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[10] ; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[11] ; - input [15:0]\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] ; - input s_axi_lite_resetn; - input s_axi_lite_bready; - input s_axi_lite_rready; - input [25:0]p_68_out; - input p_67_out; - input [7:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7] ; - input [7:0]\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] ; - input err_irq_reg; - input dly_irq_reg_0; - input ioc_irq_reg_0; - input dma_decerr_reg; - input dma_slverr_reg; - input dma_interr_reg; - input mm2s_ioc_irq_set; - input mm2s_dly_irq_set; - input [5:0]s_axi_lite_araddr; - input [31:0]\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 ; - input [31:0]s_axi_lite_wdata; - input [5:0]s_axi_lite_awaddr; - input [4:0]\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] ; - input [4:0]\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] ; + input s_axi_lite_aclk; + input m_axis_mm2s_aclk; + input p_77_out; + input s_soft_reset_i0; + input stop; + input [0:0]p_71_out; + input [0:0]mm2s_axi2ip_wrce; + input [0:0]D; + input hold_ff_q_reg; + input p_24_out; + input out; + input sig_s_ready_out_reg; + input FULL; + input dma_err_4; + input sig_rst2all_stop_request; + input reset_counts; + input \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ; + input prmry_in; + input mm2s_halt_cmplt; - wire \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg ; - wire \ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_3_n_0 ; - wire \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[16] ; - wire [0:0]\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] ; - wire \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg ; - wire [7:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7] ; - wire [7:0]\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] ; - wire [31:0]\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[10]_i_1_n_0 ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[11]_i_1_n_0 ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[12]_i_1_n_0 ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[13]_i_1_n_0 ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[14]_i_1_n_0 ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[15]_i_1_n_0 ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[21]_i_1_n_0 ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[22]_i_1_n_0 ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[23]_i_1_n_0 ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[24]_i_1_n_0 ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[26]_i_1_n_0 ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[27]_i_1_n_0 ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_1_n_0 ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0 ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_2_n_0 ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[5]_i_1_n_0 ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[7]_i_1_n_0 ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[8]_i_1_n_0 ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[9]_i_1_n_0 ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.prepare_wrce_pulse_lite_d6_reg_srl6_i_1_n_0 ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.rvalid_out_i_i_1_n_0 ; - wire [4:0]\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] ; - wire [4:0]\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i[31]_i_2_n_0 ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[0] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[10] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[11] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[12] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[13] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[14] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[15] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[1] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[2] ; - wire [15:0]\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[3] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[4] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[5] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[6] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[7] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[8] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[9] ; - wire \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I/I_DMA_REGISTER/threshold_is_zero ; - wire [0:0]SR; - wire addr_region_mm2s_rden_cmb__4; - wire arvalid; - wire [7:2]awaddr; - wire awvalid; - (* async_reg = "true" *) wire [7:2]axi2ip_rdaddr_captured_mm2s_cdc_tig; - wire \axi2ip_rdaddr_captured_reg_n_0_[2] ; - wire \axi2ip_rdaddr_captured_reg_n_0_[3] ; - wire \axi2ip_rdaddr_captured_reg_n_0_[4] ; - wire \axi2ip_rdaddr_captured_reg_n_0_[5] ; - wire \axi2ip_rdaddr_captured_reg_n_0_[6] ; - wire \axi2ip_rdaddr_captured_reg_n_0_[7] ; - (* async_reg = "true" *) wire [7:2]axi2ip_rdaddr_captured_s2mm_cdc_tig; - wire [7:2]axi2ip_wraddr_captured; - (* async_reg = "true" *) wire [7:2]axi2ip_wraddr_captured_mm2s_cdc_tig; - (* async_reg = "true" *) wire [7:2]axi2ip_wraddr_captured_s2mm_cdc_tig; - wire bvalid_out_i_i_1_n_0; - wire different_delay; - wire different_thresh; - wire dly_irq_reg; - wire dly_irq_reg_0; - wire dma_decerr_reg; - wire dma_interr_reg; - wire dma_slverr_reg; - wire \dmacr_i[1]_i_2_n_0 ; - wire err_irq_reg; - wire [31:0]in0; - wire ioc_irq_reg; - wire ioc_irq_reg_0; - wire [30:0]ip2axi_rddata_captured; - (* async_reg = "true" *) wire [31:0]ip2axi_rddata_captured_mm2s_cdc_tig; - (* async_reg = "true" *) wire [31:0]ip2axi_rddata_captured_s2mm_cdc_tig; - wire ip2axi_rddata_int_inferred_i_33_n_0; - wire ip2axi_rddata_int_inferred_i_34_n_0; - wire ip2axi_rddata_int_inferred_i_35_n_0; - wire ip2axi_rddata_int_inferred_i_36_n_0; - wire ip2axi_rddata_int_inferred_i_37_n_0; - wire ip2axi_rddata_int_inferred_i_38_n_0; - wire ip2axi_rddata_int_inferred_i_39_n_0; - wire ip2axi_rddata_int_inferred_i_40_n_0; - wire ip2axi_rddata_int_inferred_i_41_n_0; - wire ip2axi_rddata_int_inferred_i_42_n_0; - wire ip2axi_rddata_int_inferred_i_43_n_0; - wire ip2axi_rddata_int_inferred_i_44_n_0; - wire ip2axi_rddata_int_inferred_i_45_n_0; - wire ip2axi_rddata_int_inferred_i_46_n_0; - wire ip2axi_rddata_int_inferred_i_47_n_0; - wire ip2axi_rddata_int_inferred_i_48_n_0; - wire ip2axi_rddata_int_inferred_i_49_n_0; - wire ip2axi_rddata_int_inferred_i_50_n_0; - wire ip2axi_rddata_int_inferred_i_51_n_0; - wire ip2axi_rddata_int_inferred_i_52_n_0; - wire ip2axi_rddata_int_inferred_i_53_n_0; - wire ip2axi_rddata_int_inferred_i_54_n_0; - wire ip2axi_rddata_int_inferred_i_55_n_0; - wire ip2axi_rddata_int_inferred_i_56_n_0; - wire ip2axi_rddata_int_inferred_i_57_n_0; - wire ip2axi_rddata_int_inferred_i_58_n_0; - wire ip2axi_rddata_int_inferred_i_59_n_0; - wire ip2axi_rddata_int_inferred_i_60_n_0; - wire ip2axi_rddata_int_inferred_i_61_n_0; - wire ip2axi_rddata_int_inferred_i_62_n_0; - wire ip2axi_rddata_int_inferred_i_63_n_0; - wire ip2axi_rddata_int_inferred_i_64_n_0; - wire ip2axi_rddata_int_inferred_i_66_n_0; - wire ip2axi_rddata_int_inferred_i_68_n_0; - wire ip2axi_rddata_int_inferred_i_70_n_0; - wire ip2axi_rddata_int_inferred_i_72_n_0; - wire ip2axi_rddata_int_inferred_i_79_n_0; - wire ip2axi_rddata_int_inferred_i_81_n_0; - wire ip2axi_rddata_int_inferred_i_83_n_0; - wire ip2axi_rddata_int_inferred_i_86_n_0; - wire ip2axi_rddata_int_inferred_i_88_n_0; - wire ip2axi_rddata_int_inferred_i_90_n_0; - wire lite_wr_addr_phase_finished_data_phase_started; - wire lite_wr_addr_phase_finished_data_phase_started_i_1_n_0; + wire [0:0]D; + wire FULL; + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ; + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ; + wire \GEN_LINEBUF_NO_SOF.s_axis_fifo_ainit_nosync_reg_reg ; + wire \GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2 ; + wire \GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_i_1_n_0 ; + wire \GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2 ; + wire \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_3 ; + wire \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_4 ; + wire \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_1_n_0 ; + wire \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_2_n_0 ; + wire \GEN_MIN_FOR_ASYNC.axis_min_count[0]_i_1_n_0 ; + wire \GEN_MIN_FOR_ASYNC.axis_min_count[1]_i_1_n_0 ; + wire \GEN_MIN_FOR_ASYNC.axis_min_count[2]_i_1_n_0 ; + wire \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0 ; + wire \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_3_n_0 ; + wire \GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_i_1_n_0 ; + wire \GEN_MIN_FOR_ASYNC.lite_min_count[0]_i_1_n_0 ; + wire \GEN_MIN_FOR_ASYNC.lite_min_count[1]_i_1_n_0 ; + wire \GEN_MIN_FOR_ASYNC.lite_min_count[2]_i_1_n_0 ; + wire \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0 ; + wire \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_3_n_0 ; + wire \GEN_MIN_FOR_ASYNC.prmry_min_count[0]_i_1_n_0 ; + wire \GEN_MIN_FOR_ASYNC.prmry_min_count[1]_i_1_n_0 ; + wire \GEN_MIN_FOR_ASYNC.prmry_min_count[2]_i_1_n_0 ; + wire \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0 ; + wire \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_3_n_0 ; + wire \GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_1 ; + wire \GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_4 ; + wire WR_EN; + wire assert_sftrst_d1; + wire axis_all_idle; + wire axis_min_assert_sftrst; + wire [3:0]axis_min_count; + wire [0:0]\cmnds_queued_reg[7] ; + wire dma_err_4; + wire \dmacr_i_reg[2] ; + wire halt_i0; + wire halt_i_reg_0; + wire halt_reset_i_1_n_0; + wire hold_ff_q_reg; + wire in0; + wire lite_all_idle; + wire lite_min_assert_sftrst; + wire [3:0]lite_min_count; wire m_axi_mm2s_aclk; - wire [5:0]mm2s_axi2ip_wrce; - (* async_reg = "true" *) wire [31:0]mm2s_axi2ip_wrdata_cdc_tig; - wire mm2s_dly_irq_set; - wire mm2s_ioc_irq_set; - wire [31:0]mm2s_ip2axi_rddata_d1; - wire [5:0]p_2_in; - wire p_67_out; - wire [25:0]p_68_out; - wire prepare_wrce; - wire prepare_wrce_d1; - wire prepare_wrce_pulse_lite_d6; + wire m_axis_mm2s_aclk; + wire min_assert_sftrst; + wire [0:0]mm2s_axi2ip_wrce; + wire mm2s_halt_cmplt; + wire out; + wire p_11_out; + wire p_1_out; + wire p_24_out; + wire p_2_out; + wire p_3_out; + wire p_4_out; + wire p_5_out; + wire p_6_out; + wire [0:0]p_71_out; + wire p_77_out; + wire p_8_out; + wire p_in_d1_cdc_from; + wire p_in_d1_cdc_from_0; + wire prmry_in; + wire prmry_in_xored; + wire prmry_in_xored_1; + wire prmry_min_assert_sftrst; + wire [3:0]prmry_min_count; wire prmry_reset2; - wire prmry_resetn_i_reg; - wire prmtr_updt_complete_i_reg; - wire read_has_started_i; - wire read_has_started_i_i_1_n_0; - (* async_reg = "true" *) wire [31:0]s2mm_axi2ip_wrdata_cdc_tig; + wire reset_counts; + wire reset_counts_reg; + wire resetn_i; + wire run_stop_d1; wire s_axi_lite_aclk; - wire [5:0]s_axi_lite_araddr; - wire s_axi_lite_arready; - wire s_axi_lite_arvalid; - wire [5:0]s_axi_lite_awaddr; - wire s_axi_lite_awready; - wire s_axi_lite_awvalid; - wire s_axi_lite_bready; - wire s_axi_lite_bvalid; - wire [31:0]s_axi_lite_rdata; - wire s_axi_lite_resetn; - wire s_axi_lite_rready; - wire s_axi_lite_rvalid; - wire [31:0]s_axi_lite_wdata; - wire s_axi_lite_wready; - wire s_axi_lite_wvalid; - wire sig_arvalid_arrived_d1; - wire sig_arvalid_arrived_d1_i_1_n_0; - wire sig_arvalid_arrived_d4; - wire sig_arvalid_detected__0; - wire sig_awvalid_arrived_d1; - wire sig_awvalid_arrived_d1_i_1_n_0; - wire sig_awvalid_detected__0; - wire [31:0]wdata; - wire write_has_started; - wire write_has_started_i_1_n_0; - wire wvalid; + wire s_soft_reset_i; + wire s_soft_reset_i0; + wire s_soft_reset_i_d1; + wire scndry_out; + wire sig_mm2s_dm_prmry_resetn; + wire sig_rst2all_stop_request; + wire sig_s_h_halt_reg_reg; + wire sig_s_ready_out_reg; + wire soft_reset_d1; + wire stop; - assign D[31:0] = mm2s_axi2ip_wrdata_cdc_tig; - assign out[1:0] = axi2ip_rdaddr_captured_mm2s_cdc_tig[3:2]; - LUT5 #( - .INIT(32'h00000001)) - \ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_2 - (.I0(mm2s_axi2ip_wrdata_cdc_tig[21]), - .I1(mm2s_axi2ip_wrdata_cdc_tig[20]), - .I2(mm2s_axi2ip_wrdata_cdc_tig[22]), - .I3(mm2s_axi2ip_wrdata_cdc_tig[23]), - .I4(\ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_3_n_0 ), - .O(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I/I_DMA_REGISTER/threshold_is_zero )); - LUT4 #( - .INIT(16'hFFFE)) - \ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_3 - (.I0(mm2s_axi2ip_wrdata_cdc_tig[18]), - .I1(mm2s_axi2ip_wrdata_cdc_tig[19]), - .I2(mm2s_axi2ip_wrdata_cdc_tig[16]), - .I3(mm2s_axi2ip_wrdata_cdc_tig[17]), - .O(\ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_3_n_0 )); - Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized6 \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.LITE_WVALID_MM2S_CDC_I - (.D(mm2s_axi2ip_wrdata_cdc_tig[13:12]), - .\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg (\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg ), - .\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[16] (\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[16] ), - .\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] (\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] ), - .\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg (\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[4] (\GEN_NUM_FSTORES_1.reg_module_start_address1_i[31]_i_2_n_0 ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[6] (\dmacr_i[1]_i_2_n_0 ), - .SR(SR), - .different_delay(different_delay), - .different_thresh(different_thresh), - .dly_irq_reg(dly_irq_reg), - .dly_irq_reg_0(dly_irq_reg_0), - .ioc_irq_reg(ioc_irq_reg), - .ioc_irq_reg_0(ioc_irq_reg_0), - .lite_wr_addr_phase_finished_data_phase_started(lite_wr_addr_phase_finished_data_phase_started), + (* SOFT_HLUTNM = "soft_lutpair263" *) + LUT2 #( + .INIT(4'hB)) + \GEN_LINEBUF_NO_SOF.s_axis_fifo_ainit_nosync_reg_i_1 + (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ), + .I1(out), + .O(\GEN_LINEBUF_NO_SOF.s_axis_fifo_ainit_nosync_reg_reg )); + Arty_Z7_20_axi_vdma_0_0_cdc_sync_6 \GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I + (.SR(\GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2 ), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .mm2s_axi2ip_wrce(mm2s_axi2ip_wrce), - .mm2s_dly_irq_set(mm2s_dly_irq_set), - .mm2s_ioc_irq_set(mm2s_ioc_irq_set), - .out(axi2ip_wraddr_captured_mm2s_cdc_tig), - .p_68_out(p_68_out[0]), - .prepare_wrce_d1(prepare_wrce_d1), - .prmry_reset2(prmry_reset2), - .prmry_resetn_i_reg(prmry_resetn_i_reg), - .prmtr_updt_complete_i_reg(prmtr_updt_complete_i_reg), - .s_axi_lite_aclk(s_axi_lite_aclk), - .threshold_is_zero(\GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I/I_DMA_REGISTER/threshold_is_zero ), - .wvalid(wvalid)); - FDRE #( - .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.arready_out_i_reg - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(sig_arvalid_arrived_d4), - .Q(s_axi_lite_arready), - .R(SR)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + .m_axis_mm2s_aclk(m_axis_mm2s_aclk), + .p_1_out(p_1_out), + .p_3_out(p_3_out), + .p_in_d1_cdc_from(p_in_d1_cdc_from), + .prmry_in_xored(prmry_in_xored)); + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized2_7 \GEN_MIN_FOR_ASYNC.AXIS_IDLE_CDC_I + (.\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .m_axis_mm2s_aclk(m_axis_mm2s_aclk), + .scndry_out(axis_all_idle)); + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized3_8 \GEN_MIN_FOR_ASYNC.AXIS_MIN_CDC_I + (.axis_min_assert_sftrst(axis_min_assert_sftrst), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .m_axis_mm2s_aclk(m_axis_mm2s_aclk), + .scndry_out(p_2_out)); + Arty_Z7_20_axi_vdma_0_0_cdc_sync_9 \GEN_MIN_FOR_ASYNC.AXIS_RESET_CDC_I + (.m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .m_axis_mm2s_aclk(m_axis_mm2s_aclk), + .p_3_out(p_3_out), + .s_soft_reset_i(s_soft_reset_i), + .s_soft_reset_i_d1(s_soft_reset_i_d1)); + LUT6 #( + .INIT(64'hF0E0FFFFF0E0F0E0)) + \GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_i_1 + (.I0(prmry_min_assert_sftrst), + .I1(p_5_out), + .I2(min_assert_sftrst), + .I3(p_2_out), + .I4(s_soft_reset_i_d1), + .I5(s_soft_reset_i), + .O(\GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_i_1_n_0 )); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[2] + \GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_reg (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(\axi2ip_rdaddr_captured_reg_n_0_[2] ), - .Q(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), + .D(\GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_i_1_n_0 ), + .Q(min_assert_sftrst), .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + Arty_Z7_20_axi_vdma_0_0_cdc_sync_10 \GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I + (.SR(\GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2 ), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .p_4_out(p_4_out), + .p_6_out(p_6_out), + .p_in_d1_cdc_from(p_in_d1_cdc_from_0), + .prmry_in_xored(prmry_in_xored_1), + .s_axi_lite_aclk(s_axi_lite_aclk)); + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized0_11 \GEN_MIN_FOR_ASYNC.LITE_IDLE_CDC_I + (.\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .s_axi_lite_aclk(s_axi_lite_aclk), + .scndry_out(lite_all_idle)); + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized1_12 \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I + (.\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 (p_2_out), + .\GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_reg (\GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_4 ), + .SR(\GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_3 ), + .lite_min_assert_sftrst(lite_min_assert_sftrst), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .p_11_out(p_11_out), + .p_in_d1_cdc_from(p_in_d1_cdc_from_0), + .p_in_d1_cdc_from_1(p_in_d1_cdc_from), + .prmry_in_xored(prmry_in_xored_1), + .prmry_in_xored_0(prmry_in_xored), + .prmry_min_assert_sftrst(prmry_min_assert_sftrst), + .s_axi_lite_aclk(s_axi_lite_aclk), + .s_soft_reset_i(s_soft_reset_i), + .s_soft_reset_i_d1(s_soft_reset_i_d1), + .scndry_out(p_5_out)); + Arty_Z7_20_axi_vdma_0_0_cdc_sync_13 \GEN_MIN_FOR_ASYNC.LITE_RESET_CDC_I + (.m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .p_6_out(p_6_out), + .s_axi_lite_aclk(s_axi_lite_aclk), + .s_soft_reset_i(s_soft_reset_i), + .s_soft_reset_i_d1(s_soft_reset_i_d1)); + LUT4 #( + .INIT(16'h00FE)) + \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_1 + (.I0(axis_min_assert_sftrst), + .I1(\GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_2_n_0 ), + .I2(p_3_out), + .I3(p_1_out), + .O(\GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair259" *) + LUT5 #( + .INIT(32'h80000000)) + \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_2 + (.I0(axis_min_count[2]), + .I1(axis_min_count[0]), + .I2(axis_min_assert_sftrst), + .I3(axis_min_count[3]), + .I4(axis_min_count[1]), + .O(\GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_2_n_0 )); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] - (.C(m_axi_mm2s_aclk), + \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_reg + (.C(m_axis_mm2s_aclk), .CE(1'b1), - .D(\axi2ip_rdaddr_captured_reg_n_0_[3] ), - .Q(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), + .D(\GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_1_n_0 ), + .Q(axis_min_assert_sftrst), .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + (* SOFT_HLUTNM = "soft_lutpair262" *) + LUT5 #( + .INIT(32'h8000FFFF)) + \GEN_MIN_FOR_ASYNC.axis_min_count[0]_i_1 + (.I0(axis_min_count[1]), + .I1(axis_min_count[3]), + .I2(axis_min_assert_sftrst), + .I3(axis_min_count[2]), + .I4(axis_min_count[0]), + .O(\GEN_MIN_FOR_ASYNC.axis_min_count[0]_i_1_n_0 )); + LUT5 #( + .INIT(32'hD5AA55AA)) + \GEN_MIN_FOR_ASYNC.axis_min_count[1]_i_1 + (.I0(axis_min_count[1]), + .I1(axis_min_count[3]), + .I2(axis_min_assert_sftrst), + .I3(axis_min_count[0]), + .I4(axis_min_count[2]), + .O(\GEN_MIN_FOR_ASYNC.axis_min_count[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair262" *) + LUT5 #( + .INIT(32'hD5FFAA00)) + \GEN_MIN_FOR_ASYNC.axis_min_count[2]_i_1 + (.I0(axis_min_count[1]), + .I1(axis_min_count[3]), + .I2(axis_min_assert_sftrst), + .I3(axis_min_count[0]), + .I4(axis_min_count[2]), + .O(\GEN_MIN_FOR_ASYNC.axis_min_count[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hEA00AA00AA00AA00)) + \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2 + (.I0(axis_all_idle), + .I1(axis_min_count[1]), + .I2(axis_min_count[3]), + .I3(axis_min_assert_sftrst), + .I4(axis_min_count[0]), + .I5(axis_min_count[2]), + .O(\GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair259" *) + LUT5 #( + .INIT(32'hE6CCCCCC)) + \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_3 + (.I0(axis_min_count[1]), + .I1(axis_min_count[3]), + .I2(axis_min_assert_sftrst), + .I3(axis_min_count[0]), + .I4(axis_min_count[2]), + .O(\GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_3_n_0 )); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[4] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\axi2ip_rdaddr_captured_reg_n_0_[4] ), - .Q(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \GEN_MIN_FOR_ASYNC.axis_min_count_reg[0] + (.C(m_axis_mm2s_aclk), + .CE(\GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0 ), + .D(\GEN_MIN_FOR_ASYNC.axis_min_count[0]_i_1_n_0 ), + .Q(axis_min_count[0]), + .R(\GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2 )); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\axi2ip_rdaddr_captured_reg_n_0_[5] ), - .Q(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \GEN_MIN_FOR_ASYNC.axis_min_count_reg[1] + (.C(m_axis_mm2s_aclk), + .CE(\GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0 ), + .D(\GEN_MIN_FOR_ASYNC.axis_min_count[1]_i_1_n_0 ), + .Q(axis_min_count[1]), + .R(\GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2 )); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[6] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\axi2ip_rdaddr_captured_reg_n_0_[6] ), - .Q(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \GEN_MIN_FOR_ASYNC.axis_min_count_reg[2] + (.C(m_axis_mm2s_aclk), + .CE(\GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0 ), + .D(\GEN_MIN_FOR_ASYNC.axis_min_count[2]_i_1_n_0 ), + .Q(axis_min_count[2]), + .R(\GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2 )); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\axi2ip_rdaddr_captured_reg_n_0_[7] ), - .Q(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \GEN_MIN_FOR_ASYNC.axis_min_count_reg[3] + (.C(m_axis_mm2s_aclk), + .CE(\GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0 ), + .D(\GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_3_n_0 ), + .Q(axis_min_count[3]), + .R(\GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2 )); + LUT4 #( + .INIT(16'h00FE)) + \GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_i_1 + (.I0(lite_min_assert_sftrst), + .I1(p_8_out), + .I2(p_6_out), + .I3(p_4_out), + .O(\GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair258" *) + LUT5 #( + .INIT(32'h80000000)) + \GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_i_2 + (.I0(lite_min_count[2]), + .I1(lite_min_count[0]), + .I2(lite_min_assert_sftrst), + .I3(lite_min_count[3]), + .I4(lite_min_count[1]), + .O(p_8_out)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[2] - (.C(m_axi_mm2s_aclk), + \GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_reg + (.C(s_axi_lite_aclk), .CE(1'b1), - .D(axi2ip_wraddr_captured[2]), - .Q(axi2ip_wraddr_captured_mm2s_cdc_tig[2]), + .D(\GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_i_1_n_0 ), + .Q(lite_min_assert_sftrst), .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + (* SOFT_HLUTNM = "soft_lutpair261" *) + LUT5 #( + .INIT(32'h8000FFFF)) + \GEN_MIN_FOR_ASYNC.lite_min_count[0]_i_1 + (.I0(lite_min_count[1]), + .I1(lite_min_count[3]), + .I2(lite_min_assert_sftrst), + .I3(lite_min_count[2]), + .I4(lite_min_count[0]), + .O(\GEN_MIN_FOR_ASYNC.lite_min_count[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair258" *) + LUT5 #( + .INIT(32'hD5AA55AA)) + \GEN_MIN_FOR_ASYNC.lite_min_count[1]_i_1 + (.I0(lite_min_count[1]), + .I1(lite_min_count[3]), + .I2(lite_min_assert_sftrst), + .I3(lite_min_count[0]), + .I4(lite_min_count[2]), + .O(\GEN_MIN_FOR_ASYNC.lite_min_count[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair261" *) + LUT5 #( + .INIT(32'hD5FFAA00)) + \GEN_MIN_FOR_ASYNC.lite_min_count[2]_i_1 + (.I0(lite_min_count[1]), + .I1(lite_min_count[3]), + .I2(lite_min_assert_sftrst), + .I3(lite_min_count[0]), + .I4(lite_min_count[2]), + .O(\GEN_MIN_FOR_ASYNC.lite_min_count[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hEA00AA00AA00AA00)) + \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2 + (.I0(lite_all_idle), + .I1(lite_min_count[1]), + .I2(lite_min_count[3]), + .I3(lite_min_assert_sftrst), + .I4(lite_min_count[0]), + .I5(lite_min_count[2]), + .O(\GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0 )); + LUT5 #( + .INIT(32'hE6CCCCCC)) + \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_3 + (.I0(lite_min_count[1]), + .I1(lite_min_count[3]), + .I2(lite_min_assert_sftrst), + .I3(lite_min_count[0]), + .I4(lite_min_count[2]), + .O(\GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_3_n_0 )); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[3] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(axi2ip_wraddr_captured[3]), - .Q(axi2ip_wraddr_captured_mm2s_cdc_tig[3]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \GEN_MIN_FOR_ASYNC.lite_min_count_reg[0] + (.C(s_axi_lite_aclk), + .CE(\GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0 ), + .D(\GEN_MIN_FOR_ASYNC.lite_min_count[0]_i_1_n_0 ), + .Q(lite_min_count[0]), + .R(\GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2 )); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[4] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(axi2ip_wraddr_captured[4]), - .Q(axi2ip_wraddr_captured_mm2s_cdc_tig[4]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \GEN_MIN_FOR_ASYNC.lite_min_count_reg[1] + (.C(s_axi_lite_aclk), + .CE(\GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0 ), + .D(\GEN_MIN_FOR_ASYNC.lite_min_count[1]_i_1_n_0 ), + .Q(lite_min_count[1]), + .R(\GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2 )); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[5] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(axi2ip_wraddr_captured[5]), - .Q(axi2ip_wraddr_captured_mm2s_cdc_tig[5]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \GEN_MIN_FOR_ASYNC.lite_min_count_reg[2] + (.C(s_axi_lite_aclk), + .CE(\GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0 ), + .D(\GEN_MIN_FOR_ASYNC.lite_min_count[2]_i_1_n_0 ), + .Q(lite_min_count[2]), + .R(\GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2 )); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[6] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(axi2ip_wraddr_captured[6]), - .Q(axi2ip_wraddr_captured_mm2s_cdc_tig[6]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \GEN_MIN_FOR_ASYNC.lite_min_count_reg[3] + (.C(s_axi_lite_aclk), + .CE(\GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0 ), + .D(\GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_3_n_0 ), + .Q(lite_min_count[3]), + .R(\GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2 )); + (* SOFT_HLUTNM = "soft_lutpair257" *) + LUT5 #( + .INIT(32'h80000000)) + \GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_i_2 + (.I0(prmry_min_count[2]), + .I1(prmry_min_count[0]), + .I2(prmry_min_assert_sftrst), + .I3(prmry_min_count[3]), + .I4(prmry_min_count[1]), + .O(p_11_out)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7] + \GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_reg (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(axi2ip_wraddr_captured[7]), - .Q(axi2ip_wraddr_captured_mm2s_cdc_tig[7]), + .D(\GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_4 ), + .Q(prmry_min_assert_sftrst), .R(1'b0)); - LUT6 #( - .INIT(64'h04FF040004000400)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[0]_i_1 - (.I0(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0 ), - .I1(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] [0]), - .I2(\axi2ip_rdaddr_captured_reg_n_0_[2] ), - .I3(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 ), - .I4(addr_region_mm2s_rden_cmb__4), - .I5(ip2axi_rddata_captured_mm2s_cdc_tig[0]), - .O(ip2axi_rddata_captured[0])); - LUT5 #( - .INIT(32'h000AA80A)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[10]_i_1 - (.I0(ip2axi_rddata_captured_mm2s_cdc_tig[10]), - .I1(\axi2ip_rdaddr_captured_reg_n_0_[4] ), - .I2(\axi2ip_rdaddr_captured_reg_n_0_[5] ), - .I3(\axi2ip_rdaddr_captured_reg_n_0_[6] ), - .I4(\axi2ip_rdaddr_captured_reg_n_0_[7] ), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[10]_i_1_n_0 )); - LUT5 #( - .INIT(32'h000AA80A)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[11]_i_1 - (.I0(ip2axi_rddata_captured_mm2s_cdc_tig[11]), - .I1(\axi2ip_rdaddr_captured_reg_n_0_[4] ), - .I2(\axi2ip_rdaddr_captured_reg_n_0_[5] ), - .I3(\axi2ip_rdaddr_captured_reg_n_0_[6] ), - .I4(\axi2ip_rdaddr_captured_reg_n_0_[7] ), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[11]_i_1_n_0 )); - LUT5 #( - .INIT(32'h000AA80A)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[12]_i_1 - (.I0(ip2axi_rddata_captured_mm2s_cdc_tig[12]), - .I1(\axi2ip_rdaddr_captured_reg_n_0_[4] ), - .I2(\axi2ip_rdaddr_captured_reg_n_0_[5] ), - .I3(\axi2ip_rdaddr_captured_reg_n_0_[6] ), - .I4(\axi2ip_rdaddr_captured_reg_n_0_[7] ), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[12]_i_1_n_0 )); - LUT5 #( - .INIT(32'h000AA80A)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[13]_i_1 - (.I0(ip2axi_rddata_captured_mm2s_cdc_tig[13]), - .I1(\axi2ip_rdaddr_captured_reg_n_0_[4] ), - .I2(\axi2ip_rdaddr_captured_reg_n_0_[5] ), - .I3(\axi2ip_rdaddr_captured_reg_n_0_[6] ), - .I4(\axi2ip_rdaddr_captured_reg_n_0_[7] ), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[13]_i_1_n_0 )); - LUT5 #( - .INIT(32'h000AA80A)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[14]_i_1 - (.I0(ip2axi_rddata_captured_mm2s_cdc_tig[14]), - .I1(\axi2ip_rdaddr_captured_reg_n_0_[4] ), - .I2(\axi2ip_rdaddr_captured_reg_n_0_[5] ), - .I3(\axi2ip_rdaddr_captured_reg_n_0_[6] ), - .I4(\axi2ip_rdaddr_captured_reg_n_0_[7] ), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[14]_i_1_n_0 )); - LUT5 #( - .INIT(32'h000AA80A)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[15]_i_1 - (.I0(ip2axi_rddata_captured_mm2s_cdc_tig[15]), - .I1(\axi2ip_rdaddr_captured_reg_n_0_[4] ), - .I2(\axi2ip_rdaddr_captured_reg_n_0_[5] ), - .I3(\axi2ip_rdaddr_captured_reg_n_0_[6] ), - .I4(\axi2ip_rdaddr_captured_reg_n_0_[7] ), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[15]_i_1_n_0 )); - LUT6 #( - .INIT(64'h04FF040004000400)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[16]_i_1 - (.I0(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0 ), - .I1(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] [0]), - .I2(\axi2ip_rdaddr_captured_reg_n_0_[2] ), - .I3(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 ), - .I4(addr_region_mm2s_rden_cmb__4), - .I5(ip2axi_rddata_captured_mm2s_cdc_tig[16]), - .O(ip2axi_rddata_captured[16])); - LUT6 #( - .INIT(64'h04FF040004000400)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[17]_i_1 - (.I0(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0 ), - .I1(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] [1]), - .I2(\axi2ip_rdaddr_captured_reg_n_0_[2] ), - .I3(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 ), - .I4(addr_region_mm2s_rden_cmb__4), - .I5(ip2axi_rddata_captured_mm2s_cdc_tig[17]), - .O(ip2axi_rddata_captured[17])); - LUT6 #( - .INIT(64'h04FF040004000400)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[18]_i_1 - (.I0(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0 ), - .I1(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] [2]), - .I2(\axi2ip_rdaddr_captured_reg_n_0_[2] ), - .I3(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 ), - .I4(addr_region_mm2s_rden_cmb__4), - .I5(ip2axi_rddata_captured_mm2s_cdc_tig[18]), - .O(ip2axi_rddata_captured[18])); - LUT6 #( - .INIT(64'h04FF040004000400)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[19]_i_1 - (.I0(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0 ), - .I1(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] [3]), - .I2(\axi2ip_rdaddr_captured_reg_n_0_[2] ), - .I3(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 ), - .I4(addr_region_mm2s_rden_cmb__4), - .I5(ip2axi_rddata_captured_mm2s_cdc_tig[19]), - .O(ip2axi_rddata_captured[19])); - LUT6 #( - .INIT(64'h04FF040004000400)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[1]_i_1 - (.I0(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0 ), - .I1(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] [1]), - .I2(\axi2ip_rdaddr_captured_reg_n_0_[2] ), - .I3(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 ), - .I4(addr_region_mm2s_rden_cmb__4), - .I5(ip2axi_rddata_captured_mm2s_cdc_tig[1]), - .O(ip2axi_rddata_captured[1])); - LUT6 #( - .INIT(64'h04FF040004000400)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[20]_i_1 - (.I0(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0 ), - .I1(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] [4]), - .I2(\axi2ip_rdaddr_captured_reg_n_0_[2] ), - .I3(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 ), - .I4(addr_region_mm2s_rden_cmb__4), - .I5(ip2axi_rddata_captured_mm2s_cdc_tig[20]), - .O(ip2axi_rddata_captured[20])); - LUT5 #( - .INIT(32'h000AA80A)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[21]_i_1 - (.I0(ip2axi_rddata_captured_mm2s_cdc_tig[21]), - .I1(\axi2ip_rdaddr_captured_reg_n_0_[4] ), - .I2(\axi2ip_rdaddr_captured_reg_n_0_[5] ), - .I3(\axi2ip_rdaddr_captured_reg_n_0_[6] ), - .I4(\axi2ip_rdaddr_captured_reg_n_0_[7] ), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[21]_i_1_n_0 )); - LUT5 #( - .INIT(32'h000AA80A)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[22]_i_1 - (.I0(ip2axi_rddata_captured_mm2s_cdc_tig[22]), - .I1(\axi2ip_rdaddr_captured_reg_n_0_[4] ), - .I2(\axi2ip_rdaddr_captured_reg_n_0_[5] ), - .I3(\axi2ip_rdaddr_captured_reg_n_0_[6] ), - .I4(\axi2ip_rdaddr_captured_reg_n_0_[7] ), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[22]_i_1_n_0 )); - LUT5 #( - .INIT(32'h000AA80A)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[23]_i_1 - (.I0(ip2axi_rddata_captured_mm2s_cdc_tig[23]), - .I1(\axi2ip_rdaddr_captured_reg_n_0_[4] ), - .I2(\axi2ip_rdaddr_captured_reg_n_0_[5] ), - .I3(\axi2ip_rdaddr_captured_reg_n_0_[6] ), - .I4(\axi2ip_rdaddr_captured_reg_n_0_[7] ), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[23]_i_1_n_0 )); - LUT5 #( - .INIT(32'h000AA80A)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[24]_i_1 - (.I0(ip2axi_rddata_captured_mm2s_cdc_tig[24]), - .I1(\axi2ip_rdaddr_captured_reg_n_0_[4] ), - .I2(\axi2ip_rdaddr_captured_reg_n_0_[5] ), - .I3(\axi2ip_rdaddr_captured_reg_n_0_[6] ), - .I4(\axi2ip_rdaddr_captured_reg_n_0_[7] ), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[24]_i_1_n_0 )); - LUT5 #( - .INIT(32'h2F202020)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[25]_i_1 - (.I0(\axi2ip_rdaddr_captured_reg_n_0_[2] ), - .I1(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0 ), - .I2(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 ), - .I3(addr_region_mm2s_rden_cmb__4), - .I4(ip2axi_rddata_captured_mm2s_cdc_tig[25]), - .O(ip2axi_rddata_captured[25])); + (* SOFT_HLUTNM = "soft_lutpair257" *) LUT5 #( - .INIT(32'h000AA80A)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[26]_i_1 - (.I0(ip2axi_rddata_captured_mm2s_cdc_tig[26]), - .I1(\axi2ip_rdaddr_captured_reg_n_0_[4] ), - .I2(\axi2ip_rdaddr_captured_reg_n_0_[5] ), - .I3(\axi2ip_rdaddr_captured_reg_n_0_[6] ), - .I4(\axi2ip_rdaddr_captured_reg_n_0_[7] ), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[26]_i_1_n_0 )); - LUT5 #( - .INIT(32'h000AA80A)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[27]_i_1 - (.I0(ip2axi_rddata_captured_mm2s_cdc_tig[27]), - .I1(\axi2ip_rdaddr_captured_reg_n_0_[4] ), - .I2(\axi2ip_rdaddr_captured_reg_n_0_[5] ), - .I3(\axi2ip_rdaddr_captured_reg_n_0_[6] ), - .I4(\axi2ip_rdaddr_captured_reg_n_0_[7] ), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[27]_i_1_n_0 )); - LUT5 #( - .INIT(32'h000AA80A)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_1 - (.I0(ip2axi_rddata_captured_mm2s_cdc_tig[28]), - .I1(\axi2ip_rdaddr_captured_reg_n_0_[4] ), - .I2(\axi2ip_rdaddr_captured_reg_n_0_[5] ), - .I3(\axi2ip_rdaddr_captured_reg_n_0_[6] ), - .I4(\axi2ip_rdaddr_captured_reg_n_0_[7] ), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_1_n_0 )); - LUT5 #( - .INIT(32'h2F202020)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[29]_i_1 - (.I0(\axi2ip_rdaddr_captured_reg_n_0_[2] ), - .I1(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0 ), - .I2(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 ), - .I3(addr_region_mm2s_rden_cmb__4), - .I4(ip2axi_rddata_captured_mm2s_cdc_tig[29]), - .O(ip2axi_rddata_captured[29])); - LUT6 #( - .INIT(64'h04FF040004000400)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[2]_i_1 - (.I0(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0 ), - .I1(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] [2]), - .I2(\axi2ip_rdaddr_captured_reg_n_0_[2] ), - .I3(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 ), - .I4(addr_region_mm2s_rden_cmb__4), - .I5(ip2axi_rddata_captured_mm2s_cdc_tig[2]), - .O(ip2axi_rddata_captured[2])); - LUT5 #( - .INIT(32'h2F202020)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_1 - (.I0(\axi2ip_rdaddr_captured_reg_n_0_[2] ), - .I1(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0 ), - .I2(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 ), - .I3(addr_region_mm2s_rden_cmb__4), - .I4(ip2axi_rddata_captured_mm2s_cdc_tig[30]), - .O(ip2axi_rddata_captured[30])); - (* SOFT_HLUTNM = "soft_lutpair3" *) + .INIT(32'h8000FFFF)) + \GEN_MIN_FOR_ASYNC.prmry_min_count[0]_i_1 + (.I0(prmry_min_count[1]), + .I1(prmry_min_count[3]), + .I2(prmry_min_assert_sftrst), + .I3(prmry_min_count[2]), + .I4(prmry_min_count[0]), + .O(\GEN_MIN_FOR_ASYNC.prmry_min_count[0]_i_1_n_0 )); LUT5 #( - .INIT(32'hFEFFFFFF)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2 - (.I0(\axi2ip_rdaddr_captured_reg_n_0_[7] ), - .I1(\axi2ip_rdaddr_captured_reg_n_0_[6] ), - .I2(\axi2ip_rdaddr_captured_reg_n_0_[4] ), - .I3(\axi2ip_rdaddr_captured_reg_n_0_[5] ), - .I4(\axi2ip_rdaddr_captured_reg_n_0_[3] ), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair3" *) - LUT4 #( - .INIT(16'h4743)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3 - (.I0(\axi2ip_rdaddr_captured_reg_n_0_[7] ), - .I1(\axi2ip_rdaddr_captured_reg_n_0_[6] ), - .I2(\axi2ip_rdaddr_captured_reg_n_0_[5] ), - .I3(\axi2ip_rdaddr_captured_reg_n_0_[4] ), - .O(addr_region_mm2s_rden_cmb__4)); - LUT4 #( - .INIT(16'h8004)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1 - (.I0(\axi2ip_rdaddr_captured_reg_n_0_[7] ), - .I1(\axi2ip_rdaddr_captured_reg_n_0_[5] ), - .I2(\axi2ip_rdaddr_captured_reg_n_0_[6] ), - .I3(\axi2ip_rdaddr_captured_reg_n_0_[4] ), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 )); + .INIT(32'hD5AA55AA)) + \GEN_MIN_FOR_ASYNC.prmry_min_count[1]_i_1 + (.I0(prmry_min_count[1]), + .I1(prmry_min_count[3]), + .I2(prmry_min_assert_sftrst), + .I3(prmry_min_count[0]), + .I4(prmry_min_count[2]), + .O(\GEN_MIN_FOR_ASYNC.prmry_min_count[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair260" *) LUT5 #( - .INIT(32'h000AA80A)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_2 - (.I0(ip2axi_rddata_captured_mm2s_cdc_tig[31]), - .I1(\axi2ip_rdaddr_captured_reg_n_0_[4] ), - .I2(\axi2ip_rdaddr_captured_reg_n_0_[5] ), - .I3(\axi2ip_rdaddr_captured_reg_n_0_[6] ), - .I4(\axi2ip_rdaddr_captured_reg_n_0_[7] ), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_2_n_0 )); - LUT6 #( - .INIT(64'h04FF040004000400)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[3]_i_1 - (.I0(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0 ), - .I1(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] [3]), - .I2(\axi2ip_rdaddr_captured_reg_n_0_[2] ), - .I3(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 ), - .I4(addr_region_mm2s_rden_cmb__4), - .I5(ip2axi_rddata_captured_mm2s_cdc_tig[3]), - .O(ip2axi_rddata_captured[3])); + .INIT(32'hD5FFAA00)) + \GEN_MIN_FOR_ASYNC.prmry_min_count[2]_i_1 + (.I0(prmry_min_count[1]), + .I1(prmry_min_count[3]), + .I2(prmry_min_assert_sftrst), + .I3(prmry_min_count[0]), + .I4(prmry_min_count[2]), + .O(\GEN_MIN_FOR_ASYNC.prmry_min_count[2]_i_1_n_0 )); LUT6 #( - .INIT(64'h0EFF0E000E000E00)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[4]_i_1 - (.I0(\axi2ip_rdaddr_captured_reg_n_0_[2] ), - .I1(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] [4]), - .I2(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0 ), - .I3(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 ), - .I4(addr_region_mm2s_rden_cmb__4), - .I5(ip2axi_rddata_captured_mm2s_cdc_tig[4]), - .O(ip2axi_rddata_captured[4])); - LUT5 #( - .INIT(32'h000AA80A)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[5]_i_1 - (.I0(ip2axi_rddata_captured_mm2s_cdc_tig[5]), - .I1(\axi2ip_rdaddr_captured_reg_n_0_[4] ), - .I2(\axi2ip_rdaddr_captured_reg_n_0_[5] ), - .I3(\axi2ip_rdaddr_captured_reg_n_0_[6] ), - .I4(\axi2ip_rdaddr_captured_reg_n_0_[7] ), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[5]_i_1_n_0 )); - LUT5 #( - .INIT(32'h2F202020)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[6]_i_1 - (.I0(\axi2ip_rdaddr_captured_reg_n_0_[2] ), - .I1(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0 ), - .I2(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 ), - .I3(addr_region_mm2s_rden_cmb__4), - .I4(ip2axi_rddata_captured_mm2s_cdc_tig[6]), - .O(ip2axi_rddata_captured[6])); + .INIT(64'hEA00AA00AA00AA00)) + \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2 + (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ), + .I1(prmry_min_count[1]), + .I2(prmry_min_count[3]), + .I3(prmry_min_assert_sftrst), + .I4(prmry_min_count[0]), + .I5(prmry_min_count[2]), + .O(\GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair260" *) LUT5 #( - .INIT(32'h000AA80A)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[7]_i_1 - (.I0(ip2axi_rddata_captured_mm2s_cdc_tig[7]), - .I1(\axi2ip_rdaddr_captured_reg_n_0_[4] ), - .I2(\axi2ip_rdaddr_captured_reg_n_0_[5] ), - .I3(\axi2ip_rdaddr_captured_reg_n_0_[6] ), - .I4(\axi2ip_rdaddr_captured_reg_n_0_[7] ), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[7]_i_1_n_0 )); - LUT5 #( - .INIT(32'h000AA80A)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[8]_i_1 - (.I0(ip2axi_rddata_captured_mm2s_cdc_tig[8]), - .I1(\axi2ip_rdaddr_captured_reg_n_0_[4] ), - .I2(\axi2ip_rdaddr_captured_reg_n_0_[5] ), - .I3(\axi2ip_rdaddr_captured_reg_n_0_[6] ), - .I4(\axi2ip_rdaddr_captured_reg_n_0_[7] ), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[8]_i_1_n_0 )); - LUT5 #( - .INIT(32'h000AA80A)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[9]_i_1 - (.I0(ip2axi_rddata_captured_mm2s_cdc_tig[9]), - .I1(\axi2ip_rdaddr_captured_reg_n_0_[4] ), - .I2(\axi2ip_rdaddr_captured_reg_n_0_[5] ), - .I3(\axi2ip_rdaddr_captured_reg_n_0_[6] ), - .I4(\axi2ip_rdaddr_captured_reg_n_0_[7] ), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[9]_i_1_n_0 )); + .INIT(32'hE6CCCCCC)) + \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_3 + (.I0(prmry_min_count[1]), + .I1(prmry_min_count[3]), + .I2(prmry_min_assert_sftrst), + .I3(prmry_min_count[0]), + .I4(prmry_min_count[2]), + .O(\GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_3_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_MIN_FOR_ASYNC.prmry_min_count_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0 ), + .D(\GEN_MIN_FOR_ASYNC.prmry_min_count[0]_i_1_n_0 ), + .Q(prmry_min_count[0]), + .R(\GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_3 )); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[0] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(ip2axi_rddata_captured[0]), - .Q(s_axi_lite_rdata[0]), - .R(1'b0)); + \GEN_MIN_FOR_ASYNC.prmry_min_count_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0 ), + .D(\GEN_MIN_FOR_ASYNC.prmry_min_count[1]_i_1_n_0 ), + .Q(prmry_min_count[1]), + .R(\GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_3 )); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[10] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[10]_i_1_n_0 ), - .Q(s_axi_lite_rdata[10]), - .R(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 )); + \GEN_MIN_FOR_ASYNC.prmry_min_count_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0 ), + .D(\GEN_MIN_FOR_ASYNC.prmry_min_count[2]_i_1_n_0 ), + .Q(prmry_min_count[2]), + .R(\GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_3 )); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[11] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[11]_i_1_n_0 ), - .Q(s_axi_lite_rdata[11]), - .R(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 )); + \GEN_MIN_FOR_ASYNC.prmry_min_count_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0 ), + .D(\GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_3_n_0 ), + .Q(prmry_min_count[3]), + .R(\GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_3 )); + LUT2 #( + .INIT(4'hE)) + \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/sig_s_h_halt_reg_i_1 + (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ), + .I1(sig_rst2all_stop_request), + .O(sig_s_h_halt_reg_reg)); + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized5_14 \GEN_RESET_FOR_ASYNC.AXIS_RESET_CDC_I + (.m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .m_axis_mm2s_aclk(m_axis_mm2s_aclk), + .prmry_in(resetn_i), + .scndry_out(scndry_out)); + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized4_15 \GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I + (.D(D), + .assert_sftrst_d1(assert_sftrst_d1), + .\dmacr_i_reg[2] (\dmacr_i_reg[2] ), + .halt_i0(halt_i0), + .halt_i_reg(\GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_4 ), + .halt_i_reg_0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ), + .halt_reset_reg(halt_i_reg_0), + .hrd_resetn_i_reg(prmry_in), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .min_assert_sftrst(min_assert_sftrst), + .mm2s_axi2ip_wrce(mm2s_axi2ip_wrce), + .out(out), + .p_71_out(p_71_out), + .p_77_out(p_77_out), + .prmry_in(resetn_i), + .prmry_reset2(prmry_reset2), + .reset_counts(reset_counts), + .reset_counts_reg(reset_counts_reg), + .run_stop_d1_reg(\GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_1 ), + .s_axi_lite_aclk(s_axi_lite_aclk), + .s_soft_reset_i(s_soft_reset_i), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0(sig_mm2s_dm_prmry_resetn), + .stop(stop)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[12] - (.C(s_axi_lite_aclk), + assert_sftrst_d1_reg + (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[12]_i_1_n_0 ), - .Q(s_axi_lite_rdata[12]), - .R(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 )); + .D(min_assert_sftrst), + .Q(assert_sftrst_d1), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair263" *) + LUT4 #( + .INIT(16'hFEFF)) + \cmnds_queued[7]_i_1 + (.I0(dma_err_4), + .I1(p_77_out), + .I2(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ), + .I3(out), + .O(\cmnds_queued_reg[7] )); + LUT6 #( + .INIT(64'h0000000000000100)) + \gf36e1_inst.sngfifo36e1_i_3__0 + (.I0(hold_ff_q_reg), + .I1(p_24_out), + .I2(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ), + .I3(out), + .I4(sig_s_ready_out_reg), + .I5(FULL), + .O(WR_EN)); + LUT5 #( + .INIT(32'hAEAEFFAE)) + halt_i_i_2 + (.I0(stop), + .I1(run_stop_d1), + .I2(p_71_out), + .I3(p_77_out), + .I4(soft_reset_d1), + .O(halt_i0)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[13] - (.C(s_axi_lite_aclk), + halt_i_reg + (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[13]_i_1_n_0 ), - .Q(s_axi_lite_rdata[13]), - .R(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 )); + .D(\GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_4 ), + .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ), + .R(1'b0)); + LUT6 #( + .INIT(64'h222222222222F222)) + halt_reset_i_1 + (.I0(halt_i_reg_0), + .I1(p_71_out), + .I2(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ), + .I3(mm2s_halt_cmplt), + .I4(p_77_out), + .I5(stop), + .O(halt_reset_i_1_n_0)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[14] - (.C(s_axi_lite_aclk), + halt_reset_reg + (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[14]_i_1_n_0 ), - .Q(s_axi_lite_rdata[14]), - .R(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 )); + .D(halt_reset_i_1_n_0), + .Q(halt_i_reg_0), + .R(1'b0)); FDRE #( - .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[15] - (.C(s_axi_lite_aclk), + .INIT(1'b1)) + prmry_resetn_i_reg + (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[15]_i_1_n_0 ), - .Q(s_axi_lite_rdata[15]), - .R(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 )); + .D(resetn_i), + .Q(in0), + .R(1'b0)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[16] - (.C(s_axi_lite_aclk), + run_stop_d1_reg + (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(ip2axi_rddata_captured[16]), - .Q(s_axi_lite_rdata[16]), + .D(\GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_1 ), + .Q(run_stop_d1), .R(1'b0)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[17] - (.C(s_axi_lite_aclk), + s_soft_reset_i_d1_reg + (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(ip2axi_rddata_captured[17]), - .Q(s_axi_lite_rdata[17]), + .D(s_soft_reset_i), + .Q(s_soft_reset_i_d1), .R(1'b0)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[18] - (.C(s_axi_lite_aclk), + s_soft_reset_i_reg + (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(ip2axi_rddata_captured[18]), - .Q(s_axi_lite_rdata[18]), + .D(s_soft_reset_i0), + .Q(s_soft_reset_i), .R(1'b0)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[19] - (.C(s_axi_lite_aclk), + soft_reset_d1_reg + (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(ip2axi_rddata_captured[19]), - .Q(s_axi_lite_rdata[19]), + .D(p_77_out), + .Q(soft_reset_d1), .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_reset" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_reset_2 + (soft_reset_d1, + in0, + run_stop_d1, + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from , + prmry_reset2_0, + \dmacr_i_reg[2] , + p_12_out, + \FSM_sequential_dmacntrl_cs_reg[2] , + halt_i_reg_0, + sig_s2mm_dm_prmry_resetn, + \cmnds_queued_reg[7] , + reset_counts_reg, + sig_s_h_halt_reg_reg, + scndry_out, + m_axi_s2mm_aclk, + s_axi_lite_aclk, + s_axis_s2mm_aclk, + s2mm_soft_reset, + s_soft_reset_i0_3, + s2mm_dmacr, + s2mm_stop, + s2mm_axi2ip_wrce, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[2] , + CO, + dma_err, + Q, + halt_i0, + out, + reset_counts_5, + sig_rst2all_stop_request_6, + \cmnds_queued_reg[0] , + prmry_in, + s2mm_halt_cmplt); + output soft_reset_d1; + output in0; + output run_stop_d1; + output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ; + output prmry_reset2_0; + output \dmacr_i_reg[2] ; + output p_12_out; + output \FSM_sequential_dmacntrl_cs_reg[2] ; + output halt_i_reg_0; + output sig_s2mm_dm_prmry_resetn; + output [0:0]\cmnds_queued_reg[7] ; + output reset_counts_reg; + output sig_s_h_halt_reg_reg; + output scndry_out; + input m_axi_s2mm_aclk; + input s_axi_lite_aclk; + input s_axis_s2mm_aclk; + input s2mm_soft_reset; + input s_soft_reset_i0_3; + input [0:0]s2mm_dmacr; + input s2mm_stop; + input [0:0]s2mm_axi2ip_wrce; + input [0:0]\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[2] ; + input [0:0]CO; + input dma_err; + input [0:0]Q; + input halt_i0; + input out; + input reset_counts_5; + input sig_rst2all_stop_request_6; + input \cmnds_queued_reg[0] ; + input prmry_in; + input s2mm_halt_cmplt; + + wire [0:0]CO; + wire \FSM_sequential_dmacntrl_cs_reg[2] ; + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ; + wire [0:0]\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[2] ; + wire \GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2 ; + wire \GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_i_1_n_0 ; + wire \GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2 ; + wire \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_3 ; + wire \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_4 ; + wire \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_1_n_0 ; + wire \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_2__0_n_0 ; + wire \GEN_MIN_FOR_ASYNC.axis_min_count[0]_i_1__0_n_0 ; + wire \GEN_MIN_FOR_ASYNC.axis_min_count[1]_i_1_n_0 ; + wire \GEN_MIN_FOR_ASYNC.axis_min_count[2]_i_1_n_0 ; + wire \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0 ; + wire \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_3_n_0 ; + wire \GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_i_1_n_0 ; + wire \GEN_MIN_FOR_ASYNC.lite_min_count[0]_i_1__0_n_0 ; + wire \GEN_MIN_FOR_ASYNC.lite_min_count[1]_i_1_n_0 ; + wire \GEN_MIN_FOR_ASYNC.lite_min_count[2]_i_1_n_0 ; + wire \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0 ; + wire \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_3_n_0 ; + wire \GEN_MIN_FOR_ASYNC.prmry_min_count[0]_i_1__0_n_0 ; + wire \GEN_MIN_FOR_ASYNC.prmry_min_count[1]_i_1_n_0 ; + wire \GEN_MIN_FOR_ASYNC.prmry_min_count[2]_i_1_n_0 ; + wire \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0 ; + wire \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_3_n_0 ; + wire \GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_1 ; + wire \GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_4 ; + wire [0:0]Q; + wire assert_sftrst_d1; + wire axis_all_idle; + wire axis_min_assert_sftrst; + wire [3:0]axis_min_count; + wire \cmnds_queued_reg[0] ; + wire [0:0]\cmnds_queued_reg[7] ; + wire dma_err; + wire \dmacr_i_reg[2] ; + wire halt_i0; + wire halt_i_reg_0; + wire halt_reset_i_1_n_0; + wire in0; + wire lite_all_idle; + wire lite_min_assert_sftrst; + wire [3:0]lite_min_count; + wire m_axi_s2mm_aclk; + wire min_assert_sftrst; + wire out; + wire p_11_out; + wire p_12_out; + wire p_1_out; + wire p_2_out; + wire p_3_out; + wire p_4_out; + wire p_5_out; + wire p_6_out; + wire p_8_out; + wire p_in_d1_cdc_from; + wire p_in_d1_cdc_from_0; + wire prmry_in; + wire prmry_in_xored; + wire prmry_in_xored_1; + wire prmry_min_assert_sftrst; + wire [3:0]prmry_min_count; + wire prmry_reset2_0; + wire reset_counts_5; + wire reset_counts_reg; + wire resetn_i; + wire run_stop_d1; + wire [0:0]s2mm_axi2ip_wrce; + wire [0:0]s2mm_dmacr; + wire s2mm_halt_cmplt; + wire s2mm_soft_reset; + wire s2mm_stop; + wire s_axi_lite_aclk; + wire s_axis_s2mm_aclk; + wire s_soft_reset_i; + wire s_soft_reset_i0_3; + wire s_soft_reset_i_d1; + wire scndry_out; + wire sig_rst2all_stop_request_6; + wire sig_s2mm_dm_prmry_resetn; + wire sig_s_h_halt_reg_reg; + wire soft_reset_d1; + + Arty_Z7_20_axi_vdma_0_0_cdc_sync \GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I + (.SR(\GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2 ), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .p_1_out(p_1_out), + .p_3_out(p_3_out), + .p_in_d1_cdc_from(p_in_d1_cdc_from), + .prmry_in_xored(prmry_in_xored), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk)); + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized2 \GEN_MIN_FOR_ASYNC.AXIS_IDLE_CDC_I + (.\FSM_sequential_dmacntrl_cs_reg[2] (\FSM_sequential_dmacntrl_cs_reg[2] ), + .\cmnds_queued_reg[0] (\cmnds_queued_reg[0] ), + .dma_err(dma_err), + .halt_i_reg(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .s2mm_soft_reset(s2mm_soft_reset), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk), + .scndry_out(axis_all_idle)); + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized3 \GEN_MIN_FOR_ASYNC.AXIS_MIN_CDC_I + (.axis_min_assert_sftrst(axis_min_assert_sftrst), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk), + .scndry_out(p_2_out)); + Arty_Z7_20_axi_vdma_0_0_cdc_sync_3 \GEN_MIN_FOR_ASYNC.AXIS_RESET_CDC_I + (.m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .p_3_out(p_3_out), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk), + .s_soft_reset_i(s_soft_reset_i), + .s_soft_reset_i_d1(s_soft_reset_i_d1)); + LUT6 #( + .INIT(64'hF0E0FFFFF0E0F0E0)) + \GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_i_1 + (.I0(prmry_min_assert_sftrst), + .I1(p_5_out), + .I2(min_assert_sftrst), + .I3(p_2_out), + .I4(s_soft_reset_i_d1), + .I5(s_soft_reset_i), + .O(\GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_i_1_n_0 )); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[1] - (.C(s_axi_lite_aclk), + \GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(ip2axi_rddata_captured[1]), - .Q(s_axi_lite_rdata[1]), + .D(\GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_i_1_n_0 ), + .Q(min_assert_sftrst), .R(1'b0)); + Arty_Z7_20_axi_vdma_0_0_cdc_sync_4 \GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I + (.SR(\GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2 ), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .p_4_out(p_4_out), + .p_6_out(p_6_out), + .p_in_d1_cdc_from(p_in_d1_cdc_from_0), + .prmry_in_xored(prmry_in_xored_1), + .s_axi_lite_aclk(s_axi_lite_aclk)); + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized0 \GEN_MIN_FOR_ASYNC.LITE_IDLE_CDC_I + (.\cmnds_queued_reg[0] (\cmnds_queued_reg[0] ), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .s_axi_lite_aclk(s_axi_lite_aclk), + .scndry_out(lite_all_idle)); + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized1 \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I + (.\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 (p_2_out), + .\GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_reg (\GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_4 ), + .SR(\GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_3 ), + .lite_min_assert_sftrst(lite_min_assert_sftrst), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .p_11_out(p_11_out), + .p_in_d1_cdc_from(p_in_d1_cdc_from_0), + .p_in_d1_cdc_from_1(p_in_d1_cdc_from), + .prmry_in_xored(prmry_in_xored_1), + .prmry_in_xored_0(prmry_in_xored), + .prmry_min_assert_sftrst(prmry_min_assert_sftrst), + .s_axi_lite_aclk(s_axi_lite_aclk), + .s_soft_reset_i(s_soft_reset_i), + .s_soft_reset_i_d1(s_soft_reset_i_d1), + .scndry_out(p_5_out)); + Arty_Z7_20_axi_vdma_0_0_cdc_sync_5 \GEN_MIN_FOR_ASYNC.LITE_RESET_CDC_I + (.m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .p_6_out(p_6_out), + .s_axi_lite_aclk(s_axi_lite_aclk), + .s_soft_reset_i(s_soft_reset_i), + .s_soft_reset_i_d1(s_soft_reset_i_d1)); + LUT4 #( + .INIT(16'h00FE)) + \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_1 + (.I0(axis_min_assert_sftrst), + .I1(\GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_2__0_n_0 ), + .I2(p_3_out), + .I3(p_1_out), + .O(\GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair267" *) + LUT5 #( + .INIT(32'h80000000)) + \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_2__0 + (.I0(axis_min_count[2]), + .I1(axis_min_count[0]), + .I2(axis_min_assert_sftrst), + .I3(axis_min_count[3]), + .I4(axis_min_count[1]), + .O(\GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_2__0_n_0 )); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[20] - (.C(s_axi_lite_aclk), + \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_reg + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(ip2axi_rddata_captured[20]), - .Q(s_axi_lite_rdata[20]), + .D(\GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_1_n_0 ), + .Q(axis_min_assert_sftrst), .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair267" *) + LUT5 #( + .INIT(32'h8000FFFF)) + \GEN_MIN_FOR_ASYNC.axis_min_count[0]_i_1__0 + (.I0(axis_min_count[1]), + .I1(axis_min_count[3]), + .I2(axis_min_assert_sftrst), + .I3(axis_min_count[2]), + .I4(axis_min_count[0]), + .O(\GEN_MIN_FOR_ASYNC.axis_min_count[0]_i_1__0_n_0 )); + LUT5 #( + .INIT(32'hD5AA55AA)) + \GEN_MIN_FOR_ASYNC.axis_min_count[1]_i_1 + (.I0(axis_min_count[1]), + .I1(axis_min_count[3]), + .I2(axis_min_assert_sftrst), + .I3(axis_min_count[0]), + .I4(axis_min_count[2]), + .O(\GEN_MIN_FOR_ASYNC.axis_min_count[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair269" *) + LUT5 #( + .INIT(32'hD5FFAA00)) + \GEN_MIN_FOR_ASYNC.axis_min_count[2]_i_1 + (.I0(axis_min_count[1]), + .I1(axis_min_count[3]), + .I2(axis_min_assert_sftrst), + .I3(axis_min_count[0]), + .I4(axis_min_count[2]), + .O(\GEN_MIN_FOR_ASYNC.axis_min_count[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hEA00AA00AA00AA00)) + \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2 + (.I0(axis_all_idle), + .I1(axis_min_count[1]), + .I2(axis_min_count[3]), + .I3(axis_min_assert_sftrst), + .I4(axis_min_count[0]), + .I5(axis_min_count[2]), + .O(\GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair269" *) + LUT5 #( + .INIT(32'hE6CCCCCC)) + \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_3 + (.I0(axis_min_count[1]), + .I1(axis_min_count[3]), + .I2(axis_min_assert_sftrst), + .I3(axis_min_count[0]), + .I4(axis_min_count[2]), + .O(\GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_3_n_0 )); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[21] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[21]_i_1_n_0 ), - .Q(s_axi_lite_rdata[21]), - .R(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 )); + \GEN_MIN_FOR_ASYNC.axis_min_count_reg[0] + (.C(s_axis_s2mm_aclk), + .CE(\GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0 ), + .D(\GEN_MIN_FOR_ASYNC.axis_min_count[0]_i_1__0_n_0 ), + .Q(axis_min_count[0]), + .R(\GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2 )); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[22] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[22]_i_1_n_0 ), - .Q(s_axi_lite_rdata[22]), - .R(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 )); + \GEN_MIN_FOR_ASYNC.axis_min_count_reg[1] + (.C(s_axis_s2mm_aclk), + .CE(\GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0 ), + .D(\GEN_MIN_FOR_ASYNC.axis_min_count[1]_i_1_n_0 ), + .Q(axis_min_count[1]), + .R(\GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2 )); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[23] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[23]_i_1_n_0 ), - .Q(s_axi_lite_rdata[23]), - .R(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 )); + \GEN_MIN_FOR_ASYNC.axis_min_count_reg[2] + (.C(s_axis_s2mm_aclk), + .CE(\GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0 ), + .D(\GEN_MIN_FOR_ASYNC.axis_min_count[2]_i_1_n_0 ), + .Q(axis_min_count[2]), + .R(\GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2 )); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[24] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[24]_i_1_n_0 ), - .Q(s_axi_lite_rdata[24]), - .R(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 )); + \GEN_MIN_FOR_ASYNC.axis_min_count_reg[3] + (.C(s_axis_s2mm_aclk), + .CE(\GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0 ), + .D(\GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_3_n_0 ), + .Q(axis_min_count[3]), + .R(\GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2 )); + LUT4 #( + .INIT(16'h00FE)) + \GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_i_1 + (.I0(lite_min_assert_sftrst), + .I1(p_8_out), + .I2(p_6_out), + .I3(p_4_out), + .O(\GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair270" *) + LUT5 #( + .INIT(32'h80000000)) + \GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_i_2__0 + (.I0(lite_min_count[2]), + .I1(lite_min_count[0]), + .I2(lite_min_assert_sftrst), + .I3(lite_min_count[3]), + .I4(lite_min_count[1]), + .O(p_8_out)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[25] + \GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_reg (.C(s_axi_lite_aclk), .CE(1'b1), - .D(ip2axi_rddata_captured[25]), - .Q(s_axi_lite_rdata[25]), + .D(\GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_i_1_n_0 ), + .Q(lite_min_assert_sftrst), .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair271" *) + LUT5 #( + .INIT(32'h8000FFFF)) + \GEN_MIN_FOR_ASYNC.lite_min_count[0]_i_1__0 + (.I0(lite_min_count[1]), + .I1(lite_min_count[3]), + .I2(lite_min_assert_sftrst), + .I3(lite_min_count[2]), + .I4(lite_min_count[0]), + .O(\GEN_MIN_FOR_ASYNC.lite_min_count[0]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair271" *) + LUT5 #( + .INIT(32'hD5AA55AA)) + \GEN_MIN_FOR_ASYNC.lite_min_count[1]_i_1 + (.I0(lite_min_count[1]), + .I1(lite_min_count[3]), + .I2(lite_min_assert_sftrst), + .I3(lite_min_count[0]), + .I4(lite_min_count[2]), + .O(\GEN_MIN_FOR_ASYNC.lite_min_count[1]_i_1_n_0 )); + LUT5 #( + .INIT(32'hD5FFAA00)) + \GEN_MIN_FOR_ASYNC.lite_min_count[2]_i_1 + (.I0(lite_min_count[1]), + .I1(lite_min_count[3]), + .I2(lite_min_assert_sftrst), + .I3(lite_min_count[0]), + .I4(lite_min_count[2]), + .O(\GEN_MIN_FOR_ASYNC.lite_min_count[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hEA00AA00AA00AA00)) + \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2 + (.I0(lite_all_idle), + .I1(lite_min_count[1]), + .I2(lite_min_count[3]), + .I3(lite_min_assert_sftrst), + .I4(lite_min_count[0]), + .I5(lite_min_count[2]), + .O(\GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair270" *) + LUT5 #( + .INIT(32'hE6CCCCCC)) + \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_3 + (.I0(lite_min_count[1]), + .I1(lite_min_count[3]), + .I2(lite_min_assert_sftrst), + .I3(lite_min_count[0]), + .I4(lite_min_count[2]), + .O(\GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_3_n_0 )); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[26] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[26]_i_1_n_0 ), - .Q(s_axi_lite_rdata[26]), - .R(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[27] + \GEN_MIN_FOR_ASYNC.lite_min_count_reg[0] (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[27]_i_1_n_0 ), - .Q(s_axi_lite_rdata[27]), - .R(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 )); + .CE(\GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0 ), + .D(\GEN_MIN_FOR_ASYNC.lite_min_count[0]_i_1__0_n_0 ), + .Q(lite_min_count[0]), + .R(\GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2 )); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[28] + \GEN_MIN_FOR_ASYNC.lite_min_count_reg[1] (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_1_n_0 ), - .Q(s_axi_lite_rdata[28]), - .R(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 )); + .CE(\GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0 ), + .D(\GEN_MIN_FOR_ASYNC.lite_min_count[1]_i_1_n_0 ), + .Q(lite_min_count[1]), + .R(\GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2 )); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[29] + \GEN_MIN_FOR_ASYNC.lite_min_count_reg[2] (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(ip2axi_rddata_captured[29]), - .Q(s_axi_lite_rdata[29]), - .R(1'b0)); + .CE(\GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0 ), + .D(\GEN_MIN_FOR_ASYNC.lite_min_count[2]_i_1_n_0 ), + .Q(lite_min_count[2]), + .R(\GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2 )); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[2] + \GEN_MIN_FOR_ASYNC.lite_min_count_reg[3] (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(ip2axi_rddata_captured[2]), - .Q(s_axi_lite_rdata[2]), - .R(1'b0)); + .CE(\GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0 ), + .D(\GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_3_n_0 ), + .Q(lite_min_count[3]), + .R(\GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2 )); + (* SOFT_HLUTNM = "soft_lutpair266" *) + LUT5 #( + .INIT(32'h80000000)) + \GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_i_2__0 + (.I0(prmry_min_count[2]), + .I1(prmry_min_count[0]), + .I2(prmry_min_assert_sftrst), + .I3(prmry_min_count[3]), + .I4(prmry_min_count[1]), + .O(p_11_out)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[30] - (.C(s_axi_lite_aclk), + \GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(ip2axi_rddata_captured[30]), - .Q(s_axi_lite_rdata[30]), + .D(\GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_4 ), + .Q(prmry_min_assert_sftrst), .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair266" *) + LUT5 #( + .INIT(32'h8000FFFF)) + \GEN_MIN_FOR_ASYNC.prmry_min_count[0]_i_1__0 + (.I0(prmry_min_count[1]), + .I1(prmry_min_count[3]), + .I2(prmry_min_assert_sftrst), + .I3(prmry_min_count[2]), + .I4(prmry_min_count[0]), + .O(\GEN_MIN_FOR_ASYNC.prmry_min_count[0]_i_1__0_n_0 )); + LUT5 #( + .INIT(32'hD5AA55AA)) + \GEN_MIN_FOR_ASYNC.prmry_min_count[1]_i_1 + (.I0(prmry_min_count[1]), + .I1(prmry_min_count[3]), + .I2(prmry_min_assert_sftrst), + .I3(prmry_min_count[0]), + .I4(prmry_min_count[2]), + .O(\GEN_MIN_FOR_ASYNC.prmry_min_count[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair268" *) + LUT5 #( + .INIT(32'hD5FFAA00)) + \GEN_MIN_FOR_ASYNC.prmry_min_count[2]_i_1 + (.I0(prmry_min_count[1]), + .I1(prmry_min_count[3]), + .I2(prmry_min_assert_sftrst), + .I3(prmry_min_count[0]), + .I4(prmry_min_count[2]), + .O(\GEN_MIN_FOR_ASYNC.prmry_min_count[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hEA00AA00AA00AA00)) + \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2 + (.I0(\cmnds_queued_reg[0] ), + .I1(prmry_min_count[1]), + .I2(prmry_min_count[3]), + .I3(prmry_min_assert_sftrst), + .I4(prmry_min_count[0]), + .I5(prmry_min_count[2]), + .O(\GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair268" *) + LUT5 #( + .INIT(32'hE6CCCCCC)) + \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_3 + (.I0(prmry_min_count[1]), + .I1(prmry_min_count[3]), + .I2(prmry_min_assert_sftrst), + .I3(prmry_min_count[0]), + .I4(prmry_min_count[2]), + .O(\GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_3_n_0 )); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[31] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_2_n_0 ), - .Q(s_axi_lite_rdata[31]), - .R(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 )); + \GEN_MIN_FOR_ASYNC.prmry_min_count_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0 ), + .D(\GEN_MIN_FOR_ASYNC.prmry_min_count[0]_i_1__0_n_0 ), + .Q(prmry_min_count[0]), + .R(\GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_3 )); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[3] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(ip2axi_rddata_captured[3]), - .Q(s_axi_lite_rdata[3]), - .R(1'b0)); + \GEN_MIN_FOR_ASYNC.prmry_min_count_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0 ), + .D(\GEN_MIN_FOR_ASYNC.prmry_min_count[1]_i_1_n_0 ), + .Q(prmry_min_count[1]), + .R(\GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_3 )); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[4] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(ip2axi_rddata_captured[4]), - .Q(s_axi_lite_rdata[4]), - .R(1'b0)); + \GEN_MIN_FOR_ASYNC.prmry_min_count_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0 ), + .D(\GEN_MIN_FOR_ASYNC.prmry_min_count[2]_i_1_n_0 ), + .Q(prmry_min_count[2]), + .R(\GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_3 )); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[5] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[5]_i_1_n_0 ), - .Q(s_axi_lite_rdata[5]), - .R(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 )); + \GEN_MIN_FOR_ASYNC.prmry_min_count_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0 ), + .D(\GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_3_n_0 ), + .Q(prmry_min_count[3]), + .R(\GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_3 )); + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized5 \GEN_RESET_FOR_ASYNC.AXIS_RESET_CDC_I + (.m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .prmry_in(resetn_i), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk), + .scndry_out(scndry_out)); + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized4 \GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I + (.\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[2] (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[2] ), + .assert_sftrst_d1(assert_sftrst_d1), + .\dmacr_i_reg[2] (\dmacr_i_reg[2] ), + .halt_i0(halt_i0), + .halt_i_reg(\GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_4 ), + .halt_i_reg_0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ), + .halt_reset_reg(halt_i_reg_0), + .hrd_resetn_i_reg(prmry_in), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .min_assert_sftrst(min_assert_sftrst), + .out(out), + .prmry_in(resetn_i), + .prmry_reset2_0(prmry_reset2_0), + .reset_counts_5(reset_counts_5), + .reset_counts_reg(reset_counts_reg), + .run_stop_d1_reg(\GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_1 ), + .s2mm_axi2ip_wrce(s2mm_axi2ip_wrce), + .s2mm_dmacr(s2mm_dmacr), + .s2mm_soft_reset(s2mm_soft_reset), + .s2mm_stop(s2mm_stop), + .s_axi_lite_aclk(s_axi_lite_aclk), + .s_soft_reset_i(s_soft_reset_i), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0(sig_s2mm_dm_prmry_resetn)); + LUT5 #( + .INIT(32'h00000002)) + \GEN_STS_GRTR_THAN_8.undrflo_err_i_1 + (.I0(CO), + .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ), + .I2(s2mm_soft_reset), + .I3(dma_err), + .I4(Q), + .O(p_12_out)); + (* SOFT_HLUTNM = "soft_lutpair272" *) + LUT2 #( + .INIT(4'hE)) + \I_RESET/sig_s_h_halt_reg_i_1 + (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ), + .I1(sig_rst2all_stop_request_6), + .O(sig_s_h_halt_reg_reg)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[6] - (.C(s_axi_lite_aclk), + assert_sftrst_d1_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(ip2axi_rddata_captured[6]), - .Q(s_axi_lite_rdata[6]), + .D(min_assert_sftrst), + .Q(assert_sftrst_d1), .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair272" *) + LUT4 #( + .INIT(16'hFEFF)) + \cmnds_queued[7]_i_1__0 + (.I0(dma_err), + .I1(s2mm_soft_reset), + .I2(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ), + .I3(out), + .O(\cmnds_queued_reg[7] )); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[7] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[7]_i_1_n_0 ), - .Q(s_axi_lite_rdata[7]), - .R(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[8] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[8]_i_1_n_0 ), - .Q(s_axi_lite_rdata[8]), - .R(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[9] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[9]_i_1_n_0 ), - .Q(s_axi_lite_rdata[9]), - .R(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0 )); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[0] - (.C(s_axi_lite_aclk), + halt_i_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[0]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[0]), + .D(\GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_4 ), + .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ), .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + LUT6 #( + .INIT(64'h222222222222F222)) + halt_reset_i_1 + (.I0(halt_i_reg_0), + .I1(s2mm_dmacr), + .I2(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ), + .I3(s2mm_halt_cmplt), + .I4(s2mm_soft_reset), + .I5(s2mm_stop), + .O(halt_reset_i_1_n_0)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[10] - (.C(s_axi_lite_aclk), + halt_reset_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[10]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[10]), + .D(halt_reset_i_1_n_0), + .Q(halt_i_reg_0), .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) FDRE #( - .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[11] - (.C(s_axi_lite_aclk), + .INIT(1'b1)) + prmry_resetn_i_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[11]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[11]), + .D(resetn_i), + .Q(in0), .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[12] - (.C(s_axi_lite_aclk), + run_stop_d1_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[12]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[12]), + .D(\GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_1 ), + .Q(run_stop_d1), .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[13] - (.C(s_axi_lite_aclk), + s_soft_reset_i_d1_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[13]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[13]), + .D(s_soft_reset_i), + .Q(s_soft_reset_i_d1), .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[14] - (.C(s_axi_lite_aclk), + s_soft_reset_i_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[14]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[14]), + .D(s_soft_reset_i0_3), + .Q(s_soft_reset_i), .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[15] - (.C(s_axi_lite_aclk), + soft_reset_d1_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[15]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[15]), + .D(s2mm_soft_reset), + .Q(soft_reset_d1), .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) +endmodule + +(* ORIG_REF_NAME = "axi_vdma_rst_module" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_rst_module + (out, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0, + \GEN_LINEBUF_NO_SOF.vsize_counter_reg[12] , + sts_tready_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0_0, + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from , + soft_reset_d1, + prmry_in, + mm2s_halt, + run_stop_d1, + s2mm_halt, + SR, + prmry_reset2, + prmry_reset2_0, + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0] , + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[1] , + \dmacr_i_reg[2] , + \GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]_0 , + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_0 , + \dmacr_i_reg[2]_0 , + prmry_reset2_1, + p_12_out, + \FSM_sequential_dmacntrl_cs_reg[2] , + halt_reset, + halt_reset_2, + WR_EN, + \cmnds_queued_reg[7] , + \cmnds_queued_reg[7]_0 , + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_reg , + \GEN_LINEBUF_NO_SOF.s_axis_fifo_ainit_nosync_reg_reg , + sig_s_h_halt_reg_reg, + reset_counts_reg, + reset_counts_reg_0, + sig_s_h_halt_reg_reg_0, + m_axi_mm2s_aclk, + s_axi_lite_aclk, + m_axis_mm2s_aclk, + m_axi_s2mm_aclk, + s_axis_s2mm_aclk, + p_77_out, + s_soft_reset_i0, + s2mm_soft_reset, + s_soft_reset_i0_3, + axi_resetn, + stop, + p_71_out, + s2mm_dmacr, + s2mm_stop, + mm2s_axi2ip_wrce, + D, + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 , + p_15_out, + s2mm_axi2ip_wrce, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[2] , + CO, + dma_err, + Q, + halt_i0, + hold_ff_q_reg, + p_24_out, + sig_s_ready_out_reg, + FULL, + dma_err_4, + d_tready_before_fsync_clr_flag1, + d_tready_before_fsync, + s2mm_dmasr_halted_s, + sig_rst2all_stop_request, + reset_counts, + reset_counts_5, + sig_rst2all_stop_request_6, + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 , + \cmnds_queued_reg[0] , + mm2s_halt_cmplt, + s2mm_halt_cmplt); + output out; + output sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0; + output \GEN_LINEBUF_NO_SOF.vsize_counter_reg[12] ; + output sts_tready_reg; + output sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0_0; + output \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from ; + output soft_reset_d1; + output prmry_in; + output mm2s_halt; + output run_stop_d1; + output s2mm_halt; + output [0:0]SR; + output prmry_reset2; + output prmry_reset2_0; + output [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0] ; + output [0:0]\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[1] ; + output \dmacr_i_reg[2] ; + output [0:0]\GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]_0 ; + output [0:0]\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_0 ; + output \dmacr_i_reg[2]_0 ; + output prmry_reset2_1; + output p_12_out; + output \FSM_sequential_dmacntrl_cs_reg[2] ; + output halt_reset; + output halt_reset_2; + output WR_EN; + output [0:0]\cmnds_queued_reg[7] ; + output [0:0]\cmnds_queued_reg[7]_0 ; + output \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_reg ; + output \GEN_LINEBUF_NO_SOF.s_axis_fifo_ainit_nosync_reg_reg ; + output sig_s_h_halt_reg_reg; + output reset_counts_reg; + output reset_counts_reg_0; + output sig_s_h_halt_reg_reg_0; + input m_axi_mm2s_aclk; + input s_axi_lite_aclk; + input m_axis_mm2s_aclk; + input m_axi_s2mm_aclk; + input s_axis_s2mm_aclk; + input p_77_out; + input s_soft_reset_i0; + input s2mm_soft_reset; + input s_soft_reset_i0_3; + input axi_resetn; + input stop; + input [0:0]p_71_out; + input [0:0]s2mm_dmacr; + input s2mm_stop; + input [0:0]mm2s_axi2ip_wrce; + input [0:0]D; + input \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ; + input p_15_out; + input [0:0]s2mm_axi2ip_wrce; + input [0:0]\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[2] ; + input [0:0]CO; + input dma_err; + input [0:0]Q; + input halt_i0; + input hold_ff_q_reg; + input p_24_out; + input sig_s_ready_out_reg; + input FULL; + input dma_err_4; + input d_tready_before_fsync_clr_flag1; + input d_tready_before_fsync; + input s2mm_dmasr_halted_s; + input sig_rst2all_stop_request; + input reset_counts; + input reset_counts_5; + input sig_rst2all_stop_request_6; + input \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ; + input \cmnds_queued_reg[0] ; + input mm2s_halt_cmplt; + input s2mm_halt_cmplt; + + wire [0:0]CO; + wire [0:0]D; + wire \FSM_sequential_dmacntrl_cs_reg[2] ; + wire FULL; + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ; + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ; + wire [0:0]\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_0 ; + wire [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0] ; + wire [0:0]\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[1] ; + wire \GEN_LINEBUF_NO_SOF.s_axis_fifo_ainit_nosync_reg_reg ; + wire [0:0]\GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]_0 ; + wire [0:0]\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[2] ; + wire \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_reg ; + wire [0:0]Q; + wire [0:0]SR; + wire WR_EN; + wire axi_resetn; + wire \cmnds_queued_reg[0] ; + wire [0:0]\cmnds_queued_reg[7] ; + wire [0:0]\cmnds_queued_reg[7]_0 ; + wire d_tready_before_fsync; + wire d_tready_before_fsync_clr_flag1; + wire dma_err; + wire dma_err_4; + wire \dmacr_i_reg[2] ; + wire \dmacr_i_reg[2]_0 ; + wire halt_i0; + wire halt_reset; + wire halt_reset_2; + wire hold_ff_q_reg; + wire m_axi_mm2s_aclk; + wire m_axi_s2mm_aclk; + wire m_axis_mm2s_aclk; + wire [0:0]mm2s_axi2ip_wrce; + wire mm2s_halt; + wire mm2s_halt_cmplt; + wire p_12_out; + wire p_15_out; + wire p_24_out; + wire [0:0]p_71_out; + wire p_77_out; + wire prmry_in; + wire prmry_reset2; + wire prmry_reset2_0; + wire prmry_reset2_1; + wire reset_counts; + wire reset_counts_5; + wire reset_counts_reg; + wire reset_counts_reg_0; + wire run_stop_d1; + wire [0:0]s2mm_axi2ip_wrce; + wire [0:0]s2mm_dmacr; + wire s2mm_dmasr_halted_s; + wire s2mm_halt; + wire s2mm_halt_cmplt; + wire s2mm_soft_reset; + wire s2mm_stop; + wire s_axi_lite_aclk; + wire s_axis_s2mm_aclk; + wire s_soft_reset_i0; + wire s_soft_reset_i0_3; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_mm2s_axis_resetn; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_mm2s_dm_prmry_resetn; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_mm2s_prmry_resetn; + wire sig_rst2all_stop_request; + wire sig_rst2all_stop_request_6; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_s2mm_axis_resetn; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_s2mm_dm_prmry_resetn; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_s2mm_prmry_resetn; + wire sig_s_h_halt_reg_reg; + wire sig_s_h_halt_reg_reg_0; + wire sig_s_ready_out_reg; + wire soft_reset_d1; + wire stop; + + assign \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from = sig_s2mm_axis_resetn; + assign \GEN_LINEBUF_NO_SOF.vsize_counter_reg[12] = sig_mm2s_axis_resetn; + assign out = sig_mm2s_prmry_resetn; + assign sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0 = sig_mm2s_dm_prmry_resetn; + assign sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0_0 = sig_s2mm_dm_prmry_resetn; + assign sts_tready_reg = sig_s2mm_prmry_resetn; + LUT1 #( + .INIT(2'h1)) + \GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out[5]_i_1 + (.I0(sig_mm2s_axis_resetn), + .O(\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out[5]_i_1__0 + (.I0(sig_s2mm_axis_resetn), + .O(prmry_reset2_1)); + LUT1 #( + .INIT(2'h1)) + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_1 + (.I0(sig_mm2s_prmry_resetn), + .O(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0] )); + LUT1 #( + .INIT(2'h1)) + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_1 + (.I0(sig_s2mm_prmry_resetn), + .O(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[1] )); + LUT3 #( + .INIT(8'h0D)) + \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_1 + (.I0(sig_mm2s_axis_resetn), + .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ), + .I2(p_15_out), + .O(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]_0 )); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_reset \GEN_RESET_FOR_MM2S.RESET_I + (.D(D), + .FULL(FULL), + .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ), + .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from (mm2s_halt), + .\GEN_LINEBUF_NO_SOF.s_axis_fifo_ainit_nosync_reg_reg (\GEN_LINEBUF_NO_SOF.s_axis_fifo_ainit_nosync_reg_reg ), + .WR_EN(WR_EN), + .\cmnds_queued_reg[7] (\cmnds_queued_reg[7] ), + .dma_err_4(dma_err_4), + .\dmacr_i_reg[2] (\dmacr_i_reg[2] ), + .halt_i_reg_0(halt_reset), + .hold_ff_q_reg(hold_ff_q_reg), + .in0(sig_mm2s_prmry_resetn), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .m_axis_mm2s_aclk(m_axis_mm2s_aclk), + .mm2s_axi2ip_wrce(mm2s_axi2ip_wrce), + .mm2s_halt_cmplt(mm2s_halt_cmplt), + .out(sig_mm2s_prmry_resetn), + .p_24_out(p_24_out), + .p_71_out(p_71_out), + .p_77_out(p_77_out), + .prmry_in(prmry_in), + .prmry_reset2(prmry_reset2), + .reset_counts(reset_counts), + .reset_counts_reg(reset_counts_reg), + .s_axi_lite_aclk(s_axi_lite_aclk), + .s_soft_reset_i0(s_soft_reset_i0), + .scndry_out(sig_mm2s_axis_resetn), + .sig_mm2s_dm_prmry_resetn(sig_mm2s_dm_prmry_resetn), + .sig_rst2all_stop_request(sig_rst2all_stop_request), + .sig_s_h_halt_reg_reg(sig_s_h_halt_reg_reg), + .sig_s_ready_out_reg(sig_s_ready_out_reg), + .stop(stop)); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_reset_2 \GEN_RESET_FOR_S2MM.RESET_I + (.CO(CO), + .\FSM_sequential_dmacntrl_cs_reg[2] (\FSM_sequential_dmacntrl_cs_reg[2] ), + .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from (s2mm_halt), + .\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[2] (\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[2] ), + .Q(Q), + .\cmnds_queued_reg[0] (\cmnds_queued_reg[0] ), + .\cmnds_queued_reg[7] (\cmnds_queued_reg[7]_0 ), + .dma_err(dma_err), + .\dmacr_i_reg[2] (\dmacr_i_reg[2]_0 ), + .halt_i0(halt_i0), + .halt_i_reg_0(halt_reset_2), + .in0(sig_s2mm_prmry_resetn), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(sig_s2mm_prmry_resetn), + .p_12_out(p_12_out), + .prmry_in(prmry_in), + .prmry_reset2_0(prmry_reset2_0), + .reset_counts_5(reset_counts_5), + .reset_counts_reg(reset_counts_reg_0), + .run_stop_d1(run_stop_d1), + .s2mm_axi2ip_wrce(s2mm_axi2ip_wrce), + .s2mm_dmacr(s2mm_dmacr), + .s2mm_halt_cmplt(s2mm_halt_cmplt), + .s2mm_soft_reset(s2mm_soft_reset), + .s2mm_stop(s2mm_stop), + .s_axi_lite_aclk(s_axi_lite_aclk), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk), + .s_soft_reset_i0_3(s_soft_reset_i0_3), + .scndry_out(sig_s2mm_axis_resetn), + .sig_rst2all_stop_request_6(sig_rst2all_stop_request_6), + .sig_s2mm_dm_prmry_resetn(sig_s2mm_dm_prmry_resetn), + .sig_s_h_halt_reg_reg(sig_s_h_halt_reg_reg_0), + .soft_reset_d1(soft_reset_d1)); + LUT4 #( + .INIT(16'hAAA8)) + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_i_1 + (.I0(d_tready_before_fsync_clr_flag1), + .I1(d_tready_before_fsync), + .I2(sig_s2mm_axis_resetn), + .I3(s2mm_dmasr_halted_s), + .O(\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_reg )); + LUT1 #( + .INIT(2'h1)) + awready_out_i_i_1 + (.I0(prmry_in), + .O(SR)); FDRE #( - .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[16] + .INIT(1'b1)) + hrd_resetn_i_reg (.C(s_axi_lite_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[16]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[16]), + .D(axi_resetn), + .Q(prmry_in), .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_s2mm_linebuf" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_s2mm_linebuf + (run_stop_reg, + p_in_d1_cdc_from, + s2mm_fsync_out_m_i, + s_axis_fifo_ainit_nosync, + s2mm_fsync_core, + delay_s2mm_fsync_core_till_mmap_done_flag, + DOUT, + EMPTY, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg , + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg , + strm_not_finished_no_dwidth, + s_valid0, + sig_last_reg_out_reg, + \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_s1_reg , + D, + prmry_reset2, + s_axis_s2mm_aclk, + SR, + s2mm_halt, + m_axi_s2mm_aclk, + s2mm_dmacr, + prmry_in_xored, + Q, + sig_reset_reg, + \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg , + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 , + M_VALID, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 , + s2mm_fsync_out_i, + out, + \sig_user_reg_out_reg[0] , + fsize_mismatch_err_s1, + drop_fsync_d_pulse_gen_fsize_less_err_d1, + s2mm_strm_wready, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] , + M_Last, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] , + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg_0 , + minusOp, + RD_EN, + DIN); + output run_stop_reg; + output p_in_d1_cdc_from; + output s2mm_fsync_out_m_i; + output s_axis_fifo_ainit_nosync; + output s2mm_fsync_core; + output delay_s2mm_fsync_core_till_mmap_done_flag; + output [8:0]DOUT; + output EMPTY; + output \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg ; + output \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ; + output strm_not_finished_no_dwidth; + output s_valid0; + output sig_last_reg_out_reg; + output \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_s1_reg ; + output [12:0]D; + input prmry_reset2; + input s_axis_s2mm_aclk; + input [0:0]SR; + input s2mm_halt; + input m_axi_s2mm_aclk; + input [2:0]s2mm_dmacr; + input prmry_in_xored; + input [12:0]Q; + input sig_reset_reg; + input [0:0]\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg ; + input \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ; + input M_VALID; + input \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ; + input s2mm_fsync_out_i; + input out; + input \sig_user_reg_out_reg[0] ; + input fsize_mismatch_err_s1; + input drop_fsync_d_pulse_gen_fsize_less_err_d1; + input s2mm_strm_wready; + input [0:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] ; + input M_Last; + input \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ; + input \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg_0 ; + input [11:0]minusOp; + input RD_EN; + input [7:0]DIN; + + wire [12:0]D; + wire [7:0]DIN; + wire [8:0]DOUT; + wire EMPTY; + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ; + wire [0:0]\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_s1_reg ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_2 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF_n_1 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.RUNSTOP_AXIS_0_CDC_I_FLUSH_SOF_n_1 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.STRM_WR_HALT_CDC_I_n_3 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.STRM_WR_HALT_CDC_I_n_7 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_1 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_10 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_11 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_12 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_13 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_14 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_2 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_25 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_3 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_4 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_5 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_6 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_7 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_8 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_9 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_10_n_0 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_11_n_0 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_12_n_0 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_13_n_0 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_5_n_0 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_6_n_0 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_7_n_0 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_3_n_0 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_4_n_0 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_5_n_0 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_6_n_0 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_3_n_0 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_4_n_0 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_5_n_0 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_6_n_0 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_i_8_n_1 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_i_8_n_2 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_i_8_n_3 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[4]_i_2_n_0 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[4]_i_2_n_1 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[4]_i_2_n_2 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[4]_i_2_n_3 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[8]_i_2_n_0 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[8]_i_2_n_1 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[8]_i_2_n_2 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[8]_i_2_n_3 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg_n_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg_0 ; + wire [0:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ; + wire M_Last; + wire M_VALID; + wire [12:0]Q; + wire RD_EN; + wire [0:0]SR; + (* async_reg = "true" *) wire [12:0]crnt_vsize_cdc_tig; + (* async_reg = "true" *) wire [12:0]crnt_vsize_d1; + (* async_reg = "true" *) wire [10:0]data_count_af_threshold_cdc_tig; + (* async_reg = "true" *) wire [10:0]data_count_af_threshold_d1; + wire delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s; + wire delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1; + wire delay_s2mm_fsync_core_till_mmap_done_flag; + wire delay_s2mm_fsync_core_till_mmap_done_flag_d1; + wire [12:0]done_vsize_counter; + wire drop_fsync_d_pulse_gen_fsize_less_err_d1; + wire fifo_full_i; + wire fsize_err_to_dm_halt_flag; + wire fsize_mismatch_err_s1; + (* async_reg = "true" *) wire [1:0]fsync_src_select_cdc_tig; + (* async_reg = "true" *) wire [1:0]fsync_src_select_d1; + wire m_axi_s2mm_aclk; + wire [11:0]minusOp; + wire [12:1]minusOp_1; + wire mmap_not_finished_s; + wire out; + wire p_3_out; + wire p_in_d1_cdc_from; + wire prmry_in_xored; + wire prmry_reset2; + wire run_stop_reg; + wire [2:0]s2mm_dmacr; + wire s2mm_fsync_core; + wire s2mm_fsync_out_i; + wire s2mm_fsync_out_m_i; + wire s2mm_halt; + wire s2mm_strm_wready; + wire s_axis_fifo_ainit_nosync; + wire s_axis_s2mm_aclk; + wire s_valid0; + wire sig_last_reg_out_reg; + wire sig_reset_reg; + wire \sig_user_reg_out_reg[0] ; + wire strm_not_finished_no_dwidth; + wire [3:3]\NLW_GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_i_8_CO_UNCONNECTED ; + + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized27 \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF + (.E(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3 ), + .\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.s2mm_fsync_out_m_d1_reg (s2mm_fsync_out_m_i), + .\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] (\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_5_n_0 ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[3] (\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_6_n_0 ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[6] (\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_14 ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[6]_0 (\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_7_n_0 ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg (\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_2 ), + .Q(done_vsize_counter[0]), + .SR(SR), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .p_in_d1_cdc_from(p_in_d1_cdc_from), + .prmry_in_xored(prmry_in_xored), + .prmry_reset2(prmry_reset2), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk), + .sig_s_ready_out_reg(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_25 )); + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized29 \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF + (.\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 (run_stop_reg), + .\GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_reg (\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF_n_1 ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_reg_0 (delay_s2mm_fsync_core_till_mmap_done_flag), + .\GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg (\GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg_n_0 ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ), + .SR(SR), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .mmap_not_finished_s(mmap_not_finished_s), + .out(out), + .prmry_reset2(prmry_reset2), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk), + .\sig_user_reg_out_reg[0] (\sig_user_reg_out_reg[0] )); + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized26 \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.RUNSTOP_AXIS_0_CDC_I_FLUSH_SOF + (.\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 (\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.STRM_WR_HALT_CDC_I_n_3 ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg (run_stop_reg), + .\GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg_0 (\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.RUNSTOP_AXIS_0_CDC_I_FLUSH_SOF_n_1 ), + .SR(SR), + .delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s(delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out), + .prmry_reset2(prmry_reset2), + .s2mm_dmacr(s2mm_dmacr[0]), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk), + .\sig_user_reg_out_reg[0] (\sig_user_reg_out_reg[0] )); + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized25 \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.STRM_WR_HALT_CDC_I + (.FULL(fifo_full_i), + .\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_s1_reg (\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_s1_reg ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg (\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.STRM_WR_HALT_CDC_I_n_3 ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_reg (delay_s2mm_fsync_core_till_mmap_done_flag), + .\GEN_S2MM_FLUSH_SOF_LOGIC.fsize_err_to_dm_halt_flag_reg (\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.STRM_WR_HALT_CDC_I_n_7 ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg_0 ), + .M_VALID(M_VALID), + .SR(SR), + .delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s(delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s), + .delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1(delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1), + .delay_s2mm_fsync_core_till_mmap_done_flag_d1(delay_s2mm_fsync_core_till_mmap_done_flag_d1), + .drop_fsync_d_pulse_gen_fsize_less_err_d1(drop_fsync_d_pulse_gen_fsize_less_err_d1), + .fsize_err_to_dm_halt_flag(fsize_err_to_dm_halt_flag), + .fsize_mismatch_err_s1(fsize_mismatch_err_s1), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .mmap_not_finished_s(mmap_not_finished_s), + .out(out), + .p_3_out(p_3_out), + .prmry_reset2(prmry_reset2), + .run_stop_reg(run_stop_reg), + .s2mm_fsync_core(s2mm_fsync_core), + .s2mm_fsync_out_i(s2mm_fsync_out_i), + .s2mm_halt(s2mm_halt), + .s_axis_fifo_ainit_nosync(s_axis_fifo_ainit_nosync), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk), + .s_valid0(s_valid0), + .sig_last_reg_out_reg(sig_last_reg_out_reg), + .\sig_user_reg_out_reg[0] (\sig_user_reg_out_reg[0] )); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[17] - (.C(s_axi_lite_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[0] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[17]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[17]), + .D(Q[0]), + .Q(crnt_vsize_cdc_tig[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[18] - (.C(s_axi_lite_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[10] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[18]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[18]), + .D(Q[10]), + .Q(crnt_vsize_cdc_tig[10]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[19] - (.C(s_axi_lite_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[11] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[19]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[19]), + .D(Q[11]), + .Q(crnt_vsize_cdc_tig[11]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[1] - (.C(s_axi_lite_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[1]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[1]), + .D(Q[12]), + .Q(crnt_vsize_cdc_tig[12]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[20] - (.C(s_axi_lite_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[1] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[20]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[20]), + .D(Q[1]), + .Q(crnt_vsize_cdc_tig[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[21] - (.C(s_axi_lite_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[2] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[21]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[21]), + .D(Q[2]), + .Q(crnt_vsize_cdc_tig[2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[22] - (.C(s_axi_lite_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[3] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[22]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[22]), + .D(Q[3]), + .Q(crnt_vsize_cdc_tig[3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[23] - (.C(s_axi_lite_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[4] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[23]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[23]), + .D(Q[4]), + .Q(crnt_vsize_cdc_tig[4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[24] - (.C(s_axi_lite_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[5] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[24]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[24]), + .D(Q[5]), + .Q(crnt_vsize_cdc_tig[5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[25] - (.C(s_axi_lite_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[6] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[25]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[25]), + .D(Q[6]), + .Q(crnt_vsize_cdc_tig[6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[26] - (.C(s_axi_lite_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[7] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[26]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[26]), + .D(Q[7]), + .Q(crnt_vsize_cdc_tig[7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[27] - (.C(s_axi_lite_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[8] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[27]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[27]), + .D(Q[8]), + .Q(crnt_vsize_cdc_tig[8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[28] - (.C(s_axi_lite_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[9] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[28]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[28]), + .D(Q[9]), + .Q(crnt_vsize_cdc_tig[9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[29] - (.C(s_axi_lite_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[0] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[29]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[29]), + .D(crnt_vsize_cdc_tig[0]), + .Q(crnt_vsize_d1[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[2] - (.C(s_axi_lite_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[10] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[2]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[2]), + .D(crnt_vsize_cdc_tig[10]), + .Q(crnt_vsize_d1[10]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[30] - (.C(s_axi_lite_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[11] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[30]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[30]), + .D(crnt_vsize_cdc_tig[11]), + .Q(crnt_vsize_d1[11]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[31] - (.C(s_axi_lite_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[31]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[31]), + .D(crnt_vsize_cdc_tig[12]), + .Q(crnt_vsize_d1[12]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[3] - (.C(s_axi_lite_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[1] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[3]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[3]), + .D(crnt_vsize_cdc_tig[1]), + .Q(crnt_vsize_d1[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[4] - (.C(s_axi_lite_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[2] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[4]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[4]), + .D(crnt_vsize_cdc_tig[2]), + .Q(crnt_vsize_d1[2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[5] - (.C(s_axi_lite_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[3] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[5]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[5]), + .D(crnt_vsize_cdc_tig[3]), + .Q(crnt_vsize_d1[3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[6] - (.C(s_axi_lite_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[4] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[6]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[6]), + .D(crnt_vsize_cdc_tig[4]), + .Q(crnt_vsize_d1[4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[7] - (.C(s_axi_lite_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[5] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[7]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[7]), + .D(crnt_vsize_cdc_tig[5]), + .Q(crnt_vsize_d1[5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[8] - (.C(s_axi_lite_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[6] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[8]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[8]), + .D(crnt_vsize_cdc_tig[6]), + .Q(crnt_vsize_d1[6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[9] - (.C(s_axi_lite_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[7] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(mm2s_ip2axi_rddata_d1[9]), - .Q(ip2axi_rddata_captured_mm2s_cdc_tig[9]), + .D(crnt_vsize_cdc_tig[7]), + .Q(crnt_vsize_d1[7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[0] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[8] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[0]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[0]), + .D(crnt_vsize_cdc_tig[8]), + .Q(crnt_vsize_d1[8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[10] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[9] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[10]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[10]), + .D(crnt_vsize_cdc_tig[9]), + .Q(crnt_vsize_d1[9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[11] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[0] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[11]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[11]), + .D(1'b0), + .Q(data_count_af_threshold_cdc_tig[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[10] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[12]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[12]), + .D(1'b0), + .Q(data_count_af_threshold_cdc_tig[10]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[1] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[13]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[13]), + .D(1'b0), + .Q(data_count_af_threshold_cdc_tig[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[14] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[2] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[14]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[14]), + .D(1'b0), + .Q(data_count_af_threshold_cdc_tig[2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[15] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[3] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[15]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[15]), + .D(1'b0), + .Q(data_count_af_threshold_cdc_tig[3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[16] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[4] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[16]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[16]), + .D(1'b0), + .Q(data_count_af_threshold_cdc_tig[4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[17] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[5] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[17]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[17]), + .D(1'b0), + .Q(data_count_af_threshold_cdc_tig[5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[6] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[18]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[18]), + .D(1'b0), + .Q(data_count_af_threshold_cdc_tig[6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[19] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[7] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[19]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[19]), + .D(1'b0), + .Q(data_count_af_threshold_cdc_tig[7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[1] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[8] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[1]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[1]), + .D(1'b0), + .Q(data_count_af_threshold_cdc_tig[8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[20] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[9] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[20]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[20]), + .D(1'b0), + .Q(data_count_af_threshold_cdc_tig[9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[21] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[0] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[21]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[21]), + .D(data_count_af_threshold_cdc_tig[0]), + .Q(data_count_af_threshold_d1[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[22] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[10] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[22]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[22]), + .D(data_count_af_threshold_cdc_tig[10]), + .Q(data_count_af_threshold_d1[10]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[23] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[1] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[23]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[23]), + .D(data_count_af_threshold_cdc_tig[1]), + .Q(data_count_af_threshold_d1[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[24] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[2] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[24]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[24]), + .D(data_count_af_threshold_cdc_tig[2]), + .Q(data_count_af_threshold_d1[2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[25] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[3] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[25]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[25]), + .D(data_count_af_threshold_cdc_tig[3]), + .Q(data_count_af_threshold_d1[3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[26] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[4] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[26]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[26]), + .D(data_count_af_threshold_cdc_tig[4]), + .Q(data_count_af_threshold_d1[4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[27] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[5] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[27]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[27]), + .D(data_count_af_threshold_cdc_tig[5]), + .Q(data_count_af_threshold_d1[5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[28] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[6] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[28]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[28]), + .D(data_count_af_threshold_cdc_tig[6]), + .Q(data_count_af_threshold_d1[6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[29] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[7] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[29]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[29]), + .D(data_count_af_threshold_cdc_tig[7]), + .Q(data_count_af_threshold_d1[7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[2] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[8] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[2]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[2]), + .D(data_count_af_threshold_cdc_tig[8]), + .Q(data_count_af_threshold_d1[8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[30] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[9] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[30]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[30]), + .D(data_count_af_threshold_cdc_tig[9]), + .Q(data_count_af_threshold_d1[9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[31] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.fsync_src_select_cdc_tig_reg[0] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[31]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[31]), + .D(s2mm_dmacr[1]), + .Q(fsync_src_select_cdc_tig[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[3] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.fsync_src_select_cdc_tig_reg[1] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[3]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[3]), + .D(s2mm_dmacr[2]), + .Q(fsync_src_select_cdc_tig[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.fsync_src_select_d1_reg[0] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[4]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[4]), + .D(fsync_src_select_cdc_tig[0]), + .Q(fsync_src_select_d1[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[5] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.fsync_src_select_d1_reg[1] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[5]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[5]), + .D(fsync_src_select_cdc_tig[1]), + .Q(fsync_src_select_d1[1]), .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + Arty_Z7_20_axi_vdma_0_0_axi_vdma_afifo_builtin__parameterized0 \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO + (.D({\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_1 ,\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_2 ,\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_3 ,\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_4 ,\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_5 ,\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_6 ,\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_7 ,\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_8 ,\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_9 ,\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_10 ,\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_11 ,\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_12 ,\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_13 }), + .DIN({M_Last,DIN}), + .DOUT(DOUT), + .EMPTY(EMPTY), + .FULL(fifo_full_i), + .\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out (s2mm_fsync_out_m_i), + .\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] (crnt_vsize_d1), + .\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] (\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_14 ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 (\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_5_n_0 ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg (\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_25 ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] (D), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ), + .M_VALID(M_VALID), + .Q(done_vsize_counter[6:0]), + .RD_EN(RD_EN), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .minusOp(minusOp), + .minusOp_1(minusOp_1), + .out(out), + .p_3_out(p_3_out), + .s2mm_fsync_out_i(s2mm_fsync_out_i), + .s2mm_strm_wready(s2mm_strm_wready), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk), + .sig_reset_reg(sig_reset_reg), + .strm_not_finished_no_dwidth(strm_not_finished_no_dwidth), + .\vsize_vid_reg[12] (Q)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[6] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[6]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[6]), + .D(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.RUNSTOP_AXIS_0_CDC_I_FLUSH_SOF_n_1 ), + .Q(delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s), .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[7] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1_reg + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[7]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[7]), + .D(delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s), + .Q(delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1), + .R(prmry_reset2)); + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_d1_reg + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ), + .Q(delay_s2mm_fsync_core_till_mmap_done_flag_d1), .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[8] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_reg + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[8]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[8]), + .D(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF_n_1 ), + .Q(delay_s2mm_fsync_core_till_mmap_done_flag), .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + LUT1 #( + .INIT(2'h1)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_10 + (.I0(done_vsize_counter[12]), + .O(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_10_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_11 + (.I0(done_vsize_counter[11]), + .O(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_11_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_12 + (.I0(done_vsize_counter[10]), + .O(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_12_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_13 + (.I0(done_vsize_counter[9]), + .O(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_13_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_5 + (.I0(done_vsize_counter[12]), + .I1(done_vsize_counter[10]), + .I2(done_vsize_counter[7]), + .I3(done_vsize_counter[11]), + .I4(done_vsize_counter[8]), + .I5(done_vsize_counter[9]), + .O(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_5_n_0 )); + LUT2 #( + .INIT(4'hE)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_6 + (.I0(done_vsize_counter[3]), + .I1(done_vsize_counter[4]), + .O(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_6_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_7 + (.I0(done_vsize_counter[6]), + .I1(done_vsize_counter[1]), + .I2(done_vsize_counter[5]), + .I3(done_vsize_counter[2]), + .O(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_7_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_3 + (.I0(done_vsize_counter[4]), + .O(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_3_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_4 + (.I0(done_vsize_counter[3]), + .O(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_5 + (.I0(done_vsize_counter[2]), + .O(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_5_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_6 + (.I0(done_vsize_counter[1]), + .O(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_6_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_3 + (.I0(done_vsize_counter[8]), + .O(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_3_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_4 + (.I0(done_vsize_counter[7]), + .O(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_5 + (.I0(done_vsize_counter[6]), + .O(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_5_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_6 + (.I0(done_vsize_counter[5]), + .O(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_6_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3 ), + .D(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_13 ), + .Q(done_vsize_counter[0]), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg )); + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3 ), + .D(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_3 ), + .Q(done_vsize_counter[10]), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg )); + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3 ), + .D(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_2 ), + .Q(done_vsize_counter[11]), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg )); + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3 ), + .D(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_1 ), + .Q(done_vsize_counter[12]), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg )); + CARRY4 \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_i_8 + (.CI(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[8]_i_2_n_0 ), + .CO({\NLW_GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_i_8_CO_UNCONNECTED [3],\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_i_8_n_1 ,\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_i_8_n_2 ,\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_i_8_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,done_vsize_counter[11:9]}), + .O(minusOp_1[12:9]), + .S({\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_10_n_0 ,\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_11_n_0 ,\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_12_n_0 ,\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_13_n_0 })); + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3 ), + .D(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_12 ), + .Q(done_vsize_counter[1]), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg )); + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3 ), + .D(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_11 ), + .Q(done_vsize_counter[2]), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg )); + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3 ), + .D(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_10 ), + .Q(done_vsize_counter[3]), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg )); + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3 ), + .D(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_9 ), + .Q(done_vsize_counter[4]), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg )); + CARRY4 \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[4]_i_2 + (.CI(1'b0), + .CO({\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[4]_i_2_n_0 ,\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[4]_i_2_n_1 ,\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[4]_i_2_n_2 ,\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[4]_i_2_n_3 }), + .CYINIT(done_vsize_counter[0]), + .DI(done_vsize_counter[4:1]), + .O(minusOp_1[4:1]), + .S({\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_3_n_0 ,\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_4_n_0 ,\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_5_n_0 ,\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_6_n_0 })); + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3 ), + .D(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_8 ), + .Q(done_vsize_counter[5]), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg )); + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3 ), + .D(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_7 ), + .Q(done_vsize_counter[6]), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg )); + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3 ), + .D(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_6 ), + .Q(done_vsize_counter[7]), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg )); + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3 ), + .D(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_5 ), + .Q(done_vsize_counter[8]), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg )); + CARRY4 \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[8]_i_2 + (.CI(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[4]_i_2_n_0 ), + .CO({\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[8]_i_2_n_0 ,\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[8]_i_2_n_1 ,\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[8]_i_2_n_2 ,\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[8]_i_2_n_3 }), + .CYINIT(1'b0), + .DI(done_vsize_counter[8:5]), + .O(minusOp_1[8:5]), + .S({\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_3_n_0 ,\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_4_n_0 ,\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_5_n_0 ,\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_6_n_0 })); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[9] - (.C(m_axi_mm2s_aclk), + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3 ), + .D(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_4 ), + .Q(done_vsize_counter[9]), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg )); + FDRE #( + .INIT(1'b0)) + \GEN_S2MM_FLUSH_SOF_LOGIC.fsize_err_to_dm_halt_flag_reg + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(wdata[9]), - .Q(mm2s_axi2ip_wrdata_cdc_tig[9]), + .D(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.STRM_WR_HALT_CDC_I_n_7 ), + .Q(fsize_err_to_dm_halt_flag), .R(1'b0)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [0]), - .Q(mm2s_ip2axi_rddata_d1[0]), - .R(1'b0)); + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg + (.C(m_axi_s2mm_aclk), + .CE(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3 ), + .D(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_2 ), + .Q(\GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg_n_0 ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg )); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_skid_buf" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_skid_buf + (out, + m_axis_mm2s_tvalid, + m_axis_mm2s_tlast, + m_axis_mm2s_tuser, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tlast_d1_reg , + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tvalid_d1_reg , + s_valid0, + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from , + m_axis_mm2s_tdata, + m_axis_mm2s_aclk, + m_axis_fifo_ainit_nosync, + fifo_dout, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg , + m_axis_mm2s_tready, + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 , + mm2s_axis_resetn, + p_15_out, + \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg ); + output out; + output m_axis_mm2s_tvalid; + output m_axis_mm2s_tlast; + output [0:0]m_axis_mm2s_tuser; + output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tlast_d1_reg ; + output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tvalid_d1_reg ; + output s_valid0; + output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ; + output [31:0]m_axis_mm2s_tdata; + input m_axis_mm2s_aclk; + input m_axis_fifo_ainit_nosync; + input [33:0]fifo_dout; + input \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; + input m_axis_mm2s_tready; + input \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ; + input mm2s_axis_resetn; + input p_15_out; + input \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg ; + + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ; + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tlast_d1_reg ; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tvalid_d1_reg ; + wire \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg ; + wire [33:0]fifo_dout; + wire m_axis_fifo_ainit_nosync; + wire m_axis_mm2s_aclk; + wire [31:0]m_axis_mm2s_tdata; + wire m_axis_mm2s_tlast; + wire m_axis_mm2s_tready; + wire [0:0]m_axis_mm2s_tuser; + wire mm2s_axis_resetn; + wire p_15_out; + wire s_valid0; + wire sig_data_reg_out_en; + wire [31:0]sig_data_skid_mux_out; + wire [31:0]sig_data_skid_reg; + wire sig_last_skid_mux_out; + wire sig_last_skid_reg; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_m_valid_dup; + wire sig_m_valid_dup_i_1__2_n_0; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_m_valid_out; + wire sig_reset_reg; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_s_ready_dup; + wire sig_s_ready_dup_i_1__2_n_0; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_s_ready_out; + wire sig_user_skid_mux_out; + wire sig_user_skid_reg; + + assign m_axis_mm2s_tvalid = sig_m_valid_out; + assign out = sig_s_ready_out; + LUT2 #( + .INIT(4'h2)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_1__4 + (.I0(\GEN_LINEBUF_NO_SOF.all_lines_xfred_reg ), + .I1(sig_m_valid_out), + .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from )); + LUT4 #( + .INIT(16'h0020)) + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tlast_d1_i_1 + (.I0(m_axis_mm2s_tlast), + .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ), + .I2(mm2s_axis_resetn), + .I3(p_15_out), + .O(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tlast_d1_reg )); + LUT4 #( + .INIT(16'h0020)) + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tvalid_d1_i_1 + (.I0(sig_m_valid_out), + .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ), + .I2(mm2s_axis_resetn), + .I3(p_15_out), + .O(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tvalid_d1_reg )); + LUT2 #( + .INIT(4'h8)) + s_valid_i_1__0 + (.I0(sig_m_valid_out), + .I1(m_axis_mm2s_tready), + .O(s_valid0)); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[0]_i_1__1 + (.I0(fifo_dout[0]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[0]), + .O(sig_data_skid_mux_out[0])); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[10]_i_1__1 + (.I0(fifo_dout[10]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[10]), + .O(sig_data_skid_mux_out[10])); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[11]_i_1__1 + (.I0(fifo_dout[11]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[11]), + .O(sig_data_skid_mux_out[11])); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[12]_i_1__1 + (.I0(fifo_dout[12]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[12]), + .O(sig_data_skid_mux_out[12])); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[13]_i_1__1 + (.I0(fifo_dout[13]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[13]), + .O(sig_data_skid_mux_out[13])); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[14]_i_1__1 + (.I0(fifo_dout[14]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[14]), + .O(sig_data_skid_mux_out[14])); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[15]_i_1__1 + (.I0(fifo_dout[15]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[15]), + .O(sig_data_skid_mux_out[15])); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[16]_i_1__1 + (.I0(fifo_dout[16]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[16]), + .O(sig_data_skid_mux_out[16])); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[17]_i_1__1 + (.I0(fifo_dout[17]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[17]), + .O(sig_data_skid_mux_out[17])); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[18]_i_1__1 + (.I0(fifo_dout[18]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[18]), + .O(sig_data_skid_mux_out[18])); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[19]_i_1__1 + (.I0(fifo_dout[19]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[19]), + .O(sig_data_skid_mux_out[19])); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[1]_i_1__1 + (.I0(fifo_dout[1]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[1]), + .O(sig_data_skid_mux_out[1])); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[20]_i_1__1 + (.I0(fifo_dout[20]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[20]), + .O(sig_data_skid_mux_out[20])); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[21]_i_1__1 + (.I0(fifo_dout[21]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[21]), + .O(sig_data_skid_mux_out[21])); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[22]_i_1__1 + (.I0(fifo_dout[22]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[22]), + .O(sig_data_skid_mux_out[22])); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[23]_i_1__1 + (.I0(fifo_dout[23]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[23]), + .O(sig_data_skid_mux_out[23])); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[24]_i_1__1 + (.I0(fifo_dout[24]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[24]), + .O(sig_data_skid_mux_out[24])); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[25]_i_1__1 + (.I0(fifo_dout[25]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[25]), + .O(sig_data_skid_mux_out[25])); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[26]_i_1__1 + (.I0(fifo_dout[26]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[26]), + .O(sig_data_skid_mux_out[26])); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[27]_i_1__1 + (.I0(fifo_dout[27]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[27]), + .O(sig_data_skid_mux_out[27])); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[28]_i_1__1 + (.I0(fifo_dout[28]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[28]), + .O(sig_data_skid_mux_out[28])); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[29]_i_1__1 + (.I0(fifo_dout[29]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[29]), + .O(sig_data_skid_mux_out[29])); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[2]_i_1__1 + (.I0(fifo_dout[2]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[2]), + .O(sig_data_skid_mux_out[2])); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[30]_i_1__1 + (.I0(fifo_dout[30]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[30]), + .O(sig_data_skid_mux_out[30])); + LUT2 #( + .INIT(4'hB)) + \sig_data_reg_out[31]_i_2 + (.I0(m_axis_mm2s_tready), + .I1(sig_m_valid_dup), + .O(sig_data_reg_out_en)); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[31]_i_3 + (.I0(fifo_dout[31]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[31]), + .O(sig_data_skid_mux_out[31])); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[3]_i_1__1 + (.I0(fifo_dout[3]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[3]), + .O(sig_data_skid_mux_out[3])); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[4]_i_1__1 + (.I0(fifo_dout[4]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[4]), + .O(sig_data_skid_mux_out[4])); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[5]_i_1__1 + (.I0(fifo_dout[5]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[5]), + .O(sig_data_skid_mux_out[5])); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[6]_i_1__1 + (.I0(fifo_dout[6]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[6]), + .O(sig_data_skid_mux_out[6])); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[7]_i_1__1 + (.I0(fifo_dout[7]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[7]), + .O(sig_data_skid_mux_out[7])); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[8]_i_1__1 + (.I0(fifo_dout[8]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[8]), + .O(sig_data_skid_mux_out[8])); + LUT3 #( + .INIT(8'hB8)) + \sig_data_reg_out[9]_i_1__1 + (.I0(fifo_dout[9]), + .I1(sig_s_ready_dup), + .I2(sig_data_skid_reg[9]), + .O(sig_data_skid_mux_out[9])); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[0] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[0]), + .Q(m_axis_mm2s_tdata[0]), + .R(m_axis_fifo_ainit_nosync)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[10] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[10]), + .Q(m_axis_mm2s_tdata[10]), + .R(m_axis_fifo_ainit_nosync)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[11] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[11]), + .Q(m_axis_mm2s_tdata[11]), + .R(m_axis_fifo_ainit_nosync)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[12] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[12]), + .Q(m_axis_mm2s_tdata[12]), + .R(m_axis_fifo_ainit_nosync)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[13] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[13]), + .Q(m_axis_mm2s_tdata[13]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [10]), - .Q(mm2s_ip2axi_rddata_d1[10]), - .R(1'b0)); + \sig_data_reg_out_reg[14] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[14]), + .Q(m_axis_mm2s_tdata[14]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [11]), - .Q(mm2s_ip2axi_rddata_d1[11]), - .R(1'b0)); + \sig_data_reg_out_reg[15] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[15]), + .Q(m_axis_mm2s_tdata[15]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [12]), - .Q(mm2s_ip2axi_rddata_d1[12]), - .R(1'b0)); + \sig_data_reg_out_reg[16] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[16]), + .Q(m_axis_mm2s_tdata[16]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[13] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [13]), - .Q(mm2s_ip2axi_rddata_d1[13]), - .R(1'b0)); + \sig_data_reg_out_reg[17] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[17]), + .Q(m_axis_mm2s_tdata[17]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[14] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [14]), - .Q(mm2s_ip2axi_rddata_d1[14]), - .R(1'b0)); + \sig_data_reg_out_reg[18] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[18]), + .Q(m_axis_mm2s_tdata[18]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [15]), - .Q(mm2s_ip2axi_rddata_d1[15]), - .R(1'b0)); + \sig_data_reg_out_reg[19] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[19]), + .Q(m_axis_mm2s_tdata[19]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[16] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [16]), - .Q(mm2s_ip2axi_rddata_d1[16]), - .R(1'b0)); + \sig_data_reg_out_reg[1] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[1]), + .Q(m_axis_mm2s_tdata[1]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[17] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [17]), - .Q(mm2s_ip2axi_rddata_d1[17]), - .R(1'b0)); + \sig_data_reg_out_reg[20] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[20]), + .Q(m_axis_mm2s_tdata[20]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[18] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [18]), - .Q(mm2s_ip2axi_rddata_d1[18]), - .R(1'b0)); + \sig_data_reg_out_reg[21] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[21]), + .Q(m_axis_mm2s_tdata[21]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[19] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [19]), - .Q(mm2s_ip2axi_rddata_d1[19]), - .R(1'b0)); + \sig_data_reg_out_reg[22] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[22]), + .Q(m_axis_mm2s_tdata[22]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [1]), - .Q(mm2s_ip2axi_rddata_d1[1]), - .R(1'b0)); + \sig_data_reg_out_reg[23] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[23]), + .Q(m_axis_mm2s_tdata[23]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[20] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [20]), - .Q(mm2s_ip2axi_rddata_d1[20]), - .R(1'b0)); + \sig_data_reg_out_reg[24] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[24]), + .Q(m_axis_mm2s_tdata[24]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[21] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [21]), - .Q(mm2s_ip2axi_rddata_d1[21]), - .R(1'b0)); + \sig_data_reg_out_reg[25] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[25]), + .Q(m_axis_mm2s_tdata[25]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[22] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [22]), - .Q(mm2s_ip2axi_rddata_d1[22]), - .R(1'b0)); + \sig_data_reg_out_reg[26] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[26]), + .Q(m_axis_mm2s_tdata[26]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[23] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [23]), - .Q(mm2s_ip2axi_rddata_d1[23]), - .R(1'b0)); + \sig_data_reg_out_reg[27] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[27]), + .Q(m_axis_mm2s_tdata[27]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[24] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [24]), - .Q(mm2s_ip2axi_rddata_d1[24]), - .R(1'b0)); + \sig_data_reg_out_reg[28] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[28]), + .Q(m_axis_mm2s_tdata[28]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[25] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [25]), - .Q(mm2s_ip2axi_rddata_d1[25]), - .R(1'b0)); + \sig_data_reg_out_reg[29] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[29]), + .Q(m_axis_mm2s_tdata[29]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[26] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [26]), - .Q(mm2s_ip2axi_rddata_d1[26]), - .R(1'b0)); + \sig_data_reg_out_reg[2] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[2]), + .Q(m_axis_mm2s_tdata[2]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[27] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [27]), - .Q(mm2s_ip2axi_rddata_d1[27]), - .R(1'b0)); + \sig_data_reg_out_reg[30] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[30]), + .Q(m_axis_mm2s_tdata[30]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[28] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [28]), - .Q(mm2s_ip2axi_rddata_d1[28]), - .R(1'b0)); + \sig_data_reg_out_reg[31] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[31]), + .Q(m_axis_mm2s_tdata[31]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[29] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [29]), - .Q(mm2s_ip2axi_rddata_d1[29]), - .R(1'b0)); + \sig_data_reg_out_reg[3] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[3]), + .Q(m_axis_mm2s_tdata[3]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [2]), - .Q(mm2s_ip2axi_rddata_d1[2]), - .R(1'b0)); + \sig_data_reg_out_reg[4] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[4]), + .Q(m_axis_mm2s_tdata[4]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[30] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [30]), - .Q(mm2s_ip2axi_rddata_d1[30]), - .R(1'b0)); + \sig_data_reg_out_reg[5] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[5]), + .Q(m_axis_mm2s_tdata[5]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [31]), - .Q(mm2s_ip2axi_rddata_d1[31]), - .R(1'b0)); + \sig_data_reg_out_reg[6] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[6]), + .Q(m_axis_mm2s_tdata[6]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [3]), - .Q(mm2s_ip2axi_rddata_d1[3]), - .R(1'b0)); + \sig_data_reg_out_reg[7] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[7]), + .Q(m_axis_mm2s_tdata[7]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [4]), - .Q(mm2s_ip2axi_rddata_d1[4]), - .R(1'b0)); + \sig_data_reg_out_reg[8] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[8]), + .Q(m_axis_mm2s_tdata[8]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [5]), - .Q(mm2s_ip2axi_rddata_d1[5]), - .R(1'b0)); + \sig_data_reg_out_reg[9] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_data_skid_mux_out[9]), + .Q(m_axis_mm2s_tdata[9]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [6]), - .Q(mm2s_ip2axi_rddata_d1[6]), - .R(1'b0)); + \sig_data_skid_reg_reg[0] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[0]), + .Q(sig_data_skid_reg[0]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [7]), - .Q(mm2s_ip2axi_rddata_d1[7]), - .R(1'b0)); + \sig_data_skid_reg_reg[10] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[10]), + .Q(sig_data_skid_reg[10]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [8]), - .Q(mm2s_ip2axi_rddata_d1[8]), - .R(1'b0)); + \sig_data_skid_reg_reg[11] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[11]), + .Q(sig_data_skid_reg[11]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 [9]), - .Q(mm2s_ip2axi_rddata_d1[9]), - .R(1'b0)); - (* SOFT_HLUTNM = "soft_lutpair5" *) - LUT2 #( - .INIT(4'h8)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.prepare_wrce_d1_i_1 - (.I0(lite_wr_addr_phase_finished_data_phase_started), - .I1(wvalid), - .O(prepare_wrce)); + \sig_data_skid_reg_reg[12] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[12]), + .Q(sig_data_skid_reg[12]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.prepare_wrce_d1_reg - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(prepare_wrce), - .Q(prepare_wrce_d1), - .R(SR)); - (* srl_name = "U0/\AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.prepare_wrce_pulse_lite_d6_reg_srl6 " *) - SRL16E #( - .INIT(16'h0000)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.prepare_wrce_pulse_lite_d6_reg_srl6 - (.A0(1'b1), - .A1(1'b0), - .A2(1'b1), - .A3(1'b0), - .CE(1'b1), - .CLK(s_axi_lite_aclk), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.prepare_wrce_pulse_lite_d6_reg_srl6_i_1_n_0 ), - .Q(prepare_wrce_pulse_lite_d6)); - (* SOFT_HLUTNM = "soft_lutpair5" *) - LUT3 #( - .INIT(8'h08)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.prepare_wrce_pulse_lite_d6_reg_srl6_i_1 - (.I0(wvalid), - .I1(lite_wr_addr_phase_finished_data_phase_started), - .I2(prepare_wrce_d1), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.prepare_wrce_pulse_lite_d6_reg_srl6_i_1_n_0 )); - LUT4 #( - .INIT(16'h0C88)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.rvalid_out_i_i_1 - (.I0(s_axi_lite_arready), - .I1(s_axi_lite_resetn), - .I2(s_axi_lite_rready), - .I3(s_axi_lite_rvalid), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.rvalid_out_i_i_1_n_0 )); + \sig_data_skid_reg_reg[13] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[13]), + .Q(sig_data_skid_reg[13]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.rvalid_out_i_reg - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.rvalid_out_i_i_1_n_0 ), - .Q(s_axi_lite_rvalid), - .R(1'b0)); - (* srl_name = "U0/\AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.sig_arvalid_arrived_d4_reg_srl3 " *) - SRL16E #( - .INIT(16'h0000)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.sig_arvalid_arrived_d4_reg_srl3 - (.A0(1'b0), - .A1(1'b1), - .A2(1'b0), - .A3(1'b0), - .CE(1'b1), - .CLK(s_axi_lite_aclk), - .D(sig_arvalid_arrived_d1), - .Q(sig_arvalid_arrived_d4)); + \sig_data_skid_reg_reg[14] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[14]), + .Q(sig_data_skid_reg[14]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.wready_out_i_reg - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(prepare_wrce_pulse_lite_d6), - .Q(s_axi_lite_wready), - .R(SR)); - LUT4 #( - .INIT(16'h7FFF)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i[31]_i_2 - (.I0(axi2ip_wraddr_captured_mm2s_cdc_tig[4]), - .I1(axi2ip_wraddr_captured_mm2s_cdc_tig[6]), - .I2(axi2ip_wraddr_captured_mm2s_cdc_tig[2]), - .I3(axi2ip_wraddr_captured_mm2s_cdc_tig[3]), - .O(\GEN_NUM_FSTORES_1.reg_module_start_address1_i[31]_i_2_n_0 )); + \sig_data_skid_reg_reg[15] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[15]), + .Q(sig_data_skid_reg[15]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \araddr_reg[2] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_araddr[0]), - .Q(p_2_in[0]), - .R(SR)); + \sig_data_skid_reg_reg[16] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[16]), + .Q(sig_data_skid_reg[16]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \araddr_reg[3] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_araddr[1]), - .Q(p_2_in[1]), - .R(SR)); + \sig_data_skid_reg_reg[17] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[17]), + .Q(sig_data_skid_reg[17]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \araddr_reg[4] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_araddr[2]), - .Q(p_2_in[2]), - .R(SR)); + \sig_data_skid_reg_reg[18] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[18]), + .Q(sig_data_skid_reg[18]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \araddr_reg[5] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_araddr[3]), - .Q(p_2_in[3]), - .R(SR)); + \sig_data_skid_reg_reg[19] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[19]), + .Q(sig_data_skid_reg[19]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \araddr_reg[6] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_araddr[4]), - .Q(p_2_in[4]), - .R(SR)); + \sig_data_skid_reg_reg[1] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[1]), + .Q(sig_data_skid_reg[1]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \araddr_reg[7] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_araddr[5]), - .Q(p_2_in[5]), - .R(SR)); + \sig_data_skid_reg_reg[20] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[20]), + .Q(sig_data_skid_reg[20]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - arvalid_reg - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_arvalid), - .Q(arvalid), - .R(SR)); + \sig_data_skid_reg_reg[21] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[21]), + .Q(sig_data_skid_reg[21]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \awaddr_reg[2] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_awaddr[0]), - .Q(awaddr[2]), - .R(SR)); + \sig_data_skid_reg_reg[22] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[22]), + .Q(sig_data_skid_reg[22]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \awaddr_reg[3] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_awaddr[1]), - .Q(awaddr[3]), - .R(SR)); + \sig_data_skid_reg_reg[23] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[23]), + .Q(sig_data_skid_reg[23]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \awaddr_reg[4] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_awaddr[2]), - .Q(awaddr[4]), - .R(SR)); + \sig_data_skid_reg_reg[24] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[24]), + .Q(sig_data_skid_reg[24]), + .R(m_axis_fifo_ainit_nosync)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[25] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[25]), + .Q(sig_data_skid_reg[25]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \awaddr_reg[5] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_awaddr[3]), - .Q(awaddr[5]), - .R(SR)); + \sig_data_skid_reg_reg[26] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[26]), + .Q(sig_data_skid_reg[26]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \awaddr_reg[6] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_awaddr[4]), - .Q(awaddr[6]), - .R(SR)); + \sig_data_skid_reg_reg[27] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[27]), + .Q(sig_data_skid_reg[27]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \awaddr_reg[7] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_awaddr[5]), - .Q(awaddr[7]), - .R(SR)); + \sig_data_skid_reg_reg[28] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[28]), + .Q(sig_data_skid_reg[28]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - awready_out_i_reg - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(sig_awvalid_detected__0), - .Q(s_axi_lite_awready), - .R(SR)); + \sig_data_skid_reg_reg[29] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[29]), + .Q(sig_data_skid_reg[29]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - awvalid_reg - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_awvalid), - .Q(awvalid), - .R(SR)); + \sig_data_skid_reg_reg[2] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[2]), + .Q(sig_data_skid_reg[2]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \axi2ip_rdaddr_captured_reg[2] - (.C(s_axi_lite_aclk), - .CE(sig_arvalid_detected__0), - .D(p_2_in[0]), - .Q(\axi2ip_rdaddr_captured_reg_n_0_[2] ), - .R(SR)); + \sig_data_skid_reg_reg[30] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[30]), + .Q(sig_data_skid_reg[30]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \axi2ip_rdaddr_captured_reg[3] - (.C(s_axi_lite_aclk), - .CE(sig_arvalid_detected__0), - .D(p_2_in[1]), - .Q(\axi2ip_rdaddr_captured_reg_n_0_[3] ), - .R(SR)); + \sig_data_skid_reg_reg[31] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[31]), + .Q(sig_data_skid_reg[31]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \axi2ip_rdaddr_captured_reg[4] - (.C(s_axi_lite_aclk), - .CE(sig_arvalid_detected__0), - .D(p_2_in[2]), - .Q(\axi2ip_rdaddr_captured_reg_n_0_[4] ), - .R(SR)); + \sig_data_skid_reg_reg[3] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[3]), + .Q(sig_data_skid_reg[3]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \axi2ip_rdaddr_captured_reg[5] - (.C(s_axi_lite_aclk), - .CE(sig_arvalid_detected__0), - .D(p_2_in[3]), - .Q(\axi2ip_rdaddr_captured_reg_n_0_[5] ), - .R(SR)); + \sig_data_skid_reg_reg[4] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[4]), + .Q(sig_data_skid_reg[4]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \axi2ip_rdaddr_captured_reg[6] - (.C(s_axi_lite_aclk), - .CE(sig_arvalid_detected__0), - .D(p_2_in[4]), - .Q(\axi2ip_rdaddr_captured_reg_n_0_[6] ), - .R(SR)); + \sig_data_skid_reg_reg[5] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[5]), + .Q(sig_data_skid_reg[5]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \axi2ip_rdaddr_captured_reg[7] - (.C(s_axi_lite_aclk), - .CE(sig_arvalid_detected__0), - .D(p_2_in[5]), - .Q(\axi2ip_rdaddr_captured_reg_n_0_[7] ), - .R(SR)); + \sig_data_skid_reg_reg[6] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[6]), + .Q(sig_data_skid_reg[6]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \axi2ip_wraddr_captured_reg[2] - (.C(s_axi_lite_aclk), - .CE(sig_awvalid_detected__0), - .D(awaddr[2]), - .Q(axi2ip_wraddr_captured[2]), - .R(SR)); + \sig_data_skid_reg_reg[7] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[7]), + .Q(sig_data_skid_reg[7]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \axi2ip_wraddr_captured_reg[3] - (.C(s_axi_lite_aclk), - .CE(sig_awvalid_detected__0), - .D(awaddr[3]), - .Q(axi2ip_wraddr_captured[3]), - .R(SR)); + \sig_data_skid_reg_reg[8] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[8]), + .Q(sig_data_skid_reg[8]), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \axi2ip_wraddr_captured_reg[4] - (.C(s_axi_lite_aclk), - .CE(sig_awvalid_detected__0), - .D(awaddr[4]), - .Q(axi2ip_wraddr_captured[4]), - .R(SR)); + \sig_data_skid_reg_reg[9] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[9]), + .Q(sig_data_skid_reg[9]), + .R(m_axis_fifo_ainit_nosync)); + LUT3 #( + .INIT(8'hB8)) + sig_last_reg_out_i_1__2 + (.I0(fifo_dout[32]), + .I1(sig_s_ready_dup), + .I2(sig_last_skid_reg), + .O(sig_last_skid_mux_out)); FDRE #( .INIT(1'b0)) - \axi2ip_wraddr_captured_reg[5] - (.C(s_axi_lite_aclk), - .CE(sig_awvalid_detected__0), - .D(awaddr[5]), - .Q(axi2ip_wraddr_captured[5]), - .R(SR)); + sig_last_reg_out_reg + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_last_skid_mux_out), + .Q(m_axis_mm2s_tlast), + .R(m_axis_fifo_ainit_nosync)); FDRE #( .INIT(1'b0)) - \axi2ip_wraddr_captured_reg[6] - (.C(s_axi_lite_aclk), - .CE(sig_awvalid_detected__0), - .D(awaddr[6]), - .Q(axi2ip_wraddr_captured[6]), - .R(SR)); + sig_last_skid_reg_reg + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[32]), + .Q(sig_last_skid_reg), + .R(m_axis_fifo_ainit_nosync)); + LUT6 #( + .INIT(64'h00000000000075F5)) + sig_m_valid_dup_i_1__2 + (.I0(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ), + .I1(sig_s_ready_dup), + .I2(sig_m_valid_dup), + .I3(m_axis_mm2s_tready), + .I4(m_axis_fifo_ainit_nosync), + .I5(sig_reset_reg), + .O(sig_m_valid_dup_i_1__2_n_0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) - \axi2ip_wraddr_captured_reg[7] - (.C(s_axi_lite_aclk), - .CE(sig_awvalid_detected__0), - .D(awaddr[7]), - .Q(axi2ip_wraddr_captured[7]), - .R(SR)); - LUT4 #( - .INIT(16'h0C88)) - bvalid_out_i_i_1 - (.I0(s_axi_lite_wready), - .I1(s_axi_lite_resetn), - .I2(s_axi_lite_bready), - .I3(s_axi_lite_bvalid), - .O(bvalid_out_i_i_1_n_0)); + sig_m_valid_dup_reg + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(sig_m_valid_dup_i_1__2_n_0), + .Q(sig_m_valid_dup), + .R(1'b0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) - bvalid_out_i_reg - (.C(s_axi_lite_aclk), + sig_m_valid_out_reg + (.C(m_axis_mm2s_aclk), .CE(1'b1), - .D(bvalid_out_i_i_1_n_0), - .Q(s_axi_lite_bvalid), - .R(1'b0)); - LUT2 #( - .INIT(4'h1)) - \dmacr_i[1]_i_2 - (.I0(axi2ip_wraddr_captured_mm2s_cdc_tig[6]), - .I1(axi2ip_wraddr_captured_mm2s_cdc_tig[5]), - .O(\dmacr_i[1]_i_2_n_0 )); - LUT1 #( - .INIT(2'h2)) - i_0 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[31])); - LUT1 #( - .INIT(2'h2)) - i_1 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[30])); - LUT1 #( - .INIT(2'h2)) - i_10 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[21])); - LUT1 #( - .INIT(2'h2)) - i_11 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[20])); - LUT1 #( - .INIT(2'h2)) - i_12 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[19])); - LUT1 #( - .INIT(2'h2)) - i_13 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[18])); - LUT1 #( - .INIT(2'h2)) - i_14 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[17])); - LUT1 #( - .INIT(2'h2)) - i_15 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[16])); - LUT1 #( - .INIT(2'h2)) - i_16 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[15])); - LUT1 #( - .INIT(2'h2)) - i_17 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[14])); - LUT1 #( - .INIT(2'h2)) - i_18 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[13])); - LUT1 #( - .INIT(2'h2)) - i_19 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[12])); - LUT1 #( - .INIT(2'h2)) - i_2 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[29])); - LUT1 #( - .INIT(2'h2)) - i_20 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[11])); - LUT1 #( - .INIT(2'h2)) - i_21 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[10])); - LUT1 #( - .INIT(2'h2)) - i_22 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[9])); - LUT1 #( - .INIT(2'h2)) - i_23 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[8])); - LUT1 #( - .INIT(2'h2)) - i_24 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[7])); - LUT1 #( - .INIT(2'h2)) - i_25 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[6])); - LUT1 #( - .INIT(2'h2)) - i_26 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[5])); - LUT1 #( - .INIT(2'h2)) - i_27 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[4])); - LUT1 #( - .INIT(2'h2)) - i_28 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[3])); - LUT1 #( - .INIT(2'h2)) - i_29 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[2])); - LUT1 #( - .INIT(2'h2)) - i_3 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[28])); - LUT1 #( - .INIT(2'h2)) - i_30 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[1])); - LUT1 #( - .INIT(2'h2)) - i_31 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[0])); - LUT1 #( - .INIT(2'h2)) - i_32 - (.I0(1'b0), - .O(axi2ip_rdaddr_captured_s2mm_cdc_tig[7])); - LUT1 #( - .INIT(2'h2)) - i_33 - (.I0(1'b0), - .O(axi2ip_rdaddr_captured_s2mm_cdc_tig[6])); - LUT1 #( - .INIT(2'h2)) - i_34 - (.I0(1'b0), - .O(axi2ip_rdaddr_captured_s2mm_cdc_tig[5])); - LUT1 #( - .INIT(2'h2)) - i_35 - (.I0(1'b0), - .O(axi2ip_rdaddr_captured_s2mm_cdc_tig[4])); - LUT1 #( - .INIT(2'h2)) - i_36 - (.I0(1'b0), - .O(axi2ip_rdaddr_captured_s2mm_cdc_tig[3])); - LUT1 #( - .INIT(2'h2)) - i_37 - (.I0(1'b0), - .O(axi2ip_rdaddr_captured_s2mm_cdc_tig[2])); - LUT1 #( - .INIT(2'h2)) - i_38 - (.I0(1'b0), - .O(axi2ip_wraddr_captured_s2mm_cdc_tig[7])); - LUT1 #( - .INIT(2'h2)) - i_39 - (.I0(1'b0), - .O(axi2ip_wraddr_captured_s2mm_cdc_tig[6])); - LUT1 #( - .INIT(2'h2)) - i_4 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[27])); - LUT1 #( - .INIT(2'h2)) - i_40 - (.I0(1'b0), - .O(axi2ip_wraddr_captured_s2mm_cdc_tig[5])); - LUT1 #( - .INIT(2'h2)) - i_41 - (.I0(1'b0), - .O(axi2ip_wraddr_captured_s2mm_cdc_tig[4])); - LUT1 #( - .INIT(2'h2)) - i_42 - (.I0(1'b0), - .O(axi2ip_wraddr_captured_s2mm_cdc_tig[3])); - LUT1 #( - .INIT(2'h2)) - i_43 - (.I0(1'b0), - .O(axi2ip_wraddr_captured_s2mm_cdc_tig[2])); - LUT1 #( - .INIT(2'h2)) - i_44 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[31])); - LUT1 #( - .INIT(2'h2)) - i_45 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[30])); - LUT1 #( - .INIT(2'h2)) - i_46 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[29])); - LUT1 #( - .INIT(2'h2)) - i_47 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[28])); - LUT1 #( - .INIT(2'h2)) - i_48 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[27])); - LUT1 #( - .INIT(2'h2)) - i_49 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[26])); - LUT1 #( - .INIT(2'h2)) - i_5 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[26])); - LUT1 #( - .INIT(2'h2)) - i_50 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[25])); - LUT1 #( - .INIT(2'h2)) - i_51 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[24])); - LUT1 #( - .INIT(2'h2)) - i_52 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[23])); - LUT1 #( - .INIT(2'h2)) - i_53 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[22])); - LUT1 #( - .INIT(2'h2)) - i_54 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[21])); - LUT1 #( - .INIT(2'h2)) - i_55 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[20])); - LUT1 #( - .INIT(2'h2)) - i_56 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[19])); - LUT1 #( - .INIT(2'h2)) - i_57 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[18])); - LUT1 #( - .INIT(2'h2)) - i_58 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[17])); - LUT1 #( - .INIT(2'h2)) - i_59 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[16])); - LUT1 #( - .INIT(2'h2)) - i_6 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[25])); - LUT1 #( - .INIT(2'h2)) - i_60 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[15])); - LUT1 #( - .INIT(2'h2)) - i_61 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[14])); - LUT1 #( - .INIT(2'h2)) - i_62 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[13])); - LUT1 #( - .INIT(2'h2)) - i_63 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[12])); - LUT1 #( - .INIT(2'h2)) - i_64 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[11])); - LUT1 #( - .INIT(2'h2)) - i_65 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[10])); - LUT1 #( - .INIT(2'h2)) - i_66 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[9])); - LUT1 #( - .INIT(2'h2)) - i_67 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[8])); - LUT1 #( - .INIT(2'h2)) - i_68 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[7])); - LUT1 #( - .INIT(2'h2)) - i_69 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[6])); - LUT1 #( - .INIT(2'h2)) - i_7 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[24])); - LUT1 #( - .INIT(2'h2)) - i_70 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[5])); - LUT1 #( - .INIT(2'h2)) - i_71 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[4])); - LUT1 #( - .INIT(2'h2)) - i_72 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[3])); - LUT1 #( - .INIT(2'h2)) - i_73 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[2])); - LUT1 #( - .INIT(2'h2)) - i_74 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[1])); - LUT1 #( - .INIT(2'h2)) - i_75 - (.I0(1'b0), - .O(s2mm_axi2ip_wrdata_cdc_tig[0])); - LUT1 #( - .INIT(2'h2)) - i_8 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[23])); - LUT1 #( - .INIT(2'h2)) - i_9 - (.I0(1'b0), - .O(ip2axi_rddata_captured_s2mm_cdc_tig[22])); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_1 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(ip2axi_rddata_int_inferred_i_33_n_0), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I3(ip2axi_rddata_int_inferred_i_34_n_0), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[31])); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_10 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(ip2axi_rddata_int_inferred_i_51_n_0), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I3(ip2axi_rddata_int_inferred_i_52_n_0), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[22])); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_11 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(ip2axi_rddata_int_inferred_i_53_n_0), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I3(ip2axi_rddata_int_inferred_i_54_n_0), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[21])); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_12 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(ip2axi_rddata_int_inferred_i_55_n_0), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I3(ip2axi_rddata_int_inferred_i_56_n_0), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[20])); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_13 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(ip2axi_rddata_int_inferred_i_57_n_0), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I3(ip2axi_rddata_int_inferred_i_58_n_0), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[19])); + .D(sig_m_valid_dup_i_1__2_n_0), + .Q(sig_m_valid_out), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + sig_reset_reg_reg + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(m_axis_fifo_ainit_nosync), + .Q(sig_reset_reg), + .R(1'b0)); + LUT6 #( + .INIT(64'h00000000FFFFFFA2)) + sig_s_ready_dup_i_1__2 + (.I0(sig_s_ready_dup), + .I1(sig_m_valid_dup), + .I2(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ), + .I3(m_axis_mm2s_tready), + .I4(sig_reset_reg), + .I5(m_axis_fifo_ainit_nosync), + .O(sig_s_ready_dup_i_1__2_n_0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + sig_s_ready_dup_reg + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(sig_s_ready_dup_i_1__2_n_0), + .Q(sig_s_ready_dup), + .R(1'b0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + sig_s_ready_out_reg + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(sig_s_ready_dup_i_1__2_n_0), + .Q(sig_s_ready_out), + .R(1'b0)); + LUT3 #( + .INIT(8'hB8)) + \sig_user_reg_out[0]_i_1 + (.I0(fifo_dout[33]), + .I1(sig_s_ready_dup), + .I2(sig_user_skid_reg), + .O(sig_user_skid_mux_out)); + FDRE #( + .INIT(1'b0)) + \sig_user_reg_out_reg[0] + (.C(m_axis_mm2s_aclk), + .CE(sig_data_reg_out_en), + .D(sig_user_skid_mux_out), + .Q(m_axis_mm2s_tuser), + .R(m_axis_fifo_ainit_nosync)); + FDRE #( + .INIT(1'b0)) + \sig_user_skid_reg_reg[0] + (.C(m_axis_mm2s_aclk), + .CE(sig_s_ready_dup), + .D(fifo_dout[33]), + .Q(sig_user_skid_reg), + .R(m_axis_fifo_ainit_nosync)); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_skid_buf" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_skid_buf__parameterized0 + (sig_reset_reg, + drop_fsync_d_pulse_gen_fsize_less_err, + M_VALID, + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_d1_reg , + SR, + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_tuser_to_fsync_out_reg , + p_19_in, + s2mm_fsize_more_or_sof_late_s, + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_tuser_to_fsync_out_reg_0 , + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_sof_late_err_reg , + s_axis_s2mm_tready, + M_Last, + M_Data, + s_axis_fifo_ainit_nosync, + s_axis_s2mm_aclk, + s_axis_s2mm_tuser_d1, + run_stop_reg, + delay_s2mm_fsync_core_till_mmap_done_flag, + out, + s2mm_fsync_out_i, + s2mm_fsize_less_err_flag_10, + s2mm_tuser_to_fsync_out, + d_tready_sof_late, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg , + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_reg , + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 , + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_1 , + s_axis_s2mm_tvalid, + d_tready_before_fsync_clr_flag1, + s_axis_s2mm_tlast, + s_axis_s2mm_tdata, + s_axis_s2mm_tuser); + output sig_reset_reg; + output drop_fsync_d_pulse_gen_fsize_less_err; + output M_VALID; + output \GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_d1_reg ; + output [0:0]SR; + output \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_tuser_to_fsync_out_reg ; + output p_19_in; + output s2mm_fsize_more_or_sof_late_s; + output \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_tuser_to_fsync_out_reg_0 ; + output \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_sof_late_err_reg ; + output s_axis_s2mm_tready; + output M_Last; + output [7:0]M_Data; + input s_axis_fifo_ainit_nosync; + input s_axis_s2mm_aclk; + input s_axis_s2mm_tuser_d1; + input run_stop_reg; + input delay_s2mm_fsync_core_till_mmap_done_flag; + input out; + input s2mm_fsync_out_i; + input s2mm_fsize_less_err_flag_10; + input s2mm_tuser_to_fsync_out; + input d_tready_sof_late; + input \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ; + input \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_reg ; + input \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ; + input \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_1 ; + input s_axis_s2mm_tvalid; + input d_tready_before_fsync_clr_flag1; + input s_axis_s2mm_tlast; + input [7:0]s_axis_s2mm_tdata; + input [0:0]s_axis_s2mm_tuser; + + wire \GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_d1_reg ; + wire \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_reg ; + wire \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_sof_late_err_reg ; + wire \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_tuser_to_fsync_out_reg ; + wire \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_tuser_to_fsync_out_reg_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_1 ; + wire [7:0]M_Data; + wire M_Last; + wire [0:0]SR; + wire d_tready_before_fsync_clr_flag1; + wire d_tready_sof_late; + wire delay_s2mm_fsync_core_till_mmap_done_flag; + wire drop_fsync_d_pulse_gen_fsize_less_err; + wire out; + wire p_19_in; + wire p_97_out; + wire run_stop_reg; + wire s2mm_fsize_less_err_flag_10; + wire s2mm_fsize_more_or_sof_late_s; + wire s2mm_fsync_out_i; + wire s2mm_tuser_to_fsync_out; + wire s_axis_fifo_ainit_nosync; + wire s_axis_s2mm_aclk; + wire [7:0]s_axis_s2mm_tdata; + wire s_axis_s2mm_tlast; + wire s_axis_s2mm_tready_signal; + wire [0:0]s_axis_s2mm_tuser; + wire s_axis_s2mm_tuser_d1; + wire s_axis_s2mm_tvalid; + wire [7:0]sig_data_skid_mux_out; + wire [7:0]sig_data_skid_reg; + wire sig_last_reg_out_i_1__3_n_0; + wire sig_last_skid_mux_out; + wire sig_last_skid_reg; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_m_valid_dup; + wire sig_m_valid_dup_i_1__3_n_0; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_m_valid_out; + wire sig_reset_reg; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_s_ready_dup; + wire sig_s_ready_dup_i_1__3_n_0; + (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_s_ready_out; + wire sig_user_skid_mux_out; + wire sig_user_skid_reg; + + assign M_VALID = sig_m_valid_out; + assign s_axis_s2mm_tready = sig_s_ready_out; + LUT6 #( + .INIT(64'h33F3000022020000)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_1__3 + (.I0(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_1 ), + .I1(s2mm_fsize_less_err_flag_10), + .I2(p_97_out), + .I3(s_axis_s2mm_tuser_d1), + .I4(sig_m_valid_out), + .I5(\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_reg ), + .O(s2mm_fsize_more_or_sof_late_s)); LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_14 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(ip2axi_rddata_int_inferred_i_59_n_0), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I3(ip2axi_rddata_int_inferred_i_60_n_0), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[18])); + .INIT(32'h20000000)) + \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.drop_fsync_d_pulse_gen_fsize_less_err_d1_i_1 + (.I0(p_97_out), + .I1(s_axis_s2mm_tuser_d1), + .I2(sig_m_valid_out), + .I3(run_stop_reg), + .I4(delay_s2mm_fsync_core_till_mmap_done_flag), + .O(drop_fsync_d_pulse_gen_fsize_less_err)); + LUT3 #( + .INIT(8'hDF)) + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_i_2 + (.I0(p_97_out), + .I1(s_axis_s2mm_tuser_d1), + .I2(sig_m_valid_out), + .O(\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_tuser_to_fsync_out_reg )); + LUT6 #( + .INIT(64'hA2AAAAAA00000000)) + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_d1_i_1 + (.I0(out), + .I1(p_97_out), + .I2(s_axis_s2mm_tuser_d1), + .I3(sig_m_valid_out), + .I4(run_stop_reg), + .I5(delay_s2mm_fsync_core_till_mmap_done_flag), + .O(\GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_d1_reg )); + LUT6 #( + .INIT(64'h0000000000000200)) + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_sof_late_err_i_1 + (.I0(sig_m_valid_out), + .I1(p_97_out), + .I2(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ), + .I3(out), + .I4(d_tready_sof_late), + .I5(d_tready_before_fsync_clr_flag1), + .O(\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_sof_late_err_reg )); LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_15 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(ip2axi_rddata_int_inferred_i_61_n_0), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I3(ip2axi_rddata_int_inferred_i_62_n_0), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[17])); + .INIT(32'h0000AB00)) + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_tuser_to_fsync_out_i_1 + (.I0(s2mm_tuser_to_fsync_out), + .I1(\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_tuser_to_fsync_out_reg ), + .I2(d_tready_before_fsync_clr_flag1), + .I3(out), + .I4(s2mm_fsync_out_i), + .O(\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_tuser_to_fsync_out_reg_0 )); + LUT2 #( + .INIT(4'h8)) + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s_axis_s2mm_tuser_d1_i_1 + (.I0(p_97_out), + .I1(sig_m_valid_out), + .O(p_19_in)); + LUT6 #( + .INIT(64'hF4F444F4F4F4F4F4)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_1 + (.I0(s2mm_fsync_out_i), + .I1(s_axis_fifo_ainit_nosync), + .I2(s2mm_fsize_less_err_flag_10), + .I3(p_97_out), + .I4(s_axis_s2mm_tuser_d1), + .I5(sig_m_valid_out), + .O(SR)); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[0]_i_1__2 + (.I0(sig_data_skid_reg[0]), + .I1(s_axis_s2mm_tdata[0]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[0])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[1]_i_1__2 + (.I0(sig_data_skid_reg[1]), + .I1(s_axis_s2mm_tdata[1]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[1])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[2]_i_1__2 + (.I0(sig_data_skid_reg[2]), + .I1(s_axis_s2mm_tdata[2]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[2])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[3]_i_1__2 + (.I0(sig_data_skid_reg[3]), + .I1(s_axis_s2mm_tdata[3]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[3])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[4]_i_1__2 + (.I0(sig_data_skid_reg[4]), + .I1(s_axis_s2mm_tdata[4]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[4])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[5]_i_1__2 + (.I0(sig_data_skid_reg[5]), + .I1(s_axis_s2mm_tdata[5]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[5])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[6]_i_1__2 + (.I0(sig_data_skid_reg[6]), + .I1(s_axis_s2mm_tdata[6]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[6])); + LUT3 #( + .INIT(8'hCA)) + \sig_data_reg_out[7]_i_1__2 + (.I0(sig_data_skid_reg[7]), + .I1(s_axis_s2mm_tdata[7]), + .I2(sig_s_ready_dup), + .O(sig_data_skid_mux_out[7])); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[0] + (.C(s_axis_s2mm_aclk), + .CE(sig_last_reg_out_i_1__3_n_0), + .D(sig_data_skid_mux_out[0]), + .Q(M_Data[0]), + .R(s_axis_fifo_ainit_nosync)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[1] + (.C(s_axis_s2mm_aclk), + .CE(sig_last_reg_out_i_1__3_n_0), + .D(sig_data_skid_mux_out[1]), + .Q(M_Data[1]), + .R(s_axis_fifo_ainit_nosync)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[2] + (.C(s_axis_s2mm_aclk), + .CE(sig_last_reg_out_i_1__3_n_0), + .D(sig_data_skid_mux_out[2]), + .Q(M_Data[2]), + .R(s_axis_fifo_ainit_nosync)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[3] + (.C(s_axis_s2mm_aclk), + .CE(sig_last_reg_out_i_1__3_n_0), + .D(sig_data_skid_mux_out[3]), + .Q(M_Data[3]), + .R(s_axis_fifo_ainit_nosync)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[4] + (.C(s_axis_s2mm_aclk), + .CE(sig_last_reg_out_i_1__3_n_0), + .D(sig_data_skid_mux_out[4]), + .Q(M_Data[4]), + .R(s_axis_fifo_ainit_nosync)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[5] + (.C(s_axis_s2mm_aclk), + .CE(sig_last_reg_out_i_1__3_n_0), + .D(sig_data_skid_mux_out[5]), + .Q(M_Data[5]), + .R(s_axis_fifo_ainit_nosync)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[6] + (.C(s_axis_s2mm_aclk), + .CE(sig_last_reg_out_i_1__3_n_0), + .D(sig_data_skid_mux_out[6]), + .Q(M_Data[6]), + .R(s_axis_fifo_ainit_nosync)); + FDRE #( + .INIT(1'b0)) + \sig_data_reg_out_reg[7] + (.C(s_axis_s2mm_aclk), + .CE(sig_last_reg_out_i_1__3_n_0), + .D(sig_data_skid_mux_out[7]), + .Q(M_Data[7]), + .R(s_axis_fifo_ainit_nosync)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[0] + (.C(s_axis_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(s_axis_s2mm_tdata[0]), + .Q(sig_data_skid_reg[0]), + .R(s_axis_fifo_ainit_nosync)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[1] + (.C(s_axis_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(s_axis_s2mm_tdata[1]), + .Q(sig_data_skid_reg[1]), + .R(s_axis_fifo_ainit_nosync)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[2] + (.C(s_axis_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(s_axis_s2mm_tdata[2]), + .Q(sig_data_skid_reg[2]), + .R(s_axis_fifo_ainit_nosync)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[3] + (.C(s_axis_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(s_axis_s2mm_tdata[3]), + .Q(sig_data_skid_reg[3]), + .R(s_axis_fifo_ainit_nosync)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[4] + (.C(s_axis_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(s_axis_s2mm_tdata[4]), + .Q(sig_data_skid_reg[4]), + .R(s_axis_fifo_ainit_nosync)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[5] + (.C(s_axis_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(s_axis_s2mm_tdata[5]), + .Q(sig_data_skid_reg[5]), + .R(s_axis_fifo_ainit_nosync)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[6] + (.C(s_axis_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(s_axis_s2mm_tdata[6]), + .Q(sig_data_skid_reg[6]), + .R(s_axis_fifo_ainit_nosync)); + FDRE #( + .INIT(1'b0)) + \sig_data_skid_reg_reg[7] + (.C(s_axis_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(s_axis_s2mm_tdata[7]), + .Q(sig_data_skid_reg[7]), + .R(s_axis_fifo_ainit_nosync)); + LUT2 #( + .INIT(4'hB)) + sig_last_reg_out_i_1__3 + (.I0(s_axis_s2mm_tready_signal), + .I1(sig_m_valid_dup), + .O(sig_last_reg_out_i_1__3_n_0)); + LUT3 #( + .INIT(8'hB8)) + sig_last_reg_out_i_2__0 + (.I0(s_axis_s2mm_tlast), + .I1(sig_s_ready_dup), + .I2(sig_last_skid_reg), + .O(sig_last_skid_mux_out)); + LUT6 #( + .INIT(64'hFFFF0400FFFFFFFF)) + sig_last_reg_out_i_3__0 + (.I0(s2mm_tuser_to_fsync_out), + .I1(d_tready_sof_late), + .I2(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ), + .I3(\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_tuser_to_fsync_out_reg ), + .I4(\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_reg ), + .I5(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ), + .O(s_axis_s2mm_tready_signal)); + FDRE #( + .INIT(1'b0)) + sig_last_reg_out_reg + (.C(s_axis_s2mm_aclk), + .CE(sig_last_reg_out_i_1__3_n_0), + .D(sig_last_skid_mux_out), + .Q(M_Last), + .R(s_axis_fifo_ainit_nosync)); + FDRE #( + .INIT(1'b0)) + sig_last_skid_reg_reg + (.C(s_axis_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(s_axis_s2mm_tlast), + .Q(sig_last_skid_reg), + .R(s_axis_fifo_ainit_nosync)); + LUT6 #( + .INIT(64'h000000000000FF2A)) + sig_m_valid_dup_i_1__3 + (.I0(sig_m_valid_dup), + .I1(sig_s_ready_dup), + .I2(s_axis_s2mm_tready_signal), + .I3(s_axis_s2mm_tvalid), + .I4(s_axis_fifo_ainit_nosync), + .I5(sig_reset_reg), + .O(sig_m_valid_dup_i_1__3_n_0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + sig_m_valid_dup_reg + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(sig_m_valid_dup_i_1__3_n_0), + .Q(sig_m_valid_dup), + .R(1'b0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + sig_m_valid_out_reg + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(sig_m_valid_dup_i_1__3_n_0), + .Q(sig_m_valid_out), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + sig_reset_reg_reg + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(s_axis_fifo_ainit_nosync), + .Q(sig_reset_reg), + .R(1'b0)); + LUT6 #( + .INIT(64'h00000000FFFFBFAA)) + sig_s_ready_dup_i_1__3 + (.I0(s_axis_s2mm_tready_signal), + .I1(s_axis_s2mm_tvalid), + .I2(sig_m_valid_dup), + .I3(sig_s_ready_dup), + .I4(sig_reset_reg), + .I5(s_axis_fifo_ainit_nosync), + .O(sig_s_ready_dup_i_1__3_n_0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + sig_s_ready_dup_reg + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(sig_s_ready_dup_i_1__3_n_0), + .Q(sig_s_ready_dup), + .R(1'b0)); + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + sig_s_ready_out_reg + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(sig_s_ready_dup_i_1__3_n_0), + .Q(sig_s_ready_out), + .R(1'b0)); + LUT3 #( + .INIT(8'hB8)) + \sig_user_reg_out[0]_i_1__0 + (.I0(s_axis_s2mm_tuser), + .I1(sig_s_ready_dup), + .I2(sig_user_skid_reg), + .O(sig_user_skid_mux_out)); + FDRE #( + .INIT(1'b0)) + \sig_user_reg_out_reg[0] + (.C(s_axis_s2mm_aclk), + .CE(sig_last_reg_out_i_1__3_n_0), + .D(sig_user_skid_mux_out), + .Q(p_97_out), + .R(s_axis_fifo_ainit_nosync)); + FDRE #( + .INIT(1'b0)) + \sig_user_skid_reg_reg[0] + (.C(s_axis_s2mm_aclk), + .CE(sig_s_ready_dup), + .D(s_axis_s2mm_tuser), + .Q(sig_user_skid_reg), + .R(s_axis_fifo_ainit_nosync)); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_sm" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_sm + (tstvect_fsync_d2, + tstvect_fsync_d1, + frame_sync_reg, + s_axis_cmd_tvalid_reg, + zero_vsize_err, + zero_hsize_err, + \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 , + load_new_addr, + halted_set_i0, + p_39_out, + D, + dma_interr_reg, + SR, + m_axi_mm2s_aclk, + mm2s_all_lines_xfred, + zero_vsize_err0, + zero_hsize_err0, + O, + \stride_vid_reg[7] , + \stride_vid_reg[11] , + \stride_vid_reg[15] , + p_24_out, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][30] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][29] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][28] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][27] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][26] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][25] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][24] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][23] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][22] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][21] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][20] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][19] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][18] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][17] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][16] , + s_axis_cmd_tvalid_reg_0, + Q, + mm2s_prmry_resetn, + mm2s_fifo_pipe_empty, + datamover_idle, + p_71_out, + \dmacr_i_reg[2] , + halt_i_reg, + dma_err, + p_77_out, + mm2s_halt, + \INFERRED_GEN.cnt_i_reg[2] , + p_58_out, + CO, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] , + mm2s_axi2ip_wrce, + interr_i_reg, + dma_interr_reg_0, + \hsize_vid_reg[15] , + err_i_reg, + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg ); + output tstvect_fsync_d2; + output tstvect_fsync_d1; + output frame_sync_reg; + output s_axis_cmd_tvalid_reg; + output zero_vsize_err; + output zero_hsize_err; + output [15:0]\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 ; + output load_new_addr; + output halted_set_i0; + output p_39_out; + output [48:0]D; + output dma_interr_reg; + input [0:0]SR; + input m_axi_mm2s_aclk; + input mm2s_all_lines_xfred; + input zero_vsize_err0; + input zero_hsize_err0; + input [3:0]O; + input [3:0]\stride_vid_reg[7] ; + input [3:0]\stride_vid_reg[11] ; + input [3:0]\stride_vid_reg[15] ; + input p_24_out; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][30] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][29] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][28] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][27] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][26] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][25] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][24] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][23] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][22] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][21] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][20] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][19] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][18] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][17] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][16] ; + input s_axis_cmd_tvalid_reg_0; + input [12:0]Q; + input mm2s_prmry_resetn; + input mm2s_fifo_pipe_empty; + input datamover_idle; + input [0:0]p_71_out; + input \dmacr_i_reg[2] ; + input halt_i_reg; + input dma_err; + input p_77_out; + input mm2s_halt; + input [0:0]\INFERRED_GEN.cnt_i_reg[2] ; + input p_58_out; + input [0:0]CO; + input [0:0]\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] ; + input [0:0]mm2s_axi2ip_wrce; + input interr_i_reg; + input dma_interr_reg_0; + input [15:0]\hsize_vid_reg[15] ; + input [0:0]err_i_reg; + input \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg ; + + wire [0:0]CO; + wire [48:0]D; + wire \FSM_sequential_dmacntrl_cs[0]_i_1_n_0 ; + wire \FSM_sequential_dmacntrl_cs[0]_i_2_n_0 ; + wire \FSM_sequential_dmacntrl_cs[0]_i_3_n_0 ; + wire \FSM_sequential_dmacntrl_cs[1]_i_1_n_0 ; + wire \FSM_sequential_dmacntrl_cs[1]_i_2_n_0 ; + wire \FSM_sequential_dmacntrl_cs[1]_i_3_n_0 ; + wire \FSM_sequential_dmacntrl_cs[2]_i_1_n_0 ; + wire \FSM_sequential_dmacntrl_cs[2]_i_2_n_0 ; + wire \FSM_sequential_dmacntrl_cs[2]_i_3_n_0 ; + wire \FSM_sequential_dmacntrl_cs[2]_i_4__0_n_0 ; + wire \FSM_sequential_dmacntrl_cs[2]_i_5_n_0 ; + wire \FSM_sequential_dmacntrl_cs[2]_i_6_n_0 ; + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_3_n_0 ; + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_4_n_0 ; + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_5_n_0 ; + wire \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_i_1_n_0 ; + wire \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg_n_0 ; + wire [0:0]\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data[23]_i_1_n_0 ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ; + wire [15:0]\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[0] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[10] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[11] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[12] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[13] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[14] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[15] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[1] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[23] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[2] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[32] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[33] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[34] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[35] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[36] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[37] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[38] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[39] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[3] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[40] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[41] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[42] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[43] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[44] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[45] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[46] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[47] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[48] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[49] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[4] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[50] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[51] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[52] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[53] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[54] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[55] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[56] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[57] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[58] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[59] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[5] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[60] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[61] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[62] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[63] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[6] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[7] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[8] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[9] ; + wire \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][16] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][17] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][18] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][19] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][20] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][21] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][22] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][23] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][24] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][25] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][26] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][27] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][28] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][29] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][30] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] ; + wire [0:0]\INFERRED_GEN.cnt_i_reg[2] ; + wire [3:0]O; + wire [12:0]Q; + wire [0:0]SR; + wire all_lines_xfred_d1; + wire \cmnds_queued[0]_i_1_n_0 ; + wire \cmnds_queued[4]_i_2_n_0 ; + wire \cmnds_queued[4]_i_3_n_0 ; + wire \cmnds_queued[4]_i_4_n_0 ; + wire \cmnds_queued[4]_i_5_n_0 ; + wire \cmnds_queued[4]_i_6_n_0 ; + wire \cmnds_queued[7]_i_2_n_0 ; + wire \cmnds_queued[7]_i_4_n_0 ; + wire \cmnds_queued[7]_i_5_n_0 ; + wire \cmnds_queued[7]_i_6_n_0 ; + wire \cmnds_queued_reg[4]_i_1_n_0 ; + wire \cmnds_queued_reg[4]_i_1_n_1 ; + wire \cmnds_queued_reg[4]_i_1_n_2 ; + wire \cmnds_queued_reg[4]_i_1_n_3 ; + wire \cmnds_queued_reg[4]_i_1_n_4 ; + wire \cmnds_queued_reg[4]_i_1_n_5 ; + wire \cmnds_queued_reg[4]_i_1_n_6 ; + wire \cmnds_queued_reg[4]_i_1_n_7 ; + wire \cmnds_queued_reg[7]_i_3_n_2 ; + wire \cmnds_queued_reg[7]_i_3_n_3 ; + wire \cmnds_queued_reg[7]_i_3_n_5 ; + wire \cmnds_queued_reg[7]_i_3_n_6 ; + wire \cmnds_queued_reg[7]_i_3_n_7 ; + wire [7:0]cmnds_queued_reg__0; + wire datamover_idle; + wire \dm_address[0]_i_1_n_0 ; + wire \dm_address[16]_i_2_n_0 ; + wire \dm_address[16]_i_3_n_0 ; + wire \dm_address[16]_i_4_n_0 ; + wire \dm_address[16]_i_5_n_0 ; + wire \dm_address[20]_i_2_n_0 ; + wire \dm_address[20]_i_3_n_0 ; + wire \dm_address[20]_i_4_n_0 ; + wire \dm_address[20]_i_5_n_0 ; + wire \dm_address[24]_i_2_n_0 ; + wire \dm_address[24]_i_3_n_0 ; + wire \dm_address[24]_i_4_n_0 ; + wire \dm_address[24]_i_5_n_0 ; + wire \dm_address[28]_i_2_n_0 ; + wire \dm_address[28]_i_3_n_0 ; + wire \dm_address[28]_i_4_n_0 ; + wire \dm_address[28]_i_5_n_0 ; + wire [31:16]dm_address_reg; + wire \dm_address_reg[16]_i_1_n_0 ; + wire \dm_address_reg[16]_i_1_n_1 ; + wire \dm_address_reg[16]_i_1_n_2 ; + wire \dm_address_reg[16]_i_1_n_3 ; + wire \dm_address_reg[16]_i_1_n_4 ; + wire \dm_address_reg[16]_i_1_n_5 ; + wire \dm_address_reg[16]_i_1_n_6 ; + wire \dm_address_reg[16]_i_1_n_7 ; + wire \dm_address_reg[20]_i_1_n_0 ; + wire \dm_address_reg[20]_i_1_n_1 ; + wire \dm_address_reg[20]_i_1_n_2 ; + wire \dm_address_reg[20]_i_1_n_3 ; + wire \dm_address_reg[20]_i_1_n_4 ; + wire \dm_address_reg[20]_i_1_n_5 ; + wire \dm_address_reg[20]_i_1_n_6 ; + wire \dm_address_reg[20]_i_1_n_7 ; + wire \dm_address_reg[24]_i_1_n_0 ; + wire \dm_address_reg[24]_i_1_n_1 ; + wire \dm_address_reg[24]_i_1_n_2 ; + wire \dm_address_reg[24]_i_1_n_3 ; + wire \dm_address_reg[24]_i_1_n_4 ; + wire \dm_address_reg[24]_i_1_n_5 ; + wire \dm_address_reg[24]_i_1_n_6 ; + wire \dm_address_reg[24]_i_1_n_7 ; + wire \dm_address_reg[28]_i_1_n_1 ; + wire \dm_address_reg[28]_i_1_n_2 ; + wire \dm_address_reg[28]_i_1_n_3 ; + wire \dm_address_reg[28]_i_1_n_4 ; + wire \dm_address_reg[28]_i_1_n_5 ; + wire \dm_address_reg[28]_i_1_n_6 ; + wire \dm_address_reg[28]_i_1_n_7 ; + wire dma_err; + wire dma_interr_reg; + wire dma_interr_reg_0; + (* RTL_KEEP = "yes" *) wire [2:0]dmacntrl_cs; + wire \dmacr_i_reg[2] ; + wire [0:0]err_i_reg; + wire frame_sync_d3; + wire frame_sync_reg; + wire halt_i_reg; + wire halted_set_i0; + wire [15:0]\hsize_vid_reg[15] ; + wire interr_i_reg; + wire load_new_addr; + wire m_axi_mm2s_aclk; + wire mm2s_all_lines_xfred; + wire [0:0]mm2s_axi2ip_wrce; + wire mm2s_fifo_pipe_empty; + wire mm2s_halt; + wire mm2s_prmry_resetn; + wire p_1_in; + wire p_24_out; + wire p_39_out; + wire p_58_out; + wire [0:0]p_71_out; + wire p_77_out; + wire s_axis_cmd_tvalid_reg; + wire s_axis_cmd_tvalid_reg_0; + wire [3:0]\stride_vid_reg[11] ; + wire [3:0]\stride_vid_reg[15] ; + wire [3:0]\stride_vid_reg[7] ; + wire tstvect_fsync_d1; + wire tstvect_fsync_d2; + wire \vert_count[0]_i_10_n_0 ; + wire \vert_count[0]_i_11_n_0 ; + wire \vert_count[0]_i_1_n_0 ; + wire \vert_count[0]_i_4_n_0 ; + wire \vert_count[0]_i_5_n_0 ; + wire \vert_count[0]_i_6_n_0 ; + wire \vert_count[0]_i_7_n_0 ; + wire \vert_count[0]_i_8_n_0 ; + wire \vert_count[0]_i_9_n_0 ; + wire \vert_count[12]_i_2_n_0 ; + wire \vert_count[4]_i_2_n_0 ; + wire \vert_count[4]_i_3_n_0 ; + wire \vert_count[4]_i_4_n_0 ; + wire \vert_count[4]_i_5_n_0 ; + wire \vert_count[4]_i_6_n_0 ; + wire \vert_count[4]_i_7_n_0 ; + wire \vert_count[4]_i_8_n_0 ; + wire \vert_count[4]_i_9_n_0 ; + wire \vert_count[8]_i_2_n_0 ; + wire \vert_count[8]_i_3_n_0 ; + wire \vert_count[8]_i_4_n_0 ; + wire \vert_count[8]_i_5_n_0 ; + wire \vert_count[8]_i_6_n_0 ; + wire \vert_count[8]_i_7_n_0 ; + wire \vert_count[8]_i_8_n_0 ; + wire \vert_count[8]_i_9_n_0 ; + wire [12:0]vert_count_reg; + wire \vert_count_reg[0]_i_2_n_0 ; + wire \vert_count_reg[0]_i_2_n_1 ; + wire \vert_count_reg[0]_i_2_n_2 ; + wire \vert_count_reg[0]_i_2_n_3 ; + wire \vert_count_reg[0]_i_2_n_4 ; + wire \vert_count_reg[0]_i_2_n_5 ; + wire \vert_count_reg[0]_i_2_n_6 ; + wire \vert_count_reg[0]_i_2_n_7 ; + wire \vert_count_reg[12]_i_1_n_7 ; + wire \vert_count_reg[4]_i_1_n_0 ; + wire \vert_count_reg[4]_i_1_n_1 ; + wire \vert_count_reg[4]_i_1_n_2 ; + wire \vert_count_reg[4]_i_1_n_3 ; + wire \vert_count_reg[4]_i_1_n_4 ; + wire \vert_count_reg[4]_i_1_n_5 ; + wire \vert_count_reg[4]_i_1_n_6 ; + wire \vert_count_reg[4]_i_1_n_7 ; + wire \vert_count_reg[8]_i_1_n_0 ; + wire \vert_count_reg[8]_i_1_n_1 ; + wire \vert_count_reg[8]_i_1_n_2 ; + wire \vert_count_reg[8]_i_1_n_3 ; + wire \vert_count_reg[8]_i_1_n_4 ; + wire \vert_count_reg[8]_i_1_n_5 ; + wire \vert_count_reg[8]_i_1_n_6 ; + wire \vert_count_reg[8]_i_1_n_7 ; + wire write_cmnd_cmb; + wire zero_hsize_err; + wire zero_hsize_err0; + wire zero_vsize_err; + wire zero_vsize_err0; + wire [3:2]\NLW_cmnds_queued_reg[7]_i_3_CO_UNCONNECTED ; + wire [3:3]\NLW_cmnds_queued_reg[7]_i_3_O_UNCONNECTED ; + wire [3:3]\NLW_dm_address_reg[28]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_vert_count_reg[12]_i_1_CO_UNCONNECTED ; + wire [3:1]\NLW_vert_count_reg[12]_i_1_O_UNCONNECTED ; + + LUT3 #( + .INIT(8'hB8)) + \FSM_sequential_dmacntrl_cs[0]_i_1 + (.I0(\FSM_sequential_dmacntrl_cs[0]_i_2_n_0 ), + .I1(\FSM_sequential_dmacntrl_cs[2]_i_3_n_0 ), + .I2(dmacntrl_cs[0]), + .O(\FSM_sequential_dmacntrl_cs[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h88888B8BBB88BBBB)) + \FSM_sequential_dmacntrl_cs[0]_i_2 + (.I0(\FSM_sequential_dmacntrl_cs[0]_i_3_n_0 ), + .I1(dmacntrl_cs[0]), + .I2(\FSM_sequential_dmacntrl_cs[2]_i_4__0_n_0 ), + .I3(\FSM_sequential_dmacntrl_cs[1]_i_3_n_0 ), + .I4(dmacntrl_cs[1]), + .I5(dmacntrl_cs[2]), + .O(\FSM_sequential_dmacntrl_cs[0]_i_2_n_0 )); + LUT4 #( + .INIT(16'h2808)) + \FSM_sequential_dmacntrl_cs[0]_i_3 + (.I0(p_1_in), + .I1(dmacntrl_cs[2]), + .I2(dmacntrl_cs[1]), + .I3(s_axis_cmd_tvalid_reg_0), + .O(\FSM_sequential_dmacntrl_cs[0]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT3 #( + .INIT(8'hB8)) + \FSM_sequential_dmacntrl_cs[1]_i_1 + (.I0(\FSM_sequential_dmacntrl_cs[1]_i_2_n_0 ), + .I1(\FSM_sequential_dmacntrl_cs[2]_i_3_n_0 ), + .I2(dmacntrl_cs[1]), + .O(\FSM_sequential_dmacntrl_cs[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'h4055DD0040008800)) + \FSM_sequential_dmacntrl_cs[1]_i_2 + (.I0(dmacntrl_cs[2]), + .I1(p_1_in), + .I2(s_axis_cmd_tvalid_reg_0), + .I3(dmacntrl_cs[0]), + .I4(dmacntrl_cs[1]), + .I5(\FSM_sequential_dmacntrl_cs[1]_i_3_n_0 ), + .O(\FSM_sequential_dmacntrl_cs[1]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair13" *) LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_16 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(ip2axi_rddata_int_inferred_i_63_n_0), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I3(ip2axi_rddata_int_inferred_i_64_n_0), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[16])); + .INIT(32'h00000010)) + \FSM_sequential_dmacntrl_cs[1]_i_3 + (.I0(frame_sync_reg), + .I1(mm2s_halt), + .I2(p_71_out), + .I3(dma_err), + .I4(p_77_out), + .O(\FSM_sequential_dmacntrl_cs[1]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT3 #( + .INIT(8'hB8)) + \FSM_sequential_dmacntrl_cs[2]_i_1 + (.I0(\FSM_sequential_dmacntrl_cs[2]_i_2_n_0 ), + .I1(\FSM_sequential_dmacntrl_cs[2]_i_3_n_0 ), + .I2(dmacntrl_cs[2]), + .O(\FSM_sequential_dmacntrl_cs[2]_i_1_n_0 )); LUT6 #( - .INIT(64'h0000000040554000)) - ip2axi_rddata_int_inferred_i_17 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I2(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[15] ), - .I3(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I4(ip2axi_rddata_int_inferred_i_66_n_0), - .I5(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[15])); + .INIT(64'h0040004000000F00)) + \FSM_sequential_dmacntrl_cs[2]_i_2 + (.I0(s_axis_cmd_tvalid_reg_0), + .I1(p_1_in), + .I2(dmacntrl_cs[0]), + .I3(dmacntrl_cs[2]), + .I4(\FSM_sequential_dmacntrl_cs[2]_i_4__0_n_0 ), + .I5(dmacntrl_cs[1]), + .O(\FSM_sequential_dmacntrl_cs[2]_i_2_n_0 )); LUT6 #( - .INIT(64'h0000000040554000)) - ip2axi_rddata_int_inferred_i_18 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I2(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[14] ), - .I3(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I4(ip2axi_rddata_int_inferred_i_68_n_0), - .I5(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[14])); + .INIT(64'h5E5E5E5E5F5E5E5E)) + \FSM_sequential_dmacntrl_cs[2]_i_3 + (.I0(dmacntrl_cs[1]), + .I1(dmacntrl_cs[0]), + .I2(dmacntrl_cs[2]), + .I3(frame_sync_reg), + .I4(\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg ), + .I5(\dmacr_i_reg[2] ), + .O(\FSM_sequential_dmacntrl_cs[2]_i_3_n_0 )); LUT6 #( - .INIT(64'h0000000040554000)) - ip2axi_rddata_int_inferred_i_19 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I2(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[13] ), - .I3(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I4(ip2axi_rddata_int_inferred_i_70_n_0), - .I5(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[13])); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_2 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(ip2axi_rddata_int_inferred_i_35_n_0), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I3(ip2axi_rddata_int_inferred_i_36_n_0), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[30])); - LUT6 #( - .INIT(64'h0000000040554000)) - ip2axi_rddata_int_inferred_i_20 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I2(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[12] ), - .I3(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I4(ip2axi_rddata_int_inferred_i_72_n_0), - .I5(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[12])); - LUT5 #( - .INIT(32'h00004000)) - ip2axi_rddata_int_inferred_i_21 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[11] ), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I3(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[11])); - LUT5 #( - .INIT(32'h00004000)) - ip2axi_rddata_int_inferred_i_22 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[10] ), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I3(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[10])); - LUT5 #( - .INIT(32'h00004000)) - ip2axi_rddata_int_inferred_i_23 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[9] ), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I3(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[9])); - LUT5 #( - .INIT(32'h00004000)) - ip2axi_rddata_int_inferred_i_24 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[8] ), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I3(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[8])); - LUT5 #( - .INIT(32'h00004000)) - ip2axi_rddata_int_inferred_i_25 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[7] ), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I3(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[7])); + .INIT(64'h00010000FFFFFFFF)) + \FSM_sequential_dmacntrl_cs[2]_i_4__0 + (.I0(vert_count_reg[4]), + .I1(vert_count_reg[7]), + .I2(vert_count_reg[5]), + .I3(\FSM_sequential_dmacntrl_cs[2]_i_5_n_0 ), + .I4(\FSM_sequential_dmacntrl_cs[2]_i_6_n_0 ), + .I5(p_1_in), + .O(\FSM_sequential_dmacntrl_cs[2]_i_4__0_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \FSM_sequential_dmacntrl_cs[2]_i_5 + (.I0(vert_count_reg[8]), + .I1(vert_count_reg[0]), + .I2(vert_count_reg[9]), + .I3(vert_count_reg[1]), + .O(\FSM_sequential_dmacntrl_cs[2]_i_5_n_0 )); LUT6 #( - .INIT(64'h0000000040554000)) - ip2axi_rddata_int_inferred_i_26 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I2(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[6] ), - .I3(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I4(ip2axi_rddata_int_inferred_i_79_n_0), - .I5(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[6])); + .INIT(64'h0000000000000001)) + \FSM_sequential_dmacntrl_cs[2]_i_6 + (.I0(vert_count_reg[11]), + .I1(vert_count_reg[6]), + .I2(vert_count_reg[3]), + .I3(vert_count_reg[12]), + .I4(vert_count_reg[2]), + .I5(vert_count_reg[10]), + .O(\FSM_sequential_dmacntrl_cs[2]_i_6_n_0 )); + (* KEEP = "yes" *) + FDRE \FSM_sequential_dmacntrl_cs_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\FSM_sequential_dmacntrl_cs[0]_i_1_n_0 ), + .Q(dmacntrl_cs[0]), + .R(SR)); + (* KEEP = "yes" *) + FDRE \FSM_sequential_dmacntrl_cs_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\FSM_sequential_dmacntrl_cs[1]_i_1_n_0 ), + .Q(dmacntrl_cs[1]), + .R(SR)); + (* KEEP = "yes" *) + FDRE \FSM_sequential_dmacntrl_cs_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\FSM_sequential_dmacntrl_cs[2]_i_1_n_0 ), + .Q(dmacntrl_cs[2]), + .R(SR)); + LUT4 #( + .INIT(16'h00F8)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_1__1 + (.I0(mm2s_all_lines_xfred), + .I1(\GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg_n_0 ), + .I2(\dmacr_i_reg[2] ), + .I3(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_3_n_0 ), + .O(p_39_out)); LUT6 #( - .INIT(64'h0000000040554000)) - ip2axi_rddata_int_inferred_i_27 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I2(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[5] ), - .I3(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I4(ip2axi_rddata_int_inferred_i_81_n_0), - .I5(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[5])); + .INIT(64'hFFFFFFFFFFFFFFFE)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_3 + (.I0(cmnds_queued_reg__0[3]), + .I1(cmnds_queued_reg__0[0]), + .I2(cmnds_queued_reg__0[1]), + .I3(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_4_n_0 ), + .I4(cmnds_queued_reg__0[6]), + .I5(cmnds_queued_reg__0[7]), + .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_3_n_0 )); LUT6 #( - .INIT(64'h0000000040554000)) - ip2axi_rddata_int_inferred_i_28 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I2(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[4] ), - .I3(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I4(ip2axi_rddata_int_inferred_i_83_n_0), - .I5(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[4])); - LUT5 #( - .INIT(32'h00004000)) - ip2axi_rddata_int_inferred_i_29 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[3] ), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I3(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[3])); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_3 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(ip2axi_rddata_int_inferred_i_37_n_0), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I3(ip2axi_rddata_int_inferred_i_38_n_0), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[29])); - LUT6 #( - .INIT(64'h0000000040554000)) - ip2axi_rddata_int_inferred_i_30 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I2(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[2] ), - .I3(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I4(ip2axi_rddata_int_inferred_i_86_n_0), - .I5(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[2])); + .INIT(64'hFFFFFFFFFFFFFFFB)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_4 + (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_5_n_0 ), + .I1(halt_i_reg), + .I2(dmacntrl_cs[1]), + .I3(cmnds_queued_reg__0[5]), + .I4(cmnds_queued_reg__0[4]), + .I5(cmnds_queued_reg__0[2]), + .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_4_n_0 )); + LUT2 #( + .INIT(4'hE)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_5 + (.I0(dmacntrl_cs[2]), + .I1(dmacntrl_cs[0]), + .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_5_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.all_lines_xfred_d1_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(mm2s_all_lines_xfred), + .Q(all_lines_xfred_d1), + .R(SR)); LUT6 #( - .INIT(64'h0000000040554000)) - ip2axi_rddata_int_inferred_i_31 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I2(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[1] ), - .I3(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I4(ip2axi_rddata_int_inferred_i_88_n_0), - .I5(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[1])); + .INIT(64'h00AEFFFFFFFFFFFF)) + \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_i_1 + (.I0(\GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg_n_0 ), + .I1(all_lines_xfred_d1), + .I2(mm2s_all_lines_xfred), + .I3(p_24_out), + .I4(mm2s_prmry_resetn), + .I5(p_71_out), + .O(\GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_i_1_n_0 ), + .Q(\GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg_n_0 ), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT3 #( + .INIT(8'hB8)) + \GEN_NORMAL_DM_COMMAND.cmnd_data[23]_i_1 + (.I0(mm2s_prmry_resetn), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .I2(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[23] ), + .O(\GEN_NORMAL_DM_COMMAND.cmnd_data[23]_i_1_n_0 )); + LUT2 #( + .INIT(4'h2)) + \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1 + (.I0(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .I1(mm2s_prmry_resetn), + .O(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); LUT6 #( - .INIT(64'h0000000040554000)) - ip2axi_rddata_int_inferred_i_32 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I2(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[0] ), - .I3(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I4(ip2axi_rddata_int_inferred_i_90_n_0), - .I5(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[0])); - LUT5 #( - .INIT(32'h80000000)) - ip2axi_rddata_int_inferred_i_33 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [15]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .O(ip2axi_rddata_int_inferred_i_33_n_0)); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_34 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7] [7]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(p_68_out[25]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .O(ip2axi_rddata_int_inferred_i_34_n_0)); - LUT5 #( - .INIT(32'h80000000)) - ip2axi_rddata_int_inferred_i_35 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [14]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .O(ip2axi_rddata_int_inferred_i_35_n_0)); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_36 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7] [6]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(p_68_out[24]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .O(ip2axi_rddata_int_inferred_i_36_n_0)); - LUT5 #( - .INIT(32'h80000000)) - ip2axi_rddata_int_inferred_i_37 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [13]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .O(ip2axi_rddata_int_inferred_i_37_n_0)); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_38 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7] [5]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(p_68_out[23]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .O(ip2axi_rddata_int_inferred_i_38_n_0)); - LUT5 #( - .INIT(32'h80000000)) - ip2axi_rddata_int_inferred_i_39 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [12]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .O(ip2axi_rddata_int_inferred_i_39_n_0)); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_4 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(ip2axi_rddata_int_inferred_i_39_n_0), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I3(ip2axi_rddata_int_inferred_i_40_n_0), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[28])); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_40 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7] [4]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(p_68_out[22]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .O(ip2axi_rddata_int_inferred_i_40_n_0)); - LUT5 #( - .INIT(32'h80000000)) - ip2axi_rddata_int_inferred_i_41 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [11]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .O(ip2axi_rddata_int_inferred_i_41_n_0)); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_42 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7] [3]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(p_68_out[21]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .O(ip2axi_rddata_int_inferred_i_42_n_0)); - LUT5 #( - .INIT(32'h80000000)) - ip2axi_rddata_int_inferred_i_43 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [10]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .O(ip2axi_rddata_int_inferred_i_43_n_0)); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_44 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7] [2]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(p_68_out[20]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .O(ip2axi_rddata_int_inferred_i_44_n_0)); - LUT5 #( - .INIT(32'h80000000)) - ip2axi_rddata_int_inferred_i_45 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [9]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .O(ip2axi_rddata_int_inferred_i_45_n_0)); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_46 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7] [1]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(p_68_out[19]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .O(ip2axi_rddata_int_inferred_i_46_n_0)); - LUT5 #( - .INIT(32'h80000000)) - ip2axi_rddata_int_inferred_i_47 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [8]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .O(ip2axi_rddata_int_inferred_i_47_n_0)); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_48 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7] [0]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(p_68_out[18]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .O(ip2axi_rddata_int_inferred_i_48_n_0)); - LUT5 #( - .INIT(32'h80000000)) - ip2axi_rddata_int_inferred_i_49 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [7]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .O(ip2axi_rddata_int_inferred_i_49_n_0)); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_5 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(ip2axi_rddata_int_inferred_i_41_n_0), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I3(ip2axi_rddata_int_inferred_i_42_n_0), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[27])); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_50 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .I1(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] [7]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(p_68_out[17]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .O(ip2axi_rddata_int_inferred_i_50_n_0)); - LUT5 #( - .INIT(32'h80000000)) - ip2axi_rddata_int_inferred_i_51 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [6]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .O(ip2axi_rddata_int_inferred_i_51_n_0)); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_52 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .I1(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] [6]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(p_68_out[16]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .O(ip2axi_rddata_int_inferred_i_52_n_0)); - LUT5 #( - .INIT(32'h80000000)) - ip2axi_rddata_int_inferred_i_53 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [5]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .O(ip2axi_rddata_int_inferred_i_53_n_0)); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_54 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .I1(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] [5]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(p_68_out[15]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .O(ip2axi_rddata_int_inferred_i_54_n_0)); - LUT5 #( - .INIT(32'h80000000)) - ip2axi_rddata_int_inferred_i_55 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [4]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .O(ip2axi_rddata_int_inferred_i_55_n_0)); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_56 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .I1(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] [4]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(p_68_out[14]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .O(ip2axi_rddata_int_inferred_i_56_n_0)); - LUT5 #( - .INIT(32'h80000000)) - ip2axi_rddata_int_inferred_i_57 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [3]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .O(ip2axi_rddata_int_inferred_i_57_n_0)); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_58 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .I1(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] [3]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(p_68_out[13]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .O(ip2axi_rddata_int_inferred_i_58_n_0)); - LUT5 #( - .INIT(32'h80000000)) - ip2axi_rddata_int_inferred_i_59 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [2]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .O(ip2axi_rddata_int_inferred_i_59_n_0)); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_6 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(ip2axi_rddata_int_inferred_i_43_n_0), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I3(ip2axi_rddata_int_inferred_i_44_n_0), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[26])); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_60 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .I1(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] [2]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(p_68_out[12]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .O(ip2axi_rddata_int_inferred_i_60_n_0)); - LUT5 #( - .INIT(32'h80000000)) - ip2axi_rddata_int_inferred_i_61 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [1]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .O(ip2axi_rddata_int_inferred_i_61_n_0)); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_62 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .I1(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] [1]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(p_68_out[11]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .O(ip2axi_rddata_int_inferred_i_62_n_0)); - LUT5 #( - .INIT(32'h80000000)) - ip2axi_rddata_int_inferred_i_63 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .I1(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [0]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .O(ip2axi_rddata_int_inferred_i_63_n_0)); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_64 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .I1(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] [0]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(p_68_out[10]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .O(ip2axi_rddata_int_inferred_i_64_n_0)); - LUT4 #( - .INIT(16'h0004)) - ip2axi_rddata_int_inferred_i_66 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .I1(p_68_out[9]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .O(ip2axi_rddata_int_inferred_i_66_n_0)); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_68 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .I1(err_irq_reg), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(p_68_out[8]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .O(ip2axi_rddata_int_inferred_i_68_n_0)); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_7 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(ip2axi_rddata_int_inferred_i_45_n_0), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I3(ip2axi_rddata_int_inferred_i_46_n_0), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[25])); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_70 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .I1(dly_irq_reg_0), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(p_68_out[7]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .O(ip2axi_rddata_int_inferred_i_70_n_0)); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_72 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .I1(ioc_irq_reg_0), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(p_68_out[6]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .O(ip2axi_rddata_int_inferred_i_72_n_0)); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_79 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .I1(dma_decerr_reg), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(p_68_out[5]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .O(ip2axi_rddata_int_inferred_i_79_n_0)); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_8 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(ip2axi_rddata_int_inferred_i_47_n_0), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I3(ip2axi_rddata_int_inferred_i_48_n_0), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[24])); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_81 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .I1(dma_slverr_reg), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(p_68_out[4]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .O(ip2axi_rddata_int_inferred_i_81_n_0)); + .INIT(64'h00080000FFFFFFFF)) + \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2 + (.I0(dmacntrl_cs[1]), + .I1(dmacntrl_cs[0]), + .I2(dmacntrl_cs[2]), + .I3(s_axis_cmd_tvalid_reg_0), + .I4(p_1_in), + .I5(mm2s_prmry_resetn), + .O(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\hsize_vid_reg[15] [0]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[0] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[10] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\hsize_vid_reg[15] [10]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[10] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[11] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\hsize_vid_reg[15] [11]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[11] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[12] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\hsize_vid_reg[15] [12]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[12] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[13] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\hsize_vid_reg[15] [13]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[13] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[14] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\hsize_vid_reg[15] [14]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[14] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\hsize_vid_reg[15] [15]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[15] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\hsize_vid_reg[15] [1]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[1] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[23] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data[23]_i_1_n_0 ), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[23] ), + .R(1'b0)); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\hsize_vid_reg[15] [2]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[2] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[32] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [0]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[32] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[33] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [1]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[33] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[34] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [2]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[34] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[35] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [3]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[35] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[36] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [4]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[36] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[37] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [5]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[37] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[38] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [6]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[38] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[39] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [7]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[39] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\hsize_vid_reg[15] [3]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[3] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[40] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [8]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[40] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[41] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [9]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[41] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[42] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [10]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[42] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[43] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [11]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[43] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[44] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [12]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[44] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[45] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [13]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[45] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[46] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [14]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[46] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [15]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[47] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[48] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(dm_address_reg[16]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[48] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[49] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(dm_address_reg[17]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[49] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\hsize_vid_reg[15] [4]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[4] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[50] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(dm_address_reg[18]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[50] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[51] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(dm_address_reg[19]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[51] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[52] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(dm_address_reg[20]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[52] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[53] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(dm_address_reg[21]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[53] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[54] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(dm_address_reg[22]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[54] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[55] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(dm_address_reg[23]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[55] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[56] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(dm_address_reg[24]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[56] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[57] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(dm_address_reg[25]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[57] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[58] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(dm_address_reg[26]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[58] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[59] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(dm_address_reg[27]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[59] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\hsize_vid_reg[15] [5]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[5] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[60] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(dm_address_reg[28]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[60] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[61] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(dm_address_reg[29]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[61] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[62] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(dm_address_reg[30]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[62] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[63] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(dm_address_reg[31]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[63] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[6] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\hsize_vid_reg[15] [6]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[6] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\hsize_vid_reg[15] [7]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[7] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[8] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\hsize_vid_reg[15] [8]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[8] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[9] + (.C(m_axi_mm2s_aclk), + .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), + .D(\hsize_vid_reg[15] [9]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[9] ), + .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_83 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .I1(dma_interr_reg), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(p_68_out[3]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .O(ip2axi_rddata_int_inferred_i_83_n_0)); + .INIT(32'h02000000)) + \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_i_1 + (.I0(p_1_in), + .I1(s_axis_cmd_tvalid_reg_0), + .I2(dmacntrl_cs[2]), + .I3(dmacntrl_cs[0]), + .I4(dmacntrl_cs[1]), + .O(write_cmnd_cmb)); + (* SOFT_HLUTNM = "soft_lutpair13" *) LUT4 #( - .INIT(16'h0004)) - ip2axi_rddata_int_inferred_i_86 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .I1(p_68_out[2]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .O(ip2axi_rddata_int_inferred_i_86_n_0)); + .INIT(16'h0001)) + \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_i_2 + (.I0(frame_sync_reg), + .I1(dma_err), + .I2(p_77_out), + .I3(mm2s_halt), + .O(p_1_in)); + FDRE #( + .INIT(1'b0)) + \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(write_cmnd_cmb), + .Q(s_axis_cmd_tvalid_reg), + .R(SR)); + LUT6 #( + .INIT(64'hFFFFFFF7FFFFFFF0)) + \I_DMA_REGISTER/dma_interr_i_1 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] ), + .I1(mm2s_axi2ip_wrce), + .I2(interr_i_reg), + .I3(zero_vsize_err), + .I4(zero_hsize_err), + .I5(dma_interr_reg_0), + .O(dma_interr_reg)); + LUT1 #( + .INIT(2'h1)) + \cmnds_queued[0]_i_1 + (.I0(cmnds_queued_reg__0[0]), + .O(\cmnds_queued[0]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \cmnds_queued[4]_i_2 + (.I0(cmnds_queued_reg__0[1]), + .O(\cmnds_queued[4]_i_2_n_0 )); + LUT2 #( + .INIT(4'h9)) + \cmnds_queued[4]_i_3 + (.I0(cmnds_queued_reg__0[3]), + .I1(cmnds_queued_reg__0[4]), + .O(\cmnds_queued[4]_i_3_n_0 )); + LUT2 #( + .INIT(4'h9)) + \cmnds_queued[4]_i_4 + (.I0(cmnds_queued_reg__0[2]), + .I1(cmnds_queued_reg__0[3]), + .O(\cmnds_queued[4]_i_4_n_0 )); + LUT2 #( + .INIT(4'h9)) + \cmnds_queued[4]_i_5 + (.I0(cmnds_queued_reg__0[1]), + .I1(cmnds_queued_reg__0[2]), + .O(\cmnds_queued[4]_i_5_n_0 )); LUT4 #( - .INIT(16'h0004)) - ip2axi_rddata_int_inferred_i_88 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .I1(p_68_out[1]), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .O(ip2axi_rddata_int_inferred_i_88_n_0)); - LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_9 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[5]), - .I1(ip2axi_rddata_int_inferred_i_49_n_0), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[4]), - .I3(ip2axi_rddata_int_inferred_i_50_n_0), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[7]), - .O(in0[23])); + .INIT(16'hA655)) + \cmnds_queued[4]_i_6 + (.I0(cmnds_queued_reg__0[1]), + .I1(p_58_out), + .I2(\INFERRED_GEN.cnt_i_reg[2] ), + .I3(s_axis_cmd_tvalid_reg), + .O(\cmnds_queued[4]_i_6_n_0 )); + LUT3 #( + .INIT(8'h9A)) + \cmnds_queued[7]_i_2 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\INFERRED_GEN.cnt_i_reg[2] ), + .I2(p_58_out), + .O(\cmnds_queued[7]_i_2_n_0 )); + LUT2 #( + .INIT(4'h9)) + \cmnds_queued[7]_i_4 + (.I0(cmnds_queued_reg__0[6]), + .I1(cmnds_queued_reg__0[7]), + .O(\cmnds_queued[7]_i_4_n_0 )); + LUT2 #( + .INIT(4'h9)) + \cmnds_queued[7]_i_5 + (.I0(cmnds_queued_reg__0[5]), + .I1(cmnds_queued_reg__0[6]), + .O(\cmnds_queued[7]_i_5_n_0 )); + LUT2 #( + .INIT(4'h9)) + \cmnds_queued[7]_i_6 + (.I0(cmnds_queued_reg__0[4]), + .I1(cmnds_queued_reg__0[5]), + .O(\cmnds_queued[7]_i_6_n_0 )); + FDRE #( + .INIT(1'b0)) + \cmnds_queued_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(\cmnds_queued[7]_i_2_n_0 ), + .D(\cmnds_queued[0]_i_1_n_0 ), + .Q(cmnds_queued_reg__0[0]), + .R(err_i_reg)); + FDRE #( + .INIT(1'b0)) + \cmnds_queued_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(\cmnds_queued[7]_i_2_n_0 ), + .D(\cmnds_queued_reg[4]_i_1_n_7 ), + .Q(cmnds_queued_reg__0[1]), + .R(err_i_reg)); + FDRE #( + .INIT(1'b0)) + \cmnds_queued_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(\cmnds_queued[7]_i_2_n_0 ), + .D(\cmnds_queued_reg[4]_i_1_n_6 ), + .Q(cmnds_queued_reg__0[2]), + .R(err_i_reg)); + FDRE #( + .INIT(1'b0)) + \cmnds_queued_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(\cmnds_queued[7]_i_2_n_0 ), + .D(\cmnds_queued_reg[4]_i_1_n_5 ), + .Q(cmnds_queued_reg__0[3]), + .R(err_i_reg)); + FDRE #( + .INIT(1'b0)) + \cmnds_queued_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(\cmnds_queued[7]_i_2_n_0 ), + .D(\cmnds_queued_reg[4]_i_1_n_4 ), + .Q(cmnds_queued_reg__0[4]), + .R(err_i_reg)); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \cmnds_queued_reg[4]_i_1 + (.CI(1'b0), + .CO({\cmnds_queued_reg[4]_i_1_n_0 ,\cmnds_queued_reg[4]_i_1_n_1 ,\cmnds_queued_reg[4]_i_1_n_2 ,\cmnds_queued_reg[4]_i_1_n_3 }), + .CYINIT(cmnds_queued_reg__0[0]), + .DI({cmnds_queued_reg__0[3:1],\cmnds_queued[4]_i_2_n_0 }), + .O({\cmnds_queued_reg[4]_i_1_n_4 ,\cmnds_queued_reg[4]_i_1_n_5 ,\cmnds_queued_reg[4]_i_1_n_6 ,\cmnds_queued_reg[4]_i_1_n_7 }), + .S({\cmnds_queued[4]_i_3_n_0 ,\cmnds_queued[4]_i_4_n_0 ,\cmnds_queued[4]_i_5_n_0 ,\cmnds_queued[4]_i_6_n_0 })); + FDRE #( + .INIT(1'b0)) + \cmnds_queued_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(\cmnds_queued[7]_i_2_n_0 ), + .D(\cmnds_queued_reg[7]_i_3_n_7 ), + .Q(cmnds_queued_reg__0[5]), + .R(err_i_reg)); + FDRE #( + .INIT(1'b0)) + \cmnds_queued_reg[6] + (.C(m_axi_mm2s_aclk), + .CE(\cmnds_queued[7]_i_2_n_0 ), + .D(\cmnds_queued_reg[7]_i_3_n_6 ), + .Q(cmnds_queued_reg__0[6]), + .R(err_i_reg)); + FDRE #( + .INIT(1'b0)) + \cmnds_queued_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(\cmnds_queued[7]_i_2_n_0 ), + .D(\cmnds_queued_reg[7]_i_3_n_5 ), + .Q(cmnds_queued_reg__0[7]), + .R(err_i_reg)); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \cmnds_queued_reg[7]_i_3 + (.CI(\cmnds_queued_reg[4]_i_1_n_0 ), + .CO({\NLW_cmnds_queued_reg[7]_i_3_CO_UNCONNECTED [3:2],\cmnds_queued_reg[7]_i_3_n_2 ,\cmnds_queued_reg[7]_i_3_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,cmnds_queued_reg__0[5:4]}), + .O({\NLW_cmnds_queued_reg[7]_i_3_O_UNCONNECTED [3],\cmnds_queued_reg[7]_i_3_n_5 ,\cmnds_queued_reg[7]_i_3_n_6 ,\cmnds_queued_reg[7]_i_3_n_7 }), + .S({1'b0,\cmnds_queued[7]_i_4_n_0 ,\cmnds_queued[7]_i_5_n_0 ,\cmnds_queued[7]_i_6_n_0 })); LUT5 #( - .INIT(32'h00004540)) - ip2axi_rddata_int_inferred_i_90 - (.I0(axi2ip_rdaddr_captured_mm2s_cdc_tig[3]), - .I1(p_67_out), - .I2(axi2ip_rdaddr_captured_mm2s_cdc_tig[2]), - .I3(p_68_out[0]), - .I4(axi2ip_rdaddr_captured_mm2s_cdc_tig[6]), - .O(ip2axi_rddata_int_inferred_i_90_n_0)); - LUT4 #( - .INIT(16'h00E0)) - lite_wr_addr_phase_finished_data_phase_started_i_1 - (.I0(lite_wr_addr_phase_finished_data_phase_started), - .I1(s_axi_lite_awready), - .I2(s_axi_lite_resetn), - .I3(s_axi_lite_wready), - .O(lite_wr_addr_phase_finished_data_phase_started_i_1_n_0)); + .INIT(32'hAAEAAAAA)) + \dm_address[0]_i_1 + (.I0(load_new_addr), + .I1(p_1_in), + .I2(dmacntrl_cs[0]), + .I3(dmacntrl_cs[1]), + .I4(dmacntrl_cs[2]), + .O(\dm_address[0]_i_1_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[16]_i_2 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][19] ), + .I1(load_new_addr), + .I2(dm_address_reg[19]), + .O(\dm_address[16]_i_2_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[16]_i_3 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][18] ), + .I1(load_new_addr), + .I2(dm_address_reg[18]), + .O(\dm_address[16]_i_3_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[16]_i_4 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][17] ), + .I1(load_new_addr), + .I2(dm_address_reg[17]), + .O(\dm_address[16]_i_4_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[16]_i_5 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][16] ), + .I1(load_new_addr), + .I2(dm_address_reg[16]), + .O(\dm_address[16]_i_5_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[20]_i_2 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][23] ), + .I1(load_new_addr), + .I2(dm_address_reg[23]), + .O(\dm_address[20]_i_2_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[20]_i_3 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][22] ), + .I1(load_new_addr), + .I2(dm_address_reg[22]), + .O(\dm_address[20]_i_3_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[20]_i_4 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][21] ), + .I1(load_new_addr), + .I2(dm_address_reg[21]), + .O(\dm_address[20]_i_4_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[20]_i_5 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][20] ), + .I1(load_new_addr), + .I2(dm_address_reg[20]), + .O(\dm_address[20]_i_5_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[24]_i_2 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][27] ), + .I1(load_new_addr), + .I2(dm_address_reg[27]), + .O(\dm_address[24]_i_2_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[24]_i_3 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][26] ), + .I1(load_new_addr), + .I2(dm_address_reg[26]), + .O(\dm_address[24]_i_3_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[24]_i_4 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][25] ), + .I1(load_new_addr), + .I2(dm_address_reg[25]), + .O(\dm_address[24]_i_4_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[24]_i_5 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][24] ), + .I1(load_new_addr), + .I2(dm_address_reg[24]), + .O(\dm_address[24]_i_5_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[28]_i_2 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] ), + .I1(load_new_addr), + .I2(dm_address_reg[31]), + .O(\dm_address[28]_i_2_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[28]_i_3 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][30] ), + .I1(load_new_addr), + .I2(dm_address_reg[30]), + .O(\dm_address[28]_i_3_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[28]_i_4 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][29] ), + .I1(load_new_addr), + .I2(dm_address_reg[29]), + .O(\dm_address[28]_i_4_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[28]_i_5 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][28] ), + .I1(load_new_addr), + .I2(dm_address_reg[28]), + .O(\dm_address[28]_i_5_n_0 )); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(O[0]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [0]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[10] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(\stride_vid_reg[11] [2]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [10]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[11] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(\stride_vid_reg[11] [3]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [11]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[12] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(\stride_vid_reg[15] [0]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [12]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[13] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(\stride_vid_reg[15] [1]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [13]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[14] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(\stride_vid_reg[15] [2]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [14]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[15] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(\stride_vid_reg[15] [3]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [15]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[16] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(\dm_address_reg[16]_i_1_n_7 ), + .Q(dm_address_reg[16]), + .R(SR)); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \dm_address_reg[16]_i_1 + (.CI(CO), + .CO({\dm_address_reg[16]_i_1_n_0 ,\dm_address_reg[16]_i_1_n_1 ,\dm_address_reg[16]_i_1_n_2 ,\dm_address_reg[16]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\dm_address_reg[16]_i_1_n_4 ,\dm_address_reg[16]_i_1_n_5 ,\dm_address_reg[16]_i_1_n_6 ,\dm_address_reg[16]_i_1_n_7 }), + .S({\dm_address[16]_i_2_n_0 ,\dm_address[16]_i_3_n_0 ,\dm_address[16]_i_4_n_0 ,\dm_address[16]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[17] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(\dm_address_reg[16]_i_1_n_6 ), + .Q(dm_address_reg[17]), + .R(SR)); FDRE #( .INIT(1'b0)) - lite_wr_addr_phase_finished_data_phase_started_reg - (.C(s_axi_lite_aclk), + \dm_address_reg[18] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(\dm_address_reg[16]_i_1_n_5 ), + .Q(dm_address_reg[18]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[19] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(\dm_address_reg[16]_i_1_n_4 ), + .Q(dm_address_reg[19]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(O[1]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [1]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[20] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(\dm_address_reg[20]_i_1_n_7 ), + .Q(dm_address_reg[20]), + .R(SR)); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \dm_address_reg[20]_i_1 + (.CI(\dm_address_reg[16]_i_1_n_0 ), + .CO({\dm_address_reg[20]_i_1_n_0 ,\dm_address_reg[20]_i_1_n_1 ,\dm_address_reg[20]_i_1_n_2 ,\dm_address_reg[20]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\dm_address_reg[20]_i_1_n_4 ,\dm_address_reg[20]_i_1_n_5 ,\dm_address_reg[20]_i_1_n_6 ,\dm_address_reg[20]_i_1_n_7 }), + .S({\dm_address[20]_i_2_n_0 ,\dm_address[20]_i_3_n_0 ,\dm_address[20]_i_4_n_0 ,\dm_address[20]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[21] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(\dm_address_reg[20]_i_1_n_6 ), + .Q(dm_address_reg[21]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[22] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(\dm_address_reg[20]_i_1_n_5 ), + .Q(dm_address_reg[22]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[23] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(\dm_address_reg[20]_i_1_n_4 ), + .Q(dm_address_reg[23]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[24] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(\dm_address_reg[24]_i_1_n_7 ), + .Q(dm_address_reg[24]), + .R(SR)); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \dm_address_reg[24]_i_1 + (.CI(\dm_address_reg[20]_i_1_n_0 ), + .CO({\dm_address_reg[24]_i_1_n_0 ,\dm_address_reg[24]_i_1_n_1 ,\dm_address_reg[24]_i_1_n_2 ,\dm_address_reg[24]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\dm_address_reg[24]_i_1_n_4 ,\dm_address_reg[24]_i_1_n_5 ,\dm_address_reg[24]_i_1_n_6 ,\dm_address_reg[24]_i_1_n_7 }), + .S({\dm_address[24]_i_2_n_0 ,\dm_address[24]_i_3_n_0 ,\dm_address[24]_i_4_n_0 ,\dm_address[24]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[25] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(\dm_address_reg[24]_i_1_n_6 ), + .Q(dm_address_reg[25]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[26] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(\dm_address_reg[24]_i_1_n_5 ), + .Q(dm_address_reg[26]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[27] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(\dm_address_reg[24]_i_1_n_4 ), + .Q(dm_address_reg[27]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[28] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(\dm_address_reg[28]_i_1_n_7 ), + .Q(dm_address_reg[28]), + .R(SR)); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \dm_address_reg[28]_i_1 + (.CI(\dm_address_reg[24]_i_1_n_0 ), + .CO({\NLW_dm_address_reg[28]_i_1_CO_UNCONNECTED [3],\dm_address_reg[28]_i_1_n_1 ,\dm_address_reg[28]_i_1_n_2 ,\dm_address_reg[28]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\dm_address_reg[28]_i_1_n_4 ,\dm_address_reg[28]_i_1_n_5 ,\dm_address_reg[28]_i_1_n_6 ,\dm_address_reg[28]_i_1_n_7 }), + .S({\dm_address[28]_i_2_n_0 ,\dm_address[28]_i_3_n_0 ,\dm_address[28]_i_4_n_0 ,\dm_address[28]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[29] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(\dm_address_reg[28]_i_1_n_6 ), + .Q(dm_address_reg[29]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(O[2]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [2]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[30] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(\dm_address_reg[28]_i_1_n_5 ), + .Q(dm_address_reg[30]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[31] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(\dm_address_reg[28]_i_1_n_4 ), + .Q(dm_address_reg[31]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(O[3]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [3]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(\stride_vid_reg[7] [0]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [4]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(\stride_vid_reg[7] [1]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [5]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[6] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(\stride_vid_reg[7] [2]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [6]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(\stride_vid_reg[7] [3]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [7]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[8] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(\stride_vid_reg[11] [0]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [8]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \dm_address_reg[9] + (.C(m_axi_mm2s_aclk), + .CE(\dm_address[0]_i_1_n_0 ), + .D(\stride_vid_reg[11] [1]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [9]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + frame_sync_d1_reg + (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(lite_wr_addr_phase_finished_data_phase_started_i_1_n_0), - .Q(lite_wr_addr_phase_finished_data_phase_started), - .R(1'b0)); + .D(p_24_out), + .Q(tstvect_fsync_d1), + .R(SR)); + FDRE #( + .INIT(1'b0)) + frame_sync_d2_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(tstvect_fsync_d1), + .Q(tstvect_fsync_d2), + .R(SR)); + FDRE #( + .INIT(1'b0)) + frame_sync_d3_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(tstvect_fsync_d2), + .Q(frame_sync_d3), + .R(SR)); + FDRE #( + .INIT(1'b0)) + frame_sync_reg_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(frame_sync_d3), + .Q(frame_sync_reg), + .R(SR)); + LUT4 #( + .INIT(16'h0080)) + halted_set_i_i_1 + (.I0(p_39_out), + .I1(mm2s_fifo_pipe_empty), + .I2(datamover_idle), + .I3(p_71_out), + .O(halted_set_i0)); + (* SOFT_HLUTNM = "soft_lutpair39" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[0]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[0] ), + .O(D[0])); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[10]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[10] ), + .O(D[10])); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[11]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[11] ), + .O(D[11])); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[12]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[12] ), + .O(D[12])); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[13]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[13] ), + .O(D[13])); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[14]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[14] ), + .O(D[14])); + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[15]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[15] ), + .O(D[15])); + (* SOFT_HLUTNM = "soft_lutpair39" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[1]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[1] ), + .O(D[1])); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[23]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[23] ), + .O(D[16])); + (* SOFT_HLUTNM = "soft_lutpair38" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[2]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[2] ), + .O(D[2])); + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[32]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[32] ), + .O(D[17])); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[33]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[33] ), + .O(D[18])); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[34]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[34] ), + .O(D[19])); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[35]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[35] ), + .O(D[20])); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[36]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[36] ), + .O(D[21])); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[37]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[37] ), + .O(D[22])); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[38]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[38] ), + .O(D[23])); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[39]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[39] ), + .O(D[24])); + (* SOFT_HLUTNM = "soft_lutpair38" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[3]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[3] ), + .O(D[3])); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[40]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[40] ), + .O(D[25])); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[41]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[41] ), + .O(D[26])); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[42]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[42] ), + .O(D[27])); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[43]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[43] ), + .O(D[28])); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[44]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[44] ), + .O(D[29])); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[45]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[45] ), + .O(D[30])); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[46]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[46] ), + .O(D[31])); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[47]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[47] ), + .O(D[32])); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[48]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[48] ), + .O(D[33])); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[49]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[49] ), + .O(D[34])); + (* SOFT_HLUTNM = "soft_lutpair37" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[4]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[4] ), + .O(D[4])); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[50]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[50] ), + .O(D[35])); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[51]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[51] ), + .O(D[36])); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[52]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[52] ), + .O(D[37])); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[53]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[53] ), + .O(D[38])); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[54]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[54] ), + .O(D[39])); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[55]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[55] ), + .O(D[40])); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[56]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[56] ), + .O(D[41])); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[57]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[57] ), + .O(D[42])); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[58]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[58] ), + .O(D[43])); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[59]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[59] ), + .O(D[44])); + (* SOFT_HLUTNM = "soft_lutpair37" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[5]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[5] ), + .O(D[5])); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[60]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[60] ), + .O(D[45])); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[61]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[61] ), + .O(D[46])); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[62]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[62] ), + .O(D[47])); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[63]_i_3 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[63] ), + .O(D[48])); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[6]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[6] ), + .O(D[6])); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[7]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[7] ), + .O(D[7])); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[8]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[8] ), + .O(D[8])); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[9]_i_1 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[9] ), + .O(D[9])); LUT6 #( - .INIT(64'h0000AE00AE00AE00)) - read_has_started_i_i_1 - (.I0(read_has_started_i), - .I1(arvalid), - .I2(sig_arvalid_arrived_d1), - .I3(s_axi_lite_resetn), - .I4(s_axi_lite_rready), - .I5(s_axi_lite_rvalid), - .O(read_has_started_i_i_1_n_0)); - FDRE #( - .INIT(1'b0)) - read_has_started_i_reg - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(read_has_started_i_i_1_n_0), - .Q(read_has_started_i), - .R(1'b0)); - (* SOFT_HLUTNM = "soft_lutpair4" *) + .INIT(64'hFFFFFFFF00080000)) + \vert_count[0]_i_1 + (.I0(dmacntrl_cs[1]), + .I1(dmacntrl_cs[0]), + .I2(dmacntrl_cs[2]), + .I3(s_axis_cmd_tvalid_reg_0), + .I4(p_1_in), + .I5(load_new_addr), + .O(\vert_count[0]_i_1_n_0 )); LUT3 #( - .INIT(8'h08)) - sig_arvalid_arrived_d1_i_1 - (.I0(arvalid), - .I1(s_axi_lite_resetn), - .I2(read_has_started_i), - .O(sig_arvalid_arrived_d1_i_1_n_0)); - FDRE #( - .INIT(1'b0)) - sig_arvalid_arrived_d1_reg - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(sig_arvalid_arrived_d1_i_1_n_0), - .Q(sig_arvalid_arrived_d1), - .R(1'b0)); + .INIT(8'hC5)) + \vert_count[0]_i_10 + (.I0(vert_count_reg[1]), + .I1(Q[1]), + .I2(load_new_addr), + .O(\vert_count[0]_i_10_n_0 )); LUT3 #( - .INIT(8'h02)) - sig_arvalid_detected - (.I0(arvalid), - .I1(read_has_started_i), - .I2(sig_arvalid_arrived_d1), - .O(sig_arvalid_detected__0)); - (* SOFT_HLUTNM = "soft_lutpair4" *) + .INIT(8'hC5)) + \vert_count[0]_i_11 + (.I0(vert_count_reg[0]), + .I1(Q[0]), + .I2(load_new_addr), + .O(\vert_count[0]_i_11_n_0 )); + LUT4 #( + .INIT(16'h1000)) + \vert_count[0]_i_3 + (.I0(dmacntrl_cs[0]), + .I1(dmacntrl_cs[2]), + .I2(dmacntrl_cs[1]), + .I3(\FSM_sequential_dmacntrl_cs[1]_i_3_n_0 ), + .O(load_new_addr)); + LUT1 #( + .INIT(2'h1)) + \vert_count[0]_i_4 + (.I0(load_new_addr), + .O(\vert_count[0]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \vert_count[0]_i_5 + (.I0(load_new_addr), + .O(\vert_count[0]_i_5_n_0 )); + LUT1 #( + .INIT(2'h1)) + \vert_count[0]_i_6 + (.I0(load_new_addr), + .O(\vert_count[0]_i_6_n_0 )); + LUT1 #( + .INIT(2'h1)) + \vert_count[0]_i_7 + (.I0(load_new_addr), + .O(\vert_count[0]_i_7_n_0 )); LUT3 #( - .INIT(8'h08)) - sig_awvalid_arrived_d1_i_1 - (.I0(awvalid), - .I1(s_axi_lite_resetn), - .I2(write_has_started), - .O(sig_awvalid_arrived_d1_i_1_n_0)); - FDRE #( - .INIT(1'b0)) - sig_awvalid_arrived_d1_reg - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(sig_awvalid_arrived_d1_i_1_n_0), - .Q(sig_awvalid_arrived_d1), - .R(1'b0)); + .INIT(8'hC5)) + \vert_count[0]_i_8 + (.I0(vert_count_reg[3]), + .I1(Q[3]), + .I2(load_new_addr), + .O(\vert_count[0]_i_8_n_0 )); LUT3 #( - .INIT(8'h02)) - sig_awvalid_detected - (.I0(awvalid), - .I1(write_has_started), - .I2(sig_awvalid_arrived_d1), - .O(sig_awvalid_detected__0)); - FDRE #( - .INIT(1'b0)) - \wdata_reg[0] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[0]), - .Q(wdata[0]), - .R(SR)); - FDRE #( - .INIT(1'b0)) - \wdata_reg[10] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[10]), - .Q(wdata[10]), - .R(SR)); - FDRE #( - .INIT(1'b0)) - \wdata_reg[11] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[11]), - .Q(wdata[11]), - .R(SR)); - FDRE #( - .INIT(1'b0)) - \wdata_reg[12] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[12]), - .Q(wdata[12]), - .R(SR)); - FDRE #( - .INIT(1'b0)) - \wdata_reg[13] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[13]), - .Q(wdata[13]), - .R(SR)); - FDRE #( - .INIT(1'b0)) - \wdata_reg[14] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[14]), - .Q(wdata[14]), - .R(SR)); - FDRE #( - .INIT(1'b0)) - \wdata_reg[15] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[15]), - .Q(wdata[15]), - .R(SR)); - FDRE #( - .INIT(1'b0)) - \wdata_reg[16] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[16]), - .Q(wdata[16]), - .R(SR)); - FDRE #( - .INIT(1'b0)) - \wdata_reg[17] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[17]), - .Q(wdata[17]), - .R(SR)); - FDRE #( - .INIT(1'b0)) - \wdata_reg[18] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[18]), - .Q(wdata[18]), - .R(SR)); - FDRE #( - .INIT(1'b0)) - \wdata_reg[19] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[19]), - .Q(wdata[19]), - .R(SR)); - FDRE #( - .INIT(1'b0)) - \wdata_reg[1] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[1]), - .Q(wdata[1]), - .R(SR)); - FDRE #( - .INIT(1'b0)) - \wdata_reg[20] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[20]), - .Q(wdata[20]), - .R(SR)); - FDRE #( - .INIT(1'b0)) - \wdata_reg[21] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[21]), - .Q(wdata[21]), - .R(SR)); - FDRE #( - .INIT(1'b0)) - \wdata_reg[22] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[22]), - .Q(wdata[22]), - .R(SR)); - FDRE #( - .INIT(1'b0)) - \wdata_reg[23] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[23]), - .Q(wdata[23]), - .R(SR)); - FDRE #( - .INIT(1'b0)) - \wdata_reg[24] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[24]), - .Q(wdata[24]), - .R(SR)); - FDRE #( - .INIT(1'b0)) - \wdata_reg[25] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[25]), - .Q(wdata[25]), - .R(SR)); + .INIT(8'hC5)) + \vert_count[0]_i_9 + (.I0(vert_count_reg[2]), + .I1(Q[2]), + .I2(load_new_addr), + .O(\vert_count[0]_i_9_n_0 )); + LUT3 #( + .INIT(8'hA3)) + \vert_count[12]_i_2 + (.I0(Q[12]), + .I1(vert_count_reg[12]), + .I2(load_new_addr), + .O(\vert_count[12]_i_2_n_0 )); + LUT1 #( + .INIT(2'h1)) + \vert_count[4]_i_2 + (.I0(load_new_addr), + .O(\vert_count[4]_i_2_n_0 )); + LUT1 #( + .INIT(2'h1)) + \vert_count[4]_i_3 + (.I0(load_new_addr), + .O(\vert_count[4]_i_3_n_0 )); + LUT1 #( + .INIT(2'h1)) + \vert_count[4]_i_4 + (.I0(load_new_addr), + .O(\vert_count[4]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \vert_count[4]_i_5 + (.I0(load_new_addr), + .O(\vert_count[4]_i_5_n_0 )); + LUT3 #( + .INIT(8'hC5)) + \vert_count[4]_i_6 + (.I0(vert_count_reg[7]), + .I1(Q[7]), + .I2(load_new_addr), + .O(\vert_count[4]_i_6_n_0 )); + LUT3 #( + .INIT(8'hC5)) + \vert_count[4]_i_7 + (.I0(vert_count_reg[6]), + .I1(Q[6]), + .I2(load_new_addr), + .O(\vert_count[4]_i_7_n_0 )); + LUT3 #( + .INIT(8'hC5)) + \vert_count[4]_i_8 + (.I0(vert_count_reg[5]), + .I1(Q[5]), + .I2(load_new_addr), + .O(\vert_count[4]_i_8_n_0 )); + LUT3 #( + .INIT(8'hC5)) + \vert_count[4]_i_9 + (.I0(vert_count_reg[4]), + .I1(Q[4]), + .I2(load_new_addr), + .O(\vert_count[4]_i_9_n_0 )); + LUT1 #( + .INIT(2'h1)) + \vert_count[8]_i_2 + (.I0(load_new_addr), + .O(\vert_count[8]_i_2_n_0 )); + LUT1 #( + .INIT(2'h1)) + \vert_count[8]_i_3 + (.I0(load_new_addr), + .O(\vert_count[8]_i_3_n_0 )); + LUT1 #( + .INIT(2'h1)) + \vert_count[8]_i_4 + (.I0(load_new_addr), + .O(\vert_count[8]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \vert_count[8]_i_5 + (.I0(load_new_addr), + .O(\vert_count[8]_i_5_n_0 )); + LUT3 #( + .INIT(8'hC5)) + \vert_count[8]_i_6 + (.I0(vert_count_reg[11]), + .I1(Q[11]), + .I2(load_new_addr), + .O(\vert_count[8]_i_6_n_0 )); + LUT3 #( + .INIT(8'hC5)) + \vert_count[8]_i_7 + (.I0(vert_count_reg[10]), + .I1(Q[10]), + .I2(load_new_addr), + .O(\vert_count[8]_i_7_n_0 )); + LUT3 #( + .INIT(8'hC5)) + \vert_count[8]_i_8 + (.I0(vert_count_reg[9]), + .I1(Q[9]), + .I2(load_new_addr), + .O(\vert_count[8]_i_8_n_0 )); + LUT3 #( + .INIT(8'hC5)) + \vert_count[8]_i_9 + (.I0(vert_count_reg[8]), + .I1(Q[8]), + .I2(load_new_addr), + .O(\vert_count[8]_i_9_n_0 )); FDRE #( .INIT(1'b0)) - \wdata_reg[26] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[26]), - .Q(wdata[26]), + \vert_count_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(\vert_count[0]_i_1_n_0 ), + .D(\vert_count_reg[0]_i_2_n_7 ), + .Q(vert_count_reg[0]), .R(SR)); + CARRY4 \vert_count_reg[0]_i_2 + (.CI(1'b0), + .CO({\vert_count_reg[0]_i_2_n_0 ,\vert_count_reg[0]_i_2_n_1 ,\vert_count_reg[0]_i_2_n_2 ,\vert_count_reg[0]_i_2_n_3 }), + .CYINIT(1'b0), + .DI({\vert_count[0]_i_4_n_0 ,\vert_count[0]_i_5_n_0 ,\vert_count[0]_i_6_n_0 ,\vert_count[0]_i_7_n_0 }), + .O({\vert_count_reg[0]_i_2_n_4 ,\vert_count_reg[0]_i_2_n_5 ,\vert_count_reg[0]_i_2_n_6 ,\vert_count_reg[0]_i_2_n_7 }), + .S({\vert_count[0]_i_8_n_0 ,\vert_count[0]_i_9_n_0 ,\vert_count[0]_i_10_n_0 ,\vert_count[0]_i_11_n_0 })); FDRE #( .INIT(1'b0)) - \wdata_reg[27] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[27]), - .Q(wdata[27]), + \vert_count_reg[10] + (.C(m_axi_mm2s_aclk), + .CE(\vert_count[0]_i_1_n_0 ), + .D(\vert_count_reg[8]_i_1_n_5 ), + .Q(vert_count_reg[10]), .R(SR)); FDRE #( .INIT(1'b0)) - \wdata_reg[28] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[28]), - .Q(wdata[28]), + \vert_count_reg[11] + (.C(m_axi_mm2s_aclk), + .CE(\vert_count[0]_i_1_n_0 ), + .D(\vert_count_reg[8]_i_1_n_4 ), + .Q(vert_count_reg[11]), .R(SR)); FDRE #( .INIT(1'b0)) - \wdata_reg[29] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[29]), - .Q(wdata[29]), + \vert_count_reg[12] + (.C(m_axi_mm2s_aclk), + .CE(\vert_count[0]_i_1_n_0 ), + .D(\vert_count_reg[12]_i_1_n_7 ), + .Q(vert_count_reg[12]), .R(SR)); + CARRY4 \vert_count_reg[12]_i_1 + (.CI(\vert_count_reg[8]_i_1_n_0 ), + .CO(\NLW_vert_count_reg[12]_i_1_CO_UNCONNECTED [3:0]), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_vert_count_reg[12]_i_1_O_UNCONNECTED [3:1],\vert_count_reg[12]_i_1_n_7 }), + .S({1'b0,1'b0,1'b0,\vert_count[12]_i_2_n_0 })); FDRE #( .INIT(1'b0)) - \wdata_reg[2] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[2]), - .Q(wdata[2]), + \vert_count_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(\vert_count[0]_i_1_n_0 ), + .D(\vert_count_reg[0]_i_2_n_6 ), + .Q(vert_count_reg[1]), .R(SR)); FDRE #( .INIT(1'b0)) - \wdata_reg[30] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[30]), - .Q(wdata[30]), + \vert_count_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(\vert_count[0]_i_1_n_0 ), + .D(\vert_count_reg[0]_i_2_n_5 ), + .Q(vert_count_reg[2]), .R(SR)); FDRE #( .INIT(1'b0)) - \wdata_reg[31] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[31]), - .Q(wdata[31]), + \vert_count_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(\vert_count[0]_i_1_n_0 ), + .D(\vert_count_reg[0]_i_2_n_4 ), + .Q(vert_count_reg[3]), .R(SR)); FDRE #( .INIT(1'b0)) - \wdata_reg[3] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[3]), - .Q(wdata[3]), + \vert_count_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(\vert_count[0]_i_1_n_0 ), + .D(\vert_count_reg[4]_i_1_n_7 ), + .Q(vert_count_reg[4]), .R(SR)); + CARRY4 \vert_count_reg[4]_i_1 + (.CI(\vert_count_reg[0]_i_2_n_0 ), + .CO({\vert_count_reg[4]_i_1_n_0 ,\vert_count_reg[4]_i_1_n_1 ,\vert_count_reg[4]_i_1_n_2 ,\vert_count_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({\vert_count[4]_i_2_n_0 ,\vert_count[4]_i_3_n_0 ,\vert_count[4]_i_4_n_0 ,\vert_count[4]_i_5_n_0 }), + .O({\vert_count_reg[4]_i_1_n_4 ,\vert_count_reg[4]_i_1_n_5 ,\vert_count_reg[4]_i_1_n_6 ,\vert_count_reg[4]_i_1_n_7 }), + .S({\vert_count[4]_i_6_n_0 ,\vert_count[4]_i_7_n_0 ,\vert_count[4]_i_8_n_0 ,\vert_count[4]_i_9_n_0 })); FDRE #( .INIT(1'b0)) - \wdata_reg[4] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[4]), - .Q(wdata[4]), + \vert_count_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(\vert_count[0]_i_1_n_0 ), + .D(\vert_count_reg[4]_i_1_n_6 ), + .Q(vert_count_reg[5]), .R(SR)); FDRE #( .INIT(1'b0)) - \wdata_reg[5] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[5]), - .Q(wdata[5]), + \vert_count_reg[6] + (.C(m_axi_mm2s_aclk), + .CE(\vert_count[0]_i_1_n_0 ), + .D(\vert_count_reg[4]_i_1_n_5 ), + .Q(vert_count_reg[6]), .R(SR)); FDRE #( .INIT(1'b0)) - \wdata_reg[6] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[6]), - .Q(wdata[6]), + \vert_count_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(\vert_count[0]_i_1_n_0 ), + .D(\vert_count_reg[4]_i_1_n_4 ), + .Q(vert_count_reg[7]), .R(SR)); FDRE #( .INIT(1'b0)) - \wdata_reg[7] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[7]), - .Q(wdata[7]), + \vert_count_reg[8] + (.C(m_axi_mm2s_aclk), + .CE(\vert_count[0]_i_1_n_0 ), + .D(\vert_count_reg[8]_i_1_n_7 ), + .Q(vert_count_reg[8]), .R(SR)); + CARRY4 \vert_count_reg[8]_i_1 + (.CI(\vert_count_reg[4]_i_1_n_0 ), + .CO({\vert_count_reg[8]_i_1_n_0 ,\vert_count_reg[8]_i_1_n_1 ,\vert_count_reg[8]_i_1_n_2 ,\vert_count_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({\vert_count[8]_i_2_n_0 ,\vert_count[8]_i_3_n_0 ,\vert_count[8]_i_4_n_0 ,\vert_count[8]_i_5_n_0 }), + .O({\vert_count_reg[8]_i_1_n_4 ,\vert_count_reg[8]_i_1_n_5 ,\vert_count_reg[8]_i_1_n_6 ,\vert_count_reg[8]_i_1_n_7 }), + .S({\vert_count[8]_i_6_n_0 ,\vert_count[8]_i_7_n_0 ,\vert_count[8]_i_8_n_0 ,\vert_count[8]_i_9_n_0 })); FDRE #( .INIT(1'b0)) - \wdata_reg[8] - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_axi_lite_wdata[8]), - .Q(wdata[8]), + \vert_count_reg[9] + (.C(m_axi_mm2s_aclk), + .CE(\vert_count[0]_i_1_n_0 ), + .D(\vert_count_reg[8]_i_1_n_6 ), + .Q(vert_count_reg[9]), .R(SR)); FDRE #( .INIT(1'b0)) - \wdata_reg[9] - (.C(s_axi_lite_aclk), + zero_hsize_err_reg + (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(s_axi_lite_wdata[9]), - .Q(wdata[9]), + .D(zero_hsize_err0), + .Q(zero_hsize_err), .R(SR)); - LUT6 #( - .INIT(64'h0000AE00AE00AE00)) - write_has_started_i_1 - (.I0(write_has_started), - .I1(awvalid), - .I2(sig_awvalid_arrived_d1), - .I3(s_axi_lite_resetn), - .I4(s_axi_lite_bready), - .I5(s_axi_lite_bvalid), - .O(write_has_started_i_1_n_0)); - FDRE #( - .INIT(1'b0)) - write_has_started_reg - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(write_has_started_i_1_n_0), - .Q(write_has_started), - .R(1'b0)); FDRE #( .INIT(1'b0)) - wvalid_reg - (.C(s_axi_lite_aclk), + zero_vsize_err_reg + (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(s_axi_lite_wvalid), - .Q(wvalid), + .D(zero_vsize_err0), + .Q(zero_vsize_err), .R(SR)); endmodule -(* ORIG_REF_NAME = "axi_vdma_mm2s_linebuf" *) -module Arty_Z7_20_axi_vdma_0_0_axi_vdma_mm2s_linebuf - (out, - p_1_out, - p_0_out, - sig_reset_reg_reg, - m_axis_mm2s_tlast, - m_axis_mm2s_tuser, - DIN, - fifo_full_i, - s_valid0, - \GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 , - m_axis_mm2s_tdata, +(* ORIG_REF_NAME = "axi_vdma_sm" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_sm__parameterized0 + (\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg , + tstvect_fsync_d2, + tstvect_fsync_d1, + s_axis_cmd_tvalid_reg, + zero_hsize_err, + zero_vsize_err, + drop_fsync_d_pulse_gen_fsize_less_err_d1, + fsize_mismatch_err_s1, + \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 , + halt_i0, + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0 , + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_irqthresh_decr_mask_sig_reg , + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[0] , + load_new_addr, + halted_set_i0, + s2mm_ftchcmdsts_idle, + D, + s2mm_dma_interr_set_minus_frame_errors, + \DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_reg , + \s_axis_cmd_tdata_reg[63] , + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_fsize_less_err_flag_10_reg , + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF.flag_to_repeat_after_fsize_less_err_reg , + \S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg , + prmry_reset2, + s_axis_s2mm_aclk, SR, - m_axi_mm2s_aclk, - scndry_reset2, - m_axis_mm2s_aclk, - mm2s_halt, + m_axi_s2mm_aclk, + s2mm_fsync_out_m_i, + zero_hsize_err0, + zero_vsize_err0, + drop_fsync_d_pulse_gen_fsize_less_err, + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg , + O, + \stride_vid_reg[7] , + \stride_vid_reg[11] , + \stride_vid_reg[15] , + s2mm_cdc2dmac_fsync, + s2mm_stop, + run_stop_d1, + s2mm_dmacr, + s2mm_soft_reset, + soft_reset_d1, + prmry_resetn_i_reg, + s2mm_tstvect_fsync, + ch2_delay_cnt_en, + s2mm_packet_sof, + ch2_irqthresh_decr_mask_sig, + s2mm_halt, + out, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][30] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][29] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][28] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][27] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][26] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][25] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][24] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][23] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][22] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][21] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][20] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][19] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][18] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][17] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][16] , + s_axis_cmd_tvalid_reg_0, Q, + datamover_idle, + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] , + flag_to_repeat_after_fsize_less_err, + \GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[4] , + halt_i_reg, + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg , + dma_err, + \INFERRED_GEN.cnt_i_reg[2] , + m_axis_s2mm_sts_tready, + interr_i_reg, + \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[4] , + valid_frame_sync_d2, + CO, + s2mm_fsize_less_err_flag_10, \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 , - all_lines_xfred, - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 , - fifo_wren__0, - m_axis_mm2s_tready, - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 , - p_15_out, - dm2linebuf_mm2s_tdata, - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ); - output out; - output p_1_out; - output p_0_out; - output sig_reset_reg_reg; - output m_axis_mm2s_tlast; - output [0:0]m_axis_mm2s_tuser; - output [0:0]DIN; - output fifo_full_i; - output s_valid0; - output \GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 ; - output [31:0]m_axis_mm2s_tdata; + \sig_user_reg_out_reg[0] , + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4] , + s2mm_axi2ip_wrce, + \S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg_0 , + \hsize_vid_reg[15] , + err_i_reg); + output \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg ; + output tstvect_fsync_d2; + output tstvect_fsync_d1; + output s_axis_cmd_tvalid_reg; + output zero_hsize_err; + output zero_vsize_err; + output drop_fsync_d_pulse_gen_fsize_less_err_d1; + output fsize_mismatch_err_s1; + output [15:0]\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 ; + output halt_i0; + output \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0 ; + output \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_irqthresh_decr_mask_sig_reg ; + output [0:0]\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[0] ; + output load_new_addr; + output halted_set_i0; + output s2mm_ftchcmdsts_idle; + output [4:0]D; + output s2mm_dma_interr_set_minus_frame_errors; + output \DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_reg ; + output [48:0]\s_axis_cmd_tdata_reg[63] ; + output \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_fsize_less_err_flag_10_reg ; + output \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF.flag_to_repeat_after_fsize_less_err_reg ; + output \S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg ; + input prmry_reset2; + input s_axis_s2mm_aclk; input [0:0]SR; - input m_axi_mm2s_aclk; - input scndry_reset2; - input m_axis_mm2s_aclk; - input mm2s_halt; + input m_axi_s2mm_aclk; + input s2mm_fsync_out_m_i; + input zero_hsize_err0; + input zero_vsize_err0; + input drop_fsync_d_pulse_gen_fsize_less_err; + input \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg ; + input [3:0]O; + input [3:0]\stride_vid_reg[7] ; + input [3:0]\stride_vid_reg[11] ; + input [3:0]\stride_vid_reg[15] ; + input s2mm_cdc2dmac_fsync; + input s2mm_stop; + input run_stop_d1; + input [1:0]s2mm_dmacr; + input s2mm_soft_reset; + input soft_reset_d1; + input prmry_resetn_i_reg; + input s2mm_tstvect_fsync; + input ch2_delay_cnt_en; + input s2mm_packet_sof; + input ch2_irqthresh_decr_mask_sig; + input s2mm_halt; + input out; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][30] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][29] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][28] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][27] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][26] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][25] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][24] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][23] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][22] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][21] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][20] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][19] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][18] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][17] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][16] ; + input s_axis_cmd_tvalid_reg_0; input [12:0]Q; - input [0:0]\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ; - input all_lines_xfred; - input \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ; - input fifo_wren__0; - input m_axis_mm2s_tready; - input \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ; - input p_15_out; - input [31:0]dm2linebuf_mm2s_tdata; - input [0:0]\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + input datamover_idle; + input [4:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] ; + input flag_to_repeat_after_fsize_less_err; + input [4:0]\GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[4] ; + input halt_i_reg; + input \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg ; + input dma_err; + input [0:0]\INFERRED_GEN.cnt_i_reg[2] ; + input m_axis_s2mm_sts_tready; + input interr_i_reg; + input [3:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[4] ; + input valid_frame_sync_d2; + input [0:0]CO; + input s2mm_fsize_less_err_flag_10; + input \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ; + input \sig_user_reg_out_reg[0] ; + input [0:0]\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4] ; + input [0:0]s2mm_axi2ip_wrce; + input \S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg_0 ; + input [15:0]\hsize_vid_reg[15] ; + input [0:0]err_i_reg; - wire [0:0]DIN; - wire [0:0]\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ; - wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ; - wire \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I_n_2 ; - wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_1 ; - wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ; - wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID_n_6 ; - wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID_n_7 ; - wire \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg_n_0 ; - wire \GEN_LINEBUF_NO_SOF.vsize_counter[0]_i_1_n_0 ; - wire \GEN_LINEBUF_NO_SOF.vsize_counter[10]_i_1_n_0 ; - wire \GEN_LINEBUF_NO_SOF.vsize_counter[11]_i_1_n_0 ; - wire \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 ; - wire \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_3_n_0 ; - wire \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_4_n_0 ; - wire \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_5_n_0 ; - wire \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_7_n_0 ; - wire \GEN_LINEBUF_NO_SOF.vsize_counter[1]_i_1_n_0 ; - wire \GEN_LINEBUF_NO_SOF.vsize_counter[2]_i_1_n_0 ; - wire \GEN_LINEBUF_NO_SOF.vsize_counter[3]_i_1_n_0 ; - wire \GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_1_n_0 ; - wire \GEN_LINEBUF_NO_SOF.vsize_counter[5]_i_1_n_0 ; - wire \GEN_LINEBUF_NO_SOF.vsize_counter[6]_i_1_n_0 ; - wire \GEN_LINEBUF_NO_SOF.vsize_counter[7]_i_1_n_0 ; - wire \GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_1_n_0 ; - wire \GEN_LINEBUF_NO_SOF.vsize_counter[9]_i_1_n_0 ; - wire \GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 ; - wire [0:0]\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + wire [0:0]CO; + wire [4:0]D; + wire \DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_reg ; + wire [4:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] ; + wire \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF.flag_to_repeat_after_fsize_less_err_reg ; + wire [3:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[4] ; + wire \FSM_sequential_dmacntrl_cs[2]_i_5__0_n_0 ; + wire \FSM_sequential_dmacntrl_cs[2]_i_6__0_n_0 ; + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ; + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_3__0_n_0 ; + wire [4:0]\GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[4] ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_17 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_18 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_19 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_20 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_21 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_22 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_23 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_24 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_25 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_26 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_27 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_28 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_29 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_30 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_31 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_32 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_33 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_34 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_35 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_36 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_37 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_38 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_39 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_40 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_41 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_42 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_43 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_44 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_45 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_47 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_48 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_49 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_7 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_i_1_n_0 ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0 ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_irqthresh_decr_mask_sig_reg ; + wire [0:0]\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data[23]_i_1__0_n_0 ; + wire [15:0]\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[0] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[10] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[11] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[12] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[13] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[14] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[15] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[1] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[23] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[2] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[32] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[33] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[34] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[35] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[36] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[37] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[38] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[39] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[3] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[40] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[41] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[42] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[43] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[44] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[45] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[46] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[47] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[48] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[49] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[4] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[50] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[51] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[52] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[53] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[54] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[55] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[56] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[57] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[58] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[59] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[5] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[60] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[61] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[62] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[63] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[6] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[7] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[8] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[9] ; + wire \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg ; + wire [0:0]\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[0] ; + wire \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_fsize_less_err_flag_10_reg ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][16] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][17] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][18] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][19] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][20] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][21] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][22] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][23] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][24] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][25] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][26] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][27] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][28] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][29] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][30] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] ; + wire [0:0]\INFERRED_GEN.cnt_i_reg[2] ; + wire [3:0]O; wire [12:0]Q; + wire \S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg ; + wire \S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg_0 ; wire [0:0]SR; - wire all_lines_xfred; - (* async_reg = "true" *) wire [12:0]crnt_vsize_cdc_tig; - (* async_reg = "true" *) wire [12:0]crnt_vsize_d1; - (* async_reg = "true" *) wire [11:0]data_count_ae_threshold_cdc_tig; - (* async_reg = "true" *) wire [11:0]data_count_ae_threshold_d1; - wire [31:0]dm2linebuf_mm2s_tdata; - wire [33:0]fifo_dout; - wire fifo_full_i; - wire fifo_pipe_empty; - wire fifo_wren__0; - wire m_axi_mm2s_aclk; - wire m_axis_fifo_ainit_nosync; - wire m_axis_mm2s_aclk; - wire [31:0]m_axis_mm2s_tdata; - wire m_axis_mm2s_tlast; - wire m_axis_mm2s_tready; - wire [0:0]m_axis_mm2s_tuser; - wire m_axis_tlast_d1; - wire m_axis_tready_d1; - wire m_axis_tvalid_d1; - wire [12:1]minusOp; - wire minusOp_carry__0_i_1_n_0; - wire minusOp_carry__0_i_2_n_0; - wire minusOp_carry__0_i_3_n_0; - wire minusOp_carry__0_i_4_n_0; - wire minusOp_carry__0_n_0; - wire minusOp_carry__0_n_1; - wire minusOp_carry__0_n_2; - wire minusOp_carry__0_n_3; - wire minusOp_carry__1_i_1_n_0; - wire minusOp_carry__1_i_2_n_0; - wire minusOp_carry__1_i_3_n_0; - wire minusOp_carry__1_i_4_n_0; - wire minusOp_carry__1_n_1; - wire minusOp_carry__1_n_2; - wire minusOp_carry__1_n_3; - wire minusOp_carry_i_1_n_0; - wire minusOp_carry_i_2_n_0; - wire minusOp_carry_i_3_n_0; - wire minusOp_carry_i_4_n_0; - wire minusOp_carry_n_0; - wire minusOp_carry_n_1; - wire minusOp_carry_n_2; - wire minusOp_carry_n_3; - wire mm2s_halt; + wire ch2_delay_cnt_en; + wire ch2_irqthresh_decr_mask_sig; + wire \cmnds_queued[0]_i_1__0_n_0 ; + wire \cmnds_queued[4]_i_2__0_n_0 ; + wire \cmnds_queued[4]_i_3__0_n_0 ; + wire \cmnds_queued[4]_i_4__0_n_0 ; + wire \cmnds_queued[4]_i_5__0_n_0 ; + wire \cmnds_queued[4]_i_6__0_n_0 ; + wire \cmnds_queued[7]_i_2__0_n_0 ; + wire \cmnds_queued[7]_i_4__0_n_0 ; + wire \cmnds_queued[7]_i_5__0_n_0 ; + wire \cmnds_queued[7]_i_6__0_n_0 ; + wire [7:0]cmnds_queued_reg; + wire \cmnds_queued_reg[4]_i_1__0_n_0 ; + wire \cmnds_queued_reg[4]_i_1__0_n_1 ; + wire \cmnds_queued_reg[4]_i_1__0_n_2 ; + wire \cmnds_queued_reg[4]_i_1__0_n_3 ; + wire \cmnds_queued_reg[4]_i_1__0_n_4 ; + wire \cmnds_queued_reg[4]_i_1__0_n_5 ; + wire \cmnds_queued_reg[4]_i_1__0_n_6 ; + wire \cmnds_queued_reg[4]_i_1__0_n_7 ; + wire \cmnds_queued_reg[7]_i_3__0_n_2 ; + wire \cmnds_queued_reg[7]_i_3__0_n_3 ; + wire \cmnds_queued_reg[7]_i_3__0_n_5 ; + wire \cmnds_queued_reg[7]_i_3__0_n_6 ; + wire \cmnds_queued_reg[7]_i_3__0_n_7 ; + wire datamover_idle; + wire [31:16]dm_address_reg; + wire dma_err; + (* RTL_KEEP = "yes" *) wire [2:0]dmacntrl_cs; + wire drop_fsync_d_pulse_gen_fsize_less_err; + wire drop_fsync_d_pulse_gen_fsize_less_err_d1; + wire [0:0]err_i_reg; + wire flag_to_repeat_after_fsize_less_err; + wire frame_sync_d3; + wire frame_sync_reg; + wire fsize_mismatch_err_flag_int; + wire fsize_mismatch_err_s1; + wire halt_i0; + wire halt_i_reg; + wire halted_set_i0; + wire [15:0]\hsize_vid_reg[15] ; + wire interr_i_reg; + wire load_new_addr; + wire m_axi_s2mm_aclk; + wire m_axis_s2mm_sts_tready; wire out; - wire p_0_out; - wire p_15_out; - wire p_1_out; - wire p_4_in; - wire s_axis_fifo_ainit_nosync_reg; - wire s_valid0; - wire scndry_reset2; - wire sig_reset_reg_reg; - wire [12:0]vsize_counter; - wire [3:3]NLW_minusOp_carry__1_CO_UNCONNECTED; + wire prmry_reset2; + wire prmry_resetn_i_reg; + wire run_stop_d1; + wire [0:0]s2mm_axi2ip_wrce; + wire s2mm_cdc2dmac_fsync; + wire s2mm_dma_interr_set_minus_frame_errors; + wire [1:0]s2mm_dmacr; + wire s2mm_fsize_less_err_flag_10; + wire s2mm_fsync_out_m_d1; + wire s2mm_fsync_out_m_i; + wire s2mm_ftchcmdsts_idle; + wire s2mm_halt; + wire s2mm_packet_sof; + wire s2mm_soft_reset; + wire s2mm_stop; + wire s2mm_tstvect_fsync; + wire [48:0]\s_axis_cmd_tdata_reg[63] ; + wire s_axis_cmd_tvalid_reg; + wire s_axis_cmd_tvalid_reg_0; + wire s_axis_s2mm_aclk; + wire \sig_user_reg_out_reg[0] ; + wire soft_reset_d1; + wire [3:0]\stride_vid_reg[11] ; + wire [3:0]\stride_vid_reg[15] ; + wire [3:0]\stride_vid_reg[7] ; + wire tstvect_fsync_d1; + wire tstvect_fsync_d2; + wire valid_frame_sync_d2; + wire [12:0]vert_count_reg; + wire write_cmnd_cmb; + wire zero_hsize_err; + wire zero_hsize_err0; + wire zero_vsize_err; + wire zero_vsize_err0; + wire [3:2]\NLW_cmnds_queued_reg[7]_i_3__0_CO_UNCONNECTED ; + wire [3:3]\NLW_cmnds_queued_reg[7]_i_3__0_O_UNCONNECTED ; - Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized15 \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I - (.\GEN_LINEBUF_NO_SOF.all_lines_xfred_reg (\GEN_LINEBUF_NO_SOF.all_lines_xfred_reg_n_0 ), - .SR(SR), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axis_mm2s_aclk(m_axis_mm2s_aclk), - .p_0_out(p_0_out), - .scndry_reset2(scndry_reset2)); - Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized18 \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I - (.\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ), - .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tready_d1_reg (\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I_n_2 ), - .SR(SR), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axis_fifo_ainit_nosync(m_axis_fifo_ainit_nosync), - .m_axis_mm2s_aclk(m_axis_mm2s_aclk), - .m_axis_mm2s_tready(m_axis_mm2s_tready), - .mm2s_halt(mm2s_halt), - .p_15_out(p_15_out), - .scndry_reset2(scndry_reset2), - .sig_reset_reg_reg(sig_reset_reg_reg)); - Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized14 \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I - (.SR(SR), - .fifo_pipe_empty(fifo_pipe_empty), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axis_mm2s_aclk(m_axis_mm2s_aclk), - .p_1_out(p_1_out), - .scndry_reset2(scndry_reset2)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[0] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(Q[0]), - .Q(crnt_vsize_cdc_tig[0]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[10] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(Q[10]), - .Q(crnt_vsize_cdc_tig[10]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[11] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(Q[11]), - .Q(crnt_vsize_cdc_tig[11]), - .R(1'b0)); - (* ASYNC_REG *) + LUT4 #( + .INIT(16'hFFFE)) + \FSM_sequential_dmacntrl_cs[2]_i_5__0 + (.I0(vert_count_reg[1]), + .I1(vert_count_reg[0]), + .I2(vert_count_reg[9]), + .I3(vert_count_reg[2]), + .O(\FSM_sequential_dmacntrl_cs[2]_i_5__0_n_0 )); + LUT6 #( + .INIT(64'h0000000000000001)) + \FSM_sequential_dmacntrl_cs[2]_i_6__0 + (.I0(vert_count_reg[11]), + .I1(vert_count_reg[8]), + .I2(vert_count_reg[3]), + .I3(vert_count_reg[4]), + .I4(vert_count_reg[5]), + .I5(vert_count_reg[6]), + .O(\FSM_sequential_dmacntrl_cs[2]_i_6__0_n_0 )); (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[12] - (.C(m_axis_mm2s_aclk), + FDRE \FSM_sequential_dmacntrl_cs_reg[0] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(Q[12]), - .Q(crnt_vsize_cdc_tig[12]), - .R(1'b0)); - (* ASYNC_REG *) + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_47 ), + .Q(dmacntrl_cs[0]), + .R(SR)); (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[1] - (.C(m_axis_mm2s_aclk), + FDRE \FSM_sequential_dmacntrl_cs_reg[1] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(Q[1]), - .Q(crnt_vsize_cdc_tig[1]), - .R(1'b0)); - (* ASYNC_REG *) + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_48 ), + .Q(dmacntrl_cs[1]), + .R(SR)); (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[2] - (.C(m_axis_mm2s_aclk), + FDRE \FSM_sequential_dmacntrl_cs_reg[2] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(Q[2]), - .Q(crnt_vsize_cdc_tig[2]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_49 ), + .Q(dmacntrl_cs[2]), + .R(SR)); + LUT5 #( + .INIT(32'hFEFEFFFE)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_3__0 + (.I0(cmnds_queued_reg[1]), + .I1(cmnds_queued_reg[4]), + .I2(cmnds_queued_reg[2]), + .I3(s2mm_dmacr[0]), + .I4(halt_i_reg), + .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_3__0_n_0 )); + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized24 \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF + (.CO(CO), + .D(D), + .\DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_reg (\DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_reg ), + .\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] (\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] ), + .\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF.flag_to_repeat_after_fsize_less_err_reg (\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF.flag_to_repeat_after_fsize_less_err_reg ), + .\DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[4] (\DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[4] ), + .\FSM_sequential_dmacntrl_cs_reg[0] (\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_47 ), + .\FSM_sequential_dmacntrl_cs_reg[1] (\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_48 ), + .\FSM_sequential_dmacntrl_cs_reg[2] (\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_49 ), + .\FSM_sequential_dmacntrl_cs_reg[2]_0 (dmacntrl_cs), + .\GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[4] (\GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[4] ), + .\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg (\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg ), + .\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0 (\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0 ), + .\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_irqthresh_decr_mask_sig_reg (\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_irqthresh_decr_mask_sig_reg ), + .\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[0] (\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[63] (\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 ), + .\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg (\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[0] (\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[0] ), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][16] (\GEN_START_ADDR_REG[1].start_address_vid_reg[1][16] ), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][17] (\GEN_START_ADDR_REG[1].start_address_vid_reg[1][17] ), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][18] (\GEN_START_ADDR_REG[1].start_address_vid_reg[1][18] ), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][19] (\GEN_START_ADDR_REG[1].start_address_vid_reg[1][19] ), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][20] (\GEN_START_ADDR_REG[1].start_address_vid_reg[1][20] ), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][21] (\GEN_START_ADDR_REG[1].start_address_vid_reg[1][21] ), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][22] (\GEN_START_ADDR_REG[1].start_address_vid_reg[1][22] ), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][23] (\GEN_START_ADDR_REG[1].start_address_vid_reg[1][23] ), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][24] (\GEN_START_ADDR_REG[1].start_address_vid_reg[1][24] ), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][25] (\GEN_START_ADDR_REG[1].start_address_vid_reg[1][25] ), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][26] (\GEN_START_ADDR_REG[1].start_address_vid_reg[1][26] ), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][27] (\GEN_START_ADDR_REG[1].start_address_vid_reg[1][27] ), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][28] (\GEN_START_ADDR_REG[1].start_address_vid_reg[1][28] ), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][29] (\GEN_START_ADDR_REG[1].start_address_vid_reg[1][29] ), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][30] (\GEN_START_ADDR_REG[1].start_address_vid_reg[1][30] ), + .\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] (\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] ), + .O({\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_17 ,\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_18 ,\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_19 ,\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_20 }), + .Q(Q), + .SR(SR), + .ch2_delay_cnt_en(ch2_delay_cnt_en), + .ch2_irqthresh_decr_mask_sig(ch2_irqthresh_decr_mask_sig), + .\cmnds_queued_reg[1] (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_3__0_n_0 ), + .\cmnds_queued_reg[7] ({cmnds_queued_reg[7:5],cmnds_queued_reg[3],cmnds_queued_reg[0]}), + .datamover_idle(datamover_idle), + .dm_address_reg(dm_address_reg), + .\dm_address_reg[19] ({\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_30 ,\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_31 ,\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_32 ,\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_33 }), + .\dm_address_reg[23] ({\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_34 ,\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_35 ,\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_36 ,\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_37 }), + .\dm_address_reg[27] ({\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_38 ,\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_39 ,\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_40 ,\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_41 }), + .\dm_address_reg[31] ({\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_42 ,\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_43 ,\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_44 ,\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_45 }), + .\dm_address_reg_0__s_port_] (\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .dma_err(dma_err), + .drop_fsync_d_pulse_gen_fsize_less_err_d1(drop_fsync_d_pulse_gen_fsize_less_err_d1), + .flag_to_repeat_after_fsize_less_err(flag_to_repeat_after_fsize_less_err), + .frame_sync_reg(frame_sync_reg), + .fsize_mismatch_err_flag_int(fsize_mismatch_err_flag_int), + .fsize_mismatch_err_s1(fsize_mismatch_err_s1), + .halt_i0(halt_i0), + .halt_i_reg(halt_i_reg), + .halted_set_i0(halted_set_i0), + .in0(dmacntrl_cs), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out), + .prmry_reset2(prmry_reset2), + .prmry_resetn_i_reg(prmry_resetn_i_reg), + .run_stop_d1(run_stop_d1), + .s2mm_cdc2dmac_fsync(s2mm_cdc2dmac_fsync), + .s2mm_dmacr(s2mm_dmacr), + .s2mm_fsync_out_m_i(s2mm_fsync_out_m_i), + .s2mm_ftchcmdsts_idle(s2mm_ftchcmdsts_idle), + .s2mm_halt(s2mm_halt), + .s2mm_packet_sof(s2mm_packet_sof), + .s2mm_soft_reset(s2mm_soft_reset), + .s2mm_stop(s2mm_stop), + .s2mm_tstvect_fsync(s2mm_tstvect_fsync), + .s_axis_cmd_tvalid_reg(s_axis_cmd_tvalid_reg_0), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk), + .soft_reset_d1(soft_reset_d1), + .valid_frame_sync_d2(valid_frame_sync_d2), + .vert_count_reg(vert_count_reg), + .\vert_count_reg[0]_0 (\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_7 ), + .\vert_count_reg[11] ({\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_25 ,\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_26 ,\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_27 ,\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_28 }), + .\vert_count_reg[11]_0 (\FSM_sequential_dmacntrl_cs[2]_i_6__0_n_0 ), + .\vert_count_reg[12] (\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_29 ), + .\vert_count_reg[7] ({\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_21 ,\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_22 ,\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_23 ,\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_24 }), + .\vert_count_reg_0__s_port_] (load_new_addr), + .vert_count_reg_1__s_port_(\FSM_sequential_dmacntrl_cs[2]_i_5__0_n_0 ), + .write_cmnd_cmb(write_cmnd_cmb)); + FDRE #( + .INIT(1'b0)) + \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.drop_fsync_d_pulse_gen_fsize_less_err_d1_reg + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(drop_fsync_d_pulse_gen_fsize_less_err), + .Q(drop_fsync_d_pulse_gen_fsize_less_err_d1), + .R(prmry_reset2)); + LUT4 #( + .INIT(16'h00E0)) + \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_i_1 + (.I0(fsize_mismatch_err_flag_int), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg ), + .I2(out), + .I3(s2mm_fsync_out_m_d1), + .O(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_i_1_n_0 )); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[3] - (.C(m_axis_mm2s_aclk), + \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(Q[3]), - .Q(crnt_vsize_cdc_tig[3]), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_i_1_n_0 ), + .Q(fsize_mismatch_err_flag_int), .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[4] - (.C(m_axis_mm2s_aclk), + \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_s1_reg + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(Q[4]), - .Q(crnt_vsize_cdc_tig[4]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + .D(\GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg ), + .Q(fsize_mismatch_err_s1), + .R(prmry_reset2)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[5] - (.C(m_axis_mm2s_aclk), + \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.s2mm_fsync_out_m_d1_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(Q[5]), - .Q(crnt_vsize_cdc_tig[5]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[6] - (.C(m_axis_mm2s_aclk), + .D(s2mm_fsync_out_m_i), + .Q(s2mm_fsync_out_m_d1), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair51" *) + LUT3 #( + .INIT(8'hB8)) + \GEN_NORMAL_DM_COMMAND.cmnd_data[23]_i_1__0 + (.I0(out), + .I1(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .I2(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[23] ), + .O(\GEN_NORMAL_DM_COMMAND.cmnd_data[23]_i_1__0_n_0 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\hsize_vid_reg[15] [0]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[0] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\hsize_vid_reg[15] [10]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[10] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\hsize_vid_reg[15] [11]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[11] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\hsize_vid_reg[15] [12]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[12] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[13] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\hsize_vid_reg[15] [13]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[13] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[14] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\hsize_vid_reg[15] [14]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[14] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\hsize_vid_reg[15] [15]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[15] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\hsize_vid_reg[15] [1]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[1] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[23] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(Q[6]), - .Q(crnt_vsize_cdc_tig[6]), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data[23]_i_1__0_n_0 ), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[23] ), .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\hsize_vid_reg[15] [2]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[2] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[32] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [0]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[32] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[33] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [1]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[33] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[34] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [2]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[34] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[35] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [3]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[35] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[36] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [4]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[36] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[37] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [5]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[37] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[38] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [6]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[38] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[39] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [7]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[39] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\hsize_vid_reg[15] [3]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[3] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[40] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [8]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[40] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[41] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [9]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[41] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[42] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [10]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[42] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[43] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [11]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[43] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[44] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [12]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[44] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[45] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [13]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[45] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[46] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [14]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[46] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [15]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[47] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[48] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(dm_address_reg[16]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[48] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[49] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(dm_address_reg[17]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[49] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\hsize_vid_reg[15] [4]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[4] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[50] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(dm_address_reg[18]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[50] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[51] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(dm_address_reg[19]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[51] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[52] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(dm_address_reg[20]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[52] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[53] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(dm_address_reg[21]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[53] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[54] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(dm_address_reg[22]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[54] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[55] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(dm_address_reg[23]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[55] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[56] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(dm_address_reg[24]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[56] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[57] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(dm_address_reg[25]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[57] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[58] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(dm_address_reg[26]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[58] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[59] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(dm_address_reg[27]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[59] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\hsize_vid_reg[15] [5]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[5] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[60] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(dm_address_reg[28]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[60] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[61] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(dm_address_reg[29]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[61] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[62] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(dm_address_reg[30]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[62] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[63] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(dm_address_reg[31]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[63] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\hsize_vid_reg[15] [6]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[6] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\hsize_vid_reg[15] [7]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[7] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\hsize_vid_reg[15] [8]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[8] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); + FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8 ), + .D(\hsize_vid_reg[15] [9]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[9] ), + .R(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46 )); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[7] - (.C(m_axis_mm2s_aclk), + \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(Q[7]), - .Q(crnt_vsize_cdc_tig[7]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + .D(write_cmnd_cmb), + .Q(s_axis_cmd_tvalid_reg), + .R(SR)); + LUT5 #( + .INIT(32'hFE000000)) + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_fsize_less_err_flag_10_i_1 + (.I0(s2mm_fsize_less_err_flag_10), + .I1(fsize_mismatch_err_s1), + .I2(drop_fsync_d_pulse_gen_fsize_less_err_d1), + .I3(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ), + .I4(\sig_user_reg_out_reg[0] ), + .O(\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_fsize_less_err_flag_10_reg )); + LUT6 #( + .INIT(64'hFFFFFFF7FFFFFFF0)) + \I_DMA_REGISTER/S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_i_1 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4] ), + .I1(s2mm_axi2ip_wrce), + .I2(interr_i_reg), + .I3(zero_vsize_err), + .I4(zero_hsize_err), + .I5(\S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg_0 ), + .O(\S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg )); + LUT1 #( + .INIT(2'h1)) + \cmnds_queued[0]_i_1__0 + (.I0(cmnds_queued_reg[0]), + .O(\cmnds_queued[0]_i_1__0_n_0 )); + LUT1 #( + .INIT(2'h1)) + \cmnds_queued[4]_i_2__0 + (.I0(cmnds_queued_reg[1]), + .O(\cmnds_queued[4]_i_2__0_n_0 )); + LUT2 #( + .INIT(4'h9)) + \cmnds_queued[4]_i_3__0 + (.I0(cmnds_queued_reg[3]), + .I1(cmnds_queued_reg[4]), + .O(\cmnds_queued[4]_i_3__0_n_0 )); + LUT2 #( + .INIT(4'h9)) + \cmnds_queued[4]_i_4__0 + (.I0(cmnds_queued_reg[2]), + .I1(cmnds_queued_reg[3]), + .O(\cmnds_queued[4]_i_4__0_n_0 )); + LUT2 #( + .INIT(4'h9)) + \cmnds_queued[4]_i_5__0 + (.I0(cmnds_queued_reg[1]), + .I1(cmnds_queued_reg[2]), + .O(\cmnds_queued[4]_i_5__0_n_0 )); + LUT4 #( + .INIT(16'hA655)) + \cmnds_queued[4]_i_6__0 + (.I0(cmnds_queued_reg[1]), + .I1(m_axis_s2mm_sts_tready), + .I2(\INFERRED_GEN.cnt_i_reg[2] ), + .I3(s_axis_cmd_tvalid_reg), + .O(\cmnds_queued[4]_i_6__0_n_0 )); + LUT3 #( + .INIT(8'h9A)) + \cmnds_queued[7]_i_2__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\INFERRED_GEN.cnt_i_reg[2] ), + .I2(m_axis_s2mm_sts_tready), + .O(\cmnds_queued[7]_i_2__0_n_0 )); + LUT2 #( + .INIT(4'h9)) + \cmnds_queued[7]_i_4__0 + (.I0(cmnds_queued_reg[6]), + .I1(cmnds_queued_reg[7]), + .O(\cmnds_queued[7]_i_4__0_n_0 )); + LUT2 #( + .INIT(4'h9)) + \cmnds_queued[7]_i_5__0 + (.I0(cmnds_queued_reg[5]), + .I1(cmnds_queued_reg[6]), + .O(\cmnds_queued[7]_i_5__0_n_0 )); + LUT2 #( + .INIT(4'h9)) + \cmnds_queued[7]_i_6__0 + (.I0(cmnds_queued_reg[4]), + .I1(cmnds_queued_reg[5]), + .O(\cmnds_queued[7]_i_6__0_n_0 )); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[8] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(Q[8]), - .Q(crnt_vsize_cdc_tig[8]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \cmnds_queued_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(\cmnds_queued[7]_i_2__0_n_0 ), + .D(\cmnds_queued[0]_i_1__0_n_0 ), + .Q(cmnds_queued_reg[0]), + .R(err_i_reg)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[9] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(Q[9]), - .Q(crnt_vsize_cdc_tig[9]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \cmnds_queued_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(\cmnds_queued[7]_i_2__0_n_0 ), + .D(\cmnds_queued_reg[4]_i_1__0_n_7 ), + .Q(cmnds_queued_reg[1]), + .R(err_i_reg)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[0] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(crnt_vsize_cdc_tig[0]), - .Q(crnt_vsize_d1[0]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \cmnds_queued_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(\cmnds_queued[7]_i_2__0_n_0 ), + .D(\cmnds_queued_reg[4]_i_1__0_n_6 ), + .Q(cmnds_queued_reg[2]), + .R(err_i_reg)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[10] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(crnt_vsize_cdc_tig[10]), - .Q(crnt_vsize_d1[10]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \cmnds_queued_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(\cmnds_queued[7]_i_2__0_n_0 ), + .D(\cmnds_queued_reg[4]_i_1__0_n_5 ), + .Q(cmnds_queued_reg[3]), + .R(err_i_reg)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[11] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(crnt_vsize_cdc_tig[11]), - .Q(crnt_vsize_d1[11]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \cmnds_queued_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(\cmnds_queued[7]_i_2__0_n_0 ), + .D(\cmnds_queued_reg[4]_i_1__0_n_4 ), + .Q(cmnds_queued_reg[4]), + .R(err_i_reg)); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \cmnds_queued_reg[4]_i_1__0 + (.CI(1'b0), + .CO({\cmnds_queued_reg[4]_i_1__0_n_0 ,\cmnds_queued_reg[4]_i_1__0_n_1 ,\cmnds_queued_reg[4]_i_1__0_n_2 ,\cmnds_queued_reg[4]_i_1__0_n_3 }), + .CYINIT(cmnds_queued_reg[0]), + .DI({cmnds_queued_reg[3:1],\cmnds_queued[4]_i_2__0_n_0 }), + .O({\cmnds_queued_reg[4]_i_1__0_n_4 ,\cmnds_queued_reg[4]_i_1__0_n_5 ,\cmnds_queued_reg[4]_i_1__0_n_6 ,\cmnds_queued_reg[4]_i_1__0_n_7 }), + .S({\cmnds_queued[4]_i_3__0_n_0 ,\cmnds_queued[4]_i_4__0_n_0 ,\cmnds_queued[4]_i_5__0_n_0 ,\cmnds_queued[4]_i_6__0_n_0 })); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[12] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(crnt_vsize_cdc_tig[12]), - .Q(crnt_vsize_d1[12]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \cmnds_queued_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(\cmnds_queued[7]_i_2__0_n_0 ), + .D(\cmnds_queued_reg[7]_i_3__0_n_7 ), + .Q(cmnds_queued_reg[5]), + .R(err_i_reg)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[1] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(crnt_vsize_cdc_tig[1]), - .Q(crnt_vsize_d1[1]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \cmnds_queued_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(\cmnds_queued[7]_i_2__0_n_0 ), + .D(\cmnds_queued_reg[7]_i_3__0_n_6 ), + .Q(cmnds_queued_reg[6]), + .R(err_i_reg)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[2] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(crnt_vsize_cdc_tig[2]), - .Q(crnt_vsize_d1[2]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \cmnds_queued_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(\cmnds_queued[7]_i_2__0_n_0 ), + .D(\cmnds_queued_reg[7]_i_3__0_n_5 ), + .Q(cmnds_queued_reg[7]), + .R(err_i_reg)); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \cmnds_queued_reg[7]_i_3__0 + (.CI(\cmnds_queued_reg[4]_i_1__0_n_0 ), + .CO({\NLW_cmnds_queued_reg[7]_i_3__0_CO_UNCONNECTED [3:2],\cmnds_queued_reg[7]_i_3__0_n_2 ,\cmnds_queued_reg[7]_i_3__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,cmnds_queued_reg[5:4]}), + .O({\NLW_cmnds_queued_reg[7]_i_3__0_O_UNCONNECTED [3],\cmnds_queued_reg[7]_i_3__0_n_5 ,\cmnds_queued_reg[7]_i_3__0_n_6 ,\cmnds_queued_reg[7]_i_3__0_n_7 }), + .S({1'b0,\cmnds_queued[7]_i_4__0_n_0 ,\cmnds_queued[7]_i_5__0_n_0 ,\cmnds_queued[7]_i_6__0_n_0 })); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[3] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(crnt_vsize_cdc_tig[3]), - .Q(crnt_vsize_d1[3]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \dm_address_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(O[0]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [0]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[4] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(crnt_vsize_cdc_tig[4]), - .Q(crnt_vsize_d1[4]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \dm_address_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(\stride_vid_reg[11] [2]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [10]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[5] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(crnt_vsize_cdc_tig[5]), - .Q(crnt_vsize_d1[5]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \dm_address_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(\stride_vid_reg[11] [3]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [11]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[6] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(crnt_vsize_cdc_tig[6]), - .Q(crnt_vsize_d1[6]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \dm_address_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(\stride_vid_reg[15] [0]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [12]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[7] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(crnt_vsize_cdc_tig[7]), - .Q(crnt_vsize_d1[7]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \dm_address_reg[13] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(\stride_vid_reg[15] [1]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [13]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[8] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(crnt_vsize_cdc_tig[8]), - .Q(crnt_vsize_d1[8]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \dm_address_reg[14] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(\stride_vid_reg[15] [2]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [14]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[9] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(crnt_vsize_cdc_tig[9]), - .Q(crnt_vsize_d1[9]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \dm_address_reg[15] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(\stride_vid_reg[15] [3]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [15]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[0] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(1'b0), - .Q(data_count_ae_threshold_cdc_tig[0]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \dm_address_reg[16] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_33 ), + .Q(dm_address_reg[16]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[10] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(1'b0), - .Q(data_count_ae_threshold_cdc_tig[10]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \dm_address_reg[17] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_32 ), + .Q(dm_address_reg[17]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[11] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(1'b0), - .Q(data_count_ae_threshold_cdc_tig[11]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \dm_address_reg[18] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_31 ), + .Q(dm_address_reg[18]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[1] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(1'b0), - .Q(data_count_ae_threshold_cdc_tig[1]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \dm_address_reg[19] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_30 ), + .Q(dm_address_reg[19]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[2] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(1'b0), - .Q(data_count_ae_threshold_cdc_tig[2]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \dm_address_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(O[1]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [1]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[3] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(1'b0), - .Q(data_count_ae_threshold_cdc_tig[3]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \dm_address_reg[20] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_37 ), + .Q(dm_address_reg[20]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[4] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(1'b0), - .Q(data_count_ae_threshold_cdc_tig[4]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \dm_address_reg[21] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_36 ), + .Q(dm_address_reg[21]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[5] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(1'b0), - .Q(data_count_ae_threshold_cdc_tig[5]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \dm_address_reg[22] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_35 ), + .Q(dm_address_reg[22]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[6] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(1'b0), - .Q(data_count_ae_threshold_cdc_tig[6]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \dm_address_reg[23] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_34 ), + .Q(dm_address_reg[23]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[7] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(1'b0), - .Q(data_count_ae_threshold_cdc_tig[7]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \dm_address_reg[24] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_41 ), + .Q(dm_address_reg[24]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[8] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(1'b0), - .Q(data_count_ae_threshold_cdc_tig[8]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \dm_address_reg[25] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_40 ), + .Q(dm_address_reg[25]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[9] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(1'b0), - .Q(data_count_ae_threshold_cdc_tig[9]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \dm_address_reg[26] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_39 ), + .Q(dm_address_reg[26]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[0] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(data_count_ae_threshold_cdc_tig[0]), - .Q(data_count_ae_threshold_d1[0]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \dm_address_reg[27] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_38 ), + .Q(dm_address_reg[27]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[10] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(data_count_ae_threshold_cdc_tig[10]), - .Q(data_count_ae_threshold_d1[10]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \dm_address_reg[28] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_45 ), + .Q(dm_address_reg[28]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[11] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(data_count_ae_threshold_cdc_tig[11]), - .Q(data_count_ae_threshold_d1[11]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \dm_address_reg[29] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_44 ), + .Q(dm_address_reg[29]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[1] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(data_count_ae_threshold_cdc_tig[1]), - .Q(data_count_ae_threshold_d1[1]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \dm_address_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(O[2]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [2]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[2] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(data_count_ae_threshold_cdc_tig[2]), - .Q(data_count_ae_threshold_d1[2]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \dm_address_reg[30] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_43 ), + .Q(dm_address_reg[30]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[3] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(data_count_ae_threshold_cdc_tig[3]), - .Q(data_count_ae_threshold_d1[3]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \dm_address_reg[31] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_42 ), + .Q(dm_address_reg[31]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[4] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(data_count_ae_threshold_cdc_tig[4]), - .Q(data_count_ae_threshold_d1[4]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \dm_address_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(O[3]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [3]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[5] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(data_count_ae_threshold_cdc_tig[5]), - .Q(data_count_ae_threshold_d1[5]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \dm_address_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(\stride_vid_reg[7] [0]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [4]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[6] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(data_count_ae_threshold_cdc_tig[6]), - .Q(data_count_ae_threshold_d1[6]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \dm_address_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(\stride_vid_reg[7] [1]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [5]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[7] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(data_count_ae_threshold_cdc_tig[7]), - .Q(data_count_ae_threshold_d1[7]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \dm_address_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(\stride_vid_reg[7] [2]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [6]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[8] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(data_count_ae_threshold_cdc_tig[8]), - .Q(data_count_ae_threshold_d1[8]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \dm_address_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(\stride_vid_reg[7] [3]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [7]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[9] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(data_count_ae_threshold_cdc_tig[9]), - .Q(data_count_ae_threshold_d1[9]), - .R(1'b0)); - Arty_Z7_20_axi_vdma_0_0_axi_vdma_afifo_builtin \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO - (.DIN({DIN,\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] }), - .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), - .fifo_dout(fifo_dout), - .fifo_full_i(fifo_full_i), - .fifo_wren__0(fifo_wren__0), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axis_mm2s_aclk(m_axis_mm2s_aclk), - .out(p_4_in), - .s_axis_fifo_ainit_nosync_reg(s_axis_fifo_ainit_nosync_reg), - .sig_m_valid_out_reg(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_1 )); + \dm_address_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(\stride_vid_reg[11] [0]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [8]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ), - .Q(DIN), - .R(1'b0)); - Arty_Z7_20_axi_vdma_0_0_axi_vdma_skid_buf \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID - (.\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 (sig_reset_reg_reg), - .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ), - .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_1 ), - .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tlast_d1_reg (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID_n_6 ), - .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tvalid_d1_reg (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID_n_7 ), - .\GEN_LINEBUF_NO_SOF.all_lines_xfred_reg (\GEN_LINEBUF_NO_SOF.all_lines_xfred_reg_n_0 ), - .fifo_dout(fifo_dout), - .fifo_pipe_empty(fifo_pipe_empty), - .m_axis_fifo_ainit_nosync(m_axis_fifo_ainit_nosync), - .m_axis_mm2s_aclk(m_axis_mm2s_aclk), - .m_axis_mm2s_tdata(m_axis_mm2s_tdata), - .m_axis_mm2s_tlast(m_axis_mm2s_tlast), - .m_axis_mm2s_tready(m_axis_mm2s_tready), - .m_axis_mm2s_tuser(m_axis_mm2s_tuser), - .m_axis_mm2s_tvalid(out), - .out(p_4_in), - .p_15_out(p_15_out), - .s_valid0(s_valid0)); + \dm_address_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5 ), + .D(\stride_vid_reg[11] [1]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [9]), + .R(SR)); + LUT3 #( + .INIT(8'hFE)) + dma_interr_i_3 + (.I0(interr_i_reg), + .I1(zero_vsize_err), + .I2(zero_hsize_err), + .O(s2mm_dma_interr_set_minus_frame_errors)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tlast_d1_reg - (.C(m_axis_mm2s_aclk), + frame_sync_d1_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID_n_6 ), - .Q(m_axis_tlast_d1), - .R(1'b0)); + .D(s2mm_cdc2dmac_fsync), + .Q(tstvect_fsync_d1), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tready_d1_reg - (.C(m_axis_mm2s_aclk), + frame_sync_d2_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I_n_2 ), - .Q(m_axis_tready_d1), - .R(1'b0)); + .D(tstvect_fsync_d1), + .Q(tstvect_fsync_d2), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tvalid_d1_reg - (.C(m_axis_mm2s_aclk), + frame_sync_d3_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID_n_7 ), - .Q(m_axis_tvalid_d1), - .R(1'b0)); - FDSE #( - .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg - (.C(m_axis_mm2s_aclk), - .CE(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 ), - .D(all_lines_xfred), - .Q(\GEN_LINEBUF_NO_SOF.all_lines_xfred_reg_n_0 ), - .S(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 )); - FDSE #( + .D(tstvect_fsync_d2), + .Q(frame_sync_d3), + .R(SR)); + FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.s_axis_fifo_ainit_nosync_reg_reg - (.C(m_axi_mm2s_aclk), + frame_sync_reg_reg + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(mm2s_halt), - .Q(s_axis_fifo_ainit_nosync_reg), - .S(SR)); - LUT4 #( - .INIT(16'h8B88)) - \GEN_LINEBUF_NO_SOF.vsize_counter[0]_i_1 - (.I0(crnt_vsize_d1[0]), - .I1(p_15_out), - .I2(vsize_counter[0]), - .I3(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 ), - .O(\GEN_LINEBUF_NO_SOF.vsize_counter[0]_i_1_n_0 )); - LUT4 #( - .INIT(16'hB888)) - \GEN_LINEBUF_NO_SOF.vsize_counter[10]_i_1 - (.I0(crnt_vsize_d1[10]), - .I1(p_15_out), - .I2(minusOp[10]), - .I3(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 ), - .O(\GEN_LINEBUF_NO_SOF.vsize_counter[10]_i_1_n_0 )); - LUT4 #( - .INIT(16'hB888)) - \GEN_LINEBUF_NO_SOF.vsize_counter[11]_i_1 - (.I0(crnt_vsize_d1[11]), - .I1(p_15_out), - .I2(minusOp[11]), - .I3(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 ), - .O(\GEN_LINEBUF_NO_SOF.vsize_counter[11]_i_1_n_0 )); - LUT6 #( - .INIT(64'hBBBBBBBBBBBBBBBA)) - \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2 - (.I0(p_15_out), - .I1(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_4_n_0 ), - .I2(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_5_n_0 ), - .I3(vsize_counter[3]), - .I4(vsize_counter[4]), - .I5(vsize_counter[0]), - .O(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 )); - LUT4 #( - .INIT(16'hB888)) - \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_3 - (.I0(crnt_vsize_d1[12]), - .I1(p_15_out), - .I2(minusOp[12]), - .I3(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 ), - .O(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_3_n_0 )); - LUT3 #( - .INIT(8'h7F)) - \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_4 - (.I0(m_axis_tvalid_d1), - .I1(m_axis_tlast_d1), - .I2(m_axis_tready_d1), - .O(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_4_n_0 )); - LUT5 #( - .INIT(32'hFFFFFFFE)) - \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_5 - (.I0(vsize_counter[1]), - .I1(vsize_counter[10]), - .I2(vsize_counter[7]), - .I3(vsize_counter[12]), - .I4(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_7_n_0 ), - .O(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_5_n_0 )); - LUT5 #( - .INIT(32'hFFFFFEFF)) - \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_6 - (.I0(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_5_n_0 ), - .I1(vsize_counter[4]), - .I2(vsize_counter[3]), - .I3(vsize_counter[0]), - .I4(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_4_n_0 ), - .O(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 )); - LUT6 #( - .INIT(64'hFFFFFFFFFFFFFFFE)) - \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_7 - (.I0(vsize_counter[11]), - .I1(vsize_counter[6]), - .I2(vsize_counter[2]), - .I3(vsize_counter[8]), - .I4(vsize_counter[5]), - .I5(vsize_counter[9]), - .O(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_7_n_0 )); - LUT4 #( - .INIT(16'hB888)) - \GEN_LINEBUF_NO_SOF.vsize_counter[1]_i_1 - (.I0(crnt_vsize_d1[1]), - .I1(p_15_out), - .I2(minusOp[1]), - .I3(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 ), - .O(\GEN_LINEBUF_NO_SOF.vsize_counter[1]_i_1_n_0 )); - LUT4 #( - .INIT(16'hB888)) - \GEN_LINEBUF_NO_SOF.vsize_counter[2]_i_1 - (.I0(crnt_vsize_d1[2]), - .I1(p_15_out), - .I2(minusOp[2]), - .I3(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 ), - .O(\GEN_LINEBUF_NO_SOF.vsize_counter[2]_i_1_n_0 )); - LUT4 #( - .INIT(16'hB888)) - \GEN_LINEBUF_NO_SOF.vsize_counter[3]_i_1 - (.I0(crnt_vsize_d1[3]), - .I1(p_15_out), - .I2(minusOp[3]), - .I3(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 ), - .O(\GEN_LINEBUF_NO_SOF.vsize_counter[3]_i_1_n_0 )); - LUT4 #( - .INIT(16'hB888)) - \GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_1 - (.I0(crnt_vsize_d1[4]), - .I1(p_15_out), - .I2(minusOp[4]), - .I3(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 ), - .O(\GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_1_n_0 )); - LUT4 #( - .INIT(16'hB888)) - \GEN_LINEBUF_NO_SOF.vsize_counter[5]_i_1 - (.I0(crnt_vsize_d1[5]), - .I1(p_15_out), - .I2(minusOp[5]), - .I3(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 ), - .O(\GEN_LINEBUF_NO_SOF.vsize_counter[5]_i_1_n_0 )); - LUT4 #( - .INIT(16'hB888)) - \GEN_LINEBUF_NO_SOF.vsize_counter[6]_i_1 - (.I0(crnt_vsize_d1[6]), - .I1(p_15_out), - .I2(minusOp[6]), - .I3(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 ), - .O(\GEN_LINEBUF_NO_SOF.vsize_counter[6]_i_1_n_0 )); - LUT4 #( - .INIT(16'hB888)) - \GEN_LINEBUF_NO_SOF.vsize_counter[7]_i_1 - (.I0(crnt_vsize_d1[7]), - .I1(p_15_out), - .I2(minusOp[7]), - .I3(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 ), - .O(\GEN_LINEBUF_NO_SOF.vsize_counter[7]_i_1_n_0 )); - LUT4 #( - .INIT(16'hB888)) - \GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_1 - (.I0(crnt_vsize_d1[8]), - .I1(p_15_out), - .I2(minusOp[8]), - .I3(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 ), - .O(\GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_1_n_0 )); - LUT4 #( - .INIT(16'hB888)) - \GEN_LINEBUF_NO_SOF.vsize_counter[9]_i_1 - (.I0(crnt_vsize_d1[9]), - .I1(p_15_out), - .I2(minusOp[9]), - .I3(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0 ), - .O(\GEN_LINEBUF_NO_SOF.vsize_counter[9]_i_1_n_0 )); + .D(frame_sync_d3), + .Q(frame_sync_reg), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair75" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[0]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[0] ), + .O(\s_axis_cmd_tdata_reg[63] [0])); + (* SOFT_HLUTNM = "soft_lutpair70" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[10]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[10] ), + .O(\s_axis_cmd_tdata_reg[63] [10])); + (* SOFT_HLUTNM = "soft_lutpair70" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[11]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[11] ), + .O(\s_axis_cmd_tdata_reg[63] [11])); + (* SOFT_HLUTNM = "soft_lutpair69" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[12]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[12] ), + .O(\s_axis_cmd_tdata_reg[63] [12])); + (* SOFT_HLUTNM = "soft_lutpair69" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[13]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[13] ), + .O(\s_axis_cmd_tdata_reg[63] [13])); + (* SOFT_HLUTNM = "soft_lutpair68" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[14]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[14] ), + .O(\s_axis_cmd_tdata_reg[63] [14])); + (* SOFT_HLUTNM = "soft_lutpair68" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[15]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[15] ), + .O(\s_axis_cmd_tdata_reg[63] [15])); + (* SOFT_HLUTNM = "soft_lutpair75" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[1]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[1] ), + .O(\s_axis_cmd_tdata_reg[63] [1])); + (* SOFT_HLUTNM = "soft_lutpair51" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[23]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[23] ), + .O(\s_axis_cmd_tdata_reg[63] [16])); + (* SOFT_HLUTNM = "soft_lutpair74" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[2]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[2] ), + .O(\s_axis_cmd_tdata_reg[63] [2])); + (* SOFT_HLUTNM = "soft_lutpair67" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[32]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[32] ), + .O(\s_axis_cmd_tdata_reg[63] [17])); + (* SOFT_HLUTNM = "soft_lutpair67" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[33]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[33] ), + .O(\s_axis_cmd_tdata_reg[63] [18])); + (* SOFT_HLUTNM = "soft_lutpair66" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[34]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[34] ), + .O(\s_axis_cmd_tdata_reg[63] [19])); + (* SOFT_HLUTNM = "soft_lutpair66" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[35]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[35] ), + .O(\s_axis_cmd_tdata_reg[63] [20])); + (* SOFT_HLUTNM = "soft_lutpair65" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[36]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[36] ), + .O(\s_axis_cmd_tdata_reg[63] [21])); + (* SOFT_HLUTNM = "soft_lutpair65" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[37]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[37] ), + .O(\s_axis_cmd_tdata_reg[63] [22])); + (* SOFT_HLUTNM = "soft_lutpair64" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[38]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[38] ), + .O(\s_axis_cmd_tdata_reg[63] [23])); + (* SOFT_HLUTNM = "soft_lutpair64" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[39]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[39] ), + .O(\s_axis_cmd_tdata_reg[63] [24])); + (* SOFT_HLUTNM = "soft_lutpair74" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[3]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[3] ), + .O(\s_axis_cmd_tdata_reg[63] [3])); + (* SOFT_HLUTNM = "soft_lutpair63" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[40]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[40] ), + .O(\s_axis_cmd_tdata_reg[63] [25])); + (* SOFT_HLUTNM = "soft_lutpair63" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[41]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[41] ), + .O(\s_axis_cmd_tdata_reg[63] [26])); + (* SOFT_HLUTNM = "soft_lutpair62" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[42]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[42] ), + .O(\s_axis_cmd_tdata_reg[63] [27])); + (* SOFT_HLUTNM = "soft_lutpair62" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[43]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[43] ), + .O(\s_axis_cmd_tdata_reg[63] [28])); + (* SOFT_HLUTNM = "soft_lutpair61" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[44]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[44] ), + .O(\s_axis_cmd_tdata_reg[63] [29])); + (* SOFT_HLUTNM = "soft_lutpair61" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[45]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[45] ), + .O(\s_axis_cmd_tdata_reg[63] [30])); + (* SOFT_HLUTNM = "soft_lutpair60" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[46]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[46] ), + .O(\s_axis_cmd_tdata_reg[63] [31])); + (* SOFT_HLUTNM = "soft_lutpair60" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[47]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[47] ), + .O(\s_axis_cmd_tdata_reg[63] [32])); + (* SOFT_HLUTNM = "soft_lutpair59" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[48]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[48] ), + .O(\s_axis_cmd_tdata_reg[63] [33])); + (* SOFT_HLUTNM = "soft_lutpair59" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[49]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[49] ), + .O(\s_axis_cmd_tdata_reg[63] [34])); + (* SOFT_HLUTNM = "soft_lutpair73" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[4]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[4] ), + .O(\s_axis_cmd_tdata_reg[63] [4])); + (* SOFT_HLUTNM = "soft_lutpair58" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[50]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[50] ), + .O(\s_axis_cmd_tdata_reg[63] [35])); + (* SOFT_HLUTNM = "soft_lutpair58" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[51]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[51] ), + .O(\s_axis_cmd_tdata_reg[63] [36])); + (* SOFT_HLUTNM = "soft_lutpair57" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[52]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[52] ), + .O(\s_axis_cmd_tdata_reg[63] [37])); + (* SOFT_HLUTNM = "soft_lutpair57" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[53]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[53] ), + .O(\s_axis_cmd_tdata_reg[63] [38])); + (* SOFT_HLUTNM = "soft_lutpair56" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[54]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[54] ), + .O(\s_axis_cmd_tdata_reg[63] [39])); + (* SOFT_HLUTNM = "soft_lutpair56" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[55]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[55] ), + .O(\s_axis_cmd_tdata_reg[63] [40])); + (* SOFT_HLUTNM = "soft_lutpair55" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[56]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[56] ), + .O(\s_axis_cmd_tdata_reg[63] [41])); + (* SOFT_HLUTNM = "soft_lutpair55" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[57]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[57] ), + .O(\s_axis_cmd_tdata_reg[63] [42])); + (* SOFT_HLUTNM = "soft_lutpair54" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[58]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[58] ), + .O(\s_axis_cmd_tdata_reg[63] [43])); + (* SOFT_HLUTNM = "soft_lutpair54" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[59]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[59] ), + .O(\s_axis_cmd_tdata_reg[63] [44])); + (* SOFT_HLUTNM = "soft_lutpair73" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[5]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[5] ), + .O(\s_axis_cmd_tdata_reg[63] [5])); + (* SOFT_HLUTNM = "soft_lutpair52" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[60]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[60] ), + .O(\s_axis_cmd_tdata_reg[63] [45])); + (* SOFT_HLUTNM = "soft_lutpair53" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[61]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[61] ), + .O(\s_axis_cmd_tdata_reg[63] [46])); + (* SOFT_HLUTNM = "soft_lutpair53" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[62]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[62] ), + .O(\s_axis_cmd_tdata_reg[63] [47])); + (* SOFT_HLUTNM = "soft_lutpair52" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[63]_i_3__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[63] ), + .O(\s_axis_cmd_tdata_reg[63] [48])); + (* SOFT_HLUTNM = "soft_lutpair72" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[6]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[6] ), + .O(\s_axis_cmd_tdata_reg[63] [6])); + (* SOFT_HLUTNM = "soft_lutpair72" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[7]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[7] ), + .O(\s_axis_cmd_tdata_reg[63] [7])); + (* SOFT_HLUTNM = "soft_lutpair71" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[8]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[8] ), + .O(\s_axis_cmd_tdata_reg[63] [8])); + (* SOFT_HLUTNM = "soft_lutpair71" *) + LUT2 #( + .INIT(4'h8)) + \s_axis_cmd_tdata[9]_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[9] ), + .O(\s_axis_cmd_tdata_reg[63] [9])); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.vsize_counter_reg[0] - (.C(m_axis_mm2s_aclk), - .CE(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 ), - .D(\GEN_LINEBUF_NO_SOF.vsize_counter[0]_i_1_n_0 ), - .Q(vsize_counter[0]), - .R(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 )); + \vert_count_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_7 ), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_20 ), + .Q(vert_count_reg[0]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.vsize_counter_reg[10] - (.C(m_axis_mm2s_aclk), - .CE(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 ), - .D(\GEN_LINEBUF_NO_SOF.vsize_counter[10]_i_1_n_0 ), - .Q(vsize_counter[10]), - .R(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 )); + \vert_count_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_7 ), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_26 ), + .Q(vert_count_reg[10]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.vsize_counter_reg[11] - (.C(m_axis_mm2s_aclk), - .CE(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 ), - .D(\GEN_LINEBUF_NO_SOF.vsize_counter[11]_i_1_n_0 ), - .Q(vsize_counter[11]), - .R(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 )); + \vert_count_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_7 ), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_25 ), + .Q(vert_count_reg[11]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.vsize_counter_reg[12] - (.C(m_axis_mm2s_aclk), - .CE(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 ), - .D(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_3_n_0 ), - .Q(vsize_counter[12]), - .R(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 )); + \vert_count_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_7 ), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_29 ), + .Q(vert_count_reg[12]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.vsize_counter_reg[1] - (.C(m_axis_mm2s_aclk), - .CE(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 ), - .D(\GEN_LINEBUF_NO_SOF.vsize_counter[1]_i_1_n_0 ), - .Q(vsize_counter[1]), - .R(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 )); + \vert_count_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_7 ), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_19 ), + .Q(vert_count_reg[1]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.vsize_counter_reg[2] - (.C(m_axis_mm2s_aclk), - .CE(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 ), - .D(\GEN_LINEBUF_NO_SOF.vsize_counter[2]_i_1_n_0 ), - .Q(vsize_counter[2]), - .R(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 )); + \vert_count_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_7 ), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_18 ), + .Q(vert_count_reg[2]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.vsize_counter_reg[3] - (.C(m_axis_mm2s_aclk), - .CE(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 ), - .D(\GEN_LINEBUF_NO_SOF.vsize_counter[3]_i_1_n_0 ), - .Q(vsize_counter[3]), - .R(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 )); + \vert_count_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_7 ), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_17 ), + .Q(vert_count_reg[3]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4] - (.C(m_axis_mm2s_aclk), - .CE(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 ), - .D(\GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_1_n_0 ), - .Q(vsize_counter[4]), - .R(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 )); + \vert_count_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_7 ), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_24 ), + .Q(vert_count_reg[4]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.vsize_counter_reg[5] - (.C(m_axis_mm2s_aclk), - .CE(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 ), - .D(\GEN_LINEBUF_NO_SOF.vsize_counter[5]_i_1_n_0 ), - .Q(vsize_counter[5]), - .R(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 )); + \vert_count_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_7 ), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_23 ), + .Q(vert_count_reg[5]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.vsize_counter_reg[6] - (.C(m_axis_mm2s_aclk), - .CE(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 ), - .D(\GEN_LINEBUF_NO_SOF.vsize_counter[6]_i_1_n_0 ), - .Q(vsize_counter[6]), - .R(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 )); + \vert_count_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_7 ), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_22 ), + .Q(vert_count_reg[6]), + .R(SR)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.vsize_counter_reg[7] + \vert_count_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_7 ), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_21 ), + .Q(vert_count_reg[7]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \vert_count_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_7 ), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_28 ), + .Q(vert_count_reg[8]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \vert_count_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_7 ), + .D(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_27 ), + .Q(vert_count_reg[9]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + zero_hsize_err_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(zero_hsize_err0), + .Q(zero_hsize_err), + .R(SR)); + FDRE #( + .INIT(1'b0)) + zero_vsize_err_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(zero_vsize_err0), + .Q(zero_vsize_err), + .R(SR)); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_sof_gen" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_sof_gen + (prmry_in_xored, + scndry_reset2, + s_valid0, + m_axis_mm2s_aclk, + p_in_d1_cdc_from, + out, + p_15_out); + output prmry_in_xored; + input scndry_reset2; + input s_valid0; + input m_axis_mm2s_aclk; + input p_in_d1_cdc_from; + input out; + input p_15_out; + + wire hold_sof; + wire hold_sof_i_1_n_0; + wire m_axis_mm2s_aclk; + wire out; + wire p_15_out; + wire p_in_d1_cdc_from; + wire prmry_in_xored; + wire s_valid; + wire s_valid0; + wire s_valid_d1; + wire scndry_reset2; + + LUT4 #( + .INIT(16'hEF10)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__11 + (.I0(hold_sof), + .I1(s_valid_d1), + .I2(s_valid), + .I3(p_in_d1_cdc_from), + .O(prmry_in_xored)); + LUT5 #( + .INIT(32'h0000AE00)) + hold_sof_i_1 + (.I0(hold_sof), + .I1(s_valid), + .I2(s_valid_d1), + .I3(out), + .I4(p_15_out), + .O(hold_sof_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + hold_sof_reg (.C(m_axis_mm2s_aclk), - .CE(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 ), - .D(\GEN_LINEBUF_NO_SOF.vsize_counter[7]_i_1_n_0 ), - .Q(vsize_counter[7]), - .R(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 )); + .CE(1'b1), + .D(hold_sof_i_1_n_0), + .Q(hold_sof), + .R(1'b0)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.vsize_counter_reg[8] + s_valid_d1_reg (.C(m_axis_mm2s_aclk), - .CE(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 ), - .D(\GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_1_n_0 ), - .Q(vsize_counter[8]), - .R(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 )); + .CE(1'b1), + .D(s_valid), + .Q(s_valid_d1), + .R(scndry_reset2)); FDRE #( .INIT(1'b0)) - \GEN_LINEBUF_NO_SOF.vsize_counter_reg[9] + s_valid_reg (.C(m_axis_mm2s_aclk), - .CE(\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0 ), - .D(\GEN_LINEBUF_NO_SOF.vsize_counter[9]_i_1_n_0 ), - .Q(vsize_counter[9]), - .R(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 )); - CARRY4 minusOp_carry - (.CI(1'b0), - .CO({minusOp_carry_n_0,minusOp_carry_n_1,minusOp_carry_n_2,minusOp_carry_n_3}), - .CYINIT(vsize_counter[0]), - .DI(vsize_counter[4:1]), - .O(minusOp[4:1]), - .S({minusOp_carry_i_1_n_0,minusOp_carry_i_2_n_0,minusOp_carry_i_3_n_0,minusOp_carry_i_4_n_0})); - CARRY4 minusOp_carry__0 - (.CI(minusOp_carry_n_0), - .CO({minusOp_carry__0_n_0,minusOp_carry__0_n_1,minusOp_carry__0_n_2,minusOp_carry__0_n_3}), - .CYINIT(1'b0), - .DI(vsize_counter[8:5]), - .O(minusOp[8:5]), - .S({minusOp_carry__0_i_1_n_0,minusOp_carry__0_i_2_n_0,minusOp_carry__0_i_3_n_0,minusOp_carry__0_i_4_n_0})); - LUT1 #( - .INIT(2'h1)) - minusOp_carry__0_i_1 - (.I0(vsize_counter[8]), - .O(minusOp_carry__0_i_1_n_0)); - LUT1 #( - .INIT(2'h1)) - minusOp_carry__0_i_2 - (.I0(vsize_counter[7]), - .O(minusOp_carry__0_i_2_n_0)); - LUT1 #( - .INIT(2'h1)) - minusOp_carry__0_i_3 - (.I0(vsize_counter[6]), - .O(minusOp_carry__0_i_3_n_0)); - LUT1 #( - .INIT(2'h1)) - minusOp_carry__0_i_4 - (.I0(vsize_counter[5]), - .O(minusOp_carry__0_i_4_n_0)); - CARRY4 minusOp_carry__1 - (.CI(minusOp_carry__0_n_0), - .CO({NLW_minusOp_carry__1_CO_UNCONNECTED[3],minusOp_carry__1_n_1,minusOp_carry__1_n_2,minusOp_carry__1_n_3}), - .CYINIT(1'b0), - .DI({1'b0,vsize_counter[11:9]}), - .O(minusOp[12:9]), - .S({minusOp_carry__1_i_1_n_0,minusOp_carry__1_i_2_n_0,minusOp_carry__1_i_3_n_0,minusOp_carry__1_i_4_n_0})); - LUT1 #( - .INIT(2'h1)) - minusOp_carry__1_i_1 - (.I0(vsize_counter[12]), - .O(minusOp_carry__1_i_1_n_0)); - LUT1 #( - .INIT(2'h1)) - minusOp_carry__1_i_2 - (.I0(vsize_counter[11]), - .O(minusOp_carry__1_i_2_n_0)); - LUT1 #( - .INIT(2'h1)) - minusOp_carry__1_i_3 - (.I0(vsize_counter[10]), - .O(minusOp_carry__1_i_3_n_0)); - LUT1 #( - .INIT(2'h1)) - minusOp_carry__1_i_4 - (.I0(vsize_counter[9]), - .O(minusOp_carry__1_i_4_n_0)); - LUT1 #( - .INIT(2'h1)) - minusOp_carry_i_1 - (.I0(vsize_counter[4]), - .O(minusOp_carry_i_1_n_0)); - LUT1 #( - .INIT(2'h1)) - minusOp_carry_i_2 - (.I0(vsize_counter[3]), - .O(minusOp_carry_i_2_n_0)); - LUT1 #( - .INIT(2'h1)) - minusOp_carry_i_3 - (.I0(vsize_counter[2]), - .O(minusOp_carry_i_3_n_0)); - LUT1 #( - .INIT(2'h1)) - minusOp_carry_i_4 - (.I0(vsize_counter[1]), - .O(minusOp_carry_i_4_n_0)); + .CE(1'b1), + .D(s_valid0), + .Q(s_valid), + .R(scndry_reset2)); endmodule -(* ORIG_REF_NAME = "axi_vdma_mngr" *) -module Arty_Z7_20_axi_vdma_0_0_axi_vdma_mngr - (cmnd_wr, - p_57_out, - p_36_out, - p_44_out, - in0, - p_35_out, - p_49_out, - p_55_out, - \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg , - dma_err, - datamover_idle, - prmtr_update_complete, - p_46_out, - initial_frame, - Q, - p_37_out, - \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 , - p_2_out, - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg , - halted_reg, - dma_decerr_reg, - dma_slverr_reg, - \INFERRED_GEN.cnt_i_reg[1] , - dma_interr_reg, - \sig_addr_cntr_lsh_kh_reg[31] , - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4] , - p_0_in, - m_axi_mm2s_aclk, - p_0_out, +(* ORIG_REF_NAME = "axi_vdma_sof_gen" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_sof_gen_0 + (prmry_in_xored, + prmry_reset2, + s_valid0, + s_axis_s2mm_aclk, + p_in_d1_cdc_from, out, - \INFERRED_GEN.cnt_i_reg[2] , - \INFERRED_GEN.cnt_i_reg[2]_0 , - \INFERRED_GEN.cnt_i_reg[2]_1 , - p_68_out, - p_45_out, - stop_i, - p_23_out, + s2mm_fsync_out_i); + output prmry_in_xored; + input prmry_reset2; + input s_valid0; + input s_axis_s2mm_aclk; + input p_in_d1_cdc_from; + input out; + input s2mm_fsync_out_i; + + wire hold_sof; + wire hold_sof_i_1__0_n_0; + wire out; + wire p_in_d1_cdc_from; + wire prmry_in_xored; + wire prmry_reset2; + wire s2mm_fsync_out_i; + wire s_axis_s2mm_aclk; + wire s_valid; + wire s_valid0; + wire s_valid_d1; + + LUT4 #( + .INIT(16'hEF10)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__12 + (.I0(hold_sof), + .I1(s_valid_d1), + .I2(s_valid), + .I3(p_in_d1_cdc_from), + .O(prmry_in_xored)); + LUT5 #( + .INIT(32'h0000AE00)) + hold_sof_i_1__0 + (.I0(hold_sof), + .I1(s_valid), + .I2(s_valid_d1), + .I3(out), + .I4(s2mm_fsync_out_i), + .O(hold_sof_i_1__0_n_0)); + FDRE #( + .INIT(1'b0)) + hold_sof_reg + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(hold_sof_i_1__0_n_0), + .Q(hold_sof), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + s_valid_d1_reg + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(s_valid), + .Q(s_valid_d1), + .R(prmry_reset2)); + FDRE #( + .INIT(1'b0)) + s_valid_reg + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(s_valid0), + .Q(s_valid), + .R(prmry_reset2)); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_sts_mngr" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_sts_mngr + (datamover_idle, + halted_reg, SR, - E, - \dmacr_i_reg[0] , - prmtr_updt_complete_i_reg, - p_1_out, - p_64_out, - halt_i_reg, - mm2s_halt, - \INFERRED_GEN.cnt_i_reg[2]_2 , - \ptr_ref_i_reg[4] , - mask_fsync_out_i, - ch1_delay_cnt_en, - p_17_out, - ch1_disable_delay2_out, - p_67_out, - dma_decerr_reg_0, - dma_slverr_reg_0, - D, - mm2s_axi2ip_wrce, - dma_interr_reg_0, - \reg_module_vsize_reg[12] , - \reg_module_hsize_reg[15] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] , - \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] , - prmry_resetn_i_reg, - halt_i_reg_0); - output cmnd_wr; - output p_57_out; - output p_36_out; - output p_44_out; - output [0:0]in0; - output p_35_out; - output p_49_out; - output p_55_out; - output \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg ; - output dma_err; + s2mm_dmacr, + m_axi_s2mm_aclk, + halted_set_i0, + sig_halt_cmplt_reg, + s2mm_dmasr, + out); output datamover_idle; - output prmtr_update_complete; - output p_46_out; - output initial_frame; - output [12:0]Q; + output halted_reg; + input [0:0]SR; + input [0:0]s2mm_dmacr; + input m_axi_s2mm_aclk; + input halted_set_i0; + input sig_halt_cmplt_reg; + input [0:0]s2mm_dmasr; + input out; + + wire [0:0]SR; + wire datamover_idle; + wire halted_reg; + wire halted_set_i0; + wire m_axi_s2mm_aclk; + wire out; + wire [0:0]s2mm_dmacr; + wire [0:0]s2mm_dmasr; + wire s2mm_halted_clr; + wire s2mm_halted_set; + wire sig_halt_cmplt_reg; + + LUT4 #( + .INIT(16'hFF4F)) + \I_DMA_REGISTER/halted_i_1__0 + (.I0(s2mm_halted_clr), + .I1(s2mm_dmasr), + .I2(out), + .I3(s2mm_halted_set), + .O(halted_reg)); + FDRE #( + .INIT(1'b0)) + datamover_idle_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_halt_cmplt_reg), + .Q(datamover_idle), + .R(SR)); + FDRE halted_clr_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s2mm_dmacr), + .Q(s2mm_halted_clr), + .R(SR)); + FDRE #( + .INIT(1'b0)) + halted_set_i_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(halted_set_i0), + .Q(s2mm_halted_set), + .R(SR)); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_sts_mngr" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_sts_mngr_42 + (p_37_out, + datamover_idle, + halted_reg, + SR, + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 , + m_axi_mm2s_aclk, + p_71_out, + halted_set_i0, + sig_halt_cmplt_reg, + p_70_out, + mm2s_prmry_resetn); output p_37_out; - output [4:0]\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 ; - output p_2_out; - output \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg ; + output datamover_idle; output halted_reg; - output dma_decerr_reg; - output dma_slverr_reg; - output \INFERRED_GEN.cnt_i_reg[1] ; - output dma_interr_reg; - output [48:0]\sig_addr_cntr_lsh_kh_reg[31] ; - output [4:0]\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4] ; - input p_0_in; + input [0:0]SR; + input \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ; input m_axi_mm2s_aclk; - input p_0_out; - input out; - input \INFERRED_GEN.cnt_i_reg[2] ; - input \INFERRED_GEN.cnt_i_reg[2]_0 ; - input \INFERRED_GEN.cnt_i_reg[2]_1 ; - input [2:0]p_68_out; - input p_45_out; - input stop_i; - input p_23_out; + input [0:0]p_71_out; + input halted_set_i0; + input sig_halt_cmplt_reg; + input p_70_out; + input mm2s_prmry_resetn; + + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ; + wire [0:0]SR; + wire datamover_idle; + wire halted_reg; + wire halted_set_i0; + wire m_axi_mm2s_aclk; + wire mm2s_prmry_resetn; + wire p_27_out; + wire p_28_out; + wire p_37_out; + wire p_70_out; + wire [0:0]p_71_out; + wire sig_halt_cmplt_reg; + + LUT4 #( + .INIT(16'hFF4F)) + \I_DMA_REGISTER/halted_i_1 + (.I0(p_27_out), + .I1(p_70_out), + .I2(mm2s_prmry_resetn), + .I3(p_28_out), + .O(halted_reg)); + FDSE all_idle_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ), + .Q(p_37_out), + .S(SR)); + FDRE #( + .INIT(1'b0)) + datamover_idle_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(sig_halt_cmplt_reg), + .Q(datamover_idle), + .R(SR)); + FDRE halted_clr_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(p_71_out), + .Q(p_27_out), + .R(SR)); + FDRE #( + .INIT(1'b0)) + halted_set_i_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(halted_set_i0), + .Q(p_28_out), + .R(SR)); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_vid_cdc" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_vid_cdc + (p_in_d1_cdc_from, + p_17_out, + p_in_d1_cdc_from_0, + p_15_out, + all_lines_xfred, + mm2s_frame_ptr_out, + SR, + prmry_in_xored, + m_axis_mm2s_aclk, + prmry_resetn_i_reg, + m_axi_mm2s_aclk, + prmry_in_xored_1, + \GENLOCK_FOR_MASTER.frame_ptr_out_reg[2] , + mm2s_frame_ptr_in, + \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4] ); + output p_in_d1_cdc_from; + output p_17_out; + output p_in_d1_cdc_from_0; + output p_15_out; + output all_lines_xfred; + output [5:0]mm2s_frame_ptr_out; input [0:0]SR; - input [0:0]E; - input \dmacr_i_reg[0] ; - input prmtr_updt_complete_i_reg; - input p_1_out; - input p_64_out; - input halt_i_reg; - input mm2s_halt; - input [0:0]\INFERRED_GEN.cnt_i_reg[2]_2 ; - input [4:0]\ptr_ref_i_reg[4] ; - input mask_fsync_out_i; - input ch1_delay_cnt_en; - input p_17_out; - input ch1_disable_delay2_out; - input p_67_out; - input dma_decerr_reg_0; - input dma_slverr_reg_0; - input [0:0]D; - input [0:0]mm2s_axi2ip_wrce; - input dma_interr_reg_0; - input [12:0]\reg_module_vsize_reg[12] ; - input [15:0]\reg_module_hsize_reg[15] ; - input [31:0]\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] ; - input [15:0]\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ; + input prmry_in_xored; + input m_axis_mm2s_aclk; input [0:0]prmry_resetn_i_reg; - input [0:0]halt_i_reg_0; + input m_axi_mm2s_aclk; + input prmry_in_xored_1; + input [2:0]\GENLOCK_FOR_MASTER.frame_ptr_out_reg[2] ; + input [5:0]mm2s_frame_ptr_in; + input \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4] ; - wire [31:16]C; - wire [0:0]D; - wire [0:0]E; - wire \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg ; - wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg ; - wire [4:0]\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4] ; - wire [31:0]\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] ; - wire \INFERRED_GEN.cnt_i_reg[1] ; - wire \INFERRED_GEN.cnt_i_reg[2] ; - wire \INFERRED_GEN.cnt_i_reg[2]_0 ; - wire \INFERRED_GEN.cnt_i_reg[2]_1 ; - wire [0:0]\INFERRED_GEN.cnt_i_reg[2]_2 ; - wire I_CMDSTS_n_1; - wire I_CMDSTS_n_6; - wire I_CMDSTS_n_7; - wire I_SM_n_31; - wire I_SM_n_32; - wire I_SM_n_33; - wire I_SM_n_34; - wire I_SM_n_35; - wire I_SM_n_36; - wire I_SM_n_37; - wire I_SM_n_38; - wire I_SM_n_39; - wire I_SM_n_40; - wire I_SM_n_41; - wire I_SM_n_42; - wire I_SM_n_43; - wire I_SM_n_44; - wire I_SM_n_45; - wire I_SM_n_46; - wire I_SM_n_47; - wire I_SM_n_48; - wire I_SM_n_49; - wire I_SM_n_50; - wire I_SM_n_51; - wire I_SM_n_52; - wire I_SM_n_53; - wire I_SM_n_54; - wire I_SM_n_55; - wire I_SM_n_56; - wire I_SM_n_57; - wire I_SM_n_58; - wire I_SM_n_59; - wire I_SM_n_60; - wire I_SM_n_61; - wire I_SM_n_62; - wire I_SM_n_63; - wire I_SM_n_64; - wire I_SM_n_65; - wire I_SM_n_66; - wire I_SM_n_67; - wire I_SM_n_68; - wire I_SM_n_69; - wire I_SM_n_70; - wire I_SM_n_71; - wire I_SM_n_72; - wire I_SM_n_73; - wire I_SM_n_74; - wire I_SM_n_75; - wire I_SM_n_76; - wire I_SM_n_77; - wire I_SM_n_78; - wire I_SM_n_79; - wire I_SM_n_80; - wire I_SM_n_81; - wire I_SM_n_82; - wire I_SM_n_83; - wire I_SM_n_84; - wire I_SM_n_85; - wire I_SM_n_86; - wire I_SM_n_87; - wire [4:0]\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 ; - wire \MASTER_MODE_FRAME_CNT.frame_number_i[0]_i_1_n_0 ; - wire \MASTER_MODE_FRAME_CNT.frame_number_i[1]_i_1_n_0 ; - wire \MASTER_MODE_FRAME_CNT.frame_number_i[2]_i_1_n_0 ; - wire \MASTER_MODE_FRAME_CNT.frame_number_i[3]_i_1_n_0 ; - wire \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_3_n_0 ; - wire \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_5_n_0 ; - wire \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_6_n_0 ; - wire [15:0]\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ; - wire [12:0]Q; + wire \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4] ; wire [0:0]SR; - wire VIDEO_REG_I_n_17; - wire VIDEO_REG_I_n_18; - wire VIDEO_REG_I_n_36; - wire VIDEO_REG_I_n_37; - wire VIDEO_REG_I_n_38; - wire VIDEO_REG_I_n_39; - wire VIDEO_REG_I_n_40; - wire VIDEO_REG_I_n_41; - wire VIDEO_REG_I_n_42; - wire VIDEO_REG_I_n_43; - wire VIDEO_REG_I_n_44; - wire VIDEO_REG_I_n_45; - wire VIDEO_REG_I_n_46; - wire VIDEO_REG_I_n_47; - wire VIDEO_REG_I_n_48; - wire VIDEO_REG_I_n_49; - wire VIDEO_REG_I_n_50; - wire VIDEO_REG_I_n_51; - wire VIDEO_REG_I_n_52; - wire ch1_delay_cnt_en; - wire ch1_disable_delay2_out; - wire cmnd_wr; - wire [5:0]cmnds_queued_reg; - wire [15:0]crnt_hsize; - wire datamover_idle; - wire [15:0]dm_address_reg; - wire dma_decerr_reg; - wire dma_decerr_reg_0; - wire dma_err; - wire dma_interr_reg; - wire dma_interr_reg_0; - wire dma_slverr_reg; - wire dma_slverr_reg_0; - wire dmacntrl_ns14_out; - wire \dmacr_i_reg[0] ; - wire frame_sync_reg; - wire halt_i_reg; - wire [0:0]halt_i_reg_0; - wire halted_reg; - wire [0:0]in0; - wire initial_frame; - wire initial_frame_i_1_n_0; - wire load_new_addr; + wire all_lines_xfred; + (* async_reg = "true" *) wire [5:0]frame_ptr_in_d1_cdc_tig; + (* async_reg = "true" *) wire [5:0]frame_ptr_in_d2; + (* async_reg = "true" *) wire [5:0]frame_ptr_out_d1_cdc_tig; + (* async_reg = "true" *) wire [5:0]frame_ptr_out_d2; wire m_axi_mm2s_aclk; - wire mask_fsync_out_i; - wire [0:0]mm2s_axi2ip_wrce; - wire mm2s_halt; - wire out; - wire p_0_in; - wire p_0_out; - wire p_0_out_carry__0_n_2; - wire p_0_out_carry__0_n_3; - wire p_0_out_carry__0_n_5; - wire p_0_out_carry__0_n_6; - wire p_0_out_carry__0_n_7; - wire p_0_out_carry_n_0; - wire p_0_out_carry_n_1; - wire p_0_out_carry_n_2; - wire p_0_out_carry_n_3; - wire p_0_out_carry_n_4; - wire p_0_out_carry_n_5; - wire p_0_out_carry_n_6; - wire p_0_out_carry_n_7; - wire p_10_out; + wire m_axis_mm2s_aclk; + wire [5:0]mm2s_frame_ptr_in; + wire [5:0]mm2s_frame_ptr_out; + (* async_reg = "true" *) wire [5:0]othrchnl_frame_ptr_in_d1_cdc_tig; + (* async_reg = "true" *) wire [5:0]othrchnl_frame_ptr_in_d2; + wire p_15_out; wire p_17_out; - wire p_1_out; - wire p_23_out; - wire p_2_out; - wire p_35_out; - wire p_36_out; - wire p_37_out; - wire p_3_in; - wire p_44_out; - wire p_45_out; - wire p_46_out; - wire p_49_out; - wire p_55_out; - wire p_57_out; - wire p_64_out; - wire p_67_out; - wire [2:0]p_68_out; - wire p_6_out__0; + wire [5:0]p_2_in; + wire p_in_d1_cdc_from; + wire p_in_d1_cdc_from_0; + wire prmry_in_xored; + wire prmry_in_xored_1; wire [0:0]prmry_resetn_i_reg; - wire prmtr_update_complete; - wire prmtr_updt_complete_i_reg; - wire [4:0]\ptr_ref_i_reg[4] ; - wire [15:0]\reg_module_hsize_reg[15] ; - wire [12:0]\reg_module_vsize_reg[12] ; - wire [48:0]\sig_addr_cntr_lsh_kh_reg[31] ; - wire stop_i; - wire tstvect_fsync_d1; - wire valid_frame_sync_d1; - wire valid_frame_sync_d2; - wire zero_hsize_err; - wire zero_hsize_err0; - wire zero_vsize_err; - wire zero_vsize_err0; - wire [3:2]NLW_p_0_out_carry__0_CO_UNCONNECTED; - wire [3:3]NLW_p_0_out_carry__0_O_UNCONNECTED; - LUT5 #( - .INIT(32'h00AE0000)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_i_1 - (.I0(p_49_out), - .I1(ch1_delay_cnt_en), - .I2(p_17_out), - .I3(ch1_disable_delay2_out), - .I4(out), - .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg )); - Arty_Z7_20_axi_vdma_0_0_axi_vdma_cmdsts_if I_CMDSTS - (.D({I_SM_n_39,I_SM_n_40,I_SM_n_41,I_SM_n_42,I_SM_n_43,I_SM_n_44,I_SM_n_45,I_SM_n_46,I_SM_n_47,I_SM_n_48,I_SM_n_49,I_SM_n_50,I_SM_n_51,I_SM_n_52,I_SM_n_53,I_SM_n_54,I_SM_n_55,I_SM_n_56,I_SM_n_57,I_SM_n_58,I_SM_n_59,I_SM_n_60,I_SM_n_61,I_SM_n_62,I_SM_n_63,I_SM_n_64,I_SM_n_65,I_SM_n_66,I_SM_n_67,I_SM_n_68,I_SM_n_69,I_SM_n_70,I_SM_n_71,I_SM_n_72,I_SM_n_73,I_SM_n_74,I_SM_n_75,I_SM_n_76,I_SM_n_77,I_SM_n_78,I_SM_n_79,I_SM_n_80,I_SM_n_81,I_SM_n_82,I_SM_n_83,I_SM_n_84,I_SM_n_85,I_SM_n_86,I_SM_n_87}), - .E(E), - .\FSM_sequential_dmacntrl_cs_reg[1] (I_CMDSTS_n_7), - .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from (I_CMDSTS_n_6), - .\GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg (p_55_out), - .\GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg_0 (cmnd_wr), - .\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg (p_46_out), - .\INFERRED_GEN.cnt_i_reg[1] (\INFERRED_GEN.cnt_i_reg[1] ), - .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ), - .\INFERRED_GEN.cnt_i_reg[2]_0 (\INFERRED_GEN.cnt_i_reg[2]_0 ), - .\INFERRED_GEN.cnt_i_reg[2]_1 (\INFERRED_GEN.cnt_i_reg[2]_1 ), - .\INFERRED_GEN.cnt_i_reg[2]_2 (\INFERRED_GEN.cnt_i_reg[2]_2 ), + assign p_2_in[2:0] = \GENLOCK_FOR_MASTER.frame_ptr_out_reg[2] [2:0]; + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized14_37 \GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I + (.\GEN_LINEBUF_NO_SOF.vsize_counter_reg[4] (\GEN_LINEBUF_NO_SOF.vsize_counter_reg[4] ), .SR(SR), - .\cmnds_queued_reg[7] (p_57_out), - .dma_decerr_reg(dma_decerr_reg), - .dma_decerr_reg_0(dma_decerr_reg_0), - .dma_slverr_reg(dma_slverr_reg), - .dma_slverr_reg_0(dma_slverr_reg_0), - .dmacntrl_ns14_out(dmacntrl_ns14_out), - .err_i_reg_0(I_CMDSTS_n_1), - .err_i_reg_1(dma_err), - .frame_sync_reg(frame_sync_reg), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .mm2s_halt(mm2s_halt), - .out(out), - .p_0_in(p_0_in), - .p_3_in(p_3_in), - .p_68_out({p_68_out[2],p_68_out[0]}), - .\sig_addr_cntr_lsh_kh_reg[31] (\sig_addr_cntr_lsh_kh_reg[31] ), - .zero_hsize_err(zero_hsize_err), - .zero_vsize_err(zero_vsize_err)); - Arty_Z7_20_axi_vdma_0_0_axi_vdma_sm I_SM - (.CO(VIDEO_REG_I_n_48), - .D({I_SM_n_39,I_SM_n_40,I_SM_n_41,I_SM_n_42,I_SM_n_43,I_SM_n_44,I_SM_n_45,I_SM_n_46,I_SM_n_47,I_SM_n_48,I_SM_n_49,I_SM_n_50,I_SM_n_51,I_SM_n_52,I_SM_n_53,I_SM_n_54,I_SM_n_55,I_SM_n_56,I_SM_n_57,I_SM_n_58,I_SM_n_59,I_SM_n_60,I_SM_n_61,I_SM_n_62,I_SM_n_63,I_SM_n_64,I_SM_n_65,I_SM_n_66,I_SM_n_67,I_SM_n_68,I_SM_n_69,I_SM_n_70,I_SM_n_71,I_SM_n_72,I_SM_n_73,I_SM_n_74,I_SM_n_75,I_SM_n_76,I_SM_n_77,I_SM_n_78,I_SM_n_79,I_SM_n_80,I_SM_n_81,I_SM_n_82,I_SM_n_83,I_SM_n_84,I_SM_n_85,I_SM_n_86,I_SM_n_87}), - .DI(I_SM_n_31), - .\GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg_0 (\GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] (D), - .\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 (dm_address_reg), - .\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg (p_46_out), - .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2]_2 ), - .O({VIDEO_REG_I_n_36,VIDEO_REG_I_n_37,VIDEO_REG_I_n_38,VIDEO_REG_I_n_39}), - .Q(C), - .S({I_SM_n_32,I_SM_n_33,I_SM_n_34,I_SM_n_35}), - .\cmnds_queued_reg[5]_0 ({p_0_out_carry__0_n_5,p_0_out_carry__0_n_6,p_0_out_carry__0_n_7,p_0_out_carry_n_4,p_0_out_carry_n_5,p_0_out_carry_n_6,p_0_out_carry_n_7}), - .\cmnds_queued_reg[7]_0 (cmnds_queued_reg), - .\cmnds_queued_reg[7]_1 ({I_SM_n_36,I_SM_n_37,I_SM_n_38}), - .dma_err(dma_err), - .dma_interr_reg(dma_interr_reg), - .dma_interr_reg_0(dma_interr_reg_0), - .dmacntrl_ns14_out(dmacntrl_ns14_out), - .err_i_reg(I_CMDSTS_n_6), - .err_i_reg_0(I_CMDSTS_n_7), - .frame_sync_reg(frame_sync_reg), - .halt_i_reg(halt_i_reg), - .halt_i_reg_0(halt_i_reg_0), - .\hsize_vid_reg[15] (crnt_hsize), - .interr_i_reg(I_CMDSTS_n_1), - .load_new_addr(load_new_addr), + .all_lines_xfred(all_lines_xfred), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .mm2s_axi2ip_wrce(mm2s_axi2ip_wrce), - .mm2s_halt(mm2s_halt), - .out(out), - .p_0_in(p_0_in), - .p_0_out(p_0_out), - .p_10_out(p_10_out), - .p_23_out(p_23_out), - .p_37_out(p_37_out), - .p_3_in(p_3_in), - .p_57_out(p_57_out), - .p_68_out({p_68_out[2],p_68_out[0]}), - .s_axis_cmd_tvalid_reg(cmnd_wr), - .s_axis_cmd_tvalid_reg_0(p_55_out), - .\stride_vid_reg[11] ({VIDEO_REG_I_n_44,VIDEO_REG_I_n_45,VIDEO_REG_I_n_46,VIDEO_REG_I_n_47}), - .\stride_vid_reg[15] ({VIDEO_REG_I_n_49,VIDEO_REG_I_n_50,VIDEO_REG_I_n_51,VIDEO_REG_I_n_52}), - .\stride_vid_reg[7] ({VIDEO_REG_I_n_40,VIDEO_REG_I_n_41,VIDEO_REG_I_n_42,VIDEO_REG_I_n_43}), - .tstvect_fsync_d1(tstvect_fsync_d1), - .\vsize_vid_reg[12] (Q), - .zero_hsize_err(zero_hsize_err), - .zero_hsize_err0(zero_hsize_err0), - .zero_vsize_err(zero_vsize_err), - .zero_vsize_err0(zero_vsize_err0)); - Arty_Z7_20_axi_vdma_0_0_axi_vdma_sts_mngr I_STS_MNGR - (.\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg (VIDEO_REG_I_n_17), - .datamover_idle(datamover_idle), - .\dmacr_i_reg[0] (\dmacr_i_reg[0] ), - .halted_reg(halted_reg), + .m_axis_mm2s_aclk(m_axis_mm2s_aclk), + .p_15_out(p_15_out), + .p_in_d1_cdc_from_0(p_in_d1_cdc_from_0), + .prmry_in_xored_1(prmry_in_xored_1), + .prmry_resetn_i_reg(prmry_resetn_i_reg)); + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized12_38 \GEN_CDC_FOR_ASYNC.SOF_CDC_I + (.SR(SR), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .out(out), - .p_0_in(p_0_in), - .p_1_out(p_1_out), - .p_36_out(p_36_out), - .p_37_out(p_37_out), - .p_67_out(p_67_out), - .p_68_out(p_68_out[0])); - FDRE \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[0] + .m_axis_mm2s_aclk(m_axis_mm2s_aclk), + .p_17_out(p_17_out), + .p_in_d1_cdc_from(p_in_d1_cdc_from), + .prmry_in_xored(prmry_in_xored), + .prmry_resetn_i_reg(prmry_resetn_i_reg)); + FDRE \GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[0] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(frame_ptr_out_d2[0]), + .Q(mm2s_frame_ptr_out[0]), + .R(SR)); + FDRE \GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[1] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(frame_ptr_out_d2[1]), + .Q(mm2s_frame_ptr_out[1]), + .R(SR)); + FDRE \GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[2] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(frame_ptr_out_d2[2]), + .Q(mm2s_frame_ptr_out[2]), + .R(SR)); + FDRE \GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[3] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(frame_ptr_out_d2[3]), + .Q(mm2s_frame_ptr_out[3]), + .R(SR)); + FDRE \GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[4] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(frame_ptr_out_d2[4]), + .Q(mm2s_frame_ptr_out[4]), + .R(SR)); + FDRE \GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[5] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(frame_ptr_out_d2[5]), + .Q(mm2s_frame_ptr_out[5]), + .R(SR)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[0] (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [0]), - .Q(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4] [0]), - .R(p_0_in)); - FDRE \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[1] + .D(mm2s_frame_ptr_in[0]), + .Q(frame_ptr_in_d1_cdc_tig[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[1] (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [1]), - .Q(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4] [1]), - .R(p_0_in)); - FDRE \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[2] + .D(mm2s_frame_ptr_in[1]), + .Q(frame_ptr_in_d1_cdc_tig[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[2] (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [2]), - .Q(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4] [2]), - .R(p_0_in)); - FDRE \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[3] + .D(mm2s_frame_ptr_in[2]), + .Q(frame_ptr_in_d1_cdc_tig[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[3] (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [3]), - .Q(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4] [3]), - .R(p_0_in)); - FDRE \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4] + .D(mm2s_frame_ptr_in[3]), + .Q(frame_ptr_in_d1_cdc_tig[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[4] (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [4]), - .Q(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4] [4]), - .R(p_0_in)); - (* SOFT_HLUTNM = "soft_lutpair33" *) - LUT5 #( - .INIT(32'h080808FB)) - \MASTER_MODE_FRAME_CNT.frame_number_i[0]_i_1 - (.I0(\ptr_ref_i_reg[4] [0]), - .I1(valid_frame_sync_d2), - .I2(p_68_out[1]), - .I3(p_6_out__0), - .I4(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [0]), - .O(\MASTER_MODE_FRAME_CNT.frame_number_i[0]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0808080808FBFB08)) - \MASTER_MODE_FRAME_CNT.frame_number_i[1]_i_1 - (.I0(\ptr_ref_i_reg[4] [1]), - .I1(valid_frame_sync_d2), - .I2(p_68_out[1]), - .I3(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [1]), - .I4(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [0]), - .I5(p_6_out__0), - .O(\MASTER_MODE_FRAME_CNT.frame_number_i[1]_i_1_n_0 )); - LUT6 #( - .INIT(64'h888888888BB8B8B8)) - \MASTER_MODE_FRAME_CNT.frame_number_i[2]_i_1 - (.I0(\ptr_ref_i_reg[4] [2]), - .I1(\MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_5_n_0 ), - .I2(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [2]), - .I3(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [1]), - .I4(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [0]), - .I5(p_6_out__0), - .O(\MASTER_MODE_FRAME_CNT.frame_number_i[2]_i_1_n_0 )); - LUT6 #( - .INIT(64'h0808080808FBFB08)) - \MASTER_MODE_FRAME_CNT.frame_number_i[3]_i_1 - (.I0(\ptr_ref_i_reg[4] [3]), - .I1(valid_frame_sync_d2), - .I2(p_68_out[1]), - .I3(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [3]), - .I4(\MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_6_n_0 ), - .I5(p_6_out__0), - .O(\MASTER_MODE_FRAME_CNT.frame_number_i[3]_i_1_n_0 )); - LUT6 #( - .INIT(64'h888888888BB8B8B8)) - \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_3 - (.I0(\ptr_ref_i_reg[4] [4]), - .I1(\MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_5_n_0 ), - .I2(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [4]), - .I3(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [3]), - .I4(\MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_6_n_0 ), - .I5(p_6_out__0), - .O(\MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_3_n_0 )); - LUT6 #( - .INIT(64'h0000000000000002)) - \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_4 - (.I0(valid_frame_sync_d2), - .I1(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [3]), - .I2(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [0]), - .I3(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [1]), - .I4(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [2]), - .I5(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [4]), - .O(p_6_out__0)); - (* SOFT_HLUTNM = "soft_lutpair33" *) - LUT2 #( - .INIT(4'h2)) - \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_5 - (.I0(valid_frame_sync_d2), - .I1(p_68_out[1]), - .O(\MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_5_n_0 )); - LUT3 #( - .INIT(8'h80)) - \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_6 - (.I0(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [2]), - .I1(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [0]), - .I2(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [1]), - .O(\MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_6_n_0 )); + .D(mm2s_frame_ptr_in[4]), + .Q(frame_ptr_in_d1_cdc_tig[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \MASTER_MODE_FRAME_CNT.frame_number_i_reg[0] + \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[5] (.C(m_axi_mm2s_aclk), - .CE(VIDEO_REG_I_n_18), - .D(\MASTER_MODE_FRAME_CNT.frame_number_i[0]_i_1_n_0 ), - .Q(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [0]), - .R(prmry_resetn_i_reg)); + .CE(1'b1), + .D(mm2s_frame_ptr_in[5]), + .Q(frame_ptr_in_d1_cdc_tig[5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] + \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[0] (.C(m_axi_mm2s_aclk), - .CE(VIDEO_REG_I_n_18), - .D(\MASTER_MODE_FRAME_CNT.frame_number_i[1]_i_1_n_0 ), - .Q(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [1]), - .R(prmry_resetn_i_reg)); + .CE(1'b1), + .D(frame_ptr_in_d1_cdc_tig[0]), + .Q(frame_ptr_in_d2[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(frame_ptr_in_d1_cdc_tig[1]), + .Q(frame_ptr_in_d2[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(frame_ptr_in_d1_cdc_tig[2]), + .Q(frame_ptr_in_d2[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(frame_ptr_in_d1_cdc_tig[3]), + .Q(frame_ptr_in_d2[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(frame_ptr_in_d1_cdc_tig[4]), + .Q(frame_ptr_in_d2[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(frame_ptr_in_d1_cdc_tig[5]), + .Q(frame_ptr_in_d2[5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[0] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(p_2_in[0]), + .Q(frame_ptr_out_d1_cdc_tig[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[1] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(p_2_in[1]), + .Q(frame_ptr_out_d1_cdc_tig[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(p_2_in[2]), + .Q(frame_ptr_out_d1_cdc_tig[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[3] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(p_2_in[3]), + .Q(frame_ptr_out_d1_cdc_tig[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[4] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(p_2_in[4]), + .Q(frame_ptr_out_d1_cdc_tig[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \MASTER_MODE_FRAME_CNT.frame_number_i_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(VIDEO_REG_I_n_18), - .D(\MASTER_MODE_FRAME_CNT.frame_number_i[2]_i_1_n_0 ), - .Q(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [2]), - .R(prmry_resetn_i_reg)); + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[5] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(p_2_in[5]), + .Q(frame_ptr_out_d1_cdc_tig[5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \MASTER_MODE_FRAME_CNT.frame_number_i_reg[3] - (.C(m_axi_mm2s_aclk), - .CE(VIDEO_REG_I_n_18), - .D(\MASTER_MODE_FRAME_CNT.frame_number_i[3]_i_1_n_0 ), - .Q(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [3]), - .R(prmry_resetn_i_reg)); + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[0] + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(frame_ptr_out_d1_cdc_tig[0]), + .Q(frame_ptr_out_d2[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4] - (.C(m_axi_mm2s_aclk), - .CE(VIDEO_REG_I_n_18), - .D(\MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_3_n_0 ), - .Q(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 [4]), - .R(prmry_resetn_i_reg)); - FDRE \MASTER_MODE_FRAME_CNT.tstvect_fsync_reg - (.C(m_axi_mm2s_aclk), + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[1] + (.C(m_axis_mm2s_aclk), .CE(1'b1), - .D(p_10_out), - .Q(p_49_out), - .R(p_0_in)); + .D(frame_ptr_out_d1_cdc_tig[1]), + .Q(frame_ptr_out_d2[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \MASTER_MODE_FRAME_CNT.valid_frame_sync_d1_reg - (.C(m_axi_mm2s_aclk), + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[2] + (.C(m_axis_mm2s_aclk), .CE(1'b1), - .D(p_45_out), - .Q(valid_frame_sync_d1), - .R(p_0_in)); + .D(frame_ptr_out_d1_cdc_tig[2]), + .Q(frame_ptr_out_d2[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \MASTER_MODE_FRAME_CNT.valid_frame_sync_d2_reg - (.C(m_axi_mm2s_aclk), + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[3] + (.C(m_axis_mm2s_aclk), .CE(1'b1), - .D(valid_frame_sync_d1), - .Q(valid_frame_sync_d2), - .R(p_0_in)); - Arty_Z7_20_axi_vdma_0_0_axi_vdma_genlock_mngr VIDEO_GENLOCK_I - (.Q(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0 ), - .in0(in0), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .out(out), - .p_0_in(p_0_in), - .p_44_out(p_44_out), - .p_67_out(p_67_out), - .p_68_out(p_68_out[1]), - .valid_frame_sync_d2(valid_frame_sync_d2)); - Arty_Z7_20_axi_vdma_0_0_axi_vdma_vidreg_module VIDEO_REG_I - (.CO(VIDEO_REG_I_n_48), - .E(VIDEO_REG_I_n_18), - .\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] (crnt_hsize), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] (\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] ), - .\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] (\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ), - .O({VIDEO_REG_I_n_36,VIDEO_REG_I_n_37,VIDEO_REG_I_n_38,VIDEO_REG_I_n_39}), - .Q(Q), - .all_idle_reg(VIDEO_REG_I_n_17), - .\dm_address_reg[11] ({VIDEO_REG_I_n_44,VIDEO_REG_I_n_45,VIDEO_REG_I_n_46,VIDEO_REG_I_n_47}), - .\dm_address_reg[15] ({VIDEO_REG_I_n_49,VIDEO_REG_I_n_50,VIDEO_REG_I_n_51,VIDEO_REG_I_n_52}), - .\dm_address_reg[15]_0 (dm_address_reg), - .\dm_address_reg[31] (C), - .\dm_address_reg[7] ({VIDEO_REG_I_n_40,VIDEO_REG_I_n_41,VIDEO_REG_I_n_42,VIDEO_REG_I_n_43}), - .load_new_addr(load_new_addr), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .mask_fsync_out_i(mask_fsync_out_i), - .out(out), - .p_0_in(p_0_in), - .p_1_out(p_1_out), - .p_23_out(p_23_out), - .p_2_out(p_2_out), - .p_37_out(p_37_out), - .p_64_out(p_64_out), - .p_67_out(p_67_out), - .p_68_out(p_68_out[1]), - .p_6_out__0(p_6_out__0), - .prmtr_updt_complete_i_reg(prmtr_updt_complete_i_reg), - .\reg_module_hsize_reg[15] (\reg_module_hsize_reg[15] ), - .\reg_module_vsize_reg[12] (\reg_module_vsize_reg[12] ), - .\stride_vid_reg[0] (prmtr_update_complete), - .\stride_vid_reg[0]_0 (p_46_out), - .tstvect_fsync_d1(tstvect_fsync_d1), - .valid_frame_sync_d2(valid_frame_sync_d2), - .zero_hsize_err0(zero_hsize_err0), - .zero_vsize_err0(zero_vsize_err0)); - LUT4 #( - .INIT(16'h00E0)) - initial_frame_i_1 - (.I0(initial_frame), - .I1(p_23_out), - .I2(out), - .I3(p_67_out), - .O(initial_frame_i_1_n_0)); + .D(frame_ptr_out_d1_cdc_tig[3]), + .Q(frame_ptr_out_d2[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - initial_frame_reg - (.C(m_axi_mm2s_aclk), + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[4] + (.C(m_axis_mm2s_aclk), .CE(1'b1), - .D(initial_frame_i_1_n_0), - .Q(initial_frame), + .D(frame_ptr_out_d1_cdc_tig[4]), + .Q(frame_ptr_out_d2[4]), .R(1'b0)); - (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) - CARRY4 p_0_out_carry - (.CI(1'b0), - .CO({p_0_out_carry_n_0,p_0_out_carry_n_1,p_0_out_carry_n_2,p_0_out_carry_n_3}), - .CYINIT(cmnds_queued_reg[0]), - .DI({cmnds_queued_reg[3:1],I_SM_n_31}), - .O({p_0_out_carry_n_4,p_0_out_carry_n_5,p_0_out_carry_n_6,p_0_out_carry_n_7}), - .S({I_SM_n_32,I_SM_n_33,I_SM_n_34,I_SM_n_35})); - (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) - CARRY4 p_0_out_carry__0 - (.CI(p_0_out_carry_n_0), - .CO({NLW_p_0_out_carry__0_CO_UNCONNECTED[3:2],p_0_out_carry__0_n_2,p_0_out_carry__0_n_3}), - .CYINIT(1'b0), - .DI({1'b0,1'b0,cmnds_queued_reg[5:4]}), - .O({NLW_p_0_out_carry__0_O_UNCONNECTED[3],p_0_out_carry__0_n_5,p_0_out_carry__0_n_6,p_0_out_carry__0_n_7}), - .S({1'b0,I_SM_n_36,I_SM_n_37,I_SM_n_38})); - FDRE stop_reg - (.C(m_axi_mm2s_aclk), + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[5] + (.C(m_axis_mm2s_aclk), .CE(1'b1), - .D(stop_i), - .Q(p_35_out), - .R(p_0_in)); + .D(frame_ptr_out_d1_cdc_tig[5]), + .Q(frame_ptr_out_d2[5]), + .R(1'b0)); + LUT1 #( + .INIT(2'h2)) + i_0 + (.I0(1'b0), + .O(p_2_in[5])); + LUT1 #( + .INIT(2'h2)) + i_1 + (.I0(1'b0), + .O(p_2_in[4])); + LUT1 #( + .INIT(2'h2)) + i_10 + (.I0(1'b0), + .O(othrchnl_frame_ptr_in_d2[4])); + LUT1 #( + .INIT(2'h2)) + i_11 + (.I0(1'b0), + .O(othrchnl_frame_ptr_in_d2[3])); + LUT1 #( + .INIT(2'h2)) + i_12 + (.I0(1'b0), + .O(othrchnl_frame_ptr_in_d2[2])); + LUT1 #( + .INIT(2'h2)) + i_13 + (.I0(1'b0), + .O(othrchnl_frame_ptr_in_d2[1])); + LUT1 #( + .INIT(2'h2)) + i_14 + (.I0(1'b0), + .O(othrchnl_frame_ptr_in_d2[0])); + LUT1 #( + .INIT(2'h2)) + i_2 + (.I0(1'b0), + .O(p_2_in[3])); + LUT1 #( + .INIT(2'h2)) + i_3 + (.I0(1'b0), + .O(othrchnl_frame_ptr_in_d1_cdc_tig[5])); + LUT1 #( + .INIT(2'h2)) + i_4 + (.I0(1'b0), + .O(othrchnl_frame_ptr_in_d1_cdc_tig[4])); + LUT1 #( + .INIT(2'h2)) + i_5 + (.I0(1'b0), + .O(othrchnl_frame_ptr_in_d1_cdc_tig[3])); + LUT1 #( + .INIT(2'h2)) + i_6 + (.I0(1'b0), + .O(othrchnl_frame_ptr_in_d1_cdc_tig[2])); + LUT1 #( + .INIT(2'h2)) + i_7 + (.I0(1'b0), + .O(othrchnl_frame_ptr_in_d1_cdc_tig[1])); + LUT1 #( + .INIT(2'h2)) + i_8 + (.I0(1'b0), + .O(othrchnl_frame_ptr_in_d1_cdc_tig[0])); + LUT1 #( + .INIT(2'h2)) + i_9 + (.I0(1'b0), + .O(othrchnl_frame_ptr_in_d2[5])); endmodule -(* ORIG_REF_NAME = "axi_vdma_reg_if" *) -module Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_if - (D, - out, - mm2s_introut, - s_axi_lite_awready, - s_axi_lite_wready, - s_axi_lite_arready, - s_axi_lite_bvalid, - s_axi_lite_rvalid, - \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg , - mm2s_axi2ip_wrce, - \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg , - \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] , - in0, - prmtr_updt_complete_i_reg, - ioc_irq_reg, - dly_irq_reg, - s_axi_lite_rdata, - SR, - s_axi_lite_aclk, +(* ORIG_REF_NAME = "axi_vdma_vid_cdc" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_vid_cdc_1 + (p_in_d1_cdc_from, + s2mm_packet_sof, + s2mm_cdc2dmac_fsync, + p_in_d1_cdc_from_0, + s2mm_fsync_out_i, + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[0] , + prmry_in_xored, + s2mm_valid_frame_sync_cmb, + E, + s2mm_frame_ptr_out, + \frame_ptr_out_reg[2] , prmry_reset2, - m_axi_mm2s_aclk, - p_75_out, + prmry_in_xored_1, + s_axis_s2mm_aclk, + SR, + m_axi_s2mm_aclk, + prmry_in_xored_2, + \DYNAMIC_GENLOCK_FOR_MASTER.frame_ptr_out_reg[2] , + s2mm_frame_ptr_in, + s2mm_fsync_core, + reset_counts, + irqdelay_wren_i, + p_in_d1_cdc_from_3, + s2mm_valid_video_prmtrs, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] , Q, - \MM2S_ERR_FOR_IRQ.frm_store_i_reg[4] , - s_axi_lite_wvalid, - s_axi_lite_awvalid, - s_axi_lite_arvalid, - different_delay, - different_thresh, - prmry_resetn_i_reg, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[0] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[15] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[14] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[13] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[12] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[6] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[5] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[4] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[2] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[1] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[3] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[7] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[8] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[9] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[10] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[11] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] , - s_axi_lite_resetn, - s_axi_lite_bready, - s_axi_lite_rready, - p_68_out, - p_67_out, - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7] , - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] , - err_irq_reg, - dly_irq_reg_0, - ioc_irq_reg_0, - dma_decerr_reg, - dma_slverr_reg, - dma_interr_reg, - mm2s_ioc_irq_set, - mm2s_dly_irq_set, - s_axi_lite_araddr, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5] , - s_axi_lite_wdata, - s_axi_lite_awaddr, - \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4] ); - output [31:0]D; - output [1:0]out; - output mm2s_introut; - output s_axi_lite_awready; - output s_axi_lite_wready; - output s_axi_lite_arready; - output s_axi_lite_bvalid; - output s_axi_lite_rvalid; - output \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg ; - output [6:0]mm2s_axi2ip_wrce; - output \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg ; - output [0:0]\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] ; - output [31:0]in0; - output prmtr_updt_complete_i_reg; - output ioc_irq_reg; - output dly_irq_reg; - output [31:0]s_axi_lite_rdata; - input [0:0]SR; - input s_axi_lite_aclk; + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out , + M_Last); + output p_in_d1_cdc_from; + output s2mm_packet_sof; + output s2mm_cdc2dmac_fsync; + output p_in_d1_cdc_from_0; + output s2mm_fsync_out_i; + output \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[0] ; + output prmry_in_xored; + output s2mm_valid_frame_sync_cmb; + output [0:0]E; + output [5:0]s2mm_frame_ptr_out; + output [2:0]\frame_ptr_out_reg[2] ; input prmry_reset2; - input m_axi_mm2s_aclk; - input p_75_out; - input [4:0]Q; - input [4:0]\MM2S_ERR_FOR_IRQ.frm_store_i_reg[4] ; - input s_axi_lite_wvalid; - input s_axi_lite_awvalid; - input s_axi_lite_arvalid; - input different_delay; - input different_thresh; - input prmry_resetn_i_reg; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[0] ; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[15] ; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[14] ; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[13] ; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[12] ; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[6] ; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[5] ; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[4] ; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[2] ; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[1] ; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[3] ; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[7] ; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[8] ; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[9] ; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[10] ; - input \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[11] ; - input [15:0]\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] ; - input s_axi_lite_resetn; - input s_axi_lite_bready; - input s_axi_lite_rready; - input [25:0]p_68_out; - input p_67_out; - input [7:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7] ; - input [7:0]\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] ; - input err_irq_reg; - input dly_irq_reg_0; - input ioc_irq_reg_0; - input dma_decerr_reg; - input dma_slverr_reg; - input dma_interr_reg; - input mm2s_ioc_irq_set; - input mm2s_dly_irq_set; - input [5:0]s_axi_lite_araddr; - input [31:0]\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5] ; - input [31:0]s_axi_lite_wdata; - input [5:0]s_axi_lite_awaddr; - input [4:0]\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4] ; + input prmry_in_xored_1; + input s_axis_s2mm_aclk; + input [0:0]SR; + input m_axi_s2mm_aclk; + input prmry_in_xored_2; + input [2:0]\DYNAMIC_GENLOCK_FOR_MASTER.frame_ptr_out_reg[2] ; + input [5:0]s2mm_frame_ptr_in; + input s2mm_fsync_core; + input reset_counts; + input irqdelay_wren_i; + input p_in_d1_cdc_from_3; + input s2mm_valid_video_prmtrs; + input \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ; + input [0:0]Q; + input \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ; + input M_Last; - wire [31:0]D; - wire \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg ; - wire [0:0]\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] ; - wire \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg ; - wire [7:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7] ; - wire [7:0]\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] ; - wire [31:0]\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[0] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[10] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[11] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[12] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[13] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[14] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[15] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[1] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[2] ; - wire [15:0]\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[3] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[4] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[5] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[6] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[7] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[8] ; - wire \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[9] ; - wire [4:0]\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4] ; - wire [4:0]\MM2S_ERR_FOR_IRQ.frm_store_i_reg[4] ; - wire [4:0]Q; + wire [0:0]E; + wire \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[0] ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ; + wire M_Last; + wire [0:0]Q; wire [0:0]SR; - wire different_delay; - wire different_thresh; - wire dly_irq_reg; - wire dly_irq_reg_0; - wire dma_decerr_reg; - wire dma_interr_reg; - wire dma_slverr_reg; - wire err_irq_reg; - wire [31:0]in0; - wire ioc_irq_reg; - wire ioc_irq_reg_0; - wire m_axi_mm2s_aclk; - wire [6:0]mm2s_axi2ip_wrce; - (* async_reg = "true" *) wire [4:0]mm2s_chnl_current_frame_cdc_tig; - wire mm2s_dly_irq_set; - (* async_reg = "true" *) wire [4:0]mm2s_genlock_pair_frame_cdc_tig; - wire mm2s_introut; - wire mm2s_ioc_irq_set; - (* async_reg = "true" *) wire [4:0]mm2s_ip2axi_frame_ptr_ref_cdc_tig; - (* async_reg = "true" *) wire [4:0]mm2s_ip2axi_frame_store_cdc_tig; - wire [1:0]out; - wire p_67_out; - wire [25:0]p_68_out; - wire p_75_out; + (* async_reg = "true" *) wire [5:0]frame_ptr_in_d1_cdc_tig; + (* async_reg = "true" *) wire [5:0]frame_ptr_in_d2; + (* async_reg = "true" *) wire [5:0]frame_ptr_out_d1_cdc_tig; + (* async_reg = "true" *) wire [5:0]frame_ptr_out_d2; + wire [2:0]\frame_ptr_out_reg[2] ; + wire irqdelay_wren_i; + wire m_axi_s2mm_aclk; + (* async_reg = "true" *) wire [5:0]othrchnl_frame_ptr_in_d1_cdc_tig; + (* async_reg = "true" *) wire [5:0]othrchnl_frame_ptr_in_d2; + wire [5:0]p_2_in; + wire p_in_d1_cdc_from; + wire p_in_d1_cdc_from_0; + wire p_in_d1_cdc_from_3; + wire prmry_in_xored; + wire prmry_in_xored_1; + wire prmry_in_xored_2; wire prmry_reset2; - wire prmry_resetn_i_reg; - wire prmtr_updt_complete_i_reg; - (* async_reg = "true" *) wire [12:0]s2mm_capture_dm_done_vsize_counter_cdc_tig; - (* async_reg = "true" *) wire [15:0]s2mm_capture_hsize_at_uf_err_cdc_tig; - (* async_reg = "true" *) wire [4:0]s2mm_chnl_current_frame_cdc_tig; - (* async_reg = "true" *) wire [4:0]s2mm_genlock_pair_frame_cdc_tig; - (* async_reg = "true" *) wire [4:0]s2mm_ip2axi_frame_ptr_ref_cdc_tig; - (* async_reg = "true" *) wire [4:0]s2mm_ip2axi_frame_store_cdc_tig; - wire s_axi_lite_aclk; - wire [5:0]s_axi_lite_araddr; - wire s_axi_lite_arready; - wire s_axi_lite_arvalid; - wire [5:0]s_axi_lite_awaddr; - wire s_axi_lite_awready; - wire s_axi_lite_awvalid; - wire s_axi_lite_bready; - wire s_axi_lite_bvalid; - wire [31:0]s_axi_lite_rdata; - wire s_axi_lite_resetn; - wire s_axi_lite_rready; - wire s_axi_lite_rvalid; - wire [31:0]s_axi_lite_wdata; - wire s_axi_lite_wready; - wire s_axi_lite_wvalid; + wire reset_counts; + wire s2mm_cdc2dmac_fsync; + wire [5:0]s2mm_frame_ptr_in; + wire [5:0]s2mm_frame_ptr_out; + wire s2mm_fsync_core; + wire s2mm_fsync_out_i; + wire s2mm_packet_sof; + wire s2mm_valid_frame_sync_cmb; + wire s2mm_valid_video_prmtrs; + wire s_axis_s2mm_aclk; + wire s_fsync_d1; + wire s_fsync_d2; - Arty_Z7_20_axi_vdma_0_0_axi_vdma_lite_if \GEN_AXI_LITE_IF.AXI_LITE_IF_I - (.D(D), - .\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg (\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg ), - .\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[16] (mm2s_axi2ip_wrce[0]), - .\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] (\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] ), - .\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg (\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg ), - .\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7] (\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7] ), - .\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] (\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0 (\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5] ), - .\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] (mm2s_ip2axi_frame_ptr_ref_cdc_tig), - .\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] (mm2s_ip2axi_frame_store_cdc_tig), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[0] (\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[0] ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[10] (\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[10] ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[11] (\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[11] ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[12] (\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[12] ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[13] (\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[13] ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[14] (\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[14] ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[15] (\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[15] ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[1] (\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[1] ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[2] (\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[2] ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] (\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[3] (\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[3] ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[4] (\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[4] ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[5] (\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[5] ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[6] (\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[6] ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[7] (\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[7] ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[8] (\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[8] ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[9] (\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[9] ), + assign p_2_in[2:0] = \DYNAMIC_GENLOCK_FOR_MASTER.frame_ptr_out_reg[2] [2:0]; + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized13 \GEN_CDC_FOR_ASYNC.FSYNC_IN_CDC_I + (.SR(SR), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .prmry_reset2(prmry_reset2), + .s2mm_cdc2dmac_fsync(s2mm_cdc2dmac_fsync), + .s2mm_valid_frame_sync_cmb(s2mm_valid_frame_sync_cmb), + .s2mm_valid_video_prmtrs(s2mm_valid_video_prmtrs), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk), + .s_fsync_d1(s_fsync_d1), + .s_fsync_d2(s_fsync_d2)); + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized14 \GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I + (.E(E), + .\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out_0 (\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ), + .M_Last(M_Last), + .Q(Q), .SR(SR), - .different_delay(different_delay), - .different_thresh(different_thresh), - .dly_irq_reg(dly_irq_reg), - .dly_irq_reg_0(dly_irq_reg_0), - .dma_decerr_reg(dma_decerr_reg), - .dma_interr_reg(dma_interr_reg), - .dma_slverr_reg(dma_slverr_reg), - .err_irq_reg(err_irq_reg), - .in0(in0), - .ioc_irq_reg(ioc_irq_reg), - .ioc_irq_reg_0(ioc_irq_reg_0), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .mm2s_axi2ip_wrce(mm2s_axi2ip_wrce[6:1]), - .mm2s_dly_irq_set(mm2s_dly_irq_set), - .mm2s_ioc_irq_set(mm2s_ioc_irq_set), - .out(out), - .p_67_out(p_67_out), - .p_68_out(p_68_out), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .p_in_d1_cdc_from_0(p_in_d1_cdc_from_0), + .p_in_d1_cdc_from_3(p_in_d1_cdc_from_3), + .prmry_in_xored(prmry_in_xored), + .prmry_in_xored_2(prmry_in_xored_2), .prmry_reset2(prmry_reset2), - .prmry_resetn_i_reg(prmry_resetn_i_reg), - .prmtr_updt_complete_i_reg(prmtr_updt_complete_i_reg), - .s_axi_lite_aclk(s_axi_lite_aclk), - .s_axi_lite_araddr(s_axi_lite_araddr), - .s_axi_lite_arready(s_axi_lite_arready), - .s_axi_lite_arvalid(s_axi_lite_arvalid), - .s_axi_lite_awaddr(s_axi_lite_awaddr), - .s_axi_lite_awready(s_axi_lite_awready), - .s_axi_lite_awvalid(s_axi_lite_awvalid), - .s_axi_lite_bready(s_axi_lite_bready), - .s_axi_lite_bvalid(s_axi_lite_bvalid), - .s_axi_lite_rdata(s_axi_lite_rdata), - .s_axi_lite_resetn(s_axi_lite_resetn), - .s_axi_lite_rready(s_axi_lite_rready), - .s_axi_lite_rvalid(s_axi_lite_rvalid), - .s_axi_lite_wdata(s_axi_lite_wdata), - .s_axi_lite_wready(s_axi_lite_wready), - .s_axi_lite_wvalid(s_axi_lite_wvalid)); - Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized7 \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.MM2S_INTRPT_CROSSING_I - (.SR(SR), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .mm2s_introut(mm2s_introut), - .p_75_out(p_75_out), + .s2mm_fsync_out_i(s2mm_fsync_out_i), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk)); + Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized12 \GEN_CDC_FOR_ASYNC.SOF_CDC_I + (.\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[0] (\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[0] ), + .SR(SR), + .irqdelay_wren_i(irqdelay_wren_i), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .p_in_d1_cdc_from(p_in_d1_cdc_from), + .prmry_in_xored_1(prmry_in_xored_1), .prmry_reset2(prmry_reset2), - .s_axi_lite_aclk(s_axi_lite_aclk)); + .reset_counts(reset_counts), + .s2mm_cdc2dmac_fsync(s2mm_cdc2dmac_fsync), + .s2mm_packet_sof(s2mm_packet_sof), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk)); + FDRE \GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(frame_ptr_in_d2[0]), + .Q(\frame_ptr_out_reg[2] [0]), + .R(SR)); + FDRE \GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(frame_ptr_in_d2[1]), + .Q(\frame_ptr_out_reg[2] [1]), + .R(SR)); + FDRE \GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(frame_ptr_in_d2[2]), + .Q(\frame_ptr_out_reg[2] [2]), + .R(SR)); + FDRE \GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[0] + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(frame_ptr_out_d2[0]), + .Q(s2mm_frame_ptr_out[0]), + .R(prmry_reset2)); + FDRE \GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[1] + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(frame_ptr_out_d2[1]), + .Q(s2mm_frame_ptr_out[1]), + .R(prmry_reset2)); + FDRE \GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[2] + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(frame_ptr_out_d2[2]), + .Q(s2mm_frame_ptr_out[2]), + .R(prmry_reset2)); + FDRE \GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[3] + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(frame_ptr_out_d2[3]), + .Q(s2mm_frame_ptr_out[3]), + .R(prmry_reset2)); + FDRE \GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[4] + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(frame_ptr_out_d2[4]), + .Q(s2mm_frame_ptr_out[4]), + .R(prmry_reset2)); + FDRE \GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[5] + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(frame_ptr_out_d2[5]), + .Q(s2mm_frame_ptr_out[5]), + .R(prmry_reset2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[0] - (.C(s_axi_lite_aclk), + \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[0] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4] [0]), - .Q(mm2s_chnl_current_frame_cdc_tig[0]), + .D(s2mm_frame_ptr_in[0]), + .Q(frame_ptr_in_d1_cdc_tig[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[1] - (.C(s_axi_lite_aclk), + \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[1] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4] [1]), - .Q(mm2s_chnl_current_frame_cdc_tig[1]), + .D(s2mm_frame_ptr_in[1]), + .Q(frame_ptr_in_d1_cdc_tig[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[2] - (.C(s_axi_lite_aclk), + \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[2] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4] [2]), - .Q(mm2s_chnl_current_frame_cdc_tig[2]), + .D(s2mm_frame_ptr_in[2]), + .Q(frame_ptr_in_d1_cdc_tig[2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[3] - (.C(s_axi_lite_aclk), + \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[3] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4] [3]), - .Q(mm2s_chnl_current_frame_cdc_tig[3]), + .D(s2mm_frame_ptr_in[3]), + .Q(frame_ptr_in_d1_cdc_tig[3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4] - (.C(s_axi_lite_aclk), + \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s2mm_frame_ptr_in[4]), + .Q(frame_ptr_in_d1_cdc_tig[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s2mm_frame_ptr_in[5]), + .Q(frame_ptr_in_d1_cdc_tig[5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(frame_ptr_in_d1_cdc_tig[0]), + .Q(frame_ptr_in_d2[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(frame_ptr_in_d1_cdc_tig[1]), + .Q(frame_ptr_in_d2[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[2] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4] [4]), - .Q(mm2s_chnl_current_frame_cdc_tig[4]), + .D(frame_ptr_in_d1_cdc_tig[2]), + .Q(frame_ptr_in_d2[2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[0] - (.C(s_axi_lite_aclk), + \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[3] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(1'b0), - .Q(mm2s_genlock_pair_frame_cdc_tig[0]), + .D(frame_ptr_in_d1_cdc_tig[3]), + .Q(frame_ptr_in_d2[3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[1] - (.C(s_axi_lite_aclk), + \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[4] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(1'b0), - .Q(mm2s_genlock_pair_frame_cdc_tig[1]), + .D(frame_ptr_in_d1_cdc_tig[4]), + .Q(frame_ptr_in_d2[4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[2] - (.C(s_axi_lite_aclk), + \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[5] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(1'b0), - .Q(mm2s_genlock_pair_frame_cdc_tig[2]), + .D(frame_ptr_in_d1_cdc_tig[5]), + .Q(frame_ptr_in_d2[5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[3] - (.C(s_axi_lite_aclk), + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[0] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(1'b0), - .Q(mm2s_genlock_pair_frame_cdc_tig[3]), + .D(p_2_in[0]), + .Q(frame_ptr_out_d1_cdc_tig[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[4] - (.C(s_axi_lite_aclk), + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[1] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(1'b0), - .Q(mm2s_genlock_pair_frame_cdc_tig[4]), + .D(p_2_in[1]), + .Q(frame_ptr_out_d1_cdc_tig[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[0] - (.C(s_axi_lite_aclk), + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(Q[0]), - .Q(mm2s_ip2axi_frame_ptr_ref_cdc_tig[0]), + .D(p_2_in[2]), + .Q(frame_ptr_out_d1_cdc_tig[2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[1] - (.C(s_axi_lite_aclk), + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[3] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(Q[1]), - .Q(mm2s_ip2axi_frame_ptr_ref_cdc_tig[1]), + .D(p_2_in[3]), + .Q(frame_ptr_out_d1_cdc_tig[3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[2] - (.C(s_axi_lite_aclk), + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[4] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(Q[2]), - .Q(mm2s_ip2axi_frame_ptr_ref_cdc_tig[2]), + .D(p_2_in[4]), + .Q(frame_ptr_out_d1_cdc_tig[4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[3] - (.C(s_axi_lite_aclk), + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[5] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(Q[3]), - .Q(mm2s_ip2axi_frame_ptr_ref_cdc_tig[3]), + .D(p_2_in[5]), + .Q(frame_ptr_out_d1_cdc_tig[5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] - (.C(s_axi_lite_aclk), + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[0] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(Q[4]), - .Q(mm2s_ip2axi_frame_ptr_ref_cdc_tig[4]), + .D(frame_ptr_out_d1_cdc_tig[0]), + .Q(frame_ptr_out_d2[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[0] - (.C(s_axi_lite_aclk), + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[1] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(\MM2S_ERR_FOR_IRQ.frm_store_i_reg[4] [0]), - .Q(mm2s_ip2axi_frame_store_cdc_tig[0]), + .D(frame_ptr_out_d1_cdc_tig[1]), + .Q(frame_ptr_out_d2[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[1] - (.C(s_axi_lite_aclk), + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[2] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(\MM2S_ERR_FOR_IRQ.frm_store_i_reg[4] [1]), - .Q(mm2s_ip2axi_frame_store_cdc_tig[1]), + .D(frame_ptr_out_d1_cdc_tig[2]), + .Q(frame_ptr_out_d2[2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[2] - (.C(s_axi_lite_aclk), + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[3] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(\MM2S_ERR_FOR_IRQ.frm_store_i_reg[4] [2]), - .Q(mm2s_ip2axi_frame_store_cdc_tig[2]), + .D(frame_ptr_out_d1_cdc_tig[3]), + .Q(frame_ptr_out_d2[3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[3] - (.C(s_axi_lite_aclk), + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[4] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(\MM2S_ERR_FOR_IRQ.frm_store_i_reg[4] [3]), - .Q(mm2s_ip2axi_frame_store_cdc_tig[3]), + .D(frame_ptr_out_d1_cdc_tig[4]), + .Q(frame_ptr_out_d2[4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] - (.C(s_axi_lite_aclk), + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[5] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(\MM2S_ERR_FOR_IRQ.frm_store_i_reg[4] [4]), - .Q(mm2s_ip2axi_frame_store_cdc_tig[4]), + .D(frame_ptr_out_d1_cdc_tig[5]), + .Q(frame_ptr_out_d2[5]), .R(1'b0)); LUT1 #( .INIT(2'h2)) i_0 (.I0(1'b0), - .O(s2mm_ip2axi_frame_ptr_ref_cdc_tig[4])); + .O(p_2_in[5])); LUT1 #( .INIT(2'h2)) i_1 (.I0(1'b0), - .O(s2mm_ip2axi_frame_ptr_ref_cdc_tig[3])); + .O(p_2_in[4])); LUT1 #( .INIT(2'h2)) i_10 (.I0(1'b0), - .O(s2mm_chnl_current_frame_cdc_tig[4])); + .O(othrchnl_frame_ptr_in_d2[4])); LUT1 #( .INIT(2'h2)) i_11 (.I0(1'b0), - .O(s2mm_chnl_current_frame_cdc_tig[3])); + .O(othrchnl_frame_ptr_in_d2[3])); LUT1 #( .INIT(2'h2)) i_12 (.I0(1'b0), - .O(s2mm_chnl_current_frame_cdc_tig[2])); + .O(othrchnl_frame_ptr_in_d2[2])); LUT1 #( .INIT(2'h2)) i_13 (.I0(1'b0), - .O(s2mm_chnl_current_frame_cdc_tig[1])); + .O(othrchnl_frame_ptr_in_d2[1])); LUT1 #( .INIT(2'h2)) i_14 (.I0(1'b0), - .O(s2mm_chnl_current_frame_cdc_tig[0])); - LUT1 #( - .INIT(2'h2)) - i_15 - (.I0(1'b0), - .O(s2mm_genlock_pair_frame_cdc_tig[4])); - LUT1 #( - .INIT(2'h2)) - i_16 - (.I0(1'b0), - .O(s2mm_genlock_pair_frame_cdc_tig[3])); - LUT1 #( - .INIT(2'h2)) - i_17 - (.I0(1'b0), - .O(s2mm_genlock_pair_frame_cdc_tig[2])); - LUT1 #( - .INIT(2'h2)) - i_18 - (.I0(1'b0), - .O(s2mm_genlock_pair_frame_cdc_tig[1])); - LUT1 #( - .INIT(2'h2)) - i_19 - (.I0(1'b0), - .O(s2mm_genlock_pair_frame_cdc_tig[0])); + .O(othrchnl_frame_ptr_in_d2[0])); LUT1 #( .INIT(2'h2)) i_2 (.I0(1'b0), - .O(s2mm_ip2axi_frame_ptr_ref_cdc_tig[2])); - LUT1 #( - .INIT(2'h2)) - i_20 - (.I0(1'b0), - .O(s2mm_capture_hsize_at_uf_err_cdc_tig[15])); - LUT1 #( - .INIT(2'h2)) - i_21 - (.I0(1'b0), - .O(s2mm_capture_hsize_at_uf_err_cdc_tig[14])); - LUT1 #( - .INIT(2'h2)) - i_22 - (.I0(1'b0), - .O(s2mm_capture_hsize_at_uf_err_cdc_tig[13])); - LUT1 #( - .INIT(2'h2)) - i_23 - (.I0(1'b0), - .O(s2mm_capture_hsize_at_uf_err_cdc_tig[12])); - LUT1 #( - .INIT(2'h2)) - i_24 - (.I0(1'b0), - .O(s2mm_capture_hsize_at_uf_err_cdc_tig[11])); - LUT1 #( - .INIT(2'h2)) - i_25 - (.I0(1'b0), - .O(s2mm_capture_hsize_at_uf_err_cdc_tig[10])); - LUT1 #( - .INIT(2'h2)) - i_26 - (.I0(1'b0), - .O(s2mm_capture_hsize_at_uf_err_cdc_tig[9])); - LUT1 #( - .INIT(2'h2)) - i_27 - (.I0(1'b0), - .O(s2mm_capture_hsize_at_uf_err_cdc_tig[8])); - LUT1 #( - .INIT(2'h2)) - i_28 - (.I0(1'b0), - .O(s2mm_capture_hsize_at_uf_err_cdc_tig[7])); - LUT1 #( - .INIT(2'h2)) - i_29 - (.I0(1'b0), - .O(s2mm_capture_hsize_at_uf_err_cdc_tig[6])); + .O(p_2_in[3])); LUT1 #( .INIT(2'h2)) i_3 (.I0(1'b0), - .O(s2mm_ip2axi_frame_ptr_ref_cdc_tig[1])); - LUT1 #( - .INIT(2'h2)) - i_30 - (.I0(1'b0), - .O(s2mm_capture_hsize_at_uf_err_cdc_tig[5])); - LUT1 #( - .INIT(2'h2)) - i_31 - (.I0(1'b0), - .O(s2mm_capture_hsize_at_uf_err_cdc_tig[4])); - LUT1 #( - .INIT(2'h2)) - i_32 - (.I0(1'b0), - .O(s2mm_capture_hsize_at_uf_err_cdc_tig[3])); - LUT1 #( - .INIT(2'h2)) - i_33 - (.I0(1'b0), - .O(s2mm_capture_hsize_at_uf_err_cdc_tig[2])); - LUT1 #( - .INIT(2'h2)) - i_34 - (.I0(1'b0), - .O(s2mm_capture_hsize_at_uf_err_cdc_tig[1])); - LUT1 #( - .INIT(2'h2)) - i_35 - (.I0(1'b0), - .O(s2mm_capture_hsize_at_uf_err_cdc_tig[0])); - LUT1 #( - .INIT(2'h2)) - i_36 - (.I0(1'b0), - .O(s2mm_capture_dm_done_vsize_counter_cdc_tig[12])); - LUT1 #( - .INIT(2'h2)) - i_37 - (.I0(1'b0), - .O(s2mm_capture_dm_done_vsize_counter_cdc_tig[11])); - LUT1 #( - .INIT(2'h2)) - i_38 - (.I0(1'b0), - .O(s2mm_capture_dm_done_vsize_counter_cdc_tig[10])); - LUT1 #( - .INIT(2'h2)) - i_39 - (.I0(1'b0), - .O(s2mm_capture_dm_done_vsize_counter_cdc_tig[9])); + .O(othrchnl_frame_ptr_in_d1_cdc_tig[5])); LUT1 #( .INIT(2'h2)) i_4 (.I0(1'b0), - .O(s2mm_ip2axi_frame_ptr_ref_cdc_tig[0])); - LUT1 #( - .INIT(2'h2)) - i_40 - (.I0(1'b0), - .O(s2mm_capture_dm_done_vsize_counter_cdc_tig[8])); - LUT1 #( - .INIT(2'h2)) - i_41 - (.I0(1'b0), - .O(s2mm_capture_dm_done_vsize_counter_cdc_tig[7])); - LUT1 #( - .INIT(2'h2)) - i_42 - (.I0(1'b0), - .O(s2mm_capture_dm_done_vsize_counter_cdc_tig[6])); - LUT1 #( - .INIT(2'h2)) - i_43 - (.I0(1'b0), - .O(s2mm_capture_dm_done_vsize_counter_cdc_tig[5])); - LUT1 #( - .INIT(2'h2)) - i_44 - (.I0(1'b0), - .O(s2mm_capture_dm_done_vsize_counter_cdc_tig[4])); - LUT1 #( - .INIT(2'h2)) - i_45 - (.I0(1'b0), - .O(s2mm_capture_dm_done_vsize_counter_cdc_tig[3])); - LUT1 #( - .INIT(2'h2)) - i_46 - (.I0(1'b0), - .O(s2mm_capture_dm_done_vsize_counter_cdc_tig[2])); - LUT1 #( - .INIT(2'h2)) - i_47 - (.I0(1'b0), - .O(s2mm_capture_dm_done_vsize_counter_cdc_tig[1])); - LUT1 #( - .INIT(2'h2)) - i_48 - (.I0(1'b0), - .O(s2mm_capture_dm_done_vsize_counter_cdc_tig[0])); + .O(othrchnl_frame_ptr_in_d1_cdc_tig[4])); LUT1 #( .INIT(2'h2)) i_5 (.I0(1'b0), - .O(s2mm_ip2axi_frame_store_cdc_tig[4])); + .O(othrchnl_frame_ptr_in_d1_cdc_tig[3])); LUT1 #( .INIT(2'h2)) i_6 (.I0(1'b0), - .O(s2mm_ip2axi_frame_store_cdc_tig[3])); + .O(othrchnl_frame_ptr_in_d1_cdc_tig[2])); LUT1 #( .INIT(2'h2)) i_7 (.I0(1'b0), - .O(s2mm_ip2axi_frame_store_cdc_tig[2])); + .O(othrchnl_frame_ptr_in_d1_cdc_tig[1])); LUT1 #( .INIT(2'h2)) i_8 (.I0(1'b0), - .O(s2mm_ip2axi_frame_store_cdc_tig[1])); + .O(othrchnl_frame_ptr_in_d1_cdc_tig[0])); LUT1 #( .INIT(2'h2)) i_9 (.I0(1'b0), - .O(s2mm_ip2axi_frame_store_cdc_tig[0])); + .O(othrchnl_frame_ptr_in_d2[5])); + FDRE #( + .INIT(1'b0)) + s_fsync_d1_reg + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(s2mm_fsync_core), + .Q(s_fsync_d1), + .R(prmry_reset2)); + FDRE #( + .INIT(1'b0)) + s_fsync_d2_reg + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(s_fsync_d1), + .Q(s_fsync_d2), + .R(prmry_reset2)); endmodule -(* ORIG_REF_NAME = "axi_vdma_reg_module" *) -module Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_module - (p_68_out, +(* ORIG_REF_NAME = "axi_vdma_vidreg_module" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_vidreg_module + (prmtr_update_complete, + zero_hsize_err0, + Q, + zero_vsize_err0, + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] , + p_26_out, + \stride_vid_reg[0] , + \dm_address_reg[19] , + \dm_address_reg[19]_0 , + \dm_address_reg[19]_1 , + \dm_address_reg[19]_2 , + \dm_address_reg[23] , + \dm_address_reg[23]_0 , + \dm_address_reg[23]_1 , + \dm_address_reg[23]_2 , + \dm_address_reg[27] , + \dm_address_reg[27]_0 , + \dm_address_reg[27]_1 , + \dm_address_reg[27]_2 , + \dm_address_reg[31] , + \dm_address_reg[31]_0 , + \dm_address_reg[31]_1 , + \dm_address_reg[31]_2 , + S, + \GEN_STS_GRTR_THAN_8.undrflo_err_reg , + O, + \dm_address_reg[7] , + \dm_address_reg[11] , + CO, + \dm_address_reg[15] , + p_2_out, + prmtr_updt_complete_i_reg, + m_axi_s2mm_aclk, + load_new_addr, + tstvect_fsync_d2, + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] , + m_axis_s2mm_sts_tdata, + s2mm_cdc2dmac_fsync, + \dm_address_reg[15]_0 , + mask_fsync_out_i, + tstvect_fsync_d1, + SR, + \reg_module_vsize_reg[12] , + \reg_module_hsize_reg[15] , + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] , + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] , + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] , + \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] , out, - err_d1_reg, - ioc_irq_reg, - dly_irq_reg, - reset_counts, - p_67_out, - err_d1_reg_0, - err_d1_reg_1, - p_75_out, - p_64_out, - s_soft_reset_i0, - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] , - ch1_disable_delay2_out, - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0] , - p_6_out__1, - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from , - stop_i, - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6] , - ch1_delay_zero__6, - err_irq_reg, - different_delay, - different_thresh, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0] , - \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] , - \stride_vid_reg[15] , - \hsize_vid_reg[15] , - \vsize_vid_reg[12] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[1] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[2] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[13] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[14] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15] , - \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4] , + s2mm_dmasr); + output prmtr_update_complete; + output zero_hsize_err0; + output [15:0]Q; + output zero_vsize_err0; + output [12:0]\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] ; + output p_26_out; + output \stride_vid_reg[0] ; + output \dm_address_reg[19] ; + output \dm_address_reg[19]_0 ; + output \dm_address_reg[19]_1 ; + output \dm_address_reg[19]_2 ; + output \dm_address_reg[23] ; + output \dm_address_reg[23]_0 ; + output \dm_address_reg[23]_1 ; + output \dm_address_reg[23]_2 ; + output \dm_address_reg[27] ; + output \dm_address_reg[27]_0 ; + output \dm_address_reg[27]_1 ; + output \dm_address_reg[27]_2 ; + output \dm_address_reg[31] ; + output \dm_address_reg[31]_0 ; + output \dm_address_reg[31]_1 ; + output \dm_address_reg[31]_2 ; + output [0:0]S; + output [0:0]\GEN_STS_GRTR_THAN_8.undrflo_err_reg ; + output [3:0]O; + output [3:0]\dm_address_reg[7] ; + output [3:0]\dm_address_reg[11] ; + output [0:0]CO; + output [3:0]\dm_address_reg[15] ; + output p_2_out; + input prmtr_updt_complete_i_reg; + input m_axi_s2mm_aclk; + input load_new_addr; + input tstvect_fsync_d2; + input [1:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] ; + input [0:0]m_axis_s2mm_sts_tdata; + input s2mm_cdc2dmac_fsync; + input [15:0]\dm_address_reg[15]_0 ; + input mask_fsync_out_i; + input tstvect_fsync_d1; + input [0:0]SR; + input [12:0]\reg_module_vsize_reg[12] ; + input [15:0]\reg_module_hsize_reg[15] ; + input [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] ; + input [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] ; + input [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] ; + input [15:0]\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ; + input out; + input [0:0]s2mm_dmasr; + + wire [0:0]CO; + wire [15:0]\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ; + wire [1:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] ; + wire [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] ; + wire [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] ; + wire [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] ; + wire \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_i_1__0_n_0 ; + wire [12:0]\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] ; + wire [0:0]\GEN_STS_GRTR_THAN_8.undrflo_err_reg ; + wire [3:0]O; + wire [15:0]Q; + wire [0:0]S; + wire [0:0]SR; + wire [3:0]\dm_address_reg[11] ; + wire [3:0]\dm_address_reg[15] ; + wire [15:0]\dm_address_reg[15]_0 ; + wire \dm_address_reg[19] ; + wire \dm_address_reg[19]_0 ; + wire \dm_address_reg[19]_1 ; + wire \dm_address_reg[19]_2 ; + wire \dm_address_reg[23] ; + wire \dm_address_reg[23]_0 ; + wire \dm_address_reg[23]_1 ; + wire \dm_address_reg[23]_2 ; + wire \dm_address_reg[27] ; + wire \dm_address_reg[27]_0 ; + wire \dm_address_reg[27]_1 ; + wire \dm_address_reg[27]_2 ; + wire \dm_address_reg[31] ; + wire \dm_address_reg[31]_0 ; + wire \dm_address_reg[31]_1 ; + wire \dm_address_reg[31]_2 ; + wire [3:0]\dm_address_reg[7] ; + wire load_new_addr; + wire m_axi_s2mm_aclk; + wire [0:0]m_axis_s2mm_sts_tdata; + wire mask_fsync_out_i; + wire out; + wire p_26_out; + wire p_2_out; + wire prmtr_update_complete; + wire prmtr_updt_complete_i_reg; + wire [15:0]\reg_module_hsize_reg[15] ; + wire [12:0]\reg_module_vsize_reg[12] ; + wire s2mm_cdc2dmac_fsync; + wire [0:0]s2mm_dmasr; + wire \stride_vid_reg[0] ; + wire tstvect_fsync_d1; + wire tstvect_fsync_d2; + wire zero_hsize_err0; + wire zero_vsize_err0; + + (* SOFT_HLUTNM = "soft_lutpair81" *) + LUT2 #( + .INIT(4'h8)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.tstvect_fsync_i_1 + (.I0(\stride_vid_reg[0] ), + .I1(tstvect_fsync_d2), + .O(p_26_out)); + (* SOFT_HLUTNM = "soft_lutpair81" *) + LUT3 #( + .INIT(8'h20)) + \GEN_FSYNC_MODE_S2MM_FLUSH_SOF.frame_sync_out_i_1 + (.I0(\stride_vid_reg[0] ), + .I1(mask_fsync_out_i), + .I2(tstvect_fsync_d1), + .O(p_2_out)); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_vregister \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.VIDREGISTER_I + (.CO(CO), + .\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] (\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ), + .\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] (\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] ), + .\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] (\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] ), + .\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] (\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] ), + .\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] (\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] ), + .\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg (\stride_vid_reg[0] ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] (\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] ), + .\GEN_STS_GRTR_THAN_8.undrflo_err_reg (\GEN_STS_GRTR_THAN_8.undrflo_err_reg ), + .O(O), + .Q(Q), + .S(S), + .SR(SR), + .\dm_address_reg[11] (\dm_address_reg[11] ), + .\dm_address_reg[15] (\dm_address_reg[15] ), + .\dm_address_reg[15]_0 (\dm_address_reg[15]_0 ), + .\dm_address_reg[19] (\dm_address_reg[19] ), + .\dm_address_reg[19]_0 (\dm_address_reg[19]_0 ), + .\dm_address_reg[19]_1 (\dm_address_reg[19]_1 ), + .\dm_address_reg[19]_2 (\dm_address_reg[19]_2 ), + .\dm_address_reg[23] (\dm_address_reg[23] ), + .\dm_address_reg[23]_0 (\dm_address_reg[23]_0 ), + .\dm_address_reg[23]_1 (\dm_address_reg[23]_1 ), + .\dm_address_reg[23]_2 (\dm_address_reg[23]_2 ), + .\dm_address_reg[27] (\dm_address_reg[27] ), + .\dm_address_reg[27]_0 (\dm_address_reg[27]_0 ), + .\dm_address_reg[27]_1 (\dm_address_reg[27]_1 ), + .\dm_address_reg[27]_2 (\dm_address_reg[27]_2 ), + .\dm_address_reg[31] (\dm_address_reg[31] ), + .\dm_address_reg[31]_0 (\dm_address_reg[31]_0 ), + .\dm_address_reg[31]_1 (\dm_address_reg[31]_1 ), + .\dm_address_reg[31]_2 (\dm_address_reg[31]_2 ), + .\dm_address_reg[7] (\dm_address_reg[7] ), + .load_new_addr(load_new_addr), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .m_axis_s2mm_sts_tdata(m_axis_s2mm_sts_tdata), + .prmtr_update_complete(prmtr_update_complete), + .\reg_module_hsize_reg[15] (\reg_module_hsize_reg[15] ), + .\reg_module_vsize_reg[12] (\reg_module_vsize_reg[12] ), + .s2mm_cdc2dmac_fsync(s2mm_cdc2dmac_fsync), + .zero_hsize_err0(zero_hsize_err0), + .zero_vsize_err0(zero_vsize_err0)); + LUT5 #( + .INIT(32'h0000EA00)) + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_i_1__0 + (.I0(\stride_vid_reg[0] ), + .I1(prmtr_update_complete), + .I2(s2mm_cdc2dmac_fsync), + .I3(out), + .I4(s2mm_dmasr), + .O(\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_i_1__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_i_1__0_n_0 ), + .Q(\stride_vid_reg[0] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(prmtr_updt_complete_i_reg), + .Q(prmtr_update_complete), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_vidreg_module" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_vidreg_module_43 + (\stride_vid_reg[0] , + zero_vsize_err0, + Q, + zero_hsize_err0, + \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] , + all_idle_reg, + \stride_vid_reg[0]_0 , + p_10_out, + \dm_address_reg[19] , + \dm_address_reg[19]_0 , + \dm_address_reg[19]_1 , + \dm_address_reg[19]_2 , + \dm_address_reg[23] , + \dm_address_reg[23]_0 , + \dm_address_reg[23]_1 , + \dm_address_reg[23]_2 , + \dm_address_reg[27] , + \dm_address_reg[27]_0 , + \dm_address_reg[27]_1 , + \dm_address_reg[27]_2 , + \dm_address_reg[31] , + \dm_address_reg[31]_0 , + \dm_address_reg[31]_1 , + \dm_address_reg[31]_2 , E, - datamover_idle_reg, - \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg , - \s_axis_cmd_tdata_reg[63] , - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] , - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] , + O, + \dm_address_reg[7] , + \dm_address_reg[11] , + CO, + \dm_address_reg[15] , + p_2_out, + prmtr_updt_complete_i_reg, m_axi_mm2s_aclk, - SR, - mm2s_axi2ip_wrce, - D, - in0, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7]_0 , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13] , - \dmacr_i_reg[2] , - reset_counts_reg, - halted_clr_reg, - slverr_i_reg, - decerr_i_reg, - prmry_resetn_i_reg, - mm2s_halt_cmplt, - halt_reset, - prmry_in, - p_17_out, - ch1_delay_cnt_en, - p_10_out, - ch1_ioc_irq_set_i__0, - Q, - p_49_out, - p_44_out, - mm2s_dly_irq_set, - mm2s_halt, - dma_err, - \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg , - p_0_out, - p_46_out, + load_new_addr, + p_39_out, + mm2s_fifo_pipe_empty, + p_67_out, + tstvect_fsync_d2, + \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] , + p_24_out, + \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]_0 , + valid_frame_sync_d2, + p_71_out, + \dm_address_reg[15]_0 , mask_fsync_out_i, - prmry_resetn_i_reg_0, - p_35_out, - mm2s_ioc_irq_set, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] , - initial_frame, - datamover_idle, - p_23_out, - prmtr_update_complete, - prmry_resetn_i_reg_1, - \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0 ); - output [25:0]p_68_out; - output [31:0]out; - output err_d1_reg; - output ioc_irq_reg; - output dly_irq_reg; - output reset_counts; - output p_67_out; - output err_d1_reg_0; - output err_d1_reg_1; - output p_75_out; - output p_64_out; - output s_soft_reset_i0; - output [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] ; - output ch1_disable_delay2_out; - output [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0] ; - output p_6_out__1; - output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ; - output stop_i; - output [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6] ; - output ch1_delay_zero__6; - output err_irq_reg; - output different_delay; - output different_thresh; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0] ; - output [31:0]\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] ; - output [15:0]\stride_vid_reg[15] ; - output [15:0]\hsize_vid_reg[15] ; - output [12:0]\vsize_vid_reg[12] ; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[1] ; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[2] ; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3] ; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4] ; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5] ; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6] ; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7] ; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8] ; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9] ; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10] ; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11] ; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12] ; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[13] ; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[14] ; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15] ; - output [0:0]\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4] ; + tstvect_fsync_d1, + SR, + \reg_module_vsize_reg[12] , + \reg_module_hsize_reg[15] , + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] , + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] , + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] , + \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] , + mm2s_prmry_resetn, + p_70_out); + output \stride_vid_reg[0] ; + output zero_vsize_err0; + output [12:0]Q; + output zero_hsize_err0; + output [15:0]\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] ; + output all_idle_reg; + output \stride_vid_reg[0]_0 ; + output p_10_out; + output \dm_address_reg[19] ; + output \dm_address_reg[19]_0 ; + output \dm_address_reg[19]_1 ; + output \dm_address_reg[19]_2 ; + output \dm_address_reg[23] ; + output \dm_address_reg[23]_0 ; + output \dm_address_reg[23]_1 ; + output \dm_address_reg[23]_2 ; + output \dm_address_reg[27] ; + output \dm_address_reg[27]_0 ; + output \dm_address_reg[27]_1 ; + output \dm_address_reg[27]_2 ; + output \dm_address_reg[31] ; + output \dm_address_reg[31]_0 ; + output \dm_address_reg[31]_1 ; + output \dm_address_reg[31]_2 ; output [0:0]E; - output datamover_idle_reg; - output \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg ; - output [0:0]\s_axis_cmd_tdata_reg[63] ; - output [4:0]\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] ; - output [4:0]\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] ; + output [3:0]O; + output [3:0]\dm_address_reg[7] ; + output [3:0]\dm_address_reg[11] ; + output [0:0]CO; + output [3:0]\dm_address_reg[15] ; + output p_2_out; + input prmtr_updt_complete_i_reg; input m_axi_mm2s_aclk; - input [0:0]SR; - input [6:0]mm2s_axi2ip_wrce; - input [31:0]D; - input [31:0]in0; - input \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7] ; - input \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7]_0 ; - input \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] ; - input \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12] ; - input \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13] ; - input \dmacr_i_reg[2] ; - input reset_counts_reg; - input halted_clr_reg; - input slverr_i_reg; - input decerr_i_reg; - input prmry_resetn_i_reg; - input mm2s_halt_cmplt; - input halt_reset; - input prmry_in; - input p_17_out; - input ch1_delay_cnt_en; - input p_10_out; - input ch1_ioc_irq_set_i__0; - input [0:0]Q; - input p_49_out; - input p_44_out; - input mm2s_dly_irq_set; - input mm2s_halt; - input dma_err; - input \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg ; - input p_0_out; - input p_46_out; + input load_new_addr; + input p_39_out; + input mm2s_fifo_pipe_empty; + input p_67_out; + input tstvect_fsync_d2; + input [1:0]\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] ; + input p_24_out; + input \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]_0 ; + input valid_frame_sync_d2; + input [0:0]p_71_out; + input [15:0]\dm_address_reg[15]_0 ; input mask_fsync_out_i; - input prmry_resetn_i_reg_0; - input p_35_out; - input mm2s_ioc_irq_set; - input [1:0]\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] ; - input initial_frame; - input datamover_idle; - input p_23_out; - input prmtr_update_complete; - input [0:0]prmry_resetn_i_reg_1; - input [4:0]\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0 ; + input tstvect_fsync_d1; + input [0:0]SR; + input [12:0]\reg_module_vsize_reg[12] ; + input [15:0]\reg_module_hsize_reg[15] ; + input [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] ; + input [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] ; + input [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] ; + input [15:0]\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ; + input mm2s_prmry_resetn; + input p_70_out; - wire [31:0]D; + wire [0:0]CO; wire [0:0]E; - wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ; - wire \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg ; - wire [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6] ; - wire [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] ; - wire [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0] ; - wire [1:0]\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7]_0 ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[13] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[14] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[1] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[2] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9] ; - wire [4:0]\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] ; - wire [4:0]\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] ; - wire \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg ; - wire [31:0]\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] ; - wire [0:0]\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4] ; - wire [4:0]\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0 ; - wire [0:0]Q; + wire [15:0]\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] ; + wire [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] ; + wire [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] ; + wire [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] ; + wire \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_i_1_n_0 ; + wire [1:0]\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] ; + wire \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]_0 ; + wire [15:0]\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ; + wire [3:0]O; + wire [12:0]Q; wire [0:0]SR; - wire ch1_delay_cnt_en; - wire ch1_delay_zero__6; - wire ch1_disable_delay2_out; - wire ch1_ioc_irq_set_i__0; - wire datamover_idle; - wire datamover_idle_reg; - wire decerr_i_reg; - wire different_delay; - wire different_thresh; - wire dly_irq_reg; - wire dma_err; - wire \dmacr_i_reg[2] ; - wire err_d1_reg; - wire err_d1_reg_0; - wire err_d1_reg_1; - wire err_irq_reg; - wire halt_reset; - wire halted_clr_reg; - wire [15:0]\hsize_vid_reg[15] ; - wire [31:0]in0; - wire initial_frame; - wire ioc_irq_reg; + wire all_idle_reg; + wire [3:0]\dm_address_reg[11] ; + wire [3:0]\dm_address_reg[15] ; + wire [15:0]\dm_address_reg[15]_0 ; + wire \dm_address_reg[19] ; + wire \dm_address_reg[19]_0 ; + wire \dm_address_reg[19]_1 ; + wire \dm_address_reg[19]_2 ; + wire \dm_address_reg[23] ; + wire \dm_address_reg[23]_0 ; + wire \dm_address_reg[23]_1 ; + wire \dm_address_reg[23]_2 ; + wire \dm_address_reg[27] ; + wire \dm_address_reg[27]_0 ; + wire \dm_address_reg[27]_1 ; + wire \dm_address_reg[27]_2 ; + wire \dm_address_reg[31] ; + wire \dm_address_reg[31]_0 ; + wire \dm_address_reg[31]_1 ; + wire \dm_address_reg[31]_2 ; + wire [3:0]\dm_address_reg[7] ; + wire load_new_addr; wire m_axi_mm2s_aclk; wire mask_fsync_out_i; - wire [6:0]mm2s_axi2ip_wrce; - wire mm2s_dly_irq_set; - wire mm2s_halt; - wire mm2s_halt_cmplt; - wire mm2s_ioc_irq_set; - wire [31:0]out; - wire p_0_out; + wire mm2s_fifo_pipe_empty; + wire mm2s_prmry_resetn; wire p_10_out; - wire p_17_out; - wire p_23_out; - wire p_35_out; - wire p_44_out; - wire p_46_out; - wire p_49_out; - wire p_64_out; + wire p_24_out; + wire p_2_out; + wire p_39_out; wire p_67_out; - wire [25:0]p_68_out; - wire p_6_out__1; - wire p_75_out; - wire prmry_in; - wire prmry_resetn_i_reg; - wire prmry_resetn_i_reg_0; - wire [0:0]prmry_resetn_i_reg_1; - wire prmtr_update_complete; - wire reset_counts; - wire reset_counts_reg; - wire [0:0]\s_axis_cmd_tdata_reg[63] ; - wire s_soft_reset_i0; - wire slverr_i_reg; - wire stop_i; - wire [15:0]\stride_vid_reg[15] ; - wire [12:0]\vsize_vid_reg[12] ; + wire p_70_out; + wire [0:0]p_71_out; + wire prmtr_updt_complete_i_reg; + wire [15:0]\reg_module_hsize_reg[15] ; + wire [12:0]\reg_module_vsize_reg[12] ; + wire \stride_vid_reg[0] ; + wire \stride_vid_reg[0]_0 ; + wire tstvect_fsync_d1; + wire tstvect_fsync_d2; + wire valid_frame_sync_d2; + wire zero_hsize_err0; + wire zero_vsize_err0; - Arty_Z7_20_axi_vdma_0_0_axi_vdma_regdirect \GEN_REG_DIRECT_MODE.REGDIRECT_I - (.D(D), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] (\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0] (\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0] ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10] (\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10] ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11] (\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11] ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12] (\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12] ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[13] (\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[13] ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[14] (\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[14] ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15] (\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15] ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[1] (\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[1] ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[2] (\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[2] ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3] (\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3] ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4] (\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4] ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5] (\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5] ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6] (\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6] ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7] (\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7] ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8] (\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8] ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9] (\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9] ), - .\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg (\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg ), - .\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] (\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] ), - .SR(SR), - .\dmacr_i_reg[0] (p_68_out[0]), - .halted_reg(p_67_out), - .\hsize_vid_reg[15] (\hsize_vid_reg[15] ), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .mm2s_axi2ip_wrce(mm2s_axi2ip_wrce[6:3]), - .p_23_out(p_23_out), - .p_35_out(p_35_out), - .p_64_out(p_64_out), - .prmry_resetn_i_reg(prmry_resetn_i_reg), - .prmry_resetn_i_reg_0(prmry_resetn_i_reg_0), - .prmtr_update_complete(prmtr_update_complete), - .\stride_vid_reg[15] (\stride_vid_reg[15] ), - .\vsize_vid_reg[12] (\vsize_vid_reg[12] )); - Arty_Z7_20_axi_vdma_0_0_axi_vdma_register I_DMA_REGISTER - (.D({D[31:12],D[6:4],D[1:0]}), - .E(E), - .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ), - .\GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg (\GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg ), - .\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6] (\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6] ), - .\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] (\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] ), - .\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0] (\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0] ), - .\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] (reset_counts), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7] (\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7] ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7]_0 (\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7]_0 ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12] (\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12] ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13] (\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13] ), - .\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] (\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] ), - .\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] (\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] ), - .\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4] (\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4] ), - .\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0 (\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0 ), + LUT3 #( + .INIT(8'h20)) + \GEN_FREE_RUN_MODE.frame_sync_out_i_1 + (.I0(\stride_vid_reg[0]_0 ), + .I1(mask_fsync_out_i), + .I2(tstvect_fsync_d1), + .O(p_2_out)); + Arty_Z7_20_axi_vdma_0_0_axi_vdma_vregister_44 \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.VIDREGISTER_I + (.CO(CO), + .\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] (\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] ), + .\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] (\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] ), + .\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] (\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] ), + .\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] (\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] ), + .\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg (\stride_vid_reg[0]_0 ), + .\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg (\stride_vid_reg[0] ), + .\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] (\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] ), + .\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] (\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ), + .O(O), .Q(Q), .SR(SR), - .ch1_delay_cnt_en(ch1_delay_cnt_en), - .ch1_delay_zero__6(ch1_delay_zero__6), - .ch1_disable_delay2_out(ch1_disable_delay2_out), - .ch1_ioc_irq_set_i__0(ch1_ioc_irq_set_i__0), - .datamover_idle(datamover_idle), - .datamover_idle_reg(datamover_idle_reg), - .decerr_i_reg(decerr_i_reg), - .different_delay(different_delay), - .different_thresh(different_thresh), - .dly_irq_reg_0(dly_irq_reg), - .dma_err(dma_err), - .\dmacr_i_reg[2]_0 (\dmacr_i_reg[2] ), - .err_d1_reg_0(err_d1_reg), - .err_d1_reg_1(err_d1_reg_0), - .err_d1_reg_2(err_d1_reg_1), - .err_irq_reg_0(err_irq_reg), - .halt_reset(halt_reset), - .halted_clr_reg(halted_clr_reg), - .initial_frame(initial_frame), - .ioc_irq_reg_0(ioc_irq_reg), + .\dm_address_reg[11] (\dm_address_reg[11] ), + .\dm_address_reg[15] (\dm_address_reg[15] ), + .\dm_address_reg[15]_0 (\dm_address_reg[15]_0 ), + .\dm_address_reg[19] (\dm_address_reg[19] ), + .\dm_address_reg[19]_0 (\dm_address_reg[19]_0 ), + .\dm_address_reg[19]_1 (\dm_address_reg[19]_1 ), + .\dm_address_reg[19]_2 (\dm_address_reg[19]_2 ), + .\dm_address_reg[23] (\dm_address_reg[23] ), + .\dm_address_reg[23]_0 (\dm_address_reg[23]_0 ), + .\dm_address_reg[23]_1 (\dm_address_reg[23]_1 ), + .\dm_address_reg[23]_2 (\dm_address_reg[23]_2 ), + .\dm_address_reg[27] (\dm_address_reg[27] ), + .\dm_address_reg[27]_0 (\dm_address_reg[27]_0 ), + .\dm_address_reg[27]_1 (\dm_address_reg[27]_1 ), + .\dm_address_reg[27]_2 (\dm_address_reg[27]_2 ), + .\dm_address_reg[31] (\dm_address_reg[31] ), + .\dm_address_reg[31]_0 (\dm_address_reg[31]_0 ), + .\dm_address_reg[31]_1 (\dm_address_reg[31]_1 ), + .\dm_address_reg[31]_2 (\dm_address_reg[31]_2 ), + .\dm_address_reg[7] (\dm_address_reg[7] ), + .load_new_addr(load_new_addr), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .mask_fsync_out_i(mask_fsync_out_i), - .mm2s_axi2ip_wrce(mm2s_axi2ip_wrce[1:0]), - .mm2s_dly_irq_set(mm2s_dly_irq_set), - .mm2s_halt(mm2s_halt), - .mm2s_halt_cmplt(mm2s_halt_cmplt), - .mm2s_ioc_irq_set(mm2s_ioc_irq_set), - .p_0_out(p_0_out), - .p_10_out(p_10_out), - .p_17_out(p_17_out), - .p_23_out(p_23_out), - .p_35_out(p_35_out), - .p_44_out(p_44_out), - .p_46_out(p_46_out), - .p_49_out(p_49_out), - .p_68_out(p_68_out[25:1]), - .p_6_out__1(p_6_out__1), - .p_75_out(p_75_out), - .prmry_in(prmry_in), - .prmry_resetn_i_reg(prmry_resetn_i_reg_0), - .prmry_resetn_i_reg_0(prmry_resetn_i_reg_1), - .reset_counts_reg_0(reset_counts_reg), - .run_stop_d1_reg(p_68_out[0]), - .\s_axis_cmd_tdata_reg[63] (p_67_out), - .\s_axis_cmd_tdata_reg[63]_0 (\s_axis_cmd_tdata_reg[63] ), - .s_soft_reset_i0(s_soft_reset_i0), - .slverr_i_reg(slverr_i_reg), - .stop_i(stop_i)); - Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_mux LITE_READ_MUX_I - (.in0(in0), - .out(out)); + .p_24_out(p_24_out), + .\reg_module_hsize_reg[15] (\reg_module_hsize_reg[15] ), + .\reg_module_vsize_reg[12] (\reg_module_vsize_reg[12] ), + .zero_hsize_err0(zero_hsize_err0), + .zero_vsize_err0(zero_vsize_err0)); + LUT5 #( + .INIT(32'h0000EA00)) + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_i_1 + (.I0(\stride_vid_reg[0]_0 ), + .I1(p_24_out), + .I2(\stride_vid_reg[0] ), + .I3(mm2s_prmry_resetn), + .I4(p_70_out), + .O(\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_i_1_n_0 )); FDRE #( .INIT(1'b0)) - \ptr_ref_i_reg[0] + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[2]), - .D(D[0]), - .Q(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] [0]), + .CE(1'b1), + .D(\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_i_1_n_0 ), + .Q(\stride_vid_reg[0]_0 ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(prmtr_updt_complete_i_reg), + .Q(\stride_vid_reg[0] ), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair42" *) + LUT4 #( + .INIT(16'hEAFA)) + \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_2 + (.I0(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]_0 ), + .I1(\stride_vid_reg[0]_0 ), + .I2(valid_frame_sync_d2), + .I3(p_71_out), + .O(E)); + (* SOFT_HLUTNM = "soft_lutpair42" *) + LUT2 #( + .INIT(4'h8)) + \MASTER_MODE_FRAME_CNT.tstvect_fsync_i_1 + (.I0(\stride_vid_reg[0]_0 ), + .I1(tstvect_fsync_d2), + .O(p_10_out)); + LUT5 #( + .INIT(32'h88888000)) + all_idle_i_1 + (.I0(p_39_out), + .I1(mm2s_fifo_pipe_empty), + .I2(\stride_vid_reg[0] ), + .I3(p_67_out), + .I4(\stride_vid_reg[0]_0 ), + .O(all_idle_reg)); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_vregister" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_vregister + (zero_hsize_err0, + Q, + zero_vsize_err0, + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] , + \dm_address_reg[19] , + \dm_address_reg[19]_0 , + \dm_address_reg[19]_1 , + \dm_address_reg[19]_2 , + \dm_address_reg[23] , + \dm_address_reg[23]_0 , + \dm_address_reg[23]_1 , + \dm_address_reg[23]_2 , + \dm_address_reg[27] , + \dm_address_reg[27]_0 , + \dm_address_reg[27]_1 , + \dm_address_reg[27]_2 , + \dm_address_reg[31] , + \dm_address_reg[31]_0 , + \dm_address_reg[31]_1 , + \dm_address_reg[31]_2 , + S, + \GEN_STS_GRTR_THAN_8.undrflo_err_reg , + O, + \dm_address_reg[7] , + \dm_address_reg[11] , + CO, + \dm_address_reg[15] , + load_new_addr, + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] , + m_axis_s2mm_sts_tdata, + prmtr_update_complete, + s2mm_cdc2dmac_fsync, + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg , + \dm_address_reg[15]_0 , + SR, + \reg_module_vsize_reg[12] , + m_axi_s2mm_aclk, + \reg_module_hsize_reg[15] , + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] , + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] , + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] , + \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ); + output zero_hsize_err0; + output [15:0]Q; + output zero_vsize_err0; + output [12:0]\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] ; + output \dm_address_reg[19] ; + output \dm_address_reg[19]_0 ; + output \dm_address_reg[19]_1 ; + output \dm_address_reg[19]_2 ; + output \dm_address_reg[23] ; + output \dm_address_reg[23]_0 ; + output \dm_address_reg[23]_1 ; + output \dm_address_reg[23]_2 ; + output \dm_address_reg[27] ; + output \dm_address_reg[27]_0 ; + output \dm_address_reg[27]_1 ; + output \dm_address_reg[27]_2 ; + output \dm_address_reg[31] ; + output \dm_address_reg[31]_0 ; + output \dm_address_reg[31]_1 ; + output \dm_address_reg[31]_2 ; + output [0:0]S; + output [0:0]\GEN_STS_GRTR_THAN_8.undrflo_err_reg ; + output [3:0]O; + output [3:0]\dm_address_reg[7] ; + output [3:0]\dm_address_reg[11] ; + output [0:0]CO; + output [3:0]\dm_address_reg[15] ; + input load_new_addr; + input [1:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] ; + input [0:0]m_axis_s2mm_sts_tdata; + input prmtr_update_complete; + input s2mm_cdc2dmac_fsync; + input \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg ; + input [15:0]\dm_address_reg[15]_0 ; + input [0:0]SR; + input [12:0]\reg_module_vsize_reg[12] ; + input m_axi_s2mm_aclk; + input [15:0]\reg_module_hsize_reg[15] ; + input [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] ; + input [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] ; + input [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] ; + input [15:0]\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ; + + wire [0:0]CO; + wire [15:0]\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ; + wire [1:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] ; + wire [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] ; + wire [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] ; + wire [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] ; + wire \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg ; + wire [12:0]\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] ; + wire [31:0]\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 ; + wire [31:0]\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 ; + wire [31:0]\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 ; + wire [0:0]\GEN_STS_GRTR_THAN_8.undrflo_err_reg ; + wire [3:0]O; + wire [15:0]Q; + wire [0:0]S; + wire [0:0]SR; + wire \dm_address[0]_i_10__0_n_0 ; + wire \dm_address[0]_i_11__0_n_0 ; + wire \dm_address[0]_i_12__0_n_0 ; + wire \dm_address[0]_i_13__0_n_0 ; + wire \dm_address[0]_i_14__0_n_0 ; + wire \dm_address[0]_i_3__0_n_0 ; + wire \dm_address[0]_i_4__0_n_0 ; + wire \dm_address[0]_i_5__0_n_0 ; + wire \dm_address[0]_i_6__0_n_0 ; + wire \dm_address[0]_i_7__0_n_0 ; + wire \dm_address[0]_i_8__0_n_0 ; + wire \dm_address[0]_i_9__0_n_0 ; + wire \dm_address[12]_i_10__0_n_0 ; + wire \dm_address[12]_i_11__0_n_0 ; + wire \dm_address[12]_i_12__0_n_0 ; + wire \dm_address[12]_i_13__0_n_0 ; + wire \dm_address[12]_i_2__0_n_0 ; + wire \dm_address[12]_i_3__0_n_0 ; + wire \dm_address[12]_i_4__0_n_0 ; + wire \dm_address[12]_i_5__0_n_0 ; + wire \dm_address[12]_i_6__0_n_0 ; + wire \dm_address[12]_i_7__0_n_0 ; + wire \dm_address[12]_i_8__0_n_0 ; + wire \dm_address[12]_i_9__0_n_0 ; + wire \dm_address[4]_i_10__0_n_0 ; + wire \dm_address[4]_i_11__0_n_0 ; + wire \dm_address[4]_i_12__0_n_0 ; + wire \dm_address[4]_i_13__0_n_0 ; + wire \dm_address[4]_i_2__0_n_0 ; + wire \dm_address[4]_i_3__0_n_0 ; + wire \dm_address[4]_i_4__0_n_0 ; + wire \dm_address[4]_i_5__0_n_0 ; + wire \dm_address[4]_i_6__0_n_0 ; + wire \dm_address[4]_i_7__0_n_0 ; + wire \dm_address[4]_i_8__0_n_0 ; + wire \dm_address[4]_i_9__0_n_0 ; + wire \dm_address[8]_i_10__0_n_0 ; + wire \dm_address[8]_i_11__0_n_0 ; + wire \dm_address[8]_i_12__0_n_0 ; + wire \dm_address[8]_i_13__0_n_0 ; + wire \dm_address[8]_i_2__0_n_0 ; + wire \dm_address[8]_i_3__0_n_0 ; + wire \dm_address[8]_i_4__0_n_0 ; + wire \dm_address[8]_i_5__0_n_0 ; + wire \dm_address[8]_i_6__0_n_0 ; + wire \dm_address[8]_i_7__0_n_0 ; + wire \dm_address[8]_i_8__0_n_0 ; + wire \dm_address[8]_i_9__0_n_0 ; + wire \dm_address_reg[0]_i_2__0_n_0 ; + wire \dm_address_reg[0]_i_2__0_n_1 ; + wire \dm_address_reg[0]_i_2__0_n_2 ; + wire \dm_address_reg[0]_i_2__0_n_3 ; + wire [3:0]\dm_address_reg[11] ; + wire \dm_address_reg[12]_i_1__0_n_1 ; + wire \dm_address_reg[12]_i_1__0_n_2 ; + wire \dm_address_reg[12]_i_1__0_n_3 ; + wire [3:0]\dm_address_reg[15] ; + wire [15:0]\dm_address_reg[15]_0 ; + wire \dm_address_reg[19] ; + wire \dm_address_reg[19]_0 ; + wire \dm_address_reg[19]_1 ; + wire \dm_address_reg[19]_2 ; + wire \dm_address_reg[23] ; + wire \dm_address_reg[23]_0 ; + wire \dm_address_reg[23]_1 ; + wire \dm_address_reg[23]_2 ; + wire \dm_address_reg[27] ; + wire \dm_address_reg[27]_0 ; + wire \dm_address_reg[27]_1 ; + wire \dm_address_reg[27]_2 ; + wire \dm_address_reg[31] ; + wire \dm_address_reg[31]_0 ; + wire \dm_address_reg[31]_1 ; + wire \dm_address_reg[31]_2 ; + wire \dm_address_reg[4]_i_1__0_n_0 ; + wire \dm_address_reg[4]_i_1__0_n_1 ; + wire \dm_address_reg[4]_i_1__0_n_2 ; + wire \dm_address_reg[4]_i_1__0_n_3 ; + wire [3:0]\dm_address_reg[7] ; + wire \dm_address_reg[8]_i_1__0_n_0 ; + wire \dm_address_reg[8]_i_1__0_n_1 ; + wire \dm_address_reg[8]_i_1__0_n_2 ; + wire \dm_address_reg[8]_i_1__0_n_3 ; + wire load_new_addr; + wire m_axi_s2mm_aclk; + wire [0:0]m_axis_s2mm_sts_tdata; + wire prmtr_update_complete; + wire [15:0]\reg_module_hsize_reg[15] ; + wire [12:0]\reg_module_vsize_reg[12] ; + wire s2mm_cdc2dmac_fsync; + wire [15:0]stride_vid; + wire video_reg_update; + wire zero_hsize_err0; + wire zero_hsize_err_i_2__0_n_0; + wire zero_hsize_err_i_3__0_n_0; + wire zero_hsize_err_i_4__0_n_0; + wire zero_vsize_err0; + wire zero_vsize_err_i_2__0_n_0; + wire zero_vsize_err_i_3__0_n_0; + + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][0] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [0]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [0]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][10] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [10]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [10]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][11] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [11]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [11]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][12] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [12]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [12]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][13] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [13]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [13]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][14] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [14]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [14]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][15] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [15]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [15]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][16] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [16]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [16]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][17] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [17]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [17]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][18] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [18]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [18]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][19] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [19]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [19]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][1] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [1]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [1]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][20] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [20]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [20]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][21] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [21]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [21]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][22] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [22]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [22]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][23] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [23]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [23]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][24] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [24]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [24]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][25] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [25]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [25]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][26] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [26]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [26]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][27] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [27]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [27]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][28] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [28]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [28]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][29] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [29]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [29]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][2] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [2]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [2]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][30] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [30]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [30]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [31]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [31]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][3] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [3]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [3]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][4] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [4]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [4]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][5] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [5]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [5]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][6] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [6]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [6]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][7] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [7]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [7]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][8] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [8]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [8]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][9] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [9]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [9]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][0] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [0]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [0]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][10] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [10]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [10]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][11] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [11]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [11]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][12] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [12]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [12]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][13] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [13]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [13]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][14] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [14]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [14]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][15] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [15]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [15]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][16] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [16]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [16]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][17] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [17]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [17]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][18] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [18]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [18]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][19] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [19]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [19]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][1] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [1]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [1]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][20] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [20]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [20]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][21] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [21]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [21]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][22] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [22]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [22]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][23] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [23]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [23]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][24] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [24]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [24]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][25] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [25]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [25]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][26] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [26]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [26]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][27] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [27]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [27]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][28] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [28]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [28]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][29] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [29]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [29]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][2] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [2]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [2]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][30] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [30]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [30]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [31]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [31]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][3] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [3]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [3]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][4] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [4]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [4]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][5] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [5]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [5]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][6] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [6]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [6]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][7] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [7]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [7]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][8] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [8]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [8]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][9] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [9]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [9]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][0] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [0]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [0]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][10] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [10]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [10]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][11] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [11]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [11]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][12] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [12]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [12]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][13] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [13]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [13]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][14] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [14]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [14]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][15] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [15]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [15]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][16] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [16]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [16]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][17] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [17]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [17]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][18] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [18]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [18]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][19] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [19]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [19]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][1] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [1]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [1]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][20] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [20]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [20]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][21] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [21]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [21]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][22] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [22]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [22]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][23] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [23]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [23]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][24] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [24]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [24]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][25] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [25]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [25]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][26] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [26]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [26]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][27] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [27]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [27]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][28] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [28]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [28]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][29] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [29]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [29]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][2] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [2]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [2]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][30] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [30]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [30]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [31]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [31]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][3] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [3]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [3]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][4] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [4]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [4]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][5] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [5]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [5]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][6] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [6]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [6]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][7] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [7]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [7]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][8] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [8]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [8]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][9] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [9]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [9]), + .R(SR)); + LUT4 #( + .INIT(16'h1001)) + \GEN_STS_GRTR_THAN_8.ovrflo_err_i_9 + (.I0(Q[2]), + .I1(Q[1]), + .I2(Q[0]), + .I3(m_axis_s2mm_sts_tdata), + .O(S)); + LUT4 #( + .INIT(16'h1001)) + \GEN_STS_GRTR_THAN_8.undrflo_err_i_9 + (.I0(Q[2]), + .I1(Q[1]), + .I2(Q[0]), + .I3(m_axis_s2mm_sts_tdata), + .O(\GEN_STS_GRTR_THAN_8.undrflo_err_reg )); + LUT4 #( + .INIT(16'hF606)) + \dm_address[0]_i_10__0 + (.I0(stride_vid[0]), + .I1(\dm_address_reg[15]_0 [0]), + .I2(load_new_addr), + .I3(\dm_address[0]_i_14__0_n_0 ), + .O(\dm_address[0]_i_10__0_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[0]_i_11__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [3]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [3]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [3]), + .O(\dm_address[0]_i_11__0_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[0]_i_12__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [2]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [2]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [2]), + .O(\dm_address[0]_i_12__0_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[0]_i_13__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [1]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [1]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [1]), + .O(\dm_address[0]_i_13__0_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[0]_i_14__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [0]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [0]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [0]), + .O(\dm_address[0]_i_14__0_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dm_address[0]_i_3__0 + (.I0(stride_vid[3]), + .I1(load_new_addr), + .O(\dm_address[0]_i_3__0_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dm_address[0]_i_4__0 + (.I0(stride_vid[2]), + .I1(load_new_addr), + .O(\dm_address[0]_i_4__0_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dm_address[0]_i_5__0 + (.I0(stride_vid[1]), + .I1(load_new_addr), + .O(\dm_address[0]_i_5__0_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dm_address[0]_i_6__0 + (.I0(stride_vid[0]), + .I1(load_new_addr), + .O(\dm_address[0]_i_6__0_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \dm_address[0]_i_7__0 + (.I0(stride_vid[3]), + .I1(\dm_address_reg[15]_0 [3]), + .I2(load_new_addr), + .I3(\dm_address[0]_i_11__0_n_0 ), + .O(\dm_address[0]_i_7__0_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \dm_address[0]_i_8__0 + (.I0(stride_vid[2]), + .I1(\dm_address_reg[15]_0 [2]), + .I2(load_new_addr), + .I3(\dm_address[0]_i_12__0_n_0 ), + .O(\dm_address[0]_i_8__0_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \dm_address[0]_i_9__0 + (.I0(stride_vid[1]), + .I1(\dm_address_reg[15]_0 [1]), + .I2(load_new_addr), + .I3(\dm_address[0]_i_13__0_n_0 ), + .O(\dm_address[0]_i_9__0_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[12]_i_10__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [15]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [15]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [15]), + .O(\dm_address[12]_i_10__0_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[12]_i_11__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [14]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [14]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [14]), + .O(\dm_address[12]_i_11__0_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[12]_i_12__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [13]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [13]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [13]), + .O(\dm_address[12]_i_12__0_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[12]_i_13__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [12]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [12]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [12]), + .O(\dm_address[12]_i_13__0_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dm_address[12]_i_2__0 + (.I0(stride_vid[15]), + .I1(load_new_addr), + .O(\dm_address[12]_i_2__0_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dm_address[12]_i_3__0 + (.I0(stride_vid[14]), + .I1(load_new_addr), + .O(\dm_address[12]_i_3__0_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dm_address[12]_i_4__0 + (.I0(stride_vid[13]), + .I1(load_new_addr), + .O(\dm_address[12]_i_4__0_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dm_address[12]_i_5__0 + (.I0(stride_vid[12]), + .I1(load_new_addr), + .O(\dm_address[12]_i_5__0_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \dm_address[12]_i_6__0 + (.I0(stride_vid[15]), + .I1(\dm_address_reg[15]_0 [15]), + .I2(load_new_addr), + .I3(\dm_address[12]_i_10__0_n_0 ), + .O(\dm_address[12]_i_6__0_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \dm_address[12]_i_7__0 + (.I0(stride_vid[14]), + .I1(\dm_address_reg[15]_0 [14]), + .I2(load_new_addr), + .I3(\dm_address[12]_i_11__0_n_0 ), + .O(\dm_address[12]_i_7__0_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \dm_address[12]_i_8__0 + (.I0(stride_vid[13]), + .I1(\dm_address_reg[15]_0 [13]), + .I2(load_new_addr), + .I3(\dm_address[12]_i_12__0_n_0 ), + .O(\dm_address[12]_i_8__0_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \dm_address[12]_i_9__0 + (.I0(stride_vid[12]), + .I1(\dm_address_reg[15]_0 [12]), + .I2(load_new_addr), + .I3(\dm_address[12]_i_13__0_n_0 ), + .O(\dm_address[12]_i_9__0_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[16]_i_6__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [19]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [19]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [19]), + .O(\dm_address_reg[19]_2 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[16]_i_7__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [18]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [18]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [18]), + .O(\dm_address_reg[19]_1 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[16]_i_8__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [17]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [17]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [17]), + .O(\dm_address_reg[19]_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[16]_i_9__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [16]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [16]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [16]), + .O(\dm_address_reg[19] )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[20]_i_6__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [23]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [23]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [23]), + .O(\dm_address_reg[23]_2 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[20]_i_7__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [22]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [22]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [22]), + .O(\dm_address_reg[23]_1 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[20]_i_8__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [21]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [21]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [21]), + .O(\dm_address_reg[23]_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[20]_i_9__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [20]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [20]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [20]), + .O(\dm_address_reg[23] )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[24]_i_6__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [27]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [27]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [27]), + .O(\dm_address_reg[27]_2 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[24]_i_7__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [26]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [26]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [26]), + .O(\dm_address_reg[27]_1 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[24]_i_8__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [25]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [25]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [25]), + .O(\dm_address_reg[27]_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[24]_i_9__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [24]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [24]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [24]), + .O(\dm_address_reg[27] )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[28]_i_6__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [31]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [31]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [31]), + .O(\dm_address_reg[31]_2 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[28]_i_7__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [30]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [30]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [30]), + .O(\dm_address_reg[31]_1 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[28]_i_8__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [29]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [29]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [29]), + .O(\dm_address_reg[31]_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[28]_i_9__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [28]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [28]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [28]), + .O(\dm_address_reg[31] )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[4]_i_10__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [7]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [7]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [7]), + .O(\dm_address[4]_i_10__0_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[4]_i_11__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [6]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [6]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [6]), + .O(\dm_address[4]_i_11__0_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[4]_i_12__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [5]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [5]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [5]), + .O(\dm_address[4]_i_12__0_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[4]_i_13__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [4]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [4]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [4]), + .O(\dm_address[4]_i_13__0_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dm_address[4]_i_2__0 + (.I0(stride_vid[7]), + .I1(load_new_addr), + .O(\dm_address[4]_i_2__0_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dm_address[4]_i_3__0 + (.I0(stride_vid[6]), + .I1(load_new_addr), + .O(\dm_address[4]_i_3__0_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dm_address[4]_i_4__0 + (.I0(stride_vid[5]), + .I1(load_new_addr), + .O(\dm_address[4]_i_4__0_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dm_address[4]_i_5__0 + (.I0(stride_vid[4]), + .I1(load_new_addr), + .O(\dm_address[4]_i_5__0_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \dm_address[4]_i_6__0 + (.I0(stride_vid[7]), + .I1(\dm_address_reg[15]_0 [7]), + .I2(load_new_addr), + .I3(\dm_address[4]_i_10__0_n_0 ), + .O(\dm_address[4]_i_6__0_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \dm_address[4]_i_7__0 + (.I0(stride_vid[6]), + .I1(\dm_address_reg[15]_0 [6]), + .I2(load_new_addr), + .I3(\dm_address[4]_i_11__0_n_0 ), + .O(\dm_address[4]_i_7__0_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \dm_address[4]_i_8__0 + (.I0(stride_vid[5]), + .I1(\dm_address_reg[15]_0 [5]), + .I2(load_new_addr), + .I3(\dm_address[4]_i_12__0_n_0 ), + .O(\dm_address[4]_i_8__0_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \dm_address[4]_i_9__0 + (.I0(stride_vid[4]), + .I1(\dm_address_reg[15]_0 [4]), + .I2(load_new_addr), + .I3(\dm_address[4]_i_13__0_n_0 ), + .O(\dm_address[4]_i_9__0_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[8]_i_10__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [11]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [11]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [11]), + .O(\dm_address[8]_i_10__0_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[8]_i_11__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [10]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [10]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [10]), + .O(\dm_address[8]_i_11__0_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[8]_i_12__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [9]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [9]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [9]), + .O(\dm_address[8]_i_12__0_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[8]_i_13__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [8]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [8]), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [8]), + .O(\dm_address[8]_i_13__0_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dm_address[8]_i_2__0 + (.I0(stride_vid[11]), + .I1(load_new_addr), + .O(\dm_address[8]_i_2__0_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dm_address[8]_i_3__0 + (.I0(stride_vid[10]), + .I1(load_new_addr), + .O(\dm_address[8]_i_3__0_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dm_address[8]_i_4__0 + (.I0(stride_vid[9]), + .I1(load_new_addr), + .O(\dm_address[8]_i_4__0_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dm_address[8]_i_5__0 + (.I0(stride_vid[8]), + .I1(load_new_addr), + .O(\dm_address[8]_i_5__0_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \dm_address[8]_i_6__0 + (.I0(stride_vid[11]), + .I1(\dm_address_reg[15]_0 [11]), + .I2(load_new_addr), + .I3(\dm_address[8]_i_10__0_n_0 ), + .O(\dm_address[8]_i_6__0_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \dm_address[8]_i_7__0 + (.I0(stride_vid[10]), + .I1(\dm_address_reg[15]_0 [10]), + .I2(load_new_addr), + .I3(\dm_address[8]_i_11__0_n_0 ), + .O(\dm_address[8]_i_7__0_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \dm_address[8]_i_8__0 + (.I0(stride_vid[9]), + .I1(\dm_address_reg[15]_0 [9]), + .I2(load_new_addr), + .I3(\dm_address[8]_i_12__0_n_0 ), + .O(\dm_address[8]_i_8__0_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \dm_address[8]_i_9__0 + (.I0(stride_vid[8]), + .I1(\dm_address_reg[15]_0 [8]), + .I2(load_new_addr), + .I3(\dm_address[8]_i_13__0_n_0 ), + .O(\dm_address[8]_i_9__0_n_0 )); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \dm_address_reg[0]_i_2__0 + (.CI(1'b0), + .CO({\dm_address_reg[0]_i_2__0_n_0 ,\dm_address_reg[0]_i_2__0_n_1 ,\dm_address_reg[0]_i_2__0_n_2 ,\dm_address_reg[0]_i_2__0_n_3 }), + .CYINIT(1'b0), + .DI({\dm_address[0]_i_3__0_n_0 ,\dm_address[0]_i_4__0_n_0 ,\dm_address[0]_i_5__0_n_0 ,\dm_address[0]_i_6__0_n_0 }), + .O(O), + .S({\dm_address[0]_i_7__0_n_0 ,\dm_address[0]_i_8__0_n_0 ,\dm_address[0]_i_9__0_n_0 ,\dm_address[0]_i_10__0_n_0 })); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \dm_address_reg[12]_i_1__0 + (.CI(\dm_address_reg[8]_i_1__0_n_0 ), + .CO({CO,\dm_address_reg[12]_i_1__0_n_1 ,\dm_address_reg[12]_i_1__0_n_2 ,\dm_address_reg[12]_i_1__0_n_3 }), + .CYINIT(1'b0), + .DI({\dm_address[12]_i_2__0_n_0 ,\dm_address[12]_i_3__0_n_0 ,\dm_address[12]_i_4__0_n_0 ,\dm_address[12]_i_5__0_n_0 }), + .O(\dm_address_reg[15] ), + .S({\dm_address[12]_i_6__0_n_0 ,\dm_address[12]_i_7__0_n_0 ,\dm_address[12]_i_8__0_n_0 ,\dm_address[12]_i_9__0_n_0 })); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \dm_address_reg[4]_i_1__0 + (.CI(\dm_address_reg[0]_i_2__0_n_0 ), + .CO({\dm_address_reg[4]_i_1__0_n_0 ,\dm_address_reg[4]_i_1__0_n_1 ,\dm_address_reg[4]_i_1__0_n_2 ,\dm_address_reg[4]_i_1__0_n_3 }), + .CYINIT(1'b0), + .DI({\dm_address[4]_i_2__0_n_0 ,\dm_address[4]_i_3__0_n_0 ,\dm_address[4]_i_4__0_n_0 ,\dm_address[4]_i_5__0_n_0 }), + .O(\dm_address_reg[7] ), + .S({\dm_address[4]_i_6__0_n_0 ,\dm_address[4]_i_7__0_n_0 ,\dm_address[4]_i_8__0_n_0 ,\dm_address[4]_i_9__0_n_0 })); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \dm_address_reg[8]_i_1__0 + (.CI(\dm_address_reg[4]_i_1__0_n_0 ), + .CO({\dm_address_reg[8]_i_1__0_n_0 ,\dm_address_reg[8]_i_1__0_n_1 ,\dm_address_reg[8]_i_1__0_n_2 ,\dm_address_reg[8]_i_1__0_n_3 }), + .CYINIT(1'b0), + .DI({\dm_address[8]_i_2__0_n_0 ,\dm_address[8]_i_3__0_n_0 ,\dm_address[8]_i_4__0_n_0 ,\dm_address[8]_i_5__0_n_0 }), + .O(\dm_address_reg[11] ), + .S({\dm_address[8]_i_6__0_n_0 ,\dm_address[8]_i_7__0_n_0 ,\dm_address[8]_i_8__0_n_0 ,\dm_address[8]_i_9__0_n_0 })); + FDRE \hsize_vid_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [0]), + .Q(Q[0]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \ptr_ref_i_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[2]), - .D(D[1]), - .Q(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] [1]), + FDRE \hsize_vid_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [10]), + .Q(Q[10]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \ptr_ref_i_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[2]), - .D(D[2]), - .Q(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] [2]), + FDRE \hsize_vid_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [11]), + .Q(Q[11]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \ptr_ref_i_reg[3] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[2]), - .D(D[3]), - .Q(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] [3]), + FDRE \hsize_vid_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [12]), + .Q(Q[12]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \ptr_ref_i_reg[4] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[2]), - .D(D[4]), - .Q(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4] [4]), + FDRE \hsize_vid_reg[13] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [13]), + .Q(Q[13]), .R(SR)); -endmodule - -(* ORIG_REF_NAME = "axi_vdma_reg_mux" *) -module Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_mux - (out, - in0); - output [31:0]out; - input [31:0]in0; - - (* DONT_TOUCH *) wire [31:0]ip2axi_rddata_int; - - assign ip2axi_rddata_int = in0[31:0]; - assign out[31:0] = ip2axi_rddata_int; -endmodule - -(* ORIG_REF_NAME = "axi_vdma_regdirect" *) -module Arty_Z7_20_axi_vdma_0_0_axi_vdma_regdirect - (p_64_out, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0] , - \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] , - \stride_vid_reg[15] , - \hsize_vid_reg[15] , - \vsize_vid_reg[12] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[1] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[2] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[13] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[14] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15] , - \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg , - SR, - \dmacr_i_reg[0] , - m_axi_mm2s_aclk, - prmry_resetn_i_reg, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] , - prmry_resetn_i_reg_0, - p_35_out, - p_23_out, - prmtr_update_complete, - halted_reg, - mm2s_axi2ip_wrce, - D); - output p_64_out; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0] ; - output [31:0]\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] ; - output [15:0]\stride_vid_reg[15] ; - output [15:0]\hsize_vid_reg[15] ; - output [12:0]\vsize_vid_reg[12] ; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[1] ; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[2] ; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3] ; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4] ; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5] ; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6] ; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7] ; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8] ; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9] ; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10] ; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11] ; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12] ; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[13] ; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[14] ; - output \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15] ; - output \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg ; - input [0:0]SR; - input \dmacr_i_reg[0] ; - input m_axi_mm2s_aclk; - input prmry_resetn_i_reg; - input [1:0]\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] ; - input prmry_resetn_i_reg_0; - input p_35_out; - input p_23_out; - input prmtr_update_complete; - input halted_reg; - input [3:0]mm2s_axi2ip_wrce; - input [31:0]D; - - wire [31:0]D; - wire [1:0]\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[13] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[14] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[1] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[2] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9] ; - wire \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg ; - wire [31:0]\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] ; - wire [0:0]SR; - wire \dmacr_i_reg[0] ; - wire halted_reg; - wire [15:0]\hsize_vid_reg[15] ; - wire m_axi_mm2s_aclk; - wire [3:0]mm2s_axi2ip_wrce; - wire p_23_out; - wire p_35_out; - wire p_63_out; - wire p_64_out; - wire prmry_resetn_i_reg; - wire prmry_resetn_i_reg_0; - wire prmtr_update_complete; - wire regdir_idle_i_i_1_n_0; - wire run_stop_d1; - wire [15:0]\stride_vid_reg[15] ; - wire [12:0]\vsize_vid_reg[12] ; - - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[0] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[0]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [0]), + FDRE \hsize_vid_reg[14] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [14]), + .Q(Q[14]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[10] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[10]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [10]), + FDRE \hsize_vid_reg[15] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [15]), + .Q(Q[15]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[11] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[11]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [11]), + FDRE \hsize_vid_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [1]), + .Q(Q[1]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[12] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[12]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [12]), + FDRE \hsize_vid_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [2]), + .Q(Q[2]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[13] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[13]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [13]), + FDRE \hsize_vid_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [3]), + .Q(Q[3]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[14] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[14]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [14]), + FDRE \hsize_vid_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [4]), + .Q(Q[4]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[15] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[15]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [15]), + FDRE \hsize_vid_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [5]), + .Q(Q[5]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[16] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[16]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [16]), + FDRE \hsize_vid_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [6]), + .Q(Q[6]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[17] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[17]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [17]), + FDRE \hsize_vid_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [7]), + .Q(Q[7]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[18] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[18]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [18]), + FDRE \hsize_vid_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [8]), + .Q(Q[8]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[19] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[19]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [19]), + FDRE \hsize_vid_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [9]), + .Q(Q[9]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[1]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [1]), + FDRE \stride_vid_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [0]), + .Q(stride_vid[0]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[20] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[20]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [20]), + FDRE \stride_vid_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [10]), + .Q(stride_vid[10]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[21] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[21]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [21]), + FDRE \stride_vid_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [11]), + .Q(stride_vid[11]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[22] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[22]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [22]), + FDRE \stride_vid_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [12]), + .Q(stride_vid[12]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[23] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[23]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [23]), + FDRE \stride_vid_reg[13] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [13]), + .Q(stride_vid[13]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[24] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[24]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [24]), + FDRE \stride_vid_reg[14] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [14]), + .Q(stride_vid[14]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[25] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[25]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [25]), + FDRE \stride_vid_reg[15] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [15]), + .Q(stride_vid[15]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[26] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[26]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [26]), + FDRE \stride_vid_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [1]), + .Q(stride_vid[1]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[27] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[27]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [27]), + FDRE \stride_vid_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [2]), + .Q(stride_vid[2]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[28] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[28]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [28]), + FDRE \stride_vid_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [3]), + .Q(stride_vid[3]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[29] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[29]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [29]), + FDRE \stride_vid_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [4]), + .Q(stride_vid[4]), + .R(SR)); + FDRE \stride_vid_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [5]), + .Q(stride_vid[5]), + .R(SR)); + FDRE \stride_vid_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [6]), + .Q(stride_vid[6]), + .R(SR)); + FDRE \stride_vid_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [7]), + .Q(stride_vid[7]), + .R(SR)); + FDRE \stride_vid_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [8]), + .Q(stride_vid[8]), + .R(SR)); + FDRE \stride_vid_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [9]), + .Q(stride_vid[9]), + .R(SR)); + LUT3 #( + .INIT(8'h8A)) + \vsize_vid[12]_i_1__0 + (.I0(prmtr_update_complete), + .I1(s2mm_cdc2dmac_fsync), + .I2(\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg ), + .O(video_reg_update)); + FDRE \vsize_vid_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\reg_module_vsize_reg[12] [0]), + .Q(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] [0]), + .R(SR)); + FDRE \vsize_vid_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\reg_module_vsize_reg[12] [10]), + .Q(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] [10]), + .R(SR)); + FDRE \vsize_vid_reg[11] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\reg_module_vsize_reg[12] [11]), + .Q(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] [11]), + .R(SR)); + FDRE \vsize_vid_reg[12] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\reg_module_vsize_reg[12] [12]), + .Q(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] [12]), + .R(SR)); + FDRE \vsize_vid_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\reg_module_vsize_reg[12] [1]), + .Q(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] [1]), + .R(SR)); + FDRE \vsize_vid_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\reg_module_vsize_reg[12] [2]), + .Q(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] [2]), + .R(SR)); + FDRE \vsize_vid_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\reg_module_vsize_reg[12] [3]), + .Q(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] [3]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[2]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [2]), + FDRE \vsize_vid_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\reg_module_vsize_reg[12] [4]), + .Q(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] [4]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[30] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[30]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [30]), + FDRE \vsize_vid_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\reg_module_vsize_reg[12] [5]), + .Q(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] [5]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[31]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [31]), + FDRE \vsize_vid_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\reg_module_vsize_reg[12] [6]), + .Q(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] [6]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[3] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[3]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [3]), + FDRE \vsize_vid_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\reg_module_vsize_reg[12] [7]), + .Q(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] [7]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[4] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[4]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [4]), + FDRE \vsize_vid_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\reg_module_vsize_reg[12] [8]), + .Q(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] [8]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[5] - (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[5]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [5]), + FDRE \vsize_vid_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(video_reg_update), + .D(\reg_module_vsize_reg[12] [9]), + .Q(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] [9]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[6] + LUT5 #( + .INIT(32'h00000002)) + zero_hsize_err_i_1__0 + (.I0(zero_hsize_err_i_2__0_n_0), + .I1(zero_hsize_err_i_3__0_n_0), + .I2(Q[11]), + .I3(Q[4]), + .I4(Q[13]), + .O(zero_hsize_err0)); + LUT6 #( + .INIT(64'h0000000000000100)) + zero_hsize_err_i_2__0 + (.I0(Q[8]), + .I1(Q[12]), + .I2(Q[7]), + .I3(load_new_addr), + .I4(Q[15]), + .I5(Q[9]), + .O(zero_hsize_err_i_2__0_n_0)); + LUT5 #( + .INIT(32'hFFFFFFFE)) + zero_hsize_err_i_3__0 + (.I0(Q[5]), + .I1(Q[1]), + .I2(Q[10]), + .I3(Q[3]), + .I4(zero_hsize_err_i_4__0_n_0), + .O(zero_hsize_err_i_3__0_n_0)); + LUT4 #( + .INIT(16'hFFFE)) + zero_hsize_err_i_4__0 + (.I0(Q[6]), + .I1(Q[14]), + .I2(Q[0]), + .I3(Q[2]), + .O(zero_hsize_err_i_4__0_n_0)); + LUT6 #( + .INIT(64'h0000000000000002)) + zero_vsize_err_i_1__0 + (.I0(zero_vsize_err_i_2__0_n_0), + .I1(zero_vsize_err_i_3__0_n_0), + .I2(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] [10]), + .I3(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] [6]), + .I4(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] [12]), + .I5(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] [7]), + .O(zero_vsize_err0)); + LUT6 #( + .INIT(64'h0000000000000004)) + zero_vsize_err_i_2__0 + (.I0(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] [0]), + .I1(load_new_addr), + .I2(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] [5]), + .I3(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] [8]), + .I4(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] [2]), + .I5(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] [4]), + .O(zero_vsize_err_i_2__0_n_0)); + LUT4 #( + .INIT(16'hFFFE)) + zero_vsize_err_i_3__0 + (.I0(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] [9]), + .I1(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] [3]), + .I2(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] [11]), + .I3(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12] [1]), + .O(zero_vsize_err_i_3__0_n_0)); +endmodule + +(* ORIG_REF_NAME = "axi_vdma_vregister" *) +module Arty_Z7_20_axi_vdma_0_0_axi_vdma_vregister_44 + (zero_vsize_err0, + Q, + zero_hsize_err0, + \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] , + \dm_address_reg[19] , + \dm_address_reg[19]_0 , + \dm_address_reg[19]_1 , + \dm_address_reg[19]_2 , + \dm_address_reg[23] , + \dm_address_reg[23]_0 , + \dm_address_reg[23]_1 , + \dm_address_reg[23]_2 , + \dm_address_reg[27] , + \dm_address_reg[27]_0 , + \dm_address_reg[27]_1 , + \dm_address_reg[27]_2 , + \dm_address_reg[31] , + \dm_address_reg[31]_0 , + \dm_address_reg[31]_1 , + \dm_address_reg[31]_2 , + O, + \dm_address_reg[7] , + \dm_address_reg[11] , + CO, + \dm_address_reg[15] , + load_new_addr, + \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] , + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg , + p_24_out, + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg , + \dm_address_reg[15]_0 , + SR, + \reg_module_vsize_reg[12] , + m_axi_mm2s_aclk, + \reg_module_hsize_reg[15] , + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] , + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] , + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] , + \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ); + output zero_vsize_err0; + output [12:0]Q; + output zero_hsize_err0; + output [15:0]\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] ; + output \dm_address_reg[19] ; + output \dm_address_reg[19]_0 ; + output \dm_address_reg[19]_1 ; + output \dm_address_reg[19]_2 ; + output \dm_address_reg[23] ; + output \dm_address_reg[23]_0 ; + output \dm_address_reg[23]_1 ; + output \dm_address_reg[23]_2 ; + output \dm_address_reg[27] ; + output \dm_address_reg[27]_0 ; + output \dm_address_reg[27]_1 ; + output \dm_address_reg[27]_2 ; + output \dm_address_reg[31] ; + output \dm_address_reg[31]_0 ; + output \dm_address_reg[31]_1 ; + output \dm_address_reg[31]_2 ; + output [3:0]O; + output [3:0]\dm_address_reg[7] ; + output [3:0]\dm_address_reg[11] ; + output [0:0]CO; + output [3:0]\dm_address_reg[15] ; + input load_new_addr; + input [1:0]\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] ; + input \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg ; + input p_24_out; + input \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg ; + input [15:0]\dm_address_reg[15]_0 ; + input [0:0]SR; + input [12:0]\reg_module_vsize_reg[12] ; + input m_axi_mm2s_aclk; + input [15:0]\reg_module_hsize_reg[15] ; + input [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] ; + input [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] ; + input [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] ; + input [15:0]\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ; + + wire [0:0]CO; + wire [15:0]\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] ; + wire [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] ; + wire [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] ; + wire [31:0]\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] ; + wire \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg ; + wire \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg ; + wire [31:0]\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 ; + wire [31:0]\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 ; + wire [31:0]\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 ; + wire [1:0]\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] ; + wire [15:0]\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ; + wire [3:0]O; + wire [12:0]Q; + wire [0:0]SR; + wire \dm_address[0]_i_10_n_0 ; + wire \dm_address[0]_i_11_n_0 ; + wire \dm_address[0]_i_12_n_0 ; + wire \dm_address[0]_i_13_n_0 ; + wire \dm_address[0]_i_14_n_0 ; + wire \dm_address[0]_i_3_n_0 ; + wire \dm_address[0]_i_4_n_0 ; + wire \dm_address[0]_i_5_n_0 ; + wire \dm_address[0]_i_6_n_0 ; + wire \dm_address[0]_i_7_n_0 ; + wire \dm_address[0]_i_8_n_0 ; + wire \dm_address[0]_i_9_n_0 ; + wire \dm_address[12]_i_10_n_0 ; + wire \dm_address[12]_i_11_n_0 ; + wire \dm_address[12]_i_12_n_0 ; + wire \dm_address[12]_i_13_n_0 ; + wire \dm_address[12]_i_2_n_0 ; + wire \dm_address[12]_i_3_n_0 ; + wire \dm_address[12]_i_4_n_0 ; + wire \dm_address[12]_i_5_n_0 ; + wire \dm_address[12]_i_6_n_0 ; + wire \dm_address[12]_i_7_n_0 ; + wire \dm_address[12]_i_8_n_0 ; + wire \dm_address[12]_i_9_n_0 ; + wire \dm_address[4]_i_10_n_0 ; + wire \dm_address[4]_i_11_n_0 ; + wire \dm_address[4]_i_12_n_0 ; + wire \dm_address[4]_i_13_n_0 ; + wire \dm_address[4]_i_2_n_0 ; + wire \dm_address[4]_i_3_n_0 ; + wire \dm_address[4]_i_4_n_0 ; + wire \dm_address[4]_i_5_n_0 ; + wire \dm_address[4]_i_6_n_0 ; + wire \dm_address[4]_i_7_n_0 ; + wire \dm_address[4]_i_8_n_0 ; + wire \dm_address[4]_i_9_n_0 ; + wire \dm_address[8]_i_10_n_0 ; + wire \dm_address[8]_i_11_n_0 ; + wire \dm_address[8]_i_12_n_0 ; + wire \dm_address[8]_i_13_n_0 ; + wire \dm_address[8]_i_2_n_0 ; + wire \dm_address[8]_i_3_n_0 ; + wire \dm_address[8]_i_4_n_0 ; + wire \dm_address[8]_i_5_n_0 ; + wire \dm_address[8]_i_6_n_0 ; + wire \dm_address[8]_i_7_n_0 ; + wire \dm_address[8]_i_8_n_0 ; + wire \dm_address[8]_i_9_n_0 ; + wire \dm_address_reg[0]_i_2_n_0 ; + wire \dm_address_reg[0]_i_2_n_1 ; + wire \dm_address_reg[0]_i_2_n_2 ; + wire \dm_address_reg[0]_i_2_n_3 ; + wire [3:0]\dm_address_reg[11] ; + wire \dm_address_reg[12]_i_1_n_1 ; + wire \dm_address_reg[12]_i_1_n_2 ; + wire \dm_address_reg[12]_i_1_n_3 ; + wire [3:0]\dm_address_reg[15] ; + wire [15:0]\dm_address_reg[15]_0 ; + wire \dm_address_reg[19] ; + wire \dm_address_reg[19]_0 ; + wire \dm_address_reg[19]_1 ; + wire \dm_address_reg[19]_2 ; + wire \dm_address_reg[23] ; + wire \dm_address_reg[23]_0 ; + wire \dm_address_reg[23]_1 ; + wire \dm_address_reg[23]_2 ; + wire \dm_address_reg[27] ; + wire \dm_address_reg[27]_0 ; + wire \dm_address_reg[27]_1 ; + wire \dm_address_reg[27]_2 ; + wire \dm_address_reg[31] ; + wire \dm_address_reg[31]_0 ; + wire \dm_address_reg[31]_1 ; + wire \dm_address_reg[31]_2 ; + wire \dm_address_reg[4]_i_1_n_0 ; + wire \dm_address_reg[4]_i_1_n_1 ; + wire \dm_address_reg[4]_i_1_n_2 ; + wire \dm_address_reg[4]_i_1_n_3 ; + wire [3:0]\dm_address_reg[7] ; + wire \dm_address_reg[8]_i_1_n_0 ; + wire \dm_address_reg[8]_i_1_n_1 ; + wire \dm_address_reg[8]_i_1_n_2 ; + wire \dm_address_reg[8]_i_1_n_3 ; + wire load_new_addr; + wire m_axi_mm2s_aclk; + wire p_24_out; + wire [15:0]\reg_module_hsize_reg[15] ; + wire [12:0]\reg_module_vsize_reg[12] ; + wire [15:0]stride_vid; + wire video_reg_update; + wire zero_hsize_err0; + wire zero_hsize_err_i_2_n_0; + wire zero_hsize_err_i_3_n_0; + wire zero_hsize_err_i_4_n_0; + wire zero_vsize_err0; + wire zero_vsize_err_i_2_n_0; + wire zero_vsize_err_i_3_n_0; + + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][0] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[6]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [6]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [0]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [0]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[7] + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][10] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[7]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [7]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [10]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [10]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[8] + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][11] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[8]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [8]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [11]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [11]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[9] + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][12] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[3]), - .D(D[9]), - .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [9]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [12]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [12]), .R(SR)); - LUT5 #( - .INIT(32'h003A0000)) - \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_i_1 - (.I0(p_63_out), - .I1(p_23_out), - .I2(prmtr_update_complete), - .I3(halted_reg), - .I4(prmry_resetn_i_reg_0), - .O(\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg )); - FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[0] + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][13] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[2]), - .D(D[0]), - .Q(\stride_vid_reg[15] [0]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [13]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [13]), .R(SR)); - FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[10] + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][14] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[2]), - .D(D[10]), - .Q(\stride_vid_reg[15] [10]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [14]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [14]), .R(SR)); - FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[11] + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][15] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[2]), - .D(D[11]), - .Q(\stride_vid_reg[15] [11]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [15]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [15]), .R(SR)); - FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[12] + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][16] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[2]), - .D(D[12]), - .Q(\stride_vid_reg[15] [12]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [16]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [16]), .R(SR)); - FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[13] + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][17] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[2]), - .D(D[13]), - .Q(\stride_vid_reg[15] [13]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [17]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [17]), .R(SR)); - FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[14] + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][18] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[2]), - .D(D[14]), - .Q(\stride_vid_reg[15] [14]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [18]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [18]), .R(SR)); - FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][19] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[2]), - .D(D[15]), - .Q(\stride_vid_reg[15] [15]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [19]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [19]), .R(SR)); - FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[1] + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][1] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[2]), - .D(D[1]), - .Q(\stride_vid_reg[15] [1]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [1]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [1]), .R(SR)); - FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[2] + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][20] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[2]), - .D(D[2]), - .Q(\stride_vid_reg[15] [2]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [20]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [20]), .R(SR)); - FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[3] + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][21] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[2]), - .D(D[3]), - .Q(\stride_vid_reg[15] [3]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [21]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [21]), .R(SR)); - FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[4] + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][22] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[2]), - .D(D[4]), - .Q(\stride_vid_reg[15] [4]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [22]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [22]), .R(SR)); - FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[5] + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][23] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[2]), - .D(D[5]), - .Q(\stride_vid_reg[15] [5]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [23]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [23]), .R(SR)); - FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[6] + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][24] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[2]), - .D(D[6]), - .Q(\stride_vid_reg[15] [6]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [24]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [24]), .R(SR)); - FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[7] + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][25] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[2]), - .D(D[7]), - .Q(\stride_vid_reg[15] [7]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [25]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [25]), .R(SR)); - FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[8] + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][26] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[2]), - .D(D[8]), - .Q(\stride_vid_reg[15] [8]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [26]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [26]), .R(SR)); - FDRE \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[9] + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][27] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[2]), - .D(D[9]), - .Q(\stride_vid_reg[15] [9]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [27]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [27]), .R(SR)); - LUT5 #( - .INIT(32'hAFC0A0C0)) - ip2axi_rddata_int_inferred_i_65 - (.I0(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [15]), - .I1(\stride_vid_reg[15] [15]), - .I2(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [1]), - .I3(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [0]), - .I4(\hsize_vid_reg[15] [15]), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15] )); - LUT5 #( - .INIT(32'hAFC0A0C0)) - ip2axi_rddata_int_inferred_i_67 - (.I0(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [14]), - .I1(\stride_vid_reg[15] [14]), - .I2(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [1]), - .I3(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [0]), - .I4(\hsize_vid_reg[15] [14]), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[14] )); - LUT5 #( - .INIT(32'hAFC0A0C0)) - ip2axi_rddata_int_inferred_i_69 - (.I0(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [13]), - .I1(\stride_vid_reg[15] [13]), - .I2(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [1]), - .I3(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [0]), - .I4(\hsize_vid_reg[15] [13]), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[13] )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - ip2axi_rddata_int_inferred_i_71 - (.I0(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [12]), - .I1(\stride_vid_reg[15] [12]), - .I2(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [1]), - .I3(\hsize_vid_reg[15] [12]), - .I4(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [0]), - .I5(\vsize_vid_reg[12] [12]), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12] )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - ip2axi_rddata_int_inferred_i_73 - (.I0(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [11]), - .I1(\stride_vid_reg[15] [11]), - .I2(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [1]), - .I3(\hsize_vid_reg[15] [11]), - .I4(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [0]), - .I5(\vsize_vid_reg[12] [11]), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11] )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - ip2axi_rddata_int_inferred_i_74 - (.I0(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [10]), - .I1(\stride_vid_reg[15] [10]), - .I2(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [1]), - .I3(\hsize_vid_reg[15] [10]), - .I4(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [0]), - .I5(\vsize_vid_reg[12] [10]), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10] )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - ip2axi_rddata_int_inferred_i_75 - (.I0(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [9]), - .I1(\stride_vid_reg[15] [9]), - .I2(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [1]), - .I3(\hsize_vid_reg[15] [9]), - .I4(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [0]), - .I5(\vsize_vid_reg[12] [9]), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9] )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - ip2axi_rddata_int_inferred_i_76 - (.I0(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [8]), - .I1(\stride_vid_reg[15] [8]), - .I2(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [1]), - .I3(\hsize_vid_reg[15] [8]), - .I4(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [0]), - .I5(\vsize_vid_reg[12] [8]), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8] )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - ip2axi_rddata_int_inferred_i_77 - (.I0(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [7]), - .I1(\stride_vid_reg[15] [7]), - .I2(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [1]), - .I3(\hsize_vid_reg[15] [7]), - .I4(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [0]), - .I5(\vsize_vid_reg[12] [7]), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7] )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - ip2axi_rddata_int_inferred_i_78 - (.I0(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [6]), - .I1(\stride_vid_reg[15] [6]), - .I2(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [1]), - .I3(\hsize_vid_reg[15] [6]), - .I4(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [0]), - .I5(\vsize_vid_reg[12] [6]), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6] )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - ip2axi_rddata_int_inferred_i_80 - (.I0(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [5]), - .I1(\stride_vid_reg[15] [5]), - .I2(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [1]), - .I3(\hsize_vid_reg[15] [5]), - .I4(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [0]), - .I5(\vsize_vid_reg[12] [5]), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5] )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - ip2axi_rddata_int_inferred_i_82 - (.I0(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [4]), - .I1(\stride_vid_reg[15] [4]), - .I2(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [1]), - .I3(\hsize_vid_reg[15] [4]), - .I4(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [0]), - .I5(\vsize_vid_reg[12] [4]), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4] )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - ip2axi_rddata_int_inferred_i_84 - (.I0(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [3]), - .I1(\stride_vid_reg[15] [3]), - .I2(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [1]), - .I3(\hsize_vid_reg[15] [3]), - .I4(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [0]), - .I5(\vsize_vid_reg[12] [3]), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3] )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - ip2axi_rddata_int_inferred_i_85 - (.I0(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [2]), - .I1(\stride_vid_reg[15] [2]), - .I2(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [1]), - .I3(\hsize_vid_reg[15] [2]), - .I4(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [0]), - .I5(\vsize_vid_reg[12] [2]), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[2] )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - ip2axi_rddata_int_inferred_i_87 - (.I0(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [1]), - .I1(\stride_vid_reg[15] [1]), - .I2(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [1]), - .I3(\hsize_vid_reg[15] [1]), - .I4(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [0]), - .I5(\vsize_vid_reg[12] [1]), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[1] )); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - ip2axi_rddata_int_inferred_i_89 - (.I0(\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] [0]), - .I1(\stride_vid_reg[15] [0]), - .I2(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [1]), - .I3(\hsize_vid_reg[15] [0]), - .I4(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3] [0]), - .I5(\vsize_vid_reg[12] [0]), - .O(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0] )); - FDRE #( - .INIT(1'b0)) - prmtr_updt_complete_i_reg + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][28] (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(prmry_resetn_i_reg), - .Q(p_63_out), - .R(1'b0)); - FDRE \reg_module_hsize_reg[0] + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [28]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [28]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][29] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[1]), - .D(D[0]), - .Q(\hsize_vid_reg[15] [0]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [29]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [29]), .R(SR)); - FDRE \reg_module_hsize_reg[10] + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][2] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[1]), - .D(D[10]), - .Q(\hsize_vid_reg[15] [10]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [2]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [2]), .R(SR)); - FDRE \reg_module_hsize_reg[11] + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][30] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[1]), - .D(D[11]), - .Q(\hsize_vid_reg[15] [11]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [30]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [30]), .R(SR)); - FDRE \reg_module_hsize_reg[12] + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[1]), - .D(D[12]), - .Q(\hsize_vid_reg[15] [12]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [31]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [31]), .R(SR)); - FDRE \reg_module_hsize_reg[13] + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][3] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[1]), - .D(D[13]), - .Q(\hsize_vid_reg[15] [13]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [3]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [3]), .R(SR)); - FDRE \reg_module_hsize_reg[14] + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][4] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[1]), - .D(D[14]), - .Q(\hsize_vid_reg[15] [14]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [4]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [4]), .R(SR)); - FDRE \reg_module_hsize_reg[15] + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][5] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[1]), - .D(D[15]), - .Q(\hsize_vid_reg[15] [15]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [5]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [5]), .R(SR)); - FDRE \reg_module_hsize_reg[1] + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][6] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[1]), - .D(D[1]), - .Q(\hsize_vid_reg[15] [1]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [6]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [6]), .R(SR)); - FDRE \reg_module_hsize_reg[2] + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][7] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[1]), - .D(D[2]), - .Q(\hsize_vid_reg[15] [2]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [7]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [7]), .R(SR)); - FDRE \reg_module_hsize_reg[3] + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][8] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[1]), - .D(D[3]), - .Q(\hsize_vid_reg[15] [3]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [8]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [8]), .R(SR)); - FDRE \reg_module_hsize_reg[4] + FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][9] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[1]), - .D(D[4]), - .Q(\hsize_vid_reg[15] [4]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31] [9]), + .Q(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [9]), .R(SR)); - FDRE \reg_module_hsize_reg[5] + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][0] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[1]), - .D(D[5]), - .Q(\hsize_vid_reg[15] [5]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [0]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [0]), .R(SR)); - FDRE \reg_module_hsize_reg[6] + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][10] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[1]), - .D(D[6]), - .Q(\hsize_vid_reg[15] [6]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [10]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [10]), .R(SR)); - FDRE \reg_module_hsize_reg[7] + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][11] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[1]), - .D(D[7]), - .Q(\hsize_vid_reg[15] [7]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [11]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [11]), .R(SR)); - FDRE \reg_module_hsize_reg[8] + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][12] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[1]), - .D(D[8]), - .Q(\hsize_vid_reg[15] [8]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [12]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [12]), .R(SR)); - FDRE \reg_module_hsize_reg[9] + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][13] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[1]), - .D(D[9]), - .Q(\hsize_vid_reg[15] [9]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [13]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [13]), .R(SR)); - FDRE \reg_module_vsize_reg[0] + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][14] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[0]), - .Q(\vsize_vid_reg[12] [0]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [14]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [14]), .R(SR)); - FDRE \reg_module_vsize_reg[10] + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][15] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[10]), - .Q(\vsize_vid_reg[12] [10]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [15]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [15]), .R(SR)); - FDRE \reg_module_vsize_reg[11] + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][16] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[11]), - .Q(\vsize_vid_reg[12] [11]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [16]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [16]), .R(SR)); - FDRE \reg_module_vsize_reg[12] + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][17] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[12]), - .Q(\vsize_vid_reg[12] [12]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [17]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [17]), .R(SR)); - FDRE \reg_module_vsize_reg[1] + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][18] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[1]), - .Q(\vsize_vid_reg[12] [1]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [18]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [18]), .R(SR)); - FDRE \reg_module_vsize_reg[2] + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][19] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[2]), - .Q(\vsize_vid_reg[12] [2]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [19]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [19]), .R(SR)); - FDRE \reg_module_vsize_reg[3] + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][1] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[3]), - .Q(\vsize_vid_reg[12] [3]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [1]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [1]), .R(SR)); - FDRE \reg_module_vsize_reg[4] + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][20] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[4]), - .Q(\vsize_vid_reg[12] [4]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [20]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [20]), .R(SR)); - FDRE \reg_module_vsize_reg[5] + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][21] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[5]), - .Q(\vsize_vid_reg[12] [5]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [21]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [21]), .R(SR)); - FDRE \reg_module_vsize_reg[6] + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][22] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[6]), - .Q(\vsize_vid_reg[12] [6]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [22]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [22]), .R(SR)); - FDRE \reg_module_vsize_reg[7] + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][23] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[7]), - .Q(\vsize_vid_reg[12] [7]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [23]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [23]), .R(SR)); - FDRE \reg_module_vsize_reg[8] + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][24] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[8]), - .Q(\vsize_vid_reg[12] [8]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [24]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [24]), .R(SR)); - FDRE \reg_module_vsize_reg[9] + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][25] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[9]), - .Q(\vsize_vid_reg[12] [9]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [25]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [25]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][26] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [26]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [26]), .R(SR)); - LUT6 #( - .INIT(64'hFFFFFFFFEE0EFFFF)) - regdir_idle_i_i_1 - (.I0(p_64_out), - .I1(p_63_out), - .I2(\dmacr_i_reg[0] ), - .I3(run_stop_d1), - .I4(prmry_resetn_i_reg_0), - .I5(p_35_out), - .O(regdir_idle_i_i_1_n_0)); - FDRE #( - .INIT(1'b0)) - regdir_idle_i_reg + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][27] (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(regdir_idle_i_i_1_n_0), - .Q(p_64_out), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - run_stop_d1_reg + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [27]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [27]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][28] (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\dmacr_i_reg[0] ), - .Q(run_stop_d1), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [28]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [28]), .R(SR)); -endmodule - -(* ORIG_REF_NAME = "axi_vdma_register" *) -module Arty_Z7_20_axi_vdma_0_0_axi_vdma_register - (run_stop_d1_reg, - p_68_out, - err_d1_reg_0, - ioc_irq_reg_0, - dly_irq_reg_0, - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] , - \s_axis_cmd_tdata_reg[63] , - err_d1_reg_1, - err_d1_reg_2, - p_75_out, - s_soft_reset_i0, - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] , - ch1_disable_delay2_out, - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0] , - p_6_out__1, - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from , - stop_i, - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6] , - ch1_delay_zero__6, - err_irq_reg_0, - different_delay, - different_thresh, - \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4] , - E, - datamover_idle_reg, - \s_axis_cmd_tdata_reg[63]_0 , - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] , - m_axi_mm2s_aclk, - SR, - mm2s_axi2ip_wrce, - D, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7]_0 , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12] , - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13] , - \dmacr_i_reg[2]_0 , - reset_counts_reg_0, - halted_clr_reg, - slverr_i_reg, - decerr_i_reg, - mm2s_halt_cmplt, - halt_reset, - prmry_in, - p_17_out, - ch1_delay_cnt_en, - p_10_out, - ch1_ioc_irq_set_i__0, - Q, - p_49_out, - p_44_out, - mm2s_dly_irq_set, - mm2s_halt, - dma_err, - \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg , - p_0_out, - p_46_out, - mask_fsync_out_i, - prmry_resetn_i_reg, - p_35_out, - mm2s_ioc_irq_set, - initial_frame, - datamover_idle, - p_23_out, - prmry_resetn_i_reg_0, - \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0 ); - output run_stop_d1_reg; - output [24:0]p_68_out; - output err_d1_reg_0; - output ioc_irq_reg_0; - output dly_irq_reg_0; - output \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] ; - output \s_axis_cmd_tdata_reg[63] ; - output err_d1_reg_1; - output err_d1_reg_2; - output p_75_out; - output s_soft_reset_i0; - output [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] ; - output ch1_disable_delay2_out; - output [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0] ; - output p_6_out__1; - output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ; - output stop_i; - output [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6] ; - output ch1_delay_zero__6; - output err_irq_reg_0; - output different_delay; - output different_thresh; - output [0:0]\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4] ; - output [0:0]E; - output datamover_idle_reg; - output [0:0]\s_axis_cmd_tdata_reg[63]_0 ; - output [4:0]\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] ; - input m_axi_mm2s_aclk; - input [0:0]SR; - input [1:0]mm2s_axi2ip_wrce; - input [24:0]D; - input \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7] ; - input \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7]_0 ; - input \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] ; - input \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12] ; - input \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13] ; - input \dmacr_i_reg[2]_0 ; - input reset_counts_reg_0; - input halted_clr_reg; - input slverr_i_reg; - input decerr_i_reg; - input mm2s_halt_cmplt; - input halt_reset; - input prmry_in; - input p_17_out; - input ch1_delay_cnt_en; - input p_10_out; - input ch1_ioc_irq_set_i__0; - input [0:0]Q; - input p_49_out; - input p_44_out; - input mm2s_dly_irq_set; - input mm2s_halt; - input dma_err; - input \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg ; - input p_0_out; - input p_46_out; - input mask_fsync_out_i; - input prmry_resetn_i_reg; - input p_35_out; - input mm2s_ioc_irq_set; - input initial_frame; - input datamover_idle; - input p_23_out; - input [0:0]prmry_resetn_i_reg_0; - input [4:0]\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0 ; - - wire [24:0]D; - wire [0:0]E; - wire \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_3_n_0 ; - wire \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_4_n_0 ; - wire \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_3_n_0 ; - wire \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_4_n_0 ; - wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ; - wire \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg ; - wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_3_n_0 ; - wire [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6] ; - wire [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] ; - wire \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_4_n_0 ; - wire [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0] ; - wire \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7]_0 ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] ; - wire [4:0]\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] ; - wire [0:0]\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4] ; - wire [4:0]\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0 ; - wire [0:0]Q; - wire [0:0]SR; - wire ch1_delay_cnt_en; - wire ch1_delay_zero__6; - wire ch1_disable_delay2_out; - wire ch1_ioc_irq_set_i__0; - wire datamover_idle; - wire datamover_idle_reg; - wire decerr_i_reg; - wire different_delay; - wire different_thresh; - wire dly_irq_reg_0; - wire dma_err; - wire [0:0]dmacr_i; - wire \dmacr_i_reg[2]_0 ; - wire err; - wire err_d1; - wire err_d1_reg_0; - wire err_d1_reg_1; - wire err_d1_reg_2; - wire err_irq_i_1_n_0; - wire err_irq_reg_0; - wire halt_reset; - wire halted_clr_reg; - wire initial_frame; - wire introut01_out; - wire introut_i_1_n_0; - wire ioc_irq_reg_0; - wire irqdelay_wren_i; - wire irqthresh_wren_i; - wire m_axi_mm2s_aclk; - wire mask_fsync_out_i; - wire [1:0]mm2s_axi2ip_wrce; - wire mm2s_dly_irq_set; - wire mm2s_halt; - wire mm2s_halt_cmplt; - wire mm2s_ioc_irq_set; - wire p_0_out; - wire p_10_out; - wire p_16_in; - wire p_17_out; - wire p_1_in; - wire p_23_out; - wire p_35_out; - wire p_44_out; - wire p_46_out; - wire p_49_out; - wire [24:0]p_68_out; - wire p_6_out__1; - wire p_75_out; - wire prmry_in; - wire prmry_resetn_i_reg; - wire [0:0]prmry_resetn_i_reg_0; - wire reset_counts_reg_0; - wire run_stop_d1_reg; - wire \s_axis_cmd_tdata_reg[63] ; - wire [0:0]\s_axis_cmd_tdata_reg[63]_0 ; - wire s_soft_reset_i0; - wire slverr_i_reg; - wire stop_i; - - FDRE #( - .INIT(1'b0)) - \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[24] + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][29] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[17]), - .Q(p_68_out[17]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [29]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [29]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[25] + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][2] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[18]), - .Q(p_68_out[18]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [2]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [2]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[26] + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][30] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[19]), - .Q(p_68_out[19]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [30]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [30]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[27] + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[20]), - .Q(p_68_out[20]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [31]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [31]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[28] + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][3] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[21]), - .Q(p_68_out[21]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [3]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [3]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[29] + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][4] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[22]), - .Q(p_68_out[22]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [4]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [4]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[30] + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][5] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[23]), - .Q(p_68_out[23]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [5]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [5]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31] + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][6] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[24]), - .Q(p_68_out[24]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [6]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [6]), .R(SR)); - LUT6 #( - .INIT(64'hFFFFFFFFFFFF6FF6)) - \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_2 - (.I0(D[24]), - .I1(p_68_out[24]), - .I2(D[23]), - .I3(p_68_out[23]), - .I4(\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_3_n_0 ), - .I5(\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_4_n_0 ), - .O(different_delay)); - LUT6 #( - .INIT(64'h6FF6FFFFFFFF6FF6)) - \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_3 - (.I0(p_68_out[20]), - .I1(D[20]), - .I2(D[22]), - .I3(p_68_out[22]), - .I4(D[21]), - .I5(p_68_out[21]), - .O(\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_3_n_0 )); - LUT6 #( - .INIT(64'h6FF6FFFFFFFF6FF6)) - \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_4 - (.I0(p_68_out[17]), - .I1(D[17]), - .I2(D[19]), - .I3(p_68_out[19]), - .I4(D[18]), - .I5(p_68_out[18]), - .O(\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_4_n_0 )); - FDRE #( - .INIT(1'b0)) - \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][7] (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7] ), - .Q(irqdelay_wren_i), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [7]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [7]), .R(SR)); - FDSE #( - .INIT(1'b0)) - \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[16] + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][8] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[9]), - .Q(p_68_out[9]), - .S(prmry_resetn_i_reg_0)); - FDRE #( - .INIT(1'b0)) - \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[17] + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [8]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [8]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[1].start_address_vid_reg[1][9] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[10]), - .Q(p_68_out[10]), - .R(prmry_resetn_i_reg_0)); - FDRE #( - .INIT(1'b0)) - \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[18] + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31] [9]), + .Q(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [9]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][0] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[11]), - .Q(p_68_out[11]), - .R(prmry_resetn_i_reg_0)); - FDRE #( - .INIT(1'b0)) - \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[19] + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [0]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [0]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][10] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[12]), - .Q(p_68_out[12]), - .R(prmry_resetn_i_reg_0)); - FDRE #( - .INIT(1'b0)) - \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[20] + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [10]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [10]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][11] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[13]), - .Q(p_68_out[13]), - .R(prmry_resetn_i_reg_0)); - FDRE #( - .INIT(1'b0)) - \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [11]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [11]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][12] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[14]), - .Q(p_68_out[14]), - .R(prmry_resetn_i_reg_0)); - FDRE #( - .INIT(1'b0)) - \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[22] + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [12]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [12]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][13] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[15]), - .Q(p_68_out[15]), - .R(prmry_resetn_i_reg_0)); - FDRE #( - .INIT(1'b0)) - \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[23] + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [13]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [13]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][14] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[16]), - .Q(p_68_out[16]), - .R(prmry_resetn_i_reg_0)); - LUT6 #( - .INIT(64'hFFFFFFFFFFFF6FF6)) - \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_2 - (.I0(D[16]), - .I1(p_68_out[16]), - .I2(D[15]), - .I3(p_68_out[15]), - .I4(\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_3_n_0 ), - .I5(\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_4_n_0 ), - .O(different_thresh)); - LUT6 #( - .INIT(64'h6FF6FFFFFFFF6FF6)) - \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_3 - (.I0(p_68_out[12]), - .I1(D[12]), - .I2(D[14]), - .I3(p_68_out[14]), - .I4(D[13]), - .I5(p_68_out[13]), - .O(\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_3_n_0 )); - LUT6 #( - .INIT(64'h6FF6FFFFFFFF6FF6)) - \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_4 - (.I0(p_68_out[9]), - .I1(D[9]), - .I2(D[11]), - .I3(p_68_out[11]), - .I4(D[10]), - .I5(p_68_out[10]), - .O(\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_4_n_0 )); - FDRE #( - .INIT(1'b0)) - \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [14]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [14]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][15] (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7]_0 ), - .Q(irqthresh_wren_i), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [15]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [15]), .R(SR)); - LUT6 #( - .INIT(64'hFFFFFEFFFEFFFEFF)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_4 - (.I0(mm2s_halt), - .I1(p_68_out[1]), - .I2(dma_err), - .I3(run_stop_d1_reg), - .I4(\GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg ), - .I5(p_0_out), - .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from )); - (* SOFT_HLUTNM = "soft_lutpair35" *) - LUT4 #( - .INIT(16'hFFFD)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_1 - (.I0(ch1_delay_cnt_en), - .I1(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_3_n_0 ), - .I2(ch1_disable_delay2_out), - .I3(p_17_out), - .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6] )); - (* SOFT_HLUTNM = "soft_lutpair36" *) - LUT4 #( - .INIT(16'hFEFF)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_3 - (.I0(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] ), - .I1(irqdelay_wren_i), - .I2(p_23_out), - .I3(prmry_resetn_i_reg), - .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_3_n_0 )); - LUT6 #( - .INIT(64'hFFFFFFFFFFFFFFEF)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_4 - (.I0(mm2s_dly_irq_set), - .I1(ch1_delay_zero__6), - .I2(p_46_out), - .I3(mask_fsync_out_i), - .I4(\s_axis_cmd_tdata_reg[63] ), - .I5(dly_irq_reg_0), - .O(ch1_disable_delay2_out)); - (* SOFT_HLUTNM = "soft_lutpair35" *) - LUT5 #( - .INIT(32'hFFFFFEFF)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_1 - (.I0(p_17_out), - .I1(ch1_disable_delay2_out), - .I2(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_3_n_0 ), - .I3(ch1_delay_cnt_en), - .I4(p_10_out), - .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0] )); - LUT5 #( - .INIT(32'h00000001)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_2 - (.I0(p_68_out[22]), - .I1(p_68_out[21]), - .I2(p_68_out[23]), - .I3(p_68_out[24]), - .I4(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_4_n_0 ), - .O(ch1_delay_zero__6)); - LUT4 #( - .INIT(16'hFFFE)) - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_4 - (.I0(p_68_out[19]), - .I1(p_68_out[20]), - .I2(p_68_out[17]), - .I3(p_68_out[18]), - .O(\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_4_n_0 )); - LUT4 #( - .INIT(16'hAA8B)) - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[0]_i_1 - (.I0(p_68_out[9]), - .I1(ch1_ioc_irq_set_i__0), - .I2(Q), - .I3(p_6_out__1), - .O(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0] )); - LUT5 #( - .INIT(32'hFFFFFFF8)) - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_2 - (.I0(p_68_out[6]), - .I1(mm2s_dly_irq_set), - .I2(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] ), - .I3(irqthresh_wren_i), - .I4(p_49_out), - .O(E)); - LUT6 #( - .INIT(64'hFFFFFFF2FFF2FFF2)) - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_6 - (.I0(p_49_out), - .I1(p_44_out), - .I2(irqthresh_wren_i), - .I3(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] ), - .I4(mm2s_dly_irq_set), - .I5(p_68_out[6]), - .O(p_6_out__1)); - FDRE #( - .INIT(1'b0)) - \GEN_NOSYNCEN_BIT.dmacr_i_reg[15] + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][16] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[8]), - .Q(p_68_out[8]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [16]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [16]), .R(SR)); - LUT4 #( - .INIT(16'hDFDD)) - \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_1 - (.I0(prmry_resetn_i_reg), - .I1(\s_axis_cmd_tdata_reg[63] ), - .I2(initial_frame), - .I3(p_68_out[0]), - .O(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4] )); - LUT3 #( - .INIT(8'h01)) - \MM2S_ERR_FOR_IRQ.frm_store_i[4]_i_1 - (.I0(err_d1_reg_2), - .I1(err_d1_reg_0), - .I2(err_d1_reg_1), - .O(p_1_in)); - FDRE #( - .INIT(1'b0)) - \MM2S_ERR_FOR_IRQ.frm_store_i_reg[0] + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][17] (.C(m_axi_mm2s_aclk), - .CE(p_1_in), - .D(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0 [0]), - .Q(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] [0]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [17]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [17]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \MM2S_ERR_FOR_IRQ.frm_store_i_reg[1] + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][18] (.C(m_axi_mm2s_aclk), - .CE(p_1_in), - .D(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0 [1]), - .Q(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] [1]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [18]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [18]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \MM2S_ERR_FOR_IRQ.frm_store_i_reg[2] + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][19] (.C(m_axi_mm2s_aclk), - .CE(p_1_in), - .D(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0 [2]), - .Q(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] [2]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [19]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [19]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \MM2S_ERR_FOR_IRQ.frm_store_i_reg[3] + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][1] (.C(m_axi_mm2s_aclk), - .CE(p_1_in), - .D(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0 [3]), - .Q(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] [3]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [1]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [1]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \MM2S_ERR_FOR_IRQ.frm_store_i_reg[4] + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][20] (.C(m_axi_mm2s_aclk), - .CE(p_1_in), - .D(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0 [4]), - .Q(\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4] [4]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [20]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [20]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \M_GEN_DMACR_REGISTER.dmacr_i_reg[12] + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][21] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[5]), - .Q(p_68_out[5]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [21]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [21]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \M_GEN_DMACR_REGISTER.dmacr_i_reg[13] + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][22] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[6]), - .Q(p_68_out[6]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [22]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [22]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \M_GEN_DMACR_REGISTER.dmacr_i_reg[14] + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][23] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[7]), - .Q(p_68_out[7]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [23]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [23]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \M_GEN_DMACR_REGISTER.dmacr_i_reg[4] + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][24] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[2]), - .Q(p_68_out[2]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [24]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [24]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \M_GEN_DMACR_REGISTER.dmacr_i_reg[5] + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][25] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[3]), - .Q(p_68_out[3]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [25]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [25]), .R(SR)); - FDRE #( - .INIT(1'b0)) - \M_GEN_DMACR_REGISTER.dmacr_i_reg[6] + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][26] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[4]), - .Q(p_68_out[4]), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [26]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [26]), .R(SR)); - LUT4 #( - .INIT(16'hF5C0)) - datamover_idle_i_1 - (.I0(run_stop_d1_reg), - .I1(mm2s_halt_cmplt), - .I2(mm2s_halt), - .I3(datamover_idle), - .O(datamover_idle_reg)); - FDRE #( - .INIT(1'b0)) - dly_irq_reg + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][27] (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13] ), - .Q(dly_irq_reg_0), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [27]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [27]), .R(SR)); - FDRE #( - .INIT(1'b0)) - dma_decerr_reg + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][28] (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(decerr_i_reg), - .Q(err_d1_reg_2), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [28]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [28]), .R(SR)); - FDRE #( - .INIT(1'b0)) - dma_interr_reg + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][29] (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] ), - .Q(err_d1_reg_0), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [29]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [29]), .R(SR)); - FDRE #( - .INIT(1'b0)) - dma_slverr_reg + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][2] (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(slverr_i_reg), - .Q(err_d1_reg_1), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [2]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [2]), .R(SR)); - LUT4 #( - .INIT(16'hA808)) - \dmacr_i[0]_i_1 - (.I0(p_16_in), - .I1(run_stop_d1_reg), - .I2(mm2s_axi2ip_wrce[0]), - .I3(D[0]), - .O(dmacr_i)); - LUT5 #( - .INIT(32'h00000222)) - \dmacr_i[0]_i_2 - (.I0(prmry_resetn_i_reg), - .I1(p_35_out), - .I2(p_68_out[2]), - .I3(mm2s_ioc_irq_set), - .I4(p_68_out[1]), - .O(p_16_in)); - FDRE #( - .INIT(1'b0)) - \dmacr_i_reg[0] + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][30] (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(dmacr_i), - .Q(run_stop_d1_reg), - .R(1'b0)); - FDSE #( - .INIT(1'b0)) - \dmacr_i_reg[1] + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [30]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [30]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31] (.C(m_axi_mm2s_aclk), - .CE(mm2s_axi2ip_wrce[0]), - .D(D[1]), - .Q(p_68_out[0]), - .S(SR)); - FDRE #( - .INIT(1'b0)) - \dmacr_i_reg[2] + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [31]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [31]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][3] (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\dmacr_i_reg[2]_0 ), - .Q(p_68_out[1]), - .R(1'b0)); - LUT3 #( - .INIT(8'hFE)) - err_d1_i_1 - (.I0(err_d1_reg_1), - .I1(err_d1_reg_0), - .I2(err_d1_reg_2), - .O(err)); - FDRE #( - .INIT(1'b0)) - err_d1_reg + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [3]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [3]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][4] (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(err), - .Q(err_d1), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [4]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [4]), .R(SR)); - LUT5 #( - .INIT(32'h77F700F0)) - err_irq_i_1 - (.I0(D[7]), - .I1(mm2s_axi2ip_wrce[1]), - .I2(err), - .I3(err_d1), - .I4(err_irq_reg_0), - .O(err_irq_i_1_n_0)); - FDRE #( - .INIT(1'b0)) - err_irq_reg + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][5] (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(err_irq_i_1_n_0), - .Q(err_irq_reg_0), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [5]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [5]), .R(SR)); - FDRE #( - .INIT(1'b0)) - halted_reg + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][6] (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(halted_clr_reg), - .Q(\s_axis_cmd_tdata_reg[63] ), - .R(1'b0)); - LUT3 #( - .INIT(8'h08)) - introut_i_1 - (.I0(introut01_out), - .I1(prmry_resetn_i_reg), - .I2(p_68_out[1]), - .O(introut_i_1_n_0)); - LUT6 #( - .INIT(64'hFFFFF888F888F888)) - introut_i_2 - (.I0(p_68_out[7]), - .I1(err_irq_reg_0), - .I2(dly_irq_reg_0), - .I3(p_68_out[6]), - .I4(ioc_irq_reg_0), - .I5(p_68_out[5]), - .O(introut01_out)); - FDRE introut_reg + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [6]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [6]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][7] (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(introut_i_1_n_0), - .Q(p_75_out), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - ioc_irq_reg + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [7]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [7]), + .R(SR)); + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][8] (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12] ), - .Q(ioc_irq_reg_0), + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [8]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [8]), .R(SR)); - FDRE #( - .INIT(1'b0)) - reset_counts_reg + FDRE \GEN_START_ADDR_REG[2].start_address_vid_reg[2][9] (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(reset_counts_reg_0), - .Q(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7] ), - .R(1'b0)); - (* SOFT_HLUTNM = "soft_lutpair36" *) + .CE(video_reg_update), + .D(\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31] [9]), + .Q(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [9]), + .R(SR)); + LUT4 #( + .INIT(16'hF606)) + \dm_address[0]_i_10 + (.I0(stride_vid[0]), + .I1(\dm_address_reg[15]_0 [0]), + .I2(load_new_addr), + .I3(\dm_address[0]_i_14_n_0 ), + .O(\dm_address[0]_i_10_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[0]_i_11 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [3]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [3]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [3]), + .O(\dm_address[0]_i_11_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[0]_i_12 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [2]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [2]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [2]), + .O(\dm_address[0]_i_12_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[0]_i_13 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [1]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [1]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [1]), + .O(\dm_address[0]_i_13_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[0]_i_14 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [0]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [0]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [0]), + .O(\dm_address[0]_i_14_n_0 )); LUT2 #( - .INIT(4'hB)) - \s_axis_cmd_tdata[63]_i_1 - (.I0(\s_axis_cmd_tdata_reg[63] ), - .I1(prmry_resetn_i_reg), - .O(\s_axis_cmd_tdata_reg[63]_0 )); - (* SOFT_HLUTNM = "soft_lutpair37" *) + .INIT(4'h2)) + \dm_address[0]_i_3 + (.I0(stride_vid[3]), + .I1(load_new_addr), + .O(\dm_address[0]_i_3_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dm_address[0]_i_4 + (.I0(stride_vid[2]), + .I1(load_new_addr), + .O(\dm_address[0]_i_4_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dm_address[0]_i_5 + (.I0(stride_vid[1]), + .I1(load_new_addr), + .O(\dm_address[0]_i_5_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dm_address[0]_i_6 + (.I0(stride_vid[0]), + .I1(load_new_addr), + .O(\dm_address[0]_i_6_n_0 )); LUT4 #( - .INIT(16'hA800)) - s_soft_reset_i_i_1 - (.I0(p_68_out[1]), - .I1(mm2s_halt_cmplt), - .I2(halt_reset), - .I3(prmry_in), - .O(s_soft_reset_i0)); - (* SOFT_HLUTNM = "soft_lutpair37" *) + .INIT(16'hF606)) + \dm_address[0]_i_7 + (.I0(stride_vid[3]), + .I1(\dm_address_reg[15]_0 [3]), + .I2(load_new_addr), + .I3(\dm_address[0]_i_11_n_0 ), + .O(\dm_address[0]_i_7_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \dm_address[0]_i_8 + (.I0(stride_vid[2]), + .I1(\dm_address_reg[15]_0 [2]), + .I2(load_new_addr), + .I3(\dm_address[0]_i_12_n_0 ), + .O(\dm_address[0]_i_8_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \dm_address[0]_i_9 + (.I0(stride_vid[1]), + .I1(\dm_address_reg[15]_0 [1]), + .I2(load_new_addr), + .I3(\dm_address[0]_i_13_n_0 ), + .O(\dm_address[0]_i_9_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[12]_i_10 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [15]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [15]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [15]), + .O(\dm_address[12]_i_10_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[12]_i_11 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [14]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [14]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [14]), + .O(\dm_address[12]_i_11_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[12]_i_12 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [13]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [13]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [13]), + .O(\dm_address[12]_i_12_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[12]_i_13 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [12]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [12]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [12]), + .O(\dm_address[12]_i_13_n_0 )); LUT2 #( - .INIT(4'hE)) - stop_i_1 - (.I0(p_68_out[1]), - .I1(dma_err), - .O(stop_i)); -endmodule - -(* ORIG_REF_NAME = "axi_vdma_reset" *) -module Arty_Z7_20_axi_vdma_0_0_axi_vdma_reset - (in0, - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from , - halt_i_reg_0, - prmry_reset2, - fifo_wren__0, - p_8_out, - \dmacr_i_reg[2] , - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg , - \cmnds_queued_reg[7] , - sig_mm2s_dm_prmry_resetn, - reset_counts_reg, - sig_s_h_halt_reg_reg, - scndry_out, - m_axi_mm2s_aclk, - s_axi_lite_aclk, - m_axis_mm2s_aclk, - p_68_out, - s_soft_reset_i0, - dm2linebuf_mm2s_tvalid, - fifo_full_i, - out, - p_23_out, - p_35_out, - mm2s_halt_cmplt, - mm2s_axi2ip_wrce, - D, - DIN, - dma_err, - reset_counts, - sig_rst2all_stop_request, - \FSM_sequential_dmacntrl_cs_reg[1] , - prmry_in); - output in0; - output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ; - output halt_i_reg_0; - output prmry_reset2; - output fifo_wren__0; - output p_8_out; - output \dmacr_i_reg[2] ; - output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; - output [0:0]\cmnds_queued_reg[7] ; - output sig_mm2s_dm_prmry_resetn; - output reset_counts_reg; - output sig_s_h_halt_reg_reg; - output scndry_out; - input m_axi_mm2s_aclk; - input s_axi_lite_aclk; - input m_axis_mm2s_aclk; - input [1:0]p_68_out; - input s_soft_reset_i0; - input dm2linebuf_mm2s_tvalid; - input fifo_full_i; - input out; - input p_23_out; - input p_35_out; - input mm2s_halt_cmplt; - input [0:0]mm2s_axi2ip_wrce; - input [0:0]D; - input [0:0]DIN; - input dma_err; - input reset_counts; - input sig_rst2all_stop_request; - input \FSM_sequential_dmacntrl_cs_reg[1] ; - input prmry_in; - - wire [0:0]D; - wire [0:0]DIN; - wire \FSM_sequential_dmacntrl_cs_reg[1] ; - wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ; - wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; - wire \GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2 ; - wire \GEN_MIN_FOR_ASYNC.AXIS_RESET_CDC_I_n_1 ; - wire \GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2 ; - wire \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_2 ; - wire \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_3 ; - wire \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_4 ; - wire \GEN_MIN_FOR_ASYNC.LITE_RESET_CDC_I_n_1 ; - wire \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_2_n_0 ; - wire \GEN_MIN_FOR_ASYNC.axis_min_count[0]_i_1_n_0 ; - wire \GEN_MIN_FOR_ASYNC.axis_min_count[1]_i_1_n_0 ; - wire \GEN_MIN_FOR_ASYNC.axis_min_count[2]_i_1_n_0 ; - wire \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0 ; - wire \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_3_n_0 ; - wire \GEN_MIN_FOR_ASYNC.lite_min_count[0]_i_1_n_0 ; - wire \GEN_MIN_FOR_ASYNC.lite_min_count[1]_i_1_n_0 ; - wire \GEN_MIN_FOR_ASYNC.lite_min_count[2]_i_1_n_0 ; - wire \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0 ; - wire \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_3_n_0 ; - wire \GEN_MIN_FOR_ASYNC.prmry_min_count[0]_i_1_n_0 ; - wire \GEN_MIN_FOR_ASYNC.prmry_min_count[1]_i_1_n_0 ; - wire \GEN_MIN_FOR_ASYNC.prmry_min_count[2]_i_1_n_0 ; - wire \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0 ; - wire \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_3_n_0 ; - wire \GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_2 ; - wire \GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_3 ; - wire assert_sftrst_d1; - wire axis_all_idle; - wire axis_min_assert_sftrst; - wire [3:0]axis_min_count; - wire [0:0]\cmnds_queued_reg[7] ; - wire dm2linebuf_mm2s_tvalid; - wire dma_err; - wire \dmacr_i_reg[2] ; - wire fifo_full_i; - wire fifo_wren__0; - wire halt_i0; - wire halt_i_reg_0; - wire halt_reset_i_1_n_0; - wire in0; - wire lite_all_idle; - wire lite_min_assert_sftrst; - wire [3:0]lite_min_count; - wire m_axi_mm2s_aclk; - wire m_axis_mm2s_aclk; - wire min_assert_sftrst; - wire [0:0]mm2s_axi2ip_wrce; - wire mm2s_halt_cmplt; - wire out; - wire p_11_out; - wire p_1_out; - wire p_23_out; - wire p_2_out; - wire p_35_out; - wire p_3_out; - wire p_4_out; - wire [1:0]p_68_out; - wire p_6_out; - wire p_8_out; - wire p_8_out_0; - wire p_in_d1_cdc_from; - wire p_in_d1_cdc_from_0; - wire prmry_in; - wire prmry_in_xored; - wire prmry_in_xored_1; - wire prmry_min_assert_sftrst; - wire [3:0]prmry_min_count; - wire prmry_reset2; - wire reset_counts; - wire reset_counts_reg; - wire resetn_i; - wire run_stop_d1; - wire s_axi_lite_aclk; - wire s_soft_reset_i; - wire s_soft_reset_i0; - wire s_soft_reset_i_d1; - wire scndry_out; - wire sig_mm2s_dm_prmry_resetn; - wire sig_rst2all_stop_request; - wire sig_s_h_halt_reg_reg; - wire soft_reset_d1; - + .INIT(4'h2)) + \dm_address[12]_i_2 + (.I0(stride_vid[15]), + .I1(load_new_addr), + .O(\dm_address[12]_i_2_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dm_address[12]_i_3 + (.I0(stride_vid[14]), + .I1(load_new_addr), + .O(\dm_address[12]_i_3_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dm_address[12]_i_4 + (.I0(stride_vid[13]), + .I1(load_new_addr), + .O(\dm_address[12]_i_4_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dm_address[12]_i_5 + (.I0(stride_vid[12]), + .I1(load_new_addr), + .O(\dm_address[12]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \dm_address[12]_i_6 + (.I0(stride_vid[15]), + .I1(\dm_address_reg[15]_0 [15]), + .I2(load_new_addr), + .I3(\dm_address[12]_i_10_n_0 ), + .O(\dm_address[12]_i_6_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \dm_address[12]_i_7 + (.I0(stride_vid[14]), + .I1(\dm_address_reg[15]_0 [14]), + .I2(load_new_addr), + .I3(\dm_address[12]_i_11_n_0 ), + .O(\dm_address[12]_i_7_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \dm_address[12]_i_8 + (.I0(stride_vid[13]), + .I1(\dm_address_reg[15]_0 [13]), + .I2(load_new_addr), + .I3(\dm_address[12]_i_12_n_0 ), + .O(\dm_address[12]_i_8_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \dm_address[12]_i_9 + (.I0(stride_vid[12]), + .I1(\dm_address_reg[15]_0 [12]), + .I2(load_new_addr), + .I3(\dm_address[12]_i_13_n_0 ), + .O(\dm_address[12]_i_9_n_0 )); LUT5 #( - .INIT(32'h00000E00)) - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_i_1 - (.I0(DIN), - .I1(p_23_out), - .I2(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ), - .I3(out), - .I4(fifo_wren__0), - .O(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg )); - Arty_Z7_20_axi_vdma_0_0_cdc_sync \GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I - (.SR(\GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2 ), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axis_mm2s_aclk(m_axis_mm2s_aclk), - .p_1_out(p_1_out), - .p_3_out(p_3_out), - .p_in_d1_cdc_from(p_in_d1_cdc_from), - .prmry_in_xored(prmry_in_xored)); - Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized2 \GEN_MIN_FOR_ASYNC.AXIS_IDLE_CDC_I - (.\FSM_sequential_dmacntrl_cs_reg[1] (\FSM_sequential_dmacntrl_cs_reg[1] ), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axis_mm2s_aclk(m_axis_mm2s_aclk), - .scndry_out(axis_all_idle)); - Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized3 \GEN_MIN_FOR_ASYNC.AXIS_MIN_CDC_I - (.axis_min_assert_sftrst(axis_min_assert_sftrst), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axis_mm2s_aclk(m_axis_mm2s_aclk), - .scndry_out(p_2_out)); - Arty_Z7_20_axi_vdma_0_0_cdc_sync_0 \GEN_MIN_FOR_ASYNC.AXIS_RESET_CDC_I - (.\GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_reg (\GEN_MIN_FOR_ASYNC.AXIS_RESET_CDC_I_n_1 ), - .\GEN_MIN_FOR_ASYNC.axis_min_count_reg[2] (\GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_2_n_0 ), - .axis_min_assert_sftrst(axis_min_assert_sftrst), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axis_mm2s_aclk(m_axis_mm2s_aclk), - .p_1_out(p_1_out), - .p_3_out(p_3_out), - .s_soft_reset_i(s_soft_reset_i), - .s_soft_reset_i_d1(s_soft_reset_i_d1)); - FDRE #( - .INIT(1'b0)) - \GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_reg - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_3 ), - .Q(min_assert_sftrst), - .R(1'b0)); - Arty_Z7_20_axi_vdma_0_0_cdc_sync_1 \GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I - (.SR(\GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2 ), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .p_4_out(p_4_out), - .p_6_out(p_6_out), - .p_in_d1_cdc_from(p_in_d1_cdc_from_0), - .prmry_in_xored(prmry_in_xored_1), - .s_axi_lite_aclk(s_axi_lite_aclk)); - Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized0 \GEN_MIN_FOR_ASYNC.LITE_IDLE_CDC_I - (.\FSM_sequential_dmacntrl_cs_reg[1] (\FSM_sequential_dmacntrl_cs_reg[1] ), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .s_axi_lite_aclk(s_axi_lite_aclk), - .scndry_out(lite_all_idle)); - Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized1 \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I - (.\GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_reg (\GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_3 ), - .\GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_reg (\GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_4 ), - .SR(\GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_2 ), - .lite_min_assert_sftrst(lite_min_assert_sftrst), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .min_assert_sftrst(min_assert_sftrst), - .p_11_out(p_11_out), - .p_in_d1_cdc_from(p_in_d1_cdc_from_0), - .p_in_d1_cdc_from_1(p_in_d1_cdc_from), - .prmry_in_xored(prmry_in_xored_1), - .prmry_in_xored_0(prmry_in_xored), - .prmry_min_assert_sftrst(prmry_min_assert_sftrst), - .s_axi_lite_aclk(s_axi_lite_aclk), - .s_soft_reset_i(s_soft_reset_i), - .s_soft_reset_i_d1(s_soft_reset_i_d1), - .scndry_out(p_2_out)); - Arty_Z7_20_axi_vdma_0_0_cdc_sync_2 \GEN_MIN_FOR_ASYNC.LITE_RESET_CDC_I - (.\GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_reg (\GEN_MIN_FOR_ASYNC.LITE_RESET_CDC_I_n_1 ), - .lite_min_assert_sftrst(lite_min_assert_sftrst), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .p_4_out(p_4_out), - .p_6_out(p_6_out), - .p_8_out_0(p_8_out_0), - .s_axi_lite_aclk(s_axi_lite_aclk), - .s_soft_reset_i(s_soft_reset_i), - .s_soft_reset_i_d1(s_soft_reset_i_d1)); - (* SOFT_HLUTNM = "soft_lutpair117" *) + .INIT(32'h30BB3088)) + \dm_address[16]_i_6 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [19]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [19]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [19]), + .O(\dm_address_reg[19]_2 )); LUT5 #( - .INIT(32'h80000000)) - \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_2 - (.I0(axis_min_count[2]), - .I1(axis_min_count[0]), - .I2(axis_min_assert_sftrst), - .I3(axis_min_count[3]), - .I4(axis_min_count[1]), - .O(\GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_2_n_0 )); - FDRE #( - .INIT(1'b0)) - \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_reg - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(\GEN_MIN_FOR_ASYNC.AXIS_RESET_CDC_I_n_1 ), - .Q(axis_min_assert_sftrst), - .R(1'b0)); - (* SOFT_HLUTNM = "soft_lutpair117" *) + .INIT(32'h30BB3088)) + \dm_address[16]_i_7 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [18]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [18]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [18]), + .O(\dm_address_reg[19]_1 )); LUT5 #( - .INIT(32'h8000FFFF)) - \GEN_MIN_FOR_ASYNC.axis_min_count[0]_i_1 - (.I0(axis_min_count[1]), - .I1(axis_min_count[3]), - .I2(axis_min_assert_sftrst), - .I3(axis_min_count[2]), - .I4(axis_min_count[0]), - .O(\GEN_MIN_FOR_ASYNC.axis_min_count[0]_i_1_n_0 )); + .INIT(32'h30BB3088)) + \dm_address[16]_i_8 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [17]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [17]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [17]), + .O(\dm_address_reg[19]_0 )); LUT5 #( - .INIT(32'hD5AA55AA)) - \GEN_MIN_FOR_ASYNC.axis_min_count[1]_i_1 - (.I0(axis_min_count[1]), - .I1(axis_min_count[3]), - .I2(axis_min_assert_sftrst), - .I3(axis_min_count[0]), - .I4(axis_min_count[2]), - .O(\GEN_MIN_FOR_ASYNC.axis_min_count[1]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair119" *) + .INIT(32'h30BB3088)) + \dm_address[16]_i_9 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [16]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [16]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [16]), + .O(\dm_address_reg[19] )); LUT5 #( - .INIT(32'hD5FFAA00)) - \GEN_MIN_FOR_ASYNC.axis_min_count[2]_i_1 - (.I0(axis_min_count[1]), - .I1(axis_min_count[3]), - .I2(axis_min_assert_sftrst), - .I3(axis_min_count[0]), - .I4(axis_min_count[2]), - .O(\GEN_MIN_FOR_ASYNC.axis_min_count[2]_i_1_n_0 )); - LUT6 #( - .INIT(64'hEA00AA00AA00AA00)) - \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2 - (.I0(axis_all_idle), - .I1(axis_min_count[1]), - .I2(axis_min_count[3]), - .I3(axis_min_assert_sftrst), - .I4(axis_min_count[0]), - .I5(axis_min_count[2]), - .O(\GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair119" *) + .INIT(32'h30BB3088)) + \dm_address[20]_i_6 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [23]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [23]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [23]), + .O(\dm_address_reg[23]_2 )); LUT5 #( - .INIT(32'hE6CCCCCC)) - \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_3 - (.I0(axis_min_count[1]), - .I1(axis_min_count[3]), - .I2(axis_min_assert_sftrst), - .I3(axis_min_count[0]), - .I4(axis_min_count[2]), - .O(\GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_3_n_0 )); - FDRE #( - .INIT(1'b0)) - \GEN_MIN_FOR_ASYNC.axis_min_count_reg[0] - (.C(m_axis_mm2s_aclk), - .CE(\GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0 ), - .D(\GEN_MIN_FOR_ASYNC.axis_min_count[0]_i_1_n_0 ), - .Q(axis_min_count[0]), - .R(\GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2 )); - FDRE #( - .INIT(1'b0)) - \GEN_MIN_FOR_ASYNC.axis_min_count_reg[1] - (.C(m_axis_mm2s_aclk), - .CE(\GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0 ), - .D(\GEN_MIN_FOR_ASYNC.axis_min_count[1]_i_1_n_0 ), - .Q(axis_min_count[1]), - .R(\GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2 )); - FDRE #( - .INIT(1'b0)) - \GEN_MIN_FOR_ASYNC.axis_min_count_reg[2] - (.C(m_axis_mm2s_aclk), - .CE(\GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0 ), - .D(\GEN_MIN_FOR_ASYNC.axis_min_count[2]_i_1_n_0 ), - .Q(axis_min_count[2]), - .R(\GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2 )); - FDRE #( - .INIT(1'b0)) - \GEN_MIN_FOR_ASYNC.axis_min_count_reg[3] - (.C(m_axis_mm2s_aclk), - .CE(\GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0 ), - .D(\GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_3_n_0 ), - .Q(axis_min_count[3]), - .R(\GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2 )); - (* SOFT_HLUTNM = "soft_lutpair120" *) + .INIT(32'h30BB3088)) + \dm_address[20]_i_7 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [22]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [22]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [22]), + .O(\dm_address_reg[23]_1 )); LUT5 #( - .INIT(32'h80000000)) - \GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_i_2 - (.I0(lite_min_count[2]), - .I1(lite_min_count[0]), - .I2(lite_min_assert_sftrst), - .I3(lite_min_count[3]), - .I4(lite_min_count[1]), - .O(p_8_out_0)); - FDRE #( - .INIT(1'b0)) - \GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_reg - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(\GEN_MIN_FOR_ASYNC.LITE_RESET_CDC_I_n_1 ), - .Q(lite_min_assert_sftrst), - .R(1'b0)); - (* SOFT_HLUTNM = "soft_lutpair120" *) + .INIT(32'h30BB3088)) + \dm_address[20]_i_8 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [21]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [21]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [21]), + .O(\dm_address_reg[23]_0 )); LUT5 #( - .INIT(32'h8000FFFF)) - \GEN_MIN_FOR_ASYNC.lite_min_count[0]_i_1 - (.I0(lite_min_count[1]), - .I1(lite_min_count[3]), - .I2(lite_min_assert_sftrst), - .I3(lite_min_count[2]), - .I4(lite_min_count[0]), - .O(\GEN_MIN_FOR_ASYNC.lite_min_count[0]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair121" *) + .INIT(32'h30BB3088)) + \dm_address[20]_i_9 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [20]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [20]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [20]), + .O(\dm_address_reg[23] )); LUT5 #( - .INIT(32'hD5AA55AA)) - \GEN_MIN_FOR_ASYNC.lite_min_count[1]_i_1 - (.I0(lite_min_count[1]), - .I1(lite_min_count[3]), - .I2(lite_min_assert_sftrst), - .I3(lite_min_count[0]), - .I4(lite_min_count[2]), - .O(\GEN_MIN_FOR_ASYNC.lite_min_count[1]_i_1_n_0 )); + .INIT(32'h30BB3088)) + \dm_address[24]_i_6 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [27]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [27]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [27]), + .O(\dm_address_reg[27]_2 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[24]_i_7 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [26]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [26]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [26]), + .O(\dm_address_reg[27]_1 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[24]_i_8 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [25]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [25]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [25]), + .O(\dm_address_reg[27]_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[24]_i_9 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [24]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [24]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [24]), + .O(\dm_address_reg[27] )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[28]_i_6 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [31]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [31]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [31]), + .O(\dm_address_reg[31]_2 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[28]_i_7 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [30]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [30]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [30]), + .O(\dm_address_reg[31]_1 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[28]_i_8 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [29]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [29]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [29]), + .O(\dm_address_reg[31]_0 )); LUT5 #( - .INIT(32'hD5FFAA00)) - \GEN_MIN_FOR_ASYNC.lite_min_count[2]_i_1 - (.I0(lite_min_count[1]), - .I1(lite_min_count[3]), - .I2(lite_min_assert_sftrst), - .I3(lite_min_count[0]), - .I4(lite_min_count[2]), - .O(\GEN_MIN_FOR_ASYNC.lite_min_count[2]_i_1_n_0 )); - LUT6 #( - .INIT(64'hEA00AA00AA00AA00)) - \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2 - (.I0(lite_all_idle), - .I1(lite_min_count[1]), - .I2(lite_min_count[3]), - .I3(lite_min_assert_sftrst), - .I4(lite_min_count[0]), - .I5(lite_min_count[2]), - .O(\GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair121" *) + .INIT(32'h30BB3088)) + \dm_address[28]_i_9 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [28]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [28]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [28]), + .O(\dm_address_reg[31] )); LUT5 #( - .INIT(32'hE6CCCCCC)) - \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_3 - (.I0(lite_min_count[1]), - .I1(lite_min_count[3]), - .I2(lite_min_assert_sftrst), - .I3(lite_min_count[0]), - .I4(lite_min_count[2]), - .O(\GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_3_n_0 )); - FDRE #( - .INIT(1'b0)) - \GEN_MIN_FOR_ASYNC.lite_min_count_reg[0] - (.C(s_axi_lite_aclk), - .CE(\GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0 ), - .D(\GEN_MIN_FOR_ASYNC.lite_min_count[0]_i_1_n_0 ), - .Q(lite_min_count[0]), - .R(\GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2 )); - FDRE #( - .INIT(1'b0)) - \GEN_MIN_FOR_ASYNC.lite_min_count_reg[1] - (.C(s_axi_lite_aclk), - .CE(\GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0 ), - .D(\GEN_MIN_FOR_ASYNC.lite_min_count[1]_i_1_n_0 ), - .Q(lite_min_count[1]), - .R(\GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2 )); - FDRE #( - .INIT(1'b0)) - \GEN_MIN_FOR_ASYNC.lite_min_count_reg[2] - (.C(s_axi_lite_aclk), - .CE(\GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0 ), - .D(\GEN_MIN_FOR_ASYNC.lite_min_count[2]_i_1_n_0 ), - .Q(lite_min_count[2]), - .R(\GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2 )); - FDRE #( - .INIT(1'b0)) - \GEN_MIN_FOR_ASYNC.lite_min_count_reg[3] - (.C(s_axi_lite_aclk), - .CE(\GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0 ), - .D(\GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_3_n_0 ), - .Q(lite_min_count[3]), - .R(\GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2 )); - (* SOFT_HLUTNM = "soft_lutpair116" *) + .INIT(32'h30BB3088)) + \dm_address[4]_i_10 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [7]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [7]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [7]), + .O(\dm_address[4]_i_10_n_0 )); LUT5 #( - .INIT(32'h80000000)) - \GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_i_2 - (.I0(prmry_min_count[2]), - .I1(prmry_min_count[0]), - .I2(prmry_min_assert_sftrst), - .I3(prmry_min_count[3]), - .I4(prmry_min_count[1]), - .O(p_11_out)); - FDRE #( - .INIT(1'b0)) - \GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_reg - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_4 ), - .Q(prmry_min_assert_sftrst), - .R(1'b0)); - (* SOFT_HLUTNM = "soft_lutpair118" *) + .INIT(32'h30BB3088)) + \dm_address[4]_i_11 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [6]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [6]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [6]), + .O(\dm_address[4]_i_11_n_0 )); LUT5 #( - .INIT(32'h8000FFFF)) - \GEN_MIN_FOR_ASYNC.prmry_min_count[0]_i_1 - (.I0(prmry_min_count[1]), - .I1(prmry_min_count[3]), - .I2(prmry_min_assert_sftrst), - .I3(prmry_min_count[2]), - .I4(prmry_min_count[0]), - .O(\GEN_MIN_FOR_ASYNC.prmry_min_count[0]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair116" *) + .INIT(32'h30BB3088)) + \dm_address[4]_i_12 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [5]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [5]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [5]), + .O(\dm_address[4]_i_12_n_0 )); LUT5 #( - .INIT(32'hD5AA55AA)) - \GEN_MIN_FOR_ASYNC.prmry_min_count[1]_i_1 - (.I0(prmry_min_count[1]), - .I1(prmry_min_count[3]), - .I2(prmry_min_assert_sftrst), - .I3(prmry_min_count[0]), - .I4(prmry_min_count[2]), - .O(\GEN_MIN_FOR_ASYNC.prmry_min_count[1]_i_1_n_0 )); + .INIT(32'h30BB3088)) + \dm_address[4]_i_13 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [4]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [4]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [4]), + .O(\dm_address[4]_i_13_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dm_address[4]_i_2 + (.I0(stride_vid[7]), + .I1(load_new_addr), + .O(\dm_address[4]_i_2_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dm_address[4]_i_3 + (.I0(stride_vid[6]), + .I1(load_new_addr), + .O(\dm_address[4]_i_3_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dm_address[4]_i_4 + (.I0(stride_vid[5]), + .I1(load_new_addr), + .O(\dm_address[4]_i_4_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dm_address[4]_i_5 + (.I0(stride_vid[4]), + .I1(load_new_addr), + .O(\dm_address[4]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \dm_address[4]_i_6 + (.I0(stride_vid[7]), + .I1(\dm_address_reg[15]_0 [7]), + .I2(load_new_addr), + .I3(\dm_address[4]_i_10_n_0 ), + .O(\dm_address[4]_i_6_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \dm_address[4]_i_7 + (.I0(stride_vid[6]), + .I1(\dm_address_reg[15]_0 [6]), + .I2(load_new_addr), + .I3(\dm_address[4]_i_11_n_0 ), + .O(\dm_address[4]_i_7_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \dm_address[4]_i_8 + (.I0(stride_vid[5]), + .I1(\dm_address_reg[15]_0 [5]), + .I2(load_new_addr), + .I3(\dm_address[4]_i_12_n_0 ), + .O(\dm_address[4]_i_8_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \dm_address[4]_i_9 + (.I0(stride_vid[4]), + .I1(\dm_address_reg[15]_0 [4]), + .I2(load_new_addr), + .I3(\dm_address[4]_i_13_n_0 ), + .O(\dm_address[4]_i_9_n_0 )); LUT5 #( - .INIT(32'hD5FFAA00)) - \GEN_MIN_FOR_ASYNC.prmry_min_count[2]_i_1 - (.I0(prmry_min_count[1]), - .I1(prmry_min_count[3]), - .I2(prmry_min_assert_sftrst), - .I3(prmry_min_count[0]), - .I4(prmry_min_count[2]), - .O(\GEN_MIN_FOR_ASYNC.prmry_min_count[2]_i_1_n_0 )); + .INIT(32'h30BB3088)) + \dm_address[8]_i_10 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [11]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [11]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [11]), + .O(\dm_address[8]_i_10_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[8]_i_11 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [10]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [10]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [10]), + .O(\dm_address[8]_i_11_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[8]_i_12 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [9]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [9]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [9]), + .O(\dm_address[8]_i_12_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \dm_address[8]_i_13 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1 [8]), + .I1(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [0]), + .I2(\GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0 [8]), + .I3(\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1] [1]), + .I4(\GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2 [8]), + .O(\dm_address[8]_i_13_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dm_address[8]_i_2 + (.I0(stride_vid[11]), + .I1(load_new_addr), + .O(\dm_address[8]_i_2_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dm_address[8]_i_3 + (.I0(stride_vid[10]), + .I1(load_new_addr), + .O(\dm_address[8]_i_3_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dm_address[8]_i_4 + (.I0(stride_vid[9]), + .I1(load_new_addr), + .O(\dm_address[8]_i_4_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dm_address[8]_i_5 + (.I0(stride_vid[8]), + .I1(load_new_addr), + .O(\dm_address[8]_i_5_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \dm_address[8]_i_6 + (.I0(stride_vid[11]), + .I1(\dm_address_reg[15]_0 [11]), + .I2(load_new_addr), + .I3(\dm_address[8]_i_10_n_0 ), + .O(\dm_address[8]_i_6_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \dm_address[8]_i_7 + (.I0(stride_vid[10]), + .I1(\dm_address_reg[15]_0 [10]), + .I2(load_new_addr), + .I3(\dm_address[8]_i_11_n_0 ), + .O(\dm_address[8]_i_7_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \dm_address[8]_i_8 + (.I0(stride_vid[9]), + .I1(\dm_address_reg[15]_0 [9]), + .I2(load_new_addr), + .I3(\dm_address[8]_i_12_n_0 ), + .O(\dm_address[8]_i_8_n_0 )); + LUT4 #( + .INIT(16'hF606)) + \dm_address[8]_i_9 + (.I0(stride_vid[8]), + .I1(\dm_address_reg[15]_0 [8]), + .I2(load_new_addr), + .I3(\dm_address[8]_i_13_n_0 ), + .O(\dm_address[8]_i_9_n_0 )); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \dm_address_reg[0]_i_2 + (.CI(1'b0), + .CO({\dm_address_reg[0]_i_2_n_0 ,\dm_address_reg[0]_i_2_n_1 ,\dm_address_reg[0]_i_2_n_2 ,\dm_address_reg[0]_i_2_n_3 }), + .CYINIT(1'b0), + .DI({\dm_address[0]_i_3_n_0 ,\dm_address[0]_i_4_n_0 ,\dm_address[0]_i_5_n_0 ,\dm_address[0]_i_6_n_0 }), + .O(O), + .S({\dm_address[0]_i_7_n_0 ,\dm_address[0]_i_8_n_0 ,\dm_address[0]_i_9_n_0 ,\dm_address[0]_i_10_n_0 })); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \dm_address_reg[12]_i_1 + (.CI(\dm_address_reg[8]_i_1_n_0 ), + .CO({CO,\dm_address_reg[12]_i_1_n_1 ,\dm_address_reg[12]_i_1_n_2 ,\dm_address_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({\dm_address[12]_i_2_n_0 ,\dm_address[12]_i_3_n_0 ,\dm_address[12]_i_4_n_0 ,\dm_address[12]_i_5_n_0 }), + .O(\dm_address_reg[15] ), + .S({\dm_address[12]_i_6_n_0 ,\dm_address[12]_i_7_n_0 ,\dm_address[12]_i_8_n_0 ,\dm_address[12]_i_9_n_0 })); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \dm_address_reg[4]_i_1 + (.CI(\dm_address_reg[0]_i_2_n_0 ), + .CO({\dm_address_reg[4]_i_1_n_0 ,\dm_address_reg[4]_i_1_n_1 ,\dm_address_reg[4]_i_1_n_2 ,\dm_address_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({\dm_address[4]_i_2_n_0 ,\dm_address[4]_i_3_n_0 ,\dm_address[4]_i_4_n_0 ,\dm_address[4]_i_5_n_0 }), + .O(\dm_address_reg[7] ), + .S({\dm_address[4]_i_6_n_0 ,\dm_address[4]_i_7_n_0 ,\dm_address[4]_i_8_n_0 ,\dm_address[4]_i_9_n_0 })); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \dm_address_reg[8]_i_1 + (.CI(\dm_address_reg[4]_i_1_n_0 ), + .CO({\dm_address_reg[8]_i_1_n_0 ,\dm_address_reg[8]_i_1_n_1 ,\dm_address_reg[8]_i_1_n_2 ,\dm_address_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({\dm_address[8]_i_2_n_0 ,\dm_address[8]_i_3_n_0 ,\dm_address[8]_i_4_n_0 ,\dm_address[8]_i_5_n_0 }), + .O(\dm_address_reg[11] ), + .S({\dm_address[8]_i_6_n_0 ,\dm_address[8]_i_7_n_0 ,\dm_address[8]_i_8_n_0 ,\dm_address[8]_i_9_n_0 })); + FDRE \hsize_vid_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [0]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [0]), + .R(SR)); + FDRE \hsize_vid_reg[10] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [10]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [10]), + .R(SR)); + FDRE \hsize_vid_reg[11] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [11]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [11]), + .R(SR)); + FDRE \hsize_vid_reg[12] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [12]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [12]), + .R(SR)); + FDRE \hsize_vid_reg[13] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [13]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [13]), + .R(SR)); + FDRE \hsize_vid_reg[14] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [14]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [14]), + .R(SR)); + FDRE \hsize_vid_reg[15] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [15]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [15]), + .R(SR)); + FDRE \hsize_vid_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [1]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [1]), + .R(SR)); + FDRE \hsize_vid_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [2]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [2]), + .R(SR)); + FDRE \hsize_vid_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [3]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [3]), + .R(SR)); + FDRE \hsize_vid_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [4]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [4]), + .R(SR)); + FDRE \hsize_vid_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [5]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [5]), + .R(SR)); + FDRE \hsize_vid_reg[6] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [6]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [6]), + .R(SR)); + FDRE \hsize_vid_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [7]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [7]), + .R(SR)); + FDRE \hsize_vid_reg[8] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [8]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [8]), + .R(SR)); + FDRE \hsize_vid_reg[9] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\reg_module_hsize_reg[15] [9]), + .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [9]), + .R(SR)); + FDRE \stride_vid_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [0]), + .Q(stride_vid[0]), + .R(SR)); + FDRE \stride_vid_reg[10] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [10]), + .Q(stride_vid[10]), + .R(SR)); + FDRE \stride_vid_reg[11] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [11]), + .Q(stride_vid[11]), + .R(SR)); + FDRE \stride_vid_reg[12] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [12]), + .Q(stride_vid[12]), + .R(SR)); + FDRE \stride_vid_reg[13] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [13]), + .Q(stride_vid[13]), + .R(SR)); + FDRE \stride_vid_reg[14] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [14]), + .Q(stride_vid[14]), + .R(SR)); + FDRE \stride_vid_reg[15] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [15]), + .Q(stride_vid[15]), + .R(SR)); + FDRE \stride_vid_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [1]), + .Q(stride_vid[1]), + .R(SR)); + FDRE \stride_vid_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [2]), + .Q(stride_vid[2]), + .R(SR)); + FDRE \stride_vid_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [3]), + .Q(stride_vid[3]), + .R(SR)); + FDRE \stride_vid_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [4]), + .Q(stride_vid[4]), + .R(SR)); + FDRE \stride_vid_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [5]), + .Q(stride_vid[5]), + .R(SR)); + FDRE \stride_vid_reg[6] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [6]), + .Q(stride_vid[6]), + .R(SR)); + FDRE \stride_vid_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [7]), + .Q(stride_vid[7]), + .R(SR)); + FDRE \stride_vid_reg[8] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [8]), + .Q(stride_vid[8]), + .R(SR)); + FDRE \stride_vid_reg[9] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [9]), + .Q(stride_vid[9]), + .R(SR)); + LUT3 #( + .INIT(8'h8A)) + \vsize_vid[12]_i_1 + (.I0(\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg ), + .I1(p_24_out), + .I2(\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg ), + .O(video_reg_update)); + FDRE \vsize_vid_reg[0] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\reg_module_vsize_reg[12] [0]), + .Q(Q[0]), + .R(SR)); + FDRE \vsize_vid_reg[10] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\reg_module_vsize_reg[12] [10]), + .Q(Q[10]), + .R(SR)); + FDRE \vsize_vid_reg[11] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\reg_module_vsize_reg[12] [11]), + .Q(Q[11]), + .R(SR)); + FDRE \vsize_vid_reg[12] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\reg_module_vsize_reg[12] [12]), + .Q(Q[12]), + .R(SR)); + FDRE \vsize_vid_reg[1] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\reg_module_vsize_reg[12] [1]), + .Q(Q[1]), + .R(SR)); + FDRE \vsize_vid_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\reg_module_vsize_reg[12] [2]), + .Q(Q[2]), + .R(SR)); + FDRE \vsize_vid_reg[3] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\reg_module_vsize_reg[12] [3]), + .Q(Q[3]), + .R(SR)); + FDRE \vsize_vid_reg[4] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\reg_module_vsize_reg[12] [4]), + .Q(Q[4]), + .R(SR)); + FDRE \vsize_vid_reg[5] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\reg_module_vsize_reg[12] [5]), + .Q(Q[5]), + .R(SR)); + FDRE \vsize_vid_reg[6] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\reg_module_vsize_reg[12] [6]), + .Q(Q[6]), + .R(SR)); + FDRE \vsize_vid_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\reg_module_vsize_reg[12] [7]), + .Q(Q[7]), + .R(SR)); + FDRE \vsize_vid_reg[8] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\reg_module_vsize_reg[12] [8]), + .Q(Q[8]), + .R(SR)); + FDRE \vsize_vid_reg[9] + (.C(m_axi_mm2s_aclk), + .CE(video_reg_update), + .D(\reg_module_vsize_reg[12] [9]), + .Q(Q[9]), + .R(SR)); + LUT5 #( + .INIT(32'h00000002)) + zero_hsize_err_i_1 + (.I0(zero_hsize_err_i_2_n_0), + .I1(zero_hsize_err_i_3_n_0), + .I2(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [7]), + .I3(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [10]), + .I4(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [0]), + .O(zero_hsize_err0)); LUT6 #( - .INIT(64'hEA00AA00AA00AA00)) - \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2 - (.I0(\FSM_sequential_dmacntrl_cs_reg[1] ), - .I1(prmry_min_count[1]), - .I2(prmry_min_count[3]), - .I3(prmry_min_assert_sftrst), - .I4(prmry_min_count[0]), - .I5(prmry_min_count[2]), - .O(\GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair118" *) + .INIT(64'h0000000000000001)) + zero_hsize_err_i_2 + (.I0(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [13]), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [4]), + .I2(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [6]), + .I3(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [15]), + .I4(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [9]), + .I5(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [14]), + .O(zero_hsize_err_i_2_n_0)); LUT5 #( - .INIT(32'hE6CCCCCC)) - \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_3 - (.I0(prmry_min_count[1]), - .I1(prmry_min_count[3]), - .I2(prmry_min_assert_sftrst), - .I3(prmry_min_count[0]), - .I4(prmry_min_count[2]), - .O(\GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_3_n_0 )); + .INIT(32'hFFFFFEFF)) + zero_hsize_err_i_3 + (.I0(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [1]), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [8]), + .I2(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [11]), + .I3(load_new_addr), + .I4(zero_hsize_err_i_4_n_0), + .O(zero_hsize_err_i_3_n_0)); + LUT4 #( + .INIT(16'hFFFE)) + zero_hsize_err_i_4 + (.I0(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [12]), + .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [3]), + .I2(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [5]), + .I3(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [2]), + .O(zero_hsize_err_i_4_n_0)); + LUT6 #( + .INIT(64'h0000000000000002)) + zero_vsize_err_i_1 + (.I0(zero_vsize_err_i_2_n_0), + .I1(zero_vsize_err_i_3_n_0), + .I2(Q[4]), + .I3(Q[1]), + .I4(Q[12]), + .I5(Q[3]), + .O(zero_vsize_err0)); + LUT6 #( + .INIT(64'h0000000000000004)) + zero_vsize_err_i_2 + (.I0(Q[0]), + .I1(load_new_addr), + .I2(Q[10]), + .I3(Q[11]), + .I4(Q[2]), + .I5(Q[7]), + .O(zero_vsize_err_i_2_n_0)); + LUT4 #( + .INIT(16'hFFFE)) + zero_vsize_err_i_3 + (.I0(Q[9]), + .I1(Q[8]), + .I2(Q[6]), + .I3(Q[5]), + .O(zero_vsize_err_i_3_n_0)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync + (p_in_d1_cdc_from, + p_1_out, + SR, + prmry_in_xored, + m_axi_s2mm_aclk, + s_axis_s2mm_aclk, + p_3_out); + output p_in_d1_cdc_from; + output p_1_out; + output [0:0]SR; + input prmry_in_xored; + input m_axi_s2mm_aclk; + input s_axis_s2mm_aclk; + input p_3_out; + + wire [0:0]SR; + wire m_axi_s2mm_aclk; + wire p_1_out; + wire p_3_out; + wire p_in_d1_cdc_from; + wire prmry_in_xored; + wire s_axis_s2mm_aclk; + wire s_out_d1_cdc_to; + wire s_out_d2; + wire s_out_d3; + wire s_out_d4; + wire s_out_d5; + wire s_out_re__0; + wire srst_d1; + wire srst_d2; + wire srst_d3; + wire srst_d4; + wire srst_d5; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GEN_MIN_FOR_ASYNC.prmry_min_count_reg[0] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0 ), - .D(\GEN_MIN_FOR_ASYNC.prmry_min_count[0]_i_1_n_0 ), - .Q(prmry_min_count[0]), - .R(\GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_2 )); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(s_out_d1_cdc_to), + .Q(s_out_d2), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GEN_MIN_FOR_ASYNC.prmry_min_count_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0 ), - .D(\GEN_MIN_FOR_ASYNC.prmry_min_count[1]_i_1_n_0 ), - .Q(prmry_min_count[1]), - .R(\GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_2 )); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(s_out_d2), + .Q(s_out_d3), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GEN_MIN_FOR_ASYNC.prmry_min_count_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0 ), - .D(\GEN_MIN_FOR_ASYNC.prmry_min_count[2]_i_1_n_0 ), - .Q(prmry_min_count[2]), - .R(\GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_2 )); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(s_out_d3), + .Q(s_out_d4), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GEN_MIN_FOR_ASYNC.prmry_min_count_reg[3] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0 ), - .D(\GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_3_n_0 ), - .Q(prmry_min_count[3]), - .R(\GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_2 )); - Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized5 \GEN_RESET_FOR_ASYNC.AXIS_RESET_CDC_I - (.m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axis_mm2s_aclk(m_axis_mm2s_aclk), - .prmry_in(resetn_i), - .scndry_out(scndry_out)); - Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized4 \GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I - (.D(D), - .assert_sftrst_d1(assert_sftrst_d1), - .\dmacr_i_reg[2] (\dmacr_i_reg[2] ), - .halt_i0(halt_i0), - .halt_i_reg(\GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_3 ), - .halt_i_reg_0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ), - .halt_reset_reg(halt_i_reg_0), - .hrd_resetn_i_reg(prmry_in), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .min_assert_sftrst(min_assert_sftrst), - .mm2s_axi2ip_wrce(mm2s_axi2ip_wrce), - .out(out), - .p_35_out(p_35_out), - .p_68_out(p_68_out), - .prmry_in(resetn_i), - .prmry_reset2(prmry_reset2), - .reset_counts(reset_counts), - .reset_counts_reg(reset_counts_reg), - .run_stop_d1_reg(\GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_2 ), - .s_axi_lite_aclk(s_axi_lite_aclk), - .s_soft_reset_i(s_soft_reset_i), - .sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0(sig_mm2s_dm_prmry_resetn)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(s_out_d4), + .Q(s_out_d5), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - assert_sftrst_d1_reg - (.C(m_axi_mm2s_aclk), + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(min_assert_sftrst), - .Q(assert_sftrst_d1), + .D(s_out_re__0), + .Q(p_1_out), .R(1'b0)); - (* SOFT_HLUTNM = "soft_lutpair122" *) - LUT4 #( - .INIT(16'hFEFF)) - \cmnds_queued[7]_i_1 - (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ), - .I1(p_68_out[1]), - .I2(dma_err), - .I3(out), - .O(\cmnds_queued_reg[7] )); - (* SOFT_HLUTNM = "soft_lutpair115" *) - LUT4 #( - .INIT(16'h0010)) - \gc1.count_d1[6]_i_3 - (.I0(p_23_out), - .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ), - .I2(out), - .I3(fifo_full_i), - .O(p_8_out)); - (* SOFT_HLUTNM = "soft_lutpair115" *) - LUT5 #( - .INIT(32'h00000020)) - \gf36e1_inst.sngfifo36e1_i_13 - (.I0(dm2linebuf_mm2s_tvalid), - .I1(fifo_full_i), - .I2(out), - .I3(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ), - .I4(p_23_out), - .O(fifo_wren__0)); - LUT5 #( - .INIT(32'hAEAEFFAE)) - halt_i_i_2 - (.I0(p_35_out), - .I1(run_stop_d1), - .I2(p_68_out[0]), - .I3(p_68_out[1]), - .I4(soft_reset_d1), - .O(halt_i0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - halt_i_reg - (.C(m_axi_mm2s_aclk), + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(\GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_3 ), - .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ), + .D(p_in_d1_cdc_from), + .Q(s_out_d1_cdc_to), .R(1'b0)); - LUT6 #( - .INIT(64'h222222222222F222)) - halt_reset_i_1 - (.I0(halt_i_reg_0), - .I1(p_68_out[0]), - .I2(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ), - .I3(mm2s_halt_cmplt), - .I4(p_68_out[1]), - .I5(p_35_out), - .O(halt_reset_i_1_n_0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - halt_reset_reg - (.C(m_axi_mm2s_aclk), + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(halt_reset_i_1_n_0), - .Q(halt_i_reg_0), + .D(prmry_in_xored), + .Q(p_in_d1_cdc_from), .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( - .INIT(1'b1)) - prmry_resetn_i_reg - (.C(m_axi_mm2s_aclk), + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1 + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(resetn_i), - .Q(in0), + .D(1'b1), + .Q(srst_d1), .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - run_stop_d1_reg - (.C(m_axi_mm2s_aclk), + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2 + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(\GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_2 ), - .Q(run_stop_d1), + .D(srst_d1), + .Q(srst_d2), .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - s_soft_reset_i_d1_reg - (.C(m_axi_mm2s_aclk), + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3 + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(s_soft_reset_i), - .Q(s_soft_reset_i_d1), + .D(srst_d2), + .Q(srst_d3), .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - s_soft_reset_i_reg - (.C(m_axi_mm2s_aclk), + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4 + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(s_soft_reset_i0), - .Q(s_soft_reset_i), + .D(srst_d3), + .Q(srst_d4), .R(1'b0)); - (* SOFT_HLUTNM = "soft_lutpair122" *) - LUT2 #( - .INIT(4'hE)) - sig_s_h_halt_reg_i_1 - (.I0(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from ), - .I1(sig_rst2all_stop_request), - .O(sig_s_h_halt_reg_reg)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - soft_reset_d1_reg - (.C(m_axi_mm2s_aclk), + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5 + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(p_68_out[1]), - .Q(soft_reset_d1), + .D(srst_d4), + .Q(srst_d5), .R(1'b0)); + LUT2 #( + .INIT(4'hE)) + \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_1__0 + (.I0(p_1_out), + .I1(p_3_out), + .O(SR)); + LUT3 #( + .INIT(8'h28)) + s_out_re + (.I0(srst_d5), + .I1(s_out_d5), + .I2(s_out_d4), + .O(s_out_re__0)); endmodule -(* ORIG_REF_NAME = "axi_vdma_rst_module" *) -module Arty_Z7_20_axi_vdma_0_0_axi_vdma_rst_module - (out, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0, - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from , - prmry_in, - mm2s_halt, - halt_reset, - prmry_reset2, - fifo_wren__0, - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0] , - p_8_out, +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync_10 + (p_in_d1_cdc_from, + p_4_out, SR, - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_0 , - \GEN_LINEBUF_NO_SOF.vsize_counter_reg[12] , - \dmacr_i_reg[2] , - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg , - \cmnds_queued_reg[7] , - reset_counts_reg, - sig_s_h_halt_reg_reg, + prmry_in_xored, m_axi_mm2s_aclk, s_axi_lite_aclk, - m_axis_mm2s_aclk, - p_68_out, - s_soft_reset_i0, - axi_resetn, - dm2linebuf_mm2s_tvalid, - fifo_full_i, - p_23_out, - p_35_out, - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 , - p_15_out, - mm2s_halt_cmplt, - mm2s_axi2ip_wrce, - D, - DIN, - dma_err, - reset_counts, - sig_rst2all_stop_request, - \FSM_sequential_dmacntrl_cs_reg[1] ); - output out; - output sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0; - output \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from ; - output prmry_in; - output mm2s_halt; - output halt_reset; - output prmry_reset2; - output fifo_wren__0; - output [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0] ; - output p_8_out; + p_6_out); + output p_in_d1_cdc_from; + output p_4_out; output [0:0]SR; - output [0:0]\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_0 ; - output [0:0]\GEN_LINEBUF_NO_SOF.vsize_counter_reg[12] ; - output \dmacr_i_reg[2] ; - output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; - output [0:0]\cmnds_queued_reg[7] ; - output reset_counts_reg; - output sig_s_h_halt_reg_reg; + input prmry_in_xored; input m_axi_mm2s_aclk; input s_axi_lite_aclk; - input m_axis_mm2s_aclk; - input [1:0]p_68_out; - input s_soft_reset_i0; - input axi_resetn; - input dm2linebuf_mm2s_tvalid; - input fifo_full_i; - input p_23_out; - input p_35_out; - input \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ; - input p_15_out; - input mm2s_halt_cmplt; - input [0:0]mm2s_axi2ip_wrce; - input [0:0]D; - input [0:0]DIN; - input dma_err; - input reset_counts; - input sig_rst2all_stop_request; - input \FSM_sequential_dmacntrl_cs_reg[1] ; + input p_6_out; - wire [0:0]D; - wire [0:0]DIN; - wire \FSM_sequential_dmacntrl_cs_reg[1] ; - wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ; - wire [0:0]\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_0 ; - wire [0:0]\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0] ; - wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; - wire [0:0]\GEN_LINEBUF_NO_SOF.vsize_counter_reg[12] ; wire [0:0]SR; - wire axi_resetn; - wire [0:0]\cmnds_queued_reg[7] ; - wire dm2linebuf_mm2s_tvalid; - wire dma_err; - wire \dmacr_i_reg[2] ; - wire fifo_full_i; - wire fifo_wren__0; - wire halt_reset; wire m_axi_mm2s_aclk; - wire m_axis_mm2s_aclk; - wire [0:0]mm2s_axi2ip_wrce; - wire mm2s_halt; - wire mm2s_halt_cmplt; - wire p_15_out; - wire p_23_out; - wire p_35_out; - wire [1:0]p_68_out; - wire p_8_out; - wire prmry_in; - wire prmry_reset2; - wire reset_counts; - wire reset_counts_reg; + wire p_4_out; + wire p_6_out; + wire p_in_d1_cdc_from; + wire prmry_in_xored; wire s_axi_lite_aclk; - wire s_soft_reset_i0; - (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_mm2s_axis_resetn; - (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_mm2s_dm_prmry_resetn; - (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_mm2s_prmry_resetn; - wire sig_rst2all_stop_request; - wire sig_s_h_halt_reg_reg; + wire s_out_d1_cdc_to; + wire s_out_d2; + wire s_out_d3; + wire s_out_d4; + wire s_out_d5; + wire s_out_re__0; + wire srst_d1; + wire srst_d2; + wire srst_d3; + wire srst_d4; + wire srst_d5; - assign \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from = sig_mm2s_axis_resetn; - assign out = sig_mm2s_prmry_resetn; - assign sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0 = sig_mm2s_dm_prmry_resetn; - LUT1 #( - .INIT(2'h1)) - \GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out[5]_i_1 - (.I0(sig_mm2s_axis_resetn), - .O(\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_0 )); - LUT1 #( - .INIT(2'h1)) - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_1 - (.I0(sig_mm2s_prmry_resetn), - .O(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0] )); - LUT3 #( - .INIT(8'h0D)) - \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_1 - (.I0(sig_mm2s_axis_resetn), - .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ), - .I2(p_15_out), - .O(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[12] )); - Arty_Z7_20_axi_vdma_0_0_axi_vdma_reset \GEN_RESET_FOR_MM2S.RESET_I - (.D(D), - .DIN(DIN), - .\FSM_sequential_dmacntrl_cs_reg[1] (\FSM_sequential_dmacntrl_cs_reg[1] ), - .\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from (mm2s_halt), - .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ), - .\cmnds_queued_reg[7] (\cmnds_queued_reg[7] ), - .dm2linebuf_mm2s_tvalid(dm2linebuf_mm2s_tvalid), - .dma_err(dma_err), - .\dmacr_i_reg[2] (\dmacr_i_reg[2] ), - .fifo_full_i(fifo_full_i), - .fifo_wren__0(fifo_wren__0), - .halt_i_reg_0(halt_reset), - .in0(sig_mm2s_prmry_resetn), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axis_mm2s_aclk(m_axis_mm2s_aclk), - .mm2s_axi2ip_wrce(mm2s_axi2ip_wrce), - .mm2s_halt_cmplt(mm2s_halt_cmplt), - .out(sig_mm2s_prmry_resetn), - .p_23_out(p_23_out), - .p_35_out(p_35_out), - .p_68_out(p_68_out), - .p_8_out(p_8_out), - .prmry_in(prmry_in), - .prmry_reset2(prmry_reset2), - .reset_counts(reset_counts), - .reset_counts_reg(reset_counts_reg), - .s_axi_lite_aclk(s_axi_lite_aclk), - .s_soft_reset_i0(s_soft_reset_i0), - .scndry_out(sig_mm2s_axis_resetn), - .sig_mm2s_dm_prmry_resetn(sig_mm2s_dm_prmry_resetn), - .sig_rst2all_stop_request(sig_rst2all_stop_request), - .sig_s_h_halt_reg_reg(sig_s_h_halt_reg_reg)); - LUT1 #( - .INIT(2'h1)) - awready_out_i_i_1 - (.I0(prmry_in), - .O(SR)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_out_d1_cdc_to), + .Q(s_out_d2), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_out_d2), + .Q(s_out_d3), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_out_d3), + .Q(s_out_d4), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_out_d4), + .Q(s_out_d5), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_out_re__0), + .Q(p_4_out), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(p_in_d1_cdc_from), + .Q(s_out_d1_cdc_to), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( - .INIT(1'b1)) - hrd_resetn_i_reg + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(prmry_in_xored), + .Q(p_in_d1_cdc_from), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1 (.C(s_axi_lite_aclk), .CE(1'b1), - .D(axi_resetn), - .Q(prmry_in), + .D(1'b1), + .Q(srst_d1), .R(1'b0)); -endmodule - -(* ORIG_REF_NAME = "axi_vdma_skid_buf" *) -module Arty_Z7_20_axi_vdma_0_0_axi_vdma_skid_buf - (out, - m_axis_mm2s_tvalid, - m_axis_mm2s_tlast, - m_axis_mm2s_tuser, - s_valid0, - fifo_pipe_empty, - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tlast_d1_reg , - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tvalid_d1_reg , - m_axis_mm2s_tdata, - m_axis_mm2s_aclk, - m_axis_fifo_ainit_nosync, - fifo_dout, - m_axis_mm2s_tready, - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg , - \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg , - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 , - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 , - p_15_out); - output out; - output m_axis_mm2s_tvalid; - output m_axis_mm2s_tlast; - output [0:0]m_axis_mm2s_tuser; - output s_valid0; - output fifo_pipe_empty; - output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tlast_d1_reg ; - output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tvalid_d1_reg ; - output [31:0]m_axis_mm2s_tdata; - input m_axis_mm2s_aclk; - input m_axis_fifo_ainit_nosync; - input [33:0]fifo_dout; - input m_axis_mm2s_tready; - input \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; - input \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg ; - input \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ; - input \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ; - input p_15_out; - - wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ; - wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ; - wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; - wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tlast_d1_reg ; - wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tvalid_d1_reg ; - wire \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg ; - wire [33:0]fifo_dout; - wire fifo_pipe_empty; - wire m_axis_fifo_ainit_nosync; - wire m_axis_mm2s_aclk; - wire [31:0]m_axis_mm2s_tdata; - wire m_axis_mm2s_tlast; - wire m_axis_mm2s_tready; - wire [0:0]m_axis_mm2s_tuser; - wire p_15_out; - wire s_valid0; - wire sig_data_reg_out_en; - wire [31:0]sig_data_skid_mux_out; - wire [31:0]sig_data_skid_reg; - wire sig_last_skid_mux_out; - wire sig_last_skid_reg; - (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_m_valid_dup; - wire sig_m_valid_dup_i_1_n_0; - (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_m_valid_out; - wire sig_reset_reg; - (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_s_ready_dup; - wire sig_s_ready_dup_i_1_n_0; - (* RTL_KEEP = "true" *) (* equivalent_register_removal = "no" *) wire sig_s_ready_out; - wire sig_user_skid_mux_out; - wire sig_user_skid_reg; - - assign m_axis_mm2s_tvalid = sig_m_valid_out; - assign out = sig_s_ready_out; - LUT2 #( - .INIT(4'h2)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_1__1 - (.I0(\GEN_LINEBUF_NO_SOF.all_lines_xfred_reg ), - .I1(sig_m_valid_out), - .O(fifo_pipe_empty)); - LUT4 #( - .INIT(16'h0020)) - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tlast_d1_i_1 - (.I0(m_axis_mm2s_tlast), - .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ), - .I2(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ), - .I3(p_15_out), - .O(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tlast_d1_reg )); - LUT4 #( - .INIT(16'h0020)) - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tvalid_d1_i_1 - (.I0(sig_m_valid_out), - .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 ), - .I2(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ), - .I3(p_15_out), - .O(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tvalid_d1_reg )); - LUT2 #( - .INIT(4'h8)) - s_valid_i_1 - (.I0(m_axis_mm2s_tready), - .I1(sig_m_valid_out), - .O(s_valid0)); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[0]_i_1 - (.I0(fifo_dout[0]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[0]), - .O(sig_data_skid_mux_out[0])); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[10]_i_1 - (.I0(fifo_dout[10]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[10]), - .O(sig_data_skid_mux_out[10])); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[11]_i_1 - (.I0(fifo_dout[11]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[11]), - .O(sig_data_skid_mux_out[11])); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[12]_i_1 - (.I0(fifo_dout[12]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[12]), - .O(sig_data_skid_mux_out[12])); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[13]_i_1 - (.I0(fifo_dout[13]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[13]), - .O(sig_data_skid_mux_out[13])); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[14]_i_1 - (.I0(fifo_dout[14]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[14]), - .O(sig_data_skid_mux_out[14])); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[15]_i_1 - (.I0(fifo_dout[15]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[15]), - .O(sig_data_skid_mux_out[15])); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[16]_i_1 - (.I0(fifo_dout[16]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[16]), - .O(sig_data_skid_mux_out[16])); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[17]_i_1 - (.I0(fifo_dout[17]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[17]), - .O(sig_data_skid_mux_out[17])); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[18]_i_1 - (.I0(fifo_dout[18]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[18]), - .O(sig_data_skid_mux_out[18])); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[19]_i_1 - (.I0(fifo_dout[19]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[19]), - .O(sig_data_skid_mux_out[19])); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[1]_i_1 - (.I0(fifo_dout[1]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[1]), - .O(sig_data_skid_mux_out[1])); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[20]_i_1 - (.I0(fifo_dout[20]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[20]), - .O(sig_data_skid_mux_out[20])); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[21]_i_1 - (.I0(fifo_dout[21]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[21]), - .O(sig_data_skid_mux_out[21])); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[22]_i_1 - (.I0(fifo_dout[22]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[22]), - .O(sig_data_skid_mux_out[22])); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[23]_i_1 - (.I0(fifo_dout[23]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[23]), - .O(sig_data_skid_mux_out[23])); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[24]_i_1 - (.I0(fifo_dout[24]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[24]), - .O(sig_data_skid_mux_out[24])); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[25]_i_1 - (.I0(fifo_dout[25]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[25]), - .O(sig_data_skid_mux_out[25])); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[26]_i_1 - (.I0(fifo_dout[26]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[26]), - .O(sig_data_skid_mux_out[26])); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[27]_i_1 - (.I0(fifo_dout[27]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[27]), - .O(sig_data_skid_mux_out[27])); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[28]_i_1 - (.I0(fifo_dout[28]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[28]), - .O(sig_data_skid_mux_out[28])); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[29]_i_1 - (.I0(fifo_dout[29]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[29]), - .O(sig_data_skid_mux_out[29])); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[2]_i_1 - (.I0(fifo_dout[2]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[2]), - .O(sig_data_skid_mux_out[2])); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[30]_i_1 - (.I0(fifo_dout[30]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[30]), - .O(sig_data_skid_mux_out[30])); - LUT2 #( - .INIT(4'hB)) - \sig_data_reg_out[31]_i_2 - (.I0(m_axis_mm2s_tready), - .I1(sig_m_valid_dup), - .O(sig_data_reg_out_en)); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[31]_i_3 - (.I0(fifo_dout[31]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[31]), - .O(sig_data_skid_mux_out[31])); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[3]_i_1 - (.I0(fifo_dout[3]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[3]), - .O(sig_data_skid_mux_out[3])); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[4]_i_1 - (.I0(fifo_dout[4]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[4]), - .O(sig_data_skid_mux_out[4])); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[5]_i_1 - (.I0(fifo_dout[5]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[5]), - .O(sig_data_skid_mux_out[5])); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[6]_i_1 - (.I0(fifo_dout[6]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[6]), - .O(sig_data_skid_mux_out[6])); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[7]_i_1 - (.I0(fifo_dout[7]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[7]), - .O(sig_data_skid_mux_out[7])); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[8]_i_1 - (.I0(fifo_dout[8]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[8]), - .O(sig_data_skid_mux_out[8])); - LUT3 #( - .INIT(8'hB8)) - \sig_data_reg_out[9]_i_1 - (.I0(fifo_dout[9]), - .I1(sig_s_ready_dup), - .I2(sig_data_skid_reg[9]), - .O(sig_data_skid_mux_out[9])); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[0] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[0]), - .Q(m_axis_mm2s_tdata[0]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(srst_d1), + .Q(srst_d2), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[10] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[10]), - .Q(m_axis_mm2s_tdata[10]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(srst_d2), + .Q(srst_d3), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[11] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[11]), - .Q(m_axis_mm2s_tdata[11]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(srst_d3), + .Q(srst_d4), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[12] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[12]), - .Q(m_axis_mm2s_tdata[12]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(srst_d4), + .Q(srst_d5), + .R(1'b0)); + LUT2 #( + .INIT(4'hE)) + \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_1 + (.I0(p_4_out), + .I1(p_6_out), + .O(SR)); + LUT3 #( + .INIT(8'h28)) + s_out_re + (.I0(srst_d5), + .I1(s_out_d5), + .I2(s_out_d4), + .O(s_out_re__0)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync_13 + (p_6_out, + m_axi_mm2s_aclk, + s_axi_lite_aclk, + s_soft_reset_i_d1, + s_soft_reset_i); + output p_6_out; + input m_axi_mm2s_aclk; + input s_axi_lite_aclk; + input s_soft_reset_i_d1; + input s_soft_reset_i; + + wire m_axi_mm2s_aclk; + wire p_6_out; + wire p_in_d1_cdc_from; + wire prmry_in_xored; + wire s_axi_lite_aclk; + wire s_out_d1_cdc_to; + wire s_out_d2; + wire s_out_d3; + wire s_out_d4; + wire s_out_d5; + wire s_out_re__0; + wire s_soft_reset_i; + wire s_soft_reset_i_d1; + wire srst_d1; + wire srst_d2; + wire srst_d3; + wire srst_d4; + wire srst_d5; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[13] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[13]), - .Q(m_axis_mm2s_tdata[13]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_out_d1_cdc_to), + .Q(s_out_d2), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[14] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[14]), - .Q(m_axis_mm2s_tdata[14]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_out_d2), + .Q(s_out_d3), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[15] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[15]), - .Q(m_axis_mm2s_tdata[15]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_out_d3), + .Q(s_out_d4), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_out_d4), + .Q(s_out_d5), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_out_re__0), + .Q(p_6_out), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[16] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[16]), - .Q(m_axis_mm2s_tdata[16]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(p_in_d1_cdc_from), + .Q(s_out_d1_cdc_to), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[17] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[17]), - .Q(m_axis_mm2s_tdata[17]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(prmry_in_xored), + .Q(p_in_d1_cdc_from), + .R(1'b0)); + LUT3 #( + .INIT(8'hB4)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1 + (.I0(s_soft_reset_i_d1), + .I1(s_soft_reset_i), + .I2(p_in_d1_cdc_from), + .O(prmry_in_xored)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[18] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[18]), - .Q(m_axis_mm2s_tdata[18]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b1), + .Q(srst_d1), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[19] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[19]), - .Q(m_axis_mm2s_tdata[19]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(srst_d1), + .Q(srst_d2), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[1] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[1]), - .Q(m_axis_mm2s_tdata[1]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(srst_d2), + .Q(srst_d3), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[20] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[20]), - .Q(m_axis_mm2s_tdata[20]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(srst_d3), + .Q(srst_d4), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[21] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[21]), - .Q(m_axis_mm2s_tdata[21]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(srst_d4), + .Q(srst_d5), + .R(1'b0)); + LUT3 #( + .INIT(8'h28)) + s_out_re + (.I0(srst_d5), + .I1(s_out_d5), + .I2(s_out_d4), + .O(s_out_re__0)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync_3 + (p_3_out, + m_axi_s2mm_aclk, + s_axis_s2mm_aclk, + s_soft_reset_i_d1, + s_soft_reset_i); + output p_3_out; + input m_axi_s2mm_aclk; + input s_axis_s2mm_aclk; + input s_soft_reset_i_d1; + input s_soft_reset_i; + + wire m_axi_s2mm_aclk; + wire p_3_out; + wire p_in_d1_cdc_from; + wire prmry_in_xored; + wire s_axis_s2mm_aclk; + wire s_out_d1_cdc_to; + wire s_out_d2; + wire s_out_d3; + wire s_out_d4; + wire s_out_d5; + wire s_out_re__0; + wire s_soft_reset_i; + wire s_soft_reset_i_d1; + wire srst_d1; + wire srst_d2; + wire srst_d3; + wire srst_d4; + wire srst_d5; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[22] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[22]), - .Q(m_axis_mm2s_tdata[22]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(s_out_d1_cdc_to), + .Q(s_out_d2), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[23] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[23]), - .Q(m_axis_mm2s_tdata[23]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(s_out_d2), + .Q(s_out_d3), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[24] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[24]), - .Q(m_axis_mm2s_tdata[24]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(s_out_d3), + .Q(s_out_d4), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[25] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[25]), - .Q(m_axis_mm2s_tdata[25]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(s_out_d4), + .Q(s_out_d5), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[26] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[26]), - .Q(m_axis_mm2s_tdata[26]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(s_out_re__0), + .Q(p_3_out), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[27] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[27]), - .Q(m_axis_mm2s_tdata[27]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(p_in_d1_cdc_from), + .Q(s_out_d1_cdc_to), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[28] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[28]), - .Q(m_axis_mm2s_tdata[28]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(prmry_in_xored), + .Q(p_in_d1_cdc_from), + .R(1'b0)); + LUT3 #( + .INIT(8'hB4)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__5 + (.I0(s_soft_reset_i_d1), + .I1(s_soft_reset_i), + .I2(p_in_d1_cdc_from), + .O(prmry_in_xored)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[29] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[29]), - .Q(m_axis_mm2s_tdata[29]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(1'b1), + .Q(srst_d1), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[2] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[2]), - .Q(m_axis_mm2s_tdata[2]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(srst_d1), + .Q(srst_d2), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[30] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[30]), - .Q(m_axis_mm2s_tdata[30]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(srst_d2), + .Q(srst_d3), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[31] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[31]), - .Q(m_axis_mm2s_tdata[31]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(srst_d3), + .Q(srst_d4), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[3] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[3]), - .Q(m_axis_mm2s_tdata[3]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(srst_d4), + .Q(srst_d5), + .R(1'b0)); + LUT3 #( + .INIT(8'h28)) + s_out_re + (.I0(srst_d5), + .I1(s_out_d5), + .I2(s_out_d4), + .O(s_out_re__0)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync_4 + (p_in_d1_cdc_from, + p_4_out, + SR, + prmry_in_xored, + m_axi_s2mm_aclk, + s_axi_lite_aclk, + p_6_out); + output p_in_d1_cdc_from; + output p_4_out; + output [0:0]SR; + input prmry_in_xored; + input m_axi_s2mm_aclk; + input s_axi_lite_aclk; + input p_6_out; + + wire [0:0]SR; + wire m_axi_s2mm_aclk; + wire p_4_out; + wire p_6_out; + wire p_in_d1_cdc_from; + wire prmry_in_xored; + wire s_axi_lite_aclk; + wire s_out_d1_cdc_to; + wire s_out_d2; + wire s_out_d3; + wire s_out_d4; + wire s_out_d5; + wire s_out_re__0; + wire srst_d1; + wire srst_d2; + wire srst_d3; + wire srst_d4; + wire srst_d5; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[4] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[4]), - .Q(m_axis_mm2s_tdata[4]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_out_d1_cdc_to), + .Q(s_out_d2), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[5] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[5]), - .Q(m_axis_mm2s_tdata[5]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_out_d2), + .Q(s_out_d3), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[6] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[6]), - .Q(m_axis_mm2s_tdata[6]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_out_d3), + .Q(s_out_d4), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[7] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[7]), - .Q(m_axis_mm2s_tdata[7]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_out_d4), + .Q(s_out_d5), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[8] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[8]), - .Q(m_axis_mm2s_tdata[8]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_out_re__0), + .Q(p_4_out), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_reg_out_reg[9] - (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_data_skid_mux_out[9]), - .Q(m_axis_mm2s_tdata[9]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(p_in_d1_cdc_from), + .Q(s_out_d1_cdc_to), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[0] - (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[0]), - .Q(sig_data_skid_reg[0]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(prmry_in_xored), + .Q(p_in_d1_cdc_from), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[10] - (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[10]), - .Q(sig_data_skid_reg[10]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b1), + .Q(srst_d1), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[11] - (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[11]), - .Q(sig_data_skid_reg[11]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(srst_d1), + .Q(srst_d2), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[12] - (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[12]), - .Q(sig_data_skid_reg[12]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(srst_d2), + .Q(srst_d3), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[13] - (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[13]), - .Q(sig_data_skid_reg[13]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(srst_d3), + .Q(srst_d4), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[14] - (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[14]), - .Q(sig_data_skid_reg[14]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(srst_d4), + .Q(srst_d5), + .R(1'b0)); + LUT2 #( + .INIT(4'hE)) + \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_1__0 + (.I0(p_4_out), + .I1(p_6_out), + .O(SR)); + LUT3 #( + .INIT(8'h28)) + s_out_re + (.I0(srst_d5), + .I1(s_out_d5), + .I2(s_out_d4), + .O(s_out_re__0)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync_5 + (p_6_out, + m_axi_s2mm_aclk, + s_axi_lite_aclk, + s_soft_reset_i_d1, + s_soft_reset_i); + output p_6_out; + input m_axi_s2mm_aclk; + input s_axi_lite_aclk; + input s_soft_reset_i_d1; + input s_soft_reset_i; + + wire m_axi_s2mm_aclk; + wire p_6_out; + wire p_in_d1_cdc_from; + wire prmry_in_xored; + wire s_axi_lite_aclk; + wire s_out_d1_cdc_to; + wire s_out_d2; + wire s_out_d3; + wire s_out_d4; + wire s_out_d5; + wire s_out_re__0; + wire s_soft_reset_i; + wire s_soft_reset_i_d1; + wire srst_d1; + wire srst_d2; + wire srst_d3; + wire srst_d4; + wire srst_d5; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[15] - (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[15]), - .Q(sig_data_skid_reg[15]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_out_d1_cdc_to), + .Q(s_out_d2), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[16] - (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[16]), - .Q(sig_data_skid_reg[16]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_out_d2), + .Q(s_out_d3), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[17] - (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[17]), - .Q(sig_data_skid_reg[17]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_out_d3), + .Q(s_out_d4), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[18] - (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[18]), - .Q(sig_data_skid_reg[18]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_out_d4), + .Q(s_out_d5), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[19] - (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[19]), - .Q(sig_data_skid_reg[19]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_out_re__0), + .Q(p_6_out), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[1] - (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[1]), - .Q(sig_data_skid_reg[1]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(p_in_d1_cdc_from), + .Q(s_out_d1_cdc_to), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[20] - (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[20]), - .Q(sig_data_skid_reg[20]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(prmry_in_xored), + .Q(p_in_d1_cdc_from), + .R(1'b0)); + LUT3 #( + .INIT(8'hB4)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__3 + (.I0(s_soft_reset_i_d1), + .I1(s_soft_reset_i), + .I2(p_in_d1_cdc_from), + .O(prmry_in_xored)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[21] - (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[21]), - .Q(sig_data_skid_reg[21]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(1'b1), + .Q(srst_d1), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[22] - (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[22]), - .Q(sig_data_skid_reg[22]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(srst_d1), + .Q(srst_d2), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[23] - (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[23]), - .Q(sig_data_skid_reg[23]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(srst_d2), + .Q(srst_d3), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[24] - (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[24]), - .Q(sig_data_skid_reg[24]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(srst_d3), + .Q(srst_d4), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[25] - (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[25]), - .Q(sig_data_skid_reg[25]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(srst_d4), + .Q(srst_d5), + .R(1'b0)); + LUT3 #( + .INIT(8'h28)) + s_out_re + (.I0(srst_d5), + .I1(s_out_d5), + .I2(s_out_d4), + .O(s_out_re__0)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync_6 + (p_in_d1_cdc_from, + p_1_out, + SR, + prmry_in_xored, + m_axi_mm2s_aclk, + m_axis_mm2s_aclk, + p_3_out); + output p_in_d1_cdc_from; + output p_1_out; + output [0:0]SR; + input prmry_in_xored; + input m_axi_mm2s_aclk; + input m_axis_mm2s_aclk; + input p_3_out; + + wire [0:0]SR; + wire m_axi_mm2s_aclk; + wire m_axis_mm2s_aclk; + wire p_1_out; + wire p_3_out; + wire p_in_d1_cdc_from; + wire prmry_in_xored; + wire s_out_d1_cdc_to; + wire s_out_d2; + wire s_out_d3; + wire s_out_d4; + wire s_out_d5; + wire s_out_re__0; + wire srst_d1; + wire srst_d2; + wire srst_d3; + wire srst_d4; + wire srst_d5; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[26] + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2 (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[26]), - .Q(sig_data_skid_reg[26]), - .R(m_axis_fifo_ainit_nosync)); + .CE(1'b1), + .D(s_out_d1_cdc_to), + .Q(s_out_d2), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[27] + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3 (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[27]), - .Q(sig_data_skid_reg[27]), - .R(m_axis_fifo_ainit_nosync)); + .CE(1'b1), + .D(s_out_d2), + .Q(s_out_d3), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[28] + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4 (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[28]), - .Q(sig_data_skid_reg[28]), - .R(m_axis_fifo_ainit_nosync)); + .CE(1'b1), + .D(s_out_d3), + .Q(s_out_d4), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[29] + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5 (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[29]), - .Q(sig_data_skid_reg[29]), - .R(m_axis_fifo_ainit_nosync)); + .CE(1'b1), + .D(s_out_d4), + .Q(s_out_d5), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[2] + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[2]), - .Q(sig_data_skid_reg[2]), - .R(m_axis_fifo_ainit_nosync)); + .CE(1'b1), + .D(s_out_re__0), + .Q(p_1_out), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[30] + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[30]), - .Q(sig_data_skid_reg[30]), - .R(m_axis_fifo_ainit_nosync)); + .CE(1'b1), + .D(p_in_d1_cdc_from), + .Q(s_out_d1_cdc_to), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[31] - (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[31]), - .Q(sig_data_skid_reg[31]), - .R(m_axis_fifo_ainit_nosync)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(prmry_in_xored), + .Q(p_in_d1_cdc_from), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[3] + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1 (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[3]), - .Q(sig_data_skid_reg[3]), - .R(m_axis_fifo_ainit_nosync)); + .CE(1'b1), + .D(1'b1), + .Q(srst_d1), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[4] + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2 (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[4]), - .Q(sig_data_skid_reg[4]), - .R(m_axis_fifo_ainit_nosync)); + .CE(1'b1), + .D(srst_d1), + .Q(srst_d2), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[5] + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3 (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[5]), - .Q(sig_data_skid_reg[5]), - .R(m_axis_fifo_ainit_nosync)); + .CE(1'b1), + .D(srst_d2), + .Q(srst_d3), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[6] + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4 (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[6]), - .Q(sig_data_skid_reg[6]), - .R(m_axis_fifo_ainit_nosync)); + .CE(1'b1), + .D(srst_d3), + .Q(srst_d4), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[7] + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5 (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[7]), - .Q(sig_data_skid_reg[7]), - .R(m_axis_fifo_ainit_nosync)); + .CE(1'b1), + .D(srst_d4), + .Q(srst_d5), + .R(1'b0)); + LUT2 #( + .INIT(4'hE)) + \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_1 + (.I0(p_1_out), + .I1(p_3_out), + .O(SR)); + LUT3 #( + .INIT(8'h28)) + s_out_re + (.I0(srst_d5), + .I1(s_out_d5), + .I2(s_out_d4), + .O(s_out_re__0)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync_9 + (p_3_out, + m_axi_mm2s_aclk, + m_axis_mm2s_aclk, + s_soft_reset_i_d1, + s_soft_reset_i); + output p_3_out; + input m_axi_mm2s_aclk; + input m_axis_mm2s_aclk; + input s_soft_reset_i_d1; + input s_soft_reset_i; + + wire m_axi_mm2s_aclk; + wire m_axis_mm2s_aclk; + wire p_3_out; + wire p_in_d1_cdc_from; + wire prmry_in_xored; + wire s_out_d1_cdc_to; + wire s_out_d2; + wire s_out_d3; + wire s_out_d4; + wire s_out_d5; + wire s_out_re__0; + wire s_soft_reset_i; + wire s_soft_reset_i_d1; + wire srst_d1; + wire srst_d2; + wire srst_d3; + wire srst_d4; + wire srst_d5; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[8] + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2 (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[8]), - .Q(sig_data_skid_reg[8]), - .R(m_axis_fifo_ainit_nosync)); + .CE(1'b1), + .D(s_out_d1_cdc_to), + .Q(s_out_d2), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_data_skid_reg_reg[9] + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3 (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[9]), - .Q(sig_data_skid_reg[9]), - .R(m_axis_fifo_ainit_nosync)); - LUT3 #( - .INIT(8'hB8)) - sig_last_reg_out_i_1 - (.I0(fifo_dout[32]), - .I1(sig_s_ready_dup), - .I2(sig_last_skid_reg), - .O(sig_last_skid_mux_out)); + .CE(1'b1), + .D(s_out_d2), + .Q(s_out_d3), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - sig_last_reg_out_reg + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4 (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_last_skid_mux_out), - .Q(m_axis_mm2s_tlast), - .R(m_axis_fifo_ainit_nosync)); + .CE(1'b1), + .D(s_out_d3), + .Q(s_out_d4), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - sig_last_skid_reg_reg + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5 (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[32]), - .Q(sig_last_skid_reg), - .R(m_axis_fifo_ainit_nosync)); - LUT6 #( - .INIT(64'h00000000000070FF)) - sig_m_valid_dup_i_1 - (.I0(sig_s_ready_dup), - .I1(m_axis_mm2s_tready), - .I2(sig_m_valid_dup), - .I3(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ), - .I4(m_axis_fifo_ainit_nosync), - .I5(sig_reset_reg), - .O(sig_m_valid_dup_i_1_n_0)); - (* KEEP = "yes" *) - (* equivalent_register_removal = "no" *) + .CE(1'b1), + .D(s_out_d4), + .Q(s_out_d5), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - sig_m_valid_dup_reg + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out (.C(m_axis_mm2s_aclk), .CE(1'b1), - .D(sig_m_valid_dup_i_1_n_0), - .Q(sig_m_valid_dup), + .D(s_out_re__0), + .Q(p_3_out), .R(1'b0)); - (* KEEP = "yes" *) - (* equivalent_register_removal = "no" *) + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - sig_m_valid_out_reg + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to (.C(m_axis_mm2s_aclk), .CE(1'b1), - .D(sig_m_valid_dup_i_1_n_0), - .Q(sig_m_valid_out), + .D(p_in_d1_cdc_from), + .Q(s_out_d1_cdc_to), .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - sig_reset_reg_reg + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(prmry_in_xored), + .Q(p_in_d1_cdc_from), + .R(1'b0)); + LUT3 #( + .INIT(8'hB4)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__1 + (.I0(s_soft_reset_i_d1), + .I1(s_soft_reset_i), + .I2(p_in_d1_cdc_from), + .O(prmry_in_xored)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1 (.C(m_axis_mm2s_aclk), .CE(1'b1), - .D(m_axis_fifo_ainit_nosync), - .Q(sig_reset_reg), + .D(1'b1), + .Q(srst_d1), .R(1'b0)); - LUT6 #( - .INIT(64'h00000000FFFFFFA2)) - sig_s_ready_dup_i_1 - (.I0(sig_s_ready_dup), - .I1(sig_m_valid_dup), - .I2(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ), - .I3(m_axis_mm2s_tready), - .I4(sig_reset_reg), - .I5(m_axis_fifo_ainit_nosync), - .O(sig_s_ready_dup_i_1_n_0)); - (* KEEP = "yes" *) - (* equivalent_register_removal = "no" *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - sig_s_ready_dup_reg + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2 (.C(m_axis_mm2s_aclk), .CE(1'b1), - .D(sig_s_ready_dup_i_1_n_0), - .Q(sig_s_ready_dup), + .D(srst_d1), + .Q(srst_d2), .R(1'b0)); - (* KEEP = "yes" *) - (* equivalent_register_removal = "no" *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - sig_s_ready_out_reg + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3 (.C(m_axis_mm2s_aclk), .CE(1'b1), - .D(sig_s_ready_dup_i_1_n_0), - .Q(sig_s_ready_out), + .D(srst_d2), + .Q(srst_d3), .R(1'b0)); - LUT3 #( - .INIT(8'hB8)) - \sig_user_reg_out[0]_i_1 - (.I0(fifo_dout[33]), - .I1(sig_s_ready_dup), - .I2(sig_user_skid_reg), - .O(sig_user_skid_mux_out)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_user_reg_out_reg[0] + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4 (.C(m_axis_mm2s_aclk), - .CE(sig_data_reg_out_en), - .D(sig_user_skid_mux_out), - .Q(m_axis_mm2s_tuser), - .R(m_axis_fifo_ainit_nosync)); + .CE(1'b1), + .D(srst_d3), + .Q(srst_d4), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \sig_user_skid_reg_reg[0] + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5 (.C(m_axis_mm2s_aclk), - .CE(sig_s_ready_dup), - .D(fifo_dout[33]), - .Q(sig_user_skid_reg), - .R(m_axis_fifo_ainit_nosync)); -endmodule - -(* ORIG_REF_NAME = "axi_vdma_sm" *) -module Arty_Z7_20_axi_vdma_0_0_axi_vdma_sm - (tstvect_fsync_d1, - frame_sync_reg, - s_axis_cmd_tvalid_reg, - zero_vsize_err, - zero_hsize_err, - \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 , - \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg_0 , - load_new_addr, - p_37_out, - \cmnds_queued_reg[7]_0 , - p_10_out, - DI, - S, - \cmnds_queued_reg[7]_1 , - D, - dma_interr_reg, - p_0_in, - m_axi_mm2s_aclk, - p_0_out, - zero_vsize_err0, - zero_hsize_err0, - p_23_out, - O, - \stride_vid_reg[7] , - \stride_vid_reg[11] , - \stride_vid_reg[15] , - dmacntrl_ns14_out, - Q, - s_axis_cmd_tvalid_reg_0, - \vsize_vid_reg[12] , - err_i_reg, - halt_i_reg, - p_57_out, - \INFERRED_GEN.cnt_i_reg[2] , - \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg , - CO, - out, - p_68_out, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] , - mm2s_axi2ip_wrce, - interr_i_reg, - dma_interr_reg_0, - \hsize_vid_reg[15] , - halt_i_reg_0, - \cmnds_queued_reg[5]_0 , - p_3_in, - mm2s_halt, - dma_err, - err_i_reg_0); - output tstvect_fsync_d1; - output frame_sync_reg; - output s_axis_cmd_tvalid_reg; - output zero_vsize_err; - output zero_hsize_err; - output [15:0]\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 ; - output \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg_0 ; - output load_new_addr; - output p_37_out; - output [5:0]\cmnds_queued_reg[7]_0 ; - output p_10_out; - output [0:0]DI; - output [3:0]S; - output [2:0]\cmnds_queued_reg[7]_1 ; - output [48:0]D; - output dma_interr_reg; - input p_0_in; - input m_axi_mm2s_aclk; - input p_0_out; - input zero_vsize_err0; - input zero_hsize_err0; - input p_23_out; - input [3:0]O; - input [3:0]\stride_vid_reg[7] ; - input [3:0]\stride_vid_reg[11] ; - input [3:0]\stride_vid_reg[15] ; - input dmacntrl_ns14_out; - input [15:0]Q; - input s_axis_cmd_tvalid_reg_0; - input [12:0]\vsize_vid_reg[12] ; - input err_i_reg; - input halt_i_reg; - input p_57_out; - input [0:0]\INFERRED_GEN.cnt_i_reg[2] ; - input \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg ; - input [0:0]CO; - input out; - input [1:0]p_68_out; - input [0:0]\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] ; - input [0:0]mm2s_axi2ip_wrce; - input interr_i_reg; - input dma_interr_reg_0; - input [15:0]\hsize_vid_reg[15] ; - input [0:0]halt_i_reg_0; - input [6:0]\cmnds_queued_reg[5]_0 ; - input p_3_in; - input mm2s_halt; - input dma_err; - input err_i_reg_0; - - wire [0:0]CO; - wire [48:0]D; - wire [0:0]DI; - wire \FSM_sequential_dmacntrl_cs[0]_i_1_n_0 ; - wire \FSM_sequential_dmacntrl_cs[0]_i_2_n_0 ; - wire \FSM_sequential_dmacntrl_cs[0]_i_3_n_0 ; - wire \FSM_sequential_dmacntrl_cs[0]_i_4_n_0 ; - wire \FSM_sequential_dmacntrl_cs[1]_i_1_n_0 ; - wire \FSM_sequential_dmacntrl_cs[1]_i_2_n_0 ; - wire \FSM_sequential_dmacntrl_cs[2]_i_1_n_0 ; - wire \FSM_sequential_dmacntrl_cs[2]_i_2_n_0 ; - wire \FSM_sequential_dmacntrl_cs[2]_i_3_n_0 ; - wire \FSM_sequential_dmacntrl_cs[2]_i_4_n_0 ; - wire \FSM_sequential_dmacntrl_cs[2]_i_5_n_0 ; - wire \FSM_sequential_dmacntrl_cs[2]_i_6_n_0 ; - wire \FSM_sequential_dmacntrl_cs[2]_i_7_n_0 ; - wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_5_n_0 ; - wire \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_i_1_n_0 ; - wire \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg_0 ; - wire [0:0]\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data[23]_i_1_n_0 ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ; - wire [15:0]\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[0] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[10] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[11] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[12] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[13] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[14] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[15] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[1] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[23] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[2] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[32] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[33] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[34] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[35] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[36] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[37] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[38] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[39] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[3] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[40] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[41] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[42] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[43] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[44] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[45] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[46] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[47] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[48] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[49] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[4] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[50] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[51] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[52] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[53] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[54] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[55] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[56] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[57] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[58] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[59] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[5] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[60] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[61] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[62] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[63] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[6] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[7] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[8] ; - wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[9] ; - wire \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg ; - wire [0:0]\INFERRED_GEN.cnt_i_reg[2] ; - wire [3:0]O; - wire [15:0]Q; - wire [3:0]S; - wire all_lines_xfred_d1; - wire \cmnds_queued[0]_i_1_n_0 ; - wire \cmnds_queued[7]_i_2_n_0 ; - wire [6:0]\cmnds_queued_reg[5]_0 ; - wire [5:0]\cmnds_queued_reg[7]_0 ; - wire [2:0]\cmnds_queued_reg[7]_1 ; - wire [7:6]cmnds_queued_reg__0; - wire \dm_address[0]_i_1_n_0 ; - wire \dm_address[16]_i_2_n_0 ; - wire \dm_address[16]_i_3_n_0 ; - wire \dm_address[16]_i_4_n_0 ; - wire \dm_address[16]_i_5_n_0 ; - wire \dm_address[20]_i_2_n_0 ; - wire \dm_address[20]_i_3_n_0 ; - wire \dm_address[20]_i_4_n_0 ; - wire \dm_address[20]_i_5_n_0 ; - wire \dm_address[24]_i_2_n_0 ; - wire \dm_address[24]_i_3_n_0 ; - wire \dm_address[24]_i_4_n_0 ; - wire \dm_address[24]_i_5_n_0 ; - wire \dm_address[28]_i_2_n_0 ; - wire \dm_address[28]_i_3_n_0 ; - wire \dm_address[28]_i_4_n_0 ; - wire \dm_address[28]_i_5_n_0 ; - wire [31:16]dm_address_reg; - wire \dm_address_reg[16]_i_1_n_0 ; - wire \dm_address_reg[16]_i_1_n_1 ; - wire \dm_address_reg[16]_i_1_n_2 ; - wire \dm_address_reg[16]_i_1_n_3 ; - wire \dm_address_reg[16]_i_1_n_4 ; - wire \dm_address_reg[16]_i_1_n_5 ; - wire \dm_address_reg[16]_i_1_n_6 ; - wire \dm_address_reg[16]_i_1_n_7 ; - wire \dm_address_reg[20]_i_1_n_0 ; - wire \dm_address_reg[20]_i_1_n_1 ; - wire \dm_address_reg[20]_i_1_n_2 ; - wire \dm_address_reg[20]_i_1_n_3 ; - wire \dm_address_reg[20]_i_1_n_4 ; - wire \dm_address_reg[20]_i_1_n_5 ; - wire \dm_address_reg[20]_i_1_n_6 ; - wire \dm_address_reg[20]_i_1_n_7 ; - wire \dm_address_reg[24]_i_1_n_0 ; - wire \dm_address_reg[24]_i_1_n_1 ; - wire \dm_address_reg[24]_i_1_n_2 ; - wire \dm_address_reg[24]_i_1_n_3 ; - wire \dm_address_reg[24]_i_1_n_4 ; - wire \dm_address_reg[24]_i_1_n_5 ; - wire \dm_address_reg[24]_i_1_n_6 ; - wire \dm_address_reg[24]_i_1_n_7 ; - wire \dm_address_reg[28]_i_1_n_1 ; - wire \dm_address_reg[28]_i_1_n_2 ; - wire \dm_address_reg[28]_i_1_n_3 ; - wire \dm_address_reg[28]_i_1_n_4 ; - wire \dm_address_reg[28]_i_1_n_5 ; - wire \dm_address_reg[28]_i_1_n_6 ; - wire \dm_address_reg[28]_i_1_n_7 ; - wire dma_err; - wire dma_interr_reg; - wire dma_interr_reg_0; - (* RTL_KEEP = "yes" *) wire [2:0]dmacntrl_cs; - wire dmacntrl_ns14_out; - wire err_i_reg; - wire err_i_reg_0; - wire frame_sync_d3; - wire frame_sync_reg; - wire halt_i_reg; - wire [0:0]halt_i_reg_0; - wire [15:0]\hsize_vid_reg[15] ; - wire interr_i_reg; - wire load_new_addr; - wire m_axi_mm2s_aclk; - wire [0:0]mm2s_axi2ip_wrce; - wire mm2s_halt; - wire out; - wire p_0_in; - wire p_0_out; - wire p_10_out; - wire p_23_out; - wire p_37_out; - wire p_3_in; - wire p_57_out; - wire [1:0]p_68_out; - wire s_axis_cmd_tvalid_reg; - wire s_axis_cmd_tvalid_reg_0; - wire [3:0]\stride_vid_reg[11] ; - wire [3:0]\stride_vid_reg[15] ; - wire [3:0]\stride_vid_reg[7] ; - wire sts_idle; - wire tstvect_fsync_d1; - wire tstvect_fsync_d2; - wire \vert_count[0]_i_10_n_0 ; - wire \vert_count[0]_i_1_n_0 ; - wire \vert_count[0]_i_3_n_0 ; - wire \vert_count[0]_i_4_n_0 ; - wire \vert_count[0]_i_5_n_0 ; - wire \vert_count[0]_i_6_n_0 ; - wire \vert_count[0]_i_7_n_0 ; - wire \vert_count[0]_i_8_n_0 ; - wire \vert_count[0]_i_9_n_0 ; - wire \vert_count[12]_i_2_n_0 ; - wire \vert_count[4]_i_2_n_0 ; - wire \vert_count[4]_i_3_n_0 ; - wire \vert_count[4]_i_4_n_0 ; - wire \vert_count[4]_i_5_n_0 ; - wire \vert_count[4]_i_6_n_0 ; - wire \vert_count[4]_i_7_n_0 ; - wire \vert_count[4]_i_8_n_0 ; - wire \vert_count[4]_i_9_n_0 ; - wire \vert_count[8]_i_2_n_0 ; - wire \vert_count[8]_i_3_n_0 ; - wire \vert_count[8]_i_4_n_0 ; - wire \vert_count[8]_i_5_n_0 ; - wire \vert_count[8]_i_6_n_0 ; - wire \vert_count[8]_i_7_n_0 ; - wire \vert_count[8]_i_8_n_0 ; - wire \vert_count[8]_i_9_n_0 ; - wire [12:0]vert_count_reg; - wire \vert_count_reg[0]_i_2_n_0 ; - wire \vert_count_reg[0]_i_2_n_1 ; - wire \vert_count_reg[0]_i_2_n_2 ; - wire \vert_count_reg[0]_i_2_n_3 ; - wire \vert_count_reg[0]_i_2_n_4 ; - wire \vert_count_reg[0]_i_2_n_5 ; - wire \vert_count_reg[0]_i_2_n_6 ; - wire \vert_count_reg[0]_i_2_n_7 ; - wire \vert_count_reg[12]_i_1_n_7 ; - wire \vert_count_reg[4]_i_1_n_0 ; - wire \vert_count_reg[4]_i_1_n_1 ; - wire \vert_count_reg[4]_i_1_n_2 ; - wire \vert_count_reg[4]_i_1_n_3 ; - wire \vert_count_reg[4]_i_1_n_4 ; - wire \vert_count_reg[4]_i_1_n_5 ; - wire \vert_count_reg[4]_i_1_n_6 ; - wire \vert_count_reg[4]_i_1_n_7 ; - wire \vert_count_reg[8]_i_1_n_0 ; - wire \vert_count_reg[8]_i_1_n_1 ; - wire \vert_count_reg[8]_i_1_n_2 ; - wire \vert_count_reg[8]_i_1_n_3 ; - wire \vert_count_reg[8]_i_1_n_4 ; - wire \vert_count_reg[8]_i_1_n_5 ; - wire \vert_count_reg[8]_i_1_n_6 ; - wire \vert_count_reg[8]_i_1_n_7 ; - wire [12:0]\vsize_vid_reg[12] ; - wire write_cmnd_cmb; - wire zero_hsize_err; - wire zero_hsize_err0; - wire zero_vsize_err; - wire zero_vsize_err0; - wire [3:3]\NLW_dm_address_reg[28]_i_1_CO_UNCONNECTED ; - wire [3:0]\NLW_vert_count_reg[12]_i_1_CO_UNCONNECTED ; - wire [3:1]\NLW_vert_count_reg[12]_i_1_O_UNCONNECTED ; - - LUT6 #( - .INIT(64'hB888FFFFB8880000)) - \FSM_sequential_dmacntrl_cs[0]_i_1 - (.I0(\FSM_sequential_dmacntrl_cs[0]_i_2_n_0 ), - .I1(dmacntrl_cs[0]), - .I2(\FSM_sequential_dmacntrl_cs[0]_i_3_n_0 ), - .I3(\FSM_sequential_dmacntrl_cs[0]_i_4_n_0 ), - .I4(\FSM_sequential_dmacntrl_cs[2]_i_4_n_0 ), - .I5(dmacntrl_cs[0]), - .O(\FSM_sequential_dmacntrl_cs[0]_i_1_n_0 )); - LUT4 #( - .INIT(16'h0062)) - \FSM_sequential_dmacntrl_cs[0]_i_2 - (.I0(dmacntrl_cs[2]), - .I1(dmacntrl_cs[1]), - .I2(s_axis_cmd_tvalid_reg_0), - .I3(dmacntrl_ns14_out), - .O(\FSM_sequential_dmacntrl_cs[0]_i_2_n_0 )); - LUT6 #( - .INIT(64'h00000002FFFFFFFF)) - \FSM_sequential_dmacntrl_cs[0]_i_3 - (.I0(p_68_out[0]), - .I1(frame_sync_reg), - .I2(mm2s_halt), - .I3(p_68_out[1]), - .I4(dma_err), - .I5(dmacntrl_cs[1]), - .O(\FSM_sequential_dmacntrl_cs[0]_i_3_n_0 )); - LUT6 #( - .INIT(64'h555555555557555F)) - \FSM_sequential_dmacntrl_cs[0]_i_4 - (.I0(dmacntrl_cs[2]), - .I1(dmacntrl_cs[1]), - .I2(p_3_in), - .I3(frame_sync_reg), - .I4(p_68_out[0]), - .I5(\FSM_sequential_dmacntrl_cs[2]_i_5_n_0 ), - .O(\FSM_sequential_dmacntrl_cs[0]_i_4_n_0 )); + .CE(1'b1), + .D(srst_d4), + .Q(srst_d5), + .R(1'b0)); LUT3 #( - .INIT(8'hB8)) - \FSM_sequential_dmacntrl_cs[1]_i_1 - (.I0(\FSM_sequential_dmacntrl_cs[1]_i_2_n_0 ), - .I1(\FSM_sequential_dmacntrl_cs[2]_i_4_n_0 ), - .I2(dmacntrl_cs[1]), - .O(\FSM_sequential_dmacntrl_cs[1]_i_1_n_0 )); - LUT6 #( - .INIT(64'h04000A0004555F00)) - \FSM_sequential_dmacntrl_cs[1]_i_2 - (.I0(dmacntrl_cs[2]), - .I1(s_axis_cmd_tvalid_reg_0), - .I2(dmacntrl_ns14_out), - .I3(dmacntrl_cs[0]), - .I4(dmacntrl_cs[1]), - .I5(err_i_reg_0), - .O(\FSM_sequential_dmacntrl_cs[1]_i_2_n_0 )); - LUT6 #( - .INIT(64'hB888FFFFB8880000)) - \FSM_sequential_dmacntrl_cs[2]_i_1 - (.I0(\FSM_sequential_dmacntrl_cs[2]_i_2_n_0 ), - .I1(dmacntrl_cs[0]), - .I2(dmacntrl_cs[2]), - .I3(\FSM_sequential_dmacntrl_cs[2]_i_3_n_0 ), - .I4(\FSM_sequential_dmacntrl_cs[2]_i_4_n_0 ), - .I5(dmacntrl_cs[2]), - .O(\FSM_sequential_dmacntrl_cs[2]_i_1_n_0 )); - LUT4 #( - .INIT(16'h0010)) - \FSM_sequential_dmacntrl_cs[2]_i_2 - (.I0(dmacntrl_cs[2]), - .I1(s_axis_cmd_tvalid_reg_0), - .I2(dmacntrl_cs[1]), - .I3(dmacntrl_ns14_out), - .O(\FSM_sequential_dmacntrl_cs[2]_i_2_n_0 )); - LUT6 #( - .INIT(64'h0000000000000001)) - \FSM_sequential_dmacntrl_cs[2]_i_3 - (.I0(dmacntrl_cs[1]), - .I1(\FSM_sequential_dmacntrl_cs[2]_i_5_n_0 ), - .I2(frame_sync_reg), - .I3(mm2s_halt), - .I4(p_68_out[1]), - .I5(dma_err), - .O(\FSM_sequential_dmacntrl_cs[2]_i_3_n_0 )); - LUT4 #( - .INIT(16'h5F5E)) - \FSM_sequential_dmacntrl_cs[2]_i_4 - (.I0(dmacntrl_cs[1]), - .I1(dmacntrl_cs[0]), - .I2(dmacntrl_cs[2]), - .I3(err_i_reg), - .O(\FSM_sequential_dmacntrl_cs[2]_i_4_n_0 )); - LUT6 #( - .INIT(64'h0000000000000001)) - \FSM_sequential_dmacntrl_cs[2]_i_5 - (.I0(\FSM_sequential_dmacntrl_cs[2]_i_6_n_0 ), - .I1(\FSM_sequential_dmacntrl_cs[2]_i_7_n_0 ), - .I2(vert_count_reg[6]), - .I3(vert_count_reg[7]), - .I4(vert_count_reg[4]), - .I5(vert_count_reg[5]), - .O(\FSM_sequential_dmacntrl_cs[2]_i_5_n_0 )); - LUT5 #( - .INIT(32'hFFFFFFFE)) - \FSM_sequential_dmacntrl_cs[2]_i_6 - (.I0(vert_count_reg[11]), - .I1(vert_count_reg[9]), - .I2(vert_count_reg[8]), - .I3(vert_count_reg[12]), - .I4(vert_count_reg[10]), - .O(\FSM_sequential_dmacntrl_cs[2]_i_6_n_0 )); - LUT4 #( - .INIT(16'hFFFE)) - \FSM_sequential_dmacntrl_cs[2]_i_7 - (.I0(vert_count_reg[2]), - .I1(vert_count_reg[3]), - .I2(vert_count_reg[0]), - .I3(vert_count_reg[1]), - .O(\FSM_sequential_dmacntrl_cs[2]_i_7_n_0 )); - (* KEEP = "yes" *) - FDRE \FSM_sequential_dmacntrl_cs_reg[0] - (.C(m_axi_mm2s_aclk), + .INIT(8'h28)) + s_out_re + (.I0(srst_d5), + .I1(s_out_d5), + .I2(s_out_d4), + .O(s_out_re__0)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized0 + (scndry_out, + s_axi_lite_aclk, + \cmnds_queued_reg[0] , + m_axi_s2mm_aclk); + output scndry_out; + input s_axi_lite_aclk; + input \cmnds_queued_reg[0] ; + input m_axi_s2mm_aclk; + + wire \cmnds_queued_reg[0] ; + wire m_axi_s2mm_aclk; + wire p_level_in_d1_cdc_from; + wire s_axi_lite_aclk; + wire s_level_out_d1_cdc_to; + wire s_level_out_d2; + wire s_level_out_d3; + wire scndry_out; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_lite_aclk), .CE(1'b1), - .D(\FSM_sequential_dmacntrl_cs[0]_i_1_n_0 ), - .Q(dmacntrl_cs[0]), - .R(p_0_in)); - (* KEEP = "yes" *) - FDRE \FSM_sequential_dmacntrl_cs_reg[1] - (.C(m_axi_mm2s_aclk), + .D(p_level_in_d1_cdc_from), + .Q(s_level_out_d1_cdc_to), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 + (.C(s_axi_lite_aclk), .CE(1'b1), - .D(\FSM_sequential_dmacntrl_cs[1]_i_1_n_0 ), - .Q(dmacntrl_cs[1]), - .R(p_0_in)); - (* KEEP = "yes" *) - FDRE \FSM_sequential_dmacntrl_cs_reg[2] - (.C(m_axi_mm2s_aclk), + .D(s_level_out_d1_cdc_to), + .Q(s_level_out_d2), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 + (.C(s_axi_lite_aclk), .CE(1'b1), - .D(\FSM_sequential_dmacntrl_cs[2]_i_1_n_0 ), - .Q(dmacntrl_cs[2]), - .R(p_0_in)); - LUT5 #( - .INIT(32'h00000002)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_1 - (.I0(sts_idle), - .I1(dmacntrl_cs[1]), - .I2(err_i_reg), - .I3(dmacntrl_cs[2]), - .I4(dmacntrl_cs[0]), - .O(p_37_out)); - LUT6 #( - .INIT(64'h0000000000000002)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_2 - (.I0(halt_i_reg), - .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_5_n_0 ), - .I2(cmnds_queued_reg__0[6]), - .I3(cmnds_queued_reg__0[7]), - .I4(\cmnds_queued_reg[7]_0 [4]), - .I5(\cmnds_queued_reg[7]_0 [5]), - .O(sts_idle)); - (* SOFT_HLUTNM = "soft_lutpair7" *) - LUT4 #( - .INIT(16'hFFFE)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_5 - (.I0(\cmnds_queued_reg[7]_0 [2]), - .I1(\cmnds_queued_reg[7]_0 [3]), - .I2(\cmnds_queued_reg[7]_0 [0]), - .I3(\cmnds_queued_reg[7]_0 [1]), - .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_5_n_0 )); + .D(s_level_out_d2), + .Q(s_level_out_d3), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.all_lines_xfred_d1_reg - (.C(m_axi_mm2s_aclk), + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 + (.C(s_axi_lite_aclk), .CE(1'b1), - .D(p_0_out), - .Q(all_lines_xfred_d1), - .R(p_0_in)); - LUT6 #( - .INIT(64'h00AEFFFFFFFFFFFF)) - \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_i_1 - (.I0(\GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg_0 ), - .I1(all_lines_xfred_d1), - .I2(p_0_out), - .I3(p_23_out), - .I4(p_68_out[0]), - .I5(out), - .O(\GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_i_1_n_0 )); + .D(s_level_out_d3), + .Q(scndry_out), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg - (.C(m_axi_mm2s_aclk), + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(\GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_i_1_n_0 ), - .Q(\GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg_0 ), + .D(\cmnds_queued_reg[0] ), + .Q(p_level_in_d1_cdc_from), .R(1'b0)); - (* SOFT_HLUTNM = "soft_lutpair8" *) - LUT3 #( - .INIT(8'hB8)) - \GEN_NORMAL_DM_COMMAND.cmnd_data[23]_i_1 - (.I0(out), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .I2(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[23] ), - .O(\GEN_NORMAL_DM_COMMAND.cmnd_data[23]_i_1_n_0 )); - LUT2 #( - .INIT(4'h2)) - \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1 - (.I0(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .I1(out), - .O(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - LUT6 #( - .INIT(64'h00000008FFFFFFFF)) - \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2 - (.I0(dmacntrl_cs[1]), - .I1(dmacntrl_cs[0]), - .I2(dmacntrl_cs[2]), - .I3(dmacntrl_ns14_out), - .I4(s_axis_cmd_tvalid_reg_0), - .I5(out), - .O(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[0] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\hsize_vid_reg[15] [0]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[0] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[10] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\hsize_vid_reg[15] [10]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[10] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[11] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\hsize_vid_reg[15] [11]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[11] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[12] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\hsize_vid_reg[15] [12]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[12] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[13] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\hsize_vid_reg[15] [13]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[13] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[14] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\hsize_vid_reg[15] [14]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[14] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\hsize_vid_reg[15] [15]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[15] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\hsize_vid_reg[15] [1]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[1] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[23] - (.C(m_axi_mm2s_aclk), +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized0_11 + (scndry_out, + s_axi_lite_aclk, + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 , + m_axi_mm2s_aclk); + output scndry_out; + input s_axi_lite_aclk; + input \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ; + input m_axi_mm2s_aclk; + + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ; + wire m_axi_mm2s_aclk; + wire p_level_in_d1_cdc_from; + wire s_axi_lite_aclk; + wire s_level_out_d1_cdc_to; + wire s_level_out_d2; + wire s_level_out_d3; + wire scndry_out; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axi_lite_aclk), .CE(1'b1), - .D(\GEN_NORMAL_DM_COMMAND.cmnd_data[23]_i_1_n_0 ), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[23] ), + .D(p_level_in_d1_cdc_from), + .Q(s_level_out_d1_cdc_to), .R(1'b0)); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\hsize_vid_reg[15] [2]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[2] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[32] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [0]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[32] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[33] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [1]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[33] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[34] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [2]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[34] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[35] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [3]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[35] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[36] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [4]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[36] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[37] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [5]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[37] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[38] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [6]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[38] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[39] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [7]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[39] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[3] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\hsize_vid_reg[15] [3]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[3] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[40] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [8]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[40] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[41] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [9]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[41] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[42] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [10]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[42] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[43] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [11]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[43] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[44] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [12]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[44] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[45] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [13]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[45] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[46] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [14]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[46] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [15]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[47] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[48] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(dm_address_reg[16]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[48] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[49] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(dm_address_reg[17]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[49] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[4] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\hsize_vid_reg[15] [4]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[4] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[50] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(dm_address_reg[18]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[50] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[51] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(dm_address_reg[19]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[51] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[52] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(dm_address_reg[20]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[52] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[53] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(dm_address_reg[21]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[53] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[54] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(dm_address_reg[22]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[54] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[55] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(dm_address_reg[23]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[55] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[56] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(dm_address_reg[24]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[56] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[57] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(dm_address_reg[25]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[57] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[58] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(dm_address_reg[26]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[58] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[59] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(dm_address_reg[27]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[59] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[5] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\hsize_vid_reg[15] [5]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[5] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[60] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(dm_address_reg[28]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[60] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[61] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(dm_address_reg[29]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[61] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[62] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(dm_address_reg[30]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[62] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[63] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(dm_address_reg[31]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[63] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[6] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\hsize_vid_reg[15] [6]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[6] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[7] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\hsize_vid_reg[15] [7]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[7] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[8] - (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\hsize_vid_reg[15] [8]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[8] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - FDRE \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[9] + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_level_out_d1_cdc_to), + .Q(s_level_out_d2), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_level_out_d2), + .Q(s_level_out_d3), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(s_level_out_d3), + .Q(scndry_out), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from (.C(m_axi_mm2s_aclk), - .CE(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0 ), - .D(\hsize_vid_reg[15] [9]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[9] ), - .R(\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0 )); - LUT5 #( - .INIT(32'h01000000)) - \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_i_1 - (.I0(s_axis_cmd_tvalid_reg_0), - .I1(dmacntrl_ns14_out), - .I2(dmacntrl_cs[2]), - .I3(dmacntrl_cs[0]), - .I4(dmacntrl_cs[1]), - .O(write_cmnd_cmb)); + .CE(1'b1), + .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ), + .Q(p_level_in_d1_cdc_from), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized1 + (prmry_in_xored, + scndry_out, + prmry_in_xored_0, + SR, + \GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_reg , + prmry_min_assert_sftrst, + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 , + p_in_d1_cdc_from, + p_in_d1_cdc_from_1, + s_soft_reset_i_d1, + s_soft_reset_i, + p_11_out, + m_axi_s2mm_aclk, + lite_min_assert_sftrst, + s_axi_lite_aclk); + output prmry_in_xored; + output scndry_out; + output prmry_in_xored_0; + output [0:0]SR; + output \GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_reg ; + input prmry_min_assert_sftrst; + input \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ; + input p_in_d1_cdc_from; + input p_in_d1_cdc_from_1; + input s_soft_reset_i_d1; + input s_soft_reset_i; + input p_11_out; + input m_axi_s2mm_aclk; + input lite_min_assert_sftrst; + input s_axi_lite_aclk; + + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ; + wire \GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_reg ; + wire [0:0]SR; + wire lite_min_assert_sftrst; + wire m_axi_s2mm_aclk; + wire p_11_out; + wire p_in_d1_cdc_from; + wire p_in_d1_cdc_from_1; + wire p_level_in_d1_cdc_from; + wire prmry_in_xored; + wire prmry_in_xored_0; + wire prmry_min_assert_sftrst; + wire s_axi_lite_aclk; + wire s_level_out_d1_cdc_to; + wire s_level_out_d2; + wire s_level_out_d3; + wire s_soft_reset_i; + wire s_soft_reset_i_d1; + wire scndry_out; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg - (.C(m_axi_mm2s_aclk), + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(write_cmnd_cmb), - .Q(s_axis_cmd_tvalid_reg), - .R(p_0_in)); + .D(p_level_in_d1_cdc_from), + .Q(s_level_out_d1_cdc_to), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s_level_out_d1_cdc_to), + .Q(s_level_out_d2), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s_level_out_d2), + .Q(s_level_out_d3), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s_level_out_d3), + .Q(scndry_out), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(lite_min_assert_sftrst), + .Q(p_level_in_d1_cdc_from), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair264" *) + LUT4 #( + .INIT(16'h7F80)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__4 + (.I0(scndry_out), + .I1(prmry_min_assert_sftrst), + .I2(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ), + .I3(p_in_d1_cdc_from), + .O(prmry_in_xored)); + (* SOFT_HLUTNM = "soft_lutpair264" *) + LUT4 #( + .INIT(16'h7F80)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__6 + (.I0(scndry_out), + .I1(prmry_min_assert_sftrst), + .I2(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ), + .I3(p_in_d1_cdc_from_1), + .O(prmry_in_xored_0)); LUT6 #( - .INIT(64'hFFFFFFF7FFFFFFF0)) - \I_DMA_REGISTER/dma_interr_i_1 - (.I0(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4] ), - .I1(mm2s_axi2ip_wrce), - .I2(interr_i_reg), - .I3(zero_vsize_err), - .I4(zero_hsize_err), - .I5(dma_interr_reg_0), - .O(dma_interr_reg)); - LUT2 #( - .INIT(4'h8)) - \MASTER_MODE_FRAME_CNT.tstvect_fsync_i_1 - (.I0(tstvect_fsync_d2), - .I1(\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg ), - .O(p_10_out)); - (* SOFT_HLUTNM = "soft_lutpair7" *) - LUT1 #( - .INIT(2'h1)) - \cmnds_queued[0]_i_1 - (.I0(\cmnds_queued_reg[7]_0 [0]), - .O(\cmnds_queued[0]_i_1_n_0 )); - LUT3 #( - .INIT(8'hA6)) - \cmnds_queued[7]_i_2 - (.I0(s_axis_cmd_tvalid_reg), - .I1(p_57_out), - .I2(\INFERRED_GEN.cnt_i_reg[2] ), - .O(\cmnds_queued[7]_i_2_n_0 )); + .INIT(64'h00FFF2F2FFFFF2F2)) + \GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_i_1__0 + (.I0(s_soft_reset_i), + .I1(s_soft_reset_i_d1), + .I2(p_11_out), + .I3(scndry_out), + .I4(prmry_min_assert_sftrst), + .I5(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ), + .O(\GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_reg )); + LUT5 #( + .INIT(32'h80FF8080)) + \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_1__0 + (.I0(scndry_out), + .I1(prmry_min_assert_sftrst), + .I2(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ), + .I3(s_soft_reset_i_d1), + .I4(s_soft_reset_i), + .O(SR)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized12 + (p_in_d1_cdc_from, + s2mm_packet_sof, + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[0] , + prmry_reset2, + prmry_in_xored_1, + s_axis_s2mm_aclk, + SR, + m_axi_s2mm_aclk, + reset_counts, + s2mm_cdc2dmac_fsync, + irqdelay_wren_i); + output p_in_d1_cdc_from; + output s2mm_packet_sof; + output \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[0] ; + input prmry_reset2; + input prmry_in_xored_1; + input s_axis_s2mm_aclk; + input [0:0]SR; + input m_axi_s2mm_aclk; + input reset_counts; + input s2mm_cdc2dmac_fsync; + input irqdelay_wren_i; + + wire \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[0] ; + wire [0:0]SR; + wire irqdelay_wren_i; + wire m_axi_s2mm_aclk; + wire p_in_d1_cdc_from; + wire prmry_in_xored_1; + wire prmry_reset2; + wire reset_counts; + wire s2mm_cdc2dmac_fsync; + wire s2mm_packet_sof; + wire s_axis_s2mm_aclk; + wire s_out_d1_cdc_to; + wire s_out_d2; + wire s_out_d3; + wire s_out_d4; + wire s_out_d5; + wire s_out_re__0; + wire srst_d1; + wire srst_d2; + wire srst_d3; + wire srst_d4; + wire srst_d5; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \cmnds_queued_reg[0] - (.C(m_axi_mm2s_aclk), - .CE(\cmnds_queued[7]_i_2_n_0 ), - .D(\cmnds_queued[0]_i_1_n_0 ), - .Q(\cmnds_queued_reg[7]_0 [0]), - .R(halt_i_reg_0)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s_out_d1_cdc_to), + .Q(s_out_d2), + .R(SR)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \cmnds_queued_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(\cmnds_queued[7]_i_2_n_0 ), - .D(\cmnds_queued_reg[5]_0 [0]), - .Q(\cmnds_queued_reg[7]_0 [1]), - .R(halt_i_reg_0)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s_out_d2), + .Q(s_out_d3), + .R(SR)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \cmnds_queued_reg[2] + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s_out_d3), + .Q(s_out_d4), + .R(SR)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s_out_d4), + .Q(s_out_d5), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s_out_re__0), + .Q(s2mm_packet_sof), + .R(SR)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(p_in_d1_cdc_from), + .Q(s_out_d1_cdc_to), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(prmry_in_xored_1), + .Q(p_in_d1_cdc_from), + .R(prmry_reset2)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(1'b1), + .Q(srst_d1), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(srst_d1), + .Q(srst_d2), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(srst_d2), + .Q(srst_d3), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(srst_d3), + .Q(srst_d4), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(srst_d4), + .Q(srst_d5), + .R(SR)); + LUT4 #( + .INIT(16'hFFFE)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_3 + (.I0(s2mm_packet_sof), + .I1(reset_counts), + .I2(s2mm_cdc2dmac_fsync), + .I3(irqdelay_wren_i), + .O(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[0] )); + LUT3 #( + .INIT(8'h28)) + s_out_re + (.I0(srst_d5), + .I1(s_out_d5), + .I2(s_out_d4), + .O(s_out_re__0)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized12_38 + (p_in_d1_cdc_from, + p_17_out, + SR, + prmry_in_xored, + m_axis_mm2s_aclk, + prmry_resetn_i_reg, + m_axi_mm2s_aclk); + output p_in_d1_cdc_from; + output p_17_out; + input [0:0]SR; + input prmry_in_xored; + input m_axis_mm2s_aclk; + input [0:0]prmry_resetn_i_reg; + input m_axi_mm2s_aclk; + + wire [0:0]SR; + wire m_axi_mm2s_aclk; + wire m_axis_mm2s_aclk; + wire p_17_out; + wire p_in_d1_cdc_from; + wire prmry_in_xored; + wire [0:0]prmry_resetn_i_reg; + wire s_out_d1_cdc_to; + wire s_out_d2; + wire s_out_d3; + wire s_out_d4; + wire s_out_d5; + wire s_out_re__0; + wire srst_d1; + wire srst_d2; + wire srst_d3; + wire srst_d4; + wire srst_d5; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2 (.C(m_axi_mm2s_aclk), - .CE(\cmnds_queued[7]_i_2_n_0 ), - .D(\cmnds_queued_reg[5]_0 [1]), - .Q(\cmnds_queued_reg[7]_0 [2]), - .R(halt_i_reg_0)); + .CE(1'b1), + .D(s_out_d1_cdc_to), + .Q(s_out_d2), + .R(prmry_resetn_i_reg)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \cmnds_queued_reg[3] + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3 (.C(m_axi_mm2s_aclk), - .CE(\cmnds_queued[7]_i_2_n_0 ), - .D(\cmnds_queued_reg[5]_0 [2]), - .Q(\cmnds_queued_reg[7]_0 [3]), - .R(halt_i_reg_0)); + .CE(1'b1), + .D(s_out_d2), + .Q(s_out_d3), + .R(prmry_resetn_i_reg)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \cmnds_queued_reg[4] + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4 (.C(m_axi_mm2s_aclk), - .CE(\cmnds_queued[7]_i_2_n_0 ), - .D(\cmnds_queued_reg[5]_0 [3]), - .Q(\cmnds_queued_reg[7]_0 [4]), - .R(halt_i_reg_0)); + .CE(1'b1), + .D(s_out_d3), + .Q(s_out_d4), + .R(prmry_resetn_i_reg)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \cmnds_queued_reg[5] + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5 (.C(m_axi_mm2s_aclk), - .CE(\cmnds_queued[7]_i_2_n_0 ), - .D(\cmnds_queued_reg[5]_0 [4]), - .Q(\cmnds_queued_reg[7]_0 [5]), - .R(halt_i_reg_0)); + .CE(1'b1), + .D(s_out_d4), + .Q(s_out_d5), + .R(prmry_resetn_i_reg)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \cmnds_queued_reg[6] + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out (.C(m_axi_mm2s_aclk), - .CE(\cmnds_queued[7]_i_2_n_0 ), - .D(\cmnds_queued_reg[5]_0 [5]), - .Q(cmnds_queued_reg__0[6]), - .R(halt_i_reg_0)); + .CE(1'b1), + .D(s_out_re__0), + .Q(p_17_out), + .R(prmry_resetn_i_reg)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \cmnds_queued_reg[7] + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to (.C(m_axi_mm2s_aclk), - .CE(\cmnds_queued[7]_i_2_n_0 ), - .D(\cmnds_queued_reg[5]_0 [6]), - .Q(cmnds_queued_reg__0[7]), - .R(halt_i_reg_0)); - LUT5 #( - .INIT(32'hAABAAAAA)) - \dm_address[0]_i_1 - (.I0(load_new_addr), - .I1(dmacntrl_ns14_out), - .I2(dmacntrl_cs[0]), - .I3(dmacntrl_cs[1]), - .I4(dmacntrl_cs[2]), - .O(\dm_address[0]_i_1_n_0 )); - LUT3 #( - .INIT(8'hB8)) - \dm_address[16]_i_2 - (.I0(Q[3]), - .I1(load_new_addr), - .I2(dm_address_reg[19]), - .O(\dm_address[16]_i_2_n_0 )); - LUT3 #( - .INIT(8'hB8)) - \dm_address[16]_i_3 - (.I0(Q[2]), - .I1(load_new_addr), - .I2(dm_address_reg[18]), - .O(\dm_address[16]_i_3_n_0 )); - LUT3 #( - .INIT(8'hB8)) - \dm_address[16]_i_4 - (.I0(Q[1]), - .I1(load_new_addr), - .I2(dm_address_reg[17]), - .O(\dm_address[16]_i_4_n_0 )); - LUT3 #( - .INIT(8'hB8)) - \dm_address[16]_i_5 - (.I0(Q[0]), - .I1(load_new_addr), - .I2(dm_address_reg[16]), - .O(\dm_address[16]_i_5_n_0 )); - LUT3 #( - .INIT(8'hB8)) - \dm_address[20]_i_2 - (.I0(Q[7]), - .I1(load_new_addr), - .I2(dm_address_reg[23]), - .O(\dm_address[20]_i_2_n_0 )); - LUT3 #( - .INIT(8'hB8)) - \dm_address[20]_i_3 - (.I0(Q[6]), - .I1(load_new_addr), - .I2(dm_address_reg[22]), - .O(\dm_address[20]_i_3_n_0 )); - LUT3 #( - .INIT(8'hB8)) - \dm_address[20]_i_4 - (.I0(Q[5]), - .I1(load_new_addr), - .I2(dm_address_reg[21]), - .O(\dm_address[20]_i_4_n_0 )); - LUT3 #( - .INIT(8'hB8)) - \dm_address[20]_i_5 - (.I0(Q[4]), - .I1(load_new_addr), - .I2(dm_address_reg[20]), - .O(\dm_address[20]_i_5_n_0 )); - LUT3 #( - .INIT(8'hB8)) - \dm_address[24]_i_2 - (.I0(Q[11]), - .I1(load_new_addr), - .I2(dm_address_reg[27]), - .O(\dm_address[24]_i_2_n_0 )); - LUT3 #( - .INIT(8'hB8)) - \dm_address[24]_i_3 - (.I0(Q[10]), - .I1(load_new_addr), - .I2(dm_address_reg[26]), - .O(\dm_address[24]_i_3_n_0 )); - LUT3 #( - .INIT(8'hB8)) - \dm_address[24]_i_4 - (.I0(Q[9]), - .I1(load_new_addr), - .I2(dm_address_reg[25]), - .O(\dm_address[24]_i_4_n_0 )); - LUT3 #( - .INIT(8'hB8)) - \dm_address[24]_i_5 - (.I0(Q[8]), - .I1(load_new_addr), - .I2(dm_address_reg[24]), - .O(\dm_address[24]_i_5_n_0 )); - LUT3 #( - .INIT(8'hB8)) - \dm_address[28]_i_2 - (.I0(Q[15]), - .I1(load_new_addr), - .I2(dm_address_reg[31]), - .O(\dm_address[28]_i_2_n_0 )); - LUT3 #( - .INIT(8'hB8)) - \dm_address[28]_i_3 - (.I0(Q[14]), - .I1(load_new_addr), - .I2(dm_address_reg[30]), - .O(\dm_address[28]_i_3_n_0 )); - LUT3 #( - .INIT(8'hB8)) - \dm_address[28]_i_4 - (.I0(Q[13]), - .I1(load_new_addr), - .I2(dm_address_reg[29]), - .O(\dm_address[28]_i_4_n_0 )); - LUT3 #( - .INIT(8'hB8)) - \dm_address[28]_i_5 - (.I0(Q[12]), - .I1(load_new_addr), - .I2(dm_address_reg[28]), - .O(\dm_address[28]_i_5_n_0 )); + .CE(1'b1), + .D(p_in_d1_cdc_from), + .Q(s_out_d1_cdc_to), + .R(prmry_resetn_i_reg)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(prmry_in_xored), + .Q(p_in_d1_cdc_from), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[0] + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1 (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(O[0]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [0]), - .R(p_0_in)); + .CE(1'b1), + .D(1'b1), + .Q(srst_d1), + .R(prmry_resetn_i_reg)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[10] + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2 (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(\stride_vid_reg[11] [2]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [10]), - .R(p_0_in)); + .CE(1'b1), + .D(srst_d1), + .Q(srst_d2), + .R(prmry_resetn_i_reg)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[11] + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3 (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(\stride_vid_reg[11] [3]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [11]), - .R(p_0_in)); + .CE(1'b1), + .D(srst_d2), + .Q(srst_d3), + .R(prmry_resetn_i_reg)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[12] + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4 (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(\stride_vid_reg[15] [0]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [12]), - .R(p_0_in)); + .CE(1'b1), + .D(srst_d3), + .Q(srst_d4), + .R(prmry_resetn_i_reg)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[13] + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5 (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(\stride_vid_reg[15] [1]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [13]), - .R(p_0_in)); + .CE(1'b1), + .D(srst_d4), + .Q(srst_d5), + .R(prmry_resetn_i_reg)); + LUT3 #( + .INIT(8'h28)) + s_out_re + (.I0(srst_d5), + .I1(s_out_d5), + .I2(s_out_d4), + .O(s_out_re__0)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized13 + (s2mm_cdc2dmac_fsync, + s2mm_valid_frame_sync_cmb, + prmry_reset2, + s_axis_s2mm_aclk, + SR, + m_axi_s2mm_aclk, + s2mm_valid_video_prmtrs, + s_fsync_d1, + s_fsync_d2); + output s2mm_cdc2dmac_fsync; + output s2mm_valid_frame_sync_cmb; + input prmry_reset2; + input s_axis_s2mm_aclk; + input [0:0]SR; + input m_axi_s2mm_aclk; + input s2mm_valid_video_prmtrs; + input s_fsync_d1; + input s_fsync_d2; + + wire [0:0]SR; + wire m_axi_s2mm_aclk; + wire p_in_d1_cdc_from; + wire prmry_in_xored; + wire prmry_reset2; + wire s2mm_cdc2dmac_fsync; + wire s2mm_valid_frame_sync_cmb; + wire s2mm_valid_video_prmtrs; + wire s_axis_s2mm_aclk; + wire s_fsync_d1; + wire s_fsync_d2; + wire s_out_d1_cdc_to; + wire s_out_d2; + wire s_out_d3; + wire s_out_d4; + wire s_out_d5; + wire s_out_re__0; + wire srst_d1; + wire srst_d2; + wire srst_d3; + wire srst_d4; + wire srst_d5; + + LUT2 #( + .INIT(4'h8)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.valid_frame_sync_d1_i_1 + (.I0(s2mm_cdc2dmac_fsync), + .I1(s2mm_valid_video_prmtrs), + .O(s2mm_valid_frame_sync_cmb)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[14] - (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(\stride_vid_reg[15] [2]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [14]), - .R(p_0_in)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s_out_d1_cdc_to), + .Q(s_out_d2), + .R(SR)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[15] - (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(\stride_vid_reg[15] [3]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [15]), - .R(p_0_in)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s_out_d2), + .Q(s_out_d3), + .R(SR)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[16] - (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(\dm_address_reg[16]_i_1_n_7 ), - .Q(dm_address_reg[16]), - .R(p_0_in)); - (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) - CARRY4 \dm_address_reg[16]_i_1 - (.CI(CO), - .CO({\dm_address_reg[16]_i_1_n_0 ,\dm_address_reg[16]_i_1_n_1 ,\dm_address_reg[16]_i_1_n_2 ,\dm_address_reg[16]_i_1_n_3 }), - .CYINIT(1'b0), - .DI({1'b0,1'b0,1'b0,1'b0}), - .O({\dm_address_reg[16]_i_1_n_4 ,\dm_address_reg[16]_i_1_n_5 ,\dm_address_reg[16]_i_1_n_6 ,\dm_address_reg[16]_i_1_n_7 }), - .S({\dm_address[16]_i_2_n_0 ,\dm_address[16]_i_3_n_0 ,\dm_address[16]_i_4_n_0 ,\dm_address[16]_i_5_n_0 })); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s_out_d3), + .Q(s_out_d4), + .R(SR)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[17] - (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(\dm_address_reg[16]_i_1_n_6 ), - .Q(dm_address_reg[17]), - .R(p_0_in)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s_out_d4), + .Q(s_out_d5), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[18] - (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(\dm_address_reg[16]_i_1_n_5 ), - .Q(dm_address_reg[18]), - .R(p_0_in)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s_out_re__0), + .Q(s2mm_cdc2dmac_fsync), + .R(SR)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[19] - (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(\dm_address_reg[16]_i_1_n_4 ), - .Q(dm_address_reg[19]), - .R(p_0_in)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(p_in_d1_cdc_from), + .Q(s_out_d1_cdc_to), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(O[1]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [1]), - .R(p_0_in)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(prmry_in_xored), + .Q(p_in_d1_cdc_from), + .R(prmry_reset2)); + LUT3 #( + .INIT(8'hB4)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__16 + (.I0(s_fsync_d1), + .I1(s_fsync_d2), + .I2(p_in_d1_cdc_from), + .O(prmry_in_xored)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[20] - (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(\dm_address_reg[20]_i_1_n_7 ), - .Q(dm_address_reg[20]), - .R(p_0_in)); - (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) - CARRY4 \dm_address_reg[20]_i_1 - (.CI(\dm_address_reg[16]_i_1_n_0 ), - .CO({\dm_address_reg[20]_i_1_n_0 ,\dm_address_reg[20]_i_1_n_1 ,\dm_address_reg[20]_i_1_n_2 ,\dm_address_reg[20]_i_1_n_3 }), - .CYINIT(1'b0), - .DI({1'b0,1'b0,1'b0,1'b0}), - .O({\dm_address_reg[20]_i_1_n_4 ,\dm_address_reg[20]_i_1_n_5 ,\dm_address_reg[20]_i_1_n_6 ,\dm_address_reg[20]_i_1_n_7 }), - .S({\dm_address[20]_i_2_n_0 ,\dm_address[20]_i_3_n_0 ,\dm_address[20]_i_4_n_0 ,\dm_address[20]_i_5_n_0 })); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(1'b1), + .Q(srst_d1), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[21] - (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(\dm_address_reg[20]_i_1_n_6 ), - .Q(dm_address_reg[21]), - .R(p_0_in)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(srst_d1), + .Q(srst_d2), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[22] - (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(\dm_address_reg[20]_i_1_n_5 ), - .Q(dm_address_reg[22]), - .R(p_0_in)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(srst_d2), + .Q(srst_d3), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[23] - (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(\dm_address_reg[20]_i_1_n_4 ), - .Q(dm_address_reg[23]), - .R(p_0_in)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(srst_d3), + .Q(srst_d4), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[24] - (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(\dm_address_reg[24]_i_1_n_7 ), - .Q(dm_address_reg[24]), - .R(p_0_in)); - (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) - CARRY4 \dm_address_reg[24]_i_1 - (.CI(\dm_address_reg[20]_i_1_n_0 ), - .CO({\dm_address_reg[24]_i_1_n_0 ,\dm_address_reg[24]_i_1_n_1 ,\dm_address_reg[24]_i_1_n_2 ,\dm_address_reg[24]_i_1_n_3 }), - .CYINIT(1'b0), - .DI({1'b0,1'b0,1'b0,1'b0}), - .O({\dm_address_reg[24]_i_1_n_4 ,\dm_address_reg[24]_i_1_n_5 ,\dm_address_reg[24]_i_1_n_6 ,\dm_address_reg[24]_i_1_n_7 }), - .S({\dm_address[24]_i_2_n_0 ,\dm_address[24]_i_3_n_0 ,\dm_address[24]_i_4_n_0 ,\dm_address[24]_i_5_n_0 })); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(srst_d4), + .Q(srst_d5), + .R(SR)); + LUT3 #( + .INIT(8'h28)) + s_out_re + (.I0(srst_d5), + .I1(s_out_d5), + .I2(s_out_d4), + .O(s_out_re__0)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized14 + (p_in_d1_cdc_from_0, + s2mm_fsync_out_i, + prmry_in_xored, + E, + SR, + prmry_in_xored_2, + m_axi_s2mm_aclk, + prmry_reset2, + s_axis_s2mm_aclk, + p_in_d1_cdc_from_3, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] , + Q, + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out_0 , + M_Last); + output p_in_d1_cdc_from_0; + output s2mm_fsync_out_i; + output prmry_in_xored; + output [0:0]E; + input [0:0]SR; + input prmry_in_xored_2; + input m_axi_s2mm_aclk; + input prmry_reset2; + input s_axis_s2mm_aclk; + input p_in_d1_cdc_from_3; + input \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ; + input [0:0]Q; + input \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out_0 ; + input M_Last; + + wire [0:0]E; + wire \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ; + wire M_Last; + wire [0:0]Q; + wire [0:0]SR; + wire m_axi_s2mm_aclk; + wire p_in_d1_cdc_from_0; + wire p_in_d1_cdc_from_3; + wire prmry_in_xored; + wire prmry_in_xored_2; + wire prmry_reset2; + wire s2mm_fsync_out_i; + wire s_axis_s2mm_aclk; + wire s_out_d1_cdc_to; + wire s_out_d2; + wire s_out_d3; + wire s_out_d4; + wire s_out_d5; + wire s_out_re__0; + wire srst_d1; + wire srst_d2; + wire srst_d3; + wire srst_d4; + wire srst_d5; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[25] - (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(\dm_address_reg[24]_i_1_n_6 ), - .Q(dm_address_reg[25]), - .R(p_0_in)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(s_out_d1_cdc_to), + .Q(s_out_d2), + .R(prmry_reset2)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[26] - (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(\dm_address_reg[24]_i_1_n_5 ), - .Q(dm_address_reg[26]), - .R(p_0_in)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(s_out_d2), + .Q(s_out_d3), + .R(prmry_reset2)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[27] - (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(\dm_address_reg[24]_i_1_n_4 ), - .Q(dm_address_reg[27]), - .R(p_0_in)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(s_out_d3), + .Q(s_out_d4), + .R(prmry_reset2)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[28] - (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(\dm_address_reg[28]_i_1_n_7 ), - .Q(dm_address_reg[28]), - .R(p_0_in)); - (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) - CARRY4 \dm_address_reg[28]_i_1 - (.CI(\dm_address_reg[24]_i_1_n_0 ), - .CO({\NLW_dm_address_reg[28]_i_1_CO_UNCONNECTED [3],\dm_address_reg[28]_i_1_n_1 ,\dm_address_reg[28]_i_1_n_2 ,\dm_address_reg[28]_i_1_n_3 }), - .CYINIT(1'b0), - .DI({1'b0,1'b0,1'b0,1'b0}), - .O({\dm_address_reg[28]_i_1_n_4 ,\dm_address_reg[28]_i_1_n_5 ,\dm_address_reg[28]_i_1_n_6 ,\dm_address_reg[28]_i_1_n_7 }), - .S({\dm_address[28]_i_2_n_0 ,\dm_address[28]_i_3_n_0 ,\dm_address[28]_i_4_n_0 ,\dm_address[28]_i_5_n_0 })); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(s_out_d4), + .Q(s_out_d5), + .R(prmry_reset2)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[29] - (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(\dm_address_reg[28]_i_1_n_6 ), - .Q(dm_address_reg[29]), - .R(p_0_in)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(s_out_re__0), + .Q(s2mm_fsync_out_i), + .R(prmry_reset2)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(O[2]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [2]), - .R(p_0_in)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(p_in_d1_cdc_from_0), + .Q(s_out_d1_cdc_to), + .R(prmry_reset2)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[30] - (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(\dm_address_reg[28]_i_1_n_5 ), - .Q(dm_address_reg[30]), - .R(p_0_in)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(prmry_in_xored_2), + .Q(p_in_d1_cdc_from_0), + .R(SR)); + LUT2 #( + .INIT(4'h6)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__9 + (.I0(s2mm_fsync_out_i), + .I1(p_in_d1_cdc_from_3), + .O(prmry_in_xored)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(1'b1), + .Q(srst_d1), + .R(prmry_reset2)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(srst_d1), + .Q(srst_d2), + .R(prmry_reset2)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(srst_d2), + .Q(srst_d3), + .R(prmry_reset2)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(srst_d3), + .Q(srst_d4), + .R(prmry_reset2)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(srst_d4), + .Q(srst_d5), + .R(prmry_reset2)); + LUT5 #( + .INIT(32'hAAFEAAAA)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_2 + (.I0(s2mm_fsync_out_i), + .I1(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ), + .I2(Q), + .I3(\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out_0 ), + .I4(M_Last), + .O(E)); + LUT3 #( + .INIT(8'h28)) + s_out_re + (.I0(srst_d5), + .I1(s_out_d5), + .I2(s_out_d4), + .O(s_out_re__0)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized14_37 + (p_in_d1_cdc_from_0, + p_15_out, + all_lines_xfred, + prmry_resetn_i_reg, + prmry_in_xored_1, + m_axi_mm2s_aclk, + SR, + m_axis_mm2s_aclk, + \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4] ); + output p_in_d1_cdc_from_0; + output p_15_out; + output all_lines_xfred; + input [0:0]prmry_resetn_i_reg; + input prmry_in_xored_1; + input m_axi_mm2s_aclk; + input [0:0]SR; + input m_axis_mm2s_aclk; + input \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4] ; + + wire \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4] ; + wire [0:0]SR; + wire all_lines_xfred; + wire m_axi_mm2s_aclk; + wire m_axis_mm2s_aclk; + wire p_15_out; + wire p_in_d1_cdc_from_0; + wire prmry_in_xored_1; + wire [0:0]prmry_resetn_i_reg; + wire s_out_d1_cdc_to; + wire s_out_d2; + wire s_out_d3; + wire s_out_d4; + wire s_out_d5; + wire s_out_re__0; + wire srst_d1; + wire srst_d2; + wire srst_d3; + wire srst_d4; + wire srst_d5; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[31] - (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(\dm_address_reg[28]_i_1_n_4 ), - .Q(dm_address_reg[31]), - .R(p_0_in)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2 + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(s_out_d1_cdc_to), + .Q(s_out_d2), + .R(SR)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[3] - (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(O[3]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [3]), - .R(p_0_in)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3 + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(s_out_d2), + .Q(s_out_d3), + .R(SR)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[4] - (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(\stride_vid_reg[7] [0]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [4]), - .R(p_0_in)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4 + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(s_out_d3), + .Q(s_out_d4), + .R(SR)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[5] - (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(\stride_vid_reg[7] [1]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [5]), - .R(p_0_in)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5 + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(s_out_d4), + .Q(s_out_d5), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[6] - (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(\stride_vid_reg[7] [2]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [6]), - .R(p_0_in)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(s_out_re__0), + .Q(p_15_out), + .R(SR)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[7] - (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(\stride_vid_reg[7] [3]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [7]), - .R(p_0_in)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(p_in_d1_cdc_from_0), + .Q(s_out_d1_cdc_to), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[8] + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(\stride_vid_reg[11] [0]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [8]), - .R(p_0_in)); + .CE(1'b1), + .D(prmry_in_xored_1), + .Q(p_in_d1_cdc_from_0), + .R(prmry_resetn_i_reg)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \dm_address_reg[9] - (.C(m_axi_mm2s_aclk), - .CE(\dm_address[0]_i_1_n_0 ), - .D(\stride_vid_reg[11] [1]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0 [9]), - .R(p_0_in)); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1 + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(1'b1), + .Q(srst_d1), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - frame_sync_d1_reg - (.C(m_axi_mm2s_aclk), + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2 + (.C(m_axis_mm2s_aclk), .CE(1'b1), - .D(p_23_out), - .Q(tstvect_fsync_d1), - .R(p_0_in)); + .D(srst_d1), + .Q(srst_d2), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - frame_sync_d2_reg - (.C(m_axi_mm2s_aclk), + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3 + (.C(m_axis_mm2s_aclk), .CE(1'b1), - .D(tstvect_fsync_d1), - .Q(tstvect_fsync_d2), - .R(p_0_in)); + .D(srst_d2), + .Q(srst_d3), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - frame_sync_d3_reg - (.C(m_axi_mm2s_aclk), + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4 + (.C(m_axis_mm2s_aclk), .CE(1'b1), - .D(tstvect_fsync_d2), - .Q(frame_sync_d3), - .R(p_0_in)); + .D(srst_d3), + .Q(srst_d4), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - frame_sync_reg_reg - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(frame_sync_d3), - .Q(frame_sync_reg), - .R(p_0_in)); - LUT2 #( - .INIT(4'h9)) - p_0_out_carry__0_i_1__0 - (.I0(cmnds_queued_reg__0[6]), - .I1(cmnds_queued_reg__0[7]), - .O(\cmnds_queued_reg[7]_1 [2])); - LUT2 #( - .INIT(4'h9)) - p_0_out_carry__0_i_2__0 - (.I0(\cmnds_queued_reg[7]_0 [5]), - .I1(cmnds_queued_reg__0[6]), - .O(\cmnds_queued_reg[7]_1 [1])); - LUT2 #( - .INIT(4'h9)) - p_0_out_carry__0_i_3 - (.I0(\cmnds_queued_reg[7]_0 [4]), - .I1(\cmnds_queued_reg[7]_0 [5]), - .O(\cmnds_queued_reg[7]_1 [0])); - LUT1 #( - .INIT(2'h1)) - p_0_out_carry_i_1__0 - (.I0(\cmnds_queued_reg[7]_0 [1]), - .O(DI)); - LUT2 #( - .INIT(4'h9)) - p_0_out_carry_i_2__0 - (.I0(\cmnds_queued_reg[7]_0 [3]), - .I1(\cmnds_queued_reg[7]_0 [4]), - .O(S[3])); - LUT2 #( - .INIT(4'h9)) - p_0_out_carry_i_3__0 - (.I0(\cmnds_queued_reg[7]_0 [2]), - .I1(\cmnds_queued_reg[7]_0 [3]), - .O(S[2])); - LUT2 #( - .INIT(4'h9)) - p_0_out_carry_i_4__0 - (.I0(\cmnds_queued_reg[7]_0 [1]), - .I1(\cmnds_queued_reg[7]_0 [2]), - .O(S[1])); - LUT4 #( - .INIT(16'hA655)) - p_0_out_carry_i_5__0 - (.I0(\cmnds_queued_reg[7]_0 [1]), - .I1(p_57_out), - .I2(\INFERRED_GEN.cnt_i_reg[2] ), - .I3(s_axis_cmd_tvalid_reg), - .O(S[0])); - (* SOFT_HLUTNM = "soft_lutpair9" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[0]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[0] ), - .O(D[0])); - (* SOFT_HLUTNM = "soft_lutpair14" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[10]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[10] ), - .O(D[10])); - (* SOFT_HLUTNM = "soft_lutpair15" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[11]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[11] ), - .O(D[11])); - (* SOFT_HLUTNM = "soft_lutpair15" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[12]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[12] ), - .O(D[12])); - (* SOFT_HLUTNM = "soft_lutpair16" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[13]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[13] ), - .O(D[13])); - (* SOFT_HLUTNM = "soft_lutpair16" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[14]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[14] ), - .O(D[14])); - (* SOFT_HLUTNM = "soft_lutpair17" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[15]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[15] ), - .O(D[15])); - (* SOFT_HLUTNM = "soft_lutpair10" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[1]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[1] ), - .O(D[1])); - (* SOFT_HLUTNM = "soft_lutpair8" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[23]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[23] ), - .O(D[16])); - (* SOFT_HLUTNM = "soft_lutpair10" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[2]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[2] ), - .O(D[2])); - (* SOFT_HLUTNM = "soft_lutpair17" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[32]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[32] ), - .O(D[17])); - (* SOFT_HLUTNM = "soft_lutpair18" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[33]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[33] ), - .O(D[18])); - (* SOFT_HLUTNM = "soft_lutpair9" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[34]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[34] ), - .O(D[19])); - (* SOFT_HLUTNM = "soft_lutpair18" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[35]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[35] ), - .O(D[20])); - (* SOFT_HLUTNM = "soft_lutpair19" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[36]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[36] ), - .O(D[21])); - (* SOFT_HLUTNM = "soft_lutpair20" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[37]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[37] ), - .O(D[22])); - (* SOFT_HLUTNM = "soft_lutpair20" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[38]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[38] ), - .O(D[23])); - (* SOFT_HLUTNM = "soft_lutpair19" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[39]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[39] ), - .O(D[24])); - (* SOFT_HLUTNM = "soft_lutpair11" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[3]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[3] ), - .O(D[3])); - (* SOFT_HLUTNM = "soft_lutpair21" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[40]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[40] ), - .O(D[25])); - (* SOFT_HLUTNM = "soft_lutpair22" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[41]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[41] ), - .O(D[26])); - (* SOFT_HLUTNM = "soft_lutpair22" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[42]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[42] ), - .O(D[27])); - (* SOFT_HLUTNM = "soft_lutpair23" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[43]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[43] ), - .O(D[28])); - (* SOFT_HLUTNM = "soft_lutpair23" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[44]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[44] ), - .O(D[29])); - (* SOFT_HLUTNM = "soft_lutpair24" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[45]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[45] ), - .O(D[30])); - (* SOFT_HLUTNM = "soft_lutpair24" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[46]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[46] ), - .O(D[31])); - (* SOFT_HLUTNM = "soft_lutpair25" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[47]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[47] ), - .O(D[32])); - (* SOFT_HLUTNM = "soft_lutpair25" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[48]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[48] ), - .O(D[33])); - (* SOFT_HLUTNM = "soft_lutpair21" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[49]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[49] ), - .O(D[34])); - (* SOFT_HLUTNM = "soft_lutpair11" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[4]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[4] ), - .O(D[4])); - (* SOFT_HLUTNM = "soft_lutpair26" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[50]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[50] ), - .O(D[35])); - (* SOFT_HLUTNM = "soft_lutpair27" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[51]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[51] ), - .O(D[36])); - (* SOFT_HLUTNM = "soft_lutpair26" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[52]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[52] ), - .O(D[37])); - (* SOFT_HLUTNM = "soft_lutpair27" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[53]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[53] ), - .O(D[38])); - (* SOFT_HLUTNM = "soft_lutpair28" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[54]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[54] ), - .O(D[39])); - (* SOFT_HLUTNM = "soft_lutpair29" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[55]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[55] ), - .O(D[40])); - (* SOFT_HLUTNM = "soft_lutpair29" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[56]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[56] ), - .O(D[41])); - (* SOFT_HLUTNM = "soft_lutpair28" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[57]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[57] ), - .O(D[42])); - (* SOFT_HLUTNM = "soft_lutpair30" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[58]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[58] ), - .O(D[43])); - (* SOFT_HLUTNM = "soft_lutpair30" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[59]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[59] ), - .O(D[44])); - (* SOFT_HLUTNM = "soft_lutpair12" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[5]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[5] ), - .O(D[5])); - (* SOFT_HLUTNM = "soft_lutpair31" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[60]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[60] ), - .O(D[45])); - (* SOFT_HLUTNM = "soft_lutpair31" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[61]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[61] ), - .O(D[46])); - (* SOFT_HLUTNM = "soft_lutpair32" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[62]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[62] ), - .O(D[47])); - (* SOFT_HLUTNM = "soft_lutpair32" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[63]_i_3 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[63] ), - .O(D[48])); - (* SOFT_HLUTNM = "soft_lutpair12" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[6]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[6] ), - .O(D[6])); - (* SOFT_HLUTNM = "soft_lutpair13" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[7]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[7] ), - .O(D[7])); - (* SOFT_HLUTNM = "soft_lutpair13" *) - LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[8]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[8] ), - .O(D[8])); - (* SOFT_HLUTNM = "soft_lutpair14" *) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5 + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(srst_d4), + .Q(srst_d5), + .R(SR)); LUT2 #( - .INIT(4'h8)) - \s_axis_cmd_tdata[9]_i_1 - (.I0(s_axis_cmd_tvalid_reg), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[9] ), - .O(D[9])); - LUT6 #( - .INIT(64'hAAAAAAAAAAAAAAEA)) - \vert_count[0]_i_1 - (.I0(load_new_addr), - .I1(dmacntrl_cs[1]), - .I2(dmacntrl_cs[0]), - .I3(dmacntrl_cs[2]), - .I4(dmacntrl_ns14_out), - .I5(s_axis_cmd_tvalid_reg_0), - .O(\vert_count[0]_i_1_n_0 )); - LUT3 #( - .INIT(8'hC5)) - \vert_count[0]_i_10 - (.I0(vert_count_reg[0]), - .I1(\vsize_vid_reg[12] [0]), - .I2(load_new_addr), - .O(\vert_count[0]_i_10_n_0 )); - LUT3 #( - .INIT(8'hB8)) - \vert_count[0]_i_3 - (.I0(\vsize_vid_reg[12] [3]), - .I1(load_new_addr), - .I2(vert_count_reg[3]), - .O(\vert_count[0]_i_3_n_0 )); - LUT3 #( - .INIT(8'hB8)) - \vert_count[0]_i_4 - (.I0(\vsize_vid_reg[12] [2]), - .I1(load_new_addr), - .I2(vert_count_reg[2]), - .O(\vert_count[0]_i_4_n_0 )); - LUT3 #( - .INIT(8'hB8)) - \vert_count[0]_i_5 - (.I0(\vsize_vid_reg[12] [1]), - .I1(load_new_addr), - .I2(vert_count_reg[1]), - .O(\vert_count[0]_i_5_n_0 )); - LUT3 #( - .INIT(8'hB8)) - \vert_count[0]_i_6 - (.I0(\vsize_vid_reg[12] [0]), - .I1(load_new_addr), - .I2(vert_count_reg[0]), - .O(\vert_count[0]_i_6_n_0 )); - LUT3 #( - .INIT(8'hC5)) - \vert_count[0]_i_7 - (.I0(vert_count_reg[3]), - .I1(\vsize_vid_reg[12] [3]), - .I2(load_new_addr), - .O(\vert_count[0]_i_7_n_0 )); - LUT3 #( - .INIT(8'hC5)) - \vert_count[0]_i_8 - (.I0(vert_count_reg[2]), - .I1(\vsize_vid_reg[12] [2]), - .I2(load_new_addr), - .O(\vert_count[0]_i_8_n_0 )); - LUT3 #( - .INIT(8'hC5)) - \vert_count[0]_i_9 - (.I0(vert_count_reg[1]), - .I1(\vsize_vid_reg[12] [1]), - .I2(load_new_addr), - .O(\vert_count[0]_i_9_n_0 )); - LUT3 #( - .INIT(8'hC5)) - \vert_count[12]_i_2 - (.I0(vert_count_reg[12]), - .I1(\vsize_vid_reg[12] [12]), - .I2(load_new_addr), - .O(\vert_count[12]_i_2_n_0 )); - LUT3 #( - .INIT(8'hB8)) - \vert_count[4]_i_2 - (.I0(\vsize_vid_reg[12] [7]), - .I1(load_new_addr), - .I2(vert_count_reg[7]), - .O(\vert_count[4]_i_2_n_0 )); - LUT3 #( - .INIT(8'hB8)) - \vert_count[4]_i_3 - (.I0(\vsize_vid_reg[12] [6]), - .I1(load_new_addr), - .I2(vert_count_reg[6]), - .O(\vert_count[4]_i_3_n_0 )); - LUT3 #( - .INIT(8'hB8)) - \vert_count[4]_i_4 - (.I0(\vsize_vid_reg[12] [5]), - .I1(load_new_addr), - .I2(vert_count_reg[5]), - .O(\vert_count[4]_i_4_n_0 )); - LUT3 #( - .INIT(8'hB8)) - \vert_count[4]_i_5 - (.I0(\vsize_vid_reg[12] [4]), - .I1(load_new_addr), - .I2(vert_count_reg[4]), - .O(\vert_count[4]_i_5_n_0 )); - LUT3 #( - .INIT(8'hC5)) - \vert_count[4]_i_6 - (.I0(vert_count_reg[7]), - .I1(\vsize_vid_reg[12] [7]), - .I2(load_new_addr), - .O(\vert_count[4]_i_6_n_0 )); - LUT3 #( - .INIT(8'hC5)) - \vert_count[4]_i_7 - (.I0(vert_count_reg[6]), - .I1(\vsize_vid_reg[12] [6]), - .I2(load_new_addr), - .O(\vert_count[4]_i_7_n_0 )); - LUT3 #( - .INIT(8'hC5)) - \vert_count[4]_i_8 - (.I0(vert_count_reg[5]), - .I1(\vsize_vid_reg[12] [5]), - .I2(load_new_addr), - .O(\vert_count[4]_i_8_n_0 )); - LUT3 #( - .INIT(8'hC5)) - \vert_count[4]_i_9 - (.I0(vert_count_reg[4]), - .I1(\vsize_vid_reg[12] [4]), - .I2(load_new_addr), - .O(\vert_count[4]_i_9_n_0 )); - LUT3 #( - .INIT(8'hB8)) - \vert_count[8]_i_2 - (.I0(\vsize_vid_reg[12] [11]), - .I1(load_new_addr), - .I2(vert_count_reg[11]), - .O(\vert_count[8]_i_2_n_0 )); - LUT3 #( - .INIT(8'hB8)) - \vert_count[8]_i_3 - (.I0(\vsize_vid_reg[12] [10]), - .I1(load_new_addr), - .I2(vert_count_reg[10]), - .O(\vert_count[8]_i_3_n_0 )); - LUT3 #( - .INIT(8'hB8)) - \vert_count[8]_i_4 - (.I0(\vsize_vid_reg[12] [9]), - .I1(load_new_addr), - .I2(vert_count_reg[9]), - .O(\vert_count[8]_i_4_n_0 )); - LUT3 #( - .INIT(8'hB8)) - \vert_count[8]_i_5 - (.I0(\vsize_vid_reg[12] [8]), - .I1(load_new_addr), - .I2(vert_count_reg[8]), - .O(\vert_count[8]_i_5_n_0 )); - LUT3 #( - .INIT(8'hC5)) - \vert_count[8]_i_6 - (.I0(vert_count_reg[11]), - .I1(\vsize_vid_reg[12] [11]), - .I2(load_new_addr), - .O(\vert_count[8]_i_6_n_0 )); - LUT3 #( - .INIT(8'hC5)) - \vert_count[8]_i_7 - (.I0(vert_count_reg[10]), - .I1(\vsize_vid_reg[12] [10]), - .I2(load_new_addr), - .O(\vert_count[8]_i_7_n_0 )); - LUT3 #( - .INIT(8'hC5)) - \vert_count[8]_i_8 - (.I0(vert_count_reg[9]), - .I1(\vsize_vid_reg[12] [9]), - .I2(load_new_addr), - .O(\vert_count[8]_i_8_n_0 )); + .INIT(4'h1)) + \GEN_LINEBUF_NO_SOF.all_lines_xfred_i_1 + (.I0(p_15_out), + .I1(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[4] ), + .O(all_lines_xfred)); LUT3 #( - .INIT(8'hC5)) - \vert_count[8]_i_9 - (.I0(vert_count_reg[8]), - .I1(\vsize_vid_reg[12] [8]), - .I2(load_new_addr), - .O(\vert_count[8]_i_9_n_0 )); + .INIT(8'h28)) + s_out_re + (.I0(srst_d5), + .I1(s_out_d5), + .I2(s_out_d4), + .O(s_out_re__0)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized16 + (mm2s_fifo_pipe_empty, + SR, + m_axi_mm2s_aclk, + scndry_reset2, + \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg , + m_axis_mm2s_aclk); + output mm2s_fifo_pipe_empty; + input [0:0]SR; + input m_axi_mm2s_aclk; + input scndry_reset2; + input \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg ; + input m_axis_mm2s_aclk; + + wire \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg ; + wire [0:0]SR; + wire m_axi_mm2s_aclk; + wire m_axis_mm2s_aclk; + wire mm2s_fifo_pipe_empty; + wire p_level_in_d1_cdc_from; + wire s_level_out_d1_cdc_to; + wire s_level_out_d2; + wire s_level_out_d3; + wire scndry_reset2; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \vert_count_reg[0] + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to (.C(m_axi_mm2s_aclk), - .CE(\vert_count[0]_i_1_n_0 ), - .D(\vert_count_reg[0]_i_2_n_7 ), - .Q(vert_count_reg[0]), - .R(p_0_in)); - (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) - CARRY4 \vert_count_reg[0]_i_2 - (.CI(1'b0), - .CO({\vert_count_reg[0]_i_2_n_0 ,\vert_count_reg[0]_i_2_n_1 ,\vert_count_reg[0]_i_2_n_2 ,\vert_count_reg[0]_i_2_n_3 }), - .CYINIT(1'b0), - .DI({\vert_count[0]_i_3_n_0 ,\vert_count[0]_i_4_n_0 ,\vert_count[0]_i_5_n_0 ,\vert_count[0]_i_6_n_0 }), - .O({\vert_count_reg[0]_i_2_n_4 ,\vert_count_reg[0]_i_2_n_5 ,\vert_count_reg[0]_i_2_n_6 ,\vert_count_reg[0]_i_2_n_7 }), - .S({\vert_count[0]_i_7_n_0 ,\vert_count[0]_i_8_n_0 ,\vert_count[0]_i_9_n_0 ,\vert_count[0]_i_10_n_0 })); + .CE(1'b1), + .D(p_level_in_d1_cdc_from), + .Q(s_level_out_d1_cdc_to), + .R(SR)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \vert_count_reg[10] + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 (.C(m_axi_mm2s_aclk), - .CE(\vert_count[0]_i_1_n_0 ), - .D(\vert_count_reg[8]_i_1_n_5 ), - .Q(vert_count_reg[10]), - .R(p_0_in)); + .CE(1'b1), + .D(s_level_out_d1_cdc_to), + .Q(s_level_out_d2), + .R(SR)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \vert_count_reg[11] + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 (.C(m_axi_mm2s_aclk), - .CE(\vert_count[0]_i_1_n_0 ), - .D(\vert_count_reg[8]_i_1_n_4 ), - .Q(vert_count_reg[11]), - .R(p_0_in)); + .CE(1'b1), + .D(s_level_out_d2), + .Q(s_level_out_d3), + .R(SR)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \vert_count_reg[12] + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 (.C(m_axi_mm2s_aclk), - .CE(\vert_count[0]_i_1_n_0 ), - .D(\vert_count_reg[12]_i_1_n_7 ), - .Q(vert_count_reg[12]), - .R(p_0_in)); - (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) - CARRY4 \vert_count_reg[12]_i_1 - (.CI(\vert_count_reg[8]_i_1_n_0 ), - .CO(\NLW_vert_count_reg[12]_i_1_CO_UNCONNECTED [3:0]), - .CYINIT(1'b0), - .DI({1'b0,1'b0,1'b0,1'b0}), - .O({\NLW_vert_count_reg[12]_i_1_O_UNCONNECTED [3:1],\vert_count_reg[12]_i_1_n_7 }), - .S({1'b0,1'b0,1'b0,\vert_count[12]_i_2_n_0 })); + .CE(1'b1), + .D(s_level_out_d3), + .Q(mm2s_fifo_pipe_empty), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \vert_count_reg[1] + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(\GEN_LINEBUF_NO_SOF.all_lines_xfred_reg ), + .Q(p_level_in_d1_cdc_from), + .R(scndry_reset2)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized17 + (mm2s_all_lines_xfred, + SR, + m_axi_mm2s_aclk, + scndry_reset2, + \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg , + m_axis_mm2s_aclk); + output mm2s_all_lines_xfred; + input [0:0]SR; + input m_axi_mm2s_aclk; + input scndry_reset2; + input \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg ; + input m_axis_mm2s_aclk; + + wire \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg ; + wire [0:0]SR; + wire m_axi_mm2s_aclk; + wire m_axis_mm2s_aclk; + wire mm2s_all_lines_xfred; + wire p_level_in_d1_cdc_from; + wire s_level_out_d1_cdc_to; + wire s_level_out_d2; + wire s_level_out_d3; + wire scndry_reset2; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to (.C(m_axi_mm2s_aclk), - .CE(\vert_count[0]_i_1_n_0 ), - .D(\vert_count_reg[0]_i_2_n_6 ), - .Q(vert_count_reg[1]), - .R(p_0_in)); + .CE(1'b1), + .D(p_level_in_d1_cdc_from), + .Q(s_level_out_d1_cdc_to), + .R(SR)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \vert_count_reg[2] + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 (.C(m_axi_mm2s_aclk), - .CE(\vert_count[0]_i_1_n_0 ), - .D(\vert_count_reg[0]_i_2_n_5 ), - .Q(vert_count_reg[2]), - .R(p_0_in)); + .CE(1'b1), + .D(s_level_out_d1_cdc_to), + .Q(s_level_out_d2), + .R(SR)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \vert_count_reg[3] + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 (.C(m_axi_mm2s_aclk), - .CE(\vert_count[0]_i_1_n_0 ), - .D(\vert_count_reg[0]_i_2_n_4 ), - .Q(vert_count_reg[3]), - .R(p_0_in)); + .CE(1'b1), + .D(s_level_out_d2), + .Q(s_level_out_d3), + .R(SR)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \vert_count_reg[4] + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 (.C(m_axi_mm2s_aclk), - .CE(\vert_count[0]_i_1_n_0 ), - .D(\vert_count_reg[4]_i_1_n_7 ), - .Q(vert_count_reg[4]), - .R(p_0_in)); - (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) - CARRY4 \vert_count_reg[4]_i_1 - (.CI(\vert_count_reg[0]_i_2_n_0 ), - .CO({\vert_count_reg[4]_i_1_n_0 ,\vert_count_reg[4]_i_1_n_1 ,\vert_count_reg[4]_i_1_n_2 ,\vert_count_reg[4]_i_1_n_3 }), - .CYINIT(1'b0), - .DI({\vert_count[4]_i_2_n_0 ,\vert_count[4]_i_3_n_0 ,\vert_count[4]_i_4_n_0 ,\vert_count[4]_i_5_n_0 }), - .O({\vert_count_reg[4]_i_1_n_4 ,\vert_count_reg[4]_i_1_n_5 ,\vert_count_reg[4]_i_1_n_6 ,\vert_count_reg[4]_i_1_n_7 }), - .S({\vert_count[4]_i_6_n_0 ,\vert_count[4]_i_7_n_0 ,\vert_count[4]_i_8_n_0 ,\vert_count[4]_i_9_n_0 })); + .CE(1'b1), + .D(s_level_out_d3), + .Q(mm2s_all_lines_xfred), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \vert_count_reg[5] + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(\GEN_LINEBUF_NO_SOF.all_lines_xfred_reg ), + .Q(p_level_in_d1_cdc_from), + .R(scndry_reset2)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized1_12 + (prmry_in_xored, + scndry_out, + prmry_in_xored_0, + SR, + \GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_reg , + prmry_min_assert_sftrst, + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 , + p_in_d1_cdc_from, + p_in_d1_cdc_from_1, + s_soft_reset_i_d1, + s_soft_reset_i, + p_11_out, + m_axi_mm2s_aclk, + lite_min_assert_sftrst, + s_axi_lite_aclk); + output prmry_in_xored; + output scndry_out; + output prmry_in_xored_0; + output [0:0]SR; + output \GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_reg ; + input prmry_min_assert_sftrst; + input \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ; + input p_in_d1_cdc_from; + input p_in_d1_cdc_from_1; + input s_soft_reset_i_d1; + input s_soft_reset_i; + input p_11_out; + input m_axi_mm2s_aclk; + input lite_min_assert_sftrst; + input s_axi_lite_aclk; + + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ; + wire \GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_reg ; + wire [0:0]SR; + wire lite_min_assert_sftrst; + wire m_axi_mm2s_aclk; + wire p_11_out; + wire p_in_d1_cdc_from; + wire p_in_d1_cdc_from_1; + wire p_level_in_d1_cdc_from; + wire prmry_in_xored; + wire prmry_in_xored_0; + wire prmry_min_assert_sftrst; + wire s_axi_lite_aclk; + wire s_level_out_d1_cdc_to; + wire s_level_out_d2; + wire s_level_out_d3; + wire s_soft_reset_i; + wire s_soft_reset_i_d1; + wire scndry_out; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to (.C(m_axi_mm2s_aclk), - .CE(\vert_count[0]_i_1_n_0 ), - .D(\vert_count_reg[4]_i_1_n_6 ), - .Q(vert_count_reg[5]), - .R(p_0_in)); + .CE(1'b1), + .D(p_level_in_d1_cdc_from), + .Q(s_level_out_d1_cdc_to), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \vert_count_reg[6] + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 (.C(m_axi_mm2s_aclk), - .CE(\vert_count[0]_i_1_n_0 ), - .D(\vert_count_reg[4]_i_1_n_5 ), - .Q(vert_count_reg[6]), - .R(p_0_in)); + .CE(1'b1), + .D(s_level_out_d1_cdc_to), + .Q(s_level_out_d2), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(s_level_out_d2), + .Q(s_level_out_d3), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(s_level_out_d3), + .Q(scndry_out), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(lite_min_assert_sftrst), + .Q(p_level_in_d1_cdc_from), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair255" *) + LUT4 #( + .INIT(16'h7F80)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__0 + (.I0(scndry_out), + .I1(prmry_min_assert_sftrst), + .I2(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ), + .I3(p_in_d1_cdc_from), + .O(prmry_in_xored)); + (* SOFT_HLUTNM = "soft_lutpair255" *) + LUT4 #( + .INIT(16'h7F80)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__2 + (.I0(scndry_out), + .I1(prmry_min_assert_sftrst), + .I2(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ), + .I3(p_in_d1_cdc_from_1), + .O(prmry_in_xored_0)); + LUT6 #( + .INIT(64'h00FFF2F2FFFFF2F2)) + \GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_i_1 + (.I0(s_soft_reset_i), + .I1(s_soft_reset_i_d1), + .I2(p_11_out), + .I3(scndry_out), + .I4(prmry_min_assert_sftrst), + .I5(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ), + .O(\GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_reg )); + LUT5 #( + .INIT(32'h80FF8080)) + \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_1 + (.I0(scndry_out), + .I1(prmry_min_assert_sftrst), + .I2(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ), + .I3(s_soft_reset_i_d1), + .I4(s_soft_reset_i), + .O(SR)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized2 + (\FSM_sequential_dmacntrl_cs_reg[2] , + scndry_out, + halt_i_reg, + s2mm_soft_reset, + dma_err, + s_axis_s2mm_aclk, + \cmnds_queued_reg[0] , + m_axi_s2mm_aclk); + output \FSM_sequential_dmacntrl_cs_reg[2] ; + output scndry_out; + input halt_i_reg; + input s2mm_soft_reset; + input dma_err; + input s_axis_s2mm_aclk; + input \cmnds_queued_reg[0] ; + input m_axi_s2mm_aclk; + + wire \FSM_sequential_dmacntrl_cs_reg[2] ; + wire \cmnds_queued_reg[0] ; + wire dma_err; + wire halt_i_reg; + wire m_axi_s2mm_aclk; + wire p_level_in_d1_cdc_from; + wire s2mm_soft_reset; + wire s_axis_s2mm_aclk; + wire s_level_out_d1_cdc_to; + wire s_level_out_d2; + wire s_level_out_d3; + wire scndry_out; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \vert_count_reg[7] - (.C(m_axi_mm2s_aclk), - .CE(\vert_count[0]_i_1_n_0 ), - .D(\vert_count_reg[4]_i_1_n_4 ), - .Q(vert_count_reg[7]), - .R(p_0_in)); + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(p_level_in_d1_cdc_from), + .Q(s_level_out_d1_cdc_to), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \vert_count_reg[8] - (.C(m_axi_mm2s_aclk), - .CE(\vert_count[0]_i_1_n_0 ), - .D(\vert_count_reg[8]_i_1_n_7 ), - .Q(vert_count_reg[8]), - .R(p_0_in)); - (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) - CARRY4 \vert_count_reg[8]_i_1 - (.CI(\vert_count_reg[4]_i_1_n_0 ), - .CO({\vert_count_reg[8]_i_1_n_0 ,\vert_count_reg[8]_i_1_n_1 ,\vert_count_reg[8]_i_1_n_2 ,\vert_count_reg[8]_i_1_n_3 }), - .CYINIT(1'b0), - .DI({\vert_count[8]_i_2_n_0 ,\vert_count[8]_i_3_n_0 ,\vert_count[8]_i_4_n_0 ,\vert_count[8]_i_5_n_0 }), - .O({\vert_count_reg[8]_i_1_n_4 ,\vert_count_reg[8]_i_1_n_5 ,\vert_count_reg[8]_i_1_n_6 ,\vert_count_reg[8]_i_1_n_7 }), - .S({\vert_count[8]_i_6_n_0 ,\vert_count[8]_i_7_n_0 ,\vert_count[8]_i_8_n_0 ,\vert_count[8]_i_9_n_0 })); + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(s_level_out_d1_cdc_to), + .Q(s_level_out_d2), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \vert_count_reg[9] - (.C(m_axi_mm2s_aclk), - .CE(\vert_count[0]_i_1_n_0 ), - .D(\vert_count_reg[8]_i_1_n_6 ), - .Q(vert_count_reg[9]), - .R(p_0_in)); + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(s_level_out_d2), + .Q(s_level_out_d3), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - zero_hsize_err_reg - (.C(m_axi_mm2s_aclk), + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(zero_hsize_err0), - .Q(zero_hsize_err), - .R(p_0_in)); - LUT6 #( - .INIT(64'h0000001000000000)) - zero_vsize_err_i_3 - (.I0(dmacntrl_cs[0]), - .I1(dmacntrl_cs[2]), - .I2(dmacntrl_cs[1]), - .I3(p_3_in), - .I4(frame_sync_reg), - .I5(p_68_out[0]), - .O(load_new_addr)); + .D(s_level_out_d3), + .Q(scndry_out), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - zero_vsize_err_reg - (.C(m_axi_mm2s_aclk), + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(zero_vsize_err0), - .Q(zero_vsize_err), - .R(p_0_in)); + .D(\cmnds_queued_reg[0] ), + .Q(p_level_in_d1_cdc_from), + .R(1'b0)); + LUT3 #( + .INIT(8'hFE)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_4__0 + (.I0(halt_i_reg), + .I1(s2mm_soft_reset), + .I2(dma_err), + .O(\FSM_sequential_dmacntrl_cs_reg[2] )); endmodule -(* ORIG_REF_NAME = "axi_vdma_sof_gen" *) -module Arty_Z7_20_axi_vdma_0_0_axi_vdma_sof_gen - (prmry_in_xored, +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized20 + (sig_reset_reg_reg, + m_axis_fifo_ainit_nosync, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tready_d1_reg , scndry_reset2, - s_valid0, m_axis_mm2s_aclk, - p_in_d1_cdc_from, - out, + SR, + mm2s_halt, + m_axi_mm2s_aclk, + mm2s_axis_resetn, + m_axis_mm2s_tready, p_15_out); - output prmry_in_xored; + output sig_reset_reg_reg; + output m_axis_fifo_ainit_nosync; + output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tready_d1_reg ; input scndry_reset2; - input s_valid0; input m_axis_mm2s_aclk; - input p_in_d1_cdc_from; - input out; + input [0:0]SR; + input mm2s_halt; + input m_axi_mm2s_aclk; + input mm2s_axis_resetn; + input m_axis_mm2s_tready; input p_15_out; - wire hold_sof; - wire hold_sof_i_1_n_0; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tready_d1_reg ; + wire [0:0]SR; + wire m_axi_mm2s_aclk; + wire m_axis_fifo_ainit_nosync; wire m_axis_mm2s_aclk; - wire out; + wire m_axis_mm2s_tready; + wire mm2s_axis_resetn; + wire mm2s_halt; wire p_15_out; - wire p_in_d1_cdc_from; - wire prmry_in_xored; - wire s_valid; - wire s_valid0; - wire s_valid_d1; + wire p_level_in_d1_cdc_from; + wire s_level_out_d1_cdc_to; + wire s_level_out_d2; + wire s_level_out_d3; wire scndry_reset2; + wire sig_reset_reg_reg; - LUT4 #( - .INIT(16'hEF10)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__4 - (.I0(hold_sof), - .I1(s_valid_d1), - .I2(s_valid), - .I3(p_in_d1_cdc_from), - .O(prmry_in_xored)); - LUT5 #( - .INIT(32'h0000AE00)) - hold_sof_i_1 - (.I0(hold_sof), - .I1(s_valid), - .I2(s_valid_d1), - .I3(out), - .I4(p_15_out), - .O(hold_sof_i_1_n_0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - hold_sof_reg + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to (.C(m_axis_mm2s_aclk), .CE(1'b1), - .D(hold_sof_i_1_n_0), - .Q(hold_sof), - .R(1'b0)); + .D(p_level_in_d1_cdc_from), + .Q(s_level_out_d1_cdc_to), + .R(scndry_reset2)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - s_valid_d1_reg + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 (.C(m_axis_mm2s_aclk), .CE(1'b1), - .D(s_valid), - .Q(s_valid_d1), + .D(s_level_out_d1_cdc_to), + .Q(s_level_out_d2), .R(scndry_reset2)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - s_valid_reg + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 (.C(m_axis_mm2s_aclk), .CE(1'b1), - .D(s_valid0), - .Q(s_valid), + .D(s_level_out_d2), + .Q(s_level_out_d3), .R(scndry_reset2)); -endmodule - -(* ORIG_REF_NAME = "axi_vdma_sts_mngr" *) -module Arty_Z7_20_axi_vdma_0_0_axi_vdma_sts_mngr - (p_36_out, - datamover_idle, - halted_reg, - p_0_in, - \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg , - m_axi_mm2s_aclk, - p_68_out, - \dmacr_i_reg[0] , - p_1_out, - p_37_out, - p_67_out, - out); - output p_36_out; - output datamover_idle; - output halted_reg; - input p_0_in; - input \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg ; - input m_axi_mm2s_aclk; - input [0:0]p_68_out; - input \dmacr_i_reg[0] ; - input p_1_out; - input p_37_out; - input p_67_out; - input out; - - wire \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg ; - wire datamover_idle; - wire \dmacr_i_reg[0] ; - wire halted_reg; - wire halted_set_i0; - wire m_axi_mm2s_aclk; - wire out; - wire p_0_in; - wire p_1_out; - wire p_26_out; - wire p_27_out; - wire p_36_out; - wire p_37_out; - wire p_67_out; - wire [0:0]p_68_out; - - FDSE all_idle_reg - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg ), - .Q(p_36_out), - .S(p_0_in)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - datamover_idle_reg - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\dmacr_i_reg[0] ), - .Q(datamover_idle), - .R(p_0_in)); - FDRE halted_clr_reg - (.C(m_axi_mm2s_aclk), + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 + (.C(m_axis_mm2s_aclk), .CE(1'b1), - .D(p_68_out), - .Q(p_26_out), - .R(p_0_in)); - LUT4 #( - .INIT(16'hFF4F)) - halted_i_1 - (.I0(p_26_out), - .I1(p_67_out), - .I2(out), - .I3(p_27_out), - .O(halted_reg)); - LUT4 #( - .INIT(16'h2000)) - halted_set_i_i_1 - (.I0(p_1_out), - .I1(p_68_out), - .I2(datamover_idle), - .I3(p_37_out), - .O(halted_set_i0)); + .D(s_level_out_d3), + .Q(sig_reset_reg_reg), + .R(scndry_reset2)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - halted_set_i_reg + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(halted_set_i0), - .Q(p_27_out), - .R(p_0_in)); + .D(mm2s_halt), + .Q(p_level_in_d1_cdc_from), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair44" *) + LUT4 #( + .INIT(16'h0020)) + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tready_d1_i_1 + (.I0(m_axis_mm2s_tready), + .I1(sig_reset_reg_reg), + .I2(mm2s_axis_resetn), + .I3(p_15_out), + .O(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tready_d1_reg )); + (* SOFT_HLUTNM = "soft_lutpair44" *) + LUT2 #( + .INIT(4'hB)) + \sig_data_reg_out[31]_i_1__1 + (.I0(sig_reset_reg_reg), + .I1(mm2s_axis_resetn), + .O(m_axis_fifo_ainit_nosync)); endmodule -(* ORIG_REF_NAME = "axi_vdma_vid_cdc" *) -module Arty_Z7_20_axi_vdma_0_0_axi_vdma_vid_cdc +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized21 (p_in_d1_cdc_from, - p_17_out, - p_in_d1_cdc_from_0, - p_15_out, - all_lines_xfred, - mm2s_frame_ptr_out, + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_clr_flag1_reg , SR, prmry_in_xored, - m_axis_mm2s_aclk, - prmry_resetn_i_reg, - m_axi_mm2s_aclk, - prmry_in_xored_1, - in0, - mm2s_frame_ptr_in, - \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4] ); + m_axi_s2mm_aclk, + prmry_reset2, + s_axis_s2mm_aclk, + d_tready_before_fsync_clr_flag1, + out, + s2mm_dmasr_halted_s); output p_in_d1_cdc_from; - output p_17_out; - output p_in_d1_cdc_from_0; - output p_15_out; - output all_lines_xfred; - output [5:0]mm2s_frame_ptr_out; + output \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_clr_flag1_reg ; input [0:0]SR; input prmry_in_xored; - input m_axis_mm2s_aclk; - input [0:0]prmry_resetn_i_reg; - input m_axi_mm2s_aclk; - input prmry_in_xored_1; - input [0:0]in0; - input [5:0]mm2s_frame_ptr_in; - input \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4] ; + input m_axi_s2mm_aclk; + input prmry_reset2; + input s_axis_s2mm_aclk; + input d_tready_before_fsync_clr_flag1; + input out; + input s2mm_dmasr_halted_s; - wire \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4] ; + wire \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_clr_flag1_reg ; wire [0:0]SR; - wire all_lines_xfred; - (* async_reg = "true" *) wire [5:0]frame_ptr_in_d1_cdc_tig; - (* async_reg = "true" *) wire [5:0]frame_ptr_in_d2; - (* async_reg = "true" *) wire [5:0]frame_ptr_out_d1_cdc_tig; - (* async_reg = "true" *) wire [5:0]frame_ptr_out_d2; - wire m_axi_mm2s_aclk; - wire m_axis_mm2s_aclk; - wire [5:0]mm2s_frame_ptr_in; - wire [5:0]mm2s_frame_ptr_out; - (* async_reg = "true" *) wire [5:0]othrchnl_frame_ptr_in_d1_cdc_tig; - (* async_reg = "true" *) wire [5:0]othrchnl_frame_ptr_in_d2; - wire p_15_out; - wire p_17_out; - wire [5:0]p_2_in; + wire d_tready_before_fsync_clr_flag1; + wire m_axi_s2mm_aclk; + wire out; wire p_in_d1_cdc_from; - wire p_in_d1_cdc_from_0; wire prmry_in_xored; - wire prmry_in_xored_1; - wire [0:0]prmry_resetn_i_reg; + wire prmry_reset2; + wire s2mm_dmasr_halted_s; + wire s2mm_prmtr_updt_complete_s; + wire s_axis_s2mm_aclk; + wire s_out_d1_cdc_to; + wire s_out_d2; + wire s_out_d3; + wire s_out_d4; + wire s_out_d5; + wire s_out_re__0; + wire srst_d1; + wire srst_d2; + wire srst_d3; + wire srst_d4; + wire srst_d5; - assign p_2_in[0] = in0[0]; - Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized12 \GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I - (.\GEN_LINEBUF_NO_SOF.vsize_counter_reg[4] (\GEN_LINEBUF_NO_SOF.vsize_counter_reg[4] ), - .SR(SR), - .all_lines_xfred(all_lines_xfred), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axis_mm2s_aclk(m_axis_mm2s_aclk), - .p_15_out(p_15_out), - .p_in_d1_cdc_from_0(p_in_d1_cdc_from_0), - .prmry_in_xored_1(prmry_in_xored_1), - .prmry_resetn_i_reg(prmry_resetn_i_reg)); - Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized10 \GEN_CDC_FOR_ASYNC.SOF_CDC_I - (.SR(SR), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axis_mm2s_aclk(m_axis_mm2s_aclk), - .p_17_out(p_17_out), - .p_in_d1_cdc_from(p_in_d1_cdc_from), - .prmry_in_xored(prmry_in_xored), - .prmry_resetn_i_reg(prmry_resetn_i_reg)); - FDRE \GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[0] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(frame_ptr_out_d2[0]), - .Q(mm2s_frame_ptr_out[0]), - .R(SR)); - FDRE \GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[1] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(frame_ptr_out_d2[1]), - .Q(mm2s_frame_ptr_out[1]), - .R(SR)); - FDRE \GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[2] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(frame_ptr_out_d2[2]), - .Q(mm2s_frame_ptr_out[2]), - .R(SR)); - FDRE \GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[3] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(frame_ptr_out_d2[3]), - .Q(mm2s_frame_ptr_out[3]), - .R(SR)); - FDRE \GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[4] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(frame_ptr_out_d2[4]), - .Q(mm2s_frame_ptr_out[4]), - .R(SR)); - FDRE \GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[5] - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(frame_ptr_out_d2[5]), - .Q(mm2s_frame_ptr_out[5]), - .R(SR)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[0] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(mm2s_frame_ptr_in[0]), - .Q(frame_ptr_in_d1_cdc_tig[0]), - .R(1'b0)); (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(mm2s_frame_ptr_in[1]), - .Q(frame_ptr_in_d1_cdc_tig[1]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(mm2s_frame_ptr_in[2]), - .Q(frame_ptr_in_d1_cdc_tig[2]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) - FDRE #( - .INIT(1'b0)) - \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[3] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(mm2s_frame_ptr_in[3]), - .Q(frame_ptr_in_d1_cdc_tig[3]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[4] - (.C(m_axi_mm2s_aclk), + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2 + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(mm2s_frame_ptr_in[4]), - .Q(frame_ptr_in_d1_cdc_tig[4]), - .R(1'b0)); + .D(s_out_d1_cdc_to), + .Q(s_out_d2), + .R(prmry_reset2)); (* ASYNC_REG *) - (* KEEP = "yes" *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[5] - (.C(m_axi_mm2s_aclk), + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3 + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(mm2s_frame_ptr_in[5]), - .Q(frame_ptr_in_d1_cdc_tig[5]), - .R(1'b0)); + .D(s_out_d2), + .Q(s_out_d3), + .R(prmry_reset2)); (* ASYNC_REG *) - (* KEEP = "yes" *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[0] - (.C(m_axi_mm2s_aclk), + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4 + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(frame_ptr_in_d1_cdc_tig[0]), - .Q(frame_ptr_in_d2[0]), - .R(1'b0)); + .D(s_out_d3), + .Q(s_out_d4), + .R(prmry_reset2)); (* ASYNC_REG *) - (* KEEP = "yes" *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[1] - (.C(m_axi_mm2s_aclk), + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5 + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(frame_ptr_in_d1_cdc_tig[1]), - .Q(frame_ptr_in_d2[1]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + .D(s_out_d4), + .Q(s_out_d5), + .R(prmry_reset2)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[2] - (.C(m_axi_mm2s_aclk), + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(frame_ptr_in_d1_cdc_tig[2]), - .Q(frame_ptr_in_d2[2]), - .R(1'b0)); + .D(s_out_re__0), + .Q(s2mm_prmtr_updt_complete_s), + .R(prmry_reset2)); (* ASYNC_REG *) - (* KEEP = "yes" *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[3] - (.C(m_axi_mm2s_aclk), + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(frame_ptr_in_d1_cdc_tig[3]), - .Q(frame_ptr_in_d2[3]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + .D(p_in_d1_cdc_from), + .Q(s_out_d1_cdc_to), + .R(prmry_reset2)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[4] - (.C(m_axi_mm2s_aclk), + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(frame_ptr_in_d1_cdc_tig[4]), - .Q(frame_ptr_in_d2[4]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + .D(prmry_in_xored), + .Q(p_in_d1_cdc_from), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[5] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(frame_ptr_in_d1_cdc_tig[5]), - .Q(frame_ptr_in_d2[5]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(1'b1), + .Q(srst_d1), + .R(prmry_reset2)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[0] - (.C(m_axis_mm2s_aclk), + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2 + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(p_2_in[0]), - .Q(frame_ptr_out_d1_cdc_tig[0]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + .D(srst_d1), + .Q(srst_d2), + .R(prmry_reset2)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[1] - (.C(m_axis_mm2s_aclk), + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3 + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(p_2_in[1]), - .Q(frame_ptr_out_d1_cdc_tig[1]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + .D(srst_d2), + .Q(srst_d3), + .R(prmry_reset2)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2] - (.C(m_axis_mm2s_aclk), + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4 + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(p_2_in[2]), - .Q(frame_ptr_out_d1_cdc_tig[2]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + .D(srst_d3), + .Q(srst_d4), + .R(prmry_reset2)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[3] - (.C(m_axis_mm2s_aclk), + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5 + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(p_2_in[3]), - .Q(frame_ptr_out_d1_cdc_tig[3]), - .R(1'b0)); + .D(srst_d4), + .Q(srst_d5), + .R(prmry_reset2)); + LUT4 #( + .INIT(16'hFF4F)) + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_clr_flag1_i_1 + (.I0(s2mm_prmtr_updt_complete_s), + .I1(d_tready_before_fsync_clr_flag1), + .I2(out), + .I3(s2mm_dmasr_halted_s), + .O(\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_clr_flag1_reg )); + LUT3 #( + .INIT(8'h28)) + s_out_re + (.I0(srst_d5), + .I1(s_out_d5), + .I2(s_out_d4), + .O(s_out_re__0)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized22 + (s2mm_dmasr_halted_s, + prmry_reset2, + s_axis_s2mm_aclk, + SR, + s2mm_dmasr, + m_axi_s2mm_aclk); + output s2mm_dmasr_halted_s; + input prmry_reset2; + input s_axis_s2mm_aclk; + input [0:0]SR; + input [0:0]s2mm_dmasr; + input m_axi_s2mm_aclk; + + wire [0:0]SR; + wire m_axi_s2mm_aclk; + wire p_level_in_d1_cdc_from; + wire prmry_reset2; + wire [0:0]s2mm_dmasr; + wire s2mm_dmasr_halted_s; + wire s_axis_s2mm_aclk; + wire s_level_out_d1_cdc_to; + wire s_level_out_d2; + wire s_level_out_d3; + (* ASYNC_REG *) - (* KEEP = "yes" *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[4] - (.C(m_axis_mm2s_aclk), + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(p_2_in[4]), - .Q(frame_ptr_out_d1_cdc_tig[4]), - .R(1'b0)); + .D(p_level_in_d1_cdc_from), + .Q(s_level_out_d1_cdc_to), + .R(prmry_reset2)); (* ASYNC_REG *) - (* KEEP = "yes" *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[5] - (.C(m_axis_mm2s_aclk), + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(p_2_in[5]), - .Q(frame_ptr_out_d1_cdc_tig[5]), - .R(1'b0)); + .D(s_level_out_d1_cdc_to), + .Q(s_level_out_d2), + .R(prmry_reset2)); (* ASYNC_REG *) - (* KEEP = "yes" *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[0] - (.C(m_axis_mm2s_aclk), + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(frame_ptr_out_d1_cdc_tig[0]), - .Q(frame_ptr_out_d2[0]), - .R(1'b0)); + .D(s_level_out_d2), + .Q(s_level_out_d3), + .R(prmry_reset2)); (* ASYNC_REG *) - (* KEEP = "yes" *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[1] - (.C(m_axis_mm2s_aclk), + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(frame_ptr_out_d1_cdc_tig[1]), - .Q(frame_ptr_out_d2[1]), - .R(1'b0)); - (* ASYNC_REG *) - (* KEEP = "yes" *) + .D(s_level_out_d3), + .Q(s2mm_dmasr_halted_s), + .R(prmry_reset2)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[2] - (.C(m_axis_mm2s_aclk), + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(frame_ptr_out_d1_cdc_tig[2]), - .Q(frame_ptr_out_d2[2]), - .R(1'b0)); + .D(s2mm_dmasr), + .Q(p_level_in_d1_cdc_from), + .R(SR)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized23 + (s2mm_fsize_more_or_sof_late, + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_0 , + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_1 , + SR, + m_axi_s2mm_aclk, + prmry_reset2, + s2mm_fsize_more_or_sof_late_s, + s_axis_s2mm_aclk, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg , + d_tready_sof_late, + s2mm_tuser_to_fsync_out, + d_tready_before_fsync, + d_tready_before_fsync_clr_flag1); + output s2mm_fsize_more_or_sof_late; + output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_0 ; + output \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_1 ; + input [0:0]SR; + input m_axi_s2mm_aclk; + input prmry_reset2; + input s2mm_fsize_more_or_sof_late_s; + input s_axis_s2mm_aclk; + input \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ; + input d_tready_sof_late; + input s2mm_tuser_to_fsync_out; + input d_tready_before_fsync; + input d_tready_before_fsync_clr_flag1; + + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_0 ; + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_1 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ; + wire [0:0]SR; + wire d_tready_before_fsync; + wire d_tready_before_fsync_clr_flag1; + wire d_tready_sof_late; + wire m_axi_s2mm_aclk; + wire p_level_in_d1_cdc_from; + wire prmry_reset2; + wire s2mm_fsize_more_or_sof_late; + wire s2mm_fsize_more_or_sof_late_s; + wire s2mm_tuser_to_fsync_out; + wire s_axis_s2mm_aclk; + wire s_level_out_d1_cdc_to; + wire s_level_out_d2; + wire s_level_out_d3; + (* ASYNC_REG *) - (* KEEP = "yes" *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[3] - (.C(m_axis_mm2s_aclk), + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(frame_ptr_out_d1_cdc_tig[3]), - .Q(frame_ptr_out_d2[3]), - .R(1'b0)); + .D(p_level_in_d1_cdc_from), + .Q(s_level_out_d1_cdc_to), + .R(SR)); (* ASYNC_REG *) - (* KEEP = "yes" *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[4] - (.C(m_axis_mm2s_aclk), + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(frame_ptr_out_d1_cdc_tig[4]), - .Q(frame_ptr_out_d2[4]), - .R(1'b0)); + .D(s_level_out_d1_cdc_to), + .Q(s_level_out_d2), + .R(SR)); (* ASYNC_REG *) - (* KEEP = "yes" *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[5] - (.C(m_axis_mm2s_aclk), + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(frame_ptr_out_d1_cdc_tig[5]), - .Q(frame_ptr_out_d2[5]), - .R(1'b0)); - LUT1 #( - .INIT(2'h2)) - i_0 - (.I0(1'b0), - .O(p_2_in[5])); - LUT1 #( - .INIT(2'h2)) - i_1 - (.I0(1'b0), - .O(p_2_in[4])); - LUT1 #( - .INIT(2'h2)) - i_10 - (.I0(1'b0), - .O(othrchnl_frame_ptr_in_d1_cdc_tig[0])); - LUT1 #( - .INIT(2'h2)) - i_11 - (.I0(1'b0), - .O(othrchnl_frame_ptr_in_d2[5])); - LUT1 #( - .INIT(2'h2)) - i_12 - (.I0(1'b0), - .O(othrchnl_frame_ptr_in_d2[4])); - LUT1 #( - .INIT(2'h2)) - i_13 - (.I0(1'b0), - .O(othrchnl_frame_ptr_in_d2[3])); - LUT1 #( - .INIT(2'h2)) - i_14 - (.I0(1'b0), - .O(othrchnl_frame_ptr_in_d2[2])); - LUT1 #( - .INIT(2'h2)) - i_15 - (.I0(1'b0), - .O(othrchnl_frame_ptr_in_d2[1])); - LUT1 #( - .INIT(2'h2)) - i_16 - (.I0(1'b0), - .O(othrchnl_frame_ptr_in_d2[0])); - LUT1 #( - .INIT(2'h2)) - i_2 - (.I0(1'b0), - .O(p_2_in[3])); - LUT1 #( - .INIT(2'h2)) - i_3 - (.I0(1'b0), - .O(p_2_in[2])); - LUT1 #( - .INIT(2'h2)) - i_4 - (.I0(1'b0), - .O(p_2_in[1])); - LUT1 #( - .INIT(2'h2)) - i_5 - (.I0(1'b0), - .O(othrchnl_frame_ptr_in_d1_cdc_tig[5])); - LUT1 #( - .INIT(2'h2)) - i_6 - (.I0(1'b0), - .O(othrchnl_frame_ptr_in_d1_cdc_tig[4])); - LUT1 #( - .INIT(2'h2)) - i_7 - (.I0(1'b0), - .O(othrchnl_frame_ptr_in_d1_cdc_tig[3])); - LUT1 #( - .INIT(2'h2)) - i_8 - (.I0(1'b0), - .O(othrchnl_frame_ptr_in_d1_cdc_tig[2])); - LUT1 #( - .INIT(2'h2)) - i_9 - (.I0(1'b0), - .O(othrchnl_frame_ptr_in_d1_cdc_tig[1])); -endmodule - -(* ORIG_REF_NAME = "axi_vdma_vidreg_module" *) -module Arty_Z7_20_axi_vdma_0_0_axi_vdma_vidreg_module - (\stride_vid_reg[0] , - \stride_vid_reg[0]_0 , - zero_vsize_err0, - Q, - zero_hsize_err0, - all_idle_reg, - E, - p_2_out, - \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] , - O, - \dm_address_reg[7] , - \dm_address_reg[11] , - CO, - \dm_address_reg[15] , - \dm_address_reg[31] , - prmtr_updt_complete_i_reg, - m_axi_mm2s_aclk, - load_new_addr, - p_1_out, - p_64_out, - p_37_out, - p_23_out, - p_6_out__0, - p_68_out, - valid_frame_sync_d2, - mask_fsync_out_i, - tstvect_fsync_d1, - \dm_address_reg[15]_0 , - out, - p_67_out, - p_0_in, - \reg_module_vsize_reg[12] , - \reg_module_hsize_reg[15] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] , - \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ); - output \stride_vid_reg[0] ; - output \stride_vid_reg[0]_0 ; - output zero_vsize_err0; - output [12:0]Q; - output zero_hsize_err0; - output all_idle_reg; - output [0:0]E; - output p_2_out; - output [15:0]\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] ; - output [3:0]O; - output [3:0]\dm_address_reg[7] ; - output [3:0]\dm_address_reg[11] ; - output [0:0]CO; - output [3:0]\dm_address_reg[15] ; - output [15:0]\dm_address_reg[31] ; - input prmtr_updt_complete_i_reg; - input m_axi_mm2s_aclk; - input load_new_addr; - input p_1_out; - input p_64_out; - input p_37_out; - input p_23_out; - input p_6_out__0; - input [0:0]p_68_out; - input valid_frame_sync_d2; - input mask_fsync_out_i; - input tstvect_fsync_d1; - input [15:0]\dm_address_reg[15]_0 ; - input out; - input p_67_out; - input p_0_in; - input [12:0]\reg_module_vsize_reg[12] ; - input [15:0]\reg_module_hsize_reg[15] ; - input [31:0]\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] ; - input [15:0]\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ; - - wire [0:0]CO; - wire [0:0]E; - wire [15:0]\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] ; - wire [31:0]\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] ; - wire \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_i_1_n_0 ; - wire [15:0]\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ; - wire [3:0]O; - wire [12:0]Q; - wire all_idle_reg; - wire [3:0]\dm_address_reg[11] ; - wire [3:0]\dm_address_reg[15] ; - wire [15:0]\dm_address_reg[15]_0 ; - wire [15:0]\dm_address_reg[31] ; - wire [3:0]\dm_address_reg[7] ; - wire load_new_addr; - wire m_axi_mm2s_aclk; - wire mask_fsync_out_i; - wire out; - wire p_0_in; - wire p_1_out; - wire p_23_out; - wire p_2_out; - wire p_37_out; - wire p_64_out; - wire p_67_out; - wire [0:0]p_68_out; - wire p_6_out__0; - wire prmtr_updt_complete_i_reg; - wire [15:0]\reg_module_hsize_reg[15] ; - wire [12:0]\reg_module_vsize_reg[12] ; - wire \stride_vid_reg[0] ; - wire \stride_vid_reg[0]_0 ; - wire tstvect_fsync_d1; - wire valid_frame_sync_d2; - wire zero_hsize_err0; - wire zero_vsize_err0; - - LUT3 #( - .INIT(8'h20)) - \GEN_FREE_RUN_MODE.frame_sync_out_i_1 - (.I0(\stride_vid_reg[0]_0 ), - .I1(mask_fsync_out_i), - .I2(tstvect_fsync_d1), - .O(p_2_out)); - Arty_Z7_20_axi_vdma_0_0_axi_vdma_vregister \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.VIDREGISTER_I - (.CO(CO), - .\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] (\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] ), - .\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] (\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] ), - .\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg (\stride_vid_reg[0]_0 ), - .\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg (\stride_vid_reg[0] ), - .\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] (\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ), - .O(O), - .Q(Q), - .\dm_address_reg[11] (\dm_address_reg[11] ), - .\dm_address_reg[15] (\dm_address_reg[15] ), - .\dm_address_reg[15]_0 (\dm_address_reg[15]_0 ), - .\dm_address_reg[31] (\dm_address_reg[31] ), - .\dm_address_reg[7] (\dm_address_reg[7] ), - .load_new_addr(load_new_addr), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .p_0_in(p_0_in), - .p_23_out(p_23_out), - .\reg_module_hsize_reg[15] (\reg_module_hsize_reg[15] ), - .\reg_module_vsize_reg[12] (\reg_module_vsize_reg[12] ), - .zero_hsize_err0(zero_hsize_err0), - .zero_vsize_err0(zero_vsize_err0)); - LUT5 #( - .INIT(32'h0000EA00)) - \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_i_1 - (.I0(\stride_vid_reg[0]_0 ), - .I1(p_23_out), - .I2(\stride_vid_reg[0] ), - .I3(out), - .I4(p_67_out), - .O(\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_i_1_n_0 )); + .D(s_level_out_d2), + .Q(s_level_out_d3), + .R(SR)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg - (.C(m_axi_mm2s_aclk), + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_i_1_n_0 ), - .Q(\stride_vid_reg[0]_0 ), - .R(1'b0)); + .D(s_level_out_d3), + .Q(s2mm_fsize_more_or_sof_late), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg - (.C(m_axi_mm2s_aclk), + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(prmtr_updt_complete_i_reg), - .Q(\stride_vid_reg[0] ), - .R(1'b0)); - LUT4 #( - .INIT(16'hEFCC)) - \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_2 - (.I0(\stride_vid_reg[0]_0 ), - .I1(p_6_out__0), - .I2(p_68_out), - .I3(valid_frame_sync_d2), - .O(E)); - LUT5 #( - .INIT(32'hC8880000)) - all_idle_i_1 - (.I0(\stride_vid_reg[0]_0 ), - .I1(p_1_out), - .I2(\stride_vid_reg[0] ), - .I3(p_64_out), - .I4(p_37_out), - .O(all_idle_reg)); + .D(s2mm_fsize_more_or_sof_late_s), + .Q(p_level_in_d1_cdc_from), + .R(prmry_reset2)); + LUT3 #( + .INIT(8'h04)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_2__1 + (.I0(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ), + .I1(d_tready_sof_late), + .I2(s2mm_tuser_to_fsync_out), + .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_0 )); + LUT2 #( + .INIT(4'h8)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_3__1 + (.I0(d_tready_before_fsync), + .I1(d_tready_before_fsync_clr_flag1), + .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_1 )); endmodule -(* ORIG_REF_NAME = "axi_vdma_vregister" *) -module Arty_Z7_20_axi_vdma_0_0_axi_vdma_vregister - (zero_vsize_err0, - Q, - zero_hsize_err0, - \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] , +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized24 + (\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg , + halt_i0, + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0 , + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_irqthresh_decr_mask_sig_reg , + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[0] , + \dm_address_reg_0__s_port_] , + \vert_count_reg_0__s_port_] , + \vert_count_reg[0]_0 , + \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[0] , + halted_set_i0, + s2mm_ftchcmdsts_idle, + D, + \DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_reg , O, - \dm_address_reg[7] , - \dm_address_reg[11] , - CO, - \dm_address_reg[15] , + \vert_count_reg[7] , + \vert_count_reg[11] , + \vert_count_reg[12] , + \dm_address_reg[19] , + \dm_address_reg[23] , + \dm_address_reg[27] , \dm_address_reg[31] , - load_new_addr, - p_23_out, + \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[63] , + \FSM_sequential_dmacntrl_cs_reg[0] , + \FSM_sequential_dmacntrl_cs_reg[1] , + \FSM_sequential_dmacntrl_cs_reg[2] , + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF.flag_to_repeat_after_fsize_less_err_reg , + write_cmnd_cmb, + prmry_reset2, + s_axis_s2mm_aclk, + SR, + m_axi_s2mm_aclk, + s2mm_stop, + run_stop_d1, + s2mm_dmacr, + s2mm_soft_reset, + soft_reset_d1, + fsize_mismatch_err_flag_int, + prmry_resetn_i_reg, + s2mm_tstvect_fsync, + ch2_delay_cnt_en, + s2mm_packet_sof, + ch2_irqthresh_decr_mask_sig, + s2mm_halt, + out, + s2mm_cdc2dmac_fsync, + s2mm_fsync_out_m_i, + drop_fsync_d_pulse_gen_fsize_less_err_d1, + fsize_mismatch_err_s1, + \FSM_sequential_dmacntrl_cs_reg[2]_0 , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] , + dm_address_reg, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][30] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][29] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][28] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][27] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][26] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][25] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][24] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][23] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][22] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][21] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][20] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][19] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][18] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][17] , + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][16] , + s_axis_cmd_tvalid_reg, + Q, + vert_count_reg, + datamover_idle, + \cmnds_queued_reg[7] , + \cmnds_queued_reg[1] , + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] , + flag_to_repeat_after_fsize_less_err, + \GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[4] , + halt_i_reg, + frame_sync_reg, \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg , - \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg , - \dm_address_reg[15]_0 , - p_0_in, - \reg_module_vsize_reg[12] , - m_axi_mm2s_aclk, - \reg_module_hsize_reg[15] , - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] , - \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ); - output zero_vsize_err0; - output [12:0]Q; - output zero_hsize_err0; - output [15:0]\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] ; + dma_err, + vert_count_reg_1__s_port_, + \vert_count_reg[11]_0 , + \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[4] , + valid_frame_sync_d2, + CO, + in0); + output \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg ; + output halt_i0; + output \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0 ; + output \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_irqthresh_decr_mask_sig_reg ; + output [0:0]\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[0] ; + output \dm_address_reg_0__s_port_] ; + output \vert_count_reg_0__s_port_] ; + output \vert_count_reg[0]_0 ; + output \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[0] ; + output halted_set_i0; + output s2mm_ftchcmdsts_idle; + output [4:0]D; + output \DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_reg ; output [3:0]O; - output [3:0]\dm_address_reg[7] ; - output [3:0]\dm_address_reg[11] ; - output [0:0]CO; - output [3:0]\dm_address_reg[15] ; - output [15:0]\dm_address_reg[31] ; - input load_new_addr; - input p_23_out; + output [3:0]\vert_count_reg[7] ; + output [3:0]\vert_count_reg[11] ; + output [0:0]\vert_count_reg[12] ; + output [3:0]\dm_address_reg[19] ; + output [3:0]\dm_address_reg[23] ; + output [3:0]\dm_address_reg[27] ; + output [3:0]\dm_address_reg[31] ; + output \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[63] ; + output \FSM_sequential_dmacntrl_cs_reg[0] ; + output \FSM_sequential_dmacntrl_cs_reg[1] ; + output \FSM_sequential_dmacntrl_cs_reg[2] ; + output \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF.flag_to_repeat_after_fsize_less_err_reg ; + output write_cmnd_cmb; + input prmry_reset2; + input s_axis_s2mm_aclk; + input [0:0]SR; + input m_axi_s2mm_aclk; + input s2mm_stop; + input run_stop_d1; + input [1:0]s2mm_dmacr; + input s2mm_soft_reset; + input soft_reset_d1; + input fsize_mismatch_err_flag_int; + input prmry_resetn_i_reg; + input s2mm_tstvect_fsync; + input ch2_delay_cnt_en; + input s2mm_packet_sof; + input ch2_irqthresh_decr_mask_sig; + input s2mm_halt; + input out; + input s2mm_cdc2dmac_fsync; + input s2mm_fsync_out_m_i; + input drop_fsync_d_pulse_gen_fsize_less_err_d1; + input fsize_mismatch_err_s1; + input [2:0]\FSM_sequential_dmacntrl_cs_reg[2]_0 ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] ; + input [15:0]dm_address_reg; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][30] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][29] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][28] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][27] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][26] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][25] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][24] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][23] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][22] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][21] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][20] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][19] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][18] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][17] ; + input \GEN_START_ADDR_REG[1].start_address_vid_reg[1][16] ; + input s_axis_cmd_tvalid_reg; + input [12:0]Q; + input [12:0]vert_count_reg; + input datamover_idle; + input [4:0]\cmnds_queued_reg[7] ; + input \cmnds_queued_reg[1] ; + input [4:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] ; + input flag_to_repeat_after_fsize_less_err; + input [4:0]\GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[4] ; + input halt_i_reg; + input frame_sync_reg; input \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg ; - input \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg ; - input [15:0]\dm_address_reg[15]_0 ; - input p_0_in; - input [12:0]\reg_module_vsize_reg[12] ; - input m_axi_mm2s_aclk; - input [15:0]\reg_module_hsize_reg[15] ; - input [31:0]\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] ; - input [15:0]\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ; + input dma_err; + input vert_count_reg_1__s_port_; + input \vert_count_reg[11]_0 ; + input [3:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[4] ; + input valid_frame_sync_d2; + input [0:0]CO; + input [2:0]in0; - wire [15:0]C; wire [0:0]CO; - wire [15:0]\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] ; - wire [31:0]\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] ; + wire [4:0]D; + wire \DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_i_3_n_0 ; + wire \DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_reg ; + wire [4:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] ; + wire \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF.flag_to_repeat_after_fsize_less_err_reg ; + wire [3:0]\DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[4] ; + wire \FSM_sequential_dmacntrl_cs[0]_i_2__0_n_0 ; + wire \FSM_sequential_dmacntrl_cs[0]_i_3__0_n_0 ; + wire \FSM_sequential_dmacntrl_cs[1]_i_2__0_n_0 ; + wire \FSM_sequential_dmacntrl_cs[1]_i_3__0_n_0 ; + wire \FSM_sequential_dmacntrl_cs[2]_i_2__0_n_0 ; + wire \FSM_sequential_dmacntrl_cs[2]_i_3__0_n_0 ; + wire \FSM_sequential_dmacntrl_cs_reg[0] ; + wire \FSM_sequential_dmacntrl_cs_reg[1] ; + wire \FSM_sequential_dmacntrl_cs_reg[2] ; + wire [2:0]\FSM_sequential_dmacntrl_cs_reg[2]_0 ; + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_2__0_n_0 ; + wire [4:0]\GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[4] ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0 ; + wire \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_irqthresh_decr_mask_sig_reg ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[0] ; + wire \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[63] ; wire \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg ; - wire \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg ; - wire [15:0]\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] ; + wire [0:0]\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[0] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][16] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][17] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][18] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][19] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][20] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][21] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][22] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][23] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][24] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][25] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][26] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][27] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][28] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][29] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][30] ; + wire \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] ; wire [3:0]O; wire [12:0]Q; - wire \dm_address[0]_i_10_n_0 ; - wire \dm_address[0]_i_3_n_0 ; - wire \dm_address[0]_i_4_n_0 ; - wire \dm_address[0]_i_5_n_0 ; - wire \dm_address[0]_i_6_n_0 ; - wire \dm_address[0]_i_7_n_0 ; - wire \dm_address[0]_i_8_n_0 ; - wire \dm_address[0]_i_9_n_0 ; - wire \dm_address[12]_i_2_n_0 ; - wire \dm_address[12]_i_3_n_0 ; - wire \dm_address[12]_i_4_n_0 ; - wire \dm_address[12]_i_5_n_0 ; - wire \dm_address[12]_i_6_n_0 ; - wire \dm_address[12]_i_7_n_0 ; - wire \dm_address[12]_i_8_n_0 ; - wire \dm_address[12]_i_9_n_0 ; - wire \dm_address[4]_i_2_n_0 ; - wire \dm_address[4]_i_3_n_0 ; - wire \dm_address[4]_i_4_n_0 ; - wire \dm_address[4]_i_5_n_0 ; - wire \dm_address[4]_i_6_n_0 ; - wire \dm_address[4]_i_7_n_0 ; - wire \dm_address[4]_i_8_n_0 ; - wire \dm_address[4]_i_9_n_0 ; - wire \dm_address[8]_i_2_n_0 ; - wire \dm_address[8]_i_3_n_0 ; - wire \dm_address[8]_i_4_n_0 ; - wire \dm_address[8]_i_5_n_0 ; - wire \dm_address[8]_i_6_n_0 ; - wire \dm_address[8]_i_7_n_0 ; - wire \dm_address[8]_i_8_n_0 ; - wire \dm_address[8]_i_9_n_0 ; - wire \dm_address_reg[0]_i_2_n_0 ; - wire \dm_address_reg[0]_i_2_n_1 ; - wire \dm_address_reg[0]_i_2_n_2 ; - wire \dm_address_reg[0]_i_2_n_3 ; - wire [3:0]\dm_address_reg[11] ; - wire \dm_address_reg[12]_i_1_n_1 ; - wire \dm_address_reg[12]_i_1_n_2 ; - wire \dm_address_reg[12]_i_1_n_3 ; - wire [3:0]\dm_address_reg[15] ; - wire [15:0]\dm_address_reg[15]_0 ; - wire [15:0]\dm_address_reg[31] ; - wire \dm_address_reg[4]_i_1_n_0 ; - wire \dm_address_reg[4]_i_1_n_1 ; - wire \dm_address_reg[4]_i_1_n_2 ; - wire \dm_address_reg[4]_i_1_n_3 ; - wire [3:0]\dm_address_reg[7] ; - wire \dm_address_reg[8]_i_1_n_0 ; - wire \dm_address_reg[8]_i_1_n_1 ; - wire \dm_address_reg[8]_i_1_n_2 ; - wire \dm_address_reg[8]_i_1_n_3 ; - wire load_new_addr; - wire m_axi_mm2s_aclk; - wire p_0_in; - wire p_23_out; - wire [15:0]\reg_module_hsize_reg[15] ; - wire [12:0]\reg_module_vsize_reg[12] ; - wire [15:0]stride_vid; - wire video_reg_update; - wire zero_hsize_err0; - wire zero_hsize_err_i_2_n_0; - wire zero_hsize_err_i_3_n_0; - wire zero_hsize_err_i_4_n_0; - wire zero_hsize_err_i_5_n_0; - wire zero_vsize_err0; - wire zero_vsize_err_i_2_n_0; - wire zero_vsize_err_i_4_n_0; + wire [0:0]SR; + wire ch2_delay_cnt_en; + wire ch2_irqthresh_decr_mask_sig; + wire \cmnds_queued_reg[1] ; + wire [4:0]\cmnds_queued_reg[7] ; + wire datamover_idle; + wire \dm_address[16]_i_2__0_n_0 ; + wire \dm_address[16]_i_3__0_n_0 ; + wire \dm_address[16]_i_4__0_n_0 ; + wire \dm_address[16]_i_5__0_n_0 ; + wire \dm_address[20]_i_2__0_n_0 ; + wire \dm_address[20]_i_3__0_n_0 ; + wire \dm_address[20]_i_4__0_n_0 ; + wire \dm_address[20]_i_5__0_n_0 ; + wire \dm_address[24]_i_2__0_n_0 ; + wire \dm_address[24]_i_3__0_n_0 ; + wire \dm_address[24]_i_4__0_n_0 ; + wire \dm_address[24]_i_5__0_n_0 ; + wire \dm_address[28]_i_2__0_n_0 ; + wire \dm_address[28]_i_3__0_n_0 ; + wire \dm_address[28]_i_4__0_n_0 ; + wire \dm_address[28]_i_5__0_n_0 ; + wire [15:0]dm_address_reg; + wire \dm_address_reg[16]_i_1__0_n_0 ; + wire \dm_address_reg[16]_i_1__0_n_1 ; + wire \dm_address_reg[16]_i_1__0_n_2 ; + wire \dm_address_reg[16]_i_1__0_n_3 ; + wire [3:0]\dm_address_reg[19] ; + wire \dm_address_reg[20]_i_1__0_n_0 ; + wire \dm_address_reg[20]_i_1__0_n_1 ; + wire \dm_address_reg[20]_i_1__0_n_2 ; + wire \dm_address_reg[20]_i_1__0_n_3 ; + wire [3:0]\dm_address_reg[23] ; + wire \dm_address_reg[24]_i_1__0_n_0 ; + wire \dm_address_reg[24]_i_1__0_n_1 ; + wire \dm_address_reg[24]_i_1__0_n_2 ; + wire \dm_address_reg[24]_i_1__0_n_3 ; + wire [3:0]\dm_address_reg[27] ; + wire \dm_address_reg[28]_i_1__0_n_1 ; + wire \dm_address_reg[28]_i_1__0_n_2 ; + wire \dm_address_reg[28]_i_1__0_n_3 ; + wire [3:0]\dm_address_reg[31] ; + wire dm_address_reg_0__s_net_1; + wire dma_err; + wire dmacntrl_ns1; + wire dmacntrl_ns15_out; + wire drop_fsync_d_pulse_gen_fsize_less_err_d1; + wire flag_to_repeat_after_fsize_less_err; + wire frame_sync_reg; + wire fsize_mismatch_err_flag_int; + wire fsize_mismatch_err_s1; + wire halt_i0; + wire halt_i_reg; + wire halted_set_i0; + wire [2:0]in0; + wire m_axi_s2mm_aclk; + wire out; + wire p_in_d1_cdc_from; + wire prmry_in_xored; + wire prmry_reset2; + wire prmry_resetn_i_reg; + wire run_stop_d1; + wire s2mm_cdc2dmac_fsync; + wire [1:0]s2mm_dmacr; + wire s2mm_fsize_mismatch_err_flag; + wire s2mm_fsync_out_m_i; + wire s2mm_ftchcmdsts_idle; + wire s2mm_halt; + wire s2mm_packet_sof; + wire s2mm_soft_reset; + wire s2mm_stop; + wire s2mm_tstvect_fsync; + wire s_axis_cmd_tvalid_reg; + wire s_axis_s2mm_aclk; + wire s_out_d1_cdc_to; + wire s_out_d2; + wire s_out_d3; + wire s_out_d4; + wire s_out_d5; + wire s_out_re__0; + wire soft_reset_d1; + wire srst_d1; + wire srst_d2; + wire srst_d3; + wire srst_d4; + wire srst_d5; + wire valid_frame_sync_d2; + wire \vert_count[0]_i_10__0_n_0 ; + wire \vert_count[0]_i_11__0_n_0 ; + wire \vert_count[0]_i_4__0_n_0 ; + wire \vert_count[0]_i_5__0_n_0 ; + wire \vert_count[0]_i_6__0_n_0 ; + wire \vert_count[0]_i_7__0_n_0 ; + wire \vert_count[0]_i_8__0_n_0 ; + wire \vert_count[0]_i_9__0_n_0 ; + wire \vert_count[12]_i_2__0_n_0 ; + wire \vert_count[4]_i_2__0_n_0 ; + wire \vert_count[4]_i_3__0_n_0 ; + wire \vert_count[4]_i_4__0_n_0 ; + wire \vert_count[4]_i_5__0_n_0 ; + wire \vert_count[4]_i_6__0_n_0 ; + wire \vert_count[4]_i_7__0_n_0 ; + wire \vert_count[4]_i_8__0_n_0 ; + wire \vert_count[4]_i_9__0_n_0 ; + wire \vert_count[8]_i_2__0_n_0 ; + wire \vert_count[8]_i_3__0_n_0 ; + wire \vert_count[8]_i_4__0_n_0 ; + wire \vert_count[8]_i_5__0_n_0 ; + wire \vert_count[8]_i_6__0_n_0 ; + wire \vert_count[8]_i_7__0_n_0 ; + wire \vert_count[8]_i_8__0_n_0 ; + wire \vert_count[8]_i_9__0_n_0 ; + wire [12:0]vert_count_reg; + wire \vert_count_reg[0]_0 ; + wire \vert_count_reg[0]_i_2__0_n_0 ; + wire \vert_count_reg[0]_i_2__0_n_1 ; + wire \vert_count_reg[0]_i_2__0_n_2 ; + wire \vert_count_reg[0]_i_2__0_n_3 ; + wire [3:0]\vert_count_reg[11] ; + wire \vert_count_reg[11]_0 ; + wire [0:0]\vert_count_reg[12] ; + wire \vert_count_reg[4]_i_1__0_n_0 ; + wire \vert_count_reg[4]_i_1__0_n_1 ; + wire \vert_count_reg[4]_i_1__0_n_2 ; + wire \vert_count_reg[4]_i_1__0_n_3 ; + wire [3:0]\vert_count_reg[7] ; + wire \vert_count_reg[8]_i_1__0_n_0 ; + wire \vert_count_reg[8]_i_1__0_n_1 ; + wire \vert_count_reg[8]_i_1__0_n_2 ; + wire \vert_count_reg[8]_i_1__0_n_3 ; + wire vert_count_reg_0__s_net_1; + wire vert_count_reg_1__s_net_1; + wire write_cmnd_cmb; + wire [3:3]\NLW_dm_address_reg[28]_i_1__0_CO_UNCONNECTED ; + wire [3:0]\NLW_vert_count_reg[12]_i_1__0_CO_UNCONNECTED ; + wire [3:1]\NLW_vert_count_reg[12]_i_1__0_O_UNCONNECTED ; - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][0] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [0]), - .Q(C[0]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][10] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [10]), - .Q(C[10]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][11] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [11]), - .Q(C[11]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][12] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [12]), - .Q(C[12]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][13] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [13]), - .Q(C[13]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][14] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [14]), - .Q(C[14]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][15] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [15]), - .Q(C[15]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][16] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [16]), - .Q(\dm_address_reg[31] [0]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][17] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [17]), - .Q(\dm_address_reg[31] [1]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][18] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [18]), - .Q(\dm_address_reg[31] [2]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][19] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [19]), - .Q(\dm_address_reg[31] [3]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][1] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [1]), - .Q(C[1]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][20] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [20]), - .Q(\dm_address_reg[31] [4]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][21] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [21]), - .Q(\dm_address_reg[31] [5]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][22] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [22]), - .Q(\dm_address_reg[31] [6]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][23] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [23]), - .Q(\dm_address_reg[31] [7]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][24] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [24]), - .Q(\dm_address_reg[31] [8]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][25] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [25]), - .Q(\dm_address_reg[31] [9]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][26] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [26]), - .Q(\dm_address_reg[31] [10]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][27] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [27]), - .Q(\dm_address_reg[31] [11]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][28] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [28]), - .Q(\dm_address_reg[31] [12]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][29] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [29]), - .Q(\dm_address_reg[31] [13]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][2] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [2]), - .Q(C[2]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][30] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [30]), - .Q(\dm_address_reg[31] [14]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [31]), - .Q(\dm_address_reg[31] [15]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][3] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [3]), - .Q(C[3]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][4] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [4]), - .Q(C[4]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][5] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [5]), - .Q(C[5]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][6] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [6]), - .Q(C[6]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][7] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [7]), - .Q(C[7]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][8] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [8]), - .Q(C[8]), - .R(p_0_in)); - FDRE \GEN_START_ADDR_REG[0].start_address_vid_reg[0][9] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31] [9]), - .Q(C[9]), - .R(p_0_in)); - LUT4 #( - .INIT(16'hF606)) - \dm_address[0]_i_10 - (.I0(stride_vid[0]), - .I1(\dm_address_reg[15]_0 [0]), - .I2(load_new_addr), - .I3(C[0]), - .O(\dm_address[0]_i_10_n_0 )); - LUT2 #( - .INIT(4'h2)) - \dm_address[0]_i_3 - (.I0(stride_vid[3]), - .I1(load_new_addr), - .O(\dm_address[0]_i_3_n_0 )); - LUT2 #( - .INIT(4'h2)) - \dm_address[0]_i_4 - (.I0(stride_vid[2]), - .I1(load_new_addr), - .O(\dm_address[0]_i_4_n_0 )); - LUT2 #( - .INIT(4'h2)) - \dm_address[0]_i_5 - (.I0(stride_vid[1]), - .I1(load_new_addr), - .O(\dm_address[0]_i_5_n_0 )); - LUT2 #( - .INIT(4'h2)) - \dm_address[0]_i_6 - (.I0(stride_vid[0]), - .I1(load_new_addr), - .O(\dm_address[0]_i_6_n_0 )); - LUT4 #( - .INIT(16'hF606)) - \dm_address[0]_i_7 - (.I0(stride_vid[3]), - .I1(\dm_address_reg[15]_0 [3]), - .I2(load_new_addr), - .I3(C[3]), - .O(\dm_address[0]_i_7_n_0 )); - LUT4 #( - .INIT(16'hF606)) - \dm_address[0]_i_8 - (.I0(stride_vid[2]), - .I1(\dm_address_reg[15]_0 [2]), - .I2(load_new_addr), - .I3(C[2]), - .O(\dm_address[0]_i_8_n_0 )); - LUT4 #( - .INIT(16'hF606)) - \dm_address[0]_i_9 - (.I0(stride_vid[1]), - .I1(\dm_address_reg[15]_0 [1]), - .I2(load_new_addr), - .I3(C[1]), - .O(\dm_address[0]_i_9_n_0 )); - LUT2 #( - .INIT(4'h2)) - \dm_address[12]_i_2 - (.I0(stride_vid[15]), - .I1(load_new_addr), - .O(\dm_address[12]_i_2_n_0 )); - LUT2 #( - .INIT(4'h2)) - \dm_address[12]_i_3 - (.I0(stride_vid[14]), - .I1(load_new_addr), - .O(\dm_address[12]_i_3_n_0 )); - LUT2 #( - .INIT(4'h2)) - \dm_address[12]_i_4 - (.I0(stride_vid[13]), - .I1(load_new_addr), - .O(\dm_address[12]_i_4_n_0 )); - LUT2 #( - .INIT(4'h2)) - \dm_address[12]_i_5 - (.I0(stride_vid[12]), - .I1(load_new_addr), - .O(\dm_address[12]_i_5_n_0 )); + assign \dm_address_reg_0__s_port_] = dm_address_reg_0__s_net_1; + assign \vert_count_reg_0__s_port_] = vert_count_reg_0__s_net_1; + assign vert_count_reg_1__s_net_1 = vert_count_reg_1__s_port_; + LUT5 #( + .INIT(32'hFFFFFEFF)) + \DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_i_2 + (.I0(\DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[4] [0]), + .I1(\DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[4] [1]), + .I2(\DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[4] [3]), + .I3(s2mm_dmacr[1]), + .I4(\DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_i_3_n_0 ), + .O(\DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_reg )); LUT4 #( - .INIT(16'hF606)) - \dm_address[12]_i_6 - (.I0(stride_vid[15]), - .I1(\dm_address_reg[15]_0 [15]), - .I2(load_new_addr), - .I3(C[15]), - .O(\dm_address[12]_i_6_n_0 )); + .INIT(16'hFFEF)) + \DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_i_3 + (.I0(fsize_mismatch_err_flag_int), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg ), + .I2(valid_frame_sync_d2), + .I3(\DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[4] [2]), + .O(\DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair50" *) LUT4 #( - .INIT(16'hF606)) - \dm_address[12]_i_7 - (.I0(stride_vid[14]), - .I1(\dm_address_reg[15]_0 [14]), - .I2(load_new_addr), - .I3(C[14]), - .O(\dm_address[12]_i_7_n_0 )); + .INIT(16'h00E0)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF.flag_to_repeat_after_fsize_less_err_i_1 + (.I0(flag_to_repeat_after_fsize_less_err), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg ), + .I2(out), + .I3(valid_frame_sync_d2), + .O(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF.flag_to_repeat_after_fsize_less_err_reg )); LUT4 #( - .INIT(16'hF606)) - \dm_address[12]_i_8 - (.I0(stride_vid[13]), - .I1(\dm_address_reg[15]_0 [13]), - .I2(load_new_addr), - .I3(C[13]), - .O(\dm_address[12]_i_8_n_0 )); + .INIT(16'hFE02)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr[0]_i_1 + (.I0(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] [0]), + .I1(flag_to_repeat_after_fsize_less_err), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg ), + .I3(\GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[4] [0]), + .O(D[0])); LUT4 #( - .INIT(16'hF606)) - \dm_address[12]_i_9 - (.I0(stride_vid[12]), - .I1(\dm_address_reg[15]_0 [12]), - .I2(load_new_addr), - .I3(C[12]), - .O(\dm_address[12]_i_9_n_0 )); - LUT2 #( - .INIT(4'h2)) - \dm_address[4]_i_2 - (.I0(stride_vid[7]), - .I1(load_new_addr), - .O(\dm_address[4]_i_2_n_0 )); - LUT2 #( - .INIT(4'h2)) - \dm_address[4]_i_3 - (.I0(stride_vid[6]), - .I1(load_new_addr), - .O(\dm_address[4]_i_3_n_0 )); - LUT2 #( - .INIT(4'h2)) - \dm_address[4]_i_4 - (.I0(stride_vid[5]), - .I1(load_new_addr), - .O(\dm_address[4]_i_4_n_0 )); - LUT2 #( - .INIT(4'h2)) - \dm_address[4]_i_5 - (.I0(stride_vid[4]), - .I1(load_new_addr), - .O(\dm_address[4]_i_5_n_0 )); + .INIT(16'hFE02)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr[1]_i_1 + (.I0(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] [1]), + .I1(flag_to_repeat_after_fsize_less_err), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg ), + .I3(\GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[4] [1]), + .O(D[1])); LUT4 #( - .INIT(16'hF606)) - \dm_address[4]_i_6 - (.I0(stride_vid[7]), - .I1(\dm_address_reg[15]_0 [7]), - .I2(load_new_addr), - .I3(C[7]), - .O(\dm_address[4]_i_6_n_0 )); + .INIT(16'hFE02)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr[2]_i_1 + (.I0(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] [2]), + .I1(flag_to_repeat_after_fsize_less_err), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg ), + .I3(\GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[4] [2]), + .O(D[2])); LUT4 #( - .INIT(16'hF606)) - \dm_address[4]_i_7 - (.I0(stride_vid[6]), - .I1(\dm_address_reg[15]_0 [6]), - .I2(load_new_addr), - .I3(C[6]), - .O(\dm_address[4]_i_7_n_0 )); + .INIT(16'hFE02)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr[3]_i_1 + (.I0(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] [3]), + .I1(flag_to_repeat_after_fsize_less_err), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg ), + .I3(\GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[4] [3]), + .O(D[3])); LUT4 #( - .INIT(16'hF606)) - \dm_address[4]_i_8 - (.I0(stride_vid[5]), - .I1(\dm_address_reg[15]_0 [5]), - .I2(load_new_addr), - .I3(C[5]), - .O(\dm_address[4]_i_8_n_0 )); + .INIT(16'hFE02)) + \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr[4]_i_3 + (.I0(\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4] [4]), + .I1(flag_to_repeat_after_fsize_less_err), + .I2(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg ), + .I3(\GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[4] [4]), + .O(D[4])); + LUT6 #( + .INIT(64'hFFFFA1A05E5F0000)) + \FSM_sequential_dmacntrl_cs[0]_i_1__0 + (.I0(\FSM_sequential_dmacntrl_cs_reg[2]_0 [1]), + .I1(\FSM_sequential_dmacntrl_cs_reg[2]_0 [0]), + .I2(\FSM_sequential_dmacntrl_cs_reg[2]_0 [2]), + .I3(\FSM_sequential_dmacntrl_cs[2]_i_2__0_n_0 ), + .I4(\FSM_sequential_dmacntrl_cs[0]_i_2__0_n_0 ), + .I5(in0[0]), + .O(\FSM_sequential_dmacntrl_cs_reg[0] )); + LUT6 #( + .INIT(64'h88888B8BBB88BBBB)) + \FSM_sequential_dmacntrl_cs[0]_i_2__0 + (.I0(\FSM_sequential_dmacntrl_cs[0]_i_3__0_n_0 ), + .I1(\FSM_sequential_dmacntrl_cs_reg[2]_0 [0]), + .I2(dmacntrl_ns1), + .I3(\FSM_sequential_dmacntrl_cs[1]_i_3__0_n_0 ), + .I4(\FSM_sequential_dmacntrl_cs_reg[2]_0 [1]), + .I5(\FSM_sequential_dmacntrl_cs_reg[2]_0 [2]), + .O(\FSM_sequential_dmacntrl_cs[0]_i_2__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair48" *) LUT4 #( - .INIT(16'hF606)) - \dm_address[4]_i_9 - (.I0(stride_vid[4]), - .I1(\dm_address_reg[15]_0 [4]), - .I2(load_new_addr), - .I3(C[4]), - .O(\dm_address[4]_i_9_n_0 )); - LUT2 #( - .INIT(4'h2)) - \dm_address[8]_i_2 - (.I0(stride_vid[11]), - .I1(load_new_addr), - .O(\dm_address[8]_i_2_n_0 )); - LUT2 #( - .INIT(4'h2)) - \dm_address[8]_i_3 - (.I0(stride_vid[10]), - .I1(load_new_addr), - .O(\dm_address[8]_i_3_n_0 )); + .INIT(16'h0062)) + \FSM_sequential_dmacntrl_cs[0]_i_3__0 + (.I0(\FSM_sequential_dmacntrl_cs_reg[2]_0 [2]), + .I1(\FSM_sequential_dmacntrl_cs_reg[2]_0 [1]), + .I2(s_axis_cmd_tvalid_reg), + .I3(dmacntrl_ns15_out), + .O(\FSM_sequential_dmacntrl_cs[0]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hFFFFA1A05E5F0000)) + \FSM_sequential_dmacntrl_cs[1]_i_1__0 + (.I0(\FSM_sequential_dmacntrl_cs_reg[2]_0 [1]), + .I1(\FSM_sequential_dmacntrl_cs_reg[2]_0 [0]), + .I2(\FSM_sequential_dmacntrl_cs_reg[2]_0 [2]), + .I3(\FSM_sequential_dmacntrl_cs[2]_i_2__0_n_0 ), + .I4(\FSM_sequential_dmacntrl_cs[1]_i_2__0_n_0 ), + .I5(in0[1]), + .O(\FSM_sequential_dmacntrl_cs_reg[1] )); + LUT6 #( + .INIT(64'h04555F0004000A00)) + \FSM_sequential_dmacntrl_cs[1]_i_2__0 + (.I0(\FSM_sequential_dmacntrl_cs_reg[2]_0 [2]), + .I1(s_axis_cmd_tvalid_reg), + .I2(dmacntrl_ns15_out), + .I3(\FSM_sequential_dmacntrl_cs_reg[2]_0 [0]), + .I4(\FSM_sequential_dmacntrl_cs_reg[2]_0 [1]), + .I5(\FSM_sequential_dmacntrl_cs[1]_i_3__0_n_0 ), + .O(\FSM_sequential_dmacntrl_cs[1]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'h0000000000000010)) + \FSM_sequential_dmacntrl_cs[1]_i_3__0 + (.I0(s2mm_fsize_mismatch_err_flag), + .I1(frame_sync_reg), + .I2(s2mm_dmacr[0]), + .I3(s2mm_halt), + .I4(s2mm_soft_reset), + .I5(dma_err), + .O(\FSM_sequential_dmacntrl_cs[1]_i_3__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair49" *) LUT2 #( - .INIT(4'h2)) - \dm_address[8]_i_4 - (.I0(stride_vid[9]), - .I1(load_new_addr), - .O(\dm_address[8]_i_4_n_0 )); + .INIT(4'hE)) + \FSM_sequential_dmacntrl_cs[1]_i_4 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg ), + .I1(fsize_mismatch_err_flag_int), + .O(s2mm_fsize_mismatch_err_flag)); + LUT6 #( + .INIT(64'hFFFFA1A05E5F0000)) + \FSM_sequential_dmacntrl_cs[2]_i_1__0 + (.I0(\FSM_sequential_dmacntrl_cs_reg[2]_0 [1]), + .I1(\FSM_sequential_dmacntrl_cs_reg[2]_0 [0]), + .I2(\FSM_sequential_dmacntrl_cs_reg[2]_0 [2]), + .I3(\FSM_sequential_dmacntrl_cs[2]_i_2__0_n_0 ), + .I4(\FSM_sequential_dmacntrl_cs[2]_i_3__0_n_0 ), + .I5(in0[2]), + .O(\FSM_sequential_dmacntrl_cs_reg[2] )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFDFFF)) + \FSM_sequential_dmacntrl_cs[2]_i_2__0 + (.I0(s2mm_dmacr[0]), + .I1(halt_i_reg), + .I2(frame_sync_reg), + .I3(\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg ), + .I4(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg ), + .I5(fsize_mismatch_err_flag_int), + .O(\FSM_sequential_dmacntrl_cs[2]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'h0010001000000F00)) + \FSM_sequential_dmacntrl_cs[2]_i_3__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(dmacntrl_ns15_out), + .I2(\FSM_sequential_dmacntrl_cs_reg[2]_0 [0]), + .I3(\FSM_sequential_dmacntrl_cs_reg[2]_0 [2]), + .I4(dmacntrl_ns1), + .I5(\FSM_sequential_dmacntrl_cs_reg[2]_0 [1]), + .O(\FSM_sequential_dmacntrl_cs[2]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAABAAAAAAAA)) + \FSM_sequential_dmacntrl_cs[2]_i_4 + (.I0(dmacntrl_ns15_out), + .I1(vert_count_reg[10]), + .I2(vert_count_reg[12]), + .I3(vert_count_reg[7]), + .I4(vert_count_reg_1__s_net_1), + .I5(\vert_count_reg[11]_0 ), + .O(dmacntrl_ns1)); + LUT6 #( + .INIT(64'h0000000000000001)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_1__2 + (.I0(\cmnds_queued_reg[7] [0]), + .I1(\cmnds_queued_reg[7] [2]), + .I2(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_2__0_n_0 ), + .I3(\cmnds_queued_reg[7] [3]), + .I4(\cmnds_queued_reg[7] [4]), + .I5(\cmnds_queued_reg[1] ), + .O(s2mm_ftchcmdsts_idle)); + LUT5 #( + .INIT(32'hFFFFFFEF)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_2__0 + (.I0(\cmnds_queued_reg[7] [1]), + .I1(\FSM_sequential_dmacntrl_cs_reg[2]_0 [1]), + .I2(\FSM_sequential_dmacntrl_cs[2]_i_2__0_n_0 ), + .I3(\FSM_sequential_dmacntrl_cs_reg[2]_0 [2]), + .I4(\FSM_sequential_dmacntrl_cs_reg[2]_0 [0]), + .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_2__0_n_0 )); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s_out_d1_cdc_to), + .Q(s_out_d2), + .R(SR)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s_out_d2), + .Q(s_out_d3), + .R(SR)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s_out_d3), + .Q(s_out_d4), + .R(SR)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s_out_d4), + .Q(s_out_d5), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s_out_re__0), + .Q(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg ), + .R(SR)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(p_in_d1_cdc_from), + .Q(s_out_d1_cdc_to), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(prmry_in_xored), + .Q(p_in_d1_cdc_from), + .R(prmry_reset2)); + LUT3 #( + .INIT(8'h1E)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__10 + (.I0(drop_fsync_d_pulse_gen_fsize_less_err_d1), + .I1(fsize_mismatch_err_s1), + .I2(p_in_d1_cdc_from), + .O(prmry_in_xored)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(1'b1), + .Q(srst_d1), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(srst_d1), + .Q(srst_d2), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(srst_d2), + .Q(srst_d3), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(srst_d3), + .Q(srst_d4), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(srst_d4), + .Q(srst_d5), + .R(SR)); + LUT6 #( + .INIT(64'h0F0001000F0F0100)) + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_i_1 + (.I0(fsize_mismatch_err_flag_int), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg ), + .I2(prmry_resetn_i_reg), + .I3(s2mm_tstvect_fsync), + .I4(ch2_delay_cnt_en), + .I5(s2mm_packet_sof), + .O(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0 )); + (* SOFT_HLUTNM = "soft_lutpair49" *) + LUT4 #( + .INIT(16'hEFE0)) + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_irqthresh_decr_mask_sig_i_1 + (.I0(fsize_mismatch_err_flag_int), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg ), + .I2(s2mm_tstvect_fsync), + .I3(ch2_irqthresh_decr_mask_sig), + .O(\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_irqthresh_decr_mask_sig_reg )); + (* SOFT_HLUTNM = "soft_lutpair50" *) LUT2 #( .INIT(4'h2)) - \dm_address[8]_i_5 - (.I0(stride_vid[8]), - .I1(load_new_addr), - .O(\dm_address[8]_i_5_n_0 )); - LUT4 #( - .INIT(16'hF606)) - \dm_address[8]_i_6 - (.I0(stride_vid[11]), - .I1(\dm_address_reg[15]_0 [11]), - .I2(load_new_addr), - .I3(C[11]), - .O(\dm_address[8]_i_6_n_0 )); - LUT4 #( - .INIT(16'hF606)) - \dm_address[8]_i_7 - (.I0(stride_vid[10]), - .I1(\dm_address_reg[15]_0 [10]), - .I2(load_new_addr), - .I3(C[10]), - .O(\dm_address[8]_i_7_n_0 )); - LUT4 #( - .INIT(16'hF606)) - \dm_address[8]_i_8 - (.I0(stride_vid[9]), - .I1(\dm_address_reg[15]_0 [9]), - .I2(load_new_addr), - .I3(C[9]), - .O(\dm_address[8]_i_8_n_0 )); - LUT4 #( - .INIT(16'hF606)) - \dm_address[8]_i_9 - (.I0(stride_vid[8]), - .I1(\dm_address_reg[15]_0 [8]), - .I2(load_new_addr), - .I3(C[8]), - .O(\dm_address[8]_i_9_n_0 )); + \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1__0 + (.I0(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[0] ), + .I1(out), + .O(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[63] )); + LUT6 #( + .INIT(64'h00000008FFFFFFFF)) + \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2__0 + (.I0(\FSM_sequential_dmacntrl_cs_reg[2]_0 [1]), + .I1(\FSM_sequential_dmacntrl_cs_reg[2]_0 [0]), + .I2(\FSM_sequential_dmacntrl_cs_reg[2]_0 [2]), + .I3(dmacntrl_ns15_out), + .I4(s_axis_cmd_tvalid_reg), + .I5(out), + .O(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[0] )); + (* SOFT_HLUTNM = "soft_lutpair48" *) + LUT5 #( + .INIT(32'h01000000)) + \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_i_1__0 + (.I0(s_axis_cmd_tvalid_reg), + .I1(dmacntrl_ns15_out), + .I2(\FSM_sequential_dmacntrl_cs_reg[2]_0 [2]), + .I3(\FSM_sequential_dmacntrl_cs_reg[2]_0 [0]), + .I4(\FSM_sequential_dmacntrl_cs_reg[2]_0 [1]), + .O(write_cmnd_cmb)); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_i_2__0 + (.I0(dma_err), + .I1(s2mm_soft_reset), + .I2(s2mm_halt), + .I3(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg ), + .I4(fsize_mismatch_err_flag_int), + .I5(frame_sync_reg), + .O(dmacntrl_ns15_out)); + LUT6 #( + .INIT(64'hEEEEEEEEFFFFFEFF)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_1 + (.I0(fsize_mismatch_err_flag_int), + .I1(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg ), + .I2(s2mm_halt), + .I3(out), + .I4(s2mm_cdc2dmac_fsync), + .I5(s2mm_fsync_out_m_i), + .O(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[0] )); + LUT5 #( + .INIT(32'hAABAAAAA)) + \dm_address[0]_i_1__0 + (.I0(vert_count_reg_0__s_net_1), + .I1(dmacntrl_ns15_out), + .I2(\FSM_sequential_dmacntrl_cs_reg[2]_0 [0]), + .I3(\FSM_sequential_dmacntrl_cs_reg[2]_0 [1]), + .I4(\FSM_sequential_dmacntrl_cs_reg[2]_0 [2]), + .O(dm_address_reg_0__s_net_1)); + LUT3 #( + .INIT(8'hB8)) + \dm_address[16]_i_2__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][19] ), + .I1(vert_count_reg_0__s_net_1), + .I2(dm_address_reg[3]), + .O(\dm_address[16]_i_2__0_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[16]_i_3__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][18] ), + .I1(vert_count_reg_0__s_net_1), + .I2(dm_address_reg[2]), + .O(\dm_address[16]_i_3__0_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[16]_i_4__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][17] ), + .I1(vert_count_reg_0__s_net_1), + .I2(dm_address_reg[1]), + .O(\dm_address[16]_i_4__0_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[16]_i_5__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][16] ), + .I1(vert_count_reg_0__s_net_1), + .I2(dm_address_reg[0]), + .O(\dm_address[16]_i_5__0_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[20]_i_2__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][23] ), + .I1(vert_count_reg_0__s_net_1), + .I2(dm_address_reg[7]), + .O(\dm_address[20]_i_2__0_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[20]_i_3__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][22] ), + .I1(vert_count_reg_0__s_net_1), + .I2(dm_address_reg[6]), + .O(\dm_address[20]_i_3__0_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[20]_i_4__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][21] ), + .I1(vert_count_reg_0__s_net_1), + .I2(dm_address_reg[5]), + .O(\dm_address[20]_i_4__0_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[20]_i_5__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][20] ), + .I1(vert_count_reg_0__s_net_1), + .I2(dm_address_reg[4]), + .O(\dm_address[20]_i_5__0_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[24]_i_2__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][27] ), + .I1(vert_count_reg_0__s_net_1), + .I2(dm_address_reg[11]), + .O(\dm_address[24]_i_2__0_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[24]_i_3__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][26] ), + .I1(vert_count_reg_0__s_net_1), + .I2(dm_address_reg[10]), + .O(\dm_address[24]_i_3__0_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[24]_i_4__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][25] ), + .I1(vert_count_reg_0__s_net_1), + .I2(dm_address_reg[9]), + .O(\dm_address[24]_i_4__0_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[24]_i_5__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][24] ), + .I1(vert_count_reg_0__s_net_1), + .I2(dm_address_reg[8]), + .O(\dm_address[24]_i_5__0_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[28]_i_2__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31] ), + .I1(vert_count_reg_0__s_net_1), + .I2(dm_address_reg[15]), + .O(\dm_address[28]_i_2__0_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[28]_i_3__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][30] ), + .I1(vert_count_reg_0__s_net_1), + .I2(dm_address_reg[14]), + .O(\dm_address[28]_i_3__0_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[28]_i_4__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][29] ), + .I1(vert_count_reg_0__s_net_1), + .I2(dm_address_reg[13]), + .O(\dm_address[28]_i_4__0_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \dm_address[28]_i_5__0 + (.I0(\GEN_START_ADDR_REG[1].start_address_vid_reg[1][28] ), + .I1(vert_count_reg_0__s_net_1), + .I2(dm_address_reg[12]), + .O(\dm_address[28]_i_5__0_n_0 )); (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) - CARRY4 \dm_address_reg[0]_i_2 - (.CI(1'b0), - .CO({\dm_address_reg[0]_i_2_n_0 ,\dm_address_reg[0]_i_2_n_1 ,\dm_address_reg[0]_i_2_n_2 ,\dm_address_reg[0]_i_2_n_3 }), + CARRY4 \dm_address_reg[16]_i_1__0 + (.CI(CO), + .CO({\dm_address_reg[16]_i_1__0_n_0 ,\dm_address_reg[16]_i_1__0_n_1 ,\dm_address_reg[16]_i_1__0_n_2 ,\dm_address_reg[16]_i_1__0_n_3 }), .CYINIT(1'b0), - .DI({\dm_address[0]_i_3_n_0 ,\dm_address[0]_i_4_n_0 ,\dm_address[0]_i_5_n_0 ,\dm_address[0]_i_6_n_0 }), - .O(O), - .S({\dm_address[0]_i_7_n_0 ,\dm_address[0]_i_8_n_0 ,\dm_address[0]_i_9_n_0 ,\dm_address[0]_i_10_n_0 })); + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\dm_address_reg[19] ), + .S({\dm_address[16]_i_2__0_n_0 ,\dm_address[16]_i_3__0_n_0 ,\dm_address[16]_i_4__0_n_0 ,\dm_address[16]_i_5__0_n_0 })); (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) - CARRY4 \dm_address_reg[12]_i_1 - (.CI(\dm_address_reg[8]_i_1_n_0 ), - .CO({CO,\dm_address_reg[12]_i_1_n_1 ,\dm_address_reg[12]_i_1_n_2 ,\dm_address_reg[12]_i_1_n_3 }), + CARRY4 \dm_address_reg[20]_i_1__0 + (.CI(\dm_address_reg[16]_i_1__0_n_0 ), + .CO({\dm_address_reg[20]_i_1__0_n_0 ,\dm_address_reg[20]_i_1__0_n_1 ,\dm_address_reg[20]_i_1__0_n_2 ,\dm_address_reg[20]_i_1__0_n_3 }), .CYINIT(1'b0), - .DI({\dm_address[12]_i_2_n_0 ,\dm_address[12]_i_3_n_0 ,\dm_address[12]_i_4_n_0 ,\dm_address[12]_i_5_n_0 }), - .O(\dm_address_reg[15] ), - .S({\dm_address[12]_i_6_n_0 ,\dm_address[12]_i_7_n_0 ,\dm_address[12]_i_8_n_0 ,\dm_address[12]_i_9_n_0 })); + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\dm_address_reg[23] ), + .S({\dm_address[20]_i_2__0_n_0 ,\dm_address[20]_i_3__0_n_0 ,\dm_address[20]_i_4__0_n_0 ,\dm_address[20]_i_5__0_n_0 })); (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) - CARRY4 \dm_address_reg[4]_i_1 - (.CI(\dm_address_reg[0]_i_2_n_0 ), - .CO({\dm_address_reg[4]_i_1_n_0 ,\dm_address_reg[4]_i_1_n_1 ,\dm_address_reg[4]_i_1_n_2 ,\dm_address_reg[4]_i_1_n_3 }), + CARRY4 \dm_address_reg[24]_i_1__0 + (.CI(\dm_address_reg[20]_i_1__0_n_0 ), + .CO({\dm_address_reg[24]_i_1__0_n_0 ,\dm_address_reg[24]_i_1__0_n_1 ,\dm_address_reg[24]_i_1__0_n_2 ,\dm_address_reg[24]_i_1__0_n_3 }), .CYINIT(1'b0), - .DI({\dm_address[4]_i_2_n_0 ,\dm_address[4]_i_3_n_0 ,\dm_address[4]_i_4_n_0 ,\dm_address[4]_i_5_n_0 }), - .O(\dm_address_reg[7] ), - .S({\dm_address[4]_i_6_n_0 ,\dm_address[4]_i_7_n_0 ,\dm_address[4]_i_8_n_0 ,\dm_address[4]_i_9_n_0 })); + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\dm_address_reg[27] ), + .S({\dm_address[24]_i_2__0_n_0 ,\dm_address[24]_i_3__0_n_0 ,\dm_address[24]_i_4__0_n_0 ,\dm_address[24]_i_5__0_n_0 })); (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) - CARRY4 \dm_address_reg[8]_i_1 - (.CI(\dm_address_reg[4]_i_1_n_0 ), - .CO({\dm_address_reg[8]_i_1_n_0 ,\dm_address_reg[8]_i_1_n_1 ,\dm_address_reg[8]_i_1_n_2 ,\dm_address_reg[8]_i_1_n_3 }), + CARRY4 \dm_address_reg[28]_i_1__0 + (.CI(\dm_address_reg[24]_i_1__0_n_0 ), + .CO({\NLW_dm_address_reg[28]_i_1__0_CO_UNCONNECTED [3],\dm_address_reg[28]_i_1__0_n_1 ,\dm_address_reg[28]_i_1__0_n_2 ,\dm_address_reg[28]_i_1__0_n_3 }), .CYINIT(1'b0), - .DI({\dm_address[8]_i_2_n_0 ,\dm_address[8]_i_3_n_0 ,\dm_address[8]_i_4_n_0 ,\dm_address[8]_i_5_n_0 }), - .O(\dm_address_reg[11] ), - .S({\dm_address[8]_i_6_n_0 ,\dm_address[8]_i_7_n_0 ,\dm_address[8]_i_8_n_0 ,\dm_address[8]_i_9_n_0 })); - FDRE \hsize_vid_reg[0] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\reg_module_hsize_reg[15] [0]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [0]), - .R(p_0_in)); - FDRE \hsize_vid_reg[10] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\reg_module_hsize_reg[15] [10]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [10]), - .R(p_0_in)); - FDRE \hsize_vid_reg[11] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\reg_module_hsize_reg[15] [11]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [11]), - .R(p_0_in)); - FDRE \hsize_vid_reg[12] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\reg_module_hsize_reg[15] [12]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [12]), - .R(p_0_in)); - FDRE \hsize_vid_reg[13] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\reg_module_hsize_reg[15] [13]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [13]), - .R(p_0_in)); - FDRE \hsize_vid_reg[14] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\reg_module_hsize_reg[15] [14]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [14]), - .R(p_0_in)); - FDRE \hsize_vid_reg[15] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\reg_module_hsize_reg[15] [15]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [15]), - .R(p_0_in)); - FDRE \hsize_vid_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\reg_module_hsize_reg[15] [1]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [1]), - .R(p_0_in)); - FDRE \hsize_vid_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\reg_module_hsize_reg[15] [2]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [2]), - .R(p_0_in)); - FDRE \hsize_vid_reg[3] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\reg_module_hsize_reg[15] [3]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [3]), - .R(p_0_in)); - FDRE \hsize_vid_reg[4] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\reg_module_hsize_reg[15] [4]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [4]), - .R(p_0_in)); - FDRE \hsize_vid_reg[5] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\reg_module_hsize_reg[15] [5]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [5]), - .R(p_0_in)); - FDRE \hsize_vid_reg[6] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\reg_module_hsize_reg[15] [6]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [6]), - .R(p_0_in)); - FDRE \hsize_vid_reg[7] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\reg_module_hsize_reg[15] [7]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [7]), - .R(p_0_in)); - FDRE \hsize_vid_reg[8] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\reg_module_hsize_reg[15] [8]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [8]), - .R(p_0_in)); - FDRE \hsize_vid_reg[9] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\reg_module_hsize_reg[15] [9]), - .Q(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [9]), - .R(p_0_in)); - FDRE \stride_vid_reg[0] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [0]), - .Q(stride_vid[0]), - .R(p_0_in)); - FDRE \stride_vid_reg[10] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [10]), - .Q(stride_vid[10]), - .R(p_0_in)); - FDRE \stride_vid_reg[11] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [11]), - .Q(stride_vid[11]), - .R(p_0_in)); - FDRE \stride_vid_reg[12] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [12]), - .Q(stride_vid[12]), - .R(p_0_in)); - FDRE \stride_vid_reg[13] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [13]), - .Q(stride_vid[13]), - .R(p_0_in)); - FDRE \stride_vid_reg[14] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [14]), - .Q(stride_vid[14]), - .R(p_0_in)); - FDRE \stride_vid_reg[15] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [15]), - .Q(stride_vid[15]), - .R(p_0_in)); - FDRE \stride_vid_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [1]), - .Q(stride_vid[1]), - .R(p_0_in)); - FDRE \stride_vid_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [2]), - .Q(stride_vid[2]), - .R(p_0_in)); - FDRE \stride_vid_reg[3] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [3]), - .Q(stride_vid[3]), - .R(p_0_in)); - FDRE \stride_vid_reg[4] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [4]), - .Q(stride_vid[4]), - .R(p_0_in)); - FDRE \stride_vid_reg[5] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [5]), - .Q(stride_vid[5]), - .R(p_0_in)); - FDRE \stride_vid_reg[6] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [6]), - .Q(stride_vid[6]), - .R(p_0_in)); - FDRE \stride_vid_reg[7] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [7]), - .Q(stride_vid[7]), - .R(p_0_in)); - FDRE \stride_vid_reg[8] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [8]), - .Q(stride_vid[8]), - .R(p_0_in)); - FDRE \stride_vid_reg[9] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15] [9]), - .Q(stride_vid[9]), - .R(p_0_in)); + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\dm_address_reg[31] ), + .S({\dm_address[28]_i_2__0_n_0 ,\dm_address[28]_i_3__0_n_0 ,\dm_address[28]_i_4__0_n_0 ,\dm_address[28]_i_5__0_n_0 })); + LUT6 #( + .INIT(64'hEEFEEEFEFFFFEEFE)) + halt_i_i_2__0 + (.I0(\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg ), + .I1(s2mm_stop), + .I2(run_stop_d1), + .I3(s2mm_dmacr[0]), + .I4(s2mm_soft_reset), + .I5(soft_reset_d1), + .O(halt_i0)); + LUT3 #( + .INIT(8'h08)) + halted_set_i_i_1__0 + (.I0(s2mm_ftchcmdsts_idle), + .I1(datamover_idle), + .I2(s2mm_dmacr[0]), + .O(halted_set_i0)); + LUT3 #( + .INIT(8'h28)) + s_out_re + (.I0(srst_d5), + .I1(s_out_d5), + .I2(s_out_d4), + .O(s_out_re__0)); + LUT3 #( + .INIT(8'hC5)) + \vert_count[0]_i_10__0 + (.I0(vert_count_reg[1]), + .I1(Q[1]), + .I2(vert_count_reg_0__s_net_1), + .O(\vert_count[0]_i_10__0_n_0 )); + LUT3 #( + .INIT(8'hC5)) + \vert_count[0]_i_11__0 + (.I0(vert_count_reg[0]), + .I1(Q[0]), + .I2(vert_count_reg_0__s_net_1), + .O(\vert_count[0]_i_11__0_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFF00000008)) + \vert_count[0]_i_1__0 + (.I0(\FSM_sequential_dmacntrl_cs_reg[2]_0 [1]), + .I1(\FSM_sequential_dmacntrl_cs_reg[2]_0 [0]), + .I2(\FSM_sequential_dmacntrl_cs_reg[2]_0 [2]), + .I3(dmacntrl_ns15_out), + .I4(s_axis_cmd_tvalid_reg), + .I5(vert_count_reg_0__s_net_1), + .O(\vert_count_reg[0]_0 )); + LUT4 #( + .INIT(16'h1000)) + \vert_count[0]_i_3__0 + (.I0(\FSM_sequential_dmacntrl_cs_reg[2]_0 [0]), + .I1(\FSM_sequential_dmacntrl_cs_reg[2]_0 [2]), + .I2(\FSM_sequential_dmacntrl_cs_reg[2]_0 [1]), + .I3(\FSM_sequential_dmacntrl_cs[1]_i_3__0_n_0 ), + .O(vert_count_reg_0__s_net_1)); + LUT1 #( + .INIT(2'h1)) + \vert_count[0]_i_4__0 + (.I0(vert_count_reg_0__s_net_1), + .O(\vert_count[0]_i_4__0_n_0 )); + LUT1 #( + .INIT(2'h1)) + \vert_count[0]_i_5__0 + (.I0(vert_count_reg_0__s_net_1), + .O(\vert_count[0]_i_5__0_n_0 )); + LUT1 #( + .INIT(2'h1)) + \vert_count[0]_i_6__0 + (.I0(vert_count_reg_0__s_net_1), + .O(\vert_count[0]_i_6__0_n_0 )); + LUT1 #( + .INIT(2'h1)) + \vert_count[0]_i_7__0 + (.I0(vert_count_reg_0__s_net_1), + .O(\vert_count[0]_i_7__0_n_0 )); + LUT3 #( + .INIT(8'hC5)) + \vert_count[0]_i_8__0 + (.I0(vert_count_reg[3]), + .I1(Q[3]), + .I2(vert_count_reg_0__s_net_1), + .O(\vert_count[0]_i_8__0_n_0 )); + LUT3 #( + .INIT(8'hC5)) + \vert_count[0]_i_9__0 + (.I0(vert_count_reg[2]), + .I1(Q[2]), + .I2(vert_count_reg_0__s_net_1), + .O(\vert_count[0]_i_9__0_n_0 )); + LUT3 #( + .INIT(8'hA3)) + \vert_count[12]_i_2__0 + (.I0(Q[12]), + .I1(vert_count_reg[12]), + .I2(vert_count_reg_0__s_net_1), + .O(\vert_count[12]_i_2__0_n_0 )); + LUT1 #( + .INIT(2'h1)) + \vert_count[4]_i_2__0 + (.I0(vert_count_reg_0__s_net_1), + .O(\vert_count[4]_i_2__0_n_0 )); + LUT1 #( + .INIT(2'h1)) + \vert_count[4]_i_3__0 + (.I0(vert_count_reg_0__s_net_1), + .O(\vert_count[4]_i_3__0_n_0 )); + LUT1 #( + .INIT(2'h1)) + \vert_count[4]_i_4__0 + (.I0(vert_count_reg_0__s_net_1), + .O(\vert_count[4]_i_4__0_n_0 )); + LUT1 #( + .INIT(2'h1)) + \vert_count[4]_i_5__0 + (.I0(vert_count_reg_0__s_net_1), + .O(\vert_count[4]_i_5__0_n_0 )); + LUT3 #( + .INIT(8'hC5)) + \vert_count[4]_i_6__0 + (.I0(vert_count_reg[7]), + .I1(Q[7]), + .I2(vert_count_reg_0__s_net_1), + .O(\vert_count[4]_i_6__0_n_0 )); + LUT3 #( + .INIT(8'hC5)) + \vert_count[4]_i_7__0 + (.I0(vert_count_reg[6]), + .I1(Q[6]), + .I2(vert_count_reg_0__s_net_1), + .O(\vert_count[4]_i_7__0_n_0 )); + LUT3 #( + .INIT(8'hC5)) + \vert_count[4]_i_8__0 + (.I0(vert_count_reg[5]), + .I1(Q[5]), + .I2(vert_count_reg_0__s_net_1), + .O(\vert_count[4]_i_8__0_n_0 )); + LUT3 #( + .INIT(8'hC5)) + \vert_count[4]_i_9__0 + (.I0(vert_count_reg[4]), + .I1(Q[4]), + .I2(vert_count_reg_0__s_net_1), + .O(\vert_count[4]_i_9__0_n_0 )); + LUT1 #( + .INIT(2'h1)) + \vert_count[8]_i_2__0 + (.I0(vert_count_reg_0__s_net_1), + .O(\vert_count[8]_i_2__0_n_0 )); + LUT1 #( + .INIT(2'h1)) + \vert_count[8]_i_3__0 + (.I0(vert_count_reg_0__s_net_1), + .O(\vert_count[8]_i_3__0_n_0 )); + LUT1 #( + .INIT(2'h1)) + \vert_count[8]_i_4__0 + (.I0(vert_count_reg_0__s_net_1), + .O(\vert_count[8]_i_4__0_n_0 )); + LUT1 #( + .INIT(2'h1)) + \vert_count[8]_i_5__0 + (.I0(vert_count_reg_0__s_net_1), + .O(\vert_count[8]_i_5__0_n_0 )); + LUT3 #( + .INIT(8'hC5)) + \vert_count[8]_i_6__0 + (.I0(vert_count_reg[11]), + .I1(Q[11]), + .I2(vert_count_reg_0__s_net_1), + .O(\vert_count[8]_i_6__0_n_0 )); + LUT3 #( + .INIT(8'hC5)) + \vert_count[8]_i_7__0 + (.I0(vert_count_reg[10]), + .I1(Q[10]), + .I2(vert_count_reg_0__s_net_1), + .O(\vert_count[8]_i_7__0_n_0 )); + LUT3 #( + .INIT(8'hC5)) + \vert_count[8]_i_8__0 + (.I0(vert_count_reg[9]), + .I1(Q[9]), + .I2(vert_count_reg_0__s_net_1), + .O(\vert_count[8]_i_8__0_n_0 )); + LUT3 #( + .INIT(8'hC5)) + \vert_count[8]_i_9__0 + (.I0(vert_count_reg[8]), + .I1(Q[8]), + .I2(vert_count_reg_0__s_net_1), + .O(\vert_count[8]_i_9__0_n_0 )); + CARRY4 \vert_count_reg[0]_i_2__0 + (.CI(1'b0), + .CO({\vert_count_reg[0]_i_2__0_n_0 ,\vert_count_reg[0]_i_2__0_n_1 ,\vert_count_reg[0]_i_2__0_n_2 ,\vert_count_reg[0]_i_2__0_n_3 }), + .CYINIT(1'b0), + .DI({\vert_count[0]_i_4__0_n_0 ,\vert_count[0]_i_5__0_n_0 ,\vert_count[0]_i_6__0_n_0 ,\vert_count[0]_i_7__0_n_0 }), + .O(O), + .S({\vert_count[0]_i_8__0_n_0 ,\vert_count[0]_i_9__0_n_0 ,\vert_count[0]_i_10__0_n_0 ,\vert_count[0]_i_11__0_n_0 })); + CARRY4 \vert_count_reg[12]_i_1__0 + (.CI(\vert_count_reg[8]_i_1__0_n_0 ), + .CO(\NLW_vert_count_reg[12]_i_1__0_CO_UNCONNECTED [3:0]), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_vert_count_reg[12]_i_1__0_O_UNCONNECTED [3:1],\vert_count_reg[12] }), + .S({1'b0,1'b0,1'b0,\vert_count[12]_i_2__0_n_0 })); + CARRY4 \vert_count_reg[4]_i_1__0 + (.CI(\vert_count_reg[0]_i_2__0_n_0 ), + .CO({\vert_count_reg[4]_i_1__0_n_0 ,\vert_count_reg[4]_i_1__0_n_1 ,\vert_count_reg[4]_i_1__0_n_2 ,\vert_count_reg[4]_i_1__0_n_3 }), + .CYINIT(1'b0), + .DI({\vert_count[4]_i_2__0_n_0 ,\vert_count[4]_i_3__0_n_0 ,\vert_count[4]_i_4__0_n_0 ,\vert_count[4]_i_5__0_n_0 }), + .O(\vert_count_reg[7] ), + .S({\vert_count[4]_i_6__0_n_0 ,\vert_count[4]_i_7__0_n_0 ,\vert_count[4]_i_8__0_n_0 ,\vert_count[4]_i_9__0_n_0 })); + CARRY4 \vert_count_reg[8]_i_1__0 + (.CI(\vert_count_reg[4]_i_1__0_n_0 ), + .CO({\vert_count_reg[8]_i_1__0_n_0 ,\vert_count_reg[8]_i_1__0_n_1 ,\vert_count_reg[8]_i_1__0_n_2 ,\vert_count_reg[8]_i_1__0_n_3 }), + .CYINIT(1'b0), + .DI({\vert_count[8]_i_2__0_n_0 ,\vert_count[8]_i_3__0_n_0 ,\vert_count[8]_i_4__0_n_0 ,\vert_count[8]_i_5__0_n_0 }), + .O(\vert_count_reg[11] ), + .S({\vert_count[8]_i_6__0_n_0 ,\vert_count[8]_i_7__0_n_0 ,\vert_count[8]_i_8__0_n_0 ,\vert_count[8]_i_9__0_n_0 })); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized25 + (p_3_out, + s_axis_fifo_ainit_nosync, + s2mm_fsync_core, + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg , + s_valid0, + sig_last_reg_out_reg, + \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_s1_reg , + \GEN_S2MM_FLUSH_SOF_LOGIC.fsize_err_to_dm_halt_flag_reg , + prmry_reset2, + s_axis_s2mm_aclk, + SR, + s2mm_halt, + m_axi_s2mm_aclk, + out, + delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s, + delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1, + delay_s2mm_fsync_core_till_mmap_done_flag_d1, + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_reg , + run_stop_reg, + \sig_user_reg_out_reg[0] , + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg , + mmap_not_finished_s, + fsize_mismatch_err_s1, + drop_fsync_d_pulse_gen_fsize_less_err_d1, + fsize_err_to_dm_halt_flag, + M_VALID, + FULL, + s2mm_fsync_out_i, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg ); + output p_3_out; + output s_axis_fifo_ainit_nosync; + output s2mm_fsync_core; + output \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg ; + output s_valid0; + output sig_last_reg_out_reg; + output \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_s1_reg ; + output \GEN_S2MM_FLUSH_SOF_LOGIC.fsize_err_to_dm_halt_flag_reg ; + input prmry_reset2; + input s_axis_s2mm_aclk; + input [0:0]SR; + input s2mm_halt; + input m_axi_s2mm_aclk; + input out; + input delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s; + input delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1; + input delay_s2mm_fsync_core_till_mmap_done_flag_d1; + input \GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_reg ; + input run_stop_reg; + input \sig_user_reg_out_reg[0] ; + input \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ; + input mmap_not_finished_s; + input fsize_mismatch_err_s1; + input drop_fsync_d_pulse_gen_fsize_less_err_d1; + input fsize_err_to_dm_halt_flag; + input M_VALID; + input FULL; + input s2mm_fsync_out_i; + input \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg ; + + wire FULL; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_s1_reg ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_reg ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.fsize_err_to_dm_halt_flag_reg ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg ; + wire M_VALID; + wire [0:0]SR; + wire delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s; + wire delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1; + wire delay_s2mm_fsync_core_till_mmap_done_flag_d1; + wire drop_fsync_d_pulse_gen_fsize_less_err_d1; + wire fsize_err_to_dm_halt_flag; + wire fsize_mismatch_err_s1; + wire m_axi_s2mm_aclk; + wire mmap_not_finished_s; + wire out; + wire p_3_out; + wire p_level_in_d1_cdc_from; + wire prmry_reset2; + wire run_stop_reg; + wire s2mm_fsync_core; + wire s2mm_fsync_out_i; + wire s2mm_halt; + wire s_axis_fifo_ainit_nosync; + wire s_axis_s2mm_aclk; + wire s_fsync_d1_i_2_n_0; + wire s_level_out_d1_cdc_to; + wire s_level_out_d2; + wire s_level_out_d3; + wire s_valid0; + wire sig_last_reg_out_reg; + wire \sig_user_reg_out_reg[0] ; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(p_level_in_d1_cdc_from), + .Q(s_level_out_d1_cdc_to), + .R(prmry_reset2)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(s_level_out_d1_cdc_to), + .Q(s_level_out_d2), + .R(prmry_reset2)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(s_level_out_d2), + .Q(s_level_out_d3), + .R(prmry_reset2)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(s_level_out_d3), + .Q(p_3_out), + .R(prmry_reset2)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s2mm_halt), + .Q(p_level_in_d1_cdc_from), + .R(SR)); + LUT6 #( + .INIT(64'h00000000F4F4FFF4)) + \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_s1_i_1 + (.I0(delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s), + .I1(delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1), + .I2(s_fsync_d1_i_2_n_0), + .I3(delay_s2mm_fsync_core_till_mmap_done_flag_d1), + .I4(\GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_reg ), + .I5(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg ), + .O(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_s1_reg )); + (* SOFT_HLUTNM = "soft_lutpair83" *) + LUT4 #( + .INIT(16'hFFFE)) + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_i_3 + (.I0(p_3_out), + .I1(fsize_mismatch_err_s1), + .I2(drop_fsync_d_pulse_gen_fsize_less_err_d1), + .I3(fsize_err_to_dm_halt_flag), + .O(\GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg )); + (* SOFT_HLUTNM = "soft_lutpair83" *) + LUT5 #( + .INIT(32'h0000FE00)) + \GEN_S2MM_FLUSH_SOF_LOGIC.fsize_err_to_dm_halt_flag_i_1 + (.I0(fsize_err_to_dm_halt_flag), + .I1(fsize_mismatch_err_s1), + .I2(drop_fsync_d_pulse_gen_fsize_less_err_d1), + .I3(out), + .I4(p_3_out), + .O(\GEN_S2MM_FLUSH_SOF_LOGIC.fsize_err_to_dm_halt_flag_reg )); + LUT5 #( + .INIT(32'hF4F4FFF4)) + s_fsync_d1_i_1 + (.I0(delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s), + .I1(delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1), + .I2(s_fsync_d1_i_2_n_0), + .I3(delay_s2mm_fsync_core_till_mmap_done_flag_d1), + .I4(\GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_reg ), + .O(s2mm_fsync_core)); + LUT6 #( + .INIT(64'h0404040004040404)) + s_fsync_d1_i_2 + (.I0(\GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg ), + .I1(run_stop_reg), + .I2(\sig_user_reg_out_reg[0] ), + .I3(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ), + .I4(\GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_reg ), + .I5(mmap_not_finished_s), + .O(s_fsync_d1_i_2_n_0)); + LUT6 #( + .INIT(64'h0000000000000800)) + s_valid_i_1 + (.I0(M_VALID), + .I1(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ), + .I2(p_3_out), + .I3(out), + .I4(FULL), + .I5(s2mm_fsync_out_i), + .O(s_valid0)); + (* SOFT_HLUTNM = "soft_lutpair82" *) + LUT5 #( + .INIT(32'hFFFFFFDF)) + sig_last_reg_out_i_4__0 + (.I0(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ), + .I1(p_3_out), + .I2(out), + .I3(FULL), + .I4(s2mm_fsync_out_i), + .O(sig_last_reg_out_reg)); + (* SOFT_HLUTNM = "soft_lutpair82" *) + LUT2 #( + .INIT(4'hB)) + sig_last_skid_reg_i_1__1 + (.I0(p_3_out), + .I1(out), + .O(s_axis_fifo_ainit_nosync)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized26 + (\GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg , + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg_0 , + prmry_reset2, + s_axis_s2mm_aclk, + SR, + s2mm_dmacr, + m_axi_s2mm_aclk, + delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s, + \sig_user_reg_out_reg[0] , + out, + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ); + output \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg ; + output \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg_0 ; + input prmry_reset2; + input s_axis_s2mm_aclk; + input [0:0]SR; + input [0:0]s2mm_dmacr; + input m_axi_s2mm_aclk; + input delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s; + input \sig_user_reg_out_reg[0] ; + input out; + input \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ; + + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg_0 ; + wire [0:0]SR; + wire delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s; + wire m_axi_s2mm_aclk; + wire out; + wire p_level_in_d1_cdc_from; + wire prmry_reset2; + wire [0:0]s2mm_dmacr; + wire s_axis_s2mm_aclk; + wire s_level_out_d1_cdc_to; + wire s_level_out_d2; + wire s_level_out_d3; + wire \sig_user_reg_out_reg[0] ; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(p_level_in_d1_cdc_from), + .Q(s_level_out_d1_cdc_to), + .R(prmry_reset2)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(s_level_out_d1_cdc_to), + .Q(s_level_out_d2), + .R(prmry_reset2)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(s_level_out_d2), + .Q(s_level_out_d3), + .R(prmry_reset2)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(s_level_out_d3), + .Q(\GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg ), + .R(prmry_reset2)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s2mm_dmacr), + .Q(p_level_in_d1_cdc_from), + .R(SR)); + LUT5 #( + .INIT(32'hBA000000)) + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_i_1 + (.I0(delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s), + .I1(\sig_user_reg_out_reg[0] ), + .I2(\GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg ), + .I3(out), + .I4(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ), + .O(\GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg_0 )); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized27 + (p_in_d1_cdc_from, + \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.s2mm_fsync_out_m_d1_reg , + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg , + E, + prmry_reset2, + prmry_in_xored, + s_axis_s2mm_aclk, + SR, + m_axi_s2mm_aclk, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[6] , + sig_s_ready_out_reg, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] , + Q, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[3] , + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[6]_0 ); + output p_in_d1_cdc_from; + output \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.s2mm_fsync_out_m_d1_reg ; + output \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg ; + output [0:0]E; + input prmry_reset2; + input prmry_in_xored; + input s_axis_s2mm_aclk; + input [0:0]SR; + input m_axi_s2mm_aclk; + input \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[6] ; + input sig_s_ready_out_reg; + input \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ; + input [0:0]Q; + input \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[3] ; + input \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[6]_0 ; + + wire [0:0]E; + wire \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.s2mm_fsync_out_m_d1_reg ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[3] ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[6] ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[6]_0 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg ; + wire [0:0]Q; + wire [0:0]SR; + wire m_axi_s2mm_aclk; + wire p_in_d1_cdc_from; + wire prmry_in_xored; + wire prmry_reset2; + wire s_axis_s2mm_aclk; + wire s_out_d1_cdc_to; + wire s_out_d2; + wire s_out_d3; + wire s_out_d4; + wire s_out_d5; + wire s_out_re__0; + wire sig_s_ready_out_reg; + wire srst_d1; + wire srst_d2; + wire srst_d3; + wire srst_d4; + wire srst_d5; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s_out_d1_cdc_to), + .Q(s_out_d2), + .R(SR)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s_out_d2), + .Q(s_out_d3), + .R(SR)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s_out_d3), + .Q(s_out_d4), + .R(SR)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s_out_d4), + .Q(s_out_d5), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s_out_re__0), + .Q(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.s2mm_fsync_out_m_d1_reg ), + .R(SR)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(p_in_d1_cdc_from), + .Q(s_out_d1_cdc_to), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(prmry_in_xored), + .Q(p_in_d1_cdc_from), + .R(prmry_reset2)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(1'b1), + .Q(srst_d1), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(srst_d1), + .Q(srst_d2), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(srst_d2), + .Q(srst_d3), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(srst_d3), + .Q(srst_d4), + .R(SR)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(srst_d4), + .Q(srst_d5), + .R(SR)); + LUT6 #( + .INIT(64'hBBBBBBBBBBBBBBBA)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_2 + (.I0(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.s2mm_fsync_out_m_d1_reg ), + .I1(sig_s_ready_out_reg), + .I2(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ), + .I3(Q), + .I4(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[3] ), + .I5(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[6]_0 ), + .O(E)); LUT3 #( - .INIT(8'hB0)) - \vsize_vid[12]_i_1 - (.I0(p_23_out), - .I1(\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg ), - .I2(\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg ), - .O(video_reg_update)); - FDRE \vsize_vid_reg[0] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\reg_module_vsize_reg[12] [0]), - .Q(Q[0]), - .R(p_0_in)); - FDRE \vsize_vid_reg[10] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\reg_module_vsize_reg[12] [10]), - .Q(Q[10]), - .R(p_0_in)); - FDRE \vsize_vid_reg[11] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\reg_module_vsize_reg[12] [11]), - .Q(Q[11]), - .R(p_0_in)); - FDRE \vsize_vid_reg[12] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\reg_module_vsize_reg[12] [12]), - .Q(Q[12]), - .R(p_0_in)); - FDRE \vsize_vid_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\reg_module_vsize_reg[12] [1]), - .Q(Q[1]), - .R(p_0_in)); - FDRE \vsize_vid_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\reg_module_vsize_reg[12] [2]), - .Q(Q[2]), - .R(p_0_in)); - FDRE \vsize_vid_reg[3] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\reg_module_vsize_reg[12] [3]), - .Q(Q[3]), - .R(p_0_in)); - FDRE \vsize_vid_reg[4] - (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\reg_module_vsize_reg[12] [4]), - .Q(Q[4]), - .R(p_0_in)); - FDRE \vsize_vid_reg[5] + .INIT(8'hA8)) + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_i_1 + (.I0(E), + .I1(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[6] ), + .I2(\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.s2mm_fsync_out_m_d1_reg ), + .O(\GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg )); + LUT3 #( + .INIT(8'h28)) + s_out_re + (.I0(srst_d5), + .I1(s_out_d5), + .I2(s_out_d4), + .O(s_out_re__0)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized29 + (mmap_not_finished_s, + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_reg , + prmry_reset2, + s_axis_s2mm_aclk, + SR, + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg , + m_axi_s2mm_aclk, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg , + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_reg_0 , + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 , + \sig_user_reg_out_reg[0] , + out); + output mmap_not_finished_s; + output \GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_reg ; + input prmry_reset2; + input s_axis_s2mm_aclk; + input [0:0]SR; + input \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg ; + input m_axi_s2mm_aclk; + input \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ; + input \GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_reg_0 ; + input \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ; + input \sig_user_reg_out_reg[0] ; + input out; + + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_reg ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_reg_0 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ; + wire [0:0]SR; + wire m_axi_s2mm_aclk; + wire mmap_not_finished_s; + wire out; + wire p_level_in_d1_cdc_from; + wire prmry_reset2; + wire s_axis_s2mm_aclk; + wire s_level_out_d1_cdc_to; + wire s_level_out_d2; + wire s_level_out_d3; + wire \sig_user_reg_out_reg[0] ; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(p_level_in_d1_cdc_from), + .Q(s_level_out_d1_cdc_to), + .R(prmry_reset2)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(s_level_out_d1_cdc_to), + .Q(s_level_out_d2), + .R(prmry_reset2)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(s_level_out_d2), + .Q(s_level_out_d3), + .R(prmry_reset2)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(s_level_out_d3), + .Q(mmap_not_finished_s), + .R(prmry_reset2)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg ), + .Q(p_level_in_d1_cdc_from), + .R(SR)); + LUT6 #( + .INIT(64'hC0C004C000000000)) + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_i_1 + (.I0(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ), + .I1(mmap_not_finished_s), + .I2(\GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_reg_0 ), + .I3(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ), + .I4(\sig_user_reg_out_reg[0] ), + .I5(out), + .O(\GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_reg )); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized2_7 + (scndry_out, + m_axis_mm2s_aclk, + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 , + m_axi_mm2s_aclk); + output scndry_out; + input m_axis_mm2s_aclk; + input \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ; + input m_axi_mm2s_aclk; + + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ; + wire m_axi_mm2s_aclk; + wire m_axis_mm2s_aclk; + wire p_level_in_d1_cdc_from; + wire s_level_out_d1_cdc_to; + wire s_level_out_d2; + wire s_level_out_d3; + wire scndry_out; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(p_level_in_d1_cdc_from), + .Q(s_level_out_d1_cdc_to), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(s_level_out_d1_cdc_to), + .Q(s_level_out_d2), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(s_level_out_d2), + .Q(s_level_out_d3), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(s_level_out_d3), + .Q(scndry_out), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\reg_module_vsize_reg[12] [5]), - .Q(Q[5]), - .R(p_0_in)); - FDRE \vsize_vid_reg[6] + .CE(1'b1), + .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ), + .Q(p_level_in_d1_cdc_from), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized3 + (scndry_out, + m_axi_s2mm_aclk, + axis_min_assert_sftrst, + s_axis_s2mm_aclk); + output scndry_out; + input m_axi_s2mm_aclk; + input axis_min_assert_sftrst; + input s_axis_s2mm_aclk; + + wire axis_min_assert_sftrst; + wire m_axi_s2mm_aclk; + wire p_level_in_d1_cdc_from; + wire s_axis_s2mm_aclk; + wire s_level_out_d1_cdc_to; + wire s_level_out_d2; + wire s_level_out_d3; + wire scndry_out; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(p_level_in_d1_cdc_from), + .Q(s_level_out_d1_cdc_to), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s_level_out_d1_cdc_to), + .Q(s_level_out_d2), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s_level_out_d2), + .Q(s_level_out_d3), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s_level_out_d3), + .Q(scndry_out), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(axis_min_assert_sftrst), + .Q(p_level_in_d1_cdc_from), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized3_8 + (scndry_out, + m_axi_mm2s_aclk, + axis_min_assert_sftrst, + m_axis_mm2s_aclk); + output scndry_out; + input m_axi_mm2s_aclk; + input axis_min_assert_sftrst; + input m_axis_mm2s_aclk; + + wire axis_min_assert_sftrst; + wire m_axi_mm2s_aclk; + wire m_axis_mm2s_aclk; + wire p_level_in_d1_cdc_from; + wire s_level_out_d1_cdc_to; + wire s_level_out_d2; + wire s_level_out_d3; + wire scndry_out; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\reg_module_vsize_reg[12] [6]), - .Q(Q[6]), - .R(p_0_in)); - FDRE \vsize_vid_reg[7] + .CE(1'b1), + .D(p_level_in_d1_cdc_from), + .Q(s_level_out_d1_cdc_to), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\reg_module_vsize_reg[12] [7]), - .Q(Q[7]), - .R(p_0_in)); - FDRE \vsize_vid_reg[8] + .CE(1'b1), + .D(s_level_out_d1_cdc_to), + .Q(s_level_out_d2), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\reg_module_vsize_reg[12] [8]), - .Q(Q[8]), - .R(p_0_in)); - FDRE \vsize_vid_reg[9] + .CE(1'b1), + .D(s_level_out_d2), + .Q(s_level_out_d3), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 (.C(m_axi_mm2s_aclk), - .CE(video_reg_update), - .D(\reg_module_vsize_reg[12] [9]), - .Q(Q[9]), - .R(p_0_in)); + .CE(1'b1), + .D(s_level_out_d3), + .Q(scndry_out), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from + (.C(m_axis_mm2s_aclk), + .CE(1'b1), + .D(axis_min_assert_sftrst), + .Q(p_level_in_d1_cdc_from), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized4 + (prmry_in, + run_stop_d1_reg, + prmry_reset2_0, + \dmacr_i_reg[2] , + halt_i_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0, + reset_counts_reg, + min_assert_sftrst, + s_soft_reset_i, + s2mm_dmacr, + s2mm_stop, + s2mm_soft_reset, + s2mm_axi2ip_wrce, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[2] , + assert_sftrst_d1, + halt_i_reg_0, + halt_reset_reg, + halt_i0, + reset_counts_5, + out, + m_axi_s2mm_aclk, + hrd_resetn_i_reg, + s_axi_lite_aclk); + output prmry_in; + output run_stop_d1_reg; + output prmry_reset2_0; + output \dmacr_i_reg[2] ; + output halt_i_reg; + output sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0; + output reset_counts_reg; + input min_assert_sftrst; + input s_soft_reset_i; + input [0:0]s2mm_dmacr; + input s2mm_stop; + input s2mm_soft_reset; + input [0:0]s2mm_axi2ip_wrce; + input [0:0]\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[2] ; + input assert_sftrst_d1; + input halt_i_reg_0; + input halt_reset_reg; + input halt_i0; + input reset_counts_5; + input out; + input m_axi_s2mm_aclk; + input hrd_resetn_i_reg; + input s_axi_lite_aclk; + + wire [0:0]\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[2] ; + wire assert_sftrst_d1; + wire \dmacr_i_reg[2] ; + wire halt_i0; + wire halt_i_reg; + wire halt_i_reg_0; + wire halt_reset_reg; + wire hrd_resetn_i_reg; + wire m_axi_s2mm_aclk; + wire min_assert_sftrst; + wire out; + wire p_level_in_d1_cdc_from; + wire prmry_in; + wire prmry_reset2_0; + wire reset_counts_5; + wire reset_counts_reg; + wire run_stop_d1_reg; + wire [0:0]s2mm_axi2ip_wrce; + wire [0:0]s2mm_dmacr; + wire s2mm_hrd_resetn; + wire s2mm_soft_reset; + wire s2mm_stop; + wire s_axi_lite_aclk; + wire s_level_out_d1_cdc_to; + wire s_level_out_d2; + wire s_level_out_d3; + wire s_soft_reset_i; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(p_level_in_d1_cdc_from), + .Q(s_level_out_d1_cdc_to), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s_level_out_d1_cdc_to), + .Q(s_level_out_d2), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s_level_out_d2), + .Q(s_level_out_d3), + .R(1'b0)); + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(s_level_out_d3), + .Q(s2mm_hrd_resetn), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from + (.C(s_axi_lite_aclk), + .CE(1'b1), + .D(hrd_resetn_i_reg), + .Q(p_level_in_d1_cdc_from), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair265" *) LUT3 #( .INIT(8'h02)) - zero_hsize_err_i_1 - (.I0(load_new_addr), - .I1(zero_hsize_err_i_2_n_0), - .I2(zero_hsize_err_i_3_n_0), - .O(zero_hsize_err0)); - LUT5 #( - .INIT(32'hFFFFFFFE)) - zero_hsize_err_i_2 - (.I0(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [5]), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [4]), - .I2(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [7]), - .I3(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [6]), - .I4(zero_hsize_err_i_4_n_0), - .O(zero_hsize_err_i_2_n_0)); - LUT5 #( - .INIT(32'hFFFFFFFE)) - zero_hsize_err_i_3 - (.I0(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [13]), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [12]), - .I2(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [14]), - .I3(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [15]), - .I4(zero_hsize_err_i_5_n_0), - .O(zero_hsize_err_i_3_n_0)); - LUT4 #( - .INIT(16'hFFFE)) - zero_hsize_err_i_4 - (.I0(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [2]), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [3]), - .I2(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [0]), - .I3(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [1]), - .O(zero_hsize_err_i_4_n_0)); - LUT4 #( - .INIT(16'hFFFE)) - zero_hsize_err_i_5 - (.I0(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [10]), - .I1(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [11]), - .I2(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [8]), - .I3(\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15] [9]), - .O(zero_hsize_err_i_5_n_0)); + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_1__0 + (.I0(s2mm_hrd_resetn), + .I1(min_assert_sftrst), + .I2(s_soft_reset_i), + .O(prmry_in)); + LUT1 #( + .INIT(2'h1)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to_i_1__0 + (.I0(s2mm_hrd_resetn), + .O(prmry_reset2_0)); LUT6 #( - .INIT(64'h0000000000000100)) - zero_vsize_err_i_1 - (.I0(zero_vsize_err_i_2_n_0), - .I1(Q[1]), - .I2(Q[2]), - .I3(load_new_addr), - .I4(Q[0]), - .I5(zero_vsize_err_i_4_n_0), - .O(zero_vsize_err0)); + .INIT(64'hAE00AEAE00000000)) + \I_DMA_REGISTER/reset_counts_i_1__0 + (.I0(reset_counts_5), + .I1(s2mm_soft_reset), + .I2(out), + .I3(min_assert_sftrst), + .I4(assert_sftrst_d1), + .I5(s2mm_hrd_resetn), + .O(reset_counts_reg)); LUT6 #( - .INIT(64'hFFFFFFFFFFFFFFFE)) - zero_vsize_err_i_2 - (.I0(Q[12]), - .I1(Q[11]), - .I2(Q[8]), - .I3(Q[7]), - .I4(Q[10]), - .I5(Q[9]), - .O(zero_vsize_err_i_2_n_0)); + .INIT(64'hEA00EAEA00000000)) + \dmacr_i[2]_i_1__0 + (.I0(s2mm_soft_reset), + .I1(s2mm_axi2ip_wrce), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[2] ), + .I3(min_assert_sftrst), + .I4(assert_sftrst_d1), + .I5(s2mm_hrd_resetn), + .O(\dmacr_i_reg[2] )); + LUT5 #( + .INIT(32'hAAAA0888)) + halt_i_i_1__0 + (.I0(prmry_in), + .I1(halt_i_reg_0), + .I2(halt_reset_reg), + .I3(s2mm_dmacr), + .I4(halt_i0), + .O(halt_i_reg)); + LUT6 #( + .INIT(64'h0000000000000200)) + run_stop_d1_i_1__0 + (.I0(s2mm_dmacr), + .I1(s2mm_stop), + .I2(s2mm_soft_reset), + .I3(s2mm_hrd_resetn), + .I4(min_assert_sftrst), + .I5(s_soft_reset_i), + .O(run_stop_d1_reg)); + (* SOFT_HLUTNM = "soft_lutpair265" *) LUT4 #( - .INIT(16'hFFFE)) - zero_vsize_err_i_4 - (.I0(Q[5]), - .I1(Q[6]), - .I2(Q[3]), - .I3(Q[4]), - .O(zero_vsize_err_i_4_n_0)); + .INIT(16'h0010)) + sig_s2mm_dm_prmry_resetn_inferred_i_1 + (.I0(s_soft_reset_i), + .I1(min_assert_sftrst), + .I2(s2mm_hrd_resetn), + .I3(halt_reset_reg), + .O(sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0)); endmodule (* ORIG_REF_NAME = "cdc_sync" *) -module Arty_Z7_20_axi_vdma_0_0_cdc_sync - (p_in_d1_cdc_from, - p_1_out, - SR, - prmry_in_xored, +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized4_15 + (prmry_in, + run_stop_d1_reg, + prmry_reset2, + \dmacr_i_reg[2] , + halt_i_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0, + reset_counts_reg, + min_assert_sftrst, + s_soft_reset_i, + p_71_out, + stop, + p_77_out, + mm2s_axi2ip_wrce, + D, + assert_sftrst_d1, + halt_i_reg_0, + halt_reset_reg, + halt_i0, + reset_counts, + out, m_axi_mm2s_aclk, - m_axis_mm2s_aclk, - p_3_out); - output p_in_d1_cdc_from; - output p_1_out; - output [0:0]SR; - input prmry_in_xored; + hrd_resetn_i_reg, + s_axi_lite_aclk); + output prmry_in; + output run_stop_d1_reg; + output prmry_reset2; + output \dmacr_i_reg[2] ; + output halt_i_reg; + output sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0; + output reset_counts_reg; + input min_assert_sftrst; + input s_soft_reset_i; + input [0:0]p_71_out; + input stop; + input p_77_out; + input [0:0]mm2s_axi2ip_wrce; + input [0:0]D; + input assert_sftrst_d1; + input halt_i_reg_0; + input halt_reset_reg; + input halt_i0; + input reset_counts; + input out; input m_axi_mm2s_aclk; - input m_axis_mm2s_aclk; - input p_3_out; + input hrd_resetn_i_reg; + input s_axi_lite_aclk; - wire [0:0]SR; + wire [0:0]D; + wire assert_sftrst_d1; + wire \dmacr_i_reg[2] ; + wire halt_i0; + wire halt_i_reg; + wire halt_i_reg_0; + wire halt_reset_reg; + wire hrd_resetn_i_reg; wire m_axi_mm2s_aclk; - wire m_axis_mm2s_aclk; - wire p_1_out; - wire p_3_out; - wire p_in_d1_cdc_from; - wire prmry_in_xored; - wire s_out_d1_cdc_to; - wire s_out_d2; - wire s_out_d3; - wire s_out_d4; - wire s_out_d5; - wire s_out_re__0; - wire srst_d1; - wire srst_d2; - wire srst_d3; - wire srst_d4; - wire srst_d5; + wire min_assert_sftrst; + wire [0:0]mm2s_axi2ip_wrce; + wire mm2s_hrd_resetn; + wire out; + wire [0:0]p_71_out; + wire p_77_out; + wire p_level_in_d1_cdc_from; + wire prmry_in; + wire prmry_reset2; + wire reset_counts; + wire reset_counts_reg; + wire run_stop_d1_reg; + wire s_axi_lite_aclk; + wire s_level_out_d1_cdc_to; + wire s_level_out_d2; + wire s_level_out_d3; + wire s_soft_reset_i; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0; + wire stop; (* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2 - (.C(m_axis_mm2s_aclk), + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(s_out_d1_cdc_to), - .Q(s_out_d2), + .D(p_level_in_d1_cdc_from), + .Q(s_level_out_d1_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3 - (.C(m_axis_mm2s_aclk), + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 + (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(s_out_d2), - .Q(s_out_d3), + .D(s_level_out_d1_cdc_to), + .Q(s_level_out_d2), .R(1'b0)); (* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4 - (.C(m_axis_mm2s_aclk), + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 + (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(s_out_d3), - .Q(s_out_d4), + .D(s_level_out_d2), + .Q(s_level_out_d3), .R(1'b0)); (* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5 - (.C(m_axis_mm2s_aclk), + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 + (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(s_out_d4), - .Q(s_out_d5), + .D(s_level_out_d3), + .Q(mm2s_hrd_resetn), .R(1'b0)); (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out - (.C(m_axis_mm2s_aclk), + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from + (.C(s_axi_lite_aclk), .CE(1'b1), - .D(s_out_re__0), - .Q(p_1_out), + .D(hrd_resetn_i_reg), + .Q(p_level_in_d1_cdc_from), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair256" *) + LUT3 #( + .INIT(8'h02)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_1 + (.I0(mm2s_hrd_resetn), + .I1(min_assert_sftrst), + .I2(s_soft_reset_i), + .O(prmry_in)); + LUT1 #( + .INIT(2'h1)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to_i_1 + (.I0(mm2s_hrd_resetn), + .O(prmry_reset2)); + LUT6 #( + .INIT(64'hAE00AEAE00000000)) + \I_DMA_REGISTER/reset_counts_i_1 + (.I0(reset_counts), + .I1(p_77_out), + .I2(out), + .I3(min_assert_sftrst), + .I4(assert_sftrst_d1), + .I5(mm2s_hrd_resetn), + .O(reset_counts_reg)); + LUT6 #( + .INIT(64'hEA00EAEA00000000)) + \dmacr_i[2]_i_1 + (.I0(p_77_out), + .I1(mm2s_axi2ip_wrce), + .I2(D), + .I3(min_assert_sftrst), + .I4(assert_sftrst_d1), + .I5(mm2s_hrd_resetn), + .O(\dmacr_i_reg[2] )); + LUT5 #( + .INIT(32'hAAAA0888)) + halt_i_i_1 + (.I0(prmry_in), + .I1(halt_i_reg_0), + .I2(halt_reset_reg), + .I3(p_71_out), + .I4(halt_i0), + .O(halt_i_reg)); + LUT6 #( + .INIT(64'h0000000000000200)) + run_stop_d1_i_1 + (.I0(p_71_out), + .I1(stop), + .I2(p_77_out), + .I3(mm2s_hrd_resetn), + .I4(min_assert_sftrst), + .I5(s_soft_reset_i), + .O(run_stop_d1_reg)); + (* SOFT_HLUTNM = "soft_lutpair256" *) + LUT4 #( + .INIT(16'h0010)) + sig_mm2s_dm_prmry_resetn_inferred_i_1 + (.I0(s_soft_reset_i), + .I1(min_assert_sftrst), + .I2(mm2s_hrd_resetn), + .I3(halt_reset_reg), + .O(sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized5 + (scndry_out, + s_axis_s2mm_aclk, + prmry_in, + m_axi_s2mm_aclk); + output scndry_out; + input s_axis_s2mm_aclk; + input prmry_in; + input m_axi_s2mm_aclk; + + wire m_axi_s2mm_aclk; + wire p_level_in_d1_cdc_from; + wire prmry_in; + wire s_axis_s2mm_aclk; + wire s_level_out_d1_cdc_to; + wire s_level_out_d2; + wire s_level_out_d3; + wire scndry_out; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(p_level_in_d1_cdc_from), + .Q(s_level_out_d1_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to - (.C(m_axis_mm2s_aclk), + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(p_in_d1_cdc_from), - .Q(s_out_d1_cdc_to), + .D(s_level_out_d1_cdc_to), + .Q(s_level_out_d2), .R(1'b0)); + (* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from - (.C(m_axi_mm2s_aclk), + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(prmry_in_xored), - .Q(p_in_d1_cdc_from), + .D(s_level_out_d2), + .Q(s_level_out_d3), .R(1'b0)); + (* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1 - (.C(m_axis_mm2s_aclk), + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(1'b1), - .Q(srst_d1), + .D(s_level_out_d3), + .Q(scndry_out), .R(1'b0)); (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2 + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(prmry_in), + .Q(p_level_in_d1_cdc_from), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized5_14 + (scndry_out, + m_axis_mm2s_aclk, + prmry_in, + m_axi_mm2s_aclk); + output scndry_out; + input m_axis_mm2s_aclk; + input prmry_in; + input m_axi_mm2s_aclk; + + wire m_axi_mm2s_aclk; + wire m_axis_mm2s_aclk; + wire p_level_in_d1_cdc_from; + wire prmry_in; + wire s_level_out_d1_cdc_to; + wire s_level_out_d2; + wire s_level_out_d3; + wire scndry_out; + + (* ASYNC_REG *) + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to (.C(m_axis_mm2s_aclk), .CE(1'b1), - .D(srst_d1), - .Q(srst_d2), + .D(p_level_in_d1_cdc_from), + .Q(s_level_out_d1_cdc_to), .R(1'b0)); + (* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3 + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 (.C(m_axis_mm2s_aclk), .CE(1'b1), - .D(srst_d2), - .Q(srst_d3), + .D(s_level_out_d1_cdc_to), + .Q(s_level_out_d2), .R(1'b0)); + (* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4 + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 (.C(m_axis_mm2s_aclk), .CE(1'b1), - .D(srst_d3), - .Q(srst_d4), + .D(s_level_out_d2), + .Q(s_level_out_d3), .R(1'b0)); + (* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5 + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 (.C(m_axis_mm2s_aclk), .CE(1'b1), - .D(srst_d4), - .Q(srst_d5), + .D(s_level_out_d3), + .Q(scndry_out), + .R(1'b0)); + (* XILINX_LEGACY_PRIM = "FDR" *) + (* box_type = "PRIMITIVE" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(prmry_in), + .Q(p_level_in_d1_cdc_from), .R(1'b0)); - LUT2 #( - .INIT(4'hE)) - \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_1 - (.I0(p_1_out), - .I1(p_3_out), - .O(SR)); - LUT3 #( - .INIT(8'h28)) - s_out_re - (.I0(srst_d5), - .I1(s_out_d5), - .I2(s_out_d4), - .O(s_out_re__0)); endmodule (* ORIG_REF_NAME = "cdc_sync" *) -module Arty_Z7_20_axi_vdma_0_0_cdc_sync_0 - (p_3_out, - \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_reg , +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized6 + (dmacr_i, + mm2s_axi2ip_wrce, + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] , + prmtr_updt_complete_i_reg, + ioc_irq_reg, + dly_irq_reg, + SR, + s_axi_lite_aclk, + prmry_reset2, m_axi_mm2s_aclk, - m_axis_mm2s_aclk, - s_soft_reset_i_d1, - s_soft_reset_i, - axis_min_assert_sftrst, - \GEN_MIN_FOR_ASYNC.axis_min_count_reg[2] , - p_1_out); - output p_3_out; - output \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_reg ; + D, + p_71_out, + mm2s_prmry_resetn, + stop, + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_reg , + out, + prepare_wrce_d1, + lite_wr_addr_phase_finished_data_phase_started, + wvalid, + mm2s_ioc_irq_set, + ioc_irq_reg_0, + ch1_dly_irq_set, + dly_irq_reg_0); + output [0:0]dmacr_i; + output [8:0]mm2s_axi2ip_wrce; + output [0:0]\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] ; + output prmtr_updt_complete_i_reg; + output ioc_irq_reg; + output dly_irq_reg; + input [0:0]SR; + input s_axi_lite_aclk; + input prmry_reset2; input m_axi_mm2s_aclk; - input m_axis_mm2s_aclk; - input s_soft_reset_i_d1; - input s_soft_reset_i; - input axis_min_assert_sftrst; - input \GEN_MIN_FOR_ASYNC.axis_min_count_reg[2] ; - input p_1_out; + input [10:0]D; + input [0:0]p_71_out; + input mm2s_prmry_resetn; + input stop; + input \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_reg ; + input [5:0]out; + input prepare_wrce_d1; + input lite_wr_addr_phase_finished_data_phase_started; + input wvalid; + input mm2s_ioc_irq_set; + input ioc_irq_reg_0; + input ch1_dly_irq_set; + input dly_irq_reg_0; - wire \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_reg ; - wire \GEN_MIN_FOR_ASYNC.axis_min_count_reg[2] ; - wire axis_min_assert_sftrst; + wire [10:0]D; + wire \ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_2_n_0 ; + wire [0:0]\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] ; + wire \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_reg ; + wire \GEN_NUM_FSTORES_3.reg_module_start_address2_i[31]_i_2_n_0 ; + wire [0:0]SR; + wire ch1_dly_irq_set; + wire dly_irq_reg; + wire dly_irq_reg_0; + wire [0:0]dmacr_i; + wire \dmacr_i[1]_i_2_n_0 ; + wire ioc_irq_reg; + wire ioc_irq_reg_0; + wire lite_wr_addr_phase_finished_data_phase_started; wire m_axi_mm2s_aclk; - wire m_axis_mm2s_aclk; - wire p_1_out; - wire p_3_out; + wire [8:0]mm2s_axi2ip_wrce; + wire mm2s_ioc_irq_set; + wire mm2s_prmry_resetn; + wire [5:0]out; + wire p_0_out; + wire [0:0]p_71_out; wire p_in_d1_cdc_from; + wire prepare_wrce_d1; wire prmry_in_xored; + wire prmry_reset2; + wire prmtr_updt_complete_i_reg; + wire \reg_module_vsize[12]_i_2_n_0 ; + wire s_axi_lite_aclk; wire s_out_d1_cdc_to; wire s_out_d2; wire s_out_d3; wire s_out_d4; wire s_out_d5; wire s_out_re__0; - wire s_soft_reset_i; - wire s_soft_reset_i_d1; wire srst_d1; wire srst_d2; wire srst_d3; wire srst_d4; wire srst_d5; + wire stop; + wire wvalid; + LUT5 #( + .INIT(32'h0100FFFF)) + \ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_1 + (.I0(D[5]), + .I1(D[4]), + .I2(D[3]), + .I3(\ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_2_n_0 ), + .I4(mm2s_prmry_resetn), + .O(\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] )); + LUT6 #( + .INIT(64'h0000000100000000)) + \ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_2 + (.I0(D[6]), + .I1(D[7]), + .I2(D[8]), + .I3(D[9]), + .I4(D[10]), + .I5(mm2s_axi2ip_wrce[0]), + .O(\ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_2_n_0 )); (* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2 - (.C(m_axis_mm2s_aclk), + (.C(m_axi_mm2s_aclk), .CE(1'b1), .D(s_out_d1_cdc_to), .Q(s_out_d2), - .R(1'b0)); + .R(prmry_reset2)); (* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3 - (.C(m_axis_mm2s_aclk), + (.C(m_axi_mm2s_aclk), .CE(1'b1), .D(s_out_d2), .Q(s_out_d3), - .R(1'b0)); + .R(prmry_reset2)); (* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4 - (.C(m_axis_mm2s_aclk), + (.C(m_axi_mm2s_aclk), .CE(1'b1), .D(s_out_d3), .Q(s_out_d4), - .R(1'b0)); + .R(prmry_reset2)); (* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5 - (.C(m_axis_mm2s_aclk), + (.C(m_axi_mm2s_aclk), .CE(1'b1), .D(s_out_d4), .Q(s_out_d5), - .R(1'b0)); + .R(prmry_reset2)); (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out - (.C(m_axis_mm2s_aclk), + (.C(m_axi_mm2s_aclk), .CE(1'b1), .D(s_out_re__0), - .Q(p_3_out), - .R(1'b0)); + .Q(p_0_out), + .R(prmry_reset2)); (* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to - (.C(m_axis_mm2s_aclk), + (.C(m_axi_mm2s_aclk), .CE(1'b1), .D(p_in_d1_cdc_from), .Q(s_out_d1_cdc_to), - .R(1'b0)); + .R(prmry_reset2)); (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from - (.C(m_axi_mm2s_aclk), + (.C(s_axi_lite_aclk), .CE(1'b1), .D(prmry_in_xored), .Q(p_in_d1_cdc_from), - .R(1'b0)); - LUT3 #( - .INIT(8'hB4)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__1 - (.I0(s_soft_reset_i_d1), - .I1(s_soft_reset_i), - .I2(p_in_d1_cdc_from), + .R(SR)); + LUT4 #( + .INIT(16'hBF40)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__7 + (.I0(prepare_wrce_d1), + .I1(lite_wr_addr_phase_finished_data_phase_started), + .I2(wvalid), + .I3(p_in_d1_cdc_from), .O(prmry_in_xored)); (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1 - (.C(m_axis_mm2s_aclk), + (.C(m_axi_mm2s_aclk), .CE(1'b1), .D(1'b1), .Q(srst_d1), - .R(1'b0)); + .R(prmry_reset2)); (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2 - (.C(m_axis_mm2s_aclk), + (.C(m_axi_mm2s_aclk), .CE(1'b1), .D(srst_d1), .Q(srst_d2), - .R(1'b0)); + .R(prmry_reset2)); (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3 - (.C(m_axis_mm2s_aclk), + (.C(m_axi_mm2s_aclk), .CE(1'b1), .D(srst_d2), .Q(srst_d3), - .R(1'b0)); + .R(prmry_reset2)); (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4 - (.C(m_axis_mm2s_aclk), + (.C(m_axi_mm2s_aclk), .CE(1'b1), .D(srst_d3), .Q(srst_d4), - .R(1'b0)); + .R(prmry_reset2)); (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5 - (.C(m_axis_mm2s_aclk), + (.C(m_axi_mm2s_aclk), .CE(1'b1), .D(srst_d4), .Q(srst_d5), - .R(1'b0)); + .R(prmry_reset2)); + (* SOFT_HLUTNM = "soft_lutpair1" *) LUT4 #( - .INIT(16'h00FE)) - \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_1 - (.I0(axis_min_assert_sftrst), - .I1(\GEN_MIN_FOR_ASYNC.axis_min_count_reg[2] ), - .I2(p_3_out), - .I3(p_1_out), - .O(\GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_reg )); + .INIT(16'h0800)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i[31]_i_1 + (.I0(out[0]), + .I1(out[1]), + .I2(out[3]), + .I3(\reg_module_vsize[12]_i_2_n_0 ), + .O(mm2s_axi2ip_wrce[6])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h00020000)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i[31]_i_1 + (.I0(out[3]), + .I1(out[2]), + .I2(out[0]), + .I3(out[1]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address2_i[31]_i_2_n_0 ), + .O(mm2s_axi2ip_wrce[7])); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h40)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i[31]_i_2 + (.I0(out[5]), + .I1(p_0_out), + .I2(out[4]), + .O(\GEN_NUM_FSTORES_3.reg_module_start_address2_i[31]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h00200000)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i[31]_i_1 + (.I0(out[3]), + .I1(out[2]), + .I2(out[0]), + .I3(out[1]), + .I4(\GEN_NUM_FSTORES_3.reg_module_start_address2_i[31]_i_2_n_0 ), + .O(mm2s_axi2ip_wrce[8])); + LUT4 #( + .INIT(16'hF7F0)) + \I_DMA_REGISTER/dly_irq_i_1 + (.I0(D[2]), + .I1(mm2s_axi2ip_wrce[1]), + .I2(ch1_dly_irq_set), + .I3(dly_irq_reg_0), + .O(dly_irq_reg)); + LUT4 #( + .INIT(16'hF7F0)) + \I_DMA_REGISTER/ioc_irq_i_1 + (.I0(D[1]), + .I1(mm2s_axi2ip_wrce[1]), + .I2(mm2s_ioc_irq_set), + .I3(ioc_irq_reg_0), + .O(ioc_irq_reg)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'h0400)) + \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid[15]_i_1 + (.I0(out[0]), + .I1(out[1]), + .I2(out[3]), + .I3(\reg_module_vsize[12]_i_2_n_0 ), + .O(mm2s_axi2ip_wrce[5])); + LUT6 #( + .INIT(64'h0000000000000200)) + dma_interr_i_2 + (.I0(\dmacr_i[1]_i_2_n_0 ), + .I1(out[3]), + .I2(out[1]), + .I3(out[0]), + .I4(out[2]), + .I5(out[4]), + .O(mm2s_axi2ip_wrce[1])); + LUT6 #( + .INIT(64'h000000000000B800)) + \dmacr_i[0]_i_1 + (.I0(D[0]), + .I1(mm2s_axi2ip_wrce[0]), + .I2(p_71_out), + .I3(mm2s_prmry_resetn), + .I4(stop), + .I5(\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_reg ), + .O(dmacr_i)); + LUT6 #( + .INIT(64'h0000000000000002)) + \dmacr_i[1]_i_1 + (.I0(\dmacr_i[1]_i_2_n_0 ), + .I1(out[3]), + .I2(out[1]), + .I3(out[0]), + .I4(out[2]), + .I5(out[4]), + .O(mm2s_axi2ip_wrce[0])); + LUT2 #( + .INIT(4'h2)) + \dmacr_i[1]_i_2 + (.I0(p_0_out), + .I1(out[5]), + .O(\dmacr_i[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'h0100000000000000)) + prmtr_updt_complete_i_i_1 + (.I0(out[0]), + .I1(out[3]), + .I2(out[1]), + .I3(\reg_module_vsize[12]_i_2_n_0 ), + .I4(p_71_out), + .I5(mm2s_prmry_resetn), + .O(prmtr_updt_complete_i_reg)); + LUT6 #( + .INIT(64'h0000000000200000)) + \ptr_ref_i[4]_i_1 + (.I0(out[3]), + .I1(out[4]), + .I2(\dmacr_i[1]_i_2_n_0 ), + .I3(out[0]), + .I4(out[1]), + .I5(out[2]), + .O(mm2s_axi2ip_wrce[2])); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'h0200)) + \reg_module_hsize[15]_i_1 + (.I0(out[0]), + .I1(out[3]), + .I2(out[1]), + .I3(\reg_module_vsize[12]_i_2_n_0 ), + .O(mm2s_axi2ip_wrce[4])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT4 #( + .INIT(16'h0100)) + \reg_module_vsize[12]_i_1 + (.I0(out[0]), + .I1(out[3]), + .I2(out[1]), + .I3(\reg_module_vsize[12]_i_2_n_0 ), + .O(mm2s_axi2ip_wrce[3])); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT4 #( + .INIT(16'h0800)) + \reg_module_vsize[12]_i_2 + (.I0(out[4]), + .I1(p_0_out), + .I2(out[5]), + .I3(out[2]), + .O(\reg_module_vsize[12]_i_2_n_0 )); LUT3 #( .INIT(8'h28)) s_out_re @@ -23389,28 +62256,142 @@ module Arty_Z7_20_axi_vdma_0_0_cdc_sync_0 endmodule (* ORIG_REF_NAME = "cdc_sync" *) -module Arty_Z7_20_axi_vdma_0_0_cdc_sync_1 - (p_in_d1_cdc_from, - p_4_out, +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized7 + (p_15_out, + \dmacr_i_reg[1] , + p_14_out, + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] , + prmtr_updt_complete_i_reg, + dma_interr_reg, + dma_interr_reg_0, + \GEN_FOR_FLUSH.fsize_err_reg , + lsize_err_reg, + \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg , + ioc_irq_reg, + dly_irq_reg, + lsize_more_err_reg, + s2mm_axi2ip_wrce, SR, - prmry_in_xored, - m_axi_mm2s_aclk, s_axi_lite_aclk, - p_6_out); - output p_in_d1_cdc_from; - output p_4_out; - output [0:0]SR; - input prmry_in_xored; - input m_axi_mm2s_aclk; + prmry_reset2_0, + m_axi_s2mm_aclk, + s2mm_dmacr, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] , + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31] , + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[23] , + s2mm_prmry_resetn, + out, + prepare_wrce_d1, + lite_wr_addr_phase_finished_data_phase_started, + wvalid, + s2mm_dma_interr_set_minus_frame_errors, + s2mm_fsize_more_or_sof_late, + fsize_mismatch_err, + dma_interr_reg_1, + \GEN_FOR_FLUSH.fsize_err_reg_0 , + lsize_mismatch_err, + lsize_err_reg_0, + \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg_0 , + s2mm_ioc_irq_set, + ioc_irq_reg_0, + ch2_dly_irq_set, + dly_irq_reg_0, + lsize_more_mismatch_err, + lsize_more_err_reg_0); + output p_15_out; + output \dmacr_i_reg[1] ; + output p_14_out; + output [0:0]\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] ; + output prmtr_updt_complete_i_reg; + output dma_interr_reg; + output dma_interr_reg_0; + output \GEN_FOR_FLUSH.fsize_err_reg ; + output lsize_err_reg; + output \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg ; + output ioc_irq_reg; + output dly_irq_reg; + output lsize_more_err_reg; + output [7:0]s2mm_axi2ip_wrce; + input [0:0]SR; input s_axi_lite_aclk; - input p_6_out; + input prmry_reset2_0; + input m_axi_s2mm_aclk; + input [12:0]s2mm_dmacr; + input [20:0]\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] ; + input \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31] ; + input \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[23] ; + input s2mm_prmry_resetn; + input [5:0]out; + input prepare_wrce_d1; + input lite_wr_addr_phase_finished_data_phase_started; + input wvalid; + input s2mm_dma_interr_set_minus_frame_errors; + input s2mm_fsize_more_or_sof_late; + input fsize_mismatch_err; + input dma_interr_reg_1; + input \GEN_FOR_FLUSH.fsize_err_reg_0 ; + input lsize_mismatch_err; + input lsize_err_reg_0; + input \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg_0 ; + input s2mm_ioc_irq_set; + input ioc_irq_reg_0; + input ch2_dly_irq_set; + input dly_irq_reg_0; + input lsize_more_mismatch_err; + input lsize_more_err_reg_0; + wire \DMA_IRQ_MASK_GEN.dma_irq_mask_i[3]_i_2_n_0 ; + wire \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31] ; + wire \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_2__0_n_0 ; + wire \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_3__0_n_0 ; + wire \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_4__0_n_0 ; + wire \ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_2__0_n_0 ; + wire [0:0]\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] ; + wire \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[23] ; + wire \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_2__0_n_0 ; + wire \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_3__0_n_0 ; + wire \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_4__0_n_0 ; + wire \GEN_FOR_FLUSH.fsize_err_reg ; + wire \GEN_FOR_FLUSH.fsize_err_reg_0 ; + wire \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg ; + wire \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg_0 ; + wire [20:0]\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] ; wire [0:0]SR; - wire m_axi_mm2s_aclk; - wire p_4_out; - wire p_6_out; + wire ch2_dly_irq_set; + wire dly_irq_reg; + wire dly_irq_reg_0; + wire dma_interr_reg; + wire dma_interr_reg_0; + wire dma_interr_reg_1; + wire \dmacr_i[1]_i_2__0_n_0 ; + wire \dmacr_i_reg[1] ; + wire fsize_mismatch_err; + wire ioc_irq_reg; + wire ioc_irq_reg_0; + wire lite_wr_addr_phase_finished_data_phase_started; + wire lsize_err_reg; + wire lsize_err_reg_0; + wire lsize_mismatch_err; + wire lsize_more_err_reg; + wire lsize_more_err_reg_0; + wire lsize_more_mismatch_err; + wire m_axi_s2mm_aclk; + wire [5:0]out; + wire p_14_out; + wire p_15_out; + wire p_1_out; wire p_in_d1_cdc_from; + wire prepare_wrce_d1; wire prmry_in_xored; + wire prmry_reset2_0; + wire prmtr_updt_complete_i_reg; + wire \reg_module_vsize[12]_i_2__0_n_0 ; + wire [7:0]s2mm_axi2ip_wrce; + wire s2mm_dma_interr_set_minus_frame_errors; + wire [12:0]s2mm_dmacr; + wire s2mm_fsize_more_or_sof_late; + wire s2mm_ioc_irq_set; + wire s2mm_prmry_resetn; wire s_axi_lite_aclk; wire s_out_d1_cdc_to; wire s_out_d2; @@ -23423,138 +62404,417 @@ module Arty_Z7_20_axi_vdma_0_0_cdc_sync_1 wire srst_d3; wire srst_d4; wire srst_d5; + wire wvalid; + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT4 #( + .INIT(16'h0800)) + \DMA_IRQ_MASK_GEN.dma_irq_mask_i[3]_i_1 + (.I0(out[0]), + .I1(out[2]), + .I2(out[5]), + .I3(\DMA_IRQ_MASK_GEN.dma_irq_mask_i[3]_i_2_n_0 ), + .O(s2mm_axi2ip_wrce[1])); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h4000)) + \DMA_IRQ_MASK_GEN.dma_irq_mask_i[3]_i_2 + (.I0(out[4]), + .I1(p_1_out), + .I2(out[3]), + .I3(out[1]), + .O(\DMA_IRQ_MASK_GEN.dma_irq_mask_i[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT4 #( + .INIT(16'h0400)) + \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid[15]_i_1 + (.I0(out[0]), + .I1(out[5]), + .I2(out[2]), + .I3(\DMA_IRQ_MASK_GEN.dma_irq_mask_i[3]_i_2_n_0 ), + .O(s2mm_axi2ip_wrce[4])); + LUT6 #( + .INIT(64'hF6FFFFF6F0F0F0F0)) + \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_1__0 + (.I0(s2mm_dmacr[7]), + .I1(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] [15]), + .I2(\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_2__0_n_0 ), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] [16]), + .I4(s2mm_dmacr[8]), + .I5(\dmacr_i_reg[1] ), + .O(p_15_out)); + LUT6 #( + .INIT(64'hFEFFFEFEFEFEFEFE)) + \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_2__0 + (.I0(\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_3__0_n_0 ), + .I1(\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_4__0_n_0 ), + .I2(\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31] ), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] [18]), + .I4(s2mm_dmacr[10]), + .I5(\dmacr_i_reg[1] ), + .O(\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_2__0_n_0 )); + LUT5 #( + .INIT(32'h40F0F040)) + \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_3__0 + (.I0(s2mm_dmacr[10]), + .I1(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] [18]), + .I2(\dmacr_i_reg[1] ), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] [17]), + .I4(s2mm_dmacr[9]), + .O(\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_3__0_n_0 )); + LUT5 #( + .INIT(32'h40F0F040)) + \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_4__0 + (.I0(s2mm_dmacr[12]), + .I1(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] [20]), + .I2(\dmacr_i_reg[1] ), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] [19]), + .I4(s2mm_dmacr[11]), + .O(\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_4__0_n_0 )); + LUT5 #( + .INIT(32'h0002FFFF)) + \ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_1__0 + (.I0(\ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_2__0_n_0 ), + .I1(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] [9]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] [8]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] [7]), + .I4(s2mm_prmry_resetn), + .O(\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] )); + LUT6 #( + .INIT(64'h0000000100000000)) + \ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_2__0 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] [12]), + .I1(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] [13]), + .I2(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] [10]), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] [11]), + .I4(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] [14]), + .I5(\dmacr_i_reg[1] ), + .O(\ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hF6FFFFF6F0F0F0F0)) + \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_1__0 + (.I0(s2mm_dmacr[1]), + .I1(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] [7]), + .I2(\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_2__0_n_0 ), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] [8]), + .I4(s2mm_dmacr[2]), + .I5(\dmacr_i_reg[1] ), + .O(p_14_out)); + LUT6 #( + .INIT(64'hFEFFFEFEFEFEFEFE)) + \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_2__0 + (.I0(\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_3__0_n_0 ), + .I1(\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_4__0_n_0 ), + .I2(\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[23] ), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] [10]), + .I4(s2mm_dmacr[4]), + .I5(\dmacr_i_reg[1] ), + .O(\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_2__0_n_0 )); + LUT5 #( + .INIT(32'h40F0F040)) + \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_3__0 + (.I0(s2mm_dmacr[4]), + .I1(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] [10]), + .I2(\dmacr_i_reg[1] ), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] [9]), + .I4(s2mm_dmacr[3]), + .O(\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_3__0_n_0 )); + LUT5 #( + .INIT(32'h40F0F040)) + \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_4__0 + (.I0(s2mm_dmacr[6]), + .I1(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] [12]), + .I2(\dmacr_i_reg[1] ), + .I3(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] [11]), + .I4(s2mm_dmacr[5]), + .O(\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_4__0_n_0 )); (* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2 - (.C(s_axi_lite_aclk), + (.C(m_axi_s2mm_aclk), .CE(1'b1), .D(s_out_d1_cdc_to), .Q(s_out_d2), - .R(1'b0)); + .R(prmry_reset2_0)); (* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3 - (.C(s_axi_lite_aclk), + (.C(m_axi_s2mm_aclk), .CE(1'b1), .D(s_out_d2), .Q(s_out_d3), - .R(1'b0)); + .R(prmry_reset2_0)); (* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4 - (.C(s_axi_lite_aclk), + (.C(m_axi_s2mm_aclk), .CE(1'b1), .D(s_out_d3), .Q(s_out_d4), - .R(1'b0)); + .R(prmry_reset2_0)); (* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5 - (.C(s_axi_lite_aclk), + (.C(m_axi_s2mm_aclk), .CE(1'b1), .D(s_out_d4), .Q(s_out_d5), - .R(1'b0)); + .R(prmry_reset2_0)); (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out - (.C(s_axi_lite_aclk), + (.C(m_axi_s2mm_aclk), .CE(1'b1), .D(s_out_re__0), - .Q(p_4_out), - .R(1'b0)); + .Q(p_1_out), + .R(prmry_reset2_0)); (* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to - (.C(s_axi_lite_aclk), + (.C(m_axi_s2mm_aclk), .CE(1'b1), .D(p_in_d1_cdc_from), .Q(s_out_d1_cdc_to), - .R(1'b0)); + .R(prmry_reset2_0)); (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from - (.C(m_axi_mm2s_aclk), + (.C(s_axi_lite_aclk), .CE(1'b1), .D(prmry_in_xored), .Q(p_in_d1_cdc_from), - .R(1'b0)); + .R(SR)); + LUT4 #( + .INIT(16'hBF40)) + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__8 + (.I0(prepare_wrce_d1), + .I1(lite_wr_addr_phase_finished_data_phase_started), + .I2(wvalid), + .I3(p_in_d1_cdc_from), + .O(prmry_in_xored)); (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1 - (.C(s_axi_lite_aclk), + (.C(m_axi_s2mm_aclk), .CE(1'b1), .D(1'b1), .Q(srst_d1), - .R(1'b0)); + .R(prmry_reset2_0)); (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2 - (.C(s_axi_lite_aclk), + (.C(m_axi_s2mm_aclk), .CE(1'b1), .D(srst_d1), .Q(srst_d2), - .R(1'b0)); + .R(prmry_reset2_0)); (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3 - (.C(s_axi_lite_aclk), + (.C(m_axi_s2mm_aclk), .CE(1'b1), .D(srst_d2), .Q(srst_d3), - .R(1'b0)); + .R(prmry_reset2_0)); (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4 - (.C(s_axi_lite_aclk), + (.C(m_axi_s2mm_aclk), .CE(1'b1), .D(srst_d3), .Q(srst_d4), - .R(1'b0)); + .R(prmry_reset2_0)); (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5 - (.C(s_axi_lite_aclk), + (.C(m_axi_s2mm_aclk), .CE(1'b1), .D(srst_d4), .Q(srst_d5), - .R(1'b0)); - LUT2 #( - .INIT(4'hE)) - \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_1 - (.I0(p_4_out), - .I1(p_6_out), - .O(SR)); + .R(prmry_reset2_0)); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT4 #( + .INIT(16'h0800)) + \GEN_NUM_FSTORES_3.reg_module_start_address1_i[31]_i_1__0 + (.I0(out[0]), + .I1(out[5]), + .I2(out[2]), + .I3(\DMA_IRQ_MASK_GEN.dma_irq_mask_i[3]_i_2_n_0 ), + .O(s2mm_axi2ip_wrce[5])); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT3 #( + .INIT(8'h40)) + \GEN_NUM_FSTORES_3.reg_module_start_address2_i[31]_i_1__0 + (.I0(out[0]), + .I1(out[5]), + .I2(\dmacr_i[1]_i_2__0_n_0 ), + .O(s2mm_axi2ip_wrce[6])); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT3 #( + .INIT(8'h80)) + \GEN_NUM_FSTORES_3.reg_module_start_address3_i[31]_i_1__0 + (.I0(out[5]), + .I1(out[0]), + .I2(\dmacr_i[1]_i_2__0_n_0 ), + .O(s2mm_axi2ip_wrce[7])); + LUT4 #( + .INIT(16'hF7F0)) + \I_DMA_REGISTER/GEN_FOR_FLUSH.fsize_err_i_1 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] [1]), + .I1(dma_interr_reg_0), + .I2(fsize_mismatch_err), + .I3(\GEN_FOR_FLUSH.fsize_err_reg_0 ), + .O(\GEN_FOR_FLUSH.fsize_err_reg )); + LUT4 #( + .INIT(16'hF7F0)) + \I_DMA_REGISTER/GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_i_1 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] [3]), + .I1(dma_interr_reg_0), + .I2(s2mm_fsize_more_or_sof_late), + .I3(\GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg_0 ), + .O(\GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg )); + LUT4 #( + .INIT(16'hF7F0)) + \I_DMA_REGISTER/dly_irq_i_1__0 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] [5]), + .I1(dma_interr_reg_0), + .I2(ch2_dly_irq_set), + .I3(dly_irq_reg_0), + .O(dly_irq_reg)); + LUT6 #( + .INIT(64'hFFFFFFF7FFFFFFF0)) + \I_DMA_REGISTER/dma_interr_i_1__0 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] [0]), + .I1(dma_interr_reg_0), + .I2(s2mm_dma_interr_set_minus_frame_errors), + .I3(s2mm_fsize_more_or_sof_late), + .I4(fsize_mismatch_err), + .I5(dma_interr_reg_1), + .O(dma_interr_reg)); + LUT4 #( + .INIT(16'hF7F0)) + \I_DMA_REGISTER/ioc_irq_i_1__0 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] [4]), + .I1(dma_interr_reg_0), + .I2(s2mm_ioc_irq_set), + .I3(ioc_irq_reg_0), + .O(ioc_irq_reg)); + LUT4 #( + .INIT(16'hF7F0)) + \I_DMA_REGISTER/lsize_err_i_1 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] [2]), + .I1(dma_interr_reg_0), + .I2(lsize_mismatch_err), + .I3(lsize_err_reg_0), + .O(lsize_err_reg)); + LUT4 #( + .INIT(16'hF7F0)) + \I_DMA_REGISTER/lsize_more_err_i_1 + (.I0(\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29] [6]), + .I1(dma_interr_reg_0), + .I2(lsize_more_mismatch_err), + .I3(lsize_more_err_reg_0), + .O(lsize_more_err_reg)); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT3 #( + .INIT(8'h40)) + dma_interr_i_2__0 + (.I0(out[5]), + .I1(out[0]), + .I2(\dmacr_i[1]_i_2__0_n_0 ), + .O(dma_interr_reg_0)); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT3 #( + .INIT(8'h10)) + \dmacr_i[1]_i_1__0 + (.I0(out[5]), + .I1(out[0]), + .I2(\dmacr_i[1]_i_2__0_n_0 ), + .O(\dmacr_i_reg[1] )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT5 #( + .INIT(32'h00400000)) + \dmacr_i[1]_i_2__0 + (.I0(out[1]), + .I1(out[3]), + .I2(p_1_out), + .I3(out[4]), + .I4(out[2]), + .O(\dmacr_i[1]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'h0400000000000000)) + prmtr_updt_complete_i_i_1__0 + (.I0(out[0]), + .I1(out[5]), + .I2(out[2]), + .I3(\reg_module_vsize[12]_i_2__0_n_0 ), + .I4(s2mm_prmry_resetn), + .I5(s2mm_dmacr[0]), + .O(prmtr_updt_complete_i_reg)); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT4 #( + .INIT(16'h0100)) + \ptr_ref_i[4]_i_1__0 + (.I0(out[0]), + .I1(out[2]), + .I2(out[5]), + .I3(\DMA_IRQ_MASK_GEN.dma_irq_mask_i[3]_i_2_n_0 ), + .O(s2mm_axi2ip_wrce[0])); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT4 #( + .INIT(16'h0800)) + \reg_module_hsize[15]_i_1__0 + (.I0(out[0]), + .I1(out[5]), + .I2(out[2]), + .I3(\reg_module_vsize[12]_i_2__0_n_0 ), + .O(s2mm_axi2ip_wrce[3])); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT4 #( + .INIT(16'h0400)) + \reg_module_vsize[12]_i_1__0 + (.I0(out[0]), + .I1(out[5]), + .I2(out[2]), + .I3(\reg_module_vsize[12]_i_2__0_n_0 ), + .O(s2mm_axi2ip_wrce[2])); + LUT4 #( + .INIT(16'h0040)) + \reg_module_vsize[12]_i_2__0 + (.I0(out[4]), + .I1(p_1_out), + .I2(out[3]), + .I3(out[1]), + .O(\reg_module_vsize[12]_i_2__0_n_0 )); LUT3 #( .INIT(8'h28)) s_out_re @@ -23565,3262 +62825,6203 @@ module Arty_Z7_20_axi_vdma_0_0_cdc_sync_1 endmodule (* ORIG_REF_NAME = "cdc_sync" *) -module Arty_Z7_20_axi_vdma_0_0_cdc_sync_2 - (p_6_out, - \GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_reg , - m_axi_mm2s_aclk, +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized8 + (mm2s_introut, + SR, s_axi_lite_aclk, - s_soft_reset_i_d1, - s_soft_reset_i, - lite_min_assert_sftrst, - p_8_out_0, - p_4_out); - output p_6_out; - output \GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_reg ; - input m_axi_mm2s_aclk; + prmry_reset2, + p_78_out, + m_axi_mm2s_aclk); + output mm2s_introut; + input [0:0]SR; input s_axi_lite_aclk; - input s_soft_reset_i_d1; - input s_soft_reset_i; - input lite_min_assert_sftrst; - input p_8_out_0; - input p_4_out; - - wire \GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_reg ; - wire lite_min_assert_sftrst; - wire m_axi_mm2s_aclk; - wire p_4_out; - wire p_6_out; - wire p_8_out_0; - wire p_in_d1_cdc_from; - wire prmry_in_xored; - wire s_axi_lite_aclk; - wire s_out_d1_cdc_to; - wire s_out_d2; - wire s_out_d3; - wire s_out_d4; - wire s_out_d5; - wire s_out_re__0; - wire s_soft_reset_i; - wire s_soft_reset_i_d1; - wire srst_d1; - wire srst_d2; - wire srst_d3; - wire srst_d4; - wire srst_d5; + input prmry_reset2; + input p_78_out; + input m_axi_mm2s_aclk; + + wire [0:0]SR; + wire m_axi_mm2s_aclk; + wire mm2s_introut; + wire p_78_out; + wire p_level_in_d1_cdc_from; + wire prmry_reset2; + wire s_axi_lite_aclk; + wire s_level_out_d1_cdc_to; + wire s_level_out_d2; (* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2 - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_out_d1_cdc_to), - .Q(s_out_d2), - .R(1'b0)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3 - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_out_d2), - .Q(s_out_d3), - .R(1'b0)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4 + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to (.C(s_axi_lite_aclk), .CE(1'b1), - .D(s_out_d3), - .Q(s_out_d4), - .R(1'b0)); + .D(p_level_in_d1_cdc_from), + .Q(s_level_out_d1_cdc_to), + .R(SR)); (* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5 - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_out_d4), - .Q(s_out_d5), - .R(1'b0)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 (.C(s_axi_lite_aclk), .CE(1'b1), - .D(s_out_re__0), - .Q(p_6_out), - .R(1'b0)); + .D(s_level_out_d1_cdc_to), + .Q(s_level_out_d2), + .R(SR)); (* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 (.C(s_axi_lite_aclk), .CE(1'b1), - .D(p_in_d1_cdc_from), - .Q(s_out_d1_cdc_to), - .R(1'b0)); + .D(s_level_out_d2), + .Q(mm2s_introut), + .R(SR)); (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(prmry_in_xored), - .Q(p_in_d1_cdc_from), - .R(1'b0)); - LUT3 #( - .INIT(8'hB4)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1 - (.I0(s_soft_reset_i_d1), - .I1(s_soft_reset_i), - .I2(p_in_d1_cdc_from), - .O(prmry_in_xored)); + .D(p_78_out), + .Q(p_level_in_d1_cdc_from), + .R(prmry_reset2)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized9 + (s2mm_introut, + SR, + s_axi_lite_aclk, + prmry_reset2_0, + s2mm_ip2axi_introut, + m_axi_s2mm_aclk); + output s2mm_introut; + input [0:0]SR; + input s_axi_lite_aclk; + input prmry_reset2_0; + input s2mm_ip2axi_introut; + input m_axi_s2mm_aclk; + + wire [0:0]SR; + wire m_axi_s2mm_aclk; + wire p_level_in_d1_cdc_from; + wire prmry_reset2_0; + wire s2mm_introut; + wire s2mm_ip2axi_introut; + wire s_axi_lite_aclk; + wire s_level_out_d1_cdc_to; + wire s_level_out_d2; + + (* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1 + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to (.C(s_axi_lite_aclk), .CE(1'b1), - .D(1'b1), - .Q(srst_d1), - .R(1'b0)); + .D(p_level_in_d1_cdc_from), + .Q(s_level_out_d1_cdc_to), + .R(SR)); + (* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2 + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 (.C(s_axi_lite_aclk), .CE(1'b1), - .D(srst_d1), - .Q(srst_d2), - .R(1'b0)); + .D(s_level_out_d1_cdc_to), + .Q(s_level_out_d2), + .R(SR)); + (* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3 + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 (.C(s_axi_lite_aclk), .CE(1'b1), - .D(srst_d2), - .Q(srst_d3), - .R(1'b0)); + .D(s_level_out_d2), + .Q(s2mm_introut), + .R(SR)); (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4 - (.C(s_axi_lite_aclk), + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(srst_d3), - .Q(srst_d4), - .R(1'b0)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5 - (.C(s_axi_lite_aclk), + .D(s2mm_ip2axi_introut), + .Q(p_level_in_d1_cdc_from), + .R(prmry_reset2_0)); +endmodule + +(* ORIG_REF_NAME = "cntr_incr_decr_addn_f" *) +module Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f + (sig_ld_new_cmd_reg_reg, + sig_dqual_reg_empty_reg, + sig_next_calc_error_reg_reg, + sig_dqual_reg_empty_reg_0, + D, + fifo_full_p1, + FIFO_Full_reg, + E, + sig_dqual_reg_empty_reg_1, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_ld_new_cmd_reg, + sig_next_calc_error_reg, + \sig_dbeat_cntr_reg[1] , + sig_dqual_reg_full_reg, + Q, + \sig_dbeat_cntr_reg[4] , + sig_wr_fifo, + p_11_out, + FIFO_Full_reg_0, + sig_inhibit_rdy_n_reg, + sig_next_sequential_reg, + sig_last_dbeat_reg, + sig_dqual_reg_empty, + sig_halt_reg, + sig_m_valid_out_reg, + sig_s_ready_out_reg, + sig_wdc_status_going_full, + sig_inhibit_rdy_n_reg_0, + sig_wsc2stat_status_valid, + sig_addr_posted_cntr, + sig_halt_reg_dly3, + sig_last_mmap_dbeat_reg, + sig_posted_to_axi_reg, + sig_stream_rst, + m_axi_s2mm_aclk); + output sig_ld_new_cmd_reg_reg; + output sig_dqual_reg_empty_reg; + output sig_next_calc_error_reg_reg; + output sig_dqual_reg_empty_reg_0; + output [1:0]D; + output fifo_full_p1; + output [1:0]FIFO_Full_reg; + output [0:0]E; + output sig_dqual_reg_empty_reg_1; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_ld_new_cmd_reg; + input sig_next_calc_error_reg; + input \sig_dbeat_cntr_reg[1] ; + input sig_dqual_reg_full_reg; + input [1:0]Q; + input \sig_dbeat_cntr_reg[4] ; + input sig_wr_fifo; + input p_11_out; + input FIFO_Full_reg_0; + input sig_inhibit_rdy_n_reg; + input sig_next_sequential_reg; + input sig_last_dbeat_reg; + input sig_dqual_reg_empty; + input sig_halt_reg; + input sig_m_valid_out_reg; + input sig_s_ready_out_reg; + input sig_wdc_status_going_full; + input sig_inhibit_rdy_n_reg_0; + input sig_wsc2stat_status_valid; + input [2:0]sig_addr_posted_cntr; + input sig_halt_reg_dly3; + input sig_last_mmap_dbeat_reg; + input sig_posted_to_axi_reg; + input sig_stream_rst; + input m_axi_s2mm_aclk; + + wire [1:0]D; + wire [0:0]E; + wire [1:0]FIFO_Full_reg; + wire FIFO_Full_reg_0; + wire [1:0]Q; + wire [2:0]addr_i_p1; + wire fifo_full_p1; + wire m_axi_s2mm_aclk; + wire p_11_out; + wire [2:0]sig_addr_posted_cntr; + wire sig_addr_posted_cntr_max__1; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire \sig_dbeat_cntr_reg[1] ; + wire \sig_dbeat_cntr_reg[4] ; + wire sig_dqual_reg_empty; + wire sig_dqual_reg_empty_reg; + wire sig_dqual_reg_empty_reg_0; + wire sig_dqual_reg_empty_reg_1; + wire sig_dqual_reg_full_reg; + wire sig_halt_reg; + wire sig_halt_reg_dly3; + wire sig_inhibit_rdy_n_reg; + wire sig_inhibit_rdy_n_reg_0; + wire sig_last_dbeat_reg; + wire sig_last_mmap_dbeat_reg; + wire sig_ld_new_cmd_reg; + wire sig_ld_new_cmd_reg_reg; + wire sig_m_valid_out_reg; + wire sig_next_calc_error_reg; + wire sig_next_calc_error_reg_i_4_n_0; + wire sig_next_calc_error_reg_i_8_n_0; + wire sig_next_calc_error_reg_reg; + wire sig_next_sequential_reg; + wire sig_posted_to_axi_reg; + wire sig_rd_empty; + wire sig_s_ready_out_reg; + wire sig_stream_rst; + wire sig_wdc_status_going_full; + wire sig_wr_fifo; + wire sig_wsc2stat_status_valid; + + (* SOFT_HLUTNM = "soft_lutpair240" *) + LUT5 #( + .INIT(32'h41100000)) + FIFO_Full_i_1__8 + (.I0(sig_rd_empty), + .I1(sig_dqual_reg_empty_reg), + .I2(sig_wr_fifo), + .I3(FIFO_Full_reg[0]), + .I4(FIFO_Full_reg[1]), + .O(fifo_full_p1)); + LUT6 #( + .INIT(64'hBB4BBBBB44B44444)) + \INFERRED_GEN.cnt_i[0]_i_1__8 + (.I0(sig_rd_empty), + .I1(sig_dqual_reg_empty_reg), + .I2(p_11_out), + .I3(FIFO_Full_reg_0), + .I4(sig_inhibit_rdy_n_reg), + .I5(FIFO_Full_reg[0]), + .O(addr_i_p1[0])); + (* SOFT_HLUTNM = "soft_lutpair240" *) + LUT5 #( + .INIT(32'h77E78818)) + \INFERRED_GEN.cnt_i[1]_i_1__8 + (.I0(FIFO_Full_reg[0]), + .I1(sig_wr_fifo), + .I2(sig_dqual_reg_empty_reg), + .I3(sig_rd_empty), + .I4(FIFO_Full_reg[1]), + .O(addr_i_p1[1])); + LUT5 #( + .INIT(32'h7F7F0180)) + \INFERRED_GEN.cnt_i[2]_i_1__8 + (.I0(sig_wr_fifo), + .I1(FIFO_Full_reg[0]), + .I2(FIFO_Full_reg[1]), + .I3(sig_dqual_reg_empty_reg), + .I4(sig_rd_empty), + .O(addr_i_p1[2])); + FDSE \INFERRED_GEN.cnt_i_reg[0] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(srst_d4), - .Q(srst_d5), - .R(1'b0)); + .D(addr_i_p1[0]), + .Q(FIFO_Full_reg[0]), + .S(sig_stream_rst)); + FDSE \INFERRED_GEN.cnt_i_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(addr_i_p1[1]), + .Q(FIFO_Full_reg[1]), + .S(sig_stream_rst)); + FDSE \INFERRED_GEN.cnt_i_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(addr_i_p1[2]), + .Q(sig_rd_empty), + .S(sig_stream_rst)); + (* SOFT_HLUTNM = "soft_lutpair241" *) + LUT3 #( + .INIT(8'h41)) + \sig_dbeat_cntr[6]_i_1__0 + (.I0(sig_dqual_reg_empty_reg), + .I1(Q[0]), + .I2(\sig_dbeat_cntr_reg[4] ), + .O(D[0])); + (* SOFT_HLUTNM = "soft_lutpair242" *) + LUT3 #( + .INIT(8'hBA)) + \sig_dbeat_cntr[7]_i_1__0 + (.I0(sig_dqual_reg_empty_reg), + .I1(\sig_dbeat_cntr_reg[1] ), + .I2(sig_dqual_reg_empty_reg_0), + .O(E)); + (* SOFT_HLUTNM = "soft_lutpair241" *) LUT4 #( - .INIT(16'h00FE)) - \GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_i_1 - (.I0(lite_min_assert_sftrst), - .I1(p_8_out_0), - .I2(p_6_out), - .I3(p_4_out), - .O(\GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_reg )); + .INIT(16'h4441)) + \sig_dbeat_cntr[7]_i_2__0 + (.I0(sig_dqual_reg_empty_reg), + .I1(Q[1]), + .I2(\sig_dbeat_cntr_reg[4] ), + .I3(Q[0]), + .O(D[1])); + (* SOFT_HLUTNM = "soft_lutpair242" *) LUT3 #( - .INIT(8'h28)) - s_out_re - (.I0(srst_d5), - .I1(s_out_d5), - .I2(s_out_d4), - .O(s_out_re__0)); + .INIT(8'h08)) + sig_ld_new_cmd_reg_i_1 + (.I0(sig_dqual_reg_empty_reg), + .I1(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I2(sig_ld_new_cmd_reg), + .O(sig_ld_new_cmd_reg_reg)); + LUT6 #( + .INIT(64'h10000000FFFFFFFF)) + sig_next_calc_error_reg_i_1 + (.I0(sig_dqual_reg_empty_reg), + .I1(sig_next_calc_error_reg), + .I2(sig_dqual_reg_empty_reg_0), + .I3(\sig_dbeat_cntr_reg[1] ), + .I4(sig_dqual_reg_full_reg), + .I5(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .O(sig_next_calc_error_reg_reg)); + LUT5 #( + .INIT(32'hAAAA8000)) + sig_next_calc_error_reg_i_2 + (.I0(sig_next_calc_error_reg_i_4_n_0), + .I1(sig_next_sequential_reg), + .I2(sig_last_dbeat_reg), + .I3(sig_dqual_reg_empty_reg_0), + .I4(sig_dqual_reg_empty), + .O(sig_dqual_reg_empty_reg)); + LUT6 #( + .INIT(64'h4440000000000000)) + sig_next_calc_error_reg_i_3 + (.I0(sig_next_calc_error_reg), + .I1(sig_dqual_reg_full_reg), + .I2(sig_halt_reg), + .I3(sig_m_valid_out_reg), + .I4(sig_dqual_reg_empty_reg_1), + .I5(sig_s_ready_out_reg), + .O(sig_dqual_reg_empty_reg_0)); + LUT6 #( + .INIT(64'h0000000000001011)) + sig_next_calc_error_reg_i_4 + (.I0(sig_addr_posted_cntr_max__1), + .I1(sig_wdc_status_going_full), + .I2(sig_inhibit_rdy_n_reg_0), + .I3(sig_wsc2stat_status_valid), + .I4(sig_rd_empty), + .I5(sig_next_calc_error_reg), + .O(sig_next_calc_error_reg_i_4_n_0)); + LUT6 #( + .INIT(64'h00FEFEFE00000000)) + sig_next_calc_error_reg_i_5 + (.I0(sig_addr_posted_cntr[1]), + .I1(sig_addr_posted_cntr[0]), + .I2(sig_addr_posted_cntr[2]), + .I3(sig_halt_reg_dly3), + .I4(sig_next_calc_error_reg), + .I5(sig_next_calc_error_reg_i_8_n_0), + .O(sig_dqual_reg_empty_reg_1)); + LUT3 #( + .INIT(8'h80)) + sig_next_calc_error_reg_i_6 + (.I0(sig_addr_posted_cntr[1]), + .I1(sig_addr_posted_cntr[0]), + .I2(sig_addr_posted_cntr[2]), + .O(sig_addr_posted_cntr_max__1)); + LUT6 #( + .INIT(64'h55555555FFFFFDFF)) + sig_next_calc_error_reg_i_8 + (.I0(sig_last_mmap_dbeat_reg), + .I1(sig_addr_posted_cntr[1]), + .I2(sig_addr_posted_cntr[2]), + .I3(sig_addr_posted_cntr[0]), + .I4(sig_posted_to_axi_reg), + .I5(sig_halt_reg), + .O(sig_next_calc_error_reg_i_8_n_0)); endmodule -(* ORIG_REF_NAME = "cdc_sync" *) -module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized0 - (scndry_out, - s_axi_lite_aclk, - \FSM_sequential_dmacntrl_cs_reg[1] , - m_axi_mm2s_aclk); - output scndry_out; - input s_axi_lite_aclk; - input \FSM_sequential_dmacntrl_cs_reg[1] ; - input m_axi_mm2s_aclk; +(* ORIG_REF_NAME = "cntr_incr_decr_addn_f" *) +module Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_16 + (fifo_full_p1, + Q, + sig_input_reg_empty, + sig_psm_halt, + sig_wr_fifo, + sig_stream_rst, + m_axi_s2mm_aclk); + output fifo_full_p1; + output [2:0]Q; + input sig_input_reg_empty; + input sig_psm_halt; + input sig_wr_fifo; + input sig_stream_rst; + input m_axi_s2mm_aclk; - wire \FSM_sequential_dmacntrl_cs_reg[1] ; - wire m_axi_mm2s_aclk; - wire p_level_in_d1_cdc_from; - wire s_axi_lite_aclk; - wire s_level_out_d1_cdc_to; - wire s_level_out_d2; - wire s_level_out_d3; - wire scndry_out; + wire [2:0]Q; + wire [2:0]addr_i_p1; + wire fifo_full_p1; + wire m_axi_s2mm_aclk; + wire sig_input_reg_empty; + wire sig_psm_halt; + wire sig_stream_rst; + wire sig_wr_fifo; - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to - (.C(s_axi_lite_aclk), + LUT6 #( + .INIT(64'h0451510000000000)) + FIFO_Full_i_1__4 + (.I0(Q[2]), + .I1(sig_input_reg_empty), + .I2(sig_psm_halt), + .I3(sig_wr_fifo), + .I4(Q[0]), + .I5(Q[1]), + .O(fifo_full_p1)); + LUT5 #( + .INIT(32'h04FBFB04)) + \INFERRED_GEN.cnt_i[0]_i_1__4 + (.I0(Q[2]), + .I1(sig_input_reg_empty), + .I2(sig_psm_halt), + .I3(sig_wr_fifo), + .I4(Q[0]), + .O(addr_i_p1[0])); + LUT6 #( + .INIT(64'h77777E7788888188)) + \INFERRED_GEN.cnt_i[1]_i_1__4 + (.I0(Q[0]), + .I1(sig_wr_fifo), + .I2(sig_psm_halt), + .I3(sig_input_reg_empty), + .I4(Q[2]), + .I5(Q[1]), + .O(addr_i_p1[1])); + LUT6 #( + .INIT(64'h7F7F7F7F80018080)) + \INFERRED_GEN.cnt_i[2]_i_1__4 + (.I0(sig_wr_fifo), + .I1(Q[0]), + .I2(Q[1]), + .I3(sig_psm_halt), + .I4(sig_input_reg_empty), + .I5(Q[2]), + .O(addr_i_p1[2])); + FDSE \INFERRED_GEN.cnt_i_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(addr_i_p1[0]), + .Q(Q[0]), + .S(sig_stream_rst)); + FDSE \INFERRED_GEN.cnt_i_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(addr_i_p1[1]), + .Q(Q[1]), + .S(sig_stream_rst)); + FDSE \INFERRED_GEN.cnt_i_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(addr_i_p1[2]), + .Q(Q[2]), + .S(sig_stream_rst)); +endmodule + +(* ORIG_REF_NAME = "cntr_incr_decr_addn_f" *) +module Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_17 + (p_9_out, + Q, + fifo_full_p1, + s2mm_halt, + s2mm_soft_reset, + dma_err, + CO, + out, + m_axis_s2mm_sts_tready, + sig_wr_fifo, + sig_wsc2stat_status_valid, + FIFO_Full_reg, + sig_inhibit_rdy_n, + sig_stream_rst, + m_axi_s2mm_aclk); + output p_9_out; + output [2:0]Q; + output fifo_full_p1; + input s2mm_halt; + input s2mm_soft_reset; + input dma_err; + input [0:0]CO; + input [0:0]out; + input m_axis_s2mm_sts_tready; + input sig_wr_fifo; + input sig_wsc2stat_status_valid; + input FIFO_Full_reg; + input sig_inhibit_rdy_n; + input sig_stream_rst; + input m_axi_s2mm_aclk; + + wire [0:0]CO; + wire FIFO_Full_reg; + wire [2:0]Q; + wire [2:0]addr_i_p1; + wire dma_err; + wire fifo_full_p1; + wire m_axi_s2mm_aclk; + wire m_axis_s2mm_sts_tready; + wire [0:0]out; + wire p_9_out; + wire s2mm_halt; + wire s2mm_soft_reset; + wire sig_inhibit_rdy_n; + wire sig_stream_rst; + wire sig_wr_fifo; + wire sig_wsc2stat_status_valid; + + (* SOFT_HLUTNM = "soft_lutpair236" *) + LUT5 #( + .INIT(32'h41100000)) + FIFO_Full_i_1__11 + (.I0(Q[2]), + .I1(m_axis_s2mm_sts_tready), + .I2(sig_wr_fifo), + .I3(Q[0]), + .I4(Q[1]), + .O(fifo_full_p1)); + LUT6 #( + .INIT(64'h0000000000010000)) + \GEN_STS_GRTR_THAN_8.ovrflo_err_i_1 + (.I0(s2mm_halt), + .I1(s2mm_soft_reset), + .I2(dma_err), + .I3(Q[2]), + .I4(CO), + .I5(out), + .O(p_9_out)); + LUT6 #( + .INIT(64'hBB4BBBBB44B44444)) + \INFERRED_GEN.cnt_i[0]_i_1__11 + (.I0(Q[2]), + .I1(m_axis_s2mm_sts_tready), + .I2(sig_wsc2stat_status_valid), + .I3(FIFO_Full_reg), + .I4(sig_inhibit_rdy_n), + .I5(Q[0]), + .O(addr_i_p1[0])); + LUT5 #( + .INIT(32'h77E78818)) + \INFERRED_GEN.cnt_i[1]_i_1__11 + (.I0(Q[0]), + .I1(sig_wr_fifo), + .I2(m_axis_s2mm_sts_tready), + .I3(Q[2]), + .I4(Q[1]), + .O(addr_i_p1[1])); + (* SOFT_HLUTNM = "soft_lutpair236" *) + LUT5 #( + .INIT(32'h7F7F0180)) + \INFERRED_GEN.cnt_i[2]_i_1__11 + (.I0(sig_wr_fifo), + .I1(Q[0]), + .I2(Q[1]), + .I3(m_axis_s2mm_sts_tready), + .I4(Q[2]), + .O(addr_i_p1[2])); + FDSE \INFERRED_GEN.cnt_i_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(addr_i_p1[0]), + .Q(Q[0]), + .S(sig_stream_rst)); + FDSE \INFERRED_GEN.cnt_i_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(addr_i_p1[1]), + .Q(Q[1]), + .S(sig_stream_rst)); + FDSE \INFERRED_GEN.cnt_i_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(addr_i_p1[2]), + .Q(Q[2]), + .S(sig_stream_rst)); +endmodule + +(* ORIG_REF_NAME = "cntr_incr_decr_addn_f" *) +module Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_18 + (sig_calc_error_reg_reg, + fifo_full_p1, + Q, + sig_halt_reg, + sig_addr_reg_empty_reg, + sig_wr_fifo, + p_22_out, + FIFO_Full_reg, + sig_inhibit_rdy_n_reg, + sig_stream_rst, + m_axi_s2mm_aclk); + output sig_calc_error_reg_reg; + output fifo_full_p1; + output [1:0]Q; + input sig_halt_reg; + input sig_addr_reg_empty_reg; + input sig_wr_fifo; + input p_22_out; + input FIFO_Full_reg; + input sig_inhibit_rdy_n_reg; + input sig_stream_rst; + input m_axi_s2mm_aclk; + + wire FIFO_Full_reg; + wire [1:0]Q; + wire [2:0]addr_i_p1; + wire fifo_full_p1; + wire m_axi_s2mm_aclk; + wire p_22_out; + wire sig_addr_reg_empty_reg; + wire sig_calc_error_reg_reg; + wire sig_halt_reg; + wire sig_inhibit_rdy_n_reg; + wire sig_rd_empty; + wire sig_stream_rst; + wire sig_wr_fifo; + + LUT6 #( + .INIT(64'h0451510000000000)) + FIFO_Full_i_1__7 + (.I0(sig_rd_empty), + .I1(sig_addr_reg_empty_reg), + .I2(sig_halt_reg), + .I3(sig_wr_fifo), + .I4(Q[0]), + .I5(Q[1]), + .O(fifo_full_p1)); + LUT5 #( + .INIT(32'h5955A6AA)) + \INFERRED_GEN.cnt_i[0]_i_1__7 + (.I0(sig_calc_error_reg_reg), + .I1(p_22_out), + .I2(FIFO_Full_reg), + .I3(sig_inhibit_rdy_n_reg), + .I4(Q[0]), + .O(addr_i_p1[0])); + LUT6 #( + .INIT(64'hAEAAF7FF51550800)) + \INFERRED_GEN.cnt_i[1]_i_1__7 + (.I0(Q[0]), + .I1(p_22_out), + .I2(FIFO_Full_reg), + .I3(sig_inhibit_rdy_n_reg), + .I4(sig_calc_error_reg_reg), + .I5(Q[1]), + .O(addr_i_p1[1])); + LUT6 #( + .INIT(64'h7F7F7F7F80018080)) + \INFERRED_GEN.cnt_i[2]_i_1__7 + (.I0(sig_wr_fifo), + .I1(Q[0]), + .I2(Q[1]), + .I3(sig_halt_reg), + .I4(sig_addr_reg_empty_reg), + .I5(sig_rd_empty), + .O(addr_i_p1[2])); + FDSE \INFERRED_GEN.cnt_i_reg[0] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(p_level_in_d1_cdc_from), - .Q(s_level_out_d1_cdc_to), - .R(1'b0)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 - (.C(s_axi_lite_aclk), + .D(addr_i_p1[0]), + .Q(Q[0]), + .S(sig_stream_rst)); + FDSE \INFERRED_GEN.cnt_i_reg[1] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(s_level_out_d1_cdc_to), - .Q(s_level_out_d2), - .R(1'b0)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 - (.C(s_axi_lite_aclk), + .D(addr_i_p1[1]), + .Q(Q[1]), + .S(sig_stream_rst)); + FDSE \INFERRED_GEN.cnt_i_reg[2] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(s_level_out_d2), - .Q(s_level_out_d3), - .R(1'b0)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 - (.C(s_axi_lite_aclk), + .D(addr_i_p1[2]), + .Q(sig_rd_empty), + .S(sig_stream_rst)); + LUT3 #( + .INIT(8'h04)) + \sig_next_addr_reg[31]_i_2__0 + (.I0(sig_halt_reg), + .I1(sig_addr_reg_empty_reg), + .I2(sig_rd_empty), + .O(sig_calc_error_reg_reg)); +endmodule + +(* ORIG_REF_NAME = "cntr_incr_decr_addn_f" *) +module Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_19 + (Q, + fifo_full_p1, + sig_sm_ld_dre_cmd_ns, + D, + sig_need_cmd_flush, + p_7_out, + out, + sig_sm_pop_cmd_fifo, + sig_wr_fifo, + p_9_out_0, + FIFO_Full_reg, + sig_inhibit_rdy_n_reg, + \FSM_sequential_sig_cmdcntl_sm_state_reg[2] , + sig_cmd_empty_reg, + \INFERRED_GEN.cnt_i_reg[2]_0 , + sig_stream_rst, + m_axi_s2mm_aclk); + output [2:0]Q; + output fifo_full_p1; + output sig_sm_ld_dre_cmd_ns; + output [1:0]D; + input sig_need_cmd_flush; + input p_7_out; + input [0:0]out; + input sig_sm_pop_cmd_fifo; + input sig_wr_fifo; + input p_9_out_0; + input FIFO_Full_reg; + input sig_inhibit_rdy_n_reg; + input [2:0]\FSM_sequential_sig_cmdcntl_sm_state_reg[2] ; + input sig_cmd_empty_reg; + input \INFERRED_GEN.cnt_i_reg[2]_0 ; + input sig_stream_rst; + input m_axi_s2mm_aclk; + + wire [1:0]D; + wire FIFO_Full_reg; + wire \FSM_sequential_sig_cmdcntl_sm_state[0]_i_2_n_0 ; + wire [2:0]\FSM_sequential_sig_cmdcntl_sm_state_reg[2] ; + wire \INFERRED_GEN.cnt_i_reg[2]_0 ; + wire [2:0]Q; + wire [2:0]addr_i_p1; + wire fifo_full_p1; + wire m_axi_s2mm_aclk; + wire [0:0]out; + wire p_7_out; + wire p_9_out_0; + wire sig_cmd_empty_reg; + wire sig_inhibit_rdy_n_reg; + wire sig_need_cmd_flush; + wire sig_sm_ld_dre_cmd_i_2_n_0; + wire sig_sm_ld_dre_cmd_ns; + wire sig_sm_pop_cmd_fifo; + wire sig_stream_rst; + wire sig_wr_fifo; + + (* SOFT_HLUTNM = "soft_lutpair233" *) + LUT5 #( + .INIT(32'h41100000)) + FIFO_Full_i_1__9 + (.I0(Q[2]), + .I1(sig_sm_pop_cmd_fifo), + .I2(sig_wr_fifo), + .I3(Q[0]), + .I4(Q[1]), + .O(fifo_full_p1)); + LUT6 #( + .INIT(64'h000F0B0FF00FF30F)) + \FSM_sequential_sig_cmdcntl_sm_state[0]_i_1 + (.I0(\FSM_sequential_sig_cmdcntl_sm_state[0]_i_2_n_0 ), + .I1(sig_cmd_empty_reg), + .I2(\FSM_sequential_sig_cmdcntl_sm_state_reg[2] [2]), + .I3(\FSM_sequential_sig_cmdcntl_sm_state_reg[2] [0]), + .I4(\INFERRED_GEN.cnt_i_reg[2]_0 ), + .I5(\FSM_sequential_sig_cmdcntl_sm_state_reg[2] [1]), + .O(D[0])); + (* SOFT_HLUTNM = "soft_lutpair234" *) + LUT2 #( + .INIT(4'h2)) + \FSM_sequential_sig_cmdcntl_sm_state[0]_i_2 + (.I0(sig_need_cmd_flush), + .I1(Q[2]), + .O(\FSM_sequential_sig_cmdcntl_sm_state[0]_i_2_n_0 )); + LUT6 #( + .INIT(64'h0000540000FF5000)) + \FSM_sequential_sig_cmdcntl_sm_state[2]_i_1 + (.I0(Q[2]), + .I1(sig_need_cmd_flush), + .I2(out), + .I3(\FSM_sequential_sig_cmdcntl_sm_state_reg[2] [0]), + .I4(\FSM_sequential_sig_cmdcntl_sm_state_reg[2] [2]), + .I5(\FSM_sequential_sig_cmdcntl_sm_state_reg[2] [1]), + .O(D[1])); + LUT6 #( + .INIT(64'hBB4BBBBB44B44444)) + \INFERRED_GEN.cnt_i[0]_i_1__9 + (.I0(Q[2]), + .I1(sig_sm_pop_cmd_fifo), + .I2(p_9_out_0), + .I3(FIFO_Full_reg), + .I4(sig_inhibit_rdy_n_reg), + .I5(Q[0]), + .O(addr_i_p1[0])); + LUT5 #( + .INIT(32'h77E78818)) + \INFERRED_GEN.cnt_i[1]_i_1__9 + (.I0(Q[0]), + .I1(sig_wr_fifo), + .I2(sig_sm_pop_cmd_fifo), + .I3(Q[2]), + .I4(Q[1]), + .O(addr_i_p1[1])); + (* SOFT_HLUTNM = "soft_lutpair233" *) + LUT5 #( + .INIT(32'h7F7F0180)) + \INFERRED_GEN.cnt_i[2]_i_1__9 + (.I0(sig_wr_fifo), + .I1(Q[0]), + .I2(Q[1]), + .I3(sig_sm_pop_cmd_fifo), + .I4(Q[2]), + .O(addr_i_p1[2])); + FDSE \INFERRED_GEN.cnt_i_reg[0] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(s_level_out_d3), - .Q(scndry_out), - .R(1'b0)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from - (.C(m_axi_mm2s_aclk), + .D(addr_i_p1[0]), + .Q(Q[0]), + .S(sig_stream_rst)); + FDSE \INFERRED_GEN.cnt_i_reg[1] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(\FSM_sequential_dmacntrl_cs_reg[1] ), - .Q(p_level_in_d1_cdc_from), - .R(1'b0)); + .D(addr_i_p1[1]), + .Q(Q[1]), + .S(sig_stream_rst)); + FDSE \INFERRED_GEN.cnt_i_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(addr_i_p1[2]), + .Q(Q[2]), + .S(sig_stream_rst)); + LUT6 #( + .INIT(64'h4040404000404040)) + sig_sm_ld_dre_cmd_i_1 + (.I0(\FSM_sequential_sig_cmdcntl_sm_state_reg[2] [2]), + .I1(\FSM_sequential_sig_cmdcntl_sm_state_reg[2] [0]), + .I2(sig_sm_ld_dre_cmd_i_2_n_0), + .I3(\FSM_sequential_sig_cmdcntl_sm_state_reg[2] [1]), + .I4(sig_need_cmd_flush), + .I5(Q[2]), + .O(sig_sm_ld_dre_cmd_ns)); + (* SOFT_HLUTNM = "soft_lutpair234" *) + LUT3 #( + .INIT(8'h02)) + sig_sm_ld_dre_cmd_i_2 + (.I0(p_7_out), + .I1(Q[2]), + .I2(out), + .O(sig_sm_ld_dre_cmd_i_2_n_0)); endmodule -(* ORIG_REF_NAME = "cdc_sync" *) -module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized1 - (prmry_in_xored, - prmry_in_xored_0, +(* ORIG_REF_NAME = "cntr_incr_decr_addn_f" *) +module Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_21 + (D, + sig_dqual_reg_empty_reg, + sig_next_cmd_cmplt_reg_reg, + sig_dqual_reg_empty_reg_0, + fifo_full_p1, + FIFO_Full_reg, + E, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram , + Q, + \sig_dbeat_cntr_reg[0] , + m_axi_mm2s_rlast, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + FIFO_Full_reg_0, + sig_mstr2data_cmd_valid, + sig_inhibit_rdy_n_0, + FIFO_Full_reg_1, + \sig_dbeat_cntr_reg[5] , + sig_next_sequential_reg, + sig_last_dbeat, + sig_dqual_reg_empty, + sig_rsc2stat_status_valid, + FIFO_Full_reg_2, + sig_inhibit_rdy_n, + sig_next_calc_error_reg_reg, + \sig_addr_posted_cntr_reg[2] , + \sig_addr_posted_cntr_reg[1] , + \sig_addr_posted_cntr_reg[0] , + ram_full_i_reg, + sig_halt_reg_reg, + m_axi_mm2s_rvalid, + sig_dqual_reg_full, + sig_data2rsc_valid, SR, - \GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_reg , - \GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_reg , - prmry_min_assert_sftrst, - scndry_out, - p_in_d1_cdc_from, - p_in_d1_cdc_from_1, - s_soft_reset_i_d1, - s_soft_reset_i, - min_assert_sftrst, - p_11_out, - m_axi_mm2s_aclk, - lite_min_assert_sftrst, - s_axi_lite_aclk); - output prmry_in_xored; - output prmry_in_xored_0; - output [0:0]SR; - output \GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_reg ; - output \GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_reg ; - input prmry_min_assert_sftrst; - input scndry_out; - input p_in_d1_cdc_from; - input p_in_d1_cdc_from_1; - input s_soft_reset_i_d1; - input s_soft_reset_i; - input min_assert_sftrst; - input p_11_out; + m_axi_mm2s_aclk); + output [2:0]D; + output sig_dqual_reg_empty_reg; + output sig_next_cmd_cmplt_reg_reg; + output sig_dqual_reg_empty_reg_0; + output fifo_full_p1; + output [1:0]FIFO_Full_reg; + output [0:0]E; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; + input [3:0]Q; + input \sig_dbeat_cntr_reg[0] ; + input m_axi_mm2s_rlast; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input FIFO_Full_reg_0; + input sig_mstr2data_cmd_valid; + input sig_inhibit_rdy_n_0; + input FIFO_Full_reg_1; + input \sig_dbeat_cntr_reg[5] ; + input sig_next_sequential_reg; + input sig_last_dbeat; + input sig_dqual_reg_empty; + input sig_rsc2stat_status_valid; + input FIFO_Full_reg_2; + input sig_inhibit_rdy_n; + input sig_next_calc_error_reg_reg; + input \sig_addr_posted_cntr_reg[2] ; + input \sig_addr_posted_cntr_reg[1] ; + input \sig_addr_posted_cntr_reg[0] ; + input ram_full_i_reg; + input sig_halt_reg_reg; + input m_axi_mm2s_rvalid; + input sig_dqual_reg_full; + input sig_data2rsc_valid; + input [0:0]SR; input m_axi_mm2s_aclk; - input lite_min_assert_sftrst; - input s_axi_lite_aclk; - wire \GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_reg ; - wire \GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_reg ; + wire [2:0]D; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; + wire [0:0]E; + wire [1:0]FIFO_Full_reg; + wire FIFO_Full_reg_0; + wire FIFO_Full_reg_1; + wire FIFO_Full_reg_2; + wire [3:0]Q; wire [0:0]SR; - wire lite_min_assert_sftrst; + wire [2:0]addr_i_p1; + wire fifo_full_p1; wire m_axi_mm2s_aclk; - wire min_assert_sftrst; - wire p_11_out; - wire p_5_out; - wire p_in_d1_cdc_from; - wire p_in_d1_cdc_from_1; - wire p_level_in_d1_cdc_from; - wire prmry_in_xored; - wire prmry_in_xored_0; - wire prmry_min_assert_sftrst; - wire s_axi_lite_aclk; - wire s_level_out_d1_cdc_to; - wire s_level_out_d2; - wire s_level_out_d3; - wire s_soft_reset_i; - wire s_soft_reset_i_d1; - wire scndry_out; + wire m_axi_mm2s_rlast; + wire m_axi_mm2s_rvalid; + wire ram_full_i_reg; + wire \sig_addr_posted_cntr_reg[0] ; + wire \sig_addr_posted_cntr_reg[1] ; + wire \sig_addr_posted_cntr_reg[2] ; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_data2rsc_valid; + wire \sig_dbeat_cntr_reg[0] ; + wire \sig_dbeat_cntr_reg[5] ; + wire sig_dqual_reg_empty; + wire sig_dqual_reg_empty_reg; + wire sig_dqual_reg_empty_reg_0; + wire sig_dqual_reg_full; + wire sig_halt_reg_reg; + wire sig_inhibit_rdy_n; + wire sig_inhibit_rdy_n_0; + wire sig_last_dbeat; + wire sig_mstr2data_cmd_valid; + wire sig_next_calc_error_reg_reg; + wire sig_next_cmd_cmplt_reg_i_4_n_0; + wire sig_next_cmd_cmplt_reg_i_5_n_0; + wire sig_next_cmd_cmplt_reg_reg; + wire sig_next_sequential_reg; + wire sig_rd_empty; + wire sig_rsc2stat_status_valid; - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(p_level_in_d1_cdc_from), - .Q(s_level_out_d1_cdc_to), - .R(1'b0)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 + LUT6 #( + .INIT(64'hFFFFFFFFFF01FFFF)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_7 + (.I0(\sig_addr_posted_cntr_reg[0] ), + .I1(\sig_addr_posted_cntr_reg[2] ), + .I2(\sig_addr_posted_cntr_reg[1] ), + .I3(sig_next_calc_error_reg_reg), + .I4(sig_dqual_reg_full), + .I5(sig_data2rsc_valid), + .O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram )); + (* SOFT_HLUTNM = "soft_lutpair160" *) + LUT5 #( + .INIT(32'h80009200)) + FIFO_Full_i_1__0 + (.I0(FIFO_Full_reg[0]), + .I1(sig_dqual_reg_empty_reg), + .I2(FIFO_Full_reg_0), + .I3(FIFO_Full_reg[1]), + .I4(sig_rd_empty), + .O(fifo_full_p1)); + LUT5 #( + .INIT(32'h5595AA6A)) + \INFERRED_GEN.cnt_i[0]_i_1__0 + (.I0(FIFO_Full_reg[0]), + .I1(sig_mstr2data_cmd_valid), + .I2(sig_inhibit_rdy_n_0), + .I3(FIFO_Full_reg_1), + .I4(sig_dqual_reg_empty_reg), + .O(addr_i_p1[0])); + LUT6 #( + .INIT(64'hAAEAFF7F55150080)) + \INFERRED_GEN.cnt_i[1]_i_1__0 + (.I0(FIFO_Full_reg[0]), + .I1(sig_mstr2data_cmd_valid), + .I2(sig_inhibit_rdy_n_0), + .I3(FIFO_Full_reg_1), + .I4(sig_dqual_reg_empty_reg), + .I5(FIFO_Full_reg[1]), + .O(addr_i_p1[1])); + (* SOFT_HLUTNM = "soft_lutpair160" *) + LUT5 #( + .INIT(32'h006A03AA)) + \INFERRED_GEN.cnt_i[2]_i_1__0 + (.I0(sig_rd_empty), + .I1(FIFO_Full_reg[1]), + .I2(FIFO_Full_reg_0), + .I3(sig_dqual_reg_empty_reg), + .I4(FIFO_Full_reg[0]), + .O(addr_i_p1[2])); + FDSE \INFERRED_GEN.cnt_i_reg[0] (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(s_level_out_d1_cdc_to), - .Q(s_level_out_d2), - .R(1'b0)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 + .D(addr_i_p1[0]), + .Q(FIFO_Full_reg[0]), + .S(SR)); + FDSE \INFERRED_GEN.cnt_i_reg[1] (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(s_level_out_d2), - .Q(s_level_out_d3), - .R(1'b0)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 + .D(addr_i_p1[1]), + .Q(FIFO_Full_reg[1]), + .S(SR)); + FDSE \INFERRED_GEN.cnt_i_reg[2] (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(s_level_out_d3), - .Q(p_5_out), - .R(1'b0)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(lite_min_assert_sftrst), - .Q(p_level_in_d1_cdc_from), - .R(1'b0)); - (* SOFT_HLUTNM = "soft_lutpair113" *) + .D(addr_i_p1[2]), + .Q(sig_rd_empty), + .S(SR)); + (* SOFT_HLUTNM = "soft_lutpair159" *) LUT4 #( - .INIT(16'h7F80)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__0 - (.I0(p_5_out), - .I1(prmry_min_assert_sftrst), - .I2(scndry_out), - .I3(p_in_d1_cdc_from), - .O(prmry_in_xored)); - (* SOFT_HLUTNM = "soft_lutpair113" *) + .INIT(16'h00D2)) + \sig_dbeat_cntr[5]_i_1__0 + (.I0(\sig_dbeat_cntr_reg[0] ), + .I1(Q[0]), + .I2(Q[1]), + .I3(sig_dqual_reg_empty_reg), + .O(D[0])); + (* SOFT_HLUTNM = "soft_lutpair159" *) + LUT5 #( + .INIT(32'h0000FD02)) + \sig_dbeat_cntr[6]_i_1 + (.I0(\sig_dbeat_cntr_reg[0] ), + .I1(Q[1]), + .I2(Q[0]), + .I3(Q[2]), + .I4(sig_dqual_reg_empty_reg), + .O(D[1])); LUT4 #( - .INIT(16'h7F80)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__2 - (.I0(p_5_out), - .I1(prmry_min_assert_sftrst), - .I2(scndry_out), - .I3(p_in_d1_cdc_from_1), - .O(prmry_in_xored_0)); - LUT6 #( - .INIT(64'hF0E0FFFFF0E0F0E0)) - \GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_i_1 - (.I0(prmry_min_assert_sftrst), - .I1(p_5_out), - .I2(min_assert_sftrst), - .I3(scndry_out), - .I4(s_soft_reset_i_d1), - .I5(s_soft_reset_i), - .O(\GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_reg )); + .INIT(16'hFBAA)) + \sig_dbeat_cntr[7]_i_1 + (.I0(sig_dqual_reg_empty_reg), + .I1(\sig_dbeat_cntr_reg[0] ), + .I2(\sig_dbeat_cntr_reg[5] ), + .I3(sig_dqual_reg_empty_reg_0), + .O(E)); LUT6 #( - .INIT(64'h00FFF2F2FFFFF2F2)) - \GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_i_1 - (.I0(s_soft_reset_i), - .I1(s_soft_reset_i_d1), - .I2(p_11_out), - .I3(p_5_out), - .I4(prmry_min_assert_sftrst), - .I5(scndry_out), - .O(\GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_reg )); + .INIT(64'h00000000FFEF0010)) + \sig_dbeat_cntr[7]_i_2 + (.I0(Q[0]), + .I1(Q[1]), + .I2(\sig_dbeat_cntr_reg[0] ), + .I3(Q[2]), + .I4(Q[3]), + .I5(sig_dqual_reg_empty_reg), + .O(D[2])); + LUT4 #( + .INIT(16'h40FF)) + sig_next_cmd_cmplt_reg_i_1 + (.I0(sig_dqual_reg_empty_reg), + .I1(m_axi_mm2s_rlast), + .I2(sig_dqual_reg_empty_reg_0), + .I3(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .O(sig_next_cmd_cmplt_reg_reg)); LUT5 #( - .INIT(32'h80FF8080)) - \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_1 - (.I0(p_5_out), - .I1(prmry_min_assert_sftrst), - .I2(scndry_out), - .I3(s_soft_reset_i_d1), - .I4(s_soft_reset_i), - .O(SR)); + .INIT(32'h0000FF80)) + sig_next_cmd_cmplt_reg_i_2 + (.I0(sig_dqual_reg_empty_reg_0), + .I1(sig_next_sequential_reg), + .I2(sig_last_dbeat), + .I3(sig_dqual_reg_empty), + .I4(sig_next_cmd_cmplt_reg_i_4_n_0), + .O(sig_dqual_reg_empty_reg)); + LUT4 #( + .INIT(16'h00D0)) + sig_next_cmd_cmplt_reg_i_3 + (.I0(ram_full_i_reg), + .I1(sig_halt_reg_reg), + .I2(m_axi_mm2s_rvalid), + .I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ), + .O(sig_dqual_reg_empty_reg_0)); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFEAEE)) + sig_next_cmd_cmplt_reg_i_4 + (.I0(sig_next_cmd_cmplt_reg_i_5_n_0), + .I1(sig_rsc2stat_status_valid), + .I2(FIFO_Full_reg_2), + .I3(sig_inhibit_rdy_n), + .I4(sig_next_calc_error_reg_reg), + .I5(sig_rd_empty), + .O(sig_next_cmd_cmplt_reg_i_4_n_0)); + LUT3 #( + .INIT(8'h80)) + sig_next_cmd_cmplt_reg_i_5 + (.I0(\sig_addr_posted_cntr_reg[2] ), + .I1(\sig_addr_posted_cntr_reg[1] ), + .I2(\sig_addr_posted_cntr_reg[0] ), + .O(sig_next_cmd_cmplt_reg_i_5_n_0)); endmodule -(* ORIG_REF_NAME = "cdc_sync" *) -module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized10 - (p_in_d1_cdc_from, - p_17_out, +(* ORIG_REF_NAME = "cntr_incr_decr_addn_f" *) +module Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_25 + (fifo_full_p1, + Q, + sig_calc_error_pushed_reg, + sig_wr_fifo, + sig_calc_error_pushed, + sig_sm_halt_reg, + sig_input_reg_empty, + p_56_out, + FIFO_Full_reg, + sig_inhibit_rdy_n, SR, - prmry_in_xored, - m_axis_mm2s_aclk, - prmry_resetn_i_reg, m_axi_mm2s_aclk); - output p_in_d1_cdc_from; - output p_17_out; + output fifo_full_p1; + output [2:0]Q; + input sig_calc_error_pushed_reg; + input sig_wr_fifo; + input sig_calc_error_pushed; + input sig_sm_halt_reg; + input sig_input_reg_empty; + input p_56_out; + input FIFO_Full_reg; + input sig_inhibit_rdy_n; input [0:0]SR; - input prmry_in_xored; - input m_axis_mm2s_aclk; - input [0:0]prmry_resetn_i_reg; input m_axi_mm2s_aclk; + wire FIFO_Full_reg; + wire [2:0]Q; wire [0:0]SR; + wire [2:0]addr_i_p1; + wire fifo_full_p1; wire m_axi_mm2s_aclk; - wire m_axis_mm2s_aclk; - wire p_17_out; - wire p_in_d1_cdc_from; - wire prmry_in_xored; - wire [0:0]prmry_resetn_i_reg; - wire s_out_d1_cdc_to; - wire s_out_d2; - wire s_out_d3; - wire s_out_d4; - wire s_out_d5; - wire s_out_re__0; - wire srst_d1; - wire srst_d2; - wire srst_d3; - wire srst_d4; - wire srst_d5; + wire p_56_out; + wire sig_calc_error_pushed; + wire sig_calc_error_pushed_reg; + wire sig_inhibit_rdy_n; + wire sig_input_reg_empty; + wire sig_sm_halt_reg; + wire sig_wr_fifo; - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2 - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(s_out_d1_cdc_to), - .Q(s_out_d2), - .R(prmry_resetn_i_reg)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3 - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(s_out_d2), - .Q(s_out_d3), - .R(prmry_resetn_i_reg)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4 + (* SOFT_HLUTNM = "soft_lutpair132" *) + LUT5 #( + .INIT(32'h80008220)) + FIFO_Full_i_1 + (.I0(Q[1]), + .I1(sig_calc_error_pushed_reg), + .I2(Q[0]), + .I3(sig_wr_fifo), + .I4(Q[2]), + .O(fifo_full_p1)); + LUT6 #( + .INIT(64'h6666666666696666)) + \INFERRED_GEN.cnt_i[0]_i_1 + (.I0(Q[0]), + .I1(sig_wr_fifo), + .I2(sig_calc_error_pushed), + .I3(sig_sm_halt_reg), + .I4(sig_input_reg_empty), + .I5(Q[2]), + .O(addr_i_p1[0])); + LUT6 #( + .INIT(64'hAA9AAAAA66A66666)) + \INFERRED_GEN.cnt_i[1]_i_1 + (.I0(Q[1]), + .I1(sig_calc_error_pushed_reg), + .I2(p_56_out), + .I3(FIFO_Full_reg), + .I4(sig_inhibit_rdy_n), + .I5(Q[0]), + .O(addr_i_p1[1])); + (* SOFT_HLUTNM = "soft_lutpair132" *) + LUT5 #( + .INIT(32'h006A03AA)) + \INFERRED_GEN.cnt_i[2]_i_1 + (.I0(Q[2]), + .I1(sig_wr_fifo), + .I2(Q[0]), + .I3(sig_calc_error_pushed_reg), + .I4(Q[1]), + .O(addr_i_p1[2])); + FDSE \INFERRED_GEN.cnt_i_reg[0] (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(s_out_d3), - .Q(s_out_d4), - .R(prmry_resetn_i_reg)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5 + .D(addr_i_p1[0]), + .Q(Q[0]), + .S(SR)); + FDSE \INFERRED_GEN.cnt_i_reg[1] (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(s_out_d4), - .Q(s_out_d5), - .R(prmry_resetn_i_reg)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out + .D(addr_i_p1[1]), + .Q(Q[1]), + .S(SR)); + FDSE \INFERRED_GEN.cnt_i_reg[2] (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(s_out_re__0), - .Q(p_17_out), - .R(prmry_resetn_i_reg)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to + .D(addr_i_p1[2]), + .Q(Q[2]), + .S(SR)); +endmodule + +(* ORIG_REF_NAME = "cntr_incr_decr_addn_f" *) +module Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_27 + (fifo_full_p1, + Q, + sig_wr_fifo, + p_58_out, + sig_inhibit_rdy_n_reg, + FIFO_Full_reg, + sig_rsc2stat_status_valid, + sts_tready_reg, + SR, + m_axi_mm2s_aclk); + output fifo_full_p1; + output [2:0]Q; + input sig_wr_fifo; + input p_58_out; + input sig_inhibit_rdy_n_reg; + input FIFO_Full_reg; + input sig_rsc2stat_status_valid; + input sts_tready_reg; + input [0:0]SR; + input m_axi_mm2s_aclk; + + wire FIFO_Full_reg; + wire [2:0]Q; + wire [0:0]SR; + wire [2:0]addr_i_p1; + wire fifo_full_p1; + wire m_axi_mm2s_aclk; + wire p_58_out; + wire sig_inhibit_rdy_n_reg; + wire sig_rsc2stat_status_valid; + wire sig_wr_fifo; + wire sts_tready_reg; + + (* SOFT_HLUTNM = "soft_lutpair130" *) + LUT5 #( + .INIT(32'h08060000)) + FIFO_Full_i_1__3 + (.I0(sig_wr_fifo), + .I1(Q[0]), + .I2(Q[2]), + .I3(p_58_out), + .I4(Q[1]), + .O(fifo_full_p1)); + LUT6 #( + .INIT(64'hDFDF20DF2020DF20)) + \INFERRED_GEN.cnt_i[0]_i_1__3 + (.I0(sig_inhibit_rdy_n_reg), + .I1(FIFO_Full_reg), + .I2(sig_rsc2stat_status_valid), + .I3(p_58_out), + .I4(Q[2]), + .I5(Q[0]), + .O(addr_i_p1[0])); + LUT6 #( + .INIT(64'hAEAAF7FF51550800)) + \INFERRED_GEN.cnt_i[1]_i_1__3 + (.I0(Q[0]), + .I1(sig_inhibit_rdy_n_reg), + .I2(FIFO_Full_reg), + .I3(sig_rsc2stat_status_valid), + .I4(sts_tready_reg), + .I5(Q[1]), + .O(addr_i_p1[1])); + (* SOFT_HLUTNM = "soft_lutpair130" *) + LUT5 #( + .INIT(32'h52F0F0F4)) + \INFERRED_GEN.cnt_i[2]_i_1__3 + (.I0(Q[1]), + .I1(p_58_out), + .I2(Q[2]), + .I3(Q[0]), + .I4(sig_wr_fifo), + .O(addr_i_p1[2])); + FDSE \INFERRED_GEN.cnt_i_reg[0] (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(p_in_d1_cdc_from), - .Q(s_out_d1_cdc_to), - .R(prmry_resetn_i_reg)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(prmry_in_xored), - .Q(p_in_d1_cdc_from), - .R(SR)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1 + .D(addr_i_p1[0]), + .Q(Q[0]), + .S(SR)); + FDSE \INFERRED_GEN.cnt_i_reg[1] (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(1'b1), - .Q(srst_d1), - .R(prmry_resetn_i_reg)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2 + .D(addr_i_p1[1]), + .Q(Q[1]), + .S(SR)); + FDSE \INFERRED_GEN.cnt_i_reg[2] (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(srst_d1), - .Q(srst_d2), - .R(prmry_resetn_i_reg)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3 + .D(addr_i_p1[2]), + .Q(Q[2]), + .S(SR)); +endmodule + +(* ORIG_REF_NAME = "cntr_incr_decr_addn_f" *) +module Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_28 + (sig_posted_to_axi_2_reg, + fifo_full_p1, + Q, + sig_addr_reg_empty_reg, + sig_addr_reg_empty, + sig_sf_allow_addr_req, + sig_data2addr_stop_req, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + FIFO_Full_reg, + FIFO_Full_reg_0, + sig_inhibit_rdy_n, + sig_mstr2addr_cmd_valid, + SR, + m_axi_mm2s_aclk); + output sig_posted_to_axi_2_reg; + output fifo_full_p1; + output [1:0]Q; + output sig_addr_reg_empty_reg; + input sig_addr_reg_empty; + input sig_sf_allow_addr_req; + input sig_data2addr_stop_req; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input FIFO_Full_reg; + input FIFO_Full_reg_0; + input sig_inhibit_rdy_n; + input sig_mstr2addr_cmd_valid; + input [0:0]SR; + input m_axi_mm2s_aclk; + + wire FIFO_Full_reg; + wire FIFO_Full_reg_0; + wire [1:0]Q; + wire [0:0]SR; + wire [2:0]addr_i_p1; + wire fifo_full_p1; + wire m_axi_mm2s_aclk; + wire sig_addr_reg_empty; + wire sig_addr_reg_empty_reg; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_data2addr_stop_req; + wire sig_inhibit_rdy_n; + wire sig_mstr2addr_cmd_valid; + wire sig_posted_to_axi_2_reg; + wire sig_rd_empty; + wire sig_sf_allow_addr_req; + + (* SOFT_HLUTNM = "soft_lutpair128" *) + LUT5 #( + .INIT(32'h80008208)) + FIFO_Full_i_1__1 + (.I0(Q[1]), + .I1(FIFO_Full_reg), + .I2(sig_addr_reg_empty_reg), + .I3(Q[0]), + .I4(sig_rd_empty), + .O(fifo_full_p1)); + LUT5 #( + .INIT(32'h69666666)) + \INFERRED_GEN.cnt_i[0]_i_1__1 + (.I0(Q[0]), + .I1(sig_addr_reg_empty_reg), + .I2(FIFO_Full_reg_0), + .I3(sig_inhibit_rdy_n), + .I4(sig_mstr2addr_cmd_valid), + .O(addr_i_p1[0])); + LUT6 #( + .INIT(64'hA69AA6A6A6A6A6A6)) + \INFERRED_GEN.cnt_i[1]_i_1__1 + (.I0(Q[1]), + .I1(sig_addr_reg_empty_reg), + .I2(Q[0]), + .I3(FIFO_Full_reg_0), + .I4(sig_inhibit_rdy_n), + .I5(sig_mstr2addr_cmd_valid), + .O(addr_i_p1[1])); + (* SOFT_HLUTNM = "soft_lutpair128" *) + LUT5 #( + .INIT(32'h060A0A3A)) + \INFERRED_GEN.cnt_i[2]_i_1__1 + (.I0(sig_rd_empty), + .I1(Q[0]), + .I2(sig_addr_reg_empty_reg), + .I3(FIFO_Full_reg), + .I4(Q[1]), + .O(addr_i_p1[2])); + FDSE \INFERRED_GEN.cnt_i_reg[0] (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(srst_d2), - .Q(srst_d3), - .R(prmry_resetn_i_reg)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4 + .D(addr_i_p1[0]), + .Q(Q[0]), + .S(SR)); + FDSE \INFERRED_GEN.cnt_i_reg[1] (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(srst_d3), - .Q(srst_d4), - .R(prmry_resetn_i_reg)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5 + .D(addr_i_p1[1]), + .Q(Q[1]), + .S(SR)); + FDSE \INFERRED_GEN.cnt_i_reg[2] (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(srst_d4), - .Q(srst_d5), - .R(prmry_resetn_i_reg)); - LUT3 #( - .INIT(8'h28)) - s_out_re - (.I0(srst_d5), - .I1(s_out_d5), - .I2(s_out_d4), - .O(s_out_re__0)); + .D(addr_i_p1[2]), + .Q(sig_rd_empty), + .S(SR)); + (* SOFT_HLUTNM = "soft_lutpair129" *) + LUT4 #( + .INIT(16'h0040)) + \sig_next_addr_reg[31]_i_2 + (.I0(sig_data2addr_stop_req), + .I1(sig_sf_allow_addr_req), + .I2(sig_addr_reg_empty), + .I3(sig_rd_empty), + .O(sig_addr_reg_empty_reg)); + (* SOFT_HLUTNM = "soft_lutpair129" *) + LUT5 #( + .INIT(32'h00400000)) + sig_posted_to_axi_2_i_1 + (.I0(sig_rd_empty), + .I1(sig_addr_reg_empty), + .I2(sig_sf_allow_addr_req), + .I3(sig_data2addr_stop_req), + .I4(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .O(sig_posted_to_axi_2_reg)); endmodule -(* ORIG_REF_NAME = "cdc_sync" *) -module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized12 - (p_in_d1_cdc_from_0, - p_15_out, - all_lines_xfred, - prmry_resetn_i_reg, - prmry_in_xored_1, - m_axi_mm2s_aclk, +(* ORIG_REF_NAME = "cntr_incr_decr_addn_f" *) +module Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_29 + (fifo_full_p1, + Q, + FIFO_Full_reg, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg , + FIFO_Full_reg_0, + sig_inhibit_rdy_n_reg, + sig_mstr2sf_cmd_valid, + DOBDO, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , + lsig_cmd_loaded, SR, - m_axis_mm2s_aclk, - \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4] ); - output p_in_d1_cdc_from_0; - output p_15_out; - output all_lines_xfred; - input [0:0]prmry_resetn_i_reg; - input prmry_in_xored_1; - input m_axi_mm2s_aclk; + m_axi_mm2s_aclk); + output fifo_full_p1; + output [2:0]Q; + output FIFO_Full_reg; + input \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + input FIFO_Full_reg_0; + input sig_inhibit_rdy_n_reg; + input sig_mstr2sf_cmd_valid; + input [0:0]DOBDO; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + input lsig_cmd_loaded; input [0:0]SR; - input m_axis_mm2s_aclk; - input \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4] ; + input m_axi_mm2s_aclk; - wire \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4] ; + wire [0:0]DOBDO; + wire FIFO_Full_reg; + wire FIFO_Full_reg_0; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + wire \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + wire \INFERRED_GEN.cnt_i[1]_i_2_n_0 ; + wire [2:0]Q; wire [0:0]SR; - wire all_lines_xfred; + wire [2:0]addr_i_p1; + wire fifo_full_p1; + wire lsig_cmd_loaded; wire m_axi_mm2s_aclk; - wire m_axis_mm2s_aclk; - wire p_15_out; - wire p_in_d1_cdc_from_0; - wire prmry_in_xored_1; - wire [0:0]prmry_resetn_i_reg; - wire s_out_d1_cdc_to; - wire s_out_d2; - wire s_out_d3; - wire s_out_d4; - wire s_out_d5; - wire s_out_re__0; - wire srst_d1; - wire srst_d2; - wire srst_d3; - wire srst_d4; - wire srst_d5; + wire sig_inhibit_rdy_n_reg; + wire sig_mstr2sf_cmd_valid; - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2 - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(s_out_d1_cdc_to), - .Q(s_out_d2), - .R(SR)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3 - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(s_out_d2), - .Q(s_out_d3), - .R(SR)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4 - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(s_out_d3), - .Q(s_out_d4), - .R(SR)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5 - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(s_out_d4), - .Q(s_out_d5), - .R(SR)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(s_out_re__0), - .Q(p_15_out), - .R(SR)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(p_in_d1_cdc_from_0), - .Q(s_out_d1_cdc_to), - .R(SR)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from + (* SOFT_HLUTNM = "soft_lutpair125" *) + LUT5 #( + .INIT(32'h02080800)) + FIFO_Full_i_1__2 + (.I0(Q[1]), + .I1(Q[0]), + .I2(Q[2]), + .I3(\INCLUDE_UNPACKING.lsig_cmd_loaded_reg ), + .I4(FIFO_Full_reg), + .O(fifo_full_p1)); + (* SOFT_HLUTNM = "soft_lutpair126" *) + LUT5 #( + .INIT(32'hAA6A5595)) + \INFERRED_GEN.cnt_i[0]_i_1__2 + (.I0(Q[0]), + .I1(sig_mstr2sf_cmd_valid), + .I2(sig_inhibit_rdy_n_reg), + .I3(FIFO_Full_reg_0), + .I4(\INFERRED_GEN.cnt_i[1]_i_2_n_0 ), + .O(addr_i_p1[0])); + LUT6 #( + .INIT(64'hA6AAAAAA9A999999)) + \INFERRED_GEN.cnt_i[1]_i_1__2 + (.I0(Q[1]), + .I1(\INFERRED_GEN.cnt_i[1]_i_2_n_0 ), + .I2(FIFO_Full_reg_0), + .I3(sig_inhibit_rdy_n_reg), + .I4(sig_mstr2sf_cmd_valid), + .I5(Q[0]), + .O(addr_i_p1[1])); + LUT4 #( + .INIT(16'hFBAA)) + \INFERRED_GEN.cnt_i[1]_i_2 + (.I0(Q[2]), + .I1(DOBDO), + .I2(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), + .I3(lsig_cmd_loaded), + .O(\INFERRED_GEN.cnt_i[1]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair125" *) + LUT5 #( + .INIT(32'h58F0F0F1)) + \INFERRED_GEN.cnt_i[2]_i_1__2 + (.I0(FIFO_Full_reg), + .I1(\INCLUDE_UNPACKING.lsig_cmd_loaded_reg ), + .I2(Q[2]), + .I3(Q[0]), + .I4(Q[1]), + .O(addr_i_p1[2])); + FDSE \INFERRED_GEN.cnt_i_reg[0] (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(prmry_in_xored_1), - .Q(p_in_d1_cdc_from_0), - .R(prmry_resetn_i_reg)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1 - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(1'b1), - .Q(srst_d1), - .R(SR)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2 - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(srst_d1), - .Q(srst_d2), - .R(SR)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3 - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(srst_d2), - .Q(srst_d3), - .R(SR)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4 - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(srst_d3), - .Q(srst_d4), - .R(SR)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5 - (.C(m_axis_mm2s_aclk), + .D(addr_i_p1[0]), + .Q(Q[0]), + .S(SR)); + FDSE \INFERRED_GEN.cnt_i_reg[1] + (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(srst_d4), - .Q(srst_d5), - .R(SR)); - LUT2 #( - .INIT(4'h1)) - \GEN_LINEBUF_NO_SOF.all_lines_xfred_i_1 - (.I0(p_15_out), - .I1(\GEN_LINEBUF_NO_SOF.vsize_counter_reg[4] ), - .O(all_lines_xfred)); + .D(addr_i_p1[1]), + .Q(Q[1]), + .S(SR)); + FDSE \INFERRED_GEN.cnt_i_reg[2] + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(addr_i_p1[2]), + .Q(Q[2]), + .S(SR)); + (* SOFT_HLUTNM = "soft_lutpair126" *) LUT3 #( - .INIT(8'h28)) - s_out_re - (.I0(srst_d5), - .I1(s_out_d5), - .I2(s_out_d4), - .O(s_out_re__0)); + .INIT(8'h40)) + \INFERRED_GEN.data_reg[3][7]_srl4_i_1__0 + (.I0(FIFO_Full_reg_0), + .I1(sig_inhibit_rdy_n_reg), + .I2(sig_mstr2sf_cmd_valid), + .O(FIFO_Full_reg)); endmodule -(* ORIG_REF_NAME = "cdc_sync" *) -module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized14 - (p_1_out, - SR, - m_axi_mm2s_aclk, - scndry_reset2, - fifo_pipe_empty, - m_axis_mm2s_aclk); - output p_1_out; - input [0:0]SR; - input m_axi_mm2s_aclk; - input scndry_reset2; - input fifo_pipe_empty; - input m_axis_mm2s_aclk; +(* ORIG_REF_NAME = "cntr_incr_decr_addn_f" *) +module Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f__parameterized0 + (fifo_full_p1, + Q, + sig_wr_fifo, + sig_push_coelsc_reg, + m_axi_s2mm_bvalid, + FIFO_Full_reg, + sig_inhibit_rdy_n, + \INFERRED_GEN.cnt_i_reg[3]_0 , + sig_stream_rst, + m_axi_s2mm_aclk); + output fifo_full_p1; + output [3:0]Q; + output sig_wr_fifo; + input sig_push_coelsc_reg; + input m_axi_s2mm_bvalid; + input FIFO_Full_reg; + input sig_inhibit_rdy_n; + input \INFERRED_GEN.cnt_i_reg[3]_0 ; + input sig_stream_rst; + input m_axi_s2mm_aclk; - wire [0:0]SR; - wire fifo_pipe_empty; - wire m_axi_mm2s_aclk; - wire m_axis_mm2s_aclk; - wire p_1_out; - wire p_level_in_d1_cdc_from; - wire s_level_out_d1_cdc_to; - wire s_level_out_d2; - wire s_level_out_d3; - wire scndry_reset2; + wire FIFO_Full_reg; + wire \INFERRED_GEN.cnt_i_reg[3]_0 ; + wire [3:0]Q; + wire [3:0]addr_i_p1; + wire fifo_full_p1; + wire m_axi_s2mm_aclk; + wire m_axi_s2mm_bvalid; + wire sig_inhibit_rdy_n; + wire sig_push_coelsc_reg; + wire sig_stream_rst; + wire sig_wr_fifo; - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(p_level_in_d1_cdc_from), - .Q(s_level_out_d1_cdc_to), - .R(SR)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 - (.C(m_axi_mm2s_aclk), + LUT6 #( + .INIT(64'h0004411000000000)) + FIFO_Full_i_1__5 + (.I0(Q[3]), + .I1(sig_push_coelsc_reg), + .I2(sig_wr_fifo), + .I3(Q[0]), + .I4(Q[1]), + .I5(Q[2]), + .O(fifo_full_p1)); + LUT6 #( + .INIT(64'hBB4BBBBB44B44444)) + \INFERRED_GEN.cnt_i[0]_i_1__5 + (.I0(Q[3]), + .I1(sig_push_coelsc_reg), + .I2(m_axi_s2mm_bvalid), + .I3(FIFO_Full_reg), + .I4(sig_inhibit_rdy_n), + .I5(Q[0]), + .O(addr_i_p1[0])); + LUT6 #( + .INIT(64'hAEAAF7FF51550800)) + \INFERRED_GEN.cnt_i[1]_i_1__5 + (.I0(Q[0]), + .I1(m_axi_s2mm_bvalid), + .I2(FIFO_Full_reg), + .I3(sig_inhibit_rdy_n), + .I4(\INFERRED_GEN.cnt_i_reg[3]_0 ), + .I5(Q[1]), + .O(addr_i_p1[1])); + LUT6 #( + .INIT(64'h7F7FFE7F80800180)) + \INFERRED_GEN.cnt_i[2]_i_1__5 + (.I0(sig_wr_fifo), + .I1(Q[0]), + .I2(Q[1]), + .I3(sig_push_coelsc_reg), + .I4(Q[3]), + .I5(Q[2]), + .O(addr_i_p1[2])); + LUT6 #( + .INIT(64'h7FFF7FFF00018000)) + \INFERRED_GEN.cnt_i[3]_i_1 + (.I0(Q[1]), + .I1(Q[0]), + .I2(sig_wr_fifo), + .I3(Q[2]), + .I4(sig_push_coelsc_reg), + .I5(Q[3]), + .O(addr_i_p1[3])); + FDSE \INFERRED_GEN.cnt_i_reg[0] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(s_level_out_d1_cdc_to), - .Q(s_level_out_d2), - .R(SR)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 - (.C(m_axi_mm2s_aclk), + .D(addr_i_p1[0]), + .Q(Q[0]), + .S(sig_stream_rst)); + FDSE \INFERRED_GEN.cnt_i_reg[1] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(s_level_out_d2), - .Q(s_level_out_d3), - .R(SR)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 - (.C(m_axi_mm2s_aclk), + .D(addr_i_p1[1]), + .Q(Q[1]), + .S(sig_stream_rst)); + FDSE \INFERRED_GEN.cnt_i_reg[2] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(s_level_out_d3), - .Q(p_1_out), - .R(SR)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from - (.C(m_axis_mm2s_aclk), + .D(addr_i_p1[2]), + .Q(Q[2]), + .S(sig_stream_rst)); + FDSE \INFERRED_GEN.cnt_i_reg[3] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(fifo_pipe_empty), - .Q(p_level_in_d1_cdc_from), - .R(scndry_reset2)); + .D(addr_i_p1[3]), + .Q(Q[3]), + .S(sig_stream_rst)); + LUT3 #( + .INIT(8'h20)) + \INFERRED_GEN.data_reg[5][0]_srl6_i_1 + (.I0(m_axi_s2mm_bvalid), + .I1(FIFO_Full_reg), + .I2(sig_inhibit_rdy_n), + .O(sig_wr_fifo)); endmodule -(* ORIG_REF_NAME = "cdc_sync" *) -module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized15 - (p_0_out, - SR, - m_axi_mm2s_aclk, - scndry_reset2, - \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg , - m_axis_mm2s_aclk); - output p_0_out; - input [0:0]SR; - input m_axi_mm2s_aclk; - input scndry_reset2; - input \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg ; - input m_axis_mm2s_aclk; +(* ORIG_REF_NAME = "cntr_incr_decr_addn_f" *) +module Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f__parameterized1 + (\INFERRED_GEN.cnt_i_reg[1]_0 , + Q, + fifo_full_p1, + \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg , + sig_coelsc_reg_empty, + \INFERRED_GEN.cnt_i_reg[3]_0 , + sig_push_to_wsc_reg, + out, + sig_data2wsc_valid, + FIFO_Full_reg, + sig_inhibit_rdy_n, + \INFERRED_GEN.cnt_i_reg[3]_1 , + sig_stream_rst, + m_axi_s2mm_aclk); + output \INFERRED_GEN.cnt_i_reg[1]_0 ; + output [3:0]Q; + output fifo_full_p1; + output \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ; + input sig_coelsc_reg_empty; + input [0:0]\INFERRED_GEN.cnt_i_reg[3]_0 ; + input sig_push_to_wsc_reg; + input [0:0]out; + input sig_data2wsc_valid; + input FIFO_Full_reg; + input sig_inhibit_rdy_n; + input \INFERRED_GEN.cnt_i_reg[3]_1 ; + input sig_stream_rst; + input m_axi_s2mm_aclk; - wire \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg ; - wire [0:0]SR; - wire m_axi_mm2s_aclk; - wire m_axis_mm2s_aclk; - wire p_0_out; - wire p_level_in_d1_cdc_from; - wire s_level_out_d1_cdc_to; - wire s_level_out_d2; - wire s_level_out_d3; - wire scndry_reset2; + wire FIFO_Full_reg; + wire \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ; + wire \INFERRED_GEN.cnt_i_reg[1]_0 ; + wire [0:0]\INFERRED_GEN.cnt_i_reg[3]_0 ; + wire \INFERRED_GEN.cnt_i_reg[3]_1 ; + wire [3:0]Q; + wire [3:0]addr_i_p1; + wire fifo_full_p1; + wire m_axi_s2mm_aclk; + wire [0:0]out; + wire sig_coelsc_reg_empty; + wire sig_data2wsc_valid; + wire sig_inhibit_rdy_n; + wire sig_push_to_wsc_reg; + wire sig_stream_rst; - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(p_level_in_d1_cdc_from), - .Q(s_level_out_d1_cdc_to), - .R(SR)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 - (.C(m_axi_mm2s_aclk), + LUT6 #( + .INIT(64'h0004411000000000)) + FIFO_Full_i_1__6 + (.I0(Q[3]), + .I1(\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ), + .I2(sig_push_to_wsc_reg), + .I3(Q[0]), + .I4(Q[1]), + .I5(Q[2]), + .O(fifo_full_p1)); + (* SOFT_HLUTNM = "soft_lutpair248" *) + LUT4 #( + .INIT(16'h2022)) + \GEN_ENABLE_INDET_BTT.sig_coelsc_reg_empty_i_2 + (.I0(sig_coelsc_reg_empty), + .I1(Q[3]), + .I2(out), + .I3(\INFERRED_GEN.cnt_i_reg[3]_0 ), + .O(\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg )); + LUT6 #( + .INIT(64'h4044BFBBBFBB4044)) + \INFERRED_GEN.cnt_i[0]_i_1__6 + (.I0(Q[3]), + .I1(sig_coelsc_reg_empty), + .I2(out), + .I3(\INFERRED_GEN.cnt_i_reg[3]_0 ), + .I4(sig_push_to_wsc_reg), + .I5(Q[0]), + .O(addr_i_p1[0])); + LUT6 #( + .INIT(64'hAEAAF7FF51550800)) + \INFERRED_GEN.cnt_i[1]_i_1__6 + (.I0(Q[0]), + .I1(sig_data2wsc_valid), + .I2(FIFO_Full_reg), + .I3(sig_inhibit_rdy_n), + .I4(\INFERRED_GEN.cnt_i_reg[3]_1 ), + .I5(Q[1]), + .O(addr_i_p1[1])); + (* SOFT_HLUTNM = "soft_lutpair248" *) + LUT3 #( + .INIT(8'h04)) + \INFERRED_GEN.cnt_i[1]_i_2__2 + (.I0(Q[3]), + .I1(sig_coelsc_reg_empty), + .I2(\INFERRED_GEN.cnt_i_reg[3]_0 ), + .O(\INFERRED_GEN.cnt_i_reg[1]_0 )); + LUT6 #( + .INIT(64'h7F7FFE7F80800180)) + \INFERRED_GEN.cnt_i[2]_i_1__6 + (.I0(sig_push_to_wsc_reg), + .I1(Q[0]), + .I2(Q[1]), + .I3(\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ), + .I4(Q[3]), + .I5(Q[2]), + .O(addr_i_p1[2])); + LUT6 #( + .INIT(64'h7FFF7FFF00018000)) + \INFERRED_GEN.cnt_i[3]_i_1__0 + (.I0(Q[1]), + .I1(Q[0]), + .I2(sig_push_to_wsc_reg), + .I3(Q[2]), + .I4(\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ), + .I5(Q[3]), + .O(addr_i_p1[3])); + FDSE \INFERRED_GEN.cnt_i_reg[0] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(s_level_out_d1_cdc_to), - .Q(s_level_out_d2), - .R(SR)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 - (.C(m_axi_mm2s_aclk), + .D(addr_i_p1[0]), + .Q(Q[0]), + .S(sig_stream_rst)); + FDSE \INFERRED_GEN.cnt_i_reg[1] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(s_level_out_d2), - .Q(s_level_out_d3), - .R(SR)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 - (.C(m_axi_mm2s_aclk), + .D(addr_i_p1[1]), + .Q(Q[1]), + .S(sig_stream_rst)); + FDSE \INFERRED_GEN.cnt_i_reg[2] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(s_level_out_d3), - .Q(p_0_out), - .R(SR)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from - (.C(m_axis_mm2s_aclk), + .D(addr_i_p1[2]), + .Q(Q[2]), + .S(sig_stream_rst)); + FDSE \INFERRED_GEN.cnt_i_reg[3] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(\GEN_LINEBUF_NO_SOF.all_lines_xfred_reg ), - .Q(p_level_in_d1_cdc_from), - .R(scndry_reset2)); + .D(addr_i_p1[3]), + .Q(Q[3]), + .S(sig_stream_rst)); endmodule -(* ORIG_REF_NAME = "cdc_sync" *) -module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized18 - (sig_reset_reg_reg, - m_axis_fifo_ainit_nosync, - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tready_d1_reg , - scndry_reset2, - m_axis_mm2s_aclk, +(* ORIG_REF_NAME = "cntr_incr_decr_addn_f" *) +module Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f__parameterized2 + (\INCLUDE_PACKING.lsig_first_dbeat_reg , + \sig_byte_cntr_reg[0] , + sig_dre2ibtt_tlast, + sig_cmd_full_reg, + sig_cmd_empty_reg, + sig_good_tlast_dbeat37_out__0, SR, - mm2s_halt, - m_axi_mm2s_aclk, - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 , - m_axis_mm2s_tready, - p_15_out); - output sig_reset_reg_reg; - output m_axis_fifo_ainit_nosync; - output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tready_d1_reg ; - input scndry_reset2; - input m_axis_mm2s_aclk; - input [0:0]SR; - input mm2s_halt; - input m_axi_mm2s_aclk; - input \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ; - input m_axis_mm2s_tready; - input p_15_out; + E, + Q, + sig_s_ready_dup4_reg, + \sig_byte_cntr_reg[7] , + SS, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] , + fifo_full_p1, + sig_wr_fifo, + sig_eop_sent, + \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg , + \INCLUDE_PACKING.lsig_first_dbeat_reg_0 , + sig_cmd_full, + sig_sm_ld_dre_cmd, + p_7_out, + sig_strm_tlast, + sig_m_valid_out_reg, + lsig_absorb2tlast, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_last_reg_out_reg, + sig_eop_halt_xfer, + sig_ibtt2dre_tready, + out, + sig_clr_dbc_reg, + sig_eop_sent_reg, + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 , + sig_inhibit_rdy_n_reg, + FIFO_Full_reg, + slice_insert_valid, + \storage_data_reg[3] , + lsig_cmd_fetch_pause, + sig_need_cmd_flush, + sig_sm_pop_cmd_fifo, + m_axi_s2mm_aclk); + output \INCLUDE_PACKING.lsig_first_dbeat_reg ; + output \sig_byte_cntr_reg[0] ; + output sig_dre2ibtt_tlast; + output sig_cmd_full_reg; + output sig_cmd_empty_reg; + output sig_good_tlast_dbeat37_out__0; + output [0:0]SR; + output [0:0]E; + output [4:0]Q; + output sig_s_ready_dup4_reg; + output [0:0]\sig_byte_cntr_reg[7] ; + output [0:0]SS; + output \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ; + output \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] ; + output fifo_full_p1; + output sig_wr_fifo; + output sig_eop_sent; + output \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg ; + input \INCLUDE_PACKING.lsig_first_dbeat_reg_0 ; + input sig_cmd_full; + input sig_sm_ld_dre_cmd; + input p_7_out; + input sig_strm_tlast; + input sig_m_valid_out_reg; + input lsig_absorb2tlast; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_last_reg_out_reg; + input sig_eop_halt_xfer; + input sig_ibtt2dre_tready; + input out; + input sig_clr_dbc_reg; + input sig_eop_sent_reg; + input [1:0]\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1] ; + input [1:0]\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ; + input sig_inhibit_rdy_n_reg; + input FIFO_Full_reg; + input slice_insert_valid; + input [1:0]\storage_data_reg[3] ; + input lsig_cmd_fetch_pause; + input sig_need_cmd_flush; + input sig_sm_pop_cmd_fifo; + input m_axi_s2mm_aclk; - wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ; - wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tready_d1_reg ; + wire [0:0]E; + wire FIFO_Full_i_2_n_0; + wire FIFO_Full_i_3_n_0; + wire FIFO_Full_reg; + wire \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg ; + wire [1:0]\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ; + wire [1:0]\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ; + wire \INCLUDE_PACKING.lsig_first_dbeat_reg ; + wire \INCLUDE_PACKING.lsig_first_dbeat_reg_0 ; + wire \INFERRED_GEN.cnt_i[3]_i_2_n_0 ; + wire \INFERRED_GEN.cnt_i[4]_i_3_n_0 ; + wire [4:0]Q; wire [0:0]SR; - wire m_axi_mm2s_aclk; - wire m_axis_fifo_ainit_nosync; - wire m_axis_mm2s_aclk; - wire m_axis_mm2s_tready; - wire mm2s_halt; - wire p_15_out; - wire p_level_in_d1_cdc_from; - wire s_level_out_d1_cdc_to; - wire s_level_out_d2; - wire s_level_out_d3; - wire scndry_reset2; - wire sig_reset_reg_reg; + wire [0:0]SS; + wire [4:0]addr_i_p1; + wire fifo_full_p1; + wire lsig_absorb2tlast; + wire lsig_cmd_fetch_pause; + wire lsig_set_absorb2tlast; + wire m_axi_s2mm_aclk; + wire out; + wire p_7_out; + wire \sig_byte_cntr_reg[0] ; + wire [0:0]\sig_byte_cntr_reg[7] ; + wire sig_clr_dbc_reg; + wire sig_cmd_empty_reg; + wire sig_cmd_full; + wire sig_cmd_full_i_2_n_0; + wire sig_cmd_full_reg; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_dre2ibtt_tlast; + wire sig_eop_halt_xfer; + wire sig_eop_sent; + wire sig_eop_sent_reg; + wire sig_good_tlast_dbeat37_out__0; + wire sig_ibtt2dre_tready; + wire sig_inhibit_rdy_n_reg; + wire sig_last_reg_out_reg; + wire sig_m_valid_out_reg; + wire sig_need_cmd_flush; + wire sig_s_ready_dup4_reg; + wire sig_sm_ld_dre_cmd; + wire sig_sm_pop_cmd_fifo; + wire sig_strm_tlast; + wire sig_wr_fifo; + wire slice_insert_valid; + wire [1:0]\storage_data_reg[3] ; - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to - (.C(m_axis_mm2s_aclk), + LUT6 #( + .INIT(64'h0040000400000040)) + FIFO_Full_i_1__10 + (.I0(FIFO_Full_i_2_n_0), + .I1(Q[3]), + .I2(Q[2]), + .I3(Q[4]), + .I4(\sig_byte_cntr_reg[0] ), + .I5(FIFO_Full_i_3_n_0), + .O(fifo_full_p1)); + LUT6 #( + .INIT(64'hEE7EEEEE77D77777)) + FIFO_Full_i_2 + (.I0(Q[1]), + .I1(Q[0]), + .I2(sig_inhibit_rdy_n_reg), + .I3(FIFO_Full_reg), + .I4(slice_insert_valid), + .I5(\INFERRED_GEN.cnt_i[3]_i_2_n_0 ), + .O(FIFO_Full_i_2_n_0)); + LUT6 #( + .INIT(64'hA8A8EAA8A8A8A8A8)) + FIFO_Full_i_3 + (.I0(\INFERRED_GEN.cnt_i[3]_i_2_n_0 ), + .I1(Q[1]), + .I2(Q[0]), + .I3(slice_insert_valid), + .I4(FIFO_Full_reg), + .I5(sig_inhibit_rdy_n_reg), + .O(FIFO_Full_i_3_n_0)); + LUT6 #( + .INIT(64'h000000C800000000)) + \GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_i_2 + (.I0(\storage_data_reg[3] [1]), + .I1(sig_m_valid_out_reg), + .I2(sig_strm_tlast), + .I3(sig_eop_halt_xfer), + .I4(Q[4]), + .I5(\sig_byte_cntr_reg[0] ), + .O(sig_good_tlast_dbeat37_out__0)); + LUT6 #( + .INIT(64'h00008000FF008000)) + \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_i_1 + (.I0(\sig_byte_cntr_reg[0] ), + .I1(lsig_cmd_fetch_pause), + .I2(sig_last_reg_out_reg), + .I3(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I4(sig_need_cmd_flush), + .I5(sig_sm_pop_cmd_fifo), + .O(\GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg )); + (* SOFT_HLUTNM = "soft_lutpair229" *) + LUT4 #( + .INIT(16'h4F70)) + \INCLUDE_PACKING.lsig_0ffset_cntr[0]_i_1 + (.I0(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1] [0]), + .I1(\INCLUDE_PACKING.lsig_first_dbeat_reg_0 ), + .I2(\sig_byte_cntr_reg[0] ), + .I3(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 [0]), + .O(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] )); + LUT6 #( + .INIT(64'h660FFFFF66F00000)) + \INCLUDE_PACKING.lsig_0ffset_cntr[1]_i_1 + (.I0(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1] [0]), + .I1(\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1] [1]), + .I2(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 [0]), + .I3(\INCLUDE_PACKING.lsig_first_dbeat_reg_0 ), + .I4(\sig_byte_cntr_reg[0] ), + .I5(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 [1]), + .O(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] )); + (* SOFT_HLUTNM = "soft_lutpair229" *) + LUT3 #( + .INIT(8'hD8)) + \INCLUDE_PACKING.lsig_first_dbeat_i_1 + (.I0(\sig_byte_cntr_reg[0] ), + .I1(sig_dre2ibtt_tlast), + .I2(\INCLUDE_PACKING.lsig_first_dbeat_reg_0 ), + .O(\INCLUDE_PACKING.lsig_first_dbeat_reg )); + LUT6 #( + .INIT(64'hBB4BBBBB44B44444)) + \INFERRED_GEN.cnt_i[0]_i_1__10 + (.I0(Q[4]), + .I1(\sig_byte_cntr_reg[0] ), + .I2(slice_insert_valid), + .I3(FIFO_Full_reg), + .I4(sig_inhibit_rdy_n_reg), + .I5(Q[0]), + .O(addr_i_p1[0])); + LUT6 #( + .INIT(64'hAEAAF7FF51550800)) + \INFERRED_GEN.cnt_i[1]_i_1__10 + (.I0(Q[0]), + .I1(slice_insert_valid), + .I2(FIFO_Full_reg), + .I3(sig_inhibit_rdy_n_reg), + .I4(\INFERRED_GEN.cnt_i[3]_i_2_n_0 ), + .I5(Q[1]), + .O(addr_i_p1[1])); + LUT6 #( + .INIT(64'h7F7FFE7F80800180)) + \INFERRED_GEN.cnt_i[2]_i_1__10 + (.I0(sig_wr_fifo), + .I1(Q[0]), + .I2(Q[1]), + .I3(\sig_byte_cntr_reg[0] ), + .I4(Q[4]), + .I5(Q[2]), + .O(addr_i_p1[2])); + LUT6 #( + .INIT(64'hFFFE7FFF00018000)) + \INFERRED_GEN.cnt_i[3]_i_1__1 + (.I0(Q[1]), + .I1(Q[0]), + .I2(sig_wr_fifo), + .I3(Q[2]), + .I4(\INFERRED_GEN.cnt_i[3]_i_2_n_0 ), + .I5(Q[3]), + .O(addr_i_p1[3])); + (* SOFT_HLUTNM = "soft_lutpair227" *) + LUT2 #( + .INIT(4'h2)) + \INFERRED_GEN.cnt_i[3]_i_2 + (.I0(\sig_byte_cntr_reg[0] ), + .I1(Q[4]), + .O(\INFERRED_GEN.cnt_i[3]_i_2_n_0 )); + LUT2 #( + .INIT(4'hB)) + \INFERRED_GEN.cnt_i[4]_i_1 + (.I0(sig_eop_sent_reg), + .I1(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .O(SS)); + LUT6 #( + .INIT(64'h7FFF7FFF00018000)) + \INFERRED_GEN.cnt_i[4]_i_2 + (.I0(Q[2]), + .I1(\INFERRED_GEN.cnt_i[4]_i_3_n_0 ), + .I2(Q[1]), + .I3(Q[3]), + .I4(\sig_byte_cntr_reg[0] ), + .I5(Q[4]), + .O(addr_i_p1[4])); + LUT6 #( + .INIT(64'h2000FF2020002000)) + \INFERRED_GEN.cnt_i[4]_i_3 + (.I0(sig_inhibit_rdy_n_reg), + .I1(FIFO_Full_reg), + .I2(slice_insert_valid), + .I3(Q[0]), + .I4(Q[4]), + .I5(\sig_byte_cntr_reg[0] ), + .O(\INFERRED_GEN.cnt_i[4]_i_3_n_0 )); + FDSE \INFERRED_GEN.cnt_i_reg[0] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(p_level_in_d1_cdc_from), - .Q(s_level_out_d1_cdc_to), - .R(scndry_reset2)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 - (.C(m_axis_mm2s_aclk), + .D(addr_i_p1[0]), + .Q(Q[0]), + .S(SS)); + FDSE \INFERRED_GEN.cnt_i_reg[1] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(s_level_out_d1_cdc_to), - .Q(s_level_out_d2), - .R(scndry_reset2)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 - (.C(m_axis_mm2s_aclk), + .D(addr_i_p1[1]), + .Q(Q[1]), + .S(SS)); + FDSE \INFERRED_GEN.cnt_i_reg[2] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(s_level_out_d2), - .Q(s_level_out_d3), - .R(scndry_reset2)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 - (.C(m_axis_mm2s_aclk), + .D(addr_i_p1[2]), + .Q(Q[2]), + .S(SS)); + FDSE \INFERRED_GEN.cnt_i_reg[3] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(s_level_out_d3), - .Q(sig_reset_reg_reg), - .R(scndry_reset2)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from - (.C(m_axi_mm2s_aclk), + .D(addr_i_p1[3]), + .Q(Q[3]), + .S(SS)); + FDSE \INFERRED_GEN.cnt_i_reg[4] + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(mm2s_halt), - .Q(p_level_in_d1_cdc_from), - .R(SR)); - (* SOFT_HLUTNM = "soft_lutpair34" *) + .D(addr_i_p1[4]), + .Q(Q[4]), + .S(SS)); + LUT3 #( + .INIT(8'h20)) + \INFERRED_GEN.data_reg[15][2]_srl16_i_1 + (.I0(slice_insert_valid), + .I1(FIFO_Full_reg), + .I2(sig_inhibit_rdy_n_reg), + .O(sig_wr_fifo)); + (* SOFT_HLUTNM = "soft_lutpair225" *) + LUT5 #( + .INIT(32'hF222FFFF)) + \sig_btt_cntr[15]_i_1__0 + (.I0(lsig_set_absorb2tlast), + .I1(lsig_absorb2tlast), + .I2(sig_last_reg_out_reg), + .I3(\sig_byte_cntr_reg[0] ), + .I4(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .O(SR)); + (* SOFT_HLUTNM = "soft_lutpair227" *) + LUT4 #( + .INIT(16'h1000)) + \sig_btt_cntr[15]_i_4 + (.I0(Q[4]), + .I1(sig_strm_tlast), + .I2(\storage_data_reg[3] [0]), + .I3(sig_m_valid_out_reg), + .O(lsig_set_absorb2tlast)); + LUT3 #( + .INIT(8'h4F)) + \sig_byte_cntr[7]_i_1 + (.I0(\sig_byte_cntr_reg[0] ), + .I1(sig_clr_dbc_reg), + .I2(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .O(\sig_byte_cntr_reg[7] )); + LUT4 #( + .INIT(16'h0200)) + \sig_byte_cntr[8]_i_2 + (.I0(sig_ibtt2dre_tready), + .I1(Q[4]), + .I2(sig_eop_halt_xfer), + .I3(sig_m_valid_out_reg), + .O(\sig_byte_cntr_reg[0] )); + (* SOFT_HLUTNM = "soft_lutpair228" *) + LUT4 #( + .INIT(16'hFF8A)) + sig_cmd_empty_i_1 + (.I0(p_7_out), + .I1(sig_cmd_full), + .I2(sig_sm_ld_dre_cmd), + .I3(sig_cmd_full_i_2_n_0), + .O(sig_cmd_empty_reg)); + (* SOFT_HLUTNM = "soft_lutpair228" *) + LUT3 #( + .INIT(8'h0E)) + sig_cmd_full_i_1 + (.I0(sig_cmd_full), + .I1(sig_sm_ld_dre_cmd), + .I2(sig_cmd_full_i_2_n_0), + .O(sig_cmd_full_reg)); + LUT6 #( + .INIT(64'hF2222222FFFFFFFF)) + sig_cmd_full_i_2 + (.I0(sig_good_tlast_dbeat37_out__0), + .I1(lsig_set_absorb2tlast), + .I2(sig_strm_tlast), + .I3(sig_m_valid_out_reg), + .I4(lsig_absorb2tlast), + .I5(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .O(sig_cmd_full_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair226" *) + LUT5 #( + .INIT(32'hFF10FFFF)) + \sig_data_reg_out[7]_i_1__3 + (.I0(sig_eop_halt_xfer), + .I1(Q[4]), + .I2(sig_ibtt2dre_tready), + .I3(lsig_absorb2tlast), + .I4(out), + .O(E)); + LUT5 #( + .INIT(32'h11001000)) + sig_dre2ibtt_tlast_reg_i_1 + (.I0(Q[4]), + .I1(sig_eop_halt_xfer), + .I2(sig_strm_tlast), + .I3(sig_m_valid_out_reg), + .I4(\storage_data_reg[3] [1]), + .O(sig_dre2ibtt_tlast)); + (* SOFT_HLUTNM = "soft_lutpair225" *) + LUT4 #( + .INIT(16'h8F88)) + sig_eop_sent_reg_i_1 + (.I0(\sig_byte_cntr_reg[0] ), + .I1(sig_last_reg_out_reg), + .I2(lsig_absorb2tlast), + .I3(lsig_set_absorb2tlast), + .O(sig_eop_sent)); + (* SOFT_HLUTNM = "soft_lutpair226" *) + LUT4 #( + .INIT(16'hAAAE)) + sig_m_valid_dup_i_2__1 + (.I0(lsig_absorb2tlast), + .I1(sig_ibtt2dre_tready), + .I2(Q[4]), + .I3(sig_eop_halt_xfer), + .O(sig_s_ready_dup4_reg)); +endmodule + +(* ORIG_REF_NAME = "dynshreg_f" *) +module Arty_Z7_20_axi_vdma_0_0_dynshreg_f + (sig_calc_error_reg_reg, + sig_wr_fifo, + out, + sig_psm_halt, + sig_input_reg_empty, + Q, + p_10_out, + s_axis_s2mm_cmd_tvalid, + FIFO_Full_reg, + sig_inhibit_rdy_n, + \s_axis_cmd_tdata_reg[63] , + m_axi_s2mm_aclk); + output sig_calc_error_reg_reg; + output sig_wr_fifo; + output [49:0]out; + input sig_psm_halt; + input sig_input_reg_empty; + input [2:0]Q; + input p_10_out; + input s_axis_s2mm_cmd_tvalid; + input FIFO_Full_reg; + input sig_inhibit_rdy_n; + input [48:0]\s_axis_cmd_tdata_reg[63] ; + input m_axi_s2mm_aclk; + + wire FIFO_Full_reg; + wire [2:0]Q; + wire m_axi_s2mm_aclk; + wire [49:0]out; + wire p_10_out; + wire [48:0]\s_axis_cmd_tdata_reg[63] ; + wire s_axis_s2mm_cmd_tvalid; + wire sig_calc_error_reg_i_2__0_n_0; + wire sig_calc_error_reg_i_3__0_n_0; + wire sig_calc_error_reg_i_4__0_n_0; + wire sig_calc_error_reg_i_5__0_n_0; + wire sig_calc_error_reg_reg; + wire sig_inhibit_rdy_n; + wire sig_input_reg_empty; + wire sig_psm_halt; + wire sig_wr_fifo; + + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][0]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][0]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [0]), + .Q(out[0])); + LUT3 #( + .INIT(8'h20)) + \INFERRED_GEN.data_reg[3][0]_srl4_i_1__0 + (.I0(s_axis_s2mm_cmd_tvalid), + .I1(FIFO_Full_reg), + .I2(sig_inhibit_rdy_n), + .O(sig_wr_fifo)); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][10]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][10]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [10]), + .Q(out[10])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][11]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][11]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [11]), + .Q(out[11])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][12]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][12]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [12]), + .Q(out[12])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][13]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][13]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [13]), + .Q(out[13])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][14]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][14]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [14]), + .Q(out[14])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][15]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][15]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [15]), + .Q(out[15])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][1]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][1]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [1]), + .Q(out[1])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][23]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][23]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [16]), + .Q(out[16])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][2]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][2]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [2]), + .Q(out[2])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][30]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][30]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [16]), + .Q(out[17])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][32]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][32]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [17]), + .Q(out[18])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][33]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][33]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [18]), + .Q(out[19])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][34]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][34]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [19]), + .Q(out[20])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][35]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][35]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [20]), + .Q(out[21])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][36]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][36]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [21]), + .Q(out[22])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][37]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][37]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [22]), + .Q(out[23])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][38]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][38]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [23]), + .Q(out[24])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][39]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][39]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [24]), + .Q(out[25])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][3]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][3]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [3]), + .Q(out[3])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][40]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][40]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [25]), + .Q(out[26])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][41]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][41]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [26]), + .Q(out[27])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][42]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][42]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [27]), + .Q(out[28])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][43]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][43]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [28]), + .Q(out[29])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][44]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][44]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [29]), + .Q(out[30])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][45]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][45]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [30]), + .Q(out[31])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][46]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][46]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [31]), + .Q(out[32])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][47]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][47]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [32]), + .Q(out[33])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][48]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][48]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [33]), + .Q(out[34])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][49]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][49]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [34]), + .Q(out[35])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][4]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][4]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [4]), + .Q(out[4])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][50]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][50]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [35]), + .Q(out[36])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][51]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][51]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [36]), + .Q(out[37])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][52]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][52]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [37]), + .Q(out[38])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][53]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][53]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [38]), + .Q(out[39])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][54]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][54]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [39]), + .Q(out[40])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][55]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][55]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [40]), + .Q(out[41])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][56]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][56]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [41]), + .Q(out[42])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][57]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][57]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [42]), + .Q(out[43])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][58]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][58]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [43]), + .Q(out[44])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][59]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][59]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [44]), + .Q(out[45])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][5]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][5]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [5]), + .Q(out[5])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][60]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][60]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [45]), + .Q(out[46])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][61]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][61]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [46]), + .Q(out[47])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][62]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][62]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [47]), + .Q(out[48])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][63]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][63]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [48]), + .Q(out[49])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][6]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][6]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [6]), + .Q(out[6])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][7]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][7]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [7]), + .Q(out[7])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][8]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][8]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [8]), + .Q(out[8])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][9]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][9]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(\s_axis_cmd_tdata_reg[63] [9]), + .Q(out[9])); + LUT6 #( + .INIT(64'hFFFFFFFF00000100)) + sig_calc_error_reg_i_1__0 + (.I0(sig_calc_error_reg_i_2__0_n_0), + .I1(sig_calc_error_reg_i_3__0_n_0), + .I2(sig_psm_halt), + .I3(sig_input_reg_empty), + .I4(Q[2]), + .I5(p_10_out), + .O(sig_calc_error_reg_reg)); + LUT5 #( + .INIT(32'hFFFFFFFE)) + sig_calc_error_reg_i_2__0 + (.I0(out[13]), + .I1(out[12]), + .I2(out[14]), + .I3(out[15]), + .I4(sig_calc_error_reg_i_4__0_n_0), + .O(sig_calc_error_reg_i_2__0_n_0)); + LUT5 #( + .INIT(32'hFFFFFFFE)) + sig_calc_error_reg_i_3__0 + (.I0(out[5]), + .I1(out[4]), + .I2(out[7]), + .I3(out[6]), + .I4(sig_calc_error_reg_i_5__0_n_0), + .O(sig_calc_error_reg_i_3__0_n_0)); LUT4 #( - .INIT(16'h0020)) - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tready_d1_i_1 - (.I0(m_axis_mm2s_tready), - .I1(sig_reset_reg_reg), - .I2(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ), - .I3(p_15_out), - .O(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tready_d1_reg )); - (* SOFT_HLUTNM = "soft_lutpair34" *) - LUT2 #( - .INIT(4'hB)) - \sig_data_reg_out[31]_i_1 - (.I0(sig_reset_reg_reg), - .I1(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0 ), - .O(m_axis_fifo_ainit_nosync)); -endmodule - -(* ORIG_REF_NAME = "cdc_sync" *) -module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized2 - (scndry_out, - m_axis_mm2s_aclk, - \FSM_sequential_dmacntrl_cs_reg[1] , - m_axi_mm2s_aclk); - output scndry_out; - input m_axis_mm2s_aclk; - input \FSM_sequential_dmacntrl_cs_reg[1] ; - input m_axi_mm2s_aclk; - - wire \FSM_sequential_dmacntrl_cs_reg[1] ; - wire m_axi_mm2s_aclk; - wire m_axis_mm2s_aclk; - wire p_level_in_d1_cdc_from; - wire s_level_out_d1_cdc_to; - wire s_level_out_d2; - wire s_level_out_d3; - wire scndry_out; - - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(p_level_in_d1_cdc_from), - .Q(s_level_out_d1_cdc_to), - .R(1'b0)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(s_level_out_d1_cdc_to), - .Q(s_level_out_d2), - .R(1'b0)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(s_level_out_d2), - .Q(s_level_out_d3), - .R(1'b0)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(s_level_out_d3), - .Q(scndry_out), - .R(1'b0)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(\FSM_sequential_dmacntrl_cs_reg[1] ), - .Q(p_level_in_d1_cdc_from), - .R(1'b0)); -endmodule - -(* ORIG_REF_NAME = "cdc_sync" *) -module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized3 - (scndry_out, - m_axi_mm2s_aclk, - axis_min_assert_sftrst, - m_axis_mm2s_aclk); - output scndry_out; - input m_axi_mm2s_aclk; - input axis_min_assert_sftrst; - input m_axis_mm2s_aclk; - - wire axis_min_assert_sftrst; - wire m_axi_mm2s_aclk; - wire m_axis_mm2s_aclk; - wire p_level_in_d1_cdc_from; - wire s_level_out_d1_cdc_to; - wire s_level_out_d2; - wire s_level_out_d3; - wire scndry_out; - - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(p_level_in_d1_cdc_from), - .Q(s_level_out_d1_cdc_to), - .R(1'b0)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(s_level_out_d1_cdc_to), - .Q(s_level_out_d2), - .R(1'b0)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(s_level_out_d2), - .Q(s_level_out_d3), - .R(1'b0)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(s_level_out_d3), - .Q(scndry_out), - .R(1'b0)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(axis_min_assert_sftrst), - .Q(p_level_in_d1_cdc_from), - .R(1'b0)); + .INIT(16'hFFFE)) + sig_calc_error_reg_i_4__0 + (.I0(out[10]), + .I1(out[11]), + .I2(out[8]), + .I3(out[9]), + .O(sig_calc_error_reg_i_4__0_n_0)); + LUT4 #( + .INIT(16'hFFFE)) + sig_calc_error_reg_i_5__0 + (.I0(out[2]), + .I1(out[3]), + .I2(out[0]), + .I3(out[1]), + .O(sig_calc_error_reg_i_5__0_n_0)); endmodule -(* ORIG_REF_NAME = "cdc_sync" *) -module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized4 - (prmry_reset2, - prmry_in, - run_stop_d1_reg, - halt_i_reg, - \dmacr_i_reg[2] , - sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0, - reset_counts_reg, - min_assert_sftrst, - s_soft_reset_i, - p_68_out, - p_35_out, - halt_i_reg_0, - halt_reset_reg, - halt_i0, - mm2s_axi2ip_wrce, - D, - assert_sftrst_d1, - reset_counts, +(* ORIG_REF_NAME = "dynshreg_f" *) +module Arty_Z7_20_axi_vdma_0_0_dynshreg_f_26 + (sig_calc_error_reg_reg, + sig_wr_fifo, out, - m_axi_mm2s_aclk, - hrd_resetn_i_reg, - s_axi_lite_aclk); - output prmry_reset2; - output prmry_in; - output run_stop_d1_reg; - output halt_i_reg; - output \dmacr_i_reg[2] ; - output sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0; - output reset_counts_reg; - input min_assert_sftrst; - input s_soft_reset_i; - input [1:0]p_68_out; - input p_35_out; - input halt_i_reg_0; - input halt_reset_reg; - input halt_i0; - input [0:0]mm2s_axi2ip_wrce; - input [0:0]D; - input assert_sftrst_d1; - input reset_counts; - input out; + in, + sig_sm_halt_reg, + sig_input_reg_empty, + Q, + p_56_out, + FIFO_Full_reg, + sig_inhibit_rdy_n, + \s_axis_cmd_tdata_reg[63] , + m_axi_mm2s_aclk); + output sig_calc_error_reg_reg; + output sig_wr_fifo; + output [49:0]out; + input [0:0]in; + input sig_sm_halt_reg; + input sig_input_reg_empty; + input [2:0]Q; + input p_56_out; + input FIFO_Full_reg; + input sig_inhibit_rdy_n; + input [48:0]\s_axis_cmd_tdata_reg[63] ; input m_axi_mm2s_aclk; - input hrd_resetn_i_reg; - input s_axi_lite_aclk; - wire [0:0]D; - wire assert_sftrst_d1; - wire \dmacr_i_reg[2] ; - wire halt_i0; - wire halt_i_reg; - wire halt_i_reg_0; - wire halt_reset_reg; - wire hrd_resetn_i_reg; + wire FIFO_Full_reg; + wire [2:0]Q; + wire [0:0]in; wire m_axi_mm2s_aclk; - wire min_assert_sftrst; - wire [0:0]mm2s_axi2ip_wrce; - wire mm2s_hrd_resetn; - wire out; - wire p_35_out; - wire [1:0]p_68_out; - wire p_level_in_d1_cdc_from; - wire prmry_in; - wire prmry_reset2; - wire reset_counts; - wire reset_counts_reg; - wire run_stop_d1_reg; - wire s_axi_lite_aclk; - wire s_level_out_d1_cdc_to; - wire s_level_out_d2; - wire s_level_out_d3; - wire s_soft_reset_i; - wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0; + wire [49:0]out; + wire p_56_out; + wire [48:0]\s_axis_cmd_tdata_reg[63] ; + wire sig_calc_error_reg_i_2_n_0; + wire sig_calc_error_reg_i_3_n_0; + wire sig_calc_error_reg_i_4_n_0; + wire sig_calc_error_reg_i_5_n_0; + wire sig_calc_error_reg_reg; + wire sig_inhibit_rdy_n; + wire sig_input_reg_empty; + wire sig_sm_halt_reg; + wire sig_wr_fifo; - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(p_level_in_d1_cdc_from), - .Q(s_level_out_d1_cdc_to), - .R(1'b0)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(s_level_out_d1_cdc_to), - .Q(s_level_out_d2), - .R(1'b0)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(s_level_out_d2), - .Q(s_level_out_d3), - .R(1'b0)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(s_level_out_d3), - .Q(mm2s_hrd_resetn), - .R(1'b0)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(hrd_resetn_i_reg), - .Q(p_level_in_d1_cdc_from), - .R(1'b0)); - (* SOFT_HLUTNM = "soft_lutpair114" *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][0]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][0]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [0]), + .Q(out[0])); LUT3 #( - .INIT(8'h02)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_1__0 - (.I0(mm2s_hrd_resetn), - .I1(min_assert_sftrst), - .I2(s_soft_reset_i), - .O(prmry_in)); - LUT1 #( - .INIT(2'h1)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to_i_1 - (.I0(mm2s_hrd_resetn), - .O(prmry_reset2)); + .INIT(8'h20)) + \INFERRED_GEN.data_reg[3][0]_srl4_i_1 + (.I0(p_56_out), + .I1(FIFO_Full_reg), + .I2(sig_inhibit_rdy_n), + .O(sig_wr_fifo)); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][10]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][10]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [10]), + .Q(out[10])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][11]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][11]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [11]), + .Q(out[11])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][12]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][12]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [12]), + .Q(out[12])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][13]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][13]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [13]), + .Q(out[13])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][14]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][14]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [14]), + .Q(out[14])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][15]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][15]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [15]), + .Q(out[15])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][1]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][1]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [1]), + .Q(out[1])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][23]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][23]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [16]), + .Q(out[16])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][2]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][2]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [2]), + .Q(out[2])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][30]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][30]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [16]), + .Q(out[17])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][32]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][32]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [17]), + .Q(out[18])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][33]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][33]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [18]), + .Q(out[19])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][34]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][34]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [19]), + .Q(out[20])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][35]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][35]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [20]), + .Q(out[21])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][36]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][36]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [21]), + .Q(out[22])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][37]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][37]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [22]), + .Q(out[23])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][38]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][38]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [23]), + .Q(out[24])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][39]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][39]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [24]), + .Q(out[25])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][3]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][3]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [3]), + .Q(out[3])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][40]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][40]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [25]), + .Q(out[26])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][41]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][41]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [26]), + .Q(out[27])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][42]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][42]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [27]), + .Q(out[28])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][43]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][43]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [28]), + .Q(out[29])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][44]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][44]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [29]), + .Q(out[30])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][45]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][45]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [30]), + .Q(out[31])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][46]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][46]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [31]), + .Q(out[32])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][47]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][47]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [32]), + .Q(out[33])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][48]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][48]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [33]), + .Q(out[34])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][49]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][49]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [34]), + .Q(out[35])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][4]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][4]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [4]), + .Q(out[4])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][50]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][50]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [35]), + .Q(out[36])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][51]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][51]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [36]), + .Q(out[37])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][52]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][52]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [37]), + .Q(out[38])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][53]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][53]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [38]), + .Q(out[39])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][54]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][54]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [39]), + .Q(out[40])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][55]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][55]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [40]), + .Q(out[41])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][56]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][56]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [41]), + .Q(out[42])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][57]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][57]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [42]), + .Q(out[43])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][58]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][58]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [43]), + .Q(out[44])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][59]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][59]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [44]), + .Q(out[45])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][5]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][5]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [5]), + .Q(out[5])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][60]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][60]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [45]), + .Q(out[46])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][61]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][61]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [46]), + .Q(out[47])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][62]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][62]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [47]), + .Q(out[48])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][63]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][63]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [48]), + .Q(out[49])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][6]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][6]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [6]), + .Q(out[6])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][7]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][7]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [7]), + .Q(out[7])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][8]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][8]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [8]), + .Q(out[8])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][9]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][9]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(\s_axis_cmd_tdata_reg[63] [9]), + .Q(out[9])); LUT6 #( - .INIT(64'hEA00EAEA00000000)) - \dmacr_i[2]_i_1 - (.I0(p_68_out[1]), - .I1(mm2s_axi2ip_wrce), - .I2(D), - .I3(min_assert_sftrst), - .I4(assert_sftrst_d1), - .I5(mm2s_hrd_resetn), - .O(\dmacr_i_reg[2] )); + .INIT(64'hF0F0F0F0F0F2F0F0)) + sig_calc_error_reg_i_1 + (.I0(sig_calc_error_reg_i_2_n_0), + .I1(sig_calc_error_reg_i_3_n_0), + .I2(in), + .I3(sig_sm_halt_reg), + .I4(sig_input_reg_empty), + .I5(Q[2]), + .O(sig_calc_error_reg_reg)); LUT5 #( - .INIT(32'hAAAA0888)) - halt_i_i_1 - (.I0(prmry_in), - .I1(halt_i_reg_0), - .I2(halt_reset_reg), - .I3(p_68_out[0]), - .I4(halt_i0), - .O(halt_i_reg)); - LUT6 #( - .INIT(64'hAE00AEAE00000000)) - reset_counts_i_1 - (.I0(reset_counts), - .I1(p_68_out[1]), - .I2(out), - .I3(min_assert_sftrst), - .I4(assert_sftrst_d1), - .I5(mm2s_hrd_resetn), - .O(reset_counts_reg)); - LUT6 #( - .INIT(64'h0000000000000200)) - run_stop_d1_i_1 - (.I0(p_68_out[0]), - .I1(p_35_out), - .I2(p_68_out[1]), - .I3(mm2s_hrd_resetn), - .I4(min_assert_sftrst), - .I5(s_soft_reset_i), - .O(run_stop_d1_reg)); - (* SOFT_HLUTNM = "soft_lutpair114" *) + .INIT(32'h00000001)) + sig_calc_error_reg_i_2 + (.I0(out[8]), + .I1(out[11]), + .I2(out[9]), + .I3(out[10]), + .I4(sig_calc_error_reg_i_4_n_0), + .O(sig_calc_error_reg_i_2_n_0)); + LUT5 #( + .INIT(32'hFFFFFFFE)) + sig_calc_error_reg_i_3 + (.I0(out[0]), + .I1(out[3]), + .I2(out[1]), + .I3(out[2]), + .I4(sig_calc_error_reg_i_5_n_0), + .O(sig_calc_error_reg_i_3_n_0)); LUT4 #( - .INIT(16'h0010)) - sig_mm2s_dm_prmry_resetn_inferred_i_1 - (.I0(s_soft_reset_i), - .I1(min_assert_sftrst), - .I2(mm2s_hrd_resetn), - .I3(halt_reset_reg), - .O(sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0)); + .INIT(16'hFFFE)) + sig_calc_error_reg_i_4 + (.I0(out[13]), + .I1(out[12]), + .I2(out[15]), + .I3(out[14]), + .O(sig_calc_error_reg_i_4_n_0)); + LUT4 #( + .INIT(16'hFFFE)) + sig_calc_error_reg_i_5 + (.I0(out[5]), + .I1(out[4]), + .I2(out[7]), + .I3(out[6]), + .O(sig_calc_error_reg_i_5_n_0)); endmodule -(* ORIG_REF_NAME = "cdc_sync" *) -module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized5 - (scndry_out, - m_axis_mm2s_aclk, - prmry_in, +(* ORIG_REF_NAME = "dynshreg_f" *) +module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized0 + (decerr_i_reg, + slverr_i_reg, + interr_i_reg, + sig_wr_fifo, + Q, + sig_rsc2stat_status_valid, + FIFO_Full_reg, + sig_inhibit_rdy_n_reg, + sig_rd_sts_slverr_reg_reg, m_axi_mm2s_aclk); - output scndry_out; - input m_axis_mm2s_aclk; - input prmry_in; - input m_axi_mm2s_aclk; - - wire m_axi_mm2s_aclk; - wire m_axis_mm2s_aclk; - wire p_level_in_d1_cdc_from; - wire prmry_in; - wire s_level_out_d1_cdc_to; - wire s_level_out_d2; - wire s_level_out_d3; - wire scndry_out; - - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(p_level_in_d1_cdc_from), - .Q(s_level_out_d1_cdc_to), - .R(1'b0)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(s_level_out_d1_cdc_to), - .Q(s_level_out_d2), - .R(1'b0)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(s_level_out_d2), - .Q(s_level_out_d3), - .R(1'b0)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 - (.C(m_axis_mm2s_aclk), - .CE(1'b1), - .D(s_level_out_d3), - .Q(scndry_out), - .R(1'b0)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(prmry_in), - .Q(p_level_in_d1_cdc_from), - .R(1'b0)); -endmodule - -(* ORIG_REF_NAME = "cdc_sync" *) -module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized6 - (\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg , - \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[16] , - \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg , - mm2s_axi2ip_wrce, - \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] , - prmtr_updt_complete_i_reg, - ioc_irq_reg, - dly_irq_reg, - SR, - s_axi_lite_aclk, - prmry_reset2, - m_axi_mm2s_aclk, - different_delay, - different_thresh, - out, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[6] , - prmry_resetn_i_reg, - threshold_is_zero, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[4] , - p_68_out, - prepare_wrce_d1, - lite_wr_addr_phase_finished_data_phase_started, - wvalid, - D, - mm2s_ioc_irq_set, - ioc_irq_reg_0, - mm2s_dly_irq_set, - dly_irq_reg_0); - output \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg ; - output \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[16] ; - output \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg ; - output [5:0]mm2s_axi2ip_wrce; - output [0:0]\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] ; - output prmtr_updt_complete_i_reg; - output ioc_irq_reg; - output dly_irq_reg; - input [0:0]SR; - input s_axi_lite_aclk; - input prmry_reset2; + output decerr_i_reg; + output slverr_i_reg; + output interr_i_reg; + output sig_wr_fifo; + input [2:0]Q; + input sig_rsc2stat_status_valid; + input FIFO_Full_reg; + input sig_inhibit_rdy_n_reg; + input [2:0]sig_rd_sts_slverr_reg_reg; input m_axi_mm2s_aclk; - input different_delay; - input different_thresh; - input [5:0]out; - input \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[6] ; - input prmry_resetn_i_reg; - input threshold_is_zero; - input \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[4] ; - input [0:0]p_68_out; - input prepare_wrce_d1; - input lite_wr_addr_phase_finished_data_phase_started; - input wvalid; - input [1:0]D; - input mm2s_ioc_irq_set; - input ioc_irq_reg_0; - input mm2s_dly_irq_set; - input dly_irq_reg_0; - wire [1:0]D; - wire \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg ; - wire \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[16] ; - wire [0:0]\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] ; - wire \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[4] ; - wire \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[6] ; - wire [0:0]SR; - wire different_delay; - wire different_thresh; - wire dly_irq_reg; - wire dly_irq_reg_0; - wire ioc_irq_reg; - wire ioc_irq_reg_0; - wire lite_wr_addr_phase_finished_data_phase_started; + wire FIFO_Full_reg; + wire [2:0]Q; + wire decerr_i_reg; + wire interr_i_reg; wire m_axi_mm2s_aclk; - wire [5:0]mm2s_axi2ip_wrce; - wire mm2s_dly_irq_set; - wire mm2s_ioc_irq_set; - wire [5:0]out; - wire p_0_out; - wire [0:0]p_68_out; - wire p_in_d1_cdc_from; - wire prepare_wrce_d1; - wire prmry_in_xored; - wire prmry_reset2; - wire prmry_resetn_i_reg; - wire prmtr_updt_complete_i_reg; - wire \ptr_ref_i[4]_i_2_n_0 ; - wire \reg_module_vsize[12]_i_2_n_0 ; - wire s_axi_lite_aclk; - wire s_out_d1_cdc_to; - wire s_out_d2; - wire s_out_d3; - wire s_out_d4; - wire s_out_d5; - wire s_out_re__0; - wire srst_d1; - wire srst_d2; - wire srst_d3; - wire srst_d4; - wire srst_d5; - wire threshold_is_zero; - wire wvalid; + wire [6:4]m_axis_mm2s_sts_tdata; + wire sig_inhibit_rdy_n_reg; + wire [2:0]sig_rd_sts_slverr_reg_reg; + wire sig_rsc2stat_status_valid; + wire sig_wr_fifo; + wire slverr_i_reg; - (* SOFT_HLUTNM = "soft_lutpair2" *) - LUT2 #( - .INIT(4'h8)) - \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_1 - (.I0(\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[16] ), - .I1(different_delay), - .O(\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg )); - (* SOFT_HLUTNM = "soft_lutpair1" *) - LUT3 #( - .INIT(8'hD5)) - \ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_1 - (.I0(prmry_resetn_i_reg), - .I1(\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[16] ), - .I2(threshold_is_zero), - .O(\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21] )); - (* SOFT_HLUTNM = "soft_lutpair2" *) - LUT2 #( - .INIT(4'h8)) - \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_1 - (.I0(\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[16] ), - .I1(different_thresh), - .O(\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg )); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2 - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(s_out_d1_cdc_to), - .Q(s_out_d2), - .R(prmry_reset2)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3 - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(s_out_d2), - .Q(s_out_d3), - .R(prmry_reset2)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4 - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(s_out_d3), - .Q(s_out_d4), - .R(prmry_reset2)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5 - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(s_out_d4), - .Q(s_out_d5), - .R(prmry_reset2)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(s_out_re__0), - .Q(p_0_out), - .R(prmry_reset2)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(p_in_d1_cdc_from), - .Q(s_out_d1_cdc_to), - .R(prmry_reset2)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(prmry_in_xored), - .Q(p_in_d1_cdc_from), - .R(SR)); - LUT4 #( - .INIT(16'hBF40)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__3 - (.I0(prepare_wrce_d1), - .I1(lite_wr_addr_phase_finished_data_phase_started), - .I2(wvalid), - .I3(p_in_d1_cdc_from), - .O(prmry_in_xored)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1 - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(1'b1), - .Q(srst_d1), - .R(prmry_reset2)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2 - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(srst_d1), - .Q(srst_d2), - .R(prmry_reset2)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3 - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(srst_d2), - .Q(srst_d3), - .R(prmry_reset2)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4 - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(srst_d3), - .Q(srst_d4), - .R(prmry_reset2)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5 - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(srst_d4), - .Q(srst_d5), - .R(prmry_reset2)); - LUT4 #( - .INIT(16'h0004)) - \GEN_NUM_FSTORES_1.reg_module_start_address1_i[31]_i_1 - (.I0(out[3]), - .I1(p_0_out), - .I2(out[5]), - .I3(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[4] ), - .O(mm2s_axi2ip_wrce[5])); - LUT4 #( - .INIT(16'hF7F0)) - \I_DMA_REGISTER/dly_irq_i_1 - (.I0(D[1]), - .I1(mm2s_axi2ip_wrce[0]), - .I2(mm2s_dly_irq_set), - .I3(dly_irq_reg_0), - .O(dly_irq_reg)); - LUT4 #( - .INIT(16'hF7F0)) - \I_DMA_REGISTER/ioc_irq_i_1 - (.I0(D[0]), - .I1(mm2s_axi2ip_wrce[0]), - .I2(mm2s_ioc_irq_set), - .I3(ioc_irq_reg_0), - .O(ioc_irq_reg)); - LUT6 #( - .INIT(64'h0100000000000000)) - \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid[15]_i_1 - (.I0(out[3]), - .I1(out[0]), - .I2(out[5]), - .I3(out[1]), - .I4(out[4]), - .I5(\reg_module_vsize[12]_i_2_n_0 ), - .O(mm2s_axi2ip_wrce[4])); - LUT6 #( - .INIT(64'h0000100000000000)) - dma_interr_i_2 - (.I0(out[5]), - .I1(out[1]), - .I2(out[0]), - .I3(p_0_out), - .I4(out[2]), - .I5(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[6] ), - .O(mm2s_axi2ip_wrce[0])); - LUT6 #( - .INIT(64'h0000001000000000)) - \dmacr_i[1]_i_1 - (.I0(out[5]), - .I1(out[0]), - .I2(p_0_out), - .I3(out[2]), - .I4(out[1]), - .I5(\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[6] ), - .O(\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[16] )); - (* SOFT_HLUTNM = "soft_lutpair1" *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][4]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][4]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(sig_rd_sts_slverr_reg_reg[0]), + .Q(m_axis_mm2s_sts_tdata[4])); LUT3 #( - .INIT(8'h80)) - prmtr_updt_complete_i_i_1 - (.I0(mm2s_axi2ip_wrce[2]), - .I1(prmry_resetn_i_reg), - .I2(p_68_out), - .O(prmtr_updt_complete_i_reg)); - LUT4 #( - .INIT(16'h0010)) - \ptr_ref_i[4]_i_1 - (.I0(out[5]), - .I1(out[2]), - .I2(out[3]), - .I3(\ptr_ref_i[4]_i_2_n_0 ), - .O(mm2s_axi2ip_wrce[1])); - (* SOFT_HLUTNM = "soft_lutpair0" *) - LUT4 #( - .INIT(16'hEFFF)) - \ptr_ref_i[4]_i_2 - (.I0(out[0]), - .I1(out[4]), - .I2(out[1]), - .I3(p_0_out), - .O(\ptr_ref_i[4]_i_2_n_0 )); - LUT6 #( - .INIT(64'h0100000000000000)) - \reg_module_hsize[15]_i_1 - (.I0(out[3]), - .I1(out[1]), - .I2(out[5]), - .I3(out[4]), - .I4(out[0]), - .I5(\reg_module_vsize[12]_i_2_n_0 ), - .O(mm2s_axi2ip_wrce[3])); - LUT6 #( - .INIT(64'h0000000000001000)) - \reg_module_vsize[12]_i_1 - (.I0(out[5]), - .I1(out[1]), - .I2(out[4]), - .I3(\reg_module_vsize[12]_i_2_n_0 ), - .I4(out[0]), - .I5(out[3]), - .O(mm2s_axi2ip_wrce[2])); - (* SOFT_HLUTNM = "soft_lutpair0" *) + .INIT(8'h20)) + \INFERRED_GEN.data_reg[3][4]_srl4_i_1__0 + (.I0(sig_rsc2stat_status_valid), + .I1(FIFO_Full_reg), + .I2(sig_inhibit_rdy_n_reg), + .O(sig_wr_fifo)); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][5]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][5]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(sig_rd_sts_slverr_reg_reg[1]), + .Q(m_axis_mm2s_sts_tdata[5])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][6]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][6]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_mm2s_aclk), + .D(sig_rd_sts_slverr_reg_reg[2]), + .Q(m_axis_mm2s_sts_tdata[6])); + (* SOFT_HLUTNM = "soft_lutpair131" *) LUT2 #( - .INIT(4'h8)) - \reg_module_vsize[12]_i_2 - (.I0(p_0_out), - .I1(out[2]), - .O(\reg_module_vsize[12]_i_2_n_0 )); + .INIT(4'h2)) + decerr_i_i_1 + (.I0(m_axis_mm2s_sts_tdata[5]), + .I1(Q[2]), + .O(decerr_i_reg)); + LUT2 #( + .INIT(4'h2)) + interr_i_i_1 + (.I0(m_axis_mm2s_sts_tdata[4]), + .I1(Q[2]), + .O(interr_i_reg)); + (* SOFT_HLUTNM = "soft_lutpair131" *) + LUT2 #( + .INIT(4'h2)) + slverr_i_i_1 + (.I0(m_axis_mm2s_sts_tdata[6]), + .I1(Q[2]), + .O(slverr_i_reg)); +endmodule + +(* ORIG_REF_NAME = "dynshreg_f" *) +module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 + (sig_addr_valid_reg_reg, + out, + sig_calc_error_reg_reg, + FIFO_Full_reg, + sig_inhibit_rdy_n, + sig_mstr2addr_cmd_valid, + in, + Q, + m_axi_mm2s_aclk); + output sig_addr_valid_reg_reg; + output [40:0]out; + output sig_calc_error_reg_reg; + input FIFO_Full_reg; + input sig_inhibit_rdy_n; + input sig_mstr2addr_cmd_valid; + input [38:0]in; + input [1:0]Q; + input m_axi_mm2s_aclk; + + wire FIFO_Full_reg; + wire [1:0]Q; + wire [38:0]in; + wire m_axi_mm2s_aclk; + wire [40:0]out; + wire sig_addr_valid_reg_reg; + wire sig_calc_error_reg_reg; + wire sig_inhibit_rdy_n; + wire sig_mstr2addr_cmd_valid; + + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][10]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][10]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[6]), + .Q(out[6])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][11]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][11]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[7]), + .Q(out[7])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][12]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][12]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[8]), + .Q(out[8])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][13]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][13]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[9]), + .Q(out[9])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][14]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][14]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[10]), + .Q(out[10])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][15]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][15]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[11]), + .Q(out[11])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][16]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][16]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[12]), + .Q(out[12])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][17]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][17]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[13]), + .Q(out[13])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][18]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][18]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[14]), + .Q(out[14])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][19]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][19]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[15]), + .Q(out[15])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][20]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][20]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[16]), + .Q(out[16])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][21]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][21]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[17]), + .Q(out[17])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][22]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][22]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[18]), + .Q(out[18])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][23]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][23]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[19]), + .Q(out[19])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][24]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][24]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[20]), + .Q(out[20])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][25]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][25]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[21]), + .Q(out[21])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][26]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][26]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[22]), + .Q(out[22])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][27]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][27]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[23]), + .Q(out[23])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][28]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][28]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[24]), + .Q(out[24])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][29]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][29]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[25]), + .Q(out[25])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][30]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][30]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[26]), + .Q(out[26])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][31]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][31]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[27]), + .Q(out[27])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][32]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][32]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[28]), + .Q(out[28])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][33]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][33]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[29]), + .Q(out[29])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][34]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][34]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[30]), + .Q(out[30])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][35]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][35]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[31]), + .Q(out[31])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][36]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][36]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[32]), + .Q(out[32])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][37]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][37]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[33]), + .Q(out[33])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][38]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][38]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[34]), + .Q(out[34])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][39]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][39]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[35]), + .Q(out[35])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][40]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][40]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[36]), + .Q(out[36])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][44]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][44]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(1'b1), + .Q(out[37])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][45]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][45]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(1'b1), + .Q(out[38])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][47]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][47]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[37]), + .Q(out[39])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][4]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][4]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[0]), + .Q(out[0])); LUT3 #( - .INIT(8'h28)) - s_out_re - (.I0(srst_d5), - .I1(s_out_d5), - .I2(s_out_d4), - .O(s_out_re__0)); -endmodule - -(* ORIG_REF_NAME = "cdc_sync" *) -module Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized7 - (mm2s_introut, - SR, - s_axi_lite_aclk, - prmry_reset2, - p_75_out, - m_axi_mm2s_aclk); - output mm2s_introut; - input [0:0]SR; - input s_axi_lite_aclk; - input prmry_reset2; - input p_75_out; - input m_axi_mm2s_aclk; - - wire [0:0]SR; - wire m_axi_mm2s_aclk; - wire mm2s_introut; - wire p_75_out; - wire p_level_in_d1_cdc_from; - wire prmry_reset2; - wire s_axi_lite_aclk; - wire s_level_out_d1_cdc_to; - wire s_level_out_d2; - - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(p_level_in_d1_cdc_from), - .Q(s_level_out_d1_cdc_to), - .R(SR)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_level_out_d1_cdc_to), - .Q(s_level_out_d2), - .R(SR)); - (* ASYNC_REG *) - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 - (.C(s_axi_lite_aclk), - .CE(1'b1), - .D(s_level_out_d2), - .Q(mm2s_introut), - .R(SR)); - (* XILINX_LEGACY_PRIM = "FDR" *) - (* box_type = "PRIMITIVE" *) - FDRE #( - .INIT(1'b0)) - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(p_75_out), - .Q(p_level_in_d1_cdc_from), - .R(prmry_reset2)); + .INIT(8'h40)) + \INFERRED_GEN.data_reg[3][4]_srl4_i_1 + (.I0(FIFO_Full_reg), + .I1(sig_inhibit_rdy_n), + .I2(sig_mstr2addr_cmd_valid), + .O(sig_calc_error_reg_reg)); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][50]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][50]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[38]), + .Q(out[40])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][5]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][5]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[1]), + .Q(out[1])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][6]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][6]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[2]), + .Q(out[2])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][7]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][7]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[3]), + .Q(out[3])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][8]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][8]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[4]), + .Q(out[4])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][9]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][9]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[5]), + .Q(out[5])); + LUT1 #( + .INIT(2'h1)) + sig_addr_valid_reg_i_1 + (.I0(out[40]), + .O(sig_addr_valid_reg_reg)); endmodule -(* ORIG_REF_NAME = "cntr_incr_decr_addn_f" *) -module Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f - (fifo_full_p1, - sig_dqual_reg_empty_reg, - Q, - E, - sig_dqual_reg_empty_reg_0, - sig_ld_new_cmd_reg_reg, - sig_next_cmd_cmplt_reg_reg, +(* ORIG_REF_NAME = "dynshreg_f" *) +module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized10 + (sig_last_dbeat_reg, + sig_wr_fifo, D, - sig_cmd2data_valid_reg, - sig_mstr2data_cmd_valid, - FIFO_Full_reg, - sig_inhibit_rdy_n_0, - \sig_dbeat_cntr_reg[2] , - sig_next_sequential_reg, - sig_last_dbeat, - sig_dqual_reg_empty, - m_axi_mm2s_rvalid, - sig_halt_reg_reg, - ram_full_i_reg, - sig_advance_pipe9_out__1, - sig_rsc2stat_status_valid, - FIFO_Full_reg_0, - sig_inhibit_rdy_n, - sig_next_calc_error_reg, - sig_addr_posted_cntr, + out, + sig_first_dbeat1__0, + sig_next_sequential_reg_reg, sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_ld_new_cmd_reg, - sig_dqual_reg_full, - m_axi_mm2s_rlast, - \sig_dbeat_cntr_reg[7] , - \sig_dbeat_cntr_reg[3] , - \sig_dbeat_cntr_reg[4] , - SR, - m_axi_mm2s_aclk); - output fifo_full_p1; - output sig_dqual_reg_empty_reg; - output [1:0]Q; - output [0:0]E; - output sig_dqual_reg_empty_reg_0; - output sig_ld_new_cmd_reg_reg; - output sig_next_cmd_cmplt_reg_reg; - output [3:0]D; - input sig_cmd2data_valid_reg; - input sig_mstr2data_cmd_valid; - input FIFO_Full_reg; - input sig_inhibit_rdy_n_0; - input \sig_dbeat_cntr_reg[2] ; - input sig_next_sequential_reg; - input sig_last_dbeat; - input sig_dqual_reg_empty; - input m_axi_mm2s_rvalid; - input sig_halt_reg_reg; - input ram_full_i_reg; - input sig_advance_pipe9_out__1; - input sig_rsc2stat_status_valid; - input FIFO_Full_reg_0; - input sig_inhibit_rdy_n; - input sig_next_calc_error_reg; - input [2:0]sig_addr_posted_cntr; - input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - input sig_ld_new_cmd_reg; - input sig_dqual_reg_full; - input m_axi_mm2s_rlast; - input [7:0]\sig_dbeat_cntr_reg[7] ; - input \sig_dbeat_cntr_reg[3] ; - input \sig_dbeat_cntr_reg[4] ; - input [0:0]SR; - input m_axi_mm2s_aclk; - - wire [3:0]D; - wire [0:0]E; - wire FIFO_Full_reg; - wire FIFO_Full_reg_0; - wire [1:0]Q; - wire [0:0]SR; - wire [2:0]addr_i_p1; - wire fifo_full_p1; - wire m_axi_mm2s_aclk; - wire m_axi_mm2s_rlast; - wire m_axi_mm2s_rvalid; - wire ram_full_i_reg; - wire [2:0]sig_addr_posted_cntr; - wire sig_addr_posted_cntr_max__1; - wire sig_advance_pipe9_out__1; - wire sig_cmd2data_valid_reg; - wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - wire \sig_dbeat_cntr_reg[2] ; - wire \sig_dbeat_cntr_reg[3] ; - wire \sig_dbeat_cntr_reg[4] ; - wire [7:0]\sig_dbeat_cntr_reg[7] ; - wire sig_dqual_reg_empty; - wire sig_dqual_reg_empty_reg; - wire sig_dqual_reg_empty_reg_0; - wire sig_dqual_reg_full; - wire sig_halt_reg_reg; - wire sig_inhibit_rdy_n; - wire sig_inhibit_rdy_n_0; - wire sig_last_dbeat; - wire sig_ld_new_cmd_reg; - wire sig_ld_new_cmd_reg_reg; - wire sig_mstr2data_cmd_valid; - wire sig_next_calc_error_reg; - wire sig_next_cmd_cmplt_reg_i_4_n_0; - wire sig_next_cmd_cmplt_reg_reg; - wire sig_next_sequential_reg; - wire sig_rd_empty; - wire sig_rsc2stat_status_valid; - - (* SOFT_HLUTNM = "soft_lutpair104" *) - LUT5 #( - .INIT(32'h41100000)) - FIFO_Full_i_1__2 - (.I0(sig_rd_empty), - .I1(sig_dqual_reg_empty_reg), - .I2(sig_cmd2data_valid_reg), - .I3(Q[0]), - .I4(Q[1]), - .O(fifo_full_p1)); - LUT6 #( - .INIT(64'hBB4BBBBB44B44444)) - \INFERRED_GEN.cnt_i[0]_i_1__2 - (.I0(sig_rd_empty), - .I1(sig_dqual_reg_empty_reg), - .I2(sig_mstr2data_cmd_valid), - .I3(FIFO_Full_reg), - .I4(sig_inhibit_rdy_n_0), - .I5(Q[0]), - .O(addr_i_p1[0])); - LUT5 #( - .INIT(32'h77E78818)) - \INFERRED_GEN.cnt_i[1]_i_1__2 - (.I0(Q[0]), - .I1(sig_cmd2data_valid_reg), - .I2(sig_dqual_reg_empty_reg), - .I3(sig_rd_empty), - .I4(Q[1]), - .O(addr_i_p1[1])); - (* SOFT_HLUTNM = "soft_lutpair104" *) - LUT5 #( - .INIT(32'h7F7F0180)) - \INFERRED_GEN.cnt_i[2]_i_1__2 - (.I0(sig_cmd2data_valid_reg), - .I1(Q[0]), - .I2(Q[1]), - .I3(sig_dqual_reg_empty_reg), - .I4(sig_rd_empty), - .O(addr_i_p1[2])); - FDSE \INFERRED_GEN.cnt_i_reg[0] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(addr_i_p1[0]), - .Q(Q[0]), - .S(SR)); - FDSE \INFERRED_GEN.cnt_i_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(addr_i_p1[1]), - .Q(Q[1]), - .S(SR)); - FDSE \INFERRED_GEN.cnt_i_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(addr_i_p1[2]), - .Q(sig_rd_empty), - .S(SR)); - LUT6 #( - .INIT(64'h4444444444444441)) - \sig_dbeat_cntr[4]_i_1 - (.I0(sig_dqual_reg_empty_reg), - .I1(\sig_dbeat_cntr_reg[7] [4]), - .I2(\sig_dbeat_cntr_reg[7] [2]), - .I3(\sig_dbeat_cntr_reg[7] [0]), - .I4(\sig_dbeat_cntr_reg[7] [1]), - .I5(\sig_dbeat_cntr_reg[7] [3]), - .O(D[0])); - LUT3 #( - .INIT(8'h41)) - \sig_dbeat_cntr[5]_i_1 - (.I0(sig_dqual_reg_empty_reg), - .I1(\sig_dbeat_cntr_reg[7] [5]), - .I2(\sig_dbeat_cntr_reg[3] ), - .O(D[1])); - (* SOFT_HLUTNM = "soft_lutpair105" *) - LUT3 #( - .INIT(8'h41)) - \sig_dbeat_cntr[6]_i_1 - (.I0(sig_dqual_reg_empty_reg), - .I1(\sig_dbeat_cntr_reg[7] [6]), - .I2(\sig_dbeat_cntr_reg[4] ), - .O(D[2])); - (* SOFT_HLUTNM = "soft_lutpair106" *) - LUT2 #( - .INIT(4'hE)) - \sig_dbeat_cntr[7]_i_1 - (.I0(sig_dqual_reg_empty_reg), - .I1(\sig_dbeat_cntr_reg[2] ), - .O(E)); - (* SOFT_HLUTNM = "soft_lutpair105" *) - LUT4 #( - .INIT(16'h4441)) - \sig_dbeat_cntr[7]_i_2 - (.I0(sig_dqual_reg_empty_reg), - .I1(\sig_dbeat_cntr_reg[7] [7]), - .I2(\sig_dbeat_cntr_reg[4] ), - .I3(\sig_dbeat_cntr_reg[7] [6]), - .O(D[3])); - (* SOFT_HLUTNM = "soft_lutpair106" *) - LUT3 #( - .INIT(8'h08)) - sig_ld_new_cmd_reg_i_1 - (.I0(sig_dqual_reg_empty_reg), - .I1(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .I2(sig_ld_new_cmd_reg), - .O(sig_ld_new_cmd_reg_reg)); - LUT6 #( - .INIT(64'h10000000FFFFFFFF)) - sig_next_cmd_cmplt_reg_i_1 - (.I0(sig_dqual_reg_empty_reg), - .I1(sig_next_calc_error_reg), - .I2(sig_dqual_reg_full), - .I3(sig_dqual_reg_empty_reg_0), - .I4(m_axi_mm2s_rlast), - .I5(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .O(sig_next_cmd_cmplt_reg_reg)); - LUT5 #( - .INIT(32'hAAAA8000)) - sig_next_cmd_cmplt_reg_i_2 - (.I0(sig_next_cmd_cmplt_reg_i_4_n_0), - .I1(sig_next_sequential_reg), - .I2(sig_last_dbeat), - .I3(sig_dqual_reg_empty_reg_0), - .I4(sig_dqual_reg_empty), - .O(sig_dqual_reg_empty_reg)); - LUT4 #( - .INIT(16'h8A00)) - sig_next_cmd_cmplt_reg_i_3 - (.I0(m_axi_mm2s_rvalid), - .I1(sig_halt_reg_reg), - .I2(ram_full_i_reg), - .I3(sig_advance_pipe9_out__1), - .O(sig_dqual_reg_empty_reg_0)); - LUT6 #( - .INIT(64'h0000000000000075)) - sig_next_cmd_cmplt_reg_i_4 - (.I0(sig_rsc2stat_status_valid), - .I1(FIFO_Full_reg_0), - .I2(sig_inhibit_rdy_n), - .I3(sig_addr_posted_cntr_max__1), - .I4(sig_rd_empty), - .I5(sig_next_calc_error_reg), - .O(sig_next_cmd_cmplt_reg_i_4_n_0)); - LUT3 #( - .INIT(8'h80)) - sig_next_cmd_cmplt_reg_i_5 - (.I0(sig_addr_posted_cntr[1]), - .I1(sig_addr_posted_cntr[0]), - .I2(sig_addr_posted_cntr[2]), - .O(sig_addr_posted_cntr_max__1)); -endmodule - -(* ORIG_REF_NAME = "cntr_incr_decr_addn_f" *) -module Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_3 - (fifo_full_p1, - Q, - sig_calc_error_pushed_reg, - sig_wr_fifo, - sig_sm_halt_reg, - sig_input_reg_empty, - sig_calc_error_pushed, - p_55_out, - FIFO_Full_reg, - sig_inhibit_rdy_n, - SR, - m_axi_mm2s_aclk); - output fifo_full_p1; - output [2:0]Q; - input sig_calc_error_pushed_reg; - input sig_wr_fifo; - input sig_sm_halt_reg; - input sig_input_reg_empty; - input sig_calc_error_pushed; - input p_55_out; - input FIFO_Full_reg; - input sig_inhibit_rdy_n; - input [0:0]SR; - input m_axi_mm2s_aclk; - - wire FIFO_Full_reg; - wire [2:0]Q; - wire [0:0]SR; - wire [2:0]addr_i_p1; - wire fifo_full_p1; - wire m_axi_mm2s_aclk; - wire p_55_out; - wire sig_calc_error_pushed; - wire sig_calc_error_pushed_reg; - wire sig_inhibit_rdy_n; - wire sig_input_reg_empty; - wire sig_sm_halt_reg; - wire sig_wr_fifo; - - (* SOFT_HLUTNM = "soft_lutpair75" *) - LUT5 #( - .INIT(32'h41100008)) - FIFO_Full_i_1 - (.I0(Q[2]), - .I1(sig_calc_error_pushed_reg), - .I2(sig_wr_fifo), - .I3(Q[0]), - .I4(Q[1]), - .O(fifo_full_p1)); - LUT6 #( - .INIT(64'h0010FFEFFFEF0010)) - \INFERRED_GEN.cnt_i[0]_i_1 - (.I0(Q[2]), - .I1(sig_sm_halt_reg), - .I2(sig_input_reg_empty), - .I3(sig_calc_error_pushed), - .I4(sig_wr_fifo), - .I5(Q[0]), - .O(addr_i_p1[0])); - LUT6 #( - .INIT(64'hAEAAF7FF51550800)) - \INFERRED_GEN.cnt_i[1]_i_1 - (.I0(Q[0]), - .I1(p_55_out), - .I2(FIFO_Full_reg), - .I3(sig_inhibit_rdy_n), - .I4(sig_calc_error_pushed_reg), - .I5(Q[1]), - .O(addr_i_p1[1])); - (* SOFT_HLUTNM = "soft_lutpair75" *) - LUT5 #( - .INIT(32'hFE7F0180)) - \INFERRED_GEN.cnt_i[2]_i_1 - (.I0(sig_wr_fifo), - .I1(Q[0]), - .I2(Q[1]), - .I3(sig_calc_error_pushed_reg), - .I4(Q[2]), - .O(addr_i_p1[2])); - FDSE \INFERRED_GEN.cnt_i_reg[0] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(addr_i_p1[0]), - .Q(Q[0]), - .S(SR)); - FDSE \INFERRED_GEN.cnt_i_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(addr_i_p1[1]), - .Q(Q[1]), - .S(SR)); - FDSE \INFERRED_GEN.cnt_i_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(addr_i_p1[2]), - .Q(Q[2]), - .S(SR)); -endmodule - -(* ORIG_REF_NAME = "cntr_incr_decr_addn_f" *) -module Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_4 - (fifo_full_p1, - Q, - p_57_out, - sig_wr_fifo, - sig_rsc2stat_status_valid, + sig_single_dbeat, + sig_last_dbeat_reg_0, + p_11_out, FIFO_Full_reg, - sig_inhibit_rdy_n_reg, - sts_tready_reg, - SR, - m_axi_mm2s_aclk); - output fifo_full_p1; - output [2:0]Q; - input p_57_out; - input sig_wr_fifo; - input sig_rsc2stat_status_valid; + sig_inhibit_rdy_n_reg, + Q, + \sig_dbeat_cntr_reg[2] , + \sig_dbeat_cntr_reg[3] , + sig_xfer_calc_err_reg_reg, + \INFERRED_GEN.cnt_i_reg[1] , + m_axi_s2mm_aclk); + output sig_last_dbeat_reg; + output sig_wr_fifo; + output [5:0]D; + output [2:0]out; + input sig_first_dbeat1__0; + input sig_next_sequential_reg_reg; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_single_dbeat; + input sig_last_dbeat_reg_0; + input p_11_out; input FIFO_Full_reg; input sig_inhibit_rdy_n_reg; - input sts_tready_reg; - input [0:0]SR; - input m_axi_mm2s_aclk; + input [5:0]Q; + input \sig_dbeat_cntr_reg[2] ; + input \sig_dbeat_cntr_reg[3] ; + input [8:0]sig_xfer_calc_err_reg_reg; + input [1:0]\INFERRED_GEN.cnt_i_reg[1] ; + input m_axi_s2mm_aclk; + wire [5:0]D; wire FIFO_Full_reg; - wire [2:0]Q; - wire [0:0]SR; - wire [2:0]addr_i_p1; - wire fifo_full_p1; - wire m_axi_mm2s_aclk; - wire p_57_out; + wire [1:0]\INFERRED_GEN.cnt_i_reg[1] ; + wire [5:0]Q; + wire m_axi_s2mm_aclk; + wire [2:0]out; + wire p_11_out; + wire [12:7]sig_cmd_fifo_data_out; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire \sig_dbeat_cntr_reg[2] ; + wire \sig_dbeat_cntr_reg[3] ; + wire sig_first_dbeat1__0; wire sig_inhibit_rdy_n_reg; - wire sig_rsc2stat_status_valid; + wire sig_last_dbeat_reg; + wire sig_last_dbeat_reg_0; + wire sig_new_len_eq_0__6; + wire sig_next_sequential_reg_reg; + wire sig_single_dbeat; wire sig_wr_fifo; - wire sts_tready_reg; + wire [8:0]sig_xfer_calc_err_reg_reg; - (* SOFT_HLUTNM = "soft_lutpair73" *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][10]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][10]_srl4 + (.A0(\INFERRED_GEN.cnt_i_reg[1] [0]), + .A1(\INFERRED_GEN.cnt_i_reg[1] [1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(sig_xfer_calc_err_reg_reg[3]), + .Q(sig_cmd_fifo_data_out[10])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][11]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][11]_srl4 + (.A0(\INFERRED_GEN.cnt_i_reg[1] [0]), + .A1(\INFERRED_GEN.cnt_i_reg[1] [1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(sig_xfer_calc_err_reg_reg[4]), + .Q(sig_cmd_fifo_data_out[11])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][12]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][12]_srl4 + (.A0(\INFERRED_GEN.cnt_i_reg[1] [0]), + .A1(\INFERRED_GEN.cnt_i_reg[1] [1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(sig_xfer_calc_err_reg_reg[5]), + .Q(sig_cmd_fifo_data_out[12])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][33]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][33]_srl4 + (.A0(\INFERRED_GEN.cnt_i_reg[1] [0]), + .A1(\INFERRED_GEN.cnt_i_reg[1] [1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(sig_xfer_calc_err_reg_reg[6]), + .Q(out[0])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][34]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][34]_srl4 + (.A0(\INFERRED_GEN.cnt_i_reg[1] [0]), + .A1(\INFERRED_GEN.cnt_i_reg[1] [1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(sig_xfer_calc_err_reg_reg[7]), + .Q(out[1])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][35]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][35]_srl4 + (.A0(\INFERRED_GEN.cnt_i_reg[1] [0]), + .A1(\INFERRED_GEN.cnt_i_reg[1] [1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(sig_xfer_calc_err_reg_reg[8]), + .Q(out[2])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][7]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][7]_srl4 + (.A0(\INFERRED_GEN.cnt_i_reg[1] [0]), + .A1(\INFERRED_GEN.cnt_i_reg[1] [1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(sig_xfer_calc_err_reg_reg[0]), + .Q(sig_cmd_fifo_data_out[7])); + LUT3 #( + .INIT(8'h20)) + \INFERRED_GEN.data_reg[3][7]_srl4_i_1__2 + (.I0(p_11_out), + .I1(FIFO_Full_reg), + .I2(sig_inhibit_rdy_n_reg), + .O(sig_wr_fifo)); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][8]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][8]_srl4 + (.A0(\INFERRED_GEN.cnt_i_reg[1] [0]), + .A1(\INFERRED_GEN.cnt_i_reg[1] [1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(sig_xfer_calc_err_reg_reg[1]), + .Q(sig_cmd_fifo_data_out[8])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][9]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][9]_srl4 + (.A0(\INFERRED_GEN.cnt_i_reg[1] [0]), + .A1(\INFERRED_GEN.cnt_i_reg[1] [1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(sig_xfer_calc_err_reg_reg[2]), + .Q(sig_cmd_fifo_data_out[9])); + (* SOFT_HLUTNM = "soft_lutpair243" *) + LUT3 #( + .INIT(8'h8B)) + \sig_dbeat_cntr[0]_i_1__0 + (.I0(sig_cmd_fifo_data_out[7]), + .I1(sig_next_sequential_reg_reg), + .I2(Q[0]), + .O(D[0])); + (* SOFT_HLUTNM = "soft_lutpair243" *) + LUT4 #( + .INIT(16'hB88B)) + \sig_dbeat_cntr[1]_i_1__0 + (.I0(sig_cmd_fifo_data_out[8]), + .I1(sig_next_sequential_reg_reg), + .I2(Q[0]), + .I3(Q[1]), + .O(D[1])); LUT5 #( - .INIT(32'h41100000)) - FIFO_Full_i_1__3 - (.I0(Q[2]), - .I1(p_57_out), - .I2(sig_wr_fifo), + .INIT(32'hBBB8888B)) + \sig_dbeat_cntr[2]_i_1__0 + (.I0(sig_cmd_fifo_data_out[9]), + .I1(sig_next_sequential_reg_reg), + .I2(Q[1]), + .I3(Q[0]), + .I4(Q[2]), + .O(D[2])); + LUT6 #( + .INIT(64'hBBBBBBB88888888B)) + \sig_dbeat_cntr[3]_i_1__0 + (.I0(sig_cmd_fifo_data_out[10]), + .I1(sig_next_sequential_reg_reg), + .I2(Q[2]), .I3(Q[0]), .I4(Q[1]), - .O(fifo_full_p1)); + .I5(Q[3]), + .O(D[3])); + LUT4 #( + .INIT(16'hB88B)) + \sig_dbeat_cntr[4]_i_1__0 + (.I0(sig_cmd_fifo_data_out[11]), + .I1(sig_next_sequential_reg_reg), + .I2(\sig_dbeat_cntr_reg[2] ), + .I3(Q[4]), + .O(D[4])); + LUT4 #( + .INIT(16'hB88B)) + \sig_dbeat_cntr[5]_i_1 + (.I0(sig_cmd_fifo_data_out[12]), + .I1(sig_next_sequential_reg_reg), + .I2(\sig_dbeat_cntr_reg[3] ), + .I3(Q[5]), + .O(D[5])); LUT6 #( - .INIT(64'hBB4BBBBB44B44444)) - \INFERRED_GEN.cnt_i[0]_i_1__3 - (.I0(Q[2]), - .I1(p_57_out), - .I2(sig_rsc2stat_status_valid), - .I3(FIFO_Full_reg), - .I4(sig_inhibit_rdy_n_reg), - .I5(Q[0]), - .O(addr_i_p1[0])); + .INIT(64'hCA00CF00CA00C000)) + sig_last_dbeat_i_1__0 + (.I0(sig_first_dbeat1__0), + .I1(sig_new_len_eq_0__6), + .I2(sig_next_sequential_reg_reg), + .I3(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I4(sig_single_dbeat), + .I5(sig_last_dbeat_reg_0), + .O(sig_last_dbeat_reg)); LUT6 #( - .INIT(64'hAEAAF7FF51550800)) - \INFERRED_GEN.cnt_i[1]_i_1__3 - (.I0(Q[0]), - .I1(sig_rsc2stat_status_valid), - .I2(FIFO_Full_reg), - .I3(sig_inhibit_rdy_n_reg), - .I4(sts_tready_reg), - .I5(Q[1]), - .O(addr_i_p1[1])); - (* SOFT_HLUTNM = "soft_lutpair73" *) - LUT5 #( - .INIT(32'h7F7F0180)) - \INFERRED_GEN.cnt_i[2]_i_1__3 - (.I0(sig_wr_fifo), - .I1(Q[0]), - .I2(Q[1]), - .I3(p_57_out), - .I4(Q[2]), - .O(addr_i_p1[2])); - FDSE \INFERRED_GEN.cnt_i_reg[0] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(addr_i_p1[0]), - .Q(Q[0]), - .S(SR)); - FDSE \INFERRED_GEN.cnt_i_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(addr_i_p1[1]), - .Q(Q[1]), - .S(SR)); - FDSE \INFERRED_GEN.cnt_i_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(addr_i_p1[2]), - .Q(Q[2]), - .S(SR)); + .INIT(64'h0000000000000001)) + sig_last_dbeat_i_3__0 + (.I0(sig_cmd_fifo_data_out[11]), + .I1(sig_cmd_fifo_data_out[12]), + .I2(sig_cmd_fifo_data_out[8]), + .I3(sig_cmd_fifo_data_out[7]), + .I4(sig_cmd_fifo_data_out[10]), + .I5(sig_cmd_fifo_data_out[9]), + .O(sig_new_len_eq_0__6)); endmodule -(* ORIG_REF_NAME = "cntr_incr_decr_addn_f" *) -module Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_5 - (fifo_full_p1, - sig_calc_error_reg_reg, - Q, - sig_posted_to_axi_reg, - sig_cmd2addr_valid_reg, - sig_mstr2addr_cmd_valid, +(* ORIG_REF_NAME = "dynshreg_f" *) +module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized2 + (sig_next_calc_error_reg_reg, + D, + sig_last_dbeat_reg, + out, FIFO_Full_reg, - sig_inhibit_rdy_n, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_data2addr_stop_req, - sig_addr_reg_empty, - sig_sf_allow_addr_req, - SR, + sig_inhibit_rdy_n_0, + sig_mstr2data_cmd_valid, + sig_next_sequential_reg_reg, + Q, + \sig_dbeat_cntr_reg[3] , + \sig_dbeat_cntr_reg[0] , + in, + \INFERRED_GEN.cnt_i_reg[1] , m_axi_mm2s_aclk); - output fifo_full_p1; - output sig_calc_error_reg_reg; - output [1:0]Q; - output sig_posted_to_axi_reg; - input sig_cmd2addr_valid_reg; - input sig_mstr2addr_cmd_valid; + output sig_next_calc_error_reg_reg; + output [4:0]D; + output sig_last_dbeat_reg; + output [3:0]out; input FIFO_Full_reg; - input sig_inhibit_rdy_n; - input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - input sig_data2addr_stop_req; - input sig_addr_reg_empty; - input sig_sf_allow_addr_req; - input [0:0]SR; + input sig_inhibit_rdy_n_0; + input sig_mstr2data_cmd_valid; + input sig_next_sequential_reg_reg; + input [4:0]Q; + input \sig_dbeat_cntr_reg[3] ; + input \sig_dbeat_cntr_reg[0] ; + input [8:0]in; + input [1:0]\INFERRED_GEN.cnt_i_reg[1] ; input m_axi_mm2s_aclk; + wire [4:0]D; wire FIFO_Full_reg; - wire [1:0]Q; - wire [0:0]SR; - wire [2:0]addr_i_p1; - wire fifo_full_p1; + wire [1:0]\INFERRED_GEN.cnt_i_reg[1] ; + wire [4:0]Q; + wire [8:0]in; wire m_axi_mm2s_aclk; - wire sig_addr_reg_empty; - wire sig_calc_error_reg_reg; - wire sig_cmd2addr_valid_reg; - wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - wire sig_data2addr_stop_req; - wire sig_inhibit_rdy_n; - wire sig_mstr2addr_cmd_valid; - wire sig_posted_to_axi_reg; - wire sig_rd_empty; - wire sig_sf_allow_addr_req; + wire [3:0]out; + wire [11:7]sig_cmd_fifo_data_out; + wire \sig_dbeat_cntr_reg[0] ; + wire \sig_dbeat_cntr_reg[3] ; + wire sig_inhibit_rdy_n_0; + wire sig_last_dbeat_i_3_n_0; + wire sig_last_dbeat_reg; + wire sig_mstr2data_cmd_valid; + wire sig_next_calc_error_reg_reg; + wire sig_next_sequential_reg_reg; - (* SOFT_HLUTNM = "soft_lutpair71" *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][10]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][10]_srl4 + (.A0(\INFERRED_GEN.cnt_i_reg[1] [0]), + .A1(\INFERRED_GEN.cnt_i_reg[1] [1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_next_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[3]), + .Q(sig_cmd_fifo_data_out[10])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][11]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][11]_srl4 + (.A0(\INFERRED_GEN.cnt_i_reg[1] [0]), + .A1(\INFERRED_GEN.cnt_i_reg[1] [1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_next_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[4]), + .Q(sig_cmd_fifo_data_out[11])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][32]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][32]_srl4 + (.A0(\INFERRED_GEN.cnt_i_reg[1] [0]), + .A1(\INFERRED_GEN.cnt_i_reg[1] [1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_next_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[5]), + .Q(out[0])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][33]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][33]_srl4 + (.A0(\INFERRED_GEN.cnt_i_reg[1] [0]), + .A1(\INFERRED_GEN.cnt_i_reg[1] [1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_next_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[6]), + .Q(out[1])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][34]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][34]_srl4 + (.A0(\INFERRED_GEN.cnt_i_reg[1] [0]), + .A1(\INFERRED_GEN.cnt_i_reg[1] [1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_next_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[7]), + .Q(out[2])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][35]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][35]_srl4 + (.A0(\INFERRED_GEN.cnt_i_reg[1] [0]), + .A1(\INFERRED_GEN.cnt_i_reg[1] [1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_next_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[8]), + .Q(out[3])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][7]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][7]_srl4 + (.A0(\INFERRED_GEN.cnt_i_reg[1] [0]), + .A1(\INFERRED_GEN.cnt_i_reg[1] [1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_next_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[0]), + .Q(sig_cmd_fifo_data_out[7])); + LUT3 #( + .INIT(8'h40)) + \INFERRED_GEN.data_reg[3][7]_srl4_i_1 + (.I0(FIFO_Full_reg), + .I1(sig_inhibit_rdy_n_0), + .I2(sig_mstr2data_cmd_valid), + .O(sig_next_calc_error_reg_reg)); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][8]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][8]_srl4 + (.A0(\INFERRED_GEN.cnt_i_reg[1] [0]), + .A1(\INFERRED_GEN.cnt_i_reg[1] [1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_next_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[1]), + .Q(sig_cmd_fifo_data_out[8])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][9]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][9]_srl4 + (.A0(\INFERRED_GEN.cnt_i_reg[1] [0]), + .A1(\INFERRED_GEN.cnt_i_reg[1] [1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_next_calc_error_reg_reg), + .CLK(m_axi_mm2s_aclk), + .D(in[2]), + .Q(sig_cmd_fifo_data_out[9])); + (* SOFT_HLUTNM = "soft_lutpair161" *) + LUT3 #( + .INIT(8'h8B)) + \sig_dbeat_cntr[0]_i_1 + (.I0(sig_cmd_fifo_data_out[7]), + .I1(sig_next_sequential_reg_reg), + .I2(Q[0]), + .O(D[0])); + (* SOFT_HLUTNM = "soft_lutpair161" *) + LUT4 #( + .INIT(16'hB88B)) + \sig_dbeat_cntr[1]_i_1 + (.I0(sig_cmd_fifo_data_out[8]), + .I1(sig_next_sequential_reg_reg), + .I2(Q[1]), + .I3(Q[0]), + .O(D[1])); LUT5 #( - .INIT(32'h41100008)) - FIFO_Full_i_1__1 - (.I0(sig_rd_empty), - .I1(sig_calc_error_reg_reg), - .I2(sig_cmd2addr_valid_reg), + .INIT(32'hB8B8B88B)) + \sig_dbeat_cntr[2]_i_1 + (.I0(sig_cmd_fifo_data_out[9]), + .I1(sig_next_sequential_reg_reg), + .I2(Q[2]), .I3(Q[0]), .I4(Q[1]), - .O(fifo_full_p1)); - LUT5 #( - .INIT(32'h5955A6AA)) - \INFERRED_GEN.cnt_i[0]_i_1__1 - (.I0(sig_calc_error_reg_reg), - .I1(sig_mstr2addr_cmd_valid), - .I2(FIFO_Full_reg), - .I3(sig_inhibit_rdy_n), - .I4(Q[0]), - .O(addr_i_p1[0])); + .O(D[2])); LUT6 #( - .INIT(64'hAEAAF7FF51550800)) - \INFERRED_GEN.cnt_i[1]_i_1__1 - (.I0(Q[0]), - .I1(sig_mstr2addr_cmd_valid), - .I2(FIFO_Full_reg), - .I3(sig_inhibit_rdy_n), - .I4(sig_calc_error_reg_reg), - .I5(Q[1]), - .O(addr_i_p1[1])); - (* SOFT_HLUTNM = "soft_lutpair71" *) - LUT5 #( - .INIT(32'hFE7F0180)) - \INFERRED_GEN.cnt_i[2]_i_1__1 - (.I0(sig_cmd2addr_valid_reg), - .I1(Q[0]), - .I2(Q[1]), - .I3(sig_calc_error_reg_reg), - .I4(sig_rd_empty), - .O(addr_i_p1[2])); - FDSE \INFERRED_GEN.cnt_i_reg[0] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(addr_i_p1[0]), - .Q(Q[0]), - .S(SR)); - FDSE \INFERRED_GEN.cnt_i_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(addr_i_p1[1]), - .Q(Q[1]), - .S(SR)); - FDSE \INFERRED_GEN.cnt_i_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(addr_i_p1[2]), - .Q(sig_rd_empty), - .S(SR)); - (* SOFT_HLUTNM = "soft_lutpair72" *) + .INIT(64'hB8B8B8B8B8B8B88B)) + \sig_dbeat_cntr[3]_i_1 + (.I0(sig_cmd_fifo_data_out[10]), + .I1(sig_next_sequential_reg_reg), + .I2(Q[3]), + .I3(Q[2]), + .I4(Q[1]), + .I5(Q[0]), + .O(D[3])); LUT4 #( - .INIT(16'h0008)) - \sig_next_addr_reg[31]_i_2 - (.I0(sig_sf_allow_addr_req), - .I1(sig_addr_reg_empty), - .I2(sig_data2addr_stop_req), - .I3(sig_rd_empty), - .O(sig_calc_error_reg_reg)); - (* SOFT_HLUTNM = "soft_lutpair72" *) - LUT5 #( - .INIT(32'h02000000)) - sig_posted_to_axi_2_i_1 - (.I0(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .I1(sig_rd_empty), - .I2(sig_data2addr_stop_req), - .I3(sig_addr_reg_empty), - .I4(sig_sf_allow_addr_req), - .O(sig_posted_to_axi_reg)); + .INIT(16'h8BB8)) + \sig_dbeat_cntr[4]_i_1 + (.I0(sig_cmd_fifo_data_out[11]), + .I1(sig_next_sequential_reg_reg), + .I2(Q[4]), + .I3(\sig_dbeat_cntr_reg[0] ), + .O(D[4])); + LUT4 #( + .INIT(16'h0535)) + sig_last_dbeat_i_1 + (.I0(\sig_dbeat_cntr_reg[3] ), + .I1(sig_last_dbeat_i_3_n_0), + .I2(sig_next_sequential_reg_reg), + .I3(sig_cmd_fifo_data_out[11]), + .O(sig_last_dbeat_reg)); + LUT4 #( + .INIT(16'hFFFE)) + sig_last_dbeat_i_3 + (.I0(sig_cmd_fifo_data_out[8]), + .I1(sig_cmd_fifo_data_out[7]), + .I2(sig_cmd_fifo_data_out[10]), + .I3(sig_cmd_fifo_data_out[9]), + .O(sig_last_dbeat_i_3_n_0)); endmodule - -(* ORIG_REF_NAME = "cntr_incr_decr_addn_f" *) -module Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_6 - (fifo_full_p1, - Q, - FIFO_Full_reg, - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram , - sig_mstr2sf_cmd_valid, - FIFO_Full_reg_0, - sig_inhibit_rdy_n_reg, - sig_stream_rst, - m_axi_mm2s_aclk); - output fifo_full_p1; - output [2:0]Q; - output FIFO_Full_reg; - input \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; - input sig_mstr2sf_cmd_valid; - input FIFO_Full_reg_0; - input sig_inhibit_rdy_n_reg; - input sig_stream_rst; + +(* ORIG_REF_NAME = "dynshreg_f" *) +module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized3 + (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , + FIFO_Full_reg, + in, + Q, + m_axi_mm2s_aclk, + lsig_cmd_loaded, + prmry_resetn_i_reg, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 , + DOBDO); + output \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + input FIFO_Full_reg; + input [0:0]in; + input [2:0]Q; input m_axi_mm2s_aclk; + input lsig_cmd_loaded; + input prmry_resetn_i_reg; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; + input [0:0]DOBDO; - wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; + wire [0:0]DOBDO; wire FIFO_Full_reg; - wire FIFO_Full_reg_0; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; wire [2:0]Q; - wire [2:0]addr_i_p1; - wire fifo_full_p1; + wire [0:0]in; + wire lsig_cmd_loaded; wire m_axi_mm2s_aclk; - wire sig_inhibit_rdy_n_reg; - wire sig_mstr2sf_cmd_valid; - wire sig_stream_rst; + wire [7:7]p_0_out; + wire prmry_resetn_i_reg; - (* SOFT_HLUTNM = "soft_lutpair68" *) - LUT5 #( - .INIT(32'h41100008)) - FIFO_Full_i_1__0 - (.I0(Q[2]), - .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ), - .I2(FIFO_Full_reg), - .I3(Q[0]), - .I4(Q[1]), - .O(fifo_full_p1)); - (* SOFT_HLUTNM = "soft_lutpair69" *) - LUT5 #( - .INIT(32'h5955A6AA)) - \INFERRED_GEN.cnt_i[0]_i_1__0 - (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ), - .I1(sig_mstr2sf_cmd_valid), - .I2(FIFO_Full_reg_0), - .I3(sig_inhibit_rdy_n_reg), - .I4(Q[0]), - .O(addr_i_p1[0])); LUT6 #( - .INIT(64'hAEAAF7FF51550800)) - \INFERRED_GEN.cnt_i[1]_i_1__0 - (.I0(Q[0]), - .I1(sig_mstr2sf_cmd_valid), - .I2(FIFO_Full_reg_0), - .I3(sig_inhibit_rdy_n_reg), - .I4(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ), - .I5(Q[1]), - .O(addr_i_p1[1])); - (* SOFT_HLUTNM = "soft_lutpair68" *) - LUT5 #( - .INIT(32'hFE7F0180)) - \INFERRED_GEN.cnt_i[2]_i_1__0 - (.I0(FIFO_Full_reg), - .I1(Q[0]), - .I2(Q[1]), - .I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ), - .I4(Q[2]), - .O(addr_i_p1[2])); - FDSE \INFERRED_GEN.cnt_i_reg[0] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(addr_i_p1[0]), - .Q(Q[0]), - .S(sig_stream_rst)); - FDSE \INFERRED_GEN.cnt_i_reg[1] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(addr_i_p1[1]), - .Q(Q[1]), - .S(sig_stream_rst)); - FDSE \INFERRED_GEN.cnt_i_reg[2] - (.C(m_axi_mm2s_aclk), - .CE(1'b1), - .D(addr_i_p1[2]), - .Q(Q[2]), - .S(sig_stream_rst)); - (* SOFT_HLUTNM = "soft_lutpair69" *) - LUT3 #( - .INIT(8'h20)) - \INFERRED_GEN.data_reg[3][7]_srl4_i_1 - (.I0(sig_mstr2sf_cmd_valid), - .I1(FIFO_Full_reg_0), - .I2(sig_inhibit_rdy_n_reg), - .O(FIFO_Full_reg)); + .INIT(64'h0FF00FF0AEE22EE2)) + \INCLUDE_UNPACKING.lsig_0ffset_cntr[0]_i_1 + (.I0(p_0_out), + .I1(lsig_cmd_loaded), + .I2(prmry_resetn_i_reg), + .I3(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I4(DOBDO), + .I5(Q[2]), + .O(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] )); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][7]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][7]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(FIFO_Full_reg), + .CLK(m_axi_mm2s_aclk), + .D(in), + .Q(p_0_out)); endmodule (* ORIG_REF_NAME = "dynshreg_f" *) -module Arty_Z7_20_axi_vdma_0_0_dynshreg_f - (sig_wr_fifo, - out, - sig_calc_error_reg_reg, - p_55_out, +module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized4 + (out, + CO, + \GEN_STS_GRTR_THAN_8.ovrflo_err_reg , + decerr_i_reg, + slverr_i_reg, + interr_i_reg, + sig_wr_fifo, + \hsize_vid_reg[15] , + \hsize_vid_reg[2] , + S, + Q, + sig_wsc2stat_status_valid, FIFO_Full_reg, sig_inhibit_rdy_n, - Q, - sig_sm_halt_reg, - sig_input_reg_empty, in, - \s_axis_cmd_tdata_reg[63] , - m_axi_mm2s_aclk); + m_axi_s2mm_aclk); + output [1:0]out; + output [0:0]CO; + output [0:0]\GEN_STS_GRTR_THAN_8.ovrflo_err_reg ; + output decerr_i_reg; + output slverr_i_reg; + output interr_i_reg; output sig_wr_fifo; - output [49:0]out; - output sig_calc_error_reg_reg; - input p_55_out; + input [12:0]\hsize_vid_reg[15] ; + input [0:0]\hsize_vid_reg[2] ; + input [0:0]S; + input [2:0]Q; + input sig_wsc2stat_status_valid; input FIFO_Full_reg; input sig_inhibit_rdy_n; - input [2:0]Q; - input sig_sm_halt_reg; - input sig_input_reg_empty; - input [0:0]in; - input [48:0]\s_axis_cmd_tdata_reg[63] ; - input m_axi_mm2s_aclk; + input [16:0]in; + input m_axi_s2mm_aclk; + wire [0:0]CO; wire FIFO_Full_reg; + wire \GEN_STS_GRTR_THAN_8.ovrflo_err_i_4_n_0 ; + wire \GEN_STS_GRTR_THAN_8.ovrflo_err_i_5_n_0 ; + wire \GEN_STS_GRTR_THAN_8.ovrflo_err_i_6_n_0 ; + wire \GEN_STS_GRTR_THAN_8.ovrflo_err_i_7_n_0 ; + wire \GEN_STS_GRTR_THAN_8.ovrflo_err_i_8_n_0 ; + wire [0:0]\GEN_STS_GRTR_THAN_8.ovrflo_err_reg ; + wire \GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_2_n_3 ; + wire \GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_3_n_0 ; + wire \GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_3_n_1 ; + wire \GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_3_n_2 ; + wire \GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_3_n_3 ; + wire \GEN_STS_GRTR_THAN_8.undrflo_err_i_4_n_0 ; + wire \GEN_STS_GRTR_THAN_8.undrflo_err_i_5_n_0 ; + wire \GEN_STS_GRTR_THAN_8.undrflo_err_i_6_n_0 ; + wire \GEN_STS_GRTR_THAN_8.undrflo_err_i_7_n_0 ; + wire \GEN_STS_GRTR_THAN_8.undrflo_err_i_8_n_0 ; + wire \GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_2_n_3 ; + wire \GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_3_n_0 ; + wire \GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_3_n_1 ; + wire \GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_3_n_2 ; + wire \GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_3_n_3 ; wire [2:0]Q; - wire [0:0]in; - wire m_axi_mm2s_aclk; - wire [49:0]out; - wire p_55_out; - wire [48:0]\s_axis_cmd_tdata_reg[63] ; - wire sig_calc_error_reg_i_2_n_0; - wire sig_calc_error_reg_i_3_n_0; - wire sig_calc_error_reg_i_4_n_0; - wire sig_calc_error_reg_i_5_n_0; - wire sig_calc_error_reg_reg; + wire [0:0]S; + wire decerr_i_reg; + wire [12:0]\hsize_vid_reg[15] ; + wire [0:0]\hsize_vid_reg[2] ; + wire [16:0]in; + wire interr_i_reg; + wire m_axi_s2mm_aclk; + wire [23:4]m_axis_s2mm_sts_tdata; + wire [1:0]out; wire sig_inhibit_rdy_n; - wire sig_input_reg_empty; - wire sig_sm_halt_reg; wire sig_wr_fifo; + wire sig_wsc2stat_status_valid; + wire slverr_i_reg; + wire [3:2]\NLW_GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_2_CO_UNCONNECTED ; + wire [3:0]\NLW_GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_2_O_UNCONNECTED ; + wire [3:0]\NLW_GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_3_O_UNCONNECTED ; + wire [3:2]\NLW_GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_2_CO_UNCONNECTED ; + wire [3:0]\NLW_GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_2_O_UNCONNECTED ; + wire [3:0]\NLW_GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_3_O_UNCONNECTED ; - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][0]_srl4 " *) + LUT2 #( + .INIT(4'h9)) + \GEN_STS_GRTR_THAN_8.ovrflo_err_i_4 + (.I0(m_axis_s2mm_sts_tdata[23]), + .I1(\hsize_vid_reg[15] [12]), + .O(\GEN_STS_GRTR_THAN_8.ovrflo_err_i_4_n_0 )); + LUT6 #( + .INIT(64'h9009000000009009)) + \GEN_STS_GRTR_THAN_8.ovrflo_err_i_5 + (.I0(m_axis_s2mm_sts_tdata[22]), + .I1(\hsize_vid_reg[15] [11]), + .I2(m_axis_s2mm_sts_tdata[20]), + .I3(\hsize_vid_reg[15] [9]), + .I4(\hsize_vid_reg[15] [10]), + .I5(m_axis_s2mm_sts_tdata[21]), + .O(\GEN_STS_GRTR_THAN_8.ovrflo_err_i_5_n_0 )); + LUT6 #( + .INIT(64'h9009000000009009)) + \GEN_STS_GRTR_THAN_8.ovrflo_err_i_6 + (.I0(m_axis_s2mm_sts_tdata[19]), + .I1(\hsize_vid_reg[15] [8]), + .I2(m_axis_s2mm_sts_tdata[18]), + .I3(\hsize_vid_reg[15] [7]), + .I4(\hsize_vid_reg[15] [6]), + .I5(m_axis_s2mm_sts_tdata[17]), + .O(\GEN_STS_GRTR_THAN_8.ovrflo_err_i_6_n_0 )); + LUT6 #( + .INIT(64'h9009000000009009)) + \GEN_STS_GRTR_THAN_8.ovrflo_err_i_7 + (.I0(m_axis_s2mm_sts_tdata[16]), + .I1(\hsize_vid_reg[15] [5]), + .I2(m_axis_s2mm_sts_tdata[14]), + .I3(\hsize_vid_reg[15] [3]), + .I4(\hsize_vid_reg[15] [4]), + .I5(m_axis_s2mm_sts_tdata[15]), + .O(\GEN_STS_GRTR_THAN_8.ovrflo_err_i_7_n_0 )); + LUT6 #( + .INIT(64'h9009000000009009)) + \GEN_STS_GRTR_THAN_8.ovrflo_err_i_8 + (.I0(m_axis_s2mm_sts_tdata[13]), + .I1(\hsize_vid_reg[15] [2]), + .I2(m_axis_s2mm_sts_tdata[12]), + .I3(\hsize_vid_reg[15] [1]), + .I4(\hsize_vid_reg[15] [0]), + .I5(m_axis_s2mm_sts_tdata[11]), + .O(\GEN_STS_GRTR_THAN_8.ovrflo_err_i_8_n_0 )); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_2 + (.CI(\GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_3_n_0 ), + .CO({\NLW_GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_2_CO_UNCONNECTED [3:2],\GEN_STS_GRTR_THAN_8.ovrflo_err_reg ,\GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_2_O_UNCONNECTED [3:0]), + .S({1'b0,1'b0,\GEN_STS_GRTR_THAN_8.ovrflo_err_i_4_n_0 ,\GEN_STS_GRTR_THAN_8.ovrflo_err_i_5_n_0 })); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_3 + (.CI(1'b0), + .CO({\GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_3_n_0 ,\GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_3_n_1 ,\GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_3_n_2 ,\GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_3_n_3 }), + .CYINIT(1'b1), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_3_O_UNCONNECTED [3:0]), + .S({\GEN_STS_GRTR_THAN_8.ovrflo_err_i_6_n_0 ,\GEN_STS_GRTR_THAN_8.ovrflo_err_i_7_n_0 ,\GEN_STS_GRTR_THAN_8.ovrflo_err_i_8_n_0 ,S})); + LUT2 #( + .INIT(4'h9)) + \GEN_STS_GRTR_THAN_8.undrflo_err_i_4 + (.I0(m_axis_s2mm_sts_tdata[23]), + .I1(\hsize_vid_reg[15] [12]), + .O(\GEN_STS_GRTR_THAN_8.undrflo_err_i_4_n_0 )); + LUT6 #( + .INIT(64'h9009000000009009)) + \GEN_STS_GRTR_THAN_8.undrflo_err_i_5 + (.I0(m_axis_s2mm_sts_tdata[22]), + .I1(\hsize_vid_reg[15] [11]), + .I2(m_axis_s2mm_sts_tdata[20]), + .I3(\hsize_vid_reg[15] [9]), + .I4(\hsize_vid_reg[15] [10]), + .I5(m_axis_s2mm_sts_tdata[21]), + .O(\GEN_STS_GRTR_THAN_8.undrflo_err_i_5_n_0 )); + LUT6 #( + .INIT(64'h9009000000009009)) + \GEN_STS_GRTR_THAN_8.undrflo_err_i_6 + (.I0(m_axis_s2mm_sts_tdata[19]), + .I1(\hsize_vid_reg[15] [8]), + .I2(m_axis_s2mm_sts_tdata[18]), + .I3(\hsize_vid_reg[15] [7]), + .I4(\hsize_vid_reg[15] [6]), + .I5(m_axis_s2mm_sts_tdata[17]), + .O(\GEN_STS_GRTR_THAN_8.undrflo_err_i_6_n_0 )); + LUT6 #( + .INIT(64'h9009000000009009)) + \GEN_STS_GRTR_THAN_8.undrflo_err_i_7 + (.I0(m_axis_s2mm_sts_tdata[16]), + .I1(\hsize_vid_reg[15] [5]), + .I2(m_axis_s2mm_sts_tdata[14]), + .I3(\hsize_vid_reg[15] [3]), + .I4(\hsize_vid_reg[15] [4]), + .I5(m_axis_s2mm_sts_tdata[15]), + .O(\GEN_STS_GRTR_THAN_8.undrflo_err_i_7_n_0 )); + LUT6 #( + .INIT(64'h9009000000009009)) + \GEN_STS_GRTR_THAN_8.undrflo_err_i_8 + (.I0(m_axis_s2mm_sts_tdata[13]), + .I1(\hsize_vid_reg[15] [2]), + .I2(m_axis_s2mm_sts_tdata[12]), + .I3(\hsize_vid_reg[15] [1]), + .I4(\hsize_vid_reg[15] [0]), + .I5(m_axis_s2mm_sts_tdata[11]), + .O(\GEN_STS_GRTR_THAN_8.undrflo_err_i_8_n_0 )); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_2 + (.CI(\GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_3_n_0 ), + .CO({\NLW_GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_2_CO_UNCONNECTED [3:2],CO,\GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b1,1'b1}), + .O(\NLW_GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_2_O_UNCONNECTED [3:0]), + .S({1'b0,1'b0,\GEN_STS_GRTR_THAN_8.undrflo_err_i_4_n_0 ,\GEN_STS_GRTR_THAN_8.undrflo_err_i_5_n_0 })); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_3 + (.CI(1'b0), + .CO({\GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_3_n_0 ,\GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_3_n_1 ,\GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_3_n_2 ,\GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_3_n_3 }), + .CYINIT(1'b0), + .DI({1'b1,1'b1,1'b1,1'b1}), + .O(\NLW_GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_3_O_UNCONNECTED [3:0]), + .S({\GEN_STS_GRTR_THAN_8.undrflo_err_i_6_n_0 ,\GEN_STS_GRTR_THAN_8.undrflo_err_i_7_n_0 ,\GEN_STS_GRTR_THAN_8.undrflo_err_i_8_n_0 ,\hsize_vid_reg[2] })); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][11]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][0]_srl4 + \INFERRED_GEN.data_reg[3][11]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [0]), - .Q(out[0])); - LUT3 #( - .INIT(8'h20)) - \INFERRED_GEN.data_reg[3][0]_srl4_i_1 - (.I0(p_55_out), - .I1(FIFO_Full_reg), - .I2(sig_inhibit_rdy_n), - .O(sig_wr_fifo)); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][10]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[3]), + .Q(m_axis_s2mm_sts_tdata[11])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][12]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][10]_srl4 + \INFERRED_GEN.data_reg[3][12]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [10]), - .Q(out[10])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][11]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[4]), + .Q(m_axis_s2mm_sts_tdata[12])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][13]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][11]_srl4 + \INFERRED_GEN.data_reg[3][13]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [11]), - .Q(out[11])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][12]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[5]), + .Q(m_axis_s2mm_sts_tdata[13])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][14]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][12]_srl4 + \INFERRED_GEN.data_reg[3][14]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [12]), - .Q(out[12])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][13]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[6]), + .Q(m_axis_s2mm_sts_tdata[14])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][15]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][13]_srl4 + \INFERRED_GEN.data_reg[3][15]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [13]), - .Q(out[13])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][14]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[7]), + .Q(m_axis_s2mm_sts_tdata[15])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][16]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][14]_srl4 + \INFERRED_GEN.data_reg[3][16]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [14]), - .Q(out[14])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][15]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[8]), + .Q(m_axis_s2mm_sts_tdata[16])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][17]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][15]_srl4 + \INFERRED_GEN.data_reg[3][17]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [15]), - .Q(out[15])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][1]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[9]), + .Q(m_axis_s2mm_sts_tdata[17])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][18]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][1]_srl4 + \INFERRED_GEN.data_reg[3][18]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [1]), - .Q(out[1])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][23]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[10]), + .Q(m_axis_s2mm_sts_tdata[18])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][19]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][23]_srl4 + \INFERRED_GEN.data_reg[3][19]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [16]), - .Q(out[16])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][2]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[11]), + .Q(m_axis_s2mm_sts_tdata[19])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][20]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][2]_srl4 + \INFERRED_GEN.data_reg[3][20]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [2]), - .Q(out[2])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][30]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[12]), + .Q(m_axis_s2mm_sts_tdata[20])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][21]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][30]_srl4 + \INFERRED_GEN.data_reg[3][21]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [16]), - .Q(out[17])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][32]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[13]), + .Q(m_axis_s2mm_sts_tdata[21])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][22]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][32]_srl4 + \INFERRED_GEN.data_reg[3][22]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [17]), - .Q(out[18])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][33]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[14]), + .Q(m_axis_s2mm_sts_tdata[22])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][23]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][33]_srl4 + \INFERRED_GEN.data_reg[3][23]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [18]), - .Q(out[19])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][34]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[15]), + .Q(m_axis_s2mm_sts_tdata[23])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][31]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][34]_srl4 + \INFERRED_GEN.data_reg[3][31]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [19]), - .Q(out[20])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][35]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[16]), + .Q(out[1])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][4]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][35]_srl4 + \INFERRED_GEN.data_reg[3][4]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [20]), - .Q(out[21])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][36]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[0]), + .Q(m_axis_s2mm_sts_tdata[4])); + LUT3 #( + .INIT(8'h20)) + \INFERRED_GEN.data_reg[3][4]_srl4_i_1__2 + (.I0(sig_wsc2stat_status_valid), + .I1(FIFO_Full_reg), + .I2(sig_inhibit_rdy_n), + .O(sig_wr_fifo)); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][5]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][36]_srl4 + \INFERRED_GEN.data_reg[3][5]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [21]), - .Q(out[22])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][37]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[1]), + .Q(m_axis_s2mm_sts_tdata[5])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][6]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][37]_srl4 + \INFERRED_GEN.data_reg[3][6]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [22]), - .Q(out[23])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][38]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[2]), + .Q(m_axis_s2mm_sts_tdata[6])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][8]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][38]_srl4 + \INFERRED_GEN.data_reg[3][8]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [23]), - .Q(out[24])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][39]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(1'b0), + .Q(out[0])); + (* SOFT_HLUTNM = "soft_lutpair237" *) + LUT2 #( + .INIT(4'h2)) + decerr_i_i_1__0 + (.I0(m_axis_s2mm_sts_tdata[5]), + .I1(Q[2]), + .O(decerr_i_reg)); + LUT2 #( + .INIT(4'h2)) + interr_i_i_1__0 + (.I0(m_axis_s2mm_sts_tdata[4]), + .I1(Q[2]), + .O(interr_i_reg)); + (* SOFT_HLUTNM = "soft_lutpair237" *) + LUT2 #( + .INIT(4'h2)) + slverr_i_i_1__0 + (.I0(m_axis_s2mm_sts_tdata[6]), + .I1(Q[2]), + .O(slverr_i_reg)); +endmodule + +(* ORIG_REF_NAME = "dynshreg_f" *) +module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized5 + (\GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg , + \GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg , + in, + out, + sel, + m_axi_s2mm_bresp, + addr, + m_axi_s2mm_aclk); + output \GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg ; + output \GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg ; + input [1:0]in; + input [0:0]out; + input sel; + input [1:0]m_axi_s2mm_bresp; + input [0:2]addr; + input m_axi_s2mm_aclk; + + wire \GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg ; + wire \GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg ; + wire [0:2]addr; + wire [1:0]in; + wire m_axi_s2mm_aclk; + wire [1:0]m_axi_s2mm_bresp; + wire [0:0]out; + wire sel; + wire [1:0]sig_wresp_sfifo_out; + + (* SOFT_HLUTNM = "soft_lutpair250" *) + LUT4 #( + .INIT(16'h00EA)) + \GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_i_1 + (.I0(in[0]), + .I1(sig_wresp_sfifo_out[0]), + .I2(sig_wresp_sfifo_out[1]), + .I3(out), + .O(\GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg )); + (* SOFT_HLUTNM = "soft_lutpair250" *) + LUT4 #( + .INIT(16'h00AE)) + \GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_i_1 + (.I0(in[1]), + .I1(sig_wresp_sfifo_out[1]), + .I2(sig_wresp_sfifo_out[0]), + .I3(out), + .O(\GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg )); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][0]_srl6 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][39]_srl4 - (.A0(Q[0]), - .A1(Q[1]), - .A2(1'b0), + \INFERRED_GEN.data_reg[5][0]_srl6 + (.A0(addr[2]), + .A1(addr[1]), + .A2(addr[0]), .A3(1'b0), - .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [24]), - .Q(out[25])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][3]_srl4 " *) + .CE(sel), + .CLK(m_axi_s2mm_aclk), + .D(m_axi_s2mm_bresp[0]), + .Q(sig_wresp_sfifo_out[0])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][1]_srl6 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][3]_srl4 - (.A0(Q[0]), - .A1(Q[1]), - .A2(1'b0), + \INFERRED_GEN.data_reg[5][1]_srl6 + (.A0(addr[2]), + .A1(addr[1]), + .A2(addr[0]), .A3(1'b0), - .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [3]), + .CE(sel), + .CLK(m_axi_s2mm_aclk), + .D(m_axi_s2mm_bresp[1]), + .Q(sig_wresp_sfifo_out[1])); +endmodule + +(* ORIG_REF_NAME = "dynshreg_f" *) +module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized6 + (p_0_in, + out, + D, + \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg , + \sig_wdc_statcnt_reg[3] , + E, + p_4_out, + Q, + \INFERRED_GEN.cnt_i_reg[3] , + sig_coelsc_reg_empty, + \INFERRED_GEN.cnt_i_reg[3]_0 , + sig_data2wsc_valid, + FIFO_Full_reg, + sig_inhibit_rdy_n, + in, + \GEN_INDET_BTT.lsig_eop_reg_reg , + m_axi_s2mm_aclk); + output p_0_in; + output [15:0]out; + output [2:0]D; + output \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ; + output \sig_wdc_statcnt_reg[3] ; + output [0:0]E; + output p_4_out; + input [3:0]Q; + input [0:0]\INFERRED_GEN.cnt_i_reg[3] ; + input sig_coelsc_reg_empty; + input [3:0]\INFERRED_GEN.cnt_i_reg[3]_0 ; + input sig_data2wsc_valid; + input FIFO_Full_reg; + input sig_inhibit_rdy_n; + input [0:0]in; + input [15:0]\GEN_INDET_BTT.lsig_eop_reg_reg ; + input m_axi_s2mm_aclk; + + wire [2:0]D; + wire [0:0]E; + wire FIFO_Full_reg; + wire \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ; + wire [15:0]\GEN_INDET_BTT.lsig_eop_reg_reg ; + wire [0:0]\INFERRED_GEN.cnt_i_reg[3] ; + wire [3:0]\INFERRED_GEN.cnt_i_reg[3]_0 ; + wire [3:0]Q; + wire [0:0]in; + wire m_axi_s2mm_aclk; + wire [15:0]out; + wire p_0_in; + wire p_4_out; + wire sig_coelsc_reg_empty; + wire sig_data2wsc_valid; + wire sig_inhibit_rdy_n; + wire \sig_wdc_statcnt_reg[3] ; + + (* SOFT_HLUTNM = "soft_lutpair249" *) + LUT2 #( + .INIT(4'hE)) + \GEN_ENABLE_INDET_BTT.sig_coelsc_interr_reg_i_1 + (.I0(in), + .I1(out[0]), + .O(p_4_out)); + LUT1 #( + .INIT(2'h1)) + \GEN_ENABLE_INDET_BTT.sig_coelsc_reg_empty_i_3 + (.I0(out[1]), + .O(p_0_in)); + (* SOFT_HLUTNM = "soft_lutpair249" *) + LUT4 #( + .INIT(16'h00D0)) + \INFERRED_GEN.cnt_i[1]_i_2__0 + (.I0(\INFERRED_GEN.cnt_i_reg[3] ), + .I1(out[0]), + .I2(sig_coelsc_reg_empty), + .I3(\INFERRED_GEN.cnt_i_reg[3]_0 [3]), + .O(\sig_wdc_statcnt_reg[3] )); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][10]_srl6 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[5][10]_srl6 + (.A0(\INFERRED_GEN.cnt_i_reg[3]_0 [0]), + .A1(\INFERRED_GEN.cnt_i_reg[3]_0 [1]), + .A2(\INFERRED_GEN.cnt_i_reg[3]_0 [2]), + .A3(1'b0), + .CE(\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ), + .CLK(m_axi_s2mm_aclk), + .D(\GEN_INDET_BTT.lsig_eop_reg_reg [3]), .Q(out[3])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][40]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][11]_srl6 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][40]_srl4 - (.A0(Q[0]), - .A1(Q[1]), - .A2(1'b0), + \INFERRED_GEN.data_reg[5][11]_srl6 + (.A0(\INFERRED_GEN.cnt_i_reg[3]_0 [0]), + .A1(\INFERRED_GEN.cnt_i_reg[3]_0 [1]), + .A2(\INFERRED_GEN.cnt_i_reg[3]_0 [2]), .A3(1'b0), - .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [25]), - .Q(out[26])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][41]_srl4 " *) + .CE(\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ), + .CLK(m_axi_s2mm_aclk), + .D(\GEN_INDET_BTT.lsig_eop_reg_reg [4]), + .Q(out[4])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][12]_srl6 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][41]_srl4 - (.A0(Q[0]), - .A1(Q[1]), - .A2(1'b0), + \INFERRED_GEN.data_reg[5][12]_srl6 + (.A0(\INFERRED_GEN.cnt_i_reg[3]_0 [0]), + .A1(\INFERRED_GEN.cnt_i_reg[3]_0 [1]), + .A2(\INFERRED_GEN.cnt_i_reg[3]_0 [2]), .A3(1'b0), - .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [26]), - .Q(out[27])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][42]_srl4 " *) + .CE(\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ), + .CLK(m_axi_s2mm_aclk), + .D(\GEN_INDET_BTT.lsig_eop_reg_reg [5]), + .Q(out[5])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][13]_srl6 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][42]_srl4 - (.A0(Q[0]), - .A1(Q[1]), - .A2(1'b0), + \INFERRED_GEN.data_reg[5][13]_srl6 + (.A0(\INFERRED_GEN.cnt_i_reg[3]_0 [0]), + .A1(\INFERRED_GEN.cnt_i_reg[3]_0 [1]), + .A2(\INFERRED_GEN.cnt_i_reg[3]_0 [2]), .A3(1'b0), - .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [27]), - .Q(out[28])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][43]_srl4 " *) + .CE(\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ), + .CLK(m_axi_s2mm_aclk), + .D(\GEN_INDET_BTT.lsig_eop_reg_reg [6]), + .Q(out[6])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][14]_srl6 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][43]_srl4 - (.A0(Q[0]), - .A1(Q[1]), - .A2(1'b0), + \INFERRED_GEN.data_reg[5][14]_srl6 + (.A0(\INFERRED_GEN.cnt_i_reg[3]_0 [0]), + .A1(\INFERRED_GEN.cnt_i_reg[3]_0 [1]), + .A2(\INFERRED_GEN.cnt_i_reg[3]_0 [2]), .A3(1'b0), - .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [28]), - .Q(out[29])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][44]_srl4 " *) + .CE(\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ), + .CLK(m_axi_s2mm_aclk), + .D(\GEN_INDET_BTT.lsig_eop_reg_reg [7]), + .Q(out[7])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][15]_srl6 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[5][15]_srl6 + (.A0(\INFERRED_GEN.cnt_i_reg[3]_0 [0]), + .A1(\INFERRED_GEN.cnt_i_reg[3]_0 [1]), + .A2(\INFERRED_GEN.cnt_i_reg[3]_0 [2]), + .A3(1'b0), + .CE(\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ), + .CLK(m_axi_s2mm_aclk), + .D(\GEN_INDET_BTT.lsig_eop_reg_reg [8]), + .Q(out[8])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][16]_srl6 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[5][16]_srl6 + (.A0(\INFERRED_GEN.cnt_i_reg[3]_0 [0]), + .A1(\INFERRED_GEN.cnt_i_reg[3]_0 [1]), + .A2(\INFERRED_GEN.cnt_i_reg[3]_0 [2]), + .A3(1'b0), + .CE(\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ), + .CLK(m_axi_s2mm_aclk), + .D(\GEN_INDET_BTT.lsig_eop_reg_reg [9]), + .Q(out[9])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][17]_srl6 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[5][17]_srl6 + (.A0(\INFERRED_GEN.cnt_i_reg[3]_0 [0]), + .A1(\INFERRED_GEN.cnt_i_reg[3]_0 [1]), + .A2(\INFERRED_GEN.cnt_i_reg[3]_0 [2]), + .A3(1'b0), + .CE(\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ), + .CLK(m_axi_s2mm_aclk), + .D(\GEN_INDET_BTT.lsig_eop_reg_reg [10]), + .Q(out[10])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][18]_srl6 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[5][18]_srl6 + (.A0(\INFERRED_GEN.cnt_i_reg[3]_0 [0]), + .A1(\INFERRED_GEN.cnt_i_reg[3]_0 [1]), + .A2(\INFERRED_GEN.cnt_i_reg[3]_0 [2]), + .A3(1'b0), + .CE(\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ), + .CLK(m_axi_s2mm_aclk), + .D(\GEN_INDET_BTT.lsig_eop_reg_reg [11]), + .Q(out[11])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][19]_srl6 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[5][19]_srl6 + (.A0(\INFERRED_GEN.cnt_i_reg[3]_0 [0]), + .A1(\INFERRED_GEN.cnt_i_reg[3]_0 [1]), + .A2(\INFERRED_GEN.cnt_i_reg[3]_0 [2]), + .A3(1'b0), + .CE(\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ), + .CLK(m_axi_s2mm_aclk), + .D(\GEN_INDET_BTT.lsig_eop_reg_reg [12]), + .Q(out[12])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][20]_srl6 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[5][20]_srl6 + (.A0(\INFERRED_GEN.cnt_i_reg[3]_0 [0]), + .A1(\INFERRED_GEN.cnt_i_reg[3]_0 [1]), + .A2(\INFERRED_GEN.cnt_i_reg[3]_0 [2]), + .A3(1'b0), + .CE(\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ), + .CLK(m_axi_s2mm_aclk), + .D(\GEN_INDET_BTT.lsig_eop_reg_reg [13]), + .Q(out[13])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][21]_srl6 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[5][21]_srl6 + (.A0(\INFERRED_GEN.cnt_i_reg[3]_0 [0]), + .A1(\INFERRED_GEN.cnt_i_reg[3]_0 [1]), + .A2(\INFERRED_GEN.cnt_i_reg[3]_0 [2]), + .A3(1'b0), + .CE(\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ), + .CLK(m_axi_s2mm_aclk), + .D(\GEN_INDET_BTT.lsig_eop_reg_reg [14]), + .Q(out[14])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][22]_srl6 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][44]_srl4 - (.A0(Q[0]), - .A1(Q[1]), - .A2(1'b0), + \INFERRED_GEN.data_reg[5][22]_srl6 + (.A0(\INFERRED_GEN.cnt_i_reg[3]_0 [0]), + .A1(\INFERRED_GEN.cnt_i_reg[3]_0 [1]), + .A2(\INFERRED_GEN.cnt_i_reg[3]_0 [2]), .A3(1'b0), - .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [29]), - .Q(out[30])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][45]_srl4 " *) + .CE(\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ), + .CLK(m_axi_s2mm_aclk), + .D(\GEN_INDET_BTT.lsig_eop_reg_reg [15]), + .Q(out[15])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][4]_srl6 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][45]_srl4 - (.A0(Q[0]), - .A1(Q[1]), - .A2(1'b0), + \INFERRED_GEN.data_reg[5][4]_srl6 + (.A0(\INFERRED_GEN.cnt_i_reg[3]_0 [0]), + .A1(\INFERRED_GEN.cnt_i_reg[3]_0 [1]), + .A2(\INFERRED_GEN.cnt_i_reg[3]_0 [2]), .A3(1'b0), - .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [30]), - .Q(out[31])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][46]_srl4 " *) + .CE(\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ), + .CLK(m_axi_s2mm_aclk), + .D(\GEN_INDET_BTT.lsig_eop_reg_reg [0]), + .Q(out[0])); + LUT3 #( + .INIT(8'h20)) + \INFERRED_GEN.data_reg[5][4]_srl6_i_1 + (.I0(sig_data2wsc_valid), + .I1(FIFO_Full_reg), + .I2(sig_inhibit_rdy_n), + .O(\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg )); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][5]_srl6 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][46]_srl4 - (.A0(Q[0]), - .A1(Q[1]), - .A2(1'b0), + \INFERRED_GEN.data_reg[5][5]_srl6 + (.A0(\INFERRED_GEN.cnt_i_reg[3]_0 [0]), + .A1(\INFERRED_GEN.cnt_i_reg[3]_0 [1]), + .A2(\INFERRED_GEN.cnt_i_reg[3]_0 [2]), .A3(1'b0), - .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [31]), - .Q(out[32])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][47]_srl4 " *) + .CE(\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ), + .CLK(m_axi_s2mm_aclk), + .D(\GEN_INDET_BTT.lsig_eop_reg_reg [1]), + .Q(out[1])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][9]_srl6 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][47]_srl4 - (.A0(Q[0]), - .A1(Q[1]), - .A2(1'b0), + \INFERRED_GEN.data_reg[5][9]_srl6 + (.A0(\INFERRED_GEN.cnt_i_reg[3]_0 [0]), + .A1(\INFERRED_GEN.cnt_i_reg[3]_0 [1]), + .A2(\INFERRED_GEN.cnt_i_reg[3]_0 [2]), .A3(1'b0), - .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [32]), - .Q(out[33])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][48]_srl4 " *) + .CE(\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ), + .CLK(m_axi_s2mm_aclk), + .D(\GEN_INDET_BTT.lsig_eop_reg_reg [2]), + .Q(out[2])); + LUT6 #( + .INIT(64'hDD2022DDDD2222DD)) + \sig_wdc_statcnt[1]_i_1 + (.I0(\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ), + .I1(\sig_wdc_statcnt_reg[3] ), + .I2(Q[3]), + .I3(Q[0]), + .I4(Q[1]), + .I5(Q[2]), + .O(D[0])); + LUT5 #( + .INIT(32'hDF20F20D)) + \sig_wdc_statcnt[2]_i_1 + (.I0(\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ), + .I1(\sig_wdc_statcnt_reg[3] ), + .I2(Q[0]), + .I3(Q[2]), + .I4(Q[1]), + .O(D[1])); + LUT6 #( + .INIT(64'h0000FFFEFFDF0000)) + \sig_wdc_statcnt[3]_i_1 + (.I0(Q[1]), + .I1(Q[0]), + .I2(Q[2]), + .I3(Q[3]), + .I4(\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ), + .I5(\sig_wdc_statcnt_reg[3] ), + .O(E)); + LUT6 #( + .INIT(64'hDFFF2000FFBA0045)) + \sig_wdc_statcnt[3]_i_2 + (.I0(Q[0]), + .I1(\sig_wdc_statcnt_reg[3] ), + .I2(\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ), + .I3(Q[1]), + .I4(Q[3]), + .I5(Q[2]), + .O(D[2])); +endmodule + +(* ORIG_REF_NAME = "dynshreg_f" *) +module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized7 + (\FSM_sequential_sig_cmdcntl_sm_state_reg[0] , + out, + sig_wr_fifo, + \GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg , + sig_sm_pop_cmd_fifo_ns, + D, + Q, + p_9_out_0, + FIFO_Full_reg, + sig_inhibit_rdy_n_reg, + lsig_cmd_fetch_pause, + E, + sig_need_cmd_flush, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_good_tlast_dbeat37_out__0, + \FSM_sequential_sig_cmdcntl_sm_state_reg[0]_0 , + p_7_out, + \FSM_sequential_sig_cmdcntl_sm_state_reg[2] , + in, + m_axi_s2mm_aclk); + output \FSM_sequential_sig_cmdcntl_sm_state_reg[0] ; + output [20:0]out; + output sig_wr_fifo; + output \GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg ; + output sig_sm_pop_cmd_fifo_ns; + output [0:0]D; + input [2:0]Q; + input p_9_out_0; + input FIFO_Full_reg; + input sig_inhibit_rdy_n_reg; + input lsig_cmd_fetch_pause; + input [0:0]E; + input sig_need_cmd_flush; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_good_tlast_dbeat37_out__0; + input \FSM_sequential_sig_cmdcntl_sm_state_reg[0]_0 ; + input p_7_out; + input [2:0]\FSM_sequential_sig_cmdcntl_sm_state_reg[2] ; + input [21:0]in; + input m_axi_s2mm_aclk; + + wire [0:0]D; + wire [0:0]E; + wire FIFO_Full_reg; + wire \FSM_sequential_sig_cmdcntl_sm_state[1]_i_2_n_0 ; + wire \FSM_sequential_sig_cmdcntl_sm_state_reg[0] ; + wire \FSM_sequential_sig_cmdcntl_sm_state_reg[0]_0 ; + wire [2:0]\FSM_sequential_sig_cmdcntl_sm_state_reg[2] ; + wire \GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg ; + wire [2:0]Q; + wire [21:0]in; + wire lsig_cmd_fetch_pause; + wire m_axi_s2mm_aclk; + wire [20:0]out; + wire p_7_out; + wire p_9_out_0; + wire [24:24]sig_cmd_fifo_data_out; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_good_tlast_dbeat37_out__0; + wire sig_inhibit_rdy_n_reg; + wire sig_need_cmd_flush; + wire sig_sm_pop_cmd_fifo_ns; + wire sig_wr_fifo; + + (* SOFT_HLUTNM = "soft_lutpair235" *) + LUT2 #( + .INIT(4'h2)) + \FSM_sequential_sig_cmdcntl_sm_state[0]_i_4 + (.I0(out[17]), + .I1(Q[2]), + .O(\FSM_sequential_sig_cmdcntl_sm_state_reg[0] )); + LUT5 #( + .INIT(32'h00045504)) + \FSM_sequential_sig_cmdcntl_sm_state[1]_i_1 + (.I0(\FSM_sequential_sig_cmdcntl_sm_state_reg[2] [2]), + .I1(\FSM_sequential_sig_cmdcntl_sm_state_reg[2] [1]), + .I2(sig_cmd_fifo_data_out), + .I3(\FSM_sequential_sig_cmdcntl_sm_state_reg[2] [0]), + .I4(\FSM_sequential_sig_cmdcntl_sm_state[1]_i_2_n_0 ), + .O(D)); + (* SOFT_HLUTNM = "soft_lutpair235" *) + LUT5 #( + .INIT(32'h0FFB0AFB)) + \FSM_sequential_sig_cmdcntl_sm_state[1]_i_2 + (.I0(out[17]), + .I1(p_7_out), + .I2(Q[2]), + .I3(\FSM_sequential_sig_cmdcntl_sm_state_reg[2] [1]), + .I4(sig_need_cmd_flush), + .O(\FSM_sequential_sig_cmdcntl_sm_state[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'h00000000AAAE0000)) + \GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_i_1 + (.I0(lsig_cmd_fetch_pause), + .I1(E), + .I2(sig_cmd_fifo_data_out), + .I3(sig_need_cmd_flush), + .I4(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I5(sig_good_tlast_dbeat37_out__0), + .O(\GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg )); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][10]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][48]_srl4 + \INFERRED_GEN.data_reg[3][10]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [33]), - .Q(out[34])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][49]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[4]), + .Q(out[4])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][11]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][49]_srl4 + \INFERRED_GEN.data_reg[3][11]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [34]), - .Q(out[35])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][4]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[5]), + .Q(out[5])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][12]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][4]_srl4 + \INFERRED_GEN.data_reg[3][12]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [4]), - .Q(out[4])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][50]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[6]), + .Q(out[6])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][13]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][50]_srl4 + \INFERRED_GEN.data_reg[3][13]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [35]), - .Q(out[36])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][51]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[7]), + .Q(out[7])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][14]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][51]_srl4 + \INFERRED_GEN.data_reg[3][14]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [36]), - .Q(out[37])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][52]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[8]), + .Q(out[8])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][15]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][52]_srl4 + \INFERRED_GEN.data_reg[3][15]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [37]), - .Q(out[38])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][53]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[9]), + .Q(out[9])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][16]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][53]_srl4 + \INFERRED_GEN.data_reg[3][16]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [38]), - .Q(out[39])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][54]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[10]), + .Q(out[10])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][17]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][54]_srl4 + \INFERRED_GEN.data_reg[3][17]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [39]), - .Q(out[40])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][55]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[11]), + .Q(out[11])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][18]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][55]_srl4 + \INFERRED_GEN.data_reg[3][18]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [40]), - .Q(out[41])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][56]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[12]), + .Q(out[12])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][19]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][56]_srl4 + \INFERRED_GEN.data_reg[3][19]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [41]), - .Q(out[42])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][57]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[13]), + .Q(out[13])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][20]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][57]_srl4 + \INFERRED_GEN.data_reg[3][20]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [42]), - .Q(out[43])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][58]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[14]), + .Q(out[14])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][21]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][58]_srl4 + \INFERRED_GEN.data_reg[3][21]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [43]), - .Q(out[44])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][59]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[15]), + .Q(out[15])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][23]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][59]_srl4 + \INFERRED_GEN.data_reg[3][23]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [44]), - .Q(out[45])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][5]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[16]), + .Q(out[16])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][24]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][5]_srl4 + \INFERRED_GEN.data_reg[3][24]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [5]), - .Q(out[5])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][60]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[17]), + .Q(sig_cmd_fifo_data_out)); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][25]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][60]_srl4 + \INFERRED_GEN.data_reg[3][25]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [45]), - .Q(out[46])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][61]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[18]), + .Q(out[17])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][26]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][61]_srl4 + \INFERRED_GEN.data_reg[3][26]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [46]), - .Q(out[47])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][62]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[19]), + .Q(out[18])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][27]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][62]_srl4 + \INFERRED_GEN.data_reg[3][27]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [47]), - .Q(out[48])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][63]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[20]), + .Q(out[19])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][28]_srl4 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][63]_srl4 + \INFERRED_GEN.data_reg[3][28]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [48]), - .Q(out[49])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][6]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[21]), + .Q(out[20])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][6]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][6]_srl4 @@ -26829,11 +69030,18 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [6]), - .Q(out[6])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][7]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[0]), + .Q(out[0])); + LUT3 #( + .INIT(8'h20)) + \INFERRED_GEN.data_reg[3][6]_srl4_i_1__0 + (.I0(p_9_out_0), + .I1(FIFO_Full_reg), + .I2(sig_inhibit_rdy_n_reg), + .O(sig_wr_fifo)); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][7]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][7]_srl4 @@ -26842,11 +69050,11 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [7]), - .Q(out[7])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][8]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[1]), + .Q(out[1])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][8]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][8]_srl4 @@ -26855,11 +69063,11 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [8]), - .Q(out[8])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][9]_srl4 " *) + .CLK(m_axi_s2mm_aclk), + .D(in[2]), + .Q(out[2])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][9]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][9]_srl4 @@ -26868,191 +69076,238 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f .A2(1'b0), .A3(1'b0), .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(\s_axis_cmd_tdata_reg[63] [9]), - .Q(out[9])); + .CLK(m_axi_s2mm_aclk), + .D(in[3]), + .Q(out[3])); LUT6 #( - .INIT(64'hFFFFFFFF00010000)) - sig_calc_error_reg_i_1 - (.I0(sig_calc_error_reg_i_2_n_0), - .I1(sig_calc_error_reg_i_3_n_0), + .INIT(64'h0202020002000200)) + sig_sm_pop_cmd_fifo_i_1 + (.I0(\FSM_sequential_sig_cmdcntl_sm_state_reg[0]_0 ), + .I1(out[17]), .I2(Q[2]), - .I3(sig_sm_halt_reg), - .I4(sig_input_reg_empty), - .I5(in), - .O(sig_calc_error_reg_reg)); - LUT5 #( - .INIT(32'hFFFFFFFE)) - sig_calc_error_reg_i_2 - (.I0(out[13]), - .I1(out[12]), - .I2(out[14]), - .I3(out[15]), - .I4(sig_calc_error_reg_i_4_n_0), - .O(sig_calc_error_reg_i_2_n_0)); - LUT5 #( - .INIT(32'hFFFFFFFE)) - sig_calc_error_reg_i_3 - (.I0(out[5]), - .I1(out[4]), - .I2(out[7]), - .I3(out[6]), - .I4(sig_calc_error_reg_i_5_n_0), - .O(sig_calc_error_reg_i_3_n_0)); - LUT4 #( - .INIT(16'hFFFE)) - sig_calc_error_reg_i_4 - (.I0(out[10]), - .I1(out[11]), - .I2(out[8]), - .I3(out[9]), - .O(sig_calc_error_reg_i_4_n_0)); - LUT4 #( - .INIT(16'hFFFE)) - sig_calc_error_reg_i_5 - (.I0(out[2]), - .I1(out[3]), - .I2(out[0]), - .I3(out[1]), - .O(sig_calc_error_reg_i_5_n_0)); + .I3(p_7_out), + .I4(\FSM_sequential_sig_cmdcntl_sm_state_reg[2] [1]), + .I5(sig_need_cmd_flush), + .O(sig_sm_pop_cmd_fifo_ns)); endmodule (* ORIG_REF_NAME = "dynshreg_f" *) -module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized0 - (sig_wr_fifo, - interr_i_reg, - slverr_i_reg, - decerr_i_reg, - sig_rsc2stat_status_valid, - FIFO_Full_reg, - sig_inhibit_rdy_n_reg, +module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized8 + (\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] , + out, + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] , + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] , + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] , + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] , + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] , + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] , + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] , + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 , + sig_m_valid_out_reg, + sig_strm_tlast, + sig_eop_halt_xfer, Q, - sig_rd_sts_slverr_reg_reg, - m_axi_mm2s_aclk); - output sig_wr_fifo; - output interr_i_reg; - output slverr_i_reg; - output decerr_i_reg; - input sig_rsc2stat_status_valid; - input FIFO_Full_reg; - input sig_inhibit_rdy_n_reg; - input [2:0]Q; - input [2:0]sig_rd_sts_slverr_reg_reg; - input m_axi_mm2s_aclk; + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 , + p_0_in, + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 , + sel, + in, + m_axi_s2mm_aclk); + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] ; + output [1:0]out; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] ; + input \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ; + input sig_m_valid_out_reg; + input sig_strm_tlast; + input sig_eop_halt_xfer; + input [4:0]Q; + input \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ; + input p_0_in; + input \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ; + input sel; + input [1:0]in; + input m_axi_s2mm_aclk; - wire FIFO_Full_reg; - wire [2:0]Q; - wire decerr_i_reg; - wire interr_i_reg; - wire m_axi_mm2s_aclk; - wire [6:4]m_axis_mm2s_sts_tdata; - wire sig_inhibit_rdy_n_reg; - wire [2:0]sig_rd_sts_slverr_reg_reg; - wire sig_rsc2stat_status_valid; - wire sig_wr_fifo; - wire slverr_i_reg; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ; + wire [4:0]Q; + wire [1:0]in; + wire m_axi_s2mm_aclk; + wire [1:0]out; + wire p_0_in; + wire sel; + wire sig_eop_halt_xfer; + wire sig_m_valid_out_reg; + wire sig_strm_tlast; - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][4]_srl4 " *) - SRL16E #( - .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][4]_srl4 - (.A0(Q[0]), - .A1(Q[1]), - .A2(1'b0), - .A3(1'b0), - .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(sig_rd_sts_slverr_reg_reg[0]), - .Q(m_axis_mm2s_sts_tdata[4])); - LUT3 #( - .INIT(8'h20)) - \INFERRED_GEN.data_reg[3][4]_srl4_i_1__0 - (.I0(sig_rsc2stat_status_valid), - .I1(FIFO_Full_reg), - .I2(sig_inhibit_rdy_n_reg), - .O(sig_wr_fifo)); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][5]_srl4 " *) + LUT6 #( + .INIT(64'h000000000000A080)) + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg[0][1]_i_2 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ), + .I1(out[1]), + .I2(sig_m_valid_out_reg), + .I3(sig_strm_tlast), + .I4(sig_eop_halt_xfer), + .I5(Q[4]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] )); + LUT6 #( + .INIT(64'h000000000000A080)) + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg[1][1]_i_2 + (.I0(p_0_in), + .I1(out[1]), + .I2(sig_m_valid_out_reg), + .I3(sig_strm_tlast), + .I4(sig_eop_halt_xfer), + .I5(Q[4]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] )); + LUT6 #( + .INIT(64'h000000000000A080)) + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg[2][1]_i_2 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ), + .I1(out[1]), + .I2(sig_m_valid_out_reg), + .I3(sig_strm_tlast), + .I4(sig_eop_halt_xfer), + .I5(Q[4]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] )); + LUT6 #( + .INIT(64'h000000000000A080)) + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg[3][1]_i_2 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ), + .I1(out[1]), + .I2(sig_m_valid_out_reg), + .I3(sig_strm_tlast), + .I4(sig_eop_halt_xfer), + .I5(Q[4]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] )); + LUT6 #( + .INIT(64'h000000000000A080)) + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg[4][1]_i_2 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ), + .I1(out[1]), + .I2(sig_m_valid_out_reg), + .I3(sig_strm_tlast), + .I4(sig_eop_halt_xfer), + .I5(Q[4]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] )); + LUT6 #( + .INIT(64'h000000000000A080)) + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg[5][1]_i_2 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ), + .I1(out[1]), + .I2(sig_m_valid_out_reg), + .I3(sig_strm_tlast), + .I4(sig_eop_halt_xfer), + .I5(Q[4]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] )); + LUT6 #( + .INIT(64'h000000000000A080)) + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg[6][1]_i_2 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ), + .I1(out[1]), + .I2(sig_m_valid_out_reg), + .I3(sig_strm_tlast), + .I4(sig_eop_halt_xfer), + .I5(Q[4]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] )); + LUT6 #( + .INIT(64'h000000000000A080)) + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg[7][1]_i_2 + (.I0(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ), + .I1(out[1]), + .I2(sig_m_valid_out_reg), + .I3(sig_strm_tlast), + .I4(sig_eop_halt_xfer), + .I5(Q[4]), + .O(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] )); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][2]_srl16 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][5]_srl4 + \INFERRED_GEN.data_reg[15][2]_srl16 (.A0(Q[0]), .A1(Q[1]), - .A2(1'b0), - .A3(1'b0), - .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(sig_rd_sts_slverr_reg_reg[1]), - .Q(m_axis_mm2s_sts_tdata[5])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][6]_srl4 " *) + .A2(Q[2]), + .A3(Q[3]), + .CE(sel), + .CLK(m_axi_s2mm_aclk), + .D(in[0]), + .Q(out[0])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][3]_srl16 " *) SRL16E #( .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][6]_srl4 + \INFERRED_GEN.data_reg[15][3]_srl16 (.A0(Q[0]), .A1(Q[1]), - .A2(1'b0), - .A3(1'b0), - .CE(sig_wr_fifo), - .CLK(m_axi_mm2s_aclk), - .D(sig_rd_sts_slverr_reg_reg[2]), - .Q(m_axis_mm2s_sts_tdata[6])); - LUT2 #( - .INIT(4'h2)) - decerr_i_i_1 - (.I0(m_axis_mm2s_sts_tdata[5]), - .I1(Q[2]), - .O(decerr_i_reg)); - (* SOFT_HLUTNM = "soft_lutpair74" *) - LUT2 #( - .INIT(4'h2)) - interr_i_i_1 - (.I0(m_axis_mm2s_sts_tdata[4]), - .I1(Q[2]), - .O(interr_i_reg)); - (* SOFT_HLUTNM = "soft_lutpair74" *) - LUT2 #( - .INIT(4'h2)) - slverr_i_i_1 - (.I0(m_axis_mm2s_sts_tdata[6]), - .I1(Q[2]), - .O(slverr_i_reg)); + .A2(Q[2]), + .A3(Q[3]), + .CE(sel), + .CLK(m_axi_s2mm_aclk), + .D(in[1]), + .Q(out[1])); endmodule (* ORIG_REF_NAME = "dynshreg_f" *) -module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 - (sig_calc_error_reg_reg, - sig_addr_valid_reg_reg, +module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized9 + (p_0_in, out, - sig_mstr2addr_cmd_valid, + sig_wr_fifo, + p_22_out, FIFO_Full_reg, - sig_inhibit_rdy_n, + sig_inhibit_rdy_n_reg, in, Q, - m_axi_mm2s_aclk); - output sig_calc_error_reg_reg; - output sig_addr_valid_reg_reg; - output [39:0]out; - input sig_mstr2addr_cmd_valid; + m_axi_s2mm_aclk); + output p_0_in; + output [41:0]out; + output sig_wr_fifo; + input p_22_out; input FIFO_Full_reg; - input sig_inhibit_rdy_n; - input [37:0]in; + input sig_inhibit_rdy_n_reg; + input [39:0]in; input [1:0]Q; - input m_axi_mm2s_aclk; + input m_axi_s2mm_aclk; wire FIFO_Full_reg; wire [1:0]Q; - wire [37:0]in; - wire m_axi_mm2s_aclk; - wire [39:0]out; - wire sig_addr_valid_reg_reg; - wire sig_calc_error_reg_reg; - wire sig_inhibit_rdy_n; - wire sig_mstr2addr_cmd_valid; + wire [39:0]in; + wire m_axi_s2mm_aclk; + wire [41:0]out; + wire p_0_in; + wire p_22_out; + wire sig_inhibit_rdy_n_reg; + wire sig_wr_fifo; - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][10]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][10]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][10]_srl4 @@ -27060,12 +69315,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[6]), .Q(out[6])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][11]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][11]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][11]_srl4 @@ -27073,25 +69328,25 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[7]), .Q(out[7])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][12]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][12]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][12]_srl4 (.A0(Q[0]), .A1(Q[1]), .A2(1'b0), - .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[8]), .Q(out[8])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][13]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][13]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][13]_srl4 @@ -27099,12 +69354,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[9]), .Q(out[9])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][14]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][14]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][14]_srl4 @@ -27112,12 +69367,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[10]), .Q(out[10])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][15]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][15]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][15]_srl4 @@ -27125,12 +69380,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[11]), .Q(out[11])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][16]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][16]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][16]_srl4 @@ -27138,12 +69393,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[12]), .Q(out[12])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][17]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][17]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][17]_srl4 @@ -27151,12 +69406,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[13]), .Q(out[13])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][18]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][18]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][18]_srl4 @@ -27164,12 +69419,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[14]), .Q(out[14])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][19]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][19]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][19]_srl4 @@ -27177,12 +69432,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[15]), .Q(out[15])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][20]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][20]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][20]_srl4 @@ -27190,12 +69445,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[16]), .Q(out[16])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][21]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][21]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][21]_srl4 @@ -27203,12 +69458,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[17]), .Q(out[17])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][22]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][22]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][22]_srl4 @@ -27216,12 +69471,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[18]), .Q(out[18])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][23]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][23]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][23]_srl4 @@ -27229,12 +69484,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[19]), .Q(out[19])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][24]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][24]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][24]_srl4 @@ -27242,12 +69497,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[20]), .Q(out[20])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][25]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][25]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][25]_srl4 @@ -27255,12 +69510,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[21]), .Q(out[21])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][26]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][26]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][26]_srl4 @@ -27268,12 +69523,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[22]), .Q(out[22])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][27]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][27]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][27]_srl4 @@ -27281,12 +69536,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[23]), .Q(out[23])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][28]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][28]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][28]_srl4 @@ -27294,12 +69549,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[24]), .Q(out[24])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][29]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][29]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][29]_srl4 @@ -27307,12 +69562,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[25]), .Q(out[25])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][30]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][30]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][30]_srl4 @@ -27320,12 +69575,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[26]), .Q(out[26])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][31]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][31]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][31]_srl4 @@ -27333,12 +69588,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[27]), .Q(out[27])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][32]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][32]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][32]_srl4 @@ -27346,12 +69601,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[28]), .Q(out[28])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][33]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][33]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][33]_srl4 @@ -27359,12 +69614,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[29]), .Q(out[29])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][34]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][34]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][34]_srl4 @@ -27372,12 +69627,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[30]), .Q(out[30])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][35]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][35]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][35]_srl4 @@ -27385,12 +69640,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[31]), .Q(out[31])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][36]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][36]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][36]_srl4 @@ -27398,12 +69653,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[32]), .Q(out[32])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][37]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][37]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][37]_srl4 @@ -27411,12 +69666,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[33]), .Q(out[33])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][38]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][38]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][38]_srl4 @@ -27424,12 +69679,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[34]), .Q(out[34])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][39]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][39]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][39]_srl4 @@ -27437,12 +69692,38 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[35]), .Q(out[35])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][44]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][40]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][40]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(in[36]), + .Q(out[36])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][41]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \INFERRED_GEN.data_reg[3][41]_srl4 + (.A0(Q[0]), + .A1(Q[1]), + .A2(1'b0), + .A3(1'b0), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(in[37]), + .Q(out[37])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][44]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][44]_srl4 @@ -27450,12 +69731,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(1'b1), - .Q(out[36])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][45]_srl4 " *) + .Q(out[38])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][45]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][45]_srl4 @@ -27463,12 +69744,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(1'b1), - .Q(out[37])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][47]_srl4 " *) + .Q(out[39])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][47]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][47]_srl4 @@ -27476,12 +69757,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), - .D(in[36]), - .Q(out[38])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][4]_srl4 " *) + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(in[38]), + .Q(out[40])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][4]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][4]_srl4 @@ -27489,19 +69770,19 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[0]), .Q(out[0])); LUT3 #( .INIT(8'h20)) - \INFERRED_GEN.data_reg[3][4]_srl4_i_1 - (.I0(sig_mstr2addr_cmd_valid), + \INFERRED_GEN.data_reg[3][4]_srl4_i_1__1 + (.I0(p_22_out), .I1(FIFO_Full_reg), - .I2(sig_inhibit_rdy_n), - .O(sig_calc_error_reg_reg)); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][50]_srl4 " *) + .I2(sig_inhibit_rdy_n_reg), + .O(sig_wr_fifo)); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][50]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][50]_srl4 @@ -27509,12 +69790,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), - .D(in[37]), - .Q(out[39])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][5]_srl4 " *) + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), + .D(in[39]), + .Q(out[41])); + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][5]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][5]_srl4 @@ -27522,12 +69803,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[1]), .Q(out[1])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][6]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][6]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][6]_srl4 @@ -27535,12 +69816,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[2]), .Q(out[2])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][7]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][7]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][7]_srl4 @@ -27548,12 +69829,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[3]), .Q(out[3])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][8]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][8]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][8]_srl4 @@ -27561,12 +69842,12 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[4]), .Q(out[4])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][9]_srl4 " *) + (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) + (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][9]_srl4 " *) SRL16E #( .INIT(16'h0000)) \INFERRED_GEN.data_reg[3][9]_srl4 @@ -27574,316 +69855,1440 @@ module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 .A1(Q[1]), .A2(1'b0), .A3(1'b0), - .CE(sig_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), + .CE(sig_wr_fifo), + .CLK(m_axi_s2mm_aclk), .D(in[5]), .Q(out[5])); LUT1 #( .INIT(2'h1)) - sig_addr_valid_reg_i_1 - (.I0(out[39]), - .O(sig_addr_valid_reg_reg)); + sig_addr_valid_reg_i_1__0 + (.I0(out[41]), + .O(p_0_in)); +endmodule + +(* ORIG_REF_NAME = "srl_fifo_f" *) +module Arty_Z7_20_axi_vdma_0_0_srl_fifo_f + (sig_calc_error_reg_reg, + Q, + s_axis_cmd_tvalid_reg, + out, + sig_stream_rst, + m_axi_s2mm_aclk, + sig_psm_halt, + sig_input_reg_empty, + p_10_out, + cmnd_wr_1, + sig_inhibit_rdy_n, + s2mm_halt, + s_axis_s2mm_cmd_tvalid, + \s_axis_cmd_tdata_reg[63] ); + output sig_calc_error_reg_reg; + output [0:0]Q; + output [0:0]s_axis_cmd_tvalid_reg; + output [49:0]out; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input sig_psm_halt; + input sig_input_reg_empty; + input p_10_out; + input cmnd_wr_1; + input sig_inhibit_rdy_n; + input s2mm_halt; + input s_axis_s2mm_cmd_tvalid; + input [48:0]\s_axis_cmd_tdata_reg[63] ; + + wire [0:0]Q; + wire cmnd_wr_1; + wire m_axi_s2mm_aclk; + wire [49:0]out; + wire p_10_out; + wire s2mm_halt; + wire [48:0]\s_axis_cmd_tdata_reg[63] ; + wire [0:0]s_axis_cmd_tvalid_reg; + wire s_axis_s2mm_cmd_tvalid; + wire sig_calc_error_reg_reg; + wire sig_inhibit_rdy_n; + wire sig_input_reg_empty; + wire sig_psm_halt; + wire sig_stream_rst; + + Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f I_SRL_FIFO_RBU_F + (.Q(Q), + .cmnd_wr_1(cmnd_wr_1), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out), + .p_10_out(p_10_out), + .s2mm_halt(s2mm_halt), + .\s_axis_cmd_tdata_reg[63] (\s_axis_cmd_tdata_reg[63] ), + .s_axis_cmd_tvalid_reg(s_axis_cmd_tvalid_reg), + .s_axis_s2mm_cmd_tvalid(s_axis_s2mm_cmd_tvalid), + .sig_calc_error_reg_reg(sig_calc_error_reg_reg), + .sig_inhibit_rdy_n(sig_inhibit_rdy_n), + .sig_input_reg_empty(sig_input_reg_empty), + .sig_psm_halt(sig_psm_halt), + .sig_stream_rst(sig_stream_rst)); +endmodule + +(* ORIG_REF_NAME = "srl_fifo_f" *) +module Arty_Z7_20_axi_vdma_0_0_srl_fifo_f_23 + (sig_calc_error_reg_reg, + Q, + E, + out, + SR, + m_axi_mm2s_aclk, + in, + sig_sm_halt_reg, + sig_input_reg_empty, + cmnd_wr, + sig_inhibit_rdy_n, + mm2s_halt, + sig_calc_error_pushed_reg, + sig_calc_error_pushed, + p_56_out, + \s_axis_cmd_tdata_reg[63] ); + output sig_calc_error_reg_reg; + output [0:0]Q; + output [0:0]E; + output [49:0]out; + input [0:0]SR; + input m_axi_mm2s_aclk; + input [0:0]in; + input sig_sm_halt_reg; + input sig_input_reg_empty; + input cmnd_wr; + input sig_inhibit_rdy_n; + input mm2s_halt; + input sig_calc_error_pushed_reg; + input sig_calc_error_pushed; + input p_56_out; + input [48:0]\s_axis_cmd_tdata_reg[63] ; + + wire [0:0]E; + wire [0:0]Q; + wire [0:0]SR; + wire cmnd_wr; + wire [0:0]in; + wire m_axi_mm2s_aclk; + wire mm2s_halt; + wire [49:0]out; + wire p_56_out; + wire [48:0]\s_axis_cmd_tdata_reg[63] ; + wire sig_calc_error_pushed; + wire sig_calc_error_pushed_reg; + wire sig_calc_error_reg_reg; + wire sig_inhibit_rdy_n; + wire sig_input_reg_empty; + wire sig_sm_halt_reg; + + Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f_24 I_SRL_FIFO_RBU_F + (.E(E), + .Q(Q), + .SR(SR), + .cmnd_wr(cmnd_wr), + .in(in), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .mm2s_halt(mm2s_halt), + .out(out), + .p_56_out(p_56_out), + .\s_axis_cmd_tdata_reg[63] (\s_axis_cmd_tdata_reg[63] ), + .sig_calc_error_pushed(sig_calc_error_pushed), + .sig_calc_error_pushed_reg(sig_calc_error_pushed_reg), + .sig_calc_error_reg_reg(sig_calc_error_reg_reg), + .sig_inhibit_rdy_n(sig_inhibit_rdy_n), + .sig_input_reg_empty(sig_input_reg_empty), + .sig_sm_halt_reg(sig_sm_halt_reg)); +endmodule + +(* ORIG_REF_NAME = "srl_fifo_f" *) +module Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized0 + (\INFERRED_GEN.cnt_i_reg[1] , + sig_rd_sts_slverr_reg_reg, + decerr_i_reg, + Q, + slverr_i_reg, + interr_i_reg, + SR, + m_axi_mm2s_aclk, + sig_inhibit_rdy_n_reg, + sig_rsc2stat_status_valid, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + p_58_out, + sts_tready_reg, + sig_rd_sts_slverr_reg_reg_0); + output \INFERRED_GEN.cnt_i_reg[1] ; + output sig_rd_sts_slverr_reg_reg; + output decerr_i_reg; + output [0:0]Q; + output slverr_i_reg; + output interr_i_reg; + input [0:0]SR; + input m_axi_mm2s_aclk; + input sig_inhibit_rdy_n_reg; + input sig_rsc2stat_status_valid; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input p_58_out; + input sts_tready_reg; + input [2:0]sig_rd_sts_slverr_reg_reg_0; + + wire \INFERRED_GEN.cnt_i_reg[1] ; + wire [0:0]Q; + wire [0:0]SR; + wire decerr_i_reg; + wire interr_i_reg; + wire m_axi_mm2s_aclk; + wire p_58_out; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_inhibit_rdy_n_reg; + wire sig_rd_sts_slverr_reg_reg; + wire [2:0]sig_rd_sts_slverr_reg_reg_0; + wire sig_rsc2stat_status_valid; + wire slverr_i_reg; + wire sts_tready_reg; + + Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized0 I_SRL_FIFO_RBU_F + (.\INFERRED_GEN.cnt_i_reg[1] (\INFERRED_GEN.cnt_i_reg[1] ), + .Q(Q), + .SR(SR), + .decerr_i_reg(decerr_i_reg), + .interr_i_reg(interr_i_reg), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .p_58_out(p_58_out), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_inhibit_rdy_n_reg(sig_inhibit_rdy_n_reg), + .sig_rd_sts_slverr_reg_reg(sig_rd_sts_slverr_reg_reg), + .sig_rd_sts_slverr_reg_reg_0(sig_rd_sts_slverr_reg_reg_0), + .sig_rsc2stat_status_valid(sig_rsc2stat_status_valid), + .slverr_i_reg(slverr_i_reg), + .sts_tready_reg(sts_tready_reg)); +endmodule + +(* ORIG_REF_NAME = "srl_fifo_f" *) +module Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized1 + (sig_addr_valid_reg_reg, + out, + sig_posted_to_axi_2_reg, + sig_calc_error_reg_reg, + sig_addr_reg_empty_reg, + SR, + m_axi_mm2s_aclk, + sig_addr_reg_empty, + sig_sf_allow_addr_req, + sig_data2addr_stop_req, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_inhibit_rdy_n, + sig_mstr2addr_cmd_valid, + in); + output sig_addr_valid_reg_reg; + output [40:0]out; + output sig_posted_to_axi_2_reg; + output sig_calc_error_reg_reg; + output sig_addr_reg_empty_reg; + input [0:0]SR; + input m_axi_mm2s_aclk; + input sig_addr_reg_empty; + input sig_sf_allow_addr_req; + input sig_data2addr_stop_req; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_inhibit_rdy_n; + input sig_mstr2addr_cmd_valid; + input [38:0]in; + + wire [0:0]SR; + wire [38:0]in; + wire m_axi_mm2s_aclk; + wire [40:0]out; + wire sig_addr_reg_empty; + wire sig_addr_reg_empty_reg; + wire sig_addr_valid_reg_reg; + wire sig_calc_error_reg_reg; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_data2addr_stop_req; + wire sig_inhibit_rdy_n; + wire sig_mstr2addr_cmd_valid; + wire sig_posted_to_axi_2_reg; + wire sig_sf_allow_addr_req; + + Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized1 I_SRL_FIFO_RBU_F + (.SR(SR), + .in(in), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .out(out), + .sel(sig_calc_error_reg_reg), + .sig_addr_reg_empty(sig_addr_reg_empty), + .sig_addr_reg_empty_reg(sig_addr_reg_empty_reg), + .sig_addr_valid_reg_reg(sig_addr_valid_reg_reg), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_data2addr_stop_req(sig_data2addr_stop_req), + .sig_inhibit_rdy_n(sig_inhibit_rdy_n), + .sig_mstr2addr_cmd_valid(sig_mstr2addr_cmd_valid), + .sig_posted_to_axi_2_reg(sig_posted_to_axi_2_reg), + .sig_sf_allow_addr_req(sig_sf_allow_addr_req)); +endmodule + +(* ORIG_REF_NAME = "srl_fifo_f" *) +module Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized10 + (\INFERRED_GEN.cnt_i_reg[0] , + sig_last_dbeat_reg, + sig_dqual_reg_empty_reg, + sig_ld_new_cmd_reg_reg, + sig_next_calc_error_reg_reg, + sig_dqual_reg_empty_reg_0, + D, + E, + sig_dqual_reg_empty_reg_1, + sig_clr_cmd2data_valid4_out__0, + out, + sig_stream_rst, + m_axi_s2mm_aclk, + sig_first_dbeat1__0, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_single_dbeat, + sig_last_dbeat_reg_0, + sig_ld_new_cmd_reg, + sig_next_calc_error_reg, + \sig_dbeat_cntr_reg[1] , + sig_dqual_reg_full_reg, + Q, + \sig_dbeat_cntr_reg[4] , + p_11_out, + sig_inhibit_rdy_n_reg, + \sig_dbeat_cntr_reg[2] , + \sig_dbeat_cntr_reg[3] , + sig_next_sequential_reg, + sig_dqual_reg_empty, + sig_halt_reg, + sig_m_valid_out_reg, + sig_s_ready_out_reg, + sig_wdc_status_going_full, + sig_inhibit_rdy_n_reg_0, + sig_wsc2stat_status_valid, + sig_addr_posted_cntr, + sig_halt_reg_dly3, + sig_last_mmap_dbeat_reg, + sig_posted_to_axi_reg, + sig_xfer_calc_err_reg_reg); + output \INFERRED_GEN.cnt_i_reg[0] ; + output sig_last_dbeat_reg; + output sig_dqual_reg_empty_reg; + output sig_ld_new_cmd_reg_reg; + output sig_next_calc_error_reg_reg; + output sig_dqual_reg_empty_reg_0; + output [7:0]D; + output [0:0]E; + output sig_dqual_reg_empty_reg_1; + output sig_clr_cmd2data_valid4_out__0; + output [2:0]out; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input sig_first_dbeat1__0; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_single_dbeat; + input sig_last_dbeat_reg_0; + input sig_ld_new_cmd_reg; + input sig_next_calc_error_reg; + input \sig_dbeat_cntr_reg[1] ; + input sig_dqual_reg_full_reg; + input [7:0]Q; + input \sig_dbeat_cntr_reg[4] ; + input p_11_out; + input sig_inhibit_rdy_n_reg; + input \sig_dbeat_cntr_reg[2] ; + input \sig_dbeat_cntr_reg[3] ; + input sig_next_sequential_reg; + input sig_dqual_reg_empty; + input sig_halt_reg; + input sig_m_valid_out_reg; + input sig_s_ready_out_reg; + input sig_wdc_status_going_full; + input sig_inhibit_rdy_n_reg_0; + input sig_wsc2stat_status_valid; + input [2:0]sig_addr_posted_cntr; + input sig_halt_reg_dly3; + input sig_last_mmap_dbeat_reg; + input sig_posted_to_axi_reg; + input [8:0]sig_xfer_calc_err_reg_reg; + + wire [7:0]D; + wire [0:0]E; + wire \INFERRED_GEN.cnt_i_reg[0] ; + wire [7:0]Q; + wire m_axi_s2mm_aclk; + wire [2:0]out; + wire p_11_out; + wire [2:0]sig_addr_posted_cntr; + wire sig_clr_cmd2data_valid4_out__0; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire \sig_dbeat_cntr_reg[1] ; + wire \sig_dbeat_cntr_reg[2] ; + wire \sig_dbeat_cntr_reg[3] ; + wire \sig_dbeat_cntr_reg[4] ; + wire sig_dqual_reg_empty; + wire sig_dqual_reg_empty_reg; + wire sig_dqual_reg_empty_reg_0; + wire sig_dqual_reg_empty_reg_1; + wire sig_dqual_reg_full_reg; + wire sig_first_dbeat1__0; + wire sig_halt_reg; + wire sig_halt_reg_dly3; + wire sig_inhibit_rdy_n_reg; + wire sig_inhibit_rdy_n_reg_0; + wire sig_last_dbeat_reg; + wire sig_last_dbeat_reg_0; + wire sig_last_mmap_dbeat_reg; + wire sig_ld_new_cmd_reg; + wire sig_ld_new_cmd_reg_reg; + wire sig_m_valid_out_reg; + wire sig_next_calc_error_reg; + wire sig_next_calc_error_reg_reg; + wire sig_next_sequential_reg; + wire sig_posted_to_axi_reg; + wire sig_s_ready_out_reg; + wire sig_single_dbeat; + wire sig_stream_rst; + wire sig_wdc_status_going_full; + wire sig_wsc2stat_status_valid; + wire [8:0]sig_xfer_calc_err_reg_reg; + + Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized10 I_SRL_FIFO_RBU_F + (.D(D), + .E(E), + .\INFERRED_GEN.cnt_i_reg[0] (\INFERRED_GEN.cnt_i_reg[0] ), + .Q(Q), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out), + .p_11_out(p_11_out), + .sig_addr_posted_cntr(sig_addr_posted_cntr), + .sig_clr_cmd2data_valid4_out__0(sig_clr_cmd2data_valid4_out__0), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .\sig_dbeat_cntr_reg[1] (\sig_dbeat_cntr_reg[1] ), + .\sig_dbeat_cntr_reg[2] (\sig_dbeat_cntr_reg[2] ), + .\sig_dbeat_cntr_reg[3] (\sig_dbeat_cntr_reg[3] ), + .\sig_dbeat_cntr_reg[4] (\sig_dbeat_cntr_reg[4] ), + .sig_dqual_reg_empty(sig_dqual_reg_empty), + .sig_dqual_reg_empty_reg(sig_dqual_reg_empty_reg), + .sig_dqual_reg_empty_reg_0(sig_dqual_reg_empty_reg_0), + .sig_dqual_reg_empty_reg_1(sig_dqual_reg_empty_reg_1), + .sig_dqual_reg_full_reg(sig_dqual_reg_full_reg), + .sig_first_dbeat1__0(sig_first_dbeat1__0), + .sig_halt_reg(sig_halt_reg), + .sig_halt_reg_dly3(sig_halt_reg_dly3), + .sig_inhibit_rdy_n_reg(sig_inhibit_rdy_n_reg), + .sig_inhibit_rdy_n_reg_0(sig_inhibit_rdy_n_reg_0), + .sig_last_dbeat_reg(sig_last_dbeat_reg), + .sig_last_dbeat_reg_0(sig_last_dbeat_reg_0), + .sig_last_mmap_dbeat_reg(sig_last_mmap_dbeat_reg), + .sig_ld_new_cmd_reg(sig_ld_new_cmd_reg), + .sig_ld_new_cmd_reg_reg(sig_ld_new_cmd_reg_reg), + .sig_m_valid_out_reg(sig_m_valid_out_reg), + .sig_next_calc_error_reg(sig_next_calc_error_reg), + .sig_next_calc_error_reg_reg(sig_next_calc_error_reg_reg), + .sig_next_sequential_reg(sig_next_sequential_reg), + .sig_posted_to_axi_reg(sig_posted_to_axi_reg), + .sig_s_ready_out_reg(sig_s_ready_out_reg), + .sig_single_dbeat(sig_single_dbeat), + .sig_stream_rst(sig_stream_rst), + .sig_wdc_status_going_full(sig_wdc_status_going_full), + .sig_wsc2stat_status_valid(sig_wsc2stat_status_valid), + .sig_xfer_calc_err_reg_reg(sig_xfer_calc_err_reg_reg)); endmodule -(* ORIG_REF_NAME = "dynshreg_f" *) -module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized2 - (sig_next_calc_error_reg_reg, - D, +(* ORIG_REF_NAME = "srl_fifo_f" *) +module Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized2 + (D, + sig_dqual_reg_empty_reg, + sig_next_cmd_cmplt_reg_reg, + sig_dqual_reg_empty_reg_0, + sig_next_calc_error_reg_reg, sig_last_dbeat_reg, + E, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram , out, + SR, + m_axi_mm2s_aclk, + Q, + \sig_dbeat_cntr_reg[0] , + m_axi_mm2s_rlast, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, sig_mstr2data_cmd_valid, - FIFO_Full_reg, sig_inhibit_rdy_n_0, - sig_next_sequential_reg_reg, - Q, - sig_halt_reg_reg, - \sig_dbeat_cntr_reg[2] , - sig_dbeat_cntr_eq_1, + \sig_dbeat_cntr_reg[3] , + \sig_dbeat_cntr_reg[5] , + sig_next_sequential_reg, sig_last_dbeat, - in, - \INFERRED_GEN.cnt_i_reg[1] , - m_axi_mm2s_aclk); + sig_dqual_reg_empty, + sig_rsc2stat_status_valid, + FIFO_Full_reg, + sig_inhibit_rdy_n, + sig_next_calc_error_reg_reg_0, + \sig_addr_posted_cntr_reg[2] , + \sig_addr_posted_cntr_reg[1] , + \sig_addr_posted_cntr_reg[0] , + ram_full_i_reg, + sig_halt_reg_reg, + m_axi_mm2s_rvalid, + sig_dqual_reg_full, + sig_data2rsc_valid, + in); + output [7:0]D; + output sig_dqual_reg_empty_reg; + output sig_next_cmd_cmplt_reg_reg; + output sig_dqual_reg_empty_reg_0; output sig_next_calc_error_reg_reg; - output [3:0]D; output sig_last_dbeat_reg; + output [0:0]E; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; output [3:0]out; + input [0:0]SR; + input m_axi_mm2s_aclk; + input [7:0]Q; + input \sig_dbeat_cntr_reg[0] ; + input m_axi_mm2s_rlast; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; input sig_mstr2data_cmd_valid; - input FIFO_Full_reg; input sig_inhibit_rdy_n_0; - input sig_next_sequential_reg_reg; - input [3:0]Q; - input sig_halt_reg_reg; - input \sig_dbeat_cntr_reg[2] ; - input sig_dbeat_cntr_eq_1; + input \sig_dbeat_cntr_reg[3] ; + input \sig_dbeat_cntr_reg[5] ; + input sig_next_sequential_reg; input sig_last_dbeat; - input [7:0]in; - input [1:0]\INFERRED_GEN.cnt_i_reg[1] ; - input m_axi_mm2s_aclk; + input sig_dqual_reg_empty; + input sig_rsc2stat_status_valid; + input FIFO_Full_reg; + input sig_inhibit_rdy_n; + input sig_next_calc_error_reg_reg_0; + input \sig_addr_posted_cntr_reg[2] ; + input \sig_addr_posted_cntr_reg[1] ; + input \sig_addr_posted_cntr_reg[0] ; + input ram_full_i_reg; + input sig_halt_reg_reg; + input m_axi_mm2s_rvalid; + input sig_dqual_reg_full; + input sig_data2rsc_valid; + input [8:0]in; - wire [3:0]D; + wire [7:0]D; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; + wire [0:0]E; wire FIFO_Full_reg; - wire [1:0]\INFERRED_GEN.cnt_i_reg[1] ; - wire [3:0]Q; - wire [7:0]in; + wire [7:0]Q; + wire [0:0]SR; + wire [8:0]in; wire m_axi_mm2s_aclk; + wire m_axi_mm2s_rlast; + wire m_axi_mm2s_rvalid; wire [3:0]out; - wire [10:7]sig_cmd_fifo_data_out; - wire sig_dbeat_cntr_eq_1; - wire \sig_dbeat_cntr_reg[2] ; + wire ram_full_i_reg; + wire \sig_addr_posted_cntr_reg[0] ; + wire \sig_addr_posted_cntr_reg[1] ; + wire \sig_addr_posted_cntr_reg[2] ; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_data2rsc_valid; + wire \sig_dbeat_cntr_reg[0] ; + wire \sig_dbeat_cntr_reg[3] ; + wire \sig_dbeat_cntr_reg[5] ; + wire sig_dqual_reg_empty; + wire sig_dqual_reg_empty_reg; + wire sig_dqual_reg_empty_reg_0; + wire sig_dqual_reg_full; wire sig_halt_reg_reg; + wire sig_inhibit_rdy_n; wire sig_inhibit_rdy_n_0; wire sig_last_dbeat; - wire sig_last_dbeat_i_2_n_0; wire sig_last_dbeat_reg; wire sig_mstr2data_cmd_valid; wire sig_next_calc_error_reg_reg; - wire sig_next_sequential_reg_reg; + wire sig_next_calc_error_reg_reg_0; + wire sig_next_cmd_cmplt_reg_reg; + wire sig_next_sequential_reg; + wire sig_rsc2stat_status_valid; - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][10]_srl4 " *) - SRL16E #( - .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][10]_srl4 - (.A0(\INFERRED_GEN.cnt_i_reg[1] [0]), - .A1(\INFERRED_GEN.cnt_i_reg[1] [1]), - .A2(1'b0), - .A3(1'b0), - .CE(sig_next_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), - .D(in[3]), - .Q(sig_cmd_fifo_data_out[10])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][32]_srl4 " *) - SRL16E #( - .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][32]_srl4 - (.A0(\INFERRED_GEN.cnt_i_reg[1] [0]), - .A1(\INFERRED_GEN.cnt_i_reg[1] [1]), - .A2(1'b0), - .A3(1'b0), - .CE(sig_next_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), - .D(in[4]), - .Q(out[0])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][33]_srl4 " *) - SRL16E #( - .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][33]_srl4 - (.A0(\INFERRED_GEN.cnt_i_reg[1] [0]), - .A1(\INFERRED_GEN.cnt_i_reg[1] [1]), - .A2(1'b0), - .A3(1'b0), - .CE(sig_next_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), - .D(in[5]), - .Q(out[1])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][34]_srl4 " *) - SRL16E #( - .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][34]_srl4 - (.A0(\INFERRED_GEN.cnt_i_reg[1] [0]), - .A1(\INFERRED_GEN.cnt_i_reg[1] [1]), - .A2(1'b0), - .A3(1'b0), - .CE(sig_next_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), - .D(in[6]), - .Q(out[2])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][35]_srl4 " *) - SRL16E #( - .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][35]_srl4 - (.A0(\INFERRED_GEN.cnt_i_reg[1] [0]), - .A1(\INFERRED_GEN.cnt_i_reg[1] [1]), - .A2(1'b0), - .A3(1'b0), - .CE(sig_next_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), - .D(in[7]), - .Q(out[3])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][7]_srl4 " *) - SRL16E #( - .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][7]_srl4 - (.A0(\INFERRED_GEN.cnt_i_reg[1] [0]), - .A1(\INFERRED_GEN.cnt_i_reg[1] [1]), - .A2(1'b0), - .A3(1'b0), - .CE(sig_next_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), - .D(in[0]), - .Q(sig_cmd_fifo_data_out[7])); - LUT3 #( - .INIT(8'h20)) - \INFERRED_GEN.data_reg[3][7]_srl4_i_1__0 - (.I0(sig_mstr2data_cmd_valid), - .I1(FIFO_Full_reg), - .I2(sig_inhibit_rdy_n_0), - .O(sig_next_calc_error_reg_reg)); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][8]_srl4 " *) - SRL16E #( - .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][8]_srl4 - (.A0(\INFERRED_GEN.cnt_i_reg[1] [0]), - .A1(\INFERRED_GEN.cnt_i_reg[1] [1]), - .A2(1'b0), - .A3(1'b0), - .CE(sig_next_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), - .D(in[1]), - .Q(sig_cmd_fifo_data_out[8])); - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][9]_srl4 " *) - SRL16E #( - .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][9]_srl4 - (.A0(\INFERRED_GEN.cnt_i_reg[1] [0]), - .A1(\INFERRED_GEN.cnt_i_reg[1] [1]), - .A2(1'b0), - .A3(1'b0), - .CE(sig_next_calc_error_reg_reg), - .CLK(m_axi_mm2s_aclk), - .D(in[2]), - .Q(sig_cmd_fifo_data_out[9])); - (* SOFT_HLUTNM = "soft_lutpair107" *) - LUT3 #( - .INIT(8'h8B)) - \sig_dbeat_cntr[0]_i_1 - (.I0(sig_cmd_fifo_data_out[7]), - .I1(sig_next_sequential_reg_reg), - .I2(Q[0]), - .O(D[0])); - (* SOFT_HLUTNM = "soft_lutpair107" *) - LUT4 #( - .INIT(16'hB88B)) - \sig_dbeat_cntr[1]_i_1 - (.I0(sig_cmd_fifo_data_out[8]), - .I1(sig_next_sequential_reg_reg), - .I2(Q[0]), - .I3(Q[1]), - .O(D[1])); - LUT5 #( - .INIT(32'hBBB8888B)) - \sig_dbeat_cntr[2]_i_1 - (.I0(sig_cmd_fifo_data_out[9]), - .I1(sig_next_sequential_reg_reg), - .I2(Q[1]), - .I3(Q[0]), - .I4(Q[2]), - .O(D[2])); - LUT6 #( - .INIT(64'hBBBBBBB88888888B)) - \sig_dbeat_cntr[3]_i_1 - (.I0(sig_cmd_fifo_data_out[10]), - .I1(sig_next_sequential_reg_reg), - .I2(Q[2]), - .I3(Q[0]), - .I4(Q[1]), - .I5(Q[3]), - .O(D[3])); - LUT6 #( - .INIT(64'hAFAFA0AFACACA0A0)) - sig_last_dbeat_i_1 - (.I0(sig_last_dbeat_i_2_n_0), - .I1(sig_halt_reg_reg), - .I2(sig_next_sequential_reg_reg), - .I3(\sig_dbeat_cntr_reg[2] ), - .I4(sig_dbeat_cntr_eq_1), - .I5(sig_last_dbeat), - .O(sig_last_dbeat_reg)); - LUT4 #( - .INIT(16'h0001)) - sig_last_dbeat_i_2 - (.I0(sig_cmd_fifo_data_out[9]), - .I1(sig_cmd_fifo_data_out[10]), - .I2(sig_cmd_fifo_data_out[7]), - .I3(sig_cmd_fifo_data_out[8]), - .O(sig_last_dbeat_i_2_n_0)); + Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized2 I_SRL_FIFO_RBU_F + (.D(D), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ), + .E(E), + .FIFO_Full_reg_0(FIFO_Full_reg), + .Q(Q), + .SR(SR), + .in(in), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .m_axi_mm2s_rlast(m_axi_mm2s_rlast), + .m_axi_mm2s_rvalid(m_axi_mm2s_rvalid), + .out(out), + .ram_full_i_reg(ram_full_i_reg), + .sel(sig_next_calc_error_reg_reg), + .\sig_addr_posted_cntr_reg[0] (\sig_addr_posted_cntr_reg[0] ), + .\sig_addr_posted_cntr_reg[1] (\sig_addr_posted_cntr_reg[1] ), + .\sig_addr_posted_cntr_reg[2] (\sig_addr_posted_cntr_reg[2] ), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_data2rsc_valid(sig_data2rsc_valid), + .\sig_dbeat_cntr_reg[0] (\sig_dbeat_cntr_reg[0] ), + .\sig_dbeat_cntr_reg[3] (\sig_dbeat_cntr_reg[3] ), + .\sig_dbeat_cntr_reg[5] (\sig_dbeat_cntr_reg[5] ), + .sig_dqual_reg_empty(sig_dqual_reg_empty), + .sig_dqual_reg_empty_reg(sig_dqual_reg_empty_reg), + .sig_dqual_reg_empty_reg_0(sig_dqual_reg_empty_reg_0), + .sig_dqual_reg_full(sig_dqual_reg_full), + .sig_halt_reg_reg(sig_halt_reg_reg), + .sig_inhibit_rdy_n(sig_inhibit_rdy_n), + .sig_inhibit_rdy_n_0(sig_inhibit_rdy_n_0), + .sig_last_dbeat(sig_last_dbeat), + .sig_last_dbeat_reg(sig_last_dbeat_reg), + .sig_mstr2data_cmd_valid(sig_mstr2data_cmd_valid), + .sig_next_calc_error_reg_reg(sig_next_calc_error_reg_reg_0), + .sig_next_cmd_cmplt_reg_reg(sig_next_cmd_cmplt_reg_reg), + .sig_next_sequential_reg(sig_next_sequential_reg), + .sig_rsc2stat_status_valid(sig_rsc2stat_status_valid)); +endmodule + +(* ORIG_REF_NAME = "srl_fifo_f" *) +module Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized3 + (FIFO_Full_reg, + \INFERRED_GEN.cnt_i_reg[1] , + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , + Q, + in, + m_axi_mm2s_aclk, + SR, + lsig_cmd_loaded, + prmry_resetn_i_reg, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 , + DOBDO, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg , + sig_inhibit_rdy_n_reg, + sig_mstr2sf_cmd_valid, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1 ); + output FIFO_Full_reg; + output \INFERRED_GEN.cnt_i_reg[1] ; + output \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + output [0:0]Q; + input [0:0]in; + input m_axi_mm2s_aclk; + input [0:0]SR; + input lsig_cmd_loaded; + input prmry_resetn_i_reg; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; + input [0:0]DOBDO; + input \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + input sig_inhibit_rdy_n_reg; + input sig_mstr2sf_cmd_valid; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1 ; + + wire [0:0]DOBDO; + wire FIFO_Full_reg; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1 ; + wire \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + wire \INFERRED_GEN.cnt_i_reg[1] ; + wire [0:0]Q; + wire [0:0]SR; + wire [0:0]in; + wire lsig_cmd_loaded; + wire m_axi_mm2s_aclk; + wire prmry_resetn_i_reg; + wire sig_inhibit_rdy_n_reg; + wire sig_mstr2sf_cmd_valid; + + Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized3 I_SRL_FIFO_RBU_F + (.DOBDO(DOBDO), + .FIFO_Full_reg_0(FIFO_Full_reg), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1 (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1 ), + .\INCLUDE_UNPACKING.lsig_cmd_loaded_reg (\INCLUDE_UNPACKING.lsig_cmd_loaded_reg ), + .\INFERRED_GEN.cnt_i_reg[1] (\INFERRED_GEN.cnt_i_reg[1] ), + .Q(Q), + .SR(SR), + .in(in), + .lsig_cmd_loaded(lsig_cmd_loaded), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .prmry_resetn_i_reg(prmry_resetn_i_reg), + .sig_inhibit_rdy_n_reg(sig_inhibit_rdy_n_reg), + .sig_mstr2sf_cmd_valid(sig_mstr2sf_cmd_valid)); +endmodule + +(* ORIG_REF_NAME = "srl_fifo_f" *) +module Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized4 + (p_9_out, + Q, + CO, + \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg , + decerr_i_reg, + slverr_i_reg, + interr_i_reg, + sig_dqual_reg_empty_reg, + \GEN_STS_GRTR_THAN_8.ovrflo_err_reg , + sig_stream_rst, + m_axi_s2mm_aclk, + s2mm_halt, + s2mm_soft_reset, + dma_err, + \hsize_vid_reg[15] , + \hsize_vid_reg[2] , + S, + sig_inhibit_rdy_n, + sig_wsc2stat_status_valid, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + m_axis_s2mm_sts_tready, + in); + output p_9_out; + output [0:0]Q; + output [0:0]CO; + output \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ; + output decerr_i_reg; + output slverr_i_reg; + output interr_i_reg; + output sig_dqual_reg_empty_reg; + output [0:0]\GEN_STS_GRTR_THAN_8.ovrflo_err_reg ; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input s2mm_halt; + input s2mm_soft_reset; + input dma_err; + input [12:0]\hsize_vid_reg[15] ; + input [0:0]\hsize_vid_reg[2] ; + input [0:0]S; + input sig_inhibit_rdy_n; + input sig_wsc2stat_status_valid; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input m_axis_s2mm_sts_tready; + input [16:0]in; + + wire [0:0]CO; + wire \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ; + wire [0:0]\GEN_STS_GRTR_THAN_8.ovrflo_err_reg ; + wire [0:0]Q; + wire [0:0]S; + wire decerr_i_reg; + wire dma_err; + wire [12:0]\hsize_vid_reg[15] ; + wire [0:0]\hsize_vid_reg[2] ; + wire [16:0]in; + wire interr_i_reg; + wire m_axi_s2mm_aclk; + wire m_axis_s2mm_sts_tready; + wire p_9_out; + wire s2mm_halt; + wire s2mm_soft_reset; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_dqual_reg_empty_reg; + wire sig_inhibit_rdy_n; + wire sig_stream_rst; + wire sig_wsc2stat_status_valid; + wire slverr_i_reg; + + Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized4 I_SRL_FIFO_RBU_F + (.CO(CO), + .\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg (\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ), + .\GEN_STS_GRTR_THAN_8.ovrflo_err_reg (\GEN_STS_GRTR_THAN_8.ovrflo_err_reg ), + .Q(Q), + .S(S), + .decerr_i_reg(decerr_i_reg), + .dma_err(dma_err), + .\hsize_vid_reg[15] (\hsize_vid_reg[15] ), + .\hsize_vid_reg[2] (\hsize_vid_reg[2] ), + .in(in), + .interr_i_reg(interr_i_reg), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .m_axis_s2mm_sts_tready(m_axis_s2mm_sts_tready), + .p_9_out(p_9_out), + .s2mm_halt(s2mm_halt), + .s2mm_soft_reset(s2mm_soft_reset), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_dqual_reg_empty_reg(sig_dqual_reg_empty_reg), + .sig_inhibit_rdy_n(sig_inhibit_rdy_n), + .sig_stream_rst(sig_stream_rst), + .sig_wsc2stat_status_valid(sig_wsc2stat_status_valid), + .slverr_i_reg(slverr_i_reg)); +endmodule + +(* ORIG_REF_NAME = "srl_fifo_f" *) +module Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized5 + (\GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg , + \GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg , + D, + \INFERRED_GEN.cnt_i_reg[2] , + E, + m_axi_s2mm_bready, + sig_stream_rst, + m_axi_s2mm_aclk, + in, + out, + sig_posted_to_axi_reg, + Q, + sig_push_coelsc_reg, + m_axi_s2mm_bvalid, + sig_inhibit_rdy_n, + \INFERRED_GEN.cnt_i_reg[3] , + sig_halt_reg, + m_axi_s2mm_bresp); + output \GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg ; + output \GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg ; + output [2:0]D; + output [0:0]\INFERRED_GEN.cnt_i_reg[2] ; + output [0:0]E; + output m_axi_s2mm_bready; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input [1:0]in; + input [0:0]out; + input sig_posted_to_axi_reg; + input [3:0]Q; + input sig_push_coelsc_reg; + input m_axi_s2mm_bvalid; + input sig_inhibit_rdy_n; + input \INFERRED_GEN.cnt_i_reg[3] ; + input sig_halt_reg; + input [1:0]m_axi_s2mm_bresp; + + wire [2:0]D; + wire [0:0]E; + wire \GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg ; + wire \GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg ; + wire [0:0]\INFERRED_GEN.cnt_i_reg[2] ; + wire \INFERRED_GEN.cnt_i_reg[3] ; + wire [3:0]Q; + wire [1:0]in; + wire m_axi_s2mm_aclk; + wire m_axi_s2mm_bready; + wire [1:0]m_axi_s2mm_bresp; + wire m_axi_s2mm_bvalid; + wire [0:0]out; + wire sig_halt_reg; + wire sig_inhibit_rdy_n; + wire sig_posted_to_axi_reg; + wire sig_push_coelsc_reg; + wire sig_stream_rst; + + Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized5 I_SRL_FIFO_RBU_F + (.D(D), + .E(E), + .\GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg (\GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg ), + .\GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg (\GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg ), + .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ), + .\INFERRED_GEN.cnt_i_reg[3] (\INFERRED_GEN.cnt_i_reg[3] ), + .Q(Q), + .in(in), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .m_axi_s2mm_bready(m_axi_s2mm_bready), + .m_axi_s2mm_bresp(m_axi_s2mm_bresp), + .m_axi_s2mm_bvalid(m_axi_s2mm_bvalid), + .out(out), + .sig_halt_reg(sig_halt_reg), + .sig_inhibit_rdy_n(sig_inhibit_rdy_n), + .sig_posted_to_axi_reg(sig_posted_to_axi_reg), + .sig_push_coelsc_reg(sig_push_coelsc_reg), + .sig_stream_rst(sig_stream_rst)); +endmodule + +(* ORIG_REF_NAME = "srl_fifo_f" *) +module Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized6 + (p_0_in, + out, + sig_push_to_wsc_reg, + D, + \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg , + \INFERRED_GEN.cnt_i_reg[1] , + \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg_0 , + E, + p_4_out, + sig_stream_rst, + m_axi_s2mm_aclk, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_inhibit_rdy_n, + sig_data2wsc_valid, + sig_set_push2wsc, + Q, + \INFERRED_GEN.cnt_i_reg[3] , + sig_coelsc_reg_empty, + in, + \GEN_INDET_BTT.lsig_eop_reg_reg ); + output p_0_in; + output [15:0]out; + output sig_push_to_wsc_reg; + output [2:0]D; + output \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ; + output \INFERRED_GEN.cnt_i_reg[1] ; + output \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg_0 ; + output [0:0]E; + output p_4_out; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_inhibit_rdy_n; + input sig_data2wsc_valid; + input sig_set_push2wsc; + input [3:0]Q; + input [0:0]\INFERRED_GEN.cnt_i_reg[3] ; + input sig_coelsc_reg_empty; + input [0:0]in; + input [15:0]\GEN_INDET_BTT.lsig_eop_reg_reg ; + + wire [2:0]D; + wire [0:0]E; + wire \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ; + wire \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg_0 ; + wire [15:0]\GEN_INDET_BTT.lsig_eop_reg_reg ; + wire \INFERRED_GEN.cnt_i_reg[1] ; + wire [0:0]\INFERRED_GEN.cnt_i_reg[3] ; + wire [3:0]Q; + wire [0:0]in; + wire m_axi_s2mm_aclk; + wire [15:0]out; + wire p_0_in; + wire p_4_out; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_coelsc_reg_empty; + wire sig_data2wsc_valid; + wire sig_inhibit_rdy_n; + wire sig_push_to_wsc_reg; + wire sig_set_push2wsc; + wire sig_stream_rst; + + Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized6 I_SRL_FIFO_RBU_F + (.D(D), + .E(E), + .\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg (\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg_0 ), + .\GEN_INDET_BTT.lsig_eop_reg_reg (\GEN_INDET_BTT.lsig_eop_reg_reg ), + .\INFERRED_GEN.cnt_i_reg[1] (\INFERRED_GEN.cnt_i_reg[1] ), + .\INFERRED_GEN.cnt_i_reg[3] (\INFERRED_GEN.cnt_i_reg[3] ), + .Q(Q), + .in(in), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out), + .p_0_in(p_0_in), + .p_4_out(p_4_out), + .sel(\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_coelsc_reg_empty(sig_coelsc_reg_empty), + .sig_data2wsc_valid(sig_data2wsc_valid), + .sig_inhibit_rdy_n(sig_inhibit_rdy_n), + .sig_push_to_wsc_reg(sig_push_to_wsc_reg), + .sig_set_push2wsc(sig_set_push2wsc), + .sig_stream_rst(sig_stream_rst)); +endmodule + +(* ORIG_REF_NAME = "srl_fifo_f" *) +module Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized7 + (\INFERRED_GEN.cnt_i_reg[0] , + Q, + \GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg , + out, + sig_sm_pop_cmd_fifo_ns, + sig_sm_ld_dre_cmd_ns, + D, + sig_stream_rst, + m_axi_s2mm_aclk, + sig_need_cmd_flush, + p_7_out, + sig_sm_pop_cmd_fifo, + p_9_out_0, + sig_inhibit_rdy_n_reg, + lsig_cmd_fetch_pause, + E, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_good_tlast_dbeat37_out__0, + in, + \FSM_sequential_sig_cmdcntl_sm_state_reg[0] , + \FSM_sequential_sig_cmdcntl_sm_state_reg[2] , + sig_cmd_empty_reg); + output \INFERRED_GEN.cnt_i_reg[0] ; + output [0:0]Q; + output \GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg ; + output [19:0]out; + output sig_sm_pop_cmd_fifo_ns; + output sig_sm_ld_dre_cmd_ns; + output [2:0]D; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input sig_need_cmd_flush; + input p_7_out; + input sig_sm_pop_cmd_fifo; + input p_9_out_0; + input sig_inhibit_rdy_n_reg; + input lsig_cmd_fetch_pause; + input [0:0]E; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_good_tlast_dbeat37_out__0; + input [21:0]in; + input \FSM_sequential_sig_cmdcntl_sm_state_reg[0] ; + input [2:0]\FSM_sequential_sig_cmdcntl_sm_state_reg[2] ; + input sig_cmd_empty_reg; + + wire [2:0]D; + wire [0:0]E; + wire \FSM_sequential_sig_cmdcntl_sm_state_reg[0] ; + wire [2:0]\FSM_sequential_sig_cmdcntl_sm_state_reg[2] ; + wire \GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg ; + wire \INFERRED_GEN.cnt_i_reg[0] ; + wire [0:0]Q; + wire [21:0]in; + wire lsig_cmd_fetch_pause; + wire m_axi_s2mm_aclk; + wire [19:0]out; + wire p_7_out; + wire p_9_out_0; + wire sig_cmd_empty_reg; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_good_tlast_dbeat37_out__0; + wire sig_inhibit_rdy_n_reg; + wire sig_need_cmd_flush; + wire sig_sm_ld_dre_cmd_ns; + wire sig_sm_pop_cmd_fifo; + wire sig_sm_pop_cmd_fifo_ns; + wire sig_stream_rst; + + Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized7 I_SRL_FIFO_RBU_F + (.D(D), + .E(E), + .\FSM_sequential_sig_cmdcntl_sm_state_reg[0] (\FSM_sequential_sig_cmdcntl_sm_state_reg[0] ), + .\FSM_sequential_sig_cmdcntl_sm_state_reg[2] (\FSM_sequential_sig_cmdcntl_sm_state_reg[2] ), + .\GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg (\GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg ), + .\INFERRED_GEN.cnt_i_reg[0] (\INFERRED_GEN.cnt_i_reg[0] ), + .Q(Q), + .in(in), + .lsig_cmd_fetch_pause(lsig_cmd_fetch_pause), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out), + .p_7_out(p_7_out), + .p_9_out_0(p_9_out_0), + .sig_cmd_empty_reg(sig_cmd_empty_reg), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_good_tlast_dbeat37_out__0(sig_good_tlast_dbeat37_out__0), + .sig_inhibit_rdy_n_reg(sig_inhibit_rdy_n_reg), + .sig_need_cmd_flush(sig_need_cmd_flush), + .sig_sm_ld_dre_cmd_ns(sig_sm_ld_dre_cmd_ns), + .sig_sm_pop_cmd_fifo(sig_sm_pop_cmd_fifo), + .sig_sm_pop_cmd_fifo_ns(sig_sm_pop_cmd_fifo_ns), + .sig_stream_rst(sig_stream_rst)); endmodule -(* ORIG_REF_NAME = "dynshreg_f" *) -module Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized3 - (p_0_out, - sig_cmd2dre_valid_reg, - in, +(* ORIG_REF_NAME = "srl_fifo_f" *) +module Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized8 + (\INFERRED_GEN.cnt_i_reg[1] , + \INFERRED_GEN.cnt_i_reg[4] , + \INCLUDE_PACKING.lsig_first_dbeat_reg , + \sig_byte_cntr_reg[0] , + sig_dre2ibtt_tlast, + sig_cmd_full_reg, + sig_cmd_empty_reg, + sig_good_tlast_dbeat37_out__0, + SR, + E, Q, - m_axi_mm2s_aclk); - output [0:0]p_0_out; - input sig_cmd2dre_valid_reg; - input [0:0]in; - input [1:0]Q; - input m_axi_mm2s_aclk; + sig_s_ready_dup4_reg, + \sig_byte_cntr_reg[7] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] , + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] , + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] , + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] , + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] , + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] , + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] , + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] , + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] , + sig_eop_sent, + \GEN_INDET_BTT.lsig_absorb2tlast_reg , + \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg , + m_axi_s2mm_aclk, + \INCLUDE_PACKING.lsig_first_dbeat_reg_0 , + sig_cmd_full, + sig_sm_ld_dre_cmd, + p_7_out, + sig_strm_tlast, + sig_m_valid_out_reg, + lsig_absorb2tlast, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_last_reg_out_reg, + sig_eop_halt_xfer, + sig_ibtt2dre_tready, + out, + sig_clr_dbc_reg, + sig_eop_sent_reg, + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 , + sig_inhibit_rdy_n_reg, + slice_insert_valid, + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 , + p_0_in, + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 , + lsig_cmd_fetch_pause, + sig_need_cmd_flush, + sig_sm_pop_cmd_fifo, + in); + output \INFERRED_GEN.cnt_i_reg[1] ; + output \INFERRED_GEN.cnt_i_reg[4] ; + output \INCLUDE_PACKING.lsig_first_dbeat_reg ; + output \sig_byte_cntr_reg[0] ; + output sig_dre2ibtt_tlast; + output sig_cmd_full_reg; + output sig_cmd_empty_reg; + output sig_good_tlast_dbeat37_out__0; + output [0:0]SR; + output [0:0]E; + output [0:0]Q; + output sig_s_ready_dup4_reg; + output [0:0]\sig_byte_cntr_reg[7] ; + output \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ; + output \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] ; + output sig_eop_sent; + output [0:0]\GEN_INDET_BTT.lsig_absorb2tlast_reg ; + output \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg ; + input m_axi_s2mm_aclk; + input \INCLUDE_PACKING.lsig_first_dbeat_reg_0 ; + input sig_cmd_full; + input sig_sm_ld_dre_cmd; + input p_7_out; + input sig_strm_tlast; + input sig_m_valid_out_reg; + input lsig_absorb2tlast; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_last_reg_out_reg; + input sig_eop_halt_xfer; + input sig_ibtt2dre_tready; + input out; + input sig_clr_dbc_reg; + input sig_eop_sent_reg; + input [1:0]\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1] ; + input [1:0]\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ; + input sig_inhibit_rdy_n_reg; + input slice_insert_valid; + input \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ; + input p_0_in; + input \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ; + input lsig_cmd_fetch_pause; + input sig_need_cmd_flush; + input sig_sm_pop_cmd_fifo; + input [1:0]in; - wire [1:0]Q; - wire [0:0]in; - wire m_axi_mm2s_aclk; - wire [0:0]p_0_out; - wire sig_cmd2dre_valid_reg; + wire [0:0]E; + wire \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg ; + wire [0:0]\GEN_INDET_BTT.lsig_absorb2tlast_reg ; + wire [1:0]\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ; + wire [1:0]\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ; + wire \INCLUDE_PACKING.lsig_first_dbeat_reg ; + wire \INCLUDE_PACKING.lsig_first_dbeat_reg_0 ; + wire \INFERRED_GEN.cnt_i_reg[1] ; + wire \INFERRED_GEN.cnt_i_reg[4] ; + wire [0:0]Q; + wire [0:0]SR; + wire [1:0]in; + wire lsig_absorb2tlast; + wire lsig_cmd_fetch_pause; + wire m_axi_s2mm_aclk; + wire out; + wire p_0_in; + wire p_7_out; + wire \sig_byte_cntr_reg[0] ; + wire [0:0]\sig_byte_cntr_reg[7] ; + wire sig_clr_dbc_reg; + wire sig_cmd_empty_reg; + wire sig_cmd_full; + wire sig_cmd_full_reg; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_dre2ibtt_tlast; + wire sig_eop_halt_xfer; + wire sig_eop_sent; + wire sig_eop_sent_reg; + wire sig_good_tlast_dbeat37_out__0; + wire sig_ibtt2dre_tready; + wire sig_inhibit_rdy_n_reg; + wire sig_last_reg_out_reg; + wire sig_m_valid_out_reg; + wire sig_need_cmd_flush; + wire sig_s_ready_dup4_reg; + wire sig_sm_ld_dre_cmd; + wire sig_sm_pop_cmd_fifo; + wire sig_strm_tlast; + wire slice_insert_valid; - (* srl_bus_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] " *) - (* srl_name = "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][7]_srl4 " *) - SRL16E #( - .INIT(16'h0000)) - \INFERRED_GEN.data_reg[3][7]_srl4 - (.A0(Q[0]), - .A1(Q[1]), - .A2(1'b0), - .A3(1'b0), - .CE(sig_cmd2dre_valid_reg), - .CLK(m_axi_mm2s_aclk), - .D(in), - .Q(p_0_out)); + Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized8 I_SRL_FIFO_RBU_F + (.E(E), + .\GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg (\GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg ), + .\GEN_INDET_BTT.lsig_absorb2tlast_reg (\GEN_INDET_BTT.lsig_absorb2tlast_reg ), + .\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1] (\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] (\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] (\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] (\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] (\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] (\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] (\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] (\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] (\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ), + .\INCLUDE_PACKING.lsig_first_dbeat_reg (\INCLUDE_PACKING.lsig_first_dbeat_reg ), + .\INCLUDE_PACKING.lsig_first_dbeat_reg_0 (\INCLUDE_PACKING.lsig_first_dbeat_reg_0 ), + .\INFERRED_GEN.cnt_i_reg[1] (\INFERRED_GEN.cnt_i_reg[1] ), + .Q(Q), + .SR(SR), + .SS(\INFERRED_GEN.cnt_i_reg[4] ), + .in(in), + .lsig_absorb2tlast(lsig_absorb2tlast), + .lsig_cmd_fetch_pause(lsig_cmd_fetch_pause), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out), + .p_0_in(p_0_in), + .p_7_out(p_7_out), + .\sig_byte_cntr_reg[0] (\sig_byte_cntr_reg[0] ), + .\sig_byte_cntr_reg[7] (\sig_byte_cntr_reg[7] ), + .sig_clr_dbc_reg(sig_clr_dbc_reg), + .sig_cmd_empty_reg(sig_cmd_empty_reg), + .sig_cmd_full(sig_cmd_full), + .sig_cmd_full_reg(sig_cmd_full_reg), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_dre2ibtt_tlast(sig_dre2ibtt_tlast), + .sig_eop_halt_xfer(sig_eop_halt_xfer), + .sig_eop_sent(sig_eop_sent), + .sig_eop_sent_reg(sig_eop_sent_reg), + .sig_good_tlast_dbeat37_out__0(sig_good_tlast_dbeat37_out__0), + .sig_ibtt2dre_tready(sig_ibtt2dre_tready), + .sig_inhibit_rdy_n_reg(sig_inhibit_rdy_n_reg), + .sig_last_reg_out_reg(sig_last_reg_out_reg), + .sig_m_valid_out_reg(sig_m_valid_out_reg), + .sig_need_cmd_flush(sig_need_cmd_flush), + .sig_s_ready_dup4_reg(sig_s_ready_dup4_reg), + .sig_sm_ld_dre_cmd(sig_sm_ld_dre_cmd), + .sig_sm_pop_cmd_fifo(sig_sm_pop_cmd_fifo), + .sig_strm_tlast(sig_strm_tlast), + .slice_insert_valid(slice_insert_valid)); endmodule (* ORIG_REF_NAME = "srl_fifo_f" *) -module Arty_Z7_20_axi_vdma_0_0_srl_fifo_f - (Q, - E, +module Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized9 + (\INFERRED_GEN.cnt_i_reg[0] , + p_0_in, out, sig_calc_error_reg_reg, + sig_clr_cmd2addr_valid3_out__0, + sig_stream_rst, + m_axi_s2mm_aclk, + sig_halt_reg, + sig_addr_reg_empty_reg, + p_22_out, + sig_inhibit_rdy_n_reg, + in); + output \INFERRED_GEN.cnt_i_reg[0] ; + output p_0_in; + output [41:0]out; + output sig_calc_error_reg_reg; + output sig_clr_cmd2addr_valid3_out__0; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input sig_halt_reg; + input sig_addr_reg_empty_reg; + input p_22_out; + input sig_inhibit_rdy_n_reg; + input [39:0]in; + + wire \INFERRED_GEN.cnt_i_reg[0] ; + wire [39:0]in; + wire m_axi_s2mm_aclk; + wire [41:0]out; + wire p_0_in; + wire p_22_out; + wire sig_addr_reg_empty_reg; + wire sig_calc_error_reg_reg; + wire sig_clr_cmd2addr_valid3_out__0; + wire sig_halt_reg; + wire sig_inhibit_rdy_n_reg; + wire sig_stream_rst; + + Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized9 I_SRL_FIFO_RBU_F + (.\INFERRED_GEN.cnt_i_reg[0] (\INFERRED_GEN.cnt_i_reg[0] ), + .in(in), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out), + .p_0_in(p_0_in), + .p_22_out(p_22_out), + .sig_addr_reg_empty_reg(sig_addr_reg_empty_reg), + .sig_calc_error_reg_reg(sig_calc_error_reg_reg), + .sig_clr_cmd2addr_valid3_out__0(sig_clr_cmd2addr_valid3_out__0), + .sig_halt_reg(sig_halt_reg), + .sig_inhibit_rdy_n_reg(sig_inhibit_rdy_n_reg), + .sig_stream_rst(sig_stream_rst)); +endmodule + +(* ORIG_REF_NAME = "srl_fifo_rbu_f" *) +module Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f + (sig_calc_error_reg_reg, + Q, + s_axis_cmd_tvalid_reg, + out, + sig_stream_rst, + m_axi_s2mm_aclk, + sig_psm_halt, + sig_input_reg_empty, + p_10_out, + cmnd_wr_1, + sig_inhibit_rdy_n, + s2mm_halt, + s_axis_s2mm_cmd_tvalid, + \s_axis_cmd_tdata_reg[63] ); + output sig_calc_error_reg_reg; + output [0:0]Q; + output [0:0]s_axis_cmd_tvalid_reg; + output [49:0]out; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input sig_psm_halt; + input sig_input_reg_empty; + input p_10_out; + input cmnd_wr_1; + input sig_inhibit_rdy_n; + input s2mm_halt; + input s_axis_s2mm_cmd_tvalid; + input [48:0]\s_axis_cmd_tdata_reg[63] ; + + wire CNTR_INCR_DECR_ADDN_F_I_n_2; + wire CNTR_INCR_DECR_ADDN_F_I_n_3; + wire FIFO_Full_reg_n_0; + wire [0:0]Q; + wire cmnd_wr_1; + wire fifo_full_p1; + wire m_axi_s2mm_aclk; + wire [49:0]out; + wire p_10_out; + wire s2mm_halt; + wire [48:0]\s_axis_cmd_tdata_reg[63] ; + wire [0:0]s_axis_cmd_tvalid_reg; + wire s_axis_s2mm_cmd_tvalid; + wire sig_calc_error_reg_reg; + wire sig_inhibit_rdy_n; + wire sig_input_reg_empty; + wire sig_psm_halt; + wire sig_stream_rst; + wire sig_wr_fifo; + + Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_16 CNTR_INCR_DECR_ADDN_F_I + (.Q({Q,CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3}), + .fifo_full_p1(fifo_full_p1), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .sig_input_reg_empty(sig_input_reg_empty), + .sig_psm_halt(sig_psm_halt), + .sig_stream_rst(sig_stream_rst), + .sig_wr_fifo(sig_wr_fifo)); + Arty_Z7_20_axi_vdma_0_0_dynshreg_f DYNSHREG_F_I + (.FIFO_Full_reg(FIFO_Full_reg_n_0), + .Q({Q,CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3}), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out), + .p_10_out(p_10_out), + .\s_axis_cmd_tdata_reg[63] (\s_axis_cmd_tdata_reg[63] ), + .s_axis_s2mm_cmd_tvalid(s_axis_s2mm_cmd_tvalid), + .sig_calc_error_reg_reg(sig_calc_error_reg_reg), + .sig_inhibit_rdy_n(sig_inhibit_rdy_n), + .sig_input_reg_empty(sig_input_reg_empty), + .sig_psm_halt(sig_psm_halt), + .sig_wr_fifo(sig_wr_fifo)); + FDRE FIFO_Full_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(fifo_full_p1), + .Q(FIFO_Full_reg_n_0), + .R(sig_stream_rst)); + LUT4 #( + .INIT(16'hFFAE)) + \s_axis_cmd_tdata[63]_i_2__0 + (.I0(cmnd_wr_1), + .I1(sig_inhibit_rdy_n), + .I2(FIFO_Full_reg_n_0), + .I3(s2mm_halt), + .O(s_axis_cmd_tvalid_reg)); +endmodule + +(* ORIG_REF_NAME = "srl_fifo_rbu_f" *) +module Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f_24 + (sig_calc_error_reg_reg, + Q, + E, + out, SR, m_axi_mm2s_aclk, - sig_calc_error_pushed_reg, + in, sig_sm_halt_reg, sig_input_reg_empty, - sig_calc_error_pushed, - p_55_out, - sig_inhibit_rdy_n, cmnd_wr, + sig_inhibit_rdy_n, mm2s_halt, - in, + sig_calc_error_pushed_reg, + sig_calc_error_pushed, + p_56_out, \s_axis_cmd_tdata_reg[63] ); + output sig_calc_error_reg_reg; output [0:0]Q; output [0:0]E; output [49:0]out; - output sig_calc_error_reg_reg; input [0:0]SR; input m_axi_mm2s_aclk; - input sig_calc_error_pushed_reg; + input [0:0]in; input sig_sm_halt_reg; input sig_input_reg_empty; - input sig_calc_error_pushed; - input p_55_out; - input sig_inhibit_rdy_n; input cmnd_wr; + input sig_inhibit_rdy_n; input mm2s_halt; - input [0:0]in; + input sig_calc_error_pushed_reg; + input sig_calc_error_pushed; + input p_56_out; input [48:0]\s_axis_cmd_tdata_reg[63] ; + wire CNTR_INCR_DECR_ADDN_F_I_n_2; + wire CNTR_INCR_DECR_ADDN_F_I_n_3; wire [0:0]E; + wire FIFO_Full_reg_n_0; wire [0:0]Q; wire [0:0]SR; wire cmnd_wr; + wire fifo_full_p1; wire [0:0]in; wire m_axi_mm2s_aclk; wire mm2s_halt; wire [49:0]out; - wire p_55_out; + wire p_56_out; wire [48:0]\s_axis_cmd_tdata_reg[63] ; wire sig_calc_error_pushed; wire sig_calc_error_pushed_reg; @@ -27891,243 +71296,517 @@ module Arty_Z7_20_axi_vdma_0_0_srl_fifo_f wire sig_inhibit_rdy_n; wire sig_input_reg_empty; wire sig_sm_halt_reg; + wire sig_wr_fifo; - Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f I_SRL_FIFO_RBU_F - (.E(E), - .Q(Q), + Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_25 CNTR_INCR_DECR_ADDN_F_I + (.FIFO_Full_reg(FIFO_Full_reg_n_0), + .Q({Q,CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3}), .SR(SR), - .cmnd_wr(cmnd_wr), + .fifo_full_p1(fifo_full_p1), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .p_56_out(p_56_out), + .sig_calc_error_pushed(sig_calc_error_pushed), + .sig_calc_error_pushed_reg(sig_calc_error_pushed_reg), + .sig_inhibit_rdy_n(sig_inhibit_rdy_n), + .sig_input_reg_empty(sig_input_reg_empty), + .sig_sm_halt_reg(sig_sm_halt_reg), + .sig_wr_fifo(sig_wr_fifo)); + Arty_Z7_20_axi_vdma_0_0_dynshreg_f_26 DYNSHREG_F_I + (.FIFO_Full_reg(FIFO_Full_reg_n_0), + .Q({Q,CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3}), .in(in), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .mm2s_halt(mm2s_halt), .out(out), - .p_55_out(p_55_out), + .p_56_out(p_56_out), .\s_axis_cmd_tdata_reg[63] (\s_axis_cmd_tdata_reg[63] ), - .sig_calc_error_pushed(sig_calc_error_pushed), - .sig_calc_error_pushed_reg(sig_calc_error_pushed_reg), .sig_calc_error_reg_reg(sig_calc_error_reg_reg), .sig_inhibit_rdy_n(sig_inhibit_rdy_n), .sig_input_reg_empty(sig_input_reg_empty), - .sig_sm_halt_reg(sig_sm_halt_reg)); + .sig_sm_halt_reg(sig_sm_halt_reg), + .sig_wr_fifo(sig_wr_fifo)); + FDRE FIFO_Full_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(fifo_full_p1), + .Q(FIFO_Full_reg_n_0), + .R(SR)); + LUT4 #( + .INIT(16'hFFAE)) + \s_axis_cmd_tdata[63]_i_2 + (.I0(cmnd_wr), + .I1(sig_inhibit_rdy_n), + .I2(FIFO_Full_reg_n_0), + .I3(mm2s_halt), + .O(E)); endmodule -(* ORIG_REF_NAME = "srl_fifo_f" *) -module Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized0 +(* ORIG_REF_NAME = "srl_fifo_rbu_f" *) +module Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized0 (\INFERRED_GEN.cnt_i_reg[1] , - Q, sig_rd_sts_slverr_reg_reg, - interr_i_reg, - slverr_i_reg, decerr_i_reg, + Q, + slverr_i_reg, + interr_i_reg, SR, m_axi_mm2s_aclk, - p_57_out, - sig_rsc2stat_status_valid, sig_inhibit_rdy_n_reg, - sts_tready_reg, + sig_rsc2stat_status_valid, sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + p_58_out, + sts_tready_reg, sig_rd_sts_slverr_reg_reg_0); output \INFERRED_GEN.cnt_i_reg[1] ; - output [0:0]Q; output sig_rd_sts_slverr_reg_reg; - output interr_i_reg; - output slverr_i_reg; output decerr_i_reg; + output [0:0]Q; + output slverr_i_reg; + output interr_i_reg; input [0:0]SR; input m_axi_mm2s_aclk; - input p_57_out; - input sig_rsc2stat_status_valid; input sig_inhibit_rdy_n_reg; - input sts_tready_reg; + input sig_rsc2stat_status_valid; input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input p_58_out; + input sts_tready_reg; input [2:0]sig_rd_sts_slverr_reg_reg_0; + wire CNTR_INCR_DECR_ADDN_F_I_n_2; + wire CNTR_INCR_DECR_ADDN_F_I_n_3; wire \INFERRED_GEN.cnt_i_reg[1] ; wire [0:0]Q; wire [0:0]SR; wire decerr_i_reg; + wire fifo_full_p1; wire interr_i_reg; wire m_axi_mm2s_aclk; - wire p_57_out; + wire p_58_out; wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; wire sig_inhibit_rdy_n_reg; wire sig_rd_sts_slverr_reg_reg; wire [2:0]sig_rd_sts_slverr_reg_reg_0; wire sig_rsc2stat_status_valid; + wire sig_wr_fifo; wire slverr_i_reg; wire sts_tready_reg; - Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized0 I_SRL_FIFO_RBU_F - (.\INFERRED_GEN.cnt_i_reg[1] (\INFERRED_GEN.cnt_i_reg[1] ), - .Q(Q), + Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_27 CNTR_INCR_DECR_ADDN_F_I + (.FIFO_Full_reg(\INFERRED_GEN.cnt_i_reg[1] ), + .Q({Q,CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3}), .SR(SR), + .fifo_full_p1(fifo_full_p1), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .p_58_out(p_58_out), + .sig_inhibit_rdy_n_reg(sig_inhibit_rdy_n_reg), + .sig_rsc2stat_status_valid(sig_rsc2stat_status_valid), + .sig_wr_fifo(sig_wr_fifo), + .sts_tready_reg(sts_tready_reg)); + Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized0 DYNSHREG_F_I + (.FIFO_Full_reg(\INFERRED_GEN.cnt_i_reg[1] ), + .Q({Q,CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3}), .decerr_i_reg(decerr_i_reg), .interr_i_reg(interr_i_reg), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .p_57_out(p_57_out), - .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), .sig_inhibit_rdy_n_reg(sig_inhibit_rdy_n_reg), - .sig_rd_sts_slverr_reg_reg(sig_rd_sts_slverr_reg_reg), - .sig_rd_sts_slverr_reg_reg_0(sig_rd_sts_slverr_reg_reg_0), + .sig_rd_sts_slverr_reg_reg(sig_rd_sts_slverr_reg_reg_0), .sig_rsc2stat_status_valid(sig_rsc2stat_status_valid), - .slverr_i_reg(slverr_i_reg), - .sts_tready_reg(sts_tready_reg)); + .sig_wr_fifo(sig_wr_fifo), + .slverr_i_reg(slverr_i_reg)); + FDRE FIFO_Full_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(fifo_full_p1), + .Q(\INFERRED_GEN.cnt_i_reg[1] ), + .R(SR)); + LUT4 #( + .INIT(16'h20FF)) + sig_rd_sts_reg_full_i_1 + (.I0(sig_inhibit_rdy_n_reg), + .I1(\INFERRED_GEN.cnt_i_reg[1] ), + .I2(sig_rsc2stat_status_valid), + .I3(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .O(sig_rd_sts_slverr_reg_reg)); endmodule -(* ORIG_REF_NAME = "srl_fifo_f" *) -module Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized1 - (sig_calc_error_reg_reg, - sig_calc_error_reg_reg_0, - sig_posted_to_axi_reg, - sig_addr_valid_reg_reg, +(* ORIG_REF_NAME = "srl_fifo_rbu_f" *) +module Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized1 + (sig_addr_valid_reg_reg, out, + sig_posted_to_axi_2_reg, + sel, + sig_addr_reg_empty_reg, SR, m_axi_mm2s_aclk, - sig_mstr2addr_cmd_valid, - sig_inhibit_rdy_n, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_data2addr_stop_req, sig_addr_reg_empty, sig_sf_allow_addr_req, + sig_data2addr_stop_req, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_inhibit_rdy_n, + sig_mstr2addr_cmd_valid, in); - output sig_calc_error_reg_reg; - output sig_calc_error_reg_reg_0; - output sig_posted_to_axi_reg; output sig_addr_valid_reg_reg; - output [39:0]out; + output [40:0]out; + output sig_posted_to_axi_2_reg; + output sel; + output sig_addr_reg_empty_reg; input [0:0]SR; input m_axi_mm2s_aclk; - input sig_mstr2addr_cmd_valid; - input sig_inhibit_rdy_n; - input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - input sig_data2addr_stop_req; input sig_addr_reg_empty; input sig_sf_allow_addr_req; - input [37:0]in; + input sig_data2addr_stop_req; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_inhibit_rdy_n; + input sig_mstr2addr_cmd_valid; + input [38:0]in; + wire CNTR_INCR_DECR_ADDN_F_I_n_2; + wire CNTR_INCR_DECR_ADDN_F_I_n_3; + wire FIFO_Full_reg_n_0; wire [0:0]SR; - wire [37:0]in; + wire fifo_full_p1; + wire [38:0]in; wire m_axi_mm2s_aclk; - wire [39:0]out; + wire [40:0]out; + wire sel; wire sig_addr_reg_empty; + wire sig_addr_reg_empty_reg; wire sig_addr_valid_reg_reg; - wire sig_calc_error_reg_reg; - wire sig_calc_error_reg_reg_0; wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; wire sig_data2addr_stop_req; wire sig_inhibit_rdy_n; wire sig_mstr2addr_cmd_valid; - wire sig_posted_to_axi_reg; + wire sig_posted_to_axi_2_reg; wire sig_sf_allow_addr_req; - Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized1 I_SRL_FIFO_RBU_F - (.SR(SR), - .in(in), + Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_28 CNTR_INCR_DECR_ADDN_F_I + (.FIFO_Full_reg(sel), + .FIFO_Full_reg_0(FIFO_Full_reg_n_0), + .Q({CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3}), + .SR(SR), + .fifo_full_p1(fifo_full_p1), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .out(out), - .sel(sig_calc_error_reg_reg_0), .sig_addr_reg_empty(sig_addr_reg_empty), - .sig_addr_valid_reg_reg(sig_addr_valid_reg_reg), - .sig_calc_error_reg_reg(sig_calc_error_reg_reg), + .sig_addr_reg_empty_reg(sig_addr_reg_empty_reg), .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), .sig_data2addr_stop_req(sig_data2addr_stop_req), .sig_inhibit_rdy_n(sig_inhibit_rdy_n), .sig_mstr2addr_cmd_valid(sig_mstr2addr_cmd_valid), - .sig_posted_to_axi_reg(sig_posted_to_axi_reg), + .sig_posted_to_axi_2_reg(sig_posted_to_axi_2_reg), .sig_sf_allow_addr_req(sig_sf_allow_addr_req)); + Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 DYNSHREG_F_I + (.FIFO_Full_reg(FIFO_Full_reg_n_0), + .Q({CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3}), + .in(in), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .out(out), + .sig_addr_valid_reg_reg(sig_addr_valid_reg_reg), + .sig_calc_error_reg_reg(sel), + .sig_inhibit_rdy_n(sig_inhibit_rdy_n), + .sig_mstr2addr_cmd_valid(sig_mstr2addr_cmd_valid)); + FDRE FIFO_Full_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(fifo_full_p1), + .Q(FIFO_Full_reg_n_0), + .R(SR)); endmodule -(* ORIG_REF_NAME = "srl_fifo_f" *) -module Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized2 - (sig_dqual_reg_empty_reg, +(* ORIG_REF_NAME = "srl_fifo_rbu_f" *) +module Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized10 + (\INFERRED_GEN.cnt_i_reg[0] , + sig_last_dbeat_reg, + sig_dqual_reg_empty_reg, + sig_ld_new_cmd_reg_reg, sig_next_calc_error_reg_reg, - E, + sig_dqual_reg_empty_reg_0, D, + E, + sig_dqual_reg_empty_reg_1, + sig_clr_cmd2data_valid4_out__0, + out, + sig_stream_rst, + m_axi_s2mm_aclk, + sig_first_dbeat1__0, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_single_dbeat, + sig_last_dbeat_reg_0, + sig_ld_new_cmd_reg, + sig_next_calc_error_reg, + \sig_dbeat_cntr_reg[1] , + sig_dqual_reg_full_reg, + Q, + \sig_dbeat_cntr_reg[4] , + p_11_out, + sig_inhibit_rdy_n_reg, + \sig_dbeat_cntr_reg[2] , + \sig_dbeat_cntr_reg[3] , + sig_next_sequential_reg, + sig_dqual_reg_empty, + sig_halt_reg, + sig_m_valid_out_reg, + sig_s_ready_out_reg, + sig_wdc_status_going_full, + sig_inhibit_rdy_n_reg_0, + sig_wsc2stat_status_valid, + sig_addr_posted_cntr, + sig_halt_reg_dly3, + sig_last_mmap_dbeat_reg, + sig_posted_to_axi_reg, + sig_xfer_calc_err_reg_reg); + output \INFERRED_GEN.cnt_i_reg[0] ; + output sig_last_dbeat_reg; + output sig_dqual_reg_empty_reg; + output sig_ld_new_cmd_reg_reg; + output sig_next_calc_error_reg_reg; + output sig_dqual_reg_empty_reg_0; + output [7:0]D; + output [0:0]E; + output sig_dqual_reg_empty_reg_1; + output sig_clr_cmd2data_valid4_out__0; + output [2:0]out; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input sig_first_dbeat1__0; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_single_dbeat; + input sig_last_dbeat_reg_0; + input sig_ld_new_cmd_reg; + input sig_next_calc_error_reg; + input \sig_dbeat_cntr_reg[1] ; + input sig_dqual_reg_full_reg; + input [7:0]Q; + input \sig_dbeat_cntr_reg[4] ; + input p_11_out; + input sig_inhibit_rdy_n_reg; + input \sig_dbeat_cntr_reg[2] ; + input \sig_dbeat_cntr_reg[3] ; + input sig_next_sequential_reg; + input sig_dqual_reg_empty; + input sig_halt_reg; + input sig_m_valid_out_reg; + input sig_s_ready_out_reg; + input sig_wdc_status_going_full; + input sig_inhibit_rdy_n_reg_0; + input sig_wsc2stat_status_valid; + input [2:0]sig_addr_posted_cntr; + input sig_halt_reg_dly3; + input sig_last_mmap_dbeat_reg; + input sig_posted_to_axi_reg; + input [8:0]sig_xfer_calc_err_reg_reg; + + wire CNTR_INCR_DECR_ADDN_F_I_n_7; + wire CNTR_INCR_DECR_ADDN_F_I_n_8; + wire [7:0]D; + wire [0:0]E; + wire \INFERRED_GEN.cnt_i_reg[0] ; + wire [7:0]Q; + wire fifo_full_p1; + wire m_axi_s2mm_aclk; + wire [2:0]out; + wire p_11_out; + wire [2:0]sig_addr_posted_cntr; + wire sig_clr_cmd2data_valid4_out__0; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire \sig_dbeat_cntr_reg[1] ; + wire \sig_dbeat_cntr_reg[2] ; + wire \sig_dbeat_cntr_reg[3] ; + wire \sig_dbeat_cntr_reg[4] ; + wire sig_dqual_reg_empty; + wire sig_dqual_reg_empty_reg; + wire sig_dqual_reg_empty_reg_0; + wire sig_dqual_reg_empty_reg_1; + wire sig_dqual_reg_full_reg; + wire sig_first_dbeat1__0; + wire sig_halt_reg; + wire sig_halt_reg_dly3; + wire sig_inhibit_rdy_n_reg; + wire sig_inhibit_rdy_n_reg_0; + wire sig_last_dbeat_reg; + wire sig_last_dbeat_reg_0; + wire sig_last_mmap_dbeat_reg; + wire sig_ld_new_cmd_reg; + wire sig_ld_new_cmd_reg_reg; + wire sig_m_valid_out_reg; + wire sig_next_calc_error_reg; + wire sig_next_calc_error_reg_reg; + wire sig_next_sequential_reg; + wire sig_posted_to_axi_reg; + wire sig_s_ready_out_reg; + wire sig_single_dbeat; + wire sig_stream_rst; + wire sig_wdc_status_going_full; + wire sig_wr_fifo; + wire sig_wsc2stat_status_valid; + wire [8:0]sig_xfer_calc_err_reg_reg; + + Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f CNTR_INCR_DECR_ADDN_F_I + (.D(D[7:6]), + .E(E), + .FIFO_Full_reg({CNTR_INCR_DECR_ADDN_F_I_n_7,CNTR_INCR_DECR_ADDN_F_I_n_8}), + .FIFO_Full_reg_0(\INFERRED_GEN.cnt_i_reg[0] ), + .Q(Q[7:6]), + .fifo_full_p1(fifo_full_p1), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .p_11_out(p_11_out), + .sig_addr_posted_cntr(sig_addr_posted_cntr), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .\sig_dbeat_cntr_reg[1] (\sig_dbeat_cntr_reg[1] ), + .\sig_dbeat_cntr_reg[4] (\sig_dbeat_cntr_reg[4] ), + .sig_dqual_reg_empty(sig_dqual_reg_empty), + .sig_dqual_reg_empty_reg(sig_dqual_reg_empty_reg), + .sig_dqual_reg_empty_reg_0(sig_dqual_reg_empty_reg_0), + .sig_dqual_reg_empty_reg_1(sig_dqual_reg_empty_reg_1), + .sig_dqual_reg_full_reg(sig_dqual_reg_full_reg), + .sig_halt_reg(sig_halt_reg), + .sig_halt_reg_dly3(sig_halt_reg_dly3), + .sig_inhibit_rdy_n_reg(sig_inhibit_rdy_n_reg), + .sig_inhibit_rdy_n_reg_0(sig_inhibit_rdy_n_reg_0), + .sig_last_dbeat_reg(sig_last_dbeat_reg_0), + .sig_last_mmap_dbeat_reg(sig_last_mmap_dbeat_reg), + .sig_ld_new_cmd_reg(sig_ld_new_cmd_reg), + .sig_ld_new_cmd_reg_reg(sig_ld_new_cmd_reg_reg), + .sig_m_valid_out_reg(sig_m_valid_out_reg), + .sig_next_calc_error_reg(sig_next_calc_error_reg), + .sig_next_calc_error_reg_reg(sig_next_calc_error_reg_reg), + .sig_next_sequential_reg(sig_next_sequential_reg), + .sig_posted_to_axi_reg(sig_posted_to_axi_reg), + .sig_s_ready_out_reg(sig_s_ready_out_reg), + .sig_stream_rst(sig_stream_rst), + .sig_wdc_status_going_full(sig_wdc_status_going_full), + .sig_wr_fifo(sig_wr_fifo), + .sig_wsc2stat_status_valid(sig_wsc2stat_status_valid)); + Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized10 DYNSHREG_F_I + (.D(D[5:0]), + .FIFO_Full_reg(\INFERRED_GEN.cnt_i_reg[0] ), + .\INFERRED_GEN.cnt_i_reg[1] ({CNTR_INCR_DECR_ADDN_F_I_n_7,CNTR_INCR_DECR_ADDN_F_I_n_8}), + .Q(Q[5:0]), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out), + .p_11_out(p_11_out), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .\sig_dbeat_cntr_reg[2] (\sig_dbeat_cntr_reg[2] ), + .\sig_dbeat_cntr_reg[3] (\sig_dbeat_cntr_reg[3] ), + .sig_first_dbeat1__0(sig_first_dbeat1__0), + .sig_inhibit_rdy_n_reg(sig_inhibit_rdy_n_reg), + .sig_last_dbeat_reg(sig_last_dbeat_reg), + .sig_last_dbeat_reg_0(sig_last_dbeat_reg_0), + .sig_next_sequential_reg_reg(sig_dqual_reg_empty_reg), + .sig_single_dbeat(sig_single_dbeat), + .sig_wr_fifo(sig_wr_fifo), + .sig_xfer_calc_err_reg_reg(sig_xfer_calc_err_reg_reg)); + FDRE FIFO_Full_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(fifo_full_p1), + .Q(\INFERRED_GEN.cnt_i_reg[0] ), + .R(sig_stream_rst)); + LUT3 #( + .INIT(8'h40)) + \sig_xfer_addr_reg[31]_i_3 + (.I0(\INFERRED_GEN.cnt_i_reg[0] ), + .I1(sig_inhibit_rdy_n_reg), + .I2(p_11_out), + .O(sig_clr_cmd2data_valid4_out__0)); +endmodule + +(* ORIG_REF_NAME = "srl_fifo_rbu_f" *) +module Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized2 + (D, + sig_dqual_reg_empty_reg, + sig_next_cmd_cmplt_reg_reg, sig_dqual_reg_empty_reg_0, - sig_ld_new_cmd_reg_reg, + sel, sig_last_dbeat_reg, - sig_next_cmd_cmplt_reg_reg, + E, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram , out, SR, m_axi_mm2s_aclk, + Q, + \sig_dbeat_cntr_reg[0] , + m_axi_mm2s_rlast, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, sig_mstr2data_cmd_valid, sig_inhibit_rdy_n_0, - \sig_dbeat_cntr_reg[2] , - Q, + \sig_dbeat_cntr_reg[3] , + \sig_dbeat_cntr_reg[5] , sig_next_sequential_reg, sig_last_dbeat, sig_dqual_reg_empty, - m_axi_mm2s_rvalid, - sig_halt_reg_reg, - ram_full_i_reg, - sig_advance_pipe9_out__1, sig_rsc2stat_status_valid, - FIFO_Full_reg, + FIFO_Full_reg_0, sig_inhibit_rdy_n, - sig_next_calc_error_reg, - sig_addr_posted_cntr, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_ld_new_cmd_reg, - sig_dbeat_cntr_eq_1, + sig_next_calc_error_reg_reg, + \sig_addr_posted_cntr_reg[2] , + \sig_addr_posted_cntr_reg[1] , + \sig_addr_posted_cntr_reg[0] , + ram_full_i_reg, + sig_halt_reg_reg, + m_axi_mm2s_rvalid, sig_dqual_reg_full, - m_axi_mm2s_rlast, - \sig_dbeat_cntr_reg[3] , - \sig_dbeat_cntr_reg[4] , + sig_data2rsc_valid, in); - output sig_dqual_reg_empty_reg; - output sig_next_calc_error_reg_reg; - output [0:0]E; output [7:0]D; + output sig_dqual_reg_empty_reg; + output sig_next_cmd_cmplt_reg_reg; output sig_dqual_reg_empty_reg_0; - output sig_ld_new_cmd_reg_reg; + output sel; output sig_last_dbeat_reg; - output sig_next_cmd_cmplt_reg_reg; + output [0:0]E; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; output [3:0]out; input [0:0]SR; input m_axi_mm2s_aclk; + input [7:0]Q; + input \sig_dbeat_cntr_reg[0] ; + input m_axi_mm2s_rlast; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; input sig_mstr2data_cmd_valid; input sig_inhibit_rdy_n_0; - input \sig_dbeat_cntr_reg[2] ; - input [7:0]Q; + input \sig_dbeat_cntr_reg[3] ; + input \sig_dbeat_cntr_reg[5] ; input sig_next_sequential_reg; input sig_last_dbeat; input sig_dqual_reg_empty; - input m_axi_mm2s_rvalid; - input sig_halt_reg_reg; - input ram_full_i_reg; - input sig_advance_pipe9_out__1; input sig_rsc2stat_status_valid; - input FIFO_Full_reg; + input FIFO_Full_reg_0; input sig_inhibit_rdy_n; - input sig_next_calc_error_reg; - input [2:0]sig_addr_posted_cntr; - input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - input sig_ld_new_cmd_reg; - input sig_dbeat_cntr_eq_1; + input sig_next_calc_error_reg_reg; + input \sig_addr_posted_cntr_reg[2] ; + input \sig_addr_posted_cntr_reg[1] ; + input \sig_addr_posted_cntr_reg[0] ; + input ram_full_i_reg; + input sig_halt_reg_reg; + input m_axi_mm2s_rvalid; input sig_dqual_reg_full; - input m_axi_mm2s_rlast; - input \sig_dbeat_cntr_reg[3] ; - input \sig_dbeat_cntr_reg[4] ; - input [7:0]in; + input sig_data2rsc_valid; + input [8:0]in; + wire CNTR_INCR_DECR_ADDN_F_I_n_7; + wire CNTR_INCR_DECR_ADDN_F_I_n_8; wire [7:0]D; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; wire [0:0]E; - wire FIFO_Full_reg; + wire FIFO_Full_reg_0; + wire FIFO_Full_reg_n_0; wire [7:0]Q; wire [0:0]SR; - wire [7:0]in; + wire fifo_full_p1; + wire [8:0]in; wire m_axi_mm2s_aclk; wire m_axi_mm2s_rlast; wire m_axi_mm2s_rvalid; wire [3:0]out; wire ram_full_i_reg; - wire [2:0]sig_addr_posted_cntr; - wire sig_advance_pipe9_out__1; + wire sel; + wire \sig_addr_posted_cntr_reg[0] ; + wire \sig_addr_posted_cntr_reg[1] ; + wire \sig_addr_posted_cntr_reg[2] ; wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - wire sig_dbeat_cntr_eq_1; - wire \sig_dbeat_cntr_reg[2] ; + wire sig_data2rsc_valid; + wire \sig_dbeat_cntr_reg[0] ; wire \sig_dbeat_cntr_reg[3] ; - wire \sig_dbeat_cntr_reg[4] ; + wire \sig_dbeat_cntr_reg[5] ; wire sig_dqual_reg_empty; wire sig_dqual_reg_empty_reg; wire sig_dqual_reg_empty_reg_0; @@ -28137,35 +71816,34 @@ module Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized2 wire sig_inhibit_rdy_n_0; wire sig_last_dbeat; wire sig_last_dbeat_reg; - wire sig_ld_new_cmd_reg; - wire sig_ld_new_cmd_reg_reg; wire sig_mstr2data_cmd_valid; - wire sig_next_calc_error_reg; wire sig_next_calc_error_reg_reg; wire sig_next_cmd_cmplt_reg_reg; wire sig_next_sequential_reg; wire sig_rsc2stat_status_valid; - Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized2 I_SRL_FIFO_RBU_F - (.D(D), + Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_21 CNTR_INCR_DECR_ADDN_F_I + (.D(D[7:5]), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ), .E(E), - .FIFO_Full_reg_0(FIFO_Full_reg), - .Q(Q), + .FIFO_Full_reg({CNTR_INCR_DECR_ADDN_F_I_n_7,CNTR_INCR_DECR_ADDN_F_I_n_8}), + .FIFO_Full_reg_0(sel), + .FIFO_Full_reg_1(FIFO_Full_reg_n_0), + .FIFO_Full_reg_2(FIFO_Full_reg_0), + .Q(Q[7:4]), .SR(SR), - .in(in), + .fifo_full_p1(fifo_full_p1), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), .m_axi_mm2s_rlast(m_axi_mm2s_rlast), .m_axi_mm2s_rvalid(m_axi_mm2s_rvalid), - .out(out), .ram_full_i_reg(ram_full_i_reg), - .sel(sig_next_calc_error_reg_reg), - .sig_addr_posted_cntr(sig_addr_posted_cntr), - .sig_advance_pipe9_out__1(sig_advance_pipe9_out__1), + .\sig_addr_posted_cntr_reg[0] (\sig_addr_posted_cntr_reg[0] ), + .\sig_addr_posted_cntr_reg[1] (\sig_addr_posted_cntr_reg[1] ), + .\sig_addr_posted_cntr_reg[2] (\sig_addr_posted_cntr_reg[2] ), .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .sig_dbeat_cntr_eq_1(sig_dbeat_cntr_eq_1), - .\sig_dbeat_cntr_reg[2] (\sig_dbeat_cntr_reg[2] ), - .\sig_dbeat_cntr_reg[3] (\sig_dbeat_cntr_reg[3] ), - .\sig_dbeat_cntr_reg[4] (\sig_dbeat_cntr_reg[4] ), + .sig_data2rsc_valid(sig_data2rsc_valid), + .\sig_dbeat_cntr_reg[0] (\sig_dbeat_cntr_reg[0] ), + .\sig_dbeat_cntr_reg[5] (\sig_dbeat_cntr_reg[5] ), .sig_dqual_reg_empty(sig_dqual_reg_empty), .sig_dqual_reg_empty_reg(sig_dqual_reg_empty_reg), .sig_dqual_reg_empty_reg_0(sig_dqual_reg_empty_reg_0), @@ -28174,980 +71852,2251 @@ module Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized2 .sig_inhibit_rdy_n(sig_inhibit_rdy_n), .sig_inhibit_rdy_n_0(sig_inhibit_rdy_n_0), .sig_last_dbeat(sig_last_dbeat), - .sig_last_dbeat_reg(sig_last_dbeat_reg), - .sig_ld_new_cmd_reg(sig_ld_new_cmd_reg), - .sig_ld_new_cmd_reg_reg(sig_ld_new_cmd_reg_reg), .sig_mstr2data_cmd_valid(sig_mstr2data_cmd_valid), - .sig_next_calc_error_reg(sig_next_calc_error_reg), + .sig_next_calc_error_reg_reg(sig_next_calc_error_reg_reg), .sig_next_cmd_cmplt_reg_reg(sig_next_cmd_cmplt_reg_reg), .sig_next_sequential_reg(sig_next_sequential_reg), .sig_rsc2stat_status_valid(sig_rsc2stat_status_valid)); + Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized2 DYNSHREG_F_I + (.D(D[4:0]), + .FIFO_Full_reg(FIFO_Full_reg_n_0), + .\INFERRED_GEN.cnt_i_reg[1] ({CNTR_INCR_DECR_ADDN_F_I_n_7,CNTR_INCR_DECR_ADDN_F_I_n_8}), + .Q(Q[4:0]), + .in(in), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .out(out), + .\sig_dbeat_cntr_reg[0] (\sig_dbeat_cntr_reg[0] ), + .\sig_dbeat_cntr_reg[3] (\sig_dbeat_cntr_reg[3] ), + .sig_inhibit_rdy_n_0(sig_inhibit_rdy_n_0), + .sig_last_dbeat_reg(sig_last_dbeat_reg), + .sig_mstr2data_cmd_valid(sig_mstr2data_cmd_valid), + .sig_next_calc_error_reg_reg(sel), + .sig_next_sequential_reg_reg(sig_dqual_reg_empty_reg)); + FDRE FIFO_Full_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(fifo_full_p1), + .Q(FIFO_Full_reg_n_0), + .R(SR)); endmodule -(* ORIG_REF_NAME = "srl_fifo_f" *) -module Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized3 - (p_0_out, - FIFO_Full_reg, +(* ORIG_REF_NAME = "srl_fifo_rbu_f" *) +module Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized3 + (FIFO_Full_reg_0, \INFERRED_GEN.cnt_i_reg[1] , + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , Q, in, m_axi_mm2s_aclk, - sig_stream_rst, - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram , + SR, + lsig_cmd_loaded, + prmry_resetn_i_reg, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 , + DOBDO, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg , + sig_inhibit_rdy_n_reg, sig_mstr2sf_cmd_valid, - sig_inhibit_rdy_n_reg); - output [0:0]p_0_out; - output FIFO_Full_reg; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1 ); + output FIFO_Full_reg_0; output \INFERRED_GEN.cnt_i_reg[1] ; + output \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; output [0:0]Q; input [0:0]in; input m_axi_mm2s_aclk; - input sig_stream_rst; - input \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; - input sig_mstr2sf_cmd_valid; - input sig_inhibit_rdy_n_reg; - - wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; - wire FIFO_Full_reg; - wire \INFERRED_GEN.cnt_i_reg[1] ; - wire [0:0]Q; - wire [0:0]in; - wire m_axi_mm2s_aclk; - wire [0:0]p_0_out; - wire sig_inhibit_rdy_n_reg; - wire sig_mstr2sf_cmd_valid; - wire sig_stream_rst; - - Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized3 I_SRL_FIFO_RBU_F - (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ), - .FIFO_Full_reg_0(FIFO_Full_reg), - .\INFERRED_GEN.cnt_i_reg[1] (\INFERRED_GEN.cnt_i_reg[1] ), - .Q(Q), - .in(in), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .p_0_out(p_0_out), - .sig_inhibit_rdy_n_reg(sig_inhibit_rdy_n_reg), - .sig_mstr2sf_cmd_valid(sig_mstr2sf_cmd_valid), - .sig_stream_rst(sig_stream_rst)); -endmodule - -(* ORIG_REF_NAME = "srl_fifo_rbu_f" *) -module Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f - (Q, - E, - out, - sig_calc_error_reg_reg, - SR, - m_axi_mm2s_aclk, - sig_calc_error_pushed_reg, - sig_sm_halt_reg, - sig_input_reg_empty, - sig_calc_error_pushed, - p_55_out, - sig_inhibit_rdy_n, - cmnd_wr, - mm2s_halt, - in, - \s_axis_cmd_tdata_reg[63] ); - output [0:0]Q; - output [0:0]E; - output [49:0]out; - output sig_calc_error_reg_reg; input [0:0]SR; - input m_axi_mm2s_aclk; - input sig_calc_error_pushed_reg; - input sig_sm_halt_reg; - input sig_input_reg_empty; - input sig_calc_error_pushed; - input p_55_out; - input sig_inhibit_rdy_n; - input cmnd_wr; - input mm2s_halt; - input [0:0]in; - input [48:0]\s_axis_cmd_tdata_reg[63] ; + input lsig_cmd_loaded; + input prmry_resetn_i_reg; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; + input [0:0]DOBDO; + input \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + input sig_inhibit_rdy_n_reg; + input sig_mstr2sf_cmd_valid; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1 ; wire CNTR_INCR_DECR_ADDN_F_I_n_2; wire CNTR_INCR_DECR_ADDN_F_I_n_3; - wire [0:0]E; - wire FIFO_Full_reg_n_0; + wire [0:0]DOBDO; + wire FIFO_Full_reg_0; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1 ; + wire \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + wire \INFERRED_GEN.cnt_i_reg[1] ; wire [0:0]Q; wire [0:0]SR; - wire cmnd_wr; wire fifo_full_p1; wire [0:0]in; + wire lsig_cmd_loaded; wire m_axi_mm2s_aclk; - wire mm2s_halt; - wire [49:0]out; - wire p_55_out; - wire [48:0]\s_axis_cmd_tdata_reg[63] ; - wire sig_calc_error_pushed; - wire sig_calc_error_pushed_reg; - wire sig_calc_error_reg_reg; - wire sig_inhibit_rdy_n; - wire sig_input_reg_empty; - wire sig_sm_halt_reg; - wire sig_wr_fifo; + wire prmry_resetn_i_reg; + wire sig_inhibit_rdy_n_reg; + wire sig_mstr2sf_cmd_valid; - Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_3 CNTR_INCR_DECR_ADDN_F_I - (.FIFO_Full_reg(FIFO_Full_reg_n_0), + Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_29 CNTR_INCR_DECR_ADDN_F_I + (.DOBDO(DOBDO), + .FIFO_Full_reg(FIFO_Full_reg_0), + .FIFO_Full_reg_0(\INFERRED_GEN.cnt_i_reg[1] ), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1 ), + .\INCLUDE_UNPACKING.lsig_cmd_loaded_reg (\INCLUDE_UNPACKING.lsig_cmd_loaded_reg ), .Q({Q,CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3}), .SR(SR), .fifo_full_p1(fifo_full_p1), + .lsig_cmd_loaded(lsig_cmd_loaded), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .p_55_out(p_55_out), - .sig_calc_error_pushed(sig_calc_error_pushed), - .sig_calc_error_pushed_reg(sig_calc_error_pushed_reg), - .sig_inhibit_rdy_n(sig_inhibit_rdy_n), - .sig_input_reg_empty(sig_input_reg_empty), - .sig_sm_halt_reg(sig_sm_halt_reg), - .sig_wr_fifo(sig_wr_fifo)); - Arty_Z7_20_axi_vdma_0_0_dynshreg_f DYNSHREG_F_I - (.FIFO_Full_reg(FIFO_Full_reg_n_0), + .sig_inhibit_rdy_n_reg(sig_inhibit_rdy_n_reg), + .sig_mstr2sf_cmd_valid(sig_mstr2sf_cmd_valid)); + Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized3 DYNSHREG_F_I + (.DOBDO(DOBDO), + .FIFO_Full_reg(FIFO_Full_reg_0), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), .Q({Q,CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3}), .in(in), + .lsig_cmd_loaded(lsig_cmd_loaded), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .out(out), - .p_55_out(p_55_out), - .\s_axis_cmd_tdata_reg[63] (\s_axis_cmd_tdata_reg[63] ), - .sig_calc_error_reg_reg(sig_calc_error_reg_reg), - .sig_inhibit_rdy_n(sig_inhibit_rdy_n), - .sig_input_reg_empty(sig_input_reg_empty), - .sig_sm_halt_reg(sig_sm_halt_reg), - .sig_wr_fifo(sig_wr_fifo)); + .prmry_resetn_i_reg(prmry_resetn_i_reg)); FDRE FIFO_Full_reg (.C(m_axi_mm2s_aclk), .CE(1'b1), .D(fifo_full_p1), - .Q(FIFO_Full_reg_n_0), + .Q(\INFERRED_GEN.cnt_i_reg[1] ), .R(SR)); - LUT4 #( - .INIT(16'hFFAE)) - \s_axis_cmd_tdata[63]_i_2 - (.I0(cmnd_wr), - .I1(sig_inhibit_rdy_n), - .I2(FIFO_Full_reg_n_0), - .I3(mm2s_halt), - .O(E)); endmodule (* ORIG_REF_NAME = "srl_fifo_rbu_f" *) -module Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized0 - (\INFERRED_GEN.cnt_i_reg[1] , +module Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized4 + (p_9_out, Q, - sig_rd_sts_slverr_reg_reg, - interr_i_reg, - slverr_i_reg, + CO, + \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg , decerr_i_reg, - SR, - m_axi_mm2s_aclk, - p_57_out, - sig_rsc2stat_status_valid, - sig_inhibit_rdy_n_reg, - sts_tready_reg, + slverr_i_reg, + interr_i_reg, + sig_dqual_reg_empty_reg, + \GEN_STS_GRTR_THAN_8.ovrflo_err_reg , + sig_stream_rst, + m_axi_s2mm_aclk, + s2mm_halt, + s2mm_soft_reset, + dma_err, + \hsize_vid_reg[15] , + \hsize_vid_reg[2] , + S, + sig_inhibit_rdy_n, + sig_wsc2stat_status_valid, sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_rd_sts_slverr_reg_reg_0); - output \INFERRED_GEN.cnt_i_reg[1] ; + m_axis_s2mm_sts_tready, + in); + output p_9_out; output [0:0]Q; - output sig_rd_sts_slverr_reg_reg; - output interr_i_reg; - output slverr_i_reg; + output [0:0]CO; + output \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ; output decerr_i_reg; - input [0:0]SR; - input m_axi_mm2s_aclk; - input p_57_out; - input sig_rsc2stat_status_valid; - input sig_inhibit_rdy_n_reg; - input sts_tready_reg; + output slverr_i_reg; + output interr_i_reg; + output sig_dqual_reg_empty_reg; + output [0:0]\GEN_STS_GRTR_THAN_8.ovrflo_err_reg ; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input s2mm_halt; + input s2mm_soft_reset; + input dma_err; + input [12:0]\hsize_vid_reg[15] ; + input [0:0]\hsize_vid_reg[2] ; + input [0:0]S; + input sig_inhibit_rdy_n; + input sig_wsc2stat_status_valid; input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - input [2:0]sig_rd_sts_slverr_reg_reg_0; + input m_axis_s2mm_sts_tready; + input [16:0]in; wire CNTR_INCR_DECR_ADDN_F_I_n_2; wire CNTR_INCR_DECR_ADDN_F_I_n_3; - wire \INFERRED_GEN.cnt_i_reg[1] ; + wire [0:0]CO; + wire DYNSHREG_F_I_n_3; + wire FIFO_Full_reg_n_0; + wire \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ; + wire [0:0]\GEN_STS_GRTR_THAN_8.ovrflo_err_reg ; wire [0:0]Q; - wire [0:0]SR; + wire [0:0]S; wire decerr_i_reg; + wire dma_err; wire fifo_full_p1; + wire [12:0]\hsize_vid_reg[15] ; + wire [0:0]\hsize_vid_reg[2] ; + wire [16:0]in; wire interr_i_reg; - wire m_axi_mm2s_aclk; - wire p_57_out; + wire m_axi_s2mm_aclk; + wire [31:31]m_axis_s2mm_sts_tdata; + wire m_axis_s2mm_sts_tready; + wire p_9_out; + wire s2mm_halt; + wire s2mm_soft_reset; wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - wire sig_inhibit_rdy_n_reg; - wire sig_rd_sts_slverr_reg_reg; - wire [2:0]sig_rd_sts_slverr_reg_reg_0; - wire sig_rsc2stat_status_valid; + wire sig_dqual_reg_empty_reg; + wire sig_inhibit_rdy_n; + wire sig_stream_rst; wire sig_wr_fifo; + wire sig_wsc2stat_status_valid; wire slverr_i_reg; - wire sts_tready_reg; - Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_4 CNTR_INCR_DECR_ADDN_F_I - (.FIFO_Full_reg(\INFERRED_GEN.cnt_i_reg[1] ), + Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_17 CNTR_INCR_DECR_ADDN_F_I + (.CO(DYNSHREG_F_I_n_3), + .FIFO_Full_reg(FIFO_Full_reg_n_0), .Q({Q,CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3}), - .SR(SR), + .dma_err(dma_err), .fifo_full_p1(fifo_full_p1), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .p_57_out(p_57_out), - .sig_inhibit_rdy_n_reg(sig_inhibit_rdy_n_reg), - .sig_rsc2stat_status_valid(sig_rsc2stat_status_valid), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .m_axis_s2mm_sts_tready(m_axis_s2mm_sts_tready), + .out(m_axis_s2mm_sts_tdata), + .p_9_out(p_9_out), + .s2mm_halt(s2mm_halt), + .s2mm_soft_reset(s2mm_soft_reset), + .sig_inhibit_rdy_n(sig_inhibit_rdy_n), + .sig_stream_rst(sig_stream_rst), .sig_wr_fifo(sig_wr_fifo), - .sts_tready_reg(sts_tready_reg)); - Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized0 DYNSHREG_F_I - (.FIFO_Full_reg(\INFERRED_GEN.cnt_i_reg[1] ), + .sig_wsc2stat_status_valid(sig_wsc2stat_status_valid)); + Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized4 DYNSHREG_F_I + (.CO(CO), + .FIFO_Full_reg(FIFO_Full_reg_n_0), + .\GEN_STS_GRTR_THAN_8.ovrflo_err_reg (DYNSHREG_F_I_n_3), .Q({Q,CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3}), + .S(S), .decerr_i_reg(decerr_i_reg), + .\hsize_vid_reg[15] (\hsize_vid_reg[15] ), + .\hsize_vid_reg[2] (\hsize_vid_reg[2] ), + .in(in), .interr_i_reg(interr_i_reg), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .sig_inhibit_rdy_n_reg(sig_inhibit_rdy_n_reg), - .sig_rd_sts_slverr_reg_reg(sig_rd_sts_slverr_reg_reg_0), - .sig_rsc2stat_status_valid(sig_rsc2stat_status_valid), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out({m_axis_s2mm_sts_tdata,\GEN_STS_GRTR_THAN_8.ovrflo_err_reg }), + .sig_inhibit_rdy_n(sig_inhibit_rdy_n), .sig_wr_fifo(sig_wr_fifo), + .sig_wsc2stat_status_valid(sig_wsc2stat_status_valid), .slverr_i_reg(slverr_i_reg)); FDRE FIFO_Full_reg - (.C(m_axi_mm2s_aclk), + (.C(m_axi_s2mm_aclk), .CE(1'b1), .D(fifo_full_p1), - .Q(\INFERRED_GEN.cnt_i_reg[1] ), - .R(SR)); + .Q(FIFO_Full_reg_n_0), + .R(sig_stream_rst)); + (* SOFT_HLUTNM = "soft_lutpair238" *) LUT4 #( .INIT(16'h20FF)) - sig_rd_sts_reg_full_i_1 - (.I0(sig_inhibit_rdy_n_reg), - .I1(\INFERRED_GEN.cnt_i_reg[1] ), - .I2(sig_rsc2stat_status_valid), + \GEN_ENABLE_INDET_BTT.sig_coelsc_reg_empty_i_1 + (.I0(sig_inhibit_rdy_n), + .I1(FIFO_Full_reg_n_0), + .I2(sig_wsc2stat_status_valid), .I3(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .O(sig_rd_sts_slverr_reg_reg)); + .O(\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg )); + (* SOFT_HLUTNM = "soft_lutpair238" *) + LUT2 #( + .INIT(4'h2)) + sig_next_calc_error_reg_i_7 + (.I0(sig_inhibit_rdy_n), + .I1(FIFO_Full_reg_n_0), + .O(sig_dqual_reg_empty_reg)); endmodule (* ORIG_REF_NAME = "srl_fifo_rbu_f" *) -module Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized1 - (sig_calc_error_reg_reg, - sel, - sig_posted_to_axi_reg, - sig_addr_valid_reg_reg, +module Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized5 + (\GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg , + \GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg , + D, + \INFERRED_GEN.cnt_i_reg[2] , + E, + m_axi_s2mm_bready, + sig_stream_rst, + m_axi_s2mm_aclk, + in, out, - SR, - m_axi_mm2s_aclk, - sig_mstr2addr_cmd_valid, + sig_posted_to_axi_reg, + Q, + sig_push_coelsc_reg, + m_axi_s2mm_bvalid, sig_inhibit_rdy_n, + \INFERRED_GEN.cnt_i_reg[3] , + sig_halt_reg, + m_axi_s2mm_bresp); + output \GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg ; + output \GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg ; + output [2:0]D; + output [0:0]\INFERRED_GEN.cnt_i_reg[2] ; + output [0:0]E; + output m_axi_s2mm_bready; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input [1:0]in; + input [0:0]out; + input sig_posted_to_axi_reg; + input [3:0]Q; + input sig_push_coelsc_reg; + input m_axi_s2mm_bvalid; + input sig_inhibit_rdy_n; + input \INFERRED_GEN.cnt_i_reg[3] ; + input sig_halt_reg; + input [1:0]m_axi_s2mm_bresp; + + wire CNTR_INCR_DECR_ADDN_F_I_n_2; + wire CNTR_INCR_DECR_ADDN_F_I_n_3; + wire CNTR_INCR_DECR_ADDN_F_I_n_4; + wire [2:0]D; + wire [0:0]E; + wire FIFO_Full_reg_n_0; + wire \GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg ; + wire \GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg ; + wire [0:0]\INFERRED_GEN.cnt_i_reg[2] ; + wire \INFERRED_GEN.cnt_i_reg[3] ; + wire [3:0]Q; + wire fifo_full_p1; + wire [1:0]in; + wire m_axi_s2mm_aclk; + wire m_axi_s2mm_bready; + wire [1:0]m_axi_s2mm_bresp; + wire m_axi_s2mm_bvalid; + wire [0:0]out; + wire sig_decr_addr_posted_cntr5_out; + wire sig_halt_reg; + wire sig_inhibit_rdy_n; + wire sig_posted_to_axi_reg; + wire sig_push_coelsc_reg; + wire sig_stream_rst; + wire sig_wr_fifo; + + Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f__parameterized0 CNTR_INCR_DECR_ADDN_F_I + (.FIFO_Full_reg(FIFO_Full_reg_n_0), + .\INFERRED_GEN.cnt_i_reg[3]_0 (\INFERRED_GEN.cnt_i_reg[3] ), + .Q({\INFERRED_GEN.cnt_i_reg[2] ,CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3,CNTR_INCR_DECR_ADDN_F_I_n_4}), + .fifo_full_p1(fifo_full_p1), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .m_axi_s2mm_bvalid(m_axi_s2mm_bvalid), + .sig_inhibit_rdy_n(sig_inhibit_rdy_n), + .sig_push_coelsc_reg(sig_push_coelsc_reg), + .sig_stream_rst(sig_stream_rst), + .sig_wr_fifo(sig_wr_fifo)); + Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized5 DYNSHREG_F_I + (.\GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg (\GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg ), + .\GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg (\GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg ), + .addr({CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3,CNTR_INCR_DECR_ADDN_F_I_n_4}), + .in(in), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .m_axi_s2mm_bresp(m_axi_s2mm_bresp), + .out(out), + .sel(sig_wr_fifo)); + FDRE FIFO_Full_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(fifo_full_p1), + .Q(FIFO_Full_reg_n_0), + .R(sig_stream_rst)); + (* SOFT_HLUTNM = "soft_lutpair251" *) + LUT3 #( + .INIT(8'hF4)) + m_axi_s2mm_bready_INST_0 + (.I0(FIFO_Full_reg_n_0), + .I1(sig_inhibit_rdy_n), + .I2(sig_halt_reg), + .O(m_axi_s2mm_bready)); + LUT6 #( + .INIT(64'hFDDD22222222DDDD)) + \sig_addr_posted_cntr[1]_i_1__0 + (.I0(sig_posted_to_axi_reg), + .I1(sig_decr_addr_posted_cntr5_out), + .I2(Q[3]), + .I3(Q[2]), + .I4(Q[0]), + .I5(Q[1]), + .O(D[0])); + LUT6 #( + .INIT(64'hFD22FF00FF0022DD)) + \sig_addr_posted_cntr[2]_i_1__0 + (.I0(sig_posted_to_axi_reg), + .I1(sig_decr_addr_posted_cntr5_out), + .I2(Q[3]), + .I3(Q[2]), + .I4(Q[0]), + .I5(Q[1]), + .O(D[1])); + LUT6 #( + .INIT(64'h0000FFFE7FFF0000)) + \sig_addr_posted_cntr[3]_i_1 + (.I0(Q[1]), + .I1(Q[0]), + .I2(Q[2]), + .I3(Q[3]), + .I4(sig_posted_to_axi_reg), + .I5(sig_decr_addr_posted_cntr5_out), + .O(E)); + LUT6 #( + .INIT(64'hF2F0F0F0F0F0F02D)) + \sig_addr_posted_cntr[3]_i_2 + (.I0(sig_posted_to_axi_reg), + .I1(sig_decr_addr_posted_cntr5_out), + .I2(Q[3]), + .I3(Q[2]), + .I4(Q[0]), + .I5(Q[1]), + .O(D[2])); + (* SOFT_HLUTNM = "soft_lutpair251" *) + LUT3 #( + .INIT(8'h40)) + \sig_addr_posted_cntr[3]_i_3 + (.I0(FIFO_Full_reg_n_0), + .I1(sig_inhibit_rdy_n), + .I2(m_axi_s2mm_bvalid), + .O(sig_decr_addr_posted_cntr5_out)); +endmodule + +(* ORIG_REF_NAME = "srl_fifo_rbu_f" *) +module Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized6 + (p_0_in, + out, + sig_push_to_wsc_reg, + D, + sel, + \INFERRED_GEN.cnt_i_reg[1] , + \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg , + E, + p_4_out, + sig_stream_rst, + m_axi_s2mm_aclk, sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_data2addr_stop_req, - sig_addr_reg_empty, - sig_sf_allow_addr_req, - in); - output sig_calc_error_reg_reg; + sig_inhibit_rdy_n, + sig_data2wsc_valid, + sig_set_push2wsc, + Q, + \INFERRED_GEN.cnt_i_reg[3] , + sig_coelsc_reg_empty, + in, + \GEN_INDET_BTT.lsig_eop_reg_reg ); + output p_0_in; + output [15:0]out; + output sig_push_to_wsc_reg; + output [2:0]D; output sel; - output sig_posted_to_axi_reg; - output sig_addr_valid_reg_reg; - output [39:0]out; - input [0:0]SR; - input m_axi_mm2s_aclk; - input sig_mstr2addr_cmd_valid; - input sig_inhibit_rdy_n; + output \INFERRED_GEN.cnt_i_reg[1] ; + output \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ; + output [0:0]E; + output p_4_out; + input sig_stream_rst; + input m_axi_s2mm_aclk; input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - input sig_data2addr_stop_req; - input sig_addr_reg_empty; - input sig_sf_allow_addr_req; - input [37:0]in; + input sig_inhibit_rdy_n; + input sig_data2wsc_valid; + input sig_set_push2wsc; + input [3:0]Q; + input [0:0]\INFERRED_GEN.cnt_i_reg[3] ; + input sig_coelsc_reg_empty; + input [0:0]in; + input [15:0]\GEN_INDET_BTT.lsig_eop_reg_reg ; wire CNTR_INCR_DECR_ADDN_F_I_n_2; wire CNTR_INCR_DECR_ADDN_F_I_n_3; + wire CNTR_INCR_DECR_ADDN_F_I_n_4; + wire [2:0]D; + wire DYNSHREG_F_I_n_21; + wire [0:0]E; wire FIFO_Full_reg_n_0; - wire [0:0]SR; + wire \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ; + wire [15:0]\GEN_INDET_BTT.lsig_eop_reg_reg ; + wire \INFERRED_GEN.cnt_i_reg[1] ; + wire [0:0]\INFERRED_GEN.cnt_i_reg[3] ; + wire [3:0]Q; wire fifo_full_p1; - wire [37:0]in; - wire m_axi_mm2s_aclk; - wire [39:0]out; + wire [0:0]in; + wire m_axi_s2mm_aclk; + wire [15:0]out; + wire p_0_in; + wire p_4_out; wire sel; - wire sig_addr_reg_empty; - wire sig_addr_valid_reg_reg; - wire sig_calc_error_reg_reg; wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - wire sig_data2addr_stop_req; - wire sig_inhibit_rdy_n; - wire sig_mstr2addr_cmd_valid; - wire sig_posted_to_axi_reg; - wire sig_sf_allow_addr_req; + wire sig_coelsc_reg_empty; + wire sig_data2wsc_valid; + wire sig_inhibit_rdy_n; + wire sig_push_to_wsc_reg; + wire sig_rd_empty; + wire sig_set_push2wsc; + wire sig_stream_rst; + + Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f__parameterized1 CNTR_INCR_DECR_ADDN_F_I + (.FIFO_Full_reg(FIFO_Full_reg_n_0), + .\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg (\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg ), + .\INFERRED_GEN.cnt_i_reg[1]_0 (\INFERRED_GEN.cnt_i_reg[1] ), + .\INFERRED_GEN.cnt_i_reg[3]_0 (\INFERRED_GEN.cnt_i_reg[3] ), + .\INFERRED_GEN.cnt_i_reg[3]_1 (DYNSHREG_F_I_n_21), + .Q({sig_rd_empty,CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3,CNTR_INCR_DECR_ADDN_F_I_n_4}), + .fifo_full_p1(fifo_full_p1), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out[0]), + .sig_coelsc_reg_empty(sig_coelsc_reg_empty), + .sig_data2wsc_valid(sig_data2wsc_valid), + .sig_inhibit_rdy_n(sig_inhibit_rdy_n), + .sig_push_to_wsc_reg(sel), + .sig_stream_rst(sig_stream_rst)); + Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized6 DYNSHREG_F_I + (.D(D), + .E(E), + .FIFO_Full_reg(FIFO_Full_reg_n_0), + .\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg (sel), + .\GEN_INDET_BTT.lsig_eop_reg_reg (\GEN_INDET_BTT.lsig_eop_reg_reg ), + .\INFERRED_GEN.cnt_i_reg[3] (\INFERRED_GEN.cnt_i_reg[3] ), + .\INFERRED_GEN.cnt_i_reg[3]_0 ({sig_rd_empty,CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3,CNTR_INCR_DECR_ADDN_F_I_n_4}), + .Q(Q), + .in(in), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out), + .p_0_in(p_0_in), + .p_4_out(p_4_out), + .sig_coelsc_reg_empty(sig_coelsc_reg_empty), + .sig_data2wsc_valid(sig_data2wsc_valid), + .sig_inhibit_rdy_n(sig_inhibit_rdy_n), + .\sig_wdc_statcnt_reg[3] (DYNSHREG_F_I_n_21)); + FDRE FIFO_Full_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(fifo_full_p1), + .Q(FIFO_Full_reg_n_0), + .R(sig_stream_rst)); + LUT5 #( + .INIT(32'hAAAAA200)) + sig_push_to_wsc_i_1 + (.I0(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I1(sig_inhibit_rdy_n), + .I2(FIFO_Full_reg_n_0), + .I3(sig_data2wsc_valid), + .I4(sig_set_push2wsc), + .O(sig_push_to_wsc_reg)); +endmodule + +(* ORIG_REF_NAME = "srl_fifo_rbu_f" *) +module Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized7 + (\INFERRED_GEN.cnt_i_reg[0] , + Q, + \GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg , + out, + sig_sm_pop_cmd_fifo_ns, + sig_sm_ld_dre_cmd_ns, + D, + sig_stream_rst, + m_axi_s2mm_aclk, + sig_need_cmd_flush, + p_7_out, + sig_sm_pop_cmd_fifo, + p_9_out_0, + sig_inhibit_rdy_n_reg, + lsig_cmd_fetch_pause, + E, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_good_tlast_dbeat37_out__0, + in, + \FSM_sequential_sig_cmdcntl_sm_state_reg[0] , + \FSM_sequential_sig_cmdcntl_sm_state_reg[2] , + sig_cmd_empty_reg); + output \INFERRED_GEN.cnt_i_reg[0] ; + output [0:0]Q; + output \GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg ; + output [19:0]out; + output sig_sm_pop_cmd_fifo_ns; + output sig_sm_ld_dre_cmd_ns; + output [2:0]D; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input sig_need_cmd_flush; + input p_7_out; + input sig_sm_pop_cmd_fifo; + input p_9_out_0; + input sig_inhibit_rdy_n_reg; + input lsig_cmd_fetch_pause; + input [0:0]E; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_good_tlast_dbeat37_out__0; + input [21:0]in; + input \FSM_sequential_sig_cmdcntl_sm_state_reg[0] ; + input [2:0]\FSM_sequential_sig_cmdcntl_sm_state_reg[2] ; + input sig_cmd_empty_reg; + + wire CNTR_INCR_DECR_ADDN_F_I_n_1; + wire CNTR_INCR_DECR_ADDN_F_I_n_2; + wire [2:0]D; + wire DYNSHREG_F_I_n_0; + wire [0:0]E; + wire \FSM_sequential_sig_cmdcntl_sm_state_reg[0] ; + wire [2:0]\FSM_sequential_sig_cmdcntl_sm_state_reg[2] ; + wire \GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg ; + wire \INFERRED_GEN.cnt_i_reg[0] ; + wire [0:0]Q; + wire fifo_full_p1; + wire [21:0]in; + wire lsig_cmd_fetch_pause; + wire m_axi_s2mm_aclk; + wire [19:0]out; + wire p_7_out; + wire p_9_out_0; + wire sig_cmd_empty_reg; + wire [25:25]sig_cmd_fifo_data_out; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_good_tlast_dbeat37_out__0; + wire sig_inhibit_rdy_n_reg; + wire sig_need_cmd_flush; + wire sig_sm_ld_dre_cmd_ns; + wire sig_sm_pop_cmd_fifo; + wire sig_sm_pop_cmd_fifo_ns; + wire sig_stream_rst; + wire sig_wr_fifo; - Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_5 CNTR_INCR_DECR_ADDN_F_I - (.FIFO_Full_reg(FIFO_Full_reg_n_0), - .Q({CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3}), - .SR(SR), + Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_19 CNTR_INCR_DECR_ADDN_F_I + (.D({D[2],D[0]}), + .FIFO_Full_reg(\INFERRED_GEN.cnt_i_reg[0] ), + .\FSM_sequential_sig_cmdcntl_sm_state_reg[2] (\FSM_sequential_sig_cmdcntl_sm_state_reg[2] ), + .\INFERRED_GEN.cnt_i_reg[2]_0 (DYNSHREG_F_I_n_0), + .Q({Q,CNTR_INCR_DECR_ADDN_F_I_n_1,CNTR_INCR_DECR_ADDN_F_I_n_2}), .fifo_full_p1(fifo_full_p1), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .sig_addr_reg_empty(sig_addr_reg_empty), - .sig_calc_error_reg_reg(sig_calc_error_reg_reg), - .sig_cmd2addr_valid_reg(sel), - .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .sig_data2addr_stop_req(sig_data2addr_stop_req), - .sig_inhibit_rdy_n(sig_inhibit_rdy_n), - .sig_mstr2addr_cmd_valid(sig_mstr2addr_cmd_valid), - .sig_posted_to_axi_reg(sig_posted_to_axi_reg), - .sig_sf_allow_addr_req(sig_sf_allow_addr_req)); - Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1 DYNSHREG_F_I - (.FIFO_Full_reg(FIFO_Full_reg_n_0), - .Q({CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3}), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(sig_cmd_fifo_data_out), + .p_7_out(p_7_out), + .p_9_out_0(p_9_out_0), + .sig_cmd_empty_reg(sig_cmd_empty_reg), + .sig_inhibit_rdy_n_reg(sig_inhibit_rdy_n_reg), + .sig_need_cmd_flush(sig_need_cmd_flush), + .sig_sm_ld_dre_cmd_ns(sig_sm_ld_dre_cmd_ns), + .sig_sm_pop_cmd_fifo(sig_sm_pop_cmd_fifo), + .sig_stream_rst(sig_stream_rst), + .sig_wr_fifo(sig_wr_fifo)); + Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized7 DYNSHREG_F_I + (.D(D[1]), + .E(E), + .FIFO_Full_reg(\INFERRED_GEN.cnt_i_reg[0] ), + .\FSM_sequential_sig_cmdcntl_sm_state_reg[0] (DYNSHREG_F_I_n_0), + .\FSM_sequential_sig_cmdcntl_sm_state_reg[0]_0 (\FSM_sequential_sig_cmdcntl_sm_state_reg[0] ), + .\FSM_sequential_sig_cmdcntl_sm_state_reg[2] (\FSM_sequential_sig_cmdcntl_sm_state_reg[2] ), + .\GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg (\GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg ), + .Q({Q,CNTR_INCR_DECR_ADDN_F_I_n_1,CNTR_INCR_DECR_ADDN_F_I_n_2}), .in(in), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .out(out), - .sig_addr_valid_reg_reg(sig_addr_valid_reg_reg), - .sig_calc_error_reg_reg(sel), - .sig_inhibit_rdy_n(sig_inhibit_rdy_n), - .sig_mstr2addr_cmd_valid(sig_mstr2addr_cmd_valid)); + .lsig_cmd_fetch_pause(lsig_cmd_fetch_pause), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out({out[19:17],sig_cmd_fifo_data_out,out[16:0]}), + .p_7_out(p_7_out), + .p_9_out_0(p_9_out_0), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_good_tlast_dbeat37_out__0(sig_good_tlast_dbeat37_out__0), + .sig_inhibit_rdy_n_reg(sig_inhibit_rdy_n_reg), + .sig_need_cmd_flush(sig_need_cmd_flush), + .sig_sm_pop_cmd_fifo_ns(sig_sm_pop_cmd_fifo_ns), + .sig_wr_fifo(sig_wr_fifo)); FDRE FIFO_Full_reg - (.C(m_axi_mm2s_aclk), + (.C(m_axi_s2mm_aclk), .CE(1'b1), .D(fifo_full_p1), - .Q(FIFO_Full_reg_n_0), - .R(SR)); + .Q(\INFERRED_GEN.cnt_i_reg[0] ), + .R(sig_stream_rst)); endmodule (* ORIG_REF_NAME = "srl_fifo_rbu_f" *) -module Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized2 - (sig_dqual_reg_empty_reg, - sel, - E, - D, - sig_dqual_reg_empty_reg_0, - sig_ld_new_cmd_reg_reg, - sig_last_dbeat_reg, - sig_next_cmd_cmplt_reg_reg, - out, +module Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized8 + (\INFERRED_GEN.cnt_i_reg[1] , + SS, + \INCLUDE_PACKING.lsig_first_dbeat_reg , + \sig_byte_cntr_reg[0] , + sig_dre2ibtt_tlast, + sig_cmd_full_reg, + sig_cmd_empty_reg, + sig_good_tlast_dbeat37_out__0, SR, - m_axi_mm2s_aclk, - sig_mstr2data_cmd_valid, - sig_inhibit_rdy_n_0, - \sig_dbeat_cntr_reg[2] , + E, Q, - sig_next_sequential_reg, - sig_last_dbeat, - sig_dqual_reg_empty, - m_axi_mm2s_rvalid, - sig_halt_reg_reg, - ram_full_i_reg, - sig_advance_pipe9_out__1, - sig_rsc2stat_status_valid, - FIFO_Full_reg_0, - sig_inhibit_rdy_n, - sig_next_calc_error_reg, - sig_addr_posted_cntr, + sig_s_ready_dup4_reg, + \sig_byte_cntr_reg[7] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] , + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] , + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] , + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] , + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] , + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] , + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] , + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] , + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] , + sig_eop_sent, + \GEN_INDET_BTT.lsig_absorb2tlast_reg , + \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg , + m_axi_s2mm_aclk, + \INCLUDE_PACKING.lsig_first_dbeat_reg_0 , + sig_cmd_full, + sig_sm_ld_dre_cmd, + p_7_out, + sig_strm_tlast, + sig_m_valid_out_reg, + lsig_absorb2tlast, sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_ld_new_cmd_reg, - sig_dbeat_cntr_eq_1, - sig_dqual_reg_full, - m_axi_mm2s_rlast, - \sig_dbeat_cntr_reg[3] , - \sig_dbeat_cntr_reg[4] , + sig_last_reg_out_reg, + sig_eop_halt_xfer, + sig_ibtt2dre_tready, + out, + sig_clr_dbc_reg, + sig_eop_sent_reg, + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 , + sig_inhibit_rdy_n_reg, + slice_insert_valid, + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 , + p_0_in, + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 , + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 , + lsig_cmd_fetch_pause, + sig_need_cmd_flush, + sig_sm_pop_cmd_fifo, in); - output sig_dqual_reg_empty_reg; - output sel; + output \INFERRED_GEN.cnt_i_reg[1] ; + output [0:0]SS; + output \INCLUDE_PACKING.lsig_first_dbeat_reg ; + output \sig_byte_cntr_reg[0] ; + output sig_dre2ibtt_tlast; + output sig_cmd_full_reg; + output sig_cmd_empty_reg; + output sig_good_tlast_dbeat37_out__0; + output [0:0]SR; output [0:0]E; - output [7:0]D; - output sig_dqual_reg_empty_reg_0; - output sig_ld_new_cmd_reg_reg; - output sig_last_dbeat_reg; - output sig_next_cmd_cmplt_reg_reg; - output [3:0]out; - input [0:0]SR; - input m_axi_mm2s_aclk; - input sig_mstr2data_cmd_valid; - input sig_inhibit_rdy_n_0; - input \sig_dbeat_cntr_reg[2] ; - input [7:0]Q; - input sig_next_sequential_reg; - input sig_last_dbeat; - input sig_dqual_reg_empty; - input m_axi_mm2s_rvalid; - input sig_halt_reg_reg; - input ram_full_i_reg; - input sig_advance_pipe9_out__1; - input sig_rsc2stat_status_valid; - input FIFO_Full_reg_0; - input sig_inhibit_rdy_n; - input sig_next_calc_error_reg; - input [2:0]sig_addr_posted_cntr; + output [0:0]Q; + output sig_s_ready_dup4_reg; + output [0:0]\sig_byte_cntr_reg[7] ; + output \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ; + output \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] ; + output sig_eop_sent; + output [0:0]\GEN_INDET_BTT.lsig_absorb2tlast_reg ; + output \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg ; + input m_axi_s2mm_aclk; + input \INCLUDE_PACKING.lsig_first_dbeat_reg_0 ; + input sig_cmd_full; + input sig_sm_ld_dre_cmd; + input p_7_out; + input sig_strm_tlast; + input sig_m_valid_out_reg; + input lsig_absorb2tlast; input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - input sig_ld_new_cmd_reg; - input sig_dbeat_cntr_eq_1; - input sig_dqual_reg_full; - input m_axi_mm2s_rlast; - input \sig_dbeat_cntr_reg[3] ; - input \sig_dbeat_cntr_reg[4] ; - input [7:0]in; + input sig_last_reg_out_reg; + input sig_eop_halt_xfer; + input sig_ibtt2dre_tready; + input out; + input sig_clr_dbc_reg; + input sig_eop_sent_reg; + input [1:0]\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1] ; + input [1:0]\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ; + input sig_inhibit_rdy_n_reg; + input slice_insert_valid; + input \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ; + input p_0_in; + input \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ; + input \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ; + input lsig_cmd_fetch_pause; + input sig_need_cmd_flush; + input sig_sm_pop_cmd_fifo; + input [1:0]in; - wire CNTR_INCR_DECR_ADDN_F_I_n_2; - wire CNTR_INCR_DECR_ADDN_F_I_n_3; - wire [7:0]D; + wire CNTR_INCR_DECR_ADDN_F_I_n_10; + wire CNTR_INCR_DECR_ADDN_F_I_n_11; + wire CNTR_INCR_DECR_ADDN_F_I_n_12; + wire CNTR_INCR_DECR_ADDN_F_I_n_9; wire [0:0]E; - wire FIFO_Full_reg_0; - wire FIFO_Full_reg_n_0; - wire [7:0]Q; + wire \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg ; + wire [0:0]\GEN_INDET_BTT.lsig_absorb2tlast_reg ; + wire [1:0]\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] ; + wire \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ; + wire [1:0]\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ; + wire \INCLUDE_PACKING.lsig_first_dbeat_reg ; + wire \INCLUDE_PACKING.lsig_first_dbeat_reg_0 ; + wire \INFERRED_GEN.cnt_i_reg[1] ; + wire [0:0]Q; wire [0:0]SR; + wire [0:0]SS; wire fifo_full_p1; - wire [7:0]in; - wire m_axi_mm2s_aclk; - wire m_axi_mm2s_rlast; - wire m_axi_mm2s_rvalid; - wire [3:0]out; - wire ram_full_i_reg; - wire sel; - wire [2:0]sig_addr_posted_cntr; - wire sig_advance_pipe9_out__1; + wire [1:0]in; + wire lsig_absorb2tlast; + wire lsig_cmd_fetch_pause; + wire m_axi_s2mm_aclk; + wire out; + wire p_0_in; + wire p_7_out; + wire \sig_byte_cntr_reg[0] ; + wire [0:0]\sig_byte_cntr_reg[7] ; + wire sig_clr_dbc_reg; + wire sig_cmd_empty_reg; + wire sig_cmd_full; + wire sig_cmd_full_reg; wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - wire sig_dbeat_cntr_eq_1; - wire \sig_dbeat_cntr_reg[2] ; - wire \sig_dbeat_cntr_reg[3] ; - wire \sig_dbeat_cntr_reg[4] ; - wire sig_dqual_reg_empty; - wire sig_dqual_reg_empty_reg; - wire sig_dqual_reg_empty_reg_0; - wire sig_dqual_reg_full; - wire sig_halt_reg_reg; - wire sig_inhibit_rdy_n; - wire sig_inhibit_rdy_n_0; - wire sig_last_dbeat; - wire sig_last_dbeat_reg; - wire sig_ld_new_cmd_reg; - wire sig_ld_new_cmd_reg_reg; - wire sig_mstr2data_cmd_valid; - wire sig_next_calc_error_reg; - wire sig_next_cmd_cmplt_reg_reg; - wire sig_next_sequential_reg; - wire sig_rsc2stat_status_valid; + wire sig_dre2ibtt_tlast; + wire sig_eop_halt_xfer; + wire sig_eop_sent; + wire sig_eop_sent_reg; + wire sig_good_tlast_dbeat37_out__0; + wire sig_ibtt2dre_tready; + wire sig_inhibit_rdy_n_reg; + wire sig_last_reg_out_reg; + wire sig_m_valid_out_reg; + wire sig_need_cmd_flush; + wire sig_s_ready_dup4_reg; + wire sig_sm_ld_dre_cmd; + wire sig_sm_pop_cmd_fifo; + wire sig_strm_tlast; + wire [3:3]sig_tstrb_fifo_data_out; + wire sig_wr_fifo; + wire slice_insert_valid; - Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f CNTR_INCR_DECR_ADDN_F_I - (.D(D[7:4]), - .E(E), - .FIFO_Full_reg(FIFO_Full_reg_n_0), - .FIFO_Full_reg_0(FIFO_Full_reg_0), - .Q({CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3}), + Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f__parameterized2 CNTR_INCR_DECR_ADDN_F_I + (.E(E), + .FIFO_Full_reg(\INFERRED_GEN.cnt_i_reg[1] ), + .\GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg (\GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg ), + .\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1] (\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[0] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ), + .\INCLUDE_PACKING.lsig_first_dbeat_reg (\INCLUDE_PACKING.lsig_first_dbeat_reg ), + .\INCLUDE_PACKING.lsig_first_dbeat_reg_0 (\INCLUDE_PACKING.lsig_first_dbeat_reg_0 ), + .Q({Q,CNTR_INCR_DECR_ADDN_F_I_n_9,CNTR_INCR_DECR_ADDN_F_I_n_10,CNTR_INCR_DECR_ADDN_F_I_n_11,CNTR_INCR_DECR_ADDN_F_I_n_12}), .SR(SR), + .SS(SS), .fifo_full_p1(fifo_full_p1), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axi_mm2s_rlast(m_axi_mm2s_rlast), - .m_axi_mm2s_rvalid(m_axi_mm2s_rvalid), - .ram_full_i_reg(ram_full_i_reg), - .sig_addr_posted_cntr(sig_addr_posted_cntr), - .sig_advance_pipe9_out__1(sig_advance_pipe9_out__1), - .sig_cmd2data_valid_reg(sel), + .lsig_absorb2tlast(lsig_absorb2tlast), + .lsig_cmd_fetch_pause(lsig_cmd_fetch_pause), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out), + .p_7_out(p_7_out), + .\sig_byte_cntr_reg[0] (\sig_byte_cntr_reg[0] ), + .\sig_byte_cntr_reg[7] (\sig_byte_cntr_reg[7] ), + .sig_clr_dbc_reg(sig_clr_dbc_reg), + .sig_cmd_empty_reg(sig_cmd_empty_reg), + .sig_cmd_full(sig_cmd_full), + .sig_cmd_full_reg(sig_cmd_full_reg), .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .\sig_dbeat_cntr_reg[2] (\sig_dbeat_cntr_reg[2] ), - .\sig_dbeat_cntr_reg[3] (\sig_dbeat_cntr_reg[3] ), - .\sig_dbeat_cntr_reg[4] (\sig_dbeat_cntr_reg[4] ), - .\sig_dbeat_cntr_reg[7] (Q), - .sig_dqual_reg_empty(sig_dqual_reg_empty), - .sig_dqual_reg_empty_reg(sig_dqual_reg_empty_reg), - .sig_dqual_reg_empty_reg_0(sig_dqual_reg_empty_reg_0), - .sig_dqual_reg_full(sig_dqual_reg_full), - .sig_halt_reg_reg(sig_halt_reg_reg), - .sig_inhibit_rdy_n(sig_inhibit_rdy_n), - .sig_inhibit_rdy_n_0(sig_inhibit_rdy_n_0), - .sig_last_dbeat(sig_last_dbeat), - .sig_ld_new_cmd_reg(sig_ld_new_cmd_reg), - .sig_ld_new_cmd_reg_reg(sig_ld_new_cmd_reg_reg), - .sig_mstr2data_cmd_valid(sig_mstr2data_cmd_valid), - .sig_next_calc_error_reg(sig_next_calc_error_reg), - .sig_next_cmd_cmplt_reg_reg(sig_next_cmd_cmplt_reg_reg), - .sig_next_sequential_reg(sig_next_sequential_reg), - .sig_rsc2stat_status_valid(sig_rsc2stat_status_valid)); - Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized2 DYNSHREG_F_I - (.D(D[3:0]), - .FIFO_Full_reg(FIFO_Full_reg_n_0), - .\INFERRED_GEN.cnt_i_reg[1] ({CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3}), - .Q(Q[3:0]), + .sig_dre2ibtt_tlast(sig_dre2ibtt_tlast), + .sig_eop_halt_xfer(sig_eop_halt_xfer), + .sig_eop_sent(sig_eop_sent), + .sig_eop_sent_reg(sig_eop_sent_reg), + .sig_good_tlast_dbeat37_out__0(sig_good_tlast_dbeat37_out__0), + .sig_ibtt2dre_tready(sig_ibtt2dre_tready), + .sig_inhibit_rdy_n_reg(sig_inhibit_rdy_n_reg), + .sig_last_reg_out_reg(sig_last_reg_out_reg), + .sig_m_valid_out_reg(sig_m_valid_out_reg), + .sig_need_cmd_flush(sig_need_cmd_flush), + .sig_s_ready_dup4_reg(sig_s_ready_dup4_reg), + .sig_sm_ld_dre_cmd(sig_sm_ld_dre_cmd), + .sig_sm_pop_cmd_fifo(sig_sm_pop_cmd_fifo), + .sig_strm_tlast(sig_strm_tlast), + .sig_wr_fifo(sig_wr_fifo), + .slice_insert_valid(slice_insert_valid), + .\storage_data_reg[3] ({sig_tstrb_fifo_data_out,\GEN_INDET_BTT.lsig_absorb2tlast_reg })); + Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized8 DYNSHREG_F_I + (.\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] (\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] (\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] (\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] (\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] (\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] (\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] (\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0 ), + .\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] (\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1] ), + .\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 (\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0 ), + .Q({Q,CNTR_INCR_DECR_ADDN_F_I_n_9,CNTR_INCR_DECR_ADDN_F_I_n_10,CNTR_INCR_DECR_ADDN_F_I_n_11,CNTR_INCR_DECR_ADDN_F_I_n_12}), .in(in), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .out(out), - .sig_dbeat_cntr_eq_1(sig_dbeat_cntr_eq_1), - .\sig_dbeat_cntr_reg[2] (\sig_dbeat_cntr_reg[2] ), - .sig_halt_reg_reg(sig_dqual_reg_empty_reg_0), - .sig_inhibit_rdy_n_0(sig_inhibit_rdy_n_0), - .sig_last_dbeat(sig_last_dbeat), - .sig_last_dbeat_reg(sig_last_dbeat_reg), - .sig_mstr2data_cmd_valid(sig_mstr2data_cmd_valid), - .sig_next_calc_error_reg_reg(sel), - .sig_next_sequential_reg_reg(sig_dqual_reg_empty_reg)); + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out({sig_tstrb_fifo_data_out,\GEN_INDET_BTT.lsig_absorb2tlast_reg }), + .p_0_in(p_0_in), + .sel(sig_wr_fifo), + .sig_eop_halt_xfer(sig_eop_halt_xfer), + .sig_m_valid_out_reg(sig_m_valid_out_reg), + .sig_strm_tlast(sig_strm_tlast)); FDRE FIFO_Full_reg - (.C(m_axi_mm2s_aclk), + (.C(m_axi_s2mm_aclk), .CE(1'b1), .D(fifo_full_p1), - .Q(FIFO_Full_reg_n_0), - .R(SR)); + .Q(\INFERRED_GEN.cnt_i_reg[1] ), + .R(SS)); endmodule (* ORIG_REF_NAME = "srl_fifo_rbu_f" *) -module Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized3 - (p_0_out, - FIFO_Full_reg_0, - \INFERRED_GEN.cnt_i_reg[1] , - Q, - in, - m_axi_mm2s_aclk, +module Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized9 + (\INFERRED_GEN.cnt_i_reg[0] , + p_0_in, + out, + sig_calc_error_reg_reg, + sig_clr_cmd2addr_valid3_out__0, sig_stream_rst, - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram , - sig_mstr2sf_cmd_valid, - sig_inhibit_rdy_n_reg); - output [0:0]p_0_out; - output FIFO_Full_reg_0; - output \INFERRED_GEN.cnt_i_reg[1] ; - output [0:0]Q; - input [0:0]in; - input m_axi_mm2s_aclk; + m_axi_s2mm_aclk, + sig_halt_reg, + sig_addr_reg_empty_reg, + p_22_out, + sig_inhibit_rdy_n_reg, + in); + output \INFERRED_GEN.cnt_i_reg[0] ; + output p_0_in; + output [41:0]out; + output sig_calc_error_reg_reg; + output sig_clr_cmd2addr_valid3_out__0; input sig_stream_rst; - input \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; - input sig_mstr2sf_cmd_valid; + input m_axi_s2mm_aclk; + input sig_halt_reg; + input sig_addr_reg_empty_reg; + input p_22_out; input sig_inhibit_rdy_n_reg; + input [39:0]in; wire CNTR_INCR_DECR_ADDN_F_I_n_2; wire CNTR_INCR_DECR_ADDN_F_I_n_3; - wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; - wire FIFO_Full_reg_0; - wire \INFERRED_GEN.cnt_i_reg[1] ; - wire [0:0]Q; + wire \INFERRED_GEN.cnt_i_reg[0] ; wire fifo_full_p1; - wire [0:0]in; - wire m_axi_mm2s_aclk; - wire [0:0]p_0_out; + wire [39:0]in; + wire m_axi_s2mm_aclk; + wire [41:0]out; + wire p_0_in; + wire p_22_out; + wire sig_addr_reg_empty_reg; + wire sig_calc_error_reg_reg; + wire sig_clr_cmd2addr_valid3_out__0; + wire sig_halt_reg; wire sig_inhibit_rdy_n_reg; - wire sig_mstr2sf_cmd_valid; wire sig_stream_rst; + wire sig_wr_fifo; - Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_6 CNTR_INCR_DECR_ADDN_F_I - (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ), - .FIFO_Full_reg(FIFO_Full_reg_0), - .FIFO_Full_reg_0(\INFERRED_GEN.cnt_i_reg[1] ), - .Q({Q,CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3}), + Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_18 CNTR_INCR_DECR_ADDN_F_I + (.FIFO_Full_reg(\INFERRED_GEN.cnt_i_reg[0] ), + .Q({CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3}), .fifo_full_p1(fifo_full_p1), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .p_22_out(p_22_out), + .sig_addr_reg_empty_reg(sig_addr_reg_empty_reg), + .sig_calc_error_reg_reg(sig_calc_error_reg_reg), + .sig_halt_reg(sig_halt_reg), .sig_inhibit_rdy_n_reg(sig_inhibit_rdy_n_reg), - .sig_mstr2sf_cmd_valid(sig_mstr2sf_cmd_valid), - .sig_stream_rst(sig_stream_rst)); - Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized3 DYNSHREG_F_I - (.Q({CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3}), + .sig_stream_rst(sig_stream_rst), + .sig_wr_fifo(sig_wr_fifo)); + Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized9 DYNSHREG_F_I + (.FIFO_Full_reg(\INFERRED_GEN.cnt_i_reg[0] ), + .Q({CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3}), .in(in), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .p_0_out(p_0_out), - .sig_cmd2dre_valid_reg(FIFO_Full_reg_0)); + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out), + .p_0_in(p_0_in), + .p_22_out(p_22_out), + .sig_inhibit_rdy_n_reg(sig_inhibit_rdy_n_reg), + .sig_wr_fifo(sig_wr_fifo)); FDRE FIFO_Full_reg - (.C(m_axi_mm2s_aclk), + (.C(m_axi_s2mm_aclk), .CE(1'b1), .D(fifo_full_p1), - .Q(\INFERRED_GEN.cnt_i_reg[1] ), + .Q(\INFERRED_GEN.cnt_i_reg[0] ), .R(sig_stream_rst)); + LUT3 #( + .INIT(8'h40)) + \sig_xfer_addr_reg[31]_i_2 + (.I0(\INFERRED_GEN.cnt_i_reg[0] ), + .I1(sig_inhibit_rdy_n_reg), + .I2(p_22_out), + .O(sig_clr_cmd2addr_valid3_out__0)); endmodule (* ORIG_REF_NAME = "sync_fifo_fg" *) module Arty_Z7_20_axi_vdma_0_0_sync_fifo_fg - (out, - \sig_user_skid_reg_reg[0] , - dm2linebuf_mm2s_tvalid, - DI, - Q, - dm2linebuf_mm2s_tdata, - hold_ff_q_reg, + (DOBDO, + out, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram , sig_ok_to_post_rd_addr_reg, - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , \INCLUDE_UNPACKING.lsig_cmd_loaded_reg , - \INFERRED_GEN.cnt_i_reg[0] , - S, - \count_reg[6] , + hold_ff_q_reg, + \gc1.count_reg[7] , + \INFERRED_GEN.cnt_i_reg[2] , + DIN, + \sig_user_skid_reg_reg[0] , + dm2linebuf_mm2s_tdata, m_axi_mm2s_aclk, - sig_stream_rst, + E, + SR, m_axi_mm2s_rdata, DIBDI, - lsig_0ffset_cntr, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_posted_to_axi_2_reg, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , + Q, lsig_cmd_loaded, hold_ff_q, + ram_full_i_reg, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 , + \sig_token_cntr_reg[0] , \sig_token_cntr_reg[3] , - p_8_out, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_posted_to_axi_2_reg, - sig_posted_to_axi_2_reg_0, - p_0_out, - \INFERRED_GEN.cnt_i_reg[2] , - fifo_wren__0, - mm2s_strm_wvalid0__1, - m_axi_mm2s_rvalid, - sig_advance_pipe9_out__1, - D); + ram_full_i_reg_0); + output [0:0]DOBDO; output out; - output [0:0]\sig_user_skid_reg_reg[0] ; - output dm2linebuf_mm2s_tvalid; - output [3:0]DI; - output [1:0]Q; - output [31:0]dm2linebuf_mm2s_tdata; - output hold_ff_q_reg; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; output sig_ok_to_post_rd_addr_reg; - output \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; output \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; - output \INFERRED_GEN.cnt_i_reg[0] ; - output [3:0]S; - output [1:0]\count_reg[6] ; + output hold_ff_q_reg; + output \gc1.count_reg[7] ; + output \INFERRED_GEN.cnt_i_reg[2] ; + output [0:0]DIN; + output \sig_user_skid_reg_reg[0] ; + output [31:0]dm2linebuf_mm2s_tdata; input m_axi_mm2s_aclk; - input sig_stream_rst; + input [0:0]E; + input [0:0]SR; input [63:0]m_axi_mm2s_rdata; input [1:0]DIBDI; - input lsig_0ffset_cntr; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_posted_to_axi_2_reg; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + input [0:0]Q; input lsig_cmd_loaded; input hold_ff_q; + input ram_full_i_reg; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; + input \sig_token_cntr_reg[0] ; input [3:0]\sig_token_cntr_reg[3] ; - input p_8_out; - input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - input sig_posted_to_axi_2_reg; - input sig_posted_to_axi_2_reg_0; - input [0:0]p_0_out; - input [0:0]\INFERRED_GEN.cnt_i_reg[2] ; - input fifo_wren__0; - input mm2s_strm_wvalid0__1; - input m_axi_mm2s_rvalid; - input sig_advance_pipe9_out__1; - input [5:0]D; + input [0:0]ram_full_i_reg_0; - wire [5:0]D; - wire [3:0]DI; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; wire [1:0]DIBDI; + wire [0:0]DIN; + wire [0:0]DOBDO; + wire [0:0]E; wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; wire \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; - wire \INFERRED_GEN.cnt_i_reg[0] ; - wire [0:0]\INFERRED_GEN.cnt_i_reg[2] ; - wire [1:0]Q; - wire [3:0]S; - wire [1:0]\count_reg[6] ; + wire \INFERRED_GEN.cnt_i_reg[2] ; + wire [0:0]Q; + wire [0:0]SR; wire [31:0]dm2linebuf_mm2s_tdata; - wire dm2linebuf_mm2s_tvalid; - wire fifo_wren__0; + wire \gc1.count_reg[7] ; wire hold_ff_q; wire hold_ff_q_reg; - wire lsig_0ffset_cntr; wire lsig_cmd_loaded; wire m_axi_mm2s_aclk; wire [63:0]m_axi_mm2s_rdata; - wire m_axi_mm2s_rvalid; - wire mm2s_strm_wvalid0__1; wire out; - wire [0:0]p_0_out; - wire p_8_out; - wire sig_advance_pipe9_out__1; + wire ram_full_i_reg; + wire [0:0]ram_full_i_reg_0; wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; wire sig_ok_to_post_rd_addr_reg; wire sig_posted_to_axi_2_reg; - wire sig_posted_to_axi_2_reg_0; - wire sig_stream_rst; + wire \sig_token_cntr_reg[0] ; wire [3:0]\sig_token_cntr_reg[3] ; - wire [0:0]\sig_user_skid_reg_reg[0] ; + wire \sig_user_skid_reg_reg[0] ; - Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized0 \FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM - (.D(D), - .DI(DI), + Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized1 \FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM + (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ), .DIBDI(DIBDI), + .DIN(DIN), + .DOBDO(DOBDO), + .E(E), .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), .\INCLUDE_UNPACKING.lsig_cmd_loaded_reg (\INCLUDE_UNPACKING.lsig_cmd_loaded_reg ), - .\INFERRED_GEN.cnt_i_reg[0] (\INFERRED_GEN.cnt_i_reg[0] ), .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ), .Q(Q), - .S(S), - .\count_reg[6] (\count_reg[6] ), + .SR(SR), .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), - .dm2linebuf_mm2s_tvalid(dm2linebuf_mm2s_tvalid), - .fifo_wren__0(fifo_wren__0), + .\gc1.count_reg[7] (\gc1.count_reg[7] ), .hold_ff_q(hold_ff_q), .hold_ff_q_reg(hold_ff_q_reg), - .lsig_0ffset_cntr(lsig_0ffset_cntr), .lsig_cmd_loaded(lsig_cmd_loaded), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), .m_axi_mm2s_rdata(m_axi_mm2s_rdata), - .m_axi_mm2s_rvalid(m_axi_mm2s_rvalid), - .mm2s_strm_wvalid0__1(mm2s_strm_wvalid0__1), .out(out), - .p_0_out(p_0_out), - .p_8_out(p_8_out), - .sig_advance_pipe9_out__1(sig_advance_pipe9_out__1), - .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .sig_ok_to_post_rd_addr_reg(sig_ok_to_post_rd_addr_reg), - .sig_posted_to_axi_2_reg(sig_posted_to_axi_2_reg), - .sig_posted_to_axi_2_reg_0(sig_posted_to_axi_2_reg_0), - .sig_stream_rst(sig_stream_rst), - .\sig_token_cntr_reg[3] (\sig_token_cntr_reg[3] ), - .\sig_user_skid_reg_reg[0] (\sig_user_skid_reg_reg[0] )); + .ram_full_i_reg(ram_full_i_reg), + .ram_full_i_reg_0(ram_full_i_reg_0), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_ok_to_post_rd_addr_reg(sig_ok_to_post_rd_addr_reg), + .sig_posted_to_axi_2_reg(sig_posted_to_axi_2_reg), + .\sig_token_cntr_reg[0] (\sig_token_cntr_reg[0] ), + .\sig_token_cntr_reg[3] (\sig_token_cntr_reg[3] ), + .\sig_user_skid_reg_reg[0] (\sig_user_skid_reg_reg[0] )); +endmodule + +(* ORIG_REF_NAME = "sync_fifo_fg" *) +module Arty_Z7_20_axi_vdma_0_0_sync_fifo_fg__parameterized0 + (hold_ff_q_reg, + D, + sig_xfer_is_seq_reg_reg, + \sig_child_addr_cntr_lsh_reg[11] , + E, + S, + \sig_xfer_len_reg_reg[4] , + \sig_xfer_len_reg_reg[5] , + sig_xfer_is_seq_reg_reg_0, + sig_xfer_cmd_cmplt_reg0, + sig_sf2pcc_xfer_valid, + sig_ibtt2dre_tready, + sig_csm_state_ns1, + \gpr1.dout_i_reg[1] , + \gpr1.dout_i_reg[1]_0 , + O, + CO, + \sig_child_addr_cntr_lsh_reg[7] , + sig_stream_rst, + m_axi_s2mm_aclk, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + p_32_out, + hold_ff_q, + sig_adjusted_addr_incr, + sig_clr_dbc_reg_reg, + sig_csm_pop_child_cmd, + sig_child_qual_first_of_2, + sig_child_qual_error_reg, + lsig_packer_full, + ram_full_i_reg, + \gpr1.dout_i_reg[3] , + \gpr1.dout_i_reg[7] , + sig_child_addr_cntr_lsh_reg, + p_0_out); + output hold_ff_q_reg; + output [2:0]D; + output [9:0]sig_xfer_is_seq_reg_reg; + output [0:0]\sig_child_addr_cntr_lsh_reg[11] ; + output [0:0]E; + output [3:0]S; + output [3:0]\sig_xfer_len_reg_reg[4] ; + output [0:0]\sig_xfer_len_reg_reg[5] ; + output sig_xfer_is_seq_reg_reg_0; + output sig_xfer_cmd_cmplt_reg0; + output sig_sf2pcc_xfer_valid; + output sig_ibtt2dre_tready; + output sig_csm_state_ns1; + output [2:0]\gpr1.dout_i_reg[1] ; + output [2:0]\gpr1.dout_i_reg[1]_0 ; + output [3:0]O; + output [0:0]CO; + output [3:0]\sig_child_addr_cntr_lsh_reg[7] ; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input p_32_out; + input hold_ff_q; + input [8:0]sig_adjusted_addr_incr; + input sig_clr_dbc_reg_reg; + input sig_csm_pop_child_cmd; + input sig_child_qual_first_of_2; + input sig_child_qual_error_reg; + input lsig_packer_full; + input ram_full_i_reg; + input [3:0]\gpr1.dout_i_reg[3] ; + input [3:0]\gpr1.dout_i_reg[7] ; + input [2:0]sig_child_addr_cntr_lsh_reg; + input [10:0]p_0_out; + + wire [0:0]CO; + wire [2:0]D; + wire [0:0]E; + wire [3:0]O; + wire [3:0]S; + wire [2:0]\gpr1.dout_i_reg[1] ; + wire [2:0]\gpr1.dout_i_reg[1]_0 ; + wire [3:0]\gpr1.dout_i_reg[3] ; + wire [3:0]\gpr1.dout_i_reg[7] ; + wire hold_ff_q; + wire hold_ff_q_reg; + wire lsig_packer_full; + wire m_axi_s2mm_aclk; + wire [10:0]p_0_out; + wire p_32_out; + wire ram_full_i_reg; + wire [8:0]sig_adjusted_addr_incr; + wire [2:0]sig_child_addr_cntr_lsh_reg; + wire [0:0]\sig_child_addr_cntr_lsh_reg[11] ; + wire [3:0]\sig_child_addr_cntr_lsh_reg[7] ; + wire sig_child_qual_error_reg; + wire sig_child_qual_first_of_2; + wire sig_clr_dbc_reg_reg; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_csm_pop_child_cmd; + wire sig_csm_state_ns1; + wire sig_ibtt2dre_tready; + wire sig_sf2pcc_xfer_valid; + wire sig_stream_rst; + wire sig_xfer_cmd_cmplt_reg0; + wire [9:0]sig_xfer_is_seq_reg_reg; + wire sig_xfer_is_seq_reg_reg_0; + wire [3:0]\sig_xfer_len_reg_reg[4] ; + wire [0:0]\sig_xfer_len_reg_reg[5] ; + + Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized2 \FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM + (.CO(CO), + .D(D), + .E(E), + .O(O), + .S(S), + .\gpr1.dout_i_reg[1] (\gpr1.dout_i_reg[1] ), + .\gpr1.dout_i_reg[1]_0 (\gpr1.dout_i_reg[1]_0 ), + .\gpr1.dout_i_reg[3] (\gpr1.dout_i_reg[3] ), + .\gpr1.dout_i_reg[7] (\gpr1.dout_i_reg[7] ), + .hold_ff_q(hold_ff_q), + .hold_ff_q_reg(hold_ff_q_reg), + .lsig_packer_full(lsig_packer_full), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .p_0_out(p_0_out), + .p_32_out(p_32_out), + .ram_full_i_reg(ram_full_i_reg), + .sig_adjusted_addr_incr(sig_adjusted_addr_incr), + .sig_child_addr_cntr_lsh_reg(sig_child_addr_cntr_lsh_reg), + .\sig_child_addr_cntr_lsh_reg[11] (\sig_child_addr_cntr_lsh_reg[11] ), + .\sig_child_addr_cntr_lsh_reg[7] (\sig_child_addr_cntr_lsh_reg[7] ), + .sig_child_qual_error_reg(sig_child_qual_error_reg), + .sig_child_qual_first_of_2(sig_child_qual_first_of_2), + .sig_clr_dbc_reg_reg(sig_clr_dbc_reg_reg), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_csm_pop_child_cmd(sig_csm_pop_child_cmd), + .sig_csm_state_ns1(sig_csm_state_ns1), + .sig_ibtt2dre_tready(sig_ibtt2dre_tready), + .sig_sf2pcc_xfer_valid(sig_sf2pcc_xfer_valid), + .sig_stream_rst(sig_stream_rst), + .sig_xfer_cmd_cmplt_reg0(sig_xfer_cmd_cmplt_reg0), + .sig_xfer_is_seq_reg_reg(sig_xfer_is_seq_reg_reg), + .sig_xfer_is_seq_reg_reg_0(sig_xfer_is_seq_reg_reg_0), + .\sig_xfer_len_reg_reg[4] (\sig_xfer_len_reg_reg[4] ), + .\sig_xfer_len_reg_reg[5] (\sig_xfer_len_reg_reg[5] )); +endmodule + +(* ORIG_REF_NAME = "sync_fifo_fg" *) +module Arty_Z7_20_axi_vdma_0_0_sync_fifo_fg__parameterized1 + (sig_data_fifo_data_out, + out, + \gcc0.gc0.count_d1_reg[7] , + hold_ff_q_reg, + \INCLUDE_PACKING.lsig_packer_full_reg , + E, + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] , + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] , + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] , + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] , + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] , + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] , + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] , + sig_data_fifo_dvalid, + m_axi_s2mm_aclk, + sig_stream_rst, + lsig_combined_data, + DIBDI, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + hold_ff_q_reg_0, + sig_s_ready_out_reg, + lsig_set_packer_full__1, + lsig_packer_full, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ); + output [65:0]sig_data_fifo_data_out; + output out; + output \gcc0.gc0.count_d1_reg[7] ; + output hold_ff_q_reg; + output \INCLUDE_PACKING.lsig_packer_full_reg ; + output [0:0]E; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] ; + output sig_data_fifo_dvalid; + input m_axi_s2mm_aclk; + input sig_stream_rst; + input [63:0]lsig_combined_data; + input [1:0]DIBDI; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input hold_ff_q_reg_0; + input sig_s_ready_out_reg; + input lsig_set_packer_full__1; + input lsig_packer_full; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ; + + wire [1:0]DIBDI; + wire [0:0]E; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ; + wire \INCLUDE_PACKING.lsig_packer_full_reg ; + wire \gcc0.gc0.count_d1_reg[7] ; + wire hold_ff_q_reg; + wire hold_ff_q_reg_0; + wire [63:0]lsig_combined_data; + wire lsig_packer_full; + wire lsig_set_packer_full__1; + wire m_axi_s2mm_aclk; + wire out; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire [65:0]sig_data_fifo_data_out; + wire sig_data_fifo_dvalid; + wire sig_s_ready_out_reg; + wire sig_stream_rst; + + Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized3 \FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM + (.DIBDI(DIBDI), + .E(E), + .\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] (\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] (\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] (\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] (\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] (\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] (\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] (\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ), + .\INCLUDE_PACKING.lsig_packer_full_reg (\INCLUDE_PACKING.lsig_packer_full_reg ), + .\gcc0.gc0.count_d1_reg[7] (\gcc0.gc0.count_d1_reg[7] ), + .hold_ff_q_reg(hold_ff_q_reg), + .hold_ff_q_reg_0(hold_ff_q_reg_0), + .lsig_combined_data(lsig_combined_data), + .lsig_packer_full(lsig_packer_full), + .lsig_set_packer_full__1(lsig_set_packer_full__1), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_data_fifo_data_out(sig_data_fifo_data_out), + .sig_data_fifo_dvalid(sig_data_fifo_dvalid), + .sig_s_ready_out_reg(sig_s_ready_out_reg), + .sig_stream_rst(sig_stream_rst)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *) +module Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_generic_cstr + (DOBDO, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg , + \INFERRED_GEN.cnt_i_reg[2] , + DIN, + dm2linebuf_mm2s_tdata, + m_axi_mm2s_aclk, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0, + E, + \gpregsm1.curr_fwft_state_reg[0] , + SR, + \gc1.count_d2_reg[7] , + \gcc0.gc0.count_d1_reg[7] , + m_axi_mm2s_rdata, + DIBDI, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , + Q, + lsig_cmd_loaded, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 , + hold_ff_q, + out); + output [0:0]DOBDO; + output \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + output \INFERRED_GEN.cnt_i_reg[2] ; + output [0:0]DIN; + output [31:0]dm2linebuf_mm2s_tdata; + input m_axi_mm2s_aclk; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0; + input [0:0]E; + input \gpregsm1.curr_fwft_state_reg[0] ; + input [0:0]SR; + input [7:0]\gc1.count_d2_reg[7] ; + input [7:0]\gcc0.gc0.count_d1_reg[7] ; + input [63:0]m_axi_mm2s_rdata; + input [1:0]DIBDI; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + input [0:0]Q; + input lsig_cmd_loaded; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; + input hold_ff_q; + input out; + + wire [1:0]DIBDI; + wire [0:0]DIN; + wire [0:0]DOBDO; + wire [0:0]E; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; + wire \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + wire \INFERRED_GEN.cnt_i_reg[2] ; + wire [0:0]Q; + wire [0:0]SR; + wire [31:0]dm2linebuf_mm2s_tdata; + wire [7:0]\gc1.count_d2_reg[7] ; + wire [7:0]\gcc0.gc0.count_d1_reg[7] ; + wire \gpregsm1.curr_fwft_state_reg[0] ; + wire hold_ff_q; + wire lsig_cmd_loaded; + wire m_axi_mm2s_aclk; + wire [63:0]m_axi_mm2s_rdata; + wire out; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0; + + Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_width \ramloop[0].ram.r + (.DIBDI(DIBDI), + .DIN(DIN), + .DOBDO(DOBDO), + .E(E), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .\INCLUDE_UNPACKING.lsig_cmd_loaded_reg (\INCLUDE_UNPACKING.lsig_cmd_loaded_reg ), + .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ), + .Q(Q), + .SR(SR), + .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), + .\gc1.count_d2_reg[7] (\gc1.count_d2_reg[7] ), + .\gcc0.gc0.count_d1_reg[7] (\gcc0.gc0.count_d1_reg[7] ), + .\gpregsm1.curr_fwft_state_reg[0] (\gpregsm1.curr_fwft_state_reg[0] ), + .hold_ff_q(hold_ff_q), + .lsig_cmd_loaded(lsig_cmd_loaded), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .m_axi_mm2s_rdata(m_axi_mm2s_rdata), + .out(out), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0(sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *) -module Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_generic_cstr +module Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_generic_cstr__parameterized0 + (sig_data_fifo_data_out, + m_axi_s2mm_aclk, + ram_empty_fb_i_reg, + WEBWE, + sig_s_ready_out_reg, + sig_stream_rst, + \gc1.count_d2_reg[7] , + Q, + lsig_combined_data, + DIBDI); + output [65:0]sig_data_fifo_data_out; + input m_axi_s2mm_aclk; + input ram_empty_fb_i_reg; + input [0:0]WEBWE; + input sig_s_ready_out_reg; + input sig_stream_rst; + input [7:0]\gc1.count_d2_reg[7] ; + input [7:0]Q; + input [63:0]lsig_combined_data; + input [1:0]DIBDI; + + wire [1:0]DIBDI; + wire [7:0]Q; + wire [0:0]WEBWE; + wire [7:0]\gc1.count_d2_reg[7] ; + wire [63:0]lsig_combined_data; + wire m_axi_s2mm_aclk; + wire ram_empty_fb_i_reg; + wire [65:0]sig_data_fifo_data_out; + wire sig_s_ready_out_reg; + wire sig_stream_rst; + + Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_width__parameterized0 \ramloop[0].ram.r + (.DIBDI(DIBDI), + .Q(Q), + .WEBWE(WEBWE), + .\gc1.count_d2_reg[7] (\gc1.count_d2_reg[7] ), + .lsig_combined_data(lsig_combined_data), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .sig_data_fifo_data_out(sig_data_fifo_data_out), + .sig_s_ready_out_reg(sig_s_ready_out_reg), + .sig_stream_rst(sig_stream_rst)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_width (DOBDO, - \sig_user_skid_reg_reg[0] , + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg , + \INFERRED_GEN.cnt_i_reg[2] , + DIN, dm2linebuf_mm2s_tdata, - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , - \INFERRED_GEN.cnt_i_reg[0] , m_axi_mm2s_aclk, - ram_empty_fb_i_reg, - ram_full_i_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0, + E, \gpregsm1.curr_fwft_state_reg[0] , - sig_stream_rst, - \gc1.count_d2_reg[6] , - Q, + SR, + \gc1.count_d2_reg[7] , + \gcc0.gc0.count_d1_reg[7] , m_axi_mm2s_rdata, DIBDI, - lsig_0ffset_cntr, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , + Q, lsig_cmd_loaded, - \gpregsm1.user_valid_reg , + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 , hold_ff_q, - p_0_out, - dm2linebuf_mm2s_tvalid, - p_8_out, - fifo_wren__0, - \INFERRED_GEN.cnt_i_reg[2] ); + out); output [0:0]DOBDO; - output [0:0]\sig_user_skid_reg_reg[0] ; + output \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + output \INFERRED_GEN.cnt_i_reg[2] ; + output [0:0]DIN; output [31:0]dm2linebuf_mm2s_tdata; - output \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; - output \INFERRED_GEN.cnt_i_reg[0] ; input m_axi_mm2s_aclk; - input ram_empty_fb_i_reg; - input ram_full_i_reg; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0; + input [0:0]E; input \gpregsm1.curr_fwft_state_reg[0] ; - input sig_stream_rst; - input [6:0]\gc1.count_d2_reg[6] ; - input [6:0]Q; + input [0:0]SR; + input [7:0]\gc1.count_d2_reg[7] ; + input [7:0]\gcc0.gc0.count_d1_reg[7] ; input [63:0]m_axi_mm2s_rdata; input [1:0]DIBDI; - input lsig_0ffset_cntr; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + input [0:0]Q; input lsig_cmd_loaded; - input \gpregsm1.user_valid_reg ; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; input hold_ff_q; - input [0:0]p_0_out; - input dm2linebuf_mm2s_tvalid; - input p_8_out; - input fifo_wren__0; - input [0:0]\INFERRED_GEN.cnt_i_reg[2] ; + input out; wire [1:0]DIBDI; + wire [0:0]DIN; wire [0:0]DOBDO; + wire [0:0]E; wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; - wire \INFERRED_GEN.cnt_i_reg[0] ; - wire [0:0]\INFERRED_GEN.cnt_i_reg[2] ; - wire [6:0]Q; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; + wire \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + wire \INFERRED_GEN.cnt_i_reg[2] ; + wire [0:0]Q; + wire [0:0]SR; wire [31:0]dm2linebuf_mm2s_tdata; - wire dm2linebuf_mm2s_tvalid; - wire fifo_wren__0; - wire [6:0]\gc1.count_d2_reg[6] ; + wire [7:0]\gc1.count_d2_reg[7] ; + wire [7:0]\gcc0.gc0.count_d1_reg[7] ; wire \gpregsm1.curr_fwft_state_reg[0] ; - wire \gpregsm1.user_valid_reg ; wire hold_ff_q; - wire lsig_0ffset_cntr; wire lsig_cmd_loaded; wire m_axi_mm2s_aclk; wire [63:0]m_axi_mm2s_rdata; - wire [0:0]p_0_out; - wire p_8_out; - wire ram_empty_fb_i_reg; - wire ram_full_i_reg; - wire sig_stream_rst; - wire [0:0]\sig_user_skid_reg_reg[0] ; + wire out; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0; - Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_width \ramloop[0].ram.r + Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_wrapper \prim_noinit.ram (.DIBDI(DIBDI), + .DIN(DIN), .DOBDO(DOBDO), + .E(E), .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), - .\INFERRED_GEN.cnt_i_reg[0] (\INFERRED_GEN.cnt_i_reg[0] ), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .\INCLUDE_UNPACKING.lsig_cmd_loaded_reg (\INCLUDE_UNPACKING.lsig_cmd_loaded_reg ), .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ), .Q(Q), + .SR(SR), .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), - .dm2linebuf_mm2s_tvalid(dm2linebuf_mm2s_tvalid), - .fifo_wren__0(fifo_wren__0), - .\gc1.count_d2_reg[6] (\gc1.count_d2_reg[6] ), + .\gc1.count_d2_reg[7] (\gc1.count_d2_reg[7] ), + .\gcc0.gc0.count_d1_reg[7] (\gcc0.gc0.count_d1_reg[7] ), .\gpregsm1.curr_fwft_state_reg[0] (\gpregsm1.curr_fwft_state_reg[0] ), - .\gpregsm1.user_valid_reg (\gpregsm1.user_valid_reg ), .hold_ff_q(hold_ff_q), - .lsig_0ffset_cntr(lsig_0ffset_cntr), .lsig_cmd_loaded(lsig_cmd_loaded), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), .m_axi_mm2s_rdata(m_axi_mm2s_rdata), - .p_0_out(p_0_out), - .p_8_out(p_8_out), - .ram_empty_fb_i_reg(ram_empty_fb_i_reg), - .ram_full_i_reg(ram_full_i_reg), - .sig_stream_rst(sig_stream_rst), - .\sig_user_skid_reg_reg[0] (\sig_user_skid_reg_reg[0] )); + .out(out), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0(sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) -module Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_width +module Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_width__parameterized0 + (sig_data_fifo_data_out, + m_axi_s2mm_aclk, + ram_empty_fb_i_reg, + WEBWE, + sig_s_ready_out_reg, + sig_stream_rst, + \gc1.count_d2_reg[7] , + Q, + lsig_combined_data, + DIBDI); + output [65:0]sig_data_fifo_data_out; + input m_axi_s2mm_aclk; + input ram_empty_fb_i_reg; + input [0:0]WEBWE; + input sig_s_ready_out_reg; + input sig_stream_rst; + input [7:0]\gc1.count_d2_reg[7] ; + input [7:0]Q; + input [63:0]lsig_combined_data; + input [1:0]DIBDI; + + wire [1:0]DIBDI; + wire [7:0]Q; + wire [0:0]WEBWE; + wire [7:0]\gc1.count_d2_reg[7] ; + wire [63:0]lsig_combined_data; + wire m_axi_s2mm_aclk; + wire ram_empty_fb_i_reg; + wire [65:0]sig_data_fifo_data_out; + wire sig_s_ready_out_reg; + wire sig_stream_rst; + + Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram + (.DIBDI(DIBDI), + .Q(Q), + .WEBWE(WEBWE), + .\gc1.count_d2_reg[7] (\gc1.count_d2_reg[7] ), + .lsig_combined_data(lsig_combined_data), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .sig_data_fifo_data_out(sig_data_fifo_data_out), + .sig_s_ready_out_reg(sig_s_ready_out_reg), + .sig_stream_rst(sig_stream_rst)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_wrapper (DOBDO, - \sig_user_skid_reg_reg[0] , + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg , + \INFERRED_GEN.cnt_i_reg[2] , + DIN, dm2linebuf_mm2s_tdata, - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , - \INFERRED_GEN.cnt_i_reg[0] , m_axi_mm2s_aclk, - ram_empty_fb_i_reg, - ram_full_i_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0, + E, \gpregsm1.curr_fwft_state_reg[0] , - sig_stream_rst, - \gc1.count_d2_reg[6] , - Q, + SR, + \gc1.count_d2_reg[7] , + \gcc0.gc0.count_d1_reg[7] , m_axi_mm2s_rdata, DIBDI, - lsig_0ffset_cntr, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , + Q, lsig_cmd_loaded, - \gpregsm1.user_valid_reg , + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 , hold_ff_q, - p_0_out, - dm2linebuf_mm2s_tvalid, - p_8_out, - fifo_wren__0, - \INFERRED_GEN.cnt_i_reg[2] ); + out); output [0:0]DOBDO; - output [0:0]\sig_user_skid_reg_reg[0] ; + output \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + output \INFERRED_GEN.cnt_i_reg[2] ; + output [0:0]DIN; output [31:0]dm2linebuf_mm2s_tdata; - output \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; - output \INFERRED_GEN.cnt_i_reg[0] ; input m_axi_mm2s_aclk; - input ram_empty_fb_i_reg; - input ram_full_i_reg; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0; + input [0:0]E; input \gpregsm1.curr_fwft_state_reg[0] ; - input sig_stream_rst; - input [6:0]\gc1.count_d2_reg[6] ; - input [6:0]Q; + input [0:0]SR; + input [7:0]\gc1.count_d2_reg[7] ; + input [7:0]\gcc0.gc0.count_d1_reg[7] ; input [63:0]m_axi_mm2s_rdata; input [1:0]DIBDI; - input lsig_0ffset_cntr; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + input [0:0]Q; input lsig_cmd_loaded; - input \gpregsm1.user_valid_reg ; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; input hold_ff_q; - input [0:0]p_0_out; - input dm2linebuf_mm2s_tvalid; - input p_8_out; - input fifo_wren__0; - input [0:0]\INFERRED_GEN.cnt_i_reg[2] ; + input out; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_53 ; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85 ; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87 ; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89 ; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90 ; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91 ; wire [1:0]DIBDI; + wire [0:0]DIN; wire [0:0]DOBDO; + wire [0:0]E; wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; - wire \INFERRED_GEN.cnt_i_reg[0] ; - wire [0:0]\INFERRED_GEN.cnt_i_reg[2] ; - wire [6:0]Q; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; + wire \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + wire \INFERRED_GEN.cnt_i_reg[2] ; + wire [0:0]Q; + wire [0:0]SR; wire [31:0]dm2linebuf_mm2s_tdata; - wire dm2linebuf_mm2s_tvalid; - wire fifo_wren__0; - wire [6:0]\gc1.count_d2_reg[6] ; + wire [7:0]\gc1.count_d2_reg[7] ; + wire [7:0]\gcc0.gc0.count_d1_reg[7] ; wire \gpregsm1.curr_fwft_state_reg[0] ; - wire \gpregsm1.user_valid_reg ; wire hold_ff_q; - wire lsig_0ffset_cntr; wire lsig_cmd_loaded; wire m_axi_mm2s_aclk; wire [63:0]m_axi_mm2s_rdata; - wire [0:0]p_0_out; - wire p_8_out; - wire ram_empty_fb_i_reg; - wire ram_full_i_reg; - wire sig_stream_rst; - wire [0:0]\sig_user_skid_reg_reg[0] ; + wire out; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0; + wire [64:0]sig_data_fifo_data_out; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED ; - Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_wrapper \prim_noinit.ram - (.DIBDI(DIBDI), - .DOBDO(DOBDO), - .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), - .\INFERRED_GEN.cnt_i_reg[0] (\INFERRED_GEN.cnt_i_reg[0] ), - .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ), - .Q(Q), - .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), - .dm2linebuf_mm2s_tvalid(dm2linebuf_mm2s_tvalid), - .fifo_wren__0(fifo_wren__0), - .\gc1.count_d2_reg[6] (\gc1.count_d2_reg[6] ), - .\gpregsm1.curr_fwft_state_reg[0] (\gpregsm1.curr_fwft_state_reg[0] ), - .\gpregsm1.user_valid_reg (\gpregsm1.user_valid_reg ), - .hold_ff_q(hold_ff_q), - .lsig_0ffset_cntr(lsig_0ffset_cntr), - .lsig_cmd_loaded(lsig_cmd_loaded), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axi_mm2s_rdata(m_axi_mm2s_rdata), - .p_0_out(p_0_out), - .p_8_out(p_8_out), - .ram_empty_fb_i_reg(ram_empty_fb_i_reg), - .ram_full_i_reg(ram_full_i_reg), - .sig_stream_rst(sig_stream_rst), - .\sig_user_skid_reg_reg[0] (\sig_user_skid_reg_reg[0] )); + (* CLOCK_DOMAINS = "COMMON" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(1), + .DOB_REG(1), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("SDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(72), + .READ_WIDTH_B(0), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("READ_FIRST"), + .WRITE_MODE_B("READ_FIRST"), + .WRITE_WIDTH_A(0), + .WRITE_WIDTH_B(72)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram + (.ADDRARDADDR({1'b1,1'b0,\gc1.count_d2_reg[7] ,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,1'b0,\gcc0.gc0.count_d1_reg[7] ,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(m_axi_mm2s_aclk), + .CLKBWRCLK(m_axi_mm2s_aclk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED ), + .DIADI({m_axi_mm2s_rdata[33:26],m_axi_mm2s_rdata[24:9],m_axi_mm2s_rdata[7:0]}), + .DIBDI({1'b0,DIBDI,m_axi_mm2s_rdata[63:43],m_axi_mm2s_rdata[41:34]}), + .DIPADIP({1'b0,m_axi_mm2s_rdata[25],1'b0,m_axi_mm2s_rdata[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,m_axi_mm2s_rdata[42]}), + .DOADO({sig_data_fifo_data_out[33:26],sig_data_fifo_data_out[24:9],sig_data_fifo_data_out[7:0]}), + .DOBDO({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_53 ,DOBDO,sig_data_fifo_data_out[64:43],sig_data_fifo_data_out[41:34]}), + .DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85 ,sig_data_fifo_data_out[25],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87 ,sig_data_fifo_data_out[8]}), + .DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91 ,sig_data_fifo_data_out[42]}), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0), + .ENBWREN(E), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(\gpregsm1.curr_fwft_state_reg[0] ), + .REGCEB(1'b0), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(SR), + .RSTREGB(1'b0), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED ), + .WEA({1'b0,1'b0,1'b0,1'b0}), + .WEBWE({E,E,E,E,E,E,E,E})); + (* SOFT_HLUTNM = "soft_lutpair108" *) + LUT4 #( + .INIT(16'hBF0F)) + \INCLUDE_UNPACKING.lsig_cmd_loaded_i_1 + (.I0(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), + .I1(DOBDO), + .I2(Q), + .I3(lsig_cmd_loaded), + .O(\INCLUDE_UNPACKING.lsig_cmd_loaded_reg )); + (* SOFT_HLUTNM = "soft_lutpair108" *) + LUT3 #( + .INIT(8'h8A)) + \INFERRED_GEN.cnt_i[2]_i_2__0 + (.I0(lsig_cmd_loaded), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), + .I2(DOBDO), + .O(\INFERRED_GEN.cnt_i_reg[2] )); + LUT5 #( + .INIT(32'h88800000)) + \gf36e1_inst.sngfifo36e1_i_1 + (.I0(sig_data_fifo_data_out[64]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(hold_ff_q), + .I3(out), + .I4(lsig_cmd_loaded), + .O(DIN)); + (* SOFT_HLUTNM = "soft_lutpair113" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_10 + (.I0(sig_data_fifo_data_out[55]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[23]), + .O(dm2linebuf_mm2s_tdata[23])); + (* SOFT_HLUTNM = "soft_lutpair120" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_10__0 + (.I0(sig_data_fifo_data_out[41]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[9]), + .O(dm2linebuf_mm2s_tdata[9])); + (* SOFT_HLUTNM = "soft_lutpair113" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_11 + (.I0(sig_data_fifo_data_out[54]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[22]), + .O(dm2linebuf_mm2s_tdata[22])); + (* SOFT_HLUTNM = "soft_lutpair120" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_11__0 + (.I0(sig_data_fifo_data_out[40]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[8]), + .O(dm2linebuf_mm2s_tdata[8])); + (* SOFT_HLUTNM = "soft_lutpair114" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_12 + (.I0(sig_data_fifo_data_out[53]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[21]), + .O(dm2linebuf_mm2s_tdata[21])); + (* SOFT_HLUTNM = "soft_lutpair121" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_12__0 + (.I0(sig_data_fifo_data_out[39]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[7]), + .O(dm2linebuf_mm2s_tdata[7])); + (* SOFT_HLUTNM = "soft_lutpair114" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_13 + (.I0(sig_data_fifo_data_out[52]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[20]), + .O(dm2linebuf_mm2s_tdata[20])); + (* SOFT_HLUTNM = "soft_lutpair121" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_13__0 + (.I0(sig_data_fifo_data_out[38]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[6]), + .O(dm2linebuf_mm2s_tdata[6])); + (* SOFT_HLUTNM = "soft_lutpair115" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_14 + (.I0(sig_data_fifo_data_out[51]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[19]), + .O(dm2linebuf_mm2s_tdata[19])); + (* SOFT_HLUTNM = "soft_lutpair122" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_14__0 + (.I0(sig_data_fifo_data_out[37]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[5]), + .O(dm2linebuf_mm2s_tdata[5])); + (* SOFT_HLUTNM = "soft_lutpair115" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_15 + (.I0(sig_data_fifo_data_out[50]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[18]), + .O(dm2linebuf_mm2s_tdata[18])); + (* SOFT_HLUTNM = "soft_lutpair122" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_15__0 + (.I0(sig_data_fifo_data_out[36]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[4]), + .O(dm2linebuf_mm2s_tdata[4])); + (* SOFT_HLUTNM = "soft_lutpair123" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_16 + (.I0(sig_data_fifo_data_out[35]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[3]), + .O(dm2linebuf_mm2s_tdata[3])); + (* SOFT_HLUTNM = "soft_lutpair123" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_17 + (.I0(sig_data_fifo_data_out[34]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[2]), + .O(dm2linebuf_mm2s_tdata[2])); + (* SOFT_HLUTNM = "soft_lutpair124" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_18 + (.I0(sig_data_fifo_data_out[33]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[1]), + .O(dm2linebuf_mm2s_tdata[1])); + (* SOFT_HLUTNM = "soft_lutpair124" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_19 + (.I0(sig_data_fifo_data_out[32]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[0]), + .O(dm2linebuf_mm2s_tdata[0])); + (* SOFT_HLUTNM = "soft_lutpair109" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_2 + (.I0(sig_data_fifo_data_out[63]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[31]), + .O(dm2linebuf_mm2s_tdata[31])); + (* SOFT_HLUTNM = "soft_lutpair116" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_20 + (.I0(sig_data_fifo_data_out[49]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[17]), + .O(dm2linebuf_mm2s_tdata[17])); + (* SOFT_HLUTNM = "soft_lutpair116" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_21 + (.I0(sig_data_fifo_data_out[48]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[16]), + .O(dm2linebuf_mm2s_tdata[16])); + (* SOFT_HLUTNM = "soft_lutpair109" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_3 + (.I0(sig_data_fifo_data_out[62]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[30]), + .O(dm2linebuf_mm2s_tdata[30])); + (* SOFT_HLUTNM = "soft_lutpair110" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_4 + (.I0(sig_data_fifo_data_out[61]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[29]), + .O(dm2linebuf_mm2s_tdata[29])); + (* SOFT_HLUTNM = "soft_lutpair117" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_4__0 + (.I0(sig_data_fifo_data_out[47]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[15]), + .O(dm2linebuf_mm2s_tdata[15])); + (* SOFT_HLUTNM = "soft_lutpair110" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_5 + (.I0(sig_data_fifo_data_out[60]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[28]), + .O(dm2linebuf_mm2s_tdata[28])); + (* SOFT_HLUTNM = "soft_lutpair117" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_5__0 + (.I0(sig_data_fifo_data_out[46]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[14]), + .O(dm2linebuf_mm2s_tdata[14])); + (* SOFT_HLUTNM = "soft_lutpair111" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_6 + (.I0(sig_data_fifo_data_out[59]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[27]), + .O(dm2linebuf_mm2s_tdata[27])); + (* SOFT_HLUTNM = "soft_lutpair118" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_6__0 + (.I0(sig_data_fifo_data_out[45]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[13]), + .O(dm2linebuf_mm2s_tdata[13])); + (* SOFT_HLUTNM = "soft_lutpair111" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_7 + (.I0(sig_data_fifo_data_out[58]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[26]), + .O(dm2linebuf_mm2s_tdata[26])); + (* SOFT_HLUTNM = "soft_lutpair118" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_7__0 + (.I0(sig_data_fifo_data_out[44]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[12]), + .O(dm2linebuf_mm2s_tdata[12])); + (* SOFT_HLUTNM = "soft_lutpair112" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_8 + (.I0(sig_data_fifo_data_out[57]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[25]), + .O(dm2linebuf_mm2s_tdata[25])); + (* SOFT_HLUTNM = "soft_lutpair119" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_8__0 + (.I0(sig_data_fifo_data_out[43]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[11]), + .O(dm2linebuf_mm2s_tdata[11])); + (* SOFT_HLUTNM = "soft_lutpair112" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_9 + (.I0(sig_data_fifo_data_out[56]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[24]), + .O(dm2linebuf_mm2s_tdata[24])); + (* SOFT_HLUTNM = "soft_lutpair119" *) + LUT3 #( + .INIT(8'hB8)) + \gf36e1_inst.sngfifo36e1_i_9__0 + (.I0(sig_data_fifo_data_out[42]), + .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .I2(sig_data_fifo_data_out[10]), + .O(dm2linebuf_mm2s_tdata[10])); endmodule (* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) -module Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_wrapper - (DOBDO, - \sig_user_skid_reg_reg[0] , - dm2linebuf_mm2s_tdata, - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , - \INFERRED_GEN.cnt_i_reg[0] , - m_axi_mm2s_aclk, +module Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_wrapper__parameterized0 + (sig_data_fifo_data_out, + m_axi_s2mm_aclk, ram_empty_fb_i_reg, - ram_full_i_reg, - \gpregsm1.curr_fwft_state_reg[0] , + WEBWE, + sig_s_ready_out_reg, sig_stream_rst, - \gc1.count_d2_reg[6] , + \gc1.count_d2_reg[7] , Q, - m_axi_mm2s_rdata, - DIBDI, - lsig_0ffset_cntr, - lsig_cmd_loaded, - \gpregsm1.user_valid_reg , - hold_ff_q, - p_0_out, - dm2linebuf_mm2s_tvalid, - p_8_out, - fifo_wren__0, - \INFERRED_GEN.cnt_i_reg[2] ); - output [0:0]DOBDO; - output [0:0]\sig_user_skid_reg_reg[0] ; - output [31:0]dm2linebuf_mm2s_tdata; - output \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; - output \INFERRED_GEN.cnt_i_reg[0] ; - input m_axi_mm2s_aclk; + lsig_combined_data, + DIBDI); + output [65:0]sig_data_fifo_data_out; + input m_axi_s2mm_aclk; input ram_empty_fb_i_reg; - input ram_full_i_reg; - input \gpregsm1.curr_fwft_state_reg[0] ; + input [0:0]WEBWE; + input sig_s_ready_out_reg; input sig_stream_rst; - input [6:0]\gc1.count_d2_reg[6] ; - input [6:0]Q; - input [63:0]m_axi_mm2s_rdata; + input [7:0]\gc1.count_d2_reg[7] ; + input [7:0]Q; + input [63:0]lsig_combined_data; input [1:0]DIBDI; - input lsig_0ffset_cntr; - input lsig_cmd_loaded; - input \gpregsm1.user_valid_reg ; - input hold_ff_q; - input [0:0]p_0_out; - input dm2linebuf_mm2s_tvalid; - input p_8_out; - input fifo_wren__0; - input [0:0]\INFERRED_GEN.cnt_i_reg[2] ; - wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_53 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85 ; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_86 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90 ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91 ; wire [1:0]DIBDI; - wire [0:0]DOBDO; - wire \INCLUDE_UNPACKING.lsig_0ffset_cntr[0]_i_2_n_0 ; - wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; - wire \INFERRED_GEN.cnt_i_reg[0] ; - wire [0:0]\INFERRED_GEN.cnt_i_reg[2] ; - wire [6:0]Q; - wire [31:0]dm2linebuf_mm2s_tdata; - wire dm2linebuf_mm2s_tvalid; - wire fifo_wren__0; - wire [6:0]\gc1.count_d2_reg[6] ; - wire \gpregsm1.curr_fwft_state_reg[0] ; - wire \gpregsm1.user_valid_reg ; - wire hold_ff_q; - wire lsig_0ffset_cntr; - wire lsig_cmd_loaded; - wire m_axi_mm2s_aclk; - wire [63:0]m_axi_mm2s_rdata; - wire [0:0]p_0_out; - wire p_8_out; + wire [7:0]Q; + wire [0:0]WEBWE; + wire [7:0]\gc1.count_d2_reg[7] ; + wire [63:0]lsig_combined_data; + wire m_axi_s2mm_aclk; wire ram_empty_fb_i_reg; - wire ram_full_i_reg; - wire [64:0]sig_data_fifo_data_out; + wire [65:0]sig_data_fifo_data_out; + wire sig_s_ready_out_reg; wire sig_stream_rst; - wire [0:0]\sig_user_skid_reg_reg[0] ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED ; wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED ; @@ -29334,30 +74283,30 @@ module Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_wrapper .WRITE_WIDTH_A(0), .WRITE_WIDTH_B(72)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram - (.ADDRARDADDR({1'b1,1'b0,1'b0,\gc1.count_d2_reg[6] ,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), - .ADDRBWRADDR({1'b1,1'b0,1'b0,Q,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), + (.ADDRARDADDR({1'b1,1'b0,\gc1.count_d2_reg[7] ,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,1'b0,Q,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED ), .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED ), - .CLKARDCLK(m_axi_mm2s_aclk), - .CLKBWRCLK(m_axi_mm2s_aclk), + .CLKARDCLK(m_axi_s2mm_aclk), + .CLKBWRCLK(m_axi_s2mm_aclk), .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED ), - .DIADI({m_axi_mm2s_rdata[33:26],m_axi_mm2s_rdata[24:9],m_axi_mm2s_rdata[7:0]}), - .DIBDI({1'b0,DIBDI,m_axi_mm2s_rdata[63:43],m_axi_mm2s_rdata[41:34]}), - .DIPADIP({1'b0,m_axi_mm2s_rdata[25],1'b0,m_axi_mm2s_rdata[8]}), - .DIPBDIP({1'b0,1'b0,1'b0,m_axi_mm2s_rdata[42]}), - .DOADO({sig_data_fifo_data_out[33:26],sig_data_fifo_data_out[24:9],sig_data_fifo_data_out[7:0]}), - .DOBDO({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_53 ,DOBDO,sig_data_fifo_data_out[64:43],sig_data_fifo_data_out[41:34]}), - .DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85 ,sig_data_fifo_data_out[25],\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87 ,sig_data_fifo_data_out[8]}), - .DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91 ,sig_data_fifo_data_out[42]}), + .DIADI({lsig_combined_data[32:9],lsig_combined_data[7:0]}), + .DIBDI({DIBDI,lsig_combined_data[63:42],lsig_combined_data[40:33]}), + .DIPADIP({1'b0,1'b0,1'b0,lsig_combined_data[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,lsig_combined_data[41]}), + .DOADO({sig_data_fifo_data_out[32:9],sig_data_fifo_data_out[7:0]}), + .DOBDO({sig_data_fifo_data_out[65:42],sig_data_fifo_data_out[40:33]}), + .DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_86 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87 ,sig_data_fifo_data_out[8]}), + .DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91 ,sig_data_fifo_data_out[41]}), .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED [7:0]), .ENARDEN(ram_empty_fb_i_reg), - .ENBWREN(ram_full_i_reg), + .ENBWREN(WEBWE), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED [8:0]), - .REGCEAREGCE(\gpregsm1.curr_fwft_state_reg[0] ), + .REGCEAREGCE(sig_s_ready_out_reg), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), @@ -29365,729 +74314,454 @@ module Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_wrapper .RSTREGB(1'b0), .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED ), .WEA({1'b0,1'b0,1'b0,1'b0}), - .WEBWE({ram_full_i_reg,ram_full_i_reg,ram_full_i_reg,ram_full_i_reg,ram_full_i_reg,ram_full_i_reg,ram_full_i_reg,ram_full_i_reg})); - LUT5 #( - .INIT(32'h8BBBB888)) - \INCLUDE_UNPACKING.lsig_0ffset_cntr[0]_i_1 - (.I0(p_0_out), - .I1(\INCLUDE_UNPACKING.lsig_0ffset_cntr[0]_i_2_n_0 ), - .I2(dm2linebuf_mm2s_tvalid), - .I3(p_8_out), - .I4(lsig_0ffset_cntr), - .O(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] )); - (* SOFT_HLUTNM = "soft_lutpair51" *) - LUT5 #( - .INIT(32'h0000D555)) - \INCLUDE_UNPACKING.lsig_0ffset_cntr[0]_i_2 - (.I0(lsig_cmd_loaded), - .I1(fifo_wren__0), - .I2(lsig_0ffset_cntr), - .I3(DOBDO), - .I4(\INFERRED_GEN.cnt_i_reg[2] ), - .O(\INCLUDE_UNPACKING.lsig_0ffset_cntr[0]_i_2_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair51" *) - LUT5 #( - .INIT(32'h000080FF)) - \INFERRED_GEN.cnt_i[2]_i_2 - (.I0(DOBDO), - .I1(lsig_0ffset_cntr), - .I2(fifo_wren__0), - .I3(lsig_cmd_loaded), - .I4(\INFERRED_GEN.cnt_i_reg[2] ), - .O(\INFERRED_GEN.cnt_i_reg[0] )); - LUT5 #( - .INIT(32'h80808000)) - \gf36e1_inst.sngfifo36e1_i_1 - (.I0(lsig_0ffset_cntr), - .I1(sig_data_fifo_data_out[64]), - .I2(lsig_cmd_loaded), - .I3(\gpregsm1.user_valid_reg ), - .I4(hold_ff_q), - .O(\sig_user_skid_reg_reg[0] )); - (* SOFT_HLUTNM = "soft_lutpair53" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_10 - (.I0(sig_data_fifo_data_out[33]), - .I1(sig_data_fifo_data_out[1]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[1])); - (* SOFT_HLUTNM = "soft_lutpair52" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_11 - (.I0(sig_data_fifo_data_out[32]), - .I1(sig_data_fifo_data_out[0]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[0])); - (* SOFT_HLUTNM = "soft_lutpair56" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_12 - (.I0(sig_data_fifo_data_out[40]), - .I1(sig_data_fifo_data_out[8]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[8])); - (* SOFT_HLUTNM = "soft_lutpair60" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_1__0 - (.I0(sig_data_fifo_data_out[48]), - .I1(sig_data_fifo_data_out[16]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[16])); - (* SOFT_HLUTNM = "soft_lutpair64" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_1__1 - (.I0(sig_data_fifo_data_out[57]), - .I1(sig_data_fifo_data_out[25]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[25])); - (* SOFT_HLUTNM = "soft_lutpair59" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_2 - (.I0(sig_data_fifo_data_out[47]), - .I1(sig_data_fifo_data_out[15]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[15])); - (* SOFT_HLUTNM = "soft_lutpair64" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_2__0 - (.I0(sig_data_fifo_data_out[56]), - .I1(sig_data_fifo_data_out[24]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[24])); - (* SOFT_HLUTNM = "soft_lutpair67" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_2__1 - (.I0(sig_data_fifo_data_out[63]), - .I1(sig_data_fifo_data_out[31]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[31])); - (* SOFT_HLUTNM = "soft_lutpair59" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_3__0 - (.I0(sig_data_fifo_data_out[46]), - .I1(sig_data_fifo_data_out[14]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[14])); - (* SOFT_HLUTNM = "soft_lutpair63" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_3__1 - (.I0(sig_data_fifo_data_out[55]), - .I1(sig_data_fifo_data_out[23]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[23])); - (* SOFT_HLUTNM = "soft_lutpair67" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_3__2 - (.I0(sig_data_fifo_data_out[62]), - .I1(sig_data_fifo_data_out[30]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[30])); - (* SOFT_HLUTNM = "soft_lutpair55" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_4 - (.I0(sig_data_fifo_data_out[39]), - .I1(sig_data_fifo_data_out[7]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[7])); - (* SOFT_HLUTNM = "soft_lutpair58" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_4__0 - (.I0(sig_data_fifo_data_out[45]), - .I1(sig_data_fifo_data_out[13]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[13])); - (* SOFT_HLUTNM = "soft_lutpair63" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_4__1 - (.I0(sig_data_fifo_data_out[54]), - .I1(sig_data_fifo_data_out[22]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[22])); - (* SOFT_HLUTNM = "soft_lutpair66" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_4__2 - (.I0(sig_data_fifo_data_out[61]), - .I1(sig_data_fifo_data_out[29]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[29])); - (* SOFT_HLUTNM = "soft_lutpair55" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_5 - (.I0(sig_data_fifo_data_out[38]), - .I1(sig_data_fifo_data_out[6]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[6])); - (* SOFT_HLUTNM = "soft_lutpair58" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_5__0 - (.I0(sig_data_fifo_data_out[44]), - .I1(sig_data_fifo_data_out[12]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[12])); - (* SOFT_HLUTNM = "soft_lutpair62" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_5__1 - (.I0(sig_data_fifo_data_out[53]), - .I1(sig_data_fifo_data_out[21]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[21])); - (* SOFT_HLUTNM = "soft_lutpair66" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_5__2 - (.I0(sig_data_fifo_data_out[60]), - .I1(sig_data_fifo_data_out[28]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[28])); - (* SOFT_HLUTNM = "soft_lutpair54" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_6 - (.I0(sig_data_fifo_data_out[37]), - .I1(sig_data_fifo_data_out[5]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[5])); - (* SOFT_HLUTNM = "soft_lutpair57" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_6__0 - (.I0(sig_data_fifo_data_out[43]), - .I1(sig_data_fifo_data_out[11]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[11])); - (* SOFT_HLUTNM = "soft_lutpair62" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_6__1 - (.I0(sig_data_fifo_data_out[52]), - .I1(sig_data_fifo_data_out[20]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[20])); - (* SOFT_HLUTNM = "soft_lutpair65" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_6__2 - (.I0(sig_data_fifo_data_out[59]), - .I1(sig_data_fifo_data_out[27]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[27])); - (* SOFT_HLUTNM = "soft_lutpair53" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_7 - (.I0(sig_data_fifo_data_out[36]), - .I1(sig_data_fifo_data_out[4]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[4])); - (* SOFT_HLUTNM = "soft_lutpair57" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_7__0 - (.I0(sig_data_fifo_data_out[42]), - .I1(sig_data_fifo_data_out[10]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[10])); - (* SOFT_HLUTNM = "soft_lutpair61" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_7__1 - (.I0(sig_data_fifo_data_out[51]), - .I1(sig_data_fifo_data_out[19]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[19])); - (* SOFT_HLUTNM = "soft_lutpair52" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_8 - (.I0(sig_data_fifo_data_out[35]), - .I1(sig_data_fifo_data_out[3]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[3])); - (* SOFT_HLUTNM = "soft_lutpair56" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_8__0 - (.I0(sig_data_fifo_data_out[41]), - .I1(sig_data_fifo_data_out[9]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[9])); - (* SOFT_HLUTNM = "soft_lutpair61" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_8__1 - (.I0(sig_data_fifo_data_out[50]), - .I1(sig_data_fifo_data_out[18]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[18])); - (* SOFT_HLUTNM = "soft_lutpair54" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_9 - (.I0(sig_data_fifo_data_out[34]), - .I1(sig_data_fifo_data_out[2]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[2])); - (* SOFT_HLUTNM = "soft_lutpair60" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_9__0 - (.I0(sig_data_fifo_data_out[49]), - .I1(sig_data_fifo_data_out[17]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[17])); - (* SOFT_HLUTNM = "soft_lutpair65" *) - LUT3 #( - .INIT(8'hAC)) - \gf36e1_inst.sngfifo36e1_i_9__1 - (.I0(sig_data_fifo_data_out[58]), - .I1(sig_data_fifo_data_out[26]), - .I2(lsig_0ffset_cntr), - .O(dm2linebuf_mm2s_tdata[26])); + .WEBWE({WEBWE,WEBWE,WEBWE,WEBWE,WEBWE,WEBWE,WEBWE,WEBWE})); endmodule (* ORIG_REF_NAME = "blk_mem_gen_top" *) module Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_top (DOBDO, - \sig_user_skid_reg_reg[0] , + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg , + \INFERRED_GEN.cnt_i_reg[2] , + DIN, dm2linebuf_mm2s_tdata, - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , - \INFERRED_GEN.cnt_i_reg[0] , m_axi_mm2s_aclk, - ram_empty_fb_i_reg, - ram_full_i_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0, + E, \gpregsm1.curr_fwft_state_reg[0] , - sig_stream_rst, - \gc1.count_d2_reg[6] , - Q, + SR, + \gc1.count_d2_reg[7] , + \gcc0.gc0.count_d1_reg[7] , m_axi_mm2s_rdata, DIBDI, - lsig_0ffset_cntr, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , + Q, lsig_cmd_loaded, - \gpregsm1.user_valid_reg , + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 , hold_ff_q, - p_0_out, - dm2linebuf_mm2s_tvalid, - p_8_out, - fifo_wren__0, - \INFERRED_GEN.cnt_i_reg[2] ); + out); output [0:0]DOBDO; - output [0:0]\sig_user_skid_reg_reg[0] ; + output \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + output \INFERRED_GEN.cnt_i_reg[2] ; + output [0:0]DIN; output [31:0]dm2linebuf_mm2s_tdata; - output \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; - output \INFERRED_GEN.cnt_i_reg[0] ; input m_axi_mm2s_aclk; - input ram_empty_fb_i_reg; - input ram_full_i_reg; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0; + input [0:0]E; input \gpregsm1.curr_fwft_state_reg[0] ; - input sig_stream_rst; - input [6:0]\gc1.count_d2_reg[6] ; - input [6:0]Q; + input [0:0]SR; + input [7:0]\gc1.count_d2_reg[7] ; + input [7:0]\gcc0.gc0.count_d1_reg[7] ; input [63:0]m_axi_mm2s_rdata; input [1:0]DIBDI; - input lsig_0ffset_cntr; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + input [0:0]Q; input lsig_cmd_loaded; - input \gpregsm1.user_valid_reg ; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; input hold_ff_q; - input [0:0]p_0_out; - input dm2linebuf_mm2s_tvalid; - input p_8_out; - input fifo_wren__0; - input [0:0]\INFERRED_GEN.cnt_i_reg[2] ; + input out; wire [1:0]DIBDI; + wire [0:0]DIN; wire [0:0]DOBDO; + wire [0:0]E; wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; - wire \INFERRED_GEN.cnt_i_reg[0] ; - wire [0:0]\INFERRED_GEN.cnt_i_reg[2] ; - wire [6:0]Q; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; + wire \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + wire \INFERRED_GEN.cnt_i_reg[2] ; + wire [0:0]Q; + wire [0:0]SR; wire [31:0]dm2linebuf_mm2s_tdata; - wire dm2linebuf_mm2s_tvalid; - wire fifo_wren__0; - wire [6:0]\gc1.count_d2_reg[6] ; + wire [7:0]\gc1.count_d2_reg[7] ; + wire [7:0]\gcc0.gc0.count_d1_reg[7] ; wire \gpregsm1.curr_fwft_state_reg[0] ; - wire \gpregsm1.user_valid_reg ; wire hold_ff_q; - wire lsig_0ffset_cntr; wire lsig_cmd_loaded; wire m_axi_mm2s_aclk; wire [63:0]m_axi_mm2s_rdata; - wire [0:0]p_0_out; - wire p_8_out; - wire ram_empty_fb_i_reg; - wire ram_full_i_reg; - wire sig_stream_rst; - wire [0:0]\sig_user_skid_reg_reg[0] ; + wire out; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0; Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_generic_cstr \valid.cstr (.DIBDI(DIBDI), + .DIN(DIN), .DOBDO(DOBDO), + .E(E), .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), - .\INFERRED_GEN.cnt_i_reg[0] (\INFERRED_GEN.cnt_i_reg[0] ), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .\INCLUDE_UNPACKING.lsig_cmd_loaded_reg (\INCLUDE_UNPACKING.lsig_cmd_loaded_reg ), .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ), .Q(Q), + .SR(SR), .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), - .dm2linebuf_mm2s_tvalid(dm2linebuf_mm2s_tvalid), - .fifo_wren__0(fifo_wren__0), - .\gc1.count_d2_reg[6] (\gc1.count_d2_reg[6] ), + .\gc1.count_d2_reg[7] (\gc1.count_d2_reg[7] ), + .\gcc0.gc0.count_d1_reg[7] (\gcc0.gc0.count_d1_reg[7] ), .\gpregsm1.curr_fwft_state_reg[0] (\gpregsm1.curr_fwft_state_reg[0] ), - .\gpregsm1.user_valid_reg (\gpregsm1.user_valid_reg ), .hold_ff_q(hold_ff_q), - .lsig_0ffset_cntr(lsig_0ffset_cntr), .lsig_cmd_loaded(lsig_cmd_loaded), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), .m_axi_mm2s_rdata(m_axi_mm2s_rdata), - .p_0_out(p_0_out), - .p_8_out(p_8_out), + .out(out), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0(sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_top" *) +module Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_top__parameterized0 + (sig_data_fifo_data_out, + m_axi_s2mm_aclk, + ram_empty_fb_i_reg, + WEBWE, + sig_s_ready_out_reg, + sig_stream_rst, + \gc1.count_d2_reg[7] , + Q, + lsig_combined_data, + DIBDI); + output [65:0]sig_data_fifo_data_out; + input m_axi_s2mm_aclk; + input ram_empty_fb_i_reg; + input [0:0]WEBWE; + input sig_s_ready_out_reg; + input sig_stream_rst; + input [7:0]\gc1.count_d2_reg[7] ; + input [7:0]Q; + input [63:0]lsig_combined_data; + input [1:0]DIBDI; + + wire [1:0]DIBDI; + wire [7:0]Q; + wire [0:0]WEBWE; + wire [7:0]\gc1.count_d2_reg[7] ; + wire [63:0]lsig_combined_data; + wire m_axi_s2mm_aclk; + wire ram_empty_fb_i_reg; + wire [65:0]sig_data_fifo_data_out; + wire sig_s_ready_out_reg; + wire sig_stream_rst; + + Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_generic_cstr__parameterized0 \valid.cstr + (.DIBDI(DIBDI), + .Q(Q), + .WEBWE(WEBWE), + .\gc1.count_d2_reg[7] (\gc1.count_d2_reg[7] ), + .lsig_combined_data(lsig_combined_data), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), .ram_empty_fb_i_reg(ram_empty_fb_i_reg), - .ram_full_i_reg(ram_full_i_reg), - .sig_stream_rst(sig_stream_rst), - .\sig_user_skid_reg_reg[0] (\sig_user_skid_reg_reg[0] )); + .sig_data_fifo_data_out(sig_data_fifo_data_out), + .sig_s_ready_out_reg(sig_s_ready_out_reg), + .sig_stream_rst(sig_stream_rst)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_v8_3_5" *) module Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5 (DOBDO, - \sig_user_skid_reg_reg[0] , + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg , + \INFERRED_GEN.cnt_i_reg[2] , + DIN, dm2linebuf_mm2s_tdata, - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , - \INFERRED_GEN.cnt_i_reg[0] , m_axi_mm2s_aclk, - ram_empty_fb_i_reg, - ram_full_i_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0, + E, \gpregsm1.curr_fwft_state_reg[0] , - sig_stream_rst, - \gc1.count_d2_reg[6] , - Q, + SR, + \gc1.count_d2_reg[7] , + \gcc0.gc0.count_d1_reg[7] , m_axi_mm2s_rdata, DIBDI, - lsig_0ffset_cntr, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , + Q, lsig_cmd_loaded, - \gpregsm1.user_valid_reg , + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 , hold_ff_q, - p_0_out, - dm2linebuf_mm2s_tvalid, - p_8_out, - fifo_wren__0, - \INFERRED_GEN.cnt_i_reg[2] ); + out); output [0:0]DOBDO; - output [0:0]\sig_user_skid_reg_reg[0] ; + output \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + output \INFERRED_GEN.cnt_i_reg[2] ; + output [0:0]DIN; output [31:0]dm2linebuf_mm2s_tdata; - output \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; - output \INFERRED_GEN.cnt_i_reg[0] ; input m_axi_mm2s_aclk; - input ram_empty_fb_i_reg; - input ram_full_i_reg; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0; + input [0:0]E; input \gpregsm1.curr_fwft_state_reg[0] ; - input sig_stream_rst; - input [6:0]\gc1.count_d2_reg[6] ; - input [6:0]Q; + input [0:0]SR; + input [7:0]\gc1.count_d2_reg[7] ; + input [7:0]\gcc0.gc0.count_d1_reg[7] ; input [63:0]m_axi_mm2s_rdata; input [1:0]DIBDI; - input lsig_0ffset_cntr; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + input [0:0]Q; input lsig_cmd_loaded; - input \gpregsm1.user_valid_reg ; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; input hold_ff_q; - input [0:0]p_0_out; - input dm2linebuf_mm2s_tvalid; - input p_8_out; - input fifo_wren__0; - input [0:0]\INFERRED_GEN.cnt_i_reg[2] ; + input out; wire [1:0]DIBDI; + wire [0:0]DIN; wire [0:0]DOBDO; + wire [0:0]E; wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; - wire \INFERRED_GEN.cnt_i_reg[0] ; - wire [0:0]\INFERRED_GEN.cnt_i_reg[2] ; - wire [6:0]Q; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; + wire \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + wire \INFERRED_GEN.cnt_i_reg[2] ; + wire [0:0]Q; + wire [0:0]SR; wire [31:0]dm2linebuf_mm2s_tdata; - wire dm2linebuf_mm2s_tvalid; - wire fifo_wren__0; - wire [6:0]\gc1.count_d2_reg[6] ; + wire [7:0]\gc1.count_d2_reg[7] ; + wire [7:0]\gcc0.gc0.count_d1_reg[7] ; wire \gpregsm1.curr_fwft_state_reg[0] ; - wire \gpregsm1.user_valid_reg ; wire hold_ff_q; - wire lsig_0ffset_cntr; wire lsig_cmd_loaded; wire m_axi_mm2s_aclk; wire [63:0]m_axi_mm2s_rdata; - wire [0:0]p_0_out; - wire p_8_out; - wire ram_empty_fb_i_reg; - wire ram_full_i_reg; - wire sig_stream_rst; - wire [0:0]\sig_user_skid_reg_reg[0] ; + wire out; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0; Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen (.DIBDI(DIBDI), + .DIN(DIN), .DOBDO(DOBDO), + .E(E), .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), - .\INFERRED_GEN.cnt_i_reg[0] (\INFERRED_GEN.cnt_i_reg[0] ), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .\INCLUDE_UNPACKING.lsig_cmd_loaded_reg (\INCLUDE_UNPACKING.lsig_cmd_loaded_reg ), .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ), .Q(Q), + .SR(SR), .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), - .dm2linebuf_mm2s_tvalid(dm2linebuf_mm2s_tvalid), - .fifo_wren__0(fifo_wren__0), - .\gc1.count_d2_reg[6] (\gc1.count_d2_reg[6] ), + .\gc1.count_d2_reg[7] (\gc1.count_d2_reg[7] ), + .\gcc0.gc0.count_d1_reg[7] (\gcc0.gc0.count_d1_reg[7] ), .\gpregsm1.curr_fwft_state_reg[0] (\gpregsm1.curr_fwft_state_reg[0] ), - .\gpregsm1.user_valid_reg (\gpregsm1.user_valid_reg ), .hold_ff_q(hold_ff_q), - .lsig_0ffset_cntr(lsig_0ffset_cntr), .lsig_cmd_loaded(lsig_cmd_loaded), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), .m_axi_mm2s_rdata(m_axi_mm2s_rdata), - .p_0_out(p_0_out), - .p_8_out(p_8_out), + .out(out), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0(sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_v8_3_5" *) +module Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5__parameterized1 + (sig_data_fifo_data_out, + m_axi_s2mm_aclk, + ram_empty_fb_i_reg, + WEBWE, + sig_s_ready_out_reg, + sig_stream_rst, + \gc1.count_d2_reg[7] , + Q, + lsig_combined_data, + DIBDI); + output [65:0]sig_data_fifo_data_out; + input m_axi_s2mm_aclk; + input ram_empty_fb_i_reg; + input [0:0]WEBWE; + input sig_s_ready_out_reg; + input sig_stream_rst; + input [7:0]\gc1.count_d2_reg[7] ; + input [7:0]Q; + input [63:0]lsig_combined_data; + input [1:0]DIBDI; + + wire [1:0]DIBDI; + wire [7:0]Q; + wire [0:0]WEBWE; + wire [7:0]\gc1.count_d2_reg[7] ; + wire [63:0]lsig_combined_data; + wire m_axi_s2mm_aclk; + wire ram_empty_fb_i_reg; + wire [65:0]sig_data_fifo_data_out; + wire sig_s_ready_out_reg; + wire sig_stream_rst; + + Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5_synth__parameterized0 inst_blk_mem_gen + (.DIBDI(DIBDI), + .Q(Q), + .WEBWE(WEBWE), + .\gc1.count_d2_reg[7] (\gc1.count_d2_reg[7] ), + .lsig_combined_data(lsig_combined_data), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), .ram_empty_fb_i_reg(ram_empty_fb_i_reg), - .ram_full_i_reg(ram_full_i_reg), - .sig_stream_rst(sig_stream_rst), - .\sig_user_skid_reg_reg[0] (\sig_user_skid_reg_reg[0] )); + .sig_data_fifo_data_out(sig_data_fifo_data_out), + .sig_s_ready_out_reg(sig_s_ready_out_reg), + .sig_stream_rst(sig_stream_rst)); endmodule (* ORIG_REF_NAME = "blk_mem_gen_v8_3_5_synth" *) module Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5_synth (DOBDO, - \sig_user_skid_reg_reg[0] , + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg , + \INFERRED_GEN.cnt_i_reg[2] , + DIN, dm2linebuf_mm2s_tdata, - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , - \INFERRED_GEN.cnt_i_reg[0] , m_axi_mm2s_aclk, - ram_empty_fb_i_reg, - ram_full_i_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0, + E, \gpregsm1.curr_fwft_state_reg[0] , - sig_stream_rst, - \gc1.count_d2_reg[6] , - Q, + SR, + \gc1.count_d2_reg[7] , + \gcc0.gc0.count_d1_reg[7] , m_axi_mm2s_rdata, DIBDI, - lsig_0ffset_cntr, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , + Q, lsig_cmd_loaded, - \gpregsm1.user_valid_reg , + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 , hold_ff_q, - p_0_out, - dm2linebuf_mm2s_tvalid, - p_8_out, - fifo_wren__0, - \INFERRED_GEN.cnt_i_reg[2] ); + out); output [0:0]DOBDO; - output [0:0]\sig_user_skid_reg_reg[0] ; + output \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + output \INFERRED_GEN.cnt_i_reg[2] ; + output [0:0]DIN; output [31:0]dm2linebuf_mm2s_tdata; - output \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; - output \INFERRED_GEN.cnt_i_reg[0] ; input m_axi_mm2s_aclk; - input ram_empty_fb_i_reg; - input ram_full_i_reg; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0; + input [0:0]E; input \gpregsm1.curr_fwft_state_reg[0] ; - input sig_stream_rst; - input [6:0]\gc1.count_d2_reg[6] ; - input [6:0]Q; + input [0:0]SR; + input [7:0]\gc1.count_d2_reg[7] ; + input [7:0]\gcc0.gc0.count_d1_reg[7] ; input [63:0]m_axi_mm2s_rdata; input [1:0]DIBDI; - input lsig_0ffset_cntr; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + input [0:0]Q; input lsig_cmd_loaded; - input \gpregsm1.user_valid_reg ; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; input hold_ff_q; - input [0:0]p_0_out; - input dm2linebuf_mm2s_tvalid; - input p_8_out; - input fifo_wren__0; - input [0:0]\INFERRED_GEN.cnt_i_reg[2] ; + input out; wire [1:0]DIBDI; + wire [0:0]DIN; wire [0:0]DOBDO; + wire [0:0]E; wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; - wire \INFERRED_GEN.cnt_i_reg[0] ; - wire [0:0]\INFERRED_GEN.cnt_i_reg[2] ; - wire [6:0]Q; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; + wire \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + wire \INFERRED_GEN.cnt_i_reg[2] ; + wire [0:0]Q; + wire [0:0]SR; wire [31:0]dm2linebuf_mm2s_tdata; - wire dm2linebuf_mm2s_tvalid; - wire fifo_wren__0; - wire [6:0]\gc1.count_d2_reg[6] ; + wire [7:0]\gc1.count_d2_reg[7] ; + wire [7:0]\gcc0.gc0.count_d1_reg[7] ; wire \gpregsm1.curr_fwft_state_reg[0] ; - wire \gpregsm1.user_valid_reg ; wire hold_ff_q; - wire lsig_0ffset_cntr; wire lsig_cmd_loaded; wire m_axi_mm2s_aclk; wire [63:0]m_axi_mm2s_rdata; - wire [0:0]p_0_out; - wire p_8_out; - wire ram_empty_fb_i_reg; - wire ram_full_i_reg; - wire sig_stream_rst; - wire [0:0]\sig_user_skid_reg_reg[0] ; + wire out; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0; Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen (.DIBDI(DIBDI), + .DIN(DIN), .DOBDO(DOBDO), + .E(E), .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), - .\INFERRED_GEN.cnt_i_reg[0] (\INFERRED_GEN.cnt_i_reg[0] ), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .\INCLUDE_UNPACKING.lsig_cmd_loaded_reg (\INCLUDE_UNPACKING.lsig_cmd_loaded_reg ), .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ), .Q(Q), + .SR(SR), .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), - .dm2linebuf_mm2s_tvalid(dm2linebuf_mm2s_tvalid), - .fifo_wren__0(fifo_wren__0), - .\gc1.count_d2_reg[6] (\gc1.count_d2_reg[6] ), + .\gc1.count_d2_reg[7] (\gc1.count_d2_reg[7] ), + .\gcc0.gc0.count_d1_reg[7] (\gcc0.gc0.count_d1_reg[7] ), .\gpregsm1.curr_fwft_state_reg[0] (\gpregsm1.curr_fwft_state_reg[0] ), - .\gpregsm1.user_valid_reg (\gpregsm1.user_valid_reg ), .hold_ff_q(hold_ff_q), - .lsig_0ffset_cntr(lsig_0ffset_cntr), .lsig_cmd_loaded(lsig_cmd_loaded), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), .m_axi_mm2s_rdata(m_axi_mm2s_rdata), - .p_0_out(p_0_out), - .p_8_out(p_8_out), - .ram_empty_fb_i_reg(ram_empty_fb_i_reg), - .ram_full_i_reg(ram_full_i_reg), - .sig_stream_rst(sig_stream_rst), - .\sig_user_skid_reg_reg[0] (\sig_user_skid_reg_reg[0] )); + .out(out), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0(sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0)); endmodule -(* ORIG_REF_NAME = "builtin_extdepth_v6" *) -module Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6 - (EMPTY, - FULL, - fifo_dout, - m_axis_mm2s_aclk, - RD_EN, - RST, - m_axi_mm2s_aclk, - WR_EN, - dm2linebuf_mm2s_tdata); - output EMPTY; - output FULL; - output [8:0]fifo_dout; - input m_axis_mm2s_aclk; - input RD_EN; - input RST; - input m_axi_mm2s_aclk; - input WR_EN; - input [8:0]dm2linebuf_mm2s_tdata; +(* ORIG_REF_NAME = "blk_mem_gen_v8_3_5_synth" *) +module Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5_synth__parameterized0 + (sig_data_fifo_data_out, + m_axi_s2mm_aclk, + ram_empty_fb_i_reg, + WEBWE, + sig_s_ready_out_reg, + sig_stream_rst, + \gc1.count_d2_reg[7] , + Q, + lsig_combined_data, + DIBDI); + output [65:0]sig_data_fifo_data_out; + input m_axi_s2mm_aclk; + input ram_empty_fb_i_reg; + input [0:0]WEBWE; + input sig_s_ready_out_reg; + input sig_stream_rst; + input [7:0]\gc1.count_d2_reg[7] ; + input [7:0]Q; + input [63:0]lsig_combined_data; + input [1:0]DIBDI; - wire EMPTY; - wire FULL; - wire RD_EN; - wire RST; - wire WR_EN; - wire [8:0]dm2linebuf_mm2s_tdata; - wire [8:0]fifo_dout; - wire m_axi_mm2s_aclk; - wire m_axis_mm2s_aclk; - wire \NLW_gextw[1].gnll_fifo.inst_extdi_0_O_UNCONNECTED ; - wire \NLW_gextw[1].gnll_fifo.inst_extdi_1_O_UNCONNECTED ; - wire \NLW_gextw[1].gnll_fifo.inst_extdi_2_O_UNCONNECTED ; - wire \NLW_gextw[1].gnll_fifo.inst_extdi_3_O_UNCONNECTED ; + wire [1:0]DIBDI; + wire [7:0]Q; + wire [0:0]WEBWE; + wire [7:0]\gc1.count_d2_reg[7] ; + wire [63:0]lsig_combined_data; + wire m_axi_s2mm_aclk; + wire ram_empty_fb_i_reg; + wire [65:0]sig_data_fifo_data_out; + wire sig_s_ready_out_reg; + wire sig_stream_rst; - LUT1 #( - .INIT(2'h2)) - \gextw[1].gnll_fifo.inst_extdi_0 - (.I0(1'b0), - .O(\NLW_gextw[1].gnll_fifo.inst_extdi_0_O_UNCONNECTED )); - LUT1 #( - .INIT(2'h2)) - \gextw[1].gnll_fifo.inst_extdi_1 - (.I0(1'b0), - .O(\NLW_gextw[1].gnll_fifo.inst_extdi_1_O_UNCONNECTED )); - LUT1 #( - .INIT(2'h2)) - \gextw[1].gnll_fifo.inst_extdi_2 - (.I0(1'b0), - .O(\NLW_gextw[1].gnll_fifo.inst_extdi_2_O_UNCONNECTED )); - LUT1 #( - .INIT(2'h2)) - \gextw[1].gnll_fifo.inst_extdi_3 - (.I0(1'b0), - .O(\NLW_gextw[1].gnll_fifo.inst_extdi_3_O_UNCONNECTED )); - Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_12 \gonep.inst_prim - (.EMPTY(EMPTY), - .FULL(FULL), - .RD_EN(RD_EN), - .RST(RST), - .WR_EN(WR_EN), - .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), - .fifo_dout(fifo_dout), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axis_mm2s_aclk(m_axis_mm2s_aclk)); + Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_top__parameterized0 \gnbram.gnativebmg.native_blk_mem_gen + (.DIBDI(DIBDI), + .Q(Q), + .WEBWE(WEBWE), + .\gc1.count_d2_reg[7] (\gc1.count_d2_reg[7] ), + .lsig_combined_data(lsig_combined_data), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .sig_data_fifo_data_out(sig_data_fifo_data_out), + .sig_s_ready_out_reg(sig_s_ready_out_reg), + .sig_stream_rst(sig_stream_rst)); endmodule (* ORIG_REF_NAME = "builtin_extdepth_v6" *) -module Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_7 - (fifo_full_i, - FULL, - sig_m_valid_out_reg, +module Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6 + (sig_m_valid_out_reg, EMPTY, - fifo_dout, - sig_s_ready_out_reg, - sig_s_ready_out_reg_0, \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg , + fifo_dout, \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 , - sig_s_ready_out_reg_1, - sig_s_ready_out_reg_2, m_axis_mm2s_aclk, RD_EN, RST, m_axi_mm2s_aclk, WR_EN, dm2linebuf_mm2s_tdata); - output fifo_full_i; - output FULL; output sig_m_valid_out_reg; output EMPTY; - output [8:0]fifo_dout; - input sig_s_ready_out_reg; - input sig_s_ready_out_reg_0; - input \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; + output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; + output [17:0]fifo_dout; input \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ; - input sig_s_ready_out_reg_1; - input sig_s_ready_out_reg_2; input m_axis_mm2s_aclk; input RD_EN; input RST; input m_axi_mm2s_aclk; input WR_EN; - input [8:0]dm2linebuf_mm2s_tdata; + input [17:0]dm2linebuf_mm2s_tdata; wire EMPTY; - wire FULL; wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ; wire RD_EN; wire RST; wire WR_EN; - wire [8:0]dm2linebuf_mm2s_tdata; - wire [8:0]fifo_dout; - wire fifo_full_i; + wire [17:0]dm2linebuf_mm2s_tdata; + wire [17:0]fifo_dout; wire m_axi_mm2s_aclk; wire m_axis_mm2s_aclk; wire sig_m_valid_out_reg; - wire sig_s_ready_out_reg; - wire sig_s_ready_out_reg_0; - wire sig_s_ready_out_reg_1; - wire sig_s_ready_out_reg_2; wire NLW_i_0_O_UNCONNECTED; wire NLW_i_1_O_UNCONNECTED; wire NLW_i_2_O_UNCONNECTED; wire NLW_i_3_O_UNCONNECTED; - Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_11 \gonep.inst_prim + Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_41 \gonep.inst_prim (.EMPTY(EMPTY), - .FULL(FULL), .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ), .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ), .RD_EN(RD_EN), @@ -30095,14 +74769,9 @@ module Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_7 .WR_EN(WR_EN), .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), .fifo_dout(fifo_dout), - .fifo_full_i(fifo_full_i), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), .m_axis_mm2s_aclk(m_axis_mm2s_aclk), - .sig_m_valid_out_reg(sig_m_valid_out_reg), - .sig_s_ready_out_reg(sig_s_ready_out_reg), - .sig_s_ready_out_reg_0(sig_s_ready_out_reg_0), - .sig_s_ready_out_reg_1(sig_s_ready_out_reg_1), - .sig_s_ready_out_reg_2(sig_s_ready_out_reg_2)); + .sig_m_valid_out_reg(sig_m_valid_out_reg)); LUT1 #( .INIT(2'h2)) i_0 @@ -30126,45 +74795,66 @@ module Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_7 endmodule (* ORIG_REF_NAME = "builtin_extdepth_v6" *) -module Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_8 +module Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_40 (RD_EN, EMPTY, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg , + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg , FULL, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 , fifo_dout, out, sig_s_ready_out_reg, - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg , + lsig_0ffset_cntr, sig_s_ready_out_reg_0, + mm2s_prmry_resetn, + mm2s_halt, + p_24_out, + hold_ff_q_reg, + DIN, m_axis_mm2s_aclk, RST, m_axi_mm2s_aclk, - WR_EN, - dm2linebuf_mm2s_tdata); + WR_EN); output RD_EN; output EMPTY; + output \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; output FULL; - output [8:0]fifo_dout; + output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ; + output [15:0]fifo_dout; input out; input sig_s_ready_out_reg; - input \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; + input lsig_0ffset_cntr; input sig_s_ready_out_reg_0; + input mm2s_prmry_resetn; + input mm2s_halt; + input p_24_out; + input hold_ff_q_reg; + input [15:0]DIN; input m_axis_mm2s_aclk; input RST; input m_axi_mm2s_aclk; input WR_EN; - input [8:0]dm2linebuf_mm2s_tdata; + wire [15:0]DIN; wire EMPTY; wire FULL; wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ; + wire \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; wire RD_EN; wire RST; wire WR_EN; - wire [8:0]dm2linebuf_mm2s_tdata; - wire [8:0]fifo_dout; + wire [15:0]fifo_dout; + wire hold_ff_q_reg; + wire lsig_0ffset_cntr; wire m_axi_mm2s_aclk; wire m_axis_mm2s_aclk; + wire mm2s_halt; + wire mm2s_prmry_resetn; wire out; + wire p_24_out; wire sig_s_ready_out_reg; wire sig_s_ready_out_reg_0; wire NLW_i_0_O_UNCONNECTED; @@ -30172,18 +74862,25 @@ module Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_8 wire NLW_i_2_O_UNCONNECTED; wire NLW_i_3_O_UNCONNECTED; - Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_10 \gonep.inst_prim - (.EMPTY(EMPTY), + Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6 \gonep.inst_prim + (.DIN(DIN), + .EMPTY(EMPTY), .FULL(FULL), .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ), + .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ), + .\INCLUDE_UNPACKING.lsig_cmd_loaded_reg (\INCLUDE_UNPACKING.lsig_cmd_loaded_reg ), .RD_EN(RD_EN), .RST(RST), .WR_EN(WR_EN), - .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), .fifo_dout(fifo_dout), + .hold_ff_q_reg(hold_ff_q_reg), + .lsig_0ffset_cntr(lsig_0ffset_cntr), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), .m_axis_mm2s_aclk(m_axis_mm2s_aclk), + .mm2s_halt(mm2s_halt), + .mm2s_prmry_resetn(mm2s_prmry_resetn), .out(out), + .p_24_out(p_24_out), .sig_s_ready_out_reg(sig_s_ready_out_reg), .sig_s_ready_out_reg_0(sig_s_ready_out_reg_0)); LUT1 #( @@ -30209,66 +74906,134 @@ module Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_8 endmodule (* ORIG_REF_NAME = "builtin_extdepth_v6" *) -module Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_9 - (WR_EN, - FULL, +module Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6__parameterized0 + (FULL, + D, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] , + DOUT, EMPTY, - fifo_dout, - fifo_wren__0, - sig_s_ready_out_reg, - sig_s_ready_out_reg_0, - sig_s_ready_out_reg_1, - m_axis_mm2s_aclk, + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg , + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg , + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg , + strm_not_finished_no_dwidth, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] , + M_VALID, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 , + s2mm_fsync_out_i, + out, + p_3_out, + Q, + \vsize_vid_reg[12] , + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out , + minusOp_1, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 , + s2mm_strm_wready, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] , + DIN, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] , + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] , + minusOp, + m_axi_s2mm_aclk, RD_EN, RST, - m_axi_mm2s_aclk, - DIN); - output WR_EN; + s_axis_s2mm_aclk); output FULL; + output [12:0]D; + output \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ; + output [8:0]DOUT; output EMPTY; - output [6:0]fifo_dout; - input fifo_wren__0; - input sig_s_ready_out_reg; - input sig_s_ready_out_reg_0; - input sig_s_ready_out_reg_1; - input m_axis_mm2s_aclk; + output \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg ; + output \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg ; + output \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ; + output strm_not_finished_no_dwidth; + output [12:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] ; + input M_VALID; + input \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ; + input s2mm_fsync_out_i; + input out; + input p_3_out; + input [6:0]Q; + input [12:0]\vsize_vid_reg[12] ; + input \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ; + input [11:0]minusOp_1; + input \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 ; + input s2mm_strm_wready; + input [0:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] ; + input [8:0]DIN; + input \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ; + input [12:0]\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] ; + input [11:0]minusOp; + input m_axi_s2mm_aclk; input RD_EN; input RST; - input m_axi_mm2s_aclk; - input [6:0]DIN; + input s_axis_s2mm_aclk; - wire [6:0]DIN; + wire [12:0]D; + wire [8:0]DIN; + wire [8:0]DOUT; wire EMPTY; wire FULL; + wire \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ; + wire [12:0]\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg ; + wire [0:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] ; + wire [12:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ; + wire M_VALID; + wire [6:0]Q; wire RD_EN; wire RST; - wire WR_EN; - wire [6:0]fifo_dout; - wire fifo_wren__0; - wire m_axi_mm2s_aclk; - wire m_axis_mm2s_aclk; - wire sig_s_ready_out_reg; - wire sig_s_ready_out_reg_0; - wire sig_s_ready_out_reg_1; + wire m_axi_s2mm_aclk; + wire [11:0]minusOp; + wire [11:0]minusOp_1; + wire out; + wire p_3_out; + wire s2mm_fsync_out_i; + wire s2mm_strm_wready; + wire s_axis_s2mm_aclk; + wire strm_not_finished_no_dwidth; + wire [12:0]\vsize_vid_reg[12] ; wire NLW_i_0_O_UNCONNECTED; wire NLW_i_1_O_UNCONNECTED; wire NLW_i_2_O_UNCONNECTED; wire NLW_i_3_O_UNCONNECTED; - Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6 \gonep.inst_prim - (.DIN(DIN), + Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6__parameterized0 \gonep.inst_prim + (.D(D), + .DIN(DIN), + .DOUT(DOUT), .EMPTY(EMPTY), .FULL(FULL), + .\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out (\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] (\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] (\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 (\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg (\GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ), + .M_VALID(M_VALID), + .Q(Q), .RD_EN(RD_EN), .RST(RST), - .WR_EN(WR_EN), - .fifo_dout(fifo_dout), - .fifo_wren__0(fifo_wren__0), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axis_mm2s_aclk(m_axis_mm2s_aclk), - .sig_s_ready_out_reg(sig_s_ready_out_reg), - .sig_s_ready_out_reg_0(sig_s_ready_out_reg_0), - .sig_s_ready_out_reg_1(sig_s_ready_out_reg_1)); + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .minusOp(minusOp), + .minusOp_1(minusOp_1), + .out(out), + .p_3_out(p_3_out), + .s2mm_fsync_out_i(s2mm_fsync_out_i), + .s2mm_strm_wready(s2mm_strm_wready), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk), + .strm_not_finished_no_dwidth(strm_not_finished_no_dwidth), + .\vsize_vid_reg[12] (\vsize_vid_reg[12] )); LUT1 #( .INIT(2'h2)) i_0 @@ -30296,45 +75061,61 @@ module Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6 (EMPTY, FULL, fifo_dout, - WR_EN, - m_axis_mm2s_aclk, RD_EN, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg , + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg , + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 , + m_axis_mm2s_aclk, RST, m_axi_mm2s_aclk, + WR_EN, DIN, - fifo_wren__0, + out, sig_s_ready_out_reg, + lsig_0ffset_cntr, sig_s_ready_out_reg_0, - sig_s_ready_out_reg_1); + mm2s_prmry_resetn, + mm2s_halt, + p_24_out, + hold_ff_q_reg); output EMPTY; output FULL; - output [6:0]fifo_dout; - output WR_EN; + output [15:0]fifo_dout; + output RD_EN; + output \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; + output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ; input m_axis_mm2s_aclk; - input RD_EN; input RST; input m_axi_mm2s_aclk; - input [6:0]DIN; - input fifo_wren__0; + input WR_EN; + input [15:0]DIN; + input out; input sig_s_ready_out_reg; + input lsig_0ffset_cntr; input sig_s_ready_out_reg_0; - input sig_s_ready_out_reg_1; + input mm2s_prmry_resetn; + input mm2s_halt; + input p_24_out; + input hold_ff_q_reg; - wire [6:0]DIN; + wire [15:0]DIN; wire EMPTY; wire FULL; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ; + wire \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; wire RD_EN; wire RST; wire WR_EN; - wire [6:0]fifo_dout; - wire fifo_wren__0; + wire [15:0]fifo_dout; wire \gf36e1_inst.sngfifo36e1_n_0 ; wire \gf36e1_inst.sngfifo36e1_n_1 ; wire \gf36e1_inst.sngfifo36e1_n_10 ; + wire \gf36e1_inst.sngfifo36e1_n_112 ; wire \gf36e1_inst.sngfifo36e1_n_113 ; wire \gf36e1_inst.sngfifo36e1_n_14 ; wire \gf36e1_inst.sngfifo36e1_n_15 ; - wire \gf36e1_inst.sngfifo36e1_n_17 ; wire \gf36e1_inst.sngfifo36e1_n_18 ; wire \gf36e1_inst.sngfifo36e1_n_19 ; wire \gf36e1_inst.sngfifo36e1_n_20 ; @@ -30346,7 +75127,6 @@ module Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6 wire \gf36e1_inst.sngfifo36e1_n_26 ; wire \gf36e1_inst.sngfifo36e1_n_27 ; wire \gf36e1_inst.sngfifo36e1_n_28 ; - wire \gf36e1_inst.sngfifo36e1_n_30 ; wire \gf36e1_inst.sngfifo36e1_n_31 ; wire \gf36e1_inst.sngfifo36e1_n_32 ; wire \gf36e1_inst.sngfifo36e1_n_33 ; @@ -30358,25 +75138,54 @@ module Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6 wire \gf36e1_inst.sngfifo36e1_n_39 ; wire \gf36e1_inst.sngfifo36e1_n_40 ; wire \gf36e1_inst.sngfifo36e1_n_41 ; - wire \gf36e1_inst.sngfifo36e1_n_98 ; + wire hold_ff_q_reg; + wire lsig_0ffset_cntr; wire m_axi_mm2s_aclk; wire m_axis_mm2s_aclk; + wire mm2s_halt; + wire mm2s_prmry_resetn; + wire out; + wire p_24_out; wire p_3_out; wire sig_s_ready_out_reg; wire sig_s_ready_out_reg_0; - wire sig_s_ready_out_reg_1; - wire [63:8]\NLW_gf36e1_inst.sngfifo36e1_DO_UNCONNECTED ; - wire [7:1]\NLW_gf36e1_inst.sngfifo36e1_DOP_UNCONNECTED ; + wire [63:16]\NLW_gf36e1_inst.sngfifo36e1_DO_UNCONNECTED ; + wire [7:2]\NLW_gf36e1_inst.sngfifo36e1_DOP_UNCONNECTED ; wire [7:0]\NLW_gf36e1_inst.sngfifo36e1_ECCPARITY_UNCONNECTED ; - wire [12:12]\NLW_gf36e1_inst.sngfifo36e1_RDCOUNT_UNCONNECTED ; - wire [12:12]\NLW_gf36e1_inst.sngfifo36e1_WRCOUNT_UNCONNECTED ; + wire [12:11]\NLW_gf36e1_inst.sngfifo36e1_RDCOUNT_UNCONNECTED ; + wire [12:11]\NLW_gf36e1_inst.sngfifo36e1_WRCOUNT_UNCONNECTED ; + LUT2 #( + .INIT(4'h7)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_9 + (.I0(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ), + .I1(lsig_0ffset_cntr), + .O(\INCLUDE_UNPACKING.lsig_cmd_loaded_reg )); + LUT5 #( + .INIT(32'h00000E00)) + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_i_1 + (.I0(DIN[15]), + .I1(p_24_out), + .I2(mm2s_halt), + .I3(mm2s_prmry_resetn), + .I4(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ), + .O(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 )); + LUT6 #( + .INIT(64'h0000000000000010)) + \INCLUDE_UNPACKING.lsig_0ffset_cntr[0]_i_2 + (.I0(FULL), + .I1(sig_s_ready_out_reg_0), + .I2(mm2s_prmry_resetn), + .I3(mm2s_halt), + .I4(p_24_out), + .I5(hold_ff_q_reg), + .O(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg )); (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) FIFO36E1 #( .ALMOST_EMPTY_OFFSET(13'h000A), .ALMOST_FULL_OFFSET(13'h0097), - .DATA_WIDTH(9), + .DATA_WIDTH(18), .DO_REG(1), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), @@ -30396,17 +75205,17 @@ module Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6 (.ALMOSTEMPTY(\gf36e1_inst.sngfifo36e1_n_10 ), .ALMOSTFULL(p_3_out), .DBITERR(\gf36e1_inst.sngfifo36e1_n_0 ), - .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,DIN}), + .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,DIN}), .DIP({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DO({\NLW_gf36e1_inst.sngfifo36e1_DO_UNCONNECTED [63:8],\gf36e1_inst.sngfifo36e1_n_98 ,fifo_dout}), - .DOP({\NLW_gf36e1_inst.sngfifo36e1_DOP_UNCONNECTED [7:1],\gf36e1_inst.sngfifo36e1_n_113 }), + .DO({\NLW_gf36e1_inst.sngfifo36e1_DO_UNCONNECTED [63:16],fifo_dout}), + .DOP({\NLW_gf36e1_inst.sngfifo36e1_DOP_UNCONNECTED [7:2],\gf36e1_inst.sngfifo36e1_n_112 ,\gf36e1_inst.sngfifo36e1_n_113 }), .ECCPARITY(\NLW_gf36e1_inst.sngfifo36e1_ECCPARITY_UNCONNECTED [7:0]), .EMPTY(EMPTY), .FULL(FULL), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDCLK(m_axis_mm2s_aclk), - .RDCOUNT({\NLW_gf36e1_inst.sngfifo36e1_RDCOUNT_UNCONNECTED [12],\gf36e1_inst.sngfifo36e1_n_17 ,\gf36e1_inst.sngfifo36e1_n_18 ,\gf36e1_inst.sngfifo36e1_n_19 ,\gf36e1_inst.sngfifo36e1_n_20 ,\gf36e1_inst.sngfifo36e1_n_21 ,\gf36e1_inst.sngfifo36e1_n_22 ,\gf36e1_inst.sngfifo36e1_n_23 ,\gf36e1_inst.sngfifo36e1_n_24 ,\gf36e1_inst.sngfifo36e1_n_25 ,\gf36e1_inst.sngfifo36e1_n_26 ,\gf36e1_inst.sngfifo36e1_n_27 ,\gf36e1_inst.sngfifo36e1_n_28 }), + .RDCOUNT({\NLW_gf36e1_inst.sngfifo36e1_RDCOUNT_UNCONNECTED [12:11],\gf36e1_inst.sngfifo36e1_n_18 ,\gf36e1_inst.sngfifo36e1_n_19 ,\gf36e1_inst.sngfifo36e1_n_20 ,\gf36e1_inst.sngfifo36e1_n_21 ,\gf36e1_inst.sngfifo36e1_n_22 ,\gf36e1_inst.sngfifo36e1_n_23 ,\gf36e1_inst.sngfifo36e1_n_24 ,\gf36e1_inst.sngfifo36e1_n_25 ,\gf36e1_inst.sngfifo36e1_n_26 ,\gf36e1_inst.sngfifo36e1_n_27 ,\gf36e1_inst.sngfifo36e1_n_28 }), .RDEN(RD_EN), .RDERR(\gf36e1_inst.sngfifo36e1_n_14 ), .REGCE(1'b0), @@ -30414,60 +75223,53 @@ module Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6 .RSTREG(1'b0), .SBITERR(\gf36e1_inst.sngfifo36e1_n_1 ), .WRCLK(m_axi_mm2s_aclk), - .WRCOUNT({\NLW_gf36e1_inst.sngfifo36e1_WRCOUNT_UNCONNECTED [12],\gf36e1_inst.sngfifo36e1_n_30 ,\gf36e1_inst.sngfifo36e1_n_31 ,\gf36e1_inst.sngfifo36e1_n_32 ,\gf36e1_inst.sngfifo36e1_n_33 ,\gf36e1_inst.sngfifo36e1_n_34 ,\gf36e1_inst.sngfifo36e1_n_35 ,\gf36e1_inst.sngfifo36e1_n_36 ,\gf36e1_inst.sngfifo36e1_n_37 ,\gf36e1_inst.sngfifo36e1_n_38 ,\gf36e1_inst.sngfifo36e1_n_39 ,\gf36e1_inst.sngfifo36e1_n_40 ,\gf36e1_inst.sngfifo36e1_n_41 }), + .WRCOUNT({\NLW_gf36e1_inst.sngfifo36e1_WRCOUNT_UNCONNECTED [12:11],\gf36e1_inst.sngfifo36e1_n_31 ,\gf36e1_inst.sngfifo36e1_n_32 ,\gf36e1_inst.sngfifo36e1_n_33 ,\gf36e1_inst.sngfifo36e1_n_34 ,\gf36e1_inst.sngfifo36e1_n_35 ,\gf36e1_inst.sngfifo36e1_n_36 ,\gf36e1_inst.sngfifo36e1_n_37 ,\gf36e1_inst.sngfifo36e1_n_38 ,\gf36e1_inst.sngfifo36e1_n_39 ,\gf36e1_inst.sngfifo36e1_n_40 ,\gf36e1_inst.sngfifo36e1_n_41 }), .WREN(WR_EN), .WRERR(\gf36e1_inst.sngfifo36e1_n_15 )); - LUT5 #( - .INIT(32'h00000002)) - \gf36e1_inst.sngfifo36e1_i_3 - (.I0(fifo_wren__0), - .I1(FULL), + LUT3 #( + .INIT(8'h02)) + \gf36e1_inst.sngfifo36e1_i_1__0 + (.I0(out), + .I1(EMPTY), .I2(sig_s_ready_out_reg), - .I3(sig_s_ready_out_reg_0), - .I4(sig_s_ready_out_reg_1), - .O(WR_EN)); + .O(RD_EN)); endmodule (* ORIG_REF_NAME = "builtin_prim_v6" *) -module Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_10 +module Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_41 (EMPTY, - FULL, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg , fifo_dout, - RD_EN, + sig_m_valid_out_reg, m_axis_mm2s_aclk, + RD_EN, RST, m_axi_mm2s_aclk, WR_EN, dm2linebuf_mm2s_tdata, - out, - sig_s_ready_out_reg, - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg , - sig_s_ready_out_reg_0); + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ); output EMPTY; - output FULL; - output [8:0]fifo_dout; - output RD_EN; + output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; + output [17:0]fifo_dout; + output sig_m_valid_out_reg; input m_axis_mm2s_aclk; + input RD_EN; input RST; input m_axi_mm2s_aclk; input WR_EN; - input [8:0]dm2linebuf_mm2s_tdata; - input out; - input sig_s_ready_out_reg; - input \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; - input sig_s_ready_out_reg_0; + input [17:0]dm2linebuf_mm2s_tdata; + input \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ; wire EMPTY; - wire FULL; wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ; wire RD_EN; wire RST; wire WR_EN; - wire [8:0]dm2linebuf_mm2s_tdata; - wire [8:0]fifo_dout; + wire [17:0]dm2linebuf_mm2s_tdata; + wire [17:0]fifo_dout; wire \gf36e1_inst.sngfifo36e1_n_14 ; wire \gf36e1_inst.sngfifo36e1_n_15 ; - wire \gf36e1_inst.sngfifo36e1_n_17 ; wire \gf36e1_inst.sngfifo36e1_n_18 ; wire \gf36e1_inst.sngfifo36e1_n_19 ; wire \gf36e1_inst.sngfifo36e1_n_20 ; @@ -30479,7 +75281,6 @@ module Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_10 wire \gf36e1_inst.sngfifo36e1_n_26 ; wire \gf36e1_inst.sngfifo36e1_n_27 ; wire \gf36e1_inst.sngfifo36e1_n_28 ; - wire \gf36e1_inst.sngfifo36e1_n_30 ; wire \gf36e1_inst.sngfifo36e1_n_31 ; wire \gf36e1_inst.sngfifo36e1_n_32 ; wire \gf36e1_inst.sngfifo36e1_n_33 ; @@ -30493,25 +75294,23 @@ module Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_10 wire \gf36e1_inst.sngfifo36e1_n_41 ; wire m_axi_mm2s_aclk; wire m_axis_mm2s_aclk; - wire out; wire p_10_out; wire p_11_out; wire p_12_out; wire p_13_out; - wire sig_s_ready_out_reg; - wire sig_s_ready_out_reg_0; - wire [63:8]\NLW_gf36e1_inst.sngfifo36e1_DO_UNCONNECTED ; - wire [7:1]\NLW_gf36e1_inst.sngfifo36e1_DOP_UNCONNECTED ; + wire sig_m_valid_out_reg; + wire [63:16]\NLW_gf36e1_inst.sngfifo36e1_DO_UNCONNECTED ; + wire [7:2]\NLW_gf36e1_inst.sngfifo36e1_DOP_UNCONNECTED ; wire [7:0]\NLW_gf36e1_inst.sngfifo36e1_ECCPARITY_UNCONNECTED ; - wire [12:12]\NLW_gf36e1_inst.sngfifo36e1_RDCOUNT_UNCONNECTED ; - wire [12:12]\NLW_gf36e1_inst.sngfifo36e1_WRCOUNT_UNCONNECTED ; + wire [12:11]\NLW_gf36e1_inst.sngfifo36e1_RDCOUNT_UNCONNECTED ; + wire [12:11]\NLW_gf36e1_inst.sngfifo36e1_WRCOUNT_UNCONNECTED ; (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) FIFO36E1 #( .ALMOST_EMPTY_OFFSET(13'h000A), .ALMOST_FULL_OFFSET(13'h0097), - .DATA_WIDTH(9), + .DATA_WIDTH(18), .DO_REG(1), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), @@ -30531,17 +75330,17 @@ module Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_10 (.ALMOSTEMPTY(p_11_out), .ALMOSTFULL(p_10_out), .DBITERR(p_13_out), - .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dm2linebuf_mm2s_tdata[7:0]}), - .DIP({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dm2linebuf_mm2s_tdata[8]}), - .DO({\NLW_gf36e1_inst.sngfifo36e1_DO_UNCONNECTED [63:8],fifo_dout[7:0]}), - .DOP({\NLW_gf36e1_inst.sngfifo36e1_DOP_UNCONNECTED [7:1],fifo_dout[8]}), + .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dm2linebuf_mm2s_tdata[15:0]}), + .DIP({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dm2linebuf_mm2s_tdata[17:16]}), + .DO({\NLW_gf36e1_inst.sngfifo36e1_DO_UNCONNECTED [63:16],fifo_dout[15:0]}), + .DOP({\NLW_gf36e1_inst.sngfifo36e1_DOP_UNCONNECTED [7:2],fifo_dout[17:16]}), .ECCPARITY(\NLW_gf36e1_inst.sngfifo36e1_ECCPARITY_UNCONNECTED [7:0]), .EMPTY(EMPTY), - .FULL(FULL), + .FULL(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDCLK(m_axis_mm2s_aclk), - .RDCOUNT({\NLW_gf36e1_inst.sngfifo36e1_RDCOUNT_UNCONNECTED [12],\gf36e1_inst.sngfifo36e1_n_17 ,\gf36e1_inst.sngfifo36e1_n_18 ,\gf36e1_inst.sngfifo36e1_n_19 ,\gf36e1_inst.sngfifo36e1_n_20 ,\gf36e1_inst.sngfifo36e1_n_21 ,\gf36e1_inst.sngfifo36e1_n_22 ,\gf36e1_inst.sngfifo36e1_n_23 ,\gf36e1_inst.sngfifo36e1_n_24 ,\gf36e1_inst.sngfifo36e1_n_25 ,\gf36e1_inst.sngfifo36e1_n_26 ,\gf36e1_inst.sngfifo36e1_n_27 ,\gf36e1_inst.sngfifo36e1_n_28 }), + .RDCOUNT({\NLW_gf36e1_inst.sngfifo36e1_RDCOUNT_UNCONNECTED [12:11],\gf36e1_inst.sngfifo36e1_n_18 ,\gf36e1_inst.sngfifo36e1_n_19 ,\gf36e1_inst.sngfifo36e1_n_20 ,\gf36e1_inst.sngfifo36e1_n_21 ,\gf36e1_inst.sngfifo36e1_n_22 ,\gf36e1_inst.sngfifo36e1_n_23 ,\gf36e1_inst.sngfifo36e1_n_24 ,\gf36e1_inst.sngfifo36e1_n_25 ,\gf36e1_inst.sngfifo36e1_n_26 ,\gf36e1_inst.sngfifo36e1_n_27 ,\gf36e1_inst.sngfifo36e1_n_28 }), .RDEN(RD_EN), .RDERR(\gf36e1_inst.sngfifo36e1_n_14 ), .REGCE(1'b0), @@ -30549,131 +75348,426 @@ module Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_10 .RSTREG(1'b0), .SBITERR(p_12_out), .WRCLK(m_axi_mm2s_aclk), - .WRCOUNT({\NLW_gf36e1_inst.sngfifo36e1_WRCOUNT_UNCONNECTED [12],\gf36e1_inst.sngfifo36e1_n_30 ,\gf36e1_inst.sngfifo36e1_n_31 ,\gf36e1_inst.sngfifo36e1_n_32 ,\gf36e1_inst.sngfifo36e1_n_33 ,\gf36e1_inst.sngfifo36e1_n_34 ,\gf36e1_inst.sngfifo36e1_n_35 ,\gf36e1_inst.sngfifo36e1_n_36 ,\gf36e1_inst.sngfifo36e1_n_37 ,\gf36e1_inst.sngfifo36e1_n_38 ,\gf36e1_inst.sngfifo36e1_n_39 ,\gf36e1_inst.sngfifo36e1_n_40 ,\gf36e1_inst.sngfifo36e1_n_41 }), + .WRCOUNT({\NLW_gf36e1_inst.sngfifo36e1_WRCOUNT_UNCONNECTED [12:11],\gf36e1_inst.sngfifo36e1_n_31 ,\gf36e1_inst.sngfifo36e1_n_32 ,\gf36e1_inst.sngfifo36e1_n_33 ,\gf36e1_inst.sngfifo36e1_n_34 ,\gf36e1_inst.sngfifo36e1_n_35 ,\gf36e1_inst.sngfifo36e1_n_36 ,\gf36e1_inst.sngfifo36e1_n_37 ,\gf36e1_inst.sngfifo36e1_n_38 ,\gf36e1_inst.sngfifo36e1_n_39 ,\gf36e1_inst.sngfifo36e1_n_40 ,\gf36e1_inst.sngfifo36e1_n_41 }), .WREN(WR_EN), .WRERR(\gf36e1_inst.sngfifo36e1_n_15 )); - LUT5 #( - .INIT(32'h00000002)) - \gf36e1_inst.sngfifo36e1_i_1__2 - (.I0(out), - .I1(EMPTY), - .I2(sig_s_ready_out_reg), - .I3(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ), - .I4(sig_s_ready_out_reg_0), - .O(RD_EN)); + LUT2 #( + .INIT(4'hE)) + sig_s_ready_dup_i_2 + (.I0(EMPTY), + .I1(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ), + .O(sig_m_valid_out_reg)); endmodule (* ORIG_REF_NAME = "builtin_prim_v6" *) -module Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_11 +module Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6__parameterized0 (EMPTY, FULL, - fifo_dout, - fifo_full_i, - sig_m_valid_out_reg, - m_axis_mm2s_aclk, + DOUT, + D, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] , + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg , + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg , + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg , + strm_not_finished_no_dwidth, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] , + m_axi_s2mm_aclk, RD_EN, RST, - m_axi_mm2s_aclk, - WR_EN, - dm2linebuf_mm2s_tdata, - sig_s_ready_out_reg, - sig_s_ready_out_reg_0, - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg , - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 , - sig_s_ready_out_reg_1, - sig_s_ready_out_reg_2); + s_axis_s2mm_aclk, + DIN, + M_VALID, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 , + s2mm_fsync_out_i, + out, + p_3_out, + Q, + \vsize_vid_reg[12] , + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out , + minusOp_1, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 , + s2mm_strm_wready, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] , + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] , + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] , + minusOp); output EMPTY; output FULL; - output [8:0]fifo_dout; - output fifo_full_i; - output sig_m_valid_out_reg; - input m_axis_mm2s_aclk; + output [8:0]DOUT; + output [12:0]D; + output \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ; + output \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg ; + output \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg ; + output \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ; + output strm_not_finished_no_dwidth; + output [12:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] ; + input m_axi_s2mm_aclk; input RD_EN; input RST; - input m_axi_mm2s_aclk; - input WR_EN; - input [8:0]dm2linebuf_mm2s_tdata; - input sig_s_ready_out_reg; - input sig_s_ready_out_reg_0; - input \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; - input \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ; - input sig_s_ready_out_reg_1; - input sig_s_ready_out_reg_2; + input s_axis_s2mm_aclk; + input [8:0]DIN; + input M_VALID; + input \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ; + input s2mm_fsync_out_i; + input out; + input p_3_out; + input [6:0]Q; + input [12:0]\vsize_vid_reg[12] ; + input \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ; + input [11:0]minusOp_1; + input \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 ; + input s2mm_strm_wready; + input [0:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] ; + input \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ; + input [12:0]\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] ; + input [11:0]minusOp; + wire [12:0]D; + wire [8:0]DIN; + wire [8:0]DOUT; wire EMPTY; wire FULL; - wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; - wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ; + wire \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ; + wire [12:0]\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_14_n_0 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0 ; + wire [0:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] ; + wire [12:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ; + wire M_VALID; + wire [6:0]Q; wire RD_EN; wire RST; - wire WR_EN; - wire [8:0]dm2linebuf_mm2s_tdata; - wire [8:0]fifo_dout; - wire fifo_full_i; - wire \gf36e1_inst.sngfifo36e1_n_14 ; - wire \gf36e1_inst.sngfifo36e1_n_15 ; - wire \gf36e1_inst.sngfifo36e1_n_17 ; - wire \gf36e1_inst.sngfifo36e1_n_18 ; - wire \gf36e1_inst.sngfifo36e1_n_19 ; - wire \gf36e1_inst.sngfifo36e1_n_20 ; - wire \gf36e1_inst.sngfifo36e1_n_21 ; - wire \gf36e1_inst.sngfifo36e1_n_22 ; - wire \gf36e1_inst.sngfifo36e1_n_23 ; - wire \gf36e1_inst.sngfifo36e1_n_24 ; - wire \gf36e1_inst.sngfifo36e1_n_25 ; - wire \gf36e1_inst.sngfifo36e1_n_26 ; - wire \gf36e1_inst.sngfifo36e1_n_27 ; - wire \gf36e1_inst.sngfifo36e1_n_28 ; - wire \gf36e1_inst.sngfifo36e1_n_30 ; - wire \gf36e1_inst.sngfifo36e1_n_31 ; - wire \gf36e1_inst.sngfifo36e1_n_32 ; - wire \gf36e1_inst.sngfifo36e1_n_33 ; - wire \gf36e1_inst.sngfifo36e1_n_34 ; - wire \gf36e1_inst.sngfifo36e1_n_35 ; - wire \gf36e1_inst.sngfifo36e1_n_36 ; - wire \gf36e1_inst.sngfifo36e1_n_37 ; - wire \gf36e1_inst.sngfifo36e1_n_38 ; - wire \gf36e1_inst.sngfifo36e1_n_39 ; - wire \gf36e1_inst.sngfifo36e1_n_40 ; - wire \gf36e1_inst.sngfifo36e1_n_41 ; - wire m_axi_mm2s_aclk; - wire m_axis_mm2s_aclk; - wire p_17_out; - wire p_18_out; - wire p_19_out; - wire p_20_out; - wire sig_m_valid_out_reg; - wire sig_s_ready_out_reg; - wire sig_s_ready_out_reg_0; - wire sig_s_ready_out_reg_1; - wire sig_s_ready_out_reg_2; - wire [63:8]\NLW_gf36e1_inst.sngfifo36e1_DO_UNCONNECTED ; - wire [7:1]\NLW_gf36e1_inst.sngfifo36e1_DOP_UNCONNECTED ; - wire [7:0]\NLW_gf36e1_inst.sngfifo36e1_ECCPARITY_UNCONNECTED ; - wire [12:12]\NLW_gf36e1_inst.sngfifo36e1_RDCOUNT_UNCONNECTED ; - wire [12:12]\NLW_gf36e1_inst.sngfifo36e1_WRCOUNT_UNCONNECTED ; + wire fifo_wren; + wire \gf18e1_inst.sngfifo18e1_n_0 ; + wire \gf18e1_inst.sngfifo18e1_n_1 ; + wire \gf18e1_inst.sngfifo18e1_n_10 ; + wire \gf18e1_inst.sngfifo18e1_n_11 ; + wire \gf18e1_inst.sngfifo18e1_n_12 ; + wire \gf18e1_inst.sngfifo18e1_n_13 ; + wire \gf18e1_inst.sngfifo18e1_n_14 ; + wire \gf18e1_inst.sngfifo18e1_n_15 ; + wire \gf18e1_inst.sngfifo18e1_n_16 ; + wire \gf18e1_inst.sngfifo18e1_n_17 ; + wire \gf18e1_inst.sngfifo18e1_n_19 ; + wire \gf18e1_inst.sngfifo18e1_n_20 ; + wire \gf18e1_inst.sngfifo18e1_n_21 ; + wire \gf18e1_inst.sngfifo18e1_n_22 ; + wire \gf18e1_inst.sngfifo18e1_n_23 ; + wire \gf18e1_inst.sngfifo18e1_n_24 ; + wire \gf18e1_inst.sngfifo18e1_n_25 ; + wire \gf18e1_inst.sngfifo18e1_n_26 ; + wire \gf18e1_inst.sngfifo18e1_n_27 ; + wire \gf18e1_inst.sngfifo18e1_n_28 ; + wire \gf18e1_inst.sngfifo18e1_n_29 ; + wire \gf18e1_inst.sngfifo18e1_n_4 ; + wire \gf18e1_inst.sngfifo18e1_n_7 ; + wire \gf18e1_inst.sngfifo18e1_n_8 ; + wire \gf18e1_inst.sngfifo18e1_n_9 ; + wire m_axi_s2mm_aclk; + wire [11:0]minusOp; + wire [11:0]minusOp_1; + wire out; + wire p_3_out; + wire p_5_out; + wire s2mm_fsync_out_i; + wire s2mm_strm_wready; + wire s_axis_s2mm_aclk; + wire strm_not_finished_no_dwidth; + wire [12:0]\vsize_vid_reg[12] ; + wire [31:8]\NLW_gf18e1_inst.sngfifo18e1_DO_UNCONNECTED ; + wire [3:1]\NLW_gf18e1_inst.sngfifo18e1_DOP_UNCONNECTED ; + wire [11:11]\NLW_gf18e1_inst.sngfifo18e1_RDCOUNT_UNCONNECTED ; + wire [11:11]\NLW_gf18e1_inst.sngfifo18e1_WRCOUNT_UNCONNECTED ; LUT4 #( - .INIT(16'hFFFE)) - \gc1.count_d1[6]_i_4 - (.I0(FULL), - .I1(sig_s_ready_out_reg), - .I2(sig_s_ready_out_reg_0), - .I3(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ), - .O(fifo_full_i)); + .INIT(16'hF044)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[0]_i_1 + (.I0(Q[0]), + .I1(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ), + .I2(\vsize_vid_reg[12] [0]), + .I3(\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ), + .O(D[0])); + LUT4 #( + .INIT(16'hF088)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[10]_i_1 + (.I0(minusOp_1[9]), + .I1(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ), + .I2(\vsize_vid_reg[12] [10]), + .I3(\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ), + .O(D[10])); + LUT4 #( + .INIT(16'hF088)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[11]_i_1 + (.I0(minusOp_1[10]), + .I1(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ), + .I2(\vsize_vid_reg[12] [11]), + .I3(\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ), + .O(D[11])); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFDFFF)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_14 + (.I0(DOUT[8]), + .I1(EMPTY), + .I2(s2mm_strm_wready), + .I3(Q[0]), + .I4(Q[3]), + .I5(Q[4]), + .O(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_14_n_0 )); + LUT4 #( + .INIT(16'hF088)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_3 + (.I0(minusOp_1[11]), + .I1(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ), + .I2(\vsize_vid_reg[12] [12]), + .I3(\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ), + .O(D[12])); + LUT3 #( + .INIT(8'hDF)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_4 + (.I0(s2mm_strm_wready), + .I1(EMPTY), + .I2(DOUT[8]), + .O(\GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_9 + (.I0(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 ), + .I1(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_14_n_0 ), + .I2(Q[6]), + .I3(Q[1]), + .I4(Q[5]), + .I5(Q[2]), + .O(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] )); + LUT4 #( + .INIT(16'hF088)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[1]_i_1 + (.I0(minusOp_1[0]), + .I1(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ), + .I2(\vsize_vid_reg[12] [1]), + .I3(\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ), + .O(D[1])); + LUT4 #( + .INIT(16'hF088)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[2]_i_1 + (.I0(minusOp_1[1]), + .I1(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ), + .I2(\vsize_vid_reg[12] [2]), + .I3(\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ), + .O(D[2])); + LUT4 #( + .INIT(16'hF088)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[3]_i_1 + (.I0(minusOp_1[2]), + .I1(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ), + .I2(\vsize_vid_reg[12] [3]), + .I3(\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ), + .O(D[3])); + LUT4 #( + .INIT(16'hF088)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_1 + (.I0(minusOp_1[3]), + .I1(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ), + .I2(\vsize_vid_reg[12] [4]), + .I3(\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ), + .O(D[4])); + LUT4 #( + .INIT(16'hF088)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[5]_i_1 + (.I0(minusOp_1[4]), + .I1(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ), + .I2(\vsize_vid_reg[12] [5]), + .I3(\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ), + .O(D[5])); + LUT4 #( + .INIT(16'hF088)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[6]_i_1 + (.I0(minusOp_1[5]), + .I1(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ), + .I2(\vsize_vid_reg[12] [6]), + .I3(\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ), + .O(D[6])); + LUT4 #( + .INIT(16'hF088)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[7]_i_1 + (.I0(minusOp_1[6]), + .I1(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ), + .I2(\vsize_vid_reg[12] [7]), + .I3(\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ), + .O(D[7])); + LUT4 #( + .INIT(16'hF088)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_1 + (.I0(minusOp_1[7]), + .I1(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ), + .I2(\vsize_vid_reg[12] [8]), + .I3(\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ), + .O(D[8])); + LUT4 #( + .INIT(16'hF088)) + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[9]_i_1 + (.I0(minusOp_1[8]), + .I1(\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ), + .I2(\vsize_vid_reg[12] [9]), + .I3(\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ), + .O(D[9])); + (* SOFT_HLUTNM = "soft_lutpair85" *) + LUT4 #( + .INIT(16'hFF40)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_i_1 + (.I0(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ), + .I1(DIN[8]), + .I2(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ), + .I3(s2mm_fsync_out_i), + .O(strm_not_finished_no_dwidth)); + (* SOFT_HLUTNM = "soft_lutpair84" *) + LUT2 #( + .INIT(4'h1)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_i_1 + (.I0(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0 ), + .I1(s2mm_fsync_out_i), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg )); + LUT4 #( + .INIT(16'hC0E2)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[0]_i_1 + (.I0(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0 ), + .I1(s2mm_fsync_out_i), + .I2(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] [0]), + .I3(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] ), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] [0])); + LUT4 #( + .INIT(16'hE2C0)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[10]_i_1 + (.I0(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0 ), + .I1(s2mm_fsync_out_i), + .I2(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] [10]), + .I3(minusOp[9]), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] [10])); + LUT4 #( + .INIT(16'hE2C0)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[11]_i_1 + (.I0(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0 ), + .I1(s2mm_fsync_out_i), + .I2(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] [11]), + .I3(minusOp[10]), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] [11])); + LUT4 #( + .INIT(16'hE2C0)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_3 + (.I0(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0 ), + .I1(s2mm_fsync_out_i), + .I2(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] [12]), + .I3(minusOp[11]), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] [12])); + LUT6 #( + .INIT(64'hFFEFFFFFFFFFFFFF)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_5 + (.I0(s2mm_fsync_out_i), + .I1(FULL), + .I2(out), + .I3(p_3_out), + .I4(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ), + .I5(M_VALID), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg )); + (* SOFT_HLUTNM = "soft_lutpair85" *) + LUT4 #( + .INIT(16'hFFDF)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6 + (.I0(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] ), + .I1(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ), + .I2(DIN[8]), + .I3(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0 )); + LUT4 #( + .INIT(16'hE2C0)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[1]_i_1 + (.I0(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0 ), + .I1(s2mm_fsync_out_i), + .I2(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] [1]), + .I3(minusOp[0]), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] [1])); + LUT4 #( + .INIT(16'hE2C0)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[2]_i_1 + (.I0(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0 ), + .I1(s2mm_fsync_out_i), + .I2(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] [2]), + .I3(minusOp[1]), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] [2])); + LUT4 #( + .INIT(16'hE2C0)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[3]_i_1 + (.I0(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0 ), + .I1(s2mm_fsync_out_i), + .I2(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] [3]), + .I3(minusOp[2]), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] [3])); + LUT4 #( + .INIT(16'hE2C0)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_1 + (.I0(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0 ), + .I1(s2mm_fsync_out_i), + .I2(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] [4]), + .I3(minusOp[3]), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] [4])); + LUT4 #( + .INIT(16'hE2C0)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[5]_i_1 + (.I0(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0 ), + .I1(s2mm_fsync_out_i), + .I2(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] [5]), + .I3(minusOp[4]), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] [5])); + LUT4 #( + .INIT(16'hE2C0)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[6]_i_1 + (.I0(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0 ), + .I1(s2mm_fsync_out_i), + .I2(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] [6]), + .I3(minusOp[5]), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] [6])); + (* SOFT_HLUTNM = "soft_lutpair84" *) + LUT4 #( + .INIT(16'hE2C0)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[7]_i_1 + (.I0(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0 ), + .I1(s2mm_fsync_out_i), + .I2(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] [7]), + .I3(minusOp[6]), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] [7])); + LUT4 #( + .INIT(16'hE2C0)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_1 + (.I0(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0 ), + .I1(s2mm_fsync_out_i), + .I2(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] [8]), + .I3(minusOp[7]), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] [8])); + LUT4 #( + .INIT(16'hE2C0)) + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[9]_i_1 + (.I0(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0 ), + .I1(s2mm_fsync_out_i), + .I2(\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] [9]), + .I3(minusOp[8]), + .O(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] [9])); (* CLOCK_DOMAINS = "INDEPENDENT" *) (* box_type = "PRIMITIVE" *) - FIFO36E1 #( + FIFO18E1 #( .ALMOST_EMPTY_OFFSET(13'h000A), .ALMOST_FULL_OFFSET(13'h0097), .DATA_WIDTH(9), .DO_REG(1), - .EN_ECC_READ("FALSE"), - .EN_ECC_WRITE("FALSE"), .EN_SYN("FALSE"), - .FIFO_MODE("FIFO36"), + .FIFO_MODE("FIFO18"), .FIRST_WORD_FALL_THROUGH("TRUE"), - .INIT(72'h000000000000000000), + .INIT(36'h000000000), .IS_RDCLK_INVERTED(1'b0), .IS_RDEN_INVERTED(1'b0), .IS_RSTREG_INVERTED(1'b0), @@ -30681,1228 +75775,3801 @@ module Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_11 .IS_WRCLK_INVERTED(1'b0), .IS_WREN_INVERTED(1'b0), .SIM_DEVICE("7SERIES"), - .SRVAL(72'h000000000000000000)) - \gf36e1_inst.sngfifo36e1 - (.ALMOSTEMPTY(p_18_out), - .ALMOSTFULL(p_17_out), - .DBITERR(p_20_out), - .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dm2linebuf_mm2s_tdata[7:0]}), - .DIP({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dm2linebuf_mm2s_tdata[8]}), - .DO({\NLW_gf36e1_inst.sngfifo36e1_DO_UNCONNECTED [63:8],fifo_dout[7:0]}), - .DOP({\NLW_gf36e1_inst.sngfifo36e1_DOP_UNCONNECTED [7:1],fifo_dout[8]}), - .ECCPARITY(\NLW_gf36e1_inst.sngfifo36e1_ECCPARITY_UNCONNECTED [7:0]), + .SRVAL(36'h000000000)) + \gf18e1_inst.sngfifo18e1 + (.ALMOSTEMPTY(\gf18e1_inst.sngfifo18e1_n_0 ), + .ALMOSTFULL(\gf18e1_inst.sngfifo18e1_n_1 ), + .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,DIN[7:0]}), + .DIP({1'b0,1'b0,1'b0,DIN[8]}), + .DO({\NLW_gf18e1_inst.sngfifo18e1_DO_UNCONNECTED [31:8],DOUT[7:0]}), + .DOP({\NLW_gf18e1_inst.sngfifo18e1_DOP_UNCONNECTED [3:1],DOUT[8]}), .EMPTY(EMPTY), .FULL(FULL), - .INJECTDBITERR(1'b0), - .INJECTSBITERR(1'b0), - .RDCLK(m_axis_mm2s_aclk), - .RDCOUNT({\NLW_gf36e1_inst.sngfifo36e1_RDCOUNT_UNCONNECTED [12],\gf36e1_inst.sngfifo36e1_n_17 ,\gf36e1_inst.sngfifo36e1_n_18 ,\gf36e1_inst.sngfifo36e1_n_19 ,\gf36e1_inst.sngfifo36e1_n_20 ,\gf36e1_inst.sngfifo36e1_n_21 ,\gf36e1_inst.sngfifo36e1_n_22 ,\gf36e1_inst.sngfifo36e1_n_23 ,\gf36e1_inst.sngfifo36e1_n_24 ,\gf36e1_inst.sngfifo36e1_n_25 ,\gf36e1_inst.sngfifo36e1_n_26 ,\gf36e1_inst.sngfifo36e1_n_27 ,\gf36e1_inst.sngfifo36e1_n_28 }), + .RDCLK(m_axi_s2mm_aclk), + .RDCOUNT({\NLW_gf18e1_inst.sngfifo18e1_RDCOUNT_UNCONNECTED [11],\gf18e1_inst.sngfifo18e1_n_7 ,\gf18e1_inst.sngfifo18e1_n_8 ,\gf18e1_inst.sngfifo18e1_n_9 ,\gf18e1_inst.sngfifo18e1_n_10 ,\gf18e1_inst.sngfifo18e1_n_11 ,\gf18e1_inst.sngfifo18e1_n_12 ,\gf18e1_inst.sngfifo18e1_n_13 ,\gf18e1_inst.sngfifo18e1_n_14 ,\gf18e1_inst.sngfifo18e1_n_15 ,\gf18e1_inst.sngfifo18e1_n_16 ,\gf18e1_inst.sngfifo18e1_n_17 }), .RDEN(RD_EN), - .RDERR(\gf36e1_inst.sngfifo36e1_n_14 ), + .RDERR(\gf18e1_inst.sngfifo18e1_n_4 ), .REGCE(1'b0), .RST(RST), .RSTREG(1'b0), - .SBITERR(p_19_out), - .WRCLK(m_axi_mm2s_aclk), - .WRCOUNT({\NLW_gf36e1_inst.sngfifo36e1_WRCOUNT_UNCONNECTED [12],\gf36e1_inst.sngfifo36e1_n_30 ,\gf36e1_inst.sngfifo36e1_n_31 ,\gf36e1_inst.sngfifo36e1_n_32 ,\gf36e1_inst.sngfifo36e1_n_33 ,\gf36e1_inst.sngfifo36e1_n_34 ,\gf36e1_inst.sngfifo36e1_n_35 ,\gf36e1_inst.sngfifo36e1_n_36 ,\gf36e1_inst.sngfifo36e1_n_37 ,\gf36e1_inst.sngfifo36e1_n_38 ,\gf36e1_inst.sngfifo36e1_n_39 ,\gf36e1_inst.sngfifo36e1_n_40 ,\gf36e1_inst.sngfifo36e1_n_41 }), - .WREN(WR_EN), - .WRERR(\gf36e1_inst.sngfifo36e1_n_15 )); + .WRCLK(s_axis_s2mm_aclk), + .WRCOUNT({\NLW_gf18e1_inst.sngfifo18e1_WRCOUNT_UNCONNECTED [11],\gf18e1_inst.sngfifo18e1_n_19 ,\gf18e1_inst.sngfifo18e1_n_20 ,\gf18e1_inst.sngfifo18e1_n_21 ,\gf18e1_inst.sngfifo18e1_n_22 ,\gf18e1_inst.sngfifo18e1_n_23 ,\gf18e1_inst.sngfifo18e1_n_24 ,\gf18e1_inst.sngfifo18e1_n_25 ,\gf18e1_inst.sngfifo18e1_n_26 ,\gf18e1_inst.sngfifo18e1_n_27 ,\gf18e1_inst.sngfifo18e1_n_28 ,\gf18e1_inst.sngfifo18e1_n_29 }), + .WREN(fifo_wren), + .WRERR(p_5_out)); + LUT6 #( + .INIT(64'h0000000000400000)) + \gf18e1_inst.sngfifo18e1_i_3 + (.I0(FULL), + .I1(M_VALID), + .I2(\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ), + .I3(s2mm_fsync_out_i), + .I4(out), + .I5(p_3_out), + .O(fifo_wren)); +endmodule + +(* ORIG_REF_NAME = "builtin_top_v6" *) +module Arty_Z7_20_axi_vdma_0_0_builtin_top_v6 + (sig_m_valid_out_reg, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg , + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg , + FULL, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 , + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 , + fifo_dout, + out, + lsig_0ffset_cntr, + mm2s_prmry_resetn, + mm2s_halt, + p_24_out, + hold_ff_q_reg, + DIN, + m_axis_mm2s_aclk, + RST, + m_axi_mm2s_aclk, + WR_EN, + dm2linebuf_mm2s_tdata); + output sig_m_valid_out_reg; + output \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; + output FULL; + output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ; + output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 ; + output [33:0]fifo_dout; + input out; + input lsig_0ffset_cntr; + input mm2s_prmry_resetn; + input mm2s_halt; + input p_24_out; + input hold_ff_q_reg; + input [15:0]DIN; + input m_axis_mm2s_aclk; + input RST; + input m_axi_mm2s_aclk; + input WR_EN; + input [17:0]dm2linebuf_mm2s_tdata; + + wire [15:0]DIN; + wire FULL; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 ; + wire \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + wire RST; + wire WR_EN; + wire [17:0]dm2linebuf_mm2s_tdata; + wire [33:0]fifo_dout; + wire hold_ff_q_reg; + wire lsig_0ffset_cntr; + wire m_axi_mm2s_aclk; + wire m_axis_mm2s_aclk; + wire mm2s_halt; + wire mm2s_prmry_resetn; + wire out; + wire p_24_out; + wire p_4_out; + wire p_9_out; + wire rd_tmp; + wire sig_m_valid_out_reg; + + Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6 \gextw[1].gnll_fifo.inst_extd + (.EMPTY(p_9_out), + .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ), + .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 (p_4_out), + .RD_EN(rd_tmp), + .RST(RST), + .WR_EN(WR_EN), + .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), + .fifo_dout(fifo_dout[17:0]), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .m_axis_mm2s_aclk(m_axis_mm2s_aclk), + .sig_m_valid_out_reg(sig_m_valid_out_reg)); + Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_40 \gextw[2].gnll_fifo.inst_extd + (.DIN(DIN), + .EMPTY(p_4_out), + .FULL(FULL), + .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ), + .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 ), + .\INCLUDE_UNPACKING.lsig_cmd_loaded_reg (\INCLUDE_UNPACKING.lsig_cmd_loaded_reg ), + .RD_EN(rd_tmp), + .RST(RST), + .WR_EN(WR_EN), + .fifo_dout(fifo_dout[33:18]), + .hold_ff_q_reg(hold_ff_q_reg), + .lsig_0ffset_cntr(lsig_0ffset_cntr), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .m_axis_mm2s_aclk(m_axis_mm2s_aclk), + .mm2s_halt(mm2s_halt), + .mm2s_prmry_resetn(mm2s_prmry_resetn), + .out(out), + .p_24_out(p_24_out), + .sig_s_ready_out_reg(p_9_out), + .sig_s_ready_out_reg_0(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 )); +endmodule + +(* ORIG_REF_NAME = "builtin_top_v6" *) +module Arty_Z7_20_axi_vdma_0_0_builtin_top_v6__parameterized0 + (FULL, + D, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] , + DOUT, + EMPTY, + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg , + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg , + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg , + strm_not_finished_no_dwidth, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] , + M_VALID, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 , + s2mm_fsync_out_i, + out, + p_3_out, + Q, + \vsize_vid_reg[12] , + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out , + minusOp_1, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 , + s2mm_strm_wready, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] , + DIN, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] , + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] , + minusOp, + m_axi_s2mm_aclk, + RD_EN, + RST, + s_axis_s2mm_aclk); + output FULL; + output [12:0]D; + output \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ; + output [8:0]DOUT; + output EMPTY; + output \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg ; + output \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg ; + output \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ; + output strm_not_finished_no_dwidth; + output [12:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] ; + input M_VALID; + input \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ; + input s2mm_fsync_out_i; + input out; + input p_3_out; + input [6:0]Q; + input [12:0]\vsize_vid_reg[12] ; + input \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ; + input [11:0]minusOp_1; + input \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 ; + input s2mm_strm_wready; + input [0:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] ; + input [8:0]DIN; + input \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ; + input [12:0]\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] ; + input [11:0]minusOp; + input m_axi_s2mm_aclk; + input RD_EN; + input RST; + input s_axis_s2mm_aclk; + + wire [12:0]D; + wire [8:0]DIN; + wire [8:0]DOUT; + wire EMPTY; + wire FULL; + wire \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ; + wire [12:0]\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg ; + wire [0:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] ; + wire [12:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ; + wire M_VALID; + wire [6:0]Q; + wire RD_EN; + wire RST; + wire m_axi_s2mm_aclk; + wire [11:0]minusOp; + wire [11:0]minusOp_1; + wire out; + wire p_3_out; + wire s2mm_fsync_out_i; + wire s2mm_strm_wready; + wire s_axis_s2mm_aclk; + wire strm_not_finished_no_dwidth; + wire [12:0]\vsize_vid_reg[12] ; + + Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6__parameterized0 \gextw[1].gnll_fifo.inst_extd + (.D(D), + .DIN(DIN), + .DOUT(DOUT), + .EMPTY(EMPTY), + .FULL(FULL), + .\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out (\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] (\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] (\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 (\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg (\GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ), + .M_VALID(M_VALID), + .Q(Q), + .RD_EN(RD_EN), + .RST(RST), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .minusOp(minusOp), + .minusOp_1(minusOp_1), + .out(out), + .p_3_out(p_3_out), + .s2mm_fsync_out_i(s2mm_fsync_out_i), + .s2mm_strm_wready(s2mm_strm_wready), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk), + .strm_not_finished_no_dwidth(strm_not_finished_no_dwidth), + .\vsize_vid_reg[12] (\vsize_vid_reg[12] )); +endmodule + +(* ORIG_REF_NAME = "dc_ss" *) +module Arty_Z7_20_axi_vdma_0_0_dc_ss + (sig_ok_to_post_rd_addr_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_posted_to_axi_2_reg, + ram_empty_fb_i_reg, + \sig_token_cntr_reg[0] , + \sig_token_cntr_reg[3] , + sig_posted_to_axi_2_reg_0, + SR, + ram_full_i_reg, + m_axi_mm2s_aclk); + output sig_ok_to_post_rd_addr_reg; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_posted_to_axi_2_reg; + input ram_empty_fb_i_reg; + input \sig_token_cntr_reg[0] ; + input [3:0]\sig_token_cntr_reg[3] ; + input sig_posted_to_axi_2_reg_0; + input [0:0]SR; + input [0:0]ram_full_i_reg; + input m_axi_mm2s_aclk; + + wire [0:0]SR; + wire m_axi_mm2s_aclk; + wire ram_empty_fb_i_reg; + wire [0:0]ram_full_i_reg; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_ok_to_post_rd_addr_reg; + wire sig_posted_to_axi_2_reg; + wire sig_posted_to_axi_2_reg_0; + wire \sig_token_cntr_reg[0] ; + wire [3:0]\sig_token_cntr_reg[3] ; + + Arty_Z7_20_axi_vdma_0_0_updn_cntr \gsym_dc.dc + (.SR(SR), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_full_i_reg(ram_full_i_reg), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_ok_to_post_rd_addr_reg(sig_ok_to_post_rd_addr_reg), + .sig_posted_to_axi_2_reg(sig_posted_to_axi_2_reg), + .sig_posted_to_axi_2_reg_0(sig_posted_to_axi_2_reg_0), + .\sig_token_cntr_reg[0] (\sig_token_cntr_reg[0] ), + .\sig_token_cntr_reg[3] (\sig_token_cntr_reg[3] )); +endmodule + +(* ORIG_REF_NAME = "dc_ss" *) +module Arty_Z7_20_axi_vdma_0_0_dc_ss__parameterized0 + (sig_ibtt2dre_tready, + lsig_packer_full, + ram_full_i_reg, + ram_full_i_reg_0, + E, + ram_full_fb_i_reg, + sig_clr_dbc_reg_reg, + sig_stream_rst, + m_axi_s2mm_aclk); + output sig_ibtt2dre_tready; + input lsig_packer_full; + input ram_full_i_reg; + input ram_full_i_reg_0; + input [0:0]E; + input ram_full_fb_i_reg; + input sig_clr_dbc_reg_reg; + input sig_stream_rst; + input m_axi_s2mm_aclk; + + wire [0:0]E; + wire lsig_packer_full; + wire m_axi_s2mm_aclk; + wire ram_full_fb_i_reg; + wire ram_full_i_reg; + wire ram_full_i_reg_0; + wire sig_clr_dbc_reg_reg; + wire sig_ibtt2dre_tready; + wire sig_stream_rst; + + Arty_Z7_20_axi_vdma_0_0_updn_cntr__parameterized0 \gsym_dc.dc + (.E(E), + .lsig_packer_full(lsig_packer_full), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .ram_full_i_reg(ram_full_i_reg), + .ram_full_i_reg_0(ram_full_i_reg_0), + .sig_clr_dbc_reg_reg(sig_clr_dbc_reg_reg), + .sig_ibtt2dre_tready(sig_ibtt2dre_tready), + .sig_stream_rst(sig_stream_rst)); +endmodule + +(* ORIG_REF_NAME = "dmem" *) +module Arty_Z7_20_axi_vdma_0_0_dmem + (D, + sig_xfer_is_seq_reg_reg, + \sig_child_addr_cntr_lsh_reg[11] , + S, + \sig_xfer_len_reg_reg[4] , + \sig_xfer_len_reg_reg[5] , + sig_xfer_is_seq_reg_reg_0, + sig_xfer_cmd_cmplt_reg0, + sig_csm_state_ns1, + O, + CO, + \sig_child_addr_cntr_lsh_reg[7] , + sig_adjusted_addr_incr, + sig_csm_pop_child_cmd, + sig_child_qual_first_of_2, + sig_child_qual_error_reg, + \gpr1.dout_i_reg[3]_0 , + \gpr1.dout_i_reg[7]_0 , + sig_child_addr_cntr_lsh_reg, + sig_stream_rst, + E, + p_0_out, + m_axi_s2mm_aclk); + output [2:0]D; + output [9:0]sig_xfer_is_seq_reg_reg; + output [0:0]\sig_child_addr_cntr_lsh_reg[11] ; + output [3:0]S; + output [3:0]\sig_xfer_len_reg_reg[4] ; + output [0:0]\sig_xfer_len_reg_reg[5] ; + output sig_xfer_is_seq_reg_reg_0; + output sig_xfer_cmd_cmplt_reg0; + output sig_csm_state_ns1; + output [3:0]O; + output [0:0]CO; + output [3:0]\sig_child_addr_cntr_lsh_reg[7] ; + input [8:0]sig_adjusted_addr_incr; + input sig_csm_pop_child_cmd; + input sig_child_qual_first_of_2; + input sig_child_qual_error_reg; + input [3:0]\gpr1.dout_i_reg[3]_0 ; + input [3:0]\gpr1.dout_i_reg[7]_0 ; + input [2:0]sig_child_addr_cntr_lsh_reg; + input sig_stream_rst; + input [0:0]E; + input [10:0]p_0_out; + input m_axi_s2mm_aclk; + + wire [0:0]CO; + wire [2:0]D; + wire [0:0]E; + wire [3:0]O; + wire [3:0]S; + wire [3:0]\gpr1.dout_i_reg[3]_0 ; + wire [3:0]\gpr1.dout_i_reg[7]_0 ; + wire m_axi_s2mm_aclk; + wire [10:0]p_0_out; + wire [8:0]sig_adjusted_addr_incr; + wire \sig_child_addr_cntr_lsh[0]_i_3_n_0 ; + wire \sig_child_addr_cntr_lsh[0]_i_4_n_0 ; + wire \sig_child_addr_cntr_lsh[0]_i_5_n_0 ; + wire \sig_child_addr_cntr_lsh[0]_i_6_n_0 ; + wire \sig_child_addr_cntr_lsh[4]_i_2_n_0 ; + wire \sig_child_addr_cntr_lsh[4]_i_3_n_0 ; + wire \sig_child_addr_cntr_lsh[4]_i_4_n_0 ; + wire \sig_child_addr_cntr_lsh[4]_i_5_n_0 ; + wire [2:0]sig_child_addr_cntr_lsh_reg; + wire \sig_child_addr_cntr_lsh_reg[0]_i_2_n_0 ; + wire \sig_child_addr_cntr_lsh_reg[0]_i_2_n_1 ; + wire \sig_child_addr_cntr_lsh_reg[0]_i_2_n_2 ; + wire \sig_child_addr_cntr_lsh_reg[0]_i_2_n_3 ; + wire [0:0]\sig_child_addr_cntr_lsh_reg[11] ; + wire \sig_child_addr_cntr_lsh_reg[4]_i_1_n_1 ; + wire \sig_child_addr_cntr_lsh_reg[4]_i_1_n_2 ; + wire \sig_child_addr_cntr_lsh_reg[4]_i_1_n_3 ; + wire [3:0]\sig_child_addr_cntr_lsh_reg[7] ; + wire sig_child_qual_error_reg; + wire sig_child_qual_first_of_2; + wire sig_csm_pop_child_cmd; + wire sig_csm_state_ns1; + wire sig_sf2pcc_packet_eop; + wire sig_stream_rst; + wire sig_xfer_cmd_cmplt_reg0; + wire [9:0]sig_xfer_is_seq_reg_reg; + wire sig_xfer_is_seq_reg_reg_0; + wire \sig_xfer_len_reg[5]_i_2_n_0 ; + wire [3:0]\sig_xfer_len_reg_reg[4] ; + wire [0:0]\sig_xfer_len_reg_reg[5] ; + + (* SOFT_HLUTNM = "soft_lutpair178" *) + LUT3 #( + .INIT(8'hA2)) + \FSM_sequential_sig_csm_state[2]_i_2 + (.I0(sig_xfer_is_seq_reg_reg[9]), + .I1(sig_child_qual_first_of_2), + .I2(sig_sf2pcc_packet_eop), + .O(sig_csm_state_ns1)); + FDRE #( + .INIT(1'b0)) + \gpr1.dout_i_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(p_0_out[0]), + .Q(sig_xfer_is_seq_reg_reg[0]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gpr1.dout_i_reg[10] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(p_0_out[10]), + .Q(sig_sf2pcc_packet_eop), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gpr1.dout_i_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(p_0_out[1]), + .Q(sig_xfer_is_seq_reg_reg[1]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gpr1.dout_i_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(p_0_out[2]), + .Q(sig_xfer_is_seq_reg_reg[2]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gpr1.dout_i_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(p_0_out[3]), + .Q(sig_xfer_is_seq_reg_reg[3]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gpr1.dout_i_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(p_0_out[4]), + .Q(sig_xfer_is_seq_reg_reg[4]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gpr1.dout_i_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(p_0_out[5]), + .Q(sig_xfer_is_seq_reg_reg[5]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gpr1.dout_i_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(p_0_out[6]), + .Q(sig_xfer_is_seq_reg_reg[6]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gpr1.dout_i_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(p_0_out[7]), + .Q(sig_xfer_is_seq_reg_reg[7]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gpr1.dout_i_reg[8] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(p_0_out[8]), + .Q(sig_xfer_is_seq_reg_reg[8]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gpr1.dout_i_reg[9] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(p_0_out[9]), + .Q(sig_xfer_is_seq_reg_reg[9]), + .R(sig_stream_rst)); + LUT1 #( + .INIT(2'h2)) + sig_byte_change_minus1_carry__0_i_1 + (.I0(sig_xfer_is_seq_reg_reg[7]), + .O(\sig_xfer_len_reg_reg[4] [3])); + LUT1 #( + .INIT(2'h2)) + sig_byte_change_minus1_carry__0_i_2 + (.I0(sig_xfer_is_seq_reg_reg[6]), + .O(\sig_xfer_len_reg_reg[4] [2])); + LUT1 #( + .INIT(2'h2)) + sig_byte_change_minus1_carry__0_i_3 + (.I0(sig_xfer_is_seq_reg_reg[5]), + .O(\sig_xfer_len_reg_reg[4] [1])); + LUT1 #( + .INIT(2'h2)) + sig_byte_change_minus1_carry__0_i_4 + (.I0(sig_xfer_is_seq_reg_reg[4]), + .O(\sig_xfer_len_reg_reg[4] [0])); + LUT1 #( + .INIT(2'h2)) + sig_byte_change_minus1_carry__1_i_1 + (.I0(sig_xfer_is_seq_reg_reg[8]), + .O(\sig_xfer_len_reg_reg[5] )); + LUT1 #( + .INIT(2'h2)) + sig_byte_change_minus1_carry_i_1 + (.I0(sig_xfer_is_seq_reg_reg[3]), + .O(S[3])); + LUT2 #( + .INIT(4'h6)) + sig_byte_change_minus1_carry_i_2 + (.I0(sig_xfer_is_seq_reg_reg[2]), + .I1(sig_child_addr_cntr_lsh_reg[2]), + .O(S[2])); + LUT2 #( + .INIT(4'h6)) + sig_byte_change_minus1_carry_i_3 + (.I0(sig_xfer_is_seq_reg_reg[1]), + .I1(sig_child_addr_cntr_lsh_reg[1]), + .O(S[1])); + LUT2 #( + .INIT(4'h6)) + sig_byte_change_minus1_carry_i_4 + (.I0(sig_xfer_is_seq_reg_reg[0]), + .I1(sig_child_addr_cntr_lsh_reg[0]), + .O(S[0])); + LUT2 #( + .INIT(4'h2)) + \sig_child_addr_cntr_lsh[0]_i_3 + (.I0(sig_xfer_is_seq_reg_reg[3]), + .I1(sig_csm_pop_child_cmd), + .O(\sig_child_addr_cntr_lsh[0]_i_3_n_0 )); + LUT2 #( + .INIT(4'h2)) + \sig_child_addr_cntr_lsh[0]_i_4 + (.I0(sig_xfer_is_seq_reg_reg[2]), + .I1(sig_csm_pop_child_cmd), + .O(\sig_child_addr_cntr_lsh[0]_i_4_n_0 )); + LUT2 #( + .INIT(4'h2)) + \sig_child_addr_cntr_lsh[0]_i_5 + (.I0(sig_xfer_is_seq_reg_reg[1]), + .I1(sig_csm_pop_child_cmd), + .O(\sig_child_addr_cntr_lsh[0]_i_5_n_0 )); + LUT2 #( + .INIT(4'h2)) + \sig_child_addr_cntr_lsh[0]_i_6 + (.I0(sig_xfer_is_seq_reg_reg[0]), + .I1(sig_csm_pop_child_cmd), + .O(\sig_child_addr_cntr_lsh[0]_i_6_n_0 )); + LUT2 #( + .INIT(4'h2)) + \sig_child_addr_cntr_lsh[4]_i_2 + (.I0(sig_xfer_is_seq_reg_reg[7]), + .I1(sig_csm_pop_child_cmd), + .O(\sig_child_addr_cntr_lsh[4]_i_2_n_0 )); + LUT2 #( + .INIT(4'h2)) + \sig_child_addr_cntr_lsh[4]_i_3 + (.I0(sig_xfer_is_seq_reg_reg[6]), + .I1(sig_csm_pop_child_cmd), + .O(\sig_child_addr_cntr_lsh[4]_i_3_n_0 )); + LUT2 #( + .INIT(4'h2)) + \sig_child_addr_cntr_lsh[4]_i_4 + (.I0(sig_xfer_is_seq_reg_reg[5]), + .I1(sig_csm_pop_child_cmd), + .O(\sig_child_addr_cntr_lsh[4]_i_4_n_0 )); + LUT2 #( + .INIT(4'h2)) + \sig_child_addr_cntr_lsh[4]_i_5 + (.I0(sig_xfer_is_seq_reg_reg[4]), + .I1(sig_csm_pop_child_cmd), + .O(\sig_child_addr_cntr_lsh[4]_i_5_n_0 )); + LUT2 #( + .INIT(4'h2)) + \sig_child_addr_cntr_lsh[8]_i_2 + (.I0(sig_xfer_is_seq_reg_reg[8]), + .I1(sig_csm_pop_child_cmd), + .O(\sig_child_addr_cntr_lsh_reg[11] )); + CARRY4 \sig_child_addr_cntr_lsh_reg[0]_i_2 + (.CI(1'b0), + .CO({\sig_child_addr_cntr_lsh_reg[0]_i_2_n_0 ,\sig_child_addr_cntr_lsh_reg[0]_i_2_n_1 ,\sig_child_addr_cntr_lsh_reg[0]_i_2_n_2 ,\sig_child_addr_cntr_lsh_reg[0]_i_2_n_3 }), + .CYINIT(1'b0), + .DI({\sig_child_addr_cntr_lsh[0]_i_3_n_0 ,\sig_child_addr_cntr_lsh[0]_i_4_n_0 ,\sig_child_addr_cntr_lsh[0]_i_5_n_0 ,\sig_child_addr_cntr_lsh[0]_i_6_n_0 }), + .O(O), + .S(\gpr1.dout_i_reg[3]_0 )); + CARRY4 \sig_child_addr_cntr_lsh_reg[4]_i_1 + (.CI(\sig_child_addr_cntr_lsh_reg[0]_i_2_n_0 ), + .CO({CO,\sig_child_addr_cntr_lsh_reg[4]_i_1_n_1 ,\sig_child_addr_cntr_lsh_reg[4]_i_1_n_2 ,\sig_child_addr_cntr_lsh_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({\sig_child_addr_cntr_lsh[4]_i_2_n_0 ,\sig_child_addr_cntr_lsh[4]_i_3_n_0 ,\sig_child_addr_cntr_lsh[4]_i_4_n_0 ,\sig_child_addr_cntr_lsh[4]_i_5_n_0 }), + .O(\sig_child_addr_cntr_lsh_reg[7] ), + .S(\gpr1.dout_i_reg[7]_0 )); + (* SOFT_HLUTNM = "soft_lutpair178" *) LUT4 #( - .INIT(16'hFFFE)) - sig_s_ready_dup_i_2 - (.I0(EMPTY), - .I1(\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ), - .I2(sig_s_ready_out_reg_1), - .I3(sig_s_ready_out_reg_2), - .O(sig_m_valid_out_reg)); + .INIT(16'hFFB0)) + sig_xfer_cmd_cmplt_reg_i_1 + (.I0(sig_sf2pcc_packet_eop), + .I1(sig_child_qual_first_of_2), + .I2(sig_xfer_is_seq_reg_reg[9]), + .I3(sig_child_qual_error_reg), + .O(sig_xfer_cmd_cmplt_reg0)); + LUT3 #( + .INIT(8'h4F)) + sig_xfer_is_seq_reg_i_1 + (.I0(sig_sf2pcc_packet_eop), + .I1(sig_child_qual_first_of_2), + .I2(sig_xfer_is_seq_reg_reg[9]), + .O(sig_xfer_is_seq_reg_reg_0)); + LUT2 #( + .INIT(4'h9)) + \sig_xfer_len_reg[3]_i_1 + (.I0(\sig_xfer_len_reg[5]_i_2_n_0 ), + .I1(sig_adjusted_addr_incr[6]), + .O(D[0])); + (* SOFT_HLUTNM = "soft_lutpair179" *) + LUT3 #( + .INIT(8'hE1)) + \sig_xfer_len_reg[4]_i_1 + (.I0(sig_adjusted_addr_incr[6]), + .I1(\sig_xfer_len_reg[5]_i_2_n_0 ), + .I2(sig_adjusted_addr_incr[7]), + .O(D[1])); + (* SOFT_HLUTNM = "soft_lutpair179" *) + LUT4 #( + .INIT(16'hFE01)) + \sig_xfer_len_reg[5]_i_1 + (.I0(sig_adjusted_addr_incr[7]), + .I1(\sig_xfer_len_reg[5]_i_2_n_0 ), + .I2(sig_adjusted_addr_incr[6]), + .I3(sig_adjusted_addr_incr[8]), + .O(D[2])); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \sig_xfer_len_reg[5]_i_2 + (.I0(sig_adjusted_addr_incr[4]), + .I1(sig_adjusted_addr_incr[2]), + .I2(sig_adjusted_addr_incr[0]), + .I3(sig_adjusted_addr_incr[1]), + .I4(sig_adjusted_addr_incr[3]), + .I5(sig_adjusted_addr_incr[5]), + .O(\sig_xfer_len_reg[5]_i_2_n_0 )); +endmodule + +(* ORIG_REF_NAME = "fifo_generator_ramfifo" *) +module Arty_Z7_20_axi_vdma_0_0_fifo_generator_ramfifo + (DOBDO, + out, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram , + sig_ok_to_post_rd_addr_reg, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg , + hold_ff_q_reg, + \gc1.count_reg[7] , + \INFERRED_GEN.cnt_i_reg[2] , + DIN, + \sig_user_skid_reg_reg[0] , + dm2linebuf_mm2s_tdata, + m_axi_mm2s_aclk, + E, + SR, + m_axi_mm2s_rdata, + DIBDI, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_posted_to_axi_2_reg, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , + Q, + lsig_cmd_loaded, + hold_ff_q, + ram_full_i_reg, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 , + \sig_token_cntr_reg[0] , + \sig_token_cntr_reg[3] , + ram_full_i_reg_0); + output [0:0]DOBDO; + output out; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; + output sig_ok_to_post_rd_addr_reg; + output \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + output hold_ff_q_reg; + output \gc1.count_reg[7] ; + output \INFERRED_GEN.cnt_i_reg[2] ; + output [0:0]DIN; + output \sig_user_skid_reg_reg[0] ; + output [31:0]dm2linebuf_mm2s_tdata; + input m_axi_mm2s_aclk; + input [0:0]E; + input [0:0]SR; + input [63:0]m_axi_mm2s_rdata; + input [1:0]DIBDI; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_posted_to_axi_2_reg; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + input [0:0]Q; + input lsig_cmd_loaded; + input hold_ff_q; + input ram_full_i_reg; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; + input \sig_token_cntr_reg[0] ; + input [3:0]\sig_token_cntr_reg[3] ; + input [0:0]ram_full_i_reg_0; + + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; + wire [1:0]DIBDI; + wire [0:0]DIN; + wire [0:0]DOBDO; + wire [0:0]E; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; + wire \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + wire \INFERRED_GEN.cnt_i_reg[2] ; + wire [0:0]Q; + wire [0:0]SR; + wire [31:0]dm2linebuf_mm2s_tdata; + wire \gc1.count_reg[7] ; + wire \gntv_or_sync_fifo.gl0.rd_n_0 ; + wire \gntv_or_sync_fifo.gl0.rd_n_4 ; + wire \gntv_or_sync_fifo.gl0.rd_n_5 ; + wire \gntv_or_sync_fifo.gl0.rd_n_6 ; + wire \gntv_or_sync_fifo.gl0.wr_n_2 ; + wire hold_ff_q; + wire hold_ff_q_reg; + wire lsig_cmd_loaded; + wire m_axi_mm2s_aclk; + wire [63:0]m_axi_mm2s_rdata; + wire out; + wire [7:0]p_0_out; + wire [7:0]p_11_out; + wire [7:0]p_12_out; + wire ram_full_i_reg; + wire [0:0]ram_full_i_reg_0; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_ok_to_post_rd_addr_reg; + wire sig_posted_to_axi_2_reg; + wire \sig_token_cntr_reg[0] ; + wire [3:0]\sig_token_cntr_reg[3] ; + wire \sig_user_skid_reg_reg[0] ; + + Arty_Z7_20_axi_vdma_0_0_rd_logic_30 \gntv_or_sync_fifo.gl0.rd + (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\gntv_or_sync_fifo.gl0.rd_n_4 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0 (\gntv_or_sync_fifo.gl0.rd_n_5 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_1 (p_0_out), + .E(\gc1.count_reg[7] ), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), + .Q(p_11_out), + .SR(SR), + .\gcc0.gc0.count_reg[7] (p_12_out), + .hold_ff_q(hold_ff_q), + .hold_ff_q_reg(hold_ff_q_reg), + .lsig_cmd_loaded(lsig_cmd_loaded), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .out(\gntv_or_sync_fifo.gl0.rd_n_0 ), + .ram_full_fb_i_reg(out), + .ram_full_i_reg(\gntv_or_sync_fifo.gl0.rd_n_6 ), + .ram_full_i_reg_0(ram_full_i_reg), + .ram_full_i_reg_1(E), + .ram_full_i_reg_2(ram_full_i_reg_0), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_ok_to_post_rd_addr_reg(sig_ok_to_post_rd_addr_reg), + .sig_posted_to_axi_2_reg(sig_posted_to_axi_2_reg), + .sig_posted_to_axi_2_reg_0(\gntv_or_sync_fifo.gl0.wr_n_2 ), + .\sig_token_cntr_reg[0] (\sig_token_cntr_reg[0] ), + .\sig_token_cntr_reg[3] (\sig_token_cntr_reg[3] ), + .\sig_user_skid_reg_reg[0] (\sig_user_skid_reg_reg[0] )); + Arty_Z7_20_axi_vdma_0_0_wr_logic_31 \gntv_or_sync_fifo.gl0.wr + (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0 (p_11_out), + .E(E), + .Q(p_12_out), + .SR(SR), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .out(out), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0(\gntv_or_sync_fifo.gl0.rd_n_6 ), + .sig_ok_to_post_rd_addr_reg(\gntv_or_sync_fifo.gl0.wr_n_2 ), + .sig_posted_to_axi_2_reg(sig_posted_to_axi_2_reg), + .\sig_token_cntr_reg[3] (\sig_token_cntr_reg[3] )); + Arty_Z7_20_axi_vdma_0_0_memory \gntv_or_sync_fifo.mem + (.DIBDI(DIBDI), + .DIN(DIN), + .DOBDO(DOBDO), + .E(E), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .\INCLUDE_UNPACKING.lsig_cmd_loaded_reg (\INCLUDE_UNPACKING.lsig_cmd_loaded_reg ), + .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ), + .Q(Q), + .SR(SR), + .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), + .\gc1.count_d2_reg[7] (p_0_out), + .\gcc0.gc0.count_d1_reg[7] (p_11_out), + .\gpregsm1.curr_fwft_state_reg[0] (\gntv_or_sync_fifo.gl0.rd_n_5 ), + .hold_ff_q(hold_ff_q), + .lsig_cmd_loaded(lsig_cmd_loaded), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .m_axi_mm2s_rdata(m_axi_mm2s_rdata), + .out(\gntv_or_sync_fifo.gl0.rd_n_0 ), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0(\gntv_or_sync_fifo.gl0.rd_n_4 )); +endmodule + +(* ORIG_REF_NAME = "fifo_generator_ramfifo" *) +module Arty_Z7_20_axi_vdma_0_0_fifo_generator_ramfifo__parameterized0 + (hold_ff_q_reg, + D, + sig_xfer_is_seq_reg_reg, + \sig_child_addr_cntr_lsh_reg[11] , + E, + S, + \sig_xfer_len_reg_reg[4] , + \sig_xfer_len_reg_reg[5] , + sig_xfer_is_seq_reg_reg_0, + sig_xfer_cmd_cmplt_reg0, + sig_sf2pcc_xfer_valid, + sig_ibtt2dre_tready, + sig_csm_state_ns1, + \gpr1.dout_i_reg[1] , + \gpr1.dout_i_reg[1]_0 , + O, + CO, + \sig_child_addr_cntr_lsh_reg[7] , + sig_stream_rst, + m_axi_s2mm_aclk, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + p_32_out, + hold_ff_q, + sig_adjusted_addr_incr, + sig_clr_dbc_reg_reg, + sig_csm_pop_child_cmd, + sig_child_qual_first_of_2, + sig_child_qual_error_reg, + lsig_packer_full, + ram_full_i_reg, + \gpr1.dout_i_reg[3] , + \gpr1.dout_i_reg[7] , + sig_child_addr_cntr_lsh_reg, + p_0_out); + output hold_ff_q_reg; + output [2:0]D; + output [9:0]sig_xfer_is_seq_reg_reg; + output [0:0]\sig_child_addr_cntr_lsh_reg[11] ; + output [0:0]E; + output [3:0]S; + output [3:0]\sig_xfer_len_reg_reg[4] ; + output [0:0]\sig_xfer_len_reg_reg[5] ; + output sig_xfer_is_seq_reg_reg_0; + output sig_xfer_cmd_cmplt_reg0; + output sig_sf2pcc_xfer_valid; + output sig_ibtt2dre_tready; + output sig_csm_state_ns1; + output [2:0]\gpr1.dout_i_reg[1] ; + output [2:0]\gpr1.dout_i_reg[1]_0 ; + output [3:0]O; + output [0:0]CO; + output [3:0]\sig_child_addr_cntr_lsh_reg[7] ; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input p_32_out; + input hold_ff_q; + input [8:0]sig_adjusted_addr_incr; + input sig_clr_dbc_reg_reg; + input sig_csm_pop_child_cmd; + input sig_child_qual_first_of_2; + input sig_child_qual_error_reg; + input lsig_packer_full; + input ram_full_i_reg; + input [3:0]\gpr1.dout_i_reg[3] ; + input [3:0]\gpr1.dout_i_reg[7] ; + input [2:0]sig_child_addr_cntr_lsh_reg; + input [10:0]p_0_out; + + wire [0:0]CO; + wire [2:0]D; + wire [0:0]E; + wire [3:0]O; + wire [3:0]S; + wire \gntv_or_sync_fifo.gl0.rd_n_2 ; + wire \gntv_or_sync_fifo.gl0.rd_n_3 ; + wire \gntv_or_sync_fifo.gl0.wr_n_0 ; + wire [2:0]\gpr1.dout_i_reg[1] ; + wire [2:0]\gpr1.dout_i_reg[1]_0 ; + wire [3:0]\gpr1.dout_i_reg[3] ; + wire [3:0]\gpr1.dout_i_reg[7] ; + wire \grss.rsts/ram_empty_i0__3 ; + wire hold_ff_q; + wire hold_ff_q_reg; + wire lsig_packer_full; + wire m_axi_s2mm_aclk; + wire [10:0]p_0_out; + wire p_1_in; + wire p_2_out; + wire p_32_out; + wire ram_full_i_reg; + wire [2:0]rd_pntr_plus1; + wire [8:0]sig_adjusted_addr_incr; + wire [2:0]sig_child_addr_cntr_lsh_reg; + wire [0:0]\sig_child_addr_cntr_lsh_reg[11] ; + wire [3:0]\sig_child_addr_cntr_lsh_reg[7] ; + wire sig_child_qual_error_reg; + wire sig_child_qual_first_of_2; + wire sig_clr_dbc_reg_reg; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_csm_pop_child_cmd; + wire sig_csm_state_ns1; + wire sig_ibtt2dre_tready; + wire sig_sf2pcc_xfer_valid; + wire sig_stream_rst; + wire sig_xfer_cmd_cmplt_reg0; + wire [9:0]sig_xfer_is_seq_reg_reg; + wire sig_xfer_is_seq_reg_reg_0; + wire [3:0]\sig_xfer_len_reg_reg[4] ; + wire [0:0]\sig_xfer_len_reg_reg[5] ; + + Arty_Z7_20_axi_vdma_0_0_rd_logic__parameterized0 \gntv_or_sync_fifo.gl0.rd + (.E(\gntv_or_sync_fifo.gl0.rd_n_2 ), + .Q(rd_pntr_plus1), + .\gc1.count_reg[2] (\gntv_or_sync_fifo.gl0.rd_n_3 ), + .\gpr1.dout_i_reg[1] (\gpr1.dout_i_reg[1]_0 ), + .hold_ff_q(hold_ff_q), + .hold_ff_q_reg(hold_ff_q_reg), + .lsig_packer_full(lsig_packer_full), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(p_2_out), + .p_32_out(p_32_out), + .ram_empty_i0__3(\grss.rsts/ram_empty_i0__3 ), + .ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_0 ), + .ram_full_i_reg(ram_full_i_reg), + .ram_full_i_reg_0(p_1_in), + .sig_clr_dbc_reg_reg(sig_clr_dbc_reg_reg), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_ibtt2dre_tready(sig_ibtt2dre_tready), + .sig_sf2pcc_xfer_valid(sig_sf2pcc_xfer_valid), + .sig_stream_rst(sig_stream_rst)); + Arty_Z7_20_axi_vdma_0_0_wr_logic__parameterized0 \gntv_or_sync_fifo.gl0.wr + (.E(E), + .Q(rd_pntr_plus1), + .\gc1.count_d2_reg[2] (\gpr1.dout_i_reg[1]_0 ), + .\gpr1.dout_i_reg[1] (\gpr1.dout_i_reg[1] ), + .\gv.ram_valid_d1_reg (\gntv_or_sync_fifo.gl0.rd_n_3 ), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(\gntv_or_sync_fifo.gl0.wr_n_0 ), + .ram_empty_fb_i_reg(p_2_out), + .ram_empty_i0__3(\grss.rsts/ram_empty_i0__3 ), + .\sig_byte_cntr_reg[0] (p_1_in), + .sig_clr_dbc_reg_reg(sig_clr_dbc_reg_reg), + .sig_stream_rst(sig_stream_rst)); + Arty_Z7_20_axi_vdma_0_0_memory__parameterized0 \gntv_or_sync_fifo.mem + (.CO(CO), + .D(D), + .E(\gntv_or_sync_fifo.gl0.rd_n_2 ), + .O(O), + .S(S), + .\gpr1.dout_i_reg[3] (\gpr1.dout_i_reg[3] ), + .\gpr1.dout_i_reg[7] (\gpr1.dout_i_reg[7] ), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .p_0_out(p_0_out), + .sig_adjusted_addr_incr(sig_adjusted_addr_incr), + .sig_child_addr_cntr_lsh_reg(sig_child_addr_cntr_lsh_reg), + .\sig_child_addr_cntr_lsh_reg[11] (\sig_child_addr_cntr_lsh_reg[11] ), + .\sig_child_addr_cntr_lsh_reg[7] (\sig_child_addr_cntr_lsh_reg[7] ), + .sig_child_qual_error_reg(sig_child_qual_error_reg), + .sig_child_qual_first_of_2(sig_child_qual_first_of_2), + .sig_csm_pop_child_cmd(sig_csm_pop_child_cmd), + .sig_csm_state_ns1(sig_csm_state_ns1), + .sig_stream_rst(sig_stream_rst), + .sig_xfer_cmd_cmplt_reg0(sig_xfer_cmd_cmplt_reg0), + .sig_xfer_is_seq_reg_reg(sig_xfer_is_seq_reg_reg), + .sig_xfer_is_seq_reg_reg_0(sig_xfer_is_seq_reg_reg_0), + .\sig_xfer_len_reg_reg[4] (\sig_xfer_len_reg_reg[4] ), + .\sig_xfer_len_reg_reg[5] (\sig_xfer_len_reg_reg[5] )); +endmodule + +(* ORIG_REF_NAME = "fifo_generator_ramfifo" *) +module Arty_Z7_20_axi_vdma_0_0_fifo_generator_ramfifo__parameterized1 + (sig_data_fifo_data_out, + out, + \gcc0.gc0.count_d1_reg[7] , + hold_ff_q_reg, + \INCLUDE_PACKING.lsig_packer_full_reg , + E, + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] , + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] , + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] , + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] , + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] , + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] , + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] , + sig_data_fifo_dvalid, + m_axi_s2mm_aclk, + sig_stream_rst, + lsig_combined_data, + DIBDI, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + hold_ff_q_reg_0, + sig_s_ready_out_reg, + lsig_set_packer_full__1, + lsig_packer_full, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ); + output [65:0]sig_data_fifo_data_out; + output out; + output \gcc0.gc0.count_d1_reg[7] ; + output hold_ff_q_reg; + output \INCLUDE_PACKING.lsig_packer_full_reg ; + output [0:0]E; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] ; + output sig_data_fifo_dvalid; + input m_axi_s2mm_aclk; + input sig_stream_rst; + input [63:0]lsig_combined_data; + input [1:0]DIBDI; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input hold_ff_q_reg_0; + input sig_s_ready_out_reg; + input lsig_set_packer_full__1; + input lsig_packer_full; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ; + + wire [1:0]DIBDI; + wire [0:0]E; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ; + wire \INCLUDE_PACKING.lsig_packer_full_reg ; + wire \gcc0.gc0.count_d1_reg[7] ; + wire \gntv_or_sync_fifo.gl0.rd_n_3 ; + wire \gntv_or_sync_fifo.gl0.rd_n_4 ; + wire \gntv_or_sync_fifo.gl0.wr_n_2 ; + wire \grss.rsts/ram_empty_i0__3 ; + wire hold_ff_q_reg; + wire hold_ff_q_reg_0; + wire [63:0]lsig_combined_data; + wire lsig_packer_full; + wire lsig_set_packer_full__1; + wire m_axi_s2mm_aclk; + wire out; + wire [7:0]p_0_out; + wire [7:0]p_11_out; + wire p_2_out_0; + wire p_7_out; + wire [7:0]rd_pntr_plus1; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire [65:0]sig_data_fifo_data_out; + wire sig_data_fifo_dvalid; + wire sig_s_ready_out_reg; + wire sig_stream_rst; + + Arty_Z7_20_axi_vdma_0_0_rd_logic \gntv_or_sync_fifo.gl0.rd + (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\gntv_or_sync_fifo.gl0.rd_n_3 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0 (\gntv_or_sync_fifo.gl0.rd_n_4 ), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_1 (p_0_out), + .Q(rd_pntr_plus1), + .\gpregsm1.user_valid_reg (out), + .hold_ff_q_reg(hold_ff_q_reg), + .hold_ff_q_reg_0(hold_ff_q_reg_0), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(p_2_out_0), + .p_7_out(p_7_out), + .ram_empty_i0__3(\grss.rsts/ram_empty_i0__3 ), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_data_fifo_dvalid(sig_data_fifo_dvalid), + .sig_s_ready_out_reg(sig_s_ready_out_reg), + .sig_stream_rst(sig_stream_rst)); + Arty_Z7_20_axi_vdma_0_0_wr_logic \gntv_or_sync_fifo.gl0.wr + (.E(E), + .\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] (\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] (\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] (\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] (\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] (\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] (\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] (\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ), + .\INCLUDE_PACKING.lsig_packer_full_reg (\INCLUDE_PACKING.lsig_packer_full_reg ), + .Q(p_11_out), + .WEBWE(\gntv_or_sync_fifo.gl0.wr_n_2 ), + .\gc1.count_d1_reg[7] (rd_pntr_plus1), + .\gc1.count_d2_reg[7] (p_0_out), + .lsig_packer_full(lsig_packer_full), + .lsig_set_packer_full__1(lsig_set_packer_full__1), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(\gcc0.gc0.count_d1_reg[7] ), + .p_7_out(p_7_out), + .ram_empty_fb_i_reg(p_2_out_0), + .ram_empty_i0__3(\grss.rsts/ram_empty_i0__3 ), + .sig_stream_rst(sig_stream_rst)); + Arty_Z7_20_axi_vdma_0_0_memory__parameterized1 \gntv_or_sync_fifo.mem + (.DIBDI(DIBDI), + .Q(p_11_out), + .WEBWE(\gntv_or_sync_fifo.gl0.wr_n_2 ), + .\gc1.count_d2_reg[7] (p_0_out), + .lsig_combined_data(lsig_combined_data), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .ram_empty_fb_i_reg(\gntv_or_sync_fifo.gl0.rd_n_4 ), + .sig_data_fifo_data_out(sig_data_fifo_data_out), + .sig_s_ready_out_reg(\gntv_or_sync_fifo.gl0.rd_n_3 ), + .sig_stream_rst(sig_stream_rst)); endmodule -(* ORIG_REF_NAME = "builtin_prim_v6" *) -module Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_12 - (EMPTY, +(* ORIG_REF_NAME = "fifo_generator_top" *) +module Arty_Z7_20_axi_vdma_0_0_fifo_generator_top + (sig_m_valid_out_reg, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg , + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg , FULL, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 , + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 , fifo_dout, - m_axis_mm2s_aclk, - RD_EN, - RST, m_axi_mm2s_aclk, + s_axis_fifo_ainit_nosync_reg, + m_axis_mm2s_aclk, + out, + lsig_0ffset_cntr, + mm2s_prmry_resetn, + mm2s_halt, + p_24_out, + hold_ff_q_reg, + DIN, WR_EN, dm2linebuf_mm2s_tdata); - output EMPTY; + output sig_m_valid_out_reg; + output \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; output FULL; - output [8:0]fifo_dout; - input m_axis_mm2s_aclk; - input RD_EN; - input RST; + output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ; + output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 ; + output [33:0]fifo_dout; input m_axi_mm2s_aclk; + input s_axis_fifo_ainit_nosync_reg; + input m_axis_mm2s_aclk; + input out; + input lsig_0ffset_cntr; + input mm2s_prmry_resetn; + input mm2s_halt; + input p_24_out; + input hold_ff_q_reg; + input [15:0]DIN; input WR_EN; - input [8:0]dm2linebuf_mm2s_tdata; + input [17:0]dm2linebuf_mm2s_tdata; - wire EMPTY; + wire [15:0]DIN; wire FULL; - wire RD_EN; - wire RST; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 ; + wire \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; wire WR_EN; - wire [8:0]dm2linebuf_mm2s_tdata; - wire [8:0]fifo_dout; - wire \gf36e1_inst.sngfifo36e1_n_14 ; - wire \gf36e1_inst.sngfifo36e1_n_15 ; - wire \gf36e1_inst.sngfifo36e1_n_17 ; - wire \gf36e1_inst.sngfifo36e1_n_18 ; - wire \gf36e1_inst.sngfifo36e1_n_19 ; - wire \gf36e1_inst.sngfifo36e1_n_20 ; - wire \gf36e1_inst.sngfifo36e1_n_21 ; - wire \gf36e1_inst.sngfifo36e1_n_22 ; - wire \gf36e1_inst.sngfifo36e1_n_23 ; - wire \gf36e1_inst.sngfifo36e1_n_24 ; - wire \gf36e1_inst.sngfifo36e1_n_25 ; - wire \gf36e1_inst.sngfifo36e1_n_26 ; - wire \gf36e1_inst.sngfifo36e1_n_27 ; - wire \gf36e1_inst.sngfifo36e1_n_28 ; - wire \gf36e1_inst.sngfifo36e1_n_30 ; - wire \gf36e1_inst.sngfifo36e1_n_31 ; - wire \gf36e1_inst.sngfifo36e1_n_32 ; - wire \gf36e1_inst.sngfifo36e1_n_33 ; - wire \gf36e1_inst.sngfifo36e1_n_34 ; - wire \gf36e1_inst.sngfifo36e1_n_35 ; - wire \gf36e1_inst.sngfifo36e1_n_36 ; - wire \gf36e1_inst.sngfifo36e1_n_37 ; - wire \gf36e1_inst.sngfifo36e1_n_38 ; - wire \gf36e1_inst.sngfifo36e1_n_39 ; - wire \gf36e1_inst.sngfifo36e1_n_40 ; - wire \gf36e1_inst.sngfifo36e1_n_41 ; - wire m_axi_mm2s_aclk; - wire m_axis_mm2s_aclk; - wire p_24_out; - wire p_25_out; - wire p_26_out; - wire p_27_out; - wire [63:8]\NLW_gf36e1_inst.sngfifo36e1_DO_UNCONNECTED ; - wire [7:1]\NLW_gf36e1_inst.sngfifo36e1_DOP_UNCONNECTED ; - wire [7:0]\NLW_gf36e1_inst.sngfifo36e1_ECCPARITY_UNCONNECTED ; - wire [12:12]\NLW_gf36e1_inst.sngfifo36e1_RDCOUNT_UNCONNECTED ; - wire [12:12]\NLW_gf36e1_inst.sngfifo36e1_WRCOUNT_UNCONNECTED ; - - (* CLOCK_DOMAINS = "INDEPENDENT" *) - (* box_type = "PRIMITIVE" *) - FIFO36E1 #( - .ALMOST_EMPTY_OFFSET(13'h000A), - .ALMOST_FULL_OFFSET(13'h0097), - .DATA_WIDTH(9), - .DO_REG(1), - .EN_ECC_READ("FALSE"), - .EN_ECC_WRITE("FALSE"), - .EN_SYN("FALSE"), - .FIFO_MODE("FIFO36"), - .FIRST_WORD_FALL_THROUGH("TRUE"), - .INIT(72'h000000000000000000), - .IS_RDCLK_INVERTED(1'b0), - .IS_RDEN_INVERTED(1'b0), - .IS_RSTREG_INVERTED(1'b0), - .IS_RST_INVERTED(1'b0), - .IS_WRCLK_INVERTED(1'b0), - .IS_WREN_INVERTED(1'b0), - .SIM_DEVICE("7SERIES"), - .SRVAL(72'h000000000000000000)) - \gf36e1_inst.sngfifo36e1 - (.ALMOSTEMPTY(p_25_out), - .ALMOSTFULL(p_24_out), - .DBITERR(p_27_out), - .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dm2linebuf_mm2s_tdata[7:0]}), - .DIP({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dm2linebuf_mm2s_tdata[8]}), - .DO({\NLW_gf36e1_inst.sngfifo36e1_DO_UNCONNECTED [63:8],fifo_dout[7:0]}), - .DOP({\NLW_gf36e1_inst.sngfifo36e1_DOP_UNCONNECTED [7:1],fifo_dout[8]}), - .ECCPARITY(\NLW_gf36e1_inst.sngfifo36e1_ECCPARITY_UNCONNECTED [7:0]), - .EMPTY(EMPTY), - .FULL(FULL), - .INJECTDBITERR(1'b0), - .INJECTSBITERR(1'b0), - .RDCLK(m_axis_mm2s_aclk), - .RDCOUNT({\NLW_gf36e1_inst.sngfifo36e1_RDCOUNT_UNCONNECTED [12],\gf36e1_inst.sngfifo36e1_n_17 ,\gf36e1_inst.sngfifo36e1_n_18 ,\gf36e1_inst.sngfifo36e1_n_19 ,\gf36e1_inst.sngfifo36e1_n_20 ,\gf36e1_inst.sngfifo36e1_n_21 ,\gf36e1_inst.sngfifo36e1_n_22 ,\gf36e1_inst.sngfifo36e1_n_23 ,\gf36e1_inst.sngfifo36e1_n_24 ,\gf36e1_inst.sngfifo36e1_n_25 ,\gf36e1_inst.sngfifo36e1_n_26 ,\gf36e1_inst.sngfifo36e1_n_27 ,\gf36e1_inst.sngfifo36e1_n_28 }), - .RDEN(RD_EN), - .RDERR(\gf36e1_inst.sngfifo36e1_n_14 ), - .REGCE(1'b0), - .RST(RST), - .RSTREG(1'b0), - .SBITERR(p_26_out), - .WRCLK(m_axi_mm2s_aclk), - .WRCOUNT({\NLW_gf36e1_inst.sngfifo36e1_WRCOUNT_UNCONNECTED [12],\gf36e1_inst.sngfifo36e1_n_30 ,\gf36e1_inst.sngfifo36e1_n_31 ,\gf36e1_inst.sngfifo36e1_n_32 ,\gf36e1_inst.sngfifo36e1_n_33 ,\gf36e1_inst.sngfifo36e1_n_34 ,\gf36e1_inst.sngfifo36e1_n_35 ,\gf36e1_inst.sngfifo36e1_n_36 ,\gf36e1_inst.sngfifo36e1_n_37 ,\gf36e1_inst.sngfifo36e1_n_38 ,\gf36e1_inst.sngfifo36e1_n_39 ,\gf36e1_inst.sngfifo36e1_n_40 ,\gf36e1_inst.sngfifo36e1_n_41 }), - .WREN(WR_EN), - .WRERR(\gf36e1_inst.sngfifo36e1_n_15 )); -endmodule - -(* ORIG_REF_NAME = "builtin_top_v6" *) -module Arty_Z7_20_axi_vdma_0_0_builtin_top_v6 - (fifo_full_i, - sig_m_valid_out_reg, - fifo_dout, - fifo_wren__0, - out, - m_axis_mm2s_aclk, - RST, - m_axi_mm2s_aclk, - dm2linebuf_mm2s_tdata, - DIN); - output fifo_full_i; - output sig_m_valid_out_reg; - output [33:0]fifo_dout; - input fifo_wren__0; - input out; - input m_axis_mm2s_aclk; - input RST; - input m_axi_mm2s_aclk; - input [31:0]dm2linebuf_mm2s_tdata; - input [1:0]DIN; - - wire [1:0]DIN; - wire RST; - wire [31:0]dm2linebuf_mm2s_tdata; + wire [17:0]dm2linebuf_mm2s_tdata; wire [33:0]fifo_dout; - wire fifo_full_i; - wire fifo_wren__0; + wire hold_ff_q_reg; + wire lsig_0ffset_cntr; wire m_axi_mm2s_aclk; wire m_axis_mm2s_aclk; + wire mm2s_halt; + wire mm2s_prmry_resetn; wire out; - wire p_15_out; - wire p_16_out; - wire p_22_out; - wire p_23_out; - wire p_4_out; - wire p_5_out; - wire p_8_out; - wire p_9_out; - wire rd_tmp; + wire p_24_out; + wire s_axis_fifo_ainit_nosync_reg; wire sig_m_valid_out_reg; - wire wr_tmp; - Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6 \gextw[1].gnll_fifo.inst_extd - (.EMPTY(p_23_out), - .FULL(p_22_out), - .RD_EN(rd_tmp), - .RST(RST), - .WR_EN(wr_tmp), - .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata[8:0]), - .fifo_dout(fifo_dout[8:0]), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axis_mm2s_aclk(m_axis_mm2s_aclk)); - Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_7 \gextw[2].gnll_fifo.inst_extd - (.EMPTY(p_16_out), - .FULL(p_15_out), - .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg (p_5_out), - .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 (p_4_out), - .RD_EN(rd_tmp), - .RST(RST), - .WR_EN(wr_tmp), - .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata[17:9]), - .fifo_dout(fifo_dout[17:9]), - .fifo_full_i(fifo_full_i), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axis_mm2s_aclk(m_axis_mm2s_aclk), - .sig_m_valid_out_reg(sig_m_valid_out_reg), - .sig_s_ready_out_reg(p_22_out), - .sig_s_ready_out_reg_0(p_8_out), - .sig_s_ready_out_reg_1(p_23_out), - .sig_s_ready_out_reg_2(p_9_out)); - Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_8 \gextw[3].gnll_fifo.inst_extd - (.EMPTY(p_9_out), - .FULL(p_8_out), - .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg (p_4_out), - .RD_EN(rd_tmp), - .RST(RST), - .WR_EN(wr_tmp), - .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata[26:18]), - .fifo_dout(fifo_dout[26:18]), + Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_builtin \gbi.bi + (.DIN(DIN), + .FULL(FULL), + .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ), + .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ), + .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 ), + .\INCLUDE_UNPACKING.lsig_cmd_loaded_reg (\INCLUDE_UNPACKING.lsig_cmd_loaded_reg ), + .WR_EN(WR_EN), + .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), + .fifo_dout(fifo_dout), + .hold_ff_q_reg(hold_ff_q_reg), + .lsig_0ffset_cntr(lsig_0ffset_cntr), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), .m_axis_mm2s_aclk(m_axis_mm2s_aclk), + .mm2s_halt(mm2s_halt), + .mm2s_prmry_resetn(mm2s_prmry_resetn), .out(out), - .sig_s_ready_out_reg(p_23_out), - .sig_s_ready_out_reg_0(p_16_out)); - Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_9 \gextw[4].gnll_fifo.inst_extd - (.DIN({DIN,dm2linebuf_mm2s_tdata[31:27]}), - .EMPTY(p_4_out), - .FULL(p_5_out), - .RD_EN(rd_tmp), - .RST(RST), - .WR_EN(wr_tmp), - .fifo_dout(fifo_dout[33:27]), - .fifo_wren__0(fifo_wren__0), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axis_mm2s_aclk(m_axis_mm2s_aclk), - .sig_s_ready_out_reg(p_8_out), - .sig_s_ready_out_reg_0(p_22_out), - .sig_s_ready_out_reg_1(p_15_out)); + .p_24_out(p_24_out), + .s_axis_fifo_ainit_nosync_reg(s_axis_fifo_ainit_nosync_reg), + .sig_m_valid_out_reg(sig_m_valid_out_reg)); endmodule -(* ORIG_REF_NAME = "dc_ss" *) -module Arty_Z7_20_axi_vdma_0_0_dc_ss - (DI, - Q, - sig_ok_to_post_rd_addr_reg, - S, - \count_reg[6] , - ram_full_i_reg, - \sig_token_cntr_reg[3] , - sig_posted_to_axi_2_reg, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_posted_to_axi_2_reg_0, - E, - sig_stream_rst, - \gpregsm1.curr_fwft_state_reg[0] , +(* ORIG_REF_NAME = "fifo_generator_top" *) +module Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized0 + (FULL, D, - m_axi_mm2s_aclk); - output [3:0]DI; - output [1:0]Q; - output sig_ok_to_post_rd_addr_reg; - output [3:0]S; - output [1:0]\count_reg[6] ; - input ram_full_i_reg; - input [3:0]\sig_token_cntr_reg[3] ; - input sig_posted_to_axi_2_reg; - input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - input sig_posted_to_axi_2_reg_0; - input [0:0]E; - input sig_stream_rst; - input [0:0]\gpregsm1.curr_fwft_state_reg[0] ; - input [5:0]D; - input m_axi_mm2s_aclk; + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] , + DOUT, + EMPTY, + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg , + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg , + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg , + strm_not_finished_no_dwidth, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] , + s_axis_s2mm_aclk, + sig_reset_reg, + m_axi_s2mm_aclk, + M_VALID, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 , + s2mm_fsync_out_i, + out, + p_3_out, + Q, + \vsize_vid_reg[12] , + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out , + minusOp_1, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 , + s2mm_strm_wready, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] , + DIN, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] , + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] , + minusOp, + RD_EN); + output FULL; + output [12:0]D; + output \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ; + output [8:0]DOUT; + output EMPTY; + output \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg ; + output \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg ; + output \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ; + output strm_not_finished_no_dwidth; + output [12:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] ; + input s_axis_s2mm_aclk; + input sig_reset_reg; + input m_axi_s2mm_aclk; + input M_VALID; + input \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ; + input s2mm_fsync_out_i; + input out; + input p_3_out; + input [6:0]Q; + input [12:0]\vsize_vid_reg[12] ; + input \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ; + input [11:0]minusOp_1; + input \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 ; + input s2mm_strm_wready; + input [0:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] ; + input [8:0]DIN; + input \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ; + input [12:0]\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] ; + input [11:0]minusOp; + input RD_EN; - wire [5:0]D; - wire [3:0]DI; - wire [0:0]E; - wire [1:0]Q; - wire [3:0]S; - wire [1:0]\count_reg[6] ; - wire [0:0]\gpregsm1.curr_fwft_state_reg[0] ; - wire m_axi_mm2s_aclk; - wire ram_full_i_reg; - wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - wire sig_ok_to_post_rd_addr_reg; - wire sig_posted_to_axi_2_reg; - wire sig_posted_to_axi_2_reg_0; - wire sig_stream_rst; - wire [3:0]\sig_token_cntr_reg[3] ; + wire [12:0]D; + wire [8:0]DIN; + wire [8:0]DOUT; + wire EMPTY; + wire FULL; + wire \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ; + wire [12:0]\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg ; + wire [0:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] ; + wire [12:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ; + wire M_VALID; + wire [6:0]Q; + wire RD_EN; + wire m_axi_s2mm_aclk; + wire [11:0]minusOp; + wire [11:0]minusOp_1; + wire out; + wire p_3_out; + wire s2mm_fsync_out_i; + wire s2mm_strm_wready; + wire s_axis_s2mm_aclk; + wire sig_reset_reg; + wire strm_not_finished_no_dwidth; + wire [12:0]\vsize_vid_reg[12] ; - Arty_Z7_20_axi_vdma_0_0_updn_cntr \gsym_dc.dc + Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_builtin__parameterized0 \gbi.bi (.D(D), - .DI(DI), - .E(E), + .DIN(DIN), + .DOUT(DOUT), + .EMPTY(EMPTY), + .FULL(FULL), + .\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out (\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] (\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] (\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 (\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg (\GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ), + .M_VALID(M_VALID), .Q(Q), - .S(S), - .\count_reg[6]_0 (\count_reg[6] ), - .\gpregsm1.curr_fwft_state_reg[0] (\gpregsm1.curr_fwft_state_reg[0] ), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .ram_full_i_reg(ram_full_i_reg), - .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .sig_ok_to_post_rd_addr_reg(sig_ok_to_post_rd_addr_reg), - .sig_posted_to_axi_2_reg(sig_posted_to_axi_2_reg), - .sig_posted_to_axi_2_reg_0(sig_posted_to_axi_2_reg_0), - .sig_stream_rst(sig_stream_rst), - .\sig_token_cntr_reg[3] (\sig_token_cntr_reg[3] )); + .RD_EN(RD_EN), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .minusOp(minusOp), + .minusOp_1(minusOp_1), + .out(out), + .p_3_out(p_3_out), + .s2mm_fsync_out_i(s2mm_fsync_out_i), + .s2mm_strm_wready(s2mm_strm_wready), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk), + .sig_reset_reg(sig_reset_reg), + .strm_not_finished_no_dwidth(strm_not_finished_no_dwidth), + .\vsize_vid_reg[12] (\vsize_vid_reg[12] )); endmodule -(* ORIG_REF_NAME = "fifo_generator_ramfifo" *) -module Arty_Z7_20_axi_vdma_0_0_fifo_generator_ramfifo - (out, - \sig_user_skid_reg_reg[0] , - dm2linebuf_mm2s_tvalid, - DI, - Q, - dm2linebuf_mm2s_tdata, - hold_ff_q_reg, +(* ORIG_REF_NAME = "fifo_generator_top" *) +module Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized1 + (DOBDO, + out, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram , sig_ok_to_post_rd_addr_reg, - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , \INCLUDE_UNPACKING.lsig_cmd_loaded_reg , - \INFERRED_GEN.cnt_i_reg[0] , - S, - \count_reg[6] , + hold_ff_q_reg, + \gc1.count_reg[7] , + \INFERRED_GEN.cnt_i_reg[2] , + DIN, + \sig_user_skid_reg_reg[0] , + dm2linebuf_mm2s_tdata, m_axi_mm2s_aclk, - sig_stream_rst, + E, + SR, m_axi_mm2s_rdata, DIBDI, - lsig_0ffset_cntr, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_posted_to_axi_2_reg, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , + Q, lsig_cmd_loaded, hold_ff_q, + ram_full_i_reg, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 , + \sig_token_cntr_reg[0] , \sig_token_cntr_reg[3] , - p_8_out, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_posted_to_axi_2_reg, - sig_posted_to_axi_2_reg_0, - p_0_out, - \INFERRED_GEN.cnt_i_reg[2] , - fifo_wren__0, - mm2s_strm_wvalid0__1, - m_axi_mm2s_rvalid, - sig_advance_pipe9_out__1, - D); + ram_full_i_reg_0); + output [0:0]DOBDO; output out; - output [0:0]\sig_user_skid_reg_reg[0] ; - output dm2linebuf_mm2s_tvalid; - output [3:0]DI; - output [1:0]Q; - output [31:0]dm2linebuf_mm2s_tdata; - output hold_ff_q_reg; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; output sig_ok_to_post_rd_addr_reg; - output \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; output \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; - output \INFERRED_GEN.cnt_i_reg[0] ; - output [3:0]S; - output [1:0]\count_reg[6] ; + output hold_ff_q_reg; + output [0:0]\gc1.count_reg[7] ; + output \INFERRED_GEN.cnt_i_reg[2] ; + output [0:0]DIN; + output \sig_user_skid_reg_reg[0] ; + output [31:0]dm2linebuf_mm2s_tdata; input m_axi_mm2s_aclk; - input sig_stream_rst; + input [0:0]E; + input [0:0]SR; input [63:0]m_axi_mm2s_rdata; input [1:0]DIBDI; - input lsig_0ffset_cntr; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_posted_to_axi_2_reg; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + input [0:0]Q; input lsig_cmd_loaded; input hold_ff_q; + input ram_full_i_reg; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; + input \sig_token_cntr_reg[0] ; input [3:0]\sig_token_cntr_reg[3] ; - input p_8_out; - input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - input sig_posted_to_axi_2_reg; - input sig_posted_to_axi_2_reg_0; - input [0:0]p_0_out; - input [0:0]\INFERRED_GEN.cnt_i_reg[2] ; - input fifo_wren__0; - input mm2s_strm_wvalid0__1; - input m_axi_mm2s_rvalid; - input sig_advance_pipe9_out__1; - input [5:0]D; + input [0:0]ram_full_i_reg_0; - wire [5:0]D; - wire [3:0]DI; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; wire [1:0]DIBDI; + wire [0:0]DIN; + wire [0:0]DOBDO; + wire [0:0]E; wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; wire \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; - wire \INFERRED_GEN.cnt_i_reg[0] ; - wire [0:0]\INFERRED_GEN.cnt_i_reg[2] ; - wire [1:0]Q; - wire [3:0]S; - wire [1:0]\count_reg[6] ; + wire \INFERRED_GEN.cnt_i_reg[2] ; + wire [0:0]Q; + wire [0:0]SR; wire [31:0]dm2linebuf_mm2s_tdata; - wire dm2linebuf_mm2s_tvalid; - wire fifo_wren__0; - wire \gntv_or_sync_fifo.gl0.rd_n_1 ; - wire \gntv_or_sync_fifo.gl0.rd_n_13 ; - wire \gntv_or_sync_fifo.gl0.rd_n_18 ; - wire \gntv_or_sync_fifo.gl0.wr_n_2 ; - wire \grss.rsts/ram_empty_i0__3 ; + wire [0:0]\gc1.count_reg[7] ; wire hold_ff_q; wire hold_ff_q_reg; - wire lsig_0ffset_cntr; wire lsig_cmd_loaded; wire m_axi_mm2s_aclk; wire [63:0]m_axi_mm2s_rdata; - wire m_axi_mm2s_rvalid; - wire mm2s_strm_wvalid0__1; wire out; - wire [0:0]p_0_out; - wire [6:0]p_0_out_1; - wire [6:0]p_11_out; - wire p_2_out_0; - wire p_7_out; - wire p_8_out; - wire [6:0]rd_pntr_plus1; - wire sig_advance_pipe9_out__1; + wire ram_full_i_reg; + wire [0:0]ram_full_i_reg_0; wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - wire [65:65]sig_data_fifo_data_out; wire sig_ok_to_post_rd_addr_reg; wire sig_posted_to_axi_2_reg; - wire sig_posted_to_axi_2_reg_0; - wire sig_stream_rst; + wire \sig_token_cntr_reg[0] ; wire [3:0]\sig_token_cntr_reg[3] ; - wire [0:0]\sig_user_skid_reg_reg[0] ; + wire \sig_user_skid_reg_reg[0] ; - Arty_Z7_20_axi_vdma_0_0_rd_logic \gntv_or_sync_fifo.gl0.rd - (.D(D), - .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\gntv_or_sync_fifo.gl0.rd_n_13 ), - .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0 (\gntv_or_sync_fifo.gl0.rd_n_18 ), - .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_1 (p_0_out_1), - .DI(DI), - .DOBDO(sig_data_fifo_data_out), + Arty_Z7_20_axi_vdma_0_0_fifo_generator_ramfifo \grf.rf + (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ), + .DIBDI(DIBDI), + .DIN(DIN), + .DOBDO(DOBDO), + .E(E), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), .\INCLUDE_UNPACKING.lsig_cmd_loaded_reg (\INCLUDE_UNPACKING.lsig_cmd_loaded_reg ), .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ), .Q(Q), - .S(S), - .\count_reg[6] (\count_reg[6] ), - .dm2linebuf_mm2s_tvalid(dm2linebuf_mm2s_tvalid), - .\gc1.count_d2_reg[6] (rd_pntr_plus1), + .SR(SR), + .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), + .\gc1.count_reg[7] (\gc1.count_reg[7] ), .hold_ff_q(hold_ff_q), - .hold_ff_q_reg(\gntv_or_sync_fifo.gl0.rd_n_1 ), - .hold_ff_q_reg_0(hold_ff_q_reg), - .lsig_0ffset_cntr(lsig_0ffset_cntr), + .hold_ff_q_reg(hold_ff_q_reg), .lsig_cmd_loaded(lsig_cmd_loaded), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .out(p_2_out_0), - .p_7_out(p_7_out), - .p_8_out(p_8_out), - .ram_empty_i0__3(\grss.rsts/ram_empty_i0__3 ), - .ram_full_i_reg(\gntv_or_sync_fifo.gl0.wr_n_2 ), - .ram_full_i_reg_0(out), + .m_axi_mm2s_rdata(m_axi_mm2s_rdata), + .out(out), + .ram_full_i_reg(ram_full_i_reg), + .ram_full_i_reg_0(ram_full_i_reg_0), .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), .sig_ok_to_post_rd_addr_reg(sig_ok_to_post_rd_addr_reg), .sig_posted_to_axi_2_reg(sig_posted_to_axi_2_reg), - .sig_posted_to_axi_2_reg_0(sig_posted_to_axi_2_reg_0), - .sig_stream_rst(sig_stream_rst), - .\sig_token_cntr_reg[3] (\sig_token_cntr_reg[3] )); - Arty_Z7_20_axi_vdma_0_0_wr_logic \gntv_or_sync_fifo.gl0.wr - (.Q(p_11_out), - .\gc1.count_d1_reg[6] (rd_pntr_plus1), - .\gc1.count_d2_reg[6] (p_0_out_1), - .\gcc0.gc0.count_d1_reg[6] (\gntv_or_sync_fifo.gl0.wr_n_2 ), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axi_mm2s_rvalid(m_axi_mm2s_rvalid), - .mm2s_strm_wvalid0__1(mm2s_strm_wvalid0__1), - .out(out), - .p_7_out(p_7_out), - .ram_empty_fb_i_reg(p_2_out_0), - .ram_empty_i0__3(\grss.rsts/ram_empty_i0__3 ), - .sig_advance_pipe9_out__1(sig_advance_pipe9_out__1), - .sig_stream_rst(sig_stream_rst)); - Arty_Z7_20_axi_vdma_0_0_memory \gntv_or_sync_fifo.mem - (.DIBDI(DIBDI), - .DOBDO(sig_data_fifo_data_out), - .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), - .\INFERRED_GEN.cnt_i_reg[0] (\INFERRED_GEN.cnt_i_reg[0] ), - .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ), - .Q(p_11_out), - .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), - .dm2linebuf_mm2s_tvalid(dm2linebuf_mm2s_tvalid), - .fifo_wren__0(fifo_wren__0), - .\gc1.count_d2_reg[6] (p_0_out_1), - .\gpregsm1.curr_fwft_state_reg[0] (\gntv_or_sync_fifo.gl0.rd_n_13 ), - .\gpregsm1.user_valid_reg (\gntv_or_sync_fifo.gl0.rd_n_1 ), + .\sig_token_cntr_reg[0] (\sig_token_cntr_reg[0] ), + .\sig_token_cntr_reg[3] (\sig_token_cntr_reg[3] ), + .\sig_user_skid_reg_reg[0] (\sig_user_skid_reg_reg[0] )); +endmodule + +(* ORIG_REF_NAME = "fifo_generator_top" *) +module Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized2 + (hold_ff_q_reg, + D, + sig_xfer_is_seq_reg_reg, + \sig_child_addr_cntr_lsh_reg[11] , + E, + S, + \sig_xfer_len_reg_reg[4] , + \sig_xfer_len_reg_reg[5] , + sig_xfer_is_seq_reg_reg_0, + sig_xfer_cmd_cmplt_reg0, + sig_sf2pcc_xfer_valid, + sig_ibtt2dre_tready, + sig_csm_state_ns1, + \gpr1.dout_i_reg[1] , + \gpr1.dout_i_reg[1]_0 , + O, + CO, + \sig_child_addr_cntr_lsh_reg[7] , + sig_stream_rst, + m_axi_s2mm_aclk, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + p_32_out, + hold_ff_q, + sig_adjusted_addr_incr, + sig_clr_dbc_reg_reg, + sig_csm_pop_child_cmd, + sig_child_qual_first_of_2, + sig_child_qual_error_reg, + lsig_packer_full, + ram_full_i_reg, + \gpr1.dout_i_reg[3] , + \gpr1.dout_i_reg[7] , + sig_child_addr_cntr_lsh_reg, + p_0_out); + output hold_ff_q_reg; + output [2:0]D; + output [9:0]sig_xfer_is_seq_reg_reg; + output [0:0]\sig_child_addr_cntr_lsh_reg[11] ; + output [0:0]E; + output [3:0]S; + output [3:0]\sig_xfer_len_reg_reg[4] ; + output [0:0]\sig_xfer_len_reg_reg[5] ; + output sig_xfer_is_seq_reg_reg_0; + output sig_xfer_cmd_cmplt_reg0; + output sig_sf2pcc_xfer_valid; + output sig_ibtt2dre_tready; + output sig_csm_state_ns1; + output [2:0]\gpr1.dout_i_reg[1] ; + output [2:0]\gpr1.dout_i_reg[1]_0 ; + output [3:0]O; + output [0:0]CO; + output [3:0]\sig_child_addr_cntr_lsh_reg[7] ; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input p_32_out; + input hold_ff_q; + input [8:0]sig_adjusted_addr_incr; + input sig_clr_dbc_reg_reg; + input sig_csm_pop_child_cmd; + input sig_child_qual_first_of_2; + input sig_child_qual_error_reg; + input lsig_packer_full; + input ram_full_i_reg; + input [3:0]\gpr1.dout_i_reg[3] ; + input [3:0]\gpr1.dout_i_reg[7] ; + input [2:0]sig_child_addr_cntr_lsh_reg; + input [10:0]p_0_out; + + wire [0:0]CO; + wire [2:0]D; + wire [0:0]E; + wire [3:0]O; + wire [3:0]S; + wire [2:0]\gpr1.dout_i_reg[1] ; + wire [2:0]\gpr1.dout_i_reg[1]_0 ; + wire [3:0]\gpr1.dout_i_reg[3] ; + wire [3:0]\gpr1.dout_i_reg[7] ; + wire hold_ff_q; + wire hold_ff_q_reg; + wire lsig_packer_full; + wire m_axi_s2mm_aclk; + wire [10:0]p_0_out; + wire p_32_out; + wire ram_full_i_reg; + wire [8:0]sig_adjusted_addr_incr; + wire [2:0]sig_child_addr_cntr_lsh_reg; + wire [0:0]\sig_child_addr_cntr_lsh_reg[11] ; + wire [3:0]\sig_child_addr_cntr_lsh_reg[7] ; + wire sig_child_qual_error_reg; + wire sig_child_qual_first_of_2; + wire sig_clr_dbc_reg_reg; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_csm_pop_child_cmd; + wire sig_csm_state_ns1; + wire sig_ibtt2dre_tready; + wire sig_sf2pcc_xfer_valid; + wire sig_stream_rst; + wire sig_xfer_cmd_cmplt_reg0; + wire [9:0]sig_xfer_is_seq_reg_reg; + wire sig_xfer_is_seq_reg_reg_0; + wire [3:0]\sig_xfer_len_reg_reg[4] ; + wire [0:0]\sig_xfer_len_reg_reg[5] ; + + Arty_Z7_20_axi_vdma_0_0_fifo_generator_ramfifo__parameterized0 \grf.rf + (.CO(CO), + .D(D), + .E(E), + .O(O), + .S(S), + .\gpr1.dout_i_reg[1] (\gpr1.dout_i_reg[1] ), + .\gpr1.dout_i_reg[1]_0 (\gpr1.dout_i_reg[1]_0 ), + .\gpr1.dout_i_reg[3] (\gpr1.dout_i_reg[3] ), + .\gpr1.dout_i_reg[7] (\gpr1.dout_i_reg[7] ), .hold_ff_q(hold_ff_q), - .lsig_0ffset_cntr(lsig_0ffset_cntr), - .lsig_cmd_loaded(lsig_cmd_loaded), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axi_mm2s_rdata(m_axi_mm2s_rdata), + .hold_ff_q_reg(hold_ff_q_reg), + .lsig_packer_full(lsig_packer_full), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), .p_0_out(p_0_out), - .p_8_out(p_8_out), - .ram_empty_fb_i_reg(\gntv_or_sync_fifo.gl0.rd_n_18 ), - .ram_full_i_reg(\gntv_or_sync_fifo.gl0.wr_n_2 ), + .p_32_out(p_32_out), + .ram_full_i_reg(ram_full_i_reg), + .sig_adjusted_addr_incr(sig_adjusted_addr_incr), + .sig_child_addr_cntr_lsh_reg(sig_child_addr_cntr_lsh_reg), + .\sig_child_addr_cntr_lsh_reg[11] (\sig_child_addr_cntr_lsh_reg[11] ), + .\sig_child_addr_cntr_lsh_reg[7] (\sig_child_addr_cntr_lsh_reg[7] ), + .sig_child_qual_error_reg(sig_child_qual_error_reg), + .sig_child_qual_first_of_2(sig_child_qual_first_of_2), + .sig_clr_dbc_reg_reg(sig_clr_dbc_reg_reg), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_csm_pop_child_cmd(sig_csm_pop_child_cmd), + .sig_csm_state_ns1(sig_csm_state_ns1), + .sig_ibtt2dre_tready(sig_ibtt2dre_tready), + .sig_sf2pcc_xfer_valid(sig_sf2pcc_xfer_valid), .sig_stream_rst(sig_stream_rst), - .\sig_user_skid_reg_reg[0] (\sig_user_skid_reg_reg[0] )); + .sig_xfer_cmd_cmplt_reg0(sig_xfer_cmd_cmplt_reg0), + .sig_xfer_is_seq_reg_reg(sig_xfer_is_seq_reg_reg), + .sig_xfer_is_seq_reg_reg_0(sig_xfer_is_seq_reg_reg_0), + .\sig_xfer_len_reg_reg[4] (\sig_xfer_len_reg_reg[4] ), + .\sig_xfer_len_reg_reg[5] (\sig_xfer_len_reg_reg[5] )); endmodule (* ORIG_REF_NAME = "fifo_generator_top" *) -module Arty_Z7_20_axi_vdma_0_0_fifo_generator_top - (fifo_full_i, - sig_m_valid_out_reg, +module Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized3 + (sig_data_fifo_data_out, + out, + \gcc0.gc0.count_d1_reg[7] , + hold_ff_q_reg, + \INCLUDE_PACKING.lsig_packer_full_reg , + E, + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] , + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] , + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] , + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] , + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] , + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] , + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] , + sig_data_fifo_dvalid, + m_axi_s2mm_aclk, + sig_stream_rst, + lsig_combined_data, + DIBDI, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + hold_ff_q_reg_0, + sig_s_ready_out_reg, + lsig_set_packer_full__1, + lsig_packer_full, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ); + output [65:0]sig_data_fifo_data_out; + output out; + output \gcc0.gc0.count_d1_reg[7] ; + output hold_ff_q_reg; + output \INCLUDE_PACKING.lsig_packer_full_reg ; + output [0:0]E; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] ; + output sig_data_fifo_dvalid; + input m_axi_s2mm_aclk; + input sig_stream_rst; + input [63:0]lsig_combined_data; + input [1:0]DIBDI; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input hold_ff_q_reg_0; + input sig_s_ready_out_reg; + input lsig_set_packer_full__1; + input lsig_packer_full; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ; + + wire [1:0]DIBDI; + wire [0:0]E; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ; + wire \INCLUDE_PACKING.lsig_packer_full_reg ; + wire \gcc0.gc0.count_d1_reg[7] ; + wire hold_ff_q_reg; + wire hold_ff_q_reg_0; + wire [63:0]lsig_combined_data; + wire lsig_packer_full; + wire lsig_set_packer_full__1; + wire m_axi_s2mm_aclk; + wire out; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire [65:0]sig_data_fifo_data_out; + wire sig_data_fifo_dvalid; + wire sig_s_ready_out_reg; + wire sig_stream_rst; + + Arty_Z7_20_axi_vdma_0_0_fifo_generator_ramfifo__parameterized1 \grf.rf + (.DIBDI(DIBDI), + .E(E), + .\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] (\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] (\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] (\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] (\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] (\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] (\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] (\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ), + .\INCLUDE_PACKING.lsig_packer_full_reg (\INCLUDE_PACKING.lsig_packer_full_reg ), + .\gcc0.gc0.count_d1_reg[7] (\gcc0.gc0.count_d1_reg[7] ), + .hold_ff_q_reg(hold_ff_q_reg), + .hold_ff_q_reg_0(hold_ff_q_reg_0), + .lsig_combined_data(lsig_combined_data), + .lsig_packer_full(lsig_packer_full), + .lsig_set_packer_full__1(lsig_set_packer_full__1), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_data_fifo_data_out(sig_data_fifo_data_out), + .sig_data_fifo_dvalid(sig_data_fifo_dvalid), + .sig_s_ready_out_reg(sig_s_ready_out_reg), + .sig_stream_rst(sig_stream_rst)); +endmodule + +(* ORIG_REF_NAME = "fifo_generator_v13_1_3" *) +module Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3 + (sig_m_valid_out_reg, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg , + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg , + FULL, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 , + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 , fifo_dout, m_axi_mm2s_aclk, s_axis_fifo_ainit_nosync_reg, m_axis_mm2s_aclk, - fifo_wren__0, out, - dm2linebuf_mm2s_tdata, - DIN); - output fifo_full_i; + lsig_0ffset_cntr, + mm2s_prmry_resetn, + mm2s_halt, + p_24_out, + hold_ff_q_reg, + DIN, + WR_EN, + dm2linebuf_mm2s_tdata); output sig_m_valid_out_reg; + output \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; + output FULL; + output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ; + output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 ; output [33:0]fifo_dout; input m_axi_mm2s_aclk; input s_axis_fifo_ainit_nosync_reg; input m_axis_mm2s_aclk; - input fifo_wren__0; input out; - input [31:0]dm2linebuf_mm2s_tdata; - input [1:0]DIN; + input lsig_0ffset_cntr; + input mm2s_prmry_resetn; + input mm2s_halt; + input p_24_out; + input hold_ff_q_reg; + input [15:0]DIN; + input WR_EN; + input [17:0]dm2linebuf_mm2s_tdata; - wire [1:0]DIN; - wire [31:0]dm2linebuf_mm2s_tdata; + wire [15:0]DIN; + wire FULL; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 ; + wire \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + wire WR_EN; + wire [17:0]dm2linebuf_mm2s_tdata; wire [33:0]fifo_dout; - wire fifo_full_i; - wire fifo_wren__0; + wire hold_ff_q_reg; + wire lsig_0ffset_cntr; wire m_axi_mm2s_aclk; wire m_axis_mm2s_aclk; + wire mm2s_halt; + wire mm2s_prmry_resetn; wire out; + wire p_24_out; wire s_axis_fifo_ainit_nosync_reg; wire sig_m_valid_out_reg; - Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_builtin \gbi.bi + Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth inst_fifo_gen (.DIN(DIN), + .FULL(FULL), + .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ), + .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ), + .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 ), + .\INCLUDE_UNPACKING.lsig_cmd_loaded_reg (\INCLUDE_UNPACKING.lsig_cmd_loaded_reg ), + .WR_EN(WR_EN), .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), .fifo_dout(fifo_dout), - .fifo_full_i(fifo_full_i), - .fifo_wren__0(fifo_wren__0), + .hold_ff_q_reg(hold_ff_q_reg), + .lsig_0ffset_cntr(lsig_0ffset_cntr), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), .m_axis_mm2s_aclk(m_axis_mm2s_aclk), + .mm2s_halt(mm2s_halt), + .mm2s_prmry_resetn(mm2s_prmry_resetn), .out(out), + .p_24_out(p_24_out), .s_axis_fifo_ainit_nosync_reg(s_axis_fifo_ainit_nosync_reg), .sig_m_valid_out_reg(sig_m_valid_out_reg)); endmodule -(* ORIG_REF_NAME = "fifo_generator_top" *) -module Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized0 - (out, - \sig_user_skid_reg_reg[0] , - dm2linebuf_mm2s_tvalid, - DI, +(* ORIG_REF_NAME = "fifo_generator_v13_1_3" *) +module Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized0 + (FULL, + D, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] , + DOUT, + EMPTY, + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg , + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg , + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg , + strm_not_finished_no_dwidth, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] , + s_axis_s2mm_aclk, + sig_reset_reg, + m_axi_s2mm_aclk, + M_VALID, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 , + s2mm_fsync_out_i, + out, + p_3_out, Q, - dm2linebuf_mm2s_tdata, - hold_ff_q_reg, + \vsize_vid_reg[12] , + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out , + minusOp_1, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 , + s2mm_strm_wready, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] , + DIN, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] , + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] , + minusOp, + RD_EN); + output FULL; + output [12:0]D; + output \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ; + output [8:0]DOUT; + output EMPTY; + output \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg ; + output \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg ; + output \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ; + output strm_not_finished_no_dwidth; + output [12:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] ; + input s_axis_s2mm_aclk; + input sig_reset_reg; + input m_axi_s2mm_aclk; + input M_VALID; + input \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ; + input s2mm_fsync_out_i; + input out; + input p_3_out; + input [6:0]Q; + input [12:0]\vsize_vid_reg[12] ; + input \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ; + input [11:0]minusOp_1; + input \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 ; + input s2mm_strm_wready; + input [0:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] ; + input [8:0]DIN; + input \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ; + input [12:0]\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] ; + input [11:0]minusOp; + input RD_EN; + + wire [12:0]D; + wire [8:0]DIN; + wire [8:0]DOUT; + wire EMPTY; + wire FULL; + wire \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ; + wire [12:0]\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg ; + wire [0:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] ; + wire [12:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ; + wire M_VALID; + wire [6:0]Q; + wire RD_EN; + wire m_axi_s2mm_aclk; + wire [11:0]minusOp; + wire [11:0]minusOp_1; + wire out; + wire p_3_out; + wire s2mm_fsync_out_i; + wire s2mm_strm_wready; + wire s_axis_s2mm_aclk; + wire sig_reset_reg; + wire strm_not_finished_no_dwidth; + wire [12:0]\vsize_vid_reg[12] ; + + Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized0 inst_fifo_gen + (.D(D), + .DIN(DIN), + .DOUT(DOUT), + .EMPTY(EMPTY), + .FULL(FULL), + .\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out (\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] (\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] (\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 (\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg (\GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ), + .M_VALID(M_VALID), + .Q(Q), + .RD_EN(RD_EN), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .minusOp(minusOp), + .minusOp_1(minusOp_1), + .out(out), + .p_3_out(p_3_out), + .s2mm_fsync_out_i(s2mm_fsync_out_i), + .s2mm_strm_wready(s2mm_strm_wready), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk), + .sig_reset_reg(sig_reset_reg), + .strm_not_finished_no_dwidth(strm_not_finished_no_dwidth), + .\vsize_vid_reg[12] (\vsize_vid_reg[12] )); +endmodule + +(* ORIG_REF_NAME = "fifo_generator_v13_1_3" *) +module Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized1 + (DOBDO, + out, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram , sig_ok_to_post_rd_addr_reg, - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , \INCLUDE_UNPACKING.lsig_cmd_loaded_reg , - \INFERRED_GEN.cnt_i_reg[0] , - S, - \count_reg[6] , + hold_ff_q_reg, + \gc1.count_reg[7] , + \INFERRED_GEN.cnt_i_reg[2] , + DIN, + \sig_user_skid_reg_reg[0] , + dm2linebuf_mm2s_tdata, m_axi_mm2s_aclk, - sig_stream_rst, + E, + SR, m_axi_mm2s_rdata, DIBDI, - lsig_0ffset_cntr, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_posted_to_axi_2_reg, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , + Q, lsig_cmd_loaded, hold_ff_q, + ram_full_i_reg, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 , + \sig_token_cntr_reg[0] , \sig_token_cntr_reg[3] , - p_8_out, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_posted_to_axi_2_reg, - sig_posted_to_axi_2_reg_0, - p_0_out, - \INFERRED_GEN.cnt_i_reg[2] , - fifo_wren__0, - mm2s_strm_wvalid0__1, - m_axi_mm2s_rvalid, - sig_advance_pipe9_out__1, - D); + ram_full_i_reg_0); + output [0:0]DOBDO; output out; - output [0:0]\sig_user_skid_reg_reg[0] ; - output dm2linebuf_mm2s_tvalid; - output [3:0]DI; - output [1:0]Q; - output [31:0]dm2linebuf_mm2s_tdata; - output hold_ff_q_reg; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; output sig_ok_to_post_rd_addr_reg; - output \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; output \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; - output \INFERRED_GEN.cnt_i_reg[0] ; - output [3:0]S; - output [1:0]\count_reg[6] ; + output hold_ff_q_reg; + output [0:0]\gc1.count_reg[7] ; + output \INFERRED_GEN.cnt_i_reg[2] ; + output [0:0]DIN; + output \sig_user_skid_reg_reg[0] ; + output [31:0]dm2linebuf_mm2s_tdata; input m_axi_mm2s_aclk; - input sig_stream_rst; + input [0:0]E; + input [0:0]SR; input [63:0]m_axi_mm2s_rdata; input [1:0]DIBDI; - input lsig_0ffset_cntr; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_posted_to_axi_2_reg; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + input [0:0]Q; input lsig_cmd_loaded; input hold_ff_q; + input ram_full_i_reg; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; + input \sig_token_cntr_reg[0] ; input [3:0]\sig_token_cntr_reg[3] ; - input p_8_out; - input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - input sig_posted_to_axi_2_reg; - input sig_posted_to_axi_2_reg_0; - input [0:0]p_0_out; - input [0:0]\INFERRED_GEN.cnt_i_reg[2] ; - input fifo_wren__0; - input mm2s_strm_wvalid0__1; - input m_axi_mm2s_rvalid; - input sig_advance_pipe9_out__1; - input [5:0]D; + input [0:0]ram_full_i_reg_0; - wire [5:0]D; - wire [3:0]DI; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; wire [1:0]DIBDI; + wire [0:0]DIN; + wire [0:0]DOBDO; + wire [0:0]E; wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; wire \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; - wire \INFERRED_GEN.cnt_i_reg[0] ; - wire [0:0]\INFERRED_GEN.cnt_i_reg[2] ; - wire [1:0]Q; - wire [3:0]S; - wire [1:0]\count_reg[6] ; + wire \INFERRED_GEN.cnt_i_reg[2] ; + wire [0:0]Q; + wire [0:0]SR; wire [31:0]dm2linebuf_mm2s_tdata; - wire dm2linebuf_mm2s_tvalid; - wire fifo_wren__0; + wire [0:0]\gc1.count_reg[7] ; wire hold_ff_q; wire hold_ff_q_reg; - wire lsig_0ffset_cntr; wire lsig_cmd_loaded; wire m_axi_mm2s_aclk; wire [63:0]m_axi_mm2s_rdata; - wire m_axi_mm2s_rvalid; - wire mm2s_strm_wvalid0__1; wire out; - wire [0:0]p_0_out; - wire p_8_out; - wire sig_advance_pipe9_out__1; + wire ram_full_i_reg; + wire [0:0]ram_full_i_reg_0; wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; wire sig_ok_to_post_rd_addr_reg; wire sig_posted_to_axi_2_reg; - wire sig_posted_to_axi_2_reg_0; - wire sig_stream_rst; + wire \sig_token_cntr_reg[0] ; wire [3:0]\sig_token_cntr_reg[3] ; - wire [0:0]\sig_user_skid_reg_reg[0] ; + wire \sig_user_skid_reg_reg[0] ; - Arty_Z7_20_axi_vdma_0_0_fifo_generator_ramfifo \grf.rf - (.D(D), - .DI(DI), + Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized1 inst_fifo_gen + (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ), .DIBDI(DIBDI), + .DIN(DIN), + .DOBDO(DOBDO), + .E(E), .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), .\INCLUDE_UNPACKING.lsig_cmd_loaded_reg (\INCLUDE_UNPACKING.lsig_cmd_loaded_reg ), - .\INFERRED_GEN.cnt_i_reg[0] (\INFERRED_GEN.cnt_i_reg[0] ), .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ), .Q(Q), - .S(S), - .\count_reg[6] (\count_reg[6] ), + .SR(SR), .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), - .dm2linebuf_mm2s_tvalid(dm2linebuf_mm2s_tvalid), - .fifo_wren__0(fifo_wren__0), + .\gc1.count_reg[7] (\gc1.count_reg[7] ), .hold_ff_q(hold_ff_q), .hold_ff_q_reg(hold_ff_q_reg), - .lsig_0ffset_cntr(lsig_0ffset_cntr), .lsig_cmd_loaded(lsig_cmd_loaded), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), .m_axi_mm2s_rdata(m_axi_mm2s_rdata), - .m_axi_mm2s_rvalid(m_axi_mm2s_rvalid), - .mm2s_strm_wvalid0__1(mm2s_strm_wvalid0__1), .out(out), - .p_0_out(p_0_out), - .p_8_out(p_8_out), - .sig_advance_pipe9_out__1(sig_advance_pipe9_out__1), + .ram_full_i_reg(ram_full_i_reg), + .ram_full_i_reg_0(ram_full_i_reg_0), .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), .sig_ok_to_post_rd_addr_reg(sig_ok_to_post_rd_addr_reg), .sig_posted_to_axi_2_reg(sig_posted_to_axi_2_reg), - .sig_posted_to_axi_2_reg_0(sig_posted_to_axi_2_reg_0), - .sig_stream_rst(sig_stream_rst), + .\sig_token_cntr_reg[0] (\sig_token_cntr_reg[0] ), .\sig_token_cntr_reg[3] (\sig_token_cntr_reg[3] ), .\sig_user_skid_reg_reg[0] (\sig_user_skid_reg_reg[0] )); endmodule (* ORIG_REF_NAME = "fifo_generator_v13_1_3" *) -module Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3 - (fifo_full_i, - sig_m_valid_out_reg, - fifo_dout, - m_axi_mm2s_aclk, - s_axis_fifo_ainit_nosync_reg, - m_axis_mm2s_aclk, - fifo_wren__0, - out, - dm2linebuf_mm2s_tdata, - DIN); - output fifo_full_i; - output sig_m_valid_out_reg; - output [33:0]fifo_dout; - input m_axi_mm2s_aclk; - input s_axis_fifo_ainit_nosync_reg; - input m_axis_mm2s_aclk; - input fifo_wren__0; - input out; - input [31:0]dm2linebuf_mm2s_tdata; - input [1:0]DIN; +module Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized2 + (hold_ff_q_reg, + D, + sig_xfer_is_seq_reg_reg, + \sig_child_addr_cntr_lsh_reg[11] , + E, + S, + \sig_xfer_len_reg_reg[4] , + \sig_xfer_len_reg_reg[5] , + sig_xfer_is_seq_reg_reg_0, + sig_xfer_cmd_cmplt_reg0, + sig_sf2pcc_xfer_valid, + sig_ibtt2dre_tready, + sig_csm_state_ns1, + \gpr1.dout_i_reg[1] , + \gpr1.dout_i_reg[1]_0 , + O, + CO, + \sig_child_addr_cntr_lsh_reg[7] , + sig_stream_rst, + m_axi_s2mm_aclk, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + p_32_out, + hold_ff_q, + sig_adjusted_addr_incr, + sig_clr_dbc_reg_reg, + sig_csm_pop_child_cmd, + sig_child_qual_first_of_2, + sig_child_qual_error_reg, + lsig_packer_full, + ram_full_i_reg, + \gpr1.dout_i_reg[3] , + \gpr1.dout_i_reg[7] , + sig_child_addr_cntr_lsh_reg, + p_0_out); + output hold_ff_q_reg; + output [2:0]D; + output [9:0]sig_xfer_is_seq_reg_reg; + output [0:0]\sig_child_addr_cntr_lsh_reg[11] ; + output [0:0]E; + output [3:0]S; + output [3:0]\sig_xfer_len_reg_reg[4] ; + output [0:0]\sig_xfer_len_reg_reg[5] ; + output sig_xfer_is_seq_reg_reg_0; + output sig_xfer_cmd_cmplt_reg0; + output sig_sf2pcc_xfer_valid; + output sig_ibtt2dre_tready; + output sig_csm_state_ns1; + output [2:0]\gpr1.dout_i_reg[1] ; + output [2:0]\gpr1.dout_i_reg[1]_0 ; + output [3:0]O; + output [0:0]CO; + output [3:0]\sig_child_addr_cntr_lsh_reg[7] ; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input p_32_out; + input hold_ff_q; + input [8:0]sig_adjusted_addr_incr; + input sig_clr_dbc_reg_reg; + input sig_csm_pop_child_cmd; + input sig_child_qual_first_of_2; + input sig_child_qual_error_reg; + input lsig_packer_full; + input ram_full_i_reg; + input [3:0]\gpr1.dout_i_reg[3] ; + input [3:0]\gpr1.dout_i_reg[7] ; + input [2:0]sig_child_addr_cntr_lsh_reg; + input [10:0]p_0_out; - wire [1:0]DIN; - wire [31:0]dm2linebuf_mm2s_tdata; - wire [33:0]fifo_dout; - wire fifo_full_i; - wire fifo_wren__0; - wire m_axi_mm2s_aclk; - wire m_axis_mm2s_aclk; - wire out; - wire s_axis_fifo_ainit_nosync_reg; - wire sig_m_valid_out_reg; + wire [0:0]CO; + wire [2:0]D; + wire [0:0]E; + wire [3:0]O; + wire [3:0]S; + wire [2:0]\gpr1.dout_i_reg[1] ; + wire [2:0]\gpr1.dout_i_reg[1]_0 ; + wire [3:0]\gpr1.dout_i_reg[3] ; + wire [3:0]\gpr1.dout_i_reg[7] ; + wire hold_ff_q; + wire hold_ff_q_reg; + wire lsig_packer_full; + wire m_axi_s2mm_aclk; + wire [10:0]p_0_out; + wire p_32_out; + wire ram_full_i_reg; + wire [8:0]sig_adjusted_addr_incr; + wire [2:0]sig_child_addr_cntr_lsh_reg; + wire [0:0]\sig_child_addr_cntr_lsh_reg[11] ; + wire [3:0]\sig_child_addr_cntr_lsh_reg[7] ; + wire sig_child_qual_error_reg; + wire sig_child_qual_first_of_2; + wire sig_clr_dbc_reg_reg; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_csm_pop_child_cmd; + wire sig_csm_state_ns1; + wire sig_ibtt2dre_tready; + wire sig_sf2pcc_xfer_valid; + wire sig_stream_rst; + wire sig_xfer_cmd_cmplt_reg0; + wire [9:0]sig_xfer_is_seq_reg_reg; + wire sig_xfer_is_seq_reg_reg_0; + wire [3:0]\sig_xfer_len_reg_reg[4] ; + wire [0:0]\sig_xfer_len_reg_reg[5] ; - Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth inst_fifo_gen - (.DIN(DIN), - .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), - .fifo_dout(fifo_dout), - .fifo_full_i(fifo_full_i), - .fifo_wren__0(fifo_wren__0), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axis_mm2s_aclk(m_axis_mm2s_aclk), - .out(out), - .s_axis_fifo_ainit_nosync_reg(s_axis_fifo_ainit_nosync_reg), - .sig_m_valid_out_reg(sig_m_valid_out_reg)); + Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized2 inst_fifo_gen + (.CO(CO), + .D(D), + .E(E), + .O(O), + .S(S), + .\gpr1.dout_i_reg[1] (\gpr1.dout_i_reg[1] ), + .\gpr1.dout_i_reg[1]_0 (\gpr1.dout_i_reg[1]_0 ), + .\gpr1.dout_i_reg[3] (\gpr1.dout_i_reg[3] ), + .\gpr1.dout_i_reg[7] (\gpr1.dout_i_reg[7] ), + .hold_ff_q(hold_ff_q), + .hold_ff_q_reg(hold_ff_q_reg), + .lsig_packer_full(lsig_packer_full), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .p_0_out(p_0_out), + .p_32_out(p_32_out), + .ram_full_i_reg(ram_full_i_reg), + .sig_adjusted_addr_incr(sig_adjusted_addr_incr), + .sig_child_addr_cntr_lsh_reg(sig_child_addr_cntr_lsh_reg), + .\sig_child_addr_cntr_lsh_reg[11] (\sig_child_addr_cntr_lsh_reg[11] ), + .\sig_child_addr_cntr_lsh_reg[7] (\sig_child_addr_cntr_lsh_reg[7] ), + .sig_child_qual_error_reg(sig_child_qual_error_reg), + .sig_child_qual_first_of_2(sig_child_qual_first_of_2), + .sig_clr_dbc_reg_reg(sig_clr_dbc_reg_reg), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_csm_pop_child_cmd(sig_csm_pop_child_cmd), + .sig_csm_state_ns1(sig_csm_state_ns1), + .sig_ibtt2dre_tready(sig_ibtt2dre_tready), + .sig_sf2pcc_xfer_valid(sig_sf2pcc_xfer_valid), + .sig_stream_rst(sig_stream_rst), + .sig_xfer_cmd_cmplt_reg0(sig_xfer_cmd_cmplt_reg0), + .sig_xfer_is_seq_reg_reg(sig_xfer_is_seq_reg_reg), + .sig_xfer_is_seq_reg_reg_0(sig_xfer_is_seq_reg_reg_0), + .\sig_xfer_len_reg_reg[4] (\sig_xfer_len_reg_reg[4] ), + .\sig_xfer_len_reg_reg[5] (\sig_xfer_len_reg_reg[5] )); endmodule (* ORIG_REF_NAME = "fifo_generator_v13_1_3" *) -module Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized0 - (out, - \sig_user_skid_reg_reg[0] , - dm2linebuf_mm2s_tvalid, - DI, - Q, - dm2linebuf_mm2s_tdata, +module Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized3 + (sig_data_fifo_data_out, + out, + \gcc0.gc0.count_d1_reg[7] , hold_ff_q_reg, - sig_ok_to_post_rd_addr_reg, - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , - \INCLUDE_UNPACKING.lsig_cmd_loaded_reg , - \INFERRED_GEN.cnt_i_reg[0] , - S, - \count_reg[6] , - m_axi_mm2s_aclk, + \INCLUDE_PACKING.lsig_packer_full_reg , + E, + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] , + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] , + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] , + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] , + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] , + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] , + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] , + sig_data_fifo_dvalid, + m_axi_s2mm_aclk, sig_stream_rst, - m_axi_mm2s_rdata, + lsig_combined_data, DIBDI, - lsig_0ffset_cntr, - lsig_cmd_loaded, - hold_ff_q, - \sig_token_cntr_reg[3] , - p_8_out, sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_posted_to_axi_2_reg, - sig_posted_to_axi_2_reg_0, - p_0_out, - \INFERRED_GEN.cnt_i_reg[2] , - fifo_wren__0, - mm2s_strm_wvalid0__1, - m_axi_mm2s_rvalid, - sig_advance_pipe9_out__1, - D); + hold_ff_q_reg_0, + sig_s_ready_out_reg, + lsig_set_packer_full__1, + lsig_packer_full, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ); + output [65:0]sig_data_fifo_data_out; output out; - output [0:0]\sig_user_skid_reg_reg[0] ; - output dm2linebuf_mm2s_tvalid; - output [3:0]DI; - output [1:0]Q; - output [31:0]dm2linebuf_mm2s_tdata; + output \gcc0.gc0.count_d1_reg[7] ; output hold_ff_q_reg; - output sig_ok_to_post_rd_addr_reg; - output \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; - output \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; - output \INFERRED_GEN.cnt_i_reg[0] ; - output [3:0]S; - output [1:0]\count_reg[6] ; - input m_axi_mm2s_aclk; + output \INCLUDE_PACKING.lsig_packer_full_reg ; + output [0:0]E; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] ; + output sig_data_fifo_dvalid; + input m_axi_s2mm_aclk; input sig_stream_rst; - input [63:0]m_axi_mm2s_rdata; + input [63:0]lsig_combined_data; input [1:0]DIBDI; - input lsig_0ffset_cntr; - input lsig_cmd_loaded; - input hold_ff_q; - input [3:0]\sig_token_cntr_reg[3] ; - input p_8_out; input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - input sig_posted_to_axi_2_reg; - input sig_posted_to_axi_2_reg_0; - input [0:0]p_0_out; - input [0:0]\INFERRED_GEN.cnt_i_reg[2] ; - input fifo_wren__0; - input mm2s_strm_wvalid0__1; - input m_axi_mm2s_rvalid; - input sig_advance_pipe9_out__1; - input [5:0]D; + input hold_ff_q_reg_0; + input sig_s_ready_out_reg; + input lsig_set_packer_full__1; + input lsig_packer_full; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ; - wire [5:0]D; - wire [3:0]DI; wire [1:0]DIBDI; - wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; - wire \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; - wire \INFERRED_GEN.cnt_i_reg[0] ; - wire [0:0]\INFERRED_GEN.cnt_i_reg[2] ; - wire [1:0]Q; - wire [3:0]S; - wire [1:0]\count_reg[6] ; - wire [31:0]dm2linebuf_mm2s_tdata; - wire dm2linebuf_mm2s_tvalid; - wire fifo_wren__0; - wire hold_ff_q; + wire [0:0]E; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ; + wire \INCLUDE_PACKING.lsig_packer_full_reg ; + wire \gcc0.gc0.count_d1_reg[7] ; wire hold_ff_q_reg; - wire lsig_0ffset_cntr; - wire lsig_cmd_loaded; - wire m_axi_mm2s_aclk; - wire [63:0]m_axi_mm2s_rdata; - wire m_axi_mm2s_rvalid; - wire mm2s_strm_wvalid0__1; + wire hold_ff_q_reg_0; + wire [63:0]lsig_combined_data; + wire lsig_packer_full; + wire lsig_set_packer_full__1; + wire m_axi_s2mm_aclk; wire out; - wire [0:0]p_0_out; - wire p_8_out; - wire sig_advance_pipe9_out__1; wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - wire sig_ok_to_post_rd_addr_reg; - wire sig_posted_to_axi_2_reg; - wire sig_posted_to_axi_2_reg_0; + wire [65:0]sig_data_fifo_data_out; + wire sig_data_fifo_dvalid; + wire sig_s_ready_out_reg; wire sig_stream_rst; - wire [3:0]\sig_token_cntr_reg[3] ; - wire [0:0]\sig_user_skid_reg_reg[0] ; - Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized0 inst_fifo_gen - (.D(D), - .DI(DI), - .DIBDI(DIBDI), - .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), - .\INCLUDE_UNPACKING.lsig_cmd_loaded_reg (\INCLUDE_UNPACKING.lsig_cmd_loaded_reg ), - .\INFERRED_GEN.cnt_i_reg[0] (\INFERRED_GEN.cnt_i_reg[0] ), - .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ), - .Q(Q), - .S(S), - .\count_reg[6] (\count_reg[6] ), - .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), - .dm2linebuf_mm2s_tvalid(dm2linebuf_mm2s_tvalid), - .fifo_wren__0(fifo_wren__0), - .hold_ff_q(hold_ff_q), + Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized3 inst_fifo_gen + (.DIBDI(DIBDI), + .E(E), + .\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] (\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] (\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] (\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] (\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] (\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] (\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] (\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ), + .\INCLUDE_PACKING.lsig_packer_full_reg (\INCLUDE_PACKING.lsig_packer_full_reg ), + .\gcc0.gc0.count_d1_reg[7] (\gcc0.gc0.count_d1_reg[7] ), .hold_ff_q_reg(hold_ff_q_reg), - .lsig_0ffset_cntr(lsig_0ffset_cntr), - .lsig_cmd_loaded(lsig_cmd_loaded), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axi_mm2s_rdata(m_axi_mm2s_rdata), - .m_axi_mm2s_rvalid(m_axi_mm2s_rvalid), - .mm2s_strm_wvalid0__1(mm2s_strm_wvalid0__1), + .hold_ff_q_reg_0(hold_ff_q_reg_0), + .lsig_combined_data(lsig_combined_data), + .lsig_packer_full(lsig_packer_full), + .lsig_set_packer_full__1(lsig_set_packer_full__1), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), .out(out), - .p_0_out(p_0_out), - .p_8_out(p_8_out), - .sig_advance_pipe9_out__1(sig_advance_pipe9_out__1), .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .sig_ok_to_post_rd_addr_reg(sig_ok_to_post_rd_addr_reg), - .sig_posted_to_axi_2_reg(sig_posted_to_axi_2_reg), - .sig_posted_to_axi_2_reg_0(sig_posted_to_axi_2_reg_0), - .sig_stream_rst(sig_stream_rst), - .\sig_token_cntr_reg[3] (\sig_token_cntr_reg[3] ), - .\sig_user_skid_reg_reg[0] (\sig_user_skid_reg_reg[0] )); + .sig_data_fifo_data_out(sig_data_fifo_data_out), + .sig_data_fifo_dvalid(sig_data_fifo_dvalid), + .sig_s_ready_out_reg(sig_s_ready_out_reg), + .sig_stream_rst(sig_stream_rst)); endmodule (* ORIG_REF_NAME = "fifo_generator_v13_1_3_builtin" *) module Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_builtin - (fifo_full_i, - sig_m_valid_out_reg, + (sig_m_valid_out_reg, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg , + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg , + FULL, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 , + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 , fifo_dout, m_axi_mm2s_aclk, s_axis_fifo_ainit_nosync_reg, m_axis_mm2s_aclk, - fifo_wren__0, out, - dm2linebuf_mm2s_tdata, - DIN); - output fifo_full_i; + lsig_0ffset_cntr, + mm2s_prmry_resetn, + mm2s_halt, + p_24_out, + hold_ff_q_reg, + DIN, + WR_EN, + dm2linebuf_mm2s_tdata); output sig_m_valid_out_reg; + output \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; + output FULL; + output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ; + output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 ; output [33:0]fifo_dout; input m_axi_mm2s_aclk; input s_axis_fifo_ainit_nosync_reg; input m_axis_mm2s_aclk; - input fifo_wren__0; input out; - input [31:0]dm2linebuf_mm2s_tdata; - input [1:0]DIN; + input lsig_0ffset_cntr; + input mm2s_prmry_resetn; + input mm2s_halt; + input p_24_out; + input hold_ff_q_reg; + input [15:0]DIN; + input WR_EN; + input [17:0]dm2linebuf_mm2s_tdata; - wire [1:0]DIN; - wire [31:0]dm2linebuf_mm2s_tdata; + wire [15:0]DIN; + wire FULL; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 ; + wire \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + wire WR_EN; + wire [17:0]dm2linebuf_mm2s_tdata; wire [33:0]fifo_dout; - wire fifo_full_i; - wire fifo_wren__0; + wire hold_ff_q_reg; + wire lsig_0ffset_cntr; wire m_axi_mm2s_aclk; wire m_axis_mm2s_aclk; + wire mm2s_halt; + wire mm2s_prmry_resetn; wire out; + wire p_24_out; wire rd_rst_i; wire s_axis_fifo_ainit_nosync_reg; wire sig_m_valid_out_reg; - Arty_Z7_20_axi_vdma_0_0_reset_builtin \g7ser_birst.rstbt + Arty_Z7_20_axi_vdma_0_0_reset_builtin_39 \g7ser_birst.rstbt (.RST(rd_rst_i), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), .m_axis_mm2s_aclk(m_axis_mm2s_aclk), .s_axis_fifo_ainit_nosync_reg(s_axis_fifo_ainit_nosync_reg)); Arty_Z7_20_axi_vdma_0_0_builtin_top_v6 \v7_bi_fifo.fblk (.DIN(DIN), + .FULL(FULL), + .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ), + .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ), + .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 ), + .\INCLUDE_UNPACKING.lsig_cmd_loaded_reg (\INCLUDE_UNPACKING.lsig_cmd_loaded_reg ), .RST(rd_rst_i), + .WR_EN(WR_EN), .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), .fifo_dout(fifo_dout), - .fifo_full_i(fifo_full_i), - .fifo_wren__0(fifo_wren__0), + .hold_ff_q_reg(hold_ff_q_reg), + .lsig_0ffset_cntr(lsig_0ffset_cntr), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), .m_axis_mm2s_aclk(m_axis_mm2s_aclk), + .mm2s_halt(mm2s_halt), + .mm2s_prmry_resetn(mm2s_prmry_resetn), .out(out), + .p_24_out(p_24_out), .sig_m_valid_out_reg(sig_m_valid_out_reg)); endmodule +(* ORIG_REF_NAME = "fifo_generator_v13_1_3_builtin" *) +module Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_builtin__parameterized0 + (FULL, + D, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] , + DOUT, + EMPTY, + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg , + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg , + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg , + strm_not_finished_no_dwidth, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] , + s_axis_s2mm_aclk, + sig_reset_reg, + m_axi_s2mm_aclk, + M_VALID, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 , + s2mm_fsync_out_i, + out, + p_3_out, + Q, + \vsize_vid_reg[12] , + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out , + minusOp_1, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 , + s2mm_strm_wready, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] , + DIN, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] , + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] , + minusOp, + RD_EN); + output FULL; + output [12:0]D; + output \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ; + output [8:0]DOUT; + output EMPTY; + output \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg ; + output \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg ; + output \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ; + output strm_not_finished_no_dwidth; + output [12:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] ; + input s_axis_s2mm_aclk; + input sig_reset_reg; + input m_axi_s2mm_aclk; + input M_VALID; + input \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ; + input s2mm_fsync_out_i; + input out; + input p_3_out; + input [6:0]Q; + input [12:0]\vsize_vid_reg[12] ; + input \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ; + input [11:0]minusOp_1; + input \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 ; + input s2mm_strm_wready; + input [0:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] ; + input [8:0]DIN; + input \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ; + input [12:0]\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] ; + input [11:0]minusOp; + input RD_EN; + + wire [12:0]D; + wire [8:0]DIN; + wire [8:0]DOUT; + wire EMPTY; + wire FULL; + wire \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ; + wire [12:0]\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg ; + wire [0:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] ; + wire [12:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ; + wire M_VALID; + wire [6:0]Q; + wire RD_EN; + wire m_axi_s2mm_aclk; + wire [11:0]minusOp; + wire [11:0]minusOp_1; + wire out; + wire p_3_out; + wire s2mm_fsync_out_i; + wire s2mm_strm_wready; + wire s_axis_s2mm_aclk; + wire sig_reset_reg; + wire strm_not_finished_no_dwidth; + wire [12:0]\vsize_vid_reg[12] ; + wire wr_rst_i; + + Arty_Z7_20_axi_vdma_0_0_reset_builtin \g7ser_birst.rstbt + (.RST(wr_rst_i), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk), + .sig_reset_reg(sig_reset_reg)); + Arty_Z7_20_axi_vdma_0_0_builtin_top_v6__parameterized0 \v7_bi_fifo.fblk + (.D(D), + .DIN(DIN), + .DOUT(DOUT), + .EMPTY(EMPTY), + .FULL(FULL), + .\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out (\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] (\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] (\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 (\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg (\GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ), + .M_VALID(M_VALID), + .Q(Q), + .RD_EN(RD_EN), + .RST(wr_rst_i), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .minusOp(minusOp), + .minusOp_1(minusOp_1), + .out(out), + .p_3_out(p_3_out), + .s2mm_fsync_out_i(s2mm_fsync_out_i), + .s2mm_strm_wready(s2mm_strm_wready), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk), + .strm_not_finished_no_dwidth(strm_not_finished_no_dwidth), + .\vsize_vid_reg[12] (\vsize_vid_reg[12] )); +endmodule + (* ORIG_REF_NAME = "fifo_generator_v13_1_3_synth" *) module Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth - (fifo_full_i, - sig_m_valid_out_reg, + (sig_m_valid_out_reg, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg , + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg , + FULL, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 , + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 , fifo_dout, m_axi_mm2s_aclk, s_axis_fifo_ainit_nosync_reg, m_axis_mm2s_aclk, - fifo_wren__0, out, - dm2linebuf_mm2s_tdata, - DIN); - output fifo_full_i; + lsig_0ffset_cntr, + mm2s_prmry_resetn, + mm2s_halt, + p_24_out, + hold_ff_q_reg, + DIN, + WR_EN, + dm2linebuf_mm2s_tdata); output sig_m_valid_out_reg; + output \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; + output FULL; + output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ; + output \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 ; output [33:0]fifo_dout; input m_axi_mm2s_aclk; input s_axis_fifo_ainit_nosync_reg; input m_axis_mm2s_aclk; - input fifo_wren__0; input out; - input [31:0]dm2linebuf_mm2s_tdata; - input [1:0]DIN; + input lsig_0ffset_cntr; + input mm2s_prmry_resetn; + input mm2s_halt; + input p_24_out; + input hold_ff_q_reg; + input [15:0]DIN; + input WR_EN; + input [17:0]dm2linebuf_mm2s_tdata; - wire [1:0]DIN; - wire [31:0]dm2linebuf_mm2s_tdata; + wire [15:0]DIN; + wire FULL; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ; + wire \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 ; + wire \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + wire WR_EN; + wire [17:0]dm2linebuf_mm2s_tdata; wire [33:0]fifo_dout; - wire fifo_full_i; - wire fifo_wren__0; + wire hold_ff_q_reg; + wire lsig_0ffset_cntr; wire m_axi_mm2s_aclk; wire m_axis_mm2s_aclk; + wire mm2s_halt; + wire mm2s_prmry_resetn; wire out; + wire p_24_out; wire s_axis_fifo_ainit_nosync_reg; wire sig_m_valid_out_reg; Arty_Z7_20_axi_vdma_0_0_fifo_generator_top \gconvfifo.rf (.DIN(DIN), + .FULL(FULL), + .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg ), + .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0 ), + .\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 (\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1 ), + .\INCLUDE_UNPACKING.lsig_cmd_loaded_reg (\INCLUDE_UNPACKING.lsig_cmd_loaded_reg ), + .WR_EN(WR_EN), .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), .fifo_dout(fifo_dout), - .fifo_full_i(fifo_full_i), - .fifo_wren__0(fifo_wren__0), + .hold_ff_q_reg(hold_ff_q_reg), + .lsig_0ffset_cntr(lsig_0ffset_cntr), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), .m_axis_mm2s_aclk(m_axis_mm2s_aclk), + .mm2s_halt(mm2s_halt), + .mm2s_prmry_resetn(mm2s_prmry_resetn), .out(out), + .p_24_out(p_24_out), .s_axis_fifo_ainit_nosync_reg(s_axis_fifo_ainit_nosync_reg), .sig_m_valid_out_reg(sig_m_valid_out_reg)); endmodule (* ORIG_REF_NAME = "fifo_generator_v13_1_3_synth" *) module Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized0 - (out, - \sig_user_skid_reg_reg[0] , - dm2linebuf_mm2s_tvalid, - DI, + (FULL, + D, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] , + DOUT, + EMPTY, + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg , + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg , + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg , + strm_not_finished_no_dwidth, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] , + s_axis_s2mm_aclk, + sig_reset_reg, + m_axi_s2mm_aclk, + M_VALID, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 , + s2mm_fsync_out_i, + out, + p_3_out, Q, - dm2linebuf_mm2s_tdata, - hold_ff_q_reg, + \vsize_vid_reg[12] , + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out , + minusOp_1, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 , + s2mm_strm_wready, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] , + DIN, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] , + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] , + minusOp, + RD_EN); + output FULL; + output [12:0]D; + output \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ; + output [8:0]DOUT; + output EMPTY; + output \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg ; + output \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg ; + output \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ; + output strm_not_finished_no_dwidth; + output [12:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] ; + input s_axis_s2mm_aclk; + input sig_reset_reg; + input m_axi_s2mm_aclk; + input M_VALID; + input \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ; + input s2mm_fsync_out_i; + input out; + input p_3_out; + input [6:0]Q; + input [12:0]\vsize_vid_reg[12] ; + input \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ; + input [11:0]minusOp_1; + input \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 ; + input s2mm_strm_wready; + input [0:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] ; + input [8:0]DIN; + input \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ; + input [12:0]\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] ; + input [11:0]minusOp; + input RD_EN; + + wire [12:0]D; + wire [8:0]DIN; + wire [8:0]DOUT; + wire EMPTY; + wire FULL; + wire \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ; + wire [12:0]\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 ; + wire \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg ; + wire [0:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] ; + wire [12:0]\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] ; + wire \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ; + wire M_VALID; + wire [6:0]Q; + wire RD_EN; + wire m_axi_s2mm_aclk; + wire [11:0]minusOp; + wire [11:0]minusOp_1; + wire out; + wire p_3_out; + wire s2mm_fsync_out_i; + wire s2mm_strm_wready; + wire s_axis_s2mm_aclk; + wire sig_reset_reg; + wire strm_not_finished_no_dwidth; + wire [12:0]\vsize_vid_reg[12] ; + + Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized0 \gconvfifo.rf + (.D(D), + .DIN(DIN), + .DOUT(DOUT), + .EMPTY(EMPTY), + .FULL(FULL), + .\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out (\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] (\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12] ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] (\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12] ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 (\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0 ), + .\GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg (\GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0 ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0] ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12] ), + .\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] (\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6] ), + .M_VALID(M_VALID), + .Q(Q), + .RD_EN(RD_EN), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .minusOp(minusOp), + .minusOp_1(minusOp_1), + .out(out), + .p_3_out(p_3_out), + .s2mm_fsync_out_i(s2mm_fsync_out_i), + .s2mm_strm_wready(s2mm_strm_wready), + .s_axis_s2mm_aclk(s_axis_s2mm_aclk), + .sig_reset_reg(sig_reset_reg), + .strm_not_finished_no_dwidth(strm_not_finished_no_dwidth), + .\vsize_vid_reg[12] (\vsize_vid_reg[12] )); +endmodule + +(* ORIG_REF_NAME = "fifo_generator_v13_1_3_synth" *) +module Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized1 + (DOBDO, + out, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram , sig_ok_to_post_rd_addr_reg, - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , \INCLUDE_UNPACKING.lsig_cmd_loaded_reg , - \INFERRED_GEN.cnt_i_reg[0] , - S, - \count_reg[6] , + hold_ff_q_reg, + \gc1.count_reg[7] , + \INFERRED_GEN.cnt_i_reg[2] , + DIN, + \sig_user_skid_reg_reg[0] , + dm2linebuf_mm2s_tdata, m_axi_mm2s_aclk, - sig_stream_rst, + E, + SR, m_axi_mm2s_rdata, DIBDI, - lsig_0ffset_cntr, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_posted_to_axi_2_reg, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , + Q, lsig_cmd_loaded, hold_ff_q, + ram_full_i_reg, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 , + \sig_token_cntr_reg[0] , \sig_token_cntr_reg[3] , - p_8_out, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_posted_to_axi_2_reg, - sig_posted_to_axi_2_reg_0, - p_0_out, - \INFERRED_GEN.cnt_i_reg[2] , - fifo_wren__0, - mm2s_strm_wvalid0__1, - m_axi_mm2s_rvalid, - sig_advance_pipe9_out__1, - D); + ram_full_i_reg_0); + output [0:0]DOBDO; output out; - output [0:0]\sig_user_skid_reg_reg[0] ; - output dm2linebuf_mm2s_tvalid; - output [3:0]DI; - output [1:0]Q; - output [31:0]dm2linebuf_mm2s_tdata; - output hold_ff_q_reg; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; output sig_ok_to_post_rd_addr_reg; - output \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; output \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; - output \INFERRED_GEN.cnt_i_reg[0] ; - output [3:0]S; - output [1:0]\count_reg[6] ; + output hold_ff_q_reg; + output \gc1.count_reg[7] ; + output \INFERRED_GEN.cnt_i_reg[2] ; + output [0:0]DIN; + output \sig_user_skid_reg_reg[0] ; + output [31:0]dm2linebuf_mm2s_tdata; input m_axi_mm2s_aclk; - input sig_stream_rst; + input [0:0]E; + input [0:0]SR; input [63:0]m_axi_mm2s_rdata; input [1:0]DIBDI; - input lsig_0ffset_cntr; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_posted_to_axi_2_reg; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + input [0:0]Q; input lsig_cmd_loaded; input hold_ff_q; + input ram_full_i_reg; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; + input \sig_token_cntr_reg[0] ; input [3:0]\sig_token_cntr_reg[3] ; - input p_8_out; - input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - input sig_posted_to_axi_2_reg; - input sig_posted_to_axi_2_reg_0; - input [0:0]p_0_out; - input [0:0]\INFERRED_GEN.cnt_i_reg[2] ; - input fifo_wren__0; - input mm2s_strm_wvalid0__1; - input m_axi_mm2s_rvalid; - input sig_advance_pipe9_out__1; - input [5:0]D; + input [0:0]ram_full_i_reg_0; - wire [5:0]D; - wire [3:0]DI; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; wire [1:0]DIBDI; + wire [0:0]DIN; + wire [0:0]DOBDO; + wire [0:0]E; wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; wire \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; - wire \INFERRED_GEN.cnt_i_reg[0] ; - wire [0:0]\INFERRED_GEN.cnt_i_reg[2] ; - wire [1:0]Q; - wire [3:0]S; - wire [1:0]\count_reg[6] ; + wire \INFERRED_GEN.cnt_i_reg[2] ; + wire [0:0]Q; + wire [0:0]SR; wire [31:0]dm2linebuf_mm2s_tdata; - wire dm2linebuf_mm2s_tvalid; - wire fifo_wren__0; + wire \gc1.count_reg[7] ; wire hold_ff_q; wire hold_ff_q_reg; - wire lsig_0ffset_cntr; wire lsig_cmd_loaded; wire m_axi_mm2s_aclk; wire [63:0]m_axi_mm2s_rdata; - wire m_axi_mm2s_rvalid; - wire mm2s_strm_wvalid0__1; wire out; - wire [0:0]p_0_out; - wire p_8_out; - wire sig_advance_pipe9_out__1; + wire ram_full_i_reg; + wire [0:0]ram_full_i_reg_0; wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; wire sig_ok_to_post_rd_addr_reg; wire sig_posted_to_axi_2_reg; - wire sig_posted_to_axi_2_reg_0; - wire sig_stream_rst; + wire \sig_token_cntr_reg[0] ; wire [3:0]\sig_token_cntr_reg[3] ; - wire [0:0]\sig_user_skid_reg_reg[0] ; + wire \sig_user_skid_reg_reg[0] ; - Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized0 \gconvfifo.rf - (.D(D), - .DI(DI), + Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized1 \gconvfifo.rf + (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ), .DIBDI(DIBDI), + .DIN(DIN), + .DOBDO(DOBDO), + .E(E), .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), .\INCLUDE_UNPACKING.lsig_cmd_loaded_reg (\INCLUDE_UNPACKING.lsig_cmd_loaded_reg ), - .\INFERRED_GEN.cnt_i_reg[0] (\INFERRED_GEN.cnt_i_reg[0] ), .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ), .Q(Q), - .S(S), - .\count_reg[6] (\count_reg[6] ), + .SR(SR), .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), - .dm2linebuf_mm2s_tvalid(dm2linebuf_mm2s_tvalid), - .fifo_wren__0(fifo_wren__0), + .\gc1.count_reg[7] (\gc1.count_reg[7] ), .hold_ff_q(hold_ff_q), .hold_ff_q_reg(hold_ff_q_reg), - .lsig_0ffset_cntr(lsig_0ffset_cntr), .lsig_cmd_loaded(lsig_cmd_loaded), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), .m_axi_mm2s_rdata(m_axi_mm2s_rdata), - .m_axi_mm2s_rvalid(m_axi_mm2s_rvalid), - .mm2s_strm_wvalid0__1(mm2s_strm_wvalid0__1), .out(out), - .p_0_out(p_0_out), - .p_8_out(p_8_out), - .sig_advance_pipe9_out__1(sig_advance_pipe9_out__1), + .ram_full_i_reg(ram_full_i_reg), + .ram_full_i_reg_0(ram_full_i_reg_0), .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), .sig_ok_to_post_rd_addr_reg(sig_ok_to_post_rd_addr_reg), .sig_posted_to_axi_2_reg(sig_posted_to_axi_2_reg), - .sig_posted_to_axi_2_reg_0(sig_posted_to_axi_2_reg_0), - .sig_stream_rst(sig_stream_rst), + .\sig_token_cntr_reg[0] (\sig_token_cntr_reg[0] ), .\sig_token_cntr_reg[3] (\sig_token_cntr_reg[3] ), .\sig_user_skid_reg_reg[0] (\sig_user_skid_reg_reg[0] )); endmodule +(* ORIG_REF_NAME = "fifo_generator_v13_1_3_synth" *) +module Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized2 + (hold_ff_q_reg, + D, + sig_xfer_is_seq_reg_reg, + \sig_child_addr_cntr_lsh_reg[11] , + E, + S, + \sig_xfer_len_reg_reg[4] , + \sig_xfer_len_reg_reg[5] , + sig_xfer_is_seq_reg_reg_0, + sig_xfer_cmd_cmplt_reg0, + sig_sf2pcc_xfer_valid, + sig_ibtt2dre_tready, + sig_csm_state_ns1, + \gpr1.dout_i_reg[1] , + \gpr1.dout_i_reg[1]_0 , + O, + CO, + \sig_child_addr_cntr_lsh_reg[7] , + sig_stream_rst, + m_axi_s2mm_aclk, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + p_32_out, + hold_ff_q, + sig_adjusted_addr_incr, + sig_clr_dbc_reg_reg, + sig_csm_pop_child_cmd, + sig_child_qual_first_of_2, + sig_child_qual_error_reg, + lsig_packer_full, + ram_full_i_reg, + \gpr1.dout_i_reg[3] , + \gpr1.dout_i_reg[7] , + sig_child_addr_cntr_lsh_reg, + p_0_out); + output hold_ff_q_reg; + output [2:0]D; + output [9:0]sig_xfer_is_seq_reg_reg; + output [0:0]\sig_child_addr_cntr_lsh_reg[11] ; + output [0:0]E; + output [3:0]S; + output [3:0]\sig_xfer_len_reg_reg[4] ; + output [0:0]\sig_xfer_len_reg_reg[5] ; + output sig_xfer_is_seq_reg_reg_0; + output sig_xfer_cmd_cmplt_reg0; + output sig_sf2pcc_xfer_valid; + output sig_ibtt2dre_tready; + output sig_csm_state_ns1; + output [2:0]\gpr1.dout_i_reg[1] ; + output [2:0]\gpr1.dout_i_reg[1]_0 ; + output [3:0]O; + output [0:0]CO; + output [3:0]\sig_child_addr_cntr_lsh_reg[7] ; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input p_32_out; + input hold_ff_q; + input [8:0]sig_adjusted_addr_incr; + input sig_clr_dbc_reg_reg; + input sig_csm_pop_child_cmd; + input sig_child_qual_first_of_2; + input sig_child_qual_error_reg; + input lsig_packer_full; + input ram_full_i_reg; + input [3:0]\gpr1.dout_i_reg[3] ; + input [3:0]\gpr1.dout_i_reg[7] ; + input [2:0]sig_child_addr_cntr_lsh_reg; + input [10:0]p_0_out; + + wire [0:0]CO; + wire [2:0]D; + wire [0:0]E; + wire [3:0]O; + wire [3:0]S; + wire [2:0]\gpr1.dout_i_reg[1] ; + wire [2:0]\gpr1.dout_i_reg[1]_0 ; + wire [3:0]\gpr1.dout_i_reg[3] ; + wire [3:0]\gpr1.dout_i_reg[7] ; + wire hold_ff_q; + wire hold_ff_q_reg; + wire lsig_packer_full; + wire m_axi_s2mm_aclk; + wire [10:0]p_0_out; + wire p_32_out; + wire ram_full_i_reg; + wire [8:0]sig_adjusted_addr_incr; + wire [2:0]sig_child_addr_cntr_lsh_reg; + wire [0:0]\sig_child_addr_cntr_lsh_reg[11] ; + wire [3:0]\sig_child_addr_cntr_lsh_reg[7] ; + wire sig_child_qual_error_reg; + wire sig_child_qual_first_of_2; + wire sig_clr_dbc_reg_reg; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_csm_pop_child_cmd; + wire sig_csm_state_ns1; + wire sig_ibtt2dre_tready; + wire sig_sf2pcc_xfer_valid; + wire sig_stream_rst; + wire sig_xfer_cmd_cmplt_reg0; + wire [9:0]sig_xfer_is_seq_reg_reg; + wire sig_xfer_is_seq_reg_reg_0; + wire [3:0]\sig_xfer_len_reg_reg[4] ; + wire [0:0]\sig_xfer_len_reg_reg[5] ; + + Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized2 \gconvfifo.rf + (.CO(CO), + .D(D), + .E(E), + .O(O), + .S(S), + .\gpr1.dout_i_reg[1] (\gpr1.dout_i_reg[1] ), + .\gpr1.dout_i_reg[1]_0 (\gpr1.dout_i_reg[1]_0 ), + .\gpr1.dout_i_reg[3] (\gpr1.dout_i_reg[3] ), + .\gpr1.dout_i_reg[7] (\gpr1.dout_i_reg[7] ), + .hold_ff_q(hold_ff_q), + .hold_ff_q_reg(hold_ff_q_reg), + .lsig_packer_full(lsig_packer_full), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .p_0_out(p_0_out), + .p_32_out(p_32_out), + .ram_full_i_reg(ram_full_i_reg), + .sig_adjusted_addr_incr(sig_adjusted_addr_incr), + .sig_child_addr_cntr_lsh_reg(sig_child_addr_cntr_lsh_reg), + .\sig_child_addr_cntr_lsh_reg[11] (\sig_child_addr_cntr_lsh_reg[11] ), + .\sig_child_addr_cntr_lsh_reg[7] (\sig_child_addr_cntr_lsh_reg[7] ), + .sig_child_qual_error_reg(sig_child_qual_error_reg), + .sig_child_qual_first_of_2(sig_child_qual_first_of_2), + .sig_clr_dbc_reg_reg(sig_clr_dbc_reg_reg), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_csm_pop_child_cmd(sig_csm_pop_child_cmd), + .sig_csm_state_ns1(sig_csm_state_ns1), + .sig_ibtt2dre_tready(sig_ibtt2dre_tready), + .sig_sf2pcc_xfer_valid(sig_sf2pcc_xfer_valid), + .sig_stream_rst(sig_stream_rst), + .sig_xfer_cmd_cmplt_reg0(sig_xfer_cmd_cmplt_reg0), + .sig_xfer_is_seq_reg_reg(sig_xfer_is_seq_reg_reg), + .sig_xfer_is_seq_reg_reg_0(sig_xfer_is_seq_reg_reg_0), + .\sig_xfer_len_reg_reg[4] (\sig_xfer_len_reg_reg[4] ), + .\sig_xfer_len_reg_reg[5] (\sig_xfer_len_reg_reg[5] )); +endmodule + +(* ORIG_REF_NAME = "fifo_generator_v13_1_3_synth" *) +module Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized3 + (sig_data_fifo_data_out, + out, + \gcc0.gc0.count_d1_reg[7] , + hold_ff_q_reg, + \INCLUDE_PACKING.lsig_packer_full_reg , + E, + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] , + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] , + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] , + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] , + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] , + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] , + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] , + sig_data_fifo_dvalid, + m_axi_s2mm_aclk, + sig_stream_rst, + lsig_combined_data, + DIBDI, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + hold_ff_q_reg_0, + sig_s_ready_out_reg, + lsig_set_packer_full__1, + lsig_packer_full, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ); + output [65:0]sig_data_fifo_data_out; + output out; + output \gcc0.gc0.count_d1_reg[7] ; + output hold_ff_q_reg; + output \INCLUDE_PACKING.lsig_packer_full_reg ; + output [0:0]E; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] ; + output sig_data_fifo_dvalid; + input m_axi_s2mm_aclk; + input sig_stream_rst; + input [63:0]lsig_combined_data; + input [1:0]DIBDI; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input hold_ff_q_reg_0; + input sig_s_ready_out_reg; + input lsig_set_packer_full__1; + input lsig_packer_full; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ; + + wire [1:0]DIBDI; + wire [0:0]E; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ; + wire \INCLUDE_PACKING.lsig_packer_full_reg ; + wire \gcc0.gc0.count_d1_reg[7] ; + wire hold_ff_q_reg; + wire hold_ff_q_reg_0; + wire [63:0]lsig_combined_data; + wire lsig_packer_full; + wire lsig_set_packer_full__1; + wire m_axi_s2mm_aclk; + wire out; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire [65:0]sig_data_fifo_data_out; + wire sig_data_fifo_dvalid; + wire sig_s_ready_out_reg; + wire sig_stream_rst; + + Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized3 \gconvfifo.rf + (.DIBDI(DIBDI), + .E(E), + .\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] (\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] (\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] (\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] (\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] (\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] (\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] (\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ), + .\INCLUDE_PACKING.lsig_packer_full_reg (\INCLUDE_PACKING.lsig_packer_full_reg ), + .\gcc0.gc0.count_d1_reg[7] (\gcc0.gc0.count_d1_reg[7] ), + .hold_ff_q_reg(hold_ff_q_reg), + .hold_ff_q_reg_0(hold_ff_q_reg_0), + .lsig_combined_data(lsig_combined_data), + .lsig_packer_full(lsig_packer_full), + .lsig_set_packer_full__1(lsig_set_packer_full__1), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_data_fifo_data_out(sig_data_fifo_data_out), + .sig_data_fifo_dvalid(sig_data_fifo_dvalid), + .sig_s_ready_out_reg(sig_s_ready_out_reg), + .sig_stream_rst(sig_stream_rst)); +endmodule + (* ORIG_REF_NAME = "memory" *) module Arty_Z7_20_axi_vdma_0_0_memory (DOBDO, - \sig_user_skid_reg_reg[0] , + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg , + \INFERRED_GEN.cnt_i_reg[2] , + DIN, dm2linebuf_mm2s_tdata, - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , - \INFERRED_GEN.cnt_i_reg[0] , m_axi_mm2s_aclk, - ram_empty_fb_i_reg, - ram_full_i_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0, + E, \gpregsm1.curr_fwft_state_reg[0] , - sig_stream_rst, - \gc1.count_d2_reg[6] , - Q, + SR, + \gc1.count_d2_reg[7] , + \gcc0.gc0.count_d1_reg[7] , m_axi_mm2s_rdata, DIBDI, - lsig_0ffset_cntr, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , + Q, lsig_cmd_loaded, - \gpregsm1.user_valid_reg , + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 , hold_ff_q, - p_0_out, - dm2linebuf_mm2s_tvalid, - p_8_out, - fifo_wren__0, - \INFERRED_GEN.cnt_i_reg[2] ); + out); output [0:0]DOBDO; - output [0:0]\sig_user_skid_reg_reg[0] ; + output \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + output \INFERRED_GEN.cnt_i_reg[2] ; + output [0:0]DIN; output [31:0]dm2linebuf_mm2s_tdata; - output \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; - output \INFERRED_GEN.cnt_i_reg[0] ; input m_axi_mm2s_aclk; - input ram_empty_fb_i_reg; - input ram_full_i_reg; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0; + input [0:0]E; input \gpregsm1.curr_fwft_state_reg[0] ; - input sig_stream_rst; - input [6:0]\gc1.count_d2_reg[6] ; - input [6:0]Q; + input [0:0]SR; + input [7:0]\gc1.count_d2_reg[7] ; + input [7:0]\gcc0.gc0.count_d1_reg[7] ; input [63:0]m_axi_mm2s_rdata; input [1:0]DIBDI; - input lsig_0ffset_cntr; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + input [0:0]Q; input lsig_cmd_loaded; - input \gpregsm1.user_valid_reg ; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; input hold_ff_q; - input [0:0]p_0_out; - input dm2linebuf_mm2s_tvalid; - input p_8_out; - input fifo_wren__0; - input [0:0]\INFERRED_GEN.cnt_i_reg[2] ; + input out; wire [1:0]DIBDI; + wire [0:0]DIN; wire [0:0]DOBDO; + wire [0:0]E; wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; - wire \INFERRED_GEN.cnt_i_reg[0] ; - wire [0:0]\INFERRED_GEN.cnt_i_reg[2] ; - wire [6:0]Q; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ; + wire \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + wire \INFERRED_GEN.cnt_i_reg[2] ; + wire [0:0]Q; + wire [0:0]SR; wire [31:0]dm2linebuf_mm2s_tdata; - wire dm2linebuf_mm2s_tvalid; - wire fifo_wren__0; - wire [6:0]\gc1.count_d2_reg[6] ; + wire [7:0]\gc1.count_d2_reg[7] ; + wire [7:0]\gcc0.gc0.count_d1_reg[7] ; wire \gpregsm1.curr_fwft_state_reg[0] ; - wire \gpregsm1.user_valid_reg ; wire hold_ff_q; - wire lsig_0ffset_cntr; wire lsig_cmd_loaded; wire m_axi_mm2s_aclk; wire [63:0]m_axi_mm2s_rdata; - wire [0:0]p_0_out; - wire p_8_out; - wire ram_empty_fb_i_reg; - wire ram_full_i_reg; - wire sig_stream_rst; - wire [0:0]\sig_user_skid_reg_reg[0] ; + wire out; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0; Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5 \gbm.gbmg.gbmgb.ngecc.bmg (.DIBDI(DIBDI), + .DIN(DIN), .DOBDO(DOBDO), + .E(E), .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), - .\INFERRED_GEN.cnt_i_reg[0] (\INFERRED_GEN.cnt_i_reg[0] ), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0 ), + .\INCLUDE_UNPACKING.lsig_cmd_loaded_reg (\INCLUDE_UNPACKING.lsig_cmd_loaded_reg ), .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ), .Q(Q), + .SR(SR), .dm2linebuf_mm2s_tdata(dm2linebuf_mm2s_tdata), - .dm2linebuf_mm2s_tvalid(dm2linebuf_mm2s_tvalid), - .fifo_wren__0(fifo_wren__0), - .\gc1.count_d2_reg[6] (\gc1.count_d2_reg[6] ), + .\gc1.count_d2_reg[7] (\gc1.count_d2_reg[7] ), + .\gcc0.gc0.count_d1_reg[7] (\gcc0.gc0.count_d1_reg[7] ), .\gpregsm1.curr_fwft_state_reg[0] (\gpregsm1.curr_fwft_state_reg[0] ), - .\gpregsm1.user_valid_reg (\gpregsm1.user_valid_reg ), .hold_ff_q(hold_ff_q), - .lsig_0ffset_cntr(lsig_0ffset_cntr), .lsig_cmd_loaded(lsig_cmd_loaded), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), .m_axi_mm2s_rdata(m_axi_mm2s_rdata), + .out(out), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0(sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0)); +endmodule + +(* ORIG_REF_NAME = "memory" *) +module Arty_Z7_20_axi_vdma_0_0_memory__parameterized0 + (D, + sig_xfer_is_seq_reg_reg, + \sig_child_addr_cntr_lsh_reg[11] , + S, + \sig_xfer_len_reg_reg[4] , + \sig_xfer_len_reg_reg[5] , + sig_xfer_is_seq_reg_reg_0, + sig_xfer_cmd_cmplt_reg0, + sig_csm_state_ns1, + O, + CO, + \sig_child_addr_cntr_lsh_reg[7] , + sig_adjusted_addr_incr, + sig_csm_pop_child_cmd, + sig_child_qual_first_of_2, + sig_child_qual_error_reg, + \gpr1.dout_i_reg[3] , + \gpr1.dout_i_reg[7] , + sig_child_addr_cntr_lsh_reg, + sig_stream_rst, + E, + p_0_out, + m_axi_s2mm_aclk); + output [2:0]D; + output [9:0]sig_xfer_is_seq_reg_reg; + output [0:0]\sig_child_addr_cntr_lsh_reg[11] ; + output [3:0]S; + output [3:0]\sig_xfer_len_reg_reg[4] ; + output [0:0]\sig_xfer_len_reg_reg[5] ; + output sig_xfer_is_seq_reg_reg_0; + output sig_xfer_cmd_cmplt_reg0; + output sig_csm_state_ns1; + output [3:0]O; + output [0:0]CO; + output [3:0]\sig_child_addr_cntr_lsh_reg[7] ; + input [8:0]sig_adjusted_addr_incr; + input sig_csm_pop_child_cmd; + input sig_child_qual_first_of_2; + input sig_child_qual_error_reg; + input [3:0]\gpr1.dout_i_reg[3] ; + input [3:0]\gpr1.dout_i_reg[7] ; + input [2:0]sig_child_addr_cntr_lsh_reg; + input sig_stream_rst; + input [0:0]E; + input [10:0]p_0_out; + input m_axi_s2mm_aclk; + + wire [0:0]CO; + wire [2:0]D; + wire [0:0]E; + wire [3:0]O; + wire [3:0]S; + wire [3:0]\gpr1.dout_i_reg[3] ; + wire [3:0]\gpr1.dout_i_reg[7] ; + wire m_axi_s2mm_aclk; + wire [10:0]p_0_out; + wire [8:0]sig_adjusted_addr_incr; + wire [2:0]sig_child_addr_cntr_lsh_reg; + wire [0:0]\sig_child_addr_cntr_lsh_reg[11] ; + wire [3:0]\sig_child_addr_cntr_lsh_reg[7] ; + wire sig_child_qual_error_reg; + wire sig_child_qual_first_of_2; + wire sig_csm_pop_child_cmd; + wire sig_csm_state_ns1; + wire sig_stream_rst; + wire sig_xfer_cmd_cmplt_reg0; + wire [9:0]sig_xfer_is_seq_reg_reg; + wire sig_xfer_is_seq_reg_reg_0; + wire [3:0]\sig_xfer_len_reg_reg[4] ; + wire [0:0]\sig_xfer_len_reg_reg[5] ; + + Arty_Z7_20_axi_vdma_0_0_dmem \gdm.dm_gen.dm + (.CO(CO), + .D(D), + .E(E), + .O(O), + .S(S), + .\gpr1.dout_i_reg[3]_0 (\gpr1.dout_i_reg[3] ), + .\gpr1.dout_i_reg[7]_0 (\gpr1.dout_i_reg[7] ), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), .p_0_out(p_0_out), - .p_8_out(p_8_out), - .ram_empty_fb_i_reg(ram_empty_fb_i_reg), - .ram_full_i_reg(ram_full_i_reg), + .sig_adjusted_addr_incr(sig_adjusted_addr_incr), + .sig_child_addr_cntr_lsh_reg(sig_child_addr_cntr_lsh_reg), + .\sig_child_addr_cntr_lsh_reg[11] (\sig_child_addr_cntr_lsh_reg[11] ), + .\sig_child_addr_cntr_lsh_reg[7] (\sig_child_addr_cntr_lsh_reg[7] ), + .sig_child_qual_error_reg(sig_child_qual_error_reg), + .sig_child_qual_first_of_2(sig_child_qual_first_of_2), + .sig_csm_pop_child_cmd(sig_csm_pop_child_cmd), + .sig_csm_state_ns1(sig_csm_state_ns1), .sig_stream_rst(sig_stream_rst), - .\sig_user_skid_reg_reg[0] (\sig_user_skid_reg_reg[0] )); + .sig_xfer_cmd_cmplt_reg0(sig_xfer_cmd_cmplt_reg0), + .sig_xfer_is_seq_reg_reg(sig_xfer_is_seq_reg_reg), + .sig_xfer_is_seq_reg_reg_0(sig_xfer_is_seq_reg_reg_0), + .\sig_xfer_len_reg_reg[4] (\sig_xfer_len_reg_reg[4] ), + .\sig_xfer_len_reg_reg[5] (\sig_xfer_len_reg_reg[5] )); +endmodule + +(* ORIG_REF_NAME = "memory" *) +module Arty_Z7_20_axi_vdma_0_0_memory__parameterized1 + (sig_data_fifo_data_out, + m_axi_s2mm_aclk, + ram_empty_fb_i_reg, + WEBWE, + sig_s_ready_out_reg, + sig_stream_rst, + \gc1.count_d2_reg[7] , + Q, + lsig_combined_data, + DIBDI); + output [65:0]sig_data_fifo_data_out; + input m_axi_s2mm_aclk; + input ram_empty_fb_i_reg; + input [0:0]WEBWE; + input sig_s_ready_out_reg; + input sig_stream_rst; + input [7:0]\gc1.count_d2_reg[7] ; + input [7:0]Q; + input [63:0]lsig_combined_data; + input [1:0]DIBDI; + + wire [1:0]DIBDI; + wire [7:0]Q; + wire [0:0]WEBWE; + wire [7:0]\gc1.count_d2_reg[7] ; + wire [63:0]lsig_combined_data; + wire m_axi_s2mm_aclk; + wire ram_empty_fb_i_reg; + wire [65:0]sig_data_fifo_data_out; + wire sig_s_ready_out_reg; + wire sig_stream_rst; + + Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5__parameterized1 \gbm.gbmg.gbmgb.ngecc.bmg + (.DIBDI(DIBDI), + .Q(Q), + .WEBWE(WEBWE), + .\gc1.count_d2_reg[7] (\gc1.count_d2_reg[7] ), + .lsig_combined_data(lsig_combined_data), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .sig_data_fifo_data_out(sig_data_fifo_data_out), + .sig_s_ready_out_reg(sig_s_ready_out_reg), + .sig_stream_rst(sig_stream_rst)); endmodule (* ORIG_REF_NAME = "rd_bin_cntr" *) module Arty_Z7_20_axi_vdma_0_0_rd_bin_cntr - (\gc1.count_d2_reg[6]_0 , + (Q, \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram , sig_stream_rst, E, - m_axi_mm2s_aclk); - output [6:0]\gc1.count_d2_reg[6]_0 ; - output [6:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; + m_axi_s2mm_aclk); + output [7:0]Q; + output [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; input sig_stream_rst; input [0:0]E; - input m_axi_mm2s_aclk; + input m_axi_s2mm_aclk; - wire [6:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; + wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; wire [0:0]E; - wire \gc1.count[6]_i_2_n_0 ; - wire [6:0]\gc1.count_d2_reg[6]_0 ; - wire m_axi_mm2s_aclk; - wire [6:0]plusOp; - wire [6:0]rd_pntr_plus2; + wire [7:0]Q; + wire \gc1.count[7]_i_2__0_n_0 ; + wire m_axi_s2mm_aclk; + wire [7:0]plusOp__1; + wire [7:0]rd_pntr_plus2; wire sig_stream_rst; + (* SOFT_HLUTNM = "soft_lutpair170" *) + LUT1 #( + .INIT(2'h1)) + \gc1.count[0]_i_1__0 + (.I0(rd_pntr_plus2[0]), + .O(plusOp__1[0])); + LUT2 #( + .INIT(4'h6)) + \gc1.count[1]_i_1__0 + (.I0(rd_pntr_plus2[0]), + .I1(rd_pntr_plus2[1]), + .O(plusOp__1[1])); + (* SOFT_HLUTNM = "soft_lutpair170" *) + LUT3 #( + .INIT(8'h78)) + \gc1.count[2]_i_1__0 + (.I0(rd_pntr_plus2[0]), + .I1(rd_pntr_plus2[1]), + .I2(rd_pntr_plus2[2]), + .O(plusOp__1[2])); + (* SOFT_HLUTNM = "soft_lutpair168" *) + LUT4 #( + .INIT(16'h7F80)) + \gc1.count[3]_i_1__0 + (.I0(rd_pntr_plus2[1]), + .I1(rd_pntr_plus2[0]), + .I2(rd_pntr_plus2[2]), + .I3(rd_pntr_plus2[3]), + .O(plusOp__1[3])); + (* SOFT_HLUTNM = "soft_lutpair168" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \gc1.count[4]_i_1__0 + (.I0(rd_pntr_plus2[2]), + .I1(rd_pntr_plus2[0]), + .I2(rd_pntr_plus2[1]), + .I3(rd_pntr_plus2[3]), + .I4(rd_pntr_plus2[4]), + .O(plusOp__1[4])); + LUT6 #( + .INIT(64'h7FFFFFFF80000000)) + \gc1.count[5]_i_1__0 + (.I0(rd_pntr_plus2[3]), + .I1(rd_pntr_plus2[1]), + .I2(rd_pntr_plus2[0]), + .I3(rd_pntr_plus2[2]), + .I4(rd_pntr_plus2[4]), + .I5(rd_pntr_plus2[5]), + .O(plusOp__1[5])); + (* SOFT_HLUTNM = "soft_lutpair169" *) + LUT2 #( + .INIT(4'h6)) + \gc1.count[6]_i_1__0 + (.I0(\gc1.count[7]_i_2__0_n_0 ), + .I1(rd_pntr_plus2[6]), + .O(plusOp__1[6])); + (* SOFT_HLUTNM = "soft_lutpair169" *) + LUT3 #( + .INIT(8'h78)) + \gc1.count[7]_i_1__0 + (.I0(\gc1.count[7]_i_2__0_n_0 ), + .I1(rd_pntr_plus2[6]), + .I2(rd_pntr_plus2[7]), + .O(plusOp__1[7])); + LUT6 #( + .INIT(64'h8000000000000000)) + \gc1.count[7]_i_2__0 + (.I0(rd_pntr_plus2[5]), + .I1(rd_pntr_plus2[3]), + .I2(rd_pntr_plus2[1]), + .I3(rd_pntr_plus2[0]), + .I4(rd_pntr_plus2[2]), + .I5(rd_pntr_plus2[4]), + .O(\gc1.count[7]_i_2__0_n_0 )); + FDSE #( + .INIT(1'b1)) + \gc1.count_d1_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(rd_pntr_plus2[0]), + .Q(Q[0]), + .S(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gc1.count_d1_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(rd_pntr_plus2[1]), + .Q(Q[1]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gc1.count_d1_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(rd_pntr_plus2[2]), + .Q(Q[2]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gc1.count_d1_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(rd_pntr_plus2[3]), + .Q(Q[3]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gc1.count_d1_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(rd_pntr_plus2[4]), + .Q(Q[4]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gc1.count_d1_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(rd_pntr_plus2[5]), + .Q(Q[5]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gc1.count_d1_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(rd_pntr_plus2[6]), + .Q(Q[6]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gc1.count_d1_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(rd_pntr_plus2[7]), + .Q(Q[7]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gc1.count_d2_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(Q[0]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gc1.count_d2_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(Q[1]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gc1.count_d2_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(Q[2]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [2]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gc1.count_d2_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(Q[3]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [3]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gc1.count_d2_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(Q[4]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [4]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gc1.count_d2_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(Q[5]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [5]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gc1.count_d2_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(Q[6]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [6]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gc1.count_d2_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(Q[7]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [7]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gc1.count_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(plusOp__1[0]), + .Q(rd_pntr_plus2[0]), + .R(sig_stream_rst)); + FDSE #( + .INIT(1'b1)) + \gc1.count_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(plusOp__1[1]), + .Q(rd_pntr_plus2[1]), + .S(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gc1.count_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(plusOp__1[2]), + .Q(rd_pntr_plus2[2]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gc1.count_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(plusOp__1[3]), + .Q(rd_pntr_plus2[3]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gc1.count_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(plusOp__1[4]), + .Q(rd_pntr_plus2[4]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gc1.count_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(plusOp__1[5]), + .Q(rd_pntr_plus2[5]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gc1.count_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(plusOp__1[6]), + .Q(rd_pntr_plus2[6]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gc1.count_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(plusOp__1[7]), + .Q(rd_pntr_plus2[7]), + .R(sig_stream_rst)); +endmodule + +(* ORIG_REF_NAME = "rd_bin_cntr" *) +module Arty_Z7_20_axi_vdma_0_0_rd_bin_cntr_36 + (ram_full_i_reg, + ram_empty_fb_i_reg, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram , + ram_full_i_reg_0, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + ram_empty_fb_i_reg_0, + ram_full_fb_i_reg, + out, + ram_full_i_reg_1, + Q, + \gcc0.gc0.count_reg[7] , + SR, + m_axi_mm2s_aclk); + output ram_full_i_reg; + output ram_empty_fb_i_reg; + output [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; + input ram_full_i_reg_0; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input ram_empty_fb_i_reg_0; + input ram_full_fb_i_reg; + input out; + input [0:0]ram_full_i_reg_1; + input [7:0]Q; + input [7:0]\gcc0.gc0.count_reg[7] ; + input [0:0]SR; + input m_axi_mm2s_aclk; + + wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; + wire [7:0]Q; + wire [0:0]SR; + wire \gc1.count[7]_i_2_n_0 ; + wire [7:0]\gcc0.gc0.count_reg[7] ; + wire m_axi_mm2s_aclk; + wire out; + wire [7:0]plusOp; + wire ram_empty_fb_i_i_2_n_0; + wire ram_empty_fb_i_i_3_n_0; + wire ram_empty_fb_i_i_4_n_0; + wire ram_empty_fb_i_i_5_n_0; + wire ram_empty_fb_i_i_6_n_0; + wire ram_empty_fb_i_i_7_n_0; + wire ram_empty_fb_i_i_8_n_0; + wire ram_empty_fb_i_i_9_n_0; + wire ram_empty_fb_i_reg; + wire ram_empty_fb_i_reg_0; + wire ram_full_fb_i_i_3_n_0; + wire ram_full_fb_i_i_5_n_0; + wire ram_full_fb_i_i_6_n_0; + wire ram_full_fb_i_i_7_n_0; + wire ram_full_fb_i_reg; + wire ram_full_i_reg; + wire ram_full_i_reg_0; + wire [0:0]ram_full_i_reg_1; + wire [7:0]rd_pntr_plus1; + wire [7:0]rd_pntr_plus2; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + + (* SOFT_HLUTNM = "soft_lutpair103" *) LUT1 #( .INIT(2'h1)) \gc1.count[0]_i_1 @@ -31914,351 +79581,584 @@ module Arty_Z7_20_axi_vdma_0_0_rd_bin_cntr (.I0(rd_pntr_plus2[0]), .I1(rd_pntr_plus2[1]), .O(plusOp[1])); - (* SOFT_HLUTNM = "soft_lutpair47" *) + (* SOFT_HLUTNM = "soft_lutpair103" *) LUT3 #( - .INIT(8'h78)) + .INIT(8'h6A)) \gc1.count[2]_i_1 - (.I0(rd_pntr_plus2[0]), + (.I0(rd_pntr_plus2[2]), .I1(rd_pntr_plus2[1]), - .I2(rd_pntr_plus2[2]), + .I2(rd_pntr_plus2[0]), .O(plusOp[2])); - (* SOFT_HLUTNM = "soft_lutpair47" *) + (* SOFT_HLUTNM = "soft_lutpair102" *) LUT4 #( - .INIT(16'h7F80)) + .INIT(16'h6AAA)) \gc1.count[3]_i_1 - (.I0(rd_pntr_plus2[1]), + (.I0(rd_pntr_plus2[3]), .I1(rd_pntr_plus2[0]), - .I2(rd_pntr_plus2[2]), - .I3(rd_pntr_plus2[3]), + .I2(rd_pntr_plus2[1]), + .I3(rd_pntr_plus2[2]), .O(plusOp[3])); - (* SOFT_HLUTNM = "soft_lutpair46" *) + (* SOFT_HLUTNM = "soft_lutpair102" *) LUT5 #( - .INIT(32'h7FFF8000)) + .INIT(32'h6AAAAAAA)) \gc1.count[4]_i_1 - (.I0(rd_pntr_plus2[2]), - .I1(rd_pntr_plus2[0]), + (.I0(rd_pntr_plus2[4]), + .I1(rd_pntr_plus2[2]), .I2(rd_pntr_plus2[1]), - .I3(rd_pntr_plus2[3]), - .I4(rd_pntr_plus2[4]), + .I3(rd_pntr_plus2[0]), + .I4(rd_pntr_plus2[3]), .O(plusOp[4])); LUT6 #( - .INIT(64'h7FFFFFFF80000000)) + .INIT(64'h6AAAAAAAAAAAAAAA)) \gc1.count[5]_i_1 - (.I0(rd_pntr_plus2[3]), - .I1(rd_pntr_plus2[1]), + (.I0(rd_pntr_plus2[5]), + .I1(rd_pntr_plus2[3]), .I2(rd_pntr_plus2[0]), - .I3(rd_pntr_plus2[2]), - .I4(rd_pntr_plus2[4]), - .I5(rd_pntr_plus2[5]), + .I3(rd_pntr_plus2[1]), + .I4(rd_pntr_plus2[2]), + .I5(rd_pntr_plus2[4]), .O(plusOp[5])); - LUT3 #( - .INIT(8'h78)) + (* SOFT_HLUTNM = "soft_lutpair104" *) + LUT2 #( + .INIT(4'h6)) \gc1.count[6]_i_1 - (.I0(\gc1.count[6]_i_2_n_0 ), - .I1(rd_pntr_plus2[5]), - .I2(rd_pntr_plus2[6]), + (.I0(rd_pntr_plus2[6]), + .I1(\gc1.count[7]_i_2_n_0 ), .O(plusOp[6])); - (* SOFT_HLUTNM = "soft_lutpair46" *) - LUT5 #( - .INIT(32'h80000000)) - \gc1.count[6]_i_2 - (.I0(rd_pntr_plus2[4]), - .I1(rd_pntr_plus2[2]), + (* SOFT_HLUTNM = "soft_lutpair104" *) + LUT3 #( + .INIT(8'h6A)) + \gc1.count[7]_i_1 + (.I0(rd_pntr_plus2[7]), + .I1(\gc1.count[7]_i_2_n_0 ), + .I2(rd_pntr_plus2[6]), + .O(plusOp[7])); + LUT6 #( + .INIT(64'h8000000000000000)) + \gc1.count[7]_i_2 + (.I0(rd_pntr_plus2[5]), + .I1(rd_pntr_plus2[3]), .I2(rd_pntr_plus2[0]), .I3(rd_pntr_plus2[1]), - .I4(rd_pntr_plus2[3]), - .O(\gc1.count[6]_i_2_n_0 )); + .I4(rd_pntr_plus2[2]), + .I5(rd_pntr_plus2[4]), + .O(\gc1.count[7]_i_2_n_0 )); FDSE #( .INIT(1'b1)) \gc1.count_d1_reg[0] (.C(m_axi_mm2s_aclk), - .CE(E), + .CE(ram_empty_fb_i_reg_0), .D(rd_pntr_plus2[0]), - .Q(\gc1.count_d2_reg[6]_0 [0]), - .S(sig_stream_rst)); + .Q(rd_pntr_plus1[0]), + .S(SR)); FDRE #( .INIT(1'b0)) \gc1.count_d1_reg[1] (.C(m_axi_mm2s_aclk), - .CE(E), + .CE(ram_empty_fb_i_reg_0), .D(rd_pntr_plus2[1]), - .Q(\gc1.count_d2_reg[6]_0 [1]), - .R(sig_stream_rst)); + .Q(rd_pntr_plus1[1]), + .R(SR)); FDRE #( .INIT(1'b0)) \gc1.count_d1_reg[2] (.C(m_axi_mm2s_aclk), - .CE(E), + .CE(ram_empty_fb_i_reg_0), .D(rd_pntr_plus2[2]), - .Q(\gc1.count_d2_reg[6]_0 [2]), - .R(sig_stream_rst)); + .Q(rd_pntr_plus1[2]), + .R(SR)); FDRE #( .INIT(1'b0)) \gc1.count_d1_reg[3] (.C(m_axi_mm2s_aclk), - .CE(E), + .CE(ram_empty_fb_i_reg_0), .D(rd_pntr_plus2[3]), - .Q(\gc1.count_d2_reg[6]_0 [3]), - .R(sig_stream_rst)); + .Q(rd_pntr_plus1[3]), + .R(SR)); FDRE #( .INIT(1'b0)) \gc1.count_d1_reg[4] (.C(m_axi_mm2s_aclk), - .CE(E), + .CE(ram_empty_fb_i_reg_0), .D(rd_pntr_plus2[4]), - .Q(\gc1.count_d2_reg[6]_0 [4]), - .R(sig_stream_rst)); + .Q(rd_pntr_plus1[4]), + .R(SR)); FDRE #( .INIT(1'b0)) \gc1.count_d1_reg[5] (.C(m_axi_mm2s_aclk), - .CE(E), + .CE(ram_empty_fb_i_reg_0), .D(rd_pntr_plus2[5]), - .Q(\gc1.count_d2_reg[6]_0 [5]), - .R(sig_stream_rst)); + .Q(rd_pntr_plus1[5]), + .R(SR)); FDRE #( .INIT(1'b0)) \gc1.count_d1_reg[6] (.C(m_axi_mm2s_aclk), - .CE(E), + .CE(ram_empty_fb_i_reg_0), .D(rd_pntr_plus2[6]), - .Q(\gc1.count_d2_reg[6]_0 [6]), - .R(sig_stream_rst)); + .Q(rd_pntr_plus1[6]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \gc1.count_d1_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(ram_empty_fb_i_reg_0), + .D(rd_pntr_plus2[7]), + .Q(rd_pntr_plus1[7]), + .R(SR)); FDRE #( .INIT(1'b0)) \gc1.count_d2_reg[0] (.C(m_axi_mm2s_aclk), - .CE(E), - .D(\gc1.count_d2_reg[6]_0 [0]), + .CE(ram_empty_fb_i_reg_0), + .D(rd_pntr_plus1[0]), .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]), - .R(sig_stream_rst)); + .R(SR)); FDRE #( .INIT(1'b0)) \gc1.count_d2_reg[1] (.C(m_axi_mm2s_aclk), - .CE(E), - .D(\gc1.count_d2_reg[6]_0 [1]), + .CE(ram_empty_fb_i_reg_0), + .D(rd_pntr_plus1[1]), .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]), - .R(sig_stream_rst)); + .R(SR)); FDRE #( .INIT(1'b0)) \gc1.count_d2_reg[2] (.C(m_axi_mm2s_aclk), - .CE(E), - .D(\gc1.count_d2_reg[6]_0 [2]), + .CE(ram_empty_fb_i_reg_0), + .D(rd_pntr_plus1[2]), .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [2]), - .R(sig_stream_rst)); + .R(SR)); FDRE #( .INIT(1'b0)) \gc1.count_d2_reg[3] (.C(m_axi_mm2s_aclk), - .CE(E), - .D(\gc1.count_d2_reg[6]_0 [3]), + .CE(ram_empty_fb_i_reg_0), + .D(rd_pntr_plus1[3]), .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [3]), - .R(sig_stream_rst)); + .R(SR)); FDRE #( .INIT(1'b0)) \gc1.count_d2_reg[4] (.C(m_axi_mm2s_aclk), - .CE(E), - .D(\gc1.count_d2_reg[6]_0 [4]), + .CE(ram_empty_fb_i_reg_0), + .D(rd_pntr_plus1[4]), .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [4]), - .R(sig_stream_rst)); + .R(SR)); FDRE #( .INIT(1'b0)) \gc1.count_d2_reg[5] (.C(m_axi_mm2s_aclk), - .CE(E), - .D(\gc1.count_d2_reg[6]_0 [5]), + .CE(ram_empty_fb_i_reg_0), + .D(rd_pntr_plus1[5]), .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [5]), - .R(sig_stream_rst)); + .R(SR)); FDRE #( .INIT(1'b0)) \gc1.count_d2_reg[6] (.C(m_axi_mm2s_aclk), - .CE(E), - .D(\gc1.count_d2_reg[6]_0 [6]), + .CE(ram_empty_fb_i_reg_0), + .D(rd_pntr_plus1[6]), .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [6]), - .R(sig_stream_rst)); + .R(SR)); + FDRE #( + .INIT(1'b0)) + \gc1.count_d2_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(ram_empty_fb_i_reg_0), + .D(rd_pntr_plus1[7]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [7]), + .R(SR)); FDRE #( .INIT(1'b0)) \gc1.count_reg[0] (.C(m_axi_mm2s_aclk), - .CE(E), + .CE(ram_empty_fb_i_reg_0), .D(plusOp[0]), .Q(rd_pntr_plus2[0]), - .R(sig_stream_rst)); + .R(SR)); FDSE #( .INIT(1'b1)) \gc1.count_reg[1] (.C(m_axi_mm2s_aclk), - .CE(E), + .CE(ram_empty_fb_i_reg_0), .D(plusOp[1]), .Q(rd_pntr_plus2[1]), - .S(sig_stream_rst)); + .S(SR)); FDRE #( .INIT(1'b0)) \gc1.count_reg[2] (.C(m_axi_mm2s_aclk), - .CE(E), + .CE(ram_empty_fb_i_reg_0), .D(plusOp[2]), .Q(rd_pntr_plus2[2]), - .R(sig_stream_rst)); + .R(SR)); FDRE #( .INIT(1'b0)) \gc1.count_reg[3] (.C(m_axi_mm2s_aclk), - .CE(E), + .CE(ram_empty_fb_i_reg_0), .D(plusOp[3]), .Q(rd_pntr_plus2[3]), - .R(sig_stream_rst)); + .R(SR)); FDRE #( .INIT(1'b0)) \gc1.count_reg[4] (.C(m_axi_mm2s_aclk), - .CE(E), + .CE(ram_empty_fb_i_reg_0), .D(plusOp[4]), .Q(rd_pntr_plus2[4]), - .R(sig_stream_rst)); + .R(SR)); FDRE #( .INIT(1'b0)) \gc1.count_reg[5] (.C(m_axi_mm2s_aclk), - .CE(E), + .CE(ram_empty_fb_i_reg_0), .D(plusOp[5]), .Q(rd_pntr_plus2[5]), - .R(sig_stream_rst)); + .R(SR)); FDRE #( .INIT(1'b0)) \gc1.count_reg[6] (.C(m_axi_mm2s_aclk), - .CE(E), + .CE(ram_empty_fb_i_reg_0), .D(plusOp[6]), .Q(rd_pntr_plus2[6]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \gc1.count_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(ram_empty_fb_i_reg_0), + .D(plusOp[7]), + .Q(rd_pntr_plus2[7]), + .R(SR)); + LUT6 #( + .INIT(64'h4FCF4FCF4FFF4FCF)) + ram_empty_fb_i_i_1 + (.I0(ram_empty_fb_i_i_2_n_0), + .I1(out), + .I2(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I3(ram_full_i_reg_1), + .I4(ram_empty_fb_i_reg_0), + .I5(ram_empty_fb_i_i_3_n_0), + .O(ram_empty_fb_i_reg)); + LUT6 #( + .INIT(64'h0000000041000041)) + ram_empty_fb_i_i_2 + (.I0(ram_empty_fb_i_i_4_n_0), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [2]), + .I2(Q[2]), + .I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [3]), + .I4(Q[3]), + .I5(ram_empty_fb_i_i_5_n_0), + .O(ram_empty_fb_i_i_2_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFFBEFFFFBE)) + ram_empty_fb_i_i_3 + (.I0(ram_empty_fb_i_i_6_n_0), + .I1(rd_pntr_plus1[3]), + .I2(Q[3]), + .I3(rd_pntr_plus1[2]), + .I4(Q[2]), + .I5(ram_empty_fb_i_i_7_n_0), + .O(ram_empty_fb_i_i_3_n_0)); + LUT4 #( + .INIT(16'h6FF6)) + ram_empty_fb_i_i_4 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]), + .I1(Q[0]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]), + .I3(Q[1]), + .O(ram_empty_fb_i_i_4_n_0)); + LUT5 #( + .INIT(32'hFFFF6FF6)) + ram_empty_fb_i_i_5 + (.I0(Q[6]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [6]), + .I2(Q[7]), + .I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [7]), + .I4(ram_empty_fb_i_i_8_n_0), + .O(ram_empty_fb_i_i_5_n_0)); + LUT4 #( + .INIT(16'h6FF6)) + ram_empty_fb_i_i_6 + (.I0(rd_pntr_plus1[1]), + .I1(Q[1]), + .I2(rd_pntr_plus1[0]), + .I3(Q[0]), + .O(ram_empty_fb_i_i_6_n_0)); + LUT5 #( + .INIT(32'hFFFF6FF6)) + ram_empty_fb_i_i_7 + (.I0(Q[5]), + .I1(rd_pntr_plus1[5]), + .I2(Q[4]), + .I3(rd_pntr_plus1[4]), + .I4(ram_empty_fb_i_i_9_n_0), + .O(ram_empty_fb_i_i_7_n_0)); + LUT4 #( + .INIT(16'h6FF6)) + ram_empty_fb_i_i_8 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [5]), + .I1(Q[5]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [4]), + .I3(Q[4]), + .O(ram_empty_fb_i_i_8_n_0)); + LUT4 #( + .INIT(16'h6FF6)) + ram_empty_fb_i_i_9 + (.I0(rd_pntr_plus1[6]), + .I1(Q[6]), + .I2(rd_pntr_plus1[7]), + .I3(Q[7]), + .O(ram_empty_fb_i_i_9_n_0)); + LUT6 #( + .INIT(64'h00F0F0F000200020)) + ram_full_fb_i_i_1 + (.I0(ram_full_i_reg_0), + .I1(ram_full_fb_i_i_3_n_0), + .I2(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I3(ram_empty_fb_i_reg_0), + .I4(ram_empty_fb_i_i_2_n_0), + .I5(ram_full_fb_i_reg), + .O(ram_full_i_reg)); + LUT6 #( + .INIT(64'hFFFFFFFFBEFFFFBE)) + ram_full_fb_i_i_3 + (.I0(ram_full_fb_i_i_5_n_0), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]), + .I2(\gcc0.gc0.count_reg[7] [1]), + .I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]), + .I4(\gcc0.gc0.count_reg[7] [0]), + .I5(ram_full_fb_i_i_6_n_0), + .O(ram_full_fb_i_i_3_n_0)); + LUT4 #( + .INIT(16'h6FF6)) + ram_full_fb_i_i_5 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [2]), + .I1(\gcc0.gc0.count_reg[7] [2]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [3]), + .I3(\gcc0.gc0.count_reg[7] [3]), + .O(ram_full_fb_i_i_5_n_0)); + LUT5 #( + .INIT(32'hFFFF6FF6)) + ram_full_fb_i_i_6 + (.I0(\gcc0.gc0.count_reg[7] [5]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [5]), + .I2(\gcc0.gc0.count_reg[7] [4]), + .I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [4]), + .I4(ram_full_fb_i_i_7_n_0), + .O(ram_full_fb_i_i_6_n_0)); + LUT4 #( + .INIT(16'h6FF6)) + ram_full_fb_i_i_7 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [7]), + .I1(\gcc0.gc0.count_reg[7] [7]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [6]), + .I3(\gcc0.gc0.count_reg[7] [6]), + .O(ram_full_fb_i_i_7_n_0)); +endmodule + +(* ORIG_REF_NAME = "rd_bin_cntr" *) +module Arty_Z7_20_axi_vdma_0_0_rd_bin_cntr__parameterized0 + (Q, + \gpr1.dout_i_reg[1] , + sig_stream_rst, + E, + m_axi_s2mm_aclk); + output [2:0]Q; + output [2:0]\gpr1.dout_i_reg[1] ; + input sig_stream_rst; + input [0:0]E; + input m_axi_s2mm_aclk; + + wire [0:0]E; + wire [2:0]Q; + wire [2:0]\gpr1.dout_i_reg[1] ; + wire m_axi_s2mm_aclk; + wire [2:0]plusOp; + wire [2:0]rd_pntr_plus2; + wire sig_stream_rst; + + (* SOFT_HLUTNM = "soft_lutpair176" *) + LUT1 #( + .INIT(2'h1)) + \gc1.count[0]_i_1 + (.I0(rd_pntr_plus2[0]), + .O(plusOp[0])); + LUT2 #( + .INIT(4'h6)) + \gc1.count[1]_i_1 + (.I0(rd_pntr_plus2[0]), + .I1(rd_pntr_plus2[1]), + .O(plusOp[1])); + (* SOFT_HLUTNM = "soft_lutpair176" *) + LUT3 #( + .INIT(8'h78)) + \gc1.count[2]_i_2 + (.I0(rd_pntr_plus2[0]), + .I1(rd_pntr_plus2[1]), + .I2(rd_pntr_plus2[2]), + .O(plusOp[2])); + FDSE #( + .INIT(1'b1)) + \gc1.count_d1_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(rd_pntr_plus2[0]), + .Q(Q[0]), + .S(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gc1.count_d1_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(rd_pntr_plus2[1]), + .Q(Q[1]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gc1.count_d1_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(rd_pntr_plus2[2]), + .Q(Q[2]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gc1.count_d2_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(Q[0]), + .Q(\gpr1.dout_i_reg[1] [0]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gc1.count_d2_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(Q[1]), + .Q(\gpr1.dout_i_reg[1] [1]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gc1.count_d2_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(Q[2]), + .Q(\gpr1.dout_i_reg[1] [2]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gc1.count_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(plusOp[0]), + .Q(rd_pntr_plus2[0]), + .R(sig_stream_rst)); + FDSE #( + .INIT(1'b1)) + \gc1.count_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(plusOp[1]), + .Q(rd_pntr_plus2[1]), + .S(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gc1.count_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(plusOp[2]), + .Q(rd_pntr_plus2[2]), .R(sig_stream_rst)); endmodule (* ORIG_REF_NAME = "rd_fwft" *) module Arty_Z7_20_axi_vdma_0_0_rd_fwft (out, - E, - \gc1.count_reg[0] , - dm2linebuf_mm2s_tvalid, hold_ff_q_reg, - \INCLUDE_UNPACKING.lsig_cmd_loaded_reg , \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram , + E, + sig_data_fifo_dvalid, sig_stream_rst, - m_axi_mm2s_aclk, - ram_full_i_reg, - ram_empty_fb_i_reg, - lsig_cmd_loaded, - hold_ff_q, - lsig_0ffset_cntr, - p_8_out, + m_axi_s2mm_aclk, sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - \INFERRED_GEN.cnt_i_reg[2] , - DOBDO); + hold_ff_q_reg_0, + sig_s_ready_out_reg, + ram_empty_fb_i_reg); output out; - output [0:0]E; - output [0:0]\gc1.count_reg[0] ; - output dm2linebuf_mm2s_tvalid; output hold_ff_q_reg; - output \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; output \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; + output [0:0]E; + output sig_data_fifo_dvalid; input sig_stream_rst; - input m_axi_mm2s_aclk; - input ram_full_i_reg; - input ram_empty_fb_i_reg; - input lsig_cmd_loaded; - input hold_ff_q; - input lsig_0ffset_cntr; - input p_8_out; + input m_axi_s2mm_aclk; input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - input [0:0]\INFERRED_GEN.cnt_i_reg[2] ; - input [0:0]DOBDO; + input hold_ff_q_reg_0; + input sig_s_ready_out_reg; + input ram_empty_fb_i_reg; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; - wire [0:0]DOBDO; wire [0:0]E; - wire \INCLUDE_UNPACKING.lsig_cmd_loaded_i_2_n_0 ; - wire \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; - wire [0:0]\INFERRED_GEN.cnt_i_reg[2] ; (* DONT_TOUCH *) wire aempty_fwft_fb_i; (* DONT_TOUCH *) wire aempty_fwft_i; wire aempty_fwft_i0__6; (* DONT_TOUCH *) wire [1:0]curr_fwft_state; - wire dm2linebuf_mm2s_tvalid; (* DONT_TOUCH *) wire empty_fwft_fb_i; (* DONT_TOUCH *) wire empty_fwft_fb_o_i; wire empty_fwft_fb_o_i_reg0; (* DONT_TOUCH *) wire empty_fwft_i; wire empty_fwft_i0__1; - wire [0:0]\gc1.count_reg[0] ; - wire hold_ff_q; wire hold_ff_q_reg; - wire lsig_0ffset_cntr; - wire lsig_cmd_loaded; - wire m_axi_mm2s_aclk; + wire hold_ff_q_reg_0; + wire m_axi_s2mm_aclk; wire [1:0]next_fwft_state; - wire p_8_out; wire ram_empty_fb_i_reg; - wire ram_full_i_reg; wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - wire sig_pop_data_fifo__3; + wire sig_data_fifo_dvalid; + wire sig_pop_data_fifo__0; + wire sig_s_ready_out_reg; wire sig_stream_rst; (* DONT_TOUCH *) wire user_valid; assign out = user_valid; - LUT4 #( - .INIT(16'hB0FF)) - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_3 - (.I0(sig_pop_data_fifo__3), - .I1(curr_fwft_state[0]), - .I2(curr_fwft_state[1]), - .I3(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram )); - LUT5 #( - .INIT(32'h80808000)) - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_9 - (.I0(lsig_0ffset_cntr), - .I1(p_8_out), - .I2(lsig_cmd_loaded), - .I3(user_valid), - .I4(hold_ff_q), - .O(sig_pop_data_fifo__3)); - LUT3 #( - .INIT(8'h2F)) - \INCLUDE_UNPACKING.lsig_cmd_loaded_i_1 - (.I0(lsig_cmd_loaded), - .I1(\INCLUDE_UNPACKING.lsig_cmd_loaded_i_2_n_0 ), - .I2(\INFERRED_GEN.cnt_i_reg[2] ), - .O(\INCLUDE_UNPACKING.lsig_cmd_loaded_reg )); LUT6 #( - .INIT(64'h8880000000000000)) - \INCLUDE_UNPACKING.lsig_cmd_loaded_i_2 - (.I0(p_8_out), - .I1(lsig_cmd_loaded), + .INIT(64'hA8FF0000FFFFFFFF)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_3 + (.I0(sig_s_ready_out_reg), + .I1(hold_ff_q_reg_0), .I2(user_valid), - .I3(hold_ff_q), - .I4(lsig_0ffset_cntr), - .I5(DOBDO), - .O(\INCLUDE_UNPACKING.lsig_cmd_loaded_i_2_n_0 )); + .I3(curr_fwft_state[0]), + .I4(curr_fwft_state[1]), + .I5(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram )); LUT5 #( .INIT(32'hEEFD8000)) aempty_fwft_fb_i_i_1 (.I0(curr_fwft_state[0]), .I1(ram_empty_fb_i_reg), - .I2(sig_pop_data_fifo__3), + .I2(sig_pop_data_fifo__0), .I3(curr_fwft_state[1]), .I4(aempty_fwft_fb_i), .O(aempty_fwft_i0__6)); + LUT3 #( + .INIT(8'hE0)) + aempty_fwft_fb_i_i_2 + (.I0(user_valid), + .I1(hold_ff_q_reg_0), + .I2(sig_s_ready_out_reg), + .O(sig_pop_data_fifo__0)); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDSE #( .INIT(1'b1)) aempty_fwft_fb_i_reg - (.C(m_axi_mm2s_aclk), + (.C(m_axi_s2mm_aclk), .CE(1'b1), .D(aempty_fwft_i0__6), .Q(aempty_fwft_fb_i), @@ -32269,40 +80169,267 @@ module Arty_Z7_20_axi_vdma_0_0_rd_fwft FDSE #( .INIT(1'b1)) aempty_fwft_i_reg - (.C(m_axi_mm2s_aclk), + (.C(m_axi_s2mm_aclk), .CE(1'b1), .D(aempty_fwft_i0__6), .Q(aempty_fwft_i), .S(sig_stream_rst)); - LUT2 #( - .INIT(4'h6)) - \count[6]_i_1 - (.I0(\gc1.count_reg[0] ), - .I1(ram_full_i_reg), + LUT6 #( + .INIT(64'hFFFF00FF00A80000)) + empty_fwft_fb_i_i_1__0 + (.I0(sig_s_ready_out_reg), + .I1(hold_ff_q_reg_0), + .I2(user_valid), + .I3(curr_fwft_state[1]), + .I4(curr_fwft_state[0]), + .I5(empty_fwft_fb_i), + .O(empty_fwft_i0__1)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDSE #( + .INIT(1'b1)) + empty_fwft_fb_i_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(empty_fwft_i0__1), + .Q(empty_fwft_fb_i), + .S(sig_stream_rst)); + LUT6 #( + .INIT(64'hFFFF00FF00A80000)) + empty_fwft_fb_o_i_i_1__0 + (.I0(sig_s_ready_out_reg), + .I1(hold_ff_q_reg_0), + .I2(user_valid), + .I3(curr_fwft_state[1]), + .I4(curr_fwft_state[0]), + .I5(empty_fwft_fb_o_i), + .O(empty_fwft_fb_o_i_reg0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDSE #( + .INIT(1'b1)) + empty_fwft_fb_o_i_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(empty_fwft_fb_o_i_reg0), + .Q(empty_fwft_fb_o_i), + .S(sig_stream_rst)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDSE #( + .INIT(1'b1)) + empty_fwft_i_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(empty_fwft_i0__1), + .Q(empty_fwft_i), + .S(sig_stream_rst)); + LUT6 #( + .INIT(64'h00000000A8FFFFFF)) + \gc1.count_d1[7]_i_1 + (.I0(sig_s_ready_out_reg), + .I1(hold_ff_q_reg_0), + .I2(user_valid), + .I3(curr_fwft_state[0]), + .I4(curr_fwft_state[1]), + .I5(ram_empty_fb_i_reg), .O(E)); + LUT5 #( + .INIT(32'hABFFAAAA)) + \gpregsm1.curr_fwft_state[0]_i_1 + (.I0(curr_fwft_state[1]), + .I1(user_valid), + .I2(hold_ff_q_reg_0), + .I3(sig_s_ready_out_reg), + .I4(curr_fwft_state[0]), + .O(next_fwft_state[0])); + LUT6 #( + .INIT(64'h222A0000FFFFFFFF)) + \gpregsm1.curr_fwft_state[1]_i_1 + (.I0(curr_fwft_state[1]), + .I1(sig_s_ready_out_reg), + .I2(hold_ff_q_reg_0), + .I3(user_valid), + .I4(curr_fwft_state[0]), + .I5(ram_empty_fb_i_reg), + .O(next_fwft_state[1])); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \gpregsm1.curr_fwft_state_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(next_fwft_state[0]), + .Q(curr_fwft_state[0]), + .R(sig_stream_rst)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \gpregsm1.curr_fwft_state_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(next_fwft_state[1]), + .Q(curr_fwft_state[1]), + .R(sig_stream_rst)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \gpregsm1.user_valid_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(next_fwft_state[0]), + .Q(user_valid), + .R(sig_stream_rst)); + LUT4 #( + .INIT(16'h00A8)) + hold_ff_q_i_1 + (.I0(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I1(user_valid), + .I2(hold_ff_q_reg_0), + .I3(sig_s_ready_out_reg), + .O(hold_ff_q_reg)); + LUT2 #( + .INIT(4'hE)) + sig_m_valid_dup_i_2 + (.I0(hold_ff_q_reg_0), + .I1(user_valid), + .O(sig_data_fifo_dvalid)); +endmodule + +(* ORIG_REF_NAME = "rd_fwft" *) +module Arty_Z7_20_axi_vdma_0_0_rd_fwft_34 + (out, + hold_ff_q_reg, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram , + \gc1.count_reg[7] , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0 , + \sig_user_skid_reg_reg[0] , + m_axi_mm2s_aclk, + SR, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + hold_ff_q, + ram_empty_fb_i_reg, + lsig_cmd_loaded); + output out; + output hold_ff_q_reg; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; + output \gc1.count_reg[7] ; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0 ; + output \sig_user_skid_reg_reg[0] ; + input m_axi_mm2s_aclk; + input [0:0]SR; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input hold_ff_q; + input ram_empty_fb_i_reg; + input lsig_cmd_loaded; + + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0 ; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + wire [0:0]SR; + (* DONT_TOUCH *) wire aempty_fwft_fb_i; + wire aempty_fwft_fb_i_i_1__0_n_0; + (* DONT_TOUCH *) wire aempty_fwft_i; + (* DONT_TOUCH *) wire [1:0]curr_fwft_state; + (* DONT_TOUCH *) wire empty_fwft_fb_i; + wire empty_fwft_fb_i_i_1_n_0; + (* DONT_TOUCH *) wire empty_fwft_fb_o_i; + wire empty_fwft_fb_o_i_reg0; + (* DONT_TOUCH *) wire empty_fwft_i; + wire \gc1.count_reg[7] ; + wire \gpregsm1.curr_fwft_state[1]_i_1__0_n_0 ; + wire hold_ff_q; + wire hold_ff_q_reg; + wire lsig_cmd_loaded; + wire m_axi_mm2s_aclk; + wire [0:0]next_fwft_state; + wire ram_empty_fb_i_reg; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire \sig_user_skid_reg_reg[0] ; + (* DONT_TOUCH *) wire user_valid; + + assign out = user_valid; + LUT2 #( + .INIT(4'hB)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1 + (.I0(\gc1.count_reg[7] ), + .I1(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram )); LUT4 #( - .INIT(16'hF320)) + .INIT(16'h70FF)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_3__0 + (.I0(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), + .I1(curr_fwft_state[0]), + .I2(curr_fwft_state[1]), + .I3(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0 )); + LUT6 #( + .INIT(64'hEB00EF80FFFFFFFF)) + aempty_fwft_fb_i_i_1__0 + (.I0(ram_empty_fb_i_reg), + .I1(curr_fwft_state[0]), + .I2(curr_fwft_state[1]), + .I3(aempty_fwft_fb_i), + .I4(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), + .I5(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .O(aempty_fwft_fb_i_i_1__0_n_0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b1)) + aempty_fwft_fb_i_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(aempty_fwft_fb_i_i_1__0_n_0), + .Q(aempty_fwft_fb_i), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b1)) + aempty_fwft_i_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(aempty_fwft_fb_i_i_1__0_n_0), + .Q(aempty_fwft_i), + .R(1'b0)); + LUT5 #( + .INIT(32'hF333F7F3)) empty_fwft_fb_i_i_1 - (.I0(sig_pop_data_fifo__3), - .I1(curr_fwft_state[1]), - .I2(curr_fwft_state[0]), - .I3(empty_fwft_fb_i), - .O(empty_fwft_i0__1)); + (.I0(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), + .I1(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I2(empty_fwft_fb_i), + .I3(curr_fwft_state[0]), + .I4(curr_fwft_state[1]), + .O(empty_fwft_fb_i_i_1_n_0)); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) - FDSE #( + FDRE #( .INIT(1'b1)) empty_fwft_fb_i_reg (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(empty_fwft_i0__1), + .D(empty_fwft_fb_i_i_1_n_0), .Q(empty_fwft_fb_i), - .S(sig_stream_rst)); + .R(1'b0)); LUT4 #( - .INIT(16'hF320)) + .INIT(16'hF310)) empty_fwft_fb_o_i_i_1 - (.I0(sig_pop_data_fifo__3), + (.I0(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), .I1(curr_fwft_state[1]), .I2(curr_fwft_state[0]), .I3(empty_fwft_fb_o_i), @@ -32317,50 +80444,48 @@ module Arty_Z7_20_axi_vdma_0_0_rd_fwft .CE(1'b1), .D(empty_fwft_fb_o_i_reg0), .Q(empty_fwft_fb_o_i), - .S(sig_stream_rst)); + .S(SR)); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) - FDSE #( + FDRE #( .INIT(1'b1)) empty_fwft_i_reg (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(empty_fwft_i0__1), + .D(empty_fwft_fb_i_i_1_n_0), .Q(empty_fwft_i), - .S(sig_stream_rst)); - LUT6 #( - .INIT(64'h00000000F7777777)) - \gc1.count_d1[6]_i_1 - (.I0(curr_fwft_state[0]), + .R(1'b0)); + LUT4 #( + .INIT(16'h1555)) + \gc1.count_d1[7]_i_1__0 + (.I0(ram_empty_fb_i_reg), .I1(curr_fwft_state[1]), - .I2(dm2linebuf_mm2s_tvalid), - .I3(p_8_out), - .I4(lsig_0ffset_cntr), - .I5(ram_empty_fb_i_reg), - .O(\gc1.count_reg[0] )); + .I2(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), + .I3(curr_fwft_state[0]), + .O(\gc1.count_reg[7] )); LUT3 #( - .INIT(8'hA8)) - \gc1.count_d1[6]_i_2 - (.I0(lsig_cmd_loaded), + .INIT(8'h1F)) + \gf36e1_inst.sngfifo36e1_i_22 + (.I0(hold_ff_q), .I1(user_valid), - .I2(hold_ff_q), - .O(dm2linebuf_mm2s_tvalid)); + .I2(lsig_cmd_loaded), + .O(\sig_user_skid_reg_reg[0] )); LUT3 #( - .INIT(8'hBA)) - \gpregsm1.curr_fwft_state[0]_i_1 - (.I0(curr_fwft_state[1]), - .I1(sig_pop_data_fifo__3), - .I2(curr_fwft_state[0]), - .O(next_fwft_state[0])); + .INIT(8'hF8)) + \gpregsm1.curr_fwft_state[0]_i_1__0 + (.I0(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), + .I1(curr_fwft_state[0]), + .I2(curr_fwft_state[1]), + .O(next_fwft_state)); LUT4 #( - .INIT(16'h20FF)) - \gpregsm1.curr_fwft_state[1]_i_1 - (.I0(curr_fwft_state[1]), - .I1(sig_pop_data_fifo__3), - .I2(curr_fwft_state[0]), + .INIT(16'h80FF)) + \gpregsm1.curr_fwft_state[1]_i_1__0 + (.I0(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), + .I1(curr_fwft_state[0]), + .I2(curr_fwft_state[1]), .I3(ram_empty_fb_i_reg), - .O(next_fwft_state[1])); + .O(\gpregsm1.curr_fwft_state[1]_i_1__0_n_0 )); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) @@ -32369,9 +80494,9 @@ module Arty_Z7_20_axi_vdma_0_0_rd_fwft \gpregsm1.curr_fwft_state_reg[0] (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(next_fwft_state[0]), + .D(next_fwft_state), .Q(curr_fwft_state[0]), - .R(sig_stream_rst)); + .R(SR)); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) @@ -32380,9 +80505,9 @@ module Arty_Z7_20_axi_vdma_0_0_rd_fwft \gpregsm1.curr_fwft_state_reg[1] (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(next_fwft_state[1]), + .D(\gpregsm1.curr_fwft_state[1]_i_1__0_n_0 ), .Q(curr_fwft_state[1]), - .R(sig_stream_rst)); + .R(SR)); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) @@ -32391,165 +80516,387 @@ module Arty_Z7_20_axi_vdma_0_0_rd_fwft \gpregsm1.user_valid_reg (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(next_fwft_state[0]), + .D(next_fwft_state), .Q(user_valid), - .R(sig_stream_rst)); + .R(SR)); LUT4 #( - .INIT(16'h00E0)) - hold_ff_q_i_1 - (.I0(user_valid), + .INIT(16'h8880)) + hold_ff_q_i_1__1 + (.I0(\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), + .I1(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I2(hold_ff_q), + .I3(user_valid), + .O(hold_ff_q_reg)); +endmodule + +(* ORIG_REF_NAME = "rd_handshaking_flags" *) +module Arty_Z7_20_axi_vdma_0_0_rd_handshaking_flags__parameterized0 + (\gv.ram_valid_d1_reg_0 , + hold_ff_q_reg, + sig_sf2pcc_xfer_valid, + sig_stream_rst, + m_axi_s2mm_aclk, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + p_32_out, + hold_ff_q, + out); + output \gv.ram_valid_d1_reg_0 ; + output hold_ff_q_reg; + output sig_sf2pcc_xfer_valid; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input p_32_out; + input hold_ff_q; + input out; + + wire \gv.ram_valid_d1_i_1_n_0 ; + wire \gv.ram_valid_d1_reg_0 ; + wire hold_ff_q; + wire hold_ff_q_reg; + wire m_axi_s2mm_aclk; + wire out; + wire p_32_out; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_sf2pcc_xfer_valid; + wire sig_stream_rst; + + LUT2 #( + .INIT(4'hE)) + \FSM_sequential_sig_csm_state[0]_i_4 + (.I0(hold_ff_q), + .I1(\gv.ram_valid_d1_reg_0 ), + .O(sig_sf2pcc_xfer_valid)); + (* SOFT_HLUTNM = "soft_lutpair174" *) + LUT4 #( + .INIT(16'h00F1)) + \gv.ram_valid_d1_i_1 + (.I0(\gv.ram_valid_d1_reg_0 ), .I1(hold_ff_q), - .I2(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .I3(sig_pop_data_fifo__3), + .I2(p_32_out), + .I3(out), + .O(\gv.ram_valid_d1_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \gv.ram_valid_d1_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\gv.ram_valid_d1_i_1_n_0 ), + .Q(\gv.ram_valid_d1_reg_0 ), + .R(sig_stream_rst)); + (* SOFT_HLUTNM = "soft_lutpair174" *) + LUT4 #( + .INIT(16'h2220)) + hold_ff_q_i_1__0 + (.I0(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I1(p_32_out), + .I2(hold_ff_q), + .I3(\gv.ram_valid_d1_reg_0 ), .O(hold_ff_q_reg)); endmodule (* ORIG_REF_NAME = "rd_logic" *) module Arty_Z7_20_axi_vdma_0_0_rd_logic (out, + \gpregsm1.user_valid_reg , hold_ff_q_reg, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram , + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0 , p_7_out, - dm2linebuf_mm2s_tvalid, - DI, + sig_data_fifo_dvalid, Q, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_1 , + sig_stream_rst, + m_axi_s2mm_aclk, + ram_empty_i0__3, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, hold_ff_q_reg_0, + sig_s_ready_out_reg); + output out; + output \gpregsm1.user_valid_reg ; + output hold_ff_q_reg; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0 ; + output p_7_out; + output sig_data_fifo_dvalid; + output [7:0]Q; + output [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_1 ; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input ram_empty_i0__3; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input hold_ff_q_reg_0; + input sig_s_ready_out_reg; + + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0 ; + wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_1 ; + wire [7:0]Q; + wire \gpregsm1.user_valid_reg ; + wire hold_ff_q_reg; + wire hold_ff_q_reg_0; + wire m_axi_s2mm_aclk; + wire out; + wire p_7_out; + wire ram_empty_i0__3; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_data_fifo_dvalid; + wire sig_s_ready_out_reg; + wire sig_stream_rst; + + Arty_Z7_20_axi_vdma_0_0_rd_fwft \gr1.gr1_int.rfwft + (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ), + .E(p_7_out), + .hold_ff_q_reg(hold_ff_q_reg), + .hold_ff_q_reg_0(hold_ff_q_reg_0), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(\gpregsm1.user_valid_reg ), + .ram_empty_fb_i_reg(out), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_data_fifo_dvalid(sig_data_fifo_dvalid), + .sig_s_ready_out_reg(sig_s_ready_out_reg), + .sig_stream_rst(sig_stream_rst)); + Arty_Z7_20_axi_vdma_0_0_rd_status_flags_ss \grss.rsts + (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0 ), + .E(p_7_out), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out), + .ram_empty_i0__3(ram_empty_i0__3), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_stream_rst(sig_stream_rst)); + Arty_Z7_20_axi_vdma_0_0_rd_bin_cntr rpntr + (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_1 ), + .E(p_7_out), + .Q(Q), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .sig_stream_rst(sig_stream_rst)); +endmodule + +(* ORIG_REF_NAME = "rd_logic" *) +module Arty_Z7_20_axi_vdma_0_0_rd_logic_30 + (out, sig_ok_to_post_rd_addr_reg, - \INCLUDE_UNPACKING.lsig_cmd_loaded_reg , + hold_ff_q_reg, + E, \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram , - S, \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0 , - \count_reg[6] , - \gc1.count_d2_reg[6] , + ram_full_i_reg, + \sig_user_skid_reg_reg[0] , \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_1 , - sig_stream_rst, m_axi_mm2s_aclk, - ram_empty_i0__3, - ram_full_i_reg, - lsig_cmd_loaded, + SR, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_posted_to_axi_2_reg, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] , hold_ff_q, ram_full_i_reg_0, + ram_full_fb_i_reg, + ram_full_i_reg_1, + lsig_cmd_loaded, + Q, + \sig_token_cntr_reg[0] , \sig_token_cntr_reg[3] , - lsig_0ffset_cntr, - p_8_out, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_posted_to_axi_2_reg, sig_posted_to_axi_2_reg_0, - \INFERRED_GEN.cnt_i_reg[2] , - DOBDO, - D); + \gcc0.gc0.count_reg[7] , + ram_full_i_reg_2); output out; - output hold_ff_q_reg; - output p_7_out; - output dm2linebuf_mm2s_tvalid; - output [3:0]DI; - output [1:0]Q; - output hold_ff_q_reg_0; output sig_ok_to_post_rd_addr_reg; - output \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; + output hold_ff_q_reg; + output [0:0]E; output \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; - output [3:0]S; output \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0 ; - output [1:0]\count_reg[6] ; - output [6:0]\gc1.count_d2_reg[6] ; - output [6:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_1 ; - input sig_stream_rst; + output ram_full_i_reg; + output \sig_user_skid_reg_reg[0] ; + output [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_1 ; input m_axi_mm2s_aclk; - input ram_empty_i0__3; - input ram_full_i_reg; - input lsig_cmd_loaded; + input [0:0]SR; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_posted_to_axi_2_reg; + input \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; input hold_ff_q; input ram_full_i_reg_0; + input ram_full_fb_i_reg; + input [0:0]ram_full_i_reg_1; + input lsig_cmd_loaded; + input [7:0]Q; + input \sig_token_cntr_reg[0] ; input [3:0]\sig_token_cntr_reg[3] ; - input lsig_0ffset_cntr; - input p_8_out; - input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - input sig_posted_to_axi_2_reg; input sig_posted_to_axi_2_reg_0; - input [0:0]\INFERRED_GEN.cnt_i_reg[2] ; - input [0:0]DOBDO; - input [5:0]D; + input [7:0]\gcc0.gc0.count_reg[7] ; + input [0:0]ram_full_i_reg_2; - wire [5:0]D; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0 ; - wire [6:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_1 ; - wire [3:0]DI; - wire [0:0]DOBDO; - wire \INCLUDE_UNPACKING.lsig_cmd_loaded_reg ; - wire [0:0]\INFERRED_GEN.cnt_i_reg[2] ; - wire [1:0]Q; - wire [3:0]S; - wire cntr_en; - wire [1:0]\count_reg[6] ; - wire dm2linebuf_mm2s_tvalid; - wire [6:0]\gc1.count_d2_reg[6] ; + wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_1 ; + wire [0:0]E; + wire \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ; + wire [7:0]Q; + wire [0:0]SR; + wire [7:0]\gcc0.gc0.count_reg[7] ; wire hold_ff_q; wire hold_ff_q_reg; - wire hold_ff_q_reg_0; - wire lsig_0ffset_cntr; wire lsig_cmd_loaded; wire m_axi_mm2s_aclk; wire out; - wire p_7_out; - wire p_8_out; - wire ram_empty_i0__3; + wire p_2_out_0; + wire ram_full_fb_i_reg; wire ram_full_i_reg; wire ram_full_i_reg_0; + wire [0:0]ram_full_i_reg_1; + wire [0:0]ram_full_i_reg_2; + wire rpntr_n_1; wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; wire sig_ok_to_post_rd_addr_reg; wire sig_posted_to_axi_2_reg; wire sig_posted_to_axi_2_reg_0; - wire sig_stream_rst; + wire \sig_token_cntr_reg[0] ; wire [3:0]\sig_token_cntr_reg[3] ; + wire \sig_user_skid_reg_reg[0] ; - Arty_Z7_20_axi_vdma_0_0_rd_fwft \gr1.gr1_int.rfwft + Arty_Z7_20_axi_vdma_0_0_rd_fwft_34 \gr1.gr1_int.rfwft (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ), - .DOBDO(DOBDO), - .E(cntr_en), - .\INCLUDE_UNPACKING.lsig_cmd_loaded_reg (\INCLUDE_UNPACKING.lsig_cmd_loaded_reg ), - .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ), - .dm2linebuf_mm2s_tvalid(dm2linebuf_mm2s_tvalid), - .\gc1.count_reg[0] (p_7_out), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0 ), + .\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] (\INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0] ), + .SR(SR), + .\gc1.count_reg[7] (E), .hold_ff_q(hold_ff_q), - .hold_ff_q_reg(hold_ff_q_reg_0), - .lsig_0ffset_cntr(lsig_0ffset_cntr), + .hold_ff_q_reg(hold_ff_q_reg), .lsig_cmd_loaded(lsig_cmd_loaded), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .out(hold_ff_q_reg), - .p_8_out(p_8_out), - .ram_empty_fb_i_reg(out), - .ram_full_i_reg(ram_full_i_reg), + .out(out), + .ram_empty_fb_i_reg(p_2_out_0), .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .sig_stream_rst(sig_stream_rst)); + .\sig_user_skid_reg_reg[0] (\sig_user_skid_reg_reg[0] )); Arty_Z7_20_axi_vdma_0_0_dc_ss \grss.gdc.dc - (.D(D), - .DI(DI), - .E(p_7_out), - .Q(Q), - .S(S), - .\count_reg[6] (\count_reg[6] ), - .\gpregsm1.curr_fwft_state_reg[0] (cntr_en), + (.SR(SR), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .ram_full_i_reg(ram_full_i_reg_0), + .ram_empty_fb_i_reg(E), + .ram_full_i_reg(ram_full_i_reg_2), .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), .sig_ok_to_post_rd_addr_reg(sig_ok_to_post_rd_addr_reg), .sig_posted_to_axi_2_reg(sig_posted_to_axi_2_reg), .sig_posted_to_axi_2_reg_0(sig_posted_to_axi_2_reg_0), - .sig_stream_rst(sig_stream_rst), + .\sig_token_cntr_reg[0] (\sig_token_cntr_reg[0] ), .\sig_token_cntr_reg[3] (\sig_token_cntr_reg[3] )); - Arty_Z7_20_axi_vdma_0_0_rd_status_flags_ss \grss.rsts - (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0 ), - .E(p_7_out), + Arty_Z7_20_axi_vdma_0_0_rd_status_flags_ss_35 \grss.rsts + (.m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .out(p_2_out_0), + .ram_empty_fb_i_reg_0(rpntr_n_1)); + Arty_Z7_20_axi_vdma_0_0_rd_bin_cntr_36 rpntr + (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_1 ), + .Q(Q), + .SR(SR), + .\gcc0.gc0.count_reg[7] (\gcc0.gc0.count_reg[7] ), .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .out(p_2_out_0), + .ram_empty_fb_i_reg(rpntr_n_1), + .ram_empty_fb_i_reg_0(E), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .ram_full_i_reg(ram_full_i_reg), + .ram_full_i_reg_0(ram_full_i_reg_0), + .ram_full_i_reg_1(ram_full_i_reg_1), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg)); +endmodule + +(* ORIG_REF_NAME = "rd_logic" *) +module Arty_Z7_20_axi_vdma_0_0_rd_logic__parameterized0 + (out, + hold_ff_q_reg, + E, + \gc1.count_reg[2] , + sig_sf2pcc_xfer_valid, + sig_ibtt2dre_tready, + Q, + \gpr1.dout_i_reg[1] , + sig_stream_rst, + m_axi_s2mm_aclk, + ram_empty_i0__3, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + p_32_out, + hold_ff_q, + lsig_packer_full, + ram_full_i_reg, + ram_full_i_reg_0, + ram_full_fb_i_reg, + sig_clr_dbc_reg_reg); + output out; + output hold_ff_q_reg; + output [0:0]E; + output \gc1.count_reg[2] ; + output sig_sf2pcc_xfer_valid; + output sig_ibtt2dre_tready; + output [2:0]Q; + output [2:0]\gpr1.dout_i_reg[1] ; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input ram_empty_i0__3; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input p_32_out; + input hold_ff_q; + input lsig_packer_full; + input ram_full_i_reg; + input ram_full_i_reg_0; + input ram_full_fb_i_reg; + input sig_clr_dbc_reg_reg; + + wire [0:0]E; + wire [2:0]Q; + wire \gc1.count_reg[2] ; + wire [2:0]\gpr1.dout_i_reg[1] ; + wire \grhf.rhf_n_0 ; + wire hold_ff_q; + wire hold_ff_q_reg; + wire lsig_packer_full; + wire m_axi_s2mm_aclk; + wire out; + wire p_32_out; + wire p_3_out; + wire ram_empty_i0__3; + wire ram_full_fb_i_reg; + wire ram_full_i_reg; + wire ram_full_i_reg_0; + wire sig_clr_dbc_reg_reg; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + wire sig_ibtt2dre_tready; + wire sig_sf2pcc_xfer_valid; + wire sig_stream_rst; + + Arty_Z7_20_axi_vdma_0_0_rd_handshaking_flags__parameterized0 \grhf.rhf + (.\gv.ram_valid_d1_reg_0 (\grhf.rhf_n_0 ), + .hold_ff_q(hold_ff_q), + .hold_ff_q_reg(hold_ff_q_reg), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(p_3_out), + .p_32_out(p_32_out), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .sig_sf2pcc_xfer_valid(sig_sf2pcc_xfer_valid), + .sig_stream_rst(sig_stream_rst)); + Arty_Z7_20_axi_vdma_0_0_dc_ss__parameterized0 \grss.gdc.dc + (.E(\gc1.count_reg[2] ), + .lsig_packer_full(lsig_packer_full), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .ram_full_i_reg(ram_full_i_reg), + .ram_full_i_reg_0(ram_full_i_reg_0), + .sig_clr_dbc_reg_reg(sig_clr_dbc_reg_reg), + .sig_ibtt2dre_tready(sig_ibtt2dre_tready), + .sig_stream_rst(sig_stream_rst)); + Arty_Z7_20_axi_vdma_0_0_rd_status_flags_ss__parameterized0 \grss.rsts + (.E(E), + .\gc1.count_reg[2] (\gc1.count_reg[2] ), + .\gpr1.dout_i_reg[10] (p_3_out), + .\gv.ram_valid_d1_reg (\grhf.rhf_n_0 ), + .hold_ff_q(hold_ff_q), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), .out(out), + .p_32_out(p_32_out), .ram_empty_i0__3(ram_empty_i0__3), - .sig_cmd_stat_rst_user_reg_n_cdc_from_reg(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), .sig_stream_rst(sig_stream_rst)); - Arty_Z7_20_axi_vdma_0_0_rd_bin_cntr rpntr - (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_1 ), - .E(p_7_out), - .\gc1.count_d2_reg[6]_0 (\gc1.count_d2_reg[6] ), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + Arty_Z7_20_axi_vdma_0_0_rd_bin_cntr__parameterized0 rpntr + (.E(\gc1.count_reg[2] ), + .Q(Q), + .\gpr1.dout_i_reg[1] (\gpr1.dout_i_reg[1] ), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), .sig_stream_rst(sig_stream_rst)); endmodule @@ -32559,20 +80906,20 @@ module Arty_Z7_20_axi_vdma_0_0_rd_status_flags_ss \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram , sig_stream_rst, ram_empty_i0__3, - m_axi_mm2s_aclk, + m_axi_s2mm_aclk, E, sig_cmd_stat_rst_user_reg_n_cdc_from_reg); output out; output \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; input sig_stream_rst; input ram_empty_i0__3; - input m_axi_mm2s_aclk; + input m_axi_s2mm_aclk; input [0:0]E; input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; wire [0:0]E; - wire m_axi_mm2s_aclk; + wire m_axi_s2mm_aclk; (* DONT_TOUCH *) wire ram_empty_fb_i; (* DONT_TOUCH *) wire ram_empty_i; wire ram_empty_i0__3; @@ -32582,37 +80929,399 @@ module Arty_Z7_20_axi_vdma_0_0_rd_status_flags_ss assign out = ram_empty_fb_i; LUT3 #( .INIT(8'h4F)) - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1 + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1__0 (.I0(ram_empty_fb_i), .I1(E), .I2(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), .O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram )); (* DONT_TOUCH *) (* KEEP = "yes" *) - (* equivalent_register_removal = "no" *) - FDSE #( + (* equivalent_register_removal = "no" *) + FDSE #( + .INIT(1'b1)) + ram_empty_fb_i_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(ram_empty_i0__3), + .Q(ram_empty_fb_i), + .S(sig_stream_rst)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDSE #( + .INIT(1'b1)) + ram_empty_i_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(ram_empty_i0__3), + .Q(ram_empty_i), + .S(sig_stream_rst)); +endmodule + +(* ORIG_REF_NAME = "rd_status_flags_ss" *) +module Arty_Z7_20_axi_vdma_0_0_rd_status_flags_ss_35 + (out, + ram_empty_fb_i_reg_0, + m_axi_mm2s_aclk); + output out; + input ram_empty_fb_i_reg_0; + input m_axi_mm2s_aclk; + + wire m_axi_mm2s_aclk; + (* DONT_TOUCH *) wire ram_empty_fb_i; + wire ram_empty_fb_i_reg_0; + (* DONT_TOUCH *) wire ram_empty_i; + + assign out = ram_empty_fb_i; + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b1)) + ram_empty_fb_i_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(ram_empty_fb_i_reg_0), + .Q(ram_empty_fb_i), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b1)) + ram_empty_i_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(ram_empty_fb_i_reg_0), + .Q(ram_empty_i), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "rd_status_flags_ss" *) +module Arty_Z7_20_axi_vdma_0_0_rd_status_flags_ss__parameterized0 + (out, + \gpr1.dout_i_reg[10] , + E, + \gc1.count_reg[2] , + sig_stream_rst, + ram_empty_i0__3, + m_axi_s2mm_aclk, + p_32_out, + hold_ff_q, + \gv.ram_valid_d1_reg ); + output out; + output \gpr1.dout_i_reg[10] ; + output [0:0]E; + output [0:0]\gc1.count_reg[2] ; + input sig_stream_rst; + input ram_empty_i0__3; + input m_axi_s2mm_aclk; + input p_32_out; + input hold_ff_q; + input \gv.ram_valid_d1_reg ; + + wire [0:0]E; + wire [0:0]\gc1.count_reg[2] ; + wire \gv.ram_valid_d1_reg ; + wire hold_ff_q; + wire m_axi_s2mm_aclk; + wire p_32_out; + (* DONT_TOUCH *) wire ram_empty_fb_i; + (* DONT_TOUCH *) wire ram_empty_i; + wire ram_empty_i0__3; + wire sig_stream_rst; + + assign \gpr1.dout_i_reg[10] = ram_empty_i; + assign out = ram_empty_fb_i; + LUT5 #( + .INIT(32'h0000EF01)) + \gc1.count[2]_i_1__1 + (.I0(\gv.ram_valid_d1_reg ), + .I1(hold_ff_q), + .I2(ram_empty_i), + .I3(p_32_out), + .I4(ram_empty_fb_i), + .O(\gc1.count_reg[2] )); + LUT5 #( + .INIT(32'h0000AAA3)) + \gpr1.dout_i[10]_i_1 + (.I0(p_32_out), + .I1(ram_empty_i), + .I2(hold_ff_q), + .I3(\gv.ram_valid_d1_reg ), + .I4(ram_empty_fb_i), + .O(E)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDSE #( + .INIT(1'b1)) + ram_empty_fb_i_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(ram_empty_i0__3), + .Q(ram_empty_fb_i), + .S(sig_stream_rst)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDSE #( + .INIT(1'b1)) + ram_empty_i_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(ram_empty_i0__3), + .Q(ram_empty_i), + .S(sig_stream_rst)); +endmodule + +(* ORIG_REF_NAME = "reset_builtin" *) +module Arty_Z7_20_axi_vdma_0_0_reset_builtin + (RST, + s_axis_s2mm_aclk, + sig_reset_reg, + m_axi_s2mm_aclk); + output RST; + input s_axis_s2mm_aclk; + input sig_reset_reg; + input m_axi_s2mm_aclk; + + wire RST; + wire m_axi_s2mm_aclk; + (* async_reg = "true" *) (* msgon = "true" *) wire [5:0]power_on_rd_rst; + (* async_reg = "true" *) (* msgon = "true" *) wire [5:0]power_on_wr_rst; + (* async_reg = "true" *) (* msgon = "true" *) wire rd_rst_reg1; + (* async_reg = "true" *) (* msgon = "true" *) wire rd_rst_reg2; + wire \rsync.ric.wr_rst_fb_reg[1]_srl4_n_0 ; + wire \rsync.ric.wr_rst_fb_reg_n_0_[0] ; + wire \rsync.ric.wr_rst_reg_i_1_n_0 ; + wire s_axis_s2mm_aclk; + wire sig_reset_reg; + wire wr_rst_reg; + (* async_reg = "true" *) (* msgon = "true" *) wire wr_rst_reg1; + (* async_reg = "true" *) (* msgon = "true" *) wire wr_rst_reg2; + + LUT2 #( + .INIT(4'hE)) + \gf18e1_inst.sngfifo18e1_i_2 + (.I0(wr_rst_reg), + .I1(power_on_wr_rst[0]), + .O(RST)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b1)) + \rsync.ric.power_on_rd_rst_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(power_on_rd_rst[1]), + .Q(power_on_rd_rst[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b1)) + \rsync.ric.power_on_rd_rst_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(power_on_rd_rst[2]), + .Q(power_on_rd_rst[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b1)) + \rsync.ric.power_on_rd_rst_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(power_on_rd_rst[3]), + .Q(power_on_rd_rst[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b1)) + \rsync.ric.power_on_rd_rst_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(power_on_rd_rst[4]), + .Q(power_on_rd_rst[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b1)) + \rsync.ric.power_on_rd_rst_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(power_on_rd_rst[5]), + .Q(power_on_rd_rst[4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b1)) + \rsync.ric.power_on_rd_rst_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(1'b0), + .Q(power_on_rd_rst[5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b1)) + \rsync.ric.power_on_wr_rst_reg[0] + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(power_on_wr_rst[1]), + .Q(power_on_wr_rst[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b1)) + \rsync.ric.power_on_wr_rst_reg[1] + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(power_on_wr_rst[2]), + .Q(power_on_wr_rst[1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b1)) + \rsync.ric.power_on_wr_rst_reg[2] + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(power_on_wr_rst[3]), + .Q(power_on_wr_rst[2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b1)) + \rsync.ric.power_on_wr_rst_reg[3] + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(power_on_wr_rst[4]), + .Q(power_on_wr_rst[3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( .INIT(1'b1)) - ram_empty_fb_i_reg - (.C(m_axi_mm2s_aclk), + \rsync.ric.power_on_wr_rst_reg[4] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(ram_empty_i0__3), - .Q(ram_empty_fb_i), - .S(sig_stream_rst)); - (* DONT_TOUCH *) + .D(power_on_wr_rst[5]), + .Q(power_on_wr_rst[4]), + .R(1'b0)); + (* ASYNC_REG *) (* KEEP = "yes" *) - (* equivalent_register_removal = "no" *) - FDSE #( + (* msgon = "true" *) + FDRE #( .INIT(1'b1)) - ram_empty_i_reg - (.C(m_axi_mm2s_aclk), + \rsync.ric.power_on_wr_rst_reg[5] + (.C(s_axis_s2mm_aclk), .CE(1'b1), - .D(ram_empty_i0__3), - .Q(ram_empty_i), - .S(sig_stream_rst)); + .D(1'b0), + .Q(power_on_wr_rst[5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDPE #( + .INIT(1'b0)) + \rsync.ric.rd_rst_reg1_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(1'b0), + .PRE(sig_reset_reg), + .Q(rd_rst_reg1)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDPE #( + .INIT(1'b0)) + \rsync.ric.rd_rst_reg2_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(rd_rst_reg1), + .PRE(sig_reset_reg), + .Q(rd_rst_reg2)); + FDRE #( + .INIT(1'b0)) + \rsync.ric.wr_rst_fb_reg[0] + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(\rsync.ric.wr_rst_fb_reg[1]_srl4_n_0 ), + .Q(\rsync.ric.wr_rst_fb_reg_n_0_[0] ), + .R(1'b0)); + (* srl_bus_name = "U0/\GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.wr_rst_fb_reg " *) + (* srl_name = "U0/\GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.wr_rst_fb_reg[1]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \rsync.ric.wr_rst_fb_reg[1]_srl4 + (.A0(1'b1), + .A1(1'b1), + .A2(1'b0), + .A3(1'b0), + .CE(1'b1), + .CLK(s_axis_s2mm_aclk), + .D(wr_rst_reg), + .Q(\rsync.ric.wr_rst_fb_reg[1]_srl4_n_0 )); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDPE #( + .INIT(1'b0)) + \rsync.ric.wr_rst_reg1_reg + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(1'b0), + .PRE(sig_reset_reg), + .Q(wr_rst_reg1)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDPE #( + .INIT(1'b0)) + \rsync.ric.wr_rst_reg2_reg + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(wr_rst_reg1), + .PRE(sig_reset_reg), + .Q(wr_rst_reg2)); + LUT2 #( + .INIT(4'h2)) + \rsync.ric.wr_rst_reg_i_1 + (.I0(wr_rst_reg), + .I1(\rsync.ric.wr_rst_fb_reg_n_0_[0] ), + .O(\rsync.ric.wr_rst_reg_i_1_n_0 )); + FDPE #( + .INIT(1'b0)) + \rsync.ric.wr_rst_reg_reg + (.C(s_axis_s2mm_aclk), + .CE(1'b1), + .D(\rsync.ric.wr_rst_reg_i_1_n_0 ), + .PRE(wr_rst_reg2), + .Q(wr_rst_reg)); endmodule (* ORIG_REF_NAME = "reset_builtin" *) -module Arty_Z7_20_axi_vdma_0_0_reset_builtin +module Arty_Z7_20_axi_vdma_0_0_reset_builtin_39 (RST, m_axi_mm2s_aclk, s_axis_fifo_ainit_nosync_reg, @@ -32639,7 +81348,7 @@ module Arty_Z7_20_axi_vdma_0_0_reset_builtin LUT2 #( .INIT(4'hE)) - \gf36e1_inst.sngfifo36e1_i_2__2 + \gf36e1_inst.sngfifo36e1_i_2__0 (.I0(rd_rst_reg), .I1(power_on_rd_rst[0]), .O(RST)); @@ -32858,646 +81567,1513 @@ endmodule (* ORIG_REF_NAME = "updn_cntr" *) module Arty_Z7_20_axi_vdma_0_0_updn_cntr - (DI, - Q, - sig_ok_to_post_rd_addr_reg, - S, - \count_reg[6]_0 , - ram_full_i_reg, - \sig_token_cntr_reg[3] , - sig_posted_to_axi_2_reg, + (sig_ok_to_post_rd_addr_reg, sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_posted_to_axi_2_reg, + ram_empty_fb_i_reg, + \sig_token_cntr_reg[0] , + \sig_token_cntr_reg[3] , sig_posted_to_axi_2_reg_0, - E, - sig_stream_rst, - \gpregsm1.curr_fwft_state_reg[0] , - D, + SR, + ram_full_i_reg, m_axi_mm2s_aclk); - output [3:0]DI; - output [1:0]Q; output sig_ok_to_post_rd_addr_reg; - output [3:0]S; - output [1:0]\count_reg[6]_0 ; - input ram_full_i_reg; - input [3:0]\sig_token_cntr_reg[3] ; - input sig_posted_to_axi_2_reg; input sig_cmd_stat_rst_user_reg_n_cdc_from_reg; + input sig_posted_to_axi_2_reg; + input ram_empty_fb_i_reg; + input \sig_token_cntr_reg[0] ; + input [3:0]\sig_token_cntr_reg[3] ; input sig_posted_to_axi_2_reg_0; - input [0:0]E; - input sig_stream_rst; - input [0:0]\gpregsm1.curr_fwft_state_reg[0] ; - input [5:0]D; + input [0:0]SR; + input [0:0]ram_full_i_reg; input m_axi_mm2s_aclk; - wire [5:0]D; - wire [3:0]DI; - wire [0:0]E; - wire [1:0]Q; - wire [3:0]S; + wire [0:0]SR; wire \count[0]_i_1_n_0 ; - wire [1:0]\count_reg[6]_0 ; - wire [6:5]count_reg__0; - wire [0:0]\gpregsm1.curr_fwft_state_reg[0] ; + wire \count[4]_i_2_n_0 ; + wire \count[4]_i_3_n_0 ; + wire \count[4]_i_4_n_0 ; + wire \count[4]_i_5_n_0 ; + wire \count[4]_i_6_n_0 ; + wire \count[7]_i_3_n_0 ; + wire \count[7]_i_4_n_0 ; + wire \count[7]_i_5_n_0 ; + wire \count_reg[4]_i_1_n_0 ; + wire \count_reg[4]_i_1_n_1 ; + wire \count_reg[4]_i_1_n_2 ; + wire \count_reg[4]_i_1_n_3 ; + wire \count_reg[4]_i_1_n_4 ; + wire \count_reg[4]_i_1_n_5 ; + wire \count_reg[4]_i_1_n_6 ; + wire \count_reg[4]_i_1_n_7 ; + wire \count_reg[7]_i_2_n_2 ; + wire \count_reg[7]_i_2_n_3 ; + wire \count_reg[7]_i_2_n_5 ; + wire \count_reg[7]_i_2_n_6 ; + wire \count_reg[7]_i_2_n_7 ; + wire [7:5]count_reg__0; + wire \count_reg_n_0_[0] ; + wire \count_reg_n_0_[1] ; + wire \count_reg_n_0_[2] ; + wire \count_reg_n_0_[3] ; + wire \count_reg_n_0_[4] ; wire m_axi_mm2s_aclk; - wire ram_full_i_reg; + wire ram_empty_fb_i_reg; + wire [0:0]ram_full_i_reg; wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg; - wire sig_ok_to_post_rd_addr_i_2_n_0; - wire sig_ok_to_post_rd_addr_i_4_n_0; - wire sig_ok_to_post_rd_addr_i_5_n_0; + wire sig_ok_to_post_rd_addr0; + wire sig_ok_to_post_rd_addr_i_3_n_0; wire sig_ok_to_post_rd_addr_reg; wire sig_posted_to_axi_2_reg; wire sig_posted_to_axi_2_reg_0; - wire sig_stream_rst; + wire \sig_token_cntr_reg[0] ; wire [3:0]\sig_token_cntr_reg[3] ; + wire [3:2]\NLW_count_reg[7]_i_2_CO_UNCONNECTED ; + wire [3:3]\NLW_count_reg[7]_i_2_O_UNCONNECTED ; LUT1 #( .INIT(2'h1)) \count[0]_i_1 - (.I0(Q[0]), + (.I0(\count_reg_n_0_[0] ), .O(\count[0]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \count[4]_i_2 + (.I0(\count_reg_n_0_[1] ), + .O(\count[4]_i_2_n_0 )); + LUT2 #( + .INIT(4'h9)) + \count[4]_i_3 + (.I0(\count_reg_n_0_[3] ), + .I1(\count_reg_n_0_[4] ), + .O(\count[4]_i_3_n_0 )); + LUT2 #( + .INIT(4'h9)) + \count[4]_i_4 + (.I0(\count_reg_n_0_[2] ), + .I1(\count_reg_n_0_[3] ), + .O(\count[4]_i_4_n_0 )); + LUT2 #( + .INIT(4'h9)) + \count[4]_i_5 + (.I0(\count_reg_n_0_[1] ), + .I1(\count_reg_n_0_[2] ), + .O(\count[4]_i_5_n_0 )); + LUT2 #( + .INIT(4'h6)) + \count[4]_i_6 + (.I0(\count_reg_n_0_[1] ), + .I1(ram_empty_fb_i_reg), + .O(\count[4]_i_6_n_0 )); + LUT2 #( + .INIT(4'h9)) + \count[7]_i_3 + (.I0(count_reg__0[6]), + .I1(count_reg__0[7]), + .O(\count[7]_i_3_n_0 )); + LUT2 #( + .INIT(4'h9)) + \count[7]_i_4 + (.I0(count_reg__0[5]), + .I1(count_reg__0[6]), + .O(\count[7]_i_4_n_0 )); + LUT2 #( + .INIT(4'h9)) + \count[7]_i_5 + (.I0(\count_reg_n_0_[4] ), + .I1(count_reg__0[5]), + .O(\count[7]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \count_reg[0] (.C(m_axi_mm2s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_full_i_reg), .D(\count[0]_i_1_n_0 ), - .Q(Q[0]), - .R(sig_stream_rst)); + .Q(\count_reg_n_0_[0] ), + .R(SR)); FDRE #( .INIT(1'b0)) \count_reg[1] (.C(m_axi_mm2s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), - .D(D[0]), - .Q(DI[1]), - .R(sig_stream_rst)); + .CE(ram_full_i_reg), + .D(\count_reg[4]_i_1_n_7 ), + .Q(\count_reg_n_0_[1] ), + .R(SR)); FDRE #( .INIT(1'b0)) \count_reg[2] (.C(m_axi_mm2s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), - .D(D[1]), - .Q(DI[2]), - .R(sig_stream_rst)); + .CE(ram_full_i_reg), + .D(\count_reg[4]_i_1_n_6 ), + .Q(\count_reg_n_0_[2] ), + .R(SR)); FDRE #( .INIT(1'b0)) \count_reg[3] (.C(m_axi_mm2s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), - .D(D[2]), - .Q(DI[3]), - .R(sig_stream_rst)); + .CE(ram_full_i_reg), + .D(\count_reg[4]_i_1_n_5 ), + .Q(\count_reg_n_0_[3] ), + .R(SR)); FDRE #( .INIT(1'b0)) \count_reg[4] (.C(m_axi_mm2s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), - .D(D[3]), - .Q(Q[1]), - .R(sig_stream_rst)); + .CE(ram_full_i_reg), + .D(\count_reg[4]_i_1_n_4 ), + .Q(\count_reg_n_0_[4] ), + .R(SR)); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \count_reg[4]_i_1 + (.CI(1'b0), + .CO({\count_reg[4]_i_1_n_0 ,\count_reg[4]_i_1_n_1 ,\count_reg[4]_i_1_n_2 ,\count_reg[4]_i_1_n_3 }), + .CYINIT(\count_reg_n_0_[0] ), + .DI({\count_reg_n_0_[3] ,\count_reg_n_0_[2] ,\count_reg_n_0_[1] ,\count[4]_i_2_n_0 }), + .O({\count_reg[4]_i_1_n_4 ,\count_reg[4]_i_1_n_5 ,\count_reg[4]_i_1_n_6 ,\count_reg[4]_i_1_n_7 }), + .S({\count[4]_i_3_n_0 ,\count[4]_i_4_n_0 ,\count[4]_i_5_n_0 ,\count[4]_i_6_n_0 })); FDRE #( .INIT(1'b0)) \count_reg[5] (.C(m_axi_mm2s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), - .D(D[4]), + .CE(ram_full_i_reg), + .D(\count_reg[7]_i_2_n_7 ), .Q(count_reg__0[5]), - .R(sig_stream_rst)); + .R(SR)); FDRE #( .INIT(1'b0)) \count_reg[6] (.C(m_axi_mm2s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), - .D(D[5]), + .CE(ram_full_i_reg), + .D(\count_reg[7]_i_2_n_6 ), .Q(count_reg__0[6]), - .R(sig_stream_rst)); - LUT2 #( - .INIT(4'h9)) - p_0_out_carry__0_i_1 - (.I0(count_reg__0[5]), - .I1(count_reg__0[6]), - .O(\count_reg[6]_0 [1])); - LUT2 #( - .INIT(4'h9)) - p_0_out_carry__0_i_2 - (.I0(Q[1]), - .I1(count_reg__0[5]), - .O(\count_reg[6]_0 [0])); - LUT1 #( - .INIT(2'h1)) - p_0_out_carry_i_1 - (.I0(DI[1]), - .O(DI[0])); - LUT2 #( - .INIT(4'h9)) - p_0_out_carry_i_2 - (.I0(DI[3]), - .I1(Q[1]), - .O(S[3])); - LUT2 #( - .INIT(4'h9)) - p_0_out_carry_i_3 - (.I0(DI[2]), - .I1(DI[3]), - .O(S[2])); - LUT2 #( - .INIT(4'h9)) - p_0_out_carry_i_4 - (.I0(DI[1]), - .I1(DI[2]), - .O(S[1])); - LUT2 #( - .INIT(4'h6)) - p_0_out_carry_i_5 - (.I0(DI[1]), - .I1(E), - .O(S[0])); - LUT5 #( - .INIT(32'h00001000)) + .R(SR)); + FDRE #( + .INIT(1'b0)) + \count_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(ram_full_i_reg), + .D(\count_reg[7]_i_2_n_5 ), + .Q(count_reg__0[7]), + .R(SR)); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \count_reg[7]_i_2 + (.CI(\count_reg[4]_i_1_n_0 ), + .CO({\NLW_count_reg[7]_i_2_CO_UNCONNECTED [3:2],\count_reg[7]_i_2_n_2 ,\count_reg[7]_i_2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,count_reg__0[5],\count_reg_n_0_[4] }), + .O({\NLW_count_reg[7]_i_2_O_UNCONNECTED [3],\count_reg[7]_i_2_n_5 ,\count_reg[7]_i_2_n_6 ,\count_reg[7]_i_2_n_7 }), + .S({1'b0,\count[7]_i_3_n_0 ,\count[7]_i_4_n_0 ,\count[7]_i_5_n_0 })); + LUT3 #( + .INIT(8'h08)) sig_ok_to_post_rd_addr_i_1 - (.I0(sig_ok_to_post_rd_addr_i_2_n_0), - .I1(sig_posted_to_axi_2_reg), - .I2(sig_ok_to_post_rd_addr_i_4_n_0), - .I3(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), - .I4(sig_posted_to_axi_2_reg_0), + (.I0(sig_ok_to_post_rd_addr0), + .I1(sig_cmd_stat_rst_user_reg_n_cdc_from_reg), + .I2(sig_posted_to_axi_2_reg), .O(sig_ok_to_post_rd_addr_reg)); LUT6 #( - .INIT(64'hFFFFFFFEEEEEEEEF)) + .INIT(64'h0000000000D04D04)) sig_ok_to_post_rd_addr_i_2 - (.I0(sig_ok_to_post_rd_addr_i_5_n_0), - .I1(ram_full_i_reg), - .I2(\sig_token_cntr_reg[3] [2]), - .I3(\sig_token_cntr_reg[3] [0]), - .I4(\sig_token_cntr_reg[3] [1]), - .I5(\sig_token_cntr_reg[3] [3]), - .O(sig_ok_to_post_rd_addr_i_2_n_0)); - LUT6 #( - .INIT(64'hDBFFFDBFFFDBBFFD)) - sig_ok_to_post_rd_addr_i_4 - (.I0(\sig_token_cntr_reg[3] [0]), - .I1(Q[1]), - .I2(count_reg__0[5]), - .I3(count_reg__0[6]), - .I4(\sig_token_cntr_reg[3] [1]), - .I5(\sig_token_cntr_reg[3] [2]), - .O(sig_ok_to_post_rd_addr_i_4_n_0)); - LUT6 #( - .INIT(64'hBBB82BB822B82228)) - sig_ok_to_post_rd_addr_i_5 + (.I0(count_reg__0[7]), + .I1(sig_ok_to_post_rd_addr_i_3_n_0), + .I2(\sig_token_cntr_reg[0] ), + .I3(\sig_token_cntr_reg[3] [2]), + .I4(\sig_token_cntr_reg[3] [3]), + .I5(sig_posted_to_axi_2_reg_0), + .O(sig_ok_to_post_rd_addr0)); + LUT4 #( + .INIT(16'h4513)) + sig_ok_to_post_rd_addr_i_3 (.I0(count_reg__0[6]), - .I1(\sig_token_cntr_reg[3] [2]), - .I2(\sig_token_cntr_reg[3] [0]), + .I1(\sig_token_cntr_reg[3] [0]), + .I2(count_reg__0[5]), .I3(\sig_token_cntr_reg[3] [1]), - .I4(Q[1]), - .I5(count_reg__0[5]), - .O(sig_ok_to_post_rd_addr_i_5_n_0)); + .O(sig_ok_to_post_rd_addr_i_3_n_0)); +endmodule + +(* ORIG_REF_NAME = "updn_cntr" *) +module Arty_Z7_20_axi_vdma_0_0_updn_cntr__parameterized0 + (sig_ibtt2dre_tready, + lsig_packer_full, + ram_full_i_reg, + ram_full_i_reg_0, + E, + ram_full_fb_i_reg, + sig_clr_dbc_reg_reg, + sig_stream_rst, + m_axi_s2mm_aclk); + output sig_ibtt2dre_tready; + input lsig_packer_full; + input ram_full_i_reg; + input ram_full_i_reg_0; + input [0:0]E; + input ram_full_fb_i_reg; + input sig_clr_dbc_reg_reg; + input sig_stream_rst; + input m_axi_s2mm_aclk; + + wire [0:0]E; + wire \count[0]_i_1_n_0 ; + wire \count[1]_i_1_n_0 ; + wire \count[2]_i_1_n_0 ; + wire \count_reg_n_0_[0] ; + wire \count_reg_n_0_[1] ; + wire \count_reg_n_0_[2] ; + wire lsig_packer_full; + wire m_axi_s2mm_aclk; + wire ram_full_fb_i_reg; + wire ram_full_i_reg; + wire ram_full_i_reg_0; + wire sig_clr_dbc_reg_reg; + wire sig_ibtt2dre_tready; + wire sig_stream_rst; + + (* SOFT_HLUTNM = "soft_lutpair175" *) + LUT4 #( + .INIT(16'h2DD2)) + \count[0]_i_1 + (.I0(sig_clr_dbc_reg_reg), + .I1(ram_full_fb_i_reg), + .I2(E), + .I3(\count_reg_n_0_[0] ), + .O(\count[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair175" *) + LUT5 #( + .INIT(32'hBDBB4244)) + \count[1]_i_1 + (.I0(\count_reg_n_0_[0] ), + .I1(E), + .I2(ram_full_fb_i_reg), + .I3(sig_clr_dbc_reg_reg), + .I4(\count_reg_n_0_[1] ), + .O(\count[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'hEFF7EFEF10081010)) + \count[2]_i_1 + (.I0(\count_reg_n_0_[0] ), + .I1(\count_reg_n_0_[1] ), + .I2(E), + .I3(ram_full_fb_i_reg), + .I4(sig_clr_dbc_reg_reg), + .I5(\count_reg_n_0_[2] ), + .O(\count[2]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \count_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\count[0]_i_1_n_0 ), + .Q(\count_reg_n_0_[0] ), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \count_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\count[1]_i_1_n_0 ), + .Q(\count_reg_n_0_[1] ), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \count_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(\count[2]_i_1_n_0 ), + .Q(\count_reg_n_0_[2] ), + .R(sig_stream_rst)); + LUT6 #( + .INIT(64'h0007007700770077)) + \sig_data_reg_out[7]_i_3 + (.I0(lsig_packer_full), + .I1(ram_full_i_reg), + .I2(\count_reg_n_0_[2] ), + .I3(ram_full_i_reg_0), + .I4(\count_reg_n_0_[0] ), + .I5(\count_reg_n_0_[1] ), + .O(sig_ibtt2dre_tready)); endmodule (* ORIG_REF_NAME = "wr_bin_cntr" *) module Arty_Z7_20_axi_vdma_0_0_wr_bin_cntr - (ram_empty_i0__3, + (ram_full_i_reg, + ram_empty_i0__3, Q, - ram_full_i_reg, + out, + lsig_packer_full, + ram_full_fb_i_reg, p_7_out, E, ram_empty_fb_i_reg, - \gc1.count_d2_reg[6] , - \gc1.count_d1_reg[6] , - out, + \gc1.count_d2_reg[7] , + \gc1.count_d1_reg[7] , sig_stream_rst, - m_axi_mm2s_aclk); - output ram_empty_i0__3; - output [6:0]Q; + m_axi_s2mm_aclk); output ram_full_i_reg; + output ram_empty_i0__3; + output [7:0]Q; + input out; + input lsig_packer_full; + input ram_full_fb_i_reg; input p_7_out; input [0:0]E; input ram_empty_fb_i_reg; - input [6:0]\gc1.count_d2_reg[6] ; - input [6:0]\gc1.count_d1_reg[6] ; - input out; + input [7:0]\gc1.count_d2_reg[7] ; + input [7:0]\gc1.count_d1_reg[7] ; input sig_stream_rst; - input m_axi_mm2s_aclk; + input m_axi_s2mm_aclk; wire [0:0]E; - wire [6:0]Q; - wire [6:0]\gc1.count_d1_reg[6] ; - wire [6:0]\gc1.count_d2_reg[6] ; - wire \gcc0.gc0.count[6]_i_2_n_0 ; + wire [7:0]Q; + wire [7:0]\gc1.count_d1_reg[7] ; + wire [7:0]\gc1.count_d2_reg[7] ; + wire \gcc0.gc0.count[7]_i_2__0_n_0 ; + wire \gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ; wire \gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ; - wire \gwss.wsts/comp0 ; wire \gwss.wsts/comp1 ; - wire m_axi_mm2s_aclk; + wire lsig_packer_full; + wire m_axi_s2mm_aclk; wire out; - wire [6:0]p_12_out; + wire [7:0]p_12_out; wire p_7_out; - wire [6:0]plusOp__0; - wire ram_empty_fb_i_i_3_n_0; - wire ram_empty_fb_i_i_4_n_0; + wire [7:0]plusOp__2; + wire ram_empty_fb_i_i_3__0_n_0; + wire ram_empty_fb_i_i_4__0_n_0; + wire ram_empty_fb_i_i_5__0_n_0; wire ram_empty_fb_i_reg; wire ram_empty_i0__3; - wire ram_full_fb_i_i_4_n_0; - wire ram_full_fb_i_i_5_n_0; - wire ram_full_fb_i_i_6_n_0; - wire ram_full_fb_i_i_7_n_0; + wire ram_full_fb_i_i_4__0_n_0; + wire ram_full_fb_i_i_5__0_n_0; + wire ram_full_fb_i_i_6__0_n_0; + wire ram_full_fb_i_i_7__0_n_0; + wire ram_full_fb_i_i_8_n_0; + wire ram_full_fb_i_i_9_n_0; + wire ram_full_fb_i_reg; wire ram_full_i_reg; wire sig_stream_rst; LUT1 #( .INIT(2'h1)) - \gcc0.gc0.count[0]_i_1 + \gcc0.gc0.count[0]_i_1__0 (.I0(p_12_out[0]), - .O(plusOp__0[0])); - (* SOFT_HLUTNM = "soft_lutpair49" *) + .O(plusOp__2[0])); + (* SOFT_HLUTNM = "soft_lutpair172" *) LUT2 #( .INIT(4'h6)) - \gcc0.gc0.count[1]_i_1 + \gcc0.gc0.count[1]_i_1__0 (.I0(p_12_out[0]), .I1(p_12_out[1]), - .O(plusOp__0[1])); - (* SOFT_HLUTNM = "soft_lutpair50" *) + .O(plusOp__2[1])); LUT3 #( .INIT(8'h78)) - \gcc0.gc0.count[2]_i_1 + \gcc0.gc0.count[2]_i_1__0 (.I0(p_12_out[0]), .I1(p_12_out[1]), .I2(p_12_out[2]), - .O(plusOp__0[2])); - (* SOFT_HLUTNM = "soft_lutpair50" *) + .O(plusOp__2[2])); + (* SOFT_HLUTNM = "soft_lutpair171" *) LUT4 #( .INIT(16'h7F80)) - \gcc0.gc0.count[3]_i_1 + \gcc0.gc0.count[3]_i_1__0 (.I0(p_12_out[1]), .I1(p_12_out[0]), .I2(p_12_out[2]), .I3(p_12_out[3]), + .O(plusOp__2[3])); + (* SOFT_HLUTNM = "soft_lutpair171" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \gcc0.gc0.count[4]_i_1__0 + (.I0(p_12_out[2]), + .I1(p_12_out[0]), + .I2(p_12_out[1]), + .I3(p_12_out[3]), + .I4(p_12_out[4]), + .O(plusOp__2[4])); + LUT6 #( + .INIT(64'h7FFFFFFF80000000)) + \gcc0.gc0.count[5]_i_1__0 + (.I0(p_12_out[3]), + .I1(p_12_out[1]), + .I2(p_12_out[0]), + .I3(p_12_out[2]), + .I4(p_12_out[4]), + .I5(p_12_out[5]), + .O(plusOp__2[5])); + (* SOFT_HLUTNM = "soft_lutpair173" *) + LUT2 #( + .INIT(4'h6)) + \gcc0.gc0.count[6]_i_1__0 + (.I0(\gcc0.gc0.count[7]_i_2__0_n_0 ), + .I1(p_12_out[6]), + .O(plusOp__2[6])); + (* SOFT_HLUTNM = "soft_lutpair173" *) + LUT3 #( + .INIT(8'h78)) + \gcc0.gc0.count[7]_i_1__0 + (.I0(\gcc0.gc0.count[7]_i_2__0_n_0 ), + .I1(p_12_out[6]), + .I2(p_12_out[7]), + .O(plusOp__2[7])); + LUT6 #( + .INIT(64'h8000000000000000)) + \gcc0.gc0.count[7]_i_2__0 + (.I0(p_12_out[5]), + .I1(p_12_out[3]), + .I2(p_12_out[1]), + .I3(p_12_out[0]), + .I4(p_12_out[2]), + .I5(p_12_out[4]), + .O(\gcc0.gc0.count[7]_i_2__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \gcc0.gc0.count_d1_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(p_12_out[0]), + .Q(Q[0]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gcc0.gc0.count_d1_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(p_12_out[1]), + .Q(Q[1]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gcc0.gc0.count_d1_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(p_12_out[2]), + .Q(Q[2]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gcc0.gc0.count_d1_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(p_12_out[3]), + .Q(Q[3]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gcc0.gc0.count_d1_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(p_12_out[4]), + .Q(Q[4]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gcc0.gc0.count_d1_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(p_12_out[5]), + .Q(Q[5]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gcc0.gc0.count_d1_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(p_12_out[6]), + .Q(Q[6]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gcc0.gc0.count_d1_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(p_12_out[7]), + .Q(Q[7]), + .R(sig_stream_rst)); + FDSE #( + .INIT(1'b1)) + \gcc0.gc0.count_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(plusOp__2[0]), + .Q(p_12_out[0]), + .S(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gcc0.gc0.count_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(plusOp__2[1]), + .Q(p_12_out[1]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gcc0.gc0.count_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(plusOp__2[2]), + .Q(p_12_out[2]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gcc0.gc0.count_reg[3] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(plusOp__2[3]), + .Q(p_12_out[3]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gcc0.gc0.count_reg[4] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(plusOp__2[4]), + .Q(p_12_out[4]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gcc0.gc0.count_reg[5] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(plusOp__2[5]), + .Q(p_12_out[5]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gcc0.gc0.count_reg[6] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(plusOp__2[6]), + .Q(p_12_out[6]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gcc0.gc0.count_reg[7] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(plusOp__2[7]), + .Q(p_12_out[7]), + .R(sig_stream_rst)); + LUT5 #( + .INIT(32'h0FFF0088)) + ram_empty_fb_i_i_1__1 + (.I0(\gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ), + .I1(p_7_out), + .I2(\gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ), + .I3(E), + .I4(ram_empty_fb_i_reg), + .O(ram_empty_i0__3)); + LUT6 #( + .INIT(64'h0000000041000041)) + ram_empty_fb_i_i_2__1 + (.I0(ram_empty_fb_i_i_3__0_n_0), + .I1(Q[6]), + .I2(\gc1.count_d1_reg[7] [6]), + .I3(Q[7]), + .I4(\gc1.count_d1_reg[7] [7]), + .I5(ram_empty_fb_i_i_4__0_n_0), + .O(\gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 )); + LUT4 #( + .INIT(16'h6FF6)) + ram_empty_fb_i_i_3__0 + (.I0(Q[5]), + .I1(\gc1.count_d1_reg[7] [5]), + .I2(Q[4]), + .I3(\gc1.count_d1_reg[7] [4]), + .O(ram_empty_fb_i_i_3__0_n_0)); + LUT5 #( + .INIT(32'hFFFF6FF6)) + ram_empty_fb_i_i_4__0 + (.I0(\gc1.count_d1_reg[7] [2]), + .I1(Q[2]), + .I2(\gc1.count_d1_reg[7] [3]), + .I3(Q[3]), + .I4(ram_empty_fb_i_i_5__0_n_0), + .O(ram_empty_fb_i_i_4__0_n_0)); + LUT4 #( + .INIT(16'h6FF6)) + ram_empty_fb_i_i_5__0 + (.I0(Q[1]), + .I1(\gc1.count_d1_reg[7] [1]), + .I2(Q[0]), + .I3(\gc1.count_d1_reg[7] [0]), + .O(ram_empty_fb_i_i_5__0_n_0)); + LUT6 #( + .INIT(64'h55550000FFFF3000)) + ram_full_fb_i_i_1__1 + (.I0(\gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ), + .I1(out), + .I2(lsig_packer_full), + .I3(\gwss.wsts/comp1 ), + .I4(ram_full_fb_i_reg), + .I5(p_7_out), + .O(ram_full_i_reg)); + LUT6 #( + .INIT(64'h0000000041000041)) + ram_full_fb_i_i_2__0 + (.I0(ram_full_fb_i_i_4__0_n_0), + .I1(Q[6]), + .I2(\gc1.count_d2_reg[7] [6]), + .I3(Q[7]), + .I4(\gc1.count_d2_reg[7] [7]), + .I5(ram_full_fb_i_i_5__0_n_0), + .O(\gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 )); + LUT6 #( + .INIT(64'h0000000041000041)) + ram_full_fb_i_i_3__1 + (.I0(ram_full_fb_i_i_6__0_n_0), + .I1(p_12_out[6]), + .I2(\gc1.count_d2_reg[7] [6]), + .I3(p_12_out[7]), + .I4(\gc1.count_d2_reg[7] [7]), + .I5(ram_full_fb_i_i_7__0_n_0), + .O(\gwss.wsts/comp1 )); + LUT4 #( + .INIT(16'h6FF6)) + ram_full_fb_i_i_4__0 + (.I0(Q[5]), + .I1(\gc1.count_d2_reg[7] [5]), + .I2(Q[4]), + .I3(\gc1.count_d2_reg[7] [4]), + .O(ram_full_fb_i_i_4__0_n_0)); + LUT5 #( + .INIT(32'hFFFF6FF6)) + ram_full_fb_i_i_5__0 + (.I0(\gc1.count_d2_reg[7] [2]), + .I1(Q[2]), + .I2(\gc1.count_d2_reg[7] [3]), + .I3(Q[3]), + .I4(ram_full_fb_i_i_8_n_0), + .O(ram_full_fb_i_i_5__0_n_0)); + LUT4 #( + .INIT(16'h6FF6)) + ram_full_fb_i_i_6__0 + (.I0(p_12_out[5]), + .I1(\gc1.count_d2_reg[7] [5]), + .I2(p_12_out[4]), + .I3(\gc1.count_d2_reg[7] [4]), + .O(ram_full_fb_i_i_6__0_n_0)); + LUT5 #( + .INIT(32'hFFFF6FF6)) + ram_full_fb_i_i_7__0 + (.I0(\gc1.count_d2_reg[7] [2]), + .I1(p_12_out[2]), + .I2(\gc1.count_d2_reg[7] [3]), + .I3(p_12_out[3]), + .I4(ram_full_fb_i_i_9_n_0), + .O(ram_full_fb_i_i_7__0_n_0)); + LUT4 #( + .INIT(16'h6FF6)) + ram_full_fb_i_i_8 + (.I0(Q[1]), + .I1(\gc1.count_d2_reg[7] [1]), + .I2(Q[0]), + .I3(\gc1.count_d2_reg[7] [0]), + .O(ram_full_fb_i_i_8_n_0)); + (* SOFT_HLUTNM = "soft_lutpair172" *) + LUT4 #( + .INIT(16'h6FF6)) + ram_full_fb_i_i_9 + (.I0(p_12_out[1]), + .I1(\gc1.count_d2_reg[7] [1]), + .I2(p_12_out[0]), + .I3(\gc1.count_d2_reg[7] [0]), + .O(ram_full_fb_i_i_9_n_0)); +endmodule + +(* ORIG_REF_NAME = "wr_bin_cntr" *) +module Arty_Z7_20_axi_vdma_0_0_wr_bin_cntr_33 + (Q, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram , + SR, + E, + m_axi_mm2s_aclk); + output [7:0]Q; + output [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; + input [0:0]SR; + input [0:0]E; + input m_axi_mm2s_aclk; + + wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; + wire [0:0]E; + wire [7:0]Q; + wire [0:0]SR; + wire \gcc0.gc0.count[7]_i_2_n_0 ; + wire m_axi_mm2s_aclk; + wire [7:0]plusOp__0; + + LUT1 #( + .INIT(2'h1)) + \gcc0.gc0.count[0]_i_1 + (.I0(Q[0]), + .O(plusOp__0[0])); + (* SOFT_HLUTNM = "soft_lutpair107" *) + LUT2 #( + .INIT(4'h6)) + \gcc0.gc0.count[1]_i_1 + (.I0(Q[0]), + .I1(Q[1]), + .O(plusOp__0[1])); + (* SOFT_HLUTNM = "soft_lutpair107" *) + LUT3 #( + .INIT(8'h6A)) + \gcc0.gc0.count[2]_i_1 + (.I0(Q[2]), + .I1(Q[1]), + .I2(Q[0]), + .O(plusOp__0[2])); + (* SOFT_HLUTNM = "soft_lutpair105" *) + LUT4 #( + .INIT(16'h6AAA)) + \gcc0.gc0.count[3]_i_1 + (.I0(Q[3]), + .I1(Q[0]), + .I2(Q[1]), + .I3(Q[2]), .O(plusOp__0[3])); - (* SOFT_HLUTNM = "soft_lutpair48" *) + (* SOFT_HLUTNM = "soft_lutpair105" *) LUT5 #( - .INIT(32'h7FFF8000)) + .INIT(32'h6AAAAAAA)) \gcc0.gc0.count[4]_i_1 - (.I0(p_12_out[2]), - .I1(p_12_out[0]), - .I2(p_12_out[1]), - .I3(p_12_out[3]), - .I4(p_12_out[4]), + (.I0(Q[4]), + .I1(Q[2]), + .I2(Q[1]), + .I3(Q[0]), + .I4(Q[3]), .O(plusOp__0[4])); LUT6 #( - .INIT(64'h7FFFFFFF80000000)) + .INIT(64'h6AAAAAAAAAAAAAAA)) \gcc0.gc0.count[5]_i_1 - (.I0(p_12_out[3]), - .I1(p_12_out[1]), - .I2(p_12_out[0]), - .I3(p_12_out[2]), - .I4(p_12_out[4]), - .I5(p_12_out[5]), + (.I0(Q[5]), + .I1(Q[3]), + .I2(Q[0]), + .I3(Q[1]), + .I4(Q[2]), + .I5(Q[4]), .O(plusOp__0[5])); - LUT3 #( - .INIT(8'h78)) + (* SOFT_HLUTNM = "soft_lutpair106" *) + LUT2 #( + .INIT(4'h6)) \gcc0.gc0.count[6]_i_1 - (.I0(\gcc0.gc0.count[6]_i_2_n_0 ), - .I1(p_12_out[5]), - .I2(p_12_out[6]), + (.I0(Q[6]), + .I1(\gcc0.gc0.count[7]_i_2_n_0 ), .O(plusOp__0[6])); - (* SOFT_HLUTNM = "soft_lutpair48" *) - LUT5 #( - .INIT(32'h80000000)) - \gcc0.gc0.count[6]_i_2 - (.I0(p_12_out[4]), - .I1(p_12_out[2]), - .I2(p_12_out[0]), - .I3(p_12_out[1]), - .I4(p_12_out[3]), - .O(\gcc0.gc0.count[6]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair106" *) + LUT3 #( + .INIT(8'h6A)) + \gcc0.gc0.count[7]_i_1 + (.I0(Q[7]), + .I1(\gcc0.gc0.count[7]_i_2_n_0 ), + .I2(Q[6]), + .O(plusOp__0[7])); + LUT6 #( + .INIT(64'h8000000000000000)) + \gcc0.gc0.count[7]_i_2 + (.I0(Q[5]), + .I1(Q[3]), + .I2(Q[0]), + .I3(Q[1]), + .I4(Q[2]), + .I5(Q[4]), + .O(\gcc0.gc0.count[7]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gcc0.gc0.count_d1_reg[0] (.C(m_axi_mm2s_aclk), .CE(E), - .D(p_12_out[0]), - .Q(Q[0]), - .R(sig_stream_rst)); + .D(Q[0]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]), + .R(SR)); FDRE #( .INIT(1'b0)) \gcc0.gc0.count_d1_reg[1] (.C(m_axi_mm2s_aclk), .CE(E), - .D(p_12_out[1]), - .Q(Q[1]), - .R(sig_stream_rst)); + .D(Q[1]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]), + .R(SR)); FDRE #( .INIT(1'b0)) \gcc0.gc0.count_d1_reg[2] (.C(m_axi_mm2s_aclk), .CE(E), - .D(p_12_out[2]), - .Q(Q[2]), - .R(sig_stream_rst)); + .D(Q[2]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [2]), + .R(SR)); FDRE #( .INIT(1'b0)) \gcc0.gc0.count_d1_reg[3] (.C(m_axi_mm2s_aclk), .CE(E), - .D(p_12_out[3]), - .Q(Q[3]), - .R(sig_stream_rst)); + .D(Q[3]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [3]), + .R(SR)); FDRE #( .INIT(1'b0)) \gcc0.gc0.count_d1_reg[4] (.C(m_axi_mm2s_aclk), .CE(E), - .D(p_12_out[4]), - .Q(Q[4]), - .R(sig_stream_rst)); + .D(Q[4]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [4]), + .R(SR)); FDRE #( .INIT(1'b0)) \gcc0.gc0.count_d1_reg[5] (.C(m_axi_mm2s_aclk), .CE(E), - .D(p_12_out[5]), - .Q(Q[5]), - .R(sig_stream_rst)); + .D(Q[5]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [5]), + .R(SR)); FDRE #( .INIT(1'b0)) \gcc0.gc0.count_d1_reg[6] (.C(m_axi_mm2s_aclk), .CE(E), - .D(p_12_out[6]), - .Q(Q[6]), - .R(sig_stream_rst)); + .D(Q[6]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [6]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \gcc0.gc0.count_d1_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(Q[7]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [7]), + .R(SR)); FDSE #( .INIT(1'b1)) \gcc0.gc0.count_reg[0] (.C(m_axi_mm2s_aclk), .CE(E), .D(plusOp__0[0]), - .Q(p_12_out[0]), - .S(sig_stream_rst)); + .Q(Q[0]), + .S(SR)); FDRE #( .INIT(1'b0)) \gcc0.gc0.count_reg[1] (.C(m_axi_mm2s_aclk), .CE(E), .D(plusOp__0[1]), - .Q(p_12_out[1]), - .R(sig_stream_rst)); + .Q(Q[1]), + .R(SR)); FDRE #( .INIT(1'b0)) \gcc0.gc0.count_reg[2] (.C(m_axi_mm2s_aclk), .CE(E), .D(plusOp__0[2]), - .Q(p_12_out[2]), - .R(sig_stream_rst)); + .Q(Q[2]), + .R(SR)); FDRE #( .INIT(1'b0)) \gcc0.gc0.count_reg[3] (.C(m_axi_mm2s_aclk), .CE(E), .D(plusOp__0[3]), - .Q(p_12_out[3]), - .R(sig_stream_rst)); + .Q(Q[3]), + .R(SR)); FDRE #( .INIT(1'b0)) \gcc0.gc0.count_reg[4] (.C(m_axi_mm2s_aclk), .CE(E), .D(plusOp__0[4]), - .Q(p_12_out[4]), - .R(sig_stream_rst)); + .Q(Q[4]), + .R(SR)); FDRE #( .INIT(1'b0)) \gcc0.gc0.count_reg[5] (.C(m_axi_mm2s_aclk), .CE(E), .D(plusOp__0[5]), - .Q(p_12_out[5]), - .R(sig_stream_rst)); + .Q(Q[5]), + .R(SR)); FDRE #( .INIT(1'b0)) \gcc0.gc0.count_reg[6] (.C(m_axi_mm2s_aclk), .CE(E), .D(plusOp__0[6]), - .Q(p_12_out[6]), + .Q(Q[6]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \gcc0.gc0.count_reg[7] + (.C(m_axi_mm2s_aclk), + .CE(E), + .D(plusOp__0[7]), + .Q(Q[7]), + .R(SR)); +endmodule + +(* ORIG_REF_NAME = "wr_bin_cntr" *) +module Arty_Z7_20_axi_vdma_0_0_wr_bin_cntr__parameterized0 + (ram_full_i_reg, + ram_empty_i0__3, + \gpr1.dout_i_reg[1] , + sig_clr_dbc_reg_reg, + out, + \gv.ram_valid_d1_reg , + ram_empty_fb_i_reg, + \gc1.count_d2_reg[2] , + Q, + sig_stream_rst, + E, + m_axi_s2mm_aclk); + output ram_full_i_reg; + output ram_empty_i0__3; + output [2:0]\gpr1.dout_i_reg[1] ; + input sig_clr_dbc_reg_reg; + input out; + input \gv.ram_valid_d1_reg ; + input ram_empty_fb_i_reg; + input [2:0]\gc1.count_d2_reg[2] ; + input [2:0]Q; + input sig_stream_rst; + input [0:0]E; + input m_axi_s2mm_aclk; + + wire [0:0]E; + wire [2:0]Q; + wire [2:0]\gc1.count_d2_reg[2] ; + wire \gcc0.gc0.count[0]_i_1__1_n_0 ; + wire \gcc0.gc0.count[1]_i_1__1_n_0 ; + wire \gcc0.gc0.count[2]_i_2_n_0 ; + wire \gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ; + wire \gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ; + wire [2:0]\gpr1.dout_i_reg[1] ; + wire \gv.ram_valid_d1_reg ; + wire \gwss.wsts/comp1 ; + wire m_axi_s2mm_aclk; + wire out; + wire [2:0]p_12_out; + wire ram_empty_fb_i_reg; + wire ram_empty_i0__3; + wire ram_full_i_reg; + wire sig_clr_dbc_reg_reg; + wire sig_stream_rst; + + LUT1 #( + .INIT(2'h1)) + \gcc0.gc0.count[0]_i_1__1 + (.I0(p_12_out[0]), + .O(\gcc0.gc0.count[0]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair177" *) + LUT2 #( + .INIT(4'h6)) + \gcc0.gc0.count[1]_i_1__1 + (.I0(p_12_out[0]), + .I1(p_12_out[1]), + .O(\gcc0.gc0.count[1]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair177" *) + LUT3 #( + .INIT(8'h78)) + \gcc0.gc0.count[2]_i_2 + (.I0(p_12_out[0]), + .I1(p_12_out[1]), + .I2(p_12_out[2]), + .O(\gcc0.gc0.count[2]_i_2_n_0 )); + FDRE #( + .INIT(1'b0)) + \gcc0.gc0.count_d1_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(p_12_out[0]), + .Q(\gpr1.dout_i_reg[1] [0]), .R(sig_stream_rst)); - LUT5 #( - .INIT(32'h0FFF0088)) - ram_empty_fb_i_i_1 + FDRE #( + .INIT(1'b0)) + \gcc0.gc0.count_d1_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(p_12_out[1]), + .Q(\gpr1.dout_i_reg[1] [1]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gcc0.gc0.count_d1_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(p_12_out[2]), + .Q(\gpr1.dout_i_reg[1] [2]), + .R(sig_stream_rst)); + FDSE #( + .INIT(1'b1)) + \gcc0.gc0.count_reg[0] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(\gcc0.gc0.count[0]_i_1__1_n_0 ), + .Q(p_12_out[0]), + .S(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gcc0.gc0.count_reg[1] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(\gcc0.gc0.count[1]_i_1__1_n_0 ), + .Q(p_12_out[1]), + .R(sig_stream_rst)); + FDRE #( + .INIT(1'b0)) + \gcc0.gc0.count_reg[2] + (.C(m_axi_s2mm_aclk), + .CE(E), + .D(\gcc0.gc0.count[2]_i_2_n_0 ), + .Q(p_12_out[2]), + .R(sig_stream_rst)); + LUT6 #( + .INIT(64'hFF0FFFFF88008888)) + ram_empty_fb_i_i_1__0 (.I0(\gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ), - .I1(p_7_out), - .I2(\gwss.wsts/comp0 ), - .I3(E), - .I4(ram_empty_fb_i_reg), + .I1(\gv.ram_valid_d1_reg ), + .I2(\gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ), + .I3(out), + .I4(sig_clr_dbc_reg_reg), + .I5(ram_empty_fb_i_reg), .O(ram_empty_i0__3)); LUT6 #( - .INIT(64'h1001000000001001)) - ram_empty_fb_i_i_2 - (.I0(ram_empty_fb_i_i_3_n_0), - .I1(ram_empty_fb_i_i_4_n_0), - .I2(Q[3]), - .I3(\gc1.count_d1_reg[6] [3]), + .INIT(64'h9009000000009009)) + ram_empty_fb_i_i_2__0 + (.I0(\gpr1.dout_i_reg[1] [1]), + .I1(Q[1]), + .I2(Q[0]), + .I3(\gpr1.dout_i_reg[1] [0]), .I4(Q[2]), - .I5(\gc1.count_d1_reg[6] [2]), + .I5(\gpr1.dout_i_reg[1] [2]), .O(\gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 )); - LUT6 #( - .INIT(64'h6FF6FFFFFFFF6FF6)) - ram_empty_fb_i_i_3 - (.I0(Q[5]), - .I1(\gc1.count_d1_reg[6] [5]), - .I2(\gc1.count_d1_reg[6] [4]), - .I3(Q[4]), - .I4(\gc1.count_d1_reg[6] [6]), - .I5(Q[6]), - .O(ram_empty_fb_i_i_3_n_0)); - LUT4 #( - .INIT(16'h6FF6)) - ram_empty_fb_i_i_4 - (.I0(Q[1]), - .I1(\gc1.count_d1_reg[6] [1]), - .I2(Q[0]), - .I3(\gc1.count_d1_reg[6] [0]), - .O(ram_empty_fb_i_i_4_n_0)); LUT5 #( .INIT(32'h5500FFC0)) - ram_full_fb_i_i_1 - (.I0(\gwss.wsts/comp0 ), - .I1(E), + ram_full_fb_i_i_1__0 + (.I0(\gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ), + .I1(sig_clr_dbc_reg_reg), .I2(\gwss.wsts/comp1 ), .I3(out), - .I4(p_7_out), + .I4(\gv.ram_valid_d1_reg ), .O(ram_full_i_reg)); LUT6 #( - .INIT(64'h1001000000001001)) - ram_full_fb_i_i_2 - (.I0(ram_full_fb_i_i_4_n_0), - .I1(ram_full_fb_i_i_5_n_0), - .I2(Q[3]), - .I3(\gc1.count_d2_reg[6] [3]), - .I4(Q[2]), - .I5(\gc1.count_d2_reg[6] [2]), - .O(\gwss.wsts/comp0 )); - LUT6 #( - .INIT(64'h1001000000001001)) - ram_full_fb_i_i_3 - (.I0(ram_full_fb_i_i_6_n_0), - .I1(ram_full_fb_i_i_7_n_0), - .I2(p_12_out[3]), - .I3(\gc1.count_d2_reg[6] [3]), - .I4(p_12_out[2]), - .I5(\gc1.count_d2_reg[6] [2]), - .O(\gwss.wsts/comp1 )); - LUT6 #( - .INIT(64'h6FF6FFFFFFFF6FF6)) - ram_full_fb_i_i_4 - (.I0(Q[5]), - .I1(\gc1.count_d2_reg[6] [5]), - .I2(\gc1.count_d2_reg[6] [4]), - .I3(Q[4]), - .I4(\gc1.count_d2_reg[6] [6]), - .I5(Q[6]), - .O(ram_full_fb_i_i_4_n_0)); - LUT4 #( - .INIT(16'h6FF6)) - ram_full_fb_i_i_5 - (.I0(Q[1]), - .I1(\gc1.count_d2_reg[6] [1]), - .I2(Q[0]), - .I3(\gc1.count_d2_reg[6] [0]), - .O(ram_full_fb_i_i_5_n_0)); + .INIT(64'h9009000000009009)) + ram_full_fb_i_i_2__1 + (.I0(\gpr1.dout_i_reg[1] [1]), + .I1(\gc1.count_d2_reg[2] [1]), + .I2(\gc1.count_d2_reg[2] [0]), + .I3(\gpr1.dout_i_reg[1] [0]), + .I4(\gc1.count_d2_reg[2] [2]), + .I5(\gpr1.dout_i_reg[1] [2]), + .O(\gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 )); LUT6 #( - .INIT(64'h6FF6FFFFFFFF6FF6)) - ram_full_fb_i_i_6 - (.I0(p_12_out[5]), - .I1(\gc1.count_d2_reg[6] [5]), - .I2(\gc1.count_d2_reg[6] [4]), - .I3(p_12_out[4]), - .I4(\gc1.count_d2_reg[6] [6]), - .I5(p_12_out[6]), - .O(ram_full_fb_i_i_6_n_0)); - (* SOFT_HLUTNM = "soft_lutpair49" *) - LUT4 #( - .INIT(16'h6FF6)) - ram_full_fb_i_i_7 + .INIT(64'h9009000000009009)) + ram_full_fb_i_i_3__0 (.I0(p_12_out[1]), - .I1(\gc1.count_d2_reg[6] [1]), - .I2(p_12_out[0]), - .I3(\gc1.count_d2_reg[6] [0]), - .O(ram_full_fb_i_i_7_n_0)); + .I1(\gc1.count_d2_reg[2] [1]), + .I2(\gc1.count_d2_reg[2] [0]), + .I3(p_12_out[0]), + .I4(\gc1.count_d2_reg[2] [2]), + .I5(p_12_out[2]), + .O(\gwss.wsts/comp1 )); endmodule (* ORIG_REF_NAME = "wr_logic" *) module Arty_Z7_20_axi_vdma_0_0_wr_logic (out, + \INCLUDE_PACKING.lsig_packer_full_reg , + WEBWE, + E, + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] , + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] , + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] , + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] , + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] , + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] , + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] , ram_empty_i0__3, - \gcc0.gc0.count_d1_reg[6] , Q, sig_stream_rst, - m_axi_mm2s_aclk, + m_axi_s2mm_aclk, + lsig_set_packer_full__1, + lsig_packer_full, p_7_out, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 , ram_empty_fb_i_reg, - \gc1.count_d2_reg[6] , - \gc1.count_d1_reg[6] , - mm2s_strm_wvalid0__1, - m_axi_mm2s_rvalid, - sig_advance_pipe9_out__1); + \gc1.count_d2_reg[7] , + \gc1.count_d1_reg[7] ); output out; + output \INCLUDE_PACKING.lsig_packer_full_reg ; + output [0:0]WEBWE; + output [0:0]E; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] ; output ram_empty_i0__3; - output \gcc0.gc0.count_d1_reg[6] ; - output [6:0]Q; + output [7:0]Q; input sig_stream_rst; - input m_axi_mm2s_aclk; + input m_axi_s2mm_aclk; + input lsig_set_packer_full__1; + input lsig_packer_full; input p_7_out; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ; input ram_empty_fb_i_reg; - input [6:0]\gc1.count_d2_reg[6] ; - input [6:0]\gc1.count_d1_reg[6] ; - input mm2s_strm_wvalid0__1; - input m_axi_mm2s_rvalid; - input sig_advance_pipe9_out__1; + input [7:0]\gc1.count_d2_reg[7] ; + input [7:0]\gc1.count_d1_reg[7] ; - wire [6:0]Q; - wire [6:0]\gc1.count_d1_reg[6] ; - wire [6:0]\gc1.count_d2_reg[6] ; - wire \gcc0.gc0.count_d1_reg[6] ; + wire [0:0]E; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ; + wire \INCLUDE_PACKING.lsig_packer_full_reg ; + wire [7:0]Q; + wire [0:0]WEBWE; + wire [7:0]\gc1.count_d1_reg[7] ; + wire [7:0]\gc1.count_d2_reg[7] ; wire \gwss.wsts_n_0 ; - wire m_axi_mm2s_aclk; - wire m_axi_mm2s_rvalid; - wire mm2s_strm_wvalid0__1; + wire lsig_packer_full; + wire lsig_set_packer_full__1; + wire m_axi_s2mm_aclk; wire out; wire p_7_out; wire ram_empty_fb_i_reg; wire ram_empty_i0__3; - wire sig_advance_pipe9_out__1; wire sig_stream_rst; - wire wpntr_n_8; + wire wpntr_n_0; Arty_Z7_20_axi_vdma_0_0_wr_status_flags_ss \gwss.wsts - (.E(\gcc0.gc0.count_d1_reg[6] ), - .\gcc0.gc0.count_d1_reg[6] (out), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .m_axi_mm2s_rvalid(m_axi_mm2s_rvalid), - .mm2s_strm_wvalid0__1(mm2s_strm_wvalid0__1), + (.E(WEBWE), + .\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] (\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] (\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] (\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] (\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] (\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] (\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] (\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] ), + .\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][0] (E), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] ), + .\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 (\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ), + .\INCLUDE_PACKING.lsig_packer_full_reg (\INCLUDE_PACKING.lsig_packer_full_reg ), + .\gcc0.gc0.count_d1_reg[7] (out), + .lsig_packer_full(lsig_packer_full), + .lsig_set_packer_full__1(lsig_set_packer_full__1), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), .out(\gwss.wsts_n_0 ), - .ram_full_fb_i_reg_0(wpntr_n_8), - .sig_advance_pipe9_out__1(sig_advance_pipe9_out__1), + .ram_full_i_reg_0(wpntr_n_0), .sig_stream_rst(sig_stream_rst)); Arty_Z7_20_axi_vdma_0_0_wr_bin_cntr wpntr - (.E(\gcc0.gc0.count_d1_reg[6] ), + (.E(WEBWE), .Q(Q), - .\gc1.count_d1_reg[6] (\gc1.count_d1_reg[6] ), - .\gc1.count_d2_reg[6] (\gc1.count_d2_reg[6] ), - .m_axi_mm2s_aclk(m_axi_mm2s_aclk), - .out(\gwss.wsts_n_0 ), + .\gc1.count_d1_reg[7] (\gc1.count_d1_reg[7] ), + .\gc1.count_d2_reg[7] (\gc1.count_d2_reg[7] ), + .lsig_packer_full(lsig_packer_full), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out), .p_7_out(p_7_out), .ram_empty_fb_i_reg(ram_empty_fb_i_reg), .ram_empty_i0__3(ram_empty_i0__3), - .ram_full_i_reg(wpntr_n_8), + .ram_full_fb_i_reg(\gwss.wsts_n_0 ), + .ram_full_i_reg(wpntr_n_0), + .sig_stream_rst(sig_stream_rst)); +endmodule + +(* ORIG_REF_NAME = "wr_logic" *) +module Arty_Z7_20_axi_vdma_0_0_wr_logic_31 + (out, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram , + sig_ok_to_post_rd_addr_reg, + Q, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0 , + sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0, + m_axi_mm2s_aclk, + sig_posted_to_axi_2_reg, + \sig_token_cntr_reg[3] , + SR, + E); + output out; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; + output sig_ok_to_post_rd_addr_reg; + output [7:0]Q; + output [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0 ; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0; + input m_axi_mm2s_aclk; + input sig_posted_to_axi_2_reg; + input [3:0]\sig_token_cntr_reg[3] ; + input [0:0]SR; + input [0:0]E; + + wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; + wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0 ; + wire [0:0]E; + wire [7:0]Q; + wire [0:0]SR; + wire m_axi_mm2s_aclk; + wire out; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0; + wire sig_ok_to_post_rd_addr_reg; + wire sig_posted_to_axi_2_reg; + wire [3:0]\sig_token_cntr_reg[3] ; + + Arty_Z7_20_axi_vdma_0_0_wr_status_flags_ss_32 \gwss.wsts + (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk), + .out(out), + .sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0(sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0), + .sig_ok_to_post_rd_addr_reg(sig_ok_to_post_rd_addr_reg), + .sig_posted_to_axi_2_reg(sig_posted_to_axi_2_reg), + .\sig_token_cntr_reg[3] (\sig_token_cntr_reg[3] )); + Arty_Z7_20_axi_vdma_0_0_wr_bin_cntr_33 wpntr + (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0 ), + .E(E), + .Q(Q), + .SR(SR), + .m_axi_mm2s_aclk(m_axi_mm2s_aclk)); +endmodule + +(* ORIG_REF_NAME = "wr_logic" *) +module Arty_Z7_20_axi_vdma_0_0_wr_logic__parameterized0 + (out, + \sig_byte_cntr_reg[0] , + E, + ram_empty_i0__3, + \gpr1.dout_i_reg[1] , + sig_stream_rst, + m_axi_s2mm_aclk, + sig_clr_dbc_reg_reg, + \gv.ram_valid_d1_reg , + ram_empty_fb_i_reg, + \gc1.count_d2_reg[2] , + Q); + output out; + output \sig_byte_cntr_reg[0] ; + output [0:0]E; + output ram_empty_i0__3; + output [2:0]\gpr1.dout_i_reg[1] ; + input sig_stream_rst; + input m_axi_s2mm_aclk; + input sig_clr_dbc_reg_reg; + input \gv.ram_valid_d1_reg ; + input ram_empty_fb_i_reg; + input [2:0]\gc1.count_d2_reg[2] ; + input [2:0]Q; + + wire [0:0]E; + wire [2:0]Q; + wire [2:0]\gc1.count_d2_reg[2] ; + wire [2:0]\gpr1.dout_i_reg[1] ; + wire \gv.ram_valid_d1_reg ; + wire m_axi_s2mm_aclk; + wire out; + wire ram_empty_fb_i_reg; + wire ram_empty_i0__3; + wire \sig_byte_cntr_reg[0] ; + wire sig_clr_dbc_reg_reg; + wire sig_stream_rst; + wire wpntr_n_0; + + Arty_Z7_20_axi_vdma_0_0_wr_status_flags_ss__parameterized0 \gwss.wsts + (.E(E), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out), + .\sig_byte_cntr_reg[0] (\sig_byte_cntr_reg[0] ), + .sig_clr_dbc_reg_reg(wpntr_n_0), + .sig_clr_dbc_reg_reg_0(sig_clr_dbc_reg_reg), + .sig_stream_rst(sig_stream_rst)); + Arty_Z7_20_axi_vdma_0_0_wr_bin_cntr__parameterized0 wpntr + (.E(E), + .Q(Q), + .\gc1.count_d2_reg[2] (\gc1.count_d2_reg[2] ), + .\gpr1.dout_i_reg[1] (\gpr1.dout_i_reg[1] ), + .\gv.ram_valid_d1_reg (\gv.ram_valid_d1_reg ), + .m_axi_s2mm_aclk(m_axi_s2mm_aclk), + .out(out), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_empty_i0__3(ram_empty_i0__3), + .ram_full_i_reg(wpntr_n_0), + .sig_clr_dbc_reg_reg(sig_clr_dbc_reg_reg), .sig_stream_rst(sig_stream_rst)); endmodule (* ORIG_REF_NAME = "wr_status_flags_ss" *) module Arty_Z7_20_axi_vdma_0_0_wr_status_flags_ss (out, - \gcc0.gc0.count_d1_reg[6] , + \gcc0.gc0.count_d1_reg[7] , + \INCLUDE_PACKING.lsig_packer_full_reg , E, + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][0] , + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] , + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] , + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] , + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] , + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] , + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] , + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] , sig_stream_rst, - ram_full_fb_i_reg_0, - m_axi_mm2s_aclk, - mm2s_strm_wvalid0__1, - m_axi_mm2s_rvalid, - sig_advance_pipe9_out__1); + ram_full_i_reg_0, + m_axi_s2mm_aclk, + lsig_set_packer_full__1, + lsig_packer_full, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 , + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ); output out; - output \gcc0.gc0.count_d1_reg[6] ; + output \gcc0.gc0.count_d1_reg[7] ; + output \INCLUDE_PACKING.lsig_packer_full_reg ; output [0:0]E; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] ; + output [0:0]\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] ; input sig_stream_rst; - input ram_full_fb_i_reg_0; - input m_axi_mm2s_aclk; - input mm2s_strm_wvalid0__1; - input m_axi_mm2s_rvalid; - input sig_advance_pipe9_out__1; + input ram_full_i_reg_0; + input m_axi_s2mm_aclk; + input lsig_set_packer_full__1; + input lsig_packer_full; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 ; + input \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ; wire [0:0]E; - wire m_axi_mm2s_aclk; - wire m_axi_mm2s_rvalid; - wire mm2s_strm_wvalid0__1; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] ; + wire [0:0]\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][0] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] ; + wire \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ; + wire \INCLUDE_PACKING.lsig_packer_full_reg ; + wire lsig_packer_full; + wire lsig_set_packer_full__1; + wire m_axi_s2mm_aclk; (* DONT_TOUCH *) wire ram_afull_fb; (* DONT_TOUCH *) wire ram_afull_i; (* DONT_TOUCH *) wire ram_full_fb_i; - wire ram_full_fb_i_reg_0; (* DONT_TOUCH *) wire ram_full_i; - wire sig_advance_pipe9_out__1; + wire ram_full_i_reg_0; wire sig_stream_rst; - assign \gcc0.gc0.count_d1_reg[6] = ram_full_i; + assign \gcc0.gc0.count_d1_reg[7] = ram_full_i; assign out = ram_full_fb_i; - LUT5 #( - .INIT(32'h00005444)) - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_2 + LUT3 #( + .INIT(8'h04)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_2__0 (.I0(ram_full_i), - .I1(mm2s_strm_wvalid0__1), - .I2(m_axi_mm2s_rvalid), - .I3(sig_advance_pipe9_out__1), - .I4(ram_full_fb_i), + .I1(lsig_packer_full), + .I2(ram_full_fb_i), .O(E)); + LUT3 #( + .INIT(8'hBA)) + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg[0][1]_i_1 + (.I0(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4 ), + .I1(ram_full_i), + .I2(lsig_packer_full), + .O(\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0] )); + LUT3 #( + .INIT(8'hBA)) + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg[1][1]_i_1 + (.I0(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3 ), + .I1(ram_full_i), + .I2(lsig_packer_full), + .O(\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0] )); + LUT3 #( + .INIT(8'hBA)) + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg[2][1]_i_1 + (.I0(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2 ), + .I1(ram_full_i), + .I2(lsig_packer_full), + .O(\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0] )); + LUT3 #( + .INIT(8'hBA)) + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg[3][1]_i_1 + (.I0(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1 ), + .I1(ram_full_i), + .I2(lsig_packer_full), + .O(\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0] )); + LUT3 #( + .INIT(8'hBA)) + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg[4][1]_i_1 + (.I0(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0 ), + .I1(ram_full_i), + .I2(lsig_packer_full), + .O(\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0] )); + LUT3 #( + .INIT(8'hBA)) + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg[5][1]_i_1 + (.I0(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2] ), + .I1(ram_full_i), + .I2(lsig_packer_full), + .O(\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0] )); + LUT3 #( + .INIT(8'hBA)) + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg[6][1]_i_1 + (.I0(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0 ), + .I1(ram_full_i), + .I2(lsig_packer_full), + .O(\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0] )); + LUT3 #( + .INIT(8'hBA)) + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg[7][1]_i_1 + (.I0(\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1] ), + .I1(ram_full_i), + .I2(lsig_packer_full), + .O(\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][0] )); + LUT3 #( + .INIT(8'hEA)) + \INCLUDE_PACKING.lsig_packer_full_i_1 + (.I0(lsig_set_packer_full__1), + .I1(lsig_packer_full), + .I2(ram_full_i), + .O(\INCLUDE_PACKING.lsig_packer_full_reg )); LUT1 #( .INIT(2'h2)) i_0 @@ -33514,20 +83090,162 @@ module Arty_Z7_20_axi_vdma_0_0_wr_status_flags_ss FDRE #( .INIT(1'b0)) ram_full_fb_i_reg - (.C(m_axi_mm2s_aclk), + (.C(m_axi_s2mm_aclk), .CE(1'b1), - .D(ram_full_fb_i_reg_0), + .D(ram_full_i_reg_0), .Q(ram_full_fb_i), .R(sig_stream_rst)); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + ram_full_i_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(ram_full_i_reg_0), + .Q(ram_full_i), + .R(sig_stream_rst)); +endmodule + +(* ORIG_REF_NAME = "wr_status_flags_ss" *) +module Arty_Z7_20_axi_vdma_0_0_wr_status_flags_ss_32 + (out, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram , + sig_ok_to_post_rd_addr_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0, + m_axi_mm2s_aclk, + sig_posted_to_axi_2_reg, + \sig_token_cntr_reg[3] ); + output out; + output \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; + output sig_ok_to_post_rd_addr_reg; + input sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0; + input m_axi_mm2s_aclk; + input sig_posted_to_axi_2_reg; + input [3:0]\sig_token_cntr_reg[3] ; + + wire m_axi_mm2s_aclk; + (* DONT_TOUCH *) wire ram_afull_fb; + (* DONT_TOUCH *) wire ram_afull_i; + (* DONT_TOUCH *) wire ram_full_fb_i; + (* DONT_TOUCH *) wire ram_full_i; + wire sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0; + wire sig_ok_to_post_rd_addr_reg; + wire sig_posted_to_axi_2_reg; + wire [3:0]\sig_token_cntr_reg[3] ; + + assign \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram = ram_full_i; + assign out = ram_full_fb_i; + LUT1 #( + .INIT(2'h2)) + i_0 + (.I0(1'b0), + .O(ram_afull_i)); + LUT1 #( + .INIT(2'h2)) + i_1 + (.I0(1'b0), + .O(ram_afull_fb)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + ram_full_fb_i_reg + (.C(m_axi_mm2s_aclk), + .CE(1'b1), + .D(sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0), + .Q(ram_full_fb_i), + .R(1'b0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) ram_full_i_reg (.C(m_axi_mm2s_aclk), .CE(1'b1), - .D(ram_full_fb_i_reg_0), + .D(sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0), + .Q(ram_full_i), + .R(1'b0)); + LUT6 #( + .INIT(64'hFFFFFFFF00000023)) + sig_ok_to_post_rd_addr_i_5 + (.I0(sig_posted_to_axi_2_reg), + .I1(\sig_token_cntr_reg[3] [1]), + .I2(\sig_token_cntr_reg[3] [0]), + .I3(\sig_token_cntr_reg[3] [3]), + .I4(\sig_token_cntr_reg[3] [2]), + .I5(ram_full_i), + .O(sig_ok_to_post_rd_addr_reg)); +endmodule + +(* ORIG_REF_NAME = "wr_status_flags_ss" *) +module Arty_Z7_20_axi_vdma_0_0_wr_status_flags_ss__parameterized0 + (out, + \sig_byte_cntr_reg[0] , + E, + sig_stream_rst, + sig_clr_dbc_reg_reg, + m_axi_s2mm_aclk, + sig_clr_dbc_reg_reg_0); + output out; + output \sig_byte_cntr_reg[0] ; + output [0:0]E; + input sig_stream_rst; + input sig_clr_dbc_reg_reg; + input m_axi_s2mm_aclk; + input sig_clr_dbc_reg_reg_0; + + wire [0:0]E; + wire m_axi_s2mm_aclk; + (* DONT_TOUCH *) wire ram_afull_fb; + (* DONT_TOUCH *) wire ram_afull_i; + (* DONT_TOUCH *) wire ram_full_fb_i; + (* DONT_TOUCH *) wire ram_full_i; + wire sig_clr_dbc_reg_reg; + wire sig_clr_dbc_reg_reg_0; + wire sig_stream_rst; + + assign out = ram_full_fb_i; + assign \sig_byte_cntr_reg[0] = ram_full_i; + LUT2 #( + .INIT(4'h2)) + \gcc0.gc0.count[2]_i_1__1 + (.I0(sig_clr_dbc_reg_reg_0), + .I1(ram_full_fb_i), + .O(E)); + LUT1 #( + .INIT(2'h2)) + i_0 + (.I0(1'b0), + .O(ram_afull_i)); + LUT1 #( + .INIT(2'h2)) + i_1 + (.I0(1'b0), + .O(ram_afull_fb)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + ram_full_fb_i_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_clr_dbc_reg_reg), + .Q(ram_full_fb_i), + .R(sig_stream_rst)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + ram_full_i_reg + (.C(m_axi_s2mm_aclk), + .CE(1'b1), + .D(sig_clr_dbc_reg_reg), .Q(ram_full_i), .R(sig_stream_rst)); endmodule diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_sim_netlist.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_sim_netlist.vhdl index 951b30a..1fecafb 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_sim_netlist.vhdl +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 --- Date : Fri Feb 24 16:08:17 2017 +-- Date : Mon Mar 06 11:51:46 2017 -- Host : WK73 running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim --- c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_sim_netlist.vhdl +-- C:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_sim_netlist.vhdl -- Design : Arty_Z7_20_axi_vdma_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. @@ -14,36677 +14,91235 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_pcc is +entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_ibttcc is port ( - sig_init_reg : out STD_LOGIC; - \in\ : out STD_LOGIC_VECTOR ( 37 downto 0 ); - sig_sm_halt_reg : out STD_LOGIC; + p_10_out : out STD_LOGIC; + p_32_out : out STD_LOGIC; + sig_psm_pop_input_cmd : out STD_LOGIC; + sig_csm_pop_child_cmd : out STD_LOGIC; + p_9_out_0 : out STD_LOGIC; + sig_psm_halt : out STD_LOGIC; sig_input_reg_empty : out STD_LOGIC; - sig_mstr2sf_cmd_valid : out STD_LOGIC; - sig_mstr2data_cmd_valid : out STD_LOGIC; - sig_mstr2addr_cmd_valid : out STD_LOGIC; - sig_calc_error_pushed : out STD_LOGIC; - sig_next_cmd_cmplt_reg_reg : out STD_LOGIC_VECTOR ( 2 downto 0 ); - sig_init_done_reg : out STD_LOGIC; - sig_init_done_reg_0 : out STD_LOGIC; - sig_init_done_reg_1 : out STD_LOGIC; - sig_init_done_reg_2 : out STD_LOGIC; - FIFO_Full_reg : out STD_LOGIC; + \in\ : out STD_LOGIC_VECTOR ( 39 downto 0 ); + sig_next_cmd_cmplt_reg_reg : out STD_LOGIC_VECTOR ( 1 downto 0 ); + sig_child_qual_error_reg : out STD_LOGIC; + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\ : out STD_LOGIC_VECTOR ( 21 downto 0 ); + sig_child_qual_first_of_2 : out STD_LOGIC; + \sig_xfer_addr_reg_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_adjusted_addr_incr : out STD_LOGIC_VECTOR ( 8 downto 0 ); + p_22_out : out STD_LOGIC; + p_11_out : out STD_LOGIC; + \sig_child_addr_cntr_lsh_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \sig_child_addr_cntr_lsh_reg[7]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + sig_init_reg : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; + sig_input_cache_type_reg0 : in STD_LOGIC; \out\ : in STD_LOGIC_VECTOR ( 49 downto 0 ); - \INFERRED_GEN.cnt_i_reg[2]\ : in STD_LOGIC; + sig_xfer_cmd_cmplt_reg0 : in STD_LOGIC; + \gpr1.dout_i_reg[10]\ : in STD_LOGIC; + sig_psm_halt_reg_0 : in STD_LOGIC; + O : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \gpr1.dout_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \gpr1.dout_i_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); + S : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \gpr1.dout_i_reg[7]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \gpr1.dout_i_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 0 to 0 ); - sig_wr_fifo : in STD_LOGIC; - sig_wr_fifo_0 : in STD_LOGIC; - sig_wr_fifo_1 : in STD_LOGIC; - FIFO_Full_reg_0 : in STD_LOGIC; + sig_csm_state_ns1 : in STD_LOGIC; + sig_sf2pcc_xfer_valid : in STD_LOGIC; + \sig_clr_cmd2addr_valid3_out__0\ : in STD_LOGIC; + \sig_clr_cmd2data_valid4_out__0\ : in STD_LOGIC; sig_inhibit_rdy_n : in STD_LOGIC; - sig_init_reg2 : in STD_LOGIC; - sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; - sig_init_done : in STD_LOGIC; - sig_init_done_2 : in STD_LOGIC; - sig_init_done_3 : in STD_LOGIC; - sig_init_done_4 : in STD_LOGIC + FIFO_Full_reg : in STD_LOGIC; + CO : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gpr1.dout_i_reg[8]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + FIFO_Full_reg_0 : in STD_LOGIC; + sig_inhibit_rdy_n_0 : in STD_LOGIC; + FIFO_Full_reg_1 : in STD_LOGIC; + sig_inhibit_rdy_n_1 : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 2 downto 0 ) ); attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_pcc : entity is "axi_datamover_pcc"; -end Arty_Z7_20_axi_vdma_0_0_axi_datamover_pcc; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_ibttcc : entity is "axi_datamover_ibttcc"; +end Arty_Z7_20_axi_vdma_0_0_axi_datamover_ibttcc; -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_pcc is - signal \FSM_sequential_sig_pcc_sm_state[0]_i_1_n_0\ : STD_LOGIC; - signal \FSM_sequential_sig_pcc_sm_state[0]_i_2_n_0\ : STD_LOGIC; - signal \FSM_sequential_sig_pcc_sm_state[1]_i_1_n_0\ : STD_LOGIC; - signal \FSM_sequential_sig_pcc_sm_state[1]_i_2_n_0\ : STD_LOGIC; - signal \FSM_sequential_sig_pcc_sm_state[2]_i_1_n_0\ : STD_LOGIC; - signal \^in\ : STD_LOGIC_VECTOR ( 37 downto 0 ); - signal p_1_in : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal p_1_in_0 : STD_LOGIC; - signal sel0 : STD_LOGIC_VECTOR ( 8 downto 0 ); - signal sig_addr_aligned_im0 : STD_LOGIC; - signal sig_addr_aligned_ireg1 : STD_LOGIC; - signal \sig_addr_cntr_im0_msh[0]_i_1_n_0\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh[0]_i_3_n_0\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh[0]_i_4_n_0\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh[0]_i_5_n_0\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh[0]_i_6_n_0\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh[0]_i_7_n_0\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh[12]_i_2_n_0\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh[12]_i_3_n_0\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh[12]_i_4_n_0\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh[12]_i_5_n_0\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh[4]_i_2_n_0\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh[4]_i_3_n_0\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh[4]_i_4_n_0\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh[4]_i_5_n_0\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh[8]_i_2_n_0\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh[8]_i_3_n_0\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh[8]_i_4_n_0\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh[8]_i_5_n_0\ : STD_LOGIC; - signal sig_addr_cntr_im0_msh_reg : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal \sig_addr_cntr_im0_msh_reg[0]_i_2_n_0\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh_reg[0]_i_2_n_1\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh_reg[0]_i_2_n_2\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh_reg[0]_i_2_n_3\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh_reg[0]_i_2_n_4\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh_reg[0]_i_2_n_5\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh_reg[0]_i_2_n_6\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh_reg[0]_i_2_n_7\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh_reg[12]_i_1_n_1\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh_reg[12]_i_1_n_2\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh_reg[12]_i_1_n_3\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh_reg[12]_i_1_n_4\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh_reg[12]_i_1_n_5\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh_reg[12]_i_1_n_6\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh_reg[12]_i_1_n_7\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh_reg[4]_i_1_n_0\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh_reg[4]_i_1_n_1\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh_reg[4]_i_1_n_2\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh_reg[4]_i_1_n_3\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh_reg[4]_i_1_n_4\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh_reg[4]_i_1_n_5\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh_reg[4]_i_1_n_6\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh_reg[4]_i_1_n_7\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh_reg[8]_i_1_n_0\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh_reg[8]_i_1_n_1\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh_reg[8]_i_1_n_2\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh_reg[8]_i_1_n_3\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh_reg[8]_i_1_n_4\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh_reg[8]_i_1_n_5\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh_reg[8]_i_1_n_6\ : STD_LOGIC; - signal \sig_addr_cntr_im0_msh_reg[8]_i_1_n_7\ : STD_LOGIC; - signal sig_addr_cntr_incr_ireg2 : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal \sig_addr_cntr_incr_ireg2[0]_i_1_n_0\ : STD_LOGIC; - signal \sig_addr_cntr_incr_ireg2[1]_i_1_n_0\ : STD_LOGIC; - signal \sig_addr_cntr_incr_ireg2[2]_i_1_n_0\ : STD_LOGIC; - signal \sig_addr_cntr_incr_ireg2[3]_i_1_n_0\ : STD_LOGIC; - signal \sig_addr_cntr_incr_ireg2[4]_i_1_n_0\ : STD_LOGIC; - signal \sig_addr_cntr_incr_ireg2[5]_i_1_n_0\ : STD_LOGIC; - signal \sig_addr_cntr_incr_ireg2[6]_i_1_n_0\ : STD_LOGIC; - signal \sig_addr_cntr_incr_ireg2[7]_i_1_n_0\ : STD_LOGIC; - signal \sig_addr_cntr_lsh_im0[15]_i_1_n_0\ : STD_LOGIC; - signal \sig_addr_cntr_lsh_im0_reg_n_0_[0]\ : STD_LOGIC; - signal \sig_addr_cntr_lsh_im0_reg_n_0_[10]\ : STD_LOGIC; - signal \sig_addr_cntr_lsh_im0_reg_n_0_[11]\ : STD_LOGIC; - signal \sig_addr_cntr_lsh_im0_reg_n_0_[12]\ : STD_LOGIC; - signal \sig_addr_cntr_lsh_im0_reg_n_0_[13]\ : STD_LOGIC; - signal \sig_addr_cntr_lsh_im0_reg_n_0_[14]\ : STD_LOGIC; - signal \sig_addr_cntr_lsh_im0_reg_n_0_[1]\ : STD_LOGIC; - signal \sig_addr_cntr_lsh_im0_reg_n_0_[2]\ : STD_LOGIC; - signal \sig_addr_cntr_lsh_im0_reg_n_0_[3]\ : STD_LOGIC; - signal \sig_addr_cntr_lsh_im0_reg_n_0_[4]\ : STD_LOGIC; - signal \sig_addr_cntr_lsh_im0_reg_n_0_[5]\ : STD_LOGIC; - signal \sig_addr_cntr_lsh_im0_reg_n_0_[6]\ : STD_LOGIC; - signal \sig_addr_cntr_lsh_im0_reg_n_0_[7]\ : STD_LOGIC; - signal \sig_addr_cntr_lsh_im0_reg_n_0_[8]\ : STD_LOGIC; - signal \sig_addr_cntr_lsh_im0_reg_n_0_[9]\ : STD_LOGIC; - signal sig_addr_cntr_lsh_kh : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal sig_adjusted_addr_incr_im1 : STD_LOGIC_VECTOR ( 6 downto 0 ); - signal \sig_adjusted_addr_incr_ireg2[1]_i_2_n_0\ : STD_LOGIC; - signal \sig_adjusted_addr_incr_ireg2[2]_i_2_n_0\ : STD_LOGIC; - signal \sig_adjusted_addr_incr_ireg2[3]_i_2_n_0\ : STD_LOGIC; - signal \sig_adjusted_addr_incr_ireg2[6]_i_2_n_0\ : STD_LOGIC; - signal \sig_adjusted_addr_incr_ireg2_reg_n_0_[0]\ : STD_LOGIC; - signal \sig_adjusted_addr_incr_ireg2_reg_n_0_[1]\ : STD_LOGIC; - signal \sig_adjusted_addr_incr_ireg2_reg_n_0_[2]\ : STD_LOGIC; - signal \sig_adjusted_addr_incr_ireg2_reg_n_0_[3]\ : STD_LOGIC; - signal \sig_adjusted_addr_incr_ireg2_reg_n_0_[4]\ : STD_LOGIC; - signal \sig_adjusted_addr_incr_ireg2_reg_n_0_[5]\ : STD_LOGIC; - signal \sig_adjusted_addr_incr_ireg2_reg_n_0_[6]\ : STD_LOGIC; - signal sig_brst_cnt_eq_one_im0 : STD_LOGIC; - signal sig_brst_cnt_eq_one_ireg1 : STD_LOGIC; - signal sig_brst_cnt_eq_one_ireg1_i_2_n_0 : STD_LOGIC; - signal sig_brst_cnt_eq_zero_im0 : STD_LOGIC; - signal sig_brst_cnt_eq_zero_ireg1 : STD_LOGIC; - signal sig_brst_cnt_eq_zero_ireg1_i_2_n_0 : STD_LOGIC; - signal sig_btt_cntr_im00 : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal \sig_btt_cntr_im00_carry__0_i_1_n_0\ : STD_LOGIC; - signal \sig_btt_cntr_im00_carry__0_i_2_n_0\ : STD_LOGIC; - signal \sig_btt_cntr_im00_carry__0_i_3_n_0\ : STD_LOGIC; - signal \sig_btt_cntr_im00_carry__0_i_4_n_0\ : STD_LOGIC; - signal \sig_btt_cntr_im00_carry__0_n_0\ : STD_LOGIC; - signal \sig_btt_cntr_im00_carry__0_n_1\ : STD_LOGIC; - signal \sig_btt_cntr_im00_carry__0_n_2\ : STD_LOGIC; - signal \sig_btt_cntr_im00_carry__0_n_3\ : STD_LOGIC; - signal \sig_btt_cntr_im00_carry__1_i_1_n_0\ : STD_LOGIC; - signal \sig_btt_cntr_im00_carry__1_i_2_n_0\ : STD_LOGIC; - signal \sig_btt_cntr_im00_carry__1_i_3_n_0\ : STD_LOGIC; - signal \sig_btt_cntr_im00_carry__1_i_4_n_0\ : STD_LOGIC; - signal \sig_btt_cntr_im00_carry__1_n_0\ : STD_LOGIC; - signal \sig_btt_cntr_im00_carry__1_n_1\ : STD_LOGIC; - signal \sig_btt_cntr_im00_carry__1_n_2\ : STD_LOGIC; - signal \sig_btt_cntr_im00_carry__1_n_3\ : STD_LOGIC; - signal \sig_btt_cntr_im00_carry__2_i_1_n_0\ : STD_LOGIC; - signal \sig_btt_cntr_im00_carry__2_i_2_n_0\ : STD_LOGIC; - signal \sig_btt_cntr_im00_carry__2_i_3_n_0\ : STD_LOGIC; - signal \sig_btt_cntr_im00_carry__2_i_4_n_0\ : STD_LOGIC; - signal \sig_btt_cntr_im00_carry__2_n_1\ : STD_LOGIC; - signal \sig_btt_cntr_im00_carry__2_n_2\ : STD_LOGIC; - signal \sig_btt_cntr_im00_carry__2_n_3\ : STD_LOGIC; - signal sig_btt_cntr_im00_carry_i_1_n_0 : STD_LOGIC; - signal sig_btt_cntr_im00_carry_i_2_n_0 : STD_LOGIC; - signal sig_btt_cntr_im00_carry_i_3_n_0 : STD_LOGIC; - signal sig_btt_cntr_im00_carry_i_4_n_0 : STD_LOGIC; - signal sig_btt_cntr_im00_carry_n_0 : STD_LOGIC; - signal sig_btt_cntr_im00_carry_n_1 : STD_LOGIC; - signal sig_btt_cntr_im00_carry_n_2 : STD_LOGIC; - signal sig_btt_cntr_im00_carry_n_3 : STD_LOGIC; - signal \sig_btt_cntr_im0[0]_i_1_n_0\ : STD_LOGIC; - signal \sig_btt_cntr_im0[10]_i_1_n_0\ : STD_LOGIC; - signal \sig_btt_cntr_im0[11]_i_1_n_0\ : STD_LOGIC; - signal \sig_btt_cntr_im0[12]_i_1_n_0\ : STD_LOGIC; - signal \sig_btt_cntr_im0[13]_i_1_n_0\ : STD_LOGIC; - signal \sig_btt_cntr_im0[14]_i_1_n_0\ : STD_LOGIC; - signal \sig_btt_cntr_im0[15]_i_1_n_0\ : STD_LOGIC; - signal \sig_btt_cntr_im0[1]_i_1_n_0\ : STD_LOGIC; - signal \sig_btt_cntr_im0[2]_i_1_n_0\ : STD_LOGIC; - signal \sig_btt_cntr_im0[3]_i_1_n_0\ : STD_LOGIC; - signal \sig_btt_cntr_im0[4]_i_1_n_0\ : STD_LOGIC; - signal \sig_btt_cntr_im0[5]_i_1_n_0\ : STD_LOGIC; - signal \sig_btt_cntr_im0[6]_i_1_n_0\ : STD_LOGIC; - signal \sig_btt_cntr_im0[7]_i_1_n_0\ : STD_LOGIC; - signal \sig_btt_cntr_im0[8]_i_1_n_0\ : STD_LOGIC; - signal \sig_btt_cntr_im0[9]_i_1_n_0\ : STD_LOGIC; - signal sig_btt_eq_b2mbaa_im0 : STD_LOGIC; - signal sig_btt_eq_b2mbaa_ireg1 : STD_LOGIC; - signal sig_btt_eq_b2mbaa_ireg1_i_2_n_0 : STD_LOGIC; - signal sig_btt_eq_b2mbaa_ireg1_i_3_n_0 : STD_LOGIC; - signal sig_btt_eq_b2mbaa_ireg1_i_4_n_0 : STD_LOGIC; - signal sig_btt_lt_b2mbaa_im0 : STD_LOGIC; - signal sig_btt_lt_b2mbaa_im01 : STD_LOGIC; - signal sig_btt_lt_b2mbaa_im01_carry_i_1_n_0 : STD_LOGIC; - signal sig_btt_lt_b2mbaa_im01_carry_i_2_n_0 : STD_LOGIC; - signal sig_btt_lt_b2mbaa_im01_carry_i_3_n_0 : STD_LOGIC; - signal sig_btt_lt_b2mbaa_im01_carry_i_4_n_0 : STD_LOGIC; - signal sig_btt_lt_b2mbaa_im01_carry_i_5_n_0 : STD_LOGIC; - signal sig_btt_lt_b2mbaa_im01_carry_i_6_n_0 : STD_LOGIC; - signal sig_btt_lt_b2mbaa_im01_carry_i_7_n_0 : STD_LOGIC; - signal sig_btt_lt_b2mbaa_im01_carry_i_8_n_0 : STD_LOGIC; - signal sig_btt_lt_b2mbaa_im01_carry_n_1 : STD_LOGIC; - signal sig_btt_lt_b2mbaa_im01_carry_n_2 : STD_LOGIC; - signal sig_btt_lt_b2mbaa_im01_carry_n_3 : STD_LOGIC; - signal sig_btt_lt_b2mbaa_ireg1 : STD_LOGIC; - signal sig_btt_residue_slice_im0 : STD_LOGIC_VECTOR ( 6 downto 0 ); - signal \sig_byte_change_minus1_im2/i__n_0\ : STD_LOGIC; - signal sig_bytes_to_mbaa_ireg1 : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal \sig_bytes_to_mbaa_ireg1[1]_i_1_n_0\ : STD_LOGIC; - signal \sig_bytes_to_mbaa_ireg1[2]_i_1_n_0\ : STD_LOGIC; - signal \sig_bytes_to_mbaa_ireg1[3]_i_1_n_0\ : STD_LOGIC; - signal \sig_bytes_to_mbaa_ireg1[4]_i_1_n_0\ : STD_LOGIC; - signal \sig_bytes_to_mbaa_ireg1[5]_i_1_n_0\ : STD_LOGIC; - signal \sig_bytes_to_mbaa_ireg1[6]_i_1_n_0\ : STD_LOGIC; - signal \sig_bytes_to_mbaa_ireg1[7]_i_1_n_0\ : STD_LOGIC; - signal \sig_bytes_to_mbaa_ireg1[7]_i_2_n_0\ : STD_LOGIC; - signal \^sig_calc_error_pushed\ : STD_LOGIC; - signal sig_calc_error_pushed_i_1_n_0 : STD_LOGIC; +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_ibttcc is + signal \FSM_sequential_sig_csm_state[0]_i_2_n_0\ : STD_LOGIC; + signal \FSM_sequential_sig_csm_state[0]_i_3_n_0\ : STD_LOGIC; + signal \FSM_sequential_sig_csm_state[1]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_sig_csm_state[2]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_sig_csm_state_reg[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_sig_psm_state[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_sig_psm_state[0]_i_2_n_0\ : STD_LOGIC; + signal \FSM_sequential_sig_psm_state[1]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_sig_psm_state[2]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_sig_psm_state[2]_i_3_n_0\ : STD_LOGIC; + signal data : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \^p_10_out\ : STD_LOGIC; + signal \^p_11_out\ : STD_LOGIC; + signal p_1_in : STD_LOGIC; + signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \^p_22_out\ : STD_LOGIC; + signal \^p_32_out\ : STD_LOGIC; + signal \^p_9_out_0\ : STD_LOGIC; + signal sel0 : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal \sig_addr_aligned__6\ : STD_LOGIC; + signal \^sig_adjusted_addr_incr\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal sig_btt_cntr0 : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \sig_btt_cntr0_carry__0_i_1_n_0\ : STD_LOGIC; + signal \sig_btt_cntr0_carry__0_i_2_n_0\ : STD_LOGIC; + signal \sig_btt_cntr0_carry__0_i_3_n_0\ : STD_LOGIC; + signal \sig_btt_cntr0_carry__0_i_4_n_0\ : STD_LOGIC; + signal \sig_btt_cntr0_carry__0_n_0\ : STD_LOGIC; + signal \sig_btt_cntr0_carry__0_n_1\ : STD_LOGIC; + signal \sig_btt_cntr0_carry__0_n_2\ : STD_LOGIC; + signal \sig_btt_cntr0_carry__0_n_3\ : STD_LOGIC; + signal \sig_btt_cntr0_carry__1_i_1_n_0\ : STD_LOGIC; + signal \sig_btt_cntr0_carry__1_i_2_n_0\ : STD_LOGIC; + signal \sig_btt_cntr0_carry__1_i_3_n_0\ : STD_LOGIC; + signal \sig_btt_cntr0_carry__1_i_4_n_0\ : STD_LOGIC; + signal \sig_btt_cntr0_carry__1_n_0\ : STD_LOGIC; + signal \sig_btt_cntr0_carry__1_n_1\ : STD_LOGIC; + signal \sig_btt_cntr0_carry__1_n_2\ : STD_LOGIC; + signal \sig_btt_cntr0_carry__1_n_3\ : STD_LOGIC; + signal \sig_btt_cntr0_carry__2_i_1_n_0\ : STD_LOGIC; + signal \sig_btt_cntr0_carry__2_i_2_n_0\ : STD_LOGIC; + signal \sig_btt_cntr0_carry__2_i_3_n_0\ : STD_LOGIC; + signal \sig_btt_cntr0_carry__2_i_4_n_0\ : STD_LOGIC; + signal \sig_btt_cntr0_carry__2_n_1\ : STD_LOGIC; + signal \sig_btt_cntr0_carry__2_n_2\ : STD_LOGIC; + signal \sig_btt_cntr0_carry__2_n_3\ : STD_LOGIC; + signal sig_btt_cntr0_carry_i_1_n_0 : STD_LOGIC; + signal sig_btt_cntr0_carry_i_2_n_0 : STD_LOGIC; + signal sig_btt_cntr0_carry_i_3_n_0 : STD_LOGIC; + signal sig_btt_cntr0_carry_i_4_n_0 : STD_LOGIC; + signal sig_btt_cntr0_carry_n_0 : STD_LOGIC; + signal sig_btt_cntr0_carry_n_1 : STD_LOGIC; + signal sig_btt_cntr0_carry_n_2 : STD_LOGIC; + signal sig_btt_cntr0_carry_n_3 : STD_LOGIC; + signal \sig_btt_cntr[15]_i_1_n_0\ : STD_LOGIC; + signal sig_btt_eq_b2mbaa2 : STD_LOGIC; + signal sig_btt_eq_b2mbaa2_carry_i_1_n_0 : STD_LOGIC; + signal sig_btt_eq_b2mbaa2_carry_i_2_n_0 : STD_LOGIC; + signal sig_btt_eq_b2mbaa2_carry_i_3_n_0 : STD_LOGIC; + signal sig_btt_eq_b2mbaa2_carry_n_2 : STD_LOGIC; + signal sig_btt_eq_b2mbaa2_carry_n_3 : STD_LOGIC; + signal sig_btt_lt_b2mbaa2 : STD_LOGIC; + signal \sig_btt_lt_b2mbaa2_carry__0_i_1_n_0\ : STD_LOGIC; + signal \sig_btt_lt_b2mbaa2_carry__0_i_2_n_0\ : STD_LOGIC; + signal sig_btt_lt_b2mbaa2_carry_i_10_n_0 : STD_LOGIC; + signal sig_btt_lt_b2mbaa2_carry_i_1_n_0 : STD_LOGIC; + signal sig_btt_lt_b2mbaa2_carry_i_2_n_0 : STD_LOGIC; + signal sig_btt_lt_b2mbaa2_carry_i_3_n_0 : STD_LOGIC; + signal sig_btt_lt_b2mbaa2_carry_i_4_n_0 : STD_LOGIC; + signal sig_btt_lt_b2mbaa2_carry_i_5_n_0 : STD_LOGIC; + signal sig_btt_lt_b2mbaa2_carry_i_6_n_0 : STD_LOGIC; + signal sig_btt_lt_b2mbaa2_carry_i_7_n_0 : STD_LOGIC; + signal sig_btt_lt_b2mbaa2_carry_i_8_n_0 : STD_LOGIC; + signal sig_btt_lt_b2mbaa2_carry_i_9_n_0 : STD_LOGIC; + signal sig_btt_lt_b2mbaa2_carry_n_0 : STD_LOGIC; + signal sig_btt_lt_b2mbaa2_carry_n_1 : STD_LOGIC; + signal sig_btt_lt_b2mbaa2_carry_n_2 : STD_LOGIC; + signal sig_btt_lt_b2mbaa2_carry_n_3 : STD_LOGIC; + signal sig_btt_residue_slice : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal \sig_byte_change_minus1_carry__0_n_0\ : STD_LOGIC; + signal \sig_byte_change_minus1_carry__0_n_1\ : STD_LOGIC; + signal \sig_byte_change_minus1_carry__0_n_2\ : STD_LOGIC; + signal \sig_byte_change_minus1_carry__0_n_3\ : STD_LOGIC; + signal sig_byte_change_minus1_carry_n_0 : STD_LOGIC; + signal sig_byte_change_minus1_carry_n_1 : STD_LOGIC; + signal sig_byte_change_minus1_carry_n_2 : STD_LOGIC; + signal sig_byte_change_minus1_carry_n_3 : STD_LOGIC; + signal sig_bytes_to_mbaa : STD_LOGIC_VECTOR ( 8 to 8 ); + signal \sig_bytes_to_mbaa__8\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \sig_child_addr_cntr_lsh[0]_i_1_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh[12]_i_2_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh[12]_i_3_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh[12]_i_4_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh[12]_i_5_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh[8]_i_3_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh[8]_i_4_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh[8]_i_5_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh[8]_i_6_n_0\ : STD_LOGIC; + signal sig_child_addr_cntr_lsh_reg : STD_LOGIC_VECTOR ( 14 downto 3 ); + signal \sig_child_addr_cntr_lsh_reg[12]_i_1_n_1\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh_reg[12]_i_1_n_2\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh_reg[12]_i_1_n_3\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh_reg[12]_i_1_n_4\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh_reg[12]_i_1_n_5\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh_reg[12]_i_1_n_6\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh_reg[12]_i_1_n_7\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh_reg[8]_i_1_n_7\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh[0]_i_1_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh[0]_i_3_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh[0]_i_4_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh[0]_i_5_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh[0]_i_6_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh[0]_i_7_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh[12]_i_2_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh[12]_i_3_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh[12]_i_4_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh[12]_i_5_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh[4]_i_2_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh[4]_i_3_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh[4]_i_4_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh[4]_i_5_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh[8]_i_2_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh[8]_i_3_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh[8]_i_4_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh[8]_i_5_n_0\ : STD_LOGIC; + signal sig_child_addr_cntr_msh_reg : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \sig_child_addr_cntr_msh_reg[0]_i_2_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh_reg[0]_i_2_n_1\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh_reg[0]_i_2_n_2\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh_reg[0]_i_2_n_3\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh_reg[0]_i_2_n_4\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh_reg[0]_i_2_n_5\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh_reg[0]_i_2_n_6\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh_reg[0]_i_2_n_7\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh_reg[12]_i_1_n_1\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh_reg[12]_i_1_n_2\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh_reg[12]_i_1_n_3\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh_reg[12]_i_1_n_4\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh_reg[12]_i_1_n_5\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh_reg[12]_i_1_n_6\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh_reg[12]_i_1_n_7\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \sig_child_addr_cntr_msh_reg[8]_i_1_n_7\ : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_i_10_n_0 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_i_11_n_0 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_i_12_n_0 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_i_14_n_0 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_i_15_n_0 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_i_16_n_0 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_i_17_n_0 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_i_18_n_0 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_i_19_n_0 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_i_1_n_0 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_i_20_n_0 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_i_21_n_0 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_i_4_n_0 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_i_5_n_0 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_i_6_n_0 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_i_7_n_0 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_i_9_n_0 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_reg_i_13_n_0 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_reg_i_13_n_1 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_reg_i_13_n_2 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_reg_i_13_n_3 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_reg_i_2_n_1 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_reg_i_2_n_2 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_reg_i_2_n_3 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_reg_i_3_n_0 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_reg_i_3_n_1 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_reg_i_3_n_2 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_reg_i_3_n_3 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_reg_i_8_n_0 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_reg_i_8_n_1 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_reg_i_8_n_2 : STD_LOGIC; + signal sig_child_addr_lsh_rollover_reg_reg_i_8_n_3 : STD_LOGIC; + signal \sig_child_addr_reg_reg_n_0_[0]\ : STD_LOGIC; + signal \sig_child_addr_reg_reg_n_0_[10]\ : STD_LOGIC; + signal \sig_child_addr_reg_reg_n_0_[11]\ : STD_LOGIC; + signal \sig_child_addr_reg_reg_n_0_[12]\ : STD_LOGIC; + signal \sig_child_addr_reg_reg_n_0_[13]\ : STD_LOGIC; + signal \sig_child_addr_reg_reg_n_0_[14]\ : STD_LOGIC; + signal \sig_child_addr_reg_reg_n_0_[15]\ : STD_LOGIC; + signal \sig_child_addr_reg_reg_n_0_[1]\ : STD_LOGIC; + signal \sig_child_addr_reg_reg_n_0_[2]\ : STD_LOGIC; + signal \sig_child_addr_reg_reg_n_0_[3]\ : STD_LOGIC; + signal \sig_child_addr_reg_reg_n_0_[4]\ : STD_LOGIC; + signal \sig_child_addr_reg_reg_n_0_[5]\ : STD_LOGIC; + signal \sig_child_addr_reg_reg_n_0_[6]\ : STD_LOGIC; + signal \sig_child_addr_reg_reg_n_0_[7]\ : STD_LOGIC; + signal \sig_child_addr_reg_reg_n_0_[8]\ : STD_LOGIC; + signal \sig_child_addr_reg_reg_n_0_[9]\ : STD_LOGIC; + signal sig_child_burst_type_reg : STD_LOGIC; + signal sig_child_cmd_reg_full : STD_LOGIC; + signal sig_child_error_reg : STD_LOGIC; + signal sig_child_qual_burst_type : STD_LOGIC; + signal sig_child_qual_burst_type_i_1_n_0 : STD_LOGIC; + signal \^sig_child_qual_error_reg\ : STD_LOGIC; + signal sig_child_qual_error_reg_i_1_n_0 : STD_LOGIC; + signal \^sig_child_qual_first_of_2\ : STD_LOGIC; + signal sig_child_qual_first_of_2_i_1_n_0 : STD_LOGIC; signal sig_cmd2addr_valid_i_1_n_0 : STD_LOGIC; signal sig_cmd2data_valid_i_1_n_0 : STD_LOGIC; - signal sig_cmd2dre_valid_i_1_n_0 : STD_LOGIC; - signal sig_first_xfer_im0 : STD_LOGIC; - signal sig_first_xfer_im0_i_1_n_0 : STD_LOGIC; - signal \^sig_init_reg\ : STD_LOGIC; - signal sig_input_cache_type_reg0 : STD_LOGIC; - signal \^sig_input_reg_empty\ : STD_LOGIC; - signal sig_input_reg_empty_i_1_n_0 : STD_LOGIC; - signal sig_last_xfer_valid_im1 : STD_LOGIC; - signal sig_ld_xfer_reg : STD_LOGIC; - signal sig_ld_xfer_reg_i_1_n_0 : STD_LOGIC; - signal sig_ld_xfer_reg_tmp : STD_LOGIC; - signal sig_ld_xfer_reg_tmp_i_1_n_0 : STD_LOGIC; - signal \^sig_mstr2addr_cmd_valid\ : STD_LOGIC; - signal \^sig_mstr2data_cmd_valid\ : STD_LOGIC; - signal \^sig_mstr2sf_cmd_valid\ : STD_LOGIC; - signal sig_mstr2sf_eof : STD_LOGIC; - signal sig_no_btt_residue_im0 : STD_LOGIC; - signal sig_no_btt_residue_ireg1 : STD_LOGIC; - signal sig_no_btt_residue_ireg1_i_2_n_0 : STD_LOGIC; - signal sig_parent_done : STD_LOGIC; - signal sig_parent_done_i_1_n_0 : STD_LOGIC; - signal sig_pcc_sm_state : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal sig_csm_ld_xfer : STD_LOGIC; + signal sig_csm_ld_xfer_ns : STD_LOGIC; + signal \^sig_csm_pop_child_cmd\ : STD_LOGIC; + signal sig_csm_pop_child_cmd_ns : STD_LOGIC; + signal sig_csm_pop_sf_fifo_ns : STD_LOGIC; + signal sig_csm_state : STD_LOGIC_VECTOR ( 2 downto 0 ); attribute RTL_KEEP : string; - attribute RTL_KEEP of sig_pcc_sm_state : signal is "yes"; - signal sig_pop_xfer_reg0_out : STD_LOGIC; - signal sig_predict_addr_lsh_im2 : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal sig_predict_addr_lsh_ireg3 : STD_LOGIC_VECTOR ( 15 to 15 ); - signal \sig_predict_addr_lsh_ireg3[11]_i_2_n_0\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3[11]_i_3_n_0\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3[11]_i_4_n_0\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3[11]_i_5_n_0\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3[15]_i_2_n_0\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3[15]_i_3_n_0\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3[15]_i_4_n_0\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3[15]_i_5_n_0\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3[3]_i_2_n_0\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3[3]_i_3_n_0\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3[3]_i_4_n_0\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3[3]_i_5_n_0\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3[7]_i_2_n_0\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3[7]_i_3_n_0\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3[7]_i_4_n_0\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3[7]_i_5_n_0\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_0\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_1\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_2\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_3\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_1\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_2\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_3\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_0\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_1\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_2\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_3\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_0\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_1\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_2\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_3\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3_reg_n_0_[0]\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3_reg_n_0_[10]\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3_reg_n_0_[11]\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3_reg_n_0_[12]\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3_reg_n_0_[13]\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3_reg_n_0_[14]\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3_reg_n_0_[1]\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3_reg_n_0_[2]\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3_reg_n_0_[3]\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3_reg_n_0_[4]\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3_reg_n_0_[5]\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3_reg_n_0_[6]\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3_reg_n_0_[7]\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3_reg_n_0_[8]\ : STD_LOGIC; - signal \sig_predict_addr_lsh_ireg3_reg_n_0_[9]\ : STD_LOGIC; - signal sig_push_input_reg11_out : STD_LOGIC; - signal sig_sm_halt_ns : STD_LOGIC; - signal \^sig_sm_halt_reg\ : STD_LOGIC; - signal sig_sm_ld_calc1_reg : STD_LOGIC; - signal sig_sm_ld_calc1_reg_ns : STD_LOGIC; - signal sig_sm_ld_calc2_reg : STD_LOGIC; - signal sig_sm_ld_calc2_reg_ns : STD_LOGIC; - signal sig_sm_ld_calc3_reg : STD_LOGIC; - signal sig_sm_ld_calc3_reg_ns : STD_LOGIC; - signal sig_sm_ld_xfer_reg_ns : STD_LOGIC; - signal sig_sm_pop_input_reg : STD_LOGIC; - signal sig_sm_pop_input_reg_ns : STD_LOGIC; - signal sig_xfer_reg_empty : STD_LOGIC; - signal sig_xfer_reg_empty_i_1_n_0 : STD_LOGIC; - signal \NLW_sig_addr_cntr_im0_msh_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); - signal \NLW_sig_btt_cntr_im00_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); - signal NLW_sig_btt_lt_b2mbaa_im01_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal \NLW_sig_predict_addr_lsh_ireg3_reg[15]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \FSM_sequential_sig_pcc_sm_state[0]_i_2\ : label is "soft_lutpair85"; + attribute RTL_KEEP of sig_csm_state : signal is "yes"; + signal sig_csm_state_ns18_out : STD_LOGIC; + signal sig_first_realigner_cmd : STD_LOGIC; + signal sig_first_realigner_cmd_i_1_n_0 : STD_LOGIC; + signal sig_input_addr_reg : STD_LOGIC_VECTOR ( 31 downto 0 ); + attribute RTL_KEEP of sig_input_addr_reg : signal is "true"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of sig_input_addr_reg : signal is "no"; + signal sig_input_addr_reg1 : STD_LOGIC_VECTOR ( 31 downto 0 ); + attribute RTL_KEEP of sig_input_addr_reg1 : signal is "true"; + attribute equivalent_register_removal of sig_input_addr_reg1 : signal is "no"; + signal \sig_input_addr_reg[31]_i_2_n_0\ : STD_LOGIC; + signal sig_input_burst_type_reg : STD_LOGIC; + signal sig_input_eof_reg : STD_LOGIC; + signal \^sig_input_reg_empty\ : STD_LOGIC; + signal sig_needed_2_realign_cmds : STD_LOGIC; + signal sig_needed_2_realign_cmds_i_1_n_0 : STD_LOGIC; + signal sig_predict_child_addr_lsh : STD_LOGIC_VECTOR ( 15 to 15 ); + signal \^sig_psm_halt\ : STD_LOGIC; + signal sig_psm_halt_ns : STD_LOGIC; + signal sig_psm_ld_calc1 : STD_LOGIC; + signal sig_psm_ld_calc1_ns : STD_LOGIC; + signal sig_psm_ld_chcmd_reg : STD_LOGIC; + signal sig_psm_ld_chcmd_reg_ns : STD_LOGIC; + signal sig_psm_ld_realigner_reg : STD_LOGIC; + signal sig_psm_ld_realigner_reg_ns : STD_LOGIC; + signal sig_psm_pop_input_cmd_i_2_n_0 : STD_LOGIC; + signal sig_psm_pop_input_cmd_ns : STD_LOGIC; + signal sig_psm_state : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute RTL_KEEP of sig_psm_state : signal is "yes"; + signal \sig_psm_state_ns2__0\ : STD_LOGIC; + signal sig_realign_cmd_cmplt_reg_i_1_n_0 : STD_LOGIC; + signal sig_realign_eof_reg0 : STD_LOGIC; + signal sig_realign_reg_empty : STD_LOGIC; + signal sig_realign_strt_offset : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal sig_realign_tag_reg0 : STD_LOGIC; + signal sig_realigner_btt : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal sig_realigner_btt2 : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \sig_realigner_btt2[15]_i_1_n_0\ : STD_LOGIC; + signal \sig_realigner_btt2[15]_i_4_n_0\ : STD_LOGIC; + signal \sig_realigner_btt2[15]_i_5_n_0\ : STD_LOGIC; + signal \sig_realigner_btt2[2]_i_3_n_0\ : STD_LOGIC; + signal \sig_realigner_btt2[5]_i_3_n_0\ : STD_LOGIC; + signal \sig_realigner_btt2[8]_i_3_n_0\ : STD_LOGIC; + signal sig_skip_align2mbaa : STD_LOGIC; + signal sig_skip_align2mbaa_s_h : STD_LOGIC; + signal sig_skip_align2mbaa_s_h_i_1_n_0 : STD_LOGIC; + signal \^sig_xfer_addr_reg_reg[2]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal sig_xfer_cache_reg0 : STD_LOGIC; + signal \sig_xfer_len_reg[0]_i_1_n_0\ : STD_LOGIC; + signal \sig_xfer_len_reg[1]_i_1_n_0\ : STD_LOGIC; + signal \sig_xfer_len_reg[2]_i_1_n_0\ : STD_LOGIC; + signal \NLW_sig_btt_cntr0_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal NLW_sig_btt_eq_b2mbaa2_carry_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 to 3 ); + signal NLW_sig_btt_eq_b2mbaa2_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_sig_btt_lt_b2mbaa2_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_sig_btt_lt_b2mbaa2_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_sig_btt_lt_b2mbaa2_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_sig_byte_change_minus1_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_sig_byte_change_minus1_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_sig_child_addr_cntr_lsh_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_sig_child_addr_cntr_msh_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal NLW_sig_child_addr_lsh_rollover_reg_reg_i_13_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_sig_child_addr_lsh_rollover_reg_reg_i_2_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 to 3 ); + signal NLW_sig_child_addr_lsh_rollover_reg_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_sig_child_addr_lsh_rollover_reg_reg_i_3_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_sig_child_addr_lsh_rollover_reg_reg_i_8_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); attribute KEEP : string; - attribute KEEP of \FSM_sequential_sig_pcc_sm_state_reg[0]\ : label is "yes"; - attribute KEEP of \FSM_sequential_sig_pcc_sm_state_reg[1]\ : label is "yes"; - attribute KEEP of \FSM_sequential_sig_pcc_sm_state_reg[2]\ : label is "yes"; - attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[2]_i_2__0\ : label is "soft_lutpair85"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][10]_srl4_i_1\ : label is "soft_lutpair93"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][11]_srl4_i_1\ : label is "soft_lutpair94"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][12]_srl4_i_1\ : label is "soft_lutpair95"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][13]_srl4_i_1\ : label is "soft_lutpair94"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][14]_srl4_i_1\ : label is "soft_lutpair96"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][15]_srl4_i_1\ : label is "soft_lutpair97"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][16]_srl4_i_1\ : label is "soft_lutpair91"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][17]_srl4_i_1\ : label is "soft_lutpair98"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][18]_srl4_i_1\ : label is "soft_lutpair99"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][19]_srl4_i_1\ : label is "soft_lutpair98"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][20]_srl4_i_1\ : label is "soft_lutpair97"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][21]_srl4_i_1\ : label is "soft_lutpair100"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][22]_srl4_i_1\ : label is "soft_lutpair96"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][23]_srl4_i_1\ : label is "soft_lutpair88"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][24]_srl4_i_1\ : label is "soft_lutpair89"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][25]_srl4_i_1\ : label is "soft_lutpair92"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][26]_srl4_i_1\ : label is "soft_lutpair90"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][27]_srl4_i_1\ : label is "soft_lutpair101"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][28]_srl4_i_1\ : label is "soft_lutpair102"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][29]_srl4_i_1\ : label is "soft_lutpair101"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][30]_srl4_i_1\ : label is "soft_lutpair102"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][31]_srl4_i_1\ : label is "soft_lutpair100"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][32]_srl4_i_1__0\ : label is "soft_lutpair99"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][33]_srl4_i_1__0\ : label is "soft_lutpair87"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][34]_srl4_i_1\ : label is "soft_lutpair81"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][34]_srl4_i_1__0\ : label is "soft_lutpair93"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][35]_srl4_i_1\ : label is "soft_lutpair95"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][37]_srl4_i_1\ : label is "soft_lutpair76"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][4]_srl4_i_2\ : label is "soft_lutpair87"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][5]_srl4_i_1\ : label is "soft_lutpair88"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][6]_srl4_i_1\ : label is "soft_lutpair89"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][7]_srl4_i_1__1\ : label is "soft_lutpair90"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][8]_srl4_i_1\ : label is "soft_lutpair91"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][9]_srl4_i_1\ : label is "soft_lutpair92"; - attribute SOFT_HLUTNM of \sig_addr_cntr_incr_ireg2[0]_i_1\ : label is "soft_lutpair84"; - attribute SOFT_HLUTNM of \sig_addr_cntr_incr_ireg2[3]_i_1\ : label is "soft_lutpair79"; - attribute SOFT_HLUTNM of \sig_addr_cntr_incr_ireg2[4]_i_1\ : label is "soft_lutpair80"; - attribute SOFT_HLUTNM of \sig_addr_cntr_incr_ireg2[7]_i_1\ : label is "soft_lutpair84"; - attribute SOFT_HLUTNM of \sig_adjusted_addr_incr_ireg2[0]_i_1\ : label is "soft_lutpair77"; - attribute SOFT_HLUTNM of \sig_adjusted_addr_incr_ireg2[1]_i_2\ : label is "soft_lutpair77"; - attribute SOFT_HLUTNM of \sig_adjusted_addr_incr_ireg2[3]_i_1\ : label is "soft_lutpair79"; - attribute SOFT_HLUTNM of \sig_adjusted_addr_incr_ireg2[4]_i_1\ : label is "soft_lutpair80"; - attribute SOFT_HLUTNM of sig_brst_cnt_eq_one_ireg1_i_2 : label is "soft_lutpair86"; - attribute SOFT_HLUTNM of sig_brst_cnt_eq_zero_ireg1_i_2 : label is "soft_lutpair86"; - attribute SOFT_HLUTNM of \sig_byte_change_minus1_im2/i_\ : label is "soft_lutpair76"; - attribute SOFT_HLUTNM of \sig_bytes_to_mbaa_ireg1[2]_i_1\ : label is "soft_lutpair103"; - attribute SOFT_HLUTNM of \sig_bytes_to_mbaa_ireg1[3]_i_1\ : label is "soft_lutpair78"; - attribute SOFT_HLUTNM of \sig_bytes_to_mbaa_ireg1[4]_i_1\ : label is "soft_lutpair78"; - attribute SOFT_HLUTNM of \sig_bytes_to_mbaa_ireg1[7]_i_2\ : label is "soft_lutpair103"; - attribute SOFT_HLUTNM of sig_calc_error_pushed_i_1 : label is "soft_lutpair81"; - attribute SOFT_HLUTNM of sig_init_done_i_1 : label is "soft_lutpair82"; - attribute SOFT_HLUTNM of \sig_init_done_i_1__0\ : label is "soft_lutpair82"; - attribute SOFT_HLUTNM of \sig_init_done_i_1__2\ : label is "soft_lutpair83"; - attribute SOFT_HLUTNM of \sig_init_done_i_1__3\ : label is "soft_lutpair83"; + attribute KEEP of \FSM_sequential_sig_csm_state_reg[0]\ : label is "yes"; + attribute KEEP of \FSM_sequential_sig_csm_state_reg[1]\ : label is "yes"; + attribute KEEP of \FSM_sequential_sig_csm_state_reg[2]\ : label is "yes"; + attribute KEEP of \FSM_sequential_sig_psm_state_reg[0]\ : label is "yes"; + attribute KEEP of \FSM_sequential_sig_psm_state_reg[1]\ : label is "yes"; + attribute KEEP of \FSM_sequential_sig_psm_state_reg[2]\ : label is "yes"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of sig_child_qual_burst_type_i_1 : label is "soft_lutpair224"; + attribute SOFT_HLUTNM of sig_child_qual_error_reg_i_1 : label is "soft_lutpair224"; + attribute KEEP of \sig_input_addr_reg_reg[0]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[0]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[10]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[10]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[11]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[11]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[12]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[12]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[13]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[13]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[14]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[14]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[15]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[15]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[16]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[16]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[17]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[17]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[18]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[18]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[19]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[19]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[1]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[1]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[20]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[20]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[21]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[21]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[22]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[22]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[23]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[23]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[24]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[24]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[25]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[25]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[26]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[26]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[27]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[27]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[28]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[28]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[29]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[29]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[2]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[2]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[30]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[30]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[31]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[31]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[3]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[3]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[4]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[4]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[5]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[5]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[6]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[6]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[7]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[7]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[8]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[8]\ : label is "no"; + attribute KEEP of \sig_input_addr_reg_reg[9]\ : label is "yes"; + attribute equivalent_register_removal of \sig_input_addr_reg_reg[9]\ : label is "no"; + attribute SOFT_HLUTNM of sig_realign_cmd_cmplt_reg_i_1 : label is "soft_lutpair221"; + attribute SOFT_HLUTNM of sig_realign_eof_reg_i_1 : label is "soft_lutpair221"; + attribute SOFT_HLUTNM of \sig_realigner_btt2[10]_i_1\ : label is "soft_lutpair222"; + attribute SOFT_HLUTNM of \sig_realigner_btt2[11]_i_1\ : label is "soft_lutpair223"; + attribute SOFT_HLUTNM of \sig_realigner_btt2[12]_i_1\ : label is "soft_lutpair223"; + attribute SOFT_HLUTNM of \sig_realigner_btt2[13]_i_1\ : label is "soft_lutpair222"; + attribute SOFT_HLUTNM of \sig_realigner_btt2[15]_i_2\ : label is "soft_lutpair220"; + attribute SOFT_HLUTNM of \sig_realigner_btt2[3]_i_1\ : label is "soft_lutpair218"; + attribute SOFT_HLUTNM of \sig_realigner_btt2[4]_i_1\ : label is "soft_lutpair219"; + attribute SOFT_HLUTNM of \sig_realigner_btt2[5]_i_1\ : label is "soft_lutpair218"; + attribute SOFT_HLUTNM of \sig_realigner_btt2[6]_i_1\ : label is "soft_lutpair217"; + attribute SOFT_HLUTNM of \sig_realigner_btt2[7]_i_1\ : label is "soft_lutpair219"; + attribute SOFT_HLUTNM of \sig_realigner_btt2[8]_i_1\ : label is "soft_lutpair217"; + attribute SOFT_HLUTNM of \sig_realigner_btt2[9]_i_1\ : label is "soft_lutpair220"; + attribute SOFT_HLUTNM of \sig_xfer_len_reg[0]_i_1\ : label is "soft_lutpair216"; + attribute SOFT_HLUTNM of \sig_xfer_len_reg[1]_i_1\ : label is "soft_lutpair216"; begin - \in\(37 downto 0) <= \^in\(37 downto 0); - sig_calc_error_pushed <= \^sig_calc_error_pushed\; - sig_init_reg <= \^sig_init_reg\; + p_10_out <= \^p_10_out\; + p_11_out <= \^p_11_out\; + p_22_out <= \^p_22_out\; + p_32_out <= \^p_32_out\; + p_9_out_0 <= \^p_9_out_0\; + sig_adjusted_addr_incr(8 downto 0) <= \^sig_adjusted_addr_incr\(8 downto 0); + sig_child_qual_error_reg <= \^sig_child_qual_error_reg\; + sig_child_qual_first_of_2 <= \^sig_child_qual_first_of_2\; + sig_csm_pop_child_cmd <= \^sig_csm_pop_child_cmd\; sig_input_reg_empty <= \^sig_input_reg_empty\; - sig_mstr2addr_cmd_valid <= \^sig_mstr2addr_cmd_valid\; - sig_mstr2data_cmd_valid <= \^sig_mstr2data_cmd_valid\; - sig_mstr2sf_cmd_valid <= \^sig_mstr2sf_cmd_valid\; - sig_sm_halt_reg <= \^sig_sm_halt_reg\; -\FSM_sequential_sig_pcc_sm_state[0]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"DD3F00FFDD3F33FF" - ) - port map ( - I0 => sig_pop_xfer_reg0_out, - I1 => sig_pcc_sm_state(1), - I2 => \FSM_sequential_sig_pcc_sm_state[0]_i_2_n_0\, - I3 => sig_pcc_sm_state(0), - I4 => sig_pcc_sm_state(2), - I5 => sig_push_input_reg11_out, - O => \FSM_sequential_sig_pcc_sm_state[0]_i_1_n_0\ - ); -\FSM_sequential_sig_pcc_sm_state[0]_i_2\: unisim.vcomponents.LUT2 + sig_psm_halt <= \^sig_psm_halt\; + \sig_xfer_addr_reg_reg[2]_0\(2 downto 0) <= \^sig_xfer_addr_reg_reg[2]_0\(2 downto 0); +\FSM_sequential_sig_csm_state[0]_i_2\: unisim.vcomponents.LUT5 generic map( - INIT => X"1" + INIT => X"F0FF1F1F" ) port map ( - I0 => sig_parent_done, - I1 => \^sig_calc_error_pushed\, - O => \FSM_sequential_sig_pcc_sm_state[0]_i_2_n_0\ + I0 => \^p_11_out\, + I1 => \^p_22_out\, + I2 => sig_csm_state(1), + I3 => sig_child_cmd_reg_full, + I4 => sig_csm_state(0), + O => \FSM_sequential_sig_csm_state[0]_i_2_n_0\ ); -\FSM_sequential_sig_pcc_sm_state[1]_i_1\: unisim.vcomponents.LUT6 +\FSM_sequential_sig_csm_state[0]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"A8A0A8A00AA000A0" + INIT => X"3330BBBB33308888" ) port map ( - I0 => \FSM_sequential_sig_pcc_sm_state[1]_i_2_n_0\, - I1 => sig_pop_xfer_reg0_out, - I2 => sig_pcc_sm_state(1), - I3 => sig_pcc_sm_state(0), - I4 => sig_push_input_reg11_out, - I5 => sig_pcc_sm_state(2), - O => \FSM_sequential_sig_pcc_sm_state[1]_i_1_n_0\ + I0 => sig_csm_state_ns1, + I1 => sig_csm_state(1), + I2 => \^p_11_out\, + I3 => \^p_22_out\, + I4 => sig_csm_state(0), + I5 => sig_sf2pcc_xfer_valid, + O => \FSM_sequential_sig_csm_state[0]_i_3_n_0\ ); -\FSM_sequential_sig_pcc_sm_state[1]_i_2\: unisim.vcomponents.LUT4 +\FSM_sequential_sig_csm_state[1]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFF7" + INIT => X"33333333B0808080" ) port map ( - I0 => sig_pcc_sm_state(2), - I1 => sig_parent_done, - I2 => \^sig_calc_error_pushed\, - I3 => sig_pcc_sm_state(0), - O => \FSM_sequential_sig_pcc_sm_state[1]_i_2_n_0\ + I0 => sig_csm_state_ns18_out, + I1 => sig_csm_state(2), + I2 => sig_csm_state(0), + I3 => sig_child_cmd_reg_full, + I4 => sig_child_error_reg, + I5 => sig_csm_state(1), + O => \FSM_sequential_sig_csm_state[1]_i_1_n_0\ ); -\FSM_sequential_sig_pcc_sm_state[1]_i_3\: unisim.vcomponents.LUT6 +\FSM_sequential_sig_csm_state[1]_i_2\: unisim.vcomponents.LUT2 generic map( - INIT => X"CF450000CF45CF44" + INIT => X"1" ) port map ( - I0 => \^sig_mstr2addr_cmd_valid\, - I1 => sig_wr_fifo, - I2 => \^sig_mstr2data_cmd_valid\, - I3 => sig_wr_fifo_0, - I4 => sig_wr_fifo_1, - I5 => \^sig_mstr2sf_cmd_valid\, - O => sig_pop_xfer_reg0_out + I0 => \^p_22_out\, + I1 => \^p_11_out\, + O => sig_csm_state_ns18_out ); -\FSM_sequential_sig_pcc_sm_state[2]_i_1\: unisim.vcomponents.LUT4 +\FSM_sequential_sig_csm_state[2]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"ECAA" + INIT => X"04040404CCFCCCCC" ) port map ( - I0 => sig_pcc_sm_state(2), - I1 => sig_pcc_sm_state(0), - I2 => \^sig_calc_error_pushed\, - I3 => sig_pcc_sm_state(1), - O => \FSM_sequential_sig_pcc_sm_state[2]_i_1_n_0\ + I0 => sig_csm_state_ns1, + I1 => sig_csm_state(2), + I2 => sig_csm_state(0), + I3 => sig_child_error_reg, + I4 => sig_child_cmd_reg_full, + I5 => sig_csm_state(1), + O => \FSM_sequential_sig_csm_state[2]_i_1_n_0\ ); -\FSM_sequential_sig_pcc_sm_state_reg[0]\: unisim.vcomponents.FDRE +\FSM_sequential_sig_csm_state_reg[0]\: unisim.vcomponents.FDRE port map ( - C => m_axi_mm2s_aclk, + C => m_axi_s2mm_aclk, CE => '1', - D => \FSM_sequential_sig_pcc_sm_state[0]_i_1_n_0\, - Q => sig_pcc_sm_state(0), - R => \^sig_init_reg\ + D => \FSM_sequential_sig_csm_state_reg[0]_i_1_n_0\, + Q => sig_csm_state(0), + R => sig_init_reg ); -\FSM_sequential_sig_pcc_sm_state_reg[1]\: unisim.vcomponents.FDRE +\FSM_sequential_sig_csm_state_reg[0]_i_1\: unisim.vcomponents.MUXF7 port map ( - C => m_axi_mm2s_aclk, + I0 => \FSM_sequential_sig_csm_state[0]_i_2_n_0\, + I1 => \FSM_sequential_sig_csm_state[0]_i_3_n_0\, + O => \FSM_sequential_sig_csm_state_reg[0]_i_1_n_0\, + S => sig_csm_state(2) + ); +\FSM_sequential_sig_csm_state_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, CE => '1', - D => \FSM_sequential_sig_pcc_sm_state[1]_i_1_n_0\, - Q => sig_pcc_sm_state(1), - R => \^sig_init_reg\ + D => \FSM_sequential_sig_csm_state[1]_i_1_n_0\, + Q => sig_csm_state(1), + R => sig_init_reg ); -\FSM_sequential_sig_pcc_sm_state_reg[2]\: unisim.vcomponents.FDRE +\FSM_sequential_sig_csm_state_reg[2]\: unisim.vcomponents.FDRE port map ( - C => m_axi_mm2s_aclk, + C => m_axi_s2mm_aclk, CE => '1', - D => \FSM_sequential_sig_pcc_sm_state[2]_i_1_n_0\, - Q => sig_pcc_sm_state(2), - R => \^sig_init_reg\ + D => \FSM_sequential_sig_csm_state[2]_i_1_n_0\, + Q => sig_csm_state(2), + R => sig_init_reg ); -\INFERRED_GEN.cnt_i[2]_i_2__0\: unisim.vcomponents.LUT4 +\FSM_sequential_sig_psm_state[0]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"0004" + INIT => X"11114151" ) port map ( - I0 => \^sig_calc_error_pushed\, - I1 => \^sig_input_reg_empty\, - I2 => \^sig_sm_halt_reg\, - I3 => Q(0), - O => FIFO_Full_reg + I0 => \FSM_sequential_sig_psm_state[0]_i_2_n_0\, + I1 => sig_psm_state(2), + I2 => sig_psm_state(0), + I3 => \sig_input_addr_reg[31]_i_2_n_0\, + I4 => sig_psm_state(1), + O => \FSM_sequential_sig_psm_state[0]_i_1_n_0\ ); -\INFERRED_GEN.data_reg[3][10]_srl4_i_1\: unisim.vcomponents.LUT3 +\FSM_sequential_sig_psm_state[0]_i_2\: unisim.vcomponents.LUT5 generic map( - INIT => X"AC" + INIT => X"30550000" ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[6]\, - I1 => sig_addr_cntr_lsh_kh(6), - I2 => \^in\(36), - O => \^in\(6) + I0 => sig_realign_reg_empty, + I1 => sig_child_cmd_reg_full, + I2 => \^p_10_out\, + I3 => sig_psm_state(0), + I4 => sig_psm_state(1), + O => \FSM_sequential_sig_psm_state[0]_i_2_n_0\ ); -\INFERRED_GEN.data_reg[3][11]_srl4_i_1\: unisim.vcomponents.LUT3 +\FSM_sequential_sig_psm_state[1]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"AC" + INIT => X"45504050" ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[7]\, - I1 => sig_addr_cntr_lsh_kh(7), - I2 => \^in\(36), - O => \^in\(7) + I0 => sig_psm_state(2), + I1 => sig_child_cmd_reg_full, + I2 => sig_psm_state(1), + I3 => sig_psm_state(0), + I4 => \sig_input_addr_reg[31]_i_2_n_0\, + O => \FSM_sequential_sig_psm_state[1]_i_1_n_0\ ); -\INFERRED_GEN.data_reg[3][12]_srl4_i_1\: unisim.vcomponents.LUT3 +\FSM_sequential_sig_psm_state[2]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"AC" + INIT => X"FF1F0000" ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[8]\, - I1 => sig_addr_cntr_lsh_kh(8), - I2 => \^in\(36), - O => \^in\(8) + I0 => \sig_psm_state_ns2__0\, + I1 => sig_skip_align2mbaa_s_h, + I2 => sig_psm_state(1), + I3 => \^p_10_out\, + I4 => \FSM_sequential_sig_psm_state[2]_i_3_n_0\, + O => \FSM_sequential_sig_psm_state[2]_i_1_n_0\ ); -\INFERRED_GEN.data_reg[3][13]_srl4_i_1\: unisim.vcomponents.LUT3 +\FSM_sequential_sig_psm_state[2]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"AC" + INIT => X"FFFFFEAA00000000" ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[9]\, - I1 => sig_addr_cntr_lsh_kh(9), - I2 => \^in\(36), - O => \^in\(9) + I0 => \^p_10_out\, + I1 => sig_btt_eq_b2mbaa2, + I2 => sig_btt_lt_b2mbaa2, + I3 => \sig_realigner_btt2[15]_i_4_n_0\, + I4 => \sig_addr_aligned__6\, + I5 => sig_first_realigner_cmd, + O => \sig_psm_state_ns2__0\ ); -\INFERRED_GEN.data_reg[3][14]_srl4_i_1\: unisim.vcomponents.LUT3 +\FSM_sequential_sig_psm_state[2]_i_3\: unisim.vcomponents.LUT5 generic map( - INIT => X"AC" + INIT => X"04303430" ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[10]\, - I1 => sig_addr_cntr_lsh_kh(10), - I2 => \^in\(36), - O => \^in\(10) + I0 => sig_child_cmd_reg_full, + I1 => sig_psm_state(1), + I2 => sig_psm_state(2), + I3 => sig_psm_state(0), + I4 => sig_realign_reg_empty, + O => \FSM_sequential_sig_psm_state[2]_i_3_n_0\ ); -\INFERRED_GEN.data_reg[3][15]_srl4_i_1\: unisim.vcomponents.LUT3 +\FSM_sequential_sig_psm_state_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \FSM_sequential_sig_psm_state[0]_i_1_n_0\, + Q => sig_psm_state(0), + R => sig_init_reg + ); +\FSM_sequential_sig_psm_state_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \FSM_sequential_sig_psm_state[1]_i_1_n_0\, + Q => sig_psm_state(1), + R => sig_init_reg + ); +\FSM_sequential_sig_psm_state_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \FSM_sequential_sig_psm_state[2]_i_1_n_0\, + Q => sig_psm_state(2), + R => sig_init_reg + ); +i_0: unisim.vcomponents.LUT1 generic map( - INIT => X"AC" + INIT => X"2" ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[11]\, - I1 => sig_addr_cntr_lsh_kh(11), - I2 => \^in\(36), - O => \^in\(11) + I0 => '0', + O => sig_input_addr_reg1(31) ); -\INFERRED_GEN.data_reg[3][16]_srl4_i_1\: unisim.vcomponents.LUT3 +i_1: unisim.vcomponents.LUT1 generic map( - INIT => X"AC" + INIT => X"2" ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[12]\, - I1 => sig_addr_cntr_lsh_kh(12), - I2 => \^in\(36), - O => \^in\(12) + I0 => '0', + O => sig_input_addr_reg1(30) ); -\INFERRED_GEN.data_reg[3][17]_srl4_i_1\: unisim.vcomponents.LUT3 +i_10: unisim.vcomponents.LUT1 generic map( - INIT => X"AC" + INIT => X"2" ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[13]\, - I1 => sig_addr_cntr_lsh_kh(13), - I2 => \^in\(36), - O => \^in\(13) + I0 => '0', + O => sig_input_addr_reg1(21) ); -\INFERRED_GEN.data_reg[3][18]_srl4_i_1\: unisim.vcomponents.LUT3 +i_11: unisim.vcomponents.LUT1 generic map( - INIT => X"AC" + INIT => X"2" ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[14]\, - I1 => sig_addr_cntr_lsh_kh(14), - I2 => \^in\(36), - O => \^in\(14) + I0 => '0', + O => sig_input_addr_reg1(20) ); -\INFERRED_GEN.data_reg[3][19]_srl4_i_1\: unisim.vcomponents.LUT3 +i_12: unisim.vcomponents.LUT1 generic map( - INIT => X"AC" + INIT => X"2" ) port map ( - I0 => p_1_in_0, - I1 => sig_addr_cntr_lsh_kh(15), - I2 => \^in\(36), - O => \^in\(15) + I0 => '0', + O => sig_input_addr_reg1(19) ); -\INFERRED_GEN.data_reg[3][20]_srl4_i_1\: unisim.vcomponents.LUT3 +i_13: unisim.vcomponents.LUT1 generic map( - INIT => X"AC" + INIT => X"2" ) port map ( - I0 => sig_addr_cntr_im0_msh_reg(0), - I1 => sig_addr_cntr_lsh_kh(16), - I2 => \^in\(36), - O => \^in\(16) + I0 => '0', + O => sig_input_addr_reg1(18) ); -\INFERRED_GEN.data_reg[3][21]_srl4_i_1\: unisim.vcomponents.LUT3 +i_14: unisim.vcomponents.LUT1 generic map( - INIT => X"AC" + INIT => X"2" ) port map ( - I0 => sig_addr_cntr_im0_msh_reg(1), - I1 => sig_addr_cntr_lsh_kh(17), - I2 => \^in\(36), - O => \^in\(17) + I0 => '0', + O => sig_input_addr_reg1(17) ); -\INFERRED_GEN.data_reg[3][22]_srl4_i_1\: unisim.vcomponents.LUT3 +i_15: unisim.vcomponents.LUT1 generic map( - INIT => X"AC" + INIT => X"2" ) port map ( - I0 => sig_addr_cntr_im0_msh_reg(2), - I1 => sig_addr_cntr_lsh_kh(18), - I2 => \^in\(36), - O => \^in\(18) + I0 => '0', + O => sig_input_addr_reg1(16) ); -\INFERRED_GEN.data_reg[3][23]_srl4_i_1\: unisim.vcomponents.LUT3 +i_16: unisim.vcomponents.LUT1 generic map( - INIT => X"AC" + INIT => X"2" ) port map ( - I0 => sig_addr_cntr_im0_msh_reg(3), - I1 => sig_addr_cntr_lsh_kh(19), - I2 => \^in\(36), - O => \^in\(19) + I0 => '0', + O => sig_input_addr_reg1(15) ); -\INFERRED_GEN.data_reg[3][24]_srl4_i_1\: unisim.vcomponents.LUT3 +i_17: unisim.vcomponents.LUT1 generic map( - INIT => X"AC" + INIT => X"2" ) port map ( - I0 => sig_addr_cntr_im0_msh_reg(4), - I1 => sig_addr_cntr_lsh_kh(20), - I2 => \^in\(36), - O => \^in\(20) + I0 => '0', + O => sig_input_addr_reg1(14) ); -\INFERRED_GEN.data_reg[3][25]_srl4_i_1\: unisim.vcomponents.LUT3 +i_18: unisim.vcomponents.LUT1 generic map( - INIT => X"AC" + INIT => X"2" ) port map ( - I0 => sig_addr_cntr_im0_msh_reg(5), - I1 => sig_addr_cntr_lsh_kh(21), - I2 => \^in\(36), - O => \^in\(21) + I0 => '0', + O => sig_input_addr_reg1(13) ); -\INFERRED_GEN.data_reg[3][26]_srl4_i_1\: unisim.vcomponents.LUT3 +i_19: unisim.vcomponents.LUT1 generic map( - INIT => X"AC" + INIT => X"2" ) port map ( - I0 => sig_addr_cntr_im0_msh_reg(6), - I1 => sig_addr_cntr_lsh_kh(22), - I2 => \^in\(36), - O => \^in\(22) + I0 => '0', + O => sig_input_addr_reg1(12) ); -\INFERRED_GEN.data_reg[3][27]_srl4_i_1\: unisim.vcomponents.LUT3 +i_2: unisim.vcomponents.LUT1 generic map( - INIT => X"AC" + INIT => X"2" ) port map ( - I0 => sig_addr_cntr_im0_msh_reg(7), - I1 => sig_addr_cntr_lsh_kh(23), - I2 => \^in\(36), - O => \^in\(23) + I0 => '0', + O => sig_input_addr_reg1(29) ); -\INFERRED_GEN.data_reg[3][28]_srl4_i_1\: unisim.vcomponents.LUT3 +i_20: unisim.vcomponents.LUT1 generic map( - INIT => X"AC" + INIT => X"2" ) port map ( - I0 => sig_addr_cntr_im0_msh_reg(8), - I1 => sig_addr_cntr_lsh_kh(24), - I2 => \^in\(36), - O => \^in\(24) + I0 => '0', + O => sig_input_addr_reg1(11) ); -\INFERRED_GEN.data_reg[3][29]_srl4_i_1\: unisim.vcomponents.LUT3 +i_21: unisim.vcomponents.LUT1 generic map( - INIT => X"AC" + INIT => X"2" ) port map ( - I0 => sig_addr_cntr_im0_msh_reg(9), - I1 => sig_addr_cntr_lsh_kh(25), - I2 => \^in\(36), - O => \^in\(25) + I0 => '0', + O => sig_input_addr_reg1(10) ); -\INFERRED_GEN.data_reg[3][30]_srl4_i_1\: unisim.vcomponents.LUT3 +i_22: unisim.vcomponents.LUT1 generic map( - INIT => X"AC" + INIT => X"2" ) port map ( - I0 => sig_addr_cntr_im0_msh_reg(10), - I1 => sig_addr_cntr_lsh_kh(26), - I2 => \^in\(36), - O => \^in\(26) + I0 => '0', + O => sig_input_addr_reg1(9) ); -\INFERRED_GEN.data_reg[3][31]_srl4_i_1\: unisim.vcomponents.LUT3 +i_23: unisim.vcomponents.LUT1 generic map( - INIT => X"AC" + INIT => X"2" ) port map ( - I0 => sig_addr_cntr_im0_msh_reg(11), - I1 => sig_addr_cntr_lsh_kh(27), - I2 => \^in\(36), - O => \^in\(27) + I0 => '0', + O => sig_input_addr_reg1(8) ); -\INFERRED_GEN.data_reg[3][32]_srl4_i_1\: unisim.vcomponents.LUT2 +i_24: unisim.vcomponents.LUT1 generic map( - INIT => X"8" + INIT => X"2" ) port map ( - I0 => sig_mstr2sf_eof, - I1 => sig_last_xfer_valid_im1, - O => sig_next_cmd_cmplt_reg_reg(0) + I0 => '0', + O => sig_input_addr_reg1(7) ); -\INFERRED_GEN.data_reg[3][32]_srl4_i_1__0\: unisim.vcomponents.LUT3 +i_25: unisim.vcomponents.LUT1 generic map( - INIT => X"AC" + INIT => X"2" ) port map ( - I0 => sig_addr_cntr_im0_msh_reg(12), - I1 => sig_addr_cntr_lsh_kh(28), - I2 => \^in\(36), - O => \^in\(28) + I0 => '0', + O => sig_input_addr_reg1(6) ); -\INFERRED_GEN.data_reg[3][32]_srl4_i_2\: unisim.vcomponents.LUT6 +i_26: unisim.vcomponents.LUT1 generic map( - INIT => X"8F808F808F808080" + INIT => X"2" ) port map ( - I0 => sig_addr_aligned_ireg1, - I1 => sig_brst_cnt_eq_one_ireg1, - I2 => sig_no_btt_residue_ireg1, - I3 => sig_brst_cnt_eq_zero_ireg1, - I4 => sig_btt_eq_b2mbaa_ireg1, - I5 => sig_btt_lt_b2mbaa_ireg1, - O => sig_last_xfer_valid_im1 + I0 => '0', + O => sig_input_addr_reg1(5) ); -\INFERRED_GEN.data_reg[3][33]_srl4_i_1\: unisim.vcomponents.LUT6 +i_27: unisim.vcomponents.LUT1 generic map( - INIT => X"001FFF1FFF1FFF1F" + INIT => X"2" ) port map ( - I0 => sig_btt_lt_b2mbaa_ireg1, - I1 => sig_btt_eq_b2mbaa_ireg1, - I2 => sig_brst_cnt_eq_zero_ireg1, - I3 => sig_no_btt_residue_ireg1, - I4 => sig_brst_cnt_eq_one_ireg1, - I5 => sig_addr_aligned_ireg1, - O => sig_next_cmd_cmplt_reg_reg(1) + I0 => '0', + O => sig_input_addr_reg1(4) ); -\INFERRED_GEN.data_reg[3][33]_srl4_i_1__0\: unisim.vcomponents.LUT3 +i_28: unisim.vcomponents.LUT1 generic map( - INIT => X"AC" + INIT => X"2" ) port map ( - I0 => sig_addr_cntr_im0_msh_reg(13), - I1 => sig_addr_cntr_lsh_kh(29), - I2 => \^in\(36), - O => \^in\(29) + I0 => '0', + O => sig_input_addr_reg1(3) ); -\INFERRED_GEN.data_reg[3][34]_srl4_i_1\: unisim.vcomponents.LUT2 +i_29: unisim.vcomponents.LUT1 generic map( - INIT => X"E" + INIT => X"2" ) port map ( - I0 => sig_last_xfer_valid_im1, - I1 => \^in\(37), - O => sig_next_cmd_cmplt_reg_reg(2) + I0 => '0', + O => sig_input_addr_reg1(2) ); -\INFERRED_GEN.data_reg[3][34]_srl4_i_1__0\: unisim.vcomponents.LUT3 +i_3: unisim.vcomponents.LUT1 generic map( - INIT => X"AC" + INIT => X"2" ) port map ( - I0 => sig_addr_cntr_im0_msh_reg(14), - I1 => sig_addr_cntr_lsh_kh(30), - I2 => \^in\(36), - O => \^in\(30) + I0 => '0', + O => sig_input_addr_reg1(28) ); -\INFERRED_GEN.data_reg[3][35]_srl4_i_1\: unisim.vcomponents.LUT3 +i_30: unisim.vcomponents.LUT1 generic map( - INIT => X"AC" + INIT => X"2" ) port map ( - I0 => sig_addr_cntr_im0_msh_reg(15), - I1 => sig_addr_cntr_lsh_kh(31), - I2 => \^in\(36), - O => \^in\(31) + I0 => '0', + O => sig_input_addr_reg1(1) ); -\INFERRED_GEN.data_reg[3][36]_srl4_i_1\: unisim.vcomponents.LUT4 +i_31: unisim.vcomponents.LUT1 generic map( - INIT => X"FE01" + INIT => X"2" ) port map ( - I0 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[2]\, - I1 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[0]\, - I2 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[1]\, - I3 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[3]\, - O => \^in\(32) + I0 => '0', + O => sig_input_addr_reg1(0) ); -\INFERRED_GEN.data_reg[3][37]_srl4_i_1\: unisim.vcomponents.LUT5 +i_4: unisim.vcomponents.LUT1 generic map( - INIT => X"FFFE0001" + INIT => X"2" ) port map ( - I0 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[3]\, - I1 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[1]\, - I2 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[0]\, - I3 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[2]\, - I4 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[4]\, - O => \^in\(33) + I0 => '0', + O => sig_input_addr_reg1(27) ); -\INFERRED_GEN.data_reg[3][38]_srl4_i_1\: unisim.vcomponents.LUT6 +i_5: unisim.vcomponents.LUT1 generic map( - INIT => X"FFFFFFFE00000001" + INIT => X"2" ) port map ( - I0 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[4]\, - I1 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[2]\, - I2 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[0]\, - I3 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[1]\, - I4 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[3]\, - I5 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[5]\, - O => \^in\(34) + I0 => '0', + O => sig_input_addr_reg1(26) ); -\INFERRED_GEN.data_reg[3][39]_srl4_i_1\: unisim.vcomponents.LUT3 +i_6: unisim.vcomponents.LUT1 generic map( - INIT => X"E1" + INIT => X"2" ) port map ( - I0 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[5]\, - I1 => \sig_byte_change_minus1_im2/i__n_0\, - I2 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[6]\, - O => \^in\(35) + I0 => '0', + O => sig_input_addr_reg1(25) ); -\INFERRED_GEN.data_reg[3][4]_srl4_i_2\: unisim.vcomponents.LUT3 +i_7: unisim.vcomponents.LUT1 generic map( - INIT => X"AC" + INIT => X"2" ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, - I1 => sig_addr_cntr_lsh_kh(0), - I2 => \^in\(36), - O => \^in\(0) + I0 => '0', + O => sig_input_addr_reg1(24) ); -\INFERRED_GEN.data_reg[3][5]_srl4_i_1\: unisim.vcomponents.LUT3 +i_8: unisim.vcomponents.LUT1 generic map( - INIT => X"AC" + INIT => X"2" ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, - I1 => sig_addr_cntr_lsh_kh(1), - I2 => \^in\(36), - O => \^in\(1) + I0 => '0', + O => sig_input_addr_reg1(23) ); -\INFERRED_GEN.data_reg[3][6]_srl4_i_1\: unisim.vcomponents.LUT3 +i_9: unisim.vcomponents.LUT1 generic map( - INIT => X"AC" + INIT => X"2" ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, - I1 => sig_addr_cntr_lsh_kh(2), - I2 => \^in\(36), - O => \^in\(2) + I0 => '0', + O => sig_input_addr_reg1(22) ); -\INFERRED_GEN.data_reg[3][7]_srl4_i_1__1\: unisim.vcomponents.LUT3 +sig_btt_cntr0_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => sig_btt_cntr0_carry_n_0, + CO(2) => sig_btt_cntr0_carry_n_1, + CO(1) => sig_btt_cntr0_carry_n_2, + CO(0) => sig_btt_cntr0_carry_n_3, + CYINIT => '1', + DI(3 downto 0) => sig_btt_residue_slice(3 downto 0), + O(3 downto 0) => sig_btt_cntr0(3 downto 0), + S(3) => sig_btt_cntr0_carry_i_1_n_0, + S(2) => sig_btt_cntr0_carry_i_2_n_0, + S(1) => sig_btt_cntr0_carry_i_3_n_0, + S(0) => sig_btt_cntr0_carry_i_4_n_0 + ); +\sig_btt_cntr0_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => sig_btt_cntr0_carry_n_0, + CO(3) => \sig_btt_cntr0_carry__0_n_0\, + CO(2) => \sig_btt_cntr0_carry__0_n_1\, + CO(1) => \sig_btt_cntr0_carry__0_n_2\, + CO(0) => \sig_btt_cntr0_carry__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => sig_btt_residue_slice(7 downto 4), + O(3 downto 0) => sig_btt_cntr0(7 downto 4), + S(3) => \sig_btt_cntr0_carry__0_i_1_n_0\, + S(2) => \sig_btt_cntr0_carry__0_i_2_n_0\, + S(1) => \sig_btt_cntr0_carry__0_i_3_n_0\, + S(0) => \sig_btt_cntr0_carry__0_i_4_n_0\ + ); +\sig_btt_cntr0_carry__0_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"AC" + INIT => X"9" ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[3]\, - I1 => sig_addr_cntr_lsh_kh(3), - I2 => \^in\(36), - O => \^in\(3) + I0 => sig_btt_residue_slice(7), + I1 => sig_realigner_btt2(7), + O => \sig_btt_cntr0_carry__0_i_1_n_0\ ); -\INFERRED_GEN.data_reg[3][8]_srl4_i_1\: unisim.vcomponents.LUT3 +\sig_btt_cntr0_carry__0_i_2\: unisim.vcomponents.LUT2 generic map( - INIT => X"AC" + INIT => X"9" ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[4]\, - I1 => sig_addr_cntr_lsh_kh(4), - I2 => \^in\(36), - O => \^in\(4) + I0 => sig_btt_residue_slice(6), + I1 => sig_realigner_btt2(6), + O => \sig_btt_cntr0_carry__0_i_2_n_0\ ); -\INFERRED_GEN.data_reg[3][9]_srl4_i_1\: unisim.vcomponents.LUT3 +\sig_btt_cntr0_carry__0_i_3\: unisim.vcomponents.LUT2 generic map( - INIT => X"AC" + INIT => X"9" ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[5]\, - I1 => sig_addr_cntr_lsh_kh(5), - I2 => \^in\(36), - O => \^in\(5) + I0 => sig_btt_residue_slice(5), + I1 => sig_realigner_btt2(5), + O => \sig_btt_cntr0_carry__0_i_3_n_0\ ); -sig_addr_aligned_ireg1_i_1: unisim.vcomponents.LUT6 +\sig_btt_cntr0_carry__0_i_4\: unisim.vcomponents.LUT2 generic map( - INIT => X"0000000000000100" + INIT => X"9" ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[6]\, - I1 => \sig_addr_cntr_lsh_im0_reg_n_0_[4]\, - I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[5]\, - I3 => \sig_bytes_to_mbaa_ireg1[7]_i_2_n_0\, - I4 => \sig_addr_cntr_lsh_im0_reg_n_0_[3]\, - I5 => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, - O => sig_addr_aligned_im0 + I0 => sig_btt_residue_slice(4), + I1 => sig_realigner_btt2(4), + O => \sig_btt_cntr0_carry__0_i_4_n_0\ ); -sig_addr_aligned_ireg1_reg: unisim.vcomponents.FDRE +\sig_btt_cntr0_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \sig_btt_cntr0_carry__0_n_0\, + CO(3) => \sig_btt_cntr0_carry__1_n_0\, + CO(2) => \sig_btt_cntr0_carry__1_n_1\, + CO(1) => \sig_btt_cntr0_carry__1_n_2\, + CO(0) => \sig_btt_cntr0_carry__1_n_3\, + CYINIT => '0', + DI(3 downto 1) => sel0(2 downto 0), + DI(0) => sig_btt_residue_slice(8), + O(3 downto 0) => sig_btt_cntr0(11 downto 8), + S(3) => \sig_btt_cntr0_carry__1_i_1_n_0\, + S(2) => \sig_btt_cntr0_carry__1_i_2_n_0\, + S(1) => \sig_btt_cntr0_carry__1_i_3_n_0\, + S(0) => \sig_btt_cntr0_carry__1_i_4_n_0\ + ); +\sig_btt_cntr0_carry__1_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"9" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc1_reg, - D => sig_addr_aligned_im0, - Q => sig_addr_aligned_ireg1, - R => \^sig_init_reg\ + I0 => sel0(2), + I1 => sig_realigner_btt2(11), + O => \sig_btt_cntr0_carry__1_i_1_n_0\ ); -\sig_addr_cntr_im0_msh[0]_i_1\: unisim.vcomponents.LUT4 +\sig_btt_cntr0_carry__1_i_2\: unisim.vcomponents.LUT2 generic map( - INIT => X"AAEA" + INIT => X"9" ) port map ( - I0 => sig_push_input_reg11_out, - I1 => p_1_in_0, - I2 => sig_pop_xfer_reg0_out, - I3 => sig_predict_addr_lsh_ireg3(15), - O => \sig_addr_cntr_im0_msh[0]_i_1_n_0\ + I0 => sel0(1), + I1 => sig_realigner_btt2(10), + O => \sig_btt_cntr0_carry__1_i_2_n_0\ ); -\sig_addr_cntr_im0_msh[0]_i_3\: unisim.vcomponents.LUT6 +\sig_btt_cntr0_carry__1_i_3\: unisim.vcomponents.LUT2 generic map( - INIT => X"FFFFFFEF00000020" + INIT => X"9" ) port map ( - I0 => \out\(34), - I1 => \^in\(37), - I2 => \^sig_input_reg_empty\, - I3 => \^sig_sm_halt_reg\, - I4 => Q(0), - I5 => sig_addr_cntr_im0_msh_reg(0), - O => \sig_addr_cntr_im0_msh[0]_i_3_n_0\ + I0 => sel0(0), + I1 => sig_realigner_btt2(9), + O => \sig_btt_cntr0_carry__1_i_3_n_0\ ); -\sig_addr_cntr_im0_msh[0]_i_4\: unisim.vcomponents.LUT6 +\sig_btt_cntr0_carry__1_i_4\: unisim.vcomponents.LUT2 generic map( - INIT => X"FFFFFFEF00000020" + INIT => X"9" ) port map ( - I0 => \out\(37), - I1 => \^in\(37), - I2 => \^sig_input_reg_empty\, - I3 => \^sig_sm_halt_reg\, - I4 => Q(0), - I5 => sig_addr_cntr_im0_msh_reg(3), - O => \sig_addr_cntr_im0_msh[0]_i_4_n_0\ + I0 => sig_btt_residue_slice(8), + I1 => sig_realigner_btt2(8), + O => \sig_btt_cntr0_carry__1_i_4_n_0\ ); -\sig_addr_cntr_im0_msh[0]_i_5\: unisim.vcomponents.LUT6 +\sig_btt_cntr0_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \sig_btt_cntr0_carry__1_n_0\, + CO(3) => \NLW_sig_btt_cntr0_carry__2_CO_UNCONNECTED\(3), + CO(2) => \sig_btt_cntr0_carry__2_n_1\, + CO(1) => \sig_btt_cntr0_carry__2_n_2\, + CO(0) => \sig_btt_cntr0_carry__2_n_3\, + CYINIT => '0', + DI(3) => '0', + DI(2 downto 0) => sel0(5 downto 3), + O(3 downto 0) => sig_btt_cntr0(15 downto 12), + S(3) => \sig_btt_cntr0_carry__2_i_1_n_0\, + S(2) => \sig_btt_cntr0_carry__2_i_2_n_0\, + S(1) => \sig_btt_cntr0_carry__2_i_3_n_0\, + S(0) => \sig_btt_cntr0_carry__2_i_4_n_0\ + ); +\sig_btt_cntr0_carry__2_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"FFFFFFEF00000020" + INIT => X"9" ) port map ( - I0 => \out\(36), - I1 => \^in\(37), - I2 => \^sig_input_reg_empty\, - I3 => \^sig_sm_halt_reg\, - I4 => Q(0), - I5 => sig_addr_cntr_im0_msh_reg(2), - O => \sig_addr_cntr_im0_msh[0]_i_5_n_0\ + I0 => sel0(6), + I1 => sig_realigner_btt2(15), + O => \sig_btt_cntr0_carry__2_i_1_n_0\ ); -\sig_addr_cntr_im0_msh[0]_i_6\: unisim.vcomponents.LUT6 +\sig_btt_cntr0_carry__2_i_2\: unisim.vcomponents.LUT2 generic map( - INIT => X"FFFFFFEF00000020" + INIT => X"9" ) port map ( - I0 => \out\(35), - I1 => \^in\(37), - I2 => \^sig_input_reg_empty\, - I3 => \^sig_sm_halt_reg\, - I4 => Q(0), - I5 => sig_addr_cntr_im0_msh_reg(1), - O => \sig_addr_cntr_im0_msh[0]_i_6_n_0\ + I0 => sel0(5), + I1 => sig_realigner_btt2(14), + O => \sig_btt_cntr0_carry__2_i_2_n_0\ ); -\sig_addr_cntr_im0_msh[0]_i_7\: unisim.vcomponents.LUT6 +\sig_btt_cntr0_carry__2_i_3\: unisim.vcomponents.LUT2 generic map( - INIT => X"55555555555C5555" + INIT => X"9" ) port map ( - I0 => sig_addr_cntr_im0_msh_reg(0), - I1 => \out\(34), - I2 => Q(0), - I3 => \^sig_sm_halt_reg\, - I4 => \^sig_input_reg_empty\, - I5 => \^in\(37), - O => \sig_addr_cntr_im0_msh[0]_i_7_n_0\ + I0 => sel0(4), + I1 => sig_realigner_btt2(13), + O => \sig_btt_cntr0_carry__2_i_3_n_0\ ); -\sig_addr_cntr_im0_msh[12]_i_2\: unisim.vcomponents.LUT6 +\sig_btt_cntr0_carry__2_i_4\: unisim.vcomponents.LUT2 generic map( - INIT => X"FFFFFFEF00000020" + INIT => X"9" ) port map ( - I0 => \out\(49), - I1 => \^in\(37), - I2 => \^sig_input_reg_empty\, - I3 => \^sig_sm_halt_reg\, - I4 => Q(0), - I5 => sig_addr_cntr_im0_msh_reg(15), - O => \sig_addr_cntr_im0_msh[12]_i_2_n_0\ + I0 => sel0(3), + I1 => sig_realigner_btt2(12), + O => \sig_btt_cntr0_carry__2_i_4_n_0\ ); -\sig_addr_cntr_im0_msh[12]_i_3\: unisim.vcomponents.LUT6 +sig_btt_cntr0_carry_i_1: unisim.vcomponents.LUT2 generic map( - INIT => X"FFFFFFEF00000020" + INIT => X"9" ) port map ( - I0 => \out\(48), - I1 => \^in\(37), - I2 => \^sig_input_reg_empty\, - I3 => \^sig_sm_halt_reg\, - I4 => Q(0), - I5 => sig_addr_cntr_im0_msh_reg(14), - O => \sig_addr_cntr_im0_msh[12]_i_3_n_0\ + I0 => sig_btt_residue_slice(3), + I1 => sig_realigner_btt2(3), + O => sig_btt_cntr0_carry_i_1_n_0 ); -\sig_addr_cntr_im0_msh[12]_i_4\: unisim.vcomponents.LUT6 +sig_btt_cntr0_carry_i_2: unisim.vcomponents.LUT2 generic map( - INIT => X"FFFFFFEF00000020" + INIT => X"9" ) port map ( - I0 => \out\(47), - I1 => \^in\(37), - I2 => \^sig_input_reg_empty\, - I3 => \^sig_sm_halt_reg\, - I4 => Q(0), - I5 => sig_addr_cntr_im0_msh_reg(13), - O => \sig_addr_cntr_im0_msh[12]_i_4_n_0\ + I0 => sig_btt_residue_slice(2), + I1 => sig_realigner_btt2(2), + O => sig_btt_cntr0_carry_i_2_n_0 ); -\sig_addr_cntr_im0_msh[12]_i_5\: unisim.vcomponents.LUT6 +sig_btt_cntr0_carry_i_3: unisim.vcomponents.LUT2 generic map( - INIT => X"FFFFFFEF00000020" + INIT => X"9" ) port map ( - I0 => \out\(46), - I1 => \^in\(37), - I2 => \^sig_input_reg_empty\, - I3 => \^sig_sm_halt_reg\, - I4 => Q(0), - I5 => sig_addr_cntr_im0_msh_reg(12), - O => \sig_addr_cntr_im0_msh[12]_i_5_n_0\ + I0 => sig_btt_residue_slice(1), + I1 => sig_realigner_btt2(1), + O => sig_btt_cntr0_carry_i_3_n_0 ); -\sig_addr_cntr_im0_msh[4]_i_2\: unisim.vcomponents.LUT6 +sig_btt_cntr0_carry_i_4: unisim.vcomponents.LUT2 generic map( - INIT => X"FFFFFFEF00000020" + INIT => X"9" ) port map ( - I0 => \out\(41), - I1 => \^in\(37), - I2 => \^sig_input_reg_empty\, - I3 => \^sig_sm_halt_reg\, - I4 => Q(0), - I5 => sig_addr_cntr_im0_msh_reg(7), - O => \sig_addr_cntr_im0_msh[4]_i_2_n_0\ + I0 => sig_btt_residue_slice(0), + I1 => sig_realigner_btt2(0), + O => sig_btt_cntr0_carry_i_4_n_0 ); -\sig_addr_cntr_im0_msh[4]_i_3\: unisim.vcomponents.LUT6 +\sig_btt_cntr[0]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFEF00000020" + INIT => X"CCCCCCCCCCCCCACC" ) port map ( - I0 => \out\(40), - I1 => \^in\(37), - I2 => \^sig_input_reg_empty\, - I3 => \^sig_sm_halt_reg\, - I4 => Q(0), - I5 => sig_addr_cntr_im0_msh_reg(6), - O => \sig_addr_cntr_im0_msh[4]_i_3_n_0\ + I0 => \out\(0), + I1 => sig_btt_cntr0(0), + I2 => Q(0), + I3 => \^sig_input_reg_empty\, + I4 => \^sig_psm_halt\, + I5 => \^p_10_out\, + O => \p_1_in__0\(0) ); -\sig_addr_cntr_im0_msh[4]_i_4\: unisim.vcomponents.LUT6 +\sig_btt_cntr[10]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFEF00000020" + INIT => X"CCCCCCCCCCCCCACC" ) port map ( - I0 => \out\(39), - I1 => \^in\(37), - I2 => \^sig_input_reg_empty\, - I3 => \^sig_sm_halt_reg\, - I4 => Q(0), - I5 => sig_addr_cntr_im0_msh_reg(5), - O => \sig_addr_cntr_im0_msh[4]_i_4_n_0\ + I0 => \out\(10), + I1 => sig_btt_cntr0(10), + I2 => Q(0), + I3 => \^sig_input_reg_empty\, + I4 => \^sig_psm_halt\, + I5 => \^p_10_out\, + O => \p_1_in__0\(10) ); -\sig_addr_cntr_im0_msh[4]_i_5\: unisim.vcomponents.LUT6 +\sig_btt_cntr[11]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFEF00000020" + INIT => X"CCCCCCCCCCCCCACC" ) port map ( - I0 => \out\(38), - I1 => \^in\(37), - I2 => \^sig_input_reg_empty\, - I3 => \^sig_sm_halt_reg\, - I4 => Q(0), - I5 => sig_addr_cntr_im0_msh_reg(4), - O => \sig_addr_cntr_im0_msh[4]_i_5_n_0\ + I0 => \out\(11), + I1 => sig_btt_cntr0(11), + I2 => Q(0), + I3 => \^sig_input_reg_empty\, + I4 => \^sig_psm_halt\, + I5 => \^p_10_out\, + O => \p_1_in__0\(11) ); -\sig_addr_cntr_im0_msh[8]_i_2\: unisim.vcomponents.LUT6 +\sig_btt_cntr[12]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFEF00000020" + INIT => X"CCCCCCCCCCCCCACC" ) port map ( - I0 => \out\(45), - I1 => \^in\(37), - I2 => \^sig_input_reg_empty\, - I3 => \^sig_sm_halt_reg\, - I4 => Q(0), - I5 => sig_addr_cntr_im0_msh_reg(11), - O => \sig_addr_cntr_im0_msh[8]_i_2_n_0\ + I0 => \out\(12), + I1 => sig_btt_cntr0(12), + I2 => Q(0), + I3 => \^sig_input_reg_empty\, + I4 => \^sig_psm_halt\, + I5 => \^p_10_out\, + O => \p_1_in__0\(12) ); -\sig_addr_cntr_im0_msh[8]_i_3\: unisim.vcomponents.LUT6 +\sig_btt_cntr[13]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFEF00000020" + INIT => X"CCCCCCCCCCCCCACC" ) port map ( - I0 => \out\(44), - I1 => \^in\(37), - I2 => \^sig_input_reg_empty\, - I3 => \^sig_sm_halt_reg\, - I4 => Q(0), - I5 => sig_addr_cntr_im0_msh_reg(10), - O => \sig_addr_cntr_im0_msh[8]_i_3_n_0\ + I0 => \out\(13), + I1 => sig_btt_cntr0(13), + I2 => Q(0), + I3 => \^sig_input_reg_empty\, + I4 => \^sig_psm_halt\, + I5 => \^p_10_out\, + O => \p_1_in__0\(13) ); -\sig_addr_cntr_im0_msh[8]_i_4\: unisim.vcomponents.LUT6 +\sig_btt_cntr[14]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFEF00000020" + INIT => X"CCCCCCCCCCCCCACC" ) port map ( - I0 => \out\(43), - I1 => \^in\(37), - I2 => \^sig_input_reg_empty\, - I3 => \^sig_sm_halt_reg\, - I4 => Q(0), - I5 => sig_addr_cntr_im0_msh_reg(9), - O => \sig_addr_cntr_im0_msh[8]_i_4_n_0\ + I0 => \out\(14), + I1 => sig_btt_cntr0(14), + I2 => Q(0), + I3 => \^sig_input_reg_empty\, + I4 => \^sig_psm_halt\, + I5 => \^p_10_out\, + O => \p_1_in__0\(14) ); -\sig_addr_cntr_im0_msh[8]_i_5\: unisim.vcomponents.LUT6 +\sig_btt_cntr[15]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"FFFFFFEF00000020" + INIT => X"FFFF0010" ) port map ( - I0 => \out\(42), - I1 => \^in\(37), + I0 => \^p_10_out\, + I1 => \^sig_psm_halt\, I2 => \^sig_input_reg_empty\, - I3 => \^sig_sm_halt_reg\, - I4 => Q(0), - I5 => sig_addr_cntr_im0_msh_reg(8), - O => \sig_addr_cntr_im0_msh[8]_i_5_n_0\ + I3 => Q(0), + I4 => sig_psm_ld_realigner_reg, + O => \sig_btt_cntr[15]_i_1_n_0\ ); -\sig_addr_cntr_im0_msh_reg[0]\: unisim.vcomponents.FDRE +\sig_btt_cntr[15]_i_2__0\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"CCCCCCCCCCCCCACC" ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, - D => \sig_addr_cntr_im0_msh_reg[0]_i_2_n_7\, - Q => sig_addr_cntr_im0_msh_reg(0), - R => \^sig_init_reg\ + I0 => \out\(15), + I1 => sig_btt_cntr0(15), + I2 => Q(0), + I3 => \^sig_input_reg_empty\, + I4 => \^sig_psm_halt\, + I5 => \^p_10_out\, + O => \p_1_in__0\(15) ); -\sig_addr_cntr_im0_msh_reg[0]_i_2\: unisim.vcomponents.CARRY4 - port map ( - CI => '0', - CO(3) => \sig_addr_cntr_im0_msh_reg[0]_i_2_n_0\, - CO(2) => \sig_addr_cntr_im0_msh_reg[0]_i_2_n_1\, - CO(1) => \sig_addr_cntr_im0_msh_reg[0]_i_2_n_2\, - CO(0) => \sig_addr_cntr_im0_msh_reg[0]_i_2_n_3\, - CYINIT => '0', - DI(3 downto 1) => B"000", - DI(0) => \sig_addr_cntr_im0_msh[0]_i_3_n_0\, - O(3) => \sig_addr_cntr_im0_msh_reg[0]_i_2_n_4\, - O(2) => \sig_addr_cntr_im0_msh_reg[0]_i_2_n_5\, - O(1) => \sig_addr_cntr_im0_msh_reg[0]_i_2_n_6\, - O(0) => \sig_addr_cntr_im0_msh_reg[0]_i_2_n_7\, - S(3) => \sig_addr_cntr_im0_msh[0]_i_4_n_0\, - S(2) => \sig_addr_cntr_im0_msh[0]_i_5_n_0\, - S(1) => \sig_addr_cntr_im0_msh[0]_i_6_n_0\, - S(0) => \sig_addr_cntr_im0_msh[0]_i_7_n_0\ +\sig_btt_cntr[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CCCCCCCCCCCCCACC" + ) + port map ( + I0 => \out\(1), + I1 => sig_btt_cntr0(1), + I2 => Q(0), + I3 => \^sig_input_reg_empty\, + I4 => \^sig_psm_halt\, + I5 => \^p_10_out\, + O => \p_1_in__0\(1) ); -\sig_addr_cntr_im0_msh_reg[10]\: unisim.vcomponents.FDRE +\sig_btt_cntr[2]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"CCCCCCCCCCCCCACC" ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, - D => \sig_addr_cntr_im0_msh_reg[8]_i_1_n_5\, - Q => sig_addr_cntr_im0_msh_reg(10), - R => \^sig_init_reg\ + I0 => \out\(2), + I1 => sig_btt_cntr0(2), + I2 => Q(0), + I3 => \^sig_input_reg_empty\, + I4 => \^sig_psm_halt\, + I5 => \^p_10_out\, + O => \p_1_in__0\(2) ); -\sig_addr_cntr_im0_msh_reg[11]\: unisim.vcomponents.FDRE +\sig_btt_cntr[3]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"CCCCCCCCCCCCCACC" ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, - D => \sig_addr_cntr_im0_msh_reg[8]_i_1_n_4\, - Q => sig_addr_cntr_im0_msh_reg(11), - R => \^sig_init_reg\ + I0 => \out\(3), + I1 => sig_btt_cntr0(3), + I2 => Q(0), + I3 => \^sig_input_reg_empty\, + I4 => \^sig_psm_halt\, + I5 => \^p_10_out\, + O => \p_1_in__0\(3) ); -\sig_addr_cntr_im0_msh_reg[12]\: unisim.vcomponents.FDRE +\sig_btt_cntr[4]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"CCCCCCCCCCCCCACC" ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, - D => \sig_addr_cntr_im0_msh_reg[12]_i_1_n_7\, - Q => sig_addr_cntr_im0_msh_reg(12), - R => \^sig_init_reg\ + I0 => \out\(4), + I1 => sig_btt_cntr0(4), + I2 => Q(0), + I3 => \^sig_input_reg_empty\, + I4 => \^sig_psm_halt\, + I5 => \^p_10_out\, + O => \p_1_in__0\(4) ); -\sig_addr_cntr_im0_msh_reg[12]_i_1\: unisim.vcomponents.CARRY4 - port map ( - CI => \sig_addr_cntr_im0_msh_reg[8]_i_1_n_0\, - CO(3) => \NLW_sig_addr_cntr_im0_msh_reg[12]_i_1_CO_UNCONNECTED\(3), - CO(2) => \sig_addr_cntr_im0_msh_reg[12]_i_1_n_1\, - CO(1) => \sig_addr_cntr_im0_msh_reg[12]_i_1_n_2\, - CO(0) => \sig_addr_cntr_im0_msh_reg[12]_i_1_n_3\, - CYINIT => '0', - DI(3 downto 0) => B"0000", - O(3) => \sig_addr_cntr_im0_msh_reg[12]_i_1_n_4\, - O(2) => \sig_addr_cntr_im0_msh_reg[12]_i_1_n_5\, - O(1) => \sig_addr_cntr_im0_msh_reg[12]_i_1_n_6\, - O(0) => \sig_addr_cntr_im0_msh_reg[12]_i_1_n_7\, - S(3) => \sig_addr_cntr_im0_msh[12]_i_2_n_0\, - S(2) => \sig_addr_cntr_im0_msh[12]_i_3_n_0\, - S(1) => \sig_addr_cntr_im0_msh[12]_i_4_n_0\, - S(0) => \sig_addr_cntr_im0_msh[12]_i_5_n_0\ +\sig_btt_cntr[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CCCCCCCCCCCCCACC" + ) + port map ( + I0 => \out\(5), + I1 => sig_btt_cntr0(5), + I2 => Q(0), + I3 => \^sig_input_reg_empty\, + I4 => \^sig_psm_halt\, + I5 => \^p_10_out\, + O => \p_1_in__0\(5) ); -\sig_addr_cntr_im0_msh_reg[13]\: unisim.vcomponents.FDRE +\sig_btt_cntr[6]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"CCCCCCCCCCCCCACC" ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, - D => \sig_addr_cntr_im0_msh_reg[12]_i_1_n_6\, - Q => sig_addr_cntr_im0_msh_reg(13), - R => \^sig_init_reg\ + I0 => \out\(6), + I1 => sig_btt_cntr0(6), + I2 => Q(0), + I3 => \^sig_input_reg_empty\, + I4 => \^sig_psm_halt\, + I5 => \^p_10_out\, + O => \p_1_in__0\(6) ); -\sig_addr_cntr_im0_msh_reg[14]\: unisim.vcomponents.FDRE +\sig_btt_cntr[7]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"CCCCCCCCCCCCCACC" ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, - D => \sig_addr_cntr_im0_msh_reg[12]_i_1_n_5\, - Q => sig_addr_cntr_im0_msh_reg(14), - R => \^sig_init_reg\ + I0 => \out\(7), + I1 => sig_btt_cntr0(7), + I2 => Q(0), + I3 => \^sig_input_reg_empty\, + I4 => \^sig_psm_halt\, + I5 => \^p_10_out\, + O => \p_1_in__0\(7) ); -\sig_addr_cntr_im0_msh_reg[15]\: unisim.vcomponents.FDRE +\sig_btt_cntr[8]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"CCCCCCCCCCCCCACC" ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, - D => \sig_addr_cntr_im0_msh_reg[12]_i_1_n_4\, - Q => sig_addr_cntr_im0_msh_reg(15), - R => \^sig_init_reg\ + I0 => \out\(8), + I1 => sig_btt_cntr0(8), + I2 => Q(0), + I3 => \^sig_input_reg_empty\, + I4 => \^sig_psm_halt\, + I5 => \^p_10_out\, + O => \p_1_in__0\(8) ); -\sig_addr_cntr_im0_msh_reg[1]\: unisim.vcomponents.FDRE +\sig_btt_cntr[9]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"CCCCCCCCCCCCCACC" ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, - D => \sig_addr_cntr_im0_msh_reg[0]_i_2_n_6\, - Q => sig_addr_cntr_im0_msh_reg(1), - R => \^sig_init_reg\ + I0 => \out\(9), + I1 => sig_btt_cntr0(9), + I2 => Q(0), + I3 => \^sig_input_reg_empty\, + I4 => \^sig_psm_halt\, + I5 => \^p_10_out\, + O => \p_1_in__0\(9) ); -\sig_addr_cntr_im0_msh_reg[2]\: unisim.vcomponents.FDRE +\sig_btt_cntr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, - D => \sig_addr_cntr_im0_msh_reg[0]_i_2_n_5\, - Q => sig_addr_cntr_im0_msh_reg(2), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_btt_cntr[15]_i_1_n_0\, + D => \p_1_in__0\(0), + Q => sig_btt_residue_slice(0), + R => sig_init_reg ); -\sig_addr_cntr_im0_msh_reg[3]\: unisim.vcomponents.FDRE +\sig_btt_cntr_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, - D => \sig_addr_cntr_im0_msh_reg[0]_i_2_n_4\, - Q => sig_addr_cntr_im0_msh_reg(3), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_btt_cntr[15]_i_1_n_0\, + D => \p_1_in__0\(10), + Q => sel0(1), + R => sig_init_reg ); -\sig_addr_cntr_im0_msh_reg[4]\: unisim.vcomponents.FDRE +\sig_btt_cntr_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, - D => \sig_addr_cntr_im0_msh_reg[4]_i_1_n_7\, - Q => sig_addr_cntr_im0_msh_reg(4), - R => \^sig_init_reg\ - ); -\sig_addr_cntr_im0_msh_reg[4]_i_1\: unisim.vcomponents.CARRY4 - port map ( - CI => \sig_addr_cntr_im0_msh_reg[0]_i_2_n_0\, - CO(3) => \sig_addr_cntr_im0_msh_reg[4]_i_1_n_0\, - CO(2) => \sig_addr_cntr_im0_msh_reg[4]_i_1_n_1\, - CO(1) => \sig_addr_cntr_im0_msh_reg[4]_i_1_n_2\, - CO(0) => \sig_addr_cntr_im0_msh_reg[4]_i_1_n_3\, - CYINIT => '0', - DI(3 downto 0) => B"0000", - O(3) => \sig_addr_cntr_im0_msh_reg[4]_i_1_n_4\, - O(2) => \sig_addr_cntr_im0_msh_reg[4]_i_1_n_5\, - O(1) => \sig_addr_cntr_im0_msh_reg[4]_i_1_n_6\, - O(0) => \sig_addr_cntr_im0_msh_reg[4]_i_1_n_7\, - S(3) => \sig_addr_cntr_im0_msh[4]_i_2_n_0\, - S(2) => \sig_addr_cntr_im0_msh[4]_i_3_n_0\, - S(1) => \sig_addr_cntr_im0_msh[4]_i_4_n_0\, - S(0) => \sig_addr_cntr_im0_msh[4]_i_5_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_btt_cntr[15]_i_1_n_0\, + D => \p_1_in__0\(11), + Q => sel0(2), + R => sig_init_reg ); -\sig_addr_cntr_im0_msh_reg[5]\: unisim.vcomponents.FDRE +\sig_btt_cntr_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, - D => \sig_addr_cntr_im0_msh_reg[4]_i_1_n_6\, - Q => sig_addr_cntr_im0_msh_reg(5), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_btt_cntr[15]_i_1_n_0\, + D => \p_1_in__0\(12), + Q => sel0(3), + R => sig_init_reg ); -\sig_addr_cntr_im0_msh_reg[6]\: unisim.vcomponents.FDRE +\sig_btt_cntr_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, - D => \sig_addr_cntr_im0_msh_reg[4]_i_1_n_5\, - Q => sig_addr_cntr_im0_msh_reg(6), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_btt_cntr[15]_i_1_n_0\, + D => \p_1_in__0\(13), + Q => sel0(4), + R => sig_init_reg ); -\sig_addr_cntr_im0_msh_reg[7]\: unisim.vcomponents.FDRE +\sig_btt_cntr_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, - D => \sig_addr_cntr_im0_msh_reg[4]_i_1_n_4\, - Q => sig_addr_cntr_im0_msh_reg(7), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_btt_cntr[15]_i_1_n_0\, + D => \p_1_in__0\(14), + Q => sel0(5), + R => sig_init_reg ); -\sig_addr_cntr_im0_msh_reg[8]\: unisim.vcomponents.FDRE +\sig_btt_cntr_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, - D => \sig_addr_cntr_im0_msh_reg[8]_i_1_n_7\, - Q => sig_addr_cntr_im0_msh_reg(8), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_btt_cntr[15]_i_1_n_0\, + D => \p_1_in__0\(15), + Q => sel0(6), + R => sig_init_reg ); -\sig_addr_cntr_im0_msh_reg[8]_i_1\: unisim.vcomponents.CARRY4 - port map ( - CI => \sig_addr_cntr_im0_msh_reg[4]_i_1_n_0\, - CO(3) => \sig_addr_cntr_im0_msh_reg[8]_i_1_n_0\, - CO(2) => \sig_addr_cntr_im0_msh_reg[8]_i_1_n_1\, - CO(1) => \sig_addr_cntr_im0_msh_reg[8]_i_1_n_2\, - CO(0) => \sig_addr_cntr_im0_msh_reg[8]_i_1_n_3\, - CYINIT => '0', - DI(3 downto 0) => B"0000", - O(3) => \sig_addr_cntr_im0_msh_reg[8]_i_1_n_4\, - O(2) => \sig_addr_cntr_im0_msh_reg[8]_i_1_n_5\, - O(1) => \sig_addr_cntr_im0_msh_reg[8]_i_1_n_6\, - O(0) => \sig_addr_cntr_im0_msh_reg[8]_i_1_n_7\, - S(3) => \sig_addr_cntr_im0_msh[8]_i_2_n_0\, - S(2) => \sig_addr_cntr_im0_msh[8]_i_3_n_0\, - S(1) => \sig_addr_cntr_im0_msh[8]_i_4_n_0\, - S(0) => \sig_addr_cntr_im0_msh[8]_i_5_n_0\ +\sig_btt_cntr_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \sig_btt_cntr[15]_i_1_n_0\, + D => \p_1_in__0\(1), + Q => sig_btt_residue_slice(1), + R => sig_init_reg ); -\sig_addr_cntr_im0_msh_reg[9]\: unisim.vcomponents.FDRE +\sig_btt_cntr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, - D => \sig_addr_cntr_im0_msh_reg[8]_i_1_n_6\, - Q => sig_addr_cntr_im0_msh_reg(9), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_btt_cntr[15]_i_1_n_0\, + D => \p_1_in__0\(2), + Q => sig_btt_residue_slice(2), + R => sig_init_reg ); -\sig_addr_cntr_incr_ireg2[0]_i_1\: unisim.vcomponents.LUT4 +\sig_btt_cntr_reg[3]\: unisim.vcomponents.FDRE generic map( - INIT => X"B888" + INIT => '0' ) port map ( - I0 => sig_btt_residue_slice_im0(0), - I1 => sig_btt_lt_b2mbaa_ireg1, - I2 => sig_first_xfer_im0, - I3 => sig_bytes_to_mbaa_ireg1(0), - O => \sig_addr_cntr_incr_ireg2[0]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_btt_cntr[15]_i_1_n_0\, + D => \p_1_in__0\(3), + Q => sig_btt_residue_slice(3), + R => sig_init_reg ); -\sig_addr_cntr_incr_ireg2[1]_i_1\: unisim.vcomponents.LUT4 +\sig_btt_cntr_reg[4]\: unisim.vcomponents.FDRE generic map( - INIT => X"B888" + INIT => '0' ) port map ( - I0 => sig_btt_residue_slice_im0(1), - I1 => sig_btt_lt_b2mbaa_ireg1, - I2 => sig_first_xfer_im0, - I3 => sig_bytes_to_mbaa_ireg1(1), - O => \sig_addr_cntr_incr_ireg2[1]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_btt_cntr[15]_i_1_n_0\, + D => \p_1_in__0\(4), + Q => sig_btt_residue_slice(4), + R => sig_init_reg ); -\sig_addr_cntr_incr_ireg2[2]_i_1\: unisim.vcomponents.LUT4 +\sig_btt_cntr_reg[5]\: unisim.vcomponents.FDRE generic map( - INIT => X"B888" + INIT => '0' ) port map ( - I0 => sig_btt_residue_slice_im0(2), - I1 => sig_btt_lt_b2mbaa_ireg1, - I2 => sig_first_xfer_im0, - I3 => sig_bytes_to_mbaa_ireg1(2), - O => \sig_addr_cntr_incr_ireg2[2]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_btt_cntr[15]_i_1_n_0\, + D => \p_1_in__0\(5), + Q => sig_btt_residue_slice(5), + R => sig_init_reg ); -\sig_addr_cntr_incr_ireg2[3]_i_1\: unisim.vcomponents.LUT4 +\sig_btt_cntr_reg[6]\: unisim.vcomponents.FDRE generic map( - INIT => X"B888" + INIT => '0' ) port map ( - I0 => sig_btt_residue_slice_im0(3), - I1 => sig_btt_lt_b2mbaa_ireg1, - I2 => sig_first_xfer_im0, - I3 => sig_bytes_to_mbaa_ireg1(3), - O => \sig_addr_cntr_incr_ireg2[3]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_btt_cntr[15]_i_1_n_0\, + D => \p_1_in__0\(6), + Q => sig_btt_residue_slice(6), + R => sig_init_reg ); -\sig_addr_cntr_incr_ireg2[4]_i_1\: unisim.vcomponents.LUT4 +\sig_btt_cntr_reg[7]\: unisim.vcomponents.FDRE generic map( - INIT => X"B888" + INIT => '0' ) port map ( - I0 => sig_btt_residue_slice_im0(4), - I1 => sig_btt_lt_b2mbaa_ireg1, - I2 => sig_first_xfer_im0, - I3 => sig_bytes_to_mbaa_ireg1(4), - O => \sig_addr_cntr_incr_ireg2[4]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_btt_cntr[15]_i_1_n_0\, + D => \p_1_in__0\(7), + Q => sig_btt_residue_slice(7), + R => sig_init_reg ); -\sig_addr_cntr_incr_ireg2[5]_i_1\: unisim.vcomponents.LUT4 +\sig_btt_cntr_reg[8]\: unisim.vcomponents.FDRE generic map( - INIT => X"B888" + INIT => '0' ) port map ( - I0 => sig_btt_residue_slice_im0(5), - I1 => sig_btt_lt_b2mbaa_ireg1, - I2 => sig_first_xfer_im0, - I3 => sig_bytes_to_mbaa_ireg1(5), - O => \sig_addr_cntr_incr_ireg2[5]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_btt_cntr[15]_i_1_n_0\, + D => \p_1_in__0\(8), + Q => sig_btt_residue_slice(8), + R => sig_init_reg ); -\sig_addr_cntr_incr_ireg2[6]_i_1\: unisim.vcomponents.LUT4 +\sig_btt_cntr_reg[9]\: unisim.vcomponents.FDRE generic map( - INIT => X"B888" + INIT => '0' ) port map ( - I0 => sig_btt_residue_slice_im0(6), - I1 => sig_btt_lt_b2mbaa_ireg1, - I2 => sig_first_xfer_im0, - I3 => sig_bytes_to_mbaa_ireg1(6), - O => \sig_addr_cntr_incr_ireg2[6]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_btt_cntr[15]_i_1_n_0\, + D => \p_1_in__0\(9), + Q => sel0(0), + R => sig_init_reg + ); +sig_btt_eq_b2mbaa2_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => NLW_sig_btt_eq_b2mbaa2_carry_CO_UNCONNECTED(3), + CO(2) => sig_btt_eq_b2mbaa2, + CO(1) => sig_btt_eq_b2mbaa2_carry_n_2, + CO(0) => sig_btt_eq_b2mbaa2_carry_n_3, + CYINIT => '1', + DI(3 downto 0) => B"0000", + O(3 downto 0) => NLW_sig_btt_eq_b2mbaa2_carry_O_UNCONNECTED(3 downto 0), + S(3) => '0', + S(2) => sig_btt_eq_b2mbaa2_carry_i_1_n_0, + S(1) => sig_btt_eq_b2mbaa2_carry_i_2_n_0, + S(0) => sig_btt_eq_b2mbaa2_carry_i_3_n_0 ); -\sig_addr_cntr_incr_ireg2[7]_i_1\: unisim.vcomponents.LUT3 +sig_btt_eq_b2mbaa2_carry_i_1: unisim.vcomponents.LUT6 generic map( - INIT => X"0D" + INIT => X"9009000000009009" ) port map ( - I0 => sig_first_xfer_im0, - I1 => sig_bytes_to_mbaa_ireg1(7), - I2 => sig_btt_lt_b2mbaa_ireg1, - O => \sig_addr_cntr_incr_ireg2[7]_i_1_n_0\ + I0 => sig_btt_residue_slice(6), + I1 => \sig_bytes_to_mbaa__8\(6), + I2 => sig_bytes_to_mbaa(8), + I3 => sig_btt_residue_slice(8), + I4 => \sig_bytes_to_mbaa__8\(7), + I5 => sig_btt_residue_slice(7), + O => sig_btt_eq_b2mbaa2_carry_i_1_n_0 ); -\sig_addr_cntr_incr_ireg2_reg[0]\: unisim.vcomponents.FDRE +sig_btt_eq_b2mbaa2_carry_i_2: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"9009000000009009" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc2_reg, - D => \sig_addr_cntr_incr_ireg2[0]_i_1_n_0\, - Q => sig_addr_cntr_incr_ireg2(0), - R => \^sig_init_reg\ + I0 => sig_btt_residue_slice(3), + I1 => \sig_bytes_to_mbaa__8\(3), + I2 => \sig_bytes_to_mbaa__8\(5), + I3 => sig_btt_residue_slice(5), + I4 => \sig_bytes_to_mbaa__8\(4), + I5 => sig_btt_residue_slice(4), + O => sig_btt_eq_b2mbaa2_carry_i_2_n_0 ); -\sig_addr_cntr_incr_ireg2_reg[1]\: unisim.vcomponents.FDRE +sig_btt_eq_b2mbaa2_carry_i_3: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"9009000000009009" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc2_reg, - D => \sig_addr_cntr_incr_ireg2[1]_i_1_n_0\, - Q => sig_addr_cntr_incr_ireg2(1), - R => \^sig_init_reg\ + I0 => sig_btt_residue_slice(0), + I1 => \sig_bytes_to_mbaa__8\(0), + I2 => \sig_bytes_to_mbaa__8\(2), + I3 => sig_btt_residue_slice(2), + I4 => \sig_bytes_to_mbaa__8\(1), + I5 => sig_btt_residue_slice(1), + O => sig_btt_eq_b2mbaa2_carry_i_3_n_0 ); -\sig_addr_cntr_incr_ireg2_reg[2]\: unisim.vcomponents.FDRE +sig_btt_eq_b2mbaa2_carry_i_4: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"2" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc2_reg, - D => \sig_addr_cntr_incr_ireg2[2]_i_1_n_0\, - Q => sig_addr_cntr_incr_ireg2(2), - R => \^sig_init_reg\ + I0 => sig_input_addr_reg(0), + I1 => \sig_addr_aligned__6\, + O => \sig_bytes_to_mbaa__8\(0) ); -\sig_addr_cntr_incr_ireg2_reg[3]\: unisim.vcomponents.FDRE +sig_btt_eq_b2mbaa2_carry_i_5: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"06" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc2_reg, - D => \sig_addr_cntr_incr_ireg2[3]_i_1_n_0\, - Q => sig_addr_cntr_incr_ireg2(3), - R => \^sig_init_reg\ + I0 => sig_input_addr_reg(1), + I1 => sig_input_addr_reg(0), + I2 => \sig_addr_aligned__6\, + O => \sig_bytes_to_mbaa__8\(1) ); -\sig_addr_cntr_incr_ireg2_reg[4]\: unisim.vcomponents.FDRE +sig_btt_lt_b2mbaa2_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => sig_btt_lt_b2mbaa2_carry_n_0, + CO(2) => sig_btt_lt_b2mbaa2_carry_n_1, + CO(1) => sig_btt_lt_b2mbaa2_carry_n_2, + CO(0) => sig_btt_lt_b2mbaa2_carry_n_3, + CYINIT => '0', + DI(3) => sig_btt_lt_b2mbaa2_carry_i_1_n_0, + DI(2) => sig_btt_lt_b2mbaa2_carry_i_2_n_0, + DI(1) => sig_btt_lt_b2mbaa2_carry_i_3_n_0, + DI(0) => sig_btt_lt_b2mbaa2_carry_i_4_n_0, + O(3 downto 0) => NLW_sig_btt_lt_b2mbaa2_carry_O_UNCONNECTED(3 downto 0), + S(3) => sig_btt_lt_b2mbaa2_carry_i_5_n_0, + S(2) => sig_btt_lt_b2mbaa2_carry_i_6_n_0, + S(1) => sig_btt_lt_b2mbaa2_carry_i_7_n_0, + S(0) => sig_btt_lt_b2mbaa2_carry_i_8_n_0 + ); +\sig_btt_lt_b2mbaa2_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => sig_btt_lt_b2mbaa2_carry_n_0, + CO(3 downto 1) => \NLW_sig_btt_lt_b2mbaa2_carry__0_CO_UNCONNECTED\(3 downto 1), + CO(0) => sig_btt_lt_b2mbaa2, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => \sig_btt_lt_b2mbaa2_carry__0_i_1_n_0\, + O(3 downto 0) => \NLW_sig_btt_lt_b2mbaa2_carry__0_O_UNCONNECTED\(3 downto 0), + S(3 downto 1) => B"000", + S(0) => \sig_btt_lt_b2mbaa2_carry__0_i_2_n_0\ + ); +\sig_btt_lt_b2mbaa2_carry__0_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"2" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc2_reg, - D => \sig_addr_cntr_incr_ireg2[4]_i_1_n_0\, - Q => sig_addr_cntr_incr_ireg2(4), - R => \^sig_init_reg\ + I0 => sig_bytes_to_mbaa(8), + I1 => sig_btt_residue_slice(8), + O => \sig_btt_lt_b2mbaa2_carry__0_i_1_n_0\ ); -\sig_addr_cntr_incr_ireg2_reg[5]\: unisim.vcomponents.FDRE +\sig_btt_lt_b2mbaa2_carry__0_i_2\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"9" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc2_reg, - D => \sig_addr_cntr_incr_ireg2[5]_i_1_n_0\, - Q => sig_addr_cntr_incr_ireg2(5), - R => \^sig_init_reg\ + I0 => sig_btt_residue_slice(8), + I1 => sig_bytes_to_mbaa(8), + O => \sig_btt_lt_b2mbaa2_carry__0_i_2_n_0\ ); -\sig_addr_cntr_incr_ireg2_reg[6]\: unisim.vcomponents.FDRE +sig_btt_lt_b2mbaa2_carry_i_1: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"0000000017033017" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc2_reg, - D => \sig_addr_cntr_incr_ireg2[6]_i_1_n_0\, - Q => sig_addr_cntr_incr_ireg2(6), - R => \^sig_init_reg\ + I0 => sig_btt_residue_slice(6), + I1 => sig_btt_residue_slice(7), + I2 => sig_input_addr_reg(7), + I3 => sig_btt_lt_b2mbaa2_carry_i_9_n_0, + I4 => sig_input_addr_reg(6), + I5 => \sig_addr_aligned__6\, + O => sig_btt_lt_b2mbaa2_carry_i_1_n_0 ); -\sig_addr_cntr_incr_ireg2_reg[7]\: unisim.vcomponents.FDRE +sig_btt_lt_b2mbaa2_carry_i_10: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"0001" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc2_reg, - D => \sig_addr_cntr_incr_ireg2[7]_i_1_n_0\, - Q => sig_addr_cntr_incr_ireg2(7), - R => \^sig_init_reg\ + I0 => sig_input_addr_reg(2), + I1 => sig_input_addr_reg(0), + I2 => sig_input_addr_reg(1), + I3 => sig_input_addr_reg(3), + O => sig_btt_lt_b2mbaa2_carry_i_10_n_0 ); -\sig_addr_cntr_lsh_im0[0]_i_1\: unisim.vcomponents.LUT6 +sig_btt_lt_b2mbaa2_carry_i_11: unisim.vcomponents.LUT4 generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => X"0056" ) port map ( - I0 => \out\(18), - I1 => \sig_predict_addr_lsh_ireg3_reg_n_0_[0]\, - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => p_1_in(0) + I0 => sig_input_addr_reg(2), + I1 => sig_input_addr_reg(0), + I2 => sig_input_addr_reg(1), + I3 => \sig_addr_aligned__6\, + O => \sig_bytes_to_mbaa__8\(2) ); -\sig_addr_cntr_lsh_im0[10]_i_1\: unisim.vcomponents.LUT6 +sig_btt_lt_b2mbaa2_carry_i_2: unisim.vcomponents.LUT6 generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => X"0000000017033017" ) port map ( - I0 => \out\(28), - I1 => \sig_predict_addr_lsh_ireg3_reg_n_0_[10]\, - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => p_1_in(10) + I0 => sig_btt_residue_slice(4), + I1 => sig_btt_residue_slice(5), + I2 => sig_input_addr_reg(5), + I3 => sig_btt_lt_b2mbaa2_carry_i_10_n_0, + I4 => sig_input_addr_reg(4), + I5 => \sig_addr_aligned__6\, + O => sig_btt_lt_b2mbaa2_carry_i_2_n_0 ); -\sig_addr_cntr_lsh_im0[11]_i_1\: unisim.vcomponents.LUT6 +sig_btt_lt_b2mbaa2_carry_i_3: unisim.vcomponents.LUT4 generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => X"2F02" ) port map ( - I0 => \out\(29), - I1 => \sig_predict_addr_lsh_ireg3_reg_n_0_[11]\, - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => p_1_in(11) + I0 => \sig_bytes_to_mbaa__8\(2), + I1 => sig_btt_residue_slice(2), + I2 => sig_btt_residue_slice(3), + I3 => \sig_bytes_to_mbaa__8\(3), + O => sig_btt_lt_b2mbaa2_carry_i_3_n_0 ); -\sig_addr_cntr_lsh_im0[12]_i_1\: unisim.vcomponents.LUT6 +sig_btt_lt_b2mbaa2_carry_i_4: unisim.vcomponents.LUT5 generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => X"00001730" ) port map ( - I0 => \out\(30), - I1 => \sig_predict_addr_lsh_ireg3_reg_n_0_[12]\, - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => p_1_in(12) + I0 => sig_btt_residue_slice(0), + I1 => sig_btt_residue_slice(1), + I2 => sig_input_addr_reg(1), + I3 => sig_input_addr_reg(0), + I4 => \sig_addr_aligned__6\, + O => sig_btt_lt_b2mbaa2_carry_i_4_n_0 ); -\sig_addr_cntr_lsh_im0[13]_i_1\: unisim.vcomponents.LUT6 +sig_btt_lt_b2mbaa2_carry_i_5: unisim.vcomponents.LUT6 generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => X"0000214255558418" ) port map ( - I0 => \out\(31), - I1 => \sig_predict_addr_lsh_ireg3_reg_n_0_[13]\, - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => p_1_in(13) + I0 => sig_btt_residue_slice(6), + I1 => sig_input_addr_reg(7), + I2 => sig_btt_lt_b2mbaa2_carry_i_9_n_0, + I3 => sig_input_addr_reg(6), + I4 => \sig_addr_aligned__6\, + I5 => sig_btt_residue_slice(7), + O => sig_btt_lt_b2mbaa2_carry_i_5_n_0 ); -\sig_addr_cntr_lsh_im0[14]_i_1\: unisim.vcomponents.LUT6 +sig_btt_lt_b2mbaa2_carry_i_6: unisim.vcomponents.LUT6 generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => X"0000214255558418" ) port map ( - I0 => \out\(32), - I1 => \sig_predict_addr_lsh_ireg3_reg_n_0_[14]\, - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => p_1_in(14) + I0 => sig_btt_residue_slice(4), + I1 => sig_input_addr_reg(5), + I2 => sig_btt_lt_b2mbaa2_carry_i_10_n_0, + I3 => sig_input_addr_reg(4), + I4 => \sig_addr_aligned__6\, + I5 => sig_btt_residue_slice(5), + O => sig_btt_lt_b2mbaa2_carry_i_6_n_0 ); -\sig_addr_cntr_lsh_im0[15]_i_1\: unisim.vcomponents.LUT5 +sig_btt_lt_b2mbaa2_carry_i_7: unisim.vcomponents.LUT4 generic map( - INIT => X"FFFF0010" + INIT => X"9009" ) port map ( - I0 => Q(0), - I1 => \^sig_sm_halt_reg\, - I2 => \^sig_input_reg_empty\, - I3 => \^in\(37), - I4 => sig_pop_xfer_reg0_out, - O => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\ + I0 => \sig_bytes_to_mbaa__8\(2), + I1 => sig_btt_residue_slice(2), + I2 => \sig_bytes_to_mbaa__8\(3), + I3 => sig_btt_residue_slice(3), + O => sig_btt_lt_b2mbaa2_carry_i_7_n_0 ); -\sig_addr_cntr_lsh_im0[15]_i_2\: unisim.vcomponents.LUT6 +sig_btt_lt_b2mbaa2_carry_i_8: unisim.vcomponents.LUT5 generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => X"00245581" ) port map ( - I0 => \out\(33), - I1 => sig_predict_addr_lsh_ireg3(15), - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => p_1_in(15) + I0 => sig_btt_residue_slice(0), + I1 => sig_input_addr_reg(1), + I2 => sig_input_addr_reg(0), + I3 => \sig_addr_aligned__6\, + I4 => sig_btt_residue_slice(1), + O => sig_btt_lt_b2mbaa2_carry_i_8_n_0 ); -\sig_addr_cntr_lsh_im0[1]_i_1\: unisim.vcomponents.LUT6 +sig_btt_lt_b2mbaa2_carry_i_9: unisim.vcomponents.LUT6 generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => X"0000000000000001" ) port map ( - I0 => \out\(19), - I1 => \sig_predict_addr_lsh_ireg3_reg_n_0_[1]\, - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => p_1_in(1) + I0 => sig_input_addr_reg(4), + I1 => sig_input_addr_reg(2), + I2 => sig_input_addr_reg(0), + I3 => sig_input_addr_reg(1), + I4 => sig_input_addr_reg(3), + I5 => sig_input_addr_reg(5), + O => sig_btt_lt_b2mbaa2_carry_i_9_n_0 ); -\sig_addr_cntr_lsh_im0[2]_i_1\: unisim.vcomponents.LUT6 +sig_byte_change_minus1_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => sig_byte_change_minus1_carry_n_0, + CO(2) => sig_byte_change_minus1_carry_n_1, + CO(1) => sig_byte_change_minus1_carry_n_2, + CO(0) => sig_byte_change_minus1_carry_n_3, + CYINIT => '0', + DI(3) => '0', + DI(2 downto 0) => \gpr1.dout_i_reg[9]\(2 downto 0), + O(3 downto 0) => \^sig_adjusted_addr_incr\(3 downto 0), + S(3 downto 0) => S(3 downto 0) + ); +\sig_byte_change_minus1_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => sig_byte_change_minus1_carry_n_0, + CO(3) => \sig_byte_change_minus1_carry__0_n_0\, + CO(2) => \sig_byte_change_minus1_carry__0_n_1\, + CO(1) => \sig_byte_change_minus1_carry__0_n_2\, + CO(0) => \sig_byte_change_minus1_carry__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => \^sig_adjusted_addr_incr\(7 downto 4), + S(3 downto 0) => \gpr1.dout_i_reg[7]_0\(3 downto 0) + ); +\sig_byte_change_minus1_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \sig_byte_change_minus1_carry__0_n_0\, + CO(3 downto 0) => \NLW_sig_byte_change_minus1_carry__1_CO_UNCONNECTED\(3 downto 0), + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 1) => \NLW_sig_byte_change_minus1_carry__1_O_UNCONNECTED\(3 downto 1), + O(0) => \^sig_adjusted_addr_incr\(8), + S(3 downto 1) => B"000", + S(0) => \gpr1.dout_i_reg[8]\(0) + ); +sig_calc_error_reg_reg: unisim.vcomponents.FDRE generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => '0' ) port map ( - I0 => \out\(20), - I1 => \sig_predict_addr_lsh_ireg3_reg_n_0_[2]\, - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => p_1_in(2) + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_psm_halt_reg_0, + Q => \^p_10_out\, + R => sig_init_reg ); -\sig_addr_cntr_lsh_im0[3]_i_1\: unisim.vcomponents.LUT6 +\sig_child_addr_cntr_lsh[0]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => X"EA" ) port map ( - I0 => \out\(21), - I1 => \sig_predict_addr_lsh_ireg3_reg_n_0_[3]\, - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => p_1_in(3) + I0 => \^sig_csm_pop_child_cmd\, + I1 => sig_csm_ld_xfer, + I2 => sig_child_qual_burst_type, + O => \sig_child_addr_cntr_lsh[0]_i_1_n_0\ ); -\sig_addr_cntr_lsh_im0[4]_i_1\: unisim.vcomponents.LUT6 +\sig_child_addr_cntr_lsh[0]_i_10\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => X"F606" ) port map ( - I0 => \out\(22), - I1 => \sig_predict_addr_lsh_ireg3_reg_n_0_[4]\, - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => p_1_in(4) + I0 => \gpr1.dout_i_reg[9]\(0), + I1 => \^sig_xfer_addr_reg_reg[2]_0\(0), + I2 => \^sig_csm_pop_child_cmd\, + I3 => \sig_child_addr_reg_reg_n_0_[0]\, + O => \sig_child_addr_cntr_lsh_reg[3]_0\(0) ); -\sig_addr_cntr_lsh_im0[5]_i_1\: unisim.vcomponents.LUT6 +\sig_child_addr_cntr_lsh[0]_i_7\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => X"F606" ) port map ( - I0 => \out\(23), - I1 => \sig_predict_addr_lsh_ireg3_reg_n_0_[5]\, - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => p_1_in(5) + I0 => \gpr1.dout_i_reg[9]\(3), + I1 => sig_child_addr_cntr_lsh_reg(3), + I2 => \^sig_csm_pop_child_cmd\, + I3 => \sig_child_addr_reg_reg_n_0_[3]\, + O => \sig_child_addr_cntr_lsh_reg[3]_0\(3) ); -\sig_addr_cntr_lsh_im0[6]_i_1\: unisim.vcomponents.LUT6 +\sig_child_addr_cntr_lsh[0]_i_8\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => X"F606" ) port map ( - I0 => \out\(24), - I1 => \sig_predict_addr_lsh_ireg3_reg_n_0_[6]\, - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => p_1_in(6) + I0 => \gpr1.dout_i_reg[9]\(2), + I1 => \^sig_xfer_addr_reg_reg[2]_0\(2), + I2 => \^sig_csm_pop_child_cmd\, + I3 => \sig_child_addr_reg_reg_n_0_[2]\, + O => \sig_child_addr_cntr_lsh_reg[3]_0\(2) ); -\sig_addr_cntr_lsh_im0[7]_i_1\: unisim.vcomponents.LUT6 +\sig_child_addr_cntr_lsh[0]_i_9\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => X"F606" ) port map ( - I0 => \out\(25), - I1 => \sig_predict_addr_lsh_ireg3_reg_n_0_[7]\, - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => p_1_in(7) + I0 => \gpr1.dout_i_reg[9]\(1), + I1 => \^sig_xfer_addr_reg_reg[2]_0\(1), + I2 => \^sig_csm_pop_child_cmd\, + I3 => \sig_child_addr_reg_reg_n_0_[1]\, + O => \sig_child_addr_cntr_lsh_reg[3]_0\(1) ); -\sig_addr_cntr_lsh_im0[8]_i_1\: unisim.vcomponents.LUT6 +\sig_child_addr_cntr_lsh[12]_i_2\: unisim.vcomponents.LUT3 generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => X"B8" ) port map ( - I0 => \out\(26), - I1 => \sig_predict_addr_lsh_ireg3_reg_n_0_[8]\, - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => p_1_in(8) + I0 => \sig_child_addr_reg_reg_n_0_[15]\, + I1 => \^sig_csm_pop_child_cmd\, + I2 => p_1_in, + O => \sig_child_addr_cntr_lsh[12]_i_2_n_0\ ); -\sig_addr_cntr_lsh_im0[9]_i_1\: unisim.vcomponents.LUT6 +\sig_child_addr_cntr_lsh[12]_i_3\: unisim.vcomponents.LUT3 generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => X"B8" ) port map ( - I0 => \out\(27), - I1 => \sig_predict_addr_lsh_ireg3_reg_n_0_[9]\, - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => p_1_in(9) + I0 => \sig_child_addr_reg_reg_n_0_[14]\, + I1 => \^sig_csm_pop_child_cmd\, + I2 => sig_child_addr_cntr_lsh_reg(14), + O => \sig_child_addr_cntr_lsh[12]_i_3_n_0\ ); -\sig_addr_cntr_lsh_im0_reg[0]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_lsh[12]_i_4\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => p_1_in(0), - Q => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, - R => \^sig_init_reg\ + I0 => \sig_child_addr_reg_reg_n_0_[13]\, + I1 => \^sig_csm_pop_child_cmd\, + I2 => sig_child_addr_cntr_lsh_reg(13), + O => \sig_child_addr_cntr_lsh[12]_i_4_n_0\ ); -\sig_addr_cntr_lsh_im0_reg[10]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_lsh[12]_i_5\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => p_1_in(10), - Q => \sig_addr_cntr_lsh_im0_reg_n_0_[10]\, - R => \^sig_init_reg\ + I0 => \sig_child_addr_reg_reg_n_0_[12]\, + I1 => \^sig_csm_pop_child_cmd\, + I2 => sig_child_addr_cntr_lsh_reg(12), + O => \sig_child_addr_cntr_lsh[12]_i_5_n_0\ ); -\sig_addr_cntr_lsh_im0_reg[11]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_lsh[4]_i_6\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"F606" ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => p_1_in(11), - Q => \sig_addr_cntr_lsh_im0_reg_n_0_[11]\, - R => \^sig_init_reg\ + I0 => \gpr1.dout_i_reg[9]\(7), + I1 => sig_child_addr_cntr_lsh_reg(7), + I2 => \^sig_csm_pop_child_cmd\, + I3 => \sig_child_addr_reg_reg_n_0_[7]\, + O => \sig_child_addr_cntr_lsh_reg[7]_0\(3) ); -\sig_addr_cntr_lsh_im0_reg[12]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_lsh[4]_i_7\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"F606" ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => p_1_in(12), - Q => \sig_addr_cntr_lsh_im0_reg_n_0_[12]\, - R => \^sig_init_reg\ + I0 => \gpr1.dout_i_reg[9]\(6), + I1 => sig_child_addr_cntr_lsh_reg(6), + I2 => \^sig_csm_pop_child_cmd\, + I3 => \sig_child_addr_reg_reg_n_0_[6]\, + O => \sig_child_addr_cntr_lsh_reg[7]_0\(2) ); -\sig_addr_cntr_lsh_im0_reg[13]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_lsh[4]_i_8\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"F606" ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => p_1_in(13), - Q => \sig_addr_cntr_lsh_im0_reg_n_0_[13]\, - R => \^sig_init_reg\ + I0 => \gpr1.dout_i_reg[9]\(5), + I1 => sig_child_addr_cntr_lsh_reg(5), + I2 => \^sig_csm_pop_child_cmd\, + I3 => \sig_child_addr_reg_reg_n_0_[5]\, + O => \sig_child_addr_cntr_lsh_reg[7]_0\(1) ); -\sig_addr_cntr_lsh_im0_reg[14]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_lsh[4]_i_9\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"F606" ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => p_1_in(14), - Q => \sig_addr_cntr_lsh_im0_reg_n_0_[14]\, - R => \^sig_init_reg\ + I0 => \gpr1.dout_i_reg[9]\(4), + I1 => sig_child_addr_cntr_lsh_reg(4), + I2 => \^sig_csm_pop_child_cmd\, + I3 => \sig_child_addr_reg_reg_n_0_[4]\, + O => \sig_child_addr_cntr_lsh_reg[7]_0\(0) ); -\sig_addr_cntr_lsh_im0_reg[15]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_lsh[8]_i_3\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => p_1_in(15), - Q => p_1_in_0, - R => \^sig_init_reg\ + I0 => \sig_child_addr_reg_reg_n_0_[11]\, + I1 => \^sig_csm_pop_child_cmd\, + I2 => sig_child_addr_cntr_lsh_reg(11), + O => \sig_child_addr_cntr_lsh[8]_i_3_n_0\ ); -\sig_addr_cntr_lsh_im0_reg[1]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_lsh[8]_i_4\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => p_1_in(1), - Q => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, - R => \^sig_init_reg\ + I0 => \sig_child_addr_reg_reg_n_0_[10]\, + I1 => \^sig_csm_pop_child_cmd\, + I2 => sig_child_addr_cntr_lsh_reg(10), + O => \sig_child_addr_cntr_lsh[8]_i_4_n_0\ ); -\sig_addr_cntr_lsh_im0_reg[2]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_lsh[8]_i_5\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => p_1_in(2), - Q => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, - R => \^sig_init_reg\ + I0 => \sig_child_addr_reg_reg_n_0_[9]\, + I1 => \^sig_csm_pop_child_cmd\, + I2 => sig_child_addr_cntr_lsh_reg(9), + O => \sig_child_addr_cntr_lsh[8]_i_5_n_0\ ); -\sig_addr_cntr_lsh_im0_reg[3]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_lsh[8]_i_6\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"F606" ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => p_1_in(3), - Q => \sig_addr_cntr_lsh_im0_reg_n_0_[3]\, - R => \^sig_init_reg\ + I0 => \gpr1.dout_i_reg[9]\(8), + I1 => sig_child_addr_cntr_lsh_reg(8), + I2 => \^sig_csm_pop_child_cmd\, + I3 => \sig_child_addr_reg_reg_n_0_[8]\, + O => \sig_child_addr_cntr_lsh[8]_i_6_n_0\ ); -\sig_addr_cntr_lsh_im0_reg[4]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_lsh_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => p_1_in(4), - Q => \sig_addr_cntr_lsh_im0_reg_n_0_[4]\, - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_lsh[0]_i_1_n_0\, + D => O(0), + Q => \^sig_xfer_addr_reg_reg[2]_0\(0), + R => sig_init_reg ); -\sig_addr_cntr_lsh_im0_reg[5]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_lsh_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => p_1_in(5), - Q => \sig_addr_cntr_lsh_im0_reg_n_0_[5]\, - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_lsh[0]_i_1_n_0\, + D => \sig_child_addr_cntr_lsh_reg[8]_i_1_n_5\, + Q => sig_child_addr_cntr_lsh_reg(10), + R => sig_init_reg ); -\sig_addr_cntr_lsh_im0_reg[6]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_lsh_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => p_1_in(6), - Q => \sig_addr_cntr_lsh_im0_reg_n_0_[6]\, - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_lsh[0]_i_1_n_0\, + D => \sig_child_addr_cntr_lsh_reg[8]_i_1_n_4\, + Q => sig_child_addr_cntr_lsh_reg(11), + R => sig_init_reg ); -\sig_addr_cntr_lsh_im0_reg[7]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_lsh_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => p_1_in(7), - Q => \sig_addr_cntr_lsh_im0_reg_n_0_[7]\, - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_lsh[0]_i_1_n_0\, + D => \sig_child_addr_cntr_lsh_reg[12]_i_1_n_7\, + Q => sig_child_addr_cntr_lsh_reg(12), + R => sig_init_reg ); -\sig_addr_cntr_lsh_im0_reg[8]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_lsh_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \sig_child_addr_cntr_lsh_reg[8]_i_1_n_0\, + CO(3) => \NLW_sig_child_addr_cntr_lsh_reg[12]_i_1_CO_UNCONNECTED\(3), + CO(2) => \sig_child_addr_cntr_lsh_reg[12]_i_1_n_1\, + CO(1) => \sig_child_addr_cntr_lsh_reg[12]_i_1_n_2\, + CO(0) => \sig_child_addr_cntr_lsh_reg[12]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \sig_child_addr_cntr_lsh_reg[12]_i_1_n_4\, + O(2) => \sig_child_addr_cntr_lsh_reg[12]_i_1_n_5\, + O(1) => \sig_child_addr_cntr_lsh_reg[12]_i_1_n_6\, + O(0) => \sig_child_addr_cntr_lsh_reg[12]_i_1_n_7\, + S(3) => \sig_child_addr_cntr_lsh[12]_i_2_n_0\, + S(2) => \sig_child_addr_cntr_lsh[12]_i_3_n_0\, + S(1) => \sig_child_addr_cntr_lsh[12]_i_4_n_0\, + S(0) => \sig_child_addr_cntr_lsh[12]_i_5_n_0\ + ); +\sig_child_addr_cntr_lsh_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => p_1_in(8), - Q => \sig_addr_cntr_lsh_im0_reg_n_0_[8]\, - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_lsh[0]_i_1_n_0\, + D => \sig_child_addr_cntr_lsh_reg[12]_i_1_n_6\, + Q => sig_child_addr_cntr_lsh_reg(13), + R => sig_init_reg ); -\sig_addr_cntr_lsh_im0_reg[9]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_lsh_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => p_1_in(9), - Q => \sig_addr_cntr_lsh_im0_reg_n_0_[9]\, - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_lsh[0]_i_1_n_0\, + D => \sig_child_addr_cntr_lsh_reg[12]_i_1_n_5\, + Q => sig_child_addr_cntr_lsh_reg(14), + R => sig_init_reg ); -\sig_addr_cntr_lsh_kh_reg[0]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_lsh_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(18), - Q => sig_addr_cntr_lsh_kh(0), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_lsh[0]_i_1_n_0\, + D => \sig_child_addr_cntr_lsh_reg[12]_i_1_n_4\, + Q => p_1_in, + R => sig_init_reg ); -\sig_addr_cntr_lsh_kh_reg[10]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_lsh_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(28), - Q => sig_addr_cntr_lsh_kh(10), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_lsh[0]_i_1_n_0\, + D => O(1), + Q => \^sig_xfer_addr_reg_reg[2]_0\(1), + R => sig_init_reg ); -\sig_addr_cntr_lsh_kh_reg[11]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_lsh_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(29), - Q => sig_addr_cntr_lsh_kh(11), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_lsh[0]_i_1_n_0\, + D => O(2), + Q => \^sig_xfer_addr_reg_reg[2]_0\(2), + R => sig_init_reg ); -\sig_addr_cntr_lsh_kh_reg[12]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_lsh_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(30), - Q => sig_addr_cntr_lsh_kh(12), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_lsh[0]_i_1_n_0\, + D => O(3), + Q => sig_child_addr_cntr_lsh_reg(3), + R => sig_init_reg ); -\sig_addr_cntr_lsh_kh_reg[13]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_lsh_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(31), - Q => sig_addr_cntr_lsh_kh(13), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_lsh[0]_i_1_n_0\, + D => \gpr1.dout_i_reg[7]\(0), + Q => sig_child_addr_cntr_lsh_reg(4), + R => sig_init_reg ); -\sig_addr_cntr_lsh_kh_reg[14]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_lsh_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(32), - Q => sig_addr_cntr_lsh_kh(14), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_lsh[0]_i_1_n_0\, + D => \gpr1.dout_i_reg[7]\(1), + Q => sig_child_addr_cntr_lsh_reg(5), + R => sig_init_reg ); -\sig_addr_cntr_lsh_kh_reg[15]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_lsh_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(33), - Q => sig_addr_cntr_lsh_kh(15), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_lsh[0]_i_1_n_0\, + D => \gpr1.dout_i_reg[7]\(2), + Q => sig_child_addr_cntr_lsh_reg(6), + R => sig_init_reg ); -\sig_addr_cntr_lsh_kh_reg[16]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_lsh_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(34), - Q => sig_addr_cntr_lsh_kh(16), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_lsh[0]_i_1_n_0\, + D => \gpr1.dout_i_reg[7]\(3), + Q => sig_child_addr_cntr_lsh_reg(7), + R => sig_init_reg ); -\sig_addr_cntr_lsh_kh_reg[17]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_lsh_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(35), - Q => sig_addr_cntr_lsh_kh(17), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_lsh[0]_i_1_n_0\, + D => \sig_child_addr_cntr_lsh_reg[8]_i_1_n_7\, + Q => sig_child_addr_cntr_lsh_reg(8), + R => sig_init_reg ); -\sig_addr_cntr_lsh_kh_reg[18]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_lsh_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => CO(0), + CO(3) => \sig_child_addr_cntr_lsh_reg[8]_i_1_n_0\, + CO(2) => \sig_child_addr_cntr_lsh_reg[8]_i_1_n_1\, + CO(1) => \sig_child_addr_cntr_lsh_reg[8]_i_1_n_2\, + CO(0) => \sig_child_addr_cntr_lsh_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => \gpr1.dout_i_reg[8]_0\(0), + O(3) => \sig_child_addr_cntr_lsh_reg[8]_i_1_n_4\, + O(2) => \sig_child_addr_cntr_lsh_reg[8]_i_1_n_5\, + O(1) => \sig_child_addr_cntr_lsh_reg[8]_i_1_n_6\, + O(0) => \sig_child_addr_cntr_lsh_reg[8]_i_1_n_7\, + S(3) => \sig_child_addr_cntr_lsh[8]_i_3_n_0\, + S(2) => \sig_child_addr_cntr_lsh[8]_i_4_n_0\, + S(1) => \sig_child_addr_cntr_lsh[8]_i_5_n_0\, + S(0) => \sig_child_addr_cntr_lsh[8]_i_6_n_0\ + ); +\sig_child_addr_cntr_lsh_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(36), - Q => sig_addr_cntr_lsh_kh(18), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_lsh[0]_i_1_n_0\, + D => \sig_child_addr_cntr_lsh_reg[8]_i_1_n_6\, + Q => sig_child_addr_cntr_lsh_reg(9), + R => sig_init_reg ); -\sig_addr_cntr_lsh_kh_reg[19]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_msh[0]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"EAAA" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(37), - Q => sig_addr_cntr_lsh_kh(19), - R => \^sig_init_reg\ + I0 => \^sig_csm_pop_child_cmd\, + I1 => sig_child_qual_burst_type, + I2 => sig_csm_ld_xfer, + I3 => sig_child_addr_lsh_rollover_reg, + O => \sig_child_addr_cntr_msh[0]_i_1_n_0\ ); -\sig_addr_cntr_lsh_kh_reg[1]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_msh[0]_i_3\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(19), - Q => sig_addr_cntr_lsh_kh(1), - R => \^sig_init_reg\ + I0 => data(0), + I1 => \^sig_csm_pop_child_cmd\, + I2 => sig_child_addr_cntr_msh_reg(0), + O => \sig_child_addr_cntr_msh[0]_i_3_n_0\ ); -\sig_addr_cntr_lsh_kh_reg[20]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_msh[0]_i_4\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(38), - Q => sig_addr_cntr_lsh_kh(20), - R => \^sig_init_reg\ + I0 => data(3), + I1 => \^sig_csm_pop_child_cmd\, + I2 => sig_child_addr_cntr_msh_reg(3), + O => \sig_child_addr_cntr_msh[0]_i_4_n_0\ ); -\sig_addr_cntr_lsh_kh_reg[21]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_msh[0]_i_5\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(39), - Q => sig_addr_cntr_lsh_kh(21), - R => \^sig_init_reg\ + I0 => data(2), + I1 => \^sig_csm_pop_child_cmd\, + I2 => sig_child_addr_cntr_msh_reg(2), + O => \sig_child_addr_cntr_msh[0]_i_5_n_0\ ); -\sig_addr_cntr_lsh_kh_reg[22]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_msh[0]_i_6\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(40), - Q => sig_addr_cntr_lsh_kh(22), - R => \^sig_init_reg\ + I0 => data(1), + I1 => \^sig_csm_pop_child_cmd\, + I2 => sig_child_addr_cntr_msh_reg(1), + O => \sig_child_addr_cntr_msh[0]_i_6_n_0\ ); -\sig_addr_cntr_lsh_kh_reg[23]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_msh[0]_i_7\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"C5" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(41), - Q => sig_addr_cntr_lsh_kh(23), - R => \^sig_init_reg\ + I0 => sig_child_addr_cntr_msh_reg(0), + I1 => data(0), + I2 => \^sig_csm_pop_child_cmd\, + O => \sig_child_addr_cntr_msh[0]_i_7_n_0\ ); -\sig_addr_cntr_lsh_kh_reg[24]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_msh[12]_i_2\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(42), - Q => sig_addr_cntr_lsh_kh(24), - R => \^sig_init_reg\ + I0 => data(15), + I1 => \^sig_csm_pop_child_cmd\, + I2 => sig_child_addr_cntr_msh_reg(15), + O => \sig_child_addr_cntr_msh[12]_i_2_n_0\ ); -\sig_addr_cntr_lsh_kh_reg[25]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_msh[12]_i_3\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(43), - Q => sig_addr_cntr_lsh_kh(25), - R => \^sig_init_reg\ + I0 => data(14), + I1 => \^sig_csm_pop_child_cmd\, + I2 => sig_child_addr_cntr_msh_reg(14), + O => \sig_child_addr_cntr_msh[12]_i_3_n_0\ ); -\sig_addr_cntr_lsh_kh_reg[26]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_msh[12]_i_4\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(44), - Q => sig_addr_cntr_lsh_kh(26), - R => \^sig_init_reg\ + I0 => data(13), + I1 => \^sig_csm_pop_child_cmd\, + I2 => sig_child_addr_cntr_msh_reg(13), + O => \sig_child_addr_cntr_msh[12]_i_4_n_0\ ); -\sig_addr_cntr_lsh_kh_reg[27]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_msh[12]_i_5\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(45), - Q => sig_addr_cntr_lsh_kh(27), - R => \^sig_init_reg\ + I0 => data(12), + I1 => \^sig_csm_pop_child_cmd\, + I2 => sig_child_addr_cntr_msh_reg(12), + O => \sig_child_addr_cntr_msh[12]_i_5_n_0\ ); -\sig_addr_cntr_lsh_kh_reg[28]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_msh[4]_i_2\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(46), - Q => sig_addr_cntr_lsh_kh(28), - R => \^sig_init_reg\ + I0 => data(7), + I1 => \^sig_csm_pop_child_cmd\, + I2 => sig_child_addr_cntr_msh_reg(7), + O => \sig_child_addr_cntr_msh[4]_i_2_n_0\ ); -\sig_addr_cntr_lsh_kh_reg[29]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_msh[4]_i_3\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(47), - Q => sig_addr_cntr_lsh_kh(29), - R => \^sig_init_reg\ + I0 => data(6), + I1 => \^sig_csm_pop_child_cmd\, + I2 => sig_child_addr_cntr_msh_reg(6), + O => \sig_child_addr_cntr_msh[4]_i_3_n_0\ ); -\sig_addr_cntr_lsh_kh_reg[2]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_msh[4]_i_4\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(20), - Q => sig_addr_cntr_lsh_kh(2), - R => \^sig_init_reg\ + I0 => data(5), + I1 => \^sig_csm_pop_child_cmd\, + I2 => sig_child_addr_cntr_msh_reg(5), + O => \sig_child_addr_cntr_msh[4]_i_4_n_0\ ); -\sig_addr_cntr_lsh_kh_reg[30]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_msh[4]_i_5\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(48), - Q => sig_addr_cntr_lsh_kh(30), - R => \^sig_init_reg\ + I0 => data(4), + I1 => \^sig_csm_pop_child_cmd\, + I2 => sig_child_addr_cntr_msh_reg(4), + O => \sig_child_addr_cntr_msh[4]_i_5_n_0\ ); -\sig_addr_cntr_lsh_kh_reg[31]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_msh[8]_i_2\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(49), - Q => sig_addr_cntr_lsh_kh(31), - R => \^sig_init_reg\ + I0 => data(11), + I1 => \^sig_csm_pop_child_cmd\, + I2 => sig_child_addr_cntr_msh_reg(11), + O => \sig_child_addr_cntr_msh[8]_i_2_n_0\ ); -\sig_addr_cntr_lsh_kh_reg[3]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_msh[8]_i_3\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(21), - Q => sig_addr_cntr_lsh_kh(3), - R => \^sig_init_reg\ + I0 => data(10), + I1 => \^sig_csm_pop_child_cmd\, + I2 => sig_child_addr_cntr_msh_reg(10), + O => \sig_child_addr_cntr_msh[8]_i_3_n_0\ ); -\sig_addr_cntr_lsh_kh_reg[4]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_msh[8]_i_4\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(22), - Q => sig_addr_cntr_lsh_kh(4), - R => \^sig_init_reg\ + I0 => data(9), + I1 => \^sig_csm_pop_child_cmd\, + I2 => sig_child_addr_cntr_msh_reg(9), + O => \sig_child_addr_cntr_msh[8]_i_4_n_0\ ); -\sig_addr_cntr_lsh_kh_reg[5]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_msh[8]_i_5\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(23), - Q => sig_addr_cntr_lsh_kh(5), - R => \^sig_init_reg\ + I0 => data(8), + I1 => \^sig_csm_pop_child_cmd\, + I2 => sig_child_addr_cntr_msh_reg(8), + O => \sig_child_addr_cntr_msh[8]_i_5_n_0\ ); -\sig_addr_cntr_lsh_kh_reg[6]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_msh_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(24), - Q => sig_addr_cntr_lsh_kh(6), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_msh[0]_i_1_n_0\, + D => \sig_child_addr_cntr_msh_reg[0]_i_2_n_7\, + Q => sig_child_addr_cntr_msh_reg(0), + R => sig_init_reg ); -\sig_addr_cntr_lsh_kh_reg[7]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_msh_reg[0]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \sig_child_addr_cntr_msh_reg[0]_i_2_n_0\, + CO(2) => \sig_child_addr_cntr_msh_reg[0]_i_2_n_1\, + CO(1) => \sig_child_addr_cntr_msh_reg[0]_i_2_n_2\, + CO(0) => \sig_child_addr_cntr_msh_reg[0]_i_2_n_3\, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => \sig_child_addr_cntr_msh[0]_i_3_n_0\, + O(3) => \sig_child_addr_cntr_msh_reg[0]_i_2_n_4\, + O(2) => \sig_child_addr_cntr_msh_reg[0]_i_2_n_5\, + O(1) => \sig_child_addr_cntr_msh_reg[0]_i_2_n_6\, + O(0) => \sig_child_addr_cntr_msh_reg[0]_i_2_n_7\, + S(3) => \sig_child_addr_cntr_msh[0]_i_4_n_0\, + S(2) => \sig_child_addr_cntr_msh[0]_i_5_n_0\, + S(1) => \sig_child_addr_cntr_msh[0]_i_6_n_0\, + S(0) => \sig_child_addr_cntr_msh[0]_i_7_n_0\ + ); +\sig_child_addr_cntr_msh_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(25), - Q => sig_addr_cntr_lsh_kh(7), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_msh[0]_i_1_n_0\, + D => \sig_child_addr_cntr_msh_reg[8]_i_1_n_5\, + Q => sig_child_addr_cntr_msh_reg(10), + R => sig_init_reg ); -\sig_addr_cntr_lsh_kh_reg[8]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_msh_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(26), - Q => sig_addr_cntr_lsh_kh(8), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_msh[0]_i_1_n_0\, + D => \sig_child_addr_cntr_msh_reg[8]_i_1_n_4\, + Q => sig_child_addr_cntr_msh_reg(11), + R => sig_init_reg ); -\sig_addr_cntr_lsh_kh_reg[9]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_msh_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(27), - Q => sig_addr_cntr_lsh_kh(9), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_msh[0]_i_1_n_0\, + D => \sig_child_addr_cntr_msh_reg[12]_i_1_n_7\, + Q => sig_child_addr_cntr_msh_reg(12), + R => sig_init_reg + ); +\sig_child_addr_cntr_msh_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \sig_child_addr_cntr_msh_reg[8]_i_1_n_0\, + CO(3) => \NLW_sig_child_addr_cntr_msh_reg[12]_i_1_CO_UNCONNECTED\(3), + CO(2) => \sig_child_addr_cntr_msh_reg[12]_i_1_n_1\, + CO(1) => \sig_child_addr_cntr_msh_reg[12]_i_1_n_2\, + CO(0) => \sig_child_addr_cntr_msh_reg[12]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \sig_child_addr_cntr_msh_reg[12]_i_1_n_4\, + O(2) => \sig_child_addr_cntr_msh_reg[12]_i_1_n_5\, + O(1) => \sig_child_addr_cntr_msh_reg[12]_i_1_n_6\, + O(0) => \sig_child_addr_cntr_msh_reg[12]_i_1_n_7\, + S(3) => \sig_child_addr_cntr_msh[12]_i_2_n_0\, + S(2) => \sig_child_addr_cntr_msh[12]_i_3_n_0\, + S(1) => \sig_child_addr_cntr_msh[12]_i_4_n_0\, + S(0) => \sig_child_addr_cntr_msh[12]_i_5_n_0\ ); -\sig_adjusted_addr_incr_ireg2[0]_i_1\: unisim.vcomponents.LUT5 +\sig_child_addr_cntr_msh_reg[13]\: unisim.vcomponents.FDRE generic map( - INIT => X"07F7F808" + INIT => '0' ) port map ( - I0 => sig_bytes_to_mbaa_ireg1(0), - I1 => sig_first_xfer_im0, - I2 => sig_btt_lt_b2mbaa_ireg1, - I3 => sig_btt_residue_slice_im0(0), - I4 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, - O => sig_adjusted_addr_incr_im1(0) + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_msh[0]_i_1_n_0\, + D => \sig_child_addr_cntr_msh_reg[12]_i_1_n_6\, + Q => sig_child_addr_cntr_msh_reg(13), + R => sig_init_reg ); -\sig_adjusted_addr_incr_ireg2[1]_i_1\: unisim.vcomponents.LUT6 +\sig_child_addr_cntr_msh_reg[14]\: unisim.vcomponents.FDRE generic map( - INIT => X"9699966696669666" + INIT => '0' ) port map ( - I0 => \sig_adjusted_addr_incr_ireg2[1]_i_2_n_0\, - I1 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, - I2 => sig_btt_residue_slice_im0(1), - I3 => sig_btt_lt_b2mbaa_ireg1, - I4 => sig_first_xfer_im0, - I5 => sig_bytes_to_mbaa_ireg1(1), - O => sig_adjusted_addr_incr_im1(1) + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_msh[0]_i_1_n_0\, + D => \sig_child_addr_cntr_msh_reg[12]_i_1_n_5\, + Q => sig_child_addr_cntr_msh_reg(14), + R => sig_init_reg ); -\sig_adjusted_addr_incr_ireg2[1]_i_2\: unisim.vcomponents.LUT5 +\sig_child_addr_cntr_msh_reg[15]\: unisim.vcomponents.FDRE generic map( - INIT => X"AA800080" + INIT => '0' ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, - I1 => sig_bytes_to_mbaa_ireg1(0), - I2 => sig_first_xfer_im0, - I3 => sig_btt_lt_b2mbaa_ireg1, - I4 => sig_btt_residue_slice_im0(0), - O => \sig_adjusted_addr_incr_ireg2[1]_i_2_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_msh[0]_i_1_n_0\, + D => \sig_child_addr_cntr_msh_reg[12]_i_1_n_4\, + Q => sig_child_addr_cntr_msh_reg(15), + R => sig_init_reg ); -\sig_adjusted_addr_incr_ireg2[2]_i_1\: unisim.vcomponents.LUT6 +\sig_child_addr_cntr_msh_reg[1]\: unisim.vcomponents.FDRE generic map( - INIT => X"9699966696669666" + INIT => '0' ) port map ( - I0 => \sig_adjusted_addr_incr_ireg2[2]_i_2_n_0\, - I1 => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, - I2 => sig_btt_residue_slice_im0(2), - I3 => sig_btt_lt_b2mbaa_ireg1, - I4 => sig_first_xfer_im0, - I5 => sig_bytes_to_mbaa_ireg1(2), - O => sig_adjusted_addr_incr_im1(2) + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_msh[0]_i_1_n_0\, + D => \sig_child_addr_cntr_msh_reg[0]_i_2_n_6\, + Q => sig_child_addr_cntr_msh_reg(1), + R => sig_init_reg ); -\sig_adjusted_addr_incr_ireg2[2]_i_2\: unisim.vcomponents.LUT6 +\sig_child_addr_cntr_msh_reg[2]\: unisim.vcomponents.FDRE generic map( - INIT => X"FFEAAAEAAA800080" + INIT => '0' ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, - I1 => sig_bytes_to_mbaa_ireg1(1), - I2 => sig_first_xfer_im0, - I3 => sig_btt_lt_b2mbaa_ireg1, - I4 => sig_btt_residue_slice_im0(1), - I5 => \sig_adjusted_addr_incr_ireg2[1]_i_2_n_0\, - O => \sig_adjusted_addr_incr_ireg2[2]_i_2_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_msh[0]_i_1_n_0\, + D => \sig_child_addr_cntr_msh_reg[0]_i_2_n_5\, + Q => sig_child_addr_cntr_msh_reg(2), + R => sig_init_reg ); -\sig_adjusted_addr_incr_ireg2[3]_i_1\: unisim.vcomponents.LUT5 +\sig_child_addr_cntr_msh_reg[3]\: unisim.vcomponents.FDRE generic map( - INIT => X"556AAA6A" + INIT => '0' ) port map ( - I0 => \sig_adjusted_addr_incr_ireg2[3]_i_2_n_0\, - I1 => sig_bytes_to_mbaa_ireg1(3), - I2 => sig_first_xfer_im0, - I3 => sig_btt_lt_b2mbaa_ireg1, - I4 => sig_btt_residue_slice_im0(3), - O => sig_adjusted_addr_incr_im1(3) + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_msh[0]_i_1_n_0\, + D => \sig_child_addr_cntr_msh_reg[0]_i_2_n_4\, + Q => sig_child_addr_cntr_msh_reg(3), + R => sig_init_reg ); -\sig_adjusted_addr_incr_ireg2[3]_i_2\: unisim.vcomponents.LUT6 +\sig_child_addr_cntr_msh_reg[4]\: unisim.vcomponents.FDRE generic map( - INIT => X"FFEAAAEAAA800080" + INIT => '0' ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, - I1 => sig_bytes_to_mbaa_ireg1(2), - I2 => sig_first_xfer_im0, - I3 => sig_btt_lt_b2mbaa_ireg1, - I4 => sig_btt_residue_slice_im0(2), - I5 => \sig_adjusted_addr_incr_ireg2[2]_i_2_n_0\, - O => \sig_adjusted_addr_incr_ireg2[3]_i_2_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_msh[0]_i_1_n_0\, + D => \sig_child_addr_cntr_msh_reg[4]_i_1_n_7\, + Q => sig_child_addr_cntr_msh_reg(4), + R => sig_init_reg + ); +\sig_child_addr_cntr_msh_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \sig_child_addr_cntr_msh_reg[0]_i_2_n_0\, + CO(3) => \sig_child_addr_cntr_msh_reg[4]_i_1_n_0\, + CO(2) => \sig_child_addr_cntr_msh_reg[4]_i_1_n_1\, + CO(1) => \sig_child_addr_cntr_msh_reg[4]_i_1_n_2\, + CO(0) => \sig_child_addr_cntr_msh_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \sig_child_addr_cntr_msh_reg[4]_i_1_n_4\, + O(2) => \sig_child_addr_cntr_msh_reg[4]_i_1_n_5\, + O(1) => \sig_child_addr_cntr_msh_reg[4]_i_1_n_6\, + O(0) => \sig_child_addr_cntr_msh_reg[4]_i_1_n_7\, + S(3) => \sig_child_addr_cntr_msh[4]_i_2_n_0\, + S(2) => \sig_child_addr_cntr_msh[4]_i_3_n_0\, + S(1) => \sig_child_addr_cntr_msh[4]_i_4_n_0\, + S(0) => \sig_child_addr_cntr_msh[4]_i_5_n_0\ ); -\sig_adjusted_addr_incr_ireg2[4]_i_1\: unisim.vcomponents.LUT5 +\sig_child_addr_cntr_msh_reg[5]\: unisim.vcomponents.FDRE generic map( - INIT => X"556AAA6A" + INIT => '0' ) port map ( - I0 => \sig_adjusted_addr_incr_ireg2[6]_i_2_n_0\, - I1 => sig_bytes_to_mbaa_ireg1(4), - I2 => sig_first_xfer_im0, - I3 => sig_btt_lt_b2mbaa_ireg1, - I4 => sig_btt_residue_slice_im0(4), - O => sig_adjusted_addr_incr_im1(4) + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_msh[0]_i_1_n_0\, + D => \sig_child_addr_cntr_msh_reg[4]_i_1_n_6\, + Q => sig_child_addr_cntr_msh_reg(5), + R => sig_init_reg ); -\sig_adjusted_addr_incr_ireg2[5]_i_1\: unisim.vcomponents.LUT6 +\sig_child_addr_cntr_msh_reg[6]\: unisim.vcomponents.FDRE generic map( - INIT => X"757F7F7F8A808080" + INIT => '0' ) port map ( - I0 => \sig_adjusted_addr_incr_ireg2[6]_i_2_n_0\, - I1 => sig_btt_residue_slice_im0(4), - I2 => sig_btt_lt_b2mbaa_ireg1, - I3 => sig_first_xfer_im0, - I4 => sig_bytes_to_mbaa_ireg1(4), - I5 => \sig_addr_cntr_incr_ireg2[5]_i_1_n_0\, - O => sig_adjusted_addr_incr_im1(5) + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_msh[0]_i_1_n_0\, + D => \sig_child_addr_cntr_msh_reg[4]_i_1_n_5\, + Q => sig_child_addr_cntr_msh_reg(6), + R => sig_init_reg ); -\sig_adjusted_addr_incr_ireg2[6]_i_1\: unisim.vcomponents.LUT4 +\sig_child_addr_cntr_msh_reg[7]\: unisim.vcomponents.FDRE generic map( - INIT => X"7F80" + INIT => '0' ) port map ( - I0 => \sig_addr_cntr_incr_ireg2[4]_i_1_n_0\, - I1 => \sig_adjusted_addr_incr_ireg2[6]_i_2_n_0\, - I2 => \sig_addr_cntr_incr_ireg2[5]_i_1_n_0\, - I3 => \sig_addr_cntr_incr_ireg2[6]_i_1_n_0\, - O => sig_adjusted_addr_incr_im1(6) + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_msh[0]_i_1_n_0\, + D => \sig_child_addr_cntr_msh_reg[4]_i_1_n_4\, + Q => sig_child_addr_cntr_msh_reg(7), + R => sig_init_reg ); -\sig_adjusted_addr_incr_ireg2[6]_i_2\: unisim.vcomponents.LUT4 +\sig_child_addr_cntr_msh_reg[8]\: unisim.vcomponents.FDRE generic map( - INIT => X"A880" + INIT => '0' ) port map ( - I0 => \sig_addr_cntr_incr_ireg2[3]_i_1_n_0\, - I1 => \sig_adjusted_addr_incr_ireg2[2]_i_2_n_0\, - I2 => \sig_addr_cntr_incr_ireg2[2]_i_1_n_0\, - I3 => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, - O => \sig_adjusted_addr_incr_ireg2[6]_i_2_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_msh[0]_i_1_n_0\, + D => \sig_child_addr_cntr_msh_reg[8]_i_1_n_7\, + Q => sig_child_addr_cntr_msh_reg(8), + R => sig_init_reg ); -\sig_adjusted_addr_incr_ireg2_reg[0]\: unisim.vcomponents.FDRE +\sig_child_addr_cntr_msh_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \sig_child_addr_cntr_msh_reg[4]_i_1_n_0\, + CO(3) => \sig_child_addr_cntr_msh_reg[8]_i_1_n_0\, + CO(2) => \sig_child_addr_cntr_msh_reg[8]_i_1_n_1\, + CO(1) => \sig_child_addr_cntr_msh_reg[8]_i_1_n_2\, + CO(0) => \sig_child_addr_cntr_msh_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \sig_child_addr_cntr_msh_reg[8]_i_1_n_4\, + O(2) => \sig_child_addr_cntr_msh_reg[8]_i_1_n_5\, + O(1) => \sig_child_addr_cntr_msh_reg[8]_i_1_n_6\, + O(0) => \sig_child_addr_cntr_msh_reg[8]_i_1_n_7\, + S(3) => \sig_child_addr_cntr_msh[8]_i_2_n_0\, + S(2) => \sig_child_addr_cntr_msh[8]_i_3_n_0\, + S(1) => \sig_child_addr_cntr_msh[8]_i_4_n_0\, + S(0) => \sig_child_addr_cntr_msh[8]_i_5_n_0\ + ); +\sig_child_addr_cntr_msh_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc2_reg, - D => sig_adjusted_addr_incr_im1(0), - Q => \sig_adjusted_addr_incr_ireg2_reg_n_0_[0]\, - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_child_addr_cntr_msh[0]_i_1_n_0\, + D => \sig_child_addr_cntr_msh_reg[8]_i_1_n_6\, + Q => sig_child_addr_cntr_msh_reg(9), + R => sig_init_reg ); -\sig_adjusted_addr_incr_ireg2_reg[1]\: unisim.vcomponents.FDRE +sig_child_addr_lsh_rollover_reg_i_1: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"2" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc2_reg, - D => sig_adjusted_addr_incr_im1(1), - Q => \sig_adjusted_addr_incr_ireg2_reg_n_0_[1]\, - R => \^sig_init_reg\ + I0 => p_1_in, + I1 => sig_predict_child_addr_lsh(15), + O => sig_child_addr_lsh_rollover_reg_i_1_n_0 ); -\sig_adjusted_addr_incr_ireg2_reg[2]\: unisim.vcomponents.FDRE +sig_child_addr_lsh_rollover_reg_i_10: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"2" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc2_reg, - D => sig_adjusted_addr_incr_im1(2), - Q => \sig_adjusted_addr_incr_ireg2_reg_n_0_[2]\, - R => \^sig_init_reg\ + I0 => sig_child_addr_cntr_lsh_reg(10), + O => sig_child_addr_lsh_rollover_reg_i_10_n_0 ); -\sig_adjusted_addr_incr_ireg2_reg[3]\: unisim.vcomponents.FDRE +sig_child_addr_lsh_rollover_reg_i_11: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"2" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc2_reg, - D => sig_adjusted_addr_incr_im1(3), - Q => \sig_adjusted_addr_incr_ireg2_reg_n_0_[3]\, - R => \^sig_init_reg\ + I0 => sig_child_addr_cntr_lsh_reg(9), + O => sig_child_addr_lsh_rollover_reg_i_11_n_0 ); -\sig_adjusted_addr_incr_ireg2_reg[4]\: unisim.vcomponents.FDRE +sig_child_addr_lsh_rollover_reg_i_12: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"6" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc2_reg, - D => sig_adjusted_addr_incr_im1(4), - Q => \sig_adjusted_addr_incr_ireg2_reg_n_0_[4]\, - R => \^sig_init_reg\ + I0 => sig_child_addr_cntr_lsh_reg(8), + I1 => \gpr1.dout_i_reg[9]\(8), + O => sig_child_addr_lsh_rollover_reg_i_12_n_0 ); -\sig_adjusted_addr_incr_ireg2_reg[5]\: unisim.vcomponents.FDRE +sig_child_addr_lsh_rollover_reg_i_14: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"6" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc2_reg, - D => sig_adjusted_addr_incr_im1(5), - Q => \sig_adjusted_addr_incr_ireg2_reg_n_0_[5]\, - R => \^sig_init_reg\ + I0 => sig_child_addr_cntr_lsh_reg(7), + I1 => \gpr1.dout_i_reg[9]\(7), + O => sig_child_addr_lsh_rollover_reg_i_14_n_0 ); -\sig_adjusted_addr_incr_ireg2_reg[6]\: unisim.vcomponents.FDRE +sig_child_addr_lsh_rollover_reg_i_15: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"6" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc2_reg, - D => sig_adjusted_addr_incr_im1(6), - Q => \sig_adjusted_addr_incr_ireg2_reg_n_0_[6]\, - R => \^sig_init_reg\ + I0 => sig_child_addr_cntr_lsh_reg(6), + I1 => \gpr1.dout_i_reg[9]\(6), + O => sig_child_addr_lsh_rollover_reg_i_15_n_0 ); -sig_brst_cnt_eq_one_ireg1_i_1: unisim.vcomponents.LUT6 +sig_child_addr_lsh_rollover_reg_i_16: unisim.vcomponents.LUT2 generic map( - INIT => X"0000000000000002" + INIT => X"6" ) port map ( - I0 => sel0(0), - I1 => sig_brst_cnt_eq_one_ireg1_i_2_n_0, - I2 => sel0(8), - I3 => sel0(7), - I4 => sel0(5), - I5 => sel0(6), - O => sig_brst_cnt_eq_one_im0 + I0 => sig_child_addr_cntr_lsh_reg(5), + I1 => \gpr1.dout_i_reg[9]\(5), + O => sig_child_addr_lsh_rollover_reg_i_16_n_0 ); -sig_brst_cnt_eq_one_ireg1_i_2: unisim.vcomponents.LUT4 +sig_child_addr_lsh_rollover_reg_i_17: unisim.vcomponents.LUT2 generic map( - INIT => X"FFFE" + INIT => X"6" ) port map ( - I0 => sel0(3), - I1 => sel0(4), - I2 => sel0(1), - I3 => sel0(2), - O => sig_brst_cnt_eq_one_ireg1_i_2_n_0 + I0 => sig_child_addr_cntr_lsh_reg(4), + I1 => \gpr1.dout_i_reg[9]\(4), + O => sig_child_addr_lsh_rollover_reg_i_17_n_0 ); -sig_brst_cnt_eq_one_ireg1_reg: unisim.vcomponents.FDRE +sig_child_addr_lsh_rollover_reg_i_18: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"6" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc1_reg, - D => sig_brst_cnt_eq_one_im0, - Q => sig_brst_cnt_eq_one_ireg1, - R => \^sig_init_reg\ + I0 => sig_child_addr_cntr_lsh_reg(3), + I1 => \gpr1.dout_i_reg[9]\(3), + O => sig_child_addr_lsh_rollover_reg_i_18_n_0 ); -sig_brst_cnt_eq_zero_ireg1_i_1: unisim.vcomponents.LUT6 +sig_child_addr_lsh_rollover_reg_i_19: unisim.vcomponents.LUT2 generic map( - INIT => X"0000000000000001" + INIT => X"6" ) port map ( - I0 => sel0(7), - I1 => sig_brst_cnt_eq_zero_ireg1_i_2_n_0, - I2 => sel0(6), - I3 => sel0(8), - I4 => sel0(4), - I5 => sel0(5), - O => sig_brst_cnt_eq_zero_im0 + I0 => \^sig_xfer_addr_reg_reg[2]_0\(2), + I1 => \gpr1.dout_i_reg[9]\(2), + O => sig_child_addr_lsh_rollover_reg_i_19_n_0 ); -sig_brst_cnt_eq_zero_ireg1_i_2: unisim.vcomponents.LUT4 +sig_child_addr_lsh_rollover_reg_i_20: unisim.vcomponents.LUT2 generic map( - INIT => X"FFFE" + INIT => X"6" ) port map ( - I0 => sel0(2), - I1 => sel0(3), - I2 => sel0(0), - I3 => sel0(1), - O => sig_brst_cnt_eq_zero_ireg1_i_2_n_0 + I0 => \^sig_xfer_addr_reg_reg[2]_0\(1), + I1 => \gpr1.dout_i_reg[9]\(1), + O => sig_child_addr_lsh_rollover_reg_i_20_n_0 ); -sig_brst_cnt_eq_zero_ireg1_reg: unisim.vcomponents.FDRE +sig_child_addr_lsh_rollover_reg_i_21: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"6" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc1_reg, - D => sig_brst_cnt_eq_zero_im0, - Q => sig_brst_cnt_eq_zero_ireg1, - R => \^sig_init_reg\ + I0 => \^sig_xfer_addr_reg_reg[2]_0\(0), + I1 => \gpr1.dout_i_reg[9]\(0), + O => sig_child_addr_lsh_rollover_reg_i_21_n_0 ); -sig_btt_cntr_im00_carry: unisim.vcomponents.CARRY4 - port map ( - CI => '0', - CO(3) => sig_btt_cntr_im00_carry_n_0, - CO(2) => sig_btt_cntr_im00_carry_n_1, - CO(1) => sig_btt_cntr_im00_carry_n_2, - CO(0) => sig_btt_cntr_im00_carry_n_3, - CYINIT => '1', - DI(3 downto 0) => sig_btt_residue_slice_im0(3 downto 0), - O(3 downto 0) => sig_btt_cntr_im00(3 downto 0), - S(3) => sig_btt_cntr_im00_carry_i_1_n_0, - S(2) => sig_btt_cntr_im00_carry_i_2_n_0, - S(1) => sig_btt_cntr_im00_carry_i_3_n_0, - S(0) => sig_btt_cntr_im00_carry_i_4_n_0 +sig_child_addr_lsh_rollover_reg_i_4: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => p_1_in, + O => sig_child_addr_lsh_rollover_reg_i_4_n_0 ); -\sig_btt_cntr_im00_carry__0\: unisim.vcomponents.CARRY4 - port map ( - CI => sig_btt_cntr_im00_carry_n_0, - CO(3) => \sig_btt_cntr_im00_carry__0_n_0\, - CO(2) => \sig_btt_cntr_im00_carry__0_n_1\, - CO(1) => \sig_btt_cntr_im00_carry__0_n_2\, - CO(0) => \sig_btt_cntr_im00_carry__0_n_3\, - CYINIT => '0', - DI(3) => sel0(0), - DI(2 downto 0) => sig_btt_residue_slice_im0(6 downto 4), - O(3 downto 0) => sig_btt_cntr_im00(7 downto 4), - S(3) => \sig_btt_cntr_im00_carry__0_i_1_n_0\, - S(2) => \sig_btt_cntr_im00_carry__0_i_2_n_0\, - S(1) => \sig_btt_cntr_im00_carry__0_i_3_n_0\, - S(0) => \sig_btt_cntr_im00_carry__0_i_4_n_0\ +sig_child_addr_lsh_rollover_reg_i_5: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => sig_child_addr_cntr_lsh_reg(14), + O => sig_child_addr_lsh_rollover_reg_i_5_n_0 ); -\sig_btt_cntr_im00_carry__0_i_1\: unisim.vcomponents.LUT2 +sig_child_addr_lsh_rollover_reg_i_6: unisim.vcomponents.LUT1 generic map( - INIT => X"9" + INIT => X"2" ) port map ( - I0 => sel0(0), - I1 => sig_addr_cntr_incr_ireg2(7), - O => \sig_btt_cntr_im00_carry__0_i_1_n_0\ + I0 => sig_child_addr_cntr_lsh_reg(13), + O => sig_child_addr_lsh_rollover_reg_i_6_n_0 ); -\sig_btt_cntr_im00_carry__0_i_2\: unisim.vcomponents.LUT2 +sig_child_addr_lsh_rollover_reg_i_7: unisim.vcomponents.LUT1 generic map( - INIT => X"9" + INIT => X"2" ) port map ( - I0 => sig_btt_residue_slice_im0(6), - I1 => sig_addr_cntr_incr_ireg2(6), - O => \sig_btt_cntr_im00_carry__0_i_2_n_0\ + I0 => sig_child_addr_cntr_lsh_reg(12), + O => sig_child_addr_lsh_rollover_reg_i_7_n_0 ); -\sig_btt_cntr_im00_carry__0_i_3\: unisim.vcomponents.LUT2 +sig_child_addr_lsh_rollover_reg_i_9: unisim.vcomponents.LUT1 generic map( - INIT => X"9" + INIT => X"2" ) port map ( - I0 => sig_btt_residue_slice_im0(5), - I1 => sig_addr_cntr_incr_ireg2(5), - O => \sig_btt_cntr_im00_carry__0_i_3_n_0\ + I0 => sig_child_addr_cntr_lsh_reg(11), + O => sig_child_addr_lsh_rollover_reg_i_9_n_0 ); -\sig_btt_cntr_im00_carry__0_i_4\: unisim.vcomponents.LUT2 +sig_child_addr_lsh_rollover_reg_reg: unisim.vcomponents.FDRE generic map( - INIT => X"9" + INIT => '0' ) port map ( - I0 => sig_btt_residue_slice_im0(4), - I1 => sig_addr_cntr_incr_ireg2(4), - O => \sig_btt_cntr_im00_carry__0_i_4_n_0\ + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_child_addr_lsh_rollover_reg_i_1_n_0, + Q => sig_child_addr_lsh_rollover_reg, + R => sig_init_reg ); -\sig_btt_cntr_im00_carry__1\: unisim.vcomponents.CARRY4 +sig_child_addr_lsh_rollover_reg_reg_i_13: unisim.vcomponents.CARRY4 port map ( - CI => \sig_btt_cntr_im00_carry__0_n_0\, - CO(3) => \sig_btt_cntr_im00_carry__1_n_0\, - CO(2) => \sig_btt_cntr_im00_carry__1_n_1\, - CO(1) => \sig_btt_cntr_im00_carry__1_n_2\, - CO(0) => \sig_btt_cntr_im00_carry__1_n_3\, + CI => '0', + CO(3) => sig_child_addr_lsh_rollover_reg_reg_i_13_n_0, + CO(2) => sig_child_addr_lsh_rollover_reg_reg_i_13_n_1, + CO(1) => sig_child_addr_lsh_rollover_reg_reg_i_13_n_2, + CO(0) => sig_child_addr_lsh_rollover_reg_reg_i_13_n_3, CYINIT => '0', - DI(3 downto 0) => sel0(4 downto 1), - O(3 downto 0) => sig_btt_cntr_im00(11 downto 8), - S(3) => \sig_btt_cntr_im00_carry__1_i_1_n_0\, - S(2) => \sig_btt_cntr_im00_carry__1_i_2_n_0\, - S(1) => \sig_btt_cntr_im00_carry__1_i_3_n_0\, - S(0) => \sig_btt_cntr_im00_carry__1_i_4_n_0\ + DI(3) => sig_child_addr_cntr_lsh_reg(3), + DI(2 downto 0) => \^sig_xfer_addr_reg_reg[2]_0\(2 downto 0), + O(3 downto 0) => NLW_sig_child_addr_lsh_rollover_reg_reg_i_13_O_UNCONNECTED(3 downto 0), + S(3) => sig_child_addr_lsh_rollover_reg_i_18_n_0, + S(2) => sig_child_addr_lsh_rollover_reg_i_19_n_0, + S(1) => sig_child_addr_lsh_rollover_reg_i_20_n_0, + S(0) => sig_child_addr_lsh_rollover_reg_i_21_n_0 + ); +sig_child_addr_lsh_rollover_reg_reg_i_2: unisim.vcomponents.CARRY4 + port map ( + CI => sig_child_addr_lsh_rollover_reg_reg_i_3_n_0, + CO(3) => NLW_sig_child_addr_lsh_rollover_reg_reg_i_2_CO_UNCONNECTED(3), + CO(2) => sig_child_addr_lsh_rollover_reg_reg_i_2_n_1, + CO(1) => sig_child_addr_lsh_rollover_reg_reg_i_2_n_2, + CO(0) => sig_child_addr_lsh_rollover_reg_reg_i_2_n_3, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => sig_predict_child_addr_lsh(15), + O(2 downto 0) => NLW_sig_child_addr_lsh_rollover_reg_reg_i_2_O_UNCONNECTED(2 downto 0), + S(3) => sig_child_addr_lsh_rollover_reg_i_4_n_0, + S(2) => sig_child_addr_lsh_rollover_reg_i_5_n_0, + S(1) => sig_child_addr_lsh_rollover_reg_i_6_n_0, + S(0) => sig_child_addr_lsh_rollover_reg_i_7_n_0 + ); +sig_child_addr_lsh_rollover_reg_reg_i_3: unisim.vcomponents.CARRY4 + port map ( + CI => sig_child_addr_lsh_rollover_reg_reg_i_8_n_0, + CO(3) => sig_child_addr_lsh_rollover_reg_reg_i_3_n_0, + CO(2) => sig_child_addr_lsh_rollover_reg_reg_i_3_n_1, + CO(1) => sig_child_addr_lsh_rollover_reg_reg_i_3_n_2, + CO(0) => sig_child_addr_lsh_rollover_reg_reg_i_3_n_3, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => sig_child_addr_cntr_lsh_reg(8), + O(3 downto 0) => NLW_sig_child_addr_lsh_rollover_reg_reg_i_3_O_UNCONNECTED(3 downto 0), + S(3) => sig_child_addr_lsh_rollover_reg_i_9_n_0, + S(2) => sig_child_addr_lsh_rollover_reg_i_10_n_0, + S(1) => sig_child_addr_lsh_rollover_reg_i_11_n_0, + S(0) => sig_child_addr_lsh_rollover_reg_i_12_n_0 + ); +sig_child_addr_lsh_rollover_reg_reg_i_8: unisim.vcomponents.CARRY4 + port map ( + CI => sig_child_addr_lsh_rollover_reg_reg_i_13_n_0, + CO(3) => sig_child_addr_lsh_rollover_reg_reg_i_8_n_0, + CO(2) => sig_child_addr_lsh_rollover_reg_reg_i_8_n_1, + CO(1) => sig_child_addr_lsh_rollover_reg_reg_i_8_n_2, + CO(0) => sig_child_addr_lsh_rollover_reg_reg_i_8_n_3, + CYINIT => '0', + DI(3 downto 0) => sig_child_addr_cntr_lsh_reg(7 downto 4), + O(3 downto 0) => NLW_sig_child_addr_lsh_rollover_reg_reg_i_8_O_UNCONNECTED(3 downto 0), + S(3) => sig_child_addr_lsh_rollover_reg_i_14_n_0, + S(2) => sig_child_addr_lsh_rollover_reg_i_15_n_0, + S(1) => sig_child_addr_lsh_rollover_reg_i_16_n_0, + S(0) => sig_child_addr_lsh_rollover_reg_i_17_n_0 ); -\sig_btt_cntr_im00_carry__1_i_1\: unisim.vcomponents.LUT1 +\sig_child_addr_reg_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => X"1" + INIT => '0' ) port map ( - I0 => sel0(4), - O => \sig_btt_cntr_im00_carry__1_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(0), + Q => \sig_child_addr_reg_reg_n_0_[0]\, + R => SR(0) ); -\sig_btt_cntr_im00_carry__1_i_2\: unisim.vcomponents.LUT1 +\sig_child_addr_reg_reg[10]\: unisim.vcomponents.FDRE generic map( - INIT => X"1" + INIT => '0' ) port map ( - I0 => sel0(3), - O => \sig_btt_cntr_im00_carry__1_i_2_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(10), + Q => \sig_child_addr_reg_reg_n_0_[10]\, + R => SR(0) ); -\sig_btt_cntr_im00_carry__1_i_3\: unisim.vcomponents.LUT1 +\sig_child_addr_reg_reg[11]\: unisim.vcomponents.FDRE generic map( - INIT => X"1" + INIT => '0' ) port map ( - I0 => sel0(2), - O => \sig_btt_cntr_im00_carry__1_i_3_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(11), + Q => \sig_child_addr_reg_reg_n_0_[11]\, + R => SR(0) ); -\sig_btt_cntr_im00_carry__1_i_4\: unisim.vcomponents.LUT1 +\sig_child_addr_reg_reg[12]\: unisim.vcomponents.FDRE generic map( - INIT => X"1" + INIT => '0' ) port map ( - I0 => sel0(1), - O => \sig_btt_cntr_im00_carry__1_i_4_n_0\ - ); -\sig_btt_cntr_im00_carry__2\: unisim.vcomponents.CARRY4 - port map ( - CI => \sig_btt_cntr_im00_carry__1_n_0\, - CO(3) => \NLW_sig_btt_cntr_im00_carry__2_CO_UNCONNECTED\(3), - CO(2) => \sig_btt_cntr_im00_carry__2_n_1\, - CO(1) => \sig_btt_cntr_im00_carry__2_n_2\, - CO(0) => \sig_btt_cntr_im00_carry__2_n_3\, - CYINIT => '0', - DI(3) => '0', - DI(2 downto 0) => sel0(7 downto 5), - O(3 downto 0) => sig_btt_cntr_im00(15 downto 12), - S(3) => \sig_btt_cntr_im00_carry__2_i_1_n_0\, - S(2) => \sig_btt_cntr_im00_carry__2_i_2_n_0\, - S(1) => \sig_btt_cntr_im00_carry__2_i_3_n_0\, - S(0) => \sig_btt_cntr_im00_carry__2_i_4_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(12), + Q => \sig_child_addr_reg_reg_n_0_[12]\, + R => SR(0) ); -\sig_btt_cntr_im00_carry__2_i_1\: unisim.vcomponents.LUT1 +\sig_child_addr_reg_reg[13]\: unisim.vcomponents.FDRE generic map( - INIT => X"1" + INIT => '0' ) port map ( - I0 => sel0(8), - O => \sig_btt_cntr_im00_carry__2_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(13), + Q => \sig_child_addr_reg_reg_n_0_[13]\, + R => SR(0) ); -\sig_btt_cntr_im00_carry__2_i_2\: unisim.vcomponents.LUT1 +\sig_child_addr_reg_reg[14]\: unisim.vcomponents.FDRE generic map( - INIT => X"1" + INIT => '0' ) port map ( - I0 => sel0(7), - O => \sig_btt_cntr_im00_carry__2_i_2_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(14), + Q => \sig_child_addr_reg_reg_n_0_[14]\, + R => SR(0) ); -\sig_btt_cntr_im00_carry__2_i_3\: unisim.vcomponents.LUT1 +\sig_child_addr_reg_reg[15]\: unisim.vcomponents.FDRE generic map( - INIT => X"1" + INIT => '0' ) port map ( - I0 => sel0(6), - O => \sig_btt_cntr_im00_carry__2_i_3_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(15), + Q => \sig_child_addr_reg_reg_n_0_[15]\, + R => SR(0) ); -\sig_btt_cntr_im00_carry__2_i_4\: unisim.vcomponents.LUT1 +\sig_child_addr_reg_reg[16]\: unisim.vcomponents.FDRE generic map( - INIT => X"1" + INIT => '0' ) port map ( - I0 => sel0(5), - O => \sig_btt_cntr_im00_carry__2_i_4_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(16), + Q => data(0), + R => SR(0) ); -sig_btt_cntr_im00_carry_i_1: unisim.vcomponents.LUT2 +\sig_child_addr_reg_reg[17]\: unisim.vcomponents.FDRE generic map( - INIT => X"9" + INIT => '0' ) port map ( - I0 => sig_btt_residue_slice_im0(3), - I1 => sig_addr_cntr_incr_ireg2(3), - O => sig_btt_cntr_im00_carry_i_1_n_0 + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(17), + Q => data(1), + R => SR(0) ); -sig_btt_cntr_im00_carry_i_2: unisim.vcomponents.LUT2 +\sig_child_addr_reg_reg[18]\: unisim.vcomponents.FDRE generic map( - INIT => X"9" + INIT => '0' ) port map ( - I0 => sig_btt_residue_slice_im0(2), - I1 => sig_addr_cntr_incr_ireg2(2), - O => sig_btt_cntr_im00_carry_i_2_n_0 + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(18), + Q => data(2), + R => SR(0) ); -sig_btt_cntr_im00_carry_i_3: unisim.vcomponents.LUT2 +\sig_child_addr_reg_reg[19]\: unisim.vcomponents.FDRE generic map( - INIT => X"9" + INIT => '0' ) port map ( - I0 => sig_btt_residue_slice_im0(1), - I1 => sig_addr_cntr_incr_ireg2(1), - O => sig_btt_cntr_im00_carry_i_3_n_0 + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(19), + Q => data(3), + R => SR(0) ); -sig_btt_cntr_im00_carry_i_4: unisim.vcomponents.LUT2 +\sig_child_addr_reg_reg[1]\: unisim.vcomponents.FDRE generic map( - INIT => X"9" + INIT => '0' ) port map ( - I0 => sig_btt_residue_slice_im0(0), - I1 => sig_addr_cntr_incr_ireg2(0), - O => sig_btt_cntr_im00_carry_i_4_n_0 + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(1), + Q => \sig_child_addr_reg_reg_n_0_[1]\, + R => SR(0) ); -\sig_btt_cntr_im0[0]_i_1\: unisim.vcomponents.LUT6 +\sig_child_addr_reg_reg[20]\: unisim.vcomponents.FDRE generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => '0' ) port map ( - I0 => \out\(0), - I1 => sig_btt_cntr_im00(0), - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => \sig_btt_cntr_im0[0]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(20), + Q => data(4), + R => SR(0) ); -\sig_btt_cntr_im0[10]_i_1\: unisim.vcomponents.LUT6 +\sig_child_addr_reg_reg[21]\: unisim.vcomponents.FDRE generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => '0' ) port map ( - I0 => \out\(10), - I1 => sig_btt_cntr_im00(10), - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => \sig_btt_cntr_im0[10]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(21), + Q => data(5), + R => SR(0) ); -\sig_btt_cntr_im0[11]_i_1\: unisim.vcomponents.LUT6 +\sig_child_addr_reg_reg[22]\: unisim.vcomponents.FDRE generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => '0' ) port map ( - I0 => \out\(11), - I1 => sig_btt_cntr_im00(11), - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => \sig_btt_cntr_im0[11]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(22), + Q => data(6), + R => SR(0) ); -\sig_btt_cntr_im0[12]_i_1\: unisim.vcomponents.LUT6 +\sig_child_addr_reg_reg[23]\: unisim.vcomponents.FDRE generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => '0' ) port map ( - I0 => \out\(12), - I1 => sig_btt_cntr_im00(12), - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => \sig_btt_cntr_im0[12]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(23), + Q => data(7), + R => SR(0) ); -\sig_btt_cntr_im0[13]_i_1\: unisim.vcomponents.LUT6 +\sig_child_addr_reg_reg[24]\: unisim.vcomponents.FDRE generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => '0' ) port map ( - I0 => \out\(13), - I1 => sig_btt_cntr_im00(13), - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => \sig_btt_cntr_im0[13]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(24), + Q => data(8), + R => SR(0) ); -\sig_btt_cntr_im0[14]_i_1\: unisim.vcomponents.LUT6 +\sig_child_addr_reg_reg[25]\: unisim.vcomponents.FDRE generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => '0' ) port map ( - I0 => \out\(14), - I1 => sig_btt_cntr_im00(14), - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => \sig_btt_cntr_im0[14]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(25), + Q => data(9), + R => SR(0) ); -\sig_btt_cntr_im0[15]_i_1\: unisim.vcomponents.LUT6 +\sig_child_addr_reg_reg[26]\: unisim.vcomponents.FDRE generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => '0' ) port map ( - I0 => \out\(15), - I1 => sig_btt_cntr_im00(15), - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => \sig_btt_cntr_im0[15]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(26), + Q => data(10), + R => SR(0) ); -\sig_btt_cntr_im0[1]_i_1\: unisim.vcomponents.LUT6 +\sig_child_addr_reg_reg[27]\: unisim.vcomponents.FDRE generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => '0' ) port map ( - I0 => \out\(1), - I1 => sig_btt_cntr_im00(1), - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => \sig_btt_cntr_im0[1]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(27), + Q => data(11), + R => SR(0) ); -\sig_btt_cntr_im0[2]_i_1\: unisim.vcomponents.LUT6 +\sig_child_addr_reg_reg[28]\: unisim.vcomponents.FDRE generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => '0' ) port map ( - I0 => \out\(2), - I1 => sig_btt_cntr_im00(2), - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => \sig_btt_cntr_im0[2]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(28), + Q => data(12), + R => SR(0) ); -\sig_btt_cntr_im0[3]_i_1\: unisim.vcomponents.LUT6 +\sig_child_addr_reg_reg[29]\: unisim.vcomponents.FDRE generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => '0' ) port map ( - I0 => \out\(3), - I1 => sig_btt_cntr_im00(3), - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => \sig_btt_cntr_im0[3]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(29), + Q => data(13), + R => SR(0) ); -\sig_btt_cntr_im0[4]_i_1\: unisim.vcomponents.LUT6 +\sig_child_addr_reg_reg[2]\: unisim.vcomponents.FDRE generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => '0' ) port map ( - I0 => \out\(4), - I1 => sig_btt_cntr_im00(4), - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => \sig_btt_cntr_im0[4]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(2), + Q => \sig_child_addr_reg_reg_n_0_[2]\, + R => SR(0) ); -\sig_btt_cntr_im0[5]_i_1\: unisim.vcomponents.LUT6 +\sig_child_addr_reg_reg[30]\: unisim.vcomponents.FDRE generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => '0' ) port map ( - I0 => \out\(5), - I1 => sig_btt_cntr_im00(5), - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => \sig_btt_cntr_im0[5]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(30), + Q => data(14), + R => SR(0) ); -\sig_btt_cntr_im0[6]_i_1\: unisim.vcomponents.LUT6 +\sig_child_addr_reg_reg[31]\: unisim.vcomponents.FDRE generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => '0' ) port map ( - I0 => \out\(6), - I1 => sig_btt_cntr_im00(6), - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => \sig_btt_cntr_im0[6]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(31), + Q => data(15), + R => SR(0) ); -\sig_btt_cntr_im0[7]_i_1\: unisim.vcomponents.LUT6 +\sig_child_addr_reg_reg[3]\: unisim.vcomponents.FDRE generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => '0' ) port map ( - I0 => \out\(7), - I1 => sig_btt_cntr_im00(7), - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => \sig_btt_cntr_im0[7]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(3), + Q => \sig_child_addr_reg_reg_n_0_[3]\, + R => SR(0) ); -\sig_btt_cntr_im0[8]_i_1\: unisim.vcomponents.LUT6 +\sig_child_addr_reg_reg[4]\: unisim.vcomponents.FDRE generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => '0' ) port map ( - I0 => \out\(8), - I1 => sig_btt_cntr_im00(8), - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => \sig_btt_cntr_im0[8]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(4), + Q => \sig_child_addr_reg_reg_n_0_[4]\, + R => SR(0) ); -\sig_btt_cntr_im0[9]_i_1\: unisim.vcomponents.LUT6 +\sig_child_addr_reg_reg[5]\: unisim.vcomponents.FDRE generic map( - INIT => X"CCCCCCCCCCCCCACC" + INIT => '0' ) port map ( - I0 => \out\(9), - I1 => sig_btt_cntr_im00(9), - I2 => \^in\(37), - I3 => \^sig_input_reg_empty\, - I4 => \^sig_sm_halt_reg\, - I5 => Q(0), - O => \sig_btt_cntr_im0[9]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(5), + Q => \sig_child_addr_reg_reg_n_0_[5]\, + R => SR(0) ); -\sig_btt_cntr_im0_reg[0]\: unisim.vcomponents.FDRE +\sig_child_addr_reg_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => \sig_btt_cntr_im0[0]_i_1_n_0\, - Q => sig_btt_residue_slice_im0(0), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(6), + Q => \sig_child_addr_reg_reg_n_0_[6]\, + R => SR(0) ); -\sig_btt_cntr_im0_reg[10]\: unisim.vcomponents.FDRE +\sig_child_addr_reg_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => \sig_btt_cntr_im0[10]_i_1_n_0\, - Q => sel0(3), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(7), + Q => \sig_child_addr_reg_reg_n_0_[7]\, + R => SR(0) ); -\sig_btt_cntr_im0_reg[11]\: unisim.vcomponents.FDRE +\sig_child_addr_reg_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => \sig_btt_cntr_im0[11]_i_1_n_0\, - Q => sel0(4), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(8), + Q => \sig_child_addr_reg_reg_n_0_[8]\, + R => SR(0) ); -\sig_btt_cntr_im0_reg[12]\: unisim.vcomponents.FDRE +\sig_child_addr_reg_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => \sig_btt_cntr_im0[12]_i_1_n_0\, - Q => sel0(5), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_addr_reg(9), + Q => \sig_child_addr_reg_reg_n_0_[9]\, + R => SR(0) ); -\sig_btt_cntr_im0_reg[13]\: unisim.vcomponents.FDRE +sig_child_burst_type_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => \sig_btt_cntr_im0[13]_i_1_n_0\, - Q => sel0(6), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_input_burst_type_reg, + Q => sig_child_burst_type_reg, + R => SR(0) ); -\sig_btt_cntr_im0_reg[14]\: unisim.vcomponents.FDRE +sig_child_cmd_reg_full_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => \sig_btt_cntr_im0[14]_i_1_n_0\, - Q => sel0(7), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_psm_ld_chcmd_reg, + Q => sig_child_cmd_reg_full, + R => SR(0) ); -\sig_btt_cntr_im0_reg[15]\: unisim.vcomponents.FDRE +sig_child_error_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => \sig_btt_cntr_im0[15]_i_1_n_0\, - Q => sel0(8), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => \^p_10_out\, + Q => sig_child_error_reg, + R => SR(0) ); -\sig_btt_cntr_im0_reg[1]\: unisim.vcomponents.FDRE +sig_child_qual_burst_type_i_1: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => \sig_btt_cntr_im0[1]_i_1_n_0\, - Q => sig_btt_residue_slice_im0(1), - R => \^sig_init_reg\ + I0 => sig_child_burst_type_reg, + I1 => \^sig_csm_pop_child_cmd\, + I2 => sig_child_qual_burst_type, + O => sig_child_qual_burst_type_i_1_n_0 ); -\sig_btt_cntr_im0_reg[2]\: unisim.vcomponents.FDRE +sig_child_qual_burst_type_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => \sig_btt_cntr_im0[2]_i_1_n_0\, - Q => sig_btt_residue_slice_im0(2), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_child_qual_burst_type_i_1_n_0, + Q => sig_child_qual_burst_type, + R => sig_init_reg ); -\sig_btt_cntr_im0_reg[3]\: unisim.vcomponents.FDRE +sig_child_qual_error_reg_i_1: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => \sig_btt_cntr_im0[3]_i_1_n_0\, - Q => sig_btt_residue_slice_im0(3), - R => \^sig_init_reg\ + I0 => sig_child_error_reg, + I1 => \^sig_csm_pop_child_cmd\, + I2 => \^sig_child_qual_error_reg\, + O => sig_child_qual_error_reg_i_1_n_0 ); -\sig_btt_cntr_im0_reg[4]\: unisim.vcomponents.FDRE +sig_child_qual_error_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => \sig_btt_cntr_im0[4]_i_1_n_0\, - Q => sig_btt_residue_slice_im0(4), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_child_qual_error_reg_i_1_n_0, + Q => \^sig_child_qual_error_reg\, + R => sig_init_reg ); -\sig_btt_cntr_im0_reg[5]\: unisim.vcomponents.FDRE +sig_child_qual_first_of_2_i_1: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"0000000000E2E2E2" ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => \sig_btt_cntr_im0[5]_i_1_n_0\, - Q => sig_btt_residue_slice_im0(5), - R => \^sig_init_reg\ + I0 => \^sig_child_qual_first_of_2\, + I1 => \^sig_csm_pop_child_cmd\, + I2 => sig_needed_2_realign_cmds, + I3 => \^p_32_out\, + I4 => \gpr1.dout_i_reg[9]\(9), + I5 => sig_init_reg, + O => sig_child_qual_first_of_2_i_1_n_0 ); -\sig_btt_cntr_im0_reg[6]\: unisim.vcomponents.FDRE +sig_child_qual_first_of_2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => \sig_btt_cntr_im0[6]_i_1_n_0\, - Q => sig_btt_residue_slice_im0(6), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_child_qual_first_of_2_i_1_n_0, + Q => \^sig_child_qual_first_of_2\, + R => '0' ); -\sig_btt_cntr_im0_reg[7]\: unisim.vcomponents.FDRE +sig_cmd2addr_valid_i_1: unisim.vcomponents.LUT5 generic map( - INIT => '0' + INIT => X"0000CFAA" ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => \sig_btt_cntr_im0[7]_i_1_n_0\, - Q => sel0(0), - R => \^sig_init_reg\ + I0 => sig_csm_ld_xfer, + I1 => FIFO_Full_reg_1, + I2 => sig_inhibit_rdy_n_1, + I3 => \^p_22_out\, + I4 => sig_init_reg, + O => sig_cmd2addr_valid_i_1_n_0 ); -\sig_btt_cntr_im0_reg[8]\: unisim.vcomponents.FDRE +sig_cmd2addr_valid_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => \sig_btt_cntr_im0[8]_i_1_n_0\, - Q => sel0(1), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_cmd2addr_valid_i_1_n_0, + Q => \^p_22_out\, + R => '0' ); -\sig_btt_cntr_im0_reg[9]\: unisim.vcomponents.FDRE +sig_cmd2data_valid_i_1: unisim.vcomponents.LUT5 generic map( - INIT => '0' + INIT => X"0000CFAA" ) port map ( - C => m_axi_mm2s_aclk, - CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, - D => \sig_btt_cntr_im0[9]_i_1_n_0\, - Q => sel0(2), - R => \^sig_init_reg\ + I0 => sig_csm_ld_xfer, + I1 => FIFO_Full_reg_0, + I2 => sig_inhibit_rdy_n_0, + I3 => \^p_11_out\, + I4 => sig_init_reg, + O => sig_cmd2data_valid_i_1_n_0 ); -sig_btt_eq_b2mbaa_ireg1_i_1: unisim.vcomponents.LUT6 +sig_cmd2data_valid_reg: unisim.vcomponents.FDRE generic map( - INIT => X"8008008000000000" + INIT => '0' ) port map ( - I0 => sig_btt_eq_b2mbaa_ireg1_i_2_n_0, - I1 => sig_btt_eq_b2mbaa_ireg1_i_3_n_0, - I2 => sig_btt_residue_slice_im0(6), - I3 => sig_btt_eq_b2mbaa_ireg1_i_4_n_0, - I4 => \sig_addr_cntr_lsh_im0_reg_n_0_[6]\, - I5 => sig_brst_cnt_eq_zero_im0, - O => sig_btt_eq_b2mbaa_im0 + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_cmd2data_valid_i_1_n_0, + Q => \^p_11_out\, + R => '0' ); -sig_btt_eq_b2mbaa_ireg1_i_2: unisim.vcomponents.LUT6 +sig_csm_ld_xfer_i_1: unisim.vcomponents.LUT5 generic map( - INIT => X"0210084020048001" + INIT => X"00010008" ) port map ( - I0 => sig_btt_residue_slice_im0(0), - I1 => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, - I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, - I3 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, - I4 => sig_btt_residue_slice_im0(2), - I5 => sig_btt_residue_slice_im0(1), - O => sig_btt_eq_b2mbaa_ireg1_i_2_n_0 + I0 => sig_csm_state(2), + I1 => sig_csm_state(0), + I2 => \^p_22_out\, + I3 => \^p_11_out\, + I4 => sig_csm_state(1), + O => sig_csm_ld_xfer_ns ); -sig_btt_eq_b2mbaa_ireg1_i_3: unisim.vcomponents.LUT6 +sig_csm_ld_xfer_reg: unisim.vcomponents.FDRE generic map( - INIT => X"9009000000009009" + INIT => '0' ) port map ( - I0 => sig_btt_residue_slice_im0(3), - I1 => \sig_bytes_to_mbaa_ireg1[3]_i_1_n_0\, - I2 => \sig_bytes_to_mbaa_ireg1[5]_i_1_n_0\, - I3 => sig_btt_residue_slice_im0(5), - I4 => \sig_bytes_to_mbaa_ireg1[4]_i_1_n_0\, - I5 => sig_btt_residue_slice_im0(4), - O => sig_btt_eq_b2mbaa_ireg1_i_3_n_0 + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_csm_ld_xfer_ns, + Q => sig_csm_ld_xfer, + R => sig_init_reg ); -sig_btt_eq_b2mbaa_ireg1_i_4: unisim.vcomponents.LUT6 +sig_csm_pop_child_cmd_i_1: unisim.vcomponents.LUT4 generic map( - INIT => X"0000000000000001" + INIT => X"0040" ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[4]\, - I1 => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, - I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, - I3 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, - I4 => \sig_addr_cntr_lsh_im0_reg_n_0_[3]\, - I5 => \sig_addr_cntr_lsh_im0_reg_n_0_[5]\, - O => sig_btt_eq_b2mbaa_ireg1_i_4_n_0 + I0 => sig_csm_state(1), + I1 => sig_child_cmd_reg_full, + I2 => sig_csm_state(0), + I3 => sig_csm_state(2), + O => sig_csm_pop_child_cmd_ns ); -sig_btt_eq_b2mbaa_ireg1_reg: unisim.vcomponents.FDRE +sig_csm_pop_child_cmd_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc1_reg, - D => sig_btt_eq_b2mbaa_im0, - Q => sig_btt_eq_b2mbaa_ireg1, - R => \^sig_init_reg\ - ); -sig_btt_lt_b2mbaa_im01_carry: unisim.vcomponents.CARRY4 - port map ( - CI => '0', - CO(3) => sig_btt_lt_b2mbaa_im01, - CO(2) => sig_btt_lt_b2mbaa_im01_carry_n_1, - CO(1) => sig_btt_lt_b2mbaa_im01_carry_n_2, - CO(0) => sig_btt_lt_b2mbaa_im01_carry_n_3, - CYINIT => '0', - DI(3) => sig_btt_lt_b2mbaa_im01_carry_i_1_n_0, - DI(2) => sig_btt_lt_b2mbaa_im01_carry_i_2_n_0, - DI(1) => sig_btt_lt_b2mbaa_im01_carry_i_3_n_0, - DI(0) => sig_btt_lt_b2mbaa_im01_carry_i_4_n_0, - O(3 downto 0) => NLW_sig_btt_lt_b2mbaa_im01_carry_O_UNCONNECTED(3 downto 0), - S(3) => sig_btt_lt_b2mbaa_im01_carry_i_5_n_0, - S(2) => sig_btt_lt_b2mbaa_im01_carry_i_6_n_0, - S(1) => sig_btt_lt_b2mbaa_im01_carry_i_7_n_0, - S(0) => sig_btt_lt_b2mbaa_im01_carry_i_8_n_0 + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_csm_pop_child_cmd_ns, + Q => \^sig_csm_pop_child_cmd\, + R => sig_init_reg ); -sig_btt_lt_b2mbaa_im01_carry_i_1: unisim.vcomponents.LUT3 +sig_csm_pop_sf_fifo_i_1: unisim.vcomponents.LUT5 generic map( - INIT => X"71" + INIT => X"01000000" ) port map ( - I0 => sig_btt_residue_slice_im0(6), - I1 => \sig_addr_cntr_lsh_im0_reg_n_0_[6]\, - I2 => sig_btt_eq_b2mbaa_ireg1_i_4_n_0, - O => sig_btt_lt_b2mbaa_im01_carry_i_1_n_0 + I0 => sig_csm_state(1), + I1 => \^p_11_out\, + I2 => \^p_22_out\, + I3 => sig_csm_state(0), + I4 => sig_csm_state(2), + O => sig_csm_pop_sf_fifo_ns ); -sig_btt_lt_b2mbaa_im01_carry_i_2: unisim.vcomponents.LUT4 +sig_csm_pop_sf_fifo_reg: unisim.vcomponents.FDRE generic map( - INIT => X"2F02" + INIT => '0' ) port map ( - I0 => \sig_bytes_to_mbaa_ireg1[4]_i_1_n_0\, - I1 => sig_btt_residue_slice_im0(4), - I2 => sig_btt_residue_slice_im0(5), - I3 => \sig_bytes_to_mbaa_ireg1[5]_i_1_n_0\, - O => sig_btt_lt_b2mbaa_im01_carry_i_2_n_0 + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_csm_pop_sf_fifo_ns, + Q => \^p_32_out\, + R => sig_init_reg ); -sig_btt_lt_b2mbaa_im01_carry_i_3: unisim.vcomponents.LUT6 +sig_first_realigner_cmd_i_1: unisim.vcomponents.LUT4 generic map( - INIT => X"0101011337373770" + INIT => X"00F2" ) port map ( - I0 => sig_btt_residue_slice_im0(2), - I1 => sig_btt_residue_slice_im0(3), - I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, - I3 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, - I4 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, - I5 => \sig_addr_cntr_lsh_im0_reg_n_0_[3]\, - O => sig_btt_lt_b2mbaa_im01_carry_i_3_n_0 + I0 => sig_first_realigner_cmd, + I1 => sig_psm_ld_realigner_reg, + I2 => \sig_input_addr_reg[31]_i_2_n_0\, + I3 => sig_init_reg, + O => sig_first_realigner_cmd_i_1_n_0 ); -sig_btt_lt_b2mbaa_im01_carry_i_4: unisim.vcomponents.LUT4 +sig_first_realigner_cmd_reg: unisim.vcomponents.FDRE generic map( - INIT => X"1370" + INIT => '0' ) port map ( - I0 => sig_btt_residue_slice_im0(0), - I1 => sig_btt_residue_slice_im0(1), - I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, - I3 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, - O => sig_btt_lt_b2mbaa_im01_carry_i_4_n_0 + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_first_realigner_cmd_i_1_n_0, + Q => sig_first_realigner_cmd, + R => '0' ); -sig_btt_lt_b2mbaa_im01_carry_i_5: unisim.vcomponents.LUT3 +\sig_input_addr_reg[31]_i_2\: unisim.vcomponents.LUT4 generic map( - INIT => X"86" + INIT => X"0004" ) port map ( - I0 => sig_btt_residue_slice_im0(6), - I1 => \sig_addr_cntr_lsh_im0_reg_n_0_[6]\, - I2 => sig_btt_eq_b2mbaa_ireg1_i_4_n_0, - O => sig_btt_lt_b2mbaa_im01_carry_i_5_n_0 + I0 => Q(0), + I1 => \^sig_input_reg_empty\, + I2 => \^sig_psm_halt\, + I3 => \^p_10_out\, + O => \sig_input_addr_reg[31]_i_2_n_0\ ); -sig_btt_lt_b2mbaa_im01_carry_i_6: unisim.vcomponents.LUT4 +\sig_input_addr_reg_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => X"9009" + INIT => '0' ) port map ( - I0 => \sig_bytes_to_mbaa_ireg1[4]_i_1_n_0\, - I1 => sig_btt_residue_slice_im0(4), - I2 => \sig_bytes_to_mbaa_ireg1[5]_i_1_n_0\, - I3 => sig_btt_residue_slice_im0(5), - O => sig_btt_lt_b2mbaa_im01_carry_i_6_n_0 + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(18), + Q => sig_input_addr_reg(0), + R => sig_input_cache_type_reg0 ); -sig_btt_lt_b2mbaa_im01_carry_i_7: unisim.vcomponents.LUT6 +\sig_input_addr_reg_reg[10]\: unisim.vcomponents.FDRE generic map( - INIT => X"0001666866680001" + INIT => '0' ) port map ( - I0 => sig_btt_residue_slice_im0(2), - I1 => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, - I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, - I3 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, - I4 => \sig_addr_cntr_lsh_im0_reg_n_0_[3]\, - I5 => sig_btt_residue_slice_im0(3), - O => sig_btt_lt_b2mbaa_im01_carry_i_7_n_0 + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(28), + Q => sig_input_addr_reg(10), + R => sig_input_cache_type_reg0 ); -sig_btt_lt_b2mbaa_im01_carry_i_8: unisim.vcomponents.LUT4 +\sig_input_addr_reg_reg[11]\: unisim.vcomponents.FDRE generic map( - INIT => X"1881" + INIT => '0' ) port map ( - I0 => sig_btt_residue_slice_im0(0), - I1 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, - I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, - I3 => sig_btt_residue_slice_im0(1), - O => sig_btt_lt_b2mbaa_im01_carry_i_8_n_0 + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(29), + Q => sig_input_addr_reg(11), + R => sig_input_cache_type_reg0 ); -sig_btt_lt_b2mbaa_ireg1_i_1: unisim.vcomponents.LUT2 +\sig_input_addr_reg_reg[12]\: unisim.vcomponents.FDRE generic map( - INIT => X"8" + INIT => '0' ) port map ( - I0 => sig_btt_lt_b2mbaa_im01, - I1 => sig_brst_cnt_eq_zero_im0, - O => sig_btt_lt_b2mbaa_im0 + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(30), + Q => sig_input_addr_reg(12), + R => sig_input_cache_type_reg0 ); -sig_btt_lt_b2mbaa_ireg1_reg: unisim.vcomponents.FDRE +\sig_input_addr_reg_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc1_reg, - D => sig_btt_lt_b2mbaa_im0, - Q => sig_btt_lt_b2mbaa_ireg1, - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(31), + Q => sig_input_addr_reg(13), + R => sig_input_cache_type_reg0 ); -\sig_byte_change_minus1_im2/i_\: unisim.vcomponents.LUT5 +\sig_input_addr_reg_reg[14]\: unisim.vcomponents.FDRE generic map( - INIT => X"FFFFFFFE" + INIT => '0' ) port map ( - I0 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[3]\, - I1 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[1]\, - I2 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[0]\, - I3 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[2]\, - I4 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[4]\, - O => \sig_byte_change_minus1_im2/i__n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(32), + Q => sig_input_addr_reg(14), + R => sig_input_cache_type_reg0 ); -\sig_bytes_to_mbaa_ireg1[1]_i_1\: unisim.vcomponents.LUT2 +\sig_input_addr_reg_reg[15]\: unisim.vcomponents.FDRE generic map( - INIT => X"6" + INIT => '0' ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, - I1 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, - O => \sig_bytes_to_mbaa_ireg1[1]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(33), + Q => sig_input_addr_reg(15), + R => sig_input_cache_type_reg0 ); -\sig_bytes_to_mbaa_ireg1[2]_i_1\: unisim.vcomponents.LUT3 +\sig_input_addr_reg_reg[16]\: unisim.vcomponents.FDRE generic map( - INIT => X"1E" + INIT => '0' ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, - I1 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, - I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, - O => \sig_bytes_to_mbaa_ireg1[2]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(34), + Q => sig_input_addr_reg(16), + R => sig_input_cache_type_reg0 ); -\sig_bytes_to_mbaa_ireg1[3]_i_1\: unisim.vcomponents.LUT4 +\sig_input_addr_reg_reg[17]\: unisim.vcomponents.FDRE generic map( - INIT => X"01FE" + INIT => '0' ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, - I1 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, - I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, - I3 => \sig_addr_cntr_lsh_im0_reg_n_0_[3]\, - O => \sig_bytes_to_mbaa_ireg1[3]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(35), + Q => sig_input_addr_reg(17), + R => sig_input_cache_type_reg0 ); -\sig_bytes_to_mbaa_ireg1[4]_i_1\: unisim.vcomponents.LUT5 +\sig_input_addr_reg_reg[18]\: unisim.vcomponents.FDRE generic map( - INIT => X"0001FFFE" + INIT => '0' ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[3]\, - I1 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, - I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, - I3 => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, - I4 => \sig_addr_cntr_lsh_im0_reg_n_0_[4]\, - O => \sig_bytes_to_mbaa_ireg1[4]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(36), + Q => sig_input_addr_reg(18), + R => sig_input_cache_type_reg0 ); -\sig_bytes_to_mbaa_ireg1[5]_i_1\: unisim.vcomponents.LUT6 +\sig_input_addr_reg_reg[19]\: unisim.vcomponents.FDRE generic map( - INIT => X"00000001FFFFFFFE" + INIT => '0' ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[4]\, - I1 => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, - I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, - I3 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, - I4 => \sig_addr_cntr_lsh_im0_reg_n_0_[3]\, - I5 => \sig_addr_cntr_lsh_im0_reg_n_0_[5]\, - O => \sig_bytes_to_mbaa_ireg1[5]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(37), + Q => sig_input_addr_reg(19), + R => sig_input_cache_type_reg0 ); -\sig_bytes_to_mbaa_ireg1[6]_i_1\: unisim.vcomponents.LUT6 +\sig_input_addr_reg_reg[1]\: unisim.vcomponents.FDRE generic map( - INIT => X"00000010FFFFFFEF" + INIT => '0' ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[5]\, - I1 => \sig_addr_cntr_lsh_im0_reg_n_0_[3]\, - I2 => \sig_bytes_to_mbaa_ireg1[7]_i_2_n_0\, - I3 => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, - I4 => \sig_addr_cntr_lsh_im0_reg_n_0_[4]\, - I5 => \sig_addr_cntr_lsh_im0_reg_n_0_[6]\, - O => \sig_bytes_to_mbaa_ireg1[6]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(19), + Q => sig_input_addr_reg(1), + R => sig_input_cache_type_reg0 ); -\sig_bytes_to_mbaa_ireg1[7]_i_1\: unisim.vcomponents.LUT6 +\sig_input_addr_reg_reg[20]\: unisim.vcomponents.FDRE generic map( - INIT => X"0000000000000010" + INIT => '0' ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[5]\, - I1 => \sig_addr_cntr_lsh_im0_reg_n_0_[3]\, - I2 => \sig_bytes_to_mbaa_ireg1[7]_i_2_n_0\, - I3 => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, - I4 => \sig_addr_cntr_lsh_im0_reg_n_0_[4]\, - I5 => \sig_addr_cntr_lsh_im0_reg_n_0_[6]\, - O => \sig_bytes_to_mbaa_ireg1[7]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(38), + Q => sig_input_addr_reg(20), + R => sig_input_cache_type_reg0 ); -\sig_bytes_to_mbaa_ireg1[7]_i_2\: unisim.vcomponents.LUT2 +\sig_input_addr_reg_reg[21]\: unisim.vcomponents.FDRE generic map( - INIT => X"1" + INIT => '0' ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, - I1 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, - O => \sig_bytes_to_mbaa_ireg1[7]_i_2_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(39), + Q => sig_input_addr_reg(21), + R => sig_input_cache_type_reg0 ); -\sig_bytes_to_mbaa_ireg1_reg[0]\: unisim.vcomponents.FDRE +\sig_input_addr_reg_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc1_reg, - D => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, - Q => sig_bytes_to_mbaa_ireg1(0), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(40), + Q => sig_input_addr_reg(22), + R => sig_input_cache_type_reg0 ); -\sig_bytes_to_mbaa_ireg1_reg[1]\: unisim.vcomponents.FDRE +\sig_input_addr_reg_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc1_reg, - D => \sig_bytes_to_mbaa_ireg1[1]_i_1_n_0\, - Q => sig_bytes_to_mbaa_ireg1(1), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(41), + Q => sig_input_addr_reg(23), + R => sig_input_cache_type_reg0 ); -\sig_bytes_to_mbaa_ireg1_reg[2]\: unisim.vcomponents.FDRE +\sig_input_addr_reg_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc1_reg, - D => \sig_bytes_to_mbaa_ireg1[2]_i_1_n_0\, - Q => sig_bytes_to_mbaa_ireg1(2), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(42), + Q => sig_input_addr_reg(24), + R => sig_input_cache_type_reg0 ); -\sig_bytes_to_mbaa_ireg1_reg[3]\: unisim.vcomponents.FDRE +\sig_input_addr_reg_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc1_reg, - D => \sig_bytes_to_mbaa_ireg1[3]_i_1_n_0\, - Q => sig_bytes_to_mbaa_ireg1(3), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(43), + Q => sig_input_addr_reg(25), + R => sig_input_cache_type_reg0 ); -\sig_bytes_to_mbaa_ireg1_reg[4]\: unisim.vcomponents.FDRE +\sig_input_addr_reg_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc1_reg, - D => \sig_bytes_to_mbaa_ireg1[4]_i_1_n_0\, - Q => sig_bytes_to_mbaa_ireg1(4), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(44), + Q => sig_input_addr_reg(26), + R => sig_input_cache_type_reg0 ); -\sig_bytes_to_mbaa_ireg1_reg[5]\: unisim.vcomponents.FDRE +\sig_input_addr_reg_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc1_reg, - D => \sig_bytes_to_mbaa_ireg1[5]_i_1_n_0\, - Q => sig_bytes_to_mbaa_ireg1(5), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(45), + Q => sig_input_addr_reg(27), + R => sig_input_cache_type_reg0 ); -\sig_bytes_to_mbaa_ireg1_reg[6]\: unisim.vcomponents.FDRE +\sig_input_addr_reg_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc1_reg, - D => \sig_bytes_to_mbaa_ireg1[6]_i_1_n_0\, - Q => sig_bytes_to_mbaa_ireg1(6), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(46), + Q => sig_input_addr_reg(28), + R => sig_input_cache_type_reg0 ); -\sig_bytes_to_mbaa_ireg1_reg[7]\: unisim.vcomponents.FDRE +\sig_input_addr_reg_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc1_reg, - D => \sig_bytes_to_mbaa_ireg1[7]_i_1_n_0\, - Q => sig_bytes_to_mbaa_ireg1(7), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(47), + Q => sig_input_addr_reg(29), + R => sig_input_cache_type_reg0 ); -sig_calc_error_pushed_i_1: unisim.vcomponents.LUT4 +\sig_input_addr_reg_reg[2]\: unisim.vcomponents.FDRE generic map( - INIT => X"FF80" + INIT => '0' ) port map ( - I0 => \^in\(37), - I1 => sig_xfer_reg_empty, - I2 => sig_ld_xfer_reg, - I3 => \^sig_calc_error_pushed\, - O => sig_calc_error_pushed_i_1_n_0 + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(20), + Q => sig_input_addr_reg(2), + R => sig_input_cache_type_reg0 ); -sig_calc_error_pushed_reg: unisim.vcomponents.FDRE +\sig_input_addr_reg_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => sig_calc_error_pushed_i_1_n_0, - Q => \^sig_calc_error_pushed\, - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(48), + Q => sig_input_addr_reg(30), + R => sig_input_cache_type_reg0 ); -sig_calc_error_reg_reg: unisim.vcomponents.FDRE +\sig_input_addr_reg_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \INFERRED_GEN.cnt_i_reg[2]\, - Q => \^in\(37), - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(49), + Q => sig_input_addr_reg(31), + R => sig_input_cache_type_reg0 ); -sig_cmd2addr_valid_i_1: unisim.vcomponents.LUT6 +\sig_input_addr_reg_reg[3]\: unisim.vcomponents.FDRE generic map( - INIT => X"000000000000AAAE" + INIT => '0' ) port map ( - I0 => \^sig_mstr2addr_cmd_valid\, - I1 => sig_pcc_sm_state(2), - I2 => sig_pcc_sm_state(0), - I3 => sig_pcc_sm_state(1), - I4 => sig_wr_fifo_0, - I5 => \^sig_init_reg\, - O => sig_cmd2addr_valid_i_1_n_0 + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(21), + Q => sig_input_addr_reg(3), + R => sig_input_cache_type_reg0 ); -sig_cmd2addr_valid_reg: unisim.vcomponents.FDRE +\sig_input_addr_reg_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => sig_cmd2addr_valid_i_1_n_0, - Q => \^sig_mstr2addr_cmd_valid\, - R => '0' - ); -sig_cmd2data_valid_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"000000000000AAAE" - ) - port map ( - I0 => \^sig_mstr2data_cmd_valid\, - I1 => sig_pcc_sm_state(2), - I2 => sig_pcc_sm_state(0), - I3 => sig_pcc_sm_state(1), - I4 => sig_wr_fifo, - I5 => \^sig_init_reg\, - O => sig_cmd2data_valid_i_1_n_0 + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(22), + Q => sig_input_addr_reg(4), + R => sig_input_cache_type_reg0 ); -sig_cmd2data_valid_reg: unisim.vcomponents.FDRE +\sig_input_addr_reg_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => sig_cmd2data_valid_i_1_n_0, - Q => \^sig_mstr2data_cmd_valid\, - R => '0' + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(23), + Q => sig_input_addr_reg(5), + R => sig_input_cache_type_reg0 ); -sig_cmd2dre_valid_i_1: unisim.vcomponents.LUT6 +\sig_input_addr_reg_reg[6]\: unisim.vcomponents.FDRE generic map( - INIT => X"00000000F808F8F8" + INIT => '0' ) port map ( - I0 => sig_sm_ld_xfer_reg_ns, - I1 => sig_first_xfer_im0, - I2 => \^sig_mstr2sf_cmd_valid\, - I3 => FIFO_Full_reg_0, - I4 => sig_inhibit_rdy_n, - I5 => \^sig_init_reg\, - O => sig_cmd2dre_valid_i_1_n_0 + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(24), + Q => sig_input_addr_reg(6), + R => sig_input_cache_type_reg0 ); -sig_cmd2dre_valid_i_2: unisim.vcomponents.LUT3 +\sig_input_addr_reg_reg[7]\: unisim.vcomponents.FDRE generic map( - INIT => X"02" + INIT => '0' ) port map ( - I0 => sig_pcc_sm_state(2), - I1 => sig_pcc_sm_state(0), - I2 => sig_pcc_sm_state(1), - O => sig_sm_ld_xfer_reg_ns + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(25), + Q => sig_input_addr_reg(7), + R => sig_input_cache_type_reg0 ); -sig_cmd2dre_valid_reg: unisim.vcomponents.FDRE +\sig_input_addr_reg_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => sig_cmd2dre_valid_i_1_n_0, - Q => \^sig_mstr2sf_cmd_valid\, - R => '0' + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(26), + Q => sig_input_addr_reg(8), + R => sig_input_cache_type_reg0 ); -sig_first_xfer_im0_i_1: unisim.vcomponents.LUT4 +\sig_input_addr_reg_reg[9]\: unisim.vcomponents.FDRE generic map( - INIT => X"000E" + INIT => '0' ) port map ( - I0 => sig_first_xfer_im0, - I1 => sig_push_input_reg11_out, - I2 => sig_pop_xfer_reg0_out, - I3 => \^sig_init_reg\, - O => sig_first_xfer_im0_i_1_n_0 + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(27), + Q => sig_input_addr_reg(9), + R => sig_input_cache_type_reg0 ); -sig_first_xfer_im0_reg: unisim.vcomponents.FDRE +sig_input_burst_type_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => sig_first_xfer_im0_i_1_n_0, - Q => sig_first_xfer_im0, - R => '0' + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(16), + Q => sig_input_burst_type_reg, + R => sig_input_cache_type_reg0 ); -sig_init_done_i_1: unisim.vcomponents.LUT4 +sig_input_eof_reg_reg: unisim.vcomponents.FDRE generic map( - INIT => X"0080" + INIT => '0' ) port map ( - I0 => \^sig_init_reg\, - I1 => sig_init_reg2, - I2 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - I3 => sig_init_done, - O => sig_init_done_reg + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => \out\(17), + Q => sig_input_eof_reg, + R => sig_input_cache_type_reg0 ); -\sig_init_done_i_1__0\: unisim.vcomponents.LUT4 +sig_input_reg_empty_reg: unisim.vcomponents.FDSE generic map( - INIT => X"0080" + INIT => '0' ) port map ( - I0 => \^sig_init_reg\, - I1 => sig_init_reg2, - I2 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - I3 => sig_init_done_2, - O => sig_init_done_reg_0 + C => m_axi_s2mm_aclk, + CE => \sig_input_addr_reg[31]_i_2_n_0\, + D => '0', + Q => \^sig_input_reg_empty\, + S => sig_input_cache_type_reg0 ); -\sig_init_done_i_1__2\: unisim.vcomponents.LUT4 +sig_needed_2_realign_cmds_i_1: unisim.vcomponents.LUT1 generic map( - INIT => X"0080" + INIT => X"1" ) port map ( - I0 => \^sig_init_reg\, - I1 => sig_init_reg2, - I2 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - I3 => sig_init_done_3, - O => sig_init_done_reg_1 + I0 => sig_skip_align2mbaa_s_h, + O => sig_needed_2_realign_cmds_i_1_n_0 ); -\sig_init_done_i_1__3\: unisim.vcomponents.LUT4 +sig_needed_2_realign_cmds_reg: unisim.vcomponents.FDRE generic map( - INIT => X"0080" + INIT => '0' ) port map ( - I0 => \^sig_init_reg\, - I1 => sig_init_reg2, - I2 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - I3 => sig_init_done_4, - O => sig_init_done_reg_2 + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_chcmd_reg, + D => sig_needed_2_realign_cmds_i_1_n_0, + Q => sig_needed_2_realign_cmds, + R => SR(0) ); -sig_input_burst_type_reg_i_1: unisim.vcomponents.LUT3 +sig_psm_halt_i_1: unisim.vcomponents.LUT2 generic map( - INIT => X"FE" + INIT => X"1" ) port map ( - I0 => \^sig_calc_error_pushed\, - I1 => \^sig_init_reg\, - I2 => sig_sm_pop_input_reg, - O => sig_input_cache_type_reg0 + I0 => sig_psm_state(0), + I1 => sig_psm_state(1), + O => sig_psm_halt_ns ); -sig_input_burst_type_reg_i_2: unisim.vcomponents.LUT4 +sig_psm_halt_reg: unisim.vcomponents.FDSE generic map( - INIT => X"0004" + INIT => '0' ) port map ( - I0 => \^in\(37), - I1 => \^sig_input_reg_empty\, - I2 => \^sig_sm_halt_reg\, - I3 => Q(0), - O => sig_push_input_reg11_out + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_psm_halt_ns, + Q => \^sig_psm_halt\, + S => sig_init_reg ); -sig_input_burst_type_reg_reg: unisim.vcomponents.FDRE +sig_psm_ld_calc1_i_1: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"1000" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(16), - Q => \^in\(36), - R => sig_input_cache_type_reg0 + I0 => sig_psm_state(0), + I1 => sig_psm_state(2), + I2 => sig_psm_state(1), + I3 => sig_realign_reg_empty, + O => sig_psm_ld_calc1_ns ); -sig_input_eof_reg_reg: unisim.vcomponents.FDRE +sig_psm_ld_calc1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_input_reg11_out, - D => \out\(17), - Q => sig_mstr2sf_eof, - R => sig_input_cache_type_reg0 + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_psm_ld_calc1_ns, + Q => sig_psm_ld_calc1, + R => sig_init_reg ); -sig_input_reg_empty_i_1: unisim.vcomponents.LUT5 +sig_psm_ld_chcmd_reg_i_1: unisim.vcomponents.LUT4 generic map( - INIT => X"FFFFFFF2" + INIT => X"1000" ) port map ( - I0 => \^sig_input_reg_empty\, - I1 => sig_push_input_reg11_out, - I2 => sig_sm_pop_input_reg, - I3 => \^sig_init_reg\, - I4 => \^sig_calc_error_pushed\, - O => sig_input_reg_empty_i_1_n_0 + I0 => sig_child_cmd_reg_full, + I1 => sig_psm_state(2), + I2 => sig_psm_state(0), + I3 => sig_psm_state(1), + O => sig_psm_ld_chcmd_reg_ns ); -sig_input_reg_empty_reg: unisim.vcomponents.FDRE +sig_psm_ld_chcmd_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, + C => m_axi_s2mm_aclk, CE => '1', - D => sig_input_reg_empty_i_1_n_0, - Q => \^sig_input_reg_empty\, - R => '0' + D => sig_psm_ld_chcmd_reg_ns, + Q => sig_psm_ld_chcmd_reg, + R => sig_init_reg ); -sig_ld_xfer_reg_i_1: unisim.vcomponents.LUT6 +sig_psm_ld_realigner_reg_i_1: unisim.vcomponents.LUT4 generic map( - INIT => X"000000000002FF02" + INIT => X"0820" ) port map ( - I0 => sig_pcc_sm_state(2), - I1 => sig_pcc_sm_state(0), - I2 => sig_pcc_sm_state(1), - I3 => sig_ld_xfer_reg, - I4 => sig_xfer_reg_empty, - I5 => \^sig_init_reg\, - O => sig_ld_xfer_reg_i_1_n_0 + I0 => sig_realign_reg_empty, + I1 => sig_psm_state(2), + I2 => sig_psm_state(1), + I3 => sig_psm_state(0), + O => sig_psm_ld_realigner_reg_ns ); -sig_ld_xfer_reg_reg: unisim.vcomponents.FDRE +sig_psm_ld_realigner_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, + C => m_axi_s2mm_aclk, CE => '1', - D => sig_ld_xfer_reg_i_1_n_0, - Q => sig_ld_xfer_reg, - R => '0' + D => sig_psm_ld_realigner_reg_ns, + Q => sig_psm_ld_realigner_reg, + R => sig_init_reg ); -sig_ld_xfer_reg_tmp_i_1: unisim.vcomponents.LUT6 +sig_psm_pop_input_cmd_i_1: unisim.vcomponents.LUT5 generic map( - INIT => X"000000000000AAAE" + INIT => X"AA800080" ) port map ( - I0 => sig_ld_xfer_reg_tmp, - I1 => sig_pcc_sm_state(2), - I2 => sig_pcc_sm_state(0), - I3 => sig_pcc_sm_state(1), - I4 => sig_pop_xfer_reg0_out, - I5 => \^sig_init_reg\, - O => sig_ld_xfer_reg_tmp_i_1_n_0 + I0 => sig_psm_state(0), + I1 => sig_realign_reg_empty, + I2 => sig_psm_state(2), + I3 => sig_psm_state(1), + I4 => sig_psm_pop_input_cmd_i_2_n_0, + O => sig_psm_pop_input_cmd_ns ); -sig_ld_xfer_reg_tmp_reg: unisim.vcomponents.FDRE +sig_psm_pop_input_cmd_i_2: unisim.vcomponents.LUT5 generic map( - INIT => '0' + INIT => X"00000054" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => sig_ld_xfer_reg_tmp_i_1_n_0, - Q => sig_ld_xfer_reg_tmp, - R => '0' + I0 => sig_child_cmd_reg_full, + I1 => sig_skip_align2mbaa_s_h, + I2 => \sig_psm_state_ns2__0\, + I3 => \^p_10_out\, + I4 => sig_psm_state(2), + O => sig_psm_pop_input_cmd_i_2_n_0 ); -sig_mmap_reset_reg_reg: unisim.vcomponents.FDRE +sig_psm_pop_input_cmd_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, + C => m_axi_s2mm_aclk, CE => '1', - D => SR(0), - Q => \^sig_init_reg\, - R => '0' + D => sig_psm_pop_input_cmd_ns, + Q => sig_psm_pop_input_cmd, + R => sig_init_reg ); -sig_no_btt_residue_ireg1_i_1: unisim.vcomponents.LUT4 +\sig_realign_btt_reg_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => X"0001" + INIT => '0' ) port map ( - I0 => sig_btt_residue_slice_im0(6), - I1 => sig_btt_residue_slice_im0(4), - I2 => sig_btt_residue_slice_im0(5), - I3 => sig_no_btt_residue_ireg1_i_2_n_0, - O => sig_no_btt_residue_im0 + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_realigner_reg, + D => sig_realigner_btt2(0), + Q => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(0), + R => sig_realign_tag_reg0 ); -sig_no_btt_residue_ireg1_i_2: unisim.vcomponents.LUT4 +\sig_realign_btt_reg_reg[10]\: unisim.vcomponents.FDRE generic map( - INIT => X"FFFE" + INIT => '0' ) port map ( - I0 => sig_btt_residue_slice_im0(2), - I1 => sig_btt_residue_slice_im0(3), - I2 => sig_btt_residue_slice_im0(0), - I3 => sig_btt_residue_slice_im0(1), - O => sig_no_btt_residue_ireg1_i_2_n_0 + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_realigner_reg, + D => sig_realigner_btt2(10), + Q => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(10), + R => sig_realign_tag_reg0 ); -sig_no_btt_residue_ireg1_reg: unisim.vcomponents.FDRE +\sig_realign_btt_reg_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc1_reg, - D => sig_no_btt_residue_im0, - Q => sig_no_btt_residue_ireg1, - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_realigner_reg, + D => sig_realigner_btt2(11), + Q => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(11), + R => sig_realign_tag_reg0 ); -sig_parent_done_i_1: unisim.vcomponents.LUT5 +\sig_realign_btt_reg_reg[12]\: unisim.vcomponents.FDRE generic map( - INIT => X"000000E2" + INIT => '0' ) port map ( - I0 => sig_parent_done, - I1 => sig_ld_xfer_reg_tmp, - I2 => sig_last_xfer_valid_im1, - I3 => sig_push_input_reg11_out, - I4 => \^sig_init_reg\, - O => sig_parent_done_i_1_n_0 + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_realigner_reg, + D => sig_realigner_btt2(12), + Q => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(12), + R => sig_realign_tag_reg0 ); -sig_parent_done_reg: unisim.vcomponents.FDRE +\sig_realign_btt_reg_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => sig_parent_done_i_1_n_0, - Q => sig_parent_done, - R => '0' + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_realigner_reg, + D => sig_realigner_btt2(13), + Q => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(13), + R => sig_realign_tag_reg0 ); -\sig_predict_addr_lsh_ireg3[11]_i_2\: unisim.vcomponents.LUT1 +\sig_realign_btt_reg_reg[14]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[11]\, - O => \sig_predict_addr_lsh_ireg3[11]_i_2_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_realigner_reg, + D => sig_realigner_btt2(14), + Q => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(14), + R => sig_realign_tag_reg0 ); -\sig_predict_addr_lsh_ireg3[11]_i_3\: unisim.vcomponents.LUT1 +\sig_realign_btt_reg_reg[15]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[10]\, - O => \sig_predict_addr_lsh_ireg3[11]_i_3_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_realigner_reg, + D => sig_realigner_btt2(15), + Q => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(15), + R => sig_realign_tag_reg0 ); -\sig_predict_addr_lsh_ireg3[11]_i_4\: unisim.vcomponents.LUT1 +\sig_realign_btt_reg_reg[1]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[9]\, - O => \sig_predict_addr_lsh_ireg3[11]_i_4_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_realigner_reg, + D => sig_realigner_btt2(1), + Q => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(1), + R => sig_realign_tag_reg0 ); -\sig_predict_addr_lsh_ireg3[11]_i_5\: unisim.vcomponents.LUT1 +\sig_realign_btt_reg_reg[2]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[8]\, - O => \sig_predict_addr_lsh_ireg3[11]_i_5_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_realigner_reg, + D => sig_realigner_btt2(2), + Q => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(2), + R => sig_realign_tag_reg0 ); -\sig_predict_addr_lsh_ireg3[15]_i_2\: unisim.vcomponents.LUT1 +\sig_realign_btt_reg_reg[3]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => p_1_in_0, - O => \sig_predict_addr_lsh_ireg3[15]_i_2_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_realigner_reg, + D => sig_realigner_btt2(3), + Q => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(3), + R => sig_realign_tag_reg0 ); -\sig_predict_addr_lsh_ireg3[15]_i_3\: unisim.vcomponents.LUT1 +\sig_realign_btt_reg_reg[4]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[14]\, - O => \sig_predict_addr_lsh_ireg3[15]_i_3_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_realigner_reg, + D => sig_realigner_btt2(4), + Q => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(4), + R => sig_realign_tag_reg0 ); -\sig_predict_addr_lsh_ireg3[15]_i_4\: unisim.vcomponents.LUT1 +\sig_realign_btt_reg_reg[5]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[13]\, - O => \sig_predict_addr_lsh_ireg3[15]_i_4_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_realigner_reg, + D => sig_realigner_btt2(5), + Q => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(5), + R => sig_realign_tag_reg0 ); -\sig_predict_addr_lsh_ireg3[15]_i_5\: unisim.vcomponents.LUT1 +\sig_realign_btt_reg_reg[6]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[12]\, - O => \sig_predict_addr_lsh_ireg3[15]_i_5_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_realigner_reg, + D => sig_realigner_btt2(6), + Q => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(6), + R => sig_realign_tag_reg0 ); -\sig_predict_addr_lsh_ireg3[3]_i_2\: unisim.vcomponents.LUT2 +\sig_realign_btt_reg_reg[7]\: unisim.vcomponents.FDRE generic map( - INIT => X"6" + INIT => '0' ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[3]\, - I1 => sig_addr_cntr_incr_ireg2(3), - O => \sig_predict_addr_lsh_ireg3[3]_i_2_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_realigner_reg, + D => sig_realigner_btt2(7), + Q => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(7), + R => sig_realign_tag_reg0 ); -\sig_predict_addr_lsh_ireg3[3]_i_3\: unisim.vcomponents.LUT2 +\sig_realign_btt_reg_reg[8]\: unisim.vcomponents.FDRE generic map( - INIT => X"6" + INIT => '0' ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, - I1 => sig_addr_cntr_incr_ireg2(2), - O => \sig_predict_addr_lsh_ireg3[3]_i_3_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_realigner_reg, + D => sig_realigner_btt2(8), + Q => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(8), + R => sig_realign_tag_reg0 ); -\sig_predict_addr_lsh_ireg3[3]_i_4\: unisim.vcomponents.LUT2 +\sig_realign_btt_reg_reg[9]\: unisim.vcomponents.FDRE generic map( - INIT => X"6" + INIT => '0' ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, - I1 => sig_addr_cntr_incr_ireg2(1), - O => \sig_predict_addr_lsh_ireg3[3]_i_4_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_realigner_reg, + D => sig_realigner_btt2(9), + Q => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(9), + R => sig_realign_tag_reg0 ); -\sig_predict_addr_lsh_ireg3[3]_i_5\: unisim.vcomponents.LUT2 +sig_realign_calc_err_reg_reg: unisim.vcomponents.FDRE generic map( - INIT => X"6" + INIT => '0' ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, - I1 => sig_addr_cntr_incr_ireg2(0), - O => \sig_predict_addr_lsh_ireg3[3]_i_5_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_realigner_reg, + D => \^p_10_out\, + Q => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(18), + R => sig_realign_tag_reg0 ); -\sig_predict_addr_lsh_ireg3[7]_i_2\: unisim.vcomponents.LUT2 +sig_realign_cmd_cmplt_reg_i_1: unisim.vcomponents.LUT3 generic map( - INIT => X"6" + INIT => X"EF" ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[7]\, - I1 => sig_addr_cntr_incr_ireg2(7), - O => \sig_predict_addr_lsh_ireg3[7]_i_2_n_0\ + I0 => \sig_psm_state_ns2__0\, + I1 => \^p_10_out\, + I2 => sig_first_realigner_cmd, + O => sig_realign_cmd_cmplt_reg_i_1_n_0 ); -\sig_predict_addr_lsh_ireg3[7]_i_3\: unisim.vcomponents.LUT2 +sig_realign_cmd_cmplt_reg_reg: unisim.vcomponents.FDRE generic map( - INIT => X"6" + INIT => '0' ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[6]\, - I1 => sig_addr_cntr_incr_ireg2(6), - O => \sig_predict_addr_lsh_ireg3[7]_i_3_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_realigner_reg, + D => sig_realign_cmd_cmplt_reg_i_1_n_0, + Q => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(17), + R => sig_realign_tag_reg0 ); -\sig_predict_addr_lsh_ireg3[7]_i_4\: unisim.vcomponents.LUT2 +sig_realign_eof_reg_i_1: unisim.vcomponents.LUT3 generic map( - INIT => X"6" + INIT => X"A2" ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[5]\, - I1 => sig_addr_cntr_incr_ireg2(5), - O => \sig_predict_addr_lsh_ireg3[7]_i_4_n_0\ + I0 => sig_input_eof_reg, + I1 => sig_first_realigner_cmd, + I2 => \sig_psm_state_ns2__0\, + O => sig_realign_eof_reg0 ); -\sig_predict_addr_lsh_ireg3[7]_i_5\: unisim.vcomponents.LUT2 +sig_realign_eof_reg_reg: unisim.vcomponents.FDRE generic map( - INIT => X"6" + INIT => '0' ) port map ( - I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[4]\, - I1 => sig_addr_cntr_incr_ireg2(4), - O => \sig_predict_addr_lsh_ireg3[7]_i_5_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_realigner_reg, + D => sig_realign_eof_reg0, + Q => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(16), + R => sig_realign_tag_reg0 ); -\sig_predict_addr_lsh_ireg3_reg[0]\: unisim.vcomponents.FDRE +sig_realign_reg_empty_reg: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc3_reg, - D => sig_predict_addr_lsh_im2(0), - Q => \sig_predict_addr_lsh_ireg3_reg_n_0_[0]\, - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_realigner_reg, + D => '0', + Q => sig_realign_reg_empty, + S => sig_realign_tag_reg0 ); -\sig_predict_addr_lsh_ireg3_reg[10]\: unisim.vcomponents.FDRE +sig_realign_reg_full_i_1: unisim.vcomponents.LUT5 generic map( - INIT => '0' + INIT => X"AAAAAEAA" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc3_reg, - D => sig_predict_addr_lsh_im2(10), - Q => \sig_predict_addr_lsh_ireg3_reg_n_0_[10]\, - R => \^sig_init_reg\ + I0 => sig_init_reg, + I1 => \^p_9_out_0\, + I2 => sig_psm_ld_realigner_reg, + I3 => sig_inhibit_rdy_n, + I4 => FIFO_Full_reg, + O => sig_realign_tag_reg0 ); -\sig_predict_addr_lsh_ireg3_reg[11]\: unisim.vcomponents.FDRE +sig_realign_reg_full_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc3_reg, - D => sig_predict_addr_lsh_im2(11), - Q => \sig_predict_addr_lsh_ireg3_reg_n_0_[11]\, - R => \^sig_init_reg\ - ); -\sig_predict_addr_lsh_ireg3_reg[11]_i_1\: unisim.vcomponents.CARRY4 - port map ( - CI => \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_0\, - CO(3) => \sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_0\, - CO(2) => \sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_1\, - CO(1) => \sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_2\, - CO(0) => \sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_3\, - CYINIT => '0', - DI(3) => \sig_addr_cntr_lsh_im0_reg_n_0_[11]\, - DI(2) => \sig_addr_cntr_lsh_im0_reg_n_0_[10]\, - DI(1) => \sig_addr_cntr_lsh_im0_reg_n_0_[9]\, - DI(0) => \sig_addr_cntr_lsh_im0_reg_n_0_[8]\, - O(3 downto 0) => sig_predict_addr_lsh_im2(11 downto 8), - S(3) => \sig_predict_addr_lsh_ireg3[11]_i_2_n_0\, - S(2) => \sig_predict_addr_lsh_ireg3[11]_i_3_n_0\, - S(1) => \sig_predict_addr_lsh_ireg3[11]_i_4_n_0\, - S(0) => \sig_predict_addr_lsh_ireg3[11]_i_5_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_realigner_reg, + D => sig_psm_ld_realigner_reg, + Q => \^p_9_out_0\, + R => sig_realign_tag_reg0 ); -\sig_predict_addr_lsh_ireg3_reg[12]\: unisim.vcomponents.FDRE +\sig_realign_strt_offset_reg[0]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc3_reg, - D => sig_predict_addr_lsh_im2(12), - Q => \sig_predict_addr_lsh_ireg3_reg_n_0_[12]\, - R => \^sig_init_reg\ + I0 => sig_psm_ld_calc1, + I1 => sig_input_addr_reg(0), + O => sig_realign_strt_offset(0) ); -\sig_predict_addr_lsh_ireg3_reg[13]\: unisim.vcomponents.FDRE +\sig_realign_strt_offset_reg[1]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc3_reg, - D => sig_predict_addr_lsh_im2(13), - Q => \sig_predict_addr_lsh_ireg3_reg_n_0_[13]\, - R => \^sig_init_reg\ + I0 => sig_psm_ld_calc1, + I1 => sig_input_addr_reg(1), + O => sig_realign_strt_offset(1) ); -\sig_predict_addr_lsh_ireg3_reg[14]\: unisim.vcomponents.FDRE +\sig_realign_strt_offset_reg[2]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc3_reg, - D => sig_predict_addr_lsh_im2(14), - Q => \sig_predict_addr_lsh_ireg3_reg_n_0_[14]\, - R => \^sig_init_reg\ + I0 => sig_psm_ld_calc1, + I1 => sig_input_addr_reg(2), + O => sig_realign_strt_offset(2) ); -\sig_predict_addr_lsh_ireg3_reg[15]\: unisim.vcomponents.FDRE +\sig_realign_strt_offset_reg_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc3_reg, - D => sig_predict_addr_lsh_im2(15), - Q => sig_predict_addr_lsh_ireg3(15), - R => \^sig_init_reg\ - ); -\sig_predict_addr_lsh_ireg3_reg[15]_i_1\: unisim.vcomponents.CARRY4 - port map ( - CI => \sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_0\, - CO(3) => \NLW_sig_predict_addr_lsh_ireg3_reg[15]_i_1_CO_UNCONNECTED\(3), - CO(2) => \sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_1\, - CO(1) => \sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_2\, - CO(0) => \sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_3\, - CYINIT => '0', - DI(3) => '0', - DI(2) => \sig_addr_cntr_lsh_im0_reg_n_0_[14]\, - DI(1) => \sig_addr_cntr_lsh_im0_reg_n_0_[13]\, - DI(0) => \sig_addr_cntr_lsh_im0_reg_n_0_[12]\, - O(3 downto 0) => sig_predict_addr_lsh_im2(15 downto 12), - S(3) => \sig_predict_addr_lsh_ireg3[15]_i_2_n_0\, - S(2) => \sig_predict_addr_lsh_ireg3[15]_i_3_n_0\, - S(1) => \sig_predict_addr_lsh_ireg3[15]_i_4_n_0\, - S(0) => \sig_predict_addr_lsh_ireg3[15]_i_5_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_realigner_reg, + D => sig_realign_strt_offset(0), + Q => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(19), + R => sig_realign_tag_reg0 ); -\sig_predict_addr_lsh_ireg3_reg[1]\: unisim.vcomponents.FDRE +\sig_realign_strt_offset_reg_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc3_reg, - D => sig_predict_addr_lsh_im2(1), - Q => \sig_predict_addr_lsh_ireg3_reg_n_0_[1]\, - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_realigner_reg, + D => sig_realign_strt_offset(1), + Q => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(20), + R => sig_realign_tag_reg0 ); -\sig_predict_addr_lsh_ireg3_reg[2]\: unisim.vcomponents.FDRE +\sig_realign_strt_offset_reg_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc3_reg, - D => sig_predict_addr_lsh_im2(2), - Q => \sig_predict_addr_lsh_ireg3_reg_n_0_[2]\, - R => \^sig_init_reg\ + C => m_axi_s2mm_aclk, + CE => sig_psm_ld_realigner_reg, + D => sig_realign_strt_offset(2), + Q => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(21), + R => sig_realign_tag_reg0 ); -\sig_predict_addr_lsh_ireg3_reg[3]\: unisim.vcomponents.FDRE +\sig_realigner_btt2[0]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"22F0" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc3_reg, - D => sig_predict_addr_lsh_im2(3), - Q => \sig_predict_addr_lsh_ireg3_reg_n_0_[3]\, - R => \^sig_init_reg\ - ); -\sig_predict_addr_lsh_ireg3_reg[3]_i_1\: unisim.vcomponents.CARRY4 - port map ( - CI => '0', - CO(3) => \sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_0\, - CO(2) => \sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_1\, - CO(1) => \sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_2\, - CO(0) => \sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_3\, - CYINIT => '0', - DI(3) => \sig_addr_cntr_lsh_im0_reg_n_0_[3]\, - DI(2) => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, - DI(1) => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, - DI(0) => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, - O(3 downto 0) => sig_predict_addr_lsh_im2(3 downto 0), - S(3) => \sig_predict_addr_lsh_ireg3[3]_i_2_n_0\, - S(2) => \sig_predict_addr_lsh_ireg3[3]_i_3_n_0\, - S(1) => \sig_predict_addr_lsh_ireg3[3]_i_4_n_0\, - S(0) => \sig_predict_addr_lsh_ireg3[3]_i_5_n_0\ + I0 => sig_input_addr_reg(0), + I1 => \sig_addr_aligned__6\, + I2 => sig_btt_residue_slice(0), + I3 => \sig_realigner_btt2[8]_i_3_n_0\, + O => sig_realigner_btt(0) ); -\sig_predict_addr_lsh_ireg3_reg[4]\: unisim.vcomponents.FDRE +\sig_realigner_btt2[10]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"D0" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc3_reg, - D => sig_predict_addr_lsh_im2(4), - Q => \sig_predict_addr_lsh_ireg3_reg_n_0_[4]\, - R => \^sig_init_reg\ + I0 => sig_first_realigner_cmd, + I1 => sig_skip_align2mbaa, + I2 => sel0(1), + O => sig_realigner_btt(10) ); -\sig_predict_addr_lsh_ireg3_reg[5]\: unisim.vcomponents.FDRE +\sig_realigner_btt2[11]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"D0" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc3_reg, - D => sig_predict_addr_lsh_im2(5), - Q => \sig_predict_addr_lsh_ireg3_reg_n_0_[5]\, - R => \^sig_init_reg\ + I0 => sig_first_realigner_cmd, + I1 => sig_skip_align2mbaa, + I2 => sel0(2), + O => sig_realigner_btt(11) ); -\sig_predict_addr_lsh_ireg3_reg[6]\: unisim.vcomponents.FDRE +\sig_realigner_btt2[12]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"D0" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc3_reg, - D => sig_predict_addr_lsh_im2(6), - Q => \sig_predict_addr_lsh_ireg3_reg_n_0_[6]\, - R => \^sig_init_reg\ + I0 => sig_first_realigner_cmd, + I1 => sig_skip_align2mbaa, + I2 => sel0(3), + O => sig_realigner_btt(12) ); -\sig_predict_addr_lsh_ireg3_reg[7]\: unisim.vcomponents.FDRE +\sig_realigner_btt2[13]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"D0" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc3_reg, - D => sig_predict_addr_lsh_im2(7), - Q => \sig_predict_addr_lsh_ireg3_reg_n_0_[7]\, - R => \^sig_init_reg\ + I0 => sig_first_realigner_cmd, + I1 => sig_skip_align2mbaa, + I2 => sel0(4), + O => sig_realigner_btt(13) ); -\sig_predict_addr_lsh_ireg3_reg[7]_i_1\: unisim.vcomponents.CARRY4 - port map ( - CI => \sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_0\, - CO(3) => \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_0\, - CO(2) => \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_1\, - CO(1) => \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_2\, - CO(0) => \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_3\, - CYINIT => '0', - DI(3) => \sig_addr_cntr_lsh_im0_reg_n_0_[7]\, - DI(2) => \sig_addr_cntr_lsh_im0_reg_n_0_[6]\, - DI(1) => \sig_addr_cntr_lsh_im0_reg_n_0_[5]\, - DI(0) => \sig_addr_cntr_lsh_im0_reg_n_0_[4]\, - O(3 downto 0) => sig_predict_addr_lsh_im2(7 downto 4), - S(3) => \sig_predict_addr_lsh_ireg3[7]_i_2_n_0\, - S(2) => \sig_predict_addr_lsh_ireg3[7]_i_3_n_0\, - S(1) => \sig_predict_addr_lsh_ireg3[7]_i_4_n_0\, - S(0) => \sig_predict_addr_lsh_ireg3[7]_i_5_n_0\ +\sig_realigner_btt2[14]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"D0" + ) + port map ( + I0 => sig_first_realigner_cmd, + I1 => sig_skip_align2mbaa, + I2 => sel0(5), + O => sig_realigner_btt(14) ); -\sig_predict_addr_lsh_ireg3_reg[8]\: unisim.vcomponents.FDRE +\sig_realigner_btt2[15]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFFFF20202000" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc3_reg, - D => sig_predict_addr_lsh_im2(8), - Q => \sig_predict_addr_lsh_ireg3_reg_n_0_[8]\, - R => \^sig_init_reg\ + I0 => sig_first_realigner_cmd, + I1 => sig_skip_align2mbaa, + I2 => \sig_realigner_btt2[15]_i_4_n_0\, + I3 => sig_btt_lt_b2mbaa2, + I4 => sig_btt_eq_b2mbaa2, + I5 => sig_init_reg, + O => \sig_realigner_btt2[15]_i_1_n_0\ ); -\sig_predict_addr_lsh_ireg3_reg[9]\: unisim.vcomponents.FDRE +\sig_realigner_btt2[15]_i_2\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"D0" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_sm_ld_calc3_reg, - D => sig_predict_addr_lsh_im2(9), - Q => \sig_predict_addr_lsh_ireg3_reg_n_0_[9]\, - R => \^sig_init_reg\ + I0 => sig_first_realigner_cmd, + I1 => sig_skip_align2mbaa, + I2 => sel0(6), + O => sig_realigner_btt(15) ); -sig_sm_halt_reg_i_1: unisim.vcomponents.LUT4 +\sig_realigner_btt2[15]_i_3\: unisim.vcomponents.LUT5 generic map( - INIT => X"A181" + INIT => X"FFFFEEEA" ) port map ( - I0 => sig_pcc_sm_state(2), - I1 => sig_pcc_sm_state(0), - I2 => sig_pcc_sm_state(1), - I3 => \^sig_calc_error_pushed\, - O => sig_sm_halt_ns + I0 => \sig_addr_aligned__6\, + I1 => \sig_realigner_btt2[15]_i_4_n_0\, + I2 => sig_btt_lt_b2mbaa2, + I3 => sig_btt_eq_b2mbaa2, + I4 => \^p_10_out\, + O => sig_skip_align2mbaa ); -sig_sm_halt_reg_reg: unisim.vcomponents.FDSE +\sig_realigner_btt2[15]_i_4\: unisim.vcomponents.LUT5 generic map( - INIT => '0' + INIT => X"00010000" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => sig_sm_halt_ns, - Q => \^sig_sm_halt_reg\, - S => \^sig_init_reg\ + I0 => \sig_realigner_btt2[15]_i_5_n_0\, + I1 => sel0(5), + I2 => sel0(4), + I3 => sel0(6), + I4 => sig_first_realigner_cmd, + O => \sig_realigner_btt2[15]_i_4_n_0\ ); -sig_sm_ld_calc1_reg_i_1: unisim.vcomponents.LUT6 +\sig_realigner_btt2[15]_i_5\: unisim.vcomponents.LUT4 generic map( - INIT => X"0008000800083008" + INIT => X"FFFE" ) port map ( - I0 => sig_push_input_reg11_out, - I1 => sig_pcc_sm_state(0), - I2 => sig_pcc_sm_state(2), - I3 => sig_pcc_sm_state(1), - I4 => sig_parent_done, - I5 => \^sig_calc_error_pushed\, - O => sig_sm_ld_calc1_reg_ns + I0 => sel0(2), + I1 => sel0(3), + I2 => sel0(0), + I3 => sel0(1), + O => \sig_realigner_btt2[15]_i_5_n_0\ ); -sig_sm_ld_calc1_reg_reg: unisim.vcomponents.FDRE +\sig_realigner_btt2[1]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => '0' + INIT => X"0606FF00" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => sig_sm_ld_calc1_reg_ns, - Q => sig_sm_ld_calc1_reg, - R => \^sig_init_reg\ + I0 => sig_input_addr_reg(1), + I1 => sig_input_addr_reg(0), + I2 => \sig_addr_aligned__6\, + I3 => sig_btt_residue_slice(1), + I4 => \sig_realigner_btt2[8]_i_3_n_0\, + O => sig_realigner_btt(1) ); -sig_sm_ld_calc2_reg_i_1: unisim.vcomponents.LUT3 +\sig_realigner_btt2[2]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"02" + INIT => X"00560056FFFF0000" ) port map ( - I0 => sig_pcc_sm_state(1), - I1 => sig_pcc_sm_state(2), - I2 => sig_pcc_sm_state(0), - O => sig_sm_ld_calc2_reg_ns + I0 => sig_input_addr_reg(2), + I1 => sig_input_addr_reg(0), + I2 => sig_input_addr_reg(1), + I3 => \sig_addr_aligned__6\, + I4 => sig_btt_residue_slice(2), + I5 => \sig_realigner_btt2[8]_i_3_n_0\, + O => sig_realigner_btt(2) ); -sig_sm_ld_calc2_reg_reg: unisim.vcomponents.FDRE +\sig_realigner_btt2[2]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000001" + ) + port map ( + I0 => sig_input_addr_reg(5), + I1 => sig_input_addr_reg(4), + I2 => sig_input_addr_reg(6), + I3 => sig_input_addr_reg(7), + I4 => \sig_realigner_btt2[2]_i_3_n_0\, + O => \sig_addr_aligned__6\ + ); +\sig_realigner_btt2[2]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => sig_input_addr_reg(2), + I1 => sig_input_addr_reg(3), + I2 => sig_input_addr_reg(0), + I3 => sig_input_addr_reg(1), + O => \sig_realigner_btt2[2]_i_3_n_0\ + ); +\sig_realigner_btt2[3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \sig_bytes_to_mbaa__8\(3), + I1 => sig_btt_residue_slice(3), + I2 => \sig_realigner_btt2[8]_i_3_n_0\, + O => sig_realigner_btt(3) + ); +\sig_realigner_btt2[3]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00005556" + ) + port map ( + I0 => sig_input_addr_reg(3), + I1 => sig_input_addr_reg(1), + I2 => sig_input_addr_reg(0), + I3 => sig_input_addr_reg(2), + I4 => \sig_addr_aligned__6\, + O => \sig_bytes_to_mbaa__8\(3) + ); +\sig_realigner_btt2[4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \sig_bytes_to_mbaa__8\(4), + I1 => sig_btt_residue_slice(4), + I2 => \sig_realigner_btt2[8]_i_3_n_0\, + O => sig_realigner_btt(4) + ); +\sig_realigner_btt2[4]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000055555556" + ) + port map ( + I0 => sig_input_addr_reg(4), + I1 => sig_input_addr_reg(2), + I2 => sig_input_addr_reg(0), + I3 => sig_input_addr_reg(1), + I4 => sig_input_addr_reg(3), + I5 => \sig_addr_aligned__6\, + O => \sig_bytes_to_mbaa__8\(4) + ); +\sig_realigner_btt2[5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \sig_bytes_to_mbaa__8\(5), + I1 => sig_btt_residue_slice(5), + I2 => \sig_realigner_btt2[8]_i_3_n_0\, + O => sig_realigner_btt(5) + ); +\sig_realigner_btt2[5]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"09" + ) + port map ( + I0 => sig_input_addr_reg(5), + I1 => \sig_realigner_btt2[5]_i_3_n_0\, + I2 => \sig_addr_aligned__6\, + O => \sig_bytes_to_mbaa__8\(5) + ); +\sig_realigner_btt2[5]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000001" + ) + port map ( + I0 => sig_input_addr_reg(3), + I1 => sig_input_addr_reg(1), + I2 => sig_input_addr_reg(0), + I3 => sig_input_addr_reg(2), + I4 => sig_input_addr_reg(4), + O => \sig_realigner_btt2[5]_i_3_n_0\ + ); +\sig_realigner_btt2[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \sig_bytes_to_mbaa__8\(6), + I1 => sig_btt_residue_slice(6), + I2 => \sig_realigner_btt2[8]_i_3_n_0\, + O => sig_realigner_btt(6) + ); +\sig_realigner_btt2[6]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"09" + ) + port map ( + I0 => sig_input_addr_reg(6), + I1 => sig_btt_lt_b2mbaa2_carry_i_9_n_0, + I2 => \sig_addr_aligned__6\, + O => \sig_bytes_to_mbaa__8\(6) + ); +\sig_realigner_btt2[7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \sig_bytes_to_mbaa__8\(7), + I1 => sig_btt_residue_slice(7), + I2 => \sig_realigner_btt2[8]_i_3_n_0\, + O => sig_realigner_btt(7) + ); +\sig_realigner_btt2[7]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0059" + ) + port map ( + I0 => sig_input_addr_reg(7), + I1 => sig_btt_lt_b2mbaa2_carry_i_9_n_0, + I2 => sig_input_addr_reg(6), + I3 => \sig_addr_aligned__6\, + O => \sig_bytes_to_mbaa__8\(7) + ); +\sig_realigner_btt2[8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => sig_bytes_to_mbaa(8), + I1 => sig_btt_residue_slice(8), + I2 => \sig_realigner_btt2[8]_i_3_n_0\, + O => sig_realigner_btt(8) + ); +\sig_realigner_btt2[8]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF04" + ) + port map ( + I0 => sig_input_addr_reg(7), + I1 => sig_btt_lt_b2mbaa2_carry_i_9_n_0, + I2 => sig_input_addr_reg(6), + I3 => \sig_addr_aligned__6\, + O => sig_bytes_to_mbaa(8) + ); +\sig_realigner_btt2[8]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000005700000000" + ) + port map ( + I0 => \sig_realigner_btt2[15]_i_4_n_0\, + I1 => sig_btt_lt_b2mbaa2, + I2 => sig_btt_eq_b2mbaa2, + I3 => \sig_addr_aligned__6\, + I4 => \^p_10_out\, + I5 => sig_first_realigner_cmd, + O => \sig_realigner_btt2[8]_i_3_n_0\ + ); +\sig_realigner_btt2[9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"D0" + ) + port map ( + I0 => sig_first_realigner_cmd, + I1 => sig_skip_align2mbaa, + I2 => sel0(0), + O => sig_realigner_btt(9) + ); +\sig_realigner_btt2_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, + C => m_axi_s2mm_aclk, CE => '1', - D => sig_sm_ld_calc2_reg_ns, - Q => sig_sm_ld_calc2_reg, - R => \^sig_init_reg\ + D => sig_realigner_btt(0), + Q => sig_realigner_btt2(0), + R => sig_init_reg ); -sig_sm_ld_calc3_reg_i_1: unisim.vcomponents.LUT3 +\sig_realigner_btt2_reg[10]\: unisim.vcomponents.FDRE generic map( - INIT => X"40" + INIT => '0' ) port map ( - I0 => sig_pcc_sm_state(2), - I1 => sig_pcc_sm_state(0), - I2 => sig_pcc_sm_state(1), - O => sig_sm_ld_calc3_reg_ns + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_realigner_btt(10), + Q => sig_realigner_btt2(10), + R => \sig_realigner_btt2[15]_i_1_n_0\ ); -sig_sm_ld_calc3_reg_reg: unisim.vcomponents.FDRE +\sig_realigner_btt2_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, + C => m_axi_s2mm_aclk, CE => '1', - D => sig_sm_ld_calc3_reg_ns, - Q => sig_sm_ld_calc3_reg, - R => \^sig_init_reg\ + D => sig_realigner_btt(11), + Q => sig_realigner_btt2(11), + R => \sig_realigner_btt2[15]_i_1_n_0\ ); -sig_sm_pop_input_reg_i_1: unisim.vcomponents.LUT5 +\sig_realigner_btt2_reg[12]\: unisim.vcomponents.FDRE generic map( - INIT => X"00200000" + INIT => '0' ) port map ( - I0 => sig_pcc_sm_state(2), - I1 => sig_pcc_sm_state(0), - I2 => sig_parent_done, - I3 => \^sig_calc_error_pushed\, - I4 => sig_pcc_sm_state(1), - O => sig_sm_pop_input_reg_ns + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_realigner_btt(12), + Q => sig_realigner_btt2(12), + R => \sig_realigner_btt2[15]_i_1_n_0\ ); -sig_sm_pop_input_reg_reg: unisim.vcomponents.FDRE +\sig_realigner_btt2_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, + C => m_axi_s2mm_aclk, CE => '1', - D => sig_sm_pop_input_reg_ns, - Q => sig_sm_pop_input_reg, - R => \^sig_init_reg\ + D => sig_realigner_btt(13), + Q => sig_realigner_btt2(13), + R => \sig_realigner_btt2[15]_i_1_n_0\ ); -sig_xfer_reg_empty_i_1: unisim.vcomponents.LUT4 +\sig_realigner_btt2_reg[14]\: unisim.vcomponents.FDRE generic map( - INIT => X"FF2E" + INIT => '0' ) port map ( - I0 => sig_pop_xfer_reg0_out, - I1 => sig_xfer_reg_empty, - I2 => sig_ld_xfer_reg, - I3 => \^sig_init_reg\, - O => sig_xfer_reg_empty_i_1_n_0 + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_realigner_btt(14), + Q => sig_realigner_btt2(14), + R => \sig_realigner_btt2[15]_i_1_n_0\ ); -sig_xfer_reg_empty_reg: unisim.vcomponents.FDRE +\sig_realigner_btt2_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, + C => m_axi_s2mm_aclk, CE => '1', - D => sig_xfer_reg_empty_i_1_n_0, - Q => sig_xfer_reg_empty, - R => '0' + D => sig_realigner_btt(15), + Q => sig_realigner_btt2(15), + R => \sig_realigner_btt2[15]_i_1_n_0\ ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_rd_status_cntl is - port ( - sig_rsc2stat_status_valid : out STD_LOGIC; - sig_rsc2data_ready : out STD_LOGIC; - sig_rd_sts_slverr_reg_reg_0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); - sig_inhibit_rdy_n_reg : in STD_LOGIC; - sig_push_rd_sts_reg : in STD_LOGIC; - sig_rd_sts_reg_full0 : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - sig_coelsc_reg_full_reg : in STD_LOGIC; - sig_rd_sts_decerr_reg0 : in STD_LOGIC; - sig_data2rsc_calc_err : in STD_LOGIC; - sig_data2rsc_slverr : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_rd_status_cntl : entity is "axi_datamover_rd_status_cntl"; -end Arty_Z7_20_axi_vdma_0_0_axi_datamover_rd_status_cntl; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_rd_status_cntl is - signal sig_rd_sts_interr_reg0 : STD_LOGIC; - signal sig_rd_sts_slverr_reg0 : STD_LOGIC; - signal \^sig_rd_sts_slverr_reg_reg_0\ : STD_LOGIC_VECTOR ( 2 downto 0 ); -begin - sig_rd_sts_slverr_reg_reg_0(2 downto 0) <= \^sig_rd_sts_slverr_reg_reg_0\(2 downto 0); -sig_rd_sts_decerr_reg_reg: unisim.vcomponents.FDRE +\sig_realigner_btt2_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_rd_sts_reg, - D => sig_rd_sts_decerr_reg0, - Q => \^sig_rd_sts_slverr_reg_reg_0\(1), - R => sig_inhibit_rdy_n_reg + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_realigner_btt(1), + Q => sig_realigner_btt2(1), + R => sig_init_reg ); -sig_rd_sts_interr_reg_i_1: unisim.vcomponents.LUT2 +\sig_realigner_btt2_reg[2]\: unisim.vcomponents.FDRE generic map( - INIT => X"E" + INIT => '0' ) port map ( - I0 => \^sig_rd_sts_slverr_reg_reg_0\(0), - I1 => sig_data2rsc_calc_err, - O => sig_rd_sts_interr_reg0 + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_realigner_btt(2), + Q => sig_realigner_btt2(2), + R => sig_init_reg ); -sig_rd_sts_interr_reg_reg: unisim.vcomponents.FDRE +\sig_realigner_btt2_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_rd_sts_reg, - D => sig_rd_sts_interr_reg0, - Q => \^sig_rd_sts_slverr_reg_reg_0\(0), - R => sig_inhibit_rdy_n_reg + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_realigner_btt(3), + Q => sig_realigner_btt2(3), + R => sig_init_reg ); -sig_rd_sts_reg_empty_reg: unisim.vcomponents.FDSE +\sig_realigner_btt2_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_rd_sts_reg, - D => sig_coelsc_reg_full_reg, - Q => sig_rsc2data_ready, - S => sig_inhibit_rdy_n_reg + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_realigner_btt(4), + Q => sig_realigner_btt2(4), + R => sig_init_reg ); -sig_rd_sts_reg_full_reg: unisim.vcomponents.FDRE +\sig_realigner_btt2_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_rd_sts_reg, - D => sig_rd_sts_reg_full0, - Q => sig_rsc2stat_status_valid, - R => sig_inhibit_rdy_n_reg + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_realigner_btt(5), + Q => sig_realigner_btt2(5), + R => sig_init_reg ); -sig_rd_sts_slverr_reg_i_1: unisim.vcomponents.LUT2 +\sig_realigner_btt2_reg[6]\: unisim.vcomponents.FDRE generic map( - INIT => X"E" + INIT => '0' ) port map ( - I0 => \^sig_rd_sts_slverr_reg_reg_0\(2), - I1 => sig_data2rsc_slverr, - O => sig_rd_sts_slverr_reg0 + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_realigner_btt(6), + Q => sig_realigner_btt2(6), + R => sig_init_reg ); -sig_rd_sts_slverr_reg_reg: unisim.vcomponents.FDRE +\sig_realigner_btt2_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_rd_sts_reg, - D => sig_rd_sts_slverr_reg0, - Q => \^sig_rd_sts_slverr_reg_reg_0\(2), - R => sig_inhibit_rdy_n_reg + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_realigner_btt(7), + Q => sig_realigner_btt2(7), + R => sig_init_reg ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_reset is - port ( - sig_cmd_stat_rst_user_reg_n_cdc_from_reg : out STD_LOGIC; - mm2s_halt_cmplt : out STD_LOGIC; - SR : out STD_LOGIC_VECTOR ( 0 to 0 ); - sig_rst2all_stop_request : out STD_LOGIC; - sig_halt_reg_reg : out STD_LOGIC; - \out\ : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - sig_halt_reg_reg_0 : in STD_LOGIC; - halt_i_reg : in STD_LOGIC; - sig_data2addr_stop_req : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_reset : entity is "axi_datamover_reset"; -end Arty_Z7_20_axi_vdma_0_0_axi_datamover_reset; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_reset is - signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \^sig_cmd_stat_rst_user_reg_n_cdc_from_reg\ : STD_LOGIC; - signal \^sig_rst2all_stop_request\ : STD_LOGIC; -begin - SR(0) <= \^sr\(0); - sig_cmd_stat_rst_user_reg_n_cdc_from_reg <= \^sig_cmd_stat_rst_user_reg_n_cdc_from_reg\; - sig_rst2all_stop_request <= \^sig_rst2all_stop_request\; -\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_4\: unisim.vcomponents.LUT1 +\sig_realigner_btt2_reg[8]\: unisim.vcomponents.FDRE generic map( - INIT => X"1" + INIT => '0' ) port map ( - I0 => \^sig_cmd_stat_rst_user_reg_n_cdc_from_reg\, - O => \^sr\(0) + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_realigner_btt(8), + Q => sig_realigner_btt2(8), + R => sig_init_reg ); -\sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\: unisim.vcomponents.FDRE +\sig_realigner_btt2_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, + C => m_axi_s2mm_aclk, CE => '1', - D => \out\, - Q => \^sig_cmd_stat_rst_user_reg_n_cdc_from_reg\, - R => '0' + D => sig_realigner_btt(9), + Q => sig_realigner_btt2(9), + R => \sig_realigner_btt2[15]_i_1_n_0\ ); -sig_halt_cmplt_reg: unisim.vcomponents.FDRE +sig_skip_align2mbaa_s_h_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000CC0A" + ) + port map ( + I0 => sig_skip_align2mbaa_s_h, + I1 => sig_skip_align2mbaa, + I2 => sig_psm_ld_chcmd_reg, + I3 => sig_psm_ld_realigner_reg, + I4 => sig_init_reg, + O => sig_skip_align2mbaa_s_h_i_1_n_0 + ); +sig_skip_align2mbaa_s_h_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, + C => m_axi_s2mm_aclk, CE => '1', - D => sig_halt_reg_reg_0, - Q => mm2s_halt_cmplt, - R => \^sr\(0) + D => sig_skip_align2mbaa_s_h_i_1_n_0, + Q => sig_skip_align2mbaa_s_h, + R => '0' ); -sig_halt_reg_i_1: unisim.vcomponents.LUT2 +\sig_xfer_addr_reg[31]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"E" + INIT => X"AAAAAAAAFAFFBABA" ) port map ( - I0 => \^sig_rst2all_stop_request\, - I1 => sig_data2addr_stop_req, - O => sig_halt_reg_reg + I0 => sig_init_reg, + I1 => \^p_11_out\, + I2 => \sig_clr_cmd2addr_valid3_out__0\, + I3 => \^p_22_out\, + I4 => \sig_clr_cmd2data_valid4_out__0\, + I5 => sig_csm_ld_xfer, + O => sig_xfer_cache_reg0 ); -sig_s_h_halt_reg_reg: unisim.vcomponents.FDRE +\sig_xfer_addr_reg_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => halt_i_reg, - Q => \^sig_rst2all_stop_request\, - R => \^sr\(0) + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => \^sig_xfer_addr_reg_reg[2]_0\(0), + Q => \in\(0), + R => sig_xfer_cache_reg0 ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_cmdsts_if is - port ( - \cmnds_queued_reg[7]\ : out STD_LOGIC; - err_i_reg_0 : out STD_LOGIC; - \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg\ : out STD_LOGIC; - err_i_reg_1 : out STD_LOGIC; - dmacntrl_ns14_out : out STD_LOGIC; - p_3_in : out STD_LOGIC; - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : out STD_LOGIC; - \FSM_sequential_dmacntrl_cs_reg[1]\ : out STD_LOGIC; - dma_decerr_reg : out STD_LOGIC; - dma_slverr_reg : out STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[1]\ : out STD_LOGIC; - \sig_addr_cntr_lsh_kh_reg[31]\ : out STD_LOGIC_VECTOR ( 48 downto 0 ); - \out\ : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - p_0_in : in STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[2]\ : in STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[2]_0\ : in STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[2]_1\ : in STD_LOGIC; - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - E : in STD_LOGIC_VECTOR ( 0 to 0 ); - \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg_0\ : in STD_LOGIC; - mm2s_halt : in STD_LOGIC; - p_68_out : in STD_LOGIC_VECTOR ( 1 downto 0 ); - frame_sync_reg : in STD_LOGIC; - \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\ : in STD_LOGIC; - zero_hsize_err : in STD_LOGIC; - zero_vsize_err : in STD_LOGIC; - dma_decerr_reg_0 : in STD_LOGIC; - dma_slverr_reg_0 : in STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[2]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - D : in STD_LOGIC_VECTOR ( 48 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_cmdsts_if : entity is "axi_vdma_cmdsts_if"; -end Arty_Z7_20_axi_vdma_0_0_axi_vdma_cmdsts_if; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_cmdsts_if is - signal \^cmnds_queued_reg[7]\ : STD_LOGIC; - signal err_i_i_1_n_0 : STD_LOGIC; - signal \^err_i_reg_0\ : STD_LOGIC; - signal \^err_i_reg_1\ : STD_LOGIC; - signal p_53_out : STD_LOGIC; - signal p_54_out : STD_LOGIC; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \FSM_sequential_dmacntrl_cs[1]_i_3\ : label is "soft_lutpair6"; - attribute SOFT_HLUTNM of \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_i_2\ : label is "soft_lutpair6"; -begin - \cmnds_queued_reg[7]\ <= \^cmnds_queued_reg[7]\; - err_i_reg_0 <= \^err_i_reg_0\; - err_i_reg_1 <= \^err_i_reg_1\; -\FSM_sequential_dmacntrl_cs[0]_i_5\: unisim.vcomponents.LUT3 +\sig_xfer_addr_reg_reg[10]\: unisim.vcomponents.FDRE generic map( - INIT => X"FE" + INIT => '0' ) port map ( - I0 => \^err_i_reg_1\, - I1 => p_68_out(1), - I2 => mm2s_halt, - O => p_3_in + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => sig_child_addr_cntr_lsh_reg(10), + Q => \in\(10), + R => sig_xfer_cache_reg0 ); -\FSM_sequential_dmacntrl_cs[1]_i_3\: unisim.vcomponents.LUT5 +\sig_xfer_addr_reg_reg[11]\: unisim.vcomponents.FDRE generic map( - INIT => X"FFFEFFFF" + INIT => '0' ) port map ( - I0 => \^err_i_reg_1\, - I1 => p_68_out(1), - I2 => mm2s_halt, - I3 => frame_sync_reg, - I4 => p_68_out(0), - O => \FSM_sequential_dmacntrl_cs_reg[1]\ + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => sig_child_addr_cntr_lsh_reg(11), + Q => \in\(11), + R => sig_xfer_cache_reg0 ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_3\: unisim.vcomponents.LUT6 +\sig_xfer_addr_reg_reg[12]\: unisim.vcomponents.FDRE generic map( - INIT => X"0000100000000000" + INIT => '0' ) port map ( - I0 => \^err_i_reg_1\, - I1 => p_68_out(1), - I2 => p_68_out(0), - I3 => \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\, - I4 => mm2s_halt, - I5 => frame_sync_reg, - O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => sig_child_addr_cntr_lsh_reg(12), + Q => \in\(12), + R => sig_xfer_cache_reg0 ); -\GEN_NORMAL_DM_COMMAND.cmnd_wr_i_i_2\: unisim.vcomponents.LUT4 +\sig_xfer_addr_reg_reg[13]\: unisim.vcomponents.FDRE generic map( - INIT => X"FFFE" + INIT => '0' ) port map ( - I0 => mm2s_halt, - I1 => p_68_out(1), - I2 => \^err_i_reg_1\, - I3 => frame_sync_reg, - O => dmacntrl_ns14_out + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => sig_child_addr_cntr_lsh_reg(13), + Q => \in\(13), + R => sig_xfer_cache_reg0 ); -\INFERRED_GEN.cnt_i[1]_i_2\: unisim.vcomponents.LUT2 +\sig_xfer_addr_reg_reg[14]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => \^cmnds_queued_reg[7]\, - I1 => \INFERRED_GEN.cnt_i_reg[2]_2\(0), - O => \INFERRED_GEN.cnt_i_reg[1]\ + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => sig_child_addr_cntr_lsh_reg(14), + Q => \in\(14), + R => sig_xfer_cache_reg0 ); -decerr_i_reg: unisim.vcomponents.FDRE +\sig_xfer_addr_reg_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \INFERRED_GEN.cnt_i_reg[2]\, - Q => p_54_out, - R => p_0_in + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => p_1_in, + Q => \in\(15), + R => sig_xfer_cache_reg0 ); -dma_decerr_i_1: unisim.vcomponents.LUT2 +\sig_xfer_addr_reg_reg[16]\: unisim.vcomponents.FDRE generic map( - INIT => X"E" + INIT => '0' ) port map ( - I0 => p_54_out, - I1 => dma_decerr_reg_0, - O => dma_decerr_reg + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => sig_child_addr_cntr_msh_reg(0), + Q => \in\(16), + R => sig_xfer_cache_reg0 ); -dma_slverr_i_1: unisim.vcomponents.LUT2 +\sig_xfer_addr_reg_reg[17]\: unisim.vcomponents.FDRE generic map( - INIT => X"E" + INIT => '0' ) port map ( - I0 => p_53_out, - I1 => dma_slverr_reg_0, - O => dma_slverr_reg + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => sig_child_addr_cntr_msh_reg(1), + Q => \in\(17), + R => sig_xfer_cache_reg0 ); -err_i_i_1: unisim.vcomponents.LUT6 +\sig_xfer_addr_reg_reg[18]\: unisim.vcomponents.FDRE generic map( - INIT => X"FFFFFFFFFFFFFFFE" + INIT => '0' ) port map ( - I0 => p_53_out, - I1 => zero_hsize_err, - I2 => zero_vsize_err, - I3 => \^err_i_reg_0\, - I4 => p_54_out, - I5 => \^err_i_reg_1\, - O => err_i_i_1_n_0 + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => sig_child_addr_cntr_msh_reg(2), + Q => \in\(18), + R => sig_xfer_cache_reg0 ); -err_i_reg: unisim.vcomponents.FDRE +\sig_xfer_addr_reg_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => err_i_i_1_n_0, - Q => \^err_i_reg_1\, - R => p_0_in + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => sig_child_addr_cntr_msh_reg(3), + Q => \in\(19), + R => sig_xfer_cache_reg0 ); -interr_i_reg: unisim.vcomponents.FDRE +\sig_xfer_addr_reg_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \INFERRED_GEN.cnt_i_reg[2]_1\, - Q => \^err_i_reg_0\, - R => p_0_in + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => \^sig_xfer_addr_reg_reg[2]_0\(1), + Q => \in\(1), + R => sig_xfer_cache_reg0 ); -\s_axis_cmd_tdata_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(0), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(0), - R => SR(0) +\sig_xfer_addr_reg_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => sig_child_addr_cntr_msh_reg(4), + Q => \in\(20), + R => sig_xfer_cache_reg0 ); -\s_axis_cmd_tdata_reg[10]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(10), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(10), - R => SR(0) +\sig_xfer_addr_reg_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => sig_child_addr_cntr_msh_reg(5), + Q => \in\(21), + R => sig_xfer_cache_reg0 ); -\s_axis_cmd_tdata_reg[11]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(11), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(11), - R => SR(0) +\sig_xfer_addr_reg_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => sig_child_addr_cntr_msh_reg(6), + Q => \in\(22), + R => sig_xfer_cache_reg0 ); -\s_axis_cmd_tdata_reg[12]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(12), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(12), - R => SR(0) +\sig_xfer_addr_reg_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => sig_child_addr_cntr_msh_reg(7), + Q => \in\(23), + R => sig_xfer_cache_reg0 ); -\s_axis_cmd_tdata_reg[13]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(13), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(13), - R => SR(0) +\sig_xfer_addr_reg_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => sig_child_addr_cntr_msh_reg(8), + Q => \in\(24), + R => sig_xfer_cache_reg0 ); -\s_axis_cmd_tdata_reg[14]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(14), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(14), - R => SR(0) +\sig_xfer_addr_reg_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => sig_child_addr_cntr_msh_reg(9), + Q => \in\(25), + R => sig_xfer_cache_reg0 ); -\s_axis_cmd_tdata_reg[15]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(15), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(15), - R => SR(0) +\sig_xfer_addr_reg_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => sig_child_addr_cntr_msh_reg(10), + Q => \in\(26), + R => sig_xfer_cache_reg0 ); -\s_axis_cmd_tdata_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(1), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(1), - R => SR(0) +\sig_xfer_addr_reg_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => sig_child_addr_cntr_msh_reg(11), + Q => \in\(27), + R => sig_xfer_cache_reg0 ); -\s_axis_cmd_tdata_reg[23]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(16), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(16), - R => SR(0) +\sig_xfer_addr_reg_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => sig_child_addr_cntr_msh_reg(12), + Q => \in\(28), + R => sig_xfer_cache_reg0 ); -\s_axis_cmd_tdata_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(2), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(2), - R => SR(0) +\sig_xfer_addr_reg_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => sig_child_addr_cntr_msh_reg(13), + Q => \in\(29), + R => sig_xfer_cache_reg0 ); -\s_axis_cmd_tdata_reg[32]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(17), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(17), - R => SR(0) +\sig_xfer_addr_reg_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => \^sig_xfer_addr_reg_reg[2]_0\(2), + Q => \in\(2), + R => sig_xfer_cache_reg0 ); -\s_axis_cmd_tdata_reg[33]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(18), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(18), - R => SR(0) +\sig_xfer_addr_reg_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => sig_child_addr_cntr_msh_reg(14), + Q => \in\(30), + R => sig_xfer_cache_reg0 ); -\s_axis_cmd_tdata_reg[34]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(19), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(19), - R => SR(0) +\sig_xfer_addr_reg_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => sig_child_addr_cntr_msh_reg(15), + Q => \in\(31), + R => sig_xfer_cache_reg0 ); -\s_axis_cmd_tdata_reg[35]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(20), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(20), - R => SR(0) +\sig_xfer_addr_reg_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => sig_child_addr_cntr_lsh_reg(3), + Q => \in\(3), + R => sig_xfer_cache_reg0 ); -\s_axis_cmd_tdata_reg[36]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(21), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(21), - R => SR(0) +\sig_xfer_addr_reg_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => sig_child_addr_cntr_lsh_reg(4), + Q => \in\(4), + R => sig_xfer_cache_reg0 ); -\s_axis_cmd_tdata_reg[37]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(22), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(22), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[38]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(23), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(23), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[39]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(24), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(24), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(3), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(3), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[40]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(25), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(25), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[41]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(26), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(26), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[42]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(27), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(27), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[43]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(28), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(28), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[44]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(29), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(29), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[45]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(30), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(30), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[46]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(31), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(31), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[47]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(32), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(32), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[48]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(33), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(33), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[49]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(34), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(34), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(4), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(4), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[50]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(35), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(35), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[51]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(36), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(36), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[52]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(37), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(37), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[53]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(38), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(38), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[54]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(39), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(39), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[55]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(40), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(40), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[56]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(41), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(41), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[57]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(42), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(42), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[58]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(43), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(43), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[59]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(44), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(44), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(5), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(5), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[60]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(45), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(45), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[61]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(46), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(46), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[62]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(47), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(47), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[63]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(48), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(48), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(6), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(6), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(7), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(7), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[8]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(8), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(8), - R => SR(0) - ); -\s_axis_cmd_tdata_reg[9]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(9), - Q => \sig_addr_cntr_lsh_kh_reg[31]\(9), - R => SR(0) - ); -s_axis_cmd_tvalid_reg: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg_0\, - Q => \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg\, - R => SR(0) - ); -slverr_i_reg: unisim.vcomponents.FDRE +\sig_xfer_addr_reg_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \INFERRED_GEN.cnt_i_reg[2]_0\, - Q => p_53_out, - R => p_0_in + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => sig_child_addr_cntr_lsh_reg(5), + Q => \in\(5), + R => sig_xfer_cache_reg0 ); -sts_tready_reg: unisim.vcomponents.FDRE +\sig_xfer_addr_reg_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \out\, - Q => \^cmnds_queued_reg[7]\, - R => '0' + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => sig_child_addr_cntr_lsh_reg(6), + Q => \in\(6), + R => sig_xfer_cache_reg0 ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_fsync_gen is - port ( - p_23_out : out STD_LOGIC; - mask_fsync_out_i : out STD_LOGIC; - p_45_out : out STD_LOGIC; - prmry_in_xored : out STD_LOGIC; - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - p_36_out : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - p_2_out : in STD_LOGIC; - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\ : in STD_LOGIC; - p_46_out : in STD_LOGIC; - p_68_out : in STD_LOGIC_VECTOR ( 0 to 0 ); - p_in_d1_cdc_from : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_fsync_gen : entity is "axi_vdma_fsync_gen"; -end Arty_Z7_20_axi_vdma_0_0_axi_vdma_fsync_gen; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_fsync_gen is - signal all_idle_d1 : STD_LOGIC; - signal all_idle_d2 : STD_LOGIC; - signal p_22_out : STD_LOGIC; - signal \^p_23_out\ : STD_LOGIC; - signal p_8_out : STD_LOGIC; -begin - p_23_out <= \^p_23_out\; -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__5\: unisim.vcomponents.LUT2 +\sig_xfer_addr_reg_reg[7]\: unisim.vcomponents.FDRE generic map( - INIT => X"6" + INIT => '0' ) port map ( - I0 => p_22_out, - I1 => p_in_d1_cdc_from, - O => prmry_in_xored + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => sig_child_addr_cntr_lsh_reg(7), + Q => \in\(7), + R => sig_xfer_cache_reg0 ); -\GEN_FREE_RUN_MODE.all_idle_d1_reg\: unisim.vcomponents.FDRE +\sig_xfer_addr_reg_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => p_36_out, - Q => all_idle_d1, - R => SR(0) + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => sig_child_addr_cntr_lsh_reg(8), + Q => \in\(8), + R => sig_xfer_cache_reg0 ); -\GEN_FREE_RUN_MODE.all_idle_d2_reg\: unisim.vcomponents.FDRE +\sig_xfer_addr_reg_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => all_idle_d1, - Q => all_idle_d2, - R => SR(0) + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => sig_child_addr_cntr_lsh_reg(9), + Q => \in\(9), + R => sig_xfer_cache_reg0 ); -\GEN_FREE_RUN_MODE.frame_sync_i_i_1\: unisim.vcomponents.LUT3 +sig_xfer_calc_err_reg_reg: unisim.vcomponents.FDRE generic map( - INIT => X"40" + INIT => '0' ) port map ( - I0 => all_idle_d2, - I1 => all_idle_d1, - I2 => p_68_out(0), - O => p_8_out + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => \^sig_child_qual_error_reg\, + Q => \in\(39), + R => sig_xfer_cache_reg0 ); -\GEN_FREE_RUN_MODE.frame_sync_i_reg\: unisim.vcomponents.FDRE +sig_xfer_cmd_cmplt_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => p_8_out, - Q => \^p_23_out\, - R => SR(0) - ); -\GEN_FREE_RUN_MODE.frame_sync_out_reg\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => p_2_out, - Q => p_22_out, - R => SR(0) + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => sig_xfer_cmd_cmplt_reg0, + Q => sig_next_cmd_cmplt_reg_reg(1), + R => sig_xfer_cache_reg0 ); -\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg\: unisim.vcomponents.FDRE +sig_xfer_is_seq_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\, - Q => mask_fsync_out_i, - R => '0' + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => \gpr1.dout_i_reg[10]\, + Q => sig_next_cmd_cmplt_reg_reg(0), + R => sig_xfer_cache_reg0 ); -\MASTER_MODE_FRAME_CNT.valid_frame_sync_d1_i_1\: unisim.vcomponents.LUT2 +\sig_xfer_len_reg[0]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"8" + INIT => X"FE01" ) port map ( - I0 => \^p_23_out\, - I1 => p_46_out, - O => p_45_out + I0 => \^sig_adjusted_addr_incr\(2), + I1 => \^sig_adjusted_addr_incr\(0), + I2 => \^sig_adjusted_addr_incr\(1), + I3 => \^sig_adjusted_addr_incr\(3), + O => \sig_xfer_len_reg[0]_i_1_n_0\ ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_genlock_mngr is - port ( - p_44_out : out STD_LOGIC; - in0 : out STD_LOGIC_VECTOR ( 0 to 0 ); - p_0_in : in STD_LOGIC; - valid_frame_sync_d2 : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - p_68_out : in STD_LOGIC_VECTOR ( 0 to 0 ); - \out\ : in STD_LOGIC; - p_67_out : in STD_LOGIC; - Q : in STD_LOGIC_VECTOR ( 4 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_genlock_mngr : entity is "axi_vdma_genlock_mngr"; -end Arty_Z7_20_axi_vdma_0_0_axi_vdma_genlock_mngr; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_genlock_mngr is - signal \GENLOCK_FOR_MASTER.mstr_reverse_order_i_1_n_0\ : STD_LOGIC; - signal \GENLOCK_FOR_MASTER.mstr_reverse_order_i_2_n_0\ : STD_LOGIC; - signal mstr_reverse_order : STD_LOGIC; - signal mstr_reverse_order_d1 : STD_LOGIC; - signal mstr_reverse_order_d2 : STD_LOGIC; - signal s_frame_ptr_out : STD_LOGIC; -begin -\GENLOCK_FOR_MASTER.frame_ptr_out[0]_i_1\: unisim.vcomponents.LUT1 +\sig_xfer_len_reg[1]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"1" + INIT => X"FFFE0001" ) port map ( - I0 => mstr_reverse_order_d2, - O => s_frame_ptr_out + I0 => \^sig_adjusted_addr_incr\(3), + I1 => \^sig_adjusted_addr_incr\(1), + I2 => \^sig_adjusted_addr_incr\(0), + I3 => \^sig_adjusted_addr_incr\(2), + I4 => \^sig_adjusted_addr_incr\(4), + O => \sig_xfer_len_reg[1]_i_1_n_0\ ); -\GENLOCK_FOR_MASTER.frame_ptr_out_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => s_frame_ptr_out, - Q => in0(0), - R => p_0_in +\sig_xfer_len_reg[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFE00000001" + ) + port map ( + I0 => \^sig_adjusted_addr_incr\(4), + I1 => \^sig_adjusted_addr_incr\(2), + I2 => \^sig_adjusted_addr_incr\(0), + I3 => \^sig_adjusted_addr_incr\(1), + I4 => \^sig_adjusted_addr_incr\(3), + I5 => \^sig_adjusted_addr_incr\(5), + O => \sig_xfer_len_reg[2]_i_1_n_0\ ); -\GENLOCK_FOR_MASTER.mstr_reverse_order_d1_reg\: unisim.vcomponents.FDSE +\sig_xfer_len_reg_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => mstr_reverse_order, - Q => mstr_reverse_order_d1, - S => p_0_in + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => \sig_xfer_len_reg[0]_i_1_n_0\, + Q => \in\(32), + R => sig_xfer_cache_reg0 ); -\GENLOCK_FOR_MASTER.mstr_reverse_order_d2_reg\: unisim.vcomponents.FDSE +\sig_xfer_len_reg_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => mstr_reverse_order_d1, - Q => mstr_reverse_order_d2, - S => p_0_in + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => \sig_xfer_len_reg[1]_i_1_n_0\, + Q => \in\(33), + R => sig_xfer_cache_reg0 ); -\GENLOCK_FOR_MASTER.mstr_reverse_order_i_1\: unisim.vcomponents.LUT6 +\sig_xfer_len_reg_reg[2]\: unisim.vcomponents.FDRE generic map( - INIT => X"FFFFFFFF6AAAFFFF" + INIT => '0' ) port map ( - I0 => mstr_reverse_order, - I1 => \GENLOCK_FOR_MASTER.mstr_reverse_order_i_2_n_0\, - I2 => valid_frame_sync_d2, - I3 => p_68_out(0), - I4 => \out\, - I5 => p_67_out, - O => \GENLOCK_FOR_MASTER.mstr_reverse_order_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => \sig_xfer_len_reg[2]_i_1_n_0\, + Q => \in\(34), + R => sig_xfer_cache_reg0 ); -\GENLOCK_FOR_MASTER.mstr_reverse_order_i_2\: unisim.vcomponents.LUT5 +\sig_xfer_len_reg_reg[3]\: unisim.vcomponents.FDRE generic map( - INIT => X"00000001" + INIT => '0' ) port map ( - I0 => Q(4), - I1 => Q(2), - I2 => Q(1), - I3 => Q(0), - I4 => Q(3), - O => \GENLOCK_FOR_MASTER.mstr_reverse_order_i_2_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => D(0), + Q => \in\(35), + R => sig_xfer_cache_reg0 ); -\GENLOCK_FOR_MASTER.mstr_reverse_order_reg\: unisim.vcomponents.FDRE +\sig_xfer_len_reg_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GENLOCK_FOR_MASTER.mstr_reverse_order_i_1_n_0\, - Q => mstr_reverse_order, - R => '0' + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => D(1), + Q => \in\(36), + R => sig_xfer_cache_reg0 ); -\GENLOCK_FOR_MASTER.mstrfrm_tstsync_d1_reg\: unisim.vcomponents.FDRE +\sig_xfer_len_reg_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => valid_frame_sync_d2, - Q => p_44_out, - R => p_0_in + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => D(2), + Q => \in\(37), + R => sig_xfer_cache_reg0 + ); +sig_xfer_type_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_csm_ld_xfer, + D => sig_child_qual_burst_type, + Q => \in\(38), + R => sig_xfer_cache_reg0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_intrpt is +entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_mssai_skid_buf is port ( - mm2s_dly_irq_set : out STD_LOGIC; - p_10_out : out STD_LOGIC; - ch1_delay_cnt_en : out STD_LOGIC; - mm2s_ioc_irq_set : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 7 downto 0 ); - \ch1_ioc_irq_set_i__0\ : out STD_LOGIC; - \GEN_FREE_RUN_MODE.mask_fsync_out_i_reg\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); - \GEN_FREE_RUN_MODE.mask_fsync_out_i_reg_0\ : out STD_LOGIC; - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - \MASTER_MODE_FRAME_CNT.tstvect_fsync_reg\ : in STD_LOGIC; - D : in STD_LOGIC_VECTOR ( 0 to 0 ); - p_68_out : in STD_LOGIC_VECTOR ( 15 downto 0 ); - \p_6_out__1\ : in STD_LOGIC; - p_23_out : in STD_LOGIC; - p_46_out : in STD_LOGIC; - \ch1_delay_zero__6\ : in STD_LOGIC; - p_17_out : in STD_LOGIC; - p_49_out : in STD_LOGIC; - \out\ : in STD_LOGIC; - mask_fsync_out_i : in STD_LOGIC; - prmry_resetn_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : out STD_LOGIC; + \sig_data_skid_reg_reg[7]_0\ : out STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][0]\ : out STD_LOGIC; + sig_dre2ibtt_tstrb : out STD_LOGIC; + sig_strm_tlast : out STD_LOGIC; + RD_EN : out STD_LOGIC; + \sig_byte_cntr_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_dre2ibtt_eop_reg_reg : out STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_s2mm_aclk : in STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + DOUT : in STD_LOGIC_VECTOR ( 8 downto 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ); - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + EMPTY : in STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[4]\ : in STD_LOGIC; + sig_clr_dbc_reg : in STD_LOGIC; + sig_init_reg : in STD_LOGIC; + \GEN_INDET_BTT.lsig_absorb2tlast_reg\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0\ : in STD_LOGIC; + sig_eop_halt_xfer : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0\ : in STD_LOGIC; + p_0_in : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_intrpt : entity is "axi_vdma_intrpt"; -end Arty_Z7_20_axi_vdma_0_0_axi_vdma_intrpt; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_mssai_skid_buf : entity is "axi_datamover_mssai_skid_buf"; +end Arty_Z7_20_axi_vdma_0_0_axi_datamover_mssai_skid_buf; -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_intrpt is - signal \GEN_FREE_RUN_MODE.mask_fsync_out_i_i_2_n_0\ : STD_LOGIC; - signal \GEN_FREE_RUN_MODE.mask_fsync_out_i_i_3_n_0\ : STD_LOGIC; - signal \^gen_free_run_mode.mask_fsync_out_i_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[1]_i_2_n_0\ : STD_LOGIC; - signal \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_5_n_0\ : STD_LOGIC; - signal \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0\ : STD_LOGIC; - signal \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_3_n_0\ : STD_LOGIC; - signal \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_5_n_0\ : STD_LOGIC; - signal \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_6_n_0\ : STD_LOGIC; - signal \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_i_1_n_0\ : STD_LOGIC; - signal \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[3]_i_2_n_0\ : STD_LOGIC; - signal \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[4]_i_2_n_0\ : STD_LOGIC; - signal \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[5]_i_2_n_0\ : STD_LOGIC; - signal \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5_n_0\ : STD_LOGIC; - signal \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_7_n_0\ : STD_LOGIC; - signal L : STD_LOGIC_VECTOR ( 6 downto 0 ); - signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal ch1_dly_fast_cnt : STD_LOGIC_VECTOR ( 6 downto 0 ); - signal ch1_dly_fast_incr : STD_LOGIC; - signal \^ch1_ioc_irq_set_i__0\ : STD_LOGIC; - signal \^mm2s_ioc_irq_set\ : STD_LOGIC; - signal \^p_10_out\ : STD_LOGIC; - signal p_2_in : STD_LOGIC_VECTOR ( 7 downto 1 ); - signal \p_8_in__14\ : STD_LOGIC; - signal plusOp : STD_LOGIC_VECTOR ( 7 downto 0 ); - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[0]_i_1\ : label is "soft_lutpair43"; - attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[1]_i_1\ : label is "soft_lutpair43"; - attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[2]_i_1\ : label is "soft_lutpair44"; - attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[3]_i_1\ : label is "soft_lutpair38"; - attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[4]_i_1\ : label is "soft_lutpair38"; - attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_5\ : label is "soft_lutpair44"; - attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[1]_i_1\ : label is "soft_lutpair45"; - attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[2]_i_1\ : label is "soft_lutpair45"; - attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[3]_i_1\ : label is "soft_lutpair40"; - attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[4]_i_1\ : label is "soft_lutpair40"; - attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[6]_i_1\ : label is "soft_lutpair42"; - attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_2\ : label is "soft_lutpair42"; - attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[3]_i_2\ : label is "soft_lutpair41"; - attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[4]_i_2\ : label is "soft_lutpair41"; - attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[5]_i_2\ : label is "soft_lutpair39"; - attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_7\ : label is "soft_lutpair39"; +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_mssai_skid_buf is + signal sig_data_skid_mux_out : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal sig_data_skid_reg : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \^sig_dre2ibtt_tstrb\ : STD_LOGIC; + signal \sig_last_reg_out_i_1__1_n_0\ : STD_LOGIC; + signal sig_last_skid_reg : STD_LOGIC; + signal \sig_last_skid_reg_i_1__0_n_0\ : STD_LOGIC; + signal sig_m_valid_dup : STD_LOGIC; + attribute RTL_KEEP : string; + attribute RTL_KEEP of sig_m_valid_dup : signal is "true"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of sig_m_valid_dup : signal is "no"; + signal sig_m_valid_dup_i_1_n_0 : STD_LOGIC; + signal sig_m_valid_out : STD_LOGIC; + attribute RTL_KEEP of sig_m_valid_out : signal is "true"; + attribute equivalent_register_removal of sig_m_valid_out : signal is "no"; + signal sig_s_ready_dup : STD_LOGIC; + attribute RTL_KEEP of sig_s_ready_dup : signal is "true"; + attribute equivalent_register_removal of sig_s_ready_dup : signal is "no"; + signal sig_s_ready_dup2 : STD_LOGIC; + attribute RTL_KEEP of sig_s_ready_dup2 : signal is "true"; + attribute equivalent_register_removal of sig_s_ready_dup2 : signal is "no"; + signal sig_s_ready_dup3 : STD_LOGIC; + attribute RTL_KEEP of sig_s_ready_dup3 : signal is "true"; + attribute equivalent_register_removal of sig_s_ready_dup3 : signal is "no"; + signal sig_s_ready_dup4 : STD_LOGIC; + attribute RTL_KEEP of sig_s_ready_dup4 : signal is "true"; + attribute equivalent_register_removal of sig_s_ready_dup4 : signal is "no"; + signal \sig_s_ready_dup_i_1__0_n_0\ : STD_LOGIC; + signal sig_s_ready_out : STD_LOGIC; + attribute RTL_KEEP of sig_s_ready_out : signal is "true"; + attribute equivalent_register_removal of sig_s_ready_out : signal is "no"; + signal \sig_strb_reg_out[0]_i_1_n_0\ : STD_LOGIC; + signal sig_strb_skid_reg : STD_LOGIC; + signal \sig_strb_skid_reg[0]_i_1_n_0\ : STD_LOGIC; + signal \^sig_strm_tlast\ : STD_LOGIC; + attribute KEEP : string; + attribute KEEP of sig_m_valid_dup_reg : label is "yes"; + attribute equivalent_register_removal of sig_m_valid_dup_reg : label is "no"; + attribute KEEP of sig_m_valid_out_reg : label is "yes"; + attribute equivalent_register_removal of sig_m_valid_out_reg : label is "no"; + attribute KEEP of sig_s_ready_dup2_reg : label is "yes"; + attribute equivalent_register_removal of sig_s_ready_dup2_reg : label is "no"; + attribute KEEP of sig_s_ready_dup3_reg : label is "yes"; + attribute equivalent_register_removal of sig_s_ready_dup3_reg : label is "no"; + attribute KEEP of sig_s_ready_dup4_reg : label is "yes"; + attribute equivalent_register_removal of sig_s_ready_dup4_reg : label is "no"; + attribute KEEP of sig_s_ready_dup_reg : label is "yes"; + attribute equivalent_register_removal of sig_s_ready_dup_reg : label is "no"; + attribute KEEP of sig_s_ready_out_reg : label is "yes"; + attribute equivalent_register_removal of sig_s_ready_out_reg : label is "no"; begin - \GEN_FREE_RUN_MODE.mask_fsync_out_i_reg\(7 downto 0) <= \^gen_free_run_mode.mask_fsync_out_i_reg\(7 downto 0); - Q(7 downto 0) <= \^q\(7 downto 0); - \ch1_ioc_irq_set_i__0\ <= \^ch1_ioc_irq_set_i__0\; - mm2s_ioc_irq_set <= \^mm2s_ioc_irq_set\; - p_10_out <= \^p_10_out\; -\GEN_FREE_RUN_MODE.mask_fsync_out_i_i_1\: unisim.vcomponents.LUT6 + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][0]\ <= sig_m_valid_out; + \out\ <= sig_m_valid_dup; + \sig_data_skid_reg_reg[7]_0\ <= sig_s_ready_out; + sig_dre2ibtt_tstrb <= \^sig_dre2ibtt_tstrb\; + sig_strm_tlast <= \^sig_strm_tlast\; +\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg[0][0]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"00000100FF000100" + INIT => X"00080000" ) port map ( - I0 => \^gen_free_run_mode.mask_fsync_out_i_reg\(7), - I1 => \^gen_free_run_mode.mask_fsync_out_i_reg\(6), - I2 => \GEN_FREE_RUN_MODE.mask_fsync_out_i_i_2_n_0\, - I3 => \out\, - I4 => mask_fsync_out_i, - I5 => \^mm2s_ioc_irq_set\, - O => \GEN_FREE_RUN_MODE.mask_fsync_out_i_reg_0\ + I0 => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0\, + I1 => sig_m_valid_out, + I2 => sig_eop_halt_xfer, + I3 => Q(0), + I4 => \^sig_strm_tlast\, + O => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][0]_0\(0) ); -\GEN_FREE_RUN_MODE.mask_fsync_out_i_i_2\: unisim.vcomponents.LUT5 +\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg[1][0]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"FFFFFFFE" + INIT => X"00080000" ) port map ( - I0 => \^gen_free_run_mode.mask_fsync_out_i_reg\(3), - I1 => \^gen_free_run_mode.mask_fsync_out_i_reg\(2), - I2 => \^gen_free_run_mode.mask_fsync_out_i_reg\(5), - I3 => \^gen_free_run_mode.mask_fsync_out_i_reg\(4), - I4 => \GEN_FREE_RUN_MODE.mask_fsync_out_i_i_3_n_0\, - O => \GEN_FREE_RUN_MODE.mask_fsync_out_i_i_2_n_0\ + I0 => p_0_in, + I1 => sig_m_valid_out, + I2 => sig_eop_halt_xfer, + I3 => Q(0), + I4 => \^sig_strm_tlast\, + O => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][0]\(0) ); -\GEN_FREE_RUN_MODE.mask_fsync_out_i_i_3\: unisim.vcomponents.LUT5 +\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg[2][0]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"DFFFFFFF" + INIT => X"00080000" ) port map ( - I0 => \^gen_free_run_mode.mask_fsync_out_i_reg\(0), - I1 => \^gen_free_run_mode.mask_fsync_out_i_reg\(1), - I2 => p_68_out(0), - I3 => p_23_out, - I4 => p_46_out, - O => \GEN_FREE_RUN_MODE.mask_fsync_out_i_i_3_n_0\ + I0 => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0\, + I1 => sig_m_valid_out, + I2 => sig_eop_halt_xfer, + I3 => Q(0), + I4 => \^sig_strm_tlast\, + O => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][0]\(0) ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[0]_i_1\: unisim.vcomponents.LUT3 +\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg[3][0]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"32" + INIT => X"00080000" ) port map ( - I0 => L(1), - I1 => L(0), - I2 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[1]_i_2_n_0\, - O => ch1_dly_fast_cnt(0) - ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[1]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"98" - ) - port map ( - I0 => L(0), - I1 => L(1), - I2 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[1]_i_2_n_0\, - O => ch1_dly_fast_cnt(1) - ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[1]_i_2\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFFFFFFE" - ) - port map ( - I0 => L(5), - I1 => L(3), - I2 => L(2), - I3 => L(4), - I4 => L(6), - O => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[1]_i_2_n_0\ + I0 => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0\, + I1 => sig_m_valid_out, + I2 => sig_eop_halt_xfer, + I3 => Q(0), + I4 => \^sig_strm_tlast\, + O => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][0]\(0) ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[2]_i_1\: unisim.vcomponents.LUT3 +\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg[4][0]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"A9" + INIT => X"00080000" ) port map ( - I0 => L(2), - I1 => L(0), - I2 => L(1), - O => ch1_dly_fast_cnt(2) + I0 => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0\, + I1 => sig_m_valid_out, + I2 => sig_eop_halt_xfer, + I3 => Q(0), + I4 => \^sig_strm_tlast\, + O => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][0]\(0) ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[3]_i_1\: unisim.vcomponents.LUT4 +\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg[5][0]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"FE01" + INIT => X"00080000" ) port map ( - I0 => L(0), - I1 => L(1), - I2 => L(2), - I3 => L(3), - O => ch1_dly_fast_cnt(3) + I0 => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0\, + I1 => sig_m_valid_out, + I2 => sig_eop_halt_xfer, + I3 => Q(0), + I4 => \^sig_strm_tlast\, + O => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][0]\(0) ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[4]_i_1\: unisim.vcomponents.LUT5 +\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg[6][0]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"FFFE0001" + INIT => X"00080000" ) port map ( - I0 => L(0), - I1 => L(1), - I2 => L(3), - I3 => L(2), - I4 => L(4), - O => ch1_dly_fast_cnt(4) + I0 => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0\, + I1 => sig_m_valid_out, + I2 => sig_eop_halt_xfer, + I3 => Q(0), + I4 => \^sig_strm_tlast\, + O => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][0]\(0) ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[5]_i_1\: unisim.vcomponents.LUT6 +\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg[7][0]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"FFFFFFFE00000001" + INIT => X"00080000" ) port map ( - I0 => L(0), - I1 => L(1), - I2 => L(4), - I3 => L(2), - I4 => L(3), - I5 => L(5), - O => ch1_dly_fast_cnt(5) + I0 => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0\, + I1 => sig_m_valid_out, + I2 => sig_eop_halt_xfer, + I3 => Q(0), + I4 => \^sig_strm_tlast\, + O => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][0]\(0) ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_2\: unisim.vcomponents.LUT6 +\gf18e1_inst.sngfifo18e1_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"FFFFFFFE00000001" + INIT => X"2" ) port map ( - I0 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_5_n_0\, - I1 => L(5), - I2 => L(3), - I3 => L(2), - I4 => L(4), - I5 => L(6), - O => ch1_dly_fast_cnt(6) + I0 => sig_s_ready_out, + I1 => EMPTY, + O => RD_EN ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_5\: unisim.vcomponents.LUT2 +\sig_byte_cntr[3]_i_2\: unisim.vcomponents.LUT3 generic map( - INIT => X"E" + INIT => X"2A" ) port map ( - I0 => L(0), - I1 => L(1), - O => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_5_n_0\ + I0 => \^sig_dre2ibtt_tstrb\, + I1 => \INFERRED_GEN.cnt_i_reg[4]\, + I2 => sig_clr_dbc_reg, + O => \sig_byte_cntr_reg[3]\(0) ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[0]\: unisim.vcomponents.FDRE +\sig_data_reg_out[0]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => ch1_dly_fast_cnt(0), - Q => L(0), - R => SR(0) + I0 => sig_data_skid_reg(0), + I1 => DOUT(0), + I2 => sig_s_ready_dup2, + O => sig_data_skid_mux_out(0) ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[1]\: unisim.vcomponents.FDRE +\sig_data_reg_out[1]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => ch1_dly_fast_cnt(1), - Q => L(1), - R => SR(0) + I0 => sig_data_skid_reg(1), + I1 => DOUT(1), + I2 => sig_s_ready_dup2, + O => sig_data_skid_mux_out(1) ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[2]\: unisim.vcomponents.FDSE +\sig_data_reg_out[2]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => ch1_dly_fast_cnt(2), - Q => L(2), - S => SR(0) + I0 => sig_data_skid_reg(2), + I1 => DOUT(2), + I2 => sig_s_ready_dup2, + O => sig_data_skid_mux_out(2) ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[3]\: unisim.vcomponents.FDSE +\sig_data_reg_out[3]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => ch1_dly_fast_cnt(3), - Q => L(3), - S => SR(0) + I0 => sig_data_skid_reg(3), + I1 => DOUT(3), + I2 => sig_s_ready_dup2, + O => sig_data_skid_mux_out(3) ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[4]\: unisim.vcomponents.FDSE +\sig_data_reg_out[4]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => ch1_dly_fast_cnt(4), - Q => L(4), - S => SR(0) + I0 => sig_data_skid_reg(4), + I1 => DOUT(4), + I2 => sig_s_ready_dup2, + O => sig_data_skid_mux_out(4) ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[5]\: unisim.vcomponents.FDSE +\sig_data_reg_out[5]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => ch1_dly_fast_cnt(5), - Q => L(5), - S => SR(0) + I0 => sig_data_skid_reg(5), + I1 => DOUT(5), + I2 => sig_s_ready_dup2, + O => sig_data_skid_mux_out(5) ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]\: unisim.vcomponents.FDSE +\sig_data_reg_out[6]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => ch1_dly_fast_cnt(6), - Q => L(6), - S => SR(0) + I0 => sig_data_skid_reg(6), + I1 => DOUT(6), + I2 => sig_s_ready_dup2, + O => sig_data_skid_mux_out(6) ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_i_1\: unisim.vcomponents.LUT6 +\sig_data_reg_out[7]_i_2\: unisim.vcomponents.LUT3 generic map( - INIT => X"0000000000000001" + INIT => X"CA" ) port map ( - I0 => L(6), - I1 => L(4), - I2 => L(2), - I3 => L(3), - I4 => L(5), - I5 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_5_n_0\, - O => ch1_dly_fast_incr + I0 => sig_data_skid_reg(7), + I1 => DOUT(7), + I2 => sig_s_ready_dup2, + O => sig_data_skid_mux_out(7) ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => ch1_dly_fast_incr, - Q => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0\, - R => SR(0) + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(0), + Q => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7]\(0), + R => '0' ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \MASTER_MODE_FRAME_CNT.tstvect_fsync_reg\, - Q => ch1_delay_cnt_en, + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(1), + Q => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7]\(1), R => '0' ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[0]_i_1\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \^q\(0), - O => plusOp(0) - ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[1]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"6" - ) - port map ( - I0 => \^q\(0), - I1 => \^q\(1), - O => plusOp(1) - ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[2]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"78" - ) - port map ( - I0 => \^q\(0), - I1 => \^q\(1), - I2 => \^q\(2), - O => plusOp(2) - ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[3]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"7F80" - ) - port map ( - I0 => \^q\(1), - I1 => \^q\(0), - I2 => \^q\(2), - I3 => \^q\(3), - O => plusOp(3) - ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[4]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"7FFF8000" - ) - port map ( - I0 => \^q\(2), - I1 => \^q\(0), - I2 => \^q\(1), - I3 => \^q\(3), - I4 => \^q\(4), - O => plusOp(4) - ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[5]_i_1\: unisim.vcomponents.LUT6 +\sig_data_reg_out_reg[2]\: unisim.vcomponents.FDRE generic map( - INIT => X"7FFFFFFF80000000" + INIT => '0' ) port map ( - I0 => \^q\(3), - I1 => \^q\(1), - I2 => \^q\(0), - I3 => \^q\(2), - I4 => \^q\(4), - I5 => \^q\(5), - O => plusOp(5) + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(2), + Q => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7]\(2), + R => '0' ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[6]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out_reg[3]\: unisim.vcomponents.FDRE generic map( - INIT => X"6" + INIT => '0' ) port map ( - I0 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_3_n_0\, - I1 => \^q\(6), - O => plusOp(6) + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(3), + Q => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7]\(3), + R => '0' ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_2\: unisim.vcomponents.LUT3 +\sig_data_reg_out_reg[4]\: unisim.vcomponents.FDRE generic map( - INIT => X"78" + INIT => '0' ) port map ( - I0 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_3_n_0\, - I1 => \^q\(6), - I2 => \^q\(7), - O => plusOp(7) + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(4), + Q => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7]\(4), + R => '0' ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_3\: unisim.vcomponents.LUT6 +\sig_data_reg_out_reg[5]\: unisim.vcomponents.FDRE generic map( - INIT => X"8000000000000000" + INIT => '0' ) port map ( - I0 => \^q\(5), - I1 => \^q\(3), - I2 => \^q\(1), - I3 => \^q\(0), - I4 => \^q\(2), - I5 => \^q\(4), - O => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_3_n_0\ + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(5), + Q => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7]\(5), + R => '0' ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0]\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0\, - D => plusOp(0), - Q => \^q\(0), - R => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\(0) + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(6), + Q => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7]\(6), + R => '0' ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[1]\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0\, - D => plusOp(1), - Q => \^q\(1), - R => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\(0) + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(7), + Q => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7]\(7), + R => '0' ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[2]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0\, - D => plusOp(2), - Q => \^q\(2), - R => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\(0) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => DOUT(0), + Q => sig_data_skid_reg(0), + R => '0' ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[3]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0\, - D => plusOp(3), - Q => \^q\(3), - R => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\(0) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => DOUT(1), + Q => sig_data_skid_reg(1), + R => '0' ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[4]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0\, - D => plusOp(4), - Q => \^q\(4), - R => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\(0) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => DOUT(2), + Q => sig_data_skid_reg(2), + R => '0' ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[5]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0\, - D => plusOp(5), - Q => \^q\(5), - R => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\(0) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => DOUT(3), + Q => sig_data_skid_reg(3), + R => '0' ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[6]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0\, - D => plusOp(6), - Q => \^q\(6), - R => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\(0) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => DOUT(4), + Q => sig_data_skid_reg(4), + R => '0' ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0\, - D => plusOp(7), - Q => \^q\(7), - R => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\(0) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => DOUT(5), + Q => sig_data_skid_reg(5), + R => '0' ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_1\: unisim.vcomponents.LUT4 +\sig_data_skid_reg_reg[6]\: unisim.vcomponents.FDRE generic map( - INIT => X"1000" + INIT => '0' ) port map ( - I0 => \ch1_delay_zero__6\, - I1 => p_17_out, - I2 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0\, - I3 => \p_8_in__14\, - O => \^p_10_out\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => DOUT(6), + Q => sig_data_skid_reg(6), + R => '0' ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_3\: unisim.vcomponents.LUT6 +\sig_data_skid_reg_reg[7]\: unisim.vcomponents.FDRE generic map( - INIT => X"9009000000000000" + INIT => '0' ) port map ( - I0 => p_68_out(15), - I1 => \^q\(7), - I2 => p_68_out(14), - I3 => \^q\(6), - I4 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_5_n_0\, - I5 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_6_n_0\, - O => \p_8_in__14\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => DOUT(7), + Q => sig_data_skid_reg(7), + R => '0' ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_5\: unisim.vcomponents.LUT6 +sig_dre2ibtt_eop_reg_i_1: unisim.vcomponents.LUT4 generic map( - INIT => X"9009000000009009" + INIT => X"0200" ) port map ( - I0 => \^q\(3), - I1 => p_68_out(11), - I2 => p_68_out(13), - I3 => \^q\(5), - I4 => p_68_out(12), - I5 => \^q\(4), - O => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_5_n_0\ + I0 => \^sig_strm_tlast\, + I1 => Q(0), + I2 => sig_eop_halt_xfer, + I3 => sig_m_valid_out, + O => sig_dre2ibtt_eop_reg_reg ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_6\: unisim.vcomponents.LUT6 +\sig_last_reg_out_i_1__1\: unisim.vcomponents.LUT5 generic map( - INIT => X"9009000000009009" + INIT => X"B8FFB800" ) port map ( - I0 => \^q\(0), - I1 => p_68_out(8), - I2 => p_68_out(10), - I3 => \^q\(2), - I4 => p_68_out(9), - I5 => \^q\(1), - O => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_6_n_0\ + I0 => DOUT(8), + I1 => sig_s_ready_dup4, + I2 => sig_last_skid_reg, + I3 => E(0), + I4 => \^sig_strm_tlast\, + O => \sig_last_reg_out_i_1__1_n_0\ ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_reg\: unisim.vcomponents.FDRE +sig_last_reg_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, + C => m_axi_s2mm_aclk, CE => '1', - D => \^p_10_out\, - Q => mm2s_dly_irq_set, - R => SR(0) + D => \sig_last_reg_out_i_1__1_n_0\, + Q => \^sig_strm_tlast\, + R => sig_stream_rst ); -\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_i_1\: unisim.vcomponents.LUT4 +\sig_last_skid_reg_i_1__0\: unisim.vcomponents.LUT4 generic map( - INIT => X"0080" + INIT => X"E200" ) port map ( - I0 => \^ch1_ioc_irq_set_i__0\, - I1 => p_49_out, - I2 => \out\, - I3 => \p_6_out__1\, - O => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_i_1_n_0\ + I0 => sig_last_skid_reg, + I1 => sig_s_ready_dup, + I2 => DOUT(8), + I3 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + O => \sig_last_skid_reg_i_1__0_n_0\ ); -\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_reg\: unisim.vcomponents.FDRE +sig_last_skid_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, + C => m_axi_s2mm_aclk, CE => '1', - D => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_i_1_n_0\, - Q => \^mm2s_ioc_irq_set\, + D => \sig_last_skid_reg_i_1__0_n_0\, + Q => sig_last_skid_reg, R => '0' ); -\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[1]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"AAAAB88B" - ) - port map ( - I0 => p_68_out(1), - I1 => \^ch1_ioc_irq_set_i__0\, - I2 => \^gen_free_run_mode.mask_fsync_out_i_reg\(0), - I3 => \^gen_free_run_mode.mask_fsync_out_i_reg\(1), - I4 => \p_6_out__1\, - O => p_2_in(1) - ); -\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[2]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AAAAAAAABBB8888B" - ) - port map ( - I0 => p_68_out(2), - I1 => \^ch1_ioc_irq_set_i__0\, - I2 => \^gen_free_run_mode.mask_fsync_out_i_reg\(1), - I3 => \^gen_free_run_mode.mask_fsync_out_i_reg\(0), - I4 => \^gen_free_run_mode.mask_fsync_out_i_reg\(2), - I5 => \p_6_out__1\, - O => p_2_in(2) - ); -\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[3]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"AAAAB88B" - ) - port map ( - I0 => p_68_out(3), - I1 => \^ch1_ioc_irq_set_i__0\, - I2 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[3]_i_2_n_0\, - I3 => \^gen_free_run_mode.mask_fsync_out_i_reg\(3), - I4 => \p_6_out__1\, - O => p_2_in(3) - ); -\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[3]_i_2\: unisim.vcomponents.LUT3 - generic map( - INIT => X"FE" - ) - port map ( - I0 => \^gen_free_run_mode.mask_fsync_out_i_reg\(1), - I1 => \^gen_free_run_mode.mask_fsync_out_i_reg\(0), - I2 => \^gen_free_run_mode.mask_fsync_out_i_reg\(2), - O => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[3]_i_2_n_0\ - ); -\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[4]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"AAAAB88B" - ) - port map ( - I0 => p_68_out(4), - I1 => \^ch1_ioc_irq_set_i__0\, - I2 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[4]_i_2_n_0\, - I3 => \^gen_free_run_mode.mask_fsync_out_i_reg\(4), - I4 => \p_6_out__1\, - O => p_2_in(4) - ); -\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[4]_i_2\: unisim.vcomponents.LUT4 - generic map( - INIT => X"FFFE" - ) - port map ( - I0 => \^gen_free_run_mode.mask_fsync_out_i_reg\(2), - I1 => \^gen_free_run_mode.mask_fsync_out_i_reg\(0), - I2 => \^gen_free_run_mode.mask_fsync_out_i_reg\(1), - I3 => \^gen_free_run_mode.mask_fsync_out_i_reg\(3), - O => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[4]_i_2_n_0\ - ); -\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[5]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"AAAAB88B" - ) - port map ( - I0 => p_68_out(5), - I1 => \^ch1_ioc_irq_set_i__0\, - I2 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[5]_i_2_n_0\, - I3 => \^gen_free_run_mode.mask_fsync_out_i_reg\(5), - I4 => \p_6_out__1\, - O => p_2_in(5) - ); -\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[5]_i_2\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFFFFFFE" - ) - port map ( - I0 => \^gen_free_run_mode.mask_fsync_out_i_reg\(3), - I1 => \^gen_free_run_mode.mask_fsync_out_i_reg\(1), - I2 => \^gen_free_run_mode.mask_fsync_out_i_reg\(0), - I3 => \^gen_free_run_mode.mask_fsync_out_i_reg\(2), - I4 => \^gen_free_run_mode.mask_fsync_out_i_reg\(4), - O => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[5]_i_2_n_0\ - ); -\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[6]_i_1\: unisim.vcomponents.LUT5 +sig_m_valid_dup_i_1: unisim.vcomponents.LUT6 generic map( - INIT => X"AAAAB88B" + INIT => X"0404440444044404" ) port map ( - I0 => p_68_out(6), - I1 => \^ch1_ioc_irq_set_i__0\, - I2 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5_n_0\, - I3 => \^gen_free_run_mode.mask_fsync_out_i_reg\(6), - I4 => \p_6_out__1\, - O => p_2_in(6) + I0 => sig_init_reg, + I1 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I2 => EMPTY, + I3 => sig_m_valid_dup, + I4 => \GEN_INDET_BTT.lsig_absorb2tlast_reg\, + I5 => sig_s_ready_dup, + O => sig_m_valid_dup_i_1_n_0 ); -\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_3\: unisim.vcomponents.LUT6 +sig_m_valid_dup_reg: unisim.vcomponents.FDRE generic map( - INIT => X"AAAAAAAABBB8888B" + INIT => '0' ) port map ( - I0 => p_68_out(7), - I1 => \^ch1_ioc_irq_set_i__0\, - I2 => \^gen_free_run_mode.mask_fsync_out_i_reg\(6), - I3 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5_n_0\, - I4 => \^gen_free_run_mode.mask_fsync_out_i_reg\(7), - I5 => \p_6_out__1\, - O => p_2_in(7) + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_m_valid_dup_i_1_n_0, + Q => sig_m_valid_dup, + R => '0' ); -\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_4\: unisim.vcomponents.LUT5 +sig_m_valid_out_reg: unisim.vcomponents.FDRE generic map( - INIT => X"00000001" + INIT => '0' ) port map ( - I0 => \^gen_free_run_mode.mask_fsync_out_i_reg\(5), - I1 => \^gen_free_run_mode.mask_fsync_out_i_reg\(4), - I2 => \^gen_free_run_mode.mask_fsync_out_i_reg\(6), - I3 => \^gen_free_run_mode.mask_fsync_out_i_reg\(7), - I4 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_7_n_0\, - O => \^ch1_ioc_irq_set_i__0\ + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_m_valid_dup_i_1_n_0, + Q => sig_m_valid_out, + R => '0' ); -\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5\: unisim.vcomponents.LUT6 +sig_s_ready_dup2_reg: unisim.vcomponents.FDRE generic map( - INIT => X"FFFFFFFFFFFFFFFE" + INIT => '0' ) port map ( - I0 => \^gen_free_run_mode.mask_fsync_out_i_reg\(4), - I1 => \^gen_free_run_mode.mask_fsync_out_i_reg\(2), - I2 => \^gen_free_run_mode.mask_fsync_out_i_reg\(0), - I3 => \^gen_free_run_mode.mask_fsync_out_i_reg\(1), - I4 => \^gen_free_run_mode.mask_fsync_out_i_reg\(3), - I5 => \^gen_free_run_mode.mask_fsync_out_i_reg\(5), - O => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5_n_0\ + C => m_axi_s2mm_aclk, + CE => '1', + D => \sig_s_ready_dup_i_1__0_n_0\, + Q => sig_s_ready_dup2, + R => sig_stream_rst ); -\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_7\: unisim.vcomponents.LUT4 +sig_s_ready_dup3_reg: unisim.vcomponents.FDRE generic map( - INIT => X"FFEF" + INIT => '0' ) port map ( - I0 => \^gen_free_run_mode.mask_fsync_out_i_reg\(2), - I1 => \^gen_free_run_mode.mask_fsync_out_i_reg\(3), - I2 => \^gen_free_run_mode.mask_fsync_out_i_reg\(0), - I3 => \^gen_free_run_mode.mask_fsync_out_i_reg\(1), - O => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_7_n_0\ + C => m_axi_s2mm_aclk, + CE => '1', + D => \sig_s_ready_dup_i_1__0_n_0\, + Q => sig_s_ready_dup3, + R => sig_stream_rst ); -\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0]\: unisim.vcomponents.FDSE +sig_s_ready_dup4_reg: unisim.vcomponents.FDRE generic map( - INIT => '1' + INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => D(0), - Q => \^gen_free_run_mode.mask_fsync_out_i_reg\(0), - S => prmry_resetn_i_reg(0) + C => m_axi_s2mm_aclk, + CE => '1', + D => \sig_s_ready_dup_i_1__0_n_0\, + Q => sig_s_ready_dup4, + R => sig_stream_rst ); -\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[1]\: unisim.vcomponents.FDRE +\sig_s_ready_dup_i_1__0\: unisim.vcomponents.LUT5 generic map( - INIT => '0' + INIT => X"FFFFEEAE" ) port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => p_2_in(1), - Q => \^gen_free_run_mode.mask_fsync_out_i_reg\(1), - R => prmry_resetn_i_reg(0) + I0 => sig_init_reg, + I1 => sig_s_ready_dup, + I2 => sig_m_valid_dup, + I3 => EMPTY, + I4 => \GEN_INDET_BTT.lsig_absorb2tlast_reg\, + O => \sig_s_ready_dup_i_1__0_n_0\ ); -\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[2]\: unisim.vcomponents.FDRE +sig_s_ready_dup_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => p_2_in(2), - Q => \^gen_free_run_mode.mask_fsync_out_i_reg\(2), - R => prmry_resetn_i_reg(0) + C => m_axi_s2mm_aclk, + CE => '1', + D => \sig_s_ready_dup_i_1__0_n_0\, + Q => sig_s_ready_dup, + R => sig_stream_rst ); -\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[3]\: unisim.vcomponents.FDRE +sig_s_ready_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => p_2_in(3), - Q => \^gen_free_run_mode.mask_fsync_out_i_reg\(3), - R => prmry_resetn_i_reg(0) + C => m_axi_s2mm_aclk, + CE => '1', + D => \sig_s_ready_dup_i_1__0_n_0\, + Q => sig_s_ready_out, + R => sig_stream_rst ); -\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[4]\: unisim.vcomponents.FDRE +\sig_strb_reg_out[0]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"EFE0" ) port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => p_2_in(4), - Q => \^gen_free_run_mode.mask_fsync_out_i_reg\(4), - R => prmry_resetn_i_reg(0) + I0 => sig_s_ready_dup3, + I1 => sig_strb_skid_reg, + I2 => E(0), + I3 => \^sig_dre2ibtt_tstrb\, + O => \sig_strb_reg_out[0]_i_1_n_0\ ); -\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[5]\: unisim.vcomponents.FDRE +\sig_strb_reg_out_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => p_2_in(5), - Q => \^gen_free_run_mode.mask_fsync_out_i_reg\(5), - R => prmry_resetn_i_reg(0) + C => m_axi_s2mm_aclk, + CE => '1', + D => \sig_strb_reg_out[0]_i_1_n_0\, + Q => \^sig_dre2ibtt_tstrb\, + R => sig_stream_rst ); -\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[6]\: unisim.vcomponents.FDRE +\sig_strb_skid_reg[0]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"E0" ) port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => p_2_in(6), - Q => \^gen_free_run_mode.mask_fsync_out_i_reg\(6), - R => prmry_resetn_i_reg(0) + I0 => sig_strb_skid_reg, + I1 => sig_s_ready_dup, + I2 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + O => \sig_strb_skid_reg[0]_i_1_n_0\ ); -\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\: unisim.vcomponents.FDRE +\sig_strb_skid_reg_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => p_2_in(7), - Q => \^gen_free_run_mode.mask_fsync_out_i_reg\(7), - R => prmry_resetn_i_reg(0) + C => m_axi_s2mm_aclk, + CE => '1', + D => \sig_strb_skid_reg[0]_i_1_n_0\, + Q => sig_strb_skid_reg, + R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_mux is +entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_pcc is port ( - \out\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); - in0 : in STD_LOGIC_VECTOR ( 31 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_mux : entity is "axi_vdma_reg_mux"; -end Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_mux; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_mux is - signal ip2axi_rddata_int : STD_LOGIC_VECTOR ( 31 downto 0 ); - attribute DONT_TOUCH : boolean; - attribute DONT_TOUCH of ip2axi_rddata_int : signal is std.standard.true; -begin - ip2axi_rddata_int(31 downto 0) <= in0(31 downto 0); - \out\(31 downto 0) <= ip2axi_rddata_int(31 downto 0); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_regdirect is - port ( - p_64_out : out STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0]\ : out STD_LOGIC; - \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); - \stride_vid_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); - \hsize_vid_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); - \vsize_vid_reg[12]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[1]\ : out STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[2]\ : out STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3]\ : out STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4]\ : out STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5]\ : out STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6]\ : out STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7]\ : out STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8]\ : out STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9]\ : out STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10]\ : out STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]\ : out STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]\ : out STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[13]\ : out STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[14]\ : out STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]\ : out STD_LOGIC; - \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg\ : out STD_LOGIC; + sig_init_reg : out STD_LOGIC; + \in\ : out STD_LOGIC_VECTOR ( 38 downto 0 ); + sig_sm_halt_reg : out STD_LOGIC; + sig_input_reg_empty : out STD_LOGIC; + sig_calc_error_pushed : out STD_LOGIC; + sig_mstr2data_sequential : out STD_LOGIC; + FIFO_Full_reg : out STD_LOGIC; + sig_mstr2sf_cmd_valid : out STD_LOGIC; + sig_mstr2data_cmd_valid : out STD_LOGIC; + sig_mstr2addr_cmd_valid : out STD_LOGIC; + sig_next_cmd_cmplt_reg_reg : out STD_LOGIC_VECTOR ( 1 downto 0 ); SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - \dmacr_i_reg[0]\ : in STD_LOGIC; m_axi_mm2s_aclk : in STD_LOGIC; - prmry_resetn_i_reg : in STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); - prmry_resetn_i_reg_0 : in STD_LOGIC; - p_35_out : in STD_LOGIC; - p_23_out : in STD_LOGIC; - prmtr_update_complete : in STD_LOGIC; - halted_reg : in STD_LOGIC; - mm2s_axi2ip_wrce : in STD_LOGIC_VECTOR ( 3 downto 0 ); - D : in STD_LOGIC_VECTOR ( 31 downto 0 ) + \out\ : in STD_LOGIC_VECTOR ( 49 downto 0 ); + sig_calc_error_reg_reg_0 : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_wr_fifo : in STD_LOGIC; + sig_wr_fifo_0 : in STD_LOGIC; + sig_wr_fifo_1 : in STD_LOGIC; + FIFO_Full_reg_0 : in STD_LOGIC; + sig_inhibit_rdy_n : in STD_LOGIC ); attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_regdirect : entity is "axi_vdma_regdirect"; -end Arty_Z7_20_axi_vdma_0_0_axi_vdma_regdirect; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_pcc : entity is "axi_datamover_pcc"; +end Arty_Z7_20_axi_vdma_0_0_axi_datamover_pcc; -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_regdirect is - signal \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\ : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal \^hsize_vid_reg[15]\ : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal p_63_out : STD_LOGIC; - signal \^p_64_out\ : STD_LOGIC; - signal regdir_idle_i_i_1_n_0 : STD_LOGIC; - signal run_stop_d1 : STD_LOGIC; - signal \^stride_vid_reg[15]\ : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal \^vsize_vid_reg[12]\ : STD_LOGIC_VECTOR ( 12 downto 0 ); +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_pcc is + signal \FSM_sequential_sig_pcc_sm_state[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_sig_pcc_sm_state[1]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_sig_pcc_sm_state[1]_i_2_n_0\ : STD_LOGIC; + signal \FSM_sequential_sig_pcc_sm_state[2]_i_1_n_0\ : STD_LOGIC; + signal \^in\ : STD_LOGIC_VECTOR ( 38 downto 0 ); + signal p_1_in : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal p_1_in_0 : STD_LOGIC; + signal sel0 : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal sig_addr_aligned_im0 : STD_LOGIC; + signal sig_addr_aligned_ireg1 : STD_LOGIC; + signal \sig_addr_cntr_im0_msh[0]_i_1_n_0\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh[0]_i_3_n_0\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh[0]_i_4_n_0\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh[0]_i_5_n_0\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh[0]_i_6_n_0\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh[0]_i_7_n_0\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh[12]_i_2_n_0\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh[12]_i_3_n_0\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh[12]_i_4_n_0\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh[12]_i_5_n_0\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh[4]_i_2_n_0\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh[4]_i_3_n_0\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh[4]_i_4_n_0\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh[4]_i_5_n_0\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh[8]_i_2_n_0\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh[8]_i_3_n_0\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh[8]_i_4_n_0\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh[8]_i_5_n_0\ : STD_LOGIC; + signal sig_addr_cntr_im0_msh_reg : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \sig_addr_cntr_im0_msh_reg[0]_i_2_n_0\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh_reg[0]_i_2_n_1\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh_reg[0]_i_2_n_2\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh_reg[0]_i_2_n_3\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh_reg[0]_i_2_n_4\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh_reg[0]_i_2_n_5\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh_reg[0]_i_2_n_6\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh_reg[0]_i_2_n_7\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh_reg[12]_i_1_n_1\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh_reg[12]_i_1_n_2\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh_reg[12]_i_1_n_3\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh_reg[12]_i_1_n_4\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh_reg[12]_i_1_n_5\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh_reg[12]_i_1_n_6\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh_reg[12]_i_1_n_7\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \sig_addr_cntr_im0_msh_reg[8]_i_1_n_7\ : STD_LOGIC; + signal sig_addr_cntr_incr_ireg2 : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal \sig_addr_cntr_incr_ireg2[0]_i_1_n_0\ : STD_LOGIC; + signal \sig_addr_cntr_incr_ireg2[1]_i_1_n_0\ : STD_LOGIC; + signal \sig_addr_cntr_incr_ireg2[2]_i_1_n_0\ : STD_LOGIC; + signal \sig_addr_cntr_incr_ireg2[3]_i_1_n_0\ : STD_LOGIC; + signal \sig_addr_cntr_incr_ireg2[4]_i_1_n_0\ : STD_LOGIC; + signal \sig_addr_cntr_incr_ireg2[5]_i_1_n_0\ : STD_LOGIC; + signal \sig_addr_cntr_incr_ireg2[6]_i_1_n_0\ : STD_LOGIC; + signal \sig_addr_cntr_incr_ireg2[7]_i_1_n_0\ : STD_LOGIC; + signal \sig_addr_cntr_incr_ireg2[8]_i_1_n_0\ : STD_LOGIC; + signal \sig_addr_cntr_lsh_im0[15]_i_1_n_0\ : STD_LOGIC; + signal \sig_addr_cntr_lsh_im0_reg_n_0_[0]\ : STD_LOGIC; + signal \sig_addr_cntr_lsh_im0_reg_n_0_[10]\ : STD_LOGIC; + signal \sig_addr_cntr_lsh_im0_reg_n_0_[11]\ : STD_LOGIC; + signal \sig_addr_cntr_lsh_im0_reg_n_0_[12]\ : STD_LOGIC; + signal \sig_addr_cntr_lsh_im0_reg_n_0_[13]\ : STD_LOGIC; + signal \sig_addr_cntr_lsh_im0_reg_n_0_[14]\ : STD_LOGIC; + signal \sig_addr_cntr_lsh_im0_reg_n_0_[1]\ : STD_LOGIC; + signal \sig_addr_cntr_lsh_im0_reg_n_0_[2]\ : STD_LOGIC; + signal \sig_addr_cntr_lsh_im0_reg_n_0_[3]\ : STD_LOGIC; + signal \sig_addr_cntr_lsh_im0_reg_n_0_[4]\ : STD_LOGIC; + signal \sig_addr_cntr_lsh_im0_reg_n_0_[5]\ : STD_LOGIC; + signal \sig_addr_cntr_lsh_im0_reg_n_0_[6]\ : STD_LOGIC; + signal \sig_addr_cntr_lsh_im0_reg_n_0_[7]\ : STD_LOGIC; + signal \sig_addr_cntr_lsh_im0_reg_n_0_[8]\ : STD_LOGIC; + signal \sig_addr_cntr_lsh_im0_reg_n_0_[9]\ : STD_LOGIC; + signal sig_addr_cntr_lsh_kh : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal sig_adjusted_addr_incr_im1 : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \sig_adjusted_addr_incr_ireg2[3]_i_2_n_0\ : STD_LOGIC; + signal \sig_adjusted_addr_incr_ireg2[3]_i_3_n_0\ : STD_LOGIC; + signal \sig_adjusted_addr_incr_ireg2[3]_i_4_n_0\ : STD_LOGIC; + signal \sig_adjusted_addr_incr_ireg2[3]_i_5_n_0\ : STD_LOGIC; + signal \sig_adjusted_addr_incr_ireg2[7]_i_2_n_0\ : STD_LOGIC; + signal \sig_adjusted_addr_incr_ireg2[7]_i_3_n_0\ : STD_LOGIC; + signal \sig_adjusted_addr_incr_ireg2[7]_i_4_n_0\ : STD_LOGIC; + signal \sig_adjusted_addr_incr_ireg2[7]_i_5_n_0\ : STD_LOGIC; + signal \sig_adjusted_addr_incr_ireg2_reg[3]_i_1_n_0\ : STD_LOGIC; + signal \sig_adjusted_addr_incr_ireg2_reg[3]_i_1_n_1\ : STD_LOGIC; + signal \sig_adjusted_addr_incr_ireg2_reg[3]_i_1_n_2\ : STD_LOGIC; + signal \sig_adjusted_addr_incr_ireg2_reg[3]_i_1_n_3\ : STD_LOGIC; + signal \sig_adjusted_addr_incr_ireg2_reg[7]_i_1_n_1\ : STD_LOGIC; + signal \sig_adjusted_addr_incr_ireg2_reg[7]_i_1_n_2\ : STD_LOGIC; + signal \sig_adjusted_addr_incr_ireg2_reg[7]_i_1_n_3\ : STD_LOGIC; + signal \sig_adjusted_addr_incr_ireg2_reg_n_0_[0]\ : STD_LOGIC; + signal \sig_adjusted_addr_incr_ireg2_reg_n_0_[1]\ : STD_LOGIC; + signal \sig_adjusted_addr_incr_ireg2_reg_n_0_[2]\ : STD_LOGIC; + signal \sig_adjusted_addr_incr_ireg2_reg_n_0_[3]\ : STD_LOGIC; + signal \sig_adjusted_addr_incr_ireg2_reg_n_0_[4]\ : STD_LOGIC; + signal \sig_adjusted_addr_incr_ireg2_reg_n_0_[5]\ : STD_LOGIC; + signal \sig_adjusted_addr_incr_ireg2_reg_n_0_[6]\ : STD_LOGIC; + signal \sig_adjusted_addr_incr_ireg2_reg_n_0_[7]\ : STD_LOGIC; + signal sig_brst_cnt_eq_one_im0 : STD_LOGIC; + signal sig_brst_cnt_eq_one_ireg1 : STD_LOGIC; + signal sig_brst_cnt_eq_zero_im0 : STD_LOGIC; + signal sig_brst_cnt_eq_zero_ireg1 : STD_LOGIC; + signal sig_btt_cntr_im00 : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \sig_btt_cntr_im00_carry__0_i_1_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_im00_carry__0_i_2_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_im00_carry__0_i_3_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_im00_carry__0_i_4_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_im00_carry__0_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_im00_carry__0_n_1\ : STD_LOGIC; + signal \sig_btt_cntr_im00_carry__0_n_2\ : STD_LOGIC; + signal \sig_btt_cntr_im00_carry__0_n_3\ : STD_LOGIC; + signal \sig_btt_cntr_im00_carry__1_i_1_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_im00_carry__1_i_2_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_im00_carry__1_i_3_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_im00_carry__1_i_4_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_im00_carry__1_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_im00_carry__1_n_1\ : STD_LOGIC; + signal \sig_btt_cntr_im00_carry__1_n_2\ : STD_LOGIC; + signal \sig_btt_cntr_im00_carry__1_n_3\ : STD_LOGIC; + signal \sig_btt_cntr_im00_carry__2_i_1_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_im00_carry__2_i_2_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_im00_carry__2_i_3_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_im00_carry__2_i_4_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_im00_carry__2_n_1\ : STD_LOGIC; + signal \sig_btt_cntr_im00_carry__2_n_2\ : STD_LOGIC; + signal \sig_btt_cntr_im00_carry__2_n_3\ : STD_LOGIC; + signal sig_btt_cntr_im00_carry_i_1_n_0 : STD_LOGIC; + signal sig_btt_cntr_im00_carry_i_2_n_0 : STD_LOGIC; + signal sig_btt_cntr_im00_carry_i_3_n_0 : STD_LOGIC; + signal sig_btt_cntr_im00_carry_i_4_n_0 : STD_LOGIC; + signal sig_btt_cntr_im00_carry_n_0 : STD_LOGIC; + signal sig_btt_cntr_im00_carry_n_1 : STD_LOGIC; + signal sig_btt_cntr_im00_carry_n_2 : STD_LOGIC; + signal sig_btt_cntr_im00_carry_n_3 : STD_LOGIC; + signal \sig_btt_cntr_im0[0]_i_1_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_im0[10]_i_1_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_im0[11]_i_1_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_im0[12]_i_1_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_im0[13]_i_1_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_im0[14]_i_1_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_im0[15]_i_1_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_im0[1]_i_1_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_im0[2]_i_1_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_im0[3]_i_1_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_im0[4]_i_1_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_im0[5]_i_1_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_im0[6]_i_1_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_im0[7]_i_1_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_im0[8]_i_1_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_im0[9]_i_1_n_0\ : STD_LOGIC; + signal sig_btt_eq_b2mbaa_im0 : STD_LOGIC; + signal sig_btt_eq_b2mbaa_im01 : STD_LOGIC; + signal sig_btt_eq_b2mbaa_im01_carry_i_1_n_0 : STD_LOGIC; + signal sig_btt_eq_b2mbaa_im01_carry_i_2_n_0 : STD_LOGIC; + signal sig_btt_eq_b2mbaa_im01_carry_i_3_n_0 : STD_LOGIC; + signal sig_btt_eq_b2mbaa_im01_carry_i_4_n_0 : STD_LOGIC; + signal sig_btt_eq_b2mbaa_im01_carry_n_2 : STD_LOGIC; + signal sig_btt_eq_b2mbaa_im01_carry_n_3 : STD_LOGIC; + signal sig_btt_eq_b2mbaa_ireg1 : STD_LOGIC; + signal sig_btt_lt_b2mbaa_im0 : STD_LOGIC; + signal sig_btt_lt_b2mbaa_im01 : STD_LOGIC; + signal \sig_btt_lt_b2mbaa_im01_carry__0_i_1_n_0\ : STD_LOGIC; + signal \sig_btt_lt_b2mbaa_im01_carry__0_i_2_n_0\ : STD_LOGIC; + signal sig_btt_lt_b2mbaa_im01_carry_i_1_n_0 : STD_LOGIC; + signal sig_btt_lt_b2mbaa_im01_carry_i_2_n_0 : STD_LOGIC; + signal sig_btt_lt_b2mbaa_im01_carry_i_3_n_0 : STD_LOGIC; + signal sig_btt_lt_b2mbaa_im01_carry_i_4_n_0 : STD_LOGIC; + signal sig_btt_lt_b2mbaa_im01_carry_i_5_n_0 : STD_LOGIC; + signal sig_btt_lt_b2mbaa_im01_carry_i_6_n_0 : STD_LOGIC; + signal sig_btt_lt_b2mbaa_im01_carry_i_7_n_0 : STD_LOGIC; + signal sig_btt_lt_b2mbaa_im01_carry_i_8_n_0 : STD_LOGIC; + signal sig_btt_lt_b2mbaa_im01_carry_i_9_n_0 : STD_LOGIC; + signal sig_btt_lt_b2mbaa_im01_carry_n_0 : STD_LOGIC; + signal sig_btt_lt_b2mbaa_im01_carry_n_1 : STD_LOGIC; + signal sig_btt_lt_b2mbaa_im01_carry_n_2 : STD_LOGIC; + signal sig_btt_lt_b2mbaa_im01_carry_n_3 : STD_LOGIC; + signal sig_btt_lt_b2mbaa_ireg1 : STD_LOGIC; + signal sig_btt_lt_b2mbaa_ireg1_i_2_n_0 : STD_LOGIC; + signal sig_btt_residue_slice_im0 : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \sig_byte_change_minus1_im2/i__n_0\ : STD_LOGIC; + signal sig_bytes_to_mbaa_ireg1 : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \sig_bytes_to_mbaa_ireg1[1]_i_1_n_0\ : STD_LOGIC; + signal \sig_bytes_to_mbaa_ireg1[2]_i_1_n_0\ : STD_LOGIC; + signal \sig_bytes_to_mbaa_ireg1[3]_i_1_n_0\ : STD_LOGIC; + signal \sig_bytes_to_mbaa_ireg1[4]_i_1_n_0\ : STD_LOGIC; + signal \sig_bytes_to_mbaa_ireg1[5]_i_1_n_0\ : STD_LOGIC; + signal \sig_bytes_to_mbaa_ireg1[6]_i_1_n_0\ : STD_LOGIC; + signal \sig_bytes_to_mbaa_ireg1[7]_i_1_n_0\ : STD_LOGIC; + signal \sig_bytes_to_mbaa_ireg1[7]_i_2_n_0\ : STD_LOGIC; + signal \^sig_calc_error_pushed\ : STD_LOGIC; + signal sig_calc_error_pushed_i_1_n_0 : STD_LOGIC; + signal sig_calc_error_reg0 : STD_LOGIC; + signal sig_cmd2addr_valid_i_1_n_0 : STD_LOGIC; + signal sig_cmd2data_valid_i_1_n_0 : STD_LOGIC; + signal sig_cmd2dre_valid_i_1_n_0 : STD_LOGIC; + signal sig_first_xfer_im0 : STD_LOGIC; + signal sig_first_xfer_im0_i_1_n_0 : STD_LOGIC; + signal \^sig_init_reg\ : STD_LOGIC; + signal sig_input_cache_type_reg0 : STD_LOGIC; + signal \^sig_input_reg_empty\ : STD_LOGIC; + signal sig_input_reg_empty_i_1_n_0 : STD_LOGIC; + signal sig_ld_xfer_reg : STD_LOGIC; + signal sig_ld_xfer_reg_i_1_n_0 : STD_LOGIC; + signal sig_ld_xfer_reg_tmp : STD_LOGIC; + signal sig_ld_xfer_reg_tmp_i_1_n_0 : STD_LOGIC; + signal \^sig_mstr2addr_cmd_valid\ : STD_LOGIC; + signal \^sig_mstr2data_cmd_valid\ : STD_LOGIC; + signal \^sig_mstr2data_sequential\ : STD_LOGIC; + signal \^sig_mstr2sf_cmd_valid\ : STD_LOGIC; + signal sig_mstr2sf_eof : STD_LOGIC; + signal sig_no_btt_residue_im0 : STD_LOGIC; + signal sig_no_btt_residue_ireg1 : STD_LOGIC; + signal sig_no_btt_residue_ireg1_i_2_n_0 : STD_LOGIC; + signal sig_parent_done : STD_LOGIC; + signal sig_parent_done_i_1_n_0 : STD_LOGIC; + signal sig_pcc_sm_state : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute RTL_KEEP : string; + attribute RTL_KEEP of sig_pcc_sm_state : signal is "yes"; + signal sig_pop_xfer_reg0_out : STD_LOGIC; + signal sig_predict_addr_lsh_im2 : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal sig_predict_addr_lsh_ireg3 : STD_LOGIC_VECTOR ( 15 to 15 ); + signal \sig_predict_addr_lsh_ireg3[11]_i_2_n_0\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3[11]_i_3_n_0\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3[11]_i_4_n_0\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3[11]_i_5_n_0\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3[15]_i_2_n_0\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3[15]_i_3_n_0\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3[15]_i_4_n_0\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3[15]_i_5_n_0\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3[3]_i_2_n_0\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3[3]_i_3_n_0\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3[3]_i_4_n_0\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3[3]_i_5_n_0\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3[7]_i_2_n_0\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3[7]_i_3_n_0\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3[7]_i_4_n_0\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3[7]_i_5_n_0\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_0\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_1\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_2\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_3\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_1\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_2\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_3\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_0\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_1\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_2\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_3\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_0\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_1\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_2\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_3\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3_reg_n_0_[0]\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3_reg_n_0_[10]\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3_reg_n_0_[11]\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3_reg_n_0_[12]\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3_reg_n_0_[13]\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3_reg_n_0_[14]\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3_reg_n_0_[1]\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3_reg_n_0_[2]\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3_reg_n_0_[3]\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3_reg_n_0_[4]\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3_reg_n_0_[5]\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3_reg_n_0_[6]\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3_reg_n_0_[7]\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3_reg_n_0_[8]\ : STD_LOGIC; + signal \sig_predict_addr_lsh_ireg3_reg_n_0_[9]\ : STD_LOGIC; + signal sig_sm_halt_ns : STD_LOGIC; + signal \^sig_sm_halt_reg\ : STD_LOGIC; + signal sig_sm_ld_calc1_reg : STD_LOGIC; + signal sig_sm_ld_calc1_reg_ns : STD_LOGIC; + signal sig_sm_ld_calc1_reg_ns0_out : STD_LOGIC; + signal sig_sm_ld_calc2_reg : STD_LOGIC; + signal sig_sm_ld_calc2_reg_ns : STD_LOGIC; + signal sig_sm_ld_calc3_reg : STD_LOGIC; + signal sig_sm_ld_calc3_reg_ns : STD_LOGIC; + signal sig_sm_ld_xfer_reg_ns : STD_LOGIC; + signal sig_sm_pop_input_reg : STD_LOGIC; + signal sig_sm_pop_input_reg_ns : STD_LOGIC; + signal sig_xfer_reg_empty : STD_LOGIC; + signal sig_xfer_reg_empty_i_1_n_0 : STD_LOGIC; + signal \NLW_sig_addr_cntr_im0_msh_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_sig_adjusted_addr_incr_ireg2_reg[7]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_sig_btt_cntr_im00_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal NLW_sig_btt_eq_b2mbaa_im01_carry_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 to 3 ); + signal NLW_sig_btt_eq_b2mbaa_im01_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_sig_btt_lt_b2mbaa_im01_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_sig_btt_lt_b2mbaa_im01_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_sig_btt_lt_b2mbaa_im01_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_sig_predict_addr_lsh_ireg3_reg[15]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_sig_pcc_sm_state[0]_i_2\ : label is "soft_lutpair138"; + attribute KEEP : string; + attribute KEEP of \FSM_sequential_sig_pcc_sm_state_reg[0]\ : label is "yes"; + attribute KEEP of \FSM_sequential_sig_pcc_sm_state_reg[1]\ : label is "yes"; + attribute KEEP of \FSM_sequential_sig_pcc_sm_state_reg[2]\ : label is "yes"; + attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[2]_i_2\ : label is "soft_lutpair138"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][10]_srl4_i_1\ : label is "soft_lutpair156"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][11]_srl4_i_1\ : label is "soft_lutpair150"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][12]_srl4_i_1\ : label is "soft_lutpair154"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][13]_srl4_i_1\ : label is "soft_lutpair145"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][14]_srl4_i_1\ : label is "soft_lutpair151"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][15]_srl4_i_1\ : label is "soft_lutpair143"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][16]_srl4_i_1\ : label is "soft_lutpair144"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][17]_srl4_i_1\ : label is "soft_lutpair142"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][18]_srl4_i_1\ : label is "soft_lutpair141"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][19]_srl4_i_1\ : label is "soft_lutpair140"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][20]_srl4_i_1\ : label is "soft_lutpair146"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][21]_srl4_i_1\ : label is "soft_lutpair147"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][22]_srl4_i_1\ : label is "soft_lutpair148"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][23]_srl4_i_1\ : label is "soft_lutpair149"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][24]_srl4_i_1\ : label is "soft_lutpair152"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][25]_srl4_i_1\ : label is "soft_lutpair151"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][26]_srl4_i_1\ : label is "soft_lutpair149"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][27]_srl4_i_1\ : label is "soft_lutpair148"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][28]_srl4_i_1\ : label is "soft_lutpair147"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][29]_srl4_i_1\ : label is "soft_lutpair146"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][30]_srl4_i_1\ : label is "soft_lutpair145"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][31]_srl4_i_1\ : label is "soft_lutpair144"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][32]_srl4_i_1__0\ : label is "soft_lutpair143"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][33]_srl4_i_1__0\ : label is "soft_lutpair142"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][34]_srl4_i_1\ : label is "soft_lutpair137"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][34]_srl4_i_1__0\ : label is "soft_lutpair141"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][35]_srl4_i_1\ : label is "soft_lutpair140"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][36]_srl4_i_1\ : label is "soft_lutpair134"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][37]_srl4_i_1\ : label is "soft_lutpair134"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][39]_srl4_i_1\ : label is "soft_lutpair158"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][40]_srl4_i_1\ : label is "soft_lutpair158"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][4]_srl4_i_2\ : label is "soft_lutpair154"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][5]_srl4_i_1\ : label is "soft_lutpair153"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][6]_srl4_i_1\ : label is "soft_lutpair152"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][7]_srl4_i_1__1\ : label is "soft_lutpair157"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][8]_srl4_i_1\ : label is "soft_lutpair157"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][9]_srl4_i_1\ : label is "soft_lutpair156"; + attribute SOFT_HLUTNM of sig_addr_aligned_ireg1_i_1 : label is "soft_lutpair150"; + attribute SOFT_HLUTNM of \sig_addr_cntr_incr_ireg2[0]_i_1\ : label is "soft_lutpair136"; + attribute SOFT_HLUTNM of \sig_addr_cntr_incr_ireg2[8]_i_1\ : label is "soft_lutpair136"; + attribute SOFT_HLUTNM of sig_brst_cnt_eq_one_ireg1_i_1 : label is "soft_lutpair135"; + attribute SOFT_HLUTNM of sig_brst_cnt_eq_zero_ireg1_i_1 : label is "soft_lutpair135"; + attribute SOFT_HLUTNM of sig_btt_lt_b2mbaa_im01_carry_i_9 : label is "soft_lutpair133"; + attribute SOFT_HLUTNM of \sig_bytes_to_mbaa_ireg1[1]_i_1\ : label is "soft_lutpair153"; + attribute SOFT_HLUTNM of \sig_bytes_to_mbaa_ireg1[2]_i_1\ : label is "soft_lutpair139"; + attribute SOFT_HLUTNM of \sig_bytes_to_mbaa_ireg1[3]_i_1\ : label is "soft_lutpair139"; + attribute SOFT_HLUTNM of \sig_bytes_to_mbaa_ireg1[4]_i_1\ : label is "soft_lutpair133"; + attribute SOFT_HLUTNM of \sig_bytes_to_mbaa_ireg1[6]_i_1\ : label is "soft_lutpair155"; + attribute SOFT_HLUTNM of \sig_bytes_to_mbaa_ireg1[7]_i_1\ : label is "soft_lutpair155"; + attribute SOFT_HLUTNM of sig_calc_error_pushed_i_1 : label is "soft_lutpair137"; begin - \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(31 downto 0) <= \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(31 downto 0); - \hsize_vid_reg[15]\(15 downto 0) <= \^hsize_vid_reg[15]\(15 downto 0); - p_64_out <= \^p_64_out\; - \stride_vid_reg[15]\(15 downto 0) <= \^stride_vid_reg[15]\(15 downto 0); - \vsize_vid_reg[12]\(12 downto 0) <= \^vsize_vid_reg[12]\(12 downto 0); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[0]\: unisim.vcomponents.FDRE + \in\(38 downto 0) <= \^in\(38 downto 0); + sig_calc_error_pushed <= \^sig_calc_error_pushed\; + sig_init_reg <= \^sig_init_reg\; + sig_input_reg_empty <= \^sig_input_reg_empty\; + sig_mstr2addr_cmd_valid <= \^sig_mstr2addr_cmd_valid\; + sig_mstr2data_cmd_valid <= \^sig_mstr2data_cmd_valid\; + sig_mstr2data_sequential <= \^sig_mstr2data_sequential\; + sig_mstr2sf_cmd_valid <= \^sig_mstr2sf_cmd_valid\; + sig_sm_halt_reg <= \^sig_sm_halt_reg\; +\FSM_sequential_sig_pcc_sm_state[0]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"DD3F00FFDD3F33FF" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(0), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(0), - R => SR(0) + I0 => sig_pop_xfer_reg0_out, + I1 => sig_pcc_sm_state(1), + I2 => sig_sm_ld_calc1_reg_ns0_out, + I3 => sig_pcc_sm_state(0), + I4 => sig_pcc_sm_state(2), + I5 => sig_calc_error_reg0, + O => \FSM_sequential_sig_pcc_sm_state[0]_i_1_n_0\ ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[10]\: unisim.vcomponents.FDRE +\FSM_sequential_sig_pcc_sm_state[0]_i_2\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"1" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(10), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(10), - R => SR(0) + I0 => sig_parent_done, + I1 => \^sig_calc_error_pushed\, + O => sig_sm_ld_calc1_reg_ns0_out ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[11]\: unisim.vcomponents.FDRE +\FSM_sequential_sig_pcc_sm_state[1]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"A8A0A8A00AA000A0" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(11), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(11), - R => SR(0) + I0 => \FSM_sequential_sig_pcc_sm_state[1]_i_2_n_0\, + I1 => sig_pop_xfer_reg0_out, + I2 => sig_pcc_sm_state(1), + I3 => sig_pcc_sm_state(0), + I4 => sig_calc_error_reg0, + I5 => sig_pcc_sm_state(2), + O => \FSM_sequential_sig_pcc_sm_state[1]_i_1_n_0\ ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[12]\: unisim.vcomponents.FDRE +\FSM_sequential_sig_pcc_sm_state[1]_i_2\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"FFF7" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(12), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(12), - R => SR(0) + I0 => sig_pcc_sm_state(2), + I1 => sig_parent_done, + I2 => \^sig_calc_error_pushed\, + I3 => sig_pcc_sm_state(0), + O => \FSM_sequential_sig_pcc_sm_state[1]_i_2_n_0\ ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[13]\: unisim.vcomponents.FDRE +\FSM_sequential_sig_pcc_sm_state[1]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"DD0DDD0D0000DD0C" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(13), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(13), - R => SR(0) + I0 => \^sig_mstr2sf_cmd_valid\, + I1 => sig_wr_fifo, + I2 => \^sig_mstr2data_cmd_valid\, + I3 => sig_wr_fifo_0, + I4 => \^sig_mstr2addr_cmd_valid\, + I5 => sig_wr_fifo_1, + O => sig_pop_xfer_reg0_out ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[14]\: unisim.vcomponents.FDRE +\FSM_sequential_sig_pcc_sm_state[2]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"ECAA" ) port map ( + I0 => sig_pcc_sm_state(2), + I1 => sig_pcc_sm_state(0), + I2 => \^sig_calc_error_pushed\, + I3 => sig_pcc_sm_state(1), + O => \FSM_sequential_sig_pcc_sm_state[2]_i_1_n_0\ + ); +\FSM_sequential_sig_pcc_sm_state_reg[0]\: unisim.vcomponents.FDRE + port map ( C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(14), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(14), - R => SR(0) + CE => '1', + D => \FSM_sequential_sig_pcc_sm_state[0]_i_1_n_0\, + Q => sig_pcc_sm_state(0), + R => \^sig_init_reg\ ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[15]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( +\FSM_sequential_sig_pcc_sm_state_reg[1]\: unisim.vcomponents.FDRE + port map ( C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(15), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(15), - R => SR(0) + CE => '1', + D => \FSM_sequential_sig_pcc_sm_state[1]_i_1_n_0\, + Q => sig_pcc_sm_state(1), + R => \^sig_init_reg\ ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[16]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( +\FSM_sequential_sig_pcc_sm_state_reg[2]\: unisim.vcomponents.FDRE + port map ( C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(16), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(16), - R => SR(0) + CE => '1', + D => \FSM_sequential_sig_pcc_sm_state[2]_i_1_n_0\, + Q => sig_pcc_sm_state(2), + R => \^sig_init_reg\ ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[17]\: unisim.vcomponents.FDRE +\INFERRED_GEN.cnt_i[2]_i_2\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"0010" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(17), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(17), - R => SR(0) + I0 => \^sig_calc_error_pushed\, + I1 => \^sig_sm_halt_reg\, + I2 => \^sig_input_reg_empty\, + I3 => Q(0), + O => FIFO_Full_reg ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[18]\: unisim.vcomponents.FDRE +\INFERRED_GEN.data_reg[3][10]_srl4_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(18), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(18), - R => SR(0) + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[6]\, + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(6), + O => \^in\(6) ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[19]\: unisim.vcomponents.FDRE +\INFERRED_GEN.data_reg[3][11]_srl4_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(19), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(19), - R => SR(0) + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[7]\, + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(7), + O => \^in\(7) ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[1]\: unisim.vcomponents.FDRE +\INFERRED_GEN.data_reg[3][12]_srl4_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(1), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(1), - R => SR(0) + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[8]\, + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(8), + O => \^in\(8) ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[20]\: unisim.vcomponents.FDRE +\INFERRED_GEN.data_reg[3][13]_srl4_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(20), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(20), - R => SR(0) + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[9]\, + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(9), + O => \^in\(9) ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[21]\: unisim.vcomponents.FDRE +\INFERRED_GEN.data_reg[3][14]_srl4_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(21), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(21), - R => SR(0) + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[10]\, + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(10), + O => \^in\(10) ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[22]\: unisim.vcomponents.FDRE +\INFERRED_GEN.data_reg[3][15]_srl4_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(22), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(22), - R => SR(0) + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[11]\, + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(11), + O => \^in\(11) ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[23]\: unisim.vcomponents.FDRE +\INFERRED_GEN.data_reg[3][16]_srl4_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(23), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(23), - R => SR(0) + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[12]\, + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(12), + O => \^in\(12) ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[24]\: unisim.vcomponents.FDRE +\INFERRED_GEN.data_reg[3][17]_srl4_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(24), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(24), - R => SR(0) + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[13]\, + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(13), + O => \^in\(13) ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[25]\: unisim.vcomponents.FDRE +\INFERRED_GEN.data_reg[3][18]_srl4_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(25), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(25), - R => SR(0) + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[14]\, + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(14), + O => \^in\(14) ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[26]\: unisim.vcomponents.FDRE +\INFERRED_GEN.data_reg[3][19]_srl4_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(26), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(26), - R => SR(0) + I0 => p_1_in_0, + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(15), + O => \^in\(15) ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[27]\: unisim.vcomponents.FDRE +\INFERRED_GEN.data_reg[3][20]_srl4_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(27), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(27), - R => SR(0) + I0 => sig_addr_cntr_im0_msh_reg(0), + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(16), + O => \^in\(16) ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[28]\: unisim.vcomponents.FDRE +\INFERRED_GEN.data_reg[3][21]_srl4_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(28), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(28), - R => SR(0) + I0 => sig_addr_cntr_im0_msh_reg(1), + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(17), + O => \^in\(17) ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[29]\: unisim.vcomponents.FDRE +\INFERRED_GEN.data_reg[3][22]_srl4_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(29), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(29), - R => SR(0) + I0 => sig_addr_cntr_im0_msh_reg(2), + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(18), + O => \^in\(18) ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[2]\: unisim.vcomponents.FDRE +\INFERRED_GEN.data_reg[3][23]_srl4_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(2), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(2), - R => SR(0) + I0 => sig_addr_cntr_im0_msh_reg(3), + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(19), + O => \^in\(19) ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[30]\: unisim.vcomponents.FDRE +\INFERRED_GEN.data_reg[3][24]_srl4_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(30), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(30), - R => SR(0) + I0 => sig_addr_cntr_im0_msh_reg(4), + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(20), + O => \^in\(20) ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\: unisim.vcomponents.FDRE +\INFERRED_GEN.data_reg[3][25]_srl4_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(31), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(31), - R => SR(0) + I0 => sig_addr_cntr_im0_msh_reg(5), + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(21), + O => \^in\(21) ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[3]\: unisim.vcomponents.FDRE +\INFERRED_GEN.data_reg[3][26]_srl4_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(3), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(3), - R => SR(0) + I0 => sig_addr_cntr_im0_msh_reg(6), + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(22), + O => \^in\(22) ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[4]\: unisim.vcomponents.FDRE +\INFERRED_GEN.data_reg[3][27]_srl4_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(4), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(4), - R => SR(0) + I0 => sig_addr_cntr_im0_msh_reg(7), + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(23), + O => \^in\(23) ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[5]\: unisim.vcomponents.FDRE +\INFERRED_GEN.data_reg[3][28]_srl4_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(5), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(5), - R => SR(0) + I0 => sig_addr_cntr_im0_msh_reg(8), + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(24), + O => \^in\(24) ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[6]\: unisim.vcomponents.FDRE +\INFERRED_GEN.data_reg[3][29]_srl4_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(6), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(6), - R => SR(0) + I0 => sig_addr_cntr_im0_msh_reg(9), + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(25), + O => \^in\(25) ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[7]\: unisim.vcomponents.FDRE +\INFERRED_GEN.data_reg[3][30]_srl4_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(7), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(7), - R => SR(0) + I0 => sig_addr_cntr_im0_msh_reg(10), + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(26), + O => \^in\(26) ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[8]\: unisim.vcomponents.FDRE +\INFERRED_GEN.data_reg[3][31]_srl4_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(8), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(8), - R => SR(0) + I0 => sig_addr_cntr_im0_msh_reg(11), + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(27), + O => \^in\(27) ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[9]\: unisim.vcomponents.FDRE +\INFERRED_GEN.data_reg[3][32]_srl4_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"2" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(3), - D => D(9), - Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(9), - R => SR(0) + I0 => sig_mstr2sf_eof, + I1 => \^sig_mstr2data_sequential\, + O => sig_next_cmd_cmplt_reg_reg(0) ); -\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_i_1\: unisim.vcomponents.LUT5 +\INFERRED_GEN.data_reg[3][32]_srl4_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => X"003A0000" + INIT => X"B8" ) port map ( - I0 => p_63_out, - I1 => p_23_out, - I2 => prmtr_update_complete, - I3 => halted_reg, - I4 => prmry_resetn_i_reg_0, - O => \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg\ - ); -\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(2), - D => D(0), - Q => \^stride_vid_reg[15]\(0), - R => SR(0) - ); -\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[10]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(2), - D => D(10), - Q => \^stride_vid_reg[15]\(10), - R => SR(0) - ); -\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[11]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(2), - D => D(11), - Q => \^stride_vid_reg[15]\(11), - R => SR(0) - ); -\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[12]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(2), - D => D(12), - Q => \^stride_vid_reg[15]\(12), - R => SR(0) - ); -\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[13]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(2), - D => D(13), - Q => \^stride_vid_reg[15]\(13), - R => SR(0) - ); -\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[14]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(2), - D => D(14), - Q => \^stride_vid_reg[15]\(14), - R => SR(0) + I0 => sig_addr_cntr_im0_msh_reg(12), + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(28), + O => \^in\(28) ); -\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(2), - D => D(15), - Q => \^stride_vid_reg[15]\(15), - R => SR(0) +\INFERRED_GEN.data_reg[3][33]_srl4_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00FFFFFF57575757" + ) + port map ( + I0 => sig_brst_cnt_eq_zero_ireg1, + I1 => sig_btt_eq_b2mbaa_ireg1, + I2 => sig_btt_lt_b2mbaa_ireg1, + I3 => sig_brst_cnt_eq_one_ireg1, + I4 => sig_addr_aligned_ireg1, + I5 => sig_no_btt_residue_ireg1, + O => \^sig_mstr2data_sequential\ ); -\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(2), - D => D(1), - Q => \^stride_vid_reg[15]\(1), - R => SR(0) +\INFERRED_GEN.data_reg[3][33]_srl4_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_addr_cntr_im0_msh_reg(13), + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(29), + O => \^in\(29) ); -\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(2), - D => D(2), - Q => \^stride_vid_reg[15]\(2), - R => SR(0) +\INFERRED_GEN.data_reg[3][34]_srl4_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^in\(38), + I1 => \^sig_mstr2data_sequential\, + O => sig_next_cmd_cmplt_reg_reg(1) ); -\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(2), - D => D(3), - Q => \^stride_vid_reg[15]\(3), - R => SR(0) +\INFERRED_GEN.data_reg[3][34]_srl4_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_addr_cntr_im0_msh_reg(14), + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(30), + O => \^in\(30) ); -\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(2), - D => D(4), - Q => \^stride_vid_reg[15]\(4), - R => SR(0) +\INFERRED_GEN.data_reg[3][35]_srl4_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_addr_cntr_im0_msh_reg(15), + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(31), + O => \^in\(31) ); -\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(2), - D => D(5), - Q => \^stride_vid_reg[15]\(5), - R => SR(0) +\INFERRED_GEN.data_reg[3][36]_srl4_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FE01" + ) + port map ( + I0 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[2]\, + I1 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[0]\, + I2 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[1]\, + I3 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[3]\, + O => \^in\(32) ); -\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(2), - D => D(6), - Q => \^stride_vid_reg[15]\(6), - R => SR(0) +\INFERRED_GEN.data_reg[3][37]_srl4_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFE0001" + ) + port map ( + I0 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[3]\, + I1 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[1]\, + I2 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[0]\, + I3 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[2]\, + I4 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[4]\, + O => \^in\(33) ); -\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(2), - D => D(7), - Q => \^stride_vid_reg[15]\(7), - R => SR(0) +\INFERRED_GEN.data_reg[3][38]_srl4_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFE00000001" + ) + port map ( + I0 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[4]\, + I1 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[2]\, + I2 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[0]\, + I3 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[1]\, + I4 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[3]\, + I5 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[5]\, + O => \^in\(34) ); -\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[8]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(2), - D => D(8), - Q => \^stride_vid_reg[15]\(8), - R => SR(0) +\INFERRED_GEN.data_reg[3][39]_srl4_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \sig_byte_change_minus1_im2/i__n_0\, + I1 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[6]\, + O => \^in\(35) ); -\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[9]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(2), - D => D(9), - Q => \^stride_vid_reg[15]\(9), - R => SR(0) +\INFERRED_GEN.data_reg[3][40]_srl4_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E1" + ) + port map ( + I0 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[6]\, + I1 => \sig_byte_change_minus1_im2/i__n_0\, + I2 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[7]\, + O => \^in\(36) ); -ip2axi_rddata_int_inferred_i_65: unisim.vcomponents.LUT5 +\INFERRED_GEN.data_reg[3][4]_srl4_i_2\: unisim.vcomponents.LUT3 generic map( - INIT => X"AFC0A0C0" + INIT => X"B8" ) port map ( - I0 => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(15), - I1 => \^stride_vid_reg[15]\(15), - I2 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1), - I3 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(0), - I4 => \^hsize_vid_reg[15]\(15), - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]\ + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(0), + O => \^in\(0) ); -ip2axi_rddata_int_inferred_i_67: unisim.vcomponents.LUT5 +\INFERRED_GEN.data_reg[3][5]_srl4_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AFC0A0C0" + INIT => X"B8" ) port map ( - I0 => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(14), - I1 => \^stride_vid_reg[15]\(14), - I2 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1), - I3 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(0), - I4 => \^hsize_vid_reg[15]\(14), - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[14]\ + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(1), + O => \^in\(1) ); -ip2axi_rddata_int_inferred_i_69: unisim.vcomponents.LUT5 +\INFERRED_GEN.data_reg[3][6]_srl4_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AFC0A0C0" + INIT => X"B8" ) port map ( - I0 => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(13), - I1 => \^stride_vid_reg[15]\(13), - I2 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1), - I3 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(0), - I4 => \^hsize_vid_reg[15]\(13), - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[13]\ + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(2), + O => \^in\(2) ); -ip2axi_rddata_int_inferred_i_71: unisim.vcomponents.LUT6 +\INFERRED_GEN.data_reg[3][7]_srl4_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AFA0CFCFAFA0C0C0" + INIT => X"B8" ) port map ( - I0 => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(12), - I1 => \^stride_vid_reg[15]\(12), - I2 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1), - I3 => \^hsize_vid_reg[15]\(12), - I4 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(0), - I5 => \^vsize_vid_reg[12]\(12), - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]\ + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[3]\, + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(3), + O => \^in\(3) ); -ip2axi_rddata_int_inferred_i_73: unisim.vcomponents.LUT6 +\INFERRED_GEN.data_reg[3][8]_srl4_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AFA0CFCFAFA0C0C0" + INIT => X"B8" ) port map ( - I0 => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(11), - I1 => \^stride_vid_reg[15]\(11), - I2 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1), - I3 => \^hsize_vid_reg[15]\(11), - I4 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(0), - I5 => \^vsize_vid_reg[12]\(11), - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]\ + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[4]\, + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(4), + O => \^in\(4) ); -ip2axi_rddata_int_inferred_i_74: unisim.vcomponents.LUT6 +\INFERRED_GEN.data_reg[3][9]_srl4_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AFA0CFCFAFA0C0C0" + INIT => X"B8" ) port map ( - I0 => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(10), - I1 => \^stride_vid_reg[15]\(10), - I2 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1), - I3 => \^hsize_vid_reg[15]\(10), - I4 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(0), - I5 => \^vsize_vid_reg[12]\(10), - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10]\ + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[5]\, + I1 => \^in\(37), + I2 => sig_addr_cntr_lsh_kh(5), + O => \^in\(5) ); -ip2axi_rddata_int_inferred_i_75: unisim.vcomponents.LUT6 +sig_addr_aligned_ireg1_i_1: unisim.vcomponents.LUT3 generic map( - INIT => X"AFA0CFCFAFA0C0C0" + INIT => X"04" ) port map ( - I0 => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(9), - I1 => \^stride_vid_reg[15]\(9), - I2 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1), - I3 => \^hsize_vid_reg[15]\(9), - I4 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(0), - I5 => \^vsize_vid_reg[12]\(9), - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9]\ + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[6]\, + I1 => \sig_bytes_to_mbaa_ireg1[7]_i_2_n_0\, + I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[7]\, + O => sig_addr_aligned_im0 ); -ip2axi_rddata_int_inferred_i_76: unisim.vcomponents.LUT6 +sig_addr_aligned_ireg1_reg: unisim.vcomponents.FDRE generic map( - INIT => X"AFA0CFCFAFA0C0C0" + INIT => '0' ) port map ( - I0 => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(8), - I1 => \^stride_vid_reg[15]\(8), - I2 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1), - I3 => \^hsize_vid_reg[15]\(8), - I4 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(0), - I5 => \^vsize_vid_reg[12]\(8), - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8]\ + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc1_reg, + D => sig_addr_aligned_im0, + Q => sig_addr_aligned_ireg1, + R => \^sig_init_reg\ ); -ip2axi_rddata_int_inferred_i_77: unisim.vcomponents.LUT6 +\sig_addr_cntr_im0_msh[0]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"AFA0CFCFAFA0C0C0" + INIT => X"BAAA" ) port map ( - I0 => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(7), - I1 => \^stride_vid_reg[15]\(7), - I2 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1), - I3 => \^hsize_vid_reg[15]\(7), - I4 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(0), - I5 => \^vsize_vid_reg[12]\(7), - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7]\ + I0 => sig_calc_error_reg0, + I1 => sig_predict_addr_lsh_ireg3(15), + I2 => p_1_in_0, + I3 => sig_pop_xfer_reg0_out, + O => \sig_addr_cntr_im0_msh[0]_i_1_n_0\ ); -ip2axi_rddata_int_inferred_i_78: unisim.vcomponents.LUT6 +\sig_addr_cntr_im0_msh[0]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"AFA0CFCFAFA0C0C0" + INIT => X"FFFFFEFF00000200" ) port map ( - I0 => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(6), - I1 => \^stride_vid_reg[15]\(6), - I2 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1), - I3 => \^hsize_vid_reg[15]\(6), - I4 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(0), - I5 => \^vsize_vid_reg[12]\(6), - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6]\ + I0 => \out\(34), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_addr_cntr_im0_msh_reg(0), + O => \sig_addr_cntr_im0_msh[0]_i_3_n_0\ ); -ip2axi_rddata_int_inferred_i_80: unisim.vcomponents.LUT6 +\sig_addr_cntr_im0_msh[0]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"AFA0CFCFAFA0C0C0" + INIT => X"FFFFFEFF00000200" ) port map ( - I0 => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(5), - I1 => \^stride_vid_reg[15]\(5), - I2 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1), - I3 => \^hsize_vid_reg[15]\(5), - I4 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(0), - I5 => \^vsize_vid_reg[12]\(5), - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5]\ + I0 => \out\(37), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_addr_cntr_im0_msh_reg(3), + O => \sig_addr_cntr_im0_msh[0]_i_4_n_0\ ); -ip2axi_rddata_int_inferred_i_82: unisim.vcomponents.LUT6 +\sig_addr_cntr_im0_msh[0]_i_5\: unisim.vcomponents.LUT6 generic map( - INIT => X"AFA0CFCFAFA0C0C0" + INIT => X"FFFFFEFF00000200" ) port map ( - I0 => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(4), - I1 => \^stride_vid_reg[15]\(4), - I2 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1), - I3 => \^hsize_vid_reg[15]\(4), - I4 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(0), - I5 => \^vsize_vid_reg[12]\(4), - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4]\ + I0 => \out\(36), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_addr_cntr_im0_msh_reg(2), + O => \sig_addr_cntr_im0_msh[0]_i_5_n_0\ ); -ip2axi_rddata_int_inferred_i_84: unisim.vcomponents.LUT6 +\sig_addr_cntr_im0_msh[0]_i_6\: unisim.vcomponents.LUT6 generic map( - INIT => X"AFA0CFCFAFA0C0C0" + INIT => X"FFFFFEFF00000200" ) port map ( - I0 => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(3), - I1 => \^stride_vid_reg[15]\(3), - I2 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1), - I3 => \^hsize_vid_reg[15]\(3), - I4 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(0), - I5 => \^vsize_vid_reg[12]\(3), - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3]\ + I0 => \out\(35), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_addr_cntr_im0_msh_reg(1), + O => \sig_addr_cntr_im0_msh[0]_i_6_n_0\ ); -ip2axi_rddata_int_inferred_i_85: unisim.vcomponents.LUT6 +\sig_addr_cntr_im0_msh[0]_i_7\: unisim.vcomponents.LUT6 generic map( - INIT => X"AFA0CFCFAFA0C0C0" + INIT => X"5555555555555C55" ) port map ( - I0 => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(2), - I1 => \^stride_vid_reg[15]\(2), - I2 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1), - I3 => \^hsize_vid_reg[15]\(2), - I4 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(0), - I5 => \^vsize_vid_reg[12]\(2), - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[2]\ + I0 => sig_addr_cntr_im0_msh_reg(0), + I1 => \out\(34), + I2 => Q(0), + I3 => \^sig_input_reg_empty\, + I4 => \^sig_sm_halt_reg\, + I5 => \^in\(38), + O => \sig_addr_cntr_im0_msh[0]_i_7_n_0\ ); -ip2axi_rddata_int_inferred_i_87: unisim.vcomponents.LUT6 +\sig_addr_cntr_im0_msh[12]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"AFA0CFCFAFA0C0C0" + INIT => X"FFFFFEFF00000200" ) port map ( - I0 => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(1), - I1 => \^stride_vid_reg[15]\(1), - I2 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1), - I3 => \^hsize_vid_reg[15]\(1), - I4 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(0), - I5 => \^vsize_vid_reg[12]\(1), - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[1]\ + I0 => \out\(49), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_addr_cntr_im0_msh_reg(15), + O => \sig_addr_cntr_im0_msh[12]_i_2_n_0\ ); -ip2axi_rddata_int_inferred_i_89: unisim.vcomponents.LUT6 +\sig_addr_cntr_im0_msh[12]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"AFA0CFCFAFA0C0C0" + INIT => X"FFFFFEFF00000200" ) port map ( - I0 => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(0), - I1 => \^stride_vid_reg[15]\(0), - I2 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1), - I3 => \^hsize_vid_reg[15]\(0), - I4 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(0), - I5 => \^vsize_vid_reg[12]\(0), - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0]\ + I0 => \out\(48), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_addr_cntr_im0_msh_reg(14), + O => \sig_addr_cntr_im0_msh[12]_i_3_n_0\ ); -prmtr_updt_complete_i_reg: unisim.vcomponents.FDRE +\sig_addr_cntr_im0_msh[12]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => prmry_resetn_i_reg, - Q => p_63_out, - R => '0' + I0 => \out\(47), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_addr_cntr_im0_msh_reg(13), + O => \sig_addr_cntr_im0_msh[12]_i_4_n_0\ ); -\reg_module_hsize_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(1), - D => D(0), - Q => \^hsize_vid_reg[15]\(0), - R => SR(0) - ); -\reg_module_hsize_reg[10]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(1), - D => D(10), - Q => \^hsize_vid_reg[15]\(10), - R => SR(0) - ); -\reg_module_hsize_reg[11]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(1), - D => D(11), - Q => \^hsize_vid_reg[15]\(11), - R => SR(0) - ); -\reg_module_hsize_reg[12]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(1), - D => D(12), - Q => \^hsize_vid_reg[15]\(12), - R => SR(0) - ); -\reg_module_hsize_reg[13]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(1), - D => D(13), - Q => \^hsize_vid_reg[15]\(13), - R => SR(0) - ); -\reg_module_hsize_reg[14]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(1), - D => D(14), - Q => \^hsize_vid_reg[15]\(14), - R => SR(0) - ); -\reg_module_hsize_reg[15]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(1), - D => D(15), - Q => \^hsize_vid_reg[15]\(15), - R => SR(0) - ); -\reg_module_hsize_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(1), - D => D(1), - Q => \^hsize_vid_reg[15]\(1), - R => SR(0) - ); -\reg_module_hsize_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(1), - D => D(2), - Q => \^hsize_vid_reg[15]\(2), - R => SR(0) - ); -\reg_module_hsize_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(1), - D => D(3), - Q => \^hsize_vid_reg[15]\(3), - R => SR(0) - ); -\reg_module_hsize_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(1), - D => D(4), - Q => \^hsize_vid_reg[15]\(4), - R => SR(0) - ); -\reg_module_hsize_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(1), - D => D(5), - Q => \^hsize_vid_reg[15]\(5), - R => SR(0) - ); -\reg_module_hsize_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(1), - D => D(6), - Q => \^hsize_vid_reg[15]\(6), - R => SR(0) - ); -\reg_module_hsize_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(1), - D => D(7), - Q => \^hsize_vid_reg[15]\(7), - R => SR(0) - ); -\reg_module_hsize_reg[8]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(1), - D => D(8), - Q => \^hsize_vid_reg[15]\(8), - R => SR(0) - ); -\reg_module_hsize_reg[9]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(1), - D => D(9), - Q => \^hsize_vid_reg[15]\(9), - R => SR(0) - ); -\reg_module_vsize_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(0), - Q => \^vsize_vid_reg[12]\(0), - R => SR(0) - ); -\reg_module_vsize_reg[10]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(10), - Q => \^vsize_vid_reg[12]\(10), - R => SR(0) - ); -\reg_module_vsize_reg[11]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(11), - Q => \^vsize_vid_reg[12]\(11), - R => SR(0) - ); -\reg_module_vsize_reg[12]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(12), - Q => \^vsize_vid_reg[12]\(12), - R => SR(0) - ); -\reg_module_vsize_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(1), - Q => \^vsize_vid_reg[12]\(1), - R => SR(0) - ); -\reg_module_vsize_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(2), - Q => \^vsize_vid_reg[12]\(2), - R => SR(0) - ); -\reg_module_vsize_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(3), - Q => \^vsize_vid_reg[12]\(3), - R => SR(0) +\sig_addr_cntr_im0_msh[12]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFEFF00000200" + ) + port map ( + I0 => \out\(46), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_addr_cntr_im0_msh_reg(12), + O => \sig_addr_cntr_im0_msh[12]_i_5_n_0\ ); -\reg_module_vsize_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(4), - Q => \^vsize_vid_reg[12]\(4), - R => SR(0) +\sig_addr_cntr_im0_msh[4]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFEFF00000200" + ) + port map ( + I0 => \out\(41), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_addr_cntr_im0_msh_reg(7), + O => \sig_addr_cntr_im0_msh[4]_i_2_n_0\ ); -\reg_module_vsize_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(5), - Q => \^vsize_vid_reg[12]\(5), - R => SR(0) +\sig_addr_cntr_im0_msh[4]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFEFF00000200" + ) + port map ( + I0 => \out\(40), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_addr_cntr_im0_msh_reg(6), + O => \sig_addr_cntr_im0_msh[4]_i_3_n_0\ ); -\reg_module_vsize_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(6), - Q => \^vsize_vid_reg[12]\(6), - R => SR(0) +\sig_addr_cntr_im0_msh[4]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFEFF00000200" + ) + port map ( + I0 => \out\(39), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_addr_cntr_im0_msh_reg(5), + O => \sig_addr_cntr_im0_msh[4]_i_4_n_0\ ); -\reg_module_vsize_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(7), - Q => \^vsize_vid_reg[12]\(7), - R => SR(0) +\sig_addr_cntr_im0_msh[4]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFEFF00000200" + ) + port map ( + I0 => \out\(38), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_addr_cntr_im0_msh_reg(4), + O => \sig_addr_cntr_im0_msh[4]_i_5_n_0\ ); -\reg_module_vsize_reg[8]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(8), - Q => \^vsize_vid_reg[12]\(8), - R => SR(0) +\sig_addr_cntr_im0_msh[8]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFEFF00000200" + ) + port map ( + I0 => \out\(45), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_addr_cntr_im0_msh_reg(11), + O => \sig_addr_cntr_im0_msh[8]_i_2_n_0\ ); -\reg_module_vsize_reg[9]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(9), - Q => \^vsize_vid_reg[12]\(9), - R => SR(0) +\sig_addr_cntr_im0_msh[8]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFEFF00000200" + ) + port map ( + I0 => \out\(44), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_addr_cntr_im0_msh_reg(10), + O => \sig_addr_cntr_im0_msh[8]_i_3_n_0\ ); -regdir_idle_i_i_1: unisim.vcomponents.LUT6 +\sig_addr_cntr_im0_msh[8]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFEE0EFFFF" + INIT => X"FFFFFEFF00000200" ) port map ( - I0 => \^p_64_out\, - I1 => p_63_out, - I2 => \dmacr_i_reg[0]\, - I3 => run_stop_d1, - I4 => prmry_resetn_i_reg_0, - I5 => p_35_out, - O => regdir_idle_i_i_1_n_0 + I0 => \out\(43), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_addr_cntr_im0_msh_reg(9), + O => \sig_addr_cntr_im0_msh[8]_i_4_n_0\ ); -regdir_idle_i_reg: unisim.vcomponents.FDRE +\sig_addr_cntr_im0_msh[8]_i_5\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => regdir_idle_i_i_1_n_0, - Q => \^p_64_out\, - R => '0' + I0 => \out\(42), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_addr_cntr_im0_msh_reg(8), + O => \sig_addr_cntr_im0_msh[8]_i_5_n_0\ ); -run_stop_d1_reg: unisim.vcomponents.FDRE +\sig_addr_cntr_im0_msh_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => \dmacr_i_reg[0]\, - Q => run_stop_d1, - R => SR(0) + CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, + D => \sig_addr_cntr_im0_msh_reg[0]_i_2_n_7\, + Q => sig_addr_cntr_im0_msh_reg(0), + R => \^sig_init_reg\ ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_register is - port ( - run_stop_d1_reg : out STD_LOGIC; - p_68_out : out STD_LOGIC_VECTOR ( 24 downto 0 ); - err_d1_reg_0 : out STD_LOGIC; - ioc_irq_reg_0 : out STD_LOGIC; - dly_irq_reg_0 : out STD_LOGIC; - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\ : out STD_LOGIC; - \s_axis_cmd_tdata_reg[63]\ : out STD_LOGIC; - err_d1_reg_1 : out STD_LOGIC; - err_d1_reg_2 : out STD_LOGIC; - p_75_out : out STD_LOGIC; - s_soft_reset_i0 : out STD_LOGIC; - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - ch1_disable_delay2_out : out STD_LOGIC; - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - \p_6_out__1\ : out STD_LOGIC; - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : out STD_LOGIC; - stop_i : out STD_LOGIC; - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - \ch1_delay_zero__6\ : out STD_LOGIC; - err_irq_reg_0 : out STD_LOGIC; - different_delay : out STD_LOGIC; - different_thresh : out STD_LOGIC; - \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - datamover_idle_reg : out STD_LOGIC; - \s_axis_cmd_tdata_reg[63]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - mm2s_axi2ip_wrce : in STD_LOGIC_VECTOR ( 1 downto 0 ); - D : in STD_LOGIC_VECTOR ( 24 downto 0 ); - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7]\ : in STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7]_0\ : in STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4]\ : in STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12]\ : in STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13]\ : in STD_LOGIC; - \dmacr_i_reg[2]_0\ : in STD_LOGIC; - reset_counts_reg_0 : in STD_LOGIC; - halted_clr_reg : in STD_LOGIC; - slverr_i_reg : in STD_LOGIC; - decerr_i_reg : in STD_LOGIC; - mm2s_halt_cmplt : in STD_LOGIC; - halt_reset : in STD_LOGIC; - prmry_in : in STD_LOGIC; - p_17_out : in STD_LOGIC; - ch1_delay_cnt_en : in STD_LOGIC; - p_10_out : in STD_LOGIC; - \ch1_ioc_irq_set_i__0\ : in STD_LOGIC; - Q : in STD_LOGIC_VECTOR ( 0 to 0 ); - p_49_out : in STD_LOGIC; - p_44_out : in STD_LOGIC; - mm2s_dly_irq_set : in STD_LOGIC; - mm2s_halt : in STD_LOGIC; - dma_err : in STD_LOGIC; - \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg\ : in STD_LOGIC; - p_0_out : in STD_LOGIC; - p_46_out : in STD_LOGIC; - mask_fsync_out_i : in STD_LOGIC; - prmry_resetn_i_reg : in STD_LOGIC; - p_35_out : in STD_LOGIC; - mm2s_ioc_irq_set : in STD_LOGIC; - initial_frame : in STD_LOGIC; - datamover_idle : in STD_LOGIC; - p_23_out : in STD_LOGIC; - prmry_resetn_i_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); - \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_register : entity is "axi_vdma_register"; -end Arty_Z7_20_axi_vdma_0_0_axi_vdma_register; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_register is - signal \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_3_n_0\ : STD_LOGIC; - signal \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_4_n_0\ : STD_LOGIC; - signal \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_3_n_0\ : STD_LOGIC; - signal \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_4_n_0\ : STD_LOGIC; - signal \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_3_n_0\ : STD_LOGIC; - signal \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_4_n_0\ : STD_LOGIC; - signal \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]\ : STD_LOGIC; - signal \^ch1_delay_zero__6\ : STD_LOGIC; - signal \^ch1_disable_delay2_out\ : STD_LOGIC; - signal \^dly_irq_reg_0\ : STD_LOGIC; - signal dmacr_i : STD_LOGIC_VECTOR ( 0 to 0 ); - signal err : STD_LOGIC; - signal err_d1 : STD_LOGIC; - signal \^err_d1_reg_0\ : STD_LOGIC; - signal \^err_d1_reg_1\ : STD_LOGIC; - signal \^err_d1_reg_2\ : STD_LOGIC; - signal err_irq_i_1_n_0 : STD_LOGIC; - signal \^err_irq_reg_0\ : STD_LOGIC; - signal introut01_out : STD_LOGIC; - signal introut_i_1_n_0 : STD_LOGIC; - signal \^ioc_irq_reg_0\ : STD_LOGIC; - signal irqdelay_wren_i : STD_LOGIC; - signal irqthresh_wren_i : STD_LOGIC; - signal p_16_in : STD_LOGIC; - signal p_1_in : STD_LOGIC; - signal \^p_68_out\ : STD_LOGIC_VECTOR ( 24 downto 0 ); - signal \^p_6_out__1\ : STD_LOGIC; - signal \^run_stop_d1_reg\ : STD_LOGIC; - signal \^s_axis_cmd_tdata_reg[63]\ : STD_LOGIC; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_1\ : label is "soft_lutpair35"; - attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_3\ : label is "soft_lutpair36"; - attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_1\ : label is "soft_lutpair35"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[63]_i_1\ : label is "soft_lutpair36"; - attribute SOFT_HLUTNM of s_soft_reset_i_i_1 : label is "soft_lutpair37"; - attribute SOFT_HLUTNM of stop_i_1 : label is "soft_lutpair37"; -begin - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\ <= \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]\; - \ch1_delay_zero__6\ <= \^ch1_delay_zero__6\; - ch1_disable_delay2_out <= \^ch1_disable_delay2_out\; - dly_irq_reg_0 <= \^dly_irq_reg_0\; - err_d1_reg_0 <= \^err_d1_reg_0\; - err_d1_reg_1 <= \^err_d1_reg_1\; - err_d1_reg_2 <= \^err_d1_reg_2\; - err_irq_reg_0 <= \^err_irq_reg_0\; - ioc_irq_reg_0 <= \^ioc_irq_reg_0\; - p_68_out(24 downto 0) <= \^p_68_out\(24 downto 0); - \p_6_out__1\ <= \^p_6_out__1\; - run_stop_d1_reg <= \^run_stop_d1_reg\; - \s_axis_cmd_tdata_reg[63]\ <= \^s_axis_cmd_tdata_reg[63]\; -\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[24]\: unisim.vcomponents.FDRE +\sig_addr_cntr_im0_msh_reg[0]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \sig_addr_cntr_im0_msh_reg[0]_i_2_n_0\, + CO(2) => \sig_addr_cntr_im0_msh_reg[0]_i_2_n_1\, + CO(1) => \sig_addr_cntr_im0_msh_reg[0]_i_2_n_2\, + CO(0) => \sig_addr_cntr_im0_msh_reg[0]_i_2_n_3\, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => \sig_addr_cntr_im0_msh[0]_i_3_n_0\, + O(3) => \sig_addr_cntr_im0_msh_reg[0]_i_2_n_4\, + O(2) => \sig_addr_cntr_im0_msh_reg[0]_i_2_n_5\, + O(1) => \sig_addr_cntr_im0_msh_reg[0]_i_2_n_6\, + O(0) => \sig_addr_cntr_im0_msh_reg[0]_i_2_n_7\, + S(3) => \sig_addr_cntr_im0_msh[0]_i_4_n_0\, + S(2) => \sig_addr_cntr_im0_msh[0]_i_5_n_0\, + S(1) => \sig_addr_cntr_im0_msh[0]_i_6_n_0\, + S(0) => \sig_addr_cntr_im0_msh[0]_i_7_n_0\ + ); +\sig_addr_cntr_im0_msh_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(17), - Q => \^p_68_out\(17), - R => SR(0) + CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, + D => \sig_addr_cntr_im0_msh_reg[8]_i_1_n_5\, + Q => sig_addr_cntr_im0_msh_reg(10), + R => \^sig_init_reg\ ); -\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[25]\: unisim.vcomponents.FDRE +\sig_addr_cntr_im0_msh_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(18), - Q => \^p_68_out\(18), - R => SR(0) + CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, + D => \sig_addr_cntr_im0_msh_reg[8]_i_1_n_4\, + Q => sig_addr_cntr_im0_msh_reg(11), + R => \^sig_init_reg\ ); -\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[26]\: unisim.vcomponents.FDRE +\sig_addr_cntr_im0_msh_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(19), - Q => \^p_68_out\(19), - R => SR(0) + CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, + D => \sig_addr_cntr_im0_msh_reg[12]_i_1_n_7\, + Q => sig_addr_cntr_im0_msh_reg(12), + R => \^sig_init_reg\ ); -\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[27]\: unisim.vcomponents.FDRE +\sig_addr_cntr_im0_msh_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \sig_addr_cntr_im0_msh_reg[8]_i_1_n_0\, + CO(3) => \NLW_sig_addr_cntr_im0_msh_reg[12]_i_1_CO_UNCONNECTED\(3), + CO(2) => \sig_addr_cntr_im0_msh_reg[12]_i_1_n_1\, + CO(1) => \sig_addr_cntr_im0_msh_reg[12]_i_1_n_2\, + CO(0) => \sig_addr_cntr_im0_msh_reg[12]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \sig_addr_cntr_im0_msh_reg[12]_i_1_n_4\, + O(2) => \sig_addr_cntr_im0_msh_reg[12]_i_1_n_5\, + O(1) => \sig_addr_cntr_im0_msh_reg[12]_i_1_n_6\, + O(0) => \sig_addr_cntr_im0_msh_reg[12]_i_1_n_7\, + S(3) => \sig_addr_cntr_im0_msh[12]_i_2_n_0\, + S(2) => \sig_addr_cntr_im0_msh[12]_i_3_n_0\, + S(1) => \sig_addr_cntr_im0_msh[12]_i_4_n_0\, + S(0) => \sig_addr_cntr_im0_msh[12]_i_5_n_0\ + ); +\sig_addr_cntr_im0_msh_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(20), - Q => \^p_68_out\(20), - R => SR(0) + CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, + D => \sig_addr_cntr_im0_msh_reg[12]_i_1_n_6\, + Q => sig_addr_cntr_im0_msh_reg(13), + R => \^sig_init_reg\ ); -\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[28]\: unisim.vcomponents.FDRE +\sig_addr_cntr_im0_msh_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(21), - Q => \^p_68_out\(21), - R => SR(0) + CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, + D => \sig_addr_cntr_im0_msh_reg[12]_i_1_n_5\, + Q => sig_addr_cntr_im0_msh_reg(14), + R => \^sig_init_reg\ ); -\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[29]\: unisim.vcomponents.FDRE +\sig_addr_cntr_im0_msh_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(22), - Q => \^p_68_out\(22), - R => SR(0) + CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, + D => \sig_addr_cntr_im0_msh_reg[12]_i_1_n_4\, + Q => sig_addr_cntr_im0_msh_reg(15), + R => \^sig_init_reg\ ); -\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[30]\: unisim.vcomponents.FDRE +\sig_addr_cntr_im0_msh_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(23), - Q => \^p_68_out\(23), - R => SR(0) + CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, + D => \sig_addr_cntr_im0_msh_reg[0]_i_2_n_6\, + Q => sig_addr_cntr_im0_msh_reg(1), + R => \^sig_init_reg\ ); -\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31]\: unisim.vcomponents.FDRE +\sig_addr_cntr_im0_msh_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(24), - Q => \^p_68_out\(24), - R => SR(0) - ); -\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFFFFFFFFF6FF6" - ) - port map ( - I0 => D(24), - I1 => \^p_68_out\(24), - I2 => D(23), - I3 => \^p_68_out\(23), - I4 => \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_3_n_0\, - I5 => \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_4_n_0\, - O => different_delay - ); -\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"6FF6FFFFFFFF6FF6" - ) - port map ( - I0 => \^p_68_out\(20), - I1 => D(20), - I2 => D(22), - I3 => \^p_68_out\(22), - I4 => D(21), - I5 => \^p_68_out\(21), - O => \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_3_n_0\ - ); -\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"6FF6FFFFFFFF6FF6" - ) - port map ( - I0 => \^p_68_out\(17), - I1 => D(17), - I2 => D(19), - I3 => \^p_68_out\(19), - I4 => D(18), - I5 => \^p_68_out\(18), - O => \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_4_n_0\ + CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, + D => \sig_addr_cntr_im0_msh_reg[0]_i_2_n_5\, + Q => sig_addr_cntr_im0_msh_reg(2), + R => \^sig_init_reg\ ); -\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg\: unisim.vcomponents.FDRE +\sig_addr_cntr_im0_msh_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7]\, - Q => irqdelay_wren_i, - R => SR(0) + CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, + D => \sig_addr_cntr_im0_msh_reg[0]_i_2_n_4\, + Q => sig_addr_cntr_im0_msh_reg(3), + R => \^sig_init_reg\ ); -\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[16]\: unisim.vcomponents.FDSE +\sig_addr_cntr_im0_msh_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(9), - Q => \^p_68_out\(9), - S => prmry_resetn_i_reg_0(0) + CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, + D => \sig_addr_cntr_im0_msh_reg[4]_i_1_n_7\, + Q => sig_addr_cntr_im0_msh_reg(4), + R => \^sig_init_reg\ ); -\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[17]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(10), - Q => \^p_68_out\(10), - R => prmry_resetn_i_reg_0(0) +\sig_addr_cntr_im0_msh_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \sig_addr_cntr_im0_msh_reg[0]_i_2_n_0\, + CO(3) => \sig_addr_cntr_im0_msh_reg[4]_i_1_n_0\, + CO(2) => \sig_addr_cntr_im0_msh_reg[4]_i_1_n_1\, + CO(1) => \sig_addr_cntr_im0_msh_reg[4]_i_1_n_2\, + CO(0) => \sig_addr_cntr_im0_msh_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \sig_addr_cntr_im0_msh_reg[4]_i_1_n_4\, + O(2) => \sig_addr_cntr_im0_msh_reg[4]_i_1_n_5\, + O(1) => \sig_addr_cntr_im0_msh_reg[4]_i_1_n_6\, + O(0) => \sig_addr_cntr_im0_msh_reg[4]_i_1_n_7\, + S(3) => \sig_addr_cntr_im0_msh[4]_i_2_n_0\, + S(2) => \sig_addr_cntr_im0_msh[4]_i_3_n_0\, + S(1) => \sig_addr_cntr_im0_msh[4]_i_4_n_0\, + S(0) => \sig_addr_cntr_im0_msh[4]_i_5_n_0\ ); -\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[18]\: unisim.vcomponents.FDRE +\sig_addr_cntr_im0_msh_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(11), - Q => \^p_68_out\(11), - R => prmry_resetn_i_reg_0(0) + CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, + D => \sig_addr_cntr_im0_msh_reg[4]_i_1_n_6\, + Q => sig_addr_cntr_im0_msh_reg(5), + R => \^sig_init_reg\ ); -\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[19]\: unisim.vcomponents.FDRE +\sig_addr_cntr_im0_msh_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(12), - Q => \^p_68_out\(12), - R => prmry_resetn_i_reg_0(0) + CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, + D => \sig_addr_cntr_im0_msh_reg[4]_i_1_n_5\, + Q => sig_addr_cntr_im0_msh_reg(6), + R => \^sig_init_reg\ ); -\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[20]\: unisim.vcomponents.FDRE +\sig_addr_cntr_im0_msh_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(13), - Q => \^p_68_out\(13), - R => prmry_resetn_i_reg_0(0) + CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, + D => \sig_addr_cntr_im0_msh_reg[4]_i_1_n_4\, + Q => sig_addr_cntr_im0_msh_reg(7), + R => \^sig_init_reg\ ); -\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]\: unisim.vcomponents.FDRE +\sig_addr_cntr_im0_msh_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(14), - Q => \^p_68_out\(14), - R => prmry_resetn_i_reg_0(0) + CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, + D => \sig_addr_cntr_im0_msh_reg[8]_i_1_n_7\, + Q => sig_addr_cntr_im0_msh_reg(8), + R => \^sig_init_reg\ ); -\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[22]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(15), - Q => \^p_68_out\(15), - R => prmry_resetn_i_reg_0(0) +\sig_addr_cntr_im0_msh_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \sig_addr_cntr_im0_msh_reg[4]_i_1_n_0\, + CO(3) => \sig_addr_cntr_im0_msh_reg[8]_i_1_n_0\, + CO(2) => \sig_addr_cntr_im0_msh_reg[8]_i_1_n_1\, + CO(1) => \sig_addr_cntr_im0_msh_reg[8]_i_1_n_2\, + CO(0) => \sig_addr_cntr_im0_msh_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \sig_addr_cntr_im0_msh_reg[8]_i_1_n_4\, + O(2) => \sig_addr_cntr_im0_msh_reg[8]_i_1_n_5\, + O(1) => \sig_addr_cntr_im0_msh_reg[8]_i_1_n_6\, + O(0) => \sig_addr_cntr_im0_msh_reg[8]_i_1_n_7\, + S(3) => \sig_addr_cntr_im0_msh[8]_i_2_n_0\, + S(2) => \sig_addr_cntr_im0_msh[8]_i_3_n_0\, + S(1) => \sig_addr_cntr_im0_msh[8]_i_4_n_0\, + S(0) => \sig_addr_cntr_im0_msh[8]_i_5_n_0\ ); -\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[23]\: unisim.vcomponents.FDRE +\sig_addr_cntr_im0_msh_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(16), - Q => \^p_68_out\(16), - R => prmry_resetn_i_reg_0(0) + CE => \sig_addr_cntr_im0_msh[0]_i_1_n_0\, + D => \sig_addr_cntr_im0_msh_reg[8]_i_1_n_6\, + Q => sig_addr_cntr_im0_msh_reg(9), + R => \^sig_init_reg\ ); -\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_2\: unisim.vcomponents.LUT6 +\sig_addr_cntr_incr_ireg2[0]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"FFFFFFFFFFFF6FF6" + INIT => X"B888" ) port map ( - I0 => D(16), - I1 => \^p_68_out\(16), - I2 => D(15), - I3 => \^p_68_out\(15), - I4 => \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_3_n_0\, - I5 => \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_4_n_0\, - O => different_thresh + I0 => sig_btt_residue_slice_im0(0), + I1 => sig_btt_lt_b2mbaa_ireg1, + I2 => sig_first_xfer_im0, + I3 => sig_bytes_to_mbaa_ireg1(0), + O => \sig_addr_cntr_incr_ireg2[0]_i_1_n_0\ ); -\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_3\: unisim.vcomponents.LUT6 +\sig_addr_cntr_incr_ireg2[1]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"6FF6FFFFFFFF6FF6" + INIT => X"B888" ) port map ( - I0 => \^p_68_out\(12), - I1 => D(12), - I2 => D(14), - I3 => \^p_68_out\(14), - I4 => D(13), - I5 => \^p_68_out\(13), - O => \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_3_n_0\ + I0 => sig_btt_residue_slice_im0(1), + I1 => sig_btt_lt_b2mbaa_ireg1, + I2 => sig_first_xfer_im0, + I3 => sig_bytes_to_mbaa_ireg1(1), + O => \sig_addr_cntr_incr_ireg2[1]_i_1_n_0\ ); -\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_4\: unisim.vcomponents.LUT6 +\sig_addr_cntr_incr_ireg2[2]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"6FF6FFFFFFFF6FF6" + INIT => X"B888" ) port map ( - I0 => \^p_68_out\(9), - I1 => D(9), - I2 => D(11), - I3 => \^p_68_out\(11), - I4 => D(10), - I5 => \^p_68_out\(10), - O => \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_4_n_0\ + I0 => sig_btt_residue_slice_im0(2), + I1 => sig_btt_lt_b2mbaa_ireg1, + I2 => sig_first_xfer_im0, + I3 => sig_bytes_to_mbaa_ireg1(2), + O => \sig_addr_cntr_incr_ireg2[2]_i_1_n_0\ ); -\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg\: unisim.vcomponents.FDRE +\sig_addr_cntr_incr_ireg2[3]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"B888" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7]_0\, - Q => irqthresh_wren_i, - R => SR(0) + I0 => sig_btt_residue_slice_im0(3), + I1 => sig_btt_lt_b2mbaa_ireg1, + I2 => sig_first_xfer_im0, + I3 => sig_bytes_to_mbaa_ireg1(3), + O => \sig_addr_cntr_incr_ireg2[3]_i_1_n_0\ ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_4\: unisim.vcomponents.LUT6 +\sig_addr_cntr_incr_ireg2[4]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"FFFFFEFFFEFFFEFF" + INIT => X"B888" ) port map ( - I0 => mm2s_halt, - I1 => \^p_68_out\(1), - I2 => dma_err, - I3 => \^run_stop_d1_reg\, - I4 => \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg\, - I5 => p_0_out, - O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ + I0 => sig_btt_residue_slice_im0(4), + I1 => sig_btt_lt_b2mbaa_ireg1, + I2 => sig_first_xfer_im0, + I3 => sig_bytes_to_mbaa_ireg1(4), + O => \sig_addr_cntr_incr_ireg2[4]_i_1_n_0\ ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_1\: unisim.vcomponents.LUT4 +\sig_addr_cntr_incr_ireg2[5]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"FFFD" + INIT => X"B888" ) port map ( - I0 => ch1_delay_cnt_en, - I1 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_3_n_0\, - I2 => \^ch1_disable_delay2_out\, - I3 => p_17_out, - O => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]\(0) + I0 => sig_btt_residue_slice_im0(5), + I1 => sig_btt_lt_b2mbaa_ireg1, + I2 => sig_first_xfer_im0, + I3 => sig_bytes_to_mbaa_ireg1(5), + O => \sig_addr_cntr_incr_ireg2[5]_i_1_n_0\ ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_3\: unisim.vcomponents.LUT4 +\sig_addr_cntr_incr_ireg2[6]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"FEFF" + INIT => X"B888" ) port map ( - I0 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]\, - I1 => irqdelay_wren_i, - I2 => p_23_out, - I3 => prmry_resetn_i_reg, - O => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_3_n_0\ + I0 => sig_btt_residue_slice_im0(6), + I1 => sig_btt_lt_b2mbaa_ireg1, + I2 => sig_first_xfer_im0, + I3 => sig_bytes_to_mbaa_ireg1(6), + O => \sig_addr_cntr_incr_ireg2[6]_i_1_n_0\ ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_4\: unisim.vcomponents.LUT6 +\sig_addr_cntr_incr_ireg2[7]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"FFFFFFFFFFFFFFEF" + INIT => X"B888" ) port map ( - I0 => mm2s_dly_irq_set, - I1 => \^ch1_delay_zero__6\, - I2 => p_46_out, - I3 => mask_fsync_out_i, - I4 => \^s_axis_cmd_tdata_reg[63]\, - I5 => \^dly_irq_reg_0\, - O => \^ch1_disable_delay2_out\ + I0 => sig_btt_residue_slice_im0(7), + I1 => sig_btt_lt_b2mbaa_ireg1, + I2 => sig_first_xfer_im0, + I3 => sig_bytes_to_mbaa_ireg1(7), + O => \sig_addr_cntr_incr_ireg2[7]_i_1_n_0\ ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_1\: unisim.vcomponents.LUT5 +\sig_addr_cntr_incr_ireg2[8]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"FFFFFEFF" + INIT => X"0D" ) port map ( - I0 => p_17_out, - I1 => \^ch1_disable_delay2_out\, - I2 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_3_n_0\, - I3 => ch1_delay_cnt_en, - I4 => p_10_out, - O => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0]\(0) + I0 => sig_first_xfer_im0, + I1 => sig_addr_aligned_ireg1, + I2 => sig_btt_lt_b2mbaa_ireg1, + O => \sig_addr_cntr_incr_ireg2[8]_i_1_n_0\ ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_2\: unisim.vcomponents.LUT5 +\sig_addr_cntr_incr_ireg2_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => X"00000001" + INIT => '0' ) port map ( - I0 => \^p_68_out\(22), - I1 => \^p_68_out\(21), - I2 => \^p_68_out\(23), - I3 => \^p_68_out\(24), - I4 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_4_n_0\, - O => \^ch1_delay_zero__6\ + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc2_reg, + D => \sig_addr_cntr_incr_ireg2[0]_i_1_n_0\, + Q => sig_addr_cntr_incr_ireg2(0), + R => \^sig_init_reg\ ); -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_4\: unisim.vcomponents.LUT4 +\sig_addr_cntr_incr_ireg2_reg[1]\: unisim.vcomponents.FDRE generic map( - INIT => X"FFFE" + INIT => '0' ) port map ( - I0 => \^p_68_out\(19), - I1 => \^p_68_out\(20), - I2 => \^p_68_out\(17), - I3 => \^p_68_out\(18), - O => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_4_n_0\ + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc2_reg, + D => \sig_addr_cntr_incr_ireg2[1]_i_1_n_0\, + Q => sig_addr_cntr_incr_ireg2(1), + R => \^sig_init_reg\ ); -\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[0]_i_1\: unisim.vcomponents.LUT4 +\sig_addr_cntr_incr_ireg2_reg[2]\: unisim.vcomponents.FDRE generic map( - INIT => X"AA8B" + INIT => '0' ) port map ( - I0 => \^p_68_out\(9), - I1 => \ch1_ioc_irq_set_i__0\, - I2 => Q(0), - I3 => \^p_6_out__1\, - O => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0]\(0) + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc2_reg, + D => \sig_addr_cntr_incr_ireg2[2]_i_1_n_0\, + Q => sig_addr_cntr_incr_ireg2(2), + R => \^sig_init_reg\ ); -\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_2\: unisim.vcomponents.LUT5 +\sig_addr_cntr_incr_ireg2_reg[3]\: unisim.vcomponents.FDRE generic map( - INIT => X"FFFFFFF8" + INIT => '0' ) port map ( - I0 => \^p_68_out\(6), - I1 => mm2s_dly_irq_set, - I2 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]\, - I3 => irqthresh_wren_i, - I4 => p_49_out, - O => E(0) + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc2_reg, + D => \sig_addr_cntr_incr_ireg2[3]_i_1_n_0\, + Q => sig_addr_cntr_incr_ireg2(3), + R => \^sig_init_reg\ ); -\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_6\: unisim.vcomponents.LUT6 +\sig_addr_cntr_incr_ireg2_reg[4]\: unisim.vcomponents.FDRE generic map( - INIT => X"FFFFFFF2FFF2FFF2" + INIT => '0' ) port map ( - I0 => p_49_out, - I1 => p_44_out, - I2 => irqthresh_wren_i, - I3 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]\, - I4 => mm2s_dly_irq_set, - I5 => \^p_68_out\(6), - O => \^p_6_out__1\ + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc2_reg, + D => \sig_addr_cntr_incr_ireg2[4]_i_1_n_0\, + Q => sig_addr_cntr_incr_ireg2(4), + R => \^sig_init_reg\ ); -\GEN_NOSYNCEN_BIT.dmacr_i_reg[15]\: unisim.vcomponents.FDRE +\sig_addr_cntr_incr_ireg2_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(8), - Q => \^p_68_out\(8), - R => SR(0) + CE => sig_sm_ld_calc2_reg, + D => \sig_addr_cntr_incr_ireg2[5]_i_1_n_0\, + Q => sig_addr_cntr_incr_ireg2(5), + R => \^sig_init_reg\ ); -\MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_1\: unisim.vcomponents.LUT4 +\sig_addr_cntr_incr_ireg2_reg[6]\: unisim.vcomponents.FDRE generic map( - INIT => X"DFDD" + INIT => '0' ) port map ( - I0 => prmry_resetn_i_reg, - I1 => \^s_axis_cmd_tdata_reg[63]\, - I2 => initial_frame, - I3 => \^p_68_out\(0), - O => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]\(0) + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc2_reg, + D => \sig_addr_cntr_incr_ireg2[6]_i_1_n_0\, + Q => sig_addr_cntr_incr_ireg2(6), + R => \^sig_init_reg\ ); -\MM2S_ERR_FOR_IRQ.frm_store_i[4]_i_1\: unisim.vcomponents.LUT3 +\sig_addr_cntr_incr_ireg2_reg[7]\: unisim.vcomponents.FDRE generic map( - INIT => X"01" + INIT => '0' ) port map ( - I0 => \^err_d1_reg_2\, - I1 => \^err_d1_reg_0\, - I2 => \^err_d1_reg_1\, - O => p_1_in + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc2_reg, + D => \sig_addr_cntr_incr_ireg2[7]_i_1_n_0\, + Q => sig_addr_cntr_incr_ireg2(7), + R => \^sig_init_reg\ ); -\MM2S_ERR_FOR_IRQ.frm_store_i_reg[0]\: unisim.vcomponents.FDRE +\sig_addr_cntr_incr_ireg2_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => p_1_in, - D => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0\(0), - Q => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\(0), - R => SR(0) + CE => sig_sm_ld_calc2_reg, + D => \sig_addr_cntr_incr_ireg2[8]_i_1_n_0\, + Q => sig_addr_cntr_incr_ireg2(8), + R => \^sig_init_reg\ ); -\MM2S_ERR_FOR_IRQ.frm_store_i_reg[1]\: unisim.vcomponents.FDRE +\sig_addr_cntr_lsh_im0[0]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axi_mm2s_aclk, - CE => p_1_in, - D => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0\(1), - Q => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\(1), - R => SR(0) + I0 => \out\(18), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => \sig_predict_addr_lsh_ireg3_reg_n_0_[0]\, + O => p_1_in(0) ); -\MM2S_ERR_FOR_IRQ.frm_store_i_reg[2]\: unisim.vcomponents.FDRE +\sig_addr_cntr_lsh_im0[10]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axi_mm2s_aclk, - CE => p_1_in, - D => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0\(2), - Q => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\(2), - R => SR(0) + I0 => \out\(28), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => \sig_predict_addr_lsh_ireg3_reg_n_0_[10]\, + O => p_1_in(10) ); -\MM2S_ERR_FOR_IRQ.frm_store_i_reg[3]\: unisim.vcomponents.FDRE +\sig_addr_cntr_lsh_im0[11]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axi_mm2s_aclk, - CE => p_1_in, - D => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0\(3), - Q => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\(3), - R => SR(0) + I0 => \out\(29), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => \sig_predict_addr_lsh_ireg3_reg_n_0_[11]\, + O => p_1_in(11) ); -\MM2S_ERR_FOR_IRQ.frm_store_i_reg[4]\: unisim.vcomponents.FDRE +\sig_addr_cntr_lsh_im0[12]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axi_mm2s_aclk, - CE => p_1_in, - D => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0\(4), - Q => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\(4), - R => SR(0) + I0 => \out\(30), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => \sig_predict_addr_lsh_ireg3_reg_n_0_[12]\, + O => p_1_in(12) ); -\M_GEN_DMACR_REGISTER.dmacr_i_reg[12]\: unisim.vcomponents.FDRE +\sig_addr_cntr_lsh_im0[13]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(5), - Q => \^p_68_out\(5), - R => SR(0) + I0 => \out\(31), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => \sig_predict_addr_lsh_ireg3_reg_n_0_[13]\, + O => p_1_in(13) ); -\M_GEN_DMACR_REGISTER.dmacr_i_reg[13]\: unisim.vcomponents.FDRE +\sig_addr_cntr_lsh_im0[14]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(6), - Q => \^p_68_out\(6), - R => SR(0) + I0 => \out\(32), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => \sig_predict_addr_lsh_ireg3_reg_n_0_[14]\, + O => p_1_in(14) ); -\M_GEN_DMACR_REGISTER.dmacr_i_reg[14]\: unisim.vcomponents.FDRE +\sig_addr_cntr_lsh_im0[15]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => '0' + INIT => X"FFFF0004" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(7), - Q => \^p_68_out\(7), - R => SR(0) + I0 => Q(0), + I1 => \^sig_input_reg_empty\, + I2 => \^sig_sm_halt_reg\, + I3 => \^in\(38), + I4 => sig_pop_xfer_reg0_out, + O => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\ ); -\M_GEN_DMACR_REGISTER.dmacr_i_reg[4]\: unisim.vcomponents.FDRE +\sig_addr_cntr_lsh_im0[15]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(2), - Q => \^p_68_out\(2), - R => SR(0) + I0 => \out\(33), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_predict_addr_lsh_ireg3(15), + O => p_1_in(15) ); -\M_GEN_DMACR_REGISTER.dmacr_i_reg[5]\: unisim.vcomponents.FDRE +\sig_addr_cntr_lsh_im0[1]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(3), - Q => \^p_68_out\(3), - R => SR(0) + I0 => \out\(19), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => \sig_predict_addr_lsh_ireg3_reg_n_0_[1]\, + O => p_1_in(1) ); -\M_GEN_DMACR_REGISTER.dmacr_i_reg[6]\: unisim.vcomponents.FDRE +\sig_addr_cntr_lsh_im0[2]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(4), - Q => \^p_68_out\(4), - R => SR(0) + I0 => \out\(20), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => \sig_predict_addr_lsh_ireg3_reg_n_0_[2]\, + O => p_1_in(2) ); -datamover_idle_i_1: unisim.vcomponents.LUT4 +\sig_addr_cntr_lsh_im0[3]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"F5C0" + INIT => X"FFFFFEFF00000200" ) port map ( - I0 => \^run_stop_d1_reg\, - I1 => mm2s_halt_cmplt, - I2 => mm2s_halt, - I3 => datamover_idle, - O => datamover_idle_reg + I0 => \out\(21), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => \sig_predict_addr_lsh_ireg3_reg_n_0_[3]\, + O => p_1_in(3) ); -dly_irq_reg: unisim.vcomponents.FDRE +\sig_addr_cntr_lsh_im0[4]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13]\, - Q => \^dly_irq_reg_0\, - R => SR(0) + I0 => \out\(22), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => \sig_predict_addr_lsh_ireg3_reg_n_0_[4]\, + O => p_1_in(4) ); -dma_decerr_reg: unisim.vcomponents.FDRE +\sig_addr_cntr_lsh_im0[5]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => decerr_i_reg, - Q => \^err_d1_reg_2\, - R => SR(0) + I0 => \out\(23), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => \sig_predict_addr_lsh_ireg3_reg_n_0_[5]\, + O => p_1_in(5) ); -dma_interr_reg: unisim.vcomponents.FDRE +\sig_addr_cntr_lsh_im0[6]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4]\, - Q => \^err_d1_reg_0\, - R => SR(0) + I0 => \out\(24), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => \sig_predict_addr_lsh_ireg3_reg_n_0_[6]\, + O => p_1_in(6) ); -dma_slverr_reg: unisim.vcomponents.FDRE +\sig_addr_cntr_lsh_im0[7]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => slverr_i_reg, - Q => \^err_d1_reg_1\, - R => SR(0) + I0 => \out\(25), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => \sig_predict_addr_lsh_ireg3_reg_n_0_[7]\, + O => p_1_in(7) ); -\dmacr_i[0]_i_1\: unisim.vcomponents.LUT4 +\sig_addr_cntr_lsh_im0[8]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"A808" + INIT => X"FFFFFEFF00000200" ) port map ( - I0 => p_16_in, - I1 => \^run_stop_d1_reg\, - I2 => mm2s_axi2ip_wrce(0), - I3 => D(0), - O => dmacr_i(0) + I0 => \out\(26), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => \sig_predict_addr_lsh_ireg3_reg_n_0_[8]\, + O => p_1_in(8) ); -\dmacr_i[0]_i_2\: unisim.vcomponents.LUT5 +\sig_addr_cntr_lsh_im0[9]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"00000222" + INIT => X"FFFFFEFF00000200" ) port map ( - I0 => prmry_resetn_i_reg, - I1 => p_35_out, - I2 => \^p_68_out\(2), - I3 => mm2s_ioc_irq_set, - I4 => \^p_68_out\(1), - O => p_16_in + I0 => \out\(27), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => \sig_predict_addr_lsh_ireg3_reg_n_0_[9]\, + O => p_1_in(9) ); -\dmacr_i_reg[0]\: unisim.vcomponents.FDRE +\sig_addr_cntr_lsh_im0_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => dmacr_i(0), - Q => \^run_stop_d1_reg\, - R => '0' + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => p_1_in(0), + Q => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, + R => \^sig_init_reg\ ); -\dmacr_i_reg[1]\: unisim.vcomponents.FDSE +\sig_addr_cntr_lsh_im0_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(0), - D => D(1), - Q => \^p_68_out\(0), - S => SR(0) + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => p_1_in(10), + Q => \sig_addr_cntr_lsh_im0_reg_n_0_[10]\, + R => \^sig_init_reg\ ); -\dmacr_i_reg[2]\: unisim.vcomponents.FDRE +\sig_addr_cntr_lsh_im0_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => \dmacr_i_reg[2]_0\, - Q => \^p_68_out\(1), - R => '0' + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => p_1_in(11), + Q => \sig_addr_cntr_lsh_im0_reg_n_0_[11]\, + R => \^sig_init_reg\ ); -err_d1_i_1: unisim.vcomponents.LUT3 +\sig_addr_cntr_lsh_im0_reg[12]\: unisim.vcomponents.FDRE generic map( - INIT => X"FE" + INIT => '0' ) port map ( - I0 => \^err_d1_reg_1\, - I1 => \^err_d1_reg_0\, - I2 => \^err_d1_reg_2\, - O => err + C => m_axi_mm2s_aclk, + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => p_1_in(12), + Q => \sig_addr_cntr_lsh_im0_reg_n_0_[12]\, + R => \^sig_init_reg\ ); -err_d1_reg: unisim.vcomponents.FDRE +\sig_addr_cntr_lsh_im0_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => err, - Q => err_d1, - R => SR(0) + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => p_1_in(13), + Q => \sig_addr_cntr_lsh_im0_reg_n_0_[13]\, + R => \^sig_init_reg\ ); -err_irq_i_1: unisim.vcomponents.LUT5 +\sig_addr_cntr_lsh_im0_reg[14]\: unisim.vcomponents.FDRE generic map( - INIT => X"77F700F0" + INIT => '0' ) port map ( - I0 => D(7), - I1 => mm2s_axi2ip_wrce(1), - I2 => err, - I3 => err_d1, - I4 => \^err_irq_reg_0\, - O => err_irq_i_1_n_0 + C => m_axi_mm2s_aclk, + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => p_1_in(14), + Q => \sig_addr_cntr_lsh_im0_reg_n_0_[14]\, + R => \^sig_init_reg\ ); -err_irq_reg: unisim.vcomponents.FDRE +\sig_addr_cntr_lsh_im0_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => err_irq_i_1_n_0, - Q => \^err_irq_reg_0\, - R => SR(0) + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => p_1_in(15), + Q => p_1_in_0, + R => \^sig_init_reg\ ); -halted_reg: unisim.vcomponents.FDRE +\sig_addr_cntr_lsh_im0_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => halted_clr_reg, - Q => \^s_axis_cmd_tdata_reg[63]\, - R => '0' + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => p_1_in(1), + Q => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, + R => \^sig_init_reg\ ); -introut_i_1: unisim.vcomponents.LUT3 +\sig_addr_cntr_lsh_im0_reg[2]\: unisim.vcomponents.FDRE generic map( - INIT => X"08" + INIT => '0' ) port map ( - I0 => introut01_out, - I1 => prmry_resetn_i_reg, - I2 => \^p_68_out\(1), - O => introut_i_1_n_0 + C => m_axi_mm2s_aclk, + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => p_1_in(2), + Q => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, + R => \^sig_init_reg\ ); -introut_i_2: unisim.vcomponents.LUT6 +\sig_addr_cntr_lsh_im0_reg[3]\: unisim.vcomponents.FDRE generic map( - INIT => X"FFFFF888F888F888" + INIT => '0' ) port map ( - I0 => \^p_68_out\(7), - I1 => \^err_irq_reg_0\, - I2 => \^dly_irq_reg_0\, - I3 => \^p_68_out\(6), - I4 => \^ioc_irq_reg_0\, - I5 => \^p_68_out\(5), - O => introut01_out - ); -introut_reg: unisim.vcomponents.FDRE - port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => introut_i_1_n_0, - Q => p_75_out, - R => '0' + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => p_1_in(3), + Q => \sig_addr_cntr_lsh_im0_reg_n_0_[3]\, + R => \^sig_init_reg\ ); -ioc_irq_reg: unisim.vcomponents.FDRE +\sig_addr_cntr_lsh_im0_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12]\, - Q => \^ioc_irq_reg_0\, - R => SR(0) + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => p_1_in(4), + Q => \sig_addr_cntr_lsh_im0_reg_n_0_[4]\, + R => \^sig_init_reg\ ); -reset_counts_reg: unisim.vcomponents.FDRE +\sig_addr_cntr_lsh_im0_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => reset_counts_reg_0, - Q => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]\, - R => '0' + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => p_1_in(5), + Q => \sig_addr_cntr_lsh_im0_reg_n_0_[5]\, + R => \^sig_init_reg\ ); -\s_axis_cmd_tdata[63]_i_1\: unisim.vcomponents.LUT2 +\sig_addr_cntr_lsh_im0_reg[6]\: unisim.vcomponents.FDRE generic map( - INIT => X"B" + INIT => '0' ) port map ( - I0 => \^s_axis_cmd_tdata_reg[63]\, - I1 => prmry_resetn_i_reg, - O => \s_axis_cmd_tdata_reg[63]_0\(0) + C => m_axi_mm2s_aclk, + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => p_1_in(6), + Q => \sig_addr_cntr_lsh_im0_reg_n_0_[6]\, + R => \^sig_init_reg\ ); -s_soft_reset_i_i_1: unisim.vcomponents.LUT4 +\sig_addr_cntr_lsh_im0_reg[7]\: unisim.vcomponents.FDRE generic map( - INIT => X"A800" + INIT => '0' ) port map ( - I0 => \^p_68_out\(1), - I1 => mm2s_halt_cmplt, - I2 => halt_reset, - I3 => prmry_in, - O => s_soft_reset_i0 + C => m_axi_mm2s_aclk, + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => p_1_in(7), + Q => \sig_addr_cntr_lsh_im0_reg_n_0_[7]\, + R => \^sig_init_reg\ ); -stop_i_1: unisim.vcomponents.LUT2 +\sig_addr_cntr_lsh_im0_reg[8]\: unisim.vcomponents.FDRE generic map( - INIT => X"E" + INIT => '0' ) port map ( - I0 => \^p_68_out\(1), - I1 => dma_err, - O => stop_i + C => m_axi_mm2s_aclk, + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => p_1_in(8), + Q => \sig_addr_cntr_lsh_im0_reg_n_0_[8]\, + R => \^sig_init_reg\ ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_skid_buf is - port ( - \out\ : out STD_LOGIC; - m_axis_mm2s_tvalid : out STD_LOGIC; - m_axis_mm2s_tlast : out STD_LOGIC; - m_axis_mm2s_tuser : out STD_LOGIC_VECTOR ( 0 to 0 ); - s_valid0 : out STD_LOGIC; - fifo_pipe_empty : out STD_LOGIC; - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tlast_d1_reg\ : out STD_LOGIC; - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tvalid_d1_reg\ : out STD_LOGIC; - m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - m_axis_mm2s_aclk : in STD_LOGIC; - m_axis_fifo_ainit_nosync : in STD_LOGIC; - fifo_dout : in STD_LOGIC_VECTOR ( 33 downto 0 ); - m_axis_mm2s_tready : in STD_LOGIC; - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ : in STD_LOGIC; - \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg\ : in STD_LOGIC; - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : in STD_LOGIC; - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\ : in STD_LOGIC; - p_15_out : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_skid_buf : entity is "axi_vdma_skid_buf"; -end Arty_Z7_20_axi_vdma_0_0_axi_vdma_skid_buf; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_skid_buf is - signal \^m_axis_mm2s_tlast\ : STD_LOGIC; - signal sig_data_reg_out_en : STD_LOGIC; - signal sig_data_skid_mux_out : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal sig_data_skid_reg : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal sig_last_skid_mux_out : STD_LOGIC; - signal sig_last_skid_reg : STD_LOGIC; - signal sig_m_valid_dup : STD_LOGIC; - attribute RTL_KEEP : string; - attribute RTL_KEEP of sig_m_valid_dup : signal is "true"; - attribute equivalent_register_removal : string; - attribute equivalent_register_removal of sig_m_valid_dup : signal is "no"; - signal sig_m_valid_dup_i_1_n_0 : STD_LOGIC; - signal sig_m_valid_out : STD_LOGIC; - attribute RTL_KEEP of sig_m_valid_out : signal is "true"; - attribute equivalent_register_removal of sig_m_valid_out : signal is "no"; - signal sig_reset_reg : STD_LOGIC; - signal sig_s_ready_dup : STD_LOGIC; - attribute RTL_KEEP of sig_s_ready_dup : signal is "true"; - attribute equivalent_register_removal of sig_s_ready_dup : signal is "no"; - signal sig_s_ready_dup_i_1_n_0 : STD_LOGIC; - signal sig_s_ready_out : STD_LOGIC; - attribute RTL_KEEP of sig_s_ready_out : signal is "true"; - attribute equivalent_register_removal of sig_s_ready_out : signal is "no"; - signal sig_user_skid_mux_out : STD_LOGIC; - signal sig_user_skid_reg : STD_LOGIC; - attribute KEEP : string; - attribute KEEP of sig_m_valid_dup_reg : label is "yes"; - attribute equivalent_register_removal of sig_m_valid_dup_reg : label is "no"; - attribute KEEP of sig_m_valid_out_reg : label is "yes"; - attribute equivalent_register_removal of sig_m_valid_out_reg : label is "no"; - attribute KEEP of sig_s_ready_dup_reg : label is "yes"; - attribute equivalent_register_removal of sig_s_ready_dup_reg : label is "no"; - attribute KEEP of sig_s_ready_out_reg : label is "yes"; - attribute equivalent_register_removal of sig_s_ready_out_reg : label is "no"; -begin - m_axis_mm2s_tlast <= \^m_axis_mm2s_tlast\; - m_axis_mm2s_tvalid <= sig_m_valid_out; - \out\ <= sig_s_ready_out; -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_1__1\: unisim.vcomponents.LUT2 +\sig_addr_cntr_lsh_im0_reg[9]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg\, - I1 => sig_m_valid_out, - O => fifo_pipe_empty + C => m_axi_mm2s_aclk, + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => p_1_in(9), + Q => \sig_addr_cntr_lsh_im0_reg_n_0_[9]\, + R => \^sig_init_reg\ ); -\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tlast_d1_i_1\: unisim.vcomponents.LUT4 +\sig_addr_cntr_lsh_kh_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => X"0020" + INIT => '0' ) port map ( - I0 => \^m_axis_mm2s_tlast\, - I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\, - I2 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\, - I3 => p_15_out, - O => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tlast_d1_reg\ + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(18), + Q => sig_addr_cntr_lsh_kh(0), + R => \^sig_init_reg\ ); -\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tvalid_d1_i_1\: unisim.vcomponents.LUT4 +\sig_addr_cntr_lsh_kh_reg[10]\: unisim.vcomponents.FDRE generic map( - INIT => X"0020" + INIT => '0' ) port map ( - I0 => sig_m_valid_out, - I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\, - I2 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\, - I3 => p_15_out, - O => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tvalid_d1_reg\ + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(28), + Q => sig_addr_cntr_lsh_kh(10), + R => \^sig_init_reg\ ); -s_valid_i_1: unisim.vcomponents.LUT2 +\sig_addr_cntr_lsh_kh_reg[11]\: unisim.vcomponents.FDRE generic map( - INIT => X"8" + INIT => '0' ) port map ( - I0 => m_axis_mm2s_tready, - I1 => sig_m_valid_out, - O => s_valid0 + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(29), + Q => sig_addr_cntr_lsh_kh(11), + R => \^sig_init_reg\ ); -\sig_data_reg_out[0]_i_1\: unisim.vcomponents.LUT3 +\sig_addr_cntr_lsh_kh_reg[12]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => fifo_dout(0), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(0), - O => sig_data_skid_mux_out(0) + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(30), + Q => sig_addr_cntr_lsh_kh(12), + R => \^sig_init_reg\ ); -\sig_data_reg_out[10]_i_1\: unisim.vcomponents.LUT3 +\sig_addr_cntr_lsh_kh_reg[13]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => fifo_dout(10), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(10), - O => sig_data_skid_mux_out(10) + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(31), + Q => sig_addr_cntr_lsh_kh(13), + R => \^sig_init_reg\ ); -\sig_data_reg_out[11]_i_1\: unisim.vcomponents.LUT3 +\sig_addr_cntr_lsh_kh_reg[14]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => fifo_dout(11), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(11), - O => sig_data_skid_mux_out(11) + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(32), + Q => sig_addr_cntr_lsh_kh(14), + R => \^sig_init_reg\ ); -\sig_data_reg_out[12]_i_1\: unisim.vcomponents.LUT3 +\sig_addr_cntr_lsh_kh_reg[15]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => fifo_dout(12), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(12), - O => sig_data_skid_mux_out(12) + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(33), + Q => sig_addr_cntr_lsh_kh(15), + R => \^sig_init_reg\ ); -\sig_data_reg_out[13]_i_1\: unisim.vcomponents.LUT3 +\sig_addr_cntr_lsh_kh_reg[16]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => fifo_dout(13), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(13), - O => sig_data_skid_mux_out(13) + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(34), + Q => sig_addr_cntr_lsh_kh(16), + R => \^sig_init_reg\ ); -\sig_data_reg_out[14]_i_1\: unisim.vcomponents.LUT3 +\sig_addr_cntr_lsh_kh_reg[17]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => fifo_dout(14), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(14), - O => sig_data_skid_mux_out(14) + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(35), + Q => sig_addr_cntr_lsh_kh(17), + R => \^sig_init_reg\ ); -\sig_data_reg_out[15]_i_1\: unisim.vcomponents.LUT3 +\sig_addr_cntr_lsh_kh_reg[18]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => fifo_dout(15), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(15), - O => sig_data_skid_mux_out(15) + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(36), + Q => sig_addr_cntr_lsh_kh(18), + R => \^sig_init_reg\ ); -\sig_data_reg_out[16]_i_1\: unisim.vcomponents.LUT3 +\sig_addr_cntr_lsh_kh_reg[19]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => fifo_dout(16), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(16), - O => sig_data_skid_mux_out(16) + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(37), + Q => sig_addr_cntr_lsh_kh(19), + R => \^sig_init_reg\ ); -\sig_data_reg_out[17]_i_1\: unisim.vcomponents.LUT3 +\sig_addr_cntr_lsh_kh_reg[1]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => fifo_dout(17), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(17), - O => sig_data_skid_mux_out(17) + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(19), + Q => sig_addr_cntr_lsh_kh(1), + R => \^sig_init_reg\ ); -\sig_data_reg_out[18]_i_1\: unisim.vcomponents.LUT3 +\sig_addr_cntr_lsh_kh_reg[20]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => fifo_dout(18), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(18), - O => sig_data_skid_mux_out(18) + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(38), + Q => sig_addr_cntr_lsh_kh(20), + R => \^sig_init_reg\ ); -\sig_data_reg_out[19]_i_1\: unisim.vcomponents.LUT3 +\sig_addr_cntr_lsh_kh_reg[21]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => fifo_dout(19), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(19), - O => sig_data_skid_mux_out(19) + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(39), + Q => sig_addr_cntr_lsh_kh(21), + R => \^sig_init_reg\ ); -\sig_data_reg_out[1]_i_1\: unisim.vcomponents.LUT3 +\sig_addr_cntr_lsh_kh_reg[22]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => fifo_dout(1), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(1), - O => sig_data_skid_mux_out(1) + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(40), + Q => sig_addr_cntr_lsh_kh(22), + R => \^sig_init_reg\ ); -\sig_data_reg_out[20]_i_1\: unisim.vcomponents.LUT3 +\sig_addr_cntr_lsh_kh_reg[23]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => fifo_dout(20), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(20), - O => sig_data_skid_mux_out(20) + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(41), + Q => sig_addr_cntr_lsh_kh(23), + R => \^sig_init_reg\ ); -\sig_data_reg_out[21]_i_1\: unisim.vcomponents.LUT3 +\sig_addr_cntr_lsh_kh_reg[24]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => fifo_dout(21), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(21), - O => sig_data_skid_mux_out(21) + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(42), + Q => sig_addr_cntr_lsh_kh(24), + R => \^sig_init_reg\ ); -\sig_data_reg_out[22]_i_1\: unisim.vcomponents.LUT3 +\sig_addr_cntr_lsh_kh_reg[25]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => fifo_dout(22), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(22), - O => sig_data_skid_mux_out(22) + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(43), + Q => sig_addr_cntr_lsh_kh(25), + R => \^sig_init_reg\ ); -\sig_data_reg_out[23]_i_1\: unisim.vcomponents.LUT3 +\sig_addr_cntr_lsh_kh_reg[26]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => fifo_dout(23), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(23), - O => sig_data_skid_mux_out(23) + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(44), + Q => sig_addr_cntr_lsh_kh(26), + R => \^sig_init_reg\ ); -\sig_data_reg_out[24]_i_1\: unisim.vcomponents.LUT3 +\sig_addr_cntr_lsh_kh_reg[27]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => fifo_dout(24), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(24), - O => sig_data_skid_mux_out(24) + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(45), + Q => sig_addr_cntr_lsh_kh(27), + R => \^sig_init_reg\ ); -\sig_data_reg_out[25]_i_1\: unisim.vcomponents.LUT3 +\sig_addr_cntr_lsh_kh_reg[28]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => fifo_dout(25), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(25), - O => sig_data_skid_mux_out(25) + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(46), + Q => sig_addr_cntr_lsh_kh(28), + R => \^sig_init_reg\ ); -\sig_data_reg_out[26]_i_1\: unisim.vcomponents.LUT3 +\sig_addr_cntr_lsh_kh_reg[29]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => fifo_dout(26), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(26), - O => sig_data_skid_mux_out(26) + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(47), + Q => sig_addr_cntr_lsh_kh(29), + R => \^sig_init_reg\ ); -\sig_data_reg_out[27]_i_1\: unisim.vcomponents.LUT3 +\sig_addr_cntr_lsh_kh_reg[2]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => fifo_dout(27), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(27), - O => sig_data_skid_mux_out(27) + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(20), + Q => sig_addr_cntr_lsh_kh(2), + R => \^sig_init_reg\ ); -\sig_data_reg_out[28]_i_1\: unisim.vcomponents.LUT3 +\sig_addr_cntr_lsh_kh_reg[30]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => fifo_dout(28), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(28), - O => sig_data_skid_mux_out(28) + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(48), + Q => sig_addr_cntr_lsh_kh(30), + R => \^sig_init_reg\ ); -\sig_data_reg_out[29]_i_1\: unisim.vcomponents.LUT3 +\sig_addr_cntr_lsh_kh_reg[31]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => fifo_dout(29), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(29), - O => sig_data_skid_mux_out(29) + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(49), + Q => sig_addr_cntr_lsh_kh(31), + R => \^sig_init_reg\ ); -\sig_data_reg_out[2]_i_1\: unisim.vcomponents.LUT3 +\sig_addr_cntr_lsh_kh_reg[3]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => fifo_dout(2), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(2), - O => sig_data_skid_mux_out(2) + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(21), + Q => sig_addr_cntr_lsh_kh(3), + R => \^sig_init_reg\ ); -\sig_data_reg_out[30]_i_1\: unisim.vcomponents.LUT3 +\sig_addr_cntr_lsh_kh_reg[4]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => fifo_dout(30), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(30), - O => sig_data_skid_mux_out(30) + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(22), + Q => sig_addr_cntr_lsh_kh(4), + R => \^sig_init_reg\ ); -\sig_data_reg_out[31]_i_2\: unisim.vcomponents.LUT2 +\sig_addr_cntr_lsh_kh_reg[5]\: unisim.vcomponents.FDRE generic map( - INIT => X"B" + INIT => '0' ) port map ( - I0 => m_axis_mm2s_tready, - I1 => sig_m_valid_dup, - O => sig_data_reg_out_en + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(23), + Q => sig_addr_cntr_lsh_kh(5), + R => \^sig_init_reg\ ); -\sig_data_reg_out[31]_i_3\: unisim.vcomponents.LUT3 +\sig_addr_cntr_lsh_kh_reg[6]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => fifo_dout(31), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(31), - O => sig_data_skid_mux_out(31) + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(24), + Q => sig_addr_cntr_lsh_kh(6), + R => \^sig_init_reg\ ); -\sig_data_reg_out[3]_i_1\: unisim.vcomponents.LUT3 +\sig_addr_cntr_lsh_kh_reg[7]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => fifo_dout(3), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(3), - O => sig_data_skid_mux_out(3) + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(25), + Q => sig_addr_cntr_lsh_kh(7), + R => \^sig_init_reg\ ); -\sig_data_reg_out[4]_i_1\: unisim.vcomponents.LUT3 +\sig_addr_cntr_lsh_kh_reg[8]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => fifo_dout(4), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(4), - O => sig_data_skid_mux_out(4) + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(26), + Q => sig_addr_cntr_lsh_kh(8), + R => \^sig_init_reg\ ); -\sig_data_reg_out[5]_i_1\: unisim.vcomponents.LUT3 +\sig_addr_cntr_lsh_kh_reg[9]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => fifo_dout(5), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(5), - O => sig_data_skid_mux_out(5) + C => m_axi_mm2s_aclk, + CE => sig_calc_error_reg0, + D => \out\(27), + Q => sig_addr_cntr_lsh_kh(9), + R => \^sig_init_reg\ ); -\sig_data_reg_out[6]_i_1\: unisim.vcomponents.LUT3 +\sig_adjusted_addr_incr_ireg2[3]_i_2\: unisim.vcomponents.LUT4 generic map( - INIT => X"B8" + INIT => X"B888" ) port map ( - I0 => fifo_dout(6), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(6), - O => sig_data_skid_mux_out(6) + I0 => sig_btt_residue_slice_im0(3), + I1 => sig_btt_lt_b2mbaa_ireg1, + I2 => sig_first_xfer_im0, + I3 => sig_bytes_to_mbaa_ireg1(3), + O => \sig_adjusted_addr_incr_ireg2[3]_i_2_n_0\ ); -\sig_data_reg_out[7]_i_1\: unisim.vcomponents.LUT3 +\sig_adjusted_addr_incr_ireg2[3]_i_3\: unisim.vcomponents.LUT5 generic map( - INIT => X"B8" + INIT => X"07F7F808" ) port map ( - I0 => fifo_dout(7), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(7), - O => sig_data_skid_mux_out(7) + I0 => sig_bytes_to_mbaa_ireg1(2), + I1 => sig_first_xfer_im0, + I2 => sig_btt_lt_b2mbaa_ireg1, + I3 => sig_btt_residue_slice_im0(2), + I4 => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, + O => \sig_adjusted_addr_incr_ireg2[3]_i_3_n_0\ ); -\sig_data_reg_out[8]_i_1\: unisim.vcomponents.LUT3 +\sig_adjusted_addr_incr_ireg2[3]_i_4\: unisim.vcomponents.LUT5 generic map( - INIT => X"B8" + INIT => X"07F7F808" ) port map ( - I0 => fifo_dout(8), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(8), - O => sig_data_skid_mux_out(8) + I0 => sig_bytes_to_mbaa_ireg1(1), + I1 => sig_first_xfer_im0, + I2 => sig_btt_lt_b2mbaa_ireg1, + I3 => sig_btt_residue_slice_im0(1), + I4 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, + O => \sig_adjusted_addr_incr_ireg2[3]_i_4_n_0\ ); -\sig_data_reg_out[9]_i_1\: unisim.vcomponents.LUT3 +\sig_adjusted_addr_incr_ireg2[3]_i_5\: unisim.vcomponents.LUT5 generic map( - INIT => X"B8" + INIT => X"07F7F808" ) port map ( - I0 => fifo_dout(9), - I1 => sig_s_ready_dup, - I2 => sig_data_skid_reg(9), - O => sig_data_skid_mux_out(9) + I0 => sig_bytes_to_mbaa_ireg1(0), + I1 => sig_first_xfer_im0, + I2 => sig_btt_lt_b2mbaa_ireg1, + I3 => sig_btt_residue_slice_im0(0), + I4 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, + O => \sig_adjusted_addr_incr_ireg2[3]_i_5_n_0\ ); -\sig_data_reg_out_reg[0]\: unisim.vcomponents.FDRE +\sig_adjusted_addr_incr_ireg2[7]_i_2\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"B888" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(0), - Q => m_axis_mm2s_tdata(0), - R => m_axis_fifo_ainit_nosync + I0 => sig_btt_residue_slice_im0(7), + I1 => sig_btt_lt_b2mbaa_ireg1, + I2 => sig_first_xfer_im0, + I3 => sig_bytes_to_mbaa_ireg1(7), + O => \sig_adjusted_addr_incr_ireg2[7]_i_2_n_0\ ); -\sig_data_reg_out_reg[10]\: unisim.vcomponents.FDRE +\sig_adjusted_addr_incr_ireg2[7]_i_3\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"B888" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(10), - Q => m_axis_mm2s_tdata(10), - R => m_axis_fifo_ainit_nosync + I0 => sig_btt_residue_slice_im0(6), + I1 => sig_btt_lt_b2mbaa_ireg1, + I2 => sig_first_xfer_im0, + I3 => sig_bytes_to_mbaa_ireg1(6), + O => \sig_adjusted_addr_incr_ireg2[7]_i_3_n_0\ ); -\sig_data_reg_out_reg[11]\: unisim.vcomponents.FDRE +\sig_adjusted_addr_incr_ireg2[7]_i_4\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"B888" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(11), - Q => m_axis_mm2s_tdata(11), - R => m_axis_fifo_ainit_nosync + I0 => sig_btt_residue_slice_im0(5), + I1 => sig_btt_lt_b2mbaa_ireg1, + I2 => sig_first_xfer_im0, + I3 => sig_bytes_to_mbaa_ireg1(5), + O => \sig_adjusted_addr_incr_ireg2[7]_i_4_n_0\ ); -\sig_data_reg_out_reg[12]\: unisim.vcomponents.FDRE +\sig_adjusted_addr_incr_ireg2[7]_i_5\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"B888" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(12), - Q => m_axis_mm2s_tdata(12), - R => m_axis_fifo_ainit_nosync + I0 => sig_btt_residue_slice_im0(4), + I1 => sig_btt_lt_b2mbaa_ireg1, + I2 => sig_first_xfer_im0, + I3 => sig_bytes_to_mbaa_ireg1(4), + O => \sig_adjusted_addr_incr_ireg2[7]_i_5_n_0\ ); -\sig_data_reg_out_reg[13]\: unisim.vcomponents.FDRE +\sig_adjusted_addr_incr_ireg2_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(13), - Q => m_axis_mm2s_tdata(13), - R => m_axis_fifo_ainit_nosync + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc2_reg, + D => sig_adjusted_addr_incr_im1(0), + Q => \sig_adjusted_addr_incr_ireg2_reg_n_0_[0]\, + R => \^sig_init_reg\ ); -\sig_data_reg_out_reg[14]\: unisim.vcomponents.FDRE +\sig_adjusted_addr_incr_ireg2_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(14), - Q => m_axis_mm2s_tdata(14), - R => m_axis_fifo_ainit_nosync + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc2_reg, + D => sig_adjusted_addr_incr_im1(1), + Q => \sig_adjusted_addr_incr_ireg2_reg_n_0_[1]\, + R => \^sig_init_reg\ ); -\sig_data_reg_out_reg[15]\: unisim.vcomponents.FDRE +\sig_adjusted_addr_incr_ireg2_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(15), - Q => m_axis_mm2s_tdata(15), - R => m_axis_fifo_ainit_nosync + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc2_reg, + D => sig_adjusted_addr_incr_im1(2), + Q => \sig_adjusted_addr_incr_ireg2_reg_n_0_[2]\, + R => \^sig_init_reg\ ); -\sig_data_reg_out_reg[16]\: unisim.vcomponents.FDRE +\sig_adjusted_addr_incr_ireg2_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(16), - Q => m_axis_mm2s_tdata(16), - R => m_axis_fifo_ainit_nosync + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc2_reg, + D => sig_adjusted_addr_incr_im1(3), + Q => \sig_adjusted_addr_incr_ireg2_reg_n_0_[3]\, + R => \^sig_init_reg\ ); -\sig_data_reg_out_reg[17]\: unisim.vcomponents.FDRE +\sig_adjusted_addr_incr_ireg2_reg[3]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \sig_adjusted_addr_incr_ireg2_reg[3]_i_1_n_0\, + CO(2) => \sig_adjusted_addr_incr_ireg2_reg[3]_i_1_n_1\, + CO(1) => \sig_adjusted_addr_incr_ireg2_reg[3]_i_1_n_2\, + CO(0) => \sig_adjusted_addr_incr_ireg2_reg[3]_i_1_n_3\, + CYINIT => '0', + DI(3) => '0', + DI(2) => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, + DI(1) => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, + DI(0) => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, + O(3 downto 0) => sig_adjusted_addr_incr_im1(3 downto 0), + S(3) => \sig_adjusted_addr_incr_ireg2[3]_i_2_n_0\, + S(2) => \sig_adjusted_addr_incr_ireg2[3]_i_3_n_0\, + S(1) => \sig_adjusted_addr_incr_ireg2[3]_i_4_n_0\, + S(0) => \sig_adjusted_addr_incr_ireg2[3]_i_5_n_0\ + ); +\sig_adjusted_addr_incr_ireg2_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(17), - Q => m_axis_mm2s_tdata(17), - R => m_axis_fifo_ainit_nosync + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc2_reg, + D => sig_adjusted_addr_incr_im1(4), + Q => \sig_adjusted_addr_incr_ireg2_reg_n_0_[4]\, + R => \^sig_init_reg\ ); -\sig_data_reg_out_reg[18]\: unisim.vcomponents.FDRE +\sig_adjusted_addr_incr_ireg2_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(18), - Q => m_axis_mm2s_tdata(18), - R => m_axis_fifo_ainit_nosync + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc2_reg, + D => sig_adjusted_addr_incr_im1(5), + Q => \sig_adjusted_addr_incr_ireg2_reg_n_0_[5]\, + R => \^sig_init_reg\ ); -\sig_data_reg_out_reg[19]\: unisim.vcomponents.FDRE +\sig_adjusted_addr_incr_ireg2_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(19), - Q => m_axis_mm2s_tdata(19), - R => m_axis_fifo_ainit_nosync + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc2_reg, + D => sig_adjusted_addr_incr_im1(6), + Q => \sig_adjusted_addr_incr_ireg2_reg_n_0_[6]\, + R => \^sig_init_reg\ ); -\sig_data_reg_out_reg[1]\: unisim.vcomponents.FDRE +\sig_adjusted_addr_incr_ireg2_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(1), - Q => m_axis_mm2s_tdata(1), - R => m_axis_fifo_ainit_nosync + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc2_reg, + D => sig_adjusted_addr_incr_im1(7), + Q => \sig_adjusted_addr_incr_ireg2_reg_n_0_[7]\, + R => \^sig_init_reg\ ); -\sig_data_reg_out_reg[20]\: unisim.vcomponents.FDRE +\sig_adjusted_addr_incr_ireg2_reg[7]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \sig_adjusted_addr_incr_ireg2_reg[3]_i_1_n_0\, + CO(3) => \NLW_sig_adjusted_addr_incr_ireg2_reg[7]_i_1_CO_UNCONNECTED\(3), + CO(2) => \sig_adjusted_addr_incr_ireg2_reg[7]_i_1_n_1\, + CO(1) => \sig_adjusted_addr_incr_ireg2_reg[7]_i_1_n_2\, + CO(0) => \sig_adjusted_addr_incr_ireg2_reg[7]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => sig_adjusted_addr_incr_im1(7 downto 4), + S(3) => \sig_adjusted_addr_incr_ireg2[7]_i_2_n_0\, + S(2) => \sig_adjusted_addr_incr_ireg2[7]_i_3_n_0\, + S(1) => \sig_adjusted_addr_incr_ireg2[7]_i_4_n_0\, + S(0) => \sig_adjusted_addr_incr_ireg2[7]_i_5_n_0\ + ); +sig_brst_cnt_eq_one_ireg1_i_1: unisim.vcomponents.LUT5 generic map( - INIT => '0' + INIT => X"00000008" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(20), - Q => m_axis_mm2s_tdata(20), - R => m_axis_fifo_ainit_nosync + I0 => sig_btt_lt_b2mbaa_ireg1_i_2_n_0, + I1 => sel0(0), + I2 => sel0(2), + I3 => sel0(3), + I4 => sel0(1), + O => sig_brst_cnt_eq_one_im0 ); -\sig_data_reg_out_reg[21]\: unisim.vcomponents.FDRE +sig_brst_cnt_eq_one_ireg1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(21), - Q => m_axis_mm2s_tdata(21), - R => m_axis_fifo_ainit_nosync + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc1_reg, + D => sig_brst_cnt_eq_one_im0, + Q => sig_brst_cnt_eq_one_ireg1, + R => \^sig_init_reg\ ); -\sig_data_reg_out_reg[22]\: unisim.vcomponents.FDRE +sig_brst_cnt_eq_zero_ireg1_i_1: unisim.vcomponents.LUT5 generic map( - INIT => '0' + INIT => X"00000002" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(22), - Q => m_axis_mm2s_tdata(22), - R => m_axis_fifo_ainit_nosync + I0 => sig_btt_lt_b2mbaa_ireg1_i_2_n_0, + I1 => sel0(2), + I2 => sel0(3), + I3 => sel0(1), + I4 => sel0(0), + O => sig_brst_cnt_eq_zero_im0 ); -\sig_data_reg_out_reg[23]\: unisim.vcomponents.FDRE +sig_brst_cnt_eq_zero_ireg1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(23), - Q => m_axis_mm2s_tdata(23), - R => m_axis_fifo_ainit_nosync + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc1_reg, + D => sig_brst_cnt_eq_zero_im0, + Q => sig_brst_cnt_eq_zero_ireg1, + R => \^sig_init_reg\ ); -\sig_data_reg_out_reg[24]\: unisim.vcomponents.FDRE +sig_btt_cntr_im00_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => sig_btt_cntr_im00_carry_n_0, + CO(2) => sig_btt_cntr_im00_carry_n_1, + CO(1) => sig_btt_cntr_im00_carry_n_2, + CO(0) => sig_btt_cntr_im00_carry_n_3, + CYINIT => '1', + DI(3 downto 0) => sig_btt_residue_slice_im0(3 downto 0), + O(3 downto 0) => sig_btt_cntr_im00(3 downto 0), + S(3) => sig_btt_cntr_im00_carry_i_1_n_0, + S(2) => sig_btt_cntr_im00_carry_i_2_n_0, + S(1) => sig_btt_cntr_im00_carry_i_3_n_0, + S(0) => sig_btt_cntr_im00_carry_i_4_n_0 + ); +\sig_btt_cntr_im00_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => sig_btt_cntr_im00_carry_n_0, + CO(3) => \sig_btt_cntr_im00_carry__0_n_0\, + CO(2) => \sig_btt_cntr_im00_carry__0_n_1\, + CO(1) => \sig_btt_cntr_im00_carry__0_n_2\, + CO(0) => \sig_btt_cntr_im00_carry__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => sig_btt_residue_slice_im0(7 downto 4), + O(3 downto 0) => sig_btt_cntr_im00(7 downto 4), + S(3) => \sig_btt_cntr_im00_carry__0_i_1_n_0\, + S(2) => \sig_btt_cntr_im00_carry__0_i_2_n_0\, + S(1) => \sig_btt_cntr_im00_carry__0_i_3_n_0\, + S(0) => \sig_btt_cntr_im00_carry__0_i_4_n_0\ + ); +\sig_btt_cntr_im00_carry__0_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"9" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(24), - Q => m_axis_mm2s_tdata(24), - R => m_axis_fifo_ainit_nosync + I0 => sig_btt_residue_slice_im0(7), + I1 => sig_addr_cntr_incr_ireg2(7), + O => \sig_btt_cntr_im00_carry__0_i_1_n_0\ ); -\sig_data_reg_out_reg[25]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im00_carry__0_i_2\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"9" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(25), - Q => m_axis_mm2s_tdata(25), - R => m_axis_fifo_ainit_nosync + I0 => sig_btt_residue_slice_im0(6), + I1 => sig_addr_cntr_incr_ireg2(6), + O => \sig_btt_cntr_im00_carry__0_i_2_n_0\ ); -\sig_data_reg_out_reg[26]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im00_carry__0_i_3\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"9" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(26), - Q => m_axis_mm2s_tdata(26), - R => m_axis_fifo_ainit_nosync + I0 => sig_btt_residue_slice_im0(5), + I1 => sig_addr_cntr_incr_ireg2(5), + O => \sig_btt_cntr_im00_carry__0_i_3_n_0\ ); -\sig_data_reg_out_reg[27]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im00_carry__0_i_4\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"9" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(27), - Q => m_axis_mm2s_tdata(27), - R => m_axis_fifo_ainit_nosync + I0 => sig_btt_residue_slice_im0(4), + I1 => sig_addr_cntr_incr_ireg2(4), + O => \sig_btt_cntr_im00_carry__0_i_4_n_0\ ); -\sig_data_reg_out_reg[28]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im00_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \sig_btt_cntr_im00_carry__0_n_0\, + CO(3) => \sig_btt_cntr_im00_carry__1_n_0\, + CO(2) => \sig_btt_cntr_im00_carry__1_n_1\, + CO(1) => \sig_btt_cntr_im00_carry__1_n_2\, + CO(0) => \sig_btt_cntr_im00_carry__1_n_3\, + CYINIT => '0', + DI(3 downto 0) => sel0(3 downto 0), + O(3 downto 0) => sig_btt_cntr_im00(11 downto 8), + S(3) => \sig_btt_cntr_im00_carry__1_i_1_n_0\, + S(2) => \sig_btt_cntr_im00_carry__1_i_2_n_0\, + S(1) => \sig_btt_cntr_im00_carry__1_i_3_n_0\, + S(0) => \sig_btt_cntr_im00_carry__1_i_4_n_0\ + ); +\sig_btt_cntr_im00_carry__1_i_1\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"1" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(28), - Q => m_axis_mm2s_tdata(28), - R => m_axis_fifo_ainit_nosync + I0 => sel0(3), + O => \sig_btt_cntr_im00_carry__1_i_1_n_0\ ); -\sig_data_reg_out_reg[29]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im00_carry__1_i_2\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"1" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(29), - Q => m_axis_mm2s_tdata(29), - R => m_axis_fifo_ainit_nosync + I0 => sel0(2), + O => \sig_btt_cntr_im00_carry__1_i_2_n_0\ ); -\sig_data_reg_out_reg[2]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im00_carry__1_i_3\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"1" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(2), - Q => m_axis_mm2s_tdata(2), - R => m_axis_fifo_ainit_nosync + I0 => sel0(1), + O => \sig_btt_cntr_im00_carry__1_i_3_n_0\ ); -\sig_data_reg_out_reg[30]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im00_carry__1_i_4\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"9" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(30), - Q => m_axis_mm2s_tdata(30), - R => m_axis_fifo_ainit_nosync + I0 => sel0(0), + I1 => sig_addr_cntr_incr_ireg2(8), + O => \sig_btt_cntr_im00_carry__1_i_4_n_0\ ); -\sig_data_reg_out_reg[31]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im00_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \sig_btt_cntr_im00_carry__1_n_0\, + CO(3) => \NLW_sig_btt_cntr_im00_carry__2_CO_UNCONNECTED\(3), + CO(2) => \sig_btt_cntr_im00_carry__2_n_1\, + CO(1) => \sig_btt_cntr_im00_carry__2_n_2\, + CO(0) => \sig_btt_cntr_im00_carry__2_n_3\, + CYINIT => '0', + DI(3) => '0', + DI(2 downto 0) => sel0(6 downto 4), + O(3 downto 0) => sig_btt_cntr_im00(15 downto 12), + S(3) => \sig_btt_cntr_im00_carry__2_i_1_n_0\, + S(2) => \sig_btt_cntr_im00_carry__2_i_2_n_0\, + S(1) => \sig_btt_cntr_im00_carry__2_i_3_n_0\, + S(0) => \sig_btt_cntr_im00_carry__2_i_4_n_0\ + ); +\sig_btt_cntr_im00_carry__2_i_1\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"1" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(31), - Q => m_axis_mm2s_tdata(31), - R => m_axis_fifo_ainit_nosync + I0 => sel0(7), + O => \sig_btt_cntr_im00_carry__2_i_1_n_0\ ); -\sig_data_reg_out_reg[3]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im00_carry__2_i_2\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"1" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(3), - Q => m_axis_mm2s_tdata(3), - R => m_axis_fifo_ainit_nosync + I0 => sel0(6), + O => \sig_btt_cntr_im00_carry__2_i_2_n_0\ ); -\sig_data_reg_out_reg[4]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im00_carry__2_i_3\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"1" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(4), - Q => m_axis_mm2s_tdata(4), - R => m_axis_fifo_ainit_nosync + I0 => sel0(5), + O => \sig_btt_cntr_im00_carry__2_i_3_n_0\ ); -\sig_data_reg_out_reg[5]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im00_carry__2_i_4\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"1" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(5), - Q => m_axis_mm2s_tdata(5), - R => m_axis_fifo_ainit_nosync + I0 => sel0(4), + O => \sig_btt_cntr_im00_carry__2_i_4_n_0\ ); -\sig_data_reg_out_reg[6]\: unisim.vcomponents.FDRE +sig_btt_cntr_im00_carry_i_1: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"9" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(6), - Q => m_axis_mm2s_tdata(6), - R => m_axis_fifo_ainit_nosync + I0 => sig_btt_residue_slice_im0(3), + I1 => sig_addr_cntr_incr_ireg2(3), + O => sig_btt_cntr_im00_carry_i_1_n_0 ); -\sig_data_reg_out_reg[7]\: unisim.vcomponents.FDRE +sig_btt_cntr_im00_carry_i_2: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"9" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(7), - Q => m_axis_mm2s_tdata(7), - R => m_axis_fifo_ainit_nosync + I0 => sig_btt_residue_slice_im0(2), + I1 => sig_addr_cntr_incr_ireg2(2), + O => sig_btt_cntr_im00_carry_i_2_n_0 ); -\sig_data_reg_out_reg[8]\: unisim.vcomponents.FDRE +sig_btt_cntr_im00_carry_i_3: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"9" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(8), - Q => m_axis_mm2s_tdata(8), - R => m_axis_fifo_ainit_nosync + I0 => sig_btt_residue_slice_im0(1), + I1 => sig_addr_cntr_incr_ireg2(1), + O => sig_btt_cntr_im00_carry_i_3_n_0 ); -\sig_data_reg_out_reg[9]\: unisim.vcomponents.FDRE +sig_btt_cntr_im00_carry_i_4: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"9" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_data_skid_mux_out(9), - Q => m_axis_mm2s_tdata(9), - R => m_axis_fifo_ainit_nosync + I0 => sig_btt_residue_slice_im0(0), + I1 => sig_addr_cntr_incr_ireg2(0), + O => sig_btt_cntr_im00_carry_i_4_n_0 ); -\sig_data_skid_reg_reg[0]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0[0]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(0), - Q => sig_data_skid_reg(0), - R => m_axis_fifo_ainit_nosync + I0 => \out\(0), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_btt_cntr_im00(0), + O => \sig_btt_cntr_im0[0]_i_1_n_0\ ); -\sig_data_skid_reg_reg[10]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0[10]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(10), - Q => sig_data_skid_reg(10), - R => m_axis_fifo_ainit_nosync + I0 => \out\(10), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_btt_cntr_im00(10), + O => \sig_btt_cntr_im0[10]_i_1_n_0\ ); -\sig_data_skid_reg_reg[11]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0[11]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(11), - Q => sig_data_skid_reg(11), - R => m_axis_fifo_ainit_nosync + I0 => \out\(11), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_btt_cntr_im00(11), + O => \sig_btt_cntr_im0[11]_i_1_n_0\ ); -\sig_data_skid_reg_reg[12]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0[12]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(12), - Q => sig_data_skid_reg(12), - R => m_axis_fifo_ainit_nosync + I0 => \out\(12), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_btt_cntr_im00(12), + O => \sig_btt_cntr_im0[12]_i_1_n_0\ ); -\sig_data_skid_reg_reg[13]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0[13]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(13), - Q => sig_data_skid_reg(13), - R => m_axis_fifo_ainit_nosync + I0 => \out\(13), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_btt_cntr_im00(13), + O => \sig_btt_cntr_im0[13]_i_1_n_0\ ); -\sig_data_skid_reg_reg[14]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0[14]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(14), - Q => sig_data_skid_reg(14), - R => m_axis_fifo_ainit_nosync + I0 => \out\(14), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_btt_cntr_im00(14), + O => \sig_btt_cntr_im0[14]_i_1_n_0\ ); -\sig_data_skid_reg_reg[15]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0[15]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(15), - Q => sig_data_skid_reg(15), - R => m_axis_fifo_ainit_nosync + I0 => \out\(15), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_btt_cntr_im00(15), + O => \sig_btt_cntr_im0[15]_i_1_n_0\ ); -\sig_data_skid_reg_reg[16]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0[1]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(16), - Q => sig_data_skid_reg(16), - R => m_axis_fifo_ainit_nosync + I0 => \out\(1), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_btt_cntr_im00(1), + O => \sig_btt_cntr_im0[1]_i_1_n_0\ ); -\sig_data_skid_reg_reg[17]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0[2]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(17), - Q => sig_data_skid_reg(17), - R => m_axis_fifo_ainit_nosync + I0 => \out\(2), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_btt_cntr_im00(2), + O => \sig_btt_cntr_im0[2]_i_1_n_0\ ); -\sig_data_skid_reg_reg[18]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0[3]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(18), - Q => sig_data_skid_reg(18), - R => m_axis_fifo_ainit_nosync + I0 => \out\(3), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_btt_cntr_im00(3), + O => \sig_btt_cntr_im0[3]_i_1_n_0\ ); -\sig_data_skid_reg_reg[19]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0[4]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(19), - Q => sig_data_skid_reg(19), - R => m_axis_fifo_ainit_nosync + I0 => \out\(4), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_btt_cntr_im00(4), + O => \sig_btt_cntr_im0[4]_i_1_n_0\ ); -\sig_data_skid_reg_reg[1]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0[5]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(1), - Q => sig_data_skid_reg(1), - R => m_axis_fifo_ainit_nosync + I0 => \out\(5), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_btt_cntr_im00(5), + O => \sig_btt_cntr_im0[5]_i_1_n_0\ ); -\sig_data_skid_reg_reg[20]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0[6]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(20), - Q => sig_data_skid_reg(20), - R => m_axis_fifo_ainit_nosync + I0 => \out\(6), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_btt_cntr_im00(6), + O => \sig_btt_cntr_im0[6]_i_1_n_0\ ); -\sig_data_skid_reg_reg[21]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0[7]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(21), - Q => sig_data_skid_reg(21), - R => m_axis_fifo_ainit_nosync + I0 => \out\(7), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_btt_cntr_im00(7), + O => \sig_btt_cntr_im0[7]_i_1_n_0\ ); -\sig_data_skid_reg_reg[22]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0[8]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(22), - Q => sig_data_skid_reg(22), - R => m_axis_fifo_ainit_nosync + I0 => \out\(8), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_btt_cntr_im00(8), + O => \sig_btt_cntr_im0[8]_i_1_n_0\ ); -\sig_data_skid_reg_reg[23]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0[9]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFEFF00000200" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(23), - Q => sig_data_skid_reg(23), - R => m_axis_fifo_ainit_nosync + I0 => \out\(9), + I1 => \^in\(38), + I2 => \^sig_sm_halt_reg\, + I3 => \^sig_input_reg_empty\, + I4 => Q(0), + I5 => sig_btt_cntr_im00(9), + O => \sig_btt_cntr_im0[9]_i_1_n_0\ ); -\sig_data_skid_reg_reg[24]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(24), - Q => sig_data_skid_reg(24), - R => m_axis_fifo_ainit_nosync + C => m_axi_mm2s_aclk, + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => \sig_btt_cntr_im0[0]_i_1_n_0\, + Q => sig_btt_residue_slice_im0(0), + R => \^sig_init_reg\ ); -\sig_data_skid_reg_reg[25]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(25), - Q => sig_data_skid_reg(25), - R => m_axis_fifo_ainit_nosync + C => m_axi_mm2s_aclk, + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => \sig_btt_cntr_im0[10]_i_1_n_0\, + Q => sel0(2), + R => \^sig_init_reg\ ); -\sig_data_skid_reg_reg[26]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(26), - Q => sig_data_skid_reg(26), - R => m_axis_fifo_ainit_nosync + C => m_axi_mm2s_aclk, + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => \sig_btt_cntr_im0[11]_i_1_n_0\, + Q => sel0(3), + R => \^sig_init_reg\ ); -\sig_data_skid_reg_reg[27]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(27), - Q => sig_data_skid_reg(27), - R => m_axis_fifo_ainit_nosync + C => m_axi_mm2s_aclk, + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => \sig_btt_cntr_im0[12]_i_1_n_0\, + Q => sel0(4), + R => \^sig_init_reg\ ); -\sig_data_skid_reg_reg[28]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(28), - Q => sig_data_skid_reg(28), - R => m_axis_fifo_ainit_nosync + C => m_axi_mm2s_aclk, + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => \sig_btt_cntr_im0[13]_i_1_n_0\, + Q => sel0(5), + R => \^sig_init_reg\ ); -\sig_data_skid_reg_reg[29]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(29), - Q => sig_data_skid_reg(29), - R => m_axis_fifo_ainit_nosync + C => m_axi_mm2s_aclk, + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => \sig_btt_cntr_im0[14]_i_1_n_0\, + Q => sel0(6), + R => \^sig_init_reg\ ); -\sig_data_skid_reg_reg[2]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(2), - Q => sig_data_skid_reg(2), - R => m_axis_fifo_ainit_nosync + C => m_axi_mm2s_aclk, + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => \sig_btt_cntr_im0[15]_i_1_n_0\, + Q => sel0(7), + R => \^sig_init_reg\ ); -\sig_data_skid_reg_reg[30]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(30), - Q => sig_data_skid_reg(30), - R => m_axis_fifo_ainit_nosync + C => m_axi_mm2s_aclk, + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => \sig_btt_cntr_im0[1]_i_1_n_0\, + Q => sig_btt_residue_slice_im0(1), + R => \^sig_init_reg\ ); -\sig_data_skid_reg_reg[31]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(31), - Q => sig_data_skid_reg(31), - R => m_axis_fifo_ainit_nosync + C => m_axi_mm2s_aclk, + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => \sig_btt_cntr_im0[2]_i_1_n_0\, + Q => sig_btt_residue_slice_im0(2), + R => \^sig_init_reg\ ); -\sig_data_skid_reg_reg[3]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(3), - Q => sig_data_skid_reg(3), - R => m_axis_fifo_ainit_nosync + C => m_axi_mm2s_aclk, + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => \sig_btt_cntr_im0[3]_i_1_n_0\, + Q => sig_btt_residue_slice_im0(3), + R => \^sig_init_reg\ ); -\sig_data_skid_reg_reg[4]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(4), - Q => sig_data_skid_reg(4), - R => m_axis_fifo_ainit_nosync + C => m_axi_mm2s_aclk, + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => \sig_btt_cntr_im0[4]_i_1_n_0\, + Q => sig_btt_residue_slice_im0(4), + R => \^sig_init_reg\ ); -\sig_data_skid_reg_reg[5]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(5), - Q => sig_data_skid_reg(5), - R => m_axis_fifo_ainit_nosync + C => m_axi_mm2s_aclk, + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => \sig_btt_cntr_im0[5]_i_1_n_0\, + Q => sig_btt_residue_slice_im0(5), + R => \^sig_init_reg\ ); -\sig_data_skid_reg_reg[6]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(6), - Q => sig_data_skid_reg(6), - R => m_axis_fifo_ainit_nosync + C => m_axi_mm2s_aclk, + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => \sig_btt_cntr_im0[6]_i_1_n_0\, + Q => sig_btt_residue_slice_im0(6), + R => \^sig_init_reg\ ); -\sig_data_skid_reg_reg[7]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(7), - Q => sig_data_skid_reg(7), - R => m_axis_fifo_ainit_nosync + C => m_axi_mm2s_aclk, + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => \sig_btt_cntr_im0[7]_i_1_n_0\, + Q => sig_btt_residue_slice_im0(7), + R => \^sig_init_reg\ ); -\sig_data_skid_reg_reg[8]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(8), - Q => sig_data_skid_reg(8), - R => m_axis_fifo_ainit_nosync + C => m_axi_mm2s_aclk, + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => \sig_btt_cntr_im0[8]_i_1_n_0\, + Q => sel0(0), + R => \^sig_init_reg\ ); -\sig_data_skid_reg_reg[9]\: unisim.vcomponents.FDRE +\sig_btt_cntr_im0_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(9), - Q => sig_data_skid_reg(9), - R => m_axis_fifo_ainit_nosync + C => m_axi_mm2s_aclk, + CE => \sig_addr_cntr_lsh_im0[15]_i_1_n_0\, + D => \sig_btt_cntr_im0[9]_i_1_n_0\, + Q => sel0(1), + R => \^sig_init_reg\ ); -sig_last_reg_out_i_1: unisim.vcomponents.LUT3 +sig_btt_eq_b2mbaa_im01_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => NLW_sig_btt_eq_b2mbaa_im01_carry_CO_UNCONNECTED(3), + CO(2) => sig_btt_eq_b2mbaa_im01, + CO(1) => sig_btt_eq_b2mbaa_im01_carry_n_2, + CO(0) => sig_btt_eq_b2mbaa_im01_carry_n_3, + CYINIT => '1', + DI(3 downto 0) => B"0000", + O(3 downto 0) => NLW_sig_btt_eq_b2mbaa_im01_carry_O_UNCONNECTED(3 downto 0), + S(3) => '0', + S(2) => sig_btt_eq_b2mbaa_im01_carry_i_1_n_0, + S(1) => sig_btt_eq_b2mbaa_im01_carry_i_2_n_0, + S(0) => sig_btt_eq_b2mbaa_im01_carry_i_3_n_0 + ); +sig_btt_eq_b2mbaa_im01_carry_i_1: unisim.vcomponents.LUT5 generic map( - INIT => X"B8" + INIT => X"28144028" ) port map ( - I0 => fifo_dout(32), - I1 => sig_s_ready_dup, - I2 => sig_last_skid_reg, - O => sig_last_skid_mux_out + I0 => sig_btt_residue_slice_im0(6), + I1 => sig_btt_residue_slice_im0(7), + I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[7]\, + I3 => \sig_bytes_to_mbaa_ireg1[7]_i_2_n_0\, + I4 => \sig_addr_cntr_lsh_im0_reg_n_0_[6]\, + O => sig_btt_eq_b2mbaa_im01_carry_i_1_n_0 ); -sig_last_reg_out_reg: unisim.vcomponents.FDRE +sig_btt_eq_b2mbaa_im01_carry_i_2: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"2222222888888882" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_last_skid_mux_out, - Q => \^m_axis_mm2s_tlast\, - R => m_axis_fifo_ainit_nosync + I0 => sig_btt_eq_b2mbaa_im01_carry_i_4_n_0, + I1 => \sig_addr_cntr_lsh_im0_reg_n_0_[3]\, + I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, + I3 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, + I4 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, + I5 => sig_btt_residue_slice_im0(3), + O => sig_btt_eq_b2mbaa_im01_carry_i_2_n_0 ); -sig_last_skid_reg_reg: unisim.vcomponents.FDRE +sig_btt_eq_b2mbaa_im01_carry_i_3: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"0208041020804001" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(32), - Q => sig_last_skid_reg, - R => m_axis_fifo_ainit_nosync + I0 => sig_btt_residue_slice_im0(0), + I1 => sig_btt_residue_slice_im0(1), + I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, + I3 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, + I4 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, + I5 => sig_btt_residue_slice_im0(2), + O => sig_btt_eq_b2mbaa_im01_carry_i_3_n_0 ); -sig_m_valid_dup_i_1: unisim.vcomponents.LUT6 +sig_btt_eq_b2mbaa_im01_carry_i_4: unisim.vcomponents.LUT5 generic map( - INIT => X"00000000000070FF" + INIT => X"60060960" ) port map ( - I0 => sig_s_ready_dup, - I1 => m_axis_mm2s_tready, - I2 => sig_m_valid_dup, - I3 => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\, - I4 => m_axis_fifo_ainit_nosync, - I5 => sig_reset_reg, - O => sig_m_valid_dup_i_1_n_0 + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[5]\, + I1 => sig_btt_residue_slice_im0(5), + I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[4]\, + I3 => sig_btt_lt_b2mbaa_im01_carry_i_9_n_0, + I4 => sig_btt_residue_slice_im0(4), + O => sig_btt_eq_b2mbaa_im01_carry_i_4_n_0 ); -sig_m_valid_dup_reg: unisim.vcomponents.FDRE +sig_btt_eq_b2mbaa_ireg1_i_1: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"0000000200000000" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => sig_m_valid_dup_i_1_n_0, - Q => sig_m_valid_dup, - R => '0' + I0 => sig_btt_lt_b2mbaa_ireg1_i_2_n_0, + I1 => sel0(2), + I2 => sel0(3), + I3 => sel0(1), + I4 => sel0(0), + I5 => sig_btt_eq_b2mbaa_im01, + O => sig_btt_eq_b2mbaa_im0 ); -sig_m_valid_out_reg: unisim.vcomponents.FDRE +sig_btt_eq_b2mbaa_ireg1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => sig_m_valid_dup_i_1_n_0, - Q => sig_m_valid_out, - R => '0' + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc1_reg, + D => sig_btt_eq_b2mbaa_im0, + Q => sig_btt_eq_b2mbaa_ireg1, + R => \^sig_init_reg\ ); -sig_reset_reg_reg: unisim.vcomponents.FDRE +sig_btt_lt_b2mbaa_im01_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => sig_btt_lt_b2mbaa_im01_carry_n_0, + CO(2) => sig_btt_lt_b2mbaa_im01_carry_n_1, + CO(1) => sig_btt_lt_b2mbaa_im01_carry_n_2, + CO(0) => sig_btt_lt_b2mbaa_im01_carry_n_3, + CYINIT => '0', + DI(3) => sig_btt_lt_b2mbaa_im01_carry_i_1_n_0, + DI(2) => sig_btt_lt_b2mbaa_im01_carry_i_2_n_0, + DI(1) => sig_btt_lt_b2mbaa_im01_carry_i_3_n_0, + DI(0) => sig_btt_lt_b2mbaa_im01_carry_i_4_n_0, + O(3 downto 0) => NLW_sig_btt_lt_b2mbaa_im01_carry_O_UNCONNECTED(3 downto 0), + S(3) => sig_btt_lt_b2mbaa_im01_carry_i_5_n_0, + S(2) => sig_btt_lt_b2mbaa_im01_carry_i_6_n_0, + S(1) => sig_btt_lt_b2mbaa_im01_carry_i_7_n_0, + S(0) => sig_btt_lt_b2mbaa_im01_carry_i_8_n_0 + ); +\sig_btt_lt_b2mbaa_im01_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => sig_btt_lt_b2mbaa_im01_carry_n_0, + CO(3 downto 1) => \NLW_sig_btt_lt_b2mbaa_im01_carry__0_CO_UNCONNECTED\(3 downto 1), + CO(0) => sig_btt_lt_b2mbaa_im01, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => \sig_btt_lt_b2mbaa_im01_carry__0_i_1_n_0\, + O(3 downto 0) => \NLW_sig_btt_lt_b2mbaa_im01_carry__0_O_UNCONNECTED\(3 downto 0), + S(3 downto 1) => B"000", + S(0) => \sig_btt_lt_b2mbaa_im01_carry__0_i_2_n_0\ + ); +\sig_btt_lt_b2mbaa_im01_carry__0_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"04" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => m_axis_fifo_ainit_nosync, - Q => sig_reset_reg, - R => '0' + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[6]\, + I1 => \sig_bytes_to_mbaa_ireg1[7]_i_2_n_0\, + I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[7]\, + O => \sig_btt_lt_b2mbaa_im01_carry__0_i_1_n_0\ ); -sig_s_ready_dup_i_1: unisim.vcomponents.LUT6 +\sig_btt_lt_b2mbaa_im01_carry__0_i_2\: unisim.vcomponents.LUT3 generic map( - INIT => X"00000000FFFFFFA2" + INIT => X"FB" ) port map ( - I0 => sig_s_ready_dup, - I1 => sig_m_valid_dup, - I2 => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\, - I3 => m_axis_mm2s_tready, - I4 => sig_reset_reg, - I5 => m_axis_fifo_ainit_nosync, - O => sig_s_ready_dup_i_1_n_0 + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[6]\, + I1 => \sig_bytes_to_mbaa_ireg1[7]_i_2_n_0\, + I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[7]\, + O => \sig_btt_lt_b2mbaa_im01_carry__0_i_2_n_0\ ); -sig_s_ready_dup_reg: unisim.vcomponents.FDRE +sig_btt_lt_b2mbaa_im01_carry_i_1: unisim.vcomponents.LUT5 generic map( - INIT => '0' + INIT => X"004D41F3" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => sig_s_ready_dup_i_1_n_0, - Q => sig_s_ready_dup, - R => '0' + I0 => sig_btt_residue_slice_im0(6), + I1 => \sig_bytes_to_mbaa_ireg1[7]_i_2_n_0\, + I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[6]\, + I3 => sig_btt_residue_slice_im0(7), + I4 => \sig_addr_cntr_lsh_im0_reg_n_0_[7]\, + O => sig_btt_lt_b2mbaa_im01_carry_i_1_n_0 ); -sig_s_ready_out_reg: unisim.vcomponents.FDRE +sig_btt_lt_b2mbaa_im01_carry_i_2: unisim.vcomponents.LUT5 generic map( - INIT => '0' + INIT => X"004D41F3" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => sig_s_ready_dup_i_1_n_0, - Q => sig_s_ready_out, - R => '0' + I0 => sig_btt_residue_slice_im0(4), + I1 => sig_btt_lt_b2mbaa_im01_carry_i_9_n_0, + I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[4]\, + I3 => sig_btt_residue_slice_im0(5), + I4 => \sig_addr_cntr_lsh_im0_reg_n_0_[5]\, + O => sig_btt_lt_b2mbaa_im01_carry_i_2_n_0 ); -\sig_user_reg_out[0]_i_1\: unisim.vcomponents.LUT3 +sig_btt_lt_b2mbaa_im01_carry_i_3: unisim.vcomponents.LUT6 generic map( - INIT => X"B8" + INIT => X"00015554015557FC" ) port map ( - I0 => fifo_dout(33), - I1 => sig_s_ready_dup, - I2 => sig_user_skid_reg, - O => sig_user_skid_mux_out + I0 => sig_btt_residue_slice_im0(3), + I1 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, + I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, + I3 => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, + I4 => \sig_addr_cntr_lsh_im0_reg_n_0_[3]\, + I5 => sig_btt_residue_slice_im0(2), + O => sig_btt_lt_b2mbaa_im01_carry_i_3_n_0 ); -\sig_user_reg_out_reg[0]\: unisim.vcomponents.FDRE +sig_btt_lt_b2mbaa_im01_carry_i_4: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"1474" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_data_reg_out_en, - D => sig_user_skid_mux_out, - Q => m_axis_mm2s_tuser(0), - R => m_axis_fifo_ainit_nosync + I0 => sig_btt_residue_slice_im0(1), + I1 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, + I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, + I3 => sig_btt_residue_slice_im0(0), + O => sig_btt_lt_b2mbaa_im01_carry_i_4_n_0 ); -\sig_user_skid_reg_reg[0]\: unisim.vcomponents.FDRE +sig_btt_lt_b2mbaa_im01_carry_i_5: unisim.vcomponents.LUT5 generic map( - INIT => '0' + INIT => X"60060960" ) port map ( - C => m_axis_mm2s_aclk, - CE => sig_s_ready_dup, - D => fifo_dout(33), - Q => sig_user_skid_reg, - R => m_axis_fifo_ainit_nosync + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[7]\, + I1 => sig_btt_residue_slice_im0(7), + I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[6]\, + I3 => \sig_bytes_to_mbaa_ireg1[7]_i_2_n_0\, + I4 => sig_btt_residue_slice_im0(6), + O => sig_btt_lt_b2mbaa_im01_carry_i_5_n_0 ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_sm is - port ( - tstvect_fsync_d1 : out STD_LOGIC; - frame_sync_reg : out STD_LOGIC; - s_axis_cmd_tvalid_reg : out STD_LOGIC; - zero_vsize_err : out STD_LOGIC; - zero_hsize_err : out STD_LOGIC; - \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); - \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg_0\ : out STD_LOGIC; - load_new_addr : out STD_LOGIC; - p_37_out : out STD_LOGIC; - \cmnds_queued_reg[7]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 ); - p_10_out : out STD_LOGIC; - DI : out STD_LOGIC_VECTOR ( 0 to 0 ); - S : out STD_LOGIC_VECTOR ( 3 downto 0 ); - \cmnds_queued_reg[7]_1\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); - D : out STD_LOGIC_VECTOR ( 48 downto 0 ); - dma_interr_reg : out STD_LOGIC; - p_0_in : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - p_0_out : in STD_LOGIC; - zero_vsize_err0 : in STD_LOGIC; - zero_hsize_err0 : in STD_LOGIC; - p_23_out : in STD_LOGIC; - O : in STD_LOGIC_VECTOR ( 3 downto 0 ); - \stride_vid_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); - \stride_vid_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); - \stride_vid_reg[15]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); - dmacntrl_ns14_out : in STD_LOGIC; - Q : in STD_LOGIC_VECTOR ( 15 downto 0 ); - s_axis_cmd_tvalid_reg_0 : in STD_LOGIC; - \vsize_vid_reg[12]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); - err_i_reg : in STD_LOGIC; - halt_i_reg : in STD_LOGIC; - p_57_out : in STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\ : in STD_LOGIC; - CO : in STD_LOGIC_VECTOR ( 0 to 0 ); - \out\ : in STD_LOGIC; - p_68_out : in STD_LOGIC_VECTOR ( 1 downto 0 ); - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - mm2s_axi2ip_wrce : in STD_LOGIC_VECTOR ( 0 to 0 ); - interr_i_reg : in STD_LOGIC; - dma_interr_reg_0 : in STD_LOGIC; - \hsize_vid_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); - halt_i_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); - \cmnds_queued_reg[5]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); - p_3_in : in STD_LOGIC; - mm2s_halt : in STD_LOGIC; - dma_err : in STD_LOGIC; - err_i_reg_0 : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_sm : entity is "axi_vdma_sm"; -end Arty_Z7_20_axi_vdma_0_0_axi_vdma_sm; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_sm is - signal \FSM_sequential_dmacntrl_cs[0]_i_1_n_0\ : STD_LOGIC; - signal \FSM_sequential_dmacntrl_cs[0]_i_2_n_0\ : STD_LOGIC; - signal \FSM_sequential_dmacntrl_cs[0]_i_3_n_0\ : STD_LOGIC; - signal \FSM_sequential_dmacntrl_cs[0]_i_4_n_0\ : STD_LOGIC; - signal \FSM_sequential_dmacntrl_cs[1]_i_1_n_0\ : STD_LOGIC; - signal \FSM_sequential_dmacntrl_cs[1]_i_2_n_0\ : STD_LOGIC; - signal \FSM_sequential_dmacntrl_cs[2]_i_1_n_0\ : STD_LOGIC; - signal \FSM_sequential_dmacntrl_cs[2]_i_2_n_0\ : STD_LOGIC; - signal \FSM_sequential_dmacntrl_cs[2]_i_3_n_0\ : STD_LOGIC; - signal \FSM_sequential_dmacntrl_cs[2]_i_4_n_0\ : STD_LOGIC; - signal \FSM_sequential_dmacntrl_cs[2]_i_5_n_0\ : STD_LOGIC; - signal \FSM_sequential_dmacntrl_cs[2]_i_6_n_0\ : STD_LOGIC; - signal \FSM_sequential_dmacntrl_cs[2]_i_7_n_0\ : STD_LOGIC; - signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_5_n_0\ : STD_LOGIC; - signal \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_i_1_n_0\ : STD_LOGIC; - signal \^gen_done_for_snf.gen_for_free_run.xfred_started_reg_0\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data[23]_i_1_n_0\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\ : STD_LOGIC; - signal \^gen_normal_dm_command.cmnd_data_reg[47]_0\ : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[0]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[10]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[11]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[12]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[13]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[14]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[15]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[1]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[23]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[2]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[32]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[33]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[34]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[35]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[36]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[37]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[38]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[39]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[3]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[40]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[41]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[42]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[43]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[44]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[45]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[46]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[47]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[48]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[49]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[4]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[50]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[51]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[52]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[53]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[54]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[55]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[56]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[57]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[58]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[59]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[5]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[60]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[61]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[62]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[63]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[6]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[7]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[8]\ : STD_LOGIC; - signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[9]\ : STD_LOGIC; - signal all_lines_xfred_d1 : STD_LOGIC; - signal \cmnds_queued[0]_i_1_n_0\ : STD_LOGIC; - signal \cmnds_queued[7]_i_2_n_0\ : STD_LOGIC; - signal \^cmnds_queued_reg[7]_0\ : STD_LOGIC_VECTOR ( 5 downto 0 ); - signal \cmnds_queued_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 6 ); - signal \dm_address[0]_i_1_n_0\ : STD_LOGIC; - signal \dm_address[16]_i_2_n_0\ : STD_LOGIC; - signal \dm_address[16]_i_3_n_0\ : STD_LOGIC; - signal \dm_address[16]_i_4_n_0\ : STD_LOGIC; - signal \dm_address[16]_i_5_n_0\ : STD_LOGIC; - signal \dm_address[20]_i_2_n_0\ : STD_LOGIC; - signal \dm_address[20]_i_3_n_0\ : STD_LOGIC; - signal \dm_address[20]_i_4_n_0\ : STD_LOGIC; - signal \dm_address[20]_i_5_n_0\ : STD_LOGIC; - signal \dm_address[24]_i_2_n_0\ : STD_LOGIC; - signal \dm_address[24]_i_3_n_0\ : STD_LOGIC; - signal \dm_address[24]_i_4_n_0\ : STD_LOGIC; - signal \dm_address[24]_i_5_n_0\ : STD_LOGIC; - signal \dm_address[28]_i_2_n_0\ : STD_LOGIC; - signal \dm_address[28]_i_3_n_0\ : STD_LOGIC; - signal \dm_address[28]_i_4_n_0\ : STD_LOGIC; - signal \dm_address[28]_i_5_n_0\ : STD_LOGIC; - signal dm_address_reg : STD_LOGIC_VECTOR ( 31 downto 16 ); - signal \dm_address_reg[16]_i_1_n_0\ : STD_LOGIC; - signal \dm_address_reg[16]_i_1_n_1\ : STD_LOGIC; - signal \dm_address_reg[16]_i_1_n_2\ : STD_LOGIC; - signal \dm_address_reg[16]_i_1_n_3\ : STD_LOGIC; - signal \dm_address_reg[16]_i_1_n_4\ : STD_LOGIC; - signal \dm_address_reg[16]_i_1_n_5\ : STD_LOGIC; - signal \dm_address_reg[16]_i_1_n_6\ : STD_LOGIC; - signal \dm_address_reg[16]_i_1_n_7\ : STD_LOGIC; - signal \dm_address_reg[20]_i_1_n_0\ : STD_LOGIC; - signal \dm_address_reg[20]_i_1_n_1\ : STD_LOGIC; - signal \dm_address_reg[20]_i_1_n_2\ : STD_LOGIC; - signal \dm_address_reg[20]_i_1_n_3\ : STD_LOGIC; - signal \dm_address_reg[20]_i_1_n_4\ : STD_LOGIC; - signal \dm_address_reg[20]_i_1_n_5\ : STD_LOGIC; - signal \dm_address_reg[20]_i_1_n_6\ : STD_LOGIC; - signal \dm_address_reg[20]_i_1_n_7\ : STD_LOGIC; - signal \dm_address_reg[24]_i_1_n_0\ : STD_LOGIC; - signal \dm_address_reg[24]_i_1_n_1\ : STD_LOGIC; - signal \dm_address_reg[24]_i_1_n_2\ : STD_LOGIC; - signal \dm_address_reg[24]_i_1_n_3\ : STD_LOGIC; - signal \dm_address_reg[24]_i_1_n_4\ : STD_LOGIC; - signal \dm_address_reg[24]_i_1_n_5\ : STD_LOGIC; - signal \dm_address_reg[24]_i_1_n_6\ : STD_LOGIC; - signal \dm_address_reg[24]_i_1_n_7\ : STD_LOGIC; - signal \dm_address_reg[28]_i_1_n_1\ : STD_LOGIC; - signal \dm_address_reg[28]_i_1_n_2\ : STD_LOGIC; - signal \dm_address_reg[28]_i_1_n_3\ : STD_LOGIC; - signal \dm_address_reg[28]_i_1_n_4\ : STD_LOGIC; - signal \dm_address_reg[28]_i_1_n_5\ : STD_LOGIC; - signal \dm_address_reg[28]_i_1_n_6\ : STD_LOGIC; - signal \dm_address_reg[28]_i_1_n_7\ : STD_LOGIC; - signal dmacntrl_cs : STD_LOGIC_VECTOR ( 2 downto 0 ); - attribute RTL_KEEP : string; - attribute RTL_KEEP of dmacntrl_cs : signal is "yes"; - signal frame_sync_d3 : STD_LOGIC; - signal \^frame_sync_reg\ : STD_LOGIC; - signal \^load_new_addr\ : STD_LOGIC; - signal \^s_axis_cmd_tvalid_reg\ : STD_LOGIC; - signal sts_idle : STD_LOGIC; - signal \^tstvect_fsync_d1\ : STD_LOGIC; - signal tstvect_fsync_d2 : STD_LOGIC; - signal \vert_count[0]_i_10_n_0\ : STD_LOGIC; - signal \vert_count[0]_i_1_n_0\ : STD_LOGIC; - signal \vert_count[0]_i_3_n_0\ : STD_LOGIC; - signal \vert_count[0]_i_4_n_0\ : STD_LOGIC; - signal \vert_count[0]_i_5_n_0\ : STD_LOGIC; - signal \vert_count[0]_i_6_n_0\ : STD_LOGIC; - signal \vert_count[0]_i_7_n_0\ : STD_LOGIC; - signal \vert_count[0]_i_8_n_0\ : STD_LOGIC; - signal \vert_count[0]_i_9_n_0\ : STD_LOGIC; - signal \vert_count[12]_i_2_n_0\ : STD_LOGIC; - signal \vert_count[4]_i_2_n_0\ : STD_LOGIC; - signal \vert_count[4]_i_3_n_0\ : STD_LOGIC; - signal \vert_count[4]_i_4_n_0\ : STD_LOGIC; - signal \vert_count[4]_i_5_n_0\ : STD_LOGIC; - signal \vert_count[4]_i_6_n_0\ : STD_LOGIC; - signal \vert_count[4]_i_7_n_0\ : STD_LOGIC; - signal \vert_count[4]_i_8_n_0\ : STD_LOGIC; - signal \vert_count[4]_i_9_n_0\ : STD_LOGIC; - signal \vert_count[8]_i_2_n_0\ : STD_LOGIC; - signal \vert_count[8]_i_3_n_0\ : STD_LOGIC; - signal \vert_count[8]_i_4_n_0\ : STD_LOGIC; - signal \vert_count[8]_i_5_n_0\ : STD_LOGIC; - signal \vert_count[8]_i_6_n_0\ : STD_LOGIC; - signal \vert_count[8]_i_7_n_0\ : STD_LOGIC; - signal \vert_count[8]_i_8_n_0\ : STD_LOGIC; - signal \vert_count[8]_i_9_n_0\ : STD_LOGIC; - signal vert_count_reg : STD_LOGIC_VECTOR ( 12 downto 0 ); - signal \vert_count_reg[0]_i_2_n_0\ : STD_LOGIC; - signal \vert_count_reg[0]_i_2_n_1\ : STD_LOGIC; - signal \vert_count_reg[0]_i_2_n_2\ : STD_LOGIC; - signal \vert_count_reg[0]_i_2_n_3\ : STD_LOGIC; - signal \vert_count_reg[0]_i_2_n_4\ : STD_LOGIC; - signal \vert_count_reg[0]_i_2_n_5\ : STD_LOGIC; - signal \vert_count_reg[0]_i_2_n_6\ : STD_LOGIC; - signal \vert_count_reg[0]_i_2_n_7\ : STD_LOGIC; - signal \vert_count_reg[12]_i_1_n_7\ : STD_LOGIC; - signal \vert_count_reg[4]_i_1_n_0\ : STD_LOGIC; - signal \vert_count_reg[4]_i_1_n_1\ : STD_LOGIC; - signal \vert_count_reg[4]_i_1_n_2\ : STD_LOGIC; - signal \vert_count_reg[4]_i_1_n_3\ : STD_LOGIC; - signal \vert_count_reg[4]_i_1_n_4\ : STD_LOGIC; - signal \vert_count_reg[4]_i_1_n_5\ : STD_LOGIC; - signal \vert_count_reg[4]_i_1_n_6\ : STD_LOGIC; - signal \vert_count_reg[4]_i_1_n_7\ : STD_LOGIC; - signal \vert_count_reg[8]_i_1_n_0\ : STD_LOGIC; - signal \vert_count_reg[8]_i_1_n_1\ : STD_LOGIC; - signal \vert_count_reg[8]_i_1_n_2\ : STD_LOGIC; - signal \vert_count_reg[8]_i_1_n_3\ : STD_LOGIC; - signal \vert_count_reg[8]_i_1_n_4\ : STD_LOGIC; - signal \vert_count_reg[8]_i_1_n_5\ : STD_LOGIC; - signal \vert_count_reg[8]_i_1_n_6\ : STD_LOGIC; - signal \vert_count_reg[8]_i_1_n_7\ : STD_LOGIC; - signal write_cmnd_cmb : STD_LOGIC; - signal \^zero_hsize_err\ : STD_LOGIC; - signal \^zero_vsize_err\ : STD_LOGIC; - signal \NLW_dm_address_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); - signal \NLW_vert_count_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal \NLW_vert_count_reg[12]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - attribute KEEP : string; - attribute KEEP of \FSM_sequential_dmacntrl_cs_reg[0]\ : label is "yes"; - attribute KEEP of \FSM_sequential_dmacntrl_cs_reg[1]\ : label is "yes"; - attribute KEEP of \FSM_sequential_dmacntrl_cs_reg[2]\ : label is "yes"; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_5\ : label is "soft_lutpair7"; - attribute SOFT_HLUTNM of \GEN_NORMAL_DM_COMMAND.cmnd_data[23]_i_1\ : label is "soft_lutpair8"; - attribute SOFT_HLUTNM of \cmnds_queued[0]_i_1\ : label is "soft_lutpair7"; - attribute METHODOLOGY_DRC_VIOS : string; - attribute METHODOLOGY_DRC_VIOS of \dm_address_reg[16]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; - attribute METHODOLOGY_DRC_VIOS of \dm_address_reg[20]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; - attribute METHODOLOGY_DRC_VIOS of \dm_address_reg[24]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; - attribute METHODOLOGY_DRC_VIOS of \dm_address_reg[28]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[0]_i_1\ : label is "soft_lutpair9"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[10]_i_1\ : label is "soft_lutpair14"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[11]_i_1\ : label is "soft_lutpair15"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[12]_i_1\ : label is "soft_lutpair15"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[13]_i_1\ : label is "soft_lutpair16"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[14]_i_1\ : label is "soft_lutpair16"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[15]_i_1\ : label is "soft_lutpair17"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[1]_i_1\ : label is "soft_lutpair10"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[23]_i_1\ : label is "soft_lutpair8"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[2]_i_1\ : label is "soft_lutpair10"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[32]_i_1\ : label is "soft_lutpair17"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[33]_i_1\ : label is "soft_lutpair18"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[34]_i_1\ : label is "soft_lutpair9"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[35]_i_1\ : label is "soft_lutpair18"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[36]_i_1\ : label is "soft_lutpair19"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[37]_i_1\ : label is "soft_lutpair20"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[38]_i_1\ : label is "soft_lutpair20"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[39]_i_1\ : label is "soft_lutpair19"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[3]_i_1\ : label is "soft_lutpair11"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[40]_i_1\ : label is "soft_lutpair21"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[41]_i_1\ : label is "soft_lutpair22"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[42]_i_1\ : label is "soft_lutpair22"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[43]_i_1\ : label is "soft_lutpair23"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[44]_i_1\ : label is "soft_lutpair23"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[45]_i_1\ : label is "soft_lutpair24"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[46]_i_1\ : label is "soft_lutpair24"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[47]_i_1\ : label is "soft_lutpair25"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[48]_i_1\ : label is "soft_lutpair25"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[49]_i_1\ : label is "soft_lutpair21"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[4]_i_1\ : label is "soft_lutpair11"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[50]_i_1\ : label is "soft_lutpair26"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[51]_i_1\ : label is "soft_lutpair27"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[52]_i_1\ : label is "soft_lutpair26"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[53]_i_1\ : label is "soft_lutpair27"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[54]_i_1\ : label is "soft_lutpair28"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[55]_i_1\ : label is "soft_lutpair29"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[56]_i_1\ : label is "soft_lutpair29"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[57]_i_1\ : label is "soft_lutpair28"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[58]_i_1\ : label is "soft_lutpair30"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[59]_i_1\ : label is "soft_lutpair30"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[5]_i_1\ : label is "soft_lutpair12"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[60]_i_1\ : label is "soft_lutpair31"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[61]_i_1\ : label is "soft_lutpair31"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[62]_i_1\ : label is "soft_lutpair32"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[63]_i_3\ : label is "soft_lutpair32"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[6]_i_1\ : label is "soft_lutpair12"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[7]_i_1\ : label is "soft_lutpair13"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[8]_i_1\ : label is "soft_lutpair13"; - attribute SOFT_HLUTNM of \s_axis_cmd_tdata[9]_i_1\ : label is "soft_lutpair14"; - attribute METHODOLOGY_DRC_VIOS of \vert_count_reg[0]_i_2\ : label is "{SYNTH-8 {cell *THIS*}}"; - attribute METHODOLOGY_DRC_VIOS of \vert_count_reg[12]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; - attribute METHODOLOGY_DRC_VIOS of \vert_count_reg[4]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; - attribute METHODOLOGY_DRC_VIOS of \vert_count_reg[8]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; -begin - \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg_0\ <= \^gen_done_for_snf.gen_for_free_run.xfred_started_reg_0\; - \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0\(15 downto 0) <= \^gen_normal_dm_command.cmnd_data_reg[47]_0\(15 downto 0); - \cmnds_queued_reg[7]_0\(5 downto 0) <= \^cmnds_queued_reg[7]_0\(5 downto 0); - frame_sync_reg <= \^frame_sync_reg\; - load_new_addr <= \^load_new_addr\; - s_axis_cmd_tvalid_reg <= \^s_axis_cmd_tvalid_reg\; - tstvect_fsync_d1 <= \^tstvect_fsync_d1\; - zero_hsize_err <= \^zero_hsize_err\; - zero_vsize_err <= \^zero_vsize_err\; -\FSM_sequential_dmacntrl_cs[0]_i_1\: unisim.vcomponents.LUT6 +sig_btt_lt_b2mbaa_im01_carry_i_6: unisim.vcomponents.LUT5 generic map( - INIT => X"B888FFFFB8880000" + INIT => X"60060960" ) port map ( - I0 => \FSM_sequential_dmacntrl_cs[0]_i_2_n_0\, - I1 => dmacntrl_cs(0), - I2 => \FSM_sequential_dmacntrl_cs[0]_i_3_n_0\, - I3 => \FSM_sequential_dmacntrl_cs[0]_i_4_n_0\, - I4 => \FSM_sequential_dmacntrl_cs[2]_i_4_n_0\, - I5 => dmacntrl_cs(0), - O => \FSM_sequential_dmacntrl_cs[0]_i_1_n_0\ + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[5]\, + I1 => sig_btt_residue_slice_im0(5), + I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[4]\, + I3 => sig_btt_lt_b2mbaa_im01_carry_i_9_n_0, + I4 => sig_btt_residue_slice_im0(4), + O => sig_btt_lt_b2mbaa_im01_carry_i_6_n_0 ); -\FSM_sequential_dmacntrl_cs[0]_i_2\: unisim.vcomponents.LUT4 +sig_btt_lt_b2mbaa_im01_carry_i_7: unisim.vcomponents.LUT6 generic map( - INIT => X"0062" + INIT => X"0606066060606009" ) port map ( - I0 => dmacntrl_cs(2), - I1 => dmacntrl_cs(1), - I2 => s_axis_cmd_tvalid_reg_0, - I3 => dmacntrl_ns14_out, - O => \FSM_sequential_dmacntrl_cs[0]_i_2_n_0\ + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[3]\, + I1 => sig_btt_residue_slice_im0(3), + I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, + I3 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, + I4 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, + I5 => sig_btt_residue_slice_im0(2), + O => sig_btt_lt_b2mbaa_im01_carry_i_7_n_0 ); -\FSM_sequential_dmacntrl_cs[0]_i_3\: unisim.vcomponents.LUT6 +sig_btt_lt_b2mbaa_im01_carry_i_8: unisim.vcomponents.LUT4 generic map( - INIT => X"00000002FFFFFFFF" + INIT => X"6009" ) port map ( - I0 => p_68_out(0), - I1 => \^frame_sync_reg\, - I2 => mm2s_halt, - I3 => p_68_out(1), - I4 => dma_err, - I5 => dmacntrl_cs(1), - O => \FSM_sequential_dmacntrl_cs[0]_i_3_n_0\ + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, + I1 => sig_btt_residue_slice_im0(1), + I2 => sig_btt_residue_slice_im0(0), + I3 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, + O => sig_btt_lt_b2mbaa_im01_carry_i_8_n_0 ); -\FSM_sequential_dmacntrl_cs[0]_i_4\: unisim.vcomponents.LUT6 +sig_btt_lt_b2mbaa_im01_carry_i_9: unisim.vcomponents.LUT4 generic map( - INIT => X"555555555557555F" + INIT => X"0001" ) port map ( - I0 => dmacntrl_cs(2), - I1 => dmacntrl_cs(1), - I2 => p_3_in, - I3 => \^frame_sync_reg\, - I4 => p_68_out(0), - I5 => \FSM_sequential_dmacntrl_cs[2]_i_5_n_0\, - O => \FSM_sequential_dmacntrl_cs[0]_i_4_n_0\ + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, + I1 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, + I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, + I3 => \sig_addr_cntr_lsh_im0_reg_n_0_[3]\, + O => sig_btt_lt_b2mbaa_im01_carry_i_9_n_0 ); -\FSM_sequential_dmacntrl_cs[1]_i_1\: unisim.vcomponents.LUT3 +sig_btt_lt_b2mbaa_ireg1_i_1: unisim.vcomponents.LUT6 generic map( - INIT => X"B8" + INIT => X"0000000200000000" ) port map ( - I0 => \FSM_sequential_dmacntrl_cs[1]_i_2_n_0\, - I1 => \FSM_sequential_dmacntrl_cs[2]_i_4_n_0\, - I2 => dmacntrl_cs(1), - O => \FSM_sequential_dmacntrl_cs[1]_i_1_n_0\ + I0 => sig_btt_lt_b2mbaa_ireg1_i_2_n_0, + I1 => sel0(2), + I2 => sel0(3), + I3 => sel0(1), + I4 => sel0(0), + I5 => sig_btt_lt_b2mbaa_im01, + O => sig_btt_lt_b2mbaa_im0 ); -\FSM_sequential_dmacntrl_cs[1]_i_2\: unisim.vcomponents.LUT6 +sig_btt_lt_b2mbaa_ireg1_i_2: unisim.vcomponents.LUT4 generic map( - INIT => X"04000A0004555F00" + INIT => X"0001" ) port map ( - I0 => dmacntrl_cs(2), - I1 => s_axis_cmd_tvalid_reg_0, - I2 => dmacntrl_ns14_out, - I3 => dmacntrl_cs(0), - I4 => dmacntrl_cs(1), - I5 => err_i_reg_0, - O => \FSM_sequential_dmacntrl_cs[1]_i_2_n_0\ + I0 => sel0(6), + I1 => sel0(4), + I2 => sel0(7), + I3 => sel0(5), + O => sig_btt_lt_b2mbaa_ireg1_i_2_n_0 ); -\FSM_sequential_dmacntrl_cs[2]_i_1\: unisim.vcomponents.LUT6 +sig_btt_lt_b2mbaa_ireg1_reg: unisim.vcomponents.FDRE generic map( - INIT => X"B888FFFFB8880000" + INIT => '0' ) port map ( - I0 => \FSM_sequential_dmacntrl_cs[2]_i_2_n_0\, - I1 => dmacntrl_cs(0), - I2 => dmacntrl_cs(2), - I3 => \FSM_sequential_dmacntrl_cs[2]_i_3_n_0\, - I4 => \FSM_sequential_dmacntrl_cs[2]_i_4_n_0\, - I5 => dmacntrl_cs(2), - O => \FSM_sequential_dmacntrl_cs[2]_i_1_n_0\ + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc1_reg, + D => sig_btt_lt_b2mbaa_im0, + Q => sig_btt_lt_b2mbaa_ireg1, + R => \^sig_init_reg\ ); -\FSM_sequential_dmacntrl_cs[2]_i_2\: unisim.vcomponents.LUT4 +\sig_byte_change_minus1_im2/i_\: unisim.vcomponents.LUT6 generic map( - INIT => X"0010" + INIT => X"FFFFFFFFFFFFFFFE" ) port map ( - I0 => dmacntrl_cs(2), - I1 => s_axis_cmd_tvalid_reg_0, - I2 => dmacntrl_cs(1), - I3 => dmacntrl_ns14_out, - O => \FSM_sequential_dmacntrl_cs[2]_i_2_n_0\ + I0 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[4]\, + I1 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[2]\, + I2 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[0]\, + I3 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[1]\, + I4 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[3]\, + I5 => \sig_adjusted_addr_incr_ireg2_reg_n_0_[5]\, + O => \sig_byte_change_minus1_im2/i__n_0\ ); -\FSM_sequential_dmacntrl_cs[2]_i_3\: unisim.vcomponents.LUT6 +\sig_bytes_to_mbaa_ireg1[1]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"0000000000000001" + INIT => X"6" ) port map ( - I0 => dmacntrl_cs(1), - I1 => \FSM_sequential_dmacntrl_cs[2]_i_5_n_0\, - I2 => \^frame_sync_reg\, - I3 => mm2s_halt, - I4 => p_68_out(1), - I5 => dma_err, - O => \FSM_sequential_dmacntrl_cs[2]_i_3_n_0\ + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, + I1 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, + O => \sig_bytes_to_mbaa_ireg1[1]_i_1_n_0\ ); -\FSM_sequential_dmacntrl_cs[2]_i_4\: unisim.vcomponents.LUT4 +\sig_bytes_to_mbaa_ireg1[2]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"5F5E" + INIT => X"1E" ) port map ( - I0 => dmacntrl_cs(1), - I1 => dmacntrl_cs(0), - I2 => dmacntrl_cs(2), - I3 => err_i_reg, - O => \FSM_sequential_dmacntrl_cs[2]_i_4_n_0\ + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, + I1 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, + I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, + O => \sig_bytes_to_mbaa_ireg1[2]_i_1_n_0\ ); -\FSM_sequential_dmacntrl_cs[2]_i_5\: unisim.vcomponents.LUT6 +\sig_bytes_to_mbaa_ireg1[3]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"0000000000000001" + INIT => X"01FE" ) port map ( - I0 => \FSM_sequential_dmacntrl_cs[2]_i_6_n_0\, - I1 => \FSM_sequential_dmacntrl_cs[2]_i_7_n_0\, - I2 => vert_count_reg(6), - I3 => vert_count_reg(7), - I4 => vert_count_reg(4), - I5 => vert_count_reg(5), - O => \FSM_sequential_dmacntrl_cs[2]_i_5_n_0\ + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, + I1 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, + I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, + I3 => \sig_addr_cntr_lsh_im0_reg_n_0_[3]\, + O => \sig_bytes_to_mbaa_ireg1[3]_i_1_n_0\ ); -\FSM_sequential_dmacntrl_cs[2]_i_6\: unisim.vcomponents.LUT5 +\sig_bytes_to_mbaa_ireg1[4]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"FFFFFFFE" + INIT => X"0001FFFE" ) port map ( - I0 => vert_count_reg(11), - I1 => vert_count_reg(9), - I2 => vert_count_reg(8), - I3 => vert_count_reg(12), - I4 => vert_count_reg(10), - O => \FSM_sequential_dmacntrl_cs[2]_i_6_n_0\ + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, + I1 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, + I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, + I3 => \sig_addr_cntr_lsh_im0_reg_n_0_[3]\, + I4 => \sig_addr_cntr_lsh_im0_reg_n_0_[4]\, + O => \sig_bytes_to_mbaa_ireg1[4]_i_1_n_0\ ); -\FSM_sequential_dmacntrl_cs[2]_i_7\: unisim.vcomponents.LUT4 +\sig_bytes_to_mbaa_ireg1[5]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFE" + INIT => X"00000001FFFFFFFE" ) port map ( - I0 => vert_count_reg(2), - I1 => vert_count_reg(3), - I2 => vert_count_reg(0), - I3 => vert_count_reg(1), - O => \FSM_sequential_dmacntrl_cs[2]_i_7_n_0\ - ); -\FSM_sequential_dmacntrl_cs_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \FSM_sequential_dmacntrl_cs[0]_i_1_n_0\, - Q => dmacntrl_cs(0), - R => p_0_in - ); -\FSM_sequential_dmacntrl_cs_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \FSM_sequential_dmacntrl_cs[1]_i_1_n_0\, - Q => dmacntrl_cs(1), - R => p_0_in - ); -\FSM_sequential_dmacntrl_cs_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \FSM_sequential_dmacntrl_cs[2]_i_1_n_0\, - Q => dmacntrl_cs(2), - R => p_0_in + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[3]\, + I1 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, + I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, + I3 => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, + I4 => \sig_addr_cntr_lsh_im0_reg_n_0_[4]\, + I5 => \sig_addr_cntr_lsh_im0_reg_n_0_[5]\, + O => \sig_bytes_to_mbaa_ireg1[5]_i_1_n_0\ ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_1\: unisim.vcomponents.LUT5 +\sig_bytes_to_mbaa_ireg1[6]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"00000002" + INIT => X"9" ) port map ( - I0 => sts_idle, - I1 => dmacntrl_cs(1), - I2 => err_i_reg, - I3 => dmacntrl_cs(2), - I4 => dmacntrl_cs(0), - O => p_37_out + I0 => \sig_bytes_to_mbaa_ireg1[7]_i_2_n_0\, + I1 => \sig_addr_cntr_lsh_im0_reg_n_0_[6]\, + O => \sig_bytes_to_mbaa_ireg1[6]_i_1_n_0\ ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_2\: unisim.vcomponents.LUT6 +\sig_bytes_to_mbaa_ireg1[7]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"0000000000000002" + INIT => X"2D" ) port map ( - I0 => halt_i_reg, - I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_5_n_0\, - I2 => \cmnds_queued_reg__0\(6), - I3 => \cmnds_queued_reg__0\(7), - I4 => \^cmnds_queued_reg[7]_0\(4), - I5 => \^cmnds_queued_reg[7]_0\(5), - O => sts_idle + I0 => \sig_bytes_to_mbaa_ireg1[7]_i_2_n_0\, + I1 => \sig_addr_cntr_lsh_im0_reg_n_0_[6]\, + I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[7]\, + O => \sig_bytes_to_mbaa_ireg1[7]_i_1_n_0\ ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_5\: unisim.vcomponents.LUT4 +\sig_bytes_to_mbaa_ireg1[7]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFE" + INIT => X"0000000000000001" ) port map ( - I0 => \^cmnds_queued_reg[7]_0\(2), - I1 => \^cmnds_queued_reg[7]_0\(3), - I2 => \^cmnds_queued_reg[7]_0\(0), - I3 => \^cmnds_queued_reg[7]_0\(1), - O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_5_n_0\ + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[4]\, + I1 => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, + I2 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, + I3 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, + I4 => \sig_addr_cntr_lsh_im0_reg_n_0_[3]\, + I5 => \sig_addr_cntr_lsh_im0_reg_n_0_[5]\, + O => \sig_bytes_to_mbaa_ireg1[7]_i_2_n_0\ ); -\GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.all_lines_xfred_d1_reg\: unisim.vcomponents.FDRE +\sig_bytes_to_mbaa_ireg1_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => p_0_out, - Q => all_lines_xfred_d1, - R => p_0_in + CE => sig_sm_ld_calc1_reg, + D => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, + Q => sig_bytes_to_mbaa_ireg1(0), + R => \^sig_init_reg\ ); -\GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_i_1\: unisim.vcomponents.LUT6 +\sig_bytes_to_mbaa_ireg1_reg[1]\: unisim.vcomponents.FDRE generic map( - INIT => X"00AEFFFFFFFFFFFF" + INIT => '0' ) port map ( - I0 => \^gen_done_for_snf.gen_for_free_run.xfred_started_reg_0\, - I1 => all_lines_xfred_d1, - I2 => p_0_out, - I3 => p_23_out, - I4 => p_68_out(0), - I5 => \out\, - O => \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_i_1_n_0\ + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc1_reg, + D => \sig_bytes_to_mbaa_ireg1[1]_i_1_n_0\, + Q => sig_bytes_to_mbaa_ireg1(1), + R => \^sig_init_reg\ ); -\GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg\: unisim.vcomponents.FDRE +\sig_bytes_to_mbaa_ireg1_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_i_1_n_0\, - Q => \^gen_done_for_snf.gen_for_free_run.xfred_started_reg_0\, - R => '0' + CE => sig_sm_ld_calc1_reg, + D => \sig_bytes_to_mbaa_ireg1[2]_i_1_n_0\, + Q => sig_bytes_to_mbaa_ireg1(2), + R => \^sig_init_reg\ ); -\GEN_NORMAL_DM_COMMAND.cmnd_data[23]_i_1\: unisim.vcomponents.LUT3 +\sig_bytes_to_mbaa_ireg1_reg[3]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => \out\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - I2 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[23]\, - O => \GEN_NORMAL_DM_COMMAND.cmnd_data[23]_i_1_n_0\ + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc1_reg, + D => \sig_bytes_to_mbaa_ireg1[3]_i_1_n_0\, + Q => sig_bytes_to_mbaa_ireg1(3), + R => \^sig_init_reg\ ); -\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1\: unisim.vcomponents.LUT2 +\sig_bytes_to_mbaa_ireg1_reg[4]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - I1 => \out\, - O => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc1_reg, + D => \sig_bytes_to_mbaa_ireg1[4]_i_1_n_0\, + Q => sig_bytes_to_mbaa_ireg1(4), + R => \^sig_init_reg\ ); -\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2\: unisim.vcomponents.LUT6 +\sig_bytes_to_mbaa_ireg1_reg[5]\: unisim.vcomponents.FDRE generic map( - INIT => X"00000008FFFFFFFF" + INIT => '0' ) port map ( - I0 => dmacntrl_cs(1), - I1 => dmacntrl_cs(0), - I2 => dmacntrl_cs(2), - I3 => dmacntrl_ns14_out, - I4 => s_axis_cmd_tvalid_reg_0, - I5 => \out\, - O => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\ - ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[0]\: unisim.vcomponents.FDRE - port map ( C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \hsize_vid_reg[15]\(0), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[0]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + CE => sig_sm_ld_calc1_reg, + D => \sig_bytes_to_mbaa_ireg1[5]_i_1_n_0\, + Q => sig_bytes_to_mbaa_ireg1(5), + R => \^sig_init_reg\ ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[10]\: unisim.vcomponents.FDRE - port map ( +\sig_bytes_to_mbaa_ireg1_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \hsize_vid_reg[15]\(10), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[10]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + CE => sig_sm_ld_calc1_reg, + D => \sig_bytes_to_mbaa_ireg1[6]_i_1_n_0\, + Q => sig_bytes_to_mbaa_ireg1(6), + R => \^sig_init_reg\ ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[11]\: unisim.vcomponents.FDRE - port map ( +\sig_bytes_to_mbaa_ireg1_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \hsize_vid_reg[15]\(11), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[11]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + CE => sig_sm_ld_calc1_reg, + D => \sig_bytes_to_mbaa_ireg1[7]_i_1_n_0\, + Q => sig_bytes_to_mbaa_ireg1(7), + R => \^sig_init_reg\ ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[12]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \hsize_vid_reg[15]\(12), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[12]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ +sig_calc_error_pushed_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF80" + ) + port map ( + I0 => \^in\(38), + I1 => sig_ld_xfer_reg, + I2 => sig_xfer_reg_empty, + I3 => \^sig_calc_error_pushed\, + O => sig_calc_error_pushed_i_1_n_0 ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[13]\: unisim.vcomponents.FDRE - port map ( +sig_calc_error_pushed_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \hsize_vid_reg[15]\(13), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[13]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + CE => '1', + D => sig_calc_error_pushed_i_1_n_0, + Q => \^sig_calc_error_pushed\, + R => \^sig_init_reg\ ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[14]\: unisim.vcomponents.FDRE - port map ( +sig_calc_error_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \hsize_vid_reg[15]\(14), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[14]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + CE => '1', + D => sig_calc_error_reg_reg_0, + Q => \^in\(38), + R => \^sig_init_reg\ ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \hsize_vid_reg[15]\(15), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[15]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ +sig_cmd2addr_valid_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000000AAAE" + ) + port map ( + I0 => \^sig_mstr2addr_cmd_valid\, + I1 => sig_pcc_sm_state(2), + I2 => sig_pcc_sm_state(0), + I3 => sig_pcc_sm_state(1), + I4 => sig_wr_fifo_1, + I5 => \^sig_init_reg\, + O => sig_cmd2addr_valid_i_1_n_0 ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[1]\: unisim.vcomponents.FDRE - port map ( +sig_cmd2addr_valid_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \hsize_vid_reg[15]\(1), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[1]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + CE => '1', + D => sig_cmd2addr_valid_i_1_n_0, + Q => \^sig_mstr2addr_cmd_valid\, + R => '0' ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[23]\: unisim.vcomponents.FDRE - port map ( +sig_cmd2data_valid_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000000AAAE" + ) + port map ( + I0 => \^sig_mstr2data_cmd_valid\, + I1 => sig_pcc_sm_state(2), + I2 => sig_pcc_sm_state(0), + I3 => sig_pcc_sm_state(1), + I4 => sig_wr_fifo_0, + I5 => \^sig_init_reg\, + O => sig_cmd2data_valid_i_1_n_0 + ); +sig_cmd2data_valid_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( C => m_axi_mm2s_aclk, CE => '1', - D => \GEN_NORMAL_DM_COMMAND.cmnd_data[23]_i_1_n_0\, - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[23]\, + D => sig_cmd2data_valid_i_1_n_0, + Q => \^sig_mstr2data_cmd_valid\, R => '0' ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \hsize_vid_reg[15]\(2), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[2]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ +sig_cmd2dre_valid_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000F0FF8888" + ) + port map ( + I0 => sig_first_xfer_im0, + I1 => sig_sm_ld_xfer_reg_ns, + I2 => FIFO_Full_reg_0, + I3 => sig_inhibit_rdy_n, + I4 => \^sig_mstr2sf_cmd_valid\, + I5 => \^sig_init_reg\, + O => sig_cmd2dre_valid_i_1_n_0 ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[32]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(0), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[32]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ +sig_cmd2dre_valid_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"02" + ) + port map ( + I0 => sig_pcc_sm_state(2), + I1 => sig_pcc_sm_state(0), + I2 => sig_pcc_sm_state(1), + O => sig_sm_ld_xfer_reg_ns ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[33]\: unisim.vcomponents.FDRE - port map ( +sig_cmd2dre_valid_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(1), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[33]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + CE => '1', + D => sig_cmd2dre_valid_i_1_n_0, + Q => \^sig_mstr2sf_cmd_valid\, + R => '0' ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[34]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(2), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[34]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ +sig_first_xfer_im0_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"000E" + ) + port map ( + I0 => sig_first_xfer_im0, + I1 => sig_calc_error_reg0, + I2 => sig_pop_xfer_reg0_out, + I3 => \^sig_init_reg\, + O => sig_first_xfer_im0_i_1_n_0 ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[35]\: unisim.vcomponents.FDRE - port map ( +sig_first_xfer_im0_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(3), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[35]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + CE => '1', + D => sig_first_xfer_im0_i_1_n_0, + Q => sig_first_xfer_im0, + R => '0' ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[36]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(4), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[36]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ +sig_input_burst_type_reg_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => \^sig_calc_error_pushed\, + I1 => sig_sm_pop_input_reg, + I2 => \^sig_init_reg\, + O => sig_input_cache_type_reg0 ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[37]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(5), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[37]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ +sig_input_burst_type_reg_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"0010" + ) + port map ( + I0 => \^in\(38), + I1 => \^sig_sm_halt_reg\, + I2 => \^sig_input_reg_empty\, + I3 => Q(0), + O => sig_calc_error_reg0 ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[38]\: unisim.vcomponents.FDRE - port map ( +sig_input_burst_type_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(6), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[38]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + CE => sig_calc_error_reg0, + D => \out\(16), + Q => \^in\(37), + R => sig_input_cache_type_reg0 ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[39]\: unisim.vcomponents.FDRE - port map ( +sig_input_eof_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(7), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[39]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + CE => sig_calc_error_reg0, + D => \out\(17), + Q => sig_mstr2sf_eof, + R => sig_input_cache_type_reg0 ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \hsize_vid_reg[15]\(3), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[3]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ +sig_input_reg_empty_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFF2" + ) + port map ( + I0 => \^sig_input_reg_empty\, + I1 => sig_calc_error_reg0, + I2 => \^sig_init_reg\, + I3 => sig_sm_pop_input_reg, + I4 => \^sig_calc_error_pushed\, + O => sig_input_reg_empty_i_1_n_0 ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[40]\: unisim.vcomponents.FDRE - port map ( +sig_input_reg_empty_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(8), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[40]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + CE => '1', + D => sig_input_reg_empty_i_1_n_0, + Q => \^sig_input_reg_empty\, + R => '0' ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[41]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(9), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[41]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ +sig_ld_xfer_reg_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000FF0202" + ) + port map ( + I0 => sig_pcc_sm_state(2), + I1 => sig_pcc_sm_state(0), + I2 => sig_pcc_sm_state(1), + I3 => sig_xfer_reg_empty, + I4 => sig_ld_xfer_reg, + I5 => \^sig_init_reg\, + O => sig_ld_xfer_reg_i_1_n_0 ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[42]\: unisim.vcomponents.FDRE - port map ( +sig_ld_xfer_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(10), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[42]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + CE => '1', + D => sig_ld_xfer_reg_i_1_n_0, + Q => sig_ld_xfer_reg, + R => '0' ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[43]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(11), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[43]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ +sig_ld_xfer_reg_tmp_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000000AAAE" + ) + port map ( + I0 => sig_ld_xfer_reg_tmp, + I1 => sig_pcc_sm_state(2), + I2 => sig_pcc_sm_state(0), + I3 => sig_pcc_sm_state(1), + I4 => sig_pop_xfer_reg0_out, + I5 => \^sig_init_reg\, + O => sig_ld_xfer_reg_tmp_i_1_n_0 ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[44]\: unisim.vcomponents.FDRE - port map ( +sig_ld_xfer_reg_tmp_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(12), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[44]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + CE => '1', + D => sig_ld_xfer_reg_tmp_i_1_n_0, + Q => sig_ld_xfer_reg_tmp, + R => '0' ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[45]\: unisim.vcomponents.FDRE - port map ( +sig_mmap_reset_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(13), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[45]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + CE => '1', + D => SR(0), + Q => \^sig_init_reg\, + R => '0' ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[46]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(14), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[46]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ +sig_no_btt_residue_ireg1_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000001" + ) + port map ( + I0 => sig_btt_residue_slice_im0(1), + I1 => sig_btt_residue_slice_im0(4), + I2 => sig_btt_residue_slice_im0(2), + I3 => sig_btt_residue_slice_im0(5), + I4 => sig_no_btt_residue_ireg1_i_2_n_0, + O => sig_no_btt_residue_im0 ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(15), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[47]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ +sig_no_btt_residue_ireg1_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => sig_btt_residue_slice_im0(3), + I1 => sig_btt_residue_slice_im0(0), + I2 => sig_btt_residue_slice_im0(7), + I3 => sig_btt_residue_slice_im0(6), + O => sig_no_btt_residue_ireg1_i_2_n_0 ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[48]\: unisim.vcomponents.FDRE - port map ( +sig_no_btt_residue_ireg1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => dm_address_reg(16), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[48]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + CE => sig_sm_ld_calc1_reg, + D => sig_no_btt_residue_im0, + Q => sig_no_btt_residue_ireg1, + R => \^sig_init_reg\ ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[49]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => dm_address_reg(17), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[49]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ - ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \hsize_vid_reg[15]\(4), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[4]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ - ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[50]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => dm_address_reg(18), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[50]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ - ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[51]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => dm_address_reg(19), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[51]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ - ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[52]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => dm_address_reg(20), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[52]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ - ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[53]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => dm_address_reg(21), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[53]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ - ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[54]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => dm_address_reg(22), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[54]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ - ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[55]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => dm_address_reg(23), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[55]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ - ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[56]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => dm_address_reg(24), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[56]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ - ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[57]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => dm_address_reg(25), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[57]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ - ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[58]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => dm_address_reg(26), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[58]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ - ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[59]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => dm_address_reg(27), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[59]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ - ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \hsize_vid_reg[15]\(5), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[5]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ - ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[60]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => dm_address_reg(28), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[60]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ - ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[61]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => dm_address_reg(29), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[61]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ - ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[62]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => dm_address_reg(30), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[62]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ - ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[63]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => dm_address_reg(31), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[63]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ - ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \hsize_vid_reg[15]\(6), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[6]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ - ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \hsize_vid_reg[15]\(7), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[7]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ - ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[8]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \hsize_vid_reg[15]\(8), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[8]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ - ); -\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[9]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, - D => \hsize_vid_reg[15]\(9), - Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[9]\, - R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ - ); -\GEN_NORMAL_DM_COMMAND.cmnd_wr_i_i_1\: unisim.vcomponents.LUT5 +sig_parent_done_i_1: unisim.vcomponents.LUT5 generic map( - INIT => X"01000000" + INIT => X"0000002E" ) port map ( - I0 => s_axis_cmd_tvalid_reg_0, - I1 => dmacntrl_ns14_out, - I2 => dmacntrl_cs(2), - I3 => dmacntrl_cs(0), - I4 => dmacntrl_cs(1), - O => write_cmnd_cmb + I0 => sig_parent_done, + I1 => sig_ld_xfer_reg_tmp, + I2 => \^sig_mstr2data_sequential\, + I3 => sig_calc_error_reg0, + I4 => \^sig_init_reg\, + O => sig_parent_done_i_1_n_0 ); -\GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg\: unisim.vcomponents.FDRE +sig_parent_done_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, CE => '1', - D => write_cmnd_cmb, - Q => \^s_axis_cmd_tvalid_reg\, - R => p_0_in + D => sig_parent_done_i_1_n_0, + Q => sig_parent_done, + R => '0' ); -\I_DMA_REGISTER/dma_interr_i_1\: unisim.vcomponents.LUT6 +\sig_predict_addr_lsh_ireg3[11]_i_2\: unisim.vcomponents.LUT1 generic map( - INIT => X"FFFFFFF7FFFFFFF0" + INIT => X"2" ) port map ( - I0 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4]\(0), - I1 => mm2s_axi2ip_wrce(0), - I2 => interr_i_reg, - I3 => \^zero_vsize_err\, - I4 => \^zero_hsize_err\, - I5 => dma_interr_reg_0, - O => dma_interr_reg + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[11]\, + O => \sig_predict_addr_lsh_ireg3[11]_i_2_n_0\ ); -\MASTER_MODE_FRAME_CNT.tstvect_fsync_i_1\: unisim.vcomponents.LUT2 +\sig_predict_addr_lsh_ireg3[11]_i_3\: unisim.vcomponents.LUT1 generic map( - INIT => X"8" + INIT => X"2" ) port map ( - I0 => tstvect_fsync_d2, - I1 => \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\, - O => p_10_out + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[10]\, + O => \sig_predict_addr_lsh_ireg3[11]_i_3_n_0\ ); -\cmnds_queued[0]_i_1\: unisim.vcomponents.LUT1 +\sig_predict_addr_lsh_ireg3[11]_i_4\: unisim.vcomponents.LUT1 generic map( - INIT => X"1" + INIT => X"2" ) port map ( - I0 => \^cmnds_queued_reg[7]_0\(0), - O => \cmnds_queued[0]_i_1_n_0\ + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[9]\, + O => \sig_predict_addr_lsh_ireg3[11]_i_4_n_0\ ); -\cmnds_queued[7]_i_2\: unisim.vcomponents.LUT3 +\sig_predict_addr_lsh_ireg3[11]_i_5\: unisim.vcomponents.LUT2 generic map( - INIT => X"A6" + INIT => X"6" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => p_57_out, - I2 => \INFERRED_GEN.cnt_i_reg[2]\(0), - O => \cmnds_queued[7]_i_2_n_0\ + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[8]\, + I1 => sig_addr_cntr_incr_ireg2(8), + O => \sig_predict_addr_lsh_ireg3[11]_i_5_n_0\ ); -\cmnds_queued_reg[0]\: unisim.vcomponents.FDRE +\sig_predict_addr_lsh_ireg3[15]_i_2\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"2" ) port map ( - C => m_axi_mm2s_aclk, - CE => \cmnds_queued[7]_i_2_n_0\, - D => \cmnds_queued[0]_i_1_n_0\, - Q => \^cmnds_queued_reg[7]_0\(0), - R => halt_i_reg_0(0) + I0 => p_1_in_0, + O => \sig_predict_addr_lsh_ireg3[15]_i_2_n_0\ ); -\cmnds_queued_reg[1]\: unisim.vcomponents.FDRE +\sig_predict_addr_lsh_ireg3[15]_i_3\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"2" ) port map ( - C => m_axi_mm2s_aclk, - CE => \cmnds_queued[7]_i_2_n_0\, - D => \cmnds_queued_reg[5]_0\(0), - Q => \^cmnds_queued_reg[7]_0\(1), - R => halt_i_reg_0(0) + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[14]\, + O => \sig_predict_addr_lsh_ireg3[15]_i_3_n_0\ ); -\cmnds_queued_reg[2]\: unisim.vcomponents.FDRE +\sig_predict_addr_lsh_ireg3[15]_i_4\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"2" ) port map ( - C => m_axi_mm2s_aclk, - CE => \cmnds_queued[7]_i_2_n_0\, - D => \cmnds_queued_reg[5]_0\(1), - Q => \^cmnds_queued_reg[7]_0\(2), - R => halt_i_reg_0(0) + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[13]\, + O => \sig_predict_addr_lsh_ireg3[15]_i_4_n_0\ ); -\cmnds_queued_reg[3]\: unisim.vcomponents.FDRE +\sig_predict_addr_lsh_ireg3[15]_i_5\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"2" ) port map ( - C => m_axi_mm2s_aclk, - CE => \cmnds_queued[7]_i_2_n_0\, - D => \cmnds_queued_reg[5]_0\(2), - Q => \^cmnds_queued_reg[7]_0\(3), - R => halt_i_reg_0(0) + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[12]\, + O => \sig_predict_addr_lsh_ireg3[15]_i_5_n_0\ ); -\cmnds_queued_reg[4]\: unisim.vcomponents.FDRE +\sig_predict_addr_lsh_ireg3[3]_i_2\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"6" ) port map ( - C => m_axi_mm2s_aclk, - CE => \cmnds_queued[7]_i_2_n_0\, - D => \cmnds_queued_reg[5]_0\(3), - Q => \^cmnds_queued_reg[7]_0\(4), - R => halt_i_reg_0(0) + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[3]\, + I1 => sig_addr_cntr_incr_ireg2(3), + O => \sig_predict_addr_lsh_ireg3[3]_i_2_n_0\ ); -\cmnds_queued_reg[5]\: unisim.vcomponents.FDRE +\sig_predict_addr_lsh_ireg3[3]_i_3\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"6" ) port map ( - C => m_axi_mm2s_aclk, - CE => \cmnds_queued[7]_i_2_n_0\, - D => \cmnds_queued_reg[5]_0\(4), - Q => \^cmnds_queued_reg[7]_0\(5), - R => halt_i_reg_0(0) + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, + I1 => sig_addr_cntr_incr_ireg2(2), + O => \sig_predict_addr_lsh_ireg3[3]_i_3_n_0\ ); -\cmnds_queued_reg[6]\: unisim.vcomponents.FDRE +\sig_predict_addr_lsh_ireg3[3]_i_4\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"6" ) port map ( - C => m_axi_mm2s_aclk, - CE => \cmnds_queued[7]_i_2_n_0\, - D => \cmnds_queued_reg[5]_0\(5), - Q => \cmnds_queued_reg__0\(6), - R => halt_i_reg_0(0) + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, + I1 => sig_addr_cntr_incr_ireg2(1), + O => \sig_predict_addr_lsh_ireg3[3]_i_4_n_0\ ); -\cmnds_queued_reg[7]\: unisim.vcomponents.FDRE +\sig_predict_addr_lsh_ireg3[3]_i_5\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"6" ) port map ( - C => m_axi_mm2s_aclk, - CE => \cmnds_queued[7]_i_2_n_0\, - D => \cmnds_queued_reg[5]_0\(6), - Q => \cmnds_queued_reg__0\(7), - R => halt_i_reg_0(0) + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, + I1 => sig_addr_cntr_incr_ireg2(0), + O => \sig_predict_addr_lsh_ireg3[3]_i_5_n_0\ ); -\dm_address[0]_i_1\: unisim.vcomponents.LUT5 +\sig_predict_addr_lsh_ireg3[7]_i_2\: unisim.vcomponents.LUT2 generic map( - INIT => X"AABAAAAA" + INIT => X"6" ) port map ( - I0 => \^load_new_addr\, - I1 => dmacntrl_ns14_out, - I2 => dmacntrl_cs(0), - I3 => dmacntrl_cs(1), - I4 => dmacntrl_cs(2), - O => \dm_address[0]_i_1_n_0\ + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[7]\, + I1 => sig_addr_cntr_incr_ireg2(7), + O => \sig_predict_addr_lsh_ireg3[7]_i_2_n_0\ ); -\dm_address[16]_i_2\: unisim.vcomponents.LUT3 +\sig_predict_addr_lsh_ireg3[7]_i_3\: unisim.vcomponents.LUT2 generic map( - INIT => X"B8" + INIT => X"6" ) port map ( - I0 => Q(3), - I1 => \^load_new_addr\, - I2 => dm_address_reg(19), - O => \dm_address[16]_i_2_n_0\ + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[6]\, + I1 => sig_addr_cntr_incr_ireg2(6), + O => \sig_predict_addr_lsh_ireg3[7]_i_3_n_0\ ); -\dm_address[16]_i_3\: unisim.vcomponents.LUT3 +\sig_predict_addr_lsh_ireg3[7]_i_4\: unisim.vcomponents.LUT2 generic map( - INIT => X"B8" + INIT => X"6" ) port map ( - I0 => Q(2), - I1 => \^load_new_addr\, - I2 => dm_address_reg(18), - O => \dm_address[16]_i_3_n_0\ + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[5]\, + I1 => sig_addr_cntr_incr_ireg2(5), + O => \sig_predict_addr_lsh_ireg3[7]_i_4_n_0\ ); -\dm_address[16]_i_4\: unisim.vcomponents.LUT3 +\sig_predict_addr_lsh_ireg3[7]_i_5\: unisim.vcomponents.LUT2 generic map( - INIT => X"B8" + INIT => X"6" ) port map ( - I0 => Q(1), - I1 => \^load_new_addr\, - I2 => dm_address_reg(17), - O => \dm_address[16]_i_4_n_0\ + I0 => \sig_addr_cntr_lsh_im0_reg_n_0_[4]\, + I1 => sig_addr_cntr_incr_ireg2(4), + O => \sig_predict_addr_lsh_ireg3[7]_i_5_n_0\ ); -\dm_address[16]_i_5\: unisim.vcomponents.LUT3 +\sig_predict_addr_lsh_ireg3_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => Q(0), - I1 => \^load_new_addr\, - I2 => dm_address_reg(16), - O => \dm_address[16]_i_5_n_0\ + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc3_reg, + D => sig_predict_addr_lsh_im2(0), + Q => \sig_predict_addr_lsh_ireg3_reg_n_0_[0]\, + R => \^sig_init_reg\ ); -\dm_address[20]_i_2\: unisim.vcomponents.LUT3 +\sig_predict_addr_lsh_ireg3_reg[10]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => Q(7), - I1 => \^load_new_addr\, - I2 => dm_address_reg(23), - O => \dm_address[20]_i_2_n_0\ + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc3_reg, + D => sig_predict_addr_lsh_im2(10), + Q => \sig_predict_addr_lsh_ireg3_reg_n_0_[10]\, + R => \^sig_init_reg\ ); -\dm_address[20]_i_3\: unisim.vcomponents.LUT3 +\sig_predict_addr_lsh_ireg3_reg[11]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => Q(6), - I1 => \^load_new_addr\, - I2 => dm_address_reg(22), - O => \dm_address[20]_i_3_n_0\ + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc3_reg, + D => sig_predict_addr_lsh_im2(11), + Q => \sig_predict_addr_lsh_ireg3_reg_n_0_[11]\, + R => \^sig_init_reg\ ); -\dm_address[20]_i_4\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => Q(5), - I1 => \^load_new_addr\, - I2 => dm_address_reg(21), - O => \dm_address[20]_i_4_n_0\ +\sig_predict_addr_lsh_ireg3_reg[11]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_0\, + CO(3) => \sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_0\, + CO(2) => \sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_1\, + CO(1) => \sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_2\, + CO(0) => \sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_3\, + CYINIT => '0', + DI(3) => \sig_addr_cntr_lsh_im0_reg_n_0_[11]\, + DI(2) => \sig_addr_cntr_lsh_im0_reg_n_0_[10]\, + DI(1) => \sig_addr_cntr_lsh_im0_reg_n_0_[9]\, + DI(0) => \sig_addr_cntr_lsh_im0_reg_n_0_[8]\, + O(3 downto 0) => sig_predict_addr_lsh_im2(11 downto 8), + S(3) => \sig_predict_addr_lsh_ireg3[11]_i_2_n_0\, + S(2) => \sig_predict_addr_lsh_ireg3[11]_i_3_n_0\, + S(1) => \sig_predict_addr_lsh_ireg3[11]_i_4_n_0\, + S(0) => \sig_predict_addr_lsh_ireg3[11]_i_5_n_0\ ); -\dm_address[20]_i_5\: unisim.vcomponents.LUT3 +\sig_predict_addr_lsh_ireg3_reg[12]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => Q(4), - I1 => \^load_new_addr\, - I2 => dm_address_reg(20), - O => \dm_address[20]_i_5_n_0\ + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc3_reg, + D => sig_predict_addr_lsh_im2(12), + Q => \sig_predict_addr_lsh_ireg3_reg_n_0_[12]\, + R => \^sig_init_reg\ ); -\dm_address[24]_i_2\: unisim.vcomponents.LUT3 +\sig_predict_addr_lsh_ireg3_reg[13]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => Q(11), - I1 => \^load_new_addr\, - I2 => dm_address_reg(27), - O => \dm_address[24]_i_2_n_0\ + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc3_reg, + D => sig_predict_addr_lsh_im2(13), + Q => \sig_predict_addr_lsh_ireg3_reg_n_0_[13]\, + R => \^sig_init_reg\ ); -\dm_address[24]_i_3\: unisim.vcomponents.LUT3 +\sig_predict_addr_lsh_ireg3_reg[14]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => Q(10), - I1 => \^load_new_addr\, - I2 => dm_address_reg(26), - O => \dm_address[24]_i_3_n_0\ + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc3_reg, + D => sig_predict_addr_lsh_im2(14), + Q => \sig_predict_addr_lsh_ireg3_reg_n_0_[14]\, + R => \^sig_init_reg\ ); -\dm_address[24]_i_4\: unisim.vcomponents.LUT3 +\sig_predict_addr_lsh_ireg3_reg[15]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => Q(9), - I1 => \^load_new_addr\, - I2 => dm_address_reg(25), - O => \dm_address[24]_i_4_n_0\ + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc3_reg, + D => sig_predict_addr_lsh_im2(15), + Q => sig_predict_addr_lsh_ireg3(15), + R => \^sig_init_reg\ ); -\dm_address[24]_i_5\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => Q(8), - I1 => \^load_new_addr\, - I2 => dm_address_reg(24), - O => \dm_address[24]_i_5_n_0\ +\sig_predict_addr_lsh_ireg3_reg[15]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \sig_predict_addr_lsh_ireg3_reg[11]_i_1_n_0\, + CO(3) => \NLW_sig_predict_addr_lsh_ireg3_reg[15]_i_1_CO_UNCONNECTED\(3), + CO(2) => \sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_1\, + CO(1) => \sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_2\, + CO(0) => \sig_predict_addr_lsh_ireg3_reg[15]_i_1_n_3\, + CYINIT => '0', + DI(3) => '0', + DI(2) => \sig_addr_cntr_lsh_im0_reg_n_0_[14]\, + DI(1) => \sig_addr_cntr_lsh_im0_reg_n_0_[13]\, + DI(0) => \sig_addr_cntr_lsh_im0_reg_n_0_[12]\, + O(3 downto 0) => sig_predict_addr_lsh_im2(15 downto 12), + S(3) => \sig_predict_addr_lsh_ireg3[15]_i_2_n_0\, + S(2) => \sig_predict_addr_lsh_ireg3[15]_i_3_n_0\, + S(1) => \sig_predict_addr_lsh_ireg3[15]_i_4_n_0\, + S(0) => \sig_predict_addr_lsh_ireg3[15]_i_5_n_0\ ); -\dm_address[28]_i_2\: unisim.vcomponents.LUT3 +\sig_predict_addr_lsh_ireg3_reg[1]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => Q(15), - I1 => \^load_new_addr\, - I2 => dm_address_reg(31), - O => \dm_address[28]_i_2_n_0\ + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc3_reg, + D => sig_predict_addr_lsh_im2(1), + Q => \sig_predict_addr_lsh_ireg3_reg_n_0_[1]\, + R => \^sig_init_reg\ ); -\dm_address[28]_i_3\: unisim.vcomponents.LUT3 +\sig_predict_addr_lsh_ireg3_reg[2]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => Q(14), - I1 => \^load_new_addr\, - I2 => dm_address_reg(30), - O => \dm_address[28]_i_3_n_0\ + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc3_reg, + D => sig_predict_addr_lsh_im2(2), + Q => \sig_predict_addr_lsh_ireg3_reg_n_0_[2]\, + R => \^sig_init_reg\ ); -\dm_address[28]_i_4\: unisim.vcomponents.LUT3 +\sig_predict_addr_lsh_ireg3_reg[3]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => Q(13), - I1 => \^load_new_addr\, - I2 => dm_address_reg(29), - O => \dm_address[28]_i_4_n_0\ + C => m_axi_mm2s_aclk, + CE => sig_sm_ld_calc3_reg, + D => sig_predict_addr_lsh_im2(3), + Q => \sig_predict_addr_lsh_ireg3_reg_n_0_[3]\, + R => \^sig_init_reg\ ); -\dm_address[28]_i_5\: unisim.vcomponents.LUT3 - generic map( - INIT => X"B8" - ) - port map ( - I0 => Q(12), - I1 => \^load_new_addr\, - I2 => dm_address_reg(28), - O => \dm_address[28]_i_5_n_0\ +\sig_predict_addr_lsh_ireg3_reg[3]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_0\, + CO(2) => \sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_1\, + CO(1) => \sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_2\, + CO(0) => \sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_3\, + CYINIT => '0', + DI(3) => \sig_addr_cntr_lsh_im0_reg_n_0_[3]\, + DI(2) => \sig_addr_cntr_lsh_im0_reg_n_0_[2]\, + DI(1) => \sig_addr_cntr_lsh_im0_reg_n_0_[1]\, + DI(0) => \sig_addr_cntr_lsh_im0_reg_n_0_[0]\, + O(3 downto 0) => sig_predict_addr_lsh_im2(3 downto 0), + S(3) => \sig_predict_addr_lsh_ireg3[3]_i_2_n_0\, + S(2) => \sig_predict_addr_lsh_ireg3[3]_i_3_n_0\, + S(1) => \sig_predict_addr_lsh_ireg3[3]_i_4_n_0\, + S(0) => \sig_predict_addr_lsh_ireg3[3]_i_5_n_0\ ); -\dm_address_reg[0]\: unisim.vcomponents.FDRE +\sig_predict_addr_lsh_ireg3_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => O(0), - Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(0), - R => p_0_in + CE => sig_sm_ld_calc3_reg, + D => sig_predict_addr_lsh_im2(4), + Q => \sig_predict_addr_lsh_ireg3_reg_n_0_[4]\, + R => \^sig_init_reg\ ); -\dm_address_reg[10]\: unisim.vcomponents.FDRE +\sig_predict_addr_lsh_ireg3_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => \stride_vid_reg[11]\(2), - Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(10), - R => p_0_in + CE => sig_sm_ld_calc3_reg, + D => sig_predict_addr_lsh_im2(5), + Q => \sig_predict_addr_lsh_ireg3_reg_n_0_[5]\, + R => \^sig_init_reg\ ); -\dm_address_reg[11]\: unisim.vcomponents.FDRE +\sig_predict_addr_lsh_ireg3_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => \stride_vid_reg[11]\(3), - Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(11), - R => p_0_in + CE => sig_sm_ld_calc3_reg, + D => sig_predict_addr_lsh_im2(6), + Q => \sig_predict_addr_lsh_ireg3_reg_n_0_[6]\, + R => \^sig_init_reg\ ); -\dm_address_reg[12]\: unisim.vcomponents.FDRE +\sig_predict_addr_lsh_ireg3_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => \stride_vid_reg[15]\(0), - Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(12), - R => p_0_in + CE => sig_sm_ld_calc3_reg, + D => sig_predict_addr_lsh_im2(7), + Q => \sig_predict_addr_lsh_ireg3_reg_n_0_[7]\, + R => \^sig_init_reg\ ); -\dm_address_reg[13]\: unisim.vcomponents.FDRE +\sig_predict_addr_lsh_ireg3_reg[7]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \sig_predict_addr_lsh_ireg3_reg[3]_i_1_n_0\, + CO(3) => \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_0\, + CO(2) => \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_1\, + CO(1) => \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_2\, + CO(0) => \sig_predict_addr_lsh_ireg3_reg[7]_i_1_n_3\, + CYINIT => '0', + DI(3) => \sig_addr_cntr_lsh_im0_reg_n_0_[7]\, + DI(2) => \sig_addr_cntr_lsh_im0_reg_n_0_[6]\, + DI(1) => \sig_addr_cntr_lsh_im0_reg_n_0_[5]\, + DI(0) => \sig_addr_cntr_lsh_im0_reg_n_0_[4]\, + O(3 downto 0) => sig_predict_addr_lsh_im2(7 downto 4), + S(3) => \sig_predict_addr_lsh_ireg3[7]_i_2_n_0\, + S(2) => \sig_predict_addr_lsh_ireg3[7]_i_3_n_0\, + S(1) => \sig_predict_addr_lsh_ireg3[7]_i_4_n_0\, + S(0) => \sig_predict_addr_lsh_ireg3[7]_i_5_n_0\ + ); +\sig_predict_addr_lsh_ireg3_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => \stride_vid_reg[15]\(1), - Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(13), - R => p_0_in + CE => sig_sm_ld_calc3_reg, + D => sig_predict_addr_lsh_im2(8), + Q => \sig_predict_addr_lsh_ireg3_reg_n_0_[8]\, + R => \^sig_init_reg\ ); -\dm_address_reg[14]\: unisim.vcomponents.FDRE +\sig_predict_addr_lsh_ireg3_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => \stride_vid_reg[15]\(2), - Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(14), - R => p_0_in + CE => sig_sm_ld_calc3_reg, + D => sig_predict_addr_lsh_im2(9), + Q => \sig_predict_addr_lsh_ireg3_reg_n_0_[9]\, + R => \^sig_init_reg\ ); -\dm_address_reg[15]\: unisim.vcomponents.FDRE +sig_sm_halt_reg_i_1: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"A181" ) port map ( - C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => \stride_vid_reg[15]\(3), - Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(15), - R => p_0_in + I0 => sig_pcc_sm_state(2), + I1 => sig_pcc_sm_state(0), + I2 => sig_pcc_sm_state(1), + I3 => \^sig_calc_error_pushed\, + O => sig_sm_halt_ns ); -\dm_address_reg[16]\: unisim.vcomponents.FDRE +sig_sm_halt_reg_reg: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => \dm_address_reg[16]_i_1_n_7\, - Q => dm_address_reg(16), - R => p_0_in - ); -\dm_address_reg[16]_i_1\: unisim.vcomponents.CARRY4 - port map ( - CI => CO(0), - CO(3) => \dm_address_reg[16]_i_1_n_0\, - CO(2) => \dm_address_reg[16]_i_1_n_1\, - CO(1) => \dm_address_reg[16]_i_1_n_2\, - CO(0) => \dm_address_reg[16]_i_1_n_3\, - CYINIT => '0', - DI(3 downto 0) => B"0000", - O(3) => \dm_address_reg[16]_i_1_n_4\, - O(2) => \dm_address_reg[16]_i_1_n_5\, - O(1) => \dm_address_reg[16]_i_1_n_6\, - O(0) => \dm_address_reg[16]_i_1_n_7\, - S(3) => \dm_address[16]_i_2_n_0\, - S(2) => \dm_address[16]_i_3_n_0\, - S(1) => \dm_address[16]_i_4_n_0\, - S(0) => \dm_address[16]_i_5_n_0\ + CE => '1', + D => sig_sm_halt_ns, + Q => \^sig_sm_halt_reg\, + S => \^sig_init_reg\ ); -\dm_address_reg[17]\: unisim.vcomponents.FDRE +sig_sm_ld_calc1_reg_i_1: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"0008000800083008" ) port map ( - C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => \dm_address_reg[16]_i_1_n_6\, - Q => dm_address_reg(17), - R => p_0_in + I0 => sig_calc_error_reg0, + I1 => sig_pcc_sm_state(0), + I2 => sig_pcc_sm_state(2), + I3 => sig_pcc_sm_state(1), + I4 => sig_parent_done, + I5 => \^sig_calc_error_pushed\, + O => sig_sm_ld_calc1_reg_ns ); -\dm_address_reg[18]\: unisim.vcomponents.FDRE +sig_sm_ld_calc1_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => \dm_address_reg[16]_i_1_n_5\, - Q => dm_address_reg(18), - R => p_0_in + CE => '1', + D => sig_sm_ld_calc1_reg_ns, + Q => sig_sm_ld_calc1_reg, + R => \^sig_init_reg\ ); -\dm_address_reg[19]\: unisim.vcomponents.FDRE +sig_sm_ld_calc2_reg_i_1: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"02" ) port map ( - C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => \dm_address_reg[16]_i_1_n_4\, - Q => dm_address_reg(19), - R => p_0_in + I0 => sig_pcc_sm_state(1), + I1 => sig_pcc_sm_state(2), + I2 => sig_pcc_sm_state(0), + O => sig_sm_ld_calc2_reg_ns ); -\dm_address_reg[1]\: unisim.vcomponents.FDRE +sig_sm_ld_calc2_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => O(1), - Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(1), - R => p_0_in + CE => '1', + D => sig_sm_ld_calc2_reg_ns, + Q => sig_sm_ld_calc2_reg, + R => \^sig_init_reg\ ); -\dm_address_reg[20]\: unisim.vcomponents.FDRE +sig_sm_ld_calc3_reg_i_1: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"40" ) port map ( - C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => \dm_address_reg[20]_i_1_n_7\, - Q => dm_address_reg(20), - R => p_0_in - ); -\dm_address_reg[20]_i_1\: unisim.vcomponents.CARRY4 - port map ( - CI => \dm_address_reg[16]_i_1_n_0\, - CO(3) => \dm_address_reg[20]_i_1_n_0\, - CO(2) => \dm_address_reg[20]_i_1_n_1\, - CO(1) => \dm_address_reg[20]_i_1_n_2\, - CO(0) => \dm_address_reg[20]_i_1_n_3\, - CYINIT => '0', - DI(3 downto 0) => B"0000", - O(3) => \dm_address_reg[20]_i_1_n_4\, - O(2) => \dm_address_reg[20]_i_1_n_5\, - O(1) => \dm_address_reg[20]_i_1_n_6\, - O(0) => \dm_address_reg[20]_i_1_n_7\, - S(3) => \dm_address[20]_i_2_n_0\, - S(2) => \dm_address[20]_i_3_n_0\, - S(1) => \dm_address[20]_i_4_n_0\, - S(0) => \dm_address[20]_i_5_n_0\ + I0 => sig_pcc_sm_state(2), + I1 => sig_pcc_sm_state(0), + I2 => sig_pcc_sm_state(1), + O => sig_sm_ld_calc3_reg_ns ); -\dm_address_reg[21]\: unisim.vcomponents.FDRE +sig_sm_ld_calc3_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => \dm_address_reg[20]_i_1_n_6\, - Q => dm_address_reg(21), - R => p_0_in + CE => '1', + D => sig_sm_ld_calc3_reg_ns, + Q => sig_sm_ld_calc3_reg, + R => \^sig_init_reg\ ); -\dm_address_reg[22]\: unisim.vcomponents.FDRE +sig_sm_pop_input_reg_i_1: unisim.vcomponents.LUT5 generic map( - INIT => '0' + INIT => X"00200000" ) port map ( - C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => \dm_address_reg[20]_i_1_n_5\, - Q => dm_address_reg(22), - R => p_0_in + I0 => sig_pcc_sm_state(2), + I1 => sig_pcc_sm_state(0), + I2 => sig_parent_done, + I3 => \^sig_calc_error_pushed\, + I4 => sig_pcc_sm_state(1), + O => sig_sm_pop_input_reg_ns ); -\dm_address_reg[23]\: unisim.vcomponents.FDRE +sig_sm_pop_input_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => \dm_address_reg[20]_i_1_n_4\, - Q => dm_address_reg(23), - R => p_0_in + CE => '1', + D => sig_sm_pop_input_reg_ns, + Q => sig_sm_pop_input_reg, + R => \^sig_init_reg\ ); -\dm_address_reg[24]\: unisim.vcomponents.FDRE +sig_xfer_reg_empty_i_1: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"FF3A" ) port map ( - C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => \dm_address_reg[24]_i_1_n_7\, - Q => dm_address_reg(24), - R => p_0_in - ); -\dm_address_reg[24]_i_1\: unisim.vcomponents.CARRY4 - port map ( - CI => \dm_address_reg[20]_i_1_n_0\, - CO(3) => \dm_address_reg[24]_i_1_n_0\, - CO(2) => \dm_address_reg[24]_i_1_n_1\, - CO(1) => \dm_address_reg[24]_i_1_n_2\, - CO(0) => \dm_address_reg[24]_i_1_n_3\, - CYINIT => '0', - DI(3 downto 0) => B"0000", - O(3) => \dm_address_reg[24]_i_1_n_4\, - O(2) => \dm_address_reg[24]_i_1_n_5\, - O(1) => \dm_address_reg[24]_i_1_n_6\, - O(0) => \dm_address_reg[24]_i_1_n_7\, - S(3) => \dm_address[24]_i_2_n_0\, - S(2) => \dm_address[24]_i_3_n_0\, - S(1) => \dm_address[24]_i_4_n_0\, - S(0) => \dm_address[24]_i_5_n_0\ + I0 => sig_pop_xfer_reg0_out, + I1 => sig_ld_xfer_reg, + I2 => sig_xfer_reg_empty, + I3 => \^sig_init_reg\, + O => sig_xfer_reg_empty_i_1_n_0 ); -\dm_address_reg[25]\: unisim.vcomponents.FDRE +sig_xfer_reg_empty_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => \dm_address_reg[24]_i_1_n_6\, - Q => dm_address_reg(25), - R => p_0_in + CE => '1', + D => sig_xfer_reg_empty_i_1_n_0, + Q => sig_xfer_reg_empty, + R => '0' ); -\dm_address_reg[26]\: unisim.vcomponents.FDRE +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_rd_status_cntl is + port ( + sig_rsc2stat_status_valid : out STD_LOGIC; + sig_rsc2data_ready : out STD_LOGIC; + sig_rd_sts_slverr_reg_reg_0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_inhibit_rdy_n_reg : in STD_LOGIC; + sig_push_rd_sts_reg : in STD_LOGIC; + sig_rd_sts_reg_full0 : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + sig_coelsc_reg_full_reg : in STD_LOGIC; + sig_rd_sts_interr_reg0 : in STD_LOGIC; + sig_rd_sts_slverr_reg0 : in STD_LOGIC; + sig_data2rsc_decerr : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_rd_status_cntl : entity is "axi_datamover_rd_status_cntl"; +end Arty_Z7_20_axi_vdma_0_0_axi_datamover_rd_status_cntl; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_rd_status_cntl is + signal sig_rd_sts_decerr_reg0 : STD_LOGIC; + signal \^sig_rd_sts_slverr_reg_reg_0\ : STD_LOGIC_VECTOR ( 2 downto 0 ); +begin + sig_rd_sts_slverr_reg_reg_0(2 downto 0) <= \^sig_rd_sts_slverr_reg_reg_0\(2 downto 0); +sig_rd_sts_decerr_reg_i_1: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"E" ) port map ( - C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => \dm_address_reg[24]_i_1_n_5\, - Q => dm_address_reg(26), - R => p_0_in + I0 => \^sig_rd_sts_slverr_reg_reg_0\(1), + I1 => sig_data2rsc_decerr, + O => sig_rd_sts_decerr_reg0 ); -\dm_address_reg[27]\: unisim.vcomponents.FDRE +sig_rd_sts_decerr_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => \dm_address_reg[24]_i_1_n_4\, - Q => dm_address_reg(27), - R => p_0_in + CE => sig_push_rd_sts_reg, + D => sig_rd_sts_decerr_reg0, + Q => \^sig_rd_sts_slverr_reg_reg_0\(1), + R => sig_inhibit_rdy_n_reg ); -\dm_address_reg[28]\: unisim.vcomponents.FDRE +sig_rd_sts_interr_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => \dm_address_reg[28]_i_1_n_7\, - Q => dm_address_reg(28), - R => p_0_in - ); -\dm_address_reg[28]_i_1\: unisim.vcomponents.CARRY4 - port map ( - CI => \dm_address_reg[24]_i_1_n_0\, - CO(3) => \NLW_dm_address_reg[28]_i_1_CO_UNCONNECTED\(3), - CO(2) => \dm_address_reg[28]_i_1_n_1\, - CO(1) => \dm_address_reg[28]_i_1_n_2\, - CO(0) => \dm_address_reg[28]_i_1_n_3\, - CYINIT => '0', - DI(3 downto 0) => B"0000", - O(3) => \dm_address_reg[28]_i_1_n_4\, - O(2) => \dm_address_reg[28]_i_1_n_5\, - O(1) => \dm_address_reg[28]_i_1_n_6\, - O(0) => \dm_address_reg[28]_i_1_n_7\, - S(3) => \dm_address[28]_i_2_n_0\, - S(2) => \dm_address[28]_i_3_n_0\, - S(1) => \dm_address[28]_i_4_n_0\, - S(0) => \dm_address[28]_i_5_n_0\ + CE => sig_push_rd_sts_reg, + D => sig_rd_sts_interr_reg0, + Q => \^sig_rd_sts_slverr_reg_reg_0\(0), + R => sig_inhibit_rdy_n_reg ); -\dm_address_reg[29]\: unisim.vcomponents.FDRE +sig_rd_sts_reg_empty_reg: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => \dm_address_reg[28]_i_1_n_6\, - Q => dm_address_reg(29), - R => p_0_in + CE => sig_push_rd_sts_reg, + D => sig_coelsc_reg_full_reg, + Q => sig_rsc2data_ready, + S => sig_inhibit_rdy_n_reg ); -\dm_address_reg[2]\: unisim.vcomponents.FDRE +sig_rd_sts_reg_full_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => O(2), - Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(2), - R => p_0_in + CE => sig_push_rd_sts_reg, + D => sig_rd_sts_reg_full0, + Q => sig_rsc2stat_status_valid, + R => sig_inhibit_rdy_n_reg ); -\dm_address_reg[30]\: unisim.vcomponents.FDRE +sig_rd_sts_slverr_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => \dm_address_reg[28]_i_1_n_5\, - Q => dm_address_reg(30), - R => p_0_in + CE => sig_push_rd_sts_reg, + D => sig_rd_sts_slverr_reg0, + Q => \^sig_rd_sts_slverr_reg_reg_0\(2), + R => sig_inhibit_rdy_n_reg ); -\dm_address_reg[31]\: unisim.vcomponents.FDRE +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_reset is + port ( + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : out STD_LOGIC; + sig_rst2all_stop_request_0 : out STD_LOGIC; + sig_stream_rst : out STD_LOGIC; + sig_halt_reg_reg : out STD_LOGIC; + datamover_idle_reg : out STD_LOGIC; + s2mm_halt_cmplt : out STD_LOGIC; + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + \sig_byte_cntr_reg[8]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_soft_reset_i_reg : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + halt_i_reg : in STD_LOGIC; + sig_halt_reg : in STD_LOGIC; + s2mm_halt : in STD_LOGIC; + s2mm_dmacr : in STD_LOGIC_VECTOR ( 0 to 0 ); + datamover_idle_2 : in STD_LOGIC; + lsig_end_of_cmd_reg : in STD_LOGIC; + sig_clr_dbc_reg : in STD_LOGIC; + sig_wsc2rst_stop_cmplt : in STD_LOGIC; + sig_addr_reg_empty : in STD_LOGIC; + sig_addr2wsc_calc_error : in STD_LOGIC; + sig_data2rst_stop_cmplt : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_reset : entity is "axi_datamover_reset"; +end Arty_Z7_20_axi_vdma_0_0_axi_datamover_reset; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_reset is + signal \^s2mm_halt_cmplt\ : STD_LOGIC; + signal \^sig_cmd_stat_rst_user_reg_n_cdc_from_reg\ : STD_LOGIC; + signal sig_halt_cmplt_i_1_n_0 : STD_LOGIC; + signal \^sig_rst2all_stop_request_0\ : STD_LOGIC; + signal \^sig_stream_rst\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \GEN_INDET_BTT.lsig_byte_cntr[15]_i_1\ : label is "soft_lutpair239"; + attribute SOFT_HLUTNM of \sig_byte_cntr[8]_i_1\ : label is "soft_lutpair239"; +begin + s2mm_halt_cmplt <= \^s2mm_halt_cmplt\; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg <= \^sig_cmd_stat_rst_user_reg_n_cdc_from_reg\; + sig_rst2all_stop_request_0 <= \^sig_rst2all_stop_request_0\; + sig_stream_rst <= \^sig_stream_rst\; +\GEN_INDET_BTT.lsig_byte_cntr[15]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"D" ) port map ( - C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => \dm_address_reg[28]_i_1_n_4\, - Q => dm_address_reg(31), - R => p_0_in + I0 => \^sig_cmd_stat_rst_user_reg_n_cdc_from_reg\, + I1 => lsig_end_of_cmd_reg, + O => SR(0) ); -\dm_address_reg[3]\: unisim.vcomponents.FDRE +\datamover_idle_i_1__0\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"CF88" ) port map ( - C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => O(3), - Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(3), - R => p_0_in + I0 => \^s2mm_halt_cmplt\, + I1 => s2mm_halt, + I2 => s2mm_dmacr(0), + I3 => datamover_idle_2, + O => datamover_idle_reg ); -\dm_address_reg[4]\: unisim.vcomponents.FDRE +\sig_byte_cntr[8]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"D" ) port map ( - C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => \stride_vid_reg[7]\(0), - Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(4), - R => p_0_in + I0 => \^sig_cmd_stat_rst_user_reg_n_cdc_from_reg\, + I1 => sig_clr_dbc_reg, + O => \sig_byte_cntr_reg[8]\(0) ); -\dm_address_reg[5]\: unisim.vcomponents.FDRE +\sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => \stride_vid_reg[7]\(1), - Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(5), - R => p_0_in + C => m_axi_s2mm_aclk, + CE => '1', + D => s_soft_reset_i_reg, + Q => \^sig_cmd_stat_rst_user_reg_n_cdc_from_reg\, + R => '0' ); -\dm_address_reg[6]\: unisim.vcomponents.FDRE +sig_halt_cmplt_i_1: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFFFFA8000000" ) port map ( - C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => \stride_vid_reg[7]\(2), - Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(6), - R => p_0_in + I0 => sig_wsc2rst_stop_cmplt, + I1 => sig_addr_reg_empty, + I2 => sig_addr2wsc_calc_error, + I3 => sig_halt_reg, + I4 => sig_data2rst_stop_cmplt, + I5 => \^s2mm_halt_cmplt\, + O => sig_halt_cmplt_i_1_n_0 ); -\dm_address_reg[7]\: unisim.vcomponents.FDRE +sig_halt_cmplt_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => \stride_vid_reg[7]\(3), - Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(7), - R => p_0_in + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_halt_cmplt_i_1_n_0, + Q => \^s2mm_halt_cmplt\, + R => \^sig_stream_rst\ ); -\dm_address_reg[8]\: unisim.vcomponents.FDRE +sig_halt_reg_i_1: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"E" ) port map ( - C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => \stride_vid_reg[11]\(0), - Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(8), - R => p_0_in + I0 => \^sig_rst2all_stop_request_0\, + I1 => sig_halt_reg, + O => sig_halt_reg_reg ); -\dm_address_reg[9]\: unisim.vcomponents.FDRE +\sig_last_reg_out_i_1__0\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"1" ) port map ( - C => m_axi_mm2s_aclk, - CE => \dm_address[0]_i_1_n_0\, - D => \stride_vid_reg[11]\(1), - Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(9), - R => p_0_in + I0 => \^sig_cmd_stat_rst_user_reg_n_cdc_from_reg\, + O => \^sig_stream_rst\ ); -frame_sync_d1_reg: unisim.vcomponents.FDRE +sig_s_h_halt_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, + C => m_axi_s2mm_aclk, CE => '1', - D => p_23_out, - Q => \^tstvect_fsync_d1\, - R => p_0_in + D => halt_i_reg, + Q => \^sig_rst2all_stop_request_0\, + R => \^sig_stream_rst\ ); -frame_sync_d2_reg: unisim.vcomponents.FDRE +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_reset_20 is + port ( + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : out STD_LOGIC; + sig_rst2all_stop_request : out STD_LOGIC; + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + datamover_idle_reg : out STD_LOGIC; + mm2s_halt_cmplt : out STD_LOGIC; + \out\ : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + halt_i_reg : in STD_LOGIC; + p_71_out : in STD_LOGIC_VECTOR ( 0 to 0 ); + mm2s_halt : in STD_LOGIC; + datamover_idle : in STD_LOGIC; + sig_calc_error_reg_reg : in STD_LOGIC; + sig_next_calc_error_reg : in STD_LOGIC; + sig_addr_posted_cntr : in STD_LOGIC_VECTOR ( 2 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_reset_20 : entity is "axi_datamover_reset"; +end Arty_Z7_20_axi_vdma_0_0_axi_datamover_reset_20; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_reset_20 is + signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^mm2s_halt_cmplt\ : STD_LOGIC; + signal \^sig_cmd_stat_rst_user_reg_n_cdc_from_reg\ : STD_LOGIC; + signal sig_halt_cmplt_i_1_n_0 : STD_LOGIC; +begin + SR(0) <= \^sr\(0); + mm2s_halt_cmplt <= \^mm2s_halt_cmplt\; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg <= \^sig_cmd_stat_rst_user_reg_n_cdc_from_reg\; +\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_4\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"1" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \^tstvect_fsync_d1\, - Q => tstvect_fsync_d2, - R => p_0_in + I0 => \^sig_cmd_stat_rst_user_reg_n_cdc_from_reg\, + O => \^sr\(0) ); -frame_sync_d3_reg: unisim.vcomponents.FDRE +datamover_idle_i_1: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"F3A0" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => tstvect_fsync_d2, - Q => frame_sync_d3, - R => p_0_in + I0 => \^mm2s_halt_cmplt\, + I1 => p_71_out(0), + I2 => mm2s_halt, + I3 => datamover_idle, + O => datamover_idle_reg ); -frame_sync_reg_reg: unisim.vcomponents.FDRE +\sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, CE => '1', - D => frame_sync_d3, - Q => \^frame_sync_reg\, - R => p_0_in - ); -\p_0_out_carry__0_i_1__0\: unisim.vcomponents.LUT2 + D => \out\, + Q => \^sig_cmd_stat_rst_user_reg_n_cdc_from_reg\, + R => '0' + ); +sig_halt_cmplt_i_1: unisim.vcomponents.LUT6 generic map( - INIT => X"9" + INIT => X"FFFFFFFF44444445" ) port map ( - I0 => \cmnds_queued_reg__0\(6), - I1 => \cmnds_queued_reg__0\(7), - O => \cmnds_queued_reg[7]_1\(2) + I0 => sig_calc_error_reg_reg, + I1 => sig_next_calc_error_reg, + I2 => sig_addr_posted_cntr(0), + I3 => sig_addr_posted_cntr(2), + I4 => sig_addr_posted_cntr(1), + I5 => \^mm2s_halt_cmplt\, + O => sig_halt_cmplt_i_1_n_0 ); -\p_0_out_carry__0_i_2__0\: unisim.vcomponents.LUT2 +sig_halt_cmplt_reg: unisim.vcomponents.FDRE generic map( - INIT => X"9" + INIT => '0' ) port map ( - I0 => \^cmnds_queued_reg[7]_0\(5), - I1 => \cmnds_queued_reg__0\(6), - O => \cmnds_queued_reg[7]_1\(1) + C => m_axi_mm2s_aclk, + CE => '1', + D => sig_halt_cmplt_i_1_n_0, + Q => \^mm2s_halt_cmplt\, + R => \^sr\(0) ); -\p_0_out_carry__0_i_3\: unisim.vcomponents.LUT2 +sig_s_h_halt_reg_reg: unisim.vcomponents.FDRE generic map( - INIT => X"9" + INIT => '0' ) port map ( - I0 => \^cmnds_queued_reg[7]_0\(4), - I1 => \^cmnds_queued_reg[7]_0\(5), - O => \cmnds_queued_reg[7]_1\(0) + C => m_axi_mm2s_aclk, + CE => '1', + D => halt_i_reg, + Q => sig_rst2all_stop_request, + R => \^sr\(0) ); -\p_0_out_carry_i_1__0\: unisim.vcomponents.LUT1 +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_skid2mm_buf is + port ( + \out\ : out STD_LOGIC; + m_axi_s2mm_wvalid : out STD_LOGIC; + m_axi_s2mm_wlast : out STD_LOGIC; + m_axi_s2mm_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_s2mm_aclk : in STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + sig_dqual_reg_full : in STD_LOGIC; + \sig_dbeat_cntr_eq_0__2\ : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + m_axi_s2mm_wready : in STD_LOGIC; + sig_init_reg : in STD_LOGIC; + sig_data2skid_wvalid : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 63 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_skid2mm_buf : entity is "axi_datamover_skid2mm_buf"; +end Arty_Z7_20_axi_vdma_0_0_axi_datamover_skid2mm_buf; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_skid2mm_buf is + signal \^m_axi_s2mm_wlast\ : STD_LOGIC; + signal \sig_data_reg_out[63]_i_1__0_n_0\ : STD_LOGIC; + signal sig_data_skid_mux_out : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal sig_data_skid_reg : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal sig_last_reg_out_i_2_n_0 : STD_LOGIC; + signal sig_last_skid_reg : STD_LOGIC; + signal sig_last_skid_reg_i_1_n_0 : STD_LOGIC; + signal sig_m_valid_dup : STD_LOGIC; + attribute RTL_KEEP : string; + attribute RTL_KEEP of sig_m_valid_dup : signal is "true"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of sig_m_valid_dup : signal is "no"; + signal \sig_m_valid_dup_i_1__1_n_0\ : STD_LOGIC; + signal sig_m_valid_out : STD_LOGIC; + attribute RTL_KEEP of sig_m_valid_out : signal is "true"; + attribute equivalent_register_removal of sig_m_valid_out : signal is "no"; + signal sig_s_ready_dup : STD_LOGIC; + attribute RTL_KEEP of sig_s_ready_dup : signal is "true"; + attribute equivalent_register_removal of sig_s_ready_dup : signal is "no"; + signal sig_s_ready_dup_i_1_n_0 : STD_LOGIC; + signal sig_s_ready_out : STD_LOGIC; + attribute RTL_KEEP of sig_s_ready_out : signal is "true"; + attribute equivalent_register_removal of sig_s_ready_out : signal is "no"; + attribute KEEP : string; + attribute KEEP of sig_m_valid_dup_reg : label is "yes"; + attribute equivalent_register_removal of sig_m_valid_dup_reg : label is "no"; + attribute KEEP of sig_m_valid_out_reg : label is "yes"; + attribute equivalent_register_removal of sig_m_valid_out_reg : label is "no"; + attribute KEEP of sig_s_ready_dup_reg : label is "yes"; + attribute equivalent_register_removal of sig_s_ready_dup_reg : label is "no"; + attribute KEEP of sig_s_ready_out_reg : label is "yes"; + attribute equivalent_register_removal of sig_s_ready_out_reg : label is "no"; +begin + m_axi_s2mm_wlast <= \^m_axi_s2mm_wlast\; + m_axi_s2mm_wvalid <= sig_m_valid_out; + \out\ <= sig_s_ready_out; +\sig_data_reg_out[0]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"1" + INIT => X"CA" ) port map ( - I0 => \^cmnds_queued_reg[7]_0\(1), - O => DI(0) + I0 => sig_data_skid_reg(0), + I1 => D(0), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(0) ); -\p_0_out_carry_i_2__0\: unisim.vcomponents.LUT2 +\sig_data_reg_out[10]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"9" + INIT => X"CA" ) port map ( - I0 => \^cmnds_queued_reg[7]_0\(3), - I1 => \^cmnds_queued_reg[7]_0\(4), - O => S(3) + I0 => sig_data_skid_reg(10), + I1 => D(10), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(10) ); -\p_0_out_carry_i_3__0\: unisim.vcomponents.LUT2 +\sig_data_reg_out[11]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"9" + INIT => X"CA" ) port map ( - I0 => \^cmnds_queued_reg[7]_0\(2), - I1 => \^cmnds_queued_reg[7]_0\(3), - O => S(2) + I0 => sig_data_skid_reg(11), + I1 => D(11), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(11) ); -\p_0_out_carry_i_4__0\: unisim.vcomponents.LUT2 +\sig_data_reg_out[12]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"9" + INIT => X"CA" ) port map ( - I0 => \^cmnds_queued_reg[7]_0\(1), - I1 => \^cmnds_queued_reg[7]_0\(2), - O => S(1) + I0 => sig_data_skid_reg(12), + I1 => D(12), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(12) ); -\p_0_out_carry_i_5__0\: unisim.vcomponents.LUT4 +\sig_data_reg_out[13]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"A655" + INIT => X"CA" ) port map ( - I0 => \^cmnds_queued_reg[7]_0\(1), - I1 => p_57_out, - I2 => \INFERRED_GEN.cnt_i_reg[2]\(0), - I3 => \^s_axis_cmd_tvalid_reg\, - O => S(0) + I0 => sig_data_skid_reg(13), + I1 => D(13), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(13) ); -\s_axis_cmd_tdata[0]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[14]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[0]\, - O => D(0) + I0 => sig_data_skid_reg(14), + I1 => D(14), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(14) ); -\s_axis_cmd_tdata[10]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[15]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[10]\, - O => D(10) + I0 => sig_data_skid_reg(15), + I1 => D(15), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(15) ); -\s_axis_cmd_tdata[11]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[16]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[11]\, - O => D(11) + I0 => sig_data_skid_reg(16), + I1 => D(16), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(16) ); -\s_axis_cmd_tdata[12]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[17]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[12]\, - O => D(12) + I0 => sig_data_skid_reg(17), + I1 => D(17), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(17) ); -\s_axis_cmd_tdata[13]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[18]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[13]\, - O => D(13) + I0 => sig_data_skid_reg(18), + I1 => D(18), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(18) ); -\s_axis_cmd_tdata[14]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[19]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[14]\, - O => D(14) + I0 => sig_data_skid_reg(19), + I1 => D(19), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(19) ); -\s_axis_cmd_tdata[15]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[1]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[15]\, - O => D(15) + I0 => sig_data_skid_reg(1), + I1 => D(1), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(1) ); -\s_axis_cmd_tdata[1]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[20]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[1]\, - O => D(1) + I0 => sig_data_skid_reg(20), + I1 => D(20), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(20) ); -\s_axis_cmd_tdata[23]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[21]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[23]\, - O => D(16) + I0 => sig_data_skid_reg(21), + I1 => D(21), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(21) ); -\s_axis_cmd_tdata[2]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[22]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[2]\, - O => D(2) + I0 => sig_data_skid_reg(22), + I1 => D(22), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(22) ); -\s_axis_cmd_tdata[32]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[23]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[32]\, - O => D(17) + I0 => sig_data_skid_reg(23), + I1 => D(23), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(23) ); -\s_axis_cmd_tdata[33]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[24]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[33]\, - O => D(18) + I0 => sig_data_skid_reg(24), + I1 => D(24), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(24) ); -\s_axis_cmd_tdata[34]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[25]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[34]\, - O => D(19) + I0 => sig_data_skid_reg(25), + I1 => D(25), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(25) ); -\s_axis_cmd_tdata[35]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[26]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[35]\, - O => D(20) + I0 => sig_data_skid_reg(26), + I1 => D(26), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(26) ); -\s_axis_cmd_tdata[36]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[27]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[36]\, - O => D(21) + I0 => sig_data_skid_reg(27), + I1 => D(27), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(27) ); -\s_axis_cmd_tdata[37]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[28]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[37]\, - O => D(22) + I0 => sig_data_skid_reg(28), + I1 => D(28), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(28) ); -\s_axis_cmd_tdata[38]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[29]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[38]\, - O => D(23) + I0 => sig_data_skid_reg(29), + I1 => D(29), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(29) ); -\s_axis_cmd_tdata[39]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[2]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[39]\, - O => D(24) + I0 => sig_data_skid_reg(2), + I1 => D(2), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(2) ); -\s_axis_cmd_tdata[3]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[30]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[3]\, - O => D(3) + I0 => sig_data_skid_reg(30), + I1 => D(30), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(30) ); -\s_axis_cmd_tdata[40]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[31]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[40]\, - O => D(25) + I0 => sig_data_skid_reg(31), + I1 => D(31), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(31) ); -\s_axis_cmd_tdata[41]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[32]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[41]\, - O => D(26) + I0 => sig_data_skid_reg(32), + I1 => D(32), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(32) ); -\s_axis_cmd_tdata[42]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[33]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[42]\, - O => D(27) + I0 => sig_data_skid_reg(33), + I1 => D(33), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(33) ); -\s_axis_cmd_tdata[43]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[34]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[43]\, - O => D(28) + I0 => sig_data_skid_reg(34), + I1 => D(34), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(34) ); -\s_axis_cmd_tdata[44]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[35]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[44]\, - O => D(29) + I0 => sig_data_skid_reg(35), + I1 => D(35), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(35) ); -\s_axis_cmd_tdata[45]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[36]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[45]\, - O => D(30) + I0 => sig_data_skid_reg(36), + I1 => D(36), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(36) ); -\s_axis_cmd_tdata[46]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[37]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[46]\, - O => D(31) + I0 => sig_data_skid_reg(37), + I1 => D(37), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(37) ); -\s_axis_cmd_tdata[47]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[38]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[47]\, - O => D(32) + I0 => sig_data_skid_reg(38), + I1 => D(38), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(38) ); -\s_axis_cmd_tdata[48]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[39]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[48]\, - O => D(33) + I0 => sig_data_skid_reg(39), + I1 => D(39), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(39) ); -\s_axis_cmd_tdata[49]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[3]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[49]\, - O => D(34) + I0 => sig_data_skid_reg(3), + I1 => D(3), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(3) ); -\s_axis_cmd_tdata[4]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[40]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[4]\, - O => D(4) + I0 => sig_data_skid_reg(40), + I1 => D(40), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(40) ); -\s_axis_cmd_tdata[50]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[41]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[50]\, - O => D(35) + I0 => sig_data_skid_reg(41), + I1 => D(41), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(41) ); -\s_axis_cmd_tdata[51]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[42]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[51]\, - O => D(36) + I0 => sig_data_skid_reg(42), + I1 => D(42), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(42) ); -\s_axis_cmd_tdata[52]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[43]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[52]\, - O => D(37) + I0 => sig_data_skid_reg(43), + I1 => D(43), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(43) ); -\s_axis_cmd_tdata[53]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[44]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[53]\, - O => D(38) + I0 => sig_data_skid_reg(44), + I1 => D(44), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(44) ); -\s_axis_cmd_tdata[54]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[45]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[54]\, - O => D(39) + I0 => sig_data_skid_reg(45), + I1 => D(45), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(45) ); -\s_axis_cmd_tdata[55]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[46]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[55]\, - O => D(40) + I0 => sig_data_skid_reg(46), + I1 => D(46), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(46) ); -\s_axis_cmd_tdata[56]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[47]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[56]\, - O => D(41) + I0 => sig_data_skid_reg(47), + I1 => D(47), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(47) ); -\s_axis_cmd_tdata[57]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[48]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[57]\, - O => D(42) + I0 => sig_data_skid_reg(48), + I1 => D(48), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(48) ); -\s_axis_cmd_tdata[58]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[49]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[58]\, - O => D(43) + I0 => sig_data_skid_reg(49), + I1 => D(49), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(49) ); -\s_axis_cmd_tdata[59]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[4]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[59]\, - O => D(44) + I0 => sig_data_skid_reg(4), + I1 => D(4), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(4) ); -\s_axis_cmd_tdata[5]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[50]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[5]\, - O => D(5) + I0 => sig_data_skid_reg(50), + I1 => D(50), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(50) ); -\s_axis_cmd_tdata[60]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[51]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[60]\, - O => D(45) + I0 => sig_data_skid_reg(51), + I1 => D(51), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(51) ); -\s_axis_cmd_tdata[61]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[52]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[61]\, - O => D(46) + I0 => sig_data_skid_reg(52), + I1 => D(52), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(52) ); -\s_axis_cmd_tdata[62]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[53]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[62]\, - O => D(47) + I0 => sig_data_skid_reg(53), + I1 => D(53), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(53) ); -\s_axis_cmd_tdata[63]_i_3\: unisim.vcomponents.LUT2 +\sig_data_reg_out[54]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[63]\, - O => D(48) + I0 => sig_data_skid_reg(54), + I1 => D(54), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(54) ); -\s_axis_cmd_tdata[6]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[55]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[6]\, - O => D(6) + I0 => sig_data_skid_reg(55), + I1 => D(55), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(55) ); -\s_axis_cmd_tdata[7]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[56]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[7]\, - O => D(7) + I0 => sig_data_skid_reg(56), + I1 => D(56), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(56) ); -\s_axis_cmd_tdata[8]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[57]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[8]\, - O => D(8) + I0 => sig_data_skid_reg(57), + I1 => D(57), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(57) ); -\s_axis_cmd_tdata[9]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[58]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"CA" ) port map ( - I0 => \^s_axis_cmd_tvalid_reg\, - I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[9]\, - O => D(9) + I0 => sig_data_skid_reg(58), + I1 => D(58), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(58) ); -\vert_count[0]_i_1\: unisim.vcomponents.LUT6 +\sig_data_reg_out[59]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AAAAAAAAAAAAAAEA" + INIT => X"CA" ) port map ( - I0 => \^load_new_addr\, - I1 => dmacntrl_cs(1), - I2 => dmacntrl_cs(0), - I3 => dmacntrl_cs(2), - I4 => dmacntrl_ns14_out, - I5 => s_axis_cmd_tvalid_reg_0, - O => \vert_count[0]_i_1_n_0\ + I0 => sig_data_skid_reg(59), + I1 => D(59), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(59) ); -\vert_count[0]_i_10\: unisim.vcomponents.LUT3 +\sig_data_reg_out[5]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"C5" + INIT => X"CA" ) port map ( - I0 => vert_count_reg(0), - I1 => \vsize_vid_reg[12]\(0), - I2 => \^load_new_addr\, - O => \vert_count[0]_i_10_n_0\ + I0 => sig_data_skid_reg(5), + I1 => D(5), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(5) ); -\vert_count[0]_i_3\: unisim.vcomponents.LUT3 +\sig_data_reg_out[60]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"B8" + INIT => X"CA" ) port map ( - I0 => \vsize_vid_reg[12]\(3), - I1 => \^load_new_addr\, - I2 => vert_count_reg(3), - O => \vert_count[0]_i_3_n_0\ + I0 => sig_data_skid_reg(60), + I1 => D(60), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(60) ); -\vert_count[0]_i_4\: unisim.vcomponents.LUT3 +\sig_data_reg_out[61]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"B8" + INIT => X"CA" ) port map ( - I0 => \vsize_vid_reg[12]\(2), - I1 => \^load_new_addr\, - I2 => vert_count_reg(2), - O => \vert_count[0]_i_4_n_0\ + I0 => sig_data_skid_reg(61), + I1 => D(61), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(61) ); -\vert_count[0]_i_5\: unisim.vcomponents.LUT3 +\sig_data_reg_out[62]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"B8" + INIT => X"CA" ) port map ( - I0 => \vsize_vid_reg[12]\(1), - I1 => \^load_new_addr\, - I2 => vert_count_reg(1), - O => \vert_count[0]_i_5_n_0\ + I0 => sig_data_skid_reg(62), + I1 => D(62), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(62) ); -\vert_count[0]_i_6\: unisim.vcomponents.LUT3 +\sig_data_reg_out[63]_i_1__0\: unisim.vcomponents.LUT2 generic map( - INIT => X"B8" + INIT => X"B" ) port map ( - I0 => \vsize_vid_reg[12]\(0), - I1 => \^load_new_addr\, - I2 => vert_count_reg(0), - O => \vert_count[0]_i_6_n_0\ + I0 => m_axi_s2mm_wready, + I1 => sig_m_valid_dup, + O => \sig_data_reg_out[63]_i_1__0_n_0\ ); -\vert_count[0]_i_7\: unisim.vcomponents.LUT3 +\sig_data_reg_out[63]_i_2\: unisim.vcomponents.LUT3 generic map( - INIT => X"C5" + INIT => X"CA" ) port map ( - I0 => vert_count_reg(3), - I1 => \vsize_vid_reg[12]\(3), - I2 => \^load_new_addr\, - O => \vert_count[0]_i_7_n_0\ + I0 => sig_data_skid_reg(63), + I1 => D(63), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(63) ); -\vert_count[0]_i_8\: unisim.vcomponents.LUT3 +\sig_data_reg_out[6]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"C5" + INIT => X"CA" ) port map ( - I0 => vert_count_reg(2), - I1 => \vsize_vid_reg[12]\(2), - I2 => \^load_new_addr\, - O => \vert_count[0]_i_8_n_0\ + I0 => sig_data_skid_reg(6), + I1 => D(6), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(6) ); -\vert_count[0]_i_9\: unisim.vcomponents.LUT3 +\sig_data_reg_out[7]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"C5" + INIT => X"CA" ) port map ( - I0 => vert_count_reg(1), - I1 => \vsize_vid_reg[12]\(1), - I2 => \^load_new_addr\, - O => \vert_count[0]_i_9_n_0\ + I0 => sig_data_skid_reg(7), + I1 => D(7), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(7) ); -\vert_count[12]_i_2\: unisim.vcomponents.LUT3 +\sig_data_reg_out[8]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"C5" + INIT => X"CA" ) port map ( - I0 => vert_count_reg(12), - I1 => \vsize_vid_reg[12]\(12), - I2 => \^load_new_addr\, - O => \vert_count[12]_i_2_n_0\ + I0 => sig_data_skid_reg(8), + I1 => D(8), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(8) ); -\vert_count[4]_i_2\: unisim.vcomponents.LUT3 +\sig_data_reg_out[9]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"B8" + INIT => X"CA" ) port map ( - I0 => \vsize_vid_reg[12]\(7), - I1 => \^load_new_addr\, - I2 => vert_count_reg(7), - O => \vert_count[4]_i_2_n_0\ + I0 => sig_data_skid_reg(9), + I1 => D(9), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(9) ); -\vert_count[4]_i_3\: unisim.vcomponents.LUT3 +\sig_data_reg_out_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => \vsize_vid_reg[12]\(6), - I1 => \^load_new_addr\, - I2 => vert_count_reg(6), - O => \vert_count[4]_i_3_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(0), + Q => m_axi_s2mm_wdata(0), + R => '0' ); -\vert_count[4]_i_4\: unisim.vcomponents.LUT3 +\sig_data_reg_out_reg[10]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => \vsize_vid_reg[12]\(5), - I1 => \^load_new_addr\, - I2 => vert_count_reg(5), - O => \vert_count[4]_i_4_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(10), + Q => m_axi_s2mm_wdata(10), + R => '0' ); -\vert_count[4]_i_5\: unisim.vcomponents.LUT3 +\sig_data_reg_out_reg[11]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => \vsize_vid_reg[12]\(4), - I1 => \^load_new_addr\, - I2 => vert_count_reg(4), - O => \vert_count[4]_i_5_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(11), + Q => m_axi_s2mm_wdata(11), + R => '0' ); -\vert_count[4]_i_6\: unisim.vcomponents.LUT3 +\sig_data_reg_out_reg[12]\: unisim.vcomponents.FDRE generic map( - INIT => X"C5" + INIT => '0' ) port map ( - I0 => vert_count_reg(7), - I1 => \vsize_vid_reg[12]\(7), - I2 => \^load_new_addr\, - O => \vert_count[4]_i_6_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(12), + Q => m_axi_s2mm_wdata(12), + R => '0' ); -\vert_count[4]_i_7\: unisim.vcomponents.LUT3 +\sig_data_reg_out_reg[13]\: unisim.vcomponents.FDRE generic map( - INIT => X"C5" + INIT => '0' ) port map ( - I0 => vert_count_reg(6), - I1 => \vsize_vid_reg[12]\(6), - I2 => \^load_new_addr\, - O => \vert_count[4]_i_7_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(13), + Q => m_axi_s2mm_wdata(13), + R => '0' ); -\vert_count[4]_i_8\: unisim.vcomponents.LUT3 +\sig_data_reg_out_reg[14]\: unisim.vcomponents.FDRE generic map( - INIT => X"C5" + INIT => '0' ) port map ( - I0 => vert_count_reg(5), - I1 => \vsize_vid_reg[12]\(5), - I2 => \^load_new_addr\, - O => \vert_count[4]_i_8_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(14), + Q => m_axi_s2mm_wdata(14), + R => '0' ); -\vert_count[4]_i_9\: unisim.vcomponents.LUT3 +\sig_data_reg_out_reg[15]\: unisim.vcomponents.FDRE generic map( - INIT => X"C5" + INIT => '0' ) port map ( - I0 => vert_count_reg(4), - I1 => \vsize_vid_reg[12]\(4), - I2 => \^load_new_addr\, - O => \vert_count[4]_i_9_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(15), + Q => m_axi_s2mm_wdata(15), + R => '0' ); -\vert_count[8]_i_2\: unisim.vcomponents.LUT3 +\sig_data_reg_out_reg[16]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => \vsize_vid_reg[12]\(11), - I1 => \^load_new_addr\, - I2 => vert_count_reg(11), - O => \vert_count[8]_i_2_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(16), + Q => m_axi_s2mm_wdata(16), + R => '0' ); -\vert_count[8]_i_3\: unisim.vcomponents.LUT3 +\sig_data_reg_out_reg[17]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => \vsize_vid_reg[12]\(10), - I1 => \^load_new_addr\, - I2 => vert_count_reg(10), - O => \vert_count[8]_i_3_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(17), + Q => m_axi_s2mm_wdata(17), + R => '0' ); -\vert_count[8]_i_4\: unisim.vcomponents.LUT3 +\sig_data_reg_out_reg[18]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => \vsize_vid_reg[12]\(9), - I1 => \^load_new_addr\, - I2 => vert_count_reg(9), - O => \vert_count[8]_i_4_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(18), + Q => m_axi_s2mm_wdata(18), + R => '0' ); -\vert_count[8]_i_5\: unisim.vcomponents.LUT3 +\sig_data_reg_out_reg[19]\: unisim.vcomponents.FDRE generic map( - INIT => X"B8" + INIT => '0' ) port map ( - I0 => \vsize_vid_reg[12]\(8), - I1 => \^load_new_addr\, - I2 => vert_count_reg(8), - O => \vert_count[8]_i_5_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(19), + Q => m_axi_s2mm_wdata(19), + R => '0' ); -\vert_count[8]_i_6\: unisim.vcomponents.LUT3 +\sig_data_reg_out_reg[1]\: unisim.vcomponents.FDRE generic map( - INIT => X"C5" + INIT => '0' ) port map ( - I0 => vert_count_reg(11), - I1 => \vsize_vid_reg[12]\(11), - I2 => \^load_new_addr\, - O => \vert_count[8]_i_6_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(1), + Q => m_axi_s2mm_wdata(1), + R => '0' ); -\vert_count[8]_i_7\: unisim.vcomponents.LUT3 +\sig_data_reg_out_reg[20]\: unisim.vcomponents.FDRE generic map( - INIT => X"C5" + INIT => '0' ) port map ( - I0 => vert_count_reg(10), - I1 => \vsize_vid_reg[12]\(10), - I2 => \^load_new_addr\, - O => \vert_count[8]_i_7_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(20), + Q => m_axi_s2mm_wdata(20), + R => '0' ); -\vert_count[8]_i_8\: unisim.vcomponents.LUT3 +\sig_data_reg_out_reg[21]\: unisim.vcomponents.FDRE generic map( - INIT => X"C5" + INIT => '0' ) port map ( - I0 => vert_count_reg(9), - I1 => \vsize_vid_reg[12]\(9), - I2 => \^load_new_addr\, - O => \vert_count[8]_i_8_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(21), + Q => m_axi_s2mm_wdata(21), + R => '0' ); -\vert_count[8]_i_9\: unisim.vcomponents.LUT3 +\sig_data_reg_out_reg[22]\: unisim.vcomponents.FDRE generic map( - INIT => X"C5" + INIT => '0' ) port map ( - I0 => vert_count_reg(8), - I1 => \vsize_vid_reg[12]\(8), - I2 => \^load_new_addr\, - O => \vert_count[8]_i_9_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(22), + Q => m_axi_s2mm_wdata(22), + R => '0' ); -\vert_count_reg[0]\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \vert_count[0]_i_1_n_0\, - D => \vert_count_reg[0]_i_2_n_7\, - Q => vert_count_reg(0), - R => p_0_in + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(23), + Q => m_axi_s2mm_wdata(23), + R => '0' ); -\vert_count_reg[0]_i_2\: unisim.vcomponents.CARRY4 - port map ( - CI => '0', - CO(3) => \vert_count_reg[0]_i_2_n_0\, - CO(2) => \vert_count_reg[0]_i_2_n_1\, - CO(1) => \vert_count_reg[0]_i_2_n_2\, - CO(0) => \vert_count_reg[0]_i_2_n_3\, - CYINIT => '0', - DI(3) => \vert_count[0]_i_3_n_0\, - DI(2) => \vert_count[0]_i_4_n_0\, - DI(1) => \vert_count[0]_i_5_n_0\, - DI(0) => \vert_count[0]_i_6_n_0\, - O(3) => \vert_count_reg[0]_i_2_n_4\, - O(2) => \vert_count_reg[0]_i_2_n_5\, - O(1) => \vert_count_reg[0]_i_2_n_6\, - O(0) => \vert_count_reg[0]_i_2_n_7\, - S(3) => \vert_count[0]_i_7_n_0\, - S(2) => \vert_count[0]_i_8_n_0\, - S(1) => \vert_count[0]_i_9_n_0\, - S(0) => \vert_count[0]_i_10_n_0\ +\sig_data_reg_out_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(24), + Q => m_axi_s2mm_wdata(24), + R => '0' ); -\vert_count_reg[10]\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \vert_count[0]_i_1_n_0\, - D => \vert_count_reg[8]_i_1_n_5\, - Q => vert_count_reg(10), - R => p_0_in + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(25), + Q => m_axi_s2mm_wdata(25), + R => '0' ); -\vert_count_reg[11]\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \vert_count[0]_i_1_n_0\, - D => \vert_count_reg[8]_i_1_n_4\, - Q => vert_count_reg(11), - R => p_0_in + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(26), + Q => m_axi_s2mm_wdata(26), + R => '0' ); -\vert_count_reg[12]\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \vert_count[0]_i_1_n_0\, - D => \vert_count_reg[12]_i_1_n_7\, - Q => vert_count_reg(12), - R => p_0_in + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(27), + Q => m_axi_s2mm_wdata(27), + R => '0' ); -\vert_count_reg[12]_i_1\: unisim.vcomponents.CARRY4 - port map ( - CI => \vert_count_reg[8]_i_1_n_0\, - CO(3 downto 0) => \NLW_vert_count_reg[12]_i_1_CO_UNCONNECTED\(3 downto 0), - CYINIT => '0', - DI(3 downto 0) => B"0000", - O(3 downto 1) => \NLW_vert_count_reg[12]_i_1_O_UNCONNECTED\(3 downto 1), - O(0) => \vert_count_reg[12]_i_1_n_7\, - S(3 downto 1) => B"000", - S(0) => \vert_count[12]_i_2_n_0\ +\sig_data_reg_out_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(28), + Q => m_axi_s2mm_wdata(28), + R => '0' ); -\vert_count_reg[1]\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \vert_count[0]_i_1_n_0\, - D => \vert_count_reg[0]_i_2_n_6\, - Q => vert_count_reg(1), - R => p_0_in + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(29), + Q => m_axi_s2mm_wdata(29), + R => '0' ); -\vert_count_reg[2]\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \vert_count[0]_i_1_n_0\, - D => \vert_count_reg[0]_i_2_n_5\, - Q => vert_count_reg(2), - R => p_0_in + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(2), + Q => m_axi_s2mm_wdata(2), + R => '0' ); -\vert_count_reg[3]\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \vert_count[0]_i_1_n_0\, - D => \vert_count_reg[0]_i_2_n_4\, - Q => vert_count_reg(3), - R => p_0_in + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(30), + Q => m_axi_s2mm_wdata(30), + R => '0' ); -\vert_count_reg[4]\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \vert_count[0]_i_1_n_0\, - D => \vert_count_reg[4]_i_1_n_7\, - Q => vert_count_reg(4), - R => p_0_in + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(31), + Q => m_axi_s2mm_wdata(31), + R => '0' ); -\vert_count_reg[4]_i_1\: unisim.vcomponents.CARRY4 - port map ( - CI => \vert_count_reg[0]_i_2_n_0\, - CO(3) => \vert_count_reg[4]_i_1_n_0\, - CO(2) => \vert_count_reg[4]_i_1_n_1\, - CO(1) => \vert_count_reg[4]_i_1_n_2\, - CO(0) => \vert_count_reg[4]_i_1_n_3\, - CYINIT => '0', - DI(3) => \vert_count[4]_i_2_n_0\, - DI(2) => \vert_count[4]_i_3_n_0\, - DI(1) => \vert_count[4]_i_4_n_0\, - DI(0) => \vert_count[4]_i_5_n_0\, - O(3) => \vert_count_reg[4]_i_1_n_4\, - O(2) => \vert_count_reg[4]_i_1_n_5\, - O(1) => \vert_count_reg[4]_i_1_n_6\, - O(0) => \vert_count_reg[4]_i_1_n_7\, - S(3) => \vert_count[4]_i_6_n_0\, - S(2) => \vert_count[4]_i_7_n_0\, - S(1) => \vert_count[4]_i_8_n_0\, - S(0) => \vert_count[4]_i_9_n_0\ +\sig_data_reg_out_reg[32]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(32), + Q => m_axi_s2mm_wdata(32), + R => '0' ); -\vert_count_reg[5]\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[33]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \vert_count[0]_i_1_n_0\, - D => \vert_count_reg[4]_i_1_n_6\, - Q => vert_count_reg(5), - R => p_0_in + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(33), + Q => m_axi_s2mm_wdata(33), + R => '0' ); -\vert_count_reg[6]\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[34]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \vert_count[0]_i_1_n_0\, - D => \vert_count_reg[4]_i_1_n_5\, - Q => vert_count_reg(6), - R => p_0_in + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(34), + Q => m_axi_s2mm_wdata(34), + R => '0' ); -\vert_count_reg[7]\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[35]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \vert_count[0]_i_1_n_0\, - D => \vert_count_reg[4]_i_1_n_4\, - Q => vert_count_reg(7), - R => p_0_in + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(35), + Q => m_axi_s2mm_wdata(35), + R => '0' ); -\vert_count_reg[8]\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[36]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \vert_count[0]_i_1_n_0\, - D => \vert_count_reg[8]_i_1_n_7\, - Q => vert_count_reg(8), - R => p_0_in + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(36), + Q => m_axi_s2mm_wdata(36), + R => '0' ); -\vert_count_reg[8]_i_1\: unisim.vcomponents.CARRY4 - port map ( - CI => \vert_count_reg[4]_i_1_n_0\, - CO(3) => \vert_count_reg[8]_i_1_n_0\, - CO(2) => \vert_count_reg[8]_i_1_n_1\, - CO(1) => \vert_count_reg[8]_i_1_n_2\, - CO(0) => \vert_count_reg[8]_i_1_n_3\, - CYINIT => '0', - DI(3) => \vert_count[8]_i_2_n_0\, - DI(2) => \vert_count[8]_i_3_n_0\, - DI(1) => \vert_count[8]_i_4_n_0\, - DI(0) => \vert_count[8]_i_5_n_0\, - O(3) => \vert_count_reg[8]_i_1_n_4\, - O(2) => \vert_count_reg[8]_i_1_n_5\, - O(1) => \vert_count_reg[8]_i_1_n_6\, - O(0) => \vert_count_reg[8]_i_1_n_7\, - S(3) => \vert_count[8]_i_6_n_0\, - S(2) => \vert_count[8]_i_7_n_0\, - S(1) => \vert_count[8]_i_8_n_0\, - S(0) => \vert_count[8]_i_9_n_0\ +\sig_data_reg_out_reg[37]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(37), + Q => m_axi_s2mm_wdata(37), + R => '0' ); -\vert_count_reg[9]\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[38]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \vert_count[0]_i_1_n_0\, - D => \vert_count_reg[8]_i_1_n_6\, - Q => vert_count_reg(9), - R => p_0_in + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(38), + Q => m_axi_s2mm_wdata(38), + R => '0' ); -zero_hsize_err_reg: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[39]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => zero_hsize_err0, - Q => \^zero_hsize_err\, - R => p_0_in + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(39), + Q => m_axi_s2mm_wdata(39), + R => '0' ); -zero_vsize_err_i_3: unisim.vcomponents.LUT6 +\sig_data_reg_out_reg[3]\: unisim.vcomponents.FDRE generic map( - INIT => X"0000001000000000" + INIT => '0' ) port map ( - I0 => dmacntrl_cs(0), - I1 => dmacntrl_cs(2), - I2 => dmacntrl_cs(1), - I3 => p_3_in, - I4 => \^frame_sync_reg\, - I5 => p_68_out(0), - O => \^load_new_addr\ + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(3), + Q => m_axi_s2mm_wdata(3), + R => '0' ); -zero_vsize_err_reg: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[40]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => zero_vsize_err0, - Q => \^zero_vsize_err\, - R => p_0_in + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(40), + Q => m_axi_s2mm_wdata(40), + R => '0' ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_sof_gen is - port ( - prmry_in_xored : out STD_LOGIC; - scndry_reset2 : in STD_LOGIC; - s_valid0 : in STD_LOGIC; - m_axis_mm2s_aclk : in STD_LOGIC; - p_in_d1_cdc_from : in STD_LOGIC; - \out\ : in STD_LOGIC; - p_15_out : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_sof_gen : entity is "axi_vdma_sof_gen"; -end Arty_Z7_20_axi_vdma_0_0_axi_vdma_sof_gen; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_sof_gen is - signal hold_sof : STD_LOGIC; - signal hold_sof_i_1_n_0 : STD_LOGIC; - signal s_valid : STD_LOGIC; - signal s_valid_d1 : STD_LOGIC; -begin -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__4\: unisim.vcomponents.LUT4 +\sig_data_reg_out_reg[41]\: unisim.vcomponents.FDRE generic map( - INIT => X"EF10" + INIT => '0' ) port map ( - I0 => hold_sof, - I1 => s_valid_d1, - I2 => s_valid, - I3 => p_in_d1_cdc_from, - O => prmry_in_xored + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(41), + Q => m_axi_s2mm_wdata(41), + R => '0' ); -hold_sof_i_1: unisim.vcomponents.LUT5 +\sig_data_reg_out_reg[42]\: unisim.vcomponents.FDRE generic map( - INIT => X"0000AE00" + INIT => '0' ) port map ( - I0 => hold_sof, - I1 => s_valid, - I2 => s_valid_d1, - I3 => \out\, - I4 => p_15_out, - O => hold_sof_i_1_n_0 + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(42), + Q => m_axi_s2mm_wdata(42), + R => '0' ); -hold_sof_reg: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[43]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => hold_sof_i_1_n_0, - Q => hold_sof, + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(43), + Q => m_axi_s2mm_wdata(43), R => '0' ); -s_valid_d1_reg: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[44]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => s_valid, - Q => s_valid_d1, - R => scndry_reset2 + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(44), + Q => m_axi_s2mm_wdata(44), + R => '0' ); -s_valid_reg: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[45]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => s_valid0, - Q => s_valid, - R => scndry_reset2 + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(45), + Q => m_axi_s2mm_wdata(45), + R => '0' ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_sts_mngr is - port ( - p_36_out : out STD_LOGIC; - datamover_idle : out STD_LOGIC; - halted_reg : out STD_LOGIC; - p_0_in : in STD_LOGIC; - \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\ : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - p_68_out : in STD_LOGIC_VECTOR ( 0 to 0 ); - \dmacr_i_reg[0]\ : in STD_LOGIC; - p_1_out : in STD_LOGIC; - p_37_out : in STD_LOGIC; - p_67_out : in STD_LOGIC; - \out\ : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_sts_mngr : entity is "axi_vdma_sts_mngr"; -end Arty_Z7_20_axi_vdma_0_0_axi_vdma_sts_mngr; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_sts_mngr is - signal \^datamover_idle\ : STD_LOGIC; - signal halted_set_i0 : STD_LOGIC; - signal p_26_out : STD_LOGIC; - signal p_27_out : STD_LOGIC; -begin - datamover_idle <= \^datamover_idle\; -all_idle_reg: unisim.vcomponents.FDSE - port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\, - Q => p_36_out, - S => p_0_in +\sig_data_reg_out_reg[46]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(46), + Q => m_axi_s2mm_wdata(46), + R => '0' ); -datamover_idle_reg: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[47]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \dmacr_i_reg[0]\, - Q => \^datamover_idle\, - R => p_0_in + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(47), + Q => m_axi_s2mm_wdata(47), + R => '0' ); -halted_clr_reg: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => p_68_out(0), - Q => p_26_out, - R => p_0_in +\sig_data_reg_out_reg[48]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(48), + Q => m_axi_s2mm_wdata(48), + R => '0' ); -halted_i_1: unisim.vcomponents.LUT4 +\sig_data_reg_out_reg[49]\: unisim.vcomponents.FDRE generic map( - INIT => X"FF4F" + INIT => '0' ) port map ( - I0 => p_26_out, - I1 => p_67_out, - I2 => \out\, - I3 => p_27_out, - O => halted_reg + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(49), + Q => m_axi_s2mm_wdata(49), + R => '0' ); -halted_set_i_i_1: unisim.vcomponents.LUT4 +\sig_data_reg_out_reg[4]\: unisim.vcomponents.FDRE generic map( - INIT => X"2000" + INIT => '0' ) port map ( - I0 => p_1_out, - I1 => p_68_out(0), - I2 => \^datamover_idle\, - I3 => p_37_out, - O => halted_set_i0 + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(4), + Q => m_axi_s2mm_wdata(4), + R => '0' ); -halted_set_i_reg: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[50]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => halted_set_i0, - Q => p_27_out, - R => p_0_in + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(50), + Q => m_axi_s2mm_wdata(50), + R => '0' ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_vregister is - port ( - zero_vsize_err0 : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 12 downto 0 ); - zero_hsize_err0 : out STD_LOGIC; - \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); - O : out STD_LOGIC_VECTOR ( 3 downto 0 ); - \dm_address_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); - \dm_address_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); - CO : out STD_LOGIC_VECTOR ( 0 to 0 ); - \dm_address_reg[15]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); - \dm_address_reg[31]\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); - load_new_addr : in STD_LOGIC; - p_23_out : in STD_LOGIC; - \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\ : in STD_LOGIC; - \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg\ : in STD_LOGIC; - \dm_address_reg[15]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); - p_0_in : in STD_LOGIC; - \reg_module_vsize_reg[12]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - \reg_module_hsize_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); - \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_vregister : entity is "axi_vdma_vregister"; -end Arty_Z7_20_axi_vdma_0_0_axi_vdma_vregister; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_vregister is - signal C : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal \^gen_normal_dm_command.cmnd_data_reg[15]\ : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal \^q\ : STD_LOGIC_VECTOR ( 12 downto 0 ); - signal \dm_address[0]_i_10_n_0\ : STD_LOGIC; - signal \dm_address[0]_i_3_n_0\ : STD_LOGIC; - signal \dm_address[0]_i_4_n_0\ : STD_LOGIC; - signal \dm_address[0]_i_5_n_0\ : STD_LOGIC; - signal \dm_address[0]_i_6_n_0\ : STD_LOGIC; - signal \dm_address[0]_i_7_n_0\ : STD_LOGIC; - signal \dm_address[0]_i_8_n_0\ : STD_LOGIC; - signal \dm_address[0]_i_9_n_0\ : STD_LOGIC; - signal \dm_address[12]_i_2_n_0\ : STD_LOGIC; - signal \dm_address[12]_i_3_n_0\ : STD_LOGIC; - signal \dm_address[12]_i_4_n_0\ : STD_LOGIC; - signal \dm_address[12]_i_5_n_0\ : STD_LOGIC; - signal \dm_address[12]_i_6_n_0\ : STD_LOGIC; - signal \dm_address[12]_i_7_n_0\ : STD_LOGIC; - signal \dm_address[12]_i_8_n_0\ : STD_LOGIC; - signal \dm_address[12]_i_9_n_0\ : STD_LOGIC; - signal \dm_address[4]_i_2_n_0\ : STD_LOGIC; - signal \dm_address[4]_i_3_n_0\ : STD_LOGIC; - signal \dm_address[4]_i_4_n_0\ : STD_LOGIC; - signal \dm_address[4]_i_5_n_0\ : STD_LOGIC; - signal \dm_address[4]_i_6_n_0\ : STD_LOGIC; - signal \dm_address[4]_i_7_n_0\ : STD_LOGIC; - signal \dm_address[4]_i_8_n_0\ : STD_LOGIC; - signal \dm_address[4]_i_9_n_0\ : STD_LOGIC; - signal \dm_address[8]_i_2_n_0\ : STD_LOGIC; - signal \dm_address[8]_i_3_n_0\ : STD_LOGIC; - signal \dm_address[8]_i_4_n_0\ : STD_LOGIC; - signal \dm_address[8]_i_5_n_0\ : STD_LOGIC; - signal \dm_address[8]_i_6_n_0\ : STD_LOGIC; - signal \dm_address[8]_i_7_n_0\ : STD_LOGIC; - signal \dm_address[8]_i_8_n_0\ : STD_LOGIC; - signal \dm_address[8]_i_9_n_0\ : STD_LOGIC; - signal \dm_address_reg[0]_i_2_n_0\ : STD_LOGIC; - signal \dm_address_reg[0]_i_2_n_1\ : STD_LOGIC; - signal \dm_address_reg[0]_i_2_n_2\ : STD_LOGIC; - signal \dm_address_reg[0]_i_2_n_3\ : STD_LOGIC; - signal \dm_address_reg[12]_i_1_n_1\ : STD_LOGIC; - signal \dm_address_reg[12]_i_1_n_2\ : STD_LOGIC; - signal \dm_address_reg[12]_i_1_n_3\ : STD_LOGIC; - signal \dm_address_reg[4]_i_1_n_0\ : STD_LOGIC; - signal \dm_address_reg[4]_i_1_n_1\ : STD_LOGIC; - signal \dm_address_reg[4]_i_1_n_2\ : STD_LOGIC; - signal \dm_address_reg[4]_i_1_n_3\ : STD_LOGIC; - signal \dm_address_reg[8]_i_1_n_0\ : STD_LOGIC; - signal \dm_address_reg[8]_i_1_n_1\ : STD_LOGIC; - signal \dm_address_reg[8]_i_1_n_2\ : STD_LOGIC; - signal \dm_address_reg[8]_i_1_n_3\ : STD_LOGIC; - signal stride_vid : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal video_reg_update : STD_LOGIC; - signal zero_hsize_err_i_2_n_0 : STD_LOGIC; - signal zero_hsize_err_i_3_n_0 : STD_LOGIC; - signal zero_hsize_err_i_4_n_0 : STD_LOGIC; - signal zero_hsize_err_i_5_n_0 : STD_LOGIC; - signal zero_vsize_err_i_2_n_0 : STD_LOGIC; - signal zero_vsize_err_i_4_n_0 : STD_LOGIC; - attribute METHODOLOGY_DRC_VIOS : string; - attribute METHODOLOGY_DRC_VIOS of \dm_address_reg[0]_i_2\ : label is "{SYNTH-8 {cell *THIS*}}"; - attribute METHODOLOGY_DRC_VIOS of \dm_address_reg[12]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; - attribute METHODOLOGY_DRC_VIOS of \dm_address_reg[4]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; - attribute METHODOLOGY_DRC_VIOS of \dm_address_reg[8]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; -begin - \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15]\(15 downto 0) <= \^gen_normal_dm_command.cmnd_data_reg[15]\(15 downto 0); - Q(12 downto 0) <= \^q\(12 downto 0); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][0]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(0), - Q => C(0), - R => p_0_in +\sig_data_reg_out_reg[51]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(51), + Q => m_axi_s2mm_wdata(51), + R => '0' ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][10]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(10), - Q => C(10), - R => p_0_in +\sig_data_reg_out_reg[52]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(52), + Q => m_axi_s2mm_wdata(52), + R => '0' ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][11]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(11), - Q => C(11), - R => p_0_in +\sig_data_reg_out_reg[53]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(53), + Q => m_axi_s2mm_wdata(53), + R => '0' ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][12]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(12), - Q => C(12), - R => p_0_in +\sig_data_reg_out_reg[54]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(54), + Q => m_axi_s2mm_wdata(54), + R => '0' ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][13]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(13), - Q => C(13), - R => p_0_in - ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][14]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(14), - Q => C(14), - R => p_0_in - ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][15]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(15), - Q => C(15), - R => p_0_in - ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][16]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(16), - Q => \dm_address_reg[31]\(0), - R => p_0_in - ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][17]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(17), - Q => \dm_address_reg[31]\(1), - R => p_0_in - ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][18]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(18), - Q => \dm_address_reg[31]\(2), - R => p_0_in - ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][19]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(19), - Q => \dm_address_reg[31]\(3), - R => p_0_in - ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][1]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(1), - Q => C(1), - R => p_0_in - ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][20]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(20), - Q => \dm_address_reg[31]\(4), - R => p_0_in - ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][21]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(21), - Q => \dm_address_reg[31]\(5), - R => p_0_in - ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][22]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(22), - Q => \dm_address_reg[31]\(6), - R => p_0_in - ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][23]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(23), - Q => \dm_address_reg[31]\(7), - R => p_0_in - ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][24]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(24), - Q => \dm_address_reg[31]\(8), - R => p_0_in - ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][25]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(25), - Q => \dm_address_reg[31]\(9), - R => p_0_in - ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][26]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(26), - Q => \dm_address_reg[31]\(10), - R => p_0_in - ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][27]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(27), - Q => \dm_address_reg[31]\(11), - R => p_0_in - ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][28]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(28), - Q => \dm_address_reg[31]\(12), - R => p_0_in - ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][29]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(29), - Q => \dm_address_reg[31]\(13), - R => p_0_in - ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][2]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(2), - Q => C(2), - R => p_0_in - ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][30]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(30), - Q => \dm_address_reg[31]\(14), - R => p_0_in - ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(31), - Q => \dm_address_reg[31]\(15), - R => p_0_in - ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][3]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(3), - Q => C(3), - R => p_0_in - ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][4]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(4), - Q => C(4), - R => p_0_in +\sig_data_reg_out_reg[55]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(55), + Q => m_axi_s2mm_wdata(55), + R => '0' ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][5]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(5), - Q => C(5), - R => p_0_in +\sig_data_reg_out_reg[56]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(56), + Q => m_axi_s2mm_wdata(56), + R => '0' ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][6]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(6), - Q => C(6), - R => p_0_in +\sig_data_reg_out_reg[57]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(57), + Q => m_axi_s2mm_wdata(57), + R => '0' ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][7]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(7), - Q => C(7), - R => p_0_in +\sig_data_reg_out_reg[58]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(58), + Q => m_axi_s2mm_wdata(58), + R => '0' ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][8]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(8), - Q => C(8), - R => p_0_in +\sig_data_reg_out_reg[59]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(59), + Q => m_axi_s2mm_wdata(59), + R => '0' ); -\GEN_START_ADDR_REG[0].start_address_vid_reg[0][9]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(9), - Q => C(9), - R => p_0_in +\sig_data_reg_out_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(5), + Q => m_axi_s2mm_wdata(5), + R => '0' ); -\dm_address[0]_i_10\: unisim.vcomponents.LUT4 +\sig_data_reg_out_reg[60]\: unisim.vcomponents.FDRE generic map( - INIT => X"F606" + INIT => '0' ) port map ( - I0 => stride_vid(0), - I1 => \dm_address_reg[15]_0\(0), - I2 => load_new_addr, - I3 => C(0), - O => \dm_address[0]_i_10_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(60), + Q => m_axi_s2mm_wdata(60), + R => '0' ); -\dm_address[0]_i_3\: unisim.vcomponents.LUT2 +\sig_data_reg_out_reg[61]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => stride_vid(3), - I1 => load_new_addr, - O => \dm_address[0]_i_3_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(61), + Q => m_axi_s2mm_wdata(61), + R => '0' ); -\dm_address[0]_i_4\: unisim.vcomponents.LUT2 +\sig_data_reg_out_reg[62]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => stride_vid(2), - I1 => load_new_addr, - O => \dm_address[0]_i_4_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(62), + Q => m_axi_s2mm_wdata(62), + R => '0' ); -\dm_address[0]_i_5\: unisim.vcomponents.LUT2 +\sig_data_reg_out_reg[63]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => stride_vid(1), - I1 => load_new_addr, - O => \dm_address[0]_i_5_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(63), + Q => m_axi_s2mm_wdata(63), + R => '0' ); -\dm_address[0]_i_6\: unisim.vcomponents.LUT2 +\sig_data_reg_out_reg[6]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => stride_vid(0), - I1 => load_new_addr, - O => \dm_address[0]_i_6_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(6), + Q => m_axi_s2mm_wdata(6), + R => '0' ); -\dm_address[0]_i_7\: unisim.vcomponents.LUT4 +\sig_data_reg_out_reg[7]\: unisim.vcomponents.FDRE generic map( - INIT => X"F606" + INIT => '0' ) port map ( - I0 => stride_vid(3), - I1 => \dm_address_reg[15]_0\(3), - I2 => load_new_addr, - I3 => C(3), - O => \dm_address[0]_i_7_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(7), + Q => m_axi_s2mm_wdata(7), + R => '0' ); -\dm_address[0]_i_8\: unisim.vcomponents.LUT4 +\sig_data_reg_out_reg[8]\: unisim.vcomponents.FDRE generic map( - INIT => X"F606" + INIT => '0' ) port map ( - I0 => stride_vid(2), - I1 => \dm_address_reg[15]_0\(2), - I2 => load_new_addr, - I3 => C(2), - O => \dm_address[0]_i_8_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(8), + Q => m_axi_s2mm_wdata(8), + R => '0' ); -\dm_address[0]_i_9\: unisim.vcomponents.LUT4 +\sig_data_reg_out_reg[9]\: unisim.vcomponents.FDRE generic map( - INIT => X"F606" + INIT => '0' ) port map ( - I0 => stride_vid(1), - I1 => \dm_address_reg[15]_0\(1), - I2 => load_new_addr, - I3 => C(1), - O => \dm_address[0]_i_9_n_0\ + C => m_axi_s2mm_aclk, + CE => \sig_data_reg_out[63]_i_1__0_n_0\, + D => sig_data_skid_mux_out(9), + Q => m_axi_s2mm_wdata(9), + R => '0' ); -\dm_address[12]_i_2\: unisim.vcomponents.LUT2 +\sig_data_skid_reg_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => stride_vid(15), - I1 => load_new_addr, - O => \dm_address[12]_i_2_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(0), + Q => sig_data_skid_reg(0), + R => '0' ); -\dm_address[12]_i_3\: unisim.vcomponents.LUT2 +\sig_data_skid_reg_reg[10]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => stride_vid(14), - I1 => load_new_addr, - O => \dm_address[12]_i_3_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(10), + Q => sig_data_skid_reg(10), + R => '0' ); -\dm_address[12]_i_4\: unisim.vcomponents.LUT2 +\sig_data_skid_reg_reg[11]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => stride_vid(13), - I1 => load_new_addr, - O => \dm_address[12]_i_4_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(11), + Q => sig_data_skid_reg(11), + R => '0' ); -\dm_address[12]_i_5\: unisim.vcomponents.LUT2 +\sig_data_skid_reg_reg[12]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => stride_vid(12), - I1 => load_new_addr, - O => \dm_address[12]_i_5_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(12), + Q => sig_data_skid_reg(12), + R => '0' ); -\dm_address[12]_i_6\: unisim.vcomponents.LUT4 +\sig_data_skid_reg_reg[13]\: unisim.vcomponents.FDRE generic map( - INIT => X"F606" + INIT => '0' ) port map ( - I0 => stride_vid(15), - I1 => \dm_address_reg[15]_0\(15), - I2 => load_new_addr, - I3 => C(15), - O => \dm_address[12]_i_6_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(13), + Q => sig_data_skid_reg(13), + R => '0' ); -\dm_address[12]_i_7\: unisim.vcomponents.LUT4 +\sig_data_skid_reg_reg[14]\: unisim.vcomponents.FDRE generic map( - INIT => X"F606" + INIT => '0' ) port map ( - I0 => stride_vid(14), - I1 => \dm_address_reg[15]_0\(14), - I2 => load_new_addr, - I3 => C(14), - O => \dm_address[12]_i_7_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(14), + Q => sig_data_skid_reg(14), + R => '0' ); -\dm_address[12]_i_8\: unisim.vcomponents.LUT4 +\sig_data_skid_reg_reg[15]\: unisim.vcomponents.FDRE generic map( - INIT => X"F606" + INIT => '0' ) port map ( - I0 => stride_vid(13), - I1 => \dm_address_reg[15]_0\(13), - I2 => load_new_addr, - I3 => C(13), - O => \dm_address[12]_i_8_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(15), + Q => sig_data_skid_reg(15), + R => '0' ); -\dm_address[12]_i_9\: unisim.vcomponents.LUT4 +\sig_data_skid_reg_reg[16]\: unisim.vcomponents.FDRE generic map( - INIT => X"F606" + INIT => '0' ) port map ( - I0 => stride_vid(12), - I1 => \dm_address_reg[15]_0\(12), - I2 => load_new_addr, - I3 => C(12), - O => \dm_address[12]_i_9_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(16), + Q => sig_data_skid_reg(16), + R => '0' ); -\dm_address[4]_i_2\: unisim.vcomponents.LUT2 +\sig_data_skid_reg_reg[17]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => stride_vid(7), - I1 => load_new_addr, - O => \dm_address[4]_i_2_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(17), + Q => sig_data_skid_reg(17), + R => '0' ); -\dm_address[4]_i_3\: unisim.vcomponents.LUT2 +\sig_data_skid_reg_reg[18]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => stride_vid(6), - I1 => load_new_addr, - O => \dm_address[4]_i_3_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(18), + Q => sig_data_skid_reg(18), + R => '0' ); -\dm_address[4]_i_4\: unisim.vcomponents.LUT2 +\sig_data_skid_reg_reg[19]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => stride_vid(5), - I1 => load_new_addr, - O => \dm_address[4]_i_4_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(19), + Q => sig_data_skid_reg(19), + R => '0' ); -\dm_address[4]_i_5\: unisim.vcomponents.LUT2 +\sig_data_skid_reg_reg[1]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => stride_vid(4), - I1 => load_new_addr, - O => \dm_address[4]_i_5_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(1), + Q => sig_data_skid_reg(1), + R => '0' ); -\dm_address[4]_i_6\: unisim.vcomponents.LUT4 +\sig_data_skid_reg_reg[20]\: unisim.vcomponents.FDRE generic map( - INIT => X"F606" + INIT => '0' ) port map ( - I0 => stride_vid(7), - I1 => \dm_address_reg[15]_0\(7), - I2 => load_new_addr, - I3 => C(7), - O => \dm_address[4]_i_6_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(20), + Q => sig_data_skid_reg(20), + R => '0' ); -\dm_address[4]_i_7\: unisim.vcomponents.LUT4 +\sig_data_skid_reg_reg[21]\: unisim.vcomponents.FDRE generic map( - INIT => X"F606" + INIT => '0' ) port map ( - I0 => stride_vid(6), - I1 => \dm_address_reg[15]_0\(6), - I2 => load_new_addr, - I3 => C(6), - O => \dm_address[4]_i_7_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(21), + Q => sig_data_skid_reg(21), + R => '0' ); -\dm_address[4]_i_8\: unisim.vcomponents.LUT4 +\sig_data_skid_reg_reg[22]\: unisim.vcomponents.FDRE generic map( - INIT => X"F606" + INIT => '0' ) port map ( - I0 => stride_vid(5), - I1 => \dm_address_reg[15]_0\(5), - I2 => load_new_addr, - I3 => C(5), - O => \dm_address[4]_i_8_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(22), + Q => sig_data_skid_reg(22), + R => '0' ); -\dm_address[4]_i_9\: unisim.vcomponents.LUT4 +\sig_data_skid_reg_reg[23]\: unisim.vcomponents.FDRE generic map( - INIT => X"F606" + INIT => '0' ) port map ( - I0 => stride_vid(4), - I1 => \dm_address_reg[15]_0\(4), - I2 => load_new_addr, - I3 => C(4), - O => \dm_address[4]_i_9_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(23), + Q => sig_data_skid_reg(23), + R => '0' ); -\dm_address[8]_i_2\: unisim.vcomponents.LUT2 +\sig_data_skid_reg_reg[24]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => stride_vid(11), - I1 => load_new_addr, - O => \dm_address[8]_i_2_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(24), + Q => sig_data_skid_reg(24), + R => '0' ); -\dm_address[8]_i_3\: unisim.vcomponents.LUT2 +\sig_data_skid_reg_reg[25]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => stride_vid(10), - I1 => load_new_addr, - O => \dm_address[8]_i_3_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(25), + Q => sig_data_skid_reg(25), + R => '0' ); -\dm_address[8]_i_4\: unisim.vcomponents.LUT2 +\sig_data_skid_reg_reg[26]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => stride_vid(9), - I1 => load_new_addr, - O => \dm_address[8]_i_4_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(26), + Q => sig_data_skid_reg(26), + R => '0' ); -\dm_address[8]_i_5\: unisim.vcomponents.LUT2 +\sig_data_skid_reg_reg[27]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => stride_vid(8), - I1 => load_new_addr, - O => \dm_address[8]_i_5_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(27), + Q => sig_data_skid_reg(27), + R => '0' ); -\dm_address[8]_i_6\: unisim.vcomponents.LUT4 +\sig_data_skid_reg_reg[28]\: unisim.vcomponents.FDRE generic map( - INIT => X"F606" + INIT => '0' ) port map ( - I0 => stride_vid(11), - I1 => \dm_address_reg[15]_0\(11), - I2 => load_new_addr, - I3 => C(11), - O => \dm_address[8]_i_6_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(28), + Q => sig_data_skid_reg(28), + R => '0' ); -\dm_address[8]_i_7\: unisim.vcomponents.LUT4 +\sig_data_skid_reg_reg[29]\: unisim.vcomponents.FDRE generic map( - INIT => X"F606" + INIT => '0' ) port map ( - I0 => stride_vid(10), - I1 => \dm_address_reg[15]_0\(10), - I2 => load_new_addr, - I3 => C(10), - O => \dm_address[8]_i_7_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(29), + Q => sig_data_skid_reg(29), + R => '0' ); -\dm_address[8]_i_8\: unisim.vcomponents.LUT4 +\sig_data_skid_reg_reg[2]\: unisim.vcomponents.FDRE generic map( - INIT => X"F606" + INIT => '0' ) port map ( - I0 => stride_vid(9), - I1 => \dm_address_reg[15]_0\(9), - I2 => load_new_addr, - I3 => C(9), - O => \dm_address[8]_i_8_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(2), + Q => sig_data_skid_reg(2), + R => '0' ); -\dm_address[8]_i_9\: unisim.vcomponents.LUT4 +\sig_data_skid_reg_reg[30]\: unisim.vcomponents.FDRE generic map( - INIT => X"F606" + INIT => '0' ) port map ( - I0 => stride_vid(8), - I1 => \dm_address_reg[15]_0\(8), - I2 => load_new_addr, - I3 => C(8), - O => \dm_address[8]_i_9_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(30), + Q => sig_data_skid_reg(30), + R => '0' ); -\dm_address_reg[0]_i_2\: unisim.vcomponents.CARRY4 - port map ( - CI => '0', - CO(3) => \dm_address_reg[0]_i_2_n_0\, - CO(2) => \dm_address_reg[0]_i_2_n_1\, - CO(1) => \dm_address_reg[0]_i_2_n_2\, - CO(0) => \dm_address_reg[0]_i_2_n_3\, - CYINIT => '0', - DI(3) => \dm_address[0]_i_3_n_0\, - DI(2) => \dm_address[0]_i_4_n_0\, - DI(1) => \dm_address[0]_i_5_n_0\, - DI(0) => \dm_address[0]_i_6_n_0\, - O(3 downto 0) => O(3 downto 0), - S(3) => \dm_address[0]_i_7_n_0\, - S(2) => \dm_address[0]_i_8_n_0\, - S(1) => \dm_address[0]_i_9_n_0\, - S(0) => \dm_address[0]_i_10_n_0\ - ); -\dm_address_reg[12]_i_1\: unisim.vcomponents.CARRY4 - port map ( - CI => \dm_address_reg[8]_i_1_n_0\, - CO(3) => CO(0), - CO(2) => \dm_address_reg[12]_i_1_n_1\, - CO(1) => \dm_address_reg[12]_i_1_n_2\, - CO(0) => \dm_address_reg[12]_i_1_n_3\, - CYINIT => '0', - DI(3) => \dm_address[12]_i_2_n_0\, - DI(2) => \dm_address[12]_i_3_n_0\, - DI(1) => \dm_address[12]_i_4_n_0\, - DI(0) => \dm_address[12]_i_5_n_0\, - O(3 downto 0) => \dm_address_reg[15]\(3 downto 0), - S(3) => \dm_address[12]_i_6_n_0\, - S(2) => \dm_address[12]_i_7_n_0\, - S(1) => \dm_address[12]_i_8_n_0\, - S(0) => \dm_address[12]_i_9_n_0\ - ); -\dm_address_reg[4]_i_1\: unisim.vcomponents.CARRY4 - port map ( - CI => \dm_address_reg[0]_i_2_n_0\, - CO(3) => \dm_address_reg[4]_i_1_n_0\, - CO(2) => \dm_address_reg[4]_i_1_n_1\, - CO(1) => \dm_address_reg[4]_i_1_n_2\, - CO(0) => \dm_address_reg[4]_i_1_n_3\, - CYINIT => '0', - DI(3) => \dm_address[4]_i_2_n_0\, - DI(2) => \dm_address[4]_i_3_n_0\, - DI(1) => \dm_address[4]_i_4_n_0\, - DI(0) => \dm_address[4]_i_5_n_0\, - O(3 downto 0) => \dm_address_reg[7]\(3 downto 0), - S(3) => \dm_address[4]_i_6_n_0\, - S(2) => \dm_address[4]_i_7_n_0\, - S(1) => \dm_address[4]_i_8_n_0\, - S(0) => \dm_address[4]_i_9_n_0\ - ); -\dm_address_reg[8]_i_1\: unisim.vcomponents.CARRY4 - port map ( - CI => \dm_address_reg[4]_i_1_n_0\, - CO(3) => \dm_address_reg[8]_i_1_n_0\, - CO(2) => \dm_address_reg[8]_i_1_n_1\, - CO(1) => \dm_address_reg[8]_i_1_n_2\, - CO(0) => \dm_address_reg[8]_i_1_n_3\, - CYINIT => '0', - DI(3) => \dm_address[8]_i_2_n_0\, - DI(2) => \dm_address[8]_i_3_n_0\, - DI(1) => \dm_address[8]_i_4_n_0\, - DI(0) => \dm_address[8]_i_5_n_0\, - O(3 downto 0) => \dm_address_reg[11]\(3 downto 0), - S(3) => \dm_address[8]_i_6_n_0\, - S(2) => \dm_address[8]_i_7_n_0\, - S(1) => \dm_address[8]_i_8_n_0\, - S(0) => \dm_address[8]_i_9_n_0\ - ); -\hsize_vid_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \reg_module_hsize_reg[15]\(0), - Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(0), - R => p_0_in - ); -\hsize_vid_reg[10]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \reg_module_hsize_reg[15]\(10), - Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(10), - R => p_0_in - ); -\hsize_vid_reg[11]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \reg_module_hsize_reg[15]\(11), - Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(11), - R => p_0_in - ); -\hsize_vid_reg[12]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \reg_module_hsize_reg[15]\(12), - Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(12), - R => p_0_in - ); -\hsize_vid_reg[13]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \reg_module_hsize_reg[15]\(13), - Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(13), - R => p_0_in - ); -\hsize_vid_reg[14]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \reg_module_hsize_reg[15]\(14), - Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(14), - R => p_0_in - ); -\hsize_vid_reg[15]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \reg_module_hsize_reg[15]\(15), - Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(15), - R => p_0_in - ); -\hsize_vid_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \reg_module_hsize_reg[15]\(1), - Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(1), - R => p_0_in - ); -\hsize_vid_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \reg_module_hsize_reg[15]\(2), - Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(2), - R => p_0_in - ); -\hsize_vid_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \reg_module_hsize_reg[15]\(3), - Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(3), - R => p_0_in - ); -\hsize_vid_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \reg_module_hsize_reg[15]\(4), - Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(4), - R => p_0_in - ); -\hsize_vid_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \reg_module_hsize_reg[15]\(5), - Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(5), - R => p_0_in - ); -\hsize_vid_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \reg_module_hsize_reg[15]\(6), - Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(6), - R => p_0_in - ); -\hsize_vid_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \reg_module_hsize_reg[15]\(7), - Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(7), - R => p_0_in - ); -\hsize_vid_reg[8]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \reg_module_hsize_reg[15]\(8), - Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(8), - R => p_0_in - ); -\hsize_vid_reg[9]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \reg_module_hsize_reg[15]\(9), - Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(9), - R => p_0_in - ); -\stride_vid_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(0), - Q => stride_vid(0), - R => p_0_in - ); -\stride_vid_reg[10]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(10), - Q => stride_vid(10), - R => p_0_in - ); -\stride_vid_reg[11]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(11), - Q => stride_vid(11), - R => p_0_in - ); -\stride_vid_reg[12]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(12), - Q => stride_vid(12), - R => p_0_in - ); -\stride_vid_reg[13]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(13), - Q => stride_vid(13), - R => p_0_in - ); -\stride_vid_reg[14]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(14), - Q => stride_vid(14), - R => p_0_in - ); -\stride_vid_reg[15]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(15), - Q => stride_vid(15), - R => p_0_in - ); -\stride_vid_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(1), - Q => stride_vid(1), - R => p_0_in - ); -\stride_vid_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(2), - Q => stride_vid(2), - R => p_0_in - ); -\stride_vid_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(3), - Q => stride_vid(3), - R => p_0_in - ); -\stride_vid_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(4), - Q => stride_vid(4), - R => p_0_in - ); -\stride_vid_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(5), - Q => stride_vid(5), - R => p_0_in - ); -\stride_vid_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(6), - Q => stride_vid(6), - R => p_0_in - ); -\stride_vid_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(7), - Q => stride_vid(7), - R => p_0_in - ); -\stride_vid_reg[8]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(8), - Q => stride_vid(8), - R => p_0_in - ); -\stride_vid_reg[9]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(9), - Q => stride_vid(9), - R => p_0_in - ); -\vsize_vid[12]_i_1\: unisim.vcomponents.LUT3 +\sig_data_skid_reg_reg[31]\: unisim.vcomponents.FDRE generic map( - INIT => X"B0" + INIT => '0' ) port map ( - I0 => p_23_out, - I1 => \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\, - I2 => \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg\, - O => video_reg_update - ); -\vsize_vid_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \reg_module_vsize_reg[12]\(0), - Q => \^q\(0), - R => p_0_in - ); -\vsize_vid_reg[10]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \reg_module_vsize_reg[12]\(10), - Q => \^q\(10), - R => p_0_in - ); -\vsize_vid_reg[11]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \reg_module_vsize_reg[12]\(11), - Q => \^q\(11), - R => p_0_in - ); -\vsize_vid_reg[12]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \reg_module_vsize_reg[12]\(12), - Q => \^q\(12), - R => p_0_in - ); -\vsize_vid_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \reg_module_vsize_reg[12]\(1), - Q => \^q\(1), - R => p_0_in + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(31), + Q => sig_data_skid_reg(31), + R => '0' ); -\vsize_vid_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \reg_module_vsize_reg[12]\(2), - Q => \^q\(2), - R => p_0_in +\sig_data_skid_reg_reg[32]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(32), + Q => sig_data_skid_reg(32), + R => '0' ); -\vsize_vid_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \reg_module_vsize_reg[12]\(3), - Q => \^q\(3), - R => p_0_in +\sig_data_skid_reg_reg[33]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(33), + Q => sig_data_skid_reg(33), + R => '0' ); -\vsize_vid_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \reg_module_vsize_reg[12]\(4), - Q => \^q\(4), - R => p_0_in +\sig_data_skid_reg_reg[34]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(34), + Q => sig_data_skid_reg(34), + R => '0' ); -\vsize_vid_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \reg_module_vsize_reg[12]\(5), - Q => \^q\(5), - R => p_0_in +\sig_data_skid_reg_reg[35]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(35), + Q => sig_data_skid_reg(35), + R => '0' ); -\vsize_vid_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \reg_module_vsize_reg[12]\(6), - Q => \^q\(6), - R => p_0_in +\sig_data_skid_reg_reg[36]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(36), + Q => sig_data_skid_reg(36), + R => '0' ); -\vsize_vid_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \reg_module_vsize_reg[12]\(7), - Q => \^q\(7), - R => p_0_in +\sig_data_skid_reg_reg[37]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(37), + Q => sig_data_skid_reg(37), + R => '0' ); -\vsize_vid_reg[8]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \reg_module_vsize_reg[12]\(8), - Q => \^q\(8), - R => p_0_in +\sig_data_skid_reg_reg[38]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(38), + Q => sig_data_skid_reg(38), + R => '0' ); -\vsize_vid_reg[9]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => video_reg_update, - D => \reg_module_vsize_reg[12]\(9), - Q => \^q\(9), - R => p_0_in +\sig_data_skid_reg_reg[39]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(39), + Q => sig_data_skid_reg(39), + R => '0' ); -zero_hsize_err_i_1: unisim.vcomponents.LUT3 +\sig_data_skid_reg_reg[3]\: unisim.vcomponents.FDRE generic map( - INIT => X"02" + INIT => '0' ) port map ( - I0 => load_new_addr, - I1 => zero_hsize_err_i_2_n_0, - I2 => zero_hsize_err_i_3_n_0, - O => zero_hsize_err0 + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(3), + Q => sig_data_skid_reg(3), + R => '0' ); -zero_hsize_err_i_2: unisim.vcomponents.LUT5 +\sig_data_skid_reg_reg[40]\: unisim.vcomponents.FDRE generic map( - INIT => X"FFFFFFFE" + INIT => '0' ) port map ( - I0 => \^gen_normal_dm_command.cmnd_data_reg[15]\(5), - I1 => \^gen_normal_dm_command.cmnd_data_reg[15]\(4), - I2 => \^gen_normal_dm_command.cmnd_data_reg[15]\(7), - I3 => \^gen_normal_dm_command.cmnd_data_reg[15]\(6), - I4 => zero_hsize_err_i_4_n_0, - O => zero_hsize_err_i_2_n_0 + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(40), + Q => sig_data_skid_reg(40), + R => '0' ); -zero_hsize_err_i_3: unisim.vcomponents.LUT5 +\sig_data_skid_reg_reg[41]\: unisim.vcomponents.FDRE generic map( - INIT => X"FFFFFFFE" + INIT => '0' ) port map ( - I0 => \^gen_normal_dm_command.cmnd_data_reg[15]\(13), - I1 => \^gen_normal_dm_command.cmnd_data_reg[15]\(12), - I2 => \^gen_normal_dm_command.cmnd_data_reg[15]\(14), - I3 => \^gen_normal_dm_command.cmnd_data_reg[15]\(15), - I4 => zero_hsize_err_i_5_n_0, - O => zero_hsize_err_i_3_n_0 + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(41), + Q => sig_data_skid_reg(41), + R => '0' ); -zero_hsize_err_i_4: unisim.vcomponents.LUT4 +\sig_data_skid_reg_reg[42]\: unisim.vcomponents.FDRE generic map( - INIT => X"FFFE" + INIT => '0' ) port map ( - I0 => \^gen_normal_dm_command.cmnd_data_reg[15]\(2), - I1 => \^gen_normal_dm_command.cmnd_data_reg[15]\(3), - I2 => \^gen_normal_dm_command.cmnd_data_reg[15]\(0), - I3 => \^gen_normal_dm_command.cmnd_data_reg[15]\(1), - O => zero_hsize_err_i_4_n_0 + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(42), + Q => sig_data_skid_reg(42), + R => '0' ); -zero_hsize_err_i_5: unisim.vcomponents.LUT4 +\sig_data_skid_reg_reg[43]\: unisim.vcomponents.FDRE generic map( - INIT => X"FFFE" + INIT => '0' ) port map ( - I0 => \^gen_normal_dm_command.cmnd_data_reg[15]\(10), - I1 => \^gen_normal_dm_command.cmnd_data_reg[15]\(11), - I2 => \^gen_normal_dm_command.cmnd_data_reg[15]\(8), - I3 => \^gen_normal_dm_command.cmnd_data_reg[15]\(9), - O => zero_hsize_err_i_5_n_0 + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(43), + Q => sig_data_skid_reg(43), + R => '0' ); -zero_vsize_err_i_1: unisim.vcomponents.LUT6 +\sig_data_skid_reg_reg[44]\: unisim.vcomponents.FDRE generic map( - INIT => X"0000000000000100" + INIT => '0' ) port map ( - I0 => zero_vsize_err_i_2_n_0, - I1 => \^q\(1), - I2 => \^q\(2), - I3 => load_new_addr, - I4 => \^q\(0), - I5 => zero_vsize_err_i_4_n_0, - O => zero_vsize_err0 + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(44), + Q => sig_data_skid_reg(44), + R => '0' ); -zero_vsize_err_i_2: unisim.vcomponents.LUT6 +\sig_data_skid_reg_reg[45]\: unisim.vcomponents.FDRE generic map( - INIT => X"FFFFFFFFFFFFFFFE" + INIT => '0' ) port map ( - I0 => \^q\(12), - I1 => \^q\(11), - I2 => \^q\(8), - I3 => \^q\(7), - I4 => \^q\(10), - I5 => \^q\(9), - O => zero_vsize_err_i_2_n_0 + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(45), + Q => sig_data_skid_reg(45), + R => '0' ); -zero_vsize_err_i_4: unisim.vcomponents.LUT4 +\sig_data_skid_reg_reg[46]\: unisim.vcomponents.FDRE generic map( - INIT => X"FFFE" + INIT => '0' ) port map ( - I0 => \^q\(5), - I1 => \^q\(6), - I2 => \^q\(3), - I3 => \^q\(4), - O => zero_vsize_err_i_4_n_0 + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(46), + Q => sig_data_skid_reg(46), + R => '0' ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_cdc_sync is - port ( - p_in_d1_cdc_from : out STD_LOGIC; - p_1_out : out STD_LOGIC; - SR : out STD_LOGIC_VECTOR ( 0 to 0 ); - prmry_in_xored : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - m_axis_mm2s_aclk : in STD_LOGIC; - p_3_out : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_cdc_sync : entity is "cdc_sync"; -end Arty_Z7_20_axi_vdma_0_0_cdc_sync; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_cdc_sync is - signal \^p_1_out\ : STD_LOGIC; - signal \^p_in_d1_cdc_from\ : STD_LOGIC; - signal s_out_d1_cdc_to : STD_LOGIC; - signal s_out_d2 : STD_LOGIC; - signal s_out_d3 : STD_LOGIC; - signal s_out_d4 : STD_LOGIC; - signal s_out_d5 : STD_LOGIC; - signal \s_out_re__0\ : STD_LOGIC; - signal srst_d1 : STD_LOGIC; - signal srst_d2 : STD_LOGIC; - signal srst_d3 : STD_LOGIC; - signal srst_d4 : STD_LOGIC; - signal srst_d5 : STD_LOGIC; - attribute ASYNC_REG : boolean; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM : string; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "FDR"; - attribute box_type : string; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "PRIMITIVE"; -begin - p_1_out <= \^p_1_out\; - p_in_d1_cdc_from <= \^p_in_d1_cdc_from\; -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[47]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => s_out_d1_cdc_to, - Q => s_out_d2, + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(47), + Q => sig_data_skid_reg(47), R => '0' ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[48]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => s_out_d2, - Q => s_out_d3, + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(48), + Q => sig_data_skid_reg(48), R => '0' ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[49]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => s_out_d3, - Q => s_out_d4, + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(49), + Q => sig_data_skid_reg(49), R => '0' ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => s_out_d4, - Q => s_out_d5, + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(4), + Q => sig_data_skid_reg(4), R => '0' ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[50]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => \s_out_re__0\, - Q => \^p_1_out\, + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(50), + Q => sig_data_skid_reg(50), R => '0' ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[51]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => \^p_in_d1_cdc_from\, - Q => s_out_d1_cdc_to, + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(51), + Q => sig_data_skid_reg(51), R => '0' ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[52]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => prmry_in_xored, - Q => \^p_in_d1_cdc_from\, + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(52), + Q => sig_data_skid_reg(52), R => '0' ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[53]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => '1', - Q => srst_d1, + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(53), + Q => sig_data_skid_reg(53), R => '0' ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[54]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => srst_d1, - Q => srst_d2, + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(54), + Q => sig_data_skid_reg(54), R => '0' ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[55]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => srst_d2, - Q => srst_d3, + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(55), + Q => sig_data_skid_reg(55), R => '0' ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[56]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => srst_d3, - Q => srst_d4, + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(56), + Q => sig_data_skid_reg(56), R => '0' ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[57]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => srst_d4, - Q => srst_d5, + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(57), + Q => sig_data_skid_reg(57), R => '0' ); -\GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_1\: unisim.vcomponents.LUT2 +\sig_data_skid_reg_reg[58]\: unisim.vcomponents.FDRE generic map( - INIT => X"E" + INIT => '0' ) port map ( - I0 => \^p_1_out\, - I1 => p_3_out, - O => SR(0) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(58), + Q => sig_data_skid_reg(58), + R => '0' ); -s_out_re: unisim.vcomponents.LUT3 +\sig_data_skid_reg_reg[59]\: unisim.vcomponents.FDRE generic map( - INIT => X"28" + INIT => '0' ) port map ( - I0 => srst_d5, - I1 => s_out_d5, - I2 => s_out_d4, - O => \s_out_re__0\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(59), + Q => sig_data_skid_reg(59), + R => '0' ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_cdc_sync_0 is - port ( - p_3_out : out STD_LOGIC; - \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_reg\ : out STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - m_axis_mm2s_aclk : in STD_LOGIC; - s_soft_reset_i_d1 : in STD_LOGIC; - s_soft_reset_i : in STD_LOGIC; - axis_min_assert_sftrst : in STD_LOGIC; - \GEN_MIN_FOR_ASYNC.axis_min_count_reg[2]\ : in STD_LOGIC; - p_1_out : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_cdc_sync_0 : entity is "cdc_sync"; -end Arty_Z7_20_axi_vdma_0_0_cdc_sync_0; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_cdc_sync_0 is - signal \^p_3_out\ : STD_LOGIC; - signal p_in_d1_cdc_from : STD_LOGIC; - signal prmry_in_xored : STD_LOGIC; - signal s_out_d1_cdc_to : STD_LOGIC; - signal s_out_d2 : STD_LOGIC; - signal s_out_d3 : STD_LOGIC; - signal s_out_d4 : STD_LOGIC; - signal s_out_d5 : STD_LOGIC; - signal \s_out_re__0\ : STD_LOGIC; - signal srst_d1 : STD_LOGIC; - signal srst_d2 : STD_LOGIC; - signal srst_d3 : STD_LOGIC; - signal srst_d4 : STD_LOGIC; - signal srst_d5 : STD_LOGIC; - attribute ASYNC_REG : boolean; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM : string; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "FDR"; - attribute box_type : string; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "PRIMITIVE"; -begin - p_3_out <= \^p_3_out\; -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => s_out_d1_cdc_to, - Q => s_out_d2, + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(5), + Q => sig_data_skid_reg(5), R => '0' ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[60]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => s_out_d2, - Q => s_out_d3, + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(60), + Q => sig_data_skid_reg(60), R => '0' ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[61]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => s_out_d3, - Q => s_out_d4, + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(61), + Q => sig_data_skid_reg(61), R => '0' ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[62]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => s_out_d4, - Q => s_out_d5, + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(62), + Q => sig_data_skid_reg(62), R => '0' ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[63]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => \s_out_re__0\, - Q => \^p_3_out\, + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(63), + Q => sig_data_skid_reg(63), R => '0' ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => p_in_d1_cdc_from, - Q => s_out_d1_cdc_to, + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(6), + Q => sig_data_skid_reg(6), R => '0' ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => prmry_in_xored, - Q => p_in_d1_cdc_from, + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(7), + Q => sig_data_skid_reg(7), R => '0' ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__1\: unisim.vcomponents.LUT3 +\sig_data_skid_reg_reg[8]\: unisim.vcomponents.FDRE generic map( - INIT => X"B4" + INIT => '0' ) port map ( - I0 => s_soft_reset_i_d1, - I1 => s_soft_reset_i, - I2 => p_in_d1_cdc_from, - O => prmry_in_xored + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(8), + Q => sig_data_skid_reg(8), + R => '0' ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => '1', - Q => srst_d1, + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => D(9), + Q => sig_data_skid_reg(9), R => '0' ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\: unisim.vcomponents.FDRE +sig_last_reg_out_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"8F80FFFF8F800000" + ) + port map ( + I0 => \sig_dbeat_cntr_eq_0__2\, + I1 => sig_dqual_reg_full, + I2 => sig_s_ready_dup, + I3 => sig_last_skid_reg, + I4 => \sig_data_reg_out[63]_i_1__0_n_0\, + I5 => \^m_axi_s2mm_wlast\, + O => sig_last_reg_out_i_2_n_0 + ); +sig_last_reg_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, + C => m_axi_s2mm_aclk, CE => '1', - D => srst_d1, - Q => srst_d2, - R => '0' + D => sig_last_reg_out_i_2_n_0, + Q => \^m_axi_s2mm_wlast\, + R => sig_stream_rst ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\: unisim.vcomponents.FDRE +sig_last_skid_reg_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"E2220000" + ) + port map ( + I0 => sig_last_skid_reg, + I1 => sig_s_ready_dup, + I2 => sig_dqual_reg_full, + I3 => \sig_dbeat_cntr_eq_0__2\, + I4 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + O => sig_last_skid_reg_i_1_n_0 + ); +sig_last_skid_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, + C => m_axi_s2mm_aclk, CE => '1', - D => srst_d2, - Q => srst_d3, + D => sig_last_skid_reg_i_1_n_0, + Q => sig_last_skid_reg, R => '0' ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\: unisim.vcomponents.FDRE +\sig_m_valid_dup_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4444444400404040" + ) + port map ( + I0 => sig_init_reg, + I1 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I2 => sig_m_valid_dup, + I3 => sig_s_ready_dup, + I4 => m_axi_s2mm_wready, + I5 => sig_data2skid_wvalid, + O => \sig_m_valid_dup_i_1__1_n_0\ + ); +sig_m_valid_dup_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, + C => m_axi_s2mm_aclk, CE => '1', - D => srst_d3, - Q => srst_d4, + D => \sig_m_valid_dup_i_1__1_n_0\, + Q => sig_m_valid_dup, R => '0' ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\: unisim.vcomponents.FDRE +sig_m_valid_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, + C => m_axi_s2mm_aclk, CE => '1', - D => srst_d4, - Q => srst_d5, + D => \sig_m_valid_dup_i_1__1_n_0\, + Q => sig_m_valid_out, R => '0' ); -\GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_1\: unisim.vcomponents.LUT4 +sig_s_ready_dup_i_1: unisim.vcomponents.LUT5 generic map( - INIT => X"00FE" + INIT => X"FFFFAEEE" ) port map ( - I0 => axis_min_assert_sftrst, - I1 => \GEN_MIN_FOR_ASYNC.axis_min_count_reg[2]\, - I2 => \^p_3_out\, - I3 => p_1_out, - O => \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_reg\ + I0 => sig_init_reg, + I1 => sig_s_ready_dup, + I2 => sig_m_valid_dup, + I3 => sig_data2skid_wvalid, + I4 => m_axi_s2mm_wready, + O => sig_s_ready_dup_i_1_n_0 ); -s_out_re: unisim.vcomponents.LUT3 +sig_s_ready_dup_reg: unisim.vcomponents.FDRE generic map( - INIT => X"28" + INIT => '0' ) port map ( - I0 => srst_d5, - I1 => s_out_d5, - I2 => s_out_d4, - O => \s_out_re__0\ + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_s_ready_dup_i_1_n_0, + Q => sig_s_ready_dup, + R => sig_stream_rst + ); +sig_s_ready_out_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_s_ready_dup_i_1_n_0, + Q => sig_s_ready_out, + R => sig_stream_rst ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_cdc_sync_1 is +entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_skid_buf is port ( - p_in_d1_cdc_from : out STD_LOGIC; - p_4_out : out STD_LOGIC; - SR : out STD_LOGIC_VECTOR ( 0 to 0 ); - prmry_in_xored : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - s_axi_lite_aclk : in STD_LOGIC; - p_6_out : in STD_LOGIC + \out\ : out STD_LOGIC; + \gpregsm1.user_valid_reg\ : out STD_LOGIC; + \GEN_INDET_BTT.lsig_eop_reg_reg\ : out STD_LOGIC; + sig_ibtt2wdc_tlast : out STD_LOGIC; + \GEN_INDET_BTT.lsig_byte_cntr_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_INDET_BTT.lsig_byte_cntr_reg[6]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_INDET_BTT.lsig_byte_cntr_reg[3]\ : out STD_LOGIC_VECTOR ( 64 downto 0 ); + \GEN_INDET_BTT.lsig_eop_reg_reg_0\ : out STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + sig_data_fifo_data_out : in STD_LOGIC_VECTOR ( 65 downto 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_wdc2ibtt_tready : in STD_LOGIC; + lsig_end_of_cmd_reg : in STD_LOGIC; + lsig_eop_reg : in STD_LOGIC; + sig_init_reg : in STD_LOGIC; + hold_ff_q : in STD_LOGIC; + \gpregsm1.user_valid_reg_0\ : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_data_fifo_dvalid : in STD_LOGIC ); attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_cdc_sync_1 : entity is "cdc_sync"; -end Arty_Z7_20_axi_vdma_0_0_cdc_sync_1; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_skid_buf : entity is "axi_datamover_skid_buf"; +end Arty_Z7_20_axi_vdma_0_0_axi_datamover_skid_buf; -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_cdc_sync_1 is - signal \^p_4_out\ : STD_LOGIC; - signal \^p_in_d1_cdc_from\ : STD_LOGIC; - signal s_out_d1_cdc_to : STD_LOGIC; - signal s_out_d2 : STD_LOGIC; - signal s_out_d3 : STD_LOGIC; - signal s_out_d4 : STD_LOGIC; - signal s_out_d5 : STD_LOGIC; - signal \s_out_re__0\ : STD_LOGIC; - signal srst_d1 : STD_LOGIC; - signal srst_d2 : STD_LOGIC; - signal srst_d3 : STD_LOGIC; - signal srst_d4 : STD_LOGIC; - signal srst_d5 : STD_LOGIC; - attribute ASYNC_REG : boolean; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM : string; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "FDR"; - attribute box_type : string; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "PRIMITIVE"; +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_skid_buf is + signal \^gen_indet_btt.lsig_byte_cntr_reg[3]\ : STD_LOGIC_VECTOR ( 64 downto 0 ); + signal \sig_data_reg_out[67]_i_2_n_0\ : STD_LOGIC; + signal sig_data_skid_mux_out : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal sig_data_skid_reg : STD_LOGIC_VECTOR ( 67 downto 0 ); + signal sig_ibtt2wdc_eop : STD_LOGIC; + signal sig_last_skid_mux_out : STD_LOGIC; + signal sig_last_skid_reg : STD_LOGIC; + signal sig_m_valid_dup : STD_LOGIC; + attribute RTL_KEEP : string; + attribute RTL_KEEP of sig_m_valid_dup : signal is "true"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of sig_m_valid_dup : signal is "no"; + signal \sig_m_valid_dup_i_1__0_n_0\ : STD_LOGIC; + signal sig_m_valid_out : STD_LOGIC; + attribute RTL_KEEP of sig_m_valid_out : signal is "true"; + attribute equivalent_register_removal of sig_m_valid_out : signal is "no"; + signal sig_s_ready_dup : STD_LOGIC; + attribute RTL_KEEP of sig_s_ready_dup : signal is "true"; + attribute equivalent_register_removal of sig_s_ready_dup : signal is "no"; + signal \sig_s_ready_dup_i_1__1_n_0\ : STD_LOGIC; + signal sig_s_ready_out : STD_LOGIC; + attribute RTL_KEEP of sig_s_ready_out : signal is "true"; + attribute equivalent_register_removal of sig_s_ready_out : signal is "no"; + signal sig_strb_skid_mux_out : STD_LOGIC_VECTOR ( 8 to 8 ); + signal sig_strb_skid_reg : STD_LOGIC_VECTOR ( 8 to 8 ); + attribute KEEP : string; + attribute KEEP of sig_m_valid_dup_reg : label is "yes"; + attribute equivalent_register_removal of sig_m_valid_dup_reg : label is "no"; + attribute KEEP of sig_m_valid_out_reg : label is "yes"; + attribute equivalent_register_removal of sig_m_valid_out_reg : label is "no"; + attribute KEEP of sig_s_ready_dup_reg : label is "yes"; + attribute equivalent_register_removal of sig_s_ready_dup_reg : label is "no"; + attribute KEEP of sig_s_ready_out_reg : label is "yes"; + attribute equivalent_register_removal of sig_s_ready_out_reg : label is "no"; begin - p_4_out <= \^p_4_out\; - p_in_d1_cdc_from <= \^p_in_d1_cdc_from\; -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\: unisim.vcomponents.FDRE + \GEN_INDET_BTT.lsig_byte_cntr_reg[3]\(64 downto 0) <= \^gen_indet_btt.lsig_byte_cntr_reg[3]\(64 downto 0); + \GEN_INDET_BTT.lsig_eop_reg_reg\ <= sig_m_valid_out; + \gpregsm1.user_valid_reg\ <= sig_s_ready_out; + \out\ <= sig_m_valid_dup; +\GEN_INDET_BTT.lsig_byte_cntr[15]_i_2\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_out_d1_cdc_to, - Q => s_out_d2, - R => '0' + I0 => sig_m_valid_out, + I1 => sig_wdc2ibtt_tready, + O => \GEN_INDET_BTT.lsig_byte_cntr_reg[15]\(0) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\: unisim.vcomponents.FDRE +\GEN_INDET_BTT.lsig_byte_cntr[6]_i_2\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"70F0" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_out_d2, - Q => s_out_d3, - R => '0' + I0 => sig_m_valid_out, + I1 => sig_wdc2ibtt_tready, + I2 => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(64), + I3 => lsig_end_of_cmd_reg, + O => \GEN_INDET_BTT.lsig_byte_cntr_reg[6]\(0) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\: unisim.vcomponents.FDRE +\GEN_INDET_BTT.lsig_eop_reg_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"F780" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_out_d3, - Q => s_out_d4, - R => '0' + I0 => sig_m_valid_out, + I1 => sig_wdc2ibtt_tready, + I2 => sig_ibtt2wdc_eop, + I3 => lsig_eop_reg, + O => \GEN_INDET_BTT.lsig_eop_reg_reg_0\ ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\: unisim.vcomponents.FDRE +\sig_data_reg_out[0]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_out_d4, - Q => s_out_d5, - R => '0' + I0 => sig_data_skid_reg(0), + I1 => sig_data_fifo_data_out(0), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(0) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\: unisim.vcomponents.FDRE +\sig_data_reg_out[10]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => \s_out_re__0\, - Q => \^p_4_out\, - R => '0' + I0 => sig_data_skid_reg(10), + I1 => sig_data_fifo_data_out(10), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(10) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\: unisim.vcomponents.FDRE +\sig_data_reg_out[11]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => \^p_in_d1_cdc_from\, - Q => s_out_d1_cdc_to, - R => '0' + I0 => sig_data_skid_reg(11), + I1 => sig_data_fifo_data_out(11), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(11) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\: unisim.vcomponents.FDRE +\sig_data_reg_out[12]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => prmry_in_xored, - Q => \^p_in_d1_cdc_from\, - R => '0' + I0 => sig_data_skid_reg(12), + I1 => sig_data_fifo_data_out(12), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(12) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\: unisim.vcomponents.FDRE +\sig_data_reg_out[13]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => '1', - Q => srst_d1, - R => '0' + I0 => sig_data_skid_reg(13), + I1 => sig_data_fifo_data_out(13), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(13) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\: unisim.vcomponents.FDRE +\sig_data_reg_out[14]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => srst_d1, - Q => srst_d2, - R => '0' + I0 => sig_data_skid_reg(14), + I1 => sig_data_fifo_data_out(14), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(14) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\: unisim.vcomponents.FDRE +\sig_data_reg_out[15]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => srst_d2, - Q => srst_d3, - R => '0' + I0 => sig_data_skid_reg(15), + I1 => sig_data_fifo_data_out(15), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(15) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\: unisim.vcomponents.FDRE +\sig_data_reg_out[16]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => srst_d3, - Q => srst_d4, - R => '0' + I0 => sig_data_skid_reg(16), + I1 => sig_data_fifo_data_out(16), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(16) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\: unisim.vcomponents.FDRE +\sig_data_reg_out[17]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => srst_d4, - Q => srst_d5, - R => '0' + I0 => sig_data_skid_reg(17), + I1 => sig_data_fifo_data_out(17), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(17) ); -\GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out[18]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => X"E" + INIT => X"CA" ) port map ( - I0 => \^p_4_out\, - I1 => p_6_out, - O => SR(0) + I0 => sig_data_skid_reg(18), + I1 => sig_data_fifo_data_out(18), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(18) ); -s_out_re: unisim.vcomponents.LUT3 +\sig_data_reg_out[19]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => X"28" + INIT => X"CA" ) port map ( - I0 => srst_d5, - I1 => s_out_d5, - I2 => s_out_d4, - O => \s_out_re__0\ + I0 => sig_data_skid_reg(19), + I1 => sig_data_fifo_data_out(19), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(19) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_cdc_sync_2 is - port ( - p_6_out : out STD_LOGIC; - \GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_reg\ : out STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - s_axi_lite_aclk : in STD_LOGIC; - s_soft_reset_i_d1 : in STD_LOGIC; - s_soft_reset_i : in STD_LOGIC; - lite_min_assert_sftrst : in STD_LOGIC; - p_8_out_0 : in STD_LOGIC; - p_4_out : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_cdc_sync_2 : entity is "cdc_sync"; -end Arty_Z7_20_axi_vdma_0_0_cdc_sync_2; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_cdc_sync_2 is - signal \^p_6_out\ : STD_LOGIC; - signal p_in_d1_cdc_from : STD_LOGIC; - signal prmry_in_xored : STD_LOGIC; - signal s_out_d1_cdc_to : STD_LOGIC; - signal s_out_d2 : STD_LOGIC; - signal s_out_d3 : STD_LOGIC; - signal s_out_d4 : STD_LOGIC; - signal s_out_d5 : STD_LOGIC; - signal \s_out_re__0\ : STD_LOGIC; - signal srst_d1 : STD_LOGIC; - signal srst_d2 : STD_LOGIC; - signal srst_d3 : STD_LOGIC; - signal srst_d4 : STD_LOGIC; - signal srst_d5 : STD_LOGIC; - attribute ASYNC_REG : boolean; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM : string; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "FDR"; - attribute box_type : string; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "PRIMITIVE"; -begin - p_6_out <= \^p_6_out\; -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\: unisim.vcomponents.FDRE +\sig_data_reg_out[1]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_out_d1_cdc_to, - Q => s_out_d2, - R => '0' + I0 => sig_data_skid_reg(1), + I1 => sig_data_fifo_data_out(1), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(1) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\: unisim.vcomponents.FDRE +\sig_data_reg_out[20]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_out_d2, - Q => s_out_d3, - R => '0' + I0 => sig_data_skid_reg(20), + I1 => sig_data_fifo_data_out(20), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(20) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\: unisim.vcomponents.FDRE +\sig_data_reg_out[21]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_out_d3, - Q => s_out_d4, - R => '0' + I0 => sig_data_skid_reg(21), + I1 => sig_data_fifo_data_out(21), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(21) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\: unisim.vcomponents.FDRE +\sig_data_reg_out[22]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_out_d4, - Q => s_out_d5, - R => '0' + I0 => sig_data_skid_reg(22), + I1 => sig_data_fifo_data_out(22), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(22) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\: unisim.vcomponents.FDRE +\sig_data_reg_out[23]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => \s_out_re__0\, - Q => \^p_6_out\, - R => '0' + I0 => sig_data_skid_reg(23), + I1 => sig_data_fifo_data_out(23), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(23) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\: unisim.vcomponents.FDRE +\sig_data_reg_out[24]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => p_in_d1_cdc_from, - Q => s_out_d1_cdc_to, - R => '0' + I0 => sig_data_skid_reg(24), + I1 => sig_data_fifo_data_out(24), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(24) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\: unisim.vcomponents.FDRE +\sig_data_reg_out[25]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => prmry_in_xored, - Q => p_in_d1_cdc_from, - R => '0' + I0 => sig_data_skid_reg(25), + I1 => sig_data_fifo_data_out(25), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(25) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1\: unisim.vcomponents.LUT3 +\sig_data_reg_out[26]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => X"B4" + INIT => X"CA" ) port map ( - I0 => s_soft_reset_i_d1, - I1 => s_soft_reset_i, - I2 => p_in_d1_cdc_from, - O => prmry_in_xored + I0 => sig_data_skid_reg(26), + I1 => sig_data_fifo_data_out(26), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(26) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\: unisim.vcomponents.FDRE +\sig_data_reg_out[27]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => '1', - Q => srst_d1, - R => '0' + I0 => sig_data_skid_reg(27), + I1 => sig_data_fifo_data_out(27), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(27) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\: unisim.vcomponents.FDRE +\sig_data_reg_out[28]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => srst_d1, - Q => srst_d2, - R => '0' + I0 => sig_data_skid_reg(28), + I1 => sig_data_fifo_data_out(28), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(28) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\: unisim.vcomponents.FDRE +\sig_data_reg_out[29]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => srst_d2, - Q => srst_d3, - R => '0' + I0 => sig_data_skid_reg(29), + I1 => sig_data_fifo_data_out(29), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(29) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\: unisim.vcomponents.FDRE +\sig_data_reg_out[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => srst_d3, - Q => srst_d4, - R => '0' + I0 => sig_data_skid_reg(2), + I1 => sig_data_fifo_data_out(2), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(2) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\: unisim.vcomponents.FDRE +\sig_data_reg_out[30]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => srst_d4, - Q => srst_d5, - R => '0' + I0 => sig_data_skid_reg(30), + I1 => sig_data_fifo_data_out(30), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(30) ); -\GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_i_1\: unisim.vcomponents.LUT4 +\sig_data_reg_out[31]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => X"00FE" + INIT => X"CA" ) port map ( - I0 => lite_min_assert_sftrst, - I1 => p_8_out_0, - I2 => \^p_6_out\, - I3 => p_4_out, - O => \GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_reg\ + I0 => sig_data_skid_reg(31), + I1 => sig_data_fifo_data_out(31), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(31) ); -s_out_re: unisim.vcomponents.LUT3 +\sig_data_reg_out[32]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => X"28" + INIT => X"CA" ) port map ( - I0 => srst_d5, - I1 => s_out_d5, - I2 => s_out_d4, - O => \s_out_re__0\ + I0 => sig_data_skid_reg(32), + I1 => sig_data_fifo_data_out(32), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(32) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized0\ is - port ( - scndry_out : out STD_LOGIC; - s_axi_lite_aclk : in STD_LOGIC; - \FSM_sequential_dmacntrl_cs_reg[1]\ : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized0\ : entity is "cdc_sync"; -end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized0\; - -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized0\ is - signal p_level_in_d1_cdc_from : STD_LOGIC; - signal s_level_out_d1_cdc_to : STD_LOGIC; - signal s_level_out_d2 : STD_LOGIC; - signal s_level_out_d3 : STD_LOGIC; - attribute ASYNC_REG : boolean; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM : string; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; - attribute box_type : string; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; -begin -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE +\sig_data_reg_out[33]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => p_level_in_d1_cdc_from, - Q => s_level_out_d1_cdc_to, - R => '0' + I0 => sig_data_skid_reg(33), + I1 => sig_data_fifo_data_out(33), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(33) ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE +\sig_data_reg_out[34]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_level_out_d1_cdc_to, - Q => s_level_out_d2, - R => '0' + I0 => sig_data_skid_reg(34), + I1 => sig_data_fifo_data_out(34), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(34) ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE +\sig_data_reg_out[35]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_level_out_d2, - Q => s_level_out_d3, - R => '0' + I0 => sig_data_skid_reg(35), + I1 => sig_data_fifo_data_out(35), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(35) ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE +\sig_data_reg_out[36]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_level_out_d3, - Q => scndry_out, - R => '0' + I0 => sig_data_skid_reg(36), + I1 => sig_data_fifo_data_out(36), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(36) ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE +\sig_data_reg_out[37]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \FSM_sequential_dmacntrl_cs_reg[1]\, - Q => p_level_in_d1_cdc_from, - R => '0' + I0 => sig_data_skid_reg(37), + I1 => sig_data_fifo_data_out(37), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(37) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized1\ is - port ( - prmry_in_xored : out STD_LOGIC; - prmry_in_xored_0 : out STD_LOGIC; - SR : out STD_LOGIC_VECTOR ( 0 to 0 ); - \GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_reg\ : out STD_LOGIC; - \GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_reg\ : out STD_LOGIC; - prmry_min_assert_sftrst : in STD_LOGIC; - scndry_out : in STD_LOGIC; - p_in_d1_cdc_from : in STD_LOGIC; - p_in_d1_cdc_from_1 : in STD_LOGIC; - s_soft_reset_i_d1 : in STD_LOGIC; - s_soft_reset_i : in STD_LOGIC; - min_assert_sftrst : in STD_LOGIC; - p_11_out : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - lite_min_assert_sftrst : in STD_LOGIC; - s_axi_lite_aclk : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized1\ : entity is "cdc_sync"; -end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized1\; - -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized1\ is - signal p_5_out : STD_LOGIC; - signal p_level_in_d1_cdc_from : STD_LOGIC; - signal s_level_out_d1_cdc_to : STD_LOGIC; - signal s_level_out_d2 : STD_LOGIC; - signal s_level_out_d3 : STD_LOGIC; - attribute ASYNC_REG : boolean; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM : string; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; - attribute box_type : string; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__0\ : label is "soft_lutpair113"; - attribute SOFT_HLUTNM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__2\ : label is "soft_lutpair113"; -begin -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE +\sig_data_reg_out[38]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => p_level_in_d1_cdc_from, - Q => s_level_out_d1_cdc_to, - R => '0' + I0 => sig_data_skid_reg(38), + I1 => sig_data_fifo_data_out(38), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(38) ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE +\sig_data_reg_out[39]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => s_level_out_d1_cdc_to, - Q => s_level_out_d2, - R => '0' + I0 => sig_data_skid_reg(39), + I1 => sig_data_fifo_data_out(39), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(39) ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE +\sig_data_reg_out[3]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => s_level_out_d2, - Q => s_level_out_d3, - R => '0' + I0 => sig_data_skid_reg(3), + I1 => sig_data_fifo_data_out(3), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(3) ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE +\sig_data_reg_out[40]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => s_level_out_d3, - Q => p_5_out, - R => '0' + I0 => sig_data_skid_reg(40), + I1 => sig_data_fifo_data_out(40), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(40) ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE +\sig_data_reg_out[41]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => lite_min_assert_sftrst, - Q => p_level_in_d1_cdc_from, - R => '0' + I0 => sig_data_skid_reg(41), + I1 => sig_data_fifo_data_out(41), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(41) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__0\: unisim.vcomponents.LUT4 +\sig_data_reg_out[42]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => X"7F80" + INIT => X"CA" ) port map ( - I0 => p_5_out, - I1 => prmry_min_assert_sftrst, - I2 => scndry_out, - I3 => p_in_d1_cdc_from, - O => prmry_in_xored + I0 => sig_data_skid_reg(42), + I1 => sig_data_fifo_data_out(42), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(42) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__2\: unisim.vcomponents.LUT4 +\sig_data_reg_out[43]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => X"7F80" + INIT => X"CA" ) port map ( - I0 => p_5_out, - I1 => prmry_min_assert_sftrst, - I2 => scndry_out, - I3 => p_in_d1_cdc_from_1, - O => prmry_in_xored_0 + I0 => sig_data_skid_reg(43), + I1 => sig_data_fifo_data_out(43), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(43) ); -\GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_i_1\: unisim.vcomponents.LUT6 +\sig_data_reg_out[44]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => X"F0E0FFFFF0E0F0E0" + INIT => X"CA" ) port map ( - I0 => prmry_min_assert_sftrst, - I1 => p_5_out, - I2 => min_assert_sftrst, - I3 => scndry_out, - I4 => s_soft_reset_i_d1, - I5 => s_soft_reset_i, - O => \GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_reg\ + I0 => sig_data_skid_reg(44), + I1 => sig_data_fifo_data_out(44), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(44) ); -\GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_i_1\: unisim.vcomponents.LUT6 +\sig_data_reg_out[45]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => X"00FFF2F2FFFFF2F2" + INIT => X"CA" ) port map ( - I0 => s_soft_reset_i, - I1 => s_soft_reset_i_d1, - I2 => p_11_out, - I3 => p_5_out, - I4 => prmry_min_assert_sftrst, - I5 => scndry_out, - O => \GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_reg\ + I0 => sig_data_skid_reg(45), + I1 => sig_data_fifo_data_out(45), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(45) ); -\GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_1\: unisim.vcomponents.LUT5 +\sig_data_reg_out[46]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => X"80FF8080" + INIT => X"CA" ) port map ( - I0 => p_5_out, - I1 => prmry_min_assert_sftrst, - I2 => scndry_out, - I3 => s_soft_reset_i_d1, - I4 => s_soft_reset_i, - O => SR(0) + I0 => sig_data_skid_reg(46), + I1 => sig_data_fifo_data_out(46), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(46) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized10\ is - port ( - p_in_d1_cdc_from : out STD_LOGIC; - p_17_out : out STD_LOGIC; - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - prmry_in_xored : in STD_LOGIC; - m_axis_mm2s_aclk : in STD_LOGIC; - prmry_resetn_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_mm2s_aclk : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized10\ : entity is "cdc_sync"; -end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized10\; - -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized10\ is - signal \^p_in_d1_cdc_from\ : STD_LOGIC; - signal s_out_d1_cdc_to : STD_LOGIC; - signal s_out_d2 : STD_LOGIC; - signal s_out_d3 : STD_LOGIC; - signal s_out_d4 : STD_LOGIC; - signal s_out_d5 : STD_LOGIC; - signal \s_out_re__0\ : STD_LOGIC; - signal srst_d1 : STD_LOGIC; - signal srst_d2 : STD_LOGIC; - signal srst_d3 : STD_LOGIC; - signal srst_d4 : STD_LOGIC; - signal srst_d5 : STD_LOGIC; - attribute ASYNC_REG : boolean; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM : string; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "FDR"; - attribute box_type : string; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "PRIMITIVE"; -begin - p_in_d1_cdc_from <= \^p_in_d1_cdc_from\; -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\: unisim.vcomponents.FDRE +\sig_data_reg_out[47]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => s_out_d1_cdc_to, - Q => s_out_d2, - R => prmry_resetn_i_reg(0) + I0 => sig_data_skid_reg(47), + I1 => sig_data_fifo_data_out(47), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(47) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\: unisim.vcomponents.FDRE +\sig_data_reg_out[48]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => s_out_d2, - Q => s_out_d3, - R => prmry_resetn_i_reg(0) + I0 => sig_data_skid_reg(48), + I1 => sig_data_fifo_data_out(48), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(48) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\: unisim.vcomponents.FDRE +\sig_data_reg_out[49]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => s_out_d3, - Q => s_out_d4, - R => prmry_resetn_i_reg(0) + I0 => sig_data_skid_reg(49), + I1 => sig_data_fifo_data_out(49), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(49) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\: unisim.vcomponents.FDRE +\sig_data_reg_out[4]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => s_out_d4, - Q => s_out_d5, - R => prmry_resetn_i_reg(0) + I0 => sig_data_skid_reg(4), + I1 => sig_data_fifo_data_out(4), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(4) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\: unisim.vcomponents.FDRE +\sig_data_reg_out[50]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \s_out_re__0\, - Q => p_17_out, - R => prmry_resetn_i_reg(0) + I0 => sig_data_skid_reg(50), + I1 => sig_data_fifo_data_out(50), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(50) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\: unisim.vcomponents.FDRE +\sig_data_reg_out[51]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \^p_in_d1_cdc_from\, - Q => s_out_d1_cdc_to, - R => prmry_resetn_i_reg(0) + I0 => sig_data_skid_reg(51), + I1 => sig_data_fifo_data_out(51), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(51) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\: unisim.vcomponents.FDRE +\sig_data_reg_out[52]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => prmry_in_xored, - Q => \^p_in_d1_cdc_from\, - R => SR(0) + I0 => sig_data_skid_reg(52), + I1 => sig_data_fifo_data_out(52), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(52) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\: unisim.vcomponents.FDRE +\sig_data_reg_out[53]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => '1', - Q => srst_d1, - R => prmry_resetn_i_reg(0) + I0 => sig_data_skid_reg(53), + I1 => sig_data_fifo_data_out(53), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(53) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\: unisim.vcomponents.FDRE +\sig_data_reg_out[54]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => srst_d1, - Q => srst_d2, - R => prmry_resetn_i_reg(0) + I0 => sig_data_skid_reg(54), + I1 => sig_data_fifo_data_out(54), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(54) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\: unisim.vcomponents.FDRE +\sig_data_reg_out[55]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => srst_d2, - Q => srst_d3, - R => prmry_resetn_i_reg(0) + I0 => sig_data_skid_reg(55), + I1 => sig_data_fifo_data_out(55), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(55) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\: unisim.vcomponents.FDRE +\sig_data_reg_out[56]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => srst_d3, - Q => srst_d4, - R => prmry_resetn_i_reg(0) + I0 => sig_data_skid_reg(56), + I1 => sig_data_fifo_data_out(56), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(56) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\: unisim.vcomponents.FDRE +\sig_data_reg_out[57]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => srst_d4, - Q => srst_d5, - R => prmry_resetn_i_reg(0) + I0 => sig_data_skid_reg(57), + I1 => sig_data_fifo_data_out(57), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(57) ); -s_out_re: unisim.vcomponents.LUT3 +\sig_data_reg_out[58]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => X"28" + INIT => X"CA" ) port map ( - I0 => srst_d5, - I1 => s_out_d5, - I2 => s_out_d4, - O => \s_out_re__0\ + I0 => sig_data_skid_reg(58), + I1 => sig_data_fifo_data_out(58), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(58) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized12\ is - port ( - p_in_d1_cdc_from_0 : out STD_LOGIC; - p_15_out : out STD_LOGIC; - all_lines_xfred : out STD_LOGIC; - prmry_resetn_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); - prmry_in_xored_1 : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axis_mm2s_aclk : in STD_LOGIC; - \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]\ : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized12\ : entity is "cdc_sync"; -end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized12\; - -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized12\ is - signal \^p_15_out\ : STD_LOGIC; - signal \^p_in_d1_cdc_from_0\ : STD_LOGIC; - signal s_out_d1_cdc_to : STD_LOGIC; - signal s_out_d2 : STD_LOGIC; - signal s_out_d3 : STD_LOGIC; - signal s_out_d4 : STD_LOGIC; - signal s_out_d5 : STD_LOGIC; - signal \s_out_re__0\ : STD_LOGIC; - signal srst_d1 : STD_LOGIC; - signal srst_d2 : STD_LOGIC; - signal srst_d3 : STD_LOGIC; - signal srst_d4 : STD_LOGIC; - signal srst_d5 : STD_LOGIC; - attribute ASYNC_REG : boolean; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM : string; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "FDR"; - attribute box_type : string; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "PRIMITIVE"; -begin - p_15_out <= \^p_15_out\; - p_in_d1_cdc_from_0 <= \^p_in_d1_cdc_from_0\; -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\: unisim.vcomponents.FDRE +\sig_data_reg_out[59]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => s_out_d1_cdc_to, - Q => s_out_d2, - R => SR(0) + I0 => sig_data_skid_reg(59), + I1 => sig_data_fifo_data_out(59), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(59) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\: unisim.vcomponents.FDRE +\sig_data_reg_out[5]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => s_out_d2, - Q => s_out_d3, - R => SR(0) + I0 => sig_data_skid_reg(5), + I1 => sig_data_fifo_data_out(5), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(5) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\: unisim.vcomponents.FDRE +\sig_data_reg_out[60]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => s_out_d3, - Q => s_out_d4, - R => SR(0) + I0 => sig_data_skid_reg(60), + I1 => sig_data_fifo_data_out(60), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(60) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\: unisim.vcomponents.FDRE +\sig_data_reg_out[61]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => s_out_d4, - Q => s_out_d5, - R => SR(0) + I0 => sig_data_skid_reg(61), + I1 => sig_data_fifo_data_out(61), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(61) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\: unisim.vcomponents.FDRE +\sig_data_reg_out[62]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => \s_out_re__0\, - Q => \^p_15_out\, - R => SR(0) + I0 => sig_data_skid_reg(62), + I1 => sig_data_fifo_data_out(62), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(62) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\: unisim.vcomponents.FDRE +\sig_data_reg_out[63]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => \^p_in_d1_cdc_from_0\, - Q => s_out_d1_cdc_to, - R => SR(0) + I0 => sig_data_skid_reg(63), + I1 => sig_data_fifo_data_out(63), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(63) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\: unisim.vcomponents.FDRE +\sig_data_reg_out[67]_i_2\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"E" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => prmry_in_xored_1, - Q => \^p_in_d1_cdc_from_0\, - R => prmry_resetn_i_reg(0) + I0 => sig_data_skid_reg(67), + I1 => sig_s_ready_dup, + O => \sig_data_reg_out[67]_i_2_n_0\ ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\: unisim.vcomponents.FDRE +\sig_data_reg_out[6]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => '1', - Q => srst_d1, - R => SR(0) + I0 => sig_data_skid_reg(6), + I1 => sig_data_fifo_data_out(6), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(6) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\: unisim.vcomponents.FDRE +\sig_data_reg_out[7]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => srst_d1, - Q => srst_d2, - R => SR(0) + I0 => sig_data_skid_reg(7), + I1 => sig_data_fifo_data_out(7), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(7) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\: unisim.vcomponents.FDRE +\sig_data_reg_out[8]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"CA" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => srst_d2, - Q => srst_d3, - R => SR(0) + I0 => sig_data_skid_reg(8), + I1 => sig_data_fifo_data_out(8), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(8) ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\: unisim.vcomponents.FDRE +\sig_data_reg_out[9]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"CA" + ) + port map ( + I0 => sig_data_skid_reg(9), + I1 => sig_data_fifo_data_out(9), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(9) + ); +\sig_data_reg_out_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => srst_d3, - Q => srst_d4, - R => SR(0) + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(0), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(0), + R => sig_stream_rst ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => srst_d4, - Q => srst_d5, - R => SR(0) + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(10), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(10), + R => sig_stream_rst ); -\GEN_LINEBUF_NO_SOF.all_lines_xfred_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out_reg[11]\: unisim.vcomponents.FDRE generic map( - INIT => X"1" + INIT => '0' ) port map ( - I0 => \^p_15_out\, - I1 => \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]\, - O => all_lines_xfred + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(11), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(11), + R => sig_stream_rst ); -s_out_re: unisim.vcomponents.LUT3 +\sig_data_reg_out_reg[12]\: unisim.vcomponents.FDRE generic map( - INIT => X"28" + INIT => '0' ) port map ( - I0 => srst_d5, - I1 => s_out_d5, - I2 => s_out_d4, - O => \s_out_re__0\ + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(12), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(12), + R => sig_stream_rst ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized14\ is - port ( - p_1_out : out STD_LOGIC; - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - scndry_reset2 : in STD_LOGIC; - fifo_pipe_empty : in STD_LOGIC; - m_axis_mm2s_aclk : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized14\ : entity is "cdc_sync"; -end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized14\; - -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized14\ is - signal p_level_in_d1_cdc_from : STD_LOGIC; - signal s_level_out_d1_cdc_to : STD_LOGIC; - signal s_level_out_d2 : STD_LOGIC; - signal s_level_out_d3 : STD_LOGIC; - attribute ASYNC_REG : boolean; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM : string; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; - attribute box_type : string; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; -begin -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => p_level_in_d1_cdc_from, - Q => s_level_out_d1_cdc_to, - R => SR(0) + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(13), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(13), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => s_level_out_d1_cdc_to, - Q => s_level_out_d2, - R => SR(0) + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(14), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(14), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => s_level_out_d2, - Q => s_level_out_d3, - R => SR(0) + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(15), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(15), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => s_level_out_d3, - Q => p_1_out, - R => SR(0) + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(16), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(16), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => fifo_pipe_empty, - Q => p_level_in_d1_cdc_from, - R => scndry_reset2 + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(17), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(17), + R => sig_stream_rst ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized15\ is - port ( - p_0_out : out STD_LOGIC; - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - scndry_reset2 : in STD_LOGIC; - \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg\ : in STD_LOGIC; - m_axis_mm2s_aclk : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized15\ : entity is "cdc_sync"; -end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized15\; - -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized15\ is - signal p_level_in_d1_cdc_from : STD_LOGIC; - signal s_level_out_d1_cdc_to : STD_LOGIC; - signal s_level_out_d2 : STD_LOGIC; - signal s_level_out_d3 : STD_LOGIC; - attribute ASYNC_REG : boolean; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM : string; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; - attribute box_type : string; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; -begin -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => p_level_in_d1_cdc_from, - Q => s_level_out_d1_cdc_to, - R => SR(0) + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(18), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(18), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => s_level_out_d1_cdc_to, - Q => s_level_out_d2, - R => SR(0) + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(19), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(19), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => s_level_out_d2, - Q => s_level_out_d3, - R => SR(0) + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(1), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(1), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => s_level_out_d3, - Q => p_0_out, - R => SR(0) + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(20), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(20), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg\, - Q => p_level_in_d1_cdc_from, - R => scndry_reset2 + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(21), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(21), + R => sig_stream_rst ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized18\ is - port ( - sig_reset_reg_reg : out STD_LOGIC; - m_axis_fifo_ainit_nosync : out STD_LOGIC; - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tready_d1_reg\ : out STD_LOGIC; - scndry_reset2 : in STD_LOGIC; - m_axis_mm2s_aclk : in STD_LOGIC; - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - mm2s_halt : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\ : in STD_LOGIC; - m_axis_mm2s_tready : in STD_LOGIC; - p_15_out : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized18\ : entity is "cdc_sync"; -end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized18\; - -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized18\ is - signal p_level_in_d1_cdc_from : STD_LOGIC; - signal s_level_out_d1_cdc_to : STD_LOGIC; - signal s_level_out_d2 : STD_LOGIC; - signal s_level_out_d3 : STD_LOGIC; - signal \^sig_reset_reg_reg\ : STD_LOGIC; - attribute ASYNC_REG : boolean; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM : string; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; - attribute box_type : string; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tready_d1_i_1\ : label is "soft_lutpair34"; - attribute SOFT_HLUTNM of \sig_data_reg_out[31]_i_1\ : label is "soft_lutpair34"; -begin - sig_reset_reg_reg <= \^sig_reset_reg_reg\; -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => p_level_in_d1_cdc_from, - Q => s_level_out_d1_cdc_to, - R => scndry_reset2 + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(22), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(22), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => s_level_out_d1_cdc_to, - Q => s_level_out_d2, - R => scndry_reset2 + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(23), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(23), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => s_level_out_d2, - Q => s_level_out_d3, - R => scndry_reset2 + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(24), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(24), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => s_level_out_d3, - Q => \^sig_reset_reg_reg\, - R => scndry_reset2 + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(25), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(25), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => mm2s_halt, - Q => p_level_in_d1_cdc_from, - R => SR(0) + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(26), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(26), + R => sig_stream_rst ); -\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tready_d1_i_1\: unisim.vcomponents.LUT4 +\sig_data_reg_out_reg[27]\: unisim.vcomponents.FDRE generic map( - INIT => X"0020" + INIT => '0' ) port map ( - I0 => m_axis_mm2s_tready, - I1 => \^sig_reset_reg_reg\, - I2 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\, - I3 => p_15_out, - O => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tready_d1_reg\ + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(27), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(27), + R => sig_stream_rst ); -\sig_data_reg_out[31]_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out_reg[28]\: unisim.vcomponents.FDRE generic map( - INIT => X"B" + INIT => '0' ) port map ( - I0 => \^sig_reset_reg_reg\, - I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\, - O => m_axis_fifo_ainit_nosync + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(28), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(28), + R => sig_stream_rst ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized2\ is - port ( - scndry_out : out STD_LOGIC; - m_axis_mm2s_aclk : in STD_LOGIC; - \FSM_sequential_dmacntrl_cs_reg[1]\ : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized2\ : entity is "cdc_sync"; -end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized2\; - -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized2\ is - signal p_level_in_d1_cdc_from : STD_LOGIC; - signal s_level_out_d1_cdc_to : STD_LOGIC; - signal s_level_out_d2 : STD_LOGIC; - signal s_level_out_d3 : STD_LOGIC; - attribute ASYNC_REG : boolean; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM : string; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; - attribute box_type : string; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; -begin -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => p_level_in_d1_cdc_from, - Q => s_level_out_d1_cdc_to, - R => '0' + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(29), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(29), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => s_level_out_d1_cdc_to, - Q => s_level_out_d2, - R => '0' + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(2), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(2), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => s_level_out_d2, - Q => s_level_out_d3, - R => '0' + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(30), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(30), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => s_level_out_d3, - Q => scndry_out, - R => '0' + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(31), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(31), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[32]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \FSM_sequential_dmacntrl_cs_reg[1]\, - Q => p_level_in_d1_cdc_from, - R => '0' + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(32), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(32), + R => sig_stream_rst ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized3\ is - port ( - scndry_out : out STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - axis_min_assert_sftrst : in STD_LOGIC; - m_axis_mm2s_aclk : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized3\ : entity is "cdc_sync"; -end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized3\; - -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized3\ is - signal p_level_in_d1_cdc_from : STD_LOGIC; - signal s_level_out_d1_cdc_to : STD_LOGIC; - signal s_level_out_d2 : STD_LOGIC; - signal s_level_out_d3 : STD_LOGIC; - attribute ASYNC_REG : boolean; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM : string; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; - attribute box_type : string; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; -begin -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[33]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => p_level_in_d1_cdc_from, - Q => s_level_out_d1_cdc_to, - R => '0' + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(33), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(33), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[34]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => s_level_out_d1_cdc_to, - Q => s_level_out_d2, - R => '0' + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(34), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(34), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[35]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => s_level_out_d2, - Q => s_level_out_d3, - R => '0' + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(35), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(35), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[36]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => s_level_out_d3, - Q => scndry_out, - R => '0' + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(36), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(36), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[37]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => axis_min_assert_sftrst, - Q => p_level_in_d1_cdc_from, - R => '0' + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(37), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(37), + R => sig_stream_rst ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized4\ is - port ( - prmry_reset2 : out STD_LOGIC; - prmry_in : out STD_LOGIC; - run_stop_d1_reg : out STD_LOGIC; - halt_i_reg : out STD_LOGIC; - \dmacr_i_reg[2]\ : out STD_LOGIC; - \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ : out STD_LOGIC; - reset_counts_reg : out STD_LOGIC; - min_assert_sftrst : in STD_LOGIC; - s_soft_reset_i : in STD_LOGIC; - p_68_out : in STD_LOGIC_VECTOR ( 1 downto 0 ); - p_35_out : in STD_LOGIC; - halt_i_reg_0 : in STD_LOGIC; - halt_reset_reg : in STD_LOGIC; - halt_i0 : in STD_LOGIC; - mm2s_axi2ip_wrce : in STD_LOGIC_VECTOR ( 0 to 0 ); - D : in STD_LOGIC_VECTOR ( 0 to 0 ); - assert_sftrst_d1 : in STD_LOGIC; - reset_counts : in STD_LOGIC; - \out\ : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - hrd_resetn_i_reg : in STD_LOGIC; - s_axi_lite_aclk : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized4\ : entity is "cdc_sync"; -end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized4\; - -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized4\ is - signal mm2s_hrd_resetn : STD_LOGIC; - signal p_level_in_d1_cdc_from : STD_LOGIC; - signal \^prmry_in\ : STD_LOGIC; - signal s_level_out_d1_cdc_to : STD_LOGIC; - signal s_level_out_d2 : STD_LOGIC; - signal s_level_out_d3 : STD_LOGIC; - attribute ASYNC_REG : boolean; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM : string; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; - attribute box_type : string; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_1__0\ : label is "soft_lutpair114"; - attribute SOFT_HLUTNM of sig_mm2s_dm_prmry_resetn_inferred_i_1 : label is "soft_lutpair114"; -begin - prmry_in <= \^prmry_in\; -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[38]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => p_level_in_d1_cdc_from, - Q => s_level_out_d1_cdc_to, - R => '0' + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(38), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(38), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[39]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => s_level_out_d1_cdc_to, - Q => s_level_out_d2, - R => '0' + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(39), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(39), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => s_level_out_d2, - Q => s_level_out_d3, - R => '0' + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(3), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(3), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[40]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => s_level_out_d3, - Q => mm2s_hrd_resetn, - R => '0' + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(40), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(40), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[41]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => hrd_resetn_i_reg, - Q => p_level_in_d1_cdc_from, - R => '0' + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(41), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(41), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_1__0\: unisim.vcomponents.LUT3 +\sig_data_reg_out_reg[42]\: unisim.vcomponents.FDRE generic map( - INIT => X"02" + INIT => '0' ) port map ( - I0 => mm2s_hrd_resetn, - I1 => min_assert_sftrst, - I2 => s_soft_reset_i, - O => \^prmry_in\ + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(42), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(42), + R => sig_stream_rst ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to_i_1\: unisim.vcomponents.LUT1 +\sig_data_reg_out_reg[43]\: unisim.vcomponents.FDRE generic map( - INIT => X"1" + INIT => '0' ) port map ( - I0 => mm2s_hrd_resetn, - O => prmry_reset2 + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(43), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(43), + R => sig_stream_rst ); -\dmacr_i[2]_i_1\: unisim.vcomponents.LUT6 +\sig_data_reg_out_reg[44]\: unisim.vcomponents.FDRE generic map( - INIT => X"EA00EAEA00000000" + INIT => '0' ) port map ( - I0 => p_68_out(1), - I1 => mm2s_axi2ip_wrce(0), - I2 => D(0), - I3 => min_assert_sftrst, - I4 => assert_sftrst_d1, - I5 => mm2s_hrd_resetn, - O => \dmacr_i_reg[2]\ + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(44), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(44), + R => sig_stream_rst ); -halt_i_i_1: unisim.vcomponents.LUT5 +\sig_data_reg_out_reg[45]\: unisim.vcomponents.FDRE generic map( - INIT => X"AAAA0888" + INIT => '0' ) port map ( - I0 => \^prmry_in\, - I1 => halt_i_reg_0, - I2 => halt_reset_reg, - I3 => p_68_out(0), - I4 => halt_i0, - O => halt_i_reg + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(45), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(45), + R => sig_stream_rst ); -reset_counts_i_1: unisim.vcomponents.LUT6 +\sig_data_reg_out_reg[46]\: unisim.vcomponents.FDRE generic map( - INIT => X"AE00AEAE00000000" + INIT => '0' ) port map ( - I0 => reset_counts, - I1 => p_68_out(1), - I2 => \out\, - I3 => min_assert_sftrst, - I4 => assert_sftrst_d1, - I5 => mm2s_hrd_resetn, - O => reset_counts_reg + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(46), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(46), + R => sig_stream_rst ); -run_stop_d1_i_1: unisim.vcomponents.LUT6 +\sig_data_reg_out_reg[47]\: unisim.vcomponents.FDRE generic map( - INIT => X"0000000000000200" + INIT => '0' ) port map ( - I0 => p_68_out(0), - I1 => p_35_out, - I2 => p_68_out(1), - I3 => mm2s_hrd_resetn, - I4 => min_assert_sftrst, - I5 => s_soft_reset_i, - O => run_stop_d1_reg + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(47), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(47), + R => sig_stream_rst ); -sig_mm2s_dm_prmry_resetn_inferred_i_1: unisim.vcomponents.LUT4 +\sig_data_reg_out_reg[48]\: unisim.vcomponents.FDRE generic map( - INIT => X"0010" + INIT => '0' ) port map ( - I0 => s_soft_reset_i, - I1 => min_assert_sftrst, - I2 => mm2s_hrd_resetn, - I3 => halt_reset_reg, - O => \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(48), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(48), + R => sig_stream_rst ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized5\ is - port ( - scndry_out : out STD_LOGIC; - m_axis_mm2s_aclk : in STD_LOGIC; - prmry_in : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized5\ : entity is "cdc_sync"; -end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized5\; - -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized5\ is - signal p_level_in_d1_cdc_from : STD_LOGIC; - signal s_level_out_d1_cdc_to : STD_LOGIC; - signal s_level_out_d2 : STD_LOGIC; - signal s_level_out_d3 : STD_LOGIC; - attribute ASYNC_REG : boolean; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM : string; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; - attribute box_type : string; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; -begin -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[49]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => p_level_in_d1_cdc_from, - Q => s_level_out_d1_cdc_to, - R => '0' + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(49), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(49), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => s_level_out_d1_cdc_to, - Q => s_level_out_d2, - R => '0' + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(4), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(4), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[50]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => s_level_out_d2, - Q => s_level_out_d3, - R => '0' + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(50), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(50), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[51]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => s_level_out_d3, - Q => scndry_out, - R => '0' + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(51), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(51), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[52]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => prmry_in, - Q => p_level_in_d1_cdc_from, - R => '0' + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(52), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(52), + R => sig_stream_rst ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized6\ is - port ( - \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg\ : out STD_LOGIC; - \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[16]\ : out STD_LOGIC; - \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg\ : out STD_LOGIC; - mm2s_axi2ip_wrce : out STD_LOGIC_VECTOR ( 5 downto 0 ); - \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - prmtr_updt_complete_i_reg : out STD_LOGIC; - ioc_irq_reg : out STD_LOGIC; - dly_irq_reg : out STD_LOGIC; - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_lite_aclk : in STD_LOGIC; - prmry_reset2 : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - different_delay : in STD_LOGIC; - different_thresh : in STD_LOGIC; - \out\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[6]\ : in STD_LOGIC; - prmry_resetn_i_reg : in STD_LOGIC; - threshold_is_zero : in STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[4]\ : in STD_LOGIC; - p_68_out : in STD_LOGIC_VECTOR ( 0 to 0 ); - prepare_wrce_d1 : in STD_LOGIC; - lite_wr_addr_phase_finished_data_phase_started : in STD_LOGIC; - wvalid : in STD_LOGIC; - D : in STD_LOGIC_VECTOR ( 1 downto 0 ); - mm2s_ioc_irq_set : in STD_LOGIC; - ioc_irq_reg_0 : in STD_LOGIC; - mm2s_dly_irq_set : in STD_LOGIC; - dly_irq_reg_0 : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized6\ : entity is "cdc_sync"; -end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized6\; - -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized6\ is - signal \^enable_dmacr_frm_cntr.dmacr_i_reg[16]\ : STD_LOGIC; - signal \^mm2s_axi2ip_wrce\ : STD_LOGIC_VECTOR ( 5 downto 0 ); - signal p_0_out : STD_LOGIC; - signal p_in_d1_cdc_from : STD_LOGIC; - signal prmry_in_xored : STD_LOGIC; - signal \ptr_ref_i[4]_i_2_n_0\ : STD_LOGIC; - signal \reg_module_vsize[12]_i_2_n_0\ : STD_LOGIC; - signal s_out_d1_cdc_to : STD_LOGIC; - signal s_out_d2 : STD_LOGIC; - signal s_out_d3 : STD_LOGIC; - signal s_out_d4 : STD_LOGIC; - signal s_out_d5 : STD_LOGIC; - signal \s_out_re__0\ : STD_LOGIC; - signal srst_d1 : STD_LOGIC; - signal srst_d2 : STD_LOGIC; - signal srst_d3 : STD_LOGIC; - signal srst_d4 : STD_LOGIC; - signal srst_d5 : STD_LOGIC; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_1\ : label is "soft_lutpair2"; - attribute SOFT_HLUTNM of \ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_1\ : label is "soft_lutpair1"; - attribute SOFT_HLUTNM of \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_1\ : label is "soft_lutpair2"; - attribute ASYNC_REG : boolean; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM : string; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "FDR"; - attribute box_type : string; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "FDR"; - attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "PRIMITIVE"; - attribute SOFT_HLUTNM of prmtr_updt_complete_i_i_1 : label is "soft_lutpair1"; - attribute SOFT_HLUTNM of \ptr_ref_i[4]_i_2\ : label is "soft_lutpair0"; - attribute SOFT_HLUTNM of \reg_module_vsize[12]_i_2\ : label is "soft_lutpair0"; -begin - \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[16]\ <= \^enable_dmacr_frm_cntr.dmacr_i_reg[16]\; - mm2s_axi2ip_wrce(5 downto 0) <= \^mm2s_axi2ip_wrce\(5 downto 0); -\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out_reg[53]\: unisim.vcomponents.FDRE generic map( - INIT => X"8" + INIT => '0' ) port map ( - I0 => \^enable_dmacr_frm_cntr.dmacr_i_reg[16]\, - I1 => different_delay, - O => \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg\ + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(53), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(53), + R => sig_stream_rst ); -\ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_1\: unisim.vcomponents.LUT3 +\sig_data_reg_out_reg[54]\: unisim.vcomponents.FDRE generic map( - INIT => X"D5" + INIT => '0' ) port map ( - I0 => prmry_resetn_i_reg, - I1 => \^enable_dmacr_frm_cntr.dmacr_i_reg[16]\, - I2 => threshold_is_zero, - O => \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]\(0) + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(54), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(54), + R => sig_stream_rst ); -\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_1\: unisim.vcomponents.LUT2 +\sig_data_reg_out_reg[55]\: unisim.vcomponents.FDRE generic map( - INIT => X"8" + INIT => '0' ) port map ( - I0 => \^enable_dmacr_frm_cntr.dmacr_i_reg[16]\, - I1 => different_thresh, - O => \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg\ + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(55), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(55), + R => sig_stream_rst ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[56]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => s_out_d1_cdc_to, - Q => s_out_d2, - R => prmry_reset2 + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(56), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(56), + R => sig_stream_rst ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[57]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => s_out_d2, - Q => s_out_d3, - R => prmry_reset2 + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(57), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(57), + R => sig_stream_rst ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[58]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => s_out_d3, - Q => s_out_d4, - R => prmry_reset2 + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(58), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(58), + R => sig_stream_rst ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[59]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => s_out_d4, - Q => s_out_d5, - R => prmry_reset2 + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(59), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(59), + R => sig_stream_rst ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \s_out_re__0\, - Q => p_0_out, - R => prmry_reset2 + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(5), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(5), + R => sig_stream_rst ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[60]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => p_in_d1_cdc_from, - Q => s_out_d1_cdc_to, - R => prmry_reset2 + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(60), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(60), + R => sig_stream_rst ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[61]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => prmry_in_xored, - Q => p_in_d1_cdc_from, - R => SR(0) + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(61), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(61), + R => sig_stream_rst ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__3\: unisim.vcomponents.LUT4 +\sig_data_reg_out_reg[62]\: unisim.vcomponents.FDRE generic map( - INIT => X"BF40" + INIT => '0' ) port map ( - I0 => prepare_wrce_d1, - I1 => lite_wr_addr_phase_finished_data_phase_started, - I2 => wvalid, - I3 => p_in_d1_cdc_from, - O => prmry_in_xored + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(62), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(62), + R => sig_stream_rst ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[63]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => '1', - Q => srst_d1, - R => prmry_reset2 + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(63), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(63), + R => sig_stream_rst ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[67]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => srst_d1, - Q => srst_d2, - R => prmry_reset2 + C => m_axi_s2mm_aclk, + CE => E(0), + D => \sig_data_reg_out[67]_i_2_n_0\, + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(64), + R => sig_stream_rst ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => srst_d2, - Q => srst_d3, - R => prmry_reset2 + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(6), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(6), + R => sig_stream_rst ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => srst_d3, - Q => srst_d4, - R => prmry_reset2 + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(7), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(7), + R => sig_stream_rst ); -\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => srst_d4, - Q => srst_d5, - R => prmry_reset2 + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(8), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(8), + R => sig_stream_rst ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i[31]_i_1\: unisim.vcomponents.LUT4 +\sig_data_reg_out_reg[9]\: unisim.vcomponents.FDRE generic map( - INIT => X"0004" + INIT => '0' ) port map ( - I0 => \out\(3), - I1 => p_0_out, - I2 => \out\(5), - I3 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[4]\, - O => \^mm2s_axi2ip_wrce\(5) + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_data_skid_mux_out(9), + Q => \^gen_indet_btt.lsig_byte_cntr_reg[3]\(9), + R => sig_stream_rst ); -\I_DMA_REGISTER/dly_irq_i_1\: unisim.vcomponents.LUT4 +\sig_data_skid_reg_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => X"F7F0" + INIT => '0' ) port map ( - I0 => D(1), - I1 => \^mm2s_axi2ip_wrce\(0), - I2 => mm2s_dly_irq_set, - I3 => dly_irq_reg_0, - O => dly_irq_reg + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(0), + Q => sig_data_skid_reg(0), + R => sig_stream_rst ); -\I_DMA_REGISTER/ioc_irq_i_1\: unisim.vcomponents.LUT4 +\sig_data_skid_reg_reg[10]\: unisim.vcomponents.FDRE generic map( - INIT => X"F7F0" + INIT => '0' ) port map ( - I0 => D(0), - I1 => \^mm2s_axi2ip_wrce\(0), - I2 => mm2s_ioc_irq_set, - I3 => ioc_irq_reg_0, - O => ioc_irq_reg + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(10), + Q => sig_data_skid_reg(10), + R => sig_stream_rst ); -\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid[15]_i_1\: unisim.vcomponents.LUT6 +\sig_data_skid_reg_reg[11]\: unisim.vcomponents.FDRE generic map( - INIT => X"0100000000000000" + INIT => '0' ) port map ( - I0 => \out\(3), - I1 => \out\(0), - I2 => \out\(5), - I3 => \out\(1), - I4 => \out\(4), - I5 => \reg_module_vsize[12]_i_2_n_0\, - O => \^mm2s_axi2ip_wrce\(4) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(11), + Q => sig_data_skid_reg(11), + R => sig_stream_rst ); -dma_interr_i_2: unisim.vcomponents.LUT6 +\sig_data_skid_reg_reg[12]\: unisim.vcomponents.FDRE generic map( - INIT => X"0000100000000000" + INIT => '0' ) port map ( - I0 => \out\(5), - I1 => \out\(1), - I2 => \out\(0), - I3 => p_0_out, - I4 => \out\(2), - I5 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[6]\, - O => \^mm2s_axi2ip_wrce\(0) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(12), + Q => sig_data_skid_reg(12), + R => sig_stream_rst ); -\dmacr_i[1]_i_1\: unisim.vcomponents.LUT6 +\sig_data_skid_reg_reg[13]\: unisim.vcomponents.FDRE generic map( - INIT => X"0000001000000000" + INIT => '0' ) port map ( - I0 => \out\(5), - I1 => \out\(0), - I2 => p_0_out, - I3 => \out\(2), - I4 => \out\(1), - I5 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[6]\, - O => \^enable_dmacr_frm_cntr.dmacr_i_reg[16]\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(13), + Q => sig_data_skid_reg(13), + R => sig_stream_rst ); -prmtr_updt_complete_i_i_1: unisim.vcomponents.LUT3 +\sig_data_skid_reg_reg[14]\: unisim.vcomponents.FDRE generic map( - INIT => X"80" + INIT => '0' ) port map ( - I0 => \^mm2s_axi2ip_wrce\(2), - I1 => prmry_resetn_i_reg, - I2 => p_68_out(0), - O => prmtr_updt_complete_i_reg + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(14), + Q => sig_data_skid_reg(14), + R => sig_stream_rst ); -\ptr_ref_i[4]_i_1\: unisim.vcomponents.LUT4 +\sig_data_skid_reg_reg[15]\: unisim.vcomponents.FDRE generic map( - INIT => X"0010" + INIT => '0' ) port map ( - I0 => \out\(5), - I1 => \out\(2), - I2 => \out\(3), - I3 => \ptr_ref_i[4]_i_2_n_0\, - O => \^mm2s_axi2ip_wrce\(1) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(15), + Q => sig_data_skid_reg(15), + R => sig_stream_rst ); -\ptr_ref_i[4]_i_2\: unisim.vcomponents.LUT4 +\sig_data_skid_reg_reg[16]\: unisim.vcomponents.FDRE generic map( - INIT => X"EFFF" + INIT => '0' ) port map ( - I0 => \out\(0), - I1 => \out\(4), - I2 => \out\(1), - I3 => p_0_out, - O => \ptr_ref_i[4]_i_2_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(16), + Q => sig_data_skid_reg(16), + R => sig_stream_rst ); -\reg_module_hsize[15]_i_1\: unisim.vcomponents.LUT6 +\sig_data_skid_reg_reg[17]\: unisim.vcomponents.FDRE generic map( - INIT => X"0100000000000000" + INIT => '0' ) port map ( - I0 => \out\(3), - I1 => \out\(1), - I2 => \out\(5), - I3 => \out\(4), - I4 => \out\(0), - I5 => \reg_module_vsize[12]_i_2_n_0\, - O => \^mm2s_axi2ip_wrce\(3) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(17), + Q => sig_data_skid_reg(17), + R => sig_stream_rst ); -\reg_module_vsize[12]_i_1\: unisim.vcomponents.LUT6 +\sig_data_skid_reg_reg[18]\: unisim.vcomponents.FDRE generic map( - INIT => X"0000000000001000" + INIT => '0' ) port map ( - I0 => \out\(5), - I1 => \out\(1), - I2 => \out\(4), - I3 => \reg_module_vsize[12]_i_2_n_0\, - I4 => \out\(0), - I5 => \out\(3), - O => \^mm2s_axi2ip_wrce\(2) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(18), + Q => sig_data_skid_reg(18), + R => sig_stream_rst ); -\reg_module_vsize[12]_i_2\: unisim.vcomponents.LUT2 +\sig_data_skid_reg_reg[19]\: unisim.vcomponents.FDRE generic map( - INIT => X"8" + INIT => '0' ) port map ( - I0 => p_0_out, - I1 => \out\(2), - O => \reg_module_vsize[12]_i_2_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(19), + Q => sig_data_skid_reg(19), + R => sig_stream_rst ); -s_out_re: unisim.vcomponents.LUT3 +\sig_data_skid_reg_reg[1]\: unisim.vcomponents.FDRE generic map( - INIT => X"28" + INIT => '0' ) port map ( - I0 => srst_d5, - I1 => s_out_d5, - I2 => s_out_d4, - O => \s_out_re__0\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(1), + Q => sig_data_skid_reg(1), + R => sig_stream_rst ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized7\ is - port ( - mm2s_introut : out STD_LOGIC; - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_lite_aclk : in STD_LOGIC; - prmry_reset2 : in STD_LOGIC; - p_75_out : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized7\ : entity is "cdc_sync"; -end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized7\; - -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized7\ is - signal p_level_in_d1_cdc_from : STD_LOGIC; - signal s_level_out_d1_cdc_to : STD_LOGIC; - signal s_level_out_d2 : STD_LOGIC; - attribute ASYNC_REG : boolean; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM : string; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; - attribute box_type : string; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; - attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; - attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; - attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; -begin -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => p_level_in_d1_cdc_from, - Q => s_level_out_d1_cdc_to, - R => SR(0) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(20), + Q => sig_data_skid_reg(20), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_level_out_d1_cdc_to, - Q => s_level_out_d2, - R => SR(0) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(21), + Q => sig_data_skid_reg(21), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_level_out_d2, - Q => mm2s_introut, - R => SR(0) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(22), + Q => sig_data_skid_reg(22), + R => sig_stream_rst ); -\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => p_75_out, - Q => p_level_in_d1_cdc_from, - R => prmry_reset2 + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(23), + Q => sig_data_skid_reg(23), + R => sig_stream_rst ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f is - port ( - fifo_full_p1 : out STD_LOGIC; - sig_dqual_reg_empty_reg : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - sig_dqual_reg_empty_reg_0 : out STD_LOGIC; - sig_ld_new_cmd_reg_reg : out STD_LOGIC; - sig_next_cmd_cmplt_reg_reg : out STD_LOGIC; - D : out STD_LOGIC_VECTOR ( 3 downto 0 ); - sig_cmd2data_valid_reg : in STD_LOGIC; - sig_mstr2data_cmd_valid : in STD_LOGIC; - FIFO_Full_reg : in STD_LOGIC; - sig_inhibit_rdy_n_0 : in STD_LOGIC; - \sig_dbeat_cntr_reg[2]\ : in STD_LOGIC; - sig_next_sequential_reg : in STD_LOGIC; - sig_last_dbeat : in STD_LOGIC; - sig_dqual_reg_empty : in STD_LOGIC; - m_axi_mm2s_rvalid : in STD_LOGIC; - sig_halt_reg_reg : in STD_LOGIC; - ram_full_i_reg : in STD_LOGIC; - \sig_advance_pipe9_out__1\ : in STD_LOGIC; - sig_rsc2stat_status_valid : in STD_LOGIC; - FIFO_Full_reg_0 : in STD_LOGIC; - sig_inhibit_rdy_n : in STD_LOGIC; - sig_next_calc_error_reg : in STD_LOGIC; - sig_addr_posted_cntr : in STD_LOGIC_VECTOR ( 2 downto 0 ); - sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; - sig_ld_new_cmd_reg : in STD_LOGIC; - sig_dqual_reg_full : in STD_LOGIC; - m_axi_mm2s_rlast : in STD_LOGIC; - \sig_dbeat_cntr_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); - \sig_dbeat_cntr_reg[3]\ : in STD_LOGIC; - \sig_dbeat_cntr_reg[4]\ : in STD_LOGIC; - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_mm2s_aclk : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f : entity is "cntr_incr_decr_addn_f"; -end Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f is - signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal addr_i_p1 : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal \sig_addr_posted_cntr_max__1\ : STD_LOGIC; - signal \^sig_dqual_reg_empty_reg\ : STD_LOGIC; - signal \^sig_dqual_reg_empty_reg_0\ : STD_LOGIC; - signal sig_next_cmd_cmplt_reg_i_4_n_0 : STD_LOGIC; - signal sig_rd_empty : STD_LOGIC; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \FIFO_Full_i_1__2\ : label is "soft_lutpair104"; - attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[2]_i_1__2\ : label is "soft_lutpair104"; - attribute SOFT_HLUTNM of \sig_dbeat_cntr[6]_i_1\ : label is "soft_lutpair105"; - attribute SOFT_HLUTNM of \sig_dbeat_cntr[7]_i_1\ : label is "soft_lutpair106"; - attribute SOFT_HLUTNM of \sig_dbeat_cntr[7]_i_2\ : label is "soft_lutpair105"; - attribute SOFT_HLUTNM of sig_ld_new_cmd_reg_i_1 : label is "soft_lutpair106"; -begin - Q(1 downto 0) <= \^q\(1 downto 0); - sig_dqual_reg_empty_reg <= \^sig_dqual_reg_empty_reg\; - sig_dqual_reg_empty_reg_0 <= \^sig_dqual_reg_empty_reg_0\; -\FIFO_Full_i_1__2\: unisim.vcomponents.LUT5 +\sig_data_skid_reg_reg[24]\: unisim.vcomponents.FDRE generic map( - INIT => X"41100000" + INIT => '0' ) port map ( - I0 => sig_rd_empty, - I1 => \^sig_dqual_reg_empty_reg\, - I2 => sig_cmd2data_valid_reg, - I3 => \^q\(0), - I4 => \^q\(1), - O => fifo_full_p1 + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(24), + Q => sig_data_skid_reg(24), + R => sig_stream_rst ); -\INFERRED_GEN.cnt_i[0]_i_1__2\: unisim.vcomponents.LUT6 +\sig_data_skid_reg_reg[25]\: unisim.vcomponents.FDRE generic map( - INIT => X"BB4BBBBB44B44444" + INIT => '0' ) port map ( - I0 => sig_rd_empty, - I1 => \^sig_dqual_reg_empty_reg\, - I2 => sig_mstr2data_cmd_valid, - I3 => FIFO_Full_reg, - I4 => sig_inhibit_rdy_n_0, - I5 => \^q\(0), - O => addr_i_p1(0) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(25), + Q => sig_data_skid_reg(25), + R => sig_stream_rst ); -\INFERRED_GEN.cnt_i[1]_i_1__2\: unisim.vcomponents.LUT5 +\sig_data_skid_reg_reg[26]\: unisim.vcomponents.FDRE generic map( - INIT => X"77E78818" + INIT => '0' ) port map ( - I0 => \^q\(0), - I1 => sig_cmd2data_valid_reg, - I2 => \^sig_dqual_reg_empty_reg\, - I3 => sig_rd_empty, - I4 => \^q\(1), - O => addr_i_p1(1) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(26), + Q => sig_data_skid_reg(26), + R => sig_stream_rst ); -\INFERRED_GEN.cnt_i[2]_i_1__2\: unisim.vcomponents.LUT5 +\sig_data_skid_reg_reg[27]\: unisim.vcomponents.FDRE generic map( - INIT => X"7F7F0180" + INIT => '0' ) port map ( - I0 => sig_cmd2data_valid_reg, - I1 => \^q\(0), - I2 => \^q\(1), - I3 => \^sig_dqual_reg_empty_reg\, - I4 => sig_rd_empty, - O => addr_i_p1(2) - ); -\INFERRED_GEN.cnt_i_reg[0]\: unisim.vcomponents.FDSE - port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => addr_i_p1(0), - Q => \^q\(0), - S => SR(0) - ); -\INFERRED_GEN.cnt_i_reg[1]\: unisim.vcomponents.FDSE - port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => addr_i_p1(1), - Q => \^q\(1), - S => SR(0) - ); -\INFERRED_GEN.cnt_i_reg[2]\: unisim.vcomponents.FDSE - port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => addr_i_p1(2), - Q => sig_rd_empty, - S => SR(0) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(27), + Q => sig_data_skid_reg(27), + R => sig_stream_rst ); -\sig_dbeat_cntr[4]_i_1\: unisim.vcomponents.LUT6 +\sig_data_skid_reg_reg[28]\: unisim.vcomponents.FDRE generic map( - INIT => X"4444444444444441" + INIT => '0' ) port map ( - I0 => \^sig_dqual_reg_empty_reg\, - I1 => \sig_dbeat_cntr_reg[7]\(4), - I2 => \sig_dbeat_cntr_reg[7]\(2), - I3 => \sig_dbeat_cntr_reg[7]\(0), - I4 => \sig_dbeat_cntr_reg[7]\(1), - I5 => \sig_dbeat_cntr_reg[7]\(3), - O => D(0) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(28), + Q => sig_data_skid_reg(28), + R => sig_stream_rst ); -\sig_dbeat_cntr[5]_i_1\: unisim.vcomponents.LUT3 +\sig_data_skid_reg_reg[29]\: unisim.vcomponents.FDRE generic map( - INIT => X"41" + INIT => '0' ) port map ( - I0 => \^sig_dqual_reg_empty_reg\, - I1 => \sig_dbeat_cntr_reg[7]\(5), - I2 => \sig_dbeat_cntr_reg[3]\, - O => D(1) - ); -\sig_dbeat_cntr[6]_i_1\: unisim.vcomponents.LUT3 + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(29), + Q => sig_data_skid_reg(29), + R => sig_stream_rst + ); +\sig_data_skid_reg_reg[2]\: unisim.vcomponents.FDRE generic map( - INIT => X"41" + INIT => '0' ) port map ( - I0 => \^sig_dqual_reg_empty_reg\, - I1 => \sig_dbeat_cntr_reg[7]\(6), - I2 => \sig_dbeat_cntr_reg[4]\, - O => D(2) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(2), + Q => sig_data_skid_reg(2), + R => sig_stream_rst ); -\sig_dbeat_cntr[7]_i_1\: unisim.vcomponents.LUT2 +\sig_data_skid_reg_reg[30]\: unisim.vcomponents.FDRE generic map( - INIT => X"E" + INIT => '0' ) port map ( - I0 => \^sig_dqual_reg_empty_reg\, - I1 => \sig_dbeat_cntr_reg[2]\, - O => E(0) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(30), + Q => sig_data_skid_reg(30), + R => sig_stream_rst ); -\sig_dbeat_cntr[7]_i_2\: unisim.vcomponents.LUT4 +\sig_data_skid_reg_reg[31]\: unisim.vcomponents.FDRE generic map( - INIT => X"4441" + INIT => '0' ) port map ( - I0 => \^sig_dqual_reg_empty_reg\, - I1 => \sig_dbeat_cntr_reg[7]\(7), - I2 => \sig_dbeat_cntr_reg[4]\, - I3 => \sig_dbeat_cntr_reg[7]\(6), - O => D(3) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(31), + Q => sig_data_skid_reg(31), + R => sig_stream_rst ); -sig_ld_new_cmd_reg_i_1: unisim.vcomponents.LUT3 +\sig_data_skid_reg_reg[32]\: unisim.vcomponents.FDRE generic map( - INIT => X"08" + INIT => '0' ) port map ( - I0 => \^sig_dqual_reg_empty_reg\, - I1 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - I2 => sig_ld_new_cmd_reg, - O => sig_ld_new_cmd_reg_reg + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(32), + Q => sig_data_skid_reg(32), + R => sig_stream_rst ); -sig_next_cmd_cmplt_reg_i_1: unisim.vcomponents.LUT6 +\sig_data_skid_reg_reg[33]\: unisim.vcomponents.FDRE generic map( - INIT => X"10000000FFFFFFFF" + INIT => '0' ) port map ( - I0 => \^sig_dqual_reg_empty_reg\, - I1 => sig_next_calc_error_reg, - I2 => sig_dqual_reg_full, - I3 => \^sig_dqual_reg_empty_reg_0\, - I4 => m_axi_mm2s_rlast, - I5 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - O => sig_next_cmd_cmplt_reg_reg + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(33), + Q => sig_data_skid_reg(33), + R => sig_stream_rst ); -sig_next_cmd_cmplt_reg_i_2: unisim.vcomponents.LUT5 +\sig_data_skid_reg_reg[34]\: unisim.vcomponents.FDRE generic map( - INIT => X"AAAA8000" + INIT => '0' ) port map ( - I0 => sig_next_cmd_cmplt_reg_i_4_n_0, - I1 => sig_next_sequential_reg, - I2 => sig_last_dbeat, - I3 => \^sig_dqual_reg_empty_reg_0\, - I4 => sig_dqual_reg_empty, - O => \^sig_dqual_reg_empty_reg\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(34), + Q => sig_data_skid_reg(34), + R => sig_stream_rst ); -sig_next_cmd_cmplt_reg_i_3: unisim.vcomponents.LUT4 +\sig_data_skid_reg_reg[35]\: unisim.vcomponents.FDRE generic map( - INIT => X"8A00" + INIT => '0' ) port map ( - I0 => m_axi_mm2s_rvalid, - I1 => sig_halt_reg_reg, - I2 => ram_full_i_reg, - I3 => \sig_advance_pipe9_out__1\, - O => \^sig_dqual_reg_empty_reg_0\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(35), + Q => sig_data_skid_reg(35), + R => sig_stream_rst ); -sig_next_cmd_cmplt_reg_i_4: unisim.vcomponents.LUT6 +\sig_data_skid_reg_reg[36]\: unisim.vcomponents.FDRE generic map( - INIT => X"0000000000000075" + INIT => '0' ) port map ( - I0 => sig_rsc2stat_status_valid, - I1 => FIFO_Full_reg_0, - I2 => sig_inhibit_rdy_n, - I3 => \sig_addr_posted_cntr_max__1\, - I4 => sig_rd_empty, - I5 => sig_next_calc_error_reg, - O => sig_next_cmd_cmplt_reg_i_4_n_0 + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(36), + Q => sig_data_skid_reg(36), + R => sig_stream_rst ); -sig_next_cmd_cmplt_reg_i_5: unisim.vcomponents.LUT3 +\sig_data_skid_reg_reg[37]\: unisim.vcomponents.FDRE generic map( - INIT => X"80" + INIT => '0' ) port map ( - I0 => sig_addr_posted_cntr(1), - I1 => sig_addr_posted_cntr(0), - I2 => sig_addr_posted_cntr(2), - O => \sig_addr_posted_cntr_max__1\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(37), + Q => sig_data_skid_reg(37), + R => sig_stream_rst ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_3 is - port ( - fifo_full_p1 : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); - sig_calc_error_pushed_reg : in STD_LOGIC; - sig_wr_fifo : in STD_LOGIC; - sig_sm_halt_reg : in STD_LOGIC; - sig_input_reg_empty : in STD_LOGIC; - sig_calc_error_pushed : in STD_LOGIC; - p_55_out : in STD_LOGIC; - FIFO_Full_reg : in STD_LOGIC; - sig_inhibit_rdy_n : in STD_LOGIC; - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_mm2s_aclk : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_3 : entity is "cntr_incr_decr_addn_f"; -end Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_3; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_3 is - signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal addr_i_p1 : STD_LOGIC_VECTOR ( 2 downto 0 ); - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of FIFO_Full_i_1 : label is "soft_lutpair75"; - attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[2]_i_1\ : label is "soft_lutpair75"; -begin - Q(2 downto 0) <= \^q\(2 downto 0); -FIFO_Full_i_1: unisim.vcomponents.LUT5 +\sig_data_skid_reg_reg[38]\: unisim.vcomponents.FDRE generic map( - INIT => X"41100008" + INIT => '0' ) port map ( - I0 => \^q\(2), - I1 => sig_calc_error_pushed_reg, - I2 => sig_wr_fifo, - I3 => \^q\(0), - I4 => \^q\(1), - O => fifo_full_p1 + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(38), + Q => sig_data_skid_reg(38), + R => sig_stream_rst ); -\INFERRED_GEN.cnt_i[0]_i_1\: unisim.vcomponents.LUT6 +\sig_data_skid_reg_reg[39]\: unisim.vcomponents.FDRE generic map( - INIT => X"0010FFEFFFEF0010" + INIT => '0' ) port map ( - I0 => \^q\(2), - I1 => sig_sm_halt_reg, - I2 => sig_input_reg_empty, - I3 => sig_calc_error_pushed, - I4 => sig_wr_fifo, - I5 => \^q\(0), - O => addr_i_p1(0) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(39), + Q => sig_data_skid_reg(39), + R => sig_stream_rst ); -\INFERRED_GEN.cnt_i[1]_i_1\: unisim.vcomponents.LUT6 +\sig_data_skid_reg_reg[3]\: unisim.vcomponents.FDRE generic map( - INIT => X"AEAAF7FF51550800" + INIT => '0' ) port map ( - I0 => \^q\(0), - I1 => p_55_out, - I2 => FIFO_Full_reg, - I3 => sig_inhibit_rdy_n, - I4 => sig_calc_error_pushed_reg, - I5 => \^q\(1), - O => addr_i_p1(1) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(3), + Q => sig_data_skid_reg(3), + R => sig_stream_rst ); -\INFERRED_GEN.cnt_i[2]_i_1\: unisim.vcomponents.LUT5 +\sig_data_skid_reg_reg[40]\: unisim.vcomponents.FDRE generic map( - INIT => X"FE7F0180" + INIT => '0' ) port map ( - I0 => sig_wr_fifo, - I1 => \^q\(0), - I2 => \^q\(1), - I3 => sig_calc_error_pushed_reg, - I4 => \^q\(2), - O => addr_i_p1(2) - ); -\INFERRED_GEN.cnt_i_reg[0]\: unisim.vcomponents.FDSE - port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => addr_i_p1(0), - Q => \^q\(0), - S => SR(0) - ); -\INFERRED_GEN.cnt_i_reg[1]\: unisim.vcomponents.FDSE - port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => addr_i_p1(1), - Q => \^q\(1), - S => SR(0) - ); -\INFERRED_GEN.cnt_i_reg[2]\: unisim.vcomponents.FDSE - port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => addr_i_p1(2), - Q => \^q\(2), - S => SR(0) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(40), + Q => sig_data_skid_reg(40), + R => sig_stream_rst ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_4 is - port ( - fifo_full_p1 : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); - p_57_out : in STD_LOGIC; - sig_wr_fifo : in STD_LOGIC; - sig_rsc2stat_status_valid : in STD_LOGIC; - FIFO_Full_reg : in STD_LOGIC; - sig_inhibit_rdy_n_reg : in STD_LOGIC; - sts_tready_reg : in STD_LOGIC; - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_mm2s_aclk : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_4 : entity is "cntr_incr_decr_addn_f"; -end Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_4; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_4 is - signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal addr_i_p1 : STD_LOGIC_VECTOR ( 2 downto 0 ); - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \FIFO_Full_i_1__3\ : label is "soft_lutpair73"; - attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[2]_i_1__3\ : label is "soft_lutpair73"; -begin - Q(2 downto 0) <= \^q\(2 downto 0); -\FIFO_Full_i_1__3\: unisim.vcomponents.LUT5 +\sig_data_skid_reg_reg[41]\: unisim.vcomponents.FDRE generic map( - INIT => X"41100000" + INIT => '0' ) port map ( - I0 => \^q\(2), - I1 => p_57_out, - I2 => sig_wr_fifo, - I3 => \^q\(0), - I4 => \^q\(1), - O => fifo_full_p1 + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(41), + Q => sig_data_skid_reg(41), + R => sig_stream_rst ); -\INFERRED_GEN.cnt_i[0]_i_1__3\: unisim.vcomponents.LUT6 +\sig_data_skid_reg_reg[42]\: unisim.vcomponents.FDRE generic map( - INIT => X"BB4BBBBB44B44444" + INIT => '0' ) port map ( - I0 => \^q\(2), - I1 => p_57_out, - I2 => sig_rsc2stat_status_valid, - I3 => FIFO_Full_reg, - I4 => sig_inhibit_rdy_n_reg, - I5 => \^q\(0), - O => addr_i_p1(0) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(42), + Q => sig_data_skid_reg(42), + R => sig_stream_rst ); -\INFERRED_GEN.cnt_i[1]_i_1__3\: unisim.vcomponents.LUT6 +\sig_data_skid_reg_reg[43]\: unisim.vcomponents.FDRE generic map( - INIT => X"AEAAF7FF51550800" + INIT => '0' ) port map ( - I0 => \^q\(0), - I1 => sig_rsc2stat_status_valid, - I2 => FIFO_Full_reg, - I3 => sig_inhibit_rdy_n_reg, - I4 => sts_tready_reg, - I5 => \^q\(1), - O => addr_i_p1(1) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(43), + Q => sig_data_skid_reg(43), + R => sig_stream_rst ); -\INFERRED_GEN.cnt_i[2]_i_1__3\: unisim.vcomponents.LUT5 +\sig_data_skid_reg_reg[44]\: unisim.vcomponents.FDRE generic map( - INIT => X"7F7F0180" + INIT => '0' ) port map ( - I0 => sig_wr_fifo, - I1 => \^q\(0), - I2 => \^q\(1), - I3 => p_57_out, - I4 => \^q\(2), - O => addr_i_p1(2) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(44), + Q => sig_data_skid_reg(44), + R => sig_stream_rst ); -\INFERRED_GEN.cnt_i_reg[0]\: unisim.vcomponents.FDSE - port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => addr_i_p1(0), - Q => \^q\(0), - S => SR(0) +\sig_data_skid_reg_reg[45]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(45), + Q => sig_data_skid_reg(45), + R => sig_stream_rst ); -\INFERRED_GEN.cnt_i_reg[1]\: unisim.vcomponents.FDSE - port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => addr_i_p1(1), - Q => \^q\(1), - S => SR(0) +\sig_data_skid_reg_reg[46]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(46), + Q => sig_data_skid_reg(46), + R => sig_stream_rst ); -\INFERRED_GEN.cnt_i_reg[2]\: unisim.vcomponents.FDSE - port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => addr_i_p1(2), - Q => \^q\(2), - S => SR(0) +\sig_data_skid_reg_reg[47]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(47), + Q => sig_data_skid_reg(47), + R => sig_stream_rst ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_5 is - port ( - fifo_full_p1 : out STD_LOGIC; - sig_calc_error_reg_reg : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); - sig_posted_to_axi_reg : out STD_LOGIC; - sig_cmd2addr_valid_reg : in STD_LOGIC; - sig_mstr2addr_cmd_valid : in STD_LOGIC; - FIFO_Full_reg : in STD_LOGIC; - sig_inhibit_rdy_n : in STD_LOGIC; - sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; - sig_data2addr_stop_req : in STD_LOGIC; - sig_addr_reg_empty : in STD_LOGIC; - sig_sf_allow_addr_req : in STD_LOGIC; - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_mm2s_aclk : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_5 : entity is "cntr_incr_decr_addn_f"; -end Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_5; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_5 is - signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal addr_i_p1 : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal \^sig_calc_error_reg_reg\ : STD_LOGIC; - signal sig_rd_empty : STD_LOGIC; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \FIFO_Full_i_1__1\ : label is "soft_lutpair71"; - attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[2]_i_1__1\ : label is "soft_lutpair71"; - attribute SOFT_HLUTNM of \sig_next_addr_reg[31]_i_2\ : label is "soft_lutpair72"; - attribute SOFT_HLUTNM of sig_posted_to_axi_2_i_1 : label is "soft_lutpair72"; -begin - Q(1 downto 0) <= \^q\(1 downto 0); - sig_calc_error_reg_reg <= \^sig_calc_error_reg_reg\; -\FIFO_Full_i_1__1\: unisim.vcomponents.LUT5 +\sig_data_skid_reg_reg[48]\: unisim.vcomponents.FDRE generic map( - INIT => X"41100008" + INIT => '0' ) port map ( - I0 => sig_rd_empty, - I1 => \^sig_calc_error_reg_reg\, - I2 => sig_cmd2addr_valid_reg, - I3 => \^q\(0), - I4 => \^q\(1), - O => fifo_full_p1 + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(48), + Q => sig_data_skid_reg(48), + R => sig_stream_rst ); -\INFERRED_GEN.cnt_i[0]_i_1__1\: unisim.vcomponents.LUT5 +\sig_data_skid_reg_reg[49]\: unisim.vcomponents.FDRE generic map( - INIT => X"5955A6AA" + INIT => '0' ) port map ( - I0 => \^sig_calc_error_reg_reg\, - I1 => sig_mstr2addr_cmd_valid, - I2 => FIFO_Full_reg, - I3 => sig_inhibit_rdy_n, - I4 => \^q\(0), - O => addr_i_p1(0) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(49), + Q => sig_data_skid_reg(49), + R => sig_stream_rst ); -\INFERRED_GEN.cnt_i[1]_i_1__1\: unisim.vcomponents.LUT6 +\sig_data_skid_reg_reg[4]\: unisim.vcomponents.FDRE generic map( - INIT => X"AEAAF7FF51550800" + INIT => '0' ) port map ( - I0 => \^q\(0), - I1 => sig_mstr2addr_cmd_valid, - I2 => FIFO_Full_reg, - I3 => sig_inhibit_rdy_n, - I4 => \^sig_calc_error_reg_reg\, - I5 => \^q\(1), - O => addr_i_p1(1) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(4), + Q => sig_data_skid_reg(4), + R => sig_stream_rst ); -\INFERRED_GEN.cnt_i[2]_i_1__1\: unisim.vcomponents.LUT5 +\sig_data_skid_reg_reg[50]\: unisim.vcomponents.FDRE generic map( - INIT => X"FE7F0180" + INIT => '0' ) port map ( - I0 => sig_cmd2addr_valid_reg, - I1 => \^q\(0), - I2 => \^q\(1), - I3 => \^sig_calc_error_reg_reg\, - I4 => sig_rd_empty, - O => addr_i_p1(2) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(50), + Q => sig_data_skid_reg(50), + R => sig_stream_rst ); -\INFERRED_GEN.cnt_i_reg[0]\: unisim.vcomponents.FDSE - port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => addr_i_p1(0), - Q => \^q\(0), - S => SR(0) +\sig_data_skid_reg_reg[51]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(51), + Q => sig_data_skid_reg(51), + R => sig_stream_rst ); -\INFERRED_GEN.cnt_i_reg[1]\: unisim.vcomponents.FDSE - port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => addr_i_p1(1), - Q => \^q\(1), - S => SR(0) +\sig_data_skid_reg_reg[52]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(52), + Q => sig_data_skid_reg(52), + R => sig_stream_rst ); -\INFERRED_GEN.cnt_i_reg[2]\: unisim.vcomponents.FDSE - port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => addr_i_p1(2), - Q => sig_rd_empty, - S => SR(0) +\sig_data_skid_reg_reg[53]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(53), + Q => sig_data_skid_reg(53), + R => sig_stream_rst ); -\sig_next_addr_reg[31]_i_2\: unisim.vcomponents.LUT4 +\sig_data_skid_reg_reg[54]\: unisim.vcomponents.FDRE generic map( - INIT => X"0008" + INIT => '0' ) port map ( - I0 => sig_sf_allow_addr_req, - I1 => sig_addr_reg_empty, - I2 => sig_data2addr_stop_req, - I3 => sig_rd_empty, - O => \^sig_calc_error_reg_reg\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(54), + Q => sig_data_skid_reg(54), + R => sig_stream_rst ); -sig_posted_to_axi_2_i_1: unisim.vcomponents.LUT5 +\sig_data_skid_reg_reg[55]\: unisim.vcomponents.FDRE generic map( - INIT => X"02000000" + INIT => '0' ) port map ( - I0 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - I1 => sig_rd_empty, - I2 => sig_data2addr_stop_req, - I3 => sig_addr_reg_empty, - I4 => sig_sf_allow_addr_req, - O => sig_posted_to_axi_reg + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(55), + Q => sig_data_skid_reg(55), + R => sig_stream_rst ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_6 is - port ( - fifo_full_p1 : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); - FIFO_Full_reg : out STD_LOGIC; - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : in STD_LOGIC; - sig_mstr2sf_cmd_valid : in STD_LOGIC; - FIFO_Full_reg_0 : in STD_LOGIC; - sig_inhibit_rdy_n_reg : in STD_LOGIC; - sig_stream_rst : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_6 : entity is "cntr_incr_decr_addn_f"; -end Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_6; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_6 is - signal \^fifo_full_reg\ : STD_LOGIC; - signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal addr_i_p1 : STD_LOGIC_VECTOR ( 2 downto 0 ); - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \FIFO_Full_i_1__0\ : label is "soft_lutpair68"; - attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[0]_i_1__0\ : label is "soft_lutpair69"; - attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[2]_i_1__0\ : label is "soft_lutpair68"; - attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][7]_srl4_i_1\ : label is "soft_lutpair69"; -begin - FIFO_Full_reg <= \^fifo_full_reg\; - Q(2 downto 0) <= \^q\(2 downto 0); -\FIFO_Full_i_1__0\: unisim.vcomponents.LUT5 +\sig_data_skid_reg_reg[56]\: unisim.vcomponents.FDRE generic map( - INIT => X"41100008" + INIT => '0' ) port map ( - I0 => \^q\(2), - I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\, - I2 => \^fifo_full_reg\, - I3 => \^q\(0), - I4 => \^q\(1), - O => fifo_full_p1 + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(56), + Q => sig_data_skid_reg(56), + R => sig_stream_rst ); -\INFERRED_GEN.cnt_i[0]_i_1__0\: unisim.vcomponents.LUT5 +\sig_data_skid_reg_reg[57]\: unisim.vcomponents.FDRE generic map( - INIT => X"5955A6AA" + INIT => '0' ) port map ( - I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\, - I1 => sig_mstr2sf_cmd_valid, - I2 => FIFO_Full_reg_0, - I3 => sig_inhibit_rdy_n_reg, - I4 => \^q\(0), - O => addr_i_p1(0) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(57), + Q => sig_data_skid_reg(57), + R => sig_stream_rst ); -\INFERRED_GEN.cnt_i[1]_i_1__0\: unisim.vcomponents.LUT6 +\sig_data_skid_reg_reg[58]\: unisim.vcomponents.FDRE generic map( - INIT => X"AEAAF7FF51550800" + INIT => '0' ) port map ( - I0 => \^q\(0), - I1 => sig_mstr2sf_cmd_valid, - I2 => FIFO_Full_reg_0, - I3 => sig_inhibit_rdy_n_reg, - I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\, - I5 => \^q\(1), - O => addr_i_p1(1) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(58), + Q => sig_data_skid_reg(58), + R => sig_stream_rst ); -\INFERRED_GEN.cnt_i[2]_i_1__0\: unisim.vcomponents.LUT5 +\sig_data_skid_reg_reg[59]\: unisim.vcomponents.FDRE generic map( - INIT => X"FE7F0180" + INIT => '0' ) port map ( - I0 => \^fifo_full_reg\, - I1 => \^q\(0), - I2 => \^q\(1), - I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\, - I4 => \^q\(2), - O => addr_i_p1(2) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(59), + Q => sig_data_skid_reg(59), + R => sig_stream_rst ); -\INFERRED_GEN.cnt_i_reg[0]\: unisim.vcomponents.FDSE - port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => addr_i_p1(0), - Q => \^q\(0), - S => sig_stream_rst +\sig_data_skid_reg_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(5), + Q => sig_data_skid_reg(5), + R => sig_stream_rst ); -\INFERRED_GEN.cnt_i_reg[1]\: unisim.vcomponents.FDSE - port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => addr_i_p1(1), - Q => \^q\(1), - S => sig_stream_rst +\sig_data_skid_reg_reg[60]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(60), + Q => sig_data_skid_reg(60), + R => sig_stream_rst ); -\INFERRED_GEN.cnt_i_reg[2]\: unisim.vcomponents.FDSE - port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => addr_i_p1(2), - Q => \^q\(2), - S => sig_stream_rst +\sig_data_skid_reg_reg[61]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(61), + Q => sig_data_skid_reg(61), + R => sig_stream_rst ); -\INFERRED_GEN.data_reg[3][7]_srl4_i_1\: unisim.vcomponents.LUT3 +\sig_data_skid_reg_reg[62]\: unisim.vcomponents.FDRE generic map( - INIT => X"20" + INIT => '0' ) port map ( - I0 => sig_mstr2sf_cmd_valid, - I1 => FIFO_Full_reg_0, - I2 => sig_inhibit_rdy_n_reg, - O => \^fifo_full_reg\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(62), + Q => sig_data_skid_reg(62), + R => sig_stream_rst ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_dynshreg_f is - port ( - sig_wr_fifo : out STD_LOGIC; - \out\ : out STD_LOGIC_VECTOR ( 49 downto 0 ); - sig_calc_error_reg_reg : out STD_LOGIC; - p_55_out : in STD_LOGIC; - FIFO_Full_reg : in STD_LOGIC; - sig_inhibit_rdy_n : in STD_LOGIC; - Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); - sig_sm_halt_reg : in STD_LOGIC; - sig_input_reg_empty : in STD_LOGIC; - \in\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - \s_axis_cmd_tdata_reg[63]\ : in STD_LOGIC_VECTOR ( 48 downto 0 ); - m_axi_mm2s_aclk : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_dynshreg_f : entity is "dynshreg_f"; -end Arty_Z7_20_axi_vdma_0_0_dynshreg_f; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_dynshreg_f is - signal \^out\ : STD_LOGIC_VECTOR ( 49 downto 0 ); - signal sig_calc_error_reg_i_2_n_0 : STD_LOGIC; - signal sig_calc_error_reg_i_3_n_0 : STD_LOGIC; - signal sig_calc_error_reg_i_4_n_0 : STD_LOGIC; - signal sig_calc_error_reg_i_5_n_0 : STD_LOGIC; - signal \^sig_wr_fifo\ : STD_LOGIC; - attribute srl_bus_name : string; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][0]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name : string; - attribute srl_name of \INFERRED_GEN.data_reg[3][0]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][0]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][10]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][10]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][10]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][11]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][11]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][11]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][12]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][12]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][12]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][13]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][13]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][13]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][14]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][14]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][14]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][15]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][15]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][15]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][1]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][1]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][1]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][23]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][23]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][23]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][2]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][2]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][2]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][30]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][30]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][30]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][32]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][32]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][32]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][33]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][33]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][33]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][34]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][34]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][34]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][35]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][35]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][35]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][36]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][36]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][36]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][37]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][37]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][37]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][38]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][38]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][38]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][39]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][39]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][39]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][3]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][3]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][3]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][40]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][40]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][40]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][41]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][41]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][41]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][42]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][42]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][42]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][43]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][43]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][43]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][44]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][44]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][44]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][45]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][45]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][45]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][46]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][46]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][46]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][47]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][47]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][47]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][48]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][48]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][48]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][49]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][49]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][49]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][4]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][4]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][4]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][50]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][50]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][50]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][51]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][51]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][51]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][52]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][52]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][52]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][53]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][53]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][53]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][54]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][54]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][54]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][55]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][55]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][55]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][56]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][56]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][56]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][57]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][57]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][57]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][58]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][58]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][58]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][59]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][59]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][59]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][5]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][5]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][5]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][60]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][60]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][60]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][61]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][61]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][61]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][62]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][62]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][62]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][63]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][63]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][63]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][6]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][6]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][6]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][7]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][7]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][7]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][8]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][8]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][8]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][9]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][9]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][9]_srl4 "; -begin - \out\(49 downto 0) <= \^out\(49 downto 0); - sig_wr_fifo <= \^sig_wr_fifo\; -\INFERRED_GEN.data_reg[3][0]_srl4\: unisim.vcomponents.SRL16E +\sig_data_skid_reg_reg[63]\: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(0), - Q => \^out\(0) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(63), + Q => sig_data_skid_reg(63), + R => sig_stream_rst ); -\INFERRED_GEN.data_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT3 +\sig_data_skid_reg_reg[67]\: unisim.vcomponents.FDRE generic map( - INIT => X"20" + INIT => '0' ) port map ( - I0 => p_55_out, - I1 => FIFO_Full_reg, - I2 => sig_inhibit_rdy_n, - O => \^sig_wr_fifo\ + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => '1', + Q => sig_data_skid_reg(67), + R => sig_stream_rst ); -\INFERRED_GEN.data_reg[3][10]_srl4\: unisim.vcomponents.SRL16E +\sig_data_skid_reg_reg[6]\: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(10), - Q => \^out\(10) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(6), + Q => sig_data_skid_reg(6), + R => sig_stream_rst ); -\INFERRED_GEN.data_reg[3][11]_srl4\: unisim.vcomponents.SRL16E +\sig_data_skid_reg_reg[7]\: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(11), - Q => \^out\(11) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(7), + Q => sig_data_skid_reg(7), + R => sig_stream_rst ); -\INFERRED_GEN.data_reg[3][12]_srl4\: unisim.vcomponents.SRL16E +\sig_data_skid_reg_reg[8]\: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(12), - Q => \^out\(12) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(8), + Q => sig_data_skid_reg(8), + R => sig_stream_rst ); -\INFERRED_GEN.data_reg[3][13]_srl4\: unisim.vcomponents.SRL16E +\sig_data_skid_reg_reg[9]\: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(13), - Q => \^out\(13) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(9), + Q => sig_data_skid_reg(9), + R => sig_stream_rst ); -\INFERRED_GEN.data_reg[3][14]_srl4\: unisim.vcomponents.SRL16E +sig_last_reg_out_i_1: unisim.vcomponents.LUT3 generic map( - INIT => X"0000" + INIT => X"B8" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(14), - Q => \^out\(14) + I0 => sig_data_fifo_data_out(64), + I1 => sig_s_ready_dup, + I2 => sig_last_skid_reg, + O => sig_last_skid_mux_out ); -\INFERRED_GEN.data_reg[3][15]_srl4\: unisim.vcomponents.SRL16E +sig_last_reg_out_reg: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(15), - Q => \^out\(15) + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_last_skid_mux_out, + Q => sig_ibtt2wdc_tlast, + R => sig_stream_rst ); -\INFERRED_GEN.data_reg[3][1]_srl4\: unisim.vcomponents.SRL16E +sig_last_skid_reg_reg: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(1), - Q => \^out\(1) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(64), + Q => sig_last_skid_reg, + R => sig_stream_rst ); -\INFERRED_GEN.data_reg[3][23]_srl4\: unisim.vcomponents.SRL16E +\sig_m_valid_dup_i_1__0\: unisim.vcomponents.LUT6 generic map( - INIT => X"0000" + INIT => X"4444444400404040" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(16), - Q => \^out\(16) + I0 => sig_init_reg, + I1 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I2 => sig_m_valid_dup, + I3 => sig_s_ready_dup, + I4 => sig_wdc2ibtt_tready, + I5 => sig_data_fifo_dvalid, + O => \sig_m_valid_dup_i_1__0_n_0\ ); -\INFERRED_GEN.data_reg[3][2]_srl4\: unisim.vcomponents.SRL16E +sig_m_valid_dup_reg: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(2), - Q => \^out\(2) + C => m_axi_s2mm_aclk, + CE => '1', + D => \sig_m_valid_dup_i_1__0_n_0\, + Q => sig_m_valid_dup, + R => '0' ); -\INFERRED_GEN.data_reg[3][30]_srl4\: unisim.vcomponents.SRL16E +sig_m_valid_out_reg: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(16), - Q => \^out\(17) + C => m_axi_s2mm_aclk, + CE => '1', + D => \sig_m_valid_dup_i_1__0_n_0\, + Q => sig_m_valid_out, + R => '0' ); -\INFERRED_GEN.data_reg[3][32]_srl4\: unisim.vcomponents.SRL16E +\sig_s_ready_dup_i_1__1\: unisim.vcomponents.LUT6 generic map( - INIT => X"0000" + INIT => X"FFFFFFFFAEAEAEEE" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(17), - Q => \^out\(18) + I0 => sig_init_reg, + I1 => sig_s_ready_dup, + I2 => sig_m_valid_dup, + I3 => hold_ff_q, + I4 => \gpregsm1.user_valid_reg_0\, + I5 => sig_wdc2ibtt_tready, + O => \sig_s_ready_dup_i_1__1_n_0\ ); -\INFERRED_GEN.data_reg[3][33]_srl4\: unisim.vcomponents.SRL16E +sig_s_ready_dup_reg: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(18), - Q => \^out\(19) + C => m_axi_s2mm_aclk, + CE => '1', + D => \sig_s_ready_dup_i_1__1_n_0\, + Q => sig_s_ready_dup, + R => sig_stream_rst ); -\INFERRED_GEN.data_reg[3][34]_srl4\: unisim.vcomponents.SRL16E +sig_s_ready_out_reg: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(19), - Q => \^out\(20) + C => m_axi_s2mm_aclk, + CE => '1', + D => \sig_s_ready_dup_i_1__1_n_0\, + Q => sig_s_ready_out, + R => sig_stream_rst ); -\INFERRED_GEN.data_reg[3][35]_srl4\: unisim.vcomponents.SRL16E +\sig_strb_reg_out[8]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"0000" + INIT => X"CA" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(20), - Q => \^out\(21) + I0 => sig_strb_skid_reg(8), + I1 => sig_data_fifo_data_out(65), + I2 => sig_s_ready_dup, + O => sig_strb_skid_mux_out(8) ); -\INFERRED_GEN.data_reg[3][36]_srl4\: unisim.vcomponents.SRL16E +\sig_strb_reg_out_reg[8]\: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(21), - Q => \^out\(22) + C => m_axi_s2mm_aclk, + CE => E(0), + D => sig_strb_skid_mux_out(8), + Q => sig_ibtt2wdc_eop, + R => sig_stream_rst ); -\INFERRED_GEN.data_reg[3][37]_srl4\: unisim.vcomponents.SRL16E +\sig_strb_skid_reg_reg[8]\: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(22), - Q => \^out\(23) + C => m_axi_s2mm_aclk, + CE => sig_s_ready_dup, + D => sig_data_fifo_data_out(65), + Q => sig_strb_skid_reg(8), + R => sig_stream_rst ); -\INFERRED_GEN.data_reg[3][38]_srl4\: unisim.vcomponents.SRL16E +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_slice is + port ( + slice_insert_valid : out STD_LOGIC; + ld_btt_cntr_reg3_reg : out STD_LOGIC; + ld_btt_cntr_reg2_reg : out STD_LOGIC; + ld_btt_cntr_reg1_reg : out STD_LOGIC; + sig_valid_fifo_ld12_out : out STD_LOGIC; + S : out STD_LOGIC_VECTOR ( 3 downto 0 ); + DI : out STD_LOGIC_VECTOR ( 0 to 0 ); + \storage_data_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \in\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_s2mm_aclk : in STD_LOGIC; + sig_inhibit_rdy_n : in STD_LOGIC; + FIFO_Full_reg : in STD_LOGIC; + ld_btt_cntr_reg3 : in STD_LOGIC; + ld_btt_cntr_reg2 : in STD_LOGIC; + ld_btt_cntr_reg1 : in STD_LOGIC; + sig_sm_ld_dre_cmd : in STD_LOGIC; + sig_cmd_full : in STD_LOGIC; + CO : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_eop_sent : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + \sig_max_first_increment_reg[0]\ : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + sig_btt_eq_0 : in STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + sig_curr_eof_reg : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_slice : entity is "axi_datamover_slice"; +end Arty_Z7_20_axi_vdma_0_0_axi_datamover_slice; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_slice is + signal \areset_d_reg_n_0_[0]\ : STD_LOGIC; + signal \^in\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ld_btt_cntr_reg1_i_2_n_0 : STD_LOGIC; + signal m_valid_i_i_1_n_0 : STD_LOGIC; + signal p_1_in : STD_LOGIC; + signal sig_tstrb_fifo_rdy : STD_LOGIC; + signal sig_tstrb_fifo_valid : STD_LOGIC; + signal \^sig_valid_fifo_ld12_out\ : STD_LOGIC; + signal \^slice_insert_valid\ : STD_LOGIC; + signal \storage_data[2]_i_1_n_0\ : STD_LOGIC; + signal \storage_data[3]_i_1_n_0\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of ld_btt_cntr_reg1_i_2 : label is "soft_lutpair231"; + attribute SOFT_HLUTNM of ld_btt_cntr_reg2_i_1 : label is "soft_lutpair230"; + attribute SOFT_HLUTNM of ld_btt_cntr_reg3_i_1 : label is "soft_lutpair230"; + attribute SOFT_HLUTNM of m_valid_i_i_2 : label is "soft_lutpair232"; + attribute SOFT_HLUTNM of \storage_data[3]_i_1\ : label is "soft_lutpair231"; + attribute SOFT_HLUTNM of \storage_data[3]_i_2\ : label is "soft_lutpair232"; +begin + \in\(1 downto 0) <= \^in\(1 downto 0); + sig_valid_fifo_ld12_out <= \^sig_valid_fifo_ld12_out\; + slice_insert_valid <= \^slice_insert_valid\; +\areset_d_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_stream_rst, + Q => \areset_d_reg_n_0_[0]\, + R => '0' + ); +\areset_d_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \areset_d_reg_n_0_[0]\, + Q => p_1_in, + R => '0' + ); +ld_btt_cntr_reg1_i_1: unisim.vcomponents.LUT4 generic map( - INIT => X"0000" + INIT => X"00AE" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(23), - Q => \^out\(24) + I0 => ld_btt_cntr_reg1, + I1 => sig_sm_ld_dre_cmd, + I2 => sig_cmd_full, + I3 => ld_btt_cntr_reg1_i_2_n_0, + O => ld_btt_cntr_reg1_reg ); -\INFERRED_GEN.data_reg[3][39]_srl4\: unisim.vcomponents.SRL16E +ld_btt_cntr_reg1_i_2: unisim.vcomponents.LUT4 generic map( - INIT => X"0000" + INIT => X"F8FF" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(24), - Q => \^out\(25) + I0 => CO(0), + I1 => \^sig_valid_fifo_ld12_out\, + I2 => sig_eop_sent, + I3 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + O => ld_btt_cntr_reg1_i_2_n_0 ); -\INFERRED_GEN.data_reg[3][3]_srl4\: unisim.vcomponents.SRL16E +ld_btt_cntr_reg2_i_1: unisim.vcomponents.LUT4 generic map( - INIT => X"0000" + INIT => X"00E2" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(3), - Q => \^out\(3) + I0 => ld_btt_cntr_reg2, + I1 => sig_tstrb_fifo_rdy, + I2 => ld_btt_cntr_reg1, + I3 => ld_btt_cntr_reg1_i_2_n_0, + O => ld_btt_cntr_reg2_reg ); -\INFERRED_GEN.data_reg[3][40]_srl4\: unisim.vcomponents.SRL16E +ld_btt_cntr_reg2_i_2: unisim.vcomponents.LUT5 generic map( - INIT => X"0000" + INIT => X"0000005D" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(25), - Q => \^out\(26) + I0 => \^slice_insert_valid\, + I1 => sig_inhibit_rdy_n, + I2 => FIFO_Full_reg, + I3 => \areset_d_reg_n_0_[0]\, + I4 => p_1_in, + O => sig_tstrb_fifo_rdy ); -\INFERRED_GEN.data_reg[3][41]_srl4\: unisim.vcomponents.SRL16E +ld_btt_cntr_reg3_i_1: unisim.vcomponents.LUT4 generic map( - INIT => X"0000" + INIT => X"00EA" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(26), - Q => \^out\(27) + I0 => ld_btt_cntr_reg3, + I1 => sig_tstrb_fifo_rdy, + I2 => ld_btt_cntr_reg2, + I3 => ld_btt_cntr_reg1_i_2_n_0, + O => ld_btt_cntr_reg3_reg ); -\INFERRED_GEN.data_reg[3][42]_srl4\: unisim.vcomponents.SRL16E +m_valid_i_i_1: unisim.vcomponents.LUT5 generic map( - INIT => X"0000" + INIT => X"0000FFA2" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(27), - Q => \^out\(28) + I0 => \^slice_insert_valid\, + I1 => sig_inhibit_rdy_n, + I2 => FIFO_Full_reg, + I3 => sig_tstrb_fifo_valid, + I4 => p_1_in, + O => m_valid_i_i_1_n_0 ); -\INFERRED_GEN.data_reg[3][43]_srl4\: unisim.vcomponents.SRL16E +m_valid_i_i_2: unisim.vcomponents.LUT3 generic map( - INIT => X"0000" + INIT => X"BA" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(28), - Q => \^out\(29) + I0 => ld_btt_cntr_reg2, + I1 => sig_btt_eq_0, + I2 => ld_btt_cntr_reg3, + O => sig_tstrb_fifo_valid ); -\INFERRED_GEN.data_reg[3][44]_srl4\: unisim.vcomponents.SRL16E +m_valid_i_reg: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => m_valid_i_i_1_n_0, + Q => \^slice_insert_valid\, + R => '0' + ); +\sig_btt_cntr[15]_i_2\: unisim.vcomponents.LUT4 generic map( - INIT => X"0000" + INIT => X"4F44" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(29), - Q => \^out\(30) + I0 => sig_cmd_full, + I1 => sig_sm_ld_dre_cmd, + I2 => sig_btt_eq_0, + I3 => \^sig_valid_fifo_ld12_out\, + O => E(0) ); -\INFERRED_GEN.data_reg[3][45]_srl4\: unisim.vcomponents.SRL16E +\sig_btt_lteq_max_first_incr0_carry__0_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"0000" + INIT => X"1" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(30), - Q => \^out\(31) + I0 => \out\(14), + I1 => \out\(15), + O => \storage_data_reg[3]_0\(3) ); -\INFERRED_GEN.data_reg[3][46]_srl4\: unisim.vcomponents.SRL16E +\sig_btt_lteq_max_first_incr0_carry__0_i_2\: unisim.vcomponents.LUT2 generic map( - INIT => X"0000" + INIT => X"1" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(31), - Q => \^out\(32) + I0 => \out\(12), + I1 => \out\(13), + O => \storage_data_reg[3]_0\(2) ); -\INFERRED_GEN.data_reg[3][47]_srl4\: unisim.vcomponents.SRL16E +\sig_btt_lteq_max_first_incr0_carry__0_i_3\: unisim.vcomponents.LUT2 generic map( - INIT => X"0000" + INIT => X"1" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(32), - Q => \^out\(33) + I0 => \out\(10), + I1 => \out\(11), + O => \storage_data_reg[3]_0\(1) ); -\INFERRED_GEN.data_reg[3][48]_srl4\: unisim.vcomponents.SRL16E +\sig_btt_lteq_max_first_incr0_carry__0_i_4\: unisim.vcomponents.LUT2 generic map( - INIT => X"0000" + INIT => X"1" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(33), - Q => \^out\(34) + I0 => \out\(8), + I1 => \out\(9), + O => \storage_data_reg[3]_0\(0) ); -\INFERRED_GEN.data_reg[3][49]_srl4\: unisim.vcomponents.SRL16E +sig_btt_lteq_max_first_incr0_carry_i_1: unisim.vcomponents.LUT3 generic map( - INIT => X"0000" + INIT => X"04" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(34), - Q => \^out\(35) + I0 => \out\(0), + I1 => \sig_max_first_increment_reg[0]\, + I2 => \out\(1), + O => DI(0) ); -\INFERRED_GEN.data_reg[3][4]_srl4\: unisim.vcomponents.SRL16E +sig_btt_lteq_max_first_incr0_carry_i_2: unisim.vcomponents.LUT2 generic map( - INIT => X"0000" + INIT => X"1" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(4), - Q => \^out\(4) + I0 => \out\(6), + I1 => \out\(7), + O => S(3) ); -\INFERRED_GEN.data_reg[3][50]_srl4\: unisim.vcomponents.SRL16E +sig_btt_lteq_max_first_incr0_carry_i_3: unisim.vcomponents.LUT2 generic map( - INIT => X"0000" + INIT => X"1" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(35), - Q => \^out\(36) + I0 => \out\(4), + I1 => \out\(5), + O => S(2) ); -\INFERRED_GEN.data_reg[3][51]_srl4\: unisim.vcomponents.SRL16E +sig_btt_lteq_max_first_incr0_carry_i_4: unisim.vcomponents.LUT2 generic map( - INIT => X"0000" + INIT => X"1" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(36), - Q => \^out\(37) + I0 => \out\(2), + I1 => \out\(3), + O => S(1) ); -\INFERRED_GEN.data_reg[3][52]_srl4\: unisim.vcomponents.SRL16E +sig_btt_lteq_max_first_incr0_carry_i_5: unisim.vcomponents.LUT3 generic map( - INIT => X"0000" + INIT => X"09" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(37), - Q => \^out\(38) + I0 => \sig_max_first_increment_reg[0]\, + I1 => \out\(0), + I2 => \out\(1), + O => S(0) ); -\INFERRED_GEN.data_reg[3][53]_srl4\: unisim.vcomponents.SRL16E +\storage_data[2]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"0000" + INIT => X"8F80" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(38), - Q => \^out\(39) + I0 => sig_curr_eof_reg, + I1 => CO(0), + I2 => \^sig_valid_fifo_ld12_out\, + I3 => \^in\(0), + O => \storage_data[2]_i_1_n_0\ ); -\INFERRED_GEN.data_reg[3][54]_srl4\: unisim.vcomponents.SRL16E +\storage_data[3]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"0000" + INIT => X"B8" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(39), - Q => \^out\(40) + I0 => CO(0), + I1 => \^sig_valid_fifo_ld12_out\, + I2 => \^in\(1), + O => \storage_data[3]_i_1_n_0\ ); -\INFERRED_GEN.data_reg[3][55]_srl4\: unisim.vcomponents.SRL16E +\storage_data[3]_i_2\: unisim.vcomponents.LUT4 generic map( - INIT => X"0000" + INIT => X"F200" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(40), - Q => \^out\(41) + I0 => ld_btt_cntr_reg3, + I1 => sig_btt_eq_0, + I2 => ld_btt_cntr_reg2, + I3 => sig_tstrb_fifo_rdy, + O => \^sig_valid_fifo_ld12_out\ ); -\INFERRED_GEN.data_reg[3][56]_srl4\: unisim.vcomponents.SRL16E - generic map( - INIT => X"0000" - ) - port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(41), - Q => \^out\(42) +\storage_data_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \storage_data[2]_i_1_n_0\, + Q => \^in\(0), + R => '0' ); -\INFERRED_GEN.data_reg[3][57]_srl4\: unisim.vcomponents.SRL16E - generic map( - INIT => X"0000" - ) - port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(42), - Q => \^out\(43) +\storage_data_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \storage_data[3]_i_1_n_0\, + Q => \^in\(1), + R => '0' ); -\INFERRED_GEN.data_reg[3][58]_srl4\: unisim.vcomponents.SRL16E +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_cmdsts_if is + port ( + \cmnds_queued_reg[0]\ : out STD_LOGIC; + err_i_reg_0 : out STD_LOGIC; + \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg\ : out STD_LOGIC; + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : out STD_LOGIC; + stop_reg : out STD_LOGIC; + stop_i : out STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[1]\ : out STD_LOGIC; + dma_slverr_reg : out STD_LOGIC; + dma_decerr_reg : out STD_LOGIC; + \sig_addr_cntr_lsh_kh_reg[31]\ : out STD_LOGIC_VECTOR ( 48 downto 0 ); + mm2s_prmry_resetn : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + \INFERRED_GEN.cnt_i_reg[2]\ : in STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[2]_0\ : in STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[2]_1\ : in STD_LOGIC; + halted_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg_0\ : in STD_LOGIC; + mm2s_halt : in STD_LOGIC; + p_71_out : in STD_LOGIC_VECTOR ( 0 to 0 ); + p_77_out : in STD_LOGIC; + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\ : in STD_LOGIC; + frame_sync_reg : in STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[2]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + dma_slverr_reg_0 : in STD_LOGIC; + dma_decerr_reg_0 : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 48 downto 0 ); + zero_hsize_err : in STD_LOGIC; + zero_vsize_err : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_cmdsts_if : entity is "axi_vdma_cmdsts_if"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_cmdsts_if; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_cmdsts_if is + signal \^cmnds_queued_reg[0]\ : STD_LOGIC; + signal err_i_i_1_n_0 : STD_LOGIC; + signal \^err_i_reg_0\ : STD_LOGIC; + signal p_54_out : STD_LOGIC; + signal p_55_out : STD_LOGIC; + signal \^stop_reg\ : STD_LOGIC; +begin + \cmnds_queued_reg[0]\ <= \^cmnds_queued_reg[0]\; + err_i_reg_0 <= \^err_i_reg_0\; + stop_reg <= \^stop_reg\; +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_6\: unisim.vcomponents.LUT6 generic map( - INIT => X"0000" + INIT => X"FFFBFFFFFFFFFFFF" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(43), - Q => \^out\(44) + I0 => mm2s_halt, + I1 => p_71_out(0), + I2 => \^stop_reg\, + I3 => p_77_out, + I4 => \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\, + I5 => frame_sync_reg, + O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ ); -\INFERRED_GEN.data_reg[3][59]_srl4\: unisim.vcomponents.SRL16E +\INFERRED_GEN.cnt_i[1]_i_2__1\: unisim.vcomponents.LUT2 generic map( - INIT => X"0000" + INIT => X"2" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(44), - Q => \^out\(45) + I0 => \^cmnds_queued_reg[0]\, + I1 => \INFERRED_GEN.cnt_i_reg[2]_2\(0), + O => \INFERRED_GEN.cnt_i_reg[1]\ ); -\INFERRED_GEN.data_reg[3][5]_srl4\: unisim.vcomponents.SRL16E +\I_DMA_REGISTER/dma_decerr_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"0000" + INIT => X"E" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(5), - Q => \^out\(5) + I0 => p_55_out, + I1 => dma_decerr_reg_0, + O => dma_decerr_reg ); -\INFERRED_GEN.data_reg[3][60]_srl4\: unisim.vcomponents.SRL16E +\I_DMA_REGISTER/dma_slverr_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"0000" + INIT => X"E" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(45), - Q => \^out\(46) + I0 => p_54_out, + I1 => dma_slverr_reg_0, + O => dma_slverr_reg ); -\INFERRED_GEN.data_reg[3][61]_srl4\: unisim.vcomponents.SRL16E +decerr_i_reg: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(46), - Q => \^out\(47) + C => m_axi_mm2s_aclk, + CE => '1', + D => \INFERRED_GEN.cnt_i_reg[2]\, + Q => p_55_out, + R => SR(0) ); -\INFERRED_GEN.data_reg[3][62]_srl4\: unisim.vcomponents.SRL16E +err_i_i_1: unisim.vcomponents.LUT6 generic map( - INIT => X"0000" + INIT => X"FFFFFFFFFFFFFFFE" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(47), - Q => \^out\(48) + I0 => p_54_out, + I1 => zero_hsize_err, + I2 => zero_vsize_err, + I3 => \^err_i_reg_0\, + I4 => p_55_out, + I5 => \^stop_reg\, + O => err_i_i_1_n_0 ); -\INFERRED_GEN.data_reg[3][63]_srl4\: unisim.vcomponents.SRL16E +err_i_reg: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(48), - Q => \^out\(49) + C => m_axi_mm2s_aclk, + CE => '1', + D => err_i_i_1_n_0, + Q => \^stop_reg\, + R => SR(0) ); -\INFERRED_GEN.data_reg[3][6]_srl4\: unisim.vcomponents.SRL16E +interr_i_reg: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(6), - Q => \^out\(6) + C => m_axi_mm2s_aclk, + CE => '1', + D => \INFERRED_GEN.cnt_i_reg[2]_1\, + Q => \^err_i_reg_0\, + R => SR(0) ); -\INFERRED_GEN.data_reg[3][7]_srl4\: unisim.vcomponents.SRL16E - generic map( - INIT => X"0000" - ) - port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(7), - Q => \^out\(7) +\s_axis_cmd_tdata_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(0), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(0), + R => halted_reg(0) ); -\INFERRED_GEN.data_reg[3][8]_srl4\: unisim.vcomponents.SRL16E - generic map( - INIT => X"0000" - ) - port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(8), - Q => \^out\(8) +\s_axis_cmd_tdata_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(10), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(10), + R => halted_reg(0) ); -\INFERRED_GEN.data_reg[3][9]_srl4\: unisim.vcomponents.SRL16E - generic map( - INIT => X"0000" - ) - port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => \s_axis_cmd_tdata_reg[63]\(9), - Q => \^out\(9) +\s_axis_cmd_tdata_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(11), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(11), + R => halted_reg(0) ); -sig_calc_error_reg_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFFFFF00010000" - ) - port map ( - I0 => sig_calc_error_reg_i_2_n_0, - I1 => sig_calc_error_reg_i_3_n_0, - I2 => Q(2), - I3 => sig_sm_halt_reg, - I4 => sig_input_reg_empty, - I5 => \in\(0), - O => sig_calc_error_reg_reg +\s_axis_cmd_tdata_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(12), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(12), + R => halted_reg(0) ); -sig_calc_error_reg_i_2: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFFFFFFE" - ) - port map ( - I0 => \^out\(13), - I1 => \^out\(12), - I2 => \^out\(14), - I3 => \^out\(15), - I4 => sig_calc_error_reg_i_4_n_0, - O => sig_calc_error_reg_i_2_n_0 +\s_axis_cmd_tdata_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(13), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(13), + R => halted_reg(0) ); -sig_calc_error_reg_i_3: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFFFFFFE" - ) - port map ( - I0 => \^out\(5), - I1 => \^out\(4), - I2 => \^out\(7), - I3 => \^out\(6), - I4 => sig_calc_error_reg_i_5_n_0, - O => sig_calc_error_reg_i_3_n_0 +\s_axis_cmd_tdata_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(14), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(14), + R => halted_reg(0) ); -sig_calc_error_reg_i_4: unisim.vcomponents.LUT4 - generic map( - INIT => X"FFFE" - ) - port map ( - I0 => \^out\(10), - I1 => \^out\(11), - I2 => \^out\(8), - I3 => \^out\(9), - O => sig_calc_error_reg_i_4_n_0 +\s_axis_cmd_tdata_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(15), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(15), + R => halted_reg(0) ); -sig_calc_error_reg_i_5: unisim.vcomponents.LUT4 - generic map( - INIT => X"FFFE" - ) - port map ( - I0 => \^out\(2), - I1 => \^out\(3), - I2 => \^out\(0), - I3 => \^out\(1), - O => sig_calc_error_reg_i_5_n_0 +\s_axis_cmd_tdata_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(1), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(1), + R => halted_reg(0) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized0\ is - port ( - sig_wr_fifo : out STD_LOGIC; - interr_i_reg : out STD_LOGIC; - slverr_i_reg : out STD_LOGIC; - decerr_i_reg : out STD_LOGIC; - sig_rsc2stat_status_valid : in STD_LOGIC; - FIFO_Full_reg : in STD_LOGIC; - sig_inhibit_rdy_n_reg : in STD_LOGIC; - Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); - sig_rd_sts_slverr_reg_reg : in STD_LOGIC_VECTOR ( 2 downto 0 ); - m_axi_mm2s_aclk : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized0\ : entity is "dynshreg_f"; -end \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized0\; - -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized0\ is - signal m_axis_mm2s_sts_tdata : STD_LOGIC_VECTOR ( 6 downto 4 ); - signal \^sig_wr_fifo\ : STD_LOGIC; - attribute srl_bus_name : string; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][4]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name : string; - attribute srl_name of \INFERRED_GEN.data_reg[3][4]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][4]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][5]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][5]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][5]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][6]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][6]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][6]_srl4 "; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of interr_i_i_1 : label is "soft_lutpair74"; - attribute SOFT_HLUTNM of slverr_i_i_1 : label is "soft_lutpair74"; -begin - sig_wr_fifo <= \^sig_wr_fifo\; -\INFERRED_GEN.data_reg[3][4]_srl4\: unisim.vcomponents.SRL16E - generic map( - INIT => X"0000" - ) - port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => sig_rd_sts_slverr_reg_reg(0), - Q => m_axis_mm2s_sts_tdata(4) +\s_axis_cmd_tdata_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(16), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(16), + R => halted_reg(0) ); -\INFERRED_GEN.data_reg[3][4]_srl4_i_1__0\: unisim.vcomponents.LUT3 - generic map( - INIT => X"20" - ) - port map ( - I0 => sig_rsc2stat_status_valid, - I1 => FIFO_Full_reg, - I2 => sig_inhibit_rdy_n_reg, - O => \^sig_wr_fifo\ +\s_axis_cmd_tdata_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(2), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(2), + R => halted_reg(0) ); -\INFERRED_GEN.data_reg[3][5]_srl4\: unisim.vcomponents.SRL16E - generic map( - INIT => X"0000" - ) - port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => sig_rd_sts_slverr_reg_reg(1), - Q => m_axis_mm2s_sts_tdata(5) +\s_axis_cmd_tdata_reg[32]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(17), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(17), + R => halted_reg(0) ); -\INFERRED_GEN.data_reg[3][6]_srl4\: unisim.vcomponents.SRL16E - generic map( - INIT => X"0000" - ) - port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_wr_fifo\, - CLK => m_axi_mm2s_aclk, - D => sig_rd_sts_slverr_reg_reg(2), - Q => m_axis_mm2s_sts_tdata(6) +\s_axis_cmd_tdata_reg[33]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(18), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(18), + R => halted_reg(0) ); -decerr_i_i_1: unisim.vcomponents.LUT2 +\s_axis_cmd_tdata_reg[34]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(19), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(19), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[35]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(20), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(20), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[36]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(21), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(21), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[37]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(22), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(22), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[38]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(23), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(23), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[39]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(24), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(24), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(3), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(3), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[40]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(25), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(25), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[41]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(26), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(26), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[42]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(27), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(27), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[43]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(28), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(28), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[44]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(29), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(29), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[45]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(30), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(30), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[46]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(31), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(31), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[47]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(32), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(32), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[48]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(33), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(33), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[49]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(34), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(34), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(4), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(4), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[50]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(35), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(35), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[51]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(36), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(36), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[52]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(37), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(37), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[53]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(38), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(38), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[54]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(39), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(39), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[55]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(40), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(40), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[56]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(41), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(41), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[57]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(42), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(42), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[58]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(43), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(43), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[59]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(44), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(44), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(5), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(5), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[60]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(45), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(45), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[61]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(46), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(46), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[62]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(47), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(47), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[63]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(48), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(48), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(6), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(6), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(7), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(7), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(8), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(8), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => D(9), + Q => \sig_addr_cntr_lsh_kh_reg[31]\(9), + R => halted_reg(0) + ); +s_axis_cmd_tvalid_reg: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg_0\, + Q => \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg\, + R => halted_reg(0) + ); +slverr_i_reg: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => m_axis_mm2s_sts_tdata(5), - I1 => Q(2), - O => decerr_i_reg + C => m_axi_mm2s_aclk, + CE => '1', + D => \INFERRED_GEN.cnt_i_reg[2]_0\, + Q => p_54_out, + R => SR(0) ); -interr_i_i_1: unisim.vcomponents.LUT2 +stop_i_1: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"E" ) port map ( - I0 => m_axis_mm2s_sts_tdata(4), - I1 => Q(2), - O => interr_i_reg + I0 => \^stop_reg\, + I1 => p_77_out, + O => stop_i ); -slverr_i_i_1: unisim.vcomponents.LUT2 +sts_tready_reg: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => m_axis_mm2s_sts_tdata(6), - I1 => Q(2), - O => slverr_i_reg + C => m_axi_mm2s_aclk, + CE => '1', + D => mm2s_prmry_resetn, + Q => \^cmnds_queued_reg[0]\, + R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1\ is +entity \Arty_Z7_20_axi_vdma_0_0_axi_vdma_cmdsts_if__parameterized0\ is port ( - sig_calc_error_reg_reg : out STD_LOGIC; - sig_addr_valid_reg_reg : out STD_LOGIC; - \out\ : out STD_LOGIC_VECTOR ( 39 downto 0 ); - sig_mstr2addr_cmd_valid : in STD_LOGIC; - FIFO_Full_reg : in STD_LOGIC; - sig_inhibit_rdy_n : in STD_LOGIC; - \in\ : in STD_LOGIC_VECTOR ( 37 downto 0 ); - Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); - m_axi_mm2s_aclk : in STD_LOGIC + m_axis_s2mm_sts_tready : out STD_LOGIC; + err_i_reg_0 : out STD_LOGIC; + lsize_mismatch_err : out STD_LOGIC; + lsize_more_mismatch_err : out STD_LOGIC; + \vert_count_reg[0]\ : out STD_LOGIC; + \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + stop_i : out STD_LOGIC; + stop_reg : out STD_LOGIC; + \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_reg\ : out STD_LOGIC; + dma_slverr_reg : out STD_LOGIC; + dma_decerr_reg : out STD_LOGIC; + \sig_input_addr_reg_reg[31]\ : out STD_LOGIC_VECTOR ( 48 downto 0 ); + \out\ : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + \INFERRED_GEN.cnt_i_reg[2]\ : in STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[2]_0\ : in STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[2]_1\ : in STD_LOGIC; + p_12_out : in STD_LOGIC; + p_9_out : in STD_LOGIC; + halted_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg\ : in STD_LOGIC; + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : in STD_LOGIC; + flag_to_repeat_after_fsize_less_err : in STD_LOGIC; + s2mm_soft_reset : in STD_LOGIC; + repeat_frame : in STD_LOGIC; + valid_frame_sync_d2 : in STD_LOGIC; + dma_slverr_reg_0 : in STD_LOGIC; + dma_decerr_reg_0 : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 48 downto 0 ); + zero_vsize_err : in STD_LOGIC; + zero_hsize_err : in STD_LOGIC ); attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1\ : entity is "dynshreg_f"; -end \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1\; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_axi_vdma_cmdsts_if__parameterized0\ : entity is "axi_vdma_cmdsts_if"; +end \Arty_Z7_20_axi_vdma_0_0_axi_vdma_cmdsts_if__parameterized0\; -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1\ is - signal \^out\ : STD_LOGIC_VECTOR ( 39 downto 0 ); - signal \^sig_calc_error_reg_reg\ : STD_LOGIC; - attribute srl_bus_name : string; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][10]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name : string; - attribute srl_name of \INFERRED_GEN.data_reg[3][10]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][10]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][11]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][11]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][11]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][12]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][12]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][12]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][13]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][13]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][13]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][14]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][14]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][14]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][15]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][15]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][15]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][16]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][16]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][16]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][17]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][17]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][17]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][18]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][18]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][18]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][19]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][19]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][19]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][20]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][20]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][20]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][21]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][21]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][21]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][22]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][22]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][22]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][23]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][23]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][23]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][24]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][24]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][24]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][25]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][25]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][25]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][26]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][26]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][26]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][27]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][27]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][27]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][28]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][28]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][28]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][29]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][29]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][29]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][30]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][30]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][30]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][31]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][31]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][31]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][32]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][32]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][32]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][33]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][33]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][33]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][34]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][34]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][34]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][35]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][35]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][35]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][36]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][36]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][36]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][37]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][37]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][37]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][38]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][38]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][38]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][39]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][39]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][39]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][44]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][44]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][44]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][45]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][45]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][45]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][47]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][47]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][47]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][4]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][4]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][4]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][50]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][50]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][50]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][5]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][5]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][5]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][6]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][6]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][6]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][7]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][7]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][7]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][8]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][8]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][8]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][9]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][9]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][9]_srl4 "; +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_axi_vdma_cmdsts_if__parameterized0\ is + signal \^dynamic_master_mode_frame_cnt.repeat_frame_nmbr_reg[4]\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \err_i_i_1__0_n_0\ : STD_LOGIC; + signal \^err_i_reg_0\ : STD_LOGIC; + signal \^lsize_mismatch_err\ : STD_LOGIC; + signal \^lsize_more_mismatch_err\ : STD_LOGIC; + signal s2mm_dma_decerr_set : STD_LOGIC; + signal s2mm_dma_slverr_set : STD_LOGIC; + signal \^stop_reg\ : STD_LOGIC; begin - \out\(39 downto 0) <= \^out\(39 downto 0); - sig_calc_error_reg_reg <= \^sig_calc_error_reg_reg\; -\INFERRED_GEN.data_reg[3][10]_srl4\: unisim.vcomponents.SRL16E + \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr_reg[4]\(0) <= \^dynamic_master_mode_frame_cnt.repeat_frame_nmbr_reg[4]\(0); + err_i_reg_0 <= \^err_i_reg_0\; + lsize_mismatch_err <= \^lsize_mismatch_err\; + lsize_more_mismatch_err <= \^lsize_more_mismatch_err\; + stop_reg <= \^stop_reg\; +\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"0000" + INIT => X"E0E000E0" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(6), - Q => \^out\(6) + I0 => repeat_frame, + I1 => \^dynamic_master_mode_frame_cnt.repeat_frame_nmbr_reg[4]\(0), + I2 => \out\, + I3 => valid_frame_sync_d2, + I4 => flag_to_repeat_after_fsize_less_err, + O => \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_reg\ ); -\INFERRED_GEN.data_reg[3][11]_srl4\: unisim.vcomponents.SRL16E +\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr[4]_i_2\: unisim.vcomponents.LUT4 generic map( - INIT => X"0000" + INIT => X"FFFE" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(7), - Q => \^out\(7) + I0 => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\, + I1 => flag_to_repeat_after_fsize_less_err, + I2 => \^lsize_mismatch_err\, + I3 => \^lsize_more_mismatch_err\, + O => \^dynamic_master_mode_frame_cnt.repeat_frame_nmbr_reg[4]\(0) ); -\INFERRED_GEN.data_reg[3][12]_srl4\: unisim.vcomponents.SRL16E +\GEN_STS_GRTR_THAN_8.ovrflo_err_reg\: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(8), - Q => \^out\(8) + C => m_axi_s2mm_aclk, + CE => '1', + D => p_9_out, + Q => \^lsize_more_mismatch_err\, + R => SR(0) ); -\INFERRED_GEN.data_reg[3][13]_srl4\: unisim.vcomponents.SRL16E +\GEN_STS_GRTR_THAN_8.undrflo_err_reg\: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(9), - Q => \^out\(9) + C => m_axi_s2mm_aclk, + CE => '1', + D => p_12_out, + Q => \^lsize_mismatch_err\, + R => SR(0) ); -\INFERRED_GEN.data_reg[3][14]_srl4\: unisim.vcomponents.SRL16E +\I_DMA_REGISTER/dma_decerr_i_1__0\: unisim.vcomponents.LUT2 generic map( - INIT => X"0000" + INIT => X"E" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(10), - Q => \^out\(10) + I0 => s2mm_dma_decerr_set, + I1 => dma_decerr_reg_0, + O => dma_decerr_reg ); -\INFERRED_GEN.data_reg[3][15]_srl4\: unisim.vcomponents.SRL16E +\I_DMA_REGISTER/dma_slverr_i_1__0\: unisim.vcomponents.LUT2 generic map( - INIT => X"0000" + INIT => X"E" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(11), - Q => \^out\(11) + I0 => s2mm_dma_slverr_set, + I1 => dma_slverr_reg_0, + O => dma_slverr_reg ); -\INFERRED_GEN.data_reg[3][16]_srl4\: unisim.vcomponents.SRL16E +decerr_i_reg: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(12), - Q => \^out\(12) + C => m_axi_s2mm_aclk, + CE => '1', + D => \INFERRED_GEN.cnt_i_reg[2]\, + Q => s2mm_dma_decerr_set, + R => SR(0) ); -\INFERRED_GEN.data_reg[3][17]_srl4\: unisim.vcomponents.SRL16E +\err_i_i_1__0\: unisim.vcomponents.LUT6 generic map( - INIT => X"0000" + INIT => X"FFFFFFFFFFFFFFFE" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(13), - Q => \^out\(13) + I0 => s2mm_dma_decerr_set, + I1 => s2mm_dma_slverr_set, + I2 => \^err_i_reg_0\, + I3 => zero_vsize_err, + I4 => zero_hsize_err, + I5 => \^stop_reg\, + O => \err_i_i_1__0_n_0\ ); -\INFERRED_GEN.data_reg[3][18]_srl4\: unisim.vcomponents.SRL16E +err_i_reg: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(14), - Q => \^out\(14) + C => m_axi_s2mm_aclk, + CE => '1', + D => \err_i_i_1__0_n_0\, + Q => \^stop_reg\, + R => SR(0) ); -\INFERRED_GEN.data_reg[3][19]_srl4\: unisim.vcomponents.SRL16E +interr_i_reg: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(15), - Q => \^out\(15) + C => m_axi_s2mm_aclk, + CE => '1', + D => \INFERRED_GEN.cnt_i_reg[2]_1\, + Q => \^err_i_reg_0\, + R => SR(0) ); -\INFERRED_GEN.data_reg[3][20]_srl4\: unisim.vcomponents.SRL16E +\s_axis_cmd_tdata_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(0), + Q => \sig_input_addr_reg_reg[31]\(0), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(10), + Q => \sig_input_addr_reg_reg[31]\(10), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(11), + Q => \sig_input_addr_reg_reg[31]\(11), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(12), + Q => \sig_input_addr_reg_reg[31]\(12), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(13), + Q => \sig_input_addr_reg_reg[31]\(13), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(14), + Q => \sig_input_addr_reg_reg[31]\(14), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(15), + Q => \sig_input_addr_reg_reg[31]\(15), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(1), + Q => \sig_input_addr_reg_reg[31]\(1), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(16), + Q => \sig_input_addr_reg_reg[31]\(16), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(2), + Q => \sig_input_addr_reg_reg[31]\(2), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[32]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(17), + Q => \sig_input_addr_reg_reg[31]\(17), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[33]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(18), + Q => \sig_input_addr_reg_reg[31]\(18), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[34]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(19), + Q => \sig_input_addr_reg_reg[31]\(19), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[35]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(20), + Q => \sig_input_addr_reg_reg[31]\(20), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[36]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(21), + Q => \sig_input_addr_reg_reg[31]\(21), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[37]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(22), + Q => \sig_input_addr_reg_reg[31]\(22), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[38]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(23), + Q => \sig_input_addr_reg_reg[31]\(23), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[39]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(24), + Q => \sig_input_addr_reg_reg[31]\(24), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(3), + Q => \sig_input_addr_reg_reg[31]\(3), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[40]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(25), + Q => \sig_input_addr_reg_reg[31]\(25), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[41]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(26), + Q => \sig_input_addr_reg_reg[31]\(26), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[42]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(27), + Q => \sig_input_addr_reg_reg[31]\(27), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[43]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(28), + Q => \sig_input_addr_reg_reg[31]\(28), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[44]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(29), + Q => \sig_input_addr_reg_reg[31]\(29), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[45]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(30), + Q => \sig_input_addr_reg_reg[31]\(30), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[46]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(31), + Q => \sig_input_addr_reg_reg[31]\(31), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[47]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(32), + Q => \sig_input_addr_reg_reg[31]\(32), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[48]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(33), + Q => \sig_input_addr_reg_reg[31]\(33), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[49]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(34), + Q => \sig_input_addr_reg_reg[31]\(34), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(4), + Q => \sig_input_addr_reg_reg[31]\(4), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[50]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(35), + Q => \sig_input_addr_reg_reg[31]\(35), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[51]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(36), + Q => \sig_input_addr_reg_reg[31]\(36), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[52]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(37), + Q => \sig_input_addr_reg_reg[31]\(37), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[53]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(38), + Q => \sig_input_addr_reg_reg[31]\(38), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[54]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(39), + Q => \sig_input_addr_reg_reg[31]\(39), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[55]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(40), + Q => \sig_input_addr_reg_reg[31]\(40), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[56]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(41), + Q => \sig_input_addr_reg_reg[31]\(41), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[57]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(42), + Q => \sig_input_addr_reg_reg[31]\(42), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[58]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(43), + Q => \sig_input_addr_reg_reg[31]\(43), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[59]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(44), + Q => \sig_input_addr_reg_reg[31]\(44), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(5), + Q => \sig_input_addr_reg_reg[31]\(5), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[60]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(45), + Q => \sig_input_addr_reg_reg[31]\(45), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[61]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(46), + Q => \sig_input_addr_reg_reg[31]\(46), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[62]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(47), + Q => \sig_input_addr_reg_reg[31]\(47), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[63]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(48), + Q => \sig_input_addr_reg_reg[31]\(48), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(6), + Q => \sig_input_addr_reg_reg[31]\(6), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(7), + Q => \sig_input_addr_reg_reg[31]\(7), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(8), + Q => \sig_input_addr_reg_reg[31]\(8), + R => halted_reg(0) + ); +\s_axis_cmd_tdata_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => D(9), + Q => \sig_input_addr_reg_reg[31]\(9), + R => halted_reg(0) + ); +s_axis_cmd_tvalid_reg: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg\, + Q => \vert_count_reg[0]\, + R => halted_reg(0) + ); +slverr_i_reg: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(16), - Q => \^out\(16) + C => m_axi_s2mm_aclk, + CE => '1', + D => \INFERRED_GEN.cnt_i_reg[2]_0\, + Q => s2mm_dma_slverr_set, + R => SR(0) ); -\INFERRED_GEN.data_reg[3][21]_srl4\: unisim.vcomponents.SRL16E +\stop_i_1__0\: unisim.vcomponents.LUT2 generic map( - INIT => X"0000" + INIT => X"E" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(17), - Q => \^out\(17) + I0 => \^stop_reg\, + I1 => s2mm_soft_reset, + O => stop_i ); -\INFERRED_GEN.data_reg[3][22]_srl4\: unisim.vcomponents.SRL16E +sts_tready_reg: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(18), - Q => \^out\(18) + C => m_axi_s2mm_aclk, + CE => '1', + D => \out\, + Q => m_axis_s2mm_sts_tready, + R => '0' ); -\INFERRED_GEN.data_reg[3][23]_srl4\: unisim.vcomponents.SRL16E +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_fsync_gen is + port ( + p_24_out : out STD_LOGIC; + mask_fsync_out_i : out STD_LOGIC; + p_46_out : out STD_LOGIC; + prmry_in_xored : out STD_LOGIC; + p_4_out : out STD_LOGIC; + p_71_out : in STD_LOGIC_VECTOR ( 1 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + p_37_out : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + p_2_out : in STD_LOGIC; + prmry_resetn_i_reg : in STD_LOGIC; + p_47_out : in STD_LOGIC; + p_in_d1_cdc_from : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 7 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_fsync_gen : entity is "axi_vdma_fsync_gen"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_fsync_gen; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_fsync_gen is + signal \GEN_FREE_RUN_MODE.mask_fsync_out_i_i_3_n_0\ : STD_LOGIC; + signal all_idle_d1 : STD_LOGIC; + signal all_idle_d2 : STD_LOGIC; + signal p_23_out : STD_LOGIC; + signal \^p_24_out\ : STD_LOGIC; + signal \p_8_out__0\ : STD_LOGIC; +begin + p_24_out <= \^p_24_out\; +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__13\: unisim.vcomponents.LUT2 generic map( - INIT => X"0000" + INIT => X"6" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(19), - Q => \^out\(19) + I0 => p_23_out, + I1 => p_in_d1_cdc_from, + O => prmry_in_xored ); -\INFERRED_GEN.data_reg[3][24]_srl4\: unisim.vcomponents.SRL16E +\GEN_FREE_RUN_MODE.all_idle_d1_reg\: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(20), - Q => \^out\(20) + C => m_axi_mm2s_aclk, + CE => '1', + D => p_37_out, + Q => all_idle_d1, + R => SR(0) ); -\INFERRED_GEN.data_reg[3][25]_srl4\: unisim.vcomponents.SRL16E +\GEN_FREE_RUN_MODE.all_idle_d2_reg\: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(21), - Q => \^out\(21) + C => m_axi_mm2s_aclk, + CE => '1', + D => all_idle_d1, + Q => all_idle_d2, + R => SR(0) ); -\INFERRED_GEN.data_reg[3][26]_srl4\: unisim.vcomponents.SRL16E +\GEN_FREE_RUN_MODE.frame_sync_i_reg\: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(22), - Q => \^out\(22) + C => m_axi_mm2s_aclk, + CE => '1', + D => \p_8_out__0\, + Q => \^p_24_out\, + R => SR(0) ); -\INFERRED_GEN.data_reg[3][27]_srl4\: unisim.vcomponents.SRL16E +\GEN_FREE_RUN_MODE.frame_sync_out_reg\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => p_2_out, + Q => p_23_out, + R => SR(0) + ); +\GEN_FREE_RUN_MODE.mask_fsync_out_i_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"0000" + INIT => X"0000000000000010" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(23), - Q => \^out\(23) + I0 => Q(6), + I1 => Q(4), + I2 => \GEN_FREE_RUN_MODE.mask_fsync_out_i_i_3_n_0\, + I3 => Q(3), + I4 => Q(5), + I5 => Q(7), + O => p_4_out ); -\INFERRED_GEN.data_reg[3][28]_srl4\: unisim.vcomponents.SRL16E +\GEN_FREE_RUN_MODE.mask_fsync_out_i_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"0000" + INIT => X"0000000000008000" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(24), - Q => \^out\(24) + I0 => Q(0), + I1 => p_71_out(1), + I2 => \^p_24_out\, + I3 => p_47_out, + I4 => Q(1), + I5 => Q(2), + O => \GEN_FREE_RUN_MODE.mask_fsync_out_i_i_3_n_0\ ); -\INFERRED_GEN.data_reg[3][29]_srl4\: unisim.vcomponents.SRL16E +\GEN_FREE_RUN_MODE.mask_fsync_out_i_reg\: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(25), - Q => \^out\(25) + C => m_axi_mm2s_aclk, + CE => '1', + D => prmry_resetn_i_reg, + Q => mask_fsync_out_i, + R => '0' ); -\INFERRED_GEN.data_reg[3][30]_srl4\: unisim.vcomponents.SRL16E +\MASTER_MODE_FRAME_CNT.valid_frame_sync_d1_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"0000" + INIT => X"8" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(26), - Q => \^out\(26) + I0 => \^p_24_out\, + I1 => p_47_out, + O => p_46_out ); -\INFERRED_GEN.data_reg[3][31]_srl4\: unisim.vcomponents.SRL16E +p_8_out: unisim.vcomponents.LUT3 generic map( - INIT => X"0000" + INIT => X"40" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(27), - Q => \^out\(27) + I0 => all_idle_d2, + I1 => all_idle_d1, + I2 => p_71_out(0), + O => \p_8_out__0\ ); -\INFERRED_GEN.data_reg[3][32]_srl4\: unisim.vcomponents.SRL16E +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_axi_vdma_fsync_gen__parameterized0\ is + port ( + mask_fsync_out_i : out STD_LOGIC; + prmry_in_xored : out STD_LOGIC; + p_4_out : out STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + p_2_out : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + prmry_resetn_i_reg : in STD_LOGIC; + p_in_d1_cdc_from : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + s2mm_cdc2dmac_fsync : in STD_LOGIC; + s2mm_valid_video_prmtrs : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_axi_vdma_fsync_gen__parameterized0\ : entity is "axi_vdma_fsync_gen"; +end \Arty_Z7_20_axi_vdma_0_0_axi_vdma_fsync_gen__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_axi_vdma_fsync_gen__parameterized0\ is + signal \GEN_FSYNC_MODE_S2MM_FLUSH_SOF.mask_fsync_out_i_i_3_n_0\ : STD_LOGIC; + signal s2mm_dmac2cdc_fsync_out : STD_LOGIC; +begin +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__14\: unisim.vcomponents.LUT2 generic map( - INIT => X"0000" + INIT => X"6" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(28), - Q => \^out\(28) + I0 => s2mm_dmac2cdc_fsync_out, + I1 => p_in_d1_cdc_from, + O => prmry_in_xored ); -\INFERRED_GEN.data_reg[3][33]_srl4\: unisim.vcomponents.SRL16E +\GEN_FSYNC_MODE_S2MM_FLUSH_SOF.frame_sync_out_reg\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => p_2_out, + Q => s2mm_dmac2cdc_fsync_out, + R => SR(0) + ); +\GEN_FSYNC_MODE_S2MM_FLUSH_SOF.mask_fsync_out_i_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"0000" + INIT => X"0000000000000010" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(29), - Q => \^out\(29) + I0 => Q(6), + I1 => Q(4), + I2 => \GEN_FSYNC_MODE_S2MM_FLUSH_SOF.mask_fsync_out_i_i_3_n_0\, + I3 => Q(3), + I4 => Q(5), + I5 => Q(7), + O => p_4_out ); -\INFERRED_GEN.data_reg[3][34]_srl4\: unisim.vcomponents.SRL16E +\GEN_FSYNC_MODE_S2MM_FLUSH_SOF.mask_fsync_out_i_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"0000" + INIT => X"0000000000008000" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(30), - Q => \^out\(30) + I0 => Q(0), + I1 => \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[4]\(0), + I2 => s2mm_cdc2dmac_fsync, + I3 => s2mm_valid_video_prmtrs, + I4 => Q(1), + I5 => Q(2), + O => \GEN_FSYNC_MODE_S2MM_FLUSH_SOF.mask_fsync_out_i_i_3_n_0\ ); -\INFERRED_GEN.data_reg[3][35]_srl4\: unisim.vcomponents.SRL16E +\GEN_FSYNC_MODE_S2MM_FLUSH_SOF.mask_fsync_out_i_reg\: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(31), - Q => \^out\(31) + C => m_axi_s2mm_aclk, + CE => '1', + D => prmry_resetn_i_reg, + Q => mask_fsync_out_i, + R => '0' ); -\INFERRED_GEN.data_reg[3][36]_srl4\: unisim.vcomponents.SRL16E +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_genlock_mux is + port ( + data2 : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 1 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_genlock_mux : entity is "axi_vdma_genlock_mux"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_genlock_mux; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_genlock_mux is + signal \frame_ptr_out_reg_n_0_[2]\ : STD_LOGIC; + signal p_3_out : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \DYNAMIC_GENLOCK_FOR_MASTER.dm_binary_frame_ptr[0]_i_1\ : label is "soft_lutpair76"; + attribute SOFT_HLUTNM of \DYNAMIC_GENLOCK_FOR_MASTER.dm_binary_frame_ptr[1]_i_1\ : label is "soft_lutpair76"; +begin +\DYNAMIC_GENLOCK_FOR_MASTER.dm_binary_frame_ptr[0]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"0000" + INIT => X"9" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(32), - Q => \^out\(32) + I0 => p_3_out(1), + I1 => p_3_out(0), + O => D(0) ); -\INFERRED_GEN.data_reg[3][37]_srl4\: unisim.vcomponents.SRL16E +\DYNAMIC_GENLOCK_FOR_MASTER.dm_binary_frame_ptr[1]_i_1\: unisim.vcomponents.LUT1 generic map( - INIT => X"0000" + INIT => X"1" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(33), - Q => \^out\(33) + I0 => p_3_out(1), + O => D(1) ); -\INFERRED_GEN.data_reg[3][38]_srl4\: unisim.vcomponents.SRL16E +\DYNAMIC_GENLOCK_FOR_MASTER.dm_mstr_reverse_order_d1_i_1\: unisim.vcomponents.LUT1 generic map( - INIT => X"0000" + INIT => X"1" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(34), - Q => \^out\(34) + I0 => \frame_ptr_out_reg_n_0_[2]\, + O => data2 ); -\INFERRED_GEN.data_reg[3][39]_srl4\: unisim.vcomponents.SRL16E +\frame_ptr_out_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[2]\(0), + Q => p_3_out(0), + R => SR(0) + ); +\frame_ptr_out_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[2]\(1), + Q => p_3_out(1), + R => SR(0) + ); +\frame_ptr_out_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[2]\(2), + Q => \frame_ptr_out_reg_n_0_[2]\, + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_greycoder is + port ( + D : out STD_LOGIC_VECTOR ( 1 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 2 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_greycoder : entity is "axi_vdma_greycoder"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_greycoder; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_greycoder is + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \DYNAMIC_GENLOCK_FOR_MASTER.frame_ptr_out[0]_i_1\ : label is "soft_lutpair77"; + attribute SOFT_HLUTNM of \DYNAMIC_GENLOCK_FOR_MASTER.frame_ptr_out[1]_i_1\ : label is "soft_lutpair77"; +begin +\DYNAMIC_GENLOCK_FOR_MASTER.frame_ptr_out[0]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"0000" + INIT => X"6" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(35), - Q => \^out\(35) + I0 => Q(1), + I1 => Q(0), + O => D(0) ); -\INFERRED_GEN.data_reg[3][44]_srl4\: unisim.vcomponents.SRL16E +\DYNAMIC_GENLOCK_FOR_MASTER.frame_ptr_out[1]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"0000" + INIT => X"6" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => '1', - Q => \^out\(36) + I0 => Q(2), + I1 => Q(1), + O => D(1) ); -\INFERRED_GEN.data_reg[3][45]_srl4\: unisim.vcomponents.SRL16E +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_greycoder_45 is + port ( + D : out STD_LOGIC_VECTOR ( 1 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 2 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_greycoder_45 : entity is "axi_vdma_greycoder"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_greycoder_45; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_greycoder_45 is + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \GENLOCK_FOR_MASTER.frame_ptr_out[0]_i_1\ : label is "soft_lutpair40"; + attribute SOFT_HLUTNM of \GENLOCK_FOR_MASTER.frame_ptr_out[1]_i_1\ : label is "soft_lutpair40"; +begin +\GENLOCK_FOR_MASTER.frame_ptr_out[0]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"0000" + INIT => X"6" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => '1', - Q => \^out\(37) + I0 => Q(1), + I1 => Q(0), + O => D(0) ); -\INFERRED_GEN.data_reg[3][47]_srl4\: unisim.vcomponents.SRL16E +\GENLOCK_FOR_MASTER.frame_ptr_out[1]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"0000" + INIT => X"6" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(36), - Q => \^out\(38) + I0 => Q(2), + I1 => Q(1), + O => D(1) ); -\INFERRED_GEN.data_reg[3][4]_srl4\: unisim.vcomponents.SRL16E +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_intrpt is + port ( + ch1_delay_cnt_en : out STD_LOGIC; + ch1_dly_irq_set : out STD_LOGIC; + ch2_delay_cnt_en : out STD_LOGIC; + ch2_dly_irq_set : out STD_LOGIC; + mm2s_ioc_irq_set : out STD_LOGIC; + ch2_irqthresh_decr_mask_sig : out STD_LOGIC; + s2mm_ioc_irq_set : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 7 downto 0 ); + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); + \GEN_FREE_RUN_MODE.mask_fsync_out_i_reg\ : out STD_LOGIC; + \GEN_FSYNC_MODE_S2MM_FLUSH_SOF.mask_fsync_out_i_reg\ : out STD_LOGIC; + \MASTER_MODE_FRAME_CNT.tstvect_fsync_reg\ : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg\ : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + prmry_resetn_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg_0\ : in STD_LOGIC; + ch1_delay_zero : in STD_LOGIC; + p_17_out : in STD_LOGIC; + p_71_out : in STD_LOGIC_VECTOR ( 15 downto 0 ); + p_13_out : in STD_LOGIC; + ch2_delay_zero : in STD_LOGIC; + s2mm_packet_sof : in STD_LOGIC; + s2mm_dmacr : in STD_LOGIC_VECTOR ( 15 downto 0 ); + p_6_out : in STD_LOGIC; + s2mm_tstvect_fsync : in STD_LOGIC; + p_50_out : in STD_LOGIC; + \out\ : in STD_LOGIC; + prmry_resetn_i_reg_0 : in STD_LOGIC; + p_4_out : in STD_LOGIC; + mask_fsync_out_i : in STD_LOGIC; + p_4_out_0 : in STD_LOGIC; + mask_fsync_out_i_1 : in STD_LOGIC; + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_reg_0\ : in STD_LOGIC; + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : in STD_LOGIC; + prmry_resetn_i_reg_1 : in STD_LOGIC; + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out_0\ : in STD_LOGIC; + prmry_resetn_i_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_intrpt : entity is "axi_vdma_intrpt"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_intrpt; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_intrpt is + signal \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[1]_i_2_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_3_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_1_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_4_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_3_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_4_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_6_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_7_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_i_1_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[6]_i_2_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_4_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_6_n_0\ : STD_LOGIC; + signal \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[1]_i_2_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[6]_i_3_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[0]\ : STD_LOGIC; + signal \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[1]\ : STD_LOGIC; + signal \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[2]\ : STD_LOGIC; + signal \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[3]\ : STD_LOGIC; + signal \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[4]\ : STD_LOGIC; + signal \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[5]\ : STD_LOGIC; + signal \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[6]\ : STD_LOGIC; + signal \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_reg_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_1_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_4_n_0\ : STD_LOGIC; + signal \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_3_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_4_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_6_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_7_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_ioc_irq_set_i_i_1_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[0]_i_1_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[1]_i_1_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[2]_i_1_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[3]_i_1_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[4]_i_1_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[5]_i_1_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[6]_i_1_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[6]_i_2_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_2_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_3_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_5_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_6_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_7_n_0\ : STD_LOGIC; + signal \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal L : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \^ch1_delay_cnt_en\ : STD_LOGIC; + signal ch1_dly_fast_cnt : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal ch1_dly_fast_incr : STD_LOGIC; + signal ch1_ioc_irq_set_i : STD_LOGIC; + signal \^ch2_delay_cnt_en\ : STD_LOGIC; + signal ch2_dly_fast_cnt : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal ch2_dly_fast_incr : STD_LOGIC; + signal ch2_ioc_irq_set_i : STD_LOGIC; + signal \^ch2_irqthresh_decr_mask_sig\ : STD_LOGIC; + signal \^mm2s_ioc_irq_set\ : STD_LOGIC; + signal p_12_out : STD_LOGIC; + signal p_26_out : STD_LOGIC; + signal p_2_in : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \plusOp__0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \^s2mm_ioc_irq_set\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[0]_i_1\ : label is "soft_lutpair97"; + attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[1]_i_1\ : label is "soft_lutpair97"; + attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[2]_i_1\ : label is "soft_lutpair100"; + attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[3]_i_1\ : label is "soft_lutpair91"; + attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[4]_i_1\ : label is "soft_lutpair91"; + attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_3\ : label is "soft_lutpair100"; + attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[1]_i_1\ : label is "soft_lutpair98"; + attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[2]_i_1\ : label is "soft_lutpair98"; + attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[3]_i_1\ : label is "soft_lutpair90"; + attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[4]_i_1\ : label is "soft_lutpair90"; + attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_2\ : label is "soft_lutpair92"; + attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_3\ : label is "soft_lutpair92"; + attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[6]_i_2\ : label is "soft_lutpair94"; + attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_6\ : label is "soft_lutpair94"; + attribute SOFT_HLUTNM of \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[0]_i_1\ : label is "soft_lutpair96"; + attribute SOFT_HLUTNM of \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[1]_i_1\ : label is "soft_lutpair96"; + attribute SOFT_HLUTNM of \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[2]_i_1\ : label is "soft_lutpair101"; + attribute SOFT_HLUTNM of \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[3]_i_1\ : label is "soft_lutpair88"; + attribute SOFT_HLUTNM of \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[4]_i_1\ : label is "soft_lutpair88"; + attribute SOFT_HLUTNM of \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[6]_i_3\ : label is "soft_lutpair101"; + attribute SOFT_HLUTNM of \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[1]_i_1\ : label is "soft_lutpair99"; + attribute SOFT_HLUTNM of \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[2]_i_1\ : label is "soft_lutpair99"; + attribute SOFT_HLUTNM of \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[3]_i_1\ : label is "soft_lutpair89"; + attribute SOFT_HLUTNM of \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[4]_i_1\ : label is "soft_lutpair89"; + attribute SOFT_HLUTNM of \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_2\ : label is "soft_lutpair95"; + attribute SOFT_HLUTNM of \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_3\ : label is "soft_lutpair95"; + attribute SOFT_HLUTNM of \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[6]_i_2\ : label is "soft_lutpair93"; + attribute SOFT_HLUTNM of \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_7\ : label is "soft_lutpair93"; +begin + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0\(7 downto 0) <= \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(7 downto 0); + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0\(7 downto 0) <= \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(7 downto 0); + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0\(7 downto 0) <= \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(7 downto 0); + Q(7 downto 0) <= \^q\(7 downto 0); + ch1_delay_cnt_en <= \^ch1_delay_cnt_en\; + ch2_delay_cnt_en <= \^ch2_delay_cnt_en\; + ch2_irqthresh_decr_mask_sig <= \^ch2_irqthresh_decr_mask_sig\; + mm2s_ioc_irq_set <= \^mm2s_ioc_irq_set\; + s2mm_ioc_irq_set <= \^s2mm_ioc_irq_set\; +\GEN_FREE_RUN_MODE.mask_fsync_out_i_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"0000" + INIT => X"08C8" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(0), - Q => \^out\(0) + I0 => p_4_out, + I1 => \out\, + I2 => mask_fsync_out_i, + I3 => \^mm2s_ioc_irq_set\, + O => \GEN_FREE_RUN_MODE.mask_fsync_out_i_reg\ ); -\INFERRED_GEN.data_reg[3][4]_srl4_i_1\: unisim.vcomponents.LUT3 +\GEN_FSYNC_MODE_S2MM_FLUSH_SOF.mask_fsync_out_i_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"20" + INIT => X"08C8" ) port map ( - I0 => sig_mstr2addr_cmd_valid, - I1 => FIFO_Full_reg, - I2 => sig_inhibit_rdy_n, - O => \^sig_calc_error_reg_reg\ + I0 => p_4_out_0, + I1 => prmry_resetn_i_reg_0, + I2 => mask_fsync_out_i_1, + I3 => \^s2mm_ioc_irq_set\, + O => \GEN_FSYNC_MODE_S2MM_FLUSH_SOF.mask_fsync_out_i_reg\ ); -\INFERRED_GEN.data_reg[3][50]_srl4\: unisim.vcomponents.SRL16E +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[0]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"0000" + INIT => X"32" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(37), - Q => \^out\(39) + I0 => L(1), + I1 => L(0), + I2 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[1]_i_2_n_0\, + O => ch1_dly_fast_cnt(0) ); -\INFERRED_GEN.data_reg[3][5]_srl4\: unisim.vcomponents.SRL16E +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[1]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"0000" + INIT => X"98" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(1), - Q => \^out\(1) + I0 => L(0), + I1 => L(1), + I2 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[1]_i_2_n_0\, + O => ch1_dly_fast_cnt(1) ); -\INFERRED_GEN.data_reg[3][6]_srl4\: unisim.vcomponents.SRL16E +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[1]_i_2\: unisim.vcomponents.LUT5 generic map( - INIT => X"0000" + INIT => X"FFFFFFFE" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(2), - Q => \^out\(2) + I0 => L(5), + I1 => L(3), + I2 => L(2), + I3 => L(4), + I4 => L(6), + O => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[1]_i_2_n_0\ ); -\INFERRED_GEN.data_reg[3][7]_srl4\: unisim.vcomponents.SRL16E +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[2]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"0000" + INIT => X"A9" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(3), - Q => \^out\(3) + I0 => L(2), + I1 => L(0), + I2 => L(1), + O => ch1_dly_fast_cnt(2) ); -\INFERRED_GEN.data_reg[3][8]_srl4\: unisim.vcomponents.SRL16E +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[3]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"0000" + INIT => X"FE01" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(4), - Q => \^out\(4) + I0 => L(0), + I1 => L(1), + I2 => L(2), + I3 => L(3), + O => ch1_dly_fast_cnt(3) ); -\INFERRED_GEN.data_reg[3][9]_srl4\: unisim.vcomponents.SRL16E +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[4]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"0000" + INIT => X"FFFE0001" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => \^sig_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(5), - Q => \^out\(5) + I0 => L(0), + I1 => L(1), + I2 => L(3), + I3 => L(2), + I4 => L(4), + O => ch1_dly_fast_cnt(4) ); -sig_addr_valid_reg_i_1: unisim.vcomponents.LUT1 +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[5]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"1" + INIT => X"FFFFFFFE00000001" ) port map ( - I0 => \^out\(39), - O => sig_addr_valid_reg_reg + I0 => L(0), + I1 => L(1), + I2 => L(4), + I3 => L(2), + I4 => L(3), + I5 => L(5), + O => ch1_dly_fast_cnt(5) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized2\ is - port ( - sig_next_calc_error_reg_reg : out STD_LOGIC; - D : out STD_LOGIC_VECTOR ( 3 downto 0 ); - sig_last_dbeat_reg : out STD_LOGIC; - \out\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); - sig_mstr2data_cmd_valid : in STD_LOGIC; - FIFO_Full_reg : in STD_LOGIC; - sig_inhibit_rdy_n_0 : in STD_LOGIC; - sig_next_sequential_reg_reg : in STD_LOGIC; - Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); - sig_halt_reg_reg : in STD_LOGIC; - \sig_dbeat_cntr_reg[2]\ : in STD_LOGIC; - sig_dbeat_cntr_eq_1 : in STD_LOGIC; - sig_last_dbeat : in STD_LOGIC; - \in\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); - \INFERRED_GEN.cnt_i_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); - m_axi_mm2s_aclk : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized2\ : entity is "dynshreg_f"; -end \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized2\; - -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized2\ is - signal sig_cmd_fifo_data_out : STD_LOGIC_VECTOR ( 10 downto 7 ); - signal sig_last_dbeat_i_2_n_0 : STD_LOGIC; - signal \^sig_next_calc_error_reg_reg\ : STD_LOGIC; - attribute srl_bus_name : string; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][10]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name : string; - attribute srl_name of \INFERRED_GEN.data_reg[3][10]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][10]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][32]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][32]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][32]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][33]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][33]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][33]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][34]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][34]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][34]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][35]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][35]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][35]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][7]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][7]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][7]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][8]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][8]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][8]_srl4 "; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][9]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name of \INFERRED_GEN.data_reg[3][9]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][9]_srl4 "; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \sig_dbeat_cntr[0]_i_1\ : label is "soft_lutpair107"; - attribute SOFT_HLUTNM of \sig_dbeat_cntr[1]_i_1\ : label is "soft_lutpair107"; -begin - sig_next_calc_error_reg_reg <= \^sig_next_calc_error_reg_reg\; -\INFERRED_GEN.data_reg[3][10]_srl4\: unisim.vcomponents.SRL16E +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"0000" + INIT => X"FFFFFFFE00000001" ) port map ( - A0 => \INFERRED_GEN.cnt_i_reg[1]\(0), - A1 => \INFERRED_GEN.cnt_i_reg[1]\(1), - A2 => '0', - A3 => '0', - CE => \^sig_next_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(3), - Q => sig_cmd_fifo_data_out(10) + I0 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_3_n_0\, + I1 => L(5), + I2 => L(3), + I3 => L(2), + I4 => L(4), + I5 => L(6), + O => ch1_dly_fast_cnt(6) ); -\INFERRED_GEN.data_reg[3][32]_srl4\: unisim.vcomponents.SRL16E +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_3\: unisim.vcomponents.LUT2 generic map( - INIT => X"0000" + INIT => X"E" ) port map ( - A0 => \INFERRED_GEN.cnt_i_reg[1]\(0), - A1 => \INFERRED_GEN.cnt_i_reg[1]\(1), - A2 => '0', - A3 => '0', - CE => \^sig_next_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(4), - Q => \out\(0) + I0 => L(0), + I1 => L(1), + O => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_3_n_0\ ); -\INFERRED_GEN.data_reg[3][33]_srl4\: unisim.vcomponents.SRL16E +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => \INFERRED_GEN.cnt_i_reg[1]\(0), - A1 => \INFERRED_GEN.cnt_i_reg[1]\(1), - A2 => '0', - A3 => '0', - CE => \^sig_next_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(5), - Q => \out\(1) - ); -\INFERRED_GEN.data_reg[3][34]_srl4\: unisim.vcomponents.SRL16E + C => m_axi_mm2s_aclk, + CE => '1', + D => ch1_dly_fast_cnt(0), + Q => L(0), + R => SR(0) + ); +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[1]\: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => \INFERRED_GEN.cnt_i_reg[1]\(0), - A1 => \INFERRED_GEN.cnt_i_reg[1]\(1), - A2 => '0', - A3 => '0', - CE => \^sig_next_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(6), - Q => \out\(2) + C => m_axi_mm2s_aclk, + CE => '1', + D => ch1_dly_fast_cnt(1), + Q => L(1), + R => SR(0) ); -\INFERRED_GEN.data_reg[3][35]_srl4\: unisim.vcomponents.SRL16E +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[2]\: unisim.vcomponents.FDSE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => \INFERRED_GEN.cnt_i_reg[1]\(0), - A1 => \INFERRED_GEN.cnt_i_reg[1]\(1), - A2 => '0', - A3 => '0', - CE => \^sig_next_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(7), - Q => \out\(3) + C => m_axi_mm2s_aclk, + CE => '1', + D => ch1_dly_fast_cnt(2), + Q => L(2), + S => SR(0) ); -\INFERRED_GEN.data_reg[3][7]_srl4\: unisim.vcomponents.SRL16E +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[3]\: unisim.vcomponents.FDSE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => \INFERRED_GEN.cnt_i_reg[1]\(0), - A1 => \INFERRED_GEN.cnt_i_reg[1]\(1), - A2 => '0', - A3 => '0', - CE => \^sig_next_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(0), - Q => sig_cmd_fifo_data_out(7) + C => m_axi_mm2s_aclk, + CE => '1', + D => ch1_dly_fast_cnt(3), + Q => L(3), + S => SR(0) ); -\INFERRED_GEN.data_reg[3][7]_srl4_i_1__0\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[4]\: unisim.vcomponents.FDSE generic map( - INIT => X"20" + INIT => '0' ) port map ( - I0 => sig_mstr2data_cmd_valid, - I1 => FIFO_Full_reg, - I2 => sig_inhibit_rdy_n_0, - O => \^sig_next_calc_error_reg_reg\ + C => m_axi_mm2s_aclk, + CE => '1', + D => ch1_dly_fast_cnt(4), + Q => L(4), + S => SR(0) ); -\INFERRED_GEN.data_reg[3][8]_srl4\: unisim.vcomponents.SRL16E +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[5]\: unisim.vcomponents.FDSE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => \INFERRED_GEN.cnt_i_reg[1]\(0), - A1 => \INFERRED_GEN.cnt_i_reg[1]\(1), - A2 => '0', - A3 => '0', - CE => \^sig_next_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(1), - Q => sig_cmd_fifo_data_out(8) + C => m_axi_mm2s_aclk, + CE => '1', + D => ch1_dly_fast_cnt(5), + Q => L(5), + S => SR(0) ); -\INFERRED_GEN.data_reg[3][9]_srl4\: unisim.vcomponents.SRL16E +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]\: unisim.vcomponents.FDSE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => \INFERRED_GEN.cnt_i_reg[1]\(0), - A1 => \INFERRED_GEN.cnt_i_reg[1]\(1), - A2 => '0', - A3 => '0', - CE => \^sig_next_calc_error_reg_reg\, - CLK => m_axi_mm2s_aclk, - D => \in\(2), - Q => sig_cmd_fifo_data_out(9) + C => m_axi_mm2s_aclk, + CE => '1', + D => ch1_dly_fast_cnt(6), + Q => L(6), + S => SR(0) ); -\sig_dbeat_cntr[0]_i_1\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"8B" + INIT => X"0000000000000001" ) port map ( - I0 => sig_cmd_fifo_data_out(7), - I1 => sig_next_sequential_reg_reg, - I2 => Q(0), - O => D(0) + I0 => L(6), + I1 => L(4), + I2 => L(2), + I3 => L(3), + I4 => L(5), + I5 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_3_n_0\, + O => ch1_dly_fast_incr ); -\sig_dbeat_cntr[1]_i_1\: unisim.vcomponents.LUT4 +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg\: unisim.vcomponents.FDRE generic map( - INIT => X"B88B" + INIT => '0' ) port map ( - I0 => sig_cmd_fifo_data_out(8), - I1 => sig_next_sequential_reg_reg, - I2 => Q(0), - I3 => Q(1), - O => D(1) + C => m_axi_mm2s_aclk, + CE => '1', + D => ch1_dly_fast_incr, + Q => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0\, + R => SR(0) ); -\sig_dbeat_cntr[2]_i_1\: unisim.vcomponents.LUT5 +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg\: unisim.vcomponents.FDRE generic map( - INIT => X"BBB8888B" + INIT => '0' ) port map ( - I0 => sig_cmd_fifo_data_out(9), - I1 => sig_next_sequential_reg_reg, - I2 => Q(1), - I3 => Q(0), - I4 => Q(2), - O => D(2) + C => m_axi_mm2s_aclk, + CE => '1', + D => \MASTER_MODE_FRAME_CNT.tstvect_fsync_reg\, + Q => \^ch1_delay_cnt_en\, + R => '0' ); -\sig_dbeat_cntr[3]_i_1\: unisim.vcomponents.LUT6 +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[0]_i_1\: unisim.vcomponents.LUT1 generic map( - INIT => X"BBBBBBB88888888B" + INIT => X"1" ) port map ( - I0 => sig_cmd_fifo_data_out(10), - I1 => sig_next_sequential_reg_reg, - I2 => Q(2), - I3 => Q(0), - I4 => Q(1), - I5 => Q(3), - O => D(3) + I0 => \^q\(0), + O => plusOp(0) ); -sig_last_dbeat_i_1: unisim.vcomponents.LUT6 +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[1]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"AFAFA0AFACACA0A0" + INIT => X"6" ) port map ( - I0 => sig_last_dbeat_i_2_n_0, - I1 => sig_halt_reg_reg, - I2 => sig_next_sequential_reg_reg, - I3 => \sig_dbeat_cntr_reg[2]\, - I4 => sig_dbeat_cntr_eq_1, - I5 => sig_last_dbeat, - O => sig_last_dbeat_reg + I0 => \^q\(0), + I1 => \^q\(1), + O => plusOp(1) ); -sig_last_dbeat_i_2: unisim.vcomponents.LUT4 +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[2]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"0001" + INIT => X"78" ) port map ( - I0 => sig_cmd_fifo_data_out(9), - I1 => sig_cmd_fifo_data_out(10), - I2 => sig_cmd_fifo_data_out(7), - I3 => sig_cmd_fifo_data_out(8), - O => sig_last_dbeat_i_2_n_0 + I0 => \^q\(0), + I1 => \^q\(1), + I2 => \^q\(2), + O => plusOp(2) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized3\ is - port ( - p_0_out : out STD_LOGIC_VECTOR ( 0 to 0 ); - sig_cmd2dre_valid_reg : in STD_LOGIC; - \in\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); - m_axi_mm2s_aclk : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized3\ : entity is "dynshreg_f"; -end \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized3\; - -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized3\ is - attribute srl_bus_name : string; - attribute srl_bus_name of \INFERRED_GEN.data_reg[3][7]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; - attribute srl_name : string; - attribute srl_name of \INFERRED_GEN.data_reg[3][7]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][7]_srl4 "; -begin -\INFERRED_GEN.data_reg[3][7]_srl4\: unisim.vcomponents.SRL16E +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[3]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"0000" + INIT => X"7F80" ) port map ( - A0 => Q(0), - A1 => Q(1), - A2 => '0', - A3 => '0', - CE => sig_cmd2dre_valid_reg, - CLK => m_axi_mm2s_aclk, - D => \in\(0), - Q => p_0_out(0) + I0 => \^q\(2), + I1 => \^q\(1), + I2 => \^q\(0), + I3 => \^q\(3), + O => plusOp(3) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_wrapper is - port ( - DOBDO : out STD_LOGIC_VECTOR ( 0 to 0 ); - \sig_user_skid_reg_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - dm2linebuf_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : out STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[0]\ : out STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - ram_empty_fb_i_reg : in STD_LOGIC; - ram_full_i_reg : in STD_LOGIC; - \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC; - sig_stream_rst : in STD_LOGIC; - \gc1.count_d2_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); - Q : in STD_LOGIC_VECTOR ( 6 downto 0 ); - m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); - DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ); - lsig_0ffset_cntr : in STD_LOGIC; - lsig_cmd_loaded : in STD_LOGIC; - \gpregsm1.user_valid_reg\ : in STD_LOGIC; - hold_ff_q : in STD_LOGIC; - p_0_out : in STD_LOGIC_VECTOR ( 0 to 0 ); - dm2linebuf_mm2s_tvalid : in STD_LOGIC; - p_8_out : in STD_LOGIC; - \fifo_wren__0\ : in STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper"; -end Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_wrapper; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_wrapper is - signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_53\ : STD_LOGIC; - signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85\ : STD_LOGIC; - signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87\ : STD_LOGIC; - signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89\ : STD_LOGIC; - signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90\ : STD_LOGIC; - signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91\ : STD_LOGIC; - signal \^dobdo\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \INCLUDE_UNPACKING.lsig_0ffset_cntr[0]_i_2_n_0\ : STD_LOGIC; - signal sig_data_fifo_data_out : STD_LOGIC_VECTOR ( 64 downto 0 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); - attribute CLOCK_DOMAINS : string; - attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : label is "COMMON"; - attribute box_type : string; - attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : label is "PRIMITIVE"; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \INCLUDE_UNPACKING.lsig_0ffset_cntr[0]_i_2\ : label is "soft_lutpair51"; - attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[2]_i_2\ : label is "soft_lutpair51"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_10\ : label is "soft_lutpair53"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_11\ : label is "soft_lutpair52"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_12\ : label is "soft_lutpair56"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_1__0\ : label is "soft_lutpair60"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_1__1\ : label is "soft_lutpair64"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_2\ : label is "soft_lutpair59"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_2__0\ : label is "soft_lutpair64"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_2__1\ : label is "soft_lutpair67"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_3__0\ : label is "soft_lutpair59"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_3__1\ : label is "soft_lutpair63"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_3__2\ : label is "soft_lutpair67"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_4\ : label is "soft_lutpair55"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_4__0\ : label is "soft_lutpair58"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_4__1\ : label is "soft_lutpair63"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_4__2\ : label is "soft_lutpair66"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_5\ : label is "soft_lutpair55"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_5__0\ : label is "soft_lutpair58"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_5__1\ : label is "soft_lutpair62"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_5__2\ : label is "soft_lutpair66"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_6\ : label is "soft_lutpair54"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_6__0\ : label is "soft_lutpair57"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_6__1\ : label is "soft_lutpair62"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_6__2\ : label is "soft_lutpair65"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_7\ : label is "soft_lutpair53"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_7__0\ : label is "soft_lutpair57"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_7__1\ : label is "soft_lutpair61"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_8\ : label is "soft_lutpair52"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_8__0\ : label is "soft_lutpair56"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_8__1\ : label is "soft_lutpair61"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_9\ : label is "soft_lutpair54"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_9__0\ : label is "soft_lutpair60"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_9__1\ : label is "soft_lutpair65"; -begin - DOBDO(0) <= \^dobdo\(0); -\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\: unisim.vcomponents.RAMB36E1 +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[4]_i_1\: unisim.vcomponents.LUT5 generic map( - DOA_REG => 1, - DOB_REG => 1, - EN_ECC_READ => false, - EN_ECC_WRITE => false, - INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_A => X"000000000", - INIT_B => X"000000000", - INIT_FILE => "NONE", - IS_CLKARDCLK_INVERTED => '0', - IS_CLKBWRCLK_INVERTED => '0', - IS_ENARDEN_INVERTED => '0', - IS_ENBWREN_INVERTED => '0', - IS_RSTRAMARSTRAM_INVERTED => '0', - IS_RSTRAMB_INVERTED => '0', - IS_RSTREGARSTREG_INVERTED => '0', - IS_RSTREGB_INVERTED => '0', - RAM_EXTENSION_A => "NONE", - RAM_EXTENSION_B => "NONE", - RAM_MODE => "SDP", - RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", - READ_WIDTH_A => 72, - READ_WIDTH_B => 0, - RSTREG_PRIORITY_A => "REGCE", - RSTREG_PRIORITY_B => "REGCE", - SIM_COLLISION_CHECK => "ALL", - SIM_DEVICE => "7SERIES", - SRVAL_A => X"000000000", - SRVAL_B => X"000000000", - WRITE_MODE_A => "READ_FIRST", - WRITE_MODE_B => "READ_FIRST", - WRITE_WIDTH_A => 0, - WRITE_WIDTH_B => 72 + INIT => X"7FFF8000" ) port map ( - ADDRARDADDR(15 downto 13) => B"100", - ADDRARDADDR(12 downto 6) => \gc1.count_d2_reg[6]\(6 downto 0), - ADDRARDADDR(5 downto 0) => B"111111", - ADDRBWRADDR(15 downto 13) => B"100", - ADDRBWRADDR(12 downto 6) => Q(6 downto 0), - ADDRBWRADDR(5 downto 0) => B"111111", - CASCADEINA => '0', - CASCADEINB => '0', - CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED\, - CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED\, - CLKARDCLK => m_axi_mm2s_aclk, - CLKBWRCLK => m_axi_mm2s_aclk, - DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED\, - DIADI(31 downto 24) => m_axi_mm2s_rdata(33 downto 26), - DIADI(23 downto 8) => m_axi_mm2s_rdata(24 downto 9), - DIADI(7 downto 0) => m_axi_mm2s_rdata(7 downto 0), - DIBDI(31) => '0', - DIBDI(30 downto 29) => DIBDI(1 downto 0), - DIBDI(28 downto 8) => m_axi_mm2s_rdata(63 downto 43), - DIBDI(7 downto 0) => m_axi_mm2s_rdata(41 downto 34), - DIPADIP(3) => '0', - DIPADIP(2) => m_axi_mm2s_rdata(25), - DIPADIP(1) => '0', - DIPADIP(0) => m_axi_mm2s_rdata(8), - DIPBDIP(3 downto 1) => B"000", - DIPBDIP(0) => m_axi_mm2s_rdata(42), - DOADO(31 downto 24) => sig_data_fifo_data_out(33 downto 26), - DOADO(23 downto 8) => sig_data_fifo_data_out(24 downto 9), - DOADO(7 downto 0) => sig_data_fifo_data_out(7 downto 0), - DOBDO(31) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_53\, - DOBDO(30) => \^dobdo\(0), - DOBDO(29 downto 8) => sig_data_fifo_data_out(64 downto 43), - DOBDO(7 downto 0) => sig_data_fifo_data_out(41 downto 34), - DOPADOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85\, - DOPADOP(2) => sig_data_fifo_data_out(25), - DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87\, - DOPADOP(0) => sig_data_fifo_data_out(8), - DOPBDOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89\, - DOPBDOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90\, - DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91\, - DOPBDOP(0) => sig_data_fifo_data_out(42), - ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED\(7 downto 0), - ENARDEN => ram_empty_fb_i_reg, - ENBWREN => ram_full_i_reg, - INJECTDBITERR => '0', - INJECTSBITERR => '0', - RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED\(8 downto 0), - REGCEAREGCE => \gpregsm1.curr_fwft_state_reg[0]\, - REGCEB => '0', - RSTRAMARSTRAM => '0', - RSTRAMB => '0', - RSTREGARSTREG => sig_stream_rst, - RSTREGB => '0', - SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED\, - WEA(3 downto 0) => B"0000", - WEBWE(7) => ram_full_i_reg, - WEBWE(6) => ram_full_i_reg, - WEBWE(5) => ram_full_i_reg, - WEBWE(4) => ram_full_i_reg, - WEBWE(3) => ram_full_i_reg, - WEBWE(2) => ram_full_i_reg, - WEBWE(1) => ram_full_i_reg, - WEBWE(0) => ram_full_i_reg + I0 => \^q\(3), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => \^q\(2), + I4 => \^q\(4), + O => plusOp(4) ); -\INCLUDE_UNPACKING.lsig_0ffset_cntr[0]_i_1\: unisim.vcomponents.LUT5 +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[5]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"8BBBB888" + INIT => X"7FFFFFFF80000000" ) port map ( - I0 => p_0_out(0), - I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr[0]_i_2_n_0\, - I2 => dm2linebuf_mm2s_tvalid, - I3 => p_8_out, - I4 => lsig_0ffset_cntr, - O => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ + I0 => \^q\(2), + I1 => \^q\(1), + I2 => \^q\(0), + I3 => \^q\(3), + I4 => \^q\(4), + I5 => \^q\(5), + O => plusOp(5) ); -\INCLUDE_UNPACKING.lsig_0ffset_cntr[0]_i_2\: unisim.vcomponents.LUT5 +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[6]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"0000D555" + INIT => X"9" ) port map ( - I0 => lsig_cmd_loaded, - I1 => \fifo_wren__0\, - I2 => lsig_0ffset_cntr, - I3 => \^dobdo\(0), - I4 => \INFERRED_GEN.cnt_i_reg[2]\(0), - O => \INCLUDE_UNPACKING.lsig_0ffset_cntr[0]_i_2_n_0\ + I0 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_4_n_0\, + I1 => \^q\(6), + O => plusOp(6) ); -\INFERRED_GEN.cnt_i[2]_i_2\: unisim.vcomponents.LUT5 +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000080FF" + INIT => X"FFFFFFFFBBBBBFBB" ) port map ( - I0 => \^dobdo\(0), - I1 => lsig_0ffset_cntr, - I2 => \fifo_wren__0\, - I3 => lsig_cmd_loaded, - I4 => \INFERRED_GEN.cnt_i_reg[2]\(0), - O => \INFERRED_GEN.cnt_i_reg[0]\ + I0 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_reg_0\, + I1 => \^ch1_delay_cnt_en\, + I2 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_3_n_0\, + I3 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0\, + I4 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_4_n_0\, + I5 => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\, + O => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_1_n_0\ ); -\gf36e1_inst.sngfifo36e1_i_1\: unisim.vcomponents.LUT5 +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_2\: unisim.vcomponents.LUT3 generic map( - INIT => X"80808000" + INIT => X"D2" ) port map ( - I0 => lsig_0ffset_cntr, - I1 => sig_data_fifo_data_out(64), - I2 => lsig_cmd_loaded, - I3 => \gpregsm1.user_valid_reg\, - I4 => hold_ff_q, - O => \sig_user_skid_reg_reg[0]\(0) + I0 => \^q\(6), + I1 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_4_n_0\, + I2 => \^q\(7), + O => plusOp(7) ); -\gf36e1_inst.sngfifo36e1_i_10\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"AC" + INIT => X"7FFFFFFFFFFFFFFF" ) port map ( - I0 => sig_data_fifo_data_out(33), - I1 => sig_data_fifo_data_out(1), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(1) + I0 => \^q\(2), + I1 => \^q\(1), + I2 => \^q\(0), + I3 => \^q\(3), + I4 => \^q\(4), + I5 => \^q\(5), + O => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_4_n_0\ ); -\gf36e1_inst.sngfifo36e1_i_11\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => X"AC" + INIT => '0' ) port map ( - I0 => sig_data_fifo_data_out(32), - I1 => sig_data_fifo_data_out(0), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(0) + C => m_axi_mm2s_aclk, + CE => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0\, + D => plusOp(0), + Q => \^q\(0), + R => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_1_n_0\ ); -\gf36e1_inst.sngfifo36e1_i_12\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[1]\: unisim.vcomponents.FDRE generic map( - INIT => X"AC" + INIT => '0' ) port map ( - I0 => sig_data_fifo_data_out(40), - I1 => sig_data_fifo_data_out(8), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(8) + C => m_axi_mm2s_aclk, + CE => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0\, + D => plusOp(1), + Q => \^q\(1), + R => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_1_n_0\ ); -\gf36e1_inst.sngfifo36e1_i_1__0\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[2]\: unisim.vcomponents.FDRE generic map( - INIT => X"AC" + INIT => '0' ) port map ( - I0 => sig_data_fifo_data_out(48), - I1 => sig_data_fifo_data_out(16), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(16) + C => m_axi_mm2s_aclk, + CE => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0\, + D => plusOp(2), + Q => \^q\(2), + R => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_1_n_0\ ); -\gf36e1_inst.sngfifo36e1_i_1__1\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[3]\: unisim.vcomponents.FDRE generic map( - INIT => X"AC" + INIT => '0' ) port map ( - I0 => sig_data_fifo_data_out(57), - I1 => sig_data_fifo_data_out(25), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(25) + C => m_axi_mm2s_aclk, + CE => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0\, + D => plusOp(3), + Q => \^q\(3), + R => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_1_n_0\ ); -\gf36e1_inst.sngfifo36e1_i_2\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[4]\: unisim.vcomponents.FDRE generic map( - INIT => X"AC" + INIT => '0' ) port map ( - I0 => sig_data_fifo_data_out(47), - I1 => sig_data_fifo_data_out(15), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(15) + C => m_axi_mm2s_aclk, + CE => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0\, + D => plusOp(4), + Q => \^q\(4), + R => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_1_n_0\ ); -\gf36e1_inst.sngfifo36e1_i_2__0\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[5]\: unisim.vcomponents.FDRE generic map( - INIT => X"AC" + INIT => '0' ) port map ( - I0 => sig_data_fifo_data_out(56), - I1 => sig_data_fifo_data_out(24), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(24) + C => m_axi_mm2s_aclk, + CE => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0\, + D => plusOp(5), + Q => \^q\(5), + R => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_1_n_0\ ); -\gf36e1_inst.sngfifo36e1_i_2__1\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[6]\: unisim.vcomponents.FDRE generic map( - INIT => X"AC" + INIT => '0' ) port map ( - I0 => sig_data_fifo_data_out(63), - I1 => sig_data_fifo_data_out(31), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(31) + C => m_axi_mm2s_aclk, + CE => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0\, + D => plusOp(6), + Q => \^q\(6), + R => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_1_n_0\ ); -\gf36e1_inst.sngfifo36e1_i_3__0\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]\: unisim.vcomponents.FDRE generic map( - INIT => X"AC" + INIT => '0' ) port map ( - I0 => sig_data_fifo_data_out(46), - I1 => sig_data_fifo_data_out(14), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(14) + C => m_axi_mm2s_aclk, + CE => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0\, + D => plusOp(7), + Q => \^q\(7), + R => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_1_n_0\ ); -\gf36e1_inst.sngfifo36e1_i_3__1\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"AC" + INIT => X"00000010" ) port map ( - I0 => sig_data_fifo_data_out(55), - I1 => sig_data_fifo_data_out(23), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(23) + I0 => ch1_delay_zero, + I1 => p_17_out, + I2 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_incr_reg_n_0\, + I3 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_3_n_0\, + I4 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_4_n_0\, + O => p_26_out ); -\gf36e1_inst.sngfifo36e1_i_3__2\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_3\: unisim.vcomponents.LUT4 generic map( - INIT => X"AC" + INIT => X"6FF6" ) port map ( - I0 => sig_data_fifo_data_out(62), - I1 => sig_data_fifo_data_out(30), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(30) + I0 => \^q\(7), + I1 => p_71_out(15), + I2 => \^q\(6), + I3 => p_71_out(14), + O => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_3_n_0\ ); -\gf36e1_inst.sngfifo36e1_i_4\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"AC" + INIT => X"FFFFFFFFBEFFFFBE" ) port map ( - I0 => sig_data_fifo_data_out(39), - I1 => sig_data_fifo_data_out(7), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(7) + I0 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_6_n_0\, + I1 => \^q\(1), + I2 => p_71_out(9), + I3 => \^q\(0), + I4 => p_71_out(8), + I5 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_7_n_0\, + O => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_4_n_0\ ); -\gf36e1_inst.sngfifo36e1_i_4__0\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_6\: unisim.vcomponents.LUT4 generic map( - INIT => X"AC" + INIT => X"6FF6" ) port map ( - I0 => sig_data_fifo_data_out(45), - I1 => sig_data_fifo_data_out(13), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(13) + I0 => \^q\(4), + I1 => p_71_out(12), + I2 => \^q\(3), + I3 => p_71_out(11), + O => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_6_n_0\ ); -\gf36e1_inst.sngfifo36e1_i_4__1\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_7\: unisim.vcomponents.LUT4 generic map( - INIT => X"AC" + INIT => X"6FF6" ) port map ( - I0 => sig_data_fifo_data_out(54), - I1 => sig_data_fifo_data_out(22), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(22) + I0 => \^q\(5), + I1 => p_71_out(13), + I2 => \^q\(2), + I3 => p_71_out(10), + O => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_7_n_0\ ); -\gf36e1_inst.sngfifo36e1_i_4__2\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_reg\: unisim.vcomponents.FDRE generic map( - INIT => X"AC" + INIT => '0' ) port map ( - I0 => sig_data_fifo_data_out(61), - I1 => sig_data_fifo_data_out(29), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(29) + C => m_axi_mm2s_aclk, + CE => '1', + D => p_26_out, + Q => ch1_dly_irq_set, + R => SR(0) ); -\gf36e1_inst.sngfifo36e1_i_5\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"AC" + INIT => X"0080" ) port map ( - I0 => sig_data_fifo_data_out(38), - I1 => sig_data_fifo_data_out(6), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(6) + I0 => ch1_ioc_irq_set_i, + I1 => p_50_out, + I2 => \out\, + I3 => p_13_out, + O => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_i_1_n_0\ ); -\gf36e1_inst.sngfifo36e1_i_5__0\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_i_2\: unisim.vcomponents.LUT5 generic map( - INIT => X"AC" + INIT => X"00010000" ) port map ( - I0 => sig_data_fifo_data_out(44), - I1 => sig_data_fifo_data_out(12), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(12) + I0 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(4), + I1 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(5), + I2 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(6), + I3 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(7), + I4 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_6_n_0\, + O => ch1_ioc_irq_set_i ); -\gf36e1_inst.sngfifo36e1_i_5__1\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_reg\: unisim.vcomponents.FDRE generic map( - INIT => X"AC" + INIT => '0' ) port map ( - I0 => sig_data_fifo_data_out(53), - I1 => sig_data_fifo_data_out(21), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(21) + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_i_1_n_0\, + Q => \^mm2s_ioc_irq_set\, + R => '0' ); -\gf36e1_inst.sngfifo36e1_i_5__2\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[0]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"8B" ) port map ( - I0 => sig_data_fifo_data_out(60), - I1 => sig_data_fifo_data_out(28), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(28) + I0 => p_71_out(0), + I1 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5_n_0\, + I2 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(0), + O => p_2_in(0) ); -\gf36e1_inst.sngfifo36e1_i_6\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[1]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"AC" + INIT => X"F099" ) port map ( - I0 => sig_data_fifo_data_out(37), - I1 => sig_data_fifo_data_out(5), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(5) + I0 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(0), + I1 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(1), + I2 => p_71_out(1), + I3 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5_n_0\, + O => p_2_in(1) ); -\gf36e1_inst.sngfifo36e1_i_6__0\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[2]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"AC" + INIT => X"FF00A9A9" ) port map ( - I0 => sig_data_fifo_data_out(43), - I1 => sig_data_fifo_data_out(11), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(11) + I0 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(2), + I1 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(1), + I2 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(0), + I3 => p_71_out(2), + I4 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5_n_0\, + O => p_2_in(2) ); -\gf36e1_inst.sngfifo36e1_i_6__1\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[3]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"AC" + INIT => X"FFFF0000AAA9AAA9" ) port map ( - I0 => sig_data_fifo_data_out(52), - I1 => sig_data_fifo_data_out(20), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(20) + I0 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(3), + I1 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(0), + I2 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(1), + I3 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(2), + I4 => p_71_out(3), + I5 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5_n_0\, + O => p_2_in(3) ); -\gf36e1_inst.sngfifo36e1_i_6__2\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[4]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"AC" + INIT => X"F099" ) port map ( - I0 => sig_data_fifo_data_out(59), - I1 => sig_data_fifo_data_out(27), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(27) + I0 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(4), + I1 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[6]_i_2_n_0\, + I2 => p_71_out(4), + I3 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5_n_0\, + O => p_2_in(4) ); -\gf36e1_inst.sngfifo36e1_i_7\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[5]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"AC" + INIT => X"FF00A9A9" ) port map ( - I0 => sig_data_fifo_data_out(36), - I1 => sig_data_fifo_data_out(4), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(4) + I0 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(5), + I1 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[6]_i_2_n_0\, + I2 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(4), + I3 => p_71_out(5), + I4 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5_n_0\, + O => p_2_in(5) ); -\gf36e1_inst.sngfifo36e1_i_7__0\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[6]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"AC" + INIT => X"FFFF0000AAA9AAA9" ) port map ( - I0 => sig_data_fifo_data_out(42), - I1 => sig_data_fifo_data_out(10), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(10) + I0 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(6), + I1 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(4), + I2 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[6]_i_2_n_0\, + I3 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(5), + I4 => p_71_out(6), + I5 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5_n_0\, + O => p_2_in(6) ); -\gf36e1_inst.sngfifo36e1_i_7__1\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[6]_i_2\: unisim.vcomponents.LUT4 generic map( - INIT => X"AC" + INIT => X"FFFE" ) port map ( - I0 => sig_data_fifo_data_out(51), - I1 => sig_data_fifo_data_out(19), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(19) + I0 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(2), + I1 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(1), + I2 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(0), + I3 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(3), + O => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[6]_i_2_n_0\ ); -\gf36e1_inst.sngfifo36e1_i_8\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_3\: unisim.vcomponents.LUT5 generic map( - INIT => X"AC" + INIT => X"FF00A9A9" ) port map ( - I0 => sig_data_fifo_data_out(35), - I1 => sig_data_fifo_data_out(3), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(3) + I0 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(7), + I1 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(6), + I2 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_4_n_0\, + I3 => p_71_out(7), + I4 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5_n_0\, + O => p_2_in(7) ); -\gf36e1_inst.sngfifo36e1_i_8__0\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"AC" + INIT => X"FFFFFFFFFFFFFFFE" ) port map ( - I0 => sig_data_fifo_data_out(41), - I1 => sig_data_fifo_data_out(9), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(9) + I0 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(4), + I1 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(2), + I2 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(1), + I3 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(0), + I4 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(3), + I5 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(5), + O => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_4_n_0\ ); -\gf36e1_inst.sngfifo36e1_i_8__1\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5\: unisim.vcomponents.LUT6 generic map( - INIT => X"AC" + INIT => X"FFFFFFFF00000002" ) port map ( - I0 => sig_data_fifo_data_out(50), - I1 => sig_data_fifo_data_out(18), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(18) + I0 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_6_n_0\, + I1 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(7), + I2 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(6), + I3 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(5), + I4 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(4), + I5 => p_13_out, + O => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_5_n_0\ ); -\gf36e1_inst.sngfifo36e1_i_9\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_6\: unisim.vcomponents.LUT4 generic map( - INIT => X"AC" + INIT => X"0004" ) port map ( - I0 => sig_data_fifo_data_out(34), - I1 => sig_data_fifo_data_out(2), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(2) + I0 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(1), + I1 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(0), + I2 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(3), + I3 => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(2), + O => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_6_n_0\ ); -\gf36e1_inst.sngfifo36e1_i_9__0\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0]\: unisim.vcomponents.FDSE generic map( - INIT => X"AC" + INIT => '1' ) port map ( - I0 => sig_data_fifo_data_out(49), - I1 => sig_data_fifo_data_out(17), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(17) + C => m_axi_mm2s_aclk, + CE => E(0), + D => p_2_in(0), + Q => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(0), + S => prmry_resetn_i_reg_2(0) ); -\gf36e1_inst.sngfifo36e1_i_9__1\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[1]\: unisim.vcomponents.FDRE generic map( - INIT => X"AC" + INIT => '0' ) port map ( - I0 => sig_data_fifo_data_out(58), - I1 => sig_data_fifo_data_out(26), - I2 => lsig_0ffset_cntr, - O => dm2linebuf_mm2s_tdata(26) + C => m_axi_mm2s_aclk, + CE => E(0), + D => p_2_in(1), + Q => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(1), + R => prmry_resetn_i_reg_2(0) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6 is - port ( - EMPTY : out STD_LOGIC; - FULL : out STD_LOGIC; - fifo_dout : out STD_LOGIC_VECTOR ( 6 downto 0 ); - WR_EN : out STD_LOGIC; - m_axis_mm2s_aclk : in STD_LOGIC; - RD_EN : in STD_LOGIC; - RST : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - DIN : in STD_LOGIC_VECTOR ( 6 downto 0 ); - \fifo_wren__0\ : in STD_LOGIC; - sig_s_ready_out_reg : in STD_LOGIC; - sig_s_ready_out_reg_0 : in STD_LOGIC; - sig_s_ready_out_reg_1 : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6 : entity is "builtin_prim_v6"; -end Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6 is - signal \^full\ : STD_LOGIC; - signal \^wr_en\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_0\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_1\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_10\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_113\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_14\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_15\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_17\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_18\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_19\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_20\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_21\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_22\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_23\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_24\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_25\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_26\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_27\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_28\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_30\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_31\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_32\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_33\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_34\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_35\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_36\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_37\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_38\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_39\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_40\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_41\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_98\ : STD_LOGIC; - signal p_3_out : STD_LOGIC; - signal \NLW_gf36e1_inst.sngfifo36e1_DO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 8 ); - signal \NLW_gf36e1_inst.sngfifo36e1_DOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 ); - signal \NLW_gf36e1_inst.sngfifo36e1_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal \NLW_gf36e1_inst.sngfifo36e1_RDCOUNT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 12 to 12 ); - signal \NLW_gf36e1_inst.sngfifo36e1_WRCOUNT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 12 to 12 ); - attribute CLOCK_DOMAINS : string; - attribute CLOCK_DOMAINS of \gf36e1_inst.sngfifo36e1\ : label is "INDEPENDENT"; - attribute box_type : string; - attribute box_type of \gf36e1_inst.sngfifo36e1\ : label is "PRIMITIVE"; -begin - FULL <= \^full\; - WR_EN <= \^wr_en\; -\gf36e1_inst.sngfifo36e1\: unisim.vcomponents.FIFO36E1 +\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[2]\: unisim.vcomponents.FDRE generic map( - ALMOST_EMPTY_OFFSET => X"000A", - ALMOST_FULL_OFFSET => X"0097", - DATA_WIDTH => 9, - DO_REG => 1, - EN_ECC_READ => false, - EN_ECC_WRITE => false, - EN_SYN => false, - FIFO_MODE => "FIFO36", - FIRST_WORD_FALL_THROUGH => true, - INIT => X"000000000000000000", - IS_RDCLK_INVERTED => '0', - IS_RDEN_INVERTED => '0', - IS_RSTREG_INVERTED => '0', - IS_RST_INVERTED => '0', - IS_WRCLK_INVERTED => '0', - IS_WREN_INVERTED => '0', - SIM_DEVICE => "7SERIES", - SRVAL => X"000000000000000000" + INIT => '0' ) port map ( - ALMOSTEMPTY => \gf36e1_inst.sngfifo36e1_n_10\, - ALMOSTFULL => p_3_out, - DBITERR => \gf36e1_inst.sngfifo36e1_n_0\, - DI(63 downto 7) => B"000000000000000000000000000000000000000000000000000000000", - DI(6 downto 0) => DIN(6 downto 0), - DIP(7 downto 0) => B"00000000", - DO(63 downto 8) => \NLW_gf36e1_inst.sngfifo36e1_DO_UNCONNECTED\(63 downto 8), - DO(7) => \gf36e1_inst.sngfifo36e1_n_98\, - DO(6 downto 0) => fifo_dout(6 downto 0), - DOP(7 downto 1) => \NLW_gf36e1_inst.sngfifo36e1_DOP_UNCONNECTED\(7 downto 1), - DOP(0) => \gf36e1_inst.sngfifo36e1_n_113\, - ECCPARITY(7 downto 0) => \NLW_gf36e1_inst.sngfifo36e1_ECCPARITY_UNCONNECTED\(7 downto 0), - EMPTY => EMPTY, - FULL => \^full\, - INJECTDBITERR => '0', - INJECTSBITERR => '0', - RDCLK => m_axis_mm2s_aclk, - RDCOUNT(12) => \NLW_gf36e1_inst.sngfifo36e1_RDCOUNT_UNCONNECTED\(12), - RDCOUNT(11) => \gf36e1_inst.sngfifo36e1_n_17\, - RDCOUNT(10) => \gf36e1_inst.sngfifo36e1_n_18\, - RDCOUNT(9) => \gf36e1_inst.sngfifo36e1_n_19\, - RDCOUNT(8) => \gf36e1_inst.sngfifo36e1_n_20\, - RDCOUNT(7) => \gf36e1_inst.sngfifo36e1_n_21\, - RDCOUNT(6) => \gf36e1_inst.sngfifo36e1_n_22\, - RDCOUNT(5) => \gf36e1_inst.sngfifo36e1_n_23\, - RDCOUNT(4) => \gf36e1_inst.sngfifo36e1_n_24\, - RDCOUNT(3) => \gf36e1_inst.sngfifo36e1_n_25\, - RDCOUNT(2) => \gf36e1_inst.sngfifo36e1_n_26\, - RDCOUNT(1) => \gf36e1_inst.sngfifo36e1_n_27\, - RDCOUNT(0) => \gf36e1_inst.sngfifo36e1_n_28\, - RDEN => RD_EN, - RDERR => \gf36e1_inst.sngfifo36e1_n_14\, - REGCE => '0', - RST => RST, - RSTREG => '0', - SBITERR => \gf36e1_inst.sngfifo36e1_n_1\, - WRCLK => m_axi_mm2s_aclk, - WRCOUNT(12) => \NLW_gf36e1_inst.sngfifo36e1_WRCOUNT_UNCONNECTED\(12), - WRCOUNT(11) => \gf36e1_inst.sngfifo36e1_n_30\, - WRCOUNT(10) => \gf36e1_inst.sngfifo36e1_n_31\, - WRCOUNT(9) => \gf36e1_inst.sngfifo36e1_n_32\, - WRCOUNT(8) => \gf36e1_inst.sngfifo36e1_n_33\, - WRCOUNT(7) => \gf36e1_inst.sngfifo36e1_n_34\, - WRCOUNT(6) => \gf36e1_inst.sngfifo36e1_n_35\, - WRCOUNT(5) => \gf36e1_inst.sngfifo36e1_n_36\, - WRCOUNT(4) => \gf36e1_inst.sngfifo36e1_n_37\, - WRCOUNT(3) => \gf36e1_inst.sngfifo36e1_n_38\, - WRCOUNT(2) => \gf36e1_inst.sngfifo36e1_n_39\, - WRCOUNT(1) => \gf36e1_inst.sngfifo36e1_n_40\, - WRCOUNT(0) => \gf36e1_inst.sngfifo36e1_n_41\, - WREN => \^wr_en\, - WRERR => \gf36e1_inst.sngfifo36e1_n_15\ + C => m_axi_mm2s_aclk, + CE => E(0), + D => p_2_in(2), + Q => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(2), + R => prmry_resetn_i_reg_2(0) ); -\gf36e1_inst.sngfifo36e1_i_3\: unisim.vcomponents.LUT5 +\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[3]\: unisim.vcomponents.FDRE generic map( - INIT => X"00000002" + INIT => '0' ) port map ( - I0 => \fifo_wren__0\, - I1 => \^full\, - I2 => sig_s_ready_out_reg, - I3 => sig_s_ready_out_reg_0, - I4 => sig_s_ready_out_reg_1, - O => \^wr_en\ + C => m_axi_mm2s_aclk, + CE => E(0), + D => p_2_in(3), + Q => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(3), + R => prmry_resetn_i_reg_2(0) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_10 is - port ( - EMPTY : out STD_LOGIC; - FULL : out STD_LOGIC; - fifo_dout : out STD_LOGIC_VECTOR ( 8 downto 0 ); - RD_EN : out STD_LOGIC; - m_axis_mm2s_aclk : in STD_LOGIC; - RST : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - WR_EN : in STD_LOGIC; - dm2linebuf_mm2s_tdata : in STD_LOGIC_VECTOR ( 8 downto 0 ); - \out\ : in STD_LOGIC; - sig_s_ready_out_reg : in STD_LOGIC; - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ : in STD_LOGIC; - sig_s_ready_out_reg_0 : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_10 : entity is "builtin_prim_v6"; -end Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_10; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_10 is - signal \^empty\ : STD_LOGIC; - signal \^rd_en\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_14\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_15\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_17\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_18\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_19\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_20\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_21\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_22\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_23\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_24\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_25\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_26\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_27\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_28\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_30\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_31\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_32\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_33\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_34\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_35\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_36\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_37\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_38\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_39\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_40\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_41\ : STD_LOGIC; - signal p_10_out : STD_LOGIC; - signal p_11_out : STD_LOGIC; - signal p_12_out : STD_LOGIC; - signal p_13_out : STD_LOGIC; - signal \NLW_gf36e1_inst.sngfifo36e1_DO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 8 ); - signal \NLW_gf36e1_inst.sngfifo36e1_DOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 ); - signal \NLW_gf36e1_inst.sngfifo36e1_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal \NLW_gf36e1_inst.sngfifo36e1_RDCOUNT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 12 to 12 ); - signal \NLW_gf36e1_inst.sngfifo36e1_WRCOUNT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 12 to 12 ); - attribute CLOCK_DOMAINS : string; - attribute CLOCK_DOMAINS of \gf36e1_inst.sngfifo36e1\ : label is "INDEPENDENT"; - attribute box_type : string; - attribute box_type of \gf36e1_inst.sngfifo36e1\ : label is "PRIMITIVE"; -begin - EMPTY <= \^empty\; - RD_EN <= \^rd_en\; -\gf36e1_inst.sngfifo36e1\: unisim.vcomponents.FIFO36E1 +\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[4]\: unisim.vcomponents.FDRE generic map( - ALMOST_EMPTY_OFFSET => X"000A", - ALMOST_FULL_OFFSET => X"0097", - DATA_WIDTH => 9, - DO_REG => 1, - EN_ECC_READ => false, - EN_ECC_WRITE => false, - EN_SYN => false, - FIFO_MODE => "FIFO36", - FIRST_WORD_FALL_THROUGH => true, - INIT => X"000000000000000000", - IS_RDCLK_INVERTED => '0', - IS_RDEN_INVERTED => '0', - IS_RSTREG_INVERTED => '0', - IS_RST_INVERTED => '0', - IS_WRCLK_INVERTED => '0', - IS_WREN_INVERTED => '0', - SIM_DEVICE => "7SERIES", - SRVAL => X"000000000000000000" + INIT => '0' ) port map ( - ALMOSTEMPTY => p_11_out, - ALMOSTFULL => p_10_out, - DBITERR => p_13_out, - DI(63 downto 8) => B"00000000000000000000000000000000000000000000000000000000", - DI(7 downto 0) => dm2linebuf_mm2s_tdata(7 downto 0), - DIP(7 downto 1) => B"0000000", - DIP(0) => dm2linebuf_mm2s_tdata(8), - DO(63 downto 8) => \NLW_gf36e1_inst.sngfifo36e1_DO_UNCONNECTED\(63 downto 8), - DO(7 downto 0) => fifo_dout(7 downto 0), - DOP(7 downto 1) => \NLW_gf36e1_inst.sngfifo36e1_DOP_UNCONNECTED\(7 downto 1), - DOP(0) => fifo_dout(8), - ECCPARITY(7 downto 0) => \NLW_gf36e1_inst.sngfifo36e1_ECCPARITY_UNCONNECTED\(7 downto 0), - EMPTY => \^empty\, - FULL => FULL, - INJECTDBITERR => '0', - INJECTSBITERR => '0', - RDCLK => m_axis_mm2s_aclk, - RDCOUNT(12) => \NLW_gf36e1_inst.sngfifo36e1_RDCOUNT_UNCONNECTED\(12), - RDCOUNT(11) => \gf36e1_inst.sngfifo36e1_n_17\, - RDCOUNT(10) => \gf36e1_inst.sngfifo36e1_n_18\, - RDCOUNT(9) => \gf36e1_inst.sngfifo36e1_n_19\, - RDCOUNT(8) => \gf36e1_inst.sngfifo36e1_n_20\, - RDCOUNT(7) => \gf36e1_inst.sngfifo36e1_n_21\, - RDCOUNT(6) => \gf36e1_inst.sngfifo36e1_n_22\, - RDCOUNT(5) => \gf36e1_inst.sngfifo36e1_n_23\, - RDCOUNT(4) => \gf36e1_inst.sngfifo36e1_n_24\, - RDCOUNT(3) => \gf36e1_inst.sngfifo36e1_n_25\, - RDCOUNT(2) => \gf36e1_inst.sngfifo36e1_n_26\, - RDCOUNT(1) => \gf36e1_inst.sngfifo36e1_n_27\, - RDCOUNT(0) => \gf36e1_inst.sngfifo36e1_n_28\, - RDEN => \^rd_en\, - RDERR => \gf36e1_inst.sngfifo36e1_n_14\, - REGCE => '0', - RST => RST, - RSTREG => '0', - SBITERR => p_12_out, - WRCLK => m_axi_mm2s_aclk, - WRCOUNT(12) => \NLW_gf36e1_inst.sngfifo36e1_WRCOUNT_UNCONNECTED\(12), - WRCOUNT(11) => \gf36e1_inst.sngfifo36e1_n_30\, - WRCOUNT(10) => \gf36e1_inst.sngfifo36e1_n_31\, - WRCOUNT(9) => \gf36e1_inst.sngfifo36e1_n_32\, - WRCOUNT(8) => \gf36e1_inst.sngfifo36e1_n_33\, - WRCOUNT(7) => \gf36e1_inst.sngfifo36e1_n_34\, - WRCOUNT(6) => \gf36e1_inst.sngfifo36e1_n_35\, - WRCOUNT(5) => \gf36e1_inst.sngfifo36e1_n_36\, - WRCOUNT(4) => \gf36e1_inst.sngfifo36e1_n_37\, - WRCOUNT(3) => \gf36e1_inst.sngfifo36e1_n_38\, - WRCOUNT(2) => \gf36e1_inst.sngfifo36e1_n_39\, - WRCOUNT(1) => \gf36e1_inst.sngfifo36e1_n_40\, - WRCOUNT(0) => \gf36e1_inst.sngfifo36e1_n_41\, - WREN => WR_EN, - WRERR => \gf36e1_inst.sngfifo36e1_n_15\ + C => m_axi_mm2s_aclk, + CE => E(0), + D => p_2_in(4), + Q => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(4), + R => prmry_resetn_i_reg_2(0) ); -\gf36e1_inst.sngfifo36e1_i_1__2\: unisim.vcomponents.LUT5 +\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[5]\: unisim.vcomponents.FDRE generic map( - INIT => X"00000002" + INIT => '0' ) port map ( - I0 => \out\, - I1 => \^empty\, - I2 => sig_s_ready_out_reg, - I3 => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\, - I4 => sig_s_ready_out_reg_0, - O => \^rd_en\ + C => m_axi_mm2s_aclk, + CE => E(0), + D => p_2_in(5), + Q => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(5), + R => prmry_resetn_i_reg_2(0) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_11 is - port ( - EMPTY : out STD_LOGIC; - FULL : out STD_LOGIC; - fifo_dout : out STD_LOGIC_VECTOR ( 8 downto 0 ); - fifo_full_i : out STD_LOGIC; - sig_m_valid_out_reg : out STD_LOGIC; - m_axis_mm2s_aclk : in STD_LOGIC; - RD_EN : in STD_LOGIC; - RST : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - WR_EN : in STD_LOGIC; - dm2linebuf_mm2s_tdata : in STD_LOGIC_VECTOR ( 8 downto 0 ); - sig_s_ready_out_reg : in STD_LOGIC; - sig_s_ready_out_reg_0 : in STD_LOGIC; - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ : in STD_LOGIC; - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\ : in STD_LOGIC; - sig_s_ready_out_reg_1 : in STD_LOGIC; - sig_s_ready_out_reg_2 : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_11 : entity is "builtin_prim_v6"; -end Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_11; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_11 is - signal \^empty\ : STD_LOGIC; - signal \^full\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_14\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_15\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_17\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_18\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_19\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_20\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_21\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_22\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_23\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_24\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_25\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_26\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_27\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_28\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_30\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_31\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_32\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_33\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_34\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_35\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_36\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_37\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_38\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_39\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_40\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_41\ : STD_LOGIC; - signal p_17_out : STD_LOGIC; - signal p_18_out : STD_LOGIC; - signal p_19_out : STD_LOGIC; - signal p_20_out : STD_LOGIC; - signal \NLW_gf36e1_inst.sngfifo36e1_DO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 8 ); - signal \NLW_gf36e1_inst.sngfifo36e1_DOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 ); - signal \NLW_gf36e1_inst.sngfifo36e1_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal \NLW_gf36e1_inst.sngfifo36e1_RDCOUNT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 12 to 12 ); - signal \NLW_gf36e1_inst.sngfifo36e1_WRCOUNT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 12 to 12 ); - attribute CLOCK_DOMAINS : string; - attribute CLOCK_DOMAINS of \gf36e1_inst.sngfifo36e1\ : label is "INDEPENDENT"; - attribute box_type : string; - attribute box_type of \gf36e1_inst.sngfifo36e1\ : label is "PRIMITIVE"; -begin - EMPTY <= \^empty\; - FULL <= \^full\; -\gc1.count_d1[6]_i_4\: unisim.vcomponents.LUT4 +\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[6]\: unisim.vcomponents.FDRE generic map( - INIT => X"FFFE" + INIT => '0' ) port map ( - I0 => \^full\, - I1 => sig_s_ready_out_reg, - I2 => sig_s_ready_out_reg_0, - I3 => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\, - O => fifo_full_i + C => m_axi_mm2s_aclk, + CE => E(0), + D => p_2_in(6), + Q => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(6), + R => prmry_resetn_i_reg_2(0) ); -\gf36e1_inst.sngfifo36e1\: unisim.vcomponents.FIFO36E1 +\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\: unisim.vcomponents.FDRE generic map( - ALMOST_EMPTY_OFFSET => X"000A", - ALMOST_FULL_OFFSET => X"0097", - DATA_WIDTH => 9, - DO_REG => 1, - EN_ECC_READ => false, - EN_ECC_WRITE => false, - EN_SYN => false, - FIFO_MODE => "FIFO36", - FIRST_WORD_FALL_THROUGH => true, - INIT => X"000000000000000000", - IS_RDCLK_INVERTED => '0', - IS_RDEN_INVERTED => '0', - IS_RSTREG_INVERTED => '0', - IS_RST_INVERTED => '0', - IS_WRCLK_INVERTED => '0', - IS_WREN_INVERTED => '0', - SIM_DEVICE => "7SERIES", - SRVAL => X"000000000000000000" + INIT => '0' ) port map ( - ALMOSTEMPTY => p_18_out, - ALMOSTFULL => p_17_out, - DBITERR => p_20_out, - DI(63 downto 8) => B"00000000000000000000000000000000000000000000000000000000", - DI(7 downto 0) => dm2linebuf_mm2s_tdata(7 downto 0), - DIP(7 downto 1) => B"0000000", - DIP(0) => dm2linebuf_mm2s_tdata(8), - DO(63 downto 8) => \NLW_gf36e1_inst.sngfifo36e1_DO_UNCONNECTED\(63 downto 8), - DO(7 downto 0) => fifo_dout(7 downto 0), - DOP(7 downto 1) => \NLW_gf36e1_inst.sngfifo36e1_DOP_UNCONNECTED\(7 downto 1), - DOP(0) => fifo_dout(8), - ECCPARITY(7 downto 0) => \NLW_gf36e1_inst.sngfifo36e1_ECCPARITY_UNCONNECTED\(7 downto 0), - EMPTY => \^empty\, - FULL => \^full\, - INJECTDBITERR => '0', - INJECTSBITERR => '0', - RDCLK => m_axis_mm2s_aclk, - RDCOUNT(12) => \NLW_gf36e1_inst.sngfifo36e1_RDCOUNT_UNCONNECTED\(12), - RDCOUNT(11) => \gf36e1_inst.sngfifo36e1_n_17\, - RDCOUNT(10) => \gf36e1_inst.sngfifo36e1_n_18\, - RDCOUNT(9) => \gf36e1_inst.sngfifo36e1_n_19\, - RDCOUNT(8) => \gf36e1_inst.sngfifo36e1_n_20\, - RDCOUNT(7) => \gf36e1_inst.sngfifo36e1_n_21\, - RDCOUNT(6) => \gf36e1_inst.sngfifo36e1_n_22\, - RDCOUNT(5) => \gf36e1_inst.sngfifo36e1_n_23\, - RDCOUNT(4) => \gf36e1_inst.sngfifo36e1_n_24\, - RDCOUNT(3) => \gf36e1_inst.sngfifo36e1_n_25\, - RDCOUNT(2) => \gf36e1_inst.sngfifo36e1_n_26\, - RDCOUNT(1) => \gf36e1_inst.sngfifo36e1_n_27\, - RDCOUNT(0) => \gf36e1_inst.sngfifo36e1_n_28\, - RDEN => RD_EN, - RDERR => \gf36e1_inst.sngfifo36e1_n_14\, - REGCE => '0', - RST => RST, - RSTREG => '0', - SBITERR => p_19_out, - WRCLK => m_axi_mm2s_aclk, - WRCOUNT(12) => \NLW_gf36e1_inst.sngfifo36e1_WRCOUNT_UNCONNECTED\(12), - WRCOUNT(11) => \gf36e1_inst.sngfifo36e1_n_30\, - WRCOUNT(10) => \gf36e1_inst.sngfifo36e1_n_31\, - WRCOUNT(9) => \gf36e1_inst.sngfifo36e1_n_32\, - WRCOUNT(8) => \gf36e1_inst.sngfifo36e1_n_33\, - WRCOUNT(7) => \gf36e1_inst.sngfifo36e1_n_34\, - WRCOUNT(6) => \gf36e1_inst.sngfifo36e1_n_35\, - WRCOUNT(5) => \gf36e1_inst.sngfifo36e1_n_36\, - WRCOUNT(4) => \gf36e1_inst.sngfifo36e1_n_37\, - WRCOUNT(3) => \gf36e1_inst.sngfifo36e1_n_38\, - WRCOUNT(2) => \gf36e1_inst.sngfifo36e1_n_39\, - WRCOUNT(1) => \gf36e1_inst.sngfifo36e1_n_40\, - WRCOUNT(0) => \gf36e1_inst.sngfifo36e1_n_41\, - WREN => WR_EN, - WRERR => \gf36e1_inst.sngfifo36e1_n_15\ + C => m_axi_mm2s_aclk, + CE => E(0), + D => p_2_in(7), + Q => \^gen_include_mm2s.gen_ch1_frm_cntr.ch1_thresh_count_reg[7]_0\(7), + R => prmry_resetn_i_reg_2(0) ); -sig_s_ready_dup_i_2: unisim.vcomponents.LUT4 +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[0]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"FFFE" + INIT => X"32" ) port map ( - I0 => \^empty\, - I1 => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\, - I2 => sig_s_ready_out_reg_1, - I3 => sig_s_ready_out_reg_2, - O => sig_m_valid_out_reg + I0 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[1]\, + I1 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[0]\, + I2 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[1]_i_2_n_0\, + O => ch2_dly_fast_cnt(0) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_12 is - port ( - EMPTY : out STD_LOGIC; - FULL : out STD_LOGIC; - fifo_dout : out STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axis_mm2s_aclk : in STD_LOGIC; - RD_EN : in STD_LOGIC; - RST : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - WR_EN : in STD_LOGIC; - dm2linebuf_mm2s_tdata : in STD_LOGIC_VECTOR ( 8 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_12 : entity is "builtin_prim_v6"; -end Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_12; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_12 is - signal \gf36e1_inst.sngfifo36e1_n_14\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_15\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_17\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_18\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_19\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_20\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_21\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_22\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_23\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_24\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_25\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_26\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_27\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_28\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_30\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_31\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_32\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_33\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_34\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_35\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_36\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_37\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_38\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_39\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_40\ : STD_LOGIC; - signal \gf36e1_inst.sngfifo36e1_n_41\ : STD_LOGIC; - signal p_24_out : STD_LOGIC; - signal p_25_out : STD_LOGIC; - signal p_26_out : STD_LOGIC; - signal p_27_out : STD_LOGIC; - signal \NLW_gf36e1_inst.sngfifo36e1_DO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 8 ); - signal \NLW_gf36e1_inst.sngfifo36e1_DOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 ); - signal \NLW_gf36e1_inst.sngfifo36e1_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal \NLW_gf36e1_inst.sngfifo36e1_RDCOUNT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 12 to 12 ); - signal \NLW_gf36e1_inst.sngfifo36e1_WRCOUNT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 12 to 12 ); - attribute CLOCK_DOMAINS : string; - attribute CLOCK_DOMAINS of \gf36e1_inst.sngfifo36e1\ : label is "INDEPENDENT"; - attribute box_type : string; - attribute box_type of \gf36e1_inst.sngfifo36e1\ : label is "PRIMITIVE"; -begin -\gf36e1_inst.sngfifo36e1\: unisim.vcomponents.FIFO36E1 +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[1]_i_1\: unisim.vcomponents.LUT3 generic map( - ALMOST_EMPTY_OFFSET => X"000A", - ALMOST_FULL_OFFSET => X"0097", - DATA_WIDTH => 9, - DO_REG => 1, - EN_ECC_READ => false, - EN_ECC_WRITE => false, - EN_SYN => false, - FIFO_MODE => "FIFO36", - FIRST_WORD_FALL_THROUGH => true, - INIT => X"000000000000000000", - IS_RDCLK_INVERTED => '0', - IS_RDEN_INVERTED => '0', - IS_RSTREG_INVERTED => '0', - IS_RST_INVERTED => '0', - IS_WRCLK_INVERTED => '0', - IS_WREN_INVERTED => '0', - SIM_DEVICE => "7SERIES", - SRVAL => X"000000000000000000" + INIT => X"98" ) port map ( - ALMOSTEMPTY => p_25_out, - ALMOSTFULL => p_24_out, - DBITERR => p_27_out, - DI(63 downto 8) => B"00000000000000000000000000000000000000000000000000000000", - DI(7 downto 0) => dm2linebuf_mm2s_tdata(7 downto 0), - DIP(7 downto 1) => B"0000000", - DIP(0) => dm2linebuf_mm2s_tdata(8), - DO(63 downto 8) => \NLW_gf36e1_inst.sngfifo36e1_DO_UNCONNECTED\(63 downto 8), - DO(7 downto 0) => fifo_dout(7 downto 0), - DOP(7 downto 1) => \NLW_gf36e1_inst.sngfifo36e1_DOP_UNCONNECTED\(7 downto 1), - DOP(0) => fifo_dout(8), - ECCPARITY(7 downto 0) => \NLW_gf36e1_inst.sngfifo36e1_ECCPARITY_UNCONNECTED\(7 downto 0), - EMPTY => EMPTY, - FULL => FULL, - INJECTDBITERR => '0', - INJECTSBITERR => '0', - RDCLK => m_axis_mm2s_aclk, - RDCOUNT(12) => \NLW_gf36e1_inst.sngfifo36e1_RDCOUNT_UNCONNECTED\(12), - RDCOUNT(11) => \gf36e1_inst.sngfifo36e1_n_17\, - RDCOUNT(10) => \gf36e1_inst.sngfifo36e1_n_18\, - RDCOUNT(9) => \gf36e1_inst.sngfifo36e1_n_19\, - RDCOUNT(8) => \gf36e1_inst.sngfifo36e1_n_20\, - RDCOUNT(7) => \gf36e1_inst.sngfifo36e1_n_21\, - RDCOUNT(6) => \gf36e1_inst.sngfifo36e1_n_22\, - RDCOUNT(5) => \gf36e1_inst.sngfifo36e1_n_23\, - RDCOUNT(4) => \gf36e1_inst.sngfifo36e1_n_24\, - RDCOUNT(3) => \gf36e1_inst.sngfifo36e1_n_25\, - RDCOUNT(2) => \gf36e1_inst.sngfifo36e1_n_26\, - RDCOUNT(1) => \gf36e1_inst.sngfifo36e1_n_27\, - RDCOUNT(0) => \gf36e1_inst.sngfifo36e1_n_28\, - RDEN => RD_EN, - RDERR => \gf36e1_inst.sngfifo36e1_n_14\, - REGCE => '0', - RST => RST, - RSTREG => '0', - SBITERR => p_26_out, - WRCLK => m_axi_mm2s_aclk, - WRCOUNT(12) => \NLW_gf36e1_inst.sngfifo36e1_WRCOUNT_UNCONNECTED\(12), - WRCOUNT(11) => \gf36e1_inst.sngfifo36e1_n_30\, - WRCOUNT(10) => \gf36e1_inst.sngfifo36e1_n_31\, - WRCOUNT(9) => \gf36e1_inst.sngfifo36e1_n_32\, - WRCOUNT(8) => \gf36e1_inst.sngfifo36e1_n_33\, - WRCOUNT(7) => \gf36e1_inst.sngfifo36e1_n_34\, - WRCOUNT(6) => \gf36e1_inst.sngfifo36e1_n_35\, - WRCOUNT(5) => \gf36e1_inst.sngfifo36e1_n_36\, - WRCOUNT(4) => \gf36e1_inst.sngfifo36e1_n_37\, - WRCOUNT(3) => \gf36e1_inst.sngfifo36e1_n_38\, - WRCOUNT(2) => \gf36e1_inst.sngfifo36e1_n_39\, - WRCOUNT(1) => \gf36e1_inst.sngfifo36e1_n_40\, - WRCOUNT(0) => \gf36e1_inst.sngfifo36e1_n_41\, - WREN => WR_EN, - WRERR => \gf36e1_inst.sngfifo36e1_n_15\ + I0 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[0]\, + I1 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[1]\, + I2 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[1]_i_2_n_0\, + O => ch2_dly_fast_cnt(1) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_rd_bin_cntr is - port ( - \gc1.count_d2_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); - sig_stream_rst : in STD_LOGIC; - E : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_mm2s_aclk : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_rd_bin_cntr : entity is "rd_bin_cntr"; -end Arty_Z7_20_axi_vdma_0_0_rd_bin_cntr; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_rd_bin_cntr is - signal \gc1.count[6]_i_2_n_0\ : STD_LOGIC; - signal \^gc1.count_d2_reg[6]_0\ : STD_LOGIC_VECTOR ( 6 downto 0 ); - signal plusOp : STD_LOGIC_VECTOR ( 6 downto 0 ); - signal rd_pntr_plus2 : STD_LOGIC_VECTOR ( 6 downto 0 ); - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \gc1.count[2]_i_1\ : label is "soft_lutpair47"; - attribute SOFT_HLUTNM of \gc1.count[3]_i_1\ : label is "soft_lutpair47"; - attribute SOFT_HLUTNM of \gc1.count[4]_i_1\ : label is "soft_lutpair46"; - attribute SOFT_HLUTNM of \gc1.count[6]_i_2\ : label is "soft_lutpair46"; -begin - \gc1.count_d2_reg[6]_0\(6 downto 0) <= \^gc1.count_d2_reg[6]_0\(6 downto 0); -\gc1.count[0]_i_1\: unisim.vcomponents.LUT1 +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[1]_i_2\: unisim.vcomponents.LUT5 generic map( - INIT => X"1" + INIT => X"FFFFFFFE" ) port map ( - I0 => rd_pntr_plus2(0), - O => plusOp(0) + I0 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[5]\, + I1 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[3]\, + I2 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[2]\, + I3 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[4]\, + I4 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[6]\, + O => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[1]_i_2_n_0\ ); -\gc1.count[1]_i_1\: unisim.vcomponents.LUT2 +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[2]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"6" + INIT => X"A9" ) port map ( - I0 => rd_pntr_plus2(0), - I1 => rd_pntr_plus2(1), - O => plusOp(1) + I0 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[2]\, + I1 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[0]\, + I2 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[1]\, + O => ch2_dly_fast_cnt(2) ); -\gc1.count[2]_i_1\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[3]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"78" + INIT => X"FE01" ) port map ( - I0 => rd_pntr_plus2(0), - I1 => rd_pntr_plus2(1), - I2 => rd_pntr_plus2(2), - O => plusOp(2) + I0 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[0]\, + I1 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[1]\, + I2 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[2]\, + I3 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[3]\, + O => ch2_dly_fast_cnt(3) ); -\gc1.count[3]_i_1\: unisim.vcomponents.LUT4 +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[4]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"7F80" + INIT => X"FFFE0001" ) port map ( - I0 => rd_pntr_plus2(1), - I1 => rd_pntr_plus2(0), - I2 => rd_pntr_plus2(2), - I3 => rd_pntr_plus2(3), - O => plusOp(3) + I0 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[0]\, + I1 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[1]\, + I2 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[3]\, + I3 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[2]\, + I4 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[4]\, + O => ch2_dly_fast_cnt(4) ); -\gc1.count[4]_i_1\: unisim.vcomponents.LUT5 +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[5]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"7FFF8000" + INIT => X"FFFFFFFE00000001" ) port map ( - I0 => rd_pntr_plus2(2), - I1 => rd_pntr_plus2(0), - I2 => rd_pntr_plus2(1), - I3 => rd_pntr_plus2(3), - I4 => rd_pntr_plus2(4), - O => plusOp(4) + I0 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[0]\, + I1 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[1]\, + I2 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[4]\, + I3 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[2]\, + I4 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[3]\, + I5 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[5]\, + O => ch2_dly_fast_cnt(5) ); -\gc1.count[5]_i_1\: unisim.vcomponents.LUT6 +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[6]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"7FFFFFFF80000000" + INIT => X"FFFFFFFE00000001" ) port map ( - I0 => rd_pntr_plus2(3), - I1 => rd_pntr_plus2(1), - I2 => rd_pntr_plus2(0), - I3 => rd_pntr_plus2(2), - I4 => rd_pntr_plus2(4), - I5 => rd_pntr_plus2(5), - O => plusOp(5) + I0 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[6]_i_3_n_0\, + I1 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[5]\, + I2 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[3]\, + I3 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[2]\, + I4 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[4]\, + I5 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[6]\, + O => ch2_dly_fast_cnt(6) ); -\gc1.count[6]_i_1\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[6]_i_3\: unisim.vcomponents.LUT2 generic map( - INIT => X"78" + INIT => X"E" ) port map ( - I0 => \gc1.count[6]_i_2_n_0\, - I1 => rd_pntr_plus2(5), - I2 => rd_pntr_plus2(6), - O => plusOp(6) + I0 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[0]\, + I1 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[1]\, + O => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[6]_i_3_n_0\ ); -\gc1.count[6]_i_2\: unisim.vcomponents.LUT5 +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => X"80000000" + INIT => '0' ) port map ( - I0 => rd_pntr_plus2(4), - I1 => rd_pntr_plus2(2), - I2 => rd_pntr_plus2(0), - I3 => rd_pntr_plus2(1), - I4 => rd_pntr_plus2(3), - O => \gc1.count[6]_i_2_n_0\ + C => m_axi_s2mm_aclk, + CE => '1', + D => ch2_dly_fast_cnt(0), + Q => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[0]\, + R => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0\(0) ); -\gc1.count_d1_reg[0]\: unisim.vcomponents.FDSE +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[1]\: unisim.vcomponents.FDRE generic map( - INIT => '1' + INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => rd_pntr_plus2(0), - Q => \^gc1.count_d2_reg[6]_0\(0), - S => sig_stream_rst + C => m_axi_s2mm_aclk, + CE => '1', + D => ch2_dly_fast_cnt(1), + Q => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[1]\, + R => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0\(0) ); -\gc1.count_d1_reg[1]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[2]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => rd_pntr_plus2(1), - Q => \^gc1.count_d2_reg[6]_0\(1), - R => sig_stream_rst + C => m_axi_s2mm_aclk, + CE => '1', + D => ch2_dly_fast_cnt(2), + Q => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[2]\, + S => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0\(0) ); -\gc1.count_d1_reg[2]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[3]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => rd_pntr_plus2(2), - Q => \^gc1.count_d2_reg[6]_0\(2), - R => sig_stream_rst + C => m_axi_s2mm_aclk, + CE => '1', + D => ch2_dly_fast_cnt(3), + Q => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[3]\, + S => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0\(0) ); -\gc1.count_d1_reg[3]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[4]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => rd_pntr_plus2(3), - Q => \^gc1.count_d2_reg[6]_0\(3), - R => sig_stream_rst + C => m_axi_s2mm_aclk, + CE => '1', + D => ch2_dly_fast_cnt(4), + Q => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[4]\, + S => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0\(0) ); -\gc1.count_d1_reg[4]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[5]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => rd_pntr_plus2(4), - Q => \^gc1.count_d2_reg[6]_0\(4), - R => sig_stream_rst + C => m_axi_s2mm_aclk, + CE => '1', + D => ch2_dly_fast_cnt(5), + Q => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[5]\, + S => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0\(0) ); -\gc1.count_d1_reg[5]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => rd_pntr_plus2(5), - Q => \^gc1.count_d2_reg[6]_0\(5), - R => sig_stream_rst + C => m_axi_s2mm_aclk, + CE => '1', + D => ch2_dly_fast_cnt(6), + Q => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[6]\, + S => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0\(0) ); -\gc1.count_d1_reg[6]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"0000000000000001" ) port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => rd_pntr_plus2(6), - Q => \^gc1.count_d2_reg[6]_0\(6), - R => sig_stream_rst + I0 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[6]\, + I1 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[4]\, + I2 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[2]\, + I3 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[3]\, + I4 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg_n_0_[5]\, + I5 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[6]_i_3_n_0\, + O => ch2_dly_fast_incr ); -\gc1.count_d2_reg[0]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => \^gc1.count_d2_reg[6]_0\(0), - Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(0), - R => sig_stream_rst + C => m_axi_s2mm_aclk, + CE => '1', + D => ch2_dly_fast_incr, + Q => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_reg_n_0\, + R => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0\(0) ); -\gc1.count_d2_reg[1]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => \^gc1.count_d2_reg[6]_0\(1), - Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(1), - R => sig_stream_rst + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg\, + Q => \^ch2_delay_cnt_en\, + R => '0' ); -\gc1.count_d2_reg[2]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[0]_i_1\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"1" ) port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => \^gc1.count_d2_reg[6]_0\(2), - Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(2), - R => sig_stream_rst + I0 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(0), + O => \plusOp__0\(0) ); -\gc1.count_d2_reg[3]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[1]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"6" ) port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => \^gc1.count_d2_reg[6]_0\(3), - Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(3), - R => sig_stream_rst + I0 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(0), + I1 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(1), + O => \plusOp__0\(1) ); -\gc1.count_d2_reg[4]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[2]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"78" ) port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => \^gc1.count_d2_reg[6]_0\(4), - Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(4), - R => sig_stream_rst + I0 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(0), + I1 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(1), + I2 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(2), + O => \plusOp__0\(2) ); -\gc1.count_d2_reg[5]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[3]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"7F80" ) port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => \^gc1.count_d2_reg[6]_0\(5), - Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(5), - R => sig_stream_rst + I0 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(2), + I1 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(1), + I2 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(0), + I3 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(3), + O => \plusOp__0\(3) ); -\gc1.count_d2_reg[6]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(3), + I1 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(0), + I2 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(1), + I3 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(2), + I4 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(4), + O => \plusOp__0\(4) + ); +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFFFFFF80000000" + ) + port map ( + I0 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(2), + I1 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(1), + I2 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(0), + I3 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(3), + I4 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(4), + I5 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(5), + O => \plusOp__0\(5) + ); +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[6]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_4_n_0\, + I1 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(6), + O => \plusOp__0\(6) + ); +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFBBBBBFBB" + ) + port map ( + I0 => prmry_resetn_i_reg_1, + I1 => \^ch2_delay_cnt_en\, + I2 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_3_n_0\, + I3 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_reg_n_0\, + I4 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_4_n_0\, + I5 => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out_0\, + O => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_1_n_0\ + ); +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"D2" + ) + port map ( + I0 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(6), + I1 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_4_n_0\, + I2 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(7), + O => \plusOp__0\(7) + ); +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFFFFFFFFFFFFFF" + ) + port map ( + I0 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(2), + I1 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(1), + I2 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(0), + I3 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(3), + I4 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(4), + I5 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(5), + O => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_4_n_0\ + ); +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => \^gc1.count_d2_reg[6]_0\(6), - Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(6), - R => sig_stream_rst + C => m_axi_s2mm_aclk, + CE => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_reg_n_0\, + D => \plusOp__0\(0), + Q => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(0), + R => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_1_n_0\ ); -\gc1.count_reg[0]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => plusOp(0), - Q => rd_pntr_plus2(0), - R => sig_stream_rst + C => m_axi_s2mm_aclk, + CE => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_reg_n_0\, + D => \plusOp__0\(1), + Q => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(1), + R => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_1_n_0\ ); -\gc1.count_reg[1]\: unisim.vcomponents.FDSE +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[2]\: unisim.vcomponents.FDRE generic map( - INIT => '1' + INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => plusOp(1), - Q => rd_pntr_plus2(1), - S => sig_stream_rst + C => m_axi_s2mm_aclk, + CE => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_reg_n_0\, + D => \plusOp__0\(2), + Q => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(2), + R => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_1_n_0\ ); -\gc1.count_reg[2]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => plusOp(2), - Q => rd_pntr_plus2(2), - R => sig_stream_rst + C => m_axi_s2mm_aclk, + CE => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_reg_n_0\, + D => \plusOp__0\(3), + Q => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(3), + R => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_1_n_0\ ); -\gc1.count_reg[3]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => plusOp(3), - Q => rd_pntr_plus2(3), - R => sig_stream_rst + C => m_axi_s2mm_aclk, + CE => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_reg_n_0\, + D => \plusOp__0\(4), + Q => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(4), + R => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_1_n_0\ ); -\gc1.count_reg[4]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => plusOp(4), - Q => rd_pntr_plus2(4), - R => sig_stream_rst + C => m_axi_s2mm_aclk, + CE => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_reg_n_0\, + D => \plusOp__0\(5), + Q => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(5), + R => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_1_n_0\ ); -\gc1.count_reg[5]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => plusOp(5), - Q => rd_pntr_plus2(5), - R => sig_stream_rst + C => m_axi_s2mm_aclk, + CE => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_reg_n_0\, + D => \plusOp__0\(6), + Q => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(6), + R => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_1_n_0\ ); -\gc1.count_reg[6]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => E(0), - D => plusOp(6), - Q => rd_pntr_plus2(6), - R => sig_stream_rst + C => m_axi_s2mm_aclk, + CE => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_reg_n_0\, + D => \plusOp__0\(7), + Q => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(7), + R => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_1_n_0\ ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_rd_fwft is - port ( - \out\ : out STD_LOGIC; - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - \gc1.count_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - dm2linebuf_mm2s_tvalid : out STD_LOGIC; - hold_ff_q_reg : out STD_LOGIC; - \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : out STD_LOGIC; - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC; - sig_stream_rst : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - ram_full_i_reg : in STD_LOGIC; - ram_empty_fb_i_reg : in STD_LOGIC; - lsig_cmd_loaded : in STD_LOGIC; - hold_ff_q : in STD_LOGIC; - lsig_0ffset_cntr : in STD_LOGIC; - p_8_out : in STD_LOGIC; - sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - DOBDO : in STD_LOGIC_VECTOR ( 0 to 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_rd_fwft : entity is "rd_fwft"; -end Arty_Z7_20_axi_vdma_0_0_rd_fwft; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_rd_fwft is - signal \INCLUDE_UNPACKING.lsig_cmd_loaded_i_2_n_0\ : STD_LOGIC; - signal aempty_fwft_fb_i : STD_LOGIC; - attribute DONT_TOUCH : boolean; - attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true; - signal aempty_fwft_i : STD_LOGIC; - attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true; - signal \aempty_fwft_i0__6\ : STD_LOGIC; - signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 ); - attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true; - signal \^dm2linebuf_mm2s_tvalid\ : STD_LOGIC; - signal empty_fwft_fb_i : STD_LOGIC; - attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true; - signal empty_fwft_fb_o_i : STD_LOGIC; - attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true; - signal empty_fwft_fb_o_i_reg0 : STD_LOGIC; - signal empty_fwft_i : STD_LOGIC; - attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true; - signal \empty_fwft_i0__1\ : STD_LOGIC; - signal \^gc1.count_reg[0]\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal \sig_pop_data_fifo__3\ : STD_LOGIC; - signal user_valid : STD_LOGIC; - attribute DONT_TOUCH of user_valid : signal is std.standard.true; - attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true; - attribute KEEP : string; - attribute KEEP of aempty_fwft_fb_i_reg : label is "yes"; - attribute equivalent_register_removal : string; - attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no"; - attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true; - attribute KEEP of aempty_fwft_i_reg : label is "yes"; - attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no"; - attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true; - attribute KEEP of empty_fwft_fb_i_reg : label is "yes"; - attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no"; - attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true; - attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes"; - attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no"; - attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true; - attribute KEEP of empty_fwft_i_reg : label is "yes"; - attribute equivalent_register_removal of empty_fwft_i_reg : label is "no"; - attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true; - attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes"; - attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no"; - attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true; - attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes"; - attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no"; - attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true; - attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes"; - attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no"; -begin - dm2linebuf_mm2s_tvalid <= \^dm2linebuf_mm2s_tvalid\; - \gc1.count_reg[0]\(0) <= \^gc1.count_reg[0]\(0); - \out\ <= user_valid; -\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_3\: unisim.vcomponents.LUT4 +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"B0FF" + INIT => X"00000010" ) port map ( - I0 => \sig_pop_data_fifo__3\, - I1 => curr_fwft_state(0), - I2 => curr_fwft_state(1), - I3 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ + I0 => ch2_delay_zero, + I1 => s2mm_packet_sof, + I2 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_reg_n_0\, + I3 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_3_n_0\, + I4 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_4_n_0\, + O => p_12_out ); -\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_9\: unisim.vcomponents.LUT5 +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_3\: unisim.vcomponents.LUT4 generic map( - INIT => X"80808000" + INIT => X"6FF6" ) port map ( - I0 => lsig_0ffset_cntr, - I1 => p_8_out, - I2 => lsig_cmd_loaded, - I3 => user_valid, - I4 => hold_ff_q, - O => \sig_pop_data_fifo__3\ + I0 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(7), + I1 => s2mm_dmacr(15), + I2 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(6), + I3 => s2mm_dmacr(14), + O => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_3_n_0\ ); -\INCLUDE_UNPACKING.lsig_cmd_loaded_i_1\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"2F" + INIT => X"FFFFFFFFBEFFFFBE" ) port map ( - I0 => lsig_cmd_loaded, - I1 => \INCLUDE_UNPACKING.lsig_cmd_loaded_i_2_n_0\, - I2 => \INFERRED_GEN.cnt_i_reg[2]\(0), - O => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ + I0 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_6_n_0\, + I1 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(1), + I2 => s2mm_dmacr(9), + I3 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(0), + I4 => s2mm_dmacr(8), + I5 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_7_n_0\, + O => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_4_n_0\ ); -\INCLUDE_UNPACKING.lsig_cmd_loaded_i_2\: unisim.vcomponents.LUT6 +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_6\: unisim.vcomponents.LUT4 generic map( - INIT => X"8880000000000000" + INIT => X"6FF6" ) port map ( - I0 => p_8_out, - I1 => lsig_cmd_loaded, - I2 => user_valid, - I3 => hold_ff_q, - I4 => lsig_0ffset_cntr, - I5 => DOBDO(0), - O => \INCLUDE_UNPACKING.lsig_cmd_loaded_i_2_n_0\ + I0 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(4), + I1 => s2mm_dmacr(12), + I2 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(3), + I3 => s2mm_dmacr(11), + O => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_6_n_0\ ); -aempty_fwft_fb_i_i_1: unisim.vcomponents.LUT5 +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_7\: unisim.vcomponents.LUT4 generic map( - INIT => X"EEFD8000" + INIT => X"6FF6" ) port map ( - I0 => curr_fwft_state(0), - I1 => ram_empty_fb_i_reg, - I2 => \sig_pop_data_fifo__3\, - I3 => curr_fwft_state(1), - I4 => aempty_fwft_fb_i, - O => \aempty_fwft_i0__6\ + I0 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(5), + I1 => s2mm_dmacr(13), + I2 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_count_reg[7]_0\(2), + I3 => s2mm_dmacr(10), + O => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_7_n_0\ ); -aempty_fwft_fb_i_reg: unisim.vcomponents.FDSE +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_reg\: unisim.vcomponents.FDRE generic map( - INIT => '1' + INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, + C => m_axi_s2mm_aclk, CE => '1', - D => \aempty_fwft_i0__6\, - Q => aempty_fwft_fb_i, - S => sig_stream_rst + D => p_12_out, + Q => ch2_dly_irq_set, + R => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0\(0) ); -aempty_fwft_i_reg: unisim.vcomponents.FDSE +\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_ioc_irq_set_i_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => '1' + INIT => X"00000800" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \aempty_fwft_i0__6\, - Q => aempty_fwft_i, - S => sig_stream_rst + I0 => ch2_ioc_irq_set_i, + I1 => s2mm_tstvect_fsync, + I2 => \^ch2_irqthresh_decr_mask_sig\, + I3 => prmry_resetn_i_reg_0, + I4 => p_6_out, + O => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_ioc_irq_set_i_i_1_n_0\ ); -\count[6]_i_1\: unisim.vcomponents.LUT2 +\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_ioc_irq_set_i_i_2\: unisim.vcomponents.LUT5 generic map( - INIT => X"6" + INIT => X"00010000" ) port map ( - I0 => \^gc1.count_reg[0]\(0), - I1 => ram_full_i_reg, - O => E(0) + I0 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(4), + I1 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(5), + I2 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(6), + I3 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(7), + I4 => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_7_n_0\, + O => ch2_ioc_irq_set_i ); -empty_fwft_fb_i_i_1: unisim.vcomponents.LUT4 +\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_ioc_irq_set_i_reg\: unisim.vcomponents.FDRE generic map( - INIT => X"F320" + INIT => '0' ) port map ( - I0 => \sig_pop_data_fifo__3\, - I1 => curr_fwft_state(1), - I2 => curr_fwft_state(0), - I3 => empty_fwft_fb_i, - O => \empty_fwft_i0__1\ + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_ioc_irq_set_i_i_1_n_0\, + Q => \^s2mm_ioc_irq_set\, + R => '0' ); -empty_fwft_fb_i_reg: unisim.vcomponents.FDSE +\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_irqthresh_decr_mask_sig_reg\: unisim.vcomponents.FDRE generic map( - INIT => '1' + INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, + C => m_axi_s2mm_aclk, CE => '1', - D => \empty_fwft_i0__1\, - Q => empty_fwft_fb_i, - S => sig_stream_rst + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg_0\, + Q => \^ch2_irqthresh_decr_mask_sig\, + R => prmry_resetn_i_reg(0) ); -empty_fwft_fb_o_i_i_1: unisim.vcomponents.LUT4 +\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[0]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"F320" + INIT => X"8B" ) port map ( - I0 => \sig_pop_data_fifo__3\, - I1 => curr_fwft_state(1), - I2 => curr_fwft_state(0), - I3 => empty_fwft_fb_o_i, - O => empty_fwft_fb_o_i_reg0 + I0 => s2mm_dmacr(0), + I1 => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_6_n_0\, + I2 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(0), + O => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[0]_i_1_n_0\ ); -empty_fwft_fb_o_i_reg: unisim.vcomponents.FDSE +\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[1]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => '1' + INIT => X"F099" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => empty_fwft_fb_o_i_reg0, - Q => empty_fwft_fb_o_i, - S => sig_stream_rst + I0 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(0), + I1 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(1), + I2 => s2mm_dmacr(1), + I3 => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_6_n_0\, + O => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[1]_i_1_n_0\ ); -empty_fwft_i_reg: unisim.vcomponents.FDSE +\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[2]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => '1' + INIT => X"FF00A9A9" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \empty_fwft_i0__1\, - Q => empty_fwft_i, - S => sig_stream_rst + I0 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(2), + I1 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(1), + I2 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(0), + I3 => s2mm_dmacr(2), + I4 => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_6_n_0\, + O => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[2]_i_1_n_0\ ); -\gc1.count_d1[6]_i_1\: unisim.vcomponents.LUT6 +\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[3]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"00000000F7777777" + INIT => X"FFFF0000AAA9AAA9" ) port map ( - I0 => curr_fwft_state(0), - I1 => curr_fwft_state(1), - I2 => \^dm2linebuf_mm2s_tvalid\, - I3 => p_8_out, - I4 => lsig_0ffset_cntr, - I5 => ram_empty_fb_i_reg, - O => \^gc1.count_reg[0]\(0) + I0 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(3), + I1 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(0), + I2 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(1), + I3 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(2), + I4 => s2mm_dmacr(3), + I5 => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_6_n_0\, + O => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[3]_i_1_n_0\ ); -\gc1.count_d1[6]_i_2\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[4]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"A8" + INIT => X"F099" ) port map ( - I0 => lsig_cmd_loaded, - I1 => user_valid, - I2 => hold_ff_q, - O => \^dm2linebuf_mm2s_tvalid\ + I0 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(4), + I1 => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[6]_i_2_n_0\, + I2 => s2mm_dmacr(4), + I3 => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_6_n_0\, + O => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[4]_i_1_n_0\ ); -\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[5]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"BA" + INIT => X"FF00A9A9" ) port map ( - I0 => curr_fwft_state(1), - I1 => \sig_pop_data_fifo__3\, - I2 => curr_fwft_state(0), - O => next_fwft_state(0) + I0 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(5), + I1 => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[6]_i_2_n_0\, + I2 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(4), + I3 => s2mm_dmacr(5), + I4 => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_6_n_0\, + O => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[5]_i_1_n_0\ ); -\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4 +\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[6]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"20FF" + INIT => X"FFFF0000AAA9AAA9" ) port map ( - I0 => curr_fwft_state(1), - I1 => \sig_pop_data_fifo__3\, - I2 => curr_fwft_state(0), - I3 => ram_empty_fb_i_reg, - O => next_fwft_state(1) + I0 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(6), + I1 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(4), + I2 => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[6]_i_2_n_0\, + I3 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(5), + I4 => s2mm_dmacr(6), + I5 => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_6_n_0\, + O => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[6]_i_1_n_0\ ); -\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[6]_i_2\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"FFFE" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => next_fwft_state(0), - Q => curr_fwft_state(0), - R => sig_stream_rst + I0 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(2), + I1 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(1), + I2 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(0), + I3 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(3), + O => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[6]_i_2_n_0\ ); -\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_2\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"F4" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => next_fwft_state(1), - Q => curr_fwft_state(1), - R => sig_stream_rst + I0 => \^ch2_irqthresh_decr_mask_sig\, + I1 => s2mm_tstvect_fsync, + I2 => p_6_out, + O => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_2_n_0\ ); -\gpregsm1.user_valid_reg\: unisim.vcomponents.FDRE +\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_3\: unisim.vcomponents.LUT5 generic map( - INIT => '0' + INIT => X"FF00A9A9" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => next_fwft_state(0), - Q => user_valid, - R => sig_stream_rst + I0 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(7), + I1 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(6), + I2 => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_5_n_0\, + I3 => s2mm_dmacr(7), + I4 => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_6_n_0\, + O => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_3_n_0\ ); -hold_ff_q_i_1: unisim.vcomponents.LUT4 +\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_5\: unisim.vcomponents.LUT6 generic map( - INIT => X"00E0" + INIT => X"FFFFFFFFFFFFFFFE" ) port map ( - I0 => user_valid, - I1 => hold_ff_q, - I2 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - I3 => \sig_pop_data_fifo__3\, - O => hold_ff_q_reg + I0 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(4), + I1 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(2), + I2 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(1), + I3 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(0), + I4 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(3), + I5 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(5), + O => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_5_n_0\ ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_rd_status_flags_ss is - port ( - \out\ : out STD_LOGIC; - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC; - sig_stream_rst : in STD_LOGIC; - \ram_empty_i0__3\ : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - E : in STD_LOGIC_VECTOR ( 0 to 0 ); - sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_rd_status_flags_ss : entity is "rd_status_flags_ss"; -end Arty_Z7_20_axi_vdma_0_0_rd_status_flags_ss; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_rd_status_flags_ss is - signal ram_empty_fb_i : STD_LOGIC; - attribute DONT_TOUCH : boolean; - attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true; - signal ram_empty_i : STD_LOGIC; - attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true; - attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true; - attribute KEEP : string; - attribute KEEP of ram_empty_fb_i_reg : label is "yes"; - attribute equivalent_register_removal : string; - attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no"; - attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true; - attribute KEEP of ram_empty_i_reg : label is "yes"; - attribute equivalent_register_removal of ram_empty_i_reg : label is "no"; -begin - \out\ <= ram_empty_fb_i; -\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1\: unisim.vcomponents.LUT3 +\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_6\: unisim.vcomponents.LUT6 generic map( - INIT => X"4F" + INIT => X"FFFFFFFF00000002" ) port map ( - I0 => ram_empty_fb_i, - I1 => E(0), - I2 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ + I0 => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_7_n_0\, + I1 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(7), + I2 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(6), + I3 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(5), + I4 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(4), + I5 => p_6_out, + O => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_6_n_0\ ); -ram_empty_fb_i_reg: unisim.vcomponents.FDSE +\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_7\: unisim.vcomponents.LUT4 generic map( - INIT => '1' + INIT => X"0004" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \ram_empty_i0__3\, - Q => ram_empty_fb_i, - S => sig_stream_rst + I0 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(1), + I1 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(0), + I2 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(3), + I3 => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(2), + O => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_7_n_0\ ); -ram_empty_i_reg: unisim.vcomponents.FDSE +\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \ram_empty_i0__3\, - Q => ram_empty_i, - S => sig_stream_rst + C => m_axi_s2mm_aclk, + CE => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_2_n_0\, + D => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[0]_i_1_n_0\, + Q => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(0), + S => prmry_resetn_i_reg(0) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_reset_builtin is - port ( - RST : out STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - s_axis_fifo_ainit_nosync_reg : in STD_LOGIC; - m_axis_mm2s_aclk : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_reset_builtin : entity is "reset_builtin"; -end Arty_Z7_20_axi_vdma_0_0_reset_builtin; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_reset_builtin is - signal power_on_rd_rst : STD_LOGIC_VECTOR ( 5 downto 0 ); - attribute async_reg : string; - attribute async_reg of power_on_rd_rst : signal is "true"; - attribute msgon : string; - attribute msgon of power_on_rd_rst : signal is "true"; - signal power_on_wr_rst : STD_LOGIC_VECTOR ( 5 downto 0 ); - attribute async_reg of power_on_wr_rst : signal is "true"; - attribute msgon of power_on_wr_rst : signal is "true"; - signal rd_rst_reg : STD_LOGIC; - signal rd_rst_reg1 : STD_LOGIC; - attribute async_reg of rd_rst_reg1 : signal is "true"; - attribute msgon of rd_rst_reg1 : signal is "true"; - signal rd_rst_reg2 : STD_LOGIC; - attribute async_reg of rd_rst_reg2 : signal is "true"; - attribute msgon of rd_rst_reg2 : signal is "true"; - signal \rsync.ric.rd_rst_fb_reg[1]_srl4_n_0\ : STD_LOGIC; - signal \rsync.ric.rd_rst_fb_reg_n_0_[0]\ : STD_LOGIC; - signal \rsync.ric.rd_rst_reg_i_1_n_0\ : STD_LOGIC; - signal wr_rst_reg1 : STD_LOGIC; - attribute async_reg of wr_rst_reg1 : signal is "true"; - attribute msgon of wr_rst_reg1 : signal is "true"; - signal wr_rst_reg2 : STD_LOGIC; - attribute async_reg of wr_rst_reg2 : signal is "true"; - attribute msgon of wr_rst_reg2 : signal is "true"; - attribute ASYNC_REG_boolean : boolean; - attribute ASYNC_REG_boolean of \rsync.ric.power_on_rd_rst_reg[0]\ : label is std.standard.true; - attribute KEEP : string; - attribute KEEP of \rsync.ric.power_on_rd_rst_reg[0]\ : label is "yes"; - attribute msgon of \rsync.ric.power_on_rd_rst_reg[0]\ : label is "true"; - attribute ASYNC_REG_boolean of \rsync.ric.power_on_rd_rst_reg[1]\ : label is std.standard.true; - attribute KEEP of \rsync.ric.power_on_rd_rst_reg[1]\ : label is "yes"; - attribute msgon of \rsync.ric.power_on_rd_rst_reg[1]\ : label is "true"; - attribute ASYNC_REG_boolean of \rsync.ric.power_on_rd_rst_reg[2]\ : label is std.standard.true; - attribute KEEP of \rsync.ric.power_on_rd_rst_reg[2]\ : label is "yes"; - attribute msgon of \rsync.ric.power_on_rd_rst_reg[2]\ : label is "true"; - attribute ASYNC_REG_boolean of \rsync.ric.power_on_rd_rst_reg[3]\ : label is std.standard.true; - attribute KEEP of \rsync.ric.power_on_rd_rst_reg[3]\ : label is "yes"; - attribute msgon of \rsync.ric.power_on_rd_rst_reg[3]\ : label is "true"; - attribute ASYNC_REG_boolean of \rsync.ric.power_on_rd_rst_reg[4]\ : label is std.standard.true; - attribute KEEP of \rsync.ric.power_on_rd_rst_reg[4]\ : label is "yes"; - attribute msgon of \rsync.ric.power_on_rd_rst_reg[4]\ : label is "true"; - attribute ASYNC_REG_boolean of \rsync.ric.power_on_rd_rst_reg[5]\ : label is std.standard.true; - attribute KEEP of \rsync.ric.power_on_rd_rst_reg[5]\ : label is "yes"; - attribute msgon of \rsync.ric.power_on_rd_rst_reg[5]\ : label is "true"; - attribute ASYNC_REG_boolean of \rsync.ric.power_on_wr_rst_reg[0]\ : label is std.standard.true; - attribute KEEP of \rsync.ric.power_on_wr_rst_reg[0]\ : label is "yes"; - attribute msgon of \rsync.ric.power_on_wr_rst_reg[0]\ : label is "true"; - attribute ASYNC_REG_boolean of \rsync.ric.power_on_wr_rst_reg[1]\ : label is std.standard.true; - attribute KEEP of \rsync.ric.power_on_wr_rst_reg[1]\ : label is "yes"; - attribute msgon of \rsync.ric.power_on_wr_rst_reg[1]\ : label is "true"; - attribute ASYNC_REG_boolean of \rsync.ric.power_on_wr_rst_reg[2]\ : label is std.standard.true; - attribute KEEP of \rsync.ric.power_on_wr_rst_reg[2]\ : label is "yes"; - attribute msgon of \rsync.ric.power_on_wr_rst_reg[2]\ : label is "true"; - attribute ASYNC_REG_boolean of \rsync.ric.power_on_wr_rst_reg[3]\ : label is std.standard.true; - attribute KEEP of \rsync.ric.power_on_wr_rst_reg[3]\ : label is "yes"; - attribute msgon of \rsync.ric.power_on_wr_rst_reg[3]\ : label is "true"; - attribute ASYNC_REG_boolean of \rsync.ric.power_on_wr_rst_reg[4]\ : label is std.standard.true; - attribute KEEP of \rsync.ric.power_on_wr_rst_reg[4]\ : label is "yes"; - attribute msgon of \rsync.ric.power_on_wr_rst_reg[4]\ : label is "true"; - attribute ASYNC_REG_boolean of \rsync.ric.power_on_wr_rst_reg[5]\ : label is std.standard.true; - attribute KEEP of \rsync.ric.power_on_wr_rst_reg[5]\ : label is "yes"; - attribute msgon of \rsync.ric.power_on_wr_rst_reg[5]\ : label is "true"; - attribute srl_bus_name : string; - attribute srl_bus_name of \rsync.ric.rd_rst_fb_reg[1]_srl4\ : label is "U0/\GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.rd_rst_fb_reg "; - attribute srl_name : string; - attribute srl_name of \rsync.ric.rd_rst_fb_reg[1]_srl4\ : label is "U0/\GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.rd_rst_fb_reg[1]_srl4 "; - attribute ASYNC_REG_boolean of \rsync.ric.rd_rst_reg1_reg\ : label is std.standard.true; - attribute KEEP of \rsync.ric.rd_rst_reg1_reg\ : label is "yes"; - attribute msgon of \rsync.ric.rd_rst_reg1_reg\ : label is "true"; - attribute ASYNC_REG_boolean of \rsync.ric.rd_rst_reg2_reg\ : label is std.standard.true; - attribute KEEP of \rsync.ric.rd_rst_reg2_reg\ : label is "yes"; - attribute msgon of \rsync.ric.rd_rst_reg2_reg\ : label is "true"; - attribute ASYNC_REG_boolean of \rsync.ric.wr_rst_reg1_reg\ : label is std.standard.true; - attribute KEEP of \rsync.ric.wr_rst_reg1_reg\ : label is "yes"; - attribute msgon of \rsync.ric.wr_rst_reg1_reg\ : label is "true"; - attribute ASYNC_REG_boolean of \rsync.ric.wr_rst_reg2_reg\ : label is std.standard.true; - attribute KEEP of \rsync.ric.wr_rst_reg2_reg\ : label is "yes"; - attribute msgon of \rsync.ric.wr_rst_reg2_reg\ : label is "true"; -begin -\gf36e1_inst.sngfifo36e1_i_2__2\: unisim.vcomponents.LUT2 +\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[1]\: unisim.vcomponents.FDRE generic map( - INIT => X"E" + INIT => '0' ) port map ( - I0 => rd_rst_reg, - I1 => power_on_rd_rst(0), - O => RST + C => m_axi_s2mm_aclk, + CE => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_2_n_0\, + D => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[1]_i_1_n_0\, + Q => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(1), + R => prmry_resetn_i_reg(0) ); -\rsync.ric.power_on_rd_rst_reg[0]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[2]\: unisim.vcomponents.FDRE generic map( - INIT => '1' + INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => power_on_rd_rst(1), - Q => power_on_rd_rst(0), - R => '0' + C => m_axi_s2mm_aclk, + CE => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_2_n_0\, + D => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[2]_i_1_n_0\, + Q => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(2), + R => prmry_resetn_i_reg(0) ); -\rsync.ric.power_on_rd_rst_reg[1]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[3]\: unisim.vcomponents.FDRE generic map( - INIT => '1' + INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => power_on_rd_rst(2), - Q => power_on_rd_rst(1), - R => '0' + C => m_axi_s2mm_aclk, + CE => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_2_n_0\, + D => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[3]_i_1_n_0\, + Q => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(3), + R => prmry_resetn_i_reg(0) ); -\rsync.ric.power_on_rd_rst_reg[2]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[4]\: unisim.vcomponents.FDRE generic map( - INIT => '1' + INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => power_on_rd_rst(3), - Q => power_on_rd_rst(2), - R => '0' + C => m_axi_s2mm_aclk, + CE => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_2_n_0\, + D => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[4]_i_1_n_0\, + Q => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(4), + R => prmry_resetn_i_reg(0) ); -\rsync.ric.power_on_rd_rst_reg[3]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[5]\: unisim.vcomponents.FDRE generic map( - INIT => '1' + INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => power_on_rd_rst(4), - Q => power_on_rd_rst(3), - R => '0' + C => m_axi_s2mm_aclk, + CE => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_2_n_0\, + D => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[5]_i_1_n_0\, + Q => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(5), + R => prmry_resetn_i_reg(0) ); -\rsync.ric.power_on_rd_rst_reg[4]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[6]\: unisim.vcomponents.FDRE generic map( - INIT => '1' + INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => power_on_rd_rst(5), - Q => power_on_rd_rst(4), - R => '0' + C => m_axi_s2mm_aclk, + CE => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_2_n_0\, + D => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[6]_i_1_n_0\, + Q => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(6), + R => prmry_resetn_i_reg(0) ); -\rsync.ric.power_on_rd_rst_reg[5]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]\: unisim.vcomponents.FDRE generic map( - INIT => '1' + INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => '0', - Q => power_on_rd_rst(5), - R => '0' + C => m_axi_s2mm_aclk, + CE => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_2_n_0\, + D => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_3_n_0\, + Q => \^gen_include_s2mm.gen_ch2_frm_cntr.ch2_thresh_count_reg[7]_0\(7), + R => prmry_resetn_i_reg(0) ); -\rsync.ric.power_on_wr_rst_reg[0]\: unisim.vcomponents.FDRE +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_mux is + port ( + \out\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + in0 : in STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_mux : entity is "axi_vdma_reg_mux"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_mux; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_mux is + signal ip2axi_rddata_int : STD_LOGIC_VECTOR ( 31 downto 0 ); + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of ip2axi_rddata_int : signal is std.standard.true; +begin + ip2axi_rddata_int(31 downto 0) <= in0(31 downto 0); + \out\(31 downto 0) <= ip2axi_rddata_int(31 downto 0); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_mux__parameterized0\ is + port ( + \out\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_mux__parameterized0\ : entity is "axi_vdma_reg_mux"; +end \Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_mux__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_mux__parameterized0\ is + signal ip2axi_rddata_int : STD_LOGIC_VECTOR ( 31 downto 0 ); + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of ip2axi_rddata_int : signal is std.standard.true; +begin + ip2axi_rddata_int(31 downto 0) <= \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(31 downto 0); + \out\(31 downto 0) <= ip2axi_rddata_int(31 downto 0); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_regdirect is + port ( + p_67_out : out STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0]\ : out STD_LOGIC; + \hsize_vid_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \vsize_vid_reg[12]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); + \stride_vid_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + in0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3]\ : out STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4]\ : out STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5]\ : out STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6]\ : out STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7]\ : out STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8]\ : out STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9]\ : out STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10]\ : out STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]\ : out STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]\ : out STD_LOGIC; + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg\ : out STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + \dmacr_i_reg[0]\ : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[2]\ : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]\ : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_0\ : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[4]\ : in STD_LOGIC; + p_71_out : in STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_1\ : in STD_LOGIC; + \dmacr_i_reg[2]\ : in STD_LOGIC; + \GEN_NOSYNCEN_BIT.dmacr_i_reg[15]\ : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]_0\ : in STD_LOGIC; + stop : in STD_LOGIC; + prmry_resetn_i_reg : in STD_LOGIC; + halted_reg : in STD_LOGIC; + p_24_out : in STD_LOGIC; + prmtr_update_complete : in STD_LOGIC; + mm2s_axi2ip_wrce : in STD_LOGIC_VECTOR ( 5 downto 0 ); + D : in STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_regdirect : entity is "axi_vdma_regdirect"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_regdirect; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_regdirect is + signal \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \^hsize_vid_reg[15]\ : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal ip2axi_rddata_int_inferred_i_51_n_0 : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_74_n_0 : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_75_n_0 : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_79_n_0 : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_80_n_0 : STD_LOGIC; + signal p_66_out : STD_LOGIC; + signal \^p_67_out\ : STD_LOGIC; + signal regdir_idle_i_i_1_n_0 : STD_LOGIC; + signal run_stop_d1 : STD_LOGIC; + signal \^stride_vid_reg[15]\ : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \^vsize_vid_reg[12]\ : STD_LOGIC_VECTOR ( 12 downto 0 ); +begin + \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(31 downto 0) <= \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(31 downto 0); + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(31 downto 0) <= \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(31 downto 0); + \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(31 downto 0) <= \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(31 downto 0); + \hsize_vid_reg[15]\(15 downto 0) <= \^hsize_vid_reg[15]\(15 downto 0); + p_67_out <= \^p_67_out\; + \stride_vid_reg[15]\(15 downto 0) <= \^stride_vid_reg[15]\(15 downto 0); + \vsize_vid_reg[12]\(12 downto 0) <= \^vsize_vid_reg[12]\(12 downto 0); +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => '1' + INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => power_on_wr_rst(1), - Q => power_on_wr_rst(0), - R => '0' + CE => mm2s_axi2ip_wrce(3), + D => D(0), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(0), + R => SR(0) ); -\rsync.ric.power_on_wr_rst_reg[1]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[10]\: unisim.vcomponents.FDRE generic map( - INIT => '1' + INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => power_on_wr_rst(2), - Q => power_on_wr_rst(1), - R => '0' + CE => mm2s_axi2ip_wrce(3), + D => D(10), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(10), + R => SR(0) ); -\rsync.ric.power_on_wr_rst_reg[2]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[11]\: unisim.vcomponents.FDRE generic map( - INIT => '1' + INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => power_on_wr_rst(3), - Q => power_on_wr_rst(2), - R => '0' + CE => mm2s_axi2ip_wrce(3), + D => D(11), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(11), + R => SR(0) ); -\rsync.ric.power_on_wr_rst_reg[3]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[12]\: unisim.vcomponents.FDRE generic map( - INIT => '1' + INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => power_on_wr_rst(4), - Q => power_on_wr_rst(3), - R => '0' + CE => mm2s_axi2ip_wrce(3), + D => D(12), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(12), + R => SR(0) ); -\rsync.ric.power_on_wr_rst_reg[4]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[13]\: unisim.vcomponents.FDRE generic map( - INIT => '1' + INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => power_on_wr_rst(5), - Q => power_on_wr_rst(4), - R => '0' + CE => mm2s_axi2ip_wrce(3), + D => D(13), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(13), + R => SR(0) ); -\rsync.ric.power_on_wr_rst_reg[5]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[14]\: unisim.vcomponents.FDRE generic map( - INIT => '1' + INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => '0', - Q => power_on_wr_rst(5), - R => '0' + CE => mm2s_axi2ip_wrce(3), + D => D(14), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(14), + R => SR(0) ); -\rsync.ric.rd_rst_fb_reg[0]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => \rsync.ric.rd_rst_fb_reg[1]_srl4_n_0\, - Q => \rsync.ric.rd_rst_fb_reg_n_0_[0]\, - R => '0' + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(3), + D => D(15), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(15), + R => SR(0) ); -\rsync.ric.rd_rst_fb_reg[1]_srl4\: unisim.vcomponents.SRL16E +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[16]\: unisim.vcomponents.FDRE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => '1', - A1 => '1', - A2 => '0', - A3 => '0', - CE => '1', - CLK => m_axis_mm2s_aclk, - D => rd_rst_reg, - Q => \rsync.ric.rd_rst_fb_reg[1]_srl4_n_0\ + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(3), + D => D(16), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(16), + R => SR(0) ); -\rsync.ric.rd_rst_reg1_reg\: unisim.vcomponents.FDPE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => '0', - PRE => s_axis_fifo_ainit_nosync_reg, - Q => rd_rst_reg1 + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(3), + D => D(17), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(17), + R => SR(0) ); -\rsync.ric.rd_rst_reg2_reg\: unisim.vcomponents.FDPE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => rd_rst_reg1, - PRE => s_axis_fifo_ainit_nosync_reg, - Q => rd_rst_reg2 + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(3), + D => D(18), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(18), + R => SR(0) ); -\rsync.ric.rd_rst_reg_i_1\: unisim.vcomponents.LUT2 +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[19]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => rd_rst_reg, - I1 => \rsync.ric.rd_rst_fb_reg_n_0_[0]\, - O => \rsync.ric.rd_rst_reg_i_1_n_0\ + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(3), + D => D(19), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(19), + R => SR(0) ); -\rsync.ric.rd_rst_reg_reg\: unisim.vcomponents.FDPE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => \rsync.ric.rd_rst_reg_i_1_n_0\, - PRE => rd_rst_reg2, - Q => rd_rst_reg + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(3), + D => D(1), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(1), + R => SR(0) ); -\rsync.ric.wr_rst_reg1_reg\: unisim.vcomponents.FDPE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => '0', - PRE => s_axis_fifo_ainit_nosync_reg, - Q => wr_rst_reg1 + CE => mm2s_axi2ip_wrce(3), + D => D(20), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(20), + R => SR(0) ); -\rsync.ric.wr_rst_reg2_reg\: unisim.vcomponents.FDPE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => wr_rst_reg1, - PRE => s_axis_fifo_ainit_nosync_reg, - Q => wr_rst_reg2 + CE => mm2s_axi2ip_wrce(3), + D => D(21), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(21), + R => SR(0) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_updn_cntr is - port ( - DI : out STD_LOGIC_VECTOR ( 3 downto 0 ); - Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); - sig_ok_to_post_rd_addr_reg : out STD_LOGIC; - S : out STD_LOGIC_VECTOR ( 3 downto 0 ); - \count_reg[6]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); - ram_full_i_reg : in STD_LOGIC; - \sig_token_cntr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); - sig_posted_to_axi_2_reg : in STD_LOGIC; - sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; - sig_posted_to_axi_2_reg_0 : in STD_LOGIC; - E : in STD_LOGIC_VECTOR ( 0 to 0 ); - sig_stream_rst : in STD_LOGIC; - \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - D : in STD_LOGIC_VECTOR ( 5 downto 0 ); - m_axi_mm2s_aclk : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_updn_cntr : entity is "updn_cntr"; -end Arty_Z7_20_axi_vdma_0_0_updn_cntr; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_updn_cntr is - signal \^di\ : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal \count[0]_i_1_n_0\ : STD_LOGIC; - signal \count_reg__0\ : STD_LOGIC_VECTOR ( 6 downto 5 ); - signal sig_ok_to_post_rd_addr_i_2_n_0 : STD_LOGIC; - signal sig_ok_to_post_rd_addr_i_4_n_0 : STD_LOGIC; - signal sig_ok_to_post_rd_addr_i_5_n_0 : STD_LOGIC; -begin - DI(3 downto 0) <= \^di\(3 downto 0); - Q(1 downto 0) <= \^q\(1 downto 0); -\count[0]_i_1\: unisim.vcomponents.LUT1 +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[22]\: unisim.vcomponents.FDRE generic map( - INIT => X"1" + INIT => '0' ) port map ( - I0 => \^q\(0), - O => \count[0]_i_1_n_0\ + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(3), + D => D(22), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(22), + R => SR(0) ); -\count_reg[0]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), - D => \count[0]_i_1_n_0\, - Q => \^q\(0), - R => sig_stream_rst + CE => mm2s_axi2ip_wrce(3), + D => D(23), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(23), + R => SR(0) ); -\count_reg[1]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), - D => D(0), - Q => \^di\(1), - R => sig_stream_rst + CE => mm2s_axi2ip_wrce(3), + D => D(24), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(24), + R => SR(0) ); -\count_reg[2]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), - D => D(1), - Q => \^di\(2), - R => sig_stream_rst + CE => mm2s_axi2ip_wrce(3), + D => D(25), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(25), + R => SR(0) ); -\count_reg[3]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), - D => D(2), - Q => \^di\(3), - R => sig_stream_rst + CE => mm2s_axi2ip_wrce(3), + D => D(26), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(26), + R => SR(0) ); -\count_reg[4]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), - D => D(3), - Q => \^q\(1), - R => sig_stream_rst + CE => mm2s_axi2ip_wrce(3), + D => D(27), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(27), + R => SR(0) ); -\count_reg[5]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), - D => D(4), - Q => \count_reg__0\(5), - R => sig_stream_rst + CE => mm2s_axi2ip_wrce(3), + D => D(28), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(28), + R => SR(0) ); -\count_reg[6]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), - D => D(5), - Q => \count_reg__0\(6), - R => sig_stream_rst + CE => mm2s_axi2ip_wrce(3), + D => D(29), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(29), + R => SR(0) ); -\p_0_out_carry__0_i_1\: unisim.vcomponents.LUT2 +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[2]\: unisim.vcomponents.FDRE generic map( - INIT => X"9" + INIT => '0' ) port map ( - I0 => \count_reg__0\(5), - I1 => \count_reg__0\(6), - O => \count_reg[6]_0\(1) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(3), + D => D(2), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(2), + R => SR(0) ); -\p_0_out_carry__0_i_2\: unisim.vcomponents.LUT2 +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[30]\: unisim.vcomponents.FDRE generic map( - INIT => X"9" + INIT => '0' ) port map ( - I0 => \^q\(1), - I1 => \count_reg__0\(5), - O => \count_reg[6]_0\(0) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(3), + D => D(30), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(30), + R => SR(0) ); -p_0_out_carry_i_1: unisim.vcomponents.LUT1 +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\: unisim.vcomponents.FDRE generic map( - INIT => X"1" + INIT => '0' ) port map ( - I0 => \^di\(1), - O => \^di\(0) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(3), + D => D(31), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(31), + R => SR(0) ); -p_0_out_carry_i_2: unisim.vcomponents.LUT2 +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[3]\: unisim.vcomponents.FDRE generic map( - INIT => X"9" + INIT => '0' ) port map ( - I0 => \^di\(3), - I1 => \^q\(1), - O => S(3) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(3), + D => D(3), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(3), + R => SR(0) ); -p_0_out_carry_i_3: unisim.vcomponents.LUT2 +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[4]\: unisim.vcomponents.FDRE generic map( - INIT => X"9" + INIT => '0' ) port map ( - I0 => \^di\(2), - I1 => \^di\(3), - O => S(2) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(3), + D => D(4), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(4), + R => SR(0) ); -p_0_out_carry_i_4: unisim.vcomponents.LUT2 +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[5]\: unisim.vcomponents.FDRE generic map( - INIT => X"9" + INIT => '0' ) port map ( - I0 => \^di\(1), - I1 => \^di\(2), - O => S(1) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(3), + D => D(5), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(5), + R => SR(0) ); -p_0_out_carry_i_5: unisim.vcomponents.LUT2 +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[6]\: unisim.vcomponents.FDRE generic map( - INIT => X"6" + INIT => '0' ) port map ( - I0 => \^di\(1), - I1 => E(0), - O => S(0) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(3), + D => D(6), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(6), + R => SR(0) ); -sig_ok_to_post_rd_addr_i_1: unisim.vcomponents.LUT5 +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[7]\: unisim.vcomponents.FDRE generic map( - INIT => X"00001000" + INIT => '0' ) port map ( - I0 => sig_ok_to_post_rd_addr_i_2_n_0, - I1 => sig_posted_to_axi_2_reg, - I2 => sig_ok_to_post_rd_addr_i_4_n_0, - I3 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - I4 => sig_posted_to_axi_2_reg_0, - O => sig_ok_to_post_rd_addr_reg + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(3), + D => D(7), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(7), + R => SR(0) ); -sig_ok_to_post_rd_addr_i_2: unisim.vcomponents.LUT6 +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[8]\: unisim.vcomponents.FDRE generic map( - INIT => X"FFFFFFFEEEEEEEEF" + INIT => '0' ) port map ( - I0 => sig_ok_to_post_rd_addr_i_5_n_0, - I1 => ram_full_i_reg, - I2 => \sig_token_cntr_reg[3]\(2), - I3 => \sig_token_cntr_reg[3]\(0), - I4 => \sig_token_cntr_reg[3]\(1), - I5 => \sig_token_cntr_reg[3]\(3), - O => sig_ok_to_post_rd_addr_i_2_n_0 + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(3), + D => D(8), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(8), + R => SR(0) ); -sig_ok_to_post_rd_addr_i_4: unisim.vcomponents.LUT6 +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[9]\: unisim.vcomponents.FDRE generic map( - INIT => X"DBFFFDBFFFDBBFFD" + INIT => '0' ) port map ( - I0 => \sig_token_cntr_reg[3]\(0), - I1 => \^q\(1), - I2 => \count_reg__0\(5), - I3 => \count_reg__0\(6), - I4 => \sig_token_cntr_reg[3]\(1), - I5 => \sig_token_cntr_reg[3]\(2), - O => sig_ok_to_post_rd_addr_i_4_n_0 + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(3), + D => D(9), + Q => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(9), + R => SR(0) ); -sig_ok_to_post_rd_addr_i_5: unisim.vcomponents.LUT6 +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => X"BBB82BB822B82228" + INIT => '0' ) port map ( - I0 => \count_reg__0\(6), - I1 => \sig_token_cntr_reg[3]\(2), - I2 => \sig_token_cntr_reg[3]\(0), - I3 => \sig_token_cntr_reg[3]\(1), - I4 => \^q\(1), - I5 => \count_reg__0\(5), - O => sig_ok_to_post_rd_addr_i_5_n_0 + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(4), + D => D(0), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(0), + R => SR(0) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_wr_bin_cntr is - port ( - \ram_empty_i0__3\ : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 6 downto 0 ); - ram_full_i_reg : out STD_LOGIC; - p_7_out : in STD_LOGIC; - E : in STD_LOGIC_VECTOR ( 0 to 0 ); - ram_empty_fb_i_reg : in STD_LOGIC; - \gc1.count_d2_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); - \gc1.count_d1_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); - \out\ : in STD_LOGIC; - sig_stream_rst : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_wr_bin_cntr : entity is "wr_bin_cntr"; -end Arty_Z7_20_axi_vdma_0_0_wr_bin_cntr; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_wr_bin_cntr is - signal \^q\ : STD_LOGIC_VECTOR ( 6 downto 0 ); - signal \gcc0.gc0.count[6]_i_2_n_0\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1\ : STD_LOGIC; - signal \gwss.wsts/comp0\ : STD_LOGIC; - signal \gwss.wsts/comp1\ : STD_LOGIC; - signal p_12_out : STD_LOGIC_VECTOR ( 6 downto 0 ); - signal \plusOp__0\ : STD_LOGIC_VECTOR ( 6 downto 0 ); - signal ram_empty_fb_i_i_3_n_0 : STD_LOGIC; - signal ram_empty_fb_i_i_4_n_0 : STD_LOGIC; - signal ram_full_fb_i_i_4_n_0 : STD_LOGIC; - signal ram_full_fb_i_i_5_n_0 : STD_LOGIC; - signal ram_full_fb_i_i_6_n_0 : STD_LOGIC; - signal ram_full_fb_i_i_7_n_0 : STD_LOGIC; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \gcc0.gc0.count[1]_i_1\ : label is "soft_lutpair49"; - attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair50"; - attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair50"; - attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair48"; - attribute SOFT_HLUTNM of \gcc0.gc0.count[6]_i_2\ : label is "soft_lutpair48"; - attribute SOFT_HLUTNM of ram_full_fb_i_i_7 : label is "soft_lutpair49"; -begin - Q(6 downto 0) <= \^q\(6 downto 0); -\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1 +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[10]\: unisim.vcomponents.FDRE generic map( - INIT => X"1" + INIT => '0' ) port map ( - I0 => p_12_out(0), - O => \plusOp__0\(0) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(4), + D => D(10), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(10), + R => SR(0) ); -\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2 +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[11]\: unisim.vcomponents.FDRE generic map( - INIT => X"6" + INIT => '0' ) port map ( - I0 => p_12_out(0), - I1 => p_12_out(1), - O => \plusOp__0\(1) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(4), + D => D(11), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(11), + R => SR(0) ); -\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3 +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[12]\: unisim.vcomponents.FDRE generic map( - INIT => X"78" + INIT => '0' ) port map ( - I0 => p_12_out(0), - I1 => p_12_out(1), - I2 => p_12_out(2), - O => \plusOp__0\(2) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(4), + D => D(12), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(12), + R => SR(0) ); -\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4 +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[13]\: unisim.vcomponents.FDRE generic map( - INIT => X"7F80" + INIT => '0' ) port map ( - I0 => p_12_out(1), - I1 => p_12_out(0), - I2 => p_12_out(2), - I3 => p_12_out(3), - O => \plusOp__0\(3) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(4), + D => D(13), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(13), + R => SR(0) ); -\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5 +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[14]\: unisim.vcomponents.FDRE generic map( - INIT => X"7FFF8000" + INIT => '0' ) port map ( - I0 => p_12_out(2), - I1 => p_12_out(0), - I2 => p_12_out(1), - I3 => p_12_out(3), - I4 => p_12_out(4), - O => \plusOp__0\(4) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(4), + D => D(14), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(14), + R => SR(0) ); -\gcc0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6 +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[15]\: unisim.vcomponents.FDRE generic map( - INIT => X"7FFFFFFF80000000" + INIT => '0' ) port map ( - I0 => p_12_out(3), - I1 => p_12_out(1), - I2 => p_12_out(0), - I3 => p_12_out(2), - I4 => p_12_out(4), - I5 => p_12_out(5), - O => \plusOp__0\(5) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(4), + D => D(15), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(15), + R => SR(0) ); -\gcc0.gc0.count[6]_i_1\: unisim.vcomponents.LUT3 +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[16]\: unisim.vcomponents.FDRE generic map( - INIT => X"78" + INIT => '0' ) port map ( - I0 => \gcc0.gc0.count[6]_i_2_n_0\, - I1 => p_12_out(5), - I2 => p_12_out(6), - O => \plusOp__0\(6) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(4), + D => D(16), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(16), + R => SR(0) ); -\gcc0.gc0.count[6]_i_2\: unisim.vcomponents.LUT5 +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[17]\: unisim.vcomponents.FDRE generic map( - INIT => X"80000000" + INIT => '0' ) port map ( - I0 => p_12_out(4), - I1 => p_12_out(2), - I2 => p_12_out(0), - I3 => p_12_out(1), - I4 => p_12_out(3), - O => \gcc0.gc0.count[6]_i_2_n_0\ + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(4), + D => D(17), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(17), + R => SR(0) ); -\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => E(0), - D => p_12_out(0), - Q => \^q\(0), - R => sig_stream_rst + CE => mm2s_axi2ip_wrce(4), + D => D(18), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(18), + R => SR(0) ); -\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => E(0), - D => p_12_out(1), - Q => \^q\(1), - R => sig_stream_rst + CE => mm2s_axi2ip_wrce(4), + D => D(19), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(19), + R => SR(0) ); -\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => E(0), - D => p_12_out(2), - Q => \^q\(2), - R => sig_stream_rst + CE => mm2s_axi2ip_wrce(4), + D => D(1), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(1), + R => SR(0) ); -\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => E(0), - D => p_12_out(3), - Q => \^q\(3), - R => sig_stream_rst + CE => mm2s_axi2ip_wrce(4), + D => D(20), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(20), + R => SR(0) ); -\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => E(0), - D => p_12_out(4), - Q => \^q\(4), - R => sig_stream_rst + CE => mm2s_axi2ip_wrce(4), + D => D(21), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(21), + R => SR(0) ); -\gcc0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => E(0), - D => p_12_out(5), - Q => \^q\(5), - R => sig_stream_rst + CE => mm2s_axi2ip_wrce(4), + D => D(22), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(22), + R => SR(0) ); -\gcc0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => E(0), - D => p_12_out(6), - Q => \^q\(6), - R => sig_stream_rst + CE => mm2s_axi2ip_wrce(4), + D => D(23), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(23), + R => SR(0) ); -\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDSE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[24]\: unisim.vcomponents.FDRE generic map( - INIT => '1' + INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => E(0), - D => \plusOp__0\(0), - Q => p_12_out(0), - S => sig_stream_rst + CE => mm2s_axi2ip_wrce(4), + D => D(24), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(24), + R => SR(0) ); -\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => E(0), - D => \plusOp__0\(1), - Q => p_12_out(1), - R => sig_stream_rst + CE => mm2s_axi2ip_wrce(4), + D => D(25), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(25), + R => SR(0) ); -\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => E(0), - D => \plusOp__0\(2), - Q => p_12_out(2), - R => sig_stream_rst + CE => mm2s_axi2ip_wrce(4), + D => D(26), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(26), + R => SR(0) ); -\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => E(0), - D => \plusOp__0\(3), - Q => p_12_out(3), - R => sig_stream_rst + CE => mm2s_axi2ip_wrce(4), + D => D(27), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(27), + R => SR(0) ); -\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => E(0), - D => \plusOp__0\(4), - Q => p_12_out(4), - R => sig_stream_rst + CE => mm2s_axi2ip_wrce(4), + D => D(28), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(28), + R => SR(0) ); -\gcc0.gc0.count_reg[5]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => E(0), - D => \plusOp__0\(5), - Q => p_12_out(5), - R => sig_stream_rst + CE => mm2s_axi2ip_wrce(4), + D => D(29), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(29), + R => SR(0) ); -\gcc0.gc0.count_reg[6]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => E(0), - D => \plusOp__0\(6), - Q => p_12_out(6), - R => sig_stream_rst - ); -ram_empty_fb_i_i_1: unisim.vcomponents.LUT5 - generic map( - INIT => X"0FFF0088" - ) - port map ( - I0 => \gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1\, - I1 => p_7_out, - I2 => \gwss.wsts/comp0\, - I3 => E(0), - I4 => ram_empty_fb_i_reg, - O => \ram_empty_i0__3\ - ); -ram_empty_fb_i_i_2: unisim.vcomponents.LUT6 - generic map( - INIT => X"1001000000001001" - ) - port map ( - I0 => ram_empty_fb_i_i_3_n_0, - I1 => ram_empty_fb_i_i_4_n_0, - I2 => \^q\(3), - I3 => \gc1.count_d1_reg[6]\(3), - I4 => \^q\(2), - I5 => \gc1.count_d1_reg[6]\(2), - O => \gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1\ + CE => mm2s_axi2ip_wrce(4), + D => D(2), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(2), + R => SR(0) ); -ram_empty_fb_i_i_3: unisim.vcomponents.LUT6 +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[30]\: unisim.vcomponents.FDRE generic map( - INIT => X"6FF6FFFFFFFF6FF6" + INIT => '0' ) port map ( - I0 => \^q\(5), - I1 => \gc1.count_d1_reg[6]\(5), - I2 => \gc1.count_d1_reg[6]\(4), - I3 => \^q\(4), - I4 => \gc1.count_d1_reg[6]\(6), - I5 => \^q\(6), - O => ram_empty_fb_i_i_3_n_0 + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(4), + D => D(30), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(30), + R => SR(0) ); -ram_empty_fb_i_i_4: unisim.vcomponents.LUT4 +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\: unisim.vcomponents.FDRE generic map( - INIT => X"6FF6" + INIT => '0' ) port map ( - I0 => \^q\(1), - I1 => \gc1.count_d1_reg[6]\(1), - I2 => \^q\(0), - I3 => \gc1.count_d1_reg[6]\(0), - O => ram_empty_fb_i_i_4_n_0 + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(4), + D => D(31), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(31), + R => SR(0) ); -ram_full_fb_i_i_1: unisim.vcomponents.LUT5 +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[3]\: unisim.vcomponents.FDRE generic map( - INIT => X"5500FFC0" + INIT => '0' ) port map ( - I0 => \gwss.wsts/comp0\, - I1 => E(0), - I2 => \gwss.wsts/comp1\, - I3 => \out\, - I4 => p_7_out, - O => ram_full_i_reg + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(4), + D => D(3), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(3), + R => SR(0) ); -ram_full_fb_i_i_2: unisim.vcomponents.LUT6 +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[4]\: unisim.vcomponents.FDRE generic map( - INIT => X"1001000000001001" + INIT => '0' ) port map ( - I0 => ram_full_fb_i_i_4_n_0, - I1 => ram_full_fb_i_i_5_n_0, - I2 => \^q\(3), - I3 => \gc1.count_d2_reg[6]\(3), - I4 => \^q\(2), - I5 => \gc1.count_d2_reg[6]\(2), - O => \gwss.wsts/comp0\ + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(4), + D => D(4), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(4), + R => SR(0) ); -ram_full_fb_i_i_3: unisim.vcomponents.LUT6 +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[5]\: unisim.vcomponents.FDRE generic map( - INIT => X"1001000000001001" + INIT => '0' ) port map ( - I0 => ram_full_fb_i_i_6_n_0, - I1 => ram_full_fb_i_i_7_n_0, - I2 => p_12_out(3), - I3 => \gc1.count_d2_reg[6]\(3), - I4 => p_12_out(2), - I5 => \gc1.count_d2_reg[6]\(2), - O => \gwss.wsts/comp1\ + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(4), + D => D(5), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(5), + R => SR(0) ); -ram_full_fb_i_i_4: unisim.vcomponents.LUT6 +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[6]\: unisim.vcomponents.FDRE generic map( - INIT => X"6FF6FFFFFFFF6FF6" + INIT => '0' ) port map ( - I0 => \^q\(5), - I1 => \gc1.count_d2_reg[6]\(5), - I2 => \gc1.count_d2_reg[6]\(4), - I3 => \^q\(4), - I4 => \gc1.count_d2_reg[6]\(6), - I5 => \^q\(6), - O => ram_full_fb_i_i_4_n_0 + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(4), + D => D(6), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(6), + R => SR(0) ); -ram_full_fb_i_i_5: unisim.vcomponents.LUT4 +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[7]\: unisim.vcomponents.FDRE generic map( - INIT => X"6FF6" + INIT => '0' ) port map ( - I0 => \^q\(1), - I1 => \gc1.count_d2_reg[6]\(1), - I2 => \^q\(0), - I3 => \gc1.count_d2_reg[6]\(0), - O => ram_full_fb_i_i_5_n_0 + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(4), + D => D(7), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(7), + R => SR(0) ); -ram_full_fb_i_i_6: unisim.vcomponents.LUT6 +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[8]\: unisim.vcomponents.FDRE generic map( - INIT => X"6FF6FFFFFFFF6FF6" + INIT => '0' ) port map ( - I0 => p_12_out(5), - I1 => \gc1.count_d2_reg[6]\(5), - I2 => \gc1.count_d2_reg[6]\(4), - I3 => p_12_out(4), - I4 => \gc1.count_d2_reg[6]\(6), - I5 => p_12_out(6), - O => ram_full_fb_i_i_6_n_0 + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(4), + D => D(8), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(8), + R => SR(0) ); -ram_full_fb_i_i_7: unisim.vcomponents.LUT4 +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[9]\: unisim.vcomponents.FDRE generic map( - INIT => X"6FF6" + INIT => '0' ) port map ( - I0 => p_12_out(1), - I1 => \gc1.count_d2_reg[6]\(1), - I2 => p_12_out(0), - I3 => \gc1.count_d2_reg[6]\(0), - O => ram_full_fb_i_i_7_n_0 + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(4), + D => D(9), + Q => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(9), + R => SR(0) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_wr_status_flags_ss is - port ( - \out\ : out STD_LOGIC; - \gcc0.gc0.count_d1_reg[6]\ : out STD_LOGIC; - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - sig_stream_rst : in STD_LOGIC; - ram_full_fb_i_reg_0 : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - \mm2s_strm_wvalid0__1\ : in STD_LOGIC; - m_axi_mm2s_rvalid : in STD_LOGIC; - \sig_advance_pipe9_out__1\ : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_wr_status_flags_ss : entity is "wr_status_flags_ss"; -end Arty_Z7_20_axi_vdma_0_0_wr_status_flags_ss; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_wr_status_flags_ss is - signal ram_afull_fb : STD_LOGIC; - attribute DONT_TOUCH : boolean; - attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true; - signal ram_afull_i : STD_LOGIC; - attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true; - signal ram_full_fb_i : STD_LOGIC; - attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true; - signal ram_full_i : STD_LOGIC; - attribute DONT_TOUCH of ram_full_i : signal is std.standard.true; - attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true; - attribute KEEP : string; - attribute KEEP of ram_full_fb_i_reg : label is "yes"; - attribute equivalent_register_removal : string; - attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no"; - attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true; - attribute KEEP of ram_full_i_reg : label is "yes"; - attribute equivalent_register_removal of ram_full_i_reg : label is "no"; -begin - \gcc0.gc0.count_d1_reg[6]\ <= ram_full_i; - \out\ <= ram_full_fb_i; -\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_2\: unisim.vcomponents.LUT5 +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => X"00005444" + INIT => '0' ) port map ( - I0 => ram_full_i, - I1 => \mm2s_strm_wvalid0__1\, - I2 => m_axi_mm2s_rvalid, - I3 => \sig_advance_pipe9_out__1\, - I4 => ram_full_fb_i, - O => E(0) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(5), + D => D(0), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(0), + R => SR(0) ); -i_0: unisim.vcomponents.LUT1 +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[10]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => ram_afull_i + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(5), + D => D(10), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(10), + R => SR(0) ); -i_1: unisim.vcomponents.LUT1 +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[11]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => ram_afull_fb + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(5), + D => D(11), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(11), + R => SR(0) ); -ram_full_fb_i_reg: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => ram_full_fb_i_reg_0, - Q => ram_full_fb_i, - R => sig_stream_rst + CE => mm2s_axi2ip_wrce(5), + D => D(12), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(12), + R => SR(0) ); -ram_full_i_reg: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => ram_full_fb_i_reg_0, - Q => ram_full_i, - R => sig_stream_rst + CE => mm2s_axi2ip_wrce(5), + D => D(13), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(13), + R => SR(0) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_lite_if is - port ( - D : out STD_LOGIC_VECTOR ( 31 downto 0 ); - \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_lite_awready : out STD_LOGIC; - s_axi_lite_wready : out STD_LOGIC; - s_axi_lite_arready : out STD_LOGIC; - s_axi_lite_bvalid : out STD_LOGIC; - s_axi_lite_rvalid : out STD_LOGIC; - \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg\ : out STD_LOGIC; - \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[16]\ : out STD_LOGIC; - \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg\ : out STD_LOGIC; - mm2s_axi2ip_wrce : out STD_LOGIC_VECTOR ( 5 downto 0 ); - \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - in0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); - prmtr_updt_complete_i_reg : out STD_LOGIC; - ioc_irq_reg : out STD_LOGIC; - dly_irq_reg : out STD_LOGIC; - s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_lite_aclk : in STD_LOGIC; - prmry_reset2 : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - s_axi_lite_wvalid : in STD_LOGIC; - s_axi_lite_awvalid : in STD_LOGIC; - s_axi_lite_arvalid : in STD_LOGIC; - different_delay : in STD_LOGIC; - different_thresh : in STD_LOGIC; - prmry_resetn_i_reg : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[0]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[15]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[14]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[13]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[12]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[6]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[5]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[4]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[2]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[1]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[3]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[7]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[8]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[9]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[10]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[11]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); - s_axi_lite_resetn : in STD_LOGIC; - s_axi_lite_bready : in STD_LOGIC; - s_axi_lite_rready : in STD_LOGIC; - p_68_out : in STD_LOGIC_VECTOR ( 25 downto 0 ); - p_67_out : in STD_LOGIC; - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); - err_irq_reg : in STD_LOGIC; - dly_irq_reg_0 : in STD_LOGIC; - ioc_irq_reg_0 : in STD_LOGIC; - dma_decerr_reg : in STD_LOGIC; - dma_slverr_reg : in STD_LOGIC; - dma_interr_reg : in STD_LOGIC; - mm2s_ioc_irq_set : in STD_LOGIC; - mm2s_dly_irq_set : in STD_LOGIC; - s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 5 downto 0 ); - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 5 downto 0 ); - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_lite_if : entity is "axi_vdma_lite_if"; -end Arty_Z7_20_axi_vdma_0_0_axi_vdma_lite_if; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_lite_if is - signal \ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_3_n_0\ : STD_LOGIC; - signal \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[10]_i_1_n_0\ : STD_LOGIC; - signal \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[11]_i_1_n_0\ : STD_LOGIC; - signal \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[12]_i_1_n_0\ : STD_LOGIC; - signal \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[13]_i_1_n_0\ : STD_LOGIC; - signal \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[14]_i_1_n_0\ : STD_LOGIC; - signal \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[15]_i_1_n_0\ : STD_LOGIC; - signal \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[21]_i_1_n_0\ : STD_LOGIC; - signal \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[22]_i_1_n_0\ : STD_LOGIC; - signal \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[23]_i_1_n_0\ : STD_LOGIC; - signal \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[24]_i_1_n_0\ : STD_LOGIC; - signal \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[26]_i_1_n_0\ : STD_LOGIC; - signal \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[27]_i_1_n_0\ : STD_LOGIC; - signal \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_1_n_0\ : STD_LOGIC; - signal \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0\ : STD_LOGIC; - signal \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\ : STD_LOGIC; - signal \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_2_n_0\ : STD_LOGIC; - signal \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[5]_i_1_n_0\ : STD_LOGIC; - signal \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[7]_i_1_n_0\ : STD_LOGIC; - signal \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[8]_i_1_n_0\ : STD_LOGIC; - signal \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[9]_i_1_n_0\ : STD_LOGIC; - signal \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.prepare_wrce_pulse_lite_d6_reg_srl6_i_1_n_0\ : STD_LOGIC; - signal \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.rvalid_out_i_i_1_n_0\ : STD_LOGIC; - signal \GEN_NUM_FSTORES_1.reg_module_start_address1_i[31]_i_2_n_0\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I/I_DMA_REGISTER/threshold_is_zero\ : STD_LOGIC; - signal \addr_region_mm2s_rden_cmb__4\ : STD_LOGIC; - signal arvalid : STD_LOGIC; - signal awaddr : STD_LOGIC_VECTOR ( 7 downto 2 ); - signal awvalid : STD_LOGIC; - signal axi2ip_rdaddr_captured_mm2s_cdc_tig : STD_LOGIC_VECTOR ( 7 downto 2 ); - attribute async_reg : string; - attribute async_reg of axi2ip_rdaddr_captured_mm2s_cdc_tig : signal is "true"; - signal \axi2ip_rdaddr_captured_reg_n_0_[2]\ : STD_LOGIC; - signal \axi2ip_rdaddr_captured_reg_n_0_[3]\ : STD_LOGIC; - signal \axi2ip_rdaddr_captured_reg_n_0_[4]\ : STD_LOGIC; - signal \axi2ip_rdaddr_captured_reg_n_0_[5]\ : STD_LOGIC; - signal \axi2ip_rdaddr_captured_reg_n_0_[6]\ : STD_LOGIC; - signal \axi2ip_rdaddr_captured_reg_n_0_[7]\ : STD_LOGIC; - signal axi2ip_rdaddr_captured_s2mm_cdc_tig : STD_LOGIC_VECTOR ( 7 downto 2 ); - attribute async_reg of axi2ip_rdaddr_captured_s2mm_cdc_tig : signal is "true"; - signal axi2ip_wraddr_captured : STD_LOGIC_VECTOR ( 7 downto 2 ); - signal axi2ip_wraddr_captured_mm2s_cdc_tig : STD_LOGIC_VECTOR ( 7 downto 2 ); - attribute async_reg of axi2ip_wraddr_captured_mm2s_cdc_tig : signal is "true"; - signal axi2ip_wraddr_captured_s2mm_cdc_tig : STD_LOGIC_VECTOR ( 7 downto 2 ); - attribute async_reg of axi2ip_wraddr_captured_s2mm_cdc_tig : signal is "true"; - signal bvalid_out_i_i_1_n_0 : STD_LOGIC; - signal \dmacr_i[1]_i_2_n_0\ : STD_LOGIC; - signal ip2axi_rddata_captured : STD_LOGIC_VECTOR ( 30 downto 0 ); - signal ip2axi_rddata_captured_mm2s_cdc_tig : STD_LOGIC_VECTOR ( 31 downto 0 ); - attribute async_reg of ip2axi_rddata_captured_mm2s_cdc_tig : signal is "true"; - signal ip2axi_rddata_captured_s2mm_cdc_tig : STD_LOGIC_VECTOR ( 31 downto 0 ); - attribute async_reg of ip2axi_rddata_captured_s2mm_cdc_tig : signal is "true"; - signal ip2axi_rddata_int_inferred_i_33_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_34_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_35_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_36_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_37_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_38_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_39_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_40_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_41_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_42_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_43_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_44_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_45_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_46_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_47_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_48_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_49_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_50_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_51_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_52_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_53_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_54_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_55_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_56_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_57_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_58_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_59_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_60_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_61_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_62_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_63_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_64_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_66_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_68_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_70_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_72_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_79_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_81_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_83_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_86_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_88_n_0 : STD_LOGIC; - signal ip2axi_rddata_int_inferred_i_90_n_0 : STD_LOGIC; - signal lite_wr_addr_phase_finished_data_phase_started : STD_LOGIC; - signal lite_wr_addr_phase_finished_data_phase_started_i_1_n_0 : STD_LOGIC; - signal mm2s_axi2ip_wrdata_cdc_tig : STD_LOGIC_VECTOR ( 31 downto 0 ); - attribute async_reg of mm2s_axi2ip_wrdata_cdc_tig : signal is "true"; - signal mm2s_ip2axi_rddata_d1 : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal p_2_in : STD_LOGIC_VECTOR ( 5 downto 0 ); - signal prepare_wrce : STD_LOGIC; - signal prepare_wrce_d1 : STD_LOGIC; - signal prepare_wrce_pulse_lite_d6 : STD_LOGIC; - signal read_has_started_i : STD_LOGIC; - signal read_has_started_i_i_1_n_0 : STD_LOGIC; - signal s2mm_axi2ip_wrdata_cdc_tig : STD_LOGIC_VECTOR ( 31 downto 0 ); - attribute async_reg of s2mm_axi2ip_wrdata_cdc_tig : signal is "true"; - signal \^s_axi_lite_arready\ : STD_LOGIC; - signal \^s_axi_lite_awready\ : STD_LOGIC; - signal \^s_axi_lite_bvalid\ : STD_LOGIC; - signal \^s_axi_lite_rvalid\ : STD_LOGIC; - signal \^s_axi_lite_wready\ : STD_LOGIC; - signal sig_arvalid_arrived_d1 : STD_LOGIC; - signal sig_arvalid_arrived_d1_i_1_n_0 : STD_LOGIC; - signal sig_arvalid_arrived_d4 : STD_LOGIC; - signal \sig_arvalid_detected__0\ : STD_LOGIC; - signal sig_awvalid_arrived_d1 : STD_LOGIC; - signal sig_awvalid_arrived_d1_i_1_n_0 : STD_LOGIC; - signal \sig_awvalid_detected__0\ : STD_LOGIC; - signal wdata : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal write_has_started : STD_LOGIC; - signal write_has_started_i_1_n_0 : STD_LOGIC; - signal wvalid : STD_LOGIC; - attribute ASYNC_REG_boolean : boolean; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[2]\ : label is std.standard.true; - attribute KEEP : string; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[2]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[4]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[4]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[6]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[6]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[2]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[2]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[3]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[3]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[4]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[4]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[5]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[5]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[6]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[6]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7]\ : label is "yes"; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2\ : label is "soft_lutpair3"; - attribute SOFT_HLUTNM of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3\ : label is "soft_lutpair3"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[0]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[0]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[10]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[10]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[11]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[11]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[12]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[12]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[13]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[13]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[14]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[14]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[15]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[15]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[16]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[16]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[17]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[17]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[18]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[18]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[19]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[19]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[1]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[1]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[20]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[20]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[21]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[21]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[22]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[22]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[23]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[23]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[24]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[24]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[25]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[25]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[26]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[26]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[27]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[27]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[28]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[28]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[29]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[29]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[2]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[2]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[30]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[30]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[31]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[31]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[3]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[3]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[4]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[4]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[5]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[5]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[6]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[6]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[7]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[7]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[8]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[8]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[9]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[9]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[0]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[0]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[10]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[10]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[11]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[11]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[14]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[14]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[15]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[15]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[16]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[16]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[17]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[17]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[19]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[19]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[1]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[1]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[20]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[20]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[21]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[21]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[22]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[22]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[23]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[23]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[24]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[24]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[25]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[25]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[26]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[26]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[27]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[27]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[28]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[28]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[29]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[29]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[2]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[2]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[30]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[30]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[31]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[31]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[3]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[3]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[5]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[5]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[6]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[6]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[7]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[7]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[8]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[8]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[9]\ : label is std.standard.true; - attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[9]\ : label is "yes"; - attribute SOFT_HLUTNM of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.prepare_wrce_d1_i_1\ : label is "soft_lutpair5"; - attribute srl_name : string; - attribute srl_name of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.prepare_wrce_pulse_lite_d6_reg_srl6\ : label is "U0/\AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.prepare_wrce_pulse_lite_d6_reg_srl6 "; - attribute SOFT_HLUTNM of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.prepare_wrce_pulse_lite_d6_reg_srl6_i_1\ : label is "soft_lutpair5"; - attribute srl_name of \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.sig_arvalid_arrived_d4_reg_srl3\ : label is "U0/\AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.sig_arvalid_arrived_d4_reg_srl3 "; - attribute SOFT_HLUTNM of sig_arvalid_arrived_d1_i_1 : label is "soft_lutpair4"; - attribute SOFT_HLUTNM of sig_awvalid_arrived_d1_i_1 : label is "soft_lutpair4"; -begin - D(31 downto 0) <= mm2s_axi2ip_wrdata_cdc_tig(31 downto 0); - \out\(1 downto 0) <= axi2ip_rdaddr_captured_mm2s_cdc_tig(3 downto 2); - s_axi_lite_arready <= \^s_axi_lite_arready\; - s_axi_lite_awready <= \^s_axi_lite_awready\; - s_axi_lite_bvalid <= \^s_axi_lite_bvalid\; - s_axi_lite_rvalid <= \^s_axi_lite_rvalid\; - s_axi_lite_wready <= \^s_axi_lite_wready\; -\ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_2\: unisim.vcomponents.LUT5 +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[14]\: unisim.vcomponents.FDRE generic map( - INIT => X"00000001" + INIT => '0' ) port map ( - I0 => mm2s_axi2ip_wrdata_cdc_tig(21), - I1 => mm2s_axi2ip_wrdata_cdc_tig(20), - I2 => mm2s_axi2ip_wrdata_cdc_tig(22), - I3 => mm2s_axi2ip_wrdata_cdc_tig(23), - I4 => \ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_3_n_0\, - O => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I/I_DMA_REGISTER/threshold_is_zero\ + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(5), + D => D(14), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(14), + R => SR(0) ); -\ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_3\: unisim.vcomponents.LUT4 +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[15]\: unisim.vcomponents.FDRE generic map( - INIT => X"FFFE" + INIT => '0' ) port map ( - I0 => mm2s_axi2ip_wrdata_cdc_tig(18), - I1 => mm2s_axi2ip_wrdata_cdc_tig(19), - I2 => mm2s_axi2ip_wrdata_cdc_tig(16), - I3 => mm2s_axi2ip_wrdata_cdc_tig(17), - O => \ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_3_n_0\ - ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.LITE_WVALID_MM2S_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized6\ - port map ( - D(1 downto 0) => mm2s_axi2ip_wrdata_cdc_tig(13 downto 12), - \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg\ => \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg\, - \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[16]\ => \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[16]\, - \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]\(0) => \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]\(0), - \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg\ => \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[4]\ => \GEN_NUM_FSTORES_1.reg_module_start_address1_i[31]_i_2_n_0\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[6]\ => \dmacr_i[1]_i_2_n_0\, - SR(0) => SR(0), - different_delay => different_delay, - different_thresh => different_thresh, - dly_irq_reg => dly_irq_reg, - dly_irq_reg_0 => dly_irq_reg_0, - ioc_irq_reg => ioc_irq_reg, - ioc_irq_reg_0 => ioc_irq_reg_0, - lite_wr_addr_phase_finished_data_phase_started => lite_wr_addr_phase_finished_data_phase_started, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - mm2s_axi2ip_wrce(5 downto 0) => mm2s_axi2ip_wrce(5 downto 0), - mm2s_dly_irq_set => mm2s_dly_irq_set, - mm2s_ioc_irq_set => mm2s_ioc_irq_set, - \out\(5 downto 0) => axi2ip_wraddr_captured_mm2s_cdc_tig(7 downto 2), - p_68_out(0) => p_68_out(0), - prepare_wrce_d1 => prepare_wrce_d1, - prmry_reset2 => prmry_reset2, - prmry_resetn_i_reg => prmry_resetn_i_reg, - prmtr_updt_complete_i_reg => prmtr_updt_complete_i_reg, - s_axi_lite_aclk => s_axi_lite_aclk, - threshold_is_zero => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I/I_DMA_REGISTER/threshold_is_zero\, - wvalid => wvalid + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(5), + D => D(15), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(15), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.arready_out_i_reg\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => sig_arvalid_arrived_d4, - Q => \^s_axi_lite_arready\, + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(5), + D => D(16), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(16), R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[2]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => \axi2ip_rdaddr_captured_reg_n_0_[2]\, - Q => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - R => '0' + CE => mm2s_axi2ip_wrce(5), + D => D(17), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(17), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => \axi2ip_rdaddr_captured_reg_n_0_[3]\, - Q => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - R => '0' + CE => mm2s_axi2ip_wrce(5), + D => D(18), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(18), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[4]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => \axi2ip_rdaddr_captured_reg_n_0_[4]\, - Q => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - R => '0' + CE => mm2s_axi2ip_wrce(5), + D => D(19), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(19), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => \axi2ip_rdaddr_captured_reg_n_0_[5]\, - Q => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - R => '0' + CE => mm2s_axi2ip_wrce(5), + D => D(1), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(1), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[6]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => \axi2ip_rdaddr_captured_reg_n_0_[6]\, - Q => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - R => '0' + CE => mm2s_axi2ip_wrce(5), + D => D(20), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(20), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => \axi2ip_rdaddr_captured_reg_n_0_[7]\, - Q => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - R => '0' + CE => mm2s_axi2ip_wrce(5), + D => D(21), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(21), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[2]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => axi2ip_wraddr_captured(2), - Q => axi2ip_wraddr_captured_mm2s_cdc_tig(2), - R => '0' + CE => mm2s_axi2ip_wrce(5), + D => D(22), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(22), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[3]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => axi2ip_wraddr_captured(3), - Q => axi2ip_wraddr_captured_mm2s_cdc_tig(3), - R => '0' + CE => mm2s_axi2ip_wrce(5), + D => D(23), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(23), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[4]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => axi2ip_wraddr_captured(4), - Q => axi2ip_wraddr_captured_mm2s_cdc_tig(4), - R => '0' + CE => mm2s_axi2ip_wrce(5), + D => D(24), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(24), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[5]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => axi2ip_wraddr_captured(5), - Q => axi2ip_wraddr_captured_mm2s_cdc_tig(5), - R => '0' + CE => mm2s_axi2ip_wrce(5), + D => D(25), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(25), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[6]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => axi2ip_wraddr_captured(6), - Q => axi2ip_wraddr_captured_mm2s_cdc_tig(6), - R => '0' + CE => mm2s_axi2ip_wrce(5), + D => D(26), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(26), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => axi2ip_wraddr_captured(7), - Q => axi2ip_wraddr_captured_mm2s_cdc_tig(7), - R => '0' + CE => mm2s_axi2ip_wrce(5), + D => D(27), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(27), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[0]_i_1\: unisim.vcomponents.LUT6 +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[28]\: unisim.vcomponents.FDRE generic map( - INIT => X"04FF040004000400" + INIT => '0' ) port map ( - I0 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0\, - I1 => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(0), - I2 => \axi2ip_rdaddr_captured_reg_n_0_[2]\, - I3 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\, - I4 => \addr_region_mm2s_rden_cmb__4\, - I5 => ip2axi_rddata_captured_mm2s_cdc_tig(0), - O => ip2axi_rddata_captured(0) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(5), + D => D(28), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(28), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[10]_i_1\: unisim.vcomponents.LUT5 +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[29]\: unisim.vcomponents.FDRE generic map( - INIT => X"000AA80A" + INIT => '0' ) port map ( - I0 => ip2axi_rddata_captured_mm2s_cdc_tig(10), - I1 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, - I2 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, - I3 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, - I4 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[10]_i_1_n_0\ + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(5), + D => D(29), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(29), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[11]_i_1\: unisim.vcomponents.LUT5 +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[2]\: unisim.vcomponents.FDRE generic map( - INIT => X"000AA80A" + INIT => '0' ) port map ( - I0 => ip2axi_rddata_captured_mm2s_cdc_tig(11), - I1 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, - I2 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, - I3 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, - I4 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[11]_i_1_n_0\ + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(5), + D => D(2), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(2), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[12]_i_1\: unisim.vcomponents.LUT5 +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[30]\: unisim.vcomponents.FDRE generic map( - INIT => X"000AA80A" + INIT => '0' ) port map ( - I0 => ip2axi_rddata_captured_mm2s_cdc_tig(12), - I1 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, - I2 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, - I3 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, - I4 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[12]_i_1_n_0\ + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(5), + D => D(30), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(30), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[13]_i_1\: unisim.vcomponents.LUT5 +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\: unisim.vcomponents.FDRE generic map( - INIT => X"000AA80A" + INIT => '0' ) port map ( - I0 => ip2axi_rddata_captured_mm2s_cdc_tig(13), - I1 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, - I2 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, - I3 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, - I4 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[13]_i_1_n_0\ + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(5), + D => D(31), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(31), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[14]_i_1\: unisim.vcomponents.LUT5 +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[3]\: unisim.vcomponents.FDRE generic map( - INIT => X"000AA80A" + INIT => '0' ) port map ( - I0 => ip2axi_rddata_captured_mm2s_cdc_tig(14), - I1 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, - I2 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, - I3 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, - I4 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[14]_i_1_n_0\ + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(5), + D => D(3), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(3), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[15]_i_1\: unisim.vcomponents.LUT5 +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[4]\: unisim.vcomponents.FDRE generic map( - INIT => X"000AA80A" + INIT => '0' ) port map ( - I0 => ip2axi_rddata_captured_mm2s_cdc_tig(15), - I1 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, - I2 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, - I3 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, - I4 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[15]_i_1_n_0\ + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(5), + D => D(4), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(4), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[16]_i_1\: unisim.vcomponents.LUT6 +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[5]\: unisim.vcomponents.FDRE generic map( - INIT => X"04FF040004000400" + INIT => '0' ) port map ( - I0 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0\, - I1 => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\(0), - I2 => \axi2ip_rdaddr_captured_reg_n_0_[2]\, - I3 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\, - I4 => \addr_region_mm2s_rden_cmb__4\, - I5 => ip2axi_rddata_captured_mm2s_cdc_tig(16), - O => ip2axi_rddata_captured(16) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(5), + D => D(5), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(5), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[17]_i_1\: unisim.vcomponents.LUT6 +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[6]\: unisim.vcomponents.FDRE generic map( - INIT => X"04FF040004000400" + INIT => '0' ) port map ( - I0 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0\, - I1 => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\(1), - I2 => \axi2ip_rdaddr_captured_reg_n_0_[2]\, - I3 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\, - I4 => \addr_region_mm2s_rden_cmb__4\, - I5 => ip2axi_rddata_captured_mm2s_cdc_tig(17), - O => ip2axi_rddata_captured(17) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(5), + D => D(6), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(6), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[18]_i_1\: unisim.vcomponents.LUT6 +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[7]\: unisim.vcomponents.FDRE generic map( - INIT => X"04FF040004000400" + INIT => '0' ) port map ( - I0 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0\, - I1 => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\(2), - I2 => \axi2ip_rdaddr_captured_reg_n_0_[2]\, - I3 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\, - I4 => \addr_region_mm2s_rden_cmb__4\, - I5 => ip2axi_rddata_captured_mm2s_cdc_tig(18), - O => ip2axi_rddata_captured(18) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(5), + D => D(7), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(7), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[19]_i_1\: unisim.vcomponents.LUT6 +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[8]\: unisim.vcomponents.FDRE generic map( - INIT => X"04FF040004000400" + INIT => '0' ) port map ( - I0 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0\, - I1 => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\(3), - I2 => \axi2ip_rdaddr_captured_reg_n_0_[2]\, - I3 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\, - I4 => \addr_region_mm2s_rden_cmb__4\, - I5 => ip2axi_rddata_captured_mm2s_cdc_tig(19), - O => ip2axi_rddata_captured(19) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(5), + D => D(8), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(8), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[1]_i_1\: unisim.vcomponents.LUT6 +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[9]\: unisim.vcomponents.FDRE generic map( - INIT => X"04FF040004000400" + INIT => '0' ) port map ( - I0 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0\, - I1 => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(1), - I2 => \axi2ip_rdaddr_captured_reg_n_0_[2]\, - I3 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\, - I4 => \addr_region_mm2s_rden_cmb__4\, - I5 => ip2axi_rddata_captured_mm2s_cdc_tig(1), - O => ip2axi_rddata_captured(1) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(5), + D => D(9), + Q => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(9), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[20]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"04FF040004000400" - ) - port map ( - I0 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0\, - I1 => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\(4), - I2 => \axi2ip_rdaddr_captured_reg_n_0_[2]\, - I3 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\, - I4 => \addr_region_mm2s_rden_cmb__4\, - I5 => ip2axi_rddata_captured_mm2s_cdc_tig(20), - O => ip2axi_rddata_captured(20) +\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(2), + D => D(0), + Q => \^stride_vid_reg[15]\(0), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[21]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"000AA80A" - ) - port map ( - I0 => ip2axi_rddata_captured_mm2s_cdc_tig(21), - I1 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, - I2 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, - I3 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, - I4 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[21]_i_1_n_0\ +\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(2), + D => D(10), + Q => \^stride_vid_reg[15]\(10), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[22]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"000AA80A" - ) - port map ( - I0 => ip2axi_rddata_captured_mm2s_cdc_tig(22), - I1 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, - I2 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, - I3 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, - I4 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[22]_i_1_n_0\ +\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(2), + D => D(11), + Q => \^stride_vid_reg[15]\(11), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[23]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"000AA80A" - ) - port map ( - I0 => ip2axi_rddata_captured_mm2s_cdc_tig(23), - I1 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, - I2 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, - I3 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, - I4 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[23]_i_1_n_0\ +\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(2), + D => D(12), + Q => \^stride_vid_reg[15]\(12), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[24]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"000AA80A" - ) - port map ( - I0 => ip2axi_rddata_captured_mm2s_cdc_tig(24), - I1 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, - I2 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, - I3 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, - I4 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[24]_i_1_n_0\ +\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(2), + D => D(13), + Q => \^stride_vid_reg[15]\(13), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[25]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"2F202020" - ) - port map ( - I0 => \axi2ip_rdaddr_captured_reg_n_0_[2]\, - I1 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0\, - I2 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\, - I3 => \addr_region_mm2s_rden_cmb__4\, - I4 => ip2axi_rddata_captured_mm2s_cdc_tig(25), - O => ip2axi_rddata_captured(25) +\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(2), + D => D(14), + Q => \^stride_vid_reg[15]\(14), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[26]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"000AA80A" - ) - port map ( - I0 => ip2axi_rddata_captured_mm2s_cdc_tig(26), - I1 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, - I2 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, - I3 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, - I4 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[26]_i_1_n_0\ +\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(2), + D => D(15), + Q => \^stride_vid_reg[15]\(15), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[27]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"000AA80A" - ) - port map ( - I0 => ip2axi_rddata_captured_mm2s_cdc_tig(27), - I1 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, - I2 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, - I3 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, - I4 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[27]_i_1_n_0\ +\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(2), + D => D(1), + Q => \^stride_vid_reg[15]\(1), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"000AA80A" - ) - port map ( - I0 => ip2axi_rddata_captured_mm2s_cdc_tig(28), - I1 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, - I2 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, - I3 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, - I4 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_1_n_0\ +\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(2), + D => D(2), + Q => \^stride_vid_reg[15]\(2), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[29]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"2F202020" - ) - port map ( - I0 => \axi2ip_rdaddr_captured_reg_n_0_[2]\, - I1 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0\, - I2 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\, - I3 => \addr_region_mm2s_rden_cmb__4\, - I4 => ip2axi_rddata_captured_mm2s_cdc_tig(29), - O => ip2axi_rddata_captured(29) +\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(2), + D => D(3), + Q => \^stride_vid_reg[15]\(3), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[2]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"04FF040004000400" - ) - port map ( - I0 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0\, - I1 => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(2), - I2 => \axi2ip_rdaddr_captured_reg_n_0_[2]\, - I3 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\, - I4 => \addr_region_mm2s_rden_cmb__4\, - I5 => ip2axi_rddata_captured_mm2s_cdc_tig(2), - O => ip2axi_rddata_captured(2) +\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(2), + D => D(4), + Q => \^stride_vid_reg[15]\(4), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"2F202020" - ) - port map ( - I0 => \axi2ip_rdaddr_captured_reg_n_0_[2]\, - I1 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0\, - I2 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\, - I3 => \addr_region_mm2s_rden_cmb__4\, - I4 => ip2axi_rddata_captured_mm2s_cdc_tig(30), - O => ip2axi_rddata_captured(30) +\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(2), + D => D(5), + Q => \^stride_vid_reg[15]\(5), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FEFFFFFF" - ) - port map ( - I0 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, - I1 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, - I2 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, - I3 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, - I4 => \axi2ip_rdaddr_captured_reg_n_0_[3]\, - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0\ +\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(2), + D => D(6), + Q => \^stride_vid_reg[15]\(6), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3\: unisim.vcomponents.LUT4 - generic map( - INIT => X"4743" - ) - port map ( - I0 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, - I1 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, - I2 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, - I3 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, - O => \addr_region_mm2s_rden_cmb__4\ +\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(2), + D => D(7), + Q => \^stride_vid_reg[15]\(7), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"8004" - ) - port map ( - I0 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, - I1 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, - I2 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, - I3 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\ +\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(2), + D => D(8), + Q => \^stride_vid_reg[15]\(8), + R => SR(0) + ); +\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(2), + D => D(9), + Q => \^stride_vid_reg[15]\(9), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_2\: unisim.vcomponents.LUT5 +\VIDEO_REG_I/GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"000AA80A" + INIT => X"00302020" ) port map ( - I0 => ip2axi_rddata_captured_mm2s_cdc_tig(31), - I1 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, - I2 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, - I3 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, - I4 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_2_n_0\ + I0 => p_66_out, + I1 => halted_reg, + I2 => prmry_resetn_i_reg, + I3 => p_24_out, + I4 => prmtr_update_complete, + O => \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg\ ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[3]_i_1\: unisim.vcomponents.LUT6 +ip2axi_rddata_int_inferred_i_17: unisim.vcomponents.LUT4 generic map( - INIT => X"04FF040004000400" + INIT => X"FFEA" ) port map ( - I0 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0\, - I1 => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(3), - I2 => \axi2ip_rdaddr_captured_reg_n_0_[2]\, - I3 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\, - I4 => \addr_region_mm2s_rden_cmb__4\, - I5 => ip2axi_rddata_captured_mm2s_cdc_tig(3), - O => ip2axi_rddata_captured(3) + I0 => ip2axi_rddata_int_inferred_i_51_n_0, + I1 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_1\, + I2 => \GEN_NOSYNCEN_BIT.dmacr_i_reg[15]\, + I3 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]_0\, + O => in0(2) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[4]_i_1\: unisim.vcomponents.LUT6 +ip2axi_rddata_int_inferred_i_30: unisim.vcomponents.LUT5 generic map( - INIT => X"0EFF0E000E000E00" + INIT => X"FFFFF888" ) port map ( - I0 => \axi2ip_rdaddr_captured_reg_n_0_[2]\, - I1 => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(4), - I2 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0\, - I3 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\, - I4 => \addr_region_mm2s_rden_cmb__4\, - I5 => ip2axi_rddata_captured_mm2s_cdc_tig(4), - O => ip2axi_rddata_captured(4) + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]\, + I1 => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(2), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_0\, + I3 => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(2), + I4 => ip2axi_rddata_int_inferred_i_74_n_0, + O => in0(1) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[5]_i_1\: unisim.vcomponents.LUT5 +ip2axi_rddata_int_inferred_i_31: unisim.vcomponents.LUT5 generic map( - INIT => X"000AA80A" + INIT => X"FFFFF888" ) port map ( - I0 => ip2axi_rddata_captured_mm2s_cdc_tig(5), - I1 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, - I2 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, - I3 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, - I4 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[5]_i_1_n_0\ + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]\, + I1 => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(1), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_0\, + I3 => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(1), + I4 => ip2axi_rddata_int_inferred_i_75_n_0, + O => in0(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[6]_i_1\: unisim.vcomponents.LUT5 +ip2axi_rddata_int_inferred_i_51: unisim.vcomponents.LUT4 generic map( - INIT => X"2F202020" + INIT => X"F888" ) port map ( - I0 => \axi2ip_rdaddr_captured_reg_n_0_[2]\, - I1 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0\, - I2 => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\, - I3 => \addr_region_mm2s_rden_cmb__4\, - I4 => ip2axi_rddata_captured_mm2s_cdc_tig(6), - O => ip2axi_rddata_captured(6) + I0 => \^gen_start_addr_reg[2].start_address_vid_reg[2][31]\(15), + I1 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_0\, + I2 => \^gen_start_addr_reg[1].start_address_vid_reg[1][31]\(15), + I3 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]\, + O => ip2axi_rddata_int_inferred_i_51_n_0 ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[7]_i_1\: unisim.vcomponents.LUT5 +ip2axi_rddata_int_inferred_i_60: unisim.vcomponents.LUT6 generic map( - INIT => X"000AA80A" + INIT => X"CAFFCAF0CA0FCA00" ) port map ( - I0 => ip2axi_rddata_captured_mm2s_cdc_tig(7), - I1 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, - I2 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, - I3 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, - I4 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[7]_i_1_n_0\ + I0 => \^hsize_vid_reg[15]\(12), + I1 => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(12), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1), + I3 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(0), + I4 => \^vsize_vid_reg[12]\(12), + I5 => \^stride_vid_reg[15]\(12), + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]\ ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[8]_i_1\: unisim.vcomponents.LUT5 +ip2axi_rddata_int_inferred_i_61: unisim.vcomponents.LUT6 generic map( - INIT => X"000AA80A" + INIT => X"CAFFCAF0CA0FCA00" ) port map ( - I0 => ip2axi_rddata_captured_mm2s_cdc_tig(8), - I1 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, - I2 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, - I3 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, - I4 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[8]_i_1_n_0\ + I0 => \^hsize_vid_reg[15]\(11), + I1 => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(11), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1), + I3 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(0), + I4 => \^vsize_vid_reg[12]\(11), + I5 => \^stride_vid_reg[15]\(11), + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]\ ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[9]_i_1\: unisim.vcomponents.LUT5 +ip2axi_rddata_int_inferred_i_63: unisim.vcomponents.LUT6 generic map( - INIT => X"000AA80A" + INIT => X"CAFFCAF0CA0FCA00" ) port map ( - I0 => ip2axi_rddata_captured_mm2s_cdc_tig(9), - I1 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, - I2 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, - I3 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, - I4 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[9]_i_1_n_0\ + I0 => \^hsize_vid_reg[15]\(10), + I1 => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(10), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1), + I3 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(0), + I4 => \^vsize_vid_reg[12]\(10), + I5 => \^stride_vid_reg[15]\(10), + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10]\ ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[0]\: unisim.vcomponents.FDRE +ip2axi_rddata_int_inferred_i_64: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"CAFFCAF0CA0FCA00" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => ip2axi_rddata_captured(0), - Q => s_axi_lite_rdata(0), - R => '0' + I0 => \^hsize_vid_reg[15]\(9), + I1 => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(9), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1), + I3 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(0), + I4 => \^vsize_vid_reg[12]\(9), + I5 => \^stride_vid_reg[15]\(9), + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9]\ ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[10]\: unisim.vcomponents.FDRE +ip2axi_rddata_int_inferred_i_65: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"CAFFCAF0CA0FCA00" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[10]_i_1_n_0\, - Q => s_axi_lite_rdata(10), - R => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\ + I0 => \^hsize_vid_reg[15]\(8), + I1 => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(8), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1), + I3 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(0), + I4 => \^vsize_vid_reg[12]\(8), + I5 => \^stride_vid_reg[15]\(8), + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8]\ ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[11]\: unisim.vcomponents.FDRE +ip2axi_rddata_int_inferred_i_66: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"CAFFCAF0CA0FCA00" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[11]_i_1_n_0\, - Q => s_axi_lite_rdata(11), - R => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\ + I0 => \^hsize_vid_reg[15]\(7), + I1 => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(7), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1), + I3 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(0), + I4 => \^vsize_vid_reg[12]\(7), + I5 => \^stride_vid_reg[15]\(7), + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7]\ ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[12]\: unisim.vcomponents.FDRE +ip2axi_rddata_int_inferred_i_68: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"CAFFCAF0CA0FCA00" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[12]_i_1_n_0\, - Q => s_axi_lite_rdata(12), - R => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\ + I0 => \^hsize_vid_reg[15]\(6), + I1 => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(6), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1), + I3 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(0), + I4 => \^vsize_vid_reg[12]\(6), + I5 => \^stride_vid_reg[15]\(6), + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6]\ ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[13]\: unisim.vcomponents.FDRE +ip2axi_rddata_int_inferred_i_70: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"CAFFCAF0CA0FCA00" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[13]_i_1_n_0\, - Q => s_axi_lite_rdata(13), - R => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\ + I0 => \^hsize_vid_reg[15]\(5), + I1 => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(5), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1), + I3 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(0), + I4 => \^vsize_vid_reg[12]\(5), + I5 => \^stride_vid_reg[15]\(5), + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5]\ ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[14]\: unisim.vcomponents.FDRE +ip2axi_rddata_int_inferred_i_72: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"CAFFCAF0CA0FCA00" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[14]_i_1_n_0\, - Q => s_axi_lite_rdata(14), - R => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\ + I0 => \^hsize_vid_reg[15]\(4), + I1 => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(4), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1), + I3 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(0), + I4 => \^vsize_vid_reg[12]\(4), + I5 => \^stride_vid_reg[15]\(4), + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4]\ ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[15]\: unisim.vcomponents.FDRE +ip2axi_rddata_int_inferred_i_73: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"CAFFCAF0CA0FCA00" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[15]_i_1_n_0\, - Q => s_axi_lite_rdata(15), - R => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\ + I0 => \^hsize_vid_reg[15]\(3), + I1 => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(3), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1), + I3 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(0), + I4 => \^vsize_vid_reg[12]\(3), + I5 => \^stride_vid_reg[15]\(3), + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3]\ ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[16]\: unisim.vcomponents.FDRE +ip2axi_rddata_int_inferred_i_74: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"F888" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => ip2axi_rddata_captured(16), - Q => s_axi_lite_rdata(16), - R => '0' + I0 => ip2axi_rddata_int_inferred_i_79_n_0, + I1 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[4]\, + I2 => \dmacr_i_reg[2]\, + I3 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_1\, + O => ip2axi_rddata_int_inferred_i_74_n_0 ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[17]\: unisim.vcomponents.FDRE +ip2axi_rddata_int_inferred_i_75: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"F888" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => ip2axi_rddata_captured(17), - Q => s_axi_lite_rdata(17), - R => '0' + I0 => ip2axi_rddata_int_inferred_i_80_n_0, + I1 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[4]\, + I2 => p_71_out(0), + I3 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_1\, + O => ip2axi_rddata_int_inferred_i_75_n_0 ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[18]\: unisim.vcomponents.FDRE +ip2axi_rddata_int_inferred_i_77: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"CAFFCAF0CA0FCA00" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => ip2axi_rddata_captured(18), - Q => s_axi_lite_rdata(18), - R => '0' + I0 => \^hsize_vid_reg[15]\(0), + I1 => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(0), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1), + I3 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(0), + I4 => \^vsize_vid_reg[12]\(0), + I5 => \^stride_vid_reg[15]\(0), + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0]\ ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[19]\: unisim.vcomponents.FDRE +ip2axi_rddata_int_inferred_i_79: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"CAFFCAF0CA0FCA00" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => ip2axi_rddata_captured(19), - Q => s_axi_lite_rdata(19), - R => '0' + I0 => \^hsize_vid_reg[15]\(2), + I1 => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(2), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1), + I3 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(0), + I4 => \^vsize_vid_reg[12]\(2), + I5 => \^stride_vid_reg[15]\(2), + O => ip2axi_rddata_int_inferred_i_79_n_0 ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[1]\: unisim.vcomponents.FDRE +ip2axi_rddata_int_inferred_i_80: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"CAFFCAF0CA0FCA00" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => ip2axi_rddata_captured(1), - Q => s_axi_lite_rdata(1), - R => '0' + I0 => \^hsize_vid_reg[15]\(1), + I1 => \^gen_start_addr_reg[0].start_address_vid_reg[0][31]\(1), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1), + I3 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(0), + I4 => \^vsize_vid_reg[12]\(1), + I5 => \^stride_vid_reg[15]\(1), + O => ip2axi_rddata_int_inferred_i_80_n_0 ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[20]\: unisim.vcomponents.FDRE +prmtr_updt_complete_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, + C => m_axi_mm2s_aclk, CE => '1', - D => ip2axi_rddata_captured(20), - Q => s_axi_lite_rdata(20), + D => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[2]\, + Q => p_66_out, R => '0' ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[21]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_lite_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[21]_i_1_n_0\, - Q => s_axi_lite_rdata(21), - R => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\ +\reg_module_hsize_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(1), + D => D(0), + Q => \^hsize_vid_reg[15]\(0), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[22]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_lite_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[22]_i_1_n_0\, - Q => s_axi_lite_rdata(22), - R => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\ +\reg_module_hsize_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(1), + D => D(10), + Q => \^hsize_vid_reg[15]\(10), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[23]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_lite_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[23]_i_1_n_0\, - Q => s_axi_lite_rdata(23), - R => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\ +\reg_module_hsize_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(1), + D => D(11), + Q => \^hsize_vid_reg[15]\(11), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[24]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_lite_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[24]_i_1_n_0\, - Q => s_axi_lite_rdata(24), - R => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\ +\reg_module_hsize_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(1), + D => D(12), + Q => \^hsize_vid_reg[15]\(12), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[25]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_axi_lite_aclk, - CE => '1', - D => ip2axi_rddata_captured(25), - Q => s_axi_lite_rdata(25), - R => '0' +\reg_module_hsize_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(1), + D => D(13), + Q => \^hsize_vid_reg[15]\(13), + R => SR(0) + ); +\reg_module_hsize_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(1), + D => D(14), + Q => \^hsize_vid_reg[15]\(14), + R => SR(0) + ); +\reg_module_hsize_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(1), + D => D(15), + Q => \^hsize_vid_reg[15]\(15), + R => SR(0) + ); +\reg_module_hsize_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(1), + D => D(1), + Q => \^hsize_vid_reg[15]\(1), + R => SR(0) + ); +\reg_module_hsize_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(1), + D => D(2), + Q => \^hsize_vid_reg[15]\(2), + R => SR(0) + ); +\reg_module_hsize_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(1), + D => D(3), + Q => \^hsize_vid_reg[15]\(3), + R => SR(0) + ); +\reg_module_hsize_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(1), + D => D(4), + Q => \^hsize_vid_reg[15]\(4), + R => SR(0) + ); +\reg_module_hsize_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(1), + D => D(5), + Q => \^hsize_vid_reg[15]\(5), + R => SR(0) + ); +\reg_module_hsize_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(1), + D => D(6), + Q => \^hsize_vid_reg[15]\(6), + R => SR(0) + ); +\reg_module_hsize_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(1), + D => D(7), + Q => \^hsize_vid_reg[15]\(7), + R => SR(0) + ); +\reg_module_hsize_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(1), + D => D(8), + Q => \^hsize_vid_reg[15]\(8), + R => SR(0) + ); +\reg_module_hsize_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(1), + D => D(9), + Q => \^hsize_vid_reg[15]\(9), + R => SR(0) + ); +\reg_module_vsize_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(0), + D => D(0), + Q => \^vsize_vid_reg[12]\(0), + R => SR(0) + ); +\reg_module_vsize_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(0), + D => D(10), + Q => \^vsize_vid_reg[12]\(10), + R => SR(0) + ); +\reg_module_vsize_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(0), + D => D(11), + Q => \^vsize_vid_reg[12]\(11), + R => SR(0) + ); +\reg_module_vsize_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(0), + D => D(12), + Q => \^vsize_vid_reg[12]\(12), + R => SR(0) + ); +\reg_module_vsize_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(0), + D => D(1), + Q => \^vsize_vid_reg[12]\(1), + R => SR(0) + ); +\reg_module_vsize_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(0), + D => D(2), + Q => \^vsize_vid_reg[12]\(2), + R => SR(0) + ); +\reg_module_vsize_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(0), + D => D(3), + Q => \^vsize_vid_reg[12]\(3), + R => SR(0) + ); +\reg_module_vsize_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(0), + D => D(4), + Q => \^vsize_vid_reg[12]\(4), + R => SR(0) + ); +\reg_module_vsize_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(0), + D => D(5), + Q => \^vsize_vid_reg[12]\(5), + R => SR(0) + ); +\reg_module_vsize_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(0), + D => D(6), + Q => \^vsize_vid_reg[12]\(6), + R => SR(0) + ); +\reg_module_vsize_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(0), + D => D(7), + Q => \^vsize_vid_reg[12]\(7), + R => SR(0) + ); +\reg_module_vsize_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(0), + D => D(8), + Q => \^vsize_vid_reg[12]\(8), + R => SR(0) + ); +\reg_module_vsize_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(0), + D => D(9), + Q => \^vsize_vid_reg[12]\(9), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[26]\: unisim.vcomponents.FDRE +regdir_idle_i_i_1: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFCF8AFFFFFFFF" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[26]_i_1_n_0\, - Q => s_axi_lite_rdata(26), - R => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\ + I0 => \^p_67_out\, + I1 => run_stop_d1, + I2 => \dmacr_i_reg[0]\, + I3 => p_66_out, + I4 => stop, + I5 => prmry_resetn_i_reg, + O => regdir_idle_i_i_1_n_0 ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[27]\: unisim.vcomponents.FDRE +regdir_idle_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, + C => m_axi_mm2s_aclk, CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[27]_i_1_n_0\, - Q => s_axi_lite_rdata(27), - R => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\ + D => regdir_idle_i_i_1_n_0, + Q => \^p_67_out\, + R => '0' ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[28]\: unisim.vcomponents.FDRE +run_stop_d1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, + C => m_axi_mm2s_aclk, CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_1_n_0\, - Q => s_axi_lite_rdata(28), - R => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\ + D => \dmacr_i_reg[0]\, + Q => run_stop_d1, + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_axi_vdma_regdirect__parameterized0\ is + port ( + prmry_in_xored : out STD_LOGIC; + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg\ : out STD_LOGIC; + \vsize_vid_reg[12]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); + \hsize_vid_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + \stride_vid_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[2]\ : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + p_in_d1_cdc_from : in STD_LOGIC; + halted_reg : in STD_LOGIC; + prmry_resetn_i_reg : in STD_LOGIC; + prmtr_update_complete : in STD_LOGIC; + s2mm_cdc2dmac_fsync : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + s2mm_axi2ip_wrce : in STD_LOGIC_VECTOR ( 5 downto 0 ); + D : in STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_axi_vdma_regdirect__parameterized0\ : entity is "axi_vdma_regdirect"; +end \Arty_Z7_20_axi_vdma_0_0_axi_vdma_regdirect__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_axi_vdma_regdirect__parameterized0\ is + signal s2mm_prmtr_updt_complete : STD_LOGIC; +begin +\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(2), + D => D(0), + Q => \stride_vid_reg[15]\(0), + R => SR(0) + ); +\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(2), + D => D(10), + Q => \stride_vid_reg[15]\(10), + R => SR(0) + ); +\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(2), + D => D(11), + Q => \stride_vid_reg[15]\(11), + R => SR(0) + ); +\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(2), + D => D(12), + Q => \stride_vid_reg[15]\(12), + R => SR(0) + ); +\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(2), + D => D(13), + Q => \stride_vid_reg[15]\(13), + R => SR(0) + ); +\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(2), + D => D(14), + Q => \stride_vid_reg[15]\(14), + R => SR(0) + ); +\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(2), + D => D(15), + Q => \stride_vid_reg[15]\(15), + R => SR(0) + ); +\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(2), + D => D(1), + Q => \stride_vid_reg[15]\(1), + R => SR(0) + ); +\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(2), + D => D(2), + Q => \stride_vid_reg[15]\(2), + R => SR(0) + ); +\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(2), + D => D(3), + Q => \stride_vid_reg[15]\(3), + R => SR(0) + ); +\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(2), + D => D(4), + Q => \stride_vid_reg[15]\(4), + R => SR(0) + ); +\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(2), + D => D(5), + Q => \stride_vid_reg[15]\(5), + R => SR(0) + ); +\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(2), + D => D(6), + Q => \stride_vid_reg[15]\(6), + R => SR(0) + ); +\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(2), + D => D(7), + Q => \stride_vid_reg[15]\(7), + R => SR(0) + ); +\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(2), + D => D(8), + Q => \stride_vid_reg[15]\(8), + R => SR(0) + ); +\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(2), + D => D(9), + Q => \stride_vid_reg[15]\(9), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[29]\: unisim.vcomponents.FDRE +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__15\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"6" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => ip2axi_rddata_captured(29), - Q => s_axi_lite_rdata(29), - R => '0' + I0 => s2mm_prmtr_updt_complete, + I1 => p_in_d1_cdc_from, + O => prmry_in_xored ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[2]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => ip2axi_rddata_captured(2), - Q => s_axi_lite_rdata(2), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(0), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(0), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[30]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => ip2axi_rddata_captured(30), - Q => s_axi_lite_rdata(30), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(10), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(10), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[31]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_2_n_0\, - Q => s_axi_lite_rdata(31), - R => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(11), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(11), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[3]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => ip2axi_rddata_captured(3), - Q => s_axi_lite_rdata(3), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(12), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(12), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[4]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => ip2axi_rddata_captured(4), - Q => s_axi_lite_rdata(4), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(13), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(13), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[5]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[5]_i_1_n_0\, - Q => s_axi_lite_rdata(5), - R => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(14), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(14), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[6]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => ip2axi_rddata_captured(6), - Q => s_axi_lite_rdata(6), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(15), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(15), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[7]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[7]_i_1_n_0\, - Q => s_axi_lite_rdata(7), - R => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(16), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(16), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[8]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[8]_i_1_n_0\, - Q => s_axi_lite_rdata(8), - R => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(17), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(17), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[9]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[9]_i_1_n_0\, - Q => s_axi_lite_rdata(9), - R => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(18), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(18), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[0]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(0), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(0), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(19), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(19), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[10]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(10), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(10), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(1), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(1), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[11]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(11), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(11), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(20), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(20), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[12]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(12), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(12), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(21), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(21), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[13]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(13), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(13), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(22), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(22), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[14]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(14), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(14), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(23), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(23), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[15]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(15), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(15), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(24), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(24), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[16]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(16), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(16), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(25), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(25), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[17]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(17), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(17), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(26), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(26), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[18]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(18), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(18), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(27), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(27), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[19]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(19), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(19), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(28), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(28), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[1]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(1), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(1), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(29), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(29), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[20]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(20), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(20), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(2), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(2), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[21]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(21), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(21), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(30), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(30), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[22]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(22), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(22), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(31), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(31), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[23]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(23), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(23), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(3), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(3), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[24]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(24), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(24), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(4), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(4), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[25]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(25), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(25), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(5), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(5), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[26]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(26), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(26), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(6), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(6), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[27]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(27), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(27), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(7), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(7), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[28]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(28), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(28), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(8), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(8), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[29]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(29), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(29), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(3), + D => D(9), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(9), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[2]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(2), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(2), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(0), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(0), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[30]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(30), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(30), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(10), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(10), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[31]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(31), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(31), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(11), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(11), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[3]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(3), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(3), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(12), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(12), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[4]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(4), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(4), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(13), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(13), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[5]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(5), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(5), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(14), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(14), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[6]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(6), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(6), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(15), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(15), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[7]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(7), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(7), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(16), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(16), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[8]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(8), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(8), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(17), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(17), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[9]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => mm2s_ip2axi_rddata_d1(9), - Q => ip2axi_rddata_captured_mm2s_cdc_tig(9), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(18), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(18), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[0]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(0), - Q => mm2s_axi2ip_wrdata_cdc_tig(0), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(19), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(19), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[10]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(10), - Q => mm2s_axi2ip_wrdata_cdc_tig(10), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(1), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(1), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[11]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(11), - Q => mm2s_axi2ip_wrdata_cdc_tig(11), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(20), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(20), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(12), - Q => mm2s_axi2ip_wrdata_cdc_tig(12), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(21), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(21), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(13), - Q => mm2s_axi2ip_wrdata_cdc_tig(13), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(22), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(22), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[14]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(14), - Q => mm2s_axi2ip_wrdata_cdc_tig(14), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(23), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(23), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[15]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(15), - Q => mm2s_axi2ip_wrdata_cdc_tig(15), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(24), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(24), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[16]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(16), - Q => mm2s_axi2ip_wrdata_cdc_tig(16), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(25), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(25), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[17]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(17), - Q => mm2s_axi2ip_wrdata_cdc_tig(17), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(26), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(26), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(18), - Q => mm2s_axi2ip_wrdata_cdc_tig(18), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(27), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(27), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[19]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(19), - Q => mm2s_axi2ip_wrdata_cdc_tig(19), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(28), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(28), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[1]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(1), - Q => mm2s_axi2ip_wrdata_cdc_tig(1), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(29), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(29), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[20]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(20), - Q => mm2s_axi2ip_wrdata_cdc_tig(20), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(2), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(2), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[21]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(21), - Q => mm2s_axi2ip_wrdata_cdc_tig(21), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(30), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(30), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[22]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(22), - Q => mm2s_axi2ip_wrdata_cdc_tig(22), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(31), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(31), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[23]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(23), - Q => mm2s_axi2ip_wrdata_cdc_tig(23), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(3), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(3), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[24]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(24), - Q => mm2s_axi2ip_wrdata_cdc_tig(24), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(4), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(4), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[25]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(25), - Q => mm2s_axi2ip_wrdata_cdc_tig(25), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(5), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(5), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[26]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(26), - Q => mm2s_axi2ip_wrdata_cdc_tig(26), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(6), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(6), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[27]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(27), - Q => mm2s_axi2ip_wrdata_cdc_tig(27), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(7), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(7), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[28]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(28), - Q => mm2s_axi2ip_wrdata_cdc_tig(28), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(8), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(8), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[29]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(29), - Q => mm2s_axi2ip_wrdata_cdc_tig(29), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(4), + D => D(9), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(9), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[2]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(2), - Q => mm2s_axi2ip_wrdata_cdc_tig(2), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(0), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(0), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[30]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(30), - Q => mm2s_axi2ip_wrdata_cdc_tig(30), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(10), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(10), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[31]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(31), - Q => mm2s_axi2ip_wrdata_cdc_tig(31), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(11), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(11), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[3]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(3), - Q => mm2s_axi2ip_wrdata_cdc_tig(3), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(12), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(12), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(4), - Q => mm2s_axi2ip_wrdata_cdc_tig(4), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(13), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(13), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[5]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(5), - Q => mm2s_axi2ip_wrdata_cdc_tig(5), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(14), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(14), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[6]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(6), - Q => mm2s_axi2ip_wrdata_cdc_tig(6), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(15), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(15), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[7]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(7), - Q => mm2s_axi2ip_wrdata_cdc_tig(7), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(16), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(16), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[8]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(8), - Q => mm2s_axi2ip_wrdata_cdc_tig(8), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(17), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(17), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[9]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => wdata(9), - Q => mm2s_axi2ip_wrdata_cdc_tig(9), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(18), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(18), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(0), - Q => mm2s_ip2axi_rddata_d1(0), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(19), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(19), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(10), - Q => mm2s_ip2axi_rddata_d1(10), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(1), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(1), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(11), - Q => mm2s_ip2axi_rddata_d1(11), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(20), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(20), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(12), - Q => mm2s_ip2axi_rddata_d1(12), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(21), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(21), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[13]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(13), - Q => mm2s_ip2axi_rddata_d1(13), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(22), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(22), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[14]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(14), - Q => mm2s_ip2axi_rddata_d1(14), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(23), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(23), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(15), - Q => mm2s_ip2axi_rddata_d1(15), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(24), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(24), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[16]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(16), - Q => mm2s_ip2axi_rddata_d1(16), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(25), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(25), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[17]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(17), - Q => mm2s_ip2axi_rddata_d1(17), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(26), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(26), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[18]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(18), - Q => mm2s_ip2axi_rddata_d1(18), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(27), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(27), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[19]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(19), - Q => mm2s_ip2axi_rddata_d1(19), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(28), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(28), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[1]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(1), - Q => mm2s_ip2axi_rddata_d1(1), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(29), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(29), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[20]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(20), - Q => mm2s_ip2axi_rddata_d1(20), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(2), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(2), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[21]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(21), - Q => mm2s_ip2axi_rddata_d1(21), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(30), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(30), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[22]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(22), - Q => mm2s_ip2axi_rddata_d1(22), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(31), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(31), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[23]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(23), - Q => mm2s_ip2axi_rddata_d1(23), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(3), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(3), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[24]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(24), - Q => mm2s_ip2axi_rddata_d1(24), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(4), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(4), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[25]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(25), - Q => mm2s_ip2axi_rddata_d1(25), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(5), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(5), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[26]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(26), - Q => mm2s_ip2axi_rddata_d1(26), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(6), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(6), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[27]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(27), - Q => mm2s_ip2axi_rddata_d1(27), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(7), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(7), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[28]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(28), - Q => mm2s_ip2axi_rddata_d1(28), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(8), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(8), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[29]\: unisim.vcomponents.FDRE +\GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(29), - Q => mm2s_ip2axi_rddata_d1(29), - R => '0' + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(5), + D => D(9), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(9), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[2]\: unisim.vcomponents.FDRE +\VIDEO_REG_I/GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_i_1__0\: unisim.vcomponents.LUT5 generic map( - INIT => '0' + INIT => X"00203020" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(2), - Q => mm2s_ip2axi_rddata_d1(2), - R => '0' + I0 => s2mm_prmtr_updt_complete, + I1 => halted_reg, + I2 => prmry_resetn_i_reg, + I3 => prmtr_update_complete, + I4 => s2mm_cdc2dmac_fsync, + O => \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg\ ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[30]\: unisim.vcomponents.FDRE +prmtr_updt_complete_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, + C => m_axi_s2mm_aclk, CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(30), - Q => mm2s_ip2axi_rddata_d1(30), + D => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[2]\, + Q => s2mm_prmtr_updt_complete, R => '0' ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]\: unisim.vcomponents.FDRE +\reg_module_hsize_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(1), + D => D(0), + Q => \hsize_vid_reg[15]\(0), + R => SR(0) + ); +\reg_module_hsize_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(1), + D => D(10), + Q => \hsize_vid_reg[15]\(10), + R => SR(0) + ); +\reg_module_hsize_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(1), + D => D(11), + Q => \hsize_vid_reg[15]\(11), + R => SR(0) + ); +\reg_module_hsize_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(1), + D => D(12), + Q => \hsize_vid_reg[15]\(12), + R => SR(0) + ); +\reg_module_hsize_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(1), + D => D(13), + Q => \hsize_vid_reg[15]\(13), + R => SR(0) + ); +\reg_module_hsize_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(1), + D => D(14), + Q => \hsize_vid_reg[15]\(14), + R => SR(0) + ); +\reg_module_hsize_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(1), + D => D(15), + Q => \hsize_vid_reg[15]\(15), + R => SR(0) + ); +\reg_module_hsize_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(1), + D => D(1), + Q => \hsize_vid_reg[15]\(1), + R => SR(0) + ); +\reg_module_hsize_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(1), + D => D(2), + Q => \hsize_vid_reg[15]\(2), + R => SR(0) + ); +\reg_module_hsize_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(1), + D => D(3), + Q => \hsize_vid_reg[15]\(3), + R => SR(0) + ); +\reg_module_hsize_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(1), + D => D(4), + Q => \hsize_vid_reg[15]\(4), + R => SR(0) + ); +\reg_module_hsize_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(1), + D => D(5), + Q => \hsize_vid_reg[15]\(5), + R => SR(0) + ); +\reg_module_hsize_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(1), + D => D(6), + Q => \hsize_vid_reg[15]\(6), + R => SR(0) + ); +\reg_module_hsize_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(1), + D => D(7), + Q => \hsize_vid_reg[15]\(7), + R => SR(0) + ); +\reg_module_hsize_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(1), + D => D(8), + Q => \hsize_vid_reg[15]\(8), + R => SR(0) + ); +\reg_module_hsize_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(1), + D => D(9), + Q => \hsize_vid_reg[15]\(9), + R => SR(0) + ); +\reg_module_vsize_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(0), + Q => \vsize_vid_reg[12]\(0), + R => SR(0) + ); +\reg_module_vsize_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(10), + Q => \vsize_vid_reg[12]\(10), + R => SR(0) + ); +\reg_module_vsize_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(11), + Q => \vsize_vid_reg[12]\(11), + R => SR(0) + ); +\reg_module_vsize_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(12), + Q => \vsize_vid_reg[12]\(12), + R => SR(0) + ); +\reg_module_vsize_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(1), + Q => \vsize_vid_reg[12]\(1), + R => SR(0) + ); +\reg_module_vsize_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(2), + Q => \vsize_vid_reg[12]\(2), + R => SR(0) + ); +\reg_module_vsize_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(3), + Q => \vsize_vid_reg[12]\(3), + R => SR(0) + ); +\reg_module_vsize_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(4), + Q => \vsize_vid_reg[12]\(4), + R => SR(0) + ); +\reg_module_vsize_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(5), + Q => \vsize_vid_reg[12]\(5), + R => SR(0) + ); +\reg_module_vsize_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(6), + Q => \vsize_vid_reg[12]\(6), + R => SR(0) + ); +\reg_module_vsize_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(7), + Q => \vsize_vid_reg[12]\(7), + R => SR(0) + ); +\reg_module_vsize_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(8), + Q => \vsize_vid_reg[12]\(8), + R => SR(0) + ); +\reg_module_vsize_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(9), + Q => \vsize_vid_reg[12]\(9), + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_register is + port ( + p_71_out : out STD_LOGIC_VECTOR ( 18 downto 0 ); + soft_reset_d1_reg : out STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]\ : out STD_LOGIC; + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]\ : out STD_LOGIC; + s_axis_cmd_tvalid_reg : out STD_LOGIC; + err_d1_reg_0 : out STD_LOGIC; + err_d1_reg_1 : out STD_LOGIC; + err_d1_reg_2 : out STD_LOGIC; + ioc_irq_reg_0 : out STD_LOGIC; + dly_irq_reg_0 : out STD_LOGIC; + p_78_out : out STD_LOGIC; + s_soft_reset_i0 : out STD_LOGIC; + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg\ : out STD_LOGIC; + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]_0\ : out STD_LOGIC; + ch1_delay_zero : out STD_LOGIC; + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0]\ : out STD_LOGIC; + p_13_out : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 4 downto 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + err_irq_reg_0 : out STD_LOGIC; + \dmacr_i_reg[0]_0\ : out STD_LOGIC; + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : out STD_LOGIC; + \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axis_cmd_tvalid_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + dmacr_i : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + mm2s_axi2ip_wrce : in STD_LOGIC_VECTOR ( 1 downto 0 ); + D : in STD_LOGIC_VECTOR ( 23 downto 0 ); + \dmacr_i_reg[2]_0\ : in STD_LOGIC; + reset_counts_reg_0 : in STD_LOGIC; + halted_clr_reg : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4]\ : in STD_LOGIC; + slverr_i_reg : in STD_LOGIC; + decerr_i_reg : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12]\ : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13]\ : in STD_LOGIC; + mm2s_halt_cmplt : in STD_LOGIC; + halt_reset : in STD_LOGIC; + prmry_in : in STD_LOGIC; + p_50_out : in STD_LOGIC; + ch1_delay_cnt_en : in STD_LOGIC; + p_17_out : in STD_LOGIC; + ch1_dly_irq_set : in STD_LOGIC; + mask_fsync_out_i : in STD_LOGIC; + p_47_out : in STD_LOGIC; + prmry_resetn_i_reg : in STD_LOGIC; + p_24_out : in STD_LOGIC; + p_45_out : in STD_LOGIC; + mm2s_ioc_irq_set : in STD_LOGIC; + dma_err : in STD_LOGIC; + mm2s_halt : in STD_LOGIC; + initial_frame : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_register : entity is "axi_vdma_register"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_register; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_register is + signal \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_1_n_0\ : STD_LOGIC; + signal \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_2_n_0\ : STD_LOGIC; + signal \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_3_n_0\ : STD_LOGIC; + signal \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_4_n_0\ : STD_LOGIC; + signal \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_5_n_0\ : STD_LOGIC; + signal \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_1_n_0\ : STD_LOGIC; + signal \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_2_n_0\ : STD_LOGIC; + signal \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_3_n_0\ : STD_LOGIC; + signal \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_4_n_0\ : STD_LOGIC; + signal \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_5_n_0\ : STD_LOGIC; + signal \^gen_include_mm2s.gen_ch1_delay_interrupt.gen_ch1_fast_counter.ch1_dly_fast_cnt_reg[6]\ : STD_LOGIC; + signal \^gen_include_mm2s.gen_ch1_delay_interrupt.gen_ch1_fast_counter.ch1_dly_fast_cnt_reg[6]_0\ : STD_LOGIC; + signal \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_i_3_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_5_n_0\ : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \^ch1_delay_zero\ : STD_LOGIC; + signal \^dly_irq_reg_0\ : STD_LOGIC; + signal err : STD_LOGIC; + signal err_d1 : STD_LOGIC; + signal \^err_d1_reg_0\ : STD_LOGIC; + signal \^err_d1_reg_1\ : STD_LOGIC; + signal \^err_d1_reg_2\ : STD_LOGIC; + signal err_irq_i_1_n_0 : STD_LOGIC; + signal \^err_irq_reg_0\ : STD_LOGIC; + signal introut01_out : STD_LOGIC; + signal introut_i_1_n_0 : STD_LOGIC; + signal \^ioc_irq_reg_0\ : STD_LOGIC; + signal irqdelay_wren_i : STD_LOGIC; + signal irqthresh_wren_i : STD_LOGIC; + signal p_1_in : STD_LOGIC; + signal \^p_71_out\ : STD_LOGIC_VECTOR ( 18 downto 0 ); + signal \^s_axis_cmd_tvalid_reg\ : STD_LOGIC; + signal \^soft_reset_d1_reg\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_1\ : label is "soft_lutpair46"; + attribute SOFT_HLUTNM of \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_1\ : label is "soft_lutpair46"; + attribute SOFT_HLUTNM of \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_i_3\ : label is "soft_lutpair45"; + attribute SOFT_HLUTNM of \dmacr_i[0]_i_2\ : label is "soft_lutpair47"; + attribute SOFT_HLUTNM of introut_i_1 : label is "soft_lutpair47"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[63]_i_1\ : label is "soft_lutpair45"; +begin + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]\ <= \^gen_include_mm2s.gen_ch1_delay_interrupt.gen_ch1_fast_counter.ch1_dly_fast_cnt_reg[6]\; + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]_0\ <= \^gen_include_mm2s.gen_ch1_delay_interrupt.gen_ch1_fast_counter.ch1_dly_fast_cnt_reg[6]_0\; + Q(4 downto 0) <= \^q\(4 downto 0); + ch1_delay_zero <= \^ch1_delay_zero\; + dly_irq_reg_0 <= \^dly_irq_reg_0\; + err_d1_reg_0 <= \^err_d1_reg_0\; + err_d1_reg_1 <= \^err_d1_reg_1\; + err_d1_reg_2 <= \^err_d1_reg_2\; + err_irq_reg_0 <= \^err_irq_reg_0\; + ioc_irq_reg_0 <= \^ioc_irq_reg_0\; + p_71_out(18 downto 0) <= \^p_71_out\(18 downto 0); + s_axis_cmd_tvalid_reg <= \^s_axis_cmd_tvalid_reg\; + soft_reset_d1_reg <= \^soft_reset_d1_reg\; +\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(31), - Q => mm2s_ip2axi_rddata_d1(31), - R => '0' + CE => mm2s_axi2ip_wrce(0), + D => D(16), + Q => \^p_71_out\(11), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3]\: unisim.vcomponents.FDRE +\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(3), - Q => mm2s_ip2axi_rddata_d1(3), - R => '0' + CE => mm2s_axi2ip_wrce(0), + D => D(17), + Q => \^p_71_out\(12), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4]\: unisim.vcomponents.FDRE +\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(4), - Q => mm2s_ip2axi_rddata_d1(4), - R => '0' + CE => mm2s_axi2ip_wrce(0), + D => D(18), + Q => \^p_71_out\(13), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5]\: unisim.vcomponents.FDRE +\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(5), - Q => mm2s_ip2axi_rddata_d1(5), - R => '0' + CE => mm2s_axi2ip_wrce(0), + D => D(19), + Q => \^p_71_out\(14), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6]\: unisim.vcomponents.FDRE +\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(6), - Q => mm2s_ip2axi_rddata_d1(6), - R => '0' + CE => mm2s_axi2ip_wrce(0), + D => D(20), + Q => \^p_71_out\(15), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7]\: unisim.vcomponents.FDRE +\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(7), - Q => mm2s_ip2axi_rddata_d1(7), - R => '0' + CE => mm2s_axi2ip_wrce(0), + D => D(21), + Q => \^p_71_out\(16), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8]\: unisim.vcomponents.FDRE +\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(8), - Q => mm2s_ip2axi_rddata_d1(8), - R => '0' + CE => mm2s_axi2ip_wrce(0), + D => D(22), + Q => \^p_71_out\(17), + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9]\: unisim.vcomponents.FDRE +\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(9), - Q => mm2s_ip2axi_rddata_d1(9), - R => '0' - ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.prepare_wrce_d1_i_1\: unisim.vcomponents.LUT2 + CE => mm2s_axi2ip_wrce(0), + D => D(23), + Q => \^p_71_out\(18), + R => SR(0) + ); +\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8" + INIT => X"A8" ) port map ( - I0 => lite_wr_addr_phase_finished_data_phase_started, - I1 => wvalid, - O => prepare_wrce + I0 => mm2s_axi2ip_wrce(0), + I1 => \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_2_n_0\, + I2 => \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_3_n_0\, + O => \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_1_n_0\ ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.prepare_wrce_d1_reg\: unisim.vcomponents.FDRE +\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_2\: unisim.vcomponents.LUT5 generic map( - INIT => '0' + INIT => X"FFFF6FF6" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => prepare_wrce, - Q => prepare_wrce_d1, - R => SR(0) + I0 => D(16), + I1 => \^p_71_out\(11), + I2 => D(17), + I3 => \^p_71_out\(12), + I4 => \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_4_n_0\, + O => \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_2_n_0\ ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.prepare_wrce_pulse_lite_d6_reg_srl6\: unisim.vcomponents.SRL16E +\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_3\: unisim.vcomponents.LUT5 generic map( - INIT => X"0000" + INIT => X"FFFF6FF6" ) port map ( - A0 => '1', - A1 => '0', - A2 => '1', - A3 => '0', - CE => '1', - CLK => s_axi_lite_aclk, - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.prepare_wrce_pulse_lite_d6_reg_srl6_i_1_n_0\, - Q => prepare_wrce_pulse_lite_d6 + I0 => D(20), + I1 => \^p_71_out\(15), + I2 => D(21), + I3 => \^p_71_out\(16), + I4 => \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_5_n_0\, + O => \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_3_n_0\ ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.prepare_wrce_pulse_lite_d6_reg_srl6_i_1\: unisim.vcomponents.LUT3 +\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_4\: unisim.vcomponents.LUT4 generic map( - INIT => X"08" + INIT => X"6FF6" ) port map ( - I0 => wvalid, - I1 => lite_wr_addr_phase_finished_data_phase_started, - I2 => prepare_wrce_d1, - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.prepare_wrce_pulse_lite_d6_reg_srl6_i_1_n_0\ + I0 => \^p_71_out\(18), + I1 => D(23), + I2 => \^p_71_out\(17), + I3 => D(22), + O => \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_4_n_0\ ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.rvalid_out_i_i_1\: unisim.vcomponents.LUT4 +\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_5\: unisim.vcomponents.LUT4 generic map( - INIT => X"0C88" + INIT => X"6FF6" ) port map ( - I0 => \^s_axi_lite_arready\, - I1 => s_axi_lite_resetn, - I2 => s_axi_lite_rready, - I3 => \^s_axi_lite_rvalid\, - O => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.rvalid_out_i_i_1_n_0\ + I0 => \^p_71_out\(14), + I1 => D(19), + I2 => \^p_71_out\(13), + I3 => D(18), + O => \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_5_n_0\ ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.rvalid_out_i_reg\: unisim.vcomponents.FDRE +\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, + C => m_axi_mm2s_aclk, CE => '1', - D => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.rvalid_out_i_i_1_n_0\, - Q => \^s_axi_lite_rvalid\, - R => '0' + D => \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_1_n_0\, + Q => irqdelay_wren_i, + R => SR(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.sig_arvalid_arrived_d4_reg_srl3\: unisim.vcomponents.SRL16E +\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[16]\: unisim.vcomponents.FDSE generic map( - INIT => X"0000" + INIT => '0' ) port map ( - A0 => '0', - A1 => '1', - A2 => '0', - A3 => '0', - CE => '1', - CLK => s_axi_lite_aclk, - D => sig_arvalid_arrived_d1, - Q => sig_arvalid_arrived_d4 + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(0), + D => D(8), + Q => \^p_71_out\(3), + S => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18]\(0) ); -\GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.wready_out_i_reg\: unisim.vcomponents.FDRE +\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => prepare_wrce_pulse_lite_d6, - Q => \^s_axi_lite_wready\, - R => SR(0) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(0), + D => D(9), + Q => \^p_71_out\(4), + R => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18]\(0) ); -\GEN_NUM_FSTORES_1.reg_module_start_address1_i[31]_i_2\: unisim.vcomponents.LUT4 +\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[18]\: unisim.vcomponents.FDRE generic map( - INIT => X"7FFF" + INIT => '0' ) port map ( - I0 => axi2ip_wraddr_captured_mm2s_cdc_tig(4), - I1 => axi2ip_wraddr_captured_mm2s_cdc_tig(6), - I2 => axi2ip_wraddr_captured_mm2s_cdc_tig(2), - I3 => axi2ip_wraddr_captured_mm2s_cdc_tig(3), - O => \GEN_NUM_FSTORES_1.reg_module_start_address1_i[31]_i_2_n_0\ + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(0), + D => D(10), + Q => \^p_71_out\(5), + R => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18]\(0) ); -\araddr_reg[2]\: unisim.vcomponents.FDRE +\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_araddr(0), - Q => p_2_in(0), - R => SR(0) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(0), + D => D(11), + Q => \^p_71_out\(6), + R => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18]\(0) ); -\araddr_reg[3]\: unisim.vcomponents.FDRE +\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_araddr(1), - Q => p_2_in(1), - R => SR(0) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(0), + D => D(12), + Q => \^p_71_out\(7), + R => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18]\(0) ); -\araddr_reg[4]\: unisim.vcomponents.FDRE +\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_araddr(2), - Q => p_2_in(2), - R => SR(0) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(0), + D => D(13), + Q => \^p_71_out\(8), + R => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18]\(0) ); -\araddr_reg[5]\: unisim.vcomponents.FDRE +\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_araddr(3), - Q => p_2_in(3), - R => SR(0) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(0), + D => D(14), + Q => \^p_71_out\(9), + R => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18]\(0) ); -\araddr_reg[6]\: unisim.vcomponents.FDRE +\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_araddr(4), - Q => p_2_in(4), - R => SR(0) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(0), + D => D(15), + Q => \^p_71_out\(10), + R => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18]\(0) ); -\araddr_reg[7]\: unisim.vcomponents.FDRE +\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"A8" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_araddr(5), - Q => p_2_in(5), - R => SR(0) + I0 => mm2s_axi2ip_wrce(0), + I1 => \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_2_n_0\, + I2 => \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_3_n_0\, + O => \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_1_n_0\ ); -arvalid_reg: unisim.vcomponents.FDRE +\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_2\: unisim.vcomponents.LUT5 generic map( - INIT => '0' + INIT => X"FFFF6FF6" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_arvalid, - Q => arvalid, - R => SR(0) + I0 => D(8), + I1 => \^p_71_out\(3), + I2 => D(9), + I3 => \^p_71_out\(4), + I4 => \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_4_n_0\, + O => \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_2_n_0\ ); -\awaddr_reg[2]\: unisim.vcomponents.FDRE +\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_3\: unisim.vcomponents.LUT5 generic map( - INIT => '0' + INIT => X"FFFF6FF6" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_awaddr(0), - Q => awaddr(2), - R => SR(0) + I0 => D(12), + I1 => \^p_71_out\(7), + I2 => D(13), + I3 => \^p_71_out\(8), + I4 => \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_5_n_0\, + O => \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_3_n_0\ ); -\awaddr_reg[3]\: unisim.vcomponents.FDRE +\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_4\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"6FF6" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_awaddr(1), - Q => awaddr(3), - R => SR(0) + I0 => \^p_71_out\(10), + I1 => D(15), + I2 => \^p_71_out\(9), + I3 => D(14), + O => \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_4_n_0\ ); -\awaddr_reg[4]\: unisim.vcomponents.FDRE +\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_5\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"6FF6" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_awaddr(2), - Q => awaddr(4), - R => SR(0) + I0 => \^p_71_out\(6), + I1 => D(11), + I2 => \^p_71_out\(5), + I3 => D(10), + O => \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_5_n_0\ ); -\awaddr_reg[5]\: unisim.vcomponents.FDRE +\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, + C => m_axi_mm2s_aclk, CE => '1', - D => s_axi_lite_awaddr(3), - Q => awaddr(5), + D => \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_1_n_0\, + Q => irqthresh_wren_i, R => SR(0) ); -\awaddr_reg[6]\: unisim.vcomponents.FDRE +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_2\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"FFEF" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_awaddr(4), - Q => awaddr(6), - R => SR(0) + I0 => \^soft_reset_d1_reg\, + I1 => dma_err, + I2 => \^p_71_out\(0), + I3 => mm2s_halt, + O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ ); -\awaddr_reg[7]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt[6]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFFFFFFFFFFFB" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_awaddr(5), - Q => awaddr(7), - R => SR(0) + I0 => \^gen_include_mm2s.gen_ch1_delay_interrupt.gen_ch1_fast_counter.ch1_dly_fast_cnt_reg[6]_0\, + I1 => ch1_delay_cnt_en, + I2 => p_24_out, + I3 => irqdelay_wren_i, + I4 => \^gen_include_mm2s.gen_ch1_delay_interrupt.gen_ch1_fast_counter.ch1_dly_fast_cnt_reg[6]\, + I5 => p_17_out, + O => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]_1\(0) ); -awready_out_i_reg: unisim.vcomponents.FDRE +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"4454" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => \sig_awvalid_detected__0\, - Q => \^s_axi_lite_awready\, - R => SR(0) + I0 => \^gen_include_mm2s.gen_ch1_delay_interrupt.gen_ch1_fast_counter.ch1_dly_fast_cnt_reg[6]_0\, + I1 => p_50_out, + I2 => ch1_delay_cnt_en, + I3 => p_17_out, + O => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg\ ); -awvalid_reg: unisim.vcomponents.FDRE +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_i_2\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"FE" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_awvalid, - Q => awvalid, - R => SR(0) + I0 => ch1_dly_irq_set, + I1 => \^ch1_delay_zero\, + I2 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_i_3_n_0\, + O => \^gen_include_mm2s.gen_ch1_delay_interrupt.gen_ch1_fast_counter.ch1_dly_fast_cnt_reg[6]_0\ ); -\axi2ip_rdaddr_captured_reg[2]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_i_3\: unisim.vcomponents.LUT5 generic map( - INIT => '0' + INIT => X"FFFBFFFF" ) port map ( - C => s_axi_lite_aclk, - CE => \sig_arvalid_detected__0\, - D => p_2_in(0), - Q => \axi2ip_rdaddr_captured_reg_n_0_[2]\, - R => SR(0) + I0 => mask_fsync_out_i, + I1 => p_47_out, + I2 => \^dly_irq_reg_0\, + I3 => \^s_axis_cmd_tvalid_reg\, + I4 => prmry_resetn_i_reg, + O => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_i_3_n_0\ ); -\axi2ip_rdaddr_captured_reg[3]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count[7]_i_3\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"FFFE" ) port map ( - C => s_axi_lite_aclk, - CE => \sig_arvalid_detected__0\, - D => p_2_in(1), - Q => \axi2ip_rdaddr_captured_reg_n_0_[3]\, - R => SR(0) + I0 => p_17_out, + I1 => \^gen_include_mm2s.gen_ch1_delay_interrupt.gen_ch1_fast_counter.ch1_dly_fast_cnt_reg[6]\, + I2 => irqdelay_wren_i, + I3 => p_24_out, + O => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0]\ ); -\axi2ip_rdaddr_captured_reg[4]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_2\: unisim.vcomponents.LUT5 generic map( - INIT => '0' + INIT => X"00010000" ) port map ( - C => s_axi_lite_aclk, - CE => \sig_arvalid_detected__0\, - D => p_2_in(2), - Q => \axi2ip_rdaddr_captured_reg_n_0_[4]\, - R => SR(0) + I0 => \^p_71_out\(15), + I1 => \^p_71_out\(16), + I2 => \^p_71_out\(17), + I3 => \^p_71_out\(18), + I4 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_5_n_0\, + O => \^ch1_delay_zero\ ); -\axi2ip_rdaddr_captured_reg[5]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_5\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"0001" ) port map ( - C => s_axi_lite_aclk, - CE => \sig_arvalid_detected__0\, - D => p_2_in(3), - Q => \axi2ip_rdaddr_captured_reg_n_0_[5]\, - R => SR(0) + I0 => \^p_71_out\(12), + I1 => \^p_71_out\(11), + I2 => \^p_71_out\(14), + I3 => \^p_71_out\(13), + O => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_i_5_n_0\ ); -\axi2ip_rdaddr_captured_reg[6]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFFFFFFFF88F8" ) port map ( - C => s_axi_lite_aclk, - CE => \sig_arvalid_detected__0\, - D => p_2_in(4), - Q => \axi2ip_rdaddr_captured_reg_n_0_[6]\, - R => SR(0) + I0 => \^q\(3), + I1 => ch1_dly_irq_set, + I2 => p_50_out, + I3 => p_45_out, + I4 => irqthresh_wren_i, + I5 => \^gen_include_mm2s.gen_ch1_delay_interrupt.gen_ch1_fast_counter.ch1_dly_fast_cnt_reg[6]\, + O => p_13_out ); -\axi2ip_rdaddr_captured_reg[7]\: unisim.vcomponents.FDRE +\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_2\: unisim.vcomponents.LUT5 generic map( - INIT => '0' + INIT => X"FFFFFEEE" ) port map ( - C => s_axi_lite_aclk, - CE => \sig_arvalid_detected__0\, - D => p_2_in(5), - Q => \axi2ip_rdaddr_captured_reg_n_0_[7]\, - R => SR(0) + I0 => \^gen_include_mm2s.gen_ch1_delay_interrupt.gen_ch1_fast_counter.ch1_dly_fast_cnt_reg[6]\, + I1 => irqthresh_wren_i, + I2 => ch1_dly_irq_set, + I3 => \^q\(3), + I4 => p_50_out, + O => E(0) ); -\axi2ip_wraddr_captured_reg[2]\: unisim.vcomponents.FDRE +\GEN_NOSYNCEN_BIT.dmacr_i_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => \sig_awvalid_detected__0\, - D => awaddr(2), - Q => axi2ip_wraddr_captured(2), + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(0), + D => D(7), + Q => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]\, R => SR(0) ); -\axi2ip_wraddr_captured_reg[3]\: unisim.vcomponents.FDRE +\MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"DFDD" ) port map ( - C => s_axi_lite_aclk, - CE => \sig_awvalid_detected__0\, - D => awaddr(3), - Q => axi2ip_wraddr_captured(3), - R => SR(0) + I0 => prmry_resetn_i_reg, + I1 => \^s_axis_cmd_tvalid_reg\, + I2 => initial_frame, + I3 => \^p_71_out\(1), + O => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]\(0) ); -\axi2ip_wraddr_captured_reg[4]\: unisim.vcomponents.FDRE +\MM2S_ERR_FOR_IRQ.frm_store_i[4]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"01" ) port map ( - C => s_axi_lite_aclk, - CE => \sig_awvalid_detected__0\, - D => awaddr(4), - Q => axi2ip_wraddr_captured(4), - R => SR(0) + I0 => \^err_d1_reg_1\, + I1 => \^err_d1_reg_2\, + I2 => \^err_d1_reg_0\, + O => p_1_in ); -\axi2ip_wraddr_captured_reg[5]\: unisim.vcomponents.FDRE +\MM2S_ERR_FOR_IRQ.frm_store_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => \sig_awvalid_detected__0\, - D => awaddr(5), - Q => axi2ip_wraddr_captured(5), + C => m_axi_mm2s_aclk, + CE => p_1_in, + D => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0\(0), + Q => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\(0), R => SR(0) ); -\axi2ip_wraddr_captured_reg[6]\: unisim.vcomponents.FDRE +\MM2S_ERR_FOR_IRQ.frm_store_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => \sig_awvalid_detected__0\, - D => awaddr(6), - Q => axi2ip_wraddr_captured(6), + C => m_axi_mm2s_aclk, + CE => p_1_in, + D => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0\(1), + Q => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\(1), R => SR(0) ); -\axi2ip_wraddr_captured_reg[7]\: unisim.vcomponents.FDRE +\MM2S_ERR_FOR_IRQ.frm_store_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => \sig_awvalid_detected__0\, - D => awaddr(7), - Q => axi2ip_wraddr_captured(7), + C => m_axi_mm2s_aclk, + CE => p_1_in, + D => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0\(2), + Q => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\(2), R => SR(0) ); -bvalid_out_i_i_1: unisim.vcomponents.LUT4 +\MM2S_ERR_FOR_IRQ.frm_store_i_reg[3]\: unisim.vcomponents.FDRE generic map( - INIT => X"0C88" + INIT => '0' ) port map ( - I0 => \^s_axi_lite_wready\, - I1 => s_axi_lite_resetn, - I2 => s_axi_lite_bready, - I3 => \^s_axi_lite_bvalid\, - O => bvalid_out_i_i_1_n_0 + C => m_axi_mm2s_aclk, + CE => p_1_in, + D => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0\(3), + Q => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\(3), + R => SR(0) ); -bvalid_out_i_reg: unisim.vcomponents.FDRE +\MM2S_ERR_FOR_IRQ.frm_store_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => bvalid_out_i_i_1_n_0, - Q => \^s_axi_lite_bvalid\, - R => '0' + C => m_axi_mm2s_aclk, + CE => p_1_in, + D => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0\(4), + Q => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\(4), + R => SR(0) ); -\dmacr_i[1]_i_2\: unisim.vcomponents.LUT2 +\M_GEN_DMACR_REGISTER.dmacr_i_reg[12]\: unisim.vcomponents.FDRE generic map( - INIT => X"1" + INIT => '0' ) port map ( - I0 => axi2ip_wraddr_captured_mm2s_cdc_tig(6), - I1 => axi2ip_wraddr_captured_mm2s_cdc_tig(5), - O => \dmacr_i[1]_i_2_n_0\ + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(0), + D => D(4), + Q => \^q\(2), + R => SR(0) ); -i_0: unisim.vcomponents.LUT1 +\M_GEN_DMACR_REGISTER.dmacr_i_reg[13]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(31) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(0), + D => D(5), + Q => \^q\(3), + R => SR(0) ); -i_1: unisim.vcomponents.LUT1 +\M_GEN_DMACR_REGISTER.dmacr_i_reg[14]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(30) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(0), + D => D(6), + Q => \^q\(4), + R => SR(0) ); -i_10: unisim.vcomponents.LUT1 +\M_GEN_DMACR_REGISTER.dmacr_i_reg[4]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(21) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(0), + D => D(1), + Q => \^p_71_out\(2), + R => SR(0) ); -i_11: unisim.vcomponents.LUT1 +\M_GEN_DMACR_REGISTER.dmacr_i_reg[5]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(20) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(0), + D => D(2), + Q => \^q\(0), + R => SR(0) ); -i_12: unisim.vcomponents.LUT1 +\M_GEN_DMACR_REGISTER.dmacr_i_reg[6]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(19) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(0), + D => D(3), + Q => \^q\(1), + R => SR(0) ); -i_13: unisim.vcomponents.LUT1 +dly_irq_reg: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(18) + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13]\, + Q => \^dly_irq_reg_0\, + R => SR(0) ); -i_14: unisim.vcomponents.LUT1 +dma_decerr_reg: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(17) + C => m_axi_mm2s_aclk, + CE => '1', + D => decerr_i_reg, + Q => \^err_d1_reg_2\, + R => SR(0) ); -i_15: unisim.vcomponents.LUT1 +dma_interr_reg: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(16) + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4]\, + Q => \^err_d1_reg_0\, + R => SR(0) ); -i_16: unisim.vcomponents.LUT1 +dma_slverr_reg: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(15) + C => m_axi_mm2s_aclk, + CE => '1', + D => slverr_i_reg, + Q => \^err_d1_reg_1\, + R => SR(0) ); -i_17: unisim.vcomponents.LUT1 +\dmacr_i[0]_i_2\: unisim.vcomponents.LUT3 generic map( - INIT => X"2" + INIT => X"F8" ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(14) + I0 => mm2s_ioc_irq_set, + I1 => \^p_71_out\(2), + I2 => \^soft_reset_d1_reg\, + O => \dmacr_i_reg[0]_0\ ); -i_18: unisim.vcomponents.LUT1 +\dmacr_i_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(13) + C => m_axi_mm2s_aclk, + CE => '1', + D => dmacr_i(0), + Q => \^p_71_out\(0), + R => '0' ); -i_19: unisim.vcomponents.LUT1 +\dmacr_i_reg[1]\: unisim.vcomponents.FDSE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(12) + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(0), + D => D(0), + Q => \^p_71_out\(1), + S => SR(0) ); -i_2: unisim.vcomponents.LUT1 +\dmacr_i_reg[2]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(29) + C => m_axi_mm2s_aclk, + CE => '1', + D => \dmacr_i_reg[2]_0\, + Q => \^soft_reset_d1_reg\, + R => '0' ); -i_20: unisim.vcomponents.LUT1 +err_d1_i_1: unisim.vcomponents.LUT3 generic map( - INIT => X"2" + INIT => X"FE" ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(11) + I0 => \^err_d1_reg_0\, + I1 => \^err_d1_reg_2\, + I2 => \^err_d1_reg_1\, + O => err ); -i_21: unisim.vcomponents.LUT1 +err_d1_reg: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(10) + C => m_axi_mm2s_aclk, + CE => '1', + D => err, + Q => err_d1, + R => SR(0) ); -i_22: unisim.vcomponents.LUT1 +err_irq_i_1: unisim.vcomponents.LUT5 generic map( - INIT => X"2" + INIT => X"5DFF0C0C" ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(9) + I0 => D(6), + I1 => err, + I2 => err_d1, + I3 => mm2s_axi2ip_wrce(1), + I4 => \^err_irq_reg_0\, + O => err_irq_i_1_n_0 ); -i_23: unisim.vcomponents.LUT1 +err_irq_reg: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(8) + C => m_axi_mm2s_aclk, + CE => '1', + D => err_irq_i_1_n_0, + Q => \^err_irq_reg_0\, + R => SR(0) ); -i_24: unisim.vcomponents.LUT1 +halted_reg: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(7) + C => m_axi_mm2s_aclk, + CE => '1', + D => halted_clr_reg, + Q => \^s_axis_cmd_tvalid_reg\, + R => '0' ); -i_25: unisim.vcomponents.LUT1 +introut_i_1: unisim.vcomponents.LUT3 generic map( - INIT => X"2" + INIT => X"08" ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(6) + I0 => introut01_out, + I1 => prmry_resetn_i_reg, + I2 => \^soft_reset_d1_reg\, + O => introut_i_1_n_0 ); -i_26: unisim.vcomponents.LUT1 +introut_i_2: unisim.vcomponents.LUT6 generic map( - INIT => X"2" + INIT => X"FFFFF888F888F888" ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(5) + I0 => \^err_irq_reg_0\, + I1 => \^q\(4), + I2 => \^ioc_irq_reg_0\, + I3 => \^q\(2), + I4 => \^q\(3), + I5 => \^dly_irq_reg_0\, + O => introut01_out ); -i_27: unisim.vcomponents.LUT1 - generic map( - INIT => X"2" - ) - port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(4) +introut_reg: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => introut_i_1_n_0, + Q => p_78_out, + R => '0' ); -i_28: unisim.vcomponents.LUT1 +ioc_irq_reg: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(3) + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12]\, + Q => \^ioc_irq_reg_0\, + R => SR(0) ); -i_29: unisim.vcomponents.LUT1 +reset_counts_reg: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(2) + C => m_axi_mm2s_aclk, + CE => '1', + D => reset_counts_reg_0, + Q => \^gen_include_mm2s.gen_ch1_delay_interrupt.gen_ch1_fast_counter.ch1_dly_fast_cnt_reg[6]\, + R => '0' ); -i_3: unisim.vcomponents.LUT1 +\s_axis_cmd_tdata[63]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"B" ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(28) + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => prmry_resetn_i_reg, + O => s_axis_cmd_tvalid_reg_0(0) ); -i_30: unisim.vcomponents.LUT1 +s_soft_reset_i_i_1: unisim.vcomponents.LUT4 generic map( - INIT => X"2" + INIT => X"A800" ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(1) + I0 => \^soft_reset_d1_reg\, + I1 => mm2s_halt_cmplt, + I2 => halt_reset, + I3 => prmry_in, + O => s_soft_reset_i0 ); -i_31: unisim.vcomponents.LUT1 +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_axi_vdma_register__parameterized0\ is + port ( + s2mm_dmacr : out STD_LOGIC_VECTOR ( 22 downto 0 ); + soft_reset_d1_reg : out STD_LOGIC; + reset_counts : out STD_LOGIC; + irqdelay_wren_i : out STD_LOGIC; + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : out STD_LOGIC; + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_0\ : out STD_LOGIC; + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_1\ : out STD_LOGIC; + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_2\ : out STD_LOGIC; + \GEN_FOR_FLUSH.fsize_err_reg_0\ : out STD_LOGIC; + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_3\ : out STD_LOGIC; + err_d1_reg_0 : out STD_LOGIC; + ioc_irq_reg_0 : out STD_LOGIC; + dly_irq_reg_0 : out STD_LOGIC; + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_4\ : out STD_LOGIC; + err_d1_reg_1 : out STD_LOGIC; + s2mm_ip2axi_introut : out STD_LOGIC; + s_soft_reset_i0 : out STD_LOGIC; + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6]\ : out STD_LOGIC; + ch2_delay_zero : out STD_LOGIC; + p_6_out : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 6 downto 0 ); + \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg_0\ : out STD_LOGIC; + \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg_0\ : out STD_LOGIC; + err_d1_reg_2 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + err_irq_reg_0 : out STD_LOGIC; + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axis_cmd_tvalid_reg : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + m_axi_s2mm_aclk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + s2mm_axi2ip_wrce : in STD_LOGIC_VECTOR ( 2 downto 0 ); + D : in STD_LOGIC_VECTOR ( 30 downto 0 ); + \dmacr_i_reg[2]_0\ : in STD_LOGIC; + reset_counts_reg_0 : in STD_LOGIC; + p_15_out : in STD_LOGIC; + p_14_out : in STD_LOGIC; + halted_clr_reg : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4]\ : in STD_LOGIC; + slverr_i_reg : in STD_LOGIC; + decerr_i_reg : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[7]\ : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[8]\ : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[11]\ : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[12]\ : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[13]\ : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[15]\ : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4]_0\ : in STD_LOGIC; + s2mm_halt_cmplt : in STD_LOGIC; + halt_reset : in STD_LOGIC; + prmry_in : in STD_LOGIC; + prmry_resetn_i_reg : in STD_LOGIC; + ch2_dly_irq_set : in STD_LOGIC; + s2mm_tstvect_fsync : in STD_LOGIC; + s2mm_valid_frame_sync : in STD_LOGIC; + s2mm_ioc_irq_set : in STD_LOGIC; + s2mm_valid_video_prmtrs : in STD_LOGIC; + mask_fsync_out_i : in STD_LOGIC; + s2mm_stop : in STD_LOGIC; + num_fstore_minus1 : in STD_LOGIC_VECTOR ( 0 to 0 ); + initial_frame : in STD_LOGIC; + ch2_delay_cnt_en : in STD_LOGIC; + s2mm_cdc2dmac_fsync : in STD_LOGIC; + s2mm_packet_sof : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_axi_vdma_register__parameterized0\ : entity is "axi_vdma_register"; +end \Arty_Z7_20_axi_vdma_0_0_axi_vdma_register__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_axi_vdma_register__parameterized0\ is + signal \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_6_n_0\ : STD_LOGIC; + signal \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_6_n_0\ : STD_LOGIC; + signal \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\ : STD_LOGIC; + signal \^gen_for_flush.fsize_err_reg_0\ : STD_LOGIC; + signal \^gen_include_s2mm.gen_ch2_delay_interrupt.gen_ch2_fast_counter.ch2_dly_fast_cnt_reg[6]\ : STD_LOGIC; + signal \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_5_n_0\ : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal \S2MM_ERR_FOR_IRQ.frm_store_i[4]_i_1_n_0\ : STD_LOGIC; + signal \^s2mm_err_for_irq.frm_store_i_reg[0]_0\ : STD_LOGIC; + signal \^s2mm_err_for_irq.frm_store_i_reg[0]_1\ : STD_LOGIC; + signal \^s2mm_err_for_irq.frm_store_i_reg[0]_2\ : STD_LOGIC; + signal \^s2mm_err_for_irq.frm_store_i_reg[0]_3\ : STD_LOGIC; + signal \^s2mm_err_for_irq.frm_store_i_reg[0]_4\ : STD_LOGIC; + signal \^ch2_delay_zero\ : STD_LOGIC; + signal \^dly_irq_reg_0\ : STD_LOGIC; + signal dmacr_i : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \dmacr_i[0]_i_2__0_n_0\ : STD_LOGIC; + signal err : STD_LOGIC; + signal err_d1 : STD_LOGIC; + signal err_d1_i_2_n_0 : STD_LOGIC; + signal \^err_d1_reg_0\ : STD_LOGIC; + signal \^err_d1_reg_1\ : STD_LOGIC; + signal \^err_d1_reg_2\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \err_irq_i_1__0_n_0\ : STD_LOGIC; + signal \^err_irq_reg_0\ : STD_LOGIC; + signal introut07_out : STD_LOGIC; + signal \introut_i_1__0_n_0\ : STD_LOGIC; + signal \^ioc_irq_reg_0\ : STD_LOGIC; + signal \^irqdelay_wren_i\ : STD_LOGIC; + signal irqthresh_wren_i : STD_LOGIC; + signal \^reset_counts\ : STD_LOGIC; + signal s2mm_dlyirq_dsble : STD_LOGIC; + signal \^s2mm_dmacr\ : STD_LOGIC_VECTOR ( 22 downto 0 ); + signal \^soft_reset_d1_reg\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_1\ : label is "soft_lutpair86"; + attribute SOFT_HLUTNM of \dmacr_i[0]_i_2__0\ : label is "soft_lutpair87"; + attribute SOFT_HLUTNM of \introut_i_1__0\ : label is "soft_lutpair87"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[63]_i_1__0\ : label is "soft_lutpair86"; +begin + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ <= \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\; + \GEN_FOR_FLUSH.fsize_err_reg_0\ <= \^gen_for_flush.fsize_err_reg_0\; + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6]\ <= \^gen_include_s2mm.gen_ch2_delay_interrupt.gen_ch2_fast_counter.ch2_dly_fast_cnt_reg[6]\; + Q(6 downto 0) <= \^q\(6 downto 0); + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_0\ <= \^s2mm_err_for_irq.frm_store_i_reg[0]_0\; + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_1\ <= \^s2mm_err_for_irq.frm_store_i_reg[0]_1\; + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_2\ <= \^s2mm_err_for_irq.frm_store_i_reg[0]_2\; + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_3\ <= \^s2mm_err_for_irq.frm_store_i_reg[0]_3\; + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_4\ <= \^s2mm_err_for_irq.frm_store_i_reg[0]_4\; + ch2_delay_zero <= \^ch2_delay_zero\; + dly_irq_reg_0 <= \^dly_irq_reg_0\; + err_d1_reg_0 <= \^err_d1_reg_0\; + err_d1_reg_1 <= \^err_d1_reg_1\; + err_d1_reg_2(3 downto 0) <= \^err_d1_reg_2\(3 downto 0); + err_irq_reg_0 <= \^err_irq_reg_0\; + ioc_irq_reg_0 <= \^ioc_irq_reg_0\; + irqdelay_wren_i <= \^irqdelay_wren_i\; + reset_counts <= \^reset_counts\; + s2mm_dmacr(22 downto 0) <= \^s2mm_dmacr\(22 downto 0); + soft_reset_d1_reg <= \^soft_reset_d1_reg\; +\DMA_IRQ_MASK_GEN.dma_irq_mask_i_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(0) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(2), + D => D(0), + Q => \^err_d1_reg_2\(0), + R => SR(0) ); -i_32: unisim.vcomponents.LUT1 +\DMA_IRQ_MASK_GEN.dma_irq_mask_i_reg[1]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => axi2ip_rdaddr_captured_s2mm_cdc_tig(7) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(2), + D => D(1), + Q => \^err_d1_reg_2\(1), + R => SR(0) ); -i_33: unisim.vcomponents.LUT1 +\DMA_IRQ_MASK_GEN.dma_irq_mask_i_reg[2]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => axi2ip_rdaddr_captured_s2mm_cdc_tig(6) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(2), + D => D(2), + Q => \^err_d1_reg_2\(2), + R => SR(0) ); -i_34: unisim.vcomponents.LUT1 +\DMA_IRQ_MASK_GEN.dma_irq_mask_i_reg[3]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => axi2ip_rdaddr_captured_s2mm_cdc_tig(5) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(2), + D => D(3), + Q => \^err_d1_reg_2\(3), + R => SR(0) ); -i_35: unisim.vcomponents.LUT1 +\DM_GEN_SYNCEN_BIT.dmacr_i_reg[15]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => axi2ip_rdaddr_captured_s2mm_cdc_tig(4) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(14), + Q => \^s2mm_dmacr\(6), + R => SR(0) ); -i_36: unisim.vcomponents.LUT1 +\DM_GEN_SYNCEN_BIT.dmacr_i_reg[3]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => axi2ip_rdaddr_captured_s2mm_cdc_tig(3) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(3), + Q => \^s2mm_dmacr\(2), + R => SR(0) ); -i_37: unisim.vcomponents.LUT1 +\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"2" + INIT => X"DFDFFFDF" ) port map ( - I0 => '0', - O => axi2ip_rdaddr_captured_s2mm_cdc_tig(2) + I0 => prmry_resetn_i_reg, + I1 => \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\, + I2 => num_fstore_minus1(0), + I3 => \^s2mm_dmacr\(1), + I4 => initial_frame, + O => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(0) ); -i_38: unisim.vcomponents.LUT1 +\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[24]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => axi2ip_wraddr_captured_s2mm_cdc_tig(7) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(23), + Q => \^s2mm_dmacr\(15), + R => SR(0) ); -i_39: unisim.vcomponents.LUT1 +\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[25]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => axi2ip_wraddr_captured_s2mm_cdc_tig(6) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(24), + Q => \^s2mm_dmacr\(16), + R => SR(0) ); -i_4: unisim.vcomponents.LUT1 +\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[26]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(27) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(25), + Q => \^s2mm_dmacr\(17), + R => SR(0) ); -i_40: unisim.vcomponents.LUT1 +\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[27]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => axi2ip_wraddr_captured_s2mm_cdc_tig(5) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(26), + Q => \^s2mm_dmacr\(18), + R => SR(0) ); -i_41: unisim.vcomponents.LUT1 +\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[28]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => axi2ip_wraddr_captured_s2mm_cdc_tig(4) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(27), + Q => \^s2mm_dmacr\(19), + R => SR(0) ); -i_42: unisim.vcomponents.LUT1 +\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[29]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => axi2ip_wraddr_captured_s2mm_cdc_tig(3) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(28), + Q => \^s2mm_dmacr\(20), + R => SR(0) ); -i_43: unisim.vcomponents.LUT1 +\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[30]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => axi2ip_wraddr_captured_s2mm_cdc_tig(2) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(29), + Q => \^s2mm_dmacr\(21), + R => SR(0) ); -i_44: unisim.vcomponents.LUT1 +\ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(31) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(30), + Q => \^s2mm_dmacr\(22), + R => SR(0) ); -i_45: unisim.vcomponents.LUT1 +\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_5__0\: unisim.vcomponents.LUT6 generic map( - INIT => X"2" + INIT => X"8CC8CCCCCCCC8CC8" ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(30) + I0 => \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_6_n_0\, + I1 => s2mm_axi2ip_wrce(0), + I2 => \^s2mm_dmacr\(22), + I3 => D(30), + I4 => \^s2mm_dmacr\(21), + I5 => D(29), + O => \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg_0\ ); -i_46: unisim.vcomponents.LUT1 +\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(29) + I0 => \^s2mm_dmacr\(20), + I1 => D(28), + O => \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_6_n_0\ ); -i_47: unisim.vcomponents.LUT1 +\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(28) + C => m_axi_s2mm_aclk, + CE => '1', + D => p_15_out, + Q => \^irqdelay_wren_i\, + R => SR(0) ); -i_48: unisim.vcomponents.LUT1 +\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[16]\: unisim.vcomponents.FDSE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(27) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(15), + Q => \^s2mm_dmacr\(7), + S => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18]\(0) ); -i_49: unisim.vcomponents.LUT1 +\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[17]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(26) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(16), + Q => \^s2mm_dmacr\(8), + R => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18]\(0) ); -i_5: unisim.vcomponents.LUT1 +\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[18]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(26) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(17), + Q => \^s2mm_dmacr\(9), + R => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18]\(0) ); -i_50: unisim.vcomponents.LUT1 +\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[19]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(25) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(18), + Q => \^s2mm_dmacr\(10), + R => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18]\(0) ); -i_51: unisim.vcomponents.LUT1 +\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[20]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(24) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(19), + Q => \^s2mm_dmacr\(11), + R => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18]\(0) ); -i_52: unisim.vcomponents.LUT1 +\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(23) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(20), + Q => \^s2mm_dmacr\(12), + R => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18]\(0) ); -i_53: unisim.vcomponents.LUT1 +\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[22]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(22) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(21), + Q => \^s2mm_dmacr\(13), + R => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18]\(0) ); -i_54: unisim.vcomponents.LUT1 +\ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[23]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(21) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(22), + Q => \^s2mm_dmacr\(14), + R => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18]\(0) ); -i_55: unisim.vcomponents.LUT1 +\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_5__0\: unisim.vcomponents.LUT6 generic map( - INIT => X"2" + INIT => X"8CC8CCCCCCCC8CC8" ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(20) + I0 => \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_6_n_0\, + I1 => s2mm_axi2ip_wrce(0), + I2 => \^s2mm_dmacr\(14), + I3 => D(22), + I4 => \^s2mm_dmacr\(13), + I5 => D(21), + O => \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg_0\ ); -i_56: unisim.vcomponents.LUT1 +\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(19) + I0 => \^s2mm_dmacr\(12), + I1 => D(20), + O => \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_6_n_0\ ); -i_57: unisim.vcomponents.LUT1 +\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(18) + C => m_axi_s2mm_aclk, + CE => '1', + D => p_14_out, + Q => irqthresh_wren_i, + R => SR(0) ); -i_58: unisim.vcomponents.LUT1 +\GEN_FOR_FLUSH.fsize_err_reg\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(17) + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[7]\, + Q => \^gen_for_flush.fsize_err_reg_0\, + R => SR(0) ); -i_59: unisim.vcomponents.LUT1 +\GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(16) + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[11]\, + Q => \^err_d1_reg_0\, + R => SR(0) ); -i_6: unisim.vcomponents.LUT1 +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt[6]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"2" + INIT => X"FFFFFFFFFFFFFFFB" ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(25) + I0 => \^gen_include_s2mm.gen_ch2_delay_interrupt.gen_ch2_fast_counter.ch2_dly_fast_cnt_reg[6]\, + I1 => ch2_delay_cnt_en, + I2 => \^irqdelay_wren_i\, + I3 => s2mm_cdc2dmac_fsync, + I4 => \^reset_counts\, + I5 => s2mm_packet_sof, + O => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6]_0\(0) ); -i_60: unisim.vcomponents.LUT1 +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_i_2\: unisim.vcomponents.LUT4 generic map( - INIT => X"2" + INIT => X"FFEF" ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(15) + I0 => \^ch2_delay_zero\, + I1 => s2mm_dlyirq_dsble, + I2 => prmry_resetn_i_reg, + I3 => ch2_dly_irq_set, + O => \^gen_include_s2mm.gen_ch2_delay_interrupt.gen_ch2_fast_counter.ch2_dly_fast_cnt_reg[6]\ ); -i_61: unisim.vcomponents.LUT1 +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_i_3\: unisim.vcomponents.LUT4 generic map( - INIT => X"2" + INIT => X"FFEF" ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(14) + I0 => \^dly_irq_reg_0\, + I1 => \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\, + I2 => s2mm_valid_video_prmtrs, + I3 => mask_fsync_out_i, + O => s2mm_dlyirq_dsble ); -i_62: unisim.vcomponents.LUT1 +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_2\: unisim.vcomponents.LUT5 generic map( - INIT => X"2" + INIT => X"00010000" ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(13) + I0 => \^s2mm_dmacr\(19), + I1 => \^s2mm_dmacr\(20), + I2 => \^s2mm_dmacr\(21), + I3 => \^s2mm_dmacr\(22), + I4 => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_5_n_0\, + O => \^ch2_delay_zero\ ); -i_63: unisim.vcomponents.LUT1 +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_5\: unisim.vcomponents.LUT4 generic map( - INIT => X"2" + INIT => X"0001" ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(12) + I0 => \^s2mm_dmacr\(16), + I1 => \^s2mm_dmacr\(15), + I2 => \^s2mm_dmacr\(18), + I3 => \^s2mm_dmacr\(17), + O => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_dly_irq_set_i_i_5_n_0\ ); -i_64: unisim.vcomponents.LUT1 +\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"2" + INIT => X"FFFFFFFFFFFF88F8" ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(11) + I0 => \^q\(5), + I1 => ch2_dly_irq_set, + I2 => s2mm_tstvect_fsync, + I3 => s2mm_valid_frame_sync, + I4 => \^reset_counts\, + I5 => irqthresh_wren_i, + O => p_6_out ); -i_65: unisim.vcomponents.LUT1 +\GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[10]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(10) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(9), + Q => \^q\(2), + R => SR(0) ); -i_66: unisim.vcomponents.LUT1 +\GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[11]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(9) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(10), + Q => \^q\(3), + R => SR(0) ); -i_67: unisim.vcomponents.LUT1 +\GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[12]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(8) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(11), + Q => \^q\(4), + R => SR(0) ); -i_68: unisim.vcomponents.LUT1 +\GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[13]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(7) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(12), + Q => \^q\(5), + R => SR(0) ); -i_69: unisim.vcomponents.LUT1 +\GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(6) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(13), + Q => \^q\(6), + R => SR(0) ); -i_7: unisim.vcomponents.LUT1 +\GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[4]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(24) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(4), + Q => \^s2mm_dmacr\(3), + R => SR(0) ); -i_70: unisim.vcomponents.LUT1 +\GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[5]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(5) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(5), + Q => \^s2mm_dmacr\(4), + R => SR(0) ); -i_71: unisim.vcomponents.LUT1 +\GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[6]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(4) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(6), + Q => \^s2mm_dmacr\(5), + R => SR(0) ); -i_72: unisim.vcomponents.LUT1 +\GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[8]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(3) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(7), + Q => \^q\(0), + R => SR(0) ); -i_73: unisim.vcomponents.LUT1 +\GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[9]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(2) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(8), + Q => \^q\(1), + R => SR(0) ); -i_74: unisim.vcomponents.LUT1 +\S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(1) + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4]_0\, + Q => \^err_d1_reg_1\, + R => SR(0) ); -i_75: unisim.vcomponents.LUT1 +\S2MM_ERR_FOR_IRQ.frm_store_i[4]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"2" + INIT => X"00000001" ) port map ( - I0 => '0', - O => s2mm_axi2ip_wrdata_cdc_tig(0) + I0 => \^s2mm_err_for_irq.frm_store_i_reg[0]_0\, + I1 => \^s2mm_err_for_irq.frm_store_i_reg[0]_3\, + I2 => \^s2mm_err_for_irq.frm_store_i_reg[0]_4\, + I3 => \^s2mm_err_for_irq.frm_store_i_reg[0]_2\, + I4 => \^s2mm_err_for_irq.frm_store_i_reg[0]_1\, + O => \S2MM_ERR_FOR_IRQ.frm_store_i[4]_i_1_n_0\ ); -i_8: unisim.vcomponents.LUT1 +\S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(23) + C => m_axi_s2mm_aclk, + CE => \S2MM_ERR_FOR_IRQ.frm_store_i[4]_i_1_n_0\, + D => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]_0\(0), + Q => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4]\(0), + R => SR(0) ); -i_9: unisim.vcomponents.LUT1 +\S2MM_ERR_FOR_IRQ.frm_store_i_reg[1]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => ip2axi_rddata_captured_s2mm_cdc_tig(22) + C => m_axi_s2mm_aclk, + CE => \S2MM_ERR_FOR_IRQ.frm_store_i[4]_i_1_n_0\, + D => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]_0\(1), + Q => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4]\(1), + R => SR(0) ); -ip2axi_rddata_int_inferred_i_1: unisim.vcomponents.LUT5 +\S2MM_ERR_FOR_IRQ.frm_store_i_reg[2]\: unisim.vcomponents.FDRE generic map( - INIT => X"00004540" + INIT => '0' ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => ip2axi_rddata_int_inferred_i_33_n_0, - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I3 => ip2axi_rddata_int_inferred_i_34_n_0, - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(31) + C => m_axi_s2mm_aclk, + CE => \S2MM_ERR_FOR_IRQ.frm_store_i[4]_i_1_n_0\, + D => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]_0\(2), + Q => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4]\(2), + R => SR(0) ); -ip2axi_rddata_int_inferred_i_10: unisim.vcomponents.LUT5 +\S2MM_ERR_FOR_IRQ.frm_store_i_reg[3]\: unisim.vcomponents.FDRE generic map( - INIT => X"00004540" + INIT => '0' ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => ip2axi_rddata_int_inferred_i_51_n_0, - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I3 => ip2axi_rddata_int_inferred_i_52_n_0, - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(22) + C => m_axi_s2mm_aclk, + CE => \S2MM_ERR_FOR_IRQ.frm_store_i[4]_i_1_n_0\, + D => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]_0\(3), + Q => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4]\(3), + R => SR(0) ); -ip2axi_rddata_int_inferred_i_11: unisim.vcomponents.LUT5 +\S2MM_ERR_FOR_IRQ.frm_store_i_reg[4]\: unisim.vcomponents.FDRE generic map( - INIT => X"00004540" + INIT => '0' ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => ip2axi_rddata_int_inferred_i_53_n_0, - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I3 => ip2axi_rddata_int_inferred_i_54_n_0, - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(21) + C => m_axi_s2mm_aclk, + CE => \S2MM_ERR_FOR_IRQ.frm_store_i[4]_i_1_n_0\, + D => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]_0\(4), + Q => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4]\(4), + R => SR(0) ); -ip2axi_rddata_int_inferred_i_12: unisim.vcomponents.LUT5 +dly_irq_reg: unisim.vcomponents.FDRE generic map( - INIT => X"00004540" + INIT => '0' ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => ip2axi_rddata_int_inferred_i_55_n_0, - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I3 => ip2axi_rddata_int_inferred_i_56_n_0, - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(20) + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[13]\, + Q => \^dly_irq_reg_0\, + R => SR(0) ); -ip2axi_rddata_int_inferred_i_13: unisim.vcomponents.LUT5 +dma_decerr_reg: unisim.vcomponents.FDRE generic map( - INIT => X"00004540" + INIT => '0' ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => ip2axi_rddata_int_inferred_i_57_n_0, - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I3 => ip2axi_rddata_int_inferred_i_58_n_0, - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(19) + C => m_axi_s2mm_aclk, + CE => '1', + D => decerr_i_reg, + Q => \^s2mm_err_for_irq.frm_store_i_reg[0]_2\, + R => SR(0) ); -ip2axi_rddata_int_inferred_i_14: unisim.vcomponents.LUT5 +dma_interr_reg: unisim.vcomponents.FDRE generic map( - INIT => X"00004540" + INIT => '0' ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => ip2axi_rddata_int_inferred_i_59_n_0, - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I3 => ip2axi_rddata_int_inferred_i_60_n_0, - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(18) + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4]\, + Q => \^s2mm_err_for_irq.frm_store_i_reg[0]_0\, + R => SR(0) ); -ip2axi_rddata_int_inferred_i_15: unisim.vcomponents.LUT5 +dma_slverr_reg: unisim.vcomponents.FDRE generic map( - INIT => X"00004540" + INIT => '0' ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => ip2axi_rddata_int_inferred_i_61_n_0, - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I3 => ip2axi_rddata_int_inferred_i_62_n_0, - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(17) + C => m_axi_s2mm_aclk, + CE => '1', + D => slverr_i_reg, + Q => \^s2mm_err_for_irq.frm_store_i_reg[0]_1\, + R => SR(0) ); -ip2axi_rddata_int_inferred_i_16: unisim.vcomponents.LUT5 +\dmacr_i[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( - INIT => X"00004540" + INIT => X"7077700000000000" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => ip2axi_rddata_int_inferred_i_63_n_0, - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I3 => ip2axi_rddata_int_inferred_i_64_n_0, - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(16) + I0 => \^s2mm_dmacr\(3), + I1 => s2mm_ioc_irq_set, + I2 => D(0), + I3 => s2mm_axi2ip_wrce(0), + I4 => \^s2mm_dmacr\(0), + I5 => \dmacr_i[0]_i_2__0_n_0\, + O => dmacr_i(0) ); -ip2axi_rddata_int_inferred_i_17: unisim.vcomponents.LUT6 +\dmacr_i[0]_i_2__0\: unisim.vcomponents.LUT3 generic map( - INIT => X"0000000040554000" + INIT => X"04" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I2 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[15]\, - I3 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I4 => ip2axi_rddata_int_inferred_i_66_n_0, - I5 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(15) + I0 => \^soft_reset_d1_reg\, + I1 => prmry_resetn_i_reg, + I2 => s2mm_stop, + O => \dmacr_i[0]_i_2__0_n_0\ ); -ip2axi_rddata_int_inferred_i_18: unisim.vcomponents.LUT6 +\dmacr_i_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => X"0000000040554000" + INIT => '0' ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I2 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[14]\, - I3 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I4 => ip2axi_rddata_int_inferred_i_68_n_0, - I5 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(14) + C => m_axi_s2mm_aclk, + CE => '1', + D => dmacr_i(0), + Q => \^s2mm_dmacr\(0), + R => '0' ); -ip2axi_rddata_int_inferred_i_19: unisim.vcomponents.LUT6 +\dmacr_i_reg[1]\: unisim.vcomponents.FDSE generic map( - INIT => X"0000000040554000" + INIT => '0' ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I2 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[13]\, - I3 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I4 => ip2axi_rddata_int_inferred_i_70_n_0, - I5 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(13) + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(1), + Q => \^s2mm_dmacr\(1), + S => SR(0) ); -ip2axi_rddata_int_inferred_i_2: unisim.vcomponents.LUT5 +\dmacr_i_reg[2]\: unisim.vcomponents.FDRE generic map( - INIT => X"00004540" + INIT => '0' ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => ip2axi_rddata_int_inferred_i_35_n_0, - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I3 => ip2axi_rddata_int_inferred_i_36_n_0, - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(30) + C => m_axi_s2mm_aclk, + CE => '1', + D => \dmacr_i_reg[2]_0\, + Q => \^soft_reset_d1_reg\, + R => '0' ); -ip2axi_rddata_int_inferred_i_20: unisim.vcomponents.LUT6 +\err_d1_i_1__0\: unisim.vcomponents.LUT6 generic map( - INIT => X"0000000040554000" + INIT => X"EFEEFFFFEFEEEFEE" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I2 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[12]\, - I3 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I4 => ip2axi_rddata_int_inferred_i_72_n_0, - I5 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(12) + I0 => err_d1_i_2_n_0, + I1 => \^err_d1_reg_1\, + I2 => \^err_d1_reg_2\(2), + I3 => \^err_d1_reg_0\, + I4 => \^err_d1_reg_2\(3), + I5 => \^s2mm_err_for_irq.frm_store_i_reg[0]_4\, + O => err ); -ip2axi_rddata_int_inferred_i_21: unisim.vcomponents.LUT5 +err_d1_i_2: unisim.vcomponents.LUT6 generic map( - INIT => X"00004000" + INIT => X"EEFEEEFEFFFFEEFE" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[11]\, - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I3 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(11) + I0 => \^s2mm_err_for_irq.frm_store_i_reg[0]_2\, + I1 => \^s2mm_err_for_irq.frm_store_i_reg[0]_1\, + I2 => \^s2mm_err_for_irq.frm_store_i_reg[0]_3\, + I3 => \^err_d1_reg_2\(1), + I4 => \^gen_for_flush.fsize_err_reg_0\, + I5 => \^err_d1_reg_2\(0), + O => err_d1_i_2_n_0 ); -ip2axi_rddata_int_inferred_i_22: unisim.vcomponents.LUT5 +err_d1_reg: unisim.vcomponents.FDRE generic map( - INIT => X"00004000" + INIT => '0' ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[10]\, - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I3 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(10) + C => m_axi_s2mm_aclk, + CE => '1', + D => err, + Q => err_d1, + R => SR(0) ); -ip2axi_rddata_int_inferred_i_23: unisim.vcomponents.LUT5 +\err_irq_i_1__0\: unisim.vcomponents.LUT5 generic map( - INIT => X"00004000" + INIT => X"5DFF0C0C" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[9]\, - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I3 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(9) + I0 => D(13), + I1 => err, + I2 => err_d1, + I3 => s2mm_axi2ip_wrce(1), + I4 => \^err_irq_reg_0\, + O => \err_irq_i_1__0_n_0\ ); -ip2axi_rddata_int_inferred_i_24: unisim.vcomponents.LUT5 +err_irq_reg: unisim.vcomponents.FDRE generic map( - INIT => X"00004000" + INIT => '0' ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[8]\, - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I3 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(8) + C => m_axi_s2mm_aclk, + CE => '1', + D => \err_irq_i_1__0_n_0\, + Q => \^err_irq_reg_0\, + R => SR(0) ); -ip2axi_rddata_int_inferred_i_25: unisim.vcomponents.LUT5 +halted_reg: unisim.vcomponents.FDRE generic map( - INIT => X"00004000" + INIT => '0' ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[7]\, - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I3 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(7) + C => m_axi_s2mm_aclk, + CE => '1', + D => halted_clr_reg, + Q => \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\, + R => '0' ); -ip2axi_rddata_int_inferred_i_26: unisim.vcomponents.LUT6 +\introut_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => X"0000000040554000" + INIT => X"08" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I2 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[6]\, - I3 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I4 => ip2axi_rddata_int_inferred_i_79_n_0, - I5 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(6) + I0 => introut07_out, + I1 => prmry_resetn_i_reg, + I2 => \^soft_reset_d1_reg\, + O => \introut_i_1__0_n_0\ ); -ip2axi_rddata_int_inferred_i_27: unisim.vcomponents.LUT6 +\introut_i_2__0\: unisim.vcomponents.LUT6 generic map( - INIT => X"0000000040554000" + INIT => X"FFFFF888F888F888" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I2 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[5]\, - I3 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I4 => ip2axi_rddata_int_inferred_i_81_n_0, - I5 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(5) + I0 => \^q\(6), + I1 => \^err_irq_reg_0\, + I2 => \^q\(5), + I3 => \^dly_irq_reg_0\, + I4 => \^ioc_irq_reg_0\, + I5 => \^q\(4), + O => introut07_out + ); +introut_reg: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \introut_i_1__0_n_0\, + Q => s2mm_ip2axi_introut, + R => '0' ); -ip2axi_rddata_int_inferred_i_28: unisim.vcomponents.LUT6 +ioc_irq_reg: unisim.vcomponents.FDRE generic map( - INIT => X"0000000040554000" + INIT => '0' ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I2 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[4]\, - I3 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I4 => ip2axi_rddata_int_inferred_i_83_n_0, - I5 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(4) + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[12]\, + Q => \^ioc_irq_reg_0\, + R => SR(0) ); -ip2axi_rddata_int_inferred_i_29: unisim.vcomponents.LUT5 +lsize_err_reg: unisim.vcomponents.FDRE generic map( - INIT => X"00004000" + INIT => '0' ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[3]\, - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I3 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(3) + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[8]\, + Q => \^s2mm_err_for_irq.frm_store_i_reg[0]_3\, + R => SR(0) ); -ip2axi_rddata_int_inferred_i_3: unisim.vcomponents.LUT5 +lsize_more_err_reg: unisim.vcomponents.FDRE generic map( - INIT => X"00004540" + INIT => '0' ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => ip2axi_rddata_int_inferred_i_37_n_0, - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I3 => ip2axi_rddata_int_inferred_i_38_n_0, - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(29) + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[15]\, + Q => \^s2mm_err_for_irq.frm_store_i_reg[0]_4\, + R => SR(0) ); -ip2axi_rddata_int_inferred_i_30: unisim.vcomponents.LUT6 +reset_counts_reg: unisim.vcomponents.FDRE generic map( - INIT => X"0000000040554000" + INIT => '0' ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I2 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[2]\, - I3 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I4 => ip2axi_rddata_int_inferred_i_86_n_0, - I5 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(2) + C => m_axi_s2mm_aclk, + CE => '1', + D => reset_counts_reg_0, + Q => \^reset_counts\, + R => '0' ); -ip2axi_rddata_int_inferred_i_31: unisim.vcomponents.LUT6 +\s_axis_cmd_tdata[63]_i_1__0\: unisim.vcomponents.LUT2 generic map( - INIT => X"0000000040554000" + INIT => X"B" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I2 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[1]\, - I3 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I4 => ip2axi_rddata_int_inferred_i_88_n_0, - I5 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(1) + I0 => \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\, + I1 => prmry_resetn_i_reg, + O => s_axis_cmd_tvalid_reg(0) ); -ip2axi_rddata_int_inferred_i_32: unisim.vcomponents.LUT6 +\s_soft_reset_i_i_1__0\: unisim.vcomponents.LUT4 generic map( - INIT => X"0000000040554000" + INIT => X"A800" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I2 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[0]\, - I3 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I4 => ip2axi_rddata_int_inferred_i_90_n_0, - I5 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(0) - ); -ip2axi_rddata_int_inferred_i_33: unisim.vcomponents.LUT5 - generic map( - INIT => X"80000000" + I0 => \^soft_reset_d1_reg\, + I1 => s2mm_halt_cmplt, + I2 => halt_reset, + I3 => prmry_in, + O => s_soft_reset_i0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_skid_buf is + port ( + \out\ : out STD_LOGIC; + m_axis_mm2s_tvalid : out STD_LOGIC; + m_axis_mm2s_tlast : out STD_LOGIC; + m_axis_mm2s_tuser : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tlast_d1_reg\ : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tvalid_d1_reg\ : out STD_LOGIC; + s_valid0 : out STD_LOGIC; + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : out STD_LOGIC; + m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axis_mm2s_aclk : in STD_LOGIC; + m_axis_fifo_ainit_nosync : in STD_LOGIC; + fifo_dout : in STD_LOGIC_VECTOR ( 33 downto 0 ); + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ : in STD_LOGIC; + m_axis_mm2s_tready : in STD_LOGIC; + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : in STD_LOGIC; + mm2s_axis_resetn : in STD_LOGIC; + p_15_out : in STD_LOGIC; + \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_skid_buf : entity is "axi_vdma_skid_buf"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_skid_buf; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_skid_buf is + signal \^m_axis_mm2s_tlast\ : STD_LOGIC; + signal sig_data_reg_out_en : STD_LOGIC; + signal sig_data_skid_mux_out : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal sig_data_skid_reg : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal sig_last_skid_mux_out : STD_LOGIC; + signal sig_last_skid_reg : STD_LOGIC; + signal sig_m_valid_dup : STD_LOGIC; + attribute RTL_KEEP : string; + attribute RTL_KEEP of sig_m_valid_dup : signal is "true"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of sig_m_valid_dup : signal is "no"; + signal \sig_m_valid_dup_i_1__2_n_0\ : STD_LOGIC; + signal sig_m_valid_out : STD_LOGIC; + attribute RTL_KEEP of sig_m_valid_out : signal is "true"; + attribute equivalent_register_removal of sig_m_valid_out : signal is "no"; + signal sig_reset_reg : STD_LOGIC; + signal sig_s_ready_dup : STD_LOGIC; + attribute RTL_KEEP of sig_s_ready_dup : signal is "true"; + attribute equivalent_register_removal of sig_s_ready_dup : signal is "no"; + signal \sig_s_ready_dup_i_1__2_n_0\ : STD_LOGIC; + signal sig_s_ready_out : STD_LOGIC; + attribute RTL_KEEP of sig_s_ready_out : signal is "true"; + attribute equivalent_register_removal of sig_s_ready_out : signal is "no"; + signal sig_user_skid_mux_out : STD_LOGIC; + signal sig_user_skid_reg : STD_LOGIC; + attribute KEEP : string; + attribute KEEP of sig_m_valid_dup_reg : label is "yes"; + attribute equivalent_register_removal of sig_m_valid_dup_reg : label is "no"; + attribute KEEP of sig_m_valid_out_reg : label is "yes"; + attribute equivalent_register_removal of sig_m_valid_out_reg : label is "no"; + attribute KEEP of sig_s_ready_dup_reg : label is "yes"; + attribute equivalent_register_removal of sig_s_ready_dup_reg : label is "no"; + attribute KEEP of sig_s_ready_out_reg : label is "yes"; + attribute equivalent_register_removal of sig_s_ready_out_reg : label is "no"; +begin + m_axis_mm2s_tlast <= \^m_axis_mm2s_tlast\; + m_axis_mm2s_tvalid <= sig_m_valid_out; + \out\ <= sig_s_ready_out; +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_1__4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(15), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - O => ip2axi_rddata_int_inferred_i_33_n_0 + I0 => \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg\, + I1 => sig_m_valid_out, + O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ ); -ip2axi_rddata_int_inferred_i_34: unisim.vcomponents.LUT5 +\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tlast_d1_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"00004540" + INIT => X"0020" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - I1 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]\(7), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => p_68_out(25), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - O => ip2axi_rddata_int_inferred_i_34_n_0 + I0 => \^m_axis_mm2s_tlast\, + I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\, + I2 => mm2s_axis_resetn, + I3 => p_15_out, + O => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tlast_d1_reg\ ); -ip2axi_rddata_int_inferred_i_35: unisim.vcomponents.LUT5 +\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tvalid_d1_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"80000000" + INIT => X"0020" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(14), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - O => ip2axi_rddata_int_inferred_i_35_n_0 + I0 => sig_m_valid_out, + I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\, + I2 => mm2s_axis_resetn, + I3 => p_15_out, + O => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tvalid_d1_reg\ ); -ip2axi_rddata_int_inferred_i_36: unisim.vcomponents.LUT5 +\s_valid_i_1__0\: unisim.vcomponents.LUT2 generic map( - INIT => X"00004540" + INIT => X"8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - I1 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]\(6), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => p_68_out(24), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - O => ip2axi_rddata_int_inferred_i_36_n_0 + I0 => sig_m_valid_out, + I1 => m_axis_mm2s_tready, + O => s_valid0 ); -ip2axi_rddata_int_inferred_i_37: unisim.vcomponents.LUT5 +\sig_data_reg_out[0]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"80000000" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(13), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - O => ip2axi_rddata_int_inferred_i_37_n_0 + I0 => fifo_dout(0), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(0), + O => sig_data_skid_mux_out(0) ); -ip2axi_rddata_int_inferred_i_38: unisim.vcomponents.LUT5 +\sig_data_reg_out[10]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"00004540" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - I1 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]\(5), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => p_68_out(23), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - O => ip2axi_rddata_int_inferred_i_38_n_0 + I0 => fifo_dout(10), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(10), + O => sig_data_skid_mux_out(10) ); -ip2axi_rddata_int_inferred_i_39: unisim.vcomponents.LUT5 +\sig_data_reg_out[11]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"80000000" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(12), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - O => ip2axi_rddata_int_inferred_i_39_n_0 + I0 => fifo_dout(11), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(11), + O => sig_data_skid_mux_out(11) ); -ip2axi_rddata_int_inferred_i_4: unisim.vcomponents.LUT5 +\sig_data_reg_out[12]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"00004540" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => ip2axi_rddata_int_inferred_i_39_n_0, - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I3 => ip2axi_rddata_int_inferred_i_40_n_0, - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(28) + I0 => fifo_dout(12), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(12), + O => sig_data_skid_mux_out(12) ); -ip2axi_rddata_int_inferred_i_40: unisim.vcomponents.LUT5 +\sig_data_reg_out[13]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"00004540" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - I1 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]\(4), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => p_68_out(22), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - O => ip2axi_rddata_int_inferred_i_40_n_0 + I0 => fifo_dout(13), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(13), + O => sig_data_skid_mux_out(13) ); -ip2axi_rddata_int_inferred_i_41: unisim.vcomponents.LUT5 +\sig_data_reg_out[14]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"80000000" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(11), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - O => ip2axi_rddata_int_inferred_i_41_n_0 + I0 => fifo_dout(14), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(14), + O => sig_data_skid_mux_out(14) ); -ip2axi_rddata_int_inferred_i_42: unisim.vcomponents.LUT5 +\sig_data_reg_out[15]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"00004540" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - I1 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]\(3), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => p_68_out(21), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - O => ip2axi_rddata_int_inferred_i_42_n_0 + I0 => fifo_dout(15), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(15), + O => sig_data_skid_mux_out(15) ); -ip2axi_rddata_int_inferred_i_43: unisim.vcomponents.LUT5 +\sig_data_reg_out[16]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"80000000" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(10), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - O => ip2axi_rddata_int_inferred_i_43_n_0 + I0 => fifo_dout(16), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(16), + O => sig_data_skid_mux_out(16) ); -ip2axi_rddata_int_inferred_i_44: unisim.vcomponents.LUT5 +\sig_data_reg_out[17]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"00004540" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - I1 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]\(2), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => p_68_out(20), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - O => ip2axi_rddata_int_inferred_i_44_n_0 + I0 => fifo_dout(17), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(17), + O => sig_data_skid_mux_out(17) ); -ip2axi_rddata_int_inferred_i_45: unisim.vcomponents.LUT5 +\sig_data_reg_out[18]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"80000000" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(9), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - O => ip2axi_rddata_int_inferred_i_45_n_0 + I0 => fifo_dout(18), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(18), + O => sig_data_skid_mux_out(18) ); -ip2axi_rddata_int_inferred_i_46: unisim.vcomponents.LUT5 +\sig_data_reg_out[19]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"00004540" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - I1 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]\(1), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => p_68_out(19), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - O => ip2axi_rddata_int_inferred_i_46_n_0 + I0 => fifo_dout(19), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(19), + O => sig_data_skid_mux_out(19) ); -ip2axi_rddata_int_inferred_i_47: unisim.vcomponents.LUT5 +\sig_data_reg_out[1]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"80000000" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(8), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - O => ip2axi_rddata_int_inferred_i_47_n_0 + I0 => fifo_dout(1), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(1), + O => sig_data_skid_mux_out(1) ); -ip2axi_rddata_int_inferred_i_48: unisim.vcomponents.LUT5 +\sig_data_reg_out[20]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"00004540" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - I1 => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]\(0), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => p_68_out(18), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - O => ip2axi_rddata_int_inferred_i_48_n_0 + I0 => fifo_dout(20), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(20), + O => sig_data_skid_mux_out(20) ); -ip2axi_rddata_int_inferred_i_49: unisim.vcomponents.LUT5 +\sig_data_reg_out[21]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"80000000" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(7), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - O => ip2axi_rddata_int_inferred_i_49_n_0 + I0 => fifo_dout(21), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(21), + O => sig_data_skid_mux_out(21) ); -ip2axi_rddata_int_inferred_i_5: unisim.vcomponents.LUT5 +\sig_data_reg_out[22]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"00004540" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => ip2axi_rddata_int_inferred_i_41_n_0, - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I3 => ip2axi_rddata_int_inferred_i_42_n_0, - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(27) + I0 => fifo_dout(22), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(22), + O => sig_data_skid_mux_out(22) ); -ip2axi_rddata_int_inferred_i_50: unisim.vcomponents.LUT5 +\sig_data_reg_out[23]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"00004540" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - I1 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\(7), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => p_68_out(17), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - O => ip2axi_rddata_int_inferred_i_50_n_0 + I0 => fifo_dout(23), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(23), + O => sig_data_skid_mux_out(23) ); -ip2axi_rddata_int_inferred_i_51: unisim.vcomponents.LUT5 +\sig_data_reg_out[24]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"80000000" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(6), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - O => ip2axi_rddata_int_inferred_i_51_n_0 + I0 => fifo_dout(24), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(24), + O => sig_data_skid_mux_out(24) ); -ip2axi_rddata_int_inferred_i_52: unisim.vcomponents.LUT5 +\sig_data_reg_out[25]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"00004540" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - I1 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\(6), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => p_68_out(16), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - O => ip2axi_rddata_int_inferred_i_52_n_0 + I0 => fifo_dout(25), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(25), + O => sig_data_skid_mux_out(25) ); -ip2axi_rddata_int_inferred_i_53: unisim.vcomponents.LUT5 +\sig_data_reg_out[26]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"80000000" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(5), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - O => ip2axi_rddata_int_inferred_i_53_n_0 + I0 => fifo_dout(26), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(26), + O => sig_data_skid_mux_out(26) ); -ip2axi_rddata_int_inferred_i_54: unisim.vcomponents.LUT5 +\sig_data_reg_out[27]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"00004540" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - I1 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\(5), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => p_68_out(15), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - O => ip2axi_rddata_int_inferred_i_54_n_0 + I0 => fifo_dout(27), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(27), + O => sig_data_skid_mux_out(27) ); -ip2axi_rddata_int_inferred_i_55: unisim.vcomponents.LUT5 +\sig_data_reg_out[28]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"80000000" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(4), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - O => ip2axi_rddata_int_inferred_i_55_n_0 + I0 => fifo_dout(28), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(28), + O => sig_data_skid_mux_out(28) ); -ip2axi_rddata_int_inferred_i_56: unisim.vcomponents.LUT5 +\sig_data_reg_out[29]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"00004540" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - I1 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\(4), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => p_68_out(14), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - O => ip2axi_rddata_int_inferred_i_56_n_0 + I0 => fifo_dout(29), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(29), + O => sig_data_skid_mux_out(29) ); -ip2axi_rddata_int_inferred_i_57: unisim.vcomponents.LUT5 +\sig_data_reg_out[2]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"80000000" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(3), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - O => ip2axi_rddata_int_inferred_i_57_n_0 + I0 => fifo_dout(2), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(2), + O => sig_data_skid_mux_out(2) ); -ip2axi_rddata_int_inferred_i_58: unisim.vcomponents.LUT5 +\sig_data_reg_out[30]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"00004540" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - I1 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\(3), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => p_68_out(13), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - O => ip2axi_rddata_int_inferred_i_58_n_0 + I0 => fifo_dout(30), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(30), + O => sig_data_skid_mux_out(30) ); -ip2axi_rddata_int_inferred_i_59: unisim.vcomponents.LUT5 +\sig_data_reg_out[31]_i_2\: unisim.vcomponents.LUT2 generic map( - INIT => X"80000000" + INIT => X"B" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(2), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - O => ip2axi_rddata_int_inferred_i_59_n_0 + I0 => m_axis_mm2s_tready, + I1 => sig_m_valid_dup, + O => sig_data_reg_out_en ); -ip2axi_rddata_int_inferred_i_6: unisim.vcomponents.LUT5 +\sig_data_reg_out[31]_i_3\: unisim.vcomponents.LUT3 generic map( - INIT => X"00004540" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => ip2axi_rddata_int_inferred_i_43_n_0, - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I3 => ip2axi_rddata_int_inferred_i_44_n_0, - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(26) + I0 => fifo_dout(31), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(31), + O => sig_data_skid_mux_out(31) ); -ip2axi_rddata_int_inferred_i_60: unisim.vcomponents.LUT5 +\sig_data_reg_out[3]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"00004540" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - I1 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\(2), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => p_68_out(12), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - O => ip2axi_rddata_int_inferred_i_60_n_0 + I0 => fifo_dout(3), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(3), + O => sig_data_skid_mux_out(3) ); -ip2axi_rddata_int_inferred_i_61: unisim.vcomponents.LUT5 +\sig_data_reg_out[4]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"80000000" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(1), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - O => ip2axi_rddata_int_inferred_i_61_n_0 + I0 => fifo_dout(4), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(4), + O => sig_data_skid_mux_out(4) ); -ip2axi_rddata_int_inferred_i_62: unisim.vcomponents.LUT5 +\sig_data_reg_out[5]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"00004540" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - I1 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\(1), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => p_68_out(11), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - O => ip2axi_rddata_int_inferred_i_62_n_0 + I0 => fifo_dout(5), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(5), + O => sig_data_skid_mux_out(5) ); -ip2axi_rddata_int_inferred_i_63: unisim.vcomponents.LUT5 +\sig_data_reg_out[6]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"80000000" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(0), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - O => ip2axi_rddata_int_inferred_i_63_n_0 + I0 => fifo_dout(6), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(6), + O => sig_data_skid_mux_out(6) ); -ip2axi_rddata_int_inferred_i_64: unisim.vcomponents.LUT5 +\sig_data_reg_out[7]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"00004540" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - I1 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\(0), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => p_68_out(10), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - O => ip2axi_rddata_int_inferred_i_64_n_0 + I0 => fifo_dout(7), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(7), + O => sig_data_skid_mux_out(7) ); -ip2axi_rddata_int_inferred_i_66: unisim.vcomponents.LUT4 +\sig_data_reg_out[8]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"0004" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - I1 => p_68_out(9), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - O => ip2axi_rddata_int_inferred_i_66_n_0 + I0 => fifo_dout(8), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(8), + O => sig_data_skid_mux_out(8) ); -ip2axi_rddata_int_inferred_i_68: unisim.vcomponents.LUT5 +\sig_data_reg_out[9]_i_1__1\: unisim.vcomponents.LUT3 generic map( - INIT => X"00004540" + INIT => X"B8" ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - I1 => err_irq_reg, - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => p_68_out(8), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - O => ip2axi_rddata_int_inferred_i_68_n_0 + I0 => fifo_dout(9), + I1 => sig_s_ready_dup, + I2 => sig_data_skid_reg(9), + O => sig_data_skid_mux_out(9) ); -ip2axi_rddata_int_inferred_i_7: unisim.vcomponents.LUT5 +\sig_data_reg_out_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => X"00004540" + INIT => '0' ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => ip2axi_rddata_int_inferred_i_45_n_0, - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I3 => ip2axi_rddata_int_inferred_i_46_n_0, - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(25) + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(0), + Q => m_axis_mm2s_tdata(0), + R => m_axis_fifo_ainit_nosync ); -ip2axi_rddata_int_inferred_i_70: unisim.vcomponents.LUT5 +\sig_data_reg_out_reg[10]\: unisim.vcomponents.FDRE generic map( - INIT => X"00004540" + INIT => '0' ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - I1 => dly_irq_reg_0, - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => p_68_out(7), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - O => ip2axi_rddata_int_inferred_i_70_n_0 + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(10), + Q => m_axis_mm2s_tdata(10), + R => m_axis_fifo_ainit_nosync ); -ip2axi_rddata_int_inferred_i_72: unisim.vcomponents.LUT5 +\sig_data_reg_out_reg[11]\: unisim.vcomponents.FDRE generic map( - INIT => X"00004540" + INIT => '0' ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - I1 => ioc_irq_reg_0, - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => p_68_out(6), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - O => ip2axi_rddata_int_inferred_i_72_n_0 + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(11), + Q => m_axis_mm2s_tdata(11), + R => m_axis_fifo_ainit_nosync ); -ip2axi_rddata_int_inferred_i_79: unisim.vcomponents.LUT5 +\sig_data_reg_out_reg[12]\: unisim.vcomponents.FDRE generic map( - INIT => X"00004540" + INIT => '0' ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - I1 => dma_decerr_reg, - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => p_68_out(5), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - O => ip2axi_rddata_int_inferred_i_79_n_0 + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(12), + Q => m_axis_mm2s_tdata(12), + R => m_axis_fifo_ainit_nosync ); -ip2axi_rddata_int_inferred_i_8: unisim.vcomponents.LUT5 +\sig_data_reg_out_reg[13]\: unisim.vcomponents.FDRE generic map( - INIT => X"00004540" + INIT => '0' ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => ip2axi_rddata_int_inferred_i_47_n_0, - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I3 => ip2axi_rddata_int_inferred_i_48_n_0, - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(24) + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(13), + Q => m_axis_mm2s_tdata(13), + R => m_axis_fifo_ainit_nosync ); -ip2axi_rddata_int_inferred_i_81: unisim.vcomponents.LUT5 +\sig_data_reg_out_reg[14]\: unisim.vcomponents.FDRE generic map( - INIT => X"00004540" + INIT => '0' ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - I1 => dma_slverr_reg, - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => p_68_out(4), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - O => ip2axi_rddata_int_inferred_i_81_n_0 + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(14), + Q => m_axis_mm2s_tdata(14), + R => m_axis_fifo_ainit_nosync ); -ip2axi_rddata_int_inferred_i_83: unisim.vcomponents.LUT5 +\sig_data_reg_out_reg[15]\: unisim.vcomponents.FDRE generic map( - INIT => X"00004540" + INIT => '0' ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - I1 => dma_interr_reg, - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => p_68_out(3), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - O => ip2axi_rddata_int_inferred_i_83_n_0 + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(15), + Q => m_axis_mm2s_tdata(15), + R => m_axis_fifo_ainit_nosync ); -ip2axi_rddata_int_inferred_i_86: unisim.vcomponents.LUT4 +\sig_data_reg_out_reg[16]\: unisim.vcomponents.FDRE generic map( - INIT => X"0004" + INIT => '0' ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - I1 => p_68_out(2), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - O => ip2axi_rddata_int_inferred_i_86_n_0 + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(16), + Q => m_axis_mm2s_tdata(16), + R => m_axis_fifo_ainit_nosync ); -ip2axi_rddata_int_inferred_i_88: unisim.vcomponents.LUT4 +\sig_data_reg_out_reg[17]\: unisim.vcomponents.FDRE generic map( - INIT => X"0004" + INIT => '0' ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - I1 => p_68_out(1), - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - O => ip2axi_rddata_int_inferred_i_88_n_0 + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(17), + Q => m_axis_mm2s_tdata(17), + R => m_axis_fifo_ainit_nosync ); -ip2axi_rddata_int_inferred_i_9: unisim.vcomponents.LUT5 +\sig_data_reg_out_reg[18]\: unisim.vcomponents.FDRE generic map( - INIT => X"00004540" + INIT => '0' ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), - I1 => ip2axi_rddata_int_inferred_i_49_n_0, - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), - I3 => ip2axi_rddata_int_inferred_i_50_n_0, - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), - O => in0(23) + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(18), + Q => m_axis_mm2s_tdata(18), + R => m_axis_fifo_ainit_nosync ); -ip2axi_rddata_int_inferred_i_90: unisim.vcomponents.LUT5 +\sig_data_reg_out_reg[19]\: unisim.vcomponents.FDRE generic map( - INIT => X"00004540" + INIT => '0' ) port map ( - I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), - I1 => p_67_out, - I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), - I3 => p_68_out(0), - I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), - O => ip2axi_rddata_int_inferred_i_90_n_0 + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(19), + Q => m_axis_mm2s_tdata(19), + R => m_axis_fifo_ainit_nosync ); -lite_wr_addr_phase_finished_data_phase_started_i_1: unisim.vcomponents.LUT4 +\sig_data_reg_out_reg[1]\: unisim.vcomponents.FDRE generic map( - INIT => X"00E0" + INIT => '0' ) port map ( - I0 => lite_wr_addr_phase_finished_data_phase_started, - I1 => \^s_axi_lite_awready\, - I2 => s_axi_lite_resetn, - I3 => \^s_axi_lite_wready\, - O => lite_wr_addr_phase_finished_data_phase_started_i_1_n_0 + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(1), + Q => m_axis_mm2s_tdata(1), + R => m_axis_fifo_ainit_nosync ); -lite_wr_addr_phase_finished_data_phase_started_reg: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => lite_wr_addr_phase_finished_data_phase_started_i_1_n_0, - Q => lite_wr_addr_phase_finished_data_phase_started, - R => '0' + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(20), + Q => m_axis_mm2s_tdata(20), + R => m_axis_fifo_ainit_nosync ); -read_has_started_i_i_1: unisim.vcomponents.LUT6 +\sig_data_reg_out_reg[21]\: unisim.vcomponents.FDRE generic map( - INIT => X"0000AE00AE00AE00" + INIT => '0' ) port map ( - I0 => read_has_started_i, - I1 => arvalid, - I2 => sig_arvalid_arrived_d1, - I3 => s_axi_lite_resetn, - I4 => s_axi_lite_rready, - I5 => \^s_axi_lite_rvalid\, - O => read_has_started_i_i_1_n_0 + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(21), + Q => m_axis_mm2s_tdata(21), + R => m_axis_fifo_ainit_nosync ); -read_has_started_i_reg: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => read_has_started_i_i_1_n_0, - Q => read_has_started_i, - R => '0' + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(22), + Q => m_axis_mm2s_tdata(22), + R => m_axis_fifo_ainit_nosync ); -sig_arvalid_arrived_d1_i_1: unisim.vcomponents.LUT3 +\sig_data_reg_out_reg[23]\: unisim.vcomponents.FDRE generic map( - INIT => X"08" + INIT => '0' ) port map ( - I0 => arvalid, - I1 => s_axi_lite_resetn, - I2 => read_has_started_i, - O => sig_arvalid_arrived_d1_i_1_n_0 + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(23), + Q => m_axis_mm2s_tdata(23), + R => m_axis_fifo_ainit_nosync ); -sig_arvalid_arrived_d1_reg: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => sig_arvalid_arrived_d1_i_1_n_0, - Q => sig_arvalid_arrived_d1, - R => '0' + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(24), + Q => m_axis_mm2s_tdata(24), + R => m_axis_fifo_ainit_nosync ); -sig_arvalid_detected: unisim.vcomponents.LUT3 +\sig_data_reg_out_reg[25]\: unisim.vcomponents.FDRE generic map( - INIT => X"02" + INIT => '0' ) port map ( - I0 => arvalid, - I1 => read_has_started_i, - I2 => sig_arvalid_arrived_d1, - O => \sig_arvalid_detected__0\ + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(25), + Q => m_axis_mm2s_tdata(25), + R => m_axis_fifo_ainit_nosync ); -sig_awvalid_arrived_d1_i_1: unisim.vcomponents.LUT3 +\sig_data_reg_out_reg[26]\: unisim.vcomponents.FDRE generic map( - INIT => X"08" + INIT => '0' ) port map ( - I0 => awvalid, - I1 => s_axi_lite_resetn, - I2 => write_has_started, - O => sig_awvalid_arrived_d1_i_1_n_0 + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(26), + Q => m_axis_mm2s_tdata(26), + R => m_axis_fifo_ainit_nosync ); -sig_awvalid_arrived_d1_reg: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => sig_awvalid_arrived_d1_i_1_n_0, - Q => sig_awvalid_arrived_d1, - R => '0' + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(27), + Q => m_axis_mm2s_tdata(27), + R => m_axis_fifo_ainit_nosync ); -sig_awvalid_detected: unisim.vcomponents.LUT3 +\sig_data_reg_out_reg[28]\: unisim.vcomponents.FDRE generic map( - INIT => X"02" + INIT => '0' ) port map ( - I0 => awvalid, - I1 => write_has_started, - I2 => sig_awvalid_arrived_d1, - O => \sig_awvalid_detected__0\ + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(28), + Q => m_axis_mm2s_tdata(28), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[0]\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(0), - Q => wdata(0), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(29), + Q => m_axis_mm2s_tdata(29), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[10]\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(10), - Q => wdata(10), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(2), + Q => m_axis_mm2s_tdata(2), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[11]\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(11), - Q => wdata(11), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(30), + Q => m_axis_mm2s_tdata(30), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[12]\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(12), - Q => wdata(12), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(31), + Q => m_axis_mm2s_tdata(31), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[13]\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(13), - Q => wdata(13), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(3), + Q => m_axis_mm2s_tdata(3), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[14]\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(14), - Q => wdata(14), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(4), + Q => m_axis_mm2s_tdata(4), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[15]\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(15), - Q => wdata(15), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(5), + Q => m_axis_mm2s_tdata(5), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[16]\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(16), - Q => wdata(16), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(6), + Q => m_axis_mm2s_tdata(6), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[17]\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(17), - Q => wdata(17), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(7), + Q => m_axis_mm2s_tdata(7), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[18]\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(18), - Q => wdata(18), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(8), + Q => m_axis_mm2s_tdata(8), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[19]\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(19), - Q => wdata(19), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_data_skid_mux_out(9), + Q => m_axis_mm2s_tdata(9), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[1]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(1), - Q => wdata(1), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(0), + Q => sig_data_skid_reg(0), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[20]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(20), - Q => wdata(20), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(10), + Q => sig_data_skid_reg(10), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[21]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(21), - Q => wdata(21), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(11), + Q => sig_data_skid_reg(11), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[22]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(22), - Q => wdata(22), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(12), + Q => sig_data_skid_reg(12), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[23]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(23), - Q => wdata(23), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(13), + Q => sig_data_skid_reg(13), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[24]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(24), - Q => wdata(24), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(14), + Q => sig_data_skid_reg(14), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[25]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(25), - Q => wdata(25), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(15), + Q => sig_data_skid_reg(15), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[26]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(26), - Q => wdata(26), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(16), + Q => sig_data_skid_reg(16), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[27]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(27), - Q => wdata(27), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(17), + Q => sig_data_skid_reg(17), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[28]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(28), - Q => wdata(28), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(18), + Q => sig_data_skid_reg(18), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[29]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(29), - Q => wdata(29), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(19), + Q => sig_data_skid_reg(19), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[2]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(2), - Q => wdata(2), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(1), + Q => sig_data_skid_reg(1), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[30]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(30), - Q => wdata(30), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(20), + Q => sig_data_skid_reg(20), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[31]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(31), - Q => wdata(31), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(21), + Q => sig_data_skid_reg(21), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[3]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(3), - Q => wdata(3), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(22), + Q => sig_data_skid_reg(22), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[4]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(4), - Q => wdata(4), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(23), + Q => sig_data_skid_reg(23), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[5]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(5), - Q => wdata(5), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(24), + Q => sig_data_skid_reg(24), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[6]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(6), - Q => wdata(6), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(25), + Q => sig_data_skid_reg(25), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[7]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(7), - Q => wdata(7), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(26), + Q => sig_data_skid_reg(26), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[8]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(8), - Q => wdata(8), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(27), + Q => sig_data_skid_reg(27), + R => m_axis_fifo_ainit_nosync ); -\wdata_reg[9]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wdata(9), - Q => wdata(9), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(28), + Q => sig_data_skid_reg(28), + R => m_axis_fifo_ainit_nosync ); -write_has_started_i_1: unisim.vcomponents.LUT6 +\sig_data_skid_reg_reg[29]\: unisim.vcomponents.FDRE generic map( - INIT => X"0000AE00AE00AE00" + INIT => '0' ) port map ( - I0 => write_has_started, - I1 => awvalid, - I2 => sig_awvalid_arrived_d1, - I3 => s_axi_lite_resetn, - I4 => s_axi_lite_bready, - I5 => \^s_axi_lite_bvalid\, - O => write_has_started_i_1_n_0 + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(29), + Q => sig_data_skid_reg(29), + R => m_axis_fifo_ainit_nosync ); -write_has_started_reg: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => write_has_started_i_1_n_0, - Q => write_has_started, - R => '0' + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(2), + Q => sig_data_skid_reg(2), + R => m_axis_fifo_ainit_nosync ); -wvalid_reg: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => s_axi_lite_wvalid, - Q => wvalid, - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(30), + Q => sig_data_skid_reg(30), + R => m_axis_fifo_ainit_nosync ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_module is - port ( - p_68_out : out STD_LOGIC_VECTOR ( 25 downto 0 ); - \out\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); - err_d1_reg : out STD_LOGIC; - ioc_irq_reg : out STD_LOGIC; - dly_irq_reg : out STD_LOGIC; - reset_counts : out STD_LOGIC; - p_67_out : out STD_LOGIC; - err_d1_reg_0 : out STD_LOGIC; - err_d1_reg_1 : out STD_LOGIC; - p_75_out : out STD_LOGIC; - p_64_out : out STD_LOGIC; - s_soft_reset_i0 : out STD_LOGIC; - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - ch1_disable_delay2_out : out STD_LOGIC; - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - \p_6_out__1\ : out STD_LOGIC; - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : out STD_LOGIC; - stop_i : out STD_LOGIC; - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - \ch1_delay_zero__6\ : out STD_LOGIC; - err_irq_reg : out STD_LOGIC; - different_delay : out STD_LOGIC; - different_thresh : out STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0]\ : out STD_LOGIC; - \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); - \stride_vid_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); - \hsize_vid_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); - \vsize_vid_reg[12]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[1]\ : out STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[2]\ : out STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3]\ : out STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4]\ : out STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5]\ : out STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6]\ : out STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7]\ : out STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8]\ : out STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9]\ : out STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10]\ : out STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]\ : out STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]\ : out STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[13]\ : out STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[14]\ : out STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]\ : out STD_LOGIC; - \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - datamover_idle_reg : out STD_LOGIC; - \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg\ : out STD_LOGIC; - \s_axis_cmd_tdata_reg[63]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - mm2s_axi2ip_wrce : in STD_LOGIC_VECTOR ( 6 downto 0 ); - D : in STD_LOGIC_VECTOR ( 31 downto 0 ); - in0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7]\ : in STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7]_0\ : in STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4]\ : in STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12]\ : in STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13]\ : in STD_LOGIC; - \dmacr_i_reg[2]\ : in STD_LOGIC; - reset_counts_reg : in STD_LOGIC; - halted_clr_reg : in STD_LOGIC; - slverr_i_reg : in STD_LOGIC; - decerr_i_reg : in STD_LOGIC; - prmry_resetn_i_reg : in STD_LOGIC; - mm2s_halt_cmplt : in STD_LOGIC; - halt_reset : in STD_LOGIC; - prmry_in : in STD_LOGIC; - p_17_out : in STD_LOGIC; - ch1_delay_cnt_en : in STD_LOGIC; - p_10_out : in STD_LOGIC; - \ch1_ioc_irq_set_i__0\ : in STD_LOGIC; - Q : in STD_LOGIC_VECTOR ( 0 to 0 ); - p_49_out : in STD_LOGIC; - p_44_out : in STD_LOGIC; - mm2s_dly_irq_set : in STD_LOGIC; - mm2s_halt : in STD_LOGIC; - dma_err : in STD_LOGIC; - \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg\ : in STD_LOGIC; - p_0_out : in STD_LOGIC; - p_46_out : in STD_LOGIC; - mask_fsync_out_i : in STD_LOGIC; - prmry_resetn_i_reg_0 : in STD_LOGIC; - p_35_out : in STD_LOGIC; - mm2s_ioc_irq_set : in STD_LOGIC; - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); - initial_frame : in STD_LOGIC; - datamover_idle : in STD_LOGIC; - p_23_out : in STD_LOGIC; - prmtr_update_complete : in STD_LOGIC; - prmry_resetn_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 ); - \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_module : entity is "axi_vdma_reg_module"; -end Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_module; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_module is - signal \^p_67_out\ : STD_LOGIC; - signal \^p_68_out\ : STD_LOGIC_VECTOR ( 25 downto 0 ); -begin - p_67_out <= \^p_67_out\; - p_68_out(25 downto 0) <= \^p_68_out\(25 downto 0); -\GEN_REG_DIRECT_MODE.REGDIRECT_I\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_regdirect - port map ( - D(31 downto 0) => D(31 downto 0), - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1 downto 0) => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1 downto 0), - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0]\ => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0]\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10]\ => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10]\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]\ => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]\ => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[13]\ => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[13]\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[14]\ => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[14]\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]\ => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[1]\ => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[1]\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[2]\ => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[2]\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3]\ => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3]\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4]\ => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4]\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5]\ => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5]\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6]\ => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6]\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7]\ => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7]\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8]\ => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8]\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9]\ => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9]\, - \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg\ => \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg\, - \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(31 downto 0) => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(31 downto 0), - SR(0) => SR(0), - \dmacr_i_reg[0]\ => \^p_68_out\(0), - halted_reg => \^p_67_out\, - \hsize_vid_reg[15]\(15 downto 0) => \hsize_vid_reg[15]\(15 downto 0), - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - mm2s_axi2ip_wrce(3 downto 0) => mm2s_axi2ip_wrce(6 downto 3), - p_23_out => p_23_out, - p_35_out => p_35_out, - p_64_out => p_64_out, - prmry_resetn_i_reg => prmry_resetn_i_reg, - prmry_resetn_i_reg_0 => prmry_resetn_i_reg_0, - prmtr_update_complete => prmtr_update_complete, - \stride_vid_reg[15]\(15 downto 0) => \stride_vid_reg[15]\(15 downto 0), - \vsize_vid_reg[12]\(12 downto 0) => \vsize_vid_reg[12]\(12 downto 0) - ); -I_DMA_REGISTER: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_register - port map ( - D(24 downto 5) => D(31 downto 12), - D(4 downto 2) => D(6 downto 4), - D(1 downto 0) => D(1 downto 0), - E(0) => E(0), - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\, - \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg\ => \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg\, - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]\(0) => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]\(0), - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0]\(0) => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0]\(0), - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0]\(0) => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0]\(0), - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\ => reset_counts, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7]\ => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7]\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7]_0\ => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7]_0\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12]\ => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12]\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13]\ => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13]\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4]\ => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4]\, - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\(4 downto 0) => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\(4 downto 0), - \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]\(0) => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]\(0), - \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0\(4 downto 0) => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0\(4 downto 0), - Q(0) => Q(0), - SR(0) => SR(0), - ch1_delay_cnt_en => ch1_delay_cnt_en, - \ch1_delay_zero__6\ => \ch1_delay_zero__6\, - ch1_disable_delay2_out => ch1_disable_delay2_out, - \ch1_ioc_irq_set_i__0\ => \ch1_ioc_irq_set_i__0\, - datamover_idle => datamover_idle, - datamover_idle_reg => datamover_idle_reg, - decerr_i_reg => decerr_i_reg, - different_delay => different_delay, - different_thresh => different_thresh, - dly_irq_reg_0 => dly_irq_reg, - dma_err => dma_err, - \dmacr_i_reg[2]_0\ => \dmacr_i_reg[2]\, - err_d1_reg_0 => err_d1_reg, - err_d1_reg_1 => err_d1_reg_0, - err_d1_reg_2 => err_d1_reg_1, - err_irq_reg_0 => err_irq_reg, - halt_reset => halt_reset, - halted_clr_reg => halted_clr_reg, - initial_frame => initial_frame, - ioc_irq_reg_0 => ioc_irq_reg, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - mask_fsync_out_i => mask_fsync_out_i, - mm2s_axi2ip_wrce(1 downto 0) => mm2s_axi2ip_wrce(1 downto 0), - mm2s_dly_irq_set => mm2s_dly_irq_set, - mm2s_halt => mm2s_halt, - mm2s_halt_cmplt => mm2s_halt_cmplt, - mm2s_ioc_irq_set => mm2s_ioc_irq_set, - p_0_out => p_0_out, - p_10_out => p_10_out, - p_17_out => p_17_out, - p_23_out => p_23_out, - p_35_out => p_35_out, - p_44_out => p_44_out, - p_46_out => p_46_out, - p_49_out => p_49_out, - p_68_out(24 downto 0) => \^p_68_out\(25 downto 1), - \p_6_out__1\ => \p_6_out__1\, - p_75_out => p_75_out, - prmry_in => prmry_in, - prmry_resetn_i_reg => prmry_resetn_i_reg_0, - prmry_resetn_i_reg_0(0) => prmry_resetn_i_reg_1(0), - reset_counts_reg_0 => reset_counts_reg, - run_stop_d1_reg => \^p_68_out\(0), - \s_axis_cmd_tdata_reg[63]\ => \^p_67_out\, - \s_axis_cmd_tdata_reg[63]_0\(0) => \s_axis_cmd_tdata_reg[63]\(0), - s_soft_reset_i0 => s_soft_reset_i0, - slverr_i_reg => slverr_i_reg, - stop_i => stop_i - ); -LITE_READ_MUX_I: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_mux - port map ( - in0(31 downto 0) => in0(31 downto 0), - \out\(31 downto 0) => \out\(31 downto 0) - ); -\ptr_ref_i_reg[0]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(2), - D => D(0), - Q => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(0), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(31), + Q => sig_data_skid_reg(31), + R => m_axis_fifo_ainit_nosync ); -\ptr_ref_i_reg[1]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(2), - D => D(1), - Q => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(1), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(3), + Q => sig_data_skid_reg(3), + R => m_axis_fifo_ainit_nosync ); -\ptr_ref_i_reg[2]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(2), - D => D(2), - Q => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(2), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(4), + Q => sig_data_skid_reg(4), + R => m_axis_fifo_ainit_nosync ); -\ptr_ref_i_reg[3]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(2), - D => D(3), - Q => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(3), - R => SR(0) + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(5), + Q => sig_data_skid_reg(5), + R => m_axis_fifo_ainit_nosync ); -\ptr_ref_i_reg[4]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => mm2s_axi2ip_wrce(2), - D => D(4), - Q => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(4), - R => SR(0) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_reset is - port ( - in0 : out STD_LOGIC; - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : out STD_LOGIC; - halt_i_reg_0 : out STD_LOGIC; - prmry_reset2 : out STD_LOGIC; - \fifo_wren__0\ : out STD_LOGIC; - p_8_out : out STD_LOGIC; - \dmacr_i_reg[2]\ : out STD_LOGIC; - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ : out STD_LOGIC; - \cmnds_queued_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - sig_mm2s_dm_prmry_resetn : out STD_LOGIC; - reset_counts_reg : out STD_LOGIC; - sig_s_h_halt_reg_reg : out STD_LOGIC; - scndry_out : out STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - s_axi_lite_aclk : in STD_LOGIC; - m_axis_mm2s_aclk : in STD_LOGIC; - p_68_out : in STD_LOGIC_VECTOR ( 1 downto 0 ); - s_soft_reset_i0 : in STD_LOGIC; - dm2linebuf_mm2s_tvalid : in STD_LOGIC; - fifo_full_i : in STD_LOGIC; - \out\ : in STD_LOGIC; - p_23_out : in STD_LOGIC; - p_35_out : in STD_LOGIC; - mm2s_halt_cmplt : in STD_LOGIC; - mm2s_axi2ip_wrce : in STD_LOGIC_VECTOR ( 0 to 0 ); - D : in STD_LOGIC_VECTOR ( 0 to 0 ); - DIN : in STD_LOGIC_VECTOR ( 0 to 0 ); - dma_err : in STD_LOGIC; - reset_counts : in STD_LOGIC; - sig_rst2all_stop_request : in STD_LOGIC; - \FSM_sequential_dmacntrl_cs_reg[1]\ : in STD_LOGIC; - prmry_in : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_reset : entity is "axi_vdma_reset"; -end Arty_Z7_20_axi_vdma_0_0_axi_vdma_reset; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_reset is - signal \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\ : STD_LOGIC; - signal \GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2\ : STD_LOGIC; - signal \GEN_MIN_FOR_ASYNC.AXIS_RESET_CDC_I_n_1\ : STD_LOGIC; - signal \GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2\ : STD_LOGIC; - signal \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_2\ : STD_LOGIC; - signal \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_3\ : STD_LOGIC; - signal \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_4\ : STD_LOGIC; - signal \GEN_MIN_FOR_ASYNC.LITE_RESET_CDC_I_n_1\ : STD_LOGIC; - signal \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_2_n_0\ : STD_LOGIC; - signal \GEN_MIN_FOR_ASYNC.axis_min_count[0]_i_1_n_0\ : STD_LOGIC; - signal \GEN_MIN_FOR_ASYNC.axis_min_count[1]_i_1_n_0\ : STD_LOGIC; - signal \GEN_MIN_FOR_ASYNC.axis_min_count[2]_i_1_n_0\ : STD_LOGIC; - signal \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0\ : STD_LOGIC; - signal \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_3_n_0\ : STD_LOGIC; - signal \GEN_MIN_FOR_ASYNC.lite_min_count[0]_i_1_n_0\ : STD_LOGIC; - signal \GEN_MIN_FOR_ASYNC.lite_min_count[1]_i_1_n_0\ : STD_LOGIC; - signal \GEN_MIN_FOR_ASYNC.lite_min_count[2]_i_1_n_0\ : STD_LOGIC; - signal \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0\ : STD_LOGIC; - signal \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_3_n_0\ : STD_LOGIC; - signal \GEN_MIN_FOR_ASYNC.prmry_min_count[0]_i_1_n_0\ : STD_LOGIC; - signal \GEN_MIN_FOR_ASYNC.prmry_min_count[1]_i_1_n_0\ : STD_LOGIC; - signal \GEN_MIN_FOR_ASYNC.prmry_min_count[2]_i_1_n_0\ : STD_LOGIC; - signal \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0\ : STD_LOGIC; - signal \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_3_n_0\ : STD_LOGIC; - signal \GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_2\ : STD_LOGIC; - signal \GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_3\ : STD_LOGIC; - signal assert_sftrst_d1 : STD_LOGIC; - signal axis_all_idle : STD_LOGIC; - signal axis_min_assert_sftrst : STD_LOGIC; - signal axis_min_count : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal \^fifo_wren__0\ : STD_LOGIC; - signal halt_i0 : STD_LOGIC; - signal \^halt_i_reg_0\ : STD_LOGIC; - signal halt_reset_i_1_n_0 : STD_LOGIC; - signal lite_all_idle : STD_LOGIC; - signal lite_min_assert_sftrst : STD_LOGIC; - signal lite_min_count : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal min_assert_sftrst : STD_LOGIC; - signal p_11_out : STD_LOGIC; - signal p_1_out : STD_LOGIC; - signal p_2_out : STD_LOGIC; - signal p_3_out : STD_LOGIC; - signal p_4_out : STD_LOGIC; - signal p_6_out : STD_LOGIC; - signal p_8_out_0 : STD_LOGIC; - signal p_in_d1_cdc_from : STD_LOGIC; - signal p_in_d1_cdc_from_0 : STD_LOGIC; - signal prmry_in_xored : STD_LOGIC; - signal prmry_in_xored_1 : STD_LOGIC; - signal prmry_min_assert_sftrst : STD_LOGIC; - signal prmry_min_count : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal resetn_i : STD_LOGIC; - signal run_stop_d1 : STD_LOGIC; - signal s_soft_reset_i : STD_LOGIC; - signal s_soft_reset_i_d1 : STD_LOGIC; - signal soft_reset_d1 : STD_LOGIC; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_2\ : label is "soft_lutpair117"; - attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.axis_min_count[0]_i_1\ : label is "soft_lutpair117"; - attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.axis_min_count[2]_i_1\ : label is "soft_lutpair119"; - attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_3\ : label is "soft_lutpair119"; - attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_i_2\ : label is "soft_lutpair120"; - attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.lite_min_count[0]_i_1\ : label is "soft_lutpair120"; - attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.lite_min_count[1]_i_1\ : label is "soft_lutpair121"; - attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_3\ : label is "soft_lutpair121"; - attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_i_2\ : label is "soft_lutpair116"; - attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.prmry_min_count[0]_i_1\ : label is "soft_lutpair118"; - attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.prmry_min_count[1]_i_1\ : label is "soft_lutpair116"; - attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_3\ : label is "soft_lutpair118"; - attribute SOFT_HLUTNM of \cmnds_queued[7]_i_1\ : label is "soft_lutpair122"; - attribute SOFT_HLUTNM of \gc1.count_d1[6]_i_3\ : label is "soft_lutpair115"; - attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_13\ : label is "soft_lutpair115"; - attribute SOFT_HLUTNM of sig_s_h_halt_reg_i_1 : label is "soft_lutpair122"; -begin - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ <= \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\; - \fifo_wren__0\ <= \^fifo_wren__0\; - halt_i_reg_0 <= \^halt_i_reg_0\; -\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"00000E00" - ) - port map ( - I0 => DIN(0), - I1 => p_23_out, - I2 => \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\, - I3 => \out\, - I4 => \^fifo_wren__0\, - O => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ - ); -\GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I\: entity work.Arty_Z7_20_axi_vdma_0_0_cdc_sync - port map ( - SR(0) => \GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2\, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axis_mm2s_aclk => m_axis_mm2s_aclk, - p_1_out => p_1_out, - p_3_out => p_3_out, - p_in_d1_cdc_from => p_in_d1_cdc_from, - prmry_in_xored => prmry_in_xored - ); -\GEN_MIN_FOR_ASYNC.AXIS_IDLE_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized2\ - port map ( - \FSM_sequential_dmacntrl_cs_reg[1]\ => \FSM_sequential_dmacntrl_cs_reg[1]\, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axis_mm2s_aclk => m_axis_mm2s_aclk, - scndry_out => axis_all_idle - ); -\GEN_MIN_FOR_ASYNC.AXIS_MIN_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized3\ - port map ( - axis_min_assert_sftrst => axis_min_assert_sftrst, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axis_mm2s_aclk => m_axis_mm2s_aclk, - scndry_out => p_2_out - ); -\GEN_MIN_FOR_ASYNC.AXIS_RESET_CDC_I\: entity work.Arty_Z7_20_axi_vdma_0_0_cdc_sync_0 - port map ( - \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_reg\ => \GEN_MIN_FOR_ASYNC.AXIS_RESET_CDC_I_n_1\, - \GEN_MIN_FOR_ASYNC.axis_min_count_reg[2]\ => \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_2_n_0\, - axis_min_assert_sftrst => axis_min_assert_sftrst, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axis_mm2s_aclk => m_axis_mm2s_aclk, - p_1_out => p_1_out, - p_3_out => p_3_out, - s_soft_reset_i => s_soft_reset_i, - s_soft_reset_i_d1 => s_soft_reset_i_d1 + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(6), + Q => sig_data_skid_reg(6), + R => m_axis_fifo_ainit_nosync ); -\GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_reg\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_3\, - Q => min_assert_sftrst, - R => '0' - ); -\GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I\: entity work.Arty_Z7_20_axi_vdma_0_0_cdc_sync_1 - port map ( - SR(0) => \GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2\, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - p_4_out => p_4_out, - p_6_out => p_6_out, - p_in_d1_cdc_from => p_in_d1_cdc_from_0, - prmry_in_xored => prmry_in_xored_1, - s_axi_lite_aclk => s_axi_lite_aclk - ); -\GEN_MIN_FOR_ASYNC.LITE_IDLE_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized0\ - port map ( - \FSM_sequential_dmacntrl_cs_reg[1]\ => \FSM_sequential_dmacntrl_cs_reg[1]\, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - s_axi_lite_aclk => s_axi_lite_aclk, - scndry_out => lite_all_idle - ); -\GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized1\ - port map ( - \GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_reg\ => \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_3\, - \GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_reg\ => \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_4\, - SR(0) => \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_2\, - lite_min_assert_sftrst => lite_min_assert_sftrst, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - min_assert_sftrst => min_assert_sftrst, - p_11_out => p_11_out, - p_in_d1_cdc_from => p_in_d1_cdc_from_0, - p_in_d1_cdc_from_1 => p_in_d1_cdc_from, - prmry_in_xored => prmry_in_xored_1, - prmry_in_xored_0 => prmry_in_xored, - prmry_min_assert_sftrst => prmry_min_assert_sftrst, - s_axi_lite_aclk => s_axi_lite_aclk, - s_soft_reset_i => s_soft_reset_i, - s_soft_reset_i_d1 => s_soft_reset_i_d1, - scndry_out => p_2_out - ); -\GEN_MIN_FOR_ASYNC.LITE_RESET_CDC_I\: entity work.Arty_Z7_20_axi_vdma_0_0_cdc_sync_2 - port map ( - \GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_reg\ => \GEN_MIN_FOR_ASYNC.LITE_RESET_CDC_I_n_1\, - lite_min_assert_sftrst => lite_min_assert_sftrst, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - p_4_out => p_4_out, - p_6_out => p_6_out, - p_8_out_0 => p_8_out_0, - s_axi_lite_aclk => s_axi_lite_aclk, - s_soft_reset_i => s_soft_reset_i, - s_soft_reset_i_d1 => s_soft_reset_i_d1 - ); -\GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_2\: unisim.vcomponents.LUT5 - generic map( - INIT => X"80000000" - ) - port map ( - I0 => axis_min_count(2), - I1 => axis_min_count(0), - I2 => axis_min_assert_sftrst, - I3 => axis_min_count(3), - I4 => axis_min_count(1), - O => \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_2_n_0\ + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(7), + Q => sig_data_skid_reg(7), + R => m_axis_fifo_ainit_nosync ); -\GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_reg\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axis_mm2s_aclk, - CE => '1', - D => \GEN_MIN_FOR_ASYNC.AXIS_RESET_CDC_I_n_1\, - Q => axis_min_assert_sftrst, - R => '0' + CE => sig_s_ready_dup, + D => fifo_dout(8), + Q => sig_data_skid_reg(8), + R => m_axis_fifo_ainit_nosync ); -\GEN_MIN_FOR_ASYNC.axis_min_count[0]_i_1\: unisim.vcomponents.LUT5 +\sig_data_skid_reg_reg[9]\: unisim.vcomponents.FDRE generic map( - INIT => X"8000FFFF" + INIT => '0' ) port map ( - I0 => axis_min_count(1), - I1 => axis_min_count(3), - I2 => axis_min_assert_sftrst, - I3 => axis_min_count(2), - I4 => axis_min_count(0), - O => \GEN_MIN_FOR_ASYNC.axis_min_count[0]_i_1_n_0\ + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(9), + Q => sig_data_skid_reg(9), + R => m_axis_fifo_ainit_nosync ); -\GEN_MIN_FOR_ASYNC.axis_min_count[1]_i_1\: unisim.vcomponents.LUT5 +\sig_last_reg_out_i_1__2\: unisim.vcomponents.LUT3 generic map( - INIT => X"D5AA55AA" + INIT => X"B8" ) port map ( - I0 => axis_min_count(1), - I1 => axis_min_count(3), - I2 => axis_min_assert_sftrst, - I3 => axis_min_count(0), - I4 => axis_min_count(2), - O => \GEN_MIN_FOR_ASYNC.axis_min_count[1]_i_1_n_0\ + I0 => fifo_dout(32), + I1 => sig_s_ready_dup, + I2 => sig_last_skid_reg, + O => sig_last_skid_mux_out ); -\GEN_MIN_FOR_ASYNC.axis_min_count[2]_i_1\: unisim.vcomponents.LUT5 +sig_last_reg_out_reg: unisim.vcomponents.FDRE generic map( - INIT => X"D5FFAA00" + INIT => '0' ) port map ( - I0 => axis_min_count(1), - I1 => axis_min_count(3), - I2 => axis_min_assert_sftrst, - I3 => axis_min_count(0), - I4 => axis_min_count(2), - O => \GEN_MIN_FOR_ASYNC.axis_min_count[2]_i_1_n_0\ + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_last_skid_mux_out, + Q => \^m_axis_mm2s_tlast\, + R => m_axis_fifo_ainit_nosync ); -\GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2\: unisim.vcomponents.LUT6 +sig_last_skid_reg_reg: unisim.vcomponents.FDRE generic map( - INIT => X"EA00AA00AA00AA00" + INIT => '0' ) port map ( - I0 => axis_all_idle, - I1 => axis_min_count(1), - I2 => axis_min_count(3), - I3 => axis_min_assert_sftrst, - I4 => axis_min_count(0), - I5 => axis_min_count(2), - O => \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0\ + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(32), + Q => sig_last_skid_reg, + R => m_axis_fifo_ainit_nosync ); -\GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_3\: unisim.vcomponents.LUT5 +\sig_m_valid_dup_i_1__2\: unisim.vcomponents.LUT6 generic map( - INIT => X"E6CCCCCC" + INIT => X"00000000000075F5" ) port map ( - I0 => axis_min_count(1), - I1 => axis_min_count(3), - I2 => axis_min_assert_sftrst, - I3 => axis_min_count(0), - I4 => axis_min_count(2), - O => \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_3_n_0\ + I0 => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\, + I1 => sig_s_ready_dup, + I2 => sig_m_valid_dup, + I3 => m_axis_mm2s_tready, + I4 => m_axis_fifo_ainit_nosync, + I5 => sig_reset_reg, + O => \sig_m_valid_dup_i_1__2_n_0\ ); -\GEN_MIN_FOR_ASYNC.axis_min_count_reg[0]\: unisim.vcomponents.FDRE +sig_m_valid_dup_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axis_mm2s_aclk, - CE => \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0\, - D => \GEN_MIN_FOR_ASYNC.axis_min_count[0]_i_1_n_0\, - Q => axis_min_count(0), - R => \GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2\ + CE => '1', + D => \sig_m_valid_dup_i_1__2_n_0\, + Q => sig_m_valid_dup, + R => '0' ); -\GEN_MIN_FOR_ASYNC.axis_min_count_reg[1]\: unisim.vcomponents.FDRE +sig_m_valid_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axis_mm2s_aclk, - CE => \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0\, - D => \GEN_MIN_FOR_ASYNC.axis_min_count[1]_i_1_n_0\, - Q => axis_min_count(1), - R => \GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2\ + CE => '1', + D => \sig_m_valid_dup_i_1__2_n_0\, + Q => sig_m_valid_out, + R => '0' ); -\GEN_MIN_FOR_ASYNC.axis_min_count_reg[2]\: unisim.vcomponents.FDRE +sig_reset_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axis_mm2s_aclk, - CE => \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0\, - D => \GEN_MIN_FOR_ASYNC.axis_min_count[2]_i_1_n_0\, - Q => axis_min_count(2), - R => \GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2\ + CE => '1', + D => m_axis_fifo_ainit_nosync, + Q => sig_reset_reg, + R => '0' ); -\GEN_MIN_FOR_ASYNC.axis_min_count_reg[3]\: unisim.vcomponents.FDRE +\sig_s_ready_dup_i_1__2\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"00000000FFFFFFA2" ) port map ( - C => m_axis_mm2s_aclk, - CE => \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0\, - D => \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_3_n_0\, - Q => axis_min_count(3), - R => \GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2\ + I0 => sig_s_ready_dup, + I1 => sig_m_valid_dup, + I2 => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\, + I3 => m_axis_mm2s_tready, + I4 => sig_reset_reg, + I5 => m_axis_fifo_ainit_nosync, + O => \sig_s_ready_dup_i_1__2_n_0\ ); -\GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_i_2\: unisim.vcomponents.LUT5 +sig_s_ready_dup_reg: unisim.vcomponents.FDRE generic map( - INIT => X"80000000" + INIT => '0' ) port map ( - I0 => lite_min_count(2), - I1 => lite_min_count(0), - I2 => lite_min_assert_sftrst, - I3 => lite_min_count(3), - I4 => lite_min_count(1), - O => p_8_out_0 + C => m_axis_mm2s_aclk, + CE => '1', + D => \sig_s_ready_dup_i_1__2_n_0\, + Q => sig_s_ready_dup, + R => '0' ); -\GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_reg\: unisim.vcomponents.FDRE +sig_s_ready_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, + C => m_axis_mm2s_aclk, CE => '1', - D => \GEN_MIN_FOR_ASYNC.LITE_RESET_CDC_I_n_1\, - Q => lite_min_assert_sftrst, + D => \sig_s_ready_dup_i_1__2_n_0\, + Q => sig_s_ready_out, R => '0' ); -\GEN_MIN_FOR_ASYNC.lite_min_count[0]_i_1\: unisim.vcomponents.LUT5 +\sig_user_reg_out[0]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"8000FFFF" + INIT => X"B8" ) port map ( - I0 => lite_min_count(1), - I1 => lite_min_count(3), - I2 => lite_min_assert_sftrst, - I3 => lite_min_count(2), - I4 => lite_min_count(0), - O => \GEN_MIN_FOR_ASYNC.lite_min_count[0]_i_1_n_0\ + I0 => fifo_dout(33), + I1 => sig_s_ready_dup, + I2 => sig_user_skid_reg, + O => sig_user_skid_mux_out ); -\GEN_MIN_FOR_ASYNC.lite_min_count[1]_i_1\: unisim.vcomponents.LUT5 +\sig_user_reg_out_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => X"D5AA55AA" + INIT => '0' ) port map ( - I0 => lite_min_count(1), - I1 => lite_min_count(3), - I2 => lite_min_assert_sftrst, - I3 => lite_min_count(0), - I4 => lite_min_count(2), - O => \GEN_MIN_FOR_ASYNC.lite_min_count[1]_i_1_n_0\ + C => m_axis_mm2s_aclk, + CE => sig_data_reg_out_en, + D => sig_user_skid_mux_out, + Q => m_axis_mm2s_tuser(0), + R => m_axis_fifo_ainit_nosync ); -\GEN_MIN_FOR_ASYNC.lite_min_count[2]_i_1\: unisim.vcomponents.LUT5 +\sig_user_skid_reg_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => X"D5FFAA00" + INIT => '0' ) port map ( - I0 => lite_min_count(1), - I1 => lite_min_count(3), - I2 => lite_min_assert_sftrst, - I3 => lite_min_count(0), - I4 => lite_min_count(2), - O => \GEN_MIN_FOR_ASYNC.lite_min_count[2]_i_1_n_0\ + C => m_axis_mm2s_aclk, + CE => sig_s_ready_dup, + D => fifo_dout(33), + Q => sig_user_skid_reg, + R => m_axis_fifo_ainit_nosync ); -\GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2\: unisim.vcomponents.LUT6 +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_axi_vdma_skid_buf__parameterized0\ is + port ( + sig_reset_reg : out STD_LOGIC; + drop_fsync_d_pulse_gen_fsize_less_err : out STD_LOGIC; + M_VALID : out STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_d1_reg\ : out STD_LOGIC; + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_tuser_to_fsync_out_reg\ : out STD_LOGIC; + p_19_in : out STD_LOGIC; + s2mm_fsize_more_or_sof_late_s : out STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_tuser_to_fsync_out_reg_0\ : out STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_sof_late_err_reg\ : out STD_LOGIC; + s_axis_s2mm_tready : out STD_LOGIC; + M_Last : out STD_LOGIC; + M_Data : out STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axis_fifo_ainit_nosync : in STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC; + s_axis_s2mm_tuser_d1 : in STD_LOGIC; + run_stop_reg : in STD_LOGIC; + delay_s2mm_fsync_core_till_mmap_done_flag : in STD_LOGIC; + \out\ : in STD_LOGIC; + s2mm_fsync_out_i : in STD_LOGIC; + s2mm_fsize_less_err_flag_10 : in STD_LOGIC; + s2mm_tuser_to_fsync_out : in STD_LOGIC; + d_tready_sof_late : in STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\ : in STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_reg\ : in STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\ : in STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_1\ : in STD_LOGIC; + s_axis_s2mm_tvalid : in STD_LOGIC; + d_tready_before_fsync_clr_flag1 : in STD_LOGIC; + s_axis_s2mm_tlast : in STD_LOGIC; + s_axis_s2mm_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axis_s2mm_tuser : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_axi_vdma_skid_buf__parameterized0\ : entity is "axi_vdma_skid_buf"; +end \Arty_Z7_20_axi_vdma_0_0_axi_vdma_skid_buf__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_axi_vdma_skid_buf__parameterized0\ is + signal \^gen_sprt_for_s2mm.gen_flush_sof_tready.s2mm_tuser_to_fsync_out_reg\ : STD_LOGIC; + signal p_97_out : STD_LOGIC; + signal s_axis_s2mm_tready_signal : STD_LOGIC; + signal sig_data_skid_mux_out : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal sig_data_skid_reg : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \sig_last_reg_out_i_1__3_n_0\ : STD_LOGIC; + signal sig_last_skid_mux_out : STD_LOGIC; + signal sig_last_skid_reg : STD_LOGIC; + signal sig_m_valid_dup : STD_LOGIC; + attribute RTL_KEEP : string; + attribute RTL_KEEP of sig_m_valid_dup : signal is "true"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of sig_m_valid_dup : signal is "no"; + signal \sig_m_valid_dup_i_1__3_n_0\ : STD_LOGIC; + signal sig_m_valid_out : STD_LOGIC; + attribute RTL_KEEP of sig_m_valid_out : signal is "true"; + attribute equivalent_register_removal of sig_m_valid_out : signal is "no"; + signal \^sig_reset_reg\ : STD_LOGIC; + signal sig_s_ready_dup : STD_LOGIC; + attribute RTL_KEEP of sig_s_ready_dup : signal is "true"; + attribute equivalent_register_removal of sig_s_ready_dup : signal is "no"; + signal \sig_s_ready_dup_i_1__3_n_0\ : STD_LOGIC; + signal sig_s_ready_out : STD_LOGIC; + attribute RTL_KEEP of sig_s_ready_out : signal is "true"; + attribute equivalent_register_removal of sig_s_ready_out : signal is "no"; + signal sig_user_skid_mux_out : STD_LOGIC; + signal sig_user_skid_reg : STD_LOGIC; + attribute KEEP : string; + attribute KEEP of sig_m_valid_dup_reg : label is "yes"; + attribute equivalent_register_removal of sig_m_valid_dup_reg : label is "no"; + attribute KEEP of sig_m_valid_out_reg : label is "yes"; + attribute equivalent_register_removal of sig_m_valid_out_reg : label is "no"; + attribute KEEP of sig_s_ready_dup_reg : label is "yes"; + attribute equivalent_register_removal of sig_s_ready_dup_reg : label is "no"; + attribute KEEP of sig_s_ready_out_reg : label is "yes"; + attribute equivalent_register_removal of sig_s_ready_out_reg : label is "no"; +begin + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_tuser_to_fsync_out_reg\ <= \^gen_sprt_for_s2mm.gen_flush_sof_tready.s2mm_tuser_to_fsync_out_reg\; + M_VALID <= sig_m_valid_out; + s_axis_s2mm_tready <= sig_s_ready_out; + sig_reset_reg <= \^sig_reset_reg\; +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_1__3\: unisim.vcomponents.LUT6 generic map( - INIT => X"EA00AA00AA00AA00" + INIT => X"33F3000022020000" ) port map ( - I0 => lite_all_idle, - I1 => lite_min_count(1), - I2 => lite_min_count(3), - I3 => lite_min_assert_sftrst, - I4 => lite_min_count(0), - I5 => lite_min_count(2), - O => \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0\ + I0 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_1\, + I1 => s2mm_fsize_less_err_flag_10, + I2 => p_97_out, + I3 => s_axis_s2mm_tuser_d1, + I4 => sig_m_valid_out, + I5 => \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_reg\, + O => s2mm_fsize_more_or_sof_late_s ); -\GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_3\: unisim.vcomponents.LUT5 +\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.drop_fsync_d_pulse_gen_fsize_less_err_d1_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"E6CCCCCC" + INIT => X"20000000" ) port map ( - I0 => lite_min_count(1), - I1 => lite_min_count(3), - I2 => lite_min_assert_sftrst, - I3 => lite_min_count(0), - I4 => lite_min_count(2), - O => \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_3_n_0\ + I0 => p_97_out, + I1 => s_axis_s2mm_tuser_d1, + I2 => sig_m_valid_out, + I3 => run_stop_reg, + I4 => delay_s2mm_fsync_core_till_mmap_done_flag, + O => drop_fsync_d_pulse_gen_fsize_less_err ); -\GEN_MIN_FOR_ASYNC.lite_min_count_reg[0]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_i_2\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"DF" ) port map ( - C => s_axi_lite_aclk, - CE => \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0\, - D => \GEN_MIN_FOR_ASYNC.lite_min_count[0]_i_1_n_0\, - Q => lite_min_count(0), - R => \GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2\ + I0 => p_97_out, + I1 => s_axis_s2mm_tuser_d1, + I2 => sig_m_valid_out, + O => \^gen_sprt_for_s2mm.gen_flush_sof_tready.s2mm_tuser_to_fsync_out_reg\ ); -\GEN_MIN_FOR_ASYNC.lite_min_count_reg[1]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_d1_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"A2AAAAAA00000000" ) port map ( - C => s_axi_lite_aclk, - CE => \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0\, - D => \GEN_MIN_FOR_ASYNC.lite_min_count[1]_i_1_n_0\, - Q => lite_min_count(1), - R => \GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2\ + I0 => \out\, + I1 => p_97_out, + I2 => s_axis_s2mm_tuser_d1, + I3 => sig_m_valid_out, + I4 => run_stop_reg, + I5 => delay_s2mm_fsync_core_till_mmap_done_flag, + O => \GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_d1_reg\ ); -\GEN_MIN_FOR_ASYNC.lite_min_count_reg[2]\: unisim.vcomponents.FDRE +\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_sof_late_err_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000200" + ) + port map ( + I0 => sig_m_valid_out, + I1 => p_97_out, + I2 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\, + I3 => \out\, + I4 => d_tready_sof_late, + I5 => d_tready_before_fsync_clr_flag1, + O => \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_sof_late_err_reg\ + ); +\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_tuser_to_fsync_out_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000AB00" + ) + port map ( + I0 => s2mm_tuser_to_fsync_out, + I1 => \^gen_sprt_for_s2mm.gen_flush_sof_tready.s2mm_tuser_to_fsync_out_reg\, + I2 => d_tready_before_fsync_clr_flag1, + I3 => \out\, + I4 => s2mm_fsync_out_i, + O => \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_tuser_to_fsync_out_reg_0\ + ); +\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s_axis_s2mm_tuser_d1_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => p_97_out, + I1 => sig_m_valid_out, + O => p_19_in + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F4F444F4F4F4F4F4" + ) + port map ( + I0 => s2mm_fsync_out_i, + I1 => s_axis_fifo_ainit_nosync, + I2 => s2mm_fsize_less_err_flag_10, + I3 => p_97_out, + I4 => s_axis_s2mm_tuser_d1, + I5 => sig_m_valid_out, + O => SR(0) + ); +\sig_data_reg_out[0]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"CA" + ) + port map ( + I0 => sig_data_skid_reg(0), + I1 => s_axis_s2mm_tdata(0), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(0) + ); +\sig_data_reg_out[1]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"CA" + ) + port map ( + I0 => sig_data_skid_reg(1), + I1 => s_axis_s2mm_tdata(1), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(1) + ); +\sig_data_reg_out[2]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"CA" + ) + port map ( + I0 => sig_data_skid_reg(2), + I1 => s_axis_s2mm_tdata(2), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(2) + ); +\sig_data_reg_out[3]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"CA" + ) + port map ( + I0 => sig_data_skid_reg(3), + I1 => s_axis_s2mm_tdata(3), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(3) + ); +\sig_data_reg_out[4]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"CA" + ) + port map ( + I0 => sig_data_skid_reg(4), + I1 => s_axis_s2mm_tdata(4), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(4) + ); +\sig_data_reg_out[5]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"CA" + ) + port map ( + I0 => sig_data_skid_reg(5), + I1 => s_axis_s2mm_tdata(5), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(5) + ); +\sig_data_reg_out[6]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"CA" + ) + port map ( + I0 => sig_data_skid_reg(6), + I1 => s_axis_s2mm_tdata(6), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(6) + ); +\sig_data_reg_out[7]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"CA" + ) + port map ( + I0 => sig_data_skid_reg(7), + I1 => s_axis_s2mm_tdata(7), + I2 => sig_s_ready_dup, + O => sig_data_skid_mux_out(7) + ); +\sig_data_reg_out_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0\, - D => \GEN_MIN_FOR_ASYNC.lite_min_count[2]_i_1_n_0\, - Q => lite_min_count(2), - R => \GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2\ + C => s_axis_s2mm_aclk, + CE => \sig_last_reg_out_i_1__3_n_0\, + D => sig_data_skid_mux_out(0), + Q => M_Data(0), + R => s_axis_fifo_ainit_nosync ); -\GEN_MIN_FOR_ASYNC.lite_min_count_reg[3]\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => s_axi_lite_aclk, - CE => \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0\, - D => \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_3_n_0\, - Q => lite_min_count(3), - R => \GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2\ + C => s_axis_s2mm_aclk, + CE => \sig_last_reg_out_i_1__3_n_0\, + D => sig_data_skid_mux_out(1), + Q => M_Data(1), + R => s_axis_fifo_ainit_nosync ); -\GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_i_2\: unisim.vcomponents.LUT5 +\sig_data_reg_out_reg[2]\: unisim.vcomponents.FDRE generic map( - INIT => X"80000000" + INIT => '0' ) port map ( - I0 => prmry_min_count(2), - I1 => prmry_min_count(0), - I2 => prmry_min_assert_sftrst, - I3 => prmry_min_count(3), - I4 => prmry_min_count(1), - O => p_11_out + C => s_axis_s2mm_aclk, + CE => \sig_last_reg_out_i_1__3_n_0\, + D => sig_data_skid_mux_out(2), + Q => M_Data(2), + R => s_axis_fifo_ainit_nosync ); -\GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_reg\: unisim.vcomponents.FDRE +\sig_data_reg_out_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_4\, - Q => prmry_min_assert_sftrst, - R => '0' + C => s_axis_s2mm_aclk, + CE => \sig_last_reg_out_i_1__3_n_0\, + D => sig_data_skid_mux_out(3), + Q => M_Data(3), + R => s_axis_fifo_ainit_nosync ); -\GEN_MIN_FOR_ASYNC.prmry_min_count[0]_i_1\: unisim.vcomponents.LUT5 +\sig_data_reg_out_reg[4]\: unisim.vcomponents.FDRE generic map( - INIT => X"8000FFFF" + INIT => '0' ) port map ( - I0 => prmry_min_count(1), - I1 => prmry_min_count(3), - I2 => prmry_min_assert_sftrst, - I3 => prmry_min_count(2), - I4 => prmry_min_count(0), - O => \GEN_MIN_FOR_ASYNC.prmry_min_count[0]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => \sig_last_reg_out_i_1__3_n_0\, + D => sig_data_skid_mux_out(4), + Q => M_Data(4), + R => s_axis_fifo_ainit_nosync ); -\GEN_MIN_FOR_ASYNC.prmry_min_count[1]_i_1\: unisim.vcomponents.LUT5 +\sig_data_reg_out_reg[5]\: unisim.vcomponents.FDRE generic map( - INIT => X"D5AA55AA" + INIT => '0' ) port map ( - I0 => prmry_min_count(1), - I1 => prmry_min_count(3), - I2 => prmry_min_assert_sftrst, - I3 => prmry_min_count(0), - I4 => prmry_min_count(2), - O => \GEN_MIN_FOR_ASYNC.prmry_min_count[1]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => \sig_last_reg_out_i_1__3_n_0\, + D => sig_data_skid_mux_out(5), + Q => M_Data(5), + R => s_axis_fifo_ainit_nosync ); -\GEN_MIN_FOR_ASYNC.prmry_min_count[2]_i_1\: unisim.vcomponents.LUT5 +\sig_data_reg_out_reg[6]\: unisim.vcomponents.FDRE generic map( - INIT => X"D5FFAA00" + INIT => '0' ) port map ( - I0 => prmry_min_count(1), - I1 => prmry_min_count(3), - I2 => prmry_min_assert_sftrst, - I3 => prmry_min_count(0), - I4 => prmry_min_count(2), - O => \GEN_MIN_FOR_ASYNC.prmry_min_count[2]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => \sig_last_reg_out_i_1__3_n_0\, + D => sig_data_skid_mux_out(6), + Q => M_Data(6), + R => s_axis_fifo_ainit_nosync ); -\GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2\: unisim.vcomponents.LUT6 +\sig_data_reg_out_reg[7]\: unisim.vcomponents.FDRE generic map( - INIT => X"EA00AA00AA00AA00" + INIT => '0' ) port map ( - I0 => \FSM_sequential_dmacntrl_cs_reg[1]\, - I1 => prmry_min_count(1), - I2 => prmry_min_count(3), - I3 => prmry_min_assert_sftrst, - I4 => prmry_min_count(0), - I5 => prmry_min_count(2), - O => \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0\ + C => s_axis_s2mm_aclk, + CE => \sig_last_reg_out_i_1__3_n_0\, + D => sig_data_skid_mux_out(7), + Q => M_Data(7), + R => s_axis_fifo_ainit_nosync ); -\GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_3\: unisim.vcomponents.LUT5 +\sig_data_skid_reg_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => X"E6CCCCCC" + INIT => '0' ) port map ( - I0 => prmry_min_count(1), - I1 => prmry_min_count(3), - I2 => prmry_min_assert_sftrst, - I3 => prmry_min_count(0), - I4 => prmry_min_count(2), - O => \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_3_n_0\ + C => s_axis_s2mm_aclk, + CE => sig_s_ready_dup, + D => s_axis_s2mm_tdata(0), + Q => sig_data_skid_reg(0), + R => s_axis_fifo_ainit_nosync ); -\GEN_MIN_FOR_ASYNC.prmry_min_count_reg[0]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0\, - D => \GEN_MIN_FOR_ASYNC.prmry_min_count[0]_i_1_n_0\, - Q => prmry_min_count(0), - R => \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_2\ + C => s_axis_s2mm_aclk, + CE => sig_s_ready_dup, + D => s_axis_s2mm_tdata(1), + Q => sig_data_skid_reg(1), + R => s_axis_fifo_ainit_nosync ); -\GEN_MIN_FOR_ASYNC.prmry_min_count_reg[1]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0\, - D => \GEN_MIN_FOR_ASYNC.prmry_min_count[1]_i_1_n_0\, - Q => prmry_min_count(1), - R => \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_2\ + C => s_axis_s2mm_aclk, + CE => sig_s_ready_dup, + D => s_axis_s2mm_tdata(2), + Q => sig_data_skid_reg(2), + R => s_axis_fifo_ainit_nosync ); -\GEN_MIN_FOR_ASYNC.prmry_min_count_reg[2]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0\, - D => \GEN_MIN_FOR_ASYNC.prmry_min_count[2]_i_1_n_0\, - Q => prmry_min_count(2), - R => \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_2\ + C => s_axis_s2mm_aclk, + CE => sig_s_ready_dup, + D => s_axis_s2mm_tdata(3), + Q => sig_data_skid_reg(3), + R => s_axis_fifo_ainit_nosync ); -\GEN_MIN_FOR_ASYNC.prmry_min_count_reg[3]\: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0\, - D => \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_3_n_0\, - Q => prmry_min_count(3), - R => \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_2\ + C => s_axis_s2mm_aclk, + CE => sig_s_ready_dup, + D => s_axis_s2mm_tdata(4), + Q => sig_data_skid_reg(4), + R => s_axis_fifo_ainit_nosync ); -\GEN_RESET_FOR_ASYNC.AXIS_RESET_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized5\ - port map ( - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axis_mm2s_aclk => m_axis_mm2s_aclk, - prmry_in => resetn_i, - scndry_out => scndry_out +\sig_data_skid_reg_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => sig_s_ready_dup, + D => s_axis_s2mm_tdata(5), + Q => sig_data_skid_reg(5), + R => s_axis_fifo_ainit_nosync ); -\GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized4\ - port map ( - D(0) => D(0), - assert_sftrst_d1 => assert_sftrst_d1, - \dmacr_i_reg[2]\ => \dmacr_i_reg[2]\, - halt_i0 => halt_i0, - halt_i_reg => \GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_3\, - halt_i_reg_0 => \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\, - halt_reset_reg => \^halt_i_reg_0\, - hrd_resetn_i_reg => prmry_in, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - min_assert_sftrst => min_assert_sftrst, - mm2s_axi2ip_wrce(0) => mm2s_axi2ip_wrce(0), - \out\ => \out\, - p_35_out => p_35_out, - p_68_out(1 downto 0) => p_68_out(1 downto 0), - prmry_in => resetn_i, - prmry_reset2 => prmry_reset2, - reset_counts => reset_counts, - reset_counts_reg => reset_counts_reg, - run_stop_d1_reg => \GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_2\, - s_axi_lite_aclk => s_axi_lite_aclk, - s_soft_reset_i => s_soft_reset_i, - \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ => sig_mm2s_dm_prmry_resetn +\sig_data_skid_reg_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => sig_s_ready_dup, + D => s_axis_s2mm_tdata(6), + Q => sig_data_skid_reg(6), + R => s_axis_fifo_ainit_nosync ); -assert_sftrst_d1_reg: unisim.vcomponents.FDRE +\sig_data_skid_reg_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => min_assert_sftrst, - Q => assert_sftrst_d1, - R => '0' + C => s_axis_s2mm_aclk, + CE => sig_s_ready_dup, + D => s_axis_s2mm_tdata(7), + Q => sig_data_skid_reg(7), + R => s_axis_fifo_ainit_nosync ); -\cmnds_queued[7]_i_1\: unisim.vcomponents.LUT4 +\sig_last_reg_out_i_1__3\: unisim.vcomponents.LUT2 generic map( - INIT => X"FEFF" + INIT => X"B" ) port map ( - I0 => \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\, - I1 => p_68_out(1), - I2 => dma_err, - I3 => \out\, - O => \cmnds_queued_reg[7]\(0) + I0 => s_axis_s2mm_tready_signal, + I1 => sig_m_valid_dup, + O => \sig_last_reg_out_i_1__3_n_0\ ); -\gc1.count_d1[6]_i_3\: unisim.vcomponents.LUT4 +\sig_last_reg_out_i_2__0\: unisim.vcomponents.LUT3 generic map( - INIT => X"0010" + INIT => X"B8" ) port map ( - I0 => p_23_out, - I1 => \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\, - I2 => \out\, - I3 => fifo_full_i, - O => p_8_out + I0 => s_axis_s2mm_tlast, + I1 => sig_s_ready_dup, + I2 => sig_last_skid_reg, + O => sig_last_skid_mux_out ); -\gf36e1_inst.sngfifo36e1_i_13\: unisim.vcomponents.LUT5 +\sig_last_reg_out_i_3__0\: unisim.vcomponents.LUT6 generic map( - INIT => X"00000020" + INIT => X"FFFF0400FFFFFFFF" ) port map ( - I0 => dm2linebuf_mm2s_tvalid, - I1 => fifo_full_i, - I2 => \out\, - I3 => \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\, - I4 => p_23_out, - O => \^fifo_wren__0\ + I0 => s2mm_tuser_to_fsync_out, + I1 => d_tready_sof_late, + I2 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\, + I3 => \^gen_sprt_for_s2mm.gen_flush_sof_tready.s2mm_tuser_to_fsync_out_reg\, + I4 => \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_reg\, + I5 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\, + O => s_axis_s2mm_tready_signal ); -halt_i_i_2: unisim.vcomponents.LUT5 +sig_last_reg_out_reg: unisim.vcomponents.FDRE generic map( - INIT => X"AEAEFFAE" + INIT => '0' ) port map ( - I0 => p_35_out, - I1 => run_stop_d1, - I2 => p_68_out(0), - I3 => p_68_out(1), - I4 => soft_reset_d1, - O => halt_i0 + C => s_axis_s2mm_aclk, + CE => \sig_last_reg_out_i_1__3_n_0\, + D => sig_last_skid_mux_out, + Q => M_Last, + R => s_axis_fifo_ainit_nosync ); -halt_i_reg: unisim.vcomponents.FDRE +sig_last_skid_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_3\, - Q => \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\, - R => '0' + C => s_axis_s2mm_aclk, + CE => sig_s_ready_dup, + D => s_axis_s2mm_tlast, + Q => sig_last_skid_reg, + R => s_axis_fifo_ainit_nosync ); -halt_reset_i_1: unisim.vcomponents.LUT6 +\sig_m_valid_dup_i_1__3\: unisim.vcomponents.LUT6 generic map( - INIT => X"222222222222F222" + INIT => X"000000000000FF2A" ) port map ( - I0 => \^halt_i_reg_0\, - I1 => p_68_out(0), - I2 => \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\, - I3 => mm2s_halt_cmplt, - I4 => p_68_out(1), - I5 => p_35_out, - O => halt_reset_i_1_n_0 + I0 => sig_m_valid_dup, + I1 => sig_s_ready_dup, + I2 => s_axis_s2mm_tready_signal, + I3 => s_axis_s2mm_tvalid, + I4 => s_axis_fifo_ainit_nosync, + I5 => \^sig_reset_reg\, + O => \sig_m_valid_dup_i_1__3_n_0\ ); -halt_reset_reg: unisim.vcomponents.FDRE +sig_m_valid_dup_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, + C => s_axis_s2mm_aclk, CE => '1', - D => halt_reset_i_1_n_0, - Q => \^halt_i_reg_0\, + D => \sig_m_valid_dup_i_1__3_n_0\, + Q => sig_m_valid_dup, R => '0' ); -prmry_resetn_i_reg: unisim.vcomponents.FDRE +sig_m_valid_out_reg: unisim.vcomponents.FDRE generic map( - INIT => '1' + INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, + C => s_axis_s2mm_aclk, CE => '1', - D => resetn_i, - Q => in0, + D => \sig_m_valid_dup_i_1__3_n_0\, + Q => sig_m_valid_out, R => '0' ); -run_stop_d1_reg: unisim.vcomponents.FDRE +sig_reset_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, + C => s_axis_s2mm_aclk, CE => '1', - D => \GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_2\, - Q => run_stop_d1, + D => s_axis_fifo_ainit_nosync, + Q => \^sig_reset_reg\, R => '0' ); -s_soft_reset_i_d1_reg: unisim.vcomponents.FDRE +\sig_s_ready_dup_i_1__3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FFFFBFAA" + ) + port map ( + I0 => s_axis_s2mm_tready_signal, + I1 => s_axis_s2mm_tvalid, + I2 => sig_m_valid_dup, + I3 => sig_s_ready_dup, + I4 => \^sig_reset_reg\, + I5 => s_axis_fifo_ainit_nosync, + O => \sig_s_ready_dup_i_1__3_n_0\ + ); +sig_s_ready_dup_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, + C => s_axis_s2mm_aclk, CE => '1', - D => s_soft_reset_i, - Q => s_soft_reset_i_d1, + D => \sig_s_ready_dup_i_1__3_n_0\, + Q => sig_s_ready_dup, R => '0' ); -s_soft_reset_i_reg: unisim.vcomponents.FDRE +sig_s_ready_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, + C => s_axis_s2mm_aclk, CE => '1', - D => s_soft_reset_i0, - Q => s_soft_reset_i, + D => \sig_s_ready_dup_i_1__3_n_0\, + Q => sig_s_ready_out, R => '0' ); -sig_s_h_halt_reg_i_1: unisim.vcomponents.LUT2 +\sig_user_reg_out[0]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => X"E" + INIT => X"B8" ) port map ( - I0 => \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\, - I1 => sig_rst2all_stop_request, - O => sig_s_h_halt_reg_reg + I0 => s_axis_s2mm_tuser(0), + I1 => sig_s_ready_dup, + I2 => sig_user_skid_reg, + O => sig_user_skid_mux_out ); -soft_reset_d1_reg: unisim.vcomponents.FDRE +\sig_user_reg_out_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => p_68_out(1), - Q => soft_reset_d1, - R => '0' + C => s_axis_s2mm_aclk, + CE => \sig_last_reg_out_i_1__3_n_0\, + D => sig_user_skid_mux_out, + Q => p_97_out, + R => s_axis_fifo_ainit_nosync + ); +\sig_user_skid_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => sig_s_ready_dup, + D => s_axis_s2mm_tuser(0), + Q => sig_user_skid_reg, + R => s_axis_fifo_ainit_nosync ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_vid_cdc is +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_sm is port ( - p_in_d1_cdc_from : out STD_LOGIC; - p_17_out : out STD_LOGIC; - p_in_d1_cdc_from_0 : out STD_LOGIC; - p_15_out : out STD_LOGIC; - all_lines_xfred : out STD_LOGIC; - mm2s_frame_ptr_out : out STD_LOGIC_VECTOR ( 5 downto 0 ); + tstvect_fsync_d2 : out STD_LOGIC; + tstvect_fsync_d1 : out STD_LOGIC; + frame_sync_reg : out STD_LOGIC; + s_axis_cmd_tvalid_reg : out STD_LOGIC; + zero_vsize_err : out STD_LOGIC; + zero_hsize_err : out STD_LOGIC; + \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + load_new_addr : out STD_LOGIC; + halted_set_i0 : out STD_LOGIC; + p_39_out : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 48 downto 0 ); + dma_interr_reg : out STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - prmry_in_xored : in STD_LOGIC; - m_axis_mm2s_aclk : in STD_LOGIC; - prmry_resetn_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_mm2s_aclk : in STD_LOGIC; - prmry_in_xored_1 : in STD_LOGIC; - in0 : in STD_LOGIC_VECTOR ( 0 to 0 ); - mm2s_frame_ptr_in : in STD_LOGIC_VECTOR ( 5 downto 0 ); - \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]\ : in STD_LOGIC + mm2s_all_lines_xfred : in STD_LOGIC; + zero_vsize_err0 : in STD_LOGIC; + zero_hsize_err0 : in STD_LOGIC; + O : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \stride_vid_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \stride_vid_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \stride_vid_reg[15]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + p_24_out : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][30]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][29]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][28]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][27]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][26]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][25]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][24]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][23]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][22]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][21]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][20]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][19]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][18]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][17]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][16]\ : in STD_LOGIC; + s_axis_cmd_tvalid_reg_0 : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 12 downto 0 ); + mm2s_prmry_resetn : in STD_LOGIC; + mm2s_fifo_pipe_empty : in STD_LOGIC; + datamover_idle : in STD_LOGIC; + p_71_out : in STD_LOGIC_VECTOR ( 0 to 0 ); + \dmacr_i_reg[2]\ : in STD_LOGIC; + halt_i_reg : in STD_LOGIC; + dma_err : in STD_LOGIC; + p_77_out : in STD_LOGIC; + mm2s_halt : in STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + p_58_out : in STD_LOGIC; + CO : in STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + mm2s_axi2ip_wrce : in STD_LOGIC_VECTOR ( 0 to 0 ); + interr_i_reg : in STD_LOGIC; + dma_interr_reg_0 : in STD_LOGIC; + \hsize_vid_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + err_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_vid_cdc : entity is "axi_vdma_vid_cdc"; -end Arty_Z7_20_axi_vdma_0_0_axi_vdma_vid_cdc; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_sm : entity is "axi_vdma_sm"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_sm; -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_vid_cdc is - signal frame_ptr_in_d1_cdc_tig : STD_LOGIC_VECTOR ( 5 downto 0 ); - attribute async_reg : string; - attribute async_reg of frame_ptr_in_d1_cdc_tig : signal is "true"; - signal frame_ptr_in_d2 : STD_LOGIC_VECTOR ( 5 downto 0 ); - attribute async_reg of frame_ptr_in_d2 : signal is "true"; - signal frame_ptr_out_d1_cdc_tig : STD_LOGIC_VECTOR ( 5 downto 0 ); - attribute async_reg of frame_ptr_out_d1_cdc_tig : signal is "true"; - signal frame_ptr_out_d2 : STD_LOGIC_VECTOR ( 5 downto 0 ); - attribute async_reg of frame_ptr_out_d2 : signal is "true"; - signal othrchnl_frame_ptr_in_d1_cdc_tig : STD_LOGIC_VECTOR ( 5 downto 0 ); - attribute async_reg of othrchnl_frame_ptr_in_d1_cdc_tig : signal is "true"; - signal othrchnl_frame_ptr_in_d2 : STD_LOGIC_VECTOR ( 5 downto 0 ); - attribute async_reg of othrchnl_frame_ptr_in_d2 : signal is "true"; - signal p_2_in : STD_LOGIC_VECTOR ( 5 downto 0 ); - attribute ASYNC_REG_boolean : boolean; - attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[0]\ : label is std.standard.true; - attribute KEEP : string; - attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[0]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[1]\ : label is std.standard.true; - attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[1]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[2]\ : label is std.standard.true; - attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[2]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[3]\ : label is std.standard.true; - attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[3]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[4]\ : label is std.standard.true; - attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[4]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[5]\ : label is std.standard.true; - attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[5]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[0]\ : label is std.standard.true; - attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[0]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[1]\ : label is std.standard.true; - attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[1]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[2]\ : label is std.standard.true; - attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[2]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[3]\ : label is std.standard.true; - attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[3]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[4]\ : label is std.standard.true; - attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[4]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[5]\ : label is std.standard.true; - attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[5]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[0]\ : label is std.standard.true; - attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[0]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[1]\ : label is std.standard.true; - attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[1]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2]\ : label is std.standard.true; - attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[3]\ : label is std.standard.true; - attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[3]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[4]\ : label is std.standard.true; - attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[4]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[5]\ : label is std.standard.true; - attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[5]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[0]\ : label is std.standard.true; - attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[0]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[1]\ : label is std.standard.true; - attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[1]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[2]\ : label is std.standard.true; - attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[2]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[3]\ : label is std.standard.true; - attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[3]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[4]\ : label is std.standard.true; - attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[4]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[5]\ : label is std.standard.true; - attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[5]\ : label is "yes"; +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_sm is + signal \FSM_sequential_dmacntrl_cs[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_dmacntrl_cs[0]_i_2_n_0\ : STD_LOGIC; + signal \FSM_sequential_dmacntrl_cs[0]_i_3_n_0\ : STD_LOGIC; + signal \FSM_sequential_dmacntrl_cs[1]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_dmacntrl_cs[1]_i_2_n_0\ : STD_LOGIC; + signal \FSM_sequential_dmacntrl_cs[1]_i_3_n_0\ : STD_LOGIC; + signal \FSM_sequential_dmacntrl_cs[2]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_dmacntrl_cs[2]_i_2_n_0\ : STD_LOGIC; + signal \FSM_sequential_dmacntrl_cs[2]_i_3_n_0\ : STD_LOGIC; + signal \FSM_sequential_dmacntrl_cs[2]_i_4__0_n_0\ : STD_LOGIC; + signal \FSM_sequential_dmacntrl_cs[2]_i_5_n_0\ : STD_LOGIC; + signal \FSM_sequential_dmacntrl_cs[2]_i_6_n_0\ : STD_LOGIC; + signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_3_n_0\ : STD_LOGIC; + signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_4_n_0\ : STD_LOGIC; + signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_5_n_0\ : STD_LOGIC; + signal \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_i_1_n_0\ : STD_LOGIC; + signal \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg_n_0\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data[23]_i_1_n_0\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\ : STD_LOGIC; + signal \^gen_normal_dm_command.cmnd_data_reg[47]_0\ : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[0]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[10]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[11]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[12]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[13]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[14]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[15]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[1]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[23]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[2]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[32]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[33]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[34]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[35]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[36]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[37]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[38]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[39]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[3]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[40]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[41]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[42]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[43]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[44]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[45]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[46]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[47]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[48]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[49]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[4]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[50]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[51]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[52]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[53]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[54]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[55]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[56]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[57]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[58]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[59]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[5]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[60]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[61]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[62]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[63]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[6]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[7]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[8]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[9]\ : STD_LOGIC; + signal all_lines_xfred_d1 : STD_LOGIC; + signal \cmnds_queued[0]_i_1_n_0\ : STD_LOGIC; + signal \cmnds_queued[4]_i_2_n_0\ : STD_LOGIC; + signal \cmnds_queued[4]_i_3_n_0\ : STD_LOGIC; + signal \cmnds_queued[4]_i_4_n_0\ : STD_LOGIC; + signal \cmnds_queued[4]_i_5_n_0\ : STD_LOGIC; + signal \cmnds_queued[4]_i_6_n_0\ : STD_LOGIC; + signal \cmnds_queued[7]_i_2_n_0\ : STD_LOGIC; + signal \cmnds_queued[7]_i_4_n_0\ : STD_LOGIC; + signal \cmnds_queued[7]_i_5_n_0\ : STD_LOGIC; + signal \cmnds_queued[7]_i_6_n_0\ : STD_LOGIC; + signal \cmnds_queued_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \cmnds_queued_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \cmnds_queued_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \cmnds_queued_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \cmnds_queued_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \cmnds_queued_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \cmnds_queued_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \cmnds_queued_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \cmnds_queued_reg[7]_i_3_n_2\ : STD_LOGIC; + signal \cmnds_queued_reg[7]_i_3_n_3\ : STD_LOGIC; + signal \cmnds_queued_reg[7]_i_3_n_5\ : STD_LOGIC; + signal \cmnds_queued_reg[7]_i_3_n_6\ : STD_LOGIC; + signal \cmnds_queued_reg[7]_i_3_n_7\ : STD_LOGIC; + signal \cmnds_queued_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \dm_address[0]_i_1_n_0\ : STD_LOGIC; + signal \dm_address[16]_i_2_n_0\ : STD_LOGIC; + signal \dm_address[16]_i_3_n_0\ : STD_LOGIC; + signal \dm_address[16]_i_4_n_0\ : STD_LOGIC; + signal \dm_address[16]_i_5_n_0\ : STD_LOGIC; + signal \dm_address[20]_i_2_n_0\ : STD_LOGIC; + signal \dm_address[20]_i_3_n_0\ : STD_LOGIC; + signal \dm_address[20]_i_4_n_0\ : STD_LOGIC; + signal \dm_address[20]_i_5_n_0\ : STD_LOGIC; + signal \dm_address[24]_i_2_n_0\ : STD_LOGIC; + signal \dm_address[24]_i_3_n_0\ : STD_LOGIC; + signal \dm_address[24]_i_4_n_0\ : STD_LOGIC; + signal \dm_address[24]_i_5_n_0\ : STD_LOGIC; + signal \dm_address[28]_i_2_n_0\ : STD_LOGIC; + signal \dm_address[28]_i_3_n_0\ : STD_LOGIC; + signal \dm_address[28]_i_4_n_0\ : STD_LOGIC; + signal \dm_address[28]_i_5_n_0\ : STD_LOGIC; + signal dm_address_reg : STD_LOGIC_VECTOR ( 31 downto 16 ); + signal \dm_address_reg[16]_i_1_n_0\ : STD_LOGIC; + signal \dm_address_reg[16]_i_1_n_1\ : STD_LOGIC; + signal \dm_address_reg[16]_i_1_n_2\ : STD_LOGIC; + signal \dm_address_reg[16]_i_1_n_3\ : STD_LOGIC; + signal \dm_address_reg[16]_i_1_n_4\ : STD_LOGIC; + signal \dm_address_reg[16]_i_1_n_5\ : STD_LOGIC; + signal \dm_address_reg[16]_i_1_n_6\ : STD_LOGIC; + signal \dm_address_reg[16]_i_1_n_7\ : STD_LOGIC; + signal \dm_address_reg[20]_i_1_n_0\ : STD_LOGIC; + signal \dm_address_reg[20]_i_1_n_1\ : STD_LOGIC; + signal \dm_address_reg[20]_i_1_n_2\ : STD_LOGIC; + signal \dm_address_reg[20]_i_1_n_3\ : STD_LOGIC; + signal \dm_address_reg[20]_i_1_n_4\ : STD_LOGIC; + signal \dm_address_reg[20]_i_1_n_5\ : STD_LOGIC; + signal \dm_address_reg[20]_i_1_n_6\ : STD_LOGIC; + signal \dm_address_reg[20]_i_1_n_7\ : STD_LOGIC; + signal \dm_address_reg[24]_i_1_n_0\ : STD_LOGIC; + signal \dm_address_reg[24]_i_1_n_1\ : STD_LOGIC; + signal \dm_address_reg[24]_i_1_n_2\ : STD_LOGIC; + signal \dm_address_reg[24]_i_1_n_3\ : STD_LOGIC; + signal \dm_address_reg[24]_i_1_n_4\ : STD_LOGIC; + signal \dm_address_reg[24]_i_1_n_5\ : STD_LOGIC; + signal \dm_address_reg[24]_i_1_n_6\ : STD_LOGIC; + signal \dm_address_reg[24]_i_1_n_7\ : STD_LOGIC; + signal \dm_address_reg[28]_i_1_n_1\ : STD_LOGIC; + signal \dm_address_reg[28]_i_1_n_2\ : STD_LOGIC; + signal \dm_address_reg[28]_i_1_n_3\ : STD_LOGIC; + signal \dm_address_reg[28]_i_1_n_4\ : STD_LOGIC; + signal \dm_address_reg[28]_i_1_n_5\ : STD_LOGIC; + signal \dm_address_reg[28]_i_1_n_6\ : STD_LOGIC; + signal \dm_address_reg[28]_i_1_n_7\ : STD_LOGIC; + signal dmacntrl_cs : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute RTL_KEEP : string; + attribute RTL_KEEP of dmacntrl_cs : signal is "yes"; + signal frame_sync_d3 : STD_LOGIC; + signal \^frame_sync_reg\ : STD_LOGIC; + signal \^load_new_addr\ : STD_LOGIC; + signal p_1_in : STD_LOGIC; + signal \^p_39_out\ : STD_LOGIC; + signal \^s_axis_cmd_tvalid_reg\ : STD_LOGIC; + signal \^tstvect_fsync_d1\ : STD_LOGIC; + signal \^tstvect_fsync_d2\ : STD_LOGIC; + signal \vert_count[0]_i_10_n_0\ : STD_LOGIC; + signal \vert_count[0]_i_11_n_0\ : STD_LOGIC; + signal \vert_count[0]_i_1_n_0\ : STD_LOGIC; + signal \vert_count[0]_i_4_n_0\ : STD_LOGIC; + signal \vert_count[0]_i_5_n_0\ : STD_LOGIC; + signal \vert_count[0]_i_6_n_0\ : STD_LOGIC; + signal \vert_count[0]_i_7_n_0\ : STD_LOGIC; + signal \vert_count[0]_i_8_n_0\ : STD_LOGIC; + signal \vert_count[0]_i_9_n_0\ : STD_LOGIC; + signal \vert_count[12]_i_2_n_0\ : STD_LOGIC; + signal \vert_count[4]_i_2_n_0\ : STD_LOGIC; + signal \vert_count[4]_i_3_n_0\ : STD_LOGIC; + signal \vert_count[4]_i_4_n_0\ : STD_LOGIC; + signal \vert_count[4]_i_5_n_0\ : STD_LOGIC; + signal \vert_count[4]_i_6_n_0\ : STD_LOGIC; + signal \vert_count[4]_i_7_n_0\ : STD_LOGIC; + signal \vert_count[4]_i_8_n_0\ : STD_LOGIC; + signal \vert_count[4]_i_9_n_0\ : STD_LOGIC; + signal \vert_count[8]_i_2_n_0\ : STD_LOGIC; + signal \vert_count[8]_i_3_n_0\ : STD_LOGIC; + signal \vert_count[8]_i_4_n_0\ : STD_LOGIC; + signal \vert_count[8]_i_5_n_0\ : STD_LOGIC; + signal \vert_count[8]_i_6_n_0\ : STD_LOGIC; + signal \vert_count[8]_i_7_n_0\ : STD_LOGIC; + signal \vert_count[8]_i_8_n_0\ : STD_LOGIC; + signal \vert_count[8]_i_9_n_0\ : STD_LOGIC; + signal vert_count_reg : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal \vert_count_reg[0]_i_2_n_0\ : STD_LOGIC; + signal \vert_count_reg[0]_i_2_n_1\ : STD_LOGIC; + signal \vert_count_reg[0]_i_2_n_2\ : STD_LOGIC; + signal \vert_count_reg[0]_i_2_n_3\ : STD_LOGIC; + signal \vert_count_reg[0]_i_2_n_4\ : STD_LOGIC; + signal \vert_count_reg[0]_i_2_n_5\ : STD_LOGIC; + signal \vert_count_reg[0]_i_2_n_6\ : STD_LOGIC; + signal \vert_count_reg[0]_i_2_n_7\ : STD_LOGIC; + signal \vert_count_reg[12]_i_1_n_7\ : STD_LOGIC; + signal \vert_count_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \vert_count_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \vert_count_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \vert_count_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \vert_count_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \vert_count_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \vert_count_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \vert_count_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \vert_count_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \vert_count_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \vert_count_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \vert_count_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \vert_count_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \vert_count_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \vert_count_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \vert_count_reg[8]_i_1_n_7\ : STD_LOGIC; + signal write_cmnd_cmb : STD_LOGIC; + signal \^zero_hsize_err\ : STD_LOGIC; + signal \^zero_vsize_err\ : STD_LOGIC; + signal \NLW_cmnds_queued_reg[7]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_cmnds_queued_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_dm_address_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_vert_count_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_vert_count_reg[12]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_dmacntrl_cs[1]_i_1\ : label is "soft_lutpair14"; + attribute SOFT_HLUTNM of \FSM_sequential_dmacntrl_cs[1]_i_3\ : label is "soft_lutpair13"; + attribute SOFT_HLUTNM of \FSM_sequential_dmacntrl_cs[2]_i_1\ : label is "soft_lutpair14"; + attribute KEEP : string; + attribute KEEP of \FSM_sequential_dmacntrl_cs_reg[0]\ : label is "yes"; + attribute KEEP of \FSM_sequential_dmacntrl_cs_reg[1]\ : label is "yes"; + attribute KEEP of \FSM_sequential_dmacntrl_cs_reg[2]\ : label is "yes"; + attribute SOFT_HLUTNM of \GEN_NORMAL_DM_COMMAND.cmnd_data[23]_i_1\ : label is "soft_lutpair15"; + attribute SOFT_HLUTNM of \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_i_2\ : label is "soft_lutpair13"; + attribute METHODOLOGY_DRC_VIOS : string; + attribute METHODOLOGY_DRC_VIOS of \cmnds_queued_reg[4]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \cmnds_queued_reg[7]_i_3\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \dm_address_reg[16]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \dm_address_reg[20]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \dm_address_reg[24]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \dm_address_reg[28]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[0]_i_1\ : label is "soft_lutpair39"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[10]_i_1\ : label is "soft_lutpair35"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[11]_i_1\ : label is "soft_lutpair34"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[12]_i_1\ : label is "soft_lutpair33"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[13]_i_1\ : label is "soft_lutpair33"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[14]_i_1\ : label is "soft_lutpair27"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[15]_i_1\ : label is "soft_lutpair32"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[1]_i_1\ : label is "soft_lutpair39"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[23]_i_1\ : label is "soft_lutpair15"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[2]_i_1\ : label is "soft_lutpair38"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[32]_i_1\ : label is "soft_lutpair32"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[33]_i_1\ : label is "soft_lutpair31"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[34]_i_1\ : label is "soft_lutpair31"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[35]_i_1\ : label is "soft_lutpair30"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[36]_i_1\ : label is "soft_lutpair30"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[37]_i_1\ : label is "soft_lutpair29"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[38]_i_1\ : label is "soft_lutpair29"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[39]_i_1\ : label is "soft_lutpair28"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[3]_i_1\ : label is "soft_lutpair38"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[40]_i_1\ : label is "soft_lutpair28"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[41]_i_1\ : label is "soft_lutpair27"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[42]_i_1\ : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[43]_i_1\ : label is "soft_lutpair26"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[44]_i_1\ : label is "soft_lutpair26"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[45]_i_1\ : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[46]_i_1\ : label is "soft_lutpair24"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[47]_i_1\ : label is "soft_lutpair24"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[48]_i_1\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[49]_i_1\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[4]_i_1\ : label is "soft_lutpair37"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[50]_i_1\ : label is "soft_lutpair22"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[51]_i_1\ : label is "soft_lutpair22"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[52]_i_1\ : label is "soft_lutpair21"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[53]_i_1\ : label is "soft_lutpair21"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[54]_i_1\ : label is "soft_lutpair20"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[55]_i_1\ : label is "soft_lutpair20"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[56]_i_1\ : label is "soft_lutpair19"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[57]_i_1\ : label is "soft_lutpair19"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[58]_i_1\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[59]_i_1\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[5]_i_1\ : label is "soft_lutpair37"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[60]_i_1\ : label is "soft_lutpair17"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[61]_i_1\ : label is "soft_lutpair17"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[62]_i_1\ : label is "soft_lutpair16"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[63]_i_3\ : label is "soft_lutpair16"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[6]_i_1\ : label is "soft_lutpair34"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[7]_i_1\ : label is "soft_lutpair36"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[8]_i_1\ : label is "soft_lutpair36"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[9]_i_1\ : label is "soft_lutpair35"; begin - p_2_in(0) <= in0(0); -\GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized12\ - port map ( - \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]\ => \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]\, - SR(0) => SR(0), - all_lines_xfred => all_lines_xfred, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axis_mm2s_aclk => m_axis_mm2s_aclk, - p_15_out => p_15_out, - p_in_d1_cdc_from_0 => p_in_d1_cdc_from_0, - prmry_in_xored_1 => prmry_in_xored_1, - prmry_resetn_i_reg(0) => prmry_resetn_i_reg(0) - ); -\GEN_CDC_FOR_ASYNC.SOF_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized10\ - port map ( - SR(0) => SR(0), - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axis_mm2s_aclk => m_axis_mm2s_aclk, - p_17_out => p_17_out, - p_in_d1_cdc_from => p_in_d1_cdc_from, - prmry_in_xored => prmry_in_xored, - prmry_resetn_i_reg(0) => prmry_resetn_i_reg(0) - ); -\GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => frame_ptr_out_d2(0), - Q => mm2s_frame_ptr_out(0), - R => SR(0) - ); -\GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => frame_ptr_out_d2(1), - Q => mm2s_frame_ptr_out(1), - R => SR(0) - ); -\GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => frame_ptr_out_d2(2), - Q => mm2s_frame_ptr_out(2), - R => SR(0) - ); -\GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => frame_ptr_out_d2(3), - Q => mm2s_frame_ptr_out(3), - R => SR(0) - ); -\GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => frame_ptr_out_d2(4), - Q => mm2s_frame_ptr_out(4), - R => SR(0) - ); -\GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => frame_ptr_out_d2(5), - Q => mm2s_frame_ptr_out(5), - R => SR(0) + \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0\(15 downto 0) <= \^gen_normal_dm_command.cmnd_data_reg[47]_0\(15 downto 0); + frame_sync_reg <= \^frame_sync_reg\; + load_new_addr <= \^load_new_addr\; + p_39_out <= \^p_39_out\; + s_axis_cmd_tvalid_reg <= \^s_axis_cmd_tvalid_reg\; + tstvect_fsync_d1 <= \^tstvect_fsync_d1\; + tstvect_fsync_d2 <= \^tstvect_fsync_d2\; + zero_hsize_err <= \^zero_hsize_err\; + zero_vsize_err <= \^zero_vsize_err\; +\FSM_sequential_dmacntrl_cs[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \FSM_sequential_dmacntrl_cs[0]_i_2_n_0\, + I1 => \FSM_sequential_dmacntrl_cs[2]_i_3_n_0\, + I2 => dmacntrl_cs(0), + O => \FSM_sequential_dmacntrl_cs[0]_i_1_n_0\ ); -\GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[0]\: unisim.vcomponents.FDRE +\FSM_sequential_dmacntrl_cs[0]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"88888B8BBB88BBBB" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => mm2s_frame_ptr_in(0), - Q => frame_ptr_in_d1_cdc_tig(0), - R => '0' + I0 => \FSM_sequential_dmacntrl_cs[0]_i_3_n_0\, + I1 => dmacntrl_cs(0), + I2 => \FSM_sequential_dmacntrl_cs[2]_i_4__0_n_0\, + I3 => \FSM_sequential_dmacntrl_cs[1]_i_3_n_0\, + I4 => dmacntrl_cs(1), + I5 => dmacntrl_cs(2), + O => \FSM_sequential_dmacntrl_cs[0]_i_2_n_0\ ); -\GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[1]\: unisim.vcomponents.FDRE +\FSM_sequential_dmacntrl_cs[0]_i_3\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"2808" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => mm2s_frame_ptr_in(1), - Q => frame_ptr_in_d1_cdc_tig(1), - R => '0' + I0 => p_1_in, + I1 => dmacntrl_cs(2), + I2 => dmacntrl_cs(1), + I3 => s_axis_cmd_tvalid_reg_0, + O => \FSM_sequential_dmacntrl_cs[0]_i_3_n_0\ ); -\GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[2]\: unisim.vcomponents.FDRE +\FSM_sequential_dmacntrl_cs[1]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => mm2s_frame_ptr_in(2), - Q => frame_ptr_in_d1_cdc_tig(2), - R => '0' + I0 => \FSM_sequential_dmacntrl_cs[1]_i_2_n_0\, + I1 => \FSM_sequential_dmacntrl_cs[2]_i_3_n_0\, + I2 => dmacntrl_cs(1), + O => \FSM_sequential_dmacntrl_cs[1]_i_1_n_0\ ); -\GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[3]\: unisim.vcomponents.FDRE +\FSM_sequential_dmacntrl_cs[1]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"4055DD0040008800" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => mm2s_frame_ptr_in(3), - Q => frame_ptr_in_d1_cdc_tig(3), - R => '0' + I0 => dmacntrl_cs(2), + I1 => p_1_in, + I2 => s_axis_cmd_tvalid_reg_0, + I3 => dmacntrl_cs(0), + I4 => dmacntrl_cs(1), + I5 => \FSM_sequential_dmacntrl_cs[1]_i_3_n_0\, + O => \FSM_sequential_dmacntrl_cs[1]_i_2_n_0\ ); -\GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[4]\: unisim.vcomponents.FDRE +\FSM_sequential_dmacntrl_cs[1]_i_3\: unisim.vcomponents.LUT5 generic map( - INIT => '0' + INIT => X"00000010" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => mm2s_frame_ptr_in(4), - Q => frame_ptr_in_d1_cdc_tig(4), - R => '0' + I0 => \^frame_sync_reg\, + I1 => mm2s_halt, + I2 => p_71_out(0), + I3 => dma_err, + I4 => p_77_out, + O => \FSM_sequential_dmacntrl_cs[1]_i_3_n_0\ ); -\GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[5]\: unisim.vcomponents.FDRE +\FSM_sequential_dmacntrl_cs[2]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => mm2s_frame_ptr_in(5), - Q => frame_ptr_in_d1_cdc_tig(5), - R => '0' + I0 => \FSM_sequential_dmacntrl_cs[2]_i_2_n_0\, + I1 => \FSM_sequential_dmacntrl_cs[2]_i_3_n_0\, + I2 => dmacntrl_cs(2), + O => \FSM_sequential_dmacntrl_cs[2]_i_1_n_0\ ); -\GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[0]\: unisim.vcomponents.FDRE +\FSM_sequential_dmacntrl_cs[2]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"0040004000000F00" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => frame_ptr_in_d1_cdc_tig(0), - Q => frame_ptr_in_d2(0), - R => '0' + I0 => s_axis_cmd_tvalid_reg_0, + I1 => p_1_in, + I2 => dmacntrl_cs(0), + I3 => dmacntrl_cs(2), + I4 => \FSM_sequential_dmacntrl_cs[2]_i_4__0_n_0\, + I5 => dmacntrl_cs(1), + O => \FSM_sequential_dmacntrl_cs[2]_i_2_n_0\ ); -\GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[1]\: unisim.vcomponents.FDRE +\FSM_sequential_dmacntrl_cs[2]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"5E5E5E5E5F5E5E5E" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => frame_ptr_in_d1_cdc_tig(1), - Q => frame_ptr_in_d2(1), - R => '0' + I0 => dmacntrl_cs(1), + I1 => dmacntrl_cs(0), + I2 => dmacntrl_cs(2), + I3 => \^frame_sync_reg\, + I4 => \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\, + I5 => \dmacr_i_reg[2]\, + O => \FSM_sequential_dmacntrl_cs[2]_i_3_n_0\ ); -\GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[2]\: unisim.vcomponents.FDRE +\FSM_sequential_dmacntrl_cs[2]_i_4__0\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"00010000FFFFFFFF" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => frame_ptr_in_d1_cdc_tig(2), - Q => frame_ptr_in_d2(2), - R => '0' + I0 => vert_count_reg(4), + I1 => vert_count_reg(7), + I2 => vert_count_reg(5), + I3 => \FSM_sequential_dmacntrl_cs[2]_i_5_n_0\, + I4 => \FSM_sequential_dmacntrl_cs[2]_i_6_n_0\, + I5 => p_1_in, + O => \FSM_sequential_dmacntrl_cs[2]_i_4__0_n_0\ ); -\GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[3]\: unisim.vcomponents.FDRE +\FSM_sequential_dmacntrl_cs[2]_i_5\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"FFFE" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => frame_ptr_in_d1_cdc_tig(3), - Q => frame_ptr_in_d2(3), - R => '0' + I0 => vert_count_reg(8), + I1 => vert_count_reg(0), + I2 => vert_count_reg(9), + I3 => vert_count_reg(1), + O => \FSM_sequential_dmacntrl_cs[2]_i_5_n_0\ ); -\GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[4]\: unisim.vcomponents.FDRE +\FSM_sequential_dmacntrl_cs[2]_i_6\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"0000000000000001" ) port map ( + I0 => vert_count_reg(11), + I1 => vert_count_reg(6), + I2 => vert_count_reg(3), + I3 => vert_count_reg(12), + I4 => vert_count_reg(2), + I5 => vert_count_reg(10), + O => \FSM_sequential_dmacntrl_cs[2]_i_6_n_0\ + ); +\FSM_sequential_dmacntrl_cs_reg[0]\: unisim.vcomponents.FDRE + port map ( C => m_axi_mm2s_aclk, CE => '1', - D => frame_ptr_in_d1_cdc_tig(4), - Q => frame_ptr_in_d2(4), - R => '0' + D => \FSM_sequential_dmacntrl_cs[0]_i_1_n_0\, + Q => dmacntrl_cs(0), + R => SR(0) ); -\GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[5]\: unisim.vcomponents.FDRE +\FSM_sequential_dmacntrl_cs_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \FSM_sequential_dmacntrl_cs[1]_i_1_n_0\, + Q => dmacntrl_cs(1), + R => SR(0) + ); +\FSM_sequential_dmacntrl_cs_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \FSM_sequential_dmacntrl_cs[2]_i_1_n_0\, + Q => dmacntrl_cs(2), + R => SR(0) + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_1__1\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"00F8" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => frame_ptr_in_d1_cdc_tig(5), - Q => frame_ptr_in_d2(5), - R => '0' + I0 => mm2s_all_lines_xfred, + I1 => \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg_n_0\, + I2 => \dmacr_i_reg[2]\, + I3 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_3_n_0\, + O => \^p_39_out\ ); -\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[0]\: unisim.vcomponents.FDRE +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFFFFFFFFFFFE" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => p_2_in(0), - Q => frame_ptr_out_d1_cdc_tig(0), - R => '0' + I0 => \cmnds_queued_reg__0\(3), + I1 => \cmnds_queued_reg__0\(0), + I2 => \cmnds_queued_reg__0\(1), + I3 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_4_n_0\, + I4 => \cmnds_queued_reg__0\(6), + I5 => \cmnds_queued_reg__0\(7), + O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_3_n_0\ ); -\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[1]\: unisim.vcomponents.FDRE +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFFFFFFFFFFFB" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => p_2_in(1), - Q => frame_ptr_out_d1_cdc_tig(1), - R => '0' + I0 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_5_n_0\, + I1 => halt_i_reg, + I2 => dmacntrl_cs(1), + I3 => \cmnds_queued_reg__0\(5), + I4 => \cmnds_queued_reg__0\(4), + I5 => \cmnds_queued_reg__0\(2), + O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_4_n_0\ ); -\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2]\: unisim.vcomponents.FDRE +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_5\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"E" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => p_2_in(2), - Q => frame_ptr_out_d1_cdc_tig(2), - R => '0' + I0 => dmacntrl_cs(2), + I1 => dmacntrl_cs(0), + O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_5_n_0\ ); -\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[3]\: unisim.vcomponents.FDRE +\GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.all_lines_xfred_d1_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, + C => m_axi_mm2s_aclk, CE => '1', - D => p_2_in(3), - Q => frame_ptr_out_d1_cdc_tig(3), - R => '0' + D => mm2s_all_lines_xfred, + Q => all_lines_xfred_d1, + R => SR(0) ); -\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[4]\: unisim.vcomponents.FDRE +\GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"00AEFFFFFFFFFFFF" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => p_2_in(4), - Q => frame_ptr_out_d1_cdc_tig(4), - R => '0' + I0 => \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg_n_0\, + I1 => all_lines_xfred_d1, + I2 => mm2s_all_lines_xfred, + I3 => p_24_out, + I4 => mm2s_prmry_resetn, + I5 => p_71_out(0), + O => \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_i_1_n_0\ ); -\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[5]\: unisim.vcomponents.FDRE +\GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, + C => m_axi_mm2s_aclk, CE => '1', - D => p_2_in(5), - Q => frame_ptr_out_d1_cdc_tig(5), + D => \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_i_1_n_0\, + Q => \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg_n_0\, R => '0' ); -\GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[0]\: unisim.vcomponents.FDRE +\GEN_NORMAL_DM_COMMAND.cmnd_data[23]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => frame_ptr_out_d1_cdc_tig(0), - Q => frame_ptr_out_d2(0), - R => '0' + I0 => mm2s_prmry_resetn, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + I2 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[23]\, + O => \GEN_NORMAL_DM_COMMAND.cmnd_data[23]_i_1_n_0\ ); -\GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[1]\: unisim.vcomponents.FDRE +\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"2" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => frame_ptr_out_d1_cdc_tig(1), - Q => frame_ptr_out_d2(1), - R => '0' + I0 => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + I1 => mm2s_prmry_resetn, + O => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ ); -\GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[2]\: unisim.vcomponents.FDRE +\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"00080000FFFFFFFF" ) port map ( - C => m_axis_mm2s_aclk, + I0 => dmacntrl_cs(1), + I1 => dmacntrl_cs(0), + I2 => dmacntrl_cs(2), + I3 => s_axis_cmd_tvalid_reg_0, + I4 => p_1_in, + I5 => mm2s_prmry_resetn, + O => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \hsize_vid_reg[15]\(0), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[0]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \hsize_vid_reg[15]\(10), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[10]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \hsize_vid_reg[15]\(11), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[11]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \hsize_vid_reg[15]\(12), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[12]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \hsize_vid_reg[15]\(13), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[13]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \hsize_vid_reg[15]\(14), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[14]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \hsize_vid_reg[15]\(15), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[15]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \hsize_vid_reg[15]\(1), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[1]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, CE => '1', - D => frame_ptr_out_d1_cdc_tig(2), - Q => frame_ptr_out_d2(2), + D => \GEN_NORMAL_DM_COMMAND.cmnd_data[23]_i_1_n_0\, + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[23]\, R => '0' ); -\GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[3]\: unisim.vcomponents.FDRE +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \hsize_vid_reg[15]\(2), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[2]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[32]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(0), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[32]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[33]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(1), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[33]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[34]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(2), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[34]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[35]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(3), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[35]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[36]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(4), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[36]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[37]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(5), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[37]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[38]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(6), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[38]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[39]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(7), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[39]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \hsize_vid_reg[15]\(3), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[3]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[40]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(8), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[40]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[41]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(9), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[41]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[42]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(10), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[42]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[43]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(11), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[43]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[44]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(12), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[44]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[45]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(13), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[45]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[46]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(14), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[46]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(15), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[47]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[48]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => dm_address_reg(16), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[48]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[49]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => dm_address_reg(17), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[49]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \hsize_vid_reg[15]\(4), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[4]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[50]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => dm_address_reg(18), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[50]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[51]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => dm_address_reg(19), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[51]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[52]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => dm_address_reg(20), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[52]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[53]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => dm_address_reg(21), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[53]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[54]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => dm_address_reg(22), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[54]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[55]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => dm_address_reg(23), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[55]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[56]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => dm_address_reg(24), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[56]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[57]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => dm_address_reg(25), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[57]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[58]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => dm_address_reg(26), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[58]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[59]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => dm_address_reg(27), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[59]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \hsize_vid_reg[15]\(5), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[5]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[60]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => dm_address_reg(28), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[60]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[61]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => dm_address_reg(29), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[61]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[62]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => dm_address_reg(30), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[62]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[63]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => dm_address_reg(31), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[63]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \hsize_vid_reg[15]\(6), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[6]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \hsize_vid_reg[15]\(7), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[7]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \hsize_vid_reg[15]\(8), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[8]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2_n_0\, + D => \hsize_vid_reg[15]\(9), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[9]\, + R => \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_wr_i_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => '0' + INIT => X"02000000" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => frame_ptr_out_d1_cdc_tig(3), - Q => frame_ptr_out_d2(3), - R => '0' + I0 => p_1_in, + I1 => s_axis_cmd_tvalid_reg_0, + I2 => dmacntrl_cs(2), + I3 => dmacntrl_cs(0), + I4 => dmacntrl_cs(1), + O => write_cmnd_cmb ); -\GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[4]\: unisim.vcomponents.FDRE +\GEN_NORMAL_DM_COMMAND.cmnd_wr_i_i_2\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"0001" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => frame_ptr_out_d1_cdc_tig(4), - Q => frame_ptr_out_d2(4), - R => '0' + I0 => \^frame_sync_reg\, + I1 => dma_err, + I2 => p_77_out, + I3 => mm2s_halt, + O => p_1_in ); -\GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[5]\: unisim.vcomponents.FDRE +\GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, + C => m_axi_mm2s_aclk, CE => '1', - D => frame_ptr_out_d1_cdc_tig(5), - Q => frame_ptr_out_d2(5), - R => '0' + D => write_cmnd_cmb, + Q => \^s_axis_cmd_tvalid_reg\, + R => SR(0) ); -i_0: unisim.vcomponents.LUT1 +\I_DMA_REGISTER/dma_interr_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"2" + INIT => X"FFFFFFF7FFFFFFF0" ) port map ( - I0 => '0', - O => p_2_in(5) + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4]\(0), + I1 => mm2s_axi2ip_wrce(0), + I2 => interr_i_reg, + I3 => \^zero_vsize_err\, + I4 => \^zero_hsize_err\, + I5 => dma_interr_reg_0, + O => dma_interr_reg ); -i_1: unisim.vcomponents.LUT1 +\cmnds_queued[0]_i_1\: unisim.vcomponents.LUT1 generic map( - INIT => X"2" + INIT => X"1" ) port map ( - I0 => '0', - O => p_2_in(4) + I0 => \cmnds_queued_reg__0\(0), + O => \cmnds_queued[0]_i_1_n_0\ ); -i_10: unisim.vcomponents.LUT1 +\cmnds_queued[4]_i_2\: unisim.vcomponents.LUT1 generic map( - INIT => X"2" + INIT => X"1" ) port map ( - I0 => '0', - O => othrchnl_frame_ptr_in_d1_cdc_tig(0) + I0 => \cmnds_queued_reg__0\(1), + O => \cmnds_queued[4]_i_2_n_0\ ); -i_11: unisim.vcomponents.LUT1 +\cmnds_queued[4]_i_3\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"9" ) port map ( - I0 => '0', - O => othrchnl_frame_ptr_in_d2(5) + I0 => \cmnds_queued_reg__0\(3), + I1 => \cmnds_queued_reg__0\(4), + O => \cmnds_queued[4]_i_3_n_0\ ); -i_12: unisim.vcomponents.LUT1 +\cmnds_queued[4]_i_4\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"9" ) port map ( - I0 => '0', - O => othrchnl_frame_ptr_in_d2(4) + I0 => \cmnds_queued_reg__0\(2), + I1 => \cmnds_queued_reg__0\(3), + O => \cmnds_queued[4]_i_4_n_0\ ); -i_13: unisim.vcomponents.LUT1 +\cmnds_queued[4]_i_5\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"9" ) port map ( - I0 => '0', - O => othrchnl_frame_ptr_in_d2(3) + I0 => \cmnds_queued_reg__0\(1), + I1 => \cmnds_queued_reg__0\(2), + O => \cmnds_queued[4]_i_5_n_0\ ); -i_14: unisim.vcomponents.LUT1 +\cmnds_queued[4]_i_6\: unisim.vcomponents.LUT4 generic map( - INIT => X"2" + INIT => X"A655" ) port map ( - I0 => '0', - O => othrchnl_frame_ptr_in_d2(2) + I0 => \cmnds_queued_reg__0\(1), + I1 => p_58_out, + I2 => \INFERRED_GEN.cnt_i_reg[2]\(0), + I3 => \^s_axis_cmd_tvalid_reg\, + O => \cmnds_queued[4]_i_6_n_0\ ); -i_15: unisim.vcomponents.LUT1 +\cmnds_queued[7]_i_2\: unisim.vcomponents.LUT3 generic map( - INIT => X"2" + INIT => X"9A" ) port map ( - I0 => '0', - O => othrchnl_frame_ptr_in_d2(1) + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \INFERRED_GEN.cnt_i_reg[2]\(0), + I2 => p_58_out, + O => \cmnds_queued[7]_i_2_n_0\ ); -i_16: unisim.vcomponents.LUT1 +\cmnds_queued[7]_i_4\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"9" ) port map ( - I0 => '0', - O => othrchnl_frame_ptr_in_d2(0) + I0 => \cmnds_queued_reg__0\(6), + I1 => \cmnds_queued_reg__0\(7), + O => \cmnds_queued[7]_i_4_n_0\ ); -i_2: unisim.vcomponents.LUT1 +\cmnds_queued[7]_i_5\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"9" ) port map ( - I0 => '0', - O => p_2_in(3) + I0 => \cmnds_queued_reg__0\(5), + I1 => \cmnds_queued_reg__0\(6), + O => \cmnds_queued[7]_i_5_n_0\ ); -i_3: unisim.vcomponents.LUT1 +\cmnds_queued[7]_i_6\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"9" ) port map ( - I0 => '0', - O => p_2_in(2) + I0 => \cmnds_queued_reg__0\(4), + I1 => \cmnds_queued_reg__0\(5), + O => \cmnds_queued[7]_i_6_n_0\ ); -i_4: unisim.vcomponents.LUT1 +\cmnds_queued_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => p_2_in(1) + C => m_axi_mm2s_aclk, + CE => \cmnds_queued[7]_i_2_n_0\, + D => \cmnds_queued[0]_i_1_n_0\, + Q => \cmnds_queued_reg__0\(0), + R => err_i_reg(0) ); -i_5: unisim.vcomponents.LUT1 +\cmnds_queued_reg[1]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => othrchnl_frame_ptr_in_d1_cdc_tig(5) + C => m_axi_mm2s_aclk, + CE => \cmnds_queued[7]_i_2_n_0\, + D => \cmnds_queued_reg[4]_i_1_n_7\, + Q => \cmnds_queued_reg__0\(1), + R => err_i_reg(0) ); -i_6: unisim.vcomponents.LUT1 +\cmnds_queued_reg[2]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => othrchnl_frame_ptr_in_d1_cdc_tig(4) + C => m_axi_mm2s_aclk, + CE => \cmnds_queued[7]_i_2_n_0\, + D => \cmnds_queued_reg[4]_i_1_n_6\, + Q => \cmnds_queued_reg__0\(2), + R => err_i_reg(0) ); -i_7: unisim.vcomponents.LUT1 +\cmnds_queued_reg[3]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => othrchnl_frame_ptr_in_d1_cdc_tig(3) + C => m_axi_mm2s_aclk, + CE => \cmnds_queued[7]_i_2_n_0\, + D => \cmnds_queued_reg[4]_i_1_n_5\, + Q => \cmnds_queued_reg__0\(3), + R => err_i_reg(0) ); -i_8: unisim.vcomponents.LUT1 +\cmnds_queued_reg[4]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => othrchnl_frame_ptr_in_d1_cdc_tig(2) + C => m_axi_mm2s_aclk, + CE => \cmnds_queued[7]_i_2_n_0\, + D => \cmnds_queued_reg[4]_i_1_n_4\, + Q => \cmnds_queued_reg__0\(4), + R => err_i_reg(0) ); -i_9: unisim.vcomponents.LUT1 +\cmnds_queued_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \cmnds_queued_reg[4]_i_1_n_0\, + CO(2) => \cmnds_queued_reg[4]_i_1_n_1\, + CO(1) => \cmnds_queued_reg[4]_i_1_n_2\, + CO(0) => \cmnds_queued_reg[4]_i_1_n_3\, + CYINIT => \cmnds_queued_reg__0\(0), + DI(3 downto 1) => \cmnds_queued_reg__0\(3 downto 1), + DI(0) => \cmnds_queued[4]_i_2_n_0\, + O(3) => \cmnds_queued_reg[4]_i_1_n_4\, + O(2) => \cmnds_queued_reg[4]_i_1_n_5\, + O(1) => \cmnds_queued_reg[4]_i_1_n_6\, + O(0) => \cmnds_queued_reg[4]_i_1_n_7\, + S(3) => \cmnds_queued[4]_i_3_n_0\, + S(2) => \cmnds_queued[4]_i_4_n_0\, + S(1) => \cmnds_queued[4]_i_5_n_0\, + S(0) => \cmnds_queued[4]_i_6_n_0\ + ); +\cmnds_queued_reg[5]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => othrchnl_frame_ptr_in_d1_cdc_tig(1) + C => m_axi_mm2s_aclk, + CE => \cmnds_queued[7]_i_2_n_0\, + D => \cmnds_queued_reg[7]_i_3_n_7\, + Q => \cmnds_queued_reg__0\(5), + R => err_i_reg(0) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_vidreg_module is - port ( - \stride_vid_reg[0]\ : out STD_LOGIC; - \stride_vid_reg[0]_0\ : out STD_LOGIC; - zero_vsize_err0 : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 12 downto 0 ); - zero_hsize_err0 : out STD_LOGIC; - all_idle_reg : out STD_LOGIC; - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - p_2_out : out STD_LOGIC; - \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); - O : out STD_LOGIC_VECTOR ( 3 downto 0 ); - \dm_address_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); - \dm_address_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); - CO : out STD_LOGIC_VECTOR ( 0 to 0 ); - \dm_address_reg[15]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); - \dm_address_reg[31]\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); - prmtr_updt_complete_i_reg : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - load_new_addr : in STD_LOGIC; - p_1_out : in STD_LOGIC; - p_64_out : in STD_LOGIC; - p_37_out : in STD_LOGIC; - p_23_out : in STD_LOGIC; - \p_6_out__0\ : in STD_LOGIC; - p_68_out : in STD_LOGIC_VECTOR ( 0 to 0 ); - valid_frame_sync_d2 : in STD_LOGIC; - mask_fsync_out_i : in STD_LOGIC; - tstvect_fsync_d1 : in STD_LOGIC; - \dm_address_reg[15]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); - \out\ : in STD_LOGIC; - p_67_out : in STD_LOGIC; - p_0_in : in STD_LOGIC; - \reg_module_vsize_reg[12]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); - \reg_module_hsize_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); - \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_vidreg_module : entity is "axi_vdma_vidreg_module"; -end Arty_Z7_20_axi_vdma_0_0_axi_vdma_vidreg_module; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_vidreg_module is - signal \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_i_1_n_0\ : STD_LOGIC; - signal \^stride_vid_reg[0]\ : STD_LOGIC; - signal \^stride_vid_reg[0]_0\ : STD_LOGIC; -begin - \stride_vid_reg[0]\ <= \^stride_vid_reg[0]\; - \stride_vid_reg[0]_0\ <= \^stride_vid_reg[0]_0\; -\GEN_FREE_RUN_MODE.frame_sync_out_i_1\: unisim.vcomponents.LUT3 +\cmnds_queued_reg[6]\: unisim.vcomponents.FDRE generic map( - INIT => X"20" + INIT => '0' ) port map ( - I0 => \^stride_vid_reg[0]_0\, - I1 => mask_fsync_out_i, - I2 => tstvect_fsync_d1, - O => p_2_out + C => m_axi_mm2s_aclk, + CE => \cmnds_queued[7]_i_2_n_0\, + D => \cmnds_queued_reg[7]_i_3_n_6\, + Q => \cmnds_queued_reg__0\(6), + R => err_i_reg(0) ); -\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.VIDREGISTER_I\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_vregister +\cmnds_queued_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => \cmnds_queued[7]_i_2_n_0\, + D => \cmnds_queued_reg[7]_i_3_n_5\, + Q => \cmnds_queued_reg__0\(7), + R => err_i_reg(0) + ); +\cmnds_queued_reg[7]_i_3\: unisim.vcomponents.CARRY4 port map ( - CO(0) => CO(0), - \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15]\(15 downto 0) => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15]\(15 downto 0), - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(31 downto 0) => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(31 downto 0), - \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\ => \^stride_vid_reg[0]_0\, - \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg\ => \^stride_vid_reg[0]\, - \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(15 downto 0) => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(15 downto 0), - O(3 downto 0) => O(3 downto 0), - Q(12 downto 0) => Q(12 downto 0), - \dm_address_reg[11]\(3 downto 0) => \dm_address_reg[11]\(3 downto 0), - \dm_address_reg[15]\(3 downto 0) => \dm_address_reg[15]\(3 downto 0), - \dm_address_reg[15]_0\(15 downto 0) => \dm_address_reg[15]_0\(15 downto 0), - \dm_address_reg[31]\(15 downto 0) => \dm_address_reg[31]\(15 downto 0), - \dm_address_reg[7]\(3 downto 0) => \dm_address_reg[7]\(3 downto 0), - load_new_addr => load_new_addr, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - p_0_in => p_0_in, - p_23_out => p_23_out, - \reg_module_hsize_reg[15]\(15 downto 0) => \reg_module_hsize_reg[15]\(15 downto 0), - \reg_module_vsize_reg[12]\(12 downto 0) => \reg_module_vsize_reg[12]\(12 downto 0), - zero_hsize_err0 => zero_hsize_err0, - zero_vsize_err0 => zero_vsize_err0 + CI => \cmnds_queued_reg[4]_i_1_n_0\, + CO(3 downto 2) => \NLW_cmnds_queued_reg[7]_i_3_CO_UNCONNECTED\(3 downto 2), + CO(1) => \cmnds_queued_reg[7]_i_3_n_2\, + CO(0) => \cmnds_queued_reg[7]_i_3_n_3\, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1 downto 0) => \cmnds_queued_reg__0\(5 downto 4), + O(3) => \NLW_cmnds_queued_reg[7]_i_3_O_UNCONNECTED\(3), + O(2) => \cmnds_queued_reg[7]_i_3_n_5\, + O(1) => \cmnds_queued_reg[7]_i_3_n_6\, + O(0) => \cmnds_queued_reg[7]_i_3_n_7\, + S(3) => '0', + S(2) => \cmnds_queued[7]_i_4_n_0\, + S(1) => \cmnds_queued[7]_i_5_n_0\, + S(0) => \cmnds_queued[7]_i_6_n_0\ ); -\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_i_1\: unisim.vcomponents.LUT5 +\dm_address[0]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"0000EA00" + INIT => X"AAEAAAAA" ) port map ( - I0 => \^stride_vid_reg[0]_0\, - I1 => p_23_out, - I2 => \^stride_vid_reg[0]\, - I3 => \out\, - I4 => p_67_out, - O => \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_i_1_n_0\ + I0 => \^load_new_addr\, + I1 => p_1_in, + I2 => dmacntrl_cs(0), + I3 => dmacntrl_cs(1), + I4 => dmacntrl_cs(2), + O => \dm_address[0]_i_1_n_0\ ); -\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\: unisim.vcomponents.FDRE +\dm_address[16]_i_2\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_i_1_n_0\, - Q => \^stride_vid_reg[0]_0\, - R => '0' + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][19]\, + I1 => \^load_new_addr\, + I2 => dm_address_reg(19), + O => \dm_address[16]_i_2_n_0\ ); -\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg\: unisim.vcomponents.FDRE +\dm_address[16]_i_3\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => prmtr_updt_complete_i_reg, - Q => \^stride_vid_reg[0]\, - R => '0' + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][18]\, + I1 => \^load_new_addr\, + I2 => dm_address_reg(18), + O => \dm_address[16]_i_3_n_0\ ); -\MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_2\: unisim.vcomponents.LUT4 +\dm_address[16]_i_4\: unisim.vcomponents.LUT3 generic map( - INIT => X"EFCC" + INIT => X"B8" ) port map ( - I0 => \^stride_vid_reg[0]_0\, - I1 => \p_6_out__0\, - I2 => p_68_out(0), - I3 => valid_frame_sync_d2, - O => E(0) + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][17]\, + I1 => \^load_new_addr\, + I2 => dm_address_reg(17), + O => \dm_address[16]_i_4_n_0\ ); -all_idle_i_1: unisim.vcomponents.LUT5 +\dm_address[16]_i_5\: unisim.vcomponents.LUT3 generic map( - INIT => X"C8880000" + INIT => X"B8" ) port map ( - I0 => \^stride_vid_reg[0]_0\, - I1 => p_1_out, - I2 => \^stride_vid_reg[0]\, - I3 => p_64_out, - I4 => p_37_out, - O => all_idle_reg - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f is - port ( - Q : out STD_LOGIC_VECTOR ( 0 to 0 ); - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - \out\ : out STD_LOGIC_VECTOR ( 49 downto 0 ); - sig_calc_error_reg_reg : out STD_LOGIC; - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - sig_calc_error_pushed_reg : in STD_LOGIC; - sig_sm_halt_reg : in STD_LOGIC; - sig_input_reg_empty : in STD_LOGIC; - sig_calc_error_pushed : in STD_LOGIC; - p_55_out : in STD_LOGIC; - sig_inhibit_rdy_n : in STD_LOGIC; - cmnd_wr : in STD_LOGIC; - mm2s_halt : in STD_LOGIC; - \in\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - \s_axis_cmd_tdata_reg[63]\ : in STD_LOGIC_VECTOR ( 48 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f : entity is "srl_fifo_rbu_f"; -end Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f is - signal CNTR_INCR_DECR_ADDN_F_I_n_2 : STD_LOGIC; - signal CNTR_INCR_DECR_ADDN_F_I_n_3 : STD_LOGIC; - signal FIFO_Full_reg_n_0 : STD_LOGIC; - signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal fifo_full_p1 : STD_LOGIC; - signal sig_wr_fifo : STD_LOGIC; -begin - Q(0) <= \^q\(0); -CNTR_INCR_DECR_ADDN_F_I: entity work.Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_3 - port map ( - FIFO_Full_reg => FIFO_Full_reg_n_0, - Q(2) => \^q\(0), - Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_2, - Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_3, - SR(0) => SR(0), - fifo_full_p1 => fifo_full_p1, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - p_55_out => p_55_out, - sig_calc_error_pushed => sig_calc_error_pushed, - sig_calc_error_pushed_reg => sig_calc_error_pushed_reg, - sig_inhibit_rdy_n => sig_inhibit_rdy_n, - sig_input_reg_empty => sig_input_reg_empty, - sig_sm_halt_reg => sig_sm_halt_reg, - sig_wr_fifo => sig_wr_fifo + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][16]\, + I1 => \^load_new_addr\, + I2 => dm_address_reg(16), + O => \dm_address[16]_i_5_n_0\ ); -DYNSHREG_F_I: entity work.Arty_Z7_20_axi_vdma_0_0_dynshreg_f - port map ( - FIFO_Full_reg => FIFO_Full_reg_n_0, - Q(2) => \^q\(0), - Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_2, - Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_3, - \in\(0) => \in\(0), - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - \out\(49 downto 0) => \out\(49 downto 0), - p_55_out => p_55_out, - \s_axis_cmd_tdata_reg[63]\(48 downto 0) => \s_axis_cmd_tdata_reg[63]\(48 downto 0), - sig_calc_error_reg_reg => sig_calc_error_reg_reg, - sig_inhibit_rdy_n => sig_inhibit_rdy_n, - sig_input_reg_empty => sig_input_reg_empty, - sig_sm_halt_reg => sig_sm_halt_reg, - sig_wr_fifo => sig_wr_fifo +\dm_address[20]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][23]\, + I1 => \^load_new_addr\, + I2 => dm_address_reg(23), + O => \dm_address[20]_i_2_n_0\ ); -FIFO_Full_reg: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => fifo_full_p1, - Q => FIFO_Full_reg_n_0, - R => SR(0) +\dm_address[20]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][22]\, + I1 => \^load_new_addr\, + I2 => dm_address_reg(22), + O => \dm_address[20]_i_3_n_0\ ); -\s_axis_cmd_tdata[63]_i_2\: unisim.vcomponents.LUT4 +\dm_address[20]_i_4\: unisim.vcomponents.LUT3 generic map( - INIT => X"FFAE" + INIT => X"B8" ) port map ( - I0 => cmnd_wr, - I1 => sig_inhibit_rdy_n, - I2 => FIFO_Full_reg_n_0, - I3 => mm2s_halt, - O => E(0) + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][21]\, + I1 => \^load_new_addr\, + I2 => dm_address_reg(21), + O => \dm_address[20]_i_4_n_0\ ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized0\ is - port ( - \INFERRED_GEN.cnt_i_reg[1]\ : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 0 to 0 ); - sig_rd_sts_slverr_reg_reg : out STD_LOGIC; - interr_i_reg : out STD_LOGIC; - slverr_i_reg : out STD_LOGIC; - decerr_i_reg : out STD_LOGIC; - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - p_57_out : in STD_LOGIC; - sig_rsc2stat_status_valid : in STD_LOGIC; - sig_inhibit_rdy_n_reg : in STD_LOGIC; - sts_tready_reg : in STD_LOGIC; - sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; - sig_rd_sts_slverr_reg_reg_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized0\ : entity is "srl_fifo_rbu_f"; -end \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized0\; - -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized0\ is - signal CNTR_INCR_DECR_ADDN_F_I_n_2 : STD_LOGIC; - signal CNTR_INCR_DECR_ADDN_F_I_n_3 : STD_LOGIC; - signal \^inferred_gen.cnt_i_reg[1]\ : STD_LOGIC; - signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal fifo_full_p1 : STD_LOGIC; - signal sig_wr_fifo : STD_LOGIC; -begin - \INFERRED_GEN.cnt_i_reg[1]\ <= \^inferred_gen.cnt_i_reg[1]\; - Q(0) <= \^q\(0); -CNTR_INCR_DECR_ADDN_F_I: entity work.Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_4 - port map ( - FIFO_Full_reg => \^inferred_gen.cnt_i_reg[1]\, - Q(2) => \^q\(0), - Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_2, - Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_3, - SR(0) => SR(0), - fifo_full_p1 => fifo_full_p1, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - p_57_out => p_57_out, - sig_inhibit_rdy_n_reg => sig_inhibit_rdy_n_reg, - sig_rsc2stat_status_valid => sig_rsc2stat_status_valid, - sig_wr_fifo => sig_wr_fifo, - sts_tready_reg => sts_tready_reg +\dm_address[20]_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][20]\, + I1 => \^load_new_addr\, + I2 => dm_address_reg(20), + O => \dm_address[20]_i_5_n_0\ ); -DYNSHREG_F_I: entity work.\Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized0\ - port map ( - FIFO_Full_reg => \^inferred_gen.cnt_i_reg[1]\, - Q(2) => \^q\(0), - Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_2, - Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_3, - decerr_i_reg => decerr_i_reg, - interr_i_reg => interr_i_reg, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - sig_inhibit_rdy_n_reg => sig_inhibit_rdy_n_reg, - sig_rd_sts_slverr_reg_reg(2 downto 0) => sig_rd_sts_slverr_reg_reg_0(2 downto 0), - sig_rsc2stat_status_valid => sig_rsc2stat_status_valid, - sig_wr_fifo => sig_wr_fifo, - slverr_i_reg => slverr_i_reg +\dm_address[24]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][27]\, + I1 => \^load_new_addr\, + I2 => dm_address_reg(27), + O => \dm_address[24]_i_2_n_0\ ); -FIFO_Full_reg: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => fifo_full_p1, - Q => \^inferred_gen.cnt_i_reg[1]\, - R => SR(0) +\dm_address[24]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][26]\, + I1 => \^load_new_addr\, + I2 => dm_address_reg(26), + O => \dm_address[24]_i_3_n_0\ ); -sig_rd_sts_reg_full_i_1: unisim.vcomponents.LUT4 +\dm_address[24]_i_4\: unisim.vcomponents.LUT3 generic map( - INIT => X"20FF" + INIT => X"B8" ) port map ( - I0 => sig_inhibit_rdy_n_reg, - I1 => \^inferred_gen.cnt_i_reg[1]\, - I2 => sig_rsc2stat_status_valid, - I3 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - O => sig_rd_sts_slverr_reg_reg + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][25]\, + I1 => \^load_new_addr\, + I2 => dm_address_reg(25), + O => \dm_address[24]_i_4_n_0\ ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized1\ is - port ( - sig_calc_error_reg_reg : out STD_LOGIC; - sel : out STD_LOGIC; - sig_posted_to_axi_reg : out STD_LOGIC; - sig_addr_valid_reg_reg : out STD_LOGIC; - \out\ : out STD_LOGIC_VECTOR ( 39 downto 0 ); - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - sig_mstr2addr_cmd_valid : in STD_LOGIC; - sig_inhibit_rdy_n : in STD_LOGIC; - sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; - sig_data2addr_stop_req : in STD_LOGIC; - sig_addr_reg_empty : in STD_LOGIC; - sig_sf_allow_addr_req : in STD_LOGIC; - \in\ : in STD_LOGIC_VECTOR ( 37 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized1\ : entity is "srl_fifo_rbu_f"; -end \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized1\; - -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized1\ is - signal CNTR_INCR_DECR_ADDN_F_I_n_2 : STD_LOGIC; - signal CNTR_INCR_DECR_ADDN_F_I_n_3 : STD_LOGIC; - signal FIFO_Full_reg_n_0 : STD_LOGIC; - signal fifo_full_p1 : STD_LOGIC; - signal \^sel\ : STD_LOGIC; -begin - sel <= \^sel\; -CNTR_INCR_DECR_ADDN_F_I: entity work.Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_5 - port map ( - FIFO_Full_reg => FIFO_Full_reg_n_0, - Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_2, - Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_3, - SR(0) => SR(0), - fifo_full_p1 => fifo_full_p1, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - sig_addr_reg_empty => sig_addr_reg_empty, - sig_calc_error_reg_reg => sig_calc_error_reg_reg, - sig_cmd2addr_valid_reg => \^sel\, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_data2addr_stop_req => sig_data2addr_stop_req, - sig_inhibit_rdy_n => sig_inhibit_rdy_n, - sig_mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid, - sig_posted_to_axi_reg => sig_posted_to_axi_reg, - sig_sf_allow_addr_req => sig_sf_allow_addr_req +\dm_address[24]_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][24]\, + I1 => \^load_new_addr\, + I2 => dm_address_reg(24), + O => \dm_address[24]_i_5_n_0\ ); -DYNSHREG_F_I: entity work.\Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1\ - port map ( - FIFO_Full_reg => FIFO_Full_reg_n_0, - Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_2, - Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_3, - \in\(37 downto 0) => \in\(37 downto 0), - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - \out\(39 downto 0) => \out\(39 downto 0), - sig_addr_valid_reg_reg => sig_addr_valid_reg_reg, - sig_calc_error_reg_reg => \^sel\, - sig_inhibit_rdy_n => sig_inhibit_rdy_n, - sig_mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid +\dm_address[28]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\, + I1 => \^load_new_addr\, + I2 => dm_address_reg(31), + O => \dm_address[28]_i_2_n_0\ ); -FIFO_Full_reg: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => fifo_full_p1, - Q => FIFO_Full_reg_n_0, - R => SR(0) +\dm_address[28]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][30]\, + I1 => \^load_new_addr\, + I2 => dm_address_reg(30), + O => \dm_address[28]_i_3_n_0\ ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized2\ is - port ( - sig_dqual_reg_empty_reg : out STD_LOGIC; - sel : out STD_LOGIC; - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - D : out STD_LOGIC_VECTOR ( 7 downto 0 ); - sig_dqual_reg_empty_reg_0 : out STD_LOGIC; - sig_ld_new_cmd_reg_reg : out STD_LOGIC; - sig_last_dbeat_reg : out STD_LOGIC; - sig_next_cmd_cmplt_reg_reg : out STD_LOGIC; - \out\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - sig_mstr2data_cmd_valid : in STD_LOGIC; - sig_inhibit_rdy_n_0 : in STD_LOGIC; - \sig_dbeat_cntr_reg[2]\ : in STD_LOGIC; - Q : in STD_LOGIC_VECTOR ( 7 downto 0 ); - sig_next_sequential_reg : in STD_LOGIC; - sig_last_dbeat : in STD_LOGIC; - sig_dqual_reg_empty : in STD_LOGIC; - m_axi_mm2s_rvalid : in STD_LOGIC; - sig_halt_reg_reg : in STD_LOGIC; - ram_full_i_reg : in STD_LOGIC; - \sig_advance_pipe9_out__1\ : in STD_LOGIC; - sig_rsc2stat_status_valid : in STD_LOGIC; - FIFO_Full_reg_0 : in STD_LOGIC; - sig_inhibit_rdy_n : in STD_LOGIC; - sig_next_calc_error_reg : in STD_LOGIC; - sig_addr_posted_cntr : in STD_LOGIC_VECTOR ( 2 downto 0 ); - sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; - sig_ld_new_cmd_reg : in STD_LOGIC; - sig_dbeat_cntr_eq_1 : in STD_LOGIC; - sig_dqual_reg_full : in STD_LOGIC; - m_axi_mm2s_rlast : in STD_LOGIC; - \sig_dbeat_cntr_reg[3]\ : in STD_LOGIC; - \sig_dbeat_cntr_reg[4]\ : in STD_LOGIC; - \in\ : in STD_LOGIC_VECTOR ( 7 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized2\ : entity is "srl_fifo_rbu_f"; -end \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized2\; - -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized2\ is - signal CNTR_INCR_DECR_ADDN_F_I_n_2 : STD_LOGIC; - signal CNTR_INCR_DECR_ADDN_F_I_n_3 : STD_LOGIC; - signal FIFO_Full_reg_n_0 : STD_LOGIC; - signal fifo_full_p1 : STD_LOGIC; - signal \^sel\ : STD_LOGIC; - signal \^sig_dqual_reg_empty_reg\ : STD_LOGIC; - signal \^sig_dqual_reg_empty_reg_0\ : STD_LOGIC; -begin - sel <= \^sel\; - sig_dqual_reg_empty_reg <= \^sig_dqual_reg_empty_reg\; - sig_dqual_reg_empty_reg_0 <= \^sig_dqual_reg_empty_reg_0\; -CNTR_INCR_DECR_ADDN_F_I: entity work.Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f - port map ( - D(3 downto 0) => D(7 downto 4), - E(0) => E(0), - FIFO_Full_reg => FIFO_Full_reg_n_0, - FIFO_Full_reg_0 => FIFO_Full_reg_0, - Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_2, - Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_3, - SR(0) => SR(0), - fifo_full_p1 => fifo_full_p1, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axi_mm2s_rlast => m_axi_mm2s_rlast, - m_axi_mm2s_rvalid => m_axi_mm2s_rvalid, - ram_full_i_reg => ram_full_i_reg, - sig_addr_posted_cntr(2 downto 0) => sig_addr_posted_cntr(2 downto 0), - \sig_advance_pipe9_out__1\ => \sig_advance_pipe9_out__1\, - sig_cmd2data_valid_reg => \^sel\, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - \sig_dbeat_cntr_reg[2]\ => \sig_dbeat_cntr_reg[2]\, - \sig_dbeat_cntr_reg[3]\ => \sig_dbeat_cntr_reg[3]\, - \sig_dbeat_cntr_reg[4]\ => \sig_dbeat_cntr_reg[4]\, - \sig_dbeat_cntr_reg[7]\(7 downto 0) => Q(7 downto 0), - sig_dqual_reg_empty => sig_dqual_reg_empty, - sig_dqual_reg_empty_reg => \^sig_dqual_reg_empty_reg\, - sig_dqual_reg_empty_reg_0 => \^sig_dqual_reg_empty_reg_0\, - sig_dqual_reg_full => sig_dqual_reg_full, - sig_halt_reg_reg => sig_halt_reg_reg, - sig_inhibit_rdy_n => sig_inhibit_rdy_n, - sig_inhibit_rdy_n_0 => sig_inhibit_rdy_n_0, - sig_last_dbeat => sig_last_dbeat, - sig_ld_new_cmd_reg => sig_ld_new_cmd_reg, - sig_ld_new_cmd_reg_reg => sig_ld_new_cmd_reg_reg, - sig_mstr2data_cmd_valid => sig_mstr2data_cmd_valid, - sig_next_calc_error_reg => sig_next_calc_error_reg, - sig_next_cmd_cmplt_reg_reg => sig_next_cmd_cmplt_reg_reg, - sig_next_sequential_reg => sig_next_sequential_reg, - sig_rsc2stat_status_valid => sig_rsc2stat_status_valid +\dm_address[28]_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][29]\, + I1 => \^load_new_addr\, + I2 => dm_address_reg(29), + O => \dm_address[28]_i_4_n_0\ ); -DYNSHREG_F_I: entity work.\Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized2\ - port map ( - D(3 downto 0) => D(3 downto 0), - FIFO_Full_reg => FIFO_Full_reg_n_0, - \INFERRED_GEN.cnt_i_reg[1]\(1) => CNTR_INCR_DECR_ADDN_F_I_n_2, - \INFERRED_GEN.cnt_i_reg[1]\(0) => CNTR_INCR_DECR_ADDN_F_I_n_3, - Q(3 downto 0) => Q(3 downto 0), - \in\(7 downto 0) => \in\(7 downto 0), - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - \out\(3 downto 0) => \out\(3 downto 0), - sig_dbeat_cntr_eq_1 => sig_dbeat_cntr_eq_1, - \sig_dbeat_cntr_reg[2]\ => \sig_dbeat_cntr_reg[2]\, - sig_halt_reg_reg => \^sig_dqual_reg_empty_reg_0\, - sig_inhibit_rdy_n_0 => sig_inhibit_rdy_n_0, - sig_last_dbeat => sig_last_dbeat, - sig_last_dbeat_reg => sig_last_dbeat_reg, - sig_mstr2data_cmd_valid => sig_mstr2data_cmd_valid, - sig_next_calc_error_reg_reg => \^sel\, - sig_next_sequential_reg_reg => \^sig_dqual_reg_empty_reg\ +\dm_address[28]_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][28]\, + I1 => \^load_new_addr\, + I2 => dm_address_reg(28), + O => \dm_address[28]_i_5_n_0\ ); -FIFO_Full_reg: unisim.vcomponents.FDRE - port map ( +\dm_address_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => fifo_full_p1, - Q => FIFO_Full_reg_n_0, + CE => \dm_address[0]_i_1_n_0\, + D => O(0), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(0), R => SR(0) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized3\ is - port ( - p_0_out : out STD_LOGIC_VECTOR ( 0 to 0 ); - FIFO_Full_reg_0 : out STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[1]\ : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 0 to 0 ); - \in\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - sig_stream_rst : in STD_LOGIC; - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : in STD_LOGIC; - sig_mstr2sf_cmd_valid : in STD_LOGIC; - sig_inhibit_rdy_n_reg : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized3\ : entity is "srl_fifo_rbu_f"; -end \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized3\; - -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized3\ is - signal CNTR_INCR_DECR_ADDN_F_I_n_2 : STD_LOGIC; - signal CNTR_INCR_DECR_ADDN_F_I_n_3 : STD_LOGIC; - signal \^fifo_full_reg_0\ : STD_LOGIC; - signal \^inferred_gen.cnt_i_reg[1]\ : STD_LOGIC; - signal fifo_full_p1 : STD_LOGIC; -begin - FIFO_Full_reg_0 <= \^fifo_full_reg_0\; - \INFERRED_GEN.cnt_i_reg[1]\ <= \^inferred_gen.cnt_i_reg[1]\; -CNTR_INCR_DECR_ADDN_F_I: entity work.Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_6 - port map ( - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\, - FIFO_Full_reg => \^fifo_full_reg_0\, - FIFO_Full_reg_0 => \^inferred_gen.cnt_i_reg[1]\, - Q(2) => Q(0), - Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_2, - Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_3, - fifo_full_p1 => fifo_full_p1, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - sig_inhibit_rdy_n_reg => sig_inhibit_rdy_n_reg, - sig_mstr2sf_cmd_valid => sig_mstr2sf_cmd_valid, - sig_stream_rst => sig_stream_rst - ); -DYNSHREG_F_I: entity work.\Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized3\ - port map ( - Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_2, - Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_3, - \in\(0) => \in\(0), - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - p_0_out(0) => p_0_out(0), - sig_cmd2dre_valid_reg => \^fifo_full_reg_0\ +\dm_address_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => \dm_address[0]_i_1_n_0\, + D => \stride_vid_reg[11]\(2), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(10), + R => SR(0) ); -FIFO_Full_reg: unisim.vcomponents.FDRE - port map ( +\dm_address_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => fifo_full_p1, - Q => \^inferred_gen.cnt_i_reg[1]\, - R => sig_stream_rst + CE => \dm_address[0]_i_1_n_0\, + D => \stride_vid_reg[11]\(3), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(11), + R => SR(0) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_width is - port ( - DOBDO : out STD_LOGIC_VECTOR ( 0 to 0 ); - \sig_user_skid_reg_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - dm2linebuf_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : out STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[0]\ : out STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - ram_empty_fb_i_reg : in STD_LOGIC; - ram_full_i_reg : in STD_LOGIC; - \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC; - sig_stream_rst : in STD_LOGIC; - \gc1.count_d2_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); - Q : in STD_LOGIC_VECTOR ( 6 downto 0 ); - m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); - DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ); - lsig_0ffset_cntr : in STD_LOGIC; - lsig_cmd_loaded : in STD_LOGIC; - \gpregsm1.user_valid_reg\ : in STD_LOGIC; - hold_ff_q : in STD_LOGIC; - p_0_out : in STD_LOGIC_VECTOR ( 0 to 0 ); - dm2linebuf_mm2s_tvalid : in STD_LOGIC; - p_8_out : in STD_LOGIC; - \fifo_wren__0\ : in STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; -end Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_width; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_width is -begin -\prim_noinit.ram\: entity work.Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_wrapper - port map ( - DIBDI(1 downto 0) => DIBDI(1 downto 0), - DOBDO(0) => DOBDO(0), - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, - \INFERRED_GEN.cnt_i_reg[0]\ => \INFERRED_GEN.cnt_i_reg[0]\, - \INFERRED_GEN.cnt_i_reg[2]\(0) => \INFERRED_GEN.cnt_i_reg[2]\(0), - Q(6 downto 0) => Q(6 downto 0), - dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), - dm2linebuf_mm2s_tvalid => dm2linebuf_mm2s_tvalid, - \fifo_wren__0\ => \fifo_wren__0\, - \gc1.count_d2_reg[6]\(6 downto 0) => \gc1.count_d2_reg[6]\(6 downto 0), - \gpregsm1.curr_fwft_state_reg[0]\ => \gpregsm1.curr_fwft_state_reg[0]\, - \gpregsm1.user_valid_reg\ => \gpregsm1.user_valid_reg\, - hold_ff_q => hold_ff_q, - lsig_0ffset_cntr => lsig_0ffset_cntr, - lsig_cmd_loaded => lsig_cmd_loaded, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axi_mm2s_rdata(63 downto 0) => m_axi_mm2s_rdata(63 downto 0), - p_0_out(0) => p_0_out(0), - p_8_out => p_8_out, - ram_empty_fb_i_reg => ram_empty_fb_i_reg, - ram_full_i_reg => ram_full_i_reg, - sig_stream_rst => sig_stream_rst, - \sig_user_skid_reg_reg[0]\(0) => \sig_user_skid_reg_reg[0]\(0) +\dm_address_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => \dm_address[0]_i_1_n_0\, + D => \stride_vid_reg[15]\(0), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(12), + R => SR(0) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6 is - port ( - EMPTY : out STD_LOGIC; - FULL : out STD_LOGIC; - fifo_dout : out STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axis_mm2s_aclk : in STD_LOGIC; - RD_EN : in STD_LOGIC; - RST : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - WR_EN : in STD_LOGIC; - dm2linebuf_mm2s_tdata : in STD_LOGIC_VECTOR ( 8 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6 : entity is "builtin_extdepth_v6"; -end Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6 is - signal \NLW_gextw[1].gnll_fifo.inst_extdi_0_O_UNCONNECTED\ : STD_LOGIC; - signal \NLW_gextw[1].gnll_fifo.inst_extdi_1_O_UNCONNECTED\ : STD_LOGIC; - signal \NLW_gextw[1].gnll_fifo.inst_extdi_2_O_UNCONNECTED\ : STD_LOGIC; - signal \NLW_gextw[1].gnll_fifo.inst_extdi_3_O_UNCONNECTED\ : STD_LOGIC; -begin -\gextw[1].gnll_fifo.inst_extdi_0\: unisim.vcomponents.LUT1 +\dm_address_reg[13]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => \NLW_gextw[1].gnll_fifo.inst_extdi_0_O_UNCONNECTED\ + C => m_axi_mm2s_aclk, + CE => \dm_address[0]_i_1_n_0\, + D => \stride_vid_reg[15]\(1), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(13), + R => SR(0) ); -\gextw[1].gnll_fifo.inst_extdi_1\: unisim.vcomponents.LUT1 +\dm_address_reg[14]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => \NLW_gextw[1].gnll_fifo.inst_extdi_1_O_UNCONNECTED\ + C => m_axi_mm2s_aclk, + CE => \dm_address[0]_i_1_n_0\, + D => \stride_vid_reg[15]\(2), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(14), + R => SR(0) ); -\gextw[1].gnll_fifo.inst_extdi_2\: unisim.vcomponents.LUT1 +\dm_address_reg[15]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => \NLW_gextw[1].gnll_fifo.inst_extdi_2_O_UNCONNECTED\ + C => m_axi_mm2s_aclk, + CE => \dm_address[0]_i_1_n_0\, + D => \stride_vid_reg[15]\(3), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(15), + R => SR(0) ); -\gextw[1].gnll_fifo.inst_extdi_3\: unisim.vcomponents.LUT1 +\dm_address_reg[16]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => \NLW_gextw[1].gnll_fifo.inst_extdi_3_O_UNCONNECTED\ + C => m_axi_mm2s_aclk, + CE => \dm_address[0]_i_1_n_0\, + D => \dm_address_reg[16]_i_1_n_7\, + Q => dm_address_reg(16), + R => SR(0) ); -\gonep.inst_prim\: entity work.Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_12 +\dm_address_reg[16]_i_1\: unisim.vcomponents.CARRY4 port map ( - EMPTY => EMPTY, - FULL => FULL, - RD_EN => RD_EN, - RST => RST, - WR_EN => WR_EN, - dm2linebuf_mm2s_tdata(8 downto 0) => dm2linebuf_mm2s_tdata(8 downto 0), - fifo_dout(8 downto 0) => fifo_dout(8 downto 0), - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axis_mm2s_aclk => m_axis_mm2s_aclk + CI => CO(0), + CO(3) => \dm_address_reg[16]_i_1_n_0\, + CO(2) => \dm_address_reg[16]_i_1_n_1\, + CO(1) => \dm_address_reg[16]_i_1_n_2\, + CO(0) => \dm_address_reg[16]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \dm_address_reg[16]_i_1_n_4\, + O(2) => \dm_address_reg[16]_i_1_n_5\, + O(1) => \dm_address_reg[16]_i_1_n_6\, + O(0) => \dm_address_reg[16]_i_1_n_7\, + S(3) => \dm_address[16]_i_2_n_0\, + S(2) => \dm_address[16]_i_3_n_0\, + S(1) => \dm_address[16]_i_4_n_0\, + S(0) => \dm_address[16]_i_5_n_0\ ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_7 is - port ( - fifo_full_i : out STD_LOGIC; - FULL : out STD_LOGIC; - sig_m_valid_out_reg : out STD_LOGIC; - EMPTY : out STD_LOGIC; - fifo_dout : out STD_LOGIC_VECTOR ( 8 downto 0 ); - sig_s_ready_out_reg : in STD_LOGIC; - sig_s_ready_out_reg_0 : in STD_LOGIC; - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ : in STD_LOGIC; - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\ : in STD_LOGIC; - sig_s_ready_out_reg_1 : in STD_LOGIC; - sig_s_ready_out_reg_2 : in STD_LOGIC; - m_axis_mm2s_aclk : in STD_LOGIC; - RD_EN : in STD_LOGIC; - RST : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - WR_EN : in STD_LOGIC; - dm2linebuf_mm2s_tdata : in STD_LOGIC_VECTOR ( 8 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_7 : entity is "builtin_extdepth_v6"; -end Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_7; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_7 is - signal NLW_i_0_O_UNCONNECTED : STD_LOGIC; - signal NLW_i_1_O_UNCONNECTED : STD_LOGIC; - signal NLW_i_2_O_UNCONNECTED : STD_LOGIC; - signal NLW_i_3_O_UNCONNECTED : STD_LOGIC; -begin -\gonep.inst_prim\: entity work.Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_11 - port map ( - EMPTY => EMPTY, - FULL => FULL, - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\, - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\, - RD_EN => RD_EN, - RST => RST, - WR_EN => WR_EN, - dm2linebuf_mm2s_tdata(8 downto 0) => dm2linebuf_mm2s_tdata(8 downto 0), - fifo_dout(8 downto 0) => fifo_dout(8 downto 0), - fifo_full_i => fifo_full_i, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axis_mm2s_aclk => m_axis_mm2s_aclk, - sig_m_valid_out_reg => sig_m_valid_out_reg, - sig_s_ready_out_reg => sig_s_ready_out_reg, - sig_s_ready_out_reg_0 => sig_s_ready_out_reg_0, - sig_s_ready_out_reg_1 => sig_s_ready_out_reg_1, - sig_s_ready_out_reg_2 => sig_s_ready_out_reg_2 +\dm_address_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => \dm_address[0]_i_1_n_0\, + D => \dm_address_reg[16]_i_1_n_6\, + Q => dm_address_reg(17), + R => SR(0) ); -i_0: unisim.vcomponents.LUT1 +\dm_address_reg[18]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => NLW_i_0_O_UNCONNECTED + C => m_axi_mm2s_aclk, + CE => \dm_address[0]_i_1_n_0\, + D => \dm_address_reg[16]_i_1_n_5\, + Q => dm_address_reg(18), + R => SR(0) ); -i_1: unisim.vcomponents.LUT1 +\dm_address_reg[19]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => NLW_i_1_O_UNCONNECTED + C => m_axi_mm2s_aclk, + CE => \dm_address[0]_i_1_n_0\, + D => \dm_address_reg[16]_i_1_n_4\, + Q => dm_address_reg(19), + R => SR(0) ); -i_2: unisim.vcomponents.LUT1 +\dm_address_reg[1]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => NLW_i_2_O_UNCONNECTED + C => m_axi_mm2s_aclk, + CE => \dm_address[0]_i_1_n_0\, + D => O(1), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(1), + R => SR(0) ); -i_3: unisim.vcomponents.LUT1 +\dm_address_reg[20]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => NLW_i_3_O_UNCONNECTED + C => m_axi_mm2s_aclk, + CE => \dm_address[0]_i_1_n_0\, + D => \dm_address_reg[20]_i_1_n_7\, + Q => dm_address_reg(20), + R => SR(0) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_8 is - port ( - RD_EN : out STD_LOGIC; - EMPTY : out STD_LOGIC; - FULL : out STD_LOGIC; - fifo_dout : out STD_LOGIC_VECTOR ( 8 downto 0 ); - \out\ : in STD_LOGIC; - sig_s_ready_out_reg : in STD_LOGIC; - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ : in STD_LOGIC; - sig_s_ready_out_reg_0 : in STD_LOGIC; - m_axis_mm2s_aclk : in STD_LOGIC; - RST : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - WR_EN : in STD_LOGIC; - dm2linebuf_mm2s_tdata : in STD_LOGIC_VECTOR ( 8 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_8 : entity is "builtin_extdepth_v6"; -end Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_8; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_8 is - signal NLW_i_0_O_UNCONNECTED : STD_LOGIC; - signal NLW_i_1_O_UNCONNECTED : STD_LOGIC; - signal NLW_i_2_O_UNCONNECTED : STD_LOGIC; - signal NLW_i_3_O_UNCONNECTED : STD_LOGIC; -begin -\gonep.inst_prim\: entity work.Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_10 +\dm_address_reg[20]_i_1\: unisim.vcomponents.CARRY4 port map ( - EMPTY => EMPTY, - FULL => FULL, - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\, - RD_EN => RD_EN, - RST => RST, - WR_EN => WR_EN, - dm2linebuf_mm2s_tdata(8 downto 0) => dm2linebuf_mm2s_tdata(8 downto 0), - fifo_dout(8 downto 0) => fifo_dout(8 downto 0), - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axis_mm2s_aclk => m_axis_mm2s_aclk, - \out\ => \out\, - sig_s_ready_out_reg => sig_s_ready_out_reg, - sig_s_ready_out_reg_0 => sig_s_ready_out_reg_0 + CI => \dm_address_reg[16]_i_1_n_0\, + CO(3) => \dm_address_reg[20]_i_1_n_0\, + CO(2) => \dm_address_reg[20]_i_1_n_1\, + CO(1) => \dm_address_reg[20]_i_1_n_2\, + CO(0) => \dm_address_reg[20]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \dm_address_reg[20]_i_1_n_4\, + O(2) => \dm_address_reg[20]_i_1_n_5\, + O(1) => \dm_address_reg[20]_i_1_n_6\, + O(0) => \dm_address_reg[20]_i_1_n_7\, + S(3) => \dm_address[20]_i_2_n_0\, + S(2) => \dm_address[20]_i_3_n_0\, + S(1) => \dm_address[20]_i_4_n_0\, + S(0) => \dm_address[20]_i_5_n_0\ ); -i_0: unisim.vcomponents.LUT1 +\dm_address_reg[21]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => NLW_i_0_O_UNCONNECTED + C => m_axi_mm2s_aclk, + CE => \dm_address[0]_i_1_n_0\, + D => \dm_address_reg[20]_i_1_n_6\, + Q => dm_address_reg(21), + R => SR(0) ); -i_1: unisim.vcomponents.LUT1 +\dm_address_reg[22]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => NLW_i_1_O_UNCONNECTED + C => m_axi_mm2s_aclk, + CE => \dm_address[0]_i_1_n_0\, + D => \dm_address_reg[20]_i_1_n_5\, + Q => dm_address_reg(22), + R => SR(0) ); -i_2: unisim.vcomponents.LUT1 +\dm_address_reg[23]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => NLW_i_2_O_UNCONNECTED + C => m_axi_mm2s_aclk, + CE => \dm_address[0]_i_1_n_0\, + D => \dm_address_reg[20]_i_1_n_4\, + Q => dm_address_reg(23), + R => SR(0) ); -i_3: unisim.vcomponents.LUT1 +\dm_address_reg[24]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => NLW_i_3_O_UNCONNECTED + C => m_axi_mm2s_aclk, + CE => \dm_address[0]_i_1_n_0\, + D => \dm_address_reg[24]_i_1_n_7\, + Q => dm_address_reg(24), + R => SR(0) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_9 is - port ( - WR_EN : out STD_LOGIC; - FULL : out STD_LOGIC; - EMPTY : out STD_LOGIC; - fifo_dout : out STD_LOGIC_VECTOR ( 6 downto 0 ); - \fifo_wren__0\ : in STD_LOGIC; - sig_s_ready_out_reg : in STD_LOGIC; - sig_s_ready_out_reg_0 : in STD_LOGIC; - sig_s_ready_out_reg_1 : in STD_LOGIC; - m_axis_mm2s_aclk : in STD_LOGIC; - RD_EN : in STD_LOGIC; - RST : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - DIN : in STD_LOGIC_VECTOR ( 6 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_9 : entity is "builtin_extdepth_v6"; -end Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_9; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_9 is - signal NLW_i_0_O_UNCONNECTED : STD_LOGIC; - signal NLW_i_1_O_UNCONNECTED : STD_LOGIC; - signal NLW_i_2_O_UNCONNECTED : STD_LOGIC; - signal NLW_i_3_O_UNCONNECTED : STD_LOGIC; -begin -\gonep.inst_prim\: entity work.Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6 +\dm_address_reg[24]_i_1\: unisim.vcomponents.CARRY4 port map ( - DIN(6 downto 0) => DIN(6 downto 0), - EMPTY => EMPTY, - FULL => FULL, - RD_EN => RD_EN, - RST => RST, - WR_EN => WR_EN, - fifo_dout(6 downto 0) => fifo_dout(6 downto 0), - \fifo_wren__0\ => \fifo_wren__0\, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axis_mm2s_aclk => m_axis_mm2s_aclk, - sig_s_ready_out_reg => sig_s_ready_out_reg, - sig_s_ready_out_reg_0 => sig_s_ready_out_reg_0, - sig_s_ready_out_reg_1 => sig_s_ready_out_reg_1 + CI => \dm_address_reg[20]_i_1_n_0\, + CO(3) => \dm_address_reg[24]_i_1_n_0\, + CO(2) => \dm_address_reg[24]_i_1_n_1\, + CO(1) => \dm_address_reg[24]_i_1_n_2\, + CO(0) => \dm_address_reg[24]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \dm_address_reg[24]_i_1_n_4\, + O(2) => \dm_address_reg[24]_i_1_n_5\, + O(1) => \dm_address_reg[24]_i_1_n_6\, + O(0) => \dm_address_reg[24]_i_1_n_7\, + S(3) => \dm_address[24]_i_2_n_0\, + S(2) => \dm_address[24]_i_3_n_0\, + S(1) => \dm_address[24]_i_4_n_0\, + S(0) => \dm_address[24]_i_5_n_0\ ); -i_0: unisim.vcomponents.LUT1 +\dm_address_reg[25]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => NLW_i_0_O_UNCONNECTED + C => m_axi_mm2s_aclk, + CE => \dm_address[0]_i_1_n_0\, + D => \dm_address_reg[24]_i_1_n_6\, + Q => dm_address_reg(25), + R => SR(0) ); -i_1: unisim.vcomponents.LUT1 +\dm_address_reg[26]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => NLW_i_1_O_UNCONNECTED + C => m_axi_mm2s_aclk, + CE => \dm_address[0]_i_1_n_0\, + D => \dm_address_reg[24]_i_1_n_5\, + Q => dm_address_reg(26), + R => SR(0) ); -i_2: unisim.vcomponents.LUT1 +\dm_address_reg[27]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => NLW_i_2_O_UNCONNECTED + C => m_axi_mm2s_aclk, + CE => \dm_address[0]_i_1_n_0\, + D => \dm_address_reg[24]_i_1_n_4\, + Q => dm_address_reg(27), + R => SR(0) ); -i_3: unisim.vcomponents.LUT1 +\dm_address_reg[28]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => '0', - O => NLW_i_3_O_UNCONNECTED - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_dc_ss is - port ( - DI : out STD_LOGIC_VECTOR ( 3 downto 0 ); - Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); - sig_ok_to_post_rd_addr_reg : out STD_LOGIC; - S : out STD_LOGIC_VECTOR ( 3 downto 0 ); - \count_reg[6]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); - ram_full_i_reg : in STD_LOGIC; - \sig_token_cntr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); - sig_posted_to_axi_2_reg : in STD_LOGIC; - sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; - sig_posted_to_axi_2_reg_0 : in STD_LOGIC; - E : in STD_LOGIC_VECTOR ( 0 to 0 ); - sig_stream_rst : in STD_LOGIC; - \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - D : in STD_LOGIC_VECTOR ( 5 downto 0 ); - m_axi_mm2s_aclk : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_dc_ss : entity is "dc_ss"; -end Arty_Z7_20_axi_vdma_0_0_dc_ss; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_dc_ss is -begin -\gsym_dc.dc\: entity work.Arty_Z7_20_axi_vdma_0_0_updn_cntr - port map ( - D(5 downto 0) => D(5 downto 0), - DI(3 downto 0) => DI(3 downto 0), - E(0) => E(0), - Q(1 downto 0) => Q(1 downto 0), - S(3 downto 0) => S(3 downto 0), - \count_reg[6]_0\(1 downto 0) => \count_reg[6]\(1 downto 0), - \gpregsm1.curr_fwft_state_reg[0]\(0) => \gpregsm1.curr_fwft_state_reg[0]\(0), - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - ram_full_i_reg => ram_full_i_reg, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_ok_to_post_rd_addr_reg => sig_ok_to_post_rd_addr_reg, - sig_posted_to_axi_2_reg => sig_posted_to_axi_2_reg, - sig_posted_to_axi_2_reg_0 => sig_posted_to_axi_2_reg_0, - sig_stream_rst => sig_stream_rst, - \sig_token_cntr_reg[3]\(3 downto 0) => \sig_token_cntr_reg[3]\(3 downto 0) - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_wr_logic is - port ( - \out\ : out STD_LOGIC; - \ram_empty_i0__3\ : out STD_LOGIC; - \gcc0.gc0.count_d1_reg[6]\ : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 6 downto 0 ); - sig_stream_rst : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - p_7_out : in STD_LOGIC; - ram_empty_fb_i_reg : in STD_LOGIC; - \gc1.count_d2_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); - \gc1.count_d1_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); - \mm2s_strm_wvalid0__1\ : in STD_LOGIC; - m_axi_mm2s_rvalid : in STD_LOGIC; - \sig_advance_pipe9_out__1\ : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_wr_logic : entity is "wr_logic"; -end Arty_Z7_20_axi_vdma_0_0_wr_logic; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_wr_logic is - signal \^gcc0.gc0.count_d1_reg[6]\ : STD_LOGIC; - signal \gwss.wsts_n_0\ : STD_LOGIC; - signal wpntr_n_8 : STD_LOGIC; -begin - \gcc0.gc0.count_d1_reg[6]\ <= \^gcc0.gc0.count_d1_reg[6]\; -\gwss.wsts\: entity work.Arty_Z7_20_axi_vdma_0_0_wr_status_flags_ss - port map ( - E(0) => \^gcc0.gc0.count_d1_reg[6]\, - \gcc0.gc0.count_d1_reg[6]\ => \out\, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axi_mm2s_rvalid => m_axi_mm2s_rvalid, - \mm2s_strm_wvalid0__1\ => \mm2s_strm_wvalid0__1\, - \out\ => \gwss.wsts_n_0\, - ram_full_fb_i_reg_0 => wpntr_n_8, - \sig_advance_pipe9_out__1\ => \sig_advance_pipe9_out__1\, - sig_stream_rst => sig_stream_rst + C => m_axi_mm2s_aclk, + CE => \dm_address[0]_i_1_n_0\, + D => \dm_address_reg[28]_i_1_n_7\, + Q => dm_address_reg(28), + R => SR(0) ); -wpntr: entity work.Arty_Z7_20_axi_vdma_0_0_wr_bin_cntr +\dm_address_reg[28]_i_1\: unisim.vcomponents.CARRY4 port map ( - E(0) => \^gcc0.gc0.count_d1_reg[6]\, - Q(6 downto 0) => Q(6 downto 0), - \gc1.count_d1_reg[6]\(6 downto 0) => \gc1.count_d1_reg[6]\(6 downto 0), - \gc1.count_d2_reg[6]\(6 downto 0) => \gc1.count_d2_reg[6]\(6 downto 0), - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - \out\ => \gwss.wsts_n_0\, - p_7_out => p_7_out, - ram_empty_fb_i_reg => ram_empty_fb_i_reg, - \ram_empty_i0__3\ => \ram_empty_i0__3\, - ram_full_i_reg => wpntr_n_8, - sig_stream_rst => sig_stream_rst + CI => \dm_address_reg[24]_i_1_n_0\, + CO(3) => \NLW_dm_address_reg[28]_i_1_CO_UNCONNECTED\(3), + CO(2) => \dm_address_reg[28]_i_1_n_1\, + CO(1) => \dm_address_reg[28]_i_1_n_2\, + CO(0) => \dm_address_reg[28]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \dm_address_reg[28]_i_1_n_4\, + O(2) => \dm_address_reg[28]_i_1_n_5\, + O(1) => \dm_address_reg[28]_i_1_n_6\, + O(0) => \dm_address_reg[28]_i_1_n_7\, + S(3) => \dm_address[28]_i_2_n_0\, + S(2) => \dm_address[28]_i_3_n_0\, + S(1) => \dm_address[28]_i_4_n_0\, + S(0) => \dm_address[28]_i_5_n_0\ ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_mngr is - port ( - cmnd_wr : out STD_LOGIC; - p_57_out : out STD_LOGIC; - p_36_out : out STD_LOGIC; - p_44_out : out STD_LOGIC; - in0 : out STD_LOGIC_VECTOR ( 0 to 0 ); - p_35_out : out STD_LOGIC; - p_49_out : out STD_LOGIC; - p_55_out : out STD_LOGIC; - \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg\ : out STD_LOGIC; - dma_err : out STD_LOGIC; - datamover_idle : out STD_LOGIC; - prmtr_update_complete : out STD_LOGIC; - p_46_out : out STD_LOGIC; - initial_frame : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 12 downto 0 ); - p_37_out : out STD_LOGIC; - \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); - p_2_out : out STD_LOGIC; - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg\ : out STD_LOGIC; - halted_reg : out STD_LOGIC; - dma_decerr_reg : out STD_LOGIC; - dma_slverr_reg : out STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[1]\ : out STD_LOGIC; - dma_interr_reg : out STD_LOGIC; - \sig_addr_cntr_lsh_kh_reg[31]\ : out STD_LOGIC_VECTOR ( 48 downto 0 ); - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); - p_0_in : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - p_0_out : in STD_LOGIC; - \out\ : in STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[2]\ : in STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[2]_0\ : in STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[2]_1\ : in STD_LOGIC; - p_68_out : in STD_LOGIC_VECTOR ( 2 downto 0 ); - p_45_out : in STD_LOGIC; - stop_i : in STD_LOGIC; - p_23_out : in STD_LOGIC; - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - E : in STD_LOGIC_VECTOR ( 0 to 0 ); - \dmacr_i_reg[0]\ : in STD_LOGIC; - prmtr_updt_complete_i_reg : in STD_LOGIC; - p_1_out : in STD_LOGIC; - p_64_out : in STD_LOGIC; - halt_i_reg : in STD_LOGIC; - mm2s_halt : in STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[2]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - \ptr_ref_i_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); - mask_fsync_out_i : in STD_LOGIC; - ch1_delay_cnt_en : in STD_LOGIC; - p_17_out : in STD_LOGIC; - ch1_disable_delay2_out : in STD_LOGIC; - p_67_out : in STD_LOGIC; - dma_decerr_reg_0 : in STD_LOGIC; - dma_slverr_reg_0 : in STD_LOGIC; - D : in STD_LOGIC_VECTOR ( 0 to 0 ); - mm2s_axi2ip_wrce : in STD_LOGIC_VECTOR ( 0 to 0 ); - dma_interr_reg_0 : in STD_LOGIC; - \reg_module_vsize_reg[12]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); - \reg_module_hsize_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); - \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); - prmry_resetn_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); - halt_i_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_mngr : entity is "axi_vdma_mngr"; -end Arty_Z7_20_axi_vdma_0_0_axi_vdma_mngr; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_mngr is - signal C : STD_LOGIC_VECTOR ( 31 downto 16 ); - signal I_CMDSTS_n_1 : STD_LOGIC; - signal I_CMDSTS_n_6 : STD_LOGIC; - signal I_CMDSTS_n_7 : STD_LOGIC; - signal I_SM_n_31 : STD_LOGIC; - signal I_SM_n_32 : STD_LOGIC; - signal I_SM_n_33 : STD_LOGIC; - signal I_SM_n_34 : STD_LOGIC; - signal I_SM_n_35 : STD_LOGIC; - signal I_SM_n_36 : STD_LOGIC; - signal I_SM_n_37 : STD_LOGIC; - signal I_SM_n_38 : STD_LOGIC; - signal I_SM_n_39 : STD_LOGIC; - signal I_SM_n_40 : STD_LOGIC; - signal I_SM_n_41 : STD_LOGIC; - signal I_SM_n_42 : STD_LOGIC; - signal I_SM_n_43 : STD_LOGIC; - signal I_SM_n_44 : STD_LOGIC; - signal I_SM_n_45 : STD_LOGIC; - signal I_SM_n_46 : STD_LOGIC; - signal I_SM_n_47 : STD_LOGIC; - signal I_SM_n_48 : STD_LOGIC; - signal I_SM_n_49 : STD_LOGIC; - signal I_SM_n_50 : STD_LOGIC; - signal I_SM_n_51 : STD_LOGIC; - signal I_SM_n_52 : STD_LOGIC; - signal I_SM_n_53 : STD_LOGIC; - signal I_SM_n_54 : STD_LOGIC; - signal I_SM_n_55 : STD_LOGIC; - signal I_SM_n_56 : STD_LOGIC; - signal I_SM_n_57 : STD_LOGIC; - signal I_SM_n_58 : STD_LOGIC; - signal I_SM_n_59 : STD_LOGIC; - signal I_SM_n_60 : STD_LOGIC; - signal I_SM_n_61 : STD_LOGIC; - signal I_SM_n_62 : STD_LOGIC; - signal I_SM_n_63 : STD_LOGIC; - signal I_SM_n_64 : STD_LOGIC; - signal I_SM_n_65 : STD_LOGIC; - signal I_SM_n_66 : STD_LOGIC; - signal I_SM_n_67 : STD_LOGIC; - signal I_SM_n_68 : STD_LOGIC; - signal I_SM_n_69 : STD_LOGIC; - signal I_SM_n_70 : STD_LOGIC; - signal I_SM_n_71 : STD_LOGIC; - signal I_SM_n_72 : STD_LOGIC; - signal I_SM_n_73 : STD_LOGIC; - signal I_SM_n_74 : STD_LOGIC; - signal I_SM_n_75 : STD_LOGIC; - signal I_SM_n_76 : STD_LOGIC; - signal I_SM_n_77 : STD_LOGIC; - signal I_SM_n_78 : STD_LOGIC; - signal I_SM_n_79 : STD_LOGIC; - signal I_SM_n_80 : STD_LOGIC; - signal I_SM_n_81 : STD_LOGIC; - signal I_SM_n_82 : STD_LOGIC; - signal I_SM_n_83 : STD_LOGIC; - signal I_SM_n_84 : STD_LOGIC; - signal I_SM_n_85 : STD_LOGIC; - signal I_SM_n_86 : STD_LOGIC; - signal I_SM_n_87 : STD_LOGIC; - signal \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal \MASTER_MODE_FRAME_CNT.frame_number_i[0]_i_1_n_0\ : STD_LOGIC; - signal \MASTER_MODE_FRAME_CNT.frame_number_i[1]_i_1_n_0\ : STD_LOGIC; - signal \MASTER_MODE_FRAME_CNT.frame_number_i[2]_i_1_n_0\ : STD_LOGIC; - signal \MASTER_MODE_FRAME_CNT.frame_number_i[3]_i_1_n_0\ : STD_LOGIC; - signal \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_3_n_0\ : STD_LOGIC; - signal \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_5_n_0\ : STD_LOGIC; - signal \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_6_n_0\ : STD_LOGIC; - signal \^q\ : STD_LOGIC_VECTOR ( 12 downto 0 ); - signal VIDEO_REG_I_n_17 : STD_LOGIC; - signal VIDEO_REG_I_n_18 : STD_LOGIC; - signal VIDEO_REG_I_n_36 : STD_LOGIC; - signal VIDEO_REG_I_n_37 : STD_LOGIC; - signal VIDEO_REG_I_n_38 : STD_LOGIC; - signal VIDEO_REG_I_n_39 : STD_LOGIC; - signal VIDEO_REG_I_n_40 : STD_LOGIC; - signal VIDEO_REG_I_n_41 : STD_LOGIC; - signal VIDEO_REG_I_n_42 : STD_LOGIC; - signal VIDEO_REG_I_n_43 : STD_LOGIC; - signal VIDEO_REG_I_n_44 : STD_LOGIC; - signal VIDEO_REG_I_n_45 : STD_LOGIC; - signal VIDEO_REG_I_n_46 : STD_LOGIC; - signal VIDEO_REG_I_n_47 : STD_LOGIC; - signal VIDEO_REG_I_n_48 : STD_LOGIC; - signal VIDEO_REG_I_n_49 : STD_LOGIC; - signal VIDEO_REG_I_n_50 : STD_LOGIC; - signal VIDEO_REG_I_n_51 : STD_LOGIC; - signal VIDEO_REG_I_n_52 : STD_LOGIC; - signal \^cmnd_wr\ : STD_LOGIC; - signal cmnds_queued_reg : STD_LOGIC_VECTOR ( 5 downto 0 ); - signal crnt_hsize : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal dm_address_reg : STD_LOGIC_VECTOR ( 15 downto 0 ); - signal \^dma_err\ : STD_LOGIC; - signal dmacntrl_ns14_out : STD_LOGIC; - signal frame_sync_reg : STD_LOGIC; - signal \^initial_frame\ : STD_LOGIC; - signal initial_frame_i_1_n_0 : STD_LOGIC; - signal load_new_addr : STD_LOGIC; - signal \p_0_out_carry__0_n_2\ : STD_LOGIC; - signal \p_0_out_carry__0_n_3\ : STD_LOGIC; - signal \p_0_out_carry__0_n_5\ : STD_LOGIC; - signal \p_0_out_carry__0_n_6\ : STD_LOGIC; - signal \p_0_out_carry__0_n_7\ : STD_LOGIC; - signal p_0_out_carry_n_0 : STD_LOGIC; - signal p_0_out_carry_n_1 : STD_LOGIC; - signal p_0_out_carry_n_2 : STD_LOGIC; - signal p_0_out_carry_n_3 : STD_LOGIC; - signal p_0_out_carry_n_4 : STD_LOGIC; - signal p_0_out_carry_n_5 : STD_LOGIC; - signal p_0_out_carry_n_6 : STD_LOGIC; - signal p_0_out_carry_n_7 : STD_LOGIC; - signal p_10_out : STD_LOGIC; - signal \^p_37_out\ : STD_LOGIC; - signal p_3_in : STD_LOGIC; - signal \^p_46_out\ : STD_LOGIC; - signal \^p_49_out\ : STD_LOGIC; - signal \^p_55_out\ : STD_LOGIC; - signal \^p_57_out\ : STD_LOGIC; - signal \p_6_out__0\ : STD_LOGIC; - signal tstvect_fsync_d1 : STD_LOGIC; - signal valid_frame_sync_d1 : STD_LOGIC; - signal valid_frame_sync_d2 : STD_LOGIC; - signal zero_hsize_err : STD_LOGIC; - signal zero_hsize_err0 : STD_LOGIC; - signal zero_vsize_err : STD_LOGIC; - signal zero_vsize_err0 : STD_LOGIC; - signal \NLW_p_0_out_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); - signal \NLW_p_0_out_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \MASTER_MODE_FRAME_CNT.frame_number_i[0]_i_1\ : label is "soft_lutpair33"; - attribute SOFT_HLUTNM of \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_5\ : label is "soft_lutpair33"; - attribute METHODOLOGY_DRC_VIOS : string; - attribute METHODOLOGY_DRC_VIOS of p_0_out_carry : label is "{SYNTH-8 {cell *THIS*}}"; - attribute METHODOLOGY_DRC_VIOS of \p_0_out_carry__0\ : label is "{SYNTH-8 {cell *THIS*}}"; -begin - \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0\(4 downto 0) <= \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(4 downto 0); - Q(12 downto 0) <= \^q\(12 downto 0); - cmnd_wr <= \^cmnd_wr\; - dma_err <= \^dma_err\; - initial_frame <= \^initial_frame\; - p_37_out <= \^p_37_out\; - p_46_out <= \^p_46_out\; - p_49_out <= \^p_49_out\; - p_55_out <= \^p_55_out\; - p_57_out <= \^p_57_out\; -\GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_i_1\: unisim.vcomponents.LUT5 +\dm_address_reg[29]\: unisim.vcomponents.FDRE generic map( - INIT => X"00AE0000" + INIT => '0' ) port map ( - I0 => \^p_49_out\, - I1 => ch1_delay_cnt_en, - I2 => p_17_out, - I3 => ch1_disable_delay2_out, - I4 => \out\, - O => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg\ - ); -I_CMDSTS: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_cmdsts_if - port map ( - D(48) => I_SM_n_39, - D(47) => I_SM_n_40, - D(46) => I_SM_n_41, - D(45) => I_SM_n_42, - D(44) => I_SM_n_43, - D(43) => I_SM_n_44, - D(42) => I_SM_n_45, - D(41) => I_SM_n_46, - D(40) => I_SM_n_47, - D(39) => I_SM_n_48, - D(38) => I_SM_n_49, - D(37) => I_SM_n_50, - D(36) => I_SM_n_51, - D(35) => I_SM_n_52, - D(34) => I_SM_n_53, - D(33) => I_SM_n_54, - D(32) => I_SM_n_55, - D(31) => I_SM_n_56, - D(30) => I_SM_n_57, - D(29) => I_SM_n_58, - D(28) => I_SM_n_59, - D(27) => I_SM_n_60, - D(26) => I_SM_n_61, - D(25) => I_SM_n_62, - D(24) => I_SM_n_63, - D(23) => I_SM_n_64, - D(22) => I_SM_n_65, - D(21) => I_SM_n_66, - D(20) => I_SM_n_67, - D(19) => I_SM_n_68, - D(18) => I_SM_n_69, - D(17) => I_SM_n_70, - D(16) => I_SM_n_71, - D(15) => I_SM_n_72, - D(14) => I_SM_n_73, - D(13) => I_SM_n_74, - D(12) => I_SM_n_75, - D(11) => I_SM_n_76, - D(10) => I_SM_n_77, - D(9) => I_SM_n_78, - D(8) => I_SM_n_79, - D(7) => I_SM_n_80, - D(6) => I_SM_n_81, - D(5) => I_SM_n_82, - D(4) => I_SM_n_83, - D(3) => I_SM_n_84, - D(2) => I_SM_n_85, - D(1) => I_SM_n_86, - D(0) => I_SM_n_87, - E(0) => E(0), - \FSM_sequential_dmacntrl_cs_reg[1]\ => I_CMDSTS_n_7, - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ => I_CMDSTS_n_6, - \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg\ => \^p_55_out\, - \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg_0\ => \^cmnd_wr\, - \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\ => \^p_46_out\, - \INFERRED_GEN.cnt_i_reg[1]\ => \INFERRED_GEN.cnt_i_reg[1]\, - \INFERRED_GEN.cnt_i_reg[2]\ => \INFERRED_GEN.cnt_i_reg[2]\, - \INFERRED_GEN.cnt_i_reg[2]_0\ => \INFERRED_GEN.cnt_i_reg[2]_0\, - \INFERRED_GEN.cnt_i_reg[2]_1\ => \INFERRED_GEN.cnt_i_reg[2]_1\, - \INFERRED_GEN.cnt_i_reg[2]_2\(0) => \INFERRED_GEN.cnt_i_reg[2]_2\(0), - SR(0) => SR(0), - \cmnds_queued_reg[7]\ => \^p_57_out\, - dma_decerr_reg => dma_decerr_reg, - dma_decerr_reg_0 => dma_decerr_reg_0, - dma_slverr_reg => dma_slverr_reg, - dma_slverr_reg_0 => dma_slverr_reg_0, - dmacntrl_ns14_out => dmacntrl_ns14_out, - err_i_reg_0 => I_CMDSTS_n_1, - err_i_reg_1 => \^dma_err\, - frame_sync_reg => frame_sync_reg, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - mm2s_halt => mm2s_halt, - \out\ => \out\, - p_0_in => p_0_in, - p_3_in => p_3_in, - p_68_out(1) => p_68_out(2), - p_68_out(0) => p_68_out(0), - \sig_addr_cntr_lsh_kh_reg[31]\(48 downto 0) => \sig_addr_cntr_lsh_kh_reg[31]\(48 downto 0), - zero_hsize_err => zero_hsize_err, - zero_vsize_err => zero_vsize_err - ); -I_SM: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_sm - port map ( - CO(0) => VIDEO_REG_I_n_48, - D(48) => I_SM_n_39, - D(47) => I_SM_n_40, - D(46) => I_SM_n_41, - D(45) => I_SM_n_42, - D(44) => I_SM_n_43, - D(43) => I_SM_n_44, - D(42) => I_SM_n_45, - D(41) => I_SM_n_46, - D(40) => I_SM_n_47, - D(39) => I_SM_n_48, - D(38) => I_SM_n_49, - D(37) => I_SM_n_50, - D(36) => I_SM_n_51, - D(35) => I_SM_n_52, - D(34) => I_SM_n_53, - D(33) => I_SM_n_54, - D(32) => I_SM_n_55, - D(31) => I_SM_n_56, - D(30) => I_SM_n_57, - D(29) => I_SM_n_58, - D(28) => I_SM_n_59, - D(27) => I_SM_n_60, - D(26) => I_SM_n_61, - D(25) => I_SM_n_62, - D(24) => I_SM_n_63, - D(23) => I_SM_n_64, - D(22) => I_SM_n_65, - D(21) => I_SM_n_66, - D(20) => I_SM_n_67, - D(19) => I_SM_n_68, - D(18) => I_SM_n_69, - D(17) => I_SM_n_70, - D(16) => I_SM_n_71, - D(15) => I_SM_n_72, - D(14) => I_SM_n_73, - D(13) => I_SM_n_74, - D(12) => I_SM_n_75, - D(11) => I_SM_n_76, - D(10) => I_SM_n_77, - D(9) => I_SM_n_78, - D(8) => I_SM_n_79, - D(7) => I_SM_n_80, - D(6) => I_SM_n_81, - D(5) => I_SM_n_82, - D(4) => I_SM_n_83, - D(3) => I_SM_n_84, - D(2) => I_SM_n_85, - D(1) => I_SM_n_86, - D(0) => I_SM_n_87, - DI(0) => I_SM_n_31, - \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg_0\ => \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4]\(0) => D(0), - \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0\(15 downto 0) => dm_address_reg(15 downto 0), - \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\ => \^p_46_out\, - \INFERRED_GEN.cnt_i_reg[2]\(0) => \INFERRED_GEN.cnt_i_reg[2]_2\(0), - O(3) => VIDEO_REG_I_n_36, - O(2) => VIDEO_REG_I_n_37, - O(1) => VIDEO_REG_I_n_38, - O(0) => VIDEO_REG_I_n_39, - Q(15 downto 0) => C(31 downto 16), - S(3) => I_SM_n_32, - S(2) => I_SM_n_33, - S(1) => I_SM_n_34, - S(0) => I_SM_n_35, - \cmnds_queued_reg[5]_0\(6) => \p_0_out_carry__0_n_5\, - \cmnds_queued_reg[5]_0\(5) => \p_0_out_carry__0_n_6\, - \cmnds_queued_reg[5]_0\(4) => \p_0_out_carry__0_n_7\, - \cmnds_queued_reg[5]_0\(3) => p_0_out_carry_n_4, - \cmnds_queued_reg[5]_0\(2) => p_0_out_carry_n_5, - \cmnds_queued_reg[5]_0\(1) => p_0_out_carry_n_6, - \cmnds_queued_reg[5]_0\(0) => p_0_out_carry_n_7, - \cmnds_queued_reg[7]_0\(5 downto 0) => cmnds_queued_reg(5 downto 0), - \cmnds_queued_reg[7]_1\(2) => I_SM_n_36, - \cmnds_queued_reg[7]_1\(1) => I_SM_n_37, - \cmnds_queued_reg[7]_1\(0) => I_SM_n_38, - dma_err => \^dma_err\, - dma_interr_reg => dma_interr_reg, - dma_interr_reg_0 => dma_interr_reg_0, - dmacntrl_ns14_out => dmacntrl_ns14_out, - err_i_reg => I_CMDSTS_n_6, - err_i_reg_0 => I_CMDSTS_n_7, - frame_sync_reg => frame_sync_reg, - halt_i_reg => halt_i_reg, - halt_i_reg_0(0) => halt_i_reg_0(0), - \hsize_vid_reg[15]\(15 downto 0) => crnt_hsize(15 downto 0), - interr_i_reg => I_CMDSTS_n_1, - load_new_addr => load_new_addr, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - mm2s_axi2ip_wrce(0) => mm2s_axi2ip_wrce(0), - mm2s_halt => mm2s_halt, - \out\ => \out\, - p_0_in => p_0_in, - p_0_out => p_0_out, - p_10_out => p_10_out, - p_23_out => p_23_out, - p_37_out => \^p_37_out\, - p_3_in => p_3_in, - p_57_out => \^p_57_out\, - p_68_out(1) => p_68_out(2), - p_68_out(0) => p_68_out(0), - s_axis_cmd_tvalid_reg => \^cmnd_wr\, - s_axis_cmd_tvalid_reg_0 => \^p_55_out\, - \stride_vid_reg[11]\(3) => VIDEO_REG_I_n_44, - \stride_vid_reg[11]\(2) => VIDEO_REG_I_n_45, - \stride_vid_reg[11]\(1) => VIDEO_REG_I_n_46, - \stride_vid_reg[11]\(0) => VIDEO_REG_I_n_47, - \stride_vid_reg[15]\(3) => VIDEO_REG_I_n_49, - \stride_vid_reg[15]\(2) => VIDEO_REG_I_n_50, - \stride_vid_reg[15]\(1) => VIDEO_REG_I_n_51, - \stride_vid_reg[15]\(0) => VIDEO_REG_I_n_52, - \stride_vid_reg[7]\(3) => VIDEO_REG_I_n_40, - \stride_vid_reg[7]\(2) => VIDEO_REG_I_n_41, - \stride_vid_reg[7]\(1) => VIDEO_REG_I_n_42, - \stride_vid_reg[7]\(0) => VIDEO_REG_I_n_43, - tstvect_fsync_d1 => tstvect_fsync_d1, - \vsize_vid_reg[12]\(12 downto 0) => \^q\(12 downto 0), - zero_hsize_err => zero_hsize_err, - zero_hsize_err0 => zero_hsize_err0, - zero_vsize_err => zero_vsize_err, - zero_vsize_err0 => zero_vsize_err0 - ); -I_STS_MNGR: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_sts_mngr - port map ( - \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\ => VIDEO_REG_I_n_17, - datamover_idle => datamover_idle, - \dmacr_i_reg[0]\ => \dmacr_i_reg[0]\, - halted_reg => halted_reg, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - \out\ => \out\, - p_0_in => p_0_in, - p_1_out => p_1_out, - p_36_out => p_36_out, - p_37_out => \^p_37_out\, - p_67_out => p_67_out, - p_68_out(0) => p_68_out(0) - ); -\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(0), - Q => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4]\(0), - R => p_0_in - ); -\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(1), - Q => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4]\(1), - R => p_0_in - ); -\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(2), - Q => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4]\(2), - R => p_0_in - ); -\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[3]\: unisim.vcomponents.FDRE - port map ( C => m_axi_mm2s_aclk, - CE => '1', - D => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(3), - Q => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4]\(3), - R => p_0_in - ); -\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(4), - Q => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4]\(4), - R => p_0_in + CE => \dm_address[0]_i_1_n_0\, + D => \dm_address_reg[28]_i_1_n_6\, + Q => dm_address_reg(29), + R => SR(0) ); -\MASTER_MODE_FRAME_CNT.frame_number_i[0]_i_1\: unisim.vcomponents.LUT5 +\dm_address_reg[2]\: unisim.vcomponents.FDRE generic map( - INIT => X"080808FB" + INIT => '0' ) port map ( - I0 => \ptr_ref_i_reg[4]\(0), - I1 => valid_frame_sync_d2, - I2 => p_68_out(1), - I3 => \p_6_out__0\, - I4 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(0), - O => \MASTER_MODE_FRAME_CNT.frame_number_i[0]_i_1_n_0\ + C => m_axi_mm2s_aclk, + CE => \dm_address[0]_i_1_n_0\, + D => O(2), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(2), + R => SR(0) ); -\MASTER_MODE_FRAME_CNT.frame_number_i[1]_i_1\: unisim.vcomponents.LUT6 +\dm_address_reg[30]\: unisim.vcomponents.FDRE generic map( - INIT => X"0808080808FBFB08" + INIT => '0' ) port map ( - I0 => \ptr_ref_i_reg[4]\(1), - I1 => valid_frame_sync_d2, - I2 => p_68_out(1), - I3 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(1), - I4 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(0), - I5 => \p_6_out__0\, - O => \MASTER_MODE_FRAME_CNT.frame_number_i[1]_i_1_n_0\ + C => m_axi_mm2s_aclk, + CE => \dm_address[0]_i_1_n_0\, + D => \dm_address_reg[28]_i_1_n_5\, + Q => dm_address_reg(30), + R => SR(0) ); -\MASTER_MODE_FRAME_CNT.frame_number_i[2]_i_1\: unisim.vcomponents.LUT6 +\dm_address_reg[31]\: unisim.vcomponents.FDRE generic map( - INIT => X"888888888BB8B8B8" + INIT => '0' ) port map ( - I0 => \ptr_ref_i_reg[4]\(2), - I1 => \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_5_n_0\, - I2 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(2), - I3 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(1), - I4 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(0), - I5 => \p_6_out__0\, - O => \MASTER_MODE_FRAME_CNT.frame_number_i[2]_i_1_n_0\ + C => m_axi_mm2s_aclk, + CE => \dm_address[0]_i_1_n_0\, + D => \dm_address_reg[28]_i_1_n_4\, + Q => dm_address_reg(31), + R => SR(0) ); -\MASTER_MODE_FRAME_CNT.frame_number_i[3]_i_1\: unisim.vcomponents.LUT6 +\dm_address_reg[3]\: unisim.vcomponents.FDRE generic map( - INIT => X"0808080808FBFB08" + INIT => '0' ) port map ( - I0 => \ptr_ref_i_reg[4]\(3), - I1 => valid_frame_sync_d2, - I2 => p_68_out(1), - I3 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(3), - I4 => \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_6_n_0\, - I5 => \p_6_out__0\, - O => \MASTER_MODE_FRAME_CNT.frame_number_i[3]_i_1_n_0\ + C => m_axi_mm2s_aclk, + CE => \dm_address[0]_i_1_n_0\, + D => O(3), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(3), + R => SR(0) ); -\MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_3\: unisim.vcomponents.LUT6 +\dm_address_reg[4]\: unisim.vcomponents.FDRE generic map( - INIT => X"888888888BB8B8B8" + INIT => '0' ) port map ( - I0 => \ptr_ref_i_reg[4]\(4), - I1 => \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_5_n_0\, - I2 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(4), - I3 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(3), - I4 => \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_6_n_0\, - I5 => \p_6_out__0\, - O => \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_3_n_0\ - ); -\MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000000000000002" - ) - port map ( - I0 => valid_frame_sync_d2, - I1 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(3), - I2 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(0), - I3 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(1), - I4 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(2), - I5 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(4), - O => \p_6_out__0\ + C => m_axi_mm2s_aclk, + CE => \dm_address[0]_i_1_n_0\, + D => \stride_vid_reg[7]\(0), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(4), + R => SR(0) ); -\MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_5\: unisim.vcomponents.LUT2 +\dm_address_reg[5]\: unisim.vcomponents.FDRE generic map( - INIT => X"2" + INIT => '0' ) port map ( - I0 => valid_frame_sync_d2, - I1 => p_68_out(1), - O => \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_5_n_0\ + C => m_axi_mm2s_aclk, + CE => \dm_address[0]_i_1_n_0\, + D => \stride_vid_reg[7]\(1), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(5), + R => SR(0) ); -\MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_6\: unisim.vcomponents.LUT3 +\dm_address_reg[6]\: unisim.vcomponents.FDRE generic map( - INIT => X"80" + INIT => '0' ) port map ( - I0 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(2), - I1 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(0), - I2 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(1), - O => \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_6_n_0\ + C => m_axi_mm2s_aclk, + CE => \dm_address[0]_i_1_n_0\, + D => \stride_vid_reg[7]\(2), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(6), + R => SR(0) ); -\MASTER_MODE_FRAME_CNT.frame_number_i_reg[0]\: unisim.vcomponents.FDRE +\dm_address_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => VIDEO_REG_I_n_18, - D => \MASTER_MODE_FRAME_CNT.frame_number_i[0]_i_1_n_0\, - Q => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(0), - R => prmry_resetn_i_reg(0) + CE => \dm_address[0]_i_1_n_0\, + D => \stride_vid_reg[7]\(3), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(7), + R => SR(0) ); -\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\: unisim.vcomponents.FDRE +\dm_address_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => VIDEO_REG_I_n_18, - D => \MASTER_MODE_FRAME_CNT.frame_number_i[1]_i_1_n_0\, - Q => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(1), - R => prmry_resetn_i_reg(0) + CE => \dm_address[0]_i_1_n_0\, + D => \stride_vid_reg[11]\(0), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(8), + R => SR(0) ); -\MASTER_MODE_FRAME_CNT.frame_number_i_reg[2]\: unisim.vcomponents.FDRE +\dm_address_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => VIDEO_REG_I_n_18, - D => \MASTER_MODE_FRAME_CNT.frame_number_i[2]_i_1_n_0\, - Q => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(2), - R => prmry_resetn_i_reg(0) + CE => \dm_address[0]_i_1_n_0\, + D => \stride_vid_reg[11]\(1), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(9), + R => SR(0) ); -\MASTER_MODE_FRAME_CNT.frame_number_i_reg[3]\: unisim.vcomponents.FDRE +frame_sync_d1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => VIDEO_REG_I_n_18, - D => \MASTER_MODE_FRAME_CNT.frame_number_i[3]_i_1_n_0\, - Q => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(3), - R => prmry_resetn_i_reg(0) + CE => '1', + D => p_24_out, + Q => \^tstvect_fsync_d1\, + R => SR(0) ); -\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]\: unisim.vcomponents.FDRE +frame_sync_d2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, - CE => VIDEO_REG_I_n_18, - D => \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_3_n_0\, - Q => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(4), - R => prmry_resetn_i_reg(0) - ); -\MASTER_MODE_FRAME_CNT.tstvect_fsync_reg\: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, CE => '1', - D => p_10_out, - Q => \^p_49_out\, - R => p_0_in + D => \^tstvect_fsync_d1\, + Q => \^tstvect_fsync_d2\, + R => SR(0) ); -\MASTER_MODE_FRAME_CNT.valid_frame_sync_d1_reg\: unisim.vcomponents.FDRE +frame_sync_d3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, CE => '1', - D => p_45_out, - Q => valid_frame_sync_d1, - R => p_0_in + D => \^tstvect_fsync_d2\, + Q => frame_sync_d3, + R => SR(0) ); -\MASTER_MODE_FRAME_CNT.valid_frame_sync_d2_reg\: unisim.vcomponents.FDRE +frame_sync_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => m_axi_mm2s_aclk, CE => '1', - D => valid_frame_sync_d1, - Q => valid_frame_sync_d2, - R => p_0_in - ); -VIDEO_GENLOCK_I: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_genlock_mngr - port map ( - Q(4 downto 0) => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(4 downto 0), - in0(0) => in0(0), - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - \out\ => \out\, - p_0_in => p_0_in, - p_44_out => p_44_out, - p_67_out => p_67_out, - p_68_out(0) => p_68_out(1), - valid_frame_sync_d2 => valid_frame_sync_d2 - ); -VIDEO_REG_I: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_vidreg_module - port map ( - CO(0) => VIDEO_REG_I_n_48, - E(0) => VIDEO_REG_I_n_18, - \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15]\(15 downto 0) => crnt_hsize(15 downto 0), - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(31 downto 0) => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(31 downto 0), - \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(15 downto 0) => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(15 downto 0), - O(3) => VIDEO_REG_I_n_36, - O(2) => VIDEO_REG_I_n_37, - O(1) => VIDEO_REG_I_n_38, - O(0) => VIDEO_REG_I_n_39, - Q(12 downto 0) => \^q\(12 downto 0), - all_idle_reg => VIDEO_REG_I_n_17, - \dm_address_reg[11]\(3) => VIDEO_REG_I_n_44, - \dm_address_reg[11]\(2) => VIDEO_REG_I_n_45, - \dm_address_reg[11]\(1) => VIDEO_REG_I_n_46, - \dm_address_reg[11]\(0) => VIDEO_REG_I_n_47, - \dm_address_reg[15]\(3) => VIDEO_REG_I_n_49, - \dm_address_reg[15]\(2) => VIDEO_REG_I_n_50, - \dm_address_reg[15]\(1) => VIDEO_REG_I_n_51, - \dm_address_reg[15]\(0) => VIDEO_REG_I_n_52, - \dm_address_reg[15]_0\(15 downto 0) => dm_address_reg(15 downto 0), - \dm_address_reg[31]\(15 downto 0) => C(31 downto 16), - \dm_address_reg[7]\(3) => VIDEO_REG_I_n_40, - \dm_address_reg[7]\(2) => VIDEO_REG_I_n_41, - \dm_address_reg[7]\(1) => VIDEO_REG_I_n_42, - \dm_address_reg[7]\(0) => VIDEO_REG_I_n_43, - load_new_addr => load_new_addr, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - mask_fsync_out_i => mask_fsync_out_i, - \out\ => \out\, - p_0_in => p_0_in, - p_1_out => p_1_out, - p_23_out => p_23_out, - p_2_out => p_2_out, - p_37_out => \^p_37_out\, - p_64_out => p_64_out, - p_67_out => p_67_out, - p_68_out(0) => p_68_out(1), - \p_6_out__0\ => \p_6_out__0\, - prmtr_updt_complete_i_reg => prmtr_updt_complete_i_reg, - \reg_module_hsize_reg[15]\(15 downto 0) => \reg_module_hsize_reg[15]\(15 downto 0), - \reg_module_vsize_reg[12]\(12 downto 0) => \reg_module_vsize_reg[12]\(12 downto 0), - \stride_vid_reg[0]\ => prmtr_update_complete, - \stride_vid_reg[0]_0\ => \^p_46_out\, - tstvect_fsync_d1 => tstvect_fsync_d1, - valid_frame_sync_d2 => valid_frame_sync_d2, - zero_hsize_err0 => zero_hsize_err0, - zero_vsize_err0 => zero_vsize_err0 + D => frame_sync_d3, + Q => \^frame_sync_reg\, + R => SR(0) ); -initial_frame_i_1: unisim.vcomponents.LUT4 +halted_set_i_i_1: unisim.vcomponents.LUT4 generic map( - INIT => X"00E0" + INIT => X"0080" ) port map ( - I0 => \^initial_frame\, - I1 => p_23_out, - I2 => \out\, - I3 => p_67_out, - O => initial_frame_i_1_n_0 + I0 => \^p_39_out\, + I1 => mm2s_fifo_pipe_empty, + I2 => datamover_idle, + I3 => p_71_out(0), + O => halted_set_i0 ); -initial_frame_reg: unisim.vcomponents.FDRE +\s_axis_cmd_tdata[0]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => initial_frame_i_1_n_0, - Q => \^initial_frame\, - R => '0' - ); -p_0_out_carry: unisim.vcomponents.CARRY4 - port map ( - CI => '0', - CO(3) => p_0_out_carry_n_0, - CO(2) => p_0_out_carry_n_1, - CO(1) => p_0_out_carry_n_2, - CO(0) => p_0_out_carry_n_3, - CYINIT => cmnds_queued_reg(0), - DI(3 downto 1) => cmnds_queued_reg(3 downto 1), - DI(0) => I_SM_n_31, - O(3) => p_0_out_carry_n_4, - O(2) => p_0_out_carry_n_5, - O(1) => p_0_out_carry_n_6, - O(0) => p_0_out_carry_n_7, - S(3) => I_SM_n_32, - S(2) => I_SM_n_33, - S(1) => I_SM_n_34, - S(0) => I_SM_n_35 - ); -\p_0_out_carry__0\: unisim.vcomponents.CARRY4 - port map ( - CI => p_0_out_carry_n_0, - CO(3 downto 2) => \NLW_p_0_out_carry__0_CO_UNCONNECTED\(3 downto 2), - CO(1) => \p_0_out_carry__0_n_2\, - CO(0) => \p_0_out_carry__0_n_3\, - CYINIT => '0', - DI(3 downto 2) => B"00", - DI(1 downto 0) => cmnds_queued_reg(5 downto 4), - O(3) => \NLW_p_0_out_carry__0_O_UNCONNECTED\(3), - O(2) => \p_0_out_carry__0_n_5\, - O(1) => \p_0_out_carry__0_n_6\, - O(0) => \p_0_out_carry__0_n_7\, - S(3) => '0', - S(2) => I_SM_n_36, - S(1) => I_SM_n_37, - S(0) => I_SM_n_38 - ); -stop_reg: unisim.vcomponents.FDRE - port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => stop_i, - Q => p_35_out, - R => p_0_in - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_if is - port ( - D : out STD_LOGIC_VECTOR ( 31 downto 0 ); - \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); - mm2s_introut : out STD_LOGIC; - s_axi_lite_awready : out STD_LOGIC; - s_axi_lite_wready : out STD_LOGIC; - s_axi_lite_arready : out STD_LOGIC; - s_axi_lite_bvalid : out STD_LOGIC; - s_axi_lite_rvalid : out STD_LOGIC; - \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg\ : out STD_LOGIC; - mm2s_axi2ip_wrce : out STD_LOGIC_VECTOR ( 6 downto 0 ); - \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg\ : out STD_LOGIC; - \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - in0 : out STD_LOGIC_VECTOR ( 31 downto 0 ); - prmtr_updt_complete_i_reg : out STD_LOGIC; - ioc_irq_reg : out STD_LOGIC; - dly_irq_reg : out STD_LOGIC; - s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_lite_aclk : in STD_LOGIC; - prmry_reset2 : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - p_75_out : in STD_LOGIC; - Q : in STD_LOGIC_VECTOR ( 4 downto 0 ); - \MM2S_ERR_FOR_IRQ.frm_store_i_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); - s_axi_lite_wvalid : in STD_LOGIC; - s_axi_lite_awvalid : in STD_LOGIC; - s_axi_lite_arvalid : in STD_LOGIC; - different_delay : in STD_LOGIC; - different_thresh : in STD_LOGIC; - prmry_resetn_i_reg : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[0]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[15]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[14]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[13]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[12]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[6]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[5]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[4]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[2]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[1]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[3]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[7]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[8]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[9]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[10]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[11]\ : in STD_LOGIC; - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); - s_axi_lite_resetn : in STD_LOGIC; - s_axi_lite_bready : in STD_LOGIC; - s_axi_lite_rready : in STD_LOGIC; - p_68_out : in STD_LOGIC_VECTOR ( 25 downto 0 ); - p_67_out : in STD_LOGIC; - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); - err_irq_reg : in STD_LOGIC; - dly_irq_reg_0 : in STD_LOGIC; - ioc_irq_reg_0 : in STD_LOGIC; - dma_decerr_reg : in STD_LOGIC; - dma_slverr_reg : in STD_LOGIC; - dma_interr_reg : in STD_LOGIC; - mm2s_ioc_irq_set : in STD_LOGIC; - mm2s_dly_irq_set : in STD_LOGIC; - s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 5 downto 0 ); - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 5 downto 0 ); - \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_if : entity is "axi_vdma_reg_if"; -end Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_if; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_if is - signal mm2s_chnl_current_frame_cdc_tig : STD_LOGIC_VECTOR ( 4 downto 0 ); - attribute async_reg : string; - attribute async_reg of mm2s_chnl_current_frame_cdc_tig : signal is "true"; - signal mm2s_genlock_pair_frame_cdc_tig : STD_LOGIC_VECTOR ( 4 downto 0 ); - attribute async_reg of mm2s_genlock_pair_frame_cdc_tig : signal is "true"; - signal mm2s_ip2axi_frame_ptr_ref_cdc_tig : STD_LOGIC_VECTOR ( 4 downto 0 ); - attribute async_reg of mm2s_ip2axi_frame_ptr_ref_cdc_tig : signal is "true"; - signal mm2s_ip2axi_frame_store_cdc_tig : STD_LOGIC_VECTOR ( 4 downto 0 ); - attribute async_reg of mm2s_ip2axi_frame_store_cdc_tig : signal is "true"; - signal s2mm_capture_dm_done_vsize_counter_cdc_tig : STD_LOGIC_VECTOR ( 12 downto 0 ); - attribute async_reg of s2mm_capture_dm_done_vsize_counter_cdc_tig : signal is "true"; - signal s2mm_capture_hsize_at_uf_err_cdc_tig : STD_LOGIC_VECTOR ( 15 downto 0 ); - attribute async_reg of s2mm_capture_hsize_at_uf_err_cdc_tig : signal is "true"; - signal s2mm_chnl_current_frame_cdc_tig : STD_LOGIC_VECTOR ( 4 downto 0 ); - attribute async_reg of s2mm_chnl_current_frame_cdc_tig : signal is "true"; - signal s2mm_genlock_pair_frame_cdc_tig : STD_LOGIC_VECTOR ( 4 downto 0 ); - attribute async_reg of s2mm_genlock_pair_frame_cdc_tig : signal is "true"; - signal s2mm_ip2axi_frame_ptr_ref_cdc_tig : STD_LOGIC_VECTOR ( 4 downto 0 ); - attribute async_reg of s2mm_ip2axi_frame_ptr_ref_cdc_tig : signal is "true"; - signal s2mm_ip2axi_frame_store_cdc_tig : STD_LOGIC_VECTOR ( 4 downto 0 ); - attribute async_reg of s2mm_ip2axi_frame_store_cdc_tig : signal is "true"; - attribute ASYNC_REG_boolean : boolean; - attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[0]\ : label is std.standard.true; - attribute KEEP : string; - attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[0]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[1]\ : label is std.standard.true; - attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[1]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[2]\ : label is std.standard.true; - attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[2]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[3]\ : label is std.standard.true; - attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[3]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4]\ : label is std.standard.true; - attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[0]\ : label is std.standard.true; - attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[0]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[1]\ : label is std.standard.true; - attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[1]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[2]\ : label is std.standard.true; - attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[2]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[3]\ : label is std.standard.true; - attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[3]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[4]\ : label is std.standard.true; - attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[4]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[0]\ : label is std.standard.true; - attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[0]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[1]\ : label is std.standard.true; - attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[1]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[2]\ : label is std.standard.true; - attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[2]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[3]\ : label is std.standard.true; - attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[3]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\ : label is std.standard.true; - attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[0]\ : label is std.standard.true; - attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[0]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[1]\ : label is std.standard.true; - attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[1]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[2]\ : label is std.standard.true; - attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[2]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[3]\ : label is std.standard.true; - attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[3]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\ : label is std.standard.true; - attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\ : label is "yes"; -begin -\GEN_AXI_LITE_IF.AXI_LITE_IF_I\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_lite_if - port map ( - D(31 downto 0) => D(31 downto 0), - \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg\ => \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg\, - \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[16]\ => mm2s_axi2ip_wrce(0), - \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]\(0) => \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]\(0), - \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg\ => \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg\, - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]\(7 downto 0) => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]\(7 downto 0), - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\(7 downto 0) => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\(7 downto 0), - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]_0\(31 downto 0) => \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]\(31 downto 0), - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(4 downto 0) => mm2s_ip2axi_frame_ptr_ref_cdc_tig(4 downto 0), - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\(4 downto 0) => mm2s_ip2axi_frame_store_cdc_tig(4 downto 0), - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[0]\ => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[0]\, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[10]\ => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[10]\, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[11]\ => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[11]\, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[12]\ => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[12]\, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[13]\ => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[13]\, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[14]\ => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[14]\, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[15]\ => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[15]\, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[1]\ => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[1]\, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[2]\ => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[2]\, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(15 downto 0) => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(15 downto 0), - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[3]\ => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[3]\, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[4]\ => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[4]\, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[5]\ => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[5]\, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[6]\ => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[6]\, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[7]\ => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[7]\, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[8]\ => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[8]\, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[9]\ => \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[9]\, - SR(0) => SR(0), - different_delay => different_delay, - different_thresh => different_thresh, - dly_irq_reg => dly_irq_reg, - dly_irq_reg_0 => dly_irq_reg_0, - dma_decerr_reg => dma_decerr_reg, - dma_interr_reg => dma_interr_reg, - dma_slverr_reg => dma_slverr_reg, - err_irq_reg => err_irq_reg, - in0(31 downto 0) => in0(31 downto 0), - ioc_irq_reg => ioc_irq_reg, - ioc_irq_reg_0 => ioc_irq_reg_0, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - mm2s_axi2ip_wrce(5 downto 0) => mm2s_axi2ip_wrce(6 downto 1), - mm2s_dly_irq_set => mm2s_dly_irq_set, - mm2s_ioc_irq_set => mm2s_ioc_irq_set, - \out\(1 downto 0) => \out\(1 downto 0), - p_67_out => p_67_out, - p_68_out(25 downto 0) => p_68_out(25 downto 0), - prmry_reset2 => prmry_reset2, - prmry_resetn_i_reg => prmry_resetn_i_reg, - prmtr_updt_complete_i_reg => prmtr_updt_complete_i_reg, - s_axi_lite_aclk => s_axi_lite_aclk, - s_axi_lite_araddr(5 downto 0) => s_axi_lite_araddr(5 downto 0), - s_axi_lite_arready => s_axi_lite_arready, - s_axi_lite_arvalid => s_axi_lite_arvalid, - s_axi_lite_awaddr(5 downto 0) => s_axi_lite_awaddr(5 downto 0), - s_axi_lite_awready => s_axi_lite_awready, - s_axi_lite_awvalid => s_axi_lite_awvalid, - s_axi_lite_bready => s_axi_lite_bready, - s_axi_lite_bvalid => s_axi_lite_bvalid, - s_axi_lite_rdata(31 downto 0) => s_axi_lite_rdata(31 downto 0), - s_axi_lite_resetn => s_axi_lite_resetn, - s_axi_lite_rready => s_axi_lite_rready, - s_axi_lite_rvalid => s_axi_lite_rvalid, - s_axi_lite_wdata(31 downto 0) => s_axi_lite_wdata(31 downto 0), - s_axi_lite_wready => s_axi_lite_wready, - s_axi_lite_wvalid => s_axi_lite_wvalid + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[0]\, + O => D(0) ); -\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.MM2S_INTRPT_CROSSING_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized7\ - port map ( - SR(0) => SR(0), - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - mm2s_introut => mm2s_introut, - p_75_out => p_75_out, - prmry_reset2 => prmry_reset2, - s_axi_lite_aclk => s_axi_lite_aclk +\s_axis_cmd_tdata[10]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[10]\, + O => D(10) ); -\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[0]\: unisim.vcomponents.FDRE +\s_axis_cmd_tdata[11]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]\(0), - Q => mm2s_chnl_current_frame_cdc_tig(0), - R => '0' + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[11]\, + O => D(11) ); -\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[1]\: unisim.vcomponents.FDRE +\s_axis_cmd_tdata[12]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]\(1), - Q => mm2s_chnl_current_frame_cdc_tig(1), - R => '0' + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[12]\, + O => D(12) ); -\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[2]\: unisim.vcomponents.FDRE +\s_axis_cmd_tdata[13]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]\(2), - Q => mm2s_chnl_current_frame_cdc_tig(2), - R => '0' + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[13]\, + O => D(13) ); -\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[3]\: unisim.vcomponents.FDRE +\s_axis_cmd_tdata[14]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]\(3), - Q => mm2s_chnl_current_frame_cdc_tig(3), - R => '0' + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[14]\, + O => D(14) ); -\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4]\: unisim.vcomponents.FDRE +\s_axis_cmd_tdata[15]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]\(4), - Q => mm2s_chnl_current_frame_cdc_tig(4), - R => '0' + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[15]\, + O => D(15) ); -\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[0]\: unisim.vcomponents.FDRE +\s_axis_cmd_tdata[1]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => '0', - Q => mm2s_genlock_pair_frame_cdc_tig(0), - R => '0' + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[1]\, + O => D(1) ); -\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[1]\: unisim.vcomponents.FDRE +\s_axis_cmd_tdata[23]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => '0', - Q => mm2s_genlock_pair_frame_cdc_tig(1), - R => '0' + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[23]\, + O => D(16) ); -\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[2]\: unisim.vcomponents.FDRE +\s_axis_cmd_tdata[2]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => '0', - Q => mm2s_genlock_pair_frame_cdc_tig(2), - R => '0' + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[2]\, + O => D(2) ); -\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[3]\: unisim.vcomponents.FDRE +\s_axis_cmd_tdata[32]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => '0', - Q => mm2s_genlock_pair_frame_cdc_tig(3), - R => '0' + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[32]\, + O => D(17) ); -\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[4]\: unisim.vcomponents.FDRE +\s_axis_cmd_tdata[33]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => '0', - Q => mm2s_genlock_pair_frame_cdc_tig(4), - R => '0' + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[33]\, + O => D(18) ); -\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[0]\: unisim.vcomponents.FDRE +\s_axis_cmd_tdata[34]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => Q(0), - Q => mm2s_ip2axi_frame_ptr_ref_cdc_tig(0), - R => '0' + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[34]\, + O => D(19) ); -\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[1]\: unisim.vcomponents.FDRE +\s_axis_cmd_tdata[35]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => Q(1), - Q => mm2s_ip2axi_frame_ptr_ref_cdc_tig(1), - R => '0' + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[35]\, + O => D(20) ); -\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[2]\: unisim.vcomponents.FDRE +\s_axis_cmd_tdata[36]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => Q(2), - Q => mm2s_ip2axi_frame_ptr_ref_cdc_tig(2), - R => '0' + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[36]\, + O => D(21) ); -\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[3]\: unisim.vcomponents.FDRE +\s_axis_cmd_tdata[37]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => Q(3), - Q => mm2s_ip2axi_frame_ptr_ref_cdc_tig(3), - R => '0' + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[37]\, + O => D(22) ); -\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\: unisim.vcomponents.FDRE +\s_axis_cmd_tdata[38]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => Q(4), - Q => mm2s_ip2axi_frame_ptr_ref_cdc_tig(4), - R => '0' + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[38]\, + O => D(23) ); -\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[0]\: unisim.vcomponents.FDRE +\s_axis_cmd_tdata[39]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => \MM2S_ERR_FOR_IRQ.frm_store_i_reg[4]\(0), - Q => mm2s_ip2axi_frame_store_cdc_tig(0), - R => '0' + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[39]\, + O => D(24) ); -\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[1]\: unisim.vcomponents.FDRE +\s_axis_cmd_tdata[3]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => \MM2S_ERR_FOR_IRQ.frm_store_i_reg[4]\(1), - Q => mm2s_ip2axi_frame_store_cdc_tig(1), - R => '0' + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[3]\, + O => D(3) ); -\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[2]\: unisim.vcomponents.FDRE +\s_axis_cmd_tdata[40]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => \MM2S_ERR_FOR_IRQ.frm_store_i_reg[4]\(2), - Q => mm2s_ip2axi_frame_store_cdc_tig(2), - R => '0' + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[40]\, + O => D(25) ); -\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[3]\: unisim.vcomponents.FDRE +\s_axis_cmd_tdata[41]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => \MM2S_ERR_FOR_IRQ.frm_store_i_reg[4]\(3), - Q => mm2s_ip2axi_frame_store_cdc_tig(3), - R => '0' + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[41]\, + O => D(26) ); -\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\: unisim.vcomponents.FDRE +\s_axis_cmd_tdata[42]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => s_axi_lite_aclk, - CE => '1', - D => \MM2S_ERR_FOR_IRQ.frm_store_i_reg[4]\(4), - Q => mm2s_ip2axi_frame_store_cdc_tig(4), - R => '0' + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[42]\, + O => D(27) ); -i_0: unisim.vcomponents.LUT1 +\s_axis_cmd_tdata[43]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"8" ) port map ( - I0 => '0', - O => s2mm_ip2axi_frame_ptr_ref_cdc_tig(4) + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[43]\, + O => D(28) ); -i_1: unisim.vcomponents.LUT1 +\s_axis_cmd_tdata[44]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"8" ) port map ( - I0 => '0', - O => s2mm_ip2axi_frame_ptr_ref_cdc_tig(3) + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[44]\, + O => D(29) ); -i_10: unisim.vcomponents.LUT1 +\s_axis_cmd_tdata[45]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"8" ) port map ( - I0 => '0', - O => s2mm_chnl_current_frame_cdc_tig(4) + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[45]\, + O => D(30) ); -i_11: unisim.vcomponents.LUT1 +\s_axis_cmd_tdata[46]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"8" ) port map ( - I0 => '0', - O => s2mm_chnl_current_frame_cdc_tig(3) + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[46]\, + O => D(31) ); -i_12: unisim.vcomponents.LUT1 +\s_axis_cmd_tdata[47]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"8" ) port map ( - I0 => '0', - O => s2mm_chnl_current_frame_cdc_tig(2) + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[47]\, + O => D(32) ); -i_13: unisim.vcomponents.LUT1 +\s_axis_cmd_tdata[48]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"8" ) port map ( - I0 => '0', - O => s2mm_chnl_current_frame_cdc_tig(1) + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[48]\, + O => D(33) ); -i_14: unisim.vcomponents.LUT1 +\s_axis_cmd_tdata[49]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"8" ) port map ( - I0 => '0', - O => s2mm_chnl_current_frame_cdc_tig(0) + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[49]\, + O => D(34) ); -i_15: unisim.vcomponents.LUT1 +\s_axis_cmd_tdata[4]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"8" ) port map ( - I0 => '0', - O => s2mm_genlock_pair_frame_cdc_tig(4) + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[4]\, + O => D(4) ); -i_16: unisim.vcomponents.LUT1 +\s_axis_cmd_tdata[50]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"8" ) port map ( - I0 => '0', - O => s2mm_genlock_pair_frame_cdc_tig(3) + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[50]\, + O => D(35) ); -i_17: unisim.vcomponents.LUT1 +\s_axis_cmd_tdata[51]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"8" ) port map ( - I0 => '0', - O => s2mm_genlock_pair_frame_cdc_tig(2) + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[51]\, + O => D(36) ); -i_18: unisim.vcomponents.LUT1 +\s_axis_cmd_tdata[52]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"8" ) port map ( - I0 => '0', - O => s2mm_genlock_pair_frame_cdc_tig(1) + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[52]\, + O => D(37) ); -i_19: unisim.vcomponents.LUT1 +\s_axis_cmd_tdata[53]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"8" ) port map ( - I0 => '0', - O => s2mm_genlock_pair_frame_cdc_tig(0) + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[53]\, + O => D(38) ); -i_2: unisim.vcomponents.LUT1 +\s_axis_cmd_tdata[54]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"8" ) port map ( - I0 => '0', - O => s2mm_ip2axi_frame_ptr_ref_cdc_tig(2) + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[54]\, + O => D(39) ); -i_20: unisim.vcomponents.LUT1 +\s_axis_cmd_tdata[55]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"8" ) port map ( - I0 => '0', - O => s2mm_capture_hsize_at_uf_err_cdc_tig(15) + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[55]\, + O => D(40) ); -i_21: unisim.vcomponents.LUT1 +\s_axis_cmd_tdata[56]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"8" ) port map ( - I0 => '0', - O => s2mm_capture_hsize_at_uf_err_cdc_tig(14) + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[56]\, + O => D(41) ); -i_22: unisim.vcomponents.LUT1 +\s_axis_cmd_tdata[57]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"8" ) port map ( - I0 => '0', - O => s2mm_capture_hsize_at_uf_err_cdc_tig(13) + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[57]\, + O => D(42) ); -i_23: unisim.vcomponents.LUT1 +\s_axis_cmd_tdata[58]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"8" ) port map ( - I0 => '0', - O => s2mm_capture_hsize_at_uf_err_cdc_tig(12) + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[58]\, + O => D(43) ); -i_24: unisim.vcomponents.LUT1 +\s_axis_cmd_tdata[59]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"8" ) port map ( - I0 => '0', - O => s2mm_capture_hsize_at_uf_err_cdc_tig(11) + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[59]\, + O => D(44) ); -i_25: unisim.vcomponents.LUT1 +\s_axis_cmd_tdata[5]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"8" ) port map ( - I0 => '0', - O => s2mm_capture_hsize_at_uf_err_cdc_tig(10) + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[5]\, + O => D(5) ); -i_26: unisim.vcomponents.LUT1 +\s_axis_cmd_tdata[60]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"8" ) port map ( - I0 => '0', - O => s2mm_capture_hsize_at_uf_err_cdc_tig(9) + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[60]\, + O => D(45) ); -i_27: unisim.vcomponents.LUT1 +\s_axis_cmd_tdata[61]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"8" ) port map ( - I0 => '0', - O => s2mm_capture_hsize_at_uf_err_cdc_tig(8) + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[61]\, + O => D(46) ); -i_28: unisim.vcomponents.LUT1 +\s_axis_cmd_tdata[62]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"8" ) port map ( - I0 => '0', - O => s2mm_capture_hsize_at_uf_err_cdc_tig(7) + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[62]\, + O => D(47) ); -i_29: unisim.vcomponents.LUT1 +\s_axis_cmd_tdata[63]_i_3\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"8" ) port map ( - I0 => '0', - O => s2mm_capture_hsize_at_uf_err_cdc_tig(6) + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[63]\, + O => D(48) ); -i_3: unisim.vcomponents.LUT1 +\s_axis_cmd_tdata[6]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"8" ) port map ( - I0 => '0', - O => s2mm_ip2axi_frame_ptr_ref_cdc_tig(1) + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[6]\, + O => D(6) ); -i_30: unisim.vcomponents.LUT1 +\s_axis_cmd_tdata[7]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"8" ) port map ( - I0 => '0', - O => s2mm_capture_hsize_at_uf_err_cdc_tig(5) + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[7]\, + O => D(7) ); -i_31: unisim.vcomponents.LUT1 +\s_axis_cmd_tdata[8]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"8" ) port map ( - I0 => '0', - O => s2mm_capture_hsize_at_uf_err_cdc_tig(4) + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[8]\, + O => D(8) ); -i_32: unisim.vcomponents.LUT1 +\s_axis_cmd_tdata[9]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"2" + INIT => X"8" ) port map ( - I0 => '0', - O => s2mm_capture_hsize_at_uf_err_cdc_tig(3) + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[9]\, + O => D(9) ); -i_33: unisim.vcomponents.LUT1 +\vert_count[0]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"2" + INIT => X"FFFFFFFF00080000" ) port map ( - I0 => '0', - O => s2mm_capture_hsize_at_uf_err_cdc_tig(2) + I0 => dmacntrl_cs(1), + I1 => dmacntrl_cs(0), + I2 => dmacntrl_cs(2), + I3 => s_axis_cmd_tvalid_reg_0, + I4 => p_1_in, + I5 => \^load_new_addr\, + O => \vert_count[0]_i_1_n_0\ ); -i_34: unisim.vcomponents.LUT1 +\vert_count[0]_i_10\: unisim.vcomponents.LUT3 generic map( - INIT => X"2" + INIT => X"C5" ) port map ( - I0 => '0', - O => s2mm_capture_hsize_at_uf_err_cdc_tig(1) + I0 => vert_count_reg(1), + I1 => Q(1), + I2 => \^load_new_addr\, + O => \vert_count[0]_i_10_n_0\ ); -i_35: unisim.vcomponents.LUT1 +\vert_count[0]_i_11\: unisim.vcomponents.LUT3 generic map( - INIT => X"2" + INIT => X"C5" ) port map ( - I0 => '0', - O => s2mm_capture_hsize_at_uf_err_cdc_tig(0) + I0 => vert_count_reg(0), + I1 => Q(0), + I2 => \^load_new_addr\, + O => \vert_count[0]_i_11_n_0\ ); -i_36: unisim.vcomponents.LUT1 +\vert_count[0]_i_3\: unisim.vcomponents.LUT4 generic map( - INIT => X"2" + INIT => X"1000" ) port map ( - I0 => '0', - O => s2mm_capture_dm_done_vsize_counter_cdc_tig(12) + I0 => dmacntrl_cs(0), + I1 => dmacntrl_cs(2), + I2 => dmacntrl_cs(1), + I3 => \FSM_sequential_dmacntrl_cs[1]_i_3_n_0\, + O => \^load_new_addr\ ); -i_37: unisim.vcomponents.LUT1 +\vert_count[0]_i_4\: unisim.vcomponents.LUT1 generic map( - INIT => X"2" + INIT => X"1" ) port map ( - I0 => '0', - O => s2mm_capture_dm_done_vsize_counter_cdc_tig(11) + I0 => \^load_new_addr\, + O => \vert_count[0]_i_4_n_0\ ); -i_38: unisim.vcomponents.LUT1 +\vert_count[0]_i_5\: unisim.vcomponents.LUT1 generic map( - INIT => X"2" + INIT => X"1" ) port map ( - I0 => '0', - O => s2mm_capture_dm_done_vsize_counter_cdc_tig(10) + I0 => \^load_new_addr\, + O => \vert_count[0]_i_5_n_0\ ); -i_39: unisim.vcomponents.LUT1 +\vert_count[0]_i_6\: unisim.vcomponents.LUT1 generic map( - INIT => X"2" + INIT => X"1" ) port map ( - I0 => '0', - O => s2mm_capture_dm_done_vsize_counter_cdc_tig(9) + I0 => \^load_new_addr\, + O => \vert_count[0]_i_6_n_0\ ); -i_4: unisim.vcomponents.LUT1 +\vert_count[0]_i_7\: unisim.vcomponents.LUT1 generic map( - INIT => X"2" + INIT => X"1" ) port map ( - I0 => '0', - O => s2mm_ip2axi_frame_ptr_ref_cdc_tig(0) + I0 => \^load_new_addr\, + O => \vert_count[0]_i_7_n_0\ ); -i_40: unisim.vcomponents.LUT1 +\vert_count[0]_i_8\: unisim.vcomponents.LUT3 generic map( - INIT => X"2" + INIT => X"C5" ) port map ( - I0 => '0', - O => s2mm_capture_dm_done_vsize_counter_cdc_tig(8) + I0 => vert_count_reg(3), + I1 => Q(3), + I2 => \^load_new_addr\, + O => \vert_count[0]_i_8_n_0\ ); -i_41: unisim.vcomponents.LUT1 +\vert_count[0]_i_9\: unisim.vcomponents.LUT3 generic map( - INIT => X"2" + INIT => X"C5" ) port map ( - I0 => '0', - O => s2mm_capture_dm_done_vsize_counter_cdc_tig(7) + I0 => vert_count_reg(2), + I1 => Q(2), + I2 => \^load_new_addr\, + O => \vert_count[0]_i_9_n_0\ ); -i_42: unisim.vcomponents.LUT1 +\vert_count[12]_i_2\: unisim.vcomponents.LUT3 generic map( - INIT => X"2" + INIT => X"A3" ) port map ( - I0 => '0', - O => s2mm_capture_dm_done_vsize_counter_cdc_tig(6) + I0 => Q(12), + I1 => vert_count_reg(12), + I2 => \^load_new_addr\, + O => \vert_count[12]_i_2_n_0\ ); -i_43: unisim.vcomponents.LUT1 +\vert_count[4]_i_2\: unisim.vcomponents.LUT1 generic map( - INIT => X"2" + INIT => X"1" ) port map ( - I0 => '0', - O => s2mm_capture_dm_done_vsize_counter_cdc_tig(5) + I0 => \^load_new_addr\, + O => \vert_count[4]_i_2_n_0\ ); -i_44: unisim.vcomponents.LUT1 +\vert_count[4]_i_3\: unisim.vcomponents.LUT1 generic map( - INIT => X"2" + INIT => X"1" ) port map ( - I0 => '0', - O => s2mm_capture_dm_done_vsize_counter_cdc_tig(4) + I0 => \^load_new_addr\, + O => \vert_count[4]_i_3_n_0\ ); -i_45: unisim.vcomponents.LUT1 +\vert_count[4]_i_4\: unisim.vcomponents.LUT1 generic map( - INIT => X"2" + INIT => X"1" ) port map ( - I0 => '0', - O => s2mm_capture_dm_done_vsize_counter_cdc_tig(3) + I0 => \^load_new_addr\, + O => \vert_count[4]_i_4_n_0\ ); -i_46: unisim.vcomponents.LUT1 +\vert_count[4]_i_5\: unisim.vcomponents.LUT1 generic map( - INIT => X"2" + INIT => X"1" ) port map ( - I0 => '0', - O => s2mm_capture_dm_done_vsize_counter_cdc_tig(2) + I0 => \^load_new_addr\, + O => \vert_count[4]_i_5_n_0\ ); -i_47: unisim.vcomponents.LUT1 +\vert_count[4]_i_6\: unisim.vcomponents.LUT3 generic map( - INIT => X"2" + INIT => X"C5" ) port map ( - I0 => '0', - O => s2mm_capture_dm_done_vsize_counter_cdc_tig(1) + I0 => vert_count_reg(7), + I1 => Q(7), + I2 => \^load_new_addr\, + O => \vert_count[4]_i_6_n_0\ ); -i_48: unisim.vcomponents.LUT1 +\vert_count[4]_i_7\: unisim.vcomponents.LUT3 generic map( - INIT => X"2" + INIT => X"C5" ) port map ( - I0 => '0', - O => s2mm_capture_dm_done_vsize_counter_cdc_tig(0) + I0 => vert_count_reg(6), + I1 => Q(6), + I2 => \^load_new_addr\, + O => \vert_count[4]_i_7_n_0\ ); -i_5: unisim.vcomponents.LUT1 +\vert_count[4]_i_8\: unisim.vcomponents.LUT3 generic map( - INIT => X"2" + INIT => X"C5" ) port map ( - I0 => '0', - O => s2mm_ip2axi_frame_store_cdc_tig(4) + I0 => vert_count_reg(5), + I1 => Q(5), + I2 => \^load_new_addr\, + O => \vert_count[4]_i_8_n_0\ ); -i_6: unisim.vcomponents.LUT1 +\vert_count[4]_i_9\: unisim.vcomponents.LUT3 generic map( - INIT => X"2" + INIT => X"C5" ) port map ( - I0 => '0', - O => s2mm_ip2axi_frame_store_cdc_tig(3) + I0 => vert_count_reg(4), + I1 => Q(4), + I2 => \^load_new_addr\, + O => \vert_count[4]_i_9_n_0\ ); -i_7: unisim.vcomponents.LUT1 +\vert_count[8]_i_2\: unisim.vcomponents.LUT1 generic map( - INIT => X"2" + INIT => X"1" ) port map ( - I0 => '0', - O => s2mm_ip2axi_frame_store_cdc_tig(2) + I0 => \^load_new_addr\, + O => \vert_count[8]_i_2_n_0\ ); -i_8: unisim.vcomponents.LUT1 +\vert_count[8]_i_3\: unisim.vcomponents.LUT1 generic map( - INIT => X"2" + INIT => X"1" ) port map ( - I0 => '0', - O => s2mm_ip2axi_frame_store_cdc_tig(1) + I0 => \^load_new_addr\, + O => \vert_count[8]_i_3_n_0\ ); -i_9: unisim.vcomponents.LUT1 +\vert_count[8]_i_4\: unisim.vcomponents.LUT1 generic map( - INIT => X"2" + INIT => X"1" ) port map ( - I0 => '0', - O => s2mm_ip2axi_frame_store_cdc_tig(0) + I0 => \^load_new_addr\, + O => \vert_count[8]_i_4_n_0\ ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_rst_module is - port ( - \out\ : out STD_LOGIC; - \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ : out STD_LOGIC; - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : out STD_LOGIC; - prmry_in : out STD_LOGIC; - mm2s_halt : out STD_LOGIC; - halt_reset : out STD_LOGIC; - prmry_reset2 : out STD_LOGIC; - \fifo_wren__0\ : out STD_LOGIC; - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - p_8_out : out STD_LOGIC; - SR : out STD_LOGIC_VECTOR ( 0 to 0 ); - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - \GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - \dmacr_i_reg[2]\ : out STD_LOGIC; - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ : out STD_LOGIC; - \cmnds_queued_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - reset_counts_reg : out STD_LOGIC; - sig_s_h_halt_reg_reg : out STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - s_axi_lite_aclk : in STD_LOGIC; - m_axis_mm2s_aclk : in STD_LOGIC; - p_68_out : in STD_LOGIC_VECTOR ( 1 downto 0 ); - s_soft_reset_i0 : in STD_LOGIC; - axi_resetn : in STD_LOGIC; - dm2linebuf_mm2s_tvalid : in STD_LOGIC; - fifo_full_i : in STD_LOGIC; - p_23_out : in STD_LOGIC; - p_35_out : in STD_LOGIC; - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : in STD_LOGIC; - p_15_out : in STD_LOGIC; - mm2s_halt_cmplt : in STD_LOGIC; - mm2s_axi2ip_wrce : in STD_LOGIC_VECTOR ( 0 to 0 ); - D : in STD_LOGIC_VECTOR ( 0 to 0 ); - DIN : in STD_LOGIC_VECTOR ( 0 to 0 ); - dma_err : in STD_LOGIC; - reset_counts : in STD_LOGIC; - sig_rst2all_stop_request : in STD_LOGIC; - \FSM_sequential_dmacntrl_cs_reg[1]\ : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_rst_module : entity is "axi_vdma_rst_module"; -end Arty_Z7_20_axi_vdma_0_0_axi_vdma_rst_module; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_rst_module is - signal \^prmry_in\ : STD_LOGIC; - signal sig_mm2s_axis_resetn : STD_LOGIC; - attribute RTL_KEEP : string; - attribute RTL_KEEP of sig_mm2s_axis_resetn : signal is "true"; - attribute equivalent_register_removal : string; - attribute equivalent_register_removal of sig_mm2s_axis_resetn : signal is "no"; - signal sig_mm2s_dm_prmry_resetn : STD_LOGIC; - attribute RTL_KEEP of sig_mm2s_dm_prmry_resetn : signal is "true"; - attribute equivalent_register_removal of sig_mm2s_dm_prmry_resetn : signal is "no"; - signal sig_mm2s_prmry_resetn : STD_LOGIC; - attribute RTL_KEEP of sig_mm2s_prmry_resetn : signal is "true"; - attribute equivalent_register_removal of sig_mm2s_prmry_resetn : signal is "no"; -begin - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ <= sig_mm2s_axis_resetn; - \out\ <= sig_mm2s_prmry_resetn; - prmry_in <= \^prmry_in\; - \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ <= sig_mm2s_dm_prmry_resetn; -\GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out[5]_i_1\: unisim.vcomponents.LUT1 +\vert_count[8]_i_5\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( - I0 => sig_mm2s_axis_resetn, - O => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_0\(0) + I0 => \^load_new_addr\, + O => \vert_count[8]_i_5_n_0\ ); -\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_1\: unisim.vcomponents.LUT1 +\vert_count[8]_i_6\: unisim.vcomponents.LUT3 generic map( - INIT => X"1" + INIT => X"C5" ) port map ( - I0 => sig_mm2s_prmry_resetn, - O => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0]\(0) + I0 => vert_count_reg(11), + I1 => Q(11), + I2 => \^load_new_addr\, + O => \vert_count[8]_i_6_n_0\ ); -\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_1\: unisim.vcomponents.LUT3 +\vert_count[8]_i_7\: unisim.vcomponents.LUT3 generic map( - INIT => X"0D" + INIT => X"C5" ) port map ( - I0 => sig_mm2s_axis_resetn, - I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\, - I2 => p_15_out, - O => \GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]\(0) + I0 => vert_count_reg(10), + I1 => Q(10), + I2 => \^load_new_addr\, + O => \vert_count[8]_i_7_n_0\ ); -\GEN_RESET_FOR_MM2S.RESET_I\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_reset - port map ( - D(0) => D(0), - DIN(0) => DIN(0), - \FSM_sequential_dmacntrl_cs_reg[1]\ => \FSM_sequential_dmacntrl_cs_reg[1]\, - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ => mm2s_halt, - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\, - \cmnds_queued_reg[7]\(0) => \cmnds_queued_reg[7]\(0), - dm2linebuf_mm2s_tvalid => dm2linebuf_mm2s_tvalid, - dma_err => dma_err, - \dmacr_i_reg[2]\ => \dmacr_i_reg[2]\, - fifo_full_i => fifo_full_i, - \fifo_wren__0\ => \fifo_wren__0\, - halt_i_reg_0 => halt_reset, - in0 => sig_mm2s_prmry_resetn, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axis_mm2s_aclk => m_axis_mm2s_aclk, - mm2s_axi2ip_wrce(0) => mm2s_axi2ip_wrce(0), - mm2s_halt_cmplt => mm2s_halt_cmplt, - \out\ => sig_mm2s_prmry_resetn, - p_23_out => p_23_out, - p_35_out => p_35_out, - p_68_out(1 downto 0) => p_68_out(1 downto 0), - p_8_out => p_8_out, - prmry_in => \^prmry_in\, - prmry_reset2 => prmry_reset2, - reset_counts => reset_counts, - reset_counts_reg => reset_counts_reg, - s_axi_lite_aclk => s_axi_lite_aclk, - s_soft_reset_i0 => s_soft_reset_i0, - scndry_out => sig_mm2s_axis_resetn, - sig_mm2s_dm_prmry_resetn => sig_mm2s_dm_prmry_resetn, - sig_rst2all_stop_request => sig_rst2all_stop_request, - sig_s_h_halt_reg_reg => sig_s_h_halt_reg_reg +\vert_count[8]_i_8\: unisim.vcomponents.LUT3 + generic map( + INIT => X"C5" + ) + port map ( + I0 => vert_count_reg(9), + I1 => Q(9), + I2 => \^load_new_addr\, + O => \vert_count[8]_i_8_n_0\ ); -awready_out_i_i_1: unisim.vcomponents.LUT1 +\vert_count[8]_i_9\: unisim.vcomponents.LUT3 generic map( - INIT => X"1" + INIT => X"C5" ) port map ( - I0 => \^prmry_in\, - O => SR(0) + I0 => vert_count_reg(8), + I1 => Q(8), + I2 => \^load_new_addr\, + O => \vert_count[8]_i_9_n_0\ ); -hrd_resetn_i_reg: unisim.vcomponents.FDRE +\vert_count_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => '1' + INIT => '0' ) port map ( - C => s_axi_lite_aclk, + C => m_axi_mm2s_aclk, + CE => \vert_count[0]_i_1_n_0\, + D => \vert_count_reg[0]_i_2_n_7\, + Q => vert_count_reg(0), + R => SR(0) + ); +\vert_count_reg[0]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \vert_count_reg[0]_i_2_n_0\, + CO(2) => \vert_count_reg[0]_i_2_n_1\, + CO(1) => \vert_count_reg[0]_i_2_n_2\, + CO(0) => \vert_count_reg[0]_i_2_n_3\, + CYINIT => '0', + DI(3) => \vert_count[0]_i_4_n_0\, + DI(2) => \vert_count[0]_i_5_n_0\, + DI(1) => \vert_count[0]_i_6_n_0\, + DI(0) => \vert_count[0]_i_7_n_0\, + O(3) => \vert_count_reg[0]_i_2_n_4\, + O(2) => \vert_count_reg[0]_i_2_n_5\, + O(1) => \vert_count_reg[0]_i_2_n_6\, + O(0) => \vert_count_reg[0]_i_2_n_7\, + S(3) => \vert_count[0]_i_8_n_0\, + S(2) => \vert_count[0]_i_9_n_0\, + S(1) => \vert_count[0]_i_10_n_0\, + S(0) => \vert_count[0]_i_11_n_0\ + ); +\vert_count_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => \vert_count[0]_i_1_n_0\, + D => \vert_count_reg[8]_i_1_n_5\, + Q => vert_count_reg(10), + R => SR(0) + ); +\vert_count_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => \vert_count[0]_i_1_n_0\, + D => \vert_count_reg[8]_i_1_n_4\, + Q => vert_count_reg(11), + R => SR(0) + ); +\vert_count_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => \vert_count[0]_i_1_n_0\, + D => \vert_count_reg[12]_i_1_n_7\, + Q => vert_count_reg(12), + R => SR(0) + ); +\vert_count_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \vert_count_reg[8]_i_1_n_0\, + CO(3 downto 0) => \NLW_vert_count_reg[12]_i_1_CO_UNCONNECTED\(3 downto 0), + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 1) => \NLW_vert_count_reg[12]_i_1_O_UNCONNECTED\(3 downto 1), + O(0) => \vert_count_reg[12]_i_1_n_7\, + S(3 downto 1) => B"000", + S(0) => \vert_count[12]_i_2_n_0\ + ); +\vert_count_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => \vert_count[0]_i_1_n_0\, + D => \vert_count_reg[0]_i_2_n_6\, + Q => vert_count_reg(1), + R => SR(0) + ); +\vert_count_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => \vert_count[0]_i_1_n_0\, + D => \vert_count_reg[0]_i_2_n_5\, + Q => vert_count_reg(2), + R => SR(0) + ); +\vert_count_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => \vert_count[0]_i_1_n_0\, + D => \vert_count_reg[0]_i_2_n_4\, + Q => vert_count_reg(3), + R => SR(0) + ); +\vert_count_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => \vert_count[0]_i_1_n_0\, + D => \vert_count_reg[4]_i_1_n_7\, + Q => vert_count_reg(4), + R => SR(0) + ); +\vert_count_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \vert_count_reg[0]_i_2_n_0\, + CO(3) => \vert_count_reg[4]_i_1_n_0\, + CO(2) => \vert_count_reg[4]_i_1_n_1\, + CO(1) => \vert_count_reg[4]_i_1_n_2\, + CO(0) => \vert_count_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3) => \vert_count[4]_i_2_n_0\, + DI(2) => \vert_count[4]_i_3_n_0\, + DI(1) => \vert_count[4]_i_4_n_0\, + DI(0) => \vert_count[4]_i_5_n_0\, + O(3) => \vert_count_reg[4]_i_1_n_4\, + O(2) => \vert_count_reg[4]_i_1_n_5\, + O(1) => \vert_count_reg[4]_i_1_n_6\, + O(0) => \vert_count_reg[4]_i_1_n_7\, + S(3) => \vert_count[4]_i_6_n_0\, + S(2) => \vert_count[4]_i_7_n_0\, + S(1) => \vert_count[4]_i_8_n_0\, + S(0) => \vert_count[4]_i_9_n_0\ + ); +\vert_count_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => \vert_count[0]_i_1_n_0\, + D => \vert_count_reg[4]_i_1_n_6\, + Q => vert_count_reg(5), + R => SR(0) + ); +\vert_count_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => \vert_count[0]_i_1_n_0\, + D => \vert_count_reg[4]_i_1_n_5\, + Q => vert_count_reg(6), + R => SR(0) + ); +\vert_count_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => \vert_count[0]_i_1_n_0\, + D => \vert_count_reg[4]_i_1_n_4\, + Q => vert_count_reg(7), + R => SR(0) + ); +\vert_count_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => \vert_count[0]_i_1_n_0\, + D => \vert_count_reg[8]_i_1_n_7\, + Q => vert_count_reg(8), + R => SR(0) + ); +\vert_count_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \vert_count_reg[4]_i_1_n_0\, + CO(3) => \vert_count_reg[8]_i_1_n_0\, + CO(2) => \vert_count_reg[8]_i_1_n_1\, + CO(1) => \vert_count_reg[8]_i_1_n_2\, + CO(0) => \vert_count_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3) => \vert_count[8]_i_2_n_0\, + DI(2) => \vert_count[8]_i_3_n_0\, + DI(1) => \vert_count[8]_i_4_n_0\, + DI(0) => \vert_count[8]_i_5_n_0\, + O(3) => \vert_count_reg[8]_i_1_n_4\, + O(2) => \vert_count_reg[8]_i_1_n_5\, + O(1) => \vert_count_reg[8]_i_1_n_6\, + O(0) => \vert_count_reg[8]_i_1_n_7\, + S(3) => \vert_count[8]_i_6_n_0\, + S(2) => \vert_count[8]_i_7_n_0\, + S(1) => \vert_count[8]_i_8_n_0\, + S(0) => \vert_count[8]_i_9_n_0\ + ); +\vert_count_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => \vert_count[0]_i_1_n_0\, + D => \vert_count_reg[8]_i_1_n_6\, + Q => vert_count_reg(9), + R => SR(0) + ); +zero_hsize_err_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, CE => '1', - D => axi_resetn, - Q => \^prmry_in\, - R => '0' + D => zero_hsize_err0, + Q => \^zero_hsize_err\, + R => SR(0) + ); +zero_vsize_err_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => zero_vsize_err0, + Q => \^zero_vsize_err\, + R => SR(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_srl_fifo_f is +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_sof_gen is port ( - Q : out STD_LOGIC_VECTOR ( 0 to 0 ); - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - \out\ : out STD_LOGIC_VECTOR ( 49 downto 0 ); - sig_calc_error_reg_reg : out STD_LOGIC; - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - sig_calc_error_pushed_reg : in STD_LOGIC; - sig_sm_halt_reg : in STD_LOGIC; - sig_input_reg_empty : in STD_LOGIC; - sig_calc_error_pushed : in STD_LOGIC; - p_55_out : in STD_LOGIC; - sig_inhibit_rdy_n : in STD_LOGIC; - cmnd_wr : in STD_LOGIC; - mm2s_halt : in STD_LOGIC; - \in\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - \s_axis_cmd_tdata_reg[63]\ : in STD_LOGIC_VECTOR ( 48 downto 0 ) + prmry_in_xored : out STD_LOGIC; + scndry_reset2 : in STD_LOGIC; + s_valid0 : in STD_LOGIC; + m_axis_mm2s_aclk : in STD_LOGIC; + p_in_d1_cdc_from : in STD_LOGIC; + \out\ : in STD_LOGIC; + p_15_out : in STD_LOGIC ); attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_srl_fifo_f : entity is "srl_fifo_f"; -end Arty_Z7_20_axi_vdma_0_0_srl_fifo_f; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_sof_gen : entity is "axi_vdma_sof_gen"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_sof_gen; -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_srl_fifo_f is +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_sof_gen is + signal hold_sof : STD_LOGIC; + signal hold_sof_i_1_n_0 : STD_LOGIC; + signal s_valid : STD_LOGIC; + signal s_valid_d1 : STD_LOGIC; begin -I_SRL_FIFO_RBU_F: entity work.Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f - port map ( - E(0) => E(0), - Q(0) => Q(0), - SR(0) => SR(0), - cmnd_wr => cmnd_wr, - \in\(0) => \in\(0), - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - mm2s_halt => mm2s_halt, - \out\(49 downto 0) => \out\(49 downto 0), - p_55_out => p_55_out, - \s_axis_cmd_tdata_reg[63]\(48 downto 0) => \s_axis_cmd_tdata_reg[63]\(48 downto 0), - sig_calc_error_pushed => sig_calc_error_pushed, - sig_calc_error_pushed_reg => sig_calc_error_pushed_reg, - sig_calc_error_reg_reg => sig_calc_error_reg_reg, - sig_inhibit_rdy_n => sig_inhibit_rdy_n, - sig_input_reg_empty => sig_input_reg_empty, - sig_sm_halt_reg => sig_sm_halt_reg +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__11\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EF10" + ) + port map ( + I0 => hold_sof, + I1 => s_valid_d1, + I2 => s_valid, + I3 => p_in_d1_cdc_from, + O => prmry_in_xored + ); +hold_sof_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000AE00" + ) + port map ( + I0 => hold_sof, + I1 => s_valid, + I2 => s_valid_d1, + I3 => \out\, + I4 => p_15_out, + O => hold_sof_i_1_n_0 + ); +hold_sof_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => hold_sof_i_1_n_0, + Q => hold_sof, + R => '0' + ); +s_valid_d1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => s_valid, + Q => s_valid_d1, + R => scndry_reset2 + ); +s_valid_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => s_valid0, + Q => s_valid, + R => scndry_reset2 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized0\ is +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_sof_gen_0 is port ( - \INFERRED_GEN.cnt_i_reg[1]\ : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 0 to 0 ); - sig_rd_sts_slverr_reg_reg : out STD_LOGIC; - interr_i_reg : out STD_LOGIC; - slverr_i_reg : out STD_LOGIC; - decerr_i_reg : out STD_LOGIC; - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - p_57_out : in STD_LOGIC; - sig_rsc2stat_status_valid : in STD_LOGIC; - sig_inhibit_rdy_n_reg : in STD_LOGIC; - sts_tready_reg : in STD_LOGIC; - sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; - sig_rd_sts_slverr_reg_reg_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ) + prmry_in_xored : out STD_LOGIC; + prmry_reset2 : in STD_LOGIC; + s_valid0 : in STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC; + p_in_d1_cdc_from : in STD_LOGIC; + \out\ : in STD_LOGIC; + s2mm_fsync_out_i : in STD_LOGIC ); attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized0\ : entity is "srl_fifo_f"; -end \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized0\; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_sof_gen_0 : entity is "axi_vdma_sof_gen"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_sof_gen_0; -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized0\ is +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_sof_gen_0 is + signal hold_sof : STD_LOGIC; + signal \hold_sof_i_1__0_n_0\ : STD_LOGIC; + signal s_valid : STD_LOGIC; + signal s_valid_d1 : STD_LOGIC; begin -I_SRL_FIFO_RBU_F: entity work.\Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized0\ - port map ( - \INFERRED_GEN.cnt_i_reg[1]\ => \INFERRED_GEN.cnt_i_reg[1]\, - Q(0) => Q(0), - SR(0) => SR(0), - decerr_i_reg => decerr_i_reg, - interr_i_reg => interr_i_reg, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - p_57_out => p_57_out, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_inhibit_rdy_n_reg => sig_inhibit_rdy_n_reg, - sig_rd_sts_slverr_reg_reg => sig_rd_sts_slverr_reg_reg, - sig_rd_sts_slverr_reg_reg_0(2 downto 0) => sig_rd_sts_slverr_reg_reg_0(2 downto 0), - sig_rsc2stat_status_valid => sig_rsc2stat_status_valid, - slverr_i_reg => slverr_i_reg, - sts_tready_reg => sts_tready_reg +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__12\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EF10" + ) + port map ( + I0 => hold_sof, + I1 => s_valid_d1, + I2 => s_valid, + I3 => p_in_d1_cdc_from, + O => prmry_in_xored + ); +\hold_sof_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000AE00" + ) + port map ( + I0 => hold_sof, + I1 => s_valid, + I2 => s_valid_d1, + I3 => \out\, + I4 => s2mm_fsync_out_i, + O => \hold_sof_i_1__0_n_0\ + ); +hold_sof_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => \hold_sof_i_1__0_n_0\, + Q => hold_sof, + R => '0' + ); +s_valid_d1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_valid, + Q => s_valid_d1, + R => prmry_reset2 + ); +s_valid_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_valid0, + Q => s_valid, + R => prmry_reset2 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized1\ is +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_sts_mngr is port ( - sig_calc_error_reg_reg : out STD_LOGIC; - sig_calc_error_reg_reg_0 : out STD_LOGIC; - sig_posted_to_axi_reg : out STD_LOGIC; - sig_addr_valid_reg_reg : out STD_LOGIC; - \out\ : out STD_LOGIC_VECTOR ( 39 downto 0 ); + datamover_idle : out STD_LOGIC; + halted_reg : out STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - sig_mstr2addr_cmd_valid : in STD_LOGIC; - sig_inhibit_rdy_n : in STD_LOGIC; - sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; - sig_data2addr_stop_req : in STD_LOGIC; - sig_addr_reg_empty : in STD_LOGIC; - sig_sf_allow_addr_req : in STD_LOGIC; - \in\ : in STD_LOGIC_VECTOR ( 37 downto 0 ) + s2mm_dmacr : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_s2mm_aclk : in STD_LOGIC; + halted_set_i0 : in STD_LOGIC; + sig_halt_cmplt_reg : in STD_LOGIC; + s2mm_dmasr : in STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized1\ : entity is "srl_fifo_f"; -end \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized1\; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_sts_mngr : entity is "axi_vdma_sts_mngr"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_sts_mngr; -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized1\ is +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_sts_mngr is + signal s2mm_halted_clr : STD_LOGIC; + signal s2mm_halted_set : STD_LOGIC; begin -I_SRL_FIFO_RBU_F: entity work.\Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized1\ +\I_DMA_REGISTER/halted_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF4F" + ) + port map ( + I0 => s2mm_halted_clr, + I1 => s2mm_dmasr(0), + I2 => \out\, + I3 => s2mm_halted_set, + O => halted_reg + ); +datamover_idle_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_halt_cmplt_reg, + Q => datamover_idle, + R => SR(0) + ); +halted_clr_reg: unisim.vcomponents.FDRE port map ( - SR(0) => SR(0), - \in\(37 downto 0) => \in\(37 downto 0), - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - \out\(39 downto 0) => \out\(39 downto 0), - sel => sig_calc_error_reg_reg_0, - sig_addr_reg_empty => sig_addr_reg_empty, - sig_addr_valid_reg_reg => sig_addr_valid_reg_reg, - sig_calc_error_reg_reg => sig_calc_error_reg_reg, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_data2addr_stop_req => sig_data2addr_stop_req, - sig_inhibit_rdy_n => sig_inhibit_rdy_n, - sig_mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid, - sig_posted_to_axi_reg => sig_posted_to_axi_reg, - sig_sf_allow_addr_req => sig_sf_allow_addr_req + C => m_axi_s2mm_aclk, + CE => '1', + D => s2mm_dmacr(0), + Q => s2mm_halted_clr, + R => SR(0) + ); +halted_set_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => halted_set_i0, + Q => s2mm_halted_set, + R => SR(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized2\ is +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_sts_mngr_42 is port ( - sig_dqual_reg_empty_reg : out STD_LOGIC; - sig_next_calc_error_reg_reg : out STD_LOGIC; - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - D : out STD_LOGIC_VECTOR ( 7 downto 0 ); - sig_dqual_reg_empty_reg_0 : out STD_LOGIC; - sig_ld_new_cmd_reg_reg : out STD_LOGIC; - sig_last_dbeat_reg : out STD_LOGIC; - sig_next_cmd_cmplt_reg_reg : out STD_LOGIC; - \out\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + p_37_out : out STD_LOGIC; + datamover_idle : out STD_LOGIC; + halted_reg : out STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : in STD_LOGIC; m_axi_mm2s_aclk : in STD_LOGIC; - sig_mstr2data_cmd_valid : in STD_LOGIC; - sig_inhibit_rdy_n_0 : in STD_LOGIC; - \sig_dbeat_cntr_reg[2]\ : in STD_LOGIC; - Q : in STD_LOGIC_VECTOR ( 7 downto 0 ); - sig_next_sequential_reg : in STD_LOGIC; - sig_last_dbeat : in STD_LOGIC; - sig_dqual_reg_empty : in STD_LOGIC; - m_axi_mm2s_rvalid : in STD_LOGIC; - sig_halt_reg_reg : in STD_LOGIC; - ram_full_i_reg : in STD_LOGIC; - \sig_advance_pipe9_out__1\ : in STD_LOGIC; - sig_rsc2stat_status_valid : in STD_LOGIC; - FIFO_Full_reg : in STD_LOGIC; - sig_inhibit_rdy_n : in STD_LOGIC; - sig_next_calc_error_reg : in STD_LOGIC; - sig_addr_posted_cntr : in STD_LOGIC_VECTOR ( 2 downto 0 ); - sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; - sig_ld_new_cmd_reg : in STD_LOGIC; - sig_dbeat_cntr_eq_1 : in STD_LOGIC; - sig_dqual_reg_full : in STD_LOGIC; - m_axi_mm2s_rlast : in STD_LOGIC; - \sig_dbeat_cntr_reg[3]\ : in STD_LOGIC; - \sig_dbeat_cntr_reg[4]\ : in STD_LOGIC; - \in\ : in STD_LOGIC_VECTOR ( 7 downto 0 ) + p_71_out : in STD_LOGIC_VECTOR ( 0 to 0 ); + halted_set_i0 : in STD_LOGIC; + sig_halt_cmplt_reg : in STD_LOGIC; + p_70_out : in STD_LOGIC; + mm2s_prmry_resetn : in STD_LOGIC ); attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized2\ : entity is "srl_fifo_f"; -end \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized2\; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_sts_mngr_42 : entity is "axi_vdma_sts_mngr"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_sts_mngr_42; -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized2\ is +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_sts_mngr_42 is + signal p_27_out : STD_LOGIC; + signal p_28_out : STD_LOGIC; begin -I_SRL_FIFO_RBU_F: entity work.\Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized2\ +\I_DMA_REGISTER/halted_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF4F" + ) + port map ( + I0 => p_27_out, + I1 => p_70_out, + I2 => mm2s_prmry_resetn, + I3 => p_28_out, + O => halted_reg + ); +all_idle_reg: unisim.vcomponents.FDSE port map ( - D(7 downto 0) => D(7 downto 0), - E(0) => E(0), - FIFO_Full_reg_0 => FIFO_Full_reg, - Q(7 downto 0) => Q(7 downto 0), - SR(0) => SR(0), - \in\(7 downto 0) => \in\(7 downto 0), - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axi_mm2s_rlast => m_axi_mm2s_rlast, - m_axi_mm2s_rvalid => m_axi_mm2s_rvalid, - \out\(3 downto 0) => \out\(3 downto 0), - ram_full_i_reg => ram_full_i_reg, - sel => sig_next_calc_error_reg_reg, - sig_addr_posted_cntr(2 downto 0) => sig_addr_posted_cntr(2 downto 0), - \sig_advance_pipe9_out__1\ => \sig_advance_pipe9_out__1\, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_dbeat_cntr_eq_1 => sig_dbeat_cntr_eq_1, - \sig_dbeat_cntr_reg[2]\ => \sig_dbeat_cntr_reg[2]\, - \sig_dbeat_cntr_reg[3]\ => \sig_dbeat_cntr_reg[3]\, - \sig_dbeat_cntr_reg[4]\ => \sig_dbeat_cntr_reg[4]\, - sig_dqual_reg_empty => sig_dqual_reg_empty, - sig_dqual_reg_empty_reg => sig_dqual_reg_empty_reg, - sig_dqual_reg_empty_reg_0 => sig_dqual_reg_empty_reg_0, - sig_dqual_reg_full => sig_dqual_reg_full, - sig_halt_reg_reg => sig_halt_reg_reg, - sig_inhibit_rdy_n => sig_inhibit_rdy_n, - sig_inhibit_rdy_n_0 => sig_inhibit_rdy_n_0, - sig_last_dbeat => sig_last_dbeat, - sig_last_dbeat_reg => sig_last_dbeat_reg, - sig_ld_new_cmd_reg => sig_ld_new_cmd_reg, - sig_ld_new_cmd_reg_reg => sig_ld_new_cmd_reg_reg, - sig_mstr2data_cmd_valid => sig_mstr2data_cmd_valid, - sig_next_calc_error_reg => sig_next_calc_error_reg, - sig_next_cmd_cmplt_reg_reg => sig_next_cmd_cmplt_reg_reg, - sig_next_sequential_reg => sig_next_sequential_reg, - sig_rsc2stat_status_valid => sig_rsc2stat_status_valid + C => m_axi_mm2s_aclk, + CE => '1', + D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\, + Q => p_37_out, + S => SR(0) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized3\ is - port ( - p_0_out : out STD_LOGIC_VECTOR ( 0 to 0 ); - FIFO_Full_reg : out STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[1]\ : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 0 to 0 ); - \in\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - sig_stream_rst : in STD_LOGIC; - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : in STD_LOGIC; - sig_mstr2sf_cmd_valid : in STD_LOGIC; - sig_inhibit_rdy_n_reg : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized3\ : entity is "srl_fifo_f"; -end \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized3\; - -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized3\ is -begin -I_SRL_FIFO_RBU_F: entity work.\Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized3\ +datamover_idle_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => sig_halt_cmplt_reg, + Q => datamover_idle, + R => SR(0) + ); +halted_clr_reg: unisim.vcomponents.FDRE port map ( - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\, - FIFO_Full_reg_0 => FIFO_Full_reg, - \INFERRED_GEN.cnt_i_reg[1]\ => \INFERRED_GEN.cnt_i_reg[1]\, - Q(0) => Q(0), - \in\(0) => \in\(0), - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - p_0_out(0) => p_0_out(0), - sig_inhibit_rdy_n_reg => sig_inhibit_rdy_n_reg, - sig_mstr2sf_cmd_valid => sig_mstr2sf_cmd_valid, - sig_stream_rst => sig_stream_rst + C => m_axi_mm2s_aclk, + CE => '1', + D => p_71_out(0), + Q => p_27_out, + R => SR(0) + ); +halted_set_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => halted_set_i0, + Q => p_28_out, + R => SR(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_generic_cstr is +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_vregister is port ( - DOBDO : out STD_LOGIC_VECTOR ( 0 to 0 ); - \sig_user_skid_reg_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - dm2linebuf_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : out STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[0]\ : out STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - ram_empty_fb_i_reg : in STD_LOGIC; - ram_full_i_reg : in STD_LOGIC; - \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC; - sig_stream_rst : in STD_LOGIC; - \gc1.count_d2_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); - Q : in STD_LOGIC_VECTOR ( 6 downto 0 ); - m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); - DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ); - lsig_0ffset_cntr : in STD_LOGIC; - lsig_cmd_loaded : in STD_LOGIC; - \gpregsm1.user_valid_reg\ : in STD_LOGIC; - hold_ff_q : in STD_LOGIC; - p_0_out : in STD_LOGIC_VECTOR ( 0 to 0 ); - dm2linebuf_mm2s_tvalid : in STD_LOGIC; - p_8_out : in STD_LOGIC; - \fifo_wren__0\ : in STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + zero_hsize_err0 : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 15 downto 0 ); + zero_vsize_err0 : out STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); + \dm_address_reg[19]\ : out STD_LOGIC; + \dm_address_reg[19]_0\ : out STD_LOGIC; + \dm_address_reg[19]_1\ : out STD_LOGIC; + \dm_address_reg[19]_2\ : out STD_LOGIC; + \dm_address_reg[23]\ : out STD_LOGIC; + \dm_address_reg[23]_0\ : out STD_LOGIC; + \dm_address_reg[23]_1\ : out STD_LOGIC; + \dm_address_reg[23]_2\ : out STD_LOGIC; + \dm_address_reg[27]\ : out STD_LOGIC; + \dm_address_reg[27]_0\ : out STD_LOGIC; + \dm_address_reg[27]_1\ : out STD_LOGIC; + \dm_address_reg[27]_2\ : out STD_LOGIC; + \dm_address_reg[31]\ : out STD_LOGIC; + \dm_address_reg[31]_0\ : out STD_LOGIC; + \dm_address_reg[31]_1\ : out STD_LOGIC; + \dm_address_reg[31]_2\ : out STD_LOGIC; + S : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_STS_GRTR_THAN_8.undrflo_err_reg\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + O : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \dm_address_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \dm_address_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + CO : out STD_LOGIC_VECTOR ( 0 to 0 ); + \dm_address_reg[15]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + load_new_addr : in STD_LOGIC; + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axis_s2mm_sts_tdata : in STD_LOGIC_VECTOR ( 0 to 0 ); + prmtr_update_complete : in STD_LOGIC; + s2mm_cdc2dmac_fsync : in STD_LOGIC; + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\ : in STD_LOGIC; + \dm_address_reg[15]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + \reg_module_vsize_reg[12]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + m_axi_s2mm_aclk : in STD_LOGIC; + \reg_module_hsize_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ) ); attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; -end Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_generic_cstr; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_vregister : entity is "axi_vdma_vregister"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_vregister; -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_generic_cstr is +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_vregister is + signal \^gen_s2mm_flush_sof_logic.gen_for_async_flush_sof.crnt_vsize_cdc_tig_reg[12]\ : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \^q\ : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \dm_address[0]_i_10__0_n_0\ : STD_LOGIC; + signal \dm_address[0]_i_11__0_n_0\ : STD_LOGIC; + signal \dm_address[0]_i_12__0_n_0\ : STD_LOGIC; + signal \dm_address[0]_i_13__0_n_0\ : STD_LOGIC; + signal \dm_address[0]_i_14__0_n_0\ : STD_LOGIC; + signal \dm_address[0]_i_3__0_n_0\ : STD_LOGIC; + signal \dm_address[0]_i_4__0_n_0\ : STD_LOGIC; + signal \dm_address[0]_i_5__0_n_0\ : STD_LOGIC; + signal \dm_address[0]_i_6__0_n_0\ : STD_LOGIC; + signal \dm_address[0]_i_7__0_n_0\ : STD_LOGIC; + signal \dm_address[0]_i_8__0_n_0\ : STD_LOGIC; + signal \dm_address[0]_i_9__0_n_0\ : STD_LOGIC; + signal \dm_address[12]_i_10__0_n_0\ : STD_LOGIC; + signal \dm_address[12]_i_11__0_n_0\ : STD_LOGIC; + signal \dm_address[12]_i_12__0_n_0\ : STD_LOGIC; + signal \dm_address[12]_i_13__0_n_0\ : STD_LOGIC; + signal \dm_address[12]_i_2__0_n_0\ : STD_LOGIC; + signal \dm_address[12]_i_3__0_n_0\ : STD_LOGIC; + signal \dm_address[12]_i_4__0_n_0\ : STD_LOGIC; + signal \dm_address[12]_i_5__0_n_0\ : STD_LOGIC; + signal \dm_address[12]_i_6__0_n_0\ : STD_LOGIC; + signal \dm_address[12]_i_7__0_n_0\ : STD_LOGIC; + signal \dm_address[12]_i_8__0_n_0\ : STD_LOGIC; + signal \dm_address[12]_i_9__0_n_0\ : STD_LOGIC; + signal \dm_address[4]_i_10__0_n_0\ : STD_LOGIC; + signal \dm_address[4]_i_11__0_n_0\ : STD_LOGIC; + signal \dm_address[4]_i_12__0_n_0\ : STD_LOGIC; + signal \dm_address[4]_i_13__0_n_0\ : STD_LOGIC; + signal \dm_address[4]_i_2__0_n_0\ : STD_LOGIC; + signal \dm_address[4]_i_3__0_n_0\ : STD_LOGIC; + signal \dm_address[4]_i_4__0_n_0\ : STD_LOGIC; + signal \dm_address[4]_i_5__0_n_0\ : STD_LOGIC; + signal \dm_address[4]_i_6__0_n_0\ : STD_LOGIC; + signal \dm_address[4]_i_7__0_n_0\ : STD_LOGIC; + signal \dm_address[4]_i_8__0_n_0\ : STD_LOGIC; + signal \dm_address[4]_i_9__0_n_0\ : STD_LOGIC; + signal \dm_address[8]_i_10__0_n_0\ : STD_LOGIC; + signal \dm_address[8]_i_11__0_n_0\ : STD_LOGIC; + signal \dm_address[8]_i_12__0_n_0\ : STD_LOGIC; + signal \dm_address[8]_i_13__0_n_0\ : STD_LOGIC; + signal \dm_address[8]_i_2__0_n_0\ : STD_LOGIC; + signal \dm_address[8]_i_3__0_n_0\ : STD_LOGIC; + signal \dm_address[8]_i_4__0_n_0\ : STD_LOGIC; + signal \dm_address[8]_i_5__0_n_0\ : STD_LOGIC; + signal \dm_address[8]_i_6__0_n_0\ : STD_LOGIC; + signal \dm_address[8]_i_7__0_n_0\ : STD_LOGIC; + signal \dm_address[8]_i_8__0_n_0\ : STD_LOGIC; + signal \dm_address[8]_i_9__0_n_0\ : STD_LOGIC; + signal \dm_address_reg[0]_i_2__0_n_0\ : STD_LOGIC; + signal \dm_address_reg[0]_i_2__0_n_1\ : STD_LOGIC; + signal \dm_address_reg[0]_i_2__0_n_2\ : STD_LOGIC; + signal \dm_address_reg[0]_i_2__0_n_3\ : STD_LOGIC; + signal \dm_address_reg[12]_i_1__0_n_1\ : STD_LOGIC; + signal \dm_address_reg[12]_i_1__0_n_2\ : STD_LOGIC; + signal \dm_address_reg[12]_i_1__0_n_3\ : STD_LOGIC; + signal \dm_address_reg[4]_i_1__0_n_0\ : STD_LOGIC; + signal \dm_address_reg[4]_i_1__0_n_1\ : STD_LOGIC; + signal \dm_address_reg[4]_i_1__0_n_2\ : STD_LOGIC; + signal \dm_address_reg[4]_i_1__0_n_3\ : STD_LOGIC; + signal \dm_address_reg[8]_i_1__0_n_0\ : STD_LOGIC; + signal \dm_address_reg[8]_i_1__0_n_1\ : STD_LOGIC; + signal \dm_address_reg[8]_i_1__0_n_2\ : STD_LOGIC; + signal \dm_address_reg[8]_i_1__0_n_3\ : STD_LOGIC; + signal stride_vid : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal video_reg_update : STD_LOGIC; + signal \zero_hsize_err_i_2__0_n_0\ : STD_LOGIC; + signal \zero_hsize_err_i_3__0_n_0\ : STD_LOGIC; + signal \zero_hsize_err_i_4__0_n_0\ : STD_LOGIC; + signal \zero_vsize_err_i_2__0_n_0\ : STD_LOGIC; + signal \zero_vsize_err_i_3__0_n_0\ : STD_LOGIC; + attribute METHODOLOGY_DRC_VIOS : string; + attribute METHODOLOGY_DRC_VIOS of \dm_address_reg[0]_i_2__0\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \dm_address_reg[12]_i_1__0\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \dm_address_reg[4]_i_1__0\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \dm_address_reg[8]_i_1__0\ : label is "{SYNTH-8 {cell *THIS*}}"; begin -\ramloop[0].ram.r\: entity work.Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_width + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12]\(12 downto 0) <= \^gen_s2mm_flush_sof_logic.gen_for_async_flush_sof.crnt_vsize_cdc_tig_reg[12]\(12 downto 0); + Q(15 downto 0) <= \^q\(15 downto 0); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][0]\: unisim.vcomponents.FDRE port map ( - DIBDI(1 downto 0) => DIBDI(1 downto 0), - DOBDO(0) => DOBDO(0), - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, - \INFERRED_GEN.cnt_i_reg[0]\ => \INFERRED_GEN.cnt_i_reg[0]\, - \INFERRED_GEN.cnt_i_reg[2]\(0) => \INFERRED_GEN.cnt_i_reg[2]\(0), - Q(6 downto 0) => Q(6 downto 0), - dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), - dm2linebuf_mm2s_tvalid => dm2linebuf_mm2s_tvalid, - \fifo_wren__0\ => \fifo_wren__0\, - \gc1.count_d2_reg[6]\(6 downto 0) => \gc1.count_d2_reg[6]\(6 downto 0), - \gpregsm1.curr_fwft_state_reg[0]\ => \gpregsm1.curr_fwft_state_reg[0]\, - \gpregsm1.user_valid_reg\ => \gpregsm1.user_valid_reg\, - hold_ff_q => hold_ff_q, - lsig_0ffset_cntr => lsig_0ffset_cntr, - lsig_cmd_loaded => lsig_cmd_loaded, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axi_mm2s_rdata(63 downto 0) => m_axi_mm2s_rdata(63 downto 0), - p_0_out(0) => p_0_out(0), - p_8_out => p_8_out, - ram_empty_fb_i_reg => ram_empty_fb_i_reg, - ram_full_i_reg => ram_full_i_reg, - sig_stream_rst => sig_stream_rst, - \sig_user_skid_reg_reg[0]\(0) => \sig_user_skid_reg_reg[0]\(0) + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(0), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(0), + R => SR(0) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_builtin_top_v6 is - port ( - fifo_full_i : out STD_LOGIC; - sig_m_valid_out_reg : out STD_LOGIC; - fifo_dout : out STD_LOGIC_VECTOR ( 33 downto 0 ); - \fifo_wren__0\ : in STD_LOGIC; - \out\ : in STD_LOGIC; - m_axis_mm2s_aclk : in STD_LOGIC; - RST : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - dm2linebuf_mm2s_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - DIN : in STD_LOGIC_VECTOR ( 1 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_builtin_top_v6 : entity is "builtin_top_v6"; -end Arty_Z7_20_axi_vdma_0_0_builtin_top_v6; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_builtin_top_v6 is - signal p_15_out : STD_LOGIC; - signal p_16_out : STD_LOGIC; - signal p_22_out : STD_LOGIC; - signal p_23_out : STD_LOGIC; - signal p_4_out : STD_LOGIC; - signal p_5_out : STD_LOGIC; - signal p_8_out : STD_LOGIC; - signal p_9_out : STD_LOGIC; - signal rd_tmp : STD_LOGIC; - signal wr_tmp : STD_LOGIC; -begin -\gextw[1].gnll_fifo.inst_extd\: entity work.Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6 +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][10]\: unisim.vcomponents.FDRE port map ( - EMPTY => p_23_out, - FULL => p_22_out, - RD_EN => rd_tmp, - RST => RST, - WR_EN => wr_tmp, - dm2linebuf_mm2s_tdata(8 downto 0) => dm2linebuf_mm2s_tdata(8 downto 0), - fifo_dout(8 downto 0) => fifo_dout(8 downto 0), - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axis_mm2s_aclk => m_axis_mm2s_aclk + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(10), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(10), + R => SR(0) ); -\gextw[2].gnll_fifo.inst_extd\: entity work.Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_7 +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][11]\: unisim.vcomponents.FDRE port map ( - EMPTY => p_16_out, - FULL => p_15_out, - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ => p_5_out, - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\ => p_4_out, - RD_EN => rd_tmp, - RST => RST, - WR_EN => wr_tmp, - dm2linebuf_mm2s_tdata(8 downto 0) => dm2linebuf_mm2s_tdata(17 downto 9), - fifo_dout(8 downto 0) => fifo_dout(17 downto 9), - fifo_full_i => fifo_full_i, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axis_mm2s_aclk => m_axis_mm2s_aclk, - sig_m_valid_out_reg => sig_m_valid_out_reg, - sig_s_ready_out_reg => p_22_out, - sig_s_ready_out_reg_0 => p_8_out, - sig_s_ready_out_reg_1 => p_23_out, - sig_s_ready_out_reg_2 => p_9_out + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(11), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(11), + R => SR(0) ); -\gextw[3].gnll_fifo.inst_extd\: entity work.Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_8 +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][12]\: unisim.vcomponents.FDRE port map ( - EMPTY => p_9_out, - FULL => p_8_out, - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ => p_4_out, - RD_EN => rd_tmp, - RST => RST, - WR_EN => wr_tmp, - dm2linebuf_mm2s_tdata(8 downto 0) => dm2linebuf_mm2s_tdata(26 downto 18), - fifo_dout(8 downto 0) => fifo_dout(26 downto 18), - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axis_mm2s_aclk => m_axis_mm2s_aclk, - \out\ => \out\, - sig_s_ready_out_reg => p_23_out, - sig_s_ready_out_reg_0 => p_16_out + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(12), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(12), + R => SR(0) ); -\gextw[4].gnll_fifo.inst_extd\: entity work.Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_9 +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][13]\: unisim.vcomponents.FDRE port map ( - DIN(6 downto 5) => DIN(1 downto 0), - DIN(4 downto 0) => dm2linebuf_mm2s_tdata(31 downto 27), - EMPTY => p_4_out, - FULL => p_5_out, - RD_EN => rd_tmp, - RST => RST, - WR_EN => wr_tmp, - fifo_dout(6 downto 0) => fifo_dout(33 downto 27), - \fifo_wren__0\ => \fifo_wren__0\, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axis_mm2s_aclk => m_axis_mm2s_aclk, - sig_s_ready_out_reg => p_8_out, - sig_s_ready_out_reg_0 => p_22_out, - sig_s_ready_out_reg_1 => p_15_out + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(13), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(13), + R => SR(0) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_rd_logic is - port ( - \out\ : out STD_LOGIC; - hold_ff_q_reg : out STD_LOGIC; - p_7_out : out STD_LOGIC; - dm2linebuf_mm2s_tvalid : out STD_LOGIC; - DI : out STD_LOGIC_VECTOR ( 3 downto 0 ); - Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); - hold_ff_q_reg_0 : out STD_LOGIC; - sig_ok_to_post_rd_addr_reg : out STD_LOGIC; - \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : out STD_LOGIC; - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC; - S : out STD_LOGIC_VECTOR ( 3 downto 0 ); - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0\ : out STD_LOGIC; - \count_reg[6]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); - \gc1.count_d2_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_1\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); - sig_stream_rst : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - \ram_empty_i0__3\ : in STD_LOGIC; - ram_full_i_reg : in STD_LOGIC; - lsig_cmd_loaded : in STD_LOGIC; - hold_ff_q : in STD_LOGIC; - ram_full_i_reg_0 : in STD_LOGIC; - \sig_token_cntr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); - lsig_0ffset_cntr : in STD_LOGIC; - p_8_out : in STD_LOGIC; - sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; - sig_posted_to_axi_2_reg : in STD_LOGIC; - sig_posted_to_axi_2_reg_0 : in STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - DOBDO : in STD_LOGIC_VECTOR ( 0 to 0 ); - D : in STD_LOGIC_VECTOR ( 5 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_rd_logic : entity is "rd_logic"; -end Arty_Z7_20_axi_vdma_0_0_rd_logic; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_rd_logic is - signal cntr_en : STD_LOGIC; - signal \^out\ : STD_LOGIC; - signal \^p_7_out\ : STD_LOGIC; -begin - \out\ <= \^out\; - p_7_out <= \^p_7_out\; -\gr1.gr1_int.rfwft\: entity work.Arty_Z7_20_axi_vdma_0_0_rd_fwft +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][14]\: unisim.vcomponents.FDRE port map ( - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\, - DOBDO(0) => DOBDO(0), - E(0) => cntr_en, - \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, - \INFERRED_GEN.cnt_i_reg[2]\(0) => \INFERRED_GEN.cnt_i_reg[2]\(0), - dm2linebuf_mm2s_tvalid => dm2linebuf_mm2s_tvalid, - \gc1.count_reg[0]\(0) => \^p_7_out\, - hold_ff_q => hold_ff_q, - hold_ff_q_reg => hold_ff_q_reg_0, - lsig_0ffset_cntr => lsig_0ffset_cntr, - lsig_cmd_loaded => lsig_cmd_loaded, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - \out\ => hold_ff_q_reg, - p_8_out => p_8_out, - ram_empty_fb_i_reg => \^out\, - ram_full_i_reg => ram_full_i_reg, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_stream_rst => sig_stream_rst + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(14), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(14), + R => SR(0) ); -\grss.gdc.dc\: entity work.Arty_Z7_20_axi_vdma_0_0_dc_ss +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][15]\: unisim.vcomponents.FDRE port map ( - D(5 downto 0) => D(5 downto 0), - DI(3 downto 0) => DI(3 downto 0), - E(0) => \^p_7_out\, - Q(1 downto 0) => Q(1 downto 0), - S(3 downto 0) => S(3 downto 0), - \count_reg[6]\(1 downto 0) => \count_reg[6]\(1 downto 0), - \gpregsm1.curr_fwft_state_reg[0]\(0) => cntr_en, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - ram_full_i_reg => ram_full_i_reg_0, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_ok_to_post_rd_addr_reg => sig_ok_to_post_rd_addr_reg, - sig_posted_to_axi_2_reg => sig_posted_to_axi_2_reg, - sig_posted_to_axi_2_reg_0 => sig_posted_to_axi_2_reg_0, - sig_stream_rst => sig_stream_rst, - \sig_token_cntr_reg[3]\(3 downto 0) => \sig_token_cntr_reg[3]\(3 downto 0) + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(15), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(15), + R => SR(0) ); -\grss.rsts\: entity work.Arty_Z7_20_axi_vdma_0_0_rd_status_flags_ss +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][16]\: unisim.vcomponents.FDRE port map ( - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0\, - E(0) => \^p_7_out\, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - \out\ => \^out\, - \ram_empty_i0__3\ => \ram_empty_i0__3\, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_stream_rst => sig_stream_rst + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(16), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(16), + R => SR(0) ); -rpntr: entity work.Arty_Z7_20_axi_vdma_0_0_rd_bin_cntr +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][17]\: unisim.vcomponents.FDRE port map ( - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(6 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_1\(6 downto 0), - E(0) => \^p_7_out\, - \gc1.count_d2_reg[6]_0\(6 downto 0) => \gc1.count_d2_reg[6]\(6 downto 0), - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - sig_stream_rst => sig_stream_rst + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(17), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(17), + R => SR(0) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo is - port ( - sig_init_done : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 0 to 0 ); - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - \out\ : out STD_LOGIC_VECTOR ( 49 downto 0 ); - sig_calc_error_reg_reg : out STD_LOGIC; - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - sig_mmap_reset_reg_reg : in STD_LOGIC; - sig_calc_error_pushed_reg : in STD_LOGIC; - sig_sm_halt_reg : in STD_LOGIC; - sig_input_reg_empty : in STD_LOGIC; - sig_calc_error_pushed : in STD_LOGIC; - p_55_out : in STD_LOGIC; - cmnd_wr : in STD_LOGIC; - mm2s_halt : in STD_LOGIC; - \in\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - \s_axis_cmd_tdata_reg[63]\ : in STD_LOGIC_VECTOR ( 48 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo : entity is "axi_datamover_fifo"; -end Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo is - signal sig_inhibit_rdy_n : STD_LOGIC; - signal \sig_inhibit_rdy_n_i_1__3_n_0\ : STD_LOGIC; - signal \^sig_init_done\ : STD_LOGIC; -begin - sig_init_done <= \^sig_init_done\; -\USE_SRL_FIFO.I_SYNC_FIFO\: entity work.Arty_Z7_20_axi_vdma_0_0_srl_fifo_f +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][18]\: unisim.vcomponents.FDRE port map ( - E(0) => E(0), - Q(0) => Q(0), - SR(0) => SR(0), - cmnd_wr => cmnd_wr, - \in\(0) => \in\(0), - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - mm2s_halt => mm2s_halt, - \out\(49 downto 0) => \out\(49 downto 0), - p_55_out => p_55_out, - \s_axis_cmd_tdata_reg[63]\(48 downto 0) => \s_axis_cmd_tdata_reg[63]\(48 downto 0), - sig_calc_error_pushed => sig_calc_error_pushed, - sig_calc_error_pushed_reg => sig_calc_error_pushed_reg, - sig_calc_error_reg_reg => sig_calc_error_reg_reg, - sig_inhibit_rdy_n => sig_inhibit_rdy_n, - sig_input_reg_empty => sig_input_reg_empty, - sig_sm_halt_reg => sig_sm_halt_reg + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(18), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(18), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][19]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(19), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(19), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(1), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(1), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][20]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(20), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(20), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][21]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(21), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(21), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][22]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(22), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(22), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][23]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(23), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(23), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][24]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(24), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(24), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][25]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(25), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(25), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][26]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(26), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(26), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][27]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(27), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(27), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][28]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(28), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(28), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][29]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(29), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(29), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(2), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(2), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][30]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(30), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(30), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(31), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(31), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(3), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(3), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(4), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(4), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][5]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(5), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(5), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][6]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(6), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(6), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][7]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(7), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(7), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][8]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(8), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(8), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][9]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(9), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(9), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(0), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(0), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][10]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(10), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(10), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][11]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(11), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(11), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][12]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(12), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(12), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][13]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(13), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(13), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][14]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(14), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(14), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][15]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(15), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(15), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][16]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(16), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(16), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][17]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(17), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(17), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][18]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(18), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(18), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][19]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(19), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(19), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(1), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(1), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][20]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(20), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(20), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][21]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(21), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(21), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][22]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(22), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(22), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][23]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(23), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(23), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][24]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(24), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(24), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][25]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(25), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(25), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][26]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(26), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(26), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][27]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(27), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(27), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][28]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(28), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(28), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][29]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(29), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(29), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(2), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(2), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][30]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(30), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(30), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(31), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(31), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(3), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(3), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(4), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(4), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][5]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(5), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(5), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][6]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(6), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(6), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][7]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(7), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(7), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][8]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(8), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(8), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][9]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(9), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(9), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(0), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(0), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][10]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(10), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(10), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][11]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(11), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(11), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][12]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(12), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(12), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][13]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(13), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(13), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][14]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(14), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(14), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][15]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(15), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(15), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][16]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(16), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(16), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][17]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(17), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(17), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][18]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(18), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(18), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][19]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(19), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(19), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(1), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(1), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][20]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(20), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(20), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][21]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(21), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(21), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][22]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(22), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(22), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][23]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(23), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(23), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][24]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(24), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(24), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][25]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(25), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(25), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][26]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(26), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(26), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][27]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(27), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(27), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][28]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(28), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(28), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][29]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(29), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(29), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(2), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(2), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][30]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(30), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(30), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(31), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(31), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(3), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(3), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(4), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(4), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][5]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(5), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(5), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][6]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(6), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(6), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][7]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(7), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(7), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][8]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(8), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(8), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][9]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(9), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(9), + R => SR(0) + ); +\GEN_STS_GRTR_THAN_8.ovrflo_err_i_9\: unisim.vcomponents.LUT4 + generic map( + INIT => X"1001" + ) + port map ( + I0 => \^q\(2), + I1 => \^q\(1), + I2 => \^q\(0), + I3 => m_axis_s2mm_sts_tdata(0), + O => S(0) + ); +\GEN_STS_GRTR_THAN_8.undrflo_err_i_9\: unisim.vcomponents.LUT4 + generic map( + INIT => X"1001" + ) + port map ( + I0 => \^q\(2), + I1 => \^q\(1), + I2 => \^q\(0), + I3 => m_axis_s2mm_sts_tdata(0), + O => \GEN_STS_GRTR_THAN_8.undrflo_err_reg\(0) + ); +\dm_address[0]_i_10__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(0), + I1 => \dm_address_reg[15]_0\(0), + I2 => load_new_addr, + I3 => \dm_address[0]_i_14__0_n_0\, + O => \dm_address[0]_i_10__0_n_0\ + ); +\dm_address[0]_i_11__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(3), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(3), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(3), + O => \dm_address[0]_i_11__0_n_0\ + ); +\dm_address[0]_i_12__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(2), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(2), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(2), + O => \dm_address[0]_i_12__0_n_0\ + ); +\dm_address[0]_i_13__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(1), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(1), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(1), + O => \dm_address[0]_i_13__0_n_0\ + ); +\dm_address[0]_i_14__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(0), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(0), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(0), + O => \dm_address[0]_i_14__0_n_0\ + ); +\dm_address[0]_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(3), + I1 => load_new_addr, + O => \dm_address[0]_i_3__0_n_0\ + ); +\dm_address[0]_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(2), + I1 => load_new_addr, + O => \dm_address[0]_i_4__0_n_0\ + ); +\dm_address[0]_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(1), + I1 => load_new_addr, + O => \dm_address[0]_i_5__0_n_0\ + ); +\dm_address[0]_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(0), + I1 => load_new_addr, + O => \dm_address[0]_i_6__0_n_0\ + ); +\dm_address[0]_i_7__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(3), + I1 => \dm_address_reg[15]_0\(3), + I2 => load_new_addr, + I3 => \dm_address[0]_i_11__0_n_0\, + O => \dm_address[0]_i_7__0_n_0\ + ); +\dm_address[0]_i_8__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(2), + I1 => \dm_address_reg[15]_0\(2), + I2 => load_new_addr, + I3 => \dm_address[0]_i_12__0_n_0\, + O => \dm_address[0]_i_8__0_n_0\ + ); +\dm_address[0]_i_9__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(1), + I1 => \dm_address_reg[15]_0\(1), + I2 => load_new_addr, + I3 => \dm_address[0]_i_13__0_n_0\, + O => \dm_address[0]_i_9__0_n_0\ + ); +\dm_address[12]_i_10__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(15), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(15), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(15), + O => \dm_address[12]_i_10__0_n_0\ + ); +\dm_address[12]_i_11__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(14), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(14), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(14), + O => \dm_address[12]_i_11__0_n_0\ + ); +\dm_address[12]_i_12__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(13), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(13), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(13), + O => \dm_address[12]_i_12__0_n_0\ + ); +\dm_address[12]_i_13__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(12), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(12), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(12), + O => \dm_address[12]_i_13__0_n_0\ + ); +\dm_address[12]_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(15), + I1 => load_new_addr, + O => \dm_address[12]_i_2__0_n_0\ + ); +\dm_address[12]_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(14), + I1 => load_new_addr, + O => \dm_address[12]_i_3__0_n_0\ + ); +\dm_address[12]_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(13), + I1 => load_new_addr, + O => \dm_address[12]_i_4__0_n_0\ + ); +\dm_address[12]_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(12), + I1 => load_new_addr, + O => \dm_address[12]_i_5__0_n_0\ + ); +\dm_address[12]_i_6__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(15), + I1 => \dm_address_reg[15]_0\(15), + I2 => load_new_addr, + I3 => \dm_address[12]_i_10__0_n_0\, + O => \dm_address[12]_i_6__0_n_0\ + ); +\dm_address[12]_i_7__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(14), + I1 => \dm_address_reg[15]_0\(14), + I2 => load_new_addr, + I3 => \dm_address[12]_i_11__0_n_0\, + O => \dm_address[12]_i_7__0_n_0\ + ); +\dm_address[12]_i_8__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(13), + I1 => \dm_address_reg[15]_0\(13), + I2 => load_new_addr, + I3 => \dm_address[12]_i_12__0_n_0\, + O => \dm_address[12]_i_8__0_n_0\ + ); +\dm_address[12]_i_9__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(12), + I1 => \dm_address_reg[15]_0\(12), + I2 => load_new_addr, + I3 => \dm_address[12]_i_13__0_n_0\, + O => \dm_address[12]_i_9__0_n_0\ + ); +\dm_address[16]_i_6__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(19), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(19), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(19), + O => \dm_address_reg[19]_2\ + ); +\dm_address[16]_i_7__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(18), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(18), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(18), + O => \dm_address_reg[19]_1\ + ); +\dm_address[16]_i_8__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(17), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(17), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(17), + O => \dm_address_reg[19]_0\ + ); +\dm_address[16]_i_9__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(16), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(16), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(16), + O => \dm_address_reg[19]\ + ); +\dm_address[20]_i_6__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(23), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(23), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(23), + O => \dm_address_reg[23]_2\ + ); +\dm_address[20]_i_7__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(22), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(22), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(22), + O => \dm_address_reg[23]_1\ + ); +\dm_address[20]_i_8__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(21), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(21), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(21), + O => \dm_address_reg[23]_0\ + ); +\dm_address[20]_i_9__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(20), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(20), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(20), + O => \dm_address_reg[23]\ + ); +\dm_address[24]_i_6__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(27), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(27), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(27), + O => \dm_address_reg[27]_2\ + ); +\dm_address[24]_i_7__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(26), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(26), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(26), + O => \dm_address_reg[27]_1\ + ); +\dm_address[24]_i_8__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(25), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(25), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(25), + O => \dm_address_reg[27]_0\ + ); +\dm_address[24]_i_9__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(24), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(24), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(24), + O => \dm_address_reg[27]\ + ); +\dm_address[28]_i_6__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(31), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(31), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(31), + O => \dm_address_reg[31]_2\ + ); +\dm_address[28]_i_7__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(30), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(30), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(30), + O => \dm_address_reg[31]_1\ + ); +\dm_address[28]_i_8__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(29), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(29), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(29), + O => \dm_address_reg[31]_0\ + ); +\dm_address[28]_i_9__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(28), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(28), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(28), + O => \dm_address_reg[31]\ + ); +\dm_address[4]_i_10__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(7), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(7), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(7), + O => \dm_address[4]_i_10__0_n_0\ + ); +\dm_address[4]_i_11__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(6), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(6), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(6), + O => \dm_address[4]_i_11__0_n_0\ + ); +\dm_address[4]_i_12__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(5), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(5), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(5), + O => \dm_address[4]_i_12__0_n_0\ + ); +\dm_address[4]_i_13__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(4), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(4), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(4), + O => \dm_address[4]_i_13__0_n_0\ + ); +\dm_address[4]_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(7), + I1 => load_new_addr, + O => \dm_address[4]_i_2__0_n_0\ + ); +\dm_address[4]_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(6), + I1 => load_new_addr, + O => \dm_address[4]_i_3__0_n_0\ + ); +\dm_address[4]_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(5), + I1 => load_new_addr, + O => \dm_address[4]_i_4__0_n_0\ + ); +\dm_address[4]_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(4), + I1 => load_new_addr, + O => \dm_address[4]_i_5__0_n_0\ + ); +\dm_address[4]_i_6__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(7), + I1 => \dm_address_reg[15]_0\(7), + I2 => load_new_addr, + I3 => \dm_address[4]_i_10__0_n_0\, + O => \dm_address[4]_i_6__0_n_0\ + ); +\dm_address[4]_i_7__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(6), + I1 => \dm_address_reg[15]_0\(6), + I2 => load_new_addr, + I3 => \dm_address[4]_i_11__0_n_0\, + O => \dm_address[4]_i_7__0_n_0\ + ); +\dm_address[4]_i_8__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(5), + I1 => \dm_address_reg[15]_0\(5), + I2 => load_new_addr, + I3 => \dm_address[4]_i_12__0_n_0\, + O => \dm_address[4]_i_8__0_n_0\ + ); +\dm_address[4]_i_9__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(4), + I1 => \dm_address_reg[15]_0\(4), + I2 => load_new_addr, + I3 => \dm_address[4]_i_13__0_n_0\, + O => \dm_address[4]_i_9__0_n_0\ + ); +\dm_address[8]_i_10__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(11), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(11), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(11), + O => \dm_address[8]_i_10__0_n_0\ + ); +\dm_address[8]_i_11__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(10), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(10), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(10), + O => \dm_address[8]_i_11__0_n_0\ + ); +\dm_address[8]_i_12__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(9), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(9), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(9), + O => \dm_address[8]_i_12__0_n_0\ + ); +\dm_address[8]_i_13__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(8), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(8), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(8), + O => \dm_address[8]_i_13__0_n_0\ + ); +\dm_address[8]_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(11), + I1 => load_new_addr, + O => \dm_address[8]_i_2__0_n_0\ + ); +\dm_address[8]_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(10), + I1 => load_new_addr, + O => \dm_address[8]_i_3__0_n_0\ + ); +\dm_address[8]_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(9), + I1 => load_new_addr, + O => \dm_address[8]_i_4__0_n_0\ + ); +\dm_address[8]_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(8), + I1 => load_new_addr, + O => \dm_address[8]_i_5__0_n_0\ + ); +\dm_address[8]_i_6__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(11), + I1 => \dm_address_reg[15]_0\(11), + I2 => load_new_addr, + I3 => \dm_address[8]_i_10__0_n_0\, + O => \dm_address[8]_i_6__0_n_0\ + ); +\dm_address[8]_i_7__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(10), + I1 => \dm_address_reg[15]_0\(10), + I2 => load_new_addr, + I3 => \dm_address[8]_i_11__0_n_0\, + O => \dm_address[8]_i_7__0_n_0\ + ); +\dm_address[8]_i_8__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(9), + I1 => \dm_address_reg[15]_0\(9), + I2 => load_new_addr, + I3 => \dm_address[8]_i_12__0_n_0\, + O => \dm_address[8]_i_8__0_n_0\ + ); +\dm_address[8]_i_9__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(8), + I1 => \dm_address_reg[15]_0\(8), + I2 => load_new_addr, + I3 => \dm_address[8]_i_13__0_n_0\, + O => \dm_address[8]_i_9__0_n_0\ + ); +\dm_address_reg[0]_i_2__0\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \dm_address_reg[0]_i_2__0_n_0\, + CO(2) => \dm_address_reg[0]_i_2__0_n_1\, + CO(1) => \dm_address_reg[0]_i_2__0_n_2\, + CO(0) => \dm_address_reg[0]_i_2__0_n_3\, + CYINIT => '0', + DI(3) => \dm_address[0]_i_3__0_n_0\, + DI(2) => \dm_address[0]_i_4__0_n_0\, + DI(1) => \dm_address[0]_i_5__0_n_0\, + DI(0) => \dm_address[0]_i_6__0_n_0\, + O(3 downto 0) => O(3 downto 0), + S(3) => \dm_address[0]_i_7__0_n_0\, + S(2) => \dm_address[0]_i_8__0_n_0\, + S(1) => \dm_address[0]_i_9__0_n_0\, + S(0) => \dm_address[0]_i_10__0_n_0\ + ); +\dm_address_reg[12]_i_1__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \dm_address_reg[8]_i_1__0_n_0\, + CO(3) => CO(0), + CO(2) => \dm_address_reg[12]_i_1__0_n_1\, + CO(1) => \dm_address_reg[12]_i_1__0_n_2\, + CO(0) => \dm_address_reg[12]_i_1__0_n_3\, + CYINIT => '0', + DI(3) => \dm_address[12]_i_2__0_n_0\, + DI(2) => \dm_address[12]_i_3__0_n_0\, + DI(1) => \dm_address[12]_i_4__0_n_0\, + DI(0) => \dm_address[12]_i_5__0_n_0\, + O(3 downto 0) => \dm_address_reg[15]\(3 downto 0), + S(3) => \dm_address[12]_i_6__0_n_0\, + S(2) => \dm_address[12]_i_7__0_n_0\, + S(1) => \dm_address[12]_i_8__0_n_0\, + S(0) => \dm_address[12]_i_9__0_n_0\ + ); +\dm_address_reg[4]_i_1__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \dm_address_reg[0]_i_2__0_n_0\, + CO(3) => \dm_address_reg[4]_i_1__0_n_0\, + CO(2) => \dm_address_reg[4]_i_1__0_n_1\, + CO(1) => \dm_address_reg[4]_i_1__0_n_2\, + CO(0) => \dm_address_reg[4]_i_1__0_n_3\, + CYINIT => '0', + DI(3) => \dm_address[4]_i_2__0_n_0\, + DI(2) => \dm_address[4]_i_3__0_n_0\, + DI(1) => \dm_address[4]_i_4__0_n_0\, + DI(0) => \dm_address[4]_i_5__0_n_0\, + O(3 downto 0) => \dm_address_reg[7]\(3 downto 0), + S(3) => \dm_address[4]_i_6__0_n_0\, + S(2) => \dm_address[4]_i_7__0_n_0\, + S(1) => \dm_address[4]_i_8__0_n_0\, + S(0) => \dm_address[4]_i_9__0_n_0\ + ); +\dm_address_reg[8]_i_1__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \dm_address_reg[4]_i_1__0_n_0\, + CO(3) => \dm_address_reg[8]_i_1__0_n_0\, + CO(2) => \dm_address_reg[8]_i_1__0_n_1\, + CO(1) => \dm_address_reg[8]_i_1__0_n_2\, + CO(0) => \dm_address_reg[8]_i_1__0_n_3\, + CYINIT => '0', + DI(3) => \dm_address[8]_i_2__0_n_0\, + DI(2) => \dm_address[8]_i_3__0_n_0\, + DI(1) => \dm_address[8]_i_4__0_n_0\, + DI(0) => \dm_address[8]_i_5__0_n_0\, + O(3 downto 0) => \dm_address_reg[11]\(3 downto 0), + S(3) => \dm_address[8]_i_6__0_n_0\, + S(2) => \dm_address[8]_i_7__0_n_0\, + S(1) => \dm_address[8]_i_8__0_n_0\, + S(0) => \dm_address[8]_i_9__0_n_0\ + ); +\hsize_vid_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(0), + Q => \^q\(0), + R => SR(0) + ); +\hsize_vid_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(10), + Q => \^q\(10), + R => SR(0) + ); +\hsize_vid_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(11), + Q => \^q\(11), + R => SR(0) + ); +\hsize_vid_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(12), + Q => \^q\(12), + R => SR(0) + ); +\hsize_vid_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(13), + Q => \^q\(13), + R => SR(0) + ); +\hsize_vid_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(14), + Q => \^q\(14), + R => SR(0) + ); +\hsize_vid_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(15), + Q => \^q\(15), + R => SR(0) + ); +\hsize_vid_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(1), + Q => \^q\(1), + R => SR(0) + ); +\hsize_vid_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(2), + Q => \^q\(2), + R => SR(0) + ); +\hsize_vid_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(3), + Q => \^q\(3), + R => SR(0) + ); +\hsize_vid_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(4), + Q => \^q\(4), + R => SR(0) + ); +\hsize_vid_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(5), + Q => \^q\(5), + R => SR(0) + ); +\hsize_vid_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(6), + Q => \^q\(6), + R => SR(0) + ); +\hsize_vid_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(7), + Q => \^q\(7), + R => SR(0) + ); +\hsize_vid_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(8), + Q => \^q\(8), + R => SR(0) + ); +\hsize_vid_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(9), + Q => \^q\(9), + R => SR(0) + ); +\stride_vid_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(0), + Q => stride_vid(0), + R => SR(0) + ); +\stride_vid_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(10), + Q => stride_vid(10), + R => SR(0) + ); +\stride_vid_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(11), + Q => stride_vid(11), + R => SR(0) + ); +\stride_vid_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(12), + Q => stride_vid(12), + R => SR(0) + ); +\stride_vid_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(13), + Q => stride_vid(13), + R => SR(0) + ); +\stride_vid_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(14), + Q => stride_vid(14), + R => SR(0) + ); +\stride_vid_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(15), + Q => stride_vid(15), + R => SR(0) + ); +\stride_vid_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(1), + Q => stride_vid(1), + R => SR(0) + ); +\stride_vid_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(2), + Q => stride_vid(2), + R => SR(0) + ); +\stride_vid_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(3), + Q => stride_vid(3), + R => SR(0) + ); +\stride_vid_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(4), + Q => stride_vid(4), + R => SR(0) + ); +\stride_vid_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(5), + Q => stride_vid(5), + R => SR(0) + ); +\stride_vid_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(6), + Q => stride_vid(6), + R => SR(0) + ); +\stride_vid_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(7), + Q => stride_vid(7), + R => SR(0) + ); +\stride_vid_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(8), + Q => stride_vid(8), + R => SR(0) + ); +\stride_vid_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(9), + Q => stride_vid(9), + R => SR(0) + ); +\vsize_vid[12]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8A" + ) + port map ( + I0 => prmtr_update_complete, + I1 => s2mm_cdc2dmac_fsync, + I2 => \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\, + O => video_reg_update + ); +\vsize_vid_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \reg_module_vsize_reg[12]\(0), + Q => \^gen_s2mm_flush_sof_logic.gen_for_async_flush_sof.crnt_vsize_cdc_tig_reg[12]\(0), + R => SR(0) + ); +\vsize_vid_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \reg_module_vsize_reg[12]\(10), + Q => \^gen_s2mm_flush_sof_logic.gen_for_async_flush_sof.crnt_vsize_cdc_tig_reg[12]\(10), + R => SR(0) + ); +\vsize_vid_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \reg_module_vsize_reg[12]\(11), + Q => \^gen_s2mm_flush_sof_logic.gen_for_async_flush_sof.crnt_vsize_cdc_tig_reg[12]\(11), + R => SR(0) + ); +\vsize_vid_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \reg_module_vsize_reg[12]\(12), + Q => \^gen_s2mm_flush_sof_logic.gen_for_async_flush_sof.crnt_vsize_cdc_tig_reg[12]\(12), + R => SR(0) + ); +\vsize_vid_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \reg_module_vsize_reg[12]\(1), + Q => \^gen_s2mm_flush_sof_logic.gen_for_async_flush_sof.crnt_vsize_cdc_tig_reg[12]\(1), + R => SR(0) + ); +\vsize_vid_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \reg_module_vsize_reg[12]\(2), + Q => \^gen_s2mm_flush_sof_logic.gen_for_async_flush_sof.crnt_vsize_cdc_tig_reg[12]\(2), + R => SR(0) + ); +\vsize_vid_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \reg_module_vsize_reg[12]\(3), + Q => \^gen_s2mm_flush_sof_logic.gen_for_async_flush_sof.crnt_vsize_cdc_tig_reg[12]\(3), + R => SR(0) + ); +\vsize_vid_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \reg_module_vsize_reg[12]\(4), + Q => \^gen_s2mm_flush_sof_logic.gen_for_async_flush_sof.crnt_vsize_cdc_tig_reg[12]\(4), + R => SR(0) + ); +\vsize_vid_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \reg_module_vsize_reg[12]\(5), + Q => \^gen_s2mm_flush_sof_logic.gen_for_async_flush_sof.crnt_vsize_cdc_tig_reg[12]\(5), + R => SR(0) + ); +\vsize_vid_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \reg_module_vsize_reg[12]\(6), + Q => \^gen_s2mm_flush_sof_logic.gen_for_async_flush_sof.crnt_vsize_cdc_tig_reg[12]\(6), + R => SR(0) + ); +\vsize_vid_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \reg_module_vsize_reg[12]\(7), + Q => \^gen_s2mm_flush_sof_logic.gen_for_async_flush_sof.crnt_vsize_cdc_tig_reg[12]\(7), + R => SR(0) + ); +\vsize_vid_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \reg_module_vsize_reg[12]\(8), + Q => \^gen_s2mm_flush_sof_logic.gen_for_async_flush_sof.crnt_vsize_cdc_tig_reg[12]\(8), + R => SR(0) + ); +\vsize_vid_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => video_reg_update, + D => \reg_module_vsize_reg[12]\(9), + Q => \^gen_s2mm_flush_sof_logic.gen_for_async_flush_sof.crnt_vsize_cdc_tig_reg[12]\(9), + R => SR(0) + ); +\zero_hsize_err_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000002" + ) + port map ( + I0 => \zero_hsize_err_i_2__0_n_0\, + I1 => \zero_hsize_err_i_3__0_n_0\, + I2 => \^q\(11), + I3 => \^q\(4), + I4 => \^q\(13), + O => zero_hsize_err0 + ); +\zero_hsize_err_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000100" + ) + port map ( + I0 => \^q\(8), + I1 => \^q\(12), + I2 => \^q\(7), + I3 => load_new_addr, + I4 => \^q\(15), + I5 => \^q\(9), + O => \zero_hsize_err_i_2__0_n_0\ + ); +\zero_hsize_err_i_3__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => \^q\(5), + I1 => \^q\(1), + I2 => \^q\(10), + I3 => \^q\(3), + I4 => \zero_hsize_err_i_4__0_n_0\, + O => \zero_hsize_err_i_3__0_n_0\ + ); +\zero_hsize_err_i_4__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \^q\(6), + I1 => \^q\(14), + I2 => \^q\(0), + I3 => \^q\(2), + O => \zero_hsize_err_i_4__0_n_0\ + ); +\zero_vsize_err_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000002" + ) + port map ( + I0 => \zero_vsize_err_i_2__0_n_0\, + I1 => \zero_vsize_err_i_3__0_n_0\, + I2 => \^gen_s2mm_flush_sof_logic.gen_for_async_flush_sof.crnt_vsize_cdc_tig_reg[12]\(10), + I3 => \^gen_s2mm_flush_sof_logic.gen_for_async_flush_sof.crnt_vsize_cdc_tig_reg[12]\(6), + I4 => \^gen_s2mm_flush_sof_logic.gen_for_async_flush_sof.crnt_vsize_cdc_tig_reg[12]\(12), + I5 => \^gen_s2mm_flush_sof_logic.gen_for_async_flush_sof.crnt_vsize_cdc_tig_reg[12]\(7), + O => zero_vsize_err0 + ); +\zero_vsize_err_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000004" + ) + port map ( + I0 => \^gen_s2mm_flush_sof_logic.gen_for_async_flush_sof.crnt_vsize_cdc_tig_reg[12]\(0), + I1 => load_new_addr, + I2 => \^gen_s2mm_flush_sof_logic.gen_for_async_flush_sof.crnt_vsize_cdc_tig_reg[12]\(5), + I3 => \^gen_s2mm_flush_sof_logic.gen_for_async_flush_sof.crnt_vsize_cdc_tig_reg[12]\(8), + I4 => \^gen_s2mm_flush_sof_logic.gen_for_async_flush_sof.crnt_vsize_cdc_tig_reg[12]\(2), + I5 => \^gen_s2mm_flush_sof_logic.gen_for_async_flush_sof.crnt_vsize_cdc_tig_reg[12]\(4), + O => \zero_vsize_err_i_2__0_n_0\ + ); +\zero_vsize_err_i_3__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \^gen_s2mm_flush_sof_logic.gen_for_async_flush_sof.crnt_vsize_cdc_tig_reg[12]\(9), + I1 => \^gen_s2mm_flush_sof_logic.gen_for_async_flush_sof.crnt_vsize_cdc_tig_reg[12]\(3), + I2 => \^gen_s2mm_flush_sof_logic.gen_for_async_flush_sof.crnt_vsize_cdc_tig_reg[12]\(11), + I3 => \^gen_s2mm_flush_sof_logic.gen_for_async_flush_sof.crnt_vsize_cdc_tig_reg[12]\(1), + O => \zero_vsize_err_i_3__0_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_vregister_44 is + port ( + zero_vsize_err0 : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 12 downto 0 ); + zero_hsize_err0 : out STD_LOGIC; + \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + \dm_address_reg[19]\ : out STD_LOGIC; + \dm_address_reg[19]_0\ : out STD_LOGIC; + \dm_address_reg[19]_1\ : out STD_LOGIC; + \dm_address_reg[19]_2\ : out STD_LOGIC; + \dm_address_reg[23]\ : out STD_LOGIC; + \dm_address_reg[23]_0\ : out STD_LOGIC; + \dm_address_reg[23]_1\ : out STD_LOGIC; + \dm_address_reg[23]_2\ : out STD_LOGIC; + \dm_address_reg[27]\ : out STD_LOGIC; + \dm_address_reg[27]_0\ : out STD_LOGIC; + \dm_address_reg[27]_1\ : out STD_LOGIC; + \dm_address_reg[27]_2\ : out STD_LOGIC; + \dm_address_reg[31]\ : out STD_LOGIC; + \dm_address_reg[31]_0\ : out STD_LOGIC; + \dm_address_reg[31]_1\ : out STD_LOGIC; + \dm_address_reg[31]_2\ : out STD_LOGIC; + O : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \dm_address_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \dm_address_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + CO : out STD_LOGIC_VECTOR ( 0 to 0 ); + \dm_address_reg[15]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + load_new_addr : in STD_LOGIC; + \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg\ : in STD_LOGIC; + p_24_out : in STD_LOGIC; + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\ : in STD_LOGIC; + \dm_address_reg[15]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + \reg_module_vsize_reg[12]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + \reg_module_hsize_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_vregister_44 : entity is "axi_vdma_vregister"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_vregister_44; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_vregister_44 is + signal \^gen_normal_dm_command.cmnd_data_reg[15]\ : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \^q\ : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal \dm_address[0]_i_10_n_0\ : STD_LOGIC; + signal \dm_address[0]_i_11_n_0\ : STD_LOGIC; + signal \dm_address[0]_i_12_n_0\ : STD_LOGIC; + signal \dm_address[0]_i_13_n_0\ : STD_LOGIC; + signal \dm_address[0]_i_14_n_0\ : STD_LOGIC; + signal \dm_address[0]_i_3_n_0\ : STD_LOGIC; + signal \dm_address[0]_i_4_n_0\ : STD_LOGIC; + signal \dm_address[0]_i_5_n_0\ : STD_LOGIC; + signal \dm_address[0]_i_6_n_0\ : STD_LOGIC; + signal \dm_address[0]_i_7_n_0\ : STD_LOGIC; + signal \dm_address[0]_i_8_n_0\ : STD_LOGIC; + signal \dm_address[0]_i_9_n_0\ : STD_LOGIC; + signal \dm_address[12]_i_10_n_0\ : STD_LOGIC; + signal \dm_address[12]_i_11_n_0\ : STD_LOGIC; + signal \dm_address[12]_i_12_n_0\ : STD_LOGIC; + signal \dm_address[12]_i_13_n_0\ : STD_LOGIC; + signal \dm_address[12]_i_2_n_0\ : STD_LOGIC; + signal \dm_address[12]_i_3_n_0\ : STD_LOGIC; + signal \dm_address[12]_i_4_n_0\ : STD_LOGIC; + signal \dm_address[12]_i_5_n_0\ : STD_LOGIC; + signal \dm_address[12]_i_6_n_0\ : STD_LOGIC; + signal \dm_address[12]_i_7_n_0\ : STD_LOGIC; + signal \dm_address[12]_i_8_n_0\ : STD_LOGIC; + signal \dm_address[12]_i_9_n_0\ : STD_LOGIC; + signal \dm_address[4]_i_10_n_0\ : STD_LOGIC; + signal \dm_address[4]_i_11_n_0\ : STD_LOGIC; + signal \dm_address[4]_i_12_n_0\ : STD_LOGIC; + signal \dm_address[4]_i_13_n_0\ : STD_LOGIC; + signal \dm_address[4]_i_2_n_0\ : STD_LOGIC; + signal \dm_address[4]_i_3_n_0\ : STD_LOGIC; + signal \dm_address[4]_i_4_n_0\ : STD_LOGIC; + signal \dm_address[4]_i_5_n_0\ : STD_LOGIC; + signal \dm_address[4]_i_6_n_0\ : STD_LOGIC; + signal \dm_address[4]_i_7_n_0\ : STD_LOGIC; + signal \dm_address[4]_i_8_n_0\ : STD_LOGIC; + signal \dm_address[4]_i_9_n_0\ : STD_LOGIC; + signal \dm_address[8]_i_10_n_0\ : STD_LOGIC; + signal \dm_address[8]_i_11_n_0\ : STD_LOGIC; + signal \dm_address[8]_i_12_n_0\ : STD_LOGIC; + signal \dm_address[8]_i_13_n_0\ : STD_LOGIC; + signal \dm_address[8]_i_2_n_0\ : STD_LOGIC; + signal \dm_address[8]_i_3_n_0\ : STD_LOGIC; + signal \dm_address[8]_i_4_n_0\ : STD_LOGIC; + signal \dm_address[8]_i_5_n_0\ : STD_LOGIC; + signal \dm_address[8]_i_6_n_0\ : STD_LOGIC; + signal \dm_address[8]_i_7_n_0\ : STD_LOGIC; + signal \dm_address[8]_i_8_n_0\ : STD_LOGIC; + signal \dm_address[8]_i_9_n_0\ : STD_LOGIC; + signal \dm_address_reg[0]_i_2_n_0\ : STD_LOGIC; + signal \dm_address_reg[0]_i_2_n_1\ : STD_LOGIC; + signal \dm_address_reg[0]_i_2_n_2\ : STD_LOGIC; + signal \dm_address_reg[0]_i_2_n_3\ : STD_LOGIC; + signal \dm_address_reg[12]_i_1_n_1\ : STD_LOGIC; + signal \dm_address_reg[12]_i_1_n_2\ : STD_LOGIC; + signal \dm_address_reg[12]_i_1_n_3\ : STD_LOGIC; + signal \dm_address_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \dm_address_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \dm_address_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \dm_address_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \dm_address_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \dm_address_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \dm_address_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \dm_address_reg[8]_i_1_n_3\ : STD_LOGIC; + signal stride_vid : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal video_reg_update : STD_LOGIC; + signal zero_hsize_err_i_2_n_0 : STD_LOGIC; + signal zero_hsize_err_i_3_n_0 : STD_LOGIC; + signal zero_hsize_err_i_4_n_0 : STD_LOGIC; + signal zero_vsize_err_i_2_n_0 : STD_LOGIC; + signal zero_vsize_err_i_3_n_0 : STD_LOGIC; + attribute METHODOLOGY_DRC_VIOS : string; + attribute METHODOLOGY_DRC_VIOS of \dm_address_reg[0]_i_2\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \dm_address_reg[12]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \dm_address_reg[4]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \dm_address_reg[8]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; +begin + \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15]\(15 downto 0) <= \^gen_normal_dm_command.cmnd_data_reg[15]\(15 downto 0); + Q(12 downto 0) <= \^q\(12 downto 0); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(0), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(0), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][10]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(10), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(10), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][11]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(11), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(11), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][12]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(12), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(12), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][13]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(13), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(13), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][14]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(14), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(14), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][15]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(15), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(15), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][16]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(16), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(16), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][17]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(17), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(17), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][18]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(18), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(18), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][19]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(19), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(19), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(1), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(1), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][20]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(20), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(20), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][21]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(21), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(21), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][22]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(22), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(22), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][23]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(23), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(23), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][24]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(24), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(24), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][25]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(25), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(25), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][26]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(26), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(26), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][27]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(27), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(27), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][28]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(28), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(28), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][29]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(29), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(29), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(2), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(2), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][30]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(30), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(30), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(31), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(31), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(3), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(3), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(4), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(4), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][5]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(5), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(5), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][6]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(6), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(6), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][7]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(7), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(7), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][8]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(8), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(8), + R => SR(0) + ); +\GEN_START_ADDR_REG[0].start_address_vid_reg[0][9]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(9), + Q => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(9), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(0), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(0), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][10]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(10), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(10), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][11]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(11), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(11), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][12]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(12), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(12), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][13]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(13), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(13), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][14]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(14), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(14), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][15]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(15), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(15), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][16]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(16), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(16), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][17]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(17), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(17), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][18]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(18), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(18), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][19]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(19), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(19), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(1), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(1), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][20]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(20), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(20), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][21]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(21), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(21), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][22]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(22), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(22), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][23]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(23), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(23), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][24]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(24), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(24), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][25]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(25), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(25), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][26]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(26), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(26), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][27]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(27), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(27), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][28]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(28), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(28), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][29]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(29), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(29), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(2), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(2), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][30]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(30), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(30), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(31), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(31), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(3), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(3), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(4), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(4), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][5]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(5), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(5), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][6]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(6), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(6), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][7]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(7), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(7), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][8]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(8), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(8), + R => SR(0) + ); +\GEN_START_ADDR_REG[1].start_address_vid_reg[1][9]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(9), + Q => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(9), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(0), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(0), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][10]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(10), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(10), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][11]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(11), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(11), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][12]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(12), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(12), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][13]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(13), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(13), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][14]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(14), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(14), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][15]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(15), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(15), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][16]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(16), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(16), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][17]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(17), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(17), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][18]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(18), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(18), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][19]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(19), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(19), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(1), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(1), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][20]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(20), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(20), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][21]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(21), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(21), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][22]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(22), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(22), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][23]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(23), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(23), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][24]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(24), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(24), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][25]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(25), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(25), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][26]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(26), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(26), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][27]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(27), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(27), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][28]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(28), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(28), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][29]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(29), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(29), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(2), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(2), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][30]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(30), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(30), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(31), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(31), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(3), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(3), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(4), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(4), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][5]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(5), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(5), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][6]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(6), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(6), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][7]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(7), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(7), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][8]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(8), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(8), + R => SR(0) + ); +\GEN_START_ADDR_REG[2].start_address_vid_reg[2][9]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(9), + Q => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(9), + R => SR(0) + ); +\dm_address[0]_i_10\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(0), + I1 => \dm_address_reg[15]_0\(0), + I2 => load_new_addr, + I3 => \dm_address[0]_i_14_n_0\, + O => \dm_address[0]_i_10_n_0\ + ); +\dm_address[0]_i_11\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(3), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(3), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(3), + O => \dm_address[0]_i_11_n_0\ + ); +\dm_address[0]_i_12\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(2), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(2), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(2), + O => \dm_address[0]_i_12_n_0\ + ); +\dm_address[0]_i_13\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(1), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(1), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(1), + O => \dm_address[0]_i_13_n_0\ + ); +\dm_address[0]_i_14\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(0), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(0), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(0), + O => \dm_address[0]_i_14_n_0\ + ); +\dm_address[0]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(3), + I1 => load_new_addr, + O => \dm_address[0]_i_3_n_0\ + ); +\dm_address[0]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(2), + I1 => load_new_addr, + O => \dm_address[0]_i_4_n_0\ + ); +\dm_address[0]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(1), + I1 => load_new_addr, + O => \dm_address[0]_i_5_n_0\ + ); +\dm_address[0]_i_6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(0), + I1 => load_new_addr, + O => \dm_address[0]_i_6_n_0\ + ); +\dm_address[0]_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(3), + I1 => \dm_address_reg[15]_0\(3), + I2 => load_new_addr, + I3 => \dm_address[0]_i_11_n_0\, + O => \dm_address[0]_i_7_n_0\ + ); +\dm_address[0]_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(2), + I1 => \dm_address_reg[15]_0\(2), + I2 => load_new_addr, + I3 => \dm_address[0]_i_12_n_0\, + O => \dm_address[0]_i_8_n_0\ + ); +\dm_address[0]_i_9\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(1), + I1 => \dm_address_reg[15]_0\(1), + I2 => load_new_addr, + I3 => \dm_address[0]_i_13_n_0\, + O => \dm_address[0]_i_9_n_0\ + ); +\dm_address[12]_i_10\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(15), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(15), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(15), + O => \dm_address[12]_i_10_n_0\ + ); +\dm_address[12]_i_11\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(14), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(14), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(14), + O => \dm_address[12]_i_11_n_0\ + ); +\dm_address[12]_i_12\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(13), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(13), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(13), + O => \dm_address[12]_i_12_n_0\ + ); +\dm_address[12]_i_13\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(12), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(12), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(12), + O => \dm_address[12]_i_13_n_0\ + ); +\dm_address[12]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(15), + I1 => load_new_addr, + O => \dm_address[12]_i_2_n_0\ + ); +\dm_address[12]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(14), + I1 => load_new_addr, + O => \dm_address[12]_i_3_n_0\ + ); +\dm_address[12]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(13), + I1 => load_new_addr, + O => \dm_address[12]_i_4_n_0\ + ); +\dm_address[12]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(12), + I1 => load_new_addr, + O => \dm_address[12]_i_5_n_0\ + ); +\dm_address[12]_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(15), + I1 => \dm_address_reg[15]_0\(15), + I2 => load_new_addr, + I3 => \dm_address[12]_i_10_n_0\, + O => \dm_address[12]_i_6_n_0\ + ); +\dm_address[12]_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(14), + I1 => \dm_address_reg[15]_0\(14), + I2 => load_new_addr, + I3 => \dm_address[12]_i_11_n_0\, + O => \dm_address[12]_i_7_n_0\ + ); +\dm_address[12]_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(13), + I1 => \dm_address_reg[15]_0\(13), + I2 => load_new_addr, + I3 => \dm_address[12]_i_12_n_0\, + O => \dm_address[12]_i_8_n_0\ + ); +\dm_address[12]_i_9\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(12), + I1 => \dm_address_reg[15]_0\(12), + I2 => load_new_addr, + I3 => \dm_address[12]_i_13_n_0\, + O => \dm_address[12]_i_9_n_0\ + ); +\dm_address[16]_i_6\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(19), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(19), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(19), + O => \dm_address_reg[19]_2\ + ); +\dm_address[16]_i_7\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(18), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(18), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(18), + O => \dm_address_reg[19]_1\ + ); +\dm_address[16]_i_8\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(17), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(17), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(17), + O => \dm_address_reg[19]_0\ + ); +\dm_address[16]_i_9\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(16), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(16), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(16), + O => \dm_address_reg[19]\ + ); +\dm_address[20]_i_6\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(23), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(23), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(23), + O => \dm_address_reg[23]_2\ + ); +\dm_address[20]_i_7\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(22), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(22), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(22), + O => \dm_address_reg[23]_1\ + ); +\dm_address[20]_i_8\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(21), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(21), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(21), + O => \dm_address_reg[23]_0\ + ); +\dm_address[20]_i_9\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(20), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(20), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(20), + O => \dm_address_reg[23]\ + ); +\dm_address[24]_i_6\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(27), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(27), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(27), + O => \dm_address_reg[27]_2\ + ); +\dm_address[24]_i_7\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(26), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(26), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(26), + O => \dm_address_reg[27]_1\ + ); +\dm_address[24]_i_8\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(25), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(25), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(25), + O => \dm_address_reg[27]_0\ + ); +\dm_address[24]_i_9\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(24), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(24), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(24), + O => \dm_address_reg[27]\ + ); +\dm_address[28]_i_6\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(31), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(31), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(31), + O => \dm_address_reg[31]_2\ + ); +\dm_address[28]_i_7\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(30), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(30), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(30), + O => \dm_address_reg[31]_1\ + ); +\dm_address[28]_i_8\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(29), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(29), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(29), + O => \dm_address_reg[31]_0\ + ); +\dm_address[28]_i_9\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(28), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(28), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(28), + O => \dm_address_reg[31]\ + ); +\dm_address[4]_i_10\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(7), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(7), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(7), + O => \dm_address[4]_i_10_n_0\ + ); +\dm_address[4]_i_11\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(6), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(6), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(6), + O => \dm_address[4]_i_11_n_0\ + ); +\dm_address[4]_i_12\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(5), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(5), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(5), + O => \dm_address[4]_i_12_n_0\ + ); +\dm_address[4]_i_13\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(4), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(4), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(4), + O => \dm_address[4]_i_13_n_0\ + ); +\dm_address[4]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(7), + I1 => load_new_addr, + O => \dm_address[4]_i_2_n_0\ + ); +\dm_address[4]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(6), + I1 => load_new_addr, + O => \dm_address[4]_i_3_n_0\ + ); +\dm_address[4]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(5), + I1 => load_new_addr, + O => \dm_address[4]_i_4_n_0\ + ); +\dm_address[4]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(4), + I1 => load_new_addr, + O => \dm_address[4]_i_5_n_0\ + ); +\dm_address[4]_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(7), + I1 => \dm_address_reg[15]_0\(7), + I2 => load_new_addr, + I3 => \dm_address[4]_i_10_n_0\, + O => \dm_address[4]_i_6_n_0\ + ); +\dm_address[4]_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(6), + I1 => \dm_address_reg[15]_0\(6), + I2 => load_new_addr, + I3 => \dm_address[4]_i_11_n_0\, + O => \dm_address[4]_i_7_n_0\ + ); +\dm_address[4]_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(5), + I1 => \dm_address_reg[15]_0\(5), + I2 => load_new_addr, + I3 => \dm_address[4]_i_12_n_0\, + O => \dm_address[4]_i_8_n_0\ + ); +\dm_address[4]_i_9\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(4), + I1 => \dm_address_reg[15]_0\(4), + I2 => load_new_addr, + I3 => \dm_address[4]_i_13_n_0\, + O => \dm_address[4]_i_9_n_0\ + ); +\dm_address[8]_i_10\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(11), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(11), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(11), + O => \dm_address[8]_i_10_n_0\ + ); +\dm_address[8]_i_11\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(10), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(10), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(10), + O => \dm_address[8]_i_11_n_0\ + ); +\dm_address[8]_i_12\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(9), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(9), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(9), + O => \dm_address[8]_i_12_n_0\ + ); +\dm_address[8]_i_13\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1]_1\(8), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(0), + I2 => \GEN_START_ADDR_REG[2].start_address_vid_reg[2]_0\(8), + I3 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1), + I4 => \GEN_START_ADDR_REG[0].start_address_vid_reg[0]_2\(8), + O => \dm_address[8]_i_13_n_0\ + ); +\dm_address[8]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(11), + I1 => load_new_addr, + O => \dm_address[8]_i_2_n_0\ + ); +\dm_address[8]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(10), + I1 => load_new_addr, + O => \dm_address[8]_i_3_n_0\ + ); +\dm_address[8]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(9), + I1 => load_new_addr, + O => \dm_address[8]_i_4_n_0\ + ); +\dm_address[8]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => stride_vid(8), + I1 => load_new_addr, + O => \dm_address[8]_i_5_n_0\ + ); +\dm_address[8]_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(11), + I1 => \dm_address_reg[15]_0\(11), + I2 => load_new_addr, + I3 => \dm_address[8]_i_10_n_0\, + O => \dm_address[8]_i_6_n_0\ + ); +\dm_address[8]_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(10), + I1 => \dm_address_reg[15]_0\(10), + I2 => load_new_addr, + I3 => \dm_address[8]_i_11_n_0\, + O => \dm_address[8]_i_7_n_0\ + ); +\dm_address[8]_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(9), + I1 => \dm_address_reg[15]_0\(9), + I2 => load_new_addr, + I3 => \dm_address[8]_i_12_n_0\, + O => \dm_address[8]_i_8_n_0\ + ); +\dm_address[8]_i_9\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F606" + ) + port map ( + I0 => stride_vid(8), + I1 => \dm_address_reg[15]_0\(8), + I2 => load_new_addr, + I3 => \dm_address[8]_i_13_n_0\, + O => \dm_address[8]_i_9_n_0\ + ); +\dm_address_reg[0]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \dm_address_reg[0]_i_2_n_0\, + CO(2) => \dm_address_reg[0]_i_2_n_1\, + CO(1) => \dm_address_reg[0]_i_2_n_2\, + CO(0) => \dm_address_reg[0]_i_2_n_3\, + CYINIT => '0', + DI(3) => \dm_address[0]_i_3_n_0\, + DI(2) => \dm_address[0]_i_4_n_0\, + DI(1) => \dm_address[0]_i_5_n_0\, + DI(0) => \dm_address[0]_i_6_n_0\, + O(3 downto 0) => O(3 downto 0), + S(3) => \dm_address[0]_i_7_n_0\, + S(2) => \dm_address[0]_i_8_n_0\, + S(1) => \dm_address[0]_i_9_n_0\, + S(0) => \dm_address[0]_i_10_n_0\ + ); +\dm_address_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \dm_address_reg[8]_i_1_n_0\, + CO(3) => CO(0), + CO(2) => \dm_address_reg[12]_i_1_n_1\, + CO(1) => \dm_address_reg[12]_i_1_n_2\, + CO(0) => \dm_address_reg[12]_i_1_n_3\, + CYINIT => '0', + DI(3) => \dm_address[12]_i_2_n_0\, + DI(2) => \dm_address[12]_i_3_n_0\, + DI(1) => \dm_address[12]_i_4_n_0\, + DI(0) => \dm_address[12]_i_5_n_0\, + O(3 downto 0) => \dm_address_reg[15]\(3 downto 0), + S(3) => \dm_address[12]_i_6_n_0\, + S(2) => \dm_address[12]_i_7_n_0\, + S(1) => \dm_address[12]_i_8_n_0\, + S(0) => \dm_address[12]_i_9_n_0\ + ); +\dm_address_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \dm_address_reg[0]_i_2_n_0\, + CO(3) => \dm_address_reg[4]_i_1_n_0\, + CO(2) => \dm_address_reg[4]_i_1_n_1\, + CO(1) => \dm_address_reg[4]_i_1_n_2\, + CO(0) => \dm_address_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3) => \dm_address[4]_i_2_n_0\, + DI(2) => \dm_address[4]_i_3_n_0\, + DI(1) => \dm_address[4]_i_4_n_0\, + DI(0) => \dm_address[4]_i_5_n_0\, + O(3 downto 0) => \dm_address_reg[7]\(3 downto 0), + S(3) => \dm_address[4]_i_6_n_0\, + S(2) => \dm_address[4]_i_7_n_0\, + S(1) => \dm_address[4]_i_8_n_0\, + S(0) => \dm_address[4]_i_9_n_0\ + ); +\dm_address_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \dm_address_reg[4]_i_1_n_0\, + CO(3) => \dm_address_reg[8]_i_1_n_0\, + CO(2) => \dm_address_reg[8]_i_1_n_1\, + CO(1) => \dm_address_reg[8]_i_1_n_2\, + CO(0) => \dm_address_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3) => \dm_address[8]_i_2_n_0\, + DI(2) => \dm_address[8]_i_3_n_0\, + DI(1) => \dm_address[8]_i_4_n_0\, + DI(0) => \dm_address[8]_i_5_n_0\, + O(3 downto 0) => \dm_address_reg[11]\(3 downto 0), + S(3) => \dm_address[8]_i_6_n_0\, + S(2) => \dm_address[8]_i_7_n_0\, + S(1) => \dm_address[8]_i_8_n_0\, + S(0) => \dm_address[8]_i_9_n_0\ + ); +\hsize_vid_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(0), + Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(0), + R => SR(0) + ); +\hsize_vid_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(10), + Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(10), + R => SR(0) + ); +\hsize_vid_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(11), + Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(11), + R => SR(0) + ); +\hsize_vid_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(12), + Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(12), + R => SR(0) + ); +\hsize_vid_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(13), + Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(13), + R => SR(0) + ); +\hsize_vid_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(14), + Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(14), + R => SR(0) + ); +\hsize_vid_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(15), + Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(15), + R => SR(0) + ); +\hsize_vid_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(1), + Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(1), + R => SR(0) + ); +\hsize_vid_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(2), + Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(2), + R => SR(0) + ); +\hsize_vid_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(3), + Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(3), + R => SR(0) + ); +\hsize_vid_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(4), + Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(4), + R => SR(0) + ); +\hsize_vid_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(5), + Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(5), + R => SR(0) + ); +\hsize_vid_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(6), + Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(6), + R => SR(0) + ); +\hsize_vid_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(7), + Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(7), + R => SR(0) + ); +\hsize_vid_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(8), + Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(8), + R => SR(0) + ); +\hsize_vid_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \reg_module_hsize_reg[15]\(9), + Q => \^gen_normal_dm_command.cmnd_data_reg[15]\(9), + R => SR(0) + ); +\stride_vid_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(0), + Q => stride_vid(0), + R => SR(0) + ); +\stride_vid_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(10), + Q => stride_vid(10), + R => SR(0) + ); +\stride_vid_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(11), + Q => stride_vid(11), + R => SR(0) + ); +\stride_vid_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(12), + Q => stride_vid(12), + R => SR(0) + ); +\stride_vid_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(13), + Q => stride_vid(13), + R => SR(0) + ); +\stride_vid_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(14), + Q => stride_vid(14), + R => SR(0) + ); +\stride_vid_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(15), + Q => stride_vid(15), + R => SR(0) + ); +\stride_vid_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(1), + Q => stride_vid(1), + R => SR(0) + ); +\stride_vid_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(2), + Q => stride_vid(2), + R => SR(0) + ); +\stride_vid_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(3), + Q => stride_vid(3), + R => SR(0) + ); +\stride_vid_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(4), + Q => stride_vid(4), + R => SR(0) + ); +\stride_vid_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(5), + Q => stride_vid(5), + R => SR(0) + ); +\stride_vid_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(6), + Q => stride_vid(6), + R => SR(0) + ); +\stride_vid_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(7), + Q => stride_vid(7), + R => SR(0) + ); +\stride_vid_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(8), + Q => stride_vid(8), + R => SR(0) + ); +\stride_vid_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(9), + Q => stride_vid(9), + R => SR(0) + ); +\vsize_vid[12]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8A" + ) + port map ( + I0 => \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg\, + I1 => p_24_out, + I2 => \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\, + O => video_reg_update + ); +\vsize_vid_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \reg_module_vsize_reg[12]\(0), + Q => \^q\(0), + R => SR(0) + ); +\vsize_vid_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \reg_module_vsize_reg[12]\(10), + Q => \^q\(10), + R => SR(0) + ); +\vsize_vid_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \reg_module_vsize_reg[12]\(11), + Q => \^q\(11), + R => SR(0) + ); +\vsize_vid_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \reg_module_vsize_reg[12]\(12), + Q => \^q\(12), + R => SR(0) + ); +\vsize_vid_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \reg_module_vsize_reg[12]\(1), + Q => \^q\(1), + R => SR(0) + ); +\vsize_vid_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \reg_module_vsize_reg[12]\(2), + Q => \^q\(2), + R => SR(0) + ); +\vsize_vid_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \reg_module_vsize_reg[12]\(3), + Q => \^q\(3), + R => SR(0) + ); +\vsize_vid_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \reg_module_vsize_reg[12]\(4), + Q => \^q\(4), + R => SR(0) + ); +\vsize_vid_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \reg_module_vsize_reg[12]\(5), + Q => \^q\(5), + R => SR(0) + ); +\vsize_vid_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \reg_module_vsize_reg[12]\(6), + Q => \^q\(6), + R => SR(0) + ); +\vsize_vid_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \reg_module_vsize_reg[12]\(7), + Q => \^q\(7), + R => SR(0) + ); +\vsize_vid_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \reg_module_vsize_reg[12]\(8), + Q => \^q\(8), + R => SR(0) + ); +\vsize_vid_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => video_reg_update, + D => \reg_module_vsize_reg[12]\(9), + Q => \^q\(9), + R => SR(0) + ); +zero_hsize_err_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000002" + ) + port map ( + I0 => zero_hsize_err_i_2_n_0, + I1 => zero_hsize_err_i_3_n_0, + I2 => \^gen_normal_dm_command.cmnd_data_reg[15]\(7), + I3 => \^gen_normal_dm_command.cmnd_data_reg[15]\(10), + I4 => \^gen_normal_dm_command.cmnd_data_reg[15]\(0), + O => zero_hsize_err0 + ); +zero_hsize_err_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000001" + ) + port map ( + I0 => \^gen_normal_dm_command.cmnd_data_reg[15]\(13), + I1 => \^gen_normal_dm_command.cmnd_data_reg[15]\(4), + I2 => \^gen_normal_dm_command.cmnd_data_reg[15]\(6), + I3 => \^gen_normal_dm_command.cmnd_data_reg[15]\(15), + I4 => \^gen_normal_dm_command.cmnd_data_reg[15]\(9), + I5 => \^gen_normal_dm_command.cmnd_data_reg[15]\(14), + O => zero_hsize_err_i_2_n_0 + ); +zero_hsize_err_i_3: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFEFF" + ) + port map ( + I0 => \^gen_normal_dm_command.cmnd_data_reg[15]\(1), + I1 => \^gen_normal_dm_command.cmnd_data_reg[15]\(8), + I2 => \^gen_normal_dm_command.cmnd_data_reg[15]\(11), + I3 => load_new_addr, + I4 => zero_hsize_err_i_4_n_0, + O => zero_hsize_err_i_3_n_0 + ); +zero_hsize_err_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \^gen_normal_dm_command.cmnd_data_reg[15]\(12), + I1 => \^gen_normal_dm_command.cmnd_data_reg[15]\(3), + I2 => \^gen_normal_dm_command.cmnd_data_reg[15]\(5), + I3 => \^gen_normal_dm_command.cmnd_data_reg[15]\(2), + O => zero_hsize_err_i_4_n_0 + ); +zero_vsize_err_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000002" + ) + port map ( + I0 => zero_vsize_err_i_2_n_0, + I1 => zero_vsize_err_i_3_n_0, + I2 => \^q\(4), + I3 => \^q\(1), + I4 => \^q\(12), + I5 => \^q\(3), + O => zero_vsize_err0 + ); +zero_vsize_err_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000004" + ) + port map ( + I0 => \^q\(0), + I1 => load_new_addr, + I2 => \^q\(10), + I3 => \^q\(11), + I4 => \^q\(2), + I5 => \^q\(7), + O => zero_vsize_err_i_2_n_0 + ); +zero_vsize_err_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \^q\(9), + I1 => \^q\(8), + I2 => \^q\(6), + I3 => \^q\(5), + O => zero_vsize_err_i_3_n_0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_cdc_sync is + port ( + p_in_d1_cdc_from : out STD_LOGIC; + p_1_out : out STD_LOGIC; + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + prmry_in_xored : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC; + p_3_out : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_cdc_sync : entity is "cdc_sync"; +end Arty_Z7_20_axi_vdma_0_0_cdc_sync; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_cdc_sync is + signal \^p_1_out\ : STD_LOGIC; + signal \^p_in_d1_cdc_from\ : STD_LOGIC; + signal s_out_d1_cdc_to : STD_LOGIC; + signal s_out_d2 : STD_LOGIC; + signal s_out_d3 : STD_LOGIC; + signal s_out_d4 : STD_LOGIC; + signal s_out_d5 : STD_LOGIC; + signal \s_out_re__0\ : STD_LOGIC; + signal srst_d1 : STD_LOGIC; + signal srst_d2 : STD_LOGIC; + signal srst_d3 : STD_LOGIC; + signal srst_d4 : STD_LOGIC; + signal srst_d5 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "PRIMITIVE"; +begin + p_1_out <= \^p_1_out\; + p_in_d1_cdc_from <= \^p_in_d1_cdc_from\; +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_out_d1_cdc_to, + Q => s_out_d2, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_out_d2, + Q => s_out_d3, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_out_d3, + Q => s_out_d4, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_out_d4, + Q => s_out_d5, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => \s_out_re__0\, + Q => \^p_1_out\, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => \^p_in_d1_cdc_from\, + Q => s_out_d1_cdc_to, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => prmry_in_xored, + Q => \^p_in_d1_cdc_from\, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => '1', + Q => srst_d1, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => srst_d1, + Q => srst_d2, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => srst_d2, + Q => srst_d3, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => srst_d3, + Q => srst_d4, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => srst_d4, + Q => srst_d5, + R => '0' + ); +\GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^p_1_out\, + I1 => p_3_out, + O => SR(0) + ); +s_out_re: unisim.vcomponents.LUT3 + generic map( + INIT => X"28" + ) + port map ( + I0 => srst_d5, + I1 => s_out_d5, + I2 => s_out_d4, + O => \s_out_re__0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_cdc_sync_10 is + port ( + p_in_d1_cdc_from : out STD_LOGIC; + p_4_out : out STD_LOGIC; + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + prmry_in_xored : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + s_axi_lite_aclk : in STD_LOGIC; + p_6_out : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_cdc_sync_10 : entity is "cdc_sync"; +end Arty_Z7_20_axi_vdma_0_0_cdc_sync_10; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_cdc_sync_10 is + signal \^p_4_out\ : STD_LOGIC; + signal \^p_in_d1_cdc_from\ : STD_LOGIC; + signal s_out_d1_cdc_to : STD_LOGIC; + signal s_out_d2 : STD_LOGIC; + signal s_out_d3 : STD_LOGIC; + signal s_out_d4 : STD_LOGIC; + signal s_out_d5 : STD_LOGIC; + signal \s_out_re__0\ : STD_LOGIC; + signal srst_d1 : STD_LOGIC; + signal srst_d2 : STD_LOGIC; + signal srst_d3 : STD_LOGIC; + signal srst_d4 : STD_LOGIC; + signal srst_d5 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "PRIMITIVE"; +begin + p_4_out <= \^p_4_out\; + p_in_d1_cdc_from <= \^p_in_d1_cdc_from\; +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_out_d1_cdc_to, + Q => s_out_d2, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_out_d2, + Q => s_out_d3, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_out_d3, + Q => s_out_d4, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_out_d4, + Q => s_out_d5, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \s_out_re__0\, + Q => \^p_4_out\, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \^p_in_d1_cdc_from\, + Q => s_out_d1_cdc_to, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => prmry_in_xored, + Q => \^p_in_d1_cdc_from\, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '1', + Q => srst_d1, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => srst_d1, + Q => srst_d2, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => srst_d2, + Q => srst_d3, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => srst_d3, + Q => srst_d4, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => srst_d4, + Q => srst_d5, + R => '0' + ); +\GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^p_4_out\, + I1 => p_6_out, + O => SR(0) + ); +s_out_re: unisim.vcomponents.LUT3 + generic map( + INIT => X"28" + ) + port map ( + I0 => srst_d5, + I1 => s_out_d5, + I2 => s_out_d4, + O => \s_out_re__0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_cdc_sync_13 is + port ( + p_6_out : out STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + s_axi_lite_aclk : in STD_LOGIC; + s_soft_reset_i_d1 : in STD_LOGIC; + s_soft_reset_i : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_cdc_sync_13 : entity is "cdc_sync"; +end Arty_Z7_20_axi_vdma_0_0_cdc_sync_13; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_cdc_sync_13 is + signal p_in_d1_cdc_from : STD_LOGIC; + signal prmry_in_xored : STD_LOGIC; + signal s_out_d1_cdc_to : STD_LOGIC; + signal s_out_d2 : STD_LOGIC; + signal s_out_d3 : STD_LOGIC; + signal s_out_d4 : STD_LOGIC; + signal s_out_d5 : STD_LOGIC; + signal \s_out_re__0\ : STD_LOGIC; + signal srst_d1 : STD_LOGIC; + signal srst_d2 : STD_LOGIC; + signal srst_d3 : STD_LOGIC; + signal srst_d4 : STD_LOGIC; + signal srst_d5 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "PRIMITIVE"; +begin +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_out_d1_cdc_to, + Q => s_out_d2, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_out_d2, + Q => s_out_d3, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_out_d3, + Q => s_out_d4, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_out_d4, + Q => s_out_d5, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \s_out_re__0\, + Q => p_6_out, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => p_in_d1_cdc_from, + Q => s_out_d1_cdc_to, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => prmry_in_xored, + Q => p_in_d1_cdc_from, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B4" + ) + port map ( + I0 => s_soft_reset_i_d1, + I1 => s_soft_reset_i, + I2 => p_in_d1_cdc_from, + O => prmry_in_xored + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '1', + Q => srst_d1, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => srst_d1, + Q => srst_d2, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => srst_d2, + Q => srst_d3, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => srst_d3, + Q => srst_d4, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => srst_d4, + Q => srst_d5, + R => '0' + ); +s_out_re: unisim.vcomponents.LUT3 + generic map( + INIT => X"28" + ) + port map ( + I0 => srst_d5, + I1 => s_out_d5, + I2 => s_out_d4, + O => \s_out_re__0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_cdc_sync_3 is + port ( + p_3_out : out STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC; + s_soft_reset_i_d1 : in STD_LOGIC; + s_soft_reset_i : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_cdc_sync_3 : entity is "cdc_sync"; +end Arty_Z7_20_axi_vdma_0_0_cdc_sync_3; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_cdc_sync_3 is + signal p_in_d1_cdc_from : STD_LOGIC; + signal prmry_in_xored : STD_LOGIC; + signal s_out_d1_cdc_to : STD_LOGIC; + signal s_out_d2 : STD_LOGIC; + signal s_out_d3 : STD_LOGIC; + signal s_out_d4 : STD_LOGIC; + signal s_out_d5 : STD_LOGIC; + signal \s_out_re__0\ : STD_LOGIC; + signal srst_d1 : STD_LOGIC; + signal srst_d2 : STD_LOGIC; + signal srst_d3 : STD_LOGIC; + signal srst_d4 : STD_LOGIC; + signal srst_d5 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "PRIMITIVE"; +begin +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_out_d1_cdc_to, + Q => s_out_d2, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_out_d2, + Q => s_out_d3, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_out_d3, + Q => s_out_d4, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_out_d4, + Q => s_out_d5, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => \s_out_re__0\, + Q => p_3_out, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => p_in_d1_cdc_from, + Q => s_out_d1_cdc_to, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => prmry_in_xored, + Q => p_in_d1_cdc_from, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B4" + ) + port map ( + I0 => s_soft_reset_i_d1, + I1 => s_soft_reset_i, + I2 => p_in_d1_cdc_from, + O => prmry_in_xored + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => '1', + Q => srst_d1, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => srst_d1, + Q => srst_d2, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => srst_d2, + Q => srst_d3, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => srst_d3, + Q => srst_d4, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => srst_d4, + Q => srst_d5, + R => '0' + ); +s_out_re: unisim.vcomponents.LUT3 + generic map( + INIT => X"28" + ) + port map ( + I0 => srst_d5, + I1 => s_out_d5, + I2 => s_out_d4, + O => \s_out_re__0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_cdc_sync_4 is + port ( + p_in_d1_cdc_from : out STD_LOGIC; + p_4_out : out STD_LOGIC; + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + prmry_in_xored : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + s_axi_lite_aclk : in STD_LOGIC; + p_6_out : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_cdc_sync_4 : entity is "cdc_sync"; +end Arty_Z7_20_axi_vdma_0_0_cdc_sync_4; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_cdc_sync_4 is + signal \^p_4_out\ : STD_LOGIC; + signal \^p_in_d1_cdc_from\ : STD_LOGIC; + signal s_out_d1_cdc_to : STD_LOGIC; + signal s_out_d2 : STD_LOGIC; + signal s_out_d3 : STD_LOGIC; + signal s_out_d4 : STD_LOGIC; + signal s_out_d5 : STD_LOGIC; + signal \s_out_re__0\ : STD_LOGIC; + signal srst_d1 : STD_LOGIC; + signal srst_d2 : STD_LOGIC; + signal srst_d3 : STD_LOGIC; + signal srst_d4 : STD_LOGIC; + signal srst_d5 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "PRIMITIVE"; +begin + p_4_out <= \^p_4_out\; + p_in_d1_cdc_from <= \^p_in_d1_cdc_from\; +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_out_d1_cdc_to, + Q => s_out_d2, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_out_d2, + Q => s_out_d3, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_out_d3, + Q => s_out_d4, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_out_d4, + Q => s_out_d5, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \s_out_re__0\, + Q => \^p_4_out\, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \^p_in_d1_cdc_from\, + Q => s_out_d1_cdc_to, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => prmry_in_xored, + Q => \^p_in_d1_cdc_from\, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '1', + Q => srst_d1, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => srst_d1, + Q => srst_d2, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => srst_d2, + Q => srst_d3, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => srst_d3, + Q => srst_d4, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => srst_d4, + Q => srst_d5, + R => '0' + ); +\GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^p_4_out\, + I1 => p_6_out, + O => SR(0) + ); +s_out_re: unisim.vcomponents.LUT3 + generic map( + INIT => X"28" + ) + port map ( + I0 => srst_d5, + I1 => s_out_d5, + I2 => s_out_d4, + O => \s_out_re__0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_cdc_sync_5 is + port ( + p_6_out : out STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + s_axi_lite_aclk : in STD_LOGIC; + s_soft_reset_i_d1 : in STD_LOGIC; + s_soft_reset_i : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_cdc_sync_5 : entity is "cdc_sync"; +end Arty_Z7_20_axi_vdma_0_0_cdc_sync_5; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_cdc_sync_5 is + signal p_in_d1_cdc_from : STD_LOGIC; + signal prmry_in_xored : STD_LOGIC; + signal s_out_d1_cdc_to : STD_LOGIC; + signal s_out_d2 : STD_LOGIC; + signal s_out_d3 : STD_LOGIC; + signal s_out_d4 : STD_LOGIC; + signal s_out_d5 : STD_LOGIC; + signal \s_out_re__0\ : STD_LOGIC; + signal srst_d1 : STD_LOGIC; + signal srst_d2 : STD_LOGIC; + signal srst_d3 : STD_LOGIC; + signal srst_d4 : STD_LOGIC; + signal srst_d5 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "PRIMITIVE"; +begin +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_out_d1_cdc_to, + Q => s_out_d2, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_out_d2, + Q => s_out_d3, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_out_d3, + Q => s_out_d4, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_out_d4, + Q => s_out_d5, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \s_out_re__0\, + Q => p_6_out, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => p_in_d1_cdc_from, + Q => s_out_d1_cdc_to, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => prmry_in_xored, + Q => p_in_d1_cdc_from, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B4" + ) + port map ( + I0 => s_soft_reset_i_d1, + I1 => s_soft_reset_i, + I2 => p_in_d1_cdc_from, + O => prmry_in_xored + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '1', + Q => srst_d1, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => srst_d1, + Q => srst_d2, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => srst_d2, + Q => srst_d3, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => srst_d3, + Q => srst_d4, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => srst_d4, + Q => srst_d5, + R => '0' + ); +s_out_re: unisim.vcomponents.LUT3 + generic map( + INIT => X"28" + ) + port map ( + I0 => srst_d5, + I1 => s_out_d5, + I2 => s_out_d4, + O => \s_out_re__0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_cdc_sync_6 is + port ( + p_in_d1_cdc_from : out STD_LOGIC; + p_1_out : out STD_LOGIC; + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + prmry_in_xored : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + m_axis_mm2s_aclk : in STD_LOGIC; + p_3_out : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_cdc_sync_6 : entity is "cdc_sync"; +end Arty_Z7_20_axi_vdma_0_0_cdc_sync_6; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_cdc_sync_6 is + signal \^p_1_out\ : STD_LOGIC; + signal \^p_in_d1_cdc_from\ : STD_LOGIC; + signal s_out_d1_cdc_to : STD_LOGIC; + signal s_out_d2 : STD_LOGIC; + signal s_out_d3 : STD_LOGIC; + signal s_out_d4 : STD_LOGIC; + signal s_out_d5 : STD_LOGIC; + signal \s_out_re__0\ : STD_LOGIC; + signal srst_d1 : STD_LOGIC; + signal srst_d2 : STD_LOGIC; + signal srst_d3 : STD_LOGIC; + signal srst_d4 : STD_LOGIC; + signal srst_d5 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "PRIMITIVE"; +begin + p_1_out <= \^p_1_out\; + p_in_d1_cdc_from <= \^p_in_d1_cdc_from\; +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => s_out_d1_cdc_to, + Q => s_out_d2, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => s_out_d2, + Q => s_out_d3, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => s_out_d3, + Q => s_out_d4, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => s_out_d4, + Q => s_out_d5, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => \s_out_re__0\, + Q => \^p_1_out\, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => \^p_in_d1_cdc_from\, + Q => s_out_d1_cdc_to, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => prmry_in_xored, + Q => \^p_in_d1_cdc_from\, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => '1', + Q => srst_d1, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => srst_d1, + Q => srst_d2, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => srst_d2, + Q => srst_d3, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => srst_d3, + Q => srst_d4, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => srst_d4, + Q => srst_d5, + R => '0' + ); +\GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^p_1_out\, + I1 => p_3_out, + O => SR(0) + ); +s_out_re: unisim.vcomponents.LUT3 + generic map( + INIT => X"28" + ) + port map ( + I0 => srst_d5, + I1 => s_out_d5, + I2 => s_out_d4, + O => \s_out_re__0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_cdc_sync_9 is + port ( + p_3_out : out STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + m_axis_mm2s_aclk : in STD_LOGIC; + s_soft_reset_i_d1 : in STD_LOGIC; + s_soft_reset_i : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_cdc_sync_9 : entity is "cdc_sync"; +end Arty_Z7_20_axi_vdma_0_0_cdc_sync_9; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_cdc_sync_9 is + signal p_in_d1_cdc_from : STD_LOGIC; + signal prmry_in_xored : STD_LOGIC; + signal s_out_d1_cdc_to : STD_LOGIC; + signal s_out_d2 : STD_LOGIC; + signal s_out_d3 : STD_LOGIC; + signal s_out_d4 : STD_LOGIC; + signal s_out_d5 : STD_LOGIC; + signal \s_out_re__0\ : STD_LOGIC; + signal srst_d1 : STD_LOGIC; + signal srst_d2 : STD_LOGIC; + signal srst_d3 : STD_LOGIC; + signal srst_d4 : STD_LOGIC; + signal srst_d5 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "PRIMITIVE"; +begin +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => s_out_d1_cdc_to, + Q => s_out_d2, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => s_out_d2, + Q => s_out_d3, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => s_out_d3, + Q => s_out_d4, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => s_out_d4, + Q => s_out_d5, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => \s_out_re__0\, + Q => p_3_out, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => p_in_d1_cdc_from, + Q => s_out_d1_cdc_to, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => prmry_in_xored, + Q => p_in_d1_cdc_from, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B4" + ) + port map ( + I0 => s_soft_reset_i_d1, + I1 => s_soft_reset_i, + I2 => p_in_d1_cdc_from, + O => prmry_in_xored + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => '1', + Q => srst_d1, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => srst_d1, + Q => srst_d2, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => srst_d2, + Q => srst_d3, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => srst_d3, + Q => srst_d4, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => srst_d4, + Q => srst_d5, + R => '0' + ); +s_out_re: unisim.vcomponents.LUT3 + generic map( + INIT => X"28" + ) + port map ( + I0 => srst_d5, + I1 => s_out_d5, + I2 => s_out_d4, + O => \s_out_re__0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized0\ is + port ( + scndry_out : out STD_LOGIC; + s_axi_lite_aclk : in STD_LOGIC; + \cmnds_queued_reg[0]\ : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized0\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized0\ is + signal p_level_in_d1_cdc_from : STD_LOGIC; + signal s_level_out_d1_cdc_to : STD_LOGIC; + signal s_level_out_d2 : STD_LOGIC; + signal s_level_out_d3 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; +begin +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => p_level_in_d1_cdc_from, + Q => s_level_out_d1_cdc_to, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_level_out_d1_cdc_to, + Q => s_level_out_d2, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_level_out_d2, + Q => s_level_out_d3, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_level_out_d3, + Q => scndry_out, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \cmnds_queued_reg[0]\, + Q => p_level_in_d1_cdc_from, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized0_11\ is + port ( + scndry_out : out STD_LOGIC; + s_axi_lite_aclk : in STD_LOGIC; + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\ : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized0_11\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized0_11\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized0_11\ is + signal p_level_in_d1_cdc_from : STD_LOGIC; + signal s_level_out_d1_cdc_to : STD_LOGIC; + signal s_level_out_d2 : STD_LOGIC; + signal s_level_out_d3 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; +begin +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => p_level_in_d1_cdc_from, + Q => s_level_out_d1_cdc_to, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_level_out_d1_cdc_to, + Q => s_level_out_d2, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_level_out_d2, + Q => s_level_out_d3, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_level_out_d3, + Q => scndry_out, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\, + Q => p_level_in_d1_cdc_from, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized1\ is + port ( + prmry_in_xored : out STD_LOGIC; + scndry_out : out STD_LOGIC; + prmry_in_xored_0 : out STD_LOGIC; + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_reg\ : out STD_LOGIC; + prmry_min_assert_sftrst : in STD_LOGIC; + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\ : in STD_LOGIC; + p_in_d1_cdc_from : in STD_LOGIC; + p_in_d1_cdc_from_1 : in STD_LOGIC; + s_soft_reset_i_d1 : in STD_LOGIC; + s_soft_reset_i : in STD_LOGIC; + p_11_out : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + lite_min_assert_sftrst : in STD_LOGIC; + s_axi_lite_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized1\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized1\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized1\ is + signal p_level_in_d1_cdc_from : STD_LOGIC; + signal s_level_out_d1_cdc_to : STD_LOGIC; + signal s_level_out_d2 : STD_LOGIC; + signal s_level_out_d3 : STD_LOGIC; + signal \^scndry_out\ : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__4\ : label is "soft_lutpair264"; + attribute SOFT_HLUTNM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__6\ : label is "soft_lutpair264"; +begin + scndry_out <= \^scndry_out\; +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => p_level_in_d1_cdc_from, + Q => s_level_out_d1_cdc_to, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_level_out_d1_cdc_to, + Q => s_level_out_d2, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_level_out_d2, + Q => s_level_out_d3, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_level_out_d3, + Q => \^scndry_out\, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => lite_min_assert_sftrst, + Q => p_level_in_d1_cdc_from, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \^scndry_out\, + I1 => prmry_min_assert_sftrst, + I2 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\, + I3 => p_in_d1_cdc_from, + O => prmry_in_xored + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \^scndry_out\, + I1 => prmry_min_assert_sftrst, + I2 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\, + I3 => p_in_d1_cdc_from_1, + O => prmry_in_xored_0 + ); +\GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00FFF2F2FFFFF2F2" + ) + port map ( + I0 => s_soft_reset_i, + I1 => s_soft_reset_i_d1, + I2 => p_11_out, + I3 => \^scndry_out\, + I4 => prmry_min_assert_sftrst, + I5 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\, + O => \GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_reg\ + ); +\GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80FF8080" + ) + port map ( + I0 => \^scndry_out\, + I1 => prmry_min_assert_sftrst, + I2 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\, + I3 => s_soft_reset_i_d1, + I4 => s_soft_reset_i, + O => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized12\ is + port ( + p_in_d1_cdc_from : out STD_LOGIC; + s2mm_packet_sof : out STD_LOGIC; + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[0]\ : out STD_LOGIC; + prmry_reset2 : in STD_LOGIC; + prmry_in_xored_1 : in STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_s2mm_aclk : in STD_LOGIC; + reset_counts : in STD_LOGIC; + s2mm_cdc2dmac_fsync : in STD_LOGIC; + irqdelay_wren_i : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized12\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized12\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized12\ is + signal \^p_in_d1_cdc_from\ : STD_LOGIC; + signal \^s2mm_packet_sof\ : STD_LOGIC; + signal s_out_d1_cdc_to : STD_LOGIC; + signal s_out_d2 : STD_LOGIC; + signal s_out_d3 : STD_LOGIC; + signal s_out_d4 : STD_LOGIC; + signal s_out_d5 : STD_LOGIC; + signal \s_out_re__0\ : STD_LOGIC; + signal srst_d1 : STD_LOGIC; + signal srst_d2 : STD_LOGIC; + signal srst_d3 : STD_LOGIC; + signal srst_d4 : STD_LOGIC; + signal srst_d5 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "PRIMITIVE"; +begin + p_in_d1_cdc_from <= \^p_in_d1_cdc_from\; + s2mm_packet_sof <= \^s2mm_packet_sof\; +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_out_d1_cdc_to, + Q => s_out_d2, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_out_d2, + Q => s_out_d3, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_out_d3, + Q => s_out_d4, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_out_d4, + Q => s_out_d5, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \s_out_re__0\, + Q => \^s2mm_packet_sof\, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \^p_in_d1_cdc_from\, + Q => s_out_d1_cdc_to, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => prmry_in_xored_1, + Q => \^p_in_d1_cdc_from\, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => '1', + Q => srst_d1, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => srst_d1, + Q => srst_d2, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => srst_d2, + Q => srst_d3, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => srst_d3, + Q => srst_d4, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => srst_d4, + Q => srst_d5, + R => SR(0) + ); +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \^s2mm_packet_sof\, + I1 => reset_counts, + I2 => s2mm_cdc2dmac_fsync, + I3 => irqdelay_wren_i, + O => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[0]\ + ); +s_out_re: unisim.vcomponents.LUT3 + generic map( + INIT => X"28" + ) + port map ( + I0 => srst_d5, + I1 => s_out_d5, + I2 => s_out_d4, + O => \s_out_re__0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized12_38\ is + port ( + p_in_d1_cdc_from : out STD_LOGIC; + p_17_out : out STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + prmry_in_xored : in STD_LOGIC; + m_axis_mm2s_aclk : in STD_LOGIC; + prmry_resetn_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized12_38\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized12_38\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized12_38\ is + signal \^p_in_d1_cdc_from\ : STD_LOGIC; + signal s_out_d1_cdc_to : STD_LOGIC; + signal s_out_d2 : STD_LOGIC; + signal s_out_d3 : STD_LOGIC; + signal s_out_d4 : STD_LOGIC; + signal s_out_d5 : STD_LOGIC; + signal \s_out_re__0\ : STD_LOGIC; + signal srst_d1 : STD_LOGIC; + signal srst_d2 : STD_LOGIC; + signal srst_d3 : STD_LOGIC; + signal srst_d4 : STD_LOGIC; + signal srst_d5 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "PRIMITIVE"; +begin + p_in_d1_cdc_from <= \^p_in_d1_cdc_from\; +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => s_out_d1_cdc_to, + Q => s_out_d2, + R => prmry_resetn_i_reg(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => s_out_d2, + Q => s_out_d3, + R => prmry_resetn_i_reg(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => s_out_d3, + Q => s_out_d4, + R => prmry_resetn_i_reg(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => s_out_d4, + Q => s_out_d5, + R => prmry_resetn_i_reg(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \s_out_re__0\, + Q => p_17_out, + R => prmry_resetn_i_reg(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \^p_in_d1_cdc_from\, + Q => s_out_d1_cdc_to, + R => prmry_resetn_i_reg(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => prmry_in_xored, + Q => \^p_in_d1_cdc_from\, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => '1', + Q => srst_d1, + R => prmry_resetn_i_reg(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => srst_d1, + Q => srst_d2, + R => prmry_resetn_i_reg(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => srst_d2, + Q => srst_d3, + R => prmry_resetn_i_reg(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => srst_d3, + Q => srst_d4, + R => prmry_resetn_i_reg(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => srst_d4, + Q => srst_d5, + R => prmry_resetn_i_reg(0) + ); +s_out_re: unisim.vcomponents.LUT3 + generic map( + INIT => X"28" + ) + port map ( + I0 => srst_d5, + I1 => s_out_d5, + I2 => s_out_d4, + O => \s_out_re__0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized13\ is + port ( + s2mm_cdc2dmac_fsync : out STD_LOGIC; + s2mm_valid_frame_sync_cmb : out STD_LOGIC; + prmry_reset2 : in STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_s2mm_aclk : in STD_LOGIC; + s2mm_valid_video_prmtrs : in STD_LOGIC; + s_fsync_d1 : in STD_LOGIC; + s_fsync_d2 : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized13\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized13\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized13\ is + signal p_in_d1_cdc_from : STD_LOGIC; + signal prmry_in_xored : STD_LOGIC; + signal \^s2mm_cdc2dmac_fsync\ : STD_LOGIC; + signal s_out_d1_cdc_to : STD_LOGIC; + signal s_out_d2 : STD_LOGIC; + signal s_out_d3 : STD_LOGIC; + signal s_out_d4 : STD_LOGIC; + signal s_out_d5 : STD_LOGIC; + signal \s_out_re__0\ : STD_LOGIC; + signal srst_d1 : STD_LOGIC; + signal srst_d2 : STD_LOGIC; + signal srst_d3 : STD_LOGIC; + signal srst_d4 : STD_LOGIC; + signal srst_d5 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "PRIMITIVE"; +begin + s2mm_cdc2dmac_fsync <= \^s2mm_cdc2dmac_fsync\; +\DYNAMIC_MASTER_MODE_FRAME_CNT.valid_frame_sync_d1_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s2mm_cdc2dmac_fsync\, + I1 => s2mm_valid_video_prmtrs, + O => s2mm_valid_frame_sync_cmb + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_out_d1_cdc_to, + Q => s_out_d2, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_out_d2, + Q => s_out_d3, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_out_d3, + Q => s_out_d4, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_out_d4, + Q => s_out_d5, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \s_out_re__0\, + Q => \^s2mm_cdc2dmac_fsync\, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => p_in_d1_cdc_from, + Q => s_out_d1_cdc_to, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => prmry_in_xored, + Q => p_in_d1_cdc_from, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__16\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B4" + ) + port map ( + I0 => s_fsync_d1, + I1 => s_fsync_d2, + I2 => p_in_d1_cdc_from, + O => prmry_in_xored + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => '1', + Q => srst_d1, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => srst_d1, + Q => srst_d2, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => srst_d2, + Q => srst_d3, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => srst_d3, + Q => srst_d4, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => srst_d4, + Q => srst_d5, + R => SR(0) + ); +s_out_re: unisim.vcomponents.LUT3 + generic map( + INIT => X"28" + ) + port map ( + I0 => srst_d5, + I1 => s_out_d5, + I2 => s_out_d4, + O => \s_out_re__0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized14\ is + port ( + p_in_d1_cdc_from_0 : out STD_LOGIC; + s2mm_fsync_out_i : out STD_LOGIC; + prmry_in_xored : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + prmry_in_xored_2 : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + prmry_reset2 : in STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC; + p_in_d1_cdc_from_3 : in STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\ : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out_0\ : in STD_LOGIC; + M_Last : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized14\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized14\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized14\ is + signal \^p_in_d1_cdc_from_0\ : STD_LOGIC; + signal \^s2mm_fsync_out_i\ : STD_LOGIC; + signal s_out_d1_cdc_to : STD_LOGIC; + signal s_out_d2 : STD_LOGIC; + signal s_out_d3 : STD_LOGIC; + signal s_out_d4 : STD_LOGIC; + signal s_out_d5 : STD_LOGIC; + signal \s_out_re__0\ : STD_LOGIC; + signal srst_d1 : STD_LOGIC; + signal srst_d2 : STD_LOGIC; + signal srst_d3 : STD_LOGIC; + signal srst_d4 : STD_LOGIC; + signal srst_d5 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "PRIMITIVE"; +begin + p_in_d1_cdc_from_0 <= \^p_in_d1_cdc_from_0\; + s2mm_fsync_out_i <= \^s2mm_fsync_out_i\; +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_out_d1_cdc_to, + Q => s_out_d2, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_out_d2, + Q => s_out_d3, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_out_d3, + Q => s_out_d4, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_out_d4, + Q => s_out_d5, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => \s_out_re__0\, + Q => \^s2mm_fsync_out_i\, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => \^p_in_d1_cdc_from_0\, + Q => s_out_d1_cdc_to, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => prmry_in_xored_2, + Q => \^p_in_d1_cdc_from_0\, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__9\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^s2mm_fsync_out_i\, + I1 => p_in_d1_cdc_from_3, + O => prmry_in_xored + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => '1', + Q => srst_d1, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => srst_d1, + Q => srst_d2, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => srst_d2, + Q => srst_d3, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => srst_d3, + Q => srst_d4, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => srst_d4, + Q => srst_d5, + R => prmry_reset2 + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAFEAAAA" + ) + port map ( + I0 => \^s2mm_fsync_out_i\, + I1 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\, + I2 => Q(0), + I3 => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out_0\, + I4 => M_Last, + O => E(0) + ); +s_out_re: unisim.vcomponents.LUT3 + generic map( + INIT => X"28" + ) + port map ( + I0 => srst_d5, + I1 => s_out_d5, + I2 => s_out_d4, + O => \s_out_re__0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized14_37\ is + port ( + p_in_d1_cdc_from_0 : out STD_LOGIC; + p_15_out : out STD_LOGIC; + all_lines_xfred : out STD_LOGIC; + prmry_resetn_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + prmry_in_xored_1 : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axis_mm2s_aclk : in STD_LOGIC; + \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized14_37\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized14_37\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized14_37\ is + signal \^p_15_out\ : STD_LOGIC; + signal \^p_in_d1_cdc_from_0\ : STD_LOGIC; + signal s_out_d1_cdc_to : STD_LOGIC; + signal s_out_d2 : STD_LOGIC; + signal s_out_d3 : STD_LOGIC; + signal s_out_d4 : STD_LOGIC; + signal s_out_d5 : STD_LOGIC; + signal \s_out_re__0\ : STD_LOGIC; + signal srst_d1 : STD_LOGIC; + signal srst_d2 : STD_LOGIC; + signal srst_d3 : STD_LOGIC; + signal srst_d4 : STD_LOGIC; + signal srst_d5 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "PRIMITIVE"; +begin + p_15_out <= \^p_15_out\; + p_in_d1_cdc_from_0 <= \^p_in_d1_cdc_from_0\; +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => s_out_d1_cdc_to, + Q => s_out_d2, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => s_out_d2, + Q => s_out_d3, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => s_out_d3, + Q => s_out_d4, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => s_out_d4, + Q => s_out_d5, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => \s_out_re__0\, + Q => \^p_15_out\, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => \^p_in_d1_cdc_from_0\, + Q => s_out_d1_cdc_to, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => prmry_in_xored_1, + Q => \^p_in_d1_cdc_from_0\, + R => prmry_resetn_i_reg(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => '1', + Q => srst_d1, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => srst_d1, + Q => srst_d2, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => srst_d2, + Q => srst_d3, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => srst_d3, + Q => srst_d4, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => srst_d4, + Q => srst_d5, + R => SR(0) + ); +\GEN_LINEBUF_NO_SOF.all_lines_xfred_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^p_15_out\, + I1 => \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]\, + O => all_lines_xfred + ); +s_out_re: unisim.vcomponents.LUT3 + generic map( + INIT => X"28" + ) + port map ( + I0 => srst_d5, + I1 => s_out_d5, + I2 => s_out_d4, + O => \s_out_re__0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized16\ is + port ( + mm2s_fifo_pipe_empty : out STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + scndry_reset2 : in STD_LOGIC; + \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg\ : in STD_LOGIC; + m_axis_mm2s_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized16\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized16\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized16\ is + signal p_level_in_d1_cdc_from : STD_LOGIC; + signal s_level_out_d1_cdc_to : STD_LOGIC; + signal s_level_out_d2 : STD_LOGIC; + signal s_level_out_d3 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; +begin +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => p_level_in_d1_cdc_from, + Q => s_level_out_d1_cdc_to, + R => SR(0) + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => s_level_out_d1_cdc_to, + Q => s_level_out_d2, + R => SR(0) + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => s_level_out_d2, + Q => s_level_out_d3, + R => SR(0) + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => s_level_out_d3, + Q => mm2s_fifo_pipe_empty, + R => SR(0) + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg\, + Q => p_level_in_d1_cdc_from, + R => scndry_reset2 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized17\ is + port ( + mm2s_all_lines_xfred : out STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + scndry_reset2 : in STD_LOGIC; + \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg\ : in STD_LOGIC; + m_axis_mm2s_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized17\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized17\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized17\ is + signal p_level_in_d1_cdc_from : STD_LOGIC; + signal s_level_out_d1_cdc_to : STD_LOGIC; + signal s_level_out_d2 : STD_LOGIC; + signal s_level_out_d3 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; +begin +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => p_level_in_d1_cdc_from, + Q => s_level_out_d1_cdc_to, + R => SR(0) + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => s_level_out_d1_cdc_to, + Q => s_level_out_d2, + R => SR(0) + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => s_level_out_d2, + Q => s_level_out_d3, + R => SR(0) + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => s_level_out_d3, + Q => mm2s_all_lines_xfred, + R => SR(0) + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg\, + Q => p_level_in_d1_cdc_from, + R => scndry_reset2 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized1_12\ is + port ( + prmry_in_xored : out STD_LOGIC; + scndry_out : out STD_LOGIC; + prmry_in_xored_0 : out STD_LOGIC; + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_reg\ : out STD_LOGIC; + prmry_min_assert_sftrst : in STD_LOGIC; + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\ : in STD_LOGIC; + p_in_d1_cdc_from : in STD_LOGIC; + p_in_d1_cdc_from_1 : in STD_LOGIC; + s_soft_reset_i_d1 : in STD_LOGIC; + s_soft_reset_i : in STD_LOGIC; + p_11_out : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + lite_min_assert_sftrst : in STD_LOGIC; + s_axi_lite_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized1_12\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized1_12\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized1_12\ is + signal p_level_in_d1_cdc_from : STD_LOGIC; + signal s_level_out_d1_cdc_to : STD_LOGIC; + signal s_level_out_d2 : STD_LOGIC; + signal s_level_out_d3 : STD_LOGIC; + signal \^scndry_out\ : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__0\ : label is "soft_lutpair255"; + attribute SOFT_HLUTNM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__2\ : label is "soft_lutpair255"; +begin + scndry_out <= \^scndry_out\; +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => p_level_in_d1_cdc_from, + Q => s_level_out_d1_cdc_to, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => s_level_out_d1_cdc_to, + Q => s_level_out_d2, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => s_level_out_d2, + Q => s_level_out_d3, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => s_level_out_d3, + Q => \^scndry_out\, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => lite_min_assert_sftrst, + Q => p_level_in_d1_cdc_from, + R => '0' + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \^scndry_out\, + I1 => prmry_min_assert_sftrst, + I2 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\, + I3 => p_in_d1_cdc_from, + O => prmry_in_xored + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \^scndry_out\, + I1 => prmry_min_assert_sftrst, + I2 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\, + I3 => p_in_d1_cdc_from_1, + O => prmry_in_xored_0 + ); +\GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00FFF2F2FFFFF2F2" + ) + port map ( + I0 => s_soft_reset_i, + I1 => s_soft_reset_i_d1, + I2 => p_11_out, + I3 => \^scndry_out\, + I4 => prmry_min_assert_sftrst, + I5 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\, + O => \GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_reg\ + ); +\GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80FF8080" + ) + port map ( + I0 => \^scndry_out\, + I1 => prmry_min_assert_sftrst, + I2 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\, + I3 => s_soft_reset_i_d1, + I4 => s_soft_reset_i, + O => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized2\ is + port ( + \FSM_sequential_dmacntrl_cs_reg[2]\ : out STD_LOGIC; + scndry_out : out STD_LOGIC; + halt_i_reg : in STD_LOGIC; + s2mm_soft_reset : in STD_LOGIC; + dma_err : in STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC; + \cmnds_queued_reg[0]\ : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized2\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized2\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized2\ is + signal p_level_in_d1_cdc_from : STD_LOGIC; + signal s_level_out_d1_cdc_to : STD_LOGIC; + signal s_level_out_d2 : STD_LOGIC; + signal s_level_out_d3 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; +begin +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => p_level_in_d1_cdc_from, + Q => s_level_out_d1_cdc_to, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_level_out_d1_cdc_to, + Q => s_level_out_d2, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_level_out_d2, + Q => s_level_out_d3, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_level_out_d3, + Q => scndry_out, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \cmnds_queued_reg[0]\, + Q => p_level_in_d1_cdc_from, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_4__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => halt_i_reg, + I1 => s2mm_soft_reset, + I2 => dma_err, + O => \FSM_sequential_dmacntrl_cs_reg[2]\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized20\ is + port ( + sig_reset_reg_reg : out STD_LOGIC; + m_axis_fifo_ainit_nosync : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tready_d1_reg\ : out STD_LOGIC; + scndry_reset2 : in STD_LOGIC; + m_axis_mm2s_aclk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + mm2s_halt : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + mm2s_axis_resetn : in STD_LOGIC; + m_axis_mm2s_tready : in STD_LOGIC; + p_15_out : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized20\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized20\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized20\ is + signal p_level_in_d1_cdc_from : STD_LOGIC; + signal s_level_out_d1_cdc_to : STD_LOGIC; + signal s_level_out_d2 : STD_LOGIC; + signal s_level_out_d3 : STD_LOGIC; + signal \^sig_reset_reg_reg\ : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tready_d1_i_1\ : label is "soft_lutpair44"; + attribute SOFT_HLUTNM of \sig_data_reg_out[31]_i_1__1\ : label is "soft_lutpair44"; +begin + sig_reset_reg_reg <= \^sig_reset_reg_reg\; +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => p_level_in_d1_cdc_from, + Q => s_level_out_d1_cdc_to, + R => scndry_reset2 + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => s_level_out_d1_cdc_to, + Q => s_level_out_d2, + R => scndry_reset2 + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => s_level_out_d2, + Q => s_level_out_d3, + R => scndry_reset2 + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => s_level_out_d3, + Q => \^sig_reset_reg_reg\, + R => scndry_reset2 + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => mm2s_halt, + Q => p_level_in_d1_cdc_from, + R => SR(0) + ); +\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tready_d1_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0020" + ) + port map ( + I0 => m_axis_mm2s_tready, + I1 => \^sig_reset_reg_reg\, + I2 => mm2s_axis_resetn, + I3 => p_15_out, + O => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tready_d1_reg\ + ); +\sig_data_reg_out[31]_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^sig_reset_reg_reg\, + I1 => mm2s_axis_resetn, + O => m_axis_fifo_ainit_nosync + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized21\ is + port ( + p_in_d1_cdc_from : out STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_clr_flag1_reg\ : out STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + prmry_in_xored : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + prmry_reset2 : in STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC; + d_tready_before_fsync_clr_flag1 : in STD_LOGIC; + \out\ : in STD_LOGIC; + s2mm_dmasr_halted_s : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized21\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized21\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized21\ is + signal \^p_in_d1_cdc_from\ : STD_LOGIC; + signal s2mm_prmtr_updt_complete_s : STD_LOGIC; + signal s_out_d1_cdc_to : STD_LOGIC; + signal s_out_d2 : STD_LOGIC; + signal s_out_d3 : STD_LOGIC; + signal s_out_d4 : STD_LOGIC; + signal s_out_d5 : STD_LOGIC; + signal \s_out_re__0\ : STD_LOGIC; + signal srst_d1 : STD_LOGIC; + signal srst_d2 : STD_LOGIC; + signal srst_d3 : STD_LOGIC; + signal srst_d4 : STD_LOGIC; + signal srst_d5 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "PRIMITIVE"; +begin + p_in_d1_cdc_from <= \^p_in_d1_cdc_from\; +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_out_d1_cdc_to, + Q => s_out_d2, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_out_d2, + Q => s_out_d3, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_out_d3, + Q => s_out_d4, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_out_d4, + Q => s_out_d5, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => \s_out_re__0\, + Q => s2mm_prmtr_updt_complete_s, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => \^p_in_d1_cdc_from\, + Q => s_out_d1_cdc_to, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => prmry_in_xored, + Q => \^p_in_d1_cdc_from\, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => '1', + Q => srst_d1, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => srst_d1, + Q => srst_d2, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => srst_d2, + Q => srst_d3, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => srst_d3, + Q => srst_d4, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => srst_d4, + Q => srst_d5, + R => prmry_reset2 + ); +\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_clr_flag1_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF4F" + ) + port map ( + I0 => s2mm_prmtr_updt_complete_s, + I1 => d_tready_before_fsync_clr_flag1, + I2 => \out\, + I3 => s2mm_dmasr_halted_s, + O => \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_clr_flag1_reg\ + ); +s_out_re: unisim.vcomponents.LUT3 + generic map( + INIT => X"28" + ) + port map ( + I0 => srst_d5, + I1 => s_out_d5, + I2 => s_out_d4, + O => \s_out_re__0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized22\ is + port ( + s2mm_dmasr_halted_s : out STD_LOGIC; + prmry_reset2 : in STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + s2mm_dmasr : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized22\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized22\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized22\ is + signal p_level_in_d1_cdc_from : STD_LOGIC; + signal s_level_out_d1_cdc_to : STD_LOGIC; + signal s_level_out_d2 : STD_LOGIC; + signal s_level_out_d3 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; +begin +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => p_level_in_d1_cdc_from, + Q => s_level_out_d1_cdc_to, + R => prmry_reset2 + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_level_out_d1_cdc_to, + Q => s_level_out_d2, + R => prmry_reset2 + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_level_out_d2, + Q => s_level_out_d3, + R => prmry_reset2 + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_level_out_d3, + Q => s2mm_dmasr_halted_s, + R => prmry_reset2 + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s2mm_dmasr(0), + Q => p_level_in_d1_cdc_from, + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized23\ is + port ( + s2mm_fsize_more_or_sof_late : out STD_LOGIC; + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_0\ : out STD_LOGIC; + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_1\ : out STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_s2mm_aclk : in STD_LOGIC; + prmry_reset2 : in STD_LOGIC; + s2mm_fsize_more_or_sof_late_s : in STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\ : in STD_LOGIC; + d_tready_sof_late : in STD_LOGIC; + s2mm_tuser_to_fsync_out : in STD_LOGIC; + d_tready_before_fsync : in STD_LOGIC; + d_tready_before_fsync_clr_flag1 : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized23\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized23\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized23\ is + signal p_level_in_d1_cdc_from : STD_LOGIC; + signal s_level_out_d1_cdc_to : STD_LOGIC; + signal s_level_out_d2 : STD_LOGIC; + signal s_level_out_d3 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; +begin +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => p_level_in_d1_cdc_from, + Q => s_level_out_d1_cdc_to, + R => SR(0) + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_level_out_d1_cdc_to, + Q => s_level_out_d2, + R => SR(0) + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_level_out_d2, + Q => s_level_out_d3, + R => SR(0) + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_level_out_d3, + Q => s2mm_fsize_more_or_sof_late, + R => SR(0) + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s2mm_fsize_more_or_sof_late_s, + Q => p_level_in_d1_cdc_from, + R => prmry_reset2 + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_2__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\, + I1 => d_tready_sof_late, + I2 => s2mm_tuser_to_fsync_out, + O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_0\ + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => d_tready_before_fsync, + I1 => d_tready_before_fsync_clr_flag1, + O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_1\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized24\ is + port ( + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg\ : out STD_LOGIC; + halt_i0 : out STD_LOGIC; + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0\ : out STD_LOGIC; + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_irqthresh_decr_mask_sig_reg\ : out STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \dm_address_reg_0__s_port_]\ : out STD_LOGIC; + \vert_count_reg_0__s_port_]\ : out STD_LOGIC; + \vert_count_reg[0]_0\ : out STD_LOGIC; + \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[0]\ : out STD_LOGIC; + halted_set_i0 : out STD_LOGIC; + s2mm_ftchcmdsts_idle : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 4 downto 0 ); + \DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_reg\ : out STD_LOGIC; + O : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \vert_count_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \vert_count_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \vert_count_reg[12]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \dm_address_reg[19]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \dm_address_reg[23]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \dm_address_reg[27]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \dm_address_reg[31]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[63]\ : out STD_LOGIC; + \FSM_sequential_dmacntrl_cs_reg[0]\ : out STD_LOGIC; + \FSM_sequential_dmacntrl_cs_reg[1]\ : out STD_LOGIC; + \FSM_sequential_dmacntrl_cs_reg[2]\ : out STD_LOGIC; + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF.flag_to_repeat_after_fsize_less_err_reg\ : out STD_LOGIC; + write_cmnd_cmb : out STD_LOGIC; + prmry_reset2 : in STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_s2mm_aclk : in STD_LOGIC; + s2mm_stop : in STD_LOGIC; + run_stop_d1 : in STD_LOGIC; + s2mm_dmacr : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s2mm_soft_reset : in STD_LOGIC; + soft_reset_d1 : in STD_LOGIC; + fsize_mismatch_err_flag_int : in STD_LOGIC; + prmry_resetn_i_reg : in STD_LOGIC; + s2mm_tstvect_fsync : in STD_LOGIC; + ch2_delay_cnt_en : in STD_LOGIC; + s2mm_packet_sof : in STD_LOGIC; + ch2_irqthresh_decr_mask_sig : in STD_LOGIC; + s2mm_halt : in STD_LOGIC; + \out\ : in STD_LOGIC; + s2mm_cdc2dmac_fsync : in STD_LOGIC; + s2mm_fsync_out_m_i : in STD_LOGIC; + drop_fsync_d_pulse_gen_fsize_less_err_d1 : in STD_LOGIC; + fsize_mismatch_err_s1 : in STD_LOGIC; + \FSM_sequential_dmacntrl_cs_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\ : in STD_LOGIC; + dm_address_reg : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][30]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][29]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][28]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][27]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][26]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][25]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][24]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][23]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][22]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][21]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][20]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][19]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][18]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][17]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][16]\ : in STD_LOGIC; + s_axis_cmd_tvalid_reg : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 12 downto 0 ); + vert_count_reg : in STD_LOGIC_VECTOR ( 12 downto 0 ); + datamover_idle : in STD_LOGIC; + \cmnds_queued_reg[7]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \cmnds_queued_reg[1]\ : in STD_LOGIC; + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + flag_to_repeat_after_fsize_less_err : in STD_LOGIC; + \GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + halt_i_reg : in STD_LOGIC; + frame_sync_reg : in STD_LOGIC; + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\ : in STD_LOGIC; + dma_err : in STD_LOGIC; + \vert_count_reg_1__s_port_\ : in STD_LOGIC; + \vert_count_reg[11]_0\ : in STD_LOGIC; + \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[4]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + valid_frame_sync_d2 : in STD_LOGIC; + CO : in STD_LOGIC_VECTOR ( 0 to 0 ); + in0 : in STD_LOGIC_VECTOR ( 2 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized24\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized24\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized24\ is + signal \DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_i_3_n_0\ : STD_LOGIC; + signal \FSM_sequential_dmacntrl_cs[0]_i_2__0_n_0\ : STD_LOGIC; + signal \FSM_sequential_dmacntrl_cs[0]_i_3__0_n_0\ : STD_LOGIC; + signal \FSM_sequential_dmacntrl_cs[1]_i_2__0_n_0\ : STD_LOGIC; + signal \FSM_sequential_dmacntrl_cs[1]_i_3__0_n_0\ : STD_LOGIC; + signal \FSM_sequential_dmacntrl_cs[2]_i_2__0_n_0\ : STD_LOGIC; + signal \FSM_sequential_dmacntrl_cs[2]_i_3__0_n_0\ : STD_LOGIC; + signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_2__0_n_0\ : STD_LOGIC; + signal \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_cnt_en_reg\ : STD_LOGIC; + signal \^gen_normal_dm_command.cmnd_data_reg[0]\ : STD_LOGIC; + signal \dm_address[16]_i_2__0_n_0\ : STD_LOGIC; + signal \dm_address[16]_i_3__0_n_0\ : STD_LOGIC; + signal \dm_address[16]_i_4__0_n_0\ : STD_LOGIC; + signal \dm_address[16]_i_5__0_n_0\ : STD_LOGIC; + signal \dm_address[20]_i_2__0_n_0\ : STD_LOGIC; + signal \dm_address[20]_i_3__0_n_0\ : STD_LOGIC; + signal \dm_address[20]_i_4__0_n_0\ : STD_LOGIC; + signal \dm_address[20]_i_5__0_n_0\ : STD_LOGIC; + signal \dm_address[24]_i_2__0_n_0\ : STD_LOGIC; + signal \dm_address[24]_i_3__0_n_0\ : STD_LOGIC; + signal \dm_address[24]_i_4__0_n_0\ : STD_LOGIC; + signal \dm_address[24]_i_5__0_n_0\ : STD_LOGIC; + signal \dm_address[28]_i_2__0_n_0\ : STD_LOGIC; + signal \dm_address[28]_i_3__0_n_0\ : STD_LOGIC; + signal \dm_address[28]_i_4__0_n_0\ : STD_LOGIC; + signal \dm_address[28]_i_5__0_n_0\ : STD_LOGIC; + signal \dm_address_reg[16]_i_1__0_n_0\ : STD_LOGIC; + signal \dm_address_reg[16]_i_1__0_n_1\ : STD_LOGIC; + signal \dm_address_reg[16]_i_1__0_n_2\ : STD_LOGIC; + signal \dm_address_reg[16]_i_1__0_n_3\ : STD_LOGIC; + signal \dm_address_reg[20]_i_1__0_n_0\ : STD_LOGIC; + signal \dm_address_reg[20]_i_1__0_n_1\ : STD_LOGIC; + signal \dm_address_reg[20]_i_1__0_n_2\ : STD_LOGIC; + signal \dm_address_reg[20]_i_1__0_n_3\ : STD_LOGIC; + signal \dm_address_reg[24]_i_1__0_n_0\ : STD_LOGIC; + signal \dm_address_reg[24]_i_1__0_n_1\ : STD_LOGIC; + signal \dm_address_reg[24]_i_1__0_n_2\ : STD_LOGIC; + signal \dm_address_reg[24]_i_1__0_n_3\ : STD_LOGIC; + signal \dm_address_reg[28]_i_1__0_n_1\ : STD_LOGIC; + signal \dm_address_reg[28]_i_1__0_n_2\ : STD_LOGIC; + signal \dm_address_reg[28]_i_1__0_n_3\ : STD_LOGIC; + signal \dm_address_reg_0__s_net_1\ : STD_LOGIC; + signal dmacntrl_ns1 : STD_LOGIC; + signal dmacntrl_ns15_out : STD_LOGIC; + signal p_in_d1_cdc_from : STD_LOGIC; + signal prmry_in_xored : STD_LOGIC; + signal s2mm_fsize_mismatch_err_flag : STD_LOGIC; + signal \^s2mm_ftchcmdsts_idle\ : STD_LOGIC; + signal s_out_d1_cdc_to : STD_LOGIC; + signal s_out_d2 : STD_LOGIC; + signal s_out_d3 : STD_LOGIC; + signal s_out_d4 : STD_LOGIC; + signal s_out_d5 : STD_LOGIC; + signal \s_out_re__0\ : STD_LOGIC; + signal srst_d1 : STD_LOGIC; + signal srst_d2 : STD_LOGIC; + signal srst_d3 : STD_LOGIC; + signal srst_d4 : STD_LOGIC; + signal srst_d5 : STD_LOGIC; + signal \vert_count[0]_i_10__0_n_0\ : STD_LOGIC; + signal \vert_count[0]_i_11__0_n_0\ : STD_LOGIC; + signal \vert_count[0]_i_4__0_n_0\ : STD_LOGIC; + signal \vert_count[0]_i_5__0_n_0\ : STD_LOGIC; + signal \vert_count[0]_i_6__0_n_0\ : STD_LOGIC; + signal \vert_count[0]_i_7__0_n_0\ : STD_LOGIC; + signal \vert_count[0]_i_8__0_n_0\ : STD_LOGIC; + signal \vert_count[0]_i_9__0_n_0\ : STD_LOGIC; + signal \vert_count[12]_i_2__0_n_0\ : STD_LOGIC; + signal \vert_count[4]_i_2__0_n_0\ : STD_LOGIC; + signal \vert_count[4]_i_3__0_n_0\ : STD_LOGIC; + signal \vert_count[4]_i_4__0_n_0\ : STD_LOGIC; + signal \vert_count[4]_i_5__0_n_0\ : STD_LOGIC; + signal \vert_count[4]_i_6__0_n_0\ : STD_LOGIC; + signal \vert_count[4]_i_7__0_n_0\ : STD_LOGIC; + signal \vert_count[4]_i_8__0_n_0\ : STD_LOGIC; + signal \vert_count[4]_i_9__0_n_0\ : STD_LOGIC; + signal \vert_count[8]_i_2__0_n_0\ : STD_LOGIC; + signal \vert_count[8]_i_3__0_n_0\ : STD_LOGIC; + signal \vert_count[8]_i_4__0_n_0\ : STD_LOGIC; + signal \vert_count[8]_i_5__0_n_0\ : STD_LOGIC; + signal \vert_count[8]_i_6__0_n_0\ : STD_LOGIC; + signal \vert_count[8]_i_7__0_n_0\ : STD_LOGIC; + signal \vert_count[8]_i_8__0_n_0\ : STD_LOGIC; + signal \vert_count[8]_i_9__0_n_0\ : STD_LOGIC; + signal \vert_count_reg[0]_i_2__0_n_0\ : STD_LOGIC; + signal \vert_count_reg[0]_i_2__0_n_1\ : STD_LOGIC; + signal \vert_count_reg[0]_i_2__0_n_2\ : STD_LOGIC; + signal \vert_count_reg[0]_i_2__0_n_3\ : STD_LOGIC; + signal \vert_count_reg[4]_i_1__0_n_0\ : STD_LOGIC; + signal \vert_count_reg[4]_i_1__0_n_1\ : STD_LOGIC; + signal \vert_count_reg[4]_i_1__0_n_2\ : STD_LOGIC; + signal \vert_count_reg[4]_i_1__0_n_3\ : STD_LOGIC; + signal \vert_count_reg[8]_i_1__0_n_0\ : STD_LOGIC; + signal \vert_count_reg[8]_i_1__0_n_1\ : STD_LOGIC; + signal \vert_count_reg[8]_i_1__0_n_2\ : STD_LOGIC; + signal \vert_count_reg[8]_i_1__0_n_3\ : STD_LOGIC; + signal \vert_count_reg_0__s_net_1\ : STD_LOGIC; + signal \vert_count_reg_1__s_net_1\ : STD_LOGIC; + signal \NLW_dm_address_reg[28]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_vert_count_reg[12]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_vert_count_reg[12]_i_1__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF.flag_to_repeat_after_fsize_less_err_i_1\ : label is "soft_lutpair50"; + attribute SOFT_HLUTNM of \FSM_sequential_dmacntrl_cs[0]_i_3__0\ : label is "soft_lutpair48"; + attribute SOFT_HLUTNM of \FSM_sequential_dmacntrl_cs[1]_i_4\ : label is "soft_lutpair49"; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "PRIMITIVE"; + attribute SOFT_HLUTNM of \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_irqthresh_decr_mask_sig_i_1\ : label is "soft_lutpair49"; + attribute SOFT_HLUTNM of \GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1__0\ : label is "soft_lutpair50"; + attribute SOFT_HLUTNM of \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_i_1__0\ : label is "soft_lutpair48"; + attribute METHODOLOGY_DRC_VIOS : string; + attribute METHODOLOGY_DRC_VIOS of \dm_address_reg[16]_i_1__0\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \dm_address_reg[20]_i_1__0\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \dm_address_reg[24]_i_1__0\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \dm_address_reg[28]_i_1__0\ : label is "{SYNTH-8 {cell *THIS*}}"; +begin + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg\ <= \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_cnt_en_reg\; + \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[0]\ <= \^gen_normal_dm_command.cmnd_data_reg[0]\; + \dm_address_reg_0__s_port_]\ <= \dm_address_reg_0__s_net_1\; + s2mm_ftchcmdsts_idle <= \^s2mm_ftchcmdsts_idle\; + \vert_count_reg_0__s_port_]\ <= \vert_count_reg_0__s_net_1\; + \vert_count_reg_1__s_net_1\ <= \vert_count_reg_1__s_port_\; +\DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFEFF" + ) + port map ( + I0 => \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[4]\(0), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[4]\(1), + I2 => \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[4]\(3), + I3 => s2mm_dmacr(1), + I4 => \DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_i_3_n_0\, + O => \DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_reg\ + ); +\DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFEF" + ) + port map ( + I0 => fsize_mismatch_err_flag_int, + I1 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_cnt_en_reg\, + I2 => valid_frame_sync_d2, + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[4]\(2), + O => \DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_i_3_n_0\ + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF.flag_to_repeat_after_fsize_less_err_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00E0" + ) + port map ( + I0 => flag_to_repeat_after_fsize_less_err, + I1 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_cnt_en_reg\, + I2 => \out\, + I3 => valid_frame_sync_d2, + O => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF.flag_to_repeat_after_fsize_less_err_reg\ + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FE02" + ) + port map ( + I0 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(0), + I1 => flag_to_repeat_after_fsize_less_err, + I2 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_cnt_en_reg\, + I3 => \GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[4]\(0), + O => D(0) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FE02" + ) + port map ( + I0 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(1), + I1 => flag_to_repeat_after_fsize_less_err, + I2 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_cnt_en_reg\, + I3 => \GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[4]\(1), + O => D(1) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FE02" + ) + port map ( + I0 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(2), + I1 => flag_to_repeat_after_fsize_less_err, + I2 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_cnt_en_reg\, + I3 => \GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[4]\(2), + O => D(2) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FE02" + ) + port map ( + I0 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(3), + I1 => flag_to_repeat_after_fsize_less_err, + I2 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_cnt_en_reg\, + I3 => \GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[4]\(3), + O => D(3) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr[4]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FE02" + ) + port map ( + I0 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(4), + I1 => flag_to_repeat_after_fsize_less_err, + I2 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_cnt_en_reg\, + I3 => \GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[4]\(4), + O => D(4) + ); +\FSM_sequential_dmacntrl_cs[0]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFA1A05E5F0000" + ) + port map ( + I0 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(1), + I1 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(0), + I2 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(2), + I3 => \FSM_sequential_dmacntrl_cs[2]_i_2__0_n_0\, + I4 => \FSM_sequential_dmacntrl_cs[0]_i_2__0_n_0\, + I5 => in0(0), + O => \FSM_sequential_dmacntrl_cs_reg[0]\ + ); +\FSM_sequential_dmacntrl_cs[0]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888B8BBB88BBBB" + ) + port map ( + I0 => \FSM_sequential_dmacntrl_cs[0]_i_3__0_n_0\, + I1 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(0), + I2 => dmacntrl_ns1, + I3 => \FSM_sequential_dmacntrl_cs[1]_i_3__0_n_0\, + I4 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(1), + I5 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(2), + O => \FSM_sequential_dmacntrl_cs[0]_i_2__0_n_0\ + ); +\FSM_sequential_dmacntrl_cs[0]_i_3__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0062" + ) + port map ( + I0 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(2), + I1 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(1), + I2 => s_axis_cmd_tvalid_reg, + I3 => dmacntrl_ns15_out, + O => \FSM_sequential_dmacntrl_cs[0]_i_3__0_n_0\ + ); +\FSM_sequential_dmacntrl_cs[1]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFA1A05E5F0000" + ) + port map ( + I0 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(1), + I1 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(0), + I2 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(2), + I3 => \FSM_sequential_dmacntrl_cs[2]_i_2__0_n_0\, + I4 => \FSM_sequential_dmacntrl_cs[1]_i_2__0_n_0\, + I5 => in0(1), + O => \FSM_sequential_dmacntrl_cs_reg[1]\ + ); +\FSM_sequential_dmacntrl_cs[1]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"04555F0004000A00" + ) + port map ( + I0 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(2), + I1 => s_axis_cmd_tvalid_reg, + I2 => dmacntrl_ns15_out, + I3 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(0), + I4 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(1), + I5 => \FSM_sequential_dmacntrl_cs[1]_i_3__0_n_0\, + O => \FSM_sequential_dmacntrl_cs[1]_i_2__0_n_0\ + ); +\FSM_sequential_dmacntrl_cs[1]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000010" + ) + port map ( + I0 => s2mm_fsize_mismatch_err_flag, + I1 => frame_sync_reg, + I2 => s2mm_dmacr(0), + I3 => s2mm_halt, + I4 => s2mm_soft_reset, + I5 => dma_err, + O => \FSM_sequential_dmacntrl_cs[1]_i_3__0_n_0\ + ); +\FSM_sequential_dmacntrl_cs[1]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_cnt_en_reg\, + I1 => fsize_mismatch_err_flag_int, + O => s2mm_fsize_mismatch_err_flag + ); +\FSM_sequential_dmacntrl_cs[2]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFA1A05E5F0000" + ) + port map ( + I0 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(1), + I1 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(0), + I2 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(2), + I3 => \FSM_sequential_dmacntrl_cs[2]_i_2__0_n_0\, + I4 => \FSM_sequential_dmacntrl_cs[2]_i_3__0_n_0\, + I5 => in0(2), + O => \FSM_sequential_dmacntrl_cs_reg[2]\ + ); +\FSM_sequential_dmacntrl_cs[2]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFDFFF" + ) + port map ( + I0 => s2mm_dmacr(0), + I1 => halt_i_reg, + I2 => frame_sync_reg, + I3 => \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\, + I4 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_cnt_en_reg\, + I5 => fsize_mismatch_err_flag_int, + O => \FSM_sequential_dmacntrl_cs[2]_i_2__0_n_0\ + ); +\FSM_sequential_dmacntrl_cs[2]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0010001000000F00" + ) + port map ( + I0 => s_axis_cmd_tvalid_reg, + I1 => dmacntrl_ns15_out, + I2 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(0), + I3 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(2), + I4 => dmacntrl_ns1, + I5 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(1), + O => \FSM_sequential_dmacntrl_cs[2]_i_3__0_n_0\ + ); +\FSM_sequential_dmacntrl_cs[2]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAABAAAAAAAA" + ) + port map ( + I0 => dmacntrl_ns15_out, + I1 => vert_count_reg(10), + I2 => vert_count_reg(12), + I3 => vert_count_reg(7), + I4 => \vert_count_reg_1__s_net_1\, + I5 => \vert_count_reg[11]_0\, + O => dmacntrl_ns1 + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000001" + ) + port map ( + I0 => \cmnds_queued_reg[7]\(0), + I1 => \cmnds_queued_reg[7]\(2), + I2 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_2__0_n_0\, + I3 => \cmnds_queued_reg[7]\(3), + I4 => \cmnds_queued_reg[7]\(4), + I5 => \cmnds_queued_reg[1]\, + O => \^s2mm_ftchcmdsts_idle\ + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFEF" + ) + port map ( + I0 => \cmnds_queued_reg[7]\(1), + I1 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(1), + I2 => \FSM_sequential_dmacntrl_cs[2]_i_2__0_n_0\, + I3 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(2), + I4 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(0), + O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_2__0_n_0\ + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_out_d1_cdc_to, + Q => s_out_d2, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_out_d2, + Q => s_out_d3, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_out_d3, + Q => s_out_d4, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_out_d4, + Q => s_out_d5, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \s_out_re__0\, + Q => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_cnt_en_reg\, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => p_in_d1_cdc_from, + Q => s_out_d1_cdc_to, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => prmry_in_xored, + Q => p_in_d1_cdc_from, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__10\: unisim.vcomponents.LUT3 + generic map( + INIT => X"1E" + ) + port map ( + I0 => drop_fsync_d_pulse_gen_fsize_less_err_d1, + I1 => fsize_mismatch_err_s1, + I2 => p_in_d1_cdc_from, + O => prmry_in_xored + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => '1', + Q => srst_d1, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => srst_d1, + Q => srst_d2, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => srst_d2, + Q => srst_d3, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => srst_d3, + Q => srst_d4, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => srst_d4, + Q => srst_d5, + R => SR(0) + ); +\GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0F0001000F0F0100" + ) + port map ( + I0 => fsize_mismatch_err_flag_int, + I1 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_cnt_en_reg\, + I2 => prmry_resetn_i_reg, + I3 => s2mm_tstvect_fsync, + I4 => ch2_delay_cnt_en, + I5 => s2mm_packet_sof, + O => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0\ + ); +\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_irqthresh_decr_mask_sig_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EFE0" + ) + port map ( + I0 => fsize_mismatch_err_flag_int, + I1 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_cnt_en_reg\, + I2 => s2mm_tstvect_fsync, + I3 => ch2_irqthresh_decr_mask_sig, + O => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_irqthresh_decr_mask_sig_reg\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^gen_normal_dm_command.cmnd_data_reg[0]\, + I1 => \out\, + O => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[63]\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data[63]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000008FFFFFFFF" + ) + port map ( + I0 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(1), + I1 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(0), + I2 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(2), + I3 => dmacntrl_ns15_out, + I4 => s_axis_cmd_tvalid_reg, + I5 => \out\, + O => \^gen_normal_dm_command.cmnd_data_reg[0]\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_wr_i_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01000000" + ) + port map ( + I0 => s_axis_cmd_tvalid_reg, + I1 => dmacntrl_ns15_out, + I2 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(2), + I3 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(0), + I4 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(1), + O => write_cmnd_cmb + ); +\GEN_NORMAL_DM_COMMAND.cmnd_wr_i_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => dma_err, + I1 => s2mm_soft_reset, + I2 => s2mm_halt, + I3 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_cnt_en_reg\, + I4 => fsize_mismatch_err_flag_int, + I5 => frame_sync_reg, + O => dmacntrl_ns15_out + ); +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EEEEEEEEFFFFFEFF" + ) + port map ( + I0 => fsize_mismatch_err_flag_int, + I1 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_cnt_en_reg\, + I2 => s2mm_halt, + I3 => \out\, + I4 => s2mm_cdc2dmac_fsync, + I5 => s2mm_fsync_out_m_i, + O => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[0]\(0) + ); +\dm_address[0]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AABAAAAA" + ) + port map ( + I0 => \vert_count_reg_0__s_net_1\, + I1 => dmacntrl_ns15_out, + I2 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(0), + I3 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(1), + I4 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(2), + O => \dm_address_reg_0__s_net_1\ + ); +\dm_address[16]_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][19]\, + I1 => \vert_count_reg_0__s_net_1\, + I2 => dm_address_reg(3), + O => \dm_address[16]_i_2__0_n_0\ + ); +\dm_address[16]_i_3__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][18]\, + I1 => \vert_count_reg_0__s_net_1\, + I2 => dm_address_reg(2), + O => \dm_address[16]_i_3__0_n_0\ + ); +\dm_address[16]_i_4__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][17]\, + I1 => \vert_count_reg_0__s_net_1\, + I2 => dm_address_reg(1), + O => \dm_address[16]_i_4__0_n_0\ + ); +\dm_address[16]_i_5__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][16]\, + I1 => \vert_count_reg_0__s_net_1\, + I2 => dm_address_reg(0), + O => \dm_address[16]_i_5__0_n_0\ + ); +\dm_address[20]_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][23]\, + I1 => \vert_count_reg_0__s_net_1\, + I2 => dm_address_reg(7), + O => \dm_address[20]_i_2__0_n_0\ + ); +\dm_address[20]_i_3__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][22]\, + I1 => \vert_count_reg_0__s_net_1\, + I2 => dm_address_reg(6), + O => \dm_address[20]_i_3__0_n_0\ + ); +\dm_address[20]_i_4__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][21]\, + I1 => \vert_count_reg_0__s_net_1\, + I2 => dm_address_reg(5), + O => \dm_address[20]_i_4__0_n_0\ + ); +\dm_address[20]_i_5__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][20]\, + I1 => \vert_count_reg_0__s_net_1\, + I2 => dm_address_reg(4), + O => \dm_address[20]_i_5__0_n_0\ + ); +\dm_address[24]_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][27]\, + I1 => \vert_count_reg_0__s_net_1\, + I2 => dm_address_reg(11), + O => \dm_address[24]_i_2__0_n_0\ + ); +\dm_address[24]_i_3__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][26]\, + I1 => \vert_count_reg_0__s_net_1\, + I2 => dm_address_reg(10), + O => \dm_address[24]_i_3__0_n_0\ + ); +\dm_address[24]_i_4__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][25]\, + I1 => \vert_count_reg_0__s_net_1\, + I2 => dm_address_reg(9), + O => \dm_address[24]_i_4__0_n_0\ + ); +\dm_address[24]_i_5__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][24]\, + I1 => \vert_count_reg_0__s_net_1\, + I2 => dm_address_reg(8), + O => \dm_address[24]_i_5__0_n_0\ + ); +\dm_address[28]_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\, + I1 => \vert_count_reg_0__s_net_1\, + I2 => dm_address_reg(15), + O => \dm_address[28]_i_2__0_n_0\ + ); +\dm_address[28]_i_3__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][30]\, + I1 => \vert_count_reg_0__s_net_1\, + I2 => dm_address_reg(14), + O => \dm_address[28]_i_3__0_n_0\ + ); +\dm_address[28]_i_4__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][29]\, + I1 => \vert_count_reg_0__s_net_1\, + I2 => dm_address_reg(13), + O => \dm_address[28]_i_4__0_n_0\ + ); +\dm_address[28]_i_5__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][28]\, + I1 => \vert_count_reg_0__s_net_1\, + I2 => dm_address_reg(12), + O => \dm_address[28]_i_5__0_n_0\ + ); +\dm_address_reg[16]_i_1__0\: unisim.vcomponents.CARRY4 + port map ( + CI => CO(0), + CO(3) => \dm_address_reg[16]_i_1__0_n_0\, + CO(2) => \dm_address_reg[16]_i_1__0_n_1\, + CO(1) => \dm_address_reg[16]_i_1__0_n_2\, + CO(0) => \dm_address_reg[16]_i_1__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => \dm_address_reg[19]\(3 downto 0), + S(3) => \dm_address[16]_i_2__0_n_0\, + S(2) => \dm_address[16]_i_3__0_n_0\, + S(1) => \dm_address[16]_i_4__0_n_0\, + S(0) => \dm_address[16]_i_5__0_n_0\ + ); +\dm_address_reg[20]_i_1__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \dm_address_reg[16]_i_1__0_n_0\, + CO(3) => \dm_address_reg[20]_i_1__0_n_0\, + CO(2) => \dm_address_reg[20]_i_1__0_n_1\, + CO(1) => \dm_address_reg[20]_i_1__0_n_2\, + CO(0) => \dm_address_reg[20]_i_1__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => \dm_address_reg[23]\(3 downto 0), + S(3) => \dm_address[20]_i_2__0_n_0\, + S(2) => \dm_address[20]_i_3__0_n_0\, + S(1) => \dm_address[20]_i_4__0_n_0\, + S(0) => \dm_address[20]_i_5__0_n_0\ + ); +\dm_address_reg[24]_i_1__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \dm_address_reg[20]_i_1__0_n_0\, + CO(3) => \dm_address_reg[24]_i_1__0_n_0\, + CO(2) => \dm_address_reg[24]_i_1__0_n_1\, + CO(1) => \dm_address_reg[24]_i_1__0_n_2\, + CO(0) => \dm_address_reg[24]_i_1__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => \dm_address_reg[27]\(3 downto 0), + S(3) => \dm_address[24]_i_2__0_n_0\, + S(2) => \dm_address[24]_i_3__0_n_0\, + S(1) => \dm_address[24]_i_4__0_n_0\, + S(0) => \dm_address[24]_i_5__0_n_0\ + ); +\dm_address_reg[28]_i_1__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \dm_address_reg[24]_i_1__0_n_0\, + CO(3) => \NLW_dm_address_reg[28]_i_1__0_CO_UNCONNECTED\(3), + CO(2) => \dm_address_reg[28]_i_1__0_n_1\, + CO(1) => \dm_address_reg[28]_i_1__0_n_2\, + CO(0) => \dm_address_reg[28]_i_1__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => \dm_address_reg[31]\(3 downto 0), + S(3) => \dm_address[28]_i_2__0_n_0\, + S(2) => \dm_address[28]_i_3__0_n_0\, + S(1) => \dm_address[28]_i_4__0_n_0\, + S(0) => \dm_address[28]_i_5__0_n_0\ + ); +\halt_i_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EEFEEEFEFFFFEEFE" + ) + port map ( + I0 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_cnt_en_reg\, + I1 => s2mm_stop, + I2 => run_stop_d1, + I3 => s2mm_dmacr(0), + I4 => s2mm_soft_reset, + I5 => soft_reset_d1, + O => halt_i0 + ); +\halted_set_i_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => \^s2mm_ftchcmdsts_idle\, + I1 => datamover_idle, + I2 => s2mm_dmacr(0), + O => halted_set_i0 + ); +s_out_re: unisim.vcomponents.LUT3 + generic map( + INIT => X"28" + ) + port map ( + I0 => srst_d5, + I1 => s_out_d5, + I2 => s_out_d4, + O => \s_out_re__0\ + ); +\vert_count[0]_i_10__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"C5" + ) + port map ( + I0 => vert_count_reg(1), + I1 => Q(1), + I2 => \vert_count_reg_0__s_net_1\, + O => \vert_count[0]_i_10__0_n_0\ + ); +\vert_count[0]_i_11__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"C5" + ) + port map ( + I0 => vert_count_reg(0), + I1 => Q(0), + I2 => \vert_count_reg_0__s_net_1\, + O => \vert_count[0]_i_11__0_n_0\ + ); +\vert_count[0]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF00000008" + ) + port map ( + I0 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(1), + I1 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(0), + I2 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(2), + I3 => dmacntrl_ns15_out, + I4 => s_axis_cmd_tvalid_reg, + I5 => \vert_count_reg_0__s_net_1\, + O => \vert_count_reg[0]_0\ + ); +\vert_count[0]_i_3__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"1000" + ) + port map ( + I0 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(0), + I1 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(2), + I2 => \FSM_sequential_dmacntrl_cs_reg[2]_0\(1), + I3 => \FSM_sequential_dmacntrl_cs[1]_i_3__0_n_0\, + O => \vert_count_reg_0__s_net_1\ + ); +\vert_count[0]_i_4__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \vert_count_reg_0__s_net_1\, + O => \vert_count[0]_i_4__0_n_0\ + ); +\vert_count[0]_i_5__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \vert_count_reg_0__s_net_1\, + O => \vert_count[0]_i_5__0_n_0\ + ); +\vert_count[0]_i_6__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \vert_count_reg_0__s_net_1\, + O => \vert_count[0]_i_6__0_n_0\ + ); +\vert_count[0]_i_7__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \vert_count_reg_0__s_net_1\, + O => \vert_count[0]_i_7__0_n_0\ + ); +\vert_count[0]_i_8__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"C5" + ) + port map ( + I0 => vert_count_reg(3), + I1 => Q(3), + I2 => \vert_count_reg_0__s_net_1\, + O => \vert_count[0]_i_8__0_n_0\ + ); +\vert_count[0]_i_9__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"C5" + ) + port map ( + I0 => vert_count_reg(2), + I1 => Q(2), + I2 => \vert_count_reg_0__s_net_1\, + O => \vert_count[0]_i_9__0_n_0\ + ); +\vert_count[12]_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A3" + ) + port map ( + I0 => Q(12), + I1 => vert_count_reg(12), + I2 => \vert_count_reg_0__s_net_1\, + O => \vert_count[12]_i_2__0_n_0\ + ); +\vert_count[4]_i_2__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \vert_count_reg_0__s_net_1\, + O => \vert_count[4]_i_2__0_n_0\ + ); +\vert_count[4]_i_3__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \vert_count_reg_0__s_net_1\, + O => \vert_count[4]_i_3__0_n_0\ + ); +\vert_count[4]_i_4__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \vert_count_reg_0__s_net_1\, + O => \vert_count[4]_i_4__0_n_0\ + ); +\vert_count[4]_i_5__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \vert_count_reg_0__s_net_1\, + O => \vert_count[4]_i_5__0_n_0\ + ); +\vert_count[4]_i_6__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"C5" + ) + port map ( + I0 => vert_count_reg(7), + I1 => Q(7), + I2 => \vert_count_reg_0__s_net_1\, + O => \vert_count[4]_i_6__0_n_0\ + ); +\vert_count[4]_i_7__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"C5" + ) + port map ( + I0 => vert_count_reg(6), + I1 => Q(6), + I2 => \vert_count_reg_0__s_net_1\, + O => \vert_count[4]_i_7__0_n_0\ + ); +\vert_count[4]_i_8__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"C5" + ) + port map ( + I0 => vert_count_reg(5), + I1 => Q(5), + I2 => \vert_count_reg_0__s_net_1\, + O => \vert_count[4]_i_8__0_n_0\ + ); +\vert_count[4]_i_9__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"C5" + ) + port map ( + I0 => vert_count_reg(4), + I1 => Q(4), + I2 => \vert_count_reg_0__s_net_1\, + O => \vert_count[4]_i_9__0_n_0\ + ); +\vert_count[8]_i_2__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \vert_count_reg_0__s_net_1\, + O => \vert_count[8]_i_2__0_n_0\ + ); +\vert_count[8]_i_3__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \vert_count_reg_0__s_net_1\, + O => \vert_count[8]_i_3__0_n_0\ + ); +\vert_count[8]_i_4__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \vert_count_reg_0__s_net_1\, + O => \vert_count[8]_i_4__0_n_0\ + ); +\vert_count[8]_i_5__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \vert_count_reg_0__s_net_1\, + O => \vert_count[8]_i_5__0_n_0\ + ); +\vert_count[8]_i_6__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"C5" + ) + port map ( + I0 => vert_count_reg(11), + I1 => Q(11), + I2 => \vert_count_reg_0__s_net_1\, + O => \vert_count[8]_i_6__0_n_0\ + ); +\vert_count[8]_i_7__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"C5" + ) + port map ( + I0 => vert_count_reg(10), + I1 => Q(10), + I2 => \vert_count_reg_0__s_net_1\, + O => \vert_count[8]_i_7__0_n_0\ + ); +\vert_count[8]_i_8__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"C5" + ) + port map ( + I0 => vert_count_reg(9), + I1 => Q(9), + I2 => \vert_count_reg_0__s_net_1\, + O => \vert_count[8]_i_8__0_n_0\ + ); +\vert_count[8]_i_9__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"C5" + ) + port map ( + I0 => vert_count_reg(8), + I1 => Q(8), + I2 => \vert_count_reg_0__s_net_1\, + O => \vert_count[8]_i_9__0_n_0\ + ); +\vert_count_reg[0]_i_2__0\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \vert_count_reg[0]_i_2__0_n_0\, + CO(2) => \vert_count_reg[0]_i_2__0_n_1\, + CO(1) => \vert_count_reg[0]_i_2__0_n_2\, + CO(0) => \vert_count_reg[0]_i_2__0_n_3\, + CYINIT => '0', + DI(3) => \vert_count[0]_i_4__0_n_0\, + DI(2) => \vert_count[0]_i_5__0_n_0\, + DI(1) => \vert_count[0]_i_6__0_n_0\, + DI(0) => \vert_count[0]_i_7__0_n_0\, + O(3 downto 0) => O(3 downto 0), + S(3) => \vert_count[0]_i_8__0_n_0\, + S(2) => \vert_count[0]_i_9__0_n_0\, + S(1) => \vert_count[0]_i_10__0_n_0\, + S(0) => \vert_count[0]_i_11__0_n_0\ + ); +\vert_count_reg[12]_i_1__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \vert_count_reg[8]_i_1__0_n_0\, + CO(3 downto 0) => \NLW_vert_count_reg[12]_i_1__0_CO_UNCONNECTED\(3 downto 0), + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 1) => \NLW_vert_count_reg[12]_i_1__0_O_UNCONNECTED\(3 downto 1), + O(0) => \vert_count_reg[12]\(0), + S(3 downto 1) => B"000", + S(0) => \vert_count[12]_i_2__0_n_0\ + ); +\vert_count_reg[4]_i_1__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \vert_count_reg[0]_i_2__0_n_0\, + CO(3) => \vert_count_reg[4]_i_1__0_n_0\, + CO(2) => \vert_count_reg[4]_i_1__0_n_1\, + CO(1) => \vert_count_reg[4]_i_1__0_n_2\, + CO(0) => \vert_count_reg[4]_i_1__0_n_3\, + CYINIT => '0', + DI(3) => \vert_count[4]_i_2__0_n_0\, + DI(2) => \vert_count[4]_i_3__0_n_0\, + DI(1) => \vert_count[4]_i_4__0_n_0\, + DI(0) => \vert_count[4]_i_5__0_n_0\, + O(3 downto 0) => \vert_count_reg[7]\(3 downto 0), + S(3) => \vert_count[4]_i_6__0_n_0\, + S(2) => \vert_count[4]_i_7__0_n_0\, + S(1) => \vert_count[4]_i_8__0_n_0\, + S(0) => \vert_count[4]_i_9__0_n_0\ + ); +\vert_count_reg[8]_i_1__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \vert_count_reg[4]_i_1__0_n_0\, + CO(3) => \vert_count_reg[8]_i_1__0_n_0\, + CO(2) => \vert_count_reg[8]_i_1__0_n_1\, + CO(1) => \vert_count_reg[8]_i_1__0_n_2\, + CO(0) => \vert_count_reg[8]_i_1__0_n_3\, + CYINIT => '0', + DI(3) => \vert_count[8]_i_2__0_n_0\, + DI(2) => \vert_count[8]_i_3__0_n_0\, + DI(1) => \vert_count[8]_i_4__0_n_0\, + DI(0) => \vert_count[8]_i_5__0_n_0\, + O(3 downto 0) => \vert_count_reg[11]\(3 downto 0), + S(3) => \vert_count[8]_i_6__0_n_0\, + S(2) => \vert_count[8]_i_7__0_n_0\, + S(1) => \vert_count[8]_i_8__0_n_0\, + S(0) => \vert_count[8]_i_9__0_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized25\ is + port ( + p_3_out : out STD_LOGIC; + s_axis_fifo_ainit_nosync : out STD_LOGIC; + s2mm_fsync_core : out STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg\ : out STD_LOGIC; + s_valid0 : out STD_LOGIC; + sig_last_reg_out_reg : out STD_LOGIC; + \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_s1_reg\ : out STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.fsize_err_to_dm_halt_flag_reg\ : out STD_LOGIC; + prmry_reset2 : in STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + s2mm_halt : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + \out\ : in STD_LOGIC; + delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s : in STD_LOGIC; + delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 : in STD_LOGIC; + delay_s2mm_fsync_core_till_mmap_done_flag_d1 : in STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_reg\ : in STD_LOGIC; + run_stop_reg : in STD_LOGIC; + \sig_user_reg_out_reg[0]\ : in STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\ : in STD_LOGIC; + mmap_not_finished_s : in STD_LOGIC; + fsize_mismatch_err_s1 : in STD_LOGIC; + drop_fsync_d_pulse_gen_fsize_less_err_d1 : in STD_LOGIC; + fsize_err_to_dm_halt_flag : in STD_LOGIC; + M_VALID : in STD_LOGIC; + FULL : in STD_LOGIC; + s2mm_fsync_out_i : in STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized25\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized25\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized25\ is + signal \^gen_s2mm_flush_sof_logic.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg\ : STD_LOGIC; + signal \^p_3_out\ : STD_LOGIC; + signal p_level_in_d1_cdc_from : STD_LOGIC; + signal s_fsync_d1_i_2_n_0 : STD_LOGIC; + signal s_level_out_d1_cdc_to : STD_LOGIC; + signal s_level_out_d2 : STD_LOGIC; + signal s_level_out_d3 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_i_3\ : label is "soft_lutpair83"; + attribute SOFT_HLUTNM of \GEN_S2MM_FLUSH_SOF_LOGIC.fsize_err_to_dm_halt_flag_i_1\ : label is "soft_lutpair83"; + attribute SOFT_HLUTNM of \sig_last_reg_out_i_4__0\ : label is "soft_lutpair82"; + attribute SOFT_HLUTNM of \sig_last_skid_reg_i_1__1\ : label is "soft_lutpair82"; +begin + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg\ <= \^gen_s2mm_flush_sof_logic.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg\; + p_3_out <= \^p_3_out\; +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => p_level_in_d1_cdc_from, + Q => s_level_out_d1_cdc_to, + R => prmry_reset2 + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_level_out_d1_cdc_to, + Q => s_level_out_d2, + R => prmry_reset2 + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_level_out_d2, + Q => s_level_out_d3, + R => prmry_reset2 + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_level_out_d3, + Q => \^p_3_out\, + R => prmry_reset2 + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s2mm_halt, + Q => p_level_in_d1_cdc_from, + R => SR(0) + ); +\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_s1_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000F4F4FFF4" + ) + port map ( + I0 => delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s, + I1 => delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1, + I2 => s_fsync_d1_i_2_n_0, + I3 => delay_s2mm_fsync_core_till_mmap_done_flag_d1, + I4 => \GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_reg\, + I5 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\, + O => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_s1_reg\ + ); +\GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \^p_3_out\, + I1 => fsize_mismatch_err_s1, + I2 => drop_fsync_d_pulse_gen_fsize_less_err_d1, + I3 => fsize_err_to_dm_halt_flag, + O => \^gen_s2mm_flush_sof_logic.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg\ + ); +\GEN_S2MM_FLUSH_SOF_LOGIC.fsize_err_to_dm_halt_flag_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000FE00" + ) + port map ( + I0 => fsize_err_to_dm_halt_flag, + I1 => fsize_mismatch_err_s1, + I2 => drop_fsync_d_pulse_gen_fsize_less_err_d1, + I3 => \out\, + I4 => \^p_3_out\, + O => \GEN_S2MM_FLUSH_SOF_LOGIC.fsize_err_to_dm_halt_flag_reg\ + ); +s_fsync_d1_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"F4F4FFF4" + ) + port map ( + I0 => delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s, + I1 => delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1, + I2 => s_fsync_d1_i_2_n_0, + I3 => delay_s2mm_fsync_core_till_mmap_done_flag_d1, + I4 => \GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_reg\, + O => s2mm_fsync_core + ); +s_fsync_d1_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"0404040004040404" + ) + port map ( + I0 => \^gen_s2mm_flush_sof_logic.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg\, + I1 => run_stop_reg, + I2 => \sig_user_reg_out_reg[0]\, + I3 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\, + I4 => \GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_reg\, + I5 => mmap_not_finished_s, + O => s_fsync_d1_i_2_n_0 + ); +s_valid_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000800" + ) + port map ( + I0 => M_VALID, + I1 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\, + I2 => \^p_3_out\, + I3 => \out\, + I4 => FULL, + I5 => s2mm_fsync_out_i, + O => s_valid0 + ); +\sig_last_reg_out_i_4__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFDF" + ) + port map ( + I0 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\, + I1 => \^p_3_out\, + I2 => \out\, + I3 => FULL, + I4 => s2mm_fsync_out_i, + O => sig_last_reg_out_reg + ); +\sig_last_skid_reg_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^p_3_out\, + I1 => \out\, + O => s_axis_fifo_ainit_nosync + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized26\ is + port ( + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg\ : out STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg_0\ : out STD_LOGIC; + prmry_reset2 : in STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + s2mm_dmacr : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_s2mm_aclk : in STD_LOGIC; + delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s : in STD_LOGIC; + \sig_user_reg_out_reg[0]\ : in STD_LOGIC; + \out\ : in STD_LOGIC; + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized26\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized26\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized26\ is + signal \^gen_s2mm_flush_sof_logic.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg\ : STD_LOGIC; + signal p_level_in_d1_cdc_from : STD_LOGIC; + signal s_level_out_d1_cdc_to : STD_LOGIC; + signal s_level_out_d2 : STD_LOGIC; + signal s_level_out_d3 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; +begin + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg\ <= \^gen_s2mm_flush_sof_logic.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg\; +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => p_level_in_d1_cdc_from, + Q => s_level_out_d1_cdc_to, + R => prmry_reset2 + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_level_out_d1_cdc_to, + Q => s_level_out_d2, + R => prmry_reset2 + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_level_out_d2, + Q => s_level_out_d3, + R => prmry_reset2 + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_level_out_d3, + Q => \^gen_s2mm_flush_sof_logic.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg\, + R => prmry_reset2 + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s2mm_dmacr(0), + Q => p_level_in_d1_cdc_from, + R => SR(0) + ); +\GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BA000000" + ) + port map ( + I0 => delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s, + I1 => \sig_user_reg_out_reg[0]\, + I2 => \^gen_s2mm_flush_sof_logic.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg\, + I3 => \out\, + I4 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\, + O => \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized27\ is + port ( + p_in_d1_cdc_from : out STD_LOGIC; + \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.s2mm_fsync_out_m_d1_reg\ : out STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\ : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + prmry_reset2 : in STD_LOGIC; + prmry_in_xored : in STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_s2mm_aclk : in STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[6]\ : in STD_LOGIC; + sig_s_ready_out_reg : in STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]\ : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[3]\ : in STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[6]_0\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized27\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized27\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized27\ is + signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^gen_fsize_mismatch.gen_s2mm_mismatch_flush_sof.s2mm_fsync_out_m_d1_reg\ : STD_LOGIC; + signal \^p_in_d1_cdc_from\ : STD_LOGIC; + signal s_out_d1_cdc_to : STD_LOGIC; + signal s_out_d2 : STD_LOGIC; + signal s_out_d3 : STD_LOGIC; + signal s_out_d4 : STD_LOGIC; + signal s_out_d5 : STD_LOGIC; + signal \s_out_re__0\ : STD_LOGIC; + signal srst_d1 : STD_LOGIC; + signal srst_d2 : STD_LOGIC; + signal srst_d3 : STD_LOGIC; + signal srst_d4 : STD_LOGIC; + signal srst_d5 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "PRIMITIVE"; +begin + E(0) <= \^e\(0); + \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.s2mm_fsync_out_m_d1_reg\ <= \^gen_fsize_mismatch.gen_s2mm_mismatch_flush_sof.s2mm_fsync_out_m_d1_reg\; + p_in_d1_cdc_from <= \^p_in_d1_cdc_from\; +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_out_d1_cdc_to, + Q => s_out_d2, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_out_d2, + Q => s_out_d3, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_out_d3, + Q => s_out_d4, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_out_d4, + Q => s_out_d5, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \s_out_re__0\, + Q => \^gen_fsize_mismatch.gen_s2mm_mismatch_flush_sof.s2mm_fsync_out_m_d1_reg\, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \^p_in_d1_cdc_from\, + Q => s_out_d1_cdc_to, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => prmry_in_xored, + Q => \^p_in_d1_cdc_from\, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => '1', + Q => srst_d1, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => srst_d1, + Q => srst_d2, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => srst_d2, + Q => srst_d3, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => srst_d3, + Q => srst_d4, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => srst_d4, + Q => srst_d5, + R => SR(0) + ); +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBBBBBBBBBBBBA" + ) + port map ( + I0 => \^gen_fsize_mismatch.gen_s2mm_mismatch_flush_sof.s2mm_fsync_out_m_d1_reg\, + I1 => sig_s_ready_out_reg, + I2 => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]\, + I3 => Q(0), + I4 => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[3]\, + I5 => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[6]_0\, + O => \^e\(0) + ); +\GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => \^e\(0), + I1 => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[6]\, + I2 => \^gen_fsize_mismatch.gen_s2mm_mismatch_flush_sof.s2mm_fsync_out_m_d1_reg\, + O => \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\ + ); +s_out_re: unisim.vcomponents.LUT3 + generic map( + INIT => X"28" + ) + port map ( + I0 => srst_d5, + I1 => s_out_d5, + I2 => s_out_d4, + O => \s_out_re__0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized29\ is + port ( + mmap_not_finished_s : out STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_reg\ : out STD_LOGIC; + prmry_reset2 : in STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\ : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\ : in STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_reg_0\ : in STD_LOGIC; + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\ : in STD_LOGIC; + \sig_user_reg_out_reg[0]\ : in STD_LOGIC; + \out\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized29\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized29\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized29\ is + signal \^mmap_not_finished_s\ : STD_LOGIC; + signal p_level_in_d1_cdc_from : STD_LOGIC; + signal s_level_out_d1_cdc_to : STD_LOGIC; + signal s_level_out_d2 : STD_LOGIC; + signal s_level_out_d3 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; +begin + mmap_not_finished_s <= \^mmap_not_finished_s\; +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => p_level_in_d1_cdc_from, + Q => s_level_out_d1_cdc_to, + R => prmry_reset2 + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_level_out_d1_cdc_to, + Q => s_level_out_d2, + R => prmry_reset2 + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_level_out_d2, + Q => s_level_out_d3, + R => prmry_reset2 + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_level_out_d3, + Q => \^mmap_not_finished_s\, + R => prmry_reset2 + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\, + Q => p_level_in_d1_cdc_from, + R => SR(0) + ); +\GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"C0C004C000000000" + ) + port map ( + I0 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\, + I1 => \^mmap_not_finished_s\, + I2 => \GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_reg_0\, + I3 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\, + I4 => \sig_user_reg_out_reg[0]\, + I5 => \out\, + O => \GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_reg\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized2_7\ is + port ( + scndry_out : out STD_LOGIC; + m_axis_mm2s_aclk : in STD_LOGIC; + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\ : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized2_7\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized2_7\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized2_7\ is + signal p_level_in_d1_cdc_from : STD_LOGIC; + signal s_level_out_d1_cdc_to : STD_LOGIC; + signal s_level_out_d2 : STD_LOGIC; + signal s_level_out_d3 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; +begin +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => p_level_in_d1_cdc_from, + Q => s_level_out_d1_cdc_to, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => s_level_out_d1_cdc_to, + Q => s_level_out_d2, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => s_level_out_d2, + Q => s_level_out_d3, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => s_level_out_d3, + Q => scndry_out, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\, + Q => p_level_in_d1_cdc_from, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized3\ is + port ( + scndry_out : out STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + axis_min_assert_sftrst : in STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized3\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized3\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized3\ is + signal p_level_in_d1_cdc_from : STD_LOGIC; + signal s_level_out_d1_cdc_to : STD_LOGIC; + signal s_level_out_d2 : STD_LOGIC; + signal s_level_out_d3 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; +begin +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => p_level_in_d1_cdc_from, + Q => s_level_out_d1_cdc_to, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_level_out_d1_cdc_to, + Q => s_level_out_d2, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_level_out_d2, + Q => s_level_out_d3, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_level_out_d3, + Q => scndry_out, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => axis_min_assert_sftrst, + Q => p_level_in_d1_cdc_from, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized3_8\ is + port ( + scndry_out : out STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + axis_min_assert_sftrst : in STD_LOGIC; + m_axis_mm2s_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized3_8\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized3_8\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized3_8\ is + signal p_level_in_d1_cdc_from : STD_LOGIC; + signal s_level_out_d1_cdc_to : STD_LOGIC; + signal s_level_out_d2 : STD_LOGIC; + signal s_level_out_d3 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; +begin +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => p_level_in_d1_cdc_from, + Q => s_level_out_d1_cdc_to, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => s_level_out_d1_cdc_to, + Q => s_level_out_d2, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => s_level_out_d2, + Q => s_level_out_d3, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => s_level_out_d3, + Q => scndry_out, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => axis_min_assert_sftrst, + Q => p_level_in_d1_cdc_from, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized4\ is + port ( + prmry_in : out STD_LOGIC; + run_stop_d1_reg : out STD_LOGIC; + prmry_reset2_0 : out STD_LOGIC; + \dmacr_i_reg[2]\ : out STD_LOGIC; + halt_i_reg : out STD_LOGIC; + \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ : out STD_LOGIC; + reset_counts_reg : out STD_LOGIC; + min_assert_sftrst : in STD_LOGIC; + s_soft_reset_i : in STD_LOGIC; + s2mm_dmacr : in STD_LOGIC_VECTOR ( 0 to 0 ); + s2mm_stop : in STD_LOGIC; + s2mm_soft_reset : in STD_LOGIC; + s2mm_axi2ip_wrce : in STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + assert_sftrst_d1 : in STD_LOGIC; + halt_i_reg_0 : in STD_LOGIC; + halt_reset_reg : in STD_LOGIC; + halt_i0 : in STD_LOGIC; + reset_counts_5 : in STD_LOGIC; + \out\ : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + hrd_resetn_i_reg : in STD_LOGIC; + s_axi_lite_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized4\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized4\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized4\ is + signal p_level_in_d1_cdc_from : STD_LOGIC; + signal \^prmry_in\ : STD_LOGIC; + signal s2mm_hrd_resetn : STD_LOGIC; + signal s_level_out_d1_cdc_to : STD_LOGIC; + signal s_level_out_d2 : STD_LOGIC; + signal s_level_out_d3 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_1__0\ : label is "soft_lutpair265"; + attribute SOFT_HLUTNM of sig_s2mm_dm_prmry_resetn_inferred_i_1 : label is "soft_lutpair265"; +begin + prmry_in <= \^prmry_in\; +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => p_level_in_d1_cdc_from, + Q => s_level_out_d1_cdc_to, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_level_out_d1_cdc_to, + Q => s_level_out_d2, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_level_out_d2, + Q => s_level_out_d3, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_level_out_d3, + Q => s2mm_hrd_resetn, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => hrd_resetn_i_reg, + Q => p_level_in_d1_cdc_from, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"02" + ) + port map ( + I0 => s2mm_hrd_resetn, + I1 => min_assert_sftrst, + I2 => s_soft_reset_i, + O => \^prmry_in\ + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to_i_1__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => s2mm_hrd_resetn, + O => prmry_reset2_0 + ); +\I_DMA_REGISTER/reset_counts_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AE00AEAE00000000" + ) + port map ( + I0 => reset_counts_5, + I1 => s2mm_soft_reset, + I2 => \out\, + I3 => min_assert_sftrst, + I4 => assert_sftrst_d1, + I5 => s2mm_hrd_resetn, + O => reset_counts_reg + ); +\dmacr_i[2]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EA00EAEA00000000" + ) + port map ( + I0 => s2mm_soft_reset, + I1 => s2mm_axi2ip_wrce(0), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[2]\(0), + I3 => min_assert_sftrst, + I4 => assert_sftrst_d1, + I5 => s2mm_hrd_resetn, + O => \dmacr_i_reg[2]\ + ); +\halt_i_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAAA0888" + ) + port map ( + I0 => \^prmry_in\, + I1 => halt_i_reg_0, + I2 => halt_reset_reg, + I3 => s2mm_dmacr(0), + I4 => halt_i0, + O => halt_i_reg + ); +\run_stop_d1_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000200" + ) + port map ( + I0 => s2mm_dmacr(0), + I1 => s2mm_stop, + I2 => s2mm_soft_reset, + I3 => s2mm_hrd_resetn, + I4 => min_assert_sftrst, + I5 => s_soft_reset_i, + O => run_stop_d1_reg + ); +sig_s2mm_dm_prmry_resetn_inferred_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"0010" + ) + port map ( + I0 => s_soft_reset_i, + I1 => min_assert_sftrst, + I2 => s2mm_hrd_resetn, + I3 => halt_reset_reg, + O => \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized4_15\ is + port ( + prmry_in : out STD_LOGIC; + run_stop_d1_reg : out STD_LOGIC; + prmry_reset2 : out STD_LOGIC; + \dmacr_i_reg[2]\ : out STD_LOGIC; + halt_i_reg : out STD_LOGIC; + \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ : out STD_LOGIC; + reset_counts_reg : out STD_LOGIC; + min_assert_sftrst : in STD_LOGIC; + s_soft_reset_i : in STD_LOGIC; + p_71_out : in STD_LOGIC_VECTOR ( 0 to 0 ); + stop : in STD_LOGIC; + p_77_out : in STD_LOGIC; + mm2s_axi2ip_wrce : in STD_LOGIC_VECTOR ( 0 to 0 ); + D : in STD_LOGIC_VECTOR ( 0 to 0 ); + assert_sftrst_d1 : in STD_LOGIC; + halt_i_reg_0 : in STD_LOGIC; + halt_reset_reg : in STD_LOGIC; + halt_i0 : in STD_LOGIC; + reset_counts : in STD_LOGIC; + \out\ : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + hrd_resetn_i_reg : in STD_LOGIC; + s_axi_lite_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized4_15\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized4_15\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized4_15\ is + signal mm2s_hrd_resetn : STD_LOGIC; + signal p_level_in_d1_cdc_from : STD_LOGIC; + signal \^prmry_in\ : STD_LOGIC; + signal s_level_out_d1_cdc_to : STD_LOGIC; + signal s_level_out_d2 : STD_LOGIC; + signal s_level_out_d3 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_1\ : label is "soft_lutpair256"; + attribute SOFT_HLUTNM of sig_mm2s_dm_prmry_resetn_inferred_i_1 : label is "soft_lutpair256"; +begin + prmry_in <= \^prmry_in\; +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => p_level_in_d1_cdc_from, + Q => s_level_out_d1_cdc_to, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => s_level_out_d1_cdc_to, + Q => s_level_out_d2, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => s_level_out_d2, + Q => s_level_out_d3, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => s_level_out_d3, + Q => mm2s_hrd_resetn, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => hrd_resetn_i_reg, + Q => p_level_in_d1_cdc_from, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"02" + ) + port map ( + I0 => mm2s_hrd_resetn, + I1 => min_assert_sftrst, + I2 => s_soft_reset_i, + O => \^prmry_in\ + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => mm2s_hrd_resetn, + O => prmry_reset2 + ); +\I_DMA_REGISTER/reset_counts_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AE00AEAE00000000" + ) + port map ( + I0 => reset_counts, + I1 => p_77_out, + I2 => \out\, + I3 => min_assert_sftrst, + I4 => assert_sftrst_d1, + I5 => mm2s_hrd_resetn, + O => reset_counts_reg + ); +\dmacr_i[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EA00EAEA00000000" + ) + port map ( + I0 => p_77_out, + I1 => mm2s_axi2ip_wrce(0), + I2 => D(0), + I3 => min_assert_sftrst, + I4 => assert_sftrst_d1, + I5 => mm2s_hrd_resetn, + O => \dmacr_i_reg[2]\ + ); +halt_i_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAAA0888" + ) + port map ( + I0 => \^prmry_in\, + I1 => halt_i_reg_0, + I2 => halt_reset_reg, + I3 => p_71_out(0), + I4 => halt_i0, + O => halt_i_reg + ); +run_stop_d1_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000200" + ) + port map ( + I0 => p_71_out(0), + I1 => stop, + I2 => p_77_out, + I3 => mm2s_hrd_resetn, + I4 => min_assert_sftrst, + I5 => s_soft_reset_i, + O => run_stop_d1_reg + ); +sig_mm2s_dm_prmry_resetn_inferred_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"0010" + ) + port map ( + I0 => s_soft_reset_i, + I1 => min_assert_sftrst, + I2 => mm2s_hrd_resetn, + I3 => halt_reset_reg, + O => \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized5\ is + port ( + scndry_out : out STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC; + prmry_in : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized5\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized5\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized5\ is + signal p_level_in_d1_cdc_from : STD_LOGIC; + signal s_level_out_d1_cdc_to : STD_LOGIC; + signal s_level_out_d2 : STD_LOGIC; + signal s_level_out_d3 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; +begin +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => p_level_in_d1_cdc_from, + Q => s_level_out_d1_cdc_to, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_level_out_d1_cdc_to, + Q => s_level_out_d2, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_level_out_d2, + Q => s_level_out_d3, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_level_out_d3, + Q => scndry_out, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => prmry_in, + Q => p_level_in_d1_cdc_from, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized5_14\ is + port ( + scndry_out : out STD_LOGIC; + m_axis_mm2s_aclk : in STD_LOGIC; + prmry_in : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized5_14\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized5_14\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized5_14\ is + signal p_level_in_d1_cdc_from : STD_LOGIC; + signal s_level_out_d1_cdc_to : STD_LOGIC; + signal s_level_out_d2 : STD_LOGIC; + signal s_level_out_d3 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; +begin +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => p_level_in_d1_cdc_from, + Q => s_level_out_d1_cdc_to, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => s_level_out_d1_cdc_to, + Q => s_level_out_d2, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => s_level_out_d2, + Q => s_level_out_d3, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => s_level_out_d3, + Q => scndry_out, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => prmry_in, + Q => p_level_in_d1_cdc_from, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized6\ is + port ( + dmacr_i : out STD_LOGIC_VECTOR ( 0 to 0 ); + mm2s_axi2ip_wrce : out STD_LOGIC_VECTOR ( 8 downto 0 ); + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + prmtr_updt_complete_i_reg : out STD_LOGIC; + ioc_irq_reg : out STD_LOGIC; + dly_irq_reg : out STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_lite_aclk : in STD_LOGIC; + prmry_reset2 : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 10 downto 0 ); + p_71_out : in STD_LOGIC_VECTOR ( 0 to 0 ); + mm2s_prmry_resetn : in STD_LOGIC; + stop : in STD_LOGIC; + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_reg\ : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); + prepare_wrce_d1 : in STD_LOGIC; + lite_wr_addr_phase_finished_data_phase_started : in STD_LOGIC; + wvalid : in STD_LOGIC; + mm2s_ioc_irq_set : in STD_LOGIC; + ioc_irq_reg_0 : in STD_LOGIC; + ch1_dly_irq_set : in STD_LOGIC; + dly_irq_reg_0 : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized6\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized6\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized6\ is + signal \ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_2_n_0\ : STD_LOGIC; + signal \GEN_NUM_FSTORES_3.reg_module_start_address2_i[31]_i_2_n_0\ : STD_LOGIC; + signal \dmacr_i[1]_i_2_n_0\ : STD_LOGIC; + signal \^mm2s_axi2ip_wrce\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal p_0_out : STD_LOGIC; + signal p_in_d1_cdc_from : STD_LOGIC; + signal prmry_in_xored : STD_LOGIC; + signal \reg_module_vsize[12]_i_2_n_0\ : STD_LOGIC; + signal s_out_d1_cdc_to : STD_LOGIC; + signal s_out_d2 : STD_LOGIC; + signal s_out_d3 : STD_LOGIC; + signal s_out_d4 : STD_LOGIC; + signal s_out_d5 : STD_LOGIC; + signal \s_out_re__0\ : STD_LOGIC; + signal srst_d1 : STD_LOGIC; + signal srst_d2 : STD_LOGIC; + signal srst_d3 : STD_LOGIC; + signal srst_d4 : STD_LOGIC; + signal srst_d5 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "PRIMITIVE"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \GEN_NUM_FSTORES_3.reg_module_start_address1_i[31]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \GEN_NUM_FSTORES_3.reg_module_start_address2_i[31]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \GEN_NUM_FSTORES_3.reg_module_start_address2_i[31]_i_2\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \GEN_NUM_FSTORES_3.reg_module_start_address3_i[31]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid[15]_i_1\ : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \reg_module_hsize[15]_i_1\ : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \reg_module_vsize[12]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \reg_module_vsize[12]_i_2\ : label is "soft_lutpair2"; +begin + mm2s_axi2ip_wrce(8 downto 0) <= \^mm2s_axi2ip_wrce\(8 downto 0); +\ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0100FFFF" + ) + port map ( + I0 => D(5), + I1 => D(4), + I2 => D(3), + I3 => \ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_2_n_0\, + I4 => mm2s_prmry_resetn, + O => \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]\(0) + ); +\ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000100000000" + ) + port map ( + I0 => D(6), + I1 => D(7), + I2 => D(8), + I3 => D(9), + I4 => D(10), + I5 => \^mm2s_axi2ip_wrce\(0), + O => \ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_2_n_0\ + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => s_out_d1_cdc_to, + Q => s_out_d2, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => s_out_d2, + Q => s_out_d3, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => s_out_d3, + Q => s_out_d4, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => s_out_d4, + Q => s_out_d5, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \s_out_re__0\, + Q => p_0_out, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => p_in_d1_cdc_from, + Q => s_out_d1_cdc_to, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => prmry_in_xored, + Q => p_in_d1_cdc_from, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BF40" + ) + port map ( + I0 => prepare_wrce_d1, + I1 => lite_wr_addr_phase_finished_data_phase_started, + I2 => wvalid, + I3 => p_in_d1_cdc_from, + O => prmry_in_xored + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => '1', + Q => srst_d1, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => srst_d1, + Q => srst_d2, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => srst_d2, + Q => srst_d3, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => srst_d3, + Q => srst_d4, + R => prmry_reset2 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => srst_d4, + Q => srst_d5, + R => prmry_reset2 + ); +\GEN_NUM_FSTORES_3.reg_module_start_address1_i[31]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0800" + ) + port map ( + I0 => \out\(0), + I1 => \out\(1), + I2 => \out\(3), + I3 => \reg_module_vsize[12]_i_2_n_0\, + O => \^mm2s_axi2ip_wrce\(6) + ); +\GEN_NUM_FSTORES_3.reg_module_start_address2_i[31]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00020000" + ) + port map ( + I0 => \out\(3), + I1 => \out\(2), + I2 => \out\(0), + I3 => \out\(1), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i[31]_i_2_n_0\, + O => \^mm2s_axi2ip_wrce\(7) + ); +\GEN_NUM_FSTORES_3.reg_module_start_address2_i[31]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => \out\(5), + I1 => p_0_out, + I2 => \out\(4), + O => \GEN_NUM_FSTORES_3.reg_module_start_address2_i[31]_i_2_n_0\ + ); +\GEN_NUM_FSTORES_3.reg_module_start_address3_i[31]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00200000" + ) + port map ( + I0 => \out\(3), + I1 => \out\(2), + I2 => \out\(0), + I3 => \out\(1), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i[31]_i_2_n_0\, + O => \^mm2s_axi2ip_wrce\(8) + ); +\I_DMA_REGISTER/dly_irq_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F7F0" + ) + port map ( + I0 => D(2), + I1 => \^mm2s_axi2ip_wrce\(1), + I2 => ch1_dly_irq_set, + I3 => dly_irq_reg_0, + O => dly_irq_reg + ); +\I_DMA_REGISTER/ioc_irq_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F7F0" + ) + port map ( + I0 => D(1), + I1 => \^mm2s_axi2ip_wrce\(1), + I2 => mm2s_ioc_irq_set, + I3 => ioc_irq_reg_0, + O => ioc_irq_reg + ); +\M_GEN_DLYSTRIDE_REGISTER.reg_module_strid[15]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0400" + ) + port map ( + I0 => \out\(0), + I1 => \out\(1), + I2 => \out\(3), + I3 => \reg_module_vsize[12]_i_2_n_0\, + O => \^mm2s_axi2ip_wrce\(5) + ); +dma_interr_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000200" + ) + port map ( + I0 => \dmacr_i[1]_i_2_n_0\, + I1 => \out\(3), + I2 => \out\(1), + I3 => \out\(0), + I4 => \out\(2), + I5 => \out\(4), + O => \^mm2s_axi2ip_wrce\(1) + ); +\dmacr_i[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000000B800" + ) + port map ( + I0 => D(0), + I1 => \^mm2s_axi2ip_wrce\(0), + I2 => p_71_out(0), + I3 => mm2s_prmry_resetn, + I4 => stop, + I5 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_reg\, + O => dmacr_i(0) + ); +\dmacr_i[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000002" + ) + port map ( + I0 => \dmacr_i[1]_i_2_n_0\, + I1 => \out\(3), + I2 => \out\(1), + I3 => \out\(0), + I4 => \out\(2), + I5 => \out\(4), + O => \^mm2s_axi2ip_wrce\(0) + ); +\dmacr_i[1]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => p_0_out, + I1 => \out\(5), + O => \dmacr_i[1]_i_2_n_0\ + ); +prmtr_updt_complete_i_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0100000000000000" + ) + port map ( + I0 => \out\(0), + I1 => \out\(3), + I2 => \out\(1), + I3 => \reg_module_vsize[12]_i_2_n_0\, + I4 => p_71_out(0), + I5 => mm2s_prmry_resetn, + O => prmtr_updt_complete_i_reg + ); +\ptr_ref_i[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000200000" + ) + port map ( + I0 => \out\(3), + I1 => \out\(4), + I2 => \dmacr_i[1]_i_2_n_0\, + I3 => \out\(0), + I4 => \out\(1), + I5 => \out\(2), + O => \^mm2s_axi2ip_wrce\(2) + ); +\reg_module_hsize[15]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0200" + ) + port map ( + I0 => \out\(0), + I1 => \out\(3), + I2 => \out\(1), + I3 => \reg_module_vsize[12]_i_2_n_0\, + O => \^mm2s_axi2ip_wrce\(4) + ); +\reg_module_vsize[12]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0100" + ) + port map ( + I0 => \out\(0), + I1 => \out\(3), + I2 => \out\(1), + I3 => \reg_module_vsize[12]_i_2_n_0\, + O => \^mm2s_axi2ip_wrce\(3) + ); +\reg_module_vsize[12]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0800" + ) + port map ( + I0 => \out\(4), + I1 => p_0_out, + I2 => \out\(5), + I3 => \out\(2), + O => \reg_module_vsize[12]_i_2_n_0\ + ); +s_out_re: unisim.vcomponents.LUT3 + generic map( + INIT => X"28" + ) + port map ( + I0 => srst_d5, + I1 => s_out_d5, + I2 => s_out_d4, + O => \s_out_re__0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized7\ is + port ( + p_15_out : out STD_LOGIC; + \dmacr_i_reg[1]\ : out STD_LOGIC; + p_14_out : out STD_LOGIC; + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + prmtr_updt_complete_i_reg : out STD_LOGIC; + dma_interr_reg : out STD_LOGIC; + dma_interr_reg_0 : out STD_LOGIC; + \GEN_FOR_FLUSH.fsize_err_reg\ : out STD_LOGIC; + lsize_err_reg : out STD_LOGIC; + \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg\ : out STD_LOGIC; + ioc_irq_reg : out STD_LOGIC; + dly_irq_reg : out STD_LOGIC; + lsize_more_err_reg : out STD_LOGIC; + s2mm_axi2ip_wrce : out STD_LOGIC_VECTOR ( 7 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_lite_aclk : in STD_LOGIC; + prmry_reset2_0 : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + s2mm_dmacr : in STD_LOGIC_VECTOR ( 12 downto 0 ); + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\ : in STD_LOGIC_VECTOR ( 20 downto 0 ); + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31]\ : in STD_LOGIC; + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[23]\ : in STD_LOGIC; + s2mm_prmry_resetn : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); + prepare_wrce_d1 : in STD_LOGIC; + lite_wr_addr_phase_finished_data_phase_started : in STD_LOGIC; + wvalid : in STD_LOGIC; + s2mm_dma_interr_set_minus_frame_errors : in STD_LOGIC; + s2mm_fsize_more_or_sof_late : in STD_LOGIC; + fsize_mismatch_err : in STD_LOGIC; + dma_interr_reg_1 : in STD_LOGIC; + \GEN_FOR_FLUSH.fsize_err_reg_0\ : in STD_LOGIC; + lsize_mismatch_err : in STD_LOGIC; + lsize_err_reg_0 : in STD_LOGIC; + \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg_0\ : in STD_LOGIC; + s2mm_ioc_irq_set : in STD_LOGIC; + ioc_irq_reg_0 : in STD_LOGIC; + ch2_dly_irq_set : in STD_LOGIC; + dly_irq_reg_0 : in STD_LOGIC; + lsize_more_mismatch_err : in STD_LOGIC; + lsize_more_err_reg_0 : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized7\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized7\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized7\ is + signal \DMA_IRQ_MASK_GEN.dma_irq_mask_i[3]_i_2_n_0\ : STD_LOGIC; + signal \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_2__0_n_0\ : STD_LOGIC; + signal \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_3__0_n_0\ : STD_LOGIC; + signal \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_4__0_n_0\ : STD_LOGIC; + signal \ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_2__0_n_0\ : STD_LOGIC; + signal \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_2__0_n_0\ : STD_LOGIC; + signal \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_3__0_n_0\ : STD_LOGIC; + signal \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_4__0_n_0\ : STD_LOGIC; + signal \^dma_interr_reg_0\ : STD_LOGIC; + signal \dmacr_i[1]_i_2__0_n_0\ : STD_LOGIC; + signal \^dmacr_i_reg[1]\ : STD_LOGIC; + signal p_1_out : STD_LOGIC; + signal p_in_d1_cdc_from : STD_LOGIC; + signal prmry_in_xored : STD_LOGIC; + signal \reg_module_vsize[12]_i_2__0_n_0\ : STD_LOGIC; + signal s_out_d1_cdc_to : STD_LOGIC; + signal s_out_d2 : STD_LOGIC; + signal s_out_d3 : STD_LOGIC; + signal s_out_d4 : STD_LOGIC; + signal s_out_d5 : STD_LOGIC; + signal \s_out_re__0\ : STD_LOGIC; + signal srst_d1 : STD_LOGIC; + signal srst_d2 : STD_LOGIC; + signal srst_d3 : STD_LOGIC; + signal srst_d4 : STD_LOGIC; + signal srst_d5 : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \DMA_IRQ_MASK_GEN.dma_irq_mask_i[3]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \DMA_IRQ_MASK_GEN.dma_irq_mask_i[3]_i_2\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid[15]_i_1\ : label is "soft_lutpair6"; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "FDR"; + attribute box_type of \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\ : label is "PRIMITIVE"; + attribute SOFT_HLUTNM of \GEN_NUM_FSTORES_3.reg_module_start_address1_i[31]_i_1__0\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \GEN_NUM_FSTORES_3.reg_module_start_address2_i[31]_i_1__0\ : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of \GEN_NUM_FSTORES_3.reg_module_start_address3_i[31]_i_1__0\ : label is "soft_lutpair9"; + attribute SOFT_HLUTNM of \dma_interr_i_2__0\ : label is "soft_lutpair9"; + attribute SOFT_HLUTNM of \dmacr_i[1]_i_1__0\ : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of \dmacr_i[1]_i_2__0\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \ptr_ref_i[4]_i_1__0\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \reg_module_hsize[15]_i_1__0\ : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of \reg_module_vsize[12]_i_1__0\ : label is "soft_lutpair7"; +begin + dma_interr_reg_0 <= \^dma_interr_reg_0\; + \dmacr_i_reg[1]\ <= \^dmacr_i_reg[1]\; +\DMA_IRQ_MASK_GEN.dma_irq_mask_i[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0800" + ) + port map ( + I0 => \out\(0), + I1 => \out\(2), + I2 => \out\(5), + I3 => \DMA_IRQ_MASK_GEN.dma_irq_mask_i[3]_i_2_n_0\, + O => s2mm_axi2ip_wrce(1) + ); +\DMA_IRQ_MASK_GEN.dma_irq_mask_i[3]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4000" + ) + port map ( + I0 => \out\(4), + I1 => p_1_out, + I2 => \out\(3), + I3 => \out\(1), + O => \DMA_IRQ_MASK_GEN.dma_irq_mask_i[3]_i_2_n_0\ + ); +\DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid[15]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0400" + ) + port map ( + I0 => \out\(0), + I1 => \out\(5), + I2 => \out\(2), + I3 => \DMA_IRQ_MASK_GEN.dma_irq_mask_i[3]_i_2_n_0\, + O => s2mm_axi2ip_wrce(4) + ); +\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F6FFFFF6F0F0F0F0" + ) + port map ( + I0 => s2mm_dmacr(7), + I1 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(15), + I2 => \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_2__0_n_0\, + I3 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(16), + I4 => s2mm_dmacr(8), + I5 => \^dmacr_i_reg[1]\, + O => p_15_out + ); +\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FEFFFEFEFEFEFEFE" + ) + port map ( + I0 => \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_3__0_n_0\, + I1 => \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_4__0_n_0\, + I2 => \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31]\, + I3 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(18), + I4 => s2mm_dmacr(10), + I5 => \^dmacr_i_reg[1]\, + O => \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_2__0_n_0\ + ); +\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_3__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"40F0F040" + ) + port map ( + I0 => s2mm_dmacr(10), + I1 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(18), + I2 => \^dmacr_i_reg[1]\, + I3 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(17), + I4 => s2mm_dmacr(9), + O => \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_3__0_n_0\ + ); +\ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_4__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"40F0F040" + ) + port map ( + I0 => s2mm_dmacr(12), + I1 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(20), + I2 => \^dmacr_i_reg[1]\, + I3 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(19), + I4 => s2mm_dmacr(11), + O => \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_i_4__0_n_0\ + ); +\ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0002FFFF" + ) + port map ( + I0 => \ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_2__0_n_0\, + I1 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(9), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(8), + I3 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(7), + I4 => s2mm_prmry_resetn, + O => \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]\(0) + ); +\ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000100000000" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(12), + I1 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(13), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(10), + I3 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(11), + I4 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(14), + I5 => \^dmacr_i_reg[1]\, + O => \ENABLE_DMACR_FRM_CNTR.dmacr_i[23]_i_2__0_n_0\ + ); +\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F6FFFFF6F0F0F0F0" + ) + port map ( + I0 => s2mm_dmacr(1), + I1 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(7), + I2 => \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_2__0_n_0\, + I3 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(8), + I4 => s2mm_dmacr(2), + I5 => \^dmacr_i_reg[1]\, + O => p_14_out + ); +\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FEFFFEFEFEFEFEFE" + ) + port map ( + I0 => \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_3__0_n_0\, + I1 => \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_4__0_n_0\, + I2 => \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[23]\, + I3 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(10), + I4 => s2mm_dmacr(4), + I5 => \^dmacr_i_reg[1]\, + O => \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_2__0_n_0\ + ); +\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_3__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"40F0F040" + ) + port map ( + I0 => s2mm_dmacr(4), + I1 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(10), + I2 => \^dmacr_i_reg[1]\, + I3 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(9), + I4 => s2mm_dmacr(3), + O => \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_3__0_n_0\ + ); +\ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_4__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"40F0F040" + ) + port map ( + I0 => s2mm_dmacr(6), + I1 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(12), + I2 => \^dmacr_i_reg[1]\, + I3 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(11), + I4 => s2mm_dmacr(5), + O => \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_i_4__0_n_0\ + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_out_d1_cdc_to, + Q => s_out_d2, + R => prmry_reset2_0 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_out_d2, + Q => s_out_d3, + R => prmry_reset2_0 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_out_d3, + Q => s_out_d4, + R => prmry_reset2_0 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_s_out_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_out_d4, + Q => s_out_d5, + R => prmry_reset2_0 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \s_out_re__0\, + Q => p_1_out, + R => prmry_reset2_0 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN2_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => p_in_d1_cdc_from, + Q => s_out_d1_cdc_to, + R => prmry_reset2_0 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => prmry_in_xored, + Q => p_in_d1_cdc_from, + R => SR(0) + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_i_1__8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BF40" + ) + port map ( + I0 => prepare_wrce_d1, + I1 => lite_wr_addr_phase_finished_data_phase_started, + I2 => wvalid, + I3 => p_in_d1_cdc_from, + O => prmry_in_xored + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d1\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => '1', + Q => srst_d1, + R => prmry_reset2_0 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => srst_d1, + Q => srst_d2, + R => prmry_reset2_0 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => srst_d2, + Q => srst_d3, + R => prmry_reset2_0 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => srst_d3, + Q => srst_d4, + R => prmry_reset2_0 + ); +\GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_rst_d5\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => srst_d4, + Q => srst_d5, + R => prmry_reset2_0 + ); +\GEN_NUM_FSTORES_3.reg_module_start_address1_i[31]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0800" + ) + port map ( + I0 => \out\(0), + I1 => \out\(5), + I2 => \out\(2), + I3 => \DMA_IRQ_MASK_GEN.dma_irq_mask_i[3]_i_2_n_0\, + O => s2mm_axi2ip_wrce(5) + ); +\GEN_NUM_FSTORES_3.reg_module_start_address2_i[31]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => \out\(0), + I1 => \out\(5), + I2 => \dmacr_i[1]_i_2__0_n_0\, + O => s2mm_axi2ip_wrce(6) + ); +\GEN_NUM_FSTORES_3.reg_module_start_address3_i[31]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \out\(5), + I1 => \out\(0), + I2 => \dmacr_i[1]_i_2__0_n_0\, + O => s2mm_axi2ip_wrce(7) + ); +\I_DMA_REGISTER/GEN_FOR_FLUSH.fsize_err_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F7F0" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(1), + I1 => \^dma_interr_reg_0\, + I2 => fsize_mismatch_err, + I3 => \GEN_FOR_FLUSH.fsize_err_reg_0\, + O => \GEN_FOR_FLUSH.fsize_err_reg\ + ); +\I_DMA_REGISTER/GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F7F0" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(3), + I1 => \^dma_interr_reg_0\, + I2 => s2mm_fsize_more_or_sof_late, + I3 => \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg_0\, + O => \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg\ + ); +\I_DMA_REGISTER/dly_irq_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F7F0" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(5), + I1 => \^dma_interr_reg_0\, + I2 => ch2_dly_irq_set, + I3 => dly_irq_reg_0, + O => dly_irq_reg + ); +\I_DMA_REGISTER/dma_interr_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFF7FFFFFFF0" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(0), + I1 => \^dma_interr_reg_0\, + I2 => s2mm_dma_interr_set_minus_frame_errors, + I3 => s2mm_fsize_more_or_sof_late, + I4 => fsize_mismatch_err, + I5 => dma_interr_reg_1, + O => dma_interr_reg + ); +\I_DMA_REGISTER/ioc_irq_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F7F0" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(4), + I1 => \^dma_interr_reg_0\, + I2 => s2mm_ioc_irq_set, + I3 => ioc_irq_reg_0, + O => ioc_irq_reg + ); +\I_DMA_REGISTER/lsize_err_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F7F0" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(2), + I1 => \^dma_interr_reg_0\, + I2 => lsize_mismatch_err, + I3 => lsize_err_reg_0, + O => lsize_err_reg + ); +\I_DMA_REGISTER/lsize_more_err_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F7F0" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(6), + I1 => \^dma_interr_reg_0\, + I2 => lsize_more_mismatch_err, + I3 => lsize_more_err_reg_0, + O => lsize_more_err_reg + ); +\dma_interr_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => \out\(5), + I1 => \out\(0), + I2 => \dmacr_i[1]_i_2__0_n_0\, + O => \^dma_interr_reg_0\ + ); +\dmacr_i[1]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"10" + ) + port map ( + I0 => \out\(5), + I1 => \out\(0), + I2 => \dmacr_i[1]_i_2__0_n_0\, + O => \^dmacr_i_reg[1]\ + ); +\dmacr_i[1]_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00400000" + ) + port map ( + I0 => \out\(1), + I1 => \out\(3), + I2 => p_1_out, + I3 => \out\(4), + I4 => \out\(2), + O => \dmacr_i[1]_i_2__0_n_0\ + ); +\prmtr_updt_complete_i_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0400000000000000" + ) + port map ( + I0 => \out\(0), + I1 => \out\(5), + I2 => \out\(2), + I3 => \reg_module_vsize[12]_i_2__0_n_0\, + I4 => s2mm_prmry_resetn, + I5 => s2mm_dmacr(0), + O => prmtr_updt_complete_i_reg + ); +\ptr_ref_i[4]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0100" + ) + port map ( + I0 => \out\(0), + I1 => \out\(2), + I2 => \out\(5), + I3 => \DMA_IRQ_MASK_GEN.dma_irq_mask_i[3]_i_2_n_0\, + O => s2mm_axi2ip_wrce(0) + ); +\reg_module_hsize[15]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0800" + ) + port map ( + I0 => \out\(0), + I1 => \out\(5), + I2 => \out\(2), + I3 => \reg_module_vsize[12]_i_2__0_n_0\, + O => s2mm_axi2ip_wrce(3) + ); +\reg_module_vsize[12]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0400" + ) + port map ( + I0 => \out\(0), + I1 => \out\(5), + I2 => \out\(2), + I3 => \reg_module_vsize[12]_i_2__0_n_0\, + O => s2mm_axi2ip_wrce(2) + ); +\reg_module_vsize[12]_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0040" + ) + port map ( + I0 => \out\(4), + I1 => p_1_out, + I2 => \out\(3), + I3 => \out\(1), + O => \reg_module_vsize[12]_i_2__0_n_0\ + ); +s_out_re: unisim.vcomponents.LUT3 + generic map( + INIT => X"28" + ) + port map ( + I0 => srst_d5, + I1 => s_out_d5, + I2 => s_out_d4, + O => \s_out_re__0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized8\ is + port ( + mm2s_introut : out STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_lite_aclk : in STD_LOGIC; + prmry_reset2 : in STD_LOGIC; + p_78_out : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized8\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized8\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized8\ is + signal p_level_in_d1_cdc_from : STD_LOGIC; + signal s_level_out_d1_cdc_to : STD_LOGIC; + signal s_level_out_d2 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; +begin +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => p_level_in_d1_cdc_from, + Q => s_level_out_d1_cdc_to, + R => SR(0) + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_level_out_d1_cdc_to, + Q => s_level_out_d2, + R => SR(0) + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_level_out_d2, + Q => mm2s_introut, + R => SR(0) + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => p_78_out, + Q => p_level_in_d1_cdc_from, + R => prmry_reset2 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized9\ is + port ( + s2mm_introut : out STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_lite_aclk : in STD_LOGIC; + prmry_reset2_0 : in STD_LOGIC; + s2mm_ip2axi_introut : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized9\ : entity is "cdc_sync"; +end \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized9\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized9\ is + signal p_level_in_d1_cdc_from : STD_LOGIC; + signal s_level_out_d1_cdc_to : STD_LOGIC; + signal s_level_out_d2 : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute box_type : string; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "FDR"; + attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : label is "PRIMITIVE"; +begin +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => p_level_in_d1_cdc_from, + Q => s_level_out_d1_cdc_to, + R => SR(0) + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_level_out_d1_cdc_to, + Q => s_level_out_d2, + R => SR(0) + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_level_out_d2, + Q => s2mm_introut, + R => SR(0) + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s2mm_ip2axi_introut, + Q => p_level_in_d1_cdc_from, + R => prmry_reset2_0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f is + port ( + sig_ld_new_cmd_reg_reg : out STD_LOGIC; + sig_dqual_reg_empty_reg : out STD_LOGIC; + sig_next_calc_error_reg_reg : out STD_LOGIC; + sig_dqual_reg_empty_reg_0 : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 1 downto 0 ); + fifo_full_p1 : out STD_LOGIC; + FIFO_Full_reg : out STD_LOGIC_VECTOR ( 1 downto 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_dqual_reg_empty_reg_1 : out STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_ld_new_cmd_reg : in STD_LOGIC; + sig_next_calc_error_reg : in STD_LOGIC; + \sig_dbeat_cntr_reg[1]\ : in STD_LOGIC; + sig_dqual_reg_full_reg : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \sig_dbeat_cntr_reg[4]\ : in STD_LOGIC; + sig_wr_fifo : in STD_LOGIC; + p_11_out : in STD_LOGIC; + FIFO_Full_reg_0 : in STD_LOGIC; + sig_inhibit_rdy_n_reg : in STD_LOGIC; + sig_next_sequential_reg : in STD_LOGIC; + sig_last_dbeat_reg : in STD_LOGIC; + sig_dqual_reg_empty : in STD_LOGIC; + sig_halt_reg : in STD_LOGIC; + sig_m_valid_out_reg : in STD_LOGIC; + sig_s_ready_out_reg : in STD_LOGIC; + sig_wdc_status_going_full : in STD_LOGIC; + sig_inhibit_rdy_n_reg_0 : in STD_LOGIC; + sig_wsc2stat_status_valid : in STD_LOGIC; + sig_addr_posted_cntr : in STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_halt_reg_dly3 : in STD_LOGIC; + sig_last_mmap_dbeat_reg : in STD_LOGIC; + sig_posted_to_axi_reg : in STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f : entity is "cntr_incr_decr_addn_f"; +end Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f is + signal \^fifo_full_reg\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal addr_i_p1 : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \sig_addr_posted_cntr_max__1\ : STD_LOGIC; + signal \^sig_dqual_reg_empty_reg\ : STD_LOGIC; + signal \^sig_dqual_reg_empty_reg_0\ : STD_LOGIC; + signal \^sig_dqual_reg_empty_reg_1\ : STD_LOGIC; + signal sig_next_calc_error_reg_i_4_n_0 : STD_LOGIC; + signal sig_next_calc_error_reg_i_8_n_0 : STD_LOGIC; + signal sig_rd_empty : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FIFO_Full_i_1__8\ : label is "soft_lutpair240"; + attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[1]_i_1__8\ : label is "soft_lutpair240"; + attribute SOFT_HLUTNM of \sig_dbeat_cntr[6]_i_1__0\ : label is "soft_lutpair241"; + attribute SOFT_HLUTNM of \sig_dbeat_cntr[7]_i_1__0\ : label is "soft_lutpair242"; + attribute SOFT_HLUTNM of \sig_dbeat_cntr[7]_i_2__0\ : label is "soft_lutpair241"; + attribute SOFT_HLUTNM of sig_ld_new_cmd_reg_i_1 : label is "soft_lutpair242"; +begin + FIFO_Full_reg(1 downto 0) <= \^fifo_full_reg\(1 downto 0); + sig_dqual_reg_empty_reg <= \^sig_dqual_reg_empty_reg\; + sig_dqual_reg_empty_reg_0 <= \^sig_dqual_reg_empty_reg_0\; + sig_dqual_reg_empty_reg_1 <= \^sig_dqual_reg_empty_reg_1\; +\FIFO_Full_i_1__8\: unisim.vcomponents.LUT5 + generic map( + INIT => X"41100000" + ) + port map ( + I0 => sig_rd_empty, + I1 => \^sig_dqual_reg_empty_reg\, + I2 => sig_wr_fifo, + I3 => \^fifo_full_reg\(0), + I4 => \^fifo_full_reg\(1), + O => fifo_full_p1 + ); +\INFERRED_GEN.cnt_i[0]_i_1__8\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BB4BBBBB44B44444" + ) + port map ( + I0 => sig_rd_empty, + I1 => \^sig_dqual_reg_empty_reg\, + I2 => p_11_out, + I3 => FIFO_Full_reg_0, + I4 => sig_inhibit_rdy_n_reg, + I5 => \^fifo_full_reg\(0), + O => addr_i_p1(0) + ); +\INFERRED_GEN.cnt_i[1]_i_1__8\: unisim.vcomponents.LUT5 + generic map( + INIT => X"77E78818" + ) + port map ( + I0 => \^fifo_full_reg\(0), + I1 => sig_wr_fifo, + I2 => \^sig_dqual_reg_empty_reg\, + I3 => sig_rd_empty, + I4 => \^fifo_full_reg\(1), + O => addr_i_p1(1) + ); +\INFERRED_GEN.cnt_i[2]_i_1__8\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7F7F0180" + ) + port map ( + I0 => sig_wr_fifo, + I1 => \^fifo_full_reg\(0), + I2 => \^fifo_full_reg\(1), + I3 => \^sig_dqual_reg_empty_reg\, + I4 => sig_rd_empty, + O => addr_i_p1(2) + ); +\INFERRED_GEN.cnt_i_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => addr_i_p1(0), + Q => \^fifo_full_reg\(0), + S => sig_stream_rst + ); +\INFERRED_GEN.cnt_i_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => addr_i_p1(1), + Q => \^fifo_full_reg\(1), + S => sig_stream_rst + ); +\INFERRED_GEN.cnt_i_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => addr_i_p1(2), + Q => sig_rd_empty, + S => sig_stream_rst + ); +\sig_dbeat_cntr[6]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"41" + ) + port map ( + I0 => \^sig_dqual_reg_empty_reg\, + I1 => Q(0), + I2 => \sig_dbeat_cntr_reg[4]\, + O => D(0) + ); +\sig_dbeat_cntr[7]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"BA" + ) + port map ( + I0 => \^sig_dqual_reg_empty_reg\, + I1 => \sig_dbeat_cntr_reg[1]\, + I2 => \^sig_dqual_reg_empty_reg_0\, + O => E(0) + ); +\sig_dbeat_cntr[7]_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4441" + ) + port map ( + I0 => \^sig_dqual_reg_empty_reg\, + I1 => Q(1), + I2 => \sig_dbeat_cntr_reg[4]\, + I3 => Q(0), + O => D(1) + ); +sig_ld_new_cmd_reg_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => \^sig_dqual_reg_empty_reg\, + I1 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I2 => sig_ld_new_cmd_reg, + O => sig_ld_new_cmd_reg_reg + ); +sig_next_calc_error_reg_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"10000000FFFFFFFF" + ) + port map ( + I0 => \^sig_dqual_reg_empty_reg\, + I1 => sig_next_calc_error_reg, + I2 => \^sig_dqual_reg_empty_reg_0\, + I3 => \sig_dbeat_cntr_reg[1]\, + I4 => sig_dqual_reg_full_reg, + I5 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + O => sig_next_calc_error_reg_reg + ); +sig_next_calc_error_reg_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAAA8000" + ) + port map ( + I0 => sig_next_calc_error_reg_i_4_n_0, + I1 => sig_next_sequential_reg, + I2 => sig_last_dbeat_reg, + I3 => \^sig_dqual_reg_empty_reg_0\, + I4 => sig_dqual_reg_empty, + O => \^sig_dqual_reg_empty_reg\ + ); +sig_next_calc_error_reg_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"4440000000000000" + ) + port map ( + I0 => sig_next_calc_error_reg, + I1 => sig_dqual_reg_full_reg, + I2 => sig_halt_reg, + I3 => sig_m_valid_out_reg, + I4 => \^sig_dqual_reg_empty_reg_1\, + I5 => sig_s_ready_out_reg, + O => \^sig_dqual_reg_empty_reg_0\ + ); +sig_next_calc_error_reg_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000001011" + ) + port map ( + I0 => \sig_addr_posted_cntr_max__1\, + I1 => sig_wdc_status_going_full, + I2 => sig_inhibit_rdy_n_reg_0, + I3 => sig_wsc2stat_status_valid, + I4 => sig_rd_empty, + I5 => sig_next_calc_error_reg, + O => sig_next_calc_error_reg_i_4_n_0 + ); +sig_next_calc_error_reg_i_5: unisim.vcomponents.LUT6 + generic map( + INIT => X"00FEFEFE00000000" + ) + port map ( + I0 => sig_addr_posted_cntr(1), + I1 => sig_addr_posted_cntr(0), + I2 => sig_addr_posted_cntr(2), + I3 => sig_halt_reg_dly3, + I4 => sig_next_calc_error_reg, + I5 => sig_next_calc_error_reg_i_8_n_0, + O => \^sig_dqual_reg_empty_reg_1\ + ); +sig_next_calc_error_reg_i_6: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => sig_addr_posted_cntr(1), + I1 => sig_addr_posted_cntr(0), + I2 => sig_addr_posted_cntr(2), + O => \sig_addr_posted_cntr_max__1\ + ); +sig_next_calc_error_reg_i_8: unisim.vcomponents.LUT6 + generic map( + INIT => X"55555555FFFFFDFF" + ) + port map ( + I0 => sig_last_mmap_dbeat_reg, + I1 => sig_addr_posted_cntr(1), + I2 => sig_addr_posted_cntr(2), + I3 => sig_addr_posted_cntr(0), + I4 => sig_posted_to_axi_reg, + I5 => sig_halt_reg, + O => sig_next_calc_error_reg_i_8_n_0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_16 is + port ( + fifo_full_p1 : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_input_reg_empty : in STD_LOGIC; + sig_psm_halt : in STD_LOGIC; + sig_wr_fifo : in STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_16 : entity is "cntr_incr_decr_addn_f"; +end Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_16; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_16 is + signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal addr_i_p1 : STD_LOGIC_VECTOR ( 2 downto 0 ); +begin + Q(2 downto 0) <= \^q\(2 downto 0); +\FIFO_Full_i_1__4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0451510000000000" + ) + port map ( + I0 => \^q\(2), + I1 => sig_input_reg_empty, + I2 => sig_psm_halt, + I3 => sig_wr_fifo, + I4 => \^q\(0), + I5 => \^q\(1), + O => fifo_full_p1 + ); +\INFERRED_GEN.cnt_i[0]_i_1__4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"04FBFB04" + ) + port map ( + I0 => \^q\(2), + I1 => sig_input_reg_empty, + I2 => sig_psm_halt, + I3 => sig_wr_fifo, + I4 => \^q\(0), + O => addr_i_p1(0) + ); +\INFERRED_GEN.cnt_i[1]_i_1__4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"77777E7788888188" + ) + port map ( + I0 => \^q\(0), + I1 => sig_wr_fifo, + I2 => sig_psm_halt, + I3 => sig_input_reg_empty, + I4 => \^q\(2), + I5 => \^q\(1), + O => addr_i_p1(1) + ); +\INFERRED_GEN.cnt_i[2]_i_1__4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7F7F7F7F80018080" + ) + port map ( + I0 => sig_wr_fifo, + I1 => \^q\(0), + I2 => \^q\(1), + I3 => sig_psm_halt, + I4 => sig_input_reg_empty, + I5 => \^q\(2), + O => addr_i_p1(2) + ); +\INFERRED_GEN.cnt_i_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => addr_i_p1(0), + Q => \^q\(0), + S => sig_stream_rst + ); +\INFERRED_GEN.cnt_i_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => addr_i_p1(1), + Q => \^q\(1), + S => sig_stream_rst + ); +\INFERRED_GEN.cnt_i_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => addr_i_p1(2), + Q => \^q\(2), + S => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_17 is + port ( + p_9_out : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); + fifo_full_p1 : out STD_LOGIC; + s2mm_halt : in STD_LOGIC; + s2mm_soft_reset : in STD_LOGIC; + dma_err : in STD_LOGIC; + CO : in STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axis_s2mm_sts_tready : in STD_LOGIC; + sig_wr_fifo : in STD_LOGIC; + sig_wsc2stat_status_valid : in STD_LOGIC; + FIFO_Full_reg : in STD_LOGIC; + sig_inhibit_rdy_n : in STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_17 : entity is "cntr_incr_decr_addn_f"; +end Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_17; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_17 is + signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal addr_i_p1 : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FIFO_Full_i_1__11\ : label is "soft_lutpair236"; + attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[2]_i_1__11\ : label is "soft_lutpair236"; +begin + Q(2 downto 0) <= \^q\(2 downto 0); +\FIFO_Full_i_1__11\: unisim.vcomponents.LUT5 + generic map( + INIT => X"41100000" + ) + port map ( + I0 => \^q\(2), + I1 => m_axis_s2mm_sts_tready, + I2 => sig_wr_fifo, + I3 => \^q\(0), + I4 => \^q\(1), + O => fifo_full_p1 + ); +\GEN_STS_GRTR_THAN_8.ovrflo_err_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000010000" + ) + port map ( + I0 => s2mm_halt, + I1 => s2mm_soft_reset, + I2 => dma_err, + I3 => \^q\(2), + I4 => CO(0), + I5 => \out\(0), + O => p_9_out + ); +\INFERRED_GEN.cnt_i[0]_i_1__11\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BB4BBBBB44B44444" + ) + port map ( + I0 => \^q\(2), + I1 => m_axis_s2mm_sts_tready, + I2 => sig_wsc2stat_status_valid, + I3 => FIFO_Full_reg, + I4 => sig_inhibit_rdy_n, + I5 => \^q\(0), + O => addr_i_p1(0) + ); +\INFERRED_GEN.cnt_i[1]_i_1__11\: unisim.vcomponents.LUT5 + generic map( + INIT => X"77E78818" + ) + port map ( + I0 => \^q\(0), + I1 => sig_wr_fifo, + I2 => m_axis_s2mm_sts_tready, + I3 => \^q\(2), + I4 => \^q\(1), + O => addr_i_p1(1) + ); +\INFERRED_GEN.cnt_i[2]_i_1__11\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7F7F0180" + ) + port map ( + I0 => sig_wr_fifo, + I1 => \^q\(0), + I2 => \^q\(1), + I3 => m_axis_s2mm_sts_tready, + I4 => \^q\(2), + O => addr_i_p1(2) + ); +\INFERRED_GEN.cnt_i_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => addr_i_p1(0), + Q => \^q\(0), + S => sig_stream_rst + ); +\INFERRED_GEN.cnt_i_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => addr_i_p1(1), + Q => \^q\(1), + S => sig_stream_rst + ); +\INFERRED_GEN.cnt_i_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => addr_i_p1(2), + Q => \^q\(2), + S => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_18 is + port ( + sig_calc_error_reg_reg : out STD_LOGIC; + fifo_full_p1 : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); + sig_halt_reg : in STD_LOGIC; + sig_addr_reg_empty_reg : in STD_LOGIC; + sig_wr_fifo : in STD_LOGIC; + p_22_out : in STD_LOGIC; + FIFO_Full_reg : in STD_LOGIC; + sig_inhibit_rdy_n_reg : in STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_18 : entity is "cntr_incr_decr_addn_f"; +end Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_18; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_18 is + signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal addr_i_p1 : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \^sig_calc_error_reg_reg\ : STD_LOGIC; + signal sig_rd_empty : STD_LOGIC; +begin + Q(1 downto 0) <= \^q\(1 downto 0); + sig_calc_error_reg_reg <= \^sig_calc_error_reg_reg\; +\FIFO_Full_i_1__7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0451510000000000" + ) + port map ( + I0 => sig_rd_empty, + I1 => sig_addr_reg_empty_reg, + I2 => sig_halt_reg, + I3 => sig_wr_fifo, + I4 => \^q\(0), + I5 => \^q\(1), + O => fifo_full_p1 + ); +\INFERRED_GEN.cnt_i[0]_i_1__7\: unisim.vcomponents.LUT5 + generic map( + INIT => X"5955A6AA" + ) + port map ( + I0 => \^sig_calc_error_reg_reg\, + I1 => p_22_out, + I2 => FIFO_Full_reg, + I3 => sig_inhibit_rdy_n_reg, + I4 => \^q\(0), + O => addr_i_p1(0) + ); +\INFERRED_GEN.cnt_i[1]_i_1__7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AEAAF7FF51550800" + ) + port map ( + I0 => \^q\(0), + I1 => p_22_out, + I2 => FIFO_Full_reg, + I3 => sig_inhibit_rdy_n_reg, + I4 => \^sig_calc_error_reg_reg\, + I5 => \^q\(1), + O => addr_i_p1(1) + ); +\INFERRED_GEN.cnt_i[2]_i_1__7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7F7F7F7F80018080" + ) + port map ( + I0 => sig_wr_fifo, + I1 => \^q\(0), + I2 => \^q\(1), + I3 => sig_halt_reg, + I4 => sig_addr_reg_empty_reg, + I5 => sig_rd_empty, + O => addr_i_p1(2) + ); +\INFERRED_GEN.cnt_i_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => addr_i_p1(0), + Q => \^q\(0), + S => sig_stream_rst + ); +\INFERRED_GEN.cnt_i_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => addr_i_p1(1), + Q => \^q\(1), + S => sig_stream_rst + ); +\INFERRED_GEN.cnt_i_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => addr_i_p1(2), + Q => sig_rd_empty, + S => sig_stream_rst + ); +\sig_next_addr_reg[31]_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => sig_halt_reg, + I1 => sig_addr_reg_empty_reg, + I2 => sig_rd_empty, + O => \^sig_calc_error_reg_reg\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_19 is + port ( + Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); + fifo_full_p1 : out STD_LOGIC; + sig_sm_ld_dre_cmd_ns : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 1 downto 0 ); + sig_need_cmd_flush : in STD_LOGIC; + p_7_out : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_sm_pop_cmd_fifo : in STD_LOGIC; + sig_wr_fifo : in STD_LOGIC; + p_9_out_0 : in STD_LOGIC; + FIFO_Full_reg : in STD_LOGIC; + sig_inhibit_rdy_n_reg : in STD_LOGIC; + \FSM_sequential_sig_cmdcntl_sm_state_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_cmd_empty_reg : in STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[2]_0\ : in STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_19 : entity is "cntr_incr_decr_addn_f"; +end Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_19; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_19 is + signal \FSM_sequential_sig_cmdcntl_sm_state[0]_i_2_n_0\ : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal addr_i_p1 : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal sig_sm_ld_dre_cmd_i_2_n_0 : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FIFO_Full_i_1__9\ : label is "soft_lutpair233"; + attribute SOFT_HLUTNM of \FSM_sequential_sig_cmdcntl_sm_state[0]_i_2\ : label is "soft_lutpair234"; + attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[2]_i_1__9\ : label is "soft_lutpair233"; + attribute SOFT_HLUTNM of sig_sm_ld_dre_cmd_i_2 : label is "soft_lutpair234"; +begin + Q(2 downto 0) <= \^q\(2 downto 0); +\FIFO_Full_i_1__9\: unisim.vcomponents.LUT5 + generic map( + INIT => X"41100000" + ) + port map ( + I0 => \^q\(2), + I1 => sig_sm_pop_cmd_fifo, + I2 => sig_wr_fifo, + I3 => \^q\(0), + I4 => \^q\(1), + O => fifo_full_p1 + ); +\FSM_sequential_sig_cmdcntl_sm_state[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000F0B0FF00FF30F" + ) + port map ( + I0 => \FSM_sequential_sig_cmdcntl_sm_state[0]_i_2_n_0\, + I1 => sig_cmd_empty_reg, + I2 => \FSM_sequential_sig_cmdcntl_sm_state_reg[2]\(2), + I3 => \FSM_sequential_sig_cmdcntl_sm_state_reg[2]\(0), + I4 => \INFERRED_GEN.cnt_i_reg[2]_0\, + I5 => \FSM_sequential_sig_cmdcntl_sm_state_reg[2]\(1), + O => D(0) + ); +\FSM_sequential_sig_cmdcntl_sm_state[0]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => sig_need_cmd_flush, + I1 => \^q\(2), + O => \FSM_sequential_sig_cmdcntl_sm_state[0]_i_2_n_0\ + ); +\FSM_sequential_sig_cmdcntl_sm_state[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000540000FF5000" + ) + port map ( + I0 => \^q\(2), + I1 => sig_need_cmd_flush, + I2 => \out\(0), + I3 => \FSM_sequential_sig_cmdcntl_sm_state_reg[2]\(0), + I4 => \FSM_sequential_sig_cmdcntl_sm_state_reg[2]\(2), + I5 => \FSM_sequential_sig_cmdcntl_sm_state_reg[2]\(1), + O => D(1) + ); +\INFERRED_GEN.cnt_i[0]_i_1__9\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BB4BBBBB44B44444" + ) + port map ( + I0 => \^q\(2), + I1 => sig_sm_pop_cmd_fifo, + I2 => p_9_out_0, + I3 => FIFO_Full_reg, + I4 => sig_inhibit_rdy_n_reg, + I5 => \^q\(0), + O => addr_i_p1(0) + ); +\INFERRED_GEN.cnt_i[1]_i_1__9\: unisim.vcomponents.LUT5 + generic map( + INIT => X"77E78818" + ) + port map ( + I0 => \^q\(0), + I1 => sig_wr_fifo, + I2 => sig_sm_pop_cmd_fifo, + I3 => \^q\(2), + I4 => \^q\(1), + O => addr_i_p1(1) + ); +\INFERRED_GEN.cnt_i[2]_i_1__9\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7F7F0180" + ) + port map ( + I0 => sig_wr_fifo, + I1 => \^q\(0), + I2 => \^q\(1), + I3 => sig_sm_pop_cmd_fifo, + I4 => \^q\(2), + O => addr_i_p1(2) + ); +\INFERRED_GEN.cnt_i_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => addr_i_p1(0), + Q => \^q\(0), + S => sig_stream_rst + ); +\INFERRED_GEN.cnt_i_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => addr_i_p1(1), + Q => \^q\(1), + S => sig_stream_rst + ); +\INFERRED_GEN.cnt_i_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => addr_i_p1(2), + Q => \^q\(2), + S => sig_stream_rst + ); +sig_sm_ld_dre_cmd_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"4040404000404040" + ) + port map ( + I0 => \FSM_sequential_sig_cmdcntl_sm_state_reg[2]\(2), + I1 => \FSM_sequential_sig_cmdcntl_sm_state_reg[2]\(0), + I2 => sig_sm_ld_dre_cmd_i_2_n_0, + I3 => \FSM_sequential_sig_cmdcntl_sm_state_reg[2]\(1), + I4 => sig_need_cmd_flush, + I5 => \^q\(2), + O => sig_sm_ld_dre_cmd_ns + ); +sig_sm_ld_dre_cmd_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"02" + ) + port map ( + I0 => p_7_out, + I1 => \^q\(2), + I2 => \out\(0), + O => sig_sm_ld_dre_cmd_i_2_n_0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_21 is + port ( + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_dqual_reg_empty_reg : out STD_LOGIC; + sig_next_cmd_cmplt_reg_reg : out STD_LOGIC; + sig_dqual_reg_empty_reg_0 : out STD_LOGIC; + fifo_full_p1 : out STD_LOGIC; + FIFO_Full_reg : out STD_LOGIC_VECTOR ( 1 downto 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \sig_dbeat_cntr_reg[0]\ : in STD_LOGIC; + m_axi_mm2s_rlast : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + FIFO_Full_reg_0 : in STD_LOGIC; + sig_mstr2data_cmd_valid : in STD_LOGIC; + sig_inhibit_rdy_n_0 : in STD_LOGIC; + FIFO_Full_reg_1 : in STD_LOGIC; + \sig_dbeat_cntr_reg[5]\ : in STD_LOGIC; + sig_next_sequential_reg : in STD_LOGIC; + sig_last_dbeat : in STD_LOGIC; + sig_dqual_reg_empty : in STD_LOGIC; + sig_rsc2stat_status_valid : in STD_LOGIC; + FIFO_Full_reg_2 : in STD_LOGIC; + sig_inhibit_rdy_n : in STD_LOGIC; + sig_next_calc_error_reg_reg : in STD_LOGIC; + \sig_addr_posted_cntr_reg[2]\ : in STD_LOGIC; + \sig_addr_posted_cntr_reg[1]\ : in STD_LOGIC; + \sig_addr_posted_cntr_reg[0]\ : in STD_LOGIC; + ram_full_i_reg : in STD_LOGIC; + sig_halt_reg_reg : in STD_LOGIC; + m_axi_mm2s_rvalid : in STD_LOGIC; + sig_dqual_reg_full : in STD_LOGIC; + sig_data2rsc_valid : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_21 : entity is "cntr_incr_decr_addn_f"; +end Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_21; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_21 is + signal \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\ : STD_LOGIC; + signal \^fifo_full_reg\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal addr_i_p1 : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \^sig_dqual_reg_empty_reg\ : STD_LOGIC; + signal \^sig_dqual_reg_empty_reg_0\ : STD_LOGIC; + signal sig_next_cmd_cmplt_reg_i_4_n_0 : STD_LOGIC; + signal sig_next_cmd_cmplt_reg_i_5_n_0 : STD_LOGIC; + signal sig_rd_empty : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FIFO_Full_i_1__0\ : label is "soft_lutpair160"; + attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[2]_i_1__0\ : label is "soft_lutpair160"; + attribute SOFT_HLUTNM of \sig_dbeat_cntr[5]_i_1__0\ : label is "soft_lutpair159"; + attribute SOFT_HLUTNM of \sig_dbeat_cntr[6]_i_1\ : label is "soft_lutpair159"; +begin + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ <= \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\; + FIFO_Full_reg(1 downto 0) <= \^fifo_full_reg\(1 downto 0); + sig_dqual_reg_empty_reg <= \^sig_dqual_reg_empty_reg\; + sig_dqual_reg_empty_reg_0 <= \^sig_dqual_reg_empty_reg_0\; +\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFF01FFFF" + ) + port map ( + I0 => \sig_addr_posted_cntr_reg[0]\, + I1 => \sig_addr_posted_cntr_reg[2]\, + I2 => \sig_addr_posted_cntr_reg[1]\, + I3 => sig_next_calc_error_reg_reg, + I4 => sig_dqual_reg_full, + I5 => sig_data2rsc_valid, + O => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\ + ); +\FIFO_Full_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80009200" + ) + port map ( + I0 => \^fifo_full_reg\(0), + I1 => \^sig_dqual_reg_empty_reg\, + I2 => FIFO_Full_reg_0, + I3 => \^fifo_full_reg\(1), + I4 => sig_rd_empty, + O => fifo_full_p1 + ); +\INFERRED_GEN.cnt_i[0]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"5595AA6A" + ) + port map ( + I0 => \^fifo_full_reg\(0), + I1 => sig_mstr2data_cmd_valid, + I2 => sig_inhibit_rdy_n_0, + I3 => FIFO_Full_reg_1, + I4 => \^sig_dqual_reg_empty_reg\, + O => addr_i_p1(0) + ); +\INFERRED_GEN.cnt_i[1]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAEAFF7F55150080" + ) + port map ( + I0 => \^fifo_full_reg\(0), + I1 => sig_mstr2data_cmd_valid, + I2 => sig_inhibit_rdy_n_0, + I3 => FIFO_Full_reg_1, + I4 => \^sig_dqual_reg_empty_reg\, + I5 => \^fifo_full_reg\(1), + O => addr_i_p1(1) + ); +\INFERRED_GEN.cnt_i[2]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"006A03AA" + ) + port map ( + I0 => sig_rd_empty, + I1 => \^fifo_full_reg\(1), + I2 => FIFO_Full_reg_0, + I3 => \^sig_dqual_reg_empty_reg\, + I4 => \^fifo_full_reg\(0), + O => addr_i_p1(2) + ); +\INFERRED_GEN.cnt_i_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => addr_i_p1(0), + Q => \^fifo_full_reg\(0), + S => SR(0) + ); +\INFERRED_GEN.cnt_i_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => addr_i_p1(1), + Q => \^fifo_full_reg\(1), + S => SR(0) + ); +\INFERRED_GEN.cnt_i_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => addr_i_p1(2), + Q => sig_rd_empty, + S => SR(0) + ); +\sig_dbeat_cntr[5]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00D2" + ) + port map ( + I0 => \sig_dbeat_cntr_reg[0]\, + I1 => Q(0), + I2 => Q(1), + I3 => \^sig_dqual_reg_empty_reg\, + O => D(0) + ); +\sig_dbeat_cntr[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000FD02" + ) + port map ( + I0 => \sig_dbeat_cntr_reg[0]\, + I1 => Q(1), + I2 => Q(0), + I3 => Q(2), + I4 => \^sig_dqual_reg_empty_reg\, + O => D(1) + ); +\sig_dbeat_cntr[7]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FBAA" + ) + port map ( + I0 => \^sig_dqual_reg_empty_reg\, + I1 => \sig_dbeat_cntr_reg[0]\, + I2 => \sig_dbeat_cntr_reg[5]\, + I3 => \^sig_dqual_reg_empty_reg_0\, + O => E(0) + ); +\sig_dbeat_cntr[7]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FFEF0010" + ) + port map ( + I0 => Q(0), + I1 => Q(1), + I2 => \sig_dbeat_cntr_reg[0]\, + I3 => Q(2), + I4 => Q(3), + I5 => \^sig_dqual_reg_empty_reg\, + O => D(2) + ); +sig_next_cmd_cmplt_reg_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"40FF" + ) + port map ( + I0 => \^sig_dqual_reg_empty_reg\, + I1 => m_axi_mm2s_rlast, + I2 => \^sig_dqual_reg_empty_reg_0\, + I3 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + O => sig_next_cmd_cmplt_reg_reg + ); +sig_next_cmd_cmplt_reg_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000FF80" + ) + port map ( + I0 => \^sig_dqual_reg_empty_reg_0\, + I1 => sig_next_sequential_reg, + I2 => sig_last_dbeat, + I3 => sig_dqual_reg_empty, + I4 => sig_next_cmd_cmplt_reg_i_4_n_0, + O => \^sig_dqual_reg_empty_reg\ + ); +sig_next_cmd_cmplt_reg_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"00D0" + ) + port map ( + I0 => ram_full_i_reg, + I1 => sig_halt_reg_reg, + I2 => m_axi_mm2s_rvalid, + I3 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\, + O => \^sig_dqual_reg_empty_reg_0\ + ); +sig_next_cmd_cmplt_reg_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFEAEE" + ) + port map ( + I0 => sig_next_cmd_cmplt_reg_i_5_n_0, + I1 => sig_rsc2stat_status_valid, + I2 => FIFO_Full_reg_2, + I3 => sig_inhibit_rdy_n, + I4 => sig_next_calc_error_reg_reg, + I5 => sig_rd_empty, + O => sig_next_cmd_cmplt_reg_i_4_n_0 + ); +sig_next_cmd_cmplt_reg_i_5: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \sig_addr_posted_cntr_reg[2]\, + I1 => \sig_addr_posted_cntr_reg[1]\, + I2 => \sig_addr_posted_cntr_reg[0]\, + O => sig_next_cmd_cmplt_reg_i_5_n_0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_25 is + port ( + fifo_full_p1 : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_calc_error_pushed_reg : in STD_LOGIC; + sig_wr_fifo : in STD_LOGIC; + sig_calc_error_pushed : in STD_LOGIC; + sig_sm_halt_reg : in STD_LOGIC; + sig_input_reg_empty : in STD_LOGIC; + p_56_out : in STD_LOGIC; + FIFO_Full_reg : in STD_LOGIC; + sig_inhibit_rdy_n : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_25 : entity is "cntr_incr_decr_addn_f"; +end Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_25; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_25 is + signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal addr_i_p1 : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of FIFO_Full_i_1 : label is "soft_lutpair132"; + attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[2]_i_1\ : label is "soft_lutpair132"; +begin + Q(2 downto 0) <= \^q\(2 downto 0); +FIFO_Full_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"80008220" + ) + port map ( + I0 => \^q\(1), + I1 => sig_calc_error_pushed_reg, + I2 => \^q\(0), + I3 => sig_wr_fifo, + I4 => \^q\(2), + O => fifo_full_p1 + ); +\INFERRED_GEN.cnt_i[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"6666666666696666" + ) + port map ( + I0 => \^q\(0), + I1 => sig_wr_fifo, + I2 => sig_calc_error_pushed, + I3 => sig_sm_halt_reg, + I4 => sig_input_reg_empty, + I5 => \^q\(2), + O => addr_i_p1(0) + ); +\INFERRED_GEN.cnt_i[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AA9AAAAA66A66666" + ) + port map ( + I0 => \^q\(1), + I1 => sig_calc_error_pushed_reg, + I2 => p_56_out, + I3 => FIFO_Full_reg, + I4 => sig_inhibit_rdy_n, + I5 => \^q\(0), + O => addr_i_p1(1) + ); +\INFERRED_GEN.cnt_i[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"006A03AA" + ) + port map ( + I0 => \^q\(2), + I1 => sig_wr_fifo, + I2 => \^q\(0), + I3 => sig_calc_error_pushed_reg, + I4 => \^q\(1), + O => addr_i_p1(2) + ); +\INFERRED_GEN.cnt_i_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => addr_i_p1(0), + Q => \^q\(0), + S => SR(0) + ); +\INFERRED_GEN.cnt_i_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => addr_i_p1(1), + Q => \^q\(1), + S => SR(0) + ); +\INFERRED_GEN.cnt_i_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => addr_i_p1(2), + Q => \^q\(2), + S => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_27 is + port ( + fifo_full_p1 : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_wr_fifo : in STD_LOGIC; + p_58_out : in STD_LOGIC; + sig_inhibit_rdy_n_reg : in STD_LOGIC; + FIFO_Full_reg : in STD_LOGIC; + sig_rsc2stat_status_valid : in STD_LOGIC; + sts_tready_reg : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_27 : entity is "cntr_incr_decr_addn_f"; +end Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_27; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_27 is + signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal addr_i_p1 : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FIFO_Full_i_1__3\ : label is "soft_lutpair130"; + attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[2]_i_1__3\ : label is "soft_lutpair130"; +begin + Q(2 downto 0) <= \^q\(2 downto 0); +\FIFO_Full_i_1__3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"08060000" + ) + port map ( + I0 => sig_wr_fifo, + I1 => \^q\(0), + I2 => \^q\(2), + I3 => p_58_out, + I4 => \^q\(1), + O => fifo_full_p1 + ); +\INFERRED_GEN.cnt_i[0]_i_1__3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"DFDF20DF2020DF20" + ) + port map ( + I0 => sig_inhibit_rdy_n_reg, + I1 => FIFO_Full_reg, + I2 => sig_rsc2stat_status_valid, + I3 => p_58_out, + I4 => \^q\(2), + I5 => \^q\(0), + O => addr_i_p1(0) + ); +\INFERRED_GEN.cnt_i[1]_i_1__3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AEAAF7FF51550800" + ) + port map ( + I0 => \^q\(0), + I1 => sig_inhibit_rdy_n_reg, + I2 => FIFO_Full_reg, + I3 => sig_rsc2stat_status_valid, + I4 => sts_tready_reg, + I5 => \^q\(1), + O => addr_i_p1(1) + ); +\INFERRED_GEN.cnt_i[2]_i_1__3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"52F0F0F4" + ) + port map ( + I0 => \^q\(1), + I1 => p_58_out, + I2 => \^q\(2), + I3 => \^q\(0), + I4 => sig_wr_fifo, + O => addr_i_p1(2) + ); +\INFERRED_GEN.cnt_i_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => addr_i_p1(0), + Q => \^q\(0), + S => SR(0) + ); +\INFERRED_GEN.cnt_i_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => addr_i_p1(1), + Q => \^q\(1), + S => SR(0) + ); +\INFERRED_GEN.cnt_i_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => addr_i_p1(2), + Q => \^q\(2), + S => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_28 is + port ( + sig_posted_to_axi_2_reg : out STD_LOGIC; + fifo_full_p1 : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); + sig_addr_reg_empty_reg : out STD_LOGIC; + sig_addr_reg_empty : in STD_LOGIC; + sig_sf_allow_addr_req : in STD_LOGIC; + sig_data2addr_stop_req : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + FIFO_Full_reg : in STD_LOGIC; + FIFO_Full_reg_0 : in STD_LOGIC; + sig_inhibit_rdy_n : in STD_LOGIC; + sig_mstr2addr_cmd_valid : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_28 : entity is "cntr_incr_decr_addn_f"; +end Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_28; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_28 is + signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal addr_i_p1 : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \^sig_addr_reg_empty_reg\ : STD_LOGIC; + signal sig_rd_empty : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FIFO_Full_i_1__1\ : label is "soft_lutpair128"; + attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[2]_i_1__1\ : label is "soft_lutpair128"; + attribute SOFT_HLUTNM of \sig_next_addr_reg[31]_i_2\ : label is "soft_lutpair129"; + attribute SOFT_HLUTNM of sig_posted_to_axi_2_i_1 : label is "soft_lutpair129"; +begin + Q(1 downto 0) <= \^q\(1 downto 0); + sig_addr_reg_empty_reg <= \^sig_addr_reg_empty_reg\; +\FIFO_Full_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80008208" + ) + port map ( + I0 => \^q\(1), + I1 => FIFO_Full_reg, + I2 => \^sig_addr_reg_empty_reg\, + I3 => \^q\(0), + I4 => sig_rd_empty, + O => fifo_full_p1 + ); +\INFERRED_GEN.cnt_i[0]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"69666666" + ) + port map ( + I0 => \^q\(0), + I1 => \^sig_addr_reg_empty_reg\, + I2 => FIFO_Full_reg_0, + I3 => sig_inhibit_rdy_n, + I4 => sig_mstr2addr_cmd_valid, + O => addr_i_p1(0) + ); +\INFERRED_GEN.cnt_i[1]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"A69AA6A6A6A6A6A6" + ) + port map ( + I0 => \^q\(1), + I1 => \^sig_addr_reg_empty_reg\, + I2 => \^q\(0), + I3 => FIFO_Full_reg_0, + I4 => sig_inhibit_rdy_n, + I5 => sig_mstr2addr_cmd_valid, + O => addr_i_p1(1) + ); +\INFERRED_GEN.cnt_i[2]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"060A0A3A" + ) + port map ( + I0 => sig_rd_empty, + I1 => \^q\(0), + I2 => \^sig_addr_reg_empty_reg\, + I3 => FIFO_Full_reg, + I4 => \^q\(1), + O => addr_i_p1(2) + ); +\INFERRED_GEN.cnt_i_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => addr_i_p1(0), + Q => \^q\(0), + S => SR(0) + ); +\INFERRED_GEN.cnt_i_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => addr_i_p1(1), + Q => \^q\(1), + S => SR(0) + ); +\INFERRED_GEN.cnt_i_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => addr_i_p1(2), + Q => sig_rd_empty, + S => SR(0) + ); +\sig_next_addr_reg[31]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0040" + ) + port map ( + I0 => sig_data2addr_stop_req, + I1 => sig_sf_allow_addr_req, + I2 => sig_addr_reg_empty, + I3 => sig_rd_empty, + O => \^sig_addr_reg_empty_reg\ + ); +sig_posted_to_axi_2_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"00400000" + ) + port map ( + I0 => sig_rd_empty, + I1 => sig_addr_reg_empty, + I2 => sig_sf_allow_addr_req, + I3 => sig_data2addr_stop_req, + I4 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + O => sig_posted_to_axi_2_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_29 is + port ( + fifo_full_p1 : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); + FIFO_Full_reg : out STD_LOGIC; + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : in STD_LOGIC; + FIFO_Full_reg_0 : in STD_LOGIC; + sig_inhibit_rdy_n_reg : in STD_LOGIC; + sig_mstr2sf_cmd_valid : in STD_LOGIC; + DOBDO : in STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : in STD_LOGIC; + lsig_cmd_loaded : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_29 : entity is "cntr_incr_decr_addn_f"; +end Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_29; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_29 is + signal \^fifo_full_reg\ : STD_LOGIC; + signal \INFERRED_GEN.cnt_i[1]_i_2_n_0\ : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal addr_i_p1 : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FIFO_Full_i_1__2\ : label is "soft_lutpair125"; + attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[0]_i_1__2\ : label is "soft_lutpair126"; + attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[2]_i_1__2\ : label is "soft_lutpair125"; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[3][7]_srl4_i_1__0\ : label is "soft_lutpair126"; +begin + FIFO_Full_reg <= \^fifo_full_reg\; + Q(2 downto 0) <= \^q\(2 downto 0); +\FIFO_Full_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"02080800" + ) + port map ( + I0 => \^q\(1), + I1 => \^q\(0), + I2 => \^q\(2), + I3 => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, + I4 => \^fifo_full_reg\, + O => fifo_full_p1 + ); +\INFERRED_GEN.cnt_i[0]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AA6A5595" + ) + port map ( + I0 => \^q\(0), + I1 => sig_mstr2sf_cmd_valid, + I2 => sig_inhibit_rdy_n_reg, + I3 => FIFO_Full_reg_0, + I4 => \INFERRED_GEN.cnt_i[1]_i_2_n_0\, + O => addr_i_p1(0) + ); +\INFERRED_GEN.cnt_i[1]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"A6AAAAAA9A999999" + ) + port map ( + I0 => \^q\(1), + I1 => \INFERRED_GEN.cnt_i[1]_i_2_n_0\, + I2 => FIFO_Full_reg_0, + I3 => sig_inhibit_rdy_n_reg, + I4 => sig_mstr2sf_cmd_valid, + I5 => \^q\(0), + O => addr_i_p1(1) + ); +\INFERRED_GEN.cnt_i[1]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FBAA" + ) + port map ( + I0 => \^q\(2), + I1 => DOBDO(0), + I2 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, + I3 => lsig_cmd_loaded, + O => \INFERRED_GEN.cnt_i[1]_i_2_n_0\ + ); +\INFERRED_GEN.cnt_i[2]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"58F0F0F1" + ) + port map ( + I0 => \^fifo_full_reg\, + I1 => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, + I2 => \^q\(2), + I3 => \^q\(0), + I4 => \^q\(1), + O => addr_i_p1(2) + ); +\INFERRED_GEN.cnt_i_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => addr_i_p1(0), + Q => \^q\(0), + S => SR(0) + ); +\INFERRED_GEN.cnt_i_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => addr_i_p1(1), + Q => \^q\(1), + S => SR(0) + ); +\INFERRED_GEN.cnt_i_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => addr_i_p1(2), + Q => \^q\(2), + S => SR(0) + ); +\INFERRED_GEN.data_reg[3][7]_srl4_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => FIFO_Full_reg_0, + I1 => sig_inhibit_rdy_n_reg, + I2 => sig_mstr2sf_cmd_valid, + O => \^fifo_full_reg\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f__parameterized0\ is + port ( + fifo_full_p1 : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 3 downto 0 ); + sig_wr_fifo : out STD_LOGIC; + sig_push_coelsc_reg : in STD_LOGIC; + m_axi_s2mm_bvalid : in STD_LOGIC; + FIFO_Full_reg : in STD_LOGIC; + sig_inhibit_rdy_n : in STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[3]_0\ : in STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f__parameterized0\ : entity is "cntr_incr_decr_addn_f"; +end \Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f__parameterized0\ is + signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal addr_i_p1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^sig_wr_fifo\ : STD_LOGIC; +begin + Q(3 downto 0) <= \^q\(3 downto 0); + sig_wr_fifo <= \^sig_wr_fifo\; +\FIFO_Full_i_1__5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0004411000000000" + ) + port map ( + I0 => \^q\(3), + I1 => sig_push_coelsc_reg, + I2 => \^sig_wr_fifo\, + I3 => \^q\(0), + I4 => \^q\(1), + I5 => \^q\(2), + O => fifo_full_p1 + ); +\INFERRED_GEN.cnt_i[0]_i_1__5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BB4BBBBB44B44444" + ) + port map ( + I0 => \^q\(3), + I1 => sig_push_coelsc_reg, + I2 => m_axi_s2mm_bvalid, + I3 => FIFO_Full_reg, + I4 => sig_inhibit_rdy_n, + I5 => \^q\(0), + O => addr_i_p1(0) + ); +\INFERRED_GEN.cnt_i[1]_i_1__5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AEAAF7FF51550800" + ) + port map ( + I0 => \^q\(0), + I1 => m_axi_s2mm_bvalid, + I2 => FIFO_Full_reg, + I3 => sig_inhibit_rdy_n, + I4 => \INFERRED_GEN.cnt_i_reg[3]_0\, + I5 => \^q\(1), + O => addr_i_p1(1) + ); +\INFERRED_GEN.cnt_i[2]_i_1__5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7F7FFE7F80800180" + ) + port map ( + I0 => \^sig_wr_fifo\, + I1 => \^q\(0), + I2 => \^q\(1), + I3 => sig_push_coelsc_reg, + I4 => \^q\(3), + I5 => \^q\(2), + O => addr_i_p1(2) + ); +\INFERRED_GEN.cnt_i[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFF7FFF00018000" + ) + port map ( + I0 => \^q\(1), + I1 => \^q\(0), + I2 => \^sig_wr_fifo\, + I3 => \^q\(2), + I4 => sig_push_coelsc_reg, + I5 => \^q\(3), + O => addr_i_p1(3) + ); +\INFERRED_GEN.cnt_i_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => addr_i_p1(0), + Q => \^q\(0), + S => sig_stream_rst + ); +\INFERRED_GEN.cnt_i_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => addr_i_p1(1), + Q => \^q\(1), + S => sig_stream_rst + ); +\INFERRED_GEN.cnt_i_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => addr_i_p1(2), + Q => \^q\(2), + S => sig_stream_rst + ); +\INFERRED_GEN.cnt_i_reg[3]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => addr_i_p1(3), + Q => \^q\(3), + S => sig_stream_rst + ); +\INFERRED_GEN.data_reg[5][0]_srl6_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"20" + ) + port map ( + I0 => m_axi_s2mm_bvalid, + I1 => FIFO_Full_reg, + I2 => sig_inhibit_rdy_n, + O => \^sig_wr_fifo\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f__parameterized1\ is + port ( + \INFERRED_GEN.cnt_i_reg[1]_0\ : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 3 downto 0 ); + fifo_full_p1 : out STD_LOGIC; + \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg\ : out STD_LOGIC; + sig_coelsc_reg_empty : in STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_push_to_wsc_reg : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_data2wsc_valid : in STD_LOGIC; + FIFO_Full_reg : in STD_LOGIC; + sig_inhibit_rdy_n : in STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[3]_1\ : in STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f__parameterized1\ : entity is "cntr_incr_decr_addn_f"; +end \Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f__parameterized1\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f__parameterized1\ is + signal \^gen_enable_indet_btt.sig_coelsc_eop_reg\ : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal addr_i_p1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \GEN_ENABLE_INDET_BTT.sig_coelsc_reg_empty_i_2\ : label is "soft_lutpair248"; + attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[1]_i_2__2\ : label is "soft_lutpair248"; +begin + \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg\ <= \^gen_enable_indet_btt.sig_coelsc_eop_reg\; + Q(3 downto 0) <= \^q\(3 downto 0); +\FIFO_Full_i_1__6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0004411000000000" + ) + port map ( + I0 => \^q\(3), + I1 => \^gen_enable_indet_btt.sig_coelsc_eop_reg\, + I2 => sig_push_to_wsc_reg, + I3 => \^q\(0), + I4 => \^q\(1), + I5 => \^q\(2), + O => fifo_full_p1 + ); +\GEN_ENABLE_INDET_BTT.sig_coelsc_reg_empty_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2022" + ) + port map ( + I0 => sig_coelsc_reg_empty, + I1 => \^q\(3), + I2 => \out\(0), + I3 => \INFERRED_GEN.cnt_i_reg[3]_0\(0), + O => \^gen_enable_indet_btt.sig_coelsc_eop_reg\ + ); +\INFERRED_GEN.cnt_i[0]_i_1__6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4044BFBBBFBB4044" + ) + port map ( + I0 => \^q\(3), + I1 => sig_coelsc_reg_empty, + I2 => \out\(0), + I3 => \INFERRED_GEN.cnt_i_reg[3]_0\(0), + I4 => sig_push_to_wsc_reg, + I5 => \^q\(0), + O => addr_i_p1(0) + ); +\INFERRED_GEN.cnt_i[1]_i_1__6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AEAAF7FF51550800" + ) + port map ( + I0 => \^q\(0), + I1 => sig_data2wsc_valid, + I2 => FIFO_Full_reg, + I3 => sig_inhibit_rdy_n, + I4 => \INFERRED_GEN.cnt_i_reg[3]_1\, + I5 => \^q\(1), + O => addr_i_p1(1) + ); +\INFERRED_GEN.cnt_i[1]_i_2__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => \^q\(3), + I1 => sig_coelsc_reg_empty, + I2 => \INFERRED_GEN.cnt_i_reg[3]_0\(0), + O => \INFERRED_GEN.cnt_i_reg[1]_0\ + ); +\INFERRED_GEN.cnt_i[2]_i_1__6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7F7FFE7F80800180" + ) + port map ( + I0 => sig_push_to_wsc_reg, + I1 => \^q\(0), + I2 => \^q\(1), + I3 => \^gen_enable_indet_btt.sig_coelsc_eop_reg\, + I4 => \^q\(3), + I5 => \^q\(2), + O => addr_i_p1(2) + ); +\INFERRED_GEN.cnt_i[3]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFF7FFF00018000" + ) + port map ( + I0 => \^q\(1), + I1 => \^q\(0), + I2 => sig_push_to_wsc_reg, + I3 => \^q\(2), + I4 => \^gen_enable_indet_btt.sig_coelsc_eop_reg\, + I5 => \^q\(3), + O => addr_i_p1(3) + ); +\INFERRED_GEN.cnt_i_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => addr_i_p1(0), + Q => \^q\(0), + S => sig_stream_rst + ); +\INFERRED_GEN.cnt_i_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => addr_i_p1(1), + Q => \^q\(1), + S => sig_stream_rst + ); +\INFERRED_GEN.cnt_i_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => addr_i_p1(2), + Q => \^q\(2), + S => sig_stream_rst + ); +\INFERRED_GEN.cnt_i_reg[3]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => addr_i_p1(3), + Q => \^q\(3), + S => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f__parameterized2\ is + port ( + \INCLUDE_PACKING.lsig_first_dbeat_reg\ : out STD_LOGIC; + \sig_byte_cntr_reg[0]\ : out STD_LOGIC; + sig_dre2ibtt_tlast : out STD_LOGIC; + sig_cmd_full_reg : out STD_LOGIC; + sig_cmd_empty_reg : out STD_LOGIC; + \sig_good_tlast_dbeat37_out__0\ : out STD_LOGIC; + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + Q : out STD_LOGIC_VECTOR ( 4 downto 0 ); + sig_s_ready_dup4_reg : out STD_LOGIC; + \sig_byte_cntr_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + SS : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\ : out STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0]\ : out STD_LOGIC; + fifo_full_p1 : out STD_LOGIC; + sig_wr_fifo : out STD_LOGIC; + sig_eop_sent : out STD_LOGIC; + \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg\ : out STD_LOGIC; + \INCLUDE_PACKING.lsig_first_dbeat_reg_0\ : in STD_LOGIC; + sig_cmd_full : in STD_LOGIC; + sig_sm_ld_dre_cmd : in STD_LOGIC; + p_7_out : in STD_LOGIC; + sig_strm_tlast : in STD_LOGIC; + sig_m_valid_out_reg : in STD_LOGIC; + lsig_absorb2tlast : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_last_reg_out_reg : in STD_LOGIC; + sig_eop_halt_xfer : in STD_LOGIC; + sig_ibtt2dre_tready : in STD_LOGIC; + \out\ : in STD_LOGIC; + sig_clr_dbc_reg : in STD_LOGIC; + sig_eop_sent_reg : in STD_LOGIC; + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + sig_inhibit_rdy_n_reg : in STD_LOGIC; + FIFO_Full_reg : in STD_LOGIC; + slice_insert_valid : in STD_LOGIC; + \storage_data_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + lsig_cmd_fetch_pause : in STD_LOGIC; + sig_need_cmd_flush : in STD_LOGIC; + sig_sm_pop_cmd_fifo : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f__parameterized2\ : entity is "cntr_incr_decr_addn_f"; +end \Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f__parameterized2\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f__parameterized2\ is + signal FIFO_Full_i_2_n_0 : STD_LOGIC; + signal FIFO_Full_i_3_n_0 : STD_LOGIC; + signal \INFERRED_GEN.cnt_i[3]_i_2_n_0\ : STD_LOGIC; + signal \INFERRED_GEN.cnt_i[4]_i_3_n_0\ : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \^ss\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal addr_i_p1 : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal lsig_set_absorb2tlast : STD_LOGIC; + signal \^sig_byte_cntr_reg[0]\ : STD_LOGIC; + signal sig_cmd_full_i_2_n_0 : STD_LOGIC; + signal \^sig_dre2ibtt_tlast\ : STD_LOGIC; + signal \^sig_good_tlast_dbeat37_out__0\ : STD_LOGIC; + signal \^sig_wr_fifo\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.lsig_0ffset_cntr[0]_i_1\ : label is "soft_lutpair229"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.lsig_first_dbeat_i_1\ : label is "soft_lutpair229"; + attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[3]_i_2\ : label is "soft_lutpair227"; + attribute SOFT_HLUTNM of \sig_btt_cntr[15]_i_1__0\ : label is "soft_lutpair225"; + attribute SOFT_HLUTNM of \sig_btt_cntr[15]_i_4\ : label is "soft_lutpair227"; + attribute SOFT_HLUTNM of sig_cmd_empty_i_1 : label is "soft_lutpair228"; + attribute SOFT_HLUTNM of sig_cmd_full_i_1 : label is "soft_lutpair228"; + attribute SOFT_HLUTNM of \sig_data_reg_out[7]_i_1__3\ : label is "soft_lutpair226"; + attribute SOFT_HLUTNM of sig_eop_sent_reg_i_1 : label is "soft_lutpair225"; + attribute SOFT_HLUTNM of \sig_m_valid_dup_i_2__1\ : label is "soft_lutpair226"; +begin + Q(4 downto 0) <= \^q\(4 downto 0); + SS(0) <= \^ss\(0); + \sig_byte_cntr_reg[0]\ <= \^sig_byte_cntr_reg[0]\; + sig_dre2ibtt_tlast <= \^sig_dre2ibtt_tlast\; + \sig_good_tlast_dbeat37_out__0\ <= \^sig_good_tlast_dbeat37_out__0\; + sig_wr_fifo <= \^sig_wr_fifo\; +\FIFO_Full_i_1__10\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0040000400000040" + ) + port map ( + I0 => FIFO_Full_i_2_n_0, + I1 => \^q\(3), + I2 => \^q\(2), + I3 => \^q\(4), + I4 => \^sig_byte_cntr_reg[0]\, + I5 => FIFO_Full_i_3_n_0, + O => fifo_full_p1 + ); +FIFO_Full_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"EE7EEEEE77D77777" + ) + port map ( + I0 => \^q\(1), + I1 => \^q\(0), + I2 => sig_inhibit_rdy_n_reg, + I3 => FIFO_Full_reg, + I4 => slice_insert_valid, + I5 => \INFERRED_GEN.cnt_i[3]_i_2_n_0\, + O => FIFO_Full_i_2_n_0 + ); +FIFO_Full_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"A8A8EAA8A8A8A8A8" + ) + port map ( + I0 => \INFERRED_GEN.cnt_i[3]_i_2_n_0\, + I1 => \^q\(1), + I2 => \^q\(0), + I3 => slice_insert_valid, + I4 => FIFO_Full_reg, + I5 => sig_inhibit_rdy_n_reg, + O => FIFO_Full_i_3_n_0 + ); +\GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000C800000000" + ) + port map ( + I0 => \storage_data_reg[3]\(1), + I1 => sig_m_valid_out_reg, + I2 => sig_strm_tlast, + I3 => sig_eop_halt_xfer, + I4 => \^q\(4), + I5 => \^sig_byte_cntr_reg[0]\, + O => \^sig_good_tlast_dbeat37_out__0\ + ); +\GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00008000FF008000" + ) + port map ( + I0 => \^sig_byte_cntr_reg[0]\, + I1 => lsig_cmd_fetch_pause, + I2 => sig_last_reg_out_reg, + I3 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I4 => sig_need_cmd_flush, + I5 => sig_sm_pop_cmd_fifo, + O => \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg\ + ); +\INCLUDE_PACKING.lsig_0ffset_cntr[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4F70" + ) + port map ( + I0 => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1]\(0), + I1 => \INCLUDE_PACKING.lsig_first_dbeat_reg_0\, + I2 => \^sig_byte_cntr_reg[0]\, + I3 => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\(0), + O => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0]\ + ); +\INCLUDE_PACKING.lsig_0ffset_cntr[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"660FFFFF66F00000" + ) + port map ( + I0 => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1]\(0), + I1 => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1]\(1), + I2 => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\(0), + I3 => \INCLUDE_PACKING.lsig_first_dbeat_reg_0\, + I4 => \^sig_byte_cntr_reg[0]\, + I5 => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\(1), + O => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\ + ); +\INCLUDE_PACKING.lsig_first_dbeat_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"D8" + ) + port map ( + I0 => \^sig_byte_cntr_reg[0]\, + I1 => \^sig_dre2ibtt_tlast\, + I2 => \INCLUDE_PACKING.lsig_first_dbeat_reg_0\, + O => \INCLUDE_PACKING.lsig_first_dbeat_reg\ + ); +\INFERRED_GEN.cnt_i[0]_i_1__10\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BB4BBBBB44B44444" + ) + port map ( + I0 => \^q\(4), + I1 => \^sig_byte_cntr_reg[0]\, + I2 => slice_insert_valid, + I3 => FIFO_Full_reg, + I4 => sig_inhibit_rdy_n_reg, + I5 => \^q\(0), + O => addr_i_p1(0) + ); +\INFERRED_GEN.cnt_i[1]_i_1__10\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AEAAF7FF51550800" + ) + port map ( + I0 => \^q\(0), + I1 => slice_insert_valid, + I2 => FIFO_Full_reg, + I3 => sig_inhibit_rdy_n_reg, + I4 => \INFERRED_GEN.cnt_i[3]_i_2_n_0\, + I5 => \^q\(1), + O => addr_i_p1(1) + ); +\INFERRED_GEN.cnt_i[2]_i_1__10\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7F7FFE7F80800180" + ) + port map ( + I0 => \^sig_wr_fifo\, + I1 => \^q\(0), + I2 => \^q\(1), + I3 => \^sig_byte_cntr_reg[0]\, + I4 => \^q\(4), + I5 => \^q\(2), + O => addr_i_p1(2) + ); +\INFERRED_GEN.cnt_i[3]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFE7FFF00018000" + ) + port map ( + I0 => \^q\(1), + I1 => \^q\(0), + I2 => \^sig_wr_fifo\, + I3 => \^q\(2), + I4 => \INFERRED_GEN.cnt_i[3]_i_2_n_0\, + I5 => \^q\(3), + O => addr_i_p1(3) + ); +\INFERRED_GEN.cnt_i[3]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^sig_byte_cntr_reg[0]\, + I1 => \^q\(4), + O => \INFERRED_GEN.cnt_i[3]_i_2_n_0\ + ); +\INFERRED_GEN.cnt_i[4]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => sig_eop_sent_reg, + I1 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + O => \^ss\(0) + ); +\INFERRED_GEN.cnt_i[4]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFF7FFF00018000" + ) + port map ( + I0 => \^q\(2), + I1 => \INFERRED_GEN.cnt_i[4]_i_3_n_0\, + I2 => \^q\(1), + I3 => \^q\(3), + I4 => \^sig_byte_cntr_reg[0]\, + I5 => \^q\(4), + O => addr_i_p1(4) + ); +\INFERRED_GEN.cnt_i[4]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2000FF2020002000" + ) + port map ( + I0 => sig_inhibit_rdy_n_reg, + I1 => FIFO_Full_reg, + I2 => slice_insert_valid, + I3 => \^q\(0), + I4 => \^q\(4), + I5 => \^sig_byte_cntr_reg[0]\, + O => \INFERRED_GEN.cnt_i[4]_i_3_n_0\ + ); +\INFERRED_GEN.cnt_i_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => addr_i_p1(0), + Q => \^q\(0), + S => \^ss\(0) + ); +\INFERRED_GEN.cnt_i_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => addr_i_p1(1), + Q => \^q\(1), + S => \^ss\(0) + ); +\INFERRED_GEN.cnt_i_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => addr_i_p1(2), + Q => \^q\(2), + S => \^ss\(0) + ); +\INFERRED_GEN.cnt_i_reg[3]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => addr_i_p1(3), + Q => \^q\(3), + S => \^ss\(0) + ); +\INFERRED_GEN.cnt_i_reg[4]\: unisim.vcomponents.FDSE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => addr_i_p1(4), + Q => \^q\(4), + S => \^ss\(0) + ); +\INFERRED_GEN.data_reg[15][2]_srl16_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"20" + ) + port map ( + I0 => slice_insert_valid, + I1 => FIFO_Full_reg, + I2 => sig_inhibit_rdy_n_reg, + O => \^sig_wr_fifo\ + ); +\sig_btt_cntr[15]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F222FFFF" + ) + port map ( + I0 => lsig_set_absorb2tlast, + I1 => lsig_absorb2tlast, + I2 => sig_last_reg_out_reg, + I3 => \^sig_byte_cntr_reg[0]\, + I4 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + O => SR(0) + ); +\sig_btt_cntr[15]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"1000" + ) + port map ( + I0 => \^q\(4), + I1 => sig_strm_tlast, + I2 => \storage_data_reg[3]\(0), + I3 => sig_m_valid_out_reg, + O => lsig_set_absorb2tlast + ); +\sig_byte_cntr[7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"4F" + ) + port map ( + I0 => \^sig_byte_cntr_reg[0]\, + I1 => sig_clr_dbc_reg, + I2 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + O => \sig_byte_cntr_reg[7]\(0) + ); +\sig_byte_cntr[8]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0200" + ) + port map ( + I0 => sig_ibtt2dre_tready, + I1 => \^q\(4), + I2 => sig_eop_halt_xfer, + I3 => sig_m_valid_out_reg, + O => \^sig_byte_cntr_reg[0]\ + ); +sig_cmd_empty_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF8A" + ) + port map ( + I0 => p_7_out, + I1 => sig_cmd_full, + I2 => sig_sm_ld_dre_cmd, + I3 => sig_cmd_full_i_2_n_0, + O => sig_cmd_empty_reg + ); +sig_cmd_full_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => sig_cmd_full, + I1 => sig_sm_ld_dre_cmd, + I2 => sig_cmd_full_i_2_n_0, + O => sig_cmd_full_reg + ); +sig_cmd_full_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"F2222222FFFFFFFF" + ) + port map ( + I0 => \^sig_good_tlast_dbeat37_out__0\, + I1 => lsig_set_absorb2tlast, + I2 => sig_strm_tlast, + I3 => sig_m_valid_out_reg, + I4 => lsig_absorb2tlast, + I5 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + O => sig_cmd_full_i_2_n_0 + ); +\sig_data_reg_out[7]_i_1__3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FF10FFFF" + ) + port map ( + I0 => sig_eop_halt_xfer, + I1 => \^q\(4), + I2 => sig_ibtt2dre_tready, + I3 => lsig_absorb2tlast, + I4 => \out\, + O => E(0) + ); +sig_dre2ibtt_tlast_reg_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"11001000" + ) + port map ( + I0 => \^q\(4), + I1 => sig_eop_halt_xfer, + I2 => sig_strm_tlast, + I3 => sig_m_valid_out_reg, + I4 => \storage_data_reg[3]\(1), + O => \^sig_dre2ibtt_tlast\ + ); +sig_eop_sent_reg_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"8F88" + ) + port map ( + I0 => \^sig_byte_cntr_reg[0]\, + I1 => sig_last_reg_out_reg, + I2 => lsig_absorb2tlast, + I3 => lsig_set_absorb2tlast, + O => sig_eop_sent + ); +\sig_m_valid_dup_i_2__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAAE" + ) + port map ( + I0 => lsig_absorb2tlast, + I1 => sig_ibtt2dre_tready, + I2 => \^q\(4), + I3 => sig_eop_halt_xfer, + O => sig_s_ready_dup4_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_dynshreg_f is + port ( + sig_calc_error_reg_reg : out STD_LOGIC; + sig_wr_fifo : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 49 downto 0 ); + sig_psm_halt : in STD_LOGIC; + sig_input_reg_empty : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); + p_10_out : in STD_LOGIC; + s_axis_s2mm_cmd_tvalid : in STD_LOGIC; + FIFO_Full_reg : in STD_LOGIC; + sig_inhibit_rdy_n : in STD_LOGIC; + \s_axis_cmd_tdata_reg[63]\ : in STD_LOGIC_VECTOR ( 48 downto 0 ); + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_dynshreg_f : entity is "dynshreg_f"; +end Arty_Z7_20_axi_vdma_0_0_dynshreg_f; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_dynshreg_f is + signal \^out\ : STD_LOGIC_VECTOR ( 49 downto 0 ); + signal \sig_calc_error_reg_i_2__0_n_0\ : STD_LOGIC; + signal \sig_calc_error_reg_i_3__0_n_0\ : STD_LOGIC; + signal \sig_calc_error_reg_i_4__0_n_0\ : STD_LOGIC; + signal \sig_calc_error_reg_i_5__0_n_0\ : STD_LOGIC; + signal \^sig_wr_fifo\ : STD_LOGIC; + attribute srl_bus_name : string; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][0]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name : string; + attribute srl_name of \INFERRED_GEN.data_reg[3][0]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][0]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][10]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][10]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][10]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][11]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][11]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][11]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][12]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][12]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][12]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][13]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][13]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][13]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][14]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][14]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][14]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][15]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][15]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][15]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][1]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][1]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][1]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][23]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][23]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][23]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][2]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][2]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][2]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][30]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][30]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][30]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][32]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][32]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][32]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][33]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][33]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][33]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][34]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][34]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][34]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][35]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][35]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][35]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][36]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][36]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][36]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][37]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][37]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][37]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][38]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][38]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][38]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][39]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][39]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][39]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][3]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][3]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][3]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][40]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][40]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][40]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][41]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][41]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][41]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][42]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][42]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][42]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][43]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][43]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][43]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][44]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][44]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][44]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][45]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][45]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][45]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][46]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][46]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][46]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][47]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][47]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][47]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][48]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][48]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][48]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][49]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][49]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][49]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][4]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][4]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][4]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][50]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][50]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][50]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][51]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][51]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][51]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][52]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][52]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][52]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][53]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][53]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][53]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][54]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][54]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][54]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][55]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][55]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][55]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][56]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][56]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][56]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][57]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][57]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][57]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][58]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][58]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][58]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][59]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][59]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][59]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][5]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][5]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][5]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][60]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][60]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][60]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][61]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][61]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][61]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][62]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][62]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][62]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][63]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][63]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][63]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][6]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][6]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][6]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][7]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][7]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][7]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][8]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][8]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][8]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][9]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][9]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][9]_srl4 "; +begin + \out\(49 downto 0) <= \^out\(49 downto 0); + sig_wr_fifo <= \^sig_wr_fifo\; +\INFERRED_GEN.data_reg[3][0]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(0), + Q => \^out\(0) + ); +\INFERRED_GEN.data_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"20" + ) + port map ( + I0 => s_axis_s2mm_cmd_tvalid, + I1 => FIFO_Full_reg, + I2 => sig_inhibit_rdy_n, + O => \^sig_wr_fifo\ + ); +\INFERRED_GEN.data_reg[3][10]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(10), + Q => \^out\(10) + ); +\INFERRED_GEN.data_reg[3][11]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(11), + Q => \^out\(11) + ); +\INFERRED_GEN.data_reg[3][12]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(12), + Q => \^out\(12) + ); +\INFERRED_GEN.data_reg[3][13]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(13), + Q => \^out\(13) + ); +\INFERRED_GEN.data_reg[3][14]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(14), + Q => \^out\(14) + ); +\INFERRED_GEN.data_reg[3][15]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(15), + Q => \^out\(15) + ); +\INFERRED_GEN.data_reg[3][1]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(1), + Q => \^out\(1) + ); +\INFERRED_GEN.data_reg[3][23]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(16), + Q => \^out\(16) + ); +\INFERRED_GEN.data_reg[3][2]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(2), + Q => \^out\(2) + ); +\INFERRED_GEN.data_reg[3][30]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(16), + Q => \^out\(17) + ); +\INFERRED_GEN.data_reg[3][32]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(17), + Q => \^out\(18) + ); +\INFERRED_GEN.data_reg[3][33]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(18), + Q => \^out\(19) + ); +\INFERRED_GEN.data_reg[3][34]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(19), + Q => \^out\(20) + ); +\INFERRED_GEN.data_reg[3][35]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(20), + Q => \^out\(21) + ); +\INFERRED_GEN.data_reg[3][36]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(21), + Q => \^out\(22) + ); +\INFERRED_GEN.data_reg[3][37]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(22), + Q => \^out\(23) + ); +\INFERRED_GEN.data_reg[3][38]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(23), + Q => \^out\(24) + ); +\INFERRED_GEN.data_reg[3][39]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(24), + Q => \^out\(25) + ); +\INFERRED_GEN.data_reg[3][3]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(3), + Q => \^out\(3) + ); +\INFERRED_GEN.data_reg[3][40]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(25), + Q => \^out\(26) + ); +\INFERRED_GEN.data_reg[3][41]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(26), + Q => \^out\(27) + ); +\INFERRED_GEN.data_reg[3][42]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(27), + Q => \^out\(28) + ); +\INFERRED_GEN.data_reg[3][43]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(28), + Q => \^out\(29) + ); +\INFERRED_GEN.data_reg[3][44]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(29), + Q => \^out\(30) + ); +\INFERRED_GEN.data_reg[3][45]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(30), + Q => \^out\(31) + ); +\INFERRED_GEN.data_reg[3][46]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(31), + Q => \^out\(32) + ); +\INFERRED_GEN.data_reg[3][47]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(32), + Q => \^out\(33) + ); +\INFERRED_GEN.data_reg[3][48]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(33), + Q => \^out\(34) + ); +\INFERRED_GEN.data_reg[3][49]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(34), + Q => \^out\(35) + ); +\INFERRED_GEN.data_reg[3][4]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(4), + Q => \^out\(4) + ); +\INFERRED_GEN.data_reg[3][50]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(35), + Q => \^out\(36) + ); +\INFERRED_GEN.data_reg[3][51]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(36), + Q => \^out\(37) + ); +\INFERRED_GEN.data_reg[3][52]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(37), + Q => \^out\(38) + ); +\INFERRED_GEN.data_reg[3][53]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(38), + Q => \^out\(39) + ); +\INFERRED_GEN.data_reg[3][54]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(39), + Q => \^out\(40) + ); +\INFERRED_GEN.data_reg[3][55]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(40), + Q => \^out\(41) + ); +\INFERRED_GEN.data_reg[3][56]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(41), + Q => \^out\(42) + ); +\INFERRED_GEN.data_reg[3][57]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(42), + Q => \^out\(43) + ); +\INFERRED_GEN.data_reg[3][58]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(43), + Q => \^out\(44) + ); +\INFERRED_GEN.data_reg[3][59]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(44), + Q => \^out\(45) + ); +\INFERRED_GEN.data_reg[3][5]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(5), + Q => \^out\(5) + ); +\INFERRED_GEN.data_reg[3][60]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(45), + Q => \^out\(46) + ); +\INFERRED_GEN.data_reg[3][61]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(46), + Q => \^out\(47) + ); +\INFERRED_GEN.data_reg[3][62]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(47), + Q => \^out\(48) + ); +\INFERRED_GEN.data_reg[3][63]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(48), + Q => \^out\(49) + ); +\INFERRED_GEN.data_reg[3][6]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(6), + Q => \^out\(6) + ); +\INFERRED_GEN.data_reg[3][7]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(7), + Q => \^out\(7) + ); +\INFERRED_GEN.data_reg[3][8]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(8), + Q => \^out\(8) + ); +\INFERRED_GEN.data_reg[3][9]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \s_axis_cmd_tdata_reg[63]\(9), + Q => \^out\(9) + ); +\sig_calc_error_reg_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF00000100" + ) + port map ( + I0 => \sig_calc_error_reg_i_2__0_n_0\, + I1 => \sig_calc_error_reg_i_3__0_n_0\, + I2 => sig_psm_halt, + I3 => sig_input_reg_empty, + I4 => Q(2), + I5 => p_10_out, + O => sig_calc_error_reg_reg + ); +\sig_calc_error_reg_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => \^out\(13), + I1 => \^out\(12), + I2 => \^out\(14), + I3 => \^out\(15), + I4 => \sig_calc_error_reg_i_4__0_n_0\, + O => \sig_calc_error_reg_i_2__0_n_0\ + ); +\sig_calc_error_reg_i_3__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => \^out\(5), + I1 => \^out\(4), + I2 => \^out\(7), + I3 => \^out\(6), + I4 => \sig_calc_error_reg_i_5__0_n_0\, + O => \sig_calc_error_reg_i_3__0_n_0\ + ); +\sig_calc_error_reg_i_4__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \^out\(10), + I1 => \^out\(11), + I2 => \^out\(8), + I3 => \^out\(9), + O => \sig_calc_error_reg_i_4__0_n_0\ + ); +\sig_calc_error_reg_i_5__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \^out\(2), + I1 => \^out\(3), + I2 => \^out\(0), + I3 => \^out\(1), + O => \sig_calc_error_reg_i_5__0_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_dynshreg_f_26 is + port ( + sig_calc_error_reg_reg : out STD_LOGIC; + sig_wr_fifo : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 49 downto 0 ); + \in\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_sm_halt_reg : in STD_LOGIC; + sig_input_reg_empty : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); + p_56_out : in STD_LOGIC; + FIFO_Full_reg : in STD_LOGIC; + sig_inhibit_rdy_n : in STD_LOGIC; + \s_axis_cmd_tdata_reg[63]\ : in STD_LOGIC_VECTOR ( 48 downto 0 ); + m_axi_mm2s_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_dynshreg_f_26 : entity is "dynshreg_f"; +end Arty_Z7_20_axi_vdma_0_0_dynshreg_f_26; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_dynshreg_f_26 is + signal \^out\ : STD_LOGIC_VECTOR ( 49 downto 0 ); + signal sig_calc_error_reg_i_2_n_0 : STD_LOGIC; + signal sig_calc_error_reg_i_3_n_0 : STD_LOGIC; + signal sig_calc_error_reg_i_4_n_0 : STD_LOGIC; + signal sig_calc_error_reg_i_5_n_0 : STD_LOGIC; + signal \^sig_wr_fifo\ : STD_LOGIC; + attribute srl_bus_name : string; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][0]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name : string; + attribute srl_name of \INFERRED_GEN.data_reg[3][0]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][0]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][10]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][10]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][10]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][11]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][11]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][11]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][12]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][12]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][12]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][13]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][13]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][13]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][14]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][14]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][14]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][15]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][15]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][15]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][1]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][1]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][1]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][23]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][23]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][23]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][2]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][2]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][2]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][30]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][30]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][30]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][32]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][32]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][32]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][33]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][33]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][33]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][34]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][34]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][34]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][35]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][35]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][35]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][36]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][36]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][36]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][37]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][37]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][37]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][38]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][38]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][38]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][39]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][39]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][39]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][3]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][3]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][3]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][40]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][40]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][40]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][41]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][41]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][41]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][42]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][42]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][42]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][43]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][43]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][43]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][44]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][44]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][44]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][45]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][45]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][45]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][46]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][46]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][46]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][47]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][47]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][47]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][48]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][48]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][48]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][49]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][49]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][49]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][4]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][4]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][4]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][50]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][50]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][50]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][51]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][51]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][51]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][52]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][52]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][52]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][53]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][53]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][53]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][54]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][54]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][54]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][55]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][55]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][55]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][56]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][56]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][56]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][57]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][57]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][57]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][58]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][58]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][58]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][59]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][59]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][59]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][5]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][5]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][5]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][60]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][60]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][60]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][61]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][61]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][61]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][62]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][62]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][62]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][63]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][63]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][63]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][6]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][6]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][6]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][7]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][7]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][7]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][8]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][8]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][8]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][9]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][9]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][9]_srl4 "; +begin + \out\(49 downto 0) <= \^out\(49 downto 0); + sig_wr_fifo <= \^sig_wr_fifo\; +\INFERRED_GEN.data_reg[3][0]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(0), + Q => \^out\(0) + ); +\INFERRED_GEN.data_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"20" + ) + port map ( + I0 => p_56_out, + I1 => FIFO_Full_reg, + I2 => sig_inhibit_rdy_n, + O => \^sig_wr_fifo\ + ); +\INFERRED_GEN.data_reg[3][10]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(10), + Q => \^out\(10) + ); +\INFERRED_GEN.data_reg[3][11]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(11), + Q => \^out\(11) + ); +\INFERRED_GEN.data_reg[3][12]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(12), + Q => \^out\(12) + ); +\INFERRED_GEN.data_reg[3][13]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(13), + Q => \^out\(13) + ); +\INFERRED_GEN.data_reg[3][14]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(14), + Q => \^out\(14) + ); +\INFERRED_GEN.data_reg[3][15]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(15), + Q => \^out\(15) + ); +\INFERRED_GEN.data_reg[3][1]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(1), + Q => \^out\(1) + ); +\INFERRED_GEN.data_reg[3][23]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(16), + Q => \^out\(16) + ); +\INFERRED_GEN.data_reg[3][2]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(2), + Q => \^out\(2) + ); +\INFERRED_GEN.data_reg[3][30]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(16), + Q => \^out\(17) + ); +\INFERRED_GEN.data_reg[3][32]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(17), + Q => \^out\(18) + ); +\INFERRED_GEN.data_reg[3][33]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(18), + Q => \^out\(19) + ); +\INFERRED_GEN.data_reg[3][34]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(19), + Q => \^out\(20) + ); +\INFERRED_GEN.data_reg[3][35]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(20), + Q => \^out\(21) + ); +\INFERRED_GEN.data_reg[3][36]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(21), + Q => \^out\(22) + ); +\INFERRED_GEN.data_reg[3][37]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(22), + Q => \^out\(23) + ); +\INFERRED_GEN.data_reg[3][38]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(23), + Q => \^out\(24) + ); +\INFERRED_GEN.data_reg[3][39]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(24), + Q => \^out\(25) + ); +\INFERRED_GEN.data_reg[3][3]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(3), + Q => \^out\(3) + ); +\INFERRED_GEN.data_reg[3][40]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(25), + Q => \^out\(26) + ); +\INFERRED_GEN.data_reg[3][41]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(26), + Q => \^out\(27) + ); +\INFERRED_GEN.data_reg[3][42]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(27), + Q => \^out\(28) + ); +\INFERRED_GEN.data_reg[3][43]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(28), + Q => \^out\(29) + ); +\INFERRED_GEN.data_reg[3][44]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(29), + Q => \^out\(30) + ); +\INFERRED_GEN.data_reg[3][45]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(30), + Q => \^out\(31) + ); +\INFERRED_GEN.data_reg[3][46]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(31), + Q => \^out\(32) + ); +\INFERRED_GEN.data_reg[3][47]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(32), + Q => \^out\(33) + ); +\INFERRED_GEN.data_reg[3][48]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(33), + Q => \^out\(34) + ); +\INFERRED_GEN.data_reg[3][49]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(34), + Q => \^out\(35) + ); +\INFERRED_GEN.data_reg[3][4]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(4), + Q => \^out\(4) + ); +\INFERRED_GEN.data_reg[3][50]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(35), + Q => \^out\(36) + ); +\INFERRED_GEN.data_reg[3][51]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(36), + Q => \^out\(37) + ); +\INFERRED_GEN.data_reg[3][52]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(37), + Q => \^out\(38) + ); +\INFERRED_GEN.data_reg[3][53]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(38), + Q => \^out\(39) + ); +\INFERRED_GEN.data_reg[3][54]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(39), + Q => \^out\(40) + ); +\INFERRED_GEN.data_reg[3][55]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(40), + Q => \^out\(41) + ); +\INFERRED_GEN.data_reg[3][56]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(41), + Q => \^out\(42) + ); +\INFERRED_GEN.data_reg[3][57]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(42), + Q => \^out\(43) + ); +\INFERRED_GEN.data_reg[3][58]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(43), + Q => \^out\(44) + ); +\INFERRED_GEN.data_reg[3][59]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(44), + Q => \^out\(45) + ); +\INFERRED_GEN.data_reg[3][5]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(5), + Q => \^out\(5) + ); +\INFERRED_GEN.data_reg[3][60]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(45), + Q => \^out\(46) + ); +\INFERRED_GEN.data_reg[3][61]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(46), + Q => \^out\(47) + ); +\INFERRED_GEN.data_reg[3][62]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(47), + Q => \^out\(48) + ); +\INFERRED_GEN.data_reg[3][63]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(48), + Q => \^out\(49) + ); +\INFERRED_GEN.data_reg[3][6]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(6), + Q => \^out\(6) + ); +\INFERRED_GEN.data_reg[3][7]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(7), + Q => \^out\(7) + ); +\INFERRED_GEN.data_reg[3][8]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(8), + Q => \^out\(8) + ); +\INFERRED_GEN.data_reg[3][9]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => \s_axis_cmd_tdata_reg[63]\(9), + Q => \^out\(9) + ); +sig_calc_error_reg_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"F0F0F0F0F0F2F0F0" + ) + port map ( + I0 => sig_calc_error_reg_i_2_n_0, + I1 => sig_calc_error_reg_i_3_n_0, + I2 => \in\(0), + I3 => sig_sm_halt_reg, + I4 => sig_input_reg_empty, + I5 => Q(2), + O => sig_calc_error_reg_reg + ); +sig_calc_error_reg_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000001" + ) + port map ( + I0 => \^out\(8), + I1 => \^out\(11), + I2 => \^out\(9), + I3 => \^out\(10), + I4 => sig_calc_error_reg_i_4_n_0, + O => sig_calc_error_reg_i_2_n_0 + ); +sig_calc_error_reg_i_3: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => \^out\(0), + I1 => \^out\(3), + I2 => \^out\(1), + I3 => \^out\(2), + I4 => sig_calc_error_reg_i_5_n_0, + O => sig_calc_error_reg_i_3_n_0 + ); +sig_calc_error_reg_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \^out\(13), + I1 => \^out\(12), + I2 => \^out\(15), + I3 => \^out\(14), + O => sig_calc_error_reg_i_4_n_0 + ); +sig_calc_error_reg_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \^out\(5), + I1 => \^out\(4), + I2 => \^out\(7), + I3 => \^out\(6), + O => sig_calc_error_reg_i_5_n_0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized0\ is + port ( + decerr_i_reg : out STD_LOGIC; + slverr_i_reg : out STD_LOGIC; + interr_i_reg : out STD_LOGIC; + sig_wr_fifo : out STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_rsc2stat_status_valid : in STD_LOGIC; + FIFO_Full_reg : in STD_LOGIC; + sig_inhibit_rdy_n_reg : in STD_LOGIC; + sig_rd_sts_slverr_reg_reg : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_mm2s_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized0\ : entity is "dynshreg_f"; +end \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized0\ is + signal m_axis_mm2s_sts_tdata : STD_LOGIC_VECTOR ( 6 downto 4 ); + signal \^sig_wr_fifo\ : STD_LOGIC; + attribute srl_bus_name : string; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][4]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name : string; + attribute srl_name of \INFERRED_GEN.data_reg[3][4]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][4]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][5]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][5]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][5]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][6]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][6]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][6]_srl4 "; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of decerr_i_i_1 : label is "soft_lutpair131"; + attribute SOFT_HLUTNM of slverr_i_i_1 : label is "soft_lutpair131"; +begin + sig_wr_fifo <= \^sig_wr_fifo\; +\INFERRED_GEN.data_reg[3][4]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => sig_rd_sts_slverr_reg_reg(0), + Q => m_axis_mm2s_sts_tdata(4) + ); +\INFERRED_GEN.data_reg[3][4]_srl4_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"20" + ) + port map ( + I0 => sig_rsc2stat_status_valid, + I1 => FIFO_Full_reg, + I2 => sig_inhibit_rdy_n_reg, + O => \^sig_wr_fifo\ + ); +\INFERRED_GEN.data_reg[3][5]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => sig_rd_sts_slverr_reg_reg(1), + Q => m_axis_mm2s_sts_tdata(5) + ); +\INFERRED_GEN.data_reg[3][6]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_mm2s_aclk, + D => sig_rd_sts_slverr_reg_reg(2), + Q => m_axis_mm2s_sts_tdata(6) + ); +decerr_i_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => m_axis_mm2s_sts_tdata(5), + I1 => Q(2), + O => decerr_i_reg + ); +interr_i_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => m_axis_mm2s_sts_tdata(4), + I1 => Q(2), + O => interr_i_reg + ); +slverr_i_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => m_axis_mm2s_sts_tdata(6), + I1 => Q(2), + O => slverr_i_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1\ is + port ( + sig_addr_valid_reg_reg : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 40 downto 0 ); + sig_calc_error_reg_reg : out STD_LOGIC; + FIFO_Full_reg : in STD_LOGIC; + sig_inhibit_rdy_n : in STD_LOGIC; + sig_mstr2addr_cmd_valid : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 38 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_mm2s_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1\ : entity is "dynshreg_f"; +end \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1\ is + signal \^out\ : STD_LOGIC_VECTOR ( 40 downto 0 ); + signal \^sig_calc_error_reg_reg\ : STD_LOGIC; + attribute srl_bus_name : string; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][10]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name : string; + attribute srl_name of \INFERRED_GEN.data_reg[3][10]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][10]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][11]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][11]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][11]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][12]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][12]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][12]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][13]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][13]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][13]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][14]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][14]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][14]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][15]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][15]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][15]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][16]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][16]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][16]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][17]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][17]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][17]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][18]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][18]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][18]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][19]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][19]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][19]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][20]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][20]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][20]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][21]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][21]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][21]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][22]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][22]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][22]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][23]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][23]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][23]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][24]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][24]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][24]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][25]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][25]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][25]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][26]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][26]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][26]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][27]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][27]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][27]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][28]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][28]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][28]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][29]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][29]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][29]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][30]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][30]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][30]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][31]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][31]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][31]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][32]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][32]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][32]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][33]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][33]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][33]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][34]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][34]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][34]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][35]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][35]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][35]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][36]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][36]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][36]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][37]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][37]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][37]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][38]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][38]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][38]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][39]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][39]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][39]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][40]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][40]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][40]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][44]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][44]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][44]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][45]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][45]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][45]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][47]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][47]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][47]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][4]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][4]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][4]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][50]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][50]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][50]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][5]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][5]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][5]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][6]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][6]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][6]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][7]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][7]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][7]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][8]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][8]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][8]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][9]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][9]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][9]_srl4 "; +begin + \out\(40 downto 0) <= \^out\(40 downto 0); + sig_calc_error_reg_reg <= \^sig_calc_error_reg_reg\; +\INFERRED_GEN.data_reg[3][10]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(6), + Q => \^out\(6) + ); +\INFERRED_GEN.data_reg[3][11]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(7), + Q => \^out\(7) + ); +\INFERRED_GEN.data_reg[3][12]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(8), + Q => \^out\(8) + ); +\INFERRED_GEN.data_reg[3][13]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(9), + Q => \^out\(9) + ); +\INFERRED_GEN.data_reg[3][14]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(10), + Q => \^out\(10) + ); +\INFERRED_GEN.data_reg[3][15]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(11), + Q => \^out\(11) + ); +\INFERRED_GEN.data_reg[3][16]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(12), + Q => \^out\(12) + ); +\INFERRED_GEN.data_reg[3][17]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(13), + Q => \^out\(13) + ); +\INFERRED_GEN.data_reg[3][18]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(14), + Q => \^out\(14) + ); +\INFERRED_GEN.data_reg[3][19]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(15), + Q => \^out\(15) + ); +\INFERRED_GEN.data_reg[3][20]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(16), + Q => \^out\(16) + ); +\INFERRED_GEN.data_reg[3][21]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(17), + Q => \^out\(17) + ); +\INFERRED_GEN.data_reg[3][22]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(18), + Q => \^out\(18) + ); +\INFERRED_GEN.data_reg[3][23]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(19), + Q => \^out\(19) + ); +\INFERRED_GEN.data_reg[3][24]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(20), + Q => \^out\(20) + ); +\INFERRED_GEN.data_reg[3][25]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(21), + Q => \^out\(21) + ); +\INFERRED_GEN.data_reg[3][26]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(22), + Q => \^out\(22) + ); +\INFERRED_GEN.data_reg[3][27]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(23), + Q => \^out\(23) + ); +\INFERRED_GEN.data_reg[3][28]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(24), + Q => \^out\(24) + ); +\INFERRED_GEN.data_reg[3][29]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(25), + Q => \^out\(25) + ); +\INFERRED_GEN.data_reg[3][30]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(26), + Q => \^out\(26) + ); +\INFERRED_GEN.data_reg[3][31]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(27), + Q => \^out\(27) + ); +\INFERRED_GEN.data_reg[3][32]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(28), + Q => \^out\(28) + ); +\INFERRED_GEN.data_reg[3][33]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(29), + Q => \^out\(29) + ); +\INFERRED_GEN.data_reg[3][34]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(30), + Q => \^out\(30) + ); +\INFERRED_GEN.data_reg[3][35]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(31), + Q => \^out\(31) + ); +\INFERRED_GEN.data_reg[3][36]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(32), + Q => \^out\(32) + ); +\INFERRED_GEN.data_reg[3][37]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(33), + Q => \^out\(33) + ); +\INFERRED_GEN.data_reg[3][38]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(34), + Q => \^out\(34) + ); +\INFERRED_GEN.data_reg[3][39]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(35), + Q => \^out\(35) + ); +\INFERRED_GEN.data_reg[3][40]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(36), + Q => \^out\(36) + ); +\INFERRED_GEN.data_reg[3][44]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => '1', + Q => \^out\(37) + ); +\INFERRED_GEN.data_reg[3][45]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => '1', + Q => \^out\(38) + ); +\INFERRED_GEN.data_reg[3][47]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(37), + Q => \^out\(39) + ); +\INFERRED_GEN.data_reg[3][4]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(0), + Q => \^out\(0) + ); +\INFERRED_GEN.data_reg[3][4]_srl4_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => FIFO_Full_reg, + I1 => sig_inhibit_rdy_n, + I2 => sig_mstr2addr_cmd_valid, + O => \^sig_calc_error_reg_reg\ + ); +\INFERRED_GEN.data_reg[3][50]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(38), + Q => \^out\(40) + ); +\INFERRED_GEN.data_reg[3][5]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(1), + Q => \^out\(1) + ); +\INFERRED_GEN.data_reg[3][6]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(2), + Q => \^out\(2) + ); +\INFERRED_GEN.data_reg[3][7]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(3), + Q => \^out\(3) + ); +\INFERRED_GEN.data_reg[3][8]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(4), + Q => \^out\(4) + ); +\INFERRED_GEN.data_reg[3][9]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(5), + Q => \^out\(5) + ); +sig_addr_valid_reg_i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^out\(40), + O => sig_addr_valid_reg_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized10\ is + port ( + sig_last_dbeat_reg : out STD_LOGIC; + sig_wr_fifo : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 5 downto 0 ); + \out\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \sig_first_dbeat1__0\ : in STD_LOGIC; + sig_next_sequential_reg_reg : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_single_dbeat : in STD_LOGIC; + sig_last_dbeat_reg_0 : in STD_LOGIC; + p_11_out : in STD_LOGIC; + FIFO_Full_reg : in STD_LOGIC; + sig_inhibit_rdy_n_reg : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 5 downto 0 ); + \sig_dbeat_cntr_reg[2]\ : in STD_LOGIC; + \sig_dbeat_cntr_reg[3]\ : in STD_LOGIC; + sig_xfer_calc_err_reg_reg : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \INFERRED_GEN.cnt_i_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized10\ : entity is "dynshreg_f"; +end \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized10\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized10\ is + signal sig_cmd_fifo_data_out : STD_LOGIC_VECTOR ( 12 downto 7 ); + signal \sig_new_len_eq_0__6\ : STD_LOGIC; + signal \^sig_wr_fifo\ : STD_LOGIC; + attribute srl_bus_name : string; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][10]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name : string; + attribute srl_name of \INFERRED_GEN.data_reg[3][10]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][10]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][11]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][11]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][11]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][12]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][12]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][12]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][33]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][33]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][33]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][34]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][34]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][34]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][35]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][35]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][35]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][7]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][7]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][7]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][8]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][8]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][8]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][9]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][9]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][9]_srl4 "; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \sig_dbeat_cntr[0]_i_1__0\ : label is "soft_lutpair243"; + attribute SOFT_HLUTNM of \sig_dbeat_cntr[1]_i_1__0\ : label is "soft_lutpair243"; +begin + sig_wr_fifo <= \^sig_wr_fifo\; +\INFERRED_GEN.data_reg[3][10]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[1]\(0), + A1 => \INFERRED_GEN.cnt_i_reg[1]\(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => sig_xfer_calc_err_reg_reg(3), + Q => sig_cmd_fifo_data_out(10) + ); +\INFERRED_GEN.data_reg[3][11]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[1]\(0), + A1 => \INFERRED_GEN.cnt_i_reg[1]\(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => sig_xfer_calc_err_reg_reg(4), + Q => sig_cmd_fifo_data_out(11) + ); +\INFERRED_GEN.data_reg[3][12]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[1]\(0), + A1 => \INFERRED_GEN.cnt_i_reg[1]\(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => sig_xfer_calc_err_reg_reg(5), + Q => sig_cmd_fifo_data_out(12) + ); +\INFERRED_GEN.data_reg[3][33]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[1]\(0), + A1 => \INFERRED_GEN.cnt_i_reg[1]\(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => sig_xfer_calc_err_reg_reg(6), + Q => \out\(0) + ); +\INFERRED_GEN.data_reg[3][34]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[1]\(0), + A1 => \INFERRED_GEN.cnt_i_reg[1]\(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => sig_xfer_calc_err_reg_reg(7), + Q => \out\(1) + ); +\INFERRED_GEN.data_reg[3][35]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[1]\(0), + A1 => \INFERRED_GEN.cnt_i_reg[1]\(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => sig_xfer_calc_err_reg_reg(8), + Q => \out\(2) + ); +\INFERRED_GEN.data_reg[3][7]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[1]\(0), + A1 => \INFERRED_GEN.cnt_i_reg[1]\(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => sig_xfer_calc_err_reg_reg(0), + Q => sig_cmd_fifo_data_out(7) + ); +\INFERRED_GEN.data_reg[3][7]_srl4_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"20" + ) + port map ( + I0 => p_11_out, + I1 => FIFO_Full_reg, + I2 => sig_inhibit_rdy_n_reg, + O => \^sig_wr_fifo\ + ); +\INFERRED_GEN.data_reg[3][8]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[1]\(0), + A1 => \INFERRED_GEN.cnt_i_reg[1]\(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => sig_xfer_calc_err_reg_reg(1), + Q => sig_cmd_fifo_data_out(8) + ); +\INFERRED_GEN.data_reg[3][9]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[1]\(0), + A1 => \INFERRED_GEN.cnt_i_reg[1]\(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => sig_xfer_calc_err_reg_reg(2), + Q => sig_cmd_fifo_data_out(9) + ); +\sig_dbeat_cntr[0]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => sig_cmd_fifo_data_out(7), + I1 => sig_next_sequential_reg_reg, + I2 => Q(0), + O => D(0) + ); +\sig_dbeat_cntr[1]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"B88B" + ) + port map ( + I0 => sig_cmd_fifo_data_out(8), + I1 => sig_next_sequential_reg_reg, + I2 => Q(0), + I3 => Q(1), + O => D(1) + ); +\sig_dbeat_cntr[2]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB8888B" + ) + port map ( + I0 => sig_cmd_fifo_data_out(9), + I1 => sig_next_sequential_reg_reg, + I2 => Q(1), + I3 => Q(0), + I4 => Q(2), + O => D(2) + ); +\sig_dbeat_cntr[3]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBBBB88888888B" + ) + port map ( + I0 => sig_cmd_fifo_data_out(10), + I1 => sig_next_sequential_reg_reg, + I2 => Q(2), + I3 => Q(0), + I4 => Q(1), + I5 => Q(3), + O => D(3) + ); +\sig_dbeat_cntr[4]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"B88B" + ) + port map ( + I0 => sig_cmd_fifo_data_out(11), + I1 => sig_next_sequential_reg_reg, + I2 => \sig_dbeat_cntr_reg[2]\, + I3 => Q(4), + O => D(4) + ); +\sig_dbeat_cntr[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"B88B" + ) + port map ( + I0 => sig_cmd_fifo_data_out(12), + I1 => sig_next_sequential_reg_reg, + I2 => \sig_dbeat_cntr_reg[3]\, + I3 => Q(5), + O => D(5) + ); +\sig_last_dbeat_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CA00CF00CA00C000" + ) + port map ( + I0 => \sig_first_dbeat1__0\, + I1 => \sig_new_len_eq_0__6\, + I2 => sig_next_sequential_reg_reg, + I3 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I4 => sig_single_dbeat, + I5 => sig_last_dbeat_reg_0, + O => sig_last_dbeat_reg + ); +\sig_last_dbeat_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000001" + ) + port map ( + I0 => sig_cmd_fifo_data_out(11), + I1 => sig_cmd_fifo_data_out(12), + I2 => sig_cmd_fifo_data_out(8), + I3 => sig_cmd_fifo_data_out(7), + I4 => sig_cmd_fifo_data_out(10), + I5 => sig_cmd_fifo_data_out(9), + O => \sig_new_len_eq_0__6\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized2\ is + port ( + sig_next_calc_error_reg_reg : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 4 downto 0 ); + sig_last_dbeat_reg : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + FIFO_Full_reg : in STD_LOGIC; + sig_inhibit_rdy_n_0 : in STD_LOGIC; + sig_mstr2data_cmd_valid : in STD_LOGIC; + sig_next_sequential_reg_reg : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \sig_dbeat_cntr_reg[3]\ : in STD_LOGIC; + \sig_dbeat_cntr_reg[0]\ : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \INFERRED_GEN.cnt_i_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_mm2s_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized2\ : entity is "dynshreg_f"; +end \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized2\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized2\ is + signal sig_cmd_fifo_data_out : STD_LOGIC_VECTOR ( 11 downto 7 ); + signal sig_last_dbeat_i_3_n_0 : STD_LOGIC; + signal \^sig_next_calc_error_reg_reg\ : STD_LOGIC; + attribute srl_bus_name : string; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][10]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name : string; + attribute srl_name of \INFERRED_GEN.data_reg[3][10]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][10]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][11]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][11]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][11]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][32]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][32]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][32]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][33]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][33]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][33]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][34]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][34]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][34]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][35]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][35]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][35]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][7]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][7]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][7]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][8]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][8]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][8]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][9]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][9]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][9]_srl4 "; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \sig_dbeat_cntr[0]_i_1\ : label is "soft_lutpair161"; + attribute SOFT_HLUTNM of \sig_dbeat_cntr[1]_i_1\ : label is "soft_lutpair161"; +begin + sig_next_calc_error_reg_reg <= \^sig_next_calc_error_reg_reg\; +\INFERRED_GEN.data_reg[3][10]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[1]\(0), + A1 => \INFERRED_GEN.cnt_i_reg[1]\(1), + A2 => '0', + A3 => '0', + CE => \^sig_next_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(3), + Q => sig_cmd_fifo_data_out(10) + ); +\INFERRED_GEN.data_reg[3][11]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[1]\(0), + A1 => \INFERRED_GEN.cnt_i_reg[1]\(1), + A2 => '0', + A3 => '0', + CE => \^sig_next_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(4), + Q => sig_cmd_fifo_data_out(11) + ); +\INFERRED_GEN.data_reg[3][32]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[1]\(0), + A1 => \INFERRED_GEN.cnt_i_reg[1]\(1), + A2 => '0', + A3 => '0', + CE => \^sig_next_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(5), + Q => \out\(0) + ); +\INFERRED_GEN.data_reg[3][33]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[1]\(0), + A1 => \INFERRED_GEN.cnt_i_reg[1]\(1), + A2 => '0', + A3 => '0', + CE => \^sig_next_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(6), + Q => \out\(1) + ); +\INFERRED_GEN.data_reg[3][34]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[1]\(0), + A1 => \INFERRED_GEN.cnt_i_reg[1]\(1), + A2 => '0', + A3 => '0', + CE => \^sig_next_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(7), + Q => \out\(2) + ); +\INFERRED_GEN.data_reg[3][35]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[1]\(0), + A1 => \INFERRED_GEN.cnt_i_reg[1]\(1), + A2 => '0', + A3 => '0', + CE => \^sig_next_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(8), + Q => \out\(3) + ); +\INFERRED_GEN.data_reg[3][7]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[1]\(0), + A1 => \INFERRED_GEN.cnt_i_reg[1]\(1), + A2 => '0', + A3 => '0', + CE => \^sig_next_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(0), + Q => sig_cmd_fifo_data_out(7) + ); +\INFERRED_GEN.data_reg[3][7]_srl4_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => FIFO_Full_reg, + I1 => sig_inhibit_rdy_n_0, + I2 => sig_mstr2data_cmd_valid, + O => \^sig_next_calc_error_reg_reg\ + ); +\INFERRED_GEN.data_reg[3][8]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[1]\(0), + A1 => \INFERRED_GEN.cnt_i_reg[1]\(1), + A2 => '0', + A3 => '0', + CE => \^sig_next_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(1), + Q => sig_cmd_fifo_data_out(8) + ); +\INFERRED_GEN.data_reg[3][9]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[1]\(0), + A1 => \INFERRED_GEN.cnt_i_reg[1]\(1), + A2 => '0', + A3 => '0', + CE => \^sig_next_calc_error_reg_reg\, + CLK => m_axi_mm2s_aclk, + D => \in\(2), + Q => sig_cmd_fifo_data_out(9) + ); +\sig_dbeat_cntr[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => sig_cmd_fifo_data_out(7), + I1 => sig_next_sequential_reg_reg, + I2 => Q(0), + O => D(0) + ); +\sig_dbeat_cntr[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"B88B" + ) + port map ( + I0 => sig_cmd_fifo_data_out(8), + I1 => sig_next_sequential_reg_reg, + I2 => Q(1), + I3 => Q(0), + O => D(1) + ); +\sig_dbeat_cntr[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8B8B88B" + ) + port map ( + I0 => sig_cmd_fifo_data_out(9), + I1 => sig_next_sequential_reg_reg, + I2 => Q(2), + I3 => Q(0), + I4 => Q(1), + O => D(2) + ); +\sig_dbeat_cntr[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"B8B8B8B8B8B8B88B" + ) + port map ( + I0 => sig_cmd_fifo_data_out(10), + I1 => sig_next_sequential_reg_reg, + I2 => Q(3), + I3 => Q(2), + I4 => Q(1), + I5 => Q(0), + O => D(3) + ); +\sig_dbeat_cntr[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8BB8" + ) + port map ( + I0 => sig_cmd_fifo_data_out(11), + I1 => sig_next_sequential_reg_reg, + I2 => Q(4), + I3 => \sig_dbeat_cntr_reg[0]\, + O => D(4) + ); +sig_last_dbeat_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"0535" + ) + port map ( + I0 => \sig_dbeat_cntr_reg[3]\, + I1 => sig_last_dbeat_i_3_n_0, + I2 => sig_next_sequential_reg_reg, + I3 => sig_cmd_fifo_data_out(11), + O => sig_last_dbeat_reg + ); +sig_last_dbeat_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => sig_cmd_fifo_data_out(8), + I1 => sig_cmd_fifo_data_out(7), + I2 => sig_cmd_fifo_data_out(10), + I3 => sig_cmd_fifo_data_out(9), + O => sig_last_dbeat_i_3_n_0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized3\ is + port ( + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : out STD_LOGIC; + FIFO_Full_reg : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + lsig_cmd_loaded : in STD_LOGIC; + prmry_resetn_i_reg : in STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ : in STD_LOGIC; + DOBDO : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized3\ : entity is "dynshreg_f"; +end \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized3\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized3\ is + signal p_0_out : STD_LOGIC_VECTOR ( 7 to 7 ); + attribute srl_bus_name : string; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][7]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name : string; + attribute srl_name of \INFERRED_GEN.data_reg[3][7]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][7]_srl4 "; +begin +\INCLUDE_UNPACKING.lsig_0ffset_cntr[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0FF00FF0AEE22EE2" + ) + port map ( + I0 => p_0_out(7), + I1 => lsig_cmd_loaded, + I2 => prmry_resetn_i_reg, + I3 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I4 => DOBDO(0), + I5 => Q(2), + O => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ + ); +\INFERRED_GEN.data_reg[3][7]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => FIFO_Full_reg, + CLK => m_axi_mm2s_aclk, + D => \in\(0), + Q => p_0_out(7) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized4\ is + port ( + \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + CO : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_STS_GRTR_THAN_8.ovrflo_err_reg\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + decerr_i_reg : out STD_LOGIC; + slverr_i_reg : out STD_LOGIC; + interr_i_reg : out STD_LOGIC; + sig_wr_fifo : out STD_LOGIC; + \hsize_vid_reg[15]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + \hsize_vid_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + S : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_wsc2stat_status_valid : in STD_LOGIC; + FIFO_Full_reg : in STD_LOGIC; + sig_inhibit_rdy_n : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 16 downto 0 ); + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized4\ : entity is "dynshreg_f"; +end \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized4\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized4\ is + signal \GEN_STS_GRTR_THAN_8.ovrflo_err_i_4_n_0\ : STD_LOGIC; + signal \GEN_STS_GRTR_THAN_8.ovrflo_err_i_5_n_0\ : STD_LOGIC; + signal \GEN_STS_GRTR_THAN_8.ovrflo_err_i_6_n_0\ : STD_LOGIC; + signal \GEN_STS_GRTR_THAN_8.ovrflo_err_i_7_n_0\ : STD_LOGIC; + signal \GEN_STS_GRTR_THAN_8.ovrflo_err_i_8_n_0\ : STD_LOGIC; + signal \GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_2_n_3\ : STD_LOGIC; + signal \GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_3_n_0\ : STD_LOGIC; + signal \GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_3_n_1\ : STD_LOGIC; + signal \GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_3_n_2\ : STD_LOGIC; + signal \GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_3_n_3\ : STD_LOGIC; + signal \GEN_STS_GRTR_THAN_8.undrflo_err_i_4_n_0\ : STD_LOGIC; + signal \GEN_STS_GRTR_THAN_8.undrflo_err_i_5_n_0\ : STD_LOGIC; + signal \GEN_STS_GRTR_THAN_8.undrflo_err_i_6_n_0\ : STD_LOGIC; + signal \GEN_STS_GRTR_THAN_8.undrflo_err_i_7_n_0\ : STD_LOGIC; + signal \GEN_STS_GRTR_THAN_8.undrflo_err_i_8_n_0\ : STD_LOGIC; + signal \GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_2_n_3\ : STD_LOGIC; + signal \GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_3_n_0\ : STD_LOGIC; + signal \GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_3_n_1\ : STD_LOGIC; + signal \GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_3_n_2\ : STD_LOGIC; + signal \GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_3_n_3\ : STD_LOGIC; + signal m_axis_s2mm_sts_tdata : STD_LOGIC_VECTOR ( 23 downto 4 ); + signal \^sig_wr_fifo\ : STD_LOGIC; + signal \NLW_GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute METHODOLOGY_DRC_VIOS : string; + attribute METHODOLOGY_DRC_VIOS of \GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_2\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_3\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_2\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_3\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute srl_bus_name : string; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][11]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name : string; + attribute srl_name of \INFERRED_GEN.data_reg[3][11]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][11]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][12]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][12]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][12]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][13]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][13]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][13]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][14]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][14]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][14]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][15]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][15]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][15]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][16]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][16]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][16]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][17]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][17]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][17]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][18]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][18]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][18]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][19]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][19]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][19]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][20]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][20]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][20]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][21]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][21]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][21]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][22]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][22]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][22]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][23]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][23]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][23]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][31]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][31]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][31]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][4]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][4]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][4]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][5]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][5]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][5]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][6]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][6]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][6]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][8]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][8]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][8]_srl4 "; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \decerr_i_i_1__0\ : label is "soft_lutpair237"; + attribute SOFT_HLUTNM of \slverr_i_i_1__0\ : label is "soft_lutpair237"; +begin + sig_wr_fifo <= \^sig_wr_fifo\; +\GEN_STS_GRTR_THAN_8.ovrflo_err_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => m_axis_s2mm_sts_tdata(23), + I1 => \hsize_vid_reg[15]\(12), + O => \GEN_STS_GRTR_THAN_8.ovrflo_err_i_4_n_0\ + ); +\GEN_STS_GRTR_THAN_8.ovrflo_err_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => m_axis_s2mm_sts_tdata(22), + I1 => \hsize_vid_reg[15]\(11), + I2 => m_axis_s2mm_sts_tdata(20), + I3 => \hsize_vid_reg[15]\(9), + I4 => \hsize_vid_reg[15]\(10), + I5 => m_axis_s2mm_sts_tdata(21), + O => \GEN_STS_GRTR_THAN_8.ovrflo_err_i_5_n_0\ + ); +\GEN_STS_GRTR_THAN_8.ovrflo_err_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => m_axis_s2mm_sts_tdata(19), + I1 => \hsize_vid_reg[15]\(8), + I2 => m_axis_s2mm_sts_tdata(18), + I3 => \hsize_vid_reg[15]\(7), + I4 => \hsize_vid_reg[15]\(6), + I5 => m_axis_s2mm_sts_tdata(17), + O => \GEN_STS_GRTR_THAN_8.ovrflo_err_i_6_n_0\ + ); +\GEN_STS_GRTR_THAN_8.ovrflo_err_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => m_axis_s2mm_sts_tdata(16), + I1 => \hsize_vid_reg[15]\(5), + I2 => m_axis_s2mm_sts_tdata(14), + I3 => \hsize_vid_reg[15]\(3), + I4 => \hsize_vid_reg[15]\(4), + I5 => m_axis_s2mm_sts_tdata(15), + O => \GEN_STS_GRTR_THAN_8.ovrflo_err_i_7_n_0\ + ); +\GEN_STS_GRTR_THAN_8.ovrflo_err_i_8\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => m_axis_s2mm_sts_tdata(13), + I1 => \hsize_vid_reg[15]\(2), + I2 => m_axis_s2mm_sts_tdata(12), + I3 => \hsize_vid_reg[15]\(1), + I4 => \hsize_vid_reg[15]\(0), + I5 => m_axis_s2mm_sts_tdata(11), + O => \GEN_STS_GRTR_THAN_8.ovrflo_err_i_8_n_0\ + ); +\GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => \GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_3_n_0\, + CO(3 downto 2) => \NLW_GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_2_CO_UNCONNECTED\(3 downto 2), + CO(1) => \GEN_STS_GRTR_THAN_8.ovrflo_err_reg\(0), + CO(0) => \GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_2_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => \NLW_GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_2_O_UNCONNECTED\(3 downto 0), + S(3 downto 2) => B"00", + S(1) => \GEN_STS_GRTR_THAN_8.ovrflo_err_i_4_n_0\, + S(0) => \GEN_STS_GRTR_THAN_8.ovrflo_err_i_5_n_0\ + ); +\GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_3\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_3_n_0\, + CO(2) => \GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_3_n_1\, + CO(1) => \GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_3_n_2\, + CO(0) => \GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_3_n_3\, + CYINIT => '1', + DI(3 downto 0) => B"0000", + O(3 downto 0) => \NLW_GEN_STS_GRTR_THAN_8.ovrflo_err_reg_i_3_O_UNCONNECTED\(3 downto 0), + S(3) => \GEN_STS_GRTR_THAN_8.ovrflo_err_i_6_n_0\, + S(2) => \GEN_STS_GRTR_THAN_8.ovrflo_err_i_7_n_0\, + S(1) => \GEN_STS_GRTR_THAN_8.ovrflo_err_i_8_n_0\, + S(0) => S(0) + ); +\GEN_STS_GRTR_THAN_8.undrflo_err_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => m_axis_s2mm_sts_tdata(23), + I1 => \hsize_vid_reg[15]\(12), + O => \GEN_STS_GRTR_THAN_8.undrflo_err_i_4_n_0\ + ); +\GEN_STS_GRTR_THAN_8.undrflo_err_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => m_axis_s2mm_sts_tdata(22), + I1 => \hsize_vid_reg[15]\(11), + I2 => m_axis_s2mm_sts_tdata(20), + I3 => \hsize_vid_reg[15]\(9), + I4 => \hsize_vid_reg[15]\(10), + I5 => m_axis_s2mm_sts_tdata(21), + O => \GEN_STS_GRTR_THAN_8.undrflo_err_i_5_n_0\ + ); +\GEN_STS_GRTR_THAN_8.undrflo_err_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => m_axis_s2mm_sts_tdata(19), + I1 => \hsize_vid_reg[15]\(8), + I2 => m_axis_s2mm_sts_tdata(18), + I3 => \hsize_vid_reg[15]\(7), + I4 => \hsize_vid_reg[15]\(6), + I5 => m_axis_s2mm_sts_tdata(17), + O => \GEN_STS_GRTR_THAN_8.undrflo_err_i_6_n_0\ + ); +\GEN_STS_GRTR_THAN_8.undrflo_err_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => m_axis_s2mm_sts_tdata(16), + I1 => \hsize_vid_reg[15]\(5), + I2 => m_axis_s2mm_sts_tdata(14), + I3 => \hsize_vid_reg[15]\(3), + I4 => \hsize_vid_reg[15]\(4), + I5 => m_axis_s2mm_sts_tdata(15), + O => \GEN_STS_GRTR_THAN_8.undrflo_err_i_7_n_0\ + ); +\GEN_STS_GRTR_THAN_8.undrflo_err_i_8\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => m_axis_s2mm_sts_tdata(13), + I1 => \hsize_vid_reg[15]\(2), + I2 => m_axis_s2mm_sts_tdata(12), + I3 => \hsize_vid_reg[15]\(1), + I4 => \hsize_vid_reg[15]\(0), + I5 => m_axis_s2mm_sts_tdata(11), + O => \GEN_STS_GRTR_THAN_8.undrflo_err_i_8_n_0\ + ); +\GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => \GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_3_n_0\, + CO(3 downto 2) => \NLW_GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_2_CO_UNCONNECTED\(3 downto 2), + CO(1) => CO(0), + CO(0) => \GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_2_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0011", + O(3 downto 0) => \NLW_GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_2_O_UNCONNECTED\(3 downto 0), + S(3 downto 2) => B"00", + S(1) => \GEN_STS_GRTR_THAN_8.undrflo_err_i_4_n_0\, + S(0) => \GEN_STS_GRTR_THAN_8.undrflo_err_i_5_n_0\ + ); +\GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_3\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_3_n_0\, + CO(2) => \GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_3_n_1\, + CO(1) => \GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_3_n_2\, + CO(0) => \GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_3_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"1111", + O(3 downto 0) => \NLW_GEN_STS_GRTR_THAN_8.undrflo_err_reg_i_3_O_UNCONNECTED\(3 downto 0), + S(3) => \GEN_STS_GRTR_THAN_8.undrflo_err_i_6_n_0\, + S(2) => \GEN_STS_GRTR_THAN_8.undrflo_err_i_7_n_0\, + S(1) => \GEN_STS_GRTR_THAN_8.undrflo_err_i_8_n_0\, + S(0) => \hsize_vid_reg[2]\(0) + ); +\INFERRED_GEN.data_reg[3][11]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(3), + Q => m_axis_s2mm_sts_tdata(11) + ); +\INFERRED_GEN.data_reg[3][12]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(4), + Q => m_axis_s2mm_sts_tdata(12) + ); +\INFERRED_GEN.data_reg[3][13]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(5), + Q => m_axis_s2mm_sts_tdata(13) + ); +\INFERRED_GEN.data_reg[3][14]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(6), + Q => m_axis_s2mm_sts_tdata(14) + ); +\INFERRED_GEN.data_reg[3][15]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(7), + Q => m_axis_s2mm_sts_tdata(15) + ); +\INFERRED_GEN.data_reg[3][16]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(8), + Q => m_axis_s2mm_sts_tdata(16) + ); +\INFERRED_GEN.data_reg[3][17]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(9), + Q => m_axis_s2mm_sts_tdata(17) + ); +\INFERRED_GEN.data_reg[3][18]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(10), + Q => m_axis_s2mm_sts_tdata(18) + ); +\INFERRED_GEN.data_reg[3][19]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(11), + Q => m_axis_s2mm_sts_tdata(19) + ); +\INFERRED_GEN.data_reg[3][20]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(12), + Q => m_axis_s2mm_sts_tdata(20) + ); +\INFERRED_GEN.data_reg[3][21]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(13), + Q => m_axis_s2mm_sts_tdata(21) + ); +\INFERRED_GEN.data_reg[3][22]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(14), + Q => m_axis_s2mm_sts_tdata(22) + ); +\INFERRED_GEN.data_reg[3][23]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(15), + Q => m_axis_s2mm_sts_tdata(23) + ); +\INFERRED_GEN.data_reg[3][31]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(16), + Q => \out\(1) + ); +\INFERRED_GEN.data_reg[3][4]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(0), + Q => m_axis_s2mm_sts_tdata(4) + ); +\INFERRED_GEN.data_reg[3][4]_srl4_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"20" + ) + port map ( + I0 => sig_wsc2stat_status_valid, + I1 => FIFO_Full_reg, + I2 => sig_inhibit_rdy_n, + O => \^sig_wr_fifo\ + ); +\INFERRED_GEN.data_reg[3][5]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(1), + Q => m_axis_s2mm_sts_tdata(5) + ); +\INFERRED_GEN.data_reg[3][6]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(2), + Q => m_axis_s2mm_sts_tdata(6) + ); +\INFERRED_GEN.data_reg[3][8]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => '0', + Q => \out\(0) + ); +\decerr_i_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => m_axis_s2mm_sts_tdata(5), + I1 => Q(2), + O => decerr_i_reg + ); +\interr_i_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => m_axis_s2mm_sts_tdata(4), + I1 => Q(2), + O => interr_i_reg + ); +\slverr_i_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => m_axis_s2mm_sts_tdata(6), + I1 => Q(2), + O => slverr_i_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized5\ is + port ( + \GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg\ : out STD_LOGIC; + \GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg\ : out STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + sel : in STD_LOGIC; + m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + addr : in STD_LOGIC_VECTOR ( 0 to 2 ); + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized5\ : entity is "dynshreg_f"; +end \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized5\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized5\ is + signal sig_wresp_sfifo_out : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_i_1\ : label is "soft_lutpair250"; + attribute SOFT_HLUTNM of \GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_i_1\ : label is "soft_lutpair250"; + attribute srl_bus_name : string; + attribute srl_bus_name of \INFERRED_GEN.data_reg[5][0]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] "; + attribute srl_name : string; + attribute srl_name of \INFERRED_GEN.data_reg[5][0]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][0]_srl6 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[5][1]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] "; + attribute srl_name of \INFERRED_GEN.data_reg[5][1]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][1]_srl6 "; +begin +\GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00EA" + ) + port map ( + I0 => \in\(0), + I1 => sig_wresp_sfifo_out(0), + I2 => sig_wresp_sfifo_out(1), + I3 => \out\(0), + O => \GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg\ + ); +\GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00AE" + ) + port map ( + I0 => \in\(1), + I1 => sig_wresp_sfifo_out(1), + I2 => sig_wresp_sfifo_out(0), + I3 => \out\(0), + O => \GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg\ + ); +\INFERRED_GEN.data_reg[5][0]_srl6\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => addr(2), + A1 => addr(1), + A2 => addr(0), + A3 => '0', + CE => sel, + CLK => m_axi_s2mm_aclk, + D => m_axi_s2mm_bresp(0), + Q => sig_wresp_sfifo_out(0) + ); +\INFERRED_GEN.data_reg[5][1]_srl6\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => addr(2), + A1 => addr(1), + A2 => addr(0), + A3 => '0', + CE => sel, + CLK => m_axi_s2mm_aclk, + D => m_axi_s2mm_bresp(1), + Q => sig_wresp_sfifo_out(1) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized6\ is + port ( + p_0_in : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg\ : out STD_LOGIC; + \sig_wdc_statcnt_reg[3]\ : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + p_4_out : out STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \INFERRED_GEN.cnt_i_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_coelsc_reg_empty : in STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + sig_data2wsc_valid : in STD_LOGIC; + FIFO_Full_reg : in STD_LOGIC; + sig_inhibit_rdy_n : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_INDET_BTT.lsig_eop_reg_reg\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized6\ : entity is "dynshreg_f"; +end \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized6\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized6\ is + signal \^gen_enable_indet_btt.sig_coelsc_eop_reg\ : STD_LOGIC; + signal \^out\ : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \^sig_wdc_statcnt_reg[3]\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \GEN_ENABLE_INDET_BTT.sig_coelsc_interr_reg_i_1\ : label is "soft_lutpair249"; + attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[1]_i_2__0\ : label is "soft_lutpair249"; + attribute srl_bus_name : string; + attribute srl_bus_name of \INFERRED_GEN.data_reg[5][10]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] "; + attribute srl_name : string; + attribute srl_name of \INFERRED_GEN.data_reg[5][10]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][10]_srl6 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[5][11]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] "; + attribute srl_name of \INFERRED_GEN.data_reg[5][11]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][11]_srl6 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[5][12]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] "; + attribute srl_name of \INFERRED_GEN.data_reg[5][12]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][12]_srl6 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[5][13]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] "; + attribute srl_name of \INFERRED_GEN.data_reg[5][13]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][13]_srl6 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[5][14]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] "; + attribute srl_name of \INFERRED_GEN.data_reg[5][14]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][14]_srl6 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[5][15]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] "; + attribute srl_name of \INFERRED_GEN.data_reg[5][15]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][15]_srl6 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[5][16]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] "; + attribute srl_name of \INFERRED_GEN.data_reg[5][16]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][16]_srl6 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[5][17]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] "; + attribute srl_name of \INFERRED_GEN.data_reg[5][17]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][17]_srl6 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[5][18]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] "; + attribute srl_name of \INFERRED_GEN.data_reg[5][18]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][18]_srl6 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[5][19]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] "; + attribute srl_name of \INFERRED_GEN.data_reg[5][19]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][19]_srl6 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[5][20]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] "; + attribute srl_name of \INFERRED_GEN.data_reg[5][20]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][20]_srl6 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[5][21]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] "; + attribute srl_name of \INFERRED_GEN.data_reg[5][21]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][21]_srl6 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[5][22]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] "; + attribute srl_name of \INFERRED_GEN.data_reg[5][22]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][22]_srl6 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[5][4]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] "; + attribute srl_name of \INFERRED_GEN.data_reg[5][4]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][4]_srl6 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[5][5]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] "; + attribute srl_name of \INFERRED_GEN.data_reg[5][5]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][5]_srl6 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[5][9]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5] "; + attribute srl_name of \INFERRED_GEN.data_reg[5][9]_srl6\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[5][9]_srl6 "; +begin + \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg\ <= \^gen_enable_indet_btt.sig_coelsc_eop_reg\; + \out\(15 downto 0) <= \^out\(15 downto 0); + \sig_wdc_statcnt_reg[3]\ <= \^sig_wdc_statcnt_reg[3]\; +\GEN_ENABLE_INDET_BTT.sig_coelsc_interr_reg_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \in\(0), + I1 => \^out\(0), + O => p_4_out + ); +\GEN_ENABLE_INDET_BTT.sig_coelsc_reg_empty_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^out\(1), + O => p_0_in + ); +\INFERRED_GEN.cnt_i[1]_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00D0" + ) + port map ( + I0 => \INFERRED_GEN.cnt_i_reg[3]\(0), + I1 => \^out\(0), + I2 => sig_coelsc_reg_empty, + I3 => \INFERRED_GEN.cnt_i_reg[3]_0\(3), + O => \^sig_wdc_statcnt_reg[3]\ + ); +\INFERRED_GEN.data_reg[5][10]_srl6\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[3]_0\(0), + A1 => \INFERRED_GEN.cnt_i_reg[3]_0\(1), + A2 => \INFERRED_GEN.cnt_i_reg[3]_0\(2), + A3 => '0', + CE => \^gen_enable_indet_btt.sig_coelsc_eop_reg\, + CLK => m_axi_s2mm_aclk, + D => \GEN_INDET_BTT.lsig_eop_reg_reg\(3), + Q => \^out\(3) + ); +\INFERRED_GEN.data_reg[5][11]_srl6\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[3]_0\(0), + A1 => \INFERRED_GEN.cnt_i_reg[3]_0\(1), + A2 => \INFERRED_GEN.cnt_i_reg[3]_0\(2), + A3 => '0', + CE => \^gen_enable_indet_btt.sig_coelsc_eop_reg\, + CLK => m_axi_s2mm_aclk, + D => \GEN_INDET_BTT.lsig_eop_reg_reg\(4), + Q => \^out\(4) + ); +\INFERRED_GEN.data_reg[5][12]_srl6\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[3]_0\(0), + A1 => \INFERRED_GEN.cnt_i_reg[3]_0\(1), + A2 => \INFERRED_GEN.cnt_i_reg[3]_0\(2), + A3 => '0', + CE => \^gen_enable_indet_btt.sig_coelsc_eop_reg\, + CLK => m_axi_s2mm_aclk, + D => \GEN_INDET_BTT.lsig_eop_reg_reg\(5), + Q => \^out\(5) + ); +\INFERRED_GEN.data_reg[5][13]_srl6\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[3]_0\(0), + A1 => \INFERRED_GEN.cnt_i_reg[3]_0\(1), + A2 => \INFERRED_GEN.cnt_i_reg[3]_0\(2), + A3 => '0', + CE => \^gen_enable_indet_btt.sig_coelsc_eop_reg\, + CLK => m_axi_s2mm_aclk, + D => \GEN_INDET_BTT.lsig_eop_reg_reg\(6), + Q => \^out\(6) + ); +\INFERRED_GEN.data_reg[5][14]_srl6\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[3]_0\(0), + A1 => \INFERRED_GEN.cnt_i_reg[3]_0\(1), + A2 => \INFERRED_GEN.cnt_i_reg[3]_0\(2), + A3 => '0', + CE => \^gen_enable_indet_btt.sig_coelsc_eop_reg\, + CLK => m_axi_s2mm_aclk, + D => \GEN_INDET_BTT.lsig_eop_reg_reg\(7), + Q => \^out\(7) + ); +\INFERRED_GEN.data_reg[5][15]_srl6\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[3]_0\(0), + A1 => \INFERRED_GEN.cnt_i_reg[3]_0\(1), + A2 => \INFERRED_GEN.cnt_i_reg[3]_0\(2), + A3 => '0', + CE => \^gen_enable_indet_btt.sig_coelsc_eop_reg\, + CLK => m_axi_s2mm_aclk, + D => \GEN_INDET_BTT.lsig_eop_reg_reg\(8), + Q => \^out\(8) + ); +\INFERRED_GEN.data_reg[5][16]_srl6\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[3]_0\(0), + A1 => \INFERRED_GEN.cnt_i_reg[3]_0\(1), + A2 => \INFERRED_GEN.cnt_i_reg[3]_0\(2), + A3 => '0', + CE => \^gen_enable_indet_btt.sig_coelsc_eop_reg\, + CLK => m_axi_s2mm_aclk, + D => \GEN_INDET_BTT.lsig_eop_reg_reg\(9), + Q => \^out\(9) + ); +\INFERRED_GEN.data_reg[5][17]_srl6\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[3]_0\(0), + A1 => \INFERRED_GEN.cnt_i_reg[3]_0\(1), + A2 => \INFERRED_GEN.cnt_i_reg[3]_0\(2), + A3 => '0', + CE => \^gen_enable_indet_btt.sig_coelsc_eop_reg\, + CLK => m_axi_s2mm_aclk, + D => \GEN_INDET_BTT.lsig_eop_reg_reg\(10), + Q => \^out\(10) + ); +\INFERRED_GEN.data_reg[5][18]_srl6\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[3]_0\(0), + A1 => \INFERRED_GEN.cnt_i_reg[3]_0\(1), + A2 => \INFERRED_GEN.cnt_i_reg[3]_0\(2), + A3 => '0', + CE => \^gen_enable_indet_btt.sig_coelsc_eop_reg\, + CLK => m_axi_s2mm_aclk, + D => \GEN_INDET_BTT.lsig_eop_reg_reg\(11), + Q => \^out\(11) + ); +\INFERRED_GEN.data_reg[5][19]_srl6\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[3]_0\(0), + A1 => \INFERRED_GEN.cnt_i_reg[3]_0\(1), + A2 => \INFERRED_GEN.cnt_i_reg[3]_0\(2), + A3 => '0', + CE => \^gen_enable_indet_btt.sig_coelsc_eop_reg\, + CLK => m_axi_s2mm_aclk, + D => \GEN_INDET_BTT.lsig_eop_reg_reg\(12), + Q => \^out\(12) + ); +\INFERRED_GEN.data_reg[5][20]_srl6\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[3]_0\(0), + A1 => \INFERRED_GEN.cnt_i_reg[3]_0\(1), + A2 => \INFERRED_GEN.cnt_i_reg[3]_0\(2), + A3 => '0', + CE => \^gen_enable_indet_btt.sig_coelsc_eop_reg\, + CLK => m_axi_s2mm_aclk, + D => \GEN_INDET_BTT.lsig_eop_reg_reg\(13), + Q => \^out\(13) + ); +\INFERRED_GEN.data_reg[5][21]_srl6\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[3]_0\(0), + A1 => \INFERRED_GEN.cnt_i_reg[3]_0\(1), + A2 => \INFERRED_GEN.cnt_i_reg[3]_0\(2), + A3 => '0', + CE => \^gen_enable_indet_btt.sig_coelsc_eop_reg\, + CLK => m_axi_s2mm_aclk, + D => \GEN_INDET_BTT.lsig_eop_reg_reg\(14), + Q => \^out\(14) + ); +\INFERRED_GEN.data_reg[5][22]_srl6\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[3]_0\(0), + A1 => \INFERRED_GEN.cnt_i_reg[3]_0\(1), + A2 => \INFERRED_GEN.cnt_i_reg[3]_0\(2), + A3 => '0', + CE => \^gen_enable_indet_btt.sig_coelsc_eop_reg\, + CLK => m_axi_s2mm_aclk, + D => \GEN_INDET_BTT.lsig_eop_reg_reg\(15), + Q => \^out\(15) + ); +\INFERRED_GEN.data_reg[5][4]_srl6\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[3]_0\(0), + A1 => \INFERRED_GEN.cnt_i_reg[3]_0\(1), + A2 => \INFERRED_GEN.cnt_i_reg[3]_0\(2), + A3 => '0', + CE => \^gen_enable_indet_btt.sig_coelsc_eop_reg\, + CLK => m_axi_s2mm_aclk, + D => \GEN_INDET_BTT.lsig_eop_reg_reg\(0), + Q => \^out\(0) + ); +\INFERRED_GEN.data_reg[5][4]_srl6_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"20" + ) + port map ( + I0 => sig_data2wsc_valid, + I1 => FIFO_Full_reg, + I2 => sig_inhibit_rdy_n, + O => \^gen_enable_indet_btt.sig_coelsc_eop_reg\ + ); +\INFERRED_GEN.data_reg[5][5]_srl6\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[3]_0\(0), + A1 => \INFERRED_GEN.cnt_i_reg[3]_0\(1), + A2 => \INFERRED_GEN.cnt_i_reg[3]_0\(2), + A3 => '0', + CE => \^gen_enable_indet_btt.sig_coelsc_eop_reg\, + CLK => m_axi_s2mm_aclk, + D => \GEN_INDET_BTT.lsig_eop_reg_reg\(1), + Q => \^out\(1) + ); +\INFERRED_GEN.data_reg[5][9]_srl6\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => \INFERRED_GEN.cnt_i_reg[3]_0\(0), + A1 => \INFERRED_GEN.cnt_i_reg[3]_0\(1), + A2 => \INFERRED_GEN.cnt_i_reg[3]_0\(2), + A3 => '0', + CE => \^gen_enable_indet_btt.sig_coelsc_eop_reg\, + CLK => m_axi_s2mm_aclk, + D => \GEN_INDET_BTT.lsig_eop_reg_reg\(2), + Q => \^out\(2) + ); +\sig_wdc_statcnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"DD2022DDDD2222DD" + ) + port map ( + I0 => \^gen_enable_indet_btt.sig_coelsc_eop_reg\, + I1 => \^sig_wdc_statcnt_reg[3]\, + I2 => Q(3), + I3 => Q(0), + I4 => Q(1), + I5 => Q(2), + O => D(0) + ); +\sig_wdc_statcnt[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"DF20F20D" + ) + port map ( + I0 => \^gen_enable_indet_btt.sig_coelsc_eop_reg\, + I1 => \^sig_wdc_statcnt_reg[3]\, + I2 => Q(0), + I3 => Q(2), + I4 => Q(1), + O => D(1) + ); +\sig_wdc_statcnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000FFFEFFDF0000" + ) + port map ( + I0 => Q(1), + I1 => Q(0), + I2 => Q(2), + I3 => Q(3), + I4 => \^gen_enable_indet_btt.sig_coelsc_eop_reg\, + I5 => \^sig_wdc_statcnt_reg[3]\, + O => E(0) + ); +\sig_wdc_statcnt[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"DFFF2000FFBA0045" + ) + port map ( + I0 => Q(0), + I1 => \^sig_wdc_statcnt_reg[3]\, + I2 => \^gen_enable_indet_btt.sig_coelsc_eop_reg\, + I3 => Q(1), + I4 => Q(3), + I5 => Q(2), + O => D(2) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized7\ is + port ( + \FSM_sequential_sig_cmdcntl_sm_state_reg[0]\ : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 20 downto 0 ); + sig_wr_fifo : out STD_LOGIC; + \GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg\ : out STD_LOGIC; + sig_sm_pop_cmd_fifo_ns : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); + p_9_out_0 : in STD_LOGIC; + FIFO_Full_reg : in STD_LOGIC; + sig_inhibit_rdy_n_reg : in STD_LOGIC; + lsig_cmd_fetch_pause : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_need_cmd_flush : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + \sig_good_tlast_dbeat37_out__0\ : in STD_LOGIC; + \FSM_sequential_sig_cmdcntl_sm_state_reg[0]_0\ : in STD_LOGIC; + p_7_out : in STD_LOGIC; + \FSM_sequential_sig_cmdcntl_sm_state_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \in\ : in STD_LOGIC_VECTOR ( 21 downto 0 ); + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized7\ : entity is "dynshreg_f"; +end \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized7\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized7\ is + signal \FSM_sequential_sig_cmdcntl_sm_state[1]_i_2_n_0\ : STD_LOGIC; + signal \^out\ : STD_LOGIC_VECTOR ( 20 downto 0 ); + signal sig_cmd_fifo_data_out : STD_LOGIC_VECTOR ( 24 to 24 ); + signal \^sig_wr_fifo\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_sig_cmdcntl_sm_state[0]_i_4\ : label is "soft_lutpair235"; + attribute SOFT_HLUTNM of \FSM_sequential_sig_cmdcntl_sm_state[1]_i_2\ : label is "soft_lutpair235"; + attribute srl_bus_name : string; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][10]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name : string; + attribute srl_name of \INFERRED_GEN.data_reg[3][10]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][10]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][11]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][11]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][11]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][12]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][12]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][12]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][13]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][13]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][13]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][14]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][14]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][14]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][15]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][15]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][15]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][16]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][16]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][16]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][17]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][17]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][17]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][18]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][18]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][18]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][19]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][19]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][19]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][20]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][20]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][20]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][21]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][21]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][21]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][23]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][23]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][23]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][24]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][24]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][24]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][25]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][25]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][25]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][26]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][26]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][26]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][27]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][27]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][27]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][28]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][28]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][28]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][6]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][6]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][6]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][7]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][7]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][7]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][8]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][8]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][8]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][9]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][9]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][9]_srl4 "; +begin + \out\(20 downto 0) <= \^out\(20 downto 0); + sig_wr_fifo <= \^sig_wr_fifo\; +\FSM_sequential_sig_cmdcntl_sm_state[0]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^out\(17), + I1 => Q(2), + O => \FSM_sequential_sig_cmdcntl_sm_state_reg[0]\ + ); +\FSM_sequential_sig_cmdcntl_sm_state[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00045504" + ) + port map ( + I0 => \FSM_sequential_sig_cmdcntl_sm_state_reg[2]\(2), + I1 => \FSM_sequential_sig_cmdcntl_sm_state_reg[2]\(1), + I2 => sig_cmd_fifo_data_out(24), + I3 => \FSM_sequential_sig_cmdcntl_sm_state_reg[2]\(0), + I4 => \FSM_sequential_sig_cmdcntl_sm_state[1]_i_2_n_0\, + O => D(0) + ); +\FSM_sequential_sig_cmdcntl_sm_state[1]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0FFB0AFB" + ) + port map ( + I0 => \^out\(17), + I1 => p_7_out, + I2 => Q(2), + I3 => \FSM_sequential_sig_cmdcntl_sm_state_reg[2]\(1), + I4 => sig_need_cmd_flush, + O => \FSM_sequential_sig_cmdcntl_sm_state[1]_i_2_n_0\ + ); +\GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000AAAE0000" + ) + port map ( + I0 => lsig_cmd_fetch_pause, + I1 => E(0), + I2 => sig_cmd_fifo_data_out(24), + I3 => sig_need_cmd_flush, + I4 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I5 => \sig_good_tlast_dbeat37_out__0\, + O => \GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg\ + ); +\INFERRED_GEN.data_reg[3][10]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(4), + Q => \^out\(4) + ); +\INFERRED_GEN.data_reg[3][11]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(5), + Q => \^out\(5) + ); +\INFERRED_GEN.data_reg[3][12]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(6), + Q => \^out\(6) + ); +\INFERRED_GEN.data_reg[3][13]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(7), + Q => \^out\(7) + ); +\INFERRED_GEN.data_reg[3][14]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(8), + Q => \^out\(8) + ); +\INFERRED_GEN.data_reg[3][15]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(9), + Q => \^out\(9) + ); +\INFERRED_GEN.data_reg[3][16]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(10), + Q => \^out\(10) + ); +\INFERRED_GEN.data_reg[3][17]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(11), + Q => \^out\(11) + ); +\INFERRED_GEN.data_reg[3][18]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(12), + Q => \^out\(12) + ); +\INFERRED_GEN.data_reg[3][19]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(13), + Q => \^out\(13) + ); +\INFERRED_GEN.data_reg[3][20]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(14), + Q => \^out\(14) + ); +\INFERRED_GEN.data_reg[3][21]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(15), + Q => \^out\(15) + ); +\INFERRED_GEN.data_reg[3][23]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(16), + Q => \^out\(16) + ); +\INFERRED_GEN.data_reg[3][24]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(17), + Q => sig_cmd_fifo_data_out(24) + ); +\INFERRED_GEN.data_reg[3][25]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(18), + Q => \^out\(17) + ); +\INFERRED_GEN.data_reg[3][26]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(19), + Q => \^out\(18) + ); +\INFERRED_GEN.data_reg[3][27]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(20), + Q => \^out\(19) + ); +\INFERRED_GEN.data_reg[3][28]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(21), + Q => \^out\(20) + ); +\INFERRED_GEN.data_reg[3][6]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(0), + Q => \^out\(0) + ); +\INFERRED_GEN.data_reg[3][6]_srl4_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"20" + ) + port map ( + I0 => p_9_out_0, + I1 => FIFO_Full_reg, + I2 => sig_inhibit_rdy_n_reg, + O => \^sig_wr_fifo\ + ); +\INFERRED_GEN.data_reg[3][7]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(1), + Q => \^out\(1) + ); +\INFERRED_GEN.data_reg[3][8]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(2), + Q => \^out\(2) + ); +\INFERRED_GEN.data_reg[3][9]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(3), + Q => \^out\(3) + ); +sig_sm_pop_cmd_fifo_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0202020002000200" + ) + port map ( + I0 => \FSM_sequential_sig_cmdcntl_sm_state_reg[0]_0\, + I1 => \^out\(17), + I2 => Q(2), + I3 => p_7_out, + I4 => \FSM_sequential_sig_cmdcntl_sm_state_reg[2]\(1), + I5 => sig_need_cmd_flush, + O => sig_sm_pop_cmd_fifo_ns + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized8\ is + port ( + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0\ : in STD_LOGIC; + sig_m_valid_out_reg : in STD_LOGIC; + sig_strm_tlast : in STD_LOGIC; + sig_eop_halt_xfer : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0\ : in STD_LOGIC; + p_0_in : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0\ : in STD_LOGIC; + sel : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized8\ : entity is "dynshreg_f"; +end \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized8\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized8\ is + signal \^out\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute srl_bus_name : string; + attribute srl_bus_name of \INFERRED_GEN.data_reg[15][2]_srl16\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] "; + attribute srl_name : string; + attribute srl_name of \INFERRED_GEN.data_reg[15][2]_srl16\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][2]_srl16 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[15][3]_srl16\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] "; + attribute srl_name of \INFERRED_GEN.data_reg[15][3]_srl16\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][3]_srl16 "; +begin + \out\(1 downto 0) <= \^out\(1 downto 0); +\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg[0][1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000000A080" + ) + port map ( + I0 => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0\, + I1 => \^out\(1), + I2 => sig_m_valid_out_reg, + I3 => sig_strm_tlast, + I4 => sig_eop_halt_xfer, + I5 => Q(4), + O => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1]\(0) + ); +\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg[1][1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000000A080" + ) + port map ( + I0 => p_0_in, + I1 => \^out\(1), + I2 => sig_m_valid_out_reg, + I3 => sig_strm_tlast, + I4 => sig_eop_halt_xfer, + I5 => Q(4), + O => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1]\(0) + ); +\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg[2][1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000000A080" + ) + port map ( + I0 => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0\, + I1 => \^out\(1), + I2 => sig_m_valid_out_reg, + I3 => sig_strm_tlast, + I4 => sig_eop_halt_xfer, + I5 => Q(4), + O => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1]\(0) + ); +\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg[3][1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000000A080" + ) + port map ( + I0 => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0\, + I1 => \^out\(1), + I2 => sig_m_valid_out_reg, + I3 => sig_strm_tlast, + I4 => sig_eop_halt_xfer, + I5 => Q(4), + O => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1]\(0) + ); +\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg[4][1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000000A080" + ) + port map ( + I0 => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0\, + I1 => \^out\(1), + I2 => sig_m_valid_out_reg, + I3 => sig_strm_tlast, + I4 => sig_eop_halt_xfer, + I5 => Q(4), + O => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1]\(0) + ); +\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg[5][1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000000A080" + ) + port map ( + I0 => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0\, + I1 => \^out\(1), + I2 => sig_m_valid_out_reg, + I3 => sig_strm_tlast, + I4 => sig_eop_halt_xfer, + I5 => Q(4), + O => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1]\(0) + ); +\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg[6][1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000000A080" + ) + port map ( + I0 => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0\, + I1 => \^out\(1), + I2 => sig_m_valid_out_reg, + I3 => sig_strm_tlast, + I4 => sig_eop_halt_xfer, + I5 => Q(4), + O => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1]\(0) + ); +\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg[7][1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000000A080" + ) + port map ( + I0 => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0\, + I1 => \^out\(1), + I2 => sig_m_valid_out_reg, + I3 => sig_strm_tlast, + I4 => sig_eop_halt_xfer, + I5 => Q(4), + O => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1]\(0) + ); +\INFERRED_GEN.data_reg[15][2]_srl16\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => Q(2), + A3 => Q(3), + CE => sel, + CLK => m_axi_s2mm_aclk, + D => \in\(0), + Q => \^out\(0) + ); +\INFERRED_GEN.data_reg[15][3]_srl16\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => Q(2), + A3 => Q(3), + CE => sel, + CLK => m_axi_s2mm_aclk, + D => \in\(1), + Q => \^out\(1) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized9\ is + port ( + p_0_in : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 41 downto 0 ); + sig_wr_fifo : out STD_LOGIC; + p_22_out : in STD_LOGIC; + FIFO_Full_reg : in STD_LOGIC; + sig_inhibit_rdy_n_reg : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 39 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized9\ : entity is "dynshreg_f"; +end \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized9\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized9\ is + signal \^out\ : STD_LOGIC_VECTOR ( 41 downto 0 ); + signal \^sig_wr_fifo\ : STD_LOGIC; + attribute srl_bus_name : string; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][10]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name : string; + attribute srl_name of \INFERRED_GEN.data_reg[3][10]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][10]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][11]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][11]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][11]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][12]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][12]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][12]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][13]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][13]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][13]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][14]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][14]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][14]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][15]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][15]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][15]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][16]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][16]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][16]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][17]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][17]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][17]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][18]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][18]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][18]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][19]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][19]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][19]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][20]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][20]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][20]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][21]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][21]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][21]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][22]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][22]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][22]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][23]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][23]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][23]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][24]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][24]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][24]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][25]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][25]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][25]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][26]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][26]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][26]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][27]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][27]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][27]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][28]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][28]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][28]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][29]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][29]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][29]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][30]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][30]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][30]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][31]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][31]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][31]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][32]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][32]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][32]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][33]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][33]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][33]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][34]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][34]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][34]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][35]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][35]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][35]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][36]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][36]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][36]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][37]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][37]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][37]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][38]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][38]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][38]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][39]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][39]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][39]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][40]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][40]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][40]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][41]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][41]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][41]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][44]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][44]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][44]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][45]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][45]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][45]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][47]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][47]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][47]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][4]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][4]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][4]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][50]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][50]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][50]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][5]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][5]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][5]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][6]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][6]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][6]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][7]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][7]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][7]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][8]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][8]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][8]_srl4 "; + attribute srl_bus_name of \INFERRED_GEN.data_reg[3][9]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3] "; + attribute srl_name of \INFERRED_GEN.data_reg[3][9]_srl4\ : label is "U0/\I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][9]_srl4 "; +begin + \out\(41 downto 0) <= \^out\(41 downto 0); + sig_wr_fifo <= \^sig_wr_fifo\; +\INFERRED_GEN.data_reg[3][10]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(6), + Q => \^out\(6) + ); +\INFERRED_GEN.data_reg[3][11]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(7), + Q => \^out\(7) + ); +\INFERRED_GEN.data_reg[3][12]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(8), + Q => \^out\(8) + ); +\INFERRED_GEN.data_reg[3][13]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(9), + Q => \^out\(9) + ); +\INFERRED_GEN.data_reg[3][14]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(10), + Q => \^out\(10) + ); +\INFERRED_GEN.data_reg[3][15]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(11), + Q => \^out\(11) + ); +\INFERRED_GEN.data_reg[3][16]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(12), + Q => \^out\(12) + ); +\INFERRED_GEN.data_reg[3][17]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(13), + Q => \^out\(13) + ); +\INFERRED_GEN.data_reg[3][18]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(14), + Q => \^out\(14) + ); +\INFERRED_GEN.data_reg[3][19]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(15), + Q => \^out\(15) + ); +\INFERRED_GEN.data_reg[3][20]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(16), + Q => \^out\(16) + ); +\INFERRED_GEN.data_reg[3][21]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(17), + Q => \^out\(17) + ); +\INFERRED_GEN.data_reg[3][22]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(18), + Q => \^out\(18) + ); +\INFERRED_GEN.data_reg[3][23]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(19), + Q => \^out\(19) + ); +\INFERRED_GEN.data_reg[3][24]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(20), + Q => \^out\(20) + ); +\INFERRED_GEN.data_reg[3][25]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(21), + Q => \^out\(21) + ); +\INFERRED_GEN.data_reg[3][26]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(22), + Q => \^out\(22) + ); +\INFERRED_GEN.data_reg[3][27]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(23), + Q => \^out\(23) + ); +\INFERRED_GEN.data_reg[3][28]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(24), + Q => \^out\(24) + ); +\INFERRED_GEN.data_reg[3][29]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(25), + Q => \^out\(25) + ); +\INFERRED_GEN.data_reg[3][30]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(26), + Q => \^out\(26) + ); +\INFERRED_GEN.data_reg[3][31]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(27), + Q => \^out\(27) + ); +\INFERRED_GEN.data_reg[3][32]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(28), + Q => \^out\(28) + ); +\INFERRED_GEN.data_reg[3][33]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(29), + Q => \^out\(29) + ); +\INFERRED_GEN.data_reg[3][34]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(30), + Q => \^out\(30) + ); +\INFERRED_GEN.data_reg[3][35]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(31), + Q => \^out\(31) + ); +\INFERRED_GEN.data_reg[3][36]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(32), + Q => \^out\(32) + ); +\INFERRED_GEN.data_reg[3][37]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(33), + Q => \^out\(33) + ); +\INFERRED_GEN.data_reg[3][38]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(34), + Q => \^out\(34) + ); +\INFERRED_GEN.data_reg[3][39]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(35), + Q => \^out\(35) + ); +\INFERRED_GEN.data_reg[3][40]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(36), + Q => \^out\(36) + ); +\INFERRED_GEN.data_reg[3][41]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(37), + Q => \^out\(37) + ); +\INFERRED_GEN.data_reg[3][44]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => '1', + Q => \^out\(38) + ); +\INFERRED_GEN.data_reg[3][45]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => '1', + Q => \^out\(39) + ); +\INFERRED_GEN.data_reg[3][47]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(38), + Q => \^out\(40) + ); +\INFERRED_GEN.data_reg[3][4]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(0), + Q => \^out\(0) + ); +\INFERRED_GEN.data_reg[3][4]_srl4_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"20" + ) + port map ( + I0 => p_22_out, + I1 => FIFO_Full_reg, + I2 => sig_inhibit_rdy_n_reg, + O => \^sig_wr_fifo\ + ); +\INFERRED_GEN.data_reg[3][50]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(39), + Q => \^out\(41) + ); +\INFERRED_GEN.data_reg[3][5]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(1), + Q => \^out\(1) + ); +\INFERRED_GEN.data_reg[3][6]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(2), + Q => \^out\(2) + ); +\INFERRED_GEN.data_reg[3][7]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(3), + Q => \^out\(3) + ); +\INFERRED_GEN.data_reg[3][8]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(4), + Q => \^out\(4) + ); +\INFERRED_GEN.data_reg[3][9]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => Q(0), + A1 => Q(1), + A2 => '0', + A3 => '0', + CE => \^sig_wr_fifo\, + CLK => m_axi_s2mm_aclk, + D => \in\(5), + Q => \^out\(5) + ); +\sig_addr_valid_reg_i_1__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^out\(41), + O => p_0_in + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_wrapper is + port ( + DOBDO : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : out STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[2]\ : out STD_LOGIC; + DIN : out STD_LOGIC_VECTOR ( 0 to 0 ); + dm2linebuf_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gc1.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \gcc0.gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + lsig_cmd_loaded : in STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ : in STD_LOGIC; + hold_ff_q : in STD_LOGIC; + \out\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper"; +end Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_wrapper; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_wrapper is + signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_53\ : STD_LOGIC; + signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85\ : STD_LOGIC; + signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87\ : STD_LOGIC; + signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89\ : STD_LOGIC; + signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90\ : STD_LOGIC; + signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91\ : STD_LOGIC; + signal \^dobdo\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal sig_data_fifo_data_out : STD_LOGIC_VECTOR ( 64 downto 0 ); + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + attribute CLOCK_DOMAINS : string; + attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : label is "COMMON"; + attribute box_type : string; + attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : label is "PRIMITIVE"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \INCLUDE_UNPACKING.lsig_cmd_loaded_i_1\ : label is "soft_lutpair108"; + attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[2]_i_2__0\ : label is "soft_lutpair108"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_10\ : label is "soft_lutpair113"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_10__0\ : label is "soft_lutpair120"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_11\ : label is "soft_lutpair113"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_11__0\ : label is "soft_lutpair120"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_12\ : label is "soft_lutpair114"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_12__0\ : label is "soft_lutpair121"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_13\ : label is "soft_lutpair114"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_13__0\ : label is "soft_lutpair121"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_14\ : label is "soft_lutpair115"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_14__0\ : label is "soft_lutpair122"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_15\ : label is "soft_lutpair115"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_15__0\ : label is "soft_lutpair122"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_16\ : label is "soft_lutpair123"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_17\ : label is "soft_lutpair123"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_18\ : label is "soft_lutpair124"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_19\ : label is "soft_lutpair124"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_2\ : label is "soft_lutpair109"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_20\ : label is "soft_lutpair116"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_21\ : label is "soft_lutpair116"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_3\ : label is "soft_lutpair109"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_4\ : label is "soft_lutpair110"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_4__0\ : label is "soft_lutpair117"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_5\ : label is "soft_lutpair110"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_5__0\ : label is "soft_lutpair117"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_6\ : label is "soft_lutpair111"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_6__0\ : label is "soft_lutpair118"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_7\ : label is "soft_lutpair111"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_7__0\ : label is "soft_lutpair118"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_8\ : label is "soft_lutpair112"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_8__0\ : label is "soft_lutpair119"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_9\ : label is "soft_lutpair112"; + attribute SOFT_HLUTNM of \gf36e1_inst.sngfifo36e1_i_9__0\ : label is "soft_lutpair119"; +begin + DOBDO(0) <= \^dobdo\(0); +\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\: unisim.vcomponents.RAMB36E1 + generic map( + DOA_REG => 1, + DOB_REG => 1, + EN_ECC_READ => false, + EN_ECC_WRITE => false, + INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_A => X"000000000", + INIT_B => X"000000000", + INIT_FILE => "NONE", + IS_CLKARDCLK_INVERTED => '0', + IS_CLKBWRCLK_INVERTED => '0', + IS_ENARDEN_INVERTED => '0', + IS_ENBWREN_INVERTED => '0', + IS_RSTRAMARSTRAM_INVERTED => '0', + IS_RSTRAMB_INVERTED => '0', + IS_RSTREGARSTREG_INVERTED => '0', + IS_RSTREGB_INVERTED => '0', + RAM_EXTENSION_A => "NONE", + RAM_EXTENSION_B => "NONE", + RAM_MODE => "SDP", + RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", + READ_WIDTH_A => 72, + READ_WIDTH_B => 0, + RSTREG_PRIORITY_A => "REGCE", + RSTREG_PRIORITY_B => "REGCE", + SIM_COLLISION_CHECK => "ALL", + SIM_DEVICE => "7SERIES", + SRVAL_A => X"000000000", + SRVAL_B => X"000000000", + WRITE_MODE_A => "READ_FIRST", + WRITE_MODE_B => "READ_FIRST", + WRITE_WIDTH_A => 0, + WRITE_WIDTH_B => 72 + ) + port map ( + ADDRARDADDR(15 downto 14) => B"10", + ADDRARDADDR(13 downto 6) => \gc1.count_d2_reg[7]\(7 downto 0), + ADDRARDADDR(5 downto 0) => B"111111", + ADDRBWRADDR(15 downto 14) => B"10", + ADDRBWRADDR(13 downto 6) => \gcc0.gc0.count_d1_reg[7]\(7 downto 0), + ADDRBWRADDR(5 downto 0) => B"111111", + CASCADEINA => '0', + CASCADEINB => '0', + CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED\, + CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED\, + CLKARDCLK => m_axi_mm2s_aclk, + CLKBWRCLK => m_axi_mm2s_aclk, + DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED\, + DIADI(31 downto 24) => m_axi_mm2s_rdata(33 downto 26), + DIADI(23 downto 8) => m_axi_mm2s_rdata(24 downto 9), + DIADI(7 downto 0) => m_axi_mm2s_rdata(7 downto 0), + DIBDI(31) => '0', + DIBDI(30 downto 29) => DIBDI(1 downto 0), + DIBDI(28 downto 8) => m_axi_mm2s_rdata(63 downto 43), + DIBDI(7 downto 0) => m_axi_mm2s_rdata(41 downto 34), + DIPADIP(3) => '0', + DIPADIP(2) => m_axi_mm2s_rdata(25), + DIPADIP(1) => '0', + DIPADIP(0) => m_axi_mm2s_rdata(8), + DIPBDIP(3 downto 1) => B"000", + DIPBDIP(0) => m_axi_mm2s_rdata(42), + DOADO(31 downto 24) => sig_data_fifo_data_out(33 downto 26), + DOADO(23 downto 8) => sig_data_fifo_data_out(24 downto 9), + DOADO(7 downto 0) => sig_data_fifo_data_out(7 downto 0), + DOBDO(31) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_53\, + DOBDO(30) => \^dobdo\(0), + DOBDO(29 downto 8) => sig_data_fifo_data_out(64 downto 43), + DOBDO(7 downto 0) => sig_data_fifo_data_out(41 downto 34), + DOPADOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85\, + DOPADOP(2) => sig_data_fifo_data_out(25), + DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87\, + DOPADOP(0) => sig_data_fifo_data_out(8), + DOPBDOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89\, + DOPBDOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90\, + DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91\, + DOPBDOP(0) => sig_data_fifo_data_out(42), + ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED\(7 downto 0), + ENARDEN => \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\, + ENBWREN => E(0), + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED\(8 downto 0), + REGCEAREGCE => \gpregsm1.curr_fwft_state_reg[0]\, + REGCEB => '0', + RSTRAMARSTRAM => '0', + RSTRAMB => '0', + RSTREGARSTREG => SR(0), + RSTREGB => '0', + SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED\, + WEA(3 downto 0) => B"0000", + WEBWE(7) => E(0), + WEBWE(6) => E(0), + WEBWE(5) => E(0), + WEBWE(4) => E(0), + WEBWE(3) => E(0), + WEBWE(2) => E(0), + WEBWE(1) => E(0), + WEBWE(0) => E(0) + ); +\INCLUDE_UNPACKING.lsig_cmd_loaded_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BF0F" + ) + port map ( + I0 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, + I1 => \^dobdo\(0), + I2 => Q(0), + I3 => lsig_cmd_loaded, + O => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ + ); +\INFERRED_GEN.cnt_i[2]_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8A" + ) + port map ( + I0 => lsig_cmd_loaded, + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, + I2 => \^dobdo\(0), + O => \INFERRED_GEN.cnt_i_reg[2]\ + ); +\gf36e1_inst.sngfifo36e1_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88800000" + ) + port map ( + I0 => sig_data_fifo_data_out(64), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => hold_ff_q, + I3 => \out\, + I4 => lsig_cmd_loaded, + O => DIN(0) + ); +\gf36e1_inst.sngfifo36e1_i_10\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(55), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(23), + O => dm2linebuf_mm2s_tdata(23) + ); +\gf36e1_inst.sngfifo36e1_i_10__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(41), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(9), + O => dm2linebuf_mm2s_tdata(9) + ); +\gf36e1_inst.sngfifo36e1_i_11\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(54), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(22), + O => dm2linebuf_mm2s_tdata(22) + ); +\gf36e1_inst.sngfifo36e1_i_11__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(40), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(8), + O => dm2linebuf_mm2s_tdata(8) + ); +\gf36e1_inst.sngfifo36e1_i_12\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(53), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(21), + O => dm2linebuf_mm2s_tdata(21) + ); +\gf36e1_inst.sngfifo36e1_i_12__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(39), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(7), + O => dm2linebuf_mm2s_tdata(7) + ); +\gf36e1_inst.sngfifo36e1_i_13\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(52), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(20), + O => dm2linebuf_mm2s_tdata(20) + ); +\gf36e1_inst.sngfifo36e1_i_13__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(38), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(6), + O => dm2linebuf_mm2s_tdata(6) + ); +\gf36e1_inst.sngfifo36e1_i_14\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(51), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(19), + O => dm2linebuf_mm2s_tdata(19) + ); +\gf36e1_inst.sngfifo36e1_i_14__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(37), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(5), + O => dm2linebuf_mm2s_tdata(5) + ); +\gf36e1_inst.sngfifo36e1_i_15\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(50), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(18), + O => dm2linebuf_mm2s_tdata(18) + ); +\gf36e1_inst.sngfifo36e1_i_15__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(36), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(4), + O => dm2linebuf_mm2s_tdata(4) + ); +\gf36e1_inst.sngfifo36e1_i_16\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(35), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(3), + O => dm2linebuf_mm2s_tdata(3) + ); +\gf36e1_inst.sngfifo36e1_i_17\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(34), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(2), + O => dm2linebuf_mm2s_tdata(2) + ); +\gf36e1_inst.sngfifo36e1_i_18\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(33), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(1), + O => dm2linebuf_mm2s_tdata(1) + ); +\gf36e1_inst.sngfifo36e1_i_19\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(32), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(0), + O => dm2linebuf_mm2s_tdata(0) + ); +\gf36e1_inst.sngfifo36e1_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(63), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(31), + O => dm2linebuf_mm2s_tdata(31) + ); +\gf36e1_inst.sngfifo36e1_i_20\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(49), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(17), + O => dm2linebuf_mm2s_tdata(17) + ); +\gf36e1_inst.sngfifo36e1_i_21\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(48), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(16), + O => dm2linebuf_mm2s_tdata(16) + ); +\gf36e1_inst.sngfifo36e1_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(62), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(30), + O => dm2linebuf_mm2s_tdata(30) + ); +\gf36e1_inst.sngfifo36e1_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(61), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(29), + O => dm2linebuf_mm2s_tdata(29) + ); +\gf36e1_inst.sngfifo36e1_i_4__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(47), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(15), + O => dm2linebuf_mm2s_tdata(15) + ); +\gf36e1_inst.sngfifo36e1_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(60), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(28), + O => dm2linebuf_mm2s_tdata(28) + ); +\gf36e1_inst.sngfifo36e1_i_5__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(46), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(14), + O => dm2linebuf_mm2s_tdata(14) + ); +\gf36e1_inst.sngfifo36e1_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(59), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(27), + O => dm2linebuf_mm2s_tdata(27) + ); +\gf36e1_inst.sngfifo36e1_i_6__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(45), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(13), + O => dm2linebuf_mm2s_tdata(13) + ); +\gf36e1_inst.sngfifo36e1_i_7\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(58), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(26), + O => dm2linebuf_mm2s_tdata(26) + ); +\gf36e1_inst.sngfifo36e1_i_7__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(44), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(12), + O => dm2linebuf_mm2s_tdata(12) + ); +\gf36e1_inst.sngfifo36e1_i_8\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(57), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(25), + O => dm2linebuf_mm2s_tdata(25) + ); +\gf36e1_inst.sngfifo36e1_i_8__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(43), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(11), + O => dm2linebuf_mm2s_tdata(11) + ); +\gf36e1_inst.sngfifo36e1_i_9\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(56), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(24), + O => dm2linebuf_mm2s_tdata(24) + ); +\gf36e1_inst.sngfifo36e1_i_9__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => sig_data_fifo_data_out(42), + I1 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + I2 => sig_data_fifo_data_out(10), + O => dm2linebuf_mm2s_tdata(10) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_wrapper__parameterized0\ is + port ( + sig_data_fifo_data_out : out STD_LOGIC_VECTOR ( 65 downto 0 ); + m_axi_s2mm_aclk : in STD_LOGIC; + ram_empty_fb_i_reg : in STD_LOGIC; + WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_s_ready_out_reg : in STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + \gc1.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 7 downto 0 ); + lsig_combined_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); + DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper"; +end \Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_wrapper__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_wrapper__parameterized0\ is + signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85\ : STD_LOGIC; + signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_86\ : STD_LOGIC; + signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87\ : STD_LOGIC; + signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89\ : STD_LOGIC; + signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90\ : STD_LOGIC; + signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91\ : STD_LOGIC; + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + attribute CLOCK_DOMAINS : string; + attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : label is "COMMON"; + attribute box_type : string; + attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : label is "PRIMITIVE"; +begin +\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\: unisim.vcomponents.RAMB36E1 + generic map( + DOA_REG => 1, + DOB_REG => 1, + EN_ECC_READ => false, + EN_ECC_WRITE => false, + INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_A => X"000000000", + INIT_B => X"000000000", + INIT_FILE => "NONE", + IS_CLKARDCLK_INVERTED => '0', + IS_CLKBWRCLK_INVERTED => '0', + IS_ENARDEN_INVERTED => '0', + IS_ENBWREN_INVERTED => '0', + IS_RSTRAMARSTRAM_INVERTED => '0', + IS_RSTRAMB_INVERTED => '0', + IS_RSTREGARSTREG_INVERTED => '0', + IS_RSTREGB_INVERTED => '0', + RAM_EXTENSION_A => "NONE", + RAM_EXTENSION_B => "NONE", + RAM_MODE => "SDP", + RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", + READ_WIDTH_A => 72, + READ_WIDTH_B => 0, + RSTREG_PRIORITY_A => "REGCE", + RSTREG_PRIORITY_B => "REGCE", + SIM_COLLISION_CHECK => "ALL", + SIM_DEVICE => "7SERIES", + SRVAL_A => X"000000000", + SRVAL_B => X"000000000", + WRITE_MODE_A => "READ_FIRST", + WRITE_MODE_B => "READ_FIRST", + WRITE_WIDTH_A => 0, + WRITE_WIDTH_B => 72 + ) + port map ( + ADDRARDADDR(15 downto 14) => B"10", + ADDRARDADDR(13 downto 6) => \gc1.count_d2_reg[7]\(7 downto 0), + ADDRARDADDR(5 downto 0) => B"111111", + ADDRBWRADDR(15 downto 14) => B"10", + ADDRBWRADDR(13 downto 6) => Q(7 downto 0), + ADDRBWRADDR(5 downto 0) => B"111111", + CASCADEINA => '0', + CASCADEINB => '0', + CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED\, + CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED\, + CLKARDCLK => m_axi_s2mm_aclk, + CLKBWRCLK => m_axi_s2mm_aclk, + DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED\, + DIADI(31 downto 8) => lsig_combined_data(32 downto 9), + DIADI(7 downto 0) => lsig_combined_data(7 downto 0), + DIBDI(31 downto 30) => DIBDI(1 downto 0), + DIBDI(29 downto 8) => lsig_combined_data(63 downto 42), + DIBDI(7 downto 0) => lsig_combined_data(40 downto 33), + DIPADIP(3 downto 1) => B"000", + DIPADIP(0) => lsig_combined_data(8), + DIPBDIP(3 downto 1) => B"000", + DIPBDIP(0) => lsig_combined_data(41), + DOADO(31 downto 8) => sig_data_fifo_data_out(32 downto 9), + DOADO(7 downto 0) => sig_data_fifo_data_out(7 downto 0), + DOBDO(31 downto 8) => sig_data_fifo_data_out(65 downto 42), + DOBDO(7 downto 0) => sig_data_fifo_data_out(40 downto 33), + DOPADOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85\, + DOPADOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_86\, + DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87\, + DOPADOP(0) => sig_data_fifo_data_out(8), + DOPBDOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89\, + DOPBDOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90\, + DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91\, + DOPBDOP(0) => sig_data_fifo_data_out(41), + ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED\(7 downto 0), + ENARDEN => ram_empty_fb_i_reg, + ENBWREN => WEBWE(0), + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED\(8 downto 0), + REGCEAREGCE => sig_s_ready_out_reg, + REGCEB => '0', + RSTRAMARSTRAM => '0', + RSTRAMB => '0', + RSTREGARSTREG => sig_stream_rst, + RSTREGB => '0', + SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED\, + WEA(3 downto 0) => B"0000", + WEBWE(7) => WEBWE(0), + WEBWE(6) => WEBWE(0), + WEBWE(5) => WEBWE(0), + WEBWE(4) => WEBWE(0), + WEBWE(3) => WEBWE(0), + WEBWE(2) => WEBWE(0), + WEBWE(1) => WEBWE(0), + WEBWE(0) => WEBWE(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6 is + port ( + EMPTY : out STD_LOGIC; + FULL : out STD_LOGIC; + fifo_dout : out STD_LOGIC_VECTOR ( 15 downto 0 ); + RD_EN : out STD_LOGIC; + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\ : out STD_LOGIC; + m_axis_mm2s_aclk : in STD_LOGIC; + RST : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + WR_EN : in STD_LOGIC; + DIN : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \out\ : in STD_LOGIC; + sig_s_ready_out_reg : in STD_LOGIC; + lsig_0ffset_cntr : in STD_LOGIC; + sig_s_ready_out_reg_0 : in STD_LOGIC; + mm2s_prmry_resetn : in STD_LOGIC; + mm2s_halt : in STD_LOGIC; + p_24_out : in STD_LOGIC; + hold_ff_q_reg : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6 : entity is "builtin_prim_v6"; +end Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6 is + signal \^empty\ : STD_LOGIC; + signal \^full\ : STD_LOGIC; + signal \^gen_linebuf_no_sof.gen_linebuffer.gen_sof.sof_flag_reg\ : STD_LOGIC; + signal \^rd_en\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_0\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_1\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_10\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_112\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_113\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_14\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_15\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_18\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_19\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_20\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_21\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_22\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_23\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_24\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_25\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_26\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_27\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_28\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_31\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_32\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_33\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_34\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_35\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_36\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_37\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_38\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_39\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_40\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_41\ : STD_LOGIC; + signal p_3_out : STD_LOGIC; + signal \NLW_gf36e1_inst.sngfifo36e1_DO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 16 ); + signal \NLW_gf36e1_inst.sngfifo36e1_DOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal \NLW_gf36e1_inst.sngfifo36e1_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \NLW_gf36e1_inst.sngfifo36e1_RDCOUNT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 12 downto 11 ); + signal \NLW_gf36e1_inst.sngfifo36e1_WRCOUNT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 12 downto 11 ); + attribute CLOCK_DOMAINS : string; + attribute CLOCK_DOMAINS of \gf36e1_inst.sngfifo36e1\ : label is "INDEPENDENT"; + attribute box_type : string; + attribute box_type of \gf36e1_inst.sngfifo36e1\ : label is "PRIMITIVE"; +begin + EMPTY <= \^empty\; + FULL <= \^full\; + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ <= \^gen_linebuf_no_sof.gen_linebuffer.gen_sof.sof_flag_reg\; + RD_EN <= \^rd_en\; +\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_9\: unisim.vcomponents.LUT2 + generic map( + INIT => X"7" + ) + port map ( + I0 => \^gen_linebuf_no_sof.gen_linebuffer.gen_sof.sof_flag_reg\, + I1 => lsig_0ffset_cntr, + O => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ + ); +\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000E00" + ) + port map ( + I0 => DIN(15), + I1 => p_24_out, + I2 => mm2s_halt, + I3 => mm2s_prmry_resetn, + I4 => \^gen_linebuf_no_sof.gen_linebuffer.gen_sof.sof_flag_reg\, + O => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\ + ); +\INCLUDE_UNPACKING.lsig_0ffset_cntr[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000010" + ) + port map ( + I0 => \^full\, + I1 => sig_s_ready_out_reg_0, + I2 => mm2s_prmry_resetn, + I3 => mm2s_halt, + I4 => p_24_out, + I5 => hold_ff_q_reg, + O => \^gen_linebuf_no_sof.gen_linebuffer.gen_sof.sof_flag_reg\ + ); +\gf36e1_inst.sngfifo36e1\: unisim.vcomponents.FIFO36E1 + generic map( + ALMOST_EMPTY_OFFSET => X"000A", + ALMOST_FULL_OFFSET => X"0097", + DATA_WIDTH => 18, + DO_REG => 1, + EN_ECC_READ => false, + EN_ECC_WRITE => false, + EN_SYN => false, + FIFO_MODE => "FIFO36", + FIRST_WORD_FALL_THROUGH => true, + INIT => X"000000000000000000", + IS_RDCLK_INVERTED => '0', + IS_RDEN_INVERTED => '0', + IS_RSTREG_INVERTED => '0', + IS_RST_INVERTED => '0', + IS_WRCLK_INVERTED => '0', + IS_WREN_INVERTED => '0', + SIM_DEVICE => "7SERIES", + SRVAL => X"000000000000000000" + ) + port map ( + ALMOSTEMPTY => \gf36e1_inst.sngfifo36e1_n_10\, + ALMOSTFULL => p_3_out, + DBITERR => \gf36e1_inst.sngfifo36e1_n_0\, + DI(63 downto 16) => B"000000000000000000000000000000000000000000000000", + DI(15 downto 0) => DIN(15 downto 0), + DIP(7 downto 0) => B"00000000", + DO(63 downto 16) => \NLW_gf36e1_inst.sngfifo36e1_DO_UNCONNECTED\(63 downto 16), + DO(15 downto 0) => fifo_dout(15 downto 0), + DOP(7 downto 2) => \NLW_gf36e1_inst.sngfifo36e1_DOP_UNCONNECTED\(7 downto 2), + DOP(1) => \gf36e1_inst.sngfifo36e1_n_112\, + DOP(0) => \gf36e1_inst.sngfifo36e1_n_113\, + ECCPARITY(7 downto 0) => \NLW_gf36e1_inst.sngfifo36e1_ECCPARITY_UNCONNECTED\(7 downto 0), + EMPTY => \^empty\, + FULL => \^full\, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RDCLK => m_axis_mm2s_aclk, + RDCOUNT(12 downto 11) => \NLW_gf36e1_inst.sngfifo36e1_RDCOUNT_UNCONNECTED\(12 downto 11), + RDCOUNT(10) => \gf36e1_inst.sngfifo36e1_n_18\, + RDCOUNT(9) => \gf36e1_inst.sngfifo36e1_n_19\, + RDCOUNT(8) => \gf36e1_inst.sngfifo36e1_n_20\, + RDCOUNT(7) => \gf36e1_inst.sngfifo36e1_n_21\, + RDCOUNT(6) => \gf36e1_inst.sngfifo36e1_n_22\, + RDCOUNT(5) => \gf36e1_inst.sngfifo36e1_n_23\, + RDCOUNT(4) => \gf36e1_inst.sngfifo36e1_n_24\, + RDCOUNT(3) => \gf36e1_inst.sngfifo36e1_n_25\, + RDCOUNT(2) => \gf36e1_inst.sngfifo36e1_n_26\, + RDCOUNT(1) => \gf36e1_inst.sngfifo36e1_n_27\, + RDCOUNT(0) => \gf36e1_inst.sngfifo36e1_n_28\, + RDEN => \^rd_en\, + RDERR => \gf36e1_inst.sngfifo36e1_n_14\, + REGCE => '0', + RST => RST, + RSTREG => '0', + SBITERR => \gf36e1_inst.sngfifo36e1_n_1\, + WRCLK => m_axi_mm2s_aclk, + WRCOUNT(12 downto 11) => \NLW_gf36e1_inst.sngfifo36e1_WRCOUNT_UNCONNECTED\(12 downto 11), + WRCOUNT(10) => \gf36e1_inst.sngfifo36e1_n_31\, + WRCOUNT(9) => \gf36e1_inst.sngfifo36e1_n_32\, + WRCOUNT(8) => \gf36e1_inst.sngfifo36e1_n_33\, + WRCOUNT(7) => \gf36e1_inst.sngfifo36e1_n_34\, + WRCOUNT(6) => \gf36e1_inst.sngfifo36e1_n_35\, + WRCOUNT(5) => \gf36e1_inst.sngfifo36e1_n_36\, + WRCOUNT(4) => \gf36e1_inst.sngfifo36e1_n_37\, + WRCOUNT(3) => \gf36e1_inst.sngfifo36e1_n_38\, + WRCOUNT(2) => \gf36e1_inst.sngfifo36e1_n_39\, + WRCOUNT(1) => \gf36e1_inst.sngfifo36e1_n_40\, + WRCOUNT(0) => \gf36e1_inst.sngfifo36e1_n_41\, + WREN => WR_EN, + WRERR => \gf36e1_inst.sngfifo36e1_n_15\ + ); +\gf36e1_inst.sngfifo36e1_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"02" + ) + port map ( + I0 => \out\, + I1 => \^empty\, + I2 => sig_s_ready_out_reg, + O => \^rd_en\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_41 is + port ( + EMPTY : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ : out STD_LOGIC; + fifo_dout : out STD_LOGIC_VECTOR ( 17 downto 0 ); + sig_m_valid_out_reg : out STD_LOGIC; + m_axis_mm2s_aclk : in STD_LOGIC; + RD_EN : in STD_LOGIC; + RST : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + WR_EN : in STD_LOGIC; + dm2linebuf_mm2s_tdata : in STD_LOGIC_VECTOR ( 17 downto 0 ); + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_41 : entity is "builtin_prim_v6"; +end Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_41; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_41 is + signal \^empty\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_14\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_15\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_18\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_19\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_20\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_21\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_22\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_23\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_24\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_25\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_26\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_27\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_28\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_31\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_32\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_33\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_34\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_35\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_36\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_37\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_38\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_39\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_40\ : STD_LOGIC; + signal \gf36e1_inst.sngfifo36e1_n_41\ : STD_LOGIC; + signal p_10_out : STD_LOGIC; + signal p_11_out : STD_LOGIC; + signal p_12_out : STD_LOGIC; + signal p_13_out : STD_LOGIC; + signal \NLW_gf36e1_inst.sngfifo36e1_DO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 16 ); + signal \NLW_gf36e1_inst.sngfifo36e1_DOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal \NLW_gf36e1_inst.sngfifo36e1_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \NLW_gf36e1_inst.sngfifo36e1_RDCOUNT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 12 downto 11 ); + signal \NLW_gf36e1_inst.sngfifo36e1_WRCOUNT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 12 downto 11 ); + attribute CLOCK_DOMAINS : string; + attribute CLOCK_DOMAINS of \gf36e1_inst.sngfifo36e1\ : label is "INDEPENDENT"; + attribute box_type : string; + attribute box_type of \gf36e1_inst.sngfifo36e1\ : label is "PRIMITIVE"; +begin + EMPTY <= \^empty\; +\gf36e1_inst.sngfifo36e1\: unisim.vcomponents.FIFO36E1 + generic map( + ALMOST_EMPTY_OFFSET => X"000A", + ALMOST_FULL_OFFSET => X"0097", + DATA_WIDTH => 18, + DO_REG => 1, + EN_ECC_READ => false, + EN_ECC_WRITE => false, + EN_SYN => false, + FIFO_MODE => "FIFO36", + FIRST_WORD_FALL_THROUGH => true, + INIT => X"000000000000000000", + IS_RDCLK_INVERTED => '0', + IS_RDEN_INVERTED => '0', + IS_RSTREG_INVERTED => '0', + IS_RST_INVERTED => '0', + IS_WRCLK_INVERTED => '0', + IS_WREN_INVERTED => '0', + SIM_DEVICE => "7SERIES", + SRVAL => X"000000000000000000" + ) + port map ( + ALMOSTEMPTY => p_11_out, + ALMOSTFULL => p_10_out, + DBITERR => p_13_out, + DI(63 downto 16) => B"000000000000000000000000000000000000000000000000", + DI(15 downto 0) => dm2linebuf_mm2s_tdata(15 downto 0), + DIP(7 downto 2) => B"000000", + DIP(1 downto 0) => dm2linebuf_mm2s_tdata(17 downto 16), + DO(63 downto 16) => \NLW_gf36e1_inst.sngfifo36e1_DO_UNCONNECTED\(63 downto 16), + DO(15 downto 0) => fifo_dout(15 downto 0), + DOP(7 downto 2) => \NLW_gf36e1_inst.sngfifo36e1_DOP_UNCONNECTED\(7 downto 2), + DOP(1 downto 0) => fifo_dout(17 downto 16), + ECCPARITY(7 downto 0) => \NLW_gf36e1_inst.sngfifo36e1_ECCPARITY_UNCONNECTED\(7 downto 0), + EMPTY => \^empty\, + FULL => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RDCLK => m_axis_mm2s_aclk, + RDCOUNT(12 downto 11) => \NLW_gf36e1_inst.sngfifo36e1_RDCOUNT_UNCONNECTED\(12 downto 11), + RDCOUNT(10) => \gf36e1_inst.sngfifo36e1_n_18\, + RDCOUNT(9) => \gf36e1_inst.sngfifo36e1_n_19\, + RDCOUNT(8) => \gf36e1_inst.sngfifo36e1_n_20\, + RDCOUNT(7) => \gf36e1_inst.sngfifo36e1_n_21\, + RDCOUNT(6) => \gf36e1_inst.sngfifo36e1_n_22\, + RDCOUNT(5) => \gf36e1_inst.sngfifo36e1_n_23\, + RDCOUNT(4) => \gf36e1_inst.sngfifo36e1_n_24\, + RDCOUNT(3) => \gf36e1_inst.sngfifo36e1_n_25\, + RDCOUNT(2) => \gf36e1_inst.sngfifo36e1_n_26\, + RDCOUNT(1) => \gf36e1_inst.sngfifo36e1_n_27\, + RDCOUNT(0) => \gf36e1_inst.sngfifo36e1_n_28\, + RDEN => RD_EN, + RDERR => \gf36e1_inst.sngfifo36e1_n_14\, + REGCE => '0', + RST => RST, + RSTREG => '0', + SBITERR => p_12_out, + WRCLK => m_axi_mm2s_aclk, + WRCOUNT(12 downto 11) => \NLW_gf36e1_inst.sngfifo36e1_WRCOUNT_UNCONNECTED\(12 downto 11), + WRCOUNT(10) => \gf36e1_inst.sngfifo36e1_n_31\, + WRCOUNT(9) => \gf36e1_inst.sngfifo36e1_n_32\, + WRCOUNT(8) => \gf36e1_inst.sngfifo36e1_n_33\, + WRCOUNT(7) => \gf36e1_inst.sngfifo36e1_n_34\, + WRCOUNT(6) => \gf36e1_inst.sngfifo36e1_n_35\, + WRCOUNT(5) => \gf36e1_inst.sngfifo36e1_n_36\, + WRCOUNT(4) => \gf36e1_inst.sngfifo36e1_n_37\, + WRCOUNT(3) => \gf36e1_inst.sngfifo36e1_n_38\, + WRCOUNT(2) => \gf36e1_inst.sngfifo36e1_n_39\, + WRCOUNT(1) => \gf36e1_inst.sngfifo36e1_n_40\, + WRCOUNT(0) => \gf36e1_inst.sngfifo36e1_n_41\, + WREN => WR_EN, + WRERR => \gf36e1_inst.sngfifo36e1_n_15\ + ); +sig_s_ready_dup_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^empty\, + I1 => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\, + O => sig_m_valid_out_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6__parameterized0\ is + port ( + EMPTY : out STD_LOGIC; + FULL : out STD_LOGIC; + DOUT : out STD_LOGIC_VECTOR ( 8 downto 0 ); + D : out STD_LOGIC_VECTOR ( 12 downto 0 ); + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]\ : out STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\ : out STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\ : out STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\ : out STD_LOGIC; + strm_not_finished_no_dwidth : out STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); + m_axi_s2mm_aclk : in STD_LOGIC; + RD_EN : in STD_LOGIC; + RST : in STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC; + DIN : in STD_LOGIC_VECTOR ( 8 downto 0 ); + M_VALID : in STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\ : in STD_LOGIC; + s2mm_fsync_out_i : in STD_LOGIC; + \out\ : in STD_LOGIC; + p_3_out : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 6 downto 0 ); + \vsize_vid_reg[12]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : in STD_LOGIC; + minusOp_1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0\ : in STD_LOGIC; + s2mm_strm_wready : in STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\ : in STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + minusOp : in STD_LOGIC_VECTOR ( 11 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6__parameterized0\ : entity is "builtin_prim_v6"; +end \Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6__parameterized0\ is + signal \^dout\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal \^empty\ : STD_LOGIC; + signal \^full\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_14_n_0\ : STD_LOGIC; + signal \^gen_s2mm_flush_sof_logic.done_vsize_counter_reg[12]\ : STD_LOGIC; + signal \^gen_sprt_for_s2mm.gen_no_axis_s2mm_dwidth_conv.chnl_ready_no_dwidth_reg\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0\ : STD_LOGIC; + signal fifo_wren : STD_LOGIC; + signal \gf18e1_inst.sngfifo18e1_n_0\ : STD_LOGIC; + signal \gf18e1_inst.sngfifo18e1_n_1\ : STD_LOGIC; + signal \gf18e1_inst.sngfifo18e1_n_10\ : STD_LOGIC; + signal \gf18e1_inst.sngfifo18e1_n_11\ : STD_LOGIC; + signal \gf18e1_inst.sngfifo18e1_n_12\ : STD_LOGIC; + signal \gf18e1_inst.sngfifo18e1_n_13\ : STD_LOGIC; + signal \gf18e1_inst.sngfifo18e1_n_14\ : STD_LOGIC; + signal \gf18e1_inst.sngfifo18e1_n_15\ : STD_LOGIC; + signal \gf18e1_inst.sngfifo18e1_n_16\ : STD_LOGIC; + signal \gf18e1_inst.sngfifo18e1_n_17\ : STD_LOGIC; + signal \gf18e1_inst.sngfifo18e1_n_19\ : STD_LOGIC; + signal \gf18e1_inst.sngfifo18e1_n_20\ : STD_LOGIC; + signal \gf18e1_inst.sngfifo18e1_n_21\ : STD_LOGIC; + signal \gf18e1_inst.sngfifo18e1_n_22\ : STD_LOGIC; + signal \gf18e1_inst.sngfifo18e1_n_23\ : STD_LOGIC; + signal \gf18e1_inst.sngfifo18e1_n_24\ : STD_LOGIC; + signal \gf18e1_inst.sngfifo18e1_n_25\ : STD_LOGIC; + signal \gf18e1_inst.sngfifo18e1_n_26\ : STD_LOGIC; + signal \gf18e1_inst.sngfifo18e1_n_27\ : STD_LOGIC; + signal \gf18e1_inst.sngfifo18e1_n_28\ : STD_LOGIC; + signal \gf18e1_inst.sngfifo18e1_n_29\ : STD_LOGIC; + signal \gf18e1_inst.sngfifo18e1_n_4\ : STD_LOGIC; + signal \gf18e1_inst.sngfifo18e1_n_7\ : STD_LOGIC; + signal \gf18e1_inst.sngfifo18e1_n_8\ : STD_LOGIC; + signal \gf18e1_inst.sngfifo18e1_n_9\ : STD_LOGIC; + signal p_5_out : STD_LOGIC; + signal \NLW_gf18e1_inst.sngfifo18e1_DO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_gf18e1_inst.sngfifo18e1_DOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_gf18e1_inst.sngfifo18e1_RDCOUNT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 11 to 11 ); + signal \NLW_gf18e1_inst.sngfifo18e1_WRCOUNT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 11 to 11 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_i_1\ : label is "soft_lutpair85"; + attribute SOFT_HLUTNM of \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_i_1\ : label is "soft_lutpair84"; + attribute SOFT_HLUTNM of \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6\ : label is "soft_lutpair85"; + attribute SOFT_HLUTNM of \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[7]_i_1\ : label is "soft_lutpair84"; + attribute CLOCK_DOMAINS : string; + attribute CLOCK_DOMAINS of \gf18e1_inst.sngfifo18e1\ : label is "INDEPENDENT"; + attribute box_type : string; + attribute box_type of \gf18e1_inst.sngfifo18e1\ : label is "PRIMITIVE"; +begin + DOUT(8 downto 0) <= \^dout\(8 downto 0); + EMPTY <= \^empty\; + FULL <= \^full\; + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]\ <= \^gen_s2mm_flush_sof_logic.done_vsize_counter_reg[12]\; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\ <= \^gen_sprt_for_s2mm.gen_no_axis_s2mm_dwidth_conv.chnl_ready_no_dwidth_reg\; +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F044" + ) + port map ( + I0 => Q(0), + I1 => \^gen_s2mm_flush_sof_logic.done_vsize_counter_reg[12]\, + I2 => \vsize_vid_reg[12]\(0), + I3 => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\, + O => D(0) + ); +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[10]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F088" + ) + port map ( + I0 => minusOp_1(9), + I1 => \^gen_s2mm_flush_sof_logic.done_vsize_counter_reg[12]\, + I2 => \vsize_vid_reg[12]\(10), + I3 => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\, + O => D(10) + ); +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[11]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F088" + ) + port map ( + I0 => minusOp_1(10), + I1 => \^gen_s2mm_flush_sof_logic.done_vsize_counter_reg[12]\, + I2 => \vsize_vid_reg[12]\(11), + I3 => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\, + O => D(11) + ); +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_14\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFDFFF" + ) + port map ( + I0 => \^dout\(8), + I1 => \^empty\, + I2 => s2mm_strm_wready, + I3 => Q(0), + I4 => Q(3), + I5 => Q(4), + O => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_14_n_0\ + ); +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F088" + ) + port map ( + I0 => minusOp_1(11), + I1 => \^gen_s2mm_flush_sof_logic.done_vsize_counter_reg[12]\, + I2 => \vsize_vid_reg[12]\(12), + I3 => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\, + O => D(12) + ); +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"DF" + ) + port map ( + I0 => s2mm_strm_wready, + I1 => \^empty\, + I2 => \^dout\(8), + O => \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\ + ); +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_9\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0\, + I1 => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_14_n_0\, + I2 => Q(6), + I3 => Q(1), + I4 => Q(5), + I5 => Q(2), + O => \^gen_s2mm_flush_sof_logic.done_vsize_counter_reg[12]\ + ); +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F088" + ) + port map ( + I0 => minusOp_1(0), + I1 => \^gen_s2mm_flush_sof_logic.done_vsize_counter_reg[12]\, + I2 => \vsize_vid_reg[12]\(1), + I3 => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\, + O => D(1) + ); +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F088" + ) + port map ( + I0 => minusOp_1(1), + I1 => \^gen_s2mm_flush_sof_logic.done_vsize_counter_reg[12]\, + I2 => \vsize_vid_reg[12]\(2), + I3 => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\, + O => D(2) + ); +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F088" + ) + port map ( + I0 => minusOp_1(2), + I1 => \^gen_s2mm_flush_sof_logic.done_vsize_counter_reg[12]\, + I2 => \vsize_vid_reg[12]\(3), + I3 => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\, + O => D(3) + ); +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F088" + ) + port map ( + I0 => minusOp_1(3), + I1 => \^gen_s2mm_flush_sof_logic.done_vsize_counter_reg[12]\, + I2 => \vsize_vid_reg[12]\(4), + I3 => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\, + O => D(4) + ); +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F088" + ) + port map ( + I0 => minusOp_1(4), + I1 => \^gen_s2mm_flush_sof_logic.done_vsize_counter_reg[12]\, + I2 => \vsize_vid_reg[12]\(5), + I3 => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\, + O => D(5) + ); +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F088" + ) + port map ( + I0 => minusOp_1(5), + I1 => \^gen_s2mm_flush_sof_logic.done_vsize_counter_reg[12]\, + I2 => \vsize_vid_reg[12]\(6), + I3 => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\, + O => D(6) + ); +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[7]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F088" + ) + port map ( + I0 => minusOp_1(6), + I1 => \^gen_s2mm_flush_sof_logic.done_vsize_counter_reg[12]\, + I2 => \vsize_vid_reg[12]\(7), + I3 => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\, + O => D(7) + ); +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F088" + ) + port map ( + I0 => minusOp_1(7), + I1 => \^gen_s2mm_flush_sof_logic.done_vsize_counter_reg[12]\, + I2 => \vsize_vid_reg[12]\(8), + I3 => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\, + O => D(8) + ); +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[9]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F088" + ) + port map ( + I0 => minusOp_1(8), + I1 => \^gen_s2mm_flush_sof_logic.done_vsize_counter_reg[12]\, + I2 => \vsize_vid_reg[12]\(9), + I3 => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\, + O => D(9) + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => \^gen_sprt_for_s2mm.gen_no_axis_s2mm_dwidth_conv.chnl_ready_no_dwidth_reg\, + I1 => DIN(8), + I2 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\, + I3 => s2mm_fsync_out_i, + O => strm_not_finished_no_dwidth + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0\, + I1 => s2mm_fsync_out_i, + O => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"C0E2" + ) + port map ( + I0 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0\, + I1 => s2mm_fsync_out_i, + I2 => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\(0), + I3 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0]\(0), + O => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\(0) + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[10]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E2C0" + ) + port map ( + I0 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0\, + I1 => s2mm_fsync_out_i, + I2 => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\(10), + I3 => minusOp(9), + O => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\(10) + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[11]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E2C0" + ) + port map ( + I0 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0\, + I1 => s2mm_fsync_out_i, + I2 => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\(11), + I3 => minusOp(10), + O => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\(11) + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E2C0" + ) + port map ( + I0 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0\, + I1 => s2mm_fsync_out_i, + I2 => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\(12), + I3 => minusOp(11), + O => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\(12) + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFEFFFFFFFFFFFFF" + ) + port map ( + I0 => s2mm_fsync_out_i, + I1 => \^full\, + I2 => \out\, + I3 => p_3_out, + I4 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\, + I5 => M_VALID, + O => \^gen_sprt_for_s2mm.gen_no_axis_s2mm_dwidth_conv.chnl_ready_no_dwidth_reg\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFDF" + ) + port map ( + I0 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0]\(0), + I1 => \^gen_sprt_for_s2mm.gen_no_axis_s2mm_dwidth_conv.chnl_ready_no_dwidth_reg\, + I2 => DIN(8), + I3 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\, + O => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E2C0" + ) + port map ( + I0 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0\, + I1 => s2mm_fsync_out_i, + I2 => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\(1), + I3 => minusOp(0), + O => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\(1) + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E2C0" + ) + port map ( + I0 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0\, + I1 => s2mm_fsync_out_i, + I2 => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\(2), + I3 => minusOp(1), + O => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\(2) + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E2C0" + ) + port map ( + I0 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0\, + I1 => s2mm_fsync_out_i, + I2 => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\(3), + I3 => minusOp(2), + O => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\(3) + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E2C0" + ) + port map ( + I0 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0\, + I1 => s2mm_fsync_out_i, + I2 => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\(4), + I3 => minusOp(3), + O => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\(4) + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E2C0" + ) + port map ( + I0 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0\, + I1 => s2mm_fsync_out_i, + I2 => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\(5), + I3 => minusOp(4), + O => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\(5) + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E2C0" + ) + port map ( + I0 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0\, + I1 => s2mm_fsync_out_i, + I2 => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\(6), + I3 => minusOp(5), + O => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\(6) + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[7]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E2C0" + ) + port map ( + I0 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0\, + I1 => s2mm_fsync_out_i, + I2 => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\(7), + I3 => minusOp(6), + O => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\(7) + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E2C0" + ) + port map ( + I0 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0\, + I1 => s2mm_fsync_out_i, + I2 => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\(8), + I3 => minusOp(7), + O => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\(8) + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[9]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E2C0" + ) + port map ( + I0 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_6_n_0\, + I1 => s2mm_fsync_out_i, + I2 => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\(9), + I3 => minusOp(8), + O => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\(9) + ); +\gf18e1_inst.sngfifo18e1\: unisim.vcomponents.FIFO18E1 + generic map( + ALMOST_EMPTY_OFFSET => X"000A", + ALMOST_FULL_OFFSET => X"0097", + DATA_WIDTH => 9, + DO_REG => 1, + EN_SYN => false, + FIFO_MODE => "FIFO18", + FIRST_WORD_FALL_THROUGH => true, + INIT => X"000000000", + IS_RDCLK_INVERTED => '0', + IS_RDEN_INVERTED => '0', + IS_RSTREG_INVERTED => '0', + IS_RST_INVERTED => '0', + IS_WRCLK_INVERTED => '0', + IS_WREN_INVERTED => '0', + SIM_DEVICE => "7SERIES", + SRVAL => X"000000000" + ) + port map ( + ALMOSTEMPTY => \gf18e1_inst.sngfifo18e1_n_0\, + ALMOSTFULL => \gf18e1_inst.sngfifo18e1_n_1\, + DI(31 downto 8) => B"000000000000000000000000", + DI(7 downto 0) => DIN(7 downto 0), + DIP(3 downto 1) => B"000", + DIP(0) => DIN(8), + DO(31 downto 8) => \NLW_gf18e1_inst.sngfifo18e1_DO_UNCONNECTED\(31 downto 8), + DO(7 downto 0) => \^dout\(7 downto 0), + DOP(3 downto 1) => \NLW_gf18e1_inst.sngfifo18e1_DOP_UNCONNECTED\(3 downto 1), + DOP(0) => \^dout\(8), + EMPTY => \^empty\, + FULL => \^full\, + RDCLK => m_axi_s2mm_aclk, + RDCOUNT(11) => \NLW_gf18e1_inst.sngfifo18e1_RDCOUNT_UNCONNECTED\(11), + RDCOUNT(10) => \gf18e1_inst.sngfifo18e1_n_7\, + RDCOUNT(9) => \gf18e1_inst.sngfifo18e1_n_8\, + RDCOUNT(8) => \gf18e1_inst.sngfifo18e1_n_9\, + RDCOUNT(7) => \gf18e1_inst.sngfifo18e1_n_10\, + RDCOUNT(6) => \gf18e1_inst.sngfifo18e1_n_11\, + RDCOUNT(5) => \gf18e1_inst.sngfifo18e1_n_12\, + RDCOUNT(4) => \gf18e1_inst.sngfifo18e1_n_13\, + RDCOUNT(3) => \gf18e1_inst.sngfifo18e1_n_14\, + RDCOUNT(2) => \gf18e1_inst.sngfifo18e1_n_15\, + RDCOUNT(1) => \gf18e1_inst.sngfifo18e1_n_16\, + RDCOUNT(0) => \gf18e1_inst.sngfifo18e1_n_17\, + RDEN => RD_EN, + RDERR => \gf18e1_inst.sngfifo18e1_n_4\, + REGCE => '0', + RST => RST, + RSTREG => '0', + WRCLK => s_axis_s2mm_aclk, + WRCOUNT(11) => \NLW_gf18e1_inst.sngfifo18e1_WRCOUNT_UNCONNECTED\(11), + WRCOUNT(10) => \gf18e1_inst.sngfifo18e1_n_19\, + WRCOUNT(9) => \gf18e1_inst.sngfifo18e1_n_20\, + WRCOUNT(8) => \gf18e1_inst.sngfifo18e1_n_21\, + WRCOUNT(7) => \gf18e1_inst.sngfifo18e1_n_22\, + WRCOUNT(6) => \gf18e1_inst.sngfifo18e1_n_23\, + WRCOUNT(5) => \gf18e1_inst.sngfifo18e1_n_24\, + WRCOUNT(4) => \gf18e1_inst.sngfifo18e1_n_25\, + WRCOUNT(3) => \gf18e1_inst.sngfifo18e1_n_26\, + WRCOUNT(2) => \gf18e1_inst.sngfifo18e1_n_27\, + WRCOUNT(1) => \gf18e1_inst.sngfifo18e1_n_28\, + WRCOUNT(0) => \gf18e1_inst.sngfifo18e1_n_29\, + WREN => fifo_wren, + WRERR => p_5_out + ); +\gf18e1_inst.sngfifo18e1_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000400000" + ) + port map ( + I0 => \^full\, + I1 => M_VALID, + I2 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\, + I3 => s2mm_fsync_out_i, + I4 => \out\, + I5 => p_3_out, + O => fifo_wren + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_dmem is + port ( + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_xfer_is_seq_reg_reg : out STD_LOGIC_VECTOR ( 9 downto 0 ); + \sig_child_addr_cntr_lsh_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + S : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \sig_xfer_len_reg_reg[4]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \sig_xfer_len_reg_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_xfer_is_seq_reg_reg_0 : out STD_LOGIC; + sig_xfer_cmd_cmplt_reg0 : out STD_LOGIC; + sig_csm_state_ns1 : out STD_LOGIC; + O : out STD_LOGIC_VECTOR ( 3 downto 0 ); + CO : out STD_LOGIC_VECTOR ( 0 to 0 ); + \sig_child_addr_cntr_lsh_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + sig_adjusted_addr_incr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + sig_csm_pop_child_cmd : in STD_LOGIC; + sig_child_qual_first_of_2 : in STD_LOGIC; + sig_child_qual_error_reg : in STD_LOGIC; + \gpr1.dout_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \gpr1.dout_i_reg[7]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + sig_child_addr_cntr_lsh_reg : in STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_stream_rst : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + p_0_out : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_dmem : entity is "dmem"; +end Arty_Z7_20_axi_vdma_0_0_dmem; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_dmem is + signal \sig_child_addr_cntr_lsh[0]_i_3_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh[0]_i_4_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh[0]_i_5_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh[0]_i_6_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh[4]_i_2_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh[4]_i_3_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh[4]_i_4_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh[4]_i_5_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh_reg[0]_i_2_n_0\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh_reg[0]_i_2_n_1\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh_reg[0]_i_2_n_2\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh_reg[0]_i_2_n_3\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \sig_child_addr_cntr_lsh_reg[4]_i_1_n_3\ : STD_LOGIC; + signal sig_sf2pcc_packet_eop : STD_LOGIC; + signal \^sig_xfer_is_seq_reg_reg\ : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal \sig_xfer_len_reg[5]_i_2_n_0\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_sig_csm_state[2]_i_2\ : label is "soft_lutpair178"; + attribute SOFT_HLUTNM of sig_xfer_cmd_cmplt_reg_i_1 : label is "soft_lutpair178"; + attribute SOFT_HLUTNM of \sig_xfer_len_reg[4]_i_1\ : label is "soft_lutpair179"; + attribute SOFT_HLUTNM of \sig_xfer_len_reg[5]_i_1\ : label is "soft_lutpair179"; +begin + sig_xfer_is_seq_reg_reg(9 downto 0) <= \^sig_xfer_is_seq_reg_reg\(9 downto 0); +\FSM_sequential_sig_csm_state[2]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A2" + ) + port map ( + I0 => \^sig_xfer_is_seq_reg_reg\(9), + I1 => sig_child_qual_first_of_2, + I2 => sig_sf2pcc_packet_eop, + O => sig_csm_state_ns1 + ); +\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => p_0_out(0), + Q => \^sig_xfer_is_seq_reg_reg\(0), + R => sig_stream_rst + ); +\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => p_0_out(10), + Q => sig_sf2pcc_packet_eop, + R => sig_stream_rst + ); +\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => p_0_out(1), + Q => \^sig_xfer_is_seq_reg_reg\(1), + R => sig_stream_rst + ); +\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => p_0_out(2), + Q => \^sig_xfer_is_seq_reg_reg\(2), + R => sig_stream_rst + ); +\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => p_0_out(3), + Q => \^sig_xfer_is_seq_reg_reg\(3), + R => sig_stream_rst + ); +\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => p_0_out(4), + Q => \^sig_xfer_is_seq_reg_reg\(4), + R => sig_stream_rst + ); +\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => p_0_out(5), + Q => \^sig_xfer_is_seq_reg_reg\(5), + R => sig_stream_rst + ); +\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => p_0_out(6), + Q => \^sig_xfer_is_seq_reg_reg\(6), + R => sig_stream_rst + ); +\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => p_0_out(7), + Q => \^sig_xfer_is_seq_reg_reg\(7), + R => sig_stream_rst + ); +\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => p_0_out(8), + Q => \^sig_xfer_is_seq_reg_reg\(8), + R => sig_stream_rst + ); +\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => p_0_out(9), + Q => \^sig_xfer_is_seq_reg_reg\(9), + R => sig_stream_rst + ); +\sig_byte_change_minus1_carry__0_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^sig_xfer_is_seq_reg_reg\(7), + O => \sig_xfer_len_reg_reg[4]\(3) + ); +\sig_byte_change_minus1_carry__0_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^sig_xfer_is_seq_reg_reg\(6), + O => \sig_xfer_len_reg_reg[4]\(2) + ); +\sig_byte_change_minus1_carry__0_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^sig_xfer_is_seq_reg_reg\(5), + O => \sig_xfer_len_reg_reg[4]\(1) + ); +\sig_byte_change_minus1_carry__0_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^sig_xfer_is_seq_reg_reg\(4), + O => \sig_xfer_len_reg_reg[4]\(0) + ); +\sig_byte_change_minus1_carry__1_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^sig_xfer_is_seq_reg_reg\(8), + O => \sig_xfer_len_reg_reg[5]\(0) + ); +sig_byte_change_minus1_carry_i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^sig_xfer_is_seq_reg_reg\(3), + O => S(3) + ); +sig_byte_change_minus1_carry_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^sig_xfer_is_seq_reg_reg\(2), + I1 => sig_child_addr_cntr_lsh_reg(2), + O => S(2) + ); +sig_byte_change_minus1_carry_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^sig_xfer_is_seq_reg_reg\(1), + I1 => sig_child_addr_cntr_lsh_reg(1), + O => S(1) + ); +sig_byte_change_minus1_carry_i_4: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^sig_xfer_is_seq_reg_reg\(0), + I1 => sig_child_addr_cntr_lsh_reg(0), + O => S(0) + ); +\sig_child_addr_cntr_lsh[0]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^sig_xfer_is_seq_reg_reg\(3), + I1 => sig_csm_pop_child_cmd, + O => \sig_child_addr_cntr_lsh[0]_i_3_n_0\ + ); +\sig_child_addr_cntr_lsh[0]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^sig_xfer_is_seq_reg_reg\(2), + I1 => sig_csm_pop_child_cmd, + O => \sig_child_addr_cntr_lsh[0]_i_4_n_0\ + ); +\sig_child_addr_cntr_lsh[0]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^sig_xfer_is_seq_reg_reg\(1), + I1 => sig_csm_pop_child_cmd, + O => \sig_child_addr_cntr_lsh[0]_i_5_n_0\ + ); +\sig_child_addr_cntr_lsh[0]_i_6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^sig_xfer_is_seq_reg_reg\(0), + I1 => sig_csm_pop_child_cmd, + O => \sig_child_addr_cntr_lsh[0]_i_6_n_0\ + ); +\sig_child_addr_cntr_lsh[4]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^sig_xfer_is_seq_reg_reg\(7), + I1 => sig_csm_pop_child_cmd, + O => \sig_child_addr_cntr_lsh[4]_i_2_n_0\ + ); +\sig_child_addr_cntr_lsh[4]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^sig_xfer_is_seq_reg_reg\(6), + I1 => sig_csm_pop_child_cmd, + O => \sig_child_addr_cntr_lsh[4]_i_3_n_0\ + ); +\sig_child_addr_cntr_lsh[4]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^sig_xfer_is_seq_reg_reg\(5), + I1 => sig_csm_pop_child_cmd, + O => \sig_child_addr_cntr_lsh[4]_i_4_n_0\ + ); +\sig_child_addr_cntr_lsh[4]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^sig_xfer_is_seq_reg_reg\(4), + I1 => sig_csm_pop_child_cmd, + O => \sig_child_addr_cntr_lsh[4]_i_5_n_0\ + ); +\sig_child_addr_cntr_lsh[8]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^sig_xfer_is_seq_reg_reg\(8), + I1 => sig_csm_pop_child_cmd, + O => \sig_child_addr_cntr_lsh_reg[11]\(0) + ); +\sig_child_addr_cntr_lsh_reg[0]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \sig_child_addr_cntr_lsh_reg[0]_i_2_n_0\, + CO(2) => \sig_child_addr_cntr_lsh_reg[0]_i_2_n_1\, + CO(1) => \sig_child_addr_cntr_lsh_reg[0]_i_2_n_2\, + CO(0) => \sig_child_addr_cntr_lsh_reg[0]_i_2_n_3\, + CYINIT => '0', + DI(3) => \sig_child_addr_cntr_lsh[0]_i_3_n_0\, + DI(2) => \sig_child_addr_cntr_lsh[0]_i_4_n_0\, + DI(1) => \sig_child_addr_cntr_lsh[0]_i_5_n_0\, + DI(0) => \sig_child_addr_cntr_lsh[0]_i_6_n_0\, + O(3 downto 0) => O(3 downto 0), + S(3 downto 0) => \gpr1.dout_i_reg[3]_0\(3 downto 0) + ); +\sig_child_addr_cntr_lsh_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \sig_child_addr_cntr_lsh_reg[0]_i_2_n_0\, + CO(3) => CO(0), + CO(2) => \sig_child_addr_cntr_lsh_reg[4]_i_1_n_1\, + CO(1) => \sig_child_addr_cntr_lsh_reg[4]_i_1_n_2\, + CO(0) => \sig_child_addr_cntr_lsh_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3) => \sig_child_addr_cntr_lsh[4]_i_2_n_0\, + DI(2) => \sig_child_addr_cntr_lsh[4]_i_3_n_0\, + DI(1) => \sig_child_addr_cntr_lsh[4]_i_4_n_0\, + DI(0) => \sig_child_addr_cntr_lsh[4]_i_5_n_0\, + O(3 downto 0) => \sig_child_addr_cntr_lsh_reg[7]\(3 downto 0), + S(3 downto 0) => \gpr1.dout_i_reg[7]_0\(3 downto 0) + ); +sig_xfer_cmd_cmplt_reg_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFB0" + ) + port map ( + I0 => sig_sf2pcc_packet_eop, + I1 => sig_child_qual_first_of_2, + I2 => \^sig_xfer_is_seq_reg_reg\(9), + I3 => sig_child_qual_error_reg, + O => sig_xfer_cmd_cmplt_reg0 + ); +sig_xfer_is_seq_reg_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"4F" + ) + port map ( + I0 => sig_sf2pcc_packet_eop, + I1 => sig_child_qual_first_of_2, + I2 => \^sig_xfer_is_seq_reg_reg\(9), + O => sig_xfer_is_seq_reg_reg_0 + ); +\sig_xfer_len_reg[3]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \sig_xfer_len_reg[5]_i_2_n_0\, + I1 => sig_adjusted_addr_incr(6), + O => D(0) + ); +\sig_xfer_len_reg[4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E1" + ) + port map ( + I0 => sig_adjusted_addr_incr(6), + I1 => \sig_xfer_len_reg[5]_i_2_n_0\, + I2 => sig_adjusted_addr_incr(7), + O => D(1) + ); +\sig_xfer_len_reg[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FE01" + ) + port map ( + I0 => sig_adjusted_addr_incr(7), + I1 => \sig_xfer_len_reg[5]_i_2_n_0\, + I2 => sig_adjusted_addr_incr(6), + I3 => sig_adjusted_addr_incr(8), + O => D(2) + ); +\sig_xfer_len_reg[5]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => sig_adjusted_addr_incr(4), + I1 => sig_adjusted_addr_incr(2), + I2 => sig_adjusted_addr_incr(0), + I3 => sig_adjusted_addr_incr(1), + I4 => sig_adjusted_addr_incr(3), + I5 => sig_adjusted_addr_incr(5), + O => \sig_xfer_len_reg[5]_i_2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_rd_bin_cntr is + port ( + Q : out STD_LOGIC_VECTOR ( 7 downto 0 ); + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); + sig_stream_rst : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_rd_bin_cntr : entity is "rd_bin_cntr"; +end Arty_Z7_20_axi_vdma_0_0_rd_bin_cntr; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_rd_bin_cntr is + signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \gc1.count[7]_i_2__0_n_0\ : STD_LOGIC; + signal \plusOp__1\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal rd_pntr_plus2 : STD_LOGIC_VECTOR ( 7 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \gc1.count[0]_i_1__0\ : label is "soft_lutpair170"; + attribute SOFT_HLUTNM of \gc1.count[2]_i_1__0\ : label is "soft_lutpair170"; + attribute SOFT_HLUTNM of \gc1.count[3]_i_1__0\ : label is "soft_lutpair168"; + attribute SOFT_HLUTNM of \gc1.count[4]_i_1__0\ : label is "soft_lutpair168"; + attribute SOFT_HLUTNM of \gc1.count[6]_i_1__0\ : label is "soft_lutpair169"; + attribute SOFT_HLUTNM of \gc1.count[7]_i_1__0\ : label is "soft_lutpair169"; +begin + Q(7 downto 0) <= \^q\(7 downto 0); +\gc1.count[0]_i_1__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => rd_pntr_plus2(0), + O => \plusOp__1\(0) + ); +\gc1.count[1]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => rd_pntr_plus2(0), + I1 => rd_pntr_plus2(1), + O => \plusOp__1\(1) + ); +\gc1.count[2]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => rd_pntr_plus2(0), + I1 => rd_pntr_plus2(1), + I2 => rd_pntr_plus2(2), + O => \plusOp__1\(2) + ); +\gc1.count[3]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => rd_pntr_plus2(1), + I1 => rd_pntr_plus2(0), + I2 => rd_pntr_plus2(2), + I3 => rd_pntr_plus2(3), + O => \plusOp__1\(3) + ); +\gc1.count[4]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => rd_pntr_plus2(2), + I1 => rd_pntr_plus2(0), + I2 => rd_pntr_plus2(1), + I3 => rd_pntr_plus2(3), + I4 => rd_pntr_plus2(4), + O => \plusOp__1\(4) + ); +\gc1.count[5]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFFFFFF80000000" + ) + port map ( + I0 => rd_pntr_plus2(3), + I1 => rd_pntr_plus2(1), + I2 => rd_pntr_plus2(0), + I3 => rd_pntr_plus2(2), + I4 => rd_pntr_plus2(4), + I5 => rd_pntr_plus2(5), + O => \plusOp__1\(5) + ); +\gc1.count[6]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \gc1.count[7]_i_2__0_n_0\, + I1 => rd_pntr_plus2(6), + O => \plusOp__1\(6) + ); +\gc1.count[7]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \gc1.count[7]_i_2__0_n_0\, + I1 => rd_pntr_plus2(6), + I2 => rd_pntr_plus2(7), + O => \plusOp__1\(7) + ); +\gc1.count[7]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => rd_pntr_plus2(5), + I1 => rd_pntr_plus2(3), + I2 => rd_pntr_plus2(1), + I3 => rd_pntr_plus2(0), + I4 => rd_pntr_plus2(2), + I5 => rd_pntr_plus2(4), + O => \gc1.count[7]_i_2__0_n_0\ + ); +\gc1.count_d1_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => rd_pntr_plus2(0), + Q => \^q\(0), + S => sig_stream_rst + ); +\gc1.count_d1_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => rd_pntr_plus2(1), + Q => \^q\(1), + R => sig_stream_rst + ); +\gc1.count_d1_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => rd_pntr_plus2(2), + Q => \^q\(2), + R => sig_stream_rst + ); +\gc1.count_d1_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => rd_pntr_plus2(3), + Q => \^q\(3), + R => sig_stream_rst + ); +\gc1.count_d1_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => rd_pntr_plus2(4), + Q => \^q\(4), + R => sig_stream_rst + ); +\gc1.count_d1_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => rd_pntr_plus2(5), + Q => \^q\(5), + R => sig_stream_rst + ); +\gc1.count_d1_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => rd_pntr_plus2(6), + Q => \^q\(6), + R => sig_stream_rst + ); +\gc1.count_d1_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => rd_pntr_plus2(7), + Q => \^q\(7), + R => sig_stream_rst + ); +\gc1.count_d2_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \^q\(0), + Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(0), + R => sig_stream_rst + ); +\gc1.count_d2_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \^q\(1), + Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(1), + R => sig_stream_rst + ); +\gc1.count_d2_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \^q\(2), + Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(2), + R => sig_stream_rst + ); +\gc1.count_d2_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \^q\(3), + Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(3), + R => sig_stream_rst + ); +\gc1.count_d2_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \^q\(4), + Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(4), + R => sig_stream_rst + ); +\gc1.count_d2_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \^q\(5), + Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(5), + R => sig_stream_rst + ); +\gc1.count_d2_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \^q\(6), + Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(6), + R => sig_stream_rst + ); +\gc1.count_d2_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \^q\(7), + Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(7), + R => sig_stream_rst + ); +\gc1.count_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \plusOp__1\(0), + Q => rd_pntr_plus2(0), + R => sig_stream_rst + ); +\gc1.count_reg[1]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \plusOp__1\(1), + Q => rd_pntr_plus2(1), + S => sig_stream_rst + ); +\gc1.count_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \plusOp__1\(2), + Q => rd_pntr_plus2(2), + R => sig_stream_rst + ); +\gc1.count_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \plusOp__1\(3), + Q => rd_pntr_plus2(3), + R => sig_stream_rst + ); +\gc1.count_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \plusOp__1\(4), + Q => rd_pntr_plus2(4), + R => sig_stream_rst + ); +\gc1.count_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \plusOp__1\(5), + Q => rd_pntr_plus2(5), + R => sig_stream_rst + ); +\gc1.count_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \plusOp__1\(6), + Q => rd_pntr_plus2(6), + R => sig_stream_rst + ); +\gc1.count_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \plusOp__1\(7), + Q => rd_pntr_plus2(7), + R => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_rd_bin_cntr_36 is + port ( + ram_full_i_reg : out STD_LOGIC; + ram_empty_fb_i_reg : out STD_LOGIC; + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); + ram_full_i_reg_0 : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + ram_empty_fb_i_reg_0 : in STD_LOGIC; + ram_full_fb_i_reg : in STD_LOGIC; + \out\ : in STD_LOGIC; + ram_full_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \gcc0.gc0.count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_rd_bin_cntr_36 : entity is "rd_bin_cntr"; +end Arty_Z7_20_axi_vdma_0_0_rd_bin_cntr_36; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_rd_bin_cntr_36 is + signal \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \gc1.count[7]_i_2_n_0\ : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal ram_empty_fb_i_i_2_n_0 : STD_LOGIC; + signal ram_empty_fb_i_i_3_n_0 : STD_LOGIC; + signal ram_empty_fb_i_i_4_n_0 : STD_LOGIC; + signal ram_empty_fb_i_i_5_n_0 : STD_LOGIC; + signal ram_empty_fb_i_i_6_n_0 : STD_LOGIC; + signal ram_empty_fb_i_i_7_n_0 : STD_LOGIC; + signal ram_empty_fb_i_i_8_n_0 : STD_LOGIC; + signal ram_empty_fb_i_i_9_n_0 : STD_LOGIC; + signal ram_full_fb_i_i_3_n_0 : STD_LOGIC; + signal ram_full_fb_i_i_5_n_0 : STD_LOGIC; + signal ram_full_fb_i_i_6_n_0 : STD_LOGIC; + signal ram_full_fb_i_i_7_n_0 : STD_LOGIC; + signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal rd_pntr_plus2 : STD_LOGIC_VECTOR ( 7 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \gc1.count[0]_i_1\ : label is "soft_lutpair103"; + attribute SOFT_HLUTNM of \gc1.count[2]_i_1\ : label is "soft_lutpair103"; + attribute SOFT_HLUTNM of \gc1.count[3]_i_1\ : label is "soft_lutpair102"; + attribute SOFT_HLUTNM of \gc1.count[4]_i_1\ : label is "soft_lutpair102"; + attribute SOFT_HLUTNM of \gc1.count[6]_i_1\ : label is "soft_lutpair104"; + attribute SOFT_HLUTNM of \gc1.count[7]_i_1\ : label is "soft_lutpair104"; +begin + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(7 downto 0) <= \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(7 downto 0); +\gc1.count[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => rd_pntr_plus2(0), + O => plusOp(0) + ); +\gc1.count[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => rd_pntr_plus2(0), + I1 => rd_pntr_plus2(1), + O => plusOp(1) + ); +\gc1.count[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => rd_pntr_plus2(2), + I1 => rd_pntr_plus2(1), + I2 => rd_pntr_plus2(0), + O => plusOp(2) + ); +\gc1.count[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => rd_pntr_plus2(3), + I1 => rd_pntr_plus2(0), + I2 => rd_pntr_plus2(1), + I3 => rd_pntr_plus2(2), + O => plusOp(3) + ); +\gc1.count[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAAAAAA" + ) + port map ( + I0 => rd_pntr_plus2(4), + I1 => rd_pntr_plus2(2), + I2 => rd_pntr_plus2(1), + I3 => rd_pntr_plus2(0), + I4 => rd_pntr_plus2(3), + O => plusOp(4) + ); +\gc1.count[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"6AAAAAAAAAAAAAAA" + ) + port map ( + I0 => rd_pntr_plus2(5), + I1 => rd_pntr_plus2(3), + I2 => rd_pntr_plus2(0), + I3 => rd_pntr_plus2(1), + I4 => rd_pntr_plus2(2), + I5 => rd_pntr_plus2(4), + O => plusOp(5) + ); +\gc1.count[6]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => rd_pntr_plus2(6), + I1 => \gc1.count[7]_i_2_n_0\, + O => plusOp(6) + ); +\gc1.count[7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => rd_pntr_plus2(7), + I1 => \gc1.count[7]_i_2_n_0\, + I2 => rd_pntr_plus2(6), + O => plusOp(7) + ); +\gc1.count[7]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => rd_pntr_plus2(5), + I1 => rd_pntr_plus2(3), + I2 => rd_pntr_plus2(0), + I3 => rd_pntr_plus2(1), + I4 => rd_pntr_plus2(2), + I5 => rd_pntr_plus2(4), + O => \gc1.count[7]_i_2_n_0\ + ); +\gc1.count_d1_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_empty_fb_i_reg_0, + D => rd_pntr_plus2(0), + Q => rd_pntr_plus1(0), + S => SR(0) + ); +\gc1.count_d1_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_empty_fb_i_reg_0, + D => rd_pntr_plus2(1), + Q => rd_pntr_plus1(1), + R => SR(0) + ); +\gc1.count_d1_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_empty_fb_i_reg_0, + D => rd_pntr_plus2(2), + Q => rd_pntr_plus1(2), + R => SR(0) + ); +\gc1.count_d1_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_empty_fb_i_reg_0, + D => rd_pntr_plus2(3), + Q => rd_pntr_plus1(3), + R => SR(0) + ); +\gc1.count_d1_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_empty_fb_i_reg_0, + D => rd_pntr_plus2(4), + Q => rd_pntr_plus1(4), + R => SR(0) + ); +\gc1.count_d1_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_empty_fb_i_reg_0, + D => rd_pntr_plus2(5), + Q => rd_pntr_plus1(5), + R => SR(0) + ); +\gc1.count_d1_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_empty_fb_i_reg_0, + D => rd_pntr_plus2(6), + Q => rd_pntr_plus1(6), + R => SR(0) + ); +\gc1.count_d1_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_empty_fb_i_reg_0, + D => rd_pntr_plus2(7), + Q => rd_pntr_plus1(7), + R => SR(0) + ); +\gc1.count_d2_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_empty_fb_i_reg_0, + D => rd_pntr_plus1(0), + Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0), + R => SR(0) + ); +\gc1.count_d2_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_empty_fb_i_reg_0, + D => rd_pntr_plus1(1), + Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1), + R => SR(0) + ); +\gc1.count_d2_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_empty_fb_i_reg_0, + D => rd_pntr_plus1(2), + Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(2), + R => SR(0) + ); +\gc1.count_d2_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_empty_fb_i_reg_0, + D => rd_pntr_plus1(3), + Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(3), + R => SR(0) + ); +\gc1.count_d2_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_empty_fb_i_reg_0, + D => rd_pntr_plus1(4), + Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(4), + R => SR(0) + ); +\gc1.count_d2_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_empty_fb_i_reg_0, + D => rd_pntr_plus1(5), + Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(5), + R => SR(0) + ); +\gc1.count_d2_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_empty_fb_i_reg_0, + D => rd_pntr_plus1(6), + Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(6), + R => SR(0) + ); +\gc1.count_d2_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_empty_fb_i_reg_0, + D => rd_pntr_plus1(7), + Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(7), + R => SR(0) + ); +\gc1.count_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_empty_fb_i_reg_0, + D => plusOp(0), + Q => rd_pntr_plus2(0), + R => SR(0) + ); +\gc1.count_reg[1]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_empty_fb_i_reg_0, + D => plusOp(1), + Q => rd_pntr_plus2(1), + S => SR(0) + ); +\gc1.count_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_empty_fb_i_reg_0, + D => plusOp(2), + Q => rd_pntr_plus2(2), + R => SR(0) + ); +\gc1.count_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_empty_fb_i_reg_0, + D => plusOp(3), + Q => rd_pntr_plus2(3), + R => SR(0) + ); +\gc1.count_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_empty_fb_i_reg_0, + D => plusOp(4), + Q => rd_pntr_plus2(4), + R => SR(0) + ); +\gc1.count_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_empty_fb_i_reg_0, + D => plusOp(5), + Q => rd_pntr_plus2(5), + R => SR(0) + ); +\gc1.count_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_empty_fb_i_reg_0, + D => plusOp(6), + Q => rd_pntr_plus2(6), + R => SR(0) + ); +\gc1.count_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_empty_fb_i_reg_0, + D => plusOp(7), + Q => rd_pntr_plus2(7), + R => SR(0) + ); +ram_empty_fb_i_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"4FCF4FCF4FFF4FCF" + ) + port map ( + I0 => ram_empty_fb_i_i_2_n_0, + I1 => \out\, + I2 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I3 => ram_full_i_reg_1(0), + I4 => ram_empty_fb_i_reg_0, + I5 => ram_empty_fb_i_i_3_n_0, + O => ram_empty_fb_i_reg + ); +ram_empty_fb_i_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000041000041" + ) + port map ( + I0 => ram_empty_fb_i_i_4_n_0, + I1 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(2), + I2 => Q(2), + I3 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(3), + I4 => Q(3), + I5 => ram_empty_fb_i_i_5_n_0, + O => ram_empty_fb_i_i_2_n_0 + ); +ram_empty_fb_i_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFBEFFFFBE" + ) + port map ( + I0 => ram_empty_fb_i_i_6_n_0, + I1 => rd_pntr_plus1(3), + I2 => Q(3), + I3 => rd_pntr_plus1(2), + I4 => Q(2), + I5 => ram_empty_fb_i_i_7_n_0, + O => ram_empty_fb_i_i_3_n_0 + ); +ram_empty_fb_i_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"6FF6" + ) + port map ( + I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0), + I1 => Q(0), + I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1), + I3 => Q(1), + O => ram_empty_fb_i_i_4_n_0 + ); +ram_empty_fb_i_i_5: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF6FF6" + ) + port map ( + I0 => Q(6), + I1 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(6), + I2 => Q(7), + I3 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(7), + I4 => ram_empty_fb_i_i_8_n_0, + O => ram_empty_fb_i_i_5_n_0 + ); +ram_empty_fb_i_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"6FF6" + ) + port map ( + I0 => rd_pntr_plus1(1), + I1 => Q(1), + I2 => rd_pntr_plus1(0), + I3 => Q(0), + O => ram_empty_fb_i_i_6_n_0 + ); +ram_empty_fb_i_i_7: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF6FF6" + ) + port map ( + I0 => Q(5), + I1 => rd_pntr_plus1(5), + I2 => Q(4), + I3 => rd_pntr_plus1(4), + I4 => ram_empty_fb_i_i_9_n_0, + O => ram_empty_fb_i_i_7_n_0 + ); +ram_empty_fb_i_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"6FF6" + ) + port map ( + I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(5), + I1 => Q(5), + I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(4), + I3 => Q(4), + O => ram_empty_fb_i_i_8_n_0 + ); +ram_empty_fb_i_i_9: unisim.vcomponents.LUT4 + generic map( + INIT => X"6FF6" + ) + port map ( + I0 => rd_pntr_plus1(6), + I1 => Q(6), + I2 => rd_pntr_plus1(7), + I3 => Q(7), + O => ram_empty_fb_i_i_9_n_0 + ); +ram_full_fb_i_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"00F0F0F000200020" + ) + port map ( + I0 => ram_full_i_reg_0, + I1 => ram_full_fb_i_i_3_n_0, + I2 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I3 => ram_empty_fb_i_reg_0, + I4 => ram_empty_fb_i_i_2_n_0, + I5 => ram_full_fb_i_reg, + O => ram_full_i_reg + ); +ram_full_fb_i_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFBEFFFFBE" + ) + port map ( + I0 => ram_full_fb_i_i_5_n_0, + I1 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1), + I2 => \gcc0.gc0.count_reg[7]\(1), + I3 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0), + I4 => \gcc0.gc0.count_reg[7]\(0), + I5 => ram_full_fb_i_i_6_n_0, + O => ram_full_fb_i_i_3_n_0 + ); +ram_full_fb_i_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"6FF6" + ) + port map ( + I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(2), + I1 => \gcc0.gc0.count_reg[7]\(2), + I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(3), + I3 => \gcc0.gc0.count_reg[7]\(3), + O => ram_full_fb_i_i_5_n_0 + ); +ram_full_fb_i_i_6: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF6FF6" + ) + port map ( + I0 => \gcc0.gc0.count_reg[7]\(5), + I1 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(5), + I2 => \gcc0.gc0.count_reg[7]\(4), + I3 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(4), + I4 => ram_full_fb_i_i_7_n_0, + O => ram_full_fb_i_i_6_n_0 + ); +ram_full_fb_i_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"6FF6" + ) + port map ( + I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(7), + I1 => \gcc0.gc0.count_reg[7]\(7), + I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(6), + I3 => \gcc0.gc0.count_reg[7]\(6), + O => ram_full_fb_i_i_7_n_0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_rd_bin_cntr__parameterized0\ is + port ( + Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_stream_rst : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_rd_bin_cntr__parameterized0\ : entity is "rd_bin_cntr"; +end \Arty_Z7_20_axi_vdma_0_0_rd_bin_cntr__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_rd_bin_cntr__parameterized0\ is + signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal plusOp : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal rd_pntr_plus2 : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \gc1.count[0]_i_1\ : label is "soft_lutpair176"; + attribute SOFT_HLUTNM of \gc1.count[2]_i_2\ : label is "soft_lutpair176"; +begin + Q(2 downto 0) <= \^q\(2 downto 0); +\gc1.count[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => rd_pntr_plus2(0), + O => plusOp(0) + ); +\gc1.count[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => rd_pntr_plus2(0), + I1 => rd_pntr_plus2(1), + O => plusOp(1) + ); +\gc1.count[2]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => rd_pntr_plus2(0), + I1 => rd_pntr_plus2(1), + I2 => rd_pntr_plus2(2), + O => plusOp(2) + ); +\gc1.count_d1_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => rd_pntr_plus2(0), + Q => \^q\(0), + S => sig_stream_rst + ); +\gc1.count_d1_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => rd_pntr_plus2(1), + Q => \^q\(1), + R => sig_stream_rst + ); +\gc1.count_d1_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => rd_pntr_plus2(2), + Q => \^q\(2), + R => sig_stream_rst + ); +\gc1.count_d2_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \^q\(0), + Q => \gpr1.dout_i_reg[1]\(0), + R => sig_stream_rst + ); +\gc1.count_d2_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \^q\(1), + Q => \gpr1.dout_i_reg[1]\(1), + R => sig_stream_rst + ); +\gc1.count_d2_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \^q\(2), + Q => \gpr1.dout_i_reg[1]\(2), + R => sig_stream_rst + ); +\gc1.count_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => plusOp(0), + Q => rd_pntr_plus2(0), + R => sig_stream_rst + ); +\gc1.count_reg[1]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => plusOp(1), + Q => rd_pntr_plus2(1), + S => sig_stream_rst + ); +\gc1.count_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => plusOp(2), + Q => rd_pntr_plus2(2), + R => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_rd_fwft is + port ( + \out\ : out STD_LOGIC; + hold_ff_q_reg : out STD_LOGIC; + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_data_fifo_dvalid : out STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + hold_ff_q_reg_0 : in STD_LOGIC; + sig_s_ready_out_reg : in STD_LOGIC; + ram_empty_fb_i_reg : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_rd_fwft : entity is "rd_fwft"; +end Arty_Z7_20_axi_vdma_0_0_rd_fwft; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_rd_fwft is + signal aempty_fwft_fb_i : STD_LOGIC; + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true; + signal aempty_fwft_i : STD_LOGIC; + attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true; + signal \aempty_fwft_i0__6\ : STD_LOGIC; + signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true; + signal empty_fwft_fb_i : STD_LOGIC; + attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true; + signal empty_fwft_fb_o_i : STD_LOGIC; + attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true; + signal empty_fwft_fb_o_i_reg0 : STD_LOGIC; + signal empty_fwft_i : STD_LOGIC; + attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true; + signal \empty_fwft_i0__1\ : STD_LOGIC; + signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \sig_pop_data_fifo__0\ : STD_LOGIC; + signal user_valid : STD_LOGIC; + attribute DONT_TOUCH of user_valid : signal is std.standard.true; + attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of aempty_fwft_fb_i_reg : label is "yes"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no"; + attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true; + attribute KEEP of aempty_fwft_i_reg : label is "yes"; + attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no"; + attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true; + attribute KEEP of empty_fwft_fb_i_reg : label is "yes"; + attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no"; + attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true; + attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes"; + attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no"; + attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true; + attribute KEEP of empty_fwft_i_reg : label is "yes"; + attribute equivalent_register_removal of empty_fwft_i_reg : label is "no"; + attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true; + attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes"; + attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no"; + attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true; + attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes"; + attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no"; + attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true; + attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes"; + attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no"; +begin + \out\ <= user_valid; +\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"A8FF0000FFFFFFFF" + ) + port map ( + I0 => sig_s_ready_out_reg, + I1 => hold_ff_q_reg_0, + I2 => user_valid, + I3 => curr_fwft_state(0), + I4 => curr_fwft_state(1), + I5 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ + ); +aempty_fwft_fb_i_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"EEFD8000" + ) + port map ( + I0 => curr_fwft_state(0), + I1 => ram_empty_fb_i_reg, + I2 => \sig_pop_data_fifo__0\, + I3 => curr_fwft_state(1), + I4 => aempty_fwft_fb_i, + O => \aempty_fwft_i0__6\ + ); +aempty_fwft_fb_i_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"E0" + ) + port map ( + I0 => user_valid, + I1 => hold_ff_q_reg_0, + I2 => sig_s_ready_out_reg, + O => \sig_pop_data_fifo__0\ + ); +aempty_fwft_fb_i_reg: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \aempty_fwft_i0__6\, + Q => aempty_fwft_fb_i, + S => sig_stream_rst + ); +aempty_fwft_i_reg: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \aempty_fwft_i0__6\, + Q => aempty_fwft_i, + S => sig_stream_rst + ); +\empty_fwft_fb_i_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF00FF00A80000" + ) + port map ( + I0 => sig_s_ready_out_reg, + I1 => hold_ff_q_reg_0, + I2 => user_valid, + I3 => curr_fwft_state(1), + I4 => curr_fwft_state(0), + I5 => empty_fwft_fb_i, + O => \empty_fwft_i0__1\ + ); +empty_fwft_fb_i_reg: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \empty_fwft_i0__1\, + Q => empty_fwft_fb_i, + S => sig_stream_rst + ); +\empty_fwft_fb_o_i_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF00FF00A80000" + ) + port map ( + I0 => sig_s_ready_out_reg, + I1 => hold_ff_q_reg_0, + I2 => user_valid, + I3 => curr_fwft_state(1), + I4 => curr_fwft_state(0), + I5 => empty_fwft_fb_o_i, + O => empty_fwft_fb_o_i_reg0 + ); +empty_fwft_fb_o_i_reg: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => empty_fwft_fb_o_i_reg0, + Q => empty_fwft_fb_o_i, + S => sig_stream_rst + ); +empty_fwft_i_reg: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \empty_fwft_i0__1\, + Q => empty_fwft_i, + S => sig_stream_rst + ); +\gc1.count_d1[7]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000A8FFFFFF" + ) + port map ( + I0 => sig_s_ready_out_reg, + I1 => hold_ff_q_reg_0, + I2 => user_valid, + I3 => curr_fwft_state(0), + I4 => curr_fwft_state(1), + I5 => ram_empty_fb_i_reg, + O => E(0) + ); +\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ABFFAAAA" + ) + port map ( + I0 => curr_fwft_state(1), + I1 => user_valid, + I2 => hold_ff_q_reg_0, + I3 => sig_s_ready_out_reg, + I4 => curr_fwft_state(0), + O => next_fwft_state(0) + ); +\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"222A0000FFFFFFFF" + ) + port map ( + I0 => curr_fwft_state(1), + I1 => sig_s_ready_out_reg, + I2 => hold_ff_q_reg_0, + I3 => user_valid, + I4 => curr_fwft_state(0), + I5 => ram_empty_fb_i_reg, + O => next_fwft_state(1) + ); +\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => next_fwft_state(0), + Q => curr_fwft_state(0), + R => sig_stream_rst + ); +\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => next_fwft_state(1), + Q => curr_fwft_state(1), + R => sig_stream_rst + ); +\gpregsm1.user_valid_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => next_fwft_state(0), + Q => user_valid, + R => sig_stream_rst + ); +hold_ff_q_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"00A8" + ) + port map ( + I0 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I1 => user_valid, + I2 => hold_ff_q_reg_0, + I3 => sig_s_ready_out_reg, + O => hold_ff_q_reg + ); +sig_m_valid_dup_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => hold_ff_q_reg_0, + I1 => user_valid, + O => sig_data_fifo_dvalid + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_rd_fwft_34 is + port ( + \out\ : out STD_LOGIC; + hold_ff_q_reg : out STD_LOGIC; + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC; + \gc1.count_reg[7]\ : out STD_LOGIC; + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0\ : out STD_LOGIC; + \sig_user_skid_reg_reg[0]\ : out STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + hold_ff_q : in STD_LOGIC; + ram_empty_fb_i_reg : in STD_LOGIC; + lsig_cmd_loaded : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_rd_fwft_34 : entity is "rd_fwft"; +end Arty_Z7_20_axi_vdma_0_0_rd_fwft_34; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_rd_fwft_34 is + signal aempty_fwft_fb_i : STD_LOGIC; + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true; + signal \aempty_fwft_fb_i_i_1__0_n_0\ : STD_LOGIC; + signal aempty_fwft_i : STD_LOGIC; + attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true; + signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true; + signal empty_fwft_fb_i : STD_LOGIC; + attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true; + signal empty_fwft_fb_i_i_1_n_0 : STD_LOGIC; + signal empty_fwft_fb_o_i : STD_LOGIC; + attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true; + signal empty_fwft_fb_o_i_reg0 : STD_LOGIC; + signal empty_fwft_i : STD_LOGIC; + attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true; + signal \^gc1.count_reg[7]\ : STD_LOGIC; + signal \gpregsm1.curr_fwft_state[1]_i_1__0_n_0\ : STD_LOGIC; + signal next_fwft_state : STD_LOGIC_VECTOR ( 0 to 0 ); + signal user_valid : STD_LOGIC; + attribute DONT_TOUCH of user_valid : signal is std.standard.true; + attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of aempty_fwft_fb_i_reg : label is "yes"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no"; + attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true; + attribute KEEP of aempty_fwft_i_reg : label is "yes"; + attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no"; + attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true; + attribute KEEP of empty_fwft_fb_i_reg : label is "yes"; + attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no"; + attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true; + attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes"; + attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no"; + attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true; + attribute KEEP of empty_fwft_i_reg : label is "yes"; + attribute equivalent_register_removal of empty_fwft_i_reg : label is "no"; + attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true; + attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes"; + attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no"; + attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true; + attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes"; + attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no"; + attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true; + attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes"; + attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no"; +begin + \gc1.count_reg[7]\ <= \^gc1.count_reg[7]\; + \out\ <= user_valid; +\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^gc1.count_reg[7]\, + I1 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ + ); +\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_3__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"70FF" + ) + port map ( + I0 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, + I1 => curr_fwft_state(0), + I2 => curr_fwft_state(1), + I3 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0\ + ); +\aempty_fwft_fb_i_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EB00EF80FFFFFFFF" + ) + port map ( + I0 => ram_empty_fb_i_reg, + I1 => curr_fwft_state(0), + I2 => curr_fwft_state(1), + I3 => aempty_fwft_fb_i, + I4 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, + I5 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + O => \aempty_fwft_fb_i_i_1__0_n_0\ + ); +aempty_fwft_fb_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \aempty_fwft_fb_i_i_1__0_n_0\, + Q => aempty_fwft_fb_i, + R => '0' + ); +aempty_fwft_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \aempty_fwft_fb_i_i_1__0_n_0\, + Q => aempty_fwft_i, + R => '0' + ); +empty_fwft_fb_i_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"F333F7F3" + ) + port map ( + I0 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, + I1 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I2 => empty_fwft_fb_i, + I3 => curr_fwft_state(0), + I4 => curr_fwft_state(1), + O => empty_fwft_fb_i_i_1_n_0 + ); +empty_fwft_fb_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => empty_fwft_fb_i_i_1_n_0, + Q => empty_fwft_fb_i, + R => '0' + ); +empty_fwft_fb_o_i_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"F310" + ) + port map ( + I0 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, + I1 => curr_fwft_state(1), + I2 => curr_fwft_state(0), + I3 => empty_fwft_fb_o_i, + O => empty_fwft_fb_o_i_reg0 + ); +empty_fwft_fb_o_i_reg: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => empty_fwft_fb_o_i_reg0, + Q => empty_fwft_fb_o_i, + S => SR(0) + ); +empty_fwft_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => empty_fwft_fb_i_i_1_n_0, + Q => empty_fwft_i, + R => '0' + ); +\gc1.count_d1[7]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"1555" + ) + port map ( + I0 => ram_empty_fb_i_reg, + I1 => curr_fwft_state(1), + I2 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, + I3 => curr_fwft_state(0), + O => \^gc1.count_reg[7]\ + ); +\gf36e1_inst.sngfifo36e1_i_22\: unisim.vcomponents.LUT3 + generic map( + INIT => X"1F" + ) + port map ( + I0 => hold_ff_q, + I1 => user_valid, + I2 => lsig_cmd_loaded, + O => \sig_user_skid_reg_reg[0]\ + ); +\gpregsm1.curr_fwft_state[0]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"F8" + ) + port map ( + I0 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, + I1 => curr_fwft_state(0), + I2 => curr_fwft_state(1), + O => next_fwft_state(0) + ); +\gpregsm1.curr_fwft_state[1]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"80FF" + ) + port map ( + I0 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, + I1 => curr_fwft_state(0), + I2 => curr_fwft_state(1), + I3 => ram_empty_fb_i_reg, + O => \gpregsm1.curr_fwft_state[1]_i_1__0_n_0\ + ); +\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => next_fwft_state(0), + Q => curr_fwft_state(0), + R => SR(0) + ); +\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \gpregsm1.curr_fwft_state[1]_i_1__0_n_0\, + Q => curr_fwft_state(1), + R => SR(0) + ); +\gpregsm1.user_valid_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => next_fwft_state(0), + Q => user_valid, + R => SR(0) + ); +\hold_ff_q_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8880" + ) + port map ( + I0 => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, + I1 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I2 => hold_ff_q, + I3 => user_valid, + O => hold_ff_q_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_rd_handshaking_flags__parameterized0\ is + port ( + \gv.ram_valid_d1_reg_0\ : out STD_LOGIC; + hold_ff_q_reg : out STD_LOGIC; + sig_sf2pcc_xfer_valid : out STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + p_32_out : in STD_LOGIC; + hold_ff_q : in STD_LOGIC; + \out\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_rd_handshaking_flags__parameterized0\ : entity is "rd_handshaking_flags"; +end \Arty_Z7_20_axi_vdma_0_0_rd_handshaking_flags__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_rd_handshaking_flags__parameterized0\ is + signal \gv.ram_valid_d1_i_1_n_0\ : STD_LOGIC; + signal \^gv.ram_valid_d1_reg_0\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \gv.ram_valid_d1_i_1\ : label is "soft_lutpair174"; + attribute SOFT_HLUTNM of \hold_ff_q_i_1__0\ : label is "soft_lutpair174"; +begin + \gv.ram_valid_d1_reg_0\ <= \^gv.ram_valid_d1_reg_0\; +\FSM_sequential_sig_csm_state[0]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => hold_ff_q, + I1 => \^gv.ram_valid_d1_reg_0\, + O => sig_sf2pcc_xfer_valid + ); +\gv.ram_valid_d1_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00F1" + ) + port map ( + I0 => \^gv.ram_valid_d1_reg_0\, + I1 => hold_ff_q, + I2 => p_32_out, + I3 => \out\, + O => \gv.ram_valid_d1_i_1_n_0\ + ); +\gv.ram_valid_d1_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \gv.ram_valid_d1_i_1_n_0\, + Q => \^gv.ram_valid_d1_reg_0\, + R => sig_stream_rst + ); +\hold_ff_q_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2220" + ) + port map ( + I0 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I1 => p_32_out, + I2 => hold_ff_q, + I3 => \^gv.ram_valid_d1_reg_0\, + O => hold_ff_q_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_rd_status_flags_ss is + port ( + \out\ : out STD_LOGIC; + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + \ram_empty_i0__3\ : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_rd_status_flags_ss : entity is "rd_status_flags_ss"; +end Arty_Z7_20_axi_vdma_0_0_rd_status_flags_ss; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_rd_status_flags_ss is + signal ram_empty_fb_i : STD_LOGIC; + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true; + signal ram_empty_i : STD_LOGIC; + attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true; + attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of ram_empty_fb_i_reg : label is "yes"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no"; + attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true; + attribute KEEP of ram_empty_i_reg : label is "yes"; + attribute equivalent_register_removal of ram_empty_i_reg : label is "no"; +begin + \out\ <= ram_empty_fb_i; +\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"4F" + ) + port map ( + I0 => ram_empty_fb_i, + I1 => E(0), + I2 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ + ); +ram_empty_fb_i_reg: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \ram_empty_i0__3\, + Q => ram_empty_fb_i, + S => sig_stream_rst + ); +ram_empty_i_reg: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \ram_empty_i0__3\, + Q => ram_empty_i, + S => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_rd_status_flags_ss_35 is + port ( + \out\ : out STD_LOGIC; + ram_empty_fb_i_reg_0 : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_rd_status_flags_ss_35 : entity is "rd_status_flags_ss"; +end Arty_Z7_20_axi_vdma_0_0_rd_status_flags_ss_35; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_rd_status_flags_ss_35 is + signal ram_empty_fb_i : STD_LOGIC; + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true; + signal ram_empty_i : STD_LOGIC; + attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true; + attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of ram_empty_fb_i_reg : label is "yes"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no"; + attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true; + attribute KEEP of ram_empty_i_reg : label is "yes"; + attribute equivalent_register_removal of ram_empty_i_reg : label is "no"; +begin + \out\ <= ram_empty_fb_i; +ram_empty_fb_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => ram_empty_fb_i_reg_0, + Q => ram_empty_fb_i, + R => '0' + ); +ram_empty_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => ram_empty_fb_i_reg_0, + Q => ram_empty_i, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_rd_status_flags_ss__parameterized0\ is + port ( + \out\ : out STD_LOGIC; + \gpr1.dout_i_reg[10]\ : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \gc1.count_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_stream_rst : in STD_LOGIC; + \ram_empty_i0__3\ : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + p_32_out : in STD_LOGIC; + hold_ff_q : in STD_LOGIC; + \gv.ram_valid_d1_reg\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_rd_status_flags_ss__parameterized0\ : entity is "rd_status_flags_ss"; +end \Arty_Z7_20_axi_vdma_0_0_rd_status_flags_ss__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_rd_status_flags_ss__parameterized0\ is + signal ram_empty_fb_i : STD_LOGIC; + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true; + signal ram_empty_i : STD_LOGIC; + attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true; + attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of ram_empty_fb_i_reg : label is "yes"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no"; + attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true; + attribute KEEP of ram_empty_i_reg : label is "yes"; + attribute equivalent_register_removal of ram_empty_i_reg : label is "no"; +begin + \gpr1.dout_i_reg[10]\ <= ram_empty_i; + \out\ <= ram_empty_fb_i; +\gc1.count[2]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000EF01" + ) + port map ( + I0 => \gv.ram_valid_d1_reg\, + I1 => hold_ff_q, + I2 => ram_empty_i, + I3 => p_32_out, + I4 => ram_empty_fb_i, + O => \gc1.count_reg[2]\(0) + ); +\gpr1.dout_i[10]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000AAA3" + ) + port map ( + I0 => p_32_out, + I1 => ram_empty_i, + I2 => hold_ff_q, + I3 => \gv.ram_valid_d1_reg\, + I4 => ram_empty_fb_i, + O => E(0) + ); +ram_empty_fb_i_reg: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \ram_empty_i0__3\, + Q => ram_empty_fb_i, + S => sig_stream_rst + ); +ram_empty_i_reg: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \ram_empty_i0__3\, + Q => ram_empty_i, + S => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_reset_builtin is + port ( + RST : out STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC; + sig_reset_reg : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_reset_builtin : entity is "reset_builtin"; +end Arty_Z7_20_axi_vdma_0_0_reset_builtin; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_reset_builtin is + signal power_on_rd_rst : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute async_reg : string; + attribute async_reg of power_on_rd_rst : signal is "true"; + attribute msgon : string; + attribute msgon of power_on_rd_rst : signal is "true"; + signal power_on_wr_rst : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute async_reg of power_on_wr_rst : signal is "true"; + attribute msgon of power_on_wr_rst : signal is "true"; + signal rd_rst_reg1 : STD_LOGIC; + attribute async_reg of rd_rst_reg1 : signal is "true"; + attribute msgon of rd_rst_reg1 : signal is "true"; + signal rd_rst_reg2 : STD_LOGIC; + attribute async_reg of rd_rst_reg2 : signal is "true"; + attribute msgon of rd_rst_reg2 : signal is "true"; + signal \rsync.ric.wr_rst_fb_reg[1]_srl4_n_0\ : STD_LOGIC; + signal \rsync.ric.wr_rst_fb_reg_n_0_[0]\ : STD_LOGIC; + signal \rsync.ric.wr_rst_reg_i_1_n_0\ : STD_LOGIC; + signal wr_rst_reg : STD_LOGIC; + signal wr_rst_reg1 : STD_LOGIC; + attribute async_reg of wr_rst_reg1 : signal is "true"; + attribute msgon of wr_rst_reg1 : signal is "true"; + signal wr_rst_reg2 : STD_LOGIC; + attribute async_reg of wr_rst_reg2 : signal is "true"; + attribute msgon of wr_rst_reg2 : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \rsync.ric.power_on_rd_rst_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \rsync.ric.power_on_rd_rst_reg[0]\ : label is "yes"; + attribute msgon of \rsync.ric.power_on_rd_rst_reg[0]\ : label is "true"; + attribute ASYNC_REG_boolean of \rsync.ric.power_on_rd_rst_reg[1]\ : label is std.standard.true; + attribute KEEP of \rsync.ric.power_on_rd_rst_reg[1]\ : label is "yes"; + attribute msgon of \rsync.ric.power_on_rd_rst_reg[1]\ : label is "true"; + attribute ASYNC_REG_boolean of \rsync.ric.power_on_rd_rst_reg[2]\ : label is std.standard.true; + attribute KEEP of \rsync.ric.power_on_rd_rst_reg[2]\ : label is "yes"; + attribute msgon of \rsync.ric.power_on_rd_rst_reg[2]\ : label is "true"; + attribute ASYNC_REG_boolean of \rsync.ric.power_on_rd_rst_reg[3]\ : label is std.standard.true; + attribute KEEP of \rsync.ric.power_on_rd_rst_reg[3]\ : label is "yes"; + attribute msgon of \rsync.ric.power_on_rd_rst_reg[3]\ : label is "true"; + attribute ASYNC_REG_boolean of \rsync.ric.power_on_rd_rst_reg[4]\ : label is std.standard.true; + attribute KEEP of \rsync.ric.power_on_rd_rst_reg[4]\ : label is "yes"; + attribute msgon of \rsync.ric.power_on_rd_rst_reg[4]\ : label is "true"; + attribute ASYNC_REG_boolean of \rsync.ric.power_on_rd_rst_reg[5]\ : label is std.standard.true; + attribute KEEP of \rsync.ric.power_on_rd_rst_reg[5]\ : label is "yes"; + attribute msgon of \rsync.ric.power_on_rd_rst_reg[5]\ : label is "true"; + attribute ASYNC_REG_boolean of \rsync.ric.power_on_wr_rst_reg[0]\ : label is std.standard.true; + attribute KEEP of \rsync.ric.power_on_wr_rst_reg[0]\ : label is "yes"; + attribute msgon of \rsync.ric.power_on_wr_rst_reg[0]\ : label is "true"; + attribute ASYNC_REG_boolean of \rsync.ric.power_on_wr_rst_reg[1]\ : label is std.standard.true; + attribute KEEP of \rsync.ric.power_on_wr_rst_reg[1]\ : label is "yes"; + attribute msgon of \rsync.ric.power_on_wr_rst_reg[1]\ : label is "true"; + attribute ASYNC_REG_boolean of \rsync.ric.power_on_wr_rst_reg[2]\ : label is std.standard.true; + attribute KEEP of \rsync.ric.power_on_wr_rst_reg[2]\ : label is "yes"; + attribute msgon of \rsync.ric.power_on_wr_rst_reg[2]\ : label is "true"; + attribute ASYNC_REG_boolean of \rsync.ric.power_on_wr_rst_reg[3]\ : label is std.standard.true; + attribute KEEP of \rsync.ric.power_on_wr_rst_reg[3]\ : label is "yes"; + attribute msgon of \rsync.ric.power_on_wr_rst_reg[3]\ : label is "true"; + attribute ASYNC_REG_boolean of \rsync.ric.power_on_wr_rst_reg[4]\ : label is std.standard.true; + attribute KEEP of \rsync.ric.power_on_wr_rst_reg[4]\ : label is "yes"; + attribute msgon of \rsync.ric.power_on_wr_rst_reg[4]\ : label is "true"; + attribute ASYNC_REG_boolean of \rsync.ric.power_on_wr_rst_reg[5]\ : label is std.standard.true; + attribute KEEP of \rsync.ric.power_on_wr_rst_reg[5]\ : label is "yes"; + attribute msgon of \rsync.ric.power_on_wr_rst_reg[5]\ : label is "true"; + attribute ASYNC_REG_boolean of \rsync.ric.rd_rst_reg1_reg\ : label is std.standard.true; + attribute KEEP of \rsync.ric.rd_rst_reg1_reg\ : label is "yes"; + attribute msgon of \rsync.ric.rd_rst_reg1_reg\ : label is "true"; + attribute ASYNC_REG_boolean of \rsync.ric.rd_rst_reg2_reg\ : label is std.standard.true; + attribute KEEP of \rsync.ric.rd_rst_reg2_reg\ : label is "yes"; + attribute msgon of \rsync.ric.rd_rst_reg2_reg\ : label is "true"; + attribute srl_bus_name : string; + attribute srl_bus_name of \rsync.ric.wr_rst_fb_reg[1]_srl4\ : label is "U0/\GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.wr_rst_fb_reg "; + attribute srl_name : string; + attribute srl_name of \rsync.ric.wr_rst_fb_reg[1]_srl4\ : label is "U0/\GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.wr_rst_fb_reg[1]_srl4 "; + attribute ASYNC_REG_boolean of \rsync.ric.wr_rst_reg1_reg\ : label is std.standard.true; + attribute KEEP of \rsync.ric.wr_rst_reg1_reg\ : label is "yes"; + attribute msgon of \rsync.ric.wr_rst_reg1_reg\ : label is "true"; + attribute ASYNC_REG_boolean of \rsync.ric.wr_rst_reg2_reg\ : label is std.standard.true; + attribute KEEP of \rsync.ric.wr_rst_reg2_reg\ : label is "yes"; + attribute msgon of \rsync.ric.wr_rst_reg2_reg\ : label is "true"; +begin +\gf18e1_inst.sngfifo18e1_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => wr_rst_reg, + I1 => power_on_wr_rst(0), + O => RST + ); +\rsync.ric.power_on_rd_rst_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => power_on_rd_rst(1), + Q => power_on_rd_rst(0), + R => '0' + ); +\rsync.ric.power_on_rd_rst_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => power_on_rd_rst(2), + Q => power_on_rd_rst(1), + R => '0' + ); +\rsync.ric.power_on_rd_rst_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => power_on_rd_rst(3), + Q => power_on_rd_rst(2), + R => '0' + ); +\rsync.ric.power_on_rd_rst_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => power_on_rd_rst(4), + Q => power_on_rd_rst(3), + R => '0' + ); +\rsync.ric.power_on_rd_rst_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => power_on_rd_rst(5), + Q => power_on_rd_rst(4), + R => '0' + ); +\rsync.ric.power_on_rd_rst_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => '0', + Q => power_on_rd_rst(5), + R => '0' + ); +\rsync.ric.power_on_wr_rst_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => power_on_wr_rst(1), + Q => power_on_wr_rst(0), + R => '0' + ); +\rsync.ric.power_on_wr_rst_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => power_on_wr_rst(2), + Q => power_on_wr_rst(1), + R => '0' + ); +\rsync.ric.power_on_wr_rst_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => power_on_wr_rst(3), + Q => power_on_wr_rst(2), + R => '0' + ); +\rsync.ric.power_on_wr_rst_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => power_on_wr_rst(4), + Q => power_on_wr_rst(3), + R => '0' + ); +\rsync.ric.power_on_wr_rst_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => power_on_wr_rst(5), + Q => power_on_wr_rst(4), + R => '0' + ); +\rsync.ric.power_on_wr_rst_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => '0', + Q => power_on_wr_rst(5), + R => '0' + ); +\rsync.ric.rd_rst_reg1_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => '0', + PRE => sig_reset_reg, + Q => rd_rst_reg1 + ); +\rsync.ric.rd_rst_reg2_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => rd_rst_reg1, + PRE => sig_reset_reg, + Q => rd_rst_reg2 + ); +\rsync.ric.wr_rst_fb_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => \rsync.ric.wr_rst_fb_reg[1]_srl4_n_0\, + Q => \rsync.ric.wr_rst_fb_reg_n_0_[0]\, + R => '0' + ); +\rsync.ric.wr_rst_fb_reg[1]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '1', + A2 => '0', + A3 => '0', + CE => '1', + CLK => s_axis_s2mm_aclk, + D => wr_rst_reg, + Q => \rsync.ric.wr_rst_fb_reg[1]_srl4_n_0\ + ); +\rsync.ric.wr_rst_reg1_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => '0', + PRE => sig_reset_reg, + Q => wr_rst_reg1 + ); +\rsync.ric.wr_rst_reg2_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => wr_rst_reg1, + PRE => sig_reset_reg, + Q => wr_rst_reg2 + ); +\rsync.ric.wr_rst_reg_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => wr_rst_reg, + I1 => \rsync.ric.wr_rst_fb_reg_n_0_[0]\, + O => \rsync.ric.wr_rst_reg_i_1_n_0\ + ); +\rsync.ric.wr_rst_reg_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => \rsync.ric.wr_rst_reg_i_1_n_0\, + PRE => wr_rst_reg2, + Q => wr_rst_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_reset_builtin_39 is + port ( + RST : out STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + s_axis_fifo_ainit_nosync_reg : in STD_LOGIC; + m_axis_mm2s_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_reset_builtin_39 : entity is "reset_builtin"; +end Arty_Z7_20_axi_vdma_0_0_reset_builtin_39; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_reset_builtin_39 is + signal power_on_rd_rst : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute async_reg : string; + attribute async_reg of power_on_rd_rst : signal is "true"; + attribute msgon : string; + attribute msgon of power_on_rd_rst : signal is "true"; + signal power_on_wr_rst : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute async_reg of power_on_wr_rst : signal is "true"; + attribute msgon of power_on_wr_rst : signal is "true"; + signal rd_rst_reg : STD_LOGIC; + signal rd_rst_reg1 : STD_LOGIC; + attribute async_reg of rd_rst_reg1 : signal is "true"; + attribute msgon of rd_rst_reg1 : signal is "true"; + signal rd_rst_reg2 : STD_LOGIC; + attribute async_reg of rd_rst_reg2 : signal is "true"; + attribute msgon of rd_rst_reg2 : signal is "true"; + signal \rsync.ric.rd_rst_fb_reg[1]_srl4_n_0\ : STD_LOGIC; + signal \rsync.ric.rd_rst_fb_reg_n_0_[0]\ : STD_LOGIC; + signal \rsync.ric.rd_rst_reg_i_1_n_0\ : STD_LOGIC; + signal wr_rst_reg1 : STD_LOGIC; + attribute async_reg of wr_rst_reg1 : signal is "true"; + attribute msgon of wr_rst_reg1 : signal is "true"; + signal wr_rst_reg2 : STD_LOGIC; + attribute async_reg of wr_rst_reg2 : signal is "true"; + attribute msgon of wr_rst_reg2 : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \rsync.ric.power_on_rd_rst_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \rsync.ric.power_on_rd_rst_reg[0]\ : label is "yes"; + attribute msgon of \rsync.ric.power_on_rd_rst_reg[0]\ : label is "true"; + attribute ASYNC_REG_boolean of \rsync.ric.power_on_rd_rst_reg[1]\ : label is std.standard.true; + attribute KEEP of \rsync.ric.power_on_rd_rst_reg[1]\ : label is "yes"; + attribute msgon of \rsync.ric.power_on_rd_rst_reg[1]\ : label is "true"; + attribute ASYNC_REG_boolean of \rsync.ric.power_on_rd_rst_reg[2]\ : label is std.standard.true; + attribute KEEP of \rsync.ric.power_on_rd_rst_reg[2]\ : label is "yes"; + attribute msgon of \rsync.ric.power_on_rd_rst_reg[2]\ : label is "true"; + attribute ASYNC_REG_boolean of \rsync.ric.power_on_rd_rst_reg[3]\ : label is std.standard.true; + attribute KEEP of \rsync.ric.power_on_rd_rst_reg[3]\ : label is "yes"; + attribute msgon of \rsync.ric.power_on_rd_rst_reg[3]\ : label is "true"; + attribute ASYNC_REG_boolean of \rsync.ric.power_on_rd_rst_reg[4]\ : label is std.standard.true; + attribute KEEP of \rsync.ric.power_on_rd_rst_reg[4]\ : label is "yes"; + attribute msgon of \rsync.ric.power_on_rd_rst_reg[4]\ : label is "true"; + attribute ASYNC_REG_boolean of \rsync.ric.power_on_rd_rst_reg[5]\ : label is std.standard.true; + attribute KEEP of \rsync.ric.power_on_rd_rst_reg[5]\ : label is "yes"; + attribute msgon of \rsync.ric.power_on_rd_rst_reg[5]\ : label is "true"; + attribute ASYNC_REG_boolean of \rsync.ric.power_on_wr_rst_reg[0]\ : label is std.standard.true; + attribute KEEP of \rsync.ric.power_on_wr_rst_reg[0]\ : label is "yes"; + attribute msgon of \rsync.ric.power_on_wr_rst_reg[0]\ : label is "true"; + attribute ASYNC_REG_boolean of \rsync.ric.power_on_wr_rst_reg[1]\ : label is std.standard.true; + attribute KEEP of \rsync.ric.power_on_wr_rst_reg[1]\ : label is "yes"; + attribute msgon of \rsync.ric.power_on_wr_rst_reg[1]\ : label is "true"; + attribute ASYNC_REG_boolean of \rsync.ric.power_on_wr_rst_reg[2]\ : label is std.standard.true; + attribute KEEP of \rsync.ric.power_on_wr_rst_reg[2]\ : label is "yes"; + attribute msgon of \rsync.ric.power_on_wr_rst_reg[2]\ : label is "true"; + attribute ASYNC_REG_boolean of \rsync.ric.power_on_wr_rst_reg[3]\ : label is std.standard.true; + attribute KEEP of \rsync.ric.power_on_wr_rst_reg[3]\ : label is "yes"; + attribute msgon of \rsync.ric.power_on_wr_rst_reg[3]\ : label is "true"; + attribute ASYNC_REG_boolean of \rsync.ric.power_on_wr_rst_reg[4]\ : label is std.standard.true; + attribute KEEP of \rsync.ric.power_on_wr_rst_reg[4]\ : label is "yes"; + attribute msgon of \rsync.ric.power_on_wr_rst_reg[4]\ : label is "true"; + attribute ASYNC_REG_boolean of \rsync.ric.power_on_wr_rst_reg[5]\ : label is std.standard.true; + attribute KEEP of \rsync.ric.power_on_wr_rst_reg[5]\ : label is "yes"; + attribute msgon of \rsync.ric.power_on_wr_rst_reg[5]\ : label is "true"; + attribute srl_bus_name : string; + attribute srl_bus_name of \rsync.ric.rd_rst_fb_reg[1]_srl4\ : label is "U0/\GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.rd_rst_fb_reg "; + attribute srl_name : string; + attribute srl_name of \rsync.ric.rd_rst_fb_reg[1]_srl4\ : label is "U0/\GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.rd_rst_fb_reg[1]_srl4 "; + attribute ASYNC_REG_boolean of \rsync.ric.rd_rst_reg1_reg\ : label is std.standard.true; + attribute KEEP of \rsync.ric.rd_rst_reg1_reg\ : label is "yes"; + attribute msgon of \rsync.ric.rd_rst_reg1_reg\ : label is "true"; + attribute ASYNC_REG_boolean of \rsync.ric.rd_rst_reg2_reg\ : label is std.standard.true; + attribute KEEP of \rsync.ric.rd_rst_reg2_reg\ : label is "yes"; + attribute msgon of \rsync.ric.rd_rst_reg2_reg\ : label is "true"; + attribute ASYNC_REG_boolean of \rsync.ric.wr_rst_reg1_reg\ : label is std.standard.true; + attribute KEEP of \rsync.ric.wr_rst_reg1_reg\ : label is "yes"; + attribute msgon of \rsync.ric.wr_rst_reg1_reg\ : label is "true"; + attribute ASYNC_REG_boolean of \rsync.ric.wr_rst_reg2_reg\ : label is std.standard.true; + attribute KEEP of \rsync.ric.wr_rst_reg2_reg\ : label is "yes"; + attribute msgon of \rsync.ric.wr_rst_reg2_reg\ : label is "true"; +begin +\gf36e1_inst.sngfifo36e1_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => rd_rst_reg, + I1 => power_on_rd_rst(0), + O => RST + ); +\rsync.ric.power_on_rd_rst_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => power_on_rd_rst(1), + Q => power_on_rd_rst(0), + R => '0' + ); +\rsync.ric.power_on_rd_rst_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => power_on_rd_rst(2), + Q => power_on_rd_rst(1), + R => '0' + ); +\rsync.ric.power_on_rd_rst_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => power_on_rd_rst(3), + Q => power_on_rd_rst(2), + R => '0' + ); +\rsync.ric.power_on_rd_rst_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => power_on_rd_rst(4), + Q => power_on_rd_rst(3), + R => '0' + ); +\rsync.ric.power_on_rd_rst_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => power_on_rd_rst(5), + Q => power_on_rd_rst(4), + R => '0' + ); +\rsync.ric.power_on_rd_rst_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => '0', + Q => power_on_rd_rst(5), + R => '0' + ); +\rsync.ric.power_on_wr_rst_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => power_on_wr_rst(1), + Q => power_on_wr_rst(0), + R => '0' + ); +\rsync.ric.power_on_wr_rst_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => power_on_wr_rst(2), + Q => power_on_wr_rst(1), + R => '0' + ); +\rsync.ric.power_on_wr_rst_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => power_on_wr_rst(3), + Q => power_on_wr_rst(2), + R => '0' + ); +\rsync.ric.power_on_wr_rst_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => power_on_wr_rst(4), + Q => power_on_wr_rst(3), + R => '0' + ); +\rsync.ric.power_on_wr_rst_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => power_on_wr_rst(5), + Q => power_on_wr_rst(4), + R => '0' + ); +\rsync.ric.power_on_wr_rst_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => '0', + Q => power_on_wr_rst(5), + R => '0' + ); +\rsync.ric.rd_rst_fb_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => \rsync.ric.rd_rst_fb_reg[1]_srl4_n_0\, + Q => \rsync.ric.rd_rst_fb_reg_n_0_[0]\, + R => '0' + ); +\rsync.ric.rd_rst_fb_reg[1]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '1', + A2 => '0', + A3 => '0', + CE => '1', + CLK => m_axis_mm2s_aclk, + D => rd_rst_reg, + Q => \rsync.ric.rd_rst_fb_reg[1]_srl4_n_0\ + ); +\rsync.ric.rd_rst_reg1_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => '0', + PRE => s_axis_fifo_ainit_nosync_reg, + Q => rd_rst_reg1 + ); +\rsync.ric.rd_rst_reg2_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => rd_rst_reg1, + PRE => s_axis_fifo_ainit_nosync_reg, + Q => rd_rst_reg2 + ); +\rsync.ric.rd_rst_reg_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => rd_rst_reg, + I1 => \rsync.ric.rd_rst_fb_reg_n_0_[0]\, + O => \rsync.ric.rd_rst_reg_i_1_n_0\ + ); +\rsync.ric.rd_rst_reg_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => \rsync.ric.rd_rst_reg_i_1_n_0\, + PRE => rd_rst_reg2, + Q => rd_rst_reg + ); +\rsync.ric.wr_rst_reg1_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => '0', + PRE => s_axis_fifo_ainit_nosync_reg, + Q => wr_rst_reg1 + ); +\rsync.ric.wr_rst_reg2_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wr_rst_reg1, + PRE => s_axis_fifo_ainit_nosync_reg, + Q => wr_rst_reg2 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_updn_cntr is + port ( + sig_ok_to_post_rd_addr_reg : out STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_posted_to_axi_2_reg : in STD_LOGIC; + ram_empty_fb_i_reg : in STD_LOGIC; + \sig_token_cntr_reg[0]\ : in STD_LOGIC; + \sig_token_cntr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + sig_posted_to_axi_2_reg_0 : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + ram_full_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_updn_cntr : entity is "updn_cntr"; +end Arty_Z7_20_axi_vdma_0_0_updn_cntr; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_updn_cntr is + signal \count[0]_i_1_n_0\ : STD_LOGIC; + signal \count[4]_i_2_n_0\ : STD_LOGIC; + signal \count[4]_i_3_n_0\ : STD_LOGIC; + signal \count[4]_i_4_n_0\ : STD_LOGIC; + signal \count[4]_i_5_n_0\ : STD_LOGIC; + signal \count[4]_i_6_n_0\ : STD_LOGIC; + signal \count[7]_i_3_n_0\ : STD_LOGIC; + signal \count[7]_i_4_n_0\ : STD_LOGIC; + signal \count[7]_i_5_n_0\ : STD_LOGIC; + signal \count_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \count_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \count_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \count_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \count_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \count_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \count_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \count_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \count_reg[7]_i_2_n_2\ : STD_LOGIC; + signal \count_reg[7]_i_2_n_3\ : STD_LOGIC; + signal \count_reg[7]_i_2_n_5\ : STD_LOGIC; + signal \count_reg[7]_i_2_n_6\ : STD_LOGIC; + signal \count_reg[7]_i_2_n_7\ : STD_LOGIC; + signal \count_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 5 ); + signal \count_reg_n_0_[0]\ : STD_LOGIC; + signal \count_reg_n_0_[1]\ : STD_LOGIC; + signal \count_reg_n_0_[2]\ : STD_LOGIC; + signal \count_reg_n_0_[3]\ : STD_LOGIC; + signal \count_reg_n_0_[4]\ : STD_LOGIC; + signal sig_ok_to_post_rd_addr0 : STD_LOGIC; + signal sig_ok_to_post_rd_addr_i_3_n_0 : STD_LOGIC; + signal \NLW_count_reg[7]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_count_reg[7]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute METHODOLOGY_DRC_VIOS : string; + attribute METHODOLOGY_DRC_VIOS of \count_reg[4]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \count_reg[7]_i_2\ : label is "{SYNTH-8 {cell *THIS*}}"; +begin +\count[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \count_reg_n_0_[0]\, + O => \count[0]_i_1_n_0\ + ); +\count[4]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \count_reg_n_0_[1]\, + O => \count[4]_i_2_n_0\ + ); +\count[4]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \count_reg_n_0_[3]\, + I1 => \count_reg_n_0_[4]\, + O => \count[4]_i_3_n_0\ + ); +\count[4]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \count_reg_n_0_[2]\, + I1 => \count_reg_n_0_[3]\, + O => \count[4]_i_4_n_0\ + ); +\count[4]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \count_reg_n_0_[1]\, + I1 => \count_reg_n_0_[2]\, + O => \count[4]_i_5_n_0\ + ); +\count[4]_i_6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \count_reg_n_0_[1]\, + I1 => ram_empty_fb_i_reg, + O => \count[4]_i_6_n_0\ + ); +\count[7]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \count_reg__0\(6), + I1 => \count_reg__0\(7), + O => \count[7]_i_3_n_0\ + ); +\count[7]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \count_reg__0\(5), + I1 => \count_reg__0\(6), + O => \count[7]_i_4_n_0\ + ); +\count[7]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \count_reg_n_0_[4]\, + I1 => \count_reg__0\(5), + O => \count[7]_i_5_n_0\ + ); +\count_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_full_i_reg(0), + D => \count[0]_i_1_n_0\, + Q => \count_reg_n_0_[0]\, + R => SR(0) + ); +\count_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_full_i_reg(0), + D => \count_reg[4]_i_1_n_7\, + Q => \count_reg_n_0_[1]\, + R => SR(0) + ); +\count_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_full_i_reg(0), + D => \count_reg[4]_i_1_n_6\, + Q => \count_reg_n_0_[2]\, + R => SR(0) + ); +\count_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_full_i_reg(0), + D => \count_reg[4]_i_1_n_5\, + Q => \count_reg_n_0_[3]\, + R => SR(0) + ); +\count_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_full_i_reg(0), + D => \count_reg[4]_i_1_n_4\, + Q => \count_reg_n_0_[4]\, + R => SR(0) + ); +\count_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \count_reg[4]_i_1_n_0\, + CO(2) => \count_reg[4]_i_1_n_1\, + CO(1) => \count_reg[4]_i_1_n_2\, + CO(0) => \count_reg[4]_i_1_n_3\, + CYINIT => \count_reg_n_0_[0]\, + DI(3) => \count_reg_n_0_[3]\, + DI(2) => \count_reg_n_0_[2]\, + DI(1) => \count_reg_n_0_[1]\, + DI(0) => \count[4]_i_2_n_0\, + O(3) => \count_reg[4]_i_1_n_4\, + O(2) => \count_reg[4]_i_1_n_5\, + O(1) => \count_reg[4]_i_1_n_6\, + O(0) => \count_reg[4]_i_1_n_7\, + S(3) => \count[4]_i_3_n_0\, + S(2) => \count[4]_i_4_n_0\, + S(1) => \count[4]_i_5_n_0\, + S(0) => \count[4]_i_6_n_0\ + ); +\count_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_full_i_reg(0), + D => \count_reg[7]_i_2_n_7\, + Q => \count_reg__0\(5), + R => SR(0) + ); +\count_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_full_i_reg(0), + D => \count_reg[7]_i_2_n_6\, + Q => \count_reg__0\(6), + R => SR(0) + ); +\count_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => ram_full_i_reg(0), + D => \count_reg[7]_i_2_n_5\, + Q => \count_reg__0\(7), + R => SR(0) + ); +\count_reg[7]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => \count_reg[4]_i_1_n_0\, + CO(3 downto 2) => \NLW_count_reg[7]_i_2_CO_UNCONNECTED\(3 downto 2), + CO(1) => \count_reg[7]_i_2_n_2\, + CO(0) => \count_reg[7]_i_2_n_3\, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1) => \count_reg__0\(5), + DI(0) => \count_reg_n_0_[4]\, + O(3) => \NLW_count_reg[7]_i_2_O_UNCONNECTED\(3), + O(2) => \count_reg[7]_i_2_n_5\, + O(1) => \count_reg[7]_i_2_n_6\, + O(0) => \count_reg[7]_i_2_n_7\, + S(3) => '0', + S(2) => \count[7]_i_3_n_0\, + S(1) => \count[7]_i_4_n_0\, + S(0) => \count[7]_i_5_n_0\ + ); +sig_ok_to_post_rd_addr_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => sig_ok_to_post_rd_addr0, + I1 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I2 => sig_posted_to_axi_2_reg, + O => sig_ok_to_post_rd_addr_reg + ); +sig_ok_to_post_rd_addr_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000D04D04" + ) + port map ( + I0 => \count_reg__0\(7), + I1 => sig_ok_to_post_rd_addr_i_3_n_0, + I2 => \sig_token_cntr_reg[0]\, + I3 => \sig_token_cntr_reg[3]\(2), + I4 => \sig_token_cntr_reg[3]\(3), + I5 => sig_posted_to_axi_2_reg_0, + O => sig_ok_to_post_rd_addr0 + ); +sig_ok_to_post_rd_addr_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"4513" + ) + port map ( + I0 => \count_reg__0\(6), + I1 => \sig_token_cntr_reg[3]\(0), + I2 => \count_reg__0\(5), + I3 => \sig_token_cntr_reg[3]\(1), + O => sig_ok_to_post_rd_addr_i_3_n_0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_updn_cntr__parameterized0\ is + port ( + sig_ibtt2dre_tready : out STD_LOGIC; + lsig_packer_full : in STD_LOGIC; + ram_full_i_reg : in STD_LOGIC; + ram_full_i_reg_0 : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + ram_full_fb_i_reg : in STD_LOGIC; + sig_clr_dbc_reg_reg : in STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_updn_cntr__parameterized0\ : entity is "updn_cntr"; +end \Arty_Z7_20_axi_vdma_0_0_updn_cntr__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_updn_cntr__parameterized0\ is + signal \count[0]_i_1_n_0\ : STD_LOGIC; + signal \count[1]_i_1_n_0\ : STD_LOGIC; + signal \count[2]_i_1_n_0\ : STD_LOGIC; + signal \count_reg_n_0_[0]\ : STD_LOGIC; + signal \count_reg_n_0_[1]\ : STD_LOGIC; + signal \count_reg_n_0_[2]\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \count[0]_i_1\ : label is "soft_lutpair175"; + attribute SOFT_HLUTNM of \count[1]_i_1\ : label is "soft_lutpair175"; +begin +\count[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2DD2" + ) + port map ( + I0 => sig_clr_dbc_reg_reg, + I1 => ram_full_fb_i_reg, + I2 => E(0), + I3 => \count_reg_n_0_[0]\, + O => \count[0]_i_1_n_0\ + ); +\count[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BDBB4244" + ) + port map ( + I0 => \count_reg_n_0_[0]\, + I1 => E(0), + I2 => ram_full_fb_i_reg, + I3 => sig_clr_dbc_reg_reg, + I4 => \count_reg_n_0_[1]\, + O => \count[1]_i_1_n_0\ + ); +\count[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EFF7EFEF10081010" + ) + port map ( + I0 => \count_reg_n_0_[0]\, + I1 => \count_reg_n_0_[1]\, + I2 => E(0), + I3 => ram_full_fb_i_reg, + I4 => sig_clr_dbc_reg_reg, + I5 => \count_reg_n_0_[2]\, + O => \count[2]_i_1_n_0\ + ); +\count_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \count[0]_i_1_n_0\, + Q => \count_reg_n_0_[0]\, + R => sig_stream_rst + ); +\count_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \count[1]_i_1_n_0\, + Q => \count_reg_n_0_[1]\, + R => sig_stream_rst + ); +\count_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \count[2]_i_1_n_0\, + Q => \count_reg_n_0_[2]\, + R => sig_stream_rst + ); +\sig_data_reg_out[7]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0007007700770077" + ) + port map ( + I0 => lsig_packer_full, + I1 => ram_full_i_reg, + I2 => \count_reg_n_0_[2]\, + I3 => ram_full_i_reg_0, + I4 => \count_reg_n_0_[0]\, + I5 => \count_reg_n_0_[1]\, + O => sig_ibtt2dre_tready + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_wr_bin_cntr is + port ( + ram_full_i_reg : out STD_LOGIC; + \ram_empty_i0__3\ : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 7 downto 0 ); + \out\ : in STD_LOGIC; + lsig_packer_full : in STD_LOGIC; + ram_full_fb_i_reg : in STD_LOGIC; + p_7_out : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + ram_empty_fb_i_reg : in STD_LOGIC; + \gc1.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \gc1.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_wr_bin_cntr : entity is "wr_bin_cntr"; +end Arty_Z7_20_axi_vdma_0_0_wr_bin_cntr; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_wr_bin_cntr is + signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \gcc0.gc0.count[7]_i_2__0_n_0\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1\ : STD_LOGIC; + signal \gwss.wsts/comp1\ : STD_LOGIC; + signal p_12_out : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \plusOp__2\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \ram_empty_fb_i_i_3__0_n_0\ : STD_LOGIC; + signal \ram_empty_fb_i_i_4__0_n_0\ : STD_LOGIC; + signal \ram_empty_fb_i_i_5__0_n_0\ : STD_LOGIC; + signal \ram_full_fb_i_i_4__0_n_0\ : STD_LOGIC; + signal \ram_full_fb_i_i_5__0_n_0\ : STD_LOGIC; + signal \ram_full_fb_i_i_6__0_n_0\ : STD_LOGIC; + signal \ram_full_fb_i_i_7__0_n_0\ : STD_LOGIC; + signal ram_full_fb_i_i_8_n_0 : STD_LOGIC; + signal ram_full_fb_i_i_9_n_0 : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \gcc0.gc0.count[1]_i_1__0\ : label is "soft_lutpair172"; + attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1__0\ : label is "soft_lutpair171"; + attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1__0\ : label is "soft_lutpair171"; + attribute SOFT_HLUTNM of \gcc0.gc0.count[6]_i_1__0\ : label is "soft_lutpair173"; + attribute SOFT_HLUTNM of \gcc0.gc0.count[7]_i_1__0\ : label is "soft_lutpair173"; + attribute SOFT_HLUTNM of ram_full_fb_i_i_9 : label is "soft_lutpair172"; +begin + Q(7 downto 0) <= \^q\(7 downto 0); +\gcc0.gc0.count[0]_i_1__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => p_12_out(0), + O => \plusOp__2\(0) + ); +\gcc0.gc0.count[1]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => p_12_out(0), + I1 => p_12_out(1), + O => \plusOp__2\(1) + ); +\gcc0.gc0.count[2]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => p_12_out(0), + I1 => p_12_out(1), + I2 => p_12_out(2), + O => \plusOp__2\(2) + ); +\gcc0.gc0.count[3]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => p_12_out(1), + I1 => p_12_out(0), + I2 => p_12_out(2), + I3 => p_12_out(3), + O => \plusOp__2\(3) + ); +\gcc0.gc0.count[4]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => p_12_out(2), + I1 => p_12_out(0), + I2 => p_12_out(1), + I3 => p_12_out(3), + I4 => p_12_out(4), + O => \plusOp__2\(4) + ); +\gcc0.gc0.count[5]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFFFFFF80000000" + ) + port map ( + I0 => p_12_out(3), + I1 => p_12_out(1), + I2 => p_12_out(0), + I3 => p_12_out(2), + I4 => p_12_out(4), + I5 => p_12_out(5), + O => \plusOp__2\(5) + ); +\gcc0.gc0.count[6]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \gcc0.gc0.count[7]_i_2__0_n_0\, + I1 => p_12_out(6), + O => \plusOp__2\(6) + ); +\gcc0.gc0.count[7]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \gcc0.gc0.count[7]_i_2__0_n_0\, + I1 => p_12_out(6), + I2 => p_12_out(7), + O => \plusOp__2\(7) + ); +\gcc0.gc0.count[7]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => p_12_out(5), + I1 => p_12_out(3), + I2 => p_12_out(1), + I3 => p_12_out(0), + I4 => p_12_out(2), + I5 => p_12_out(4), + O => \gcc0.gc0.count[7]_i_2__0_n_0\ + ); +\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => p_12_out(0), + Q => \^q\(0), + R => sig_stream_rst + ); +\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => p_12_out(1), + Q => \^q\(1), + R => sig_stream_rst + ); +\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => p_12_out(2), + Q => \^q\(2), + R => sig_stream_rst + ); +\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => p_12_out(3), + Q => \^q\(3), + R => sig_stream_rst + ); +\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => p_12_out(4), + Q => \^q\(4), + R => sig_stream_rst + ); +\gcc0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => p_12_out(5), + Q => \^q\(5), + R => sig_stream_rst + ); +\gcc0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => p_12_out(6), + Q => \^q\(6), + R => sig_stream_rst + ); +\gcc0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => p_12_out(7), + Q => \^q\(7), + R => sig_stream_rst + ); +\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \plusOp__2\(0), + Q => p_12_out(0), + S => sig_stream_rst + ); +\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \plusOp__2\(1), + Q => p_12_out(1), + R => sig_stream_rst + ); +\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \plusOp__2\(2), + Q => p_12_out(2), + R => sig_stream_rst + ); +\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \plusOp__2\(3), + Q => p_12_out(3), + R => sig_stream_rst + ); +\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \plusOp__2\(4), + Q => p_12_out(4), + R => sig_stream_rst + ); +\gcc0.gc0.count_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \plusOp__2\(5), + Q => p_12_out(5), + R => sig_stream_rst + ); +\gcc0.gc0.count_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \plusOp__2\(6), + Q => p_12_out(6), + R => sig_stream_rst + ); +\gcc0.gc0.count_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \plusOp__2\(7), + Q => p_12_out(7), + R => sig_stream_rst + ); +\ram_empty_fb_i_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0FFF0088" + ) + port map ( + I0 => \gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1\, + I1 => p_7_out, + I2 => \gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0\, + I3 => E(0), + I4 => ram_empty_fb_i_reg, + O => \ram_empty_i0__3\ + ); +\ram_empty_fb_i_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000041000041" + ) + port map ( + I0 => \ram_empty_fb_i_i_3__0_n_0\, + I1 => \^q\(6), + I2 => \gc1.count_d1_reg[7]\(6), + I3 => \^q\(7), + I4 => \gc1.count_d1_reg[7]\(7), + I5 => \ram_empty_fb_i_i_4__0_n_0\, + O => \gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1\ + ); +\ram_empty_fb_i_i_3__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6FF6" + ) + port map ( + I0 => \^q\(5), + I1 => \gc1.count_d1_reg[7]\(5), + I2 => \^q\(4), + I3 => \gc1.count_d1_reg[7]\(4), + O => \ram_empty_fb_i_i_3__0_n_0\ + ); +\ram_empty_fb_i_i_4__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF6FF6" + ) + port map ( + I0 => \gc1.count_d1_reg[7]\(2), + I1 => \^q\(2), + I2 => \gc1.count_d1_reg[7]\(3), + I3 => \^q\(3), + I4 => \ram_empty_fb_i_i_5__0_n_0\, + O => \ram_empty_fb_i_i_4__0_n_0\ + ); +\ram_empty_fb_i_i_5__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6FF6" + ) + port map ( + I0 => \^q\(1), + I1 => \gc1.count_d1_reg[7]\(1), + I2 => \^q\(0), + I3 => \gc1.count_d1_reg[7]\(0), + O => \ram_empty_fb_i_i_5__0_n_0\ + ); +\ram_full_fb_i_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"55550000FFFF3000" + ) + port map ( + I0 => \gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0\, + I1 => \out\, + I2 => lsig_packer_full, + I3 => \gwss.wsts/comp1\, + I4 => ram_full_fb_i_reg, + I5 => p_7_out, + O => ram_full_i_reg + ); +\ram_full_fb_i_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000041000041" + ) + port map ( + I0 => \ram_full_fb_i_i_4__0_n_0\, + I1 => \^q\(6), + I2 => \gc1.count_d2_reg[7]\(6), + I3 => \^q\(7), + I4 => \gc1.count_d2_reg[7]\(7), + I5 => \ram_full_fb_i_i_5__0_n_0\, + O => \gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0\ + ); +\ram_full_fb_i_i_3__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000041000041" + ) + port map ( + I0 => \ram_full_fb_i_i_6__0_n_0\, + I1 => p_12_out(6), + I2 => \gc1.count_d2_reg[7]\(6), + I3 => p_12_out(7), + I4 => \gc1.count_d2_reg[7]\(7), + I5 => \ram_full_fb_i_i_7__0_n_0\, + O => \gwss.wsts/comp1\ + ); +\ram_full_fb_i_i_4__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6FF6" + ) + port map ( + I0 => \^q\(5), + I1 => \gc1.count_d2_reg[7]\(5), + I2 => \^q\(4), + I3 => \gc1.count_d2_reg[7]\(4), + O => \ram_full_fb_i_i_4__0_n_0\ + ); +\ram_full_fb_i_i_5__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF6FF6" + ) + port map ( + I0 => \gc1.count_d2_reg[7]\(2), + I1 => \^q\(2), + I2 => \gc1.count_d2_reg[7]\(3), + I3 => \^q\(3), + I4 => ram_full_fb_i_i_8_n_0, + O => \ram_full_fb_i_i_5__0_n_0\ + ); +\ram_full_fb_i_i_6__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6FF6" + ) + port map ( + I0 => p_12_out(5), + I1 => \gc1.count_d2_reg[7]\(5), + I2 => p_12_out(4), + I3 => \gc1.count_d2_reg[7]\(4), + O => \ram_full_fb_i_i_6__0_n_0\ + ); +\ram_full_fb_i_i_7__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF6FF6" + ) + port map ( + I0 => \gc1.count_d2_reg[7]\(2), + I1 => p_12_out(2), + I2 => \gc1.count_d2_reg[7]\(3), + I3 => p_12_out(3), + I4 => ram_full_fb_i_i_9_n_0, + O => \ram_full_fb_i_i_7__0_n_0\ + ); +ram_full_fb_i_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"6FF6" + ) + port map ( + I0 => \^q\(1), + I1 => \gc1.count_d2_reg[7]\(1), + I2 => \^q\(0), + I3 => \gc1.count_d2_reg[7]\(0), + O => ram_full_fb_i_i_8_n_0 + ); +ram_full_fb_i_i_9: unisim.vcomponents.LUT4 + generic map( + INIT => X"6FF6" + ) + port map ( + I0 => p_12_out(1), + I1 => \gc1.count_d2_reg[7]\(1), + I2 => p_12_out(0), + I3 => \gc1.count_d2_reg[7]\(0), + O => ram_full_fb_i_i_9_n_0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_wr_bin_cntr_33 is + port ( + Q : out STD_LOGIC_VECTOR ( 7 downto 0 ); + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_wr_bin_cntr_33 : entity is "wr_bin_cntr"; +end Arty_Z7_20_axi_vdma_0_0_wr_bin_cntr_33; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_wr_bin_cntr_33 is + signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \gcc0.gc0.count[7]_i_2_n_0\ : STD_LOGIC; + signal \plusOp__0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \gcc0.gc0.count[1]_i_1\ : label is "soft_lutpair107"; + attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair107"; + attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair105"; + attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair105"; + attribute SOFT_HLUTNM of \gcc0.gc0.count[6]_i_1\ : label is "soft_lutpair106"; + attribute SOFT_HLUTNM of \gcc0.gc0.count[7]_i_1\ : label is "soft_lutpair106"; +begin + Q(7 downto 0) <= \^q\(7 downto 0); +\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^q\(0), + O => \plusOp__0\(0) + ); +\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^q\(0), + I1 => \^q\(1), + O => \plusOp__0\(1) + ); +\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => \^q\(2), + I1 => \^q\(1), + I2 => \^q\(0), + O => \plusOp__0\(2) + ); +\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => \^q\(3), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => \^q\(2), + O => \plusOp__0\(3) + ); +\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAAAAAA" + ) + port map ( + I0 => \^q\(4), + I1 => \^q\(2), + I2 => \^q\(1), + I3 => \^q\(0), + I4 => \^q\(3), + O => \plusOp__0\(4) + ); +\gcc0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"6AAAAAAAAAAAAAAA" + ) + port map ( + I0 => \^q\(5), + I1 => \^q\(3), + I2 => \^q\(0), + I3 => \^q\(1), + I4 => \^q\(2), + I5 => \^q\(4), + O => \plusOp__0\(5) + ); +\gcc0.gc0.count[6]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^q\(6), + I1 => \gcc0.gc0.count[7]_i_2_n_0\, + O => \plusOp__0\(6) + ); +\gcc0.gc0.count[7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => \^q\(7), + I1 => \gcc0.gc0.count[7]_i_2_n_0\, + I2 => \^q\(6), + O => \plusOp__0\(7) + ); +\gcc0.gc0.count[7]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => \^q\(5), + I1 => \^q\(3), + I2 => \^q\(0), + I3 => \^q\(1), + I4 => \^q\(2), + I5 => \^q\(4), + O => \gcc0.gc0.count[7]_i_2_n_0\ + ); +\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => \^q\(0), + Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(0), + R => SR(0) + ); +\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => \^q\(1), + Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(1), + R => SR(0) + ); +\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => \^q\(2), + Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(2), + R => SR(0) + ); +\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => \^q\(3), + Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(3), + R => SR(0) + ); +\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => \^q\(4), + Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(4), + R => SR(0) + ); +\gcc0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => \^q\(5), + Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(5), + R => SR(0) + ); +\gcc0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => \^q\(6), + Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(6), + R => SR(0) + ); +\gcc0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => \^q\(7), + Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(7), + R => SR(0) + ); +\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => \plusOp__0\(0), + Q => \^q\(0), + S => SR(0) + ); +\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => \plusOp__0\(1), + Q => \^q\(1), + R => SR(0) + ); +\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => \plusOp__0\(2), + Q => \^q\(2), + R => SR(0) + ); +\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => \plusOp__0\(3), + Q => \^q\(3), + R => SR(0) + ); +\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => \plusOp__0\(4), + Q => \^q\(4), + R => SR(0) + ); +\gcc0.gc0.count_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => \plusOp__0\(5), + Q => \^q\(5), + R => SR(0) + ); +\gcc0.gc0.count_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => \plusOp__0\(6), + Q => \^q\(6), + R => SR(0) + ); +\gcc0.gc0.count_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => E(0), + D => \plusOp__0\(7), + Q => \^q\(7), + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_wr_bin_cntr__parameterized0\ is + port ( + ram_full_i_reg : out STD_LOGIC; + \ram_empty_i0__3\ : out STD_LOGIC; + \gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_clr_dbc_reg_reg : in STD_LOGIC; + \out\ : in STD_LOGIC; + \gv.ram_valid_d1_reg\ : in STD_LOGIC; + ram_empty_fb_i_reg : in STD_LOGIC; + \gc1.count_d2_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_stream_rst : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_wr_bin_cntr__parameterized0\ : entity is "wr_bin_cntr"; +end \Arty_Z7_20_axi_vdma_0_0_wr_bin_cntr__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_wr_bin_cntr__parameterized0\ is + signal \gcc0.gc0.count[0]_i_1__1_n_0\ : STD_LOGIC; + signal \gcc0.gc0.count[1]_i_1__1_n_0\ : STD_LOGIC; + signal \gcc0.gc0.count[2]_i_2_n_0\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1\ : STD_LOGIC; + signal \^gpr1.dout_i_reg[1]\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \gwss.wsts/comp1\ : STD_LOGIC; + signal p_12_out : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \gcc0.gc0.count[1]_i_1__1\ : label is "soft_lutpair177"; + attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_2\ : label is "soft_lutpair177"; +begin + \gpr1.dout_i_reg[1]\(2 downto 0) <= \^gpr1.dout_i_reg[1]\(2 downto 0); +\gcc0.gc0.count[0]_i_1__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => p_12_out(0), + O => \gcc0.gc0.count[0]_i_1__1_n_0\ + ); +\gcc0.gc0.count[1]_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => p_12_out(0), + I1 => p_12_out(1), + O => \gcc0.gc0.count[1]_i_1__1_n_0\ + ); +\gcc0.gc0.count[2]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => p_12_out(0), + I1 => p_12_out(1), + I2 => p_12_out(2), + O => \gcc0.gc0.count[2]_i_2_n_0\ + ); +\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => p_12_out(0), + Q => \^gpr1.dout_i_reg[1]\(0), + R => sig_stream_rst + ); +\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => p_12_out(1), + Q => \^gpr1.dout_i_reg[1]\(1), + R => sig_stream_rst + ); +\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => p_12_out(2), + Q => \^gpr1.dout_i_reg[1]\(2), + R => sig_stream_rst + ); +\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \gcc0.gc0.count[0]_i_1__1_n_0\, + Q => p_12_out(0), + S => sig_stream_rst + ); +\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \gcc0.gc0.count[1]_i_1__1_n_0\, + Q => p_12_out(1), + R => sig_stream_rst + ); +\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => E(0), + D => \gcc0.gc0.count[2]_i_2_n_0\, + Q => p_12_out(2), + R => sig_stream_rst + ); +\ram_empty_fb_i_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF0FFFFF88008888" + ) + port map ( + I0 => \gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1\, + I1 => \gv.ram_valid_d1_reg\, + I2 => \gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0\, + I3 => \out\, + I4 => sig_clr_dbc_reg_reg, + I5 => ram_empty_fb_i_reg, + O => \ram_empty_i0__3\ + ); +\ram_empty_fb_i_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^gpr1.dout_i_reg[1]\(1), + I1 => Q(1), + I2 => Q(0), + I3 => \^gpr1.dout_i_reg[1]\(0), + I4 => Q(2), + I5 => \^gpr1.dout_i_reg[1]\(2), + O => \gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1\ + ); +\ram_full_fb_i_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"5500FFC0" + ) + port map ( + I0 => \gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0\, + I1 => sig_clr_dbc_reg_reg, + I2 => \gwss.wsts/comp1\, + I3 => \out\, + I4 => \gv.ram_valid_d1_reg\, + O => ram_full_i_reg + ); +\ram_full_fb_i_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^gpr1.dout_i_reg[1]\(1), + I1 => \gc1.count_d2_reg[2]\(1), + I2 => \gc1.count_d2_reg[2]\(0), + I3 => \^gpr1.dout_i_reg[1]\(0), + I4 => \gc1.count_d2_reg[2]\(2), + I5 => \^gpr1.dout_i_reg[1]\(2), + O => \gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0\ + ); +\ram_full_fb_i_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => p_12_out(1), + I1 => \gc1.count_d2_reg[2]\(1), + I2 => \gc1.count_d2_reg[2]\(0), + I3 => p_12_out(0), + I4 => \gc1.count_d2_reg[2]\(2), + I5 => p_12_out(2), + O => \gwss.wsts/comp1\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_wr_status_flags_ss is + port ( + \out\ : out STD_LOGIC; + \gcc0.gc0.count_d1_reg[7]\ : out STD_LOGIC; + \INCLUDE_PACKING.lsig_packer_full_reg\ : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_stream_rst : in STD_LOGIC; + ram_full_i_reg_0 : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + \lsig_set_packer_full__1\ : in STD_LOGIC; + lsig_packer_full : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_wr_status_flags_ss : entity is "wr_status_flags_ss"; +end Arty_Z7_20_axi_vdma_0_0_wr_status_flags_ss; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_wr_status_flags_ss is + signal ram_afull_fb : STD_LOGIC; + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true; + signal ram_afull_i : STD_LOGIC; + attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true; + signal ram_full_fb_i : STD_LOGIC; + attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true; + signal ram_full_i : STD_LOGIC; + attribute DONT_TOUCH of ram_full_i : signal is std.standard.true; + attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of ram_full_fb_i_reg : label is "yes"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no"; + attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true; + attribute KEEP of ram_full_i_reg : label is "yes"; + attribute equivalent_register_removal of ram_full_i_reg : label is "no"; +begin + \gcc0.gc0.count_d1_reg[7]\ <= ram_full_i; + \out\ <= ram_full_fb_i; +\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => ram_full_i, + I1 => lsig_packer_full, + I2 => ram_full_fb_i, + O => E(0) + ); +\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg[0][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"BA" + ) + port map ( + I0 => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4\, + I1 => ram_full_i, + I2 => lsig_packer_full, + O => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0]\(0) + ); +\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg[1][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"BA" + ) + port map ( + I0 => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3\, + I1 => ram_full_i, + I2 => lsig_packer_full, + O => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0]\(0) + ); +\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg[2][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"BA" + ) + port map ( + I0 => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2\, + I1 => ram_full_i, + I2 => lsig_packer_full, + O => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0]\(0) + ); +\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg[3][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"BA" + ) + port map ( + I0 => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1\, + I1 => ram_full_i, + I2 => lsig_packer_full, + O => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0]\(0) + ); +\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg[4][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"BA" + ) + port map ( + I0 => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0\, + I1 => ram_full_i, + I2 => lsig_packer_full, + O => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0]\(0) + ); +\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg[5][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"BA" + ) + port map ( + I0 => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]\, + I1 => ram_full_i, + I2 => lsig_packer_full, + O => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0]\(0) + ); +\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg[6][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"BA" + ) + port map ( + I0 => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\, + I1 => ram_full_i, + I2 => lsig_packer_full, + O => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0]\(0) + ); +\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg[7][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"BA" + ) + port map ( + I0 => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\, + I1 => ram_full_i, + I2 => lsig_packer_full, + O => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][0]\(0) + ); +\INCLUDE_PACKING.lsig_packer_full_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"EA" + ) + port map ( + I0 => \lsig_set_packer_full__1\, + I1 => lsig_packer_full, + I2 => ram_full_i, + O => \INCLUDE_PACKING.lsig_packer_full_reg\ + ); +i_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => ram_afull_i + ); +i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => ram_afull_fb + ); +ram_full_fb_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => ram_full_i_reg_0, + Q => ram_full_fb_i, + R => sig_stream_rst + ); +ram_full_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => ram_full_i_reg_0, + Q => ram_full_i, + R => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_wr_status_flags_ss_32 is + port ( + \out\ : out STD_LOGIC; + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC; + sig_ok_to_post_rd_addr_reg : out STD_LOGIC; + \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + sig_posted_to_axi_2_reg : in STD_LOGIC; + \sig_token_cntr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_wr_status_flags_ss_32 : entity is "wr_status_flags_ss"; +end Arty_Z7_20_axi_vdma_0_0_wr_status_flags_ss_32; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_wr_status_flags_ss_32 is + signal ram_afull_fb : STD_LOGIC; + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true; + signal ram_afull_i : STD_LOGIC; + attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true; + signal ram_full_fb_i : STD_LOGIC; + attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true; + signal ram_full_i : STD_LOGIC; + attribute DONT_TOUCH of ram_full_i : signal is std.standard.true; + attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of ram_full_fb_i_reg : label is "yes"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no"; + attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true; + attribute KEEP of ram_full_i_reg : label is "yes"; + attribute equivalent_register_removal of ram_full_i_reg : label is "no"; +begin + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ <= ram_full_i; + \out\ <= ram_full_fb_i; +i_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => ram_afull_i + ); +i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => ram_afull_fb + ); +ram_full_fb_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\, + Q => ram_full_fb_i, + R => '0' + ); +ram_full_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\, + Q => ram_full_i, + R => '0' + ); +sig_ok_to_post_rd_addr_i_5: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF00000023" + ) + port map ( + I0 => sig_posted_to_axi_2_reg, + I1 => \sig_token_cntr_reg[3]\(1), + I2 => \sig_token_cntr_reg[3]\(0), + I3 => \sig_token_cntr_reg[3]\(3), + I4 => \sig_token_cntr_reg[3]\(2), + I5 => ram_full_i, + O => sig_ok_to_post_rd_addr_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_wr_status_flags_ss__parameterized0\ is + port ( + \out\ : out STD_LOGIC; + \sig_byte_cntr_reg[0]\ : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_stream_rst : in STD_LOGIC; + sig_clr_dbc_reg_reg : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_clr_dbc_reg_reg_0 : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_wr_status_flags_ss__parameterized0\ : entity is "wr_status_flags_ss"; +end \Arty_Z7_20_axi_vdma_0_0_wr_status_flags_ss__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_wr_status_flags_ss__parameterized0\ is + signal ram_afull_fb : STD_LOGIC; + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true; + signal ram_afull_i : STD_LOGIC; + attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true; + signal ram_full_fb_i : STD_LOGIC; + attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true; + signal ram_full_i : STD_LOGIC; + attribute DONT_TOUCH of ram_full_i : signal is std.standard.true; + attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of ram_full_fb_i_reg : label is "yes"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no"; + attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true; + attribute KEEP of ram_full_i_reg : label is "yes"; + attribute equivalent_register_removal of ram_full_i_reg : label is "no"; +begin + \out\ <= ram_full_fb_i; + \sig_byte_cntr_reg[0]\ <= ram_full_i; +\gcc0.gc0.count[2]_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => sig_clr_dbc_reg_reg_0, + I1 => ram_full_fb_i, + O => E(0) + ); +i_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => ram_afull_i + ); +i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => ram_afull_fb + ); +ram_full_fb_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_clr_dbc_reg_reg, + Q => ram_full_fb_i, + R => sig_stream_rst + ); +ram_full_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_clr_dbc_reg_reg, + Q => ram_full_i, + R => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_genlock_mngr is + port ( + p_45_out : out STD_LOGIC; + \GENLOCK_FOR_MASTER.mstr_reverse_order_reg_0\ : out STD_LOGIC; + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + valid_frame_sync_d2 : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 4 downto 0 ); + num_fstore_minus1 : in STD_LOGIC_VECTOR ( 0 to 0 ); + p_71_out : in STD_LOGIC_VECTOR ( 0 to 0 ); + mm2s_prmry_resetn : in STD_LOGIC; + p_70_out : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_genlock_mngr : entity is "axi_vdma_genlock_mngr"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_genlock_mngr; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_genlock_mngr is + signal \GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.binary_frame_ptr[0]_i_1_n_0\ : STD_LOGIC; + signal \GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg[1]_inv_n_0\ : STD_LOGIC; + signal \GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg_n_0_[0]\ : STD_LOGIC; + signal \GENLOCK_FOR_MASTER.frame_ptr_out[2]_i_1_n_0\ : STD_LOGIC; + signal \GENLOCK_FOR_MASTER.mstr_reverse_order_i_1_n_0\ : STD_LOGIC; + signal \^genlock_for_master.mstr_reverse_order_reg_0\ : STD_LOGIC; + signal \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_6_n_0\ : STD_LOGIC; + signal binary_frame_ptr : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal data0 : STD_LOGIC_VECTOR ( 2 to 2 ); + signal mstr_reverse_order : STD_LOGIC; + signal mstr_reverse_order_d1 : STD_LOGIC; + signal mstr_reverse_order_d2 : STD_LOGIC; + signal p_0_out : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal raw_frame_ptr : STD_LOGIC_VECTOR ( 2 downto 1 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr[1]_inv_i_1\ : label is "soft_lutpair41"; + attribute SOFT_HLUTNM of \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_4\ : label is "soft_lutpair41"; +begin + \GENLOCK_FOR_MASTER.mstr_reverse_order_reg_0\ <= \^genlock_for_master.mstr_reverse_order_reg_0\; +\GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.GREY_CODER_I\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_greycoder_45 + port map ( + D(1 downto 0) => p_0_out(1 downto 0), + Q(2 downto 0) => binary_frame_ptr(2 downto 0) + ); +\GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.binary_frame_ptr[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg_n_0_[0]\, + O => \GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.binary_frame_ptr[0]_i_1_n_0\ + ); +\GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.binary_frame_ptr_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.binary_frame_ptr[0]_i_1_n_0\, + Q => binary_frame_ptr(0), + R => SR(0) + ); +\GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.binary_frame_ptr_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg[1]_inv_n_0\, + Q => binary_frame_ptr(1), + R => SR(0) + ); +\GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.binary_frame_ptr_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => data0(2), + Q => binary_frame_ptr(2), + R => SR(0) + ); +\GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr[1]_inv_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"40BF" + ) + port map ( + I0 => Q(0), + I1 => mstr_reverse_order, + I2 => num_fstore_minus1(0), + I3 => Q(1), + O => raw_frame_ptr(1) + ); +\GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => Q(1), + I1 => Q(0), + I2 => mstr_reverse_order, + I3 => num_fstore_minus1(0), + I4 => Q(2), + O => raw_frame_ptr(2) + ); +\GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => Q(0), + Q => \GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg_n_0_[0]\, + R => SR(0) + ); +\GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg[1]_inv\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => raw_frame_ptr(1), + Q => \GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg[1]_inv_n_0\, + S => SR(0) + ); +\GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => raw_frame_ptr(2), + Q => data0(2), + R => SR(0) + ); +\GENLOCK_FOR_MASTER.frame_ptr_out[2]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => mstr_reverse_order_d2, + O => \GENLOCK_FOR_MASTER.frame_ptr_out[2]_i_1_n_0\ + ); +\GENLOCK_FOR_MASTER.frame_ptr_out_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => p_0_out(0), + Q => \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2]\(0), + R => SR(0) + ); +\GENLOCK_FOR_MASTER.frame_ptr_out_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => p_0_out(1), + Q => \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2]\(1), + R => SR(0) + ); +\GENLOCK_FOR_MASTER.frame_ptr_out_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GENLOCK_FOR_MASTER.frame_ptr_out[2]_i_1_n_0\, + Q => \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2]\(2), + R => SR(0) + ); +\GENLOCK_FOR_MASTER.mstr_reverse_order_d1_reg\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => mstr_reverse_order, + Q => mstr_reverse_order_d1, + S => SR(0) + ); +\GENLOCK_FOR_MASTER.mstr_reverse_order_d2_reg\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => mstr_reverse_order_d1, + Q => mstr_reverse_order_d2, + S => SR(0) + ); +\GENLOCK_FOR_MASTER.mstr_reverse_order_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF6AFF" + ) + port map ( + I0 => mstr_reverse_order, + I1 => p_71_out(0), + I2 => \^genlock_for_master.mstr_reverse_order_reg_0\, + I3 => mm2s_prmry_resetn, + I4 => p_70_out, + O => \GENLOCK_FOR_MASTER.mstr_reverse_order_i_1_n_0\ + ); +\GENLOCK_FOR_MASTER.mstr_reverse_order_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GENLOCK_FOR_MASTER.mstr_reverse_order_i_1_n_0\, + Q => mstr_reverse_order, + R => '0' + ); +\GENLOCK_FOR_MASTER.mstrfrm_tstsync_d1_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => valid_frame_sync_d2, + Q => p_45_out, + R => SR(0) + ); +\MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"09" + ) + port map ( + I0 => Q(1), + I1 => num_fstore_minus1(0), + I2 => \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_6_n_0\, + O => \^genlock_for_master.mstr_reverse_order_reg_0\ + ); +\MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_6\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFEFF" + ) + port map ( + I0 => Q(4), + I1 => Q(0), + I2 => Q(3), + I3 => valid_frame_sync_d2, + I4 => Q(2), + O => \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_6_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_axi_vdma_genlock_mngr__parameterized0\ is + port ( + s2mm_valid_frame_sync : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 4 downto 0 ); + slv_frame_ref_out : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_s2mm_aclk : in STD_LOGIC; + valid_frame_sync_d2 : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \ptr_ref_i_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_reg\ : in STD_LOGIC; + s2mm_dmacr : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\ : in STD_LOGIC; + \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \num_fstore_minus1_reg[1]\ : in STD_LOGIC; + \DYNAMIC_MASTER_MODE_FRAME_CNT.valid_frame_sync_d2_reg\ : in STD_LOGIC; + \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[0]\ : in STD_LOGIC; + \out\ : in STD_LOGIC; + s2mm_dmasr : in STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_axi_vdma_genlock_mngr__parameterized0\ : entity is "axi_vdma_genlock_mngr"; +end \Arty_Z7_20_axi_vdma_0_0_axi_vdma_genlock_mngr__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_axi_vdma_genlock_mngr__parameterized0\ is + signal \DYNAMIC_GENLOCK_FOR_MASTER.GENLOCK_MUX_I_n_2\ : STD_LOGIC; + signal \DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.binary_frame_ptr[0]_i_1_n_0\ : STD_LOGIC; + signal \DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg[1]_inv_n_0\ : STD_LOGIC; + signal \DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg_n_0_[0]\ : STD_LOGIC; + signal \DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg_n_0_[2]\ : STD_LOGIC; + signal \DYNAMIC_GENLOCK_FOR_MASTER.frame_ptr_out[2]_i_1_n_0\ : STD_LOGIC; + signal \DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_i_1_n_0\ : STD_LOGIC; + signal \DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out[0]_i_1_n_0\ : STD_LOGIC; + signal \DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out[1]_i_1_n_0\ : STD_LOGIC; + signal \DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out[3]_i_1_n_0\ : STD_LOGIC; + signal \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[0]_i_2_n_0\ : STD_LOGIC; + signal \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[0]_i_3_n_0\ : STD_LOGIC; + signal \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[1]_i_2_n_0\ : STD_LOGIC; + signal \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[2]_i_2_n_0\ : STD_LOGIC; + signal \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[2]_i_3_n_0\ : STD_LOGIC; + signal \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[2]_i_4_n_0\ : STD_LOGIC; + signal \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[3]_i_2_n_0\ : STD_LOGIC; + signal \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_10_n_0\ : STD_LOGIC; + signal \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_4_n_0\ : STD_LOGIC; + signal \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_6_n_0\ : STD_LOGIC; + signal \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_7_n_0\ : STD_LOGIC; + signal \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_9_n_0\ : STD_LOGIC; + signal binary_frame_ptr : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal data1 : STD_LOGIC; + signal data2 : STD_LOGIC; + signal dm_binary_frame_ptr : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal dm_mstr_reverse_order_d1 : STD_LOGIC; + signal mstr_reverse_order : STD_LOGIC; + signal mstr_reverse_order_d1 : STD_LOGIC; + signal mstr_reverse_order_d2 : STD_LOGIC; + signal p_0_out : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal raw_frame_ptr : STD_LOGIC_VECTOR ( 2 downto 1 ); + signal \^slv_frame_ref_out\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out[1]_i_1\ : label is "soft_lutpair78"; + attribute SOFT_HLUTNM of \DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out[3]_i_1\ : label is "soft_lutpair78"; + attribute SOFT_HLUTNM of \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[0]_i_3\ : label is "soft_lutpair79"; + attribute SOFT_HLUTNM of \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[2]_i_4\ : label is "soft_lutpair79"; + attribute SOFT_HLUTNM of \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_10\ : label is "soft_lutpair80"; + attribute SOFT_HLUTNM of \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_9\ : label is "soft_lutpair80"; +begin + slv_frame_ref_out(2 downto 0) <= \^slv_frame_ref_out\(2 downto 0); +\DYNAMIC_GENLOCK_FOR_MASTER.GENLOCK_MUX_I\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_genlock_mux + port map ( + D(1) => data1, + D(0) => \DYNAMIC_GENLOCK_FOR_MASTER.GENLOCK_MUX_I_n_2\, + \GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[2]\(2 downto 0) => \GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[2]\(2 downto 0), + SR(0) => SR(0), + data2 => data2, + m_axi_s2mm_aclk => m_axi_s2mm_aclk + ); +\DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.GREY_CODER_I\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_greycoder + port map ( + D(1 downto 0) => p_0_out(1 downto 0), + Q(2 downto 0) => binary_frame_ptr(2 downto 0) + ); +\DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.binary_frame_ptr[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg_n_0_[0]\, + O => \DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.binary_frame_ptr[0]_i_1_n_0\ + ); +\DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.binary_frame_ptr_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.binary_frame_ptr[0]_i_1_n_0\, + Q => binary_frame_ptr(0), + R => SR(0) + ); +\DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.binary_frame_ptr_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg[1]_inv_n_0\, + Q => binary_frame_ptr(1), + R => SR(0) + ); +\DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.binary_frame_ptr_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg_n_0_[2]\, + Q => binary_frame_ptr(2), + R => SR(0) + ); +\DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr[1]_inv_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6555" + ) + port map ( + I0 => \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[2]\(1), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[2]\(0), + I2 => \num_fstore_minus1_reg[1]\, + I3 => mstr_reverse_order, + O => raw_frame_ptr(1) + ); +\DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAAAAAA" + ) + port map ( + I0 => \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[2]\(2), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[2]\(0), + I2 => \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[2]\(1), + I3 => \num_fstore_minus1_reg[1]\, + I4 => mstr_reverse_order, + O => raw_frame_ptr(2) + ); +\DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[2]\(0), + Q => \DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg_n_0_[0]\, + R => SR(0) + ); +\DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg[1]_inv\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => raw_frame_ptr(1), + Q => \DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg[1]_inv_n_0\, + S => SR(0) + ); +\DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => raw_frame_ptr(2), + Q => \DYNAMIC_GENLOCK_FOR_MASTER.GEN_FSTORES_GRTR_ONE.reg_raw_frame_ptr_reg_n_0_[2]\, + R => SR(0) + ); +\DYNAMIC_GENLOCK_FOR_MASTER.dm_binary_frame_ptr_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \DYNAMIC_GENLOCK_FOR_MASTER.GENLOCK_MUX_I_n_2\, + Q => dm_binary_frame_ptr(0), + R => SR(0) + ); +\DYNAMIC_GENLOCK_FOR_MASTER.dm_binary_frame_ptr_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => data1, + Q => dm_binary_frame_ptr(1), + R => SR(0) + ); +\DYNAMIC_GENLOCK_FOR_MASTER.dm_mstr_reverse_order_d1_reg\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => data2, + Q => dm_mstr_reverse_order_d1, + S => SR(0) + ); +\DYNAMIC_GENLOCK_FOR_MASTER.frame_ptr_out[2]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => mstr_reverse_order_d2, + O => \DYNAMIC_GENLOCK_FOR_MASTER.frame_ptr_out[2]_i_1_n_0\ + ); +\DYNAMIC_GENLOCK_FOR_MASTER.frame_ptr_out_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => p_0_out(0), + Q => \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2]\(0), + R => SR(0) + ); +\DYNAMIC_GENLOCK_FOR_MASTER.frame_ptr_out_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => p_0_out(1), + Q => \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2]\(1), + R => SR(0) + ); +\DYNAMIC_GENLOCK_FOR_MASTER.frame_ptr_out_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \DYNAMIC_GENLOCK_FOR_MASTER.frame_ptr_out[2]_i_1_n_0\, + Q => \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2]\(2), + R => SR(0) + ); +\DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_d1_reg\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => mstr_reverse_order, + Q => mstr_reverse_order_d1, + S => SR(0) + ); +\DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_d2_reg\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => mstr_reverse_order_d1, + Q => mstr_reverse_order_d2, + S => SR(0) + ); +\DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFAA69FFFF" + ) + port map ( + I0 => mstr_reverse_order, + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[2]\(1), + I2 => \num_fstore_minus1_reg[1]\, + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[0]\, + I4 => \out\, + I5 => s2mm_dmasr(0), + O => \DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_i_1_n_0\ + ); +\DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_i_1_n_0\, + Q => mstr_reverse_order, + R => '0' + ); +\DYNAMIC_GENLOCK_FOR_MASTER.mstrfrm_tstsync_d1_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => valid_frame_sync_d2, + Q => s2mm_valid_frame_sync, + R => SR(0) + ); +\DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => dm_binary_frame_ptr(0), + I1 => \out\, + I2 => \num_fstore_minus1_reg[1]\, + O => \DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out[0]_i_1_n_0\ + ); +\DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D2000000" + ) + port map ( + I0 => dm_mstr_reverse_order_d1, + I1 => dm_binary_frame_ptr(0), + I2 => dm_binary_frame_ptr(1), + I3 => \out\, + I4 => \num_fstore_minus1_reg[1]\, + O => \DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out[1]_i_1_n_0\ + ); +\DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => dm_binary_frame_ptr(1), + I1 => dm_binary_frame_ptr(0), + I2 => dm_mstr_reverse_order_d1, + I3 => \out\, + I4 => \num_fstore_minus1_reg[1]\, + O => \DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out[3]_i_1_n_0\ + ); +\DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out[0]_i_1_n_0\, + Q => \^slv_frame_ref_out\(0), + R => '0' + ); +\DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out[1]_i_1_n_0\, + Q => \^slv_frame_ref_out\(1), + R => '0' + ); +\DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \DYNAMIC_GENLOCK_FOR_MASTER.slv_frame_ref_out[3]_i_1_n_0\, + Q => \^slv_frame_ref_out\(2), + R => '0' + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AA0FCCCCAA0FAA0F" + ) + port map ( + I0 => Q(0), + I1 => \ptr_ref_i_reg[4]\(0), + I2 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[0]_i_2_n_0\, + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_reg\, + I4 => s2mm_dmacr(0), + I5 => valid_frame_sync_d2, + O => D(0) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"6067666667676666" + ) + port map ( + I0 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(0), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_6_n_0\, + I2 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\, + I3 => s2mm_dmacr(1), + I4 => valid_frame_sync_d2, + I5 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[0]_i_3_n_0\, + O => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[0]_i_2_n_0\ + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[0]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"01" + ) + port map ( + I0 => \^slv_frame_ref_out\(0), + I1 => \^slv_frame_ref_out\(2), + I2 => \^slv_frame_ref_out\(1), + O => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[0]_i_3_n_0\ + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AA0FCCCCAA0FAA0F" + ) + port map ( + I0 => Q(1), + I1 => \ptr_ref_i_reg[4]\(1), + I2 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[1]_i_2_n_0\, + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_reg\, + I4 => s2mm_dmacr(0), + I5 => valid_frame_sync_d2, + O => D(1) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FAFAFAFAEBEBFFEB" + ) + port map ( + I0 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[2]_i_3_n_0\, + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(0), + I2 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(1), + I3 => valid_frame_sync_d2, + I4 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\, + I5 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_6_n_0\, + O => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[1]_i_2_n_0\ + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AA0FCCCCAA0FAA0F" + ) + port map ( + I0 => Q(2), + I1 => \ptr_ref_i_reg[4]\(2), + I2 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[2]_i_2_n_0\, + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_reg\, + I4 => s2mm_dmacr(0), + I5 => valid_frame_sync_d2, + O => D(2) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[2]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FAAFEABF" + ) + port map ( + I0 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[2]_i_3_n_0\, + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(0), + I2 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(1), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(2), + I4 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_6_n_0\, + O => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[2]_i_2_n_0\ + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[2]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000005D5D555D" + ) + port map ( + I0 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\, + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_7_n_0\, + I2 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[2]_i_4_n_0\, + I3 => \num_fstore_minus1_reg[1]\, + I4 => \^slv_frame_ref_out\(1), + I5 => \DYNAMIC_MASTER_MODE_FRAME_CNT.valid_frame_sync_d2_reg\, + O => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[2]_i_3_n_0\ + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[2]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFF4" + ) + port map ( + I0 => \num_fstore_minus1_reg[1]\, + I1 => \^slv_frame_ref_out\(1), + I2 => \^slv_frame_ref_out\(0), + I3 => \^slv_frame_ref_out\(2), + O => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[2]_i_4_n_0\ + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AA0FCCCCAA0FAA0F" + ) + port map ( + I0 => Q(3), + I1 => \ptr_ref_i_reg[4]\(3), + I2 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[3]_i_2_n_0\, + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_reg\, + I4 => s2mm_dmacr(0), + I5 => valid_frame_sync_d2, + O => D(3) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"B487474747474747" + ) + port map ( + I0 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(4), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_6_n_0\, + I2 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(3), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(0), + I4 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(1), + I5 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(2), + O => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[3]_i_2_n_0\ + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_10\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^slv_frame_ref_out\(0), + I1 => \^slv_frame_ref_out\(1), + O => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_10_n_0\ + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AA0FCCCCAA0FAA0F" + ) + port map ( + I0 => Q(4), + I1 => \ptr_ref_i_reg[4]\(4), + I2 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_4_n_0\, + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_reg\, + I4 => s2mm_dmacr(0), + I5 => valid_frame_sync_d2, + O => D(4) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"C333933333333333" + ) + port map ( + I0 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_6_n_0\, + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(4), + I2 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(2), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(1), + I4 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(0), + I5 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(3), + O => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_4_n_0\ + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000AAAAAA20" + ) + port map ( + I0 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_7_n_0\, + I1 => \num_fstore_minus1_reg[1]\, + I2 => \^slv_frame_ref_out\(1), + I3 => \^slv_frame_ref_out\(0), + I4 => \^slv_frame_ref_out\(2), + I5 => \DYNAMIC_MASTER_MODE_FRAME_CNT.valid_frame_sync_d2_reg\, + O => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_6_n_0\ + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1220000000000001" + ) + port map ( + I0 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(2), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_9_n_0\, + I2 => \^slv_frame_ref_out\(2), + I3 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_10_n_0\, + I4 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(3), + I5 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(4), + O => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_7_n_0\ + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_9\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F69F" + ) + port map ( + I0 => \^slv_frame_ref_out\(1), + I1 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(1), + I2 => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(0), + I3 => \^slv_frame_ref_out\(0), + O => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_9_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_lite_if is + port ( + D : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_lite_awready : out STD_LOGIC; + s_axi_lite_wready : out STD_LOGIC; + s_axi_lite_arready : out STD_LOGIC; + dmacr_i : out STD_LOGIC_VECTOR ( 0 to 0 ); + mm2s_axi2ip_wrce : out STD_LOGIC_VECTOR ( 8 downto 0 ); + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + in0 : out STD_LOGIC_VECTOR ( 28 downto 0 ); + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]_0\ : out STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0\ : out STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0\ : out STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_0\ : out STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1\ : out STD_LOGIC; + p_15_out : out STD_LOGIC; + \dmacr_i_reg[1]\ : out STD_LOGIC; + p_14_out : out STD_LOGIC; + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + prmtr_updt_complete_i_reg : out STD_LOGIC; + prmtr_updt_complete_i_reg_0 : out STD_LOGIC; + ioc_irq_reg : out STD_LOGIC; + dly_irq_reg : out STD_LOGIC; + dma_interr_reg : out STD_LOGIC; + dma_interr_reg_0 : out STD_LOGIC; + \GEN_FOR_FLUSH.fsize_err_reg\ : out STD_LOGIC; + lsize_err_reg : out STD_LOGIC; + \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg\ : out STD_LOGIC; + ioc_irq_reg_0 : out STD_LOGIC; + dly_irq_reg_0 : out STD_LOGIC; + lsize_more_err_reg : out STD_LOGIC; + s_axi_lite_bvalid : out STD_LOGIC; + s_axi_lite_rvalid : out STD_LOGIC; + s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s2mm_axi2ip_wrce : out STD_LOGIC_VECTOR ( 7 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_lite_aclk : in STD_LOGIC; + prmry_reset2 : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + prmry_reset2_0 : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + s_axi_lite_wvalid : in STD_LOGIC; + s_axi_lite_awvalid : in STD_LOGIC; + s_axi_lite_arvalid : in STD_LOGIC; + s_axi_lite_resetn : in STD_LOGIC; + p_71_out : in STD_LOGIC_VECTOR ( 17 downto 0 ); + mm2s_prmry_resetn : in STD_LOGIC; + stop : in STD_LOGIC; + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_reg\ : in STD_LOGIC; + \reg_module_hsize_reg[0]\ : in STD_LOGIC; + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\ : in STD_LOGIC_VECTOR ( 28 downto 0 ); + \reg_module_hsize_reg[3]\ : in STD_LOGIC; + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\ : in STD_LOGIC_VECTOR ( 28 downto 0 ); + \reg_module_hsize_reg[4]\ : in STD_LOGIC; + \reg_module_hsize_reg[5]\ : in STD_LOGIC; + \reg_module_hsize_reg[6]\ : in STD_LOGIC; + \reg_module_hsize_reg[7]\ : in STD_LOGIC; + \reg_module_hsize_reg[8]\ : in STD_LOGIC; + \reg_module_hsize_reg[9]\ : in STD_LOGIC; + \reg_module_hsize_reg[10]\ : in STD_LOGIC; + \reg_module_hsize_reg[11]\ : in STD_LOGIC; + \reg_module_hsize_reg[12]\ : in STD_LOGIC; + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\ : in STD_LOGIC_VECTOR ( 18 downto 0 ); + \reg_module_hsize_reg[15]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + p_70_out : in STD_LOGIC; + dma_interr_reg_1 : in STD_LOGIC; + \M_GEN_DMACR_REGISTER.dmacr_i_reg[14]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + dma_slverr_reg : in STD_LOGIC; + dma_decerr_reg : in STD_LOGIC; + ioc_irq_reg_1 : in STD_LOGIC; + dly_irq_reg_1 : in STD_LOGIC; + err_irq_reg : in STD_LOGIC; + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + ch1_irqdelay_status : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s2mm_dmacr : in STD_LOGIC_VECTOR ( 22 downto 0 ); + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31]_0\ : in STD_LOGIC; + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[23]\ : in STD_LOGIC; + s2mm_prmry_resetn : in STD_LOGIC; + s2mm_dmasr : in STD_LOGIC_VECTOR ( 0 to 0 ); + \DMA_IRQ_MASK_GEN.dma_irq_mask_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \reg_module_vsize_reg[12]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + s2mm_soft_reset : in STD_LOGIC; + \reg_module_hsize_reg[15]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + ch2_irqdelay_status : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dma_interr_reg_2 : in STD_LOGIC; + dma_slverr_reg_0 : in STD_LOGIC; + dma_decerr_reg_0 : in STD_LOGIC; + \GEN_FOR_FLUSH.fsize_err_reg_0\ : in STD_LOGIC; + lsize_err_reg_0 : in STD_LOGIC; + \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); + \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg_0\ : in STD_LOGIC; + ioc_irq_reg_2 : in STD_LOGIC; + dly_irq_reg_2 : in STD_LOGIC; + err_irq_reg_0 : in STD_LOGIC; + lsize_more_err_reg_0 : in STD_LOGIC; + mm2s_ioc_irq_set : in STD_LOGIC; + ch1_dly_irq_set : in STD_LOGIC; + s2mm_dma_interr_set_minus_frame_errors : in STD_LOGIC; + s2mm_fsize_more_or_sof_late : in STD_LOGIC; + fsize_mismatch_err : in STD_LOGIC; + lsize_mismatch_err : in STD_LOGIC; + s2mm_ioc_irq_set : in STD_LOGIC; + ch2_dly_irq_set : in STD_LOGIC; + lsize_more_mismatch_err : in STD_LOGIC; + s_axi_lite_bready : in STD_LOGIC; + s_axi_lite_rready : in STD_LOGIC; + s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 5 downto 0 ); + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 5 downto 0 ); + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_lite_if : entity is "axi_vdma_lite_if"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_lite_if; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_lite_if is + signal \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[25]_i_2_n_0\ : STD_LOGIC; + signal \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0\ : STD_LOGIC; + signal \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0\ : STD_LOGIC; + signal \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0\ : STD_LOGIC; + signal \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0\ : STD_LOGIC; + signal \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[4]_i_2_n_0\ : STD_LOGIC; + signal \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\ : STD_LOGIC; + signal \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[12]_0\ : STD_LOGIC; + signal \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[15]_1\ : STD_LOGIC; + signal \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\ : STD_LOGIC; + signal \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.prepare_wrce_pulse_lite_d6_reg_srl6_i_1_n_0\ : STD_LOGIC; + signal \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.rvalid_out_i_i_1_n_0\ : STD_LOGIC; + signal arvalid : STD_LOGIC; + signal awaddr : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal awvalid : STD_LOGIC; + signal axi2ip_rdaddr_captured_mm2s_cdc_tig : STD_LOGIC_VECTOR ( 7 downto 2 ); + attribute async_reg : string; + attribute async_reg of axi2ip_rdaddr_captured_mm2s_cdc_tig : signal is "true"; + signal \axi2ip_rdaddr_captured_reg_n_0_[4]\ : STD_LOGIC; + signal \axi2ip_rdaddr_captured_reg_n_0_[5]\ : STD_LOGIC; + signal \axi2ip_rdaddr_captured_reg_n_0_[6]\ : STD_LOGIC; + signal \axi2ip_rdaddr_captured_reg_n_0_[7]\ : STD_LOGIC; + signal axi2ip_rdaddr_captured_s2mm_cdc_tig : STD_LOGIC_VECTOR ( 7 downto 2 ); + attribute async_reg of axi2ip_rdaddr_captured_s2mm_cdc_tig : signal is "true"; + signal axi2ip_wraddr_captured : STD_LOGIC_VECTOR ( 7 downto 2 ); + signal axi2ip_wraddr_captured_mm2s_cdc_tig : STD_LOGIC_VECTOR ( 7 downto 2 ); + attribute async_reg of axi2ip_wraddr_captured_mm2s_cdc_tig : signal is "true"; + signal axi2ip_wraddr_captured_s2mm_cdc_tig : STD_LOGIC_VECTOR ( 7 downto 2 ); + attribute async_reg of axi2ip_wraddr_captured_s2mm_cdc_tig : signal is "true"; + signal bvalid_out_i_i_1_n_0 : STD_LOGIC; + signal ip2axi_rddata_captured : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ip2axi_rddata_captured_mm2s_cdc_tig : STD_LOGIC_VECTOR ( 31 downto 0 ); + attribute async_reg of ip2axi_rddata_captured_mm2s_cdc_tig : signal is "true"; + signal ip2axi_rddata_captured_s2mm_cdc_tig : STD_LOGIC_VECTOR ( 31 downto 0 ); + attribute async_reg of ip2axi_rddata_captured_s2mm_cdc_tig : signal is "true"; + signal \ip2axi_rddata_int_inferred_i_33__0_n_0\ : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_33_n_0 : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_34__0_n_0\ : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_34_n_0 : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_35__0_n_0\ : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_36__0_n_0\ : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_36_n_0 : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_37__0_n_0\ : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_37_n_0 : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_38__0_n_0\ : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_38_n_0 : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_39__0_n_0\ : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_39_n_0 : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_40__0_n_0\ : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_40_n_0 : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_41__0_n_0\ : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_41_n_0 : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_42__0_n_0\ : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_42_n_0 : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_43__0_n_0\ : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_43_n_0 : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_44__0_n_0\ : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_44_n_0 : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_45__0_n_0\ : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_45_n_0 : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_46__0_n_0\ : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_46_n_0 : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_47__0_n_0\ : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_47_n_0 : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_48__0_n_0\ : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_48_n_0 : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_49__0_n_0\ : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_49_n_0 : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_50__0_n_0\ : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_50_n_0 : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_51__0_n_0\ : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_52__0_n_0\ : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_53__0_n_0\ : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_54__0_n_0\ : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_54_n_0 : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_55__0_n_0\ : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_55_n_0 : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_56__0_n_0\ : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_56_n_0 : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_57__0_n_0\ : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_57_n_0 : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_58__0_n_0\ : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_58_n_0 : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_59__0_n_0\ : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_60__0_n_0\ : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_61__0_n_0\ : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_62__0_n_0\ : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_63__0_n_0\ : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_64__0_n_0\ : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_65__0_n_0\ : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_66__0_n_0\ : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_67__0_n_0\ : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_67_n_0 : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_68__0_n_0\ : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_69__0_n_0\ : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_69_n_0 : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_70__0_n_0\ : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_71__0_n_0\ : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_71_n_0 : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_72__0_n_0\ : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_73__0_n_0\ : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_74__0_n_0\ : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_75__0_n_0\ : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_76__0_n_0\ : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_76_n_0 : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_77__0_n_0\ : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_78__0_n_0\ : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_78_n_0 : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_79__0_n_0\ : STD_LOGIC; + signal \ip2axi_rddata_int_inferred_i_80__0_n_0\ : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_81_n_0 : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_82_n_0 : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_83_n_0 : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_84_n_0 : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_85_n_0 : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_86_n_0 : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_87_n_0 : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_88_n_0 : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_89_n_0 : STD_LOGIC; + signal ip2axi_rddata_int_inferred_i_90_n_0 : STD_LOGIC; + signal lite_wr_addr_phase_finished_data_phase_started : STD_LOGIC; + signal lite_wr_addr_phase_finished_data_phase_started_i_1_n_0 : STD_LOGIC; + signal mm2s_axi2ip_wrdata_cdc_tig : STD_LOGIC_VECTOR ( 31 downto 0 ); + attribute async_reg of mm2s_axi2ip_wrdata_cdc_tig : signal is "true"; + signal mm2s_ip2axi_rddata_d1 : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \p_2_in__0\ : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal p_4_in : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal prepare_wrce : STD_LOGIC; + signal prepare_wrce_d1 : STD_LOGIC; + signal prepare_wrce_pulse_lite_d6 : STD_LOGIC; + signal read_has_started_i : STD_LOGIC; + signal read_has_started_i_i_1_n_0 : STD_LOGIC; + signal s2mm_axi2ip_wrdata_cdc_tig : STD_LOGIC_VECTOR ( 31 downto 0 ); + attribute async_reg of s2mm_axi2ip_wrdata_cdc_tig : signal is "true"; + signal s2mm_ip2axi_rddata_d1 : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \^s_axi_lite_arready\ : STD_LOGIC; + signal \^s_axi_lite_awready\ : STD_LOGIC; + signal \^s_axi_lite_bvalid\ : STD_LOGIC; + signal \^s_axi_lite_rvalid\ : STD_LOGIC; + signal \^s_axi_lite_wready\ : STD_LOGIC; + signal sig_arvalid_arrived_d1 : STD_LOGIC; + signal sig_arvalid_arrived_d1_i_1_n_0 : STD_LOGIC; + signal sig_arvalid_arrived_d4 : STD_LOGIC; + signal \sig_arvalid_detected__0\ : STD_LOGIC; + signal sig_awvalid_arrived_d1 : STD_LOGIC; + signal sig_awvalid_arrived_d1_i_1_n_0 : STD_LOGIC; + signal \sig_awvalid_detected__0\ : STD_LOGIC; + signal wdata : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal write_has_started : STD_LOGIC; + signal write_has_started_i_1_n_0 : STD_LOGIC; + signal wvalid : STD_LOGIC; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[2]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[6]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[6]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_s2mm_cdc_tig_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_s2mm_cdc_tig_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_s2mm_cdc_tig_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_s2mm_cdc_tig_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_s2mm_cdc_tig_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_s2mm_cdc_tig_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_s2mm_cdc_tig_reg[5]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_s2mm_cdc_tig_reg[5]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_s2mm_cdc_tig_reg[6]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_s2mm_cdc_tig_reg[6]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_s2mm_cdc_tig_reg[7]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_s2mm_cdc_tig_reg[7]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[5]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[5]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[6]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[6]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[5]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[5]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[6]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[6]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[7]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[7]\ : label is "yes"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3\ : label is "soft_lutpair10"; + attribute SOFT_HLUTNM of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4\ : label is "soft_lutpair10"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[0]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[10]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[10]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[11]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[11]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[12]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[12]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[13]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[13]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[14]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[14]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[15]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[15]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[16]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[16]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[17]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[17]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[18]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[18]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[19]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[19]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[20]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[20]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[21]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[21]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[22]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[22]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[23]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[23]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[24]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[24]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[25]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[25]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[26]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[26]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[27]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[27]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[28]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[28]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[29]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[29]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[30]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[30]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[31]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[31]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[5]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[5]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[6]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[6]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[7]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[7]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[8]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[8]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[9]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[9]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[0]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[10]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[10]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[11]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[11]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[12]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[12]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[13]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[13]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[14]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[14]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[15]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[15]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[16]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[16]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[17]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[17]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[18]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[18]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[19]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[19]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[20]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[20]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[21]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[21]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[22]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[22]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[23]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[23]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[24]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[24]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[25]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[25]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[26]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[26]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[27]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[27]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[28]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[28]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[29]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[29]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[30]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[30]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[31]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[31]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[5]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[5]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[6]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[6]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[7]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[7]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[8]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[8]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[9]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[9]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[0]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[10]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[10]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[11]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[11]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[14]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[14]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[15]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[15]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[16]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[16]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[17]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[17]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[19]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[19]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[20]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[20]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[21]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[21]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[22]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[22]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[23]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[23]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[24]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[24]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[25]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[25]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[26]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[26]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[27]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[27]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[28]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[28]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[29]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[29]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[30]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[30]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[31]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[31]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[5]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[5]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[6]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[6]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[7]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[7]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[8]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[8]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[9]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[9]\ : label is "yes"; + attribute SOFT_HLUTNM of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.prepare_wrce_d1_i_1\ : label is "soft_lutpair11"; + attribute srl_name : string; + attribute srl_name of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.prepare_wrce_pulse_lite_d6_reg_srl6\ : label is "U0/\AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.prepare_wrce_pulse_lite_d6_reg_srl6 "; + attribute SOFT_HLUTNM of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.prepare_wrce_pulse_lite_d6_reg_srl6_i_1\ : label is "soft_lutpair11"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[0]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[10]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[10]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[11]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[11]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[12]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[12]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[13]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[13]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[14]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[14]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[15]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[15]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[16]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[16]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[17]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[17]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[19]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[19]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[20]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[20]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[21]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[21]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[22]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[22]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[23]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[23]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[24]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[24]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[25]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[25]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[26]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[26]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[27]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[27]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[28]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[28]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[30]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[30]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[31]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[31]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[5]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[5]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[6]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[6]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[7]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[7]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[8]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[8]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[9]\ : label is std.standard.true; + attribute KEEP of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[9]\ : label is "yes"; + attribute srl_name of \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.sig_arvalid_arrived_d4_reg_srl3\ : label is "U0/\AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.sig_arvalid_arrived_d4_reg_srl3 "; + attribute SOFT_HLUTNM of sig_arvalid_arrived_d1_i_1 : label is "soft_lutpair12"; + attribute SOFT_HLUTNM of sig_awvalid_arrived_d1_i_1 : label is "soft_lutpair12"; +begin + D(31 downto 0) <= mm2s_axi2ip_wrdata_cdc_tig(31 downto 0); + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31]\(31 downto 0) <= s2mm_axi2ip_wrdata_cdc_tig(31 downto 0); + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0\ <= \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]_0\ <= \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[12]_0\; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1\ <= \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[15]_1\; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0\ <= \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\; + \out\(1 downto 0) <= axi2ip_rdaddr_captured_mm2s_cdc_tig(3 downto 2); + s_axi_lite_arready <= \^s_axi_lite_arready\; + s_axi_lite_awready <= \^s_axi_lite_awready\; + s_axi_lite_bvalid <= \^s_axi_lite_bvalid\; + s_axi_lite_rvalid <= \^s_axi_lite_rvalid\; + s_axi_lite_wready <= \^s_axi_lite_wready\; +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.LITE_WVALID_MM2S_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized6\ + port map ( + D(10 downto 3) => mm2s_axi2ip_wrdata_cdc_tig(23 downto 16), + D(2 downto 1) => mm2s_axi2ip_wrdata_cdc_tig(13 downto 12), + D(0) => mm2s_axi2ip_wrdata_cdc_tig(0), + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]\(0) => \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]\(0), + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_reg\ => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_reg\, + SR(0) => SR(0), + ch1_dly_irq_set => ch1_dly_irq_set, + dly_irq_reg => dly_irq_reg, + dly_irq_reg_0 => dly_irq_reg_1, + dmacr_i(0) => dmacr_i(0), + ioc_irq_reg => ioc_irq_reg, + ioc_irq_reg_0 => ioc_irq_reg_1, + lite_wr_addr_phase_finished_data_phase_started => lite_wr_addr_phase_finished_data_phase_started, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + mm2s_axi2ip_wrce(8 downto 0) => mm2s_axi2ip_wrce(8 downto 0), + mm2s_ioc_irq_set => mm2s_ioc_irq_set, + mm2s_prmry_resetn => mm2s_prmry_resetn, + \out\(5 downto 0) => axi2ip_wraddr_captured_mm2s_cdc_tig(7 downto 2), + p_71_out(0) => p_71_out(0), + prepare_wrce_d1 => prepare_wrce_d1, + prmry_reset2 => prmry_reset2, + prmtr_updt_complete_i_reg => prmtr_updt_complete_i_reg, + s_axi_lite_aclk => s_axi_lite_aclk, + stop => stop, + wvalid => wvalid + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.LITE_WVALID_S2MM_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized7\ + port map ( + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31]\ => \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31]_0\, + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]\(0) => \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]_0\(0), + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[23]\ => \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[23]\, + \GEN_FOR_FLUSH.fsize_err_reg\ => \GEN_FOR_FLUSH.fsize_err_reg\, + \GEN_FOR_FLUSH.fsize_err_reg_0\ => \GEN_FOR_FLUSH.fsize_err_reg_0\, + \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg\ => \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg\, + \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg_0\ => \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg_0\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(20 downto 6) => s2mm_axi2ip_wrdata_cdc_tig(29 downto 15), + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(5 downto 3) => s2mm_axi2ip_wrdata_cdc_tig(13 downto 11), + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(2 downto 1) => s2mm_axi2ip_wrdata_cdc_tig(8 downto 7), + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\(0) => s2mm_axi2ip_wrdata_cdc_tig(4), + SR(0) => SR(0), + ch2_dly_irq_set => ch2_dly_irq_set, + dly_irq_reg => dly_irq_reg_0, + dly_irq_reg_0 => dly_irq_reg_2, + dma_interr_reg => dma_interr_reg, + dma_interr_reg_0 => dma_interr_reg_0, + dma_interr_reg_1 => dma_interr_reg_2, + \dmacr_i_reg[1]\ => \dmacr_i_reg[1]\, + fsize_mismatch_err => fsize_mismatch_err, + ioc_irq_reg => ioc_irq_reg_0, + ioc_irq_reg_0 => ioc_irq_reg_2, + lite_wr_addr_phase_finished_data_phase_started => lite_wr_addr_phase_finished_data_phase_started, + lsize_err_reg => lsize_err_reg, + lsize_err_reg_0 => lsize_err_reg_0, + lsize_mismatch_err => lsize_mismatch_err, + lsize_more_err_reg => lsize_more_err_reg, + lsize_more_err_reg_0 => lsize_more_err_reg_0, + lsize_more_mismatch_err => lsize_more_mismatch_err, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\(5 downto 0) => axi2ip_wraddr_captured_s2mm_cdc_tig(7 downto 2), + p_14_out => p_14_out, + p_15_out => p_15_out, + prepare_wrce_d1 => prepare_wrce_d1, + prmry_reset2_0 => prmry_reset2_0, + prmtr_updt_complete_i_reg => prmtr_updt_complete_i_reg_0, + s2mm_axi2ip_wrce(7 downto 0) => s2mm_axi2ip_wrce(7 downto 0), + s2mm_dma_interr_set_minus_frame_errors => s2mm_dma_interr_set_minus_frame_errors, + s2mm_dmacr(12 downto 7) => s2mm_dmacr(20 downto 15), + s2mm_dmacr(6 downto 1) => s2mm_dmacr(12 downto 7), + s2mm_dmacr(0) => s2mm_dmacr(0), + s2mm_fsize_more_or_sof_late => s2mm_fsize_more_or_sof_late, + s2mm_ioc_irq_set => s2mm_ioc_irq_set, + s2mm_prmry_resetn => s2mm_prmry_resetn, + s_axi_lite_aclk => s_axi_lite_aclk, + wvalid => wvalid + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.arready_out_i_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => sig_arvalid_arrived_d4, + Q => \^s_axi_lite_arready\, + R => SR(0) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => p_4_in(2), + Q => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => p_4_in(3), + Q => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \axi2ip_rdaddr_captured_reg_n_0_[4]\, + Q => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \axi2ip_rdaddr_captured_reg_n_0_[5]\, + Q => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \axi2ip_rdaddr_captured_reg_n_0_[6]\, + Q => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \axi2ip_rdaddr_captured_reg_n_0_[7]\, + Q => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_s2mm_cdc_tig_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => p_4_in(2), + Q => axi2ip_rdaddr_captured_s2mm_cdc_tig(2), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_s2mm_cdc_tig_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => p_4_in(3), + Q => axi2ip_rdaddr_captured_s2mm_cdc_tig(3), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_s2mm_cdc_tig_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \axi2ip_rdaddr_captured_reg_n_0_[4]\, + Q => axi2ip_rdaddr_captured_s2mm_cdc_tig(4), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_s2mm_cdc_tig_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \axi2ip_rdaddr_captured_reg_n_0_[5]\, + Q => axi2ip_rdaddr_captured_s2mm_cdc_tig(5), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_s2mm_cdc_tig_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \axi2ip_rdaddr_captured_reg_n_0_[6]\, + Q => axi2ip_rdaddr_captured_s2mm_cdc_tig(6), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_s2mm_cdc_tig_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \axi2ip_rdaddr_captured_reg_n_0_[7]\, + Q => axi2ip_rdaddr_captured_s2mm_cdc_tig(7), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => axi2ip_wraddr_captured(2), + Q => axi2ip_wraddr_captured_mm2s_cdc_tig(2), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => axi2ip_wraddr_captured(3), + Q => axi2ip_wraddr_captured_mm2s_cdc_tig(3), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => axi2ip_wraddr_captured(4), + Q => axi2ip_wraddr_captured_mm2s_cdc_tig(4), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => axi2ip_wraddr_captured(5), + Q => axi2ip_wraddr_captured_mm2s_cdc_tig(5), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => axi2ip_wraddr_captured(6), + Q => axi2ip_wraddr_captured_mm2s_cdc_tig(6), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => axi2ip_wraddr_captured(7), + Q => axi2ip_wraddr_captured_mm2s_cdc_tig(7), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => axi2ip_wraddr_captured(2), + Q => axi2ip_wraddr_captured_s2mm_cdc_tig(2), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => axi2ip_wraddr_captured(3), + Q => axi2ip_wraddr_captured_s2mm_cdc_tig(3), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => axi2ip_wraddr_captured(4), + Q => axi2ip_wraddr_captured_s2mm_cdc_tig(4), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => axi2ip_wraddr_captured(5), + Q => axi2ip_wraddr_captured_s2mm_cdc_tig(5), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => axi2ip_wraddr_captured(6), + Q => axi2ip_wraddr_captured_s2mm_cdc_tig(6), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => axi2ip_wraddr_captured(7), + Q => axi2ip_wraddr_captured_s2mm_cdc_tig(7), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0\, + I1 => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(0), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0\, + I3 => ip2axi_rddata_captured_mm2s_cdc_tig(0), + I4 => ip2axi_rddata_captured_s2mm_cdc_tig(0), + I5 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0\, + O => ip2axi_rddata_captured(0) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[10]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0\, + I1 => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(2), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0\, + I3 => ip2axi_rddata_captured_mm2s_cdc_tig(10), + I4 => ip2axi_rddata_captured_s2mm_cdc_tig(10), + I5 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0\, + O => ip2axi_rddata_captured(10) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[11]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0\, + I1 => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(3), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0\, + I3 => ip2axi_rddata_captured_mm2s_cdc_tig(11), + I4 => ip2axi_rddata_captured_s2mm_cdc_tig(11), + I5 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0\, + O => ip2axi_rddata_captured(11) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[12]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0\, + I1 => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(4), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0\, + I3 => ip2axi_rddata_captured_mm2s_cdc_tig(12), + I4 => ip2axi_rddata_captured_s2mm_cdc_tig(12), + I5 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0\, + O => ip2axi_rddata_captured(12) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[13]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0AAAAACCCCCAA0CC" + ) + port map ( + I0 => ip2axi_rddata_captured_s2mm_cdc_tig(13), + I1 => ip2axi_rddata_captured_mm2s_cdc_tig(13), + I2 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, + I3 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, + I4 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, + I5 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, + O => ip2axi_rddata_captured(13) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[14]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0AAAAACCCCCAA0CC" + ) + port map ( + I0 => ip2axi_rddata_captured_s2mm_cdc_tig(14), + I1 => ip2axi_rddata_captured_mm2s_cdc_tig(14), + I2 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, + I3 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, + I4 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, + I5 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, + O => ip2axi_rddata_captured(14) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[15]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0AAAAACCCCCAA0CC" + ) + port map ( + I0 => ip2axi_rddata_captured_s2mm_cdc_tig(15), + I1 => ip2axi_rddata_captured_mm2s_cdc_tig(15), + I2 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, + I3 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, + I4 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, + I5 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, + O => ip2axi_rddata_captured(15) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[16]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0\, + I1 => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\(0), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0\, + I3 => ip2axi_rddata_captured_mm2s_cdc_tig(16), + I4 => ip2axi_rddata_captured_s2mm_cdc_tig(16), + I5 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0\, + O => ip2axi_rddata_captured(16) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[17]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0\, + I1 => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\(1), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0\, + I3 => ip2axi_rddata_captured_mm2s_cdc_tig(17), + I4 => ip2axi_rddata_captured_s2mm_cdc_tig(17), + I5 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0\, + O => ip2axi_rddata_captured(17) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[18]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0\, + I1 => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\(2), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0\, + I3 => ip2axi_rddata_captured_mm2s_cdc_tig(18), + I4 => ip2axi_rddata_captured_s2mm_cdc_tig(18), + I5 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0\, + O => ip2axi_rddata_captured(18) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[19]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0\, + I1 => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\(3), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0\, + I3 => ip2axi_rddata_captured_mm2s_cdc_tig(19), + I4 => ip2axi_rddata_captured_s2mm_cdc_tig(19), + I5 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0\, + O => ip2axi_rddata_captured(19) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0\, + I1 => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(1), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0\, + I3 => ip2axi_rddata_captured_mm2s_cdc_tig(1), + I4 => ip2axi_rddata_captured_s2mm_cdc_tig(1), + I5 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0\, + O => ip2axi_rddata_captured(1) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[20]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0\, + I1 => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\(4), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0\, + I3 => ip2axi_rddata_captured_mm2s_cdc_tig(20), + I4 => ip2axi_rddata_captured_s2mm_cdc_tig(20), + I5 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0\, + O => ip2axi_rddata_captured(20) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[21]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0AAAAACCCCCAA0CC" + ) + port map ( + I0 => ip2axi_rddata_captured_s2mm_cdc_tig(21), + I1 => ip2axi_rddata_captured_mm2s_cdc_tig(21), + I2 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, + I3 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, + I4 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, + I5 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, + O => ip2axi_rddata_captured(21) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[22]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0AAAAACCCCCAA0CC" + ) + port map ( + I0 => ip2axi_rddata_captured_s2mm_cdc_tig(22), + I1 => ip2axi_rddata_captured_mm2s_cdc_tig(22), + I2 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, + I3 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, + I4 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, + I5 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, + O => ip2axi_rddata_captured(22) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[23]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0AAAAACCCCCAA0CC" + ) + port map ( + I0 => ip2axi_rddata_captured_s2mm_cdc_tig(23), + I1 => ip2axi_rddata_captured_mm2s_cdc_tig(23), + I2 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, + I3 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, + I4 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, + I5 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, + O => ip2axi_rddata_captured(23) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[24]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0\, + I1 => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4]\(0), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0\, + I3 => ip2axi_rddata_captured_mm2s_cdc_tig(24), + I4 => ip2axi_rddata_captured_s2mm_cdc_tig(24), + I5 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0\, + O => ip2axi_rddata_captured(24) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[25]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFF888" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0\, + I1 => ip2axi_rddata_captured_mm2s_cdc_tig(25), + I2 => ip2axi_rddata_captured_s2mm_cdc_tig(25), + I3 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0\, + I4 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[25]_i_2_n_0\, + I5 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0\, + O => ip2axi_rddata_captured(25) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[25]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0010000000000000" + ) + port map ( + I0 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, + I1 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, + I2 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, + I3 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, + I4 => p_4_in(3), + I5 => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4]\(1), + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[25]_i_2_n_0\ + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[26]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0\, + I1 => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4]\(2), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0\, + I3 => ip2axi_rddata_captured_mm2s_cdc_tig(26), + I4 => ip2axi_rddata_captured_s2mm_cdc_tig(26), + I5 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0\, + O => ip2axi_rddata_captured(26) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[27]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0\, + I1 => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4]\(3), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0\, + I3 => ip2axi_rddata_captured_mm2s_cdc_tig(27), + I4 => ip2axi_rddata_captured_s2mm_cdc_tig(27), + I5 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0\, + O => ip2axi_rddata_captured(27) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0\, + I1 => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4]\(4), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0\, + I3 => ip2axi_rddata_captured_mm2s_cdc_tig(28), + I4 => ip2axi_rddata_captured_s2mm_cdc_tig(28), + I5 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0\, + O => ip2axi_rddata_captured(28) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000100000" + ) + port map ( + I0 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, + I1 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, + I2 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, + I3 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, + I4 => p_4_in(3), + I5 => p_4_in(2), + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0\ + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[29]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0\, + I1 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0\, + I2 => ip2axi_rddata_captured_s2mm_cdc_tig(29), + I3 => ip2axi_rddata_captured_mm2s_cdc_tig(29), + I4 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0\, + O => ip2axi_rddata_captured(29) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0\, + I1 => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(2), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0\, + I3 => ip2axi_rddata_captured_mm2s_cdc_tig(2), + I4 => ip2axi_rddata_captured_s2mm_cdc_tig(2), + I5 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0\, + O => ip2axi_rddata_captured(2) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0\, + I1 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0\, + I2 => ip2axi_rddata_captured_s2mm_cdc_tig(30), + I3 => ip2axi_rddata_captured_mm2s_cdc_tig(30), + I4 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0\, + O => ip2axi_rddata_captured(30) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0010000000000000" + ) + port map ( + I0 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, + I1 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, + I2 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, + I3 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, + I4 => p_4_in(3), + I5 => p_4_in(2), + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0\ + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"38AC" + ) + port map ( + I0 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, + I1 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, + I2 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, + I3 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0\ + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"03E3" + ) + port map ( + I0 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, + I1 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, + I2 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, + I3 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0\ + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[31]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0AAAAACCCCCAA0CC" + ) + port map ( + I0 => ip2axi_rddata_captured_s2mm_cdc_tig(31), + I1 => ip2axi_rddata_captured_mm2s_cdc_tig(31), + I2 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, + I3 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, + I4 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, + I5 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, + O => ip2axi_rddata_captured(31) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0\, + I1 => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(3), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0\, + I3 => ip2axi_rddata_captured_mm2s_cdc_tig(3), + I4 => ip2axi_rddata_captured_s2mm_cdc_tig(3), + I5 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0\, + O => ip2axi_rddata_captured(3) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFF888" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0\, + I1 => ip2axi_rddata_captured_mm2s_cdc_tig(4), + I2 => ip2axi_rddata_captured_s2mm_cdc_tig(4), + I3 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0\, + I4 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[4]_i_2_n_0\, + I5 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0\, + O => ip2axi_rddata_captured(4) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[4]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0010000000000000" + ) + port map ( + I0 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, + I1 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, + I2 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, + I3 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, + I4 => p_4_in(3), + I5 => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(4), + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[4]_i_2_n_0\ + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0AAAAACCCCCAA0CC" + ) + port map ( + I0 => ip2axi_rddata_captured_s2mm_cdc_tig(5), + I1 => ip2axi_rddata_captured_mm2s_cdc_tig(5), + I2 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, + I3 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, + I4 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, + I5 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, + O => ip2axi_rddata_captured(5) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_2_n_0\, + I1 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0\, + I2 => ip2axi_rddata_captured_s2mm_cdc_tig(6), + I3 => ip2axi_rddata_captured_mm2s_cdc_tig(6), + I4 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0\, + O => ip2axi_rddata_captured(6) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[7]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0AAAAACCCCCAA0CC" + ) + port map ( + I0 => ip2axi_rddata_captured_s2mm_cdc_tig(7), + I1 => ip2axi_rddata_captured_mm2s_cdc_tig(7), + I2 => \axi2ip_rdaddr_captured_reg_n_0_[4]\, + I3 => \axi2ip_rdaddr_captured_reg_n_0_[5]\, + I4 => \axi2ip_rdaddr_captured_reg_n_0_[6]\, + I5 => \axi2ip_rdaddr_captured_reg_n_0_[7]\, + O => ip2axi_rddata_captured(7) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[8]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0\, + I1 => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(0), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0\, + I3 => ip2axi_rddata_captured_mm2s_cdc_tig(8), + I4 => ip2axi_rddata_captured_s2mm_cdc_tig(8), + I5 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0\, + O => ip2axi_rddata_captured(8) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[9]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[28]_i_2_n_0\, + I1 => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(1), + I2 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_4_n_0\, + I3 => ip2axi_rddata_captured_mm2s_cdc_tig(9), + I4 => ip2axi_rddata_captured_s2mm_cdc_tig(9), + I5 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1[30]_i_3_n_0\, + O => ip2axi_rddata_captured(9) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(0), + Q => s_axi_lite_rdata(0), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(10), + Q => s_axi_lite_rdata(10), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(11), + Q => s_axi_lite_rdata(11), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(12), + Q => s_axi_lite_rdata(12), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(13), + Q => s_axi_lite_rdata(13), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(14), + Q => s_axi_lite_rdata(14), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(15), + Q => s_axi_lite_rdata(15), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(16), + Q => s_axi_lite_rdata(16), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(17), + Q => s_axi_lite_rdata(17), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(18), + Q => s_axi_lite_rdata(18), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(19), + Q => s_axi_lite_rdata(19), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(1), + Q => s_axi_lite_rdata(1), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(20), + Q => s_axi_lite_rdata(20), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(21), + Q => s_axi_lite_rdata(21), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(22), + Q => s_axi_lite_rdata(22), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(23), + Q => s_axi_lite_rdata(23), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(24), + Q => s_axi_lite_rdata(24), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(25), + Q => s_axi_lite_rdata(25), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(26), + Q => s_axi_lite_rdata(26), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(27), + Q => s_axi_lite_rdata(27), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(28), + Q => s_axi_lite_rdata(28), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(29), + Q => s_axi_lite_rdata(29), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(2), + Q => s_axi_lite_rdata(2), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(30), + Q => s_axi_lite_rdata(30), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(31), + Q => s_axi_lite_rdata(31), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(3), + Q => s_axi_lite_rdata(3), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(4), + Q => s_axi_lite_rdata(4), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(5), + Q => s_axi_lite_rdata(5), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(6), + Q => s_axi_lite_rdata(6), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(7), + Q => s_axi_lite_rdata(7), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(8), + Q => s_axi_lite_rdata(8), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_d1_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => ip2axi_rddata_captured(9), + Q => s_axi_lite_rdata(9), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(0), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(0), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(10), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(10), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(11), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(11), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(12), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(12), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(13), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(13), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(14), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(14), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(15), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(15), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(16), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(16), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(17), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(17), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(18), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(18), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(19), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(19), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(1), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(1), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(20), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(20), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(21), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(21), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(22), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(22), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(23), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(23), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(24), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(24), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(25), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(25), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(26), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(26), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(27), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(27), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(28), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(28), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(29), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(29), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(2), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(2), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(30), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(30), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(31), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(31), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(3), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(3), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(4), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(4), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(5), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(5), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(6), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(6), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(7), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(7), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(8), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(8), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_mm2s_cdc_tig_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => mm2s_ip2axi_rddata_d1(9), + Q => ip2axi_rddata_captured_mm2s_cdc_tig(9), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(0), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(0), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(10), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(10), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(11), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(11), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(12), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(12), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(13), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(13), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(14), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(14), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(15), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(15), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(16), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(16), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(17), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(17), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(18), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(18), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(19), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(19), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(1), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(1), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(20), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(20), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(21), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(21), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(22), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(22), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(23), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(23), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(24), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(24), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(25), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(25), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(26), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(26), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(27), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(27), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(28), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(28), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(29), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(29), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(2), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(2), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(30), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(30), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(31), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(31), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(3), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(3), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(4), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(4), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(5), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(5), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(6), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(6), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(7), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(7), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(8), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(8), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.ip2axi_rddata_captured_s2mm_cdc_tig_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s2mm_ip2axi_rddata_d1(9), + Q => ip2axi_rddata_captured_s2mm_cdc_tig(9), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(0), + Q => mm2s_axi2ip_wrdata_cdc_tig(0), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(10), + Q => mm2s_axi2ip_wrdata_cdc_tig(10), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(11), + Q => mm2s_axi2ip_wrdata_cdc_tig(11), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(12), + Q => mm2s_axi2ip_wrdata_cdc_tig(12), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(13), + Q => mm2s_axi2ip_wrdata_cdc_tig(13), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(14), + Q => mm2s_axi2ip_wrdata_cdc_tig(14), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(15), + Q => mm2s_axi2ip_wrdata_cdc_tig(15), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(16), + Q => mm2s_axi2ip_wrdata_cdc_tig(16), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(17), + Q => mm2s_axi2ip_wrdata_cdc_tig(17), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(18), + Q => mm2s_axi2ip_wrdata_cdc_tig(18), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(19), + Q => mm2s_axi2ip_wrdata_cdc_tig(19), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(1), + Q => mm2s_axi2ip_wrdata_cdc_tig(1), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(20), + Q => mm2s_axi2ip_wrdata_cdc_tig(20), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(21), + Q => mm2s_axi2ip_wrdata_cdc_tig(21), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(22), + Q => mm2s_axi2ip_wrdata_cdc_tig(22), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(23), + Q => mm2s_axi2ip_wrdata_cdc_tig(23), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(24), + Q => mm2s_axi2ip_wrdata_cdc_tig(24), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(25), + Q => mm2s_axi2ip_wrdata_cdc_tig(25), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(26), + Q => mm2s_axi2ip_wrdata_cdc_tig(26), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(27), + Q => mm2s_axi2ip_wrdata_cdc_tig(27), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(28), + Q => mm2s_axi2ip_wrdata_cdc_tig(28), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(29), + Q => mm2s_axi2ip_wrdata_cdc_tig(29), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(2), + Q => mm2s_axi2ip_wrdata_cdc_tig(2), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(30), + Q => mm2s_axi2ip_wrdata_cdc_tig(30), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(31), + Q => mm2s_axi2ip_wrdata_cdc_tig(31), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(3), + Q => mm2s_axi2ip_wrdata_cdc_tig(3), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(4), + Q => mm2s_axi2ip_wrdata_cdc_tig(4), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(5), + Q => mm2s_axi2ip_wrdata_cdc_tig(5), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(6), + Q => mm2s_axi2ip_wrdata_cdc_tig(6), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(7), + Q => mm2s_axi2ip_wrdata_cdc_tig(7), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(8), + Q => mm2s_axi2ip_wrdata_cdc_tig(8), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => wdata(9), + Q => mm2s_axi2ip_wrdata_cdc_tig(9), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(0), + Q => mm2s_ip2axi_rddata_d1(0), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(10), + Q => mm2s_ip2axi_rddata_d1(10), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(11), + Q => mm2s_ip2axi_rddata_d1(11), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(12), + Q => mm2s_ip2axi_rddata_d1(12), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(13), + Q => mm2s_ip2axi_rddata_d1(13), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(14), + Q => mm2s_ip2axi_rddata_d1(14), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(15), + Q => mm2s_ip2axi_rddata_d1(15), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(16), + Q => mm2s_ip2axi_rddata_d1(16), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(17), + Q => mm2s_ip2axi_rddata_d1(17), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(18), + Q => mm2s_ip2axi_rddata_d1(18), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(19), + Q => mm2s_ip2axi_rddata_d1(19), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(1), + Q => mm2s_ip2axi_rddata_d1(1), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(20), + Q => mm2s_ip2axi_rddata_d1(20), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(21), + Q => mm2s_ip2axi_rddata_d1(21), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(22), + Q => mm2s_ip2axi_rddata_d1(22), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(23), + Q => mm2s_ip2axi_rddata_d1(23), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(24), + Q => mm2s_ip2axi_rddata_d1(24), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(25), + Q => mm2s_ip2axi_rddata_d1(25), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(26), + Q => mm2s_ip2axi_rddata_d1(26), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(27), + Q => mm2s_ip2axi_rddata_d1(27), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(28), + Q => mm2s_ip2axi_rddata_d1(28), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(29), + Q => mm2s_ip2axi_rddata_d1(29), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(2), + Q => mm2s_ip2axi_rddata_d1(2), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(30), + Q => mm2s_ip2axi_rddata_d1(30), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(31), + Q => mm2s_ip2axi_rddata_d1(31), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(3), + Q => mm2s_ip2axi_rddata_d1(3), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(4), + Q => mm2s_ip2axi_rddata_d1(4), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(5), + Q => mm2s_ip2axi_rddata_d1(5), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(6), + Q => mm2s_ip2axi_rddata_d1(6), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(7), + Q => mm2s_ip2axi_rddata_d1(7), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(8), + Q => mm2s_ip2axi_rddata_d1(8), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(9), + Q => mm2s_ip2axi_rddata_d1(9), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.prepare_wrce_d1_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => lite_wr_addr_phase_finished_data_phase_started, + I1 => wvalid, + O => prepare_wrce + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.prepare_wrce_d1_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => prepare_wrce, + Q => prepare_wrce_d1, + R => SR(0) + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.prepare_wrce_pulse_lite_d6_reg_srl6\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '0', + A2 => '1', + A3 => '0', + CE => '1', + CLK => s_axi_lite_aclk, + D => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.prepare_wrce_pulse_lite_d6_reg_srl6_i_1_n_0\, + Q => prepare_wrce_pulse_lite_d6 + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.prepare_wrce_pulse_lite_d6_reg_srl6_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => wvalid, + I1 => lite_wr_addr_phase_finished_data_phase_started, + I2 => prepare_wrce_d1, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.prepare_wrce_pulse_lite_d6_reg_srl6_i_1_n_0\ + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.rvalid_out_i_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0C88" + ) + port map ( + I0 => \^s_axi_lite_arready\, + I1 => s_axi_lite_resetn, + I2 => s_axi_lite_rready, + I3 => \^s_axi_lite_rvalid\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.rvalid_out_i_i_1_n_0\ + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.rvalid_out_i_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.rvalid_out_i_i_1_n_0\, + Q => \^s_axi_lite_rvalid\, + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(0), + Q => s2mm_axi2ip_wrdata_cdc_tig(0), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(10), + Q => s2mm_axi2ip_wrdata_cdc_tig(10), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(11), + Q => s2mm_axi2ip_wrdata_cdc_tig(11), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(12), + Q => s2mm_axi2ip_wrdata_cdc_tig(12), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(13), + Q => s2mm_axi2ip_wrdata_cdc_tig(13), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(14), + Q => s2mm_axi2ip_wrdata_cdc_tig(14), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(15), + Q => s2mm_axi2ip_wrdata_cdc_tig(15), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(16), + Q => s2mm_axi2ip_wrdata_cdc_tig(16), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(17), + Q => s2mm_axi2ip_wrdata_cdc_tig(17), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(18), + Q => s2mm_axi2ip_wrdata_cdc_tig(18), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(19), + Q => s2mm_axi2ip_wrdata_cdc_tig(19), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(1), + Q => s2mm_axi2ip_wrdata_cdc_tig(1), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(20), + Q => s2mm_axi2ip_wrdata_cdc_tig(20), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(21), + Q => s2mm_axi2ip_wrdata_cdc_tig(21), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(22), + Q => s2mm_axi2ip_wrdata_cdc_tig(22), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(23), + Q => s2mm_axi2ip_wrdata_cdc_tig(23), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(24), + Q => s2mm_axi2ip_wrdata_cdc_tig(24), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(25), + Q => s2mm_axi2ip_wrdata_cdc_tig(25), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(26), + Q => s2mm_axi2ip_wrdata_cdc_tig(26), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(27), + Q => s2mm_axi2ip_wrdata_cdc_tig(27), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(28), + Q => s2mm_axi2ip_wrdata_cdc_tig(28), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(29), + Q => s2mm_axi2ip_wrdata_cdc_tig(29), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(2), + Q => s2mm_axi2ip_wrdata_cdc_tig(2), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(30), + Q => s2mm_axi2ip_wrdata_cdc_tig(30), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(31), + Q => s2mm_axi2ip_wrdata_cdc_tig(31), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(3), + Q => s2mm_axi2ip_wrdata_cdc_tig(3), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(4), + Q => s2mm_axi2ip_wrdata_cdc_tig(4), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(5), + Q => s2mm_axi2ip_wrdata_cdc_tig(5), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(6), + Q => s2mm_axi2ip_wrdata_cdc_tig(6), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(7), + Q => s2mm_axi2ip_wrdata_cdc_tig(7), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(8), + Q => s2mm_axi2ip_wrdata_cdc_tig(8), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => wdata(9), + Q => s2mm_axi2ip_wrdata_cdc_tig(9), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(0), + Q => s2mm_ip2axi_rddata_d1(0), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(10), + Q => s2mm_ip2axi_rddata_d1(10), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(11), + Q => s2mm_ip2axi_rddata_d1(11), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(12), + Q => s2mm_ip2axi_rddata_d1(12), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(13), + Q => s2mm_ip2axi_rddata_d1(13), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(14), + Q => s2mm_ip2axi_rddata_d1(14), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(15), + Q => s2mm_ip2axi_rddata_d1(15), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(16), + Q => s2mm_ip2axi_rddata_d1(16), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(17), + Q => s2mm_ip2axi_rddata_d1(17), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(18), + Q => s2mm_ip2axi_rddata_d1(18), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(19), + Q => s2mm_ip2axi_rddata_d1(19), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(1), + Q => s2mm_ip2axi_rddata_d1(1), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(20), + Q => s2mm_ip2axi_rddata_d1(20), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(21), + Q => s2mm_ip2axi_rddata_d1(21), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(22), + Q => s2mm_ip2axi_rddata_d1(22), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(23), + Q => s2mm_ip2axi_rddata_d1(23), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(24), + Q => s2mm_ip2axi_rddata_d1(24), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(25), + Q => s2mm_ip2axi_rddata_d1(25), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(26), + Q => s2mm_ip2axi_rddata_d1(26), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(27), + Q => s2mm_ip2axi_rddata_d1(27), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(28), + Q => s2mm_ip2axi_rddata_d1(28), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(29), + Q => s2mm_ip2axi_rddata_d1(29), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(2), + Q => s2mm_ip2axi_rddata_d1(2), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(30), + Q => s2mm_ip2axi_rddata_d1(30), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(31), + Q => s2mm_ip2axi_rddata_d1(31), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(3), + Q => s2mm_ip2axi_rddata_d1(3), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(4), + Q => s2mm_ip2axi_rddata_d1(4), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(5), + Q => s2mm_ip2axi_rddata_d1(5), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(6), + Q => s2mm_ip2axi_rddata_d1(6), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(7), + Q => s2mm_ip2axi_rddata_d1(7), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(8), + Q => s2mm_ip2axi_rddata_d1(8), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(9), + Q => s2mm_ip2axi_rddata_d1(9), + R => '0' + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.sig_arvalid_arrived_d4_reg_srl3\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '0', + A1 => '1', + A2 => '0', + A3 => '0', + CE => '1', + CLK => s_axi_lite_aclk, + D => sig_arvalid_arrived_d1, + Q => sig_arvalid_arrived_d4 + ); +\GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.wready_out_i_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => prepare_wrce_pulse_lite_d6, + Q => \^s_axi_lite_wready\, + R => SR(0) + ); +\araddr_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_araddr(0), + Q => \p_2_in__0\(0), + R => SR(0) + ); +\araddr_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_araddr(1), + Q => \p_2_in__0\(1), + R => SR(0) + ); +\araddr_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_araddr(2), + Q => \p_2_in__0\(2), + R => SR(0) + ); +\araddr_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_araddr(3), + Q => \p_2_in__0\(3), + R => SR(0) + ); +\araddr_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_araddr(4), + Q => \p_2_in__0\(4), + R => SR(0) + ); +\araddr_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_araddr(5), + Q => \p_2_in__0\(5), + R => SR(0) + ); +arvalid_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_arvalid, + Q => arvalid, + R => SR(0) + ); +\awaddr_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_awaddr(0), + Q => awaddr(2), + R => SR(0) + ); +\awaddr_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_awaddr(1), + Q => awaddr(3), + R => SR(0) + ); +\awaddr_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_awaddr(2), + Q => awaddr(4), + R => SR(0) + ); +\awaddr_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_awaddr(3), + Q => awaddr(5), + R => SR(0) + ); +\awaddr_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_awaddr(4), + Q => awaddr(6), + R => SR(0) + ); +\awaddr_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_awaddr(5), + Q => awaddr(7), + R => SR(0) + ); +awready_out_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \sig_awvalid_detected__0\, + Q => \^s_axi_lite_awready\, + R => SR(0) + ); +awvalid_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_awvalid, + Q => awvalid, + R => SR(0) + ); +\axi2ip_rdaddr_captured_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => \sig_arvalid_detected__0\, + D => \p_2_in__0\(0), + Q => p_4_in(2), + R => SR(0) + ); +\axi2ip_rdaddr_captured_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => \sig_arvalid_detected__0\, + D => \p_2_in__0\(1), + Q => p_4_in(3), + R => SR(0) + ); +\axi2ip_rdaddr_captured_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => \sig_arvalid_detected__0\, + D => \p_2_in__0\(2), + Q => \axi2ip_rdaddr_captured_reg_n_0_[4]\, + R => SR(0) + ); +\axi2ip_rdaddr_captured_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => \sig_arvalid_detected__0\, + D => \p_2_in__0\(3), + Q => \axi2ip_rdaddr_captured_reg_n_0_[5]\, + R => SR(0) + ); +\axi2ip_rdaddr_captured_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => \sig_arvalid_detected__0\, + D => \p_2_in__0\(4), + Q => \axi2ip_rdaddr_captured_reg_n_0_[6]\, + R => SR(0) + ); +\axi2ip_rdaddr_captured_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => \sig_arvalid_detected__0\, + D => \p_2_in__0\(5), + Q => \axi2ip_rdaddr_captured_reg_n_0_[7]\, + R => SR(0) + ); +\axi2ip_wraddr_captured_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => \sig_awvalid_detected__0\, + D => awaddr(2), + Q => axi2ip_wraddr_captured(2), + R => SR(0) + ); +\axi2ip_wraddr_captured_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => \sig_awvalid_detected__0\, + D => awaddr(3), + Q => axi2ip_wraddr_captured(3), + R => SR(0) + ); +\axi2ip_wraddr_captured_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => \sig_awvalid_detected__0\, + D => awaddr(4), + Q => axi2ip_wraddr_captured(4), + R => SR(0) + ); +\axi2ip_wraddr_captured_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => \sig_awvalid_detected__0\, + D => awaddr(5), + Q => axi2ip_wraddr_captured(5), + R => SR(0) + ); +\axi2ip_wraddr_captured_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => \sig_awvalid_detected__0\, + D => awaddr(6), + Q => axi2ip_wraddr_captured(6), + R => SR(0) + ); +\axi2ip_wraddr_captured_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => \sig_awvalid_detected__0\, + D => awaddr(7), + Q => axi2ip_wraddr_captured(7), + R => SR(0) + ); +bvalid_out_i_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"0C88" + ) + port map ( + I0 => \^s_axi_lite_wready\, + I1 => s_axi_lite_resetn, + I2 => s_axi_lite_bready, + I3 => \^s_axi_lite_bvalid\, + O => bvalid_out_i_i_1_n_0 + ); +bvalid_out_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => bvalid_out_i_i_1_n_0, + Q => \^s_axi_lite_bvalid\, + R => '0' + ); +ip2axi_rddata_int_inferred_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_33_n_0, + I1 => ip2axi_rddata_int_inferred_i_34_n_0, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(18), + I3 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\, + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(28), + O => in0(28) + ); +ip2axi_rddata_int_inferred_i_10: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_44_n_0, + I1 => ip2axi_rddata_int_inferred_i_34_n_0, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(9), + I3 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\, + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(19), + O => in0(19) + ); +\ip2axi_rddata_int_inferred_i_10__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_44__0_n_0\, + I1 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(22), + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(22), + I4 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(22) + ); +ip2axi_rddata_int_inferred_i_11: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_45_n_0, + I1 => ip2axi_rddata_int_inferred_i_34_n_0, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(8), + I3 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\, + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(18), + O => in0(18) + ); +\ip2axi_rddata_int_inferred_i_11__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_45__0_n_0\, + I1 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(21), + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(21), + I4 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(21) + ); +ip2axi_rddata_int_inferred_i_12: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_46_n_0, + I1 => ip2axi_rddata_int_inferred_i_34_n_0, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(7), + I3 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\, + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(17), + O => in0(17) + ); +\ip2axi_rddata_int_inferred_i_12__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_46__0_n_0\, + I1 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(20), + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(20), + I4 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(20) + ); +ip2axi_rddata_int_inferred_i_13: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_47_n_0, + I1 => ip2axi_rddata_int_inferred_i_34_n_0, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(6), + I3 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\, + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(16), + O => in0(16) + ); +\ip2axi_rddata_int_inferred_i_13__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_47__0_n_0\, + I1 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(19), + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(19), + I4 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(19) + ); +ip2axi_rddata_int_inferred_i_14: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_48_n_0, + I1 => ip2axi_rddata_int_inferred_i_34_n_0, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(5), + I3 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\, + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(15), + O => in0(15) + ); +\ip2axi_rddata_int_inferred_i_14__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_48__0_n_0\, + I1 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(18), + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(18), + I4 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(18) + ); +ip2axi_rddata_int_inferred_i_15: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_49_n_0, + I1 => ip2axi_rddata_int_inferred_i_34_n_0, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(4), + I3 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\, + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(14), + O => in0(14) + ); +\ip2axi_rddata_int_inferred_i_15__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_49__0_n_0\, + I1 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(17), + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(17), + I4 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(17) + ); +ip2axi_rddata_int_inferred_i_16: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_50_n_0, + I1 => ip2axi_rddata_int_inferred_i_34_n_0, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(3), + I3 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\, + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(13), + O => in0(13) + ); +\ip2axi_rddata_int_inferred_i_16__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_50__0_n_0\, + I1 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(16), + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(16), + I4 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(16) + ); +\ip2axi_rddata_int_inferred_i_17__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FEEE" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_51__0_n_0\, + I1 => \ip2axi_rddata_int_inferred_i_52__0_n_0\, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(15), + I3 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(15) + ); +ip2axi_rddata_int_inferred_i_18: unisim.vcomponents.LUT4 + generic map( + INIT => X"FEEE" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_54_n_0, + I1 => ip2axi_rddata_int_inferred_i_55_n_0, + I2 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(12), + O => in0(12) + ); +\ip2axi_rddata_int_inferred_i_18__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FEEE" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_53__0_n_0\, + I1 => \ip2axi_rddata_int_inferred_i_54__0_n_0\, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(14), + I3 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(14) + ); +ip2axi_rddata_int_inferred_i_19: unisim.vcomponents.LUT4 + generic map( + INIT => X"FEEE" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_56_n_0, + I1 => ip2axi_rddata_int_inferred_i_57_n_0, + I2 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(11), + O => in0(11) + ); +\ip2axi_rddata_int_inferred_i_19__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FEEE" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_55__0_n_0\, + I1 => \ip2axi_rddata_int_inferred_i_56__0_n_0\, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(13), + I3 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(13) + ); +\ip2axi_rddata_int_inferred_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_33__0_n_0\, + I1 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(31), + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(31), + I4 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(31) + ); +ip2axi_rddata_int_inferred_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_36_n_0, + I1 => ip2axi_rddata_int_inferred_i_34_n_0, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(17), + I3 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\, + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(27), + O => in0(27) + ); +ip2axi_rddata_int_inferred_i_20: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_58_n_0, + I1 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[12]_0\, + I2 => \reg_module_hsize_reg[12]\, + I3 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\, + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(10), + O => in0(10) + ); +\ip2axi_rddata_int_inferred_i_20__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFF888" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + I1 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(12), + I2 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(12), + I4 => \ip2axi_rddata_int_inferred_i_57__0_n_0\, + I5 => \ip2axi_rddata_int_inferred_i_58__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(12) + ); +ip2axi_rddata_int_inferred_i_21: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[12]_0\, + I1 => \reg_module_hsize_reg[11]\, + I2 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(9), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(9), + I5 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\, + O => in0(9) + ); +\ip2axi_rddata_int_inferred_i_21__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFF888" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + I1 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(11), + I2 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(11), + I4 => \ip2axi_rddata_int_inferred_i_59__0_n_0\, + I5 => \ip2axi_rddata_int_inferred_i_60__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(11) + ); +ip2axi_rddata_int_inferred_i_22: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[12]_0\, + I1 => \reg_module_hsize_reg[10]\, + I2 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(8), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(8), + I5 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\, + O => in0(8) + ); +\ip2axi_rddata_int_inferred_i_22__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FEEE" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_61__0_n_0\, + I1 => \ip2axi_rddata_int_inferred_i_62__0_n_0\, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(10), + I3 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(10) + ); +ip2axi_rddata_int_inferred_i_23: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[12]_0\, + I1 => \reg_module_hsize_reg[9]\, + I2 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(7), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(7), + I5 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\, + O => in0(7) + ); +\ip2axi_rddata_int_inferred_i_23__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FEEE" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_63__0_n_0\, + I1 => \ip2axi_rddata_int_inferred_i_64__0_n_0\, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(9), + I3 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(9) + ); +ip2axi_rddata_int_inferred_i_24: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[12]_0\, + I1 => \reg_module_hsize_reg[8]\, + I2 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(6), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(6), + I5 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\, + O => in0(6) + ); +\ip2axi_rddata_int_inferred_i_24__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFF888" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + I1 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(8), + I2 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(8), + I4 => \ip2axi_rddata_int_inferred_i_65__0_n_0\, + I5 => \ip2axi_rddata_int_inferred_i_66__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(8) + ); +ip2axi_rddata_int_inferred_i_25: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[12]_0\, + I1 => \reg_module_hsize_reg[7]\, + I2 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(5), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(5), + I5 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\, + O => in0(5) + ); +\ip2axi_rddata_int_inferred_i_25__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FEEE" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_67__0_n_0\, + I1 => \ip2axi_rddata_int_inferred_i_68__0_n_0\, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(7), + I3 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(7) + ); +ip2axi_rddata_int_inferred_i_26: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_67_n_0, + I1 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[12]_0\, + I2 => \reg_module_hsize_reg[6]\, + I3 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\, + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(4), + O => in0(4) + ); +\ip2axi_rddata_int_inferred_i_26__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFF888" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + I1 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(6), + I2 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(6), + I4 => \ip2axi_rddata_int_inferred_i_69__0_n_0\, + I5 => \ip2axi_rddata_int_inferred_i_70__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(6) + ); +ip2axi_rddata_int_inferred_i_27: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_69_n_0, + I1 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[12]_0\, + I2 => \reg_module_hsize_reg[5]\, + I3 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\, + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(3), + O => in0(3) + ); +\ip2axi_rddata_int_inferred_i_27__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFF888" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + I1 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(5), + I2 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(5), + I4 => \ip2axi_rddata_int_inferred_i_71__0_n_0\, + I5 => \ip2axi_rddata_int_inferred_i_72__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(5) + ); +ip2axi_rddata_int_inferred_i_28: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_71_n_0, + I1 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[12]_0\, + I2 => \reg_module_hsize_reg[4]\, + I3 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\, + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(2), + O => in0(2) + ); +\ip2axi_rddata_int_inferred_i_28__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFF888" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + I1 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(4), + I2 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(4), + I4 => \ip2axi_rddata_int_inferred_i_73__0_n_0\, + I5 => \ip2axi_rddata_int_inferred_i_74__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(4) + ); +ip2axi_rddata_int_inferred_i_29: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[12]_0\, + I1 => \reg_module_hsize_reg[3]\, + I2 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(1), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(1), + I5 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\, + O => in0(1) + ); +\ip2axi_rddata_int_inferred_i_29__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFF888" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + I1 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(3), + I2 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(3), + I4 => \ip2axi_rddata_int_inferred_i_75__0_n_0\, + I5 => \ip2axi_rddata_int_inferred_i_76__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(3) + ); +\ip2axi_rddata_int_inferred_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_36__0_n_0\, + I1 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(30), + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(30), + I4 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(30) + ); +ip2axi_rddata_int_inferred_i_3: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_37_n_0, + I1 => ip2axi_rddata_int_inferred_i_34_n_0, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(16), + I3 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\, + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(26), + O => in0(26) + ); +\ip2axi_rddata_int_inferred_i_30__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFF888" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + I1 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(2), + I2 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(2), + I4 => \ip2axi_rddata_int_inferred_i_77__0_n_0\, + I5 => \ip2axi_rddata_int_inferred_i_78__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(2) + ); +\ip2axi_rddata_int_inferred_i_31__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFF888" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + I1 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(1), + I2 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(1), + I4 => \ip2axi_rddata_int_inferred_i_79__0_n_0\, + I5 => \ip2axi_rddata_int_inferred_i_80__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(1) + ); +ip2axi_rddata_int_inferred_i_32: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_76_n_0, + I1 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[12]_0\, + I2 => \reg_module_hsize_reg[0]\, + I3 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\, + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(0), + O => in0(0) + ); +\ip2axi_rddata_int_inferred_i_32__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_81_n_0, + I1 => ip2axi_rddata_int_inferred_i_82_n_0, + I2 => ip2axi_rddata_int_inferred_i_83_n_0, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(0) + ); +ip2axi_rddata_int_inferred_i_33: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[15]_1\, + I1 => p_71_out(17), + I2 => ip2axi_rddata_int_inferred_i_78_n_0, + I3 => ch1_irqdelay_status(7), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(28), + I5 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\, + O => ip2axi_rddata_int_inferred_i_33_n_0 + ); +\ip2axi_rddata_int_inferred_i_33__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_84_n_0, + I1 => ch2_irqdelay_status(7), + I2 => ip2axi_rddata_int_inferred_i_85_n_0, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(31), + I4 => s2mm_dmacr(22), + I5 => ip2axi_rddata_int_inferred_i_86_n_0, + O => \ip2axi_rddata_int_inferred_i_33__0_n_0\ + ); +ip2axi_rddata_int_inferred_i_34: unisim.vcomponents.LUT6 + generic map( + INIT => X"1000000000000000" + ) + port map ( + I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), + I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), + I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), + I3 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), + I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), + I5 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), + O => ip2axi_rddata_int_inferred_i_34_n_0 + ); +\ip2axi_rddata_int_inferred_i_34__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0010000000000000" + ) + port map ( + I0 => axi2ip_rdaddr_captured_s2mm_cdc_tig(2), + I1 => axi2ip_rdaddr_captured_s2mm_cdc_tig(3), + I2 => axi2ip_rdaddr_captured_s2mm_cdc_tig(5), + I3 => axi2ip_rdaddr_captured_s2mm_cdc_tig(6), + I4 => axi2ip_rdaddr_captured_s2mm_cdc_tig(4), + I5 => axi2ip_rdaddr_captured_s2mm_cdc_tig(7), + O => \ip2axi_rddata_int_inferred_i_34__0_n_0\ + ); +ip2axi_rddata_int_inferred_i_35: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000040" + ) + port map ( + I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), + I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), + I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), + I3 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), + I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), + I5 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), + O => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\ + ); +\ip2axi_rddata_int_inferred_i_35__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000800000" + ) + port map ( + I0 => axi2ip_rdaddr_captured_s2mm_cdc_tig(7), + I1 => axi2ip_rdaddr_captured_s2mm_cdc_tig(2), + I2 => axi2ip_rdaddr_captured_s2mm_cdc_tig(4), + I3 => axi2ip_rdaddr_captured_s2mm_cdc_tig(6), + I4 => axi2ip_rdaddr_captured_s2mm_cdc_tig(5), + I5 => axi2ip_rdaddr_captured_s2mm_cdc_tig(3), + O => \ip2axi_rddata_int_inferred_i_35__0_n_0\ + ); +ip2axi_rddata_int_inferred_i_36: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[15]_1\, + I1 => p_71_out(16), + I2 => ip2axi_rddata_int_inferred_i_78_n_0, + I3 => ch1_irqdelay_status(6), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(27), + I5 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\, + O => ip2axi_rddata_int_inferred_i_36_n_0 + ); +\ip2axi_rddata_int_inferred_i_36__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_84_n_0, + I1 => ch2_irqdelay_status(6), + I2 => ip2axi_rddata_int_inferred_i_85_n_0, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(30), + I4 => s2mm_dmacr(21), + I5 => ip2axi_rddata_int_inferred_i_86_n_0, + O => \ip2axi_rddata_int_inferred_i_36__0_n_0\ + ); +ip2axi_rddata_int_inferred_i_37: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[15]_1\, + I1 => p_71_out(15), + I2 => ip2axi_rddata_int_inferred_i_78_n_0, + I3 => ch1_irqdelay_status(5), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(26), + I5 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\, + O => ip2axi_rddata_int_inferred_i_37_n_0 + ); +\ip2axi_rddata_int_inferred_i_37__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_84_n_0, + I1 => ch2_irqdelay_status(5), + I2 => ip2axi_rddata_int_inferred_i_85_n_0, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(29), + I4 => s2mm_dmacr(20), + I5 => ip2axi_rddata_int_inferred_i_86_n_0, + O => \ip2axi_rddata_int_inferred_i_37__0_n_0\ + ); +ip2axi_rddata_int_inferred_i_38: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[15]_1\, + I1 => p_71_out(14), + I2 => ip2axi_rddata_int_inferred_i_78_n_0, + I3 => ch1_irqdelay_status(4), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(25), + I5 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\, + O => ip2axi_rddata_int_inferred_i_38_n_0 + ); +\ip2axi_rddata_int_inferred_i_38__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_84_n_0, + I1 => ch2_irqdelay_status(4), + I2 => ip2axi_rddata_int_inferred_i_85_n_0, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(28), + I4 => s2mm_dmacr(19), + I5 => ip2axi_rddata_int_inferred_i_86_n_0, + O => \ip2axi_rddata_int_inferred_i_38__0_n_0\ + ); +ip2axi_rddata_int_inferred_i_39: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[15]_1\, + I1 => p_71_out(13), + I2 => ip2axi_rddata_int_inferred_i_78_n_0, + I3 => ch1_irqdelay_status(3), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(24), + I5 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\, + O => ip2axi_rddata_int_inferred_i_39_n_0 + ); +\ip2axi_rddata_int_inferred_i_39__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_84_n_0, + I1 => ch2_irqdelay_status(3), + I2 => ip2axi_rddata_int_inferred_i_85_n_0, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(27), + I4 => s2mm_dmacr(18), + I5 => ip2axi_rddata_int_inferred_i_86_n_0, + O => \ip2axi_rddata_int_inferred_i_39__0_n_0\ + ); +\ip2axi_rddata_int_inferred_i_3__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_37__0_n_0\, + I1 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(29), + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(29), + I4 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(29) + ); +ip2axi_rddata_int_inferred_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_38_n_0, + I1 => ip2axi_rddata_int_inferred_i_34_n_0, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(15), + I3 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\, + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(25), + O => in0(25) + ); +ip2axi_rddata_int_inferred_i_40: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[15]_1\, + I1 => p_71_out(12), + I2 => ip2axi_rddata_int_inferred_i_78_n_0, + I3 => ch1_irqdelay_status(2), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(23), + I5 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\, + O => ip2axi_rddata_int_inferred_i_40_n_0 + ); +\ip2axi_rddata_int_inferred_i_40__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_84_n_0, + I1 => ch2_irqdelay_status(2), + I2 => ip2axi_rddata_int_inferred_i_85_n_0, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(26), + I4 => s2mm_dmacr(17), + I5 => ip2axi_rddata_int_inferred_i_86_n_0, + O => \ip2axi_rddata_int_inferred_i_40__0_n_0\ + ); +ip2axi_rddata_int_inferred_i_41: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[15]_1\, + I1 => p_71_out(11), + I2 => ip2axi_rddata_int_inferred_i_78_n_0, + I3 => ch1_irqdelay_status(1), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(22), + I5 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\, + O => ip2axi_rddata_int_inferred_i_41_n_0 + ); +\ip2axi_rddata_int_inferred_i_41__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_84_n_0, + I1 => ch2_irqdelay_status(1), + I2 => ip2axi_rddata_int_inferred_i_85_n_0, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(25), + I4 => s2mm_dmacr(16), + I5 => ip2axi_rddata_int_inferred_i_86_n_0, + O => \ip2axi_rddata_int_inferred_i_41__0_n_0\ + ); +ip2axi_rddata_int_inferred_i_42: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[15]_1\, + I1 => p_71_out(10), + I2 => ip2axi_rddata_int_inferred_i_78_n_0, + I3 => ch1_irqdelay_status(0), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(21), + I5 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\, + O => ip2axi_rddata_int_inferred_i_42_n_0 + ); +\ip2axi_rddata_int_inferred_i_42__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_84_n_0, + I1 => ch2_irqdelay_status(0), + I2 => ip2axi_rddata_int_inferred_i_85_n_0, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(24), + I4 => s2mm_dmacr(15), + I5 => ip2axi_rddata_int_inferred_i_86_n_0, + O => \ip2axi_rddata_int_inferred_i_42__0_n_0\ + ); +ip2axi_rddata_int_inferred_i_43: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[15]_1\, + I1 => p_71_out(9), + I2 => ip2axi_rddata_int_inferred_i_78_n_0, + I3 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\(7), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(20), + I5 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\, + O => ip2axi_rddata_int_inferred_i_43_n_0 + ); +\ip2axi_rddata_int_inferred_i_43__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_84_n_0, + I1 => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]\(7), + I2 => ip2axi_rddata_int_inferred_i_85_n_0, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(23), + I4 => s2mm_dmacr(14), + I5 => ip2axi_rddata_int_inferred_i_86_n_0, + O => \ip2axi_rddata_int_inferred_i_43__0_n_0\ + ); +ip2axi_rddata_int_inferred_i_44: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[15]_1\, + I1 => p_71_out(8), + I2 => ip2axi_rddata_int_inferred_i_78_n_0, + I3 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\(6), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(19), + I5 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\, + O => ip2axi_rddata_int_inferred_i_44_n_0 + ); +\ip2axi_rddata_int_inferred_i_44__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_84_n_0, + I1 => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]\(6), + I2 => ip2axi_rddata_int_inferred_i_85_n_0, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(22), + I4 => s2mm_dmacr(13), + I5 => ip2axi_rddata_int_inferred_i_86_n_0, + O => \ip2axi_rddata_int_inferred_i_44__0_n_0\ + ); +ip2axi_rddata_int_inferred_i_45: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[15]_1\, + I1 => p_71_out(7), + I2 => ip2axi_rddata_int_inferred_i_78_n_0, + I3 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\(5), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(18), + I5 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\, + O => ip2axi_rddata_int_inferred_i_45_n_0 + ); +\ip2axi_rddata_int_inferred_i_45__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_84_n_0, + I1 => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]\(5), + I2 => ip2axi_rddata_int_inferred_i_85_n_0, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(21), + I4 => s2mm_dmacr(12), + I5 => ip2axi_rddata_int_inferred_i_86_n_0, + O => \ip2axi_rddata_int_inferred_i_45__0_n_0\ + ); +ip2axi_rddata_int_inferred_i_46: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[15]_1\, + I1 => p_71_out(6), + I2 => ip2axi_rddata_int_inferred_i_78_n_0, + I3 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\(4), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(17), + I5 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\, + O => ip2axi_rddata_int_inferred_i_46_n_0 + ); +\ip2axi_rddata_int_inferred_i_46__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_84_n_0, + I1 => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]\(4), + I2 => ip2axi_rddata_int_inferred_i_85_n_0, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(20), + I4 => s2mm_dmacr(11), + I5 => ip2axi_rddata_int_inferred_i_86_n_0, + O => \ip2axi_rddata_int_inferred_i_46__0_n_0\ + ); +ip2axi_rddata_int_inferred_i_47: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[15]_1\, + I1 => p_71_out(5), + I2 => ip2axi_rddata_int_inferred_i_78_n_0, + I3 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\(3), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(16), + I5 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\, + O => ip2axi_rddata_int_inferred_i_47_n_0 + ); +\ip2axi_rddata_int_inferred_i_47__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_84_n_0, + I1 => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]\(3), + I2 => ip2axi_rddata_int_inferred_i_85_n_0, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(19), + I4 => s2mm_dmacr(10), + I5 => ip2axi_rddata_int_inferred_i_86_n_0, + O => \ip2axi_rddata_int_inferred_i_47__0_n_0\ + ); +ip2axi_rddata_int_inferred_i_48: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[15]_1\, + I1 => p_71_out(4), + I2 => ip2axi_rddata_int_inferred_i_78_n_0, + I3 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\(2), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(15), + I5 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\, + O => ip2axi_rddata_int_inferred_i_48_n_0 + ); +\ip2axi_rddata_int_inferred_i_48__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_84_n_0, + I1 => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]\(2), + I2 => ip2axi_rddata_int_inferred_i_85_n_0, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(18), + I4 => s2mm_dmacr(9), + I5 => ip2axi_rddata_int_inferred_i_86_n_0, + O => \ip2axi_rddata_int_inferred_i_48__0_n_0\ + ); +ip2axi_rddata_int_inferred_i_49: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[15]_1\, + I1 => p_71_out(3), + I2 => ip2axi_rddata_int_inferred_i_78_n_0, + I3 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\(1), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(14), + I5 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\, + O => ip2axi_rddata_int_inferred_i_49_n_0 + ); +\ip2axi_rddata_int_inferred_i_49__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_84_n_0, + I1 => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]\(1), + I2 => ip2axi_rddata_int_inferred_i_85_n_0, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(17), + I4 => s2mm_dmacr(8), + I5 => ip2axi_rddata_int_inferred_i_86_n_0, + O => \ip2axi_rddata_int_inferred_i_49__0_n_0\ + ); +\ip2axi_rddata_int_inferred_i_4__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_38__0_n_0\, + I1 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(28), + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(28), + I4 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(28) + ); +ip2axi_rddata_int_inferred_i_5: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_39_n_0, + I1 => ip2axi_rddata_int_inferred_i_34_n_0, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(14), + I3 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\, + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(24), + O => in0(24) + ); +ip2axi_rddata_int_inferred_i_50: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[15]_1\, + I1 => p_71_out(2), + I2 => ip2axi_rddata_int_inferred_i_78_n_0, + I3 => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\(0), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(13), + I5 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\, + O => ip2axi_rddata_int_inferred_i_50_n_0 + ); +\ip2axi_rddata_int_inferred_i_50__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_84_n_0, + I1 => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]\(0), + I2 => ip2axi_rddata_int_inferred_i_85_n_0, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(16), + I4 => s2mm_dmacr(7), + I5 => ip2axi_rddata_int_inferred_i_86_n_0, + O => \ip2axi_rddata_int_inferred_i_50__0_n_0\ + ); +\ip2axi_rddata_int_inferred_i_51__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_84_n_0, + I1 => lsize_more_err_reg_0, + I2 => ip2axi_rddata_int_inferred_i_87_n_0, + I3 => \reg_module_hsize_reg[15]_0\(15), + I4 => s2mm_dmacr(6), + I5 => ip2axi_rddata_int_inferred_i_86_n_0, + O => \ip2axi_rddata_int_inferred_i_51__0_n_0\ + ); +ip2axi_rddata_int_inferred_i_52: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000001" + ) + port map ( + I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), + I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), + I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), + I3 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), + I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), + I5 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), + O => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[15]_1\ + ); +\ip2axi_rddata_int_inferred_i_52__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_88_n_0, + I1 => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(15), + I2 => ip2axi_rddata_int_inferred_i_85_n_0, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(15), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(15), + I5 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + O => \ip2axi_rddata_int_inferred_i_52__0_n_0\ + ); +ip2axi_rddata_int_inferred_i_53: unisim.vcomponents.LUT6 + generic map( + INIT => X"A8288808A0208000" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[12]_0\, + I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), + I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(2), + I4 => \reg_module_hsize_reg[15]\(2), + I5 => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(2), + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_0\ + ); +\ip2axi_rddata_int_inferred_i_53__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_84_n_0, + I1 => err_irq_reg_0, + I2 => ip2axi_rddata_int_inferred_i_87_n_0, + I3 => \reg_module_hsize_reg[15]_0\(14), + I4 => \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14]\(6), + I5 => ip2axi_rddata_int_inferred_i_86_n_0, + O => \ip2axi_rddata_int_inferred_i_53__0_n_0\ + ); +ip2axi_rddata_int_inferred_i_54: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[15]_1\, + I1 => \M_GEN_DMACR_REGISTER.dmacr_i_reg[14]\(4), + I2 => ip2axi_rddata_int_inferred_i_78_n_0, + I3 => err_irq_reg, + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(12), + I5 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\, + O => ip2axi_rddata_int_inferred_i_54_n_0 + ); +\ip2axi_rddata_int_inferred_i_54__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_88_n_0, + I1 => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(14), + I2 => ip2axi_rddata_int_inferred_i_85_n_0, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(14), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(14), + I5 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + O => \ip2axi_rddata_int_inferred_i_54__0_n_0\ + ); +ip2axi_rddata_int_inferred_i_55: unisim.vcomponents.LUT6 + generic map( + INIT => X"A8288808A0208000" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[12]_0\, + I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), + I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(1), + I4 => \reg_module_hsize_reg[15]\(1), + I5 => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(1), + O => ip2axi_rddata_int_inferred_i_55_n_0 + ); +\ip2axi_rddata_int_inferred_i_55__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_84_n_0, + I1 => dly_irq_reg_2, + I2 => ip2axi_rddata_int_inferred_i_87_n_0, + I3 => \reg_module_hsize_reg[15]_0\(13), + I4 => \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14]\(5), + I5 => ip2axi_rddata_int_inferred_i_86_n_0, + O => \ip2axi_rddata_int_inferred_i_55__0_n_0\ + ); +ip2axi_rddata_int_inferred_i_56: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[15]_1\, + I1 => \M_GEN_DMACR_REGISTER.dmacr_i_reg[14]\(3), + I2 => ip2axi_rddata_int_inferred_i_78_n_0, + I3 => dly_irq_reg_1, + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(11), + I5 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\, + O => ip2axi_rddata_int_inferred_i_56_n_0 + ); +\ip2axi_rddata_int_inferred_i_56__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_88_n_0, + I1 => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(13), + I2 => ip2axi_rddata_int_inferred_i_85_n_0, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(13), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(13), + I5 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + O => \ip2axi_rddata_int_inferred_i_56__0_n_0\ + ); +ip2axi_rddata_int_inferred_i_57: unisim.vcomponents.LUT6 + generic map( + INIT => X"A8288808A0208000" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[12]_0\, + I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), + I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(0), + I4 => \reg_module_hsize_reg[15]\(0), + I5 => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(0), + O => ip2axi_rddata_int_inferred_i_57_n_0 + ); +\ip2axi_rddata_int_inferred_i_57__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_84_n_0, + I1 => ioc_irq_reg_2, + I2 => ip2axi_rddata_int_inferred_i_89_n_0, + I3 => \reg_module_vsize_reg[12]\(12), + I4 => \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14]\(4), + I5 => ip2axi_rddata_int_inferred_i_86_n_0, + O => \ip2axi_rddata_int_inferred_i_57__0_n_0\ + ); +ip2axi_rddata_int_inferred_i_58: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[15]_1\, + I1 => \M_GEN_DMACR_REGISTER.dmacr_i_reg[14]\(2), + I2 => ip2axi_rddata_int_inferred_i_78_n_0, + I3 => ioc_irq_reg_1, + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(10), + I5 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\, + O => ip2axi_rddata_int_inferred_i_58_n_0 + ); +\ip2axi_rddata_int_inferred_i_58__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_87_n_0, + I1 => \reg_module_hsize_reg[15]_0\(12), + I2 => ip2axi_rddata_int_inferred_i_88_n_0, + I3 => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(12), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(12), + I5 => ip2axi_rddata_int_inferred_i_85_n_0, + O => \ip2axi_rddata_int_inferred_i_58__0_n_0\ + ); +ip2axi_rddata_int_inferred_i_59: unisim.vcomponents.LUT4 + generic map( + INIT => X"0008" + ) + port map ( + I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), + I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), + I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), + I3 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), + O => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[12]_0\ + ); +\ip2axi_rddata_int_inferred_i_59__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_84_n_0, + I1 => \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg_0\, + I2 => ip2axi_rddata_int_inferred_i_89_n_0, + I3 => \reg_module_vsize_reg[12]\(11), + I4 => \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14]\(3), + I5 => ip2axi_rddata_int_inferred_i_86_n_0, + O => \ip2axi_rddata_int_inferred_i_59__0_n_0\ + ); +\ip2axi_rddata_int_inferred_i_5__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_39__0_n_0\, + I1 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(27), + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(27), + I4 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(27) + ); +ip2axi_rddata_int_inferred_i_6: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_40_n_0, + I1 => ip2axi_rddata_int_inferred_i_34_n_0, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(13), + I3 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\, + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(23), + O => in0(23) + ); +\ip2axi_rddata_int_inferred_i_60__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_87_n_0, + I1 => \reg_module_hsize_reg[15]_0\(11), + I2 => ip2axi_rddata_int_inferred_i_88_n_0, + I3 => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(11), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(11), + I5 => ip2axi_rddata_int_inferred_i_85_n_0, + O => \ip2axi_rddata_int_inferred_i_60__0_n_0\ + ); +\ip2axi_rddata_int_inferred_i_61__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_86_n_0, + I1 => \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14]\(2), + I2 => ip2axi_rddata_int_inferred_i_89_n_0, + I3 => \reg_module_vsize_reg[12]\(10), + I4 => \reg_module_hsize_reg[15]_0\(10), + I5 => ip2axi_rddata_int_inferred_i_87_n_0, + O => \ip2axi_rddata_int_inferred_i_61__0_n_0\ + ); +ip2axi_rddata_int_inferred_i_62: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000400000" + ) + port map ( + I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), + I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), + I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), + I3 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), + I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), + I5 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), + O => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\ + ); +\ip2axi_rddata_int_inferred_i_62__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_88_n_0, + I1 => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(10), + I2 => ip2axi_rddata_int_inferred_i_85_n_0, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(10), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(10), + I5 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + O => \ip2axi_rddata_int_inferred_i_62__0_n_0\ + ); +\ip2axi_rddata_int_inferred_i_63__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_86_n_0, + I1 => \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14]\(1), + I2 => ip2axi_rddata_int_inferred_i_89_n_0, + I3 => \reg_module_vsize_reg[12]\(9), + I4 => \reg_module_hsize_reg[15]_0\(9), + I5 => ip2axi_rddata_int_inferred_i_87_n_0, + O => \ip2axi_rddata_int_inferred_i_63__0_n_0\ + ); +\ip2axi_rddata_int_inferred_i_64__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_88_n_0, + I1 => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(9), + I2 => ip2axi_rddata_int_inferred_i_85_n_0, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(9), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(9), + I5 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + O => \ip2axi_rddata_int_inferred_i_64__0_n_0\ + ); +\ip2axi_rddata_int_inferred_i_65__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_84_n_0, + I1 => lsize_err_reg_0, + I2 => ip2axi_rddata_int_inferred_i_89_n_0, + I3 => \reg_module_vsize_reg[12]\(8), + I4 => \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14]\(0), + I5 => ip2axi_rddata_int_inferred_i_86_n_0, + O => \ip2axi_rddata_int_inferred_i_65__0_n_0\ + ); +\ip2axi_rddata_int_inferred_i_66__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_87_n_0, + I1 => \reg_module_hsize_reg[15]_0\(8), + I2 => ip2axi_rddata_int_inferred_i_88_n_0, + I3 => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(8), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(8), + I5 => ip2axi_rddata_int_inferred_i_85_n_0, + O => \ip2axi_rddata_int_inferred_i_66__0_n_0\ + ); +ip2axi_rddata_int_inferred_i_67: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[15]_1\, + I1 => \M_GEN_DMACR_REGISTER.dmacr_i_reg[14]\(1), + I2 => ip2axi_rddata_int_inferred_i_78_n_0, + I3 => dma_decerr_reg, + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(4), + I5 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\, + O => ip2axi_rddata_int_inferred_i_67_n_0 + ); +\ip2axi_rddata_int_inferred_i_67__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_84_n_0, + I1 => \GEN_FOR_FLUSH.fsize_err_reg_0\, + I2 => ip2axi_rddata_int_inferred_i_89_n_0, + I3 => \reg_module_vsize_reg[12]\(7), + I4 => \reg_module_hsize_reg[15]_0\(7), + I5 => ip2axi_rddata_int_inferred_i_87_n_0, + O => \ip2axi_rddata_int_inferred_i_67__0_n_0\ + ); +\ip2axi_rddata_int_inferred_i_68__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_88_n_0, + I1 => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(7), + I2 => ip2axi_rddata_int_inferred_i_85_n_0, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(7), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(7), + I5 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + O => \ip2axi_rddata_int_inferred_i_68__0_n_0\ + ); +ip2axi_rddata_int_inferred_i_69: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[15]_1\, + I1 => \M_GEN_DMACR_REGISTER.dmacr_i_reg[14]\(0), + I2 => ip2axi_rddata_int_inferred_i_78_n_0, + I3 => dma_slverr_reg, + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(3), + I5 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\, + O => ip2axi_rddata_int_inferred_i_69_n_0 + ); +\ip2axi_rddata_int_inferred_i_69__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_84_n_0, + I1 => dma_decerr_reg_0, + I2 => ip2axi_rddata_int_inferred_i_89_n_0, + I3 => \reg_module_vsize_reg[12]\(6), + I4 => s2mm_dmacr(5), + I5 => ip2axi_rddata_int_inferred_i_86_n_0, + O => \ip2axi_rddata_int_inferred_i_69__0_n_0\ + ); +\ip2axi_rddata_int_inferred_i_6__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_40__0_n_0\, + I1 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(26), + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(26), + I4 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(26) + ); +ip2axi_rddata_int_inferred_i_7: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_41_n_0, + I1 => ip2axi_rddata_int_inferred_i_34_n_0, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(12), + I3 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\, + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(22), + O => in0(22) + ); +\ip2axi_rddata_int_inferred_i_70__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_87_n_0, + I1 => \reg_module_hsize_reg[15]_0\(6), + I2 => ip2axi_rddata_int_inferred_i_88_n_0, + I3 => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(6), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(6), + I5 => ip2axi_rddata_int_inferred_i_85_n_0, + O => \ip2axi_rddata_int_inferred_i_70__0_n_0\ + ); +ip2axi_rddata_int_inferred_i_71: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[15]_1\, + I1 => p_71_out(1), + I2 => ip2axi_rddata_int_inferred_i_78_n_0, + I3 => dma_interr_reg_1, + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(2), + I5 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\, + O => ip2axi_rddata_int_inferred_i_71_n_0 + ); +\ip2axi_rddata_int_inferred_i_71__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_84_n_0, + I1 => dma_slverr_reg_0, + I2 => ip2axi_rddata_int_inferred_i_89_n_0, + I3 => \reg_module_vsize_reg[12]\(5), + I4 => s2mm_dmacr(4), + I5 => ip2axi_rddata_int_inferred_i_86_n_0, + O => \ip2axi_rddata_int_inferred_i_71__0_n_0\ + ); +\ip2axi_rddata_int_inferred_i_72__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_87_n_0, + I1 => \reg_module_hsize_reg[15]_0\(5), + I2 => ip2axi_rddata_int_inferred_i_88_n_0, + I3 => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(5), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(5), + I5 => ip2axi_rddata_int_inferred_i_85_n_0, + O => \ip2axi_rddata_int_inferred_i_72__0_n_0\ + ); +\ip2axi_rddata_int_inferred_i_73__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_84_n_0, + I1 => dma_interr_reg_2, + I2 => ip2axi_rddata_int_inferred_i_89_n_0, + I3 => \reg_module_vsize_reg[12]\(4), + I4 => s2mm_dmacr(3), + I5 => ip2axi_rddata_int_inferred_i_86_n_0, + O => \ip2axi_rddata_int_inferred_i_73__0_n_0\ + ); +\ip2axi_rddata_int_inferred_i_74__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_87_n_0, + I1 => \reg_module_hsize_reg[15]_0\(4), + I2 => ip2axi_rddata_int_inferred_i_88_n_0, + I3 => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(4), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(4), + I5 => ip2axi_rddata_int_inferred_i_85_n_0, + O => \ip2axi_rddata_int_inferred_i_74__0_n_0\ + ); +\ip2axi_rddata_int_inferred_i_75__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_86_n_0, + I1 => s2mm_dmacr(2), + I2 => ip2axi_rddata_int_inferred_i_90_n_0, + I3 => \DMA_IRQ_MASK_GEN.dma_irq_mask_i_reg[3]\(3), + I4 => \reg_module_vsize_reg[12]\(3), + I5 => ip2axi_rddata_int_inferred_i_89_n_0, + O => \ip2axi_rddata_int_inferred_i_75__0_n_0\ + ); +ip2axi_rddata_int_inferred_i_76: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[15]_1\, + I1 => p_71_out(0), + I2 => ip2axi_rddata_int_inferred_i_78_n_0, + I3 => p_70_out, + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(0), + I5 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[11]_0\, + O => ip2axi_rddata_int_inferred_i_76_n_0 + ); +\ip2axi_rddata_int_inferred_i_76__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_87_n_0, + I1 => \reg_module_hsize_reg[15]_0\(3), + I2 => ip2axi_rddata_int_inferred_i_88_n_0, + I3 => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(3), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(3), + I5 => ip2axi_rddata_int_inferred_i_85_n_0, + O => \ip2axi_rddata_int_inferred_i_76__0_n_0\ + ); +\ip2axi_rddata_int_inferred_i_77__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_86_n_0, + I1 => s2mm_soft_reset, + I2 => ip2axi_rddata_int_inferred_i_90_n_0, + I3 => \DMA_IRQ_MASK_GEN.dma_irq_mask_i_reg[3]\(2), + I4 => \reg_module_vsize_reg[12]\(2), + I5 => ip2axi_rddata_int_inferred_i_89_n_0, + O => \ip2axi_rddata_int_inferred_i_77__0_n_0\ + ); +ip2axi_rddata_int_inferred_i_78: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000010000" + ) + port map ( + I0 => axi2ip_rdaddr_captured_mm2s_cdc_tig(7), + I1 => axi2ip_rdaddr_captured_mm2s_cdc_tig(5), + I2 => axi2ip_rdaddr_captured_mm2s_cdc_tig(6), + I3 => axi2ip_rdaddr_captured_mm2s_cdc_tig(4), + I4 => axi2ip_rdaddr_captured_mm2s_cdc_tig(2), + I5 => axi2ip_rdaddr_captured_mm2s_cdc_tig(3), + O => ip2axi_rddata_int_inferred_i_78_n_0 + ); +\ip2axi_rddata_int_inferred_i_78__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_87_n_0, + I1 => \reg_module_hsize_reg[15]_0\(2), + I2 => ip2axi_rddata_int_inferred_i_88_n_0, + I3 => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(2), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(2), + I5 => ip2axi_rddata_int_inferred_i_85_n_0, + O => \ip2axi_rddata_int_inferred_i_78__0_n_0\ + ); +\ip2axi_rddata_int_inferred_i_79__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_86_n_0, + I1 => s2mm_dmacr(1), + I2 => ip2axi_rddata_int_inferred_i_90_n_0, + I3 => \DMA_IRQ_MASK_GEN.dma_irq_mask_i_reg[3]\(1), + I4 => \reg_module_vsize_reg[12]\(1), + I5 => ip2axi_rddata_int_inferred_i_89_n_0, + O => \ip2axi_rddata_int_inferred_i_79__0_n_0\ + ); +\ip2axi_rddata_int_inferred_i_7__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_41__0_n_0\, + I1 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(25), + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(25), + I4 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(25) + ); +ip2axi_rddata_int_inferred_i_8: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_42_n_0, + I1 => ip2axi_rddata_int_inferred_i_34_n_0, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(11), + I3 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\, + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(21), + O => in0(21) + ); +\ip2axi_rddata_int_inferred_i_80__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_87_n_0, + I1 => \reg_module_hsize_reg[15]_0\(1), + I2 => ip2axi_rddata_int_inferred_i_88_n_0, + I3 => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(1), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(1), + I5 => ip2axi_rddata_int_inferred_i_85_n_0, + O => \ip2axi_rddata_int_inferred_i_80__0_n_0\ + ); +ip2axi_rddata_int_inferred_i_81: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_84_n_0, + I1 => s2mm_dmasr(0), + I2 => ip2axi_rddata_int_inferred_i_90_n_0, + I3 => \DMA_IRQ_MASK_GEN.dma_irq_mask_i_reg[3]\(0), + I4 => s2mm_dmacr(0), + I5 => ip2axi_rddata_int_inferred_i_86_n_0, + O => ip2axi_rddata_int_inferred_i_81_n_0 + ); +ip2axi_rddata_int_inferred_i_82: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_89_n_0, + I1 => \reg_module_vsize_reg[12]\(0), + I2 => ip2axi_rddata_int_inferred_i_87_n_0, + I3 => \reg_module_hsize_reg[15]_0\(0), + I4 => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(0), + I5 => ip2axi_rddata_int_inferred_i_88_n_0, + O => ip2axi_rddata_int_inferred_i_82_n_0 + ); +ip2axi_rddata_int_inferred_i_83: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_85_n_0, + I1 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(0), + I2 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(0), + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(0), + I5 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + O => ip2axi_rddata_int_inferred_i_83_n_0 + ); +ip2axi_rddata_int_inferred_i_84: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000400000" + ) + port map ( + I0 => axi2ip_rdaddr_captured_s2mm_cdc_tig(7), + I1 => axi2ip_rdaddr_captured_s2mm_cdc_tig(2), + I2 => axi2ip_rdaddr_captured_s2mm_cdc_tig(4), + I3 => axi2ip_rdaddr_captured_s2mm_cdc_tig(6), + I4 => axi2ip_rdaddr_captured_s2mm_cdc_tig(5), + I5 => axi2ip_rdaddr_captured_s2mm_cdc_tig(3), + O => ip2axi_rddata_int_inferred_i_84_n_0 + ); +ip2axi_rddata_int_inferred_i_85: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000040000000" + ) + port map ( + I0 => axi2ip_rdaddr_captured_s2mm_cdc_tig(4), + I1 => axi2ip_rdaddr_captured_s2mm_cdc_tig(2), + I2 => axi2ip_rdaddr_captured_s2mm_cdc_tig(7), + I3 => axi2ip_rdaddr_captured_s2mm_cdc_tig(3), + I4 => axi2ip_rdaddr_captured_s2mm_cdc_tig(5), + I5 => axi2ip_rdaddr_captured_s2mm_cdc_tig(6), + O => ip2axi_rddata_int_inferred_i_85_n_0 + ); +ip2axi_rddata_int_inferred_i_86: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000100000" + ) + port map ( + I0 => axi2ip_rdaddr_captured_s2mm_cdc_tig(2), + I1 => axi2ip_rdaddr_captured_s2mm_cdc_tig(3), + I2 => axi2ip_rdaddr_captured_s2mm_cdc_tig(5), + I3 => axi2ip_rdaddr_captured_s2mm_cdc_tig(6), + I4 => axi2ip_rdaddr_captured_s2mm_cdc_tig(4), + I5 => axi2ip_rdaddr_captured_s2mm_cdc_tig(7), + O => ip2axi_rddata_int_inferred_i_86_n_0 + ); +ip2axi_rddata_int_inferred_i_87: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000400000" + ) + port map ( + I0 => axi2ip_rdaddr_captured_s2mm_cdc_tig(4), + I1 => axi2ip_rdaddr_captured_s2mm_cdc_tig(2), + I2 => axi2ip_rdaddr_captured_s2mm_cdc_tig(7), + I3 => axi2ip_rdaddr_captured_s2mm_cdc_tig(3), + I4 => axi2ip_rdaddr_captured_s2mm_cdc_tig(5), + I5 => axi2ip_rdaddr_captured_s2mm_cdc_tig(6), + O => ip2axi_rddata_int_inferred_i_87_n_0 + ); +ip2axi_rddata_int_inferred_i_88: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000002000000" + ) + port map ( + I0 => axi2ip_rdaddr_captured_s2mm_cdc_tig(7), + I1 => axi2ip_rdaddr_captured_s2mm_cdc_tig(2), + I2 => axi2ip_rdaddr_captured_s2mm_cdc_tig(4), + I3 => axi2ip_rdaddr_captured_s2mm_cdc_tig(3), + I4 => axi2ip_rdaddr_captured_s2mm_cdc_tig(5), + I5 => axi2ip_rdaddr_captured_s2mm_cdc_tig(6), + O => ip2axi_rddata_int_inferred_i_88_n_0 + ); +ip2axi_rddata_int_inferred_i_89: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000020000" + ) + port map ( + I0 => axi2ip_rdaddr_captured_s2mm_cdc_tig(7), + I1 => axi2ip_rdaddr_captured_s2mm_cdc_tig(2), + I2 => axi2ip_rdaddr_captured_s2mm_cdc_tig(4), + I3 => axi2ip_rdaddr_captured_s2mm_cdc_tig(3), + I4 => axi2ip_rdaddr_captured_s2mm_cdc_tig(5), + I5 => axi2ip_rdaddr_captured_s2mm_cdc_tig(6), + O => ip2axi_rddata_int_inferred_i_89_n_0 + ); +\ip2axi_rddata_int_inferred_i_8__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_42__0_n_0\, + I1 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(24), + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(24), + I4 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(24) + ); +ip2axi_rddata_int_inferred_i_9: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => ip2axi_rddata_int_inferred_i_43_n_0, + I1 => ip2axi_rddata_int_inferred_i_34_n_0, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(10), + I3 => \^gen_lite_is_async.gen_async_lite_access.mm2s_ip2axi_rddata_d1_reg[31]_0\, + I4 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(20), + O => in0(20) + ); +ip2axi_rddata_int_inferred_i_90: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000008000000" + ) + port map ( + I0 => axi2ip_rdaddr_captured_s2mm_cdc_tig(4), + I1 => axi2ip_rdaddr_captured_s2mm_cdc_tig(2), + I2 => axi2ip_rdaddr_captured_s2mm_cdc_tig(7), + I3 => axi2ip_rdaddr_captured_s2mm_cdc_tig(3), + I4 => axi2ip_rdaddr_captured_s2mm_cdc_tig(5), + I5 => axi2ip_rdaddr_captured_s2mm_cdc_tig(6), + O => ip2axi_rddata_int_inferred_i_90_n_0 + ); +\ip2axi_rddata_int_inferred_i_9__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \ip2axi_rddata_int_inferred_i_43__0_n_0\, + I1 => \ip2axi_rddata_int_inferred_i_34__0_n_0\, + I2 => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(23), + I3 => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(23), + I4 => \ip2axi_rddata_int_inferred_i_35__0_n_0\, + O => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(23) + ); +lite_wr_addr_phase_finished_data_phase_started_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"00E0" + ) + port map ( + I0 => lite_wr_addr_phase_finished_data_phase_started, + I1 => \^s_axi_lite_awready\, + I2 => s_axi_lite_resetn, + I3 => \^s_axi_lite_wready\, + O => lite_wr_addr_phase_finished_data_phase_started_i_1_n_0 + ); +lite_wr_addr_phase_finished_data_phase_started_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => lite_wr_addr_phase_finished_data_phase_started_i_1_n_0, + Q => lite_wr_addr_phase_finished_data_phase_started, + R => '0' + ); +read_has_started_i_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000AE00AE00AE00" + ) + port map ( + I0 => read_has_started_i, + I1 => arvalid, + I2 => sig_arvalid_arrived_d1, + I3 => s_axi_lite_resetn, + I4 => s_axi_lite_rready, + I5 => \^s_axi_lite_rvalid\, + O => read_has_started_i_i_1_n_0 + ); +read_has_started_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => read_has_started_i_i_1_n_0, + Q => read_has_started_i, + R => '0' + ); +sig_arvalid_arrived_d1_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => arvalid, + I1 => s_axi_lite_resetn, + I2 => read_has_started_i, + O => sig_arvalid_arrived_d1_i_1_n_0 + ); +sig_arvalid_arrived_d1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => sig_arvalid_arrived_d1_i_1_n_0, + Q => sig_arvalid_arrived_d1, + R => '0' + ); +sig_arvalid_detected: unisim.vcomponents.LUT3 + generic map( + INIT => X"02" + ) + port map ( + I0 => arvalid, + I1 => sig_arvalid_arrived_d1, + I2 => read_has_started_i, + O => \sig_arvalid_detected__0\ + ); +sig_awvalid_arrived_d1_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => awvalid, + I1 => s_axi_lite_resetn, + I2 => write_has_started, + O => sig_awvalid_arrived_d1_i_1_n_0 + ); +sig_awvalid_arrived_d1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => sig_awvalid_arrived_d1_i_1_n_0, + Q => sig_awvalid_arrived_d1, + R => '0' + ); +sig_awvalid_detected: unisim.vcomponents.LUT3 + generic map( + INIT => X"02" + ) + port map ( + I0 => awvalid, + I1 => sig_awvalid_arrived_d1, + I2 => write_has_started, + O => \sig_awvalid_detected__0\ + ); +\wdata_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(0), + Q => wdata(0), + R => SR(0) + ); +\wdata_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(10), + Q => wdata(10), + R => SR(0) + ); +\wdata_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(11), + Q => wdata(11), + R => SR(0) + ); +\wdata_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(12), + Q => wdata(12), + R => SR(0) + ); +\wdata_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(13), + Q => wdata(13), + R => SR(0) + ); +\wdata_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(14), + Q => wdata(14), + R => SR(0) + ); +\wdata_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(15), + Q => wdata(15), + R => SR(0) + ); +\wdata_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(16), + Q => wdata(16), + R => SR(0) + ); +\wdata_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(17), + Q => wdata(17), + R => SR(0) + ); +\wdata_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(18), + Q => wdata(18), + R => SR(0) + ); +\wdata_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(19), + Q => wdata(19), + R => SR(0) + ); +\wdata_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(1), + Q => wdata(1), + R => SR(0) + ); +\wdata_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(20), + Q => wdata(20), + R => SR(0) + ); +\wdata_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(21), + Q => wdata(21), + R => SR(0) + ); +\wdata_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(22), + Q => wdata(22), + R => SR(0) + ); +\wdata_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(23), + Q => wdata(23), + R => SR(0) + ); +\wdata_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(24), + Q => wdata(24), + R => SR(0) + ); +\wdata_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(25), + Q => wdata(25), + R => SR(0) + ); +\wdata_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(26), + Q => wdata(26), + R => SR(0) + ); +\wdata_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(27), + Q => wdata(27), + R => SR(0) + ); +\wdata_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(28), + Q => wdata(28), + R => SR(0) + ); +\wdata_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(29), + Q => wdata(29), + R => SR(0) + ); +\wdata_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(2), + Q => wdata(2), + R => SR(0) + ); +\wdata_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(30), + Q => wdata(30), + R => SR(0) + ); +\wdata_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(31), + Q => wdata(31), + R => SR(0) + ); +\wdata_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(3), + Q => wdata(3), + R => SR(0) + ); +\wdata_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(4), + Q => wdata(4), + R => SR(0) + ); +\wdata_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(5), + Q => wdata(5), + R => SR(0) + ); +\wdata_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(6), + Q => wdata(6), + R => SR(0) + ); +\wdata_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(7), + Q => wdata(7), + R => SR(0) + ); +\wdata_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(8), + Q => wdata(8), + R => SR(0) + ); +\wdata_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wdata(9), + Q => wdata(9), + R => SR(0) + ); +write_has_started_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000AE00AE00AE00" + ) + port map ( + I0 => write_has_started, + I1 => awvalid, + I2 => sig_awvalid_arrived_d1, + I3 => s_axi_lite_resetn, + I4 => s_axi_lite_bready, + I5 => \^s_axi_lite_bvalid\, + O => write_has_started_i_1_n_0 + ); +write_has_started_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => write_has_started_i_1_n_0, + Q => write_has_started, + R => '0' + ); +wvalid_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => s_axi_lite_wvalid, + Q => wvalid, + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_module is + port ( + p_71_out : out STD_LOGIC_VECTOR ( 18 downto 0 ); + p_77_out : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + reset_counts : out STD_LOGIC; + p_70_out : out STD_LOGIC; + err_d1_reg : out STD_LOGIC; + err_d1_reg_0 : out STD_LOGIC; + err_d1_reg_1 : out STD_LOGIC; + ioc_irq_reg : out STD_LOGIC; + dly_irq_reg : out STD_LOGIC; + p_78_out : out STD_LOGIC; + p_67_out : out STD_LOGIC; + s_soft_reset_i0 : out STD_LOGIC; + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg\ : out STD_LOGIC; + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]\ : out STD_LOGIC; + ch1_delay_zero : out STD_LOGIC; + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0]\ : out STD_LOGIC; + p_13_out : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 4 downto 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + err_irq_reg : out STD_LOGIC; + \dmacr_i_reg[0]\ : out STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0]\ : out STD_LOGIC; + \hsize_vid_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \vsize_vid_reg[12]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); + \stride_vid_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3]\ : out STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4]\ : out STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5]\ : out STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6]\ : out STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7]\ : out STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8]\ : out STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9]\ : out STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10]\ : out STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]\ : out STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]\ : out STD_LOGIC; + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : out STD_LOGIC; + \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axis_cmd_tvalid_reg : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg\ : out STD_LOGIC; + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + dmacr_i : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + mm2s_axi2ip_wrce : in STD_LOGIC_VECTOR ( 8 downto 0 ); + D : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \dmacr_i_reg[2]\ : in STD_LOGIC; + in0 : in STD_LOGIC_VECTOR ( 28 downto 0 ); + reset_counts_reg : in STD_LOGIC; + halted_clr_reg : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4]\ : in STD_LOGIC; + slverr_i_reg : in STD_LOGIC; + decerr_i_reg : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12]\ : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13]\ : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[2]\ : in STD_LOGIC; + mm2s_halt_cmplt : in STD_LOGIC; + halt_reset : in STD_LOGIC; + prmry_in : in STD_LOGIC; + p_50_out : in STD_LOGIC; + ch1_delay_cnt_en : in STD_LOGIC; + p_17_out : in STD_LOGIC; + ch1_dly_irq_set : in STD_LOGIC; + mask_fsync_out_i : in STD_LOGIC; + p_47_out : in STD_LOGIC; + prmry_resetn_i_reg : in STD_LOGIC; + p_24_out : in STD_LOGIC; + p_45_out : in STD_LOGIC; + mm2s_ioc_irq_set : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]\ : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_0\ : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[4]\ : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_1\ : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]_0\ : in STD_LOGIC; + dma_err : in STD_LOGIC; + mm2s_halt : in STD_LOGIC; + initial_frame : in STD_LOGIC; + stop : in STD_LOGIC; + prmtr_update_complete : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_module : entity is "axi_vdma_reg_module"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_module; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_module is + signal \GEN_REG_DIRECT_MODE.REGDIRECT_I_n_79\ : STD_LOGIC; + signal \GEN_REG_DIRECT_MODE.REGDIRECT_I_n_80\ : STD_LOGIC; + signal \GEN_REG_DIRECT_MODE.REGDIRECT_I_n_81\ : STD_LOGIC; + signal I_DMA_REGISTER_n_20 : STD_LOGIC; + signal \^p_70_out\ : STD_LOGIC; + signal \^p_71_out\ : STD_LOGIC_VECTOR ( 18 downto 0 ); + signal \^p_77_out\ : STD_LOGIC; +begin + p_70_out <= \^p_70_out\; + p_71_out(18 downto 0) <= \^p_71_out\(18 downto 0); + p_77_out <= \^p_77_out\; +\GEN_REG_DIRECT_MODE.REGDIRECT_I\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_regdirect + port map ( + D(31 downto 0) => D(31 downto 0), + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1 downto 0) => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1 downto 0), + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]_0\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]_0\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[4]\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[4]\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_0\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_0\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_1\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_1\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[2]\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[2]\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0]\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0]\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10]\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10]\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3]\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3]\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4]\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4]\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5]\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5]\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6]\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6]\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7]\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7]\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8]\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8]\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9]\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9]\, + \GEN_NOSYNCEN_BIT.dmacr_i_reg[15]\ => I_DMA_REGISTER_n_20, + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg\ => \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg\, + \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(31 downto 0) => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(31 downto 0), + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(31 downto 0) => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(31 downto 0), + \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(31 downto 0) => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(31 downto 0), + SR(0) => SR(0), + \dmacr_i_reg[0]\ => \^p_71_out\(0), + \dmacr_i_reg[2]\ => \^p_77_out\, + halted_reg => \^p_70_out\, + \hsize_vid_reg[15]\(15 downto 0) => \hsize_vid_reg[15]\(15 downto 0), + in0(2) => \GEN_REG_DIRECT_MODE.REGDIRECT_I_n_79\, + in0(1) => \GEN_REG_DIRECT_MODE.REGDIRECT_I_n_80\, + in0(0) => \GEN_REG_DIRECT_MODE.REGDIRECT_I_n_81\, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + mm2s_axi2ip_wrce(5 downto 0) => mm2s_axi2ip_wrce(8 downto 3), + p_24_out => p_24_out, + p_67_out => p_67_out, + p_71_out(0) => \^p_71_out\(1), + prmry_resetn_i_reg => prmry_resetn_i_reg, + prmtr_update_complete => prmtr_update_complete, + stop => stop, + \stride_vid_reg[15]\(15 downto 0) => \stride_vid_reg[15]\(15 downto 0), + \vsize_vid_reg[12]\(12 downto 0) => \vsize_vid_reg[12]\(12 downto 0) + ); +I_DMA_REGISTER: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_register + port map ( + D(23 downto 4) => D(31 downto 12), + D(3 downto 1) => D(6 downto 4), + D(0) => D(1), + E(0) => E(0), + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\, + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]\ => reset_counts, + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]_0\ => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]\, + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]_1\(0) => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]_0\(0), + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg\ => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg\, + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0]\ => \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0]\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12]\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12]\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13]\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13]\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18]\(0) => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18]\(0), + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4]\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4]\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]\ => I_DMA_REGISTER_n_20, + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\(4 downto 0) => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\(4 downto 0), + \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]\(0) => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]\(0), + \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0\(4 downto 0) => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0\(4 downto 0), + Q(4 downto 0) => Q(4 downto 0), + SR(0) => SR(0), + ch1_delay_cnt_en => ch1_delay_cnt_en, + ch1_delay_zero => ch1_delay_zero, + ch1_dly_irq_set => ch1_dly_irq_set, + decerr_i_reg => decerr_i_reg, + dly_irq_reg_0 => dly_irq_reg, + dma_err => dma_err, + dmacr_i(0) => dmacr_i(0), + \dmacr_i_reg[0]_0\ => \dmacr_i_reg[0]\, + \dmacr_i_reg[2]_0\ => \dmacr_i_reg[2]\, + err_d1_reg_0 => err_d1_reg, + err_d1_reg_1 => err_d1_reg_0, + err_d1_reg_2 => err_d1_reg_1, + err_irq_reg_0 => err_irq_reg, + halt_reset => halt_reset, + halted_clr_reg => halted_clr_reg, + initial_frame => initial_frame, + ioc_irq_reg_0 => ioc_irq_reg, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + mask_fsync_out_i => mask_fsync_out_i, + mm2s_axi2ip_wrce(1 downto 0) => mm2s_axi2ip_wrce(1 downto 0), + mm2s_halt => mm2s_halt, + mm2s_halt_cmplt => mm2s_halt_cmplt, + mm2s_ioc_irq_set => mm2s_ioc_irq_set, + p_13_out => p_13_out, + p_17_out => p_17_out, + p_24_out => p_24_out, + p_45_out => p_45_out, + p_47_out => p_47_out, + p_50_out => p_50_out, + p_71_out(18 downto 0) => \^p_71_out\(18 downto 0), + p_78_out => p_78_out, + prmry_in => prmry_in, + prmry_resetn_i_reg => prmry_resetn_i_reg, + reset_counts_reg_0 => reset_counts_reg, + s_axis_cmd_tvalid_reg => \^p_70_out\, + s_axis_cmd_tvalid_reg_0(0) => s_axis_cmd_tvalid_reg(0), + s_soft_reset_i0 => s_soft_reset_i0, + slverr_i_reg => slverr_i_reg, + soft_reset_d1_reg => \^p_77_out\ + ); +LITE_READ_MUX_I: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_mux + port map ( + in0(31 downto 16) => in0(28 downto 13), + in0(15) => \GEN_REG_DIRECT_MODE.REGDIRECT_I_n_79\, + in0(14 downto 3) => in0(12 downto 1), + in0(2) => \GEN_REG_DIRECT_MODE.REGDIRECT_I_n_80\, + in0(1) => \GEN_REG_DIRECT_MODE.REGDIRECT_I_n_81\, + in0(0) => in0(0), + \out\(31 downto 0) => \out\(31 downto 0) + ); +\ptr_ref_i_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(2), + D => D(0), + Q => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(0), + R => SR(0) + ); +\ptr_ref_i_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(2), + D => D(1), + Q => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(1), + R => SR(0) + ); +\ptr_ref_i_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(2), + D => D(2), + Q => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(2), + R => SR(0) + ); +\ptr_ref_i_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(2), + D => D(3), + Q => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(3), + R => SR(0) + ); +\ptr_ref_i_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => mm2s_axi2ip_wrce(2), + D => D(4), + Q => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(4), + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_module__parameterized0\ is + port ( + s2mm_dmacr : out STD_LOGIC_VECTOR ( 22 downto 0 ); + s2mm_soft_reset : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + reset_counts : out STD_LOGIC; + irqdelay_wren_i : out STD_LOGIC; + s2mm_dmasr : out STD_LOGIC_VECTOR ( 0 to 0 ); + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]\ : out STD_LOGIC; + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_0\ : out STD_LOGIC; + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_1\ : out STD_LOGIC; + \GEN_FOR_FLUSH.fsize_err_reg\ : out STD_LOGIC; + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_2\ : out STD_LOGIC; + err_d1_reg : out STD_LOGIC; + ioc_irq_reg : out STD_LOGIC; + dly_irq_reg : out STD_LOGIC; + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_3\ : out STD_LOGIC; + err_d1_reg_0 : out STD_LOGIC; + s2mm_ip2axi_introut : out STD_LOGIC; + s_soft_reset_i0 : out STD_LOGIC; + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6]\ : out STD_LOGIC; + ch2_delay_zero : out STD_LOGIC; + p_6_out : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 6 downto 0 ); + \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg\ : out STD_LOGIC; + \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg\ : out STD_LOGIC; + err_d1_reg_1 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + err_irq_reg : out STD_LOGIC; + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axis_cmd_tvalid_reg : out STD_LOGIC_VECTOR ( 0 to 0 ); + prmry_in_xored : out STD_LOGIC; + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg\ : out STD_LOGIC; + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + \vsize_vid_reg[12]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); + \hsize_vid_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + \stride_vid_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + m_axi_s2mm_aclk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + s2mm_axi2ip_wrce : in STD_LOGIC_VECTOR ( 9 downto 0 ); + D : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \dmacr_i_reg[2]\ : in STD_LOGIC; + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + reset_counts_reg : in STD_LOGIC; + p_15_out : in STD_LOGIC; + p_14_out : in STD_LOGIC; + halted_clr_reg : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4]\ : in STD_LOGIC; + slverr_i_reg : in STD_LOGIC; + decerr_i_reg : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[7]\ : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[8]\ : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[11]\ : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[12]\ : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[13]\ : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[15]\ : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4]_0\ : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[2]\ : in STD_LOGIC; + s2mm_halt_cmplt : in STD_LOGIC; + halt_reset : in STD_LOGIC; + prmry_in : in STD_LOGIC; + prmry_resetn_i_reg : in STD_LOGIC; + ch2_dly_irq_set : in STD_LOGIC; + s2mm_tstvect_fsync : in STD_LOGIC; + s2mm_valid_frame_sync : in STD_LOGIC; + s2mm_ioc_irq_set : in STD_LOGIC; + s2mm_valid_video_prmtrs : in STD_LOGIC; + mask_fsync_out_i : in STD_LOGIC; + s2mm_stop : in STD_LOGIC; + num_fstore_minus1 : in STD_LOGIC_VECTOR ( 0 to 0 ); + initial_frame : in STD_LOGIC; + p_in_d1_cdc_from : in STD_LOGIC; + ch2_delay_cnt_en : in STD_LOGIC; + s2mm_cdc2dmac_fsync : in STD_LOGIC; + s2mm_packet_sof : in STD_LOGIC; + prmtr_update_complete : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_module__parameterized0\ : entity is "axi_vdma_reg_module"; +end \Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_module__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_module__parameterized0\ is + signal \^s2mm_dmasr\ : STD_LOGIC_VECTOR ( 0 to 0 ); +begin + s2mm_dmasr(0) <= \^s2mm_dmasr\(0); +\GEN_REG_DIRECT_MODE.REGDIRECT_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_axi_vdma_regdirect__parameterized0\ + port map ( + D(31 downto 0) => D(31 downto 0), + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[2]\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[2]\, + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg\ => \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg\, + \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(31 downto 0) => \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(31 downto 0), + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(31 downto 0) => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(31 downto 0), + \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(31 downto 0) => \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(31 downto 0), + SR(0) => SR(0), + halted_reg => \^s2mm_dmasr\(0), + \hsize_vid_reg[15]\(15 downto 0) => \hsize_vid_reg[15]\(15 downto 0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + p_in_d1_cdc_from => p_in_d1_cdc_from, + prmry_in_xored => prmry_in_xored, + prmry_resetn_i_reg => prmry_resetn_i_reg, + prmtr_update_complete => prmtr_update_complete, + s2mm_axi2ip_wrce(5 downto 0) => s2mm_axi2ip_wrce(9 downto 4), + s2mm_cdc2dmac_fsync => s2mm_cdc2dmac_fsync, + \stride_vid_reg[15]\(15 downto 0) => \stride_vid_reg[15]\(15 downto 0), + \vsize_vid_reg[12]\(12 downto 0) => \vsize_vid_reg[12]\(12 downto 0) + ); +I_DMA_REGISTER: entity work.\Arty_Z7_20_axi_vdma_0_0_axi_vdma_register__parameterized0\ + port map ( + D(30 downto 7) => D(31 downto 8), + D(6 downto 0) => D(6 downto 0), + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(0) => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(0), + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]_0\(4 downto 0) => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]_0\(4 downto 0), + \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg_0\ => \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg\, + \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg_0\ => \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg\, + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ => \^s2mm_dmasr\(0), + \GEN_FOR_FLUSH.fsize_err_reg_0\ => \GEN_FOR_FLUSH.fsize_err_reg\, + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6]\ => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6]\, + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6]_0\(0) => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6]_0\(0), + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[11]\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[11]\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[12]\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[12]\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[13]\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[13]\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[15]\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[15]\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18]\(0) => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18]\(0), + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4]\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4]\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4]_0\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4]_0\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[7]\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[7]\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[8]\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[8]\, + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4]\(4 downto 0) => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4]\(4 downto 0), + Q(6 downto 0) => Q(6 downto 0), + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_0\ => \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]\, + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_1\ => \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_0\, + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_2\ => \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_1\, + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_3\ => \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_2\, + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_4\ => \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_3\, + SR(0) => SR(0), + ch2_delay_cnt_en => ch2_delay_cnt_en, + ch2_delay_zero => ch2_delay_zero, + ch2_dly_irq_set => ch2_dly_irq_set, + decerr_i_reg => decerr_i_reg, + dly_irq_reg_0 => dly_irq_reg, + \dmacr_i_reg[2]_0\ => \dmacr_i_reg[2]\, + err_d1_reg_0 => err_d1_reg, + err_d1_reg_1 => err_d1_reg_0, + err_d1_reg_2(3 downto 0) => err_d1_reg_1(3 downto 0), + err_irq_reg_0 => err_irq_reg, + halt_reset => halt_reset, + halted_clr_reg => halted_clr_reg, + initial_frame => initial_frame, + ioc_irq_reg_0 => ioc_irq_reg, + irqdelay_wren_i => irqdelay_wren_i, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + mask_fsync_out_i => mask_fsync_out_i, + num_fstore_minus1(0) => num_fstore_minus1(0), + p_14_out => p_14_out, + p_15_out => p_15_out, + p_6_out => p_6_out, + prmry_in => prmry_in, + prmry_resetn_i_reg => prmry_resetn_i_reg, + reset_counts => reset_counts, + reset_counts_reg_0 => reset_counts_reg, + s2mm_axi2ip_wrce(2 downto 0) => s2mm_axi2ip_wrce(3 downto 1), + s2mm_cdc2dmac_fsync => s2mm_cdc2dmac_fsync, + s2mm_dmacr(22 downto 0) => s2mm_dmacr(22 downto 0), + s2mm_halt_cmplt => s2mm_halt_cmplt, + s2mm_ioc_irq_set => s2mm_ioc_irq_set, + s2mm_ip2axi_introut => s2mm_ip2axi_introut, + s2mm_packet_sof => s2mm_packet_sof, + s2mm_stop => s2mm_stop, + s2mm_tstvect_fsync => s2mm_tstvect_fsync, + s2mm_valid_frame_sync => s2mm_valid_frame_sync, + s2mm_valid_video_prmtrs => s2mm_valid_video_prmtrs, + s_axis_cmd_tvalid_reg(0) => s_axis_cmd_tvalid_reg(0), + s_soft_reset_i0 => s_soft_reset_i0, + slverr_i_reg => slverr_i_reg, + soft_reset_d1_reg => s2mm_soft_reset + ); +LITE_READ_MUX_I: entity work.\Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_mux__parameterized0\ + port map ( + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(31 downto 0) => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(31 downto 0), + \out\(31 downto 0) => \out\(31 downto 0) + ); +\ptr_ref_i_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(8), + Q => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(0), + R => SR(0) + ); +\ptr_ref_i_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(9), + Q => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(1), + R => SR(0) + ); +\ptr_ref_i_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(10), + Q => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(2), + R => SR(0) + ); +\ptr_ref_i_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(11), + Q => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(3), + R => SR(0) + ); +\ptr_ref_i_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_axi2ip_wrce(0), + D => D(12), + Q => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(4), + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_reset is + port ( + in0 : out STD_LOGIC; + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : out STD_LOGIC; + prmry_reset2 : out STD_LOGIC; + \dmacr_i_reg[2]\ : out STD_LOGIC; + halt_i_reg_0 : out STD_LOGIC; + sig_mm2s_dm_prmry_resetn : out STD_LOGIC; + WR_EN : out STD_LOGIC; + \cmnds_queued_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_LINEBUF_NO_SOF.s_axis_fifo_ainit_nosync_reg_reg\ : out STD_LOGIC; + sig_s_h_halt_reg_reg : out STD_LOGIC; + reset_counts_reg : out STD_LOGIC; + scndry_out : out STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + s_axi_lite_aclk : in STD_LOGIC; + m_axis_mm2s_aclk : in STD_LOGIC; + p_77_out : in STD_LOGIC; + s_soft_reset_i0 : in STD_LOGIC; + stop : in STD_LOGIC; + p_71_out : in STD_LOGIC_VECTOR ( 0 to 0 ); + mm2s_axi2ip_wrce : in STD_LOGIC_VECTOR ( 0 to 0 ); + D : in STD_LOGIC_VECTOR ( 0 to 0 ); + hold_ff_q_reg : in STD_LOGIC; + p_24_out : in STD_LOGIC; + \out\ : in STD_LOGIC; + sig_s_ready_out_reg : in STD_LOGIC; + FULL : in STD_LOGIC; + dma_err_4 : in STD_LOGIC; + sig_rst2all_stop_request : in STD_LOGIC; + reset_counts : in STD_LOGIC; + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : in STD_LOGIC; + prmry_in : in STD_LOGIC; + mm2s_halt_cmplt : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_reset : entity is "axi_vdma_reset"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_reset; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_reset is + signal \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_i_1_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_3\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_4\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_1_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_2_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.axis_min_count[0]_i_1_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.axis_min_count[1]_i_1_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.axis_min_count[2]_i_1_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_3_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_i_1_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.lite_min_count[0]_i_1_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.lite_min_count[1]_i_1_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.lite_min_count[2]_i_1_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_3_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.prmry_min_count[0]_i_1_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.prmry_min_count[1]_i_1_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.prmry_min_count[2]_i_1_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_3_n_0\ : STD_LOGIC; + signal \GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_1\ : STD_LOGIC; + signal \GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_4\ : STD_LOGIC; + signal assert_sftrst_d1 : STD_LOGIC; + signal axis_all_idle : STD_LOGIC; + signal axis_min_assert_sftrst : STD_LOGIC; + signal axis_min_count : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal halt_i0 : STD_LOGIC; + signal \^halt_i_reg_0\ : STD_LOGIC; + signal halt_reset_i_1_n_0 : STD_LOGIC; + signal lite_all_idle : STD_LOGIC; + signal lite_min_assert_sftrst : STD_LOGIC; + signal lite_min_count : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal min_assert_sftrst : STD_LOGIC; + signal p_11_out : STD_LOGIC; + signal p_1_out : STD_LOGIC; + signal p_2_out : STD_LOGIC; + signal p_3_out : STD_LOGIC; + signal p_4_out : STD_LOGIC; + signal p_5_out : STD_LOGIC; + signal p_6_out : STD_LOGIC; + signal p_8_out : STD_LOGIC; + signal p_in_d1_cdc_from : STD_LOGIC; + signal p_in_d1_cdc_from_0 : STD_LOGIC; + signal prmry_in_xored : STD_LOGIC; + signal prmry_in_xored_1 : STD_LOGIC; + signal prmry_min_assert_sftrst : STD_LOGIC; + signal prmry_min_count : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal resetn_i : STD_LOGIC; + signal run_stop_d1 : STD_LOGIC; + signal s_soft_reset_i : STD_LOGIC; + signal s_soft_reset_i_d1 : STD_LOGIC; + signal soft_reset_d1 : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \GEN_LINEBUF_NO_SOF.s_axis_fifo_ainit_nosync_reg_i_1\ : label is "soft_lutpair263"; + attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_2\ : label is "soft_lutpair259"; + attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.axis_min_count[0]_i_1\ : label is "soft_lutpair262"; + attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.axis_min_count[2]_i_1\ : label is "soft_lutpair262"; + attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_3\ : label is "soft_lutpair259"; + attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_i_2\ : label is "soft_lutpair258"; + attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.lite_min_count[0]_i_1\ : label is "soft_lutpair261"; + attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.lite_min_count[1]_i_1\ : label is "soft_lutpair258"; + attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.lite_min_count[2]_i_1\ : label is "soft_lutpair261"; + attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_i_2\ : label is "soft_lutpair257"; + attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.prmry_min_count[0]_i_1\ : label is "soft_lutpair257"; + attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.prmry_min_count[2]_i_1\ : label is "soft_lutpair260"; + attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_3\ : label is "soft_lutpair260"; + attribute SOFT_HLUTNM of \cmnds_queued[7]_i_1\ : label is "soft_lutpair263"; +begin + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ <= \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\; + halt_i_reg_0 <= \^halt_i_reg_0\; +\GEN_LINEBUF_NO_SOF.s_axis_fifo_ainit_nosync_reg_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\, + I1 => \out\, + O => \GEN_LINEBUF_NO_SOF.s_axis_fifo_ainit_nosync_reg_reg\ + ); +\GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I\: entity work.Arty_Z7_20_axi_vdma_0_0_cdc_sync_6 + port map ( + SR(0) => \GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2\, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axis_mm2s_aclk => m_axis_mm2s_aclk, + p_1_out => p_1_out, + p_3_out => p_3_out, + p_in_d1_cdc_from => p_in_d1_cdc_from, + prmry_in_xored => prmry_in_xored + ); +\GEN_MIN_FOR_ASYNC.AXIS_IDLE_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized2_7\ + port map ( + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axis_mm2s_aclk => m_axis_mm2s_aclk, + scndry_out => axis_all_idle + ); +\GEN_MIN_FOR_ASYNC.AXIS_MIN_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized3_8\ + port map ( + axis_min_assert_sftrst => axis_min_assert_sftrst, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axis_mm2s_aclk => m_axis_mm2s_aclk, + scndry_out => p_2_out + ); +\GEN_MIN_FOR_ASYNC.AXIS_RESET_CDC_I\: entity work.Arty_Z7_20_axi_vdma_0_0_cdc_sync_9 + port map ( + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axis_mm2s_aclk => m_axis_mm2s_aclk, + p_3_out => p_3_out, + s_soft_reset_i => s_soft_reset_i, + s_soft_reset_i_d1 => s_soft_reset_i_d1 + ); +\GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F0E0FFFFF0E0F0E0" + ) + port map ( + I0 => prmry_min_assert_sftrst, + I1 => p_5_out, + I2 => min_assert_sftrst, + I3 => p_2_out, + I4 => s_soft_reset_i_d1, + I5 => s_soft_reset_i, + O => \GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_i_1_n_0\ + ); +\GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_i_1_n_0\, + Q => min_assert_sftrst, + R => '0' + ); +\GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I\: entity work.Arty_Z7_20_axi_vdma_0_0_cdc_sync_10 + port map ( + SR(0) => \GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2\, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + p_4_out => p_4_out, + p_6_out => p_6_out, + p_in_d1_cdc_from => p_in_d1_cdc_from_0, + prmry_in_xored => prmry_in_xored_1, + s_axi_lite_aclk => s_axi_lite_aclk + ); +\GEN_MIN_FOR_ASYNC.LITE_IDLE_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized0_11\ + port map ( + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + s_axi_lite_aclk => s_axi_lite_aclk, + scndry_out => lite_all_idle + ); +\GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized1_12\ + port map ( + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\ => p_2_out, + \GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_reg\ => \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_4\, + SR(0) => \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_3\, + lite_min_assert_sftrst => lite_min_assert_sftrst, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + p_11_out => p_11_out, + p_in_d1_cdc_from => p_in_d1_cdc_from_0, + p_in_d1_cdc_from_1 => p_in_d1_cdc_from, + prmry_in_xored => prmry_in_xored_1, + prmry_in_xored_0 => prmry_in_xored, + prmry_min_assert_sftrst => prmry_min_assert_sftrst, + s_axi_lite_aclk => s_axi_lite_aclk, + s_soft_reset_i => s_soft_reset_i, + s_soft_reset_i_d1 => s_soft_reset_i_d1, + scndry_out => p_5_out + ); +\GEN_MIN_FOR_ASYNC.LITE_RESET_CDC_I\: entity work.Arty_Z7_20_axi_vdma_0_0_cdc_sync_13 + port map ( + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + p_6_out => p_6_out, + s_axi_lite_aclk => s_axi_lite_aclk, + s_soft_reset_i => s_soft_reset_i, + s_soft_reset_i_d1 => s_soft_reset_i_d1 + ); +\GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00FE" + ) + port map ( + I0 => axis_min_assert_sftrst, + I1 => \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_2_n_0\, + I2 => p_3_out, + I3 => p_1_out, + O => \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_1_n_0\ + ); +\GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => axis_min_count(2), + I1 => axis_min_count(0), + I2 => axis_min_assert_sftrst, + I3 => axis_min_count(3), + I4 => axis_min_count(1), + O => \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_2_n_0\ + ); +\GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_1_n_0\, + Q => axis_min_assert_sftrst, + R => '0' + ); +\GEN_MIN_FOR_ASYNC.axis_min_count[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"8000FFFF" + ) + port map ( + I0 => axis_min_count(1), + I1 => axis_min_count(3), + I2 => axis_min_assert_sftrst, + I3 => axis_min_count(2), + I4 => axis_min_count(0), + O => \GEN_MIN_FOR_ASYNC.axis_min_count[0]_i_1_n_0\ + ); +\GEN_MIN_FOR_ASYNC.axis_min_count[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D5AA55AA" + ) + port map ( + I0 => axis_min_count(1), + I1 => axis_min_count(3), + I2 => axis_min_assert_sftrst, + I3 => axis_min_count(0), + I4 => axis_min_count(2), + O => \GEN_MIN_FOR_ASYNC.axis_min_count[1]_i_1_n_0\ + ); +\GEN_MIN_FOR_ASYNC.axis_min_count[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D5FFAA00" + ) + port map ( + I0 => axis_min_count(1), + I1 => axis_min_count(3), + I2 => axis_min_assert_sftrst, + I3 => axis_min_count(0), + I4 => axis_min_count(2), + O => \GEN_MIN_FOR_ASYNC.axis_min_count[2]_i_1_n_0\ + ); +\GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EA00AA00AA00AA00" + ) + port map ( + I0 => axis_all_idle, + I1 => axis_min_count(1), + I2 => axis_min_count(3), + I3 => axis_min_assert_sftrst, + I4 => axis_min_count(0), + I5 => axis_min_count(2), + O => \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0\ + ); +\GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"E6CCCCCC" + ) + port map ( + I0 => axis_min_count(1), + I1 => axis_min_count(3), + I2 => axis_min_assert_sftrst, + I3 => axis_min_count(0), + I4 => axis_min_count(2), + O => \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_3_n_0\ + ); +\GEN_MIN_FOR_ASYNC.axis_min_count_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0\, + D => \GEN_MIN_FOR_ASYNC.axis_min_count[0]_i_1_n_0\, + Q => axis_min_count(0), + R => \GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2\ + ); +\GEN_MIN_FOR_ASYNC.axis_min_count_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0\, + D => \GEN_MIN_FOR_ASYNC.axis_min_count[1]_i_1_n_0\, + Q => axis_min_count(1), + R => \GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2\ + ); +\GEN_MIN_FOR_ASYNC.axis_min_count_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0\, + D => \GEN_MIN_FOR_ASYNC.axis_min_count[2]_i_1_n_0\, + Q => axis_min_count(2), + R => \GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2\ + ); +\GEN_MIN_FOR_ASYNC.axis_min_count_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0\, + D => \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_3_n_0\, + Q => axis_min_count(3), + R => \GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2\ + ); +\GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00FE" + ) + port map ( + I0 => lite_min_assert_sftrst, + I1 => p_8_out, + I2 => p_6_out, + I3 => p_4_out, + O => \GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_i_1_n_0\ + ); +\GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => lite_min_count(2), + I1 => lite_min_count(0), + I2 => lite_min_assert_sftrst, + I3 => lite_min_count(3), + I4 => lite_min_count(1), + O => p_8_out + ); +\GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_i_1_n_0\, + Q => lite_min_assert_sftrst, + R => '0' + ); +\GEN_MIN_FOR_ASYNC.lite_min_count[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"8000FFFF" + ) + port map ( + I0 => lite_min_count(1), + I1 => lite_min_count(3), + I2 => lite_min_assert_sftrst, + I3 => lite_min_count(2), + I4 => lite_min_count(0), + O => \GEN_MIN_FOR_ASYNC.lite_min_count[0]_i_1_n_0\ + ); +\GEN_MIN_FOR_ASYNC.lite_min_count[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D5AA55AA" + ) + port map ( + I0 => lite_min_count(1), + I1 => lite_min_count(3), + I2 => lite_min_assert_sftrst, + I3 => lite_min_count(0), + I4 => lite_min_count(2), + O => \GEN_MIN_FOR_ASYNC.lite_min_count[1]_i_1_n_0\ + ); +\GEN_MIN_FOR_ASYNC.lite_min_count[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D5FFAA00" + ) + port map ( + I0 => lite_min_count(1), + I1 => lite_min_count(3), + I2 => lite_min_assert_sftrst, + I3 => lite_min_count(0), + I4 => lite_min_count(2), + O => \GEN_MIN_FOR_ASYNC.lite_min_count[2]_i_1_n_0\ + ); +\GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EA00AA00AA00AA00" + ) + port map ( + I0 => lite_all_idle, + I1 => lite_min_count(1), + I2 => lite_min_count(3), + I3 => lite_min_assert_sftrst, + I4 => lite_min_count(0), + I5 => lite_min_count(2), + O => \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0\ + ); +\GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"E6CCCCCC" + ) + port map ( + I0 => lite_min_count(1), + I1 => lite_min_count(3), + I2 => lite_min_assert_sftrst, + I3 => lite_min_count(0), + I4 => lite_min_count(2), + O => \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_3_n_0\ + ); +\GEN_MIN_FOR_ASYNC.lite_min_count_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0\, + D => \GEN_MIN_FOR_ASYNC.lite_min_count[0]_i_1_n_0\, + Q => lite_min_count(0), + R => \GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2\ + ); +\GEN_MIN_FOR_ASYNC.lite_min_count_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0\, + D => \GEN_MIN_FOR_ASYNC.lite_min_count[1]_i_1_n_0\, + Q => lite_min_count(1), + R => \GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2\ + ); +\GEN_MIN_FOR_ASYNC.lite_min_count_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0\, + D => \GEN_MIN_FOR_ASYNC.lite_min_count[2]_i_1_n_0\, + Q => lite_min_count(2), + R => \GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2\ + ); +\GEN_MIN_FOR_ASYNC.lite_min_count_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0\, + D => \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_3_n_0\, + Q => lite_min_count(3), + R => \GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2\ + ); +\GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => prmry_min_count(2), + I1 => prmry_min_count(0), + I2 => prmry_min_assert_sftrst, + I3 => prmry_min_count(3), + I4 => prmry_min_count(1), + O => p_11_out + ); +\GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_4\, + Q => prmry_min_assert_sftrst, + R => '0' + ); +\GEN_MIN_FOR_ASYNC.prmry_min_count[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"8000FFFF" + ) + port map ( + I0 => prmry_min_count(1), + I1 => prmry_min_count(3), + I2 => prmry_min_assert_sftrst, + I3 => prmry_min_count(2), + I4 => prmry_min_count(0), + O => \GEN_MIN_FOR_ASYNC.prmry_min_count[0]_i_1_n_0\ + ); +\GEN_MIN_FOR_ASYNC.prmry_min_count[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D5AA55AA" + ) + port map ( + I0 => prmry_min_count(1), + I1 => prmry_min_count(3), + I2 => prmry_min_assert_sftrst, + I3 => prmry_min_count(0), + I4 => prmry_min_count(2), + O => \GEN_MIN_FOR_ASYNC.prmry_min_count[1]_i_1_n_0\ + ); +\GEN_MIN_FOR_ASYNC.prmry_min_count[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D5FFAA00" + ) + port map ( + I0 => prmry_min_count(1), + I1 => prmry_min_count(3), + I2 => prmry_min_assert_sftrst, + I3 => prmry_min_count(0), + I4 => prmry_min_count(2), + O => \GEN_MIN_FOR_ASYNC.prmry_min_count[2]_i_1_n_0\ + ); +\GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EA00AA00AA00AA00" + ) + port map ( + I0 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\, + I1 => prmry_min_count(1), + I2 => prmry_min_count(3), + I3 => prmry_min_assert_sftrst, + I4 => prmry_min_count(0), + I5 => prmry_min_count(2), + O => \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0\ + ); +\GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"E6CCCCCC" + ) + port map ( + I0 => prmry_min_count(1), + I1 => prmry_min_count(3), + I2 => prmry_min_assert_sftrst, + I3 => prmry_min_count(0), + I4 => prmry_min_count(2), + O => \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_3_n_0\ + ); +\GEN_MIN_FOR_ASYNC.prmry_min_count_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0\, + D => \GEN_MIN_FOR_ASYNC.prmry_min_count[0]_i_1_n_0\, + Q => prmry_min_count(0), + R => \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_3\ + ); +\GEN_MIN_FOR_ASYNC.prmry_min_count_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0\, + D => \GEN_MIN_FOR_ASYNC.prmry_min_count[1]_i_1_n_0\, + Q => prmry_min_count(1), + R => \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_3\ + ); +\GEN_MIN_FOR_ASYNC.prmry_min_count_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0\, + D => \GEN_MIN_FOR_ASYNC.prmry_min_count[2]_i_1_n_0\, + Q => prmry_min_count(2), + R => \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_3\ + ); +\GEN_MIN_FOR_ASYNC.prmry_min_count_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0\, + D => \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_3_n_0\, + Q => prmry_min_count(3), + R => \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_3\ + ); +\GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/sig_s_h_halt_reg_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\, + I1 => sig_rst2all_stop_request, + O => sig_s_h_halt_reg_reg + ); +\GEN_RESET_FOR_ASYNC.AXIS_RESET_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized5_14\ + port map ( + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axis_mm2s_aclk => m_axis_mm2s_aclk, + prmry_in => resetn_i, + scndry_out => scndry_out + ); +\GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized4_15\ + port map ( + D(0) => D(0), + assert_sftrst_d1 => assert_sftrst_d1, + \dmacr_i_reg[2]\ => \dmacr_i_reg[2]\, + halt_i0 => halt_i0, + halt_i_reg => \GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_4\, + halt_i_reg_0 => \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\, + halt_reset_reg => \^halt_i_reg_0\, + hrd_resetn_i_reg => prmry_in, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + min_assert_sftrst => min_assert_sftrst, + mm2s_axi2ip_wrce(0) => mm2s_axi2ip_wrce(0), + \out\ => \out\, + p_71_out(0) => p_71_out(0), + p_77_out => p_77_out, + prmry_in => resetn_i, + prmry_reset2 => prmry_reset2, + reset_counts => reset_counts, + reset_counts_reg => reset_counts_reg, + run_stop_d1_reg => \GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_1\, + s_axi_lite_aclk => s_axi_lite_aclk, + s_soft_reset_i => s_soft_reset_i, + \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ => sig_mm2s_dm_prmry_resetn, + stop => stop + ); +assert_sftrst_d1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => min_assert_sftrst, + Q => assert_sftrst_d1, + R => '0' + ); +\cmnds_queued[7]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FEFF" + ) + port map ( + I0 => dma_err_4, + I1 => p_77_out, + I2 => \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\, + I3 => \out\, + O => \cmnds_queued_reg[7]\(0) + ); +\gf36e1_inst.sngfifo36e1_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000100" + ) + port map ( + I0 => hold_ff_q_reg, + I1 => p_24_out, + I2 => \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\, + I3 => \out\, + I4 => sig_s_ready_out_reg, + I5 => FULL, + O => WR_EN + ); +halt_i_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"AEAEFFAE" + ) + port map ( + I0 => stop, + I1 => run_stop_d1, + I2 => p_71_out(0), + I3 => p_77_out, + I4 => soft_reset_d1, + O => halt_i0 + ); +halt_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_4\, + Q => \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\, + R => '0' + ); +halt_reset_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"222222222222F222" + ) + port map ( + I0 => \^halt_i_reg_0\, + I1 => p_71_out(0), + I2 => \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\, + I3 => mm2s_halt_cmplt, + I4 => p_77_out, + I5 => stop, + O => halt_reset_i_1_n_0 + ); +halt_reset_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => halt_reset_i_1_n_0, + Q => \^halt_i_reg_0\, + R => '0' + ); +prmry_resetn_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => resetn_i, + Q => in0, + R => '0' + ); +run_stop_d1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_1\, + Q => run_stop_d1, + R => '0' + ); +s_soft_reset_i_d1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => s_soft_reset_i, + Q => s_soft_reset_i_d1, + R => '0' + ); +s_soft_reset_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => s_soft_reset_i0, + Q => s_soft_reset_i, + R => '0' + ); +soft_reset_d1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => p_77_out, + Q => soft_reset_d1, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_reset_2 is + port ( + soft_reset_d1 : out STD_LOGIC; + in0 : out STD_LOGIC; + run_stop_d1 : out STD_LOGIC; + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ : out STD_LOGIC; + prmry_reset2_0 : out STD_LOGIC; + \dmacr_i_reg[2]\ : out STD_LOGIC; + p_12_out : out STD_LOGIC; + \FSM_sequential_dmacntrl_cs_reg[2]\ : out STD_LOGIC; + halt_i_reg_0 : out STD_LOGIC; + sig_s2mm_dm_prmry_resetn : out STD_LOGIC; + \cmnds_queued_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + reset_counts_reg : out STD_LOGIC; + sig_s_h_halt_reg_reg : out STD_LOGIC; + scndry_out : out STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + s_axi_lite_aclk : in STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC; + s2mm_soft_reset : in STD_LOGIC; + s_soft_reset_i0_3 : in STD_LOGIC; + s2mm_dmacr : in STD_LOGIC_VECTOR ( 0 to 0 ); + s2mm_stop : in STD_LOGIC; + s2mm_axi2ip_wrce : in STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + CO : in STD_LOGIC_VECTOR ( 0 to 0 ); + dma_err : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + halt_i0 : in STD_LOGIC; + \out\ : in STD_LOGIC; + reset_counts_5 : in STD_LOGIC; + sig_rst2all_stop_request_6 : in STD_LOGIC; + \cmnds_queued_reg[0]\ : in STD_LOGIC; + prmry_in : in STD_LOGIC; + s2mm_halt_cmplt : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_reset_2 : entity is "axi_vdma_reset"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_reset_2; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_reset_2 is + signal \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_i_1_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_3\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_4\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_1_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.axis_min_count[0]_i_1__0_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.axis_min_count[1]_i_1_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.axis_min_count[2]_i_1_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_3_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_i_1_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.lite_min_count[0]_i_1__0_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.lite_min_count[1]_i_1_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.lite_min_count[2]_i_1_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_3_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.prmry_min_count[0]_i_1__0_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.prmry_min_count[1]_i_1_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.prmry_min_count[2]_i_1_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0\ : STD_LOGIC; + signal \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_3_n_0\ : STD_LOGIC; + signal \GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_1\ : STD_LOGIC; + signal \GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_4\ : STD_LOGIC; + signal assert_sftrst_d1 : STD_LOGIC; + signal axis_all_idle : STD_LOGIC; + signal axis_min_assert_sftrst : STD_LOGIC; + signal axis_min_count : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^halt_i_reg_0\ : STD_LOGIC; + signal halt_reset_i_1_n_0 : STD_LOGIC; + signal lite_all_idle : STD_LOGIC; + signal lite_min_assert_sftrst : STD_LOGIC; + signal lite_min_count : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal min_assert_sftrst : STD_LOGIC; + signal p_11_out : STD_LOGIC; + signal p_1_out : STD_LOGIC; + signal p_2_out : STD_LOGIC; + signal p_3_out : STD_LOGIC; + signal p_4_out : STD_LOGIC; + signal p_5_out : STD_LOGIC; + signal p_6_out : STD_LOGIC; + signal p_8_out : STD_LOGIC; + signal p_in_d1_cdc_from : STD_LOGIC; + signal p_in_d1_cdc_from_0 : STD_LOGIC; + signal prmry_in_xored : STD_LOGIC; + signal prmry_in_xored_1 : STD_LOGIC; + signal prmry_min_assert_sftrst : STD_LOGIC; + signal prmry_min_count : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal resetn_i : STD_LOGIC; + signal s_soft_reset_i : STD_LOGIC; + signal s_soft_reset_i_d1 : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_2__0\ : label is "soft_lutpair267"; + attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.axis_min_count[0]_i_1__0\ : label is "soft_lutpair267"; + attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.axis_min_count[2]_i_1\ : label is "soft_lutpair269"; + attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_3\ : label is "soft_lutpair269"; + attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_i_2__0\ : label is "soft_lutpair270"; + attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.lite_min_count[0]_i_1__0\ : label is "soft_lutpair271"; + attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.lite_min_count[1]_i_1\ : label is "soft_lutpair271"; + attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_3\ : label is "soft_lutpair270"; + attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_i_2__0\ : label is "soft_lutpair266"; + attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.prmry_min_count[0]_i_1__0\ : label is "soft_lutpair266"; + attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.prmry_min_count[2]_i_1\ : label is "soft_lutpair268"; + attribute SOFT_HLUTNM of \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_3\ : label is "soft_lutpair268"; + attribute SOFT_HLUTNM of \I_RESET/sig_s_h_halt_reg_i_1\ : label is "soft_lutpair272"; + attribute SOFT_HLUTNM of \cmnds_queued[7]_i_1__0\ : label is "soft_lutpair272"; +begin + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ <= \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\; + halt_i_reg_0 <= \^halt_i_reg_0\; +\GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I\: entity work.Arty_Z7_20_axi_vdma_0_0_cdc_sync + port map ( + SR(0) => \GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2\, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + p_1_out => p_1_out, + p_3_out => p_3_out, + p_in_d1_cdc_from => p_in_d1_cdc_from, + prmry_in_xored => prmry_in_xored, + s_axis_s2mm_aclk => s_axis_s2mm_aclk + ); +\GEN_MIN_FOR_ASYNC.AXIS_IDLE_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized2\ + port map ( + \FSM_sequential_dmacntrl_cs_reg[2]\ => \FSM_sequential_dmacntrl_cs_reg[2]\, + \cmnds_queued_reg[0]\ => \cmnds_queued_reg[0]\, + dma_err => dma_err, + halt_i_reg => \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + s2mm_soft_reset => s2mm_soft_reset, + s_axis_s2mm_aclk => s_axis_s2mm_aclk, + scndry_out => axis_all_idle + ); +\GEN_MIN_FOR_ASYNC.AXIS_MIN_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized3\ + port map ( + axis_min_assert_sftrst => axis_min_assert_sftrst, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + s_axis_s2mm_aclk => s_axis_s2mm_aclk, + scndry_out => p_2_out + ); +\GEN_MIN_FOR_ASYNC.AXIS_RESET_CDC_I\: entity work.Arty_Z7_20_axi_vdma_0_0_cdc_sync_3 + port map ( + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + p_3_out => p_3_out, + s_axis_s2mm_aclk => s_axis_s2mm_aclk, + s_soft_reset_i => s_soft_reset_i, + s_soft_reset_i_d1 => s_soft_reset_i_d1 + ); +\GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F0E0FFFFF0E0F0E0" + ) + port map ( + I0 => prmry_min_assert_sftrst, + I1 => p_5_out, + I2 => min_assert_sftrst, + I3 => p_2_out, + I4 => s_soft_reset_i_d1, + I5 => s_soft_reset_i, + O => \GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_i_1_n_0\ + ); +\GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_MIN_FOR_ASYNC.GEN_FOR_NO_SG.min_assert_sftrst_i_1_n_0\, + Q => min_assert_sftrst, + R => '0' + ); +\GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I\: entity work.Arty_Z7_20_axi_vdma_0_0_cdc_sync_4 + port map ( + SR(0) => \GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2\, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + p_4_out => p_4_out, + p_6_out => p_6_out, + p_in_d1_cdc_from => p_in_d1_cdc_from_0, + prmry_in_xored => prmry_in_xored_1, + s_axi_lite_aclk => s_axi_lite_aclk + ); +\GEN_MIN_FOR_ASYNC.LITE_IDLE_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized0\ + port map ( + \cmnds_queued_reg[0]\ => \cmnds_queued_reg[0]\, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + s_axi_lite_aclk => s_axi_lite_aclk, + scndry_out => lite_all_idle + ); +\GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized1\ + port map ( + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\ => p_2_out, + \GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_reg\ => \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_4\, + SR(0) => \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_3\, + lite_min_assert_sftrst => lite_min_assert_sftrst, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + p_11_out => p_11_out, + p_in_d1_cdc_from => p_in_d1_cdc_from_0, + p_in_d1_cdc_from_1 => p_in_d1_cdc_from, + prmry_in_xored => prmry_in_xored_1, + prmry_in_xored_0 => prmry_in_xored, + prmry_min_assert_sftrst => prmry_min_assert_sftrst, + s_axi_lite_aclk => s_axi_lite_aclk, + s_soft_reset_i => s_soft_reset_i, + s_soft_reset_i_d1 => s_soft_reset_i_d1, + scndry_out => p_5_out + ); +\GEN_MIN_FOR_ASYNC.LITE_RESET_CDC_I\: entity work.Arty_Z7_20_axi_vdma_0_0_cdc_sync_5 + port map ( + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + p_6_out => p_6_out, + s_axi_lite_aclk => s_axi_lite_aclk, + s_soft_reset_i => s_soft_reset_i, + s_soft_reset_i_d1 => s_soft_reset_i_d1 + ); +\GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00FE" + ) + port map ( + I0 => axis_min_assert_sftrst, + I1 => \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_2__0_n_0\, + I2 => p_3_out, + I3 => p_1_out, + O => \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_1_n_0\ + ); +\GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => axis_min_count(2), + I1 => axis_min_count(0), + I2 => axis_min_assert_sftrst, + I3 => axis_min_count(3), + I4 => axis_min_count(1), + O => \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_2__0_n_0\ + ); +\GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => \GEN_MIN_FOR_ASYNC.axis_min_assert_sftrst_i_1_n_0\, + Q => axis_min_assert_sftrst, + R => '0' + ); +\GEN_MIN_FOR_ASYNC.axis_min_count[0]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"8000FFFF" + ) + port map ( + I0 => axis_min_count(1), + I1 => axis_min_count(3), + I2 => axis_min_assert_sftrst, + I3 => axis_min_count(2), + I4 => axis_min_count(0), + O => \GEN_MIN_FOR_ASYNC.axis_min_count[0]_i_1__0_n_0\ + ); +\GEN_MIN_FOR_ASYNC.axis_min_count[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D5AA55AA" + ) + port map ( + I0 => axis_min_count(1), + I1 => axis_min_count(3), + I2 => axis_min_assert_sftrst, + I3 => axis_min_count(0), + I4 => axis_min_count(2), + O => \GEN_MIN_FOR_ASYNC.axis_min_count[1]_i_1_n_0\ + ); +\GEN_MIN_FOR_ASYNC.axis_min_count[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D5FFAA00" + ) + port map ( + I0 => axis_min_count(1), + I1 => axis_min_count(3), + I2 => axis_min_assert_sftrst, + I3 => axis_min_count(0), + I4 => axis_min_count(2), + O => \GEN_MIN_FOR_ASYNC.axis_min_count[2]_i_1_n_0\ + ); +\GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EA00AA00AA00AA00" + ) + port map ( + I0 => axis_all_idle, + I1 => axis_min_count(1), + I2 => axis_min_count(3), + I3 => axis_min_assert_sftrst, + I4 => axis_min_count(0), + I5 => axis_min_count(2), + O => \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0\ + ); +\GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"E6CCCCCC" + ) + port map ( + I0 => axis_min_count(1), + I1 => axis_min_count(3), + I2 => axis_min_assert_sftrst, + I3 => axis_min_count(0), + I4 => axis_min_count(2), + O => \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_3_n_0\ + ); +\GEN_MIN_FOR_ASYNC.axis_min_count_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0\, + D => \GEN_MIN_FOR_ASYNC.axis_min_count[0]_i_1__0_n_0\, + Q => axis_min_count(0), + R => \GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2\ + ); +\GEN_MIN_FOR_ASYNC.axis_min_count_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0\, + D => \GEN_MIN_FOR_ASYNC.axis_min_count[1]_i_1_n_0\, + Q => axis_min_count(1), + R => \GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2\ + ); +\GEN_MIN_FOR_ASYNC.axis_min_count_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0\, + D => \GEN_MIN_FOR_ASYNC.axis_min_count[2]_i_1_n_0\, + Q => axis_min_count(2), + R => \GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2\ + ); +\GEN_MIN_FOR_ASYNC.axis_min_count_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_2_n_0\, + D => \GEN_MIN_FOR_ASYNC.axis_min_count[3]_i_3_n_0\, + Q => axis_min_count(3), + R => \GEN_MIN_FOR_ASYNC.AXIS_CLR_CDC_I_n_2\ + ); +\GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00FE" + ) + port map ( + I0 => lite_min_assert_sftrst, + I1 => p_8_out, + I2 => p_6_out, + I3 => p_4_out, + O => \GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_i_1_n_0\ + ); +\GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => lite_min_count(2), + I1 => lite_min_count(0), + I2 => lite_min_assert_sftrst, + I3 => lite_min_count(3), + I4 => lite_min_count(1), + O => p_8_out + ); +\GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \GEN_MIN_FOR_ASYNC.lite_min_assert_sftrst_i_1_n_0\, + Q => lite_min_assert_sftrst, + R => '0' + ); +\GEN_MIN_FOR_ASYNC.lite_min_count[0]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"8000FFFF" + ) + port map ( + I0 => lite_min_count(1), + I1 => lite_min_count(3), + I2 => lite_min_assert_sftrst, + I3 => lite_min_count(2), + I4 => lite_min_count(0), + O => \GEN_MIN_FOR_ASYNC.lite_min_count[0]_i_1__0_n_0\ + ); +\GEN_MIN_FOR_ASYNC.lite_min_count[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D5AA55AA" + ) + port map ( + I0 => lite_min_count(1), + I1 => lite_min_count(3), + I2 => lite_min_assert_sftrst, + I3 => lite_min_count(0), + I4 => lite_min_count(2), + O => \GEN_MIN_FOR_ASYNC.lite_min_count[1]_i_1_n_0\ + ); +\GEN_MIN_FOR_ASYNC.lite_min_count[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D5FFAA00" + ) + port map ( + I0 => lite_min_count(1), + I1 => lite_min_count(3), + I2 => lite_min_assert_sftrst, + I3 => lite_min_count(0), + I4 => lite_min_count(2), + O => \GEN_MIN_FOR_ASYNC.lite_min_count[2]_i_1_n_0\ + ); +\GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EA00AA00AA00AA00" + ) + port map ( + I0 => lite_all_idle, + I1 => lite_min_count(1), + I2 => lite_min_count(3), + I3 => lite_min_assert_sftrst, + I4 => lite_min_count(0), + I5 => lite_min_count(2), + O => \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0\ + ); +\GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"E6CCCCCC" + ) + port map ( + I0 => lite_min_count(1), + I1 => lite_min_count(3), + I2 => lite_min_assert_sftrst, + I3 => lite_min_count(0), + I4 => lite_min_count(2), + O => \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_3_n_0\ + ); +\GEN_MIN_FOR_ASYNC.lite_min_count_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0\, + D => \GEN_MIN_FOR_ASYNC.lite_min_count[0]_i_1__0_n_0\, + Q => lite_min_count(0), + R => \GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2\ + ); +\GEN_MIN_FOR_ASYNC.lite_min_count_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0\, + D => \GEN_MIN_FOR_ASYNC.lite_min_count[1]_i_1_n_0\, + Q => lite_min_count(1), + R => \GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2\ + ); +\GEN_MIN_FOR_ASYNC.lite_min_count_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0\, + D => \GEN_MIN_FOR_ASYNC.lite_min_count[2]_i_1_n_0\, + Q => lite_min_count(2), + R => \GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2\ + ); +\GEN_MIN_FOR_ASYNC.lite_min_count_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_2_n_0\, + D => \GEN_MIN_FOR_ASYNC.lite_min_count[3]_i_3_n_0\, + Q => lite_min_count(3), + R => \GEN_MIN_FOR_ASYNC.LITE_CLR_CDC_I_n_2\ + ); +\GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => prmry_min_count(2), + I1 => prmry_min_count(0), + I2 => prmry_min_assert_sftrst, + I3 => prmry_min_count(3), + I4 => prmry_min_count(1), + O => p_11_out + ); +\GEN_MIN_FOR_ASYNC.prmry_min_assert_sftrst_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_4\, + Q => prmry_min_assert_sftrst, + R => '0' + ); +\GEN_MIN_FOR_ASYNC.prmry_min_count[0]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"8000FFFF" + ) + port map ( + I0 => prmry_min_count(1), + I1 => prmry_min_count(3), + I2 => prmry_min_assert_sftrst, + I3 => prmry_min_count(2), + I4 => prmry_min_count(0), + O => \GEN_MIN_FOR_ASYNC.prmry_min_count[0]_i_1__0_n_0\ + ); +\GEN_MIN_FOR_ASYNC.prmry_min_count[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D5AA55AA" + ) + port map ( + I0 => prmry_min_count(1), + I1 => prmry_min_count(3), + I2 => prmry_min_assert_sftrst, + I3 => prmry_min_count(0), + I4 => prmry_min_count(2), + O => \GEN_MIN_FOR_ASYNC.prmry_min_count[1]_i_1_n_0\ + ); +\GEN_MIN_FOR_ASYNC.prmry_min_count[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D5FFAA00" + ) + port map ( + I0 => prmry_min_count(1), + I1 => prmry_min_count(3), + I2 => prmry_min_assert_sftrst, + I3 => prmry_min_count(0), + I4 => prmry_min_count(2), + O => \GEN_MIN_FOR_ASYNC.prmry_min_count[2]_i_1_n_0\ + ); +\GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EA00AA00AA00AA00" + ) + port map ( + I0 => \cmnds_queued_reg[0]\, + I1 => prmry_min_count(1), + I2 => prmry_min_count(3), + I3 => prmry_min_assert_sftrst, + I4 => prmry_min_count(0), + I5 => prmry_min_count(2), + O => \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0\ + ); +\GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"E6CCCCCC" + ) + port map ( + I0 => prmry_min_count(1), + I1 => prmry_min_count(3), + I2 => prmry_min_assert_sftrst, + I3 => prmry_min_count(0), + I4 => prmry_min_count(2), + O => \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_3_n_0\ + ); +\GEN_MIN_FOR_ASYNC.prmry_min_count_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0\, + D => \GEN_MIN_FOR_ASYNC.prmry_min_count[0]_i_1__0_n_0\, + Q => prmry_min_count(0), + R => \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_3\ + ); +\GEN_MIN_FOR_ASYNC.prmry_min_count_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0\, + D => \GEN_MIN_FOR_ASYNC.prmry_min_count[1]_i_1_n_0\, + Q => prmry_min_count(1), + R => \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_3\ + ); +\GEN_MIN_FOR_ASYNC.prmry_min_count_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0\, + D => \GEN_MIN_FOR_ASYNC.prmry_min_count[2]_i_1_n_0\, + Q => prmry_min_count(2), + R => \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_3\ + ); +\GEN_MIN_FOR_ASYNC.prmry_min_count_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_2_n_0\, + D => \GEN_MIN_FOR_ASYNC.prmry_min_count[3]_i_3_n_0\, + Q => prmry_min_count(3), + R => \GEN_MIN_FOR_ASYNC.LITE_MIN_CDC_I_n_3\ + ); +\GEN_RESET_FOR_ASYNC.AXIS_RESET_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized5\ + port map ( + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + prmry_in => resetn_i, + s_axis_s2mm_aclk => s_axis_s2mm_aclk, + scndry_out => scndry_out + ); +\GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized4\ + port map ( + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[2]\(0) => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[2]\(0), + assert_sftrst_d1 => assert_sftrst_d1, + \dmacr_i_reg[2]\ => \dmacr_i_reg[2]\, + halt_i0 => halt_i0, + halt_i_reg => \GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_4\, + halt_i_reg_0 => \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\, + halt_reset_reg => \^halt_i_reg_0\, + hrd_resetn_i_reg => prmry_in, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + min_assert_sftrst => min_assert_sftrst, + \out\ => \out\, + prmry_in => resetn_i, + prmry_reset2_0 => prmry_reset2_0, + reset_counts_5 => reset_counts_5, + reset_counts_reg => reset_counts_reg, + run_stop_d1_reg => \GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_1\, + s2mm_axi2ip_wrce(0) => s2mm_axi2ip_wrce(0), + s2mm_dmacr(0) => s2mm_dmacr(0), + s2mm_soft_reset => s2mm_soft_reset, + s2mm_stop => s2mm_stop, + s_axi_lite_aclk => s_axi_lite_aclk, + s_soft_reset_i => s_soft_reset_i, + \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ => sig_s2mm_dm_prmry_resetn + ); +\GEN_STS_GRTR_THAN_8.undrflo_err_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000002" + ) + port map ( + I0 => CO(0), + I1 => \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\, + I2 => s2mm_soft_reset, + I3 => dma_err, + I4 => Q(0), + O => p_12_out + ); +\I_RESET/sig_s_h_halt_reg_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\, + I1 => sig_rst2all_stop_request_6, + O => sig_s_h_halt_reg_reg + ); +assert_sftrst_d1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => min_assert_sftrst, + Q => assert_sftrst_d1, + R => '0' + ); +\cmnds_queued[7]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FEFF" + ) + port map ( + I0 => dma_err, + I1 => s2mm_soft_reset, + I2 => \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\, + I3 => \out\, + O => \cmnds_queued_reg[7]\(0) + ); +halt_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_4\, + Q => \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\, + R => '0' + ); +halt_reset_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"222222222222F222" + ) + port map ( + I0 => \^halt_i_reg_0\, + I1 => s2mm_dmacr(0), + I2 => \^generate_level_p_s_cdc.single_bit.input_flop.reg_plevel_in_cdc_from\, + I3 => s2mm_halt_cmplt, + I4 => s2mm_soft_reset, + I5 => s2mm_stop, + O => halt_reset_i_1_n_0 + ); +halt_reset_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => halt_reset_i_1_n_0, + Q => \^halt_i_reg_0\, + R => '0' + ); +prmry_resetn_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => resetn_i, + Q => in0, + R => '0' + ); +run_stop_d1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_RESET_FOR_ASYNC.HARD_RESET_CDC_I_n_1\, + Q => run_stop_d1, + R => '0' + ); +s_soft_reset_i_d1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_soft_reset_i, + Q => s_soft_reset_i_d1, + R => '0' + ); +s_soft_reset_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s_soft_reset_i0_3, + Q => s_soft_reset_i, + R => '0' + ); +soft_reset_d1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s2mm_soft_reset, + Q => soft_reset_d1, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_axi_vdma_sm__parameterized0\ is + port ( + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg\ : out STD_LOGIC; + tstvect_fsync_d2 : out STD_LOGIC; + tstvect_fsync_d1 : out STD_LOGIC; + s_axis_cmd_tvalid_reg : out STD_LOGIC; + zero_hsize_err : out STD_LOGIC; + zero_vsize_err : out STD_LOGIC; + drop_fsync_d_pulse_gen_fsize_less_err_d1 : out STD_LOGIC; + fsize_mismatch_err_s1 : out STD_LOGIC; + \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + halt_i0 : out STD_LOGIC; + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0\ : out STD_LOGIC; + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_irqthresh_decr_mask_sig_reg\ : out STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + load_new_addr : out STD_LOGIC; + halted_set_i0 : out STD_LOGIC; + s2mm_ftchcmdsts_idle : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 4 downto 0 ); + s2mm_dma_interr_set_minus_frame_errors : out STD_LOGIC; + \DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_reg\ : out STD_LOGIC; + \s_axis_cmd_tdata_reg[63]\ : out STD_LOGIC_VECTOR ( 48 downto 0 ); + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_fsize_less_err_flag_10_reg\ : out STD_LOGIC; + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF.flag_to_repeat_after_fsize_less_err_reg\ : out STD_LOGIC; + \S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg\ : out STD_LOGIC; + prmry_reset2 : in STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_s2mm_aclk : in STD_LOGIC; + s2mm_fsync_out_m_i : in STD_LOGIC; + zero_hsize_err0 : in STD_LOGIC; + zero_vsize_err0 : in STD_LOGIC; + drop_fsync_d_pulse_gen_fsize_less_err : in STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg\ : in STD_LOGIC; + O : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \stride_vid_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \stride_vid_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \stride_vid_reg[15]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s2mm_cdc2dmac_fsync : in STD_LOGIC; + s2mm_stop : in STD_LOGIC; + run_stop_d1 : in STD_LOGIC; + s2mm_dmacr : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s2mm_soft_reset : in STD_LOGIC; + soft_reset_d1 : in STD_LOGIC; + prmry_resetn_i_reg : in STD_LOGIC; + s2mm_tstvect_fsync : in STD_LOGIC; + ch2_delay_cnt_en : in STD_LOGIC; + s2mm_packet_sof : in STD_LOGIC; + ch2_irqthresh_decr_mask_sig : in STD_LOGIC; + s2mm_halt : in STD_LOGIC; + \out\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][30]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][29]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][28]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][27]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][26]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][25]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][24]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][23]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][22]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][21]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][20]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][19]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][18]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][17]\ : in STD_LOGIC; + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][16]\ : in STD_LOGIC; + s_axis_cmd_tvalid_reg_0 : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 12 downto 0 ); + datamover_idle : in STD_LOGIC; + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + flag_to_repeat_after_fsize_less_err : in STD_LOGIC; + \GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + halt_i_reg : in STD_LOGIC; + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\ : in STD_LOGIC; + dma_err : in STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axis_s2mm_sts_tready : in STD_LOGIC; + interr_i_reg : in STD_LOGIC; + \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[4]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + valid_frame_sync_d2 : in STD_LOGIC; + CO : in STD_LOGIC_VECTOR ( 0 to 0 ); + s2mm_fsize_less_err_flag_10 : in STD_LOGIC; + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : in STD_LOGIC; + \sig_user_reg_out_reg[0]\ : in STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + s2mm_axi2ip_wrce : in STD_LOGIC_VECTOR ( 0 to 0 ); + \S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg_0\ : in STD_LOGIC; + \hsize_vid_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + err_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_axi_vdma_sm__parameterized0\ : entity is "axi_vdma_sm"; +end \Arty_Z7_20_axi_vdma_0_0_axi_vdma_sm__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_axi_vdma_sm__parameterized0\ is + signal \FSM_sequential_dmacntrl_cs[2]_i_5__0_n_0\ : STD_LOGIC; + signal \FSM_sequential_dmacntrl_cs[2]_i_6__0_n_0\ : STD_LOGIC; + signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_17\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_18\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_19\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_20\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_21\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_22\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_23\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_24\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_25\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_26\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_27\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_28\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_29\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_30\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_31\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_32\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_33\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_34\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_35\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_36\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_37\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_38\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_39\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_40\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_41\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_42\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_43\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_44\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_45\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_47\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_48\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_49\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_7\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\ : STD_LOGIC; + signal \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_i_1_n_0\ : STD_LOGIC; + signal \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_cnt_en_reg\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data[23]_i_1__0_n_0\ : STD_LOGIC; + signal \^gen_normal_dm_command.cmnd_data_reg[47]_0\ : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[0]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[10]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[11]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[12]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[13]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[14]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[15]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[1]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[23]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[2]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[32]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[33]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[34]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[35]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[36]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[37]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[38]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[39]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[3]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[40]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[41]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[42]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[43]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[44]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[45]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[46]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[47]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[48]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[49]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[4]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[50]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[51]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[52]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[53]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[54]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[55]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[56]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[57]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[58]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[59]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[5]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[60]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[61]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[62]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[63]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[6]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[7]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[8]\ : STD_LOGIC; + signal \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[9]\ : STD_LOGIC; + signal \cmnds_queued[0]_i_1__0_n_0\ : STD_LOGIC; + signal \cmnds_queued[4]_i_2__0_n_0\ : STD_LOGIC; + signal \cmnds_queued[4]_i_3__0_n_0\ : STD_LOGIC; + signal \cmnds_queued[4]_i_4__0_n_0\ : STD_LOGIC; + signal \cmnds_queued[4]_i_5__0_n_0\ : STD_LOGIC; + signal \cmnds_queued[4]_i_6__0_n_0\ : STD_LOGIC; + signal \cmnds_queued[7]_i_2__0_n_0\ : STD_LOGIC; + signal \cmnds_queued[7]_i_4__0_n_0\ : STD_LOGIC; + signal \cmnds_queued[7]_i_5__0_n_0\ : STD_LOGIC; + signal \cmnds_queued[7]_i_6__0_n_0\ : STD_LOGIC; + signal cmnds_queued_reg : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \cmnds_queued_reg[4]_i_1__0_n_0\ : STD_LOGIC; + signal \cmnds_queued_reg[4]_i_1__0_n_1\ : STD_LOGIC; + signal \cmnds_queued_reg[4]_i_1__0_n_2\ : STD_LOGIC; + signal \cmnds_queued_reg[4]_i_1__0_n_3\ : STD_LOGIC; + signal \cmnds_queued_reg[4]_i_1__0_n_4\ : STD_LOGIC; + signal \cmnds_queued_reg[4]_i_1__0_n_5\ : STD_LOGIC; + signal \cmnds_queued_reg[4]_i_1__0_n_6\ : STD_LOGIC; + signal \cmnds_queued_reg[4]_i_1__0_n_7\ : STD_LOGIC; + signal \cmnds_queued_reg[7]_i_3__0_n_2\ : STD_LOGIC; + signal \cmnds_queued_reg[7]_i_3__0_n_3\ : STD_LOGIC; + signal \cmnds_queued_reg[7]_i_3__0_n_5\ : STD_LOGIC; + signal \cmnds_queued_reg[7]_i_3__0_n_6\ : STD_LOGIC; + signal \cmnds_queued_reg[7]_i_3__0_n_7\ : STD_LOGIC; + signal dm_address_reg : STD_LOGIC_VECTOR ( 31 downto 16 ); + signal dmacntrl_cs : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute RTL_KEEP : string; + attribute RTL_KEEP of dmacntrl_cs : signal is "yes"; + signal \^drop_fsync_d_pulse_gen_fsize_less_err_d1\ : STD_LOGIC; + signal frame_sync_d3 : STD_LOGIC; + signal frame_sync_reg : STD_LOGIC; + signal fsize_mismatch_err_flag_int : STD_LOGIC; + signal \^fsize_mismatch_err_s1\ : STD_LOGIC; + signal s2mm_fsync_out_m_d1 : STD_LOGIC; + signal \^s_axis_cmd_tvalid_reg\ : STD_LOGIC; + signal \^tstvect_fsync_d1\ : STD_LOGIC; + signal \^tstvect_fsync_d2\ : STD_LOGIC; + signal vert_count_reg : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal write_cmnd_cmb : STD_LOGIC; + signal \^zero_hsize_err\ : STD_LOGIC; + signal \^zero_vsize_err\ : STD_LOGIC; + signal \NLW_cmnds_queued_reg[7]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_cmnds_queued_reg[7]_i_3__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute KEEP : string; + attribute KEEP of \FSM_sequential_dmacntrl_cs_reg[0]\ : label is "yes"; + attribute KEEP of \FSM_sequential_dmacntrl_cs_reg[1]\ : label is "yes"; + attribute KEEP of \FSM_sequential_dmacntrl_cs_reg[2]\ : label is "yes"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \GEN_NORMAL_DM_COMMAND.cmnd_data[23]_i_1__0\ : label is "soft_lutpair51"; + attribute METHODOLOGY_DRC_VIOS : string; + attribute METHODOLOGY_DRC_VIOS of \cmnds_queued_reg[4]_i_1__0\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \cmnds_queued_reg[7]_i_3__0\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[0]_i_1__0\ : label is "soft_lutpair75"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[10]_i_1__0\ : label is "soft_lutpair70"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[11]_i_1__0\ : label is "soft_lutpair70"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[12]_i_1__0\ : label is "soft_lutpair69"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[13]_i_1__0\ : label is "soft_lutpair69"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[14]_i_1__0\ : label is "soft_lutpair68"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[15]_i_1__0\ : label is "soft_lutpair68"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[1]_i_1__0\ : label is "soft_lutpair75"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[23]_i_1__0\ : label is "soft_lutpair51"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[2]_i_1__0\ : label is "soft_lutpair74"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[32]_i_1__0\ : label is "soft_lutpair67"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[33]_i_1__0\ : label is "soft_lutpair67"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[34]_i_1__0\ : label is "soft_lutpair66"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[35]_i_1__0\ : label is "soft_lutpair66"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[36]_i_1__0\ : label is "soft_lutpair65"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[37]_i_1__0\ : label is "soft_lutpair65"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[38]_i_1__0\ : label is "soft_lutpair64"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[39]_i_1__0\ : label is "soft_lutpair64"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[3]_i_1__0\ : label is "soft_lutpair74"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[40]_i_1__0\ : label is "soft_lutpair63"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[41]_i_1__0\ : label is "soft_lutpair63"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[42]_i_1__0\ : label is "soft_lutpair62"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[43]_i_1__0\ : label is "soft_lutpair62"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[44]_i_1__0\ : label is "soft_lutpair61"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[45]_i_1__0\ : label is "soft_lutpair61"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[46]_i_1__0\ : label is "soft_lutpair60"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[47]_i_1__0\ : label is "soft_lutpair60"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[48]_i_1__0\ : label is "soft_lutpair59"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[49]_i_1__0\ : label is "soft_lutpair59"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[4]_i_1__0\ : label is "soft_lutpair73"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[50]_i_1__0\ : label is "soft_lutpair58"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[51]_i_1__0\ : label is "soft_lutpair58"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[52]_i_1__0\ : label is "soft_lutpair57"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[53]_i_1__0\ : label is "soft_lutpair57"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[54]_i_1__0\ : label is "soft_lutpair56"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[55]_i_1__0\ : label is "soft_lutpair56"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[56]_i_1__0\ : label is "soft_lutpair55"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[57]_i_1__0\ : label is "soft_lutpair55"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[58]_i_1__0\ : label is "soft_lutpair54"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[59]_i_1__0\ : label is "soft_lutpair54"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[5]_i_1__0\ : label is "soft_lutpair73"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[60]_i_1__0\ : label is "soft_lutpair52"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[61]_i_1__0\ : label is "soft_lutpair53"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[62]_i_1__0\ : label is "soft_lutpair53"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[63]_i_3__0\ : label is "soft_lutpair52"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[6]_i_1__0\ : label is "soft_lutpair72"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[7]_i_1__0\ : label is "soft_lutpair72"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[8]_i_1__0\ : label is "soft_lutpair71"; + attribute SOFT_HLUTNM of \s_axis_cmd_tdata[9]_i_1__0\ : label is "soft_lutpair71"; +begin + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg\ <= \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_cnt_en_reg\; + \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0\(15 downto 0) <= \^gen_normal_dm_command.cmnd_data_reg[47]_0\(15 downto 0); + drop_fsync_d_pulse_gen_fsize_less_err_d1 <= \^drop_fsync_d_pulse_gen_fsize_less_err_d1\; + fsize_mismatch_err_s1 <= \^fsize_mismatch_err_s1\; + s_axis_cmd_tvalid_reg <= \^s_axis_cmd_tvalid_reg\; + tstvect_fsync_d1 <= \^tstvect_fsync_d1\; + tstvect_fsync_d2 <= \^tstvect_fsync_d2\; + zero_hsize_err <= \^zero_hsize_err\; + zero_vsize_err <= \^zero_vsize_err\; +\FSM_sequential_dmacntrl_cs[2]_i_5__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => vert_count_reg(1), + I1 => vert_count_reg(0), + I2 => vert_count_reg(9), + I3 => vert_count_reg(2), + O => \FSM_sequential_dmacntrl_cs[2]_i_5__0_n_0\ + ); +\FSM_sequential_dmacntrl_cs[2]_i_6__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000001" + ) + port map ( + I0 => vert_count_reg(11), + I1 => vert_count_reg(8), + I2 => vert_count_reg(3), + I3 => vert_count_reg(4), + I4 => vert_count_reg(5), + I5 => vert_count_reg(6), + O => \FSM_sequential_dmacntrl_cs[2]_i_6__0_n_0\ + ); +\FSM_sequential_dmacntrl_cs_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_47\, + Q => dmacntrl_cs(0), + R => SR(0) + ); +\FSM_sequential_dmacntrl_cs_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_48\, + Q => dmacntrl_cs(1), + R => SR(0) + ); +\FSM_sequential_dmacntrl_cs_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_49\, + Q => dmacntrl_cs(2), + R => SR(0) + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_3__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FEFEFFFE" + ) + port map ( + I0 => cmnds_queued_reg(1), + I1 => cmnds_queued_reg(4), + I2 => cmnds_queued_reg(2), + I3 => s2mm_dmacr(0), + I4 => halt_i_reg, + O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_3__0_n_0\ + ); +\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized24\ + port map ( + CO(0) => CO(0), + D(4 downto 0) => D(4 downto 0), + \DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_reg\ => \DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_reg\, + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(4 downto 0) => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(4 downto 0), + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF.flag_to_repeat_after_fsize_less_err_reg\ => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF.flag_to_repeat_after_fsize_less_err_reg\, + \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[4]\(3 downto 0) => \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[4]\(3 downto 0), + \FSM_sequential_dmacntrl_cs_reg[0]\ => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_47\, + \FSM_sequential_dmacntrl_cs_reg[1]\ => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_48\, + \FSM_sequential_dmacntrl_cs_reg[2]\ => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_49\, + \FSM_sequential_dmacntrl_cs_reg[2]_0\(2 downto 0) => dmacntrl_cs(2 downto 0), + \GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[4]\(4 downto 0) => \GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[4]\(4 downto 0), + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg\ => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_cnt_en_reg\, + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0\ => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0\, + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_irqthresh_decr_mask_sig_reg\ => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_irqthresh_decr_mask_sig_reg\, + \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[0]\ => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[63]\ => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\, + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\ => \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[0]\(0) => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[0]\(0), + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][16]\ => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][16]\, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][17]\ => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][17]\, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][18]\ => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][18]\, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][19]\ => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][19]\, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][20]\ => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][20]\, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][21]\ => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][21]\, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][22]\ => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][22]\, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][23]\ => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][23]\, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][24]\ => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][24]\, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][25]\ => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][25]\, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][26]\ => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][26]\, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][27]\ => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][27]\, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][28]\ => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][28]\, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][29]\ => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][29]\, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][30]\ => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][30]\, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\ => \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\, + O(3) => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_17\, + O(2) => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_18\, + O(1) => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_19\, + O(0) => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_20\, + Q(12 downto 0) => Q(12 downto 0), + SR(0) => SR(0), + ch2_delay_cnt_en => ch2_delay_cnt_en, + ch2_irqthresh_decr_mask_sig => ch2_irqthresh_decr_mask_sig, + \cmnds_queued_reg[1]\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_i_3__0_n_0\, + \cmnds_queued_reg[7]\(4 downto 2) => cmnds_queued_reg(7 downto 5), + \cmnds_queued_reg[7]\(1) => cmnds_queued_reg(3), + \cmnds_queued_reg[7]\(0) => cmnds_queued_reg(0), + datamover_idle => datamover_idle, + dm_address_reg(15 downto 0) => dm_address_reg(31 downto 16), + \dm_address_reg[19]\(3) => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_30\, + \dm_address_reg[19]\(2) => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_31\, + \dm_address_reg[19]\(1) => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_32\, + \dm_address_reg[19]\(0) => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_33\, + \dm_address_reg[23]\(3) => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_34\, + \dm_address_reg[23]\(2) => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_35\, + \dm_address_reg[23]\(1) => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_36\, + \dm_address_reg[23]\(0) => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_37\, + \dm_address_reg[27]\(3) => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_38\, + \dm_address_reg[27]\(2) => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_39\, + \dm_address_reg[27]\(1) => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_40\, + \dm_address_reg[27]\(0) => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_41\, + \dm_address_reg[31]\(3) => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_42\, + \dm_address_reg[31]\(2) => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_43\, + \dm_address_reg[31]\(1) => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_44\, + \dm_address_reg[31]\(0) => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_45\, + \dm_address_reg_0__s_port_]\ => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + dma_err => dma_err, + drop_fsync_d_pulse_gen_fsize_less_err_d1 => \^drop_fsync_d_pulse_gen_fsize_less_err_d1\, + flag_to_repeat_after_fsize_less_err => flag_to_repeat_after_fsize_less_err, + frame_sync_reg => frame_sync_reg, + fsize_mismatch_err_flag_int => fsize_mismatch_err_flag_int, + fsize_mismatch_err_s1 => \^fsize_mismatch_err_s1\, + halt_i0 => halt_i0, + halt_i_reg => halt_i_reg, + halted_set_i0 => halted_set_i0, + in0(2 downto 0) => dmacntrl_cs(2 downto 0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\ => \out\, + prmry_reset2 => prmry_reset2, + prmry_resetn_i_reg => prmry_resetn_i_reg, + run_stop_d1 => run_stop_d1, + s2mm_cdc2dmac_fsync => s2mm_cdc2dmac_fsync, + s2mm_dmacr(1 downto 0) => s2mm_dmacr(1 downto 0), + s2mm_fsync_out_m_i => s2mm_fsync_out_m_i, + s2mm_ftchcmdsts_idle => s2mm_ftchcmdsts_idle, + s2mm_halt => s2mm_halt, + s2mm_packet_sof => s2mm_packet_sof, + s2mm_soft_reset => s2mm_soft_reset, + s2mm_stop => s2mm_stop, + s2mm_tstvect_fsync => s2mm_tstvect_fsync, + s_axis_cmd_tvalid_reg => s_axis_cmd_tvalid_reg_0, + s_axis_s2mm_aclk => s_axis_s2mm_aclk, + soft_reset_d1 => soft_reset_d1, + valid_frame_sync_d2 => valid_frame_sync_d2, + vert_count_reg(12 downto 0) => vert_count_reg(12 downto 0), + \vert_count_reg[0]_0\ => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_7\, + \vert_count_reg[11]\(3) => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_25\, + \vert_count_reg[11]\(2) => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_26\, + \vert_count_reg[11]\(1) => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_27\, + \vert_count_reg[11]\(0) => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_28\, + \vert_count_reg[11]_0\ => \FSM_sequential_dmacntrl_cs[2]_i_6__0_n_0\, + \vert_count_reg[12]\(0) => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_29\, + \vert_count_reg[7]\(3) => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_21\, + \vert_count_reg[7]\(2) => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_22\, + \vert_count_reg[7]\(1) => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_23\, + \vert_count_reg[7]\(0) => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_24\, + \vert_count_reg_0__s_port_]\ => load_new_addr, + \vert_count_reg_1__s_port_\ => \FSM_sequential_dmacntrl_cs[2]_i_5__0_n_0\, + write_cmnd_cmb => write_cmnd_cmb + ); +\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.drop_fsync_d_pulse_gen_fsize_less_err_d1_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => drop_fsync_d_pulse_gen_fsize_less_err, + Q => \^drop_fsync_d_pulse_gen_fsize_less_err_d1\, + R => prmry_reset2 + ); +\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00E0" + ) + port map ( + I0 => fsize_mismatch_err_flag_int, + I1 => \^gen_include_s2mm.gen_ch2_delay_interrupt.ch2_delay_cnt_en_reg\, + I2 => \out\, + I3 => s2mm_fsync_out_m_d1, + O => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_i_1_n_0\ + ); +\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_i_1_n_0\, + Q => fsize_mismatch_err_flag_int, + R => '0' + ); +\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_s1_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg\, + Q => \^fsize_mismatch_err_s1\, + R => prmry_reset2 + ); +\GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.s2mm_fsync_out_m_d1_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s2mm_fsync_out_m_i, + Q => s2mm_fsync_out_m_d1, + R => SR(0) + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data[23]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \out\, + I1 => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + I2 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[23]\, + O => \GEN_NORMAL_DM_COMMAND.cmnd_data[23]_i_1__0_n_0\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \hsize_vid_reg[15]\(0), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[0]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \hsize_vid_reg[15]\(10), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[10]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \hsize_vid_reg[15]\(11), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[11]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \hsize_vid_reg[15]\(12), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[12]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \hsize_vid_reg[15]\(13), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[13]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \hsize_vid_reg[15]\(14), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[14]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \hsize_vid_reg[15]\(15), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[15]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \hsize_vid_reg[15]\(1), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[1]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_NORMAL_DM_COMMAND.cmnd_data[23]_i_1__0_n_0\, + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[23]\, + R => '0' + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \hsize_vid_reg[15]\(2), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[2]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[32]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(0), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[32]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[33]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(1), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[33]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[34]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(2), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[34]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[35]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(3), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[35]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[36]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(4), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[36]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[37]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(5), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[37]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[38]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(6), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[38]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[39]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(7), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[39]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \hsize_vid_reg[15]\(3), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[3]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[40]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(8), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[40]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[41]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(9), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[41]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[42]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(10), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[42]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[43]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(11), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[43]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[44]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(12), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[44]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[45]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(13), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[45]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[46]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(14), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[46]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(15), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[47]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[48]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => dm_address_reg(16), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[48]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[49]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => dm_address_reg(17), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[49]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \hsize_vid_reg[15]\(4), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[4]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[50]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => dm_address_reg(18), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[50]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[51]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => dm_address_reg(19), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[51]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[52]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => dm_address_reg(20), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[52]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[53]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => dm_address_reg(21), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[53]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[54]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => dm_address_reg(22), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[54]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[55]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => dm_address_reg(23), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[55]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[56]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => dm_address_reg(24), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[56]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[57]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => dm_address_reg(25), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[57]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[58]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => dm_address_reg(26), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[58]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[59]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => dm_address_reg(27), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[59]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \hsize_vid_reg[15]\(5), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[5]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[60]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => dm_address_reg(28), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[60]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[61]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => dm_address_reg(29), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[61]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[62]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => dm_address_reg(30), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[62]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[63]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => dm_address_reg(31), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[63]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \hsize_vid_reg[15]\(6), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[6]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \hsize_vid_reg[15]\(7), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[7]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \hsize_vid_reg[15]\(8), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[8]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_data_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_8\, + D => \hsize_vid_reg[15]\(9), + Q => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[9]\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_46\ + ); +\GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => write_cmnd_cmb, + Q => \^s_axis_cmd_tvalid_reg\, + R => SR(0) + ); +\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_fsize_less_err_flag_10_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE000000" + ) + port map ( + I0 => s2mm_fsize_less_err_flag_10, + I1 => \^fsize_mismatch_err_s1\, + I2 => \^drop_fsync_d_pulse_gen_fsize_less_err_d1\, + I3 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\, + I4 => \sig_user_reg_out_reg[0]\, + O => \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_fsize_less_err_flag_10_reg\ + ); +\I_DMA_REGISTER/S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFF7FFFFFFF0" + ) + port map ( + I0 => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4]\(0), + I1 => s2mm_axi2ip_wrce(0), + I2 => interr_i_reg, + I3 => \^zero_vsize_err\, + I4 => \^zero_hsize_err\, + I5 => \S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg_0\, + O => \S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg\ + ); +\cmnds_queued[0]_i_1__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cmnds_queued_reg(0), + O => \cmnds_queued[0]_i_1__0_n_0\ + ); +\cmnds_queued[4]_i_2__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cmnds_queued_reg(1), + O => \cmnds_queued[4]_i_2__0_n_0\ + ); +\cmnds_queued[4]_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => cmnds_queued_reg(3), + I1 => cmnds_queued_reg(4), + O => \cmnds_queued[4]_i_3__0_n_0\ + ); +\cmnds_queued[4]_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => cmnds_queued_reg(2), + I1 => cmnds_queued_reg(3), + O => \cmnds_queued[4]_i_4__0_n_0\ + ); +\cmnds_queued[4]_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => cmnds_queued_reg(1), + I1 => cmnds_queued_reg(2), + O => \cmnds_queued[4]_i_5__0_n_0\ + ); +\cmnds_queued[4]_i_6__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"A655" + ) + port map ( + I0 => cmnds_queued_reg(1), + I1 => m_axis_s2mm_sts_tready, + I2 => \INFERRED_GEN.cnt_i_reg[2]\(0), + I3 => \^s_axis_cmd_tvalid_reg\, + O => \cmnds_queued[4]_i_6__0_n_0\ + ); +\cmnds_queued[7]_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"9A" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \INFERRED_GEN.cnt_i_reg[2]\(0), + I2 => m_axis_s2mm_sts_tready, + O => \cmnds_queued[7]_i_2__0_n_0\ + ); +\cmnds_queued[7]_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => cmnds_queued_reg(6), + I1 => cmnds_queued_reg(7), + O => \cmnds_queued[7]_i_4__0_n_0\ + ); +\cmnds_queued[7]_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => cmnds_queued_reg(5), + I1 => cmnds_queued_reg(6), + O => \cmnds_queued[7]_i_5__0_n_0\ + ); +\cmnds_queued[7]_i_6__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => cmnds_queued_reg(4), + I1 => cmnds_queued_reg(5), + O => \cmnds_queued[7]_i_6__0_n_0\ + ); +\cmnds_queued_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \cmnds_queued[7]_i_2__0_n_0\, + D => \cmnds_queued[0]_i_1__0_n_0\, + Q => cmnds_queued_reg(0), + R => err_i_reg(0) + ); +\cmnds_queued_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \cmnds_queued[7]_i_2__0_n_0\, + D => \cmnds_queued_reg[4]_i_1__0_n_7\, + Q => cmnds_queued_reg(1), + R => err_i_reg(0) + ); +\cmnds_queued_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \cmnds_queued[7]_i_2__0_n_0\, + D => \cmnds_queued_reg[4]_i_1__0_n_6\, + Q => cmnds_queued_reg(2), + R => err_i_reg(0) + ); +\cmnds_queued_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \cmnds_queued[7]_i_2__0_n_0\, + D => \cmnds_queued_reg[4]_i_1__0_n_5\, + Q => cmnds_queued_reg(3), + R => err_i_reg(0) + ); +\cmnds_queued_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \cmnds_queued[7]_i_2__0_n_0\, + D => \cmnds_queued_reg[4]_i_1__0_n_4\, + Q => cmnds_queued_reg(4), + R => err_i_reg(0) + ); +\cmnds_queued_reg[4]_i_1__0\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \cmnds_queued_reg[4]_i_1__0_n_0\, + CO(2) => \cmnds_queued_reg[4]_i_1__0_n_1\, + CO(1) => \cmnds_queued_reg[4]_i_1__0_n_2\, + CO(0) => \cmnds_queued_reg[4]_i_1__0_n_3\, + CYINIT => cmnds_queued_reg(0), + DI(3 downto 1) => cmnds_queued_reg(3 downto 1), + DI(0) => \cmnds_queued[4]_i_2__0_n_0\, + O(3) => \cmnds_queued_reg[4]_i_1__0_n_4\, + O(2) => \cmnds_queued_reg[4]_i_1__0_n_5\, + O(1) => \cmnds_queued_reg[4]_i_1__0_n_6\, + O(0) => \cmnds_queued_reg[4]_i_1__0_n_7\, + S(3) => \cmnds_queued[4]_i_3__0_n_0\, + S(2) => \cmnds_queued[4]_i_4__0_n_0\, + S(1) => \cmnds_queued[4]_i_5__0_n_0\, + S(0) => \cmnds_queued[4]_i_6__0_n_0\ + ); +\cmnds_queued_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \cmnds_queued[7]_i_2__0_n_0\, + D => \cmnds_queued_reg[7]_i_3__0_n_7\, + Q => cmnds_queued_reg(5), + R => err_i_reg(0) + ); +\cmnds_queued_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \cmnds_queued[7]_i_2__0_n_0\, + D => \cmnds_queued_reg[7]_i_3__0_n_6\, + Q => cmnds_queued_reg(6), + R => err_i_reg(0) + ); +\cmnds_queued_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \cmnds_queued[7]_i_2__0_n_0\, + D => \cmnds_queued_reg[7]_i_3__0_n_5\, + Q => cmnds_queued_reg(7), + R => err_i_reg(0) + ); +\cmnds_queued_reg[7]_i_3__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \cmnds_queued_reg[4]_i_1__0_n_0\, + CO(3 downto 2) => \NLW_cmnds_queued_reg[7]_i_3__0_CO_UNCONNECTED\(3 downto 2), + CO(1) => \cmnds_queued_reg[7]_i_3__0_n_2\, + CO(0) => \cmnds_queued_reg[7]_i_3__0_n_3\, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1 downto 0) => cmnds_queued_reg(5 downto 4), + O(3) => \NLW_cmnds_queued_reg[7]_i_3__0_O_UNCONNECTED\(3), + O(2) => \cmnds_queued_reg[7]_i_3__0_n_5\, + O(1) => \cmnds_queued_reg[7]_i_3__0_n_6\, + O(0) => \cmnds_queued_reg[7]_i_3__0_n_7\, + S(3) => '0', + S(2) => \cmnds_queued[7]_i_4__0_n_0\, + S(1) => \cmnds_queued[7]_i_5__0_n_0\, + S(0) => \cmnds_queued[7]_i_6__0_n_0\ + ); +\dm_address_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => O(0), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(0), + R => SR(0) + ); +\dm_address_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => \stride_vid_reg[11]\(2), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(10), + R => SR(0) + ); +\dm_address_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => \stride_vid_reg[11]\(3), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(11), + R => SR(0) + ); +\dm_address_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => \stride_vid_reg[15]\(0), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(12), + R => SR(0) + ); +\dm_address_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => \stride_vid_reg[15]\(1), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(13), + R => SR(0) + ); +\dm_address_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => \stride_vid_reg[15]\(2), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(14), + R => SR(0) + ); +\dm_address_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => \stride_vid_reg[15]\(3), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(15), + R => SR(0) + ); +\dm_address_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_33\, + Q => dm_address_reg(16), + R => SR(0) + ); +\dm_address_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_32\, + Q => dm_address_reg(17), + R => SR(0) + ); +\dm_address_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_31\, + Q => dm_address_reg(18), + R => SR(0) + ); +\dm_address_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_30\, + Q => dm_address_reg(19), + R => SR(0) + ); +\dm_address_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => O(1), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(1), + R => SR(0) + ); +\dm_address_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_37\, + Q => dm_address_reg(20), + R => SR(0) + ); +\dm_address_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_36\, + Q => dm_address_reg(21), + R => SR(0) + ); +\dm_address_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_35\, + Q => dm_address_reg(22), + R => SR(0) + ); +\dm_address_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_34\, + Q => dm_address_reg(23), + R => SR(0) + ); +\dm_address_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_41\, + Q => dm_address_reg(24), + R => SR(0) + ); +\dm_address_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_40\, + Q => dm_address_reg(25), + R => SR(0) + ); +\dm_address_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_39\, + Q => dm_address_reg(26), + R => SR(0) + ); +\dm_address_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_38\, + Q => dm_address_reg(27), + R => SR(0) + ); +\dm_address_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_45\, + Q => dm_address_reg(28), + R => SR(0) + ); +\dm_address_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_44\, + Q => dm_address_reg(29), + R => SR(0) + ); +\dm_address_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => O(2), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(2), + R => SR(0) + ); +\dm_address_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_43\, + Q => dm_address_reg(30), + R => SR(0) + ); +\dm_address_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_42\, + Q => dm_address_reg(31), + R => SR(0) + ); +\dm_address_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => O(3), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(3), + R => SR(0) + ); +\dm_address_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => \stride_vid_reg[7]\(0), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(4), + R => SR(0) + ); +\dm_address_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => \stride_vid_reg[7]\(1), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(5), + R => SR(0) + ); +\dm_address_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => \stride_vid_reg[7]\(2), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(6), + R => SR(0) + ); +\dm_address_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => \stride_vid_reg[7]\(3), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(7), + R => SR(0) + ); +\dm_address_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => \stride_vid_reg[11]\(0), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(8), + R => SR(0) + ); +\dm_address_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_5\, + D => \stride_vid_reg[11]\(1), + Q => \^gen_normal_dm_command.cmnd_data_reg[47]_0\(9), + R => SR(0) + ); +dma_interr_i_3: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => interr_i_reg, + I1 => \^zero_vsize_err\, + I2 => \^zero_hsize_err\, + O => s2mm_dma_interr_set_minus_frame_errors + ); +frame_sync_d1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s2mm_cdc2dmac_fsync, + Q => \^tstvect_fsync_d1\, + R => SR(0) + ); +frame_sync_d2_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \^tstvect_fsync_d1\, + Q => \^tstvect_fsync_d2\, + R => SR(0) + ); +frame_sync_d3_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \^tstvect_fsync_d2\, + Q => frame_sync_d3, + R => SR(0) + ); +frame_sync_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => frame_sync_d3, + Q => frame_sync_reg, + R => SR(0) + ); +\s_axis_cmd_tdata[0]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[0]\, + O => \s_axis_cmd_tdata_reg[63]\(0) + ); +\s_axis_cmd_tdata[10]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[10]\, + O => \s_axis_cmd_tdata_reg[63]\(10) + ); +\s_axis_cmd_tdata[11]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[11]\, + O => \s_axis_cmd_tdata_reg[63]\(11) + ); +\s_axis_cmd_tdata[12]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[12]\, + O => \s_axis_cmd_tdata_reg[63]\(12) + ); +\s_axis_cmd_tdata[13]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[13]\, + O => \s_axis_cmd_tdata_reg[63]\(13) + ); +\s_axis_cmd_tdata[14]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[14]\, + O => \s_axis_cmd_tdata_reg[63]\(14) + ); +\s_axis_cmd_tdata[15]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[15]\, + O => \s_axis_cmd_tdata_reg[63]\(15) + ); +\s_axis_cmd_tdata[1]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[1]\, + O => \s_axis_cmd_tdata_reg[63]\(1) + ); +\s_axis_cmd_tdata[23]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[23]\, + O => \s_axis_cmd_tdata_reg[63]\(16) + ); +\s_axis_cmd_tdata[2]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[2]\, + O => \s_axis_cmd_tdata_reg[63]\(2) + ); +\s_axis_cmd_tdata[32]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[32]\, + O => \s_axis_cmd_tdata_reg[63]\(17) + ); +\s_axis_cmd_tdata[33]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[33]\, + O => \s_axis_cmd_tdata_reg[63]\(18) + ); +\s_axis_cmd_tdata[34]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[34]\, + O => \s_axis_cmd_tdata_reg[63]\(19) + ); +\s_axis_cmd_tdata[35]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[35]\, + O => \s_axis_cmd_tdata_reg[63]\(20) + ); +\s_axis_cmd_tdata[36]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[36]\, + O => \s_axis_cmd_tdata_reg[63]\(21) + ); +\s_axis_cmd_tdata[37]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[37]\, + O => \s_axis_cmd_tdata_reg[63]\(22) + ); +\s_axis_cmd_tdata[38]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[38]\, + O => \s_axis_cmd_tdata_reg[63]\(23) + ); +\s_axis_cmd_tdata[39]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[39]\, + O => \s_axis_cmd_tdata_reg[63]\(24) + ); +\s_axis_cmd_tdata[3]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[3]\, + O => \s_axis_cmd_tdata_reg[63]\(3) + ); +\s_axis_cmd_tdata[40]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[40]\, + O => \s_axis_cmd_tdata_reg[63]\(25) + ); +\s_axis_cmd_tdata[41]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[41]\, + O => \s_axis_cmd_tdata_reg[63]\(26) + ); +\s_axis_cmd_tdata[42]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[42]\, + O => \s_axis_cmd_tdata_reg[63]\(27) + ); +\s_axis_cmd_tdata[43]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[43]\, + O => \s_axis_cmd_tdata_reg[63]\(28) + ); +\s_axis_cmd_tdata[44]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[44]\, + O => \s_axis_cmd_tdata_reg[63]\(29) + ); +\s_axis_cmd_tdata[45]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[45]\, + O => \s_axis_cmd_tdata_reg[63]\(30) + ); +\s_axis_cmd_tdata[46]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[46]\, + O => \s_axis_cmd_tdata_reg[63]\(31) + ); +\s_axis_cmd_tdata[47]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[47]\, + O => \s_axis_cmd_tdata_reg[63]\(32) + ); +\s_axis_cmd_tdata[48]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[48]\, + O => \s_axis_cmd_tdata_reg[63]\(33) + ); +\s_axis_cmd_tdata[49]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[49]\, + O => \s_axis_cmd_tdata_reg[63]\(34) + ); +\s_axis_cmd_tdata[4]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[4]\, + O => \s_axis_cmd_tdata_reg[63]\(4) + ); +\s_axis_cmd_tdata[50]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[50]\, + O => \s_axis_cmd_tdata_reg[63]\(35) + ); +\s_axis_cmd_tdata[51]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[51]\, + O => \s_axis_cmd_tdata_reg[63]\(36) + ); +\s_axis_cmd_tdata[52]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[52]\, + O => \s_axis_cmd_tdata_reg[63]\(37) + ); +\s_axis_cmd_tdata[53]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[53]\, + O => \s_axis_cmd_tdata_reg[63]\(38) + ); +\s_axis_cmd_tdata[54]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[54]\, + O => \s_axis_cmd_tdata_reg[63]\(39) + ); +\s_axis_cmd_tdata[55]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[55]\, + O => \s_axis_cmd_tdata_reg[63]\(40) + ); +\s_axis_cmd_tdata[56]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[56]\, + O => \s_axis_cmd_tdata_reg[63]\(41) + ); +\s_axis_cmd_tdata[57]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[57]\, + O => \s_axis_cmd_tdata_reg[63]\(42) + ); +\s_axis_cmd_tdata[58]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[58]\, + O => \s_axis_cmd_tdata_reg[63]\(43) + ); +\s_axis_cmd_tdata[59]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[59]\, + O => \s_axis_cmd_tdata_reg[63]\(44) + ); +\s_axis_cmd_tdata[5]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[5]\, + O => \s_axis_cmd_tdata_reg[63]\(5) + ); +\s_axis_cmd_tdata[60]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[60]\, + O => \s_axis_cmd_tdata_reg[63]\(45) + ); +\s_axis_cmd_tdata[61]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[61]\, + O => \s_axis_cmd_tdata_reg[63]\(46) + ); +\s_axis_cmd_tdata[62]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[62]\, + O => \s_axis_cmd_tdata_reg[63]\(47) + ); +\s_axis_cmd_tdata[63]_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[63]\, + O => \s_axis_cmd_tdata_reg[63]\(48) + ); +\s_axis_cmd_tdata[6]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[6]\, + O => \s_axis_cmd_tdata_reg[63]\(6) + ); +\s_axis_cmd_tdata[7]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[7]\, + O => \s_axis_cmd_tdata_reg[63]\(7) + ); +\s_axis_cmd_tdata[8]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[8]\, + O => \s_axis_cmd_tdata_reg[63]\(8) + ); +\s_axis_cmd_tdata[9]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^s_axis_cmd_tvalid_reg\, + I1 => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg_n_0_[9]\, + O => \s_axis_cmd_tdata_reg[63]\(9) + ); +\vert_count_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_7\, + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_20\, + Q => vert_count_reg(0), + R => SR(0) + ); +\vert_count_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_7\, + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_26\, + Q => vert_count_reg(10), + R => SR(0) + ); +\vert_count_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_7\, + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_25\, + Q => vert_count_reg(11), + R => SR(0) + ); +\vert_count_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_7\, + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_29\, + Q => vert_count_reg(12), + R => SR(0) + ); +\vert_count_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_7\, + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_19\, + Q => vert_count_reg(1), + R => SR(0) + ); +\vert_count_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_7\, + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_18\, + Q => vert_count_reg(2), + R => SR(0) + ); +\vert_count_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_7\, + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_17\, + Q => vert_count_reg(3), + R => SR(0) + ); +\vert_count_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_7\, + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_24\, + Q => vert_count_reg(4), + R => SR(0) + ); +\vert_count_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_7\, + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_23\, + Q => vert_count_reg(5), + R => SR(0) + ); +\vert_count_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_7\, + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_22\, + Q => vert_count_reg(6), + R => SR(0) + ); +\vert_count_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_7\, + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_21\, + Q => vert_count_reg(7), + R => SR(0) + ); +\vert_count_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_7\, + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_28\, + Q => vert_count_reg(8), + R => SR(0) + ); +\vert_count_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_7\, + D => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF_n_27\, + Q => vert_count_reg(9), + R => SR(0) + ); +zero_hsize_err_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => zero_hsize_err0, + Q => \^zero_hsize_err\, + R => SR(0) + ); +zero_vsize_err_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => zero_vsize_err0, + Q => \^zero_vsize_err\, + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_vid_cdc is + port ( + p_in_d1_cdc_from : out STD_LOGIC; + p_17_out : out STD_LOGIC; + p_in_d1_cdc_from_0 : out STD_LOGIC; + p_15_out : out STD_LOGIC; + all_lines_xfred : out STD_LOGIC; + mm2s_frame_ptr_out : out STD_LOGIC_VECTOR ( 5 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + prmry_in_xored : in STD_LOGIC; + m_axis_mm2s_aclk : in STD_LOGIC; + prmry_resetn_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + prmry_in_xored_1 : in STD_LOGIC; + \GENLOCK_FOR_MASTER.frame_ptr_out_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + mm2s_frame_ptr_in : in STD_LOGIC_VECTOR ( 5 downto 0 ); + \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_vid_cdc : entity is "axi_vdma_vid_cdc"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_vid_cdc; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_vid_cdc is + signal frame_ptr_in_d1_cdc_tig : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute async_reg : string; + attribute async_reg of frame_ptr_in_d1_cdc_tig : signal is "true"; + signal frame_ptr_in_d2 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute async_reg of frame_ptr_in_d2 : signal is "true"; + signal frame_ptr_out_d1_cdc_tig : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute async_reg of frame_ptr_out_d1_cdc_tig : signal is "true"; + signal frame_ptr_out_d2 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute async_reg of frame_ptr_out_d2 : signal is "true"; + signal othrchnl_frame_ptr_in_d1_cdc_tig : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute async_reg of othrchnl_frame_ptr_in_d1_cdc_tig : signal is "true"; + signal othrchnl_frame_ptr_in_d2 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute async_reg of othrchnl_frame_ptr_in_d2 : signal is "true"; + signal p_2_in : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[5]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[5]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[0]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[5]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[5]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[0]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[5]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[5]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[0]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[5]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[5]\ : label is "yes"; +begin + p_2_in(2 downto 0) <= \GENLOCK_FOR_MASTER.frame_ptr_out_reg[2]\(2 downto 0); +\GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized14_37\ + port map ( + \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]\ => \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]\, + SR(0) => SR(0), + all_lines_xfred => all_lines_xfred, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axis_mm2s_aclk => m_axis_mm2s_aclk, + p_15_out => p_15_out, + p_in_d1_cdc_from_0 => p_in_d1_cdc_from_0, + prmry_in_xored_1 => prmry_in_xored_1, + prmry_resetn_i_reg(0) => prmry_resetn_i_reg(0) + ); +\GEN_CDC_FOR_ASYNC.SOF_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized12_38\ + port map ( + SR(0) => SR(0), + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axis_mm2s_aclk => m_axis_mm2s_aclk, + p_17_out => p_17_out, + p_in_d1_cdc_from => p_in_d1_cdc_from, + prmry_in_xored => prmry_in_xored, + prmry_resetn_i_reg(0) => prmry_resetn_i_reg(0) + ); +\GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => frame_ptr_out_d2(0), + Q => mm2s_frame_ptr_out(0), + R => SR(0) + ); +\GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => frame_ptr_out_d2(1), + Q => mm2s_frame_ptr_out(1), + R => SR(0) + ); +\GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => frame_ptr_out_d2(2), + Q => mm2s_frame_ptr_out(2), + R => SR(0) + ); +\GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => frame_ptr_out_d2(3), + Q => mm2s_frame_ptr_out(3), + R => SR(0) + ); +\GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => frame_ptr_out_d2(4), + Q => mm2s_frame_ptr_out(4), + R => SR(0) + ); +\GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => frame_ptr_out_d2(5), + Q => mm2s_frame_ptr_out(5), + R => SR(0) + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => mm2s_frame_ptr_in(0), + Q => frame_ptr_in_d1_cdc_tig(0), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => mm2s_frame_ptr_in(1), + Q => frame_ptr_in_d1_cdc_tig(1), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => mm2s_frame_ptr_in(2), + Q => frame_ptr_in_d1_cdc_tig(2), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => mm2s_frame_ptr_in(3), + Q => frame_ptr_in_d1_cdc_tig(3), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => mm2s_frame_ptr_in(4), + Q => frame_ptr_in_d1_cdc_tig(4), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => mm2s_frame_ptr_in(5), + Q => frame_ptr_in_d1_cdc_tig(5), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => frame_ptr_in_d1_cdc_tig(0), + Q => frame_ptr_in_d2(0), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => frame_ptr_in_d1_cdc_tig(1), + Q => frame_ptr_in_d2(1), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => frame_ptr_in_d1_cdc_tig(2), + Q => frame_ptr_in_d2(2), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => frame_ptr_in_d1_cdc_tig(3), + Q => frame_ptr_in_d2(3), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => frame_ptr_in_d1_cdc_tig(4), + Q => frame_ptr_in_d2(4), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => frame_ptr_in_d1_cdc_tig(5), + Q => frame_ptr_in_d2(5), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => p_2_in(0), + Q => frame_ptr_out_d1_cdc_tig(0), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => p_2_in(1), + Q => frame_ptr_out_d1_cdc_tig(1), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => p_2_in(2), + Q => frame_ptr_out_d1_cdc_tig(2), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => p_2_in(3), + Q => frame_ptr_out_d1_cdc_tig(3), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => p_2_in(4), + Q => frame_ptr_out_d1_cdc_tig(4), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => p_2_in(5), + Q => frame_ptr_out_d1_cdc_tig(5), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => frame_ptr_out_d1_cdc_tig(0), + Q => frame_ptr_out_d2(0), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => frame_ptr_out_d1_cdc_tig(1), + Q => frame_ptr_out_d2(1), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => frame_ptr_out_d1_cdc_tig(2), + Q => frame_ptr_out_d2(2), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => frame_ptr_out_d1_cdc_tig(3), + Q => frame_ptr_out_d2(3), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => frame_ptr_out_d1_cdc_tig(4), + Q => frame_ptr_out_d2(4), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => frame_ptr_out_d1_cdc_tig(5), + Q => frame_ptr_out_d2(5), + R => '0' + ); +i_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => p_2_in(5) + ); +i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => p_2_in(4) + ); +i_10: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => othrchnl_frame_ptr_in_d2(4) + ); +i_11: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => othrchnl_frame_ptr_in_d2(3) + ); +i_12: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => othrchnl_frame_ptr_in_d2(2) + ); +i_13: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => othrchnl_frame_ptr_in_d2(1) + ); +i_14: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => othrchnl_frame_ptr_in_d2(0) + ); +i_2: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => p_2_in(3) + ); +i_3: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => othrchnl_frame_ptr_in_d1_cdc_tig(5) + ); +i_4: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => othrchnl_frame_ptr_in_d1_cdc_tig(4) + ); +i_5: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => othrchnl_frame_ptr_in_d1_cdc_tig(3) + ); +i_6: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => othrchnl_frame_ptr_in_d1_cdc_tig(2) + ); +i_7: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => othrchnl_frame_ptr_in_d1_cdc_tig(1) + ); +i_8: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => othrchnl_frame_ptr_in_d1_cdc_tig(0) + ); +i_9: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => othrchnl_frame_ptr_in_d2(5) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_vid_cdc_1 is + port ( + p_in_d1_cdc_from : out STD_LOGIC; + s2mm_packet_sof : out STD_LOGIC; + s2mm_cdc2dmac_fsync : out STD_LOGIC; + p_in_d1_cdc_from_0 : out STD_LOGIC; + s2mm_fsync_out_i : out STD_LOGIC; + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[0]\ : out STD_LOGIC; + prmry_in_xored : out STD_LOGIC; + s2mm_valid_frame_sync_cmb : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + s2mm_frame_ptr_out : out STD_LOGIC_VECTOR ( 5 downto 0 ); + \frame_ptr_out_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + prmry_reset2 : in STD_LOGIC; + prmry_in_xored_1 : in STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_s2mm_aclk : in STD_LOGIC; + prmry_in_xored_2 : in STD_LOGIC; + \DYNAMIC_GENLOCK_FOR_MASTER.frame_ptr_out_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s2mm_frame_ptr_in : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s2mm_fsync_core : in STD_LOGIC; + reset_counts : in STD_LOGIC; + irqdelay_wren_i : in STD_LOGIC; + p_in_d1_cdc_from_3 : in STD_LOGIC; + s2mm_valid_video_prmtrs : in STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\ : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : in STD_LOGIC; + M_Last : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_vid_cdc_1 : entity is "axi_vdma_vid_cdc"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_vid_cdc_1; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_vid_cdc_1 is + signal frame_ptr_in_d1_cdc_tig : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute async_reg : string; + attribute async_reg of frame_ptr_in_d1_cdc_tig : signal is "true"; + signal frame_ptr_in_d2 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute async_reg of frame_ptr_in_d2 : signal is "true"; + signal frame_ptr_out_d1_cdc_tig : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute async_reg of frame_ptr_out_d1_cdc_tig : signal is "true"; + signal frame_ptr_out_d2 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute async_reg of frame_ptr_out_d2 : signal is "true"; + signal othrchnl_frame_ptr_in_d1_cdc_tig : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute async_reg of othrchnl_frame_ptr_in_d1_cdc_tig : signal is "true"; + signal othrchnl_frame_ptr_in_d2 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute async_reg of othrchnl_frame_ptr_in_d2 : signal is "true"; + signal p_2_in : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \^s2mm_cdc2dmac_fsync\ : STD_LOGIC; + signal s_fsync_d1 : STD_LOGIC; + signal s_fsync_d2 : STD_LOGIC; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[5]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[5]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[0]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[5]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[5]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[0]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[5]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[5]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[0]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[5]\ : label is std.standard.true; + attribute KEEP of \GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[5]\ : label is "yes"; +begin + p_2_in(2 downto 0) <= \DYNAMIC_GENLOCK_FOR_MASTER.frame_ptr_out_reg[2]\(2 downto 0); + s2mm_cdc2dmac_fsync <= \^s2mm_cdc2dmac_fsync\; +\GEN_CDC_FOR_ASYNC.FSYNC_IN_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized13\ + port map ( + SR(0) => SR(0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + prmry_reset2 => prmry_reset2, + s2mm_cdc2dmac_fsync => \^s2mm_cdc2dmac_fsync\, + s2mm_valid_frame_sync_cmb => s2mm_valid_frame_sync_cmb, + s2mm_valid_video_prmtrs => s2mm_valid_video_prmtrs, + s_axis_s2mm_aclk => s_axis_s2mm_aclk, + s_fsync_d1 => s_fsync_d1, + s_fsync_d2 => s_fsync_d2 + ); +\GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized14\ + port map ( + E(0) => E(0), + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out_0\ => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\, + M_Last => M_Last, + Q(0) => Q(0), + SR(0) => SR(0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + p_in_d1_cdc_from_0 => p_in_d1_cdc_from_0, + p_in_d1_cdc_from_3 => p_in_d1_cdc_from_3, + prmry_in_xored => prmry_in_xored, + prmry_in_xored_2 => prmry_in_xored_2, + prmry_reset2 => prmry_reset2, + s2mm_fsync_out_i => s2mm_fsync_out_i, + s_axis_s2mm_aclk => s_axis_s2mm_aclk + ); +\GEN_CDC_FOR_ASYNC.SOF_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized12\ + port map ( + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[0]\ => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[0]\, + SR(0) => SR(0), + irqdelay_wren_i => irqdelay_wren_i, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + p_in_d1_cdc_from => p_in_d1_cdc_from, + prmry_in_xored_1 => prmry_in_xored_1, + prmry_reset2 => prmry_reset2, + reset_counts => reset_counts, + s2mm_cdc2dmac_fsync => \^s2mm_cdc2dmac_fsync\, + s2mm_packet_sof => s2mm_packet_sof, + s_axis_s2mm_aclk => s_axis_s2mm_aclk + ); +\GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => frame_ptr_in_d2(0), + Q => \frame_ptr_out_reg[2]\(0), + R => SR(0) + ); +\GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => frame_ptr_in_d2(1), + Q => \frame_ptr_out_reg[2]\(1), + R => SR(0) + ); +\GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => frame_ptr_in_d2(2), + Q => \frame_ptr_out_reg[2]\(2), + R => SR(0) + ); +\GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => frame_ptr_out_d2(0), + Q => s2mm_frame_ptr_out(0), + R => prmry_reset2 + ); +\GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => frame_ptr_out_d2(1), + Q => s2mm_frame_ptr_out(1), + R => prmry_reset2 + ); +\GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => frame_ptr_out_d2(2), + Q => s2mm_frame_ptr_out(2), + R => prmry_reset2 + ); +\GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => frame_ptr_out_d2(3), + Q => s2mm_frame_ptr_out(3), + R => prmry_reset2 + ); +\GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => frame_ptr_out_d2(4), + Q => s2mm_frame_ptr_out(4), + R => prmry_reset2 + ); +\GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => frame_ptr_out_d2(5), + Q => s2mm_frame_ptr_out(5), + R => prmry_reset2 + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s2mm_frame_ptr_in(0), + Q => frame_ptr_in_d1_cdc_tig(0), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s2mm_frame_ptr_in(1), + Q => frame_ptr_in_d1_cdc_tig(1), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s2mm_frame_ptr_in(2), + Q => frame_ptr_in_d1_cdc_tig(2), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s2mm_frame_ptr_in(3), + Q => frame_ptr_in_d1_cdc_tig(3), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s2mm_frame_ptr_in(4), + Q => frame_ptr_in_d1_cdc_tig(4), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_in_d1_cdc_tig_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s2mm_frame_ptr_in(5), + Q => frame_ptr_in_d1_cdc_tig(5), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => frame_ptr_in_d1_cdc_tig(0), + Q => frame_ptr_in_d2(0), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => frame_ptr_in_d1_cdc_tig(1), + Q => frame_ptr_in_d2(1), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => frame_ptr_in_d1_cdc_tig(2), + Q => frame_ptr_in_d2(2), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => frame_ptr_in_d1_cdc_tig(3), + Q => frame_ptr_in_d2(3), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => frame_ptr_in_d1_cdc_tig(4), + Q => frame_ptr_in_d2(4), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_in_d2_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => frame_ptr_in_d1_cdc_tig(5), + Q => frame_ptr_in_d2(5), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => p_2_in(0), + Q => frame_ptr_out_d1_cdc_tig(0), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => p_2_in(1), + Q => frame_ptr_out_d1_cdc_tig(1), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => p_2_in(2), + Q => frame_ptr_out_d1_cdc_tig(2), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => p_2_in(3), + Q => frame_ptr_out_d1_cdc_tig(3), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => p_2_in(4), + Q => frame_ptr_out_d1_cdc_tig(4), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => p_2_in(5), + Q => frame_ptr_out_d1_cdc_tig(5), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => frame_ptr_out_d1_cdc_tig(0), + Q => frame_ptr_out_d2(0), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => frame_ptr_out_d1_cdc_tig(1), + Q => frame_ptr_out_d2(1), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => frame_ptr_out_d1_cdc_tig(2), + Q => frame_ptr_out_d2(2), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => frame_ptr_out_d1_cdc_tig(3), + Q => frame_ptr_out_d2(3), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => frame_ptr_out_d1_cdc_tig(4), + Q => frame_ptr_out_d2(4), + R => '0' + ); +\GEN_CDC_FOR_ASYNC.frame_ptr_out_d2_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => frame_ptr_out_d1_cdc_tig(5), + Q => frame_ptr_out_d2(5), + R => '0' + ); +i_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => p_2_in(5) + ); +i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => p_2_in(4) + ); +i_10: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => othrchnl_frame_ptr_in_d2(4) + ); +i_11: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => othrchnl_frame_ptr_in_d2(3) + ); +i_12: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => othrchnl_frame_ptr_in_d2(2) + ); +i_13: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => othrchnl_frame_ptr_in_d2(1) + ); +i_14: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => othrchnl_frame_ptr_in_d2(0) + ); +i_2: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => p_2_in(3) + ); +i_3: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => othrchnl_frame_ptr_in_d1_cdc_tig(5) + ); +i_4: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => othrchnl_frame_ptr_in_d1_cdc_tig(4) + ); +i_5: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => othrchnl_frame_ptr_in_d1_cdc_tig(3) + ); +i_6: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => othrchnl_frame_ptr_in_d1_cdc_tig(2) + ); +i_7: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => othrchnl_frame_ptr_in_d1_cdc_tig(1) + ); +i_8: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => othrchnl_frame_ptr_in_d1_cdc_tig(0) + ); +i_9: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => othrchnl_frame_ptr_in_d2(5) + ); +s_fsync_d1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s2mm_fsync_core, + Q => s_fsync_d1, + R => prmry_reset2 + ); +s_fsync_d2_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => s_fsync_d1, + Q => s_fsync_d2, + R => prmry_reset2 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_vidreg_module is + port ( + prmtr_update_complete : out STD_LOGIC; + zero_hsize_err0 : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 15 downto 0 ); + zero_vsize_err0 : out STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); + p_26_out : out STD_LOGIC; + \stride_vid_reg[0]\ : out STD_LOGIC; + \dm_address_reg[19]\ : out STD_LOGIC; + \dm_address_reg[19]_0\ : out STD_LOGIC; + \dm_address_reg[19]_1\ : out STD_LOGIC; + \dm_address_reg[19]_2\ : out STD_LOGIC; + \dm_address_reg[23]\ : out STD_LOGIC; + \dm_address_reg[23]_0\ : out STD_LOGIC; + \dm_address_reg[23]_1\ : out STD_LOGIC; + \dm_address_reg[23]_2\ : out STD_LOGIC; + \dm_address_reg[27]\ : out STD_LOGIC; + \dm_address_reg[27]_0\ : out STD_LOGIC; + \dm_address_reg[27]_1\ : out STD_LOGIC; + \dm_address_reg[27]_2\ : out STD_LOGIC; + \dm_address_reg[31]\ : out STD_LOGIC; + \dm_address_reg[31]_0\ : out STD_LOGIC; + \dm_address_reg[31]_1\ : out STD_LOGIC; + \dm_address_reg[31]_2\ : out STD_LOGIC; + S : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_STS_GRTR_THAN_8.undrflo_err_reg\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + O : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \dm_address_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \dm_address_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + CO : out STD_LOGIC_VECTOR ( 0 to 0 ); + \dm_address_reg[15]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + p_2_out : out STD_LOGIC; + prmtr_updt_complete_i_reg : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + load_new_addr : in STD_LOGIC; + tstvect_fsync_d2 : in STD_LOGIC; + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axis_s2mm_sts_tdata : in STD_LOGIC_VECTOR ( 0 to 0 ); + s2mm_cdc2dmac_fsync : in STD_LOGIC; + \dm_address_reg[15]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + mask_fsync_out_i : in STD_LOGIC; + tstvect_fsync_d1 : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + \reg_module_vsize_reg[12]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + \reg_module_hsize_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \out\ : in STD_LOGIC; + s2mm_dmasr : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_vidreg_module : entity is "axi_vdma_vidreg_module"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_vidreg_module; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_vidreg_module is + signal \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_i_1__0_n_0\ : STD_LOGIC; + signal \^prmtr_update_complete\ : STD_LOGIC; + signal \^stride_vid_reg[0]\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \DYNAMIC_MASTER_MODE_FRAME_CNT.tstvect_fsync_i_1\ : label is "soft_lutpair81"; + attribute SOFT_HLUTNM of \GEN_FSYNC_MODE_S2MM_FLUSH_SOF.frame_sync_out_i_1\ : label is "soft_lutpair81"; +begin + prmtr_update_complete <= \^prmtr_update_complete\; + \stride_vid_reg[0]\ <= \^stride_vid_reg[0]\; +\DYNAMIC_MASTER_MODE_FRAME_CNT.tstvect_fsync_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^stride_vid_reg[0]\, + I1 => tstvect_fsync_d2, + O => p_26_out + ); +\GEN_FSYNC_MODE_S2MM_FLUSH_SOF.frame_sync_out_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"20" + ) + port map ( + I0 => \^stride_vid_reg[0]\, + I1 => mask_fsync_out_i, + I2 => tstvect_fsync_d1, + O => p_2_out + ); +\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.VIDREGISTER_I\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_vregister + port map ( + CO(0) => CO(0), + \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(15 downto 0) => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(15 downto 0), + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1 downto 0) => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1 downto 0), + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(31 downto 0) => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(31 downto 0), + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(31 downto 0) => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(31 downto 0), + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(31 downto 0) => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(31 downto 0), + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\ => \^stride_vid_reg[0]\, + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12]\(12 downto 0) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12]\(12 downto 0), + \GEN_STS_GRTR_THAN_8.undrflo_err_reg\(0) => \GEN_STS_GRTR_THAN_8.undrflo_err_reg\(0), + O(3 downto 0) => O(3 downto 0), + Q(15 downto 0) => Q(15 downto 0), + S(0) => S(0), + SR(0) => SR(0), + \dm_address_reg[11]\(3 downto 0) => \dm_address_reg[11]\(3 downto 0), + \dm_address_reg[15]\(3 downto 0) => \dm_address_reg[15]\(3 downto 0), + \dm_address_reg[15]_0\(15 downto 0) => \dm_address_reg[15]_0\(15 downto 0), + \dm_address_reg[19]\ => \dm_address_reg[19]\, + \dm_address_reg[19]_0\ => \dm_address_reg[19]_0\, + \dm_address_reg[19]_1\ => \dm_address_reg[19]_1\, + \dm_address_reg[19]_2\ => \dm_address_reg[19]_2\, + \dm_address_reg[23]\ => \dm_address_reg[23]\, + \dm_address_reg[23]_0\ => \dm_address_reg[23]_0\, + \dm_address_reg[23]_1\ => \dm_address_reg[23]_1\, + \dm_address_reg[23]_2\ => \dm_address_reg[23]_2\, + \dm_address_reg[27]\ => \dm_address_reg[27]\, + \dm_address_reg[27]_0\ => \dm_address_reg[27]_0\, + \dm_address_reg[27]_1\ => \dm_address_reg[27]_1\, + \dm_address_reg[27]_2\ => \dm_address_reg[27]_2\, + \dm_address_reg[31]\ => \dm_address_reg[31]\, + \dm_address_reg[31]_0\ => \dm_address_reg[31]_0\, + \dm_address_reg[31]_1\ => \dm_address_reg[31]_1\, + \dm_address_reg[31]_2\ => \dm_address_reg[31]_2\, + \dm_address_reg[7]\(3 downto 0) => \dm_address_reg[7]\(3 downto 0), + load_new_addr => load_new_addr, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + m_axis_s2mm_sts_tdata(0) => m_axis_s2mm_sts_tdata(0), + prmtr_update_complete => \^prmtr_update_complete\, + \reg_module_hsize_reg[15]\(15 downto 0) => \reg_module_hsize_reg[15]\(15 downto 0), + \reg_module_vsize_reg[12]\(12 downto 0) => \reg_module_vsize_reg[12]\(12 downto 0), + s2mm_cdc2dmac_fsync => s2mm_cdc2dmac_fsync, + zero_hsize_err0 => zero_hsize_err0, + zero_vsize_err0 => zero_vsize_err0 + ); +\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000EA00" + ) + port map ( + I0 => \^stride_vid_reg[0]\, + I1 => \^prmtr_update_complete\, + I2 => s2mm_cdc2dmac_fsync, + I3 => \out\, + I4 => s2mm_dmasr(0), + O => \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_i_1__0_n_0\ + ); +\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_i_1__0_n_0\, + Q => \^stride_vid_reg[0]\, + R => '0' + ); +\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => prmtr_updt_complete_i_reg, + Q => \^prmtr_update_complete\, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_vidreg_module_43 is + port ( + \stride_vid_reg[0]\ : out STD_LOGIC; + zero_vsize_err0 : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 12 downto 0 ); + zero_hsize_err0 : out STD_LOGIC; + \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + all_idle_reg : out STD_LOGIC; + \stride_vid_reg[0]_0\ : out STD_LOGIC; + p_10_out : out STD_LOGIC; + \dm_address_reg[19]\ : out STD_LOGIC; + \dm_address_reg[19]_0\ : out STD_LOGIC; + \dm_address_reg[19]_1\ : out STD_LOGIC; + \dm_address_reg[19]_2\ : out STD_LOGIC; + \dm_address_reg[23]\ : out STD_LOGIC; + \dm_address_reg[23]_0\ : out STD_LOGIC; + \dm_address_reg[23]_1\ : out STD_LOGIC; + \dm_address_reg[23]_2\ : out STD_LOGIC; + \dm_address_reg[27]\ : out STD_LOGIC; + \dm_address_reg[27]_0\ : out STD_LOGIC; + \dm_address_reg[27]_1\ : out STD_LOGIC; + \dm_address_reg[27]_2\ : out STD_LOGIC; + \dm_address_reg[31]\ : out STD_LOGIC; + \dm_address_reg[31]_0\ : out STD_LOGIC; + \dm_address_reg[31]_1\ : out STD_LOGIC; + \dm_address_reg[31]_2\ : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + O : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \dm_address_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \dm_address_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + CO : out STD_LOGIC_VECTOR ( 0 to 0 ); + \dm_address_reg[15]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + p_2_out : out STD_LOGIC; + prmtr_updt_complete_i_reg : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + load_new_addr : in STD_LOGIC; + p_39_out : in STD_LOGIC; + mm2s_fifo_pipe_empty : in STD_LOGIC; + p_67_out : in STD_LOGIC; + tstvect_fsync_d2 : in STD_LOGIC; + \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + p_24_out : in STD_LOGIC; + \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]_0\ : in STD_LOGIC; + valid_frame_sync_d2 : in STD_LOGIC; + p_71_out : in STD_LOGIC_VECTOR ( 0 to 0 ); + \dm_address_reg[15]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + mask_fsync_out_i : in STD_LOGIC; + tstvect_fsync_d1 : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + \reg_module_vsize_reg[12]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + \reg_module_hsize_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + mm2s_prmry_resetn : in STD_LOGIC; + p_70_out : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_vidreg_module_43 : entity is "axi_vdma_vidreg_module"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_vidreg_module_43; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_vidreg_module_43 is + signal \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_i_1_n_0\ : STD_LOGIC; + signal \^stride_vid_reg[0]\ : STD_LOGIC; + signal \^stride_vid_reg[0]_0\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_2\ : label is "soft_lutpair42"; + attribute SOFT_HLUTNM of \MASTER_MODE_FRAME_CNT.tstvect_fsync_i_1\ : label is "soft_lutpair42"; +begin + \stride_vid_reg[0]\ <= \^stride_vid_reg[0]\; + \stride_vid_reg[0]_0\ <= \^stride_vid_reg[0]_0\; +\GEN_FREE_RUN_MODE.frame_sync_out_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"20" + ) + port map ( + I0 => \^stride_vid_reg[0]_0\, + I1 => mask_fsync_out_i, + I2 => tstvect_fsync_d1, + O => p_2_out + ); +\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.VIDREGISTER_I\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_vregister_44 + port map ( + CO(0) => CO(0), + \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15]\(15 downto 0) => \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15]\(15 downto 0), + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(31 downto 0) => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(31 downto 0), + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(31 downto 0) => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(31 downto 0), + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(31 downto 0) => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(31 downto 0), + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\ => \^stride_vid_reg[0]_0\, + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg\ => \^stride_vid_reg[0]\, + \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1 downto 0) => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1 downto 0), + \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(15 downto 0) => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(15 downto 0), + O(3 downto 0) => O(3 downto 0), + Q(12 downto 0) => Q(12 downto 0), + SR(0) => SR(0), + \dm_address_reg[11]\(3 downto 0) => \dm_address_reg[11]\(3 downto 0), + \dm_address_reg[15]\(3 downto 0) => \dm_address_reg[15]\(3 downto 0), + \dm_address_reg[15]_0\(15 downto 0) => \dm_address_reg[15]_0\(15 downto 0), + \dm_address_reg[19]\ => \dm_address_reg[19]\, + \dm_address_reg[19]_0\ => \dm_address_reg[19]_0\, + \dm_address_reg[19]_1\ => \dm_address_reg[19]_1\, + \dm_address_reg[19]_2\ => \dm_address_reg[19]_2\, + \dm_address_reg[23]\ => \dm_address_reg[23]\, + \dm_address_reg[23]_0\ => \dm_address_reg[23]_0\, + \dm_address_reg[23]_1\ => \dm_address_reg[23]_1\, + \dm_address_reg[23]_2\ => \dm_address_reg[23]_2\, + \dm_address_reg[27]\ => \dm_address_reg[27]\, + \dm_address_reg[27]_0\ => \dm_address_reg[27]_0\, + \dm_address_reg[27]_1\ => \dm_address_reg[27]_1\, + \dm_address_reg[27]_2\ => \dm_address_reg[27]_2\, + \dm_address_reg[31]\ => \dm_address_reg[31]\, + \dm_address_reg[31]_0\ => \dm_address_reg[31]_0\, + \dm_address_reg[31]_1\ => \dm_address_reg[31]_1\, + \dm_address_reg[31]_2\ => \dm_address_reg[31]_2\, + \dm_address_reg[7]\(3 downto 0) => \dm_address_reg[7]\(3 downto 0), + load_new_addr => load_new_addr, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + p_24_out => p_24_out, + \reg_module_hsize_reg[15]\(15 downto 0) => \reg_module_hsize_reg[15]\(15 downto 0), + \reg_module_vsize_reg[12]\(12 downto 0) => \reg_module_vsize_reg[12]\(12 downto 0), + zero_hsize_err0 => zero_hsize_err0, + zero_vsize_err0 => zero_vsize_err0 + ); +\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000EA00" + ) + port map ( + I0 => \^stride_vid_reg[0]_0\, + I1 => p_24_out, + I2 => \^stride_vid_reg[0]\, + I3 => mm2s_prmry_resetn, + I4 => p_70_out, + O => \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_i_1_n_0\ + ); +\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_i_1_n_0\, + Q => \^stride_vid_reg[0]_0\, + R => '0' + ); +\GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => prmtr_updt_complete_i_reg, + Q => \^stride_vid_reg[0]\, + R => '0' + ); +\MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EAFA" + ) + port map ( + I0 => \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]_0\, + I1 => \^stride_vid_reg[0]_0\, + I2 => valid_frame_sync_d2, + I3 => p_71_out(0), + O => E(0) + ); +\MASTER_MODE_FRAME_CNT.tstvect_fsync_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^stride_vid_reg[0]_0\, + I1 => tstvect_fsync_d2, + O => p_10_out + ); +all_idle_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888000" + ) + port map ( + I0 => p_39_out, + I1 => mm2s_fifo_pipe_empty, + I2 => \^stride_vid_reg[0]\, + I3 => p_67_out, + I4 => \^stride_vid_reg[0]_0\, + O => all_idle_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f is + port ( + sig_calc_error_reg_reg : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axis_cmd_tvalid_reg : out STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : out STD_LOGIC_VECTOR ( 49 downto 0 ); + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_psm_halt : in STD_LOGIC; + sig_input_reg_empty : in STD_LOGIC; + p_10_out : in STD_LOGIC; + cmnd_wr_1 : in STD_LOGIC; + sig_inhibit_rdy_n : in STD_LOGIC; + s2mm_halt : in STD_LOGIC; + s_axis_s2mm_cmd_tvalid : in STD_LOGIC; + \s_axis_cmd_tdata_reg[63]\ : in STD_LOGIC_VECTOR ( 48 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f : entity is "srl_fifo_rbu_f"; +end Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f is + signal CNTR_INCR_DECR_ADDN_F_I_n_2 : STD_LOGIC; + signal CNTR_INCR_DECR_ADDN_F_I_n_3 : STD_LOGIC; + signal FIFO_Full_reg_n_0 : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal fifo_full_p1 : STD_LOGIC; + signal sig_wr_fifo : STD_LOGIC; +begin + Q(0) <= \^q\(0); +CNTR_INCR_DECR_ADDN_F_I: entity work.Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_16 + port map ( + Q(2) => \^q\(0), + Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_2, + Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_3, + fifo_full_p1 => fifo_full_p1, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + sig_input_reg_empty => sig_input_reg_empty, + sig_psm_halt => sig_psm_halt, + sig_stream_rst => sig_stream_rst, + sig_wr_fifo => sig_wr_fifo + ); +DYNSHREG_F_I: entity work.Arty_Z7_20_axi_vdma_0_0_dynshreg_f + port map ( + FIFO_Full_reg => FIFO_Full_reg_n_0, + Q(2) => \^q\(0), + Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_2, + Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_3, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\(49 downto 0) => \out\(49 downto 0), + p_10_out => p_10_out, + \s_axis_cmd_tdata_reg[63]\(48 downto 0) => \s_axis_cmd_tdata_reg[63]\(48 downto 0), + s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid, + sig_calc_error_reg_reg => sig_calc_error_reg_reg, + sig_inhibit_rdy_n => sig_inhibit_rdy_n, + sig_input_reg_empty => sig_input_reg_empty, + sig_psm_halt => sig_psm_halt, + sig_wr_fifo => sig_wr_fifo + ); +FIFO_Full_reg: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => fifo_full_p1, + Q => FIFO_Full_reg_n_0, + R => sig_stream_rst + ); +\s_axis_cmd_tdata[63]_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFAE" + ) + port map ( + I0 => cmnd_wr_1, + I1 => sig_inhibit_rdy_n, + I2 => FIFO_Full_reg_n_0, + I3 => s2mm_halt, + O => s_axis_cmd_tvalid_reg(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f_24 is + port ( + sig_calc_error_reg_reg : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 0 to 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : out STD_LOGIC_VECTOR ( 49 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_sm_halt_reg : in STD_LOGIC; + sig_input_reg_empty : in STD_LOGIC; + cmnd_wr : in STD_LOGIC; + sig_inhibit_rdy_n : in STD_LOGIC; + mm2s_halt : in STD_LOGIC; + sig_calc_error_pushed_reg : in STD_LOGIC; + sig_calc_error_pushed : in STD_LOGIC; + p_56_out : in STD_LOGIC; + \s_axis_cmd_tdata_reg[63]\ : in STD_LOGIC_VECTOR ( 48 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f_24 : entity is "srl_fifo_rbu_f"; +end Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f_24; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f_24 is + signal CNTR_INCR_DECR_ADDN_F_I_n_2 : STD_LOGIC; + signal CNTR_INCR_DECR_ADDN_F_I_n_3 : STD_LOGIC; + signal FIFO_Full_reg_n_0 : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal fifo_full_p1 : STD_LOGIC; + signal sig_wr_fifo : STD_LOGIC; +begin + Q(0) <= \^q\(0); +CNTR_INCR_DECR_ADDN_F_I: entity work.Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_25 + port map ( + FIFO_Full_reg => FIFO_Full_reg_n_0, + Q(2) => \^q\(0), + Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_2, + Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_3, + SR(0) => SR(0), + fifo_full_p1 => fifo_full_p1, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + p_56_out => p_56_out, + sig_calc_error_pushed => sig_calc_error_pushed, + sig_calc_error_pushed_reg => sig_calc_error_pushed_reg, + sig_inhibit_rdy_n => sig_inhibit_rdy_n, + sig_input_reg_empty => sig_input_reg_empty, + sig_sm_halt_reg => sig_sm_halt_reg, + sig_wr_fifo => sig_wr_fifo + ); +DYNSHREG_F_I: entity work.Arty_Z7_20_axi_vdma_0_0_dynshreg_f_26 + port map ( + FIFO_Full_reg => FIFO_Full_reg_n_0, + Q(2) => \^q\(0), + Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_2, + Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_3, + \in\(0) => \in\(0), + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + \out\(49 downto 0) => \out\(49 downto 0), + p_56_out => p_56_out, + \s_axis_cmd_tdata_reg[63]\(48 downto 0) => \s_axis_cmd_tdata_reg[63]\(48 downto 0), + sig_calc_error_reg_reg => sig_calc_error_reg_reg, + sig_inhibit_rdy_n => sig_inhibit_rdy_n, + sig_input_reg_empty => sig_input_reg_empty, + sig_sm_halt_reg => sig_sm_halt_reg, + sig_wr_fifo => sig_wr_fifo + ); +FIFO_Full_reg: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => fifo_full_p1, + Q => FIFO_Full_reg_n_0, + R => SR(0) + ); +\s_axis_cmd_tdata[63]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFAE" + ) + port map ( + I0 => cmnd_wr, + I1 => sig_inhibit_rdy_n, + I2 => FIFO_Full_reg_n_0, + I3 => mm2s_halt, + O => E(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized0\ is + port ( + \INFERRED_GEN.cnt_i_reg[1]\ : out STD_LOGIC; + sig_rd_sts_slverr_reg_reg : out STD_LOGIC; + decerr_i_reg : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 0 to 0 ); + slverr_i_reg : out STD_LOGIC; + interr_i_reg : out STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + sig_inhibit_rdy_n_reg : in STD_LOGIC; + sig_rsc2stat_status_valid : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + p_58_out : in STD_LOGIC; + sts_tready_reg : in STD_LOGIC; + sig_rd_sts_slverr_reg_reg_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized0\ : entity is "srl_fifo_rbu_f"; +end \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized0\ is + signal CNTR_INCR_DECR_ADDN_F_I_n_2 : STD_LOGIC; + signal CNTR_INCR_DECR_ADDN_F_I_n_3 : STD_LOGIC; + signal \^inferred_gen.cnt_i_reg[1]\ : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal fifo_full_p1 : STD_LOGIC; + signal sig_wr_fifo : STD_LOGIC; +begin + \INFERRED_GEN.cnt_i_reg[1]\ <= \^inferred_gen.cnt_i_reg[1]\; + Q(0) <= \^q\(0); +CNTR_INCR_DECR_ADDN_F_I: entity work.Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_27 + port map ( + FIFO_Full_reg => \^inferred_gen.cnt_i_reg[1]\, + Q(2) => \^q\(0), + Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_2, + Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_3, + SR(0) => SR(0), + fifo_full_p1 => fifo_full_p1, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + p_58_out => p_58_out, + sig_inhibit_rdy_n_reg => sig_inhibit_rdy_n_reg, + sig_rsc2stat_status_valid => sig_rsc2stat_status_valid, + sig_wr_fifo => sig_wr_fifo, + sts_tready_reg => sts_tready_reg + ); +DYNSHREG_F_I: entity work.\Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized0\ + port map ( + FIFO_Full_reg => \^inferred_gen.cnt_i_reg[1]\, + Q(2) => \^q\(0), + Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_2, + Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_3, + decerr_i_reg => decerr_i_reg, + interr_i_reg => interr_i_reg, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + sig_inhibit_rdy_n_reg => sig_inhibit_rdy_n_reg, + sig_rd_sts_slverr_reg_reg(2 downto 0) => sig_rd_sts_slverr_reg_reg_0(2 downto 0), + sig_rsc2stat_status_valid => sig_rsc2stat_status_valid, + sig_wr_fifo => sig_wr_fifo, + slverr_i_reg => slverr_i_reg + ); +FIFO_Full_reg: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => fifo_full_p1, + Q => \^inferred_gen.cnt_i_reg[1]\, + R => SR(0) + ); +sig_rd_sts_reg_full_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"20FF" + ) + port map ( + I0 => sig_inhibit_rdy_n_reg, + I1 => \^inferred_gen.cnt_i_reg[1]\, + I2 => sig_rsc2stat_status_valid, + I3 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + O => sig_rd_sts_slverr_reg_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized1\ is + port ( + sig_addr_valid_reg_reg : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 40 downto 0 ); + sig_posted_to_axi_2_reg : out STD_LOGIC; + sel : out STD_LOGIC; + sig_addr_reg_empty_reg : out STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + sig_addr_reg_empty : in STD_LOGIC; + sig_sf_allow_addr_req : in STD_LOGIC; + sig_data2addr_stop_req : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_inhibit_rdy_n : in STD_LOGIC; + sig_mstr2addr_cmd_valid : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 38 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized1\ : entity is "srl_fifo_rbu_f"; +end \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized1\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized1\ is + signal CNTR_INCR_DECR_ADDN_F_I_n_2 : STD_LOGIC; + signal CNTR_INCR_DECR_ADDN_F_I_n_3 : STD_LOGIC; + signal FIFO_Full_reg_n_0 : STD_LOGIC; + signal fifo_full_p1 : STD_LOGIC; + signal \^sel\ : STD_LOGIC; +begin + sel <= \^sel\; +CNTR_INCR_DECR_ADDN_F_I: entity work.Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_28 + port map ( + FIFO_Full_reg => \^sel\, + FIFO_Full_reg_0 => FIFO_Full_reg_n_0, + Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_2, + Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_3, + SR(0) => SR(0), + fifo_full_p1 => fifo_full_p1, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + sig_addr_reg_empty => sig_addr_reg_empty, + sig_addr_reg_empty_reg => sig_addr_reg_empty_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_data2addr_stop_req => sig_data2addr_stop_req, + sig_inhibit_rdy_n => sig_inhibit_rdy_n, + sig_mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid, + sig_posted_to_axi_2_reg => sig_posted_to_axi_2_reg, + sig_sf_allow_addr_req => sig_sf_allow_addr_req + ); +DYNSHREG_F_I: entity work.\Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized1\ + port map ( + FIFO_Full_reg => FIFO_Full_reg_n_0, + Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_2, + Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_3, + \in\(38 downto 0) => \in\(38 downto 0), + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + \out\(40 downto 0) => \out\(40 downto 0), + sig_addr_valid_reg_reg => sig_addr_valid_reg_reg, + sig_calc_error_reg_reg => \^sel\, + sig_inhibit_rdy_n => sig_inhibit_rdy_n, + sig_mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid + ); +FIFO_Full_reg: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => fifo_full_p1, + Q => FIFO_Full_reg_n_0, + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized10\ is + port ( + \INFERRED_GEN.cnt_i_reg[0]\ : out STD_LOGIC; + sig_last_dbeat_reg : out STD_LOGIC; + sig_dqual_reg_empty_reg : out STD_LOGIC; + sig_ld_new_cmd_reg_reg : out STD_LOGIC; + sig_next_calc_error_reg_reg : out STD_LOGIC; + sig_dqual_reg_empty_reg_0 : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 7 downto 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_dqual_reg_empty_reg_1 : out STD_LOGIC; + \sig_clr_cmd2data_valid4_out__0\ : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + \sig_first_dbeat1__0\ : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_single_dbeat : in STD_LOGIC; + sig_last_dbeat_reg_0 : in STD_LOGIC; + sig_ld_new_cmd_reg : in STD_LOGIC; + sig_next_calc_error_reg : in STD_LOGIC; + \sig_dbeat_cntr_reg[1]\ : in STD_LOGIC; + sig_dqual_reg_full_reg : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \sig_dbeat_cntr_reg[4]\ : in STD_LOGIC; + p_11_out : in STD_LOGIC; + sig_inhibit_rdy_n_reg : in STD_LOGIC; + \sig_dbeat_cntr_reg[2]\ : in STD_LOGIC; + \sig_dbeat_cntr_reg[3]\ : in STD_LOGIC; + sig_next_sequential_reg : in STD_LOGIC; + sig_dqual_reg_empty : in STD_LOGIC; + sig_halt_reg : in STD_LOGIC; + sig_m_valid_out_reg : in STD_LOGIC; + sig_s_ready_out_reg : in STD_LOGIC; + sig_wdc_status_going_full : in STD_LOGIC; + sig_inhibit_rdy_n_reg_0 : in STD_LOGIC; + sig_wsc2stat_status_valid : in STD_LOGIC; + sig_addr_posted_cntr : in STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_halt_reg_dly3 : in STD_LOGIC; + sig_last_mmap_dbeat_reg : in STD_LOGIC; + sig_posted_to_axi_reg : in STD_LOGIC; + sig_xfer_calc_err_reg_reg : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized10\ : entity is "srl_fifo_rbu_f"; +end \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized10\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized10\ is + signal CNTR_INCR_DECR_ADDN_F_I_n_7 : STD_LOGIC; + signal CNTR_INCR_DECR_ADDN_F_I_n_8 : STD_LOGIC; + signal \^inferred_gen.cnt_i_reg[0]\ : STD_LOGIC; + signal fifo_full_p1 : STD_LOGIC; + signal \^sig_dqual_reg_empty_reg\ : STD_LOGIC; + signal sig_wr_fifo : STD_LOGIC; +begin + \INFERRED_GEN.cnt_i_reg[0]\ <= \^inferred_gen.cnt_i_reg[0]\; + sig_dqual_reg_empty_reg <= \^sig_dqual_reg_empty_reg\; +CNTR_INCR_DECR_ADDN_F_I: entity work.Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f + port map ( + D(1 downto 0) => D(7 downto 6), + E(0) => E(0), + FIFO_Full_reg(1) => CNTR_INCR_DECR_ADDN_F_I_n_7, + FIFO_Full_reg(0) => CNTR_INCR_DECR_ADDN_F_I_n_8, + FIFO_Full_reg_0 => \^inferred_gen.cnt_i_reg[0]\, + Q(1 downto 0) => Q(7 downto 6), + fifo_full_p1 => fifo_full_p1, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + p_11_out => p_11_out, + sig_addr_posted_cntr(2 downto 0) => sig_addr_posted_cntr(2 downto 0), + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + \sig_dbeat_cntr_reg[1]\ => \sig_dbeat_cntr_reg[1]\, + \sig_dbeat_cntr_reg[4]\ => \sig_dbeat_cntr_reg[4]\, + sig_dqual_reg_empty => sig_dqual_reg_empty, + sig_dqual_reg_empty_reg => \^sig_dqual_reg_empty_reg\, + sig_dqual_reg_empty_reg_0 => sig_dqual_reg_empty_reg_0, + sig_dqual_reg_empty_reg_1 => sig_dqual_reg_empty_reg_1, + sig_dqual_reg_full_reg => sig_dqual_reg_full_reg, + sig_halt_reg => sig_halt_reg, + sig_halt_reg_dly3 => sig_halt_reg_dly3, + sig_inhibit_rdy_n_reg => sig_inhibit_rdy_n_reg, + sig_inhibit_rdy_n_reg_0 => sig_inhibit_rdy_n_reg_0, + sig_last_dbeat_reg => sig_last_dbeat_reg_0, + sig_last_mmap_dbeat_reg => sig_last_mmap_dbeat_reg, + sig_ld_new_cmd_reg => sig_ld_new_cmd_reg, + sig_ld_new_cmd_reg_reg => sig_ld_new_cmd_reg_reg, + sig_m_valid_out_reg => sig_m_valid_out_reg, + sig_next_calc_error_reg => sig_next_calc_error_reg, + sig_next_calc_error_reg_reg => sig_next_calc_error_reg_reg, + sig_next_sequential_reg => sig_next_sequential_reg, + sig_posted_to_axi_reg => sig_posted_to_axi_reg, + sig_s_ready_out_reg => sig_s_ready_out_reg, + sig_stream_rst => sig_stream_rst, + sig_wdc_status_going_full => sig_wdc_status_going_full, + sig_wr_fifo => sig_wr_fifo, + sig_wsc2stat_status_valid => sig_wsc2stat_status_valid + ); +DYNSHREG_F_I: entity work.\Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized10\ + port map ( + D(5 downto 0) => D(5 downto 0), + FIFO_Full_reg => \^inferred_gen.cnt_i_reg[0]\, + \INFERRED_GEN.cnt_i_reg[1]\(1) => CNTR_INCR_DECR_ADDN_F_I_n_7, + \INFERRED_GEN.cnt_i_reg[1]\(0) => CNTR_INCR_DECR_ADDN_F_I_n_8, + Q(5 downto 0) => Q(5 downto 0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\(2 downto 0) => \out\(2 downto 0), + p_11_out => p_11_out, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + \sig_dbeat_cntr_reg[2]\ => \sig_dbeat_cntr_reg[2]\, + \sig_dbeat_cntr_reg[3]\ => \sig_dbeat_cntr_reg[3]\, + \sig_first_dbeat1__0\ => \sig_first_dbeat1__0\, + sig_inhibit_rdy_n_reg => sig_inhibit_rdy_n_reg, + sig_last_dbeat_reg => sig_last_dbeat_reg, + sig_last_dbeat_reg_0 => sig_last_dbeat_reg_0, + sig_next_sequential_reg_reg => \^sig_dqual_reg_empty_reg\, + sig_single_dbeat => sig_single_dbeat, + sig_wr_fifo => sig_wr_fifo, + sig_xfer_calc_err_reg_reg(8 downto 0) => sig_xfer_calc_err_reg_reg(8 downto 0) + ); +FIFO_Full_reg: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => fifo_full_p1, + Q => \^inferred_gen.cnt_i_reg[0]\, + R => sig_stream_rst + ); +\sig_xfer_addr_reg[31]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => \^inferred_gen.cnt_i_reg[0]\, + I1 => sig_inhibit_rdy_n_reg, + I2 => p_11_out, + O => \sig_clr_cmd2data_valid4_out__0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized2\ is + port ( + D : out STD_LOGIC_VECTOR ( 7 downto 0 ); + sig_dqual_reg_empty_reg : out STD_LOGIC; + sig_next_cmd_cmplt_reg_reg : out STD_LOGIC; + sig_dqual_reg_empty_reg_0 : out STD_LOGIC; + sel : out STD_LOGIC; + sig_last_dbeat_reg : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \sig_dbeat_cntr_reg[0]\ : in STD_LOGIC; + m_axi_mm2s_rlast : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_mstr2data_cmd_valid : in STD_LOGIC; + sig_inhibit_rdy_n_0 : in STD_LOGIC; + \sig_dbeat_cntr_reg[3]\ : in STD_LOGIC; + \sig_dbeat_cntr_reg[5]\ : in STD_LOGIC; + sig_next_sequential_reg : in STD_LOGIC; + sig_last_dbeat : in STD_LOGIC; + sig_dqual_reg_empty : in STD_LOGIC; + sig_rsc2stat_status_valid : in STD_LOGIC; + FIFO_Full_reg_0 : in STD_LOGIC; + sig_inhibit_rdy_n : in STD_LOGIC; + sig_next_calc_error_reg_reg : in STD_LOGIC; + \sig_addr_posted_cntr_reg[2]\ : in STD_LOGIC; + \sig_addr_posted_cntr_reg[1]\ : in STD_LOGIC; + \sig_addr_posted_cntr_reg[0]\ : in STD_LOGIC; + ram_full_i_reg : in STD_LOGIC; + sig_halt_reg_reg : in STD_LOGIC; + m_axi_mm2s_rvalid : in STD_LOGIC; + sig_dqual_reg_full : in STD_LOGIC; + sig_data2rsc_valid : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized2\ : entity is "srl_fifo_rbu_f"; +end \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized2\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized2\ is + signal CNTR_INCR_DECR_ADDN_F_I_n_7 : STD_LOGIC; + signal CNTR_INCR_DECR_ADDN_F_I_n_8 : STD_LOGIC; + signal FIFO_Full_reg_n_0 : STD_LOGIC; + signal fifo_full_p1 : STD_LOGIC; + signal \^sel\ : STD_LOGIC; + signal \^sig_dqual_reg_empty_reg\ : STD_LOGIC; +begin + sel <= \^sel\; + sig_dqual_reg_empty_reg <= \^sig_dqual_reg_empty_reg\; +CNTR_INCR_DECR_ADDN_F_I: entity work.Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_21 + port map ( + D(2 downto 0) => D(7 downto 5), + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\, + E(0) => E(0), + FIFO_Full_reg(1) => CNTR_INCR_DECR_ADDN_F_I_n_7, + FIFO_Full_reg(0) => CNTR_INCR_DECR_ADDN_F_I_n_8, + FIFO_Full_reg_0 => \^sel\, + FIFO_Full_reg_1 => FIFO_Full_reg_n_0, + FIFO_Full_reg_2 => FIFO_Full_reg_0, + Q(3 downto 0) => Q(7 downto 4), + SR(0) => SR(0), + fifo_full_p1 => fifo_full_p1, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axi_mm2s_rlast => m_axi_mm2s_rlast, + m_axi_mm2s_rvalid => m_axi_mm2s_rvalid, + ram_full_i_reg => ram_full_i_reg, + \sig_addr_posted_cntr_reg[0]\ => \sig_addr_posted_cntr_reg[0]\, + \sig_addr_posted_cntr_reg[1]\ => \sig_addr_posted_cntr_reg[1]\, + \sig_addr_posted_cntr_reg[2]\ => \sig_addr_posted_cntr_reg[2]\, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_data2rsc_valid => sig_data2rsc_valid, + \sig_dbeat_cntr_reg[0]\ => \sig_dbeat_cntr_reg[0]\, + \sig_dbeat_cntr_reg[5]\ => \sig_dbeat_cntr_reg[5]\, + sig_dqual_reg_empty => sig_dqual_reg_empty, + sig_dqual_reg_empty_reg => \^sig_dqual_reg_empty_reg\, + sig_dqual_reg_empty_reg_0 => sig_dqual_reg_empty_reg_0, + sig_dqual_reg_full => sig_dqual_reg_full, + sig_halt_reg_reg => sig_halt_reg_reg, + sig_inhibit_rdy_n => sig_inhibit_rdy_n, + sig_inhibit_rdy_n_0 => sig_inhibit_rdy_n_0, + sig_last_dbeat => sig_last_dbeat, + sig_mstr2data_cmd_valid => sig_mstr2data_cmd_valid, + sig_next_calc_error_reg_reg => sig_next_calc_error_reg_reg, + sig_next_cmd_cmplt_reg_reg => sig_next_cmd_cmplt_reg_reg, + sig_next_sequential_reg => sig_next_sequential_reg, + sig_rsc2stat_status_valid => sig_rsc2stat_status_valid + ); +DYNSHREG_F_I: entity work.\Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized2\ + port map ( + D(4 downto 0) => D(4 downto 0), + FIFO_Full_reg => FIFO_Full_reg_n_0, + \INFERRED_GEN.cnt_i_reg[1]\(1) => CNTR_INCR_DECR_ADDN_F_I_n_7, + \INFERRED_GEN.cnt_i_reg[1]\(0) => CNTR_INCR_DECR_ADDN_F_I_n_8, + Q(4 downto 0) => Q(4 downto 0), + \in\(8 downto 0) => \in\(8 downto 0), + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + \out\(3 downto 0) => \out\(3 downto 0), + \sig_dbeat_cntr_reg[0]\ => \sig_dbeat_cntr_reg[0]\, + \sig_dbeat_cntr_reg[3]\ => \sig_dbeat_cntr_reg[3]\, + sig_inhibit_rdy_n_0 => sig_inhibit_rdy_n_0, + sig_last_dbeat_reg => sig_last_dbeat_reg, + sig_mstr2data_cmd_valid => sig_mstr2data_cmd_valid, + sig_next_calc_error_reg_reg => \^sel\, + sig_next_sequential_reg_reg => \^sig_dqual_reg_empty_reg\ + ); +FIFO_Full_reg: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => fifo_full_p1, + Q => FIFO_Full_reg_n_0, + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized3\ is + port ( + FIFO_Full_reg_0 : out STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[1]\ : out STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 0 to 0 ); + \in\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + lsig_cmd_loaded : in STD_LOGIC; + prmry_resetn_i_reg : in STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ : in STD_LOGIC; + DOBDO : in STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : in STD_LOGIC; + sig_inhibit_rdy_n_reg : in STD_LOGIC; + sig_mstr2sf_cmd_valid : in STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized3\ : entity is "srl_fifo_rbu_f"; +end \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized3\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized3\ is + signal CNTR_INCR_DECR_ADDN_F_I_n_2 : STD_LOGIC; + signal CNTR_INCR_DECR_ADDN_F_I_n_3 : STD_LOGIC; + signal \^fifo_full_reg_0\ : STD_LOGIC; + signal \^inferred_gen.cnt_i_reg[1]\ : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal fifo_full_p1 : STD_LOGIC; +begin + FIFO_Full_reg_0 <= \^fifo_full_reg_0\; + \INFERRED_GEN.cnt_i_reg[1]\ <= \^inferred_gen.cnt_i_reg[1]\; + Q(0) <= \^q\(0); +CNTR_INCR_DECR_ADDN_F_I: entity work.Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_29 + port map ( + DOBDO(0) => DOBDO(0), + FIFO_Full_reg => \^fifo_full_reg_0\, + FIFO_Full_reg_0 => \^inferred_gen.cnt_i_reg[1]\, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1\, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, + Q(2) => \^q\(0), + Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_2, + Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_3, + SR(0) => SR(0), + fifo_full_p1 => fifo_full_p1, + lsig_cmd_loaded => lsig_cmd_loaded, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + sig_inhibit_rdy_n_reg => sig_inhibit_rdy_n_reg, + sig_mstr2sf_cmd_valid => sig_mstr2sf_cmd_valid + ); +DYNSHREG_F_I: entity work.\Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized3\ + port map ( + DOBDO(0) => DOBDO(0), + FIFO_Full_reg => \^fifo_full_reg_0\, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + Q(2) => \^q\(0), + Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_2, + Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_3, + \in\(0) => \in\(0), + lsig_cmd_loaded => lsig_cmd_loaded, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + prmry_resetn_i_reg => prmry_resetn_i_reg + ); +FIFO_Full_reg: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => fifo_full_p1, + Q => \^inferred_gen.cnt_i_reg[1]\, + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized4\ is + port ( + p_9_out : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 0 to 0 ); + CO : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg\ : out STD_LOGIC; + decerr_i_reg : out STD_LOGIC; + slverr_i_reg : out STD_LOGIC; + interr_i_reg : out STD_LOGIC; + sig_dqual_reg_empty_reg : out STD_LOGIC; + \GEN_STS_GRTR_THAN_8.ovrflo_err_reg\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + s2mm_halt : in STD_LOGIC; + s2mm_soft_reset : in STD_LOGIC; + dma_err : in STD_LOGIC; + \hsize_vid_reg[15]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + \hsize_vid_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + S : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_inhibit_rdy_n : in STD_LOGIC; + sig_wsc2stat_status_valid : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + m_axis_s2mm_sts_tready : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 16 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized4\ : entity is "srl_fifo_rbu_f"; +end \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized4\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized4\ is + signal CNTR_INCR_DECR_ADDN_F_I_n_2 : STD_LOGIC; + signal CNTR_INCR_DECR_ADDN_F_I_n_3 : STD_LOGIC; + signal DYNSHREG_F_I_n_3 : STD_LOGIC; + signal FIFO_Full_reg_n_0 : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal fifo_full_p1 : STD_LOGIC; + signal m_axis_s2mm_sts_tdata : STD_LOGIC_VECTOR ( 31 to 31 ); + signal sig_wr_fifo : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \GEN_ENABLE_INDET_BTT.sig_coelsc_reg_empty_i_1\ : label is "soft_lutpair238"; + attribute SOFT_HLUTNM of sig_next_calc_error_reg_i_7 : label is "soft_lutpair238"; +begin + Q(0) <= \^q\(0); +CNTR_INCR_DECR_ADDN_F_I: entity work.Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_17 + port map ( + CO(0) => DYNSHREG_F_I_n_3, + FIFO_Full_reg => FIFO_Full_reg_n_0, + Q(2) => \^q\(0), + Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_2, + Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_3, + dma_err => dma_err, + fifo_full_p1 => fifo_full_p1, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready, + \out\(0) => m_axis_s2mm_sts_tdata(31), + p_9_out => p_9_out, + s2mm_halt => s2mm_halt, + s2mm_soft_reset => s2mm_soft_reset, + sig_inhibit_rdy_n => sig_inhibit_rdy_n, + sig_stream_rst => sig_stream_rst, + sig_wr_fifo => sig_wr_fifo, + sig_wsc2stat_status_valid => sig_wsc2stat_status_valid + ); +DYNSHREG_F_I: entity work.\Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized4\ + port map ( + CO(0) => CO(0), + FIFO_Full_reg => FIFO_Full_reg_n_0, + \GEN_STS_GRTR_THAN_8.ovrflo_err_reg\(0) => DYNSHREG_F_I_n_3, + Q(2) => \^q\(0), + Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_2, + Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_3, + S(0) => S(0), + decerr_i_reg => decerr_i_reg, + \hsize_vid_reg[15]\(12 downto 0) => \hsize_vid_reg[15]\(12 downto 0), + \hsize_vid_reg[2]\(0) => \hsize_vid_reg[2]\(0), + \in\(16 downto 0) => \in\(16 downto 0), + interr_i_reg => interr_i_reg, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\(1) => m_axis_s2mm_sts_tdata(31), + \out\(0) => \GEN_STS_GRTR_THAN_8.ovrflo_err_reg\(0), + sig_inhibit_rdy_n => sig_inhibit_rdy_n, + sig_wr_fifo => sig_wr_fifo, + sig_wsc2stat_status_valid => sig_wsc2stat_status_valid, + slverr_i_reg => slverr_i_reg + ); +FIFO_Full_reg: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => fifo_full_p1, + Q => FIFO_Full_reg_n_0, + R => sig_stream_rst + ); +\GEN_ENABLE_INDET_BTT.sig_coelsc_reg_empty_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"20FF" + ) + port map ( + I0 => sig_inhibit_rdy_n, + I1 => FIFO_Full_reg_n_0, + I2 => sig_wsc2stat_status_valid, + I3 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + O => \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg\ + ); +sig_next_calc_error_reg_i_7: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => sig_inhibit_rdy_n, + I1 => FIFO_Full_reg_n_0, + O => sig_dqual_reg_empty_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized5\ is + port ( + \GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg\ : out STD_LOGIC; + \GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg\ : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \INFERRED_GEN.cnt_i_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_s2mm_bready : out STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_posted_to_axi_reg : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); + sig_push_coelsc_reg : in STD_LOGIC; + m_axi_s2mm_bvalid : in STD_LOGIC; + sig_inhibit_rdy_n : in STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[3]\ : in STD_LOGIC; + sig_halt_reg : in STD_LOGIC; + m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized5\ : entity is "srl_fifo_rbu_f"; +end \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized5\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized5\ is + signal CNTR_INCR_DECR_ADDN_F_I_n_2 : STD_LOGIC; + signal CNTR_INCR_DECR_ADDN_F_I_n_3 : STD_LOGIC; + signal CNTR_INCR_DECR_ADDN_F_I_n_4 : STD_LOGIC; + signal FIFO_Full_reg_n_0 : STD_LOGIC; + signal fifo_full_p1 : STD_LOGIC; + signal sig_decr_addr_posted_cntr5_out : STD_LOGIC; + signal sig_wr_fifo : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of m_axi_s2mm_bready_INST_0 : label is "soft_lutpair251"; + attribute SOFT_HLUTNM of \sig_addr_posted_cntr[3]_i_3\ : label is "soft_lutpair251"; +begin +CNTR_INCR_DECR_ADDN_F_I: entity work.\Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f__parameterized0\ + port map ( + FIFO_Full_reg => FIFO_Full_reg_n_0, + \INFERRED_GEN.cnt_i_reg[3]_0\ => \INFERRED_GEN.cnt_i_reg[3]\, + Q(3) => \INFERRED_GEN.cnt_i_reg[2]\(0), + Q(2) => CNTR_INCR_DECR_ADDN_F_I_n_2, + Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_3, + Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_4, + fifo_full_p1 => fifo_full_p1, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + m_axi_s2mm_bvalid => m_axi_s2mm_bvalid, + sig_inhibit_rdy_n => sig_inhibit_rdy_n, + sig_push_coelsc_reg => sig_push_coelsc_reg, + sig_stream_rst => sig_stream_rst, + sig_wr_fifo => sig_wr_fifo + ); +DYNSHREG_F_I: entity work.\Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized5\ + port map ( + \GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg\ => \GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg\, + \GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg\ => \GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg\, + addr(0) => CNTR_INCR_DECR_ADDN_F_I_n_2, + addr(1) => CNTR_INCR_DECR_ADDN_F_I_n_3, + addr(2) => CNTR_INCR_DECR_ADDN_F_I_n_4, + \in\(1 downto 0) => \in\(1 downto 0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + m_axi_s2mm_bresp(1 downto 0) => m_axi_s2mm_bresp(1 downto 0), + \out\(0) => \out\(0), + sel => sig_wr_fifo + ); +FIFO_Full_reg: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => fifo_full_p1, + Q => FIFO_Full_reg_n_0, + R => sig_stream_rst + ); +m_axi_s2mm_bready_INST_0: unisim.vcomponents.LUT3 + generic map( + INIT => X"F4" + ) + port map ( + I0 => FIFO_Full_reg_n_0, + I1 => sig_inhibit_rdy_n, + I2 => sig_halt_reg, + O => m_axi_s2mm_bready + ); +\sig_addr_posted_cntr[1]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FDDD22222222DDDD" + ) + port map ( + I0 => sig_posted_to_axi_reg, + I1 => sig_decr_addr_posted_cntr5_out, + I2 => Q(3), + I3 => Q(2), + I4 => Q(0), + I5 => Q(1), + O => D(0) + ); +\sig_addr_posted_cntr[2]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FD22FF00FF0022DD" + ) + port map ( + I0 => sig_posted_to_axi_reg, + I1 => sig_decr_addr_posted_cntr5_out, + I2 => Q(3), + I3 => Q(2), + I4 => Q(0), + I5 => Q(1), + O => D(1) + ); +\sig_addr_posted_cntr[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000FFFE7FFF0000" + ) + port map ( + I0 => Q(1), + I1 => Q(0), + I2 => Q(2), + I3 => Q(3), + I4 => sig_posted_to_axi_reg, + I5 => sig_decr_addr_posted_cntr5_out, + O => E(0) + ); +\sig_addr_posted_cntr[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F2F0F0F0F0F0F02D" + ) + port map ( + I0 => sig_posted_to_axi_reg, + I1 => sig_decr_addr_posted_cntr5_out, + I2 => Q(3), + I3 => Q(2), + I4 => Q(0), + I5 => Q(1), + O => D(2) + ); +\sig_addr_posted_cntr[3]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => FIFO_Full_reg_n_0, + I1 => sig_inhibit_rdy_n, + I2 => m_axi_s2mm_bvalid, + O => sig_decr_addr_posted_cntr5_out + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized6\ is + port ( + p_0_in : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + sig_push_to_wsc_reg : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + sel : out STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[1]\ : out STD_LOGIC; + \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg\ : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + p_4_out : out STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_inhibit_rdy_n : in STD_LOGIC; + sig_data2wsc_valid : in STD_LOGIC; + sig_set_push2wsc : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \INFERRED_GEN.cnt_i_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_coelsc_reg_empty : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_INDET_BTT.lsig_eop_reg_reg\ : in STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized6\ : entity is "srl_fifo_rbu_f"; +end \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized6\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized6\ is + signal CNTR_INCR_DECR_ADDN_F_I_n_2 : STD_LOGIC; + signal CNTR_INCR_DECR_ADDN_F_I_n_3 : STD_LOGIC; + signal CNTR_INCR_DECR_ADDN_F_I_n_4 : STD_LOGIC; + signal DYNSHREG_F_I_n_21 : STD_LOGIC; + signal FIFO_Full_reg_n_0 : STD_LOGIC; + signal fifo_full_p1 : STD_LOGIC; + signal \^out\ : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \^sel\ : STD_LOGIC; + signal sig_rd_empty : STD_LOGIC; +begin + \out\(15 downto 0) <= \^out\(15 downto 0); + sel <= \^sel\; +CNTR_INCR_DECR_ADDN_F_I: entity work.\Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f__parameterized1\ + port map ( + FIFO_Full_reg => FIFO_Full_reg_n_0, + \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg\ => \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg\, + \INFERRED_GEN.cnt_i_reg[1]_0\ => \INFERRED_GEN.cnt_i_reg[1]\, + \INFERRED_GEN.cnt_i_reg[3]_0\(0) => \INFERRED_GEN.cnt_i_reg[3]\(0), + \INFERRED_GEN.cnt_i_reg[3]_1\ => DYNSHREG_F_I_n_21, + Q(3) => sig_rd_empty, + Q(2) => CNTR_INCR_DECR_ADDN_F_I_n_2, + Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_3, + Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_4, + fifo_full_p1 => fifo_full_p1, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\(0) => \^out\(0), + sig_coelsc_reg_empty => sig_coelsc_reg_empty, + sig_data2wsc_valid => sig_data2wsc_valid, + sig_inhibit_rdy_n => sig_inhibit_rdy_n, + sig_push_to_wsc_reg => \^sel\, + sig_stream_rst => sig_stream_rst + ); +DYNSHREG_F_I: entity work.\Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized6\ + port map ( + D(2 downto 0) => D(2 downto 0), + E(0) => E(0), + FIFO_Full_reg => FIFO_Full_reg_n_0, + \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg\ => \^sel\, + \GEN_INDET_BTT.lsig_eop_reg_reg\(15 downto 0) => \GEN_INDET_BTT.lsig_eop_reg_reg\(15 downto 0), + \INFERRED_GEN.cnt_i_reg[3]\(0) => \INFERRED_GEN.cnt_i_reg[3]\(0), + \INFERRED_GEN.cnt_i_reg[3]_0\(3) => sig_rd_empty, + \INFERRED_GEN.cnt_i_reg[3]_0\(2) => CNTR_INCR_DECR_ADDN_F_I_n_2, + \INFERRED_GEN.cnt_i_reg[3]_0\(1) => CNTR_INCR_DECR_ADDN_F_I_n_3, + \INFERRED_GEN.cnt_i_reg[3]_0\(0) => CNTR_INCR_DECR_ADDN_F_I_n_4, + Q(3 downto 0) => Q(3 downto 0), + \in\(0) => \in\(0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\(15 downto 0) => \^out\(15 downto 0), + p_0_in => p_0_in, + p_4_out => p_4_out, + sig_coelsc_reg_empty => sig_coelsc_reg_empty, + sig_data2wsc_valid => sig_data2wsc_valid, + sig_inhibit_rdy_n => sig_inhibit_rdy_n, + \sig_wdc_statcnt_reg[3]\ => DYNSHREG_F_I_n_21 + ); +FIFO_Full_reg: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => fifo_full_p1, + Q => FIFO_Full_reg_n_0, + R => sig_stream_rst + ); +sig_push_to_wsc_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAAAA200" + ) + port map ( + I0 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I1 => sig_inhibit_rdy_n, + I2 => FIFO_Full_reg_n_0, + I3 => sig_data2wsc_valid, + I4 => sig_set_push2wsc, + O => sig_push_to_wsc_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized7\ is + port ( + \INFERRED_GEN.cnt_i_reg[0]\ : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg\ : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 19 downto 0 ); + sig_sm_pop_cmd_fifo_ns : out STD_LOGIC; + sig_sm_ld_dre_cmd_ns : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_need_cmd_flush : in STD_LOGIC; + p_7_out : in STD_LOGIC; + sig_sm_pop_cmd_fifo : in STD_LOGIC; + p_9_out_0 : in STD_LOGIC; + sig_inhibit_rdy_n_reg : in STD_LOGIC; + lsig_cmd_fetch_pause : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + \sig_good_tlast_dbeat37_out__0\ : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 21 downto 0 ); + \FSM_sequential_sig_cmdcntl_sm_state_reg[0]\ : in STD_LOGIC; + \FSM_sequential_sig_cmdcntl_sm_state_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_cmd_empty_reg : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized7\ : entity is "srl_fifo_rbu_f"; +end \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized7\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized7\ is + signal CNTR_INCR_DECR_ADDN_F_I_n_1 : STD_LOGIC; + signal CNTR_INCR_DECR_ADDN_F_I_n_2 : STD_LOGIC; + signal DYNSHREG_F_I_n_0 : STD_LOGIC; + signal \^inferred_gen.cnt_i_reg[0]\ : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal fifo_full_p1 : STD_LOGIC; + signal sig_cmd_fifo_data_out : STD_LOGIC_VECTOR ( 25 to 25 ); + signal sig_wr_fifo : STD_LOGIC; +begin + \INFERRED_GEN.cnt_i_reg[0]\ <= \^inferred_gen.cnt_i_reg[0]\; + Q(0) <= \^q\(0); +CNTR_INCR_DECR_ADDN_F_I: entity work.Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_19 + port map ( + D(1) => D(2), + D(0) => D(0), + FIFO_Full_reg => \^inferred_gen.cnt_i_reg[0]\, + \FSM_sequential_sig_cmdcntl_sm_state_reg[2]\(2 downto 0) => \FSM_sequential_sig_cmdcntl_sm_state_reg[2]\(2 downto 0), + \INFERRED_GEN.cnt_i_reg[2]_0\ => DYNSHREG_F_I_n_0, + Q(2) => \^q\(0), + Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_1, + Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_2, + fifo_full_p1 => fifo_full_p1, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\(0) => sig_cmd_fifo_data_out(25), + p_7_out => p_7_out, + p_9_out_0 => p_9_out_0, + sig_cmd_empty_reg => sig_cmd_empty_reg, + sig_inhibit_rdy_n_reg => sig_inhibit_rdy_n_reg, + sig_need_cmd_flush => sig_need_cmd_flush, + sig_sm_ld_dre_cmd_ns => sig_sm_ld_dre_cmd_ns, + sig_sm_pop_cmd_fifo => sig_sm_pop_cmd_fifo, + sig_stream_rst => sig_stream_rst, + sig_wr_fifo => sig_wr_fifo + ); +DYNSHREG_F_I: entity work.\Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized7\ + port map ( + D(0) => D(1), + E(0) => E(0), + FIFO_Full_reg => \^inferred_gen.cnt_i_reg[0]\, + \FSM_sequential_sig_cmdcntl_sm_state_reg[0]\ => DYNSHREG_F_I_n_0, + \FSM_sequential_sig_cmdcntl_sm_state_reg[0]_0\ => \FSM_sequential_sig_cmdcntl_sm_state_reg[0]\, + \FSM_sequential_sig_cmdcntl_sm_state_reg[2]\(2 downto 0) => \FSM_sequential_sig_cmdcntl_sm_state_reg[2]\(2 downto 0), + \GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg\ => \GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg\, + Q(2) => \^q\(0), + Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_1, + Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_2, + \in\(21 downto 0) => \in\(21 downto 0), + lsig_cmd_fetch_pause => lsig_cmd_fetch_pause, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\(20 downto 18) => \out\(19 downto 17), + \out\(17) => sig_cmd_fifo_data_out(25), + \out\(16 downto 0) => \out\(16 downto 0), + p_7_out => p_7_out, + p_9_out_0 => p_9_out_0, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + \sig_good_tlast_dbeat37_out__0\ => \sig_good_tlast_dbeat37_out__0\, + sig_inhibit_rdy_n_reg => sig_inhibit_rdy_n_reg, + sig_need_cmd_flush => sig_need_cmd_flush, + sig_sm_pop_cmd_fifo_ns => sig_sm_pop_cmd_fifo_ns, + sig_wr_fifo => sig_wr_fifo + ); +FIFO_Full_reg: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => fifo_full_p1, + Q => \^inferred_gen.cnt_i_reg[0]\, + R => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized8\ is + port ( + \INFERRED_GEN.cnt_i_reg[1]\ : out STD_LOGIC; + SS : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.lsig_first_dbeat_reg\ : out STD_LOGIC; + \sig_byte_cntr_reg[0]\ : out STD_LOGIC; + sig_dre2ibtt_tlast : out STD_LOGIC; + sig_cmd_full_reg : out STD_LOGIC; + sig_cmd_empty_reg : out STD_LOGIC; + \sig_good_tlast_dbeat37_out__0\ : out STD_LOGIC; + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + Q : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_s_ready_dup4_reg : out STD_LOGIC; + \sig_byte_cntr_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\ : out STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0]\ : out STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_eop_sent : out STD_LOGIC; + \GEN_INDET_BTT.lsig_absorb2tlast_reg\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg\ : out STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + \INCLUDE_PACKING.lsig_first_dbeat_reg_0\ : in STD_LOGIC; + sig_cmd_full : in STD_LOGIC; + sig_sm_ld_dre_cmd : in STD_LOGIC; + p_7_out : in STD_LOGIC; + sig_strm_tlast : in STD_LOGIC; + sig_m_valid_out_reg : in STD_LOGIC; + lsig_absorb2tlast : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_last_reg_out_reg : in STD_LOGIC; + sig_eop_halt_xfer : in STD_LOGIC; + sig_ibtt2dre_tready : in STD_LOGIC; + \out\ : in STD_LOGIC; + sig_clr_dbc_reg : in STD_LOGIC; + sig_eop_sent_reg : in STD_LOGIC; + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + sig_inhibit_rdy_n_reg : in STD_LOGIC; + slice_insert_valid : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0\ : in STD_LOGIC; + p_0_in : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0\ : in STD_LOGIC; + lsig_cmd_fetch_pause : in STD_LOGIC; + sig_need_cmd_flush : in STD_LOGIC; + sig_sm_pop_cmd_fifo : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized8\ : entity is "srl_fifo_rbu_f"; +end \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized8\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized8\ is + signal CNTR_INCR_DECR_ADDN_F_I_n_10 : STD_LOGIC; + signal CNTR_INCR_DECR_ADDN_F_I_n_11 : STD_LOGIC; + signal CNTR_INCR_DECR_ADDN_F_I_n_12 : STD_LOGIC; + signal CNTR_INCR_DECR_ADDN_F_I_n_9 : STD_LOGIC; + signal \^gen_indet_btt.lsig_absorb2tlast_reg\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^inferred_gen.cnt_i_reg[1]\ : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^ss\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal fifo_full_p1 : STD_LOGIC; + signal sig_tstrb_fifo_data_out : STD_LOGIC_VECTOR ( 3 to 3 ); + signal sig_wr_fifo : STD_LOGIC; +begin + \GEN_INDET_BTT.lsig_absorb2tlast_reg\(0) <= \^gen_indet_btt.lsig_absorb2tlast_reg\(0); + \INFERRED_GEN.cnt_i_reg[1]\ <= \^inferred_gen.cnt_i_reg[1]\; + Q(0) <= \^q\(0); + SS(0) <= \^ss\(0); +CNTR_INCR_DECR_ADDN_F_I: entity work.\Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f__parameterized2\ + port map ( + E(0) => E(0), + FIFO_Full_reg => \^inferred_gen.cnt_i_reg[1]\, + \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg\ => \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg\, + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1]\(1 downto 0) => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1]\(1 downto 0), + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0]\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\(1 downto 0) => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\(1 downto 0), + \INCLUDE_PACKING.lsig_first_dbeat_reg\ => \INCLUDE_PACKING.lsig_first_dbeat_reg\, + \INCLUDE_PACKING.lsig_first_dbeat_reg_0\ => \INCLUDE_PACKING.lsig_first_dbeat_reg_0\, + Q(4) => \^q\(0), + Q(3) => CNTR_INCR_DECR_ADDN_F_I_n_9, + Q(2) => CNTR_INCR_DECR_ADDN_F_I_n_10, + Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_11, + Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_12, + SR(0) => SR(0), + SS(0) => \^ss\(0), + fifo_full_p1 => fifo_full_p1, + lsig_absorb2tlast => lsig_absorb2tlast, + lsig_cmd_fetch_pause => lsig_cmd_fetch_pause, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\ => \out\, + p_7_out => p_7_out, + \sig_byte_cntr_reg[0]\ => \sig_byte_cntr_reg[0]\, + \sig_byte_cntr_reg[7]\(0) => \sig_byte_cntr_reg[7]\(0), + sig_clr_dbc_reg => sig_clr_dbc_reg, + sig_cmd_empty_reg => sig_cmd_empty_reg, + sig_cmd_full => sig_cmd_full, + sig_cmd_full_reg => sig_cmd_full_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_dre2ibtt_tlast => sig_dre2ibtt_tlast, + sig_eop_halt_xfer => sig_eop_halt_xfer, + sig_eop_sent => sig_eop_sent, + sig_eop_sent_reg => sig_eop_sent_reg, + \sig_good_tlast_dbeat37_out__0\ => \sig_good_tlast_dbeat37_out__0\, + sig_ibtt2dre_tready => sig_ibtt2dre_tready, + sig_inhibit_rdy_n_reg => sig_inhibit_rdy_n_reg, + sig_last_reg_out_reg => sig_last_reg_out_reg, + sig_m_valid_out_reg => sig_m_valid_out_reg, + sig_need_cmd_flush => sig_need_cmd_flush, + sig_s_ready_dup4_reg => sig_s_ready_dup4_reg, + sig_sm_ld_dre_cmd => sig_sm_ld_dre_cmd, + sig_sm_pop_cmd_fifo => sig_sm_pop_cmd_fifo, + sig_strm_tlast => sig_strm_tlast, + sig_wr_fifo => sig_wr_fifo, + slice_insert_valid => slice_insert_valid, + \storage_data_reg[3]\(1) => sig_tstrb_fifo_data_out(3), + \storage_data_reg[3]\(0) => \^gen_indet_btt.lsig_absorb2tlast_reg\(0) + ); +DYNSHREG_F_I: entity work.\Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized8\ + port map ( + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0\, + Q(4) => \^q\(0), + Q(3) => CNTR_INCR_DECR_ADDN_F_I_n_9, + Q(2) => CNTR_INCR_DECR_ADDN_F_I_n_10, + Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_11, + Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_12, + \in\(1 downto 0) => \in\(1 downto 0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\(1) => sig_tstrb_fifo_data_out(3), + \out\(0) => \^gen_indet_btt.lsig_absorb2tlast_reg\(0), + p_0_in => p_0_in, + sel => sig_wr_fifo, + sig_eop_halt_xfer => sig_eop_halt_xfer, + sig_m_valid_out_reg => sig_m_valid_out_reg, + sig_strm_tlast => sig_strm_tlast + ); +FIFO_Full_reg: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => fifo_full_p1, + Q => \^inferred_gen.cnt_i_reg[1]\, + R => \^ss\(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized9\ is + port ( + \INFERRED_GEN.cnt_i_reg[0]\ : out STD_LOGIC; + p_0_in : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 41 downto 0 ); + sig_calc_error_reg_reg : out STD_LOGIC; + \sig_clr_cmd2addr_valid3_out__0\ : out STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_halt_reg : in STD_LOGIC; + sig_addr_reg_empty_reg : in STD_LOGIC; + p_22_out : in STD_LOGIC; + sig_inhibit_rdy_n_reg : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 39 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized9\ : entity is "srl_fifo_rbu_f"; +end \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized9\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized9\ is + signal CNTR_INCR_DECR_ADDN_F_I_n_2 : STD_LOGIC; + signal CNTR_INCR_DECR_ADDN_F_I_n_3 : STD_LOGIC; + signal \^inferred_gen.cnt_i_reg[0]\ : STD_LOGIC; + signal fifo_full_p1 : STD_LOGIC; + signal sig_wr_fifo : STD_LOGIC; +begin + \INFERRED_GEN.cnt_i_reg[0]\ <= \^inferred_gen.cnt_i_reg[0]\; +CNTR_INCR_DECR_ADDN_F_I: entity work.Arty_Z7_20_axi_vdma_0_0_cntr_incr_decr_addn_f_18 + port map ( + FIFO_Full_reg => \^inferred_gen.cnt_i_reg[0]\, + Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_2, + Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_3, + fifo_full_p1 => fifo_full_p1, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + p_22_out => p_22_out, + sig_addr_reg_empty_reg => sig_addr_reg_empty_reg, + sig_calc_error_reg_reg => sig_calc_error_reg_reg, + sig_halt_reg => sig_halt_reg, + sig_inhibit_rdy_n_reg => sig_inhibit_rdy_n_reg, + sig_stream_rst => sig_stream_rst, + sig_wr_fifo => sig_wr_fifo + ); +DYNSHREG_F_I: entity work.\Arty_Z7_20_axi_vdma_0_0_dynshreg_f__parameterized9\ + port map ( + FIFO_Full_reg => \^inferred_gen.cnt_i_reg[0]\, + Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_2, + Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_3, + \in\(39 downto 0) => \in\(39 downto 0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\(41 downto 0) => \out\(41 downto 0), + p_0_in => p_0_in, + p_22_out => p_22_out, + sig_inhibit_rdy_n_reg => sig_inhibit_rdy_n_reg, + sig_wr_fifo => sig_wr_fifo + ); +FIFO_Full_reg: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => fifo_full_p1, + Q => \^inferred_gen.cnt_i_reg[0]\, + R => sig_stream_rst + ); +\sig_xfer_addr_reg[31]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => \^inferred_gen.cnt_i_reg[0]\, + I1 => sig_inhibit_rdy_n_reg, + I2 => p_22_out, + O => \sig_clr_cmd2addr_valid3_out__0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_width is + port ( + DOBDO : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : out STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[2]\ : out STD_LOGIC; + DIN : out STD_LOGIC_VECTOR ( 0 to 0 ); + dm2linebuf_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gc1.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \gcc0.gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + lsig_cmd_loaded : in STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ : in STD_LOGIC; + hold_ff_q : in STD_LOGIC; + \out\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; +end Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_width; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_width is +begin +\prim_noinit.ram\: entity work.Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_wrapper + port map ( + DIBDI(1 downto 0) => DIBDI(1 downto 0), + DIN(0) => DIN(0), + DOBDO(0) => DOBDO(0), + E(0) => E(0), + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, + \INFERRED_GEN.cnt_i_reg[2]\ => \INFERRED_GEN.cnt_i_reg[2]\, + Q(0) => Q(0), + SR(0) => SR(0), + dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), + \gc1.count_d2_reg[7]\(7 downto 0) => \gc1.count_d2_reg[7]\(7 downto 0), + \gcc0.gc0.count_d1_reg[7]\(7 downto 0) => \gcc0.gc0.count_d1_reg[7]\(7 downto 0), + \gpregsm1.curr_fwft_state_reg[0]\ => \gpregsm1.curr_fwft_state_reg[0]\, + hold_ff_q => hold_ff_q, + lsig_cmd_loaded => lsig_cmd_loaded, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axi_mm2s_rdata(63 downto 0) => m_axi_mm2s_rdata(63 downto 0), + \out\ => \out\, + \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ => \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_width__parameterized0\ is + port ( + sig_data_fifo_data_out : out STD_LOGIC_VECTOR ( 65 downto 0 ); + m_axi_s2mm_aclk : in STD_LOGIC; + ram_empty_fb_i_reg : in STD_LOGIC; + WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_s_ready_out_reg : in STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + \gc1.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 7 downto 0 ); + lsig_combined_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); + DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width"; +end \Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_width__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_width__parameterized0\ is +begin +\prim_noinit.ram\: entity work.\Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_wrapper__parameterized0\ + port map ( + DIBDI(1 downto 0) => DIBDI(1 downto 0), + Q(7 downto 0) => Q(7 downto 0), + WEBWE(0) => WEBWE(0), + \gc1.count_d2_reg[7]\(7 downto 0) => \gc1.count_d2_reg[7]\(7 downto 0), + lsig_combined_data(63 downto 0) => lsig_combined_data(63 downto 0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + ram_empty_fb_i_reg => ram_empty_fb_i_reg, + sig_data_fifo_data_out(65 downto 0) => sig_data_fifo_data_out(65 downto 0), + sig_s_ready_out_reg => sig_s_ready_out_reg, + sig_stream_rst => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6 is + port ( + sig_m_valid_out_reg : out STD_LOGIC; + EMPTY : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ : out STD_LOGIC; + fifo_dout : out STD_LOGIC_VECTOR ( 17 downto 0 ); + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\ : in STD_LOGIC; + m_axis_mm2s_aclk : in STD_LOGIC; + RD_EN : in STD_LOGIC; + RST : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + WR_EN : in STD_LOGIC; + dm2linebuf_mm2s_tdata : in STD_LOGIC_VECTOR ( 17 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6 : entity is "builtin_extdepth_v6"; +end Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6 is + signal NLW_i_0_O_UNCONNECTED : STD_LOGIC; + signal NLW_i_1_O_UNCONNECTED : STD_LOGIC; + signal NLW_i_2_O_UNCONNECTED : STD_LOGIC; + signal NLW_i_3_O_UNCONNECTED : STD_LOGIC; +begin +\gonep.inst_prim\: entity work.Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6_41 + port map ( + EMPTY => EMPTY, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\, + RD_EN => RD_EN, + RST => RST, + WR_EN => WR_EN, + dm2linebuf_mm2s_tdata(17 downto 0) => dm2linebuf_mm2s_tdata(17 downto 0), + fifo_dout(17 downto 0) => fifo_dout(17 downto 0), + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axis_mm2s_aclk => m_axis_mm2s_aclk, + sig_m_valid_out_reg => sig_m_valid_out_reg + ); +i_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => NLW_i_0_O_UNCONNECTED + ); +i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => NLW_i_1_O_UNCONNECTED + ); +i_2: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => NLW_i_2_O_UNCONNECTED + ); +i_3: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => NLW_i_3_O_UNCONNECTED + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_40 is + port ( + RD_EN : out STD_LOGIC; + EMPTY : out STD_LOGIC; + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ : out STD_LOGIC; + FULL : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\ : out STD_LOGIC; + fifo_dout : out STD_LOGIC_VECTOR ( 15 downto 0 ); + \out\ : in STD_LOGIC; + sig_s_ready_out_reg : in STD_LOGIC; + lsig_0ffset_cntr : in STD_LOGIC; + sig_s_ready_out_reg_0 : in STD_LOGIC; + mm2s_prmry_resetn : in STD_LOGIC; + mm2s_halt : in STD_LOGIC; + p_24_out : in STD_LOGIC; + hold_ff_q_reg : in STD_LOGIC; + DIN : in STD_LOGIC_VECTOR ( 15 downto 0 ); + m_axis_mm2s_aclk : in STD_LOGIC; + RST : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + WR_EN : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_40 : entity is "builtin_extdepth_v6"; +end Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_40; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_40 is + signal NLW_i_0_O_UNCONNECTED : STD_LOGIC; + signal NLW_i_1_O_UNCONNECTED : STD_LOGIC; + signal NLW_i_2_O_UNCONNECTED : STD_LOGIC; + signal NLW_i_3_O_UNCONNECTED : STD_LOGIC; +begin +\gonep.inst_prim\: entity work.Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6 + port map ( + DIN(15 downto 0) => DIN(15 downto 0), + EMPTY => EMPTY, + FULL => FULL, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, + RD_EN => RD_EN, + RST => RST, + WR_EN => WR_EN, + fifo_dout(15 downto 0) => fifo_dout(15 downto 0), + hold_ff_q_reg => hold_ff_q_reg, + lsig_0ffset_cntr => lsig_0ffset_cntr, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axis_mm2s_aclk => m_axis_mm2s_aclk, + mm2s_halt => mm2s_halt, + mm2s_prmry_resetn => mm2s_prmry_resetn, + \out\ => \out\, + p_24_out => p_24_out, + sig_s_ready_out_reg => sig_s_ready_out_reg, + sig_s_ready_out_reg_0 => sig_s_ready_out_reg_0 + ); +i_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => NLW_i_0_O_UNCONNECTED + ); +i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => NLW_i_1_O_UNCONNECTED + ); +i_2: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => NLW_i_2_O_UNCONNECTED + ); +i_3: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => NLW_i_3_O_UNCONNECTED + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6__parameterized0\ is + port ( + FULL : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 12 downto 0 ); + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]\ : out STD_LOGIC; + DOUT : out STD_LOGIC_VECTOR ( 8 downto 0 ); + EMPTY : out STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\ : out STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\ : out STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\ : out STD_LOGIC; + strm_not_finished_no_dwidth : out STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); + M_VALID : in STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\ : in STD_LOGIC; + s2mm_fsync_out_i : in STD_LOGIC; + \out\ : in STD_LOGIC; + p_3_out : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 6 downto 0 ); + \vsize_vid_reg[12]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : in STD_LOGIC; + minusOp_1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0\ : in STD_LOGIC; + s2mm_strm_wready : in STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + DIN : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\ : in STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + minusOp : in STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_s2mm_aclk : in STD_LOGIC; + RD_EN : in STD_LOGIC; + RST : in STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6__parameterized0\ : entity is "builtin_extdepth_v6"; +end \Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6__parameterized0\ is + signal NLW_i_0_O_UNCONNECTED : STD_LOGIC; + signal NLW_i_1_O_UNCONNECTED : STD_LOGIC; + signal NLW_i_2_O_UNCONNECTED : STD_LOGIC; + signal NLW_i_3_O_UNCONNECTED : STD_LOGIC; +begin +\gonep.inst_prim\: entity work.\Arty_Z7_20_axi_vdma_0_0_builtin_prim_v6__parameterized0\ + port map ( + D(12 downto 0) => D(12 downto 0), + DIN(8 downto 0) => DIN(8 downto 0), + DOUT(8 downto 0) => DOUT(8 downto 0), + EMPTY => EMPTY, + FULL => FULL, + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\, + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\(12 downto 0) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\(12 downto 0), + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]\ => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]\, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0\ => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0\, + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\ => \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0]\(0) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0]\(0), + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\(12 downto 0) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\(12 downto 0), + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\, + M_VALID => M_VALID, + Q(6 downto 0) => Q(6 downto 0), + RD_EN => RD_EN, + RST => RST, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + minusOp(11 downto 0) => minusOp(11 downto 0), + minusOp_1(11 downto 0) => minusOp_1(11 downto 0), + \out\ => \out\, + p_3_out => p_3_out, + s2mm_fsync_out_i => s2mm_fsync_out_i, + s2mm_strm_wready => s2mm_strm_wready, + s_axis_s2mm_aclk => s_axis_s2mm_aclk, + strm_not_finished_no_dwidth => strm_not_finished_no_dwidth, + \vsize_vid_reg[12]\(12 downto 0) => \vsize_vid_reg[12]\(12 downto 0) + ); +i_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => NLW_i_0_O_UNCONNECTED + ); +i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => NLW_i_1_O_UNCONNECTED + ); +i_2: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => NLW_i_2_O_UNCONNECTED + ); +i_3: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => NLW_i_3_O_UNCONNECTED + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_dc_ss is + port ( + sig_ok_to_post_rd_addr_reg : out STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_posted_to_axi_2_reg : in STD_LOGIC; + ram_empty_fb_i_reg : in STD_LOGIC; + \sig_token_cntr_reg[0]\ : in STD_LOGIC; + \sig_token_cntr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + sig_posted_to_axi_2_reg_0 : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + ram_full_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_dc_ss : entity is "dc_ss"; +end Arty_Z7_20_axi_vdma_0_0_dc_ss; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_dc_ss is +begin +\gsym_dc.dc\: entity work.Arty_Z7_20_axi_vdma_0_0_updn_cntr + port map ( + SR(0) => SR(0), + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + ram_empty_fb_i_reg => ram_empty_fb_i_reg, + ram_full_i_reg(0) => ram_full_i_reg(0), + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_ok_to_post_rd_addr_reg => sig_ok_to_post_rd_addr_reg, + sig_posted_to_axi_2_reg => sig_posted_to_axi_2_reg, + sig_posted_to_axi_2_reg_0 => sig_posted_to_axi_2_reg_0, + \sig_token_cntr_reg[0]\ => \sig_token_cntr_reg[0]\, + \sig_token_cntr_reg[3]\(3 downto 0) => \sig_token_cntr_reg[3]\(3 downto 0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_dc_ss__parameterized0\ is + port ( + sig_ibtt2dre_tready : out STD_LOGIC; + lsig_packer_full : in STD_LOGIC; + ram_full_i_reg : in STD_LOGIC; + ram_full_i_reg_0 : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + ram_full_fb_i_reg : in STD_LOGIC; + sig_clr_dbc_reg_reg : in STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_dc_ss__parameterized0\ : entity is "dc_ss"; +end \Arty_Z7_20_axi_vdma_0_0_dc_ss__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_dc_ss__parameterized0\ is +begin +\gsym_dc.dc\: entity work.\Arty_Z7_20_axi_vdma_0_0_updn_cntr__parameterized0\ + port map ( + E(0) => E(0), + lsig_packer_full => lsig_packer_full, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + ram_full_fb_i_reg => ram_full_fb_i_reg, + ram_full_i_reg => ram_full_i_reg, + ram_full_i_reg_0 => ram_full_i_reg_0, + sig_clr_dbc_reg_reg => sig_clr_dbc_reg_reg, + sig_ibtt2dre_tready => sig_ibtt2dre_tready, + sig_stream_rst => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_memory__parameterized0\ is + port ( + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_xfer_is_seq_reg_reg : out STD_LOGIC_VECTOR ( 9 downto 0 ); + \sig_child_addr_cntr_lsh_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + S : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \sig_xfer_len_reg_reg[4]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \sig_xfer_len_reg_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_xfer_is_seq_reg_reg_0 : out STD_LOGIC; + sig_xfer_cmd_cmplt_reg0 : out STD_LOGIC; + sig_csm_state_ns1 : out STD_LOGIC; + O : out STD_LOGIC_VECTOR ( 3 downto 0 ); + CO : out STD_LOGIC_VECTOR ( 0 to 0 ); + \sig_child_addr_cntr_lsh_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + sig_adjusted_addr_incr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + sig_csm_pop_child_cmd : in STD_LOGIC; + sig_child_qual_first_of_2 : in STD_LOGIC; + sig_child_qual_error_reg : in STD_LOGIC; + \gpr1.dout_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \gpr1.dout_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + sig_child_addr_cntr_lsh_reg : in STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_stream_rst : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + p_0_out : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_memory__parameterized0\ : entity is "memory"; +end \Arty_Z7_20_axi_vdma_0_0_memory__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_memory__parameterized0\ is +begin +\gdm.dm_gen.dm\: entity work.Arty_Z7_20_axi_vdma_0_0_dmem + port map ( + CO(0) => CO(0), + D(2 downto 0) => D(2 downto 0), + E(0) => E(0), + O(3 downto 0) => O(3 downto 0), + S(3 downto 0) => S(3 downto 0), + \gpr1.dout_i_reg[3]_0\(3 downto 0) => \gpr1.dout_i_reg[3]\(3 downto 0), + \gpr1.dout_i_reg[7]_0\(3 downto 0) => \gpr1.dout_i_reg[7]\(3 downto 0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + p_0_out(10 downto 0) => p_0_out(10 downto 0), + sig_adjusted_addr_incr(8 downto 0) => sig_adjusted_addr_incr(8 downto 0), + sig_child_addr_cntr_lsh_reg(2 downto 0) => sig_child_addr_cntr_lsh_reg(2 downto 0), + \sig_child_addr_cntr_lsh_reg[11]\(0) => \sig_child_addr_cntr_lsh_reg[11]\(0), + \sig_child_addr_cntr_lsh_reg[7]\(3 downto 0) => \sig_child_addr_cntr_lsh_reg[7]\(3 downto 0), + sig_child_qual_error_reg => sig_child_qual_error_reg, + sig_child_qual_first_of_2 => sig_child_qual_first_of_2, + sig_csm_pop_child_cmd => sig_csm_pop_child_cmd, + sig_csm_state_ns1 => sig_csm_state_ns1, + sig_stream_rst => sig_stream_rst, + sig_xfer_cmd_cmplt_reg0 => sig_xfer_cmd_cmplt_reg0, + sig_xfer_is_seq_reg_reg(9 downto 0) => sig_xfer_is_seq_reg_reg(9 downto 0), + sig_xfer_is_seq_reg_reg_0 => sig_xfer_is_seq_reg_reg_0, + \sig_xfer_len_reg_reg[4]\(3 downto 0) => \sig_xfer_len_reg_reg[4]\(3 downto 0), + \sig_xfer_len_reg_reg[5]\(0) => \sig_xfer_len_reg_reg[5]\(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_rd_logic is + port ( + \out\ : out STD_LOGIC; + \gpregsm1.user_valid_reg\ : out STD_LOGIC; + hold_ff_q_reg : out STD_LOGIC; + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC; + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0\ : out STD_LOGIC; + p_7_out : out STD_LOGIC; + sig_data_fifo_dvalid : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 7 downto 0 ); + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_1\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + \ram_empty_i0__3\ : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + hold_ff_q_reg_0 : in STD_LOGIC; + sig_s_ready_out_reg : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_rd_logic : entity is "rd_logic"; +end Arty_Z7_20_axi_vdma_0_0_rd_logic; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_rd_logic is + signal \^out\ : STD_LOGIC; + signal \^p_7_out\ : STD_LOGIC; +begin + \out\ <= \^out\; + p_7_out <= \^p_7_out\; +\gr1.gr1_int.rfwft\: entity work.Arty_Z7_20_axi_vdma_0_0_rd_fwft + port map ( + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\, + E(0) => \^p_7_out\, + hold_ff_q_reg => hold_ff_q_reg, + hold_ff_q_reg_0 => hold_ff_q_reg_0, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\ => \gpregsm1.user_valid_reg\, + ram_empty_fb_i_reg => \^out\, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_data_fifo_dvalid => sig_data_fifo_dvalid, + sig_s_ready_out_reg => sig_s_ready_out_reg, + sig_stream_rst => sig_stream_rst + ); +\grss.rsts\: entity work.Arty_Z7_20_axi_vdma_0_0_rd_status_flags_ss + port map ( + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0\, + E(0) => \^p_7_out\, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\ => \^out\, + \ram_empty_i0__3\ => \ram_empty_i0__3\, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_stream_rst => sig_stream_rst + ); +rpntr: entity work.Arty_Z7_20_axi_vdma_0_0_rd_bin_cntr + port map ( + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(7 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_1\(7 downto 0), + E(0) => \^p_7_out\, + Q(7 downto 0) => Q(7 downto 0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + sig_stream_rst => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_wr_logic is + port ( + \out\ : out STD_LOGIC; + \INCLUDE_PACKING.lsig_packer_full_reg\ : out STD_LOGIC; + WEBWE : out STD_LOGIC_VECTOR ( 0 to 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \ram_empty_i0__3\ : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 7 downto 0 ); + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + \lsig_set_packer_full__1\ : in STD_LOGIC; + lsig_packer_full : in STD_LOGIC; + p_7_out : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4\ : in STD_LOGIC; + ram_empty_fb_i_reg : in STD_LOGIC; + \gc1.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \gc1.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_wr_logic : entity is "wr_logic"; +end Arty_Z7_20_axi_vdma_0_0_wr_logic; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_wr_logic is + signal \^webwe\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \gwss.wsts_n_0\ : STD_LOGIC; + signal \^out\ : STD_LOGIC; + signal wpntr_n_0 : STD_LOGIC; +begin + WEBWE(0) <= \^webwe\(0); + \out\ <= \^out\; +\gwss.wsts\: entity work.Arty_Z7_20_axi_vdma_0_0_wr_status_flags_ss + port map ( + E(0) => \^webwe\(0), + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][0]\(0) => E(0), + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0\, + \INCLUDE_PACKING.lsig_packer_full_reg\ => \INCLUDE_PACKING.lsig_packer_full_reg\, + \gcc0.gc0.count_d1_reg[7]\ => \^out\, + lsig_packer_full => lsig_packer_full, + \lsig_set_packer_full__1\ => \lsig_set_packer_full__1\, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\ => \gwss.wsts_n_0\, + ram_full_i_reg_0 => wpntr_n_0, + sig_stream_rst => sig_stream_rst + ); +wpntr: entity work.Arty_Z7_20_axi_vdma_0_0_wr_bin_cntr + port map ( + E(0) => \^webwe\(0), + Q(7 downto 0) => Q(7 downto 0), + \gc1.count_d1_reg[7]\(7 downto 0) => \gc1.count_d1_reg[7]\(7 downto 0), + \gc1.count_d2_reg[7]\(7 downto 0) => \gc1.count_d2_reg[7]\(7 downto 0), + lsig_packer_full => lsig_packer_full, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\ => \^out\, + p_7_out => p_7_out, + ram_empty_fb_i_reg => ram_empty_fb_i_reg, + \ram_empty_i0__3\ => \ram_empty_i0__3\, + ram_full_fb_i_reg => \gwss.wsts_n_0\, + ram_full_i_reg => wpntr_n_0, + sig_stream_rst => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_wr_logic_31 is + port ( + \out\ : out STD_LOGIC; + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC; + sig_ok_to_post_rd_addr_reg : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 7 downto 0 ); + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); + \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + sig_posted_to_axi_2_reg : in STD_LOGIC; + \sig_token_cntr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_wr_logic_31 : entity is "wr_logic"; +end Arty_Z7_20_axi_vdma_0_0_wr_logic_31; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_wr_logic_31 is +begin +\gwss.wsts\: entity work.Arty_Z7_20_axi_vdma_0_0_wr_status_flags_ss_32 + port map ( + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + \out\ => \out\, + \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ => \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\, + sig_ok_to_post_rd_addr_reg => sig_ok_to_post_rd_addr_reg, + sig_posted_to_axi_2_reg => sig_posted_to_axi_2_reg, + \sig_token_cntr_reg[3]\(3 downto 0) => \sig_token_cntr_reg[3]\(3 downto 0) + ); +wpntr: entity work.Arty_Z7_20_axi_vdma_0_0_wr_bin_cntr_33 + port map ( + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(7 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0\(7 downto 0), + E(0) => E(0), + Q(7 downto 0) => Q(7 downto 0), + SR(0) => SR(0), + m_axi_mm2s_aclk => m_axi_mm2s_aclk + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_wr_logic__parameterized0\ is + port ( + \out\ : out STD_LOGIC; + \sig_byte_cntr_reg[0]\ : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \ram_empty_i0__3\ : out STD_LOGIC; + \gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_clr_dbc_reg_reg : in STD_LOGIC; + \gv.ram_valid_d1_reg\ : in STD_LOGIC; + ram_empty_fb_i_reg : in STD_LOGIC; + \gc1.count_d2_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 2 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_wr_logic__parameterized0\ : entity is "wr_logic"; +end \Arty_Z7_20_axi_vdma_0_0_wr_logic__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_wr_logic__parameterized0\ is + signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^out\ : STD_LOGIC; + signal wpntr_n_0 : STD_LOGIC; +begin + E(0) <= \^e\(0); + \out\ <= \^out\; +\gwss.wsts\: entity work.\Arty_Z7_20_axi_vdma_0_0_wr_status_flags_ss__parameterized0\ + port map ( + E(0) => \^e\(0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\ => \^out\, + \sig_byte_cntr_reg[0]\ => \sig_byte_cntr_reg[0]\, + sig_clr_dbc_reg_reg => wpntr_n_0, + sig_clr_dbc_reg_reg_0 => sig_clr_dbc_reg_reg, + sig_stream_rst => sig_stream_rst + ); +wpntr: entity work.\Arty_Z7_20_axi_vdma_0_0_wr_bin_cntr__parameterized0\ + port map ( + E(0) => \^e\(0), + Q(2 downto 0) => Q(2 downto 0), + \gc1.count_d2_reg[2]\(2 downto 0) => \gc1.count_d2_reg[2]\(2 downto 0), + \gpr1.dout_i_reg[1]\(2 downto 0) => \gpr1.dout_i_reg[1]\(2 downto 0), + \gv.ram_valid_d1_reg\ => \gv.ram_valid_d1_reg\, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\ => \^out\, + ram_empty_fb_i_reg => ram_empty_fb_i_reg, + \ram_empty_i0__3\ => \ram_empty_i0__3\, + ram_full_i_reg => wpntr_n_0, + sig_clr_dbc_reg_reg => sig_clr_dbc_reg_reg, + sig_stream_rst => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_mngr is + port ( + cmnd_wr : out STD_LOGIC; + p_58_out : out STD_LOGIC; + p_37_out : out STD_LOGIC; + prmtr_update_complete : out STD_LOGIC; + p_45_out : out STD_LOGIC; + stop : out STD_LOGIC; + p_50_out : out STD_LOGIC; + p_56_out : out STD_LOGIC; + datamover_idle : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 12 downto 0 ); + p_39_out : out STD_LOGIC; + p_47_out : out STD_LOGIC; + dma_err : out STD_LOGIC; + \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + p_2_out : out STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[1]\ : out STD_LOGIC; + halted_reg : out STD_LOGIC; + dma_interr_reg : out STD_LOGIC; + dma_slverr_reg : out STD_LOGIC; + dma_decerr_reg : out STD_LOGIC; + \sig_addr_cntr_lsh_kh_reg[31]\ : out STD_LOGIC_VECTOR ( 48 downto 0 ); + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + initial_frame : out STD_LOGIC; + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + mm2s_all_lines_xfred : in STD_LOGIC; + mm2s_prmry_resetn : in STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[2]\ : in STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[2]_0\ : in STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[2]_1\ : in STD_LOGIC; + p_71_out : in STD_LOGIC_VECTOR ( 1 downto 0 ); + prmtr_updt_complete_i_reg : in STD_LOGIC; + p_46_out : in STD_LOGIC; + halted_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_halt_cmplt_reg : in STD_LOGIC; + p_24_out : in STD_LOGIC; + mm2s_fifo_pipe_empty : in STD_LOGIC; + p_67_out : in STD_LOGIC; + \dmacr_i_reg[2]\ : in STD_LOGIC; + p_77_out : in STD_LOGIC; + mm2s_halt : in STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[2]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \ptr_ref_i_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + p_70_out : in STD_LOGIC; + mask_fsync_out_i : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 0 to 0 ); + mm2s_axi2ip_wrce : in STD_LOGIC_VECTOR ( 0 to 0 ); + dma_interr_reg_0 : in STD_LOGIC; + dma_slverr_reg_0 : in STD_LOGIC; + dma_decerr_reg_0 : in STD_LOGIC; + \reg_module_vsize_reg[12]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + \reg_module_hsize_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + prmry_resetn_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + err_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_mngr : entity is "axi_vdma_mngr"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_mngr; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_mngr is + signal I_CMDSTS_n_1 : STD_LOGIC; + signal I_CMDSTS_n_3 : STD_LOGIC; + signal I_SM_n_25 : STD_LOGIC; + signal I_SM_n_26 : STD_LOGIC; + signal I_SM_n_27 : STD_LOGIC; + signal I_SM_n_28 : STD_LOGIC; + signal I_SM_n_29 : STD_LOGIC; + signal I_SM_n_30 : STD_LOGIC; + signal I_SM_n_31 : STD_LOGIC; + signal I_SM_n_32 : STD_LOGIC; + signal I_SM_n_33 : STD_LOGIC; + signal I_SM_n_34 : STD_LOGIC; + signal I_SM_n_35 : STD_LOGIC; + signal I_SM_n_36 : STD_LOGIC; + signal I_SM_n_37 : STD_LOGIC; + signal I_SM_n_38 : STD_LOGIC; + signal I_SM_n_39 : STD_LOGIC; + signal I_SM_n_40 : STD_LOGIC; + signal I_SM_n_41 : STD_LOGIC; + signal I_SM_n_42 : STD_LOGIC; + signal I_SM_n_43 : STD_LOGIC; + signal I_SM_n_44 : STD_LOGIC; + signal I_SM_n_45 : STD_LOGIC; + signal I_SM_n_46 : STD_LOGIC; + signal I_SM_n_47 : STD_LOGIC; + signal I_SM_n_48 : STD_LOGIC; + signal I_SM_n_49 : STD_LOGIC; + signal I_SM_n_50 : STD_LOGIC; + signal I_SM_n_51 : STD_LOGIC; + signal I_SM_n_52 : STD_LOGIC; + signal I_SM_n_53 : STD_LOGIC; + signal I_SM_n_54 : STD_LOGIC; + signal I_SM_n_55 : STD_LOGIC; + signal I_SM_n_56 : STD_LOGIC; + signal I_SM_n_57 : STD_LOGIC; + signal I_SM_n_58 : STD_LOGIC; + signal I_SM_n_59 : STD_LOGIC; + signal I_SM_n_60 : STD_LOGIC; + signal I_SM_n_61 : STD_LOGIC; + signal I_SM_n_62 : STD_LOGIC; + signal I_SM_n_63 : STD_LOGIC; + signal I_SM_n_64 : STD_LOGIC; + signal I_SM_n_65 : STD_LOGIC; + signal I_SM_n_66 : STD_LOGIC; + signal I_SM_n_67 : STD_LOGIC; + signal I_SM_n_68 : STD_LOGIC; + signal I_SM_n_69 : STD_LOGIC; + signal I_SM_n_70 : STD_LOGIC; + signal I_SM_n_71 : STD_LOGIC; + signal I_SM_n_72 : STD_LOGIC; + signal I_SM_n_73 : STD_LOGIC; + signal \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \MASTER_MODE_FRAME_CNT.frame_number_i[0]_i_1_n_0\ : STD_LOGIC; + signal \MASTER_MODE_FRAME_CNT.frame_number_i[1]_i_1_n_0\ : STD_LOGIC; + signal \MASTER_MODE_FRAME_CNT.frame_number_i[2]_i_1_n_0\ : STD_LOGIC; + signal \MASTER_MODE_FRAME_CNT.frame_number_i[3]_i_1_n_0\ : STD_LOGIC; + signal \MASTER_MODE_FRAME_CNT.frame_number_i[3]_i_2_n_0\ : STD_LOGIC; + signal \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_3_n_0\ : STD_LOGIC; + signal \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_5_n_0\ : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal VIDEO_GENLOCK_I_n_1 : STD_LOGIC; + signal VIDEO_REG_I_n_32 : STD_LOGIC; + signal VIDEO_REG_I_n_35 : STD_LOGIC; + signal VIDEO_REG_I_n_36 : STD_LOGIC; + signal VIDEO_REG_I_n_37 : STD_LOGIC; + signal VIDEO_REG_I_n_38 : STD_LOGIC; + signal VIDEO_REG_I_n_39 : STD_LOGIC; + signal VIDEO_REG_I_n_40 : STD_LOGIC; + signal VIDEO_REG_I_n_41 : STD_LOGIC; + signal VIDEO_REG_I_n_42 : STD_LOGIC; + signal VIDEO_REG_I_n_43 : STD_LOGIC; + signal VIDEO_REG_I_n_44 : STD_LOGIC; + signal VIDEO_REG_I_n_45 : STD_LOGIC; + signal VIDEO_REG_I_n_46 : STD_LOGIC; + signal VIDEO_REG_I_n_47 : STD_LOGIC; + signal VIDEO_REG_I_n_48 : STD_LOGIC; + signal VIDEO_REG_I_n_49 : STD_LOGIC; + signal VIDEO_REG_I_n_50 : STD_LOGIC; + signal VIDEO_REG_I_n_51 : STD_LOGIC; + signal VIDEO_REG_I_n_52 : STD_LOGIC; + signal VIDEO_REG_I_n_53 : STD_LOGIC; + signal VIDEO_REG_I_n_54 : STD_LOGIC; + signal VIDEO_REG_I_n_55 : STD_LOGIC; + signal VIDEO_REG_I_n_56 : STD_LOGIC; + signal VIDEO_REG_I_n_57 : STD_LOGIC; + signal VIDEO_REG_I_n_58 : STD_LOGIC; + signal VIDEO_REG_I_n_59 : STD_LOGIC; + signal VIDEO_REG_I_n_60 : STD_LOGIC; + signal VIDEO_REG_I_n_61 : STD_LOGIC; + signal VIDEO_REG_I_n_62 : STD_LOGIC; + signal VIDEO_REG_I_n_63 : STD_LOGIC; + signal VIDEO_REG_I_n_64 : STD_LOGIC; + signal VIDEO_REG_I_n_65 : STD_LOGIC; + signal VIDEO_REG_I_n_66 : STD_LOGIC; + signal VIDEO_REG_I_n_67 : STD_LOGIC; + signal VIDEO_REG_I_n_68 : STD_LOGIC; + signal \^cmnd_wr\ : STD_LOGIC; + signal crnt_hsize : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \^datamover_idle\ : STD_LOGIC; + signal dm_address_reg : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \^dma_err\ : STD_LOGIC; + signal frame_sync_reg : STD_LOGIC; + signal halted_set_i0 : STD_LOGIC; + signal \^initial_frame\ : STD_LOGIC; + signal initial_frame_i_1_n_0 : STD_LOGIC; + signal load_new_addr : STD_LOGIC; + signal num_fstore_minus1 : STD_LOGIC_VECTOR ( 1 to 1 ); + signal p_10_out : STD_LOGIC; + signal \^p_39_out\ : STD_LOGIC; + signal \^p_47_out\ : STD_LOGIC; + signal \^p_56_out\ : STD_LOGIC; + signal \^p_58_out\ : STD_LOGIC; + signal stop_i : STD_LOGIC; + signal tstvect_fsync_d1 : STD_LOGIC; + signal tstvect_fsync_d2 : STD_LOGIC; + signal valid_frame_sync_d1 : STD_LOGIC; + signal valid_frame_sync_d2 : STD_LOGIC; + signal zero_hsize_err : STD_LOGIC; + signal zero_hsize_err0 : STD_LOGIC; + signal zero_vsize_err : STD_LOGIC; + signal zero_vsize_err0 : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \MASTER_MODE_FRAME_CNT.frame_number_i[0]_i_1\ : label is "soft_lutpair43"; + attribute SOFT_HLUTNM of \MASTER_MODE_FRAME_CNT.frame_number_i[3]_i_2\ : label is "soft_lutpair43"; +begin + \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0\(4 downto 0) <= \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(4 downto 0); + Q(12 downto 0) <= \^q\(12 downto 0); + cmnd_wr <= \^cmnd_wr\; + datamover_idle <= \^datamover_idle\; + dma_err <= \^dma_err\; + initial_frame <= \^initial_frame\; + p_39_out <= \^p_39_out\; + p_47_out <= \^p_47_out\; + p_56_out <= \^p_56_out\; + p_58_out <= \^p_58_out\; +I_CMDSTS: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_cmdsts_if + port map ( + D(48) => I_SM_n_25, + D(47) => I_SM_n_26, + D(46) => I_SM_n_27, + D(45) => I_SM_n_28, + D(44) => I_SM_n_29, + D(43) => I_SM_n_30, + D(42) => I_SM_n_31, + D(41) => I_SM_n_32, + D(40) => I_SM_n_33, + D(39) => I_SM_n_34, + D(38) => I_SM_n_35, + D(37) => I_SM_n_36, + D(36) => I_SM_n_37, + D(35) => I_SM_n_38, + D(34) => I_SM_n_39, + D(33) => I_SM_n_40, + D(32) => I_SM_n_41, + D(31) => I_SM_n_42, + D(30) => I_SM_n_43, + D(29) => I_SM_n_44, + D(28) => I_SM_n_45, + D(27) => I_SM_n_46, + D(26) => I_SM_n_47, + D(25) => I_SM_n_48, + D(24) => I_SM_n_49, + D(23) => I_SM_n_50, + D(22) => I_SM_n_51, + D(21) => I_SM_n_52, + D(20) => I_SM_n_53, + D(19) => I_SM_n_54, + D(18) => I_SM_n_55, + D(17) => I_SM_n_56, + D(16) => I_SM_n_57, + D(15) => I_SM_n_58, + D(14) => I_SM_n_59, + D(13) => I_SM_n_60, + D(12) => I_SM_n_61, + D(11) => I_SM_n_62, + D(10) => I_SM_n_63, + D(9) => I_SM_n_64, + D(8) => I_SM_n_65, + D(7) => I_SM_n_66, + D(6) => I_SM_n_67, + D(5) => I_SM_n_68, + D(4) => I_SM_n_69, + D(3) => I_SM_n_70, + D(2) => I_SM_n_71, + D(1) => I_SM_n_72, + D(0) => I_SM_n_73, + E(0) => E(0), + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ => I_CMDSTS_n_3, + \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg\ => \^p_56_out\, + \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg_0\ => \^cmnd_wr\, + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\ => \^p_47_out\, + \INFERRED_GEN.cnt_i_reg[1]\ => \INFERRED_GEN.cnt_i_reg[1]\, + \INFERRED_GEN.cnt_i_reg[2]\ => \INFERRED_GEN.cnt_i_reg[2]\, + \INFERRED_GEN.cnt_i_reg[2]_0\ => \INFERRED_GEN.cnt_i_reg[2]_0\, + \INFERRED_GEN.cnt_i_reg[2]_1\ => \INFERRED_GEN.cnt_i_reg[2]_1\, + \INFERRED_GEN.cnt_i_reg[2]_2\(0) => \INFERRED_GEN.cnt_i_reg[2]_2\(0), + SR(0) => SR(0), + \cmnds_queued_reg[0]\ => \^p_58_out\, + dma_decerr_reg => dma_decerr_reg, + dma_decerr_reg_0 => dma_decerr_reg_0, + dma_slverr_reg => dma_slverr_reg, + dma_slverr_reg_0 => dma_slverr_reg_0, + err_i_reg_0 => I_CMDSTS_n_1, + frame_sync_reg => frame_sync_reg, + halted_reg(0) => halted_reg_0(0), + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + mm2s_halt => mm2s_halt, + mm2s_prmry_resetn => mm2s_prmry_resetn, + p_71_out(0) => p_71_out(0), + p_77_out => p_77_out, + \sig_addr_cntr_lsh_kh_reg[31]\(48 downto 0) => \sig_addr_cntr_lsh_kh_reg[31]\(48 downto 0), + stop_i => stop_i, + stop_reg => \^dma_err\, + zero_hsize_err => zero_hsize_err, + zero_vsize_err => zero_vsize_err + ); +I_SM: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_sm + port map ( + CO(0) => VIDEO_REG_I_n_64, + D(48) => I_SM_n_25, + D(47) => I_SM_n_26, + D(46) => I_SM_n_27, + D(45) => I_SM_n_28, + D(44) => I_SM_n_29, + D(43) => I_SM_n_30, + D(42) => I_SM_n_31, + D(41) => I_SM_n_32, + D(40) => I_SM_n_33, + D(39) => I_SM_n_34, + D(38) => I_SM_n_35, + D(37) => I_SM_n_36, + D(36) => I_SM_n_37, + D(35) => I_SM_n_38, + D(34) => I_SM_n_39, + D(33) => I_SM_n_40, + D(32) => I_SM_n_41, + D(31) => I_SM_n_42, + D(30) => I_SM_n_43, + D(29) => I_SM_n_44, + D(28) => I_SM_n_45, + D(27) => I_SM_n_46, + D(26) => I_SM_n_47, + D(25) => I_SM_n_48, + D(24) => I_SM_n_49, + D(23) => I_SM_n_50, + D(22) => I_SM_n_51, + D(21) => I_SM_n_52, + D(20) => I_SM_n_53, + D(19) => I_SM_n_54, + D(18) => I_SM_n_55, + D(17) => I_SM_n_56, + D(16) => I_SM_n_57, + D(15) => I_SM_n_58, + D(14) => I_SM_n_59, + D(13) => I_SM_n_60, + D(12) => I_SM_n_61, + D(11) => I_SM_n_62, + D(10) => I_SM_n_63, + D(9) => I_SM_n_64, + D(8) => I_SM_n_65, + D(7) => I_SM_n_66, + D(6) => I_SM_n_67, + D(5) => I_SM_n_68, + D(4) => I_SM_n_69, + D(3) => I_SM_n_70, + D(2) => I_SM_n_71, + D(1) => I_SM_n_72, + D(0) => I_SM_n_73, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4]\(0) => D(0), + \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0\(15 downto 0) => dm_address_reg(15 downto 0), + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\ => \^p_47_out\, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][16]\ => VIDEO_REG_I_n_35, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][17]\ => VIDEO_REG_I_n_36, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][18]\ => VIDEO_REG_I_n_37, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][19]\ => VIDEO_REG_I_n_38, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][20]\ => VIDEO_REG_I_n_39, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][21]\ => VIDEO_REG_I_n_40, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][22]\ => VIDEO_REG_I_n_41, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][23]\ => VIDEO_REG_I_n_42, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][24]\ => VIDEO_REG_I_n_43, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][25]\ => VIDEO_REG_I_n_44, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][26]\ => VIDEO_REG_I_n_45, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][27]\ => VIDEO_REG_I_n_46, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][28]\ => VIDEO_REG_I_n_47, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][29]\ => VIDEO_REG_I_n_48, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][30]\ => VIDEO_REG_I_n_49, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\ => VIDEO_REG_I_n_50, + \INFERRED_GEN.cnt_i_reg[2]\(0) => \INFERRED_GEN.cnt_i_reg[2]_2\(0), + O(3) => VIDEO_REG_I_n_52, + O(2) => VIDEO_REG_I_n_53, + O(1) => VIDEO_REG_I_n_54, + O(0) => VIDEO_REG_I_n_55, + Q(12 downto 0) => \^q\(12 downto 0), + SR(0) => SR(0), + datamover_idle => \^datamover_idle\, + dma_err => \^dma_err\, + dma_interr_reg => dma_interr_reg, + dma_interr_reg_0 => dma_interr_reg_0, + \dmacr_i_reg[2]\ => \dmacr_i_reg[2]\, + err_i_reg(0) => err_i_reg(0), + frame_sync_reg => frame_sync_reg, + halt_i_reg => I_CMDSTS_n_3, + halted_set_i0 => halted_set_i0, + \hsize_vid_reg[15]\(15 downto 0) => crnt_hsize(15 downto 0), + interr_i_reg => I_CMDSTS_n_1, + load_new_addr => load_new_addr, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + mm2s_all_lines_xfred => mm2s_all_lines_xfred, + mm2s_axi2ip_wrce(0) => mm2s_axi2ip_wrce(0), + mm2s_fifo_pipe_empty => mm2s_fifo_pipe_empty, + mm2s_halt => mm2s_halt, + mm2s_prmry_resetn => mm2s_prmry_resetn, + p_24_out => p_24_out, + p_39_out => \^p_39_out\, + p_58_out => \^p_58_out\, + p_71_out(0) => p_71_out(0), + p_77_out => p_77_out, + s_axis_cmd_tvalid_reg => \^cmnd_wr\, + s_axis_cmd_tvalid_reg_0 => \^p_56_out\, + \stride_vid_reg[11]\(3) => VIDEO_REG_I_n_60, + \stride_vid_reg[11]\(2) => VIDEO_REG_I_n_61, + \stride_vid_reg[11]\(1) => VIDEO_REG_I_n_62, + \stride_vid_reg[11]\(0) => VIDEO_REG_I_n_63, + \stride_vid_reg[15]\(3) => VIDEO_REG_I_n_65, + \stride_vid_reg[15]\(2) => VIDEO_REG_I_n_66, + \stride_vid_reg[15]\(1) => VIDEO_REG_I_n_67, + \stride_vid_reg[15]\(0) => VIDEO_REG_I_n_68, + \stride_vid_reg[7]\(3) => VIDEO_REG_I_n_56, + \stride_vid_reg[7]\(2) => VIDEO_REG_I_n_57, + \stride_vid_reg[7]\(1) => VIDEO_REG_I_n_58, + \stride_vid_reg[7]\(0) => VIDEO_REG_I_n_59, + tstvect_fsync_d1 => tstvect_fsync_d1, + tstvect_fsync_d2 => tstvect_fsync_d2, + zero_hsize_err => zero_hsize_err, + zero_hsize_err0 => zero_hsize_err0, + zero_vsize_err => zero_vsize_err, + zero_vsize_err0 => zero_vsize_err0 + ); +I_STS_MNGR: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_sts_mngr_42 + port map ( + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ => VIDEO_REG_I_n_32, + SR(0) => SR(0), + datamover_idle => \^datamover_idle\, + halted_reg => halted_reg, + halted_set_i0 => halted_set_i0, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + mm2s_prmry_resetn => mm2s_prmry_resetn, + p_37_out => p_37_out, + p_70_out => p_70_out, + p_71_out(0) => p_71_out(0), + sig_halt_cmplt_reg => sig_halt_cmplt_reg + ); +\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(0), + Q => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4]\(0), + R => SR(0) + ); +\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(1), + Q => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4]\(1), + R => SR(0) + ); +\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(2), + Q => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4]\(2), + R => SR(0) + ); +\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(3), + Q => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4]\(3), + R => SR(0) + ); +\MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(4), + Q => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4]\(4), + R => SR(0) + ); +\MASTER_MODE_FRAME_CNT.frame_number_i[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"080808FB" + ) + port map ( + I0 => \ptr_ref_i_reg[4]\(0), + I1 => valid_frame_sync_d2, + I2 => p_71_out(1), + I3 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(0), + I4 => VIDEO_GENLOCK_I_n_1, + O => \MASTER_MODE_FRAME_CNT.frame_number_i[0]_i_1_n_0\ + ); +\MASTER_MODE_FRAME_CNT.frame_number_i[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"080808FB08FB0808" + ) + port map ( + I0 => \ptr_ref_i_reg[4]\(1), + I1 => valid_frame_sync_d2, + I2 => p_71_out(1), + I3 => VIDEO_GENLOCK_I_n_1, + I4 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(1), + I5 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(0), + O => \MASTER_MODE_FRAME_CNT.frame_number_i[1]_i_1_n_0\ + ); +\MASTER_MODE_FRAME_CNT.frame_number_i[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"08FBFB08FB08FB08" + ) + port map ( + I0 => \ptr_ref_i_reg[4]\(2), + I1 => valid_frame_sync_d2, + I2 => p_71_out(1), + I3 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(2), + I4 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(1), + I5 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(0), + O => \MASTER_MODE_FRAME_CNT.frame_number_i[2]_i_1_n_0\ + ); +\MASTER_MODE_FRAME_CNT.frame_number_i[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8BB8B8B8B8B8B8B8" + ) + port map ( + I0 => \ptr_ref_i_reg[4]\(3), + I1 => \MASTER_MODE_FRAME_CNT.frame_number_i[3]_i_2_n_0\, + I2 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(3), + I3 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(0), + I4 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(1), + I5 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(2), + O => \MASTER_MODE_FRAME_CNT.frame_number_i[3]_i_1_n_0\ + ); +\MASTER_MODE_FRAME_CNT.frame_number_i[3]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => valid_frame_sync_d2, + I1 => p_71_out(1), + O => \MASTER_MODE_FRAME_CNT.frame_number_i[3]_i_2_n_0\ + ); +\MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"08FBFB08FB08FB08" + ) + port map ( + I0 => \ptr_ref_i_reg[4]\(4), + I1 => valid_frame_sync_d2, + I2 => p_71_out(1), + I3 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(4), + I4 => \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_5_n_0\, + I5 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(3), + O => \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_3_n_0\ + ); +\MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(2), + I1 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(1), + I2 => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(0), + O => \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_5_n_0\ + ); +\MASTER_MODE_FRAME_CNT.frame_number_i_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => VIDEO_REG_I_n_51, + D => \MASTER_MODE_FRAME_CNT.frame_number_i[0]_i_1_n_0\, + Q => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(0), + R => prmry_resetn_i_reg(0) + ); +\MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => VIDEO_REG_I_n_51, + D => \MASTER_MODE_FRAME_CNT.frame_number_i[1]_i_1_n_0\, + Q => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(1), + R => prmry_resetn_i_reg(0) + ); +\MASTER_MODE_FRAME_CNT.frame_number_i_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => VIDEO_REG_I_n_51, + D => \MASTER_MODE_FRAME_CNT.frame_number_i[2]_i_1_n_0\, + Q => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(2), + R => prmry_resetn_i_reg(0) + ); +\MASTER_MODE_FRAME_CNT.frame_number_i_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => VIDEO_REG_I_n_51, + D => \MASTER_MODE_FRAME_CNT.frame_number_i[3]_i_1_n_0\, + Q => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(3), + R => prmry_resetn_i_reg(0) + ); +\MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => VIDEO_REG_I_n_51, + D => \MASTER_MODE_FRAME_CNT.frame_number_i[4]_i_3_n_0\, + Q => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(4), + R => prmry_resetn_i_reg(0) + ); +\MASTER_MODE_FRAME_CNT.tstvect_fsync_reg\: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => p_10_out, + Q => p_50_out, + R => SR(0) + ); +\MASTER_MODE_FRAME_CNT.valid_frame_sync_d1_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => p_46_out, + Q => valid_frame_sync_d1, + R => SR(0) + ); +\MASTER_MODE_FRAME_CNT.valid_frame_sync_d2_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => valid_frame_sync_d1, + Q => valid_frame_sync_d2, + R => SR(0) + ); +VIDEO_GENLOCK_I: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_genlock_mngr + port map ( + \GENLOCK_FOR_MASTER.mstr_reverse_order_reg_0\ => VIDEO_GENLOCK_I_n_1, + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2]\(2 downto 0) => \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2]\(2 downto 0), + Q(4 downto 0) => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(4 downto 0), + SR(0) => SR(0), + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + mm2s_prmry_resetn => mm2s_prmry_resetn, + num_fstore_minus1(0) => num_fstore_minus1(1), + p_45_out => p_45_out, + p_70_out => p_70_out, + p_71_out(0) => p_71_out(1), + valid_frame_sync_d2 => valid_frame_sync_d2 + ); +VIDEO_REG_I: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_vidreg_module_43 + port map ( + CO(0) => VIDEO_REG_I_n_64, + E(0) => VIDEO_REG_I_n_51, + \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15]\(15 downto 0) => crnt_hsize(15 downto 0), + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(31 downto 0) => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(31 downto 0), + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(31 downto 0) => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(31 downto 0), + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(31 downto 0) => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(31 downto 0), + \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]\(1 downto 0) => \^master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(1 downto 0), + \MASTER_MODE_FRAME_CNT.frame_number_i_reg[1]_0\ => VIDEO_GENLOCK_I_n_1, + \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(15 downto 0) => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(15 downto 0), + O(3) => VIDEO_REG_I_n_52, + O(2) => VIDEO_REG_I_n_53, + O(1) => VIDEO_REG_I_n_54, + O(0) => VIDEO_REG_I_n_55, + Q(12 downto 0) => \^q\(12 downto 0), + SR(0) => SR(0), + all_idle_reg => VIDEO_REG_I_n_32, + \dm_address_reg[11]\(3) => VIDEO_REG_I_n_60, + \dm_address_reg[11]\(2) => VIDEO_REG_I_n_61, + \dm_address_reg[11]\(1) => VIDEO_REG_I_n_62, + \dm_address_reg[11]\(0) => VIDEO_REG_I_n_63, + \dm_address_reg[15]\(3) => VIDEO_REG_I_n_65, + \dm_address_reg[15]\(2) => VIDEO_REG_I_n_66, + \dm_address_reg[15]\(1) => VIDEO_REG_I_n_67, + \dm_address_reg[15]\(0) => VIDEO_REG_I_n_68, + \dm_address_reg[15]_0\(15 downto 0) => dm_address_reg(15 downto 0), + \dm_address_reg[19]\ => VIDEO_REG_I_n_35, + \dm_address_reg[19]_0\ => VIDEO_REG_I_n_36, + \dm_address_reg[19]_1\ => VIDEO_REG_I_n_37, + \dm_address_reg[19]_2\ => VIDEO_REG_I_n_38, + \dm_address_reg[23]\ => VIDEO_REG_I_n_39, + \dm_address_reg[23]_0\ => VIDEO_REG_I_n_40, + \dm_address_reg[23]_1\ => VIDEO_REG_I_n_41, + \dm_address_reg[23]_2\ => VIDEO_REG_I_n_42, + \dm_address_reg[27]\ => VIDEO_REG_I_n_43, + \dm_address_reg[27]_0\ => VIDEO_REG_I_n_44, + \dm_address_reg[27]_1\ => VIDEO_REG_I_n_45, + \dm_address_reg[27]_2\ => VIDEO_REG_I_n_46, + \dm_address_reg[31]\ => VIDEO_REG_I_n_47, + \dm_address_reg[31]_0\ => VIDEO_REG_I_n_48, + \dm_address_reg[31]_1\ => VIDEO_REG_I_n_49, + \dm_address_reg[31]_2\ => VIDEO_REG_I_n_50, + \dm_address_reg[7]\(3) => VIDEO_REG_I_n_56, + \dm_address_reg[7]\(2) => VIDEO_REG_I_n_57, + \dm_address_reg[7]\(1) => VIDEO_REG_I_n_58, + \dm_address_reg[7]\(0) => VIDEO_REG_I_n_59, + load_new_addr => load_new_addr, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + mask_fsync_out_i => mask_fsync_out_i, + mm2s_fifo_pipe_empty => mm2s_fifo_pipe_empty, + mm2s_prmry_resetn => mm2s_prmry_resetn, + p_10_out => p_10_out, + p_24_out => p_24_out, + p_2_out => p_2_out, + p_39_out => \^p_39_out\, + p_67_out => p_67_out, + p_70_out => p_70_out, + p_71_out(0) => p_71_out(1), + prmtr_updt_complete_i_reg => prmtr_updt_complete_i_reg, + \reg_module_hsize_reg[15]\(15 downto 0) => \reg_module_hsize_reg[15]\(15 downto 0), + \reg_module_vsize_reg[12]\(12 downto 0) => \reg_module_vsize_reg[12]\(12 downto 0), + \stride_vid_reg[0]\ => prmtr_update_complete, + \stride_vid_reg[0]_0\ => \^p_47_out\, + tstvect_fsync_d1 => tstvect_fsync_d1, + tstvect_fsync_d2 => tstvect_fsync_d2, + valid_frame_sync_d2 => valid_frame_sync_d2, + zero_hsize_err0 => zero_hsize_err0, + zero_vsize_err0 => zero_vsize_err0 + ); +initial_frame_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"00E0" + ) + port map ( + I0 => \^initial_frame\, + I1 => p_24_out, + I2 => mm2s_prmry_resetn, + I3 => p_70_out, + O => initial_frame_i_1_n_0 + ); +initial_frame_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => initial_frame_i_1_n_0, + Q => \^initial_frame\, + R => '0' + ); +\num_fstore_minus1_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => '1', + Q => num_fstore_minus1(1), + R => SR(0) + ); +stop_reg: unisim.vcomponents.FDRE + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => stop_i, + Q => stop, + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_axi_vdma_mngr__parameterized0\ is + port ( + fsize_mismatch_err : out STD_LOGIC; + cmnd_wr : out STD_LOGIC; + drop_fsync_d_pulse_gen_fsize_less_err_d1 : out STD_LOGIC; + fsize_mismatch_err_s1 : out STD_LOGIC; + m_axis_s2mm_sts_tready : out STD_LOGIC; + lsize_mismatch_err : out STD_LOGIC; + lsize_more_mismatch_err : out STD_LOGIC; + prmtr_update_complete : out STD_LOGIC; + s2mm_valid_frame_sync : out STD_LOGIC; + s2mm_stop : out STD_LOGIC; + s2mm_tstvect_fsync : out STD_LOGIC; + num_fstore_minus1 : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axis_s2mm_cmd_tvalid : out STD_LOGIC; + datamover_idle : out STD_LOGIC; + halt_i0 : out STD_LOGIC; + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg\ : out STD_LOGIC; + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_irqthresh_decr_mask_sig_reg\ : out STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + Q : out STD_LOGIC_VECTOR ( 12 downto 0 ); + \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); + s2mm_ftchcmdsts_idle : out STD_LOGIC; + \DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + s2mm_valid_video_prmtrs : out STD_LOGIC; + dma_err : out STD_LOGIC; + s2mm_dma_interr_set_minus_frame_errors : out STD_LOGIC; + S : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_STS_GRTR_THAN_8.undrflo_err_reg\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + p_2_out : out STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_fsize_less_err_flag_10_reg\ : out STD_LOGIC; + halted_reg : out STD_LOGIC; + dma_slverr_reg : out STD_LOGIC; + dma_decerr_reg : out STD_LOGIC; + \S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg\ : out STD_LOGIC; + \sig_input_addr_reg_reg[31]\ : out STD_LOGIC_VECTOR ( 48 downto 0 ); + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + initial_frame : out STD_LOGIC; + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + prmry_reset2 : in STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_s2mm_aclk : in STD_LOGIC; + s2mm_fsync_out_m_i : in STD_LOGIC; + drop_fsync_d_pulse_gen_fsize_less_err : in STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg\ : in STD_LOGIC; + \out\ : in STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[2]\ : in STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[2]_0\ : in STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[2]_1\ : in STD_LOGIC; + p_12_out : in STD_LOGIC; + p_9_out : in STD_LOGIC; + s2mm_dmacr : in STD_LOGIC_VECTOR ( 3 downto 0 ); + prmtr_updt_complete_i_reg : in STD_LOGIC; + s2mm_valid_frame_sync_cmb : in STD_LOGIC; + halted_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_halt_cmplt_reg : in STD_LOGIC; + s2mm_cdc2dmac_fsync : in STD_LOGIC; + run_stop_d1 : in STD_LOGIC; + s2mm_soft_reset : in STD_LOGIC; + soft_reset_d1 : in STD_LOGIC; + prmry_resetn_i_reg : in STD_LOGIC; + ch2_delay_cnt_en : in STD_LOGIC; + s2mm_packet_sof : in STD_LOGIC; + ch2_irqthresh_decr_mask_sig : in STD_LOGIC; + s2mm_halt : in STD_LOGIC; + halt_i_reg : in STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[2]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \ptr_ref_i_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + m_axis_s2mm_sts_tdata : in STD_LOGIC_VECTOR ( 0 to 0 ); + s2mm_dmasr : in STD_LOGIC_VECTOR ( 0 to 0 ); + mask_fsync_out_i : in STD_LOGIC; + s2mm_fsize_less_err_flag_10 : in STD_LOGIC; + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : in STD_LOGIC; + \sig_user_reg_out_reg[0]\ : in STD_LOGIC; + dma_slverr_reg_0 : in STD_LOGIC; + dma_decerr_reg_0 : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 0 to 0 ); + s2mm_axi2ip_wrce : in STD_LOGIC_VECTOR ( 0 to 0 ); + \S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg_0\ : in STD_LOGIC; + \reg_module_vsize_reg[12]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + \reg_module_hsize_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + prmry_resetn_i_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + err_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_axi_vdma_mngr__parameterized0\ : entity is "axi_vdma_mngr"; +end \Arty_Z7_20_axi_vdma_0_0_axi_vdma_mngr__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_axi_vdma_mngr__parameterized0\ is + signal \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[1]_i_3_n_0\ : STD_LOGIC; + signal \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_5_n_0\ : STD_LOGIC; + signal \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_8_n_0\ : STD_LOGIC; + signal \^dynamic_master_mode_frame_cnt.chnl_current_frame_reg[4]_0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr[4]_i_1_n_0\ : STD_LOGIC; + signal \^gen_normal_dm_command.cmnd_data_reg[15]\ : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal I_CMDSTS_n_1 : STD_LOGIC; + signal I_CMDSTS_n_5 : STD_LOGIC; + signal I_CMDSTS_n_8 : STD_LOGIC; + signal I_SM_n_31 : STD_LOGIC; + signal I_SM_n_32 : STD_LOGIC; + signal I_SM_n_33 : STD_LOGIC; + signal I_SM_n_34 : STD_LOGIC; + signal I_SM_n_35 : STD_LOGIC; + signal I_SM_n_37 : STD_LOGIC; + signal I_SM_n_38 : STD_LOGIC; + signal I_SM_n_39 : STD_LOGIC; + signal I_SM_n_40 : STD_LOGIC; + signal I_SM_n_41 : STD_LOGIC; + signal I_SM_n_42 : STD_LOGIC; + signal I_SM_n_43 : STD_LOGIC; + signal I_SM_n_44 : STD_LOGIC; + signal I_SM_n_45 : STD_LOGIC; + signal I_SM_n_46 : STD_LOGIC; + signal I_SM_n_47 : STD_LOGIC; + signal I_SM_n_48 : STD_LOGIC; + signal I_SM_n_49 : STD_LOGIC; + signal I_SM_n_50 : STD_LOGIC; + signal I_SM_n_51 : STD_LOGIC; + signal I_SM_n_52 : STD_LOGIC; + signal I_SM_n_53 : STD_LOGIC; + signal I_SM_n_54 : STD_LOGIC; + signal I_SM_n_55 : STD_LOGIC; + signal I_SM_n_56 : STD_LOGIC; + signal I_SM_n_57 : STD_LOGIC; + signal I_SM_n_58 : STD_LOGIC; + signal I_SM_n_59 : STD_LOGIC; + signal I_SM_n_60 : STD_LOGIC; + signal I_SM_n_61 : STD_LOGIC; + signal I_SM_n_62 : STD_LOGIC; + signal I_SM_n_63 : STD_LOGIC; + signal I_SM_n_64 : STD_LOGIC; + signal I_SM_n_65 : STD_LOGIC; + signal I_SM_n_66 : STD_LOGIC; + signal I_SM_n_67 : STD_LOGIC; + signal I_SM_n_68 : STD_LOGIC; + signal I_SM_n_69 : STD_LOGIC; + signal I_SM_n_70 : STD_LOGIC; + signal I_SM_n_71 : STD_LOGIC; + signal I_SM_n_72 : STD_LOGIC; + signal I_SM_n_73 : STD_LOGIC; + signal I_SM_n_74 : STD_LOGIC; + signal I_SM_n_75 : STD_LOGIC; + signal I_SM_n_76 : STD_LOGIC; + signal I_SM_n_77 : STD_LOGIC; + signal I_SM_n_78 : STD_LOGIC; + signal I_SM_n_79 : STD_LOGIC; + signal I_SM_n_80 : STD_LOGIC; + signal I_SM_n_81 : STD_LOGIC; + signal I_SM_n_82 : STD_LOGIC; + signal I_SM_n_83 : STD_LOGIC; + signal I_SM_n_84 : STD_LOGIC; + signal I_SM_n_85 : STD_LOGIC; + signal I_SM_n_86 : STD_LOGIC; + signal I_SM_n_88 : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal VIDEO_GENLOCK_I_n_1 : STD_LOGIC; + signal VIDEO_GENLOCK_I_n_2 : STD_LOGIC; + signal VIDEO_GENLOCK_I_n_3 : STD_LOGIC; + signal VIDEO_GENLOCK_I_n_4 : STD_LOGIC; + signal VIDEO_GENLOCK_I_n_5 : STD_LOGIC; + signal VIDEO_REG_I_n_34 : STD_LOGIC; + signal VIDEO_REG_I_n_35 : STD_LOGIC; + signal VIDEO_REG_I_n_36 : STD_LOGIC; + signal VIDEO_REG_I_n_37 : STD_LOGIC; + signal VIDEO_REG_I_n_38 : STD_LOGIC; + signal VIDEO_REG_I_n_39 : STD_LOGIC; + signal VIDEO_REG_I_n_40 : STD_LOGIC; + signal VIDEO_REG_I_n_41 : STD_LOGIC; + signal VIDEO_REG_I_n_42 : STD_LOGIC; + signal VIDEO_REG_I_n_43 : STD_LOGIC; + signal VIDEO_REG_I_n_44 : STD_LOGIC; + signal VIDEO_REG_I_n_45 : STD_LOGIC; + signal VIDEO_REG_I_n_46 : STD_LOGIC; + signal VIDEO_REG_I_n_47 : STD_LOGIC; + signal VIDEO_REG_I_n_48 : STD_LOGIC; + signal VIDEO_REG_I_n_49 : STD_LOGIC; + signal VIDEO_REG_I_n_52 : STD_LOGIC; + signal VIDEO_REG_I_n_53 : STD_LOGIC; + signal VIDEO_REG_I_n_54 : STD_LOGIC; + signal VIDEO_REG_I_n_55 : STD_LOGIC; + signal VIDEO_REG_I_n_56 : STD_LOGIC; + signal VIDEO_REG_I_n_57 : STD_LOGIC; + signal VIDEO_REG_I_n_58 : STD_LOGIC; + signal VIDEO_REG_I_n_59 : STD_LOGIC; + signal VIDEO_REG_I_n_60 : STD_LOGIC; + signal VIDEO_REG_I_n_61 : STD_LOGIC; + signal VIDEO_REG_I_n_62 : STD_LOGIC; + signal VIDEO_REG_I_n_63 : STD_LOGIC; + signal VIDEO_REG_I_n_64 : STD_LOGIC; + signal VIDEO_REG_I_n_65 : STD_LOGIC; + signal VIDEO_REG_I_n_66 : STD_LOGIC; + signal VIDEO_REG_I_n_67 : STD_LOGIC; + signal VIDEO_REG_I_n_68 : STD_LOGIC; + signal \^cmnd_wr\ : STD_LOGIC; + signal crnt_hsize : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \^datamover_idle\ : STD_LOGIC; + signal dm_address_reg : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal dm_prev_frame_number : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \^dma_err\ : STD_LOGIC; + signal flag_to_repeat_after_fsize_less_err : STD_LOGIC; + signal frame_number_i : STD_LOGIC; + signal \^fsize_mismatch_err\ : STD_LOGIC; + signal halted_set_i0 : STD_LOGIC; + signal \^initial_frame\ : STD_LOGIC; + signal \initial_frame_i_1__0_n_0\ : STD_LOGIC; + signal load_new_addr : STD_LOGIC; + signal \^m_axis_s2mm_sts_tready\ : STD_LOGIC; + signal \^num_fstore_minus1\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal p_24_out : STD_LOGIC; + signal p_26_out : STD_LOGIC; + signal repeat_frame : STD_LOGIC; + signal repeat_frame_nmbr : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \^s2mm_stop\ : STD_LOGIC; + signal \^s2mm_tstvect_fsync\ : STD_LOGIC; + signal \^s2mm_valid_video_prmtrs\ : STD_LOGIC; + signal \^s_axis_s2mm_cmd_tvalid\ : STD_LOGIC; + signal s_h_frame_number : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal slv_frame_ref_out : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal stop_i : STD_LOGIC; + signal tstvect_fsync_d1 : STD_LOGIC; + signal tstvect_fsync_d2 : STD_LOGIC; + signal valid_frame_sync_d1 : STD_LOGIC; + signal valid_frame_sync_d2 : STD_LOGIC; + signal zero_hsize_err : STD_LOGIC; + signal zero_hsize_err0 : STD_LOGIC; + signal zero_vsize_err : STD_LOGIC; + signal zero_vsize_err0 : STD_LOGIC; +begin + \DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0\(4 downto 0) <= \^dynamic_master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(4 downto 0); + \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15]\(12 downto 0) <= \^gen_normal_dm_command.cmnd_data_reg[15]\(12 downto 0); + Q(12 downto 0) <= \^q\(12 downto 0); + cmnd_wr <= \^cmnd_wr\; + datamover_idle <= \^datamover_idle\; + dma_err <= \^dma_err\; + fsize_mismatch_err <= \^fsize_mismatch_err\; + initial_frame <= \^initial_frame\; + m_axis_s2mm_sts_tready <= \^m_axis_s2mm_sts_tready\; + num_fstore_minus1(0) <= \^num_fstore_minus1\(0); + s2mm_stop <= \^s2mm_stop\; + s2mm_tstvect_fsync <= \^s2mm_tstvect_fsync\; + s2mm_valid_video_prmtrs <= \^s2mm_valid_video_prmtrs\; + s_axis_s2mm_cmd_tvalid <= \^s_axis_s2mm_cmd_tvalid\; +\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[1]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFF6" + ) + port map ( + I0 => \^dynamic_master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(1), + I1 => \^num_fstore_minus1\(0), + I2 => \^dynamic_master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(0), + I3 => \^dynamic_master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(2), + I4 => \^dynamic_master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(3), + I5 => \^dynamic_master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(4), + O => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[1]_i_3_n_0\ + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00F8" + ) + port map ( + I0 => repeat_frame, + I1 => s2mm_dmacr(3), + I2 => valid_frame_sync_d2, + I3 => flag_to_repeat_after_fsize_less_err, + O => frame_number_i + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => repeat_frame, + I1 => s2mm_dmacr(3), + O => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_5_n_0\ + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_8\: unisim.vcomponents.LUT2 + generic map( + INIT => X"7" + ) + port map ( + I0 => valid_frame_sync_d2, + I1 => s2mm_dmacr(2), + O => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_8_n_0\ + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => frame_number_i, + D => VIDEO_GENLOCK_I_n_5, + Q => \^dynamic_master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(0), + R => prmry_resetn_i_reg_0(0) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => frame_number_i, + D => VIDEO_GENLOCK_I_n_4, + Q => \^dynamic_master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(1), + R => prmry_resetn_i_reg_0(0) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => frame_number_i, + D => VIDEO_GENLOCK_I_n_3, + Q => \^dynamic_master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(2), + R => prmry_resetn_i_reg_0(0) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => frame_number_i, + D => VIDEO_GENLOCK_I_n_2, + Q => \^dynamic_master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(3), + R => prmry_resetn_i_reg_0(0) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => frame_number_i, + D => VIDEO_GENLOCK_I_n_1, + Q => \^dynamic_master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(4), + R => prmry_resetn_i_reg_0(0) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF.flag_to_repeat_after_fsize_less_err_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => I_SM_n_88, + Q => flag_to_repeat_after_fsize_less_err, + R => '0' + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \^dynamic_master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(0), + Q => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[4]\(0), + R => SR(0) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \^dynamic_master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(1), + Q => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[4]\(1), + R => SR(0) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \^dynamic_master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(2), + Q => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[4]\(2), + R => SR(0) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \^dynamic_master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(3), + Q => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[4]\(3), + R => SR(0) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \^dynamic_master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(4), + Q => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[4]\(4), + R => SR(0) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0444" + ) + port map ( + I0 => flag_to_repeat_after_fsize_less_err, + I1 => valid_frame_sync_d2, + I2 => s2mm_dmacr(3), + I3 => repeat_frame, + O => p_24_out + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => p_24_out, + D => \^dynamic_master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(0), + Q => dm_prev_frame_number(0), + R => SR(0) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => p_24_out, + D => \^dynamic_master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(1), + Q => dm_prev_frame_number(1), + R => SR(0) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => p_24_out, + D => \^dynamic_master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(2), + Q => dm_prev_frame_number(2), + R => SR(0) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => p_24_out, + D => \^dynamic_master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(3), + Q => dm_prev_frame_number(3), + R => SR(0) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => p_24_out, + D => \^dynamic_master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(4), + Q => dm_prev_frame_number(4), + R => SR(0) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.genlock_pair_frame_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => slv_frame_ref_out(0), + Q => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[4]\(0), + R => SR(0) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.genlock_pair_frame_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => slv_frame_ref_out(1), + Q => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[4]\(1), + R => SR(0) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.genlock_pair_frame_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => slv_frame_ref_out(3), + Q => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[4]\(2), + R => SR(0) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.genlock_pair_frame_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => slv_frame_ref_out(3), + Q => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[4]\(3), + R => SR(0) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.genlock_pair_frame_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => slv_frame_ref_out(3), + Q => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[4]\(4), + R => SR(0) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr[4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"4F" + ) + port map ( + I0 => flag_to_repeat_after_fsize_less_err, + I1 => valid_frame_sync_d2, + I2 => \out\, + O => \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr[4]_i_1_n_0\ + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => I_CMDSTS_n_5, + D => I_SM_n_35, + Q => repeat_frame_nmbr(0), + R => \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr[4]_i_1_n_0\ + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => I_CMDSTS_n_5, + D => I_SM_n_34, + Q => repeat_frame_nmbr(1), + R => \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr[4]_i_1_n_0\ + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => I_CMDSTS_n_5, + D => I_SM_n_33, + Q => repeat_frame_nmbr(2), + R => \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr[4]_i_1_n_0\ + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => I_CMDSTS_n_5, + D => I_SM_n_32, + Q => repeat_frame_nmbr(3), + R => \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr[4]_i_1_n_0\ + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => I_CMDSTS_n_5, + D => I_SM_n_31, + Q => repeat_frame_nmbr(4), + R => \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr[4]_i_1_n_0\ + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => I_CMDSTS_n_8, + Q => repeat_frame, + R => '0' + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.tstvect_fsync_reg\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => p_26_out, + Q => \^s2mm_tstvect_fsync\, + R => SR(0) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.valid_frame_sync_d1_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => s2mm_valid_frame_sync_cmb, + Q => valid_frame_sync_d1, + R => SR(0) + ); +\DYNAMIC_MASTER_MODE_FRAME_CNT.valid_frame_sync_d2_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => valid_frame_sync_d1, + Q => valid_frame_sync_d2, + R => SR(0) + ); +\GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_cdc2dmac_fsync, + D => \^dynamic_master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(0), + Q => s_h_frame_number(0), + R => SR(0) + ); +\GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_cdc2dmac_fsync, + D => \^dynamic_master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(1), + Q => s_h_frame_number(1), + R => SR(0) + ); +\GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_cdc2dmac_fsync, + D => \^dynamic_master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(2), + Q => s_h_frame_number(2), + R => SR(0) + ); +\GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_cdc2dmac_fsync, + D => \^dynamic_master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(3), + Q => s_h_frame_number(3), + R => SR(0) + ); +\GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => s2mm_cdc2dmac_fsync, + D => \^dynamic_master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(4), + Q => s_h_frame_number(4), + R => SR(0) + ); +I_CMDSTS: entity work.\Arty_Z7_20_axi_vdma_0_0_axi_vdma_cmdsts_if__parameterized0\ + port map ( + D(48) => I_SM_n_38, + D(47) => I_SM_n_39, + D(46) => I_SM_n_40, + D(45) => I_SM_n_41, + D(44) => I_SM_n_42, + D(43) => I_SM_n_43, + D(42) => I_SM_n_44, + D(41) => I_SM_n_45, + D(40) => I_SM_n_46, + D(39) => I_SM_n_47, + D(38) => I_SM_n_48, + D(37) => I_SM_n_49, + D(36) => I_SM_n_50, + D(35) => I_SM_n_51, + D(34) => I_SM_n_52, + D(33) => I_SM_n_53, + D(32) => I_SM_n_54, + D(31) => I_SM_n_55, + D(30) => I_SM_n_56, + D(29) => I_SM_n_57, + D(28) => I_SM_n_58, + D(27) => I_SM_n_59, + D(26) => I_SM_n_60, + D(25) => I_SM_n_61, + D(24) => I_SM_n_62, + D(23) => I_SM_n_63, + D(22) => I_SM_n_64, + D(21) => I_SM_n_65, + D(20) => I_SM_n_66, + D(19) => I_SM_n_67, + D(18) => I_SM_n_68, + D(17) => I_SM_n_69, + D(16) => I_SM_n_70, + D(15) => I_SM_n_71, + D(14) => I_SM_n_72, + D(13) => I_SM_n_73, + D(12) => I_SM_n_74, + D(11) => I_SM_n_75, + D(10) => I_SM_n_76, + D(9) => I_SM_n_77, + D(8) => I_SM_n_78, + D(7) => I_SM_n_79, + D(6) => I_SM_n_80, + D(5) => I_SM_n_81, + D(4) => I_SM_n_82, + D(3) => I_SM_n_83, + D(2) => I_SM_n_84, + D(1) => I_SM_n_85, + D(0) => I_SM_n_86, + \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_nmbr_reg[4]\(0) => I_CMDSTS_n_5, + \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_reg\ => I_CMDSTS_n_8, + E(0) => E(0), + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ => \^fsize_mismatch_err\, + \GEN_NORMAL_DM_COMMAND.cmnd_wr_i_reg\ => \^cmnd_wr\, + \INFERRED_GEN.cnt_i_reg[2]\ => \INFERRED_GEN.cnt_i_reg[2]\, + \INFERRED_GEN.cnt_i_reg[2]_0\ => \INFERRED_GEN.cnt_i_reg[2]_0\, + \INFERRED_GEN.cnt_i_reg[2]_1\ => \INFERRED_GEN.cnt_i_reg[2]_1\, + SR(0) => SR(0), + dma_decerr_reg => dma_decerr_reg, + dma_decerr_reg_0 => dma_decerr_reg_0, + dma_slverr_reg => dma_slverr_reg, + dma_slverr_reg_0 => dma_slverr_reg_0, + err_i_reg_0 => I_CMDSTS_n_1, + flag_to_repeat_after_fsize_less_err => flag_to_repeat_after_fsize_less_err, + halted_reg(0) => halted_reg_0(0), + lsize_mismatch_err => lsize_mismatch_err, + lsize_more_mismatch_err => lsize_more_mismatch_err, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + m_axis_s2mm_sts_tready => \^m_axis_s2mm_sts_tready\, + \out\ => \out\, + p_12_out => p_12_out, + p_9_out => p_9_out, + repeat_frame => repeat_frame, + s2mm_soft_reset => s2mm_soft_reset, + \sig_input_addr_reg_reg[31]\(48 downto 0) => \sig_input_addr_reg_reg[31]\(48 downto 0), + stop_i => stop_i, + stop_reg => \^dma_err\, + valid_frame_sync_d2 => valid_frame_sync_d2, + \vert_count_reg[0]\ => \^s_axis_s2mm_cmd_tvalid\, + zero_hsize_err => zero_hsize_err, + zero_vsize_err => zero_vsize_err + ); +I_SM: entity work.\Arty_Z7_20_axi_vdma_0_0_axi_vdma_sm__parameterized0\ + port map ( + CO(0) => VIDEO_REG_I_n_64, + D(4) => I_SM_n_31, + D(3) => I_SM_n_32, + D(2) => I_SM_n_33, + D(1) => I_SM_n_34, + D(0) => I_SM_n_35, + \DYNAMIC_GENLOCK_FOR_MASTER.mstr_reverse_order_reg\ => I_SM_n_37, + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(4 downto 0) => \^dynamic_master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(4 downto 0), + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF.flag_to_repeat_after_fsize_less_err_reg\ => I_SM_n_88, + \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[4]\(3 downto 1) => dm_prev_frame_number(4 downto 2), + \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[4]\(0) => dm_prev_frame_number(0), + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\, + \GEN_FRMSTORE_EXTFSYNC.s_h_frame_number_reg[4]\(4 downto 0) => s_h_frame_number(4 downto 0), + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg\ => \^fsize_mismatch_err\, + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0\ => \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg\, + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_irqthresh_decr_mask_sig_reg\ => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_irqthresh_decr_mask_sig_reg\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4]\(0) => D(0), + \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[47]_0\(15 downto 0) => dm_address_reg(15 downto 0), + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_prmtrs_valid_i_reg\ => \^s2mm_valid_video_prmtrs\, + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg\ => \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg\, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[0]\(0) => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[0]\(0), + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_fsize_less_err_flag_10_reg\ => \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_fsize_less_err_flag_10_reg\, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][16]\ => VIDEO_REG_I_n_34, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][17]\ => VIDEO_REG_I_n_35, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][18]\ => VIDEO_REG_I_n_36, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][19]\ => VIDEO_REG_I_n_37, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][20]\ => VIDEO_REG_I_n_38, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][21]\ => VIDEO_REG_I_n_39, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][22]\ => VIDEO_REG_I_n_40, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][23]\ => VIDEO_REG_I_n_41, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][24]\ => VIDEO_REG_I_n_42, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][25]\ => VIDEO_REG_I_n_43, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][26]\ => VIDEO_REG_I_n_44, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][27]\ => VIDEO_REG_I_n_45, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][28]\ => VIDEO_REG_I_n_46, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][29]\ => VIDEO_REG_I_n_47, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][30]\ => VIDEO_REG_I_n_48, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\ => VIDEO_REG_I_n_49, + \INFERRED_GEN.cnt_i_reg[2]\(0) => \INFERRED_GEN.cnt_i_reg[2]_2\(0), + O(3) => VIDEO_REG_I_n_52, + O(2) => VIDEO_REG_I_n_53, + O(1) => VIDEO_REG_I_n_54, + O(0) => VIDEO_REG_I_n_55, + Q(12 downto 0) => \^q\(12 downto 0), + \S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg\ => \S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg\, + \S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg_0\ => \S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg_0\, + SR(0) => SR(0), + ch2_delay_cnt_en => ch2_delay_cnt_en, + ch2_irqthresh_decr_mask_sig => ch2_irqthresh_decr_mask_sig, + datamover_idle => \^datamover_idle\, + dma_err => \^dma_err\, + drop_fsync_d_pulse_gen_fsize_less_err => drop_fsync_d_pulse_gen_fsize_less_err, + drop_fsync_d_pulse_gen_fsize_less_err_d1 => drop_fsync_d_pulse_gen_fsize_less_err_d1, + err_i_reg(0) => err_i_reg(0), + flag_to_repeat_after_fsize_less_err => flag_to_repeat_after_fsize_less_err, + fsize_mismatch_err_s1 => fsize_mismatch_err_s1, + halt_i0 => halt_i0, + halt_i_reg => halt_i_reg, + halted_set_i0 => halted_set_i0, + \hsize_vid_reg[15]\(15 downto 3) => \^gen_normal_dm_command.cmnd_data_reg[15]\(12 downto 0), + \hsize_vid_reg[15]\(2 downto 0) => crnt_hsize(2 downto 0), + interr_i_reg => I_CMDSTS_n_1, + load_new_addr => load_new_addr, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + m_axis_s2mm_sts_tready => \^m_axis_s2mm_sts_tready\, + \out\ => \out\, + prmry_reset2 => prmry_reset2, + prmry_resetn_i_reg => prmry_resetn_i_reg, + run_stop_d1 => run_stop_d1, + s2mm_axi2ip_wrce(0) => s2mm_axi2ip_wrce(0), + s2mm_cdc2dmac_fsync => s2mm_cdc2dmac_fsync, + s2mm_dma_interr_set_minus_frame_errors => s2mm_dma_interr_set_minus_frame_errors, + s2mm_dmacr(1 downto 0) => s2mm_dmacr(1 downto 0), + s2mm_fsize_less_err_flag_10 => s2mm_fsize_less_err_flag_10, + s2mm_fsync_out_m_i => s2mm_fsync_out_m_i, + s2mm_ftchcmdsts_idle => s2mm_ftchcmdsts_idle, + s2mm_halt => s2mm_halt, + s2mm_packet_sof => s2mm_packet_sof, + s2mm_soft_reset => s2mm_soft_reset, + s2mm_stop => \^s2mm_stop\, + s2mm_tstvect_fsync => \^s2mm_tstvect_fsync\, + \s_axis_cmd_tdata_reg[63]\(48) => I_SM_n_38, + \s_axis_cmd_tdata_reg[63]\(47) => I_SM_n_39, + \s_axis_cmd_tdata_reg[63]\(46) => I_SM_n_40, + \s_axis_cmd_tdata_reg[63]\(45) => I_SM_n_41, + \s_axis_cmd_tdata_reg[63]\(44) => I_SM_n_42, + \s_axis_cmd_tdata_reg[63]\(43) => I_SM_n_43, + \s_axis_cmd_tdata_reg[63]\(42) => I_SM_n_44, + \s_axis_cmd_tdata_reg[63]\(41) => I_SM_n_45, + \s_axis_cmd_tdata_reg[63]\(40) => I_SM_n_46, + \s_axis_cmd_tdata_reg[63]\(39) => I_SM_n_47, + \s_axis_cmd_tdata_reg[63]\(38) => I_SM_n_48, + \s_axis_cmd_tdata_reg[63]\(37) => I_SM_n_49, + \s_axis_cmd_tdata_reg[63]\(36) => I_SM_n_50, + \s_axis_cmd_tdata_reg[63]\(35) => I_SM_n_51, + \s_axis_cmd_tdata_reg[63]\(34) => I_SM_n_52, + \s_axis_cmd_tdata_reg[63]\(33) => I_SM_n_53, + \s_axis_cmd_tdata_reg[63]\(32) => I_SM_n_54, + \s_axis_cmd_tdata_reg[63]\(31) => I_SM_n_55, + \s_axis_cmd_tdata_reg[63]\(30) => I_SM_n_56, + \s_axis_cmd_tdata_reg[63]\(29) => I_SM_n_57, + \s_axis_cmd_tdata_reg[63]\(28) => I_SM_n_58, + \s_axis_cmd_tdata_reg[63]\(27) => I_SM_n_59, + \s_axis_cmd_tdata_reg[63]\(26) => I_SM_n_60, + \s_axis_cmd_tdata_reg[63]\(25) => I_SM_n_61, + \s_axis_cmd_tdata_reg[63]\(24) => I_SM_n_62, + \s_axis_cmd_tdata_reg[63]\(23) => I_SM_n_63, + \s_axis_cmd_tdata_reg[63]\(22) => I_SM_n_64, + \s_axis_cmd_tdata_reg[63]\(21) => I_SM_n_65, + \s_axis_cmd_tdata_reg[63]\(20) => I_SM_n_66, + \s_axis_cmd_tdata_reg[63]\(19) => I_SM_n_67, + \s_axis_cmd_tdata_reg[63]\(18) => I_SM_n_68, + \s_axis_cmd_tdata_reg[63]\(17) => I_SM_n_69, + \s_axis_cmd_tdata_reg[63]\(16) => I_SM_n_70, + \s_axis_cmd_tdata_reg[63]\(15) => I_SM_n_71, + \s_axis_cmd_tdata_reg[63]\(14) => I_SM_n_72, + \s_axis_cmd_tdata_reg[63]\(13) => I_SM_n_73, + \s_axis_cmd_tdata_reg[63]\(12) => I_SM_n_74, + \s_axis_cmd_tdata_reg[63]\(11) => I_SM_n_75, + \s_axis_cmd_tdata_reg[63]\(10) => I_SM_n_76, + \s_axis_cmd_tdata_reg[63]\(9) => I_SM_n_77, + \s_axis_cmd_tdata_reg[63]\(8) => I_SM_n_78, + \s_axis_cmd_tdata_reg[63]\(7) => I_SM_n_79, + \s_axis_cmd_tdata_reg[63]\(6) => I_SM_n_80, + \s_axis_cmd_tdata_reg[63]\(5) => I_SM_n_81, + \s_axis_cmd_tdata_reg[63]\(4) => I_SM_n_82, + \s_axis_cmd_tdata_reg[63]\(3) => I_SM_n_83, + \s_axis_cmd_tdata_reg[63]\(2) => I_SM_n_84, + \s_axis_cmd_tdata_reg[63]\(1) => I_SM_n_85, + \s_axis_cmd_tdata_reg[63]\(0) => I_SM_n_86, + s_axis_cmd_tvalid_reg => \^cmnd_wr\, + s_axis_cmd_tvalid_reg_0 => \^s_axis_s2mm_cmd_tvalid\, + s_axis_s2mm_aclk => s_axis_s2mm_aclk, + \sig_user_reg_out_reg[0]\ => \sig_user_reg_out_reg[0]\, + soft_reset_d1 => soft_reset_d1, + \stride_vid_reg[11]\(3) => VIDEO_REG_I_n_60, + \stride_vid_reg[11]\(2) => VIDEO_REG_I_n_61, + \stride_vid_reg[11]\(1) => VIDEO_REG_I_n_62, + \stride_vid_reg[11]\(0) => VIDEO_REG_I_n_63, + \stride_vid_reg[15]\(3) => VIDEO_REG_I_n_65, + \stride_vid_reg[15]\(2) => VIDEO_REG_I_n_66, + \stride_vid_reg[15]\(1) => VIDEO_REG_I_n_67, + \stride_vid_reg[15]\(0) => VIDEO_REG_I_n_68, + \stride_vid_reg[7]\(3) => VIDEO_REG_I_n_56, + \stride_vid_reg[7]\(2) => VIDEO_REG_I_n_57, + \stride_vid_reg[7]\(1) => VIDEO_REG_I_n_58, + \stride_vid_reg[7]\(0) => VIDEO_REG_I_n_59, + tstvect_fsync_d1 => tstvect_fsync_d1, + tstvect_fsync_d2 => tstvect_fsync_d2, + valid_frame_sync_d2 => valid_frame_sync_d2, + zero_hsize_err => zero_hsize_err, + zero_hsize_err0 => zero_hsize_err0, + zero_vsize_err => zero_vsize_err, + zero_vsize_err0 => zero_vsize_err0 + ); +I_STS_MNGR: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_sts_mngr + port map ( + SR(0) => SR(0), + datamover_idle => \^datamover_idle\, + halted_reg => halted_reg, + halted_set_i0 => halted_set_i0, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\ => \out\, + s2mm_dmacr(0) => s2mm_dmacr(0), + s2mm_dmasr(0) => s2mm_dmasr(0), + sig_halt_cmplt_reg => sig_halt_cmplt_reg + ); +VIDEO_GENLOCK_I: entity work.\Arty_Z7_20_axi_vdma_0_0_axi_vdma_genlock_mngr__parameterized0\ + port map ( + D(4) => VIDEO_GENLOCK_I_n_1, + D(3) => VIDEO_GENLOCK_I_n_2, + D(2) => VIDEO_GENLOCK_I_n_3, + D(1) => VIDEO_GENLOCK_I_n_4, + D(0) => VIDEO_GENLOCK_I_n_5, + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\ => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[1]_i_3_n_0\, + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(4 downto 0) => \^dynamic_master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(4 downto 0), + \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[0]\ => I_SM_n_37, + \DYNAMIC_MASTER_MODE_FRAME_CNT.dm_prev_frame_number_reg[2]\(2 downto 0) => dm_prev_frame_number(2 downto 0), + \DYNAMIC_MASTER_MODE_FRAME_CNT.repeat_frame_reg\ => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_5_n_0\, + \DYNAMIC_MASTER_MODE_FRAME_CNT.valid_frame_sync_d2_reg\ => \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i[4]_i_8_n_0\, + \GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[2]\(2 downto 0) => \GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[2]\(2 downto 0), + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2]\(2 downto 0) => \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2]\(2 downto 0), + Q(4 downto 0) => repeat_frame_nmbr(4 downto 0), + SR(0) => SR(0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \num_fstore_minus1_reg[1]\ => \^num_fstore_minus1\(0), + \out\ => \out\, + \ptr_ref_i_reg[4]\(4 downto 0) => \ptr_ref_i_reg[4]\(4 downto 0), + s2mm_dmacr(1 downto 0) => s2mm_dmacr(2 downto 1), + s2mm_dmasr(0) => s2mm_dmasr(0), + s2mm_valid_frame_sync => s2mm_valid_frame_sync, + slv_frame_ref_out(2) => slv_frame_ref_out(3), + slv_frame_ref_out(1 downto 0) => slv_frame_ref_out(1 downto 0), + valid_frame_sync_d2 => valid_frame_sync_d2 + ); +VIDEO_REG_I: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_vidreg_module + port map ( + CO(0) => VIDEO_REG_I_n_64, + \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(15 downto 0) => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(15 downto 0), + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[1]\(1 downto 0) => \^dynamic_master_mode_frame_cnt.chnl_current_frame_reg[4]_0\(1 downto 0), + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(31 downto 0) => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(31 downto 0), + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(31 downto 0) => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(31 downto 0), + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(31 downto 0) => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(31 downto 0), + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12]\(12 downto 0) => \^q\(12 downto 0), + \GEN_STS_GRTR_THAN_8.undrflo_err_reg\(0) => \GEN_STS_GRTR_THAN_8.undrflo_err_reg\(0), + O(3) => VIDEO_REG_I_n_52, + O(2) => VIDEO_REG_I_n_53, + O(1) => VIDEO_REG_I_n_54, + O(0) => VIDEO_REG_I_n_55, + Q(15 downto 3) => \^gen_normal_dm_command.cmnd_data_reg[15]\(12 downto 0), + Q(2 downto 0) => crnt_hsize(2 downto 0), + S(0) => S(0), + SR(0) => SR(0), + \dm_address_reg[11]\(3) => VIDEO_REG_I_n_60, + \dm_address_reg[11]\(2) => VIDEO_REG_I_n_61, + \dm_address_reg[11]\(1) => VIDEO_REG_I_n_62, + \dm_address_reg[11]\(0) => VIDEO_REG_I_n_63, + \dm_address_reg[15]\(3) => VIDEO_REG_I_n_65, + \dm_address_reg[15]\(2) => VIDEO_REG_I_n_66, + \dm_address_reg[15]\(1) => VIDEO_REG_I_n_67, + \dm_address_reg[15]\(0) => VIDEO_REG_I_n_68, + \dm_address_reg[15]_0\(15 downto 0) => dm_address_reg(15 downto 0), + \dm_address_reg[19]\ => VIDEO_REG_I_n_34, + \dm_address_reg[19]_0\ => VIDEO_REG_I_n_35, + \dm_address_reg[19]_1\ => VIDEO_REG_I_n_36, + \dm_address_reg[19]_2\ => VIDEO_REG_I_n_37, + \dm_address_reg[23]\ => VIDEO_REG_I_n_38, + \dm_address_reg[23]_0\ => VIDEO_REG_I_n_39, + \dm_address_reg[23]_1\ => VIDEO_REG_I_n_40, + \dm_address_reg[23]_2\ => VIDEO_REG_I_n_41, + \dm_address_reg[27]\ => VIDEO_REG_I_n_42, + \dm_address_reg[27]_0\ => VIDEO_REG_I_n_43, + \dm_address_reg[27]_1\ => VIDEO_REG_I_n_44, + \dm_address_reg[27]_2\ => VIDEO_REG_I_n_45, + \dm_address_reg[31]\ => VIDEO_REG_I_n_46, + \dm_address_reg[31]_0\ => VIDEO_REG_I_n_47, + \dm_address_reg[31]_1\ => VIDEO_REG_I_n_48, + \dm_address_reg[31]_2\ => VIDEO_REG_I_n_49, + \dm_address_reg[7]\(3) => VIDEO_REG_I_n_56, + \dm_address_reg[7]\(2) => VIDEO_REG_I_n_57, + \dm_address_reg[7]\(1) => VIDEO_REG_I_n_58, + \dm_address_reg[7]\(0) => VIDEO_REG_I_n_59, + load_new_addr => load_new_addr, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + m_axis_s2mm_sts_tdata(0) => m_axis_s2mm_sts_tdata(0), + mask_fsync_out_i => mask_fsync_out_i, + \out\ => \out\, + p_26_out => p_26_out, + p_2_out => p_2_out, + prmtr_update_complete => prmtr_update_complete, + prmtr_updt_complete_i_reg => prmtr_updt_complete_i_reg, + \reg_module_hsize_reg[15]\(15 downto 0) => \reg_module_hsize_reg[15]\(15 downto 0), + \reg_module_vsize_reg[12]\(12 downto 0) => \reg_module_vsize_reg[12]\(12 downto 0), + s2mm_cdc2dmac_fsync => s2mm_cdc2dmac_fsync, + s2mm_dmasr(0) => s2mm_dmasr(0), + \stride_vid_reg[0]\ => \^s2mm_valid_video_prmtrs\, + tstvect_fsync_d1 => tstvect_fsync_d1, + tstvect_fsync_d2 => tstvect_fsync_d2, + zero_hsize_err0 => zero_hsize_err0, + zero_vsize_err0 => zero_vsize_err0 + ); +\initial_frame_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00E0" + ) + port map ( + I0 => \^initial_frame\, + I1 => s2mm_cdc2dmac_fsync, + I2 => \out\, + I3 => s2mm_dmasr(0), + O => \initial_frame_i_1__0_n_0\ + ); +initial_frame_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \initial_frame_i_1__0_n_0\, + Q => \^initial_frame\, + R => '0' + ); +\num_fstore_minus1_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => '1', + Q => \^num_fstore_minus1\(0), + R => SR(0) + ); +stop_reg: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => stop_i, + Q => \^s2mm_stop\, + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_if is + port ( + D : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + mm2s_introut : out STD_LOGIC; + s2mm_introut : out STD_LOGIC; + s_axi_lite_awready : out STD_LOGIC; + s_axi_lite_wready : out STD_LOGIC; + s_axi_lite_arready : out STD_LOGIC; + dmacr_i : out STD_LOGIC_VECTOR ( 0 to 0 ); + mm2s_axi2ip_wrce : out STD_LOGIC_VECTOR ( 8 downto 0 ); + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + in0 : out STD_LOGIC_VECTOR ( 28 downto 0 ); + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]\ : out STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]\ : out STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]\ : out STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]\ : out STD_LOGIC; + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_0\ : out STD_LOGIC; + p_15_out : out STD_LOGIC; + s2mm_axi2ip_wrce : out STD_LOGIC_VECTOR ( 9 downto 0 ); + p_14_out : out STD_LOGIC; + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + prmtr_updt_complete_i_reg : out STD_LOGIC; + prmtr_updt_complete_i_reg_0 : out STD_LOGIC; + ioc_irq_reg : out STD_LOGIC; + dly_irq_reg : out STD_LOGIC; + dma_interr_reg : out STD_LOGIC; + \GEN_FOR_FLUSH.fsize_err_reg\ : out STD_LOGIC; + lsize_err_reg : out STD_LOGIC; + \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg\ : out STD_LOGIC; + ioc_irq_reg_0 : out STD_LOGIC; + dly_irq_reg_0 : out STD_LOGIC; + lsize_more_err_reg : out STD_LOGIC; + s_axi_lite_bvalid : out STD_LOGIC; + s_axi_lite_rvalid : out STD_LOGIC; + s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_lite_aclk : in STD_LOGIC; + prmry_reset2 : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + prmry_reset2_0 : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + p_78_out : in STD_LOGIC; + s2mm_ip2axi_introut : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \ptr_ref_i_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \MM2S_ERR_FOR_IRQ.frm_store_i_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + s_axi_lite_wvalid : in STD_LOGIC; + s_axi_lite_awvalid : in STD_LOGIC; + s_axi_lite_arvalid : in STD_LOGIC; + s_axi_lite_resetn : in STD_LOGIC; + p_71_out : in STD_LOGIC_VECTOR ( 17 downto 0 ); + mm2s_prmry_resetn : in STD_LOGIC; + stop : in STD_LOGIC; + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_reg\ : in STD_LOGIC; + \reg_module_hsize_reg[0]\ : in STD_LOGIC; + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\ : in STD_LOGIC_VECTOR ( 28 downto 0 ); + \reg_module_hsize_reg[3]\ : in STD_LOGIC; + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\ : in STD_LOGIC_VECTOR ( 28 downto 0 ); + \reg_module_hsize_reg[4]\ : in STD_LOGIC; + \reg_module_hsize_reg[5]\ : in STD_LOGIC; + \reg_module_hsize_reg[6]\ : in STD_LOGIC; + \reg_module_hsize_reg[7]\ : in STD_LOGIC; + \reg_module_hsize_reg[8]\ : in STD_LOGIC; + \reg_module_hsize_reg[9]\ : in STD_LOGIC; + \reg_module_hsize_reg[10]\ : in STD_LOGIC; + \reg_module_hsize_reg[11]\ : in STD_LOGIC; + \reg_module_hsize_reg[12]\ : in STD_LOGIC; + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\ : in STD_LOGIC_VECTOR ( 18 downto 0 ); + \reg_module_hsize_reg[15]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + p_70_out : in STD_LOGIC; + dma_interr_reg_0 : in STD_LOGIC; + \M_GEN_DMACR_REGISTER.dmacr_i_reg[14]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + dma_slverr_reg : in STD_LOGIC; + dma_decerr_reg : in STD_LOGIC; + ioc_irq_reg_1 : in STD_LOGIC; + dly_irq_reg_1 : in STD_LOGIC; + err_irq_reg : in STD_LOGIC; + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + ch1_irqdelay_status : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s2mm_dmacr : in STD_LOGIC_VECTOR ( 22 downto 0 ); + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31]_0\ : in STD_LOGIC; + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[23]\ : in STD_LOGIC; + s2mm_prmry_resetn : in STD_LOGIC; + s2mm_dmasr : in STD_LOGIC_VECTOR ( 0 to 0 ); + \DMA_IRQ_MASK_GEN.dma_irq_mask_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \reg_module_vsize_reg[12]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + s2mm_soft_reset : in STD_LOGIC; + \reg_module_hsize_reg[15]_0\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + ch2_irqdelay_status : in STD_LOGIC_VECTOR ( 7 downto 0 ); + dma_interr_reg_1 : in STD_LOGIC; + dma_slverr_reg_0 : in STD_LOGIC; + dma_decerr_reg_0 : in STD_LOGIC; + \GEN_FOR_FLUSH.fsize_err_reg_0\ : in STD_LOGIC; + lsize_err_reg_0 : in STD_LOGIC; + \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); + \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg_0\ : in STD_LOGIC; + ioc_irq_reg_2 : in STD_LOGIC; + dly_irq_reg_2 : in STD_LOGIC; + err_irq_reg_0 : in STD_LOGIC; + lsize_more_err_reg_0 : in STD_LOGIC; + mm2s_ioc_irq_set : in STD_LOGIC; + ch1_dly_irq_set : in STD_LOGIC; + s2mm_dma_interr_set_minus_frame_errors : in STD_LOGIC; + s2mm_fsize_more_or_sof_late : in STD_LOGIC; + fsize_mismatch_err : in STD_LOGIC; + lsize_mismatch_err : in STD_LOGIC; + s2mm_ioc_irq_set : in STD_LOGIC; + ch2_dly_irq_set : in STD_LOGIC; + lsize_more_mismatch_err : in STD_LOGIC; + s_axi_lite_bready : in STD_LOGIC; + s_axi_lite_rready : in STD_LOGIC; + s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 5 downto 0 ); + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 5 downto 0 ); + \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \DYNAMIC_MASTER_MODE_FRAME_CNT.genlock_pair_frame_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_if : entity is "axi_vdma_reg_if"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_if; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_if is + signal mm2s_chnl_current_frame_cdc_tig : STD_LOGIC_VECTOR ( 4 downto 0 ); + attribute async_reg : string; + attribute async_reg of mm2s_chnl_current_frame_cdc_tig : signal is "true"; + signal mm2s_genlock_pair_frame_cdc_tig : STD_LOGIC_VECTOR ( 4 downto 0 ); + attribute async_reg of mm2s_genlock_pair_frame_cdc_tig : signal is "true"; + signal mm2s_ip2axi_frame_ptr_ref_cdc_tig : STD_LOGIC_VECTOR ( 4 downto 0 ); + attribute async_reg of mm2s_ip2axi_frame_ptr_ref_cdc_tig : signal is "true"; + signal mm2s_ip2axi_frame_store_cdc_tig : STD_LOGIC_VECTOR ( 4 downto 0 ); + attribute async_reg of mm2s_ip2axi_frame_store_cdc_tig : signal is "true"; + signal s2mm_capture_dm_done_vsize_counter_cdc_tig : STD_LOGIC_VECTOR ( 12 downto 0 ); + attribute async_reg of s2mm_capture_dm_done_vsize_counter_cdc_tig : signal is "true"; + signal s2mm_capture_hsize_at_uf_err_cdc_tig : STD_LOGIC_VECTOR ( 15 downto 0 ); + attribute async_reg of s2mm_capture_hsize_at_uf_err_cdc_tig : signal is "true"; + signal s2mm_chnl_current_frame_cdc_tig : STD_LOGIC_VECTOR ( 4 downto 0 ); + attribute async_reg of s2mm_chnl_current_frame_cdc_tig : signal is "true"; + signal s2mm_genlock_pair_frame_cdc_tig : STD_LOGIC_VECTOR ( 4 downto 0 ); + attribute async_reg of s2mm_genlock_pair_frame_cdc_tig : signal is "true"; + signal s2mm_ip2axi_frame_ptr_ref_cdc_tig : STD_LOGIC_VECTOR ( 4 downto 0 ); + attribute async_reg of s2mm_ip2axi_frame_ptr_ref_cdc_tig : signal is "true"; + signal s2mm_ip2axi_frame_store_cdc_tig : STD_LOGIC_VECTOR ( 4 downto 0 ); + attribute async_reg of s2mm_ip2axi_frame_store_cdc_tig : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[0]\ : label is std.standard.true; + attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[0]\ : label is std.standard.true; + attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[0]\ : label is std.standard.true; + attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[0]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[10]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[10]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[11]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[11]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[12]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[12]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[5]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[5]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[6]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[6]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[7]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[7]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[8]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[8]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[9]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[9]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[0]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[10]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[10]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[11]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[11]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[12]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[12]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[13]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[13]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[14]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[14]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[15]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[15]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[5]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[5]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[6]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[6]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[7]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[7]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[8]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[8]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[9]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[9]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[0]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[0]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[0]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[0]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4]\ : label is "yes"; +begin +\GEN_AXI_LITE_IF.AXI_LITE_IF_I\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_lite_if + port map ( + D(31 downto 0) => D(31 downto 0), + \DMA_IRQ_MASK_GEN.dma_irq_mask_i_reg[3]\(3 downto 0) => \DMA_IRQ_MASK_GEN.dma_irq_mask_i_reg[3]\(3 downto 0), + \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(15 downto 0) => \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(15 downto 0), + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31]\(31 downto 0) => \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31]\(31 downto 0), + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31]_0\ => \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31]_0\, + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]\(0) => \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]\(0), + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]_0\(0) => \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]_0\(0), + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[23]\ => \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[23]\, + \GEN_FOR_FLUSH.fsize_err_reg\ => \GEN_FOR_FLUSH.fsize_err_reg\, + \GEN_FOR_FLUSH.fsize_err_reg_0\ => \GEN_FOR_FLUSH.fsize_err_reg_0\, + \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg\ => \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg\, + \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg_0\ => \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg_0\, + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_reg\ => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_reg\, + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\(7 downto 0) => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\(7 downto 0), + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]\(7 downto 0) => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]\(7 downto 0), + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]_0\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]_0\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_0\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_1\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_0\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]_0\ => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]_0\(31 downto 0) => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(31 downto 0), + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(4 downto 0) => mm2s_ip2axi_frame_ptr_ref_cdc_tig(4 downto 0), + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\(4 downto 0) => mm2s_ip2axi_frame_store_cdc_tig(4 downto 0), + \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14]\(6 downto 0) => \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14]\(6 downto 0), + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(18 downto 0) => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(18 downto 0), + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(31 downto 0) => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(31 downto 0), + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(31 downto 0) => \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(31 downto 0), + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(28 downto 0) => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(28 downto 0), + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(31 downto 0) => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(31 downto 0), + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(31 downto 0) => \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(31 downto 0), + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(28 downto 0) => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(28 downto 0), + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(31 downto 0) => \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(31 downto 0), + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(4 downto 0) => s2mm_ip2axi_frame_ptr_ref_cdc_tig(4 downto 0), + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4]\(4 downto 0) => s2mm_ip2axi_frame_store_cdc_tig(4 downto 0), + \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(2 downto 0) => \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(2 downto 0), + \M_GEN_DMACR_REGISTER.dmacr_i_reg[14]\(4 downto 0) => \M_GEN_DMACR_REGISTER.dmacr_i_reg[14]\(4 downto 0), + SR(0) => SR(0), + ch1_dly_irq_set => ch1_dly_irq_set, + ch1_irqdelay_status(7 downto 0) => ch1_irqdelay_status(7 downto 0), + ch2_dly_irq_set => ch2_dly_irq_set, + ch2_irqdelay_status(7 downto 0) => ch2_irqdelay_status(7 downto 0), + dly_irq_reg => dly_irq_reg, + dly_irq_reg_0 => dly_irq_reg_0, + dly_irq_reg_1 => dly_irq_reg_1, + dly_irq_reg_2 => dly_irq_reg_2, + dma_decerr_reg => dma_decerr_reg, + dma_decerr_reg_0 => dma_decerr_reg_0, + dma_interr_reg => dma_interr_reg, + dma_interr_reg_0 => s2mm_axi2ip_wrce(2), + dma_interr_reg_1 => dma_interr_reg_0, + dma_interr_reg_2 => dma_interr_reg_1, + dma_slverr_reg => dma_slverr_reg, + dma_slverr_reg_0 => dma_slverr_reg_0, + dmacr_i(0) => dmacr_i(0), + \dmacr_i_reg[1]\ => s2mm_axi2ip_wrce(1), + err_irq_reg => err_irq_reg, + err_irq_reg_0 => err_irq_reg_0, + fsize_mismatch_err => fsize_mismatch_err, + in0(28 downto 0) => in0(28 downto 0), + ioc_irq_reg => ioc_irq_reg, + ioc_irq_reg_0 => ioc_irq_reg_0, + ioc_irq_reg_1 => ioc_irq_reg_1, + ioc_irq_reg_2 => ioc_irq_reg_2, + lsize_err_reg => lsize_err_reg, + lsize_err_reg_0 => lsize_err_reg_0, + lsize_mismatch_err => lsize_mismatch_err, + lsize_more_err_reg => lsize_more_err_reg, + lsize_more_err_reg_0 => lsize_more_err_reg_0, + lsize_more_mismatch_err => lsize_more_mismatch_err, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + mm2s_axi2ip_wrce(8 downto 0) => mm2s_axi2ip_wrce(8 downto 0), + mm2s_ioc_irq_set => mm2s_ioc_irq_set, + mm2s_prmry_resetn => mm2s_prmry_resetn, + \out\(1 downto 0) => \out\(1 downto 0), + p_14_out => p_14_out, + p_15_out => p_15_out, + p_70_out => p_70_out, + p_71_out(17 downto 0) => p_71_out(17 downto 0), + prmry_reset2 => prmry_reset2, + prmry_reset2_0 => prmry_reset2_0, + prmtr_updt_complete_i_reg => prmtr_updt_complete_i_reg, + prmtr_updt_complete_i_reg_0 => prmtr_updt_complete_i_reg_0, + \reg_module_hsize_reg[0]\ => \reg_module_hsize_reg[0]\, + \reg_module_hsize_reg[10]\ => \reg_module_hsize_reg[10]\, + \reg_module_hsize_reg[11]\ => \reg_module_hsize_reg[11]\, + \reg_module_hsize_reg[12]\ => \reg_module_hsize_reg[12]\, + \reg_module_hsize_reg[15]\(2 downto 0) => \reg_module_hsize_reg[15]\(2 downto 0), + \reg_module_hsize_reg[15]_0\(15 downto 0) => \reg_module_hsize_reg[15]_0\(15 downto 0), + \reg_module_hsize_reg[3]\ => \reg_module_hsize_reg[3]\, + \reg_module_hsize_reg[4]\ => \reg_module_hsize_reg[4]\, + \reg_module_hsize_reg[5]\ => \reg_module_hsize_reg[5]\, + \reg_module_hsize_reg[6]\ => \reg_module_hsize_reg[6]\, + \reg_module_hsize_reg[7]\ => \reg_module_hsize_reg[7]\, + \reg_module_hsize_reg[8]\ => \reg_module_hsize_reg[8]\, + \reg_module_hsize_reg[9]\ => \reg_module_hsize_reg[9]\, + \reg_module_vsize_reg[12]\(12 downto 0) => \reg_module_vsize_reg[12]\(12 downto 0), + s2mm_axi2ip_wrce(7 downto 1) => s2mm_axi2ip_wrce(9 downto 3), + s2mm_axi2ip_wrce(0) => s2mm_axi2ip_wrce(0), + s2mm_dma_interr_set_minus_frame_errors => s2mm_dma_interr_set_minus_frame_errors, + s2mm_dmacr(22 downto 0) => s2mm_dmacr(22 downto 0), + s2mm_dmasr(0) => s2mm_dmasr(0), + s2mm_fsize_more_or_sof_late => s2mm_fsize_more_or_sof_late, + s2mm_ioc_irq_set => s2mm_ioc_irq_set, + s2mm_prmry_resetn => s2mm_prmry_resetn, + s2mm_soft_reset => s2mm_soft_reset, + s_axi_lite_aclk => s_axi_lite_aclk, + s_axi_lite_araddr(5 downto 0) => s_axi_lite_araddr(5 downto 0), + s_axi_lite_arready => s_axi_lite_arready, + s_axi_lite_arvalid => s_axi_lite_arvalid, + s_axi_lite_awaddr(5 downto 0) => s_axi_lite_awaddr(5 downto 0), + s_axi_lite_awready => s_axi_lite_awready, + s_axi_lite_awvalid => s_axi_lite_awvalid, + s_axi_lite_bready => s_axi_lite_bready, + s_axi_lite_bvalid => s_axi_lite_bvalid, + s_axi_lite_rdata(31 downto 0) => s_axi_lite_rdata(31 downto 0), + s_axi_lite_resetn => s_axi_lite_resetn, + s_axi_lite_rready => s_axi_lite_rready, + s_axi_lite_rvalid => s_axi_lite_rvalid, + s_axi_lite_wdata(31 downto 0) => s_axi_lite_wdata(31 downto 0), + s_axi_lite_wready => s_axi_lite_wready, + s_axi_lite_wvalid => s_axi_lite_wvalid, + stop => stop + ); +\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.MM2S_INTRPT_CROSSING_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized8\ + port map ( + SR(0) => SR(0), + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + mm2s_introut => mm2s_introut, + p_78_out => p_78_out, + prmry_reset2 => prmry_reset2, + s_axi_lite_aclk => s_axi_lite_aclk + ); +\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]\(0), + Q => mm2s_chnl_current_frame_cdc_tig(0), + R => '0' + ); +\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]\(1), + Q => mm2s_chnl_current_frame_cdc_tig(1), + R => '0' + ); +\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]\(2), + Q => mm2s_chnl_current_frame_cdc_tig(2), + R => '0' + ); +\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]\(3), + Q => mm2s_chnl_current_frame_cdc_tig(3), + R => '0' + ); +\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]\(4), + Q => mm2s_chnl_current_frame_cdc_tig(4), + R => '0' + ); +\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => mm2s_genlock_pair_frame_cdc_tig(0), + R => '0' + ); +\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => mm2s_genlock_pair_frame_cdc_tig(1), + R => '0' + ); +\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => mm2s_genlock_pair_frame_cdc_tig(2), + R => '0' + ); +\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => mm2s_genlock_pair_frame_cdc_tig(3), + R => '0' + ); +\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_genlock_pair_frame_cdc_tig_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => mm2s_genlock_pair_frame_cdc_tig(4), + R => '0' + ); +\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => Q(0), + Q => mm2s_ip2axi_frame_ptr_ref_cdc_tig(0), + R => '0' + ); +\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => Q(1), + Q => mm2s_ip2axi_frame_ptr_ref_cdc_tig(1), + R => '0' + ); +\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => Q(2), + Q => mm2s_ip2axi_frame_ptr_ref_cdc_tig(2), + R => '0' + ); +\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => Q(3), + Q => mm2s_ip2axi_frame_ptr_ref_cdc_tig(3), + R => '0' + ); +\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => Q(4), + Q => mm2s_ip2axi_frame_ptr_ref_cdc_tig(4), + R => '0' + ); +\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \MM2S_ERR_FOR_IRQ.frm_store_i_reg[4]\(0), + Q => mm2s_ip2axi_frame_store_cdc_tig(0), + R => '0' + ); +\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \MM2S_ERR_FOR_IRQ.frm_store_i_reg[4]\(1), + Q => mm2s_ip2axi_frame_store_cdc_tig(1), + R => '0' + ); +\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \MM2S_ERR_FOR_IRQ.frm_store_i_reg[4]\(2), + Q => mm2s_ip2axi_frame_store_cdc_tig(2), + R => '0' + ); +\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \MM2S_ERR_FOR_IRQ.frm_store_i_reg[4]\(3), + Q => mm2s_ip2axi_frame_store_cdc_tig(3), + R => '0' + ); +\GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \MM2S_ERR_FOR_IRQ.frm_store_i_reg[4]\(4), + Q => mm2s_ip2axi_frame_store_cdc_tig(4), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.S2MM_INTRPT_CROSSING_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized9\ + port map ( + SR(0) => SR(0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + prmry_reset2_0 => prmry_reset2_0, + s2mm_introut => s2mm_introut, + s2mm_ip2axi_introut => s2mm_ip2axi_introut, + s_axi_lite_aclk => s_axi_lite_aclk + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => s2mm_capture_dm_done_vsize_counter_cdc_tig(0), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => s2mm_capture_dm_done_vsize_counter_cdc_tig(10), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => s2mm_capture_dm_done_vsize_counter_cdc_tig(11), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => s2mm_capture_dm_done_vsize_counter_cdc_tig(12), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => s2mm_capture_dm_done_vsize_counter_cdc_tig(1), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => s2mm_capture_dm_done_vsize_counter_cdc_tig(2), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => s2mm_capture_dm_done_vsize_counter_cdc_tig(3), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => s2mm_capture_dm_done_vsize_counter_cdc_tig(4), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => s2mm_capture_dm_done_vsize_counter_cdc_tig(5), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => s2mm_capture_dm_done_vsize_counter_cdc_tig(6), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => s2mm_capture_dm_done_vsize_counter_cdc_tig(7), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => s2mm_capture_dm_done_vsize_counter_cdc_tig(8), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_dm_done_vsize_counter_cdc_tig_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => s2mm_capture_dm_done_vsize_counter_cdc_tig(9), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => s2mm_capture_hsize_at_uf_err_cdc_tig(0), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => s2mm_capture_hsize_at_uf_err_cdc_tig(10), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => s2mm_capture_hsize_at_uf_err_cdc_tig(11), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => s2mm_capture_hsize_at_uf_err_cdc_tig(12), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => s2mm_capture_hsize_at_uf_err_cdc_tig(13), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => s2mm_capture_hsize_at_uf_err_cdc_tig(14), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => s2mm_capture_hsize_at_uf_err_cdc_tig(15), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => s2mm_capture_hsize_at_uf_err_cdc_tig(1), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => s2mm_capture_hsize_at_uf_err_cdc_tig(2), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => s2mm_capture_hsize_at_uf_err_cdc_tig(3), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => s2mm_capture_hsize_at_uf_err_cdc_tig(4), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => s2mm_capture_hsize_at_uf_err_cdc_tig(5), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => s2mm_capture_hsize_at_uf_err_cdc_tig(6), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => s2mm_capture_hsize_at_uf_err_cdc_tig(7), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => s2mm_capture_hsize_at_uf_err_cdc_tig(8), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_capture_hsize_at_uf_err_cdc_tig_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => '0', + Q => s2mm_capture_hsize_at_uf_err_cdc_tig(9), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]\(0), + Q => s2mm_chnl_current_frame_cdc_tig(0), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]\(1), + Q => s2mm_chnl_current_frame_cdc_tig(1), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]\(2), + Q => s2mm_chnl_current_frame_cdc_tig(2), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]\(3), + Q => s2mm_chnl_current_frame_cdc_tig(3), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]\(4), + Q => s2mm_chnl_current_frame_cdc_tig(4), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \DYNAMIC_MASTER_MODE_FRAME_CNT.genlock_pair_frame_reg[4]\(0), + Q => s2mm_genlock_pair_frame_cdc_tig(0), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \DYNAMIC_MASTER_MODE_FRAME_CNT.genlock_pair_frame_reg[4]\(1), + Q => s2mm_genlock_pair_frame_cdc_tig(1), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \DYNAMIC_MASTER_MODE_FRAME_CNT.genlock_pair_frame_reg[4]\(2), + Q => s2mm_genlock_pair_frame_cdc_tig(2), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \DYNAMIC_MASTER_MODE_FRAME_CNT.genlock_pair_frame_reg[4]\(3), + Q => s2mm_genlock_pair_frame_cdc_tig(3), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \DYNAMIC_MASTER_MODE_FRAME_CNT.genlock_pair_frame_reg[4]\(4), + Q => s2mm_genlock_pair_frame_cdc_tig(4), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \ptr_ref_i_reg[4]\(0), + Q => s2mm_ip2axi_frame_ptr_ref_cdc_tig(0), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \ptr_ref_i_reg[4]\(1), + Q => s2mm_ip2axi_frame_ptr_ref_cdc_tig(1), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \ptr_ref_i_reg[4]\(2), + Q => s2mm_ip2axi_frame_ptr_ref_cdc_tig(2), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \ptr_ref_i_reg[4]\(3), + Q => s2mm_ip2axi_frame_ptr_ref_cdc_tig(3), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \ptr_ref_i_reg[4]\(4), + Q => s2mm_ip2axi_frame_ptr_ref_cdc_tig(4), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \S2MM_ERR_FOR_IRQ.frm_store_i_reg[4]\(0), + Q => s2mm_ip2axi_frame_store_cdc_tig(0), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \S2MM_ERR_FOR_IRQ.frm_store_i_reg[4]\(1), + Q => s2mm_ip2axi_frame_store_cdc_tig(1), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \S2MM_ERR_FOR_IRQ.frm_store_i_reg[4]\(2), + Q => s2mm_ip2axi_frame_store_cdc_tig(2), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \S2MM_ERR_FOR_IRQ.frm_store_i_reg[4]\(3), + Q => s2mm_ip2axi_frame_store_cdc_tig(3), + R => '0' + ); +\GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => \S2MM_ERR_FOR_IRQ.frm_store_i_reg[4]\(4), + Q => s2mm_ip2axi_frame_store_cdc_tig(4), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_rst_module is + port ( + \out\ : out STD_LOGIC; + \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]\ : out STD_LOGIC; + sts_tready_reg : out STD_LOGIC; + \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0_0\ : out STD_LOGIC; + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ : out STD_LOGIC; + soft_reset_d1 : out STD_LOGIC; + prmry_in : out STD_LOGIC; + mm2s_halt : out STD_LOGIC; + run_stop_d1 : out STD_LOGIC; + s2mm_halt : out STD_LOGIC; + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + prmry_reset2 : out STD_LOGIC; + prmry_reset2_0 : out STD_LOGIC; + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \dmacr_i_reg[2]\ : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \dmacr_i_reg[2]_0\ : out STD_LOGIC; + prmry_reset2_1 : out STD_LOGIC; + p_12_out : out STD_LOGIC; + \FSM_sequential_dmacntrl_cs_reg[2]\ : out STD_LOGIC; + halt_reset : out STD_LOGIC; + halt_reset_2 : out STD_LOGIC; + WR_EN : out STD_LOGIC; + \cmnds_queued_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \cmnds_queued_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_reg\ : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.s_axis_fifo_ainit_nosync_reg_reg\ : out STD_LOGIC; + sig_s_h_halt_reg_reg : out STD_LOGIC; + reset_counts_reg : out STD_LOGIC; + reset_counts_reg_0 : out STD_LOGIC; + sig_s_h_halt_reg_reg_0 : out STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + s_axi_lite_aclk : in STD_LOGIC; + m_axis_mm2s_aclk : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC; + p_77_out : in STD_LOGIC; + s_soft_reset_i0 : in STD_LOGIC; + s2mm_soft_reset : in STD_LOGIC; + s_soft_reset_i0_3 : in STD_LOGIC; + axi_resetn : in STD_LOGIC; + stop : in STD_LOGIC; + p_71_out : in STD_LOGIC_VECTOR ( 0 to 0 ); + s2mm_dmacr : in STD_LOGIC_VECTOR ( 0 to 0 ); + s2mm_stop : in STD_LOGIC; + mm2s_axi2ip_wrce : in STD_LOGIC_VECTOR ( 0 to 0 ); + D : in STD_LOGIC_VECTOR ( 0 to 0 ); + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : in STD_LOGIC; + p_15_out : in STD_LOGIC; + s2mm_axi2ip_wrce : in STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + CO : in STD_LOGIC_VECTOR ( 0 to 0 ); + dma_err : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + halt_i0 : in STD_LOGIC; + hold_ff_q_reg : in STD_LOGIC; + p_24_out : in STD_LOGIC; + sig_s_ready_out_reg : in STD_LOGIC; + FULL : in STD_LOGIC; + dma_err_4 : in STD_LOGIC; + d_tready_before_fsync_clr_flag1 : in STD_LOGIC; + d_tready_before_fsync : in STD_LOGIC; + s2mm_dmasr_halted_s : in STD_LOGIC; + sig_rst2all_stop_request : in STD_LOGIC; + reset_counts : in STD_LOGIC; + reset_counts_5 : in STD_LOGIC; + sig_rst2all_stop_request_6 : in STD_LOGIC; + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\ : in STD_LOGIC; + \cmnds_queued_reg[0]\ : in STD_LOGIC; + mm2s_halt_cmplt : in STD_LOGIC; + s2mm_halt_cmplt : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_rst_module : entity is "axi_vdma_rst_module"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_rst_module; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_rst_module is + signal \^prmry_in\ : STD_LOGIC; + signal sig_mm2s_axis_resetn : STD_LOGIC; + attribute RTL_KEEP : string; + attribute RTL_KEEP of sig_mm2s_axis_resetn : signal is "true"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of sig_mm2s_axis_resetn : signal is "no"; + signal sig_mm2s_dm_prmry_resetn : STD_LOGIC; + attribute RTL_KEEP of sig_mm2s_dm_prmry_resetn : signal is "true"; + attribute equivalent_register_removal of sig_mm2s_dm_prmry_resetn : signal is "no"; + signal sig_mm2s_prmry_resetn : STD_LOGIC; + attribute RTL_KEEP of sig_mm2s_prmry_resetn : signal is "true"; + attribute equivalent_register_removal of sig_mm2s_prmry_resetn : signal is "no"; + signal sig_s2mm_axis_resetn : STD_LOGIC; + attribute RTL_KEEP of sig_s2mm_axis_resetn : signal is "true"; + attribute equivalent_register_removal of sig_s2mm_axis_resetn : signal is "no"; + signal sig_s2mm_dm_prmry_resetn : STD_LOGIC; + attribute RTL_KEEP of sig_s2mm_dm_prmry_resetn : signal is "true"; + attribute equivalent_register_removal of sig_s2mm_dm_prmry_resetn : signal is "no"; + signal sig_s2mm_prmry_resetn : STD_LOGIC; + attribute RTL_KEEP of sig_s2mm_prmry_resetn : signal is "true"; + attribute equivalent_register_removal of sig_s2mm_prmry_resetn : signal is "no"; +begin + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ <= sig_s2mm_axis_resetn; + \GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]\ <= sig_mm2s_axis_resetn; + \out\ <= sig_mm2s_prmry_resetn; + prmry_in <= \^prmry_in\; + \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ <= sig_mm2s_dm_prmry_resetn; + \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0_0\ <= sig_s2mm_dm_prmry_resetn; + sts_tready_reg <= sig_s2mm_prmry_resetn; +\GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out[5]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => sig_mm2s_axis_resetn, + O => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_0\(0) + ); +\GEN_CDC_FOR_ASYNC.cdc2top_frame_ptr_out[5]_i_1__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => sig_s2mm_axis_resetn, + O => prmry_reset2_1 + ); +\GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count[7]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => sig_mm2s_prmry_resetn, + O => \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0]\(0) + ); +\GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count[7]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => sig_s2mm_prmry_resetn, + O => \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[1]\(0) + ); +\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0D" + ) + port map ( + I0 => sig_mm2s_axis_resetn, + I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\, + I2 => p_15_out, + O => \GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]_0\(0) + ); +\GEN_RESET_FOR_MM2S.RESET_I\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_reset + port map ( + D(0) => D(0), + FULL => FULL, + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\, + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ => mm2s_halt, + \GEN_LINEBUF_NO_SOF.s_axis_fifo_ainit_nosync_reg_reg\ => \GEN_LINEBUF_NO_SOF.s_axis_fifo_ainit_nosync_reg_reg\, + WR_EN => WR_EN, + \cmnds_queued_reg[7]\(0) => \cmnds_queued_reg[7]\(0), + dma_err_4 => dma_err_4, + \dmacr_i_reg[2]\ => \dmacr_i_reg[2]\, + halt_i_reg_0 => halt_reset, + hold_ff_q_reg => hold_ff_q_reg, + in0 => sig_mm2s_prmry_resetn, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axis_mm2s_aclk => m_axis_mm2s_aclk, + mm2s_axi2ip_wrce(0) => mm2s_axi2ip_wrce(0), + mm2s_halt_cmplt => mm2s_halt_cmplt, + \out\ => sig_mm2s_prmry_resetn, + p_24_out => p_24_out, + p_71_out(0) => p_71_out(0), + p_77_out => p_77_out, + prmry_in => \^prmry_in\, + prmry_reset2 => prmry_reset2, + reset_counts => reset_counts, + reset_counts_reg => reset_counts_reg, + s_axi_lite_aclk => s_axi_lite_aclk, + s_soft_reset_i0 => s_soft_reset_i0, + scndry_out => sig_mm2s_axis_resetn, + sig_mm2s_dm_prmry_resetn => sig_mm2s_dm_prmry_resetn, + sig_rst2all_stop_request => sig_rst2all_stop_request, + sig_s_h_halt_reg_reg => sig_s_h_halt_reg_reg, + sig_s_ready_out_reg => sig_s_ready_out_reg, + stop => stop + ); +\GEN_RESET_FOR_S2MM.RESET_I\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_reset_2 + port map ( + CO(0) => CO(0), + \FSM_sequential_dmacntrl_cs_reg[2]\ => \FSM_sequential_dmacntrl_cs_reg[2]\, + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ => s2mm_halt, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[2]\(0) => \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[2]\(0), + Q(0) => Q(0), + \cmnds_queued_reg[0]\ => \cmnds_queued_reg[0]\, + \cmnds_queued_reg[7]\(0) => \cmnds_queued_reg[7]_0\(0), + dma_err => dma_err, + \dmacr_i_reg[2]\ => \dmacr_i_reg[2]_0\, + halt_i0 => halt_i0, + halt_i_reg_0 => halt_reset_2, + in0 => sig_s2mm_prmry_resetn, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\ => sig_s2mm_prmry_resetn, + p_12_out => p_12_out, + prmry_in => \^prmry_in\, + prmry_reset2_0 => prmry_reset2_0, + reset_counts_5 => reset_counts_5, + reset_counts_reg => reset_counts_reg_0, + run_stop_d1 => run_stop_d1, + s2mm_axi2ip_wrce(0) => s2mm_axi2ip_wrce(0), + s2mm_dmacr(0) => s2mm_dmacr(0), + s2mm_halt_cmplt => s2mm_halt_cmplt, + s2mm_soft_reset => s2mm_soft_reset, + s2mm_stop => s2mm_stop, + s_axi_lite_aclk => s_axi_lite_aclk, + s_axis_s2mm_aclk => s_axis_s2mm_aclk, + s_soft_reset_i0_3 => s_soft_reset_i0_3, + scndry_out => sig_s2mm_axis_resetn, + sig_rst2all_stop_request_6 => sig_rst2all_stop_request_6, + sig_s2mm_dm_prmry_resetn => sig_s2mm_dm_prmry_resetn, + sig_s_h_halt_reg_reg => sig_s_h_halt_reg_reg_0, + soft_reset_d1 => soft_reset_d1 + ); +\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => d_tready_before_fsync_clr_flag1, + I1 => d_tready_before_fsync, + I2 => sig_s2mm_axis_resetn, + I3 => s2mm_dmasr_halted_s, + O => \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_reg\ + ); +awready_out_i_i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^prmry_in\, + O => SR(0) + ); +hrd_resetn_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => s_axi_lite_aclk, + CE => '1', + D => axi_resetn, + Q => \^prmry_in\, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_srl_fifo_f is + port ( + sig_calc_error_reg_reg : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axis_cmd_tvalid_reg : out STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : out STD_LOGIC_VECTOR ( 49 downto 0 ); + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_psm_halt : in STD_LOGIC; + sig_input_reg_empty : in STD_LOGIC; + p_10_out : in STD_LOGIC; + cmnd_wr_1 : in STD_LOGIC; + sig_inhibit_rdy_n : in STD_LOGIC; + s2mm_halt : in STD_LOGIC; + s_axis_s2mm_cmd_tvalid : in STD_LOGIC; + \s_axis_cmd_tdata_reg[63]\ : in STD_LOGIC_VECTOR ( 48 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_srl_fifo_f : entity is "srl_fifo_f"; +end Arty_Z7_20_axi_vdma_0_0_srl_fifo_f; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_srl_fifo_f is +begin +I_SRL_FIFO_RBU_F: entity work.Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f + port map ( + Q(0) => Q(0), + cmnd_wr_1 => cmnd_wr_1, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\(49 downto 0) => \out\(49 downto 0), + p_10_out => p_10_out, + s2mm_halt => s2mm_halt, + \s_axis_cmd_tdata_reg[63]\(48 downto 0) => \s_axis_cmd_tdata_reg[63]\(48 downto 0), + s_axis_cmd_tvalid_reg(0) => s_axis_cmd_tvalid_reg(0), + s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid, + sig_calc_error_reg_reg => sig_calc_error_reg_reg, + sig_inhibit_rdy_n => sig_inhibit_rdy_n, + sig_input_reg_empty => sig_input_reg_empty, + sig_psm_halt => sig_psm_halt, + sig_stream_rst => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_srl_fifo_f_23 is + port ( + sig_calc_error_reg_reg : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 0 to 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : out STD_LOGIC_VECTOR ( 49 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_sm_halt_reg : in STD_LOGIC; + sig_input_reg_empty : in STD_LOGIC; + cmnd_wr : in STD_LOGIC; + sig_inhibit_rdy_n : in STD_LOGIC; + mm2s_halt : in STD_LOGIC; + sig_calc_error_pushed_reg : in STD_LOGIC; + sig_calc_error_pushed : in STD_LOGIC; + p_56_out : in STD_LOGIC; + \s_axis_cmd_tdata_reg[63]\ : in STD_LOGIC_VECTOR ( 48 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_srl_fifo_f_23 : entity is "srl_fifo_f"; +end Arty_Z7_20_axi_vdma_0_0_srl_fifo_f_23; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_srl_fifo_f_23 is +begin +I_SRL_FIFO_RBU_F: entity work.Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f_24 + port map ( + E(0) => E(0), + Q(0) => Q(0), + SR(0) => SR(0), + cmnd_wr => cmnd_wr, + \in\(0) => \in\(0), + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + mm2s_halt => mm2s_halt, + \out\(49 downto 0) => \out\(49 downto 0), + p_56_out => p_56_out, + \s_axis_cmd_tdata_reg[63]\(48 downto 0) => \s_axis_cmd_tdata_reg[63]\(48 downto 0), + sig_calc_error_pushed => sig_calc_error_pushed, + sig_calc_error_pushed_reg => sig_calc_error_pushed_reg, + sig_calc_error_reg_reg => sig_calc_error_reg_reg, + sig_inhibit_rdy_n => sig_inhibit_rdy_n, + sig_input_reg_empty => sig_input_reg_empty, + sig_sm_halt_reg => sig_sm_halt_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized0\ is + port ( + \INFERRED_GEN.cnt_i_reg[1]\ : out STD_LOGIC; + sig_rd_sts_slverr_reg_reg : out STD_LOGIC; + decerr_i_reg : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 0 to 0 ); + slverr_i_reg : out STD_LOGIC; + interr_i_reg : out STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + sig_inhibit_rdy_n_reg : in STD_LOGIC; + sig_rsc2stat_status_valid : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + p_58_out : in STD_LOGIC; + sts_tready_reg : in STD_LOGIC; + sig_rd_sts_slverr_reg_reg_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized0\ : entity is "srl_fifo_f"; +end \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized0\ is +begin +I_SRL_FIFO_RBU_F: entity work.\Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized0\ + port map ( + \INFERRED_GEN.cnt_i_reg[1]\ => \INFERRED_GEN.cnt_i_reg[1]\, + Q(0) => Q(0), + SR(0) => SR(0), + decerr_i_reg => decerr_i_reg, + interr_i_reg => interr_i_reg, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + p_58_out => p_58_out, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_inhibit_rdy_n_reg => sig_inhibit_rdy_n_reg, + sig_rd_sts_slverr_reg_reg => sig_rd_sts_slverr_reg_reg, + sig_rd_sts_slverr_reg_reg_0(2 downto 0) => sig_rd_sts_slverr_reg_reg_0(2 downto 0), + sig_rsc2stat_status_valid => sig_rsc2stat_status_valid, + slverr_i_reg => slverr_i_reg, + sts_tready_reg => sts_tready_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized1\ is + port ( + sig_addr_valid_reg_reg : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 40 downto 0 ); + sig_posted_to_axi_2_reg : out STD_LOGIC; + sig_calc_error_reg_reg : out STD_LOGIC; + sig_addr_reg_empty_reg : out STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + sig_addr_reg_empty : in STD_LOGIC; + sig_sf_allow_addr_req : in STD_LOGIC; + sig_data2addr_stop_req : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_inhibit_rdy_n : in STD_LOGIC; + sig_mstr2addr_cmd_valid : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 38 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized1\ : entity is "srl_fifo_f"; +end \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized1\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized1\ is +begin +I_SRL_FIFO_RBU_F: entity work.\Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized1\ + port map ( + SR(0) => SR(0), + \in\(38 downto 0) => \in\(38 downto 0), + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + \out\(40 downto 0) => \out\(40 downto 0), + sel => sig_calc_error_reg_reg, + sig_addr_reg_empty => sig_addr_reg_empty, + sig_addr_reg_empty_reg => sig_addr_reg_empty_reg, + sig_addr_valid_reg_reg => sig_addr_valid_reg_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_data2addr_stop_req => sig_data2addr_stop_req, + sig_inhibit_rdy_n => sig_inhibit_rdy_n, + sig_mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid, + sig_posted_to_axi_2_reg => sig_posted_to_axi_2_reg, + sig_sf_allow_addr_req => sig_sf_allow_addr_req + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized10\ is + port ( + \INFERRED_GEN.cnt_i_reg[0]\ : out STD_LOGIC; + sig_last_dbeat_reg : out STD_LOGIC; + sig_dqual_reg_empty_reg : out STD_LOGIC; + sig_ld_new_cmd_reg_reg : out STD_LOGIC; + sig_next_calc_error_reg_reg : out STD_LOGIC; + sig_dqual_reg_empty_reg_0 : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 7 downto 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_dqual_reg_empty_reg_1 : out STD_LOGIC; + \sig_clr_cmd2data_valid4_out__0\ : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + \sig_first_dbeat1__0\ : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_single_dbeat : in STD_LOGIC; + sig_last_dbeat_reg_0 : in STD_LOGIC; + sig_ld_new_cmd_reg : in STD_LOGIC; + sig_next_calc_error_reg : in STD_LOGIC; + \sig_dbeat_cntr_reg[1]\ : in STD_LOGIC; + sig_dqual_reg_full_reg : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \sig_dbeat_cntr_reg[4]\ : in STD_LOGIC; + p_11_out : in STD_LOGIC; + sig_inhibit_rdy_n_reg : in STD_LOGIC; + \sig_dbeat_cntr_reg[2]\ : in STD_LOGIC; + \sig_dbeat_cntr_reg[3]\ : in STD_LOGIC; + sig_next_sequential_reg : in STD_LOGIC; + sig_dqual_reg_empty : in STD_LOGIC; + sig_halt_reg : in STD_LOGIC; + sig_m_valid_out_reg : in STD_LOGIC; + sig_s_ready_out_reg : in STD_LOGIC; + sig_wdc_status_going_full : in STD_LOGIC; + sig_inhibit_rdy_n_reg_0 : in STD_LOGIC; + sig_wsc2stat_status_valid : in STD_LOGIC; + sig_addr_posted_cntr : in STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_halt_reg_dly3 : in STD_LOGIC; + sig_last_mmap_dbeat_reg : in STD_LOGIC; + sig_posted_to_axi_reg : in STD_LOGIC; + sig_xfer_calc_err_reg_reg : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized10\ : entity is "srl_fifo_f"; +end \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized10\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized10\ is +begin +I_SRL_FIFO_RBU_F: entity work.\Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized10\ + port map ( + D(7 downto 0) => D(7 downto 0), + E(0) => E(0), + \INFERRED_GEN.cnt_i_reg[0]\ => \INFERRED_GEN.cnt_i_reg[0]\, + Q(7 downto 0) => Q(7 downto 0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\(2 downto 0) => \out\(2 downto 0), + p_11_out => p_11_out, + sig_addr_posted_cntr(2 downto 0) => sig_addr_posted_cntr(2 downto 0), + \sig_clr_cmd2data_valid4_out__0\ => \sig_clr_cmd2data_valid4_out__0\, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + \sig_dbeat_cntr_reg[1]\ => \sig_dbeat_cntr_reg[1]\, + \sig_dbeat_cntr_reg[2]\ => \sig_dbeat_cntr_reg[2]\, + \sig_dbeat_cntr_reg[3]\ => \sig_dbeat_cntr_reg[3]\, + \sig_dbeat_cntr_reg[4]\ => \sig_dbeat_cntr_reg[4]\, + sig_dqual_reg_empty => sig_dqual_reg_empty, + sig_dqual_reg_empty_reg => sig_dqual_reg_empty_reg, + sig_dqual_reg_empty_reg_0 => sig_dqual_reg_empty_reg_0, + sig_dqual_reg_empty_reg_1 => sig_dqual_reg_empty_reg_1, + sig_dqual_reg_full_reg => sig_dqual_reg_full_reg, + \sig_first_dbeat1__0\ => \sig_first_dbeat1__0\, + sig_halt_reg => sig_halt_reg, + sig_halt_reg_dly3 => sig_halt_reg_dly3, + sig_inhibit_rdy_n_reg => sig_inhibit_rdy_n_reg, + sig_inhibit_rdy_n_reg_0 => sig_inhibit_rdy_n_reg_0, + sig_last_dbeat_reg => sig_last_dbeat_reg, + sig_last_dbeat_reg_0 => sig_last_dbeat_reg_0, + sig_last_mmap_dbeat_reg => sig_last_mmap_dbeat_reg, + sig_ld_new_cmd_reg => sig_ld_new_cmd_reg, + sig_ld_new_cmd_reg_reg => sig_ld_new_cmd_reg_reg, + sig_m_valid_out_reg => sig_m_valid_out_reg, + sig_next_calc_error_reg => sig_next_calc_error_reg, + sig_next_calc_error_reg_reg => sig_next_calc_error_reg_reg, + sig_next_sequential_reg => sig_next_sequential_reg, + sig_posted_to_axi_reg => sig_posted_to_axi_reg, + sig_s_ready_out_reg => sig_s_ready_out_reg, + sig_single_dbeat => sig_single_dbeat, + sig_stream_rst => sig_stream_rst, + sig_wdc_status_going_full => sig_wdc_status_going_full, + sig_wsc2stat_status_valid => sig_wsc2stat_status_valid, + sig_xfer_calc_err_reg_reg(8 downto 0) => sig_xfer_calc_err_reg_reg(8 downto 0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized2\ is + port ( + D : out STD_LOGIC_VECTOR ( 7 downto 0 ); + sig_dqual_reg_empty_reg : out STD_LOGIC; + sig_next_cmd_cmplt_reg_reg : out STD_LOGIC; + sig_dqual_reg_empty_reg_0 : out STD_LOGIC; + sig_next_calc_error_reg_reg : out STD_LOGIC; + sig_last_dbeat_reg : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \sig_dbeat_cntr_reg[0]\ : in STD_LOGIC; + m_axi_mm2s_rlast : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_mstr2data_cmd_valid : in STD_LOGIC; + sig_inhibit_rdy_n_0 : in STD_LOGIC; + \sig_dbeat_cntr_reg[3]\ : in STD_LOGIC; + \sig_dbeat_cntr_reg[5]\ : in STD_LOGIC; + sig_next_sequential_reg : in STD_LOGIC; + sig_last_dbeat : in STD_LOGIC; + sig_dqual_reg_empty : in STD_LOGIC; + sig_rsc2stat_status_valid : in STD_LOGIC; + FIFO_Full_reg : in STD_LOGIC; + sig_inhibit_rdy_n : in STD_LOGIC; + sig_next_calc_error_reg_reg_0 : in STD_LOGIC; + \sig_addr_posted_cntr_reg[2]\ : in STD_LOGIC; + \sig_addr_posted_cntr_reg[1]\ : in STD_LOGIC; + \sig_addr_posted_cntr_reg[0]\ : in STD_LOGIC; + ram_full_i_reg : in STD_LOGIC; + sig_halt_reg_reg : in STD_LOGIC; + m_axi_mm2s_rvalid : in STD_LOGIC; + sig_dqual_reg_full : in STD_LOGIC; + sig_data2rsc_valid : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized2\ : entity is "srl_fifo_f"; +end \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized2\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized2\ is +begin +I_SRL_FIFO_RBU_F: entity work.\Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized2\ + port map ( + D(7 downto 0) => D(7 downto 0), + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\, + E(0) => E(0), + FIFO_Full_reg_0 => FIFO_Full_reg, + Q(7 downto 0) => Q(7 downto 0), + SR(0) => SR(0), + \in\(8 downto 0) => \in\(8 downto 0), + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axi_mm2s_rlast => m_axi_mm2s_rlast, + m_axi_mm2s_rvalid => m_axi_mm2s_rvalid, + \out\(3 downto 0) => \out\(3 downto 0), + ram_full_i_reg => ram_full_i_reg, + sel => sig_next_calc_error_reg_reg, + \sig_addr_posted_cntr_reg[0]\ => \sig_addr_posted_cntr_reg[0]\, + \sig_addr_posted_cntr_reg[1]\ => \sig_addr_posted_cntr_reg[1]\, + \sig_addr_posted_cntr_reg[2]\ => \sig_addr_posted_cntr_reg[2]\, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_data2rsc_valid => sig_data2rsc_valid, + \sig_dbeat_cntr_reg[0]\ => \sig_dbeat_cntr_reg[0]\, + \sig_dbeat_cntr_reg[3]\ => \sig_dbeat_cntr_reg[3]\, + \sig_dbeat_cntr_reg[5]\ => \sig_dbeat_cntr_reg[5]\, + sig_dqual_reg_empty => sig_dqual_reg_empty, + sig_dqual_reg_empty_reg => sig_dqual_reg_empty_reg, + sig_dqual_reg_empty_reg_0 => sig_dqual_reg_empty_reg_0, + sig_dqual_reg_full => sig_dqual_reg_full, + sig_halt_reg_reg => sig_halt_reg_reg, + sig_inhibit_rdy_n => sig_inhibit_rdy_n, + sig_inhibit_rdy_n_0 => sig_inhibit_rdy_n_0, + sig_last_dbeat => sig_last_dbeat, + sig_last_dbeat_reg => sig_last_dbeat_reg, + sig_mstr2data_cmd_valid => sig_mstr2data_cmd_valid, + sig_next_calc_error_reg_reg => sig_next_calc_error_reg_reg_0, + sig_next_cmd_cmplt_reg_reg => sig_next_cmd_cmplt_reg_reg, + sig_next_sequential_reg => sig_next_sequential_reg, + sig_rsc2stat_status_valid => sig_rsc2stat_status_valid + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized3\ is + port ( + FIFO_Full_reg : out STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[1]\ : out STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 0 to 0 ); + \in\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + lsig_cmd_loaded : in STD_LOGIC; + prmry_resetn_i_reg : in STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ : in STD_LOGIC; + DOBDO : in STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : in STD_LOGIC; + sig_inhibit_rdy_n_reg : in STD_LOGIC; + sig_mstr2sf_cmd_valid : in STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized3\ : entity is "srl_fifo_f"; +end \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized3\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized3\ is +begin +I_SRL_FIFO_RBU_F: entity work.\Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized3\ + port map ( + DOBDO(0) => DOBDO(0), + FIFO_Full_reg_0 => FIFO_Full_reg, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1\, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, + \INFERRED_GEN.cnt_i_reg[1]\ => \INFERRED_GEN.cnt_i_reg[1]\, + Q(0) => Q(0), + SR(0) => SR(0), + \in\(0) => \in\(0), + lsig_cmd_loaded => lsig_cmd_loaded, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + prmry_resetn_i_reg => prmry_resetn_i_reg, + sig_inhibit_rdy_n_reg => sig_inhibit_rdy_n_reg, + sig_mstr2sf_cmd_valid => sig_mstr2sf_cmd_valid + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized4\ is + port ( + p_9_out : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 0 to 0 ); + CO : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg\ : out STD_LOGIC; + decerr_i_reg : out STD_LOGIC; + slverr_i_reg : out STD_LOGIC; + interr_i_reg : out STD_LOGIC; + sig_dqual_reg_empty_reg : out STD_LOGIC; + \GEN_STS_GRTR_THAN_8.ovrflo_err_reg\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + s2mm_halt : in STD_LOGIC; + s2mm_soft_reset : in STD_LOGIC; + dma_err : in STD_LOGIC; + \hsize_vid_reg[15]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + \hsize_vid_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + S : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_inhibit_rdy_n : in STD_LOGIC; + sig_wsc2stat_status_valid : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + m_axis_s2mm_sts_tready : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 16 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized4\ : entity is "srl_fifo_f"; +end \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized4\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized4\ is +begin +I_SRL_FIFO_RBU_F: entity work.\Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized4\ + port map ( + CO(0) => CO(0), + \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg\ => \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg\, + \GEN_STS_GRTR_THAN_8.ovrflo_err_reg\(0) => \GEN_STS_GRTR_THAN_8.ovrflo_err_reg\(0), + Q(0) => Q(0), + S(0) => S(0), + decerr_i_reg => decerr_i_reg, + dma_err => dma_err, + \hsize_vid_reg[15]\(12 downto 0) => \hsize_vid_reg[15]\(12 downto 0), + \hsize_vid_reg[2]\(0) => \hsize_vid_reg[2]\(0), + \in\(16 downto 0) => \in\(16 downto 0), + interr_i_reg => interr_i_reg, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready, + p_9_out => p_9_out, + s2mm_halt => s2mm_halt, + s2mm_soft_reset => s2mm_soft_reset, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_dqual_reg_empty_reg => sig_dqual_reg_empty_reg, + sig_inhibit_rdy_n => sig_inhibit_rdy_n, + sig_stream_rst => sig_stream_rst, + sig_wsc2stat_status_valid => sig_wsc2stat_status_valid, + slverr_i_reg => slverr_i_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized5\ is + port ( + \GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg\ : out STD_LOGIC; + \GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg\ : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \INFERRED_GEN.cnt_i_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_s2mm_bready : out STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_posted_to_axi_reg : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); + sig_push_coelsc_reg : in STD_LOGIC; + m_axi_s2mm_bvalid : in STD_LOGIC; + sig_inhibit_rdy_n : in STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[3]\ : in STD_LOGIC; + sig_halt_reg : in STD_LOGIC; + m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized5\ : entity is "srl_fifo_f"; +end \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized5\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized5\ is +begin +I_SRL_FIFO_RBU_F: entity work.\Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized5\ + port map ( + D(2 downto 0) => D(2 downto 0), + E(0) => E(0), + \GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg\ => \GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg\, + \GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg\ => \GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg\, + \INFERRED_GEN.cnt_i_reg[2]\(0) => \INFERRED_GEN.cnt_i_reg[2]\(0), + \INFERRED_GEN.cnt_i_reg[3]\ => \INFERRED_GEN.cnt_i_reg[3]\, + Q(3 downto 0) => Q(3 downto 0), + \in\(1 downto 0) => \in\(1 downto 0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + m_axi_s2mm_bready => m_axi_s2mm_bready, + m_axi_s2mm_bresp(1 downto 0) => m_axi_s2mm_bresp(1 downto 0), + m_axi_s2mm_bvalid => m_axi_s2mm_bvalid, + \out\(0) => \out\(0), + sig_halt_reg => sig_halt_reg, + sig_inhibit_rdy_n => sig_inhibit_rdy_n, + sig_posted_to_axi_reg => sig_posted_to_axi_reg, + sig_push_coelsc_reg => sig_push_coelsc_reg, + sig_stream_rst => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized6\ is + port ( + p_0_in : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + sig_push_to_wsc_reg : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg\ : out STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[1]\ : out STD_LOGIC; + \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg_0\ : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + p_4_out : out STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_inhibit_rdy_n : in STD_LOGIC; + sig_data2wsc_valid : in STD_LOGIC; + sig_set_push2wsc : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \INFERRED_GEN.cnt_i_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_coelsc_reg_empty : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_INDET_BTT.lsig_eop_reg_reg\ : in STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized6\ : entity is "srl_fifo_f"; +end \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized6\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized6\ is +begin +I_SRL_FIFO_RBU_F: entity work.\Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized6\ + port map ( + D(2 downto 0) => D(2 downto 0), + E(0) => E(0), + \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg\ => \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg_0\, + \GEN_INDET_BTT.lsig_eop_reg_reg\(15 downto 0) => \GEN_INDET_BTT.lsig_eop_reg_reg\(15 downto 0), + \INFERRED_GEN.cnt_i_reg[1]\ => \INFERRED_GEN.cnt_i_reg[1]\, + \INFERRED_GEN.cnt_i_reg[3]\(0) => \INFERRED_GEN.cnt_i_reg[3]\(0), + Q(3 downto 0) => Q(3 downto 0), + \in\(0) => \in\(0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\(15 downto 0) => \out\(15 downto 0), + p_0_in => p_0_in, + p_4_out => p_4_out, + sel => \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg\, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_coelsc_reg_empty => sig_coelsc_reg_empty, + sig_data2wsc_valid => sig_data2wsc_valid, + sig_inhibit_rdy_n => sig_inhibit_rdy_n, + sig_push_to_wsc_reg => sig_push_to_wsc_reg, + sig_set_push2wsc => sig_set_push2wsc, + sig_stream_rst => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized7\ is + port ( + \INFERRED_GEN.cnt_i_reg[0]\ : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg\ : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 19 downto 0 ); + sig_sm_pop_cmd_fifo_ns : out STD_LOGIC; + sig_sm_ld_dre_cmd_ns : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_need_cmd_flush : in STD_LOGIC; + p_7_out : in STD_LOGIC; + sig_sm_pop_cmd_fifo : in STD_LOGIC; + p_9_out_0 : in STD_LOGIC; + sig_inhibit_rdy_n_reg : in STD_LOGIC; + lsig_cmd_fetch_pause : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + \sig_good_tlast_dbeat37_out__0\ : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 21 downto 0 ); + \FSM_sequential_sig_cmdcntl_sm_state_reg[0]\ : in STD_LOGIC; + \FSM_sequential_sig_cmdcntl_sm_state_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_cmd_empty_reg : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized7\ : entity is "srl_fifo_f"; +end \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized7\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized7\ is +begin +I_SRL_FIFO_RBU_F: entity work.\Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized7\ + port map ( + D(2 downto 0) => D(2 downto 0), + E(0) => E(0), + \FSM_sequential_sig_cmdcntl_sm_state_reg[0]\ => \FSM_sequential_sig_cmdcntl_sm_state_reg[0]\, + \FSM_sequential_sig_cmdcntl_sm_state_reg[2]\(2 downto 0) => \FSM_sequential_sig_cmdcntl_sm_state_reg[2]\(2 downto 0), + \GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg\ => \GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg\, + \INFERRED_GEN.cnt_i_reg[0]\ => \INFERRED_GEN.cnt_i_reg[0]\, + Q(0) => Q(0), + \in\(21 downto 0) => \in\(21 downto 0), + lsig_cmd_fetch_pause => lsig_cmd_fetch_pause, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\(19 downto 0) => \out\(19 downto 0), + p_7_out => p_7_out, + p_9_out_0 => p_9_out_0, + sig_cmd_empty_reg => sig_cmd_empty_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + \sig_good_tlast_dbeat37_out__0\ => \sig_good_tlast_dbeat37_out__0\, + sig_inhibit_rdy_n_reg => sig_inhibit_rdy_n_reg, + sig_need_cmd_flush => sig_need_cmd_flush, + sig_sm_ld_dre_cmd_ns => sig_sm_ld_dre_cmd_ns, + sig_sm_pop_cmd_fifo => sig_sm_pop_cmd_fifo, + sig_sm_pop_cmd_fifo_ns => sig_sm_pop_cmd_fifo_ns, + sig_stream_rst => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized8\ is + port ( + \INFERRED_GEN.cnt_i_reg[1]\ : out STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[4]\ : out STD_LOGIC; + \INCLUDE_PACKING.lsig_first_dbeat_reg\ : out STD_LOGIC; + \sig_byte_cntr_reg[0]\ : out STD_LOGIC; + sig_dre2ibtt_tlast : out STD_LOGIC; + sig_cmd_full_reg : out STD_LOGIC; + sig_cmd_empty_reg : out STD_LOGIC; + \sig_good_tlast_dbeat37_out__0\ : out STD_LOGIC; + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + Q : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_s_ready_dup4_reg : out STD_LOGIC; + \sig_byte_cntr_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\ : out STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0]\ : out STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_eop_sent : out STD_LOGIC; + \GEN_INDET_BTT.lsig_absorb2tlast_reg\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg\ : out STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + \INCLUDE_PACKING.lsig_first_dbeat_reg_0\ : in STD_LOGIC; + sig_cmd_full : in STD_LOGIC; + sig_sm_ld_dre_cmd : in STD_LOGIC; + p_7_out : in STD_LOGIC; + sig_strm_tlast : in STD_LOGIC; + sig_m_valid_out_reg : in STD_LOGIC; + lsig_absorb2tlast : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_last_reg_out_reg : in STD_LOGIC; + sig_eop_halt_xfer : in STD_LOGIC; + sig_ibtt2dre_tready : in STD_LOGIC; + \out\ : in STD_LOGIC; + sig_clr_dbc_reg : in STD_LOGIC; + sig_eop_sent_reg : in STD_LOGIC; + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + sig_inhibit_rdy_n_reg : in STD_LOGIC; + slice_insert_valid : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0\ : in STD_LOGIC; + p_0_in : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0\ : in STD_LOGIC; + lsig_cmd_fetch_pause : in STD_LOGIC; + sig_need_cmd_flush : in STD_LOGIC; + sig_sm_pop_cmd_fifo : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized8\ : entity is "srl_fifo_f"; +end \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized8\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized8\ is +begin +I_SRL_FIFO_RBU_F: entity work.\Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized8\ + port map ( + E(0) => E(0), + \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg\ => \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg\, + \GEN_INDET_BTT.lsig_absorb2tlast_reg\(0) => \GEN_INDET_BTT.lsig_absorb2tlast_reg\(0), + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1]\(1 downto 0) => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1]\(1 downto 0), + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0]\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\(1 downto 0) => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\(1 downto 0), + \INCLUDE_PACKING.lsig_first_dbeat_reg\ => \INCLUDE_PACKING.lsig_first_dbeat_reg\, + \INCLUDE_PACKING.lsig_first_dbeat_reg_0\ => \INCLUDE_PACKING.lsig_first_dbeat_reg_0\, + \INFERRED_GEN.cnt_i_reg[1]\ => \INFERRED_GEN.cnt_i_reg[1]\, + Q(0) => Q(0), + SR(0) => SR(0), + SS(0) => \INFERRED_GEN.cnt_i_reg[4]\, + \in\(1 downto 0) => \in\(1 downto 0), + lsig_absorb2tlast => lsig_absorb2tlast, + lsig_cmd_fetch_pause => lsig_cmd_fetch_pause, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\ => \out\, + p_0_in => p_0_in, + p_7_out => p_7_out, + \sig_byte_cntr_reg[0]\ => \sig_byte_cntr_reg[0]\, + \sig_byte_cntr_reg[7]\(0) => \sig_byte_cntr_reg[7]\(0), + sig_clr_dbc_reg => sig_clr_dbc_reg, + sig_cmd_empty_reg => sig_cmd_empty_reg, + sig_cmd_full => sig_cmd_full, + sig_cmd_full_reg => sig_cmd_full_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_dre2ibtt_tlast => sig_dre2ibtt_tlast, + sig_eop_halt_xfer => sig_eop_halt_xfer, + sig_eop_sent => sig_eop_sent, + sig_eop_sent_reg => sig_eop_sent_reg, + \sig_good_tlast_dbeat37_out__0\ => \sig_good_tlast_dbeat37_out__0\, + sig_ibtt2dre_tready => sig_ibtt2dre_tready, + sig_inhibit_rdy_n_reg => sig_inhibit_rdy_n_reg, + sig_last_reg_out_reg => sig_last_reg_out_reg, + sig_m_valid_out_reg => sig_m_valid_out_reg, + sig_need_cmd_flush => sig_need_cmd_flush, + sig_s_ready_dup4_reg => sig_s_ready_dup4_reg, + sig_sm_ld_dre_cmd => sig_sm_ld_dre_cmd, + sig_sm_pop_cmd_fifo => sig_sm_pop_cmd_fifo, + sig_strm_tlast => sig_strm_tlast, + slice_insert_valid => slice_insert_valid + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized9\ is + port ( + \INFERRED_GEN.cnt_i_reg[0]\ : out STD_LOGIC; + p_0_in : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 41 downto 0 ); + sig_calc_error_reg_reg : out STD_LOGIC; + \sig_clr_cmd2addr_valid3_out__0\ : out STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_halt_reg : in STD_LOGIC; + sig_addr_reg_empty_reg : in STD_LOGIC; + p_22_out : in STD_LOGIC; + sig_inhibit_rdy_n_reg : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 39 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized9\ : entity is "srl_fifo_f"; +end \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized9\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized9\ is +begin +I_SRL_FIFO_RBU_F: entity work.\Arty_Z7_20_axi_vdma_0_0_srl_fifo_rbu_f__parameterized9\ + port map ( + \INFERRED_GEN.cnt_i_reg[0]\ => \INFERRED_GEN.cnt_i_reg[0]\, + \in\(39 downto 0) => \in\(39 downto 0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\(41 downto 0) => \out\(41 downto 0), + p_0_in => p_0_in, + p_22_out => p_22_out, + sig_addr_reg_empty_reg => sig_addr_reg_empty_reg, + sig_calc_error_reg_reg => sig_calc_error_reg_reg, + \sig_clr_cmd2addr_valid3_out__0\ => \sig_clr_cmd2addr_valid3_out__0\, + sig_halt_reg => sig_halt_reg, + sig_inhibit_rdy_n_reg => sig_inhibit_rdy_n_reg, + sig_stream_rst => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_generic_cstr is + port ( + DOBDO : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : out STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[2]\ : out STD_LOGIC; + DIN : out STD_LOGIC_VECTOR ( 0 to 0 ); + dm2linebuf_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gc1.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \gcc0.gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + lsig_cmd_loaded : in STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ : in STD_LOGIC; + hold_ff_q : in STD_LOGIC; + \out\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; +end Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_generic_cstr; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_generic_cstr is +begin +\ramloop[0].ram.r\: entity work.Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_width + port map ( + DIBDI(1 downto 0) => DIBDI(1 downto 0), + DIN(0) => DIN(0), + DOBDO(0) => DOBDO(0), + E(0) => E(0), + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, + \INFERRED_GEN.cnt_i_reg[2]\ => \INFERRED_GEN.cnt_i_reg[2]\, + Q(0) => Q(0), + SR(0) => SR(0), + dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), + \gc1.count_d2_reg[7]\(7 downto 0) => \gc1.count_d2_reg[7]\(7 downto 0), + \gcc0.gc0.count_d1_reg[7]\(7 downto 0) => \gcc0.gc0.count_d1_reg[7]\(7 downto 0), + \gpregsm1.curr_fwft_state_reg[0]\ => \gpregsm1.curr_fwft_state_reg[0]\, + hold_ff_q => hold_ff_q, + lsig_cmd_loaded => lsig_cmd_loaded, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axi_mm2s_rdata(63 downto 0) => m_axi_mm2s_rdata(63 downto 0), + \out\ => \out\, + \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ => \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_generic_cstr__parameterized0\ is + port ( + sig_data_fifo_data_out : out STD_LOGIC_VECTOR ( 65 downto 0 ); + m_axi_s2mm_aclk : in STD_LOGIC; + ram_empty_fb_i_reg : in STD_LOGIC; + WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_s_ready_out_reg : in STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + \gc1.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 7 downto 0 ); + lsig_combined_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); + DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_generic_cstr__parameterized0\ : entity is "blk_mem_gen_generic_cstr"; +end \Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_generic_cstr__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_generic_cstr__parameterized0\ is +begin +\ramloop[0].ram.r\: entity work.\Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_prim_width__parameterized0\ + port map ( + DIBDI(1 downto 0) => DIBDI(1 downto 0), + Q(7 downto 0) => Q(7 downto 0), + WEBWE(0) => WEBWE(0), + \gc1.count_d2_reg[7]\(7 downto 0) => \gc1.count_d2_reg[7]\(7 downto 0), + lsig_combined_data(63 downto 0) => lsig_combined_data(63 downto 0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + ram_empty_fb_i_reg => ram_empty_fb_i_reg, + sig_data_fifo_data_out(65 downto 0) => sig_data_fifo_data_out(65 downto 0), + sig_s_ready_out_reg => sig_s_ready_out_reg, + sig_stream_rst => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_builtin_top_v6 is + port ( + sig_m_valid_out_reg : out STD_LOGIC; + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ : out STD_LOGIC; + FULL : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\ : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1\ : out STD_LOGIC; + fifo_dout : out STD_LOGIC_VECTOR ( 33 downto 0 ); + \out\ : in STD_LOGIC; + lsig_0ffset_cntr : in STD_LOGIC; + mm2s_prmry_resetn : in STD_LOGIC; + mm2s_halt : in STD_LOGIC; + p_24_out : in STD_LOGIC; + hold_ff_q_reg : in STD_LOGIC; + DIN : in STD_LOGIC_VECTOR ( 15 downto 0 ); + m_axis_mm2s_aclk : in STD_LOGIC; + RST : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + WR_EN : in STD_LOGIC; + dm2linebuf_mm2s_tdata : in STD_LOGIC_VECTOR ( 17 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_builtin_top_v6 : entity is "builtin_top_v6"; +end Arty_Z7_20_axi_vdma_0_0_builtin_top_v6; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_builtin_top_v6 is + signal \^gen_linebuf_no_sof.gen_linebuffer.gen_sof.sof_flag_reg_0\ : STD_LOGIC; + signal p_4_out : STD_LOGIC; + signal p_9_out : STD_LOGIC; + signal rd_tmp : STD_LOGIC; +begin + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\ <= \^gen_linebuf_no_sof.gen_linebuffer.gen_sof.sof_flag_reg_0\; +\gextw[1].gnll_fifo.inst_extd\: entity work.Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6 + port map ( + EMPTY => p_9_out, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ => \^gen_linebuf_no_sof.gen_linebuffer.gen_sof.sof_flag_reg_0\, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\ => p_4_out, + RD_EN => rd_tmp, + RST => RST, + WR_EN => WR_EN, + dm2linebuf_mm2s_tdata(17 downto 0) => dm2linebuf_mm2s_tdata(17 downto 0), + fifo_dout(17 downto 0) => fifo_dout(17 downto 0), + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axis_mm2s_aclk => m_axis_mm2s_aclk, + sig_m_valid_out_reg => sig_m_valid_out_reg + ); +\gextw[2].gnll_fifo.inst_extd\: entity work.Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6_40 + port map ( + DIN(15 downto 0) => DIN(15 downto 0), + EMPTY => p_4_out, + FULL => FULL, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1\, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, + RD_EN => rd_tmp, + RST => RST, + WR_EN => WR_EN, + fifo_dout(15 downto 0) => fifo_dout(33 downto 18), + hold_ff_q_reg => hold_ff_q_reg, + lsig_0ffset_cntr => lsig_0ffset_cntr, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axis_mm2s_aclk => m_axis_mm2s_aclk, + mm2s_halt => mm2s_halt, + mm2s_prmry_resetn => mm2s_prmry_resetn, + \out\ => \out\, + p_24_out => p_24_out, + sig_s_ready_out_reg => p_9_out, + sig_s_ready_out_reg_0 => \^gen_linebuf_no_sof.gen_linebuffer.gen_sof.sof_flag_reg_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_builtin_top_v6__parameterized0\ is + port ( + FULL : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 12 downto 0 ); + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]\ : out STD_LOGIC; + DOUT : out STD_LOGIC_VECTOR ( 8 downto 0 ); + EMPTY : out STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\ : out STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\ : out STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\ : out STD_LOGIC; + strm_not_finished_no_dwidth : out STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); + M_VALID : in STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\ : in STD_LOGIC; + s2mm_fsync_out_i : in STD_LOGIC; + \out\ : in STD_LOGIC; + p_3_out : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 6 downto 0 ); + \vsize_vid_reg[12]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : in STD_LOGIC; + minusOp_1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0\ : in STD_LOGIC; + s2mm_strm_wready : in STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + DIN : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\ : in STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + minusOp : in STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_s2mm_aclk : in STD_LOGIC; + RD_EN : in STD_LOGIC; + RST : in STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_builtin_top_v6__parameterized0\ : entity is "builtin_top_v6"; +end \Arty_Z7_20_axi_vdma_0_0_builtin_top_v6__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_builtin_top_v6__parameterized0\ is +begin +\gextw[1].gnll_fifo.inst_extd\: entity work.\Arty_Z7_20_axi_vdma_0_0_builtin_extdepth_v6__parameterized0\ + port map ( + D(12 downto 0) => D(12 downto 0), + DIN(8 downto 0) => DIN(8 downto 0), + DOUT(8 downto 0) => DOUT(8 downto 0), + EMPTY => EMPTY, + FULL => FULL, + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\, + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\(12 downto 0) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\(12 downto 0), + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]\ => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]\, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0\ => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0\, + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\ => \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0]\(0) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0]\(0), + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\(12 downto 0) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\(12 downto 0), + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\, + M_VALID => M_VALID, + Q(6 downto 0) => Q(6 downto 0), + RD_EN => RD_EN, + RST => RST, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + minusOp(11 downto 0) => minusOp(11 downto 0), + minusOp_1(11 downto 0) => minusOp_1(11 downto 0), + \out\ => \out\, + p_3_out => p_3_out, + s2mm_fsync_out_i => s2mm_fsync_out_i, + s2mm_strm_wready => s2mm_strm_wready, + s_axis_s2mm_aclk => s_axis_s2mm_aclk, + strm_not_finished_no_dwidth => strm_not_finished_no_dwidth, + \vsize_vid_reg[12]\(12 downto 0) => \vsize_vid_reg[12]\(12 downto 0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_rd_logic_30 is + port ( + \out\ : out STD_LOGIC; + sig_ok_to_post_rd_addr_reg : out STD_LOGIC; + hold_ff_q_reg : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC; + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0\ : out STD_LOGIC; + ram_full_i_reg : out STD_LOGIC; + \sig_user_skid_reg_reg[0]\ : out STD_LOGIC; + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_1\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_posted_to_axi_2_reg : in STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : in STD_LOGIC; + hold_ff_q : in STD_LOGIC; + ram_full_i_reg_0 : in STD_LOGIC; + ram_full_fb_i_reg : in STD_LOGIC; + ram_full_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 ); + lsig_cmd_loaded : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \sig_token_cntr_reg[0]\ : in STD_LOGIC; + \sig_token_cntr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + sig_posted_to_axi_2_reg_0 : in STD_LOGIC; + \gcc0.gc0.count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + ram_full_i_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_rd_logic_30 : entity is "rd_logic"; +end Arty_Z7_20_axi_vdma_0_0_rd_logic_30; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_rd_logic_30 is + signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal p_2_out_0 : STD_LOGIC; + signal rpntr_n_1 : STD_LOGIC; +begin + E(0) <= \^e\(0); +\gr1.gr1_int.rfwft\: entity work.Arty_Z7_20_axi_vdma_0_0_rd_fwft_34 + port map ( + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0\, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, + SR(0) => SR(0), + \gc1.count_reg[7]\ => \^e\(0), + hold_ff_q => hold_ff_q, + hold_ff_q_reg => hold_ff_q_reg, + lsig_cmd_loaded => lsig_cmd_loaded, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + \out\ => \out\, + ram_empty_fb_i_reg => p_2_out_0, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + \sig_user_skid_reg_reg[0]\ => \sig_user_skid_reg_reg[0]\ + ); +\grss.gdc.dc\: entity work.Arty_Z7_20_axi_vdma_0_0_dc_ss + port map ( + SR(0) => SR(0), + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + ram_empty_fb_i_reg => \^e\(0), + ram_full_i_reg(0) => ram_full_i_reg_2(0), + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_ok_to_post_rd_addr_reg => sig_ok_to_post_rd_addr_reg, + sig_posted_to_axi_2_reg => sig_posted_to_axi_2_reg, + sig_posted_to_axi_2_reg_0 => sig_posted_to_axi_2_reg_0, + \sig_token_cntr_reg[0]\ => \sig_token_cntr_reg[0]\, + \sig_token_cntr_reg[3]\(3 downto 0) => \sig_token_cntr_reg[3]\(3 downto 0) + ); +\grss.rsts\: entity work.Arty_Z7_20_axi_vdma_0_0_rd_status_flags_ss_35 + port map ( + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + \out\ => p_2_out_0, + ram_empty_fb_i_reg_0 => rpntr_n_1 + ); +rpntr: entity work.Arty_Z7_20_axi_vdma_0_0_rd_bin_cntr_36 + port map ( + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(7 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_1\(7 downto 0), + Q(7 downto 0) => Q(7 downto 0), + SR(0) => SR(0), + \gcc0.gc0.count_reg[7]\(7 downto 0) => \gcc0.gc0.count_reg[7]\(7 downto 0), + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + \out\ => p_2_out_0, + ram_empty_fb_i_reg => rpntr_n_1, + ram_empty_fb_i_reg_0 => \^e\(0), + ram_full_fb_i_reg => ram_full_fb_i_reg, + ram_full_i_reg => ram_full_i_reg, + ram_full_i_reg_0 => ram_full_i_reg_0, + ram_full_i_reg_1(0) => ram_full_i_reg_1(0), + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_rd_logic__parameterized0\ is + port ( + \out\ : out STD_LOGIC; + hold_ff_q_reg : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \gc1.count_reg[2]\ : out STD_LOGIC; + sig_sf2pcc_xfer_valid : out STD_LOGIC; + sig_ibtt2dre_tready : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + \ram_empty_i0__3\ : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + p_32_out : in STD_LOGIC; + hold_ff_q : in STD_LOGIC; + lsig_packer_full : in STD_LOGIC; + ram_full_i_reg : in STD_LOGIC; + ram_full_i_reg_0 : in STD_LOGIC; + ram_full_fb_i_reg : in STD_LOGIC; + sig_clr_dbc_reg_reg : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_rd_logic__parameterized0\ : entity is "rd_logic"; +end \Arty_Z7_20_axi_vdma_0_0_rd_logic__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_rd_logic__parameterized0\ is + signal \^gc1.count_reg[2]\ : STD_LOGIC; + signal \grhf.rhf_n_0\ : STD_LOGIC; + signal p_3_out : STD_LOGIC; +begin + \gc1.count_reg[2]\ <= \^gc1.count_reg[2]\; +\grhf.rhf\: entity work.\Arty_Z7_20_axi_vdma_0_0_rd_handshaking_flags__parameterized0\ + port map ( + \gv.ram_valid_d1_reg_0\ => \grhf.rhf_n_0\, + hold_ff_q => hold_ff_q, + hold_ff_q_reg => hold_ff_q_reg, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\ => p_3_out, + p_32_out => p_32_out, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid, + sig_stream_rst => sig_stream_rst + ); +\grss.gdc.dc\: entity work.\Arty_Z7_20_axi_vdma_0_0_dc_ss__parameterized0\ + port map ( + E(0) => \^gc1.count_reg[2]\, + lsig_packer_full => lsig_packer_full, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + ram_full_fb_i_reg => ram_full_fb_i_reg, + ram_full_i_reg => ram_full_i_reg, + ram_full_i_reg_0 => ram_full_i_reg_0, + sig_clr_dbc_reg_reg => sig_clr_dbc_reg_reg, + sig_ibtt2dre_tready => sig_ibtt2dre_tready, + sig_stream_rst => sig_stream_rst + ); +\grss.rsts\: entity work.\Arty_Z7_20_axi_vdma_0_0_rd_status_flags_ss__parameterized0\ + port map ( + E(0) => E(0), + \gc1.count_reg[2]\(0) => \^gc1.count_reg[2]\, + \gpr1.dout_i_reg[10]\ => p_3_out, + \gv.ram_valid_d1_reg\ => \grhf.rhf_n_0\, + hold_ff_q => hold_ff_q, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\ => \out\, + p_32_out => p_32_out, + \ram_empty_i0__3\ => \ram_empty_i0__3\, + sig_stream_rst => sig_stream_rst + ); +rpntr: entity work.\Arty_Z7_20_axi_vdma_0_0_rd_bin_cntr__parameterized0\ + port map ( + E(0) => \^gc1.count_reg[2]\, + Q(2 downto 0) => Q(2 downto 0), + \gpr1.dout_i_reg[1]\(2 downto 0) => \gpr1.dout_i_reg[1]\(2 downto 0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + sig_stream_rst => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo is + port ( + sig_init_done : out STD_LOGIC; + sig_calc_error_reg_reg : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axis_cmd_tvalid_reg : out STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : out STD_LOGIC_VECTOR ( 49 downto 0 ); + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_init_reg_reg : in STD_LOGIC; + sig_psm_halt : in STD_LOGIC; + sig_input_reg_empty : in STD_LOGIC; + p_10_out : in STD_LOGIC; + cmnd_wr_1 : in STD_LOGIC; + s2mm_halt : in STD_LOGIC; + s_axis_s2mm_cmd_tvalid : in STD_LOGIC; + \s_axis_cmd_tdata_reg[63]\ : in STD_LOGIC_VECTOR ( 48 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo : entity is "axi_datamover_fifo"; +end Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo is + signal sig_inhibit_rdy_n : STD_LOGIC; + signal sig_inhibit_rdy_n_i_1_n_0 : STD_LOGIC; + signal \^sig_init_done\ : STD_LOGIC; +begin + sig_init_done <= \^sig_init_done\; +\USE_SRL_FIFO.I_SYNC_FIFO\: entity work.Arty_Z7_20_axi_vdma_0_0_srl_fifo_f + port map ( + Q(0) => Q(0), + cmnd_wr_1 => cmnd_wr_1, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\(49 downto 0) => \out\(49 downto 0), + p_10_out => p_10_out, + s2mm_halt => s2mm_halt, + \s_axis_cmd_tdata_reg[63]\(48 downto 0) => \s_axis_cmd_tdata_reg[63]\(48 downto 0), + s_axis_cmd_tvalid_reg(0) => s_axis_cmd_tvalid_reg(0), + s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid, + sig_calc_error_reg_reg => sig_calc_error_reg_reg, + sig_inhibit_rdy_n => sig_inhibit_rdy_n, + sig_input_reg_empty => sig_input_reg_empty, + sig_psm_halt => sig_psm_halt, + sig_stream_rst => sig_stream_rst + ); +sig_inhibit_rdy_n_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^sig_init_done\, + I1 => sig_inhibit_rdy_n, + O => sig_inhibit_rdy_n_i_1_n_0 + ); +sig_inhibit_rdy_n_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_inhibit_rdy_n_i_1_n_0, + Q => sig_inhibit_rdy_n, + R => sig_stream_rst + ); +sig_init_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_init_reg_reg, + Q => \^sig_init_done\, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo_22 is + port ( + sig_calc_error_reg_reg : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 0 to 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : out STD_LOGIC_VECTOR ( 49 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_sm_halt_reg : in STD_LOGIC; + sig_input_reg_empty : in STD_LOGIC; + cmnd_wr : in STD_LOGIC; + mm2s_halt : in STD_LOGIC; + sig_calc_error_pushed_reg : in STD_LOGIC; + sig_calc_error_pushed : in STD_LOGIC; + p_56_out : in STD_LOGIC; + \s_axis_cmd_tdata_reg[63]\ : in STD_LOGIC_VECTOR ( 48 downto 0 ); + sig_init_reg2 : in STD_LOGIC; + sig_init_reg : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo_22 : entity is "axi_datamover_fifo"; +end Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo_22; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo_22 is + signal sig_inhibit_rdy_n : STD_LOGIC; + signal sig_inhibit_rdy_n_i_1_n_0 : STD_LOGIC; + signal sig_init_done : STD_LOGIC; + signal sig_init_done_i_1_n_0 : STD_LOGIC; +begin +\USE_SRL_FIFO.I_SYNC_FIFO\: entity work.Arty_Z7_20_axi_vdma_0_0_srl_fifo_f_23 + port map ( + E(0) => E(0), + Q(0) => Q(0), + SR(0) => SR(0), + cmnd_wr => cmnd_wr, + \in\(0) => \in\(0), + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + mm2s_halt => mm2s_halt, + \out\(49 downto 0) => \out\(49 downto 0), + p_56_out => p_56_out, + \s_axis_cmd_tdata_reg[63]\(48 downto 0) => \s_axis_cmd_tdata_reg[63]\(48 downto 0), + sig_calc_error_pushed => sig_calc_error_pushed, + sig_calc_error_pushed_reg => sig_calc_error_pushed_reg, + sig_calc_error_reg_reg => sig_calc_error_reg_reg, + sig_inhibit_rdy_n => sig_inhibit_rdy_n, + sig_input_reg_empty => sig_input_reg_empty, + sig_sm_halt_reg => sig_sm_halt_reg + ); +sig_inhibit_rdy_n_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => sig_init_done, + I1 => sig_inhibit_rdy_n, + O => sig_inhibit_rdy_n_i_1_n_0 + ); +sig_inhibit_rdy_n_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => sig_inhibit_rdy_n_i_1_n_0, + Q => sig_inhibit_rdy_n, + R => SR(0) + ); +sig_init_done_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"0080" + ) + port map ( + I0 => sig_init_reg2, + I1 => sig_init_reg, + I2 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I3 => sig_init_done, + O => sig_init_done_i_1_n_0 + ); +sig_init_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => sig_init_done_i_1_n_0, + Q => sig_init_done, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized0\ is + port ( + \INFERRED_GEN.cnt_i_reg[1]\ : out STD_LOGIC; + sig_rd_sts_slverr_reg_reg : out STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[1]_0\ : out STD_LOGIC; + decerr_i_reg : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 0 to 0 ); + slverr_i_reg : out STD_LOGIC; + interr_i_reg : out STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + sig_rsc2stat_status_valid : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + p_58_out : in STD_LOGIC; + sts_tready_reg : in STD_LOGIC; + sig_rd_sts_slverr_reg_reg_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_init_reg2 : in STD_LOGIC; + sig_init_reg : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized0\ : entity is "axi_datamover_fifo"; +end \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized0\ is + signal \^inferred_gen.cnt_i_reg[1]_0\ : STD_LOGIC; + signal sig_inhibit_rdy_n_i_1_n_0 : STD_LOGIC; + signal sig_init_done : STD_LOGIC; + signal sig_init_done_i_1_n_0 : STD_LOGIC; +begin + \INFERRED_GEN.cnt_i_reg[1]_0\ <= \^inferred_gen.cnt_i_reg[1]_0\; +\USE_SRL_FIFO.I_SYNC_FIFO\: entity work.\Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized0\ + port map ( + \INFERRED_GEN.cnt_i_reg[1]\ => \INFERRED_GEN.cnt_i_reg[1]\, + Q(0) => Q(0), + SR(0) => SR(0), + decerr_i_reg => decerr_i_reg, + interr_i_reg => interr_i_reg, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + p_58_out => p_58_out, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_inhibit_rdy_n_reg => \^inferred_gen.cnt_i_reg[1]_0\, + sig_rd_sts_slverr_reg_reg => sig_rd_sts_slverr_reg_reg, + sig_rd_sts_slverr_reg_reg_0(2 downto 0) => sig_rd_sts_slverr_reg_reg_0(2 downto 0), + sig_rsc2stat_status_valid => sig_rsc2stat_status_valid, + slverr_i_reg => slverr_i_reg, + sts_tready_reg => sts_tready_reg + ); +sig_inhibit_rdy_n_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => sig_init_done, + I1 => \^inferred_gen.cnt_i_reg[1]_0\, + O => sig_inhibit_rdy_n_i_1_n_0 + ); +sig_inhibit_rdy_n_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => sig_inhibit_rdy_n_i_1_n_0, + Q => \^inferred_gen.cnt_i_reg[1]_0\, + R => SR(0) + ); +sig_init_done_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"0080" + ) + port map ( + I0 => sig_init_reg2, + I1 => sig_init_reg, + I2 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I3 => sig_init_done, + O => sig_init_done_i_1_n_0 + ); +sig_init_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => sig_init_done_i_1_n_0, + Q => sig_init_done, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized1\ is + port ( + sig_init_reg2 : out STD_LOGIC; + sig_addr_valid_reg_reg : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 40 downto 0 ); + sig_posted_to_axi_2_reg : out STD_LOGIC; + sel : out STD_LOGIC; + sig_push_addr_reg1_out : out STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_init_reg : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + sig_addr_reg_empty : in STD_LOGIC; + sig_sf_allow_addr_req : in STD_LOGIC; + sig_data2addr_stop_req : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_mstr2addr_cmd_valid : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 38 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized1\ : entity is "axi_datamover_fifo"; +end \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized1\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized1\ is + signal sig_inhibit_rdy_n : STD_LOGIC; + signal sig_inhibit_rdy_n_i_1_n_0 : STD_LOGIC; + signal sig_init_done : STD_LOGIC; + signal sig_init_done_i_1_n_0 : STD_LOGIC; + signal \^sig_init_reg2\ : STD_LOGIC; +begin + sig_init_reg2 <= \^sig_init_reg2\; +\USE_SRL_FIFO.I_SYNC_FIFO\: entity work.\Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized1\ + port map ( + SR(0) => SR(0), + \in\(38 downto 0) => \in\(38 downto 0), + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + \out\(40 downto 0) => \out\(40 downto 0), + sig_addr_reg_empty => sig_addr_reg_empty, + sig_addr_reg_empty_reg => sig_push_addr_reg1_out, + sig_addr_valid_reg_reg => sig_addr_valid_reg_reg, + sig_calc_error_reg_reg => sel, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_data2addr_stop_req => sig_data2addr_stop_req, + sig_inhibit_rdy_n => sig_inhibit_rdy_n, + sig_mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid, + sig_posted_to_axi_2_reg => sig_posted_to_axi_2_reg, + sig_sf_allow_addr_req => sig_sf_allow_addr_req + ); +sig_inhibit_rdy_n_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => sig_init_done, + I1 => sig_inhibit_rdy_n, + O => sig_inhibit_rdy_n_i_1_n_0 + ); +sig_inhibit_rdy_n_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => sig_inhibit_rdy_n_i_1_n_0, + Q => sig_inhibit_rdy_n, + R => SR(0) + ); +sig_init_done_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"0080" + ) + port map ( + I0 => \^sig_init_reg2\, + I1 => sig_init_reg, + I2 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I3 => sig_init_done, + O => sig_init_done_i_1_n_0 + ); +sig_init_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => sig_init_done_i_1_n_0, + Q => sig_init_done, + R => '0' + ); +sig_init_reg2_reg: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => sig_init_reg, + Q => \^sig_init_reg2\, + S => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized10\ is + port ( + \INFERRED_GEN.cnt_i_reg[0]\ : out STD_LOGIC; + sig_init_done : out STD_LOGIC; + sig_last_dbeat_reg : out STD_LOGIC; + sig_push_dqual_reg : out STD_LOGIC; + sig_ld_new_cmd_reg_reg : out STD_LOGIC; + sig_next_calc_error_reg_reg : out STD_LOGIC; + \sig_good_mmap_dbeat12_out__0\ : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 7 downto 0 ); + \INFERRED_GEN.cnt_i_reg[0]_0\ : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_dqual_reg_empty_reg : out STD_LOGIC; + \sig_clr_cmd2data_valid4_out__0\ : out STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_init_reg_reg : in STD_LOGIC; + \sig_first_dbeat1__0\ : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_single_dbeat : in STD_LOGIC; + sig_last_dbeat_reg_0 : in STD_LOGIC; + sig_ld_new_cmd_reg : in STD_LOGIC; + sig_next_calc_error_reg : in STD_LOGIC; + \sig_dbeat_cntr_reg[1]\ : in STD_LOGIC; + sig_dqual_reg_full_reg : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \sig_dbeat_cntr_reg[4]\ : in STD_LOGIC; + p_11_out : in STD_LOGIC; + \sig_dbeat_cntr_reg[2]\ : in STD_LOGIC; + \sig_dbeat_cntr_reg[3]\ : in STD_LOGIC; + sig_next_sequential_reg : in STD_LOGIC; + sig_dqual_reg_empty : in STD_LOGIC; + sig_halt_reg : in STD_LOGIC; + sig_m_valid_out_reg : in STD_LOGIC; + sig_s_ready_out_reg : in STD_LOGIC; + sig_wdc_status_going_full : in STD_LOGIC; + sig_inhibit_rdy_n_reg_0 : in STD_LOGIC; + sig_wsc2stat_status_valid : in STD_LOGIC; + sig_addr_posted_cntr : in STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_halt_reg_dly3 : in STD_LOGIC; + sig_last_mmap_dbeat_reg : in STD_LOGIC; + sig_posted_to_axi_reg : in STD_LOGIC; + sig_xfer_calc_err_reg_reg : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized10\ : entity is "axi_datamover_fifo"; +end \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized10\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized10\ is + signal \^inferred_gen.cnt_i_reg[0]_0\ : STD_LOGIC; + signal sig_inhibit_rdy_n_i_1_n_0 : STD_LOGIC; + signal \^sig_init_done\ : STD_LOGIC; +begin + \INFERRED_GEN.cnt_i_reg[0]_0\ <= \^inferred_gen.cnt_i_reg[0]_0\; + sig_init_done <= \^sig_init_done\; +\USE_SRL_FIFO.I_SYNC_FIFO\: entity work.\Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized10\ + port map ( + D(7 downto 0) => D(7 downto 0), + E(0) => E(0), + \INFERRED_GEN.cnt_i_reg[0]\ => \INFERRED_GEN.cnt_i_reg[0]\, + Q(7 downto 0) => Q(7 downto 0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\(2 downto 0) => \out\(2 downto 0), + p_11_out => p_11_out, + sig_addr_posted_cntr(2 downto 0) => sig_addr_posted_cntr(2 downto 0), + \sig_clr_cmd2data_valid4_out__0\ => \sig_clr_cmd2data_valid4_out__0\, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + \sig_dbeat_cntr_reg[1]\ => \sig_dbeat_cntr_reg[1]\, + \sig_dbeat_cntr_reg[2]\ => \sig_dbeat_cntr_reg[2]\, + \sig_dbeat_cntr_reg[3]\ => \sig_dbeat_cntr_reg[3]\, + \sig_dbeat_cntr_reg[4]\ => \sig_dbeat_cntr_reg[4]\, + sig_dqual_reg_empty => sig_dqual_reg_empty, + sig_dqual_reg_empty_reg => sig_push_dqual_reg, + sig_dqual_reg_empty_reg_0 => \sig_good_mmap_dbeat12_out__0\, + sig_dqual_reg_empty_reg_1 => sig_dqual_reg_empty_reg, + sig_dqual_reg_full_reg => sig_dqual_reg_full_reg, + \sig_first_dbeat1__0\ => \sig_first_dbeat1__0\, + sig_halt_reg => sig_halt_reg, + sig_halt_reg_dly3 => sig_halt_reg_dly3, + sig_inhibit_rdy_n_reg => \^inferred_gen.cnt_i_reg[0]_0\, + sig_inhibit_rdy_n_reg_0 => sig_inhibit_rdy_n_reg_0, + sig_last_dbeat_reg => sig_last_dbeat_reg, + sig_last_dbeat_reg_0 => sig_last_dbeat_reg_0, + sig_last_mmap_dbeat_reg => sig_last_mmap_dbeat_reg, + sig_ld_new_cmd_reg => sig_ld_new_cmd_reg, + sig_ld_new_cmd_reg_reg => sig_ld_new_cmd_reg_reg, + sig_m_valid_out_reg => sig_m_valid_out_reg, + sig_next_calc_error_reg => sig_next_calc_error_reg, + sig_next_calc_error_reg_reg => sig_next_calc_error_reg_reg, + sig_next_sequential_reg => sig_next_sequential_reg, + sig_posted_to_axi_reg => sig_posted_to_axi_reg, + sig_s_ready_out_reg => sig_s_ready_out_reg, + sig_single_dbeat => sig_single_dbeat, + sig_stream_rst => sig_stream_rst, + sig_wdc_status_going_full => sig_wdc_status_going_full, + sig_wsc2stat_status_valid => sig_wsc2stat_status_valid, + sig_xfer_calc_err_reg_reg(8 downto 0) => sig_xfer_calc_err_reg_reg(8 downto 0) + ); +sig_inhibit_rdy_n_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^sig_init_done\, + I1 => \^inferred_gen.cnt_i_reg[0]_0\, + O => sig_inhibit_rdy_n_i_1_n_0 + ); +sig_inhibit_rdy_n_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_inhibit_rdy_n_i_1_n_0, + Q => \^inferred_gen.cnt_i_reg[0]_0\, + R => sig_stream_rst + ); +sig_init_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_init_reg_reg, + Q => \^sig_init_done\, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized2\ is + port ( + D : out STD_LOGIC_VECTOR ( 7 downto 0 ); + sig_push_dqual_reg : out STD_LOGIC; + sig_next_cmd_cmplt_reg_reg : out STD_LOGIC; + sig_dqual_reg_empty_reg : out STD_LOGIC; + sel : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + sig_last_dbeat_reg : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \sig_dbeat_cntr_reg[0]\ : in STD_LOGIC; + m_axi_mm2s_rlast : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_mstr2data_cmd_valid : in STD_LOGIC; + \sig_dbeat_cntr_reg[3]\ : in STD_LOGIC; + \sig_dbeat_cntr_reg[5]\ : in STD_LOGIC; + sig_next_sequential_reg : in STD_LOGIC; + sig_last_dbeat : in STD_LOGIC; + sig_dqual_reg_empty : in STD_LOGIC; + sig_rsc2stat_status_valid : in STD_LOGIC; + FIFO_Full_reg : in STD_LOGIC; + sig_inhibit_rdy_n : in STD_LOGIC; + sig_next_calc_error_reg_reg : in STD_LOGIC; + \sig_addr_posted_cntr_reg[2]\ : in STD_LOGIC; + \sig_addr_posted_cntr_reg[1]\ : in STD_LOGIC; + \sig_addr_posted_cntr_reg[0]\ : in STD_LOGIC; + ram_full_i_reg : in STD_LOGIC; + sig_halt_reg_reg : in STD_LOGIC; + m_axi_mm2s_rvalid : in STD_LOGIC; + sig_dqual_reg_full : in STD_LOGIC; + sig_data2rsc_valid : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + sig_init_reg2 : in STD_LOGIC; + sig_init_reg : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized2\ : entity is "axi_datamover_fifo"; +end \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized2\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized2\ is + signal sig_inhibit_rdy_n_0 : STD_LOGIC; + signal sig_inhibit_rdy_n_i_1_n_0 : STD_LOGIC; + signal sig_init_done : STD_LOGIC; + signal sig_init_done_i_1_n_0 : STD_LOGIC; +begin +\USE_SRL_FIFO.I_SYNC_FIFO\: entity work.\Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized2\ + port map ( + D(7 downto 0) => D(7 downto 0), + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\, + E(0) => E(0), + FIFO_Full_reg => FIFO_Full_reg, + Q(7 downto 0) => Q(7 downto 0), + SR(0) => SR(0), + \in\(8 downto 0) => \in\(8 downto 0), + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axi_mm2s_rlast => m_axi_mm2s_rlast, + m_axi_mm2s_rvalid => m_axi_mm2s_rvalid, + \out\(3 downto 0) => \out\(3 downto 0), + ram_full_i_reg => ram_full_i_reg, + \sig_addr_posted_cntr_reg[0]\ => \sig_addr_posted_cntr_reg[0]\, + \sig_addr_posted_cntr_reg[1]\ => \sig_addr_posted_cntr_reg[1]\, + \sig_addr_posted_cntr_reg[2]\ => \sig_addr_posted_cntr_reg[2]\, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_data2rsc_valid => sig_data2rsc_valid, + \sig_dbeat_cntr_reg[0]\ => \sig_dbeat_cntr_reg[0]\, + \sig_dbeat_cntr_reg[3]\ => \sig_dbeat_cntr_reg[3]\, + \sig_dbeat_cntr_reg[5]\ => \sig_dbeat_cntr_reg[5]\, + sig_dqual_reg_empty => sig_dqual_reg_empty, + sig_dqual_reg_empty_reg => sig_push_dqual_reg, + sig_dqual_reg_empty_reg_0 => sig_dqual_reg_empty_reg, + sig_dqual_reg_full => sig_dqual_reg_full, + sig_halt_reg_reg => sig_halt_reg_reg, + sig_inhibit_rdy_n => sig_inhibit_rdy_n, + sig_inhibit_rdy_n_0 => sig_inhibit_rdy_n_0, + sig_last_dbeat => sig_last_dbeat, + sig_last_dbeat_reg => sig_last_dbeat_reg, + sig_mstr2data_cmd_valid => sig_mstr2data_cmd_valid, + sig_next_calc_error_reg_reg => sel, + sig_next_calc_error_reg_reg_0 => sig_next_calc_error_reg_reg, + sig_next_cmd_cmplt_reg_reg => sig_next_cmd_cmplt_reg_reg, + sig_next_sequential_reg => sig_next_sequential_reg, + sig_rsc2stat_status_valid => sig_rsc2stat_status_valid + ); +sig_inhibit_rdy_n_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => sig_init_done, + I1 => sig_inhibit_rdy_n_0, + O => sig_inhibit_rdy_n_i_1_n_0 + ); +sig_inhibit_rdy_n_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => sig_inhibit_rdy_n_i_1_n_0, + Q => sig_inhibit_rdy_n_0, + R => SR(0) + ); +sig_init_done_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"0080" + ) + port map ( + I0 => sig_init_reg2, + I1 => sig_init_reg, + I2 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I3 => sig_init_done, + O => sig_init_done_i_1_n_0 + ); +sig_init_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => sig_init_done_i_1_n_0, + Q => sig_init_done, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized3\ is + port ( + FIFO_Full_reg : out STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[1]\ : out STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INFERRED_GEN.cnt_i_reg[1]_0\ : out STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + lsig_cmd_loaded : in STD_LOGIC; + prmry_resetn_i_reg : in STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ : in STD_LOGIC; + DOBDO : in STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : in STD_LOGIC; + sig_mstr2sf_cmd_valid : in STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1\ : in STD_LOGIC; + sig_init_reg2 : in STD_LOGIC; + sig_init_reg : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized3\ : entity is "axi_datamover_fifo"; +end \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized3\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized3\ is + signal \^inferred_gen.cnt_i_reg[1]_0\ : STD_LOGIC; + signal sig_inhibit_rdy_n_i_1_n_0 : STD_LOGIC; + signal sig_init_done : STD_LOGIC; + signal sig_init_done_i_1_n_0 : STD_LOGIC; +begin + \INFERRED_GEN.cnt_i_reg[1]_0\ <= \^inferred_gen.cnt_i_reg[1]_0\; +\USE_SRL_FIFO.I_SYNC_FIFO\: entity work.\Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized3\ + port map ( + DOBDO(0) => DOBDO(0), + FIFO_Full_reg => FIFO_Full_reg, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1\, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, + \INFERRED_GEN.cnt_i_reg[1]\ => \INFERRED_GEN.cnt_i_reg[1]\, + Q(0) => Q(0), + SR(0) => SR(0), + \in\(0) => \in\(0), + lsig_cmd_loaded => lsig_cmd_loaded, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + prmry_resetn_i_reg => prmry_resetn_i_reg, + sig_inhibit_rdy_n_reg => \^inferred_gen.cnt_i_reg[1]_0\, + sig_mstr2sf_cmd_valid => sig_mstr2sf_cmd_valid + ); +sig_inhibit_rdy_n_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => sig_init_done, + I1 => \^inferred_gen.cnt_i_reg[1]_0\, + O => sig_inhibit_rdy_n_i_1_n_0 + ); +sig_inhibit_rdy_n_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => sig_inhibit_rdy_n_i_1_n_0, + Q => \^inferred_gen.cnt_i_reg[1]_0\, + R => SR(0) + ); +sig_init_done_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"0080" + ) + port map ( + I0 => sig_init_reg2, + I1 => sig_init_reg, + I2 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I3 => sig_init_done, + O => sig_init_done_i_1_n_0 + ); +sig_init_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => sig_init_done_i_1_n_0, + Q => sig_init_done, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized4\ is + port ( + sig_init_done_0 : out STD_LOGIC; + p_9_out : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 0 to 0 ); + CO : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg\ : out STD_LOGIC; + decerr_i_reg : out STD_LOGIC; + slverr_i_reg : out STD_LOGIC; + interr_i_reg : out STD_LOGIC; + sig_dqual_reg_empty_reg : out STD_LOGIC; + \GEN_STS_GRTR_THAN_8.ovrflo_err_reg\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_init_reg_reg : in STD_LOGIC; + s2mm_halt : in STD_LOGIC; + s2mm_soft_reset : in STD_LOGIC; + dma_err : in STD_LOGIC; + \hsize_vid_reg[15]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + \hsize_vid_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + S : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_wsc2stat_status_valid : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + m_axis_s2mm_sts_tready : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 16 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized4\ : entity is "axi_datamover_fifo"; +end \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized4\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized4\ is + signal sig_inhibit_rdy_n : STD_LOGIC; + signal sig_inhibit_rdy_n_i_1_n_0 : STD_LOGIC; + signal \^sig_init_done_0\ : STD_LOGIC; +begin + sig_init_done_0 <= \^sig_init_done_0\; +\USE_SRL_FIFO.I_SYNC_FIFO\: entity work.\Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized4\ + port map ( + CO(0) => CO(0), + \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg\ => \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg\, + \GEN_STS_GRTR_THAN_8.ovrflo_err_reg\(0) => \GEN_STS_GRTR_THAN_8.ovrflo_err_reg\(0), + Q(0) => Q(0), + S(0) => S(0), + decerr_i_reg => decerr_i_reg, + dma_err => dma_err, + \hsize_vid_reg[15]\(12 downto 0) => \hsize_vid_reg[15]\(12 downto 0), + \hsize_vid_reg[2]\(0) => \hsize_vid_reg[2]\(0), + \in\(16 downto 0) => \in\(16 downto 0), + interr_i_reg => interr_i_reg, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready, + p_9_out => p_9_out, + s2mm_halt => s2mm_halt, + s2mm_soft_reset => s2mm_soft_reset, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_dqual_reg_empty_reg => sig_dqual_reg_empty_reg, + sig_inhibit_rdy_n => sig_inhibit_rdy_n, + sig_stream_rst => sig_stream_rst, + sig_wsc2stat_status_valid => sig_wsc2stat_status_valid, + slverr_i_reg => slverr_i_reg + ); +sig_inhibit_rdy_n_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^sig_init_done_0\, + I1 => sig_inhibit_rdy_n, + O => sig_inhibit_rdy_n_i_1_n_0 + ); +sig_inhibit_rdy_n_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_inhibit_rdy_n_i_1_n_0, + Q => sig_inhibit_rdy_n, + R => sig_stream_rst + ); +sig_init_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_init_reg_reg, + Q => \^sig_init_done_0\, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized5\ is + port ( + sig_init_reg2_reg : out STD_LOGIC; + \GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg\ : out STD_LOGIC; + \GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg\ : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \INFERRED_GEN.cnt_i_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_s2mm_bready : out STD_LOGIC; + sig_input_cache_type_reg0 : out STD_LOGIC; + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_init_done_reg_0 : out STD_LOGIC; + sig_init_done_reg_1 : out STD_LOGIC; + sig_init_done_reg_2 : out STD_LOGIC; + sig_init_done_reg_3 : out STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_posted_to_axi_reg : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); + sig_push_coelsc_reg : in STD_LOGIC; + m_axi_s2mm_bvalid : in STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[3]\ : in STD_LOGIC; + sig_halt_reg : in STD_LOGIC; + sig_psm_pop_input_cmd : in STD_LOGIC; + sig_csm_pop_child_cmd : in STD_LOGIC; + sig_init_reg2 : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_init_done : in STD_LOGIC; + sig_init_done_0 : in STD_LOGIC; + sig_init_done_1 : in STD_LOGIC; + sig_init_done_2 : in STD_LOGIC; + m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized5\ : entity is "axi_datamover_fifo"; +end \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized5\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized5\ is + signal sig_inhibit_rdy_n : STD_LOGIC; + signal sig_inhibit_rdy_n_i_1_n_0 : STD_LOGIC; + signal sig_init_done_3 : STD_LOGIC; + signal sig_init_done_i_1_n_0 : STD_LOGIC; + signal \^sig_init_reg2_reg\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/sig_init_done_i_1\ : label is "soft_lutpair252"; + attribute SOFT_HLUTNM of \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_init_done_i_1\ : label is "soft_lutpair253"; + attribute SOFT_HLUTNM of \GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_init_done_i_1\ : label is "soft_lutpair252"; + attribute SOFT_HLUTNM of \I_CMD_FIFO/sig_init_done_i_1\ : label is "soft_lutpair253"; + attribute SOFT_HLUTNM of sig_init_done_i_1 : label is "soft_lutpair254"; + attribute SOFT_HLUTNM of \sig_input_addr_reg[31]_i_1\ : label is "soft_lutpair254"; +begin + sig_init_reg2_reg <= \^sig_init_reg2_reg\; +\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/sig_init_done_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0080" + ) + port map ( + I0 => \^sig_init_reg2_reg\, + I1 => sig_init_reg2, + I2 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I3 => sig_init_done, + O => sig_init_done_reg_0 + ); +\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_init_done_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0080" + ) + port map ( + I0 => \^sig_init_reg2_reg\, + I1 => sig_init_reg2, + I2 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I3 => sig_init_done_0, + O => sig_init_done_reg_1 + ); +\GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_init_done_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0080" + ) + port map ( + I0 => \^sig_init_reg2_reg\, + I1 => sig_init_reg2, + I2 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I3 => sig_init_done_1, + O => sig_init_done_reg_2 + ); +\I_CMD_FIFO/sig_init_done_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0080" + ) + port map ( + I0 => \^sig_init_reg2_reg\, + I1 => sig_init_reg2, + I2 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I3 => sig_init_done_2, + O => sig_init_done_reg_3 + ); +\USE_SRL_FIFO.I_SYNC_FIFO\: entity work.\Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized5\ + port map ( + D(2 downto 0) => D(2 downto 0), + E(0) => E(0), + \GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg\ => \GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg\, + \GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg\ => \GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg\, + \INFERRED_GEN.cnt_i_reg[2]\(0) => \INFERRED_GEN.cnt_i_reg[2]\(0), + \INFERRED_GEN.cnt_i_reg[3]\ => \INFERRED_GEN.cnt_i_reg[3]\, + Q(3 downto 0) => Q(3 downto 0), + \in\(1 downto 0) => \in\(1 downto 0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + m_axi_s2mm_bready => m_axi_s2mm_bready, + m_axi_s2mm_bresp(1 downto 0) => m_axi_s2mm_bresp(1 downto 0), + m_axi_s2mm_bvalid => m_axi_s2mm_bvalid, + \out\(0) => \out\(0), + sig_halt_reg => sig_halt_reg, + sig_inhibit_rdy_n => sig_inhibit_rdy_n, + sig_posted_to_axi_reg => sig_posted_to_axi_reg, + sig_push_coelsc_reg => sig_push_coelsc_reg, + sig_stream_rst => sig_stream_rst + ); +sig_child_error_reg_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^sig_init_reg2_reg\, + I1 => sig_csm_pop_child_cmd, + O => SR(0) + ); +sig_inhibit_rdy_n_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => sig_init_done_3, + I1 => sig_inhibit_rdy_n, + O => sig_inhibit_rdy_n_i_1_n_0 + ); +sig_inhibit_rdy_n_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_inhibit_rdy_n_i_1_n_0, + Q => sig_inhibit_rdy_n, + R => sig_stream_rst + ); +sig_init_done_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"0080" + ) + port map ( + I0 => \^sig_init_reg2_reg\, + I1 => sig_init_reg2, + I2 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I3 => sig_init_done_3, + O => sig_init_done_i_1_n_0 + ); +sig_init_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_init_done_i_1_n_0, + Q => sig_init_done_3, + R => '0' + ); +sig_init_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_stream_rst, + Q => \^sig_init_reg2_reg\, + R => '0' + ); +\sig_input_addr_reg[31]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^sig_init_reg2_reg\, + I1 => sig_psm_pop_input_cmd, + O => sig_input_cache_type_reg0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized6\ is + port ( + p_0_in : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + sig_push_to_wsc_reg : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + sel : out STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[1]\ : out STD_LOGIC; + sig_push_coelsc_reg : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + p_4_out : out STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_data2wsc_valid : in STD_LOGIC; + sig_set_push2wsc : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \INFERRED_GEN.cnt_i_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_coelsc_reg_empty : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_INDET_BTT.lsig_eop_reg_reg\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); + sig_init_reg_reg : in STD_LOGIC; + sig_init_reg2 : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized6\ : entity is "axi_datamover_fifo"; +end \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized6\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized6\ is + signal sig_inhibit_rdy_n : STD_LOGIC; + signal sig_inhibit_rdy_n_i_1_n_0 : STD_LOGIC; + signal sig_init_done : STD_LOGIC; + signal sig_init_done_i_1_n_0 : STD_LOGIC; +begin +\USE_SRL_FIFO.I_SYNC_FIFO\: entity work.\Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized6\ + port map ( + D(2 downto 0) => D(2 downto 0), + E(0) => E(0), + \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg\ => sel, + \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg_0\ => sig_push_coelsc_reg, + \GEN_INDET_BTT.lsig_eop_reg_reg\(15 downto 0) => \GEN_INDET_BTT.lsig_eop_reg_reg\(15 downto 0), + \INFERRED_GEN.cnt_i_reg[1]\ => \INFERRED_GEN.cnt_i_reg[1]\, + \INFERRED_GEN.cnt_i_reg[3]\(0) => \INFERRED_GEN.cnt_i_reg[3]\(0), + Q(3 downto 0) => Q(3 downto 0), + \in\(0) => \in\(0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\(15 downto 0) => \out\(15 downto 0), + p_0_in => p_0_in, + p_4_out => p_4_out, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_coelsc_reg_empty => sig_coelsc_reg_empty, + sig_data2wsc_valid => sig_data2wsc_valid, + sig_inhibit_rdy_n => sig_inhibit_rdy_n, + sig_push_to_wsc_reg => sig_push_to_wsc_reg, + sig_set_push2wsc => sig_set_push2wsc, + sig_stream_rst => sig_stream_rst + ); +sig_inhibit_rdy_n_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => sig_init_done, + I1 => sig_inhibit_rdy_n, + O => sig_inhibit_rdy_n_i_1_n_0 + ); +sig_inhibit_rdy_n_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_inhibit_rdy_n_i_1_n_0, + Q => sig_inhibit_rdy_n, + R => sig_stream_rst + ); +sig_init_done_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"0080" + ) + port map ( + I0 => sig_init_reg_reg, + I1 => sig_init_reg2, + I2 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I3 => sig_init_done, + O => sig_init_done_i_1_n_0 + ); +sig_init_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_init_done_i_1_n_0, + Q => sig_init_done, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized7\ is + port ( + \INFERRED_GEN.cnt_i_reg[0]\ : out STD_LOGIC; + sig_init_reg2 : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : out STD_LOGIC_VECTOR ( 19 downto 0 ); + \INFERRED_GEN.cnt_i_reg[0]_0\ : out STD_LOGIC; + \GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg\ : out STD_LOGIC; + sig_sm_pop_cmd_fifo_ns : out STD_LOGIC; + sig_sm_ld_dre_cmd_ns : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_init_reg : in STD_LOGIC; + sig_need_cmd_flush : in STD_LOGIC; + p_7_out : in STD_LOGIC; + sig_sm_pop_cmd_fifo : in STD_LOGIC; + p_9_out_0 : in STD_LOGIC; + lsig_cmd_fetch_pause : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + \sig_good_tlast_dbeat37_out__0\ : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 21 downto 0 ); + \FSM_sequential_sig_cmdcntl_sm_state_reg[0]\ : in STD_LOGIC; + \FSM_sequential_sig_cmdcntl_sm_state_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_cmd_empty_reg : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized7\ : entity is "axi_datamover_fifo"; +end \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized7\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized7\ is + signal \^inferred_gen.cnt_i_reg[0]_0\ : STD_LOGIC; + signal sig_inhibit_rdy_n_i_1_n_0 : STD_LOGIC; + signal sig_init_done : STD_LOGIC; + signal sig_init_done_i_1_n_0 : STD_LOGIC; + signal \^sig_init_reg2\ : STD_LOGIC; +begin + \INFERRED_GEN.cnt_i_reg[0]_0\ <= \^inferred_gen.cnt_i_reg[0]_0\; + sig_init_reg2 <= \^sig_init_reg2\; +\USE_SRL_FIFO.I_SYNC_FIFO\: entity work.\Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized7\ + port map ( + D(2 downto 0) => D(2 downto 0), + E(0) => E(0), + \FSM_sequential_sig_cmdcntl_sm_state_reg[0]\ => \FSM_sequential_sig_cmdcntl_sm_state_reg[0]\, + \FSM_sequential_sig_cmdcntl_sm_state_reg[2]\(2 downto 0) => \FSM_sequential_sig_cmdcntl_sm_state_reg[2]\(2 downto 0), + \GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg\ => \GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg\, + \INFERRED_GEN.cnt_i_reg[0]\ => \INFERRED_GEN.cnt_i_reg[0]\, + Q(0) => Q(0), + \in\(21 downto 0) => \in\(21 downto 0), + lsig_cmd_fetch_pause => lsig_cmd_fetch_pause, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\(19 downto 0) => \out\(19 downto 0), + p_7_out => p_7_out, + p_9_out_0 => p_9_out_0, + sig_cmd_empty_reg => sig_cmd_empty_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + \sig_good_tlast_dbeat37_out__0\ => \sig_good_tlast_dbeat37_out__0\, + sig_inhibit_rdy_n_reg => \^inferred_gen.cnt_i_reg[0]_0\, + sig_need_cmd_flush => sig_need_cmd_flush, + sig_sm_ld_dre_cmd_ns => sig_sm_ld_dre_cmd_ns, + sig_sm_pop_cmd_fifo => sig_sm_pop_cmd_fifo, + sig_sm_pop_cmd_fifo_ns => sig_sm_pop_cmd_fifo_ns, + sig_stream_rst => sig_stream_rst + ); +sig_inhibit_rdy_n_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => sig_init_done, + I1 => \^inferred_gen.cnt_i_reg[0]_0\, + O => sig_inhibit_rdy_n_i_1_n_0 + ); +sig_inhibit_rdy_n_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_inhibit_rdy_n_i_1_n_0, + Q => \^inferred_gen.cnt_i_reg[0]_0\, + R => sig_stream_rst + ); +sig_init_done_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"0080" + ) + port map ( + I0 => sig_init_reg, + I1 => \^sig_init_reg2\, + I2 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I3 => sig_init_done, + O => sig_init_done_i_1_n_0 + ); +sig_init_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_init_done_i_1_n_0, + Q => sig_init_done, + R => '0' + ); +sig_init_reg2_reg: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_init_reg, + Q => \^sig_init_reg2\, + S => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized8\ is + port ( + \INFERRED_GEN.cnt_i_reg[1]\ : out STD_LOGIC; + SS : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.lsig_first_dbeat_reg\ : out STD_LOGIC; + \sig_byte_cntr_reg[0]\ : out STD_LOGIC; + sig_dre2ibtt_tlast : out STD_LOGIC; + sig_cmd_full_reg : out STD_LOGIC; + sig_cmd_empty_reg : out STD_LOGIC; + \sig_good_tlast_dbeat37_out__0\ : out STD_LOGIC; + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + Q : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_s_ready_dup4_reg : out STD_LOGIC; + \sig_byte_cntr_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\ : out STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0]\ : out STD_LOGIC; + sig_inhibit_rdy_n : out STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_INDET_BTT.lsig_absorb2tlast_reg\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_eop_sent : out STD_LOGIC; + \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg\ : out STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + sig_eop_sent_reg : in STD_LOGIC; + \INCLUDE_PACKING.lsig_first_dbeat_reg_0\ : in STD_LOGIC; + sig_cmd_full : in STD_LOGIC; + sig_sm_ld_dre_cmd : in STD_LOGIC; + p_7_out : in STD_LOGIC; + sig_strm_tlast : in STD_LOGIC; + sig_m_valid_out_reg : in STD_LOGIC; + lsig_absorb2tlast : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_last_reg_out_reg : in STD_LOGIC; + sig_eop_halt_xfer : in STD_LOGIC; + sig_ibtt2dre_tready : in STD_LOGIC; + \out\ : in STD_LOGIC; + sig_clr_dbc_reg : in STD_LOGIC; + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + slice_insert_valid : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0\ : in STD_LOGIC; + p_0_in : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0\ : in STD_LOGIC; + lsig_cmd_fetch_pause : in STD_LOGIC; + sig_need_cmd_flush : in STD_LOGIC; + sig_sm_pop_cmd_fifo : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized8\ : entity is "axi_datamover_fifo"; +end \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized8\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized8\ is + signal \^ss\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^sig_inhibit_rdy_n\ : STD_LOGIC; + signal sig_inhibit_rdy_n_i_1_n_0 : STD_LOGIC; + signal sig_init_done : STD_LOGIC; + signal sig_init_done_i_1_n_0 : STD_LOGIC; + signal sig_init_reg : STD_LOGIC; + signal sig_init_reg2 : STD_LOGIC; +begin + SS(0) <= \^ss\(0); + sig_inhibit_rdy_n <= \^sig_inhibit_rdy_n\; +\USE_SRL_FIFO.I_SYNC_FIFO\: entity work.\Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized8\ + port map ( + E(0) => E(0), + \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg\ => \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg\, + \GEN_INDET_BTT.lsig_absorb2tlast_reg\(0) => \GEN_INDET_BTT.lsig_absorb2tlast_reg\(0), + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1]\(1 downto 0) => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1]\(1 downto 0), + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0]\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\(1 downto 0) => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\(1 downto 0), + \INCLUDE_PACKING.lsig_first_dbeat_reg\ => \INCLUDE_PACKING.lsig_first_dbeat_reg\, + \INCLUDE_PACKING.lsig_first_dbeat_reg_0\ => \INCLUDE_PACKING.lsig_first_dbeat_reg_0\, + \INFERRED_GEN.cnt_i_reg[1]\ => \INFERRED_GEN.cnt_i_reg[1]\, + \INFERRED_GEN.cnt_i_reg[4]\ => \^ss\(0), + Q(0) => Q(0), + SR(0) => SR(0), + \in\(1 downto 0) => \in\(1 downto 0), + lsig_absorb2tlast => lsig_absorb2tlast, + lsig_cmd_fetch_pause => lsig_cmd_fetch_pause, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\ => \out\, + p_0_in => p_0_in, + p_7_out => p_7_out, + \sig_byte_cntr_reg[0]\ => \sig_byte_cntr_reg[0]\, + \sig_byte_cntr_reg[7]\(0) => \sig_byte_cntr_reg[7]\(0), + sig_clr_dbc_reg => sig_clr_dbc_reg, + sig_cmd_empty_reg => sig_cmd_empty_reg, + sig_cmd_full => sig_cmd_full, + sig_cmd_full_reg => sig_cmd_full_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_dre2ibtt_tlast => sig_dre2ibtt_tlast, + sig_eop_halt_xfer => sig_eop_halt_xfer, + sig_eop_sent => sig_eop_sent, + sig_eop_sent_reg => sig_eop_sent_reg, + \sig_good_tlast_dbeat37_out__0\ => \sig_good_tlast_dbeat37_out__0\, + sig_ibtt2dre_tready => sig_ibtt2dre_tready, + sig_inhibit_rdy_n_reg => \^sig_inhibit_rdy_n\, + sig_last_reg_out_reg => sig_last_reg_out_reg, + sig_m_valid_out_reg => sig_m_valid_out_reg, + sig_need_cmd_flush => sig_need_cmd_flush, + sig_s_ready_dup4_reg => sig_s_ready_dup4_reg, + sig_sm_ld_dre_cmd => sig_sm_ld_dre_cmd, + sig_sm_pop_cmd_fifo => sig_sm_pop_cmd_fifo, + sig_strm_tlast => sig_strm_tlast, + slice_insert_valid => slice_insert_valid + ); +sig_inhibit_rdy_n_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => sig_init_done, + I1 => \^sig_inhibit_rdy_n\, + O => sig_inhibit_rdy_n_i_1_n_0 + ); +sig_inhibit_rdy_n_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_inhibit_rdy_n_i_1_n_0, + Q => \^sig_inhibit_rdy_n\, + R => \^ss\(0) + ); +sig_init_done_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"00080000" + ) + port map ( + I0 => sig_init_reg, + I1 => sig_init_reg2, + I2 => sig_init_done, + I3 => sig_eop_sent_reg, + I4 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + O => sig_init_done_i_1_n_0 + ); +sig_init_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_init_done_i_1_n_0, + Q => sig_init_done, + R => '0' + ); +sig_init_reg2_reg: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_init_reg, + Q => sig_init_reg2, + S => \^ss\(0) + ); +sig_init_reg_reg: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_eop_sent_reg, + Q => sig_init_reg, + S => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized9\ is + port ( + \INFERRED_GEN.cnt_i_reg[0]\ : out STD_LOGIC; + sig_init_done : out STD_LOGIC; + p_0_in : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 41 downto 0 ); + sig_calc_error_reg_reg : out STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[0]_0\ : out STD_LOGIC; + \sig_clr_cmd2addr_valid3_out__0\ : out STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_init_reg_reg : in STD_LOGIC; + sig_halt_reg : in STD_LOGIC; + sig_addr_reg_empty_reg : in STD_LOGIC; + p_22_out : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 39 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized9\ : entity is "axi_datamover_fifo"; +end \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized9\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized9\ is + signal \^inferred_gen.cnt_i_reg[0]_0\ : STD_LOGIC; + signal sig_inhibit_rdy_n_i_1_n_0 : STD_LOGIC; + signal \^sig_init_done\ : STD_LOGIC; +begin + \INFERRED_GEN.cnt_i_reg[0]_0\ <= \^inferred_gen.cnt_i_reg[0]_0\; + sig_init_done <= \^sig_init_done\; +\USE_SRL_FIFO.I_SYNC_FIFO\: entity work.\Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized9\ + port map ( + \INFERRED_GEN.cnt_i_reg[0]\ => \INFERRED_GEN.cnt_i_reg[0]\, + \in\(39 downto 0) => \in\(39 downto 0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\(41 downto 0) => \out\(41 downto 0), + p_0_in => p_0_in, + p_22_out => p_22_out, + sig_addr_reg_empty_reg => sig_addr_reg_empty_reg, + sig_calc_error_reg_reg => sig_calc_error_reg_reg, + \sig_clr_cmd2addr_valid3_out__0\ => \sig_clr_cmd2addr_valid3_out__0\, + sig_halt_reg => sig_halt_reg, + sig_inhibit_rdy_n_reg => \^inferred_gen.cnt_i_reg[0]_0\, + sig_stream_rst => sig_stream_rst + ); +sig_inhibit_rdy_n_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^sig_init_done\, + I1 => \^inferred_gen.cnt_i_reg[0]_0\, + O => sig_inhibit_rdy_n_i_1_n_0 + ); +sig_inhibit_rdy_n_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_inhibit_rdy_n_i_1_n_0, + Q => \^inferred_gen.cnt_i_reg[0]_0\, + R => sig_stream_rst + ); +sig_init_done_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_init_reg_reg, + Q => \^sig_init_done\, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_top is + port ( + DOBDO : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : out STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[2]\ : out STD_LOGIC; + DIN : out STD_LOGIC_VECTOR ( 0 to 0 ); + dm2linebuf_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gc1.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \gcc0.gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + lsig_cmd_loaded : in STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ : in STD_LOGIC; + hold_ff_q : in STD_LOGIC; + \out\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_top : entity is "blk_mem_gen_top"; +end Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_top; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_top is +begin +\valid.cstr\: entity work.Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_generic_cstr + port map ( + DIBDI(1 downto 0) => DIBDI(1 downto 0), + DIN(0) => DIN(0), + DOBDO(0) => DOBDO(0), + E(0) => E(0), + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, + \INFERRED_GEN.cnt_i_reg[2]\ => \INFERRED_GEN.cnt_i_reg[2]\, + Q(0) => Q(0), + SR(0) => SR(0), + dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), + \gc1.count_d2_reg[7]\(7 downto 0) => \gc1.count_d2_reg[7]\(7 downto 0), + \gcc0.gc0.count_d1_reg[7]\(7 downto 0) => \gcc0.gc0.count_d1_reg[7]\(7 downto 0), + \gpregsm1.curr_fwft_state_reg[0]\ => \gpregsm1.curr_fwft_state_reg[0]\, + hold_ff_q => hold_ff_q, + lsig_cmd_loaded => lsig_cmd_loaded, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axi_mm2s_rdata(63 downto 0) => m_axi_mm2s_rdata(63 downto 0), + \out\ => \out\, + \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ => \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_top__parameterized0\ is + port ( + sig_data_fifo_data_out : out STD_LOGIC_VECTOR ( 65 downto 0 ); + m_axi_s2mm_aclk : in STD_LOGIC; + ram_empty_fb_i_reg : in STD_LOGIC; + WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_s_ready_out_reg : in STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + \gc1.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 7 downto 0 ); + lsig_combined_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); + DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_top__parameterized0\ : entity is "blk_mem_gen_top"; +end \Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_top__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_top__parameterized0\ is +begin +\valid.cstr\: entity work.\Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_generic_cstr__parameterized0\ + port map ( + DIBDI(1 downto 0) => DIBDI(1 downto 0), + Q(7 downto 0) => Q(7 downto 0), + WEBWE(0) => WEBWE(0), + \gc1.count_d2_reg[7]\(7 downto 0) => \gc1.count_d2_reg[7]\(7 downto 0), + lsig_combined_data(63 downto 0) => lsig_combined_data(63 downto 0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + ram_empty_fb_i_reg => ram_empty_fb_i_reg, + sig_data_fifo_data_out(65 downto 0) => sig_data_fifo_data_out(65 downto 0), + sig_s_ready_out_reg => sig_s_ready_out_reg, + sig_stream_rst => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_fifo_generator_ramfifo__parameterized0\ is + port ( + hold_ff_q_reg : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_xfer_is_seq_reg_reg : out STD_LOGIC_VECTOR ( 9 downto 0 ); + \sig_child_addr_cntr_lsh_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + S : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \sig_xfer_len_reg_reg[4]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \sig_xfer_len_reg_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_xfer_is_seq_reg_reg_0 : out STD_LOGIC; + sig_xfer_cmd_cmplt_reg0 : out STD_LOGIC; + sig_sf2pcc_xfer_valid : out STD_LOGIC; + sig_ibtt2dre_tready : out STD_LOGIC; + sig_csm_state_ns1 : out STD_LOGIC; + \gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \gpr1.dout_i_reg[1]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + O : out STD_LOGIC_VECTOR ( 3 downto 0 ); + CO : out STD_LOGIC_VECTOR ( 0 to 0 ); + \sig_child_addr_cntr_lsh_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + p_32_out : in STD_LOGIC; + hold_ff_q : in STD_LOGIC; + sig_adjusted_addr_incr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + sig_clr_dbc_reg_reg : in STD_LOGIC; + sig_csm_pop_child_cmd : in STD_LOGIC; + sig_child_qual_first_of_2 : in STD_LOGIC; + sig_child_qual_error_reg : in STD_LOGIC; + lsig_packer_full : in STD_LOGIC; + ram_full_i_reg : in STD_LOGIC; + \gpr1.dout_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \gpr1.dout_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + sig_child_addr_cntr_lsh_reg : in STD_LOGIC_VECTOR ( 2 downto 0 ); + p_0_out : in STD_LOGIC_VECTOR ( 10 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_ramfifo__parameterized0\ : entity is "fifo_generator_ramfifo"; +end \Arty_Z7_20_axi_vdma_0_0_fifo_generator_ramfifo__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_ramfifo__parameterized0\ is + signal \gntv_or_sync_fifo.gl0.rd_n_2\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd_n_3\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.wr_n_0\ : STD_LOGIC; + signal \^gpr1.dout_i_reg[1]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \grss.rsts/ram_empty_i0__3\ : STD_LOGIC; + signal p_1_in : STD_LOGIC; + signal p_2_out : STD_LOGIC; + signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 ); +begin + \gpr1.dout_i_reg[1]_0\(2 downto 0) <= \^gpr1.dout_i_reg[1]_0\(2 downto 0); +\gntv_or_sync_fifo.gl0.rd\: entity work.\Arty_Z7_20_axi_vdma_0_0_rd_logic__parameterized0\ + port map ( + E(0) => \gntv_or_sync_fifo.gl0.rd_n_2\, + Q(2 downto 0) => rd_pntr_plus1(2 downto 0), + \gc1.count_reg[2]\ => \gntv_or_sync_fifo.gl0.rd_n_3\, + \gpr1.dout_i_reg[1]\(2 downto 0) => \^gpr1.dout_i_reg[1]_0\(2 downto 0), + hold_ff_q => hold_ff_q, + hold_ff_q_reg => hold_ff_q_reg, + lsig_packer_full => lsig_packer_full, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\ => p_2_out, + p_32_out => p_32_out, + \ram_empty_i0__3\ => \grss.rsts/ram_empty_i0__3\, + ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_0\, + ram_full_i_reg => ram_full_i_reg, + ram_full_i_reg_0 => p_1_in, + sig_clr_dbc_reg_reg => sig_clr_dbc_reg_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_ibtt2dre_tready => sig_ibtt2dre_tready, + sig_sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid, + sig_stream_rst => sig_stream_rst + ); +\gntv_or_sync_fifo.gl0.wr\: entity work.\Arty_Z7_20_axi_vdma_0_0_wr_logic__parameterized0\ + port map ( + E(0) => E(0), + Q(2 downto 0) => rd_pntr_plus1(2 downto 0), + \gc1.count_d2_reg[2]\(2 downto 0) => \^gpr1.dout_i_reg[1]_0\(2 downto 0), + \gpr1.dout_i_reg[1]\(2 downto 0) => \gpr1.dout_i_reg[1]\(2 downto 0), + \gv.ram_valid_d1_reg\ => \gntv_or_sync_fifo.gl0.rd_n_3\, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\ => \gntv_or_sync_fifo.gl0.wr_n_0\, + ram_empty_fb_i_reg => p_2_out, + \ram_empty_i0__3\ => \grss.rsts/ram_empty_i0__3\, + \sig_byte_cntr_reg[0]\ => p_1_in, + sig_clr_dbc_reg_reg => sig_clr_dbc_reg_reg, + sig_stream_rst => sig_stream_rst + ); +\gntv_or_sync_fifo.mem\: entity work.\Arty_Z7_20_axi_vdma_0_0_memory__parameterized0\ + port map ( + CO(0) => CO(0), + D(2 downto 0) => D(2 downto 0), + E(0) => \gntv_or_sync_fifo.gl0.rd_n_2\, + O(3 downto 0) => O(3 downto 0), + S(3 downto 0) => S(3 downto 0), + \gpr1.dout_i_reg[3]\(3 downto 0) => \gpr1.dout_i_reg[3]\(3 downto 0), + \gpr1.dout_i_reg[7]\(3 downto 0) => \gpr1.dout_i_reg[7]\(3 downto 0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + p_0_out(10 downto 0) => p_0_out(10 downto 0), + sig_adjusted_addr_incr(8 downto 0) => sig_adjusted_addr_incr(8 downto 0), + sig_child_addr_cntr_lsh_reg(2 downto 0) => sig_child_addr_cntr_lsh_reg(2 downto 0), + \sig_child_addr_cntr_lsh_reg[11]\(0) => \sig_child_addr_cntr_lsh_reg[11]\(0), + \sig_child_addr_cntr_lsh_reg[7]\(3 downto 0) => \sig_child_addr_cntr_lsh_reg[7]\(3 downto 0), + sig_child_qual_error_reg => sig_child_qual_error_reg, + sig_child_qual_first_of_2 => sig_child_qual_first_of_2, + sig_csm_pop_child_cmd => sig_csm_pop_child_cmd, + sig_csm_state_ns1 => sig_csm_state_ns1, + sig_stream_rst => sig_stream_rst, + sig_xfer_cmd_cmplt_reg0 => sig_xfer_cmd_cmplt_reg0, + sig_xfer_is_seq_reg_reg(9 downto 0) => sig_xfer_is_seq_reg_reg(9 downto 0), + sig_xfer_is_seq_reg_reg_0 => sig_xfer_is_seq_reg_reg_0, + \sig_xfer_len_reg_reg[4]\(3 downto 0) => \sig_xfer_len_reg_reg[4]\(3 downto 0), + \sig_xfer_len_reg_reg[5]\(0) => \sig_xfer_len_reg_reg[5]\(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_builtin is + port ( + sig_m_valid_out_reg : out STD_LOGIC; + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ : out STD_LOGIC; + FULL : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\ : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1\ : out STD_LOGIC; + fifo_dout : out STD_LOGIC_VECTOR ( 33 downto 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + s_axis_fifo_ainit_nosync_reg : in STD_LOGIC; + m_axis_mm2s_aclk : in STD_LOGIC; + \out\ : in STD_LOGIC; + lsig_0ffset_cntr : in STD_LOGIC; + mm2s_prmry_resetn : in STD_LOGIC; + mm2s_halt : in STD_LOGIC; + p_24_out : in STD_LOGIC; + hold_ff_q_reg : in STD_LOGIC; + DIN : in STD_LOGIC_VECTOR ( 15 downto 0 ); + WR_EN : in STD_LOGIC; + dm2linebuf_mm2s_tdata : in STD_LOGIC_VECTOR ( 17 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_builtin : entity is "fifo_generator_v13_1_3_builtin"; +end Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_builtin; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_builtin is + signal rd_rst_i : STD_LOGIC; +begin +\g7ser_birst.rstbt\: entity work.Arty_Z7_20_axi_vdma_0_0_reset_builtin_39 + port map ( + RST => rd_rst_i, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axis_mm2s_aclk => m_axis_mm2s_aclk, + s_axis_fifo_ainit_nosync_reg => s_axis_fifo_ainit_nosync_reg + ); +\v7_bi_fifo.fblk\: entity work.Arty_Z7_20_axi_vdma_0_0_builtin_top_v6 + port map ( + DIN(15 downto 0) => DIN(15 downto 0), + FULL => FULL, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1\, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, + RST => rd_rst_i, + WR_EN => WR_EN, + dm2linebuf_mm2s_tdata(17 downto 0) => dm2linebuf_mm2s_tdata(17 downto 0), + fifo_dout(33 downto 0) => fifo_dout(33 downto 0), + hold_ff_q_reg => hold_ff_q_reg, + lsig_0ffset_cntr => lsig_0ffset_cntr, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axis_mm2s_aclk => m_axis_mm2s_aclk, + mm2s_halt => mm2s_halt, + mm2s_prmry_resetn => mm2s_prmry_resetn, + \out\ => \out\, + p_24_out => p_24_out, + sig_m_valid_out_reg => sig_m_valid_out_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_builtin__parameterized0\ is + port ( + FULL : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 12 downto 0 ); + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]\ : out STD_LOGIC; + DOUT : out STD_LOGIC_VECTOR ( 8 downto 0 ); + EMPTY : out STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\ : out STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\ : out STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\ : out STD_LOGIC; + strm_not_finished_no_dwidth : out STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); + s_axis_s2mm_aclk : in STD_LOGIC; + sig_reset_reg : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + M_VALID : in STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\ : in STD_LOGIC; + s2mm_fsync_out_i : in STD_LOGIC; + \out\ : in STD_LOGIC; + p_3_out : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 6 downto 0 ); + \vsize_vid_reg[12]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : in STD_LOGIC; + minusOp_1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0\ : in STD_LOGIC; + s2mm_strm_wready : in STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + DIN : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\ : in STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + minusOp : in STD_LOGIC_VECTOR ( 11 downto 0 ); + RD_EN : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_builtin__parameterized0\ : entity is "fifo_generator_v13_1_3_builtin"; +end \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_builtin__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_builtin__parameterized0\ is + signal wr_rst_i : STD_LOGIC; +begin +\g7ser_birst.rstbt\: entity work.Arty_Z7_20_axi_vdma_0_0_reset_builtin + port map ( + RST => wr_rst_i, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + s_axis_s2mm_aclk => s_axis_s2mm_aclk, + sig_reset_reg => sig_reset_reg + ); +\v7_bi_fifo.fblk\: entity work.\Arty_Z7_20_axi_vdma_0_0_builtin_top_v6__parameterized0\ + port map ( + D(12 downto 0) => D(12 downto 0), + DIN(8 downto 0) => DIN(8 downto 0), + DOUT(8 downto 0) => DOUT(8 downto 0), + EMPTY => EMPTY, + FULL => FULL, + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\, + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\(12 downto 0) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\(12 downto 0), + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]\ => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]\, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0\ => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0\, + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\ => \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0]\(0) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0]\(0), + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\(12 downto 0) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\(12 downto 0), + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\, + M_VALID => M_VALID, + Q(6 downto 0) => Q(6 downto 0), + RD_EN => RD_EN, + RST => wr_rst_i, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + minusOp(11 downto 0) => minusOp(11 downto 0), + minusOp_1(11 downto 0) => minusOp_1(11 downto 0), + \out\ => \out\, + p_3_out => p_3_out, + s2mm_fsync_out_i => s2mm_fsync_out_i, + s2mm_strm_wready => s2mm_strm_wready, + s_axis_s2mm_aclk => s_axis_s2mm_aclk, + strm_not_finished_no_dwidth => strm_not_finished_no_dwidth, + \vsize_vid_reg[12]\(12 downto 0) => \vsize_vid_reg[12]\(12 downto 0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl is + port ( + \out\ : out STD_LOGIC; + \sig_addr_posted_cntr_reg[2]\ : out STD_LOGIC; + sig_init_reg2 : out STD_LOGIC; + m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_arvalid : out STD_LOGIC; + sig_wr_fifo : out STD_LOGIC; + sig_halt_cmplt_reg : out STD_LOGIC; + m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 4 downto 0 ); + m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 1 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_init_reg : in STD_LOGIC; + m_axi_mm2s_aclk : in STD_LOGIC; + sig_sf_allow_addr_req : in STD_LOGIC; + sig_data2addr_stop_req : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + m_axi_mm2s_arready : in STD_LOGIC; + sig_mstr2addr_cmd_valid : in STD_LOGIC; + sig_halt_reg_dly3 : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 38 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl : entity is "axi_datamover_addr_cntl"; +end Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl is + signal \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\ : STD_LOGIC; + signal \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_43\ : STD_LOGIC; + signal p_1_out : STD_LOGIC_VECTOR ( 50 downto 4 ); + signal sig_addr2rsc_calc_error : STD_LOGIC; + signal sig_addr_reg_empty : STD_LOGIC; + signal sig_addr_reg_full : STD_LOGIC; + signal \sig_next_addr_reg[31]_i_1_n_0\ : STD_LOGIC; + signal sig_posted_to_axi : STD_LOGIC; + attribute RTL_KEEP : string; + attribute RTL_KEEP of sig_posted_to_axi : signal is "true"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of sig_posted_to_axi : signal is "no"; + signal sig_posted_to_axi_2 : STD_LOGIC; + attribute RTL_KEEP of sig_posted_to_axi_2 : signal is "true"; + attribute equivalent_register_removal of sig_posted_to_axi_2 : signal is "no"; + signal sig_push_addr_reg1_out : STD_LOGIC; + attribute KEEP : string; + attribute KEEP of sig_posted_to_axi_2_reg : label is "yes"; + attribute equivalent_register_removal of sig_posted_to_axi_2_reg : label is "no"; + attribute KEEP of sig_posted_to_axi_reg : label is "yes"; + attribute equivalent_register_removal of sig_posted_to_axi_reg : label is "no"; +begin + \out\ <= sig_posted_to_axi_2; + \sig_addr_posted_cntr_reg[2]\ <= sig_posted_to_axi; +\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO\: entity work.\Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized1\ + port map ( + SR(0) => SR(0), + \in\(38 downto 0) => \in\(38 downto 0), + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + \out\(40) => p_1_out(50), + \out\(39) => p_1_out(47), + \out\(38 downto 37) => p_1_out(45 downto 44), + \out\(36 downto 0) => p_1_out(40 downto 4), + sel => sig_wr_fifo, + sig_addr_reg_empty => sig_addr_reg_empty, + sig_addr_valid_reg_reg => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_data2addr_stop_req => sig_data2addr_stop_req, + sig_init_reg => sig_init_reg, + sig_init_reg2 => sig_init_reg2, + sig_mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid, + sig_posted_to_axi_2_reg => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_43\, + sig_push_addr_reg1_out => sig_push_addr_reg1_out, + sig_sf_allow_addr_req => sig_sf_allow_addr_req + ); +sig_addr_reg_empty_reg: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => '0', + Q => sig_addr_reg_empty, + S => \sig_next_addr_reg[31]_i_1_n_0\ + ); +sig_addr_reg_full_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => sig_push_addr_reg1_out, + Q => sig_addr_reg_full, + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +sig_addr_valid_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, + Q => m_axi_mm2s_arvalid, + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +sig_calc_error_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(50), + Q => sig_addr2rsc_calc_error, + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +sig_halt_cmplt_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"1FFF" + ) + port map ( + I0 => sig_addr2rsc_calc_error, + I1 => sig_addr_reg_empty, + I2 => sig_halt_reg_dly3, + I3 => sig_data2addr_stop_req, + O => sig_halt_cmplt_reg + ); +\sig_next_addr_reg[31]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"40FF" + ) + port map ( + I0 => sig_addr2rsc_calc_error, + I1 => sig_addr_reg_full, + I2 => m_axi_mm2s_arready, + I3 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + O => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(4), + Q => m_axi_mm2s_araddr(0), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(14), + Q => m_axi_mm2s_araddr(10), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(15), + Q => m_axi_mm2s_araddr(11), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(16), + Q => m_axi_mm2s_araddr(12), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(17), + Q => m_axi_mm2s_araddr(13), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(18), + Q => m_axi_mm2s_araddr(14), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(19), + Q => m_axi_mm2s_araddr(15), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(20), + Q => m_axi_mm2s_araddr(16), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(21), + Q => m_axi_mm2s_araddr(17), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(22), + Q => m_axi_mm2s_araddr(18), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(23), + Q => m_axi_mm2s_araddr(19), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(5), + Q => m_axi_mm2s_araddr(1), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(24), + Q => m_axi_mm2s_araddr(20), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(25), + Q => m_axi_mm2s_araddr(21), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(26), + Q => m_axi_mm2s_araddr(22), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(27), + Q => m_axi_mm2s_araddr(23), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(28), + Q => m_axi_mm2s_araddr(24), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(29), + Q => m_axi_mm2s_araddr(25), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(30), + Q => m_axi_mm2s_araddr(26), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(31), + Q => m_axi_mm2s_araddr(27), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(32), + Q => m_axi_mm2s_araddr(28), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(33), + Q => m_axi_mm2s_araddr(29), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(6), + Q => m_axi_mm2s_araddr(2), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(34), + Q => m_axi_mm2s_araddr(30), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(35), + Q => m_axi_mm2s_araddr(31), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(7), + Q => m_axi_mm2s_araddr(3), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(8), + Q => m_axi_mm2s_araddr(4), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(9), + Q => m_axi_mm2s_araddr(5), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(10), + Q => m_axi_mm2s_araddr(6), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(11), + Q => m_axi_mm2s_araddr(7), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(12), + Q => m_axi_mm2s_araddr(8), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_addr_reg_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(13), + Q => m_axi_mm2s_araddr(9), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_burst_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(47), + Q => m_axi_mm2s_arburst(0), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_len_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(36), + Q => m_axi_mm2s_arlen(0), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_len_reg_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(37), + Q => m_axi_mm2s_arlen(1), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_len_reg_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(38), + Q => m_axi_mm2s_arlen(2), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_len_reg_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(39), + Q => m_axi_mm2s_arlen(3), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_len_reg_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(40), + Q => m_axi_mm2s_arlen(4), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_size_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(44), + Q => m_axi_mm2s_arsize(0), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +\sig_next_size_reg_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_addr_reg1_out, + D => p_1_out(45), + Q => m_axi_mm2s_arsize(1), + R => \sig_next_addr_reg[31]_i_1_n_0\ + ); +sig_posted_to_axi_2_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_43\, + Q => sig_posted_to_axi_2, + R => '0' + ); +sig_posted_to_axi_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_43\, + Q => sig_posted_to_axi, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl__parameterized0\ is + port ( + \out\ : out STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[0]\ : out STD_LOGIC; + sig_addr_reg_empty : out STD_LOGIC; + sig_addr2wsc_calc_error : out STD_LOGIC; + m_axi_s2mm_awburst : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_s2mm_awvalid : out STD_LOGIC; + sig_init_done : out STD_LOGIC; + sig_inhibit_rdy_n : out STD_LOGIC; + \sig_clr_cmd2addr_valid3_out__0\ : out STD_LOGIC; + m_axi_s2mm_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_s2mm_awlen : out STD_LOGIC_VECTOR ( 5 downto 0 ); + m_axi_s2mm_awsize : out STD_LOGIC_VECTOR ( 1 downto 0 ); + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_init_reg_reg : in STD_LOGIC; + m_axi_s2mm_awready : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_halt_reg : in STD_LOGIC; + p_22_out : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 39 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl__parameterized0\ : entity is "axi_datamover_addr_cntl"; +end \Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl__parameterized0\ is + signal \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\ : STD_LOGIC; + signal p_0_in : STD_LOGIC; + signal p_1_out : STD_LOGIC_VECTOR ( 50 downto 4 ); + signal \^sig_addr2wsc_calc_error\ : STD_LOGIC; + signal \^sig_addr_reg_empty\ : STD_LOGIC; + signal sig_addr_reg_full : STD_LOGIC; + signal \sig_next_addr_reg[31]_i_1__0_n_0\ : STD_LOGIC; + signal sig_posted_to_axi : STD_LOGIC; + attribute RTL_KEEP : string; + attribute RTL_KEEP of sig_posted_to_axi : signal is "true"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of sig_posted_to_axi : signal is "no"; + signal sig_posted_to_axi_2 : STD_LOGIC; + attribute RTL_KEEP of sig_posted_to_axi_2 : signal is "true"; + attribute equivalent_register_removal of sig_posted_to_axi_2 : signal is "no"; + attribute KEEP : string; + attribute KEEP of sig_posted_to_axi_2_reg : label is "yes"; + attribute equivalent_register_removal of sig_posted_to_axi_2_reg : label is "no"; + attribute KEEP of sig_posted_to_axi_reg : label is "yes"; + attribute equivalent_register_removal of sig_posted_to_axi_reg : label is "no"; +begin + \out\ <= sig_posted_to_axi; + sig_addr2wsc_calc_error <= \^sig_addr2wsc_calc_error\; + sig_addr_reg_empty <= \^sig_addr_reg_empty\; +\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO\: entity work.\Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized9\ + port map ( + \INFERRED_GEN.cnt_i_reg[0]\ => \INFERRED_GEN.cnt_i_reg[0]\, + \INFERRED_GEN.cnt_i_reg[0]_0\ => sig_inhibit_rdy_n, + \in\(39 downto 0) => \in\(39 downto 0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\(41) => p_1_out(50), + \out\(40) => p_1_out(47), + \out\(39 downto 38) => p_1_out(45 downto 44), + \out\(37 downto 0) => p_1_out(41 downto 4), + p_0_in => p_0_in, + p_22_out => p_22_out, + sig_addr_reg_empty_reg => \^sig_addr_reg_empty\, + sig_calc_error_reg_reg => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + \sig_clr_cmd2addr_valid3_out__0\ => \sig_clr_cmd2addr_valid3_out__0\, + sig_halt_reg => sig_halt_reg, + sig_init_done => sig_init_done, + sig_init_reg_reg => sig_init_reg_reg, + sig_stream_rst => sig_stream_rst + ); +sig_addr_reg_empty_reg: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => '0', + Q => \^sig_addr_reg_empty\, + S => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +sig_addr_reg_full_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + Q => sig_addr_reg_full, + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +sig_addr_valid_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_0_in, + Q => m_axi_s2mm_awvalid, + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +sig_calc_error_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(50), + Q => \^sig_addr2wsc_calc_error\, + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg[31]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"08FF" + ) + port map ( + I0 => m_axi_s2mm_awready, + I1 => sig_addr_reg_full, + I2 => \^sig_addr2wsc_calc_error\, + I3 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + O => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(4), + Q => m_axi_s2mm_awaddr(0), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(14), + Q => m_axi_s2mm_awaddr(10), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(15), + Q => m_axi_s2mm_awaddr(11), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(16), + Q => m_axi_s2mm_awaddr(12), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(17), + Q => m_axi_s2mm_awaddr(13), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(18), + Q => m_axi_s2mm_awaddr(14), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(19), + Q => m_axi_s2mm_awaddr(15), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(20), + Q => m_axi_s2mm_awaddr(16), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(21), + Q => m_axi_s2mm_awaddr(17), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(22), + Q => m_axi_s2mm_awaddr(18), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(23), + Q => m_axi_s2mm_awaddr(19), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(5), + Q => m_axi_s2mm_awaddr(1), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(24), + Q => m_axi_s2mm_awaddr(20), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(25), + Q => m_axi_s2mm_awaddr(21), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(26), + Q => m_axi_s2mm_awaddr(22), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(27), + Q => m_axi_s2mm_awaddr(23), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(28), + Q => m_axi_s2mm_awaddr(24), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(29), + Q => m_axi_s2mm_awaddr(25), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(30), + Q => m_axi_s2mm_awaddr(26), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(31), + Q => m_axi_s2mm_awaddr(27), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(32), + Q => m_axi_s2mm_awaddr(28), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(33), + Q => m_axi_s2mm_awaddr(29), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(6), + Q => m_axi_s2mm_awaddr(2), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(34), + Q => m_axi_s2mm_awaddr(30), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(35), + Q => m_axi_s2mm_awaddr(31), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(7), + Q => m_axi_s2mm_awaddr(3), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(8), + Q => m_axi_s2mm_awaddr(4), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(9), + Q => m_axi_s2mm_awaddr(5), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(10), + Q => m_axi_s2mm_awaddr(6), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(11), + Q => m_axi_s2mm_awaddr(7), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(12), + Q => m_axi_s2mm_awaddr(8), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_addr_reg_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(13), + Q => m_axi_s2mm_awaddr(9), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_burst_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(47), + Q => m_axi_s2mm_awburst(0), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_len_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(36), + Q => m_axi_s2mm_awlen(0), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_len_reg_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(37), + Q => m_axi_s2mm_awlen(1), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_len_reg_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(38), + Q => m_axi_s2mm_awlen(2), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_len_reg_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(39), + Q => m_axi_s2mm_awlen(3), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_len_reg_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(40), + Q => m_axi_s2mm_awlen(4), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_len_reg_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(41), + Q => m_axi_s2mm_awlen(5), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_size_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(44), + Q => m_axi_s2mm_awsize(0), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +\sig_next_size_reg_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + D => p_1_out(45), + Q => m_axi_s2mm_awsize(1), + R => \sig_next_addr_reg[31]_i_1__0_n_0\ + ); +sig_posted_to_axi_2_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + Q => sig_posted_to_axi_2, + R => sig_stream_rst + ); +sig_posted_to_axi_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_45\, + Q => sig_posted_to_axi, + R => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_cmd_status is + port ( + \INFERRED_GEN.cnt_i_reg[1]\ : out STD_LOGIC; + sig_calc_error_reg_reg : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 0 to 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_rd_sts_slverr_reg_reg : out STD_LOGIC; + sig_inhibit_rdy_n : out STD_LOGIC; + decerr_i_reg : out STD_LOGIC; + FIFO_Full_reg : out STD_LOGIC_VECTOR ( 0 to 0 ); + slverr_i_reg : out STD_LOGIC; + interr_i_reg : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 49 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_sm_halt_reg : in STD_LOGIC; + sig_input_reg_empty : in STD_LOGIC; + cmnd_wr : in STD_LOGIC; + mm2s_halt : in STD_LOGIC; + sig_rsc2stat_status_valid : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_calc_error_pushed_reg : in STD_LOGIC; + sig_calc_error_pushed : in STD_LOGIC; + p_56_out : in STD_LOGIC; + p_58_out : in STD_LOGIC; + sts_tready_reg : in STD_LOGIC; + \s_axis_cmd_tdata_reg[63]\ : in STD_LOGIC_VECTOR ( 48 downto 0 ); + sig_rd_sts_slverr_reg_reg_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_init_reg2 : in STD_LOGIC; + sig_init_reg : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_cmd_status : entity is "axi_datamover_cmd_status"; +end Arty_Z7_20_axi_vdma_0_0_axi_datamover_cmd_status; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_cmd_status is +begin +\GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO\: entity work.\Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized0\ + port map ( + \INFERRED_GEN.cnt_i_reg[1]\ => \INFERRED_GEN.cnt_i_reg[1]\, + \INFERRED_GEN.cnt_i_reg[1]_0\ => sig_inhibit_rdy_n, + Q(0) => FIFO_Full_reg(0), + SR(0) => SR(0), + decerr_i_reg => decerr_i_reg, + interr_i_reg => interr_i_reg, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + p_58_out => p_58_out, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_init_reg => sig_init_reg, + sig_init_reg2 => sig_init_reg2, + sig_rd_sts_slverr_reg_reg => sig_rd_sts_slverr_reg_reg, + sig_rd_sts_slverr_reg_reg_0(2 downto 0) => sig_rd_sts_slverr_reg_reg_0(2 downto 0), + sig_rsc2stat_status_valid => sig_rsc2stat_status_valid, + slverr_i_reg => slverr_i_reg, + sts_tready_reg => sts_tready_reg + ); +I_CMD_FIFO: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo_22 + port map ( + E(0) => E(0), + Q(0) => Q(0), + SR(0) => SR(0), + cmnd_wr => cmnd_wr, + \in\(0) => \in\(0), + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + mm2s_halt => mm2s_halt, + \out\(49 downto 0) => \out\(49 downto 0), + p_56_out => p_56_out, + \s_axis_cmd_tdata_reg[63]\(48 downto 0) => \s_axis_cmd_tdata_reg[63]\(48 downto 0), + sig_calc_error_pushed => sig_calc_error_pushed, + sig_calc_error_pushed_reg => sig_calc_error_pushed_reg, + sig_calc_error_reg_reg => sig_calc_error_reg_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_init_reg => sig_init_reg, + sig_init_reg2 => sig_init_reg2, + sig_input_reg_empty => sig_input_reg_empty, + sig_sm_halt_reg => sig_sm_halt_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_axi_datamover_cmd_status__parameterized0\ is + port ( + sig_init_done : out STD_LOGIC; + sig_init_done_0 : out STD_LOGIC; + sig_calc_error_reg_reg : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 0 to 0 ); + p_9_out : out STD_LOGIC; + FIFO_Full_reg : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axis_cmd_tvalid_reg : out STD_LOGIC_VECTOR ( 0 to 0 ); + CO : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg\ : out STD_LOGIC; + decerr_i_reg : out STD_LOGIC; + slverr_i_reg : out STD_LOGIC; + interr_i_reg : out STD_LOGIC; + sig_dqual_reg_empty_reg : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 49 downto 0 ); + \GEN_STS_GRTR_THAN_8.ovrflo_err_reg\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_init_reg_reg : in STD_LOGIC; + sig_init_reg_reg_0 : in STD_LOGIC; + sig_psm_halt : in STD_LOGIC; + sig_input_reg_empty : in STD_LOGIC; + p_10_out : in STD_LOGIC; + s2mm_halt : in STD_LOGIC; + s2mm_soft_reset : in STD_LOGIC; + dma_err : in STD_LOGIC; + cmnd_wr_1 : in STD_LOGIC; + \hsize_vid_reg[15]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + \hsize_vid_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + S : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_wsc2stat_status_valid : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + s_axis_s2mm_cmd_tvalid : in STD_LOGIC; + m_axis_s2mm_sts_tready : in STD_LOGIC; + \s_axis_cmd_tdata_reg[63]\ : in STD_LOGIC_VECTOR ( 48 downto 0 ); + \in\ : in STD_LOGIC_VECTOR ( 16 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_cmd_status__parameterized0\ : entity is "axi_datamover_cmd_status"; +end \Arty_Z7_20_axi_vdma_0_0_axi_datamover_cmd_status__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_cmd_status__parameterized0\ is +begin +\GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO\: entity work.\Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized4\ + port map ( + CO(0) => CO(0), + \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg\ => \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg\, + \GEN_STS_GRTR_THAN_8.ovrflo_err_reg\(0) => \GEN_STS_GRTR_THAN_8.ovrflo_err_reg\(0), + Q(0) => FIFO_Full_reg(0), + S(0) => S(0), + decerr_i_reg => decerr_i_reg, + dma_err => dma_err, + \hsize_vid_reg[15]\(12 downto 0) => \hsize_vid_reg[15]\(12 downto 0), + \hsize_vid_reg[2]\(0) => \hsize_vid_reg[2]\(0), + \in\(16 downto 0) => \in\(16 downto 0), + interr_i_reg => interr_i_reg, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready, + p_9_out => p_9_out, + s2mm_halt => s2mm_halt, + s2mm_soft_reset => s2mm_soft_reset, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_dqual_reg_empty_reg => sig_dqual_reg_empty_reg, + sig_init_done_0 => sig_init_done_0, + sig_init_reg_reg => sig_init_reg_reg_0, + sig_stream_rst => sig_stream_rst, + sig_wsc2stat_status_valid => sig_wsc2stat_status_valid, + slverr_i_reg => slverr_i_reg + ); +I_CMD_FIFO: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo + port map ( + Q(0) => Q(0), + cmnd_wr_1 => cmnd_wr_1, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\(49 downto 0) => \out\(49 downto 0), + p_10_out => p_10_out, + s2mm_halt => s2mm_halt, + \s_axis_cmd_tdata_reg[63]\(48 downto 0) => \s_axis_cmd_tdata_reg[63]\(48 downto 0), + s_axis_cmd_tvalid_reg(0) => s_axis_cmd_tvalid_reg(0), + s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid, + sig_calc_error_reg_reg => sig_calc_error_reg_reg, + sig_init_done => sig_init_done, + sig_init_reg_reg => sig_init_reg_reg, + sig_input_reg_empty => sig_input_reg_empty, + sig_psm_halt => sig_psm_halt, + sig_stream_rst => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_rddata_cntl is + port ( + sig_next_calc_error_reg : out STD_LOGIC; + \sig_addr_posted_cntr_reg[2]_0\ : out STD_LOGIC; + sig_data2addr_stop_req : out STD_LOGIC; + sig_halt_reg_dly3 : out STD_LOGIC; + sig_data2rsc_decerr : out STD_LOGIC; + sig_addr_posted_cntr : out STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_rd_sts_reg_full0 : out STD_LOGIC; + sig_rd_sts_reg_empty_reg : out STD_LOGIC; + sig_rd_sts_interr_reg0 : out STD_LOGIC; + sig_rd_sts_slverr_reg0 : out STD_LOGIC; + sig_wr_fifo : out STD_LOGIC; + DIBDI : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \count_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + ram_full_i_reg : out STD_LOGIC; + m_axi_mm2s_rready : out STD_LOGIC; + sig_push_rd_sts_reg : out STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + m_axi_mm2s_rlast : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_rsc2data_ready : in STD_LOGIC; + sig_rd_sts_slverr_reg_reg : in STD_LOGIC_VECTOR ( 1 downto 0 ); + sig_mstr2data_cmd_valid : in STD_LOGIC; + sig_rsc2stat_status_valid : in STD_LOGIC; + FIFO_Full_reg : in STD_LOGIC; + sig_inhibit_rdy_n : in STD_LOGIC; + ram_empty_fb_i_reg : in STD_LOGIC; + m_axi_mm2s_rvalid : in STD_LOGIC; + ram_full_i_reg_0 : in STD_LOGIC; + \out\ : in STD_LOGIC; + m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \in\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + sig_init_reg2 : in STD_LOGIC; + sig_init_reg : in STD_LOGIC; + sig_rst2all_stop_request : in STD_LOGIC; + sig_posted_to_axi_reg : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_rddata_cntl : entity is "axi_datamover_rddata_cntl"; +end Arty_Z7_20_axi_vdma_0_0_axi_datamover_rddata_cntl; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_rddata_cntl is + signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_8_n_0\ : STD_LOGIC; + signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_0\ : STD_LOGIC; + signal \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_1\ : STD_LOGIC; + signal \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_10\ : STD_LOGIC; + signal \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_16\ : STD_LOGIC; + signal \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_17\ : STD_LOGIC; + signal \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_18\ : STD_LOGIC; + signal \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_2\ : STD_LOGIC; + signal \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_9\ : STD_LOGIC; + signal m_axi_mm2s_rready_INST_0_i_1_n_0 : STD_LOGIC; + signal p_0_in : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal ram_full_fb_i_i_4_n_0 : STD_LOGIC; + signal \^sig_addr_posted_cntr\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \sig_addr_posted_cntr[0]_i_1_n_0\ : STD_LOGIC; + signal \sig_addr_posted_cntr[1]_i_1_n_0\ : STD_LOGIC; + signal \sig_addr_posted_cntr[2]_i_1_n_0\ : STD_LOGIC; + signal \^sig_addr_posted_cntr_reg[2]_0\ : STD_LOGIC; + signal sig_cmd_cmplt_last_dbeat : STD_LOGIC; + signal sig_cmd_fifo_data_out : STD_LOGIC_VECTOR ( 35 downto 32 ); + signal sig_coelsc_decerr_reg0 : STD_LOGIC; + signal sig_coelsc_interr_reg0 : STD_LOGIC; + signal sig_coelsc_reg_full_i_1_n_0 : STD_LOGIC; + signal sig_coelsc_slverr_reg0 : STD_LOGIC; + signal \^sig_data2addr_stop_req\ : STD_LOGIC; + signal sig_data2rsc_calc_err : STD_LOGIC; + signal \^sig_data2rsc_decerr\ : STD_LOGIC; + signal sig_data2rsc_slverr : STD_LOGIC; + signal sig_data2rsc_valid : STD_LOGIC; + signal \sig_dbeat_cntr[7]_i_3_n_0\ : STD_LOGIC; + signal \sig_dbeat_cntr[7]_i_4_n_0\ : STD_LOGIC; + signal \sig_dbeat_cntr_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal sig_dqual_reg_empty : STD_LOGIC; + signal sig_dqual_reg_full : STD_LOGIC; + signal sig_halt_reg_dly1 : STD_LOGIC; + signal sig_halt_reg_dly2 : STD_LOGIC; + signal sig_halt_reg_i_1_n_0 : STD_LOGIC; + signal sig_last_dbeat : STD_LOGIC; + signal sig_last_dbeat_i_2_n_0 : STD_LOGIC; + signal sig_last_mmap_dbeat : STD_LOGIC; + signal sig_ld_new_cmd_reg : STD_LOGIC; + signal sig_ld_new_cmd_reg_i_1_n_0 : STD_LOGIC; + signal \^sig_next_calc_error_reg\ : STD_LOGIC; + signal sig_next_cmd_cmplt_reg : STD_LOGIC; + signal sig_next_eof_reg : STD_LOGIC; + signal sig_next_sequential_reg : STD_LOGIC; + signal sig_push_coelsc_reg : STD_LOGIC; + signal sig_push_dqual_reg : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of m_axi_mm2s_rready_INST_0_i_1 : label is "soft_lutpair163"; + attribute SOFT_HLUTNM of ram_full_fb_i_i_4 : label is "soft_lutpair165"; + attribute SOFT_HLUTNM of \sig_addr_posted_cntr[0]_i_1\ : label is "soft_lutpair162"; + attribute SOFT_HLUTNM of \sig_addr_posted_cntr[1]_i_1\ : label is "soft_lutpair163"; + attribute SOFT_HLUTNM of \sig_addr_posted_cntr[2]_i_1\ : label is "soft_lutpair162"; + attribute SOFT_HLUTNM of sig_coelsc_decerr_reg_i_1 : label is "soft_lutpair164"; + attribute SOFT_HLUTNM of sig_coelsc_interr_reg_i_1 : label is "soft_lutpair167"; + attribute SOFT_HLUTNM of sig_coelsc_reg_full_i_3 : label is "soft_lutpair165"; + attribute SOFT_HLUTNM of sig_coelsc_slverr_reg_i_1 : label is "soft_lutpair164"; + attribute SOFT_HLUTNM of sig_rd_sts_interr_reg_i_1 : label is "soft_lutpair167"; + attribute SOFT_HLUTNM of sig_rd_sts_reg_empty_i_1 : label is "soft_lutpair166"; + attribute SOFT_HLUTNM of sig_rd_sts_reg_full_i_3 : label is "soft_lutpair166"; +begin + E(0) <= \^e\(0); + sig_addr_posted_cntr(2 downto 0) <= \^sig_addr_posted_cntr\(2 downto 0); + \sig_addr_posted_cntr_reg[2]_0\ <= \^sig_addr_posted_cntr_reg[2]_0\; + sig_data2addr_stop_req <= \^sig_data2addr_stop_req\; + sig_data2rsc_decerr <= \^sig_data2rsc_decerr\; + sig_next_calc_error_reg <= \^sig_next_calc_error_reg\; +\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000F2" + ) + port map ( + I0 => m_axi_mm2s_rvalid, + I1 => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_18\, + I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_8_n_0\, + I3 => ram_full_i_reg_0, + I4 => \out\, + O => \^e\(0) + ); +\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF004000400040" + ) + port map ( + I0 => m_axi_mm2s_rready_INST_0_i_1_n_0, + I1 => \^sig_data2addr_stop_req\, + I2 => sig_dqual_reg_full, + I3 => \^sig_next_calc_error_reg\, + I4 => sig_next_cmd_cmplt_reg, + I5 => m_axi_mm2s_rlast, + O => DIBDI(1) + ); +\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF004000400040" + ) + port map ( + I0 => m_axi_mm2s_rready_INST_0_i_1_n_0, + I1 => \^sig_data2addr_stop_req\, + I2 => sig_dqual_reg_full, + I3 => \^sig_next_calc_error_reg\, + I4 => sig_next_eof_reg, + I5 => m_axi_mm2s_rlast, + O => DIBDI(0) + ); +\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_8\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4040404040404000" + ) + port map ( + I0 => \^sig_next_calc_error_reg\, + I1 => sig_dqual_reg_full, + I2 => \^sig_data2addr_stop_req\, + I3 => \^sig_addr_posted_cntr\(0), + I4 => \^sig_addr_posted_cntr\(2), + I5 => \^sig_addr_posted_cntr\(1), + O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_8_n_0\ + ); +\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO\: entity work.\Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized2\ + port map ( + D(7) => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_0\, + D(6) => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_1\, + D(5) => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_2\, + D(4 downto 0) => p_0_in(4 downto 0), + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_18\, + E(0) => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_17\, + FIFO_Full_reg => FIFO_Full_reg, + Q(7 downto 0) => \sig_dbeat_cntr_reg__0\(7 downto 0), + SR(0) => SR(0), + \in\(8 downto 0) => \in\(8 downto 0), + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axi_mm2s_rlast => m_axi_mm2s_rlast, + m_axi_mm2s_rvalid => m_axi_mm2s_rvalid, + \out\(3 downto 0) => sig_cmd_fifo_data_out(35 downto 32), + ram_full_i_reg => ram_full_i_reg_0, + sel => sig_wr_fifo, + \sig_addr_posted_cntr_reg[0]\ => \^sig_addr_posted_cntr\(0), + \sig_addr_posted_cntr_reg[1]\ => \^sig_addr_posted_cntr\(1), + \sig_addr_posted_cntr_reg[2]\ => \^sig_addr_posted_cntr\(2), + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_data2rsc_valid => sig_data2rsc_valid, + \sig_dbeat_cntr_reg[0]\ => \sig_dbeat_cntr[7]_i_3_n_0\, + \sig_dbeat_cntr_reg[3]\ => sig_last_dbeat_i_2_n_0, + \sig_dbeat_cntr_reg[5]\ => \sig_dbeat_cntr[7]_i_4_n_0\, + sig_dqual_reg_empty => sig_dqual_reg_empty, + sig_dqual_reg_empty_reg => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_10\, + sig_dqual_reg_full => sig_dqual_reg_full, + sig_halt_reg_reg => \^sig_data2addr_stop_req\, + sig_inhibit_rdy_n => sig_inhibit_rdy_n, + sig_init_reg => sig_init_reg, + sig_init_reg2 => sig_init_reg2, + sig_last_dbeat => sig_last_dbeat, + sig_last_dbeat_reg => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_16\, + sig_mstr2data_cmd_valid => sig_mstr2data_cmd_valid, + sig_next_calc_error_reg_reg => \^sig_next_calc_error_reg\, + sig_next_cmd_cmplt_reg_reg => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_9\, + sig_next_sequential_reg => sig_next_sequential_reg, + sig_push_dqual_reg => sig_push_dqual_reg, + sig_rsc2stat_status_valid => sig_rsc2stat_status_valid + ); +\count[7]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^e\(0), + I1 => ram_empty_fb_i_reg, + O => \count_reg[0]\(0) + ); +m_axi_mm2s_rready_INST_0: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000D00" + ) + port map ( + I0 => ram_full_i_reg_0, + I1 => \^sig_data2addr_stop_req\, + I2 => sig_data2rsc_valid, + I3 => sig_dqual_reg_full, + I4 => \^sig_next_calc_error_reg\, + I5 => m_axi_mm2s_rready_INST_0_i_1_n_0, + O => m_axi_mm2s_rready + ); +m_axi_mm2s_rready_INST_0_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"01" + ) + port map ( + I0 => \^sig_addr_posted_cntr\(1), + I1 => \^sig_addr_posted_cntr\(2), + I2 => \^sig_addr_posted_cntr\(0), + O => m_axi_mm2s_rready_INST_0_i_1_n_0 + ); +ram_full_fb_i_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"0010001100100010" + ) + port map ( + I0 => ram_full_i_reg_0, + I1 => ram_full_fb_i_i_4_n_0, + I2 => \^sig_data2addr_stop_req\, + I3 => m_axi_mm2s_rready_INST_0_i_1_n_0, + I4 => sig_data2rsc_valid, + I5 => m_axi_mm2s_rvalid, + O => ram_full_i_reg + ); +ram_full_fb_i_i_4: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^sig_next_calc_error_reg\, + I1 => sig_dqual_reg_full, + O => ram_full_fb_i_i_4_n_0 + ); +\sig_addr_posted_cntr[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B9996662" + ) + port map ( + I0 => sig_posted_to_axi_reg, + I1 => \^sig_addr_posted_cntr_reg[2]_0\, + I2 => \^sig_addr_posted_cntr\(2), + I3 => \^sig_addr_posted_cntr\(1), + I4 => \^sig_addr_posted_cntr\(0), + O => \sig_addr_posted_cntr[0]_i_1_n_0\ + ); +\sig_addr_posted_cntr[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AADAA4AA" + ) + port map ( + I0 => \^sig_addr_posted_cntr\(1), + I1 => \^sig_addr_posted_cntr\(2), + I2 => \^sig_addr_posted_cntr\(0), + I3 => \^sig_addr_posted_cntr_reg[2]_0\, + I4 => sig_posted_to_axi_reg, + O => \sig_addr_posted_cntr[1]_i_1_n_0\ + ); +\sig_addr_posted_cntr[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"CCECC8CC" + ) + port map ( + I0 => \^sig_addr_posted_cntr\(1), + I1 => \^sig_addr_posted_cntr\(2), + I2 => \^sig_addr_posted_cntr\(0), + I3 => \^sig_addr_posted_cntr_reg[2]_0\, + I4 => sig_posted_to_axi_reg, + O => \sig_addr_posted_cntr[2]_i_1_n_0\ + ); +\sig_addr_posted_cntr_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \sig_addr_posted_cntr[0]_i_1_n_0\, + Q => \^sig_addr_posted_cntr\(0), + R => SR(0) + ); +\sig_addr_posted_cntr_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \sig_addr_posted_cntr[1]_i_1_n_0\, + Q => \^sig_addr_posted_cntr\(1), + R => SR(0) + ); +\sig_addr_posted_cntr_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \sig_addr_posted_cntr[2]_i_1_n_0\, + Q => \^sig_addr_posted_cntr\(2), + R => SR(0) + ); +sig_coelsc_decerr_reg_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"EAAA" + ) + port map ( + I0 => \^sig_data2rsc_decerr\, + I1 => m_axi_mm2s_rvalid, + I2 => m_axi_mm2s_rresp(1), + I3 => m_axi_mm2s_rresp(0), + O => sig_coelsc_decerr_reg0 + ); +sig_coelsc_decerr_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_coelsc_reg, + D => sig_coelsc_decerr_reg0, + Q => \^sig_data2rsc_decerr\, + R => sig_coelsc_reg_full_i_1_n_0 + ); +sig_coelsc_interr_reg_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => sig_data2rsc_calc_err, + I1 => \^sig_next_calc_error_reg\, + O => sig_coelsc_interr_reg0 + ); +sig_coelsc_interr_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_coelsc_reg, + D => sig_coelsc_interr_reg0, + Q => sig_data2rsc_calc_err, + R => sig_coelsc_reg_full_i_1_n_0 + ); +sig_coelsc_reg_full_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"7000FFFF" + ) + port map ( + I0 => sig_ld_new_cmd_reg, + I1 => \^sig_next_calc_error_reg\, + I2 => sig_data2rsc_valid, + I3 => sig_rsc2data_ready, + I4 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + O => sig_coelsc_reg_full_i_1_n_0 + ); +sig_coelsc_reg_full_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"EA" + ) + port map ( + I0 => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_10\, + I1 => \^sig_next_calc_error_reg\, + I2 => sig_ld_new_cmd_reg, + O => sig_push_coelsc_reg + ); +sig_coelsc_reg_full_i_3: unisim.vcomponents.LUT3 + generic map( + INIT => X"EA" + ) + port map ( + I0 => \^sig_next_calc_error_reg\, + I1 => sig_next_cmd_cmplt_reg, + I2 => m_axi_mm2s_rlast, + O => sig_cmd_cmplt_last_dbeat + ); +sig_coelsc_reg_full_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_coelsc_reg, + D => sig_cmd_cmplt_last_dbeat, + Q => sig_data2rsc_valid, + R => sig_coelsc_reg_full_i_1_n_0 + ); +sig_coelsc_slverr_reg_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAEA" + ) + port map ( + I0 => sig_data2rsc_slverr, + I1 => m_axi_mm2s_rvalid, + I2 => m_axi_mm2s_rresp(1), + I3 => m_axi_mm2s_rresp(0), + O => sig_coelsc_slverr_reg0 + ); +sig_coelsc_slverr_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_coelsc_reg, + D => sig_coelsc_slverr_reg0, + Q => sig_data2rsc_slverr, + R => sig_coelsc_reg_full_i_1_n_0 + ); +\sig_dbeat_cntr[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => \sig_dbeat_cntr_reg__0\(0), + I1 => \sig_dbeat_cntr_reg__0\(1), + I2 => \sig_dbeat_cntr_reg__0\(3), + I3 => \sig_dbeat_cntr_reg__0\(2), + O => \sig_dbeat_cntr[7]_i_3_n_0\ + ); +\sig_dbeat_cntr[7]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \sig_dbeat_cntr_reg__0\(5), + I1 => \sig_dbeat_cntr_reg__0\(4), + I2 => \sig_dbeat_cntr_reg__0\(7), + I3 => \sig_dbeat_cntr_reg__0\(6), + O => \sig_dbeat_cntr[7]_i_4_n_0\ + ); +\sig_dbeat_cntr_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_17\, + D => p_0_in(0), + Q => \sig_dbeat_cntr_reg__0\(0), + R => SR(0) + ); +\sig_dbeat_cntr_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_17\, + D => p_0_in(1), + Q => \sig_dbeat_cntr_reg__0\(1), + R => SR(0) + ); +\sig_dbeat_cntr_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_17\, + D => p_0_in(2), + Q => \sig_dbeat_cntr_reg__0\(2), + R => SR(0) + ); +\sig_dbeat_cntr_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_17\, + D => p_0_in(3), + Q => \sig_dbeat_cntr_reg__0\(3), + R => SR(0) + ); +\sig_dbeat_cntr_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_17\, + D => p_0_in(4), + Q => \sig_dbeat_cntr_reg__0\(4), + R => SR(0) + ); +\sig_dbeat_cntr_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_17\, + D => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_2\, + Q => \sig_dbeat_cntr_reg__0\(5), + R => SR(0) + ); +\sig_dbeat_cntr_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_17\, + D => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_1\, + Q => \sig_dbeat_cntr_reg__0\(6), + R => SR(0) + ); +\sig_dbeat_cntr_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_17\, + D => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_0\, + Q => \sig_dbeat_cntr_reg__0\(7), + R => SR(0) + ); +sig_dqual_reg_empty_reg: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_dqual_reg, + D => '0', + Q => sig_dqual_reg_empty, + S => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_9\ + ); +sig_dqual_reg_full_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_dqual_reg, + D => sig_push_dqual_reg, + Q => sig_dqual_reg_full, + R => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_9\ + ); +sig_halt_reg_dly1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \^sig_data2addr_stop_req\, + Q => sig_halt_reg_dly1, + R => SR(0) + ); +sig_halt_reg_dly2_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => sig_halt_reg_dly1, + Q => sig_halt_reg_dly2, + R => SR(0) + ); +sig_halt_reg_dly3_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => sig_halt_reg_dly2, + Q => sig_halt_reg_dly3, + R => SR(0) + ); +sig_halt_reg_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => sig_rst2all_stop_request, + I1 => \^sig_data2addr_stop_req\, + O => sig_halt_reg_i_1_n_0 + ); +sig_halt_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => sig_halt_reg_i_1_n_0, + Q => \^sig_data2addr_stop_req\, + R => SR(0) + ); +sig_last_dbeat_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFDFF" + ) + port map ( + I0 => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_10\, + I1 => \sig_dbeat_cntr_reg__0\(3), + I2 => \sig_dbeat_cntr_reg__0\(2), + I3 => \sig_dbeat_cntr_reg__0\(0), + I4 => \sig_dbeat_cntr_reg__0\(1), + I5 => \sig_dbeat_cntr[7]_i_4_n_0\, + O => sig_last_dbeat_i_2_n_0 + ); +sig_last_dbeat_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_17\, + D => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_16\, + Q => sig_last_dbeat, + R => SR(0) + ); +sig_last_mmap_dbeat_reg_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_axi_mm2s_rlast, + I1 => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_10\, + O => sig_last_mmap_dbeat + ); +sig_last_mmap_dbeat_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => sig_last_mmap_dbeat, + Q => \^sig_addr_posted_cntr_reg[2]_0\, + R => SR(0) + ); +sig_ld_new_cmd_reg_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => sig_push_dqual_reg, + I1 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I2 => sig_ld_new_cmd_reg, + O => sig_ld_new_cmd_reg_i_1_n_0 + ); +sig_ld_new_cmd_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => sig_ld_new_cmd_reg_i_1_n_0, + Q => sig_ld_new_cmd_reg, + R => '0' + ); +sig_next_calc_error_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_dqual_reg, + D => sig_cmd_fifo_data_out(35), + Q => \^sig_next_calc_error_reg\, + R => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_9\ + ); +sig_next_cmd_cmplt_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_dqual_reg, + D => sig_cmd_fifo_data_out(34), + Q => sig_next_cmd_cmplt_reg, + R => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_9\ + ); +sig_next_eof_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_dqual_reg, + D => sig_cmd_fifo_data_out(32), + Q => sig_next_eof_reg, + R => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_9\ + ); +sig_next_sequential_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => sig_push_dqual_reg, + D => sig_cmd_fifo_data_out(33), + Q => sig_next_sequential_reg, + R => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_9\ + ); +sig_rd_sts_interr_reg_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => sig_data2rsc_calc_err, + I1 => sig_rd_sts_slverr_reg_reg(0), + O => sig_rd_sts_interr_reg0 + ); +sig_rd_sts_reg_empty_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => sig_data2rsc_valid, + I1 => sig_data2rsc_calc_err, + O => sig_rd_sts_reg_empty_reg + ); +sig_rd_sts_reg_full_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => sig_data2rsc_valid, + I1 => sig_rsc2data_ready, + O => sig_push_rd_sts_reg + ); +sig_rd_sts_reg_full_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => sig_data2rsc_calc_err, + I1 => sig_data2rsc_valid, + O => sig_rd_sts_reg_full0 + ); +sig_rd_sts_slverr_reg_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => sig_data2rsc_slverr, + I1 => sig_rd_sts_slverr_reg_reg(1), + O => sig_rd_sts_slverr_reg0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_s2mm_scatter is + port ( + \sig_data_skid_reg_reg[7]\ : out STD_LOGIC; + sig_dre2ibtt_tstrb : out STD_LOGIC; + p_7_out : out STD_LOGIC; + \INCLUDE_PACKING.lsig_first_dbeat_reg\ : out STD_LOGIC; + \sig_byte_cntr_reg[0]\ : out STD_LOGIC; + sig_dre2ibtt_tlast : out STD_LOGIC; + RD_EN : out STD_LOGIC; + \sig_good_tlast_dbeat37_out__0\ : out STD_LOGIC; + sig_dre2ibtt_eop_reg_reg : out STD_LOGIC; + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + \sig_byte_cntr_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \FSM_sequential_sig_cmdcntl_sm_state_reg[0]\ : out STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\ : out STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0]\ : out STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg\ : out STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_s2mm_aclk : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 16 downto 0 ); + sig_stream_rst : in STD_LOGIC; + \INCLUDE_PACKING.lsig_first_dbeat_reg_0\ : in STD_LOGIC; + sig_sm_ld_dre_cmd : in STD_LOGIC; + DOUT : in STD_LOGIC_VECTOR ( 8 downto 0 ); + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + EMPTY : in STD_LOGIC; + sig_ibtt2dre_tready : in STD_LOGIC; + sig_clr_dbc_reg : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + sig_init_reg : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0\ : in STD_LOGIC; + p_0_in : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0\ : in STD_LOGIC; + lsig_cmd_fetch_pause : in STD_LOGIC; + sig_need_cmd_flush : in STD_LOGIC; + sig_sm_pop_cmd_fifo : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_s2mm_scatter : entity is "axi_datamover_s2mm_scatter"; +end Arty_Z7_20_axi_vdma_0_0_axi_datamover_s2mm_scatter; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_s2mm_scatter is + signal \GEN_INDET_BTT.lsig_absorb2tlast_i_1_n_0\ : STD_LOGIC; + signal I_TSTRB_FIFO_n_0 : STD_LOGIC; + signal I_TSTRB_FIFO_n_1 : STD_LOGIC; + signal I_TSTRB_FIFO_n_11 : STD_LOGIC; + signal I_TSTRB_FIFO_n_5 : STD_LOGIC; + signal I_TSTRB_FIFO_n_6 : STD_LOGIC; + signal I_TSTRB_FIFO_n_8 : STD_LOGIC; + signal I_TSTRB_FIFO_n_9 : STD_LOGIC; + signal SLICE_INSERTION_n_1 : STD_LOGIC; + signal SLICE_INSERTION_n_10 : STD_LOGIC; + signal SLICE_INSERTION_n_11 : STD_LOGIC; + signal SLICE_INSERTION_n_12 : STD_LOGIC; + signal SLICE_INSERTION_n_13 : STD_LOGIC; + signal SLICE_INSERTION_n_2 : STD_LOGIC; + signal SLICE_INSERTION_n_3 : STD_LOGIC; + signal SLICE_INSERTION_n_5 : STD_LOGIC; + signal SLICE_INSERTION_n_6 : STD_LOGIC; + signal SLICE_INSERTION_n_7 : STD_LOGIC; + signal SLICE_INSERTION_n_8 : STD_LOGIC; + signal SLICE_INSERTION_n_9 : STD_LOGIC; + signal ld_btt_cntr_reg1 : STD_LOGIC; + signal ld_btt_cntr_reg2 : STD_LOGIC; + signal ld_btt_cntr_reg3 : STD_LOGIC; + signal lsig_absorb2tlast : STD_LOGIC; + signal p_1_in2_in : STD_LOGIC; + signal \^p_7_out\ : STD_LOGIC; + signal sel0 : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal sig_btt_cntr : STD_LOGIC_VECTOR ( 0 to 0 ); + signal sig_btt_cntr03_out : STD_LOGIC; + signal sig_btt_cntr_dup : STD_LOGIC_VECTOR ( 15 downto 0 ); + attribute RTL_KEEP : string; + attribute RTL_KEEP of sig_btt_cntr_dup : signal is "true"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of sig_btt_cntr_dup : signal is "no"; + signal sig_btt_cntr_prv0 : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \sig_btt_cntr_prv0_carry__0_i_1_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_prv0_carry__0_i_2_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_prv0_carry__0_i_3_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_prv0_carry__0_i_4_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_prv0_carry__0_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_prv0_carry__0_n_1\ : STD_LOGIC; + signal \sig_btt_cntr_prv0_carry__0_n_2\ : STD_LOGIC; + signal \sig_btt_cntr_prv0_carry__0_n_3\ : STD_LOGIC; + signal \sig_btt_cntr_prv0_carry__1_i_1_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_prv0_carry__1_i_2_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_prv0_carry__1_i_3_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_prv0_carry__1_i_4_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_prv0_carry__1_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_prv0_carry__1_n_1\ : STD_LOGIC; + signal \sig_btt_cntr_prv0_carry__1_n_2\ : STD_LOGIC; + signal \sig_btt_cntr_prv0_carry__1_n_3\ : STD_LOGIC; + signal \sig_btt_cntr_prv0_carry__2_i_1_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_prv0_carry__2_i_2_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_prv0_carry__2_i_3_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_prv0_carry__2_i_4_n_0\ : STD_LOGIC; + signal \sig_btt_cntr_prv0_carry__2_n_1\ : STD_LOGIC; + signal \sig_btt_cntr_prv0_carry__2_n_2\ : STD_LOGIC; + signal \sig_btt_cntr_prv0_carry__2_n_3\ : STD_LOGIC; + signal sig_btt_cntr_prv0_carry_i_1_n_0 : STD_LOGIC; + signal sig_btt_cntr_prv0_carry_i_2_n_0 : STD_LOGIC; + signal sig_btt_cntr_prv0_carry_i_3_n_0 : STD_LOGIC; + signal sig_btt_cntr_prv0_carry_i_4_n_0 : STD_LOGIC; + signal sig_btt_cntr_prv0_carry_n_0 : STD_LOGIC; + signal sig_btt_cntr_prv0_carry_n_1 : STD_LOGIC; + signal sig_btt_cntr_prv0_carry_n_2 : STD_LOGIC; + signal sig_btt_cntr_prv0_carry_n_3 : STD_LOGIC; + signal \sig_btt_cntr_reg_n_0_[10]\ : STD_LOGIC; + signal \sig_btt_cntr_reg_n_0_[11]\ : STD_LOGIC; + signal \sig_btt_cntr_reg_n_0_[12]\ : STD_LOGIC; + signal \sig_btt_cntr_reg_n_0_[13]\ : STD_LOGIC; + signal \sig_btt_cntr_reg_n_0_[14]\ : STD_LOGIC; + signal \sig_btt_cntr_reg_n_0_[15]\ : STD_LOGIC; + signal \sig_btt_cntr_reg_n_0_[1]\ : STD_LOGIC; + signal \sig_btt_cntr_reg_n_0_[2]\ : STD_LOGIC; + signal \sig_btt_cntr_reg_n_0_[3]\ : STD_LOGIC; + signal \sig_btt_cntr_reg_n_0_[4]\ : STD_LOGIC; + signal \sig_btt_cntr_reg_n_0_[5]\ : STD_LOGIC; + signal \sig_btt_cntr_reg_n_0_[6]\ : STD_LOGIC; + signal \sig_btt_cntr_reg_n_0_[7]\ : STD_LOGIC; + signal \sig_btt_cntr_reg_n_0_[8]\ : STD_LOGIC; + signal \sig_btt_cntr_reg_n_0_[9]\ : STD_LOGIC; + signal sig_btt_eq_0 : STD_LOGIC; + signal sig_btt_eq_0_i_1_n_0 : STD_LOGIC; + signal sig_btt_eq_0_i_2_n_0 : STD_LOGIC; + signal sig_btt_eq_0_i_3_n_0 : STD_LOGIC; + signal sig_btt_eq_0_i_4_n_0 : STD_LOGIC; + signal sig_btt_eq_0_i_5_n_0 : STD_LOGIC; + signal sig_btt_eq_0_i_6_n_0 : STD_LOGIC; + signal sig_btt_lteq_max_first_incr : STD_LOGIC; + signal \sig_btt_lteq_max_first_incr0_carry__0_n_1\ : STD_LOGIC; + signal \sig_btt_lteq_max_first_incr0_carry__0_n_2\ : STD_LOGIC; + signal \sig_btt_lteq_max_first_incr0_carry__0_n_3\ : STD_LOGIC; + signal sig_btt_lteq_max_first_incr0_carry_n_0 : STD_LOGIC; + signal sig_btt_lteq_max_first_incr0_carry_n_1 : STD_LOGIC; + signal sig_btt_lteq_max_first_incr0_carry_n_2 : STD_LOGIC; + signal sig_btt_lteq_max_first_incr0_carry_n_3 : STD_LOGIC; + signal \^sig_byte_cntr_reg[0]\ : STD_LOGIC; + signal sig_cmd_full : STD_LOGIC; + signal sig_curr_eof_reg : STD_LOGIC; + signal sig_curr_eof_reg_i_1_n_0 : STD_LOGIC; + signal \^sig_dre2ibtt_eop_reg_reg\ : STD_LOGIC; + signal sig_eop_halt_xfer : STD_LOGIC; + signal sig_eop_halt_xfer_i_1_n_0 : STD_LOGIC; + signal sig_eop_sent : STD_LOGIC; + signal sig_eop_sent_reg : STD_LOGIC; + signal sig_inhibit_rdy_n : STD_LOGIC; + signal \sig_max_first_increment[0]_i_1_n_0\ : STD_LOGIC; + signal \sig_max_first_increment_reg_n_0_[0]\ : STD_LOGIC; + signal sig_rd_empty : STD_LOGIC; + signal sig_strm_tlast : STD_LOGIC; + signal sig_strm_tvalid : STD_LOGIC; + signal sig_tstrb_fifo_data_out : STD_LOGIC_VECTOR ( 2 to 2 ); + signal sig_valid_fifo_ld12_out : STD_LOGIC; + signal slice_insert_data : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal slice_insert_valid : STD_LOGIC; + signal \NLW_sig_btt_cntr_prv0_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal NLW_sig_btt_lteq_max_first_incr0_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_sig_btt_lteq_max_first_incr0_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute KEEP : string; + attribute KEEP of \sig_btt_cntr_dup_reg[0]\ : label is "yes"; + attribute equivalent_register_removal of \sig_btt_cntr_dup_reg[0]\ : label is "no"; + attribute KEEP of \sig_btt_cntr_dup_reg[10]\ : label is "yes"; + attribute equivalent_register_removal of \sig_btt_cntr_dup_reg[10]\ : label is "no"; + attribute KEEP of \sig_btt_cntr_dup_reg[11]\ : label is "yes"; + attribute equivalent_register_removal of \sig_btt_cntr_dup_reg[11]\ : label is "no"; + attribute KEEP of \sig_btt_cntr_dup_reg[12]\ : label is "yes"; + attribute equivalent_register_removal of \sig_btt_cntr_dup_reg[12]\ : label is "no"; + attribute KEEP of \sig_btt_cntr_dup_reg[13]\ : label is "yes"; + attribute equivalent_register_removal of \sig_btt_cntr_dup_reg[13]\ : label is "no"; + attribute KEEP of \sig_btt_cntr_dup_reg[14]\ : label is "yes"; + attribute equivalent_register_removal of \sig_btt_cntr_dup_reg[14]\ : label is "no"; + attribute KEEP of \sig_btt_cntr_dup_reg[15]\ : label is "yes"; + attribute equivalent_register_removal of \sig_btt_cntr_dup_reg[15]\ : label is "no"; + attribute KEEP of \sig_btt_cntr_dup_reg[1]\ : label is "yes"; + attribute equivalent_register_removal of \sig_btt_cntr_dup_reg[1]\ : label is "no"; + attribute KEEP of \sig_btt_cntr_dup_reg[2]\ : label is "yes"; + attribute equivalent_register_removal of \sig_btt_cntr_dup_reg[2]\ : label is "no"; + attribute KEEP of \sig_btt_cntr_dup_reg[3]\ : label is "yes"; + attribute equivalent_register_removal of \sig_btt_cntr_dup_reg[3]\ : label is "no"; + attribute KEEP of \sig_btt_cntr_dup_reg[4]\ : label is "yes"; + attribute equivalent_register_removal of \sig_btt_cntr_dup_reg[4]\ : label is "no"; + attribute KEEP of \sig_btt_cntr_dup_reg[5]\ : label is "yes"; + attribute equivalent_register_removal of \sig_btt_cntr_dup_reg[5]\ : label is "no"; + attribute KEEP of \sig_btt_cntr_dup_reg[6]\ : label is "yes"; + attribute equivalent_register_removal of \sig_btt_cntr_dup_reg[6]\ : label is "no"; + attribute KEEP of \sig_btt_cntr_dup_reg[7]\ : label is "yes"; + attribute equivalent_register_removal of \sig_btt_cntr_dup_reg[7]\ : label is "no"; + attribute KEEP of \sig_btt_cntr_dup_reg[8]\ : label is "yes"; + attribute equivalent_register_removal of \sig_btt_cntr_dup_reg[8]\ : label is "no"; + attribute KEEP of \sig_btt_cntr_dup_reg[9]\ : label is "yes"; + attribute equivalent_register_removal of \sig_btt_cntr_dup_reg[9]\ : label is "no"; + attribute equivalent_register_removal of \sig_btt_cntr_reg[0]\ : label is "no"; + attribute equivalent_register_removal of \sig_btt_cntr_reg[10]\ : label is "no"; + attribute equivalent_register_removal of \sig_btt_cntr_reg[11]\ : label is "no"; + attribute equivalent_register_removal of \sig_btt_cntr_reg[12]\ : label is "no"; + attribute equivalent_register_removal of \sig_btt_cntr_reg[13]\ : label is "no"; + attribute equivalent_register_removal of \sig_btt_cntr_reg[14]\ : label is "no"; + attribute equivalent_register_removal of \sig_btt_cntr_reg[15]\ : label is "no"; + attribute equivalent_register_removal of \sig_btt_cntr_reg[1]\ : label is "no"; + attribute equivalent_register_removal of \sig_btt_cntr_reg[2]\ : label is "no"; + attribute equivalent_register_removal of \sig_btt_cntr_reg[3]\ : label is "no"; + attribute equivalent_register_removal of \sig_btt_cntr_reg[4]\ : label is "no"; + attribute equivalent_register_removal of \sig_btt_cntr_reg[5]\ : label is "no"; + attribute equivalent_register_removal of \sig_btt_cntr_reg[6]\ : label is "no"; + attribute equivalent_register_removal of \sig_btt_cntr_reg[7]\ : label is "no"; + attribute equivalent_register_removal of \sig_btt_cntr_reg[8]\ : label is "no"; + attribute equivalent_register_removal of \sig_btt_cntr_reg[9]\ : label is "no"; +begin + p_7_out <= \^p_7_out\; + \sig_byte_cntr_reg[0]\ <= \^sig_byte_cntr_reg[0]\; + sig_dre2ibtt_eop_reg_reg <= \^sig_dre2ibtt_eop_reg_reg\; +\FSM_sequential_sig_cmdcntl_sm_state[0]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^p_7_out\, + I1 => Q(0), + O => \FSM_sequential_sig_cmdcntl_sm_state_reg[0]\ + ); +\GEN_INDET_BTT.lsig_absorb2tlast_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000F000F040F000" + ) + port map ( + I0 => sig_rd_empty, + I1 => sig_tstrb_fifo_data_out(2), + I2 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I3 => lsig_absorb2tlast, + I4 => sig_strm_tvalid, + I5 => sig_strm_tlast, + O => \GEN_INDET_BTT.lsig_absorb2tlast_i_1_n_0\ + ); +\GEN_INDET_BTT.lsig_absorb2tlast_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_INDET_BTT.lsig_absorb2tlast_i_1_n_0\, + Q => lsig_absorb2tlast, + R => '0' + ); +I_MSSAI_SKID_BUF: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover_mssai_skid_buf + port map ( + DOUT(8 downto 0) => DOUT(8 downto 0), + E(0) => I_TSTRB_FIFO_n_9, + EMPTY => EMPTY, + \GEN_INDET_BTT.lsig_absorb2tlast_reg\ => I_TSTRB_FIFO_n_11, + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][0]\ => sig_strm_tvalid, + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][0]_0\(0) => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7]\(7 downto 0) => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7]\(7 downto 0), + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0\, + \INFERRED_GEN.cnt_i_reg[4]\ => \^sig_byte_cntr_reg[0]\, + Q(0) => sig_rd_empty, + RD_EN => RD_EN, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\ => p_1_in2_in, + p_0_in => p_0_in, + \sig_byte_cntr_reg[3]\(0) => \sig_byte_cntr_reg[3]\(0), + sig_clr_dbc_reg => sig_clr_dbc_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + \sig_data_skid_reg_reg[7]_0\ => \sig_data_skid_reg_reg[7]\, + sig_dre2ibtt_eop_reg_reg => \^sig_dre2ibtt_eop_reg_reg\, + sig_dre2ibtt_tstrb => sig_dre2ibtt_tstrb, + sig_eop_halt_xfer => sig_eop_halt_xfer, + sig_init_reg => sig_init_reg, + sig_stream_rst => sig_stream_rst, + sig_strm_tlast => sig_strm_tlast + ); +I_TSTRB_FIFO: entity work.\Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized8\ + port map ( + E(0) => I_TSTRB_FIFO_n_9, + \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg\ => \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg\, + \GEN_INDET_BTT.lsig_absorb2tlast_reg\(0) => sig_tstrb_fifo_data_out(2), + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1]\(1 downto 0) => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1]\(1 downto 0), + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1]\(1), + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1]\(1), + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1]\(1), + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1]\(1), + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1]\(1), + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1]\(1), + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1]\(1), + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1]\(1), + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0]\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\(1 downto 0) => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\(1 downto 0), + \INCLUDE_PACKING.lsig_first_dbeat_reg\ => \INCLUDE_PACKING.lsig_first_dbeat_reg\, + \INCLUDE_PACKING.lsig_first_dbeat_reg_0\ => \INCLUDE_PACKING.lsig_first_dbeat_reg_0\, + \INFERRED_GEN.cnt_i_reg[1]\ => I_TSTRB_FIFO_n_0, + Q(0) => sig_rd_empty, + SR(0) => I_TSTRB_FIFO_n_8, + SS(0) => I_TSTRB_FIFO_n_1, + \in\(1 downto 0) => slice_insert_data(3 downto 2), + lsig_absorb2tlast => lsig_absorb2tlast, + lsig_cmd_fetch_pause => lsig_cmd_fetch_pause, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\ => p_1_in2_in, + p_0_in => p_0_in, + p_7_out => \^p_7_out\, + \sig_byte_cntr_reg[0]\ => \^sig_byte_cntr_reg[0]\, + \sig_byte_cntr_reg[7]\(0) => SR(0), + sig_clr_dbc_reg => sig_clr_dbc_reg, + sig_cmd_empty_reg => I_TSTRB_FIFO_n_6, + sig_cmd_full => sig_cmd_full, + sig_cmd_full_reg => I_TSTRB_FIFO_n_5, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_dre2ibtt_tlast => sig_dre2ibtt_tlast, + sig_eop_halt_xfer => sig_eop_halt_xfer, + sig_eop_sent => sig_eop_sent, + sig_eop_sent_reg => sig_eop_sent_reg, + \sig_good_tlast_dbeat37_out__0\ => \sig_good_tlast_dbeat37_out__0\, + sig_ibtt2dre_tready => sig_ibtt2dre_tready, + sig_inhibit_rdy_n => sig_inhibit_rdy_n, + sig_last_reg_out_reg => \^sig_dre2ibtt_eop_reg_reg\, + sig_m_valid_out_reg => sig_strm_tvalid, + sig_need_cmd_flush => sig_need_cmd_flush, + sig_s_ready_dup4_reg => I_TSTRB_FIFO_n_11, + sig_sm_ld_dre_cmd => sig_sm_ld_dre_cmd, + sig_sm_pop_cmd_fifo => sig_sm_pop_cmd_fifo, + sig_stream_rst => sig_stream_rst, + sig_strm_tlast => sig_strm_tlast, + slice_insert_valid => slice_insert_valid + ); +SLICE_INSERTION: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover_slice + port map ( + CO(0) => sig_btt_lteq_max_first_incr, + DI(0) => SLICE_INSERTION_n_9, + E(0) => sig_btt_cntr03_out, + FIFO_Full_reg => I_TSTRB_FIFO_n_0, + S(3) => SLICE_INSERTION_n_5, + S(2) => SLICE_INSERTION_n_6, + S(1) => SLICE_INSERTION_n_7, + S(0) => SLICE_INSERTION_n_8, + \in\(1 downto 0) => slice_insert_data(3 downto 2), + ld_btt_cntr_reg1 => ld_btt_cntr_reg1, + ld_btt_cntr_reg1_reg => SLICE_INSERTION_n_3, + ld_btt_cntr_reg2 => ld_btt_cntr_reg2, + ld_btt_cntr_reg2_reg => SLICE_INSERTION_n_2, + ld_btt_cntr_reg3 => ld_btt_cntr_reg3, + ld_btt_cntr_reg3_reg => SLICE_INSERTION_n_1, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\(15 downto 0) => sig_btt_cntr_dup(15 downto 0), + sig_btt_eq_0 => sig_btt_eq_0, + sig_cmd_full => sig_cmd_full, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_curr_eof_reg => sig_curr_eof_reg, + sig_eop_sent => sig_eop_sent, + sig_inhibit_rdy_n => sig_inhibit_rdy_n, + \sig_max_first_increment_reg[0]\ => \sig_max_first_increment_reg_n_0_[0]\, + sig_sm_ld_dre_cmd => sig_sm_ld_dre_cmd, + sig_stream_rst => sig_stream_rst, + sig_valid_fifo_ld12_out => sig_valid_fifo_ld12_out, + slice_insert_valid => slice_insert_valid, + \storage_data_reg[3]_0\(3) => SLICE_INSERTION_n_10, + \storage_data_reg[3]_0\(2) => SLICE_INSERTION_n_11, + \storage_data_reg[3]_0\(1) => SLICE_INSERTION_n_12, + \storage_data_reg[3]_0\(0) => SLICE_INSERTION_n_13 + ); +ld_btt_cntr_reg1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => SLICE_INSERTION_n_3, + Q => ld_btt_cntr_reg1, + R => '0' + ); +ld_btt_cntr_reg2_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => SLICE_INSERTION_n_2, + Q => ld_btt_cntr_reg2, + R => '0' + ); +ld_btt_cntr_reg3_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => SLICE_INSERTION_n_1, + Q => ld_btt_cntr_reg3, + R => '0' + ); +\sig_btt_cntr[0]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"CCAC" + ) + port map ( + I0 => \out\(0), + I1 => sig_btt_cntr_prv0(0), + I2 => sig_sm_ld_dre_cmd, + I3 => sig_cmd_full, + O => sel0(0) + ); +\sig_btt_cntr[10]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"CCAC" + ) + port map ( + I0 => \out\(10), + I1 => sig_btt_cntr_prv0(10), + I2 => sig_sm_ld_dre_cmd, + I3 => sig_cmd_full, + O => sel0(10) + ); +\sig_btt_cntr[11]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"CCAC" + ) + port map ( + I0 => \out\(11), + I1 => sig_btt_cntr_prv0(11), + I2 => sig_sm_ld_dre_cmd, + I3 => sig_cmd_full, + O => sel0(11) + ); +\sig_btt_cntr[12]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"CCAC" + ) + port map ( + I0 => \out\(12), + I1 => sig_btt_cntr_prv0(12), + I2 => sig_sm_ld_dre_cmd, + I3 => sig_cmd_full, + O => sel0(12) + ); +\sig_btt_cntr[13]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"CCAC" + ) + port map ( + I0 => \out\(13), + I1 => sig_btt_cntr_prv0(13), + I2 => sig_sm_ld_dre_cmd, + I3 => sig_cmd_full, + O => sel0(13) + ); +\sig_btt_cntr[14]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"CCAC" + ) + port map ( + I0 => \out\(14), + I1 => sig_btt_cntr_prv0(14), + I2 => sig_sm_ld_dre_cmd, + I3 => sig_cmd_full, + O => sel0(14) + ); +\sig_btt_cntr[15]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"CCAC" + ) + port map ( + I0 => \out\(15), + I1 => sig_btt_cntr_prv0(15), + I2 => sig_sm_ld_dre_cmd, + I3 => sig_cmd_full, + O => sel0(15) + ); +\sig_btt_cntr[1]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"CCAC" + ) + port map ( + I0 => \out\(1), + I1 => sig_btt_cntr_prv0(1), + I2 => sig_sm_ld_dre_cmd, + I3 => sig_cmd_full, + O => sel0(1) + ); +\sig_btt_cntr[2]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"CCAC" + ) + port map ( + I0 => \out\(2), + I1 => sig_btt_cntr_prv0(2), + I2 => sig_sm_ld_dre_cmd, + I3 => sig_cmd_full, + O => sel0(2) + ); +\sig_btt_cntr[3]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"CCAC" + ) + port map ( + I0 => \out\(3), + I1 => sig_btt_cntr_prv0(3), + I2 => sig_sm_ld_dre_cmd, + I3 => sig_cmd_full, + O => sel0(3) + ); +\sig_btt_cntr[4]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"CCAC" + ) + port map ( + I0 => \out\(4), + I1 => sig_btt_cntr_prv0(4), + I2 => sig_sm_ld_dre_cmd, + I3 => sig_cmd_full, + O => sel0(4) + ); +\sig_btt_cntr[5]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"CCAC" + ) + port map ( + I0 => \out\(5), + I1 => sig_btt_cntr_prv0(5), + I2 => sig_sm_ld_dre_cmd, + I3 => sig_cmd_full, + O => sel0(5) + ); +\sig_btt_cntr[6]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"CCAC" + ) + port map ( + I0 => \out\(6), + I1 => sig_btt_cntr_prv0(6), + I2 => sig_sm_ld_dre_cmd, + I3 => sig_cmd_full, + O => sel0(6) + ); +\sig_btt_cntr[7]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"CCAC" + ) + port map ( + I0 => \out\(7), + I1 => sig_btt_cntr_prv0(7), + I2 => sig_sm_ld_dre_cmd, + I3 => sig_cmd_full, + O => sel0(7) + ); +\sig_btt_cntr[8]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"CCAC" + ) + port map ( + I0 => \out\(8), + I1 => sig_btt_cntr_prv0(8), + I2 => sig_sm_ld_dre_cmd, + I3 => sig_cmd_full, + O => sel0(8) + ); +\sig_btt_cntr[9]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"CCAC" + ) + port map ( + I0 => \out\(9), + I1 => sig_btt_cntr_prv0(9), + I2 => sig_sm_ld_dre_cmd, + I3 => sig_cmd_full, + O => sel0(9) + ); +\sig_btt_cntr_dup_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(0), + Q => sig_btt_cntr_dup(0), + R => I_TSTRB_FIFO_n_8 + ); +\sig_btt_cntr_dup_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(10), + Q => sig_btt_cntr_dup(10), + R => I_TSTRB_FIFO_n_8 + ); +\sig_btt_cntr_dup_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(11), + Q => sig_btt_cntr_dup(11), + R => I_TSTRB_FIFO_n_8 + ); +\sig_btt_cntr_dup_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(12), + Q => sig_btt_cntr_dup(12), + R => I_TSTRB_FIFO_n_8 + ); +\sig_btt_cntr_dup_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(13), + Q => sig_btt_cntr_dup(13), + R => I_TSTRB_FIFO_n_8 + ); +\sig_btt_cntr_dup_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(14), + Q => sig_btt_cntr_dup(14), + R => I_TSTRB_FIFO_n_8 + ); +\sig_btt_cntr_dup_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(15), + Q => sig_btt_cntr_dup(15), + R => I_TSTRB_FIFO_n_8 + ); +\sig_btt_cntr_dup_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(1), + Q => sig_btt_cntr_dup(1), + R => I_TSTRB_FIFO_n_8 + ); +\sig_btt_cntr_dup_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(2), + Q => sig_btt_cntr_dup(2), + R => I_TSTRB_FIFO_n_8 + ); +\sig_btt_cntr_dup_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(3), + Q => sig_btt_cntr_dup(3), + R => I_TSTRB_FIFO_n_8 + ); +\sig_btt_cntr_dup_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(4), + Q => sig_btt_cntr_dup(4), + R => I_TSTRB_FIFO_n_8 + ); +\sig_btt_cntr_dup_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(5), + Q => sig_btt_cntr_dup(5), + R => I_TSTRB_FIFO_n_8 + ); +\sig_btt_cntr_dup_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(6), + Q => sig_btt_cntr_dup(6), + R => I_TSTRB_FIFO_n_8 + ); +\sig_btt_cntr_dup_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(7), + Q => sig_btt_cntr_dup(7), + R => I_TSTRB_FIFO_n_8 + ); +\sig_btt_cntr_dup_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(8), + Q => sig_btt_cntr_dup(8), + R => I_TSTRB_FIFO_n_8 + ); +\sig_btt_cntr_dup_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(9), + Q => sig_btt_cntr_dup(9), + R => I_TSTRB_FIFO_n_8 + ); +sig_btt_cntr_prv0_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => sig_btt_cntr_prv0_carry_n_0, + CO(2) => sig_btt_cntr_prv0_carry_n_1, + CO(1) => sig_btt_cntr_prv0_carry_n_2, + CO(0) => sig_btt_cntr_prv0_carry_n_3, + CYINIT => '1', + DI(3 downto 0) => sig_btt_cntr_dup(3 downto 0), + O(3 downto 0) => sig_btt_cntr_prv0(3 downto 0), + S(3) => sig_btt_cntr_prv0_carry_i_1_n_0, + S(2) => sig_btt_cntr_prv0_carry_i_2_n_0, + S(1) => sig_btt_cntr_prv0_carry_i_3_n_0, + S(0) => sig_btt_cntr_prv0_carry_i_4_n_0 + ); +\sig_btt_cntr_prv0_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => sig_btt_cntr_prv0_carry_n_0, + CO(3) => \sig_btt_cntr_prv0_carry__0_n_0\, + CO(2) => \sig_btt_cntr_prv0_carry__0_n_1\, + CO(1) => \sig_btt_cntr_prv0_carry__0_n_2\, + CO(0) => \sig_btt_cntr_prv0_carry__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => sig_btt_cntr_dup(7 downto 4), + O(3 downto 0) => sig_btt_cntr_prv0(7 downto 4), + S(3) => \sig_btt_cntr_prv0_carry__0_i_1_n_0\, + S(2) => \sig_btt_cntr_prv0_carry__0_i_2_n_0\, + S(1) => \sig_btt_cntr_prv0_carry__0_i_3_n_0\, + S(0) => \sig_btt_cntr_prv0_carry__0_i_4_n_0\ + ); +\sig_btt_cntr_prv0_carry__0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"95" + ) + port map ( + I0 => sig_btt_cntr_dup(7), + I1 => sig_btt_lteq_max_first_incr, + I2 => \sig_btt_cntr_reg_n_0_[7]\, + O => \sig_btt_cntr_prv0_carry__0_i_1_n_0\ + ); +\sig_btt_cntr_prv0_carry__0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"95" + ) + port map ( + I0 => sig_btt_cntr_dup(6), + I1 => sig_btt_lteq_max_first_incr, + I2 => \sig_btt_cntr_reg_n_0_[6]\, + O => \sig_btt_cntr_prv0_carry__0_i_2_n_0\ + ); +\sig_btt_cntr_prv0_carry__0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"95" + ) + port map ( + I0 => sig_btt_cntr_dup(5), + I1 => sig_btt_lteq_max_first_incr, + I2 => \sig_btt_cntr_reg_n_0_[5]\, + O => \sig_btt_cntr_prv0_carry__0_i_3_n_0\ + ); +\sig_btt_cntr_prv0_carry__0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"95" + ) + port map ( + I0 => sig_btt_cntr_dup(4), + I1 => sig_btt_lteq_max_first_incr, + I2 => \sig_btt_cntr_reg_n_0_[4]\, + O => \sig_btt_cntr_prv0_carry__0_i_4_n_0\ + ); +\sig_btt_cntr_prv0_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \sig_btt_cntr_prv0_carry__0_n_0\, + CO(3) => \sig_btt_cntr_prv0_carry__1_n_0\, + CO(2) => \sig_btt_cntr_prv0_carry__1_n_1\, + CO(1) => \sig_btt_cntr_prv0_carry__1_n_2\, + CO(0) => \sig_btt_cntr_prv0_carry__1_n_3\, + CYINIT => '0', + DI(3 downto 0) => sig_btt_cntr_dup(11 downto 8), + O(3 downto 0) => sig_btt_cntr_prv0(11 downto 8), + S(3) => \sig_btt_cntr_prv0_carry__1_i_1_n_0\, + S(2) => \sig_btt_cntr_prv0_carry__1_i_2_n_0\, + S(1) => \sig_btt_cntr_prv0_carry__1_i_3_n_0\, + S(0) => \sig_btt_cntr_prv0_carry__1_i_4_n_0\ + ); +\sig_btt_cntr_prv0_carry__1_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"95" + ) + port map ( + I0 => sig_btt_cntr_dup(11), + I1 => sig_btt_lteq_max_first_incr, + I2 => \sig_btt_cntr_reg_n_0_[11]\, + O => \sig_btt_cntr_prv0_carry__1_i_1_n_0\ + ); +\sig_btt_cntr_prv0_carry__1_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"95" + ) + port map ( + I0 => sig_btt_cntr_dup(10), + I1 => sig_btt_lteq_max_first_incr, + I2 => \sig_btt_cntr_reg_n_0_[10]\, + O => \sig_btt_cntr_prv0_carry__1_i_2_n_0\ + ); +\sig_btt_cntr_prv0_carry__1_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"95" + ) + port map ( + I0 => sig_btt_cntr_dup(9), + I1 => sig_btt_lteq_max_first_incr, + I2 => \sig_btt_cntr_reg_n_0_[9]\, + O => \sig_btt_cntr_prv0_carry__1_i_3_n_0\ + ); +\sig_btt_cntr_prv0_carry__1_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"95" + ) + port map ( + I0 => sig_btt_cntr_dup(8), + I1 => sig_btt_lteq_max_first_incr, + I2 => \sig_btt_cntr_reg_n_0_[8]\, + O => \sig_btt_cntr_prv0_carry__1_i_4_n_0\ + ); +\sig_btt_cntr_prv0_carry__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \sig_btt_cntr_prv0_carry__1_n_0\, + CO(3) => \NLW_sig_btt_cntr_prv0_carry__2_CO_UNCONNECTED\(3), + CO(2) => \sig_btt_cntr_prv0_carry__2_n_1\, + CO(1) => \sig_btt_cntr_prv0_carry__2_n_2\, + CO(0) => \sig_btt_cntr_prv0_carry__2_n_3\, + CYINIT => '0', + DI(3) => '0', + DI(2 downto 0) => sig_btt_cntr_dup(14 downto 12), + O(3 downto 0) => sig_btt_cntr_prv0(15 downto 12), + S(3) => \sig_btt_cntr_prv0_carry__2_i_1_n_0\, + S(2) => \sig_btt_cntr_prv0_carry__2_i_2_n_0\, + S(1) => \sig_btt_cntr_prv0_carry__2_i_3_n_0\, + S(0) => \sig_btt_cntr_prv0_carry__2_i_4_n_0\ + ); +\sig_btt_cntr_prv0_carry__2_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"95" + ) + port map ( + I0 => sig_btt_cntr_dup(15), + I1 => sig_btt_lteq_max_first_incr, + I2 => \sig_btt_cntr_reg_n_0_[15]\, + O => \sig_btt_cntr_prv0_carry__2_i_1_n_0\ + ); +\sig_btt_cntr_prv0_carry__2_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"95" + ) + port map ( + I0 => sig_btt_cntr_dup(14), + I1 => sig_btt_lteq_max_first_incr, + I2 => \sig_btt_cntr_reg_n_0_[14]\, + O => \sig_btt_cntr_prv0_carry__2_i_2_n_0\ + ); +\sig_btt_cntr_prv0_carry__2_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"95" + ) + port map ( + I0 => sig_btt_cntr_dup(13), + I1 => sig_btt_lteq_max_first_incr, + I2 => \sig_btt_cntr_reg_n_0_[13]\, + O => \sig_btt_cntr_prv0_carry__2_i_3_n_0\ + ); +\sig_btt_cntr_prv0_carry__2_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"95" + ) + port map ( + I0 => sig_btt_cntr_dup(12), + I1 => sig_btt_lteq_max_first_incr, + I2 => \sig_btt_cntr_reg_n_0_[12]\, + O => \sig_btt_cntr_prv0_carry__2_i_4_n_0\ + ); +sig_btt_cntr_prv0_carry_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"95" + ) + port map ( + I0 => sig_btt_cntr_dup(3), + I1 => sig_btt_lteq_max_first_incr, + I2 => \sig_btt_cntr_reg_n_0_[3]\, + O => sig_btt_cntr_prv0_carry_i_1_n_0 + ); +sig_btt_cntr_prv0_carry_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"95" + ) + port map ( + I0 => sig_btt_cntr_dup(2), + I1 => sig_btt_lteq_max_first_incr, + I2 => \sig_btt_cntr_reg_n_0_[2]\, + O => sig_btt_cntr_prv0_carry_i_2_n_0 + ); +sig_btt_cntr_prv0_carry_i_3: unisim.vcomponents.LUT3 + generic map( + INIT => X"95" + ) + port map ( + I0 => sig_btt_cntr_dup(1), + I1 => sig_btt_lteq_max_first_incr, + I2 => \sig_btt_cntr_reg_n_0_[1]\, + O => sig_btt_cntr_prv0_carry_i_3_n_0 + ); +sig_btt_cntr_prv0_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"A965" + ) + port map ( + I0 => sig_btt_cntr_dup(0), + I1 => sig_btt_lteq_max_first_incr, + I2 => \sig_max_first_increment_reg_n_0_[0]\, + I3 => sig_btt_cntr(0), + O => sig_btt_cntr_prv0_carry_i_4_n_0 + ); +\sig_btt_cntr_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(0), + Q => sig_btt_cntr(0), + R => I_TSTRB_FIFO_n_8 + ); +\sig_btt_cntr_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(10), + Q => \sig_btt_cntr_reg_n_0_[10]\, + R => I_TSTRB_FIFO_n_8 + ); +\sig_btt_cntr_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(11), + Q => \sig_btt_cntr_reg_n_0_[11]\, + R => I_TSTRB_FIFO_n_8 + ); +\sig_btt_cntr_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(12), + Q => \sig_btt_cntr_reg_n_0_[12]\, + R => I_TSTRB_FIFO_n_8 + ); +\sig_btt_cntr_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(13), + Q => \sig_btt_cntr_reg_n_0_[13]\, + R => I_TSTRB_FIFO_n_8 + ); +\sig_btt_cntr_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(14), + Q => \sig_btt_cntr_reg_n_0_[14]\, + R => I_TSTRB_FIFO_n_8 + ); +\sig_btt_cntr_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(15), + Q => \sig_btt_cntr_reg_n_0_[15]\, + R => I_TSTRB_FIFO_n_8 + ); +\sig_btt_cntr_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(1), + Q => \sig_btt_cntr_reg_n_0_[1]\, + R => I_TSTRB_FIFO_n_8 + ); +\sig_btt_cntr_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(2), + Q => \sig_btt_cntr_reg_n_0_[2]\, + R => I_TSTRB_FIFO_n_8 + ); +\sig_btt_cntr_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(3), + Q => \sig_btt_cntr_reg_n_0_[3]\, + R => I_TSTRB_FIFO_n_8 + ); +\sig_btt_cntr_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(4), + Q => \sig_btt_cntr_reg_n_0_[4]\, + R => I_TSTRB_FIFO_n_8 + ); +\sig_btt_cntr_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(5), + Q => \sig_btt_cntr_reg_n_0_[5]\, + R => I_TSTRB_FIFO_n_8 + ); +\sig_btt_cntr_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(6), + Q => \sig_btt_cntr_reg_n_0_[6]\, + R => I_TSTRB_FIFO_n_8 + ); +\sig_btt_cntr_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(7), + Q => \sig_btt_cntr_reg_n_0_[7]\, + R => I_TSTRB_FIFO_n_8 + ); +\sig_btt_cntr_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(8), + Q => \sig_btt_cntr_reg_n_0_[8]\, + R => I_TSTRB_FIFO_n_8 + ); +\sig_btt_cntr_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_btt_cntr03_out, + D => sel0(9), + Q => \sig_btt_cntr_reg_n_0_[9]\, + R => I_TSTRB_FIFO_n_8 + ); +sig_btt_eq_0_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF2222222E" + ) + port map ( + I0 => sig_btt_eq_0, + I1 => sig_btt_cntr03_out, + I2 => sig_btt_eq_0_i_2_n_0, + I3 => sig_btt_eq_0_i_3_n_0, + I4 => sig_btt_eq_0_i_4_n_0, + I5 => I_TSTRB_FIFO_n_8, + O => sig_btt_eq_0_i_1_n_0 + ); +sig_btt_eq_0_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => sel0(5), + I1 => sel0(4), + I2 => sel0(7), + I3 => sel0(6), + I4 => sig_btt_eq_0_i_5_n_0, + I5 => sig_btt_eq_0_i_6_n_0, + O => sig_btt_eq_0_i_2_n_0 + ); +sig_btt_eq_0_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFEEFA" + ) + port map ( + I0 => sel0(15), + I1 => \out\(14), + I2 => sig_btt_cntr_prv0(14), + I3 => sig_curr_eof_reg_i_1_n_0, + I4 => sel0(12), + I5 => sel0(13), + O => sig_btt_eq_0_i_3_n_0 + ); +sig_btt_eq_0_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFEEFA" + ) + port map ( + I0 => sel0(10), + I1 => \out\(11), + I2 => sig_btt_cntr_prv0(11), + I3 => sig_curr_eof_reg_i_1_n_0, + I4 => sel0(8), + I5 => sel0(9), + O => sig_btt_eq_0_i_4_n_0 + ); +sig_btt_eq_0_i_5: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFAFAAFCFFACAA" + ) + port map ( + I0 => sig_btt_cntr_prv0(1), + I1 => \out\(1), + I2 => sig_cmd_full, + I3 => sig_sm_ld_dre_cmd, + I4 => sig_btt_cntr_prv0(0), + I5 => \out\(0), + O => sig_btt_eq_0_i_5_n_0 + ); +sig_btt_eq_0_i_6: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFAFAAFCFFACAA" + ) + port map ( + I0 => sig_btt_cntr_prv0(3), + I1 => \out\(3), + I2 => sig_cmd_full, + I3 => sig_sm_ld_dre_cmd, + I4 => sig_btt_cntr_prv0(2), + I5 => \out\(2), + O => sig_btt_eq_0_i_6_n_0 + ); +sig_btt_eq_0_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_btt_eq_0_i_1_n_0, + Q => sig_btt_eq_0, + R => '0' + ); +sig_btt_lteq_max_first_incr0_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => sig_btt_lteq_max_first_incr0_carry_n_0, + CO(2) => sig_btt_lteq_max_first_incr0_carry_n_1, + CO(1) => sig_btt_lteq_max_first_incr0_carry_n_2, + CO(0) => sig_btt_lteq_max_first_incr0_carry_n_3, + CYINIT => '1', + DI(3 downto 1) => B"000", + DI(0) => SLICE_INSERTION_n_9, + O(3 downto 0) => NLW_sig_btt_lteq_max_first_incr0_carry_O_UNCONNECTED(3 downto 0), + S(3) => SLICE_INSERTION_n_5, + S(2) => SLICE_INSERTION_n_6, + S(1) => SLICE_INSERTION_n_7, + S(0) => SLICE_INSERTION_n_8 + ); +\sig_btt_lteq_max_first_incr0_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => sig_btt_lteq_max_first_incr0_carry_n_0, + CO(3) => sig_btt_lteq_max_first_incr, + CO(2) => \sig_btt_lteq_max_first_incr0_carry__0_n_1\, + CO(1) => \sig_btt_lteq_max_first_incr0_carry__0_n_2\, + CO(0) => \sig_btt_lteq_max_first_incr0_carry__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => \NLW_sig_btt_lteq_max_first_incr0_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => SLICE_INSERTION_n_10, + S(2) => SLICE_INSERTION_n_11, + S(1) => SLICE_INSERTION_n_12, + S(0) => SLICE_INSERTION_n_13 + ); +sig_cmd_empty_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => I_TSTRB_FIFO_n_6, + Q => \^p_7_out\, + R => '0' + ); +sig_cmd_full_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => I_TSTRB_FIFO_n_5, + Q => sig_cmd_full, + R => '0' + ); +sig_curr_eof_reg_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => sig_sm_ld_dre_cmd, + I1 => sig_cmd_full, + O => sig_curr_eof_reg_i_1_n_0 + ); +sig_curr_eof_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_curr_eof_reg_i_1_n_0, + D => \out\(16), + Q => sig_curr_eof_reg, + R => I_TSTRB_FIFO_n_1 + ); +sig_eop_halt_xfer_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"F4" + ) + port map ( + I0 => sig_valid_fifo_ld12_out, + I1 => sig_eop_halt_xfer, + I2 => I_TSTRB_FIFO_n_8, + O => sig_eop_halt_xfer_i_1_n_0 + ); +sig_eop_halt_xfer_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_eop_halt_xfer_i_1_n_0, + Q => sig_eop_halt_xfer, + R => '0' + ); +sig_eop_sent_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_eop_sent, + Q => sig_eop_sent_reg, + R => I_TSTRB_FIFO_n_1 + ); +\sig_max_first_increment[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFBA" + ) + port map ( + I0 => sig_valid_fifo_ld12_out, + I1 => sig_cmd_full, + I2 => sig_sm_ld_dre_cmd, + I3 => \sig_max_first_increment_reg_n_0_[0]\, + O => \sig_max_first_increment[0]_i_1_n_0\ + ); +\sig_max_first_increment_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \sig_max_first_increment[0]_i_1_n_0\, + Q => \sig_max_first_increment_reg_n_0_[0]\, + R => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_wr_status_cntl is + port ( + sig_wsc2stat_status_valid : out STD_LOGIC; + \in\ : out STD_LOGIC_VECTOR ( 16 downto 0 ); + sig_wdc_status_going_full : out STD_LOGIC; + sig_init_reg : out STD_LOGIC; + sig_halt_reg : out STD_LOGIC; + sig_push_to_wsc_reg : out STD_LOGIC; + sig_wr_fifo : out STD_LOGIC; + m_axi_s2mm_bready : out STD_LOGIC; + sig_input_cache_type_reg0 : out STD_LOGIC; + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_wsc2rst_stop_cmplt : out STD_LOGIC; + sig_init_done_reg : out STD_LOGIC; + sig_init_done_reg_0 : out STD_LOGIC; + sig_init_done_reg_1 : out STD_LOGIC; + sig_init_done_reg_2 : out STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_inhibit_rdy_n_reg : in STD_LOGIC; + sig_s_h_halt_reg_reg : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_data2wsc_valid : in STD_LOGIC; + sig_set_push2wsc : in STD_LOGIC; + \out\ : in STD_LOGIC; + m_axi_s2mm_bvalid : in STD_LOGIC; + sig_psm_pop_input_cmd : in STD_LOGIC; + sig_csm_pop_child_cmd : in STD_LOGIC; + sig_halt_reg_dly3 : in STD_LOGIC; + sig_addr2wsc_calc_error : in STD_LOGIC; + sig_init_reg2 : in STD_LOGIC; + sig_init_done : in STD_LOGIC; + sig_init_done_0 : in STD_LOGIC; + sig_init_done_1 : in STD_LOGIC; + sig_init_done_2 : in STD_LOGIC; + m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \GEN_INDET_BTT.lsig_eop_reg_reg\ : in STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_wr_status_cntl : entity is "axi_datamover_wr_status_cntl"; +end Arty_Z7_20_axi_vdma_0_0_axi_datamover_wr_status_cntl; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_wr_status_cntl is + signal \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_18\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_19\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_20\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_22\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_24\ : STD_LOGIC; + signal I_WRESP_STATUS_FIFO_n_1 : STD_LOGIC; + signal I_WRESP_STATUS_FIFO_n_2 : STD_LOGIC; + signal I_WRESP_STATUS_FIFO_n_3 : STD_LOGIC; + signal I_WRESP_STATUS_FIFO_n_4 : STD_LOGIC; + signal I_WRESP_STATUS_FIFO_n_5 : STD_LOGIC; + signal I_WRESP_STATUS_FIFO_n_7 : STD_LOGIC; + signal \^in\ : STD_LOGIC_VECTOR ( 16 downto 0 ); + signal p_0_in : STD_LOGIC; + signal p_4_out : STD_LOGIC; + signal \sig_addr_posted_cntr[0]_i_1__0_n_0\ : STD_LOGIC; + signal sig_addr_posted_cntr_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal sig_coelsc_reg_empty : STD_LOGIC; + signal sig_dcntl_sfifo_out : STD_LOGIC_VECTOR ( 22 downto 4 ); + signal \^sig_halt_reg\ : STD_LOGIC; + signal \^sig_init_reg\ : STD_LOGIC; + signal sig_push_coelsc_reg : STD_LOGIC; + signal sig_rd_empty : STD_LOGIC; + signal sig_statcnt_gt_eq_thres : STD_LOGIC; + signal \sig_wdc_statcnt[0]_i_1_n_0\ : STD_LOGIC; + signal \sig_wdc_statcnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); +begin + \in\(16 downto 0) <= \^in\(16 downto 0); + sig_halt_reg <= \^sig_halt_reg\; + sig_init_reg <= \^sig_init_reg\; +\GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO\: entity work.\Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized6\ + port map ( + D(2) => \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_18\, + D(1) => \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_19\, + D(0) => \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_20\, + E(0) => \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_24\, + \GEN_INDET_BTT.lsig_eop_reg_reg\(15 downto 0) => \GEN_INDET_BTT.lsig_eop_reg_reg\(15 downto 0), + \INFERRED_GEN.cnt_i_reg[1]\ => \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_22\, + \INFERRED_GEN.cnt_i_reg[3]\(0) => sig_rd_empty, + Q(3 downto 0) => \sig_wdc_statcnt_reg__0\(3 downto 0), + \in\(0) => \^in\(0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\(15 downto 2) => sig_dcntl_sfifo_out(22 downto 9), + \out\(1 downto 0) => sig_dcntl_sfifo_out(5 downto 4), + p_0_in => p_0_in, + p_4_out => p_4_out, + sel => sig_wr_fifo, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_coelsc_reg_empty => sig_coelsc_reg_empty, + sig_data2wsc_valid => sig_data2wsc_valid, + sig_init_reg2 => sig_init_reg2, + sig_init_reg_reg => \^sig_init_reg\, + sig_push_coelsc_reg => sig_push_coelsc_reg, + sig_push_to_wsc_reg => sig_push_to_wsc_reg, + sig_set_push2wsc => sig_set_push2wsc, + sig_stream_rst => sig_stream_rst + ); +\GEN_ENABLE_INDET_BTT.sig_coelsc_bytes_rcvd_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_push_coelsc_reg, + D => sig_dcntl_sfifo_out(16), + Q => \^in\(10), + R => sig_inhibit_rdy_n_reg + ); +\GEN_ENABLE_INDET_BTT.sig_coelsc_bytes_rcvd_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_push_coelsc_reg, + D => sig_dcntl_sfifo_out(17), + Q => \^in\(11), + R => sig_inhibit_rdy_n_reg + ); +\GEN_ENABLE_INDET_BTT.sig_coelsc_bytes_rcvd_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_push_coelsc_reg, + D => sig_dcntl_sfifo_out(18), + Q => \^in\(12), + R => sig_inhibit_rdy_n_reg + ); +\GEN_ENABLE_INDET_BTT.sig_coelsc_bytes_rcvd_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_push_coelsc_reg, + D => sig_dcntl_sfifo_out(19), + Q => \^in\(13), + R => sig_inhibit_rdy_n_reg + ); +\GEN_ENABLE_INDET_BTT.sig_coelsc_bytes_rcvd_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_push_coelsc_reg, + D => sig_dcntl_sfifo_out(20), + Q => \^in\(14), + R => sig_inhibit_rdy_n_reg + ); +\GEN_ENABLE_INDET_BTT.sig_coelsc_bytes_rcvd_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_push_coelsc_reg, + D => sig_dcntl_sfifo_out(21), + Q => \^in\(15), + R => sig_inhibit_rdy_n_reg + ); +\GEN_ENABLE_INDET_BTT.sig_coelsc_bytes_rcvd_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_push_coelsc_reg, + D => sig_dcntl_sfifo_out(9), + Q => \^in\(3), + R => sig_inhibit_rdy_n_reg + ); +\GEN_ENABLE_INDET_BTT.sig_coelsc_bytes_rcvd_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_push_coelsc_reg, + D => sig_dcntl_sfifo_out(10), + Q => \^in\(4), + R => sig_inhibit_rdy_n_reg + ); +\GEN_ENABLE_INDET_BTT.sig_coelsc_bytes_rcvd_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_push_coelsc_reg, + D => sig_dcntl_sfifo_out(11), + Q => \^in\(5), + R => sig_inhibit_rdy_n_reg + ); +\GEN_ENABLE_INDET_BTT.sig_coelsc_bytes_rcvd_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_push_coelsc_reg, + D => sig_dcntl_sfifo_out(12), + Q => \^in\(6), + R => sig_inhibit_rdy_n_reg + ); +\GEN_ENABLE_INDET_BTT.sig_coelsc_bytes_rcvd_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_push_coelsc_reg, + D => sig_dcntl_sfifo_out(13), + Q => \^in\(7), + R => sig_inhibit_rdy_n_reg + ); +\GEN_ENABLE_INDET_BTT.sig_coelsc_bytes_rcvd_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_push_coelsc_reg, + D => sig_dcntl_sfifo_out(14), + Q => \^in\(8), + R => sig_inhibit_rdy_n_reg + ); +\GEN_ENABLE_INDET_BTT.sig_coelsc_bytes_rcvd_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_push_coelsc_reg, + D => sig_dcntl_sfifo_out(15), + Q => \^in\(9), + R => sig_inhibit_rdy_n_reg + ); +\GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_push_coelsc_reg, + D => I_WRESP_STATUS_FIFO_n_1, + Q => \^in\(1), + R => sig_inhibit_rdy_n_reg + ); +\GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_push_coelsc_reg, + D => sig_dcntl_sfifo_out(22), + Q => \^in\(16), + R => sig_inhibit_rdy_n_reg + ); +\GEN_ENABLE_INDET_BTT.sig_coelsc_interr_reg_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_push_coelsc_reg, + D => p_4_out, + Q => \^in\(0), + R => sig_inhibit_rdy_n_reg + ); +\GEN_ENABLE_INDET_BTT.sig_coelsc_reg_empty_reg\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_push_coelsc_reg, + D => p_0_in, + Q => sig_coelsc_reg_empty, + S => sig_inhibit_rdy_n_reg + ); +\GEN_ENABLE_INDET_BTT.sig_coelsc_reg_full_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_push_coelsc_reg, + D => sig_dcntl_sfifo_out(5), + Q => sig_wsc2stat_status_valid, + R => sig_inhibit_rdy_n_reg + ); +\GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_push_coelsc_reg, + D => I_WRESP_STATUS_FIFO_n_2, + Q => \^in\(2), + R => sig_inhibit_rdy_n_reg + ); +I_WRESP_STATUS_FIFO: entity work.\Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized5\ + port map ( + D(2) => I_WRESP_STATUS_FIFO_n_3, + D(1) => I_WRESP_STATUS_FIFO_n_4, + D(0) => I_WRESP_STATUS_FIFO_n_5, + E(0) => I_WRESP_STATUS_FIFO_n_7, + \GEN_ENABLE_INDET_BTT.sig_coelsc_decerr_reg_reg\ => I_WRESP_STATUS_FIFO_n_1, + \GEN_ENABLE_INDET_BTT.sig_coelsc_slverr_reg_reg\ => I_WRESP_STATUS_FIFO_n_2, + \INFERRED_GEN.cnt_i_reg[2]\(0) => sig_rd_empty, + \INFERRED_GEN.cnt_i_reg[3]\ => \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_22\, + Q(3 downto 0) => sig_addr_posted_cntr_reg(3 downto 0), + SR(0) => SR(0), + \in\(1 downto 0) => \^in\(2 downto 1), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + m_axi_s2mm_bready => m_axi_s2mm_bready, + m_axi_s2mm_bresp(1 downto 0) => m_axi_s2mm_bresp(1 downto 0), + m_axi_s2mm_bvalid => m_axi_s2mm_bvalid, + \out\(0) => sig_dcntl_sfifo_out(4), + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_csm_pop_child_cmd => sig_csm_pop_child_cmd, + sig_halt_reg => \^sig_halt_reg\, + sig_init_done => sig_init_done, + sig_init_done_0 => sig_init_done_0, + sig_init_done_1 => sig_init_done_1, + sig_init_done_2 => sig_init_done_2, + sig_init_done_reg_0 => sig_init_done_reg, + sig_init_done_reg_1 => sig_init_done_reg_0, + sig_init_done_reg_2 => sig_init_done_reg_1, + sig_init_done_reg_3 => sig_init_done_reg_2, + sig_init_reg2 => sig_init_reg2, + sig_init_reg2_reg => \^sig_init_reg\, + sig_input_cache_type_reg0 => sig_input_cache_type_reg0, + sig_posted_to_axi_reg => \out\, + sig_psm_pop_input_cmd => sig_psm_pop_input_cmd, + sig_push_coelsc_reg => sig_push_coelsc_reg, + sig_stream_rst => sig_stream_rst + ); +\sig_addr_posted_cntr[0]_i_1__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => sig_addr_posted_cntr_reg(0), + O => \sig_addr_posted_cntr[0]_i_1__0_n_0\ + ); +\sig_addr_posted_cntr_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => I_WRESP_STATUS_FIFO_n_7, + D => \sig_addr_posted_cntr[0]_i_1__0_n_0\, + Q => sig_addr_posted_cntr_reg(0), + R => sig_stream_rst + ); +\sig_addr_posted_cntr_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => I_WRESP_STATUS_FIFO_n_7, + D => I_WRESP_STATUS_FIFO_n_5, + Q => sig_addr_posted_cntr_reg(1), + R => sig_stream_rst + ); +\sig_addr_posted_cntr_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => I_WRESP_STATUS_FIFO_n_7, + D => I_WRESP_STATUS_FIFO_n_4, + Q => sig_addr_posted_cntr_reg(2), + R => sig_stream_rst + ); +\sig_addr_posted_cntr_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => I_WRESP_STATUS_FIFO_n_7, + D => I_WRESP_STATUS_FIFO_n_3, + Q => sig_addr_posted_cntr_reg(3), + R => sig_stream_rst + ); +\sig_halt_cmplt_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000002000000002" + ) + port map ( + I0 => sig_halt_reg_dly3, + I1 => sig_addr_posted_cntr_reg(1), + I2 => sig_addr_posted_cntr_reg(0), + I3 => sig_addr_posted_cntr_reg(2), + I4 => sig_addr_posted_cntr_reg(3), + I5 => sig_addr2wsc_calc_error, + O => sig_wsc2rst_stop_cmplt + ); +sig_halt_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_s_h_halt_reg_reg, + Q => \^sig_halt_reg\, + R => sig_stream_rst + ); +\sig_wdc_statcnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \sig_wdc_statcnt_reg__0\(0), + O => \sig_wdc_statcnt[0]_i_1_n_0\ + ); +\sig_wdc_statcnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_24\, + D => \sig_wdc_statcnt[0]_i_1_n_0\, + Q => \sig_wdc_statcnt_reg__0\(0), + R => sig_stream_rst + ); +\sig_wdc_statcnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_24\, + D => \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_20\, + Q => \sig_wdc_statcnt_reg__0\(1), + R => sig_stream_rst + ); +\sig_wdc_statcnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_24\, + D => \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_19\, + Q => \sig_wdc_statcnt_reg__0\(2), + R => sig_stream_rst + ); +\sig_wdc_statcnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_24\, + D => \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO_n_18\, + Q => \sig_wdc_statcnt_reg__0\(3), + R => sig_stream_rst + ); +sig_wdc_status_going_full_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \sig_wdc_statcnt_reg__0\(3), + I1 => \sig_wdc_statcnt_reg__0\(2), + O => sig_statcnt_gt_eq_thres + ); +sig_wdc_status_going_full_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_statcnt_gt_eq_thres, + Q => sig_wdc_status_going_full, + R => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_wrdata_cntl is + port ( + \INFERRED_GEN.cnt_i_reg[0]\ : out STD_LOGIC; + sig_dqual_reg_full : out STD_LOGIC; + sig_halt_reg_dly3 : out STD_LOGIC; + sig_data2wsc_valid : out STD_LOGIC; + \in\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); + lsig_eop_reg : out STD_LOGIC; + lsig_end_of_cmd_reg : out STD_LOGIC; + sig_init_done : out STD_LOGIC; + sig_set_push2wsc : out STD_LOGIC; + \sig_dbeat_cntr_eq_0__2\ : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_wdc2ibtt_tready : out STD_LOGIC; + sig_inhibit_rdy_n : out STD_LOGIC; + \sig_clr_cmd2data_valid4_out__0\ : out STD_LOGIC; + sig_data2skid_wvalid : out STD_LOGIC; + sig_data2rst_stop_cmplt : out STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_halt_reg : in STD_LOGIC; + \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ : in STD_LOGIC; + sig_m_valid_out_reg : in STD_LOGIC; + sig_init_reg_reg : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_wr_fifo : in STD_LOGIC; + \out\ : in STD_LOGIC; + sig_m_valid_out_reg_0 : in STD_LOGIC; + \sig_data_reg_out_reg[67]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_ibtt2wdc_tlast : in STD_LOGIC; + p_11_out : in STD_LOGIC; + sig_s_ready_out_reg : in STD_LOGIC; + sig_wdc_status_going_full : in STD_LOGIC; + sig_inhibit_rdy_n_reg : in STD_LOGIC; + sig_wsc2stat_status_valid : in STD_LOGIC; + sig_posted_to_axi_reg : in STD_LOGIC; + sig_xfer_calc_err_reg_reg : in STD_LOGIC_VECTOR ( 8 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_m_valid_out_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_m_valid_out_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_wrdata_cntl : entity is "axi_datamover_wrdata_cntl"; +end Arty_Z7_20_axi_vdma_0_0_axi_datamover_wrdata_cntl; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_wrdata_cntl is + signal \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_16\ : STD_LOGIC; + signal \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_2\ : STD_LOGIC; + signal \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_20\ : STD_LOGIC; + signal \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_4\ : STD_LOGIC; + signal \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_5\ : STD_LOGIC; + signal \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_7\ : STD_LOGIC; + signal \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_8\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr[10]_i_2_n_0\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr[10]_i_3_n_0\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr[10]_i_4_n_0\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr[10]_i_5_n_0\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr[14]_i_2_n_0\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr[14]_i_3_n_0\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr[14]_i_4_n_0\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr[14]_i_5_n_0\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr[15]_i_5_n_0\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr[3]_i_1_n_0\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr[6]_i_3_n_0\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr[6]_i_4_n_0\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr[6]_i_5_n_0\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr[6]_i_6_n_0\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr[7]_i_1_n_0\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_0\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_1\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_2\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_3\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_4\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_5\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_6\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_7\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_0\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_1\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_2\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_3\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_4\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_5\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_6\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_7\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr_reg[15]_i_3_n_7\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_0\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_1\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_2\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_3\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_4\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_5\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_6\ : STD_LOGIC; + signal \GEN_INDET_BTT.lsig_end_of_cmd_reg_i_1_n_0\ : STD_LOGIC; + signal \^in\ : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \^lsig_end_of_cmd_reg\ : STD_LOGIC; + signal \^lsig_eop_reg\ : STD_LOGIC; + signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal sig_addr_posted_cntr : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \sig_addr_posted_cntr[0]_i_1_n_0\ : STD_LOGIC; + signal \sig_addr_posted_cntr[1]_i_1_n_0\ : STD_LOGIC; + signal \sig_addr_posted_cntr[2]_i_1_n_0\ : STD_LOGIC; + signal sig_cmd_fifo_data_out : STD_LOGIC_VECTOR ( 35 downto 33 ); + signal sig_data2wsc_calc_err_i_1_n_0 : STD_LOGIC; + signal sig_data2wsc_cmd_cmplt_i_1_n_0 : STD_LOGIC; + signal \sig_dbeat_cntr[4]_i_2_n_0\ : STD_LOGIC; + signal \sig_dbeat_cntr[5]_i_2_n_0\ : STD_LOGIC; + signal \sig_dbeat_cntr[7]_i_3__0_n_0\ : STD_LOGIC; + signal \^sig_dbeat_cntr_eq_0__2\ : STD_LOGIC; + signal \sig_dbeat_cntr_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal sig_dqual_reg_empty : STD_LOGIC; + signal \^sig_dqual_reg_full\ : STD_LOGIC; + signal \sig_first_dbeat1__0\ : STD_LOGIC; + signal \sig_good_mmap_dbeat12_out__0\ : STD_LOGIC; + signal sig_halt_reg_dly1 : STD_LOGIC; + signal sig_halt_reg_dly2 : STD_LOGIC; + signal \^sig_halt_reg_dly3\ : STD_LOGIC; + signal sig_last_dbeat_reg_n_0 : STD_LOGIC; + signal sig_last_mmap_dbeat : STD_LOGIC; + signal sig_last_mmap_dbeat_reg : STD_LOGIC; + signal sig_last_reg_out_i_4_n_0 : STD_LOGIC; + signal sig_ld_new_cmd_reg : STD_LOGIC; + signal sig_next_calc_error_reg : STD_LOGIC; + signal sig_next_cmd_cmplt_reg : STD_LOGIC; + signal sig_next_sequential_reg : STD_LOGIC; + signal sig_push_dqual_reg : STD_LOGIC; + signal sig_push_err2wsc : STD_LOGIC; + signal sig_push_err2wsc_i_1_n_0 : STD_LOGIC; + signal \^sig_set_push2wsc\ : STD_LOGIC; + signal sig_single_dbeat : STD_LOGIC; + signal \^sig_wdc2ibtt_tready\ : STD_LOGIC; + signal \NLW_GEN_INDET_BTT.lsig_byte_cntr_reg[15]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_GEN_INDET_BTT.lsig_byte_cntr_reg[15]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[5][22]_srl6_i_1\ : label is "soft_lutpair246"; + attribute SOFT_HLUTNM of \sig_addr_posted_cntr[1]_i_1\ : label is "soft_lutpair244"; + attribute SOFT_HLUTNM of \sig_addr_posted_cntr[2]_i_1\ : label is "soft_lutpair244"; + attribute SOFT_HLUTNM of \sig_dbeat_cntr[4]_i_2\ : label is "soft_lutpair245"; + attribute SOFT_HLUTNM of \sig_last_mmap_dbeat_reg_i_1__0\ : label is "soft_lutpair247"; + attribute SOFT_HLUTNM of sig_last_reg_out_i_3 : label is "soft_lutpair245"; + attribute SOFT_HLUTNM of sig_push_err2wsc_i_1 : label is "soft_lutpair246"; + attribute SOFT_HLUTNM of sig_push_to_wsc_i_2 : label is "soft_lutpair247"; +begin + \in\(15 downto 0) <= \^in\(15 downto 0); + lsig_end_of_cmd_reg <= \^lsig_end_of_cmd_reg\; + lsig_eop_reg <= \^lsig_eop_reg\; + \sig_dbeat_cntr_eq_0__2\ <= \^sig_dbeat_cntr_eq_0__2\; + sig_dqual_reg_full <= \^sig_dqual_reg_full\; + sig_halt_reg_dly3 <= \^sig_halt_reg_dly3\; + sig_set_push2wsc <= \^sig_set_push2wsc\; + sig_wdc2ibtt_tready <= \^sig_wdc2ibtt_tready\; +\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO\: entity work.\Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized10\ + port map ( + D(7) => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_7\, + D(6) => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_8\, + D(5 downto 0) => \p_0_in__0\(5 downto 0), + E(0) => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_16\, + \INFERRED_GEN.cnt_i_reg[0]\ => \INFERRED_GEN.cnt_i_reg[0]\, + \INFERRED_GEN.cnt_i_reg[0]_0\ => sig_inhibit_rdy_n, + Q(7 downto 0) => \sig_dbeat_cntr_reg__0\(7 downto 0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\(2 downto 0) => sig_cmd_fifo_data_out(35 downto 33), + p_11_out => p_11_out, + sig_addr_posted_cntr(2 downto 0) => sig_addr_posted_cntr(2 downto 0), + \sig_clr_cmd2data_valid4_out__0\ => \sig_clr_cmd2data_valid4_out__0\, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + \sig_dbeat_cntr_reg[1]\ => \^sig_dbeat_cntr_eq_0__2\, + \sig_dbeat_cntr_reg[2]\ => \sig_dbeat_cntr[4]_i_2_n_0\, + \sig_dbeat_cntr_reg[3]\ => \sig_dbeat_cntr[5]_i_2_n_0\, + \sig_dbeat_cntr_reg[4]\ => \sig_dbeat_cntr[7]_i_3__0_n_0\, + sig_dqual_reg_empty => sig_dqual_reg_empty, + sig_dqual_reg_empty_reg => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_20\, + sig_dqual_reg_full_reg => \^sig_dqual_reg_full\, + \sig_first_dbeat1__0\ => \sig_first_dbeat1__0\, + \sig_good_mmap_dbeat12_out__0\ => \sig_good_mmap_dbeat12_out__0\, + sig_halt_reg => sig_halt_reg, + sig_halt_reg_dly3 => \^sig_halt_reg_dly3\, + sig_inhibit_rdy_n_reg_0 => sig_inhibit_rdy_n_reg, + sig_init_done => sig_init_done, + sig_init_reg_reg => sig_init_reg_reg, + sig_last_dbeat_reg => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_2\, + sig_last_dbeat_reg_0 => sig_last_dbeat_reg_n_0, + sig_last_mmap_dbeat_reg => sig_last_mmap_dbeat_reg, + sig_ld_new_cmd_reg => sig_ld_new_cmd_reg, + sig_ld_new_cmd_reg_reg => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_4\, + sig_m_valid_out_reg => sig_m_valid_out_reg_0, + sig_next_calc_error_reg => sig_next_calc_error_reg, + sig_next_calc_error_reg_reg => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_5\, + sig_next_sequential_reg => sig_next_sequential_reg, + sig_posted_to_axi_reg => sig_posted_to_axi_reg, + sig_push_dqual_reg => sig_push_dqual_reg, + sig_s_ready_out_reg => sig_s_ready_out_reg, + sig_single_dbeat => sig_single_dbeat, + sig_stream_rst => sig_stream_rst, + sig_wdc_status_going_full => sig_wdc_status_going_full, + sig_wsc2stat_status_valid => sig_wsc2stat_status_valid, + sig_xfer_calc_err_reg_reg(8 downto 0) => sig_xfer_calc_err_reg_reg(8 downto 0) + ); +\GEN_INDET_BTT.lsig_byte_cntr[10]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"70F0" + ) + port map ( + I0 => sig_m_valid_out_reg_0, + I1 => \^sig_wdc2ibtt_tready\, + I2 => \^in\(9), + I3 => \^lsig_end_of_cmd_reg\, + O => \GEN_INDET_BTT.lsig_byte_cntr[10]_i_2_n_0\ + ); +\GEN_INDET_BTT.lsig_byte_cntr[10]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"70F0" + ) + port map ( + I0 => sig_m_valid_out_reg_0, + I1 => \^sig_wdc2ibtt_tready\, + I2 => \^in\(8), + I3 => \^lsig_end_of_cmd_reg\, + O => \GEN_INDET_BTT.lsig_byte_cntr[10]_i_3_n_0\ + ); +\GEN_INDET_BTT.lsig_byte_cntr[10]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"70F0" + ) + port map ( + I0 => sig_m_valid_out_reg_0, + I1 => \^sig_wdc2ibtt_tready\, + I2 => \^in\(7), + I3 => \^lsig_end_of_cmd_reg\, + O => \GEN_INDET_BTT.lsig_byte_cntr[10]_i_4_n_0\ + ); +\GEN_INDET_BTT.lsig_byte_cntr[10]_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"70F0" + ) + port map ( + I0 => sig_m_valid_out_reg_0, + I1 => \^sig_wdc2ibtt_tready\, + I2 => \^in\(6), + I3 => \^lsig_end_of_cmd_reg\, + O => \GEN_INDET_BTT.lsig_byte_cntr[10]_i_5_n_0\ + ); +\GEN_INDET_BTT.lsig_byte_cntr[14]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"70F0" + ) + port map ( + I0 => sig_m_valid_out_reg_0, + I1 => \^sig_wdc2ibtt_tready\, + I2 => \^in\(13), + I3 => \^lsig_end_of_cmd_reg\, + O => \GEN_INDET_BTT.lsig_byte_cntr[14]_i_2_n_0\ + ); +\GEN_INDET_BTT.lsig_byte_cntr[14]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"70F0" + ) + port map ( + I0 => sig_m_valid_out_reg_0, + I1 => \^sig_wdc2ibtt_tready\, + I2 => \^in\(12), + I3 => \^lsig_end_of_cmd_reg\, + O => \GEN_INDET_BTT.lsig_byte_cntr[14]_i_3_n_0\ + ); +\GEN_INDET_BTT.lsig_byte_cntr[14]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"70F0" + ) + port map ( + I0 => sig_m_valid_out_reg_0, + I1 => \^sig_wdc2ibtt_tready\, + I2 => \^in\(11), + I3 => \^lsig_end_of_cmd_reg\, + O => \GEN_INDET_BTT.lsig_byte_cntr[14]_i_4_n_0\ + ); +\GEN_INDET_BTT.lsig_byte_cntr[14]_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"70F0" + ) + port map ( + I0 => sig_m_valid_out_reg_0, + I1 => \^sig_wdc2ibtt_tready\, + I2 => \^in\(10), + I3 => \^lsig_end_of_cmd_reg\, + O => \GEN_INDET_BTT.lsig_byte_cntr[14]_i_5_n_0\ + ); +\GEN_INDET_BTT.lsig_byte_cntr[15]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAAAEAAA" + ) + port map ( + I0 => sig_halt_reg, + I1 => sig_s_ready_out_reg, + I2 => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_20\, + I3 => \^sig_dqual_reg_full\, + I4 => sig_next_calc_error_reg, + O => \^sig_wdc2ibtt_tready\ + ); +\GEN_INDET_BTT.lsig_byte_cntr[15]_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"70F0" + ) + port map ( + I0 => sig_m_valid_out_reg_0, + I1 => \^sig_wdc2ibtt_tready\, + I2 => \^in\(14), + I3 => \^lsig_end_of_cmd_reg\, + O => \GEN_INDET_BTT.lsig_byte_cntr[15]_i_5_n_0\ + ); +\GEN_INDET_BTT.lsig_byte_cntr[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"8F0F70F0" + ) + port map ( + I0 => sig_m_valid_out_reg_0, + I1 => \^sig_wdc2ibtt_tready\, + I2 => \^in\(2), + I3 => \^lsig_end_of_cmd_reg\, + I4 => \sig_data_reg_out_reg[67]\(0), + O => \GEN_INDET_BTT.lsig_byte_cntr[3]_i_1_n_0\ + ); +\GEN_INDET_BTT.lsig_byte_cntr[6]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"70F0" + ) + port map ( + I0 => sig_m_valid_out_reg_0, + I1 => \^sig_wdc2ibtt_tready\, + I2 => \^in\(5), + I3 => \^lsig_end_of_cmd_reg\, + O => \GEN_INDET_BTT.lsig_byte_cntr[6]_i_3_n_0\ + ); +\GEN_INDET_BTT.lsig_byte_cntr[6]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"70F0" + ) + port map ( + I0 => sig_m_valid_out_reg_0, + I1 => \^sig_wdc2ibtt_tready\, + I2 => \^in\(4), + I3 => \^lsig_end_of_cmd_reg\, + O => \GEN_INDET_BTT.lsig_byte_cntr[6]_i_4_n_0\ + ); +\GEN_INDET_BTT.lsig_byte_cntr[6]_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"70F0" + ) + port map ( + I0 => sig_m_valid_out_reg_0, + I1 => \^sig_wdc2ibtt_tready\, + I2 => \^in\(3), + I3 => \^lsig_end_of_cmd_reg\, + O => \GEN_INDET_BTT.lsig_byte_cntr[6]_i_5_n_0\ + ); +\GEN_INDET_BTT.lsig_byte_cntr[6]_i_6\: unisim.vcomponents.LUT5 + generic map( + INIT => X"8F0F70F0" + ) + port map ( + I0 => sig_m_valid_out_reg_0, + I1 => \^sig_wdc2ibtt_tready\, + I2 => \^in\(2), + I3 => \^lsig_end_of_cmd_reg\, + I4 => \sig_data_reg_out_reg[67]\(0), + O => \GEN_INDET_BTT.lsig_byte_cntr[6]_i_6_n_0\ + ); +\GEN_INDET_BTT.lsig_byte_cntr[7]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"70FF" + ) + port map ( + I0 => sig_m_valid_out_reg_0, + I1 => \^sig_wdc2ibtt_tready\, + I2 => \^lsig_end_of_cmd_reg\, + I3 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + O => \GEN_INDET_BTT.lsig_byte_cntr[7]_i_1_n_0\ + ); +\GEN_INDET_BTT.lsig_byte_cntr_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_m_valid_out_reg_1(0), + D => \GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_4\, + Q => \^in\(9), + R => SR(0) + ); +\GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_0\, + CO(3) => \GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_0\, + CO(2) => \GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_1\, + CO(1) => \GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_2\, + CO(0) => \GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_4\, + O(2) => \GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_5\, + O(1) => \GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_6\, + O(0) => \GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_7\, + S(3) => \GEN_INDET_BTT.lsig_byte_cntr[10]_i_2_n_0\, + S(2) => \GEN_INDET_BTT.lsig_byte_cntr[10]_i_3_n_0\, + S(1) => \GEN_INDET_BTT.lsig_byte_cntr[10]_i_4_n_0\, + S(0) => \GEN_INDET_BTT.lsig_byte_cntr[10]_i_5_n_0\ + ); +\GEN_INDET_BTT.lsig_byte_cntr_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_m_valid_out_reg_1(0), + D => \GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_7\, + Q => \^in\(10), + R => SR(0) + ); +\GEN_INDET_BTT.lsig_byte_cntr_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_m_valid_out_reg_1(0), + D => \GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_6\, + Q => \^in\(11), + R => SR(0) + ); +\GEN_INDET_BTT.lsig_byte_cntr_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_m_valid_out_reg_1(0), + D => \GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_5\, + Q => \^in\(12), + R => SR(0) + ); +\GEN_INDET_BTT.lsig_byte_cntr_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_m_valid_out_reg_1(0), + D => \GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_4\, + Q => \^in\(13), + R => SR(0) + ); +\GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_0\, + CO(3) => \GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_0\, + CO(2) => \GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_1\, + CO(1) => \GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_2\, + CO(0) => \GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_4\, + O(2) => \GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_5\, + O(1) => \GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_6\, + O(0) => \GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_7\, + S(3) => \GEN_INDET_BTT.lsig_byte_cntr[14]_i_2_n_0\, + S(2) => \GEN_INDET_BTT.lsig_byte_cntr[14]_i_3_n_0\, + S(1) => \GEN_INDET_BTT.lsig_byte_cntr[14]_i_4_n_0\, + S(0) => \GEN_INDET_BTT.lsig_byte_cntr[14]_i_5_n_0\ + ); +\GEN_INDET_BTT.lsig_byte_cntr_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_m_valid_out_reg_1(0), + D => \GEN_INDET_BTT.lsig_byte_cntr_reg[15]_i_3_n_7\, + Q => \^in\(14), + R => SR(0) + ); +\GEN_INDET_BTT.lsig_byte_cntr_reg[15]_i_3\: unisim.vcomponents.CARRY4 + port map ( + CI => \GEN_INDET_BTT.lsig_byte_cntr_reg[14]_i_1_n_0\, + CO(3 downto 0) => \NLW_GEN_INDET_BTT.lsig_byte_cntr_reg[15]_i_3_CO_UNCONNECTED\(3 downto 0), + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 1) => \NLW_GEN_INDET_BTT.lsig_byte_cntr_reg[15]_i_3_O_UNCONNECTED\(3 downto 1), + O(0) => \GEN_INDET_BTT.lsig_byte_cntr_reg[15]_i_3_n_7\, + S(3 downto 1) => B"000", + S(0) => \GEN_INDET_BTT.lsig_byte_cntr[15]_i_5_n_0\ + ); +\GEN_INDET_BTT.lsig_byte_cntr_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_m_valid_out_reg_1(0), + D => \GEN_INDET_BTT.lsig_byte_cntr[3]_i_1_n_0\, + Q => \^in\(2), + R => \GEN_INDET_BTT.lsig_byte_cntr[7]_i_1_n_0\ + ); +\GEN_INDET_BTT.lsig_byte_cntr_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_m_valid_out_reg_1(0), + D => \GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_6\, + Q => \^in\(3), + R => \GEN_INDET_BTT.lsig_byte_cntr[7]_i_1_n_0\ + ); +\GEN_INDET_BTT.lsig_byte_cntr_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_m_valid_out_reg_1(0), + D => \GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_5\, + Q => \^in\(4), + R => \GEN_INDET_BTT.lsig_byte_cntr[7]_i_1_n_0\ + ); +\GEN_INDET_BTT.lsig_byte_cntr_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_m_valid_out_reg_1(0), + D => \GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_4\, + Q => \^in\(5), + R => \GEN_INDET_BTT.lsig_byte_cntr[7]_i_1_n_0\ + ); +\GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_0\, + CO(2) => \GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_1\, + CO(1) => \GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_2\, + CO(0) => \GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => sig_m_valid_out_reg_2(0), + O(3) => \GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_4\, + O(2) => \GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_5\, + O(1) => \GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_n_6\, + O(0) => \NLW_GEN_INDET_BTT.lsig_byte_cntr_reg[6]_i_1_O_UNCONNECTED\(0), + S(3) => \GEN_INDET_BTT.lsig_byte_cntr[6]_i_3_n_0\, + S(2) => \GEN_INDET_BTT.lsig_byte_cntr[6]_i_4_n_0\, + S(1) => \GEN_INDET_BTT.lsig_byte_cntr[6]_i_5_n_0\, + S(0) => \GEN_INDET_BTT.lsig_byte_cntr[6]_i_6_n_0\ + ); +\GEN_INDET_BTT.lsig_byte_cntr_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_m_valid_out_reg_1(0), + D => \GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_7\, + Q => \^in\(6), + R => \GEN_INDET_BTT.lsig_byte_cntr[7]_i_1_n_0\ + ); +\GEN_INDET_BTT.lsig_byte_cntr_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_m_valid_out_reg_1(0), + D => \GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_6\, + Q => \^in\(7), + R => SR(0) + ); +\GEN_INDET_BTT.lsig_byte_cntr_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_m_valid_out_reg_1(0), + D => \GEN_INDET_BTT.lsig_byte_cntr_reg[10]_i_1_n_5\, + Q => \^in\(8), + R => SR(0) + ); +\GEN_INDET_BTT.lsig_end_of_cmd_reg_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F7778000" + ) + port map ( + I0 => sig_m_valid_out_reg_0, + I1 => \^sig_wdc2ibtt_tready\, + I2 => sig_next_cmd_cmplt_reg, + I3 => sig_ibtt2wdc_tlast, + I4 => \^lsig_end_of_cmd_reg\, + O => \GEN_INDET_BTT.lsig_end_of_cmd_reg_i_1_n_0\ + ); +\GEN_INDET_BTT.lsig_end_of_cmd_reg_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_INDET_BTT.lsig_end_of_cmd_reg_i_1_n_0\, + Q => \^lsig_end_of_cmd_reg\, + R => sig_stream_rst + ); +\GEN_INDET_BTT.lsig_eop_reg_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_m_valid_out_reg, + Q => \^lsig_eop_reg\, + R => sig_stream_rst + ); +\INFERRED_GEN.data_reg[5][22]_srl6_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^lsig_eop_reg\, + I1 => sig_next_calc_error_reg, + O => \^in\(15) + ); +\sig_addr_posted_cntr[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D9996664" + ) + port map ( + I0 => sig_last_mmap_dbeat_reg, + I1 => sig_posted_to_axi_reg, + I2 => sig_addr_posted_cntr(1), + I3 => sig_addr_posted_cntr(2), + I4 => sig_addr_posted_cntr(0), + O => \sig_addr_posted_cntr[0]_i_1_n_0\ + ); +\sig_addr_posted_cntr[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F0C2BCF0" + ) + port map ( + I0 => sig_addr_posted_cntr(2), + I1 => sig_addr_posted_cntr(0), + I2 => sig_addr_posted_cntr(1), + I3 => sig_posted_to_axi_reg, + I4 => sig_last_mmap_dbeat_reg, + O => \sig_addr_posted_cntr[1]_i_1_n_0\ + ); +\sig_addr_posted_cntr[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAA8EAAA" + ) + port map ( + I0 => sig_addr_posted_cntr(2), + I1 => sig_addr_posted_cntr(0), + I2 => sig_addr_posted_cntr(1), + I3 => sig_posted_to_axi_reg, + I4 => sig_last_mmap_dbeat_reg, + O => \sig_addr_posted_cntr[2]_i_1_n_0\ + ); +\sig_addr_posted_cntr_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \sig_addr_posted_cntr[0]_i_1_n_0\, + Q => sig_addr_posted_cntr(0), + R => sig_stream_rst + ); +\sig_addr_posted_cntr_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \sig_addr_posted_cntr[1]_i_1_n_0\, + Q => sig_addr_posted_cntr(1), + R => sig_stream_rst + ); +\sig_addr_posted_cntr_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \sig_addr_posted_cntr[2]_i_1_n_0\, + Q => sig_addr_posted_cntr(2), + R => sig_stream_rst + ); +sig_data2wsc_calc_err_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"C0C000A0" + ) + port map ( + I0 => \^in\(0), + I1 => sig_next_calc_error_reg, + I2 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I3 => sig_wr_fifo, + I4 => \^sig_set_push2wsc\, + O => sig_data2wsc_calc_err_i_1_n_0 + ); +sig_data2wsc_calc_err_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_data2wsc_calc_err_i_1_n_0, + Q => \^in\(0), + R => '0' + ); +sig_data2wsc_cmd_cmplt_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"C0C000A0" + ) + port map ( + I0 => \^in\(1), + I1 => sig_next_cmd_cmplt_reg, + I2 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I3 => sig_wr_fifo, + I4 => \^sig_set_push2wsc\, + O => sig_data2wsc_cmd_cmplt_i_1_n_0 + ); +sig_data2wsc_cmd_cmplt_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_data2wsc_cmd_cmplt_i_1_n_0, + Q => \^in\(1), + R => '0' + ); +\sig_data_reg_out[67]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^sig_wdc2ibtt_tready\, + I1 => \out\, + O => E(0) + ); +\sig_dbeat_cntr[4]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \sig_dbeat_cntr_reg__0\(2), + I1 => \sig_dbeat_cntr_reg__0\(0), + I2 => \sig_dbeat_cntr_reg__0\(1), + I3 => \sig_dbeat_cntr_reg__0\(3), + O => \sig_dbeat_cntr[4]_i_2_n_0\ + ); +\sig_dbeat_cntr[5]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => \sig_dbeat_cntr_reg__0\(3), + I1 => \sig_dbeat_cntr_reg__0\(1), + I2 => \sig_dbeat_cntr_reg__0\(0), + I3 => \sig_dbeat_cntr_reg__0\(2), + I4 => \sig_dbeat_cntr_reg__0\(4), + O => \sig_dbeat_cntr[5]_i_2_n_0\ + ); +\sig_dbeat_cntr[7]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => \sig_dbeat_cntr_reg__0\(4), + I1 => \sig_dbeat_cntr_reg__0\(2), + I2 => \sig_dbeat_cntr_reg__0\(0), + I3 => \sig_dbeat_cntr_reg__0\(1), + I4 => \sig_dbeat_cntr_reg__0\(3), + I5 => \sig_dbeat_cntr_reg__0\(5), + O => \sig_dbeat_cntr[7]_i_3__0_n_0\ + ); +\sig_dbeat_cntr_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_16\, + D => \p_0_in__0\(0), + Q => \sig_dbeat_cntr_reg__0\(0), + R => sig_stream_rst + ); +\sig_dbeat_cntr_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_16\, + D => \p_0_in__0\(1), + Q => \sig_dbeat_cntr_reg__0\(1), + R => sig_stream_rst + ); +\sig_dbeat_cntr_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_16\, + D => \p_0_in__0\(2), + Q => \sig_dbeat_cntr_reg__0\(2), + R => sig_stream_rst + ); +\sig_dbeat_cntr_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_16\, + D => \p_0_in__0\(3), + Q => \sig_dbeat_cntr_reg__0\(3), + R => sig_stream_rst + ); +\sig_dbeat_cntr_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_16\, + D => \p_0_in__0\(4), + Q => \sig_dbeat_cntr_reg__0\(4), + R => sig_stream_rst + ); +\sig_dbeat_cntr_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_16\, + D => \p_0_in__0\(5), + Q => \sig_dbeat_cntr_reg__0\(5), + R => sig_stream_rst + ); +\sig_dbeat_cntr_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_16\, + D => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_8\, + Q => \sig_dbeat_cntr_reg__0\(6), + R => sig_stream_rst + ); +\sig_dbeat_cntr_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_16\, + D => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_7\, + Q => \sig_dbeat_cntr_reg__0\(7), + R => sig_stream_rst + ); +sig_dqual_reg_empty_reg: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_push_dqual_reg, + D => '0', + Q => sig_dqual_reg_empty, + S => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_5\ + ); +sig_dqual_reg_full_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_push_dqual_reg, + D => sig_push_dqual_reg, + Q => \^sig_dqual_reg_full\, + R => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_5\ + ); +sig_halt_cmplt_i_3: unisim.vcomponents.LUT5 + generic map( + INIT => X"8888888A" + ) + port map ( + I0 => \^sig_halt_reg_dly3\, + I1 => sig_next_calc_error_reg, + I2 => sig_addr_posted_cntr(1), + I3 => sig_addr_posted_cntr(0), + I4 => sig_addr_posted_cntr(2), + O => sig_data2rst_stop_cmplt + ); +sig_halt_reg_dly1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_halt_reg, + Q => sig_halt_reg_dly1, + R => sig_stream_rst + ); +sig_halt_reg_dly2_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_halt_reg_dly1, + Q => sig_halt_reg_dly2, + R => sig_stream_rst + ); +sig_halt_reg_dly3_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_halt_reg_dly2, + Q => \^sig_halt_reg_dly3\, + R => sig_stream_rst + ); +\sig_last_dbeat_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000001000000000" + ) + port map ( + I0 => \sig_dbeat_cntr_reg__0\(2), + I1 => \sig_dbeat_cntr_reg__0\(3), + I2 => \sig_dbeat_cntr_reg__0\(0), + I3 => \sig_dbeat_cntr_reg__0\(1), + I4 => sig_last_reg_out_i_4_n_0, + I5 => \sig_good_mmap_dbeat12_out__0\, + O => \sig_first_dbeat1__0\ + ); +sig_last_dbeat_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFE00000000" + ) + port map ( + I0 => sig_last_reg_out_i_4_n_0, + I1 => \sig_dbeat_cntr_reg__0\(1), + I2 => \sig_dbeat_cntr_reg__0\(0), + I3 => \sig_dbeat_cntr_reg__0\(3), + I4 => \sig_dbeat_cntr_reg__0\(2), + I5 => \sig_good_mmap_dbeat12_out__0\, + O => sig_single_dbeat + ); +sig_last_dbeat_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_2\, + Q => sig_last_dbeat_reg_n_0, + R => '0' + ); +\sig_last_mmap_dbeat_reg_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \^sig_dqual_reg_full\, + I1 => \^sig_dbeat_cntr_eq_0__2\, + I2 => \sig_good_mmap_dbeat12_out__0\, + O => sig_last_mmap_dbeat + ); +sig_last_mmap_dbeat_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_last_mmap_dbeat, + Q => sig_last_mmap_dbeat_reg, + R => sig_stream_rst + ); +sig_last_reg_out_i_3: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000001" + ) + port map ( + I0 => sig_last_reg_out_i_4_n_0, + I1 => \sig_dbeat_cntr_reg__0\(1), + I2 => \sig_dbeat_cntr_reg__0\(0), + I3 => \sig_dbeat_cntr_reg__0\(3), + I4 => \sig_dbeat_cntr_reg__0\(2), + O => \^sig_dbeat_cntr_eq_0__2\ + ); +sig_last_reg_out_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \sig_dbeat_cntr_reg__0\(7), + I1 => \sig_dbeat_cntr_reg__0\(6), + I2 => \sig_dbeat_cntr_reg__0\(4), + I3 => \sig_dbeat_cntr_reg__0\(5), + O => sig_last_reg_out_i_4_n_0 + ); +sig_ld_new_cmd_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_4\, + Q => sig_ld_new_cmd_reg, + R => '0' + ); +\sig_m_valid_dup_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000A800" + ) + port map ( + I0 => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_20\, + I1 => sig_m_valid_out_reg_0, + I2 => sig_halt_reg, + I3 => \^sig_dqual_reg_full\, + I4 => sig_next_calc_error_reg, + O => sig_data2skid_wvalid + ); +sig_next_calc_error_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_push_dqual_reg, + D => sig_cmd_fifo_data_out(35), + Q => sig_next_calc_error_reg, + R => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_5\ + ); +sig_next_cmd_cmplt_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_push_dqual_reg, + D => sig_cmd_fifo_data_out(34), + Q => sig_next_cmd_cmplt_reg, + R => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_5\ + ); +sig_next_sequential_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_push_dqual_reg, + D => sig_cmd_fifo_data_out(33), + Q => sig_next_sequential_reg, + R => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_5\ + ); +sig_push_err2wsc_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"0080" + ) + port map ( + I0 => sig_ld_new_cmd_reg, + I1 => sig_next_calc_error_reg, + I2 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + I3 => sig_push_err2wsc, + O => sig_push_err2wsc_i_1_n_0 + ); +sig_push_err2wsc_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_push_err2wsc_i_1_n_0, + Q => sig_push_err2wsc, + R => '0' + ); +sig_push_to_wsc_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"EA" + ) + port map ( + I0 => sig_push_err2wsc, + I1 => \sig_good_mmap_dbeat12_out__0\, + I2 => \^sig_dbeat_cntr_eq_0__2\, + O => \^sig_set_push2wsc\ + ); +sig_push_to_wsc_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\, + Q => sig_data2wsc_valid, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5_synth is + port ( + DOBDO : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : out STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[2]\ : out STD_LOGIC; + DIN : out STD_LOGIC_VECTOR ( 0 to 0 ); + dm2linebuf_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gc1.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \gcc0.gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + lsig_cmd_loaded : in STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ : in STD_LOGIC; + hold_ff_q : in STD_LOGIC; + \out\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth"; +end Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5_synth; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5_synth is +begin +\gnbram.gnativebmg.native_blk_mem_gen\: entity work.Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_top + port map ( + DIBDI(1 downto 0) => DIBDI(1 downto 0), + DIN(0) => DIN(0), + DOBDO(0) => DOBDO(0), + E(0) => E(0), + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, + \INFERRED_GEN.cnt_i_reg[2]\ => \INFERRED_GEN.cnt_i_reg[2]\, + Q(0) => Q(0), + SR(0) => SR(0), + dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), + \gc1.count_d2_reg[7]\(7 downto 0) => \gc1.count_d2_reg[7]\(7 downto 0), + \gcc0.gc0.count_d1_reg[7]\(7 downto 0) => \gcc0.gc0.count_d1_reg[7]\(7 downto 0), + \gpregsm1.curr_fwft_state_reg[0]\ => \gpregsm1.curr_fwft_state_reg[0]\, + hold_ff_q => hold_ff_q, + lsig_cmd_loaded => lsig_cmd_loaded, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axi_mm2s_rdata(63 downto 0) => m_axi_mm2s_rdata(63 downto 0), + \out\ => \out\, + \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ => \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5_synth__parameterized0\ is + port ( + sig_data_fifo_data_out : out STD_LOGIC_VECTOR ( 65 downto 0 ); + m_axi_s2mm_aclk : in STD_LOGIC; + ram_empty_fb_i_reg : in STD_LOGIC; + WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_s_ready_out_reg : in STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + \gc1.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 7 downto 0 ); + lsig_combined_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); + DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5_synth__parameterized0\ : entity is "blk_mem_gen_v8_3_5_synth"; +end \Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5_synth__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5_synth__parameterized0\ is +begin +\gnbram.gnativebmg.native_blk_mem_gen\: entity work.\Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_top__parameterized0\ + port map ( + DIBDI(1 downto 0) => DIBDI(1 downto 0), + Q(7 downto 0) => Q(7 downto 0), + WEBWE(0) => WEBWE(0), + \gc1.count_d2_reg[7]\(7 downto 0) => \gc1.count_d2_reg[7]\(7 downto 0), + lsig_combined_data(63 downto 0) => lsig_combined_data(63 downto 0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + ram_empty_fb_i_reg => ram_empty_fb_i_reg, + sig_data_fifo_data_out(65 downto 0) => sig_data_fifo_data_out(65 downto 0), + sig_s_ready_out_reg => sig_s_ready_out_reg, + sig_stream_rst => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_fifo_generator_top is + port ( + sig_m_valid_out_reg : out STD_LOGIC; + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ : out STD_LOGIC; + FULL : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\ : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1\ : out STD_LOGIC; + fifo_dout : out STD_LOGIC_VECTOR ( 33 downto 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + s_axis_fifo_ainit_nosync_reg : in STD_LOGIC; + m_axis_mm2s_aclk : in STD_LOGIC; + \out\ : in STD_LOGIC; + lsig_0ffset_cntr : in STD_LOGIC; + mm2s_prmry_resetn : in STD_LOGIC; + mm2s_halt : in STD_LOGIC; + p_24_out : in STD_LOGIC; + hold_ff_q_reg : in STD_LOGIC; + DIN : in STD_LOGIC_VECTOR ( 15 downto 0 ); + WR_EN : in STD_LOGIC; + dm2linebuf_mm2s_tdata : in STD_LOGIC_VECTOR ( 17 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_fifo_generator_top : entity is "fifo_generator_top"; +end Arty_Z7_20_axi_vdma_0_0_fifo_generator_top; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_fifo_generator_top is +begin +\gbi.bi\: entity work.Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_builtin + port map ( + DIN(15 downto 0) => DIN(15 downto 0), + FULL => FULL, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1\, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, + WR_EN => WR_EN, + dm2linebuf_mm2s_tdata(17 downto 0) => dm2linebuf_mm2s_tdata(17 downto 0), + fifo_dout(33 downto 0) => fifo_dout(33 downto 0), + hold_ff_q_reg => hold_ff_q_reg, + lsig_0ffset_cntr => lsig_0ffset_cntr, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axis_mm2s_aclk => m_axis_mm2s_aclk, + mm2s_halt => mm2s_halt, + mm2s_prmry_resetn => mm2s_prmry_resetn, + \out\ => \out\, + p_24_out => p_24_out, + s_axis_fifo_ainit_nosync_reg => s_axis_fifo_ainit_nosync_reg, + sig_m_valid_out_reg => sig_m_valid_out_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized0\ is + port ( + FULL : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 12 downto 0 ); + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]\ : out STD_LOGIC; + DOUT : out STD_LOGIC_VECTOR ( 8 downto 0 ); + EMPTY : out STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\ : out STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\ : out STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\ : out STD_LOGIC; + strm_not_finished_no_dwidth : out STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); + s_axis_s2mm_aclk : in STD_LOGIC; + sig_reset_reg : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + M_VALID : in STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\ : in STD_LOGIC; + s2mm_fsync_out_i : in STD_LOGIC; + \out\ : in STD_LOGIC; + p_3_out : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 6 downto 0 ); + \vsize_vid_reg[12]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : in STD_LOGIC; + minusOp_1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0\ : in STD_LOGIC; + s2mm_strm_wready : in STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + DIN : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\ : in STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + minusOp : in STD_LOGIC_VECTOR ( 11 downto 0 ); + RD_EN : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized0\ : entity is "fifo_generator_top"; +end \Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized0\ is +begin +\gbi.bi\: entity work.\Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_builtin__parameterized0\ + port map ( + D(12 downto 0) => D(12 downto 0), + DIN(8 downto 0) => DIN(8 downto 0), + DOUT(8 downto 0) => DOUT(8 downto 0), + EMPTY => EMPTY, + FULL => FULL, + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\, + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\(12 downto 0) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\(12 downto 0), + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]\ => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]\, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0\ => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0\, + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\ => \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0]\(0) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0]\(0), + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\(12 downto 0) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\(12 downto 0), + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\, + M_VALID => M_VALID, + Q(6 downto 0) => Q(6 downto 0), + RD_EN => RD_EN, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + minusOp(11 downto 0) => minusOp(11 downto 0), + minusOp_1(11 downto 0) => minusOp_1(11 downto 0), + \out\ => \out\, + p_3_out => p_3_out, + s2mm_fsync_out_i => s2mm_fsync_out_i, + s2mm_strm_wready => s2mm_strm_wready, + s_axis_s2mm_aclk => s_axis_s2mm_aclk, + sig_reset_reg => sig_reset_reg, + strm_not_finished_no_dwidth => strm_not_finished_no_dwidth, + \vsize_vid_reg[12]\(12 downto 0) => \vsize_vid_reg[12]\(12 downto 0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized2\ is + port ( + hold_ff_q_reg : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_xfer_is_seq_reg_reg : out STD_LOGIC_VECTOR ( 9 downto 0 ); + \sig_child_addr_cntr_lsh_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + S : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \sig_xfer_len_reg_reg[4]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \sig_xfer_len_reg_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_xfer_is_seq_reg_reg_0 : out STD_LOGIC; + sig_xfer_cmd_cmplt_reg0 : out STD_LOGIC; + sig_sf2pcc_xfer_valid : out STD_LOGIC; + sig_ibtt2dre_tready : out STD_LOGIC; + sig_csm_state_ns1 : out STD_LOGIC; + \gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \gpr1.dout_i_reg[1]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + O : out STD_LOGIC_VECTOR ( 3 downto 0 ); + CO : out STD_LOGIC_VECTOR ( 0 to 0 ); + \sig_child_addr_cntr_lsh_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + p_32_out : in STD_LOGIC; + hold_ff_q : in STD_LOGIC; + sig_adjusted_addr_incr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + sig_clr_dbc_reg_reg : in STD_LOGIC; + sig_csm_pop_child_cmd : in STD_LOGIC; + sig_child_qual_first_of_2 : in STD_LOGIC; + sig_child_qual_error_reg : in STD_LOGIC; + lsig_packer_full : in STD_LOGIC; + ram_full_i_reg : in STD_LOGIC; + \gpr1.dout_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \gpr1.dout_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + sig_child_addr_cntr_lsh_reg : in STD_LOGIC_VECTOR ( 2 downto 0 ); + p_0_out : in STD_LOGIC_VECTOR ( 10 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized2\ : entity is "fifo_generator_top"; +end \Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized2\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized2\ is +begin +\grf.rf\: entity work.\Arty_Z7_20_axi_vdma_0_0_fifo_generator_ramfifo__parameterized0\ + port map ( + CO(0) => CO(0), + D(2 downto 0) => D(2 downto 0), + E(0) => E(0), + O(3 downto 0) => O(3 downto 0), + S(3 downto 0) => S(3 downto 0), + \gpr1.dout_i_reg[1]\(2 downto 0) => \gpr1.dout_i_reg[1]\(2 downto 0), + \gpr1.dout_i_reg[1]_0\(2 downto 0) => \gpr1.dout_i_reg[1]_0\(2 downto 0), + \gpr1.dout_i_reg[3]\(3 downto 0) => \gpr1.dout_i_reg[3]\(3 downto 0), + \gpr1.dout_i_reg[7]\(3 downto 0) => \gpr1.dout_i_reg[7]\(3 downto 0), + hold_ff_q => hold_ff_q, + hold_ff_q_reg => hold_ff_q_reg, + lsig_packer_full => lsig_packer_full, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + p_0_out(10 downto 0) => p_0_out(10 downto 0), + p_32_out => p_32_out, + ram_full_i_reg => ram_full_i_reg, + sig_adjusted_addr_incr(8 downto 0) => sig_adjusted_addr_incr(8 downto 0), + sig_child_addr_cntr_lsh_reg(2 downto 0) => sig_child_addr_cntr_lsh_reg(2 downto 0), + \sig_child_addr_cntr_lsh_reg[11]\(0) => \sig_child_addr_cntr_lsh_reg[11]\(0), + \sig_child_addr_cntr_lsh_reg[7]\(3 downto 0) => \sig_child_addr_cntr_lsh_reg[7]\(3 downto 0), + sig_child_qual_error_reg => sig_child_qual_error_reg, + sig_child_qual_first_of_2 => sig_child_qual_first_of_2, + sig_clr_dbc_reg_reg => sig_clr_dbc_reg_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_csm_pop_child_cmd => sig_csm_pop_child_cmd, + sig_csm_state_ns1 => sig_csm_state_ns1, + sig_ibtt2dre_tready => sig_ibtt2dre_tready, + sig_sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid, + sig_stream_rst => sig_stream_rst, + sig_xfer_cmd_cmplt_reg0 => sig_xfer_cmd_cmplt_reg0, + sig_xfer_is_seq_reg_reg(9 downto 0) => sig_xfer_is_seq_reg_reg(9 downto 0), + sig_xfer_is_seq_reg_reg_0 => sig_xfer_is_seq_reg_reg_0, + \sig_xfer_len_reg_reg[4]\(3 downto 0) => \sig_xfer_len_reg_reg[4]\(3 downto 0), + \sig_xfer_len_reg_reg[5]\(0) => \sig_xfer_len_reg_reg[5]\(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_s2mm_realign is + port ( + \sig_data_skid_reg_reg[7]\ : out STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[0]\ : out STD_LOGIC; + sig_init_reg2 : out STD_LOGIC; + sig_dre2ibtt_tstrb : out STD_LOGIC; + \INCLUDE_PACKING.lsig_first_dbeat_reg\ : out STD_LOGIC; + \sig_byte_cntr_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_dre2ibtt_tlast : out STD_LOGIC; + RD_EN : out STD_LOGIC; + sig_dre2ibtt_eop : out STD_LOGIC; + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + \sig_byte_cntr_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\ : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0]\ : out STD_LOGIC; + sig_inhibit_rdy_n : out STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]\ : out STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_init_reg : in STD_LOGIC; + \INCLUDE_PACKING.lsig_first_dbeat_reg_0\ : in STD_LOGIC; + DOUT : in STD_LOGIC_VECTOR ( 8 downto 0 ); + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + EMPTY : in STD_LOGIC; + sig_ibtt2dre_tready : in STD_LOGIC; + sig_clr_dbc_reg : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + p_9_out_0 : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0\ : in STD_LOGIC; + p_0_in : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0\ : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 21 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_s2mm_realign : entity is "axi_datamover_s2mm_realign"; +end Arty_Z7_20_axi_vdma_0_0_axi_datamover_s2mm_realign; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_s2mm_realign is + signal \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_good_tlast_dbeat37_out__0\ : STD_LOGIC; + signal \GEN_INCLUDE_SCATTER.I_S2MM_SCATTER_n_11\ : STD_LOGIC; + signal \GEN_INCLUDE_SCATTER.I_S2MM_SCATTER_n_30\ : STD_LOGIC; + signal I_DRE_CNTL_FIFO_n_24 : STD_LOGIC; + signal I_DRE_CNTL_FIFO_n_27 : STD_LOGIC; + signal I_DRE_CNTL_FIFO_n_28 : STD_LOGIC; + signal I_DRE_CNTL_FIFO_n_29 : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal lsig_cmd_fetch_pause : STD_LOGIC; + signal p_7_out : STD_LOGIC; + signal sig_cmd_fifo_data_out : STD_LOGIC_VECTOR ( 28 downto 6 ); + signal sig_cmdcntl_sm_state : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute RTL_KEEP : string; + attribute RTL_KEEP of sig_cmdcntl_sm_state : signal is "yes"; + signal sig_need_cmd_flush : STD_LOGIC; + signal sig_rd_empty : STD_LOGIC; + signal sig_sm_ld_dre_cmd : STD_LOGIC; + signal sig_sm_ld_dre_cmd_ns : STD_LOGIC; + signal sig_sm_pop_cmd_fifo : STD_LOGIC; + signal sig_sm_pop_cmd_fifo_i_2_n_0 : STD_LOGIC; + signal sig_sm_pop_cmd_fifo_ns : STD_LOGIC; + attribute KEEP : string; + attribute KEEP of \FSM_sequential_sig_cmdcntl_sm_state_reg[0]\ : label is "yes"; + attribute KEEP of \FSM_sequential_sig_cmdcntl_sm_state_reg[1]\ : label is "yes"; + attribute KEEP of \FSM_sequential_sig_cmdcntl_sm_state_reg[2]\ : label is "yes"; +begin + Q(2 downto 0) <= \^q\(2 downto 0); +\FSM_sequential_sig_cmdcntl_sm_state_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => I_DRE_CNTL_FIFO_n_29, + Q => sig_cmdcntl_sm_state(0), + R => sig_stream_rst + ); +\FSM_sequential_sig_cmdcntl_sm_state_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => I_DRE_CNTL_FIFO_n_28, + Q => sig_cmdcntl_sm_state(1), + R => sig_stream_rst + ); +\FSM_sequential_sig_cmdcntl_sm_state_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => I_DRE_CNTL_FIFO_n_27, + Q => sig_cmdcntl_sm_state(2), + R => sig_stream_rst + ); +\GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => I_DRE_CNTL_FIFO_n_24, + Q => lsig_cmd_fetch_pause, + R => '0' + ); +\GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_INCLUDE_SCATTER.I_S2MM_SCATTER_n_30\, + Q => sig_need_cmd_flush, + R => '0' + ); +\GEN_INCLUDE_SCATTER.I_S2MM_SCATTER\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover_s2mm_scatter + port map ( + DOUT(8 downto 0) => DOUT(8 downto 0), + EMPTY => EMPTY, + \FSM_sequential_sig_cmdcntl_sm_state_reg[0]\ => \GEN_INCLUDE_SCATTER.I_S2MM_SCATTER_n_11\, + \GEN_ENABLE_INDET_BTT.sig_need_cmd_flush_reg\ => \GEN_INCLUDE_SCATTER.I_S2MM_SCATTER_n_30\, + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1]\(1 downto 0) => \^q\(1 downto 0), + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1]\(1 downto 0) => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1]\(1 downto 0), + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1]\(1 downto 0) => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1]\(1 downto 0), + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1]\(1 downto 0) => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1]\(1 downto 0), + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1]\(1 downto 0) => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1]\(1 downto 0), + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1]\(1 downto 0) => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1]\(1 downto 0), + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1]\(1 downto 0) => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1]\(1 downto 0), + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1]\(1 downto 0) => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1]\(1 downto 0), + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7]\(7 downto 0) => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7]\(7 downto 0), + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1]\(1 downto 0) => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1]\(1 downto 0), + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0]\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\(1 downto 0) => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\(1 downto 0), + \INCLUDE_PACKING.lsig_first_dbeat_reg\ => \INCLUDE_PACKING.lsig_first_dbeat_reg\, + \INCLUDE_PACKING.lsig_first_dbeat_reg_0\ => \INCLUDE_PACKING.lsig_first_dbeat_reg_0\, + Q(0) => sig_rd_empty, + RD_EN => RD_EN, + SR(0) => SR(0), + lsig_cmd_fetch_pause => lsig_cmd_fetch_pause, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\(16) => sig_cmd_fifo_data_out(23), + \out\(15 downto 0) => sig_cmd_fifo_data_out(21 downto 6), + p_0_in => p_0_in, + p_7_out => p_7_out, + \sig_byte_cntr_reg[0]\ => \sig_byte_cntr_reg[0]\(0), + \sig_byte_cntr_reg[3]\(0) => \sig_byte_cntr_reg[3]\(0), + sig_clr_dbc_reg => sig_clr_dbc_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + \sig_data_skid_reg_reg[7]\ => \sig_data_skid_reg_reg[7]\, + sig_dre2ibtt_eop_reg_reg => sig_dre2ibtt_eop, + sig_dre2ibtt_tlast => sig_dre2ibtt_tlast, + sig_dre2ibtt_tstrb => sig_dre2ibtt_tstrb, + \sig_good_tlast_dbeat37_out__0\ => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_good_tlast_dbeat37_out__0\, + sig_ibtt2dre_tready => sig_ibtt2dre_tready, + sig_init_reg => sig_init_reg, + sig_need_cmd_flush => sig_need_cmd_flush, + sig_sm_ld_dre_cmd => sig_sm_ld_dre_cmd, + sig_sm_pop_cmd_fifo => sig_sm_pop_cmd_fifo, + sig_stream_rst => sig_stream_rst + ); +\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_sm_ld_dre_cmd, + D => sig_cmd_fifo_data_out(26), + Q => \^q\(0), + R => sig_stream_rst + ); +\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_sm_ld_dre_cmd, + D => sig_cmd_fifo_data_out(27), + Q => \^q\(1), + R => sig_stream_rst + ); +\GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => sig_sm_ld_dre_cmd, + D => sig_cmd_fifo_data_out(28), + Q => \^q\(2), + R => sig_stream_rst + ); +\INCLUDE_PACKING.lsig_0ffset_cntr[2]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \^q\(0), + I1 => \^q\(1), + I2 => \^q\(2), + O => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]\ + ); +I_DRE_CNTL_FIFO: entity work.\Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized7\ + port map ( + D(2) => I_DRE_CNTL_FIFO_n_27, + D(1) => I_DRE_CNTL_FIFO_n_28, + D(0) => I_DRE_CNTL_FIFO_n_29, + E(0) => sig_sm_ld_dre_cmd, + \FSM_sequential_sig_cmdcntl_sm_state_reg[0]\ => sig_sm_pop_cmd_fifo_i_2_n_0, + \FSM_sequential_sig_cmdcntl_sm_state_reg[2]\(2 downto 0) => sig_cmdcntl_sm_state(2 downto 0), + \GEN_ENABLE_INDET_BTT.lsig_cmd_fetch_pause_reg\ => I_DRE_CNTL_FIFO_n_24, + \INFERRED_GEN.cnt_i_reg[0]\ => \INFERRED_GEN.cnt_i_reg[0]\, + \INFERRED_GEN.cnt_i_reg[0]_0\ => sig_inhibit_rdy_n, + Q(0) => sig_rd_empty, + \in\(21 downto 0) => \in\(21 downto 0), + lsig_cmd_fetch_pause => lsig_cmd_fetch_pause, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\(19 downto 17) => sig_cmd_fifo_data_out(28 downto 26), + \out\(16) => sig_cmd_fifo_data_out(23), + \out\(15 downto 0) => sig_cmd_fifo_data_out(21 downto 6), + p_7_out => p_7_out, + p_9_out_0 => p_9_out_0, + sig_cmd_empty_reg => \GEN_INCLUDE_SCATTER.I_S2MM_SCATTER_n_11\, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + \sig_good_tlast_dbeat37_out__0\ => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_good_tlast_dbeat37_out__0\, + sig_init_reg => sig_init_reg, + sig_init_reg2 => sig_init_reg2, + sig_need_cmd_flush => sig_need_cmd_flush, + sig_sm_ld_dre_cmd_ns => sig_sm_ld_dre_cmd_ns, + sig_sm_pop_cmd_fifo => sig_sm_pop_cmd_fifo, + sig_sm_pop_cmd_fifo_ns => sig_sm_pop_cmd_fifo_ns, + sig_stream_rst => sig_stream_rst + ); +sig_sm_ld_dre_cmd_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_sm_ld_dre_cmd_ns, + Q => sig_sm_ld_dre_cmd, + R => sig_stream_rst + ); +sig_sm_pop_cmd_fifo_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => sig_cmdcntl_sm_state(0), + I1 => sig_cmdcntl_sm_state(2), + O => sig_sm_pop_cmd_fifo_i_2_n_0 + ); +sig_sm_pop_cmd_fifo_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_sm_pop_cmd_fifo_ns, + Q => sig_sm_pop_cmd_fifo, + R => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5 is + port ( + DOBDO : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : out STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[2]\ : out STD_LOGIC; + DIN : out STD_LOGIC_VECTOR ( 0 to 0 ); + dm2linebuf_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gc1.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \gcc0.gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + lsig_cmd_loaded : in STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ : in STD_LOGIC; + hold_ff_q : in STD_LOGIC; + \out\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5"; +end Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5 is +begin +inst_blk_mem_gen: entity work.Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5_synth + port map ( + DIBDI(1 downto 0) => DIBDI(1 downto 0), + DIN(0) => DIN(0), + DOBDO(0) => DOBDO(0), + E(0) => E(0), + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, + \INFERRED_GEN.cnt_i_reg[2]\ => \INFERRED_GEN.cnt_i_reg[2]\, + Q(0) => Q(0), + SR(0) => SR(0), + dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), + \gc1.count_d2_reg[7]\(7 downto 0) => \gc1.count_d2_reg[7]\(7 downto 0), + \gcc0.gc0.count_d1_reg[7]\(7 downto 0) => \gcc0.gc0.count_d1_reg[7]\(7 downto 0), + \gpregsm1.curr_fwft_state_reg[0]\ => \gpregsm1.curr_fwft_state_reg[0]\, + hold_ff_q => hold_ff_q, + lsig_cmd_loaded => lsig_cmd_loaded, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axi_mm2s_rdata(63 downto 0) => m_axi_mm2s_rdata(63 downto 0), + \out\ => \out\, + \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ => \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5__parameterized1\ is + port ( + sig_data_fifo_data_out : out STD_LOGIC_VECTOR ( 65 downto 0 ); + m_axi_s2mm_aclk : in STD_LOGIC; + ram_empty_fb_i_reg : in STD_LOGIC; + WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_s_ready_out_reg : in STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + \gc1.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 7 downto 0 ); + lsig_combined_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); + DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5__parameterized1\ : entity is "blk_mem_gen_v8_3_5"; +end \Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5__parameterized1\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5__parameterized1\ is +begin +inst_blk_mem_gen: entity work.\Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5_synth__parameterized0\ + port map ( + DIBDI(1 downto 0) => DIBDI(1 downto 0), + Q(7 downto 0) => Q(7 downto 0), + WEBWE(0) => WEBWE(0), + \gc1.count_d2_reg[7]\(7 downto 0) => \gc1.count_d2_reg[7]\(7 downto 0), + lsig_combined_data(63 downto 0) => lsig_combined_data(63 downto 0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + ram_empty_fb_i_reg => ram_empty_fb_i_reg, + sig_data_fifo_data_out(65 downto 0) => sig_data_fifo_data_out(65 downto 0), + sig_s_ready_out_reg => sig_s_ready_out_reg, + sig_stream_rst => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth is + port ( + sig_m_valid_out_reg : out STD_LOGIC; + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ : out STD_LOGIC; + FULL : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\ : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1\ : out STD_LOGIC; + fifo_dout : out STD_LOGIC_VECTOR ( 33 downto 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + s_axis_fifo_ainit_nosync_reg : in STD_LOGIC; + m_axis_mm2s_aclk : in STD_LOGIC; + \out\ : in STD_LOGIC; + lsig_0ffset_cntr : in STD_LOGIC; + mm2s_prmry_resetn : in STD_LOGIC; + mm2s_halt : in STD_LOGIC; + p_24_out : in STD_LOGIC; + hold_ff_q_reg : in STD_LOGIC; + DIN : in STD_LOGIC_VECTOR ( 15 downto 0 ); + WR_EN : in STD_LOGIC; + dm2linebuf_mm2s_tdata : in STD_LOGIC_VECTOR ( 17 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth : entity is "fifo_generator_v13_1_3_synth"; +end Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth is +begin +\gconvfifo.rf\: entity work.Arty_Z7_20_axi_vdma_0_0_fifo_generator_top + port map ( + DIN(15 downto 0) => DIN(15 downto 0), + FULL => FULL, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1\, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, + WR_EN => WR_EN, + dm2linebuf_mm2s_tdata(17 downto 0) => dm2linebuf_mm2s_tdata(17 downto 0), + fifo_dout(33 downto 0) => fifo_dout(33 downto 0), + hold_ff_q_reg => hold_ff_q_reg, + lsig_0ffset_cntr => lsig_0ffset_cntr, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axis_mm2s_aclk => m_axis_mm2s_aclk, + mm2s_halt => mm2s_halt, + mm2s_prmry_resetn => mm2s_prmry_resetn, + \out\ => \out\, + p_24_out => p_24_out, + s_axis_fifo_ainit_nosync_reg => s_axis_fifo_ainit_nosync_reg, + sig_m_valid_out_reg => sig_m_valid_out_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized0\ is + port ( + FULL : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 12 downto 0 ); + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]\ : out STD_LOGIC; + DOUT : out STD_LOGIC_VECTOR ( 8 downto 0 ); + EMPTY : out STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\ : out STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\ : out STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\ : out STD_LOGIC; + strm_not_finished_no_dwidth : out STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); + s_axis_s2mm_aclk : in STD_LOGIC; + sig_reset_reg : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + M_VALID : in STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\ : in STD_LOGIC; + s2mm_fsync_out_i : in STD_LOGIC; + \out\ : in STD_LOGIC; + p_3_out : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 6 downto 0 ); + \vsize_vid_reg[12]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : in STD_LOGIC; + minusOp_1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0\ : in STD_LOGIC; + s2mm_strm_wready : in STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + DIN : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\ : in STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + minusOp : in STD_LOGIC_VECTOR ( 11 downto 0 ); + RD_EN : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized0\ : entity is "fifo_generator_v13_1_3_synth"; +end \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized0\ is +begin +\gconvfifo.rf\: entity work.\Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized0\ + port map ( + D(12 downto 0) => D(12 downto 0), + DIN(8 downto 0) => DIN(8 downto 0), + DOUT(8 downto 0) => DOUT(8 downto 0), + EMPTY => EMPTY, + FULL => FULL, + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\, + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\(12 downto 0) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\(12 downto 0), + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]\ => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]\, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0\ => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0\, + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\ => \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0]\(0) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0]\(0), + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\(12 downto 0) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\(12 downto 0), + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\, + M_VALID => M_VALID, + Q(6 downto 0) => Q(6 downto 0), + RD_EN => RD_EN, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + minusOp(11 downto 0) => minusOp(11 downto 0), + minusOp_1(11 downto 0) => minusOp_1(11 downto 0), + \out\ => \out\, + p_3_out => p_3_out, + s2mm_fsync_out_i => s2mm_fsync_out_i, + s2mm_strm_wready => s2mm_strm_wready, + s_axis_s2mm_aclk => s_axis_s2mm_aclk, + sig_reset_reg => sig_reset_reg, + strm_not_finished_no_dwidth => strm_not_finished_no_dwidth, + \vsize_vid_reg[12]\(12 downto 0) => \vsize_vid_reg[12]\(12 downto 0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized2\ is + port ( + hold_ff_q_reg : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_xfer_is_seq_reg_reg : out STD_LOGIC_VECTOR ( 9 downto 0 ); + \sig_child_addr_cntr_lsh_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + S : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \sig_xfer_len_reg_reg[4]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \sig_xfer_len_reg_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_xfer_is_seq_reg_reg_0 : out STD_LOGIC; + sig_xfer_cmd_cmplt_reg0 : out STD_LOGIC; + sig_sf2pcc_xfer_valid : out STD_LOGIC; + sig_ibtt2dre_tready : out STD_LOGIC; + sig_csm_state_ns1 : out STD_LOGIC; + \gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \gpr1.dout_i_reg[1]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + O : out STD_LOGIC_VECTOR ( 3 downto 0 ); + CO : out STD_LOGIC_VECTOR ( 0 to 0 ); + \sig_child_addr_cntr_lsh_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + p_32_out : in STD_LOGIC; + hold_ff_q : in STD_LOGIC; + sig_adjusted_addr_incr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + sig_clr_dbc_reg_reg : in STD_LOGIC; + sig_csm_pop_child_cmd : in STD_LOGIC; + sig_child_qual_first_of_2 : in STD_LOGIC; + sig_child_qual_error_reg : in STD_LOGIC; + lsig_packer_full : in STD_LOGIC; + ram_full_i_reg : in STD_LOGIC; + \gpr1.dout_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \gpr1.dout_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + sig_child_addr_cntr_lsh_reg : in STD_LOGIC_VECTOR ( 2 downto 0 ); + p_0_out : in STD_LOGIC_VECTOR ( 10 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized2\ : entity is "fifo_generator_v13_1_3_synth"; +end \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized2\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized2\ is +begin +\gconvfifo.rf\: entity work.\Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized2\ + port map ( + CO(0) => CO(0), + D(2 downto 0) => D(2 downto 0), + E(0) => E(0), + O(3 downto 0) => O(3 downto 0), + S(3 downto 0) => S(3 downto 0), + \gpr1.dout_i_reg[1]\(2 downto 0) => \gpr1.dout_i_reg[1]\(2 downto 0), + \gpr1.dout_i_reg[1]_0\(2 downto 0) => \gpr1.dout_i_reg[1]_0\(2 downto 0), + \gpr1.dout_i_reg[3]\(3 downto 0) => \gpr1.dout_i_reg[3]\(3 downto 0), + \gpr1.dout_i_reg[7]\(3 downto 0) => \gpr1.dout_i_reg[7]\(3 downto 0), + hold_ff_q => hold_ff_q, + hold_ff_q_reg => hold_ff_q_reg, + lsig_packer_full => lsig_packer_full, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + p_0_out(10 downto 0) => p_0_out(10 downto 0), + p_32_out => p_32_out, + ram_full_i_reg => ram_full_i_reg, + sig_adjusted_addr_incr(8 downto 0) => sig_adjusted_addr_incr(8 downto 0), + sig_child_addr_cntr_lsh_reg(2 downto 0) => sig_child_addr_cntr_lsh_reg(2 downto 0), + \sig_child_addr_cntr_lsh_reg[11]\(0) => \sig_child_addr_cntr_lsh_reg[11]\(0), + \sig_child_addr_cntr_lsh_reg[7]\(3 downto 0) => \sig_child_addr_cntr_lsh_reg[7]\(3 downto 0), + sig_child_qual_error_reg => sig_child_qual_error_reg, + sig_child_qual_first_of_2 => sig_child_qual_first_of_2, + sig_clr_dbc_reg_reg => sig_clr_dbc_reg_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_csm_pop_child_cmd => sig_csm_pop_child_cmd, + sig_csm_state_ns1 => sig_csm_state_ns1, + sig_ibtt2dre_tready => sig_ibtt2dre_tready, + sig_sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid, + sig_stream_rst => sig_stream_rst, + sig_xfer_cmd_cmplt_reg0 => sig_xfer_cmd_cmplt_reg0, + sig_xfer_is_seq_reg_reg(9 downto 0) => sig_xfer_is_seq_reg_reg(9 downto 0), + sig_xfer_is_seq_reg_reg_0 => sig_xfer_is_seq_reg_reg_0, + \sig_xfer_len_reg_reg[4]\(3 downto 0) => \sig_xfer_len_reg_reg[4]\(3 downto 0), + \sig_xfer_len_reg_reg[5]\(0) => \sig_xfer_len_reg_reg[5]\(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3 is + port ( + sig_m_valid_out_reg : out STD_LOGIC; + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ : out STD_LOGIC; + FULL : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\ : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1\ : out STD_LOGIC; + fifo_dout : out STD_LOGIC_VECTOR ( 33 downto 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + s_axis_fifo_ainit_nosync_reg : in STD_LOGIC; + m_axis_mm2s_aclk : in STD_LOGIC; + \out\ : in STD_LOGIC; + lsig_0ffset_cntr : in STD_LOGIC; + mm2s_prmry_resetn : in STD_LOGIC; + mm2s_halt : in STD_LOGIC; + p_24_out : in STD_LOGIC; + hold_ff_q_reg : in STD_LOGIC; + DIN : in STD_LOGIC_VECTOR ( 15 downto 0 ); + WR_EN : in STD_LOGIC; + dm2linebuf_mm2s_tdata : in STD_LOGIC_VECTOR ( 17 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3 : entity is "fifo_generator_v13_1_3"; +end Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3 is +begin +inst_fifo_gen: entity work.Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth + port map ( + DIN(15 downto 0) => DIN(15 downto 0), + FULL => FULL, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1\, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, + WR_EN => WR_EN, + dm2linebuf_mm2s_tdata(17 downto 0) => dm2linebuf_mm2s_tdata(17 downto 0), + fifo_dout(33 downto 0) => fifo_dout(33 downto 0), + hold_ff_q_reg => hold_ff_q_reg, + lsig_0ffset_cntr => lsig_0ffset_cntr, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axis_mm2s_aclk => m_axis_mm2s_aclk, + mm2s_halt => mm2s_halt, + mm2s_prmry_resetn => mm2s_prmry_resetn, + \out\ => \out\, + p_24_out => p_24_out, + s_axis_fifo_ainit_nosync_reg => s_axis_fifo_ainit_nosync_reg, + sig_m_valid_out_reg => sig_m_valid_out_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized0\ is + port ( + FULL : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 12 downto 0 ); + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]\ : out STD_LOGIC; + DOUT : out STD_LOGIC_VECTOR ( 8 downto 0 ); + EMPTY : out STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\ : out STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\ : out STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\ : out STD_LOGIC; + strm_not_finished_no_dwidth : out STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); + s_axis_s2mm_aclk : in STD_LOGIC; + sig_reset_reg : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + M_VALID : in STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\ : in STD_LOGIC; + s2mm_fsync_out_i : in STD_LOGIC; + \out\ : in STD_LOGIC; + p_3_out : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 6 downto 0 ); + \vsize_vid_reg[12]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : in STD_LOGIC; + minusOp_1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0\ : in STD_LOGIC; + s2mm_strm_wready : in STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + DIN : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\ : in STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + minusOp : in STD_LOGIC_VECTOR ( 11 downto 0 ); + RD_EN : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized0\ : entity is "fifo_generator_v13_1_3"; +end \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized0\ is +begin +inst_fifo_gen: entity work.\Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized0\ + port map ( + D(12 downto 0) => D(12 downto 0), + DIN(8 downto 0) => DIN(8 downto 0), + DOUT(8 downto 0) => DOUT(8 downto 0), + EMPTY => EMPTY, + FULL => FULL, + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\, + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\(12 downto 0) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\(12 downto 0), + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]\ => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]\, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0\ => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0\, + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\ => \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0]\(0) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0]\(0), + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\(12 downto 0) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\(12 downto 0), + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\, + M_VALID => M_VALID, + Q(6 downto 0) => Q(6 downto 0), + RD_EN => RD_EN, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + minusOp(11 downto 0) => minusOp(11 downto 0), + minusOp_1(11 downto 0) => minusOp_1(11 downto 0), + \out\ => \out\, + p_3_out => p_3_out, + s2mm_fsync_out_i => s2mm_fsync_out_i, + s2mm_strm_wready => s2mm_strm_wready, + s_axis_s2mm_aclk => s_axis_s2mm_aclk, + sig_reset_reg => sig_reset_reg, + strm_not_finished_no_dwidth => strm_not_finished_no_dwidth, + \vsize_vid_reg[12]\(12 downto 0) => \vsize_vid_reg[12]\(12 downto 0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized2\ is + port ( + hold_ff_q_reg : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_xfer_is_seq_reg_reg : out STD_LOGIC_VECTOR ( 9 downto 0 ); + \sig_child_addr_cntr_lsh_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + S : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \sig_xfer_len_reg_reg[4]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \sig_xfer_len_reg_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_xfer_is_seq_reg_reg_0 : out STD_LOGIC; + sig_xfer_cmd_cmplt_reg0 : out STD_LOGIC; + sig_sf2pcc_xfer_valid : out STD_LOGIC; + sig_ibtt2dre_tready : out STD_LOGIC; + sig_csm_state_ns1 : out STD_LOGIC; + \gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \gpr1.dout_i_reg[1]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + O : out STD_LOGIC_VECTOR ( 3 downto 0 ); + CO : out STD_LOGIC_VECTOR ( 0 to 0 ); + \sig_child_addr_cntr_lsh_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + p_32_out : in STD_LOGIC; + hold_ff_q : in STD_LOGIC; + sig_adjusted_addr_incr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + sig_clr_dbc_reg_reg : in STD_LOGIC; + sig_csm_pop_child_cmd : in STD_LOGIC; + sig_child_qual_first_of_2 : in STD_LOGIC; + sig_child_qual_error_reg : in STD_LOGIC; + lsig_packer_full : in STD_LOGIC; + ram_full_i_reg : in STD_LOGIC; + \gpr1.dout_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \gpr1.dout_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + sig_child_addr_cntr_lsh_reg : in STD_LOGIC_VECTOR ( 2 downto 0 ); + p_0_out : in STD_LOGIC_VECTOR ( 10 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized2\ : entity is "fifo_generator_v13_1_3"; +end \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized2\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized2\ is +begin +inst_fifo_gen: entity work.\Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized2\ + port map ( + CO(0) => CO(0), + D(2 downto 0) => D(2 downto 0), + E(0) => E(0), + O(3 downto 0) => O(3 downto 0), + S(3 downto 0) => S(3 downto 0), + \gpr1.dout_i_reg[1]\(2 downto 0) => \gpr1.dout_i_reg[1]\(2 downto 0), + \gpr1.dout_i_reg[1]_0\(2 downto 0) => \gpr1.dout_i_reg[1]_0\(2 downto 0), + \gpr1.dout_i_reg[3]\(3 downto 0) => \gpr1.dout_i_reg[3]\(3 downto 0), + \gpr1.dout_i_reg[7]\(3 downto 0) => \gpr1.dout_i_reg[7]\(3 downto 0), + hold_ff_q => hold_ff_q, + hold_ff_q_reg => hold_ff_q_reg, + lsig_packer_full => lsig_packer_full, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + p_0_out(10 downto 0) => p_0_out(10 downto 0), + p_32_out => p_32_out, + ram_full_i_reg => ram_full_i_reg, + sig_adjusted_addr_incr(8 downto 0) => sig_adjusted_addr_incr(8 downto 0), + sig_child_addr_cntr_lsh_reg(2 downto 0) => sig_child_addr_cntr_lsh_reg(2 downto 0), + \sig_child_addr_cntr_lsh_reg[11]\(0) => \sig_child_addr_cntr_lsh_reg[11]\(0), + \sig_child_addr_cntr_lsh_reg[7]\(3 downto 0) => \sig_child_addr_cntr_lsh_reg[7]\(3 downto 0), + sig_child_qual_error_reg => sig_child_qual_error_reg, + sig_child_qual_first_of_2 => sig_child_qual_first_of_2, + sig_clr_dbc_reg_reg => sig_clr_dbc_reg_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_csm_pop_child_cmd => sig_csm_pop_child_cmd, + sig_csm_state_ns1 => sig_csm_state_ns1, + sig_ibtt2dre_tready => sig_ibtt2dre_tready, + sig_sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid, + sig_stream_rst => sig_stream_rst, + sig_xfer_cmd_cmplt_reg0 => sig_xfer_cmd_cmplt_reg0, + sig_xfer_is_seq_reg_reg(9 downto 0) => sig_xfer_is_seq_reg_reg(9 downto 0), + sig_xfer_is_seq_reg_reg_0 => sig_xfer_is_seq_reg_reg_0, + \sig_xfer_len_reg_reg[4]\(3 downto 0) => \sig_xfer_len_reg_reg[4]\(3 downto 0), + \sig_xfer_len_reg_reg[5]\(0) => \sig_xfer_len_reg_reg[5]\(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_memory is + port ( + DOBDO : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : out STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[2]\ : out STD_LOGIC; + DIN : out STD_LOGIC_VECTOR ( 0 to 0 ); + dm2linebuf_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gc1.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \gcc0.gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + lsig_cmd_loaded : in STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ : in STD_LOGIC; + hold_ff_q : in STD_LOGIC; + \out\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_memory : entity is "memory"; +end Arty_Z7_20_axi_vdma_0_0_memory; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_memory is +begin +\gbm.gbmg.gbmgb.ngecc.bmg\: entity work.Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5 + port map ( + DIBDI(1 downto 0) => DIBDI(1 downto 0), + DIN(0) => DIN(0), + DOBDO(0) => DOBDO(0), + E(0) => E(0), + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, + \INFERRED_GEN.cnt_i_reg[2]\ => \INFERRED_GEN.cnt_i_reg[2]\, + Q(0) => Q(0), + SR(0) => SR(0), + dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), + \gc1.count_d2_reg[7]\(7 downto 0) => \gc1.count_d2_reg[7]\(7 downto 0), + \gcc0.gc0.count_d1_reg[7]\(7 downto 0) => \gcc0.gc0.count_d1_reg[7]\(7 downto 0), + \gpregsm1.curr_fwft_state_reg[0]\ => \gpregsm1.curr_fwft_state_reg[0]\, + hold_ff_q => hold_ff_q, + lsig_cmd_loaded => lsig_cmd_loaded, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axi_mm2s_rdata(63 downto 0) => m_axi_mm2s_rdata(63 downto 0), + \out\ => \out\, + \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ => \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_memory__parameterized1\ is + port ( + sig_data_fifo_data_out : out STD_LOGIC_VECTOR ( 65 downto 0 ); + m_axi_s2mm_aclk : in STD_LOGIC; + ram_empty_fb_i_reg : in STD_LOGIC; + WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_s_ready_out_reg : in STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + \gc1.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 7 downto 0 ); + lsig_combined_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); + DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_memory__parameterized1\ : entity is "memory"; +end \Arty_Z7_20_axi_vdma_0_0_memory__parameterized1\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_memory__parameterized1\ is +begin +\gbm.gbmg.gbmgb.ngecc.bmg\: entity work.\Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5__parameterized1\ + port map ( + DIBDI(1 downto 0) => DIBDI(1 downto 0), + Q(7 downto 0) => Q(7 downto 0), + WEBWE(0) => WEBWE(0), + \gc1.count_d2_reg[7]\(7 downto 0) => \gc1.count_d2_reg[7]\(7 downto 0), + lsig_combined_data(63 downto 0) => lsig_combined_data(63 downto 0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + ram_empty_fb_i_reg => ram_empty_fb_i_reg, + sig_data_fifo_data_out(65 downto 0) => sig_data_fifo_data_out(65 downto 0), + sig_s_ready_out_reg => sig_s_ready_out_reg, + sig_stream_rst => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_afifo_builtin is + port ( + sig_m_valid_out_reg : out STD_LOGIC; + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ : out STD_LOGIC; + FULL : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\ : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1\ : out STD_LOGIC; + fifo_dout : out STD_LOGIC_VECTOR ( 33 downto 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + s_axis_fifo_ainit_nosync_reg : in STD_LOGIC; + m_axis_mm2s_aclk : in STD_LOGIC; + \out\ : in STD_LOGIC; + lsig_0ffset_cntr : in STD_LOGIC; + mm2s_prmry_resetn : in STD_LOGIC; + mm2s_halt : in STD_LOGIC; + p_24_out : in STD_LOGIC; + hold_ff_q_reg : in STD_LOGIC; + DIN : in STD_LOGIC_VECTOR ( 15 downto 0 ); + WR_EN : in STD_LOGIC; + dm2linebuf_mm2s_tdata : in STD_LOGIC_VECTOR ( 17 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_afifo_builtin : entity is "axi_vdma_afifo_builtin"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_afifo_builtin; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_afifo_builtin is +begin +fg_builtin_fifo_inst: entity work.Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3 + port map ( + DIN(15 downto 0) => DIN(15 downto 0), + FULL => FULL, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1\, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, + WR_EN => WR_EN, + dm2linebuf_mm2s_tdata(17 downto 0) => dm2linebuf_mm2s_tdata(17 downto 0), + fifo_dout(33 downto 0) => fifo_dout(33 downto 0), + hold_ff_q_reg => hold_ff_q_reg, + lsig_0ffset_cntr => lsig_0ffset_cntr, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axis_mm2s_aclk => m_axis_mm2s_aclk, + mm2s_halt => mm2s_halt, + mm2s_prmry_resetn => mm2s_prmry_resetn, + \out\ => \out\, + p_24_out => p_24_out, + s_axis_fifo_ainit_nosync_reg => s_axis_fifo_ainit_nosync_reg, + sig_m_valid_out_reg => sig_m_valid_out_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_axi_vdma_afifo_builtin__parameterized0\ is + port ( + FULL : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 12 downto 0 ); + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]\ : out STD_LOGIC; + DOUT : out STD_LOGIC_VECTOR ( 8 downto 0 ); + EMPTY : out STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\ : out STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\ : out STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\ : out STD_LOGIC; + strm_not_finished_no_dwidth : out STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); + s_axis_s2mm_aclk : in STD_LOGIC; + sig_reset_reg : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + M_VALID : in STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\ : in STD_LOGIC; + s2mm_fsync_out_i : in STD_LOGIC; + \out\ : in STD_LOGIC; + p_3_out : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 6 downto 0 ); + \vsize_vid_reg[12]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ : in STD_LOGIC; + minusOp_1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0\ : in STD_LOGIC; + s2mm_strm_wready : in STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + DIN : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\ : in STD_LOGIC; + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + minusOp : in STD_LOGIC_VECTOR ( 11 downto 0 ); + RD_EN : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_axi_vdma_afifo_builtin__parameterized0\ : entity is "axi_vdma_afifo_builtin"; +end \Arty_Z7_20_axi_vdma_0_0_axi_vdma_afifo_builtin__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_axi_vdma_afifo_builtin__parameterized0\ is +begin +fg_builtin_fifo_inst: entity work.\Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized0\ + port map ( + D(12 downto 0) => D(12 downto 0), + DIN(8 downto 0) => DIN(8 downto 0), + DOUT(8 downto 0) => DOUT(8 downto 0), + EMPTY => EMPTY, + FULL => FULL, + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ => \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\, + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\(12 downto 0) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\(12 downto 0), + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]\ => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]\, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0\ => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0\, + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\ => \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0]\(0) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0]\(0), + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\(12 downto 0) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\(12 downto 0), + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\, + M_VALID => M_VALID, + Q(6 downto 0) => Q(6 downto 0), + RD_EN => RD_EN, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + minusOp(11 downto 0) => minusOp(11 downto 0), + minusOp_1(11 downto 0) => minusOp_1(11 downto 0), + \out\ => \out\, + p_3_out => p_3_out, + s2mm_fsync_out_i => s2mm_fsync_out_i, + s2mm_strm_wready => s2mm_strm_wready, + s_axis_s2mm_aclk => s_axis_s2mm_aclk, + sig_reset_reg => sig_reset_reg, + strm_not_finished_no_dwidth => strm_not_finished_no_dwidth, + \vsize_vid_reg[12]\(12 downto 0) => \vsize_vid_reg[12]\(12 downto 0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_sync_fifo_fg__parameterized0\ is + port ( + hold_ff_q_reg : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_xfer_is_seq_reg_reg : out STD_LOGIC_VECTOR ( 9 downto 0 ); + \sig_child_addr_cntr_lsh_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + S : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \sig_xfer_len_reg_reg[4]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \sig_xfer_len_reg_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_xfer_is_seq_reg_reg_0 : out STD_LOGIC; + sig_xfer_cmd_cmplt_reg0 : out STD_LOGIC; + sig_sf2pcc_xfer_valid : out STD_LOGIC; + sig_ibtt2dre_tready : out STD_LOGIC; + sig_csm_state_ns1 : out STD_LOGIC; + \gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \gpr1.dout_i_reg[1]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + O : out STD_LOGIC_VECTOR ( 3 downto 0 ); + CO : out STD_LOGIC_VECTOR ( 0 to 0 ); + \sig_child_addr_cntr_lsh_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + p_32_out : in STD_LOGIC; + hold_ff_q : in STD_LOGIC; + sig_adjusted_addr_incr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + sig_clr_dbc_reg_reg : in STD_LOGIC; + sig_csm_pop_child_cmd : in STD_LOGIC; + sig_child_qual_first_of_2 : in STD_LOGIC; + sig_child_qual_error_reg : in STD_LOGIC; + lsig_packer_full : in STD_LOGIC; + ram_full_i_reg : in STD_LOGIC; + \gpr1.dout_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \gpr1.dout_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + sig_child_addr_cntr_lsh_reg : in STD_LOGIC_VECTOR ( 2 downto 0 ); + p_0_out : in STD_LOGIC_VECTOR ( 10 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_sync_fifo_fg__parameterized0\ : entity is "sync_fifo_fg"; +end \Arty_Z7_20_axi_vdma_0_0_sync_fifo_fg__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_sync_fifo_fg__parameterized0\ is +begin +\FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM\: entity work.\Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized2\ + port map ( + CO(0) => CO(0), + D(2 downto 0) => D(2 downto 0), + E(0) => E(0), + O(3 downto 0) => O(3 downto 0), + S(3 downto 0) => S(3 downto 0), + \gpr1.dout_i_reg[1]\(2 downto 0) => \gpr1.dout_i_reg[1]\(2 downto 0), + \gpr1.dout_i_reg[1]_0\(2 downto 0) => \gpr1.dout_i_reg[1]_0\(2 downto 0), + \gpr1.dout_i_reg[3]\(3 downto 0) => \gpr1.dout_i_reg[3]\(3 downto 0), + \gpr1.dout_i_reg[7]\(3 downto 0) => \gpr1.dout_i_reg[7]\(3 downto 0), + hold_ff_q => hold_ff_q, + hold_ff_q_reg => hold_ff_q_reg, + lsig_packer_full => lsig_packer_full, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + p_0_out(10 downto 0) => p_0_out(10 downto 0), + p_32_out => p_32_out, + ram_full_i_reg => ram_full_i_reg, + sig_adjusted_addr_incr(8 downto 0) => sig_adjusted_addr_incr(8 downto 0), + sig_child_addr_cntr_lsh_reg(2 downto 0) => sig_child_addr_cntr_lsh_reg(2 downto 0), + \sig_child_addr_cntr_lsh_reg[11]\(0) => \sig_child_addr_cntr_lsh_reg[11]\(0), + \sig_child_addr_cntr_lsh_reg[7]\(3 downto 0) => \sig_child_addr_cntr_lsh_reg[7]\(3 downto 0), + sig_child_qual_error_reg => sig_child_qual_error_reg, + sig_child_qual_first_of_2 => sig_child_qual_first_of_2, + sig_clr_dbc_reg_reg => sig_clr_dbc_reg_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_csm_pop_child_cmd => sig_csm_pop_child_cmd, + sig_csm_state_ns1 => sig_csm_state_ns1, + sig_ibtt2dre_tready => sig_ibtt2dre_tready, + sig_sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid, + sig_stream_rst => sig_stream_rst, + sig_xfer_cmd_cmplt_reg0 => sig_xfer_cmd_cmplt_reg0, + sig_xfer_is_seq_reg_reg(9 downto 0) => sig_xfer_is_seq_reg_reg(9 downto 0), + sig_xfer_is_seq_reg_reg_0 => sig_xfer_is_seq_reg_reg_0, + \sig_xfer_len_reg_reg[4]\(3 downto 0) => \sig_xfer_len_reg_reg[4]\(3 downto 0), + \sig_xfer_len_reg_reg[5]\(0) => \sig_xfer_len_reg_reg[5]\(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_fifo_generator_ramfifo is + port ( + DOBDO : out STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : out STD_LOGIC; + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC; + sig_ok_to_post_rd_addr_reg : out STD_LOGIC; + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : out STD_LOGIC; + hold_ff_q_reg : out STD_LOGIC; + \gc1.count_reg[7]\ : out STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[2]\ : out STD_LOGIC; + DIN : out STD_LOGIC_VECTOR ( 0 to 0 ); + \sig_user_skid_reg_reg[0]\ : out STD_LOGIC; + dm2linebuf_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ); + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_posted_to_axi_2_reg : in STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + lsig_cmd_loaded : in STD_LOGIC; + hold_ff_q : in STD_LOGIC; + ram_full_i_reg : in STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ : in STD_LOGIC; + \sig_token_cntr_reg[0]\ : in STD_LOGIC; + \sig_token_cntr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + ram_full_i_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo"; +end Arty_Z7_20_axi_vdma_0_0_fifo_generator_ramfifo; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_fifo_generator_ramfifo is + signal \gntv_or_sync_fifo.gl0.rd_n_0\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd_n_5\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.wr_n_2\ : STD_LOGIC; + signal \^out\ : STD_LOGIC; + signal p_0_out : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal p_11_out : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal p_12_out : STD_LOGIC_VECTOR ( 7 downto 0 ); +begin + \out\ <= \^out\; +\gntv_or_sync_fifo.gl0.rd\: entity work.Arty_Z7_20_axi_vdma_0_0_rd_logic_30 + port map ( + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ => \gntv_or_sync_fifo.gl0.rd_n_4\, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0\ => \gntv_or_sync_fifo.gl0.rd_n_5\, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_1\(7 downto 0) => p_0_out(7 downto 0), + E(0) => \gc1.count_reg[7]\, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, + Q(7 downto 0) => p_11_out(7 downto 0), + SR(0) => SR(0), + \gcc0.gc0.count_reg[7]\(7 downto 0) => p_12_out(7 downto 0), + hold_ff_q => hold_ff_q, + hold_ff_q_reg => hold_ff_q_reg, + lsig_cmd_loaded => lsig_cmd_loaded, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + \out\ => \gntv_or_sync_fifo.gl0.rd_n_0\, + ram_full_fb_i_reg => \^out\, + ram_full_i_reg => \gntv_or_sync_fifo.gl0.rd_n_6\, + ram_full_i_reg_0 => ram_full_i_reg, + ram_full_i_reg_1(0) => E(0), + ram_full_i_reg_2(0) => ram_full_i_reg_0(0), + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_ok_to_post_rd_addr_reg => sig_ok_to_post_rd_addr_reg, + sig_posted_to_axi_2_reg => sig_posted_to_axi_2_reg, + sig_posted_to_axi_2_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_2\, + \sig_token_cntr_reg[0]\ => \sig_token_cntr_reg[0]\, + \sig_token_cntr_reg[3]\(3 downto 0) => \sig_token_cntr_reg[3]\(3 downto 0), + \sig_user_skid_reg_reg[0]\ => \sig_user_skid_reg_reg[0]\ + ); +\gntv_or_sync_fifo.gl0.wr\: entity work.Arty_Z7_20_axi_vdma_0_0_wr_logic_31 + port map ( + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0\(7 downto 0) => p_11_out(7 downto 0), + E(0) => E(0), + Q(7 downto 0) => p_12_out(7 downto 0), + SR(0) => SR(0), + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + \out\ => \^out\, + \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ => \gntv_or_sync_fifo.gl0.rd_n_6\, + sig_ok_to_post_rd_addr_reg => \gntv_or_sync_fifo.gl0.wr_n_2\, + sig_posted_to_axi_2_reg => sig_posted_to_axi_2_reg, + \sig_token_cntr_reg[3]\(3 downto 0) => \sig_token_cntr_reg[3]\(3 downto 0) + ); +\gntv_or_sync_fifo.mem\: entity work.Arty_Z7_20_axi_vdma_0_0_memory + port map ( + DIBDI(1 downto 0) => DIBDI(1 downto 0), + DIN(0) => DIN(0), + DOBDO(0) => DOBDO(0), + E(0) => E(0), + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, + \INFERRED_GEN.cnt_i_reg[2]\ => \INFERRED_GEN.cnt_i_reg[2]\, + Q(0) => Q(0), + SR(0) => SR(0), + dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), + \gc1.count_d2_reg[7]\(7 downto 0) => p_0_out(7 downto 0), + \gcc0.gc0.count_d1_reg[7]\(7 downto 0) => p_11_out(7 downto 0), + \gpregsm1.curr_fwft_state_reg[0]\ => \gntv_or_sync_fifo.gl0.rd_n_5\, + hold_ff_q => hold_ff_q, + lsig_cmd_loaded => lsig_cmd_loaded, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axi_mm2s_rdata(63 downto 0) => m_axi_mm2s_rdata(63 downto 0), + \out\ => \gntv_or_sync_fifo.gl0.rd_n_0\, + \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ => \gntv_or_sync_fifo.gl0.rd_n_4\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_fifo_generator_ramfifo__parameterized1\ is + port ( + sig_data_fifo_data_out : out STD_LOGIC_VECTOR ( 65 downto 0 ); + \out\ : out STD_LOGIC; + \gcc0.gc0.count_d1_reg[7]\ : out STD_LOGIC; + hold_ff_q_reg : out STD_LOGIC; + \INCLUDE_PACKING.lsig_packer_full_reg\ : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_data_fifo_dvalid : out STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + lsig_combined_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); + DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ); + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + hold_ff_q_reg_0 : in STD_LOGIC; + sig_s_ready_out_reg : in STD_LOGIC; + \lsig_set_packer_full__1\ : in STD_LOGIC; + lsig_packer_full : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_ramfifo__parameterized1\ : entity is "fifo_generator_ramfifo"; +end \Arty_Z7_20_axi_vdma_0_0_fifo_generator_ramfifo__parameterized1\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_ramfifo__parameterized1\ is + signal \gntv_or_sync_fifo.gl0.rd_n_3\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.wr_n_2\ : STD_LOGIC; + signal \grss.rsts/ram_empty_i0__3\ : STD_LOGIC; + signal p_0_out : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal p_11_out : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal p_2_out_0 : STD_LOGIC; + signal p_7_out : STD_LOGIC; + signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 7 downto 0 ); +begin +\gntv_or_sync_fifo.gl0.rd\: entity work.Arty_Z7_20_axi_vdma_0_0_rd_logic + port map ( + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ => \gntv_or_sync_fifo.gl0.rd_n_3\, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0\ => \gntv_or_sync_fifo.gl0.rd_n_4\, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_1\(7 downto 0) => p_0_out(7 downto 0), + Q(7 downto 0) => rd_pntr_plus1(7 downto 0), + \gpregsm1.user_valid_reg\ => \out\, + hold_ff_q_reg => hold_ff_q_reg, + hold_ff_q_reg_0 => hold_ff_q_reg_0, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\ => p_2_out_0, + p_7_out => p_7_out, + \ram_empty_i0__3\ => \grss.rsts/ram_empty_i0__3\, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_data_fifo_dvalid => sig_data_fifo_dvalid, + sig_s_ready_out_reg => sig_s_ready_out_reg, + sig_stream_rst => sig_stream_rst + ); +\gntv_or_sync_fifo.gl0.wr\: entity work.Arty_Z7_20_axi_vdma_0_0_wr_logic + port map ( + E(0) => E(0), + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0]\(0), + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0\, + \INCLUDE_PACKING.lsig_packer_full_reg\ => \INCLUDE_PACKING.lsig_packer_full_reg\, + Q(7 downto 0) => p_11_out(7 downto 0), + WEBWE(0) => \gntv_or_sync_fifo.gl0.wr_n_2\, + \gc1.count_d1_reg[7]\(7 downto 0) => rd_pntr_plus1(7 downto 0), + \gc1.count_d2_reg[7]\(7 downto 0) => p_0_out(7 downto 0), + lsig_packer_full => lsig_packer_full, + \lsig_set_packer_full__1\ => \lsig_set_packer_full__1\, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\ => \gcc0.gc0.count_d1_reg[7]\, + p_7_out => p_7_out, + ram_empty_fb_i_reg => p_2_out_0, + \ram_empty_i0__3\ => \grss.rsts/ram_empty_i0__3\, + sig_stream_rst => sig_stream_rst + ); +\gntv_or_sync_fifo.mem\: entity work.\Arty_Z7_20_axi_vdma_0_0_memory__parameterized1\ + port map ( + DIBDI(1 downto 0) => DIBDI(1 downto 0), + Q(7 downto 0) => p_11_out(7 downto 0), + WEBWE(0) => \gntv_or_sync_fifo.gl0.wr_n_2\, + \gc1.count_d2_reg[7]\(7 downto 0) => p_0_out(7 downto 0), + lsig_combined_data(63 downto 0) => lsig_combined_data(63 downto 0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.rd_n_4\, + sig_data_fifo_data_out(65 downto 0) => sig_data_fifo_data_out(65 downto 0), + sig_s_ready_out_reg => \gntv_or_sync_fifo.gl0.rd_n_3\, + sig_stream_rst => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_axi_datamover_sfifo_autord__parameterized0\ is + port ( + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_xfer_is_seq_reg_reg : out STD_LOGIC_VECTOR ( 9 downto 0 ); + \sig_child_addr_cntr_lsh_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + S : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \sig_xfer_len_reg_reg[4]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \sig_xfer_len_reg_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_xfer_is_seq_reg_reg_0 : out STD_LOGIC; + sig_xfer_cmd_cmplt_reg0 : out STD_LOGIC; + sig_sf2pcc_xfer_valid : out STD_LOGIC; + sig_ibtt2dre_tready : out STD_LOGIC; + sig_csm_state_ns1 : out STD_LOGIC; + \gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \gpr1.dout_i_reg[1]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + O : out STD_LOGIC_VECTOR ( 3 downto 0 ); + CO : out STD_LOGIC_VECTOR ( 0 to 0 ); + \sig_child_addr_cntr_lsh_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + sig_stream_rst : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + p_32_out : in STD_LOGIC; + sig_adjusted_addr_incr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + sig_clr_dbc_reg_reg : in STD_LOGIC; + sig_csm_pop_child_cmd : in STD_LOGIC; + sig_child_qual_first_of_2 : in STD_LOGIC; + sig_child_qual_error_reg : in STD_LOGIC; + lsig_packer_full : in STD_LOGIC; + ram_full_i_reg : in STD_LOGIC; + \gpr1.dout_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \gpr1.dout_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + sig_child_addr_cntr_lsh_reg : in STD_LOGIC_VECTOR ( 2 downto 0 ); + p_0_out : in STD_LOGIC_VECTOR ( 10 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_sfifo_autord__parameterized0\ : entity is "axi_datamover_sfifo_autord"; +end \Arty_Z7_20_axi_vdma_0_0_axi_datamover_sfifo_autord__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_sfifo_autord__parameterized0\ is + signal \NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO_n_0\ : STD_LOGIC; + signal hold_ff_q : STD_LOGIC; +begin +\NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO\: entity work.\Arty_Z7_20_axi_vdma_0_0_sync_fifo_fg__parameterized0\ + port map ( + CO(0) => CO(0), + D(2 downto 0) => D(2 downto 0), + E(0) => E(0), + O(3 downto 0) => O(3 downto 0), + S(3 downto 0) => S(3 downto 0), + \gpr1.dout_i_reg[1]\(2 downto 0) => \gpr1.dout_i_reg[1]\(2 downto 0), + \gpr1.dout_i_reg[1]_0\(2 downto 0) => \gpr1.dout_i_reg[1]_0\(2 downto 0), + \gpr1.dout_i_reg[3]\(3 downto 0) => \gpr1.dout_i_reg[3]\(3 downto 0), + \gpr1.dout_i_reg[7]\(3 downto 0) => \gpr1.dout_i_reg[7]\(3 downto 0), + hold_ff_q => hold_ff_q, + hold_ff_q_reg => \NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO_n_0\, + lsig_packer_full => lsig_packer_full, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + p_0_out(10 downto 0) => p_0_out(10 downto 0), + p_32_out => p_32_out, + ram_full_i_reg => ram_full_i_reg, + sig_adjusted_addr_incr(8 downto 0) => sig_adjusted_addr_incr(8 downto 0), + sig_child_addr_cntr_lsh_reg(2 downto 0) => sig_child_addr_cntr_lsh_reg(2 downto 0), + \sig_child_addr_cntr_lsh_reg[11]\(0) => \sig_child_addr_cntr_lsh_reg[11]\(0), + \sig_child_addr_cntr_lsh_reg[7]\(3 downto 0) => \sig_child_addr_cntr_lsh_reg[7]\(3 downto 0), + sig_child_qual_error_reg => sig_child_qual_error_reg, + sig_child_qual_first_of_2 => sig_child_qual_first_of_2, + sig_clr_dbc_reg_reg => sig_clr_dbc_reg_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_csm_pop_child_cmd => sig_csm_pop_child_cmd, + sig_csm_state_ns1 => sig_csm_state_ns1, + sig_ibtt2dre_tready => sig_ibtt2dre_tready, + sig_sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid, + sig_stream_rst => sig_stream_rst, + sig_xfer_cmd_cmplt_reg0 => sig_xfer_cmd_cmplt_reg0, + sig_xfer_is_seq_reg_reg(9 downto 0) => sig_xfer_is_seq_reg_reg(9 downto 0), + sig_xfer_is_seq_reg_reg_0 => sig_xfer_is_seq_reg_reg_0, + \sig_xfer_len_reg_reg[4]\(3 downto 0) => \sig_xfer_len_reg_reg[4]\(3 downto 0), + \sig_xfer_len_reg_reg[5]\(0) => \sig_xfer_len_reg_reg[5]\(0) + ); +hold_ff_q_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO_n_0\, + Q => hold_ff_q, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_mm2s_linebuf is + port ( + \out\ : out STD_LOGIC; + mm2s_fifo_pipe_empty : out STD_LOGIC; + mm2s_all_lines_xfred : out STD_LOGIC; + sig_reset_reg_reg : out STD_LOGIC; + m_axis_mm2s_tlast : out STD_LOGIC; + m_axis_mm2s_tuser : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0\ : out STD_LOGIC; + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\ : out STD_LOGIC; + FULL : out STD_LOGIC; + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1\ : out STD_LOGIC; + s_valid0 : out STD_LOGIC; + m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_aclk : in STD_LOGIC; + scndry_reset2 : in STD_LOGIC; + m_axis_mm2s_aclk : in STD_LOGIC; + mm2s_halt : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 12 downto 0 ); + halt_i_reg : in STD_LOGIC; + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + all_lines_xfred : in STD_LOGIC; + m_axis_mm2s_tready : in STD_LOGIC; + mm2s_axis_resetn : in STD_LOGIC; + p_15_out : in STD_LOGIC; + lsig_0ffset_cntr : in STD_LOGIC; + mm2s_prmry_resetn : in STD_LOGIC; + p_24_out : in STD_LOGIC; + hold_ff_q_reg : in STD_LOGIC; + WR_EN : in STD_LOGIC; + dm2linebuf_mm2s_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + DIN : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_mm2s_linebuf : entity is "axi_vdma_mm2s_linebuf"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_mm2s_linebuf; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_mm2s_linebuf is + signal \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I_n_2\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_5\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID_n_4\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID_n_5\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID_n_7\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter[0]_i_1_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter[10]_i_1_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter[11]_i_1_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_10_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_11_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_12_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_3_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_4_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_5_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_8_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_9_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter[1]_i_1_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter[2]_i_1_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter[3]_i_1_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_1_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_3_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_4_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_5_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_6_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter[5]_i_1_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter[6]_i_1_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter[7]_i_1_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_1_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_3_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_4_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_5_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_6_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter[9]_i_1_n_0\ : STD_LOGIC; + signal \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]_i_6_n_1\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]_i_6_n_2\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]_i_6_n_3\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]_i_2_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]_i_2_n_1\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]_i_2_n_2\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]_i_2_n_3\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter_reg[8]_i_2_n_0\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter_reg[8]_i_2_n_1\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter_reg[8]_i_2_n_2\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.vsize_counter_reg[8]_i_2_n_3\ : STD_LOGIC; + signal crnt_vsize_cdc_tig : STD_LOGIC_VECTOR ( 12 downto 0 ); + attribute async_reg : string; + attribute async_reg of crnt_vsize_cdc_tig : signal is "true"; + signal crnt_vsize_d1 : STD_LOGIC_VECTOR ( 12 downto 0 ); + attribute async_reg of crnt_vsize_d1 : signal is "true"; + signal data_count_ae_threshold_cdc_tig : STD_LOGIC_VECTOR ( 10 downto 0 ); + attribute async_reg of data_count_ae_threshold_cdc_tig : signal is "true"; + signal data_count_ae_threshold_d1 : STD_LOGIC_VECTOR ( 10 downto 0 ); + attribute async_reg of data_count_ae_threshold_d1 : signal is "true"; + signal fifo_dout : STD_LOGIC_VECTOR ( 33 downto 0 ); + signal m_axis_fifo_ainit_nosync : STD_LOGIC; + signal m_axis_tlast_d1 : STD_LOGIC; + signal m_axis_tready_d1 : STD_LOGIC; + signal m_axis_tvalid_d1 : STD_LOGIC; + signal minusOp : STD_LOGIC_VECTOR ( 12 downto 1 ); + signal p_4_in : STD_LOGIC; + signal s_axis_fifo_ainit_nosync_reg : STD_LOGIC; + signal \^sig_reset_reg_reg\ : STD_LOGIC; + signal sof_flag : STD_LOGIC; + signal vsize_counter : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal \NLW_GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[10]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[10]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[11]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[11]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[12]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[12]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[5]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[5]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[6]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[6]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[7]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[7]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[8]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[8]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[9]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[9]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[0]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[10]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[10]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[11]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[11]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[12]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[12]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[5]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[5]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[6]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[6]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[7]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[7]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[8]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[8]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[9]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[9]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[0]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[10]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[10]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[5]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[5]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[6]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[6]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[7]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[7]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[8]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[8]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[9]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[9]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[0]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[10]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[10]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[5]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[5]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[6]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[6]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[7]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[7]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[8]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[8]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[9]\ : label is std.standard.true; + attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[9]\ : label is "yes"; +begin + \GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0\ <= \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\; + sig_reset_reg_reg <= \^sig_reset_reg_reg\; +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized17\ + port map ( + \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg\ => \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg_n_0\, + SR(0) => SR(0), + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axis_mm2s_aclk => m_axis_mm2s_aclk, + mm2s_all_lines_xfred => mm2s_all_lines_xfred, + scndry_reset2 => scndry_reset2 + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized20\ + port map ( + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tready_d1_reg\ => \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I_n_2\, + SR(0) => SR(0), + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axis_fifo_ainit_nosync => m_axis_fifo_ainit_nosync, + m_axis_mm2s_aclk => m_axis_mm2s_aclk, + m_axis_mm2s_tready => m_axis_mm2s_tready, + mm2s_axis_resetn => mm2s_axis_resetn, + mm2s_halt => mm2s_halt, + p_15_out => p_15_out, + scndry_reset2 => scndry_reset2, + sig_reset_reg_reg => \^sig_reset_reg_reg\ + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized16\ + port map ( + \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID_n_7\, + SR(0) => SR(0), + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axis_mm2s_aclk => m_axis_mm2s_aclk, + mm2s_fifo_pipe_empty => mm2s_fifo_pipe_empty, + scndry_reset2 => scndry_reset2 + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => Q(0), + Q => crnt_vsize_cdc_tig(0), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => Q(10), + Q => crnt_vsize_cdc_tig(10), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => Q(11), + Q => crnt_vsize_cdc_tig(11), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => Q(12), + Q => crnt_vsize_cdc_tig(12), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => Q(1), + Q => crnt_vsize_cdc_tig(1), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => Q(2), + Q => crnt_vsize_cdc_tig(2), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => Q(3), + Q => crnt_vsize_cdc_tig(3), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => Q(4), + Q => crnt_vsize_cdc_tig(4), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => Q(5), + Q => crnt_vsize_cdc_tig(5), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => Q(6), + Q => crnt_vsize_cdc_tig(6), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => Q(7), + Q => crnt_vsize_cdc_tig(7), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => Q(8), + Q => crnt_vsize_cdc_tig(8), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => Q(9), + Q => crnt_vsize_cdc_tig(9), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => crnt_vsize_cdc_tig(0), + Q => crnt_vsize_d1(0), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => crnt_vsize_cdc_tig(10), + Q => crnt_vsize_d1(10), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => crnt_vsize_cdc_tig(11), + Q => crnt_vsize_d1(11), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => crnt_vsize_cdc_tig(12), + Q => crnt_vsize_d1(12), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => crnt_vsize_cdc_tig(1), + Q => crnt_vsize_d1(1), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => crnt_vsize_cdc_tig(2), + Q => crnt_vsize_d1(2), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => crnt_vsize_cdc_tig(3), + Q => crnt_vsize_d1(3), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => crnt_vsize_cdc_tig(4), + Q => crnt_vsize_d1(4), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => crnt_vsize_cdc_tig(5), + Q => crnt_vsize_d1(5), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => crnt_vsize_cdc_tig(6), + Q => crnt_vsize_d1(6), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => crnt_vsize_cdc_tig(7), + Q => crnt_vsize_d1(7), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => crnt_vsize_cdc_tig(8), + Q => crnt_vsize_d1(8), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => crnt_vsize_cdc_tig(9), + Q => crnt_vsize_d1(9), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => '0', + Q => data_count_ae_threshold_cdc_tig(0), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => '0', + Q => data_count_ae_threshold_cdc_tig(10), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => '0', + Q => data_count_ae_threshold_cdc_tig(1), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => '0', + Q => data_count_ae_threshold_cdc_tig(2), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => '0', + Q => data_count_ae_threshold_cdc_tig(3), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => '0', + Q => data_count_ae_threshold_cdc_tig(4), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => '0', + Q => data_count_ae_threshold_cdc_tig(5), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => '0', + Q => data_count_ae_threshold_cdc_tig(6), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => '0', + Q => data_count_ae_threshold_cdc_tig(7), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => '0', + Q => data_count_ae_threshold_cdc_tig(8), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => '0', + Q => data_count_ae_threshold_cdc_tig(9), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => data_count_ae_threshold_cdc_tig(0), + Q => data_count_ae_threshold_d1(0), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => data_count_ae_threshold_cdc_tig(10), + Q => data_count_ae_threshold_d1(10), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => data_count_ae_threshold_cdc_tig(1), + Q => data_count_ae_threshold_d1(1), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => data_count_ae_threshold_cdc_tig(2), + Q => data_count_ae_threshold_d1(2), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => data_count_ae_threshold_cdc_tig(3), + Q => data_count_ae_threshold_d1(3), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => data_count_ae_threshold_cdc_tig(4), + Q => data_count_ae_threshold_d1(4), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => data_count_ae_threshold_cdc_tig(5), + Q => data_count_ae_threshold_d1(5), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => data_count_ae_threshold_cdc_tig(6), + Q => data_count_ae_threshold_d1(6), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => data_count_ae_threshold_cdc_tig(7), + Q => data_count_ae_threshold_d1(7), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => data_count_ae_threshold_cdc_tig(8), + Q => data_count_ae_threshold_d1(8), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => data_count_ae_threshold_cdc_tig(9), + Q => data_count_ae_threshold_d1(9), + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_afifo_builtin + port map ( + DIN(15) => sof_flag, + DIN(14) => DIN(0), + DIN(13 downto 0) => dm2linebuf_mm2s_tdata(31 downto 18), + FULL => FULL, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1\, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_5\, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, + WR_EN => WR_EN, + dm2linebuf_mm2s_tdata(17 downto 0) => dm2linebuf_mm2s_tdata(17 downto 0), + fifo_dout(33 downto 0) => fifo_dout(33 downto 0), + hold_ff_q_reg => hold_ff_q_reg, + lsig_0ffset_cntr => lsig_0ffset_cntr, + m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axis_mm2s_aclk => m_axis_mm2s_aclk, + mm2s_halt => mm2s_halt, + mm2s_prmry_resetn => mm2s_prmry_resetn, + \out\ => p_4_in, + p_24_out => p_24_out, + s_axis_fifo_ainit_nosync_reg => s_axis_fifo_ainit_nosync_reg, + sig_m_valid_out_reg => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_0\ + ); +\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_5\, + Q => sof_flag, + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_skid_buf + port map ( + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ => \^sig_reset_reg_reg\, + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID_n_7\, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_0\, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tlast_d1_reg\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID_n_4\, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tvalid_d1_reg\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID_n_5\, + \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg\ => \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg_n_0\, + fifo_dout(33 downto 0) => fifo_dout(33 downto 0), + m_axis_fifo_ainit_nosync => m_axis_fifo_ainit_nosync, + m_axis_mm2s_aclk => m_axis_mm2s_aclk, + m_axis_mm2s_tdata(31 downto 0) => m_axis_mm2s_tdata(31 downto 0), + m_axis_mm2s_tlast => m_axis_mm2s_tlast, + m_axis_mm2s_tready => m_axis_mm2s_tready, + m_axis_mm2s_tuser(0) => m_axis_mm2s_tuser(0), + m_axis_mm2s_tvalid => \out\, + mm2s_axis_resetn => mm2s_axis_resetn, + \out\ => p_4_in, + p_15_out => p_15_out, + s_valid0 => s_valid0 + ); +\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tlast_d1_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID_n_4\, + Q => m_axis_tlast_d1, + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tready_d1_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I_n_2\, + Q => m_axis_tready_d1, + R => '0' + ); +\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tvalid_d1_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => '1', + D => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID_n_5\, + Q => m_axis_tvalid_d1, + R => '0' + ); +\GEN_LINEBUF_NO_SOF.all_lines_xfred_reg\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => m_axis_mm2s_aclk, + CE => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\, + D => all_lines_xfred, + Q => \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg_n_0\, + S => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\(0) + ); +\GEN_LINEBUF_NO_SOF.s_axis_fifo_ainit_nosync_reg_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => halt_i_reg, + Q => s_axis_fifo_ainit_nosync_reg, + R => '0' + ); +\GEN_LINEBUF_NO_SOF.vsize_counter[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8B88" + ) + port map ( + I0 => crnt_vsize_d1(0), + I1 => p_15_out, + I2 => vsize_counter(0), + I3 => \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\, + O => \GEN_LINEBUF_NO_SOF.vsize_counter[0]_i_1_n_0\ + ); +\GEN_LINEBUF_NO_SOF.vsize_counter[10]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"B888" + ) + port map ( + I0 => crnt_vsize_d1(10), + I1 => p_15_out, + I2 => minusOp(10), + I3 => \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\, + O => \GEN_LINEBUF_NO_SOF.vsize_counter[10]_i_1_n_0\ + ); +\GEN_LINEBUF_NO_SOF.vsize_counter[11]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"B888" + ) + port map ( + I0 => crnt_vsize_d1(11), + I1 => p_15_out, + I2 => minusOp(11), + I3 => \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\, + O => \GEN_LINEBUF_NO_SOF.vsize_counter[11]_i_1_n_0\ ); -\sig_inhibit_rdy_n_i_1__3\: unisim.vcomponents.LUT2 +\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_10\: unisim.vcomponents.LUT1 generic map( - INIT => X"E" + INIT => X"1" ) port map ( - I0 => \^sig_init_done\, - I1 => sig_inhibit_rdy_n, - O => \sig_inhibit_rdy_n_i_1__3_n_0\ + I0 => vsize_counter(11), + O => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_10_n_0\ ); -sig_inhibit_rdy_n_reg: unisim.vcomponents.FDRE +\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_11\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"1" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \sig_inhibit_rdy_n_i_1__3_n_0\, - Q => sig_inhibit_rdy_n, - R => SR(0) + I0 => vsize_counter(10), + O => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_11_n_0\ ); -sig_init_done_reg: unisim.vcomponents.FDRE +\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_12\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"1" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => sig_mmap_reset_reg_reg, - Q => \^sig_init_done\, - R => '0' + I0 => vsize_counter(9), + O => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_12_n_0\ ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized0\ is - port ( - \INFERRED_GEN.cnt_i_reg[1]\ : out STD_LOGIC; - sig_init_done_0 : out STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[1]_0\ : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 0 to 0 ); - sig_rd_sts_slverr_reg_reg : out STD_LOGIC; - interr_i_reg : out STD_LOGIC; - slverr_i_reg : out STD_LOGIC; - decerr_i_reg : out STD_LOGIC; - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - sig_mmap_reset_reg_reg : in STD_LOGIC; - p_57_out : in STD_LOGIC; - sig_rsc2stat_status_valid : in STD_LOGIC; - sts_tready_reg : in STD_LOGIC; - sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; - sig_rd_sts_slverr_reg_reg_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized0\ : entity is "axi_datamover_fifo"; -end \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized0\; - -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized0\ is - signal \^inferred_gen.cnt_i_reg[1]_0\ : STD_LOGIC; - signal sig_inhibit_rdy_n_i_1_n_0 : STD_LOGIC; - signal \^sig_init_done_0\ : STD_LOGIC; -begin - \INFERRED_GEN.cnt_i_reg[1]_0\ <= \^inferred_gen.cnt_i_reg[1]_0\; - sig_init_done_0 <= \^sig_init_done_0\; -\USE_SRL_FIFO.I_SYNC_FIFO\: entity work.\Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized0\ - port map ( - \INFERRED_GEN.cnt_i_reg[1]\ => \INFERRED_GEN.cnt_i_reg[1]\, - Q(0) => Q(0), - SR(0) => SR(0), - decerr_i_reg => decerr_i_reg, - interr_i_reg => interr_i_reg, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - p_57_out => p_57_out, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_inhibit_rdy_n_reg => \^inferred_gen.cnt_i_reg[1]_0\, - sig_rd_sts_slverr_reg_reg => sig_rd_sts_slverr_reg_reg, - sig_rd_sts_slverr_reg_reg_0(2 downto 0) => sig_rd_sts_slverr_reg_reg_0(2 downto 0), - sig_rsc2stat_status_valid => sig_rsc2stat_status_valid, - slverr_i_reg => slverr_i_reg, - sts_tready_reg => sts_tready_reg +\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBBBBBBBBBBBBA" + ) + port map ( + I0 => p_15_out, + I1 => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_4_n_0\, + I2 => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_5_n_0\, + I3 => vsize_counter(3), + I4 => vsize_counter(4), + I5 => vsize_counter(0), + O => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\ ); -sig_inhibit_rdy_n_i_1: unisim.vcomponents.LUT2 +\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_3\: unisim.vcomponents.LUT4 generic map( - INIT => X"E" + INIT => X"B888" ) port map ( - I0 => \^sig_init_done_0\, - I1 => \^inferred_gen.cnt_i_reg[1]_0\, - O => sig_inhibit_rdy_n_i_1_n_0 + I0 => crnt_vsize_d1(12), + I1 => p_15_out, + I2 => minusOp(12), + I3 => \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\, + O => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_3_n_0\ ); -sig_inhibit_rdy_n_reg: unisim.vcomponents.FDRE +\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_4\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"7F" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => sig_inhibit_rdy_n_i_1_n_0, - Q => \^inferred_gen.cnt_i_reg[1]_0\, - R => SR(0) + I0 => m_axis_tvalid_d1, + I1 => m_axis_tlast_d1, + I2 => m_axis_tready_d1, + O => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_4_n_0\ ); -sig_init_done_reg: unisim.vcomponents.FDRE +\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_5\: unisim.vcomponents.LUT5 generic map( - INIT => '0' + INIT => X"FFFFFFFE" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => sig_mmap_reset_reg_reg, - Q => \^sig_init_done_0\, - R => '0' + I0 => vsize_counter(1), + I1 => vsize_counter(10), + I2 => vsize_counter(7), + I3 => vsize_counter(12), + I4 => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_8_n_0\, + O => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_5_n_0\ ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized1\ is - port ( - sig_init_reg2 : out STD_LOGIC; - sig_calc_error_reg_reg : out STD_LOGIC; - sel : out STD_LOGIC; - sig_posted_to_axi_reg : out STD_LOGIC; - sig_addr_valid_reg_reg : out STD_LOGIC; - \out\ : out STD_LOGIC_VECTOR ( 39 downto 0 ); - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - sig_init_reg : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - sig_mstr2addr_cmd_valid : in STD_LOGIC; - sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; - sig_data2addr_stop_req : in STD_LOGIC; - sig_addr_reg_empty : in STD_LOGIC; - sig_sf_allow_addr_req : in STD_LOGIC; - \in\ : in STD_LOGIC_VECTOR ( 37 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized1\ : entity is "axi_datamover_fifo"; -end \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized1\; - -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized1\ is - signal sig_inhibit_rdy_n : STD_LOGIC; - signal \sig_inhibit_rdy_n_i_1__0_n_0\ : STD_LOGIC; - signal sig_init_done : STD_LOGIC; - signal \sig_init_done_i_1__1_n_0\ : STD_LOGIC; - signal \^sig_init_reg2\ : STD_LOGIC; -begin - sig_init_reg2 <= \^sig_init_reg2\; -\USE_SRL_FIFO.I_SYNC_FIFO\: entity work.\Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized1\ - port map ( - SR(0) => SR(0), - \in\(37 downto 0) => \in\(37 downto 0), - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - \out\(39 downto 0) => \out\(39 downto 0), - sig_addr_reg_empty => sig_addr_reg_empty, - sig_addr_valid_reg_reg => sig_addr_valid_reg_reg, - sig_calc_error_reg_reg => sig_calc_error_reg_reg, - sig_calc_error_reg_reg_0 => sel, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_data2addr_stop_req => sig_data2addr_stop_req, - sig_inhibit_rdy_n => sig_inhibit_rdy_n, - sig_mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid, - sig_posted_to_axi_reg => sig_posted_to_axi_reg, - sig_sf_allow_addr_req => sig_sf_allow_addr_req +\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_7\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFEFF" + ) + port map ( + I0 => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_5_n_0\, + I1 => vsize_counter(4), + I2 => vsize_counter(3), + I3 => vsize_counter(0), + I4 => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_4_n_0\, + O => \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\ ); -\sig_inhibit_rdy_n_i_1__0\: unisim.vcomponents.LUT2 +\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_8\: unisim.vcomponents.LUT6 generic map( - INIT => X"E" + INIT => X"FFFFFFFFFFFFFFFE" ) port map ( - I0 => sig_init_done, - I1 => sig_inhibit_rdy_n, - O => \sig_inhibit_rdy_n_i_1__0_n_0\ + I0 => vsize_counter(11), + I1 => vsize_counter(6), + I2 => vsize_counter(2), + I3 => vsize_counter(8), + I4 => vsize_counter(5), + I5 => vsize_counter(9), + O => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_8_n_0\ ); -sig_inhibit_rdy_n_reg: unisim.vcomponents.FDRE +\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_9\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"1" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \sig_inhibit_rdy_n_i_1__0_n_0\, - Q => sig_inhibit_rdy_n, - R => SR(0) + I0 => vsize_counter(12), + O => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_9_n_0\ ); -\sig_init_done_i_1__1\: unisim.vcomponents.LUT4 +\GEN_LINEBUF_NO_SOF.vsize_counter[1]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"0080" + INIT => X"B888" ) port map ( - I0 => sig_init_reg, - I1 => \^sig_init_reg2\, - I2 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - I3 => sig_init_done, - O => \sig_init_done_i_1__1_n_0\ + I0 => crnt_vsize_d1(1), + I1 => p_15_out, + I2 => minusOp(1), + I3 => \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\, + O => \GEN_LINEBUF_NO_SOF.vsize_counter[1]_i_1_n_0\ ); -sig_init_done_reg: unisim.vcomponents.FDRE +\GEN_LINEBUF_NO_SOF.vsize_counter[2]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"B888" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \sig_init_done_i_1__1_n_0\, - Q => sig_init_done, - R => '0' + I0 => crnt_vsize_d1(2), + I1 => p_15_out, + I2 => minusOp(2), + I3 => \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\, + O => \GEN_LINEBUF_NO_SOF.vsize_counter[2]_i_1_n_0\ ); -sig_init_reg2_reg: unisim.vcomponents.FDSE +\GEN_LINEBUF_NO_SOF.vsize_counter[3]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"B888" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => sig_init_reg, - Q => \^sig_init_reg2\, - S => SR(0) + I0 => crnt_vsize_d1(3), + I1 => p_15_out, + I2 => minusOp(3), + I3 => \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\, + O => \GEN_LINEBUF_NO_SOF.vsize_counter[3]_i_1_n_0\ ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized2\ is - port ( - sig_init_done : out STD_LOGIC; - sig_push_dqual_reg : out STD_LOGIC; - sel : out STD_LOGIC; - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - D : out STD_LOGIC_VECTOR ( 7 downto 0 ); - \out\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); - \sig_good_mmap_dbeat7_out__0\ : out STD_LOGIC; - sig_ld_new_cmd_reg_reg : out STD_LOGIC; - sig_last_dbeat_reg : out STD_LOGIC; - sig_next_cmd_cmplt_reg_reg : out STD_LOGIC; - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - sig_mmap_reset_reg_reg : in STD_LOGIC; - sig_mstr2data_cmd_valid : in STD_LOGIC; - \sig_dbeat_cntr_reg[2]\ : in STD_LOGIC; - Q : in STD_LOGIC_VECTOR ( 7 downto 0 ); - sig_next_sequential_reg : in STD_LOGIC; - sig_last_dbeat : in STD_LOGIC; - sig_dqual_reg_empty : in STD_LOGIC; - m_axi_mm2s_rvalid : in STD_LOGIC; - sig_halt_reg_reg : in STD_LOGIC; - ram_full_i_reg : in STD_LOGIC; - \sig_advance_pipe9_out__1\ : in STD_LOGIC; - sig_rsc2stat_status_valid : in STD_LOGIC; - FIFO_Full_reg : in STD_LOGIC; - sig_inhibit_rdy_n : in STD_LOGIC; - sig_next_calc_error_reg : in STD_LOGIC; - sig_addr_posted_cntr : in STD_LOGIC_VECTOR ( 2 downto 0 ); - sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; - sig_ld_new_cmd_reg : in STD_LOGIC; - sig_dbeat_cntr_eq_1 : in STD_LOGIC; - sig_dqual_reg_full : in STD_LOGIC; - m_axi_mm2s_rlast : in STD_LOGIC; - \sig_dbeat_cntr_reg[3]\ : in STD_LOGIC; - \sig_dbeat_cntr_reg[4]\ : in STD_LOGIC; - \in\ : in STD_LOGIC_VECTOR ( 7 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized2\ : entity is "axi_datamover_fifo"; -end \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized2\; - -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized2\ is - signal sig_inhibit_rdy_n_0 : STD_LOGIC; - signal \sig_inhibit_rdy_n_i_1__1_n_0\ : STD_LOGIC; - signal \^sig_init_done\ : STD_LOGIC; -begin - sig_init_done <= \^sig_init_done\; -\USE_SRL_FIFO.I_SYNC_FIFO\: entity work.\Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized2\ - port map ( - D(7 downto 0) => D(7 downto 0), - E(0) => E(0), - FIFO_Full_reg => FIFO_Full_reg, - Q(7 downto 0) => Q(7 downto 0), - SR(0) => SR(0), - \in\(7 downto 0) => \in\(7 downto 0), - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axi_mm2s_rlast => m_axi_mm2s_rlast, - m_axi_mm2s_rvalid => m_axi_mm2s_rvalid, - \out\(3 downto 0) => \out\(3 downto 0), - ram_full_i_reg => ram_full_i_reg, - sig_addr_posted_cntr(2 downto 0) => sig_addr_posted_cntr(2 downto 0), - \sig_advance_pipe9_out__1\ => \sig_advance_pipe9_out__1\, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_dbeat_cntr_eq_1 => sig_dbeat_cntr_eq_1, - \sig_dbeat_cntr_reg[2]\ => \sig_dbeat_cntr_reg[2]\, - \sig_dbeat_cntr_reg[3]\ => \sig_dbeat_cntr_reg[3]\, - \sig_dbeat_cntr_reg[4]\ => \sig_dbeat_cntr_reg[4]\, - sig_dqual_reg_empty => sig_dqual_reg_empty, - sig_dqual_reg_empty_reg => sig_push_dqual_reg, - sig_dqual_reg_empty_reg_0 => \sig_good_mmap_dbeat7_out__0\, - sig_dqual_reg_full => sig_dqual_reg_full, - sig_halt_reg_reg => sig_halt_reg_reg, - sig_inhibit_rdy_n => sig_inhibit_rdy_n, - sig_inhibit_rdy_n_0 => sig_inhibit_rdy_n_0, - sig_last_dbeat => sig_last_dbeat, - sig_last_dbeat_reg => sig_last_dbeat_reg, - sig_ld_new_cmd_reg => sig_ld_new_cmd_reg, - sig_ld_new_cmd_reg_reg => sig_ld_new_cmd_reg_reg, - sig_mstr2data_cmd_valid => sig_mstr2data_cmd_valid, - sig_next_calc_error_reg => sig_next_calc_error_reg, - sig_next_calc_error_reg_reg => sel, - sig_next_cmd_cmplt_reg_reg => sig_next_cmd_cmplt_reg_reg, - sig_next_sequential_reg => sig_next_sequential_reg, - sig_rsc2stat_status_valid => sig_rsc2stat_status_valid +\GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"B888" + ) + port map ( + I0 => crnt_vsize_d1(4), + I1 => p_15_out, + I2 => minusOp(4), + I3 => \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\, + O => \GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_1_n_0\ ); -\sig_inhibit_rdy_n_i_1__1\: unisim.vcomponents.LUT2 +\GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_3\: unisim.vcomponents.LUT1 generic map( - INIT => X"E" + INIT => X"1" ) port map ( - I0 => \^sig_init_done\, - I1 => sig_inhibit_rdy_n_0, - O => \sig_inhibit_rdy_n_i_1__1_n_0\ + I0 => vsize_counter(4), + O => \GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_3_n_0\ ); -sig_inhibit_rdy_n_reg: unisim.vcomponents.FDRE +\GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_4\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"1" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \sig_inhibit_rdy_n_i_1__1_n_0\, - Q => sig_inhibit_rdy_n_0, - R => SR(0) + I0 => vsize_counter(3), + O => \GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_4_n_0\ ); -sig_init_done_reg: unisim.vcomponents.FDRE +\GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_5\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"1" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => sig_mmap_reset_reg_reg, - Q => \^sig_init_done\, - R => '0' + I0 => vsize_counter(2), + O => \GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_5_n_0\ ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized3\ is - port ( - p_0_out : out STD_LOGIC_VECTOR ( 0 to 0 ); - FIFO_Full_reg : out STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[1]\ : out STD_LOGIC; - sig_init_done : out STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[1]_0\ : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 0 to 0 ); - \in\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - sig_stream_rst : in STD_LOGIC; - sig_mmap_reset_reg_reg : in STD_LOGIC; - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : in STD_LOGIC; - sig_mstr2sf_cmd_valid : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized3\ : entity is "axi_datamover_fifo"; -end \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized3\; - -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized3\ is - signal \^inferred_gen.cnt_i_reg[1]_0\ : STD_LOGIC; - signal \sig_inhibit_rdy_n_i_1__2_n_0\ : STD_LOGIC; - signal \^sig_init_done\ : STD_LOGIC; -begin - \INFERRED_GEN.cnt_i_reg[1]_0\ <= \^inferred_gen.cnt_i_reg[1]_0\; - sig_init_done <= \^sig_init_done\; -\USE_SRL_FIFO.I_SYNC_FIFO\: entity work.\Arty_Z7_20_axi_vdma_0_0_srl_fifo_f__parameterized3\ - port map ( - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\, - FIFO_Full_reg => FIFO_Full_reg, - \INFERRED_GEN.cnt_i_reg[1]\ => \INFERRED_GEN.cnt_i_reg[1]\, - Q(0) => Q(0), - \in\(0) => \in\(0), - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - p_0_out(0) => p_0_out(0), - sig_inhibit_rdy_n_reg => \^inferred_gen.cnt_i_reg[1]_0\, - sig_mstr2sf_cmd_valid => sig_mstr2sf_cmd_valid, - sig_stream_rst => sig_stream_rst +\GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_6\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => vsize_counter(1), + O => \GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_6_n_0\ ); -\sig_inhibit_rdy_n_i_1__2\: unisim.vcomponents.LUT2 +\GEN_LINEBUF_NO_SOF.vsize_counter[5]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"E" + INIT => X"B888" ) port map ( - I0 => \^sig_init_done\, - I1 => \^inferred_gen.cnt_i_reg[1]_0\, - O => \sig_inhibit_rdy_n_i_1__2_n_0\ + I0 => crnt_vsize_d1(5), + I1 => p_15_out, + I2 => minusOp(5), + I3 => \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\, + O => \GEN_LINEBUF_NO_SOF.vsize_counter[5]_i_1_n_0\ ); -sig_inhibit_rdy_n_reg: unisim.vcomponents.FDRE +\GEN_LINEBUF_NO_SOF.vsize_counter[6]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"B888" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \sig_inhibit_rdy_n_i_1__2_n_0\, - Q => \^inferred_gen.cnt_i_reg[1]_0\, - R => sig_stream_rst + I0 => crnt_vsize_d1(6), + I1 => p_15_out, + I2 => minusOp(6), + I3 => \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\, + O => \GEN_LINEBUF_NO_SOF.vsize_counter[6]_i_1_n_0\ ); -sig_init_done_reg: unisim.vcomponents.FDRE +\GEN_LINEBUF_NO_SOF.vsize_counter[7]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"B888" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => sig_mmap_reset_reg_reg, - Q => \^sig_init_done\, - R => '0' + I0 => crnt_vsize_d1(7), + I1 => p_15_out, + I2 => minusOp(7), + I3 => \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\, + O => \GEN_LINEBUF_NO_SOF.vsize_counter[7]_i_1_n_0\ ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_top is - port ( - DOBDO : out STD_LOGIC_VECTOR ( 0 to 0 ); - \sig_user_skid_reg_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - dm2linebuf_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : out STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[0]\ : out STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - ram_empty_fb_i_reg : in STD_LOGIC; - ram_full_i_reg : in STD_LOGIC; - \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC; - sig_stream_rst : in STD_LOGIC; - \gc1.count_d2_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); - Q : in STD_LOGIC_VECTOR ( 6 downto 0 ); - m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); - DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ); - lsig_0ffset_cntr : in STD_LOGIC; - lsig_cmd_loaded : in STD_LOGIC; - \gpregsm1.user_valid_reg\ : in STD_LOGIC; - hold_ff_q : in STD_LOGIC; - p_0_out : in STD_LOGIC_VECTOR ( 0 to 0 ); - dm2linebuf_mm2s_tvalid : in STD_LOGIC; - p_8_out : in STD_LOGIC; - \fifo_wren__0\ : in STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_top : entity is "blk_mem_gen_top"; -end Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_top; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_top is -begin -\valid.cstr\: entity work.Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_generic_cstr - port map ( - DIBDI(1 downto 0) => DIBDI(1 downto 0), - DOBDO(0) => DOBDO(0), - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, - \INFERRED_GEN.cnt_i_reg[0]\ => \INFERRED_GEN.cnt_i_reg[0]\, - \INFERRED_GEN.cnt_i_reg[2]\(0) => \INFERRED_GEN.cnt_i_reg[2]\(0), - Q(6 downto 0) => Q(6 downto 0), - dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), - dm2linebuf_mm2s_tvalid => dm2linebuf_mm2s_tvalid, - \fifo_wren__0\ => \fifo_wren__0\, - \gc1.count_d2_reg[6]\(6 downto 0) => \gc1.count_d2_reg[6]\(6 downto 0), - \gpregsm1.curr_fwft_state_reg[0]\ => \gpregsm1.curr_fwft_state_reg[0]\, - \gpregsm1.user_valid_reg\ => \gpregsm1.user_valid_reg\, - hold_ff_q => hold_ff_q, - lsig_0ffset_cntr => lsig_0ffset_cntr, - lsig_cmd_loaded => lsig_cmd_loaded, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axi_mm2s_rdata(63 downto 0) => m_axi_mm2s_rdata(63 downto 0), - p_0_out(0) => p_0_out(0), - p_8_out => p_8_out, - ram_empty_fb_i_reg => ram_empty_fb_i_reg, - ram_full_i_reg => ram_full_i_reg, - sig_stream_rst => sig_stream_rst, - \sig_user_skid_reg_reg[0]\(0) => \sig_user_skid_reg_reg[0]\(0) +\GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"B888" + ) + port map ( + I0 => crnt_vsize_d1(8), + I1 => p_15_out, + I2 => minusOp(8), + I3 => \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\, + O => \GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_1_n_0\ ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_builtin is - port ( - fifo_full_i : out STD_LOGIC; - sig_m_valid_out_reg : out STD_LOGIC; - fifo_dout : out STD_LOGIC_VECTOR ( 33 downto 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - s_axis_fifo_ainit_nosync_reg : in STD_LOGIC; - m_axis_mm2s_aclk : in STD_LOGIC; - \fifo_wren__0\ : in STD_LOGIC; - \out\ : in STD_LOGIC; - dm2linebuf_mm2s_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - DIN : in STD_LOGIC_VECTOR ( 1 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_builtin : entity is "fifo_generator_v13_1_3_builtin"; -end Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_builtin; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_builtin is - signal rd_rst_i : STD_LOGIC; -begin -\g7ser_birst.rstbt\: entity work.Arty_Z7_20_axi_vdma_0_0_reset_builtin - port map ( - RST => rd_rst_i, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axis_mm2s_aclk => m_axis_mm2s_aclk, - s_axis_fifo_ainit_nosync_reg => s_axis_fifo_ainit_nosync_reg +\GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => vsize_counter(8), + O => \GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_3_n_0\ ); -\v7_bi_fifo.fblk\: entity work.Arty_Z7_20_axi_vdma_0_0_builtin_top_v6 - port map ( - DIN(1 downto 0) => DIN(1 downto 0), - RST => rd_rst_i, - dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), - fifo_dout(33 downto 0) => fifo_dout(33 downto 0), - fifo_full_i => fifo_full_i, - \fifo_wren__0\ => \fifo_wren__0\, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axis_mm2s_aclk => m_axis_mm2s_aclk, - \out\ => \out\, - sig_m_valid_out_reg => sig_m_valid_out_reg +\GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => vsize_counter(7), + O => \GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_4_n_0\ ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl is - port ( - \out\ : out STD_LOGIC; - \sig_addr_posted_cntr_reg[2]\ : out STD_LOGIC; - sig_init_reg2 : out STD_LOGIC; - sig_addr_reg_empty : out STD_LOGIC; - sig_addr2rsc_calc_error : out STD_LOGIC; - m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_mm2s_arvalid : out STD_LOGIC; - sig_wr_fifo : out STD_LOGIC; - m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); - m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); - m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 1 downto 0 ); - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - sig_init_reg : in STD_LOGIC; - m_axi_mm2s_aclk : in STD_LOGIC; - sig_mstr2addr_cmd_valid : in STD_LOGIC; - sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; - sig_data2addr_stop_req : in STD_LOGIC; - sig_sf_allow_addr_req : in STD_LOGIC; - m_axi_mm2s_arready : in STD_LOGIC; - \in\ : in STD_LOGIC_VECTOR ( 37 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl : entity is "axi_datamover_addr_cntl"; -end Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl is - signal \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\ : STD_LOGIC; - signal \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_3\ : STD_LOGIC; - signal \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_4\ : STD_LOGIC; - signal p_1_out : STD_LOGIC_VECTOR ( 50 downto 4 ); - signal \^sig_addr2rsc_calc_error\ : STD_LOGIC; - signal \^sig_addr_reg_empty\ : STD_LOGIC; - signal sig_addr_reg_full : STD_LOGIC; - signal \sig_next_addr_reg[31]_i_1_n_0\ : STD_LOGIC; - signal sig_posted_to_axi : STD_LOGIC; - attribute RTL_KEEP : string; - attribute RTL_KEEP of sig_posted_to_axi : signal is "true"; - attribute equivalent_register_removal : string; - attribute equivalent_register_removal of sig_posted_to_axi : signal is "no"; - signal sig_posted_to_axi_2 : STD_LOGIC; - attribute RTL_KEEP of sig_posted_to_axi_2 : signal is "true"; - attribute equivalent_register_removal of sig_posted_to_axi_2 : signal is "no"; - attribute KEEP : string; - attribute KEEP of sig_posted_to_axi_2_reg : label is "yes"; - attribute equivalent_register_removal of sig_posted_to_axi_2_reg : label is "no"; - attribute KEEP of sig_posted_to_axi_reg : label is "yes"; - attribute equivalent_register_removal of sig_posted_to_axi_reg : label is "no"; -begin - \out\ <= sig_posted_to_axi_2; - sig_addr2rsc_calc_error <= \^sig_addr2rsc_calc_error\; - \sig_addr_posted_cntr_reg[2]\ <= sig_posted_to_axi; - sig_addr_reg_empty <= \^sig_addr_reg_empty\; -\GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO\: entity work.\Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized1\ - port map ( - SR(0) => SR(0), - \in\(37 downto 0) => \in\(37 downto 0), - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - \out\(39) => p_1_out(50), - \out\(38) => p_1_out(47), - \out\(37 downto 36) => p_1_out(45 downto 44), - \out\(35 downto 0) => p_1_out(39 downto 4), - sel => sig_wr_fifo, - sig_addr_reg_empty => \^sig_addr_reg_empty\, - sig_addr_valid_reg_reg => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_4\, - sig_calc_error_reg_reg => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_data2addr_stop_req => sig_data2addr_stop_req, - sig_init_reg => sig_init_reg, - sig_init_reg2 => sig_init_reg2, - sig_mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid, - sig_posted_to_axi_reg => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_3\, - sig_sf_allow_addr_req => sig_sf_allow_addr_req +\GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => vsize_counter(6), + O => \GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_5_n_0\ ); -sig_addr_reg_empty_reg: unisim.vcomponents.FDSE +\GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_6\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"1" ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => '0', - Q => \^sig_addr_reg_empty\, - S => \sig_next_addr_reg[31]_i_1_n_0\ + I0 => vsize_counter(5), + O => \GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_6_n_0\ ); -sig_addr_reg_full_reg: unisim.vcomponents.FDRE +\GEN_LINEBUF_NO_SOF.vsize_counter[9]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"B888" ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - Q => sig_addr_reg_full, - R => \sig_next_addr_reg[31]_i_1_n_0\ + I0 => crnt_vsize_d1(9), + I1 => p_15_out, + I2 => minusOp(9), + I3 => \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\, + O => \GEN_LINEBUF_NO_SOF.vsize_counter[9]_i_1_n_0\ ); -sig_addr_valid_reg_reg: unisim.vcomponents.FDRE +\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_4\, - Q => m_axi_mm2s_arvalid, - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => m_axis_mm2s_aclk, + CE => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\, + D => \GEN_LINEBUF_NO_SOF.vsize_counter[0]_i_1_n_0\, + Q => vsize_counter(0), + R => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\(0) ); -sig_calc_error_reg_reg: unisim.vcomponents.FDRE +\GEN_LINEBUF_NO_SOF.vsize_counter_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(50), - Q => \^sig_addr2rsc_calc_error\, - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => m_axis_mm2s_aclk, + CE => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\, + D => \GEN_LINEBUF_NO_SOF.vsize_counter[10]_i_1_n_0\, + Q => vsize_counter(10), + R => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\(0) ); -\sig_next_addr_reg[31]_i_1\: unisim.vcomponents.LUT4 +\GEN_LINEBUF_NO_SOF.vsize_counter_reg[11]\: unisim.vcomponents.FDRE generic map( - INIT => X"08FF" + INIT => '0' ) port map ( - I0 => m_axi_mm2s_arready, - I1 => sig_addr_reg_full, - I2 => \^sig_addr2rsc_calc_error\, - I3 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - O => \sig_next_addr_reg[31]_i_1_n_0\ + C => m_axis_mm2s_aclk, + CE => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\, + D => \GEN_LINEBUF_NO_SOF.vsize_counter[11]_i_1_n_0\, + Q => vsize_counter(11), + R => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\(0) ); -\sig_next_addr_reg_reg[0]\: unisim.vcomponents.FDRE +\GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(4), - Q => m_axi_mm2s_araddr(0), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => m_axis_mm2s_aclk, + CE => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\, + D => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_3_n_0\, + Q => vsize_counter(12), + R => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\(0) ); -\sig_next_addr_reg_reg[10]\: unisim.vcomponents.FDRE +\GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]_i_6\: unisim.vcomponents.CARRY4 + port map ( + CI => \GEN_LINEBUF_NO_SOF.vsize_counter_reg[8]_i_2_n_0\, + CO(3) => \NLW_GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]_i_6_CO_UNCONNECTED\(3), + CO(2) => \GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]_i_6_n_1\, + CO(1) => \GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]_i_6_n_2\, + CO(0) => \GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]_i_6_n_3\, + CYINIT => '0', + DI(3) => '0', + DI(2 downto 0) => vsize_counter(11 downto 9), + O(3 downto 0) => minusOp(12 downto 9), + S(3) => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_9_n_0\, + S(2) => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_10_n_0\, + S(1) => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_11_n_0\, + S(0) => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_12_n_0\ + ); +\GEN_LINEBUF_NO_SOF.vsize_counter_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(14), - Q => m_axi_mm2s_araddr(10), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => m_axis_mm2s_aclk, + CE => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\, + D => \GEN_LINEBUF_NO_SOF.vsize_counter[1]_i_1_n_0\, + Q => vsize_counter(1), + R => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\(0) ); -\sig_next_addr_reg_reg[11]\: unisim.vcomponents.FDRE +\GEN_LINEBUF_NO_SOF.vsize_counter_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(15), - Q => m_axi_mm2s_araddr(11), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => m_axis_mm2s_aclk, + CE => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\, + D => \GEN_LINEBUF_NO_SOF.vsize_counter[2]_i_1_n_0\, + Q => vsize_counter(2), + R => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\(0) ); -\sig_next_addr_reg_reg[12]\: unisim.vcomponents.FDRE +\GEN_LINEBUF_NO_SOF.vsize_counter_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(16), - Q => m_axi_mm2s_araddr(12), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => m_axis_mm2s_aclk, + CE => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\, + D => \GEN_LINEBUF_NO_SOF.vsize_counter[3]_i_1_n_0\, + Q => vsize_counter(3), + R => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\(0) ); -\sig_next_addr_reg_reg[13]\: unisim.vcomponents.FDRE +\GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(17), - Q => m_axi_mm2s_araddr(13), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => m_axis_mm2s_aclk, + CE => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\, + D => \GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_1_n_0\, + Q => vsize_counter(4), + R => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\(0) ); -\sig_next_addr_reg_reg[14]\: unisim.vcomponents.FDRE +\GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]_i_2_n_0\, + CO(2) => \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]_i_2_n_1\, + CO(1) => \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]_i_2_n_2\, + CO(0) => \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]_i_2_n_3\, + CYINIT => vsize_counter(0), + DI(3 downto 0) => vsize_counter(4 downto 1), + O(3 downto 0) => minusOp(4 downto 1), + S(3) => \GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_3_n_0\, + S(2) => \GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_4_n_0\, + S(1) => \GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_5_n_0\, + S(0) => \GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_6_n_0\ + ); +\GEN_LINEBUF_NO_SOF.vsize_counter_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(18), - Q => m_axi_mm2s_araddr(14), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => m_axis_mm2s_aclk, + CE => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\, + D => \GEN_LINEBUF_NO_SOF.vsize_counter[5]_i_1_n_0\, + Q => vsize_counter(5), + R => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\(0) ); -\sig_next_addr_reg_reg[15]\: unisim.vcomponents.FDRE +\GEN_LINEBUF_NO_SOF.vsize_counter_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(19), - Q => m_axi_mm2s_araddr(15), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => m_axis_mm2s_aclk, + CE => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\, + D => \GEN_LINEBUF_NO_SOF.vsize_counter[6]_i_1_n_0\, + Q => vsize_counter(6), + R => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\(0) ); -\sig_next_addr_reg_reg[16]\: unisim.vcomponents.FDRE +\GEN_LINEBUF_NO_SOF.vsize_counter_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(20), - Q => m_axi_mm2s_araddr(16), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => m_axis_mm2s_aclk, + CE => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\, + D => \GEN_LINEBUF_NO_SOF.vsize_counter[7]_i_1_n_0\, + Q => vsize_counter(7), + R => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\(0) ); -\sig_next_addr_reg_reg[17]\: unisim.vcomponents.FDRE +\GEN_LINEBUF_NO_SOF.vsize_counter_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(21), - Q => m_axi_mm2s_araddr(17), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => m_axis_mm2s_aclk, + CE => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\, + D => \GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_1_n_0\, + Q => vsize_counter(8), + R => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\(0) ); -\sig_next_addr_reg_reg[18]\: unisim.vcomponents.FDRE +\GEN_LINEBUF_NO_SOF.vsize_counter_reg[8]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]_i_2_n_0\, + CO(3) => \GEN_LINEBUF_NO_SOF.vsize_counter_reg[8]_i_2_n_0\, + CO(2) => \GEN_LINEBUF_NO_SOF.vsize_counter_reg[8]_i_2_n_1\, + CO(1) => \GEN_LINEBUF_NO_SOF.vsize_counter_reg[8]_i_2_n_2\, + CO(0) => \GEN_LINEBUF_NO_SOF.vsize_counter_reg[8]_i_2_n_3\, + CYINIT => '0', + DI(3 downto 0) => vsize_counter(8 downto 5), + O(3 downto 0) => minusOp(8 downto 5), + S(3) => \GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_3_n_0\, + S(2) => \GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_4_n_0\, + S(1) => \GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_5_n_0\, + S(0) => \GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_6_n_0\ + ); +\GEN_LINEBUF_NO_SOF.vsize_counter_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(22), - Q => m_axi_mm2s_araddr(18), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => m_axis_mm2s_aclk, + CE => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\, + D => \GEN_LINEBUF_NO_SOF.vsize_counter[9]_i_1_n_0\, + Q => vsize_counter(9), + R => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\(0) ); -\sig_next_addr_reg_reg[19]\: unisim.vcomponents.FDRE +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_s2mm_linebuf is + port ( + run_stop_reg : out STD_LOGIC; + p_in_d1_cdc_from : out STD_LOGIC; + s2mm_fsync_out_m_i : out STD_LOGIC; + s_axis_fifo_ainit_nosync : out STD_LOGIC; + s2mm_fsync_core : out STD_LOGIC; + delay_s2mm_fsync_core_till_mmap_done_flag : out STD_LOGIC; + DOUT : out STD_LOGIC_VECTOR ( 8 downto 0 ); + EMPTY : out STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\ : out STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\ : out STD_LOGIC; + strm_not_finished_no_dwidth : out STD_LOGIC; + s_valid0 : out STD_LOGIC; + sig_last_reg_out_reg : out STD_LOGIC; + \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_s1_reg\ : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 12 downto 0 ); + prmry_reset2 : in STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + s2mm_halt : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + s2mm_dmacr : in STD_LOGIC_VECTOR ( 2 downto 0 ); + prmry_in_xored : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 12 downto 0 ); + sig_reset_reg : in STD_LOGIC; + \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : in STD_LOGIC; + M_VALID : in STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\ : in STD_LOGIC; + s2mm_fsync_out_i : in STD_LOGIC; + \out\ : in STD_LOGIC; + \sig_user_reg_out_reg[0]\ : in STD_LOGIC; + fsize_mismatch_err_s1 : in STD_LOGIC; + drop_fsync_d_pulse_gen_fsize_less_err_d1 : in STD_LOGIC; + s2mm_strm_wready : in STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + M_Last : in STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\ : in STD_LOGIC; + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg_0\ : in STD_LOGIC; + minusOp : in STD_LOGIC_VECTOR ( 11 downto 0 ); + RD_EN : in STD_LOGIC; + DIN : in STD_LOGIC_VECTOR ( 7 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_s2mm_linebuf : entity is "axi_vdma_s2mm_linebuf"; +end Arty_Z7_20_axi_vdma_0_0_axi_vdma_s2mm_linebuf; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_s2mm_linebuf is + signal \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_2\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF_n_1\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.RUNSTOP_AXIS_0_CDC_I_FLUSH_SOF_n_1\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.STRM_WR_HALT_CDC_I_n_3\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.STRM_WR_HALT_CDC_I_n_7\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_1\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_10\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_11\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_12\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_13\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_14\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_2\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_25\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_3\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_4\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_5\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_6\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_7\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_8\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_9\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_10_n_0\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_11_n_0\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_12_n_0\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_13_n_0\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_5_n_0\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_6_n_0\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_7_n_0\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_3_n_0\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_4_n_0\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_5_n_0\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_6_n_0\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_3_n_0\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_4_n_0\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_5_n_0\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_6_n_0\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_i_8_n_1\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_i_8_n_2\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_i_8_n_3\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[4]_i_2_n_0\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[4]_i_2_n_1\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[4]_i_2_n_2\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[4]_i_2_n_3\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[8]_i_2_n_0\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[8]_i_2_n_1\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[8]_i_2_n_2\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[8]_i_2_n_3\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg_n_0\ : STD_LOGIC; + signal crnt_vsize_cdc_tig : STD_LOGIC_VECTOR ( 12 downto 0 ); + attribute async_reg : string; + attribute async_reg of crnt_vsize_cdc_tig : signal is "true"; + signal crnt_vsize_d1 : STD_LOGIC_VECTOR ( 12 downto 0 ); + attribute async_reg of crnt_vsize_d1 : signal is "true"; + signal data_count_af_threshold_cdc_tig : STD_LOGIC_VECTOR ( 10 downto 0 ); + attribute async_reg of data_count_af_threshold_cdc_tig : signal is "true"; + signal data_count_af_threshold_d1 : STD_LOGIC_VECTOR ( 10 downto 0 ); + attribute async_reg of data_count_af_threshold_d1 : signal is "true"; + signal delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s : STD_LOGIC; + signal delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 : STD_LOGIC; + signal \^delay_s2mm_fsync_core_till_mmap_done_flag\ : STD_LOGIC; + signal delay_s2mm_fsync_core_till_mmap_done_flag_d1 : STD_LOGIC; + signal done_vsize_counter : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal fifo_full_i : STD_LOGIC; + signal fsize_err_to_dm_halt_flag : STD_LOGIC; + signal fsync_src_select_cdc_tig : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute async_reg of fsync_src_select_cdc_tig : signal is "true"; + signal fsync_src_select_d1 : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute async_reg of fsync_src_select_d1 : signal is "true"; + signal minusOp_1 : STD_LOGIC_VECTOR ( 12 downto 1 ); + signal mmap_not_finished_s : STD_LOGIC; + signal p_3_out : STD_LOGIC; + signal \^run_stop_reg\ : STD_LOGIC; + signal \^s2mm_fsync_out_m_i\ : STD_LOGIC; + signal \NLW_GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[10]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[10]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[11]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[11]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[5]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[5]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[6]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[6]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[7]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[7]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[8]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[8]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[9]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[9]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[0]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[10]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[10]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[11]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[11]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[5]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[5]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[6]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[6]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[7]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[7]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[8]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[8]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[9]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[9]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[0]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[10]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[10]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[5]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[5]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[6]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[6]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[7]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[7]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[8]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[8]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[9]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[9]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[0]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[10]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[10]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[2]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[3]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[4]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[5]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[5]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[6]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[6]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[7]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[7]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[8]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[8]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[9]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[9]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.fsync_src_select_cdc_tig_reg[0]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.fsync_src_select_cdc_tig_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.fsync_src_select_cdc_tig_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.fsync_src_select_cdc_tig_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.fsync_src_select_d1_reg[0]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.fsync_src_select_d1_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.fsync_src_select_d1_reg[1]\ : label is std.standard.true; + attribute KEEP of \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.fsync_src_select_d1_reg[1]\ : label is "yes"; +begin + delay_s2mm_fsync_core_till_mmap_done_flag <= \^delay_s2mm_fsync_core_till_mmap_done_flag\; + run_stop_reg <= \^run_stop_reg\; + s2mm_fsync_out_m_i <= \^s2mm_fsync_out_m_i\; +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized27\ + port map ( + E(0) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3\, + \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.s2mm_fsync_out_m_d1_reg\ => \^s2mm_fsync_out_m_i\, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]\ => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_5_n_0\, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[3]\ => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_6_n_0\, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[6]\ => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_14\, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[6]_0\ => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_7_n_0\, + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\ => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_2\, + Q(0) => done_vsize_counter(0), + SR(0) => SR(0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + p_in_d1_cdc_from => p_in_d1_cdc_from, + prmry_in_xored => prmry_in_xored, + prmry_reset2 => prmry_reset2, + s_axis_s2mm_aclk => s_axis_s2mm_aclk, + sig_s_ready_out_reg => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_25\ + ); +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized29\ + port map ( + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\ => \^run_stop_reg\, + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_reg\ => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF_n_1\, + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_reg_0\ => \^delay_s2mm_fsync_core_till_mmap_done_flag\, + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\ => \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg_n_0\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\, + SR(0) => SR(0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + mmap_not_finished_s => mmap_not_finished_s, + \out\ => \out\, + prmry_reset2 => prmry_reset2, + s_axis_s2mm_aclk => s_axis_s2mm_aclk, + \sig_user_reg_out_reg[0]\ => \sig_user_reg_out_reg[0]\ + ); +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.RUNSTOP_AXIS_0_CDC_I_FLUSH_SOF\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized26\ + port map ( + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\ => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.STRM_WR_HALT_CDC_I_n_3\, + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg\ => \^run_stop_reg\, + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg_0\ => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.RUNSTOP_AXIS_0_CDC_I_FLUSH_SOF_n_1\, + SR(0) => SR(0), + delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s => delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\ => \out\, + prmry_reset2 => prmry_reset2, + s2mm_dmacr(0) => s2mm_dmacr(0), + s_axis_s2mm_aclk => s_axis_s2mm_aclk, + \sig_user_reg_out_reg[0]\ => \sig_user_reg_out_reg[0]\ + ); +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.STRM_WR_HALT_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized25\ + port map ( + FULL => fifo_full_i, + \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_s1_reg\ => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_s1_reg\, + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg\ => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.STRM_WR_HALT_CDC_I_n_3\, + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_reg\ => \^delay_s2mm_fsync_core_till_mmap_done_flag\, + \GEN_S2MM_FLUSH_SOF_LOGIC.fsize_err_to_dm_halt_flag_reg\ => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.STRM_WR_HALT_CDC_I_n_7\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg_0\, + M_VALID => M_VALID, + SR(0) => SR(0), + delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s => delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s, + delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 => delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1, + delay_s2mm_fsync_core_till_mmap_done_flag_d1 => delay_s2mm_fsync_core_till_mmap_done_flag_d1, + drop_fsync_d_pulse_gen_fsize_less_err_d1 => drop_fsync_d_pulse_gen_fsize_less_err_d1, + fsize_err_to_dm_halt_flag => fsize_err_to_dm_halt_flag, + fsize_mismatch_err_s1 => fsize_mismatch_err_s1, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + mmap_not_finished_s => mmap_not_finished_s, + \out\ => \out\, + p_3_out => p_3_out, + prmry_reset2 => prmry_reset2, + run_stop_reg => \^run_stop_reg\, + s2mm_fsync_core => s2mm_fsync_core, + s2mm_fsync_out_i => s2mm_fsync_out_i, + s2mm_halt => s2mm_halt, + s_axis_fifo_ainit_nosync => s_axis_fifo_ainit_nosync, + s_axis_s2mm_aclk => s_axis_s2mm_aclk, + s_valid0 => s_valid0, + sig_last_reg_out_reg => sig_last_reg_out_reg, + \sig_user_reg_out_reg[0]\ => \sig_user_reg_out_reg[0]\ + ); +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(23), - Q => m_axi_mm2s_araddr(19), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => Q(0), + Q => crnt_vsize_cdc_tig(0), + R => '0' ); -\sig_next_addr_reg_reg[1]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(5), - Q => m_axi_mm2s_araddr(1), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => Q(10), + Q => crnt_vsize_cdc_tig(10), + R => '0' ); -\sig_next_addr_reg_reg[20]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(24), - Q => m_axi_mm2s_araddr(20), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => Q(11), + Q => crnt_vsize_cdc_tig(11), + R => '0' ); -\sig_next_addr_reg_reg[21]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(25), - Q => m_axi_mm2s_araddr(21), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => Q(12), + Q => crnt_vsize_cdc_tig(12), + R => '0' ); -\sig_next_addr_reg_reg[22]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(26), - Q => m_axi_mm2s_araddr(22), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => Q(1), + Q => crnt_vsize_cdc_tig(1), + R => '0' ); -\sig_next_addr_reg_reg[23]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(27), - Q => m_axi_mm2s_araddr(23), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => Q(2), + Q => crnt_vsize_cdc_tig(2), + R => '0' ); -\sig_next_addr_reg_reg[24]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(28), - Q => m_axi_mm2s_araddr(24), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => Q(3), + Q => crnt_vsize_cdc_tig(3), + R => '0' ); -\sig_next_addr_reg_reg[25]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(29), - Q => m_axi_mm2s_araddr(25), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => Q(4), + Q => crnt_vsize_cdc_tig(4), + R => '0' ); -\sig_next_addr_reg_reg[26]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(30), - Q => m_axi_mm2s_araddr(26), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => Q(5), + Q => crnt_vsize_cdc_tig(5), + R => '0' ); -\sig_next_addr_reg_reg[27]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(31), - Q => m_axi_mm2s_araddr(27), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => Q(6), + Q => crnt_vsize_cdc_tig(6), + R => '0' ); -\sig_next_addr_reg_reg[28]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(32), - Q => m_axi_mm2s_araddr(28), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => Q(7), + Q => crnt_vsize_cdc_tig(7), + R => '0' ); -\sig_next_addr_reg_reg[29]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(33), - Q => m_axi_mm2s_araddr(29), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => Q(8), + Q => crnt_vsize_cdc_tig(8), + R => '0' ); -\sig_next_addr_reg_reg[2]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_cdc_tig_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(6), - Q => m_axi_mm2s_araddr(2), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => Q(9), + Q => crnt_vsize_cdc_tig(9), + R => '0' ); -\sig_next_addr_reg_reg[30]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(34), - Q => m_axi_mm2s_araddr(30), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => crnt_vsize_cdc_tig(0), + Q => crnt_vsize_d1(0), + R => '0' ); -\sig_next_addr_reg_reg[31]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(35), - Q => m_axi_mm2s_araddr(31), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => crnt_vsize_cdc_tig(10), + Q => crnt_vsize_d1(10), + R => '0' ); -\sig_next_addr_reg_reg[3]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(7), - Q => m_axi_mm2s_araddr(3), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => crnt_vsize_cdc_tig(11), + Q => crnt_vsize_d1(11), + R => '0' ); -\sig_next_addr_reg_reg[4]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(8), - Q => m_axi_mm2s_araddr(4), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => crnt_vsize_cdc_tig(12), + Q => crnt_vsize_d1(12), + R => '0' ); -\sig_next_addr_reg_reg[5]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(9), - Q => m_axi_mm2s_araddr(5), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => crnt_vsize_cdc_tig(1), + Q => crnt_vsize_d1(1), + R => '0' ); -\sig_next_addr_reg_reg[6]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(10), - Q => m_axi_mm2s_araddr(6), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => crnt_vsize_cdc_tig(2), + Q => crnt_vsize_d1(2), + R => '0' ); -\sig_next_addr_reg_reg[7]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(11), - Q => m_axi_mm2s_araddr(7), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => crnt_vsize_cdc_tig(3), + Q => crnt_vsize_d1(3), + R => '0' ); -\sig_next_addr_reg_reg[8]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(12), - Q => m_axi_mm2s_araddr(8), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => crnt_vsize_cdc_tig(4), + Q => crnt_vsize_d1(4), + R => '0' ); -\sig_next_addr_reg_reg[9]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(13), - Q => m_axi_mm2s_araddr(9), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => crnt_vsize_cdc_tig(5), + Q => crnt_vsize_d1(5), + R => '0' ); -\sig_next_burst_reg_reg[0]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(47), - Q => m_axi_mm2s_arburst(0), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => crnt_vsize_cdc_tig(6), + Q => crnt_vsize_d1(6), + R => '0' ); -\sig_next_len_reg_reg[0]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(36), - Q => m_axi_mm2s_arlen(0), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => crnt_vsize_cdc_tig(7), + Q => crnt_vsize_d1(7), + R => '0' ); -\sig_next_len_reg_reg[1]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(37), - Q => m_axi_mm2s_arlen(1), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => crnt_vsize_cdc_tig(8), + Q => crnt_vsize_d1(8), + R => '0' ); -\sig_next_len_reg_reg[2]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(38), - Q => m_axi_mm2s_arlen(2), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => crnt_vsize_cdc_tig(9), + Q => crnt_vsize_d1(9), + R => '0' ); -\sig_next_len_reg_reg[3]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(39), - Q => m_axi_mm2s_arlen(3), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => '0', + Q => data_count_af_threshold_cdc_tig(0), + R => '0' ); -\sig_next_size_reg_reg[0]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(44), - Q => m_axi_mm2s_arsize(0), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => '0', + Q => data_count_af_threshold_cdc_tig(10), + R => '0' ); -\sig_next_size_reg_reg[1]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_1\, - D => p_1_out(45), - Q => m_axi_mm2s_arsize(1), - R => \sig_next_addr_reg[31]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => '0', + Q => data_count_af_threshold_cdc_tig(1), + R => '0' ); -sig_posted_to_axi_2_reg: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, + C => s_axis_s2mm_aclk, CE => '1', - D => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_3\, - Q => sig_posted_to_axi_2, + D => '0', + Q => data_count_af_threshold_cdc_tig(2), R => '0' ); -sig_posted_to_axi_reg: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, + C => s_axis_s2mm_aclk, CE => '1', - D => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO_n_3\, - Q => sig_posted_to_axi, + D => '0', + Q => data_count_af_threshold_cdc_tig(3), R => '0' ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_cmd_status is - port ( - \INFERRED_GEN.cnt_i_reg[1]\ : out STD_LOGIC; - sig_init_done : out STD_LOGIC; - sig_init_done_0 : out STD_LOGIC; - sig_inhibit_rdy_n : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 0 to 0 ); - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - FIFO_Full_reg : out STD_LOGIC_VECTOR ( 0 to 0 ); - \out\ : out STD_LOGIC_VECTOR ( 49 downto 0 ); - sig_calc_error_reg_reg : out STD_LOGIC; - sig_rd_sts_slverr_reg_reg : out STD_LOGIC; - interr_i_reg : out STD_LOGIC; - slverr_i_reg : out STD_LOGIC; - decerr_i_reg : out STD_LOGIC; - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - sig_mmap_reset_reg_reg : in STD_LOGIC; - sig_mmap_reset_reg_reg_0 : in STD_LOGIC; - sig_calc_error_pushed_reg : in STD_LOGIC; - sig_sm_halt_reg : in STD_LOGIC; - sig_input_reg_empty : in STD_LOGIC; - sig_calc_error_pushed : in STD_LOGIC; - p_55_out : in STD_LOGIC; - cmnd_wr : in STD_LOGIC; - mm2s_halt : in STD_LOGIC; - p_57_out : in STD_LOGIC; - sig_rsc2stat_status_valid : in STD_LOGIC; - sts_tready_reg : in STD_LOGIC; - \in\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; - \s_axis_cmd_tdata_reg[63]\ : in STD_LOGIC_VECTOR ( 48 downto 0 ); - sig_rd_sts_slverr_reg_reg_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_cmd_status : entity is "axi_datamover_cmd_status"; -end Arty_Z7_20_axi_vdma_0_0_axi_datamover_cmd_status; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_cmd_status is -begin -\GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO\: entity work.\Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized0\ - port map ( - \INFERRED_GEN.cnt_i_reg[1]\ => \INFERRED_GEN.cnt_i_reg[1]\, - \INFERRED_GEN.cnt_i_reg[1]_0\ => sig_inhibit_rdy_n, - Q(0) => FIFO_Full_reg(0), - SR(0) => SR(0), - decerr_i_reg => decerr_i_reg, - interr_i_reg => interr_i_reg, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - p_57_out => p_57_out, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_init_done_0 => sig_init_done_0, - sig_mmap_reset_reg_reg => sig_mmap_reset_reg_reg_0, - sig_rd_sts_slverr_reg_reg => sig_rd_sts_slverr_reg_reg, - sig_rd_sts_slverr_reg_reg_0(2 downto 0) => sig_rd_sts_slverr_reg_reg_0(2 downto 0), - sig_rsc2stat_status_valid => sig_rsc2stat_status_valid, - slverr_i_reg => slverr_i_reg, - sts_tready_reg => sts_tready_reg - ); -I_CMD_FIFO: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo - port map ( - E(0) => E(0), - Q(0) => Q(0), - SR(0) => SR(0), - cmnd_wr => cmnd_wr, - \in\(0) => \in\(0), - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - mm2s_halt => mm2s_halt, - \out\(49 downto 0) => \out\(49 downto 0), - p_55_out => p_55_out, - \s_axis_cmd_tdata_reg[63]\(48 downto 0) => \s_axis_cmd_tdata_reg[63]\(48 downto 0), - sig_calc_error_pushed => sig_calc_error_pushed, - sig_calc_error_pushed_reg => sig_calc_error_pushed_reg, - sig_calc_error_reg_reg => sig_calc_error_reg_reg, - sig_init_done => sig_init_done, - sig_input_reg_empty => sig_input_reg_empty, - sig_mmap_reset_reg_reg => sig_mmap_reset_reg_reg, - sig_sm_halt_reg => sig_sm_halt_reg - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_rddata_cntl is - port ( - \sig_addr_posted_cntr_reg[2]_0\ : out STD_LOGIC; - sig_data2addr_stop_req : out STD_LOGIC; - sig_data2rsc_calc_err : out STD_LOGIC; - sig_data2rsc_slverr : out STD_LOGIC; - sig_init_done : out STD_LOGIC; - sig_rd_sts_reg_empty_reg : out STD_LOGIC; - sig_rd_sts_reg_full0 : out STD_LOGIC; - sig_rd_sts_decerr_reg0 : out STD_LOGIC; - sig_wr_fifo : out STD_LOGIC; - \sig_advance_pipe9_out__1\ : out STD_LOGIC; - sig_push_rd_sts_reg : out STD_LOGIC; - DIBDI : out STD_LOGIC_VECTOR ( 1 downto 0 ); - \mm2s_strm_wvalid0__1\ : out STD_LOGIC; - m_axi_mm2s_rready : out STD_LOGIC; - sig_halt_cmplt_reg : out STD_LOGIC; - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - sig_mmap_reset_reg_reg : in STD_LOGIC; - sig_s_h_halt_reg_reg : in STD_LOGIC; - sig_rd_sts_decerr_reg_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); - sig_mstr2data_cmd_valid : in STD_LOGIC; - m_axi_mm2s_rlast : in STD_LOGIC; - m_axi_mm2s_rvalid : in STD_LOGIC; - \out\ : in STD_LOGIC; - m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); - sig_rsc2data_ready : in STD_LOGIC; - sig_rsc2stat_status_valid : in STD_LOGIC; - FIFO_Full_reg : in STD_LOGIC; - sig_inhibit_rdy_n : in STD_LOGIC; - sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; - sig_addr2rsc_calc_error : in STD_LOGIC; - sig_addr_reg_empty : in STD_LOGIC; - mm2s_halt_cmplt : in STD_LOGIC; - \in\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); - sig_posted_to_axi_reg : in STD_LOGIC - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_rddata_cntl : entity is "axi_datamover_rddata_cntl"; -end Arty_Z7_20_axi_vdma_0_0_axi_datamover_rddata_cntl; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_rddata_cntl is - signal \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_17\ : STD_LOGIC; - signal \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_18\ : STD_LOGIC; - signal \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_19\ : STD_LOGIC; - signal \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_3\ : STD_LOGIC; - signal \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_4\ : STD_LOGIC; - signal \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_5\ : STD_LOGIC; - signal \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_6\ : STD_LOGIC; - signal \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_7\ : STD_LOGIC; - signal p_0_in : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal sig_addr_posted_cntr : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal \sig_addr_posted_cntr[0]_i_1_n_0\ : STD_LOGIC; - signal \sig_addr_posted_cntr[1]_i_1_n_0\ : STD_LOGIC; - signal \sig_addr_posted_cntr[2]_i_1_n_0\ : STD_LOGIC; - signal \sig_addr_posted_cntr_eq_0__1\ : STD_LOGIC; - signal \^sig_addr_posted_cntr_reg[2]_0\ : STD_LOGIC; - signal \^sig_advance_pipe9_out__1\ : STD_LOGIC; - signal sig_cmd_cmplt_last_dbeat : STD_LOGIC; - signal sig_cmd_fifo_data_out : STD_LOGIC_VECTOR ( 35 downto 32 ); - signal sig_coelsc_decerr_reg0 : STD_LOGIC; - signal sig_coelsc_interr_reg0 : STD_LOGIC; - signal sig_coelsc_reg_full_i_1_n_0 : STD_LOGIC; - signal sig_coelsc_slverr_reg0 : STD_LOGIC; - signal \^sig_data2addr_stop_req\ : STD_LOGIC; - signal \^sig_data2rsc_calc_err\ : STD_LOGIC; - signal sig_data2rsc_decerr : STD_LOGIC; - signal \^sig_data2rsc_slverr\ : STD_LOGIC; - signal sig_data2rsc_valid : STD_LOGIC; - signal sig_data2rst_stop_cmplt : STD_LOGIC; - signal \sig_dbeat_cntr[5]_i_2_n_0\ : STD_LOGIC; - signal \sig_dbeat_cntr[7]_i_3_n_0\ : STD_LOGIC; - signal \sig_dbeat_cntr[7]_i_4_n_0\ : STD_LOGIC; - signal \sig_dbeat_cntr[7]_i_5_n_0\ : STD_LOGIC; - signal sig_dbeat_cntr_eq_1 : STD_LOGIC; - signal \sig_dbeat_cntr_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal sig_dqual_reg_empty : STD_LOGIC; - signal sig_dqual_reg_full : STD_LOGIC; - signal \sig_good_mmap_dbeat7_out__0\ : STD_LOGIC; - signal sig_halt_reg_dly1 : STD_LOGIC; - signal sig_halt_reg_dly2 : STD_LOGIC; - signal sig_halt_reg_dly3 : STD_LOGIC; - signal sig_last_dbeat : STD_LOGIC; - signal sig_last_mmap_dbeat : STD_LOGIC; - signal sig_ld_new_cmd_reg : STD_LOGIC; - signal sig_next_calc_error_reg : STD_LOGIC; - signal sig_next_cmd_cmplt_reg : STD_LOGIC; - signal sig_next_eof_reg : STD_LOGIC; - signal sig_next_sequential_reg : STD_LOGIC; - signal sig_push_coelsc_reg : STD_LOGIC; - signal sig_push_dqual_reg : STD_LOGIC; - attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of m_axi_mm2s_rready_INST_0_i_1 : label is "soft_lutpair109"; - attribute SOFT_HLUTNM of \sig_addr_posted_cntr[0]_i_1\ : label is "soft_lutpair108"; - attribute SOFT_HLUTNM of \sig_addr_posted_cntr[1]_i_1\ : label is "soft_lutpair109"; - attribute SOFT_HLUTNM of \sig_addr_posted_cntr[2]_i_1\ : label is "soft_lutpair108"; - attribute SOFT_HLUTNM of sig_coelsc_decerr_reg_i_1 : label is "soft_lutpair110"; - attribute SOFT_HLUTNM of sig_coelsc_interr_reg_i_1 : label is "soft_lutpair111"; - attribute SOFT_HLUTNM of sig_coelsc_reg_full_i_3 : label is "soft_lutpair111"; - attribute SOFT_HLUTNM of sig_coelsc_slverr_reg_i_1 : label is "soft_lutpair110"; - attribute SOFT_HLUTNM of sig_rd_sts_reg_empty_i_1 : label is "soft_lutpair112"; - attribute SOFT_HLUTNM of sig_rd_sts_reg_full_i_3 : label is "soft_lutpair112"; -begin - \sig_addr_posted_cntr_reg[2]_0\ <= \^sig_addr_posted_cntr_reg[2]_0\; - \sig_advance_pipe9_out__1\ <= \^sig_advance_pipe9_out__1\; - sig_data2addr_stop_req <= \^sig_data2addr_stop_req\; - sig_data2rsc_calc_err <= \^sig_data2rsc_calc_err\; - sig_data2rsc_slverr <= \^sig_data2rsc_slverr\; -\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_5\: unisim.vcomponents.LUT6 +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[4]\: unisim.vcomponents.FDRE generic map( - INIT => X"FFFF002000200020" + INIT => '0' ) port map ( - I0 => \^sig_data2addr_stop_req\, - I1 => sig_next_calc_error_reg, - I2 => sig_dqual_reg_full, - I3 => \sig_addr_posted_cntr_eq_0__1\, - I4 => sig_next_cmd_cmplt_reg, - I5 => m_axi_mm2s_rlast, - O => DIBDI(1) + C => s_axis_s2mm_aclk, + CE => '1', + D => '0', + Q => data_count_af_threshold_cdc_tig(4), + R => '0' ); -\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_6\: unisim.vcomponents.LUT6 +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[5]\: unisim.vcomponents.FDRE generic map( - INIT => X"FFFF002000200020" + INIT => '0' ) port map ( - I0 => \^sig_data2addr_stop_req\, - I1 => sig_next_calc_error_reg, - I2 => sig_dqual_reg_full, - I3 => \sig_addr_posted_cntr_eq_0__1\, - I4 => sig_next_eof_reg, - I5 => m_axi_mm2s_rlast, - O => DIBDI(0) + C => s_axis_s2mm_aclk, + CE => '1', + D => '0', + Q => data_count_af_threshold_cdc_tig(5), + R => '0' ); -\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_7\: unisim.vcomponents.LUT6 +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[6]\: unisim.vcomponents.FDRE generic map( - INIT => X"0000FE0000000000" + INIT => '0' ) port map ( - I0 => sig_addr_posted_cntr(2), - I1 => sig_addr_posted_cntr(0), - I2 => sig_addr_posted_cntr(1), - I3 => sig_dqual_reg_full, - I4 => sig_next_calc_error_reg, - I5 => \^sig_data2addr_stop_req\, - O => \mm2s_strm_wvalid0__1\ + C => s_axis_s2mm_aclk, + CE => '1', + D => '0', + Q => data_count_af_threshold_cdc_tig(6), + R => '0' ); -\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_8\: unisim.vcomponents.LUT6 +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[7]\: unisim.vcomponents.FDRE generic map( - INIT => X"000000000000FE00" + INIT => '0' ) port map ( - I0 => sig_addr_posted_cntr(2), - I1 => sig_addr_posted_cntr(0), - I2 => sig_addr_posted_cntr(1), - I3 => sig_dqual_reg_full, - I4 => sig_next_calc_error_reg, - I5 => sig_data2rsc_valid, - O => \^sig_advance_pipe9_out__1\ - ); -\GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO\: entity work.\Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized2\ - port map ( - D(7) => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_4\, - D(6) => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_5\, - D(5) => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_6\, - D(4) => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_7\, - D(3 downto 0) => p_0_in(3 downto 0), - E(0) => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_3\, - FIFO_Full_reg => FIFO_Full_reg, - Q(7 downto 0) => \sig_dbeat_cntr_reg__0\(7 downto 0), - SR(0) => SR(0), - \in\(7 downto 0) => \in\(7 downto 0), - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axi_mm2s_rlast => m_axi_mm2s_rlast, - m_axi_mm2s_rvalid => m_axi_mm2s_rvalid, - \out\(3 downto 0) => sig_cmd_fifo_data_out(35 downto 32), - ram_full_i_reg => \out\, - sel => sig_wr_fifo, - sig_addr_posted_cntr(2 downto 0) => sig_addr_posted_cntr(2 downto 0), - \sig_advance_pipe9_out__1\ => \^sig_advance_pipe9_out__1\, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_dbeat_cntr_eq_1 => sig_dbeat_cntr_eq_1, - \sig_dbeat_cntr_reg[2]\ => \sig_dbeat_cntr[7]_i_3_n_0\, - \sig_dbeat_cntr_reg[3]\ => \sig_dbeat_cntr[5]_i_2_n_0\, - \sig_dbeat_cntr_reg[4]\ => \sig_dbeat_cntr[7]_i_4_n_0\, - sig_dqual_reg_empty => sig_dqual_reg_empty, - sig_dqual_reg_full => sig_dqual_reg_full, - \sig_good_mmap_dbeat7_out__0\ => \sig_good_mmap_dbeat7_out__0\, - sig_halt_reg_reg => \^sig_data2addr_stop_req\, - sig_inhibit_rdy_n => sig_inhibit_rdy_n, - sig_init_done => sig_init_done, - sig_last_dbeat => sig_last_dbeat, - sig_last_dbeat_reg => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_18\, - sig_ld_new_cmd_reg => sig_ld_new_cmd_reg, - sig_ld_new_cmd_reg_reg => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_17\, - sig_mmap_reset_reg_reg => sig_mmap_reset_reg_reg, - sig_mstr2data_cmd_valid => sig_mstr2data_cmd_valid, - sig_next_calc_error_reg => sig_next_calc_error_reg, - sig_next_cmd_cmplt_reg_reg => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_19\, - sig_next_sequential_reg => sig_next_sequential_reg, - sig_push_dqual_reg => sig_push_dqual_reg, - sig_rsc2stat_status_valid => sig_rsc2stat_status_valid + C => s_axis_s2mm_aclk, + CE => '1', + D => '0', + Q => data_count_af_threshold_cdc_tig(7), + R => '0' ); -m_axi_mm2s_rready_INST_0: unisim.vcomponents.LUT6 +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[8]\: unisim.vcomponents.FDRE generic map( - INIT => X"0010001000000010" + INIT => '0' ) port map ( - I0 => sig_data2rsc_valid, - I1 => sig_next_calc_error_reg, - I2 => sig_dqual_reg_full, - I3 => \sig_addr_posted_cntr_eq_0__1\, - I4 => \out\, - I5 => \^sig_data2addr_stop_req\, - O => m_axi_mm2s_rready + C => s_axis_s2mm_aclk, + CE => '1', + D => '0', + Q => data_count_af_threshold_cdc_tig(8), + R => '0' ); -m_axi_mm2s_rready_INST_0_i_1: unisim.vcomponents.LUT3 +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_cdc_tig_reg[9]\: unisim.vcomponents.FDRE generic map( - INIT => X"01" + INIT => '0' ) port map ( - I0 => sig_addr_posted_cntr(1), - I1 => sig_addr_posted_cntr(0), - I2 => sig_addr_posted_cntr(2), - O => \sig_addr_posted_cntr_eq_0__1\ + C => s_axis_s2mm_aclk, + CE => '1', + D => '0', + Q => data_count_af_threshold_cdc_tig(9), + R => '0' ); -\sig_addr_posted_cntr[0]_i_1\: unisim.vcomponents.LUT5 +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => X"EA5555A8" + INIT => '0' ) port map ( - I0 => \^sig_addr_posted_cntr_reg[2]_0\, - I1 => sig_addr_posted_cntr(1), - I2 => sig_addr_posted_cntr(2), - I3 => sig_posted_to_axi_reg, - I4 => sig_addr_posted_cntr(0), - O => \sig_addr_posted_cntr[0]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => data_count_af_threshold_cdc_tig(0), + Q => data_count_af_threshold_d1(0), + R => '0' ); -\sig_addr_posted_cntr[1]_i_1\: unisim.vcomponents.LUT5 +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[10]\: unisim.vcomponents.FDRE generic map( - INIT => X"FA04DFA0" + INIT => '0' ) port map ( - I0 => sig_posted_to_axi_reg, - I1 => sig_addr_posted_cntr(2), - I2 => sig_addr_posted_cntr(0), - I3 => sig_addr_posted_cntr(1), - I4 => \^sig_addr_posted_cntr_reg[2]_0\, - O => \sig_addr_posted_cntr[1]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => data_count_af_threshold_cdc_tig(10), + Q => data_count_af_threshold_d1(10), + R => '0' ); -\sig_addr_posted_cntr[2]_i_1\: unisim.vcomponents.LUT5 +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[1]\: unisim.vcomponents.FDRE generic map( - INIT => X"CCC8ECCC" + INIT => '0' ) port map ( - I0 => sig_posted_to_axi_reg, - I1 => sig_addr_posted_cntr(2), - I2 => sig_addr_posted_cntr(0), - I3 => sig_addr_posted_cntr(1), - I4 => \^sig_addr_posted_cntr_reg[2]_0\, - O => \sig_addr_posted_cntr[2]_i_1_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => data_count_af_threshold_cdc_tig(1), + Q => data_count_af_threshold_d1(1), + R => '0' ); -\sig_addr_posted_cntr_reg[0]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, + C => s_axis_s2mm_aclk, CE => '1', - D => \sig_addr_posted_cntr[0]_i_1_n_0\, - Q => sig_addr_posted_cntr(0), - R => SR(0) + D => data_count_af_threshold_cdc_tig(2), + Q => data_count_af_threshold_d1(2), + R => '0' ); -\sig_addr_posted_cntr_reg[1]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, + C => s_axis_s2mm_aclk, CE => '1', - D => \sig_addr_posted_cntr[1]_i_1_n_0\, - Q => sig_addr_posted_cntr(1), - R => SR(0) + D => data_count_af_threshold_cdc_tig(3), + Q => data_count_af_threshold_d1(3), + R => '0' ); -\sig_addr_posted_cntr_reg[2]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, + C => s_axis_s2mm_aclk, CE => '1', - D => \sig_addr_posted_cntr[2]_i_1_n_0\, - Q => sig_addr_posted_cntr(2), - R => SR(0) + D => data_count_af_threshold_cdc_tig(4), + Q => data_count_af_threshold_d1(4), + R => '0' ); -sig_coelsc_decerr_reg_i_1: unisim.vcomponents.LUT4 +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[5]\: unisim.vcomponents.FDRE generic map( - INIT => X"FF80" + INIT => '0' ) port map ( - I0 => m_axi_mm2s_rresp(1), - I1 => m_axi_mm2s_rvalid, - I2 => m_axi_mm2s_rresp(0), - I3 => sig_data2rsc_decerr, - O => sig_coelsc_decerr_reg0 + C => s_axis_s2mm_aclk, + CE => '1', + D => data_count_af_threshold_cdc_tig(5), + Q => data_count_af_threshold_d1(5), + R => '0' ); -sig_coelsc_decerr_reg_reg: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_coelsc_reg, - D => sig_coelsc_decerr_reg0, - Q => sig_data2rsc_decerr, - R => sig_coelsc_reg_full_i_1_n_0 + C => s_axis_s2mm_aclk, + CE => '1', + D => data_count_af_threshold_cdc_tig(6), + Q => data_count_af_threshold_d1(6), + R => '0' ); -sig_coelsc_interr_reg_i_1: unisim.vcomponents.LUT2 +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[7]\: unisim.vcomponents.FDRE generic map( - INIT => X"E" + INIT => '0' ) port map ( - I0 => sig_next_calc_error_reg, - I1 => \^sig_data2rsc_calc_err\, - O => sig_coelsc_interr_reg0 + C => s_axis_s2mm_aclk, + CE => '1', + D => data_count_af_threshold_cdc_tig(7), + Q => data_count_af_threshold_d1(7), + R => '0' ); -sig_coelsc_interr_reg_reg: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_coelsc_reg, - D => sig_coelsc_interr_reg0, - Q => \^sig_data2rsc_calc_err\, - R => sig_coelsc_reg_full_i_1_n_0 + C => s_axis_s2mm_aclk, + CE => '1', + D => data_count_af_threshold_cdc_tig(8), + Q => data_count_af_threshold_d1(8), + R => '0' ); -sig_coelsc_reg_full_i_1: unisim.vcomponents.LUT5 +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.data_count_af_threshold_d1_reg[9]\: unisim.vcomponents.FDRE generic map( - INIT => X"2A00FFFF" + INIT => '0' ) port map ( - I0 => sig_data2rsc_valid, - I1 => sig_ld_new_cmd_reg, - I2 => sig_next_calc_error_reg, - I3 => sig_rsc2data_ready, - I4 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - O => sig_coelsc_reg_full_i_1_n_0 + C => s_axis_s2mm_aclk, + CE => '1', + D => data_count_af_threshold_cdc_tig(9), + Q => data_count_af_threshold_d1(9), + R => '0' ); -sig_coelsc_reg_full_i_2: unisim.vcomponents.LUT4 +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.fsync_src_select_cdc_tig_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => X"F444" + INIT => '0' ) port map ( - I0 => sig_data2rsc_valid, - I1 => \sig_good_mmap_dbeat7_out__0\, - I2 => sig_ld_new_cmd_reg, - I3 => sig_next_calc_error_reg, - O => sig_push_coelsc_reg + C => s_axis_s2mm_aclk, + CE => '1', + D => s2mm_dmacr(1), + Q => fsync_src_select_cdc_tig(0), + R => '0' ); -sig_coelsc_reg_full_i_3: unisim.vcomponents.LUT3 +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.fsync_src_select_cdc_tig_reg[1]\: unisim.vcomponents.FDRE generic map( - INIT => X"EA" + INIT => '0' ) port map ( - I0 => sig_next_calc_error_reg, - I1 => sig_next_cmd_cmplt_reg, - I2 => m_axi_mm2s_rlast, - O => sig_cmd_cmplt_last_dbeat + C => s_axis_s2mm_aclk, + CE => '1', + D => s2mm_dmacr(2), + Q => fsync_src_select_cdc_tig(1), + R => '0' ); -sig_coelsc_reg_full_reg: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.fsync_src_select_d1_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_coelsc_reg, - D => sig_cmd_cmplt_last_dbeat, - Q => sig_data2rsc_valid, - R => sig_coelsc_reg_full_i_1_n_0 + C => s_axis_s2mm_aclk, + CE => '1', + D => fsync_src_select_cdc_tig(0), + Q => fsync_src_select_d1(0), + R => '0' ); -sig_coelsc_slverr_reg_i_1: unisim.vcomponents.LUT4 +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.fsync_src_select_d1_reg[1]\: unisim.vcomponents.FDRE generic map( - INIT => X"FF08" + INIT => '0' ) port map ( - I0 => m_axi_mm2s_rresp(1), - I1 => m_axi_mm2s_rvalid, - I2 => m_axi_mm2s_rresp(0), - I3 => \^sig_data2rsc_slverr\, - O => sig_coelsc_slverr_reg0 + C => s_axis_s2mm_aclk, + CE => '1', + D => fsync_src_select_cdc_tig(1), + Q => fsync_src_select_d1(1), + R => '0' ); -sig_coelsc_slverr_reg_reg: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO\: entity work.\Arty_Z7_20_axi_vdma_0_0_axi_vdma_afifo_builtin__parameterized0\ + port map ( + D(12) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_1\, + D(11) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_2\, + D(10) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_3\, + D(9) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_4\, + D(8) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_5\, + D(7) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_6\, + D(6) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_7\, + D(5) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_8\, + D(4) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_9\, + D(3) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_10\, + D(2) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_11\, + D(1) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_12\, + D(0) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_13\, + DIN(8) => M_Last, + DIN(7 downto 0) => DIN(7 downto 0), + DOUT(8 downto 0) => DOUT(8 downto 0), + EMPTY => EMPTY, + FULL => fifo_full_i, + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ => \^s2mm_fsync_out_m_i\, + \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.crnt_vsize_d1_reg[12]\(12 downto 0) => crnt_vsize_d1(12 downto 0), + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]\ => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_14\, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_0\ => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_5_n_0\, + \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\ => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_25\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0]\(0) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0]\(0), + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\(12 downto 0) => D(12 downto 0), + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\, + M_VALID => M_VALID, + Q(6 downto 0) => done_vsize_counter(6 downto 0), + RD_EN => RD_EN, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + minusOp(11 downto 0) => minusOp(11 downto 0), + minusOp_1(11 downto 0) => minusOp_1(12 downto 1), + \out\ => \out\, + p_3_out => p_3_out, + s2mm_fsync_out_i => s2mm_fsync_out_i, + s2mm_strm_wready => s2mm_strm_wready, + s_axis_s2mm_aclk => s_axis_s2mm_aclk, + sig_reset_reg => sig_reset_reg, + strm_not_finished_no_dwidth => strm_not_finished_no_dwidth, + \vsize_vid_reg[12]\(12 downto 0) => Q(12 downto 0) + ); +\GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_coelsc_reg, - D => sig_coelsc_slverr_reg0, - Q => \^sig_data2rsc_slverr\, - R => sig_coelsc_reg_full_i_1_n_0 + C => s_axis_s2mm_aclk, + CE => '1', + D => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.RUNSTOP_AXIS_0_CDC_I_FLUSH_SOF_n_1\, + Q => delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s, + R => '0' ); -\sig_dbeat_cntr[5]_i_2\: unisim.vcomponents.LUT5 +\GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1_reg\: unisim.vcomponents.FDRE generic map( - INIT => X"FFFFFFFE" + INIT => '0' ) port map ( - I0 => \sig_dbeat_cntr_reg__0\(3), - I1 => \sig_dbeat_cntr_reg__0\(1), - I2 => \sig_dbeat_cntr_reg__0\(0), - I3 => \sig_dbeat_cntr_reg__0\(2), - I4 => \sig_dbeat_cntr_reg__0\(4), - O => \sig_dbeat_cntr[5]_i_2_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s, + Q => delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1, + R => prmry_reset2 ); -\sig_dbeat_cntr[7]_i_3\: unisim.vcomponents.LUT6 +\GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_d1_reg\: unisim.vcomponents.FDRE generic map( - INIT => X"AAAAAAAAAAAAAAA8" + INIT => '0' ) port map ( - I0 => \sig_good_mmap_dbeat7_out__0\, - I1 => \sig_dbeat_cntr_reg__0\(2), - I2 => \sig_dbeat_cntr_reg__0\(3), - I3 => \sig_dbeat_cntr_reg__0\(0), - I4 => \sig_dbeat_cntr_reg__0\(1), - I5 => \sig_dbeat_cntr[7]_i_5_n_0\, - O => \sig_dbeat_cntr[7]_i_3_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\, + Q => delay_s2mm_fsync_core_till_mmap_done_flag_d1, + R => '0' ); -\sig_dbeat_cntr[7]_i_4\: unisim.vcomponents.LUT6 +\GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_reg\: unisim.vcomponents.FDRE generic map( - INIT => X"FFFFFFFFFFFFFFFE" + INIT => '0' ) port map ( - I0 => \sig_dbeat_cntr_reg__0\(4), - I1 => \sig_dbeat_cntr_reg__0\(2), - I2 => \sig_dbeat_cntr_reg__0\(0), - I3 => \sig_dbeat_cntr_reg__0\(1), - I4 => \sig_dbeat_cntr_reg__0\(3), - I5 => \sig_dbeat_cntr_reg__0\(5), - O => \sig_dbeat_cntr[7]_i_4_n_0\ + C => s_axis_s2mm_aclk, + CE => '1', + D => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF_n_1\, + Q => \^delay_s2mm_fsync_core_till_mmap_done_flag\, + R => '0' ); -\sig_dbeat_cntr[7]_i_5\: unisim.vcomponents.LUT4 +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_10\: unisim.vcomponents.LUT1 generic map( - INIT => X"FFFE" + INIT => X"1" ) port map ( - I0 => \sig_dbeat_cntr_reg__0\(7), - I1 => \sig_dbeat_cntr_reg__0\(6), - I2 => \sig_dbeat_cntr_reg__0\(4), - I3 => \sig_dbeat_cntr_reg__0\(5), - O => \sig_dbeat_cntr[7]_i_5_n_0\ + I0 => done_vsize_counter(12), + O => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_10_n_0\ ); -\sig_dbeat_cntr_reg[0]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_11\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"1" ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_3\, - D => p_0_in(0), - Q => \sig_dbeat_cntr_reg__0\(0), - R => SR(0) + I0 => done_vsize_counter(11), + O => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_11_n_0\ ); -\sig_dbeat_cntr_reg[1]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_12\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"1" ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_3\, - D => p_0_in(1), - Q => \sig_dbeat_cntr_reg__0\(1), - R => SR(0) + I0 => done_vsize_counter(10), + O => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_12_n_0\ ); -\sig_dbeat_cntr_reg[2]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_13\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"1" ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_3\, - D => p_0_in(2), - Q => \sig_dbeat_cntr_reg__0\(2), - R => SR(0) + I0 => done_vsize_counter(9), + O => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_13_n_0\ ); -\sig_dbeat_cntr_reg[3]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_5\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"FFFFFFFFFFFFFFFE" ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_3\, - D => p_0_in(3), - Q => \sig_dbeat_cntr_reg__0\(3), - R => SR(0) + I0 => done_vsize_counter(12), + I1 => done_vsize_counter(10), + I2 => done_vsize_counter(7), + I3 => done_vsize_counter(11), + I4 => done_vsize_counter(8), + I5 => done_vsize_counter(9), + O => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_5_n_0\ ); -\sig_dbeat_cntr_reg[4]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_6\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"E" ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_3\, - D => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_7\, - Q => \sig_dbeat_cntr_reg__0\(4), - R => SR(0) + I0 => done_vsize_counter(3), + I1 => done_vsize_counter(4), + O => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_6_n_0\ ); -\sig_dbeat_cntr_reg[5]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_7\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"FFFE" ) - port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_3\, - D => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_6\, - Q => \sig_dbeat_cntr_reg__0\(5), - R => SR(0) + port map ( + I0 => done_vsize_counter(6), + I1 => done_vsize_counter(1), + I2 => done_vsize_counter(5), + I3 => done_vsize_counter(2), + O => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_7_n_0\ ); -\sig_dbeat_cntr_reg[6]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_3\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"1" ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_3\, - D => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_5\, - Q => \sig_dbeat_cntr_reg__0\(6), - R => SR(0) + I0 => done_vsize_counter(4), + O => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_3_n_0\ ); -\sig_dbeat_cntr_reg[7]\: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_4\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"1" ) port map ( - C => m_axi_mm2s_aclk, - CE => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_3\, - D => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_4\, - Q => \sig_dbeat_cntr_reg__0\(7), - R => SR(0) + I0 => done_vsize_counter(3), + O => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_4_n_0\ ); -sig_dqual_reg_empty_reg: unisim.vcomponents.FDSE +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_5\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"1" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_dqual_reg, - D => '0', - Q => sig_dqual_reg_empty, - S => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_19\ + I0 => done_vsize_counter(2), + O => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_5_n_0\ ); -sig_dqual_reg_full_reg: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_6\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"1" ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_dqual_reg, - D => sig_push_dqual_reg, - Q => sig_dqual_reg_full, - R => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_19\ + I0 => done_vsize_counter(1), + O => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_6_n_0\ ); -sig_halt_cmplt_i_1: unisim.vcomponents.LUT5 +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_3\: unisim.vcomponents.LUT1 generic map( - INIT => X"FFFF8880" + INIT => X"1" ) port map ( - I0 => sig_data2rst_stop_cmplt, - I1 => \^sig_data2addr_stop_req\, - I2 => sig_addr2rsc_calc_error, - I3 => sig_addr_reg_empty, - I4 => mm2s_halt_cmplt, - O => sig_halt_cmplt_reg + I0 => done_vsize_counter(8), + O => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_3_n_0\ ); -sig_halt_cmplt_i_2: unisim.vcomponents.LUT5 +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_4\: unisim.vcomponents.LUT1 generic map( - INIT => X"8888888A" + INIT => X"1" ) port map ( - I0 => sig_halt_reg_dly3, - I1 => sig_next_calc_error_reg, - I2 => sig_addr_posted_cntr(1), - I3 => sig_addr_posted_cntr(0), - I4 => sig_addr_posted_cntr(2), - O => sig_data2rst_stop_cmplt + I0 => done_vsize_counter(7), + O => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_4_n_0\ ); -sig_halt_reg_dly1_reg: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_5\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"1" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \^sig_data2addr_stop_req\, - Q => sig_halt_reg_dly1, - R => SR(0) + I0 => done_vsize_counter(6), + O => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_5_n_0\ ); -sig_halt_reg_dly2_reg: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_6\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"1" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => sig_halt_reg_dly1, - Q => sig_halt_reg_dly2, - R => SR(0) + I0 => done_vsize_counter(5), + O => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_6_n_0\ ); -sig_halt_reg_dly3_reg: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => sig_halt_reg_dly2, - Q => sig_halt_reg_dly3, - R => SR(0) + C => m_axi_s2mm_aclk, + CE => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3\, + D => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_13\, + Q => done_vsize_counter(0), + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg\(0) ); -sig_halt_reg_reg: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => sig_s_h_halt_reg_reg, - Q => \^sig_data2addr_stop_req\, - R => SR(0) + C => m_axi_s2mm_aclk, + CE => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3\, + D => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_3\, + Q => done_vsize_counter(10), + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg\(0) ); -sig_last_dbeat_i_3: unisim.vcomponents.LUT5 +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[11]\: unisim.vcomponents.FDRE generic map( - INIT => X"00000010" + INIT => '0' ) port map ( - I0 => \sig_dbeat_cntr[7]_i_5_n_0\, - I1 => \sig_dbeat_cntr_reg__0\(1), - I2 => \sig_dbeat_cntr_reg__0\(0), - I3 => \sig_dbeat_cntr_reg__0\(3), - I4 => \sig_dbeat_cntr_reg__0\(2), - O => sig_dbeat_cntr_eq_1 + C => m_axi_s2mm_aclk, + CE => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3\, + D => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_2\, + Q => done_vsize_counter(11), + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg\(0) ); -sig_last_dbeat_reg: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_18\, - Q => sig_last_dbeat, - R => SR(0) + C => m_axi_s2mm_aclk, + CE => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3\, + D => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_1\, + Q => done_vsize_counter(12), + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg\(0) ); -sig_last_mmap_dbeat_reg_i_1: unisim.vcomponents.LUT2 +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_i_8\: unisim.vcomponents.CARRY4 + port map ( + CI => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[8]_i_2_n_0\, + CO(3) => \NLW_GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_i_8_CO_UNCONNECTED\(3), + CO(2) => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_i_8_n_1\, + CO(1) => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_i_8_n_2\, + CO(0) => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[12]_i_8_n_3\, + CYINIT => '0', + DI(3) => '0', + DI(2 downto 0) => done_vsize_counter(11 downto 9), + O(3 downto 0) => minusOp_1(12 downto 9), + S(3) => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_10_n_0\, + S(2) => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_11_n_0\, + S(1) => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_12_n_0\, + S(0) => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[12]_i_13_n_0\ + ); +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[1]\: unisim.vcomponents.FDRE generic map( - INIT => X"8" + INIT => '0' ) port map ( - I0 => m_axi_mm2s_rlast, - I1 => \sig_good_mmap_dbeat7_out__0\, - O => sig_last_mmap_dbeat + C => m_axi_s2mm_aclk, + CE => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3\, + D => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_12\, + Q => done_vsize_counter(1), + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg\(0) ); -sig_last_mmap_dbeat_reg_reg: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => sig_last_mmap_dbeat, - Q => \^sig_addr_posted_cntr_reg[2]_0\, - R => SR(0) + C => m_axi_s2mm_aclk, + CE => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3\, + D => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_11\, + Q => done_vsize_counter(2), + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg\(0) ); -sig_ld_new_cmd_reg_reg: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_17\, - Q => sig_ld_new_cmd_reg, - R => '0' + C => m_axi_s2mm_aclk, + CE => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3\, + D => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_10\, + Q => done_vsize_counter(3), + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg\(0) ); -sig_next_calc_error_reg_reg: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_dqual_reg, - D => sig_cmd_fifo_data_out(35), - Q => sig_next_calc_error_reg, - R => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_19\ + C => m_axi_s2mm_aclk, + CE => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3\, + D => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_9\, + Q => done_vsize_counter(4), + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg\(0) ); -sig_next_cmd_cmplt_reg_reg: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[4]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[4]_i_2_n_0\, + CO(2) => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[4]_i_2_n_1\, + CO(1) => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[4]_i_2_n_2\, + CO(0) => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[4]_i_2_n_3\, + CYINIT => done_vsize_counter(0), + DI(3 downto 0) => done_vsize_counter(4 downto 1), + O(3 downto 0) => minusOp_1(4 downto 1), + S(3) => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_3_n_0\, + S(2) => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_4_n_0\, + S(1) => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_5_n_0\, + S(0) => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[4]_i_6_n_0\ + ); +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_dqual_reg, - D => sig_cmd_fifo_data_out(34), - Q => sig_next_cmd_cmplt_reg, - R => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_19\ + C => m_axi_s2mm_aclk, + CE => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3\, + D => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_8\, + Q => done_vsize_counter(5), + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg\(0) ); -sig_next_eof_reg_reg: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_dqual_reg, - D => sig_cmd_fifo_data_out(32), - Q => sig_next_eof_reg, - R => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_19\ + C => m_axi_s2mm_aclk, + CE => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3\, + D => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_7\, + Q => done_vsize_counter(6), + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg\(0) ); -sig_next_sequential_reg_reg: unisim.vcomponents.FDRE +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, - CE => sig_push_dqual_reg, - D => sig_cmd_fifo_data_out(33), - Q => sig_next_sequential_reg, - R => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO_n_19\ + C => m_axi_s2mm_aclk, + CE => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3\, + D => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_6\, + Q => done_vsize_counter(7), + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg\(0) ); -sig_rd_sts_decerr_reg_i_1: unisim.vcomponents.LUT2 +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[8]\: unisim.vcomponents.FDRE generic map( - INIT => X"E" + INIT => '0' ) port map ( - I0 => sig_data2rsc_decerr, - I1 => sig_rd_sts_decerr_reg_reg(0), - O => sig_rd_sts_decerr_reg0 + C => m_axi_s2mm_aclk, + CE => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3\, + D => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_5\, + Q => done_vsize_counter(8), + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg\(0) ); -sig_rd_sts_reg_empty_i_1: unisim.vcomponents.LUT2 +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[8]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[4]_i_2_n_0\, + CO(3) => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[8]_i_2_n_0\, + CO(2) => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[8]_i_2_n_1\, + CO(1) => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[8]_i_2_n_2\, + CO(0) => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[8]_i_2_n_3\, + CYINIT => '0', + DI(3 downto 0) => done_vsize_counter(8 downto 5), + O(3 downto 0) => minusOp_1(8 downto 5), + S(3) => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_3_n_0\, + S(2) => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_4_n_0\, + S(1) => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_5_n_0\, + S(0) => \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter[8]_i_6_n_0\ + ); +\GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[9]\: unisim.vcomponents.FDRE generic map( - INIT => X"1" + INIT => '0' ) port map ( - I0 => sig_data2rsc_valid, - I1 => \^sig_data2rsc_calc_err\, - O => sig_rd_sts_reg_empty_reg + C => m_axi_s2mm_aclk, + CE => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3\, + D => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_4\, + Q => done_vsize_counter(9), + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg\(0) ); -sig_rd_sts_reg_full_i_2: unisim.vcomponents.LUT2 +\GEN_S2MM_FLUSH_SOF_LOGIC.fsize_err_to_dm_halt_flag_reg\: unisim.vcomponents.FDRE generic map( - INIT => X"8" + INIT => '0' ) port map ( - I0 => sig_data2rsc_valid, - I1 => sig_rsc2data_ready, - O => sig_push_rd_sts_reg + C => s_axis_s2mm_aclk, + CE => '1', + D => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.STRM_WR_HALT_CDC_I_n_7\, + Q => fsize_err_to_dm_halt_flag, + R => '0' ); -sig_rd_sts_reg_full_i_3: unisim.vcomponents.LUT2 +\GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg\: unisim.vcomponents.FDRE generic map( - INIT => X"E" + INIT => '0' ) port map ( - I0 => \^sig_data2rsc_calc_err\, - I1 => sig_data2rsc_valid, - O => sig_rd_sts_reg_full0 + C => m_axi_s2mm_aclk, + CE => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_3\, + D => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF_n_2\, + Q => \GEN_S2MM_FLUSH_SOF_LOGIC.mmap_not_finished_reg_n_0\, + R => \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg\(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5_synth is +entity \Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized1\ is port ( DOBDO : out STD_LOGIC_VECTOR ( 0 to 0 ); - \sig_user_skid_reg_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : out STD_LOGIC; + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC; + sig_ok_to_post_rd_addr_reg : out STD_LOGIC; + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : out STD_LOGIC; + hold_ff_q_reg : out STD_LOGIC; + \gc1.count_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INFERRED_GEN.cnt_i_reg[2]\ : out STD_LOGIC; + DIN : out STD_LOGIC_VECTOR ( 0 to 0 ); + \sig_user_skid_reg_reg[0]\ : out STD_LOGIC; dm2linebuf_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : out STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[0]\ : out STD_LOGIC; m_axi_mm2s_aclk : in STD_LOGIC; - ram_empty_fb_i_reg : in STD_LOGIC; - ram_full_i_reg : in STD_LOGIC; - \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC; - sig_stream_rst : in STD_LOGIC; - \gc1.count_d2_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); - Q : in STD_LOGIC_VECTOR ( 6 downto 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ); - lsig_0ffset_cntr : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_posted_to_axi_2_reg : in STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); lsig_cmd_loaded : in STD_LOGIC; - \gpregsm1.user_valid_reg\ : in STD_LOGIC; hold_ff_q : in STD_LOGIC; - p_0_out : in STD_LOGIC_VECTOR ( 0 to 0 ); - dm2linebuf_mm2s_tvalid : in STD_LOGIC; - p_8_out : in STD_LOGIC; - \fifo_wren__0\ : in STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ram_full_i_reg : in STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ : in STD_LOGIC; + \sig_token_cntr_reg[0]\ : in STD_LOGIC; + \sig_token_cntr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + ram_full_i_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth"; -end Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5_synth; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized1\ : entity is "fifo_generator_top"; +end \Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized1\; -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5_synth is +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized1\ is begin -\gnbram.gnativebmg.native_blk_mem_gen\: entity work.Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_top +\grf.rf\: entity work.Arty_Z7_20_axi_vdma_0_0_fifo_generator_ramfifo port map ( + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\, DIBDI(1 downto 0) => DIBDI(1 downto 0), + DIN(0) => DIN(0), DOBDO(0) => DOBDO(0), + E(0) => E(0), \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, - \INFERRED_GEN.cnt_i_reg[0]\ => \INFERRED_GEN.cnt_i_reg[0]\, - \INFERRED_GEN.cnt_i_reg[2]\(0) => \INFERRED_GEN.cnt_i_reg[2]\(0), - Q(6 downto 0) => Q(6 downto 0), + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, + \INFERRED_GEN.cnt_i_reg[2]\ => \INFERRED_GEN.cnt_i_reg[2]\, + Q(0) => Q(0), + SR(0) => SR(0), dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), - dm2linebuf_mm2s_tvalid => dm2linebuf_mm2s_tvalid, - \fifo_wren__0\ => \fifo_wren__0\, - \gc1.count_d2_reg[6]\(6 downto 0) => \gc1.count_d2_reg[6]\(6 downto 0), - \gpregsm1.curr_fwft_state_reg[0]\ => \gpregsm1.curr_fwft_state_reg[0]\, - \gpregsm1.user_valid_reg\ => \gpregsm1.user_valid_reg\, + \gc1.count_reg[7]\ => \gc1.count_reg[7]\(0), hold_ff_q => hold_ff_q, - lsig_0ffset_cntr => lsig_0ffset_cntr, + hold_ff_q_reg => hold_ff_q_reg, lsig_cmd_loaded => lsig_cmd_loaded, m_axi_mm2s_aclk => m_axi_mm2s_aclk, m_axi_mm2s_rdata(63 downto 0) => m_axi_mm2s_rdata(63 downto 0), - p_0_out(0) => p_0_out(0), - p_8_out => p_8_out, - ram_empty_fb_i_reg => ram_empty_fb_i_reg, + \out\ => \out\, ram_full_i_reg => ram_full_i_reg, - sig_stream_rst => sig_stream_rst, - \sig_user_skid_reg_reg[0]\(0) => \sig_user_skid_reg_reg[0]\(0) + ram_full_i_reg_0(0) => ram_full_i_reg_0(0), + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_ok_to_post_rd_addr_reg => sig_ok_to_post_rd_addr_reg, + sig_posted_to_axi_2_reg => sig_posted_to_axi_2_reg, + \sig_token_cntr_reg[0]\ => \sig_token_cntr_reg[0]\, + \sig_token_cntr_reg[3]\(3 downto 0) => \sig_token_cntr_reg[3]\(3 downto 0), + \sig_user_skid_reg_reg[0]\ => \sig_user_skid_reg_reg[0]\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_fifo_generator_top is +entity \Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized3\ is port ( - fifo_full_i : out STD_LOGIC; - sig_m_valid_out_reg : out STD_LOGIC; - fifo_dout : out STD_LOGIC_VECTOR ( 33 downto 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - s_axis_fifo_ainit_nosync_reg : in STD_LOGIC; - m_axis_mm2s_aclk : in STD_LOGIC; - \fifo_wren__0\ : in STD_LOGIC; - \out\ : in STD_LOGIC; - dm2linebuf_mm2s_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - DIN : in STD_LOGIC_VECTOR ( 1 downto 0 ) + sig_data_fifo_data_out : out STD_LOGIC_VECTOR ( 65 downto 0 ); + \out\ : out STD_LOGIC; + \gcc0.gc0.count_d1_reg[7]\ : out STD_LOGIC; + hold_ff_q_reg : out STD_LOGIC; + \INCLUDE_PACKING.lsig_packer_full_reg\ : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_data_fifo_dvalid : out STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + lsig_combined_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); + DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ); + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + hold_ff_q_reg_0 : in STD_LOGIC; + sig_s_ready_out_reg : in STD_LOGIC; + \lsig_set_packer_full__1\ : in STD_LOGIC; + lsig_packer_full : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_fifo_generator_top : entity is "fifo_generator_top"; -end Arty_Z7_20_axi_vdma_0_0_fifo_generator_top; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized3\ : entity is "fifo_generator_top"; +end \Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized3\; -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_fifo_generator_top is +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized3\ is begin -\gbi.bi\: entity work.Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_builtin +\grf.rf\: entity work.\Arty_Z7_20_axi_vdma_0_0_fifo_generator_ramfifo__parameterized1\ port map ( - DIN(1 downto 0) => DIN(1 downto 0), - dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), - fifo_dout(33 downto 0) => fifo_dout(33 downto 0), - fifo_full_i => fifo_full_i, - \fifo_wren__0\ => \fifo_wren__0\, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axis_mm2s_aclk => m_axis_mm2s_aclk, + DIBDI(1 downto 0) => DIBDI(1 downto 0), + E(0) => E(0), + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0]\(0), + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0\, + \INCLUDE_PACKING.lsig_packer_full_reg\ => \INCLUDE_PACKING.lsig_packer_full_reg\, + \gcc0.gc0.count_d1_reg[7]\ => \gcc0.gc0.count_d1_reg[7]\, + hold_ff_q_reg => hold_ff_q_reg, + hold_ff_q_reg_0 => hold_ff_q_reg_0, + lsig_combined_data(63 downto 0) => lsig_combined_data(63 downto 0), + lsig_packer_full => lsig_packer_full, + \lsig_set_packer_full__1\ => \lsig_set_packer_full__1\, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, \out\ => \out\, - s_axis_fifo_ainit_nosync_reg => s_axis_fifo_ainit_nosync_reg, - sig_m_valid_out_reg => sig_m_valid_out_reg + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_data_fifo_data_out(65 downto 0) => sig_data_fifo_data_out(65 downto 0), + sig_data_fifo_dvalid => sig_data_fifo_dvalid, + sig_s_ready_out_reg => sig_s_ready_out_reg, + sig_stream_rst => sig_stream_rst ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5 is +entity \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized1\ is port ( DOBDO : out STD_LOGIC_VECTOR ( 0 to 0 ); - \sig_user_skid_reg_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : out STD_LOGIC; + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC; + sig_ok_to_post_rd_addr_reg : out STD_LOGIC; + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : out STD_LOGIC; + hold_ff_q_reg : out STD_LOGIC; + \gc1.count_reg[7]\ : out STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[2]\ : out STD_LOGIC; + DIN : out STD_LOGIC_VECTOR ( 0 to 0 ); + \sig_user_skid_reg_reg[0]\ : out STD_LOGIC; dm2linebuf_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : out STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[0]\ : out STD_LOGIC; m_axi_mm2s_aclk : in STD_LOGIC; - ram_empty_fb_i_reg : in STD_LOGIC; - ram_full_i_reg : in STD_LOGIC; - \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC; - sig_stream_rst : in STD_LOGIC; - \gc1.count_d2_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); - Q : in STD_LOGIC_VECTOR ( 6 downto 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ); - lsig_0ffset_cntr : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_posted_to_axi_2_reg : in STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); lsig_cmd_loaded : in STD_LOGIC; - \gpregsm1.user_valid_reg\ : in STD_LOGIC; hold_ff_q : in STD_LOGIC; - p_0_out : in STD_LOGIC_VECTOR ( 0 to 0 ); - dm2linebuf_mm2s_tvalid : in STD_LOGIC; - p_8_out : in STD_LOGIC; - \fifo_wren__0\ : in STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ram_full_i_reg : in STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ : in STD_LOGIC; + \sig_token_cntr_reg[0]\ : in STD_LOGIC; + \sig_token_cntr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + ram_full_i_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5"; -end Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized1\ : entity is "fifo_generator_v13_1_3_synth"; +end \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized1\; -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5 is +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized1\ is begin -inst_blk_mem_gen: entity work.Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5_synth +\gconvfifo.rf\: entity work.\Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized1\ port map ( + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\, DIBDI(1 downto 0) => DIBDI(1 downto 0), + DIN(0) => DIN(0), DOBDO(0) => DOBDO(0), + E(0) => E(0), \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, - \INFERRED_GEN.cnt_i_reg[0]\ => \INFERRED_GEN.cnt_i_reg[0]\, - \INFERRED_GEN.cnt_i_reg[2]\(0) => \INFERRED_GEN.cnt_i_reg[2]\(0), - Q(6 downto 0) => Q(6 downto 0), + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, + \INFERRED_GEN.cnt_i_reg[2]\ => \INFERRED_GEN.cnt_i_reg[2]\, + Q(0) => Q(0), + SR(0) => SR(0), dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), - dm2linebuf_mm2s_tvalid => dm2linebuf_mm2s_tvalid, - \fifo_wren__0\ => \fifo_wren__0\, - \gc1.count_d2_reg[6]\(6 downto 0) => \gc1.count_d2_reg[6]\(6 downto 0), - \gpregsm1.curr_fwft_state_reg[0]\ => \gpregsm1.curr_fwft_state_reg[0]\, - \gpregsm1.user_valid_reg\ => \gpregsm1.user_valid_reg\, + \gc1.count_reg[7]\(0) => \gc1.count_reg[7]\, hold_ff_q => hold_ff_q, - lsig_0ffset_cntr => lsig_0ffset_cntr, + hold_ff_q_reg => hold_ff_q_reg, lsig_cmd_loaded => lsig_cmd_loaded, m_axi_mm2s_aclk => m_axi_mm2s_aclk, m_axi_mm2s_rdata(63 downto 0) => m_axi_mm2s_rdata(63 downto 0), - p_0_out(0) => p_0_out(0), - p_8_out => p_8_out, - ram_empty_fb_i_reg => ram_empty_fb_i_reg, + \out\ => \out\, ram_full_i_reg => ram_full_i_reg, - sig_stream_rst => sig_stream_rst, - \sig_user_skid_reg_reg[0]\(0) => \sig_user_skid_reg_reg[0]\(0) + ram_full_i_reg_0(0) => ram_full_i_reg_0(0), + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_ok_to_post_rd_addr_reg => sig_ok_to_post_rd_addr_reg, + sig_posted_to_axi_2_reg => sig_posted_to_axi_2_reg, + \sig_token_cntr_reg[0]\ => \sig_token_cntr_reg[0]\, + \sig_token_cntr_reg[3]\(3 downto 0) => \sig_token_cntr_reg[3]\(3 downto 0), + \sig_user_skid_reg_reg[0]\ => \sig_user_skid_reg_reg[0]\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth is +entity \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized3\ is port ( - fifo_full_i : out STD_LOGIC; - sig_m_valid_out_reg : out STD_LOGIC; - fifo_dout : out STD_LOGIC_VECTOR ( 33 downto 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - s_axis_fifo_ainit_nosync_reg : in STD_LOGIC; - m_axis_mm2s_aclk : in STD_LOGIC; - \fifo_wren__0\ : in STD_LOGIC; - \out\ : in STD_LOGIC; - dm2linebuf_mm2s_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - DIN : in STD_LOGIC_VECTOR ( 1 downto 0 ) + sig_data_fifo_data_out : out STD_LOGIC_VECTOR ( 65 downto 0 ); + \out\ : out STD_LOGIC; + \gcc0.gc0.count_d1_reg[7]\ : out STD_LOGIC; + hold_ff_q_reg : out STD_LOGIC; + \INCLUDE_PACKING.lsig_packer_full_reg\ : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_data_fifo_dvalid : out STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + lsig_combined_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); + DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ); + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + hold_ff_q_reg_0 : in STD_LOGIC; + sig_s_ready_out_reg : in STD_LOGIC; + \lsig_set_packer_full__1\ : in STD_LOGIC; + lsig_packer_full : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth : entity is "fifo_generator_v13_1_3_synth"; -end Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized3\ : entity is "fifo_generator_v13_1_3_synth"; +end \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized3\; -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth is +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized3\ is begin -\gconvfifo.rf\: entity work.Arty_Z7_20_axi_vdma_0_0_fifo_generator_top +\gconvfifo.rf\: entity work.\Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized3\ port map ( - DIN(1 downto 0) => DIN(1 downto 0), - dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), - fifo_dout(33 downto 0) => fifo_dout(33 downto 0), - fifo_full_i => fifo_full_i, - \fifo_wren__0\ => \fifo_wren__0\, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axis_mm2s_aclk => m_axis_mm2s_aclk, + DIBDI(1 downto 0) => DIBDI(1 downto 0), + E(0) => E(0), + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0]\(0), + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0\, + \INCLUDE_PACKING.lsig_packer_full_reg\ => \INCLUDE_PACKING.lsig_packer_full_reg\, + \gcc0.gc0.count_d1_reg[7]\ => \gcc0.gc0.count_d1_reg[7]\, + hold_ff_q_reg => hold_ff_q_reg, + hold_ff_q_reg_0 => hold_ff_q_reg_0, + lsig_combined_data(63 downto 0) => lsig_combined_data(63 downto 0), + lsig_packer_full => lsig_packer_full, + \lsig_set_packer_full__1\ => \lsig_set_packer_full__1\, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, \out\ => \out\, - s_axis_fifo_ainit_nosync_reg => s_axis_fifo_ainit_nosync_reg, - sig_m_valid_out_reg => sig_m_valid_out_reg + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_data_fifo_data_out(65 downto 0) => sig_data_fifo_data_out(65 downto 0), + sig_data_fifo_dvalid => sig_data_fifo_dvalid, + sig_s_ready_out_reg => sig_s_ready_out_reg, + sig_stream_rst => sig_stream_rst ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3 is +entity \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized1\ is port ( - fifo_full_i : out STD_LOGIC; - sig_m_valid_out_reg : out STD_LOGIC; - fifo_dout : out STD_LOGIC_VECTOR ( 33 downto 0 ); + DOBDO : out STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : out STD_LOGIC; + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC; + sig_ok_to_post_rd_addr_reg : out STD_LOGIC; + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : out STD_LOGIC; + hold_ff_q_reg : out STD_LOGIC; + \gc1.count_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INFERRED_GEN.cnt_i_reg[2]\ : out STD_LOGIC; + DIN : out STD_LOGIC_VECTOR ( 0 to 0 ); + \sig_user_skid_reg_reg[0]\ : out STD_LOGIC; + dm2linebuf_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_mm2s_aclk : in STD_LOGIC; - s_axis_fifo_ainit_nosync_reg : in STD_LOGIC; - m_axis_mm2s_aclk : in STD_LOGIC; - \fifo_wren__0\ : in STD_LOGIC; - \out\ : in STD_LOGIC; - dm2linebuf_mm2s_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - DIN : in STD_LOGIC_VECTOR ( 1 downto 0 ) + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ); + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_posted_to_axi_2_reg : in STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + lsig_cmd_loaded : in STD_LOGIC; + hold_ff_q : in STD_LOGIC; + ram_full_i_reg : in STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ : in STD_LOGIC; + \sig_token_cntr_reg[0]\ : in STD_LOGIC; + \sig_token_cntr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + ram_full_i_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3 : entity is "fifo_generator_v13_1_3"; -end Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized1\ : entity is "fifo_generator_v13_1_3"; +end \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized1\; -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3 is +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized1\ is begin -inst_fifo_gen: entity work.Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth +inst_fifo_gen: entity work.\Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized1\ port map ( - DIN(1 downto 0) => DIN(1 downto 0), + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\, + DIBDI(1 downto 0) => DIBDI(1 downto 0), + DIN(0) => DIN(0), + DOBDO(0) => DOBDO(0), + E(0) => E(0), + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, + \INFERRED_GEN.cnt_i_reg[2]\ => \INFERRED_GEN.cnt_i_reg[2]\, + Q(0) => Q(0), + SR(0) => SR(0), dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), - fifo_dout(33 downto 0) => fifo_dout(33 downto 0), - fifo_full_i => fifo_full_i, - \fifo_wren__0\ => \fifo_wren__0\, + \gc1.count_reg[7]\ => \gc1.count_reg[7]\(0), + hold_ff_q => hold_ff_q, + hold_ff_q_reg => hold_ff_q_reg, + lsig_cmd_loaded => lsig_cmd_loaded, m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axis_mm2s_aclk => m_axis_mm2s_aclk, + m_axi_mm2s_rdata(63 downto 0) => m_axi_mm2s_rdata(63 downto 0), \out\ => \out\, - s_axis_fifo_ainit_nosync_reg => s_axis_fifo_ainit_nosync_reg, - sig_m_valid_out_reg => sig_m_valid_out_reg + ram_full_i_reg => ram_full_i_reg, + ram_full_i_reg_0(0) => ram_full_i_reg_0(0), + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_ok_to_post_rd_addr_reg => sig_ok_to_post_rd_addr_reg, + sig_posted_to_axi_2_reg => sig_posted_to_axi_2_reg, + \sig_token_cntr_reg[0]\ => \sig_token_cntr_reg[0]\, + \sig_token_cntr_reg[3]\(3 downto 0) => \sig_token_cntr_reg[3]\(3 downto 0), + \sig_user_skid_reg_reg[0]\ => \sig_user_skid_reg_reg[0]\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_memory is +entity \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized3\ is + port ( + sig_data_fifo_data_out : out STD_LOGIC_VECTOR ( 65 downto 0 ); + \out\ : out STD_LOGIC; + \gcc0.gc0.count_d1_reg[7]\ : out STD_LOGIC; + hold_ff_q_reg : out STD_LOGIC; + \INCLUDE_PACKING.lsig_packer_full_reg\ : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_data_fifo_dvalid : out STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + lsig_combined_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); + DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ); + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + hold_ff_q_reg_0 : in STD_LOGIC; + sig_s_ready_out_reg : in STD_LOGIC; + \lsig_set_packer_full__1\ : in STD_LOGIC; + lsig_packer_full : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized3\ : entity is "fifo_generator_v13_1_3"; +end \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized3\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized3\ is +begin +inst_fifo_gen: entity work.\Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized3\ + port map ( + DIBDI(1 downto 0) => DIBDI(1 downto 0), + E(0) => E(0), + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0]\(0), + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0\, + \INCLUDE_PACKING.lsig_packer_full_reg\ => \INCLUDE_PACKING.lsig_packer_full_reg\, + \gcc0.gc0.count_d1_reg[7]\ => \gcc0.gc0.count_d1_reg[7]\, + hold_ff_q_reg => hold_ff_q_reg, + hold_ff_q_reg_0 => hold_ff_q_reg_0, + lsig_combined_data(63 downto 0) => lsig_combined_data(63 downto 0), + lsig_packer_full => lsig_packer_full, + \lsig_set_packer_full__1\ => \lsig_set_packer_full__1\, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\ => \out\, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_data_fifo_data_out(65 downto 0) => sig_data_fifo_data_out(65 downto 0), + sig_data_fifo_dvalid => sig_data_fifo_dvalid, + sig_s_ready_out_reg => sig_s_ready_out_reg, + sig_stream_rst => sig_stream_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_sync_fifo_fg is port ( DOBDO : out STD_LOGIC_VECTOR ( 0 to 0 ); - \sig_user_skid_reg_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : out STD_LOGIC; + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC; + sig_ok_to_post_rd_addr_reg : out STD_LOGIC; + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : out STD_LOGIC; + hold_ff_q_reg : out STD_LOGIC; + \gc1.count_reg[7]\ : out STD_LOGIC; + \INFERRED_GEN.cnt_i_reg[2]\ : out STD_LOGIC; + DIN : out STD_LOGIC_VECTOR ( 0 to 0 ); + \sig_user_skid_reg_reg[0]\ : out STD_LOGIC; dm2linebuf_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : out STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[0]\ : out STD_LOGIC; m_axi_mm2s_aclk : in STD_LOGIC; - ram_empty_fb_i_reg : in STD_LOGIC; - ram_full_i_reg : in STD_LOGIC; - \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC; - sig_stream_rst : in STD_LOGIC; - \gc1.count_d2_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); - Q : in STD_LOGIC_VECTOR ( 6 downto 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ); - lsig_0ffset_cntr : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_posted_to_axi_2_reg : in STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); lsig_cmd_loaded : in STD_LOGIC; - \gpregsm1.user_valid_reg\ : in STD_LOGIC; hold_ff_q : in STD_LOGIC; - p_0_out : in STD_LOGIC_VECTOR ( 0 to 0 ); - dm2linebuf_mm2s_tvalid : in STD_LOGIC; - p_8_out : in STD_LOGIC; - \fifo_wren__0\ : in STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ram_full_i_reg : in STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ : in STD_LOGIC; + \sig_token_cntr_reg[0]\ : in STD_LOGIC; + \sig_token_cntr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + ram_full_i_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_memory : entity is "memory"; -end Arty_Z7_20_axi_vdma_0_0_memory; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_sync_fifo_fg : entity is "sync_fifo_fg"; +end Arty_Z7_20_axi_vdma_0_0_sync_fifo_fg; -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_memory is +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_sync_fifo_fg is begin -\gbm.gbmg.gbmgb.ngecc.bmg\: entity work.Arty_Z7_20_axi_vdma_0_0_blk_mem_gen_v8_3_5 +\FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM\: entity work.\Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized1\ port map ( + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\, DIBDI(1 downto 0) => DIBDI(1 downto 0), + DIN(0) => DIN(0), DOBDO(0) => DOBDO(0), + E(0) => E(0), \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, - \INFERRED_GEN.cnt_i_reg[0]\ => \INFERRED_GEN.cnt_i_reg[0]\, - \INFERRED_GEN.cnt_i_reg[2]\(0) => \INFERRED_GEN.cnt_i_reg[2]\(0), - Q(6 downto 0) => Q(6 downto 0), + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, + \INFERRED_GEN.cnt_i_reg[2]\ => \INFERRED_GEN.cnt_i_reg[2]\, + Q(0) => Q(0), + SR(0) => SR(0), dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), - dm2linebuf_mm2s_tvalid => dm2linebuf_mm2s_tvalid, - \fifo_wren__0\ => \fifo_wren__0\, - \gc1.count_d2_reg[6]\(6 downto 0) => \gc1.count_d2_reg[6]\(6 downto 0), - \gpregsm1.curr_fwft_state_reg[0]\ => \gpregsm1.curr_fwft_state_reg[0]\, - \gpregsm1.user_valid_reg\ => \gpregsm1.user_valid_reg\, + \gc1.count_reg[7]\(0) => \gc1.count_reg[7]\, hold_ff_q => hold_ff_q, - lsig_0ffset_cntr => lsig_0ffset_cntr, + hold_ff_q_reg => hold_ff_q_reg, lsig_cmd_loaded => lsig_cmd_loaded, m_axi_mm2s_aclk => m_axi_mm2s_aclk, m_axi_mm2s_rdata(63 downto 0) => m_axi_mm2s_rdata(63 downto 0), - p_0_out(0) => p_0_out(0), - p_8_out => p_8_out, - ram_empty_fb_i_reg => ram_empty_fb_i_reg, + \out\ => \out\, ram_full_i_reg => ram_full_i_reg, - sig_stream_rst => sig_stream_rst, - \sig_user_skid_reg_reg[0]\(0) => \sig_user_skid_reg_reg[0]\(0) + ram_full_i_reg_0(0) => ram_full_i_reg_0(0), + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_ok_to_post_rd_addr_reg => sig_ok_to_post_rd_addr_reg, + sig_posted_to_axi_2_reg => sig_posted_to_axi_2_reg, + \sig_token_cntr_reg[0]\ => \sig_token_cntr_reg[0]\, + \sig_token_cntr_reg[3]\(3 downto 0) => \sig_token_cntr_reg[3]\(3 downto 0), + \sig_user_skid_reg_reg[0]\ => \sig_user_skid_reg_reg[0]\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_afifo_builtin is +entity \Arty_Z7_20_axi_vdma_0_0_sync_fifo_fg__parameterized1\ is port ( - fifo_full_i : out STD_LOGIC; - sig_m_valid_out_reg : out STD_LOGIC; - fifo_dout : out STD_LOGIC_VECTOR ( 33 downto 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - s_axis_fifo_ainit_nosync_reg : in STD_LOGIC; - m_axis_mm2s_aclk : in STD_LOGIC; - \fifo_wren__0\ : in STD_LOGIC; - \out\ : in STD_LOGIC; - dm2linebuf_mm2s_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - DIN : in STD_LOGIC_VECTOR ( 1 downto 0 ) + sig_data_fifo_data_out : out STD_LOGIC_VECTOR ( 65 downto 0 ); + \out\ : out STD_LOGIC; + \gcc0.gc0.count_d1_reg[7]\ : out STD_LOGIC; + hold_ff_q_reg : out STD_LOGIC; + \INCLUDE_PACKING.lsig_packer_full_reg\ : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_data_fifo_dvalid : out STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + lsig_combined_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); + DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ); + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + hold_ff_q_reg_0 : in STD_LOGIC; + sig_s_ready_out_reg : in STD_LOGIC; + \lsig_set_packer_full__1\ : in STD_LOGIC; + lsig_packer_full : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_afifo_builtin : entity is "axi_vdma_afifo_builtin"; -end Arty_Z7_20_axi_vdma_0_0_axi_vdma_afifo_builtin; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_sync_fifo_fg__parameterized1\ : entity is "sync_fifo_fg"; +end \Arty_Z7_20_axi_vdma_0_0_sync_fifo_fg__parameterized1\; -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_afifo_builtin is +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_sync_fifo_fg__parameterized1\ is begin -fg_builtin_fifo_inst: entity work.Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3 +\FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM\: entity work.\Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized3\ port map ( - DIN(1 downto 0) => DIN(1 downto 0), - dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), - fifo_dout(33 downto 0) => fifo_dout(33 downto 0), - fifo_full_i => fifo_full_i, - \fifo_wren__0\ => \fifo_wren__0\, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axis_mm2s_aclk => m_axis_mm2s_aclk, + DIBDI(1 downto 0) => DIBDI(1 downto 0), + E(0) => E(0), + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0]\(0), + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0\, + \INCLUDE_PACKING.lsig_packer_full_reg\ => \INCLUDE_PACKING.lsig_packer_full_reg\, + \gcc0.gc0.count_d1_reg[7]\ => \gcc0.gc0.count_d1_reg[7]\, + hold_ff_q_reg => hold_ff_q_reg, + hold_ff_q_reg_0 => hold_ff_q_reg_0, + lsig_combined_data(63 downto 0) => lsig_combined_data(63 downto 0), + lsig_packer_full => lsig_packer_full, + \lsig_set_packer_full__1\ => \lsig_set_packer_full__1\, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, \out\ => \out\, - s_axis_fifo_ainit_nosync_reg => s_axis_fifo_ainit_nosync_reg, - sig_m_valid_out_reg => sig_m_valid_out_reg + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_data_fifo_data_out(65 downto 0) => sig_data_fifo_data_out(65 downto 0), + sig_data_fifo_dvalid => sig_data_fifo_dvalid, + sig_s_ready_out_reg => sig_s_ready_out_reg, + sig_stream_rst => sig_stream_rst ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_fifo_generator_ramfifo is +entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_sfifo_autord is port ( + DOBDO : out STD_LOGIC_VECTOR ( 0 to 0 ); \out\ : out STD_LOGIC; - \sig_user_skid_reg_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - dm2linebuf_mm2s_tvalid : out STD_LOGIC; - DI : out STD_LOGIC_VECTOR ( 3 downto 0 ); - Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); - dm2linebuf_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - hold_ff_q_reg : out STD_LOGIC; + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC; sig_ok_to_post_rd_addr_reg : out STD_LOGIC; - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : out STD_LOGIC; \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : out STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[0]\ : out STD_LOGIC; - S : out STD_LOGIC_VECTOR ( 3 downto 0 ); - \count_reg[6]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gc1.count_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INFERRED_GEN.cnt_i_reg[2]\ : out STD_LOGIC; + DIN : out STD_LOGIC_VECTOR ( 0 to 0 ); + \sig_user_skid_reg_reg[0]\ : out STD_LOGIC; + dm2linebuf_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_mm2s_aclk : in STD_LOGIC; - sig_stream_rst : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ); - lsig_0ffset_cntr : in STD_LOGIC; - lsig_cmd_loaded : in STD_LOGIC; - hold_ff_q : in STD_LOGIC; - \sig_token_cntr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); - p_8_out : in STD_LOGIC; sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; sig_posted_to_axi_2_reg : in STD_LOGIC; - sig_posted_to_axi_2_reg_0 : in STD_LOGIC; - p_0_out : in STD_LOGIC_VECTOR ( 0 to 0 ); - \INFERRED_GEN.cnt_i_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - \fifo_wren__0\ : in STD_LOGIC; - \mm2s_strm_wvalid0__1\ : in STD_LOGIC; - m_axi_mm2s_rvalid : in STD_LOGIC; - \sig_advance_pipe9_out__1\ : in STD_LOGIC; - D : in STD_LOGIC_VECTOR ( 5 downto 0 ) + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + lsig_cmd_loaded : in STD_LOGIC; + ram_full_i_reg : in STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ : in STD_LOGIC; + \sig_token_cntr_reg[0]\ : in STD_LOGIC; + \sig_token_cntr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + ram_full_i_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo"; -end Arty_Z7_20_axi_vdma_0_0_fifo_generator_ramfifo; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_sfifo_autord : entity is "axi_datamover_sfifo_autord"; +end Arty_Z7_20_axi_vdma_0_0_axi_datamover_sfifo_autord; -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_fifo_generator_ramfifo is - signal \^dm2linebuf_mm2s_tvalid\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.rd_n_1\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.rd_n_13\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.rd_n_18\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.wr_n_2\ : STD_LOGIC; - signal \grss.rsts/ram_empty_i0__3\ : STD_LOGIC; - signal \^out\ : STD_LOGIC; - signal p_0_out_1 : STD_LOGIC_VECTOR ( 6 downto 0 ); - signal p_11_out : STD_LOGIC_VECTOR ( 6 downto 0 ); - signal p_2_out_0 : STD_LOGIC; - signal p_7_out : STD_LOGIC; - signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 6 downto 0 ); - signal sig_data_fifo_data_out : STD_LOGIC_VECTOR ( 65 to 65 ); +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_sfifo_autord is + signal \BLK_MEM.I_SYNC_FIFOGEN_FIFO_n_5\ : STD_LOGIC; + signal hold_ff_q : STD_LOGIC; begin - dm2linebuf_mm2s_tvalid <= \^dm2linebuf_mm2s_tvalid\; - \out\ <= \^out\; -\gntv_or_sync_fifo.gl0.rd\: entity work.Arty_Z7_20_axi_vdma_0_0_rd_logic +\BLK_MEM.I_SYNC_FIFOGEN_FIFO\: entity work.Arty_Z7_20_axi_vdma_0_0_sync_fifo_fg port map ( - D(5 downto 0) => D(5 downto 0), - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ => \gntv_or_sync_fifo.gl0.rd_n_13\, - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0\ => \gntv_or_sync_fifo.gl0.rd_n_18\, - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_1\(6 downto 0) => p_0_out_1(6 downto 0), - DI(3 downto 0) => DI(3 downto 0), - DOBDO(0) => sig_data_fifo_data_out(65), + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\, + DIBDI(1 downto 0) => DIBDI(1 downto 0), + DIN(0) => DIN(0), + DOBDO(0) => DOBDO(0), + E(0) => E(0), + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, - \INFERRED_GEN.cnt_i_reg[2]\(0) => \INFERRED_GEN.cnt_i_reg[2]\(0), - Q(1 downto 0) => Q(1 downto 0), - S(3 downto 0) => S(3 downto 0), - \count_reg[6]\(1 downto 0) => \count_reg[6]\(1 downto 0), - dm2linebuf_mm2s_tvalid => \^dm2linebuf_mm2s_tvalid\, - \gc1.count_d2_reg[6]\(6 downto 0) => rd_pntr_plus1(6 downto 0), + \INFERRED_GEN.cnt_i_reg[2]\ => \INFERRED_GEN.cnt_i_reg[2]\, + Q(0) => Q(0), + SR(0) => SR(0), + dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), + \gc1.count_reg[7]\ => \gc1.count_reg[7]\(0), hold_ff_q => hold_ff_q, - hold_ff_q_reg => \gntv_or_sync_fifo.gl0.rd_n_1\, - hold_ff_q_reg_0 => hold_ff_q_reg, - lsig_0ffset_cntr => lsig_0ffset_cntr, + hold_ff_q_reg => \BLK_MEM.I_SYNC_FIFOGEN_FIFO_n_5\, lsig_cmd_loaded => lsig_cmd_loaded, m_axi_mm2s_aclk => m_axi_mm2s_aclk, - \out\ => p_2_out_0, - p_7_out => p_7_out, - p_8_out => p_8_out, - \ram_empty_i0__3\ => \grss.rsts/ram_empty_i0__3\, - ram_full_i_reg => \gntv_or_sync_fifo.gl0.wr_n_2\, - ram_full_i_reg_0 => \^out\, + m_axi_mm2s_rdata(63 downto 0) => m_axi_mm2s_rdata(63 downto 0), + \out\ => \out\, + ram_full_i_reg => ram_full_i_reg, + ram_full_i_reg_0(0) => ram_full_i_reg_0(0), sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, sig_ok_to_post_rd_addr_reg => sig_ok_to_post_rd_addr_reg, sig_posted_to_axi_2_reg => sig_posted_to_axi_2_reg, - sig_posted_to_axi_2_reg_0 => sig_posted_to_axi_2_reg_0, - sig_stream_rst => sig_stream_rst, - \sig_token_cntr_reg[3]\(3 downto 0) => \sig_token_cntr_reg[3]\(3 downto 0) + \sig_token_cntr_reg[0]\ => \sig_token_cntr_reg[0]\, + \sig_token_cntr_reg[3]\(3 downto 0) => \sig_token_cntr_reg[3]\(3 downto 0), + \sig_user_skid_reg_reg[0]\ => \sig_user_skid_reg_reg[0]\ ); -\gntv_or_sync_fifo.gl0.wr\: entity work.Arty_Z7_20_axi_vdma_0_0_wr_logic - port map ( - Q(6 downto 0) => p_11_out(6 downto 0), - \gc1.count_d1_reg[6]\(6 downto 0) => rd_pntr_plus1(6 downto 0), - \gc1.count_d2_reg[6]\(6 downto 0) => p_0_out_1(6 downto 0), - \gcc0.gc0.count_d1_reg[6]\ => \gntv_or_sync_fifo.gl0.wr_n_2\, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axi_mm2s_rvalid => m_axi_mm2s_rvalid, - \mm2s_strm_wvalid0__1\ => \mm2s_strm_wvalid0__1\, - \out\ => \^out\, - p_7_out => p_7_out, - ram_empty_fb_i_reg => p_2_out_0, - \ram_empty_i0__3\ => \grss.rsts/ram_empty_i0__3\, - \sig_advance_pipe9_out__1\ => \sig_advance_pipe9_out__1\, - sig_stream_rst => sig_stream_rst +hold_ff_q_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_mm2s_aclk, + CE => '1', + D => \BLK_MEM.I_SYNC_FIFOGEN_FIFO_n_5\, + Q => hold_ff_q, + R => '0' ); -\gntv_or_sync_fifo.mem\: entity work.Arty_Z7_20_axi_vdma_0_0_memory +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_axi_vdma_0_0_axi_datamover_sfifo_autord__parameterized1\ is + port ( + sig_data_fifo_data_out : out STD_LOGIC_VECTOR ( 65 downto 0 ); + \out\ : out STD_LOGIC; + \gcc0.gc0.count_d1_reg[7]\ : out STD_LOGIC; + hold_ff_q : out STD_LOGIC; + \INCLUDE_PACKING.lsig_packer_full_reg\ : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + sig_data_fifo_dvalid : out STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + lsig_combined_data : in STD_LOGIC_VECTOR ( 63 downto 0 ); + DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ); + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + sig_s_ready_out_reg : in STD_LOGIC; + \lsig_set_packer_full__1\ : in STD_LOGIC; + lsig_packer_full : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3\ : in STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_sfifo_autord__parameterized1\ : entity is "axi_datamover_sfifo_autord"; +end \Arty_Z7_20_axi_vdma_0_0_axi_datamover_sfifo_autord__parameterized1\; + +architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_axi_datamover_sfifo_autord__parameterized1\ is + signal \BLK_MEM.I_SYNC_FIFOGEN_FIFO_n_68\ : STD_LOGIC; + signal \^hold_ff_q\ : STD_LOGIC; +begin + hold_ff_q <= \^hold_ff_q\; +\BLK_MEM.I_SYNC_FIFOGEN_FIFO\: entity work.\Arty_Z7_20_axi_vdma_0_0_sync_fifo_fg__parameterized1\ port map ( DIBDI(1 downto 0) => DIBDI(1 downto 0), - DOBDO(0) => sig_data_fifo_data_out(65), - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, - \INFERRED_GEN.cnt_i_reg[0]\ => \INFERRED_GEN.cnt_i_reg[0]\, - \INFERRED_GEN.cnt_i_reg[2]\(0) => \INFERRED_GEN.cnt_i_reg[2]\(0), - Q(6 downto 0) => p_11_out(6 downto 0), - dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), - dm2linebuf_mm2s_tvalid => \^dm2linebuf_mm2s_tvalid\, - \fifo_wren__0\ => \fifo_wren__0\, - \gc1.count_d2_reg[6]\(6 downto 0) => p_0_out_1(6 downto 0), - \gpregsm1.curr_fwft_state_reg[0]\ => \gntv_or_sync_fifo.gl0.rd_n_13\, - \gpregsm1.user_valid_reg\ => \gntv_or_sync_fifo.gl0.rd_n_1\, - hold_ff_q => hold_ff_q, - lsig_0ffset_cntr => lsig_0ffset_cntr, - lsig_cmd_loaded => lsig_cmd_loaded, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axi_mm2s_rdata(63 downto 0) => m_axi_mm2s_rdata(63 downto 0), - p_0_out(0) => p_0_out(0), - p_8_out => p_8_out, - ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.rd_n_18\, - ram_full_i_reg => \gntv_or_sync_fifo.gl0.wr_n_2\, - sig_stream_rst => sig_stream_rst, - \sig_user_skid_reg_reg[0]\(0) => \sig_user_skid_reg_reg[0]\(0) + E(0) => E(0), + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0]\(0), + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0]\(0) => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0]\(0), + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0\ => \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0\, + \INCLUDE_PACKING.lsig_packer_full_reg\ => \INCLUDE_PACKING.lsig_packer_full_reg\, + \gcc0.gc0.count_d1_reg[7]\ => \gcc0.gc0.count_d1_reg[7]\, + hold_ff_q_reg => \BLK_MEM.I_SYNC_FIFOGEN_FIFO_n_68\, + hold_ff_q_reg_0 => \^hold_ff_q\, + lsig_combined_data(63 downto 0) => lsig_combined_data(63 downto 0), + lsig_packer_full => lsig_packer_full, + \lsig_set_packer_full__1\ => \lsig_set_packer_full__1\, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\ => \out\, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_data_fifo_data_out(65 downto 0) => sig_data_fifo_data_out(65 downto 0), + sig_data_fifo_dvalid => sig_data_fifo_dvalid, + sig_s_ready_out_reg => sig_s_ready_out_reg, + sig_stream_rst => sig_stream_rst + ); +hold_ff_q_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => \BLK_MEM.I_SYNC_FIFOGEN_FIFO_n_68\, + Q => \^hold_ff_q\, + R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_axi_vdma_mm2s_linebuf is +entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_indet_btt is port ( \out\ : out STD_LOGIC; - p_1_out : out STD_LOGIC; - p_0_out : out STD_LOGIC; - sig_reset_reg_reg : out STD_LOGIC; - m_axis_mm2s_tlast : out STD_LOGIC; - m_axis_mm2s_tuser : out STD_LOGIC_VECTOR ( 0 to 0 ); - DIN : out STD_LOGIC_VECTOR ( 0 to 0 ); - fifo_full_i : out STD_LOGIC; - s_valid0 : out STD_LOGIC; - \GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0\ : out STD_LOGIC; - m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - scndry_reset2 : in STD_LOGIC; - m_axis_mm2s_aclk : in STD_LOGIC; - mm2s_halt : in STD_LOGIC; - Q : in STD_LOGIC_VECTOR ( 12 downto 0 ); - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - all_lines_xfred : in STD_LOGIC; - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\ : in STD_LOGIC; - \fifo_wren__0\ : in STD_LOGIC; - m_axis_mm2s_tready : in STD_LOGIC; - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\ : in STD_LOGIC; - p_15_out : in STD_LOGIC; - dm2linebuf_mm2s_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + \GEN_INDET_BTT.lsig_eop_reg_reg\ : out STD_LOGIC; + sig_ibtt2wdc_tlast : out STD_LOGIC; + sig_clr_dbc_reg : out STD_LOGIC; + DI : out STD_LOGIC_VECTOR ( 10 downto 0 ); + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0\ : out STD_LOGIC; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0\ : out STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0\ : out STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0\ : out STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0\ : out STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0\ : out STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0\ : out STD_LOGIC; + p_0_in : out STD_LOGIC; + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0\ : out STD_LOGIC; + sig_xfer_is_seq_reg_reg : out STD_LOGIC_VECTOR ( 9 downto 0 ); + \sig_child_addr_cntr_lsh_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \gcc0.gc0.count_d1_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + S : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \sig_xfer_len_reg_reg[4]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \sig_xfer_len_reg_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_INDET_BTT.lsig_byte_cntr_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_INDET_BTT.lsig_byte_cntr_reg[6]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_INDET_BTT.lsig_byte_cntr_reg[3]\ : out STD_LOGIC_VECTOR ( 64 downto 0 ); + \GEN_INDET_BTT.lsig_eop_reg_reg_0\ : out STD_LOGIC; + sig_xfer_is_seq_reg_reg_0 : out STD_LOGIC; + sig_xfer_cmd_cmplt_reg0 : out STD_LOGIC; + sig_sf2pcc_xfer_valid : out STD_LOGIC; + sig_ibtt2dre_tready : out STD_LOGIC; + sig_csm_state_ns1 : out STD_LOGIC; + \gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \gpr1.dout_i_reg[1]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + O : out STD_LOGIC_VECTOR ( 3 downto 0 ); + CO : out STD_LOGIC_VECTOR ( 0 to 0 ); + \sig_child_addr_cntr_lsh_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_s2mm_aclk : in STD_LOGIC; + sig_stream_rst : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_dre2ibtt_tlast : in STD_LOGIC; + sig_dre2ibtt_eop : in STD_LOGIC; + \INCLUDE_PACKING.lsig_first_dbeat_reg_0\ : in STD_LOGIC; + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[0]\ : in STD_LOGIC; + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[0]_0\ : in STD_LOGIC; + sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; + p_32_out : in STD_LOGIC; + sig_adjusted_addr_incr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \INFERRED_GEN.cnt_i_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 7 downto 0 ); + sig_csm_pop_child_cmd : in STD_LOGIC; + sig_wdc2ibtt_tready : in STD_LOGIC; + lsig_end_of_cmd_reg : in STD_LOGIC; + lsig_eop_reg : in STD_LOGIC; + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[0]_1\ : in STD_LOGIC; + sig_child_qual_first_of_2 : in STD_LOGIC; + sig_child_qual_error_reg : in STD_LOGIC; + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_init_reg : in STD_LOGIC; + \gpr1.dout_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \gpr1.dout_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + sig_child_addr_cntr_lsh_reg : in STD_LOGIC_VECTOR ( 2 downto 0 ); + sig_m_valid_out_reg : in STD_LOGIC_VECTOR ( 1 downto 0 ); + sig_m_valid_out_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + sig_m_valid_out_reg_1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + sig_m_valid_out_reg_2 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + sig_m_valid_out_reg_3 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + sig_m_valid_out_reg_4 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + sig_m_valid_out_reg_5 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + sig_m_valid_out_reg_6 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 1 downto 0 ); + p_0_out : in STD_LOGIC_VECTOR ( 10 downto 0 ); + \sig_strb_reg_out_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + sig_dre2ibtt_tstrb : in STD_LOGIC ); attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_vdma_mm2s_linebuf : entity is "axi_vdma_mm2s_linebuf"; -end Arty_Z7_20_axi_vdma_0_0_axi_vdma_mm2s_linebuf; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_indet_btt : entity is "axi_datamover_indet_btt"; +end Arty_Z7_20_axi_vdma_0_0_axi_datamover_indet_btt; -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma_mm2s_linebuf is - signal \^din\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I_n_2\ : STD_LOGIC; - signal \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_1\ : STD_LOGIC; - signal \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID_n_6\ : STD_LOGIC; - signal \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID_n_7\ : STD_LOGIC; - signal \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg_n_0\ : STD_LOGIC; - signal \GEN_LINEBUF_NO_SOF.vsize_counter[0]_i_1_n_0\ : STD_LOGIC; - signal \GEN_LINEBUF_NO_SOF.vsize_counter[10]_i_1_n_0\ : STD_LOGIC; - signal \GEN_LINEBUF_NO_SOF.vsize_counter[11]_i_1_n_0\ : STD_LOGIC; - signal \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\ : STD_LOGIC; - signal \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_3_n_0\ : STD_LOGIC; - signal \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_4_n_0\ : STD_LOGIC; - signal \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_5_n_0\ : STD_LOGIC; - signal \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_7_n_0\ : STD_LOGIC; - signal \GEN_LINEBUF_NO_SOF.vsize_counter[1]_i_1_n_0\ : STD_LOGIC; - signal \GEN_LINEBUF_NO_SOF.vsize_counter[2]_i_1_n_0\ : STD_LOGIC; - signal \GEN_LINEBUF_NO_SOF.vsize_counter[3]_i_1_n_0\ : STD_LOGIC; - signal \GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_1_n_0\ : STD_LOGIC; - signal \GEN_LINEBUF_NO_SOF.vsize_counter[5]_i_1_n_0\ : STD_LOGIC; - signal \GEN_LINEBUF_NO_SOF.vsize_counter[6]_i_1_n_0\ : STD_LOGIC; - signal \GEN_LINEBUF_NO_SOF.vsize_counter[7]_i_1_n_0\ : STD_LOGIC; - signal \GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_1_n_0\ : STD_LOGIC; - signal \GEN_LINEBUF_NO_SOF.vsize_counter[9]_i_1_n_0\ : STD_LOGIC; - signal \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\ : STD_LOGIC; - signal crnt_vsize_cdc_tig : STD_LOGIC_VECTOR ( 12 downto 0 ); - attribute async_reg : string; - attribute async_reg of crnt_vsize_cdc_tig : signal is "true"; - signal crnt_vsize_d1 : STD_LOGIC_VECTOR ( 12 downto 0 ); - attribute async_reg of crnt_vsize_d1 : signal is "true"; - signal data_count_ae_threshold_cdc_tig : STD_LOGIC_VECTOR ( 11 downto 0 ); - attribute async_reg of data_count_ae_threshold_cdc_tig : signal is "true"; - signal data_count_ae_threshold_d1 : STD_LOGIC_VECTOR ( 11 downto 0 ); - attribute async_reg of data_count_ae_threshold_d1 : signal is "true"; - signal fifo_dout : STD_LOGIC_VECTOR ( 33 downto 0 ); - signal fifo_pipe_empty : STD_LOGIC; - signal m_axis_fifo_ainit_nosync : STD_LOGIC; - signal m_axis_tlast_d1 : STD_LOGIC; - signal m_axis_tready_d1 : STD_LOGIC; - signal m_axis_tvalid_d1 : STD_LOGIC; - signal minusOp : STD_LOGIC_VECTOR ( 12 downto 1 ); - signal \minusOp_carry__0_i_1_n_0\ : STD_LOGIC; - signal \minusOp_carry__0_i_2_n_0\ : STD_LOGIC; - signal \minusOp_carry__0_i_3_n_0\ : STD_LOGIC; - signal \minusOp_carry__0_i_4_n_0\ : STD_LOGIC; - signal \minusOp_carry__0_n_0\ : STD_LOGIC; - signal \minusOp_carry__0_n_1\ : STD_LOGIC; - signal \minusOp_carry__0_n_2\ : STD_LOGIC; - signal \minusOp_carry__0_n_3\ : STD_LOGIC; - signal \minusOp_carry__1_i_1_n_0\ : STD_LOGIC; - signal \minusOp_carry__1_i_2_n_0\ : STD_LOGIC; - signal \minusOp_carry__1_i_3_n_0\ : STD_LOGIC; - signal \minusOp_carry__1_i_4_n_0\ : STD_LOGIC; - signal \minusOp_carry__1_n_1\ : STD_LOGIC; - signal \minusOp_carry__1_n_2\ : STD_LOGIC; - signal \minusOp_carry__1_n_3\ : STD_LOGIC; - signal minusOp_carry_i_1_n_0 : STD_LOGIC; - signal minusOp_carry_i_2_n_0 : STD_LOGIC; - signal minusOp_carry_i_3_n_0 : STD_LOGIC; - signal minusOp_carry_i_4_n_0 : STD_LOGIC; - signal minusOp_carry_n_0 : STD_LOGIC; - signal minusOp_carry_n_1 : STD_LOGIC; - signal minusOp_carry_n_2 : STD_LOGIC; - signal minusOp_carry_n_3 : STD_LOGIC; - signal p_4_in : STD_LOGIC; - signal s_axis_fifo_ainit_nosync_reg : STD_LOGIC; - signal \^sig_reset_reg_reg\ : STD_LOGIC; - signal vsize_counter : STD_LOGIC_VECTOR ( 12 downto 0 ); - signal \NLW_minusOp_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); - attribute ASYNC_REG_boolean : boolean; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[0]\ : label is std.standard.true; - attribute KEEP : string; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[0]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[10]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[10]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[11]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[11]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[12]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[12]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[1]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[1]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[2]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[2]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[3]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[3]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[4]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[4]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[5]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[5]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[6]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[6]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[7]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[7]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[8]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[8]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[9]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[9]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[0]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[0]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[10]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[10]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[11]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[11]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[12]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[12]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[1]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[1]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[2]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[2]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[3]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[3]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[4]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[4]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[5]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[5]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[6]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[6]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[7]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[7]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[8]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[8]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[9]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[9]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[0]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[0]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[10]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[10]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[11]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[11]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[1]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[1]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[2]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[2]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[3]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[3]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[4]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[4]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[5]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[5]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[6]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[6]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[7]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[7]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[8]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[8]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[9]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[9]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[0]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[0]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[10]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[10]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[11]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[11]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[1]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[1]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[2]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[2]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[3]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[3]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[4]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[4]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[5]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[5]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[6]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[6]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[7]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[7]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[8]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[8]\ : label is "yes"; - attribute ASYNC_REG_boolean of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[9]\ : label is std.standard.true; - attribute KEEP of \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[9]\ : label is "yes"; +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_indet_btt is + signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_6_n_0\ : STD_LOGIC; + signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_7_n_0\ : STD_LOGIC; + signal \^di\ : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][0]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][1]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][2]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][3]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][4]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][5]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][6]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][7]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg_n_0_[0][0]\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg_n_0_[0][1]\ : STD_LOGIC; + signal \^include_packing.do_reg_slices[0].lsig_segment_ld_reg__0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][0]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][1]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][2]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][3]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][4]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][5]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][6]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][7]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg_n_0_[1][0]\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg_n_0_[1][1]\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][0]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][1]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][2]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][3]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][4]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][5]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][6]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][7]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg_n_0_[2][0]\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg_n_0_[2][1]\ : STD_LOGIC; + signal \^include_packing.do_reg_slices[2].lsig_segment_ld_reg__0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][0]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][1]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][2]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][3]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][4]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][5]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][6]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][7]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg_n_0_[3][0]\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg_n_0_[3][1]\ : STD_LOGIC; + signal \^include_packing.do_reg_slices[3].lsig_segment_ld_reg__0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][0]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][1]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][2]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][3]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][4]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][5]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][6]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][7]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg_n_0_[4][0]\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg_n_0_[4][1]\ : STD_LOGIC; + signal \^include_packing.do_reg_slices[4].lsig_segment_ld_reg__0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][0]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][1]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][2]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][3]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][4]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][5]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][6]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][7]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg_n_0_[5][0]\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg_n_0_[5][1]\ : STD_LOGIC; + signal \^include_packing.do_reg_slices[5].lsig_segment_ld_reg__0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][0]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][1]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][2]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][3]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][4]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][5]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][6]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][7]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg_n_0_[6][0]\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg_n_0_[6][1]\ : STD_LOGIC; + signal \^include_packing.do_reg_slices[6].lsig_segment_ld_reg__0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][0]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][1]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][2]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][3]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][4]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][5]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][6]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][7]_i_1_n_0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg_n_0_[7][0]\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg_n_0_[7][1]\ : STD_LOGIC; + signal \^include_packing.do_reg_slices[7].lsig_segment_ld_reg__0\ : STD_LOGIC; + signal \INCLUDE_PACKING.lsig_0ffset_cntr[2]_i_1_n_0\ : STD_LOGIC; + signal \^include_packing.lsig_0ffset_cntr_reg[2]_0\ : STD_LOGIC; + signal \^include_packing.lsig_0ffset_cntr_reg[2]_1\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal I_DATA_FIFO_n_66 : STD_LOGIC; + signal I_DATA_FIFO_n_69 : STD_LOGIC; + signal hold_ff_q : STD_LOGIC; + signal lsig_0ffset_cntr : STD_LOGIC_VECTOR ( 2 to 2 ); + signal \lsig_0ffset_to_to_use__2\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal lsig_combined_data : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal \lsig_flag_slice_reg[0]_7\ : STD_LOGIC; + signal \lsig_flag_slice_reg[1]_6\ : STD_LOGIC; + signal \lsig_flag_slice_reg[2]_5\ : STD_LOGIC; + signal \lsig_flag_slice_reg[3]_4\ : STD_LOGIC; + signal \lsig_flag_slice_reg[4]_3\ : STD_LOGIC; + signal \lsig_flag_slice_reg[5]_2\ : STD_LOGIC; + signal \lsig_flag_slice_reg[6]_1\ : STD_LOGIC; + signal \lsig_flag_slice_reg[7]_0\ : STD_LOGIC; + signal lsig_packer_full : STD_LOGIC; + signal \lsig_set_packer_full__1\ : STD_LOGIC; + signal \^p_0_in\ : STD_LOGIC; + signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal p_2_in : STD_LOGIC; + signal p_4_out : STD_LOGIC; + signal \sig_burst_dbeat_cntr[2]_i_1_n_0\ : STD_LOGIC; + signal \sig_burst_dbeat_cntr[4]_i_1_n_0\ : STD_LOGIC; + signal \sig_burst_dbeat_cntr_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \sig_byte_cntr[3]_i_3_n_0\ : STD_LOGIC; + signal \sig_byte_cntr[3]_i_4_n_0\ : STD_LOGIC; + signal \sig_byte_cntr[3]_i_5_n_0\ : STD_LOGIC; + signal \sig_byte_cntr[3]_i_6_n_0\ : STD_LOGIC; + signal \sig_byte_cntr[7]_i_3_n_0\ : STD_LOGIC; + signal \sig_byte_cntr[7]_i_4_n_0\ : STD_LOGIC; + signal \sig_byte_cntr[7]_i_5_n_0\ : STD_LOGIC; + signal \sig_byte_cntr[7]_i_6_n_0\ : STD_LOGIC; + signal \sig_byte_cntr[8]_i_4_n_0\ : STD_LOGIC; + signal \sig_byte_cntr_reg[3]_i_1_n_0\ : STD_LOGIC; + signal \sig_byte_cntr_reg[3]_i_1_n_1\ : STD_LOGIC; + signal \sig_byte_cntr_reg[3]_i_1_n_2\ : STD_LOGIC; + signal \sig_byte_cntr_reg[3]_i_1_n_3\ : STD_LOGIC; + signal \sig_byte_cntr_reg[3]_i_1_n_4\ : STD_LOGIC; + signal \sig_byte_cntr_reg[3]_i_1_n_5\ : STD_LOGIC; + signal \sig_byte_cntr_reg[3]_i_1_n_6\ : STD_LOGIC; + signal \sig_byte_cntr_reg[3]_i_1_n_7\ : STD_LOGIC; + signal \sig_byte_cntr_reg[7]_i_2_n_0\ : STD_LOGIC; + signal \sig_byte_cntr_reg[7]_i_2_n_1\ : STD_LOGIC; + signal \sig_byte_cntr_reg[7]_i_2_n_2\ : STD_LOGIC; + signal \sig_byte_cntr_reg[7]_i_2_n_3\ : STD_LOGIC; + signal \sig_byte_cntr_reg[7]_i_2_n_4\ : STD_LOGIC; + signal \sig_byte_cntr_reg[7]_i_2_n_5\ : STD_LOGIC; + signal \sig_byte_cntr_reg[7]_i_2_n_6\ : STD_LOGIC; + signal \sig_byte_cntr_reg[7]_i_2_n_7\ : STD_LOGIC; + signal \sig_byte_cntr_reg[8]_i_3_n_7\ : STD_LOGIC; + signal \^sig_clr_dbc_reg\ : STD_LOGIC; + signal sig_clr_dbeat_cntr0_out : STD_LOGIC; + signal \sig_data_fifo_data_in__0\ : STD_LOGIC_VECTOR ( 65 downto 64 ); + signal sig_data_fifo_data_out : STD_LOGIC_VECTOR ( 65 downto 0 ); + signal sig_data_fifo_dvalid : STD_LOGIC; + signal \sig_dbc_max__3\ : STD_LOGIC; + signal sig_incr_dbeat_cntr : STD_LOGIC; + signal \NLW_sig_byte_cntr_reg[8]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_sig_byte_cntr_reg[8]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][0]_i_1\ : label is "soft_lutpair214"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][1]_i_1\ : label is "soft_lutpair211"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][2]_i_1\ : label is "soft_lutpair211"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][3]_i_1\ : label is "soft_lutpair212"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][4]_i_1\ : label is "soft_lutpair212"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][5]_i_1\ : label is "soft_lutpair213"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][6]_i_1\ : label is "soft_lutpair213"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][7]_i_1\ : label is "soft_lutpair214"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][0]_i_1\ : label is "soft_lutpair210"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][1]_i_1\ : label is "soft_lutpair207"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][2]_i_1\ : label is "soft_lutpair207"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][3]_i_1\ : label is "soft_lutpair208"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][4]_i_1\ : label is "soft_lutpair208"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][5]_i_1\ : label is "soft_lutpair209"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][6]_i_1\ : label is "soft_lutpair209"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][7]_i_1\ : label is "soft_lutpair210"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg[1][1]_i_5\ : label is "soft_lutpair182"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][0]_i_1\ : label is "soft_lutpair206"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][1]_i_1\ : label is "soft_lutpair203"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][2]_i_1\ : label is "soft_lutpair203"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][3]_i_1\ : label is "soft_lutpair204"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][4]_i_1\ : label is "soft_lutpair204"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][5]_i_1\ : label is "soft_lutpair205"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][6]_i_1\ : label is "soft_lutpair205"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][7]_i_1\ : label is "soft_lutpair206"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][0]_i_1\ : label is "soft_lutpair202"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][1]_i_1\ : label is "soft_lutpair198"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][2]_i_1\ : label is "soft_lutpair198"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][3]_i_1\ : label is "soft_lutpair199"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][4]_i_1\ : label is "soft_lutpair199"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][5]_i_1\ : label is "soft_lutpair201"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][6]_i_1\ : label is "soft_lutpair201"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][7]_i_1\ : label is "soft_lutpair202"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][0]_i_1\ : label is "soft_lutpair197"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][1]_i_1\ : label is "soft_lutpair194"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][2]_i_1\ : label is "soft_lutpair194"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][3]_i_1\ : label is "soft_lutpair195"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][4]_i_1\ : label is "soft_lutpair195"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][5]_i_1\ : label is "soft_lutpair196"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][6]_i_1\ : label is "soft_lutpair196"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][7]_i_1\ : label is "soft_lutpair197"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg[4][1]_i_4\ : label is "soft_lutpair182"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][0]_i_1\ : label is "soft_lutpair193"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][1]_i_1\ : label is "soft_lutpair190"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][2]_i_1\ : label is "soft_lutpair190"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][3]_i_1\ : label is "soft_lutpair191"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][4]_i_1\ : label is "soft_lutpair191"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][5]_i_1\ : label is "soft_lutpair192"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][6]_i_1\ : label is "soft_lutpair192"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][7]_i_1\ : label is "soft_lutpair193"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][0]_i_1\ : label is "soft_lutpair189"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][1]_i_1\ : label is "soft_lutpair185"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][2]_i_1\ : label is "soft_lutpair185"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][3]_i_1\ : label is "soft_lutpair186"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][4]_i_1\ : label is "soft_lutpair186"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][5]_i_1\ : label is "soft_lutpair188"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][6]_i_1\ : label is "soft_lutpair189"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][7]_i_1\ : label is "soft_lutpair188"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][0]_i_1\ : label is "soft_lutpair184"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][1]_i_1\ : label is "soft_lutpair183"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][2]_i_1\ : label is "soft_lutpair184"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][3]_i_1\ : label is "soft_lutpair187"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][4]_i_1\ : label is "soft_lutpair200"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][5]_i_1\ : label is "soft_lutpair200"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][6]_i_1\ : label is "soft_lutpair187"; + attribute SOFT_HLUTNM of \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][7]_i_1\ : label is "soft_lutpair183"; + attribute SOFT_HLUTNM of \sig_burst_dbeat_cntr[0]_i_1\ : label is "soft_lutpair215"; + attribute SOFT_HLUTNM of \sig_burst_dbeat_cntr[1]_i_1\ : label is "soft_lutpair215"; + attribute SOFT_HLUTNM of \sig_burst_dbeat_cntr[2]_i_1\ : label is "soft_lutpair181"; + attribute SOFT_HLUTNM of \sig_burst_dbeat_cntr[3]_i_1\ : label is "soft_lutpair181"; + attribute SOFT_HLUTNM of \sig_burst_dbeat_cntr[4]_i_3\ : label is "soft_lutpair180"; + attribute SOFT_HLUTNM of sig_clr_dbc_reg_i_2 : label is "soft_lutpair180"; begin - DIN(0) <= \^din\(0); - \GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0\ <= \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\; - sig_reset_reg_reg <= \^sig_reset_reg_reg\; -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized15\ - port map ( - \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg\ => \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg_n_0\, - SR(0) => SR(0), - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axis_mm2s_aclk => m_axis_mm2s_aclk, - p_0_out => p_0_out, - scndry_reset2 => scndry_reset2 + DI(10 downto 0) <= \^di\(10 downto 0); + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0\ <= \^include_packing.do_reg_slices[0].lsig_segment_ld_reg__0\; + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0\ <= \^include_packing.do_reg_slices[2].lsig_segment_ld_reg__0\; + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0\ <= \^include_packing.do_reg_slices[3].lsig_segment_ld_reg__0\; + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0\ <= \^include_packing.do_reg_slices[4].lsig_segment_ld_reg__0\; + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0\ <= \^include_packing.do_reg_slices[5].lsig_segment_ld_reg__0\; + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0\ <= \^include_packing.do_reg_slices[6].lsig_segment_ld_reg__0\; + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0\ <= \^include_packing.do_reg_slices[7].lsig_segment_ld_reg__0\; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0\ <= \^include_packing.lsig_0ffset_cntr_reg[2]_0\; + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_1\(1 downto 0) <= \^include_packing.lsig_0ffset_cntr_reg[2]_1\(1 downto 0); + p_0_in <= \^p_0_in\; + sig_clr_dbc_reg <= \^sig_clr_dbc_reg\; +\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg_n_0_[3][0]\, + I1 => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg_n_0_[4][0]\, + I2 => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg_n_0_[2][0]\, + I3 => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg_n_0_[1][0]\, + I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_6_n_0\, + O => \sig_data_fifo_data_in__0\(65) ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized18\ - port map ( - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\, - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tready_d1_reg\ => \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I_n_2\, - SR(0) => SR(0), - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axis_fifo_ainit_nosync => m_axis_fifo_ainit_nosync, - m_axis_mm2s_aclk => m_axis_mm2s_aclk, - m_axis_mm2s_tready => m_axis_mm2s_tready, - mm2s_halt => mm2s_halt, - p_15_out => p_15_out, - scndry_reset2 => scndry_reset2, - sig_reset_reg_reg => \^sig_reset_reg_reg\ +\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg_n_0_[3][1]\, + I1 => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg_n_0_[4][1]\, + I2 => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg_n_0_[2][1]\, + I3 => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg_n_0_[1][1]\, + I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_7_n_0\, + O => \sig_data_fifo_data_in__0\(64) + ); +\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg_n_0_[6][0]\, + I1 => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg_n_0_[5][0]\, + I2 => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg_n_0_[0][0]\, + I3 => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg_n_0_[7][0]\, + O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_6_n_0\ + ); +\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg_n_0_[6][1]\, + I1 => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg_n_0_[5][1]\, + I2 => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg_n_0_[0][1]\, + I3 => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg_n_0_[7][1]\, + O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_7_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized14\ +\ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover_skid_buf port map ( - SR(0) => SR(0), - fifo_pipe_empty => fifo_pipe_empty, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axis_mm2s_aclk => m_axis_mm2s_aclk, - p_1_out => p_1_out, - scndry_reset2 => scndry_reset2 + E(0) => E(0), + \GEN_INDET_BTT.lsig_byte_cntr_reg[15]\(0) => \GEN_INDET_BTT.lsig_byte_cntr_reg[15]\(0), + \GEN_INDET_BTT.lsig_byte_cntr_reg[3]\(64 downto 0) => \GEN_INDET_BTT.lsig_byte_cntr_reg[3]\(64 downto 0), + \GEN_INDET_BTT.lsig_byte_cntr_reg[6]\(0) => \GEN_INDET_BTT.lsig_byte_cntr_reg[6]\(0), + \GEN_INDET_BTT.lsig_eop_reg_reg\ => \GEN_INDET_BTT.lsig_eop_reg_reg\, + \GEN_INDET_BTT.lsig_eop_reg_reg_0\ => \GEN_INDET_BTT.lsig_eop_reg_reg_0\, + \gpregsm1.user_valid_reg\ => p_4_out, + \gpregsm1.user_valid_reg_0\ => I_DATA_FIFO_n_66, + hold_ff_q => hold_ff_q, + lsig_end_of_cmd_reg => lsig_end_of_cmd_reg, + lsig_eop_reg => lsig_eop_reg, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\ => \out\, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_data_fifo_data_out(65 downto 0) => sig_data_fifo_data_out(65 downto 0), + sig_data_fifo_dvalid => sig_data_fifo_dvalid, + sig_ibtt2wdc_tlast => sig_ibtt2wdc_tlast, + sig_init_reg => sig_init_reg, + sig_stream_rst => sig_stream_rst, + sig_wdc2ibtt_tready => sig_wdc2ibtt_tready ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[0]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][0]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => Q(0), - Q => crnt_vsize_cdc_tig(0), - R => '0' + I0 => \^include_packing.do_reg_slices[0].lsig_segment_ld_reg__0\, + I1 => Q(0), + O => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][0]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[10]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][1]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => Q(10), - Q => crnt_vsize_cdc_tig(10), - R => '0' + I0 => \^include_packing.do_reg_slices[0].lsig_segment_ld_reg__0\, + I1 => Q(1), + O => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][1]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[11]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][2]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => Q(11), - Q => crnt_vsize_cdc_tig(11), - R => '0' + I0 => \^include_packing.do_reg_slices[0].lsig_segment_ld_reg__0\, + I1 => Q(2), + O => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][2]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[12]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][3]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => Q(12), - Q => crnt_vsize_cdc_tig(12), - R => '0' + I0 => \^include_packing.do_reg_slices[0].lsig_segment_ld_reg__0\, + I1 => Q(3), + O => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][3]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[1]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][4]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => Q(1), - Q => crnt_vsize_cdc_tig(1), - R => '0' + I0 => \^include_packing.do_reg_slices[0].lsig_segment_ld_reg__0\, + I1 => Q(4), + O => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][4]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[2]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][5]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => Q(2), - Q => crnt_vsize_cdc_tig(2), - R => '0' + I0 => \^include_packing.do_reg_slices[0].lsig_segment_ld_reg__0\, + I1 => Q(5), + O => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][5]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[3]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][6]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => Q(3), - Q => crnt_vsize_cdc_tig(3), - R => '0' + I0 => \^include_packing.do_reg_slices[0].lsig_segment_ld_reg__0\, + I1 => Q(6), + O => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][6]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[4]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][7]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => Q(4), - Q => crnt_vsize_cdc_tig(4), - R => '0' + I0 => \^include_packing.do_reg_slices[0].lsig_segment_ld_reg__0\, + I1 => Q(7), + O => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][7]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[5]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[0]_7\, + D => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][0]_i_1_n_0\, + Q => lsig_combined_data(0), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[0]_7\, + D => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][1]_i_1_n_0\, + Q => lsig_combined_data(1), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[0]_7\, + D => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][2]_i_1_n_0\, + Q => lsig_combined_data(2), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[0]_7\, + D => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][3]_i_1_n_0\, + Q => lsig_combined_data(3), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[0]_7\, + D => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][4]_i_1_n_0\, + Q => lsig_combined_data(4), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][5]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[0]_7\, + D => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][5]_i_1_n_0\, + Q => lsig_combined_data(5), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][6]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[0]_7\, + D => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][6]_i_1_n_0\, + Q => lsig_combined_data(6), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][7]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[0]_7\, + D => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg[0][7]_i_1_n_0\, + Q => lsig_combined_data(7), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg[0][1]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"0000015100000000" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => Q(5), - Q => crnt_vsize_cdc_tig(5), - R => '0' + I0 => \lsig_0ffset_to_to_use__2\(0), + I1 => \^include_packing.lsig_0ffset_cntr_reg[2]_1\(1), + I2 => \^include_packing.lsig_0ffset_cntr_reg[2]_0\, + I3 => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(1), + I4 => \lsig_0ffset_to_to_use__2\(2), + I5 => \INFERRED_GEN.cnt_i_reg[4]\(0), + O => \^include_packing.do_reg_slices[0].lsig_segment_ld_reg__0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[6]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[0]_7\, + D => sig_m_valid_out_reg_6(0), + Q => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg_n_0_[0][0]\, + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[0]_7\, + D => sig_m_valid_out_reg_6(1), + Q => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg_n_0_[0][1]\, + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][0]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => Q(6), - Q => crnt_vsize_cdc_tig(6), - R => '0' + I0 => \^p_0_in\, + I1 => Q(0), + O => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][0]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[7]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][1]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => Q(7), - Q => crnt_vsize_cdc_tig(7), - R => '0' + I0 => \^p_0_in\, + I1 => Q(1), + O => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][1]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[8]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][2]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => Q(8), - Q => crnt_vsize_cdc_tig(8), - R => '0' + I0 => \^p_0_in\, + I1 => Q(2), + O => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][2]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_cdc_tig_reg[9]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][3]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => Q(9), - Q => crnt_vsize_cdc_tig(9), - R => '0' + I0 => \^p_0_in\, + I1 => Q(3), + O => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][3]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[0]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][4]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => crnt_vsize_cdc_tig(0), - Q => crnt_vsize_d1(0), - R => '0' + I0 => \^p_0_in\, + I1 => Q(4), + O => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][4]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[10]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][5]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => crnt_vsize_cdc_tig(10), - Q => crnt_vsize_d1(10), - R => '0' + I0 => \^p_0_in\, + I1 => Q(5), + O => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][5]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[11]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][6]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" + ) + port map ( + I0 => \^p_0_in\, + I1 => Q(6), + O => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][6]_i_1_n_0\ + ); +\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][7]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^p_0_in\, + I1 => Q(7), + O => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][7]_i_1_n_0\ + ); +\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[1]_6\, + D => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][0]_i_1_n_0\, + Q => lsig_combined_data(8), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[1]_6\, + D => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][1]_i_1_n_0\, + Q => lsig_combined_data(9), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[1]_6\, + D => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][2]_i_1_n_0\, + Q => lsig_combined_data(10), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[1]_6\, + D => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][3]_i_1_n_0\, + Q => lsig_combined_data(11), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[1]_6\, + D => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][4]_i_1_n_0\, + Q => lsig_combined_data(12), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][5]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[1]_6\, + D => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][5]_i_1_n_0\, + Q => lsig_combined_data(13), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][6]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[1]_6\, + D => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][6]_i_1_n_0\, + Q => lsig_combined_data(14), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][7]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[1]_6\, + D => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg[1][7]_i_1_n_0\, + Q => lsig_combined_data(15), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg[1][1]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"001D000000000000" + ) + port map ( + I0 => \^include_packing.lsig_0ffset_cntr_reg[2]_1\(1), + I1 => \^include_packing.lsig_0ffset_cntr_reg[2]_0\, + I2 => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(1), + I3 => \lsig_0ffset_to_to_use__2\(2), + I4 => \lsig_0ffset_to_to_use__2\(0), + I5 => \INFERRED_GEN.cnt_i_reg[4]\(0), + O => \^p_0_in\ + ); +\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg[1][1]_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(2), + I1 => \^include_packing.lsig_0ffset_cntr_reg[2]_0\, + I2 => lsig_0ffset_cntr(2), + O => \lsig_0ffset_to_to_use__2\(2) + ); +\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg[1][1]_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(0), + I1 => \^include_packing.lsig_0ffset_cntr_reg[2]_0\, + I2 => \^include_packing.lsig_0ffset_cntr_reg[2]_1\(0), + O => \lsig_0ffset_to_to_use__2\(0) + ); +\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[1]_6\, + D => sig_m_valid_out_reg(0), + Q => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg_n_0_[1][0]\, + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[1]_6\, + D => sig_m_valid_out_reg(1), + Q => \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg_n_0_[1][1]\, + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][0]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^include_packing.do_reg_slices[2].lsig_segment_ld_reg__0\, + I1 => Q(0), + O => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][0]_i_1_n_0\ + ); +\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => crnt_vsize_cdc_tig(11), - Q => crnt_vsize_d1(11), - R => '0' + I0 => \^include_packing.do_reg_slices[2].lsig_segment_ld_reg__0\, + I1 => Q(1), + O => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][1]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[12]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][2]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => crnt_vsize_cdc_tig(12), - Q => crnt_vsize_d1(12), - R => '0' + I0 => \^include_packing.do_reg_slices[2].lsig_segment_ld_reg__0\, + I1 => Q(2), + O => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][2]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[1]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][3]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => crnt_vsize_cdc_tig(1), - Q => crnt_vsize_d1(1), - R => '0' + I0 => \^include_packing.do_reg_slices[2].lsig_segment_ld_reg__0\, + I1 => Q(3), + O => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][3]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[2]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][4]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => crnt_vsize_cdc_tig(2), - Q => crnt_vsize_d1(2), - R => '0' + I0 => \^include_packing.do_reg_slices[2].lsig_segment_ld_reg__0\, + I1 => Q(4), + O => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][4]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[3]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][5]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => crnt_vsize_cdc_tig(3), - Q => crnt_vsize_d1(3), - R => '0' + I0 => \^include_packing.do_reg_slices[2].lsig_segment_ld_reg__0\, + I1 => Q(5), + O => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][5]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[4]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][6]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => crnt_vsize_cdc_tig(4), - Q => crnt_vsize_d1(4), - R => '0' + I0 => \^include_packing.do_reg_slices[2].lsig_segment_ld_reg__0\, + I1 => Q(6), + O => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][6]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[5]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][7]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => crnt_vsize_cdc_tig(5), - Q => crnt_vsize_d1(5), - R => '0' + I0 => \^include_packing.do_reg_slices[2].lsig_segment_ld_reg__0\, + I1 => Q(7), + O => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][7]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[6]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[2]_5\, + D => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][0]_i_1_n_0\, + Q => lsig_combined_data(16), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[2]_5\, + D => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][1]_i_1_n_0\, + Q => lsig_combined_data(17), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[2]_5\, + D => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][2]_i_1_n_0\, + Q => lsig_combined_data(18), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[2]_5\, + D => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][3]_i_1_n_0\, + Q => lsig_combined_data(19), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[2]_5\, + D => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][4]_i_1_n_0\, + Q => lsig_combined_data(20), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][5]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[2]_5\, + D => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][5]_i_1_n_0\, + Q => lsig_combined_data(21), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][6]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[2]_5\, + D => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][6]_i_1_n_0\, + Q => lsig_combined_data(22), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][7]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[2]_5\, + D => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg[2][7]_i_1_n_0\, + Q => lsig_combined_data(23), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg[2][1]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"0000540400000000" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => crnt_vsize_cdc_tig(6), - Q => crnt_vsize_d1(6), - R => '0' + I0 => \lsig_0ffset_to_to_use__2\(0), + I1 => \^include_packing.lsig_0ffset_cntr_reg[2]_1\(1), + I2 => \^include_packing.lsig_0ffset_cntr_reg[2]_0\, + I3 => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(1), + I4 => \lsig_0ffset_to_to_use__2\(2), + I5 => \INFERRED_GEN.cnt_i_reg[4]\(0), + O => \^include_packing.do_reg_slices[2].lsig_segment_ld_reg__0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[7]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[2]_5\, + D => sig_m_valid_out_reg_0(0), + Q => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg_n_0_[2][0]\, + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[2]_5\, + D => sig_m_valid_out_reg_0(1), + Q => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg_n_0_[2][1]\, + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][0]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => crnt_vsize_cdc_tig(7), - Q => crnt_vsize_d1(7), - R => '0' + I0 => \^include_packing.do_reg_slices[3].lsig_segment_ld_reg__0\, + I1 => Q(0), + O => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][0]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[8]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][1]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => crnt_vsize_cdc_tig(8), - Q => crnt_vsize_d1(8), - R => '0' + I0 => \^include_packing.do_reg_slices[3].lsig_segment_ld_reg__0\, + I1 => Q(1), + O => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][1]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.crnt_vsize_d1_reg[9]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][2]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => crnt_vsize_cdc_tig(9), - Q => crnt_vsize_d1(9), - R => '0' + I0 => \^include_packing.do_reg_slices[3].lsig_segment_ld_reg__0\, + I1 => Q(2), + O => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][2]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[0]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][3]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => '0', - Q => data_count_ae_threshold_cdc_tig(0), - R => '0' + I0 => \^include_packing.do_reg_slices[3].lsig_segment_ld_reg__0\, + I1 => Q(3), + O => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][3]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[10]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][4]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => '0', - Q => data_count_ae_threshold_cdc_tig(10), - R => '0' + I0 => \^include_packing.do_reg_slices[3].lsig_segment_ld_reg__0\, + I1 => Q(4), + O => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][4]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[11]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][5]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => '0', - Q => data_count_ae_threshold_cdc_tig(11), - R => '0' + I0 => \^include_packing.do_reg_slices[3].lsig_segment_ld_reg__0\, + I1 => Q(5), + O => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][5]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[1]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][6]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => '0', - Q => data_count_ae_threshold_cdc_tig(1), - R => '0' + I0 => \^include_packing.do_reg_slices[3].lsig_segment_ld_reg__0\, + I1 => Q(6), + O => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][6]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[2]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][7]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => '0', - Q => data_count_ae_threshold_cdc_tig(2), - R => '0' + I0 => \^include_packing.do_reg_slices[3].lsig_segment_ld_reg__0\, + I1 => Q(7), + O => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][7]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[3]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[3]_4\, + D => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][0]_i_1_n_0\, + Q => lsig_combined_data(24), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[3]_4\, + D => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][1]_i_1_n_0\, + Q => lsig_combined_data(25), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[3]_4\, + D => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][2]_i_1_n_0\, + Q => lsig_combined_data(26), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[3]_4\, + D => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][3]_i_1_n_0\, + Q => lsig_combined_data(27), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[3]_4\, + D => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][4]_i_1_n_0\, + Q => lsig_combined_data(28), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][5]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[3]_4\, + D => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][5]_i_1_n_0\, + Q => lsig_combined_data(29), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][6]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[3]_4\, + D => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][6]_i_1_n_0\, + Q => lsig_combined_data(30), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][7]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[3]_4\, + D => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg[3][7]_i_1_n_0\, + Q => lsig_combined_data(31), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg[3][1]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"00E2000000000000" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => '0', - Q => data_count_ae_threshold_cdc_tig(3), - R => '0' + I0 => \^include_packing.lsig_0ffset_cntr_reg[2]_1\(1), + I1 => \^include_packing.lsig_0ffset_cntr_reg[2]_0\, + I2 => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(1), + I3 => \lsig_0ffset_to_to_use__2\(2), + I4 => \lsig_0ffset_to_to_use__2\(0), + I5 => \INFERRED_GEN.cnt_i_reg[4]\(0), + O => \^include_packing.do_reg_slices[3].lsig_segment_ld_reg__0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[4]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[3]_4\, + D => sig_m_valid_out_reg_1(0), + Q => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg_n_0_[3][0]\, + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[3]_4\, + D => sig_m_valid_out_reg_1(1), + Q => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg_n_0_[3][1]\, + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][0]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => '0', - Q => data_count_ae_threshold_cdc_tig(4), - R => '0' + I0 => \^include_packing.do_reg_slices[4].lsig_segment_ld_reg__0\, + I1 => Q(0), + O => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][0]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[5]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][1]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => '0', - Q => data_count_ae_threshold_cdc_tig(5), - R => '0' + I0 => \^include_packing.do_reg_slices[4].lsig_segment_ld_reg__0\, + I1 => Q(1), + O => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][1]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[6]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][2]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => '0', - Q => data_count_ae_threshold_cdc_tig(6), - R => '0' + I0 => \^include_packing.do_reg_slices[4].lsig_segment_ld_reg__0\, + I1 => Q(2), + O => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][2]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[7]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][3]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => '0', - Q => data_count_ae_threshold_cdc_tig(7), - R => '0' + I0 => \^include_packing.do_reg_slices[4].lsig_segment_ld_reg__0\, + I1 => Q(3), + O => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][3]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[8]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][4]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => '0', - Q => data_count_ae_threshold_cdc_tig(8), - R => '0' + I0 => \^include_packing.do_reg_slices[4].lsig_segment_ld_reg__0\, + I1 => Q(4), + O => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][4]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_cdc_tig_reg[9]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][5]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => '0', - Q => data_count_ae_threshold_cdc_tig(9), - R => '0' + I0 => \^include_packing.do_reg_slices[4].lsig_segment_ld_reg__0\, + I1 => Q(5), + O => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][5]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[0]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][6]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => data_count_ae_threshold_cdc_tig(0), - Q => data_count_ae_threshold_d1(0), - R => '0' + I0 => \^include_packing.do_reg_slices[4].lsig_segment_ld_reg__0\, + I1 => Q(6), + O => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][6]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[10]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][7]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => data_count_ae_threshold_cdc_tig(10), - Q => data_count_ae_threshold_d1(10), - R => '0' + I0 => \^include_packing.do_reg_slices[4].lsig_segment_ld_reg__0\, + I1 => Q(7), + O => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][7]_i_1_n_0\ + ); +\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[4]_3\, + D => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][0]_i_1_n_0\, + Q => lsig_combined_data(32), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[4]_3\, + D => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][1]_i_1_n_0\, + Q => lsig_combined_data(33), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[4]_3\, + D => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][2]_i_1_n_0\, + Q => lsig_combined_data(34), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[4]_3\, + D => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][3]_i_1_n_0\, + Q => lsig_combined_data(35), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[4]_3\, + D => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][4]_i_1_n_0\, + Q => lsig_combined_data(36), + R => sig_stream_rst ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[11]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][5]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[4]_3\, + D => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][5]_i_1_n_0\, + Q => lsig_combined_data(37), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][6]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[4]_3\, + D => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][6]_i_1_n_0\, + Q => lsig_combined_data(38), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][7]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[4]_3\, + D => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg[4][7]_i_1_n_0\, + Q => lsig_combined_data(39), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg[4][1]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"0000540400000000" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => data_count_ae_threshold_cdc_tig(11), - Q => data_count_ae_threshold_d1(11), - R => '0' + I0 => \lsig_0ffset_to_to_use__2\(0), + I1 => lsig_0ffset_cntr(2), + I2 => \^include_packing.lsig_0ffset_cntr_reg[2]_0\, + I3 => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(2), + I4 => \lsig_0ffset_to_to_use__2\(1), + I5 => \INFERRED_GEN.cnt_i_reg[4]\(0), + O => \^include_packing.do_reg_slices[4].lsig_segment_ld_reg__0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[1]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg[4][1]_i_4\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"B8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => data_count_ae_threshold_cdc_tig(1), - Q => data_count_ae_threshold_d1(1), - R => '0' + I0 => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(1), + I1 => \^include_packing.lsig_0ffset_cntr_reg[2]_0\, + I2 => \^include_packing.lsig_0ffset_cntr_reg[2]_1\(1), + O => \lsig_0ffset_to_to_use__2\(1) ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[2]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[4]_3\, + D => sig_m_valid_out_reg_2(0), + Q => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg_n_0_[4][0]\, + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[4]_3\, + D => sig_m_valid_out_reg_2(1), + Q => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg_n_0_[4][1]\, + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][0]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => data_count_ae_threshold_cdc_tig(2), - Q => data_count_ae_threshold_d1(2), - R => '0' + I0 => \^include_packing.do_reg_slices[5].lsig_segment_ld_reg__0\, + I1 => Q(0), + O => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][0]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[3]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][1]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => data_count_ae_threshold_cdc_tig(3), - Q => data_count_ae_threshold_d1(3), - R => '0' + I0 => \^include_packing.do_reg_slices[5].lsig_segment_ld_reg__0\, + I1 => Q(1), + O => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][1]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[4]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][2]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => data_count_ae_threshold_cdc_tig(4), - Q => data_count_ae_threshold_d1(4), - R => '0' + I0 => \^include_packing.do_reg_slices[5].lsig_segment_ld_reg__0\, + I1 => Q(2), + O => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][2]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[5]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][3]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => data_count_ae_threshold_cdc_tig(5), - Q => data_count_ae_threshold_d1(5), - R => '0' + I0 => \^include_packing.do_reg_slices[5].lsig_segment_ld_reg__0\, + I1 => Q(3), + O => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][3]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[6]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][4]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => data_count_ae_threshold_cdc_tig(6), - Q => data_count_ae_threshold_d1(6), - R => '0' + I0 => \^include_packing.do_reg_slices[5].lsig_segment_ld_reg__0\, + I1 => Q(4), + O => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][4]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[7]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][5]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => data_count_ae_threshold_cdc_tig(7), - Q => data_count_ae_threshold_d1(7), - R => '0' + I0 => \^include_packing.do_reg_slices[5].lsig_segment_ld_reg__0\, + I1 => Q(5), + O => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][5]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[8]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][6]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => data_count_ae_threshold_cdc_tig(8), - Q => data_count_ae_threshold_d1(8), - R => '0' + I0 => \^include_packing.do_reg_slices[5].lsig_segment_ld_reg__0\, + I1 => Q(6), + O => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][6]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.data_count_ae_threshold_d1_reg[9]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][7]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => data_count_ae_threshold_cdc_tig(9), - Q => data_count_ae_threshold_d1(9), - R => '0' + I0 => \^include_packing.do_reg_slices[5].lsig_segment_ld_reg__0\, + I1 => Q(7), + O => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][7]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_afifo_builtin +\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0]\: unisim.vcomponents.FDRE port map ( - DIN(1) => \^din\(0), - DIN(0) => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\(0), - dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), - fifo_dout(33 downto 0) => fifo_dout(33 downto 0), - fifo_full_i => fifo_full_i, - \fifo_wren__0\ => \fifo_wren__0\, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axis_mm2s_aclk => m_axis_mm2s_aclk, - \out\ => p_4_in, - s_axis_fifo_ainit_nosync_reg => s_axis_fifo_ainit_nosync_reg, - sig_m_valid_out_reg => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_1\ + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[5]_2\, + D => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][0]_i_1_n_0\, + Q => lsig_combined_data(40), + R => sig_stream_rst ); -\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[5]_2\, + D => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][1]_i_1_n_0\, + Q => lsig_combined_data(41), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[5]_2\, + D => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][2]_i_1_n_0\, + Q => lsig_combined_data(42), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[5]_2\, + D => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][3]_i_1_n_0\, + Q => lsig_combined_data(43), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[5]_2\, + D => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][4]_i_1_n_0\, + Q => lsig_combined_data(44), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][5]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[5]_2\, + D => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][5]_i_1_n_0\, + Q => lsig_combined_data(45), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][6]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[5]_2\, + D => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][6]_i_1_n_0\, + Q => lsig_combined_data(46), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][7]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[5]_2\, + D => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg[5][7]_i_1_n_0\, + Q => lsig_combined_data(47), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg[5][1]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => '0' + INIT => X"00E2000000000000" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\, - Q => \^din\(0), - R => '0' + I0 => lsig_0ffset_cntr(2), + I1 => \^include_packing.lsig_0ffset_cntr_reg[2]_0\, + I2 => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(2), + I3 => \lsig_0ffset_to_to_use__2\(1), + I4 => \lsig_0ffset_to_to_use__2\(0), + I5 => \INFERRED_GEN.cnt_i_reg[4]\(0), + O => \^include_packing.do_reg_slices[5].lsig_segment_ld_reg__0\ ); -\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_skid_buf +\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][0]\: unisim.vcomponents.FDRE port map ( - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ => \^sig_reset_reg_reg\, - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\, - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO_n_1\, - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tlast_d1_reg\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID_n_6\, - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tvalid_d1_reg\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID_n_7\, - \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg\ => \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg_n_0\, - fifo_dout(33 downto 0) => fifo_dout(33 downto 0), - fifo_pipe_empty => fifo_pipe_empty, - m_axis_fifo_ainit_nosync => m_axis_fifo_ainit_nosync, - m_axis_mm2s_aclk => m_axis_mm2s_aclk, - m_axis_mm2s_tdata(31 downto 0) => m_axis_mm2s_tdata(31 downto 0), - m_axis_mm2s_tlast => m_axis_mm2s_tlast, - m_axis_mm2s_tready => m_axis_mm2s_tready, - m_axis_mm2s_tuser(0) => m_axis_mm2s_tuser(0), - m_axis_mm2s_tvalid => \out\, - \out\ => p_4_in, - p_15_out => p_15_out, - s_valid0 => s_valid0 + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[5]_2\, + D => sig_m_valid_out_reg_3(0), + Q => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg_n_0_[5][0]\, + R => sig_stream_rst ); -\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tlast_d1_reg\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[5]_2\, + D => sig_m_valid_out_reg_3(1), + Q => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg_n_0_[5][1]\, + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][0]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID_n_6\, - Q => m_axis_tlast_d1, - R => '0' + I0 => \^include_packing.do_reg_slices[6].lsig_segment_ld_reg__0\, + I1 => Q(0), + O => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][0]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tready_d1_reg\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][1]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I_n_2\, - Q => m_axis_tready_d1, - R => '0' + I0 => \^include_packing.do_reg_slices[6].lsig_segment_ld_reg__0\, + I1 => Q(1), + O => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][1]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.m_axis_tvalid_d1_reg\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][2]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => '1', - D => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.I_MSTR_SKID_n_7\, - Q => m_axis_tvalid_d1, - R => '0' + I0 => \^include_packing.do_reg_slices[6].lsig_segment_ld_reg__0\, + I1 => Q(2), + O => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][2]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.all_lines_xfred_reg\: unisim.vcomponents.FDSE +\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][3]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\, - D => all_lines_xfred, - Q => \GEN_LINEBUF_NO_SOF.all_lines_xfred_reg_n_0\, - S => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\(0) + I0 => \^include_packing.do_reg_slices[6].lsig_segment_ld_reg__0\, + I1 => Q(3), + O => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][3]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.s_axis_fifo_ainit_nosync_reg_reg\: unisim.vcomponents.FDSE +\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][4]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axi_mm2s_aclk, - CE => '1', - D => mm2s_halt, - Q => s_axis_fifo_ainit_nosync_reg, - S => SR(0) + I0 => \^include_packing.do_reg_slices[6].lsig_segment_ld_reg__0\, + I1 => Q(4), + O => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][4]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.vsize_counter[0]_i_1\: unisim.vcomponents.LUT4 +\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][5]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"8B88" + INIT => X"8" ) port map ( - I0 => crnt_vsize_d1(0), - I1 => p_15_out, - I2 => vsize_counter(0), - I3 => \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\, - O => \GEN_LINEBUF_NO_SOF.vsize_counter[0]_i_1_n_0\ + I0 => \^include_packing.do_reg_slices[6].lsig_segment_ld_reg__0\, + I1 => Q(5), + O => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][5]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.vsize_counter[10]_i_1\: unisim.vcomponents.LUT4 +\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][6]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"B888" + INIT => X"8" ) port map ( - I0 => crnt_vsize_d1(10), - I1 => p_15_out, - I2 => minusOp(10), - I3 => \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\, - O => \GEN_LINEBUF_NO_SOF.vsize_counter[10]_i_1_n_0\ + I0 => \^include_packing.do_reg_slices[6].lsig_segment_ld_reg__0\, + I1 => Q(6), + O => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][6]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.vsize_counter[11]_i_1\: unisim.vcomponents.LUT4 +\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][7]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"B888" + INIT => X"8" ) port map ( - I0 => crnt_vsize_d1(11), - I1 => p_15_out, - I2 => minusOp(11), - I3 => \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\, - O => \GEN_LINEBUF_NO_SOF.vsize_counter[11]_i_1_n_0\ + I0 => \^include_packing.do_reg_slices[6].lsig_segment_ld_reg__0\, + I1 => Q(7), + O => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][7]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2\: unisim.vcomponents.LUT6 +\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[6]_1\, + D => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][0]_i_1_n_0\, + Q => lsig_combined_data(48), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[6]_1\, + D => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][1]_i_1_n_0\, + Q => lsig_combined_data(49), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[6]_1\, + D => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][2]_i_1_n_0\, + Q => lsig_combined_data(50), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[6]_1\, + D => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][3]_i_1_n_0\, + Q => lsig_combined_data(51), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[6]_1\, + D => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][4]_i_1_n_0\, + Q => lsig_combined_data(52), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][5]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[6]_1\, + D => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][5]_i_1_n_0\, + Q => lsig_combined_data(53), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][6]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[6]_1\, + D => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][6]_i_1_n_0\, + Q => lsig_combined_data(54), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][7]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[6]_1\, + D => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg[6][7]_i_1_n_0\, + Q => lsig_combined_data(55), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg[6][1]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"BBBBBBBBBBBBBBBA" + INIT => X"5404000000000000" ) port map ( - I0 => p_15_out, - I1 => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_4_n_0\, - I2 => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_5_n_0\, - I3 => vsize_counter(3), - I4 => vsize_counter(4), - I5 => vsize_counter(0), - O => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\ + I0 => \lsig_0ffset_to_to_use__2\(0), + I1 => \^include_packing.lsig_0ffset_cntr_reg[2]_1\(1), + I2 => \^include_packing.lsig_0ffset_cntr_reg[2]_0\, + I3 => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(1), + I4 => \lsig_0ffset_to_to_use__2\(2), + I5 => \INFERRED_GEN.cnt_i_reg[4]\(0), + O => \^include_packing.do_reg_slices[6].lsig_segment_ld_reg__0\ + ); +\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[6]_1\, + D => sig_m_valid_out_reg_4(0), + Q => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg_n_0_[6][0]\, + R => sig_stream_rst ); -\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_3\: unisim.vcomponents.LUT4 +\INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[6]_1\, + D => sig_m_valid_out_reg_4(1), + Q => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg_n_0_[6][1]\, + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][0]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"B888" + INIT => X"8" ) port map ( - I0 => crnt_vsize_d1(12), - I1 => p_15_out, - I2 => minusOp(12), - I3 => \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\, - O => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_3_n_0\ + I0 => \^include_packing.do_reg_slices[7].lsig_segment_ld_reg__0\, + I1 => Q(0), + O => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][0]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_4\: unisim.vcomponents.LUT3 +\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][1]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"7F" + INIT => X"8" ) port map ( - I0 => m_axis_tvalid_d1, - I1 => m_axis_tlast_d1, - I2 => m_axis_tready_d1, - O => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_4_n_0\ + I0 => \^include_packing.do_reg_slices[7].lsig_segment_ld_reg__0\, + I1 => Q(1), + O => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][1]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_5\: unisim.vcomponents.LUT5 +\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][2]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"FFFFFFFE" + INIT => X"8" ) port map ( - I0 => vsize_counter(1), - I1 => vsize_counter(10), - I2 => vsize_counter(7), - I3 => vsize_counter(12), - I4 => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_7_n_0\, - O => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_5_n_0\ + I0 => \^include_packing.do_reg_slices[7].lsig_segment_ld_reg__0\, + I1 => Q(2), + O => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][2]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_6\: unisim.vcomponents.LUT5 +\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][3]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"FFFFFEFF" + INIT => X"8" ) port map ( - I0 => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_5_n_0\, - I1 => vsize_counter(4), - I2 => vsize_counter(3), - I3 => vsize_counter(0), - I4 => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_4_n_0\, - O => \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\ + I0 => \^include_packing.do_reg_slices[7].lsig_segment_ld_reg__0\, + I1 => Q(3), + O => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][3]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_7\: unisim.vcomponents.LUT6 +\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][4]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"FFFFFFFFFFFFFFFE" + INIT => X"8" ) port map ( - I0 => vsize_counter(11), - I1 => vsize_counter(6), - I2 => vsize_counter(2), - I3 => vsize_counter(8), - I4 => vsize_counter(5), - I5 => vsize_counter(9), - O => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_7_n_0\ + I0 => \^include_packing.do_reg_slices[7].lsig_segment_ld_reg__0\, + I1 => Q(4), + O => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][4]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.vsize_counter[1]_i_1\: unisim.vcomponents.LUT4 +\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][5]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"B888" + INIT => X"8" ) port map ( - I0 => crnt_vsize_d1(1), - I1 => p_15_out, - I2 => minusOp(1), - I3 => \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\, - O => \GEN_LINEBUF_NO_SOF.vsize_counter[1]_i_1_n_0\ + I0 => \^include_packing.do_reg_slices[7].lsig_segment_ld_reg__0\, + I1 => Q(5), + O => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][5]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.vsize_counter[2]_i_1\: unisim.vcomponents.LUT4 +\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][6]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"B888" + INIT => X"8" ) port map ( - I0 => crnt_vsize_d1(2), - I1 => p_15_out, - I2 => minusOp(2), - I3 => \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\, - O => \GEN_LINEBUF_NO_SOF.vsize_counter[2]_i_1_n_0\ + I0 => \^include_packing.do_reg_slices[7].lsig_segment_ld_reg__0\, + I1 => Q(6), + O => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][6]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.vsize_counter[3]_i_1\: unisim.vcomponents.LUT4 +\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][7]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"B888" + INIT => X"8" ) port map ( - I0 => crnt_vsize_d1(3), - I1 => p_15_out, - I2 => minusOp(3), - I3 => \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\, - O => \GEN_LINEBUF_NO_SOF.vsize_counter[3]_i_1_n_0\ + I0 => \^include_packing.do_reg_slices[7].lsig_segment_ld_reg__0\, + I1 => Q(7), + O => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][7]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_1\: unisim.vcomponents.LUT4 +\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[7]_0\, + D => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][0]_i_1_n_0\, + Q => lsig_combined_data(56), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[7]_0\, + D => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][1]_i_1_n_0\, + Q => lsig_combined_data(57), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][2]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[7]_0\, + D => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][2]_i_1_n_0\, + Q => lsig_combined_data(58), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][3]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[7]_0\, + D => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][3]_i_1_n_0\, + Q => lsig_combined_data(59), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][4]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[7]_0\, + D => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][4]_i_1_n_0\, + Q => lsig_combined_data(60), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][5]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[7]_0\, + D => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][5]_i_1_n_0\, + Q => lsig_combined_data(61), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][6]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[7]_0\, + D => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][6]_i_1_n_0\, + Q => lsig_combined_data(62), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[7]_0\, + D => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg[7][7]_i_1_n_0\, + Q => lsig_combined_data(63), + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg[7][1]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"B888" + INIT => X"A808000000000000" ) port map ( - I0 => crnt_vsize_d1(4), - I1 => p_15_out, - I2 => minusOp(4), - I3 => \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\, - O => \GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_1_n_0\ + I0 => \INFERRED_GEN.cnt_i_reg[4]\(0), + I1 => \^include_packing.lsig_0ffset_cntr_reg[2]_1\(1), + I2 => \^include_packing.lsig_0ffset_cntr_reg[2]_0\, + I3 => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(1), + I4 => \lsig_0ffset_to_to_use__2\(2), + I5 => \lsig_0ffset_to_to_use__2\(0), + O => \^include_packing.do_reg_slices[7].lsig_segment_ld_reg__0\ ); -\GEN_LINEBUF_NO_SOF.vsize_counter[5]_i_1\: unisim.vcomponents.LUT4 +\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[7]_0\, + D => sig_m_valid_out_reg_5(0), + Q => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg_n_0_[7][0]\, + R => sig_stream_rst + ); +\INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1]\: unisim.vcomponents.FDRE + port map ( + C => m_axi_s2mm_aclk, + CE => \lsig_flag_slice_reg[7]_0\, + D => sig_m_valid_out_reg_5(1), + Q => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg_n_0_[7][1]\, + R => sig_stream_rst + ); +\INCLUDE_PACKING.lsig_0ffset_cntr[2]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"B888" + INIT => X"AA3FFFFFAAC00000" ) port map ( - I0 => crnt_vsize_d1(5), - I1 => p_15_out, - I2 => minusOp(5), - I3 => \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\, - O => \GEN_LINEBUF_NO_SOF.vsize_counter[5]_i_1_n_0\ + I0 => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[0]_1\, + I1 => \^include_packing.lsig_0ffset_cntr_reg[2]_1\(0), + I2 => \^include_packing.lsig_0ffset_cntr_reg[2]_1\(1), + I3 => \^include_packing.lsig_0ffset_cntr_reg[2]_0\, + I4 => \INFERRED_GEN.cnt_i_reg[4]\(0), + I5 => lsig_0ffset_cntr(2), + O => \INCLUDE_PACKING.lsig_0ffset_cntr[2]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.vsize_counter[6]_i_1\: unisim.vcomponents.LUT4 +\INCLUDE_PACKING.lsig_0ffset_cntr_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => X"B888" + INIT => '0' ) port map ( - I0 => crnt_vsize_d1(6), - I1 => p_15_out, - I2 => minusOp(6), - I3 => \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\, - O => \GEN_LINEBUF_NO_SOF.vsize_counter[6]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[0]_0\, + Q => \^include_packing.lsig_0ffset_cntr_reg[2]_1\(0), + R => sig_stream_rst ); -\GEN_LINEBUF_NO_SOF.vsize_counter[7]_i_1\: unisim.vcomponents.LUT4 +\INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\: unisim.vcomponents.FDRE generic map( - INIT => X"B888" + INIT => '0' ) port map ( - I0 => crnt_vsize_d1(7), - I1 => p_15_out, - I2 => minusOp(7), - I3 => \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\, - O => \GEN_LINEBUF_NO_SOF.vsize_counter[7]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => '1', + D => \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[0]\, + Q => \^include_packing.lsig_0ffset_cntr_reg[2]_1\(1), + R => sig_stream_rst ); -\GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_1\: unisim.vcomponents.LUT4 +\INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]\: unisim.vcomponents.FDRE generic map( - INIT => X"B888" + INIT => '0' ) port map ( - I0 => crnt_vsize_d1(8), - I1 => p_15_out, - I2 => minusOp(8), - I3 => \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\, - O => \GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => '1', + D => \INCLUDE_PACKING.lsig_0ffset_cntr[2]_i_1_n_0\, + Q => lsig_0ffset_cntr(2), + R => sig_stream_rst ); -\GEN_LINEBUF_NO_SOF.vsize_counter[9]_i_1\: unisim.vcomponents.LUT4 +\INCLUDE_PACKING.lsig_first_dbeat_reg\: unisim.vcomponents.FDSE generic map( - INIT => X"B888" + INIT => '0' ) port map ( - I0 => crnt_vsize_d1(9), - I1 => p_15_out, - I2 => minusOp(9), - I3 => \^gen_linebuf_no_sof.vsize_counter_reg[0]_0\, - O => \GEN_LINEBUF_NO_SOF.vsize_counter[9]_i_1_n_0\ + C => m_axi_s2mm_aclk, + CE => '1', + D => \INCLUDE_PACKING.lsig_first_dbeat_reg_0\, + Q => \^include_packing.lsig_0ffset_cntr_reg[2]_0\, + S => sig_stream_rst ); -\GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]\: unisim.vcomponents.FDRE +\INCLUDE_PACKING.lsig_packer_full_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\, - D => \GEN_LINEBUF_NO_SOF.vsize_counter[0]_i_1_n_0\, - Q => vsize_counter(0), - R => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\(0) + C => m_axi_s2mm_aclk, + CE => '1', + D => I_DATA_FIFO_n_69, + Q => lsig_packer_full, + R => sig_stream_rst ); -\GEN_LINEBUF_NO_SOF.vsize_counter_reg[10]\: unisim.vcomponents.FDRE +I_DATA_FIFO: entity work.\Arty_Z7_20_axi_vdma_0_0_axi_datamover_sfifo_autord__parameterized1\ + port map ( + DIBDI(1 downto 0) => \sig_data_fifo_data_in__0\(65 downto 64), + E(0) => \lsig_flag_slice_reg[7]_0\, + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_data_slice_reg_reg[0][0]\(0) => \lsig_flag_slice_reg[0]_7\, + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_data_slice_reg_reg[1][0]\(0) => \lsig_flag_slice_reg[1]_6\, + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_data_slice_reg_reg[2][0]\(0) => \lsig_flag_slice_reg[2]_5\, + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_data_slice_reg_reg[3][0]\(0) => \lsig_flag_slice_reg[3]_4\, + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_data_slice_reg_reg[4][0]\(0) => \lsig_flag_slice_reg[4]_3\, + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_data_slice_reg_reg[5][0]\(0) => \lsig_flag_slice_reg[5]_2\, + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_data_slice_reg_reg[6][0]\(0) => \lsig_flag_slice_reg[6]_1\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\ => \^include_packing.do_reg_slices[7].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\ => \^include_packing.do_reg_slices[6].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_1\ => \^include_packing.do_reg_slices[3].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_2\ => \^include_packing.do_reg_slices[2].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_3\ => \^p_0_in\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_4\ => \^include_packing.do_reg_slices[0].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]\ => \^include_packing.do_reg_slices[5].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0\ => \^include_packing.do_reg_slices[4].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.lsig_packer_full_reg\ => I_DATA_FIFO_n_69, + \gcc0.gc0.count_d1_reg[7]\ => p_2_in, + hold_ff_q => hold_ff_q, + lsig_combined_data(63 downto 0) => lsig_combined_data(63 downto 0), + lsig_packer_full => lsig_packer_full, + \lsig_set_packer_full__1\ => \lsig_set_packer_full__1\, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\ => I_DATA_FIFO_n_66, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_data_fifo_data_out(65 downto 0) => sig_data_fifo_data_out(65 downto 0), + sig_data_fifo_dvalid => sig_data_fifo_dvalid, + sig_s_ready_out_reg => p_4_out, + sig_stream_rst => sig_stream_rst + ); +I_XD_FIFO: entity work.\Arty_Z7_20_axi_vdma_0_0_axi_datamover_sfifo_autord__parameterized0\ + port map ( + CO(0) => CO(0), + D(2 downto 0) => D(2 downto 0), + E(0) => \gcc0.gc0.count_d1_reg[0]\(0), + O(3 downto 0) => O(3 downto 0), + S(3 downto 0) => S(3 downto 0), + \gpr1.dout_i_reg[1]\(2 downto 0) => \gpr1.dout_i_reg[1]\(2 downto 0), + \gpr1.dout_i_reg[1]_0\(2 downto 0) => \gpr1.dout_i_reg[1]_0\(2 downto 0), + \gpr1.dout_i_reg[3]\(3 downto 0) => \gpr1.dout_i_reg[3]\(3 downto 0), + \gpr1.dout_i_reg[7]\(3 downto 0) => \gpr1.dout_i_reg[7]\(3 downto 0), + lsig_packer_full => lsig_packer_full, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + p_0_out(10 downto 0) => p_0_out(10 downto 0), + p_32_out => p_32_out, + ram_full_i_reg => p_2_in, + sig_adjusted_addr_incr(8 downto 0) => sig_adjusted_addr_incr(8 downto 0), + sig_child_addr_cntr_lsh_reg(2 downto 0) => sig_child_addr_cntr_lsh_reg(2 downto 0), + \sig_child_addr_cntr_lsh_reg[11]\(0) => \sig_child_addr_cntr_lsh_reg[11]\(0), + \sig_child_addr_cntr_lsh_reg[7]\(3 downto 0) => \sig_child_addr_cntr_lsh_reg[7]\(3 downto 0), + sig_child_qual_error_reg => sig_child_qual_error_reg, + sig_child_qual_first_of_2 => sig_child_qual_first_of_2, + sig_clr_dbc_reg_reg => \^sig_clr_dbc_reg\, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_csm_pop_child_cmd => sig_csm_pop_child_cmd, + sig_csm_state_ns1 => sig_csm_state_ns1, + sig_ibtt2dre_tready => sig_ibtt2dre_tready, + sig_sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid, + sig_stream_rst => sig_stream_rst, + sig_xfer_cmd_cmplt_reg0 => sig_xfer_cmd_cmplt_reg0, + sig_xfer_is_seq_reg_reg(9 downto 0) => sig_xfer_is_seq_reg_reg(9 downto 0), + sig_xfer_is_seq_reg_reg_0 => sig_xfer_is_seq_reg_reg_0, + \sig_xfer_len_reg_reg[4]\(3 downto 0) => \sig_xfer_len_reg_reg[4]\(3 downto 0), + \sig_xfer_len_reg_reg[5]\(0) => \sig_xfer_len_reg_reg[5]\(0) + ); +\sig_burst_dbeat_cntr[0]_i_1\: unisim.vcomponents.LUT1 generic map( - INIT => '0' + INIT => X"1" ) port map ( - C => m_axis_mm2s_aclk, - CE => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\, - D => \GEN_LINEBUF_NO_SOF.vsize_counter[10]_i_1_n_0\, - Q => vsize_counter(10), - R => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\(0) + I0 => \sig_burst_dbeat_cntr_reg__0\(0), + O => \p_0_in__1\(0) ); -\GEN_LINEBUF_NO_SOF.vsize_counter_reg[11]\: unisim.vcomponents.FDRE +\sig_burst_dbeat_cntr[1]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"6" ) port map ( - C => m_axis_mm2s_aclk, - CE => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\, - D => \GEN_LINEBUF_NO_SOF.vsize_counter[11]_i_1_n_0\, - Q => vsize_counter(11), - R => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\(0) + I0 => \sig_burst_dbeat_cntr_reg__0\(0), + I1 => \sig_burst_dbeat_cntr_reg__0\(1), + O => \p_0_in__1\(1) ); -\GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]\: unisim.vcomponents.FDRE +\sig_burst_dbeat_cntr[2]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => '0' + INIT => X"78" ) port map ( - C => m_axis_mm2s_aclk, - CE => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\, - D => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_3_n_0\, - Q => vsize_counter(12), - R => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\(0) + I0 => \sig_burst_dbeat_cntr_reg__0\(0), + I1 => \sig_burst_dbeat_cntr_reg__0\(1), + I2 => \sig_burst_dbeat_cntr_reg__0\(2), + O => \sig_burst_dbeat_cntr[2]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.vsize_counter_reg[1]\: unisim.vcomponents.FDRE +\sig_burst_dbeat_cntr[3]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => '0' + INIT => X"7F80" ) port map ( - C => m_axis_mm2s_aclk, - CE => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\, - D => \GEN_LINEBUF_NO_SOF.vsize_counter[1]_i_1_n_0\, - Q => vsize_counter(1), - R => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\(0) + I0 => \sig_burst_dbeat_cntr_reg__0\(1), + I1 => \sig_burst_dbeat_cntr_reg__0\(0), + I2 => \sig_burst_dbeat_cntr_reg__0\(2), + I3 => \sig_burst_dbeat_cntr_reg__0\(3), + O => \p_0_in__1\(3) ); -\GEN_LINEBUF_NO_SOF.vsize_counter_reg[2]\: unisim.vcomponents.FDRE +\sig_burst_dbeat_cntr[4]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => '0' + INIT => X"E000FFFF" ) port map ( - C => m_axis_mm2s_aclk, - CE => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\, - D => \GEN_LINEBUF_NO_SOF.vsize_counter[2]_i_1_n_0\, - Q => vsize_counter(2), - R => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\(0) + I0 => \sig_dbc_max__3\, + I1 => sig_dre2ibtt_tlast, + I2 => \INFERRED_GEN.cnt_i_reg[4]\(0), + I3 => \lsig_set_packer_full__1\, + I4 => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + O => \sig_burst_dbeat_cntr[4]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.vsize_counter_reg[3]\: unisim.vcomponents.FDRE +\sig_burst_dbeat_cntr[4]_i_2\: unisim.vcomponents.LUT2 generic map( - INIT => '0' + INIT => X"8" ) port map ( - C => m_axis_mm2s_aclk, - CE => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\, - D => \GEN_LINEBUF_NO_SOF.vsize_counter[3]_i_1_n_0\, - Q => vsize_counter(3), - R => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\(0) + I0 => \lsig_set_packer_full__1\, + I1 => \INFERRED_GEN.cnt_i_reg[4]\(0), + O => sig_incr_dbeat_cntr ); -\GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]\: unisim.vcomponents.FDRE +\sig_burst_dbeat_cntr[4]_i_3\: unisim.vcomponents.LUT5 generic map( - INIT => '0' + INIT => X"7FFF8000" ) port map ( - C => m_axis_mm2s_aclk, - CE => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\, - D => \GEN_LINEBUF_NO_SOF.vsize_counter[4]_i_1_n_0\, - Q => vsize_counter(4), - R => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\(0) + I0 => \sig_burst_dbeat_cntr_reg__0\(2), + I1 => \sig_burst_dbeat_cntr_reg__0\(0), + I2 => \sig_burst_dbeat_cntr_reg__0\(1), + I3 => \sig_burst_dbeat_cntr_reg__0\(3), + I4 => \sig_burst_dbeat_cntr_reg__0\(4), + O => \p_0_in__1\(4) ); -\GEN_LINEBUF_NO_SOF.vsize_counter_reg[5]\: unisim.vcomponents.FDRE +\sig_burst_dbeat_cntr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\, - D => \GEN_LINEBUF_NO_SOF.vsize_counter[5]_i_1_n_0\, - Q => vsize_counter(5), - R => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\(0) + C => m_axi_s2mm_aclk, + CE => sig_incr_dbeat_cntr, + D => \p_0_in__1\(0), + Q => \sig_burst_dbeat_cntr_reg__0\(0), + R => \sig_burst_dbeat_cntr[4]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.vsize_counter_reg[6]\: unisim.vcomponents.FDRE +\sig_burst_dbeat_cntr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\, - D => \GEN_LINEBUF_NO_SOF.vsize_counter[6]_i_1_n_0\, - Q => vsize_counter(6), - R => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\(0) + C => m_axi_s2mm_aclk, + CE => sig_incr_dbeat_cntr, + D => \p_0_in__1\(1), + Q => \sig_burst_dbeat_cntr_reg__0\(1), + R => \sig_burst_dbeat_cntr[4]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.vsize_counter_reg[7]\: unisim.vcomponents.FDRE +\sig_burst_dbeat_cntr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\, - D => \GEN_LINEBUF_NO_SOF.vsize_counter[7]_i_1_n_0\, - Q => vsize_counter(7), - R => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\(0) + C => m_axi_s2mm_aclk, + CE => sig_incr_dbeat_cntr, + D => \sig_burst_dbeat_cntr[2]_i_1_n_0\, + Q => \sig_burst_dbeat_cntr_reg__0\(2), + R => \sig_burst_dbeat_cntr[4]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.vsize_counter_reg[8]\: unisim.vcomponents.FDRE +\sig_burst_dbeat_cntr_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\, - D => \GEN_LINEBUF_NO_SOF.vsize_counter[8]_i_1_n_0\, - Q => vsize_counter(8), - R => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\(0) + C => m_axi_s2mm_aclk, + CE => sig_incr_dbeat_cntr, + D => \p_0_in__1\(3), + Q => \sig_burst_dbeat_cntr_reg__0\(3), + R => \sig_burst_dbeat_cntr[4]_i_1_n_0\ ); -\GEN_LINEBUF_NO_SOF.vsize_counter_reg[9]\: unisim.vcomponents.FDRE +\sig_burst_dbeat_cntr_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axis_mm2s_aclk, - CE => \GEN_LINEBUF_NO_SOF.vsize_counter[12]_i_2_n_0\, - D => \GEN_LINEBUF_NO_SOF.vsize_counter[9]_i_1_n_0\, - Q => vsize_counter(9), - R => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\(0) - ); -minusOp_carry: unisim.vcomponents.CARRY4 - port map ( - CI => '0', - CO(3) => minusOp_carry_n_0, - CO(2) => minusOp_carry_n_1, - CO(1) => minusOp_carry_n_2, - CO(0) => minusOp_carry_n_3, - CYINIT => vsize_counter(0), - DI(3 downto 0) => vsize_counter(4 downto 1), - O(3 downto 0) => minusOp(4 downto 1), - S(3) => minusOp_carry_i_1_n_0, - S(2) => minusOp_carry_i_2_n_0, - S(1) => minusOp_carry_i_3_n_0, - S(0) => minusOp_carry_i_4_n_0 - ); -\minusOp_carry__0\: unisim.vcomponents.CARRY4 - port map ( - CI => minusOp_carry_n_0, - CO(3) => \minusOp_carry__0_n_0\, - CO(2) => \minusOp_carry__0_n_1\, - CO(1) => \minusOp_carry__0_n_2\, - CO(0) => \minusOp_carry__0_n_3\, - CYINIT => '0', - DI(3 downto 0) => vsize_counter(8 downto 5), - O(3 downto 0) => minusOp(8 downto 5), - S(3) => \minusOp_carry__0_i_1_n_0\, - S(2) => \minusOp_carry__0_i_2_n_0\, - S(1) => \minusOp_carry__0_i_3_n_0\, - S(0) => \minusOp_carry__0_i_4_n_0\ + C => m_axi_s2mm_aclk, + CE => sig_incr_dbeat_cntr, + D => \p_0_in__1\(4), + Q => \sig_burst_dbeat_cntr_reg__0\(4), + R => \sig_burst_dbeat_cntr[4]_i_1_n_0\ ); -\minusOp_carry__0_i_1\: unisim.vcomponents.LUT1 +\sig_byte_cntr[3]_i_3\: unisim.vcomponents.LUT3 generic map( - INIT => X"1" + INIT => X"2A" ) port map ( - I0 => vsize_counter(8), - O => \minusOp_carry__0_i_1_n_0\ + I0 => \^di\(3), + I1 => \INFERRED_GEN.cnt_i_reg[4]\(0), + I2 => \^sig_clr_dbc_reg\, + O => \sig_byte_cntr[3]_i_3_n_0\ ); -\minusOp_carry__0_i_2\: unisim.vcomponents.LUT1 +\sig_byte_cntr[3]_i_4\: unisim.vcomponents.LUT3 generic map( - INIT => X"1" + INIT => X"2A" ) port map ( - I0 => vsize_counter(7), - O => \minusOp_carry__0_i_2_n_0\ + I0 => \^di\(2), + I1 => \INFERRED_GEN.cnt_i_reg[4]\(0), + I2 => \^sig_clr_dbc_reg\, + O => \sig_byte_cntr[3]_i_4_n_0\ ); -\minusOp_carry__0_i_3\: unisim.vcomponents.LUT1 +\sig_byte_cntr[3]_i_5\: unisim.vcomponents.LUT3 generic map( - INIT => X"1" + INIT => X"2A" ) port map ( - I0 => vsize_counter(6), - O => \minusOp_carry__0_i_3_n_0\ + I0 => \^di\(1), + I1 => \INFERRED_GEN.cnt_i_reg[4]\(0), + I2 => \^sig_clr_dbc_reg\, + O => \sig_byte_cntr[3]_i_5_n_0\ ); -\minusOp_carry__0_i_4\: unisim.vcomponents.LUT1 +\sig_byte_cntr[3]_i_6\: unisim.vcomponents.LUT4 generic map( - INIT => X"1" + INIT => X"D52A" ) port map ( - I0 => vsize_counter(5), - O => \minusOp_carry__0_i_4_n_0\ + I0 => \^di\(0), + I1 => \INFERRED_GEN.cnt_i_reg[4]\(0), + I2 => \^sig_clr_dbc_reg\, + I3 => sig_dre2ibtt_tstrb, + O => \sig_byte_cntr[3]_i_6_n_0\ ); -\minusOp_carry__1\: unisim.vcomponents.CARRY4 - port map ( - CI => \minusOp_carry__0_n_0\, - CO(3) => \NLW_minusOp_carry__1_CO_UNCONNECTED\(3), - CO(2) => \minusOp_carry__1_n_1\, - CO(1) => \minusOp_carry__1_n_2\, - CO(0) => \minusOp_carry__1_n_3\, - CYINIT => '0', - DI(3) => '0', - DI(2 downto 0) => vsize_counter(11 downto 9), - O(3 downto 0) => minusOp(12 downto 9), - S(3) => \minusOp_carry__1_i_1_n_0\, - S(2) => \minusOp_carry__1_i_2_n_0\, - S(1) => \minusOp_carry__1_i_3_n_0\, - S(0) => \minusOp_carry__1_i_4_n_0\ +\sig_byte_cntr[7]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"2A" + ) + port map ( + I0 => \^di\(7), + I1 => \INFERRED_GEN.cnt_i_reg[4]\(0), + I2 => \^sig_clr_dbc_reg\, + O => \sig_byte_cntr[7]_i_3_n_0\ ); -\minusOp_carry__1_i_1\: unisim.vcomponents.LUT1 +\sig_byte_cntr[7]_i_4\: unisim.vcomponents.LUT3 generic map( - INIT => X"1" + INIT => X"2A" ) port map ( - I0 => vsize_counter(12), - O => \minusOp_carry__1_i_1_n_0\ + I0 => \^di\(6), + I1 => \INFERRED_GEN.cnt_i_reg[4]\(0), + I2 => \^sig_clr_dbc_reg\, + O => \sig_byte_cntr[7]_i_4_n_0\ ); -\minusOp_carry__1_i_2\: unisim.vcomponents.LUT1 +\sig_byte_cntr[7]_i_5\: unisim.vcomponents.LUT3 generic map( - INIT => X"1" + INIT => X"2A" ) port map ( - I0 => vsize_counter(11), - O => \minusOp_carry__1_i_2_n_0\ + I0 => \^di\(5), + I1 => \INFERRED_GEN.cnt_i_reg[4]\(0), + I2 => \^sig_clr_dbc_reg\, + O => \sig_byte_cntr[7]_i_5_n_0\ ); -\minusOp_carry__1_i_3\: unisim.vcomponents.LUT1 +\sig_byte_cntr[7]_i_6\: unisim.vcomponents.LUT3 generic map( - INIT => X"1" + INIT => X"2A" ) port map ( - I0 => vsize_counter(10), - O => \minusOp_carry__1_i_3_n_0\ + I0 => \^di\(4), + I1 => \INFERRED_GEN.cnt_i_reg[4]\(0), + I2 => \^sig_clr_dbc_reg\, + O => \sig_byte_cntr[7]_i_6_n_0\ ); -\minusOp_carry__1_i_4\: unisim.vcomponents.LUT1 +\sig_byte_cntr[8]_i_4\: unisim.vcomponents.LUT3 generic map( - INIT => X"1" + INIT => X"2A" ) port map ( - I0 => vsize_counter(9), - O => \minusOp_carry__1_i_4_n_0\ + I0 => \^di\(8), + I1 => \INFERRED_GEN.cnt_i_reg[4]\(0), + I2 => \^sig_clr_dbc_reg\, + O => \sig_byte_cntr[8]_i_4_n_0\ ); -minusOp_carry_i_1: unisim.vcomponents.LUT1 +\sig_byte_cntr_reg[0]\: unisim.vcomponents.FDRE generic map( - INIT => X"1" + INIT => '0' ) port map ( - I0 => vsize_counter(4), - O => minusOp_carry_i_1_n_0 + C => m_axi_s2mm_aclk, + CE => \INFERRED_GEN.cnt_i_reg[4]\(0), + D => \sig_byte_cntr_reg[3]_i_1_n_7\, + Q => \^di\(0), + R => SR(0) ); -minusOp_carry_i_2: unisim.vcomponents.LUT1 +\sig_byte_cntr_reg[1]\: unisim.vcomponents.FDRE generic map( - INIT => X"1" + INIT => '0' ) port map ( - I0 => vsize_counter(3), - O => minusOp_carry_i_2_n_0 + C => m_axi_s2mm_aclk, + CE => \INFERRED_GEN.cnt_i_reg[4]\(0), + D => \sig_byte_cntr_reg[3]_i_1_n_6\, + Q => \^di\(1), + R => SR(0) ); -minusOp_carry_i_3: unisim.vcomponents.LUT1 +\sig_byte_cntr_reg[2]\: unisim.vcomponents.FDRE generic map( - INIT => X"1" + INIT => '0' ) port map ( - I0 => vsize_counter(2), - O => minusOp_carry_i_3_n_0 + C => m_axi_s2mm_aclk, + CE => \INFERRED_GEN.cnt_i_reg[4]\(0), + D => \sig_byte_cntr_reg[3]_i_1_n_5\, + Q => \^di\(2), + R => SR(0) ); -minusOp_carry_i_4: unisim.vcomponents.LUT1 +\sig_byte_cntr_reg[3]\: unisim.vcomponents.FDRE generic map( - INIT => X"1" + INIT => '0' ) port map ( - I0 => vsize_counter(1), - O => minusOp_carry_i_4_n_0 + C => m_axi_s2mm_aclk, + CE => \INFERRED_GEN.cnt_i_reg[4]\(0), + D => \sig_byte_cntr_reg[3]_i_1_n_4\, + Q => \^di\(3), + R => SR(0) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized0\ is - port ( - \out\ : out STD_LOGIC; - \sig_user_skid_reg_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - dm2linebuf_mm2s_tvalid : out STD_LOGIC; - DI : out STD_LOGIC_VECTOR ( 3 downto 0 ); - Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); - dm2linebuf_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - hold_ff_q_reg : out STD_LOGIC; - sig_ok_to_post_rd_addr_reg : out STD_LOGIC; - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : out STD_LOGIC; - \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : out STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[0]\ : out STD_LOGIC; - S : out STD_LOGIC_VECTOR ( 3 downto 0 ); - \count_reg[6]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - sig_stream_rst : in STD_LOGIC; - m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); - DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ); - lsig_0ffset_cntr : in STD_LOGIC; - lsig_cmd_loaded : in STD_LOGIC; - hold_ff_q : in STD_LOGIC; - \sig_token_cntr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); - p_8_out : in STD_LOGIC; - sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; - sig_posted_to_axi_2_reg : in STD_LOGIC; - sig_posted_to_axi_2_reg_0 : in STD_LOGIC; - p_0_out : in STD_LOGIC_VECTOR ( 0 to 0 ); - \INFERRED_GEN.cnt_i_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - \fifo_wren__0\ : in STD_LOGIC; - \mm2s_strm_wvalid0__1\ : in STD_LOGIC; - m_axi_mm2s_rvalid : in STD_LOGIC; - \sig_advance_pipe9_out__1\ : in STD_LOGIC; - D : in STD_LOGIC_VECTOR ( 5 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized0\ : entity is "fifo_generator_top"; -end \Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized0\; - -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized0\ is -begin -\grf.rf\: entity work.Arty_Z7_20_axi_vdma_0_0_fifo_generator_ramfifo +\sig_byte_cntr_reg[3]_i_1\: unisim.vcomponents.CARRY4 port map ( - D(5 downto 0) => D(5 downto 0), - DI(3 downto 0) => DI(3 downto 0), - DIBDI(1 downto 0) => DIBDI(1 downto 0), - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, - \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, - \INFERRED_GEN.cnt_i_reg[0]\ => \INFERRED_GEN.cnt_i_reg[0]\, - \INFERRED_GEN.cnt_i_reg[2]\(0) => \INFERRED_GEN.cnt_i_reg[2]\(0), - Q(1 downto 0) => Q(1 downto 0), - S(3 downto 0) => S(3 downto 0), - \count_reg[6]\(1 downto 0) => \count_reg[6]\(1 downto 0), - dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), - dm2linebuf_mm2s_tvalid => dm2linebuf_mm2s_tvalid, - \fifo_wren__0\ => \fifo_wren__0\, - hold_ff_q => hold_ff_q, - hold_ff_q_reg => hold_ff_q_reg, - lsig_0ffset_cntr => lsig_0ffset_cntr, - lsig_cmd_loaded => lsig_cmd_loaded, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axi_mm2s_rdata(63 downto 0) => m_axi_mm2s_rdata(63 downto 0), - m_axi_mm2s_rvalid => m_axi_mm2s_rvalid, - \mm2s_strm_wvalid0__1\ => \mm2s_strm_wvalid0__1\, - \out\ => \out\, - p_0_out(0) => p_0_out(0), - p_8_out => p_8_out, - \sig_advance_pipe9_out__1\ => \sig_advance_pipe9_out__1\, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_ok_to_post_rd_addr_reg => sig_ok_to_post_rd_addr_reg, - sig_posted_to_axi_2_reg => sig_posted_to_axi_2_reg, - sig_posted_to_axi_2_reg_0 => sig_posted_to_axi_2_reg_0, - sig_stream_rst => sig_stream_rst, - \sig_token_cntr_reg[3]\(3 downto 0) => \sig_token_cntr_reg[3]\(3 downto 0), - \sig_user_skid_reg_reg[0]\(0) => \sig_user_skid_reg_reg[0]\(0) + CI => '0', + CO(3) => \sig_byte_cntr_reg[3]_i_1_n_0\, + CO(2) => \sig_byte_cntr_reg[3]_i_1_n_1\, + CO(1) => \sig_byte_cntr_reg[3]_i_1_n_2\, + CO(0) => \sig_byte_cntr_reg[3]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => \sig_strb_reg_out_reg[0]\(0), + O(3) => \sig_byte_cntr_reg[3]_i_1_n_4\, + O(2) => \sig_byte_cntr_reg[3]_i_1_n_5\, + O(1) => \sig_byte_cntr_reg[3]_i_1_n_6\, + O(0) => \sig_byte_cntr_reg[3]_i_1_n_7\, + S(3) => \sig_byte_cntr[3]_i_3_n_0\, + S(2) => \sig_byte_cntr[3]_i_4_n_0\, + S(1) => \sig_byte_cntr[3]_i_5_n_0\, + S(0) => \sig_byte_cntr[3]_i_6_n_0\ ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized0\ is - port ( - \out\ : out STD_LOGIC; - \sig_user_skid_reg_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - dm2linebuf_mm2s_tvalid : out STD_LOGIC; - DI : out STD_LOGIC_VECTOR ( 3 downto 0 ); - Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); - dm2linebuf_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - hold_ff_q_reg : out STD_LOGIC; - sig_ok_to_post_rd_addr_reg : out STD_LOGIC; - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : out STD_LOGIC; - \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : out STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[0]\ : out STD_LOGIC; - S : out STD_LOGIC_VECTOR ( 3 downto 0 ); - \count_reg[6]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - sig_stream_rst : in STD_LOGIC; - m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); - DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ); - lsig_0ffset_cntr : in STD_LOGIC; - lsig_cmd_loaded : in STD_LOGIC; - hold_ff_q : in STD_LOGIC; - \sig_token_cntr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); - p_8_out : in STD_LOGIC; - sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; - sig_posted_to_axi_2_reg : in STD_LOGIC; - sig_posted_to_axi_2_reg_0 : in STD_LOGIC; - p_0_out : in STD_LOGIC_VECTOR ( 0 to 0 ); - \INFERRED_GEN.cnt_i_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - \fifo_wren__0\ : in STD_LOGIC; - \mm2s_strm_wvalid0__1\ : in STD_LOGIC; - m_axi_mm2s_rvalid : in STD_LOGIC; - \sig_advance_pipe9_out__1\ : in STD_LOGIC; - D : in STD_LOGIC_VECTOR ( 5 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized0\ : entity is "fifo_generator_v13_1_3_synth"; -end \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized0\; - -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized0\ is -begin -\gconvfifo.rf\: entity work.\Arty_Z7_20_axi_vdma_0_0_fifo_generator_top__parameterized0\ - port map ( - D(5 downto 0) => D(5 downto 0), - DI(3 downto 0) => DI(3 downto 0), - DIBDI(1 downto 0) => DIBDI(1 downto 0), - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, - \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, - \INFERRED_GEN.cnt_i_reg[0]\ => \INFERRED_GEN.cnt_i_reg[0]\, - \INFERRED_GEN.cnt_i_reg[2]\(0) => \INFERRED_GEN.cnt_i_reg[2]\(0), - Q(1 downto 0) => Q(1 downto 0), - S(3 downto 0) => S(3 downto 0), - \count_reg[6]\(1 downto 0) => \count_reg[6]\(1 downto 0), - dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), - dm2linebuf_mm2s_tvalid => dm2linebuf_mm2s_tvalid, - \fifo_wren__0\ => \fifo_wren__0\, - hold_ff_q => hold_ff_q, - hold_ff_q_reg => hold_ff_q_reg, - lsig_0ffset_cntr => lsig_0ffset_cntr, - lsig_cmd_loaded => lsig_cmd_loaded, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axi_mm2s_rdata(63 downto 0) => m_axi_mm2s_rdata(63 downto 0), - m_axi_mm2s_rvalid => m_axi_mm2s_rvalid, - \mm2s_strm_wvalid0__1\ => \mm2s_strm_wvalid0__1\, - \out\ => \out\, - p_0_out(0) => p_0_out(0), - p_8_out => p_8_out, - \sig_advance_pipe9_out__1\ => \sig_advance_pipe9_out__1\, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_ok_to_post_rd_addr_reg => sig_ok_to_post_rd_addr_reg, - sig_posted_to_axi_2_reg => sig_posted_to_axi_2_reg, - sig_posted_to_axi_2_reg_0 => sig_posted_to_axi_2_reg_0, - sig_stream_rst => sig_stream_rst, - \sig_token_cntr_reg[3]\(3 downto 0) => \sig_token_cntr_reg[3]\(3 downto 0), - \sig_user_skid_reg_reg[0]\(0) => \sig_user_skid_reg_reg[0]\(0) +\sig_byte_cntr_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \INFERRED_GEN.cnt_i_reg[4]\(0), + D => \sig_byte_cntr_reg[7]_i_2_n_7\, + Q => \^di\(4), + R => SR(0) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized0\ is - port ( - \out\ : out STD_LOGIC; - \sig_user_skid_reg_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - dm2linebuf_mm2s_tvalid : out STD_LOGIC; - DI : out STD_LOGIC_VECTOR ( 3 downto 0 ); - Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); - dm2linebuf_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - hold_ff_q_reg : out STD_LOGIC; - sig_ok_to_post_rd_addr_reg : out STD_LOGIC; - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : out STD_LOGIC; - \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : out STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[0]\ : out STD_LOGIC; - S : out STD_LOGIC_VECTOR ( 3 downto 0 ); - \count_reg[6]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - sig_stream_rst : in STD_LOGIC; - m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); - DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ); - lsig_0ffset_cntr : in STD_LOGIC; - lsig_cmd_loaded : in STD_LOGIC; - hold_ff_q : in STD_LOGIC; - \sig_token_cntr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); - p_8_out : in STD_LOGIC; - sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; - sig_posted_to_axi_2_reg : in STD_LOGIC; - sig_posted_to_axi_2_reg_0 : in STD_LOGIC; - p_0_out : in STD_LOGIC_VECTOR ( 0 to 0 ); - \INFERRED_GEN.cnt_i_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - \fifo_wren__0\ : in STD_LOGIC; - \mm2s_strm_wvalid0__1\ : in STD_LOGIC; - m_axi_mm2s_rvalid : in STD_LOGIC; - \sig_advance_pipe9_out__1\ : in STD_LOGIC; - D : in STD_LOGIC_VECTOR ( 5 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized0\ : entity is "fifo_generator_v13_1_3"; -end \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized0\; - -architecture STRUCTURE of \Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized0\ is -begin -inst_fifo_gen: entity work.\Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3_synth__parameterized0\ - port map ( - D(5 downto 0) => D(5 downto 0), - DI(3 downto 0) => DI(3 downto 0), - DIBDI(1 downto 0) => DIBDI(1 downto 0), - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, - \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, - \INFERRED_GEN.cnt_i_reg[0]\ => \INFERRED_GEN.cnt_i_reg[0]\, - \INFERRED_GEN.cnt_i_reg[2]\(0) => \INFERRED_GEN.cnt_i_reg[2]\(0), - Q(1 downto 0) => Q(1 downto 0), - S(3 downto 0) => S(3 downto 0), - \count_reg[6]\(1 downto 0) => \count_reg[6]\(1 downto 0), - dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), - dm2linebuf_mm2s_tvalid => dm2linebuf_mm2s_tvalid, - \fifo_wren__0\ => \fifo_wren__0\, - hold_ff_q => hold_ff_q, - hold_ff_q_reg => hold_ff_q_reg, - lsig_0ffset_cntr => lsig_0ffset_cntr, - lsig_cmd_loaded => lsig_cmd_loaded, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axi_mm2s_rdata(63 downto 0) => m_axi_mm2s_rdata(63 downto 0), - m_axi_mm2s_rvalid => m_axi_mm2s_rvalid, - \mm2s_strm_wvalid0__1\ => \mm2s_strm_wvalid0__1\, - \out\ => \out\, - p_0_out(0) => p_0_out(0), - p_8_out => p_8_out, - \sig_advance_pipe9_out__1\ => \sig_advance_pipe9_out__1\, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_ok_to_post_rd_addr_reg => sig_ok_to_post_rd_addr_reg, - sig_posted_to_axi_2_reg => sig_posted_to_axi_2_reg, - sig_posted_to_axi_2_reg_0 => sig_posted_to_axi_2_reg_0, - sig_stream_rst => sig_stream_rst, - \sig_token_cntr_reg[3]\(3 downto 0) => \sig_token_cntr_reg[3]\(3 downto 0), - \sig_user_skid_reg_reg[0]\(0) => \sig_user_skid_reg_reg[0]\(0) +\sig_byte_cntr_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \INFERRED_GEN.cnt_i_reg[4]\(0), + D => \sig_byte_cntr_reg[7]_i_2_n_6\, + Q => \^di\(5), + R => SR(0) + ); +\sig_byte_cntr_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \INFERRED_GEN.cnt_i_reg[4]\(0), + D => \sig_byte_cntr_reg[7]_i_2_n_5\, + Q => \^di\(6), + R => SR(0) ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_sync_fifo_fg is - port ( - \out\ : out STD_LOGIC; - \sig_user_skid_reg_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - dm2linebuf_mm2s_tvalid : out STD_LOGIC; - DI : out STD_LOGIC_VECTOR ( 3 downto 0 ); - Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); - dm2linebuf_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - hold_ff_q_reg : out STD_LOGIC; - sig_ok_to_post_rd_addr_reg : out STD_LOGIC; - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : out STD_LOGIC; - \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : out STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[0]\ : out STD_LOGIC; - S : out STD_LOGIC_VECTOR ( 3 downto 0 ); - \count_reg[6]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - sig_stream_rst : in STD_LOGIC; - m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); - DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ); - lsig_0ffset_cntr : in STD_LOGIC; - lsig_cmd_loaded : in STD_LOGIC; - hold_ff_q : in STD_LOGIC; - \sig_token_cntr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); - p_8_out : in STD_LOGIC; - sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; - sig_posted_to_axi_2_reg : in STD_LOGIC; - sig_posted_to_axi_2_reg_0 : in STD_LOGIC; - p_0_out : in STD_LOGIC_VECTOR ( 0 to 0 ); - \INFERRED_GEN.cnt_i_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - \fifo_wren__0\ : in STD_LOGIC; - \mm2s_strm_wvalid0__1\ : in STD_LOGIC; - m_axi_mm2s_rvalid : in STD_LOGIC; - \sig_advance_pipe9_out__1\ : in STD_LOGIC; - D : in STD_LOGIC_VECTOR ( 5 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_sync_fifo_fg : entity is "sync_fifo_fg"; -end Arty_Z7_20_axi_vdma_0_0_sync_fifo_fg; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_sync_fifo_fg is -begin -\FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM\: entity work.\Arty_Z7_20_axi_vdma_0_0_fifo_generator_v13_1_3__parameterized0\ +\sig_byte_cntr_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \INFERRED_GEN.cnt_i_reg[4]\(0), + D => \sig_byte_cntr_reg[7]_i_2_n_4\, + Q => \^di\(7), + R => SR(0) + ); +\sig_byte_cntr_reg[7]_i_2\: unisim.vcomponents.CARRY4 port map ( - D(5 downto 0) => D(5 downto 0), - DI(3 downto 0) => DI(3 downto 0), - DIBDI(1 downto 0) => DIBDI(1 downto 0), - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, - \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, - \INFERRED_GEN.cnt_i_reg[0]\ => \INFERRED_GEN.cnt_i_reg[0]\, - \INFERRED_GEN.cnt_i_reg[2]\(0) => \INFERRED_GEN.cnt_i_reg[2]\(0), - Q(1 downto 0) => Q(1 downto 0), - S(3 downto 0) => S(3 downto 0), - \count_reg[6]\(1 downto 0) => \count_reg[6]\(1 downto 0), - dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), - dm2linebuf_mm2s_tvalid => dm2linebuf_mm2s_tvalid, - \fifo_wren__0\ => \fifo_wren__0\, - hold_ff_q => hold_ff_q, - hold_ff_q_reg => hold_ff_q_reg, - lsig_0ffset_cntr => lsig_0ffset_cntr, - lsig_cmd_loaded => lsig_cmd_loaded, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axi_mm2s_rdata(63 downto 0) => m_axi_mm2s_rdata(63 downto 0), - m_axi_mm2s_rvalid => m_axi_mm2s_rvalid, - \mm2s_strm_wvalid0__1\ => \mm2s_strm_wvalid0__1\, - \out\ => \out\, - p_0_out(0) => p_0_out(0), - p_8_out => p_8_out, - \sig_advance_pipe9_out__1\ => \sig_advance_pipe9_out__1\, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_ok_to_post_rd_addr_reg => sig_ok_to_post_rd_addr_reg, - sig_posted_to_axi_2_reg => sig_posted_to_axi_2_reg, - sig_posted_to_axi_2_reg_0 => sig_posted_to_axi_2_reg_0, - sig_stream_rst => sig_stream_rst, - \sig_token_cntr_reg[3]\(3 downto 0) => \sig_token_cntr_reg[3]\(3 downto 0), - \sig_user_skid_reg_reg[0]\(0) => \sig_user_skid_reg_reg[0]\(0) + CI => \sig_byte_cntr_reg[3]_i_1_n_0\, + CO(3) => \sig_byte_cntr_reg[7]_i_2_n_0\, + CO(2) => \sig_byte_cntr_reg[7]_i_2_n_1\, + CO(1) => \sig_byte_cntr_reg[7]_i_2_n_2\, + CO(0) => \sig_byte_cntr_reg[7]_i_2_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \sig_byte_cntr_reg[7]_i_2_n_4\, + O(2) => \sig_byte_cntr_reg[7]_i_2_n_5\, + O(1) => \sig_byte_cntr_reg[7]_i_2_n_6\, + O(0) => \sig_byte_cntr_reg[7]_i_2_n_7\, + S(3) => \sig_byte_cntr[7]_i_3_n_0\, + S(2) => \sig_byte_cntr[7]_i_4_n_0\, + S(1) => \sig_byte_cntr[7]_i_5_n_0\, + S(0) => \sig_byte_cntr[7]_i_6_n_0\ ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_sfifo_autord is - port ( - \out\ : out STD_LOGIC; - \sig_user_skid_reg_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - dm2linebuf_mm2s_tvalid : out STD_LOGIC; - DI : out STD_LOGIC_VECTOR ( 3 downto 0 ); - Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); - dm2linebuf_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - sig_ok_to_post_rd_addr_reg : out STD_LOGIC; - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : out STD_LOGIC; - \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ : out STD_LOGIC; - \INFERRED_GEN.cnt_i_reg[0]\ : out STD_LOGIC; - S : out STD_LOGIC_VECTOR ( 3 downto 0 ); - \count_reg[6]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); - m_axi_mm2s_aclk : in STD_LOGIC; - sig_stream_rst : in STD_LOGIC; - m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); - DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ); - lsig_0ffset_cntr : in STD_LOGIC; - lsig_cmd_loaded : in STD_LOGIC; - \sig_token_cntr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); - p_8_out : in STD_LOGIC; - sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; - sig_posted_to_axi_2_reg : in STD_LOGIC; - sig_posted_to_axi_2_reg_0 : in STD_LOGIC; - p_0_out : in STD_LOGIC_VECTOR ( 0 to 0 ); - \INFERRED_GEN.cnt_i_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - \fifo_wren__0\ : in STD_LOGIC; - \mm2s_strm_wvalid0__1\ : in STD_LOGIC; - m_axi_mm2s_rvalid : in STD_LOGIC; - \sig_advance_pipe9_out__1\ : in STD_LOGIC; - D : in STD_LOGIC_VECTOR ( 5 downto 0 ) - ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_sfifo_autord : entity is "axi_datamover_sfifo_autord"; -end Arty_Z7_20_axi_vdma_0_0_axi_datamover_sfifo_autord; - -architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_sfifo_autord is - signal \BLK_MEM.I_SYNC_FIFOGEN_FIFO_n_41\ : STD_LOGIC; - signal hold_ff_q : STD_LOGIC; -begin -\BLK_MEM.I_SYNC_FIFOGEN_FIFO\: entity work.Arty_Z7_20_axi_vdma_0_0_sync_fifo_fg +\sig_byte_cntr_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => \INFERRED_GEN.cnt_i_reg[4]\(0), + D => \sig_byte_cntr_reg[8]_i_3_n_7\, + Q => \^di\(8), + R => SR(1) + ); +\sig_byte_cntr_reg[8]_i_3\: unisim.vcomponents.CARRY4 port map ( - D(5 downto 0) => D(5 downto 0), - DI(3 downto 0) => DI(3 downto 0), - DIBDI(1 downto 0) => DIBDI(1 downto 0), - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, - \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\, - \INFERRED_GEN.cnt_i_reg[0]\ => \INFERRED_GEN.cnt_i_reg[0]\, - \INFERRED_GEN.cnt_i_reg[2]\(0) => \INFERRED_GEN.cnt_i_reg[2]\(0), - Q(1 downto 0) => Q(1 downto 0), - S(3 downto 0) => S(3 downto 0), - \count_reg[6]\(1 downto 0) => \count_reg[6]\(1 downto 0), - dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), - dm2linebuf_mm2s_tvalid => dm2linebuf_mm2s_tvalid, - \fifo_wren__0\ => \fifo_wren__0\, - hold_ff_q => hold_ff_q, - hold_ff_q_reg => \BLK_MEM.I_SYNC_FIFOGEN_FIFO_n_41\, - lsig_0ffset_cntr => lsig_0ffset_cntr, - lsig_cmd_loaded => lsig_cmd_loaded, - m_axi_mm2s_aclk => m_axi_mm2s_aclk, - m_axi_mm2s_rdata(63 downto 0) => m_axi_mm2s_rdata(63 downto 0), - m_axi_mm2s_rvalid => m_axi_mm2s_rvalid, - \mm2s_strm_wvalid0__1\ => \mm2s_strm_wvalid0__1\, - \out\ => \out\, - p_0_out(0) => p_0_out(0), - p_8_out => p_8_out, - \sig_advance_pipe9_out__1\ => \sig_advance_pipe9_out__1\, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_ok_to_post_rd_addr_reg => sig_ok_to_post_rd_addr_reg, - sig_posted_to_axi_2_reg => sig_posted_to_axi_2_reg, - sig_posted_to_axi_2_reg_0 => sig_posted_to_axi_2_reg_0, - sig_stream_rst => sig_stream_rst, - \sig_token_cntr_reg[3]\(3 downto 0) => \sig_token_cntr_reg[3]\(3 downto 0), - \sig_user_skid_reg_reg[0]\(0) => \sig_user_skid_reg_reg[0]\(0) + CI => \sig_byte_cntr_reg[7]_i_2_n_0\, + CO(3 downto 0) => \NLW_sig_byte_cntr_reg[8]_i_3_CO_UNCONNECTED\(3 downto 0), + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 1) => \NLW_sig_byte_cntr_reg[8]_i_3_O_UNCONNECTED\(3 downto 1), + O(0) => \sig_byte_cntr_reg[8]_i_3_n_7\, + S(3 downto 1) => B"000", + S(0) => \sig_byte_cntr[8]_i_4_n_0\ ); -hold_ff_q_reg: unisim.vcomponents.FDRE +sig_clr_dbc_reg_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"E000" + ) + port map ( + I0 => \sig_dbc_max__3\, + I1 => sig_dre2ibtt_tlast, + I2 => \INFERRED_GEN.cnt_i_reg[4]\(0), + I3 => \lsig_set_packer_full__1\, + O => sig_clr_dbeat_cntr0_out + ); +sig_clr_dbc_reg_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \sig_burst_dbeat_cntr_reg__0\(3), + I1 => \sig_burst_dbeat_cntr_reg__0\(1), + I2 => \sig_burst_dbeat_cntr_reg__0\(0), + I3 => \sig_burst_dbeat_cntr_reg__0\(4), + I4 => \sig_burst_dbeat_cntr_reg__0\(2), + O => \sig_dbc_max__3\ + ); +sig_clr_dbc_reg_i_3: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAAA8000" + ) + port map ( + I0 => \INFERRED_GEN.cnt_i_reg[4]\(0), + I1 => \lsig_0ffset_to_to_use__2\(1), + I2 => \lsig_0ffset_to_to_use__2\(0), + I3 => \lsig_0ffset_to_to_use__2\(2), + I4 => sig_dre2ibtt_tlast, + O => \lsig_set_packer_full__1\ + ); +sig_clr_dbc_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( - C => m_axi_mm2s_aclk, + C => m_axi_s2mm_aclk, CE => '1', - D => \BLK_MEM.I_SYNC_FIFOGEN_FIFO_n_41\, - Q => hold_ff_q, - R => '0' + D => sig_clr_dbeat_cntr0_out, + Q => \^sig_clr_dbc_reg\, + R => sig_stream_rst + ); +sig_dre2ibtt_eop_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_dre2ibtt_eop, + Q => \^di\(10), + R => sig_stream_rst + ); +sig_dre2ibtt_tlast_reg_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => m_axi_s2mm_aclk, + CE => '1', + D => sig_dre2ibtt_tlast, + Q => \^di\(9), + R => sig_stream_rst ); end STRUCTURE; library IEEE; @@ -36694,48 +91252,46 @@ use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_rd_sf is port ( \out\ : out STD_LOGIC; + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC; sig_wr_fifo : out STD_LOGIC; \INFERRED_GEN.cnt_i_reg[1]\ : out STD_LOGIC; - sig_init_done : out STD_LOGIC; - sig_inhibit_rdy_n : out STD_LOGIC; sig_sf_allow_addr_req : out STD_LOGIC; - \sig_user_skid_reg_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - dm2linebuf_mm2s_tvalid : out STD_LOGIC; - DI : out STD_LOGIC_VECTOR ( 3 downto 0 ); - Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ : out STD_LOGIC; + \gc1.count_reg[7]\ : out STD_LOGIC; + sig_inhibit_rdy_n : out STD_LOGIC; + DIN : out STD_LOGIC_VECTOR ( 0 to 0 ); + \sig_user_skid_reg_reg[0]\ : out STD_LOGIC; dm2linebuf_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - S : out STD_LOGIC_VECTOR ( 3 downto 0 ); - \count_reg[6]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_mm2s_aclk : in STD_LOGIC; - sig_stream_rst : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); DIBDI : in STD_LOGIC_VECTOR ( 1 downto 0 ); \in\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - sig_mmap_reset_reg_reg : in STD_LOGIC; - sig_mstr2sf_cmd_valid : in STD_LOGIC; - sig_last_mmap_dbeat_reg_reg : in STD_LOGIC; - sig_posted_to_axi_2_reg : in STD_LOGIC; - p_8_out : in STD_LOGIC; sig_cmd_stat_rst_user_reg_n_cdc_from_reg : in STD_LOGIC; - \fifo_wren__0\ : in STD_LOGIC; - \mm2s_strm_wvalid0__1\ : in STD_LOGIC; - m_axi_mm2s_rvalid : in STD_LOGIC; - \sig_advance_pipe9_out__1\ : in STD_LOGIC; - D : in STD_LOGIC_VECTOR ( 5 downto 0 ) + sig_posted_to_axi_2_reg : in STD_LOGIC; + prmry_resetn_i_reg : in STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1\ : in STD_LOGIC; + sig_last_mmap_dbeat_reg_reg : in STD_LOGIC; + sig_mstr2sf_cmd_valid : in STD_LOGIC; + ram_full_i_reg : in STD_LOGIC; + sig_init_reg2 : in STD_LOGIC; + sig_init_reg : in STD_LOGIC; + ram_full_i_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_rd_sf : entity is "axi_datamover_rd_sf"; end Arty_Z7_20_axi_vdma_0_0_axi_datamover_rd_sf; architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_rd_sf is - signal I_DATA_FIFO_n_41 : STD_LOGIC; - signal I_DATA_FIFO_n_42 : STD_LOGIC; - signal I_DATA_FIFO_n_43 : STD_LOGIC; - signal I_DATA_FIFO_n_44 : STD_LOGIC; - signal lsig_0ffset_cntr : STD_LOGIC; + signal \^include_unpacking.lsig_0ffset_cntr_reg[0]_0\ : STD_LOGIC; + signal I_DATA_FIFO_n_3 : STD_LOGIC; + signal I_DATA_FIFO_n_4 : STD_LOGIC; + signal I_DATA_FIFO_n_6 : STD_LOGIC; + signal \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO_n_2\ : STD_LOGIC; signal lsig_cmd_loaded : STD_LOGIC; - signal p_0_out : STD_LOGIC_VECTOR ( 7 to 7 ); - signal sig_ok_to_post_rd_addr_i_3_n_0 : STD_LOGIC; + signal sig_data_fifo_data_out : STD_LOGIC_VECTOR ( 65 to 65 ); + signal sig_ok_to_post_rd_addr_i_4_n_0 : STD_LOGIC; signal sig_rd_empty : STD_LOGIC; signal \sig_token_cntr[0]_i_1_n_0\ : STD_LOGIC; signal \sig_token_cntr[1]_i_1_n_0\ : STD_LOGIC; @@ -36744,9 +91300,10 @@ architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_rd_sf is signal \sig_token_cntr[3]_i_2_n_0\ : STD_LOGIC; signal \sig_token_cntr_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of sig_ok_to_post_rd_addr_i_3 : label is "soft_lutpair70"; - attribute SOFT_HLUTNM of \sig_token_cntr[0]_i_1\ : label is "soft_lutpair70"; + attribute SOFT_HLUTNM of sig_ok_to_post_rd_addr_i_4 : label is "soft_lutpair127"; + attribute SOFT_HLUTNM of \sig_token_cntr[0]_i_1\ : label is "soft_lutpair127"; begin + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ <= \^include_unpacking.lsig_0ffset_cntr_reg[0]_0\; \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' @@ -36754,9 +91311,9 @@ begin port map ( C => m_axi_mm2s_aclk, CE => '1', - D => I_DATA_FIFO_n_42, - Q => lsig_0ffset_cntr, - R => sig_stream_rst + D => \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO_n_2\, + Q => \^include_unpacking.lsig_0ffset_cntr_reg[0]_0\, + R => SR(0) ); \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\: unisim.vcomponents.FDRE generic map( @@ -36765,69 +91322,67 @@ begin port map ( C => m_axi_mm2s_aclk, CE => '1', - D => I_DATA_FIFO_n_43, + D => I_DATA_FIFO_n_4, Q => lsig_cmd_loaded, - R => sig_stream_rst + R => SR(0) ); I_DATA_FIFO: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover_sfifo_autord port map ( - D(5 downto 0) => D(5 downto 0), - DI(3 downto 0) => DI(3 downto 0), + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\, DIBDI(1 downto 0) => DIBDI(1 downto 0), - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => I_DATA_FIFO_n_42, - \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => I_DATA_FIFO_n_43, - \INFERRED_GEN.cnt_i_reg[0]\ => I_DATA_FIFO_n_44, - \INFERRED_GEN.cnt_i_reg[2]\(0) => sig_rd_empty, - Q(1 downto 0) => Q(1 downto 0), - S(3 downto 0) => S(3 downto 0), - \count_reg[6]\(1 downto 0) => \count_reg[6]\(1 downto 0), + DIN(0) => DIN(0), + DOBDO(0) => sig_data_fifo_data_out(65), + E(0) => E(0), + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1\, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ => \^include_unpacking.lsig_0ffset_cntr_reg[0]_0\, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => I_DATA_FIFO_n_4, + \INFERRED_GEN.cnt_i_reg[2]\ => I_DATA_FIFO_n_6, + Q(0) => sig_rd_empty, + SR(0) => SR(0), dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), - dm2linebuf_mm2s_tvalid => dm2linebuf_mm2s_tvalid, - \fifo_wren__0\ => \fifo_wren__0\, - lsig_0ffset_cntr => lsig_0ffset_cntr, + \gc1.count_reg[7]\(0) => \gc1.count_reg[7]\, lsig_cmd_loaded => lsig_cmd_loaded, m_axi_mm2s_aclk => m_axi_mm2s_aclk, m_axi_mm2s_rdata(63 downto 0) => m_axi_mm2s_rdata(63 downto 0), - m_axi_mm2s_rvalid => m_axi_mm2s_rvalid, - \mm2s_strm_wvalid0__1\ => \mm2s_strm_wvalid0__1\, \out\ => \out\, - p_0_out(0) => p_0_out(7), - p_8_out => p_8_out, - \sig_advance_pipe9_out__1\ => \sig_advance_pipe9_out__1\, + ram_full_i_reg => ram_full_i_reg, + ram_full_i_reg_0(0) => ram_full_i_reg_0(0), sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_ok_to_post_rd_addr_reg => I_DATA_FIFO_n_41, - sig_posted_to_axi_2_reg => sig_ok_to_post_rd_addr_i_3_n_0, - sig_posted_to_axi_2_reg_0 => sig_posted_to_axi_2_reg, - sig_stream_rst => sig_stream_rst, + sig_ok_to_post_rd_addr_reg => I_DATA_FIFO_n_3, + sig_posted_to_axi_2_reg => sig_posted_to_axi_2_reg, + \sig_token_cntr_reg[0]\ => sig_ok_to_post_rd_addr_i_4_n_0, \sig_token_cntr_reg[3]\(3 downto 0) => \sig_token_cntr_reg__0\(3 downto 0), - \sig_user_skid_reg_reg[0]\(0) => \sig_user_skid_reg_reg[0]\(0) + \sig_user_skid_reg_reg[0]\ => \sig_user_skid_reg_reg[0]\ ); \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO\: entity work.\Arty_Z7_20_axi_vdma_0_0_axi_datamover_fifo__parameterized3\ port map ( - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ => I_DATA_FIFO_n_44, + DOBDO(0) => sig_data_fifo_data_out(65), FIFO_Full_reg => sig_wr_fifo, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO_n_2\, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ => \^include_unpacking.lsig_0ffset_cntr_reg[0]_0\, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1\, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => I_DATA_FIFO_n_6, \INFERRED_GEN.cnt_i_reg[1]\ => \INFERRED_GEN.cnt_i_reg[1]\, \INFERRED_GEN.cnt_i_reg[1]_0\ => sig_inhibit_rdy_n, Q(0) => sig_rd_empty, + SR(0) => SR(0), \in\(0) => \in\(0), + lsig_cmd_loaded => lsig_cmd_loaded, m_axi_mm2s_aclk => m_axi_mm2s_aclk, - p_0_out(0) => p_0_out(7), - sig_init_done => sig_init_done, - sig_mmap_reset_reg_reg => sig_mmap_reset_reg_reg, - sig_mstr2sf_cmd_valid => sig_mstr2sf_cmd_valid, - sig_stream_rst => sig_stream_rst + prmry_resetn_i_reg => prmry_resetn_i_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_init_reg => sig_init_reg, + sig_init_reg2 => sig_init_reg2, + sig_mstr2sf_cmd_valid => sig_mstr2sf_cmd_valid ); -sig_ok_to_post_rd_addr_i_3: unisim.vcomponents.LUT5 +sig_ok_to_post_rd_addr_i_4: unisim.vcomponents.LUT2 generic map( - INIT => X"00000203" + INIT => X"1" ) port map ( - I0 => sig_posted_to_axi_2_reg, - I1 => \sig_token_cntr_reg__0\(3), - I2 => \sig_token_cntr_reg__0\(2), - I3 => \sig_token_cntr_reg__0\(0), - I4 => \sig_token_cntr_reg__0\(1), - O => sig_ok_to_post_rd_addr_i_3_n_0 + I0 => \sig_token_cntr_reg__0\(0), + I1 => \sig_token_cntr_reg__0\(1), + O => sig_ok_to_post_rd_addr_i_4_n_0 ); sig_ok_to_post_rd_addr_reg: unisim.vcomponents.FDRE generic map( @@ -36836,7 +91391,7 @@ sig_ok_to_post_rd_addr_reg: unisim.vcomponents.FDRE port map ( C => m_axi_mm2s_aclk, CE => '1', - D => I_DATA_FIFO_n_41, + D => I_DATA_FIFO_n_3, Q => sig_sf_allow_addr_req, R => '0' ); @@ -36850,54 +91405,54 @@ sig_ok_to_post_rd_addr_reg: unisim.vcomponents.FDRE ); \sig_token_cntr[1]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FF0000FD55AAAA5D" + INIT => X"AAFF55005500B8FF" ) port map ( - I0 => sig_last_mmap_dbeat_reg_reg, - I1 => \sig_token_cntr_reg__0\(3), - I2 => \sig_token_cntr_reg__0\(2), - I3 => \sig_token_cntr_reg__0\(0), + I0 => sig_posted_to_axi_2_reg, + I1 => \sig_token_cntr_reg__0\(2), + I2 => \sig_token_cntr_reg__0\(3), + I3 => sig_last_mmap_dbeat_reg_reg, I4 => \sig_token_cntr_reg__0\(1), - I5 => sig_posted_to_axi_2_reg, + I5 => \sig_token_cntr_reg__0\(0), O => \sig_token_cntr[1]_i_1_n_0\ ); \sig_token_cntr[2]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FF5F00A0F0FA0D0D" + INIT => X"99CCCCCCCCCC7433" ) port map ( - I0 => sig_last_mmap_dbeat_reg_reg, - I1 => \sig_token_cntr_reg__0\(3), - I2 => \sig_token_cntr_reg__0\(0), - I3 => sig_posted_to_axi_2_reg, - I4 => \sig_token_cntr_reg__0\(2), - I5 => \sig_token_cntr_reg__0\(1), + I0 => sig_posted_to_axi_2_reg, + I1 => \sig_token_cntr_reg__0\(2), + I2 => \sig_token_cntr_reg__0\(3), + I3 => sig_last_mmap_dbeat_reg_reg, + I4 => \sig_token_cntr_reg__0\(1), + I5 => \sig_token_cntr_reg__0\(0), O => \sig_token_cntr[2]_i_1_n_0\ ); \sig_token_cntr[3]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"55555576AAAAAA8A" + INIT => X"55565557AAAAAAA8" ) port map ( - I0 => sig_last_mmap_dbeat_reg_reg, + I0 => sig_posted_to_axi_2_reg, I1 => \sig_token_cntr_reg__0\(1), - I2 => \sig_token_cntr_reg__0\(3), + I2 => \sig_token_cntr_reg__0\(0), I3 => \sig_token_cntr_reg__0\(2), - I4 => \sig_token_cntr_reg__0\(0), - I5 => sig_posted_to_axi_2_reg, + I4 => \sig_token_cntr_reg__0\(3), + I5 => sig_last_mmap_dbeat_reg_reg, O => \sig_token_cntr[3]_i_1_n_0\ ); \sig_token_cntr[3]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"BFFF4000FFCC0003" + INIT => X"FF00EE017F80EE01" ) port map ( - I0 => sig_posted_to_axi_2_reg, - I1 => \sig_token_cntr_reg__0\(0), + I0 => \sig_token_cntr_reg__0\(0), + I1 => \sig_token_cntr_reg__0\(1), I2 => sig_last_mmap_dbeat_reg_reg, - I3 => \sig_token_cntr_reg__0\(1), - I4 => \sig_token_cntr_reg__0\(3), - I5 => \sig_token_cntr_reg__0\(2), + I3 => \sig_token_cntr_reg__0\(3), + I4 => \sig_token_cntr_reg__0\(2), + I5 => sig_posted_to_axi_2_reg, O => \sig_token_cntr[3]_i_2_n_0\ ); \sig_token_cntr_reg[0]\: unisim.vcomponents.FDRE @@ -36909,7 +91464,7 @@ sig_ok_to_post_rd_addr_reg: unisim.vcomponents.FDRE CE => \sig_token_cntr[3]_i_1_n_0\, D => \sig_token_cntr[0]_i_1_n_0\, Q => \sig_token_cntr_reg__0\(0), - R => sig_stream_rst + R => SR(0) ); \sig_token_cntr_reg[1]\: unisim.vcomponents.FDRE generic map( @@ -36920,7 +91475,7 @@ sig_ok_to_post_rd_addr_reg: unisim.vcomponents.FDRE CE => \sig_token_cntr[3]_i_1_n_0\, D => \sig_token_cntr[1]_i_1_n_0\, Q => \sig_token_cntr_reg__0\(1), - R => sig_stream_rst + R => SR(0) ); \sig_token_cntr_reg[2]\: unisim.vcomponents.FDRE generic map( @@ -36931,7 +91486,7 @@ sig_ok_to_post_rd_addr_reg: unisim.vcomponents.FDRE CE => \sig_token_cntr[3]_i_1_n_0\, D => \sig_token_cntr[2]_i_1_n_0\, Q => \sig_token_cntr_reg__0\(2), - R => sig_stream_rst + R => SR(0) ); \sig_token_cntr_reg[3]\: unisim.vcomponents.FDSE generic map( @@ -36942,7 +91497,7 @@ sig_ok_to_post_rd_addr_reg: unisim.vcomponents.FDRE CE => \sig_token_cntr[3]_i_1_n_0\, D => \sig_token_cntr[3]_i_2_n_0\, Q => \sig_token_cntr_reg__0\(3), - S => sig_stream_rst + S => SR(0) ); end STRUCTURE; library IEEE; @@ -36951,43 +91506,42 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_mm2s_full_wrap is port ( + sig_rst2all_stop_request : out STD_LOGIC; m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_mm2s_arvalid : out STD_LOGIC; - mm2s_halt_cmplt : out STD_LOGIC; - sig_rst2all_stop_request : out STD_LOGIC; - \sig_user_skid_reg_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - dm2linebuf_mm2s_tvalid : out STD_LOGIC; - DI : out STD_LOGIC_VECTOR ( 3 downto 0 ); - Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); - FIFO_Full_reg : out STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_mm2s_rready : out STD_LOGIC; - dm2linebuf_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - S : out STD_LOGIC_VECTOR ( 3 downto 0 ); - interr_i_reg : out STD_LOGIC; - slverr_i_reg : out STD_LOGIC; + datamover_idle_reg : out STD_LOGIC; + mm2s_halt_cmplt : out STD_LOGIC; decerr_i_reg : out STD_LOGIC; - \count_reg[6]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + Q : out STD_LOGIC_VECTOR ( 0 to 0 ); + slverr_i_reg : out STD_LOGIC; + interr_i_reg : out STD_LOGIC; m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); - m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 4 downto 0 ); m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_mm2s_rready : out STD_LOGIC; + DIN : out STD_LOGIC_VECTOR ( 0 to 0 ); + \sig_user_skid_reg_reg[0]\ : out STD_LOGIC; + dm2linebuf_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_mm2s_aclk : in STD_LOGIC; m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); \out\ : in STD_LOGIC; halt_i_reg : in STD_LOGIC; - p_55_out : in STD_LOGIC; - m_axi_mm2s_rlast : in STD_LOGIC; - m_axi_mm2s_rvalid : in STD_LOGIC; - m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + prmry_resetn_i_reg : in STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ : in STD_LOGIC; cmnd_wr : in STD_LOGIC; mm2s_halt : in STD_LOGIC; - p_57_out : in STD_LOGIC; - sts_tready_reg : in STD_LOGIC; - p_8_out : in STD_LOGIC; - \fifo_wren__0\ : in STD_LOGIC; + p_71_out : in STD_LOGIC_VECTOR ( 0 to 0 ); + datamover_idle : in STD_LOGIC; + m_axi_mm2s_rlast : in STD_LOGIC; m_axi_mm2s_arready : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 48 downto 0 ); - D : in STD_LOGIC_VECTOR ( 5 downto 0 ) + p_56_out : in STD_LOGIC; + p_58_out : in STD_LOGIC; + sts_tready_reg : in STD_LOGIC; + m_axi_mm2s_rvalid : in STD_LOGIC; + m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_mm2s_full_wrap : entity is "axi_datamover_mm2s_full_wrap"; @@ -36995,50 +91549,43 @@ end Arty_Z7_20_axi_vdma_0_0_axi_datamover_mm2s_full_wrap; architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_mm2s_full_wrap is signal \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/sig_wr_fifo\ : STD_LOGIC; - signal \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_init_done\ : STD_LOGIC; signal \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_wr_fifo\ : STD_LOGIC; - signal \GEN_INCLUDE_MM2S_SF.I_RD_SF_n_2\ : STD_LOGIC; + signal \GEN_INCLUDE_MM2S_SF.I_RD_SF_n_0\ : STD_LOGIC; + signal \GEN_INCLUDE_MM2S_SF.I_RD_SF_n_3\ : STD_LOGIC; + signal \GEN_INCLUDE_MM2S_SF.I_RD_SF_n_6\ : STD_LOGIC; signal \GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_inhibit_rdy_n\ : STD_LOGIC; - signal \GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_init_done\ : STD_LOGIC; signal I_ADDR_CNTL_n_0 : STD_LOGIC; - signal \I_CMD_FIFO/sig_init_done\ : STD_LOGIC; + signal I_ADDR_CNTL_n_6 : STD_LOGIC; signal \I_CMD_FIFO/sig_rd_empty\ : STD_LOGIC; signal I_CMD_STATUS_n_0 : STD_LOGIC; - signal I_CMD_STATUS_n_57 : STD_LOGIC; - signal I_CMD_STATUS_n_58 : STD_LOGIC; + signal I_CMD_STATUS_n_1 : STD_LOGIC; + signal I_CMD_STATUS_n_4 : STD_LOGIC; + signal \I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/cntr_en\ : STD_LOGIC; + signal \I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_17_out\ : STD_LOGIC; + signal I_MSTR_PCC_n_1 : STD_LOGIC; signal I_MSTR_PCC_n_3 : STD_LOGIC; signal I_MSTR_PCC_n_4 : STD_LOGIC; - signal I_MSTR_PCC_n_48 : STD_LOGIC; - signal I_MSTR_PCC_n_49 : STD_LOGIC; + signal I_MSTR_PCC_n_44 : STD_LOGIC; signal I_MSTR_PCC_n_5 : STD_LOGIC; - signal I_MSTR_PCC_n_50 : STD_LOGIC; - signal I_MSTR_PCC_n_51 : STD_LOGIC; - signal I_MSTR_PCC_n_52 : STD_LOGIC; signal I_MSTR_PCC_n_6 : STD_LOGIC; - signal I_RD_DATA_CNTL_n_0 : STD_LOGIC; - signal I_RD_DATA_CNTL_n_15 : STD_LOGIC; - signal I_RD_DATA_CNTL_n_5 : STD_LOGIC; - signal I_RESET_n_4 : STD_LOGIC; + signal I_MSTR_PCC_n_7 : STD_LOGIC; + signal I_RD_DATA_CNTL_n_1 : STD_LOGIC; + signal I_RD_DATA_CNTL_n_17 : STD_LOGIC; + signal I_RD_DATA_CNTL_n_9 : STD_LOGIC; signal \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_inhibit_rdy_n\ : STD_LOGIC; - signal \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_done\ : STD_LOGIC; signal \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg\ : STD_LOGIC; signal \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg2\ : STD_LOGIC; signal \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_wr_fifo\ : STD_LOGIC; - signal \^mm2s_halt_cmplt\ : STD_LOGIC; - signal \mm2s_strm_wvalid0__1\ : STD_LOGIC; signal sig_addr2data_addr_posted : STD_LOGIC; - signal sig_addr2rsc_calc_error : STD_LOGIC; - signal sig_addr_reg_empty : STD_LOGIC; - signal \sig_advance_pipe9_out__1\ : STD_LOGIC; + signal sig_addr_posted_cntr : STD_LOGIC_VECTOR ( 2 downto 0 ); signal sig_calc_error_pushed : STD_LOGIC; - signal sig_calc_error_reg : STD_LOGIC; signal sig_cmd2mstr_command : STD_LOGIC_VECTOR ( 63 downto 0 ); signal sig_cmd_stat_rst_user_reg_n_cdc_from_reg : STD_LOGIC; signal sig_data2addr_stop_req : STD_LOGIC; - signal sig_data2rsc_calc_err : STD_LOGIC; - signal sig_data2rsc_slverr : STD_LOGIC; + signal sig_data2rsc_decerr : STD_LOGIC; signal sig_data2sf_cmd_cmplt : STD_LOGIC; - signal sig_data_fifo_wr_cnt : STD_LOGIC_VECTOR ( 7 to 7 ); + signal sig_data_fifo_wr_cnt : STD_LOGIC_VECTOR ( 8 to 8 ); + signal sig_halt_reg_dly3 : STD_LOGIC; signal sig_input_reg_empty : STD_LOGIC; signal sig_mstr2addr_addr : STD_LOGIC_VECTOR ( 31 downto 3 ); signal sig_mstr2addr_burst : STD_LOGIC_VECTOR ( 0 to 0 ); @@ -37048,76 +91595,78 @@ architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_mm2s_full_wrap i signal sig_mstr2data_eof : STD_LOGIC; signal sig_mstr2data_sequential : STD_LOGIC; signal sig_mstr2sf_cmd_valid : STD_LOGIC; + signal sig_next_calc_error_reg : STD_LOGIC; signal sig_push_rd_sts_reg : STD_LOGIC; - signal sig_rd_sts_decerr_reg0 : STD_LOGIC; + signal sig_rd_sts_interr_reg0 : STD_LOGIC; signal sig_rd_sts_reg_full0 : STD_LOGIC; + signal sig_rd_sts_slverr_reg0 : STD_LOGIC; signal sig_rdc2sf_wlast : STD_LOGIC; signal sig_rsc2data_ready : STD_LOGIC; signal sig_rsc2stat_status : STD_LOGIC_VECTOR ( 6 downto 4 ); signal sig_rsc2stat_status_valid : STD_LOGIC; + signal \^sig_rst2all_stop_request\ : STD_LOGIC; signal sig_sf_allow_addr_req : STD_LOGIC; signal sig_sm_halt_reg : STD_LOGIC; signal sig_stream_rst : STD_LOGIC; signal sig_xfer_addr_reg : STD_LOGIC_VECTOR ( 2 downto 0 ); begin - mm2s_halt_cmplt <= \^mm2s_halt_cmplt\; + sig_rst2all_stop_request <= \^sig_rst2all_stop_request\; \GEN_INCLUDE_MM2S_SF.I_RD_SF\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover_rd_sf port map ( - D(5 downto 0) => D(5 downto 0), - DI(3 downto 0) => DI(3 downto 0), + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ => sig_data_fifo_wr_cnt(8), DIBDI(1) => sig_data2sf_cmd_cmplt, DIBDI(0) => sig_rdc2sf_wlast, - \INFERRED_GEN.cnt_i_reg[1]\ => \GEN_INCLUDE_MM2S_SF.I_RD_SF_n_2\, - Q(1 downto 0) => Q(1 downto 0), - S(3 downto 0) => S(3 downto 0), - \count_reg[6]\(1 downto 0) => \count_reg[6]\(1 downto 0), + DIN(0) => DIN(0), + E(0) => \I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_17_out\, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_1\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\, + \INFERRED_GEN.cnt_i_reg[1]\ => \GEN_INCLUDE_MM2S_SF.I_RD_SF_n_3\, + SR(0) => sig_stream_rst, dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), - dm2linebuf_mm2s_tvalid => dm2linebuf_mm2s_tvalid, - \fifo_wren__0\ => \fifo_wren__0\, + \gc1.count_reg[7]\ => \GEN_INCLUDE_MM2S_SF.I_RD_SF_n_6\, \in\(0) => sig_xfer_addr_reg(2), m_axi_mm2s_aclk => m_axi_mm2s_aclk, m_axi_mm2s_rdata(63 downto 0) => m_axi_mm2s_rdata(63 downto 0), - m_axi_mm2s_rvalid => m_axi_mm2s_rvalid, - \mm2s_strm_wvalid0__1\ => \mm2s_strm_wvalid0__1\, - \out\ => sig_data_fifo_wr_cnt(7), - p_8_out => p_8_out, - \sig_advance_pipe9_out__1\ => \sig_advance_pipe9_out__1\, + \out\ => \GEN_INCLUDE_MM2S_SF.I_RD_SF_n_0\, + prmry_resetn_i_reg => prmry_resetn_i_reg, + ram_full_i_reg => I_RD_DATA_CNTL_n_17, + ram_full_i_reg_0(0) => \I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/cntr_en\, sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, sig_inhibit_rdy_n => \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_inhibit_rdy_n\, - sig_init_done => \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_done\, - sig_last_mmap_dbeat_reg_reg => I_RD_DATA_CNTL_n_0, - sig_mmap_reset_reg_reg => I_MSTR_PCC_n_51, + sig_init_reg => \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg\, + sig_init_reg2 => \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg2\, + sig_last_mmap_dbeat_reg_reg => I_RD_DATA_CNTL_n_1, sig_mstr2sf_cmd_valid => sig_mstr2sf_cmd_valid, sig_posted_to_axi_2_reg => I_ADDR_CNTL_n_0, sig_sf_allow_addr_req => sig_sf_allow_addr_req, - sig_stream_rst => sig_stream_rst, - \sig_user_skid_reg_reg[0]\(0) => \sig_user_skid_reg_reg[0]\(0), + \sig_user_skid_reg_reg[0]\ => \sig_user_skid_reg_reg[0]\, sig_wr_fifo => \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_wr_fifo\ ); I_ADDR_CNTL: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl port map ( SR(0) => sig_stream_rst, - \in\(37) => sig_calc_error_reg, - \in\(36) => sig_mstr2addr_burst(0), - \in\(35) => I_MSTR_PCC_n_3, - \in\(34) => I_MSTR_PCC_n_4, - \in\(33) => I_MSTR_PCC_n_5, - \in\(32) => I_MSTR_PCC_n_6, + \in\(38) => I_MSTR_PCC_n_1, + \in\(37) => sig_mstr2addr_burst(0), + \in\(36) => I_MSTR_PCC_n_3, + \in\(35) => I_MSTR_PCC_n_4, + \in\(34) => I_MSTR_PCC_n_5, + \in\(33) => I_MSTR_PCC_n_6, + \in\(32) => I_MSTR_PCC_n_7, \in\(31 downto 3) => sig_mstr2addr_addr(31 downto 3), \in\(2 downto 0) => sig_xfer_addr_reg(2 downto 0), m_axi_mm2s_aclk => m_axi_mm2s_aclk, m_axi_mm2s_araddr(31 downto 0) => m_axi_mm2s_araddr(31 downto 0), m_axi_mm2s_arburst(0) => m_axi_mm2s_arburst(0), - m_axi_mm2s_arlen(3 downto 0) => m_axi_mm2s_arlen(3 downto 0), + m_axi_mm2s_arlen(4 downto 0) => m_axi_mm2s_arlen(4 downto 0), m_axi_mm2s_arready => m_axi_mm2s_arready, m_axi_mm2s_arsize(1 downto 0) => m_axi_mm2s_arsize(1 downto 0), m_axi_mm2s_arvalid => m_axi_mm2s_arvalid, \out\ => I_ADDR_CNTL_n_0, - sig_addr2rsc_calc_error => sig_addr2rsc_calc_error, \sig_addr_posted_cntr_reg[2]\ => sig_addr2data_addr_posted, - sig_addr_reg_empty => sig_addr_reg_empty, sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, sig_data2addr_stop_req => sig_data2addr_stop_req, + sig_halt_cmplt_reg => I_ADDR_CNTL_n_6, + sig_halt_reg_dly3 => sig_halt_reg_dly3, sig_init_reg => \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg\, sig_init_reg2 => \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg2\, sig_mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid, @@ -37127,13 +91676,13 @@ I_ADDR_CNTL: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl I_CMD_STATUS: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover_cmd_status port map ( E(0) => E(0), - FIFO_Full_reg(0) => FIFO_Full_reg(0), + FIFO_Full_reg(0) => Q(0), \INFERRED_GEN.cnt_i_reg[1]\ => I_CMD_STATUS_n_0, Q(0) => \I_CMD_FIFO/sig_rd_empty\, SR(0) => sig_stream_rst, cmnd_wr => cmnd_wr, decerr_i_reg => decerr_i_reg, - \in\(0) => sig_calc_error_reg, + \in\(0) => I_MSTR_PCC_n_1, interr_i_reg => interr_i_reg, m_axi_mm2s_aclk => m_axi_mm2s_aclk, mm2s_halt => mm2s_halt, @@ -37141,20 +91690,18 @@ I_CMD_STATUS: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover_cmd_status \out\(17) => sig_cmd2mstr_command(30), \out\(16) => sig_cmd2mstr_command(23), \out\(15 downto 0) => sig_cmd2mstr_command(15 downto 0), - p_55_out => p_55_out, - p_57_out => p_57_out, + p_56_out => p_56_out, + p_58_out => p_58_out, \s_axis_cmd_tdata_reg[63]\(48 downto 0) => \in\(48 downto 0), sig_calc_error_pushed => sig_calc_error_pushed, - sig_calc_error_pushed_reg => I_MSTR_PCC_n_52, - sig_calc_error_reg_reg => I_CMD_STATUS_n_57, + sig_calc_error_pushed_reg => I_MSTR_PCC_n_44, + sig_calc_error_reg_reg => I_CMD_STATUS_n_1, sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, sig_inhibit_rdy_n => \GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_inhibit_rdy_n\, - sig_init_done => \I_CMD_FIFO/sig_init_done\, - sig_init_done_0 => \GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_init_done\, + sig_init_reg => \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg\, + sig_init_reg2 => \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg2\, sig_input_reg_empty => sig_input_reg_empty, - sig_mmap_reset_reg_reg => I_MSTR_PCC_n_48, - sig_mmap_reset_reg_reg_0 => I_MSTR_PCC_n_49, - sig_rd_sts_slverr_reg_reg => I_CMD_STATUS_n_58, + sig_rd_sts_slverr_reg_reg => I_CMD_STATUS_n_4, sig_rd_sts_slverr_reg_reg_0(2 downto 0) => sig_rsc2stat_status(6 downto 4), sig_rsc2stat_status_valid => sig_rsc2stat_status_valid, sig_sm_halt_reg => sig_sm_halt_reg, @@ -37163,17 +91710,17 @@ I_CMD_STATUS: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover_cmd_status ); I_MSTR_PCC: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover_pcc port map ( - FIFO_Full_reg => I_MSTR_PCC_n_52, - FIFO_Full_reg_0 => \GEN_INCLUDE_MM2S_SF.I_RD_SF_n_2\, - \INFERRED_GEN.cnt_i_reg[2]\ => I_CMD_STATUS_n_57, + FIFO_Full_reg => I_MSTR_PCC_n_44, + FIFO_Full_reg_0 => \GEN_INCLUDE_MM2S_SF.I_RD_SF_n_3\, Q(0) => \I_CMD_FIFO/sig_rd_empty\, SR(0) => sig_stream_rst, - \in\(37) => sig_calc_error_reg, - \in\(36) => sig_mstr2addr_burst(0), - \in\(35) => I_MSTR_PCC_n_3, - \in\(34) => I_MSTR_PCC_n_4, - \in\(33) => I_MSTR_PCC_n_5, - \in\(32) => I_MSTR_PCC_n_6, + \in\(38) => I_MSTR_PCC_n_1, + \in\(37) => sig_mstr2addr_burst(0), + \in\(36) => I_MSTR_PCC_n_3, + \in\(35) => I_MSTR_PCC_n_4, + \in\(34) => I_MSTR_PCC_n_5, + \in\(33) => I_MSTR_PCC_n_6, + \in\(32) => I_MSTR_PCC_n_7, \in\(31 downto 3) => sig_mstr2addr_addr(31 downto 3), \in\(2 downto 0) => sig_xfer_addr_reg(2 downto 0), m_axi_mm2s_aclk => m_axi_mm2s_aclk, @@ -37182,102 +91729,777 @@ I_MSTR_PCC: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover_pcc \out\(16) => sig_cmd2mstr_command(23), \out\(15 downto 0) => sig_cmd2mstr_command(15 downto 0), sig_calc_error_pushed => sig_calc_error_pushed, - sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_calc_error_reg_reg_0 => I_CMD_STATUS_n_1, sig_inhibit_rdy_n => \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_inhibit_rdy_n\, - sig_init_done => \I_CMD_FIFO/sig_init_done\, - sig_init_done_2 => \GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_init_done\, - sig_init_done_3 => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_init_done\, - sig_init_done_4 => \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_done\, - sig_init_done_reg => I_MSTR_PCC_n_48, - sig_init_done_reg_0 => I_MSTR_PCC_n_49, - sig_init_done_reg_1 => I_MSTR_PCC_n_50, - sig_init_done_reg_2 => I_MSTR_PCC_n_51, sig_init_reg => \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg\, - sig_init_reg2 => \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg2\, sig_input_reg_empty => sig_input_reg_empty, sig_mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid, sig_mstr2data_cmd_valid => sig_mstr2data_cmd_valid, + sig_mstr2data_sequential => sig_mstr2data_sequential, sig_mstr2sf_cmd_valid => sig_mstr2sf_cmd_valid, - sig_next_cmd_cmplt_reg_reg(2) => sig_mstr2data_cmd_cmplt, - sig_next_cmd_cmplt_reg_reg(1) => sig_mstr2data_sequential, + sig_next_cmd_cmplt_reg_reg(1) => sig_mstr2data_cmd_cmplt, sig_next_cmd_cmplt_reg_reg(0) => sig_mstr2data_eof, sig_sm_halt_reg => sig_sm_halt_reg, - sig_wr_fifo => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_wr_fifo\, - sig_wr_fifo_0 => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/sig_wr_fifo\, - sig_wr_fifo_1 => \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_wr_fifo\ + sig_wr_fifo => \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_wr_fifo\, + sig_wr_fifo_0 => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_wr_fifo\, + sig_wr_fifo_1 => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/sig_wr_fifo\ ); I_RD_DATA_CNTL: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover_rddata_cntl port map ( DIBDI(1) => sig_data2sf_cmd_cmplt, DIBDI(0) => sig_rdc2sf_wlast, + E(0) => \I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_17_out\, FIFO_Full_reg => I_CMD_STATUS_n_0, SR(0) => sig_stream_rst, - \in\(7) => sig_calc_error_reg, - \in\(6) => sig_mstr2data_cmd_cmplt, - \in\(5) => sig_mstr2data_sequential, - \in\(4) => sig_mstr2data_eof, - \in\(3) => I_MSTR_PCC_n_3, - \in\(2) => I_MSTR_PCC_n_4, - \in\(1) => I_MSTR_PCC_n_5, - \in\(0) => I_MSTR_PCC_n_6, + \count_reg[0]\(0) => \I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/cntr_en\, + \in\(8) => I_MSTR_PCC_n_1, + \in\(7) => sig_mstr2data_cmd_cmplt, + \in\(6) => sig_mstr2data_sequential, + \in\(5) => sig_mstr2data_eof, + \in\(4) => I_MSTR_PCC_n_3, + \in\(3) => I_MSTR_PCC_n_4, + \in\(2) => I_MSTR_PCC_n_5, + \in\(1) => I_MSTR_PCC_n_6, + \in\(0) => I_MSTR_PCC_n_7, m_axi_mm2s_aclk => m_axi_mm2s_aclk, m_axi_mm2s_rlast => m_axi_mm2s_rlast, m_axi_mm2s_rready => m_axi_mm2s_rready, m_axi_mm2s_rresp(1 downto 0) => m_axi_mm2s_rresp(1 downto 0), m_axi_mm2s_rvalid => m_axi_mm2s_rvalid, - mm2s_halt_cmplt => \^mm2s_halt_cmplt\, - \mm2s_strm_wvalid0__1\ => \mm2s_strm_wvalid0__1\, - \out\ => sig_data_fifo_wr_cnt(7), - sig_addr2rsc_calc_error => sig_addr2rsc_calc_error, - \sig_addr_posted_cntr_reg[2]_0\ => I_RD_DATA_CNTL_n_0, - sig_addr_reg_empty => sig_addr_reg_empty, - \sig_advance_pipe9_out__1\ => \sig_advance_pipe9_out__1\, + \out\ => \GEN_INCLUDE_MM2S_SF.I_RD_SF_n_0\, + ram_empty_fb_i_reg => \GEN_INCLUDE_MM2S_SF.I_RD_SF_n_6\, + ram_full_i_reg => I_RD_DATA_CNTL_n_17, + ram_full_i_reg_0 => sig_data_fifo_wr_cnt(8), + sig_addr_posted_cntr(2 downto 0) => sig_addr_posted_cntr(2 downto 0), + \sig_addr_posted_cntr_reg[2]_0\ => I_RD_DATA_CNTL_n_1, sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, sig_data2addr_stop_req => sig_data2addr_stop_req, - sig_data2rsc_calc_err => sig_data2rsc_calc_err, - sig_data2rsc_slverr => sig_data2rsc_slverr, - sig_halt_cmplt_reg => I_RD_DATA_CNTL_n_15, + sig_data2rsc_decerr => sig_data2rsc_decerr, + sig_halt_reg_dly3 => sig_halt_reg_dly3, sig_inhibit_rdy_n => \GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_inhibit_rdy_n\, - sig_init_done => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_init_done\, - sig_mmap_reset_reg_reg => I_MSTR_PCC_n_50, + sig_init_reg => \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg\, + sig_init_reg2 => \OMIT_DRE_CNTL.I_DRE_CNTL_FIFO/sig_init_reg2\, sig_mstr2data_cmd_valid => sig_mstr2data_cmd_valid, + sig_next_calc_error_reg => sig_next_calc_error_reg, sig_posted_to_axi_reg => sig_addr2data_addr_posted, sig_push_rd_sts_reg => sig_push_rd_sts_reg, - sig_rd_sts_decerr_reg0 => sig_rd_sts_decerr_reg0, - sig_rd_sts_decerr_reg_reg(0) => sig_rsc2stat_status(5), - sig_rd_sts_reg_empty_reg => I_RD_DATA_CNTL_n_5, + sig_rd_sts_interr_reg0 => sig_rd_sts_interr_reg0, + sig_rd_sts_reg_empty_reg => I_RD_DATA_CNTL_n_9, sig_rd_sts_reg_full0 => sig_rd_sts_reg_full0, + sig_rd_sts_slverr_reg0 => sig_rd_sts_slverr_reg0, + sig_rd_sts_slverr_reg_reg(1) => sig_rsc2stat_status(6), + sig_rd_sts_slverr_reg_reg(0) => sig_rsc2stat_status(4), sig_rsc2data_ready => sig_rsc2data_ready, sig_rsc2stat_status_valid => sig_rsc2stat_status_valid, - sig_s_h_halt_reg_reg => I_RESET_n_4, + sig_rst2all_stop_request => \^sig_rst2all_stop_request\, sig_wr_fifo => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_wr_fifo\ ); I_RD_STATUS_CNTLR: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover_rd_status_cntl port map ( m_axi_mm2s_aclk => m_axi_mm2s_aclk, - sig_coelsc_reg_full_reg => I_RD_DATA_CNTL_n_5, - sig_data2rsc_calc_err => sig_data2rsc_calc_err, - sig_data2rsc_slverr => sig_data2rsc_slverr, - sig_inhibit_rdy_n_reg => I_CMD_STATUS_n_58, + sig_coelsc_reg_full_reg => I_RD_DATA_CNTL_n_9, + sig_data2rsc_decerr => sig_data2rsc_decerr, + sig_inhibit_rdy_n_reg => I_CMD_STATUS_n_4, sig_push_rd_sts_reg => sig_push_rd_sts_reg, - sig_rd_sts_decerr_reg0 => sig_rd_sts_decerr_reg0, + sig_rd_sts_interr_reg0 => sig_rd_sts_interr_reg0, sig_rd_sts_reg_full0 => sig_rd_sts_reg_full0, + sig_rd_sts_slverr_reg0 => sig_rd_sts_slverr_reg0, sig_rd_sts_slverr_reg_reg_0(2 downto 0) => sig_rsc2stat_status(6 downto 4), sig_rsc2data_ready => sig_rsc2data_ready, sig_rsc2stat_status_valid => sig_rsc2stat_status_valid ); -I_RESET: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover_reset +I_RESET: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover_reset_20 port map ( SR(0) => sig_stream_rst, + datamover_idle => datamover_idle, + datamover_idle_reg => datamover_idle_reg, halt_i_reg => halt_i_reg, m_axi_mm2s_aclk => m_axi_mm2s_aclk, - mm2s_halt_cmplt => \^mm2s_halt_cmplt\, + mm2s_halt => mm2s_halt, + mm2s_halt_cmplt => mm2s_halt_cmplt, \out\ => \out\, + p_71_out(0) => p_71_out(0), + sig_addr_posted_cntr(2 downto 0) => sig_addr_posted_cntr(2 downto 0), + sig_calc_error_reg_reg => I_ADDR_CNTL_n_6, sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, - sig_data2addr_stop_req => sig_data2addr_stop_req, - sig_halt_reg_reg => I_RESET_n_4, - sig_halt_reg_reg_0 => I_RD_DATA_CNTL_n_15, - sig_rst2all_stop_request => sig_rst2all_stop_request + sig_next_calc_error_reg => sig_next_calc_error_reg, + sig_rst2all_stop_request => \^sig_rst2all_stop_request\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axi_vdma_0_0_axi_datamover_s2mm_full_wrap is + port ( + m_axi_s2mm_awburst : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_s2mm_awvalid : out STD_LOGIC; + m_axi_s2mm_wvalid : out STD_LOGIC; + \sig_data_skid_reg_reg[7]\ : out STD_LOGIC; + DI : out STD_LOGIC_VECTOR ( 10 downto 0 ); + sig_rst2all_stop_request_0 : out STD_LOGIC; + m_axi_s2mm_wlast : out STD_LOGIC; + RD_EN : out STD_LOGIC; + p_9_out : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axis_cmd_tvalid_reg : out STD_LOGIC_VECTOR ( 0 to 0 ); + CO : out STD_LOGIC_VECTOR ( 0 to 0 ); + datamover_idle_reg : out STD_LOGIC; + s2mm_halt_cmplt : out STD_LOGIC; + decerr_i_reg : out STD_LOGIC; + slverr_i_reg : out STD_LOGIC; + interr_i_reg : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_STS_GRTR_THAN_8.ovrflo_err_reg\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_s2mm_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_s2mm_awlen : out STD_LOGIC_VECTOR ( 5 downto 0 ); + m_axi_s2mm_awsize : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_s2mm_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + \gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \gpr1.dout_i_reg[1]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_s2mm_bready : out STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + s_soft_reset_i_reg : in STD_LOGIC; + halt_i_reg : in STD_LOGIC; + DOUT : in STD_LOGIC_VECTOR ( 8 downto 0 ); + EMPTY : in STD_LOGIC; + s2mm_halt : in STD_LOGIC; + s2mm_soft_reset : in STD_LOGIC; + dma_err : in STD_LOGIC; + cmnd_wr_1 : in STD_LOGIC; + \hsize_vid_reg[15]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + \hsize_vid_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + S : in STD_LOGIC_VECTOR ( 0 to 0 ); + s2mm_dmacr : in STD_LOGIC_VECTOR ( 0 to 0 ); + datamover_idle_2 : in STD_LOGIC; + m_axi_s2mm_awready : in STD_LOGIC; + m_axi_s2mm_wready : in STD_LOGIC; + \s_axis_cmd_tdata_reg[63]\ : in STD_LOGIC_VECTOR ( 48 downto 0 ); + m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + p_0_out : in STD_LOGIC_VECTOR ( 10 downto 0 ); + s_axis_s2mm_cmd_tvalid : in STD_LOGIC; + m_axi_s2mm_bvalid : in STD_LOGIC; + m_axis_s2mm_sts_tready : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover_s2mm_full_wrap : entity is "axi_datamover_s2mm_full_wrap"; +end Arty_Z7_20_axi_vdma_0_0_axi_datamover_s2mm_full_wrap; + +architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover_s2mm_full_wrap is + signal \ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/p_0_in2_in\ : STD_LOGIC; + signal \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/sig_inhibit_rdy_n\ : STD_LOGIC; + signal \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/sig_init_done\ : STD_LOGIC; + signal \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_inhibit_rdy_n\ : STD_LOGIC; + signal \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_init_done\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/sig_init_reg\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/sig_wr_fifo\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_117\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_118\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_129\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_130\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_131\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_132\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_133\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_134\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_135\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_136\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_137\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_15\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_18\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_19\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_20\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_39\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_41\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_42\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_43\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_44\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_45\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_46\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_47\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_48\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_49\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_50\ : STD_LOGIC; + signal \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_51\ : STD_LOGIC; + signal \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_87\ : STD_LOGIC; + signal \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_88\ : STD_LOGIC; + signal \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_89\ : STD_LOGIC; + signal \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_90\ : STD_LOGIC; + signal \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_91\ : STD_LOGIC; + signal \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_92\ : STD_LOGIC; + signal \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_93\ : STD_LOGIC; + signal \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_94\ : STD_LOGIC; + signal \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_1\ : STD_LOGIC; + signal \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_10\ : STD_LOGIC; + signal \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_11\ : STD_LOGIC; + signal \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_15\ : STD_LOGIC; + signal \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_17\ : STD_LOGIC; + signal \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_18\ : STD_LOGIC; + signal \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_19\ : STD_LOGIC; + signal \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_20\ : STD_LOGIC; + signal \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_21\ : STD_LOGIC; + signal \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_22\ : STD_LOGIC; + signal \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_23\ : STD_LOGIC; + signal \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_24\ : STD_LOGIC; + signal \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_25\ : STD_LOGIC; + signal \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_26\ : STD_LOGIC; + signal \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_27\ : STD_LOGIC; + signal \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_28\ : STD_LOGIC; + signal \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_29\ : STD_LOGIC; + signal \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_30\ : STD_LOGIC; + signal \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_31\ : STD_LOGIC; + signal \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_32\ : STD_LOGIC; + signal \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_33\ : STD_LOGIC; + signal \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_4\ : STD_LOGIC; + signal \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_9\ : STD_LOGIC; + signal \GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_init_done\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0\ : STD_LOGIC; + signal \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0\ : STD_LOGIC; + signal I_ADDR_CNTL_n_1 : STD_LOGIC; + signal \I_CMD_FIFO/sig_init_done\ : STD_LOGIC; + signal \I_CMD_FIFO/sig_rd_empty\ : STD_LOGIC; + signal I_CMD_STATUS_n_12 : STD_LOGIC; + signal I_CMD_STATUS_n_2 : STD_LOGIC; + signal I_CMD_STATUS_n_8 : STD_LOGIC; + signal \I_DRE_CNTL_FIFO/sig_inhibit_rdy_n\ : STD_LOGIC; + signal \I_DRE_CNTL_FIFO/sig_init_reg2\ : STD_LOGIC; + signal I_RESET_n_3 : STD_LOGIC; + signal I_RESET_n_6 : STD_LOGIC; + signal I_RESET_n_7 : STD_LOGIC; + signal I_WR_DATA_CNTL_n_0 : STD_LOGIC; + signal I_WR_DATA_CNTL_n_25 : STD_LOGIC; + signal I_WR_DATA_CNTL_n_4 : STD_LOGIC; + signal I_WR_STATUS_CNTLR_n_21 : STD_LOGIC; + signal I_WR_STATUS_CNTLR_n_27 : STD_LOGIC; + signal I_WR_STATUS_CNTLR_n_28 : STD_LOGIC; + signal I_WR_STATUS_CNTLR_n_29 : STD_LOGIC; + signal I_WR_STATUS_CNTLR_n_30 : STD_LOGIC; + signal lsig_0ffset_cntr : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal lsig_end_of_cmd_reg : STD_LOGIC; + signal lsig_eop_reg : STD_LOGIC; + signal p_0_in : STD_LOGIC; + signal p_0_out_1 : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal p_10_out : STD_LOGIC; + signal p_11_out : STD_LOGIC; + signal p_12_out : STD_LOGIC; + signal p_13_out : STD_LOGIC; + signal p_14_out : STD_LOGIC; + signal p_19_out : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal p_1_out : STD_LOGIC; + signal p_20_out : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal p_22_out : STD_LOGIC; + signal p_27_out : STD_LOGIC_VECTOR ( 0 to 0 ); + signal p_2_out : STD_LOGIC; + signal p_30_out : STD_LOGIC_VECTOR ( 31 downto 3 ); + signal p_32_out : STD_LOGIC; + signal p_3_out : STD_LOGIC; + signal p_5_out : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal p_9_out_0 : STD_LOGIC; + signal sig_addr2data_addr_posted : STD_LOGIC; + signal sig_addr2wsc_calc_error : STD_LOGIC; + signal sig_addr_reg_empty : STD_LOGIC; + signal sig_adjusted_addr_incr : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal sig_child_addr_cntr_lsh_reg : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal sig_child_qual_error_reg : STD_LOGIC; + signal sig_child_qual_first_of_2 : STD_LOGIC; + signal sig_child_tag_reg0 : STD_LOGIC; + signal \sig_clr_cmd2addr_valid3_out__0\ : STD_LOGIC; + signal \sig_clr_cmd2data_valid4_out__0\ : STD_LOGIC; + signal sig_clr_dbc_reg : STD_LOGIC; + signal sig_cmd2mstr_command : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal sig_cmd_stat_rst_user_reg_n_cdc_from_reg : STD_LOGIC; + signal sig_csm_pop_child_cmd : STD_LOGIC; + signal sig_csm_state_ns1 : STD_LOGIC; + signal sig_data2rst_stop_cmplt : STD_LOGIC; + signal sig_data2skid_wvalid : STD_LOGIC; + signal sig_data2wsc_bytes_rcvd : STD_LOGIC_VECTOR ( 15 downto 3 ); + signal sig_data2wsc_calc_err : STD_LOGIC; + signal sig_data2wsc_cmd_cmplt : STD_LOGIC; + signal sig_data2wsc_valid : STD_LOGIC; + signal \sig_dbeat_cntr_eq_0__2\ : STD_LOGIC; + signal sig_dqual_reg_full : STD_LOGIC; + signal sig_dre2ibtt_eop : STD_LOGIC; + signal sig_dre2ibtt_tdata : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal sig_dre2ibtt_tlast : STD_LOGIC; + signal sig_dre2ibtt_tstrb : STD_LOGIC; + signal \sig_good_strm_dbeat38_out__0\ : STD_LOGIC; + signal sig_halt_reg : STD_LOGIC; + signal sig_halt_reg_dly3 : STD_LOGIC; + signal sig_ibtt2dre_tready : STD_LOGIC; + signal sig_ibtt2wdc_stbs_asserted : STD_LOGIC_VECTOR ( 3 to 3 ); + signal sig_ibtt2wdc_tdata : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal sig_ibtt2wdc_tlast : STD_LOGIC; + signal sig_ibtt2wdc_tvalid : STD_LOGIC; + signal sig_input_cache_type_reg0 : STD_LOGIC; + signal sig_input_reg_empty : STD_LOGIC; + signal sig_psm_halt : STD_LOGIC; + signal sig_psm_pop_input_cmd : STD_LOGIC; + signal sig_set_push2wsc : STD_LOGIC; + signal sig_sf2pcc_cmd_cmplt : STD_LOGIC; + signal sig_sf2pcc_xfer_bytes : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal sig_sf2pcc_xfer_valid : STD_LOGIC; + signal sig_sf_strt_addr_offset : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal sig_skid2data_wready : STD_LOGIC; + signal sig_stream_rst : STD_LOGIC; + signal sig_wdc2ibtt_tready : STD_LOGIC; + signal sig_wdc_status_going_full : STD_LOGIC; + signal sig_wsc2rst_stop_cmplt : STD_LOGIC; + signal sig_wsc2stat_status : STD_LOGIC_VECTOR ( 31 downto 4 ); + signal sig_wsc2stat_status_valid : STD_LOGIC; + signal sig_xfer_cmd_cmplt_reg0 : STD_LOGIC; +begin +\GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover_indet_btt + port map ( + CO(0) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_133\, + D(2) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_18\, + D(1) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_19\, + D(0) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_20\, + DI(10 downto 0) => DI(10 downto 0), + E(0) => I_WR_DATA_CNTL_n_25, + \GEN_INDET_BTT.lsig_byte_cntr_reg[15]\(0) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_50\, + \GEN_INDET_BTT.lsig_byte_cntr_reg[3]\(64) => sig_ibtt2wdc_stbs_asserted(3), + \GEN_INDET_BTT.lsig_byte_cntr_reg[3]\(63 downto 0) => sig_ibtt2wdc_tdata(63 downto 0), + \GEN_INDET_BTT.lsig_byte_cntr_reg[6]\(0) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_51\, + \GEN_INDET_BTT.lsig_eop_reg_reg\ => sig_ibtt2wdc_tvalid, + \GEN_INDET_BTT.lsig_eop_reg_reg_0\ => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_117\, + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[0]\ => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_11\, + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[0]_0\ => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_15\, + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[0]_1\ => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_33\, + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(2 downto 0) => sig_sf_strt_addr_offset(2 downto 0), + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_0\ => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_15\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]_1\(1 downto 0) => lsig_0ffset_cntr(1 downto 0), + \INCLUDE_PACKING.lsig_first_dbeat_reg_0\ => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_4\, + \INFERRED_GEN.cnt_i_reg[4]\(0) => \sig_good_strm_dbeat38_out__0\, + O(3) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_129\, + O(2) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_130\, + O(1) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_131\, + O(0) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_132\, + Q(7 downto 0) => sig_dre2ibtt_tdata(7 downto 0), + S(3) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_41\, + S(2) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_42\, + S(1) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_43\, + S(0) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_44\, + SR(1) => I_RESET_n_7, + SR(0) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_9\, + \gcc0.gc0.count_d1_reg[0]\(0) => E(0), + \gpr1.dout_i_reg[1]\(2 downto 0) => \gpr1.dout_i_reg[1]_0\(2 downto 0), + \gpr1.dout_i_reg[1]_0\(2 downto 0) => \gpr1.dout_i_reg[1]\(2 downto 0), + \gpr1.dout_i_reg[3]\(3) => \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_87\, + \gpr1.dout_i_reg[3]\(2) => \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_88\, + \gpr1.dout_i_reg[3]\(1) => \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_89\, + \gpr1.dout_i_reg[3]\(0) => \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_90\, + \gpr1.dout_i_reg[7]\(3) => \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_91\, + \gpr1.dout_i_reg[7]\(2) => \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_92\, + \gpr1.dout_i_reg[7]\(1) => \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_93\, + \gpr1.dout_i_reg[7]\(0) => \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_94\, + lsig_end_of_cmd_reg => lsig_end_of_cmd_reg, + lsig_eop_reg => lsig_eop_reg, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\ => \ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/p_0_in2_in\, + p_0_in => p_0_in, + p_0_out(10 downto 0) => p_0_out(10 downto 0), + p_32_out => p_32_out, + sig_adjusted_addr_incr(8 downto 0) => sig_adjusted_addr_incr(8 downto 0), + sig_child_addr_cntr_lsh_reg(2 downto 0) => sig_child_addr_cntr_lsh_reg(2 downto 0), + \sig_child_addr_cntr_lsh_reg[11]\(0) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_39\, + \sig_child_addr_cntr_lsh_reg[7]\(3) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_134\, + \sig_child_addr_cntr_lsh_reg[7]\(2) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_135\, + \sig_child_addr_cntr_lsh_reg[7]\(1) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_136\, + \sig_child_addr_cntr_lsh_reg[7]\(0) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_137\, + sig_child_qual_error_reg => sig_child_qual_error_reg, + sig_child_qual_first_of_2 => sig_child_qual_first_of_2, + sig_clr_dbc_reg => sig_clr_dbc_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_csm_pop_child_cmd => sig_csm_pop_child_cmd, + sig_csm_state_ns1 => sig_csm_state_ns1, + sig_dre2ibtt_eop => sig_dre2ibtt_eop, + sig_dre2ibtt_tlast => sig_dre2ibtt_tlast, + sig_dre2ibtt_tstrb => sig_dre2ibtt_tstrb, + sig_ibtt2dre_tready => sig_ibtt2dre_tready, + sig_ibtt2wdc_tlast => sig_ibtt2wdc_tlast, + sig_init_reg => \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/sig_init_reg\, + sig_m_valid_out_reg(1) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_25\, + sig_m_valid_out_reg(0) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_26\, + sig_m_valid_out_reg_0(1) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_23\, + sig_m_valid_out_reg_0(0) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_24\, + sig_m_valid_out_reg_1(1) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_27\, + sig_m_valid_out_reg_1(0) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_28\, + sig_m_valid_out_reg_2(1) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_21\, + sig_m_valid_out_reg_2(0) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_22\, + sig_m_valid_out_reg_3(1) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_29\, + sig_m_valid_out_reg_3(0) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_30\, + sig_m_valid_out_reg_4(1) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_19\, + sig_m_valid_out_reg_4(0) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_20\, + sig_m_valid_out_reg_5(1) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_31\, + sig_m_valid_out_reg_5(0) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_32\, + sig_m_valid_out_reg_6(1) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_17\, + sig_m_valid_out_reg_6(0) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_18\, + sig_sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid, + \sig_strb_reg_out_reg[0]\(0) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_10\, + sig_stream_rst => sig_stream_rst, + sig_wdc2ibtt_tready => sig_wdc2ibtt_tready, + sig_xfer_cmd_cmplt_reg0 => sig_xfer_cmd_cmplt_reg0, + sig_xfer_is_seq_reg_reg(9) => sig_sf2pcc_cmd_cmplt, + sig_xfer_is_seq_reg_reg(8 downto 0) => sig_sf2pcc_xfer_bytes(8 downto 0), + sig_xfer_is_seq_reg_reg_0 => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_118\, + \sig_xfer_len_reg_reg[4]\(3) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_45\, + \sig_xfer_len_reg_reg[4]\(2) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_46\, + \sig_xfer_len_reg_reg[4]\(1) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_47\, + \sig_xfer_len_reg_reg[4]\(0) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_48\, + \sig_xfer_len_reg_reg[5]\(0) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_49\ + ); +\GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover_ibttcc + port map ( + CO(0) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_133\, + D(2) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_18\, + D(1) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_19\, + D(0) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_20\, + FIFO_Full_reg => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_1\, + FIFO_Full_reg_0 => I_WR_DATA_CNTL_n_0, + FIFO_Full_reg_1 => I_ADDR_CNTL_n_1, + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(21 downto 19) => p_0_out_1(2 downto 0), + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(18) => p_1_out, + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(17) => p_2_out, + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(16) => p_3_out, + \GEN_OMIT_DRE.sig_output_strt_offset_reg_reg[2]\(15 downto 0) => p_5_out(15 downto 0), + O(3) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_129\, + O(2) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_130\, + O(1) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_131\, + O(0) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_132\, + Q(0) => \I_CMD_FIFO/sig_rd_empty\, + S(3) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_41\, + S(2) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_42\, + S(1) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_43\, + S(0) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_44\, + SR(0) => sig_child_tag_reg0, + \gpr1.dout_i_reg[10]\ => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_118\, + \gpr1.dout_i_reg[7]\(3) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_134\, + \gpr1.dout_i_reg[7]\(2) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_135\, + \gpr1.dout_i_reg[7]\(1) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_136\, + \gpr1.dout_i_reg[7]\(0) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_137\, + \gpr1.dout_i_reg[7]_0\(3) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_45\, + \gpr1.dout_i_reg[7]_0\(2) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_46\, + \gpr1.dout_i_reg[7]_0\(1) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_47\, + \gpr1.dout_i_reg[7]_0\(0) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_48\, + \gpr1.dout_i_reg[8]\(0) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_49\, + \gpr1.dout_i_reg[8]_0\(0) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_39\, + \gpr1.dout_i_reg[9]\(9) => sig_sf2pcc_cmd_cmplt, + \gpr1.dout_i_reg[9]\(8 downto 0) => sig_sf2pcc_xfer_bytes(8 downto 0), + \in\(39) => p_13_out, + \in\(38) => p_27_out(0), + \in\(37 downto 32) => p_19_out(5 downto 0), + \in\(31 downto 3) => p_30_out(31 downto 3), + \in\(2 downto 0) => p_20_out(2 downto 0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\(49 downto 18) => sig_cmd2mstr_command(63 downto 32), + \out\(17) => sig_cmd2mstr_command(30), + \out\(16) => sig_cmd2mstr_command(23), + \out\(15 downto 0) => sig_cmd2mstr_command(15 downto 0), + p_10_out => p_10_out, + p_11_out => p_11_out, + p_22_out => p_22_out, + p_32_out => p_32_out, + p_9_out_0 => p_9_out_0, + sig_adjusted_addr_incr(8 downto 0) => sig_adjusted_addr_incr(8 downto 0), + \sig_child_addr_cntr_lsh_reg[3]_0\(3) => \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_87\, + \sig_child_addr_cntr_lsh_reg[3]_0\(2) => \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_88\, + \sig_child_addr_cntr_lsh_reg[3]_0\(1) => \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_89\, + \sig_child_addr_cntr_lsh_reg[3]_0\(0) => \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_90\, + \sig_child_addr_cntr_lsh_reg[7]_0\(3) => \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_91\, + \sig_child_addr_cntr_lsh_reg[7]_0\(2) => \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_92\, + \sig_child_addr_cntr_lsh_reg[7]_0\(1) => \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_93\, + \sig_child_addr_cntr_lsh_reg[7]_0\(0) => \GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC_n_94\, + sig_child_qual_error_reg => sig_child_qual_error_reg, + sig_child_qual_first_of_2 => sig_child_qual_first_of_2, + \sig_clr_cmd2addr_valid3_out__0\ => \sig_clr_cmd2addr_valid3_out__0\, + \sig_clr_cmd2data_valid4_out__0\ => \sig_clr_cmd2data_valid4_out__0\, + sig_csm_pop_child_cmd => sig_csm_pop_child_cmd, + sig_csm_state_ns1 => sig_csm_state_ns1, + sig_inhibit_rdy_n => \I_DRE_CNTL_FIFO/sig_inhibit_rdy_n\, + sig_inhibit_rdy_n_0 => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_inhibit_rdy_n\, + sig_inhibit_rdy_n_1 => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/sig_inhibit_rdy_n\, + sig_init_reg => \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/sig_init_reg\, + sig_input_cache_type_reg0 => sig_input_cache_type_reg0, + sig_input_reg_empty => sig_input_reg_empty, + sig_next_cmd_cmplt_reg_reg(1) => p_12_out, + sig_next_cmd_cmplt_reg_reg(0) => p_14_out, + sig_psm_halt => sig_psm_halt, + sig_psm_halt_reg_0 => I_CMD_STATUS_n_2, + sig_psm_pop_input_cmd => sig_psm_pop_input_cmd, + sig_sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid, + \sig_xfer_addr_reg_reg[2]_0\(2 downto 0) => sig_child_addr_cntr_lsh_reg(2 downto 0), + sig_xfer_cmd_cmplt_reg0 => sig_xfer_cmd_cmplt_reg0 + ); +\GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover_s2mm_realign + port map ( + DOUT(8 downto 0) => DOUT(8 downto 0), + EMPTY => EMPTY, + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1]\(1) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_17\, + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_flag_slice_reg_reg[0][1]\(0) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_18\, + \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[0].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1]\(1) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_25\, + \INCLUDE_PACKING.DO_REG_SLICES[1].lsig_flag_slice_reg_reg[1][1]\(0) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_26\, + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1]\(1) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_23\, + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_flag_slice_reg_reg[2][1]\(0) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_24\, + \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[2].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1]\(1) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_27\, + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_flag_slice_reg_reg[3][1]\(0) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_28\, + \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[3].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1]\(1) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_21\, + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_flag_slice_reg_reg[4][1]\(0) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_22\, + \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[4].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1]\(1) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_29\, + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_flag_slice_reg_reg[5][1]\(0) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_30\, + \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[5].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1]\(1) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_19\, + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_flag_slice_reg_reg[6][1]\(0) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_20\, + \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[6].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_data_slice_reg_reg[7][7]\(7 downto 0) => sig_dre2ibtt_tdata(7 downto 0), + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1]\(1) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_31\, + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_flag_slice_reg_reg[7][1]\(0) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_32\, + \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0\ => \INCLUDE_PACKING.DO_REG_SLICES[7].lsig_segment_ld_reg__0\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[0]\ => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_15\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]\ => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_11\, + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[1]_0\(1 downto 0) => lsig_0ffset_cntr(1 downto 0), + \INCLUDE_PACKING.lsig_0ffset_cntr_reg[2]\ => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_33\, + \INCLUDE_PACKING.lsig_first_dbeat_reg\ => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_4\, + \INCLUDE_PACKING.lsig_first_dbeat_reg_0\ => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_15\, + \INFERRED_GEN.cnt_i_reg[0]\ => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_1\, + Q(2 downto 0) => sig_sf_strt_addr_offset(2 downto 0), + RD_EN => RD_EN, + SR(0) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_9\, + \in\(21 downto 19) => p_0_out_1(2 downto 0), + \in\(18) => p_1_out, + \in\(17) => p_2_out, + \in\(16) => p_3_out, + \in\(15 downto 0) => p_5_out(15 downto 0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + p_0_in => p_0_in, + p_9_out_0 => p_9_out_0, + \sig_byte_cntr_reg[0]\(0) => \sig_good_strm_dbeat38_out__0\, + \sig_byte_cntr_reg[3]\(0) => \GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER_n_10\, + sig_clr_dbc_reg => sig_clr_dbc_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + \sig_data_skid_reg_reg[7]\ => \sig_data_skid_reg_reg[7]\, + sig_dre2ibtt_eop => sig_dre2ibtt_eop, + sig_dre2ibtt_tlast => sig_dre2ibtt_tlast, + sig_dre2ibtt_tstrb => sig_dre2ibtt_tstrb, + sig_ibtt2dre_tready => sig_ibtt2dre_tready, + sig_inhibit_rdy_n => \I_DRE_CNTL_FIFO/sig_inhibit_rdy_n\, + sig_init_reg => \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/sig_init_reg\, + sig_init_reg2 => \I_DRE_CNTL_FIFO/sig_init_reg2\, + sig_stream_rst => sig_stream_rst + ); +I_ADDR_CNTL: entity work.\Arty_Z7_20_axi_vdma_0_0_axi_datamover_addr_cntl__parameterized0\ + port map ( + \INFERRED_GEN.cnt_i_reg[0]\ => I_ADDR_CNTL_n_1, + \in\(39) => p_13_out, + \in\(38) => p_27_out(0), + \in\(37 downto 32) => p_19_out(5 downto 0), + \in\(31 downto 3) => p_30_out(31 downto 3), + \in\(2 downto 0) => p_20_out(2 downto 0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + m_axi_s2mm_awaddr(31 downto 0) => m_axi_s2mm_awaddr(31 downto 0), + m_axi_s2mm_awburst(0) => m_axi_s2mm_awburst(0), + m_axi_s2mm_awlen(5 downto 0) => m_axi_s2mm_awlen(5 downto 0), + m_axi_s2mm_awready => m_axi_s2mm_awready, + m_axi_s2mm_awsize(1 downto 0) => m_axi_s2mm_awsize(1 downto 0), + m_axi_s2mm_awvalid => m_axi_s2mm_awvalid, + \out\ => sig_addr2data_addr_posted, + p_22_out => p_22_out, + sig_addr2wsc_calc_error => sig_addr2wsc_calc_error, + sig_addr_reg_empty => sig_addr_reg_empty, + \sig_clr_cmd2addr_valid3_out__0\ => \sig_clr_cmd2addr_valid3_out__0\, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_halt_reg => sig_halt_reg, + sig_inhibit_rdy_n => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/sig_inhibit_rdy_n\, + sig_init_done => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/sig_init_done\, + sig_init_reg_reg => I_WR_STATUS_CNTLR_n_27, + sig_stream_rst => sig_stream_rst + ); +I_CMD_STATUS: entity work.\Arty_Z7_20_axi_vdma_0_0_axi_datamover_cmd_status__parameterized0\ + port map ( + CO(0) => CO(0), + FIFO_Full_reg(0) => Q(0), + \GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg\ => I_CMD_STATUS_n_8, + \GEN_STS_GRTR_THAN_8.ovrflo_err_reg\(0) => \GEN_STS_GRTR_THAN_8.ovrflo_err_reg\(0), + Q(0) => \I_CMD_FIFO/sig_rd_empty\, + S(0) => S(0), + cmnd_wr_1 => cmnd_wr_1, + decerr_i_reg => decerr_i_reg, + dma_err => dma_err, + \hsize_vid_reg[15]\(12 downto 0) => \hsize_vid_reg[15]\(12 downto 0), + \hsize_vid_reg[2]\(0) => \hsize_vid_reg[2]\(0), + \in\(16) => sig_wsc2stat_status(31), + \in\(15 downto 3) => sig_wsc2stat_status(23 downto 11), + \in\(2 downto 0) => sig_wsc2stat_status(6 downto 4), + interr_i_reg => interr_i_reg, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready, + \out\(49 downto 18) => sig_cmd2mstr_command(63 downto 32), + \out\(17) => sig_cmd2mstr_command(30), + \out\(16) => sig_cmd2mstr_command(23), + \out\(15 downto 0) => sig_cmd2mstr_command(15 downto 0), + p_10_out => p_10_out, + p_9_out => p_9_out, + s2mm_halt => s2mm_halt, + s2mm_soft_reset => s2mm_soft_reset, + \s_axis_cmd_tdata_reg[63]\(48 downto 0) => \s_axis_cmd_tdata_reg[63]\(48 downto 0), + s_axis_cmd_tvalid_reg(0) => s_axis_cmd_tvalid_reg(0), + s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid, + sig_calc_error_reg_reg => I_CMD_STATUS_n_2, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_dqual_reg_empty_reg => I_CMD_STATUS_n_12, + sig_init_done => \I_CMD_FIFO/sig_init_done\, + sig_init_done_0 => \GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_init_done\, + sig_init_reg_reg => I_WR_STATUS_CNTLR_n_30, + sig_init_reg_reg_0 => I_WR_STATUS_CNTLR_n_29, + sig_input_reg_empty => sig_input_reg_empty, + sig_psm_halt => sig_psm_halt, + sig_stream_rst => sig_stream_rst, + sig_wsc2stat_status_valid => sig_wsc2stat_status_valid, + slverr_i_reg => slverr_i_reg + ); +I_RESET: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover_reset + port map ( + SR(0) => I_RESET_n_6, + datamover_idle_2 => datamover_idle_2, + datamover_idle_reg => datamover_idle_reg, + halt_i_reg => halt_i_reg, + lsig_end_of_cmd_reg => lsig_end_of_cmd_reg, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + s2mm_dmacr(0) => s2mm_dmacr(0), + s2mm_halt => s2mm_halt, + s2mm_halt_cmplt => s2mm_halt_cmplt, + s_soft_reset_i_reg => s_soft_reset_i_reg, + sig_addr2wsc_calc_error => sig_addr2wsc_calc_error, + sig_addr_reg_empty => sig_addr_reg_empty, + \sig_byte_cntr_reg[8]\(0) => I_RESET_n_7, + sig_clr_dbc_reg => sig_clr_dbc_reg, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_data2rst_stop_cmplt => sig_data2rst_stop_cmplt, + sig_halt_reg => sig_halt_reg, + sig_halt_reg_reg => I_RESET_n_3, + sig_rst2all_stop_request_0 => sig_rst2all_stop_request_0, + sig_stream_rst => sig_stream_rst, + sig_wsc2rst_stop_cmplt => sig_wsc2rst_stop_cmplt + ); +I_S2MM_MMAP_SKID_BUF: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover_skid2mm_buf + port map ( + D(63 downto 0) => sig_ibtt2wdc_tdata(63 downto 0), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + m_axi_s2mm_wdata(63 downto 0) => m_axi_s2mm_wdata(63 downto 0), + m_axi_s2mm_wlast => m_axi_s2mm_wlast, + m_axi_s2mm_wready => m_axi_s2mm_wready, + m_axi_s2mm_wvalid => m_axi_s2mm_wvalid, + \out\ => sig_skid2data_wready, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_data2skid_wvalid => sig_data2skid_wvalid, + \sig_dbeat_cntr_eq_0__2\ => \sig_dbeat_cntr_eq_0__2\, + sig_dqual_reg_full => sig_dqual_reg_full, + sig_init_reg => \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/sig_init_reg\, + sig_stream_rst => sig_stream_rst + ); +I_WR_DATA_CNTL: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover_wrdata_cntl + port map ( + E(0) => I_WR_DATA_CNTL_n_25, + \INFERRED_GEN.cnt_i_reg[0]\ => I_WR_DATA_CNTL_n_0, + SR(0) => I_RESET_n_6, + \in\(15) => I_WR_DATA_CNTL_n_4, + \in\(14 downto 2) => sig_data2wsc_bytes_rcvd(15 downto 3), + \in\(1) => sig_data2wsc_cmd_cmplt, + \in\(0) => sig_data2wsc_calc_err, + lsig_end_of_cmd_reg => lsig_end_of_cmd_reg, + lsig_eop_reg => lsig_eop_reg, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\ => \ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/p_0_in2_in\, + p_11_out => p_11_out, + \sig_clr_cmd2data_valid4_out__0\ => \sig_clr_cmd2data_valid4_out__0\, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ => I_WR_STATUS_CNTLR_n_21, + sig_data2rst_stop_cmplt => sig_data2rst_stop_cmplt, + sig_data2skid_wvalid => sig_data2skid_wvalid, + sig_data2wsc_valid => sig_data2wsc_valid, + \sig_data_reg_out_reg[67]\(0) => sig_ibtt2wdc_stbs_asserted(3), + \sig_dbeat_cntr_eq_0__2\ => \sig_dbeat_cntr_eq_0__2\, + sig_dqual_reg_full => sig_dqual_reg_full, + sig_halt_reg => sig_halt_reg, + sig_halt_reg_dly3 => sig_halt_reg_dly3, + sig_ibtt2wdc_tlast => sig_ibtt2wdc_tlast, + sig_inhibit_rdy_n => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_inhibit_rdy_n\, + sig_inhibit_rdy_n_reg => I_CMD_STATUS_n_12, + sig_init_done => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_init_done\, + sig_init_reg_reg => I_WR_STATUS_CNTLR_n_28, + sig_m_valid_out_reg => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_117\, + sig_m_valid_out_reg_0 => sig_ibtt2wdc_tvalid, + sig_m_valid_out_reg_1(0) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_50\, + sig_m_valid_out_reg_2(0) => \GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT_n_51\, + sig_posted_to_axi_reg => sig_addr2data_addr_posted, + sig_s_ready_out_reg => sig_skid2data_wready, + sig_set_push2wsc => sig_set_push2wsc, + sig_stream_rst => sig_stream_rst, + sig_wdc2ibtt_tready => sig_wdc2ibtt_tready, + sig_wdc_status_going_full => sig_wdc_status_going_full, + sig_wr_fifo => \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/sig_wr_fifo\, + sig_wsc2stat_status_valid => sig_wsc2stat_status_valid, + sig_xfer_calc_err_reg_reg(8) => p_13_out, + sig_xfer_calc_err_reg_reg(7) => p_12_out, + sig_xfer_calc_err_reg_reg(6) => p_14_out, + sig_xfer_calc_err_reg_reg(5 downto 0) => p_19_out(5 downto 0) + ); +I_WR_STATUS_CNTLR: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover_wr_status_cntl + port map ( + \GEN_INDET_BTT.lsig_eop_reg_reg\(15) => I_WR_DATA_CNTL_n_4, + \GEN_INDET_BTT.lsig_eop_reg_reg\(14 downto 2) => sig_data2wsc_bytes_rcvd(15 downto 3), + \GEN_INDET_BTT.lsig_eop_reg_reg\(1) => sig_data2wsc_cmd_cmplt, + \GEN_INDET_BTT.lsig_eop_reg_reg\(0) => sig_data2wsc_calc_err, + SR(0) => sig_child_tag_reg0, + \in\(16) => sig_wsc2stat_status(31), + \in\(15 downto 3) => sig_wsc2stat_status(23 downto 11), + \in\(2 downto 0) => sig_wsc2stat_status(6 downto 4), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + m_axi_s2mm_bready => m_axi_s2mm_bready, + m_axi_s2mm_bresp(1 downto 0) => m_axi_s2mm_bresp(1 downto 0), + m_axi_s2mm_bvalid => m_axi_s2mm_bvalid, + \out\ => sig_addr2data_addr_posted, + sig_addr2wsc_calc_error => sig_addr2wsc_calc_error, + sig_cmd_stat_rst_user_reg_n_cdc_from_reg => sig_cmd_stat_rst_user_reg_n_cdc_from_reg, + sig_csm_pop_child_cmd => sig_csm_pop_child_cmd, + sig_data2wsc_valid => sig_data2wsc_valid, + sig_halt_reg => sig_halt_reg, + sig_halt_reg_dly3 => sig_halt_reg_dly3, + sig_inhibit_rdy_n_reg => I_CMD_STATUS_n_8, + sig_init_done => \GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/sig_init_done\, + sig_init_done_0 => \GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/sig_init_done\, + sig_init_done_1 => \GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_init_done\, + sig_init_done_2 => \I_CMD_FIFO/sig_init_done\, + sig_init_done_reg => I_WR_STATUS_CNTLR_n_27, + sig_init_done_reg_0 => I_WR_STATUS_CNTLR_n_28, + sig_init_done_reg_1 => I_WR_STATUS_CNTLR_n_29, + sig_init_done_reg_2 => I_WR_STATUS_CNTLR_n_30, + sig_init_reg => \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/sig_init_reg\, + sig_init_reg2 => \I_DRE_CNTL_FIFO/sig_init_reg2\, + sig_input_cache_type_reg0 => sig_input_cache_type_reg0, + sig_psm_pop_input_cmd => sig_psm_pop_input_cmd, + sig_push_to_wsc_reg => I_WR_STATUS_CNTLR_n_21, + sig_s_h_halt_reg_reg => I_RESET_n_3, + sig_set_push2wsc => sig_set_push2wsc, + sig_stream_rst => sig_stream_rst, + sig_wdc_status_going_full => sig_wdc_status_going_full, + sig_wr_fifo => \GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/sig_wr_fifo\, + sig_wsc2rst_stop_cmplt => sig_wsc2rst_stop_cmplt, + sig_wsc2stat_status_valid => sig_wsc2stat_status_valid ); end STRUCTURE; library IEEE; @@ -37286,107 +92508,116 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20_axi_vdma_0_0_axi_datamover is port ( + sig_rst2all_stop_request : out STD_LOGIC; m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_mm2s_arvalid : out STD_LOGIC; - mm2s_halt_cmplt : out STD_LOGIC; - sig_rst2all_stop_request : out STD_LOGIC; - \sig_user_skid_reg_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - dm2linebuf_mm2s_tvalid : out STD_LOGIC; + lsig_0ffset_cntr : out STD_LOGIC; + m_axi_s2mm_awburst : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_s2mm_awvalid : out STD_LOGIC; + m_axi_s2mm_wvalid : out STD_LOGIC; + \sig_data_skid_reg_reg[7]\ : out STD_LOGIC; + DI : out STD_LOGIC_VECTOR ( 10 downto 0 ); + sig_rst2all_stop_request_0 : out STD_LOGIC; + m_axi_s2mm_wlast : out STD_LOGIC; + RD_EN : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); + datamover_idle_reg : out STD_LOGIC; + mm2s_halt_cmplt : out STD_LOGIC; + p_9_out : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_mm2s_rready : out STD_LOGIC; - dm2linebuf_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - interr_i_reg : out STD_LOGIC; - slverr_i_reg : out STD_LOGIC; + \GEN_STS_GRTR_THAN_8.ovrflo_err_reg\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axis_cmd_tvalid_reg : out STD_LOGIC_VECTOR ( 0 to 0 ); + CO : out STD_LOGIC_VECTOR ( 0 to 0 ); + datamover_idle_reg_0 : out STD_LOGIC; + s2mm_halt_cmplt : out STD_LOGIC; decerr_i_reg : out STD_LOGIC; + FIFO_Full_reg : out STD_LOGIC_VECTOR ( 0 to 0 ); + slverr_i_reg : out STD_LOGIC; + interr_i_reg : out STD_LOGIC; + decerr_i_reg_0 : out STD_LOGIC; + slverr_i_reg_0 : out STD_LOGIC; + interr_i_reg_0 : out STD_LOGIC; + \gcc0.gc0.count_d1_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); - m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 4 downto 0 ); m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_s2mm_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_s2mm_awlen : out STD_LOGIC_VECTOR ( 5 downto 0 ); + m_axi_s2mm_awsize : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_s2mm_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + \gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \gpr1.dout_i_reg[1]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_mm2s_rready : out STD_LOGIC; + DIN : out STD_LOGIC_VECTOR ( 0 to 0 ); + \sig_user_skid_reg_reg[0]\ : out STD_LOGIC; + dm2linebuf_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_s2mm_bready : out STD_LOGIC; m_axi_mm2s_aclk : in STD_LOGIC; m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); \out\ : in STD_LOGIC; halt_i_reg : in STD_LOGIC; - p_55_out : in STD_LOGIC; - m_axi_mm2s_rlast : in STD_LOGIC; - m_axi_mm2s_rvalid : in STD_LOGIC; - m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_s2mm_aclk : in STD_LOGIC; + s_soft_reset_i_reg : in STD_LOGIC; + halt_i_reg_0 : in STD_LOGIC; + prmry_resetn_i_reg : in STD_LOGIC; + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ : in STD_LOGIC; + DOUT : in STD_LOGIC_VECTOR ( 8 downto 0 ); + EMPTY : in STD_LOGIC; cmnd_wr : in STD_LOGIC; mm2s_halt : in STD_LOGIC; - p_57_out : in STD_LOGIC; - sts_tready_reg : in STD_LOGIC; - p_8_out : in STD_LOGIC; - \fifo_wren__0\ : in STD_LOGIC; + p_71_out : in STD_LOGIC_VECTOR ( 0 to 0 ); + datamover_idle : in STD_LOGIC; + s2mm_halt : in STD_LOGIC; + s2mm_soft_reset : in STD_LOGIC; + dma_err : in STD_LOGIC; + cmnd_wr_1 : in STD_LOGIC; + \hsize_vid_reg[15]\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); + \hsize_vid_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + S : in STD_LOGIC_VECTOR ( 0 to 0 ); + s2mm_dmacr : in STD_LOGIC_VECTOR ( 0 to 0 ); + datamover_idle_2 : in STD_LOGIC; + m_axi_mm2s_rlast : in STD_LOGIC; m_axi_mm2s_arready : in STD_LOGIC; - \in\ : in STD_LOGIC_VECTOR ( 48 downto 0 ) + m_axi_s2mm_awready : in STD_LOGIC; + m_axi_s2mm_wready : in STD_LOGIC; + \in\ : in STD_LOGIC_VECTOR ( 48 downto 0 ); + \s_axis_cmd_tdata_reg[63]\ : in STD_LOGIC_VECTOR ( 48 downto 0 ); + m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + p_0_out : in STD_LOGIC_VECTOR ( 10 downto 0 ); + p_56_out : in STD_LOGIC; + p_58_out : in STD_LOGIC; + sts_tready_reg : in STD_LOGIC; + m_axi_mm2s_rvalid : in STD_LOGIC; + m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axis_s2mm_cmd_tvalid : in STD_LOGIC; + m_axi_s2mm_bvalid : in STD_LOGIC; + m_axis_s2mm_sts_tready : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of Arty_Z7_20_axi_vdma_0_0_axi_datamover : entity is "axi_datamover"; end Arty_Z7_20_axi_vdma_0_0_axi_datamover; architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_datamover is - signal \GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/gsym_dc.dc/count_reg\ : STD_LOGIC_VECTOR ( 4 to 4 ); - signal \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_11\ : STD_LOGIC; - signal \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_47\ : STD_LOGIC; - signal \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_48\ : STD_LOGIC; - signal \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_49\ : STD_LOGIC; - signal \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_50\ : STD_LOGIC; - signal \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_54\ : STD_LOGIC; - signal \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_55\ : STD_LOGIC; - signal \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_6\ : STD_LOGIC; - signal \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_7\ : STD_LOGIC; - signal \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_8\ : STD_LOGIC; - signal \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_9\ : STD_LOGIC; - signal \p_0_out_carry__0_n_3\ : STD_LOGIC; - signal \p_0_out_carry__0_n_6\ : STD_LOGIC; - signal \p_0_out_carry__0_n_7\ : STD_LOGIC; - signal p_0_out_carry_n_0 : STD_LOGIC; - signal p_0_out_carry_n_1 : STD_LOGIC; - signal p_0_out_carry_n_2 : STD_LOGIC; - signal p_0_out_carry_n_3 : STD_LOGIC; - signal p_0_out_carry_n_4 : STD_LOGIC; - signal p_0_out_carry_n_5 : STD_LOGIC; - signal p_0_out_carry_n_6 : STD_LOGIC; - signal p_0_out_carry_n_7 : STD_LOGIC; - signal \NLW_p_0_out_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW_p_0_out_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); - attribute METHODOLOGY_DRC_VIOS : string; - attribute METHODOLOGY_DRC_VIOS of p_0_out_carry : label is "{SYNTH-8 {cell *THIS*}}"; - attribute METHODOLOGY_DRC_VIOS of \p_0_out_carry__0\ : label is "{SYNTH-8 {cell *THIS*}}"; begin \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover_mm2s_full_wrap port map ( - D(5) => \p_0_out_carry__0_n_6\, - D(4) => \p_0_out_carry__0_n_7\, - D(3) => p_0_out_carry_n_4, - D(2) => p_0_out_carry_n_5, - D(1) => p_0_out_carry_n_6, - D(0) => p_0_out_carry_n_7, - DI(3) => \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_6\, - DI(2) => \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_7\, - DI(1) => \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_8\, - DI(0) => \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_9\, + DIN(0) => DIN(0), E(0) => E(0), - FIFO_Full_reg(0) => Q(0), - Q(1) => \GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/gsym_dc.dc/count_reg\(4), - Q(0) => \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_11\, - S(3) => \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_47\, - S(2) => \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_48\, - S(1) => \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_49\, - S(0) => \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_50\, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => lsig_0ffset_cntr, + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]_0\ => \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\, + Q(0) => FIFO_Full_reg(0), cmnd_wr => cmnd_wr, - \count_reg[6]\(1) => \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_54\, - \count_reg[6]\(0) => \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_55\, + datamover_idle => datamover_idle, + datamover_idle_reg => datamover_idle_reg, decerr_i_reg => decerr_i_reg, dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), - dm2linebuf_mm2s_tvalid => dm2linebuf_mm2s_tvalid, - \fifo_wren__0\ => \fifo_wren__0\, halt_i_reg => halt_i_reg, \in\(48 downto 0) => \in\(48 downto 0), interr_i_reg => interr_i_reg, m_axi_mm2s_aclk => m_axi_mm2s_aclk, m_axi_mm2s_araddr(31 downto 0) => m_axi_mm2s_araddr(31 downto 0), m_axi_mm2s_arburst(0) => m_axi_mm2s_arburst(0), - m_axi_mm2s_arlen(3 downto 0) => m_axi_mm2s_arlen(3 downto 0), + m_axi_mm2s_arlen(4 downto 0) => m_axi_mm2s_arlen(4 downto 0), m_axi_mm2s_arready => m_axi_mm2s_arready, m_axi_mm2s_arsize(1 downto 0) => m_axi_mm2s_arsize(1 downto 0), m_axi_mm2s_arvalid => m_axi_mm2s_arvalid, @@ -37398,49 +92629,65 @@ begin mm2s_halt => mm2s_halt, mm2s_halt_cmplt => mm2s_halt_cmplt, \out\ => \out\, - p_55_out => p_55_out, - p_57_out => p_57_out, - p_8_out => p_8_out, + p_56_out => p_56_out, + p_58_out => p_58_out, + p_71_out(0) => p_71_out(0), + prmry_resetn_i_reg => prmry_resetn_i_reg, sig_rst2all_stop_request => sig_rst2all_stop_request, - \sig_user_skid_reg_reg[0]\(0) => \sig_user_skid_reg_reg[0]\(0), + \sig_user_skid_reg_reg[0]\ => \sig_user_skid_reg_reg[0]\, slverr_i_reg => slverr_i_reg, sts_tready_reg => sts_tready_reg ); -p_0_out_carry: unisim.vcomponents.CARRY4 +\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover_s2mm_full_wrap port map ( - CI => '0', - CO(3) => p_0_out_carry_n_0, - CO(2) => p_0_out_carry_n_1, - CO(1) => p_0_out_carry_n_2, - CO(0) => p_0_out_carry_n_3, - CYINIT => \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_11\, - DI(3) => \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_6\, - DI(2) => \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_7\, - DI(1) => \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_8\, - DI(0) => \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_9\, - O(3) => p_0_out_carry_n_4, - O(2) => p_0_out_carry_n_5, - O(1) => p_0_out_carry_n_6, - O(0) => p_0_out_carry_n_7, - S(3) => \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_47\, - S(2) => \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_48\, - S(1) => \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_49\, - S(0) => \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_50\ - ); -\p_0_out_carry__0\: unisim.vcomponents.CARRY4 - port map ( - CI => p_0_out_carry_n_0, - CO(3 downto 1) => \NLW_p_0_out_carry__0_CO_UNCONNECTED\(3 downto 1), - CO(0) => \p_0_out_carry__0_n_3\, - CYINIT => '0', - DI(3 downto 1) => B"000", - DI(0) => \GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/gsym_dc.dc/count_reg\(4), - O(3 downto 2) => \NLW_p_0_out_carry__0_O_UNCONNECTED\(3 downto 2), - O(1) => \p_0_out_carry__0_n_6\, - O(0) => \p_0_out_carry__0_n_7\, - S(3 downto 2) => B"00", - S(1) => \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_54\, - S(0) => \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER_n_55\ + CO(0) => CO(0), + DI(10 downto 0) => DI(10 downto 0), + DOUT(8 downto 0) => DOUT(8 downto 0), + E(0) => \gcc0.gc0.count_d1_reg[0]\(0), + EMPTY => EMPTY, + \GEN_STS_GRTR_THAN_8.ovrflo_err_reg\(0) => \GEN_STS_GRTR_THAN_8.ovrflo_err_reg\(0), + Q(0) => Q(0), + RD_EN => RD_EN, + S(0) => S(0), + cmnd_wr_1 => cmnd_wr_1, + datamover_idle_2 => datamover_idle_2, + datamover_idle_reg => datamover_idle_reg_0, + decerr_i_reg => decerr_i_reg_0, + dma_err => dma_err, + \gpr1.dout_i_reg[1]\(2 downto 0) => \gpr1.dout_i_reg[1]\(2 downto 0), + \gpr1.dout_i_reg[1]_0\(2 downto 0) => \gpr1.dout_i_reg[1]_0\(2 downto 0), + halt_i_reg => halt_i_reg_0, + \hsize_vid_reg[15]\(12 downto 0) => \hsize_vid_reg[15]\(12 downto 0), + \hsize_vid_reg[2]\(0) => \hsize_vid_reg[2]\(0), + interr_i_reg => interr_i_reg_0, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + m_axi_s2mm_awaddr(31 downto 0) => m_axi_s2mm_awaddr(31 downto 0), + m_axi_s2mm_awburst(0) => m_axi_s2mm_awburst(0), + m_axi_s2mm_awlen(5 downto 0) => m_axi_s2mm_awlen(5 downto 0), + m_axi_s2mm_awready => m_axi_s2mm_awready, + m_axi_s2mm_awsize(1 downto 0) => m_axi_s2mm_awsize(1 downto 0), + m_axi_s2mm_awvalid => m_axi_s2mm_awvalid, + m_axi_s2mm_bready => m_axi_s2mm_bready, + m_axi_s2mm_bresp(1 downto 0) => m_axi_s2mm_bresp(1 downto 0), + m_axi_s2mm_bvalid => m_axi_s2mm_bvalid, + m_axi_s2mm_wdata(63 downto 0) => m_axi_s2mm_wdata(63 downto 0), + m_axi_s2mm_wlast => m_axi_s2mm_wlast, + m_axi_s2mm_wready => m_axi_s2mm_wready, + m_axi_s2mm_wvalid => m_axi_s2mm_wvalid, + m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready, + p_0_out(10 downto 0) => p_0_out(10 downto 0), + p_9_out => p_9_out, + s2mm_dmacr(0) => s2mm_dmacr(0), + s2mm_halt => s2mm_halt, + s2mm_halt_cmplt => s2mm_halt_cmplt, + s2mm_soft_reset => s2mm_soft_reset, + \s_axis_cmd_tdata_reg[63]\(48 downto 0) => \s_axis_cmd_tdata_reg[63]\(48 downto 0), + s_axis_cmd_tvalid_reg(0) => s_axis_cmd_tvalid_reg(0), + s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid, + s_soft_reset_i_reg => s_soft_reset_i_reg, + \sig_data_skid_reg_reg[7]\ => \sig_data_skid_reg_reg[7]\, + sig_rst2all_stop_request_0 => sig_rst2all_stop_request_0, + slverr_i_reg => slverr_i_reg_0 ); end STRUCTURE; library IEEE; @@ -37536,8 +92783,8 @@ entity Arty_Z7_20_axi_vdma_0_0_axi_vdma is m_axi_s2mm_bvalid : in STD_LOGIC; m_axi_s2mm_bready : out STD_LOGIC; s2mm_prmry_reset_out_n : out STD_LOGIC; - s_axis_s2mm_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axis_s2mm_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axis_s2mm_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axis_s2mm_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axis_s2mm_tuser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axis_s2mm_tvalid : in STD_LOGIC; s_axis_s2mm_tready : out STD_LOGIC; @@ -37599,7 +92846,7 @@ entity Arty_Z7_20_axi_vdma_0_0_axi_vdma is attribute C_INCLUDE_MM2S_SF : integer; attribute C_INCLUDE_MM2S_SF of Arty_Z7_20_axi_vdma_0_0_axi_vdma : entity is 0; attribute C_INCLUDE_S2MM : integer; - attribute C_INCLUDE_S2MM of Arty_Z7_20_axi_vdma_0_0_axi_vdma : entity is 0; + attribute C_INCLUDE_S2MM of Arty_Z7_20_axi_vdma_0_0_axi_vdma : entity is 1; attribute C_INCLUDE_S2MM_DRE : integer; attribute C_INCLUDE_S2MM_DRE of Arty_Z7_20_axi_vdma_0_0_axi_vdma : entity is 0; attribute C_INCLUDE_S2MM_SF : integer; @@ -37615,11 +92862,11 @@ entity Arty_Z7_20_axi_vdma_0_0_axi_vdma is attribute C_MM2S_GENLOCK_REPEAT_EN : integer; attribute C_MM2S_GENLOCK_REPEAT_EN of Arty_Z7_20_axi_vdma_0_0_axi_vdma : entity is 0; attribute C_MM2S_LINEBUFFER_DEPTH : integer; - attribute C_MM2S_LINEBUFFER_DEPTH of Arty_Z7_20_axi_vdma_0_0_axi_vdma : entity is 4096; + attribute C_MM2S_LINEBUFFER_DEPTH of Arty_Z7_20_axi_vdma_0_0_axi_vdma : entity is 2048; attribute C_MM2S_LINEBUFFER_THRESH : integer; attribute C_MM2S_LINEBUFFER_THRESH of Arty_Z7_20_axi_vdma_0_0_axi_vdma : entity is 4; attribute C_MM2S_MAX_BURST_LENGTH : integer; - attribute C_MM2S_MAX_BURST_LENGTH of Arty_Z7_20_axi_vdma_0_0_axi_vdma : entity is 16; + attribute C_MM2S_MAX_BURST_LENGTH of Arty_Z7_20_axi_vdma_0_0_axi_vdma : entity is 32; attribute C_MM2S_SOF_ENABLE : integer; attribute C_MM2S_SOF_ENABLE of Arty_Z7_20_axi_vdma_0_0_axi_vdma : entity is 1; attribute C_M_AXIS_MM2S_TDATA_WIDTH : integer; @@ -37639,27 +92886,27 @@ entity Arty_Z7_20_axi_vdma_0_0_axi_vdma is attribute C_M_AXI_SG_DATA_WIDTH : integer; attribute C_M_AXI_SG_DATA_WIDTH of Arty_Z7_20_axi_vdma_0_0_axi_vdma : entity is 32; attribute C_NUM_FSTORES : integer; - attribute C_NUM_FSTORES of Arty_Z7_20_axi_vdma_0_0_axi_vdma : entity is 1; + attribute C_NUM_FSTORES of Arty_Z7_20_axi_vdma_0_0_axi_vdma : entity is 3; attribute C_PRMRY_IS_ACLK_ASYNC : integer; attribute C_PRMRY_IS_ACLK_ASYNC of Arty_Z7_20_axi_vdma_0_0_axi_vdma : entity is 1; attribute C_S2MM_GENLOCK_MODE : integer; - attribute C_S2MM_GENLOCK_MODE of Arty_Z7_20_axi_vdma_0_0_axi_vdma : entity is 0; + attribute C_S2MM_GENLOCK_MODE of Arty_Z7_20_axi_vdma_0_0_axi_vdma : entity is 2; attribute C_S2MM_GENLOCK_NUM_MASTERS : integer; attribute C_S2MM_GENLOCK_NUM_MASTERS of Arty_Z7_20_axi_vdma_0_0_axi_vdma : entity is 1; attribute C_S2MM_GENLOCK_REPEAT_EN : integer; attribute C_S2MM_GENLOCK_REPEAT_EN of Arty_Z7_20_axi_vdma_0_0_axi_vdma : entity is 1; attribute C_S2MM_LINEBUFFER_DEPTH : integer; - attribute C_S2MM_LINEBUFFER_DEPTH of Arty_Z7_20_axi_vdma_0_0_axi_vdma : entity is 512; + attribute C_S2MM_LINEBUFFER_DEPTH of Arty_Z7_20_axi_vdma_0_0_axi_vdma : entity is 2048; attribute C_S2MM_LINEBUFFER_THRESH : integer; attribute C_S2MM_LINEBUFFER_THRESH of Arty_Z7_20_axi_vdma_0_0_axi_vdma : entity is 4; attribute C_S2MM_MAX_BURST_LENGTH : integer; - attribute C_S2MM_MAX_BURST_LENGTH of Arty_Z7_20_axi_vdma_0_0_axi_vdma : entity is 8; + attribute C_S2MM_MAX_BURST_LENGTH of Arty_Z7_20_axi_vdma_0_0_axi_vdma : entity is 32; attribute C_S2MM_SOF_ENABLE : integer; attribute C_S2MM_SOF_ENABLE of Arty_Z7_20_axi_vdma_0_0_axi_vdma : entity is 1; attribute C_SELECT_XPM : integer; attribute C_SELECT_XPM of Arty_Z7_20_axi_vdma_0_0_axi_vdma : entity is 0; attribute C_S_AXIS_S2MM_TDATA_WIDTH : integer; - attribute C_S_AXIS_S2MM_TDATA_WIDTH of Arty_Z7_20_axi_vdma_0_0_axi_vdma : entity is 32; + attribute C_S_AXIS_S2MM_TDATA_WIDTH of Arty_Z7_20_axi_vdma_0_0_axi_vdma : entity is 8; attribute C_S_AXIS_S2MM_TUSER_BITS : integer; attribute C_S_AXIS_S2MM_TUSER_BITS of Arty_Z7_20_axi_vdma_0_0_axi_vdma : entity is 1; attribute C_S_AXI_LITE_ADDR_WIDTH : integer; @@ -37687,126 +92934,324 @@ end Arty_Z7_20_axi_vdma_0_0_axi_vdma; architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma is signal \\ : STD_LOGIC; signal \\ : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_40 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_48 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_49 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_50 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_51 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_52 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_53 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_54 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_55 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_56 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_57 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_58 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_59 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_60 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_61 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_62 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_63 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_64 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_65 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_66 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_67 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_68 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_69 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_70 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_71 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_72 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_73 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_74 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_75 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_76 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_77 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_78 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_79 : STD_LOGIC; - signal AXI_LITE_REG_INTERFACE_I_n_80 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_100 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_101 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_102 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_103 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_104 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_105 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_106 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_107 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_108 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_109 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_110 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_111 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_112 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_113 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_114 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_115 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_128 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_129 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_130 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_131 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_132 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_133 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_134 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_135 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_136 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_137 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_138 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_139 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_140 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_141 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_142 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_143 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_144 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_145 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_146 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_147 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_148 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_149 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_150 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_151 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_152 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_153 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_154 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_155 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_156 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_157 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_158 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_159 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_160 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_161 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_162 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_163 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_164 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_165 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_166 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_167 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_168 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_169 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_170 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_171 : STD_LOGIC; signal AXI_LITE_REG_INTERFACE_I_n_81 : STD_LOGIC; signal AXI_LITE_REG_INTERFACE_I_n_82 : STD_LOGIC; signal AXI_LITE_REG_INTERFACE_I_n_83 : STD_LOGIC; signal AXI_LITE_REG_INTERFACE_I_n_84 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_85 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_86 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_87 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_88 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_89 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_90 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_91 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_92 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_93 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_94 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_95 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_96 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_97 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_98 : STD_LOGIC; + signal AXI_LITE_REG_INTERFACE_I_n_99 : STD_LOGIC; signal \GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/p_in_d1_cdc_from\ : STD_LOGIC; + signal \GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/p_in_d1_cdc_from_13\ : STD_LOGIC; signal \GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/prmry_in_xored\ : STD_LOGIC; + signal \GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/prmry_in_xored_7\ : STD_LOGIC; signal \GEN_CDC_FOR_ASYNC.PRMTR_UPDT_CDC_I/scndry_reset2\ : STD_LOGIC; signal \GEN_CDC_FOR_ASYNC.SOF_CDC_I/p_in_d1_cdc_from\ : STD_LOGIC; + signal \GEN_CDC_FOR_ASYNC.SOF_CDC_I/p_in_d1_cdc_from_14\ : STD_LOGIC; signal \GEN_CDC_FOR_ASYNC.SOF_CDC_I/prmry_in_xored\ : STD_LOGIC; + signal \GEN_CDC_FOR_ASYNC.SOF_CDC_I/prmry_in_xored_12\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I/prmry_reset2\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/p_5_out\ : STD_LOGIC; + signal \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/p_8_out\ : STD_LOGIC; + signal \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/lsig_0ffset_cntr\ : STD_LOGIC; signal \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_rd_empty\ : STD_LOGIC; signal \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/sig_rst2all_stop_request\ : STD_LOGIC; signal \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.MM2S_INTRPT_CROSSING_I/prmry_reset2\ : STD_LOGIC; - signal \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.MM2S_INTRPT_CROSSING_I/scndry_reset2\ : STD_LOGIC; signal \GEN_RESET_FOR_MM2S.RESET_I/halt_reset\ : STD_LOGIC; signal \GEN_RESET_FOR_MM2S.RESET_I/s_soft_reset_i0\ : STD_LOGIC; + signal \GEN_RESET_FOR_S2MM.RESET_I/halt_i0\ : STD_LOGIC; + signal \GEN_RESET_FOR_S2MM.RESET_I/halt_reset\ : STD_LOGIC; + signal \GEN_RESET_FOR_S2MM.RESET_I/run_stop_d1\ : STD_LOGIC; + signal \GEN_RESET_FOR_S2MM.RESET_I/s_soft_reset_i0\ : STD_LOGIC; + signal \GEN_RESET_FOR_S2MM.RESET_I/soft_reset_d1\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF/p_in_d1_cdc_from\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF/prmry_in_xored\ : STD_LOGIC; + signal \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF/prmry_reset2\ : STD_LOGIC; + signal \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_0\ : STD_LOGIC; + signal \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_1\ : STD_LOGIC; + signal \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_2\ : STD_LOGIC; + signal \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_3\ : STD_LOGIC; + signal \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_4\ : STD_LOGIC; + signal \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_5\ : STD_LOGIC; + signal \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_n_0\ : STD_LOGIC; + signal \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_n_1\ : STD_LOGIC; + signal \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_n_2\ : STD_LOGIC; + signal \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_n_3\ : STD_LOGIC; + signal \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_n_5\ : STD_LOGIC; + signal \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_0_out\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_11_out\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_byte_cntr\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_dre2ibtt_eop_reg\ : STD_LOGIC; + signal \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_dre2ibtt_tlast_reg\ : STD_LOGIC; + signal \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_rd_empty\ : STD_LOGIC; + signal \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/sig_rst2all_stop_request\ : STD_LOGIC; + signal \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.S2MM_INTRPT_CROSSING_I/prmry_reset2\ : STD_LOGIC; + signal \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.S2MM_INTRPT_CROSSING_I/scndry_reset2\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_31\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_32\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_33\ : STD_LOGIC; signal \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_34\ : STD_LOGIC; signal \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_35\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_36\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_37\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_38\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_39\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_8\ : STD_LOGIC; signal \GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_3\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_9\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_157\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_158\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_159\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_160\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_161\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_162\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_163\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_164\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_165\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_166\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_167\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_168\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_169\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_170\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_171\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_172\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_173\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_174\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_175\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_176\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_6\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_7\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_8\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_217\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_218\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_219\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_220\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_221\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_222\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_223\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_224\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_225\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_226\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_227\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_228\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_231\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_54\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_55\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_56\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_57\ : STD_LOGIC; signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_58\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_59\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_60\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_62\ : STD_LOGIC; signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_63\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_64\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_65\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_67\ : STD_LOGIC; signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_68\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_69\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_70\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_71\ : STD_LOGIC; signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_72\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_76\ : STD_LOGIC; - signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_79\ : STD_LOGIC; - signal I_AXI_DMA_INTRPT_n_21 : STD_LOGIC; - signal \I_DMA_REGISTER/different_delay\ : STD_LOGIC; - signal \I_DMA_REGISTER/different_thresh\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_73\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_74\ : STD_LOGIC; + signal \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_75\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.GEN_FOR_ASYNC_FLUSH_SOF.S2MM_PRM_UPDT_CDC_I_n_1\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.GEN_FOR_ASYNC_FLUSH_SOF.SOF_LATE_CDC_I_n_1\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.GEN_FOR_ASYNC_FLUSH_SOF.SOF_LATE_CDC_I_n_2\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_n_0\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg_n_0\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_10_n_0\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_11_n_0\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_12_n_0\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_13_n_0\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_4_n_0\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_8_n_0\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_9_n_0\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_3_n_0\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_4_n_0\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_5_n_0\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_6_n_0\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_3_n_0\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_4_n_0\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_5_n_0\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_6_n_0\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]_i_7_n_1\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]_i_7_n_2\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]_i_7_n_3\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[4]_i_2_n_0\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[4]_i_2_n_1\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[4]_i_2_n_2\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[4]_i_2_n_3\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[8]_i_2_n_0\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[8]_i_2_n_1\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[8]_i_2_n_2\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[8]_i_2_n_3\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_3\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_5\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_8\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_9\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_15\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_16\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_17\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_53\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_54\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_56\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_57\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_58\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_59\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_60\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I_n_16\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I_n_17\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I_n_20\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I_n_21\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_59\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_60\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_61\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_62\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_63\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_64\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_65\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_66\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_67\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_68\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_71\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_74\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_75\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_76\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_77\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_78\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_79\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_80\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_81\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_82\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_87\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_88\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_92\ : STD_LOGIC; + signal \GEN_SPRT_FOR_S2MM.S2MM_VID_CDC_I_n_5\ : STD_LOGIC; + signal I_AXI_DMA_INTRPT_n_39 : STD_LOGIC; + signal I_AXI_DMA_INTRPT_n_40 : STD_LOGIC; + signal \I_CMDSTS/p_12_out\ : STD_LOGIC; + signal \I_CMDSTS/p_9_out\ : STD_LOGIC; + signal \I_CMDSTS/s_axis_cmd_tvalid0\ : STD_LOGIC; + signal \I_DMA_REGISTER/dmacr_i\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \I_DMA_REGISTER/irqdelay_wren_i\ : STD_LOGIC; + signal \I_DMA_REGISTER/p_14_out\ : STD_LOGIC; + signal \I_DMA_REGISTER/p_15_out\ : STD_LOGIC; signal \I_DMA_REGISTER/reset_counts\ : STD_LOGIC; - signal I_PRMRY_DATAMOVER_n_41 : STD_LOGIC; - signal I_PRMRY_DATAMOVER_n_42 : STD_LOGIC; - signal I_PRMRY_DATAMOVER_n_43 : STD_LOGIC; - signal I_PRMRY_DATAMOVER_n_6 : STD_LOGIC; - signal I_RST_MODULE_n_13 : STD_LOGIC; - signal I_RST_MODULE_n_14 : STD_LOGIC; - signal I_RST_MODULE_n_15 : STD_LOGIC; + signal \I_DMA_REGISTER/reset_counts_11\ : STD_LOGIC; + signal I_PRMRY_DATAMOVER_n_191 : STD_LOGIC; + signal I_PRMRY_DATAMOVER_n_22 : STD_LOGIC; + signal I_PRMRY_DATAMOVER_n_23 : STD_LOGIC; + signal I_PRMRY_DATAMOVER_n_28 : STD_LOGIC; + signal I_PRMRY_DATAMOVER_n_29 : STD_LOGIC; + signal I_PRMRY_DATAMOVER_n_30 : STD_LOGIC; + signal I_PRMRY_DATAMOVER_n_32 : STD_LOGIC; + signal I_PRMRY_DATAMOVER_n_34 : STD_LOGIC; + signal I_PRMRY_DATAMOVER_n_35 : STD_LOGIC; + signal I_PRMRY_DATAMOVER_n_36 : STD_LOGIC; + signal I_PRMRY_DATAMOVER_n_37 : STD_LOGIC; + signal I_PRMRY_DATAMOVER_n_38 : STD_LOGIC; + signal I_PRMRY_DATAMOVER_n_39 : STD_LOGIC; signal I_RST_MODULE_n_16 : STD_LOGIC; - signal I_RST_MODULE_n_17 : STD_LOGIC; + signal I_RST_MODULE_n_19 : STD_LOGIC; + signal I_RST_MODULE_n_22 : STD_LOGIC; + signal I_RST_MODULE_n_25 : STD_LOGIC; + signal I_RST_MODULE_n_26 : STD_LOGIC; + signal I_RST_MODULE_n_27 : STD_LOGIC; + signal I_RST_MODULE_n_28 : STD_LOGIC; + signal I_RST_MODULE_n_29 : STD_LOGIC; + signal I_RST_MODULE_n_30 : STD_LOGIC; + signal I_RST_MODULE_n_31 : STD_LOGIC; + signal I_RST_MODULE_n_32 : STD_LOGIC; + signal I_RST_MODULE_n_33 : STD_LOGIC; + signal \I_SM/GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF/prmry_reset2\ : STD_LOGIC; + signal \I_SM/drop_fsync_d_pulse_gen_fsize_less_err_d1\ : STD_LOGIC; + signal \I_SM/fsize_mismatch_err_s1\ : STD_LOGIC; signal \I_STS_MNGR/datamover_idle\ : STD_LOGIC; + signal \I_STS_MNGR/datamover_idle_3\ : STD_LOGIC; + signal \VIDEO_REG_I/p_1_out\ : STD_LOGIC; signal all_lines_xfred : STD_LOGIC; signal ch1_delay_cnt_en : STD_LOGIC; - signal \ch1_delay_zero__6\ : STD_LOGIC; - signal ch1_disable_delay2_out : STD_LOGIC; - signal \ch1_ioc_irq_set_i__0\ : STD_LOGIC; + signal ch1_delay_zero : STD_LOGIC; + signal ch2_delay_cnt_en : STD_LOGIC; + signal ch2_delay_zero : STD_LOGIC; + signal ch2_irqthresh_decr_mask_sig : STD_LOGIC; signal cmnd_wr : STD_LOGIC; + signal cmnd_wr_5 : STD_LOGIC; + signal crnt_hsize : STD_LOGIC_VECTOR ( 15 downto 3 ); + signal d_tready_before_fsync : STD_LOGIC; + signal d_tready_before_fsync_clr_flag1 : STD_LOGIC; + signal d_tready_sof_late : STD_LOGIC; + signal delay_s2mm_fsync_core_till_mmap_done_flag : STD_LOGIC; signal dm2linebuf_mm2s_tdata : STD_LOGIC_VECTOR ( 31 downto 0 ); signal dm2linebuf_mm2s_tlast : STD_LOGIC; - signal dm2linebuf_mm2s_tvalid : STD_LOGIC; + signal dm2linebuf_s2mm_tready : STD_LOGIC; signal dma_err : STD_LOGIC; - signal fifo_full_i : STD_LOGIC; - signal \fifo_wren__0\ : STD_LOGIC; + signal dma_err_2 : STD_LOGIC; + signal dma_irq_mask_i : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal fifo_empty_i : STD_LOGIC; + signal fifo_rden : STD_LOGIC; signal initial_frame : STD_LOGIC; + signal initial_frame_0 : STD_LOGIC; + signal linebuf2dm_s2mm_tdata : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal linebuf2dm_s2mm_tlast : STD_LOGIC; signal \^m_axi_mm2s_arburst\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \^m_axi_mm2s_arlen\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^m_axi_mm2s_arlen\ : STD_LOGIC_VECTOR ( 4 downto 0 ); signal \^m_axi_mm2s_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^m_axi_s2mm_awburst\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^m_axi_s2mm_awlen\ : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \^m_axi_s2mm_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m_axis_s2mm_sts_tdata : STD_LOGIC_VECTOR ( 8 to 8 ); + signal m_axis_s2mm_sts_tready : STD_LOGIC; signal mask_fsync_out_i : STD_LOGIC; + signal mask_fsync_out_i_8 : STD_LOGIC; + signal minusOp : STD_LOGIC_VECTOR ( 12 downto 1 ); signal mm2s_axi2ip_rdaddr : STD_LOGIC_VECTOR ( 3 downto 2 ); - signal mm2s_axi2ip_wrce : STD_LOGIC_VECTOR ( 23 downto 0 ); + signal mm2s_axi2ip_wrce : STD_LOGIC_VECTOR ( 25 downto 0 ); signal mm2s_axi2ip_wrdata : STD_LOGIC_VECTOR ( 31 downto 0 ); signal mm2s_axis_resetn : STD_LOGIC; signal mm2s_dly_irq_set : STD_LOGIC; @@ -37820,46 +93265,125 @@ architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0_axi_vdma is signal mm2s_reg_module_hsize : STD_LOGIC_VECTOR ( 15 downto 0 ); signal mm2s_reg_module_stride : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \mm2s_reg_module_strt_addr[0]\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \mm2s_reg_module_strt_addr[1]\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \mm2s_reg_module_strt_addr[2]\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal mm2s_reg_module_vsize : STD_LOGIC_VECTOR ( 12 downto 0 ); - signal p_0_in : STD_LOGIC; + signal num_fstore_minus1 : STD_LOGIC_VECTOR ( 1 to 1 ); signal p_0_out : STD_LOGIC; signal p_10_out : STD_LOGIC; + signal p_11_out : STD_LOGIC; + signal p_13_out : STD_LOGIC; signal p_15_out : STD_LOGIC; signal p_17_out : STD_LOGIC; + signal p_19_in : STD_LOGIC; + signal p_1_in : STD_LOGIC_VECTOR ( 12 downto 0 ); signal p_1_out : STD_LOGIC; - signal p_23_out : STD_LOGIC; - signal p_2_in : STD_LOGIC_VECTOR ( 0 to 0 ); + signal p_24_out : STD_LOGIC; signal p_2_out : STD_LOGIC; - signal p_30_out : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal p_32_out : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal p_35_out : STD_LOGIC; + signal p_2_out_1 : STD_LOGIC; + signal p_31_out : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal p_33_out : STD_LOGIC_VECTOR ( 4 downto 0 ); signal p_36_out : STD_LOGIC; signal p_37_out : STD_LOGIC; - signal p_43_out : STD_LOGIC_VECTOR ( 0 to 0 ); - signal p_44_out : STD_LOGIC; + signal p_39_out : STD_LOGIC; + signal p_44_out : STD_LOGIC_VECTOR ( 2 downto 0 ); signal p_45_out : STD_LOGIC; signal p_46_out : STD_LOGIC; - signal p_48_out : STD_LOGIC_VECTOR ( 12 downto 0 ); - signal p_49_out : STD_LOGIC; + signal p_47_out : STD_LOGIC; + signal p_49_out : STD_LOGIC_VECTOR ( 12 downto 0 ); signal p_4_out : STD_LOGIC; - signal p_55_out : STD_LOGIC; - signal p_56_out : STD_LOGIC_VECTOR ( 63 downto 0 ); - signal p_57_out : STD_LOGIC; - signal p_64_out : STD_LOGIC; + signal p_4_out_10 : STD_LOGIC; + signal p_4_out_6 : STD_LOGIC; + signal p_50_out : STD_LOGIC; + signal p_56_out : STD_LOGIC; + signal p_57_out : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal p_58_out : STD_LOGIC; signal p_67_out : STD_LOGIC; - signal p_68_out : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal \p_6_out__1\ : STD_LOGIC; - signal p_75_out : STD_LOGIC; - signal p_76_out : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal p_77_out : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal p_78_out : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal p_6_out : STD_LOGIC; + signal p_70_out : STD_LOGIC; + signal p_71_out : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal p_77_out : STD_LOGIC; + signal p_78_out : STD_LOGIC; + signal p_79_out : STD_LOGIC_VECTOR ( 4 downto 0 ); signal p_7_out : STD_LOGIC; - signal p_8_out : STD_LOGIC; + signal p_80_out : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal p_81_out : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal p_82_out : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal p_83_out : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal p_84_out : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal p_92_out : STD_LOGIC; + signal p_94_out : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal p_96_out : STD_LOGIC; + signal p_in_d1_cdc_from : STD_LOGIC; + signal prmry_in_xored : STD_LOGIC; signal prmtr_update_complete : STD_LOGIC; + signal prmtr_update_complete_4 : STD_LOGIC; + signal run_stop_reg : STD_LOGIC; + signal s2mm_axi2ip_wrce : STD_LOGIC_VECTOR ( 45 downto 10 ); + signal s2mm_axi2ip_wrdata : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s2mm_axis_resetn : STD_LOGIC; + signal s2mm_cdc2dmac_fsync : STD_LOGIC; + signal s2mm_chnl_current_frame : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal s2mm_crnt_vsize : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal s2mm_dly_irq_set : STD_LOGIC; + signal s2mm_dm_prmry_resetn : STD_LOGIC; + signal s2mm_dma_interr_set_minus_frame_errors : STD_LOGIC; + signal s2mm_dmacr : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s2mm_dmasr : STD_LOGIC_VECTOR ( 0 to 0 ); + signal s2mm_dmasr_halted_s : STD_LOGIC; + signal s2mm_frame_number : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal s2mm_fsize_less_err_flag_10 : STD_LOGIC; + signal s2mm_fsize_mismatch_err : STD_LOGIC; + signal s2mm_fsize_more_or_sof_late : STD_LOGIC; + signal s2mm_fsize_more_or_sof_late_s : STD_LOGIC; + signal s2mm_fsync_core : STD_LOGIC; + signal s2mm_fsync_out_i : STD_LOGIC; + signal s2mm_fsync_out_m_i : STD_LOGIC; + signal s2mm_ftchcmdsts_idle : STD_LOGIC; + signal s2mm_genlock_pair_frame : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal s2mm_halt : STD_LOGIC; + signal s2mm_halt_cmplt : STD_LOGIC; + signal s2mm_ioc_irq_set : STD_LOGIC; + signal s2mm_ip2axi_introut : STD_LOGIC; + signal s2mm_irqdelay_status : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal s2mm_irqthresh_status : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal s2mm_lsize_mismatch_err : STD_LOGIC; + signal s2mm_lsize_more_mismatch_err : STD_LOGIC; + signal s2mm_m_frame_ptr_out : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s2mm_packet_sof : STD_LOGIC; + signal s2mm_prmry_resetn : STD_LOGIC; + signal s2mm_reg_module_hsize : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal s2mm_reg_module_stride : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \s2mm_reg_module_strt_addr[0]\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \s2mm_reg_module_strt_addr[1]\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \s2mm_reg_module_strt_addr[2]\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal s2mm_reg_module_vsize : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal s2mm_s_frame_ptr_in : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal s2mm_soft_reset : STD_LOGIC; + signal s2mm_stop : STD_LOGIC; + signal s2mm_tstvect_fsync : STD_LOGIC; + signal s2mm_tuser_to_fsync_out : STD_LOGIC; + signal s2mm_valid_frame_sync : STD_LOGIC; + signal s2mm_valid_frame_sync_cmb : STD_LOGIC; + signal s2mm_valid_video_prmtrs : STD_LOGIC; signal s_axi_lite_resetn : STD_LOGIC; + signal s_axis_fifo_ainit_nosync : STD_LOGIC; + signal s_axis_s2mm_cmd_tdata : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal s_axis_s2mm_cmd_tvalid : STD_LOGIC; + signal s_axis_s2mm_tuser_d1 : STD_LOGIC; signal s_valid0 : STD_LOGIC; - signal sof_flag : STD_LOGIC; - signal stop_i : STD_LOGIC; + signal s_valid0_9 : STD_LOGIC; + signal sig_reset_reg : STD_LOGIC; + signal strm_all_lines_rcvd_no_dwidth : STD_LOGIC; + signal strm_not_finished_no_dwidth : STD_LOGIC; + signal vsize_counter_no_dwidth : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal \NLW_GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_DOC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 ); + signal \NLW_GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute METHODOLOGY_DRC_VIOS : string; + attribute METHODOLOGY_DRC_VIOS of \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5\ : label is ""; + attribute METHODOLOGY_DRC_VIOS of \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10\ : label is ""; begin axi_vdma_tstvec(63) <= \\; axi_vdma_tstvec(62) <= \\; @@ -37934,141 +93458,34 @@ begin m_axi_mm2s_arlen(7) <= \\; m_axi_mm2s_arlen(6) <= \\; m_axi_mm2s_arlen(5) <= \\; - m_axi_mm2s_arlen(4) <= \\; - m_axi_mm2s_arlen(3 downto 0) <= \^m_axi_mm2s_arlen\(3 downto 0); + m_axi_mm2s_arlen(4 downto 0) <= \^m_axi_mm2s_arlen\(4 downto 0); m_axi_mm2s_arprot(2) <= \\; m_axi_mm2s_arprot(1) <= \\; m_axi_mm2s_arprot(0) <= \\; m_axi_mm2s_arsize(2) <= \\; m_axi_mm2s_arsize(1 downto 0) <= \^m_axi_mm2s_arsize\(1 downto 0); - m_axi_s2mm_awaddr(31) <= \\; - m_axi_s2mm_awaddr(30) <= \\; - m_axi_s2mm_awaddr(29) <= \\; - m_axi_s2mm_awaddr(28) <= \\; - m_axi_s2mm_awaddr(27) <= \\; - m_axi_s2mm_awaddr(26) <= \\; - m_axi_s2mm_awaddr(25) <= \\; - m_axi_s2mm_awaddr(24) <= \\; - m_axi_s2mm_awaddr(23) <= \\; - m_axi_s2mm_awaddr(22) <= \\; - m_axi_s2mm_awaddr(21) <= \\; - m_axi_s2mm_awaddr(20) <= \\; - m_axi_s2mm_awaddr(19) <= \\; - m_axi_s2mm_awaddr(18) <= \\; - m_axi_s2mm_awaddr(17) <= \\; - m_axi_s2mm_awaddr(16) <= \\; - m_axi_s2mm_awaddr(15) <= \\; - m_axi_s2mm_awaddr(14) <= \\; - m_axi_s2mm_awaddr(13) <= \\; - m_axi_s2mm_awaddr(12) <= \\; - m_axi_s2mm_awaddr(11) <= \\; - m_axi_s2mm_awaddr(10) <= \\; - m_axi_s2mm_awaddr(9) <= \\; - m_axi_s2mm_awaddr(8) <= \\; - m_axi_s2mm_awaddr(7) <= \\; - m_axi_s2mm_awaddr(6) <= \\; - m_axi_s2mm_awaddr(5) <= \\; - m_axi_s2mm_awaddr(4) <= \\; - m_axi_s2mm_awaddr(3) <= \\; - m_axi_s2mm_awaddr(2) <= \\; - m_axi_s2mm_awaddr(1) <= \\; - m_axi_s2mm_awaddr(0) <= \\; m_axi_s2mm_awburst(1) <= \\; - m_axi_s2mm_awburst(0) <= \\; + m_axi_s2mm_awburst(0) <= \^m_axi_s2mm_awburst\(0); m_axi_s2mm_awcache(3) <= \\; m_axi_s2mm_awcache(2) <= \\; - m_axi_s2mm_awcache(1) <= \\; - m_axi_s2mm_awcache(0) <= \\; + m_axi_s2mm_awcache(1) <= \\; + m_axi_s2mm_awcache(0) <= \\; m_axi_s2mm_awlen(7) <= \\; m_axi_s2mm_awlen(6) <= \\; - m_axi_s2mm_awlen(5) <= \\; - m_axi_s2mm_awlen(4) <= \\; - m_axi_s2mm_awlen(3) <= \\; - m_axi_s2mm_awlen(2) <= \\; - m_axi_s2mm_awlen(1) <= \\; - m_axi_s2mm_awlen(0) <= \\; + m_axi_s2mm_awlen(5 downto 0) <= \^m_axi_s2mm_awlen\(5 downto 0); m_axi_s2mm_awprot(2) <= \\; m_axi_s2mm_awprot(1) <= \\; m_axi_s2mm_awprot(0) <= \\; m_axi_s2mm_awsize(2) <= \\; - m_axi_s2mm_awsize(1) <= \\; - m_axi_s2mm_awsize(0) <= \\; - m_axi_s2mm_awvalid <= \\; - m_axi_s2mm_bready <= \\; - m_axi_s2mm_wdata(63) <= \\; - m_axi_s2mm_wdata(62) <= \\; - m_axi_s2mm_wdata(61) <= \\; - m_axi_s2mm_wdata(60) <= \\; - m_axi_s2mm_wdata(59) <= \\; - m_axi_s2mm_wdata(58) <= \\; - m_axi_s2mm_wdata(57) <= \\; - m_axi_s2mm_wdata(56) <= \\; - m_axi_s2mm_wdata(55) <= \\; - m_axi_s2mm_wdata(54) <= \\; - m_axi_s2mm_wdata(53) <= \\; - m_axi_s2mm_wdata(52) <= \\; - m_axi_s2mm_wdata(51) <= \\; - m_axi_s2mm_wdata(50) <= \\; - m_axi_s2mm_wdata(49) <= \\; - m_axi_s2mm_wdata(48) <= \\; - m_axi_s2mm_wdata(47) <= \\; - m_axi_s2mm_wdata(46) <= \\; - m_axi_s2mm_wdata(45) <= \\; - m_axi_s2mm_wdata(44) <= \\; - m_axi_s2mm_wdata(43) <= \\; - m_axi_s2mm_wdata(42) <= \\; - m_axi_s2mm_wdata(41) <= \\; - m_axi_s2mm_wdata(40) <= \\; - m_axi_s2mm_wdata(39) <= \\; - m_axi_s2mm_wdata(38) <= \\; - m_axi_s2mm_wdata(37) <= \\; - m_axi_s2mm_wdata(36) <= \\; - m_axi_s2mm_wdata(35) <= \\; - m_axi_s2mm_wdata(34) <= \\; - m_axi_s2mm_wdata(33) <= \\; - m_axi_s2mm_wdata(32) <= \\; - m_axi_s2mm_wdata(31) <= \\; - m_axi_s2mm_wdata(30) <= \\; - m_axi_s2mm_wdata(29) <= \\; - m_axi_s2mm_wdata(28) <= \\; - m_axi_s2mm_wdata(27) <= \\; - m_axi_s2mm_wdata(26) <= \\; - m_axi_s2mm_wdata(25) <= \\; - m_axi_s2mm_wdata(24) <= \\; - m_axi_s2mm_wdata(23) <= \\; - m_axi_s2mm_wdata(22) <= \\; - m_axi_s2mm_wdata(21) <= \\; - m_axi_s2mm_wdata(20) <= \\; - m_axi_s2mm_wdata(19) <= \\; - m_axi_s2mm_wdata(18) <= \\; - m_axi_s2mm_wdata(17) <= \\; - m_axi_s2mm_wdata(16) <= \\; - m_axi_s2mm_wdata(15) <= \\; - m_axi_s2mm_wdata(14) <= \\; - m_axi_s2mm_wdata(13) <= \\; - m_axi_s2mm_wdata(12) <= \\; - m_axi_s2mm_wdata(11) <= \\; - m_axi_s2mm_wdata(10) <= \\; - m_axi_s2mm_wdata(9) <= \\; - m_axi_s2mm_wdata(8) <= \\; - m_axi_s2mm_wdata(7) <= \\; - m_axi_s2mm_wdata(6) <= \\; - m_axi_s2mm_wdata(5) <= \\; - m_axi_s2mm_wdata(4) <= \\; - m_axi_s2mm_wdata(3) <= \\; - m_axi_s2mm_wdata(2) <= \\; - m_axi_s2mm_wdata(1) <= \\; - m_axi_s2mm_wdata(0) <= \\; - m_axi_s2mm_wlast <= \\; - m_axi_s2mm_wstrb(7) <= \\; - m_axi_s2mm_wstrb(6) <= \\; - m_axi_s2mm_wstrb(5) <= \\; - m_axi_s2mm_wstrb(4) <= \\; - m_axi_s2mm_wstrb(3) <= \\; - m_axi_s2mm_wstrb(2) <= \\; - m_axi_s2mm_wstrb(1) <= \\; - m_axi_s2mm_wstrb(0) <= \\; - m_axi_s2mm_wvalid <= \\; + m_axi_s2mm_awsize(1 downto 0) <= \^m_axi_s2mm_awsize\(1 downto 0); + m_axi_s2mm_wstrb(7) <= \\; + m_axi_s2mm_wstrb(6) <= \\; + m_axi_s2mm_wstrb(5) <= \\; + m_axi_s2mm_wstrb(4) <= \\; + m_axi_s2mm_wstrb(3) <= \\; + m_axi_s2mm_wstrb(2) <= \\; + m_axi_s2mm_wstrb(1) <= \\; + m_axi_s2mm_wstrb(0) <= \\; m_axi_sg_araddr(31) <= \\; m_axi_sg_araddr(30) <= \\; m_axi_sg_araddr(29) <= \\; @@ -38134,109 +93551,207 @@ begin mm2s_prmtr_update <= \\; s2mm_buffer_almost_full <= \\; s2mm_buffer_full <= \\; - s2mm_frame_ptr_out(5) <= \\; - s2mm_frame_ptr_out(4) <= \\; - s2mm_frame_ptr_out(3) <= \\; - s2mm_frame_ptr_out(2) <= \\; - s2mm_frame_ptr_out(1) <= \\; - s2mm_frame_ptr_out(0) <= \\; s2mm_fsync_out <= \\; - s2mm_introut <= \\; s2mm_prmry_reset_out_n <= \\; s2mm_prmtr_update <= \\; s_axi_lite_bresp(1) <= \\; s_axi_lite_bresp(0) <= \\; s_axi_lite_rresp(1) <= \\; s_axi_lite_rresp(0) <= \\; - s_axis_s2mm_tready <= \\; AXI_LITE_REG_INTERFACE_I: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_if port map ( D(31 downto 0) => mm2s_axi2ip_wrdata(31 downto 0), - \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg\ => AXI_LITE_REG_INTERFACE_I_n_40, - \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]\(0) => AXI_LITE_REG_INTERFACE_I_n_49, - \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg\ => AXI_LITE_REG_INTERFACE_I_n_48, - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[7]\(7 downto 0) => mm2s_irqdelay_status(7 downto 0), + \DMA_IRQ_MASK_GEN.dma_irq_mask_i_reg[3]\(3 downto 0) => dma_irq_mask_i(3 downto 0), + \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(15 downto 0) => s2mm_reg_module_stride(15 downto 0), + \DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]\(4 downto 0) => s2mm_chnl_current_frame(4 downto 0), + \DYNAMIC_MASTER_MODE_FRAME_CNT.genlock_pair_frame_reg[4]\(4 downto 0) => s2mm_genlock_pair_frame(4 downto 0), + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31]\(31 downto 0) => s2mm_axi2ip_wrdata(31 downto 0), + \ENABLE_DMACR_DELAY_CNTR.dmacr_i_reg[31]_0\ => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_81\, + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]\(0) => AXI_LITE_REG_INTERFACE_I_n_81, + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[21]_0\(0) => AXI_LITE_REG_INTERFACE_I_n_128, + \ENABLE_DMACR_FRM_CNTR.dmacr_i_reg[23]\ => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_82\, + \GEN_FOR_FLUSH.fsize_err_reg\ => AXI_LITE_REG_INTERFACE_I_n_166, + \GEN_FOR_FLUSH.fsize_err_reg_0\ => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_62\, + \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg\ => AXI_LITE_REG_INTERFACE_I_n_168, + \GEN_FOR_FLUSH.s2mm_fsize_more_or_sof_late_bit_reg_0\ => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_64\, + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_ioc_irq_set_i_reg\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_74\, \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\(7 downto 0) => mm2s_irqthresh_status(7 downto 0), - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[5]\(31 downto 0) => p_78_out(31 downto 0), - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[0]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_79\, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[10]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_166\, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[11]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_167\, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[12]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_168\, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[13]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_169\, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[14]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_170\, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[15]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_171\, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[1]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_157\, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[2]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_158\, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(15 downto 0) => \mm2s_reg_module_strt_addr[0]\(31 downto 16), - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[3]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_159\, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[4]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_160\, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[5]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_161\, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[6]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_162\, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[7]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_163\, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[8]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_164\, - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[9]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_165\, - \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]\(4 downto 0) => p_30_out(4 downto 0), - \MM2S_ERR_FOR_IRQ.frm_store_i_reg[4]\(4 downto 0) => p_76_out(4 downto 0), - Q(4 downto 0) => p_77_out(4 downto 0), - SR(0) => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.MM2S_INTRPT_CROSSING_I/scndry_reset2\, - different_delay => \I_DMA_REGISTER/different_delay\, - different_thresh => \I_DMA_REGISTER/different_thresh\, - dly_irq_reg => AXI_LITE_REG_INTERFACE_I_n_84, - dly_irq_reg_0 => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_60\, - dma_decerr_reg => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_64\, - dma_interr_reg => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_58\, - dma_slverr_reg => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_63\, - err_irq_reg => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_76\, - in0(31) => AXI_LITE_REG_INTERFACE_I_n_50, - in0(30) => AXI_LITE_REG_INTERFACE_I_n_51, - in0(29) => AXI_LITE_REG_INTERFACE_I_n_52, - in0(28) => AXI_LITE_REG_INTERFACE_I_n_53, - in0(27) => AXI_LITE_REG_INTERFACE_I_n_54, - in0(26) => AXI_LITE_REG_INTERFACE_I_n_55, - in0(25) => AXI_LITE_REG_INTERFACE_I_n_56, - in0(24) => AXI_LITE_REG_INTERFACE_I_n_57, - in0(23) => AXI_LITE_REG_INTERFACE_I_n_58, - in0(22) => AXI_LITE_REG_INTERFACE_I_n_59, - in0(21) => AXI_LITE_REG_INTERFACE_I_n_60, - in0(20) => AXI_LITE_REG_INTERFACE_I_n_61, - in0(19) => AXI_LITE_REG_INTERFACE_I_n_62, - in0(18) => AXI_LITE_REG_INTERFACE_I_n_63, - in0(17) => AXI_LITE_REG_INTERFACE_I_n_64, - in0(16) => AXI_LITE_REG_INTERFACE_I_n_65, - in0(15) => AXI_LITE_REG_INTERFACE_I_n_66, - in0(14) => AXI_LITE_REG_INTERFACE_I_n_67, - in0(13) => AXI_LITE_REG_INTERFACE_I_n_68, - in0(12) => AXI_LITE_REG_INTERFACE_I_n_69, - in0(11) => AXI_LITE_REG_INTERFACE_I_n_70, - in0(10) => AXI_LITE_REG_INTERFACE_I_n_71, - in0(9) => AXI_LITE_REG_INTERFACE_I_n_72, - in0(8) => AXI_LITE_REG_INTERFACE_I_n_73, - in0(7) => AXI_LITE_REG_INTERFACE_I_n_74, - in0(6) => AXI_LITE_REG_INTERFACE_I_n_75, - in0(5) => AXI_LITE_REG_INTERFACE_I_n_76, - in0(4) => AXI_LITE_REG_INTERFACE_I_n_77, - in0(3) => AXI_LITE_REG_INTERFACE_I_n_78, - in0(2) => AXI_LITE_REG_INTERFACE_I_n_79, - in0(1) => AXI_LITE_REG_INTERFACE_I_n_80, - in0(0) => AXI_LITE_REG_INTERFACE_I_n_81, - ioc_irq_reg => AXI_LITE_REG_INTERFACE_I_n_83, - ioc_irq_reg_0 => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_59\, + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]\(7 downto 0) => s2mm_irqthresh_status(7 downto 0), + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]\ => AXI_LITE_REG_INTERFACE_I_n_113, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]\ => AXI_LITE_REG_INTERFACE_I_n_111, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]\ => AXI_LITE_REG_INTERFACE_I_n_114, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]_0\ => AXI_LITE_REG_INTERFACE_I_n_115, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[31]\ => AXI_LITE_REG_INTERFACE_I_n_112, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(31) => AXI_LITE_REG_INTERFACE_I_n_129, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(30) => AXI_LITE_REG_INTERFACE_I_n_130, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(29) => AXI_LITE_REG_INTERFACE_I_n_131, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(28) => AXI_LITE_REG_INTERFACE_I_n_132, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(27) => AXI_LITE_REG_INTERFACE_I_n_133, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(26) => AXI_LITE_REG_INTERFACE_I_n_134, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(25) => AXI_LITE_REG_INTERFACE_I_n_135, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(24) => AXI_LITE_REG_INTERFACE_I_n_136, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(23) => AXI_LITE_REG_INTERFACE_I_n_137, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(22) => AXI_LITE_REG_INTERFACE_I_n_138, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(21) => AXI_LITE_REG_INTERFACE_I_n_139, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(20) => AXI_LITE_REG_INTERFACE_I_n_140, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(19) => AXI_LITE_REG_INTERFACE_I_n_141, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(18) => AXI_LITE_REG_INTERFACE_I_n_142, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(17) => AXI_LITE_REG_INTERFACE_I_n_143, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(16) => AXI_LITE_REG_INTERFACE_I_n_144, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(15) => AXI_LITE_REG_INTERFACE_I_n_145, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(14) => AXI_LITE_REG_INTERFACE_I_n_146, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(13) => AXI_LITE_REG_INTERFACE_I_n_147, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(12) => AXI_LITE_REG_INTERFACE_I_n_148, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(11) => AXI_LITE_REG_INTERFACE_I_n_149, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(10) => AXI_LITE_REG_INTERFACE_I_n_150, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(9) => AXI_LITE_REG_INTERFACE_I_n_151, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(8) => AXI_LITE_REG_INTERFACE_I_n_152, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(7) => AXI_LITE_REG_INTERFACE_I_n_153, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(6) => AXI_LITE_REG_INTERFACE_I_n_154, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(5) => AXI_LITE_REG_INTERFACE_I_n_155, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(4) => AXI_LITE_REG_INTERFACE_I_n_156, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(3) => AXI_LITE_REG_INTERFACE_I_n_157, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(2) => AXI_LITE_REG_INTERFACE_I_n_158, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(1) => AXI_LITE_REG_INTERFACE_I_n_159, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_ip2axi_rddata_d1_reg[31]\(0) => AXI_LITE_REG_INTERFACE_I_n_160, + \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14]\(6) => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_74\, + \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14]\(5) => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_75\, + \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14]\(4) => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_76\, + \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14]\(3) => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_77\, + \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14]\(2) => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_78\, + \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14]\(1) => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_79\, + \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[14]\(0) => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_80\, + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(18 downto 0) => \mm2s_reg_module_strt_addr[0]\(31 downto 13), + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_0\(31 downto 0) => \s2mm_reg_module_strt_addr[0]\(31 downto 0), + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]_1\(31 downto 0) => p_81_out(31 downto 0), + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(28 downto 13) => \mm2s_reg_module_strt_addr[1]\(31 downto 16), + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(12 downto 1) => \mm2s_reg_module_strt_addr[1]\(14 downto 3), + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(0) => \mm2s_reg_module_strt_addr[1]\(0), + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_0\(31 downto 0) => \s2mm_reg_module_strt_addr[1]\(31 downto 0), + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]_1\(31 downto 0) => p_84_out(31 downto 0), + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(28 downto 13) => \mm2s_reg_module_strt_addr[2]\(31 downto 16), + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(12 downto 1) => \mm2s_reg_module_strt_addr[2]\(14 downto 3), + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(0) => \mm2s_reg_module_strt_addr[2]\(0), + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]_0\(31 downto 0) => \s2mm_reg_module_strt_addr[2]\(31 downto 0), + \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]\(4 downto 0) => p_31_out(4 downto 0), + \MM2S_ERR_FOR_IRQ.frm_store_i_reg[4]\(4 downto 0) => p_79_out(4 downto 0), + \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(2 downto 0) => mm2s_reg_module_stride(15 downto 13), + \M_GEN_DMACR_REGISTER.dmacr_i_reg[14]\(4) => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_67\, + \M_GEN_DMACR_REGISTER.dmacr_i_reg[14]\(3) => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_68\, + \M_GEN_DMACR_REGISTER.dmacr_i_reg[14]\(2) => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_69\, + \M_GEN_DMACR_REGISTER.dmacr_i_reg[14]\(1) => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_70\, + \M_GEN_DMACR_REGISTER.dmacr_i_reg[14]\(0) => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_71\, + Q(4 downto 0) => p_80_out(4 downto 0), + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[4]\(4 downto 0) => p_82_out(4 downto 0), + SR(0) => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.S2MM_INTRPT_CROSSING_I/scndry_reset2\, + ch1_dly_irq_set => mm2s_dly_irq_set, + ch1_irqdelay_status(7 downto 0) => mm2s_irqdelay_status(7 downto 0), + ch2_dly_irq_set => s2mm_dly_irq_set, + ch2_irqdelay_status(7 downto 0) => s2mm_irqdelay_status(7 downto 0), + dly_irq_reg => AXI_LITE_REG_INTERFACE_I_n_164, + dly_irq_reg_0 => AXI_LITE_REG_INTERFACE_I_n_170, + dly_irq_reg_1 => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_58\, + dly_irq_reg_2 => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_66\, + dma_decerr_reg => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_56\, + dma_decerr_reg_0 => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_61\, + dma_interr_reg => AXI_LITE_REG_INTERFACE_I_n_165, + dma_interr_reg_0 => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_54\, + dma_interr_reg_1 => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_59\, + dma_slverr_reg => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_55\, + dma_slverr_reg_0 => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_60\, + dmacr_i(0) => \I_DMA_REGISTER/dmacr_i\(0), + err_irq_reg => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_73\, + err_irq_reg_0 => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_87\, + fsize_mismatch_err => s2mm_fsize_mismatch_err, + in0(28) => AXI_LITE_REG_INTERFACE_I_n_82, + in0(27) => AXI_LITE_REG_INTERFACE_I_n_83, + in0(26) => AXI_LITE_REG_INTERFACE_I_n_84, + in0(25) => AXI_LITE_REG_INTERFACE_I_n_85, + in0(24) => AXI_LITE_REG_INTERFACE_I_n_86, + in0(23) => AXI_LITE_REG_INTERFACE_I_n_87, + in0(22) => AXI_LITE_REG_INTERFACE_I_n_88, + in0(21) => AXI_LITE_REG_INTERFACE_I_n_89, + in0(20) => AXI_LITE_REG_INTERFACE_I_n_90, + in0(19) => AXI_LITE_REG_INTERFACE_I_n_91, + in0(18) => AXI_LITE_REG_INTERFACE_I_n_92, + in0(17) => AXI_LITE_REG_INTERFACE_I_n_93, + in0(16) => AXI_LITE_REG_INTERFACE_I_n_94, + in0(15) => AXI_LITE_REG_INTERFACE_I_n_95, + in0(14) => AXI_LITE_REG_INTERFACE_I_n_96, + in0(13) => AXI_LITE_REG_INTERFACE_I_n_97, + in0(12) => AXI_LITE_REG_INTERFACE_I_n_98, + in0(11) => AXI_LITE_REG_INTERFACE_I_n_99, + in0(10) => AXI_LITE_REG_INTERFACE_I_n_100, + in0(9) => AXI_LITE_REG_INTERFACE_I_n_101, + in0(8) => AXI_LITE_REG_INTERFACE_I_n_102, + in0(7) => AXI_LITE_REG_INTERFACE_I_n_103, + in0(6) => AXI_LITE_REG_INTERFACE_I_n_104, + in0(5) => AXI_LITE_REG_INTERFACE_I_n_105, + in0(4) => AXI_LITE_REG_INTERFACE_I_n_106, + in0(3) => AXI_LITE_REG_INTERFACE_I_n_107, + in0(2) => AXI_LITE_REG_INTERFACE_I_n_108, + in0(1) => AXI_LITE_REG_INTERFACE_I_n_109, + in0(0) => AXI_LITE_REG_INTERFACE_I_n_110, + ioc_irq_reg => AXI_LITE_REG_INTERFACE_I_n_163, + ioc_irq_reg_0 => AXI_LITE_REG_INTERFACE_I_n_169, + ioc_irq_reg_1 => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_57\, + ioc_irq_reg_2 => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_65\, + lsize_err_reg => AXI_LITE_REG_INTERFACE_I_n_167, + lsize_err_reg_0 => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_63\, + lsize_mismatch_err => s2mm_lsize_mismatch_err, + lsize_more_err_reg => AXI_LITE_REG_INTERFACE_I_n_171, + lsize_more_err_reg_0 => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_67\, + lsize_more_mismatch_err => s2mm_lsize_more_mismatch_err, m_axi_mm2s_aclk => m_axi_mm2s_aclk, - mm2s_axi2ip_wrce(6 downto 3) => mm2s_axi2ip_wrce(23 downto 20), + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + mm2s_axi2ip_wrce(8 downto 3) => mm2s_axi2ip_wrce(25 downto 20), mm2s_axi2ip_wrce(2) => mm2s_axi2ip_wrce(10), mm2s_axi2ip_wrce(1 downto 0) => mm2s_axi2ip_wrce(1 downto 0), - mm2s_dly_irq_set => mm2s_dly_irq_set, mm2s_introut => mm2s_introut, mm2s_ioc_irq_set => mm2s_ioc_irq_set, + mm2s_prmry_resetn => mm2s_prmry_resetn, \out\(1 downto 0) => mm2s_axi2ip_rdaddr(3 downto 2), - p_67_out => p_67_out, - p_68_out(25 downto 6) => p_68_out(31 downto 12), - p_68_out(5 downto 3) => p_68_out(6 downto 4), - p_68_out(2 downto 0) => p_68_out(2 downto 0), - p_75_out => p_75_out, + p_14_out => \I_DMA_REGISTER/p_14_out\, + p_15_out => \I_DMA_REGISTER/p_15_out\, + p_70_out => p_70_out, + p_71_out(17 downto 2) => p_71_out(31 downto 16), + p_71_out(1) => p_71_out(4), + p_71_out(0) => p_71_out(0), + p_78_out => p_78_out, prmry_reset2 => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.MM2S_INTRPT_CROSSING_I/prmry_reset2\, - prmry_resetn_i_reg => mm2s_prmry_resetn, - prmtr_updt_complete_i_reg => AXI_LITE_REG_INTERFACE_I_n_82, + prmry_reset2_0 => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.S2MM_INTRPT_CROSSING_I/prmry_reset2\, + prmtr_updt_complete_i_reg => AXI_LITE_REG_INTERFACE_I_n_161, + prmtr_updt_complete_i_reg_0 => AXI_LITE_REG_INTERFACE_I_n_162, + \ptr_ref_i_reg[4]\(4 downto 0) => p_83_out(4 downto 0), + \reg_module_hsize_reg[0]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_75\, + \reg_module_hsize_reg[10]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_224\, + \reg_module_hsize_reg[11]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_225\, + \reg_module_hsize_reg[12]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_226\, + \reg_module_hsize_reg[15]\(2 downto 0) => mm2s_reg_module_hsize(15 downto 13), + \reg_module_hsize_reg[15]_0\(15 downto 0) => s2mm_reg_module_hsize(15 downto 0), + \reg_module_hsize_reg[3]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_217\, + \reg_module_hsize_reg[4]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_218\, + \reg_module_hsize_reg[5]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_219\, + \reg_module_hsize_reg[6]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_220\, + \reg_module_hsize_reg[7]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_221\, + \reg_module_hsize_reg[8]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_222\, + \reg_module_hsize_reg[9]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_223\, + \reg_module_vsize_reg[12]\(12 downto 0) => s2mm_reg_module_vsize(12 downto 0), + s2mm_axi2ip_wrce(9 downto 4) => s2mm_axi2ip_wrce(45 downto 40), + s2mm_axi2ip_wrce(3) => s2mm_axi2ip_wrce(15), + s2mm_axi2ip_wrce(2 downto 1) => s2mm_axi2ip_wrce(13 downto 12), + s2mm_axi2ip_wrce(0) => s2mm_axi2ip_wrce(10), + s2mm_dma_interr_set_minus_frame_errors => s2mm_dma_interr_set_minus_frame_errors, + s2mm_dmacr(22 downto 6) => s2mm_dmacr(31 downto 15), + s2mm_dmacr(5 downto 2) => s2mm_dmacr(6 downto 3), + s2mm_dmacr(1 downto 0) => s2mm_dmacr(1 downto 0), + s2mm_dmasr(0) => s2mm_dmasr(0), + s2mm_fsize_more_or_sof_late => s2mm_fsize_more_or_sof_late, + s2mm_introut => s2mm_introut, + s2mm_ioc_irq_set => s2mm_ioc_irq_set, + s2mm_ip2axi_introut => s2mm_ip2axi_introut, + s2mm_prmry_resetn => s2mm_prmry_resetn, + s2mm_soft_reset => s2mm_soft_reset, s_axi_lite_aclk => s_axi_lite_aclk, s_axi_lite_araddr(5 downto 0) => s_axi_lite_araddr(7 downto 2), s_axi_lite_arready => s_axi_lite_arready, @@ -38252,116 +93767,173 @@ AXI_LITE_REG_INTERFACE_I: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_if s_axi_lite_rvalid => s_axi_lite_rvalid, s_axi_lite_wdata(31 downto 0) => s_axi_lite_wdata(31 downto 0), s_axi_lite_wready => s_axi_lite_wready, - s_axi_lite_wvalid => s_axi_lite_wvalid + s_axi_lite_wvalid => s_axi_lite_wvalid, + stop => p_36_out + ); +\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 3) => B"00", + ADDRA(2 downto 0) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_0_out\(2 downto 0), + ADDRB(4 downto 3) => B"00", + ADDRB(2 downto 0) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_0_out\(2 downto 0), + ADDRC(4 downto 3) => B"00", + ADDRC(2 downto 0) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_0_out\(2 downto 0), + ADDRD(4 downto 3) => B"00", + ADDRD(2 downto 0) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_11_out\(2 downto 0), + DIA(1 downto 0) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_byte_cntr\(1 downto 0), + DIB(1 downto 0) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_byte_cntr\(3 downto 2), + DIC(1 downto 0) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_byte_cntr\(5 downto 4), + DID(1 downto 0) => B"00", + DOA(1) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_0\, + DOA(0) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_1\, + DOB(1) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_2\, + DOB(0) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_3\, + DOC(1) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_4\, + DOC(0) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_5\, + DOD(1 downto 0) => \NLW_GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_DOD_UNCONNECTED\(1 downto 0), + WCLK => m_axi_s2mm_aclk, + WE => I_PRMRY_DATAMOVER_n_39 + ); +\GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 3) => B"00", + ADDRA(2 downto 0) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_0_out\(2 downto 0), + ADDRB(4 downto 3) => B"00", + ADDRB(2 downto 0) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_0_out\(2 downto 0), + ADDRC(4 downto 3) => B"00", + ADDRC(2 downto 0) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_0_out\(2 downto 0), + ADDRD(4 downto 3) => B"00", + ADDRD(2 downto 0) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_11_out\(2 downto 0), + DIA(1 downto 0) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_byte_cntr\(7 downto 6), + DIB(1) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_dre2ibtt_tlast_reg\, + DIB(0) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_byte_cntr\(8), + DIC(1) => '0', + DIC(0) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_dre2ibtt_eop_reg\, + DID(1 downto 0) => B"00", + DOA(1) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_n_0\, + DOA(0) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_n_1\, + DOB(1) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_n_2\, + DOB(0) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_n_3\, + DOC(1) => \NLW_GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_DOC_UNCONNECTED\(1), + DOC(0) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_n_5\, + DOD(1 downto 0) => \NLW_GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_DOD_UNCONNECTED\(1 downto 0), + WCLK => m_axi_s2mm_aclk, + WE => I_PRMRY_DATAMOVER_n_39 ); \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_mngr port map ( D(0) => mm2s_axi2ip_wrdata(4), - E(0) => I_PRMRY_DATAMOVER_n_6, - \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg\ => \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_8\, - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg\ => \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_34\, - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4]\(4 downto 0) => p_30_out(4 downto 0), - \GEN_NUM_FSTORES_1.reg_module_start_address1_i_reg[31]\(31 downto 0) => \mm2s_reg_module_strt_addr[0]\(31 downto 0), - \INFERRED_GEN.cnt_i_reg[1]\ => \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_38\, - \INFERRED_GEN.cnt_i_reg[2]\ => I_PRMRY_DATAMOVER_n_43, - \INFERRED_GEN.cnt_i_reg[2]_0\ => I_PRMRY_DATAMOVER_n_42, - \INFERRED_GEN.cnt_i_reg[2]_1\ => I_PRMRY_DATAMOVER_n_41, + E(0) => I_PRMRY_DATAMOVER_n_22, + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2]\(2 downto 0) => p_44_out(2 downto 0), + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_chnl_current_frame_cdc_tig_reg[4]\(4 downto 0) => p_31_out(4 downto 0), + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(31 downto 0) => \mm2s_reg_module_strt_addr[0]\(31 downto 0), + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(31 downto 0) => \mm2s_reg_module_strt_addr[1]\(31 downto 0), + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(31 downto 0) => \mm2s_reg_module_strt_addr[2]\(31 downto 0), + \INFERRED_GEN.cnt_i_reg[1]\ => \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_31\, + \INFERRED_GEN.cnt_i_reg[2]\ => I_PRMRY_DATAMOVER_n_32, + \INFERRED_GEN.cnt_i_reg[2]_0\ => I_PRMRY_DATAMOVER_n_34, + \INFERRED_GEN.cnt_i_reg[2]_1\ => I_PRMRY_DATAMOVER_n_35, \INFERRED_GEN.cnt_i_reg[2]_2\(0) => \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_rd_empty\, - \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0\(4 downto 0) => p_32_out(4 downto 0), + \MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0\(4 downto 0) => p_33_out(4 downto 0), \M_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(15 downto 0) => mm2s_reg_module_stride(15 downto 0), - Q(12 downto 0) => p_48_out(12 downto 0), - SR(0) => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_176\, - ch1_delay_cnt_en => ch1_delay_cnt_en, - ch1_disable_delay2_out => ch1_disable_delay2_out, + Q(12 downto 0) => p_49_out(12 downto 0), + SR(0) => \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I/prmry_reset2\, cmnd_wr => cmnd_wr, datamover_idle => \I_STS_MNGR/datamover_idle\, - dma_decerr_reg => \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_36\, - dma_decerr_reg_0 => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_64\, + dma_decerr_reg => \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_35\, + dma_decerr_reg_0 => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_56\, dma_err => dma_err, - dma_interr_reg => \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_39\, - dma_interr_reg_0 => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_58\, - dma_slverr_reg => \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_37\, - dma_slverr_reg_0 => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_63\, - \dmacr_i_reg[0]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_174\, - halt_i_reg => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_72\, - halt_i_reg_0(0) => I_RST_MODULE_n_15, - halted_reg => \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_35\, - in0(0) => p_43_out(0), + dma_interr_reg => \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_33\, + dma_interr_reg_0 => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_54\, + dma_slverr_reg => \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_34\, + dma_slverr_reg_0 => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_55\, + \dmacr_i_reg[2]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_227\, + err_i_reg(0) => I_RST_MODULE_n_26, + halted_reg => \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_32\, + halted_reg_0(0) => \I_CMDSTS/s_axis_cmd_tvalid0\, initial_frame => initial_frame, m_axi_mm2s_aclk => m_axi_mm2s_aclk, mask_fsync_out_i => mask_fsync_out_i, + mm2s_all_lines_xfred => p_0_out, mm2s_axi2ip_wrce(0) => mm2s_axi2ip_wrce(1), + mm2s_fifo_pipe_empty => p_1_out, mm2s_halt => mm2s_halt, - \out\ => mm2s_prmry_resetn, - p_0_in => p_0_in, - p_0_out => p_0_out, - p_17_out => p_17_out, - p_1_out => p_1_out, - p_23_out => p_23_out, + mm2s_prmry_resetn => mm2s_prmry_resetn, + p_24_out => p_24_out, p_2_out => p_2_out, - p_35_out => p_35_out, - p_36_out => p_36_out, p_37_out => p_37_out, - p_44_out => p_44_out, + p_39_out => p_39_out, p_45_out => p_45_out, p_46_out => p_46_out, - p_49_out => p_49_out, - p_55_out => p_55_out, - p_57_out => p_57_out, - p_64_out => p_64_out, + p_47_out => p_47_out, + p_50_out => p_50_out, + p_56_out => p_56_out, + p_58_out => p_58_out, p_67_out => p_67_out, - p_68_out(2 downto 0) => p_68_out(2 downto 0), - prmry_resetn_i_reg(0) => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_172\, + p_70_out => p_70_out, + p_71_out(1 downto 0) => p_71_out(1 downto 0), + p_77_out => p_77_out, + prmry_resetn_i_reg(0) => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_228\, prmtr_update_complete => prmtr_update_complete, - prmtr_updt_complete_i_reg => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_175\, - \ptr_ref_i_reg[4]\(4 downto 0) => p_77_out(4 downto 0), + prmtr_updt_complete_i_reg => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_231\, + \ptr_ref_i_reg[4]\(4 downto 0) => p_80_out(4 downto 0), \reg_module_hsize_reg[15]\(15 downto 0) => mm2s_reg_module_hsize(15 downto 0), \reg_module_vsize_reg[12]\(12 downto 0) => mm2s_reg_module_vsize(12 downto 0), - \sig_addr_cntr_lsh_kh_reg[31]\(48 downto 17) => p_56_out(63 downto 32), - \sig_addr_cntr_lsh_kh_reg[31]\(16) => p_56_out(23), - \sig_addr_cntr_lsh_kh_reg[31]\(15 downto 0) => p_56_out(15 downto 0), - stop_i => stop_i + \sig_addr_cntr_lsh_kh_reg[31]\(48 downto 17) => p_57_out(63 downto 32), + \sig_addr_cntr_lsh_kh_reg[31]\(16) => p_57_out(23), + \sig_addr_cntr_lsh_kh_reg[31]\(15 downto 0) => p_57_out(15 downto 0), + sig_halt_cmplt_reg => I_PRMRY_DATAMOVER_n_23, + stop => p_36_out ); \GEN_SPRT_FOR_MM2S.MM2S_FSYNC_I\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_fsync_gen port map ( - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]\ => I_AXI_DMA_INTRPT_n_21, - SR(0) => p_0_in, + Q(7 downto 0) => mm2s_irqthresh_status(7 downto 0), + SR(0) => \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I/prmry_reset2\, m_axi_mm2s_aclk => m_axi_mm2s_aclk, mask_fsync_out_i => mask_fsync_out_i, - p_23_out => p_23_out, + p_24_out => p_24_out, p_2_out => p_2_out, - p_36_out => p_36_out, - p_45_out => p_45_out, + p_37_out => p_37_out, p_46_out => p_46_out, - p_68_out(0) => p_68_out(0), + p_47_out => p_47_out, + p_4_out => p_4_out, + p_71_out(1) => p_71_out(4), + p_71_out(0) => p_71_out(0), p_in_d1_cdc_from => \GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/p_in_d1_cdc_from\, - prmry_in_xored => \GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/prmry_in_xored\ + prmry_in_xored => \GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/prmry_in_xored\, + prmry_resetn_i_reg => I_AXI_DMA_INTRPT_n_39 ); \GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_mm2s_linebuf port map ( - DIN(0) => sof_flag, + DIN(0) => dm2linebuf_mm2s_tlast, + FULL => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/p_5_out\, \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\(0) => p_7_out, - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\ => mm2s_axis_resetn, - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\ => I_RST_MODULE_n_14, - \GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0\ => \GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_9\, - \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\(0) => dm2linebuf_mm2s_tlast, - Q(12 downto 0) => p_48_out(12 downto 0), - SR(0) => p_0_in, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_0\ => \GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_8\, + \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg_1\ => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/p_8_out\, + \GEN_LINEBUF_NO_SOF.vsize_counter_reg[0]_0\ => \GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_6\, + \INCLUDE_UNPACKING.lsig_cmd_loaded_reg\ => \GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_7\, + Q(12 downto 0) => p_49_out(12 downto 0), + SR(0) => \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I/prmry_reset2\, + WR_EN => I_RST_MODULE_n_25, all_lines_xfred => all_lines_xfred, dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), - fifo_full_i => fifo_full_i, - \fifo_wren__0\ => \fifo_wren__0\, + halt_i_reg => I_RST_MODULE_n_29, + hold_ff_q_reg => I_PRMRY_DATAMOVER_n_191, + lsig_0ffset_cntr => \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/lsig_0ffset_cntr\, m_axi_mm2s_aclk => m_axi_mm2s_aclk, m_axis_mm2s_aclk => m_axis_mm2s_aclk, m_axis_mm2s_tdata(31 downto 0) => m_axis_mm2s_tdata(31 downto 0), m_axis_mm2s_tlast => m_axis_mm2s_tlast, m_axis_mm2s_tready => m_axis_mm2s_tready, m_axis_mm2s_tuser(0) => m_axis_mm2s_tuser(0), + mm2s_all_lines_xfred => p_0_out, + mm2s_axis_resetn => mm2s_axis_resetn, + mm2s_fifo_pipe_empty => p_1_out, mm2s_halt => mm2s_halt, + mm2s_prmry_resetn => mm2s_prmry_resetn, \out\ => m_axis_mm2s_tvalid, - p_0_out => p_0_out, p_15_out => p_15_out, - p_1_out => p_1_out, + p_24_out => p_24_out, s_valid0 => s_valid0, scndry_reset2 => \GEN_CDC_FOR_ASYNC.PRMTR_UPDT_CDC_I/scndry_reset2\, sig_reset_reg_reg => \GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_3\ @@ -38369,131 +93941,126 @@ AXI_LITE_REG_INTERFACE_I: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_if \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_module port map ( D(31 downto 0) => mm2s_axi2ip_wrdata(31 downto 0), - E(0) => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_173\, - \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_72\, - \GEN_DONE_FOR_SNF.GEN_FOR_FREE_RUN.xfred_started_reg\ => \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_8\, - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]\(0) => p_4_out, - \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0]\(0) => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_68\, - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0]\(0) => p_2_in(0), - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1 downto 0) => mm2s_axi2ip_rdaddr(3 downto 2), - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7]\ => AXI_LITE_REG_INTERFACE_I_n_40, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[7]_0\ => AXI_LITE_REG_INTERFACE_I_n_48, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12]\ => AXI_LITE_REG_INTERFACE_I_n_83, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13]\ => AXI_LITE_REG_INTERFACE_I_n_84, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4]\ => \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_39\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_79\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_166\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_167\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_168\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[13]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_169\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[14]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_170\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[15]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_171\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[1]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_157\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[2]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_158\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_159\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_160\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_161\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_162\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_163\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_164\, - \GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_165\, - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(4 downto 0) => p_77_out(4 downto 0), - \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\(4 downto 0) => p_76_out(4 downto 0), - \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_175\, + E(0) => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_72\, + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_227\, + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_63\, + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.GEN_CH1_FAST_COUNTER.ch1_dly_fast_cnt_reg[6]_0\(0) => p_11_out, + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_cnt_en_reg\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_62\, + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_delay_count_reg[0]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_65\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]\(1 downto 0) => mm2s_axi2ip_rdaddr(3 downto 2), + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[3]_0\ => AXI_LITE_REG_INTERFACE_I_n_114, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[4]\ => AXI_LITE_REG_INTERFACE_I_n_111, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]\ => AXI_LITE_REG_INTERFACE_I_n_112, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_0\ => AXI_LITE_REG_INTERFACE_I_n_113, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_rdaddr_captured_mm2s_cdc_tig_reg[7]_1\ => AXI_LITE_REG_INTERFACE_I_n_115, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_mm2s_cdc_tig_reg[2]\ => AXI_LITE_REG_INTERFACE_I_n_161, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[12]\ => AXI_LITE_REG_INTERFACE_I_n_163, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[13]\ => AXI_LITE_REG_INTERFACE_I_n_164, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[18]\(0) => AXI_LITE_REG_INTERFACE_I_n_81, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_axi2ip_wrdata_cdc_tig_reg[4]\ => \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_33\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[0]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_75\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[10]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_224\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[11]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_225\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[12]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_226\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[3]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_217\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[4]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_218\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[5]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_219\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[6]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_220\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[7]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_221\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[8]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_222\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.mm2s_ip2axi_rddata_d1_reg[9]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_223\, + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(4 downto 0) => p_80_out(4 downto 0), + \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.mm2s_ip2axi_frame_store_cdc_tig_reg[4]\(4 downto 0) => p_79_out(4 downto 0), + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_231\, \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(31 downto 0) => \mm2s_reg_module_strt_addr[0]\(31 downto 0), - \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]\(0) => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_172\, - \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0\(4 downto 0) => p_32_out(4 downto 0), - Q(0) => mm2s_irqthresh_status(0), - SR(0) => p_0_in, + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(31 downto 0) => \mm2s_reg_module_strt_addr[1]\(31 downto 0), + \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(31 downto 0) => \mm2s_reg_module_strt_addr[2]\(31 downto 0), + \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]\(0) => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_228\, + \MASTER_MODE_FRAME_CNT.frame_number_i_reg[4]_0\(4 downto 0) => p_33_out(4 downto 0), + Q(4) => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_67\, + Q(3) => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_68\, + Q(2) => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_69\, + Q(1) => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_70\, + Q(0) => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_71\, + SR(0) => \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I/prmry_reset2\, ch1_delay_cnt_en => ch1_delay_cnt_en, - \ch1_delay_zero__6\ => \ch1_delay_zero__6\, - ch1_disable_delay2_out => ch1_disable_delay2_out, - \ch1_ioc_irq_set_i__0\ => \ch1_ioc_irq_set_i__0\, - datamover_idle => \I_STS_MNGR/datamover_idle\, - datamover_idle_reg => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_174\, - decerr_i_reg => \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_36\, - different_delay => \I_DMA_REGISTER/different_delay\, - different_thresh => \I_DMA_REGISTER/different_thresh\, - dly_irq_reg => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_60\, + ch1_delay_zero => ch1_delay_zero, + ch1_dly_irq_set => mm2s_dly_irq_set, + decerr_i_reg => \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_35\, + dly_irq_reg => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_58\, dma_err => dma_err, - \dmacr_i_reg[2]\ => I_RST_MODULE_n_13, - err_d1_reg => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_58\, - err_d1_reg_0 => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_63\, - err_d1_reg_1 => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_64\, - err_irq_reg => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_76\, + dmacr_i(0) => \I_DMA_REGISTER/dmacr_i\(0), + \dmacr_i_reg[0]\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_74\, + \dmacr_i_reg[2]\ => I_RST_MODULE_n_16, + err_d1_reg => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_54\, + err_d1_reg_0 => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_55\, + err_d1_reg_1 => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_56\, + err_irq_reg => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_73\, halt_reset => \GEN_RESET_FOR_MM2S.RESET_I/halt_reset\, - halted_clr_reg => \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_35\, + halted_clr_reg => \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_32\, \hsize_vid_reg[15]\(15 downto 0) => mm2s_reg_module_hsize(15 downto 0), - in0(31) => AXI_LITE_REG_INTERFACE_I_n_50, - in0(30) => AXI_LITE_REG_INTERFACE_I_n_51, - in0(29) => AXI_LITE_REG_INTERFACE_I_n_52, - in0(28) => AXI_LITE_REG_INTERFACE_I_n_53, - in0(27) => AXI_LITE_REG_INTERFACE_I_n_54, - in0(26) => AXI_LITE_REG_INTERFACE_I_n_55, - in0(25) => AXI_LITE_REG_INTERFACE_I_n_56, - in0(24) => AXI_LITE_REG_INTERFACE_I_n_57, - in0(23) => AXI_LITE_REG_INTERFACE_I_n_58, - in0(22) => AXI_LITE_REG_INTERFACE_I_n_59, - in0(21) => AXI_LITE_REG_INTERFACE_I_n_60, - in0(20) => AXI_LITE_REG_INTERFACE_I_n_61, - in0(19) => AXI_LITE_REG_INTERFACE_I_n_62, - in0(18) => AXI_LITE_REG_INTERFACE_I_n_63, - in0(17) => AXI_LITE_REG_INTERFACE_I_n_64, - in0(16) => AXI_LITE_REG_INTERFACE_I_n_65, - in0(15) => AXI_LITE_REG_INTERFACE_I_n_66, - in0(14) => AXI_LITE_REG_INTERFACE_I_n_67, - in0(13) => AXI_LITE_REG_INTERFACE_I_n_68, - in0(12) => AXI_LITE_REG_INTERFACE_I_n_69, - in0(11) => AXI_LITE_REG_INTERFACE_I_n_70, - in0(10) => AXI_LITE_REG_INTERFACE_I_n_71, - in0(9) => AXI_LITE_REG_INTERFACE_I_n_72, - in0(8) => AXI_LITE_REG_INTERFACE_I_n_73, - in0(7) => AXI_LITE_REG_INTERFACE_I_n_74, - in0(6) => AXI_LITE_REG_INTERFACE_I_n_75, - in0(5) => AXI_LITE_REG_INTERFACE_I_n_76, - in0(4) => AXI_LITE_REG_INTERFACE_I_n_77, - in0(3) => AXI_LITE_REG_INTERFACE_I_n_78, - in0(2) => AXI_LITE_REG_INTERFACE_I_n_79, - in0(1) => AXI_LITE_REG_INTERFACE_I_n_80, - in0(0) => AXI_LITE_REG_INTERFACE_I_n_81, + in0(28) => AXI_LITE_REG_INTERFACE_I_n_82, + in0(27) => AXI_LITE_REG_INTERFACE_I_n_83, + in0(26) => AXI_LITE_REG_INTERFACE_I_n_84, + in0(25) => AXI_LITE_REG_INTERFACE_I_n_85, + in0(24) => AXI_LITE_REG_INTERFACE_I_n_86, + in0(23) => AXI_LITE_REG_INTERFACE_I_n_87, + in0(22) => AXI_LITE_REG_INTERFACE_I_n_88, + in0(21) => AXI_LITE_REG_INTERFACE_I_n_89, + in0(20) => AXI_LITE_REG_INTERFACE_I_n_90, + in0(19) => AXI_LITE_REG_INTERFACE_I_n_91, + in0(18) => AXI_LITE_REG_INTERFACE_I_n_92, + in0(17) => AXI_LITE_REG_INTERFACE_I_n_93, + in0(16) => AXI_LITE_REG_INTERFACE_I_n_94, + in0(15) => AXI_LITE_REG_INTERFACE_I_n_95, + in0(14) => AXI_LITE_REG_INTERFACE_I_n_96, + in0(13) => AXI_LITE_REG_INTERFACE_I_n_97, + in0(12) => AXI_LITE_REG_INTERFACE_I_n_98, + in0(11) => AXI_LITE_REG_INTERFACE_I_n_99, + in0(10) => AXI_LITE_REG_INTERFACE_I_n_100, + in0(9) => AXI_LITE_REG_INTERFACE_I_n_101, + in0(8) => AXI_LITE_REG_INTERFACE_I_n_102, + in0(7) => AXI_LITE_REG_INTERFACE_I_n_103, + in0(6) => AXI_LITE_REG_INTERFACE_I_n_104, + in0(5) => AXI_LITE_REG_INTERFACE_I_n_105, + in0(4) => AXI_LITE_REG_INTERFACE_I_n_106, + in0(3) => AXI_LITE_REG_INTERFACE_I_n_107, + in0(2) => AXI_LITE_REG_INTERFACE_I_n_108, + in0(1) => AXI_LITE_REG_INTERFACE_I_n_109, + in0(0) => AXI_LITE_REG_INTERFACE_I_n_110, initial_frame => initial_frame, - ioc_irq_reg => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_59\, + ioc_irq_reg => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_57\, m_axi_mm2s_aclk => m_axi_mm2s_aclk, mask_fsync_out_i => mask_fsync_out_i, - mm2s_axi2ip_wrce(6 downto 3) => mm2s_axi2ip_wrce(23 downto 20), + mm2s_axi2ip_wrce(8 downto 3) => mm2s_axi2ip_wrce(25 downto 20), mm2s_axi2ip_wrce(2) => mm2s_axi2ip_wrce(10), mm2s_axi2ip_wrce(1 downto 0) => mm2s_axi2ip_wrce(1 downto 0), - mm2s_dly_irq_set => mm2s_dly_irq_set, mm2s_halt => mm2s_halt, mm2s_halt_cmplt => mm2s_halt_cmplt, mm2s_ioc_irq_set => mm2s_ioc_irq_set, - \out\(31 downto 0) => p_78_out(31 downto 0), - p_0_out => p_0_out, - p_10_out => p_10_out, + \out\(31 downto 0) => p_81_out(31 downto 0), + p_13_out => p_13_out, p_17_out => p_17_out, - p_23_out => p_23_out, - p_35_out => p_35_out, - p_44_out => p_44_out, - p_46_out => p_46_out, - p_49_out => p_49_out, - p_64_out => p_64_out, + p_24_out => p_24_out, + p_45_out => p_45_out, + p_47_out => p_47_out, + p_50_out => p_50_out, p_67_out => p_67_out, - p_68_out(25 downto 6) => p_68_out(31 downto 12), - p_68_out(5 downto 3) => p_68_out(6 downto 4), - p_68_out(2 downto 0) => p_68_out(2 downto 0), - \p_6_out__1\ => \p_6_out__1\, - p_75_out => p_75_out, - prmry_in => p_37_out, - prmry_resetn_i_reg => AXI_LITE_REG_INTERFACE_I_n_82, - prmry_resetn_i_reg_0 => mm2s_prmry_resetn, - prmry_resetn_i_reg_1(0) => AXI_LITE_REG_INTERFACE_I_n_49, + p_70_out => p_70_out, + p_71_out(18 downto 3) => p_71_out(31 downto 16), + p_71_out(2) => p_71_out(4), + p_71_out(1 downto 0) => p_71_out(1 downto 0), + p_77_out => p_77_out, + p_78_out => p_78_out, + prmry_in => p_39_out, + prmry_resetn_i_reg => mm2s_prmry_resetn, prmtr_update_complete => prmtr_update_complete, reset_counts => \I_DMA_REGISTER/reset_counts\, - reset_counts_reg => I_RST_MODULE_n_16, - \s_axis_cmd_tdata_reg[63]\(0) => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_176\, + reset_counts_reg => I_RST_MODULE_n_31, + s_axis_cmd_tvalid_reg(0) => \I_CMDSTS/s_axis_cmd_tvalid0\, s_soft_reset_i0 => \GEN_RESET_FOR_MM2S.RESET_I/s_soft_reset_i0\, - slverr_i_reg => \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_37\, - stop_i => stop_i, + slverr_i_reg => \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_34\, + stop => p_36_out, \stride_vid_reg[15]\(15 downto 0) => mm2s_reg_module_stride(15 downto 0), \vsize_vid_reg[12]\(12 downto 0) => mm2s_reg_module_vsize(12 downto 0) ); @@ -38509,10 +94076,10 @@ AXI_LITE_REG_INTERFACE_I: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_if ); \GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_vid_cdc port map ( - \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]\ => \GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_9\, + \GENLOCK_FOR_MASTER.frame_ptr_out_reg[2]\(2 downto 0) => p_44_out(2 downto 0), + \GEN_LINEBUF_NO_SOF.vsize_counter_reg[4]\ => \GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_6\, SR(0) => \GEN_CDC_FOR_ASYNC.PRMTR_UPDT_CDC_I/scndry_reset2\, all_lines_xfred => all_lines_xfred, - in0(0) => p_43_out(0), m_axi_mm2s_aclk => m_axi_mm2s_aclk, m_axis_mm2s_aclk => m_axis_mm2s_aclk, mm2s_frame_ptr_in(5 downto 0) => mm2s_frame_ptr_in(5 downto 0), @@ -38523,7 +94090,811 @@ AXI_LITE_REG_INTERFACE_I: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_if p_in_d1_cdc_from_0 => \GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/p_in_d1_cdc_from\, prmry_in_xored => \GEN_CDC_FOR_ASYNC.SOF_CDC_I/prmry_in_xored\, prmry_in_xored_1 => \GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/prmry_in_xored\, - prmry_resetn_i_reg(0) => p_0_in + prmry_resetn_i_reg(0) => \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I/prmry_reset2\ + ); +\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.GEN_FOR_ASYNC_FLUSH_SOF.S2MM_HALTED_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized22\ + port map ( + SR(0) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF/prmry_reset2\, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + prmry_reset2 => \I_SM/GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF/prmry_reset2\, + s2mm_dmasr(0) => s2mm_dmasr(0), + s2mm_dmasr_halted_s => s2mm_dmasr_halted_s, + s_axis_s2mm_aclk => s_axis_s2mm_aclk + ); +\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.GEN_FOR_ASYNC_FLUSH_SOF.S2MM_PRM_UPDT_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized21\ + port map ( + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_clr_flag1_reg\ => \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.GEN_FOR_ASYNC_FLUSH_SOF.S2MM_PRM_UPDT_CDC_I_n_1\, + SR(0) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF/prmry_reset2\, + d_tready_before_fsync_clr_flag1 => d_tready_before_fsync_clr_flag1, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + \out\ => s2mm_axis_resetn, + p_in_d1_cdc_from => p_in_d1_cdc_from, + prmry_in_xored => prmry_in_xored, + prmry_reset2 => \I_SM/GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF/prmry_reset2\, + s2mm_dmasr_halted_s => s2mm_dmasr_halted_s, + s_axis_s2mm_aclk => s_axis_s2mm_aclk + ); +\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.GEN_FOR_ASYNC_FLUSH_SOF.SOF_LATE_CDC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_cdc_sync__parameterized23\ + port map ( + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_0\ => \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.GEN_FOR_ASYNC_FLUSH_SOF.SOF_LATE_CDC_I_n_1\, + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from_1\ => \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.GEN_FOR_ASYNC_FLUSH_SOF.SOF_LATE_CDC_I_n_2\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_n_0\, + SR(0) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF/prmry_reset2\, + d_tready_before_fsync => d_tready_before_fsync, + d_tready_before_fsync_clr_flag1 => d_tready_before_fsync_clr_flag1, + d_tready_sof_late => d_tready_sof_late, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + prmry_reset2 => \I_SM/GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF/prmry_reset2\, + s2mm_fsize_more_or_sof_late => s2mm_fsize_more_or_sof_late, + s2mm_fsize_more_or_sof_late_s => s2mm_fsize_more_or_sof_late_s, + s2mm_tuser_to_fsync_out => s2mm_tuser_to_fsync_out, + s_axis_s2mm_aclk => s_axis_s2mm_aclk + ); +\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_clr_flag1_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.GEN_FOR_ASYNC_FLUSH_SOF.S2MM_PRM_UPDT_CDC_I_n_1\, + Q => d_tready_before_fsync_clr_flag1, + R => '0' + ); +\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => I_RST_MODULE_n_28, + Q => d_tready_before_fsync, + R => '0' + ); +\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_fsize_less_err_flag_10_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_56\, + Q => s2mm_fsize_less_err_flag_10, + R => '0' + ); +\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_sof_late_err_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_9\, + Q => d_tready_sof_late, + R => '0' + ); +\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_tuser_to_fsync_out_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_8\, + Q => s2mm_tuser_to_fsync_out, + R => '0' + ); +\GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s_axis_s2mm_tuser_d1_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => '1', + D => p_19_in, + Q => s_axis_s2mm_tuser_d1, + R => \I_SM/GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF/prmry_reset2\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => strm_all_lines_rcvd_no_dwidth, + D => strm_not_finished_no_dwidth, + Q => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_n_0\, + R => \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => strm_all_lines_rcvd_no_dwidth, + D => \GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I_n_16\, + Q => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg_n_0\, + S => \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_10\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => vsize_counter_no_dwidth(12), + O => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_10_n_0\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_11\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => vsize_counter_no_dwidth(11), + O => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_11_n_0\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_12\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => vsize_counter_no_dwidth(10), + O => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_12_n_0\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_13\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => vsize_counter_no_dwidth(9), + O => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_13_n_0\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_8_n_0\, + I1 => vsize_counter_no_dwidth(6), + I2 => vsize_counter_no_dwidth(5), + I3 => vsize_counter_no_dwidth(8), + I4 => vsize_counter_no_dwidth(7), + I5 => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_9_n_0\, + O => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_4_n_0\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => vsize_counter_no_dwidth(10), + I1 => vsize_counter_no_dwidth(9), + I2 => vsize_counter_no_dwidth(12), + I3 => vsize_counter_no_dwidth(11), + O => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_8_n_0\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_9\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => vsize_counter_no_dwidth(2), + I1 => vsize_counter_no_dwidth(1), + I2 => vsize_counter_no_dwidth(4), + I3 => vsize_counter_no_dwidth(3), + O => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_9_n_0\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => vsize_counter_no_dwidth(4), + O => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_3_n_0\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => vsize_counter_no_dwidth(3), + O => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_4_n_0\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => vsize_counter_no_dwidth(2), + O => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_5_n_0\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_6\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => vsize_counter_no_dwidth(1), + O => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_6_n_0\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => vsize_counter_no_dwidth(8), + O => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_3_n_0\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => vsize_counter_no_dwidth(7), + O => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_4_n_0\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => vsize_counter_no_dwidth(6), + O => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_5_n_0\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_6\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => vsize_counter_no_dwidth(5), + O => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_6_n_0\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => strm_all_lines_rcvd_no_dwidth, + D => p_1_in(0), + Q => vsize_counter_no_dwidth(0), + R => \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => strm_all_lines_rcvd_no_dwidth, + D => p_1_in(10), + Q => vsize_counter_no_dwidth(10), + R => \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => strm_all_lines_rcvd_no_dwidth, + D => p_1_in(11), + Q => vsize_counter_no_dwidth(11), + R => \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => strm_all_lines_rcvd_no_dwidth, + D => p_1_in(12), + Q => vsize_counter_no_dwidth(12), + R => \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]_i_7\: unisim.vcomponents.CARRY4 + port map ( + CI => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[8]_i_2_n_0\, + CO(3) => \NLW_GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]_i_7_CO_UNCONNECTED\(3), + CO(2) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]_i_7_n_1\, + CO(1) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]_i_7_n_2\, + CO(0) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[12]_i_7_n_3\, + CYINIT => '0', + DI(3) => '0', + DI(2 downto 0) => vsize_counter_no_dwidth(11 downto 9), + O(3 downto 0) => minusOp(12 downto 9), + S(3) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_10_n_0\, + S(2) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_11_n_0\, + S(1) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_12_n_0\, + S(0) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_13_n_0\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => strm_all_lines_rcvd_no_dwidth, + D => p_1_in(1), + Q => vsize_counter_no_dwidth(1), + R => \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => strm_all_lines_rcvd_no_dwidth, + D => p_1_in(2), + Q => vsize_counter_no_dwidth(2), + R => \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => strm_all_lines_rcvd_no_dwidth, + D => p_1_in(3), + Q => vsize_counter_no_dwidth(3), + R => \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => strm_all_lines_rcvd_no_dwidth, + D => p_1_in(4), + Q => vsize_counter_no_dwidth(4), + R => \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[4]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[4]_i_2_n_0\, + CO(2) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[4]_i_2_n_1\, + CO(1) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[4]_i_2_n_2\, + CO(0) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[4]_i_2_n_3\, + CYINIT => vsize_counter_no_dwidth(0), + DI(3 downto 0) => vsize_counter_no_dwidth(4 downto 1), + O(3 downto 0) => minusOp(4 downto 1), + S(3) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_3_n_0\, + S(2) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_4_n_0\, + S(1) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_5_n_0\, + S(0) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[4]_i_6_n_0\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => strm_all_lines_rcvd_no_dwidth, + D => p_1_in(5), + Q => vsize_counter_no_dwidth(5), + R => \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => strm_all_lines_rcvd_no_dwidth, + D => p_1_in(6), + Q => vsize_counter_no_dwidth(6), + R => \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => strm_all_lines_rcvd_no_dwidth, + D => p_1_in(7), + Q => vsize_counter_no_dwidth(7), + R => \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => strm_all_lines_rcvd_no_dwidth, + D => p_1_in(8), + Q => vsize_counter_no_dwidth(8), + R => \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[8]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[4]_i_2_n_0\, + CO(3) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[8]_i_2_n_0\, + CO(2) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[8]_i_2_n_1\, + CO(1) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[8]_i_2_n_2\, + CO(0) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[8]_i_2_n_3\, + CYINIT => '0', + DI(3 downto 0) => vsize_counter_no_dwidth(8 downto 5), + O(3 downto 0) => minusOp(8 downto 5), + S(3) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_3_n_0\, + S(2) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_4_n_0\, + S(1) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_5_n_0\, + S(0) => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[8]_i_6_n_0\ + ); +\GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_axis_s2mm_aclk, + CE => strm_all_lines_rcvd_no_dwidth, + D => p_1_in(9), + Q => vsize_counter_no_dwidth(9), + R => \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4\ + ); +\GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF\: entity work.\Arty_Z7_20_axi_vdma_0_0_axi_vdma_skid_buf__parameterized0\ + port map ( + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_s2mm_fsync_core_till_mmap_done_flag_d1_reg\ => \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_3\, + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_reg\ => \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.GEN_FOR_ASYNC_FLUSH_SOF.SOF_LATE_CDC_I_n_2\, + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_sof_late_err_reg\ => \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_9\, + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_tuser_to_fsync_out_reg\ => \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_5\, + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_tuser_to_fsync_out_reg_0\ => \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_8\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_n_0\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\ => \GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I_n_20\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_1\ => \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.GEN_FOR_ASYNC_FLUSH_SOF.SOF_LATE_CDC_I_n_1\, + M_Data(7 downto 0) => p_94_out(7 downto 0), + M_Last => p_96_out, + M_VALID => p_92_out, + SR(0) => \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_4\, + d_tready_before_fsync_clr_flag1 => d_tready_before_fsync_clr_flag1, + d_tready_sof_late => d_tready_sof_late, + delay_s2mm_fsync_core_till_mmap_done_flag => delay_s2mm_fsync_core_till_mmap_done_flag, + drop_fsync_d_pulse_gen_fsize_less_err => p_10_out, + \out\ => s2mm_axis_resetn, + p_19_in => p_19_in, + run_stop_reg => run_stop_reg, + s2mm_fsize_less_err_flag_10 => s2mm_fsize_less_err_flag_10, + s2mm_fsize_more_or_sof_late_s => s2mm_fsize_more_or_sof_late_s, + s2mm_fsync_out_i => s2mm_fsync_out_i, + s2mm_tuser_to_fsync_out => s2mm_tuser_to_fsync_out, + s_axis_fifo_ainit_nosync => s_axis_fifo_ainit_nosync, + s_axis_s2mm_aclk => s_axis_s2mm_aclk, + s_axis_s2mm_tdata(7 downto 0) => s_axis_s2mm_tdata(7 downto 0), + s_axis_s2mm_tlast => s_axis_s2mm_tlast, + s_axis_s2mm_tready => s_axis_s2mm_tready, + s_axis_s2mm_tuser(0) => s_axis_s2mm_tuser(0), + s_axis_s2mm_tuser_d1 => s_axis_s2mm_tuser_d1, + s_axis_s2mm_tvalid => s_axis_s2mm_tvalid, + sig_reset_reg => sig_reset_reg + ); +\GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR\: entity work.\Arty_Z7_20_axi_vdma_0_0_axi_vdma_mngr__parameterized0\ + port map ( + D(0) => s2mm_axi2ip_wrdata(4), + \DM_GEN_DLYSTRIDE_REGISTER.reg_module_strid_reg[15]\(15 downto 0) => s2mm_reg_module_stride(15 downto 0), + \DYNAMIC_MASTER_MODE_FRAME_CNT.chnl_current_frame_reg[4]_0\(4 downto 0) => s2mm_frame_number(4 downto 0), + E(0) => I_PRMRY_DATAMOVER_n_28, + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ => s2mm_axis_resetn, + \GEN_CDC_FOR_ASYNC.cdc2dmac_frame_ptr_in_reg[2]\(2 downto 0) => s2mm_s_frame_ptr_in(2 downto 0), + \GEN_CDC_FOR_ASYNC.frame_ptr_out_d1_cdc_tig_reg[2]\(2 downto 0) => s2mm_m_frame_ptr_out(2 downto 0), + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg\ => \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_15\, + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_irqthresh_decr_mask_sig_reg\ => \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_16\, + \GEN_NORMAL_DM_COMMAND.cmnd_data_reg[15]\(12 downto 0) => crnt_hsize(15 downto 3), + \GEN_NUM_FSTORES_3.reg_module_start_address1_i_reg[31]\(31 downto 0) => \s2mm_reg_module_strt_addr[0]\(31 downto 0), + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(31 downto 0) => \s2mm_reg_module_strt_addr[1]\(31 downto 0), + \GEN_NUM_FSTORES_3.reg_module_start_address3_i_reg[31]\(31 downto 0) => \s2mm_reg_module_strt_addr[2]\(31 downto 0), + \GEN_S2MM_FLUSH_SOF_LOGIC.delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s_reg\ => \GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I_n_21\, + \GEN_S2MM_FLUSH_SOF_LOGIC.done_vsize_counter_reg[0]\(0) => \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_17\, + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_chnl_current_frame_cdc_tig_reg[4]\(4 downto 0) => s2mm_chnl_current_frame(4 downto 0), + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_genlock_pair_frame_cdc_tig_reg[4]\(4 downto 0) => s2mm_genlock_pair_frame(4 downto 0), + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.s2mm_fsize_less_err_flag_10_reg\ => \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_56\, + \GEN_STS_GRTR_THAN_8.undrflo_err_reg\(0) => \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_54\, + \INFERRED_GEN.cnt_i_reg[2]\ => I_PRMRY_DATAMOVER_n_36, + \INFERRED_GEN.cnt_i_reg[2]_0\ => I_PRMRY_DATAMOVER_n_37, + \INFERRED_GEN.cnt_i_reg[2]_1\ => I_PRMRY_DATAMOVER_n_38, + \INFERRED_GEN.cnt_i_reg[2]_2\(0) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_rd_empty\, + Q(12 downto 0) => s2mm_crnt_vsize(12 downto 0), + S(0) => \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_53\, + \S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg\ => \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_60\, + \S2MM_ERR_FOR_IRQ.dma_interr_minus_frame_errors_reg_0\ => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_68\, + SR(0) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF/prmry_reset2\, + ch2_delay_cnt_en => ch2_delay_cnt_en, + ch2_irqthresh_decr_mask_sig => ch2_irqthresh_decr_mask_sig, + cmnd_wr => cmnd_wr_5, + datamover_idle => \I_STS_MNGR/datamover_idle_3\, + dma_decerr_reg => \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_59\, + dma_decerr_reg_0 => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_61\, + dma_err => dma_err_2, + dma_slverr_reg => \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_58\, + dma_slverr_reg_0 => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_60\, + drop_fsync_d_pulse_gen_fsize_less_err => p_10_out, + drop_fsync_d_pulse_gen_fsize_less_err_d1 => \I_SM/drop_fsync_d_pulse_gen_fsize_less_err_d1\, + err_i_reg(0) => I_RST_MODULE_n_27, + fsize_mismatch_err => s2mm_fsize_mismatch_err, + fsize_mismatch_err_s1 => \I_SM/fsize_mismatch_err_s1\, + halt_i0 => \GEN_RESET_FOR_S2MM.RESET_I/halt_i0\, + halt_i_reg => I_RST_MODULE_n_22, + halted_reg => \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_57\, + halted_reg_0(0) => \VIDEO_REG_I/p_1_out\, + initial_frame => initial_frame_0, + lsize_mismatch_err => s2mm_lsize_mismatch_err, + lsize_more_mismatch_err => s2mm_lsize_more_mismatch_err, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + m_axis_s2mm_sts_tdata(0) => m_axis_s2mm_sts_tdata(8), + m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready, + mask_fsync_out_i => mask_fsync_out_i_8, + num_fstore_minus1(0) => num_fstore_minus1(1), + \out\ => s2mm_prmry_resetn, + p_12_out => \I_CMDSTS/p_12_out\, + p_2_out => p_2_out_1, + p_9_out => \I_CMDSTS/p_9_out\, + prmry_reset2 => \I_SM/GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF/prmry_reset2\, + prmry_resetn_i_reg => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_71\, + prmry_resetn_i_reg_0(0) => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_88\, + prmtr_update_complete => prmtr_update_complete_4, + prmtr_updt_complete_i_reg => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_92\, + \ptr_ref_i_reg[4]\(4 downto 0) => p_83_out(4 downto 0), + \reg_module_hsize_reg[15]\(15 downto 0) => s2mm_reg_module_hsize(15 downto 0), + \reg_module_vsize_reg[12]\(12 downto 0) => s2mm_reg_module_vsize(12 downto 0), + run_stop_d1 => \GEN_RESET_FOR_S2MM.RESET_I/run_stop_d1\, + s2mm_axi2ip_wrce(0) => s2mm_axi2ip_wrce(13), + s2mm_cdc2dmac_fsync => s2mm_cdc2dmac_fsync, + s2mm_dma_interr_set_minus_frame_errors => s2mm_dma_interr_set_minus_frame_errors, + s2mm_dmacr(3) => s2mm_dmacr(15), + s2mm_dmacr(2) => s2mm_dmacr(3), + s2mm_dmacr(1 downto 0) => s2mm_dmacr(1 downto 0), + s2mm_dmasr(0) => s2mm_dmasr(0), + s2mm_fsize_less_err_flag_10 => s2mm_fsize_less_err_flag_10, + s2mm_fsync_out_m_i => s2mm_fsync_out_m_i, + s2mm_ftchcmdsts_idle => s2mm_ftchcmdsts_idle, + s2mm_halt => s2mm_halt, + s2mm_packet_sof => s2mm_packet_sof, + s2mm_soft_reset => s2mm_soft_reset, + s2mm_stop => s2mm_stop, + s2mm_tstvect_fsync => s2mm_tstvect_fsync, + s2mm_valid_frame_sync => s2mm_valid_frame_sync, + s2mm_valid_frame_sync_cmb => s2mm_valid_frame_sync_cmb, + s2mm_valid_video_prmtrs => s2mm_valid_video_prmtrs, + s_axis_s2mm_aclk => s_axis_s2mm_aclk, + s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid, + sig_halt_cmplt_reg => I_PRMRY_DATAMOVER_n_30, + \sig_input_addr_reg_reg[31]\(48 downto 17) => s_axis_s2mm_cmd_tdata(63 downto 32), + \sig_input_addr_reg_reg[31]\(16) => s_axis_s2mm_cmd_tdata(23), + \sig_input_addr_reg_reg[31]\(15 downto 0) => s_axis_s2mm_cmd_tdata(15 downto 0), + \sig_user_reg_out_reg[0]\ => \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_5\, + soft_reset_d1 => \GEN_RESET_FOR_S2MM.RESET_I/soft_reset_d1\ + ); +\GEN_SPRT_FOR_S2MM.S2MM_FSYNC_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_axi_vdma_fsync_gen__parameterized0\ + port map ( + \GEN_NO_INTERNAL_GENLOCK.DM_GEN_DMACR_REGISTER.dmacr_i_reg[4]\(0) => s2mm_dmacr(4), + Q(7 downto 0) => s2mm_irqthresh_status(7 downto 0), + SR(0) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF/prmry_reset2\, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + mask_fsync_out_i => mask_fsync_out_i_8, + p_2_out => p_2_out_1, + p_4_out => p_4_out_6, + p_in_d1_cdc_from => \GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/p_in_d1_cdc_from_13\, + prmry_in_xored => \GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/prmry_in_xored_7\, + prmry_resetn_i_reg => I_AXI_DMA_INTRPT_n_40, + s2mm_cdc2dmac_fsync => s2mm_cdc2dmac_fsync, + s2mm_valid_video_prmtrs => s2mm_valid_video_prmtrs + ); +\GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_s2mm_linebuf + port map ( + D(12 downto 0) => p_1_in(12 downto 0), + DIN(7 downto 0) => p_94_out(7 downto 0), + DOUT(8) => linebuf2dm_s2mm_tlast, + DOUT(7 downto 0) => linebuf2dm_s2mm_tdata(7 downto 0), + EMPTY => fifo_empty_i, + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ => \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_3\, + \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg\(0) => \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_17\, + \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_s1_reg\ => \GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I_n_21\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg\ => \GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I_n_17\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_0\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.chnl_ready_no_dwidth_reg_n_0\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg\ => \GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I_n_16\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg_0\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.strm_all_lines_rcvd_no_dwidth_reg_n_0\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[0]\(0) => vsize_counter_no_dwidth(0), + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_4_n_0\, + M_Last => p_96_out, + M_VALID => p_92_out, + Q(12 downto 0) => s2mm_crnt_vsize(12 downto 0), + RD_EN => fifo_rden, + SR(0) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF/prmry_reset2\, + delay_s2mm_fsync_core_till_mmap_done_flag => delay_s2mm_fsync_core_till_mmap_done_flag, + drop_fsync_d_pulse_gen_fsize_less_err_d1 => \I_SM/drop_fsync_d_pulse_gen_fsize_less_err_d1\, + fsize_mismatch_err_s1 => \I_SM/fsize_mismatch_err_s1\, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + minusOp(11 downto 0) => minusOp(12 downto 1), + \out\ => s2mm_axis_resetn, + p_in_d1_cdc_from => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF/p_in_d1_cdc_from\, + prmry_in_xored => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF/prmry_in_xored\, + prmry_reset2 => \I_SM/GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF/prmry_reset2\, + run_stop_reg => run_stop_reg, + s2mm_dmacr(2 downto 1) => s2mm_dmacr(6 downto 5), + s2mm_dmacr(0) => s2mm_dmacr(0), + s2mm_fsync_core => s2mm_fsync_core, + s2mm_fsync_out_i => s2mm_fsync_out_i, + s2mm_fsync_out_m_i => s2mm_fsync_out_m_i, + s2mm_halt => s2mm_halt, + s2mm_strm_wready => dm2linebuf_s2mm_tready, + s_axis_fifo_ainit_nosync => s_axis_fifo_ainit_nosync, + s_axis_s2mm_aclk => s_axis_s2mm_aclk, + s_valid0 => s_valid0_9, + sig_last_reg_out_reg => \GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I_n_20\, + sig_reset_reg => sig_reset_reg, + \sig_user_reg_out_reg[0]\ => \GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_OFF_SKID.I_S2MM_SKID_FLUSH_SOF_n_5\, + strm_not_finished_no_dwidth => strm_not_finished_no_dwidth + ); +\GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I\: entity work.\Arty_Z7_20_axi_vdma_0_0_axi_vdma_reg_module__parameterized0\ + port map ( + D(31 downto 0) => s2mm_axi2ip_wrdata(31 downto 0), + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]\(0) => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_88\, + \DYNAMIC_MASTER_MODE_FRAME_CNT.DM_GEN_FSTORE_GRTR_TWO.frame_number_i_reg[4]_0\(4 downto 0) => s2mm_frame_number(4 downto 0), + \ENABLE_DMACR_DELAY_CNTR.irqdelay_wren_i_reg\ => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_81\, + \ENABLE_DMACR_FRM_CNTR.irqthresh_wren_i_reg\ => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_82\, + \GEN_FOR_FLUSH.fsize_err_reg\ => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_62\, + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6]\ => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_71\, + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_cnt_reg[6]_0\(0) => p_4_out_10, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.axi2ip_wraddr_captured_s2mm_cdc_tig_reg[2]\ => AXI_LITE_REG_INTERFACE_I_n_162, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[11]\ => AXI_LITE_REG_INTERFACE_I_n_168, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[12]\ => AXI_LITE_REG_INTERFACE_I_n_169, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[13]\ => AXI_LITE_REG_INTERFACE_I_n_170, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[15]\ => AXI_LITE_REG_INTERFACE_I_n_171, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[18]\(0) => AXI_LITE_REG_INTERFACE_I_n_128, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4]\ => AXI_LITE_REG_INTERFACE_I_n_165, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[4]_0\ => \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_60\, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[7]\ => AXI_LITE_REG_INTERFACE_I_n_166, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[8]\ => AXI_LITE_REG_INTERFACE_I_n_167, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(31) => AXI_LITE_REG_INTERFACE_I_n_129, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(30) => AXI_LITE_REG_INTERFACE_I_n_130, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(29) => AXI_LITE_REG_INTERFACE_I_n_131, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(28) => AXI_LITE_REG_INTERFACE_I_n_132, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(27) => AXI_LITE_REG_INTERFACE_I_n_133, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(26) => AXI_LITE_REG_INTERFACE_I_n_134, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(25) => AXI_LITE_REG_INTERFACE_I_n_135, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(24) => AXI_LITE_REG_INTERFACE_I_n_136, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(23) => AXI_LITE_REG_INTERFACE_I_n_137, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(22) => AXI_LITE_REG_INTERFACE_I_n_138, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(21) => AXI_LITE_REG_INTERFACE_I_n_139, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(20) => AXI_LITE_REG_INTERFACE_I_n_140, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(19) => AXI_LITE_REG_INTERFACE_I_n_141, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(18) => AXI_LITE_REG_INTERFACE_I_n_142, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(17) => AXI_LITE_REG_INTERFACE_I_n_143, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(16) => AXI_LITE_REG_INTERFACE_I_n_144, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(15) => AXI_LITE_REG_INTERFACE_I_n_145, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(14) => AXI_LITE_REG_INTERFACE_I_n_146, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(13) => AXI_LITE_REG_INTERFACE_I_n_147, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(12) => AXI_LITE_REG_INTERFACE_I_n_148, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(11) => AXI_LITE_REG_INTERFACE_I_n_149, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(10) => AXI_LITE_REG_INTERFACE_I_n_150, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(9) => AXI_LITE_REG_INTERFACE_I_n_151, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(8) => AXI_LITE_REG_INTERFACE_I_n_152, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(7) => AXI_LITE_REG_INTERFACE_I_n_153, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(6) => AXI_LITE_REG_INTERFACE_I_n_154, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(5) => AXI_LITE_REG_INTERFACE_I_n_155, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(4) => AXI_LITE_REG_INTERFACE_I_n_156, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(3) => AXI_LITE_REG_INTERFACE_I_n_157, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(2) => AXI_LITE_REG_INTERFACE_I_n_158, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(1) => AXI_LITE_REG_INTERFACE_I_n_159, + \GEN_NUM_FSTORES_3.reg_module_start_address2_i_reg[31]\(0) => AXI_LITE_REG_INTERFACE_I_n_160, + \GEN_REGISTER_DIRECT.GEN_REGDIRECT_DRES.video_reg_updated_reg\ => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_92\, + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_ptr_ref_cdc_tig_reg[4]\(4 downto 0) => p_83_out(4 downto 0), + \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.s2mm_ip2axi_frame_store_cdc_tig_reg[4]\(4 downto 0) => p_82_out(4 downto 0), + \GEN_START_ADDR_REG[0].start_address_vid_reg[0][31]\(31 downto 0) => \s2mm_reg_module_strt_addr[0]\(31 downto 0), + \GEN_START_ADDR_REG[1].start_address_vid_reg[1][31]\(31 downto 0) => \s2mm_reg_module_strt_addr[1]\(31 downto 0), + \GEN_START_ADDR_REG[2].start_address_vid_reg[2][31]\(31 downto 0) => \s2mm_reg_module_strt_addr[2]\(31 downto 0), + Q(6) => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_74\, + Q(5) => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_75\, + Q(4) => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_76\, + Q(3) => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_77\, + Q(2) => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_78\, + Q(1) => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_79\, + Q(0) => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_80\, + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]\ => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_59\, + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_0\ => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_60\, + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_1\ => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_61\, + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_2\ => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_63\, + \S2MM_ERR_FOR_IRQ.frm_store_i_reg[0]_3\ => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_67\, + SR(0) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF/prmry_reset2\, + ch2_delay_cnt_en => ch2_delay_cnt_en, + ch2_delay_zero => ch2_delay_zero, + ch2_dly_irq_set => s2mm_dly_irq_set, + decerr_i_reg => \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_59\, + dly_irq_reg => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_66\, + \dmacr_i_reg[2]\ => I_RST_MODULE_n_19, + err_d1_reg => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_64\, + err_d1_reg_0 => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_68\, + err_d1_reg_1(3 downto 0) => dma_irq_mask_i(3 downto 0), + err_irq_reg => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_87\, + halt_reset => \GEN_RESET_FOR_S2MM.RESET_I/halt_reset\, + halted_clr_reg => \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_57\, + \hsize_vid_reg[15]\(15 downto 0) => s2mm_reg_module_hsize(15 downto 0), + initial_frame => initial_frame_0, + ioc_irq_reg => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_65\, + irqdelay_wren_i => \I_DMA_REGISTER/irqdelay_wren_i\, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + mask_fsync_out_i => mask_fsync_out_i_8, + num_fstore_minus1(0) => num_fstore_minus1(1), + \out\(31 downto 0) => p_84_out(31 downto 0), + p_14_out => \I_DMA_REGISTER/p_14_out\, + p_15_out => \I_DMA_REGISTER/p_15_out\, + p_6_out => p_6_out, + p_in_d1_cdc_from => p_in_d1_cdc_from, + prmry_in => s2mm_ftchcmdsts_idle, + prmry_in_xored => prmry_in_xored, + prmry_resetn_i_reg => s2mm_prmry_resetn, + prmtr_update_complete => prmtr_update_complete_4, + reset_counts => \I_DMA_REGISTER/reset_counts_11\, + reset_counts_reg => I_RST_MODULE_n_32, + s2mm_axi2ip_wrce(9 downto 4) => s2mm_axi2ip_wrce(45 downto 40), + s2mm_axi2ip_wrce(3) => s2mm_axi2ip_wrce(15), + s2mm_axi2ip_wrce(2 downto 1) => s2mm_axi2ip_wrce(13 downto 12), + s2mm_axi2ip_wrce(0) => s2mm_axi2ip_wrce(10), + s2mm_cdc2dmac_fsync => s2mm_cdc2dmac_fsync, + s2mm_dmacr(22 downto 6) => s2mm_dmacr(31 downto 15), + s2mm_dmacr(5 downto 2) => s2mm_dmacr(6 downto 3), + s2mm_dmacr(1 downto 0) => s2mm_dmacr(1 downto 0), + s2mm_dmasr(0) => s2mm_dmasr(0), + s2mm_halt_cmplt => s2mm_halt_cmplt, + s2mm_ioc_irq_set => s2mm_ioc_irq_set, + s2mm_ip2axi_introut => s2mm_ip2axi_introut, + s2mm_packet_sof => s2mm_packet_sof, + s2mm_soft_reset => s2mm_soft_reset, + s2mm_stop => s2mm_stop, + s2mm_tstvect_fsync => s2mm_tstvect_fsync, + s2mm_valid_frame_sync => s2mm_valid_frame_sync, + s2mm_valid_video_prmtrs => s2mm_valid_video_prmtrs, + s_axis_cmd_tvalid_reg(0) => \VIDEO_REG_I/p_1_out\, + s_soft_reset_i0 => \GEN_RESET_FOR_S2MM.RESET_I/s_soft_reset_i0\, + slverr_i_reg => \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_58\, + \stride_vid_reg[15]\(15 downto 0) => s2mm_reg_module_stride(15 downto 0), + \vsize_vid_reg[12]\(12 downto 0) => s2mm_reg_module_vsize(12 downto 0) + ); +\GEN_SPRT_FOR_S2MM.S2MM_SOF_I\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_sof_gen_0 + port map ( + \out\ => s2mm_axis_resetn, + p_in_d1_cdc_from => \GEN_CDC_FOR_ASYNC.SOF_CDC_I/p_in_d1_cdc_from_14\, + prmry_in_xored => \GEN_CDC_FOR_ASYNC.SOF_CDC_I/prmry_in_xored_12\, + prmry_reset2 => \I_SM/GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF/prmry_reset2\, + s2mm_fsync_out_i => s2mm_fsync_out_i, + s_axis_s2mm_aclk => s_axis_s2mm_aclk, + s_valid0 => s_valid0_9 + ); +\GEN_SPRT_FOR_S2MM.S2MM_VID_CDC_I\: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_vid_cdc_1 + port map ( + \DYNAMIC_GENLOCK_FOR_MASTER.frame_ptr_out_reg[2]\(2 downto 0) => s2mm_m_frame_ptr_out(2 downto 0), + E(0) => strm_all_lines_rcvd_no_dwidth, + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ => \GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I_n_17\, + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[0]\ => \GEN_SPRT_FOR_S2MM.S2MM_VID_CDC_I_n_5\, + \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth_reg[6]\ => \GEN_SPRT_FOR_S2MM.GEN_NO_AXIS_S2MM_DWIDTH_CONV.vsize_counter_no_dwidth[12]_i_4_n_0\, + M_Last => p_96_out, + Q(0) => vsize_counter_no_dwidth(0), + SR(0) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF/prmry_reset2\, + \frame_ptr_out_reg[2]\(2 downto 0) => s2mm_s_frame_ptr_in(2 downto 0), + irqdelay_wren_i => \I_DMA_REGISTER/irqdelay_wren_i\, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + p_in_d1_cdc_from => \GEN_CDC_FOR_ASYNC.SOF_CDC_I/p_in_d1_cdc_from_14\, + p_in_d1_cdc_from_0 => \GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/p_in_d1_cdc_from_13\, + p_in_d1_cdc_from_3 => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF/p_in_d1_cdc_from\, + prmry_in_xored => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.FSYNC_OUT_CDC_I_FLUSH_SOF/prmry_in_xored\, + prmry_in_xored_1 => \GEN_CDC_FOR_ASYNC.SOF_CDC_I/prmry_in_xored_12\, + prmry_in_xored_2 => \GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I/prmry_in_xored_7\, + prmry_reset2 => \I_SM/GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF/prmry_reset2\, + reset_counts => \I_DMA_REGISTER/reset_counts_11\, + s2mm_cdc2dmac_fsync => s2mm_cdc2dmac_fsync, + s2mm_frame_ptr_in(5 downto 0) => s2mm_frame_ptr_in(5 downto 0), + s2mm_frame_ptr_out(5 downto 0) => s2mm_frame_ptr_out(5 downto 0), + s2mm_fsync_core => s2mm_fsync_core, + s2mm_fsync_out_i => s2mm_fsync_out_i, + s2mm_packet_sof => s2mm_packet_sof, + s2mm_valid_frame_sync_cmb => s2mm_valid_frame_sync_cmb, + s2mm_valid_video_prmtrs => s2mm_valid_video_prmtrs, + s_axis_s2mm_aclk => s_axis_s2mm_aclk ); GND: unisim.vcomponents.GND port map ( @@ -38531,50 +94902,94 @@ GND: unisim.vcomponents.GND ); I_AXI_DMA_INTRPT: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_intrpt port map ( - D(0) => p_2_in(0), - E(0) => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_173\, - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\(0) => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_68\, - \GEN_FREE_RUN_MODE.mask_fsync_out_i_reg\(7 downto 0) => mm2s_irqthresh_status(7 downto 0), - \GEN_FREE_RUN_MODE.mask_fsync_out_i_reg_0\ => I_AXI_DMA_INTRPT_n_21, - \MASTER_MODE_FRAME_CNT.tstvect_fsync_reg\ => \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_34\, + E(0) => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_72\, + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_65\, + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.P_IN_CROSS2SCNDRY_scndry_out_0\ => \GEN_SPRT_FOR_S2MM.S2MM_VID_CDC_I_n_5\, + \GEN_FREE_RUN_MODE.mask_fsync_out_i_reg\ => I_AXI_DMA_INTRPT_n_39, + \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg\ => \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_15\, + \GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.fsize_mismatch_err_flag_int_reg_0\ => \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_16\, + \GEN_FSYNC_MODE_S2MM_FLUSH_SOF.mask_fsync_out_i_reg\ => I_AXI_DMA_INTRPT_n_40, + \GEN_INCLUDE_MM2S.GEN_CH1_DELAY_INTERRUPT.ch1_dly_irq_set_i_reg_0\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_63\, + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[7]_0\(7 downto 0) => mm2s_irqthresh_status(7 downto 0), + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_cnt_en_reg_0\(0) => p_4_out_10, + \GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count_reg[7]_0\(7 downto 0) => s2mm_irqdelay_status(7 downto 0), + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[7]_0\(7 downto 0) => s2mm_irqthresh_status(7 downto 0), + \MASTER_MODE_FRAME_CNT.tstvect_fsync_reg\ => \GEN_SPRT_FOR_MM2S.MM2S_REGISTER_MODULE_I_n_62\, Q(7 downto 0) => mm2s_irqdelay_status(7 downto 0), - SR(0) => p_4_out, + SR(0) => p_11_out, ch1_delay_cnt_en => ch1_delay_cnt_en, - \ch1_delay_zero__6\ => \ch1_delay_zero__6\, - \ch1_ioc_irq_set_i__0\ => \ch1_ioc_irq_set_i__0\, + ch1_delay_zero => ch1_delay_zero, + ch1_dly_irq_set => mm2s_dly_irq_set, + ch2_delay_cnt_en => ch2_delay_cnt_en, + ch2_delay_zero => ch2_delay_zero, + ch2_dly_irq_set => s2mm_dly_irq_set, + ch2_irqthresh_decr_mask_sig => ch2_irqthresh_decr_mask_sig, m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, mask_fsync_out_i => mask_fsync_out_i, - mm2s_dly_irq_set => mm2s_dly_irq_set, + mask_fsync_out_i_1 => mask_fsync_out_i_8, mm2s_ioc_irq_set => mm2s_ioc_irq_set, \out\ => mm2s_prmry_resetn, - p_10_out => p_10_out, + p_13_out => p_13_out, p_17_out => p_17_out, - p_23_out => p_23_out, - p_46_out => p_46_out, - p_49_out => p_49_out, - p_68_out(15 downto 1) => p_68_out(31 downto 17), - p_68_out(0) => p_68_out(4), - \p_6_out__1\ => \p_6_out__1\, - prmry_resetn_i_reg(0) => p_0_in + p_4_out => p_4_out, + p_4_out_0 => p_4_out_6, + p_50_out => p_50_out, + p_6_out => p_6_out, + p_71_out(15 downto 0) => p_71_out(31 downto 16), + prmry_resetn_i_reg(0) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF/prmry_reset2\, + prmry_resetn_i_reg_0 => s2mm_prmry_resetn, + prmry_resetn_i_reg_1 => \GEN_SPRT_FOR_S2MM.S2MM_REGISTER_MODULE_I_n_71\, + prmry_resetn_i_reg_2(0) => \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I/prmry_reset2\, + s2mm_dmacr(15 downto 0) => s2mm_dmacr(31 downto 16), + s2mm_ioc_irq_set => s2mm_ioc_irq_set, + s2mm_packet_sof => s2mm_packet_sof, + s2mm_tstvect_fsync => s2mm_tstvect_fsync ); I_PRMRY_DATAMOVER: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover port map ( - E(0) => I_PRMRY_DATAMOVER_n_6, - Q(0) => \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_rd_empty\, + CO(0) => I_PRMRY_DATAMOVER_n_29, + DI(10) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_dre2ibtt_eop_reg\, + DI(9) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_dre2ibtt_tlast_reg\, + DI(8 downto 0) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_byte_cntr\(8 downto 0), + DIN(0) => dm2linebuf_mm2s_tlast, + DOUT(8) => linebuf2dm_s2mm_tlast, + DOUT(7 downto 0) => linebuf2dm_s2mm_tdata(7 downto 0), + E(0) => I_PRMRY_DATAMOVER_n_22, + EMPTY => fifo_empty_i, + FIFO_Full_reg(0) => \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_rd_empty\, + \GEN_STS_GRTR_THAN_8.ovrflo_err_reg\(0) => m_axis_s2mm_sts_tdata(8), + \INCLUDE_UNPACKING.lsig_0ffset_cntr_reg[0]\ => \GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_7\, + Q(0) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_rd_empty\, + RD_EN => fifo_rden, + S(0) => \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_53\, cmnd_wr => cmnd_wr, - decerr_i_reg => I_PRMRY_DATAMOVER_n_43, + cmnd_wr_1 => cmnd_wr_5, + datamover_idle => \I_STS_MNGR/datamover_idle\, + datamover_idle_2 => \I_STS_MNGR/datamover_idle_3\, + datamover_idle_reg => I_PRMRY_DATAMOVER_n_23, + datamover_idle_reg_0 => I_PRMRY_DATAMOVER_n_30, + decerr_i_reg => I_PRMRY_DATAMOVER_n_32, + decerr_i_reg_0 => I_PRMRY_DATAMOVER_n_36, dm2linebuf_mm2s_tdata(31 downto 0) => dm2linebuf_mm2s_tdata(31 downto 0), - dm2linebuf_mm2s_tvalid => dm2linebuf_mm2s_tvalid, - \fifo_wren__0\ => \fifo_wren__0\, - halt_i_reg => I_RST_MODULE_n_17, - \in\(48 downto 17) => p_56_out(63 downto 32), - \in\(16) => p_56_out(23), - \in\(15 downto 0) => p_56_out(15 downto 0), - interr_i_reg => I_PRMRY_DATAMOVER_n_41, + dma_err => dma_err_2, + \gcc0.gc0.count_d1_reg[0]\(0) => I_PRMRY_DATAMOVER_n_39, + \gpr1.dout_i_reg[1]\(2 downto 0) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_0_out\(2 downto 0), + \gpr1.dout_i_reg[1]_0\(2 downto 0) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_11_out\(2 downto 0), + halt_i_reg => I_RST_MODULE_n_30, + halt_i_reg_0 => I_RST_MODULE_n_33, + \hsize_vid_reg[15]\(12 downto 0) => crnt_hsize(15 downto 3), + \hsize_vid_reg[2]\(0) => \GEN_SPRT_FOR_S2MM.S2MMADDR32.I_S2MM_DMA_MNGR_n_54\, + \in\(48 downto 17) => p_57_out(63 downto 32), + \in\(16) => p_57_out(23), + \in\(15 downto 0) => p_57_out(15 downto 0), + interr_i_reg => I_PRMRY_DATAMOVER_n_35, + interr_i_reg_0 => I_PRMRY_DATAMOVER_n_38, + lsig_0ffset_cntr => \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/lsig_0ffset_cntr\, m_axi_mm2s_aclk => m_axi_mm2s_aclk, m_axi_mm2s_araddr(31 downto 0) => m_axi_mm2s_araddr(31 downto 0), m_axi_mm2s_arburst(0) => \^m_axi_mm2s_arburst\(0), - m_axi_mm2s_arlen(3 downto 0) => \^m_axi_mm2s_arlen\(3 downto 0), + m_axi_mm2s_arlen(4 downto 0) => \^m_axi_mm2s_arlen\(4 downto 0), m_axi_mm2s_arready => m_axi_mm2s_arready, m_axi_mm2s_arsize(1 downto 0) => \^m_axi_mm2s_arsize\(1 downto 0), m_axi_mm2s_arvalid => m_axi_mm2s_arvalid, @@ -38583,58 +94998,134 @@ I_PRMRY_DATAMOVER: entity work.Arty_Z7_20_axi_vdma_0_0_axi_datamover m_axi_mm2s_rready => m_axi_mm2s_rready, m_axi_mm2s_rresp(1 downto 0) => m_axi_mm2s_rresp(1 downto 0), m_axi_mm2s_rvalid => m_axi_mm2s_rvalid, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + m_axi_s2mm_awaddr(31 downto 0) => m_axi_s2mm_awaddr(31 downto 0), + m_axi_s2mm_awburst(0) => \^m_axi_s2mm_awburst\(0), + m_axi_s2mm_awlen(5 downto 0) => \^m_axi_s2mm_awlen\(5 downto 0), + m_axi_s2mm_awready => m_axi_s2mm_awready, + m_axi_s2mm_awsize(1 downto 0) => \^m_axi_s2mm_awsize\(1 downto 0), + m_axi_s2mm_awvalid => m_axi_s2mm_awvalid, + m_axi_s2mm_bready => m_axi_s2mm_bready, + m_axi_s2mm_bresp(1 downto 0) => m_axi_s2mm_bresp(1 downto 0), + m_axi_s2mm_bvalid => m_axi_s2mm_bvalid, + m_axi_s2mm_wdata(63 downto 0) => m_axi_s2mm_wdata(63 downto 0), + m_axi_s2mm_wlast => m_axi_s2mm_wlast, + m_axi_s2mm_wready => m_axi_s2mm_wready, + m_axi_s2mm_wvalid => m_axi_s2mm_wvalid, + m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready, mm2s_halt => mm2s_halt, mm2s_halt_cmplt => mm2s_halt_cmplt, \out\ => mm2s_dm_prmry_resetn, - p_55_out => p_55_out, - p_57_out => p_57_out, - p_8_out => p_8_out, + p_0_out(10) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_n_5\, + p_0_out(9) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_n_2\, + p_0_out(8) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_n_3\, + p_0_out(7) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_n_0\, + p_0_out(6) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_6_10_n_1\, + p_0_out(5) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_4\, + p_0_out(4) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_5\, + p_0_out(3) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_2\, + p_0_out(2) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_3\, + p_0_out(1) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_0\, + p_0_out(0) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_7_0_5_n_1\, + p_56_out => p_56_out, + p_58_out => p_58_out, + p_71_out(0) => p_71_out(0), + p_9_out => \I_CMDSTS/p_9_out\, + prmry_resetn_i_reg => \GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_8\, + s2mm_dmacr(0) => s2mm_dmacr(0), + s2mm_halt => s2mm_halt, + s2mm_halt_cmplt => s2mm_halt_cmplt, + s2mm_soft_reset => s2mm_soft_reset, + \s_axis_cmd_tdata_reg[63]\(48 downto 17) => s_axis_s2mm_cmd_tdata(63 downto 32), + \s_axis_cmd_tdata_reg[63]\(16) => s_axis_s2mm_cmd_tdata(23), + \s_axis_cmd_tdata_reg[63]\(15 downto 0) => s_axis_s2mm_cmd_tdata(15 downto 0), + s_axis_cmd_tvalid_reg(0) => I_PRMRY_DATAMOVER_n_28, + s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid, + s_soft_reset_i_reg => s2mm_dm_prmry_resetn, + \sig_data_skid_reg_reg[7]\ => dm2linebuf_s2mm_tready, sig_rst2all_stop_request => \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/sig_rst2all_stop_request\, - \sig_user_skid_reg_reg[0]\(0) => dm2linebuf_mm2s_tlast, - slverr_i_reg => I_PRMRY_DATAMOVER_n_42, - sts_tready_reg => \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_38\ + sig_rst2all_stop_request_0 => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/sig_rst2all_stop_request\, + \sig_user_skid_reg_reg[0]\ => I_PRMRY_DATAMOVER_n_191, + slverr_i_reg => I_PRMRY_DATAMOVER_n_34, + slverr_i_reg_0 => I_PRMRY_DATAMOVER_n_37, + sts_tready_reg => \GEN_SPRT_FOR_MM2S.ADDR32.I_MM2S_DMA_MNGR_n_31\ ); I_RST_MODULE: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma_rst_module port map ( + CO(0) => I_PRMRY_DATAMOVER_n_29, D(0) => mm2s_axi2ip_wrdata(2), - DIN(0) => sof_flag, - \FSM_sequential_dmacntrl_cs_reg[1]\ => p_37_out, + \FSM_sequential_dmacntrl_cs_reg[2]\ => I_RST_MODULE_n_22, + FULL => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/p_5_out\, \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ => \GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I_n_3\, - \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ => mm2s_axis_resetn, + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\ => p_39_out, + \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from\ => s2mm_axis_resetn, \GENERATE_PULSE_P_S_CDC_OPEN_ENDED.REG_P_IN_cdc_from_0\(0) => \GEN_CDC_FOR_ASYNC.PRMTR_UPDT_CDC_I/scndry_reset2\, - \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0]\(0) => p_0_in, - \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SOF.sof_flag_reg\ => I_RST_MODULE_n_14, - \GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]\(0) => p_7_out, - SR(0) => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.MM2S_INTRPT_CROSSING_I/scndry_reset2\, + \GEN_INCLUDE_MM2S.GEN_CH1_FRM_CNTR.ch1_thresh_count_reg[0]\(0) => \GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I/prmry_reset2\, + \GEN_INCLUDE_S2MM.GEN_CH2_FRM_CNTR.ch2_thresh_count_reg[1]\(0) => \GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.MMAP_NOT_FINISHED_CDC_I_FLUSH_SOF/prmry_reset2\, + \GEN_LINEBUF_NO_SOF.s_axis_fifo_ainit_nosync_reg_reg\ => I_RST_MODULE_n_29, + \GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]\ => mm2s_axis_resetn, + \GEN_LINEBUF_NO_SOF.vsize_counter_reg[12]_0\(0) => p_7_out, + \GEN_LITE_IS_ASYNC.GEN_ASYNC_LITE_ACCESS.s2mm_axi2ip_wrdata_cdc_tig_reg[2]\(0) => s2mm_axi2ip_wrdata(2), + \GEN_SPRT_FOR_S2MM.GEN_FLUSH_SOF_TREADY.d_tready_before_fsync_reg\ => I_RST_MODULE_n_28, + Q(0) => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_rd_empty\, + SR(0) => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.S2MM_INTRPT_CROSSING_I/scndry_reset2\, + WR_EN => I_RST_MODULE_n_25, axi_resetn => axi_resetn, - \cmnds_queued_reg[7]\(0) => I_RST_MODULE_n_15, - dm2linebuf_mm2s_tvalid => dm2linebuf_mm2s_tvalid, - dma_err => dma_err, - \dmacr_i_reg[2]\ => I_RST_MODULE_n_13, - fifo_full_i => fifo_full_i, - \fifo_wren__0\ => \fifo_wren__0\, + \cmnds_queued_reg[0]\ => s2mm_ftchcmdsts_idle, + \cmnds_queued_reg[7]\(0) => I_RST_MODULE_n_26, + \cmnds_queued_reg[7]_0\(0) => I_RST_MODULE_n_27, + d_tready_before_fsync => d_tready_before_fsync, + d_tready_before_fsync_clr_flag1 => d_tready_before_fsync_clr_flag1, + dma_err => dma_err_2, + dma_err_4 => dma_err, + \dmacr_i_reg[2]\ => I_RST_MODULE_n_16, + \dmacr_i_reg[2]_0\ => I_RST_MODULE_n_19, + halt_i0 => \GEN_RESET_FOR_S2MM.RESET_I/halt_i0\, halt_reset => \GEN_RESET_FOR_MM2S.RESET_I/halt_reset\, + halt_reset_2 => \GEN_RESET_FOR_S2MM.RESET_I/halt_reset\, + hold_ff_q_reg => I_PRMRY_DATAMOVER_n_191, m_axi_mm2s_aclk => m_axi_mm2s_aclk, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, m_axis_mm2s_aclk => m_axis_mm2s_aclk, mm2s_axi2ip_wrce(0) => mm2s_axi2ip_wrce(0), mm2s_halt => mm2s_halt, mm2s_halt_cmplt => mm2s_halt_cmplt, \out\ => mm2s_prmry_resetn, + p_12_out => \I_CMDSTS/p_12_out\, p_15_out => p_15_out, - p_23_out => p_23_out, - p_35_out => p_35_out, - p_68_out(1) => p_68_out(2), - p_68_out(0) => p_68_out(0), - p_8_out => p_8_out, + p_24_out => p_24_out, + p_71_out(0) => p_71_out(0), + p_77_out => p_77_out, prmry_in => s_axi_lite_resetn, prmry_reset2 => \GEN_MM2S_LITE_CROSSINGS.GEN_MM2S_CROSSINGS_ASYNC.MM2S_INTRPT_CROSSING_I/prmry_reset2\, + prmry_reset2_0 => \GEN_S2MM_LITE_CROSSINGS.GEN_S2MM_CROSSINGS_ASYNC.S2MM_INTRPT_CROSSING_I/prmry_reset2\, + prmry_reset2_1 => \I_SM/GEN_FSIZE_MISMATCH.GEN_S2MM_MISMATCH_FLUSH_SOF.GEN_FOR_ASYNC.FSIZE_MISMATCH_CDC_I_FLUSH_SOF/prmry_reset2\, reset_counts => \I_DMA_REGISTER/reset_counts\, - reset_counts_reg => I_RST_MODULE_n_16, + reset_counts_5 => \I_DMA_REGISTER/reset_counts_11\, + reset_counts_reg => I_RST_MODULE_n_31, + reset_counts_reg_0 => I_RST_MODULE_n_32, + run_stop_d1 => \GEN_RESET_FOR_S2MM.RESET_I/run_stop_d1\, + s2mm_axi2ip_wrce(0) => s2mm_axi2ip_wrce(12), + s2mm_dmacr(0) => s2mm_dmacr(0), + s2mm_dmasr_halted_s => s2mm_dmasr_halted_s, + s2mm_halt => s2mm_halt, + s2mm_halt_cmplt => s2mm_halt_cmplt, + s2mm_soft_reset => s2mm_soft_reset, + s2mm_stop => s2mm_stop, s_axi_lite_aclk => s_axi_lite_aclk, + s_axis_s2mm_aclk => s_axis_s2mm_aclk, s_soft_reset_i0 => \GEN_RESET_FOR_MM2S.RESET_I/s_soft_reset_i0\, + s_soft_reset_i0_3 => \GEN_RESET_FOR_S2MM.RESET_I/s_soft_reset_i0\, \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0\ => mm2s_dm_prmry_resetn, + \sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0_0\ => s2mm_dm_prmry_resetn, sig_rst2all_stop_request => \GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/sig_rst2all_stop_request\, - sig_s_h_halt_reg_reg => I_RST_MODULE_n_17 + sig_rst2all_stop_request_6 => \GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/sig_rst2all_stop_request\, + sig_s_h_halt_reg_reg => I_RST_MODULE_n_30, + sig_s_h_halt_reg_reg_0 => I_RST_MODULE_n_33, + sig_s_ready_out_reg => \GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/p_8_out\, + soft_reset_d1 => \GEN_RESET_FOR_S2MM.RESET_I/soft_reset_d1\, + stop => p_36_out, + sts_tready_reg => s2mm_prmry_resetn ); VCC: unisim.vcomponents.VCC port map ( @@ -38650,6 +95141,8 @@ entity Arty_Z7_20_axi_vdma_0_0 is s_axi_lite_aclk : in STD_LOGIC; m_axi_mm2s_aclk : in STD_LOGIC; m_axis_mm2s_aclk : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC; axi_resetn : in STD_LOGIC; s_axi_lite_awvalid : in STD_LOGIC; s_axi_lite_awready : out STD_LOGIC; @@ -38668,6 +95161,8 @@ entity Arty_Z7_20_axi_vdma_0_0 is s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); mm2s_frame_ptr_out : out STD_LOGIC_VECTOR ( 5 downto 0 ); + s2mm_frame_ptr_in : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s2mm_frame_ptr_out : out STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); @@ -38687,7 +95182,30 @@ entity Arty_Z7_20_axi_vdma_0_0 is m_axis_mm2s_tvalid : out STD_LOGIC; m_axis_mm2s_tready : in STD_LOGIC; m_axis_mm2s_tlast : out STD_LOGIC; - mm2s_introut : out STD_LOGIC + m_axi_s2mm_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_s2mm_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_s2mm_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_s2mm_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_s2mm_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_s2mm_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_s2mm_awvalid : out STD_LOGIC; + m_axi_s2mm_awready : in STD_LOGIC; + m_axi_s2mm_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_s2mm_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_s2mm_wlast : out STD_LOGIC; + m_axi_s2mm_wvalid : out STD_LOGIC; + m_axi_s2mm_wready : in STD_LOGIC; + m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_s2mm_bvalid : in STD_LOGIC; + m_axi_s2mm_bready : out STD_LOGIC; + s_axis_s2mm_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axis_s2mm_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axis_s2mm_tuser : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axis_s2mm_tvalid : in STD_LOGIC; + s_axis_s2mm_tready : out STD_LOGIC; + s_axis_s2mm_tlast : in STD_LOGIC; + mm2s_introut : out STD_LOGIC; + s2mm_introut : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of Arty_Z7_20_axi_vdma_0_0 : entity is true; @@ -38700,10 +95218,6 @@ entity Arty_Z7_20_axi_vdma_0_0 is end Arty_Z7_20_axi_vdma_0_0; architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0 is - signal NLW_U0_m_axi_s2mm_awvalid_UNCONNECTED : STD_LOGIC; - signal NLW_U0_m_axi_s2mm_bready_UNCONNECTED : STD_LOGIC; - signal NLW_U0_m_axi_s2mm_wlast_UNCONNECTED : STD_LOGIC; - signal NLW_U0_m_axi_s2mm_wvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axi_sg_arvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axi_sg_rready_UNCONNECTED : STD_LOGIC; signal NLW_U0_mm2s_buffer_almost_empty_UNCONNECTED : STD_LOGIC; @@ -38714,26 +95228,15 @@ architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0 is signal NLW_U0_s2mm_buffer_almost_full_UNCONNECTED : STD_LOGIC; signal NLW_U0_s2mm_buffer_full_UNCONNECTED : STD_LOGIC; signal NLW_U0_s2mm_fsync_out_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s2mm_introut_UNCONNECTED : STD_LOGIC; signal NLW_U0_s2mm_prmry_reset_out_n_UNCONNECTED : STD_LOGIC; signal NLW_U0_s2mm_prmtr_update_UNCONNECTED : STD_LOGIC; - signal NLW_U0_s_axis_s2mm_tready_UNCONNECTED : STD_LOGIC; signal NLW_U0_axi_vdma_tstvec_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); - signal NLW_U0_m_axi_s2mm_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal NLW_U0_m_axi_s2mm_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal NLW_U0_m_axi_s2mm_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal NLW_U0_m_axi_s2mm_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); - signal NLW_U0_m_axi_s2mm_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal NLW_U0_m_axi_s2mm_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal NLW_U0_m_axi_s2mm_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); - signal NLW_U0_m_axi_s2mm_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_m_axi_sg_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_U0_m_axi_sg_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_m_axi_sg_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_m_axi_sg_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_m_axi_sg_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_U0_m_axi_sg_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal NLW_U0_s2mm_frame_ptr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); attribute C_DLYTMR_RESOLUTION : integer; attribute C_DLYTMR_RESOLUTION of U0 : label is 125; attribute C_DYNAMIC_RESOLUTION : integer; @@ -38787,7 +95290,7 @@ architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0 is attribute C_INCLUDE_MM2S_SF : integer; attribute C_INCLUDE_MM2S_SF of U0 : label is 0; attribute C_INCLUDE_S2MM : integer; - attribute C_INCLUDE_S2MM of U0 : label is 0; + attribute C_INCLUDE_S2MM of U0 : label is 1; attribute C_INCLUDE_S2MM_DRE : integer; attribute C_INCLUDE_S2MM_DRE of U0 : label is 0; attribute C_INCLUDE_S2MM_SF : integer; @@ -38803,11 +95306,11 @@ architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0 is attribute C_MM2S_GENLOCK_REPEAT_EN : integer; attribute C_MM2S_GENLOCK_REPEAT_EN of U0 : label is 0; attribute C_MM2S_LINEBUFFER_DEPTH : integer; - attribute C_MM2S_LINEBUFFER_DEPTH of U0 : label is 4096; + attribute C_MM2S_LINEBUFFER_DEPTH of U0 : label is 2048; attribute C_MM2S_LINEBUFFER_THRESH : integer; attribute C_MM2S_LINEBUFFER_THRESH of U0 : label is 4; attribute C_MM2S_MAX_BURST_LENGTH : integer; - attribute C_MM2S_MAX_BURST_LENGTH of U0 : label is 16; + attribute C_MM2S_MAX_BURST_LENGTH of U0 : label is 32; attribute C_MM2S_SOF_ENABLE : integer; attribute C_MM2S_SOF_ENABLE of U0 : label is 1; attribute C_M_AXIS_MM2S_TDATA_WIDTH : integer; @@ -38827,27 +95330,27 @@ architecture STRUCTURE of Arty_Z7_20_axi_vdma_0_0 is attribute C_M_AXI_SG_DATA_WIDTH : integer; attribute C_M_AXI_SG_DATA_WIDTH of U0 : label is 32; attribute C_NUM_FSTORES : integer; - attribute C_NUM_FSTORES of U0 : label is 1; + attribute C_NUM_FSTORES of U0 : label is 3; attribute C_PRMRY_IS_ACLK_ASYNC : integer; attribute C_PRMRY_IS_ACLK_ASYNC of U0 : label is 1; attribute C_S2MM_GENLOCK_MODE : integer; - attribute C_S2MM_GENLOCK_MODE of U0 : label is 0; + attribute C_S2MM_GENLOCK_MODE of U0 : label is 2; attribute C_S2MM_GENLOCK_NUM_MASTERS : integer; attribute C_S2MM_GENLOCK_NUM_MASTERS of U0 : label is 1; attribute C_S2MM_GENLOCK_REPEAT_EN : integer; attribute C_S2MM_GENLOCK_REPEAT_EN of U0 : label is 1; attribute C_S2MM_LINEBUFFER_DEPTH : integer; - attribute C_S2MM_LINEBUFFER_DEPTH of U0 : label is 512; + attribute C_S2MM_LINEBUFFER_DEPTH of U0 : label is 2048; attribute C_S2MM_LINEBUFFER_THRESH : integer; attribute C_S2MM_LINEBUFFER_THRESH of U0 : label is 4; attribute C_S2MM_MAX_BURST_LENGTH : integer; - attribute C_S2MM_MAX_BURST_LENGTH of U0 : label is 8; + attribute C_S2MM_MAX_BURST_LENGTH of U0 : label is 32; attribute C_S2MM_SOF_ENABLE : integer; attribute C_S2MM_SOF_ENABLE of U0 : label is 1; attribute C_SELECT_XPM : integer; attribute C_SELECT_XPM of U0 : label is 0; attribute C_S_AXIS_S2MM_TDATA_WIDTH : integer; - attribute C_S_AXIS_S2MM_TDATA_WIDTH of U0 : label is 32; + attribute C_S_AXIS_S2MM_TDATA_WIDTH of U0 : label is 8; attribute C_S_AXIS_S2MM_TUSER_BITS : integer; attribute C_S_AXIS_S2MM_TUSER_BITS of U0 : label is 1; attribute C_S_AXI_LITE_ADDR_WIDTH : integer; @@ -38886,23 +95389,23 @@ U0: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma m_axi_mm2s_rready => m_axi_mm2s_rready, m_axi_mm2s_rresp(1 downto 0) => m_axi_mm2s_rresp(1 downto 0), m_axi_mm2s_rvalid => m_axi_mm2s_rvalid, - m_axi_s2mm_aclk => '0', - m_axi_s2mm_awaddr(31 downto 0) => NLW_U0_m_axi_s2mm_awaddr_UNCONNECTED(31 downto 0), - m_axi_s2mm_awburst(1 downto 0) => NLW_U0_m_axi_s2mm_awburst_UNCONNECTED(1 downto 0), - m_axi_s2mm_awcache(3 downto 0) => NLW_U0_m_axi_s2mm_awcache_UNCONNECTED(3 downto 0), - m_axi_s2mm_awlen(7 downto 0) => NLW_U0_m_axi_s2mm_awlen_UNCONNECTED(7 downto 0), - m_axi_s2mm_awprot(2 downto 0) => NLW_U0_m_axi_s2mm_awprot_UNCONNECTED(2 downto 0), - m_axi_s2mm_awready => '0', - m_axi_s2mm_awsize(2 downto 0) => NLW_U0_m_axi_s2mm_awsize_UNCONNECTED(2 downto 0), - m_axi_s2mm_awvalid => NLW_U0_m_axi_s2mm_awvalid_UNCONNECTED, - m_axi_s2mm_bready => NLW_U0_m_axi_s2mm_bready_UNCONNECTED, - m_axi_s2mm_bresp(1 downto 0) => B"00", - m_axi_s2mm_bvalid => '0', - m_axi_s2mm_wdata(63 downto 0) => NLW_U0_m_axi_s2mm_wdata_UNCONNECTED(63 downto 0), - m_axi_s2mm_wlast => NLW_U0_m_axi_s2mm_wlast_UNCONNECTED, - m_axi_s2mm_wready => '0', - m_axi_s2mm_wstrb(7 downto 0) => NLW_U0_m_axi_s2mm_wstrb_UNCONNECTED(7 downto 0), - m_axi_s2mm_wvalid => NLW_U0_m_axi_s2mm_wvalid_UNCONNECTED, + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + m_axi_s2mm_awaddr(31 downto 0) => m_axi_s2mm_awaddr(31 downto 0), + m_axi_s2mm_awburst(1 downto 0) => m_axi_s2mm_awburst(1 downto 0), + m_axi_s2mm_awcache(3 downto 0) => m_axi_s2mm_awcache(3 downto 0), + m_axi_s2mm_awlen(7 downto 0) => m_axi_s2mm_awlen(7 downto 0), + m_axi_s2mm_awprot(2 downto 0) => m_axi_s2mm_awprot(2 downto 0), + m_axi_s2mm_awready => m_axi_s2mm_awready, + m_axi_s2mm_awsize(2 downto 0) => m_axi_s2mm_awsize(2 downto 0), + m_axi_s2mm_awvalid => m_axi_s2mm_awvalid, + m_axi_s2mm_bready => m_axi_s2mm_bready, + m_axi_s2mm_bresp(1 downto 0) => m_axi_s2mm_bresp(1 downto 0), + m_axi_s2mm_bvalid => m_axi_s2mm_bvalid, + m_axi_s2mm_wdata(63 downto 0) => m_axi_s2mm_wdata(63 downto 0), + m_axi_s2mm_wlast => m_axi_s2mm_wlast, + m_axi_s2mm_wready => m_axi_s2mm_wready, + m_axi_s2mm_wstrb(7 downto 0) => m_axi_s2mm_wstrb(7 downto 0), + m_axi_s2mm_wvalid => m_axi_s2mm_wvalid, m_axi_sg_aclk => '0', m_axi_sg_araddr(31 downto 0) => NLW_U0_m_axi_sg_araddr_UNCONNECTED(31 downto 0), m_axi_sg_arburst(1 downto 0) => NLW_U0_m_axi_sg_arburst_UNCONNECTED(1 downto 0), @@ -38935,11 +95438,11 @@ U0: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma mm2s_prmtr_update => NLW_U0_mm2s_prmtr_update_UNCONNECTED, s2mm_buffer_almost_full => NLW_U0_s2mm_buffer_almost_full_UNCONNECTED, s2mm_buffer_full => NLW_U0_s2mm_buffer_full_UNCONNECTED, - s2mm_frame_ptr_in(5 downto 0) => B"000000", - s2mm_frame_ptr_out(5 downto 0) => NLW_U0_s2mm_frame_ptr_out_UNCONNECTED(5 downto 0), + s2mm_frame_ptr_in(5 downto 0) => s2mm_frame_ptr_in(5 downto 0), + s2mm_frame_ptr_out(5 downto 0) => s2mm_frame_ptr_out(5 downto 0), s2mm_fsync => '0', s2mm_fsync_out => NLW_U0_s2mm_fsync_out_UNCONNECTED, - s2mm_introut => NLW_U0_s2mm_introut_UNCONNECTED, + s2mm_introut => s2mm_introut, s2mm_prmry_reset_out_n => NLW_U0_s2mm_prmry_reset_out_n_UNCONNECTED, s2mm_prmtr_update => NLW_U0_s2mm_prmtr_update_UNCONNECTED, s_axi_lite_aclk => s_axi_lite_aclk, @@ -38959,12 +95462,12 @@ U0: entity work.Arty_Z7_20_axi_vdma_0_0_axi_vdma s_axi_lite_wdata(31 downto 0) => s_axi_lite_wdata(31 downto 0), s_axi_lite_wready => s_axi_lite_wready, s_axi_lite_wvalid => s_axi_lite_wvalid, - s_axis_s2mm_aclk => '0', - s_axis_s2mm_tdata(31 downto 0) => B"00000000000000000000000000000000", - s_axis_s2mm_tkeep(3 downto 0) => B"1111", - s_axis_s2mm_tlast => '0', - s_axis_s2mm_tready => NLW_U0_s_axis_s2mm_tready_UNCONNECTED, - s_axis_s2mm_tuser(0) => '0', - s_axis_s2mm_tvalid => '0' + s_axis_s2mm_aclk => s_axis_s2mm_aclk, + s_axis_s2mm_tdata(7 downto 0) => s_axis_s2mm_tdata(7 downto 0), + s_axis_s2mm_tkeep(0) => s_axis_s2mm_tkeep(0), + s_axis_s2mm_tlast => s_axis_s2mm_tlast, + s_axis_s2mm_tready => s_axis_s2mm_tready, + s_axis_s2mm_tuser(0) => s_axis_s2mm_tuser(0), + s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ); end STRUCTURE; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_stub.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_stub.v index 8d71566..8d4a590 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_stub.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -// Date : Fri Feb 24 16:08:16 2017 +// Date : Mon Mar 06 11:51:46 2017 // Host : WK73 running 64-bit Service Pack 1 (build 7601) // Command : write_verilog -force -mode synth_stub -// c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_stub.v +// C:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_stub.v // Design : Arty_Z7_20_axi_vdma_0_0 // Purpose : Stub declaration of top-level module interface // Device : xc7z020clg400-1 @@ -15,20 +15,28 @@ // Please paste the declaration into a Verilog source file or add the file as an additional source. (* x_core_info = "axi_vdma,Vivado 2016.4" *) module Arty_Z7_20_axi_vdma_0_0(s_axi_lite_aclk, m_axi_mm2s_aclk, - m_axis_mm2s_aclk, axi_resetn, s_axi_lite_awvalid, s_axi_lite_awready, s_axi_lite_awaddr, - s_axi_lite_wvalid, s_axi_lite_wready, s_axi_lite_wdata, s_axi_lite_bresp, - s_axi_lite_bvalid, s_axi_lite_bready, s_axi_lite_arvalid, s_axi_lite_arready, - s_axi_lite_araddr, s_axi_lite_rvalid, s_axi_lite_rready, s_axi_lite_rdata, - s_axi_lite_rresp, mm2s_frame_ptr_out, m_axi_mm2s_araddr, m_axi_mm2s_arlen, + m_axis_mm2s_aclk, m_axi_s2mm_aclk, s_axis_s2mm_aclk, axi_resetn, s_axi_lite_awvalid, + s_axi_lite_awready, s_axi_lite_awaddr, s_axi_lite_wvalid, s_axi_lite_wready, + s_axi_lite_wdata, s_axi_lite_bresp, s_axi_lite_bvalid, s_axi_lite_bready, + s_axi_lite_arvalid, s_axi_lite_arready, s_axi_lite_araddr, s_axi_lite_rvalid, + s_axi_lite_rready, s_axi_lite_rdata, s_axi_lite_rresp, mm2s_frame_ptr_out, + s2mm_frame_ptr_in, s2mm_frame_ptr_out, m_axi_mm2s_araddr, m_axi_mm2s_arlen, m_axi_mm2s_arsize, m_axi_mm2s_arburst, m_axi_mm2s_arprot, m_axi_mm2s_arcache, m_axi_mm2s_arvalid, m_axi_mm2s_arready, m_axi_mm2s_rdata, m_axi_mm2s_rresp, m_axi_mm2s_rlast, m_axi_mm2s_rvalid, m_axi_mm2s_rready, m_axis_mm2s_tdata, m_axis_mm2s_tkeep, m_axis_mm2s_tuser, m_axis_mm2s_tvalid, m_axis_mm2s_tready, - m_axis_mm2s_tlast, mm2s_introut) -/* synthesis syn_black_box black_box_pad_pin="s_axi_lite_aclk,m_axi_mm2s_aclk,m_axis_mm2s_aclk,axi_resetn,s_axi_lite_awvalid,s_axi_lite_awready,s_axi_lite_awaddr[8:0],s_axi_lite_wvalid,s_axi_lite_wready,s_axi_lite_wdata[31:0],s_axi_lite_bresp[1:0],s_axi_lite_bvalid,s_axi_lite_bready,s_axi_lite_arvalid,s_axi_lite_arready,s_axi_lite_araddr[8:0],s_axi_lite_rvalid,s_axi_lite_rready,s_axi_lite_rdata[31:0],s_axi_lite_rresp[1:0],mm2s_frame_ptr_out[5:0],m_axi_mm2s_araddr[31:0],m_axi_mm2s_arlen[7:0],m_axi_mm2s_arsize[2:0],m_axi_mm2s_arburst[1:0],m_axi_mm2s_arprot[2:0],m_axi_mm2s_arcache[3:0],m_axi_mm2s_arvalid,m_axi_mm2s_arready,m_axi_mm2s_rdata[63:0],m_axi_mm2s_rresp[1:0],m_axi_mm2s_rlast,m_axi_mm2s_rvalid,m_axi_mm2s_rready,m_axis_mm2s_tdata[31:0],m_axis_mm2s_tkeep[3:0],m_axis_mm2s_tuser[0:0],m_axis_mm2s_tvalid,m_axis_mm2s_tready,m_axis_mm2s_tlast,mm2s_introut" */; + m_axis_mm2s_tlast, m_axi_s2mm_awaddr, m_axi_s2mm_awlen, m_axi_s2mm_awsize, + m_axi_s2mm_awburst, m_axi_s2mm_awprot, m_axi_s2mm_awcache, m_axi_s2mm_awvalid, + m_axi_s2mm_awready, m_axi_s2mm_wdata, m_axi_s2mm_wstrb, m_axi_s2mm_wlast, + m_axi_s2mm_wvalid, m_axi_s2mm_wready, m_axi_s2mm_bresp, m_axi_s2mm_bvalid, + m_axi_s2mm_bready, s_axis_s2mm_tdata, s_axis_s2mm_tkeep, s_axis_s2mm_tuser, + s_axis_s2mm_tvalid, s_axis_s2mm_tready, s_axis_s2mm_tlast, mm2s_introut, s2mm_introut) +/* synthesis syn_black_box black_box_pad_pin="s_axi_lite_aclk,m_axi_mm2s_aclk,m_axis_mm2s_aclk,m_axi_s2mm_aclk,s_axis_s2mm_aclk,axi_resetn,s_axi_lite_awvalid,s_axi_lite_awready,s_axi_lite_awaddr[8:0],s_axi_lite_wvalid,s_axi_lite_wready,s_axi_lite_wdata[31:0],s_axi_lite_bresp[1:0],s_axi_lite_bvalid,s_axi_lite_bready,s_axi_lite_arvalid,s_axi_lite_arready,s_axi_lite_araddr[8:0],s_axi_lite_rvalid,s_axi_lite_rready,s_axi_lite_rdata[31:0],s_axi_lite_rresp[1:0],mm2s_frame_ptr_out[5:0],s2mm_frame_ptr_in[5:0],s2mm_frame_ptr_out[5:0],m_axi_mm2s_araddr[31:0],m_axi_mm2s_arlen[7:0],m_axi_mm2s_arsize[2:0],m_axi_mm2s_arburst[1:0],m_axi_mm2s_arprot[2:0],m_axi_mm2s_arcache[3:0],m_axi_mm2s_arvalid,m_axi_mm2s_arready,m_axi_mm2s_rdata[63:0],m_axi_mm2s_rresp[1:0],m_axi_mm2s_rlast,m_axi_mm2s_rvalid,m_axi_mm2s_rready,m_axis_mm2s_tdata[31:0],m_axis_mm2s_tkeep[3:0],m_axis_mm2s_tuser[0:0],m_axis_mm2s_tvalid,m_axis_mm2s_tready,m_axis_mm2s_tlast,m_axi_s2mm_awaddr[31:0],m_axi_s2mm_awlen[7:0],m_axi_s2mm_awsize[2:0],m_axi_s2mm_awburst[1:0],m_axi_s2mm_awprot[2:0],m_axi_s2mm_awcache[3:0],m_axi_s2mm_awvalid,m_axi_s2mm_awready,m_axi_s2mm_wdata[63:0],m_axi_s2mm_wstrb[7:0],m_axi_s2mm_wlast,m_axi_s2mm_wvalid,m_axi_s2mm_wready,m_axi_s2mm_bresp[1:0],m_axi_s2mm_bvalid,m_axi_s2mm_bready,s_axis_s2mm_tdata[7:0],s_axis_s2mm_tkeep[0:0],s_axis_s2mm_tuser[0:0],s_axis_s2mm_tvalid,s_axis_s2mm_tready,s_axis_s2mm_tlast,mm2s_introut,s2mm_introut" */; input s_axi_lite_aclk; input m_axi_mm2s_aclk; input m_axis_mm2s_aclk; + input m_axi_s2mm_aclk; + input s_axis_s2mm_aclk; input axi_resetn; input s_axi_lite_awvalid; output s_axi_lite_awready; @@ -47,6 +55,8 @@ module Arty_Z7_20_axi_vdma_0_0(s_axi_lite_aclk, m_axi_mm2s_aclk, output [31:0]s_axi_lite_rdata; output [1:0]s_axi_lite_rresp; output [5:0]mm2s_frame_ptr_out; + input [5:0]s2mm_frame_ptr_in; + output [5:0]s2mm_frame_ptr_out; output [31:0]m_axi_mm2s_araddr; output [7:0]m_axi_mm2s_arlen; output [2:0]m_axi_mm2s_arsize; @@ -66,5 +76,28 @@ module Arty_Z7_20_axi_vdma_0_0(s_axi_lite_aclk, m_axi_mm2s_aclk, output m_axis_mm2s_tvalid; input m_axis_mm2s_tready; output m_axis_mm2s_tlast; + output [31:0]m_axi_s2mm_awaddr; + output [7:0]m_axi_s2mm_awlen; + output [2:0]m_axi_s2mm_awsize; + output [1:0]m_axi_s2mm_awburst; + output [2:0]m_axi_s2mm_awprot; + output [3:0]m_axi_s2mm_awcache; + output m_axi_s2mm_awvalid; + input m_axi_s2mm_awready; + output [63:0]m_axi_s2mm_wdata; + output [7:0]m_axi_s2mm_wstrb; + output m_axi_s2mm_wlast; + output m_axi_s2mm_wvalid; + input m_axi_s2mm_wready; + input [1:0]m_axi_s2mm_bresp; + input m_axi_s2mm_bvalid; + output m_axi_s2mm_bready; + input [7:0]s_axis_s2mm_tdata; + input [0:0]s_axis_s2mm_tkeep; + input [0:0]s_axis_s2mm_tuser; + input s_axis_s2mm_tvalid; + output s_axis_s2mm_tready; + input s_axis_s2mm_tlast; output mm2s_introut; + output s2mm_introut; endmodule diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_stub.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_stub.vhdl index 1590452..ae5aaa1 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_stub.vhdl +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 --- Date : Fri Feb 24 16:08:16 2017 +-- Date : Mon Mar 06 11:51:46 2017 -- Host : WK73 running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode synth_stub --- c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_stub.vhdl +-- C:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/Arty_Z7_20_axi_vdma_0_0_stub.vhdl -- Design : Arty_Z7_20_axi_vdma_0_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7z020clg400-1 @@ -17,6 +17,8 @@ entity Arty_Z7_20_axi_vdma_0_0 is s_axi_lite_aclk : in STD_LOGIC; m_axi_mm2s_aclk : in STD_LOGIC; m_axis_mm2s_aclk : in STD_LOGIC; + m_axi_s2mm_aclk : in STD_LOGIC; + s_axis_s2mm_aclk : in STD_LOGIC; axi_resetn : in STD_LOGIC; s_axi_lite_awvalid : in STD_LOGIC; s_axi_lite_awready : out STD_LOGIC; @@ -35,6 +37,8 @@ entity Arty_Z7_20_axi_vdma_0_0 is s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); mm2s_frame_ptr_out : out STD_LOGIC_VECTOR ( 5 downto 0 ); + s2mm_frame_ptr_in : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s2mm_frame_ptr_out : out STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); @@ -54,7 +58,30 @@ entity Arty_Z7_20_axi_vdma_0_0 is m_axis_mm2s_tvalid : out STD_LOGIC; m_axis_mm2s_tready : in STD_LOGIC; m_axis_mm2s_tlast : out STD_LOGIC; - mm2s_introut : out STD_LOGIC + m_axi_s2mm_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_s2mm_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_s2mm_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_s2mm_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_s2mm_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_s2mm_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_s2mm_awvalid : out STD_LOGIC; + m_axi_s2mm_awready : in STD_LOGIC; + m_axi_s2mm_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_s2mm_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_s2mm_wlast : out STD_LOGIC; + m_axi_s2mm_wvalid : out STD_LOGIC; + m_axi_s2mm_wready : in STD_LOGIC; + m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_s2mm_bvalid : in STD_LOGIC; + m_axi_s2mm_bready : out STD_LOGIC; + s_axis_s2mm_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axis_s2mm_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axis_s2mm_tuser : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axis_s2mm_tvalid : in STD_LOGIC; + s_axis_s2mm_tready : out STD_LOGIC; + s_axis_s2mm_tlast : in STD_LOGIC; + mm2s_introut : out STD_LOGIC; + s2mm_introut : out STD_LOGIC ); end Arty_Z7_20_axi_vdma_0_0; @@ -63,7 +90,7 @@ architecture stub of Arty_Z7_20_axi_vdma_0_0 is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "s_axi_lite_aclk,m_axi_mm2s_aclk,m_axis_mm2s_aclk,axi_resetn,s_axi_lite_awvalid,s_axi_lite_awready,s_axi_lite_awaddr[8:0],s_axi_lite_wvalid,s_axi_lite_wready,s_axi_lite_wdata[31:0],s_axi_lite_bresp[1:0],s_axi_lite_bvalid,s_axi_lite_bready,s_axi_lite_arvalid,s_axi_lite_arready,s_axi_lite_araddr[8:0],s_axi_lite_rvalid,s_axi_lite_rready,s_axi_lite_rdata[31:0],s_axi_lite_rresp[1:0],mm2s_frame_ptr_out[5:0],m_axi_mm2s_araddr[31:0],m_axi_mm2s_arlen[7:0],m_axi_mm2s_arsize[2:0],m_axi_mm2s_arburst[1:0],m_axi_mm2s_arprot[2:0],m_axi_mm2s_arcache[3:0],m_axi_mm2s_arvalid,m_axi_mm2s_arready,m_axi_mm2s_rdata[63:0],m_axi_mm2s_rresp[1:0],m_axi_mm2s_rlast,m_axi_mm2s_rvalid,m_axi_mm2s_rready,m_axis_mm2s_tdata[31:0],m_axis_mm2s_tkeep[3:0],m_axis_mm2s_tuser[0:0],m_axis_mm2s_tvalid,m_axis_mm2s_tready,m_axis_mm2s_tlast,mm2s_introut"; +attribute black_box_pad_pin of stub : architecture is "s_axi_lite_aclk,m_axi_mm2s_aclk,m_axis_mm2s_aclk,m_axi_s2mm_aclk,s_axis_s2mm_aclk,axi_resetn,s_axi_lite_awvalid,s_axi_lite_awready,s_axi_lite_awaddr[8:0],s_axi_lite_wvalid,s_axi_lite_wready,s_axi_lite_wdata[31:0],s_axi_lite_bresp[1:0],s_axi_lite_bvalid,s_axi_lite_bready,s_axi_lite_arvalid,s_axi_lite_arready,s_axi_lite_araddr[8:0],s_axi_lite_rvalid,s_axi_lite_rready,s_axi_lite_rdata[31:0],s_axi_lite_rresp[1:0],mm2s_frame_ptr_out[5:0],s2mm_frame_ptr_in[5:0],s2mm_frame_ptr_out[5:0],m_axi_mm2s_araddr[31:0],m_axi_mm2s_arlen[7:0],m_axi_mm2s_arsize[2:0],m_axi_mm2s_arburst[1:0],m_axi_mm2s_arprot[2:0],m_axi_mm2s_arcache[3:0],m_axi_mm2s_arvalid,m_axi_mm2s_arready,m_axi_mm2s_rdata[63:0],m_axi_mm2s_rresp[1:0],m_axi_mm2s_rlast,m_axi_mm2s_rvalid,m_axi_mm2s_rready,m_axis_mm2s_tdata[31:0],m_axis_mm2s_tkeep[3:0],m_axis_mm2s_tuser[0:0],m_axis_mm2s_tvalid,m_axis_mm2s_tready,m_axis_mm2s_tlast,m_axi_s2mm_awaddr[31:0],m_axi_s2mm_awlen[7:0],m_axi_s2mm_awsize[2:0],m_axi_s2mm_awburst[1:0],m_axi_s2mm_awprot[2:0],m_axi_s2mm_awcache[3:0],m_axi_s2mm_awvalid,m_axi_s2mm_awready,m_axi_s2mm_wdata[63:0],m_axi_s2mm_wstrb[7:0],m_axi_s2mm_wlast,m_axi_s2mm_wvalid,m_axi_s2mm_wready,m_axi_s2mm_bresp[1:0],m_axi_s2mm_bvalid,m_axi_s2mm_bready,s_axis_s2mm_tdata[7:0],s_axis_s2mm_tkeep[0:0],s_axis_s2mm_tuser[0:0],s_axis_s2mm_tvalid,s_axis_s2mm_tready,s_axis_s2mm_tlast,mm2s_introut,s2mm_introut"; attribute x_core_info : string; attribute x_core_info of stub : architecture is "axi_vdma,Vivado 2016.4"; begin diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/sim/Arty_Z7_20_axi_vdma_0_0.vhd b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/sim/Arty_Z7_20_axi_vdma_0_0.vhd index 9df1179..294b3fa 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/sim/Arty_Z7_20_axi_vdma_0_0.vhd +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/sim/Arty_Z7_20_axi_vdma_0_0.vhd @@ -61,6 +61,8 @@ ENTITY Arty_Z7_20_axi_vdma_0_0 IS s_axi_lite_aclk : IN STD_LOGIC; m_axi_mm2s_aclk : IN STD_LOGIC; m_axis_mm2s_aclk : IN STD_LOGIC; + m_axi_s2mm_aclk : IN STD_LOGIC; + s_axis_s2mm_aclk : IN STD_LOGIC; axi_resetn : IN STD_LOGIC; s_axi_lite_awvalid : IN STD_LOGIC; s_axi_lite_awready : OUT STD_LOGIC; @@ -79,6 +81,8 @@ ENTITY Arty_Z7_20_axi_vdma_0_0 IS s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + s2mm_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0); + s2mm_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); @@ -98,7 +102,30 @@ ENTITY Arty_Z7_20_axi_vdma_0_0 IS m_axis_mm2s_tvalid : OUT STD_LOGIC; m_axis_mm2s_tready : IN STD_LOGIC; m_axis_mm2s_tlast : OUT STD_LOGIC; - mm2s_introut : OUT STD_LOGIC + m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_s2mm_awvalid : OUT STD_LOGIC; + m_axi_s2mm_awready : IN STD_LOGIC; + m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + m_axi_s2mm_wlast : OUT STD_LOGIC; + m_axi_s2mm_wvalid : OUT STD_LOGIC; + m_axi_s2mm_wready : IN STD_LOGIC; + m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_s2mm_bvalid : IN STD_LOGIC; + m_axi_s2mm_bready : OUT STD_LOGIC; + s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + s_axis_s2mm_tvalid : IN STD_LOGIC; + s_axis_s2mm_tready : OUT STD_LOGIC; + s_axis_s2mm_tlast : IN STD_LOGIC; + mm2s_introut : OUT STD_LOGIC; + s2mm_introut : OUT STD_LOGIC ); END Arty_Z7_20_axi_vdma_0_0; @@ -259,8 +286,8 @@ ARCHITECTURE Arty_Z7_20_axi_vdma_0_0_arch OF Arty_Z7_20_axi_vdma_0_0 IS m_axi_s2mm_bvalid : IN STD_LOGIC; m_axi_s2mm_bready : OUT STD_LOGIC; s2mm_prmry_reset_out_n : OUT STD_LOGIC; - s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_s2mm_tvalid : IN STD_LOGIC; s_axis_s2mm_tready : OUT STD_LOGIC; @@ -274,6 +301,8 @@ ARCHITECTURE Arty_Z7_20_axi_vdma_0_0_arch OF Arty_Z7_20_axi_vdma_0_0 IS ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_ACLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_MM2S_ACLK CLK"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_ACLK CLK"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXIS_S2MM_ACLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY"; @@ -292,6 +321,8 @@ ARCHITECTURE Arty_Z7_20_axi_vdma_0_0_arch OF Arty_Z7_20_axi_vdma_0_0 IS ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP"; ATTRIBUTE X_INTERFACE_INFO OF mm2s_frame_ptr_out: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 MM2S_FRAME_PTR_OUT FRAME_PTR"; + ATTRIBUTE X_INTERFACE_INFO OF s2mm_frame_ptr_in: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 S2MM_FRAME_PTR_IN_0 FRAME_PTR"; + ATTRIBUTE X_INTERFACE_INFO OF s2mm_frame_ptr_out: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 S2MM_FRAME_PTR_OUT FRAME_PTR"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE"; @@ -311,7 +342,30 @@ ARCHITECTURE Arty_Z7_20_axi_vdma_0_0_arch OF Arty_Z7_20_axi_vdma_0_0 IS ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TUSER"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST"; ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT"; + ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT"; BEGIN U0 : axi_vdma GENERIC MAP ( @@ -321,7 +375,7 @@ BEGIN C_PRMRY_IS_ACLK_ASYNC => 1, C_ENABLE_VIDPRMTR_READS => 1, C_DYNAMIC_RESOLUTION => 1, - C_NUM_FSTORES => 1, + C_NUM_FSTORES => 3, C_USE_FSYNC => 1, C_USE_MM2S_FSYNC => 0, C_USE_S2MM_FSYNC => 2, @@ -337,26 +391,26 @@ BEGIN C_MM2S_SOF_ENABLE => 1, C_INCLUDE_MM2S_DRE => 0, C_INCLUDE_MM2S_SF => 0, - C_MM2S_LINEBUFFER_DEPTH => 4096, + C_MM2S_LINEBUFFER_DEPTH => 2048, C_MM2S_LINEBUFFER_THRESH => 4, - C_MM2S_MAX_BURST_LENGTH => 16, + C_MM2S_MAX_BURST_LENGTH => 32, C_M_AXI_MM2S_ADDR_WIDTH => 32, C_M_AXI_MM2S_DATA_WIDTH => 64, C_M_AXIS_MM2S_TDATA_WIDTH => 32, C_M_AXIS_MM2S_TUSER_BITS => 1, - C_INCLUDE_S2MM => 0, - C_S2MM_GENLOCK_MODE => 0, + C_INCLUDE_S2MM => 1, + C_S2MM_GENLOCK_MODE => 2, C_S2MM_GENLOCK_NUM_MASTERS => 1, C_S2MM_GENLOCK_REPEAT_EN => 1, C_S2MM_SOF_ENABLE => 1, C_INCLUDE_S2MM_DRE => 0, C_INCLUDE_S2MM_SF => 1, - C_S2MM_LINEBUFFER_DEPTH => 512, + C_S2MM_LINEBUFFER_DEPTH => 2048, C_S2MM_LINEBUFFER_THRESH => 4, - C_S2MM_MAX_BURST_LENGTH => 8, + C_S2MM_MAX_BURST_LENGTH => 32, C_M_AXI_S2MM_ADDR_WIDTH => 32, C_M_AXI_S2MM_DATA_WIDTH => 64, - C_S_AXIS_S2MM_TDATA_WIDTH => 32, + C_S_AXIS_S2MM_TDATA_WIDTH => 8, C_S_AXIS_S2MM_TUSER_BITS => 1, C_ENABLE_DEBUG_ALL => 0, C_ENABLE_DEBUG_INFO_0 => 0, @@ -384,8 +438,8 @@ BEGIN m_axi_sg_aclk => '0', m_axi_mm2s_aclk => m_axi_mm2s_aclk, m_axis_mm2s_aclk => m_axis_mm2s_aclk, - m_axi_s2mm_aclk => '0', - s_axis_s2mm_aclk => '0', + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + s_axis_s2mm_aclk => s_axis_s2mm_aclk, axi_resetn => axi_resetn, s_axi_lite_awvalid => s_axi_lite_awvalid, s_axi_lite_awready => s_axi_lite_awready, @@ -407,7 +461,8 @@ BEGIN mm2s_frame_ptr_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), mm2s_frame_ptr_out => mm2s_frame_ptr_out, s2mm_fsync => '0', - s2mm_frame_ptr_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), + s2mm_frame_ptr_in => s2mm_frame_ptr_in, + s2mm_frame_ptr_out => s2mm_frame_ptr_out, m_axi_sg_arready => '0', m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), @@ -432,15 +487,29 @@ BEGIN m_axis_mm2s_tvalid => m_axis_mm2s_tvalid, m_axis_mm2s_tready => m_axis_mm2s_tready, m_axis_mm2s_tlast => m_axis_mm2s_tlast, - m_axi_s2mm_awready => '0', - m_axi_s2mm_wready => '0', - m_axi_s2mm_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), - m_axi_s2mm_bvalid => '0', - s_axis_s2mm_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), - s_axis_s2mm_tkeep => X"F", - s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), - s_axis_s2mm_tvalid => '0', - s_axis_s2mm_tlast => '0', - mm2s_introut => mm2s_introut + m_axi_s2mm_awaddr => m_axi_s2mm_awaddr, + m_axi_s2mm_awlen => m_axi_s2mm_awlen, + m_axi_s2mm_awsize => m_axi_s2mm_awsize, + m_axi_s2mm_awburst => m_axi_s2mm_awburst, + m_axi_s2mm_awprot => m_axi_s2mm_awprot, + m_axi_s2mm_awcache => m_axi_s2mm_awcache, + m_axi_s2mm_awvalid => m_axi_s2mm_awvalid, + m_axi_s2mm_awready => m_axi_s2mm_awready, + m_axi_s2mm_wdata => m_axi_s2mm_wdata, + m_axi_s2mm_wstrb => m_axi_s2mm_wstrb, + m_axi_s2mm_wlast => m_axi_s2mm_wlast, + m_axi_s2mm_wvalid => m_axi_s2mm_wvalid, + m_axi_s2mm_wready => m_axi_s2mm_wready, + m_axi_s2mm_bresp => m_axi_s2mm_bresp, + m_axi_s2mm_bvalid => m_axi_s2mm_bvalid, + m_axi_s2mm_bready => m_axi_s2mm_bready, + s_axis_s2mm_tdata => s_axis_s2mm_tdata, + s_axis_s2mm_tkeep => s_axis_s2mm_tkeep, + s_axis_s2mm_tuser => s_axis_s2mm_tuser, + s_axis_s2mm_tvalid => s_axis_s2mm_tvalid, + s_axis_s2mm_tready => s_axis_s2mm_tready, + s_axis_s2mm_tlast => s_axis_s2mm_tlast, + mm2s_introut => mm2s_introut, + s2mm_introut => s2mm_introut ); END Arty_Z7_20_axi_vdma_0_0_arch; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/synth/Arty_Z7_20_axi_vdma_0_0.vhd b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/synth/Arty_Z7_20_axi_vdma_0_0.vhd index b533fae..ee62b4e 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/synth/Arty_Z7_20_axi_vdma_0_0.vhd +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axi_vdma_0_0/synth/Arty_Z7_20_axi_vdma_0_0.vhd @@ -61,6 +61,8 @@ ENTITY Arty_Z7_20_axi_vdma_0_0 IS s_axi_lite_aclk : IN STD_LOGIC; m_axi_mm2s_aclk : IN STD_LOGIC; m_axis_mm2s_aclk : IN STD_LOGIC; + m_axi_s2mm_aclk : IN STD_LOGIC; + s_axis_s2mm_aclk : IN STD_LOGIC; axi_resetn : IN STD_LOGIC; s_axi_lite_awvalid : IN STD_LOGIC; s_axi_lite_awready : OUT STD_LOGIC; @@ -79,6 +81,8 @@ ENTITY Arty_Z7_20_axi_vdma_0_0 IS s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + s2mm_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0); + s2mm_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); @@ -98,7 +102,30 @@ ENTITY Arty_Z7_20_axi_vdma_0_0 IS m_axis_mm2s_tvalid : OUT STD_LOGIC; m_axis_mm2s_tready : IN STD_LOGIC; m_axis_mm2s_tlast : OUT STD_LOGIC; - mm2s_introut : OUT STD_LOGIC + m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + m_axi_s2mm_awvalid : OUT STD_LOGIC; + m_axi_s2mm_awready : IN STD_LOGIC; + m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + m_axi_s2mm_wlast : OUT STD_LOGIC; + m_axi_s2mm_wvalid : OUT STD_LOGIC; + m_axi_s2mm_wready : IN STD_LOGIC; + m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + m_axi_s2mm_bvalid : IN STD_LOGIC; + m_axi_s2mm_bready : OUT STD_LOGIC; + s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + s_axis_s2mm_tvalid : IN STD_LOGIC; + s_axis_s2mm_tready : OUT STD_LOGIC; + s_axis_s2mm_tlast : IN STD_LOGIC; + mm2s_introut : OUT STD_LOGIC; + s2mm_introut : OUT STD_LOGIC ); END Arty_Z7_20_axi_vdma_0_0; @@ -259,8 +286,8 @@ ARCHITECTURE Arty_Z7_20_axi_vdma_0_0_arch OF Arty_Z7_20_axi_vdma_0_0 IS m_axi_s2mm_bvalid : IN STD_LOGIC; m_axi_s2mm_bready : OUT STD_LOGIC; s2mm_prmry_reset_out_n : OUT STD_LOGIC; - s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_s2mm_tvalid : IN STD_LOGIC; s_axis_s2mm_tready : OUT STD_LOGIC; @@ -275,14 +302,16 @@ ARCHITECTURE Arty_Z7_20_axi_vdma_0_0_arch OF Arty_Z7_20_axi_vdma_0_0 IS ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF Arty_Z7_20_axi_vdma_0_0_arch : ARCHITECTURE IS "Arty_Z7_20_axi_vdma_0_0,axi_vdma,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; - ATTRIBUTE CORE_GENERATION_INFO OF Arty_Z7_20_axi_vdma_0_0_arch: ARCHITECTURE IS "Arty_Z7_20_axi_vdma_0_0,axi_vdma,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_vdma,x_ipVersion=6.2,x_ipCoreRevision=10,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=9,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=1,C_ENABLE_VIDPRMTR_READS=1,C_DYNAMIC_RESOLUTION=1,C_NUM_FSTORES=1,C_USE_FSYNC=1,C_USE_MM2S_FSYNC=0,C_USE_S2MM_FSYNC=2,C_FLUSH_ON_FSYNC=1,C_INCLUDE_INTERNAL_GENLOCK=1,C_INCLUDE_SG=0,C_M_AXI_SG_ADDR_WIDTH=32,C_M" & -"_AXI_SG_DATA_WIDTH=32,C_INCLUDE_MM2S=1,C_MM2S_GENLOCK_MODE=0,C_MM2S_GENLOCK_NUM_MASTERS=1,C_MM2S_GENLOCK_REPEAT_EN=0,C_MM2S_SOF_ENABLE=1,C_INCLUDE_MM2S_DRE=0,C_INCLUDE_MM2S_SF=0,C_MM2S_LINEBUFFER_DEPTH=4096,C_MM2S_LINEBUFFER_THRESH=4,C_MM2S_MAX_BURST_LENGTH=16,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=64,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_M_AXIS_MM2S_TUSER_BITS=1,C_INCLUDE_S2MM=0,C_S2MM_GENLOCK_MODE=0,C_S2MM_GENLOCK_NUM_MASTERS=1,C_S2MM_GENLOCK_REPEAT_EN=1,C_S2MM_SOF_ENABLE=1,C_INCLUDE_S2MM" & -"_DRE=0,C_INCLUDE_S2MM_SF=1,C_S2MM_LINEBUFFER_DEPTH=512,C_S2MM_LINEBUFFER_THRESH=4,C_S2MM_MAX_BURST_LENGTH=8,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=64,C_S_AXIS_S2MM_TDATA_WIDTH=32,C_S_AXIS_S2MM_TUSER_BITS=1,C_ENABLE_DEBUG_ALL=0,C_ENABLE_DEBUG_INFO_0=0,C_ENABLE_DEBUG_INFO_1=0,C_ENABLE_DEBUG_INFO_2=0,C_ENABLE_DEBUG_INFO_3=0,C_ENABLE_DEBUG_INFO_4=0,C_ENABLE_DEBUG_INFO_5=0,C_ENABLE_DEBUG_INFO_6=1,C_ENABLE_DEBUG_INFO_7=1,C_ENABLE_DEBUG_INFO_8=0,C_ENABLE_DEBUG_INFO_9=0,C_ENABLE_DEBUG_INFO_1" & -"0=0,C_ENABLE_DEBUG_INFO_11=0,C_ENABLE_DEBUG_INFO_12=0,C_ENABLE_DEBUG_INFO_13=0,C_ENABLE_DEBUG_INFO_14=1,C_ENABLE_DEBUG_INFO_15=1,C_INSTANCE=axi_vdma,C_SELECT_XPM=0,C_FAMILY=zynq}"; + ATTRIBUTE CORE_GENERATION_INFO OF Arty_Z7_20_axi_vdma_0_0_arch: ARCHITECTURE IS "Arty_Z7_20_axi_vdma_0_0,axi_vdma,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_vdma,x_ipVersion=6.2,x_ipCoreRevision=10,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=9,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=1,C_ENABLE_VIDPRMTR_READS=1,C_DYNAMIC_RESOLUTION=1,C_NUM_FSTORES=3,C_USE_FSYNC=1,C_USE_MM2S_FSYNC=0,C_USE_S2MM_FSYNC=2,C_FLUSH_ON_FSYNC=1,C_INCLUDE_INTERNAL_GENLOCK=1,C_INCLUDE_SG=0,C_M_AXI_SG_ADDR_WIDTH=32,C_M" & +"_AXI_SG_DATA_WIDTH=32,C_INCLUDE_MM2S=1,C_MM2S_GENLOCK_MODE=0,C_MM2S_GENLOCK_NUM_MASTERS=1,C_MM2S_GENLOCK_REPEAT_EN=0,C_MM2S_SOF_ENABLE=1,C_INCLUDE_MM2S_DRE=0,C_INCLUDE_MM2S_SF=0,C_MM2S_LINEBUFFER_DEPTH=2048,C_MM2S_LINEBUFFER_THRESH=4,C_MM2S_MAX_BURST_LENGTH=32,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=64,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_M_AXIS_MM2S_TUSER_BITS=1,C_INCLUDE_S2MM=1,C_S2MM_GENLOCK_MODE=2,C_S2MM_GENLOCK_NUM_MASTERS=1,C_S2MM_GENLOCK_REPEAT_EN=1,C_S2MM_SOF_ENABLE=1,C_INCLUDE_S2MM" & +"_DRE=0,C_INCLUDE_S2MM_SF=1,C_S2MM_LINEBUFFER_DEPTH=2048,C_S2MM_LINEBUFFER_THRESH=4,C_S2MM_MAX_BURST_LENGTH=32,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=64,C_S_AXIS_S2MM_TDATA_WIDTH=8,C_S_AXIS_S2MM_TUSER_BITS=1,C_ENABLE_DEBUG_ALL=0,C_ENABLE_DEBUG_INFO_0=0,C_ENABLE_DEBUG_INFO_1=0,C_ENABLE_DEBUG_INFO_2=0,C_ENABLE_DEBUG_INFO_3=0,C_ENABLE_DEBUG_INFO_4=0,C_ENABLE_DEBUG_INFO_5=0,C_ENABLE_DEBUG_INFO_6=1,C_ENABLE_DEBUG_INFO_7=1,C_ENABLE_DEBUG_INFO_8=0,C_ENABLE_DEBUG_INFO_9=0,C_ENABLE_DEBUG_INFO_" & +"10=0,C_ENABLE_DEBUG_INFO_11=0,C_ENABLE_DEBUG_INFO_12=0,C_ENABLE_DEBUG_INFO_13=0,C_ENABLE_DEBUG_INFO_14=1,C_ENABLE_DEBUG_INFO_15=1,C_INSTANCE=axi_vdma,C_SELECT_XPM=0,C_FAMILY=zynq}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_ACLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_MM2S_ACLK CLK"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_ACLK CLK"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXIS_S2MM_ACLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY"; @@ -301,6 +330,8 @@ ARCHITECTURE Arty_Z7_20_axi_vdma_0_0_arch OF Arty_Z7_20_axi_vdma_0_0 IS ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP"; ATTRIBUTE X_INTERFACE_INFO OF mm2s_frame_ptr_out: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 MM2S_FRAME_PTR_OUT FRAME_PTR"; + ATTRIBUTE X_INTERFACE_INFO OF s2mm_frame_ptr_in: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 S2MM_FRAME_PTR_IN_0 FRAME_PTR"; + ATTRIBUTE X_INTERFACE_INFO OF s2mm_frame_ptr_out: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 S2MM_FRAME_PTR_OUT FRAME_PTR"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE"; @@ -320,7 +351,30 @@ ARCHITECTURE Arty_Z7_20_axi_vdma_0_0_arch OF Arty_Z7_20_axi_vdma_0_0 IS ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID"; + ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TUSER"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST"; ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT"; + ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT"; BEGIN U0 : axi_vdma GENERIC MAP ( @@ -330,7 +384,7 @@ BEGIN C_PRMRY_IS_ACLK_ASYNC => 1, C_ENABLE_VIDPRMTR_READS => 1, C_DYNAMIC_RESOLUTION => 1, - C_NUM_FSTORES => 1, + C_NUM_FSTORES => 3, C_USE_FSYNC => 1, C_USE_MM2S_FSYNC => 0, C_USE_S2MM_FSYNC => 2, @@ -346,26 +400,26 @@ BEGIN C_MM2S_SOF_ENABLE => 1, C_INCLUDE_MM2S_DRE => 0, C_INCLUDE_MM2S_SF => 0, - C_MM2S_LINEBUFFER_DEPTH => 4096, + C_MM2S_LINEBUFFER_DEPTH => 2048, C_MM2S_LINEBUFFER_THRESH => 4, - C_MM2S_MAX_BURST_LENGTH => 16, + C_MM2S_MAX_BURST_LENGTH => 32, C_M_AXI_MM2S_ADDR_WIDTH => 32, C_M_AXI_MM2S_DATA_WIDTH => 64, C_M_AXIS_MM2S_TDATA_WIDTH => 32, C_M_AXIS_MM2S_TUSER_BITS => 1, - C_INCLUDE_S2MM => 0, - C_S2MM_GENLOCK_MODE => 0, + C_INCLUDE_S2MM => 1, + C_S2MM_GENLOCK_MODE => 2, C_S2MM_GENLOCK_NUM_MASTERS => 1, C_S2MM_GENLOCK_REPEAT_EN => 1, C_S2MM_SOF_ENABLE => 1, C_INCLUDE_S2MM_DRE => 0, C_INCLUDE_S2MM_SF => 1, - C_S2MM_LINEBUFFER_DEPTH => 512, + C_S2MM_LINEBUFFER_DEPTH => 2048, C_S2MM_LINEBUFFER_THRESH => 4, - C_S2MM_MAX_BURST_LENGTH => 8, + C_S2MM_MAX_BURST_LENGTH => 32, C_M_AXI_S2MM_ADDR_WIDTH => 32, C_M_AXI_S2MM_DATA_WIDTH => 64, - C_S_AXIS_S2MM_TDATA_WIDTH => 32, + C_S_AXIS_S2MM_TDATA_WIDTH => 8, C_S_AXIS_S2MM_TUSER_BITS => 1, C_ENABLE_DEBUG_ALL => 0, C_ENABLE_DEBUG_INFO_0 => 0, @@ -393,8 +447,8 @@ BEGIN m_axi_sg_aclk => '0', m_axi_mm2s_aclk => m_axi_mm2s_aclk, m_axis_mm2s_aclk => m_axis_mm2s_aclk, - m_axi_s2mm_aclk => '0', - s_axis_s2mm_aclk => '0', + m_axi_s2mm_aclk => m_axi_s2mm_aclk, + s_axis_s2mm_aclk => s_axis_s2mm_aclk, axi_resetn => axi_resetn, s_axi_lite_awvalid => s_axi_lite_awvalid, s_axi_lite_awready => s_axi_lite_awready, @@ -416,7 +470,8 @@ BEGIN mm2s_frame_ptr_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), mm2s_frame_ptr_out => mm2s_frame_ptr_out, s2mm_fsync => '0', - s2mm_frame_ptr_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), + s2mm_frame_ptr_in => s2mm_frame_ptr_in, + s2mm_frame_ptr_out => s2mm_frame_ptr_out, m_axi_sg_arready => '0', m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), @@ -441,15 +496,29 @@ BEGIN m_axis_mm2s_tvalid => m_axis_mm2s_tvalid, m_axis_mm2s_tready => m_axis_mm2s_tready, m_axis_mm2s_tlast => m_axis_mm2s_tlast, - m_axi_s2mm_awready => '0', - m_axi_s2mm_wready => '0', - m_axi_s2mm_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), - m_axi_s2mm_bvalid => '0', - s_axis_s2mm_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), - s_axis_s2mm_tkeep => X"F", - s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), - s_axis_s2mm_tvalid => '0', - s_axis_s2mm_tlast => '0', - mm2s_introut => mm2s_introut + m_axi_s2mm_awaddr => m_axi_s2mm_awaddr, + m_axi_s2mm_awlen => m_axi_s2mm_awlen, + m_axi_s2mm_awsize => m_axi_s2mm_awsize, + m_axi_s2mm_awburst => m_axi_s2mm_awburst, + m_axi_s2mm_awprot => m_axi_s2mm_awprot, + m_axi_s2mm_awcache => m_axi_s2mm_awcache, + m_axi_s2mm_awvalid => m_axi_s2mm_awvalid, + m_axi_s2mm_awready => m_axi_s2mm_awready, + m_axi_s2mm_wdata => m_axi_s2mm_wdata, + m_axi_s2mm_wstrb => m_axi_s2mm_wstrb, + m_axi_s2mm_wlast => m_axi_s2mm_wlast, + m_axi_s2mm_wvalid => m_axi_s2mm_wvalid, + m_axi_s2mm_wready => m_axi_s2mm_wready, + m_axi_s2mm_bresp => m_axi_s2mm_bresp, + m_axi_s2mm_bvalid => m_axi_s2mm_bvalid, + m_axi_s2mm_bready => m_axi_s2mm_bready, + s_axis_s2mm_tdata => s_axis_s2mm_tdata, + s_axis_s2mm_tkeep => s_axis_s2mm_tkeep, + s_axis_s2mm_tuser => s_axis_s2mm_tuser, + s_axis_s2mm_tvalid => s_axis_s2mm_tvalid, + s_axis_s2mm_tready => s_axis_s2mm_tready, + s_axis_s2mm_tlast => s_axis_s2mm_tlast, + mm2s_introut => mm2s_introut, + s2mm_introut => s2mm_introut ); END Arty_Z7_20_axi_vdma_0_0_arch; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0.dcp b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0.dcp index fcc95cf..cf2b001 100644 Binary files a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0.dcp and b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0.dcp differ diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0.xci b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0.xci index d6990a5..b4c9755 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0.xci +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0.xci @@ -13,10 +13,10 @@ aclken aresetn Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 - 142857132 + 118181816 0.000 Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 - 142857132 + 118181816 1 1 1 @@ -30,7 +30,7 @@ ACTIVE_LOW INTERCONNECT Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 - 142857132 + 118181816 1 1 1 @@ -90,6 +90,7 @@ TRUE TRUE + acf286177b49b194 IP_Integrator 11 TRUE diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0.xml b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0.xml index d4b21da..587d10d 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0.xml +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0.xml @@ -120,7 +120,7 @@ FREQ_HZ - 142857132 + 118181816 PHASE @@ -251,7 +251,7 @@ FREQ_HZ - 142857132 + 118181816 PHASE @@ -313,7 +313,7 @@ FREQ_HZ - 142857132 + 118181816 PHASE @@ -364,6 +364,36 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Mon Mar 06 19:44:23 UTC 2017 + + + boundaryCRC + 70d1e5e8 + + + boundaryCRCversion + 1 + + + customizationCRC + acda7127 + + + customizationCRCversion + 6 + + + xilinx_verilogsynthesis Verilog Synthesis @@ -382,11 +412,11 @@ GENtimestamp - Fri Feb 24 23:57:50 UTC 2017 + Mon Mar 06 19:44:17 UTC 2017 boundaryCRC - 5224d00e + 70d1e5e8 boundaryCRCversion @@ -413,11 +443,11 @@ GENtimestamp - Fri Feb 24 23:57:50 UTC 2017 + Mon Mar 06 19:44:17 UTC 2017 boundaryCRC - 5224d00e + 70d1e5e8 boundaryCRCversion @@ -451,11 +481,11 @@ GENtimestamp - Fri Feb 24 23:57:50 UTC 2017 + Mon Mar 06 19:44:17 UTC 2017 boundaryCRC - 5224d00e + 70d1e5e8 boundaryCRCversion @@ -482,11 +512,11 @@ GENtimestamp - Fri Feb 24 23:57:50 UTC 2017 + Mon Mar 06 19:44:17 UTC 2017 boundaryCRC - 5224d00e + 70d1e5e8 boundaryCRCversion @@ -502,36 +532,6 @@ - - xilinx_externalfiles - External Files - :vivado.xilinx.com:external.files - - xilinx_externalfiles_view_fileset - - - - GENtimestamp - Sat Feb 25 00:00:31 UTC 2017 - - - boundaryCRC - 5224d00e - - - boundaryCRCversion - 1 - - - customizationCRC - acda7127 - - - customizationCRCversion - 6 - - - @@ -1104,6 +1104,42 @@ + + xilinx_externalfiles_view_fileset + + Arty_Z7_20_axis_subset_converter_0_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + Arty_Z7_20_axis_subset_converter_0_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Arty_Z7_20_axis_subset_converter_0_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Arty_Z7_20_axis_subset_converter_0_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Arty_Z7_20_axis_subset_converter_0_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + xilinx_verilogsynthesis_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset @@ -1315,42 +1351,6 @@ xil_defaultlib - - xilinx_externalfiles_view_fileset - - Arty_Z7_20_axis_subset_converter_0_0.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - Arty_Z7_20_axis_subset_converter_0_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - Arty_Z7_20_axis_subset_converter_0_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - Arty_Z7_20_axis_subset_converter_0_0_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - Arty_Z7_20_axis_subset_converter_0_0_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - The AXI4-Stream Subset Converter IP provides the infrastructure to change the AXI4-Stream interface characteristics between a AXI4-Stream master and slave. diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0_sim_netlist.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0_sim_netlist.v index 6b9a9e2..3f660fc 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0_sim_netlist.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -// Date : Fri Feb 24 16:00:31 2017 +// Date : Fri Feb 24 16:00:30 2017 // Host : WK73 running 64-bit Service Pack 1 (build 7601) -// Command : write_verilog -force -mode funcsim -// c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0_sim_netlist.v +// Command : write_verilog -force -mode funcsim -rename_top Arty_Z7_20_axis_subset_converter_0_0 -prefix +// Arty_Z7_20_axis_subset_converter_0_0_ Arty_Z7_20_axis_subset_converter_0_0_sim_netlist.v // Design : Arty_Z7_20_axis_subset_converter_0_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -131,7 +131,7 @@ endmodule (* G_MASK_SS_TDEST = "64" *) (* G_MASK_SS_TID = "32" *) (* G_MASK_SS_TKEEP = "8" *) (* G_MASK_SS_TLAST = "16" *) (* G_MASK_SS_TREADY = "1" *) (* G_MASK_SS_TSTRB = "4" *) (* G_MASK_SS_TUSER = "128" *) (* G_TASK_SEVERITY_ERR = "2" *) (* G_TASK_SEVERITY_INFO = "0" *) -(* G_TASK_SEVERITY_WARNING = "1" *) (* ORIG_REF_NAME = "top_Arty_Z7_20_axis_subset_converter_0_0" *) +(* G_TASK_SEVERITY_WARNING = "1" *) module Arty_Z7_20_axis_subset_converter_0_0_top_Arty_Z7_20_axis_subset_converter_0_0 (aclk, aresetn, diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0_sim_netlist.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0_sim_netlist.vhdl index c058ed6..82bc8d3 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0_sim_netlist.vhdl +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 --- Date : Fri Feb 24 16:00:31 2017 +-- Date : Fri Feb 24 16:00:30 2017 -- Host : WK73 running 64-bit Service Pack 1 (build 7601) --- Command : write_vhdl -force -mode funcsim --- c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0_sim_netlist.vhdl +-- Command : write_vhdl -force -mode funcsim -rename_top Arty_Z7_20_axis_subset_converter_0_0 -prefix +-- Arty_Z7_20_axis_subset_converter_0_0_ Arty_Z7_20_axis_subset_converter_0_0_sim_netlist.vhdl -- Design : Arty_Z7_20_axis_subset_converter_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. @@ -102,8 +102,6 @@ entity Arty_Z7_20_axis_subset_converter_0_0_top_Arty_Z7_20_axis_subset_converter attribute G_TASK_SEVERITY_INFO of Arty_Z7_20_axis_subset_converter_0_0_top_Arty_Z7_20_axis_subset_converter_0_0 : entity is 0; attribute G_TASK_SEVERITY_WARNING : integer; attribute G_TASK_SEVERITY_WARNING of Arty_Z7_20_axis_subset_converter_0_0_top_Arty_Z7_20_axis_subset_converter_0_0 : entity is 1; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_axis_subset_converter_0_0_top_Arty_Z7_20_axis_subset_converter_0_0 : entity is "top_Arty_Z7_20_axis_subset_converter_0_0"; end Arty_Z7_20_axis_subset_converter_0_0_top_Arty_Z7_20_axis_subset_converter_0_0; architecture STRUCTURE of Arty_Z7_20_axis_subset_converter_0_0_top_Arty_Z7_20_axis_subset_converter_0_0 is diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0_stub.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0_stub.v index 3d346bf..efe7e28 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0_stub.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -// Date : Fri Feb 24 16:00:31 2017 +// Date : Fri Feb 24 16:00:30 2017 // Host : WK73 running 64-bit Service Pack 1 (build 7601) -// Command : write_verilog -force -mode synth_stub -// c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0_stub.v +// Command : write_verilog -force -mode synth_stub -rename_top Arty_Z7_20_axis_subset_converter_0_0 -prefix +// Arty_Z7_20_axis_subset_converter_0_0_ Arty_Z7_20_axis_subset_converter_0_0_stub.v // Design : Arty_Z7_20_axis_subset_converter_0_0 // Purpose : Stub declaration of top-level module interface // Device : xc7z020clg400-1 diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0_stub.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0_stub.vhdl index 3d1d6d2..859e861 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0_stub.vhdl +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 --- Date : Fri Feb 24 16:00:31 2017 +-- Date : Fri Feb 24 16:00:30 2017 -- Host : WK73 running 64-bit Service Pack 1 (build 7601) --- Command : write_vhdl -force -mode synth_stub --- c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_0/Arty_Z7_20_axis_subset_converter_0_0_stub.vhdl +-- Command : write_vhdl -force -mode synth_stub -rename_top Arty_Z7_20_axis_subset_converter_0_0 -prefix +-- Arty_Z7_20_axis_subset_converter_0_0_ Arty_Z7_20_axis_subset_converter_0_0_stub.vhdl -- Design : Arty_Z7_20_axis_subset_converter_0_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7z020clg400-1 diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/Arty_Z7_20_axis_subset_converter_0_1.dcp b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/Arty_Z7_20_axis_subset_converter_0_1.dcp new file mode 100644 index 0000000..e082c6e Binary files /dev/null and b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/Arty_Z7_20_axis_subset_converter_0_1.dcp differ diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/Arty_Z7_20_axis_subset_converter_0_1.xci b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/Arty_Z7_20_axis_subset_converter_0_1.xci new file mode 100644 index 0000000..e90f0e2 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/Arty_Z7_20_axis_subset_converter_0_1.xci @@ -0,0 +1,147 @@ + + + xilinx.com + xci + unknown + 1.0 + + + Arty_Z7_20_axis_subset_converter_0_1 + + + S_AXIS:M_AXIS + aclken + aresetn + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 + 118181816 + 0.000 + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 + 118181816 + 0 + 1 + 1 + 0 + undef + 0.000 + 1 + 0 + 0 + 1 + ACTIVE_LOW + INTERCONNECT + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 + 118181816 + 0 + 1 + 1 + 0 + xilinx.com:interface:datatypes:1.0 {TDATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value xilinx.com:video:Y_U_V_444:1.0} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 24} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value rows} size {attribs {resolve_type generated dependency active_rows format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency active_rows_stride format long minimum {} maximum {}} value 24} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 24} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value cols} size {attribs {resolve_type generated dependency active_cols format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency active_cols_stride format long minimum {} maximum {}} value 24} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 24} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} struct {field_Y {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value Y} enabled {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency video_data_width format long minimum {} maximum {}} value 8} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}} field_U {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value U} enabled {attribs {resolve_type generated dependency video_comp1_enabled format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency video_data_width format long minimum {} maximum {}} value 8} bitoffset {attribs {resolve_type generated dependency video_comp1_offset format long minimum {} maximum {}} value 8} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}} field_V {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value V} enabled {attribs {resolve_type generated dependency video_comp2_enabled format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency video_data_width format long minimum {} maximum {}} value 8} bitoffset {attribs {resolve_type generated dependency video_comp2_offset format long minimum {} maximum {}} value 16} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}}}}}}} TDATA_WIDTH 24} + 0.000 + 3 + 0 + 0 + 1 + 0 + zynq + 0b00000000000000000000000010010011 + 8 + 1 + 1 + 1 + 0b00000000000000000000000010010011 + 24 + 1 + 1 + 1 + Arty_Z7_20_axis_subset_converter_0_1 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 1 + 0 + 1 + 1 + 0 + 3 + 0 + 0 + 1 + tdata[7:0] + 1'b0 + 1'b0 + 1'b0 + tlast[0] + 1'b0 + tuser[0:0] + zynq + digilentinc.com:arty-z7-20:part0:1.0 + xc7z020 + clg400 + VHDL + + MIXED + -1 + + TRUE + TRUE + IP_Integrator + 11 + TRUE + . + + ../../ipshared + 2016.4 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/Arty_Z7_20_axis_subset_converter_0_1.xml b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/Arty_Z7_20_axis_subset_converter_0_1.xml new file mode 100644 index 0000000..5629b7f --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/Arty_Z7_20_axis_subset_converter_0_1.xml @@ -0,0 +1,1715 @@ + + + xilinx.com + customized_ip + Arty_Z7_20_axis_subset_converter_0_1 + 1.0 + + + S_AXIS + S_AXIS + + + + + + + TDATA + + + s_axis_tdata + + + + + TDEST + + + s_axis_tdest + + + + + TID + + + s_axis_tid + + + + + TKEEP + + + s_axis_tkeep + + + + + TLAST + + + s_axis_tlast + + + + + TREADY + + + s_axis_tready + + + + + TSTRB + + + s_axis_tstrb + + + + + TUSER + + + s_axis_tuser + + + + + TVALID + + + s_axis_tvalid + + + + + + TDATA_NUM_BYTES + 3 + + + TDEST_WIDTH + 0 + + + TID_WIDTH + 0 + + + TUSER_WIDTH + 1 + + + HAS_TREADY + 1 + + + HAS_TSTRB + 0 + + + HAS_TKEEP + 0 + + + HAS_TLAST + 1 + + + FREQ_HZ + 118181816 + + + PHASE + 0.000 + + + CLK_DOMAIN + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 + + + LAYERED_METADATA + xilinx.com:interface:datatypes:1.0 {TDATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value xilinx.com:video:Y_U_V_444:1.0} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 24} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value rows} size {attribs {resolve_type generated dependency active_rows format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency active_rows_stride format long minimum {} maximum {}} value 24} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 24} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value cols} size {attribs {resolve_type generated dependency active_cols format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency active_cols_stride format long minimum {} maximum {}} value 24} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 24} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} struct {field_Y {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value Y} enabled {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency video_data_width format long minimum {} maximum {}} value 8} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}} field_U {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value U} enabled {attribs {resolve_type generated dependency video_comp1_enabled format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency video_data_width format long minimum {} maximum {}} value 8} bitoffset {attribs {resolve_type generated dependency video_comp1_offset format long minimum {} maximum {}} value 8} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}} field_V {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value V} enabled {attribs {resolve_type generated dependency video_comp2_enabled format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency video_data_width format long minimum {} maximum {}} value 8} bitoffset {attribs {resolve_type generated dependency video_comp2_offset format long minimum {} maximum {}} value 16} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}}}}}}} TDATA_WIDTH 24} + + + + + M_AXIS + M_AXIS + + + + + + + TDATA + + + m_axis_tdata + + + + + TDEST + + + m_axis_tdest + + + + + TID + + + m_axis_tid + + + + + TKEEP + + + m_axis_tkeep + + + + + TLAST + + + m_axis_tlast + + + + + TREADY + + + m_axis_tready + + + + + TSTRB + + + m_axis_tstrb + + + + + TUSER + + + m_axis_tuser + + + + + TVALID + + + m_axis_tvalid + + + + + + TDATA_NUM_BYTES + 1 + + + TDEST_WIDTH + 0 + + + TID_WIDTH + 0 + + + TUSER_WIDTH + 1 + + + HAS_TREADY + 1 + + + HAS_TSTRB + 0 + + + HAS_TKEEP + 0 + + + HAS_TLAST + 1 + + + FREQ_HZ + 118181816 + + + PHASE + 0.000 + + + CLK_DOMAIN + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 + + + LAYERED_METADATA + undef + + + + + RSTIF + RSTIF + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + TYPE + INTERCONNECT + + + + + CLKIF + CLKIF + + + + + + + CLK + + + aclk + + + + + + FREQ_HZ + 118181816 + + + PHASE + 0.000 + + + CLK_DOMAIN + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 + + + ASSOCIATED_BUSIF + S_AXIS:M_AXIS + + + ASSOCIATED_RESET + aresetn + + + ASSOCIATED_CLKEN + aclken + + + + + CLKENIF + CLKENIF + + + + + + + CE + + + aclken + + + + + + + false + + + + + + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + top_Arty_Z7_20_axis_subset_converter_0_1 + + xilinx_verilogsynthesis_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset + + + xilinx_verilogsynthesis_xilinx_com_ip_axis_register_slice_1_1__ref_view_fileset + + + xilinx_verilogsynthesis_view_fileset + + + + GENtimestamp + Mon Mar 06 19:32:59 UTC 2017 + + + boundaryCRC + 51a6b79d + + + boundaryCRCversion + 1 + + + customizationCRC + b4ea1bb0 + + + customizationCRCversion + 6 + + + + + xilinx_verilogsynthesiswrapper + Verilog Synthesis Wrapper + verilogSource:vivado.xilinx.com:synthesis.wrapper + verilog + + xilinx_verilogsynthesiswrapper_view_fileset + + + + GENtimestamp + Mon Mar 06 19:32:59 UTC 2017 + + + boundaryCRC + 51a6b79d + + + boundaryCRCversion + 1 + + + customizationCRC + b4ea1bb0 + + + customizationCRCversion + 6 + + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + top_Arty_Z7_20_axis_subset_converter_0_1 + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axis_register_slice_1_1__ref_view_fileset + + + xilinx_verilogbehavioralsimulation_view_fileset + + + + GENtimestamp + Mon Mar 06 19:32:59 UTC 2017 + + + boundaryCRC + 51a6b79d + + + boundaryCRCversion + 1 + + + customizationCRC + 7b6844ee + + + customizationCRCversion + 6 + + + + + xilinx_verilogsimulationwrapper + Verilog Simulation Wrapper + verilogSource:vivado.xilinx.com:simulation.wrapper + verilog + + xilinx_verilogsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Mar 06 19:32:59 UTC 2017 + + + boundaryCRC + 51a6b79d + + + boundaryCRCversion + 1 + + + customizationCRC + 7b6844ee + + + customizationCRCversion + 6 + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Mon Mar 06 19:33:53 UTC 2017 + + + boundaryCRC + 51a6b79d + + + boundaryCRCversion + 1 + + + customizationCRC + b4ea1bb0 + + + customizationCRCversion + 6 + + + + + + + aclk + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + aresetn + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + aclken + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x1 + + + + + + false + + + + + + s_axis_tvalid + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0 + + + + + s_axis_tready + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + s_axis_tdata + + in + + 23 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x000000 + + + + + + true + + + + + + s_axis_tstrb + + in + + 2 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x7 + + + + + + false + + + + + + s_axis_tkeep + + in + + 2 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x7 + + + + + + false + + + + + + s_axis_tlast + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x1 + + + + + + true + + + + + + s_axis_tid + + in + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0 + + + + + + false + + + + + + s_axis_tdest + + in + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0 + + + + + + false + + + + + + s_axis_tuser + + in + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0 + + + + + + true + + + + + + m_axis_tvalid + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axis_tready + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x1 + + + + + + true + + + + + + m_axis_tdata + + out + + 7 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axis_tstrb + + out + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axis_tkeep + + out + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axis_tlast + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axis_tid + + out + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axis_tdest + + out + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axis_tuser + + out + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + transfer_dropped + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + sparse_tkeep_removed + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + + + C_FAMILY + zynq + + + C_S_AXIS_TDATA_WIDTH + 24 + + + C_S_AXIS_TID_WIDTH + 1 + + + C_S_AXIS_TDEST_WIDTH + 1 + + + C_S_AXIS_TUSER_WIDTH + 1 + + + C_S_AXIS_SIGNAL_SET + 0b00000000000000000000000010010011 + + + C_M_AXIS_TDATA_WIDTH + 8 + + + C_M_AXIS_TID_WIDTH + 1 + + + C_M_AXIS_TDEST_WIDTH + 1 + + + C_M_AXIS_SIGNAL_SET + 0b00000000000000000000000010010011 + + + C_M_AXIS_TUSER_WIDTH + 1 + + + C_DEFAULT_TLAST + 0 + + + + + + choice_pairs_37189c7b + 0 + 1 + + + + + xilinx_verilogsynthesis_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset + + ../../ipshared/fe67/hdl/axis_infrastructure_v1_1_0.vh + verilogSource + true + axis_infrastructure_v1_1_0 + + + ../../ipshared/fe67/hdl/axis_infrastructure_v1_1_vl_rfs.v + verilogSource + axis_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogsynthesis_xilinx_com_ip_axis_register_slice_1_1__ref_view_fileset + + ../../ipshared/09aa/hdl/axis_register_slice_v1_1_vl_rfs.v + verilogSource + axis_register_slice_v1_1_11 + + + + + + + + + + + xilinx_verilogsynthesis_view_fileset + + hdl/tdata_Arty_Z7_20_axis_subset_converter_0_1.v + verilogSource + xil_defaultlib + tdata_Arty_Z7_20_axis_subset_converter_0_1 + + + hdl/tuser_Arty_Z7_20_axis_subset_converter_0_1.v + verilogSource + xil_defaultlib + tuser_Arty_Z7_20_axis_subset_converter_0_1 + + + hdl/tstrb_Arty_Z7_20_axis_subset_converter_0_1.v + verilogSource + xil_defaultlib + tstrb_Arty_Z7_20_axis_subset_converter_0_1 + + + hdl/tkeep_Arty_Z7_20_axis_subset_converter_0_1.v + verilogSource + xil_defaultlib + tkeep_Arty_Z7_20_axis_subset_converter_0_1 + + + hdl/tid_Arty_Z7_20_axis_subset_converter_0_1.v + verilogSource + xil_defaultlib + tid_Arty_Z7_20_axis_subset_converter_0_1 + + + hdl/tdest_Arty_Z7_20_axis_subset_converter_0_1.v + verilogSource + xil_defaultlib + tdest_Arty_Z7_20_axis_subset_converter_0_1 + + + hdl/tlast_Arty_Z7_20_axis_subset_converter_0_1.v + verilogSource + xil_defaultlib + tlast_Arty_Z7_20_axis_subset_converter_0_1 + + + ../../ipshared/8a5f/hdl/axis_subset_converter_v1_1_vl_rfs.v + verilogSource + axis_subset_converter_v1_1_11 + + + Arty_Z7_20_axis_subset_converter_0_1_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + hdl/top_Arty_Z7_20_axis_subset_converter_0_1.v + verilogSource + xil_defaultlib + top_Arty_Z7_20_axis_subset_converter_0_1 + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/Arty_Z7_20_axis_subset_converter_0_1.v + verilogSource + xil_defaultlib + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset + + ../../ipshared/fe67/hdl/axis_infrastructure_v1_1_0.vh + verilogSource + USED_IN_ipstatic + true + axis_infrastructure_v1_1_0 + + + ../../ipshared/fe67/hdl/axis_infrastructure_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axis_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axis_register_slice_1_1__ref_view_fileset + + ../../ipshared/09aa/hdl/axis_register_slice_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axis_register_slice_v1_1_11 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + hdl/tdata_Arty_Z7_20_axis_subset_converter_0_1.v + verilogSource + xil_defaultlib + tdata_Arty_Z7_20_axis_subset_converter_0_1 + + + hdl/tuser_Arty_Z7_20_axis_subset_converter_0_1.v + verilogSource + xil_defaultlib + tuser_Arty_Z7_20_axis_subset_converter_0_1 + + + hdl/tstrb_Arty_Z7_20_axis_subset_converter_0_1.v + verilogSource + xil_defaultlib + tstrb_Arty_Z7_20_axis_subset_converter_0_1 + + + hdl/tkeep_Arty_Z7_20_axis_subset_converter_0_1.v + verilogSource + xil_defaultlib + tkeep_Arty_Z7_20_axis_subset_converter_0_1 + + + hdl/tid_Arty_Z7_20_axis_subset_converter_0_1.v + verilogSource + xil_defaultlib + tid_Arty_Z7_20_axis_subset_converter_0_1 + + + hdl/tdest_Arty_Z7_20_axis_subset_converter_0_1.v + verilogSource + xil_defaultlib + tdest_Arty_Z7_20_axis_subset_converter_0_1 + + + hdl/tlast_Arty_Z7_20_axis_subset_converter_0_1.v + verilogSource + xil_defaultlib + tlast_Arty_Z7_20_axis_subset_converter_0_1 + + + ../../ipshared/8a5f/hdl/axis_subset_converter_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axis_subset_converter_v1_1_11 + + + hdl/top_Arty_Z7_20_axis_subset_converter_0_1.v + verilogSource + xil_defaultlib + top_Arty_Z7_20_axis_subset_converter_0_1 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/Arty_Z7_20_axis_subset_converter_0_1.v + verilogSource + xil_defaultlib + + + + xilinx_externalfiles_view_fileset + + Arty_Z7_20_axis_subset_converter_0_1.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + Arty_Z7_20_axis_subset_converter_0_1_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Arty_Z7_20_axis_subset_converter_0_1_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Arty_Z7_20_axis_subset_converter_0_1_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Arty_Z7_20_axis_subset_converter_0_1_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + The AXI4-Stream Subset Converter IP provides the infrastructure to change the AXI4-Stream interface characteristics between a AXI4-Stream master and slave. + + + S_TDATA_NUM_BYTES + TDATA Width (bytes) + 3 + + + + true + + + + + + M_TDATA_NUM_BYTES + TDATA Width (bytes) + 1 + + + + true + + + + + + S_TID_WIDTH + TID Width (bits) + 0 + + + + true + + + + + + M_TID_WIDTH + TID Width (bits) + 0 + + + + true + + + + + + S_TDEST_WIDTH + DEST Width (bits) + 0 + + + + true + + + + + + M_TDEST_WIDTH + DEST Width (bits) + 0 + + + + true + + + + + + S_TUSER_WIDTH + USER Width (bits) + 1 + + + + true + + + + + + M_TUSER_WIDTH + USER Width (bits) + 1 + + + + true + + + + + + S_HAS_TREADY + Enable TREADY + 1 + + + + true + + + + + + S_HAS_TSTRB + Enable TSTRB + 0 + + + + true + + + + + + S_HAS_TKEEP + Enable TKEEP + 0 + + + + true + + + + + + S_HAS_TLAST + Enable TLAST + 1 + + + + true + + + + + + M_HAS_TREADY + Enable TREADY + 1 + + + + true + + + + + + M_HAS_TSTRB + Enable TSTRB + 0 + + + + true + + + + + + M_HAS_TKEEP + Enable TKEEP + 0 + + + + true + + + + + + M_HAS_TLAST + Enable TLAST + 1 + + + + true + + + + + + HAS_ACLKEN + Enable ACLKEN + 0 + + + + true + + + + + + DEFAULT_TLAST + Generate TLAST + 0 + + + + false + + + + + + TDATA_REMAP + TDATA Remap String + tdata[7:0] + + + + true + + + + + + TUSER_REMAP + TUSER Remap String + tuser[0:0] + + + + true + + + + + + TID_REMAP + TID Remap String + 1'b0 + + + + true + + + + + + TDEST_REMAP + TDEST Remap String + 1'b0 + + + + true + + + + + + TKEEP_REMAP + TKEEP Remap String + 1'b0 + + + + true + + + + + + TSTRB_REMAP + TSTRB Remap String + 1'b0 + + + + true + + + + + + TLAST_REMAP + TLAST Remap String + tlast[0] + + + + true + + + + + + Component_Name + Arty_Z7_20_axis_subset_converter_0_1 + + + + + AXI4-Stream Subset Converter + 11 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2016.4 + + + + + + + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/Arty_Z7_20_axis_subset_converter_0_1_ooc.xdc b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/Arty_Z7_20_axis_subset_converter_0_1_ooc.xdc new file mode 100644 index 0000000..70a2fbc --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/Arty_Z7_20_axis_subset_converter_0_1_ooc.xdc @@ -0,0 +1,50 @@ +# (c) Copyright 2013 - 2017 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#----------------------------------------------------------------------------- + +# M_HAS_TREADY = 1 +# S_HAS_TREADY = 1 +# No clock in this configuration diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/Arty_Z7_20_axis_subset_converter_0_1_sim_netlist.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/Arty_Z7_20_axis_subset_converter_0_1_sim_netlist.v new file mode 100644 index 0000000..2e9e5d5 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/Arty_Z7_20_axis_subset_converter_0_1_sim_netlist.v @@ -0,0 +1,268 @@ +// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +// Date : Mon Mar 06 11:33:53 2017 +// Host : WK73 running 64-bit Service Pack 1 (build 7601) +// Command : write_verilog -force -mode funcsim +// C:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/Arty_Z7_20_axis_subset_converter_0_1_sim_netlist.v +// Design : Arty_Z7_20_axis_subset_converter_0_1 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg400-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "Arty_Z7_20_axis_subset_converter_0_1,top_Arty_Z7_20_axis_subset_converter_0_1,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "top_Arty_Z7_20_axis_subset_converter_0_1,Vivado 2016.4" *) +(* NotValidForBitStream *) +module Arty_Z7_20_axis_subset_converter_0_1 + (aclk, + aresetn, + s_axis_tvalid, + s_axis_tready, + s_axis_tdata, + s_axis_tlast, + s_axis_tuser, + m_axis_tvalid, + m_axis_tready, + m_axis_tdata, + m_axis_tlast, + m_axis_tuser); + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) input aclk; + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) input aresetn; + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) input s_axis_tvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) output s_axis_tready; + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) input [23:0]s_axis_tdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *) input s_axis_tlast; + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TUSER" *) input [0:0]s_axis_tuser; + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *) output m_axis_tvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *) input m_axis_tready; + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *) output [7:0]m_axis_tdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *) output m_axis_tlast; + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TUSER" *) output [0:0]m_axis_tuser; + + wire aclk; + wire aresetn; + wire [7:0]m_axis_tdata; + wire m_axis_tlast; + wire m_axis_tready; + wire [0:0]m_axis_tuser; + wire m_axis_tvalid; + wire [23:0]s_axis_tdata; + wire s_axis_tlast; + wire s_axis_tready; + wire [0:0]s_axis_tuser; + wire s_axis_tvalid; + wire NLW_inst_sparse_tkeep_removed_UNCONNECTED; + wire NLW_inst_transfer_dropped_UNCONNECTED; + wire [0:0]NLW_inst_m_axis_tdest_UNCONNECTED; + wire [0:0]NLW_inst_m_axis_tid_UNCONNECTED; + wire [0:0]NLW_inst_m_axis_tkeep_UNCONNECTED; + wire [0:0]NLW_inst_m_axis_tstrb_UNCONNECTED; + + (* C_DEFAULT_TLAST = "0" *) + (* C_FAMILY = "zynq" *) + (* C_M_AXIS_SIGNAL_SET = "32'b00000000000000000000000010010011" *) + (* C_M_AXIS_TDATA_WIDTH = "8" *) + (* C_M_AXIS_TDEST_WIDTH = "1" *) + (* C_M_AXIS_TID_WIDTH = "1" *) + (* C_M_AXIS_TUSER_WIDTH = "1" *) + (* C_S_AXIS_SIGNAL_SET = "32'b00000000000000000000000010010011" *) + (* C_S_AXIS_TDATA_WIDTH = "24" *) + (* C_S_AXIS_TDEST_WIDTH = "1" *) + (* C_S_AXIS_TID_WIDTH = "1" *) + (* C_S_AXIS_TUSER_WIDTH = "1" *) + (* G_INDX_SS_TDATA = "1" *) + (* G_INDX_SS_TDEST = "6" *) + (* G_INDX_SS_TID = "5" *) + (* G_INDX_SS_TKEEP = "3" *) + (* G_INDX_SS_TLAST = "4" *) + (* G_INDX_SS_TREADY = "0" *) + (* G_INDX_SS_TSTRB = "2" *) + (* G_INDX_SS_TUSER = "7" *) + (* G_MASK_SS_TDATA = "2" *) + (* G_MASK_SS_TDEST = "64" *) + (* G_MASK_SS_TID = "32" *) + (* G_MASK_SS_TKEEP = "8" *) + (* G_MASK_SS_TLAST = "16" *) + (* G_MASK_SS_TREADY = "1" *) + (* G_MASK_SS_TSTRB = "4" *) + (* G_MASK_SS_TUSER = "128" *) + (* G_TASK_SEVERITY_ERR = "2" *) + (* G_TASK_SEVERITY_INFO = "0" *) + (* G_TASK_SEVERITY_WARNING = "1" *) + Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 inst + (.aclk(aclk), + .aclken(1'b1), + .aresetn(aresetn), + .m_axis_tdata(m_axis_tdata), + .m_axis_tdest(NLW_inst_m_axis_tdest_UNCONNECTED[0]), + .m_axis_tid(NLW_inst_m_axis_tid_UNCONNECTED[0]), + .m_axis_tkeep(NLW_inst_m_axis_tkeep_UNCONNECTED[0]), + .m_axis_tlast(m_axis_tlast), + .m_axis_tready(m_axis_tready), + .m_axis_tstrb(NLW_inst_m_axis_tstrb_UNCONNECTED[0]), + .m_axis_tuser(m_axis_tuser), + .m_axis_tvalid(m_axis_tvalid), + .s_axis_tdata(s_axis_tdata), + .s_axis_tdest(1'b0), + .s_axis_tid(1'b0), + .s_axis_tkeep({1'b1,1'b1,1'b1}), + .s_axis_tlast(s_axis_tlast), + .s_axis_tready(s_axis_tready), + .s_axis_tstrb({1'b1,1'b1,1'b1}), + .s_axis_tuser(s_axis_tuser), + .s_axis_tvalid(s_axis_tvalid), + .sparse_tkeep_removed(NLW_inst_sparse_tkeep_removed_UNCONNECTED), + .transfer_dropped(NLW_inst_transfer_dropped_UNCONNECTED)); +endmodule + +(* C_DEFAULT_TLAST = "0" *) (* C_FAMILY = "zynq" *) (* C_M_AXIS_SIGNAL_SET = "32'b00000000000000000000000010010011" *) +(* C_M_AXIS_TDATA_WIDTH = "8" *) (* C_M_AXIS_TDEST_WIDTH = "1" *) (* C_M_AXIS_TID_WIDTH = "1" *) +(* C_M_AXIS_TUSER_WIDTH = "1" *) (* C_S_AXIS_SIGNAL_SET = "32'b00000000000000000000000010010011" *) (* C_S_AXIS_TDATA_WIDTH = "24" *) +(* C_S_AXIS_TDEST_WIDTH = "1" *) (* C_S_AXIS_TID_WIDTH = "1" *) (* C_S_AXIS_TUSER_WIDTH = "1" *) +(* G_INDX_SS_TDATA = "1" *) (* G_INDX_SS_TDEST = "6" *) (* G_INDX_SS_TID = "5" *) +(* G_INDX_SS_TKEEP = "3" *) (* G_INDX_SS_TLAST = "4" *) (* G_INDX_SS_TREADY = "0" *) +(* G_INDX_SS_TSTRB = "2" *) (* G_INDX_SS_TUSER = "7" *) (* G_MASK_SS_TDATA = "2" *) +(* G_MASK_SS_TDEST = "64" *) (* G_MASK_SS_TID = "32" *) (* G_MASK_SS_TKEEP = "8" *) +(* G_MASK_SS_TLAST = "16" *) (* G_MASK_SS_TREADY = "1" *) (* G_MASK_SS_TSTRB = "4" *) +(* G_MASK_SS_TUSER = "128" *) (* G_TASK_SEVERITY_ERR = "2" *) (* G_TASK_SEVERITY_INFO = "0" *) +(* G_TASK_SEVERITY_WARNING = "1" *) (* ORIG_REF_NAME = "top_Arty_Z7_20_axis_subset_converter_0_1" *) +module Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 + (aclk, + aresetn, + aclken, + s_axis_tvalid, + s_axis_tready, + s_axis_tdata, + s_axis_tstrb, + s_axis_tkeep, + s_axis_tlast, + s_axis_tid, + s_axis_tdest, + s_axis_tuser, + m_axis_tvalid, + m_axis_tready, + m_axis_tdata, + m_axis_tstrb, + m_axis_tkeep, + m_axis_tlast, + m_axis_tid, + m_axis_tdest, + m_axis_tuser, + transfer_dropped, + sparse_tkeep_removed); + input aclk; + input aresetn; + input aclken; + input s_axis_tvalid; + output s_axis_tready; + input [23:0]s_axis_tdata; + input [2:0]s_axis_tstrb; + input [2:0]s_axis_tkeep; + input s_axis_tlast; + input [0:0]s_axis_tid; + input [0:0]s_axis_tdest; + input [0:0]s_axis_tuser; + output m_axis_tvalid; + input m_axis_tready; + output [7:0]m_axis_tdata; + output [0:0]m_axis_tstrb; + output [0:0]m_axis_tkeep; + output m_axis_tlast; + output [0:0]m_axis_tid; + output [0:0]m_axis_tdest; + output [0:0]m_axis_tuser; + output transfer_dropped; + output sparse_tkeep_removed; + + wire \ ; + wire m_axis_tready; + wire [23:0]s_axis_tdata; + wire s_axis_tlast; + wire [0:0]s_axis_tuser; + wire s_axis_tvalid; + + assign m_axis_tdata[7:0] = s_axis_tdata[7:0]; + assign m_axis_tdest[0] = \ ; + assign m_axis_tid[0] = \ ; + assign m_axis_tkeep[0] = \ ; + assign m_axis_tlast = s_axis_tlast; + assign m_axis_tstrb[0] = \ ; + assign m_axis_tuser[0] = s_axis_tuser; + assign m_axis_tvalid = s_axis_tvalid; + assign s_axis_tready = m_axis_tready; + assign sparse_tkeep_removed = \ ; + assign transfer_dropped = \ ; + GND GND + (.G(\ )); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/Arty_Z7_20_axis_subset_converter_0_1_sim_netlist.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/Arty_Z7_20_axis_subset_converter_0_1_sim_netlist.vhdl new file mode 100644 index 0000000..635ac75 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/Arty_Z7_20_axis_subset_converter_0_1_sim_netlist.vhdl @@ -0,0 +1,263 @@ +-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +-- Date : Mon Mar 06 11:33:53 2017 +-- Host : WK73 running 64-bit Service Pack 1 (build 7601) +-- Command : write_vhdl -force -mode funcsim +-- C:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/Arty_Z7_20_axis_subset_converter_0_1_sim_netlist.vhdl +-- Design : Arty_Z7_20_axis_subset_converter_0_1 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg400-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 is + port ( + aclk : in STD_LOGIC; + aresetn : in STD_LOGIC; + aclken : in STD_LOGIC; + s_axis_tvalid : in STD_LOGIC; + s_axis_tready : out STD_LOGIC; + s_axis_tdata : in STD_LOGIC_VECTOR ( 23 downto 0 ); + s_axis_tstrb : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axis_tkeep : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axis_tlast : in STD_LOGIC; + s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axis_tuser : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axis_tvalid : out STD_LOGIC; + m_axis_tready : in STD_LOGIC; + m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axis_tlast : out STD_LOGIC; + m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axis_tuser : out STD_LOGIC_VECTOR ( 0 to 0 ); + transfer_dropped : out STD_LOGIC; + sparse_tkeep_removed : out STD_LOGIC + ); + attribute C_DEFAULT_TLAST : integer; + attribute C_DEFAULT_TLAST of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is 0; + attribute C_FAMILY : string; + attribute C_FAMILY of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is "zynq"; + attribute C_M_AXIS_SIGNAL_SET : string; + attribute C_M_AXIS_SIGNAL_SET of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is "32'b00000000000000000000000010010011"; + attribute C_M_AXIS_TDATA_WIDTH : integer; + attribute C_M_AXIS_TDATA_WIDTH of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is 8; + attribute C_M_AXIS_TDEST_WIDTH : integer; + attribute C_M_AXIS_TDEST_WIDTH of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is 1; + attribute C_M_AXIS_TID_WIDTH : integer; + attribute C_M_AXIS_TID_WIDTH of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is 1; + attribute C_M_AXIS_TUSER_WIDTH : integer; + attribute C_M_AXIS_TUSER_WIDTH of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is 1; + attribute C_S_AXIS_SIGNAL_SET : string; + attribute C_S_AXIS_SIGNAL_SET of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is "32'b00000000000000000000000010010011"; + attribute C_S_AXIS_TDATA_WIDTH : integer; + attribute C_S_AXIS_TDATA_WIDTH of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is 24; + attribute C_S_AXIS_TDEST_WIDTH : integer; + attribute C_S_AXIS_TDEST_WIDTH of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is 1; + attribute C_S_AXIS_TID_WIDTH : integer; + attribute C_S_AXIS_TID_WIDTH of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is 1; + attribute C_S_AXIS_TUSER_WIDTH : integer; + attribute C_S_AXIS_TUSER_WIDTH of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is 1; + attribute G_INDX_SS_TDATA : integer; + attribute G_INDX_SS_TDATA of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is 1; + attribute G_INDX_SS_TDEST : integer; + attribute G_INDX_SS_TDEST of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is 6; + attribute G_INDX_SS_TID : integer; + attribute G_INDX_SS_TID of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is 5; + attribute G_INDX_SS_TKEEP : integer; + attribute G_INDX_SS_TKEEP of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is 3; + attribute G_INDX_SS_TLAST : integer; + attribute G_INDX_SS_TLAST of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is 4; + attribute G_INDX_SS_TREADY : integer; + attribute G_INDX_SS_TREADY of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is 0; + attribute G_INDX_SS_TSTRB : integer; + attribute G_INDX_SS_TSTRB of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is 2; + attribute G_INDX_SS_TUSER : integer; + attribute G_INDX_SS_TUSER of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is 7; + attribute G_MASK_SS_TDATA : integer; + attribute G_MASK_SS_TDATA of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is 2; + attribute G_MASK_SS_TDEST : integer; + attribute G_MASK_SS_TDEST of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is 64; + attribute G_MASK_SS_TID : integer; + attribute G_MASK_SS_TID of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is 32; + attribute G_MASK_SS_TKEEP : integer; + attribute G_MASK_SS_TKEEP of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is 8; + attribute G_MASK_SS_TLAST : integer; + attribute G_MASK_SS_TLAST of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is 16; + attribute G_MASK_SS_TREADY : integer; + attribute G_MASK_SS_TREADY of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is 1; + attribute G_MASK_SS_TSTRB : integer; + attribute G_MASK_SS_TSTRB of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is 4; + attribute G_MASK_SS_TUSER : integer; + attribute G_MASK_SS_TUSER of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is 128; + attribute G_TASK_SEVERITY_ERR : integer; + attribute G_TASK_SEVERITY_ERR of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is 2; + attribute G_TASK_SEVERITY_INFO : integer; + attribute G_TASK_SEVERITY_INFO of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is 0; + attribute G_TASK_SEVERITY_WARNING : integer; + attribute G_TASK_SEVERITY_WARNING of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is 1; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 : entity is "top_Arty_Z7_20_axis_subset_converter_0_1"; +end Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1; + +architecture STRUCTURE of Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 is + signal \\ : STD_LOGIC; + signal \^m_axis_tready\ : STD_LOGIC; + signal \^s_axis_tdata\ : STD_LOGIC_VECTOR ( 23 downto 0 ); + signal \^s_axis_tlast\ : STD_LOGIC; + signal \^s_axis_tuser\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^s_axis_tvalid\ : STD_LOGIC; +begin + \^m_axis_tready\ <= m_axis_tready; + \^s_axis_tdata\(7 downto 0) <= s_axis_tdata(7 downto 0); + \^s_axis_tlast\ <= s_axis_tlast; + \^s_axis_tuser\(0) <= s_axis_tuser(0); + \^s_axis_tvalid\ <= s_axis_tvalid; + m_axis_tdata(7 downto 0) <= \^s_axis_tdata\(7 downto 0); + m_axis_tdest(0) <= \\; + m_axis_tid(0) <= \\; + m_axis_tkeep(0) <= \\; + m_axis_tlast <= \^s_axis_tlast\; + m_axis_tstrb(0) <= \\; + m_axis_tuser(0) <= \^s_axis_tuser\(0); + m_axis_tvalid <= \^s_axis_tvalid\; + s_axis_tready <= \^m_axis_tready\; + sparse_tkeep_removed <= \\; + transfer_dropped <= \\; +GND: unisim.vcomponents.GND + port map ( + G => \\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_axis_subset_converter_0_1 is + port ( + aclk : in STD_LOGIC; + aresetn : in STD_LOGIC; + s_axis_tvalid : in STD_LOGIC; + s_axis_tready : out STD_LOGIC; + s_axis_tdata : in STD_LOGIC_VECTOR ( 23 downto 0 ); + s_axis_tlast : in STD_LOGIC; + s_axis_tuser : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axis_tvalid : out STD_LOGIC; + m_axis_tready : in STD_LOGIC; + m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axis_tlast : out STD_LOGIC; + m_axis_tuser : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of Arty_Z7_20_axis_subset_converter_0_1 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of Arty_Z7_20_axis_subset_converter_0_1 : entity is "Arty_Z7_20_axis_subset_converter_0_1,top_Arty_Z7_20_axis_subset_converter_0_1,{}"; + attribute DowngradeIPIdentifiedWarnings : string; + attribute DowngradeIPIdentifiedWarnings of Arty_Z7_20_axis_subset_converter_0_1 : entity is "yes"; + attribute X_CORE_INFO : string; + attribute X_CORE_INFO of Arty_Z7_20_axis_subset_converter_0_1 : entity is "top_Arty_Z7_20_axis_subset_converter_0_1,Vivado 2016.4"; +end Arty_Z7_20_axis_subset_converter_0_1; + +architecture STRUCTURE of Arty_Z7_20_axis_subset_converter_0_1 is + signal NLW_inst_sparse_tkeep_removed_UNCONNECTED : STD_LOGIC; + signal NLW_inst_transfer_dropped_UNCONNECTED : STD_LOGIC; + signal NLW_inst_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + attribute C_DEFAULT_TLAST : integer; + attribute C_DEFAULT_TLAST of inst : label is 0; + attribute C_FAMILY : string; + attribute C_FAMILY of inst : label is "zynq"; + attribute C_M_AXIS_SIGNAL_SET : string; + attribute C_M_AXIS_SIGNAL_SET of inst : label is "32'b00000000000000000000000010010011"; + attribute C_M_AXIS_TDATA_WIDTH : integer; + attribute C_M_AXIS_TDATA_WIDTH of inst : label is 8; + attribute C_M_AXIS_TDEST_WIDTH : integer; + attribute C_M_AXIS_TDEST_WIDTH of inst : label is 1; + attribute C_M_AXIS_TID_WIDTH : integer; + attribute C_M_AXIS_TID_WIDTH of inst : label is 1; + attribute C_M_AXIS_TUSER_WIDTH : integer; + attribute C_M_AXIS_TUSER_WIDTH of inst : label is 1; + attribute C_S_AXIS_SIGNAL_SET : string; + attribute C_S_AXIS_SIGNAL_SET of inst : label is "32'b00000000000000000000000010010011"; + attribute C_S_AXIS_TDATA_WIDTH : integer; + attribute C_S_AXIS_TDATA_WIDTH of inst : label is 24; + attribute C_S_AXIS_TDEST_WIDTH : integer; + attribute C_S_AXIS_TDEST_WIDTH of inst : label is 1; + attribute C_S_AXIS_TID_WIDTH : integer; + attribute C_S_AXIS_TID_WIDTH of inst : label is 1; + attribute C_S_AXIS_TUSER_WIDTH : integer; + attribute C_S_AXIS_TUSER_WIDTH of inst : label is 1; + attribute G_INDX_SS_TDATA : integer; + attribute G_INDX_SS_TDATA of inst : label is 1; + attribute G_INDX_SS_TDEST : integer; + attribute G_INDX_SS_TDEST of inst : label is 6; + attribute G_INDX_SS_TID : integer; + attribute G_INDX_SS_TID of inst : label is 5; + attribute G_INDX_SS_TKEEP : integer; + attribute G_INDX_SS_TKEEP of inst : label is 3; + attribute G_INDX_SS_TLAST : integer; + attribute G_INDX_SS_TLAST of inst : label is 4; + attribute G_INDX_SS_TREADY : integer; + attribute G_INDX_SS_TREADY of inst : label is 0; + attribute G_INDX_SS_TSTRB : integer; + attribute G_INDX_SS_TSTRB of inst : label is 2; + attribute G_INDX_SS_TUSER : integer; + attribute G_INDX_SS_TUSER of inst : label is 7; + attribute G_MASK_SS_TDATA : integer; + attribute G_MASK_SS_TDATA of inst : label is 2; + attribute G_MASK_SS_TDEST : integer; + attribute G_MASK_SS_TDEST of inst : label is 64; + attribute G_MASK_SS_TID : integer; + attribute G_MASK_SS_TID of inst : label is 32; + attribute G_MASK_SS_TKEEP : integer; + attribute G_MASK_SS_TKEEP of inst : label is 8; + attribute G_MASK_SS_TLAST : integer; + attribute G_MASK_SS_TLAST of inst : label is 16; + attribute G_MASK_SS_TREADY : integer; + attribute G_MASK_SS_TREADY of inst : label is 1; + attribute G_MASK_SS_TSTRB : integer; + attribute G_MASK_SS_TSTRB of inst : label is 4; + attribute G_MASK_SS_TUSER : integer; + attribute G_MASK_SS_TUSER of inst : label is 128; + attribute G_TASK_SEVERITY_ERR : integer; + attribute G_TASK_SEVERITY_ERR of inst : label is 2; + attribute G_TASK_SEVERITY_INFO : integer; + attribute G_TASK_SEVERITY_INFO of inst : label is 0; + attribute G_TASK_SEVERITY_WARNING : integer; + attribute G_TASK_SEVERITY_WARNING of inst : label is 1; +begin +inst: entity work.Arty_Z7_20_axis_subset_converter_0_1_top_Arty_Z7_20_axis_subset_converter_0_1 + port map ( + aclk => aclk, + aclken => '1', + aresetn => aresetn, + m_axis_tdata(7 downto 0) => m_axis_tdata(7 downto 0), + m_axis_tdest(0) => NLW_inst_m_axis_tdest_UNCONNECTED(0), + m_axis_tid(0) => NLW_inst_m_axis_tid_UNCONNECTED(0), + m_axis_tkeep(0) => NLW_inst_m_axis_tkeep_UNCONNECTED(0), + m_axis_tlast => m_axis_tlast, + m_axis_tready => m_axis_tready, + m_axis_tstrb(0) => NLW_inst_m_axis_tstrb_UNCONNECTED(0), + m_axis_tuser(0) => m_axis_tuser(0), + m_axis_tvalid => m_axis_tvalid, + s_axis_tdata(23 downto 0) => s_axis_tdata(23 downto 0), + s_axis_tdest(0) => '0', + s_axis_tid(0) => '0', + s_axis_tkeep(2 downto 0) => B"111", + s_axis_tlast => s_axis_tlast, + s_axis_tready => s_axis_tready, + s_axis_tstrb(2 downto 0) => B"111", + s_axis_tuser(0) => s_axis_tuser(0), + s_axis_tvalid => s_axis_tvalid, + sparse_tkeep_removed => NLW_inst_sparse_tkeep_removed_UNCONNECTED, + transfer_dropped => NLW_inst_transfer_dropped_UNCONNECTED + ); +end STRUCTURE; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/Arty_Z7_20_axis_subset_converter_0_1_stub.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/Arty_Z7_20_axis_subset_converter_0_1_stub.v new file mode 100644 index 0000000..508dd16 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/Arty_Z7_20_axis_subset_converter_0_1_stub.v @@ -0,0 +1,33 @@ +// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +// Date : Mon Mar 06 11:33:53 2017 +// Host : WK73 running 64-bit Service Pack 1 (build 7601) +// Command : write_verilog -force -mode synth_stub +// C:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/Arty_Z7_20_axis_subset_converter_0_1_stub.v +// Design : Arty_Z7_20_axis_subset_converter_0_1 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg400-1 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "top_Arty_Z7_20_axis_subset_converter_0_1,Vivado 2016.4" *) +module Arty_Z7_20_axis_subset_converter_0_1(aclk, aresetn, s_axis_tvalid, s_axis_tready, + s_axis_tdata, s_axis_tlast, s_axis_tuser, m_axis_tvalid, m_axis_tready, m_axis_tdata, + m_axis_tlast, m_axis_tuser) +/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[23:0],s_axis_tlast,s_axis_tuser[0:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[7:0],m_axis_tlast,m_axis_tuser[0:0]" */; + input aclk; + input aresetn; + input s_axis_tvalid; + output s_axis_tready; + input [23:0]s_axis_tdata; + input s_axis_tlast; + input [0:0]s_axis_tuser; + output m_axis_tvalid; + input m_axis_tready; + output [7:0]m_axis_tdata; + output m_axis_tlast; + output [0:0]m_axis_tuser; +endmodule diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/Arty_Z7_20_axis_subset_converter_0_1_stub.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/Arty_Z7_20_axis_subset_converter_0_1_stub.vhdl new file mode 100644 index 0000000..8619624 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/Arty_Z7_20_axis_subset_converter_0_1_stub.vhdl @@ -0,0 +1,41 @@ +-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +-- Date : Mon Mar 06 11:33:53 2017 +-- Host : WK73 running 64-bit Service Pack 1 (build 7601) +-- Command : write_vhdl -force -mode synth_stub +-- C:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/Arty_Z7_20_axis_subset_converter_0_1_stub.vhdl +-- Design : Arty_Z7_20_axis_subset_converter_0_1 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg400-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Arty_Z7_20_axis_subset_converter_0_1 is + Port ( + aclk : in STD_LOGIC; + aresetn : in STD_LOGIC; + s_axis_tvalid : in STD_LOGIC; + s_axis_tready : out STD_LOGIC; + s_axis_tdata : in STD_LOGIC_VECTOR ( 23 downto 0 ); + s_axis_tlast : in STD_LOGIC; + s_axis_tuser : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axis_tvalid : out STD_LOGIC; + m_axis_tready : in STD_LOGIC; + m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axis_tlast : out STD_LOGIC; + m_axis_tuser : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + +end Arty_Z7_20_axis_subset_converter_0_1; + +architecture stub of Arty_Z7_20_axis_subset_converter_0_1 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[23:0],s_axis_tlast,s_axis_tuser[0:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[7:0],m_axis_tlast,m_axis_tuser[0:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "top_Arty_Z7_20_axis_subset_converter_0_1,Vivado 2016.4"; +begin +end; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/hdl/tdata_Arty_Z7_20_axis_subset_converter_0_1.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/hdl/tdata_Arty_Z7_20_axis_subset_converter_0_1.v new file mode 100644 index 0000000..e50dde4 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/hdl/tdata_Arty_Z7_20_axis_subset_converter_0_1.v @@ -0,0 +1,70 @@ + +//***************************************************************************** +// (c) Copyright 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. + +`timescale 1ps/1ps + +module tdata_Arty_Z7_20_axis_subset_converter_0_1 # +( +parameter C_S_AXIS_TDATA_WIDTH = 32, +parameter C_S_AXIS_TUSER_WIDTH = 0, +parameter C_S_AXIS_TID_WIDTH = 0, +parameter C_S_AXIS_TDEST_WIDTH = 0, +parameter C_M_AXIS_TDATA_WIDTH = 32 +) +( +input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDATA_WIDTH)-1:0 ] tdata, +input [(C_S_AXIS_TUSER_WIDTH == 0 ? 1 : C_S_AXIS_TUSER_WIDTH)-1:0 ] tuser, +input [(C_S_AXIS_TID_WIDTH == 0 ? 1 : C_S_AXIS_TID_WIDTH)-1:0 ] tid, +input [(C_S_AXIS_TDEST_WIDTH == 0 ? 1 : C_S_AXIS_TDEST_WIDTH)-1:0 ] tdest, +input [(C_S_AXIS_TDATA_WIDTH/8)-1:0 ] tkeep, +input [(C_S_AXIS_TDATA_WIDTH/8)-1:0 ] tstrb, +input tlast, +output [C_M_AXIS_TDATA_WIDTH-1:0] tdata_out +); + +assign tdata_out = {tdata[7:0]}; + +endmodule + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/hdl/tdest_Arty_Z7_20_axis_subset_converter_0_1.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/hdl/tdest_Arty_Z7_20_axis_subset_converter_0_1.v new file mode 100644 index 0000000..4169e3d --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/hdl/tdest_Arty_Z7_20_axis_subset_converter_0_1.v @@ -0,0 +1,70 @@ + +//***************************************************************************** +// (c) Copyright 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. + +`timescale 1ps/1ps + +module tdest_Arty_Z7_20_axis_subset_converter_0_1 # +( +parameter C_S_AXIS_TDATA_WIDTH = 32, +parameter C_S_AXIS_TUSER_WIDTH = 0, +parameter C_S_AXIS_TID_WIDTH = 0, +parameter C_S_AXIS_TDEST_WIDTH = 0, +parameter C_M_AXIS_TDEST_WIDTH = 32 +) +( +input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDATA_WIDTH)-1:0 ] tdata, +input [(C_S_AXIS_TUSER_WIDTH == 0 ? 1 : C_S_AXIS_TUSER_WIDTH)-1:0 ] tuser, +input [(C_S_AXIS_TID_WIDTH == 0 ? 1 : C_S_AXIS_TID_WIDTH)-1:0 ] tid, +input [(C_S_AXIS_TDEST_WIDTH == 0 ? 1 : C_S_AXIS_TDEST_WIDTH)-1:0 ] tdest, +input [(C_S_AXIS_TDATA_WIDTH/8)-1:0 ] tkeep, +input [(C_S_AXIS_TDATA_WIDTH/8)-1:0 ] tstrb, +input tlast, +output [C_M_AXIS_TDEST_WIDTH-1:0] tdest_out +); + +assign tdest_out = {1'b0}; + +endmodule + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/hdl/tid_Arty_Z7_20_axis_subset_converter_0_1.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/hdl/tid_Arty_Z7_20_axis_subset_converter_0_1.v new file mode 100644 index 0000000..55f8881 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/hdl/tid_Arty_Z7_20_axis_subset_converter_0_1.v @@ -0,0 +1,70 @@ + +//***************************************************************************** +// (c) Copyright 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. + +`timescale 1ps/1ps + +module tid_Arty_Z7_20_axis_subset_converter_0_1 # +( +parameter C_S_AXIS_TID_WIDTH = 1, +parameter C_S_AXIS_TUSER_WIDTH = 0, +parameter C_S_AXIS_TDATA_WIDTH = 0, +parameter C_S_AXIS_TDEST_WIDTH = 0, +parameter C_M_AXIS_TID_WIDTH = 32 +) +( +input [(C_S_AXIS_TID_WIDTH == 0 ? 1 : C_S_AXIS_TID_WIDTH)-1:0 ] tid, +input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDATA_WIDTH)-1:0 ] tdata, +input [(C_S_AXIS_TUSER_WIDTH == 0 ? 1 : C_S_AXIS_TUSER_WIDTH)-1:0 ] tuser, +input [(C_S_AXIS_TDEST_WIDTH == 0 ? 1 : C_S_AXIS_TDEST_WIDTH)-1:0 ] tdest, +input [(C_S_AXIS_TDATA_WIDTH/8)-1:0 ] tkeep, +input [(C_S_AXIS_TDATA_WIDTH/8)-1:0 ] tstrb, +input tlast, +output [(C_M_AXIS_TID_WIDTH == 0 ? 1 : C_M_AXIS_TID_WIDTH)-1:0 ] tid_out +); + +assign tid_out = {1'b0}; + +endmodule + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/hdl/tkeep_Arty_Z7_20_axis_subset_converter_0_1.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/hdl/tkeep_Arty_Z7_20_axis_subset_converter_0_1.v new file mode 100644 index 0000000..926feeb --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/hdl/tkeep_Arty_Z7_20_axis_subset_converter_0_1.v @@ -0,0 +1,70 @@ + +//***************************************************************************** +// (c) Copyright 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. + +`timescale 1ps/1ps + +module tkeep_Arty_Z7_20_axis_subset_converter_0_1 # +( +parameter C_S_AXIS_TDATA_WIDTH = 32, +parameter C_S_AXIS_TUSER_WIDTH = 0, +parameter C_S_AXIS_TID_WIDTH = 0, +parameter C_S_AXIS_TDEST_WIDTH = 0, +parameter C_M_AXIS_TDATA_WIDTH = 32 +) +( +input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDATA_WIDTH)-1:0 ] tdata, +input [(C_S_AXIS_TUSER_WIDTH == 0 ? 1 : C_S_AXIS_TUSER_WIDTH)-1:0 ] tuser, +input [(C_S_AXIS_TID_WIDTH == 0 ? 1 : C_S_AXIS_TID_WIDTH)-1:0 ] tid, +input [(C_S_AXIS_TDEST_WIDTH == 0 ? 1 : C_S_AXIS_TDEST_WIDTH)-1:0 ] tdest, +input [(C_S_AXIS_TDATA_WIDTH/8)-1:0 ] tkeep, +input [(C_S_AXIS_TDATA_WIDTH/8)-1:0 ] tstrb, +input tlast, +output [(C_M_AXIS_TDATA_WIDTH/8)-1:0 ] tkeep_out +); + +assign tkeep_out = {1'b0}; + +endmodule + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/hdl/tlast_Arty_Z7_20_axis_subset_converter_0_1.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/hdl/tlast_Arty_Z7_20_axis_subset_converter_0_1.v new file mode 100644 index 0000000..1d0841d --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/hdl/tlast_Arty_Z7_20_axis_subset_converter_0_1.v @@ -0,0 +1,69 @@ + +//***************************************************************************** +// (c) Copyright 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. + +`timescale 1ps/1ps + +module tlast_Arty_Z7_20_axis_subset_converter_0_1 # +( +parameter C_S_AXIS_TID_WIDTH = 1, +parameter C_S_AXIS_TUSER_WIDTH = 0, +parameter C_S_AXIS_TDATA_WIDTH = 0, +parameter C_S_AXIS_TDEST_WIDTH = 0 +) +( +input [(C_S_AXIS_TID_WIDTH == 0 ? 1 : C_S_AXIS_TID_WIDTH)-1:0 ] tid, +input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDATA_WIDTH)-1:0 ] tdata, +input [(C_S_AXIS_TUSER_WIDTH == 0 ? 1 : C_S_AXIS_TUSER_WIDTH)-1:0 ] tuser, +input [(C_S_AXIS_TDEST_WIDTH == 0 ? 1 : C_S_AXIS_TDEST_WIDTH)-1:0 ] tdest, +input [(C_S_AXIS_TDATA_WIDTH/8)-1:0 ] tkeep, +input [(C_S_AXIS_TDATA_WIDTH/8)-1:0 ] tstrb, +input [0:0] tlast, +output tlast_out +); + +assign tlast_out = {tlast[0]}; + +endmodule + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/hdl/top_Arty_Z7_20_axis_subset_converter_0_1.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/hdl/top_Arty_Z7_20_axis_subset_converter_0_1.v new file mode 100644 index 0000000..737ae4b --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/hdl/top_Arty_Z7_20_axis_subset_converter_0_1.v @@ -0,0 +1,306 @@ + +// -- (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved. +// -- +// -- This file contains confidential and proprietary information +// -- of Xilinx, Inc. and is protected under U.S. and +// -- international copyright and other intellectual property +// -- laws. +// -- +// -- DISCLAIMER +// -- This disclaimer is not a license and does not grant any +// -- rights to the materials distributed herewith. Except as +// -- otherwise provided in a valid license issued to you by +// -- Xilinx, and to the maximum extent permitted by applicable +// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// -- (2) Xilinx shall not be liable (whether in contract or tort, +// -- including negligence, or under any other theory of +// -- liability) for any loss or damage of any kind or nature +// -- related to, arising under or in connection with these +// -- materials, including for any direct, or any indirect, +// -- special, incidental, or consequential loss or damage +// -- (including loss of data, profits, goodwill, or any type of +// -- loss or damage suffered as a result of any action brought +// -- by a third party) even if such damage or loss was +// -- reasonably foreseeable or Xilinx had been advised of the +// -- possibility of the same. +// -- +// -- CRITICAL APPLICATIONS +// -- Xilinx products are not designed or intended to be fail- +// -- safe, or for use in any application requiring fail-safe +// -- performance, such as life-support or safety devices or +// -- systems, Class III medical devices, nuclear facilities, +// -- applications related to the deployment of airbags, or any +// -- other applications that could lead to death, personal +// -- injury, or severe property or environmental damage +// -- (individually and collectively, "Critical +// -- Applications"). Customer assumes the sole risk and +// -- liability of any use of Xilinx products in Critical +// -- Applications, subject only to applicable laws and +// -- regulations governing limitations on product liability. +// -- +// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// -- PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// axis_subset_converter +// Converts signal sets and id/dest dwidth based on default tie off rules. +// Remap capability allows subset of TDATA and TUSER signals to be transfered +// from SI to MI. +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- + +`timescale 1ps/1ps +`default_nettype none + +module top_Arty_Z7_20_axis_subset_converter_0_1 # +( +/////////////////////////////////////////////////////////////////////////////// +// Parameter Definitions +/////////////////////////////////////////////////////////////////////////////// +parameter C_FAMILY = "virtex7", +parameter integer C_S_AXIS_TDATA_WIDTH = 32, +parameter integer C_S_AXIS_TID_WIDTH = 1, +parameter integer C_S_AXIS_TDEST_WIDTH = 1, +parameter integer C_S_AXIS_TUSER_WIDTH = 1, +parameter [31:0] C_S_AXIS_SIGNAL_SET = 32'hFF, +// C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present +// [0] => TREADY present (Required) +// [1] => TDATA present (Required, used to calculate ratios) +// [2] => TSTRB present, TDATA must be present +// [3] => TKEEP present, TDATA must be present (Required if TLAST, TID, +// TDEST present +// [4] => TLAST present +// [5] => TID present +// [6] => TDEST present +// [7] => TUSER present +parameter integer C_M_AXIS_TDATA_WIDTH = 32, +parameter integer C_M_AXIS_TID_WIDTH = 1, +parameter integer C_M_AXIS_TDEST_WIDTH = 1, +parameter [31:0] C_M_AXIS_SIGNAL_SET = 32'hFF, +parameter integer C_M_AXIS_TUSER_WIDTH = 1, +parameter integer C_DEFAULT_TLAST = 0 +) +( +/////////////////////////////////////////////////////////////////////////////// +// Port Declarations +/////////////////////////////////////////////////////////////////////////////// +// System Signals +input wire aclk, +input wire aresetn, +input wire aclken, + +// Slave side +input wire s_axis_tvalid, +output wire s_axis_tready, +input wire [C_S_AXIS_TDATA_WIDTH-1:0] s_axis_tdata, +input wire [C_S_AXIS_TDATA_WIDTH/8-1:0] s_axis_tstrb, +input wire [C_S_AXIS_TDATA_WIDTH/8-1:0] s_axis_tkeep, +input wire s_axis_tlast, +input wire [C_S_AXIS_TID_WIDTH-1:0] s_axis_tid, +input wire [C_S_AXIS_TDEST_WIDTH-1:0] s_axis_tdest, +input wire [C_S_AXIS_TUSER_WIDTH-1:0] s_axis_tuser, + +// Master side +output wire m_axis_tvalid, +input wire m_axis_tready, +output wire [C_M_AXIS_TDATA_WIDTH-1:0] m_axis_tdata, +output wire [C_M_AXIS_TDATA_WIDTH/8-1:0] m_axis_tstrb, +output wire [C_M_AXIS_TDATA_WIDTH/8-1:0] m_axis_tkeep, +output wire m_axis_tlast, +output wire [C_M_AXIS_TID_WIDTH-1:0] m_axis_tid, +output wire [C_M_AXIS_TDEST_WIDTH-1:0] m_axis_tdest, +output wire [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_tuser, + +// Status Signals +output wire transfer_dropped, +output wire sparse_tkeep_removed +// SPARSE_TKEEP_REMOVED outputs a 1 if TKEEP is being removed and +// a conversion process detects a TKEEP that is not all HIGH +); + +`include "axis_infrastructure_v1_1_0.vh" + +wire [C_S_AXIS_TDATA_WIDTH-1:0] m_axis_tdata_i; +wire [C_S_AXIS_TUSER_WIDTH-1:0] m_axis_tuser_i; +wire [C_S_AXIS_TID_WIDTH-1:0] m_axis_tid_i; +wire [C_S_AXIS_TDEST_WIDTH-1:0] m_axis_tdest_i; +wire [C_S_AXIS_TDATA_WIDTH/8-1:0] m_axis_tkeep_i; +wire [C_S_AXIS_TDATA_WIDTH/8-1:0] m_axis_tstrb_i; +wire m_axis_tlast_i; + +axis_subset_converter_v1_1_11_core #( +.C_FAMILY ( C_FAMILY ), +.C_AXIS_TDATA_WIDTH ( C_S_AXIS_TDATA_WIDTH ), +.C_S_AXIS_TID_WIDTH ( C_S_AXIS_TID_WIDTH ), +.C_M_AXIS_TID_WIDTH ( C_S_AXIS_TID_WIDTH ), +.C_S_AXIS_TDEST_WIDTH ( C_S_AXIS_TDEST_WIDTH ), +.C_M_AXIS_TDEST_WIDTH ( C_S_AXIS_TDEST_WIDTH ), +.C_AXIS_TUSER_WIDTH ( C_S_AXIS_TUSER_WIDTH ), +.C_S_AXIS_SIGNAL_SET ( C_S_AXIS_SIGNAL_SET ), +.C_M_AXIS_SIGNAL_SET ( C_M_AXIS_SIGNAL_SET ), +.C_DEFAULT_TLAST ( C_DEFAULT_TLAST ) +) +axis_subset_converter_v1_1_11_core ( +.aclk (aclk ), +.aresetn (aresetn ), +.aclken (aclken ), +.s_axis_tvalid (s_axis_tvalid ), +.s_axis_tready (s_axis_tready ), +.s_axis_tdata (s_axis_tdata ), +.s_axis_tstrb (s_axis_tstrb ), +.s_axis_tkeep (s_axis_tkeep ), +.s_axis_tlast (s_axis_tlast ), +.s_axis_tid (s_axis_tid ), +.s_axis_tdest (s_axis_tdest ), +.s_axis_tuser (s_axis_tuser ), +.m_axis_tvalid (m_axis_tvalid ), +.m_axis_tready (m_axis_tready ), +.m_axis_tdata (m_axis_tdata_i ), +.m_axis_tstrb (m_axis_tstrb_i ), +.m_axis_tkeep (m_axis_tkeep_i ), +.m_axis_tlast (m_axis_tlast_i ), +.m_axis_tid (m_axis_tid_i ), +.m_axis_tdest (m_axis_tdest_i ), +.m_axis_tuser (m_axis_tuser_i ), +.transfer_dropped (transfer_dropped ), +.sparse_tkeep_removed (sparse_tkeep_removed ) +); + +tdata_Arty_Z7_20_axis_subset_converter_0_1 #( +.C_S_AXIS_TDATA_WIDTH ( C_S_AXIS_TDATA_WIDTH ) , +.C_S_AXIS_TUSER_WIDTH ( C_S_AXIS_TUSER_WIDTH ) , +.C_S_AXIS_TID_WIDTH ( C_S_AXIS_TID_WIDTH ) , +.C_S_AXIS_TDEST_WIDTH ( C_S_AXIS_TDEST_WIDTH ) , +.C_M_AXIS_TDATA_WIDTH ( C_M_AXIS_TDATA_WIDTH ) +) +tdata0 ( +.tdata ( m_axis_tdata_i ), +.tuser ( m_axis_tuser_i ), +.tid ( m_axis_tid_i [C_S_AXIS_TID_WIDTH-1:0 ] ), +.tdest ( m_axis_tdest_i[C_S_AXIS_TDEST_WIDTH-1:0 ] ), +.tstrb ( m_axis_tstrb_i ), +.tkeep ( m_axis_tkeep_i ), +.tlast ( m_axis_tlast_i ), +.tdata_out ( m_axis_tdata ) +); + +tuser_Arty_Z7_20_axis_subset_converter_0_1 #( +.C_S_AXIS_TDATA_WIDTH ( C_S_AXIS_TDATA_WIDTH ) , +.C_S_AXIS_TUSER_WIDTH ( C_S_AXIS_TUSER_WIDTH ) , +.C_S_AXIS_TID_WIDTH ( C_S_AXIS_TID_WIDTH ) , +.C_S_AXIS_TDEST_WIDTH ( C_S_AXIS_TDEST_WIDTH ) , +.C_M_AXIS_TUSER_WIDTH ( C_M_AXIS_TUSER_WIDTH ) +) +tuser0 ( +.tdata ( m_axis_tdata_i ), +.tuser ( m_axis_tuser_i ), +.tid ( m_axis_tid_i [C_S_AXIS_TID_WIDTH-1:0 ] ), +.tdest ( m_axis_tdest_i[C_S_AXIS_TDEST_WIDTH-1:0 ] ), +.tstrb ( m_axis_tstrb_i ), +.tkeep ( m_axis_tkeep_i ), +.tlast ( m_axis_tlast_i ), +.tuser_out ( m_axis_tuser ) +); + +tid_Arty_Z7_20_axis_subset_converter_0_1 #( +.C_S_AXIS_TDATA_WIDTH ( C_S_AXIS_TDATA_WIDTH ) , +.C_S_AXIS_TUSER_WIDTH ( C_S_AXIS_TUSER_WIDTH ) , +.C_S_AXIS_TID_WIDTH ( C_S_AXIS_TID_WIDTH ) , +.C_S_AXIS_TDEST_WIDTH ( C_S_AXIS_TDEST_WIDTH ) , +.C_M_AXIS_TID_WIDTH ( C_M_AXIS_TID_WIDTH ) +) +tid0 ( +.tdata ( m_axis_tdata_i ), +.tuser ( m_axis_tuser_i ), +.tid ( m_axis_tid_i [C_S_AXIS_TID_WIDTH-1:0 ] ), +.tdest ( m_axis_tdest_i[C_S_AXIS_TDEST_WIDTH-1:0 ] ), +.tstrb ( m_axis_tstrb_i ), +.tkeep ( m_axis_tkeep_i ), +.tlast ( m_axis_tlast_i ), +.tid_out ( m_axis_tid ) +); + +tdest_Arty_Z7_20_axis_subset_converter_0_1 #( +.C_S_AXIS_TDATA_WIDTH ( C_S_AXIS_TDATA_WIDTH ) , +.C_S_AXIS_TUSER_WIDTH ( C_S_AXIS_TUSER_WIDTH ) , +.C_S_AXIS_TID_WIDTH ( C_S_AXIS_TID_WIDTH ) , +.C_S_AXIS_TDEST_WIDTH ( C_S_AXIS_TDEST_WIDTH ) , +.C_M_AXIS_TDEST_WIDTH ( C_M_AXIS_TDEST_WIDTH ) +) +tdest0 ( +.tdata ( m_axis_tdata_i ), +.tuser ( m_axis_tuser_i ), +.tid ( m_axis_tid_i [C_S_AXIS_TID_WIDTH-1:0 ] ), +.tdest ( m_axis_tdest_i[C_S_AXIS_TDEST_WIDTH-1:0 ] ), +.tstrb ( m_axis_tstrb_i ), +.tkeep ( m_axis_tkeep_i ), +.tlast ( m_axis_tlast_i ), +.tdest_out ( m_axis_tdest ) +); + +wire [(C_S_AXIS_TDATA_WIDTH/8)-1:0] m_axis_tkeep_shunt; +assign m_axis_tkeep_shunt = (C_S_AXIS_SIGNAL_SET[G_INDX_SS_TKEEP] && !C_S_AXIS_SIGNAL_SET[G_INDX_SS_TSTRB] && C_M_AXIS_SIGNAL_SET[G_INDX_SS_TSTRB]) ? m_axis_tstrb_i : m_axis_tkeep_i; + +tstrb_Arty_Z7_20_axis_subset_converter_0_1 #( +.C_S_AXIS_TDATA_WIDTH ( C_S_AXIS_TDATA_WIDTH ) , +.C_S_AXIS_TUSER_WIDTH ( C_S_AXIS_TUSER_WIDTH ) , +.C_S_AXIS_TID_WIDTH ( C_S_AXIS_TID_WIDTH ) , +.C_S_AXIS_TDEST_WIDTH ( C_S_AXIS_TDEST_WIDTH ) , +.C_M_AXIS_TDATA_WIDTH ( C_M_AXIS_TDATA_WIDTH ) +) +tstrb0 ( +.tdata ( m_axis_tdata_i ), +.tuser ( m_axis_tuser_i ), +.tid ( m_axis_tid_i [C_S_AXIS_TID_WIDTH-1:0 ] ), +.tdest ( m_axis_tdest_i[C_S_AXIS_TDEST_WIDTH-1:0 ] ), +.tstrb ( m_axis_tstrb_i ), +.tkeep ( m_axis_tkeep_shunt ), +.tlast ( m_axis_tlast_i ), +.tstrb_out ( m_axis_tstrb ) +); + + +tkeep_Arty_Z7_20_axis_subset_converter_0_1 #( +.C_S_AXIS_TDATA_WIDTH ( C_S_AXIS_TDATA_WIDTH ) , +.C_S_AXIS_TUSER_WIDTH ( C_S_AXIS_TUSER_WIDTH ) , +.C_S_AXIS_TID_WIDTH ( C_S_AXIS_TID_WIDTH ) , +.C_S_AXIS_TDEST_WIDTH ( C_S_AXIS_TDEST_WIDTH ) , +.C_M_AXIS_TDATA_WIDTH ( C_M_AXIS_TDATA_WIDTH ) +) +tkeep0 ( +.tdata ( m_axis_tdata_i ), +.tuser ( m_axis_tuser_i ), +.tid ( m_axis_tid_i [C_S_AXIS_TID_WIDTH-1:0 ] ), +.tdest ( m_axis_tdest_i[C_S_AXIS_TDEST_WIDTH-1:0 ] ), +.tstrb ( m_axis_tstrb_i ), +.tkeep ( m_axis_tkeep_i ), +.tlast ( m_axis_tlast_i ), +.tkeep_out ( m_axis_tkeep ) +); + +tlast_Arty_Z7_20_axis_subset_converter_0_1 #( +.C_S_AXIS_TDATA_WIDTH ( C_S_AXIS_TDATA_WIDTH ) , +.C_S_AXIS_TUSER_WIDTH ( C_S_AXIS_TUSER_WIDTH ) , +.C_S_AXIS_TID_WIDTH ( C_S_AXIS_TID_WIDTH ) , +.C_S_AXIS_TDEST_WIDTH ( C_S_AXIS_TDEST_WIDTH ) +) +tlast0 ( +.tdata ( m_axis_tdata_i ), +.tuser ( m_axis_tuser_i ), +.tid ( m_axis_tid_i [C_S_AXIS_TID_WIDTH-1:0 ] ), +.tdest ( m_axis_tdest_i[C_S_AXIS_TDEST_WIDTH-1:0 ] ), +.tstrb ( m_axis_tstrb_i ), +.tkeep ( m_axis_tkeep_i ), +.tlast ( m_axis_tlast_i ), +.tlast_out ( m_axis_tlast ) +); + +endmodule // axis_subset_converter + +`default_nettype wire + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/hdl/tstrb_Arty_Z7_20_axis_subset_converter_0_1.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/hdl/tstrb_Arty_Z7_20_axis_subset_converter_0_1.v new file mode 100644 index 0000000..8a95027 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/hdl/tstrb_Arty_Z7_20_axis_subset_converter_0_1.v @@ -0,0 +1,70 @@ + +//***************************************************************************** +// (c) Copyright 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. + +`timescale 1ps/1ps + +module tstrb_Arty_Z7_20_axis_subset_converter_0_1 # +( +parameter C_S_AXIS_TDATA_WIDTH = 32, +parameter C_S_AXIS_TUSER_WIDTH = 0, +parameter C_S_AXIS_TID_WIDTH = 0, +parameter C_S_AXIS_TDEST_WIDTH = 0, +parameter C_M_AXIS_TDATA_WIDTH = 32 +) +( +input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDATA_WIDTH)-1:0 ] tdata, +input [(C_S_AXIS_TUSER_WIDTH == 0 ? 1 : C_S_AXIS_TUSER_WIDTH)-1:0 ] tuser, +input [(C_S_AXIS_TID_WIDTH == 0 ? 1 : C_S_AXIS_TID_WIDTH)-1:0 ] tid, +input [(C_S_AXIS_TDEST_WIDTH == 0 ? 1 : C_S_AXIS_TDEST_WIDTH)-1:0 ] tdest, +input [(C_S_AXIS_TDATA_WIDTH/8)-1:0 ] tkeep, +input [(C_S_AXIS_TDATA_WIDTH/8)-1:0 ] tstrb, +input tlast, +output [(C_M_AXIS_TDATA_WIDTH/8)-1:0 ] tstrb_out +); + +assign tstrb_out = {1'b0}; + +endmodule + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/hdl/tuser_Arty_Z7_20_axis_subset_converter_0_1.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/hdl/tuser_Arty_Z7_20_axis_subset_converter_0_1.v new file mode 100644 index 0000000..5db4ede --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/hdl/tuser_Arty_Z7_20_axis_subset_converter_0_1.v @@ -0,0 +1,70 @@ + +//***************************************************************************** +// (c) Copyright 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. + +`timescale 1ps/1ps + +module tuser_Arty_Z7_20_axis_subset_converter_0_1 # +( +parameter C_S_AXIS_TUSER_WIDTH = 1, +parameter C_S_AXIS_TDATA_WIDTH = 32, +parameter C_S_AXIS_TID_WIDTH = 0, +parameter C_S_AXIS_TDEST_WIDTH = 0, +parameter C_M_AXIS_TUSER_WIDTH = 1 +) +( +input [(C_S_AXIS_TUSER_WIDTH == 0 ? 1 : C_S_AXIS_TUSER_WIDTH)-1:0 ] tuser, +input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDATA_WIDTH)-1:0 ] tdata, +input [(C_S_AXIS_TID_WIDTH == 0 ? 1 : C_S_AXIS_TID_WIDTH)-1:0 ] tid, +input [(C_S_AXIS_TDEST_WIDTH == 0 ? 1 : C_S_AXIS_TDEST_WIDTH)-1:0 ] tdest, +input [(C_S_AXIS_TDATA_WIDTH/8)-1:0 ] tkeep, +input [(C_S_AXIS_TDATA_WIDTH/8)-1:0 ] tstrb, +input tlast, +output [C_M_AXIS_TUSER_WIDTH-1:0] tuser_out +); + +assign tuser_out = {tuser[0:0]}; + +endmodule + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/sim/Arty_Z7_20_axis_subset_converter_0_1.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/sim/Arty_Z7_20_axis_subset_converter_0_1.v new file mode 100644 index 0000000..5ccabb1 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/sim/Arty_Z7_20_axis_subset_converter_0_1.v @@ -0,0 +1,134 @@ +// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:axis_subset_converter:1.1 +// IP Revision: 11 + +`timescale 1ns/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module Arty_Z7_20_axis_subset_converter_0_1 ( + aclk, + aresetn, + s_axis_tvalid, + s_axis_tready, + s_axis_tdata, + s_axis_tlast, + s_axis_tuser, + m_axis_tvalid, + m_axis_tready, + m_axis_tdata, + m_axis_tlast, + m_axis_tuser +); + +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) +input wire aclk; +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) +input wire aresetn; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) +input wire s_axis_tvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) +output wire s_axis_tready; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) +input wire [23 : 0] s_axis_tdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *) +input wire s_axis_tlast; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TUSER" *) +input wire [0 : 0] s_axis_tuser; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *) +output wire m_axis_tvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *) +input wire m_axis_tready; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *) +output wire [7 : 0] m_axis_tdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *) +output wire m_axis_tlast; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TUSER" *) +output wire [0 : 0] m_axis_tuser; + + top_Arty_Z7_20_axis_subset_converter_0_1 #( + .C_FAMILY("zynq"), + .C_S_AXIS_TDATA_WIDTH(24), + .C_S_AXIS_TID_WIDTH(1), + .C_S_AXIS_TDEST_WIDTH(1), + .C_S_AXIS_TUSER_WIDTH(1), + .C_S_AXIS_SIGNAL_SET('B00000000000000000000000010010011), + .C_M_AXIS_TDATA_WIDTH(8), + .C_M_AXIS_TID_WIDTH(1), + .C_M_AXIS_TDEST_WIDTH(1), + .C_M_AXIS_SIGNAL_SET('B00000000000000000000000010010011), + .C_M_AXIS_TUSER_WIDTH(1), + .C_DEFAULT_TLAST(0) + ) inst ( + .aclk(aclk), + .aresetn(aresetn), + .aclken(1'H1), + .s_axis_tvalid(s_axis_tvalid), + .s_axis_tready(s_axis_tready), + .s_axis_tdata(s_axis_tdata), + .s_axis_tstrb(3'H7), + .s_axis_tkeep(3'H7), + .s_axis_tlast(s_axis_tlast), + .s_axis_tid(1'H0), + .s_axis_tdest(1'H0), + .s_axis_tuser(s_axis_tuser), + .m_axis_tvalid(m_axis_tvalid), + .m_axis_tready(m_axis_tready), + .m_axis_tdata(m_axis_tdata), + .m_axis_tstrb(), + .m_axis_tkeep(), + .m_axis_tlast(m_axis_tlast), + .m_axis_tid(), + .m_axis_tdest(), + .m_axis_tuser(m_axis_tuser), + .transfer_dropped(), + .sparse_tkeep_removed() + ); +endmodule diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/synth/Arty_Z7_20_axis_subset_converter_0_1.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/synth/Arty_Z7_20_axis_subset_converter_0_1.v new file mode 100644 index 0000000..1bbec89 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_axis_subset_converter_0_1/synth/Arty_Z7_20_axis_subset_converter_0_1.v @@ -0,0 +1,136 @@ +// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:axis_subset_converter:1.1 +// IP Revision: 11 + +(* X_CORE_INFO = "top_Arty_Z7_20_axis_subset_converter_0_1,Vivado 2016.4" *) +(* CHECK_LICENSE_TYPE = "Arty_Z7_20_axis_subset_converter_0_1,top_Arty_Z7_20_axis_subset_converter_0_1,{}" *) +(* CORE_GENERATION_INFO = "Arty_Z7_20_axis_subset_converter_0_1,top_Arty_Z7_20_axis_subset_converter_0_1,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axis_subset_converter,x_ipVersion=1.1,x_ipCoreRevision=11,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXIS_TDATA_WIDTH=24,C_S_AXIS_TID_WIDTH=1,C_S_AXIS_TDEST_WIDTH=1,C_S_AXIS_TUSER_WIDTH=1,C_S_AXIS_SIGNAL_SET=0b00000000000000000000000010010011,C_M_AXIS_TDATA_WIDTH=8,C_M_AXIS_TID_WIDTH=1,C_M_AXIS_TDEST_WIDTH=1,C_M_AXIS_SIGNAL_SET=0b00\ +000000000000000000000010010011,C_M_AXIS_TUSER_WIDTH=1,C_DEFAULT_TLAST=0}" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module Arty_Z7_20_axis_subset_converter_0_1 ( + aclk, + aresetn, + s_axis_tvalid, + s_axis_tready, + s_axis_tdata, + s_axis_tlast, + s_axis_tuser, + m_axis_tvalid, + m_axis_tready, + m_axis_tdata, + m_axis_tlast, + m_axis_tuser +); + +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) +input wire aclk; +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) +input wire aresetn; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) +input wire s_axis_tvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) +output wire s_axis_tready; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) +input wire [23 : 0] s_axis_tdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *) +input wire s_axis_tlast; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TUSER" *) +input wire [0 : 0] s_axis_tuser; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *) +output wire m_axis_tvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *) +input wire m_axis_tready; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *) +output wire [7 : 0] m_axis_tdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *) +output wire m_axis_tlast; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TUSER" *) +output wire [0 : 0] m_axis_tuser; + + top_Arty_Z7_20_axis_subset_converter_0_1 #( + .C_FAMILY("zynq"), + .C_S_AXIS_TDATA_WIDTH(24), + .C_S_AXIS_TID_WIDTH(1), + .C_S_AXIS_TDEST_WIDTH(1), + .C_S_AXIS_TUSER_WIDTH(1), + .C_S_AXIS_SIGNAL_SET('B00000000000000000000000010010011), + .C_M_AXIS_TDATA_WIDTH(8), + .C_M_AXIS_TID_WIDTH(1), + .C_M_AXIS_TDEST_WIDTH(1), + .C_M_AXIS_SIGNAL_SET('B00000000000000000000000010010011), + .C_M_AXIS_TUSER_WIDTH(1), + .C_DEFAULT_TLAST(0) + ) inst ( + .aclk(aclk), + .aresetn(aresetn), + .aclken(1'H1), + .s_axis_tvalid(s_axis_tvalid), + .s_axis_tready(s_axis_tready), + .s_axis_tdata(s_axis_tdata), + .s_axis_tstrb(3'H7), + .s_axis_tkeep(3'H7), + .s_axis_tlast(s_axis_tlast), + .s_axis_tid(1'H0), + .s_axis_tdest(1'H0), + .s_axis_tuser(s_axis_tuser), + .m_axis_tvalid(m_axis_tvalid), + .m_axis_tready(m_axis_tready), + .m_axis_tdata(m_axis_tdata), + .m_axis_tstrb(), + .m_axis_tkeep(), + .m_axis_tlast(m_axis_tlast), + .m_axis_tid(), + .m_axis_tdest(), + .m_axis_tuser(m_axis_tuser), + .transfer_dropped(), + .sparse_tkeep_removed() + ); +endmodule diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0.dcp b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0.dcp index cc961d9..8d78e5f 100644 Binary files a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0.dcp and b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0.dcp differ diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0.v index 8f27468..dafe0cc 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0.v @@ -57,6 +57,7 @@ // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) //---------------------------------------------------------------------------- // clk_out1___125.000______0.000______50.0______119.348_____96.948 +// clk_out2___200.000______0.000______50.0______109.241_____96.948 // //---------------------------------------------------------------------------- // Input Clock Freq (MHz) Input Jitter (UI) @@ -65,13 +66,15 @@ `timescale 1ps/1ps -(* CORE_GENERATION_INFO = "Arty_Z7_20_clk_wiz_0_0,clk_wiz_v5_3_3_0,{component_name=Arty_Z7_20_clk_wiz_0_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=8.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) +(* CORE_GENERATION_INFO = "Arty_Z7_20_clk_wiz_0_0,clk_wiz_v5_3_3_0,{component_name=Arty_Z7_20_clk_wiz_0_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=2,clkin1_period=8.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) module Arty_Z7_20_clk_wiz_0_0 ( // Clock out ports output clk_out1, + output clk_out2, // Status and control signals + input reset, output locked, // Clock in ports input clk_in1 @@ -81,7 +84,9 @@ module Arty_Z7_20_clk_wiz_0_0 ( // Clock out ports .clk_out1(clk_out1), + .clk_out2(clk_out2), // Status and control signals + .reset(reset), .locked(locked), // Clock in ports .clk_in1(clk_in1) diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0.xci b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0.xci index ce0ee81..67ec634 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0.xci +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0.xci @@ -9,6 +9,8 @@ Arty_Z7_20_clk_wiz_0_0 + + Arty_Z7_20_sys_clock 125000000 0.000 @@ -17,6 +19,11 @@ /clk_wiz_0_clk_out1 125000000 0.0 + + + /clk_wiz_0_clk_out1 + 200000000 + 0.0 MMCM cddcdone cddcreq @@ -35,9 +42,9 @@ 1104 0000 125.000 - 1041 - 00c0 - 100.000 + 1083 + 0080 + 200.000 BUFG 50.0 false @@ -51,15 +58,15 @@ 00c0 100.000 BUFG - 50.000 + 50.0 false - 100.000 + 200.000 0.000 50.000 - 100.000 + 200 0.000 1 - 0 + 1 1041 00c0 100.000 @@ -139,7 +146,7 @@ din 1041 1 - 1.25 + 0.625 1.25 1.25 1.25 @@ -189,7 +196,7 @@ 0.500 0.000 FALSE - 1 + 5 0.500 0.000 FALSE @@ -221,11 +228,11 @@ 0.010 0.010 FALSE - 1 + 2 Output Output Phase Duty Cycle Pk-to-Pk Phase Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) clk_out1___125.000______0.000______50.0______119.348_____96.948 - no_CLK_OUT2_output + clk_out2___200.000______0.000______50.0______109.241_____96.948 no_CLK_OUT3_output no_CLK_OUT4_output no_CLK_OUT5_output @@ -271,7 +278,7 @@ FFFF 1 clk_in1 - MMCM + PLL AUTO 125.000 0.010 @@ -319,7 +326,7 @@ 0 1 0 - 0 + 1 0 0 0 @@ -351,14 +358,14 @@ 1 true BUFG - 0.0 + 109.241 false - 0.0 + 96.948 50.000 - 100.000 + 200 0.000 1 - false + true BUFG 0.0 false @@ -453,16 +460,16 @@ No_Jitter locked OPTIMIZED - 8.000 + 8 0.000 false 8.0 10.0 - 8.000 + 8 0.500 0.000 false - 1 + 5 0.500 0.000 false @@ -494,7 +501,7 @@ 0.010 0.010 false - 1 + 2 false false WAVEFORM @@ -530,7 +537,7 @@ power_down 1 clk_in1 - MMCM + PLL mmcm_adv 125.000 0.010 @@ -575,7 +582,7 @@ false true false - false + true false false false @@ -590,6 +597,7 @@ TRUE TRUE + a8a3fada49bb2039 IP_Integrator 3 TRUE @@ -608,11 +616,30 @@ + + + + + + + + + + + + + + + + + + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0.xml b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0.xml index a111dd4..3ac5b1d 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0.xml +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0.xml @@ -460,7 +460,7 @@ - false + true @@ -531,6 +531,14 @@ CLK_DOMAIN Arty_Z7_20_sys_clock + + ASSOCIATED_BUSIF + + + + ASSOCIATED_RESET + + @@ -571,6 +579,44 @@ + + clock_CLK_OUT2 + + + + + + + CLK_OUT2 + + + clk_out2 + + + + + + ASSOCIATED_RESET + + + + ASSOCIATED_BUSIF + + + + CLK_DOMAIN + /clk_wiz_0_clk_out1 + + + PHASE + 0.0 + + + FREQ_HZ + 200000000 + + + @@ -581,7 +627,7 @@ boundaryCRC - 155eab18 + 3483db4d boundaryCRCversion @@ -589,7 +635,7 @@ customizationCRC - 923f6f20 + 45a0273c customizationCRCversion @@ -598,20 +644,20 @@ - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files - xilinx_anylanguagesynthesis_view_fileset + xilinx_externalfiles_view_fileset GENtimestamp - Mon Feb 27 18:05:25 UTC 2017 + Mon Mar 06 19:29:27 UTC 2017 boundaryCRC - e33de72f + aa4ce810 boundaryCRCversion @@ -619,7 +665,7 @@ customizationCRC - 923f6f20 + 45a0273c customizationCRCversion @@ -628,20 +674,20 @@ - xilinx_anylanguagesynthesiswrapper - Synthesis Wrapper - :vivado.xilinx.com:synthesis.wrapper + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis - xilinx_anylanguagesynthesiswrapper_view_fileset + xilinx_anylanguagesynthesis_view_fileset GENtimestamp - Mon Feb 27 18:05:25 UTC 2017 + Mon Mar 06 19:29:14 UTC 2017 boundaryCRC - e33de72f + aa4ce810 boundaryCRCversion @@ -649,7 +695,7 @@ customizationCRC - 923f6f20 + 45a0273c customizationCRCversion @@ -658,20 +704,20 @@ - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation + xilinx_anylanguagesynthesiswrapper + Synthesis Wrapper + :vivado.xilinx.com:synthesis.wrapper - xilinx_anylanguagebehavioralsimulation_view_fileset + xilinx_anylanguagesynthesiswrapper_view_fileset GENtimestamp - Mon Feb 27 18:05:25 UTC 2017 + Mon Mar 06 19:29:15 UTC 2017 boundaryCRC - e33de72f + aa4ce810 boundaryCRCversion @@ -679,7 +725,7 @@ customizationCRC - 43780904 + 45a0273c customizationCRCversion @@ -688,20 +734,20 @@ - xilinx_anylanguagesimulationwrapper - Simulation Wrapper - :vivado.xilinx.com:simulation.wrapper + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation - xilinx_anylanguagesimulationwrapper_view_fileset + xilinx_anylanguagebehavioralsimulation_view_fileset GENtimestamp - Mon Feb 27 18:05:25 UTC 2017 + Mon Mar 06 19:29:14 UTC 2017 boundaryCRC - e33de72f + aa4ce810 boundaryCRCversion @@ -709,7 +755,7 @@ customizationCRC - 43780904 + 40085ac8 customizationCRCversion @@ -718,20 +764,20 @@ - xilinx_implementation - Implementation - :vivado.xilinx.com:implementation + xilinx_anylanguagesimulationwrapper + Simulation Wrapper + :vivado.xilinx.com:simulation.wrapper - xilinx_implementation_view_fileset + xilinx_anylanguagesimulationwrapper_view_fileset GENtimestamp - Mon Feb 27 18:05:26 UTC 2017 + Mon Mar 06 19:29:15 UTC 2017 boundaryCRC - e33de72f + aa4ce810 boundaryCRCversion @@ -739,7 +785,7 @@ customizationCRC - 923f6f20 + 40085ac8 customizationCRCversion @@ -748,20 +794,20 @@ - xilinx_externalfiles - External Files - :vivado.xilinx.com:external.files + xilinx_implementation + Implementation + :vivado.xilinx.com:implementation - xilinx_externalfiles_view_fileset + xilinx_implementation_view_fileset GENtimestamp - Mon Feb 27 18:06:24 UTC 2017 + Mon Mar 06 19:29:15 UTC 2017 boundaryCRC - e33de72f + aa4ce810 boundaryCRCversion @@ -769,7 +815,7 @@ customizationCRC - 923f6f20 + 45a0273c customizationCRCversion @@ -1738,7 +1784,7 @@ - false + true @@ -2011,6 +2057,19 @@ + + clk_out2 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + locked @@ -2028,7 +2087,7 @@ C_CLKOUT2_USED - 0 + 1 C_USER_CLK_FREQ0 @@ -2232,7 +2291,7 @@ C_USE_RESET - 0 + 1 C_RESET_LOW @@ -2264,7 +2323,7 @@ C_NUM_OUT_CLKS - 1 + 2 C_CLKOUT1_DRIVES @@ -2321,7 +2380,7 @@ C_OUTCLK_SUM_ROW2 - no_CLK_OUT2_output + clk_out2___200.000______0.000______50.0______109.241_____96.948 C_OUTCLK_SUM_ROW3 @@ -2349,7 +2408,7 @@ C_CLKOUT2_REQUESTED_OUT_FREQ - 100.000 + 200 C_CLKOUT3_REQUESTED_OUT_FREQ @@ -2433,7 +2492,7 @@ C_CLKOUT2_OUT_FREQ - 100.000 + 200.000 C_CLKOUT3_OUT_FREQ @@ -2489,7 +2548,7 @@ C_CLKOUT2_DUTY_CYCLE - 50.000 + 50.0 C_CLKOUT3_DUTY_CYCLE @@ -2601,7 +2660,7 @@ C_MMCM_CLKOUT1_DIVIDE - 1 + 5 C_MMCM_CLKOUT2_DIVIDE @@ -2981,7 +3040,7 @@ C_PRIMITIVE - MMCM + PLL C_SS_MODE @@ -3043,11 +3102,11 @@ C_CLKOUT1_1 - 1041 + 1083 C_CLKOUT1_2 - 00c0 + 0080 C_CLKOUT2_1 @@ -3127,7 +3186,7 @@ C_DIVIDE2_AUTO - 1.25 + 0.625 C_DIVIDE3_AUTO @@ -3235,7 +3294,7 @@ C_CLKOUT1_ACTUAL_FREQ - 100.000 + 200.000 C_CLKOUT2_ACTUAL_FREQ @@ -3401,6 +3460,42 @@ + + xilinx_externalfiles_view_fileset + + Arty_Z7_20_clk_wiz_0_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + Arty_Z7_20_clk_wiz_0_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Arty_Z7_20_clk_wiz_0_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Arty_Z7_20_clk_wiz_0_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Arty_Z7_20_clk_wiz_0_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + xilinx_anylanguagesynthesis_view_fileset @@ -3506,42 +3601,6 @@ USED_IN_synthesis - - xilinx_externalfiles_view_fileset - - Arty_Z7_20_clk_wiz_0_0.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - Arty_Z7_20_clk_wiz_0_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - Arty_Z7_20_clk_wiz_0_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - Arty_Z7_20_clk_wiz_0_0_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - Arty_Z7_20_clk_wiz_0_0_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements. @@ -3617,7 +3676,7 @@ PRIMITIVE Primitive - MMCM + PLL PRIMTYPE_SEL @@ -3735,7 +3794,7 @@ CLKOUT2_USED - false + true CLKOUT3_USED @@ -3759,7 +3818,7 @@ NUM_OUT_CLKS - 1 + 2 CLK_OUT1_USE_FINE_PS_GUI @@ -3879,7 +3938,7 @@ CLKOUT2_REQUESTED_OUT_FREQ - 100.000 + 200 CLKOUT2_REQUESTED_PHASE @@ -4067,7 +4126,7 @@ USE_RESET - false + true USE_POWER_DOWN @@ -4147,7 +4206,7 @@ MMCM_DIVCLK_DIVIDE - 1 + 1 MMCM_BANDWIDTH @@ -4155,7 +4214,7 @@ MMCM_CLKFBOUT_MULT_F - 8.000 + 8 MMCM_CLKFBOUT_PHASE @@ -4199,7 +4258,7 @@ MMCM_CLKOUT0_DIVIDE_F - 8.000 + 8 MMCM_CLKOUT0_DUTY_CYCLE @@ -4215,7 +4274,7 @@ MMCM_CLKOUT1_DIVIDE - 1 + 5 MMCM_CLKOUT1_DUTY_CYCLE @@ -4524,12 +4583,12 @@ CLKOUT2_JITTER Clkout2 Jitter - 0.0 + 109.241 CLKOUT2_PHASE_ERROR Clkout2 Phase - 0.0 + 96.948 CLKOUT3_JITTER @@ -4611,11 +4670,30 @@ + + + + + + + + + + + + + + + + + + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0_clk_wiz.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0_clk_wiz.v index 8df24e8..512a1dc 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0_clk_wiz.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0_clk_wiz.v @@ -57,6 +57,7 @@ // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) //---------------------------------------------------------------------------- // clk_out1___125.000______0.000______50.0______119.348_____96.948 +// clk_out2___200.000______0.000______50.0______109.241_____96.948 // //---------------------------------------------------------------------------- // Input Clock Freq (MHz) Input Jitter (UI) @@ -70,7 +71,9 @@ module Arty_Z7_20_clk_wiz_0_0_clk_wiz (// Clock in ports // Clock out ports output clk_out1, + output clk_out2, // Status and control signals + input reset, output locked, input clk_in1 ); @@ -105,49 +108,38 @@ wire clk_in2_Arty_Z7_20_clk_wiz_0_0; wire clkfbout_Arty_Z7_20_clk_wiz_0_0; wire clkfbout_buf_Arty_Z7_20_clk_wiz_0_0; wire clkfboutb_unused; - wire clkout0b_unused; - wire clkout1_unused; - wire clkout1b_unused; wire clkout2_unused; - wire clkout2b_unused; wire clkout3_unused; - wire clkout3b_unused; wire clkout4_unused; wire clkout5_unused; wire clkout6_unused; wire clkfbstopped_unused; wire clkinstopped_unused; + wire reset_high; - MMCME2_ADV + PLLE2_ADV #(.BANDWIDTH ("OPTIMIZED"), - .CLKOUT4_CASCADE ("FALSE"), .COMPENSATION ("ZHOLD"), - .STARTUP_WAIT ("FALSE"), .DIVCLK_DIVIDE (1), - .CLKFBOUT_MULT_F (8.000), + .CLKFBOUT_MULT (8), .CLKFBOUT_PHASE (0.000), - .CLKFBOUT_USE_FINE_PS ("FALSE"), - .CLKOUT0_DIVIDE_F (8.000), + .CLKOUT0_DIVIDE (8), .CLKOUT0_PHASE (0.000), .CLKOUT0_DUTY_CYCLE (0.500), - .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKOUT1_DIVIDE (5), + .CLKOUT1_PHASE (0.000), + .CLKOUT1_DUTY_CYCLE (0.500), .CLKIN1_PERIOD (8.0)) - mmcm_adv_inst + plle2_adv_inst // Output clocks ( .CLKFBOUT (clkfbout_Arty_Z7_20_clk_wiz_0_0), - .CLKFBOUTB (clkfboutb_unused), .CLKOUT0 (clk_out1_Arty_Z7_20_clk_wiz_0_0), - .CLKOUT0B (clkout0b_unused), - .CLKOUT1 (clkout1_unused), - .CLKOUT1B (clkout1b_unused), + .CLKOUT1 (clk_out2_Arty_Z7_20_clk_wiz_0_0), .CLKOUT2 (clkout2_unused), - .CLKOUT2B (clkout2b_unused), .CLKOUT3 (clkout3_unused), - .CLKOUT3B (clkout3b_unused), .CLKOUT4 (clkout4_unused), .CLKOUT5 (clkout5_unused), - .CLKOUT6 (clkout6_unused), // Input clock control .CLKFBIN (clkfbout_buf_Arty_Z7_20_clk_wiz_0_0), .CLKIN1 (clk_in1_Arty_Z7_20_clk_wiz_0_0), @@ -162,17 +154,11 @@ wire clk_in2_Arty_Z7_20_clk_wiz_0_0; .DO (do_unused), .DRDY (drdy_unused), .DWE (1'b0), - // Ports for dynamic phase shift - .PSCLK (1'b0), - .PSEN (1'b0), - .PSINCDEC (1'b0), - .PSDONE (psdone_unused), // Other control and status signals .LOCKED (locked_int), - .CLKINSTOPPED (clkinstopped_unused), - .CLKFBSTOPPED (clkfbstopped_unused), .PWRDWN (1'b0), - .RST (1'b0)); + .RST (reset_high)); + assign reset_high = reset; assign locked = locked_int; // Clock Monitor clock assigning @@ -191,6 +177,10 @@ wire clk_in2_Arty_Z7_20_clk_wiz_0_0; .I (clk_out1_Arty_Z7_20_clk_wiz_0_0)); + BUFG clkout2_buf + (.O (clk_out2), + .I (clk_out2_Arty_Z7_20_clk_wiz_0_0)); + endmodule diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0_sim_netlist.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0_sim_netlist.v index cacddbc..3de8148 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0_sim_netlist.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -// Date : Mon Feb 27 10:06:24 2017 +// Date : Sat Mar 04 20:35:28 2017 // Host : WK73 running 64-bit Service Pack 1 (build 7601) -// Command : write_verilog -force -mode funcsim -// c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0_sim_netlist.v +// Command : write_verilog -force -mode funcsim -rename_top Arty_Z7_20_clk_wiz_0_0 -prefix +// Arty_Z7_20_clk_wiz_0_0_ Arty_Z7_20_clk_wiz_0_0_sim_netlist.v // Design : Arty_Z7_20_clk_wiz_0_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -15,28 +15,39 @@ (* NotValidForBitStream *) module Arty_Z7_20_clk_wiz_0_0 (clk_out1, + clk_out2, + reset, locked, clk_in1); output clk_out1; + output clk_out2; + input reset; output locked; input clk_in1; (* IBUF_LOW_PWR *) wire clk_in1; wire clk_out1; + wire clk_out2; wire locked; + wire reset; Arty_Z7_20_clk_wiz_0_0_Arty_Z7_20_clk_wiz_0_0_clk_wiz inst (.clk_in1(clk_in1), .clk_out1(clk_out1), - .locked(locked)); + .clk_out2(clk_out2), + .locked(locked), + .reset(reset)); endmodule -(* ORIG_REF_NAME = "Arty_Z7_20_clk_wiz_0_0_clk_wiz" *) module Arty_Z7_20_clk_wiz_0_0_Arty_Z7_20_clk_wiz_0_0_clk_wiz (clk_out1, + clk_out2, + reset, locked, clk_in1); output clk_out1; + output clk_out2; + input reset; output locked; input clk_in1; @@ -44,25 +55,18 @@ module Arty_Z7_20_clk_wiz_0_0_Arty_Z7_20_clk_wiz_0_0_clk_wiz wire clk_in1_Arty_Z7_20_clk_wiz_0_0; wire clk_out1; wire clk_out1_Arty_Z7_20_clk_wiz_0_0; + wire clk_out2; + wire clk_out2_Arty_Z7_20_clk_wiz_0_0; wire clkfbout_Arty_Z7_20_clk_wiz_0_0; wire clkfbout_buf_Arty_Z7_20_clk_wiz_0_0; wire locked; - wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED; - wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED; - wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED; - wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED; - wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED; - wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED; - wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED; - wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED; - wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED; - wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED; - wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED; - wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED; - wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED; - wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED; - wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED; - wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED; + wire reset; + wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED; + wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED; + wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED; + wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED; + wire NLW_plle2_adv_inst_DRDY_UNCONNECTED; + wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED; (* BOX_TYPE = "PRIMITIVE" *) BUFG clkf_buf @@ -82,89 +86,64 @@ module Arty_Z7_20_clk_wiz_0_0_Arty_Z7_20_clk_wiz_0_0_clk_wiz (.I(clk_out1_Arty_Z7_20_clk_wiz_0_0), .O(clk_out1)); (* BOX_TYPE = "PRIMITIVE" *) - MMCME2_ADV #( + BUFG clkout2_buf + (.I(clk_out2_Arty_Z7_20_clk_wiz_0_0), + .O(clk_out2)); + (* BOX_TYPE = "PRIMITIVE" *) + PLLE2_ADV #( .BANDWIDTH("OPTIMIZED"), - .CLKFBOUT_MULT_F(8.000000), + .CLKFBOUT_MULT(8), .CLKFBOUT_PHASE(0.000000), - .CLKFBOUT_USE_FINE_PS("FALSE"), .CLKIN1_PERIOD(8.000000), .CLKIN2_PERIOD(0.000000), - .CLKOUT0_DIVIDE_F(8.000000), + .CLKOUT0_DIVIDE(8), .CLKOUT0_DUTY_CYCLE(0.500000), .CLKOUT0_PHASE(0.000000), - .CLKOUT0_USE_FINE_PS("FALSE"), - .CLKOUT1_DIVIDE(1), + .CLKOUT1_DIVIDE(5), .CLKOUT1_DUTY_CYCLE(0.500000), .CLKOUT1_PHASE(0.000000), - .CLKOUT1_USE_FINE_PS("FALSE"), .CLKOUT2_DIVIDE(1), .CLKOUT2_DUTY_CYCLE(0.500000), .CLKOUT2_PHASE(0.000000), - .CLKOUT2_USE_FINE_PS("FALSE"), .CLKOUT3_DIVIDE(1), .CLKOUT3_DUTY_CYCLE(0.500000), .CLKOUT3_PHASE(0.000000), - .CLKOUT3_USE_FINE_PS("FALSE"), - .CLKOUT4_CASCADE("FALSE"), .CLKOUT4_DIVIDE(1), .CLKOUT4_DUTY_CYCLE(0.500000), .CLKOUT4_PHASE(0.000000), - .CLKOUT4_USE_FINE_PS("FALSE"), .CLKOUT5_DIVIDE(1), .CLKOUT5_DUTY_CYCLE(0.500000), .CLKOUT5_PHASE(0.000000), - .CLKOUT5_USE_FINE_PS("FALSE"), - .CLKOUT6_DIVIDE(1), - .CLKOUT6_DUTY_CYCLE(0.500000), - .CLKOUT6_PHASE(0.000000), - .CLKOUT6_USE_FINE_PS("FALSE"), .COMPENSATION("ZHOLD"), .DIVCLK_DIVIDE(1), .IS_CLKINSEL_INVERTED(1'b0), - .IS_PSEN_INVERTED(1'b0), - .IS_PSINCDEC_INVERTED(1'b0), .IS_PWRDWN_INVERTED(1'b0), .IS_RST_INVERTED(1'b0), .REF_JITTER1(0.010000), .REF_JITTER2(0.010000), - .SS_EN("FALSE"), - .SS_MODE("CENTER_HIGH"), - .SS_MOD_PERIOD(10000), .STARTUP_WAIT("FALSE")) - mmcm_adv_inst + plle2_adv_inst (.CLKFBIN(clkfbout_buf_Arty_Z7_20_clk_wiz_0_0), .CLKFBOUT(clkfbout_Arty_Z7_20_clk_wiz_0_0), - .CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED), - .CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED), .CLKIN1(clk_in1_Arty_Z7_20_clk_wiz_0_0), .CLKIN2(1'b0), .CLKINSEL(1'b1), - .CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED), .CLKOUT0(clk_out1_Arty_Z7_20_clk_wiz_0_0), - .CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED), - .CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED), - .CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED), - .CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED), - .CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED), - .CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED), - .CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED), - .CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED), - .CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED), - .CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED), + .CLKOUT1(clk_out2_Arty_Z7_20_clk_wiz_0_0), + .CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED), + .CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED), + .CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED), + .CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED), .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DCLK(1'b0), .DEN(1'b0), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]), - .DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED), + .DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]), + .DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED), .DWE(1'b0), .LOCKED(locked), - .PSCLK(1'b0), - .PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED), - .PSEN(1'b0), - .PSINCDEC(1'b0), .PWRDWN(1'b0), - .RST(1'b0)); + .RST(reset)); endmodule `ifndef GLBL `define GLBL diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0_sim_netlist.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0_sim_netlist.vhdl index 3aa2b69..3ff1e4d 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0_sim_netlist.vhdl +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 --- Date : Mon Feb 27 10:06:24 2017 +-- Date : Sat Mar 04 20:35:28 2017 -- Host : WK73 running 64-bit Service Pack 1 (build 7601) --- Command : write_vhdl -force -mode funcsim --- c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0_sim_netlist.vhdl +-- Command : write_vhdl -force -mode funcsim -rename_top Arty_Z7_20_clk_wiz_0_0 -prefix +-- Arty_Z7_20_clk_wiz_0_0_ Arty_Z7_20_clk_wiz_0_0_sim_netlist.vhdl -- Design : Arty_Z7_20_clk_wiz_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. @@ -17,34 +17,25 @@ use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20_clk_wiz_0_0_Arty_Z7_20_clk_wiz_0_0_clk_wiz is port ( clk_out1 : out STD_LOGIC; + clk_out2 : out STD_LOGIC; + reset : in STD_LOGIC; locked : out STD_LOGIC; clk_in1 : in STD_LOGIC ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_clk_wiz_0_0_Arty_Z7_20_clk_wiz_0_0_clk_wiz : entity is "Arty_Z7_20_clk_wiz_0_0_clk_wiz"; end Arty_Z7_20_clk_wiz_0_0_Arty_Z7_20_clk_wiz_0_0_clk_wiz; architecture STRUCTURE of Arty_Z7_20_clk_wiz_0_0_Arty_Z7_20_clk_wiz_0_0_clk_wiz is signal clk_in1_Arty_Z7_20_clk_wiz_0_0 : STD_LOGIC; signal clk_out1_Arty_Z7_20_clk_wiz_0_0 : STD_LOGIC; + signal clk_out2_Arty_Z7_20_clk_wiz_0_0 : STD_LOGIC; signal clkfbout_Arty_Z7_20_clk_wiz_0_0 : STD_LOGIC; signal clkfbout_buf_Arty_Z7_20_clk_wiz_0_0 : STD_LOGIC; - signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC; - signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC; - signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC; - signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC; - signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC; - signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC; - signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; - signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC; - signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC; - signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC; - signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; - signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; - signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC; - signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; - signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC; - signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; + signal NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC; + signal NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; + signal NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; + signal NLW_plle2_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; + signal NLW_plle2_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); attribute BOX_TYPE : string; attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE"; attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE"; @@ -55,7 +46,8 @@ architecture STRUCTURE of Arty_Z7_20_clk_wiz_0_0_Arty_Z7_20_clk_wiz_0_0_clk_wiz attribute IFD_DELAY_VALUE : string; attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO"; attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE"; - attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE"; + attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE"; + attribute BOX_TYPE of plle2_adv_inst : label is "PRIMITIVE"; begin clkf_buf: unisim.vcomponents.BUFG port map ( @@ -75,91 +67,67 @@ clkout1_buf: unisim.vcomponents.BUFG I => clk_out1_Arty_Z7_20_clk_wiz_0_0, O => clk_out1 ); -mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV +clkout2_buf: unisim.vcomponents.BUFG + port map ( + I => clk_out2_Arty_Z7_20_clk_wiz_0_0, + O => clk_out2 + ); +plle2_adv_inst: unisim.vcomponents.PLLE2_ADV generic map( BANDWIDTH => "OPTIMIZED", - CLKFBOUT_MULT_F => 8.000000, + CLKFBOUT_MULT => 8, CLKFBOUT_PHASE => 0.000000, - CLKFBOUT_USE_FINE_PS => false, CLKIN1_PERIOD => 8.000000, CLKIN2_PERIOD => 0.000000, - CLKOUT0_DIVIDE_F => 8.000000, + CLKOUT0_DIVIDE => 8, CLKOUT0_DUTY_CYCLE => 0.500000, CLKOUT0_PHASE => 0.000000, - CLKOUT0_USE_FINE_PS => false, - CLKOUT1_DIVIDE => 1, + CLKOUT1_DIVIDE => 5, CLKOUT1_DUTY_CYCLE => 0.500000, CLKOUT1_PHASE => 0.000000, - CLKOUT1_USE_FINE_PS => false, CLKOUT2_DIVIDE => 1, CLKOUT2_DUTY_CYCLE => 0.500000, CLKOUT2_PHASE => 0.000000, - CLKOUT2_USE_FINE_PS => false, CLKOUT3_DIVIDE => 1, CLKOUT3_DUTY_CYCLE => 0.500000, CLKOUT3_PHASE => 0.000000, - CLKOUT3_USE_FINE_PS => false, - CLKOUT4_CASCADE => false, CLKOUT4_DIVIDE => 1, CLKOUT4_DUTY_CYCLE => 0.500000, CLKOUT4_PHASE => 0.000000, - CLKOUT4_USE_FINE_PS => false, CLKOUT5_DIVIDE => 1, CLKOUT5_DUTY_CYCLE => 0.500000, CLKOUT5_PHASE => 0.000000, - CLKOUT5_USE_FINE_PS => false, - CLKOUT6_DIVIDE => 1, - CLKOUT6_DUTY_CYCLE => 0.500000, - CLKOUT6_PHASE => 0.000000, - CLKOUT6_USE_FINE_PS => false, COMPENSATION => "ZHOLD", DIVCLK_DIVIDE => 1, IS_CLKINSEL_INVERTED => '0', - IS_PSEN_INVERTED => '0', - IS_PSINCDEC_INVERTED => '0', IS_PWRDWN_INVERTED => '0', IS_RST_INVERTED => '0', REF_JITTER1 => 0.010000, REF_JITTER2 => 0.010000, - SS_EN => "FALSE", - SS_MODE => "CENTER_HIGH", - SS_MOD_PERIOD => 10000, - STARTUP_WAIT => false + STARTUP_WAIT => "FALSE" ) port map ( CLKFBIN => clkfbout_buf_Arty_Z7_20_clk_wiz_0_0, CLKFBOUT => clkfbout_Arty_Z7_20_clk_wiz_0_0, - CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED, - CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED, CLKIN1 => clk_in1_Arty_Z7_20_clk_wiz_0_0, CLKIN2 => '0', CLKINSEL => '1', - CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED, CLKOUT0 => clk_out1_Arty_Z7_20_clk_wiz_0_0, - CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED, - CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED, - CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED, - CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED, - CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED, - CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED, - CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED, - CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED, - CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED, - CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED, + CLKOUT1 => clk_out2_Arty_Z7_20_clk_wiz_0_0, + CLKOUT2 => NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED, + CLKOUT3 => NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED, + CLKOUT4 => NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED, + CLKOUT5 => NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED, DADDR(6 downto 0) => B"0000000", DCLK => '0', DEN => '0', DI(15 downto 0) => B"0000000000000000", - DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0), - DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED, + DO(15 downto 0) => NLW_plle2_adv_inst_DO_UNCONNECTED(15 downto 0), + DRDY => NLW_plle2_adv_inst_DRDY_UNCONNECTED, DWE => '0', LOCKED => locked, - PSCLK => '0', - PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED, - PSEN => '0', - PSINCDEC => '0', PWRDWN => '0', - RST => '0' + RST => reset ); end STRUCTURE; library IEEE; @@ -169,6 +137,8 @@ use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20_clk_wiz_0_0 is port ( clk_out1 : out STD_LOGIC; + clk_out2 : out STD_LOGIC; + reset : in STD_LOGIC; locked : out STD_LOGIC; clk_in1 : in STD_LOGIC ); @@ -182,6 +152,8 @@ inst: entity work.Arty_Z7_20_clk_wiz_0_0_Arty_Z7_20_clk_wiz_0_0_clk_wiz port map ( clk_in1 => clk_in1, clk_out1 => clk_out1, - locked => locked + clk_out2 => clk_out2, + locked => locked, + reset => reset ); end STRUCTURE; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0_stub.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0_stub.v index 7a255c4..f4311fd 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0_stub.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -// Date : Mon Feb 27 10:06:24 2017 +// Date : Sat Mar 04 20:35:28 2017 // Host : WK73 running 64-bit Service Pack 1 (build 7601) -// Command : write_verilog -force -mode synth_stub -// c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0_stub.v +// Command : write_verilog -force -mode synth_stub -rename_top Arty_Z7_20_clk_wiz_0_0 -prefix +// Arty_Z7_20_clk_wiz_0_0_ Arty_Z7_20_clk_wiz_0_0_stub.v // Design : Arty_Z7_20_clk_wiz_0_0 // Purpose : Stub declaration of top-level module interface // Device : xc7z020clg400-1 @@ -13,9 +13,11 @@ // This empty module with port declaration file causes synthesis tools to infer a black box for IP. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. -module Arty_Z7_20_clk_wiz_0_0(clk_out1, locked, clk_in1) -/* synthesis syn_black_box black_box_pad_pin="clk_out1,locked,clk_in1" */; +module Arty_Z7_20_clk_wiz_0_0(clk_out1, clk_out2, reset, locked, clk_in1) +/* synthesis syn_black_box black_box_pad_pin="clk_out1,clk_out2,reset,locked,clk_in1" */; output clk_out1; + output clk_out2; + input reset; output locked; input clk_in1; endmodule diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0_stub.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0_stub.vhdl index a2e4d35..38f4981 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0_stub.vhdl +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 --- Date : Mon Feb 27 10:06:24 2017 +-- Date : Sat Mar 04 20:35:28 2017 -- Host : WK73 running 64-bit Service Pack 1 (build 7601) --- Command : write_vhdl -force -mode synth_stub --- c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_clk_wiz_0_0/Arty_Z7_20_clk_wiz_0_0_stub.vhdl +-- Command : write_vhdl -force -mode synth_stub -rename_top Arty_Z7_20_clk_wiz_0_0 -prefix +-- Arty_Z7_20_clk_wiz_0_0_ Arty_Z7_20_clk_wiz_0_0_stub.vhdl -- Design : Arty_Z7_20_clk_wiz_0_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7z020clg400-1 @@ -15,6 +15,8 @@ use IEEE.STD_LOGIC_1164.ALL; entity Arty_Z7_20_clk_wiz_0_0 is Port ( clk_out1 : out STD_LOGIC; + clk_out2 : out STD_LOGIC; + reset : in STD_LOGIC; locked : out STD_LOGIC; clk_in1 : in STD_LOGIC ); @@ -25,6 +27,6 @@ architecture stub of Arty_Z7_20_clk_wiz_0_0 is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk_out1,locked,clk_in1"; +attribute black_box_pad_pin of stub : architecture is "clk_out1,clk_out2,reset,locked,clk_in1"; begin end; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/Arty_Z7_20_dvi2rgb_0_0.dcp b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/Arty_Z7_20_dvi2rgb_0_0.dcp new file mode 100644 index 0000000..b56c044 Binary files /dev/null and b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/Arty_Z7_20_dvi2rgb_0_0.dcp differ diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/Arty_Z7_20_dvi2rgb_0_0.xci b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/Arty_Z7_20_dvi2rgb_0_0.xci new file mode 100644 index 0000000..c42b15d --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/Arty_Z7_20_dvi2rgb_0_0.xci @@ -0,0 +1,72 @@ + + + xilinx.com + xci + unknown + 1.0 + + + Arty_Z7_20_dvi2rgb_0_0 + + + + + Arty_Z7_20_dvi2rgb_0_0_PixelClk + 100000000 + 0.000 + + + /clk_wiz_0_clk_out1 + 200000000 + 0.0 + true + 2 + 720p_edid.data + true + 78 + 5 + false + true + Arty_Z7_20_dvi2rgb_0_0 + + + true + 2 + 720p_edid.data + true + false + false + zynq + digilentinc.com:arty-z7-20:part0:1.0 + xc7z020 + clg400 + VHDL + + MIXED + -1 + + TRUE + TRUE + IP_Integrator + 1 + TRUE + . + + ../../ipshared + 2016.4 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/Arty_Z7_20_dvi2rgb_0_0.xml b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/Arty_Z7_20_dvi2rgb_0_0.xml new file mode 100644 index 0000000..248a864 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/Arty_Z7_20_dvi2rgb_0_0.xml @@ -0,0 +1,1223 @@ + + + digilentinc.com + customized_ip + Arty_Z7_20_dvi2rgb_0_0 + 1.0 + + + TMDS + + + + + + + CLK_P + + + TMDS_Clk_p + + + + + CLK_N + + + TMDS_Clk_n + + + + + DATA_P + + + TMDS_Data_p + + + + + DATA_N + + + TMDS_Data_n + + + + + + BOARD.ASSOCIATED_PARAM + TMDS_BOARD_INTERFACE + + + + + SerialClk + + + + + + + CLK + + + SerialClk + + + + + + + false + + + + + + RefClk + + + + + + + CLK + + + RefClk + + + + + + FREQ_HZ + 200000000 + + + PHASE + 0.0 + + + CLK_DOMAIN + /clk_wiz_0_clk_out1 + + + ASSOCIATED_BUSIF + + + + ASSOCIATED_RESET + + + + + + SyncRst + + + + + + + RST + + + pRst + + + + + + POLARITY + ACTIVE_HIGH + + + + + + false + + + + + + AsyncRst + + + + + + + RST + + + aRst + + + + + + POLARITY + ACTIVE_HIGH + + + + + + false + + + + + + DDC + DDC + Display Data Channel + + + + + + + SCL_I + + + DDC_SCL_I + + + + + SCL_O + + + DDC_SCL_O + + + + + SCL_T + + + DDC_SCL_T + + + + + SDA_I + + + DDC_SDA_I + + + + + SDA_O + + + DDC_SDA_O + + + + + SDA_T + + + DDC_SDA_T + + + + + + BOARD.ASSOCIATED_PARAM + IIC_BOARD_INTERFACE + + + + + + true + + + + + + AsyncRst_n + + + + + + + RST + + + aRst_n + + + + + + POLARITY + ACTIVE_LOW + + + + + SyncRst_n + + + + + + + RST + + + pRst_n + + + + + + POLARITY + ACTIVE_LOW + + + + + RGB + RGB Video Output + + + + + + + DATA + + + vid_pData + + + + + HSYNC + + + vid_pHSync + + + + + VSYNC + + + vid_pVSync + + + + + ACTIVE_VIDEO + + + vid_pVDE + + + + + + PixelClk + Pixel clock for RGB video output + + + + + + + CLK + + + PixelClk + + + + + + FREQ_HZ + 100000000 + + + PHASE + 0.000 + + + CLK_DOMAIN + Arty_Z7_20_dvi2rgb_0_0_PixelClk + + + ASSOCIATED_BUSIF + + + + ASSOCIATED_RESET + + + + + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + + xilinx_vhdlsynthesis_view_fileset + + + + GENtimestamp + Sun Mar 05 02:51:35 UTC 2017 + + + boundaryCRC + 2b18ca61 + + + boundaryCRCversion + 1 + + + customizationCRC + 1d0b22cd + + + customizationCRCversion + 6 + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Mon Mar 06 02:55:59 UTC 2017 + + + boundaryCRC + 2b18ca61 + + + boundaryCRCversion + 1 + + + customizationCRC + 1d0b22cd + + + customizationCRCversion + 6 + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + GENtimestamp + Sun Mar 05 02:51:35 UTC 2017 + + + boundaryCRC + 2b18ca61 + + + boundaryCRCversion + 1 + + + customizationCRC + 43c5f6d5 + + + customizationCRCversion + 6 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Mar 06 02:55:59 UTC 2017 + + + boundaryCRC + 2b18ca61 + + + boundaryCRCversion + 1 + + + customizationCRC + 43c5f6d5 + + + customizationCRCversion + 6 + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Mon Mar 06 02:57:17 UTC 2017 + + + boundaryCRC + 2b18ca61 + + + boundaryCRCversion + 1 + + + customizationCRC + 1d0b22cd + + + customizationCRCversion + 6 + + + + + + + TMDS_Clk_p + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + TMDS_Clk_n + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + TMDS_Data_p + + in + + 2 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + TMDS_Data_n + + in + + 2 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + RefClk + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + aRst + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + aRst_n + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + true + + + + + + vid_pData + + out + + 23 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + vid_pVDE + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + vid_pHSync + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + vid_pVSync + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + PixelClk + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + SerialClk + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + false + + + + + + aPixelClkLckd + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DDC_SDA_I + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DDC_SDA_O + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DDC_SDA_T + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DDC_SCL_I + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DDC_SCL_O + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DDC_SCL_T + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + pRst + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + pRst_n + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + true + + + + + + + + kEmulateDDC + Enable DDC ROM + true + + + kRstActiveHigh + Resets active high + false + + + kClkRange + Kclkrange + 2 + + + kIDLY_TapValuePs + Kidly Tapvalueps + 78 + + + kIDLY_TapWidth + Kidly Tapwidth + 5 + + + kAddBUFG + Kaddbufg + true + + + kEdidFileName + Kedidfilename + 720p_edid.data + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_376da672 + 1 + 2 + + + choice_pairs_54dbc231 + 720p_edid.data + 900p_edid.data + 1024_edid.data + 1080_edid.data + + + + + xilinx_vhdlsynthesis_view_fileset + + src/1024_edid.data + data + + + src/900p_edid.data + data + + + src/1080_edid.data + data + + + src/720p_edid.data + data + + + src/dvi2rgb.xdc + xdc + USED_IN_implementation + USED_IN_synthesis + + + src/dvi2rgb_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + ../../ipshared/d2d3/src/SyncBase.vhd + vhdlSource + + + ../../ipshared/d2d3/src/EEPROM_8b.vhd + vhdlSource + + + ../../ipshared/d2d3/src/TWI_SlaveCtl.vhd + vhdlSource + + + ../../ipshared/d2d3/src/GlitchFilter.vhd + vhdlSource + + + ../../ipshared/d2d3/src/SyncAsync.vhd + vhdlSource + + + ../../ipshared/d2d3/src/DVI_Constants.vhd + vhdlSource + + + ../../ipshared/d2d3/src/SyncAsyncReset.vhd + vhdlSource + + + ../../ipshared/d2d3/src/ResyncToBUFG.vhd + vhdlSource + + + ../../ipshared/d2d3/src/PhaseAlign.vhd + vhdlSource + + + ../../ipshared/d2d3/src/InputSERDES.vhd + vhdlSource + + + ../../ipshared/d2d3/src/ChannelBond.vhd + vhdlSource + + + ../../ipshared/d2d3/src/TMDS_Decoder.vhd + vhdlSource + + + ../../ipshared/d2d3/src/TMDS_Clocking.vhd + vhdlSource + + + ../../ipshared/d2d3/src/dvi2rgb.vhd + vhdlSource + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/Arty_Z7_20_dvi2rgb_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + ../../ipshared/d2d3/src/SyncBase.vhd + vhdlSource + USED_IN_ipstatic + + + ../../ipshared/d2d3/src/EEPROM_8b.vhd + vhdlSource + USED_IN_ipstatic + + + ../../ipshared/d2d3/src/TWI_SlaveCtl.vhd + vhdlSource + USED_IN_ipstatic + + + ../../ipshared/d2d3/src/GlitchFilter.vhd + vhdlSource + USED_IN_ipstatic + + + ../../ipshared/d2d3/src/SyncAsync.vhd + vhdlSource + USED_IN_ipstatic + + + ../../ipshared/d2d3/src/DVI_Constants.vhd + vhdlSource + USED_IN_ipstatic + + + ../../ipshared/d2d3/src/SyncAsyncReset.vhd + vhdlSource + USED_IN_ipstatic + + + ../../ipshared/d2d3/src/PhaseAlign.vhd + vhdlSource + USED_IN_ipstatic + + + ../../ipshared/d2d3/src/InputSERDES.vhd + vhdlSource + USED_IN_ipstatic + + + ../../ipshared/d2d3/src/ChannelBond.vhd + vhdlSource + USED_IN_ipstatic + + + ../../ipshared/d2d3/src/ResyncToBUFG.vhd + vhdlSource + USED_IN_ipstatic + + + ../../ipshared/d2d3/src/TMDS_Decoder.vhd + vhdlSource + USED_IN_ipstatic + + + ../../ipshared/d2d3/src/TMDS_Clocking.vhd + vhdlSource + USED_IN_ipstatic + + + ../../ipshared/d2d3/src/dvi2rgb.vhd + vhdlSource + USED_IN_ipstatic + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/Arty_Z7_20_dvi2rgb_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_externalfiles_view_fileset + + Arty_Z7_20_dvi2rgb_0_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + Arty_Z7_20_dvi2rgb_0_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Arty_Z7_20_dvi2rgb_0_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Arty_Z7_20_dvi2rgb_0_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Arty_Z7_20_dvi2rgb_0_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + Decodes DVI 1.0 spec video stream to a parallel 24-bit RGB video output. + + + Component_Name + Component Name + Arty_Z7_20_dvi2rgb_0_0 + + + kEmulateDDC + Enable DDC ROM + true + + + kEnableSerialClkOutput + Enable serial clock output + false + + + kRstActiveHigh + Resets active high + false + + + kClkRange + TMDS clock range + 2 + + + kAddBUFG + Add BUFG to PixelClk + true + + + kEdidFileName + Preferred resolution + 720p_edid.data + + + + true + + + + + + TMDS_BOARD_INTERFACE + + + + IIC_BOARD_INTERFACE + + + + + + DVI to RGB Video Decoder (Sink) + 1 + + c:/git/xcam/common-repo/vivado-library/ip/dvi2rgb_v1_7 + c:/git/xcam/common-repo/vivado-library/ip/dvi2rgb_v1_7 + + + + + + + + + + + 2016.4 + + + + + + + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/Arty_Z7_20_dvi2rgb_0_0_sim_netlist.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/Arty_Z7_20_dvi2rgb_0_0_sim_netlist.v new file mode 100644 index 0000000..3431f60 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/Arty_Z7_20_dvi2rgb_0_0_sim_netlist.v @@ -0,0 +1,11385 @@ +// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +// Date : Sun Mar 05 18:57:17 2017 +// Host : WK73 running 64-bit Service Pack 1 (build 7601) +// Command : write_verilog -force -mode funcsim +// c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/Arty_Z7_20_dvi2rgb_0_0_sim_netlist.v +// Design : Arty_Z7_20_dvi2rgb_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg400-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "Arty_Z7_20_dvi2rgb_0_0,dvi2rgb,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "dvi2rgb,Vivado 2016.4" *) +(* NotValidForBitStream *) +module Arty_Z7_20_dvi2rgb_0_0 + (TMDS_Clk_p, + TMDS_Clk_n, + TMDS_Data_p, + TMDS_Data_n, + RefClk, + aRst_n, + vid_pData, + vid_pVDE, + vid_pHSync, + vid_pVSync, + PixelClk, + aPixelClkLckd, + DDC_SDA_I, + DDC_SDA_O, + DDC_SDA_T, + DDC_SCL_I, + DDC_SCL_O, + DDC_SCL_T, + pRst_n); + (* x_interface_info = "digilentinc.com:interface:tmds:1.0 TMDS CLK_P" *) input TMDS_Clk_p; + (* x_interface_info = "digilentinc.com:interface:tmds:1.0 TMDS CLK_N" *) input TMDS_Clk_n; + (* x_interface_info = "digilentinc.com:interface:tmds:1.0 TMDS DATA_P" *) input [2:0]TMDS_Data_p; + (* x_interface_info = "digilentinc.com:interface:tmds:1.0 TMDS DATA_N" *) input [2:0]TMDS_Data_n; + (* x_interface_info = "xilinx.com:signal:clock:1.0 RefClk CLK" *) input RefClk; + (* x_interface_info = "xilinx.com:signal:reset:1.0 AsyncRst_n RST" *) input aRst_n; + (* x_interface_info = "xilinx.com:interface:vid_io:1.0 RGB DATA" *) output [23:0]vid_pData; + (* x_interface_info = "xilinx.com:interface:vid_io:1.0 RGB ACTIVE_VIDEO" *) output vid_pVDE; + (* x_interface_info = "xilinx.com:interface:vid_io:1.0 RGB HSYNC" *) output vid_pHSync; + (* x_interface_info = "xilinx.com:interface:vid_io:1.0 RGB VSYNC" *) output vid_pVSync; + (* x_interface_info = "xilinx.com:signal:clock:1.0 PixelClk CLK" *) output PixelClk; + output aPixelClkLckd; + (* x_interface_info = "xilinx.com:interface:iic:1.0 DDC SDA_I" *) input DDC_SDA_I; + (* x_interface_info = "xilinx.com:interface:iic:1.0 DDC SDA_O" *) output DDC_SDA_O; + (* x_interface_info = "xilinx.com:interface:iic:1.0 DDC SDA_T" *) output DDC_SDA_T; + (* x_interface_info = "xilinx.com:interface:iic:1.0 DDC SCL_I" *) input DDC_SCL_I; + (* x_interface_info = "xilinx.com:interface:iic:1.0 DDC SCL_O" *) output DDC_SCL_O; + (* x_interface_info = "xilinx.com:interface:iic:1.0 DDC SCL_T" *) output DDC_SCL_T; + (* x_interface_info = "xilinx.com:signal:reset:1.0 SyncRst_n RST" *) input pRst_n; + + wire DDC_SCL_I; + wire DDC_SCL_O; + wire DDC_SCL_T; + wire DDC_SDA_I; + wire DDC_SDA_O; + wire DDC_SDA_T; + wire PixelClk; + wire RefClk; + (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR *) (* IOSTANDARD = "TMDS_33" *) wire TMDS_Clk_n; + (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR *) (* IOSTANDARD = "TMDS_33" *) wire TMDS_Clk_p; + (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR *) (* IOSTANDARD = "TMDS_33" *) wire [2:0]TMDS_Data_n; + (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR *) (* IOSTANDARD = "TMDS_33" *) wire [2:0]TMDS_Data_p; + wire aPixelClkLckd; + wire aRst_n; + wire pRst_n; + wire [23:0]vid_pData; + wire vid_pHSync; + wire vid_pVDE; + wire vid_pVSync; + wire NLW_U0_SerialClk_UNCONNECTED; + + (* kAddBUFG = "TRUE" *) + (* kClkRange = "2" *) + (* kEdidFileName = "720p_edid.data" *) + (* kEmulateDDC = "TRUE" *) + (* kIDLY_TapValuePs = "78" *) + (* kIDLY_TapWidth = "5" *) + (* kRstActiveHigh = "FALSE" *) + Arty_Z7_20_dvi2rgb_0_0_dvi2rgb U0 + (.DDC_SCL_I(DDC_SCL_I), + .DDC_SCL_O(DDC_SCL_O), + .DDC_SCL_T(DDC_SCL_T), + .DDC_SDA_I(DDC_SDA_I), + .DDC_SDA_O(DDC_SDA_O), + .DDC_SDA_T(DDC_SDA_T), + .PixelClk(PixelClk), + .RefClk(RefClk), + .SerialClk(NLW_U0_SerialClk_UNCONNECTED), + .TMDS_Clk_n(TMDS_Clk_n), + .TMDS_Clk_p(TMDS_Clk_p), + .TMDS_Data_n(TMDS_Data_n), + .TMDS_Data_p(TMDS_Data_p), + .aPixelClkLckd(aPixelClkLckd), + .aRst(1'b0), + .aRst_n(aRst_n), + .pRst(1'b0), + .pRst_n(pRst_n), + .vid_pData(vid_pData), + .vid_pHSync(vid_pHSync), + .vid_pVDE(vid_pVDE), + .vid_pVSync(vid_pVSync)); +endmodule + +(* ORIG_REF_NAME = "ChannelBond" *) +module Arty_Z7_20_dvi2rgb_0_0_ChannelBond + (pAllVld_q, + pAllVldBgnFlag, + pMeRdy_int_reg_0, + D, + SR, + pAllVld, + PixelClk_int, + pAllVldBgnFlag0, + pAligned_reg, + pRdy_0, + pRdy_1, + pDataInRaw); + output pAllVld_q; + output pAllVldBgnFlag; + output pMeRdy_int_reg_0; + output [7:0]D; + output [0:0]SR; + input pAllVld; + input PixelClk_int; + input pAllVldBgnFlag0; + input pAligned_reg; + input pRdy_0; + input pRdy_1; + input [9:0]pDataInRaw; + + wire [7:0]D; + wire PixelClk_int; + wire [0:0]SR; + wire pAligned_reg; + wire pAllVld; + wire pAllVldBgnFlag; + wire pAllVldBgnFlag0; + wire pAllVld_q; + wire pBlnkBgnFlag; + wire pBlnkBgnFlag_i_1_n_0; + wire \pDataFIFO_reg_n_0_[9] ; + wire [8:0]pDataInBnd; + wire [9:0]pDataInRaw; + wire \pDataIn[7]_i_3__1_n_0 ; + wire \pDataIn[7]_i_4__1_n_0 ; + wire pMeRdy_int_i_1_n_0; + wire pMeRdy_int_reg_0; + wire [4:0]pRdA; + wire \pRdA_rep[0]_i_1_n_0 ; + wire \pRdA_rep[1]_i_1_n_0 ; + wire \pRdA_rep[2]_i_1_n_0 ; + wire \pRdA_rep[3]_i_1_n_0 ; + wire \pRdA_rep[4]_i_1_n_0 ; + wire pRdEn; + wire pRdEn_i_1_n_0; + wire pRdy_0; + wire pRdy_1; + wire pTokenFlag; + wire pTokenFlag0; + wire pTokenFlag_i_2_n_0; + wire pTokenFlag_i_3_n_0; + wire pTokenFlag_q; + wire [4:0]pWrA_reg__0; + wire [4:0]p_0_in__0; + wire [9:0]p_0_out__0; + wire [1:0]NLW_pFIFO_reg_0_31_0_5_DOD_UNCONNECTED; + wire [1:0]NLW_pFIFO_reg_0_31_6_9_DOC_UNCONNECTED; + wire [1:0]NLW_pFIFO_reg_0_31_6_9_DOD_UNCONNECTED; + + FDRE pAllVldBgnFlag_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pAllVldBgnFlag0), + .Q(pAllVldBgnFlag), + .R(1'b0)); + FDRE pAllVld_q_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pAllVld), + .Q(pAllVld_q), + .R(1'b0)); + LUT2 #( + .INIT(4'h2)) + pBlnkBgnFlag_i_1 + (.I0(pTokenFlag), + .I1(pTokenFlag_q), + .O(pBlnkBgnFlag_i_1_n_0)); + FDRE pBlnkBgnFlag_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pBlnkBgnFlag_i_1_n_0), + .Q(pBlnkBgnFlag), + .R(1'b0)); + FDRE \pDataFIFO_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_out__0[0]), + .Q(pDataInBnd[0]), + .R(1'b0)); + FDRE \pDataFIFO_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_out__0[1]), + .Q(pDataInBnd[1]), + .R(1'b0)); + FDRE \pDataFIFO_reg[2] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_out__0[2]), + .Q(pDataInBnd[2]), + .R(1'b0)); + FDRE \pDataFIFO_reg[3] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_out__0[3]), + .Q(pDataInBnd[3]), + .R(1'b0)); + FDRE \pDataFIFO_reg[4] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_out__0[4]), + .Q(pDataInBnd[4]), + .R(1'b0)); + FDRE \pDataFIFO_reg[5] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_out__0[5]), + .Q(pDataInBnd[5]), + .R(1'b0)); + FDRE \pDataFIFO_reg[6] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_out__0[6]), + .Q(pDataInBnd[6]), + .R(1'b0)); + FDRE \pDataFIFO_reg[7] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_out__0[7]), + .Q(pDataInBnd[7]), + .R(1'b0)); + FDRE \pDataFIFO_reg[8] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_out__0[8]), + .Q(pDataInBnd[8]), + .R(1'b0)); + FDRE \pDataFIFO_reg[9] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_out__0[9]), + .Q(\pDataFIFO_reg_n_0_[9] ), + .R(1'b0)); + LUT3 #( + .INIT(8'h60)) + \pDataIn[0]_i_1__0 + (.I0(\pDataFIFO_reg_n_0_[9] ), + .I1(pDataInBnd[0]), + .I2(\pDataIn[7]_i_3__1_n_0 ), + .O(D[0])); + (* SOFT_HLUTNM = "soft_lutpair56" *) + LUT4 #( + .INIT(16'h6090)) + \pDataIn[1]_i_1__0 + (.I0(pDataInBnd[1]), + .I1(pDataInBnd[0]), + .I2(\pDataIn[7]_i_3__1_n_0 ), + .I3(pDataInBnd[8]), + .O(D[1])); + (* SOFT_HLUTNM = "soft_lutpair56" *) + LUT4 #( + .INIT(16'h6090)) + \pDataIn[2]_i_1__0 + (.I0(pDataInBnd[2]), + .I1(pDataInBnd[1]), + .I2(\pDataIn[7]_i_3__1_n_0 ), + .I3(pDataInBnd[8]), + .O(D[2])); + (* SOFT_HLUTNM = "soft_lutpair55" *) + LUT4 #( + .INIT(16'h6090)) + \pDataIn[3]_i_1__0 + (.I0(pDataInBnd[3]), + .I1(pDataInBnd[2]), + .I2(\pDataIn[7]_i_3__1_n_0 ), + .I3(pDataInBnd[8]), + .O(D[3])); + (* SOFT_HLUTNM = "soft_lutpair55" *) + LUT4 #( + .INIT(16'h6090)) + \pDataIn[4]_i_1__0 + (.I0(pDataInBnd[4]), + .I1(pDataInBnd[3]), + .I2(\pDataIn[7]_i_3__1_n_0 ), + .I3(pDataInBnd[8]), + .O(D[4])); + LUT4 #( + .INIT(16'h6090)) + \pDataIn[5]_i_1__0 + (.I0(pDataInBnd[5]), + .I1(pDataInBnd[4]), + .I2(\pDataIn[7]_i_3__1_n_0 ), + .I3(pDataInBnd[8]), + .O(D[5])); + (* SOFT_HLUTNM = "soft_lutpair57" *) + LUT4 #( + .INIT(16'h6090)) + \pDataIn[6]_i_1__0 + (.I0(pDataInBnd[6]), + .I1(pDataInBnd[5]), + .I2(\pDataIn[7]_i_3__1_n_0 ), + .I3(pDataInBnd[8]), + .O(D[6])); + (* SOFT_HLUTNM = "soft_lutpair58" *) + LUT3 #( + .INIT(8'h7F)) + \pDataIn[7]_i_1__0 + (.I0(pMeRdy_int_reg_0), + .I1(pRdy_0), + .I2(pRdy_1), + .O(SR)); + (* SOFT_HLUTNM = "soft_lutpair57" *) + LUT4 #( + .INIT(16'h6090)) + \pDataIn[7]_i_2__0 + (.I0(pDataInBnd[7]), + .I1(pDataInBnd[6]), + .I2(\pDataIn[7]_i_3__1_n_0 ), + .I3(pDataInBnd[8]), + .O(D[7])); + LUT6 #( + .INIT(64'hFFFFFFFFFFFBDFFF)) + \pDataIn[7]_i_3__1 + (.I0(pDataInBnd[5]), + .I1(pDataInBnd[4]), + .I2(pDataInBnd[3]), + .I3(pDataInBnd[7]), + .I4(pDataInBnd[6]), + .I5(\pDataIn[7]_i_4__1_n_0 ), + .O(\pDataIn[7]_i_3__1_n_0 )); + LUT6 #( + .INIT(64'hFBBFFFFFFFFFFDDF)) + \pDataIn[7]_i_4__1 + (.I0(pDataInBnd[2]), + .I1(pDataInBnd[3]), + .I2(pDataInBnd[7]), + .I3(pDataInBnd[8]), + .I4(pDataInBnd[0]), + .I5(pDataInBnd[1]), + .O(\pDataIn[7]_i_4__1_n_0 )); + (* METHODOLOGY_DRC_VIOS = "" *) + RAM32M pFIFO_reg_0_31_0_5 + (.ADDRA(pRdA), + .ADDRB(pRdA), + .ADDRC(pRdA), + .ADDRD(pWrA_reg__0), + .DIA(pDataInRaw[1:0]), + .DIB(pDataInRaw[3:2]), + .DIC(pDataInRaw[5:4]), + .DID({1'b0,1'b0}), + .DOA(p_0_out__0[1:0]), + .DOB(p_0_out__0[3:2]), + .DOC(p_0_out__0[5:4]), + .DOD(NLW_pFIFO_reg_0_31_0_5_DOD_UNCONNECTED[1:0]), + .WCLK(PixelClk_int), + .WE(pAllVld)); + (* METHODOLOGY_DRC_VIOS = "" *) + RAM32M pFIFO_reg_0_31_6_9 + (.ADDRA(pRdA), + .ADDRB(pRdA), + .ADDRC(pRdA), + .ADDRD(pWrA_reg__0), + .DIA(pDataInRaw[7:6]), + .DIB(pDataInRaw[9:8]), + .DIC({1'b0,1'b0}), + .DID({1'b0,1'b0}), + .DOA(p_0_out__0[7:6]), + .DOB(p_0_out__0[9:8]), + .DOC(NLW_pFIFO_reg_0_31_6_9_DOC_UNCONNECTED[1:0]), + .DOD(NLW_pFIFO_reg_0_31_6_9_DOD_UNCONNECTED[1:0]), + .WCLK(PixelClk_int), + .WE(pAllVld)); + (* SOFT_HLUTNM = "soft_lutpair58" *) + LUT2 #( + .INIT(4'hE)) + pMeRdy_int_i_1 + (.I0(pBlnkBgnFlag), + .I1(pMeRdy_int_reg_0), + .O(pMeRdy_int_i_1_n_0)); + FDRE pMeRdy_int_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pMeRdy_int_i_1_n_0), + .Q(pMeRdy_int_reg_0), + .R(pAligned_reg)); + FDRE \pRdA_reg_rep[0] + (.C(PixelClk_int), + .CE(pRdEn), + .D(\pRdA_rep[0]_i_1_n_0 ), + .Q(pRdA[0]), + .R(pAligned_reg)); + FDRE \pRdA_reg_rep[1] + (.C(PixelClk_int), + .CE(pRdEn), + .D(\pRdA_rep[1]_i_1_n_0 ), + .Q(pRdA[1]), + .R(pAligned_reg)); + FDRE \pRdA_reg_rep[2] + (.C(PixelClk_int), + .CE(pRdEn), + .D(\pRdA_rep[2]_i_1_n_0 ), + .Q(pRdA[2]), + .R(pAligned_reg)); + FDRE \pRdA_reg_rep[3] + (.C(PixelClk_int), + .CE(pRdEn), + .D(\pRdA_rep[3]_i_1_n_0 ), + .Q(pRdA[3]), + .R(pAligned_reg)); + FDRE \pRdA_reg_rep[4] + (.C(PixelClk_int), + .CE(pRdEn), + .D(\pRdA_rep[4]_i_1_n_0 ), + .Q(pRdA[4]), + .R(pAligned_reg)); + LUT1 #( + .INIT(2'h1)) + \pRdA_rep[0]_i_1 + (.I0(pRdA[0]), + .O(\pRdA_rep[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair60" *) + LUT2 #( + .INIT(4'h6)) + \pRdA_rep[1]_i_1 + (.I0(pRdA[0]), + .I1(pRdA[1]), + .O(\pRdA_rep[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair60" *) + LUT3 #( + .INIT(8'h78)) + \pRdA_rep[2]_i_1 + (.I0(pRdA[1]), + .I1(pRdA[0]), + .I2(pRdA[2]), + .O(\pRdA_rep[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair53" *) + LUT4 #( + .INIT(16'h7F80)) + \pRdA_rep[3]_i_1 + (.I0(pRdA[0]), + .I1(pRdA[1]), + .I2(pRdA[2]), + .I3(pRdA[3]), + .O(\pRdA_rep[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair53" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \pRdA_rep[4]_i_1 + (.I0(pRdA[2]), + .I1(pRdA[3]), + .I2(pRdA[0]), + .I3(pRdA[1]), + .I4(pRdA[4]), + .O(\pRdA_rep[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFBBBBBBBFAAAAAAA)) + pRdEn_i_1 + (.I0(pAllVldBgnFlag), + .I1(pBlnkBgnFlag), + .I2(pRdy_1), + .I3(pMeRdy_int_reg_0), + .I4(pRdy_0), + .I5(pRdEn), + .O(pRdEn_i_1_n_0)); + FDRE pRdEn_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pRdEn_i_1_n_0), + .Q(pRdEn), + .R(pAligned_reg)); + LUT6 #( + .INIT(64'h5555DD5555F55555)) + pTokenFlag_i_1 + (.I0(pRdEn), + .I1(pTokenFlag_i_2_n_0), + .I2(pTokenFlag_i_3_n_0), + .I3(pDataInBnd[1]), + .I4(pDataInBnd[2]), + .I5(pDataInBnd[0]), + .O(pTokenFlag0)); + LUT6 #( + .INIT(64'h0000002000000000)) + pTokenFlag_i_2 + (.I0(pDataInBnd[5]), + .I1(pDataInBnd[6]), + .I2(pDataInBnd[3]), + .I3(pDataInBnd[4]), + .I4(pDataInBnd[8]), + .I5(pDataInBnd[7]), + .O(pTokenFlag_i_2_n_0)); + LUT6 #( + .INIT(64'h0000002000000000)) + pTokenFlag_i_3 + (.I0(pDataInBnd[6]), + .I1(pDataInBnd[5]), + .I2(pDataInBnd[4]), + .I3(pDataInBnd[3]), + .I4(pDataInBnd[7]), + .I5(pDataInBnd[8]), + .O(pTokenFlag_i_3_n_0)); + FDRE pTokenFlag_q_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pTokenFlag), + .Q(pTokenFlag_q), + .R(1'b0)); + FDRE pTokenFlag_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pTokenFlag0), + .Q(pTokenFlag), + .R(1'b0)); + LUT1 #( + .INIT(2'h1)) + \pWrA[0]_i_1 + (.I0(pWrA_reg__0[0]), + .O(p_0_in__0[0])); + (* SOFT_HLUTNM = "soft_lutpair59" *) + LUT2 #( + .INIT(4'h6)) + \pWrA[1]_i_1 + (.I0(pWrA_reg__0[0]), + .I1(pWrA_reg__0[1]), + .O(p_0_in__0[1])); + (* SOFT_HLUTNM = "soft_lutpair59" *) + LUT3 #( + .INIT(8'h78)) + \pWrA[2]_i_1 + (.I0(pWrA_reg__0[1]), + .I1(pWrA_reg__0[0]), + .I2(pWrA_reg__0[2]), + .O(p_0_in__0[2])); + (* SOFT_HLUTNM = "soft_lutpair54" *) + LUT4 #( + .INIT(16'h7F80)) + \pWrA[3]_i_1 + (.I0(pWrA_reg__0[0]), + .I1(pWrA_reg__0[1]), + .I2(pWrA_reg__0[2]), + .I3(pWrA_reg__0[3]), + .O(p_0_in__0[3])); + (* SOFT_HLUTNM = "soft_lutpair54" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \pWrA[4]_i_2 + (.I0(pWrA_reg__0[2]), + .I1(pWrA_reg__0[3]), + .I2(pWrA_reg__0[0]), + .I3(pWrA_reg__0[1]), + .I4(pWrA_reg__0[4]), + .O(p_0_in__0[4])); + FDRE \pWrA_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in__0[0]), + .Q(pWrA_reg__0[0]), + .R(pAligned_reg)); + FDRE \pWrA_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in__0[1]), + .Q(pWrA_reg__0[1]), + .R(pAligned_reg)); + FDRE \pWrA_reg[2] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in__0[2]), + .Q(pWrA_reg__0[2]), + .R(pAligned_reg)); + FDRE \pWrA_reg[3] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in__0[3]), + .Q(pWrA_reg__0[3]), + .R(pAligned_reg)); + FDRE \pWrA_reg[4] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in__0[4]), + .Q(pWrA_reg__0[4]), + .R(pAligned_reg)); +endmodule + +(* ORIG_REF_NAME = "ChannelBond" *) +module Arty_Z7_20_dvi2rgb_0_0_ChannelBond_10 + (pMeRdy_int_reg_0, + D, + \pDataIn_reg[7] , + PixelClk_int, + SR, + pRdy_2, + pRdy_0, + pAllVldBgnFlag, + pAllVld, + pDataInRaw); + output pMeRdy_int_reg_0; + output [7:0]D; + output [0:0]\pDataIn_reg[7] ; + input PixelClk_int; + input [0:0]SR; + input pRdy_2; + input pRdy_0; + input pAllVldBgnFlag; + input pAllVld; + input [9:0]pDataInRaw; + + wire [7:0]D; + wire PixelClk_int; + wire [0:0]SR; + wire pAllVld; + wire pAllVldBgnFlag; + wire pBlnkBgnFlag; + wire pBlnkBgnFlag_i_1__0_n_0; + wire \pDataFIFO_reg_n_0_[9] ; + wire [8:0]pDataInBnd; + wire [9:0]pDataInRaw; + wire \pDataIn[7]_i_3__0_n_0 ; + wire \pDataIn[7]_i_4__0_n_0 ; + wire [0:0]\pDataIn_reg[7] ; + wire pMeRdy_int_i_1__1_n_0; + wire pMeRdy_int_reg_0; + wire [4:0]pRdA; + wire \pRdA_rep[0]_i_1__1_n_0 ; + wire \pRdA_rep[1]_i_1__1_n_0 ; + wire \pRdA_rep[2]_i_1__1_n_0 ; + wire \pRdA_rep[3]_i_1__1_n_0 ; + wire \pRdA_rep[4]_i_1__1_n_0 ; + wire pRdEn; + wire pRdEn_i_1__0_n_0; + wire pRdy_0; + wire pRdy_2; + wire pTokenFlag; + wire pTokenFlag0; + wire pTokenFlag_i_2__0_n_0; + wire pTokenFlag_i_3__0_n_0; + wire pTokenFlag_q; + wire [4:0]pWrA_reg__0; + wire [4:0]p_0_in__0; + wire [9:0]p_0_out; + wire [1:0]NLW_pFIFO_reg_0_31_0_5_DOD_UNCONNECTED; + wire [1:0]NLW_pFIFO_reg_0_31_6_9_DOC_UNCONNECTED; + wire [1:0]NLW_pFIFO_reg_0_31_6_9_DOD_UNCONNECTED; + + LUT2 #( + .INIT(4'h2)) + pBlnkBgnFlag_i_1__0 + (.I0(pTokenFlag), + .I1(pTokenFlag_q), + .O(pBlnkBgnFlag_i_1__0_n_0)); + FDRE pBlnkBgnFlag_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pBlnkBgnFlag_i_1__0_n_0), + .Q(pBlnkBgnFlag), + .R(1'b0)); + FDRE \pDataFIFO_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_out[0]), + .Q(pDataInBnd[0]), + .R(1'b0)); + FDRE \pDataFIFO_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_out[1]), + .Q(pDataInBnd[1]), + .R(1'b0)); + FDRE \pDataFIFO_reg[2] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_out[2]), + .Q(pDataInBnd[2]), + .R(1'b0)); + FDRE \pDataFIFO_reg[3] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_out[3]), + .Q(pDataInBnd[3]), + .R(1'b0)); + FDRE \pDataFIFO_reg[4] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_out[4]), + .Q(pDataInBnd[4]), + .R(1'b0)); + FDRE \pDataFIFO_reg[5] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_out[5]), + .Q(pDataInBnd[5]), + .R(1'b0)); + FDRE \pDataFIFO_reg[6] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_out[6]), + .Q(pDataInBnd[6]), + .R(1'b0)); + FDRE \pDataFIFO_reg[7] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_out[7]), + .Q(pDataInBnd[7]), + .R(1'b0)); + FDRE \pDataFIFO_reg[8] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_out[8]), + .Q(pDataInBnd[8]), + .R(1'b0)); + FDRE \pDataFIFO_reg[9] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_out[9]), + .Q(\pDataFIFO_reg_n_0_[9] ), + .R(1'b0)); + LUT3 #( + .INIT(8'h60)) + \pDataIn[0]_i_1 + (.I0(\pDataFIFO_reg_n_0_[9] ), + .I1(pDataInBnd[0]), + .I2(\pDataIn[7]_i_3__0_n_0 ), + .O(D[0])); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT4 #( + .INIT(16'h6090)) + \pDataIn[1]_i_1 + (.I0(pDataInBnd[1]), + .I1(pDataInBnd[0]), + .I2(\pDataIn[7]_i_3__0_n_0 ), + .I3(pDataInBnd[8]), + .O(D[1])); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT4 #( + .INIT(16'h6090)) + \pDataIn[2]_i_1 + (.I0(pDataInBnd[2]), + .I1(pDataInBnd[1]), + .I2(\pDataIn[7]_i_3__0_n_0 ), + .I3(pDataInBnd[8]), + .O(D[2])); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT4 #( + .INIT(16'h6090)) + \pDataIn[3]_i_1 + (.I0(pDataInBnd[3]), + .I1(pDataInBnd[2]), + .I2(\pDataIn[7]_i_3__0_n_0 ), + .I3(pDataInBnd[8]), + .O(D[3])); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT4 #( + .INIT(16'h6090)) + \pDataIn[4]_i_1 + (.I0(pDataInBnd[4]), + .I1(pDataInBnd[3]), + .I2(\pDataIn[7]_i_3__0_n_0 ), + .I3(pDataInBnd[8]), + .O(D[4])); + LUT4 #( + .INIT(16'h6090)) + \pDataIn[5]_i_1 + (.I0(pDataInBnd[5]), + .I1(pDataInBnd[4]), + .I2(\pDataIn[7]_i_3__0_n_0 ), + .I3(pDataInBnd[8]), + .O(D[5])); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT4 #( + .INIT(16'h6090)) + \pDataIn[6]_i_1 + (.I0(pDataInBnd[6]), + .I1(pDataInBnd[5]), + .I2(\pDataIn[7]_i_3__0_n_0 ), + .I3(pDataInBnd[8]), + .O(D[6])); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT3 #( + .INIT(8'h7F)) + \pDataIn[7]_i_1 + (.I0(pMeRdy_int_reg_0), + .I1(pRdy_2), + .I2(pRdy_0), + .O(\pDataIn_reg[7] )); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT4 #( + .INIT(16'h6090)) + \pDataIn[7]_i_2 + (.I0(pDataInBnd[7]), + .I1(pDataInBnd[6]), + .I2(\pDataIn[7]_i_3__0_n_0 ), + .I3(pDataInBnd[8]), + .O(D[7])); + LUT6 #( + .INIT(64'hFFFFFFFFFFFBDFFF)) + \pDataIn[7]_i_3__0 + (.I0(pDataInBnd[5]), + .I1(pDataInBnd[4]), + .I2(pDataInBnd[3]), + .I3(pDataInBnd[7]), + .I4(pDataInBnd[6]), + .I5(\pDataIn[7]_i_4__0_n_0 ), + .O(\pDataIn[7]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hFBBFFFFFFFFFFDDF)) + \pDataIn[7]_i_4__0 + (.I0(pDataInBnd[2]), + .I1(pDataInBnd[3]), + .I2(pDataInBnd[7]), + .I3(pDataInBnd[8]), + .I4(pDataInBnd[0]), + .I5(pDataInBnd[1]), + .O(\pDataIn[7]_i_4__0_n_0 )); + (* METHODOLOGY_DRC_VIOS = "" *) + RAM32M pFIFO_reg_0_31_0_5 + (.ADDRA(pRdA), + .ADDRB(pRdA), + .ADDRC(pRdA), + .ADDRD(pWrA_reg__0), + .DIA(pDataInRaw[1:0]), + .DIB(pDataInRaw[3:2]), + .DIC(pDataInRaw[5:4]), + .DID({1'b0,1'b0}), + .DOA(p_0_out[1:0]), + .DOB(p_0_out[3:2]), + .DOC(p_0_out[5:4]), + .DOD(NLW_pFIFO_reg_0_31_0_5_DOD_UNCONNECTED[1:0]), + .WCLK(PixelClk_int), + .WE(pAllVld)); + (* METHODOLOGY_DRC_VIOS = "" *) + RAM32M pFIFO_reg_0_31_6_9 + (.ADDRA(pRdA), + .ADDRB(pRdA), + .ADDRC(pRdA), + .ADDRD(pWrA_reg__0), + .DIA(pDataInRaw[7:6]), + .DIB(pDataInRaw[9:8]), + .DIC({1'b0,1'b0}), + .DID({1'b0,1'b0}), + .DOA(p_0_out[7:6]), + .DOB(p_0_out[9:8]), + .DOC(NLW_pFIFO_reg_0_31_6_9_DOC_UNCONNECTED[1:0]), + .DOD(NLW_pFIFO_reg_0_31_6_9_DOD_UNCONNECTED[1:0]), + .WCLK(PixelClk_int), + .WE(pAllVld)); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT2 #( + .INIT(4'hE)) + pMeRdy_int_i_1__1 + (.I0(pBlnkBgnFlag), + .I1(pMeRdy_int_reg_0), + .O(pMeRdy_int_i_1__1_n_0)); + FDRE pMeRdy_int_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pMeRdy_int_i_1__1_n_0), + .Q(pMeRdy_int_reg_0), + .R(SR)); + FDRE \pRdA_reg_rep[0] + (.C(PixelClk_int), + .CE(pRdEn), + .D(\pRdA_rep[0]_i_1__1_n_0 ), + .Q(pRdA[0]), + .R(SR)); + FDRE \pRdA_reg_rep[1] + (.C(PixelClk_int), + .CE(pRdEn), + .D(\pRdA_rep[1]_i_1__1_n_0 ), + .Q(pRdA[1]), + .R(SR)); + FDRE \pRdA_reg_rep[2] + (.C(PixelClk_int), + .CE(pRdEn), + .D(\pRdA_rep[2]_i_1__1_n_0 ), + .Q(pRdA[2]), + .R(SR)); + FDRE \pRdA_reg_rep[3] + (.C(PixelClk_int), + .CE(pRdEn), + .D(\pRdA_rep[3]_i_1__1_n_0 ), + .Q(pRdA[3]), + .R(SR)); + FDRE \pRdA_reg_rep[4] + (.C(PixelClk_int), + .CE(pRdEn), + .D(\pRdA_rep[4]_i_1__1_n_0 ), + .Q(pRdA[4]), + .R(SR)); + LUT1 #( + .INIT(2'h1)) + \pRdA_rep[0]_i_1__1 + (.I0(pRdA[0]), + .O(\pRdA_rep[0]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT2 #( + .INIT(4'h6)) + \pRdA_rep[1]_i_1__1 + (.I0(pRdA[0]), + .I1(pRdA[1]), + .O(\pRdA_rep[1]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT3 #( + .INIT(8'h78)) + \pRdA_rep[2]_i_1__1 + (.I0(pRdA[1]), + .I1(pRdA[0]), + .I2(pRdA[2]), + .O(\pRdA_rep[2]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT4 #( + .INIT(16'h7F80)) + \pRdA_rep[3]_i_1__1 + (.I0(pRdA[0]), + .I1(pRdA[1]), + .I2(pRdA[2]), + .I3(pRdA[3]), + .O(\pRdA_rep[3]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \pRdA_rep[4]_i_1__1 + (.I0(pRdA[2]), + .I1(pRdA[3]), + .I2(pRdA[0]), + .I3(pRdA[1]), + .I4(pRdA[4]), + .O(\pRdA_rep[4]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hFBBBBBBBFAAAAAAA)) + pRdEn_i_1__0 + (.I0(pAllVldBgnFlag), + .I1(pBlnkBgnFlag), + .I2(pRdy_0), + .I3(pMeRdy_int_reg_0), + .I4(pRdy_2), + .I5(pRdEn), + .O(pRdEn_i_1__0_n_0)); + FDRE pRdEn_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pRdEn_i_1__0_n_0), + .Q(pRdEn), + .R(SR)); + LUT6 #( + .INIT(64'h5555DD5555F55555)) + pTokenFlag_i_1__0 + (.I0(pRdEn), + .I1(pTokenFlag_i_2__0_n_0), + .I2(pTokenFlag_i_3__0_n_0), + .I3(pDataInBnd[1]), + .I4(pDataInBnd[2]), + .I5(pDataInBnd[0]), + .O(pTokenFlag0)); + LUT6 #( + .INIT(64'h0000002000000000)) + pTokenFlag_i_2__0 + (.I0(pDataInBnd[5]), + .I1(pDataInBnd[6]), + .I2(pDataInBnd[3]), + .I3(pDataInBnd[4]), + .I4(pDataInBnd[8]), + .I5(pDataInBnd[7]), + .O(pTokenFlag_i_2__0_n_0)); + LUT6 #( + .INIT(64'h0000002000000000)) + pTokenFlag_i_3__0 + (.I0(pDataInBnd[6]), + .I1(pDataInBnd[5]), + .I2(pDataInBnd[4]), + .I3(pDataInBnd[3]), + .I4(pDataInBnd[7]), + .I5(pDataInBnd[8]), + .O(pTokenFlag_i_3__0_n_0)); + FDRE pTokenFlag_q_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pTokenFlag), + .Q(pTokenFlag_q), + .R(1'b0)); + FDRE pTokenFlag_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pTokenFlag0), + .Q(pTokenFlag), + .R(1'b0)); + LUT1 #( + .INIT(2'h1)) + \pWrA[0]_i_1__0 + (.I0(pWrA_reg__0[0]), + .O(p_0_in__0[0])); + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT2 #( + .INIT(4'h6)) + \pWrA[1]_i_1__0 + (.I0(pWrA_reg__0[0]), + .I1(pWrA_reg__0[1]), + .O(p_0_in__0[1])); + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT3 #( + .INIT(8'h78)) + \pWrA[2]_i_1__0 + (.I0(pWrA_reg__0[1]), + .I1(pWrA_reg__0[0]), + .I2(pWrA_reg__0[2]), + .O(p_0_in__0[2])); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT4 #( + .INIT(16'h7F80)) + \pWrA[3]_i_1__0 + (.I0(pWrA_reg__0[0]), + .I1(pWrA_reg__0[1]), + .I2(pWrA_reg__0[2]), + .I3(pWrA_reg__0[3]), + .O(p_0_in__0[3])); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \pWrA[4]_i_1__0 + (.I0(pWrA_reg__0[2]), + .I1(pWrA_reg__0[3]), + .I2(pWrA_reg__0[0]), + .I3(pWrA_reg__0[1]), + .I4(pWrA_reg__0[4]), + .O(p_0_in__0[4])); + FDRE \pWrA_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in__0[0]), + .Q(pWrA_reg__0[0]), + .R(SR)); + FDRE \pWrA_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in__0[1]), + .Q(pWrA_reg__0[1]), + .R(SR)); + FDRE \pWrA_reg[2] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in__0[2]), + .Q(pWrA_reg__0[2]), + .R(SR)); + FDRE \pWrA_reg[3] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in__0[3]), + .Q(pWrA_reg__0[3]), + .R(SR)); + FDRE \pWrA_reg[4] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in__0[4]), + .Q(pWrA_reg__0[4]), + .R(SR)); +endmodule + +(* ORIG_REF_NAME = "ChannelBond" *) +module Arty_Z7_20_dvi2rgb_0_0_ChannelBond_17 + (pMeRdy_int_reg_0, + pVde_0, + \pDataIn_reg[7] , + pC1_reg, + pC0_reg, + D, + PixelClk_int, + pAligned_reg, + pRdy_1, + pRdy_2, + pAllVldBgnFlag, + pC1, + pC0, + pAllVld, + pDataInRaw); + output pMeRdy_int_reg_0; + output pVde_0; + output [0:0]\pDataIn_reg[7] ; + output pC1_reg; + output pC0_reg; + output [7:0]D; + input PixelClk_int; + input pAligned_reg; + input pRdy_1; + input pRdy_2; + input pAllVldBgnFlag; + input pC1; + input pC0; + input pAllVld; + input [9:0]pDataInRaw; + + wire [7:0]D; + wire PixelClk_int; + wire pAligned_reg; + wire pAllVld; + wire pAllVldBgnFlag; + wire pBlnkBgnFlag; + wire pBlnkBgnFlag_i_1__1_n_0; + wire pC0; + wire pC0_1; + wire pC0_reg; + wire pC1; + wire pC1_reg; + wire \pDataFIFO_reg_n_0_[9] ; + wire [8:0]pDataInBnd; + wire [9:0]pDataInRaw; + wire \pDataIn[7]_i_3_n_0 ; + wire \pDataIn[7]_i_4_n_0 ; + wire [0:0]\pDataIn_reg[7] ; + wire pMeRdy_int_i_1__0_n_0; + wire pMeRdy_int_reg_0; + wire [4:0]pRdA; + wire \pRdA_rep[0]_i_1__0_n_0 ; + wire \pRdA_rep[1]_i_1__0_n_0 ; + wire \pRdA_rep[2]_i_1__0_n_0 ; + wire \pRdA_rep[3]_i_1__0_n_0 ; + wire \pRdA_rep[4]_i_1__0_n_0 ; + wire pRdEn; + wire pRdEn_i_1__1_n_0; + wire pRdy_1; + wire pRdy_2; + wire pTokenFlag; + wire pTokenFlag0; + wire pTokenFlag_i_3__1_n_0; + wire pTokenFlag_i_4_n_0; + wire pTokenFlag_q; + wire pVde_0; + wire [4:0]pWrA_reg__0; + wire [4:0]p_0_in__0; + wire [9:0]p_0_out; + wire [1:0]NLW_pFIFO_reg_0_31_0_5_DOD_UNCONNECTED; + wire [1:0]NLW_pFIFO_reg_0_31_6_9_DOC_UNCONNECTED; + wire [1:0]NLW_pFIFO_reg_0_31_6_9_DOD_UNCONNECTED; + + LUT2 #( + .INIT(4'h2)) + pBlnkBgnFlag_i_1__1 + (.I0(pTokenFlag), + .I1(pTokenFlag_q), + .O(pBlnkBgnFlag_i_1__1_n_0)); + FDRE pBlnkBgnFlag_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pBlnkBgnFlag_i_1__1_n_0), + .Q(pBlnkBgnFlag), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT3 #( + .INIT(8'h74)) + pC0_i_1 + (.I0(pDataInBnd[8]), + .I1(pC0_1), + .I2(pC0), + .O(pC0_reg)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'h6F60)) + pC1_i_1 + (.I0(\pDataFIFO_reg_n_0_[9] ), + .I1(pDataInBnd[8]), + .I2(pC0_1), + .I3(pC1), + .O(pC1_reg)); + FDRE \pDataFIFO_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_out[0]), + .Q(pDataInBnd[0]), + .R(1'b0)); + FDRE \pDataFIFO_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_out[1]), + .Q(pDataInBnd[1]), + .R(1'b0)); + FDRE \pDataFIFO_reg[2] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_out[2]), + .Q(pDataInBnd[2]), + .R(1'b0)); + FDRE \pDataFIFO_reg[3] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_out[3]), + .Q(pDataInBnd[3]), + .R(1'b0)); + FDRE \pDataFIFO_reg[4] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_out[4]), + .Q(pDataInBnd[4]), + .R(1'b0)); + FDRE \pDataFIFO_reg[5] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_out[5]), + .Q(pDataInBnd[5]), + .R(1'b0)); + FDRE \pDataFIFO_reg[6] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_out[6]), + .Q(pDataInBnd[6]), + .R(1'b0)); + FDRE \pDataFIFO_reg[7] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_out[7]), + .Q(pDataInBnd[7]), + .R(1'b0)); + FDRE \pDataFIFO_reg[8] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_out[8]), + .Q(pDataInBnd[8]), + .R(1'b0)); + FDRE \pDataFIFO_reg[9] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_out[9]), + .Q(\pDataFIFO_reg_n_0_[9] ), + .R(1'b0)); + LUT4 #( + .INIT(16'h0EE0)) + \pDataIn[0]_i_1__1 + (.I0(\pDataIn[7]_i_3_n_0 ), + .I1(\pDataIn[7]_i_4_n_0 ), + .I2(\pDataFIFO_reg_n_0_[9] ), + .I3(pDataInBnd[0]), + .O(D[0])); + LUT5 #( + .INIT(32'h0EE0E00E)) + \pDataIn[1]_i_1__1 + (.I0(\pDataIn[7]_i_3_n_0 ), + .I1(\pDataIn[7]_i_4_n_0 ), + .I2(pDataInBnd[1]), + .I3(pDataInBnd[0]), + .I4(pDataInBnd[8]), + .O(D[1])); + LUT5 #( + .INIT(32'h0EE0E00E)) + \pDataIn[2]_i_1__1 + (.I0(\pDataIn[7]_i_3_n_0 ), + .I1(\pDataIn[7]_i_4_n_0 ), + .I2(pDataInBnd[2]), + .I3(pDataInBnd[1]), + .I4(pDataInBnd[8]), + .O(D[2])); + LUT5 #( + .INIT(32'h0EE0E00E)) + \pDataIn[3]_i_1__1 + (.I0(\pDataIn[7]_i_3_n_0 ), + .I1(\pDataIn[7]_i_4_n_0 ), + .I2(pDataInBnd[3]), + .I3(pDataInBnd[2]), + .I4(pDataInBnd[8]), + .O(D[3])); + LUT5 #( + .INIT(32'h0EE0E00E)) + \pDataIn[4]_i_1__1 + (.I0(\pDataIn[7]_i_3_n_0 ), + .I1(\pDataIn[7]_i_4_n_0 ), + .I2(pDataInBnd[4]), + .I3(pDataInBnd[3]), + .I4(pDataInBnd[8]), + .O(D[4])); + LUT5 #( + .INIT(32'h0EE0E00E)) + \pDataIn[5]_i_1__1 + (.I0(\pDataIn[7]_i_3_n_0 ), + .I1(\pDataIn[7]_i_4_n_0 ), + .I2(pDataInBnd[5]), + .I3(pDataInBnd[4]), + .I4(pDataInBnd[8]), + .O(D[5])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h0EE0E00E)) + \pDataIn[6]_i_1__1 + (.I0(\pDataIn[7]_i_3_n_0 ), + .I1(\pDataIn[7]_i_4_n_0 ), + .I2(pDataInBnd[6]), + .I3(pDataInBnd[5]), + .I4(pDataInBnd[8]), + .O(D[6])); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h7F)) + \pDataIn[7]_i_1__1 + (.I0(pMeRdy_int_reg_0), + .I1(pRdy_1), + .I2(pRdy_2), + .O(\pDataIn_reg[7] )); + LUT5 #( + .INIT(32'h0EE0E00E)) + \pDataIn[7]_i_2__1 + (.I0(\pDataIn[7]_i_3_n_0 ), + .I1(\pDataIn[7]_i_4_n_0 ), + .I2(pDataInBnd[7]), + .I3(pDataInBnd[6]), + .I4(pDataInBnd[8]), + .O(D[7])); + LUT6 #( + .INIT(64'hFFFFBEFFFF7DFFFF)) + \pDataIn[7]_i_3 + (.I0(pDataInBnd[7]), + .I1(pDataInBnd[0]), + .I2(pDataInBnd[1]), + .I3(pDataInBnd[4]), + .I4(pDataInBnd[5]), + .I5(pDataInBnd[6]), + .O(\pDataIn[7]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFBBFFDDFFFFF)) + \pDataIn[7]_i_4 + (.I0(pDataInBnd[3]), + .I1(pDataInBnd[4]), + .I2(pDataInBnd[7]), + .I3(pDataInBnd[8]), + .I4(pDataInBnd[1]), + .I5(pDataInBnd[2]), + .O(\pDataIn[7]_i_4_n_0 )); + (* METHODOLOGY_DRC_VIOS = "" *) + RAM32M pFIFO_reg_0_31_0_5 + (.ADDRA(pRdA), + .ADDRB(pRdA), + .ADDRC(pRdA), + .ADDRD(pWrA_reg__0), + .DIA(pDataInRaw[1:0]), + .DIB(pDataInRaw[3:2]), + .DIC(pDataInRaw[5:4]), + .DID({1'b0,1'b0}), + .DOA(p_0_out[1:0]), + .DOB(p_0_out[3:2]), + .DOC(p_0_out[5:4]), + .DOD(NLW_pFIFO_reg_0_31_0_5_DOD_UNCONNECTED[1:0]), + .WCLK(PixelClk_int), + .WE(pAllVld)); + (* METHODOLOGY_DRC_VIOS = "" *) + RAM32M pFIFO_reg_0_31_6_9 + (.ADDRA(pRdA), + .ADDRB(pRdA), + .ADDRC(pRdA), + .ADDRD(pWrA_reg__0), + .DIA(pDataInRaw[7:6]), + .DIB(pDataInRaw[9:8]), + .DIC({1'b0,1'b0}), + .DID({1'b0,1'b0}), + .DOA(p_0_out[7:6]), + .DOB(p_0_out[9:8]), + .DOC(NLW_pFIFO_reg_0_31_6_9_DOC_UNCONNECTED[1:0]), + .DOD(NLW_pFIFO_reg_0_31_6_9_DOD_UNCONNECTED[1:0]), + .WCLK(PixelClk_int), + .WE(pAllVld)); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT2 #( + .INIT(4'hE)) + pMeRdy_int_i_1__0 + (.I0(pBlnkBgnFlag), + .I1(pMeRdy_int_reg_0), + .O(pMeRdy_int_i_1__0_n_0)); + FDRE pMeRdy_int_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pMeRdy_int_i_1__0_n_0), + .Q(pMeRdy_int_reg_0), + .R(pAligned_reg)); + FDRE \pRdA_reg_rep[0] + (.C(PixelClk_int), + .CE(pRdEn), + .D(\pRdA_rep[0]_i_1__0_n_0 ), + .Q(pRdA[0]), + .R(pAligned_reg)); + FDRE \pRdA_reg_rep[1] + (.C(PixelClk_int), + .CE(pRdEn), + .D(\pRdA_rep[1]_i_1__0_n_0 ), + .Q(pRdA[1]), + .R(pAligned_reg)); + FDRE \pRdA_reg_rep[2] + (.C(PixelClk_int), + .CE(pRdEn), + .D(\pRdA_rep[2]_i_1__0_n_0 ), + .Q(pRdA[2]), + .R(pAligned_reg)); + FDRE \pRdA_reg_rep[3] + (.C(PixelClk_int), + .CE(pRdEn), + .D(\pRdA_rep[3]_i_1__0_n_0 ), + .Q(pRdA[3]), + .R(pAligned_reg)); + FDRE \pRdA_reg_rep[4] + (.C(PixelClk_int), + .CE(pRdEn), + .D(\pRdA_rep[4]_i_1__0_n_0 ), + .Q(pRdA[4]), + .R(pAligned_reg)); + LUT1 #( + .INIT(2'h1)) + \pRdA_rep[0]_i_1__0 + (.I0(pRdA[0]), + .O(\pRdA_rep[0]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h6)) + \pRdA_rep[1]_i_1__0 + (.I0(pRdA[0]), + .I1(pRdA[1]), + .O(\pRdA_rep[1]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT3 #( + .INIT(8'h78)) + \pRdA_rep[2]_i_1__0 + (.I0(pRdA[1]), + .I1(pRdA[0]), + .I2(pRdA[2]), + .O(\pRdA_rep[2]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT4 #( + .INIT(16'h7F80)) + \pRdA_rep[3]_i_1__0 + (.I0(pRdA[0]), + .I1(pRdA[1]), + .I2(pRdA[2]), + .I3(pRdA[3]), + .O(\pRdA_rep[3]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \pRdA_rep[4]_i_1__0 + (.I0(pRdA[2]), + .I1(pRdA[3]), + .I2(pRdA[0]), + .I3(pRdA[1]), + .I4(pRdA[4]), + .O(\pRdA_rep[4]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hFBBBBBBBFAAAAAAA)) + pRdEn_i_1__1 + (.I0(pAllVldBgnFlag), + .I1(pBlnkBgnFlag), + .I2(pRdy_2), + .I3(pMeRdy_int_reg_0), + .I4(pRdy_1), + .I5(pRdEn), + .O(pRdEn_i_1__1_n_0)); + FDRE pRdEn_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pRdEn_i_1__1_n_0), + .Q(pRdEn), + .R(pAligned_reg)); + LUT2 #( + .INIT(4'hB)) + pTokenFlag_i_1__1 + (.I0(pC0_1), + .I1(pRdEn), + .O(pTokenFlag0)); + LUT5 #( + .INIT(32'h30080008)) + pTokenFlag_i_2__1 + (.I0(pTokenFlag_i_3__1_n_0), + .I1(pDataInBnd[2]), + .I2(pDataInBnd[1]), + .I3(pDataInBnd[0]), + .I4(pTokenFlag_i_4_n_0), + .O(pC0_1)); + LUT6 #( + .INIT(64'h0000002000000000)) + pTokenFlag_i_3__1 + (.I0(pDataInBnd[4]), + .I1(pDataInBnd[3]), + .I2(pDataInBnd[6]), + .I3(pDataInBnd[5]), + .I4(pDataInBnd[7]), + .I5(pDataInBnd[8]), + .O(pTokenFlag_i_3__1_n_0)); + LUT6 #( + .INIT(64'h0000002000000000)) + pTokenFlag_i_4 + (.I0(pDataInBnd[3]), + .I1(pDataInBnd[4]), + .I2(pDataInBnd[5]), + .I3(pDataInBnd[6]), + .I4(pDataInBnd[8]), + .I5(pDataInBnd[7]), + .O(pTokenFlag_i_4_n_0)); + FDRE pTokenFlag_q_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pTokenFlag), + .Q(pTokenFlag_q), + .R(1'b0)); + FDRE pTokenFlag_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pTokenFlag0), + .Q(pTokenFlag), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT2 #( + .INIT(4'hE)) + pVde_i_1 + (.I0(\pDataIn[7]_i_3_n_0 ), + .I1(\pDataIn[7]_i_4_n_0 ), + .O(pVde_0)); + LUT1 #( + .INIT(2'h1)) + \pWrA[0]_i_1__1 + (.I0(pWrA_reg__0[0]), + .O(p_0_in__0[0])); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h6)) + \pWrA[1]_i_1__1 + (.I0(pWrA_reg__0[0]), + .I1(pWrA_reg__0[1]), + .O(p_0_in__0[1])); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \pWrA[2]_i_1__1 + (.I0(pWrA_reg__0[1]), + .I1(pWrA_reg__0[0]), + .I2(pWrA_reg__0[2]), + .O(p_0_in__0[2])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT4 #( + .INIT(16'h7F80)) + \pWrA[3]_i_1__1 + (.I0(pWrA_reg__0[0]), + .I1(pWrA_reg__0[1]), + .I2(pWrA_reg__0[2]), + .I3(pWrA_reg__0[3]), + .O(p_0_in__0[3])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \pWrA[4]_i_1__1 + (.I0(pWrA_reg__0[2]), + .I1(pWrA_reg__0[3]), + .I2(pWrA_reg__0[0]), + .I3(pWrA_reg__0[1]), + .I4(pWrA_reg__0[4]), + .O(p_0_in__0[4])); + FDRE \pWrA_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in__0[0]), + .Q(pWrA_reg__0[0]), + .R(pAligned_reg)); + FDRE \pWrA_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in__0[1]), + .Q(pWrA_reg__0[1]), + .R(pAligned_reg)); + FDRE \pWrA_reg[2] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in__0[2]), + .Q(pWrA_reg__0[2]), + .R(pAligned_reg)); + FDRE \pWrA_reg[3] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in__0[3]), + .Q(pWrA_reg__0[3]), + .R(pAligned_reg)); + FDRE \pWrA_reg[4] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in__0[4]), + .Q(pWrA_reg__0[4]), + .R(pAligned_reg)); +endmodule + +(* ORIG_REF_NAME = "EEPROM_8b" *) +module Arty_Z7_20_dvi2rgb_0_0_EEPROM_8b + (DDC_SDA_T, + RefClk, + DDC_SDA_I, + DDC_SCL_I); + output DDC_SDA_T; + input RefClk; + input DDC_SDA_I; + input DDC_SCL_I; + + wire DDC_SCL_I; + wire DDC_SDA_I; + wire DDC_SDA_T; + wire I2C_SlaveController_n_10; + wire I2C_SlaveController_n_11; + wire I2C_SlaveController_n_2; + wire I2C_SlaveController_n_4; + wire I2C_SlaveController_n_5; + wire I2C_SlaveController_n_6; + wire I2C_SlaveController_n_7; + wire I2C_SlaveController_n_8; + wire I2C_SlaveController_n_9; + wire RefClk; + wire [6:0]sAddr; + wire [6:0]sAddr_0; + wire \sAddr_rep[3]_i_2_n_0 ; + wire \sAddr_rep[4]_i_2_n_0 ; + wire \sAddr_rep[6]_i_3_n_0 ; + wire [7:0]sI2C_DataOut; + wire \sI2C_DataOut[0]_i_2_n_0 ; + wire \sI2C_DataOut[0]_i_3_n_0 ; + wire \sI2C_DataOut[1]_i_2_n_0 ; + wire \sI2C_DataOut[1]_i_3_n_0 ; + wire \sI2C_DataOut[2]_i_2_n_0 ; + wire \sI2C_DataOut[2]_i_3_n_0 ; + wire \sI2C_DataOut[3]_i_2_n_0 ; + wire \sI2C_DataOut[3]_i_3_n_0 ; + wire \sI2C_DataOut[4]_i_2_n_0 ; + wire \sI2C_DataOut[4]_i_3_n_0 ; + wire \sI2C_DataOut[5]_i_2_n_0 ; + wire \sI2C_DataOut[5]_i_3_n_0 ; + wire \sI2C_DataOut[6]_i_2_n_0 ; + wire \sI2C_DataOut[6]_i_3_n_0 ; + wire \sI2C_DataOut[7]_i_2_n_0 ; + wire \sI2C_DataOut[7]_i_3_n_0 ; + wire \sI2C_DataOut_reg[0]_i_1_n_0 ; + wire \sI2C_DataOut_reg[1]_i_1_n_0 ; + wire \sI2C_DataOut_reg[2]_i_1_n_0 ; + wire \sI2C_DataOut_reg[3]_i_1_n_0 ; + wire \sI2C_DataOut_reg[4]_i_1_n_0 ; + wire \sI2C_DataOut_reg[5]_i_1_n_0 ; + wire \sI2C_DataOut_reg[6]_i_1_n_0 ; + wire \sI2C_DataOut_reg[7]_i_1_n_0 ; + wire sI2C_Done; + wire sI2C_End; + wire [1:0]sState; + wire \sState[0]_i_1_n_0 ; + wire \sState[1]_i_1_n_0 ; + + Arty_Z7_20_dvi2rgb_0_0_TWI_SlaveCtl I2C_SlaveController + (.D({I2C_SlaveController_n_5,I2C_SlaveController_n_6,I2C_SlaveController_n_7,I2C_SlaveController_n_8,I2C_SlaveController_n_9,I2C_SlaveController_n_10,I2C_SlaveController_n_11}), + .DDC_SCL_I(DDC_SCL_I), + .DDC_SDA_I(DDC_SDA_I), + .DDC_SDA_T(DDC_SDA_T), + .E(I2C_SlaveController_n_4), + .Q(sI2C_DataOut), + .RefClk(RefClk), + .rd_wrn_reg_0(I2C_SlaveController_n_2), + .\sAddr_reg[3] (\sAddr_rep[4]_i_2_n_0 ), + .\sAddr_reg[4] (\sAddr_rep[6]_i_3_n_0 ), + .\sAddr_reg[6] (sAddr), + .sI2C_Done(sI2C_Done), + .sI2C_End(sI2C_End), + .sState(sState), + .\sState_reg[0] (\sAddr_rep[3]_i_2_n_0 )); + FDRE \sAddr_reg[0] + (.C(RefClk), + .CE(I2C_SlaveController_n_4), + .D(I2C_SlaveController_n_11), + .Q(sAddr[0]), + .R(1'b0)); + FDRE \sAddr_reg[1] + (.C(RefClk), + .CE(I2C_SlaveController_n_4), + .D(I2C_SlaveController_n_10), + .Q(sAddr[1]), + .R(1'b0)); + FDRE \sAddr_reg[2] + (.C(RefClk), + .CE(I2C_SlaveController_n_4), + .D(I2C_SlaveController_n_9), + .Q(sAddr[2]), + .R(1'b0)); + FDRE \sAddr_reg[3] + (.C(RefClk), + .CE(I2C_SlaveController_n_4), + .D(I2C_SlaveController_n_8), + .Q(sAddr[3]), + .R(1'b0)); + FDRE \sAddr_reg[4] + (.C(RefClk), + .CE(I2C_SlaveController_n_4), + .D(I2C_SlaveController_n_7), + .Q(sAddr[4]), + .R(1'b0)); + FDRE \sAddr_reg[5] + (.C(RefClk), + .CE(I2C_SlaveController_n_4), + .D(I2C_SlaveController_n_6), + .Q(sAddr[5]), + .R(1'b0)); + FDRE \sAddr_reg[6] + (.C(RefClk), + .CE(I2C_SlaveController_n_4), + .D(I2C_SlaveController_n_5), + .Q(sAddr[6]), + .R(1'b0)); + (* equivalent_register_removal = "no" *) + FDRE \sAddr_reg_rep[0] + (.C(RefClk), + .CE(I2C_SlaveController_n_4), + .D(I2C_SlaveController_n_11), + .Q(sAddr_0[0]), + .R(1'b0)); + (* equivalent_register_removal = "no" *) + FDRE \sAddr_reg_rep[1] + (.C(RefClk), + .CE(I2C_SlaveController_n_4), + .D(I2C_SlaveController_n_10), + .Q(sAddr_0[1]), + .R(1'b0)); + (* equivalent_register_removal = "no" *) + FDRE \sAddr_reg_rep[2] + (.C(RefClk), + .CE(I2C_SlaveController_n_4), + .D(I2C_SlaveController_n_9), + .Q(sAddr_0[2]), + .R(1'b0)); + (* equivalent_register_removal = "no" *) + FDRE \sAddr_reg_rep[3] + (.C(RefClk), + .CE(I2C_SlaveController_n_4), + .D(I2C_SlaveController_n_8), + .Q(sAddr_0[3]), + .R(1'b0)); + (* equivalent_register_removal = "no" *) + FDRE \sAddr_reg_rep[4] + (.C(RefClk), + .CE(I2C_SlaveController_n_4), + .D(I2C_SlaveController_n_7), + .Q(sAddr_0[4]), + .R(1'b0)); + (* equivalent_register_removal = "no" *) + FDRE \sAddr_reg_rep[5] + (.C(RefClk), + .CE(I2C_SlaveController_n_4), + .D(I2C_SlaveController_n_6), + .Q(sAddr_0[5]), + .R(1'b0)); + (* equivalent_register_removal = "no" *) + FDRE \sAddr_reg_rep[6] + (.C(RefClk), + .CE(I2C_SlaveController_n_4), + .D(I2C_SlaveController_n_5), + .Q(sAddr_0[6]), + .R(1'b0)); + LUT2 #( + .INIT(4'h8)) + \sAddr_rep[3]_i_2 + (.I0(sState[0]), + .I1(sState[1]), + .O(\sAddr_rep[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair93" *) + LUT4 #( + .INIT(16'h8000)) + \sAddr_rep[4]_i_2 + (.I0(sAddr[3]), + .I1(sAddr[1]), + .I2(sAddr[0]), + .I3(sAddr[2]), + .O(\sAddr_rep[4]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair93" *) + LUT5 #( + .INIT(32'h80000000)) + \sAddr_rep[6]_i_3 + (.I0(sAddr[4]), + .I1(sAddr[2]), + .I2(sAddr[0]), + .I3(sAddr[1]), + .I4(sAddr[3]), + .O(\sAddr_rep[6]_i_3_n_0 )); + LUT6 #( + .INIT(64'h5191505554755126)) + \sI2C_DataOut[0]_i_2 + (.I0(sAddr_0[6]), + .I1(sAddr_0[0]), + .I2(sAddr_0[4]), + .I3(sAddr_0[5]), + .I4(sAddr_0[1]), + .I5(sAddr_0[2]), + .O(\sI2C_DataOut[0]_i_2_n_0 )); + LUT6 #( + .INIT(64'h010011114402A000)) + \sI2C_DataOut[0]_i_3 + (.I0(sAddr_0[6]), + .I1(sAddr_0[0]), + .I2(sAddr_0[2]), + .I3(sAddr_0[1]), + .I4(sAddr_0[4]), + .I5(sAddr_0[5]), + .O(\sI2C_DataOut[0]_i_3_n_0 )); + LUT6 #( + .INIT(64'h0129004700C50154)) + \sI2C_DataOut[1]_i_2 + (.I0(sAddr_0[6]), + .I1(sAddr_0[0]), + .I2(sAddr_0[4]), + .I3(sAddr_0[5]), + .I4(sAddr_0[1]), + .I5(sAddr_0[2]), + .O(\sI2C_DataOut[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'h9000104008414090)) + \sI2C_DataOut[1]_i_3 + (.I0(sAddr_0[6]), + .I1(sAddr_0[0]), + .I2(sAddr_0[4]), + .I3(sAddr_0[2]), + .I4(sAddr_0[1]), + .I5(sAddr_0[5]), + .O(\sI2C_DataOut[1]_i_3_n_0 )); + LUT6 #( + .INIT(64'h403900A501A50186)) + \sI2C_DataOut[2]_i_2 + (.I0(sAddr_0[6]), + .I1(sAddr_0[0]), + .I2(sAddr_0[4]), + .I3(sAddr_0[5]), + .I4(sAddr_0[1]), + .I5(sAddr_0[2]), + .O(\sI2C_DataOut[2]_i_2_n_0 )); + LUT6 #( + .INIT(64'h9100450600008884)) + \sI2C_DataOut[2]_i_3 + (.I0(sAddr_0[6]), + .I1(sAddr_0[0]), + .I2(sAddr_0[1]), + .I3(sAddr_0[2]), + .I4(sAddr_0[5]), + .I5(sAddr_0[4]), + .O(\sI2C_DataOut[2]_i_3_n_0 )); + LUT6 #( + .INIT(64'h40D90105018505E4)) + \sI2C_DataOut[3]_i_2 + (.I0(sAddr_0[6]), + .I1(sAddr_0[0]), + .I2(sAddr_0[4]), + .I3(sAddr_0[5]), + .I4(sAddr_0[1]), + .I5(sAddr_0[2]), + .O(\sI2C_DataOut[3]_i_2_n_0 )); + LUT6 #( + .INIT(64'hD100100012180074)) + \sI2C_DataOut[3]_i_3 + (.I0(sAddr_0[6]), + .I1(sAddr_0[0]), + .I2(sAddr_0[4]), + .I3(sAddr_0[2]), + .I4(sAddr_0[1]), + .I5(sAddr_0[5]), + .O(\sI2C_DataOut[3]_i_3_n_0 )); + LUT6 #( + .INIT(64'h41790067000D0046)) + \sI2C_DataOut[4]_i_2 + (.I0(sAddr_0[6]), + .I1(sAddr_0[0]), + .I2(sAddr_0[4]), + .I3(sAddr_0[5]), + .I4(sAddr_0[1]), + .I5(sAddr_0[2]), + .O(\sI2C_DataOut[4]_i_2_n_0 )); + LUT6 #( + .INIT(64'h0180510819004811)) + \sI2C_DataOut[4]_i_3 + (.I0(sAddr_0[6]), + .I1(sAddr_0[0]), + .I2(sAddr_0[5]), + .I3(sAddr_0[4]), + .I4(sAddr_0[2]), + .I5(sAddr_0[1]), + .O(\sI2C_DataOut[4]_i_3_n_0 )); + LUT6 #( + .INIT(64'h0141007504A500A4)) + \sI2C_DataOut[5]_i_2 + (.I0(sAddr_0[6]), + .I1(sAddr_0[0]), + .I2(sAddr_0[4]), + .I3(sAddr_0[5]), + .I4(sAddr_0[1]), + .I5(sAddr_0[2]), + .O(\sI2C_DataOut[5]_i_2_n_0 )); + LUT6 #( + .INIT(64'hC5004040626002D8)) + \sI2C_DataOut[5]_i_3 + (.I0(sAddr_0[6]), + .I1(sAddr_0[4]), + .I2(sAddr_0[0]), + .I3(sAddr_0[2]), + .I4(sAddr_0[1]), + .I5(sAddr_0[5]), + .O(\sI2C_DataOut[5]_i_3_n_0 )); + LUT6 #( + .INIT(64'h0000EAAA01041D76)) + \sI2C_DataOut[6]_i_2 + (.I0(sAddr_0[6]), + .I1(sAddr_0[0]), + .I2(sAddr_0[2]), + .I3(sAddr_0[1]), + .I4(sAddr_0[5]), + .I5(sAddr_0[4]), + .O(\sI2C_DataOut[6]_i_2_n_0 )); + LUT6 #( + .INIT(64'h940450450A580844)) + \sI2C_DataOut[6]_i_3 + (.I0(sAddr_0[6]), + .I1(sAddr_0[0]), + .I2(sAddr_0[4]), + .I3(sAddr_0[1]), + .I4(sAddr_0[2]), + .I5(sAddr_0[5]), + .O(\sI2C_DataOut[6]_i_3_n_0 )); + LUT6 #( + .INIT(64'h01010015000D0004)) + \sI2C_DataOut[7]_i_2 + (.I0(sAddr_0[6]), + .I1(sAddr_0[0]), + .I2(sAddr_0[4]), + .I3(sAddr_0[5]), + .I4(sAddr_0[1]), + .I5(sAddr_0[2]), + .O(\sI2C_DataOut[7]_i_2_n_0 )); + LUT6 #( + .INIT(64'h8400555514040804)) + \sI2C_DataOut[7]_i_3 + (.I0(sAddr_0[6]), + .I1(sAddr_0[0]), + .I2(sAddr_0[2]), + .I3(sAddr_0[1]), + .I4(sAddr_0[4]), + .I5(sAddr_0[5]), + .O(\sI2C_DataOut[7]_i_3_n_0 )); + FDRE \sI2C_DataOut_reg[0] + (.C(RefClk), + .CE(1'b1), + .D(\sI2C_DataOut_reg[0]_i_1_n_0 ), + .Q(sI2C_DataOut[0]), + .R(1'b0)); + MUXF7 \sI2C_DataOut_reg[0]_i_1 + (.I0(\sI2C_DataOut[0]_i_2_n_0 ), + .I1(\sI2C_DataOut[0]_i_3_n_0 ), + .O(\sI2C_DataOut_reg[0]_i_1_n_0 ), + .S(sAddr_0[3])); + FDRE \sI2C_DataOut_reg[1] + (.C(RefClk), + .CE(1'b1), + .D(\sI2C_DataOut_reg[1]_i_1_n_0 ), + .Q(sI2C_DataOut[1]), + .R(1'b0)); + MUXF7 \sI2C_DataOut_reg[1]_i_1 + (.I0(\sI2C_DataOut[1]_i_2_n_0 ), + .I1(\sI2C_DataOut[1]_i_3_n_0 ), + .O(\sI2C_DataOut_reg[1]_i_1_n_0 ), + .S(sAddr_0[3])); + FDRE \sI2C_DataOut_reg[2] + (.C(RefClk), + .CE(1'b1), + .D(\sI2C_DataOut_reg[2]_i_1_n_0 ), + .Q(sI2C_DataOut[2]), + .R(1'b0)); + MUXF7 \sI2C_DataOut_reg[2]_i_1 + (.I0(\sI2C_DataOut[2]_i_2_n_0 ), + .I1(\sI2C_DataOut[2]_i_3_n_0 ), + .O(\sI2C_DataOut_reg[2]_i_1_n_0 ), + .S(sAddr_0[3])); + FDRE \sI2C_DataOut_reg[3] + (.C(RefClk), + .CE(1'b1), + .D(\sI2C_DataOut_reg[3]_i_1_n_0 ), + .Q(sI2C_DataOut[3]), + .R(1'b0)); + MUXF7 \sI2C_DataOut_reg[3]_i_1 + (.I0(\sI2C_DataOut[3]_i_2_n_0 ), + .I1(\sI2C_DataOut[3]_i_3_n_0 ), + .O(\sI2C_DataOut_reg[3]_i_1_n_0 ), + .S(sAddr_0[3])); + FDRE \sI2C_DataOut_reg[4] + (.C(RefClk), + .CE(1'b1), + .D(\sI2C_DataOut_reg[4]_i_1_n_0 ), + .Q(sI2C_DataOut[4]), + .R(1'b0)); + MUXF7 \sI2C_DataOut_reg[4]_i_1 + (.I0(\sI2C_DataOut[4]_i_2_n_0 ), + .I1(\sI2C_DataOut[4]_i_3_n_0 ), + .O(\sI2C_DataOut_reg[4]_i_1_n_0 ), + .S(sAddr_0[3])); + FDRE \sI2C_DataOut_reg[5] + (.C(RefClk), + .CE(1'b1), + .D(\sI2C_DataOut_reg[5]_i_1_n_0 ), + .Q(sI2C_DataOut[5]), + .R(1'b0)); + MUXF7 \sI2C_DataOut_reg[5]_i_1 + (.I0(\sI2C_DataOut[5]_i_2_n_0 ), + .I1(\sI2C_DataOut[5]_i_3_n_0 ), + .O(\sI2C_DataOut_reg[5]_i_1_n_0 ), + .S(sAddr_0[3])); + FDRE \sI2C_DataOut_reg[6] + (.C(RefClk), + .CE(1'b1), + .D(\sI2C_DataOut_reg[6]_i_1_n_0 ), + .Q(sI2C_DataOut[6]), + .R(1'b0)); + MUXF7 \sI2C_DataOut_reg[6]_i_1 + (.I0(\sI2C_DataOut[6]_i_2_n_0 ), + .I1(\sI2C_DataOut[6]_i_3_n_0 ), + .O(\sI2C_DataOut_reg[6]_i_1_n_0 ), + .S(sAddr_0[3])); + FDRE \sI2C_DataOut_reg[7] + (.C(RefClk), + .CE(1'b1), + .D(\sI2C_DataOut_reg[7]_i_1_n_0 ), + .Q(sI2C_DataOut[7]), + .R(1'b0)); + MUXF7 \sI2C_DataOut_reg[7]_i_1 + (.I0(\sI2C_DataOut[7]_i_2_n_0 ), + .I1(\sI2C_DataOut[7]_i_3_n_0 ), + .O(\sI2C_DataOut_reg[7]_i_1_n_0 ), + .S(sAddr_0[3])); + (* SOFT_HLUTNM = "soft_lutpair92" *) + LUT4 #( + .INIT(16'h105C)) + \sState[0]_i_1 + (.I0(sI2C_End), + .I1(sI2C_Done), + .I2(sState[0]), + .I3(sState[1]), + .O(\sState[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair92" *) + LUT5 #( + .INIT(32'h33330050)) + \sState[1]_i_1 + (.I0(I2C_SlaveController_n_2), + .I1(sI2C_End), + .I2(sI2C_Done), + .I3(sState[0]), + .I4(sState[1]), + .O(\sState[1]_i_1_n_0 )); + FDRE \sState_reg[0] + (.C(RefClk), + .CE(1'b1), + .D(\sState[0]_i_1_n_0 ), + .Q(sState[0]), + .R(1'b0)); + FDRE \sState_reg[1] + (.C(RefClk), + .CE(1'b1), + .D(\sState[1]_i_1_n_0 ), + .Q(sState[1]), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "GlitchFilter" *) +module Arty_Z7_20_dvi2rgb_0_0_GlitchFilter + (\Filter.sOut_reg_0 , + dScl_reg, + out, + RefClk, + SS); + output \Filter.sOut_reg_0 ; + output dScl_reg; + input [0:0]out; + input RefClk; + input [0:0]SS; + + wire \Filter.cntPeriods[1]_i_1__0_n_0 ; + wire \Filter.cntPeriods[2]_i_1__0_n_0 ; + wire \Filter.cntPeriods[3]_i_2__0_n_0 ; + wire \Filter.cntPeriods[3]_i_3__0_n_0 ; + wire [3:0]\Filter.cntPeriods_reg__0 ; + wire \Filter.sOut_i_1__0_n_0 ; + wire \Filter.sOut_reg_0 ; + wire RefClk; + wire [0:0]SS; + wire dScl_reg; + wire [0:0]out; + wire [0:0]p_0_in__0; + + (* SOFT_HLUTNM = "soft_lutpair81" *) + LUT1 #( + .INIT(2'h1)) + \Filter.cntPeriods[0]_i_1__0 + (.I0(\Filter.cntPeriods_reg__0 [0]), + .O(p_0_in__0)); + (* SOFT_HLUTNM = "soft_lutpair82" *) + LUT2 #( + .INIT(4'h9)) + \Filter.cntPeriods[1]_i_1__0 + (.I0(\Filter.cntPeriods_reg__0 [0]), + .I1(\Filter.cntPeriods_reg__0 [1]), + .O(\Filter.cntPeriods[1]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair82" *) + LUT3 #( + .INIT(8'hE1)) + \Filter.cntPeriods[2]_i_1__0 + (.I0(\Filter.cntPeriods_reg__0 [1]), + .I1(\Filter.cntPeriods_reg__0 [0]), + .I2(\Filter.cntPeriods_reg__0 [2]), + .O(\Filter.cntPeriods[2]_i_1__0_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \Filter.cntPeriods[3]_i_2__0 + (.I0(\Filter.cntPeriods_reg__0 [1]), + .I1(\Filter.cntPeriods_reg__0 [0]), + .I2(\Filter.cntPeriods_reg__0 [2]), + .I3(\Filter.cntPeriods_reg__0 [3]), + .O(\Filter.cntPeriods[3]_i_2__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair81" *) + LUT4 #( + .INIT(16'hFE01)) + \Filter.cntPeriods[3]_i_3__0 + (.I0(\Filter.cntPeriods_reg__0 [2]), + .I1(\Filter.cntPeriods_reg__0 [0]), + .I2(\Filter.cntPeriods_reg__0 [1]), + .I3(\Filter.cntPeriods_reg__0 [3]), + .O(\Filter.cntPeriods[3]_i_3__0_n_0 )); + FDSE #( + .INIT(1'b1)) + \Filter.cntPeriods_reg[0] + (.C(RefClk), + .CE(\Filter.cntPeriods[3]_i_2__0_n_0 ), + .D(p_0_in__0), + .Q(\Filter.cntPeriods_reg__0 [0]), + .S(SS)); + FDRE #( + .INIT(1'b0)) + \Filter.cntPeriods_reg[1] + (.C(RefClk), + .CE(\Filter.cntPeriods[3]_i_2__0_n_0 ), + .D(\Filter.cntPeriods[1]_i_1__0_n_0 ), + .Q(\Filter.cntPeriods_reg__0 [1]), + .R(SS)); + FDRE #( + .INIT(1'b0)) + \Filter.cntPeriods_reg[2] + (.C(RefClk), + .CE(\Filter.cntPeriods[3]_i_2__0_n_0 ), + .D(\Filter.cntPeriods[2]_i_1__0_n_0 ), + .Q(\Filter.cntPeriods_reg__0 [2]), + .R(SS)); + FDSE #( + .INIT(1'b1)) + \Filter.cntPeriods_reg[3] + (.C(RefClk), + .CE(\Filter.cntPeriods[3]_i_2__0_n_0 ), + .D(\Filter.cntPeriods[3]_i_3__0_n_0 ), + .Q(\Filter.cntPeriods_reg__0 [3]), + .S(SS)); + FDRE \Filter.sIn_q_reg + (.C(RefClk), + .CE(1'b1), + .D(out), + .Q(\Filter.sOut_reg_0 ), + .R(1'b0)); + LUT6 #( + .INIT(64'hFFFFFFFE00000002)) + \Filter.sOut_i_1__0 + (.I0(\Filter.sOut_reg_0 ), + .I1(\Filter.cntPeriods_reg__0 [3]), + .I2(\Filter.cntPeriods_reg__0 [2]), + .I3(\Filter.cntPeriods_reg__0 [0]), + .I4(\Filter.cntPeriods_reg__0 [1]), + .I5(dScl_reg), + .O(\Filter.sOut_i_1__0_n_0 )); + FDRE \Filter.sOut_reg + (.C(RefClk), + .CE(1'b1), + .D(\Filter.sOut_i_1__0_n_0 ), + .Q(dScl_reg), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "GlitchFilter" *) +module Arty_Z7_20_dvi2rgb_0_0_GlitchFilter_6 + (sIn_q, + sOut, + out, + RefClk, + SS); + output sIn_q; + output sOut; + input [0:0]out; + input RefClk; + input [0:0]SS; + + wire \Filter.cntPeriods[1]_i_1_n_0 ; + wire \Filter.cntPeriods[2]_i_1_n_0 ; + wire \Filter.cntPeriods[3]_i_2_n_0 ; + wire \Filter.cntPeriods[3]_i_3_n_0 ; + wire [3:0]\Filter.cntPeriods_reg__0 ; + wire \Filter.sOut_i_1_n_0 ; + wire RefClk; + wire [0:0]SS; + wire [0:0]out; + wire [0:0]p_0_in; + wire sIn_q; + wire sOut; + + (* SOFT_HLUTNM = "soft_lutpair83" *) + LUT1 #( + .INIT(2'h1)) + \Filter.cntPeriods[0]_i_1 + (.I0(\Filter.cntPeriods_reg__0 [0]), + .O(p_0_in)); + (* SOFT_HLUTNM = "soft_lutpair84" *) + LUT2 #( + .INIT(4'h9)) + \Filter.cntPeriods[1]_i_1 + (.I0(\Filter.cntPeriods_reg__0 [0]), + .I1(\Filter.cntPeriods_reg__0 [1]), + .O(\Filter.cntPeriods[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair84" *) + LUT3 #( + .INIT(8'hE1)) + \Filter.cntPeriods[2]_i_1 + (.I0(\Filter.cntPeriods_reg__0 [1]), + .I1(\Filter.cntPeriods_reg__0 [0]), + .I2(\Filter.cntPeriods_reg__0 [2]), + .O(\Filter.cntPeriods[2]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \Filter.cntPeriods[3]_i_2 + (.I0(\Filter.cntPeriods_reg__0 [1]), + .I1(\Filter.cntPeriods_reg__0 [0]), + .I2(\Filter.cntPeriods_reg__0 [2]), + .I3(\Filter.cntPeriods_reg__0 [3]), + .O(\Filter.cntPeriods[3]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair83" *) + LUT4 #( + .INIT(16'hFE01)) + \Filter.cntPeriods[3]_i_3 + (.I0(\Filter.cntPeriods_reg__0 [2]), + .I1(\Filter.cntPeriods_reg__0 [0]), + .I2(\Filter.cntPeriods_reg__0 [1]), + .I3(\Filter.cntPeriods_reg__0 [3]), + .O(\Filter.cntPeriods[3]_i_3_n_0 )); + FDSE #( + .INIT(1'b1)) + \Filter.cntPeriods_reg[0] + (.C(RefClk), + .CE(\Filter.cntPeriods[3]_i_2_n_0 ), + .D(p_0_in), + .Q(\Filter.cntPeriods_reg__0 [0]), + .S(SS)); + FDRE #( + .INIT(1'b0)) + \Filter.cntPeriods_reg[1] + (.C(RefClk), + .CE(\Filter.cntPeriods[3]_i_2_n_0 ), + .D(\Filter.cntPeriods[1]_i_1_n_0 ), + .Q(\Filter.cntPeriods_reg__0 [1]), + .R(SS)); + FDRE #( + .INIT(1'b0)) + \Filter.cntPeriods_reg[2] + (.C(RefClk), + .CE(\Filter.cntPeriods[3]_i_2_n_0 ), + .D(\Filter.cntPeriods[2]_i_1_n_0 ), + .Q(\Filter.cntPeriods_reg__0 [2]), + .R(SS)); + FDSE #( + .INIT(1'b1)) + \Filter.cntPeriods_reg[3] + (.C(RefClk), + .CE(\Filter.cntPeriods[3]_i_2_n_0 ), + .D(\Filter.cntPeriods[3]_i_3_n_0 ), + .Q(\Filter.cntPeriods_reg__0 [3]), + .S(SS)); + FDRE \Filter.sIn_q_reg + (.C(RefClk), + .CE(1'b1), + .D(out), + .Q(sIn_q), + .R(1'b0)); + LUT6 #( + .INIT(64'hFFFFFFFE00000002)) + \Filter.sOut_i_1 + (.I0(sIn_q), + .I1(\Filter.cntPeriods_reg__0 [3]), + .I2(\Filter.cntPeriods_reg__0 [2]), + .I3(\Filter.cntPeriods_reg__0 [0]), + .I4(\Filter.cntPeriods_reg__0 [1]), + .I5(sOut), + .O(\Filter.sOut_i_1_n_0 )); + FDRE \Filter.sOut_reg + (.C(RefClk), + .CE(1'b1), + .D(\Filter.sOut_i_1_n_0 ), + .Q(sOut), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "InputSERDES" *) +module Arty_Z7_20_dvi2rgb_0_0_InputSERDES + (D, + pDataInRaw, + TMDS_Data_p, + TMDS_Data_n, + PixelClk_int, + pIDLY_CE, + pIDLY_INC, + pIDLY_LD, + pBitslip, + \rMMCM_Reset_q_reg[0] , + CLKB, + out); + output [4:0]D; + output [9:0]pDataInRaw; + input [0:0]TMDS_Data_p; + input [0:0]TMDS_Data_n; + input PixelClk_int; + input pIDLY_CE; + input pIDLY_INC; + input pIDLY_LD; + input pBitslip; + input \rMMCM_Reset_q_reg[0] ; + input CLKB; + input [0:0]out; + + wire CLKB; + wire [4:0]D; + wire PixelClk_int; + wire [0:0]TMDS_Data_n; + wire [0:0]TMDS_Data_p; + wire icascade1; + wire icascade2; + wire [0:0]out; + wire pBitslip; + wire [9:0]pDataInRaw; + wire pIDLY_CE; + wire pIDLY_INC; + wire pIDLY_LD; + wire \rMMCM_Reset_q_reg[0] ; + wire sDataIn; + wire sDataInDly; + wire NLW_DeserializerMaster_O_UNCONNECTED; + wire NLW_DeserializerSlave_O_UNCONNECTED; + wire NLW_DeserializerSlave_Q1_UNCONNECTED; + wire NLW_DeserializerSlave_Q2_UNCONNECTED; + wire NLW_DeserializerSlave_Q5_UNCONNECTED; + wire NLW_DeserializerSlave_Q6_UNCONNECTED; + wire NLW_DeserializerSlave_Q7_UNCONNECTED; + wire NLW_DeserializerSlave_Q8_UNCONNECTED; + wire NLW_DeserializerSlave_SHIFTOUT1_UNCONNECTED; + wire NLW_DeserializerSlave_SHIFTOUT2_UNCONNECTED; + + (* box_type = "PRIMITIVE" *) + ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(10), + .DYN_CLKDIV_INV_EN("FALSE"), + .DYN_CLK_INV_EN("FALSE"), + .INIT_Q1(1'b0), + .INIT_Q2(1'b0), + .INIT_Q3(1'b0), + .INIT_Q4(1'b0), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .IS_CLKB_INVERTED(1'b1), + .IS_CLKDIVP_INVERTED(1'b0), + .IS_CLKDIV_INVERTED(1'b0), + .IS_CLK_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_OCLKB_INVERTED(1'b0), + .IS_OCLK_INVERTED(1'b0), + .NUM_CE(2), + .OFB_USED("FALSE"), + .SERDES_MODE("MASTER"), + .SRVAL_Q1(1'b0), + .SRVAL_Q2(1'b0), + .SRVAL_Q3(1'b0), + .SRVAL_Q4(1'b0)) + DeserializerMaster + (.BITSLIP(pBitslip), + .CE1(1'b1), + .CE2(1'b1), + .CLK(\rMMCM_Reset_q_reg[0] ), + .CLKB(CLKB), + .CLKDIV(PixelClk_int), + .CLKDIVP(1'b0), + .D(1'b0), + .DDLY(sDataInDly), + .DYNCLKDIVSEL(1'b0), + .DYNCLKSEL(1'b0), + .O(NLW_DeserializerMaster_O_UNCONNECTED), + .OCLK(1'b0), + .OCLKB(1'b0), + .OFB(1'b0), + .Q1(pDataInRaw[9]), + .Q2(pDataInRaw[8]), + .Q3(pDataInRaw[7]), + .Q4(pDataInRaw[6]), + .Q5(pDataInRaw[5]), + .Q6(pDataInRaw[4]), + .Q7(pDataInRaw[3]), + .Q8(pDataInRaw[2]), + .RST(out), + .SHIFTIN1(1'b0), + .SHIFTIN2(1'b0), + .SHIFTOUT1(icascade1), + .SHIFTOUT2(icascade2)); + (* box_type = "PRIMITIVE" *) + ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(10), + .DYN_CLKDIV_INV_EN("FALSE"), + .DYN_CLK_INV_EN("FALSE"), + .INIT_Q1(1'b0), + .INIT_Q2(1'b0), + .INIT_Q3(1'b0), + .INIT_Q4(1'b0), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .IS_CLKB_INVERTED(1'b1), + .IS_CLKDIVP_INVERTED(1'b0), + .IS_CLKDIV_INVERTED(1'b0), + .IS_CLK_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_OCLKB_INVERTED(1'b0), + .IS_OCLK_INVERTED(1'b0), + .NUM_CE(2), + .OFB_USED("FALSE"), + .SERDES_MODE("SLAVE"), + .SRVAL_Q1(1'b0), + .SRVAL_Q2(1'b0), + .SRVAL_Q3(1'b0), + .SRVAL_Q4(1'b0)) + DeserializerSlave + (.BITSLIP(pBitslip), + .CE1(1'b1), + .CE2(1'b1), + .CLK(\rMMCM_Reset_q_reg[0] ), + .CLKB(CLKB), + .CLKDIV(PixelClk_int), + .CLKDIVP(1'b0), + .D(1'b0), + .DDLY(1'b0), + .DYNCLKDIVSEL(1'b0), + .DYNCLKSEL(1'b0), + .O(NLW_DeserializerSlave_O_UNCONNECTED), + .OCLK(1'b0), + .OCLKB(1'b0), + .OFB(1'b0), + .Q1(NLW_DeserializerSlave_Q1_UNCONNECTED), + .Q2(NLW_DeserializerSlave_Q2_UNCONNECTED), + .Q3(pDataInRaw[1]), + .Q4(pDataInRaw[0]), + .Q5(NLW_DeserializerSlave_Q5_UNCONNECTED), + .Q6(NLW_DeserializerSlave_Q6_UNCONNECTED), + .Q7(NLW_DeserializerSlave_Q7_UNCONNECTED), + .Q8(NLW_DeserializerSlave_Q8_UNCONNECTED), + .RST(out), + .SHIFTIN1(icascade1), + .SHIFTIN2(icascade2), + .SHIFTOUT1(NLW_DeserializerSlave_SHIFTOUT1_UNCONNECTED), + .SHIFTOUT2(NLW_DeserializerSlave_SHIFTOUT2_UNCONNECTED)); + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + (* box_type = "PRIMITIVE" *) + IBUFDS #( + .DQS_BIAS("FALSE")) + InputBuffer + (.I(TMDS_Data_p), + .IB(TMDS_Data_n), + .O(sDataIn)); + (* box_type = "PRIMITIVE" *) + IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(0), + .IS_C_INVERTED(1'b0), + .IS_DATAIN_INVERTED(1'b0), + .IS_IDATAIN_INVERTED(1'b0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.000000), + .SIGNAL_PATTERN("DATA")) + InputDelay + (.C(PixelClk_int), + .CE(pIDLY_CE), + .CINVCTRL(1'b0), + .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), + .CNTVALUEOUT(D), + .DATAIN(1'b0), + .DATAOUT(sDataInDly), + .IDATAIN(sDataIn), + .INC(pIDLY_INC), + .LD(pIDLY_LD), + .LDPIPEEN(1'b0), + .REGRST(1'b0)); +endmodule + +(* ORIG_REF_NAME = "InputSERDES" *) +module Arty_Z7_20_dvi2rgb_0_0_InputSERDES_11 + (D, + pDataInRaw, + TMDS_Data_p, + TMDS_Data_n, + PixelClk_int, + pIDLY_CE, + pIDLY_INC, + pIDLY_LD, + pBitslip, + \rMMCM_Reset_q_reg[0] , + CLKB, + AS); + output [4:0]D; + output [9:0]pDataInRaw; + input [0:0]TMDS_Data_p; + input [0:0]TMDS_Data_n; + input PixelClk_int; + input pIDLY_CE; + input pIDLY_INC; + input pIDLY_LD; + input pBitslip; + input \rMMCM_Reset_q_reg[0] ; + input CLKB; + input [0:0]AS; + + wire [0:0]AS; + wire CLKB; + wire [4:0]D; + wire PixelClk_int; + wire [0:0]TMDS_Data_n; + wire [0:0]TMDS_Data_p; + wire icascade1; + wire icascade2; + wire pBitslip; + wire [9:0]pDataInRaw; + wire pIDLY_CE; + wire pIDLY_INC; + wire pIDLY_LD; + wire \rMMCM_Reset_q_reg[0] ; + wire sDataIn; + wire sDataInDly; + wire NLW_DeserializerMaster_O_UNCONNECTED; + wire NLW_DeserializerSlave_O_UNCONNECTED; + wire NLW_DeserializerSlave_Q1_UNCONNECTED; + wire NLW_DeserializerSlave_Q2_UNCONNECTED; + wire NLW_DeserializerSlave_Q5_UNCONNECTED; + wire NLW_DeserializerSlave_Q6_UNCONNECTED; + wire NLW_DeserializerSlave_Q7_UNCONNECTED; + wire NLW_DeserializerSlave_Q8_UNCONNECTED; + wire NLW_DeserializerSlave_SHIFTOUT1_UNCONNECTED; + wire NLW_DeserializerSlave_SHIFTOUT2_UNCONNECTED; + + (* box_type = "PRIMITIVE" *) + ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(10), + .DYN_CLKDIV_INV_EN("FALSE"), + .DYN_CLK_INV_EN("FALSE"), + .INIT_Q1(1'b0), + .INIT_Q2(1'b0), + .INIT_Q3(1'b0), + .INIT_Q4(1'b0), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .IS_CLKB_INVERTED(1'b1), + .IS_CLKDIVP_INVERTED(1'b0), + .IS_CLKDIV_INVERTED(1'b0), + .IS_CLK_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_OCLKB_INVERTED(1'b0), + .IS_OCLK_INVERTED(1'b0), + .NUM_CE(2), + .OFB_USED("FALSE"), + .SERDES_MODE("MASTER"), + .SRVAL_Q1(1'b0), + .SRVAL_Q2(1'b0), + .SRVAL_Q3(1'b0), + .SRVAL_Q4(1'b0)) + DeserializerMaster + (.BITSLIP(pBitslip), + .CE1(1'b1), + .CE2(1'b1), + .CLK(\rMMCM_Reset_q_reg[0] ), + .CLKB(CLKB), + .CLKDIV(PixelClk_int), + .CLKDIVP(1'b0), + .D(1'b0), + .DDLY(sDataInDly), + .DYNCLKDIVSEL(1'b0), + .DYNCLKSEL(1'b0), + .O(NLW_DeserializerMaster_O_UNCONNECTED), + .OCLK(1'b0), + .OCLKB(1'b0), + .OFB(1'b0), + .Q1(pDataInRaw[9]), + .Q2(pDataInRaw[8]), + .Q3(pDataInRaw[7]), + .Q4(pDataInRaw[6]), + .Q5(pDataInRaw[5]), + .Q6(pDataInRaw[4]), + .Q7(pDataInRaw[3]), + .Q8(pDataInRaw[2]), + .RST(AS), + .SHIFTIN1(1'b0), + .SHIFTIN2(1'b0), + .SHIFTOUT1(icascade1), + .SHIFTOUT2(icascade2)); + (* box_type = "PRIMITIVE" *) + ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(10), + .DYN_CLKDIV_INV_EN("FALSE"), + .DYN_CLK_INV_EN("FALSE"), + .INIT_Q1(1'b0), + .INIT_Q2(1'b0), + .INIT_Q3(1'b0), + .INIT_Q4(1'b0), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .IS_CLKB_INVERTED(1'b1), + .IS_CLKDIVP_INVERTED(1'b0), + .IS_CLKDIV_INVERTED(1'b0), + .IS_CLK_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_OCLKB_INVERTED(1'b0), + .IS_OCLK_INVERTED(1'b0), + .NUM_CE(2), + .OFB_USED("FALSE"), + .SERDES_MODE("SLAVE"), + .SRVAL_Q1(1'b0), + .SRVAL_Q2(1'b0), + .SRVAL_Q3(1'b0), + .SRVAL_Q4(1'b0)) + DeserializerSlave + (.BITSLIP(pBitslip), + .CE1(1'b1), + .CE2(1'b1), + .CLK(\rMMCM_Reset_q_reg[0] ), + .CLKB(CLKB), + .CLKDIV(PixelClk_int), + .CLKDIVP(1'b0), + .D(1'b0), + .DDLY(1'b0), + .DYNCLKDIVSEL(1'b0), + .DYNCLKSEL(1'b0), + .O(NLW_DeserializerSlave_O_UNCONNECTED), + .OCLK(1'b0), + .OCLKB(1'b0), + .OFB(1'b0), + .Q1(NLW_DeserializerSlave_Q1_UNCONNECTED), + .Q2(NLW_DeserializerSlave_Q2_UNCONNECTED), + .Q3(pDataInRaw[1]), + .Q4(pDataInRaw[0]), + .Q5(NLW_DeserializerSlave_Q5_UNCONNECTED), + .Q6(NLW_DeserializerSlave_Q6_UNCONNECTED), + .Q7(NLW_DeserializerSlave_Q7_UNCONNECTED), + .Q8(NLW_DeserializerSlave_Q8_UNCONNECTED), + .RST(AS), + .SHIFTIN1(icascade1), + .SHIFTIN2(icascade2), + .SHIFTOUT1(NLW_DeserializerSlave_SHIFTOUT1_UNCONNECTED), + .SHIFTOUT2(NLW_DeserializerSlave_SHIFTOUT2_UNCONNECTED)); + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + (* box_type = "PRIMITIVE" *) + IBUFDS #( + .DQS_BIAS("FALSE")) + InputBuffer + (.I(TMDS_Data_p), + .IB(TMDS_Data_n), + .O(sDataIn)); + (* box_type = "PRIMITIVE" *) + IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(0), + .IS_C_INVERTED(1'b0), + .IS_DATAIN_INVERTED(1'b0), + .IS_IDATAIN_INVERTED(1'b0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.000000), + .SIGNAL_PATTERN("DATA")) + InputDelay + (.C(PixelClk_int), + .CE(pIDLY_CE), + .CINVCTRL(1'b0), + .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), + .CNTVALUEOUT(D), + .DATAIN(1'b0), + .DATAOUT(sDataInDly), + .IDATAIN(sDataIn), + .INC(pIDLY_INC), + .LD(pIDLY_LD), + .LDPIPEEN(1'b0), + .REGRST(1'b0)); +endmodule + +(* ORIG_REF_NAME = "InputSERDES" *) +module Arty_Z7_20_dvi2rgb_0_0_InputSERDES_18 + (D, + pDataInRaw, + TMDS_Data_p, + TMDS_Data_n, + PixelClk_int, + pIDLY_CE, + pIDLY_INC, + pIDLY_LD, + pBitslip, + \rMMCM_Reset_q_reg[0] , + CLKB, + AS); + output [4:0]D; + output [9:0]pDataInRaw; + input [0:0]TMDS_Data_p; + input [0:0]TMDS_Data_n; + input PixelClk_int; + input pIDLY_CE; + input pIDLY_INC; + input pIDLY_LD; + input pBitslip; + input \rMMCM_Reset_q_reg[0] ; + input CLKB; + input [0:0]AS; + + wire [0:0]AS; + wire CLKB; + wire [4:0]D; + wire PixelClk_int; + wire [0:0]TMDS_Data_n; + wire [0:0]TMDS_Data_p; + wire icascade1; + wire icascade2; + wire pBitslip; + wire [9:0]pDataInRaw; + wire pIDLY_CE; + wire pIDLY_INC; + wire pIDLY_LD; + wire \rMMCM_Reset_q_reg[0] ; + wire sDataIn; + wire sDataInDly; + wire NLW_DeserializerMaster_O_UNCONNECTED; + wire NLW_DeserializerSlave_O_UNCONNECTED; + wire NLW_DeserializerSlave_Q1_UNCONNECTED; + wire NLW_DeserializerSlave_Q2_UNCONNECTED; + wire NLW_DeserializerSlave_Q5_UNCONNECTED; + wire NLW_DeserializerSlave_Q6_UNCONNECTED; + wire NLW_DeserializerSlave_Q7_UNCONNECTED; + wire NLW_DeserializerSlave_Q8_UNCONNECTED; + wire NLW_DeserializerSlave_SHIFTOUT1_UNCONNECTED; + wire NLW_DeserializerSlave_SHIFTOUT2_UNCONNECTED; + + (* box_type = "PRIMITIVE" *) + ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(10), + .DYN_CLKDIV_INV_EN("FALSE"), + .DYN_CLK_INV_EN("FALSE"), + .INIT_Q1(1'b0), + .INIT_Q2(1'b0), + .INIT_Q3(1'b0), + .INIT_Q4(1'b0), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .IS_CLKB_INVERTED(1'b1), + .IS_CLKDIVP_INVERTED(1'b0), + .IS_CLKDIV_INVERTED(1'b0), + .IS_CLK_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_OCLKB_INVERTED(1'b0), + .IS_OCLK_INVERTED(1'b0), + .NUM_CE(2), + .OFB_USED("FALSE"), + .SERDES_MODE("MASTER"), + .SRVAL_Q1(1'b0), + .SRVAL_Q2(1'b0), + .SRVAL_Q3(1'b0), + .SRVAL_Q4(1'b0)) + DeserializerMaster + (.BITSLIP(pBitslip), + .CE1(1'b1), + .CE2(1'b1), + .CLK(\rMMCM_Reset_q_reg[0] ), + .CLKB(CLKB), + .CLKDIV(PixelClk_int), + .CLKDIVP(1'b0), + .D(1'b0), + .DDLY(sDataInDly), + .DYNCLKDIVSEL(1'b0), + .DYNCLKSEL(1'b0), + .O(NLW_DeserializerMaster_O_UNCONNECTED), + .OCLK(1'b0), + .OCLKB(1'b0), + .OFB(1'b0), + .Q1(pDataInRaw[9]), + .Q2(pDataInRaw[8]), + .Q3(pDataInRaw[7]), + .Q4(pDataInRaw[6]), + .Q5(pDataInRaw[5]), + .Q6(pDataInRaw[4]), + .Q7(pDataInRaw[3]), + .Q8(pDataInRaw[2]), + .RST(AS), + .SHIFTIN1(1'b0), + .SHIFTIN2(1'b0), + .SHIFTOUT1(icascade1), + .SHIFTOUT2(icascade2)); + (* box_type = "PRIMITIVE" *) + ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(10), + .DYN_CLKDIV_INV_EN("FALSE"), + .DYN_CLK_INV_EN("FALSE"), + .INIT_Q1(1'b0), + .INIT_Q2(1'b0), + .INIT_Q3(1'b0), + .INIT_Q4(1'b0), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .IS_CLKB_INVERTED(1'b1), + .IS_CLKDIVP_INVERTED(1'b0), + .IS_CLKDIV_INVERTED(1'b0), + .IS_CLK_INVERTED(1'b0), + .IS_D_INVERTED(1'b0), + .IS_OCLKB_INVERTED(1'b0), + .IS_OCLK_INVERTED(1'b0), + .NUM_CE(2), + .OFB_USED("FALSE"), + .SERDES_MODE("SLAVE"), + .SRVAL_Q1(1'b0), + .SRVAL_Q2(1'b0), + .SRVAL_Q3(1'b0), + .SRVAL_Q4(1'b0)) + DeserializerSlave + (.BITSLIP(pBitslip), + .CE1(1'b1), + .CE2(1'b1), + .CLK(\rMMCM_Reset_q_reg[0] ), + .CLKB(CLKB), + .CLKDIV(PixelClk_int), + .CLKDIVP(1'b0), + .D(1'b0), + .DDLY(1'b0), + .DYNCLKDIVSEL(1'b0), + .DYNCLKSEL(1'b0), + .O(NLW_DeserializerSlave_O_UNCONNECTED), + .OCLK(1'b0), + .OCLKB(1'b0), + .OFB(1'b0), + .Q1(NLW_DeserializerSlave_Q1_UNCONNECTED), + .Q2(NLW_DeserializerSlave_Q2_UNCONNECTED), + .Q3(pDataInRaw[1]), + .Q4(pDataInRaw[0]), + .Q5(NLW_DeserializerSlave_Q5_UNCONNECTED), + .Q6(NLW_DeserializerSlave_Q6_UNCONNECTED), + .Q7(NLW_DeserializerSlave_Q7_UNCONNECTED), + .Q8(NLW_DeserializerSlave_Q8_UNCONNECTED), + .RST(AS), + .SHIFTIN1(icascade1), + .SHIFTIN2(icascade2), + .SHIFTOUT1(NLW_DeserializerSlave_SHIFTOUT1_UNCONNECTED), + .SHIFTOUT2(NLW_DeserializerSlave_SHIFTOUT2_UNCONNECTED)); + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + (* box_type = "PRIMITIVE" *) + IBUFDS #( + .DQS_BIAS("FALSE")) + InputBuffer + (.I(TMDS_Data_p), + .IB(TMDS_Data_n), + .O(sDataIn)); + (* box_type = "PRIMITIVE" *) + IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(0), + .IS_C_INVERTED(1'b0), + .IS_DATAIN_INVERTED(1'b0), + .IS_IDATAIN_INVERTED(1'b0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.000000), + .SIGNAL_PATTERN("DATA")) + InputDelay + (.C(PixelClk_int), + .CE(pIDLY_CE), + .CINVCTRL(1'b0), + .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}), + .CNTVALUEOUT(D), + .DATAIN(1'b0), + .DATAOUT(sDataInDly), + .IDATAIN(sDataIn), + .INC(pIDLY_INC), + .LD(pIDLY_LD), + .LDPIPEEN(1'b0), + .REGRST(1'b0)); +endmodule + +(* ORIG_REF_NAME = "PhaseAlign" *) +module Arty_Z7_20_dvi2rgb_0_0_PhaseAlign + (pIDLY_CE, + pIDLY_INC, + pIDLY_LD, + pVld_2, + pAlignErr_q_reg, + iIn_q_reg, + pAllVldBgnFlag0, + pBitslip_reg, + PixelClk_int, + out, + pVld_0, + pVld_1, + pAllVld_q, + pAlignErr_q, + D, + pIDLY_CE_reg_0, + SR); + output pIDLY_CE; + output pIDLY_INC; + output pIDLY_LD; + output pVld_2; + output pAlignErr_q_reg; + output iIn_q_reg; + output pAllVldBgnFlag0; + output pBitslip_reg; + input PixelClk_int; + input [0:0]out; + input pVld_0; + input pVld_1; + input pAllVld_q; + input pAlignErr_q; + input [8:0]D; + input [4:0]pIDLY_CE_reg_0; + input [0:0]SR; + + wire [8:0]D; + wire PixelClk_int; + wire [0:0]SR; + wire iIn_q_i_2_n_0; + wire iIn_q_i_3_n_0; + wire iIn_q_i_4_n_0; + wire iIn_q_i_5_n_0; + wire iIn_q_reg; + wire [0:0]out; + wire pAlignErr_q; + wire pAlignErr_q_reg; + wire pAligned; + wire pAllVldBgnFlag0; + wire pAllVld_q; + wire pBitslip_reg; + wire pBlankBegin; + wire pBlankBegin0; + wire \pCenterTap[0]_i_1_n_0 ; + wire \pCenterTap[1]_i_1_n_0 ; + wire \pCenterTap[2]_i_1_n_0 ; + wire \pCenterTap[3]_i_1_n_0 ; + wire \pCenterTap[3]_i_2_n_0 ; + wire \pCenterTap[4]_i_1_n_0 ; + wire \pCenterTap[5]_i_1_n_0 ; + wire \pCenterTap[5]_i_2_n_0 ; + wire \pCenterTap[5]_i_3_n_0 ; + wire \pCenterTap[5]_i_5_n_0 ; + wire \pCenterTap_reg_n_0_[0] ; + wire \pCenterTap_reg_n_0_[1] ; + wire \pCenterTap_reg_n_0_[2] ; + wire \pCenterTap_reg_n_0_[3] ; + wire \pCenterTap_reg_n_0_[4] ; + wire \pCenterTap_reg_n_0_[5] ; + wire \pCtlTknCnt[6]_i_3_n_0 ; + wire \pCtlTknCnt[6]_i_4_n_0 ; + wire [6:0]pCtlTknCnt_reg__0; + wire pCtlTknOvf_i_1_n_0; + wire pCtlTknOvf_i_2_n_0; + wire pCtlTknOvf_reg_n_0; + wire pCtlTknRst; + wire [8:0]pDataQ; + wire pDelayCenter; + wire pDelayCenter_i_1_n_0; + wire pDelayCenter_i_2_n_0; + wire pDelayOvf; + wire pDelayOvf_i_1_n_0; + wire [1:0]pDelayWaitCnt; + wire \pDelayWaitCnt[0]_i_1_n_0 ; + wire \pDelayWaitCnt[0]_i_2_n_0 ; + wire \pDelayWaitCnt[1]_i_1_n_0 ; + wire pDelayWaitOvf; + wire pDelayWaitOvf_i_1_n_0; + wire pDelayWaitOvf_i_2_n_0; + wire pDelayWaitOvf_i_3_n_0; + wire pError; + wire \pEyeOpenCnt[0]_i_1_n_0 ; + wire \pEyeOpenCnt[1]_i_1_n_0 ; + wire \pEyeOpenCnt[2]_i_1_n_0 ; + wire \pEyeOpenCnt[3]_i_1_n_0 ; + wire \pEyeOpenCnt[4]_i_1_n_0 ; + wire \pEyeOpenCnt[4]_i_2_n_0 ; + wire \pEyeOpenCnt[4]_i_3_n_0 ; + wire \pEyeOpenCnt_reg_n_0_[0] ; + wire \pEyeOpenCnt_reg_n_0_[1] ; + wire \pEyeOpenCnt_reg_n_0_[2] ; + wire \pEyeOpenCnt_reg_n_0_[3] ; + wire \pEyeOpenCnt_reg_n_0_[4] ; + wire pEyeOpenEn__5; + wire pEyeOpenRst; + wire pFoundEyeFlag; + wire pFoundEyeFlag_i_1_n_0; + wire pFoundEyeFlag_i_2_n_0; + wire pFoundEyeFlag_i_3_n_0; + wire pFoundEyeFlag_i_4_n_0; + wire pFoundJtrFlag; + wire pFoundJtrFlag_i_1_n_0; + wire pIDLY_CE; + wire pIDLY_CE_1; + wire [4:0]pIDLY_CE_reg_0; + wire \pIDLY_CNT_Q_reg_n_0_[0] ; + wire \pIDLY_CNT_Q_reg_n_0_[1] ; + wire \pIDLY_CNT_Q_reg_n_0_[2] ; + wire \pIDLY_CNT_Q_reg_n_0_[3] ; + wire \pIDLY_CNT_Q_reg_n_0_[4] ; + wire pIDLY_INC; + wire pIDLY_INC_i_1_n_0; + wire pIDLY_LD; + wire pIDLY_LD_0; + wire pIDLY_LD_i_2_n_0; + wire [10:0]pState; + wire pStateNxt__0_n_0; + wire pStateNxt__1_n_0; + wire pStateNxt__2_n_0; + wire pStateNxt__3_n_0; + wire pStateNxt__4; + wire pStateNxt_n_0; + wire \pState[0]_i_1_n_0 ; + wire \pState[10]_i_2_n_0 ; + wire \pState[10]_i_3_n_0 ; + wire \pState[10]_i_4_n_0 ; + wire \pState[10]_i_5_n_0 ; + wire \pState[10]_i_6_n_0 ; + wire \pState[1]_i_1_n_0 ; + wire \pState[2]_i_1_n_0 ; + wire \pState[3]_i_1_n_0 ; + wire \pState[4]_i_1_n_0 ; + wire \pState[5]_i_1_n_0 ; + wire \pState[5]_i_2_n_0 ; + wire \pState[6]_i_1_n_0 ; + wire \pState[7]_i_1_n_0 ; + wire \pState[8]_i_1_n_0 ; + wire \pState[9]_i_1_n_0 ; + wire pTknFlag; + wire pTknFlag0; + wire pTknFlagQ; + wire pTknFlag_i_2_n_0; + wire pTknFlag_i_3_n_0; + wire pVld_0; + wire pVld_1; + wire pVld_2; + wire [6:0]p_0_in; + wire p_2_in; + wire [5:4]plusOp__16; + + LUT6 #( + .INIT(64'hFFFFFFFEFFFEFFFF)) + iIn_q_i_1 + (.I0(iIn_q_i_2_n_0), + .I1(iIn_q_i_3_n_0), + .I2(iIn_q_i_4_n_0), + .I3(iIn_q_i_5_n_0), + .I4(pState[1]), + .I5(pState[2]), + .O(iIn_q_reg)); + (* SOFT_HLUTNM = "soft_lutpair67" *) + LUT3 #( + .INIT(8'hFE)) + iIn_q_i_2 + (.I0(pState[4]), + .I1(pState[0]), + .I2(pState[3]), + .O(iIn_q_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair69" *) + LUT2 #( + .INIT(4'hE)) + iIn_q_i_3 + (.I0(pState[6]), + .I1(pState[8]), + .O(iIn_q_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair75" *) + LUT2 #( + .INIT(4'hE)) + iIn_q_i_4 + (.I0(pState[9]), + .I1(pState[10]), + .O(iIn_q_i_4_n_0)); + (* SOFT_HLUTNM = "soft_lutpair78" *) + LUT2 #( + .INIT(4'hE)) + iIn_q_i_5 + (.I0(pState[5]), + .I1(pState[7]), + .O(iIn_q_i_5_n_0)); + (* SOFT_HLUTNM = "soft_lutpair71" *) + LUT4 #( + .INIT(16'h0004)) + pAligned_i_1 + (.I0(pState[2]), + .I1(pState[9]), + .I2(pState[10]), + .I3(\pCtlTknCnt[6]_i_3_n_0 ), + .O(pAligned)); + FDRE pAligned_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pAligned), + .Q(pVld_2), + .R(1'b0)); + LUT4 #( + .INIT(16'h0080)) + pAllVldBgnFlag_i_1 + (.I0(pVld_0), + .I1(pVld_2), + .I2(pVld_1), + .I3(pAllVld_q), + .O(pAllVldBgnFlag0)); + LUT2 #( + .INIT(4'h2)) + pBitslip_i_1 + (.I0(pAlignErr_q_reg), + .I1(pAlignErr_q), + .O(pBitslip_reg)); + LUT2 #( + .INIT(4'h2)) + pBlankBegin_i_1 + (.I0(pTknFlag), + .I1(pTknFlagQ), + .O(pBlankBegin0)); + FDRE pBlankBegin_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pBlankBegin0), + .Q(pBlankBegin), + .R(1'b0)); + LUT6 #( + .INIT(64'hAAAAAAA5AAAAAFBA)) + \pCenterTap[0]_i_1 + (.I0(\pCenterTap_reg_n_0_[0] ), + .I1(pFoundEyeFlag), + .I2(pState[4]), + .I3(pState[0]), + .I4(\pCenterTap[5]_i_3_n_0 ), + .I5(pState[3]), + .O(\pCenterTap[0]_i_1_n_0 )); + LUT5 #( + .INIT(32'hFF606060)) + \pCenterTap[1]_i_1 + (.I0(\pCenterTap_reg_n_0_[0] ), + .I1(\pCenterTap_reg_n_0_[1] ), + .I2(\pCenterTap[5]_i_5_n_0 ), + .I3(\pIDLY_CNT_Q_reg_n_0_[0] ), + .I4(pEyeOpenRst), + .O(\pCenterTap[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFF780078007800)) + \pCenterTap[2]_i_1 + (.I0(\pCenterTap_reg_n_0_[1] ), + .I1(\pCenterTap_reg_n_0_[0] ), + .I2(\pCenterTap_reg_n_0_[2] ), + .I3(\pCenterTap[5]_i_5_n_0 ), + .I4(\pIDLY_CNT_Q_reg_n_0_[1] ), + .I5(pEyeOpenRst), + .O(\pCenterTap[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFF780078007800)) + \pCenterTap[3]_i_1 + (.I0(\pCenterTap_reg_n_0_[2] ), + .I1(\pCenterTap[3]_i_2_n_0 ), + .I2(\pCenterTap_reg_n_0_[3] ), + .I3(\pCenterTap[5]_i_5_n_0 ), + .I4(\pIDLY_CNT_Q_reg_n_0_[2] ), + .I5(pEyeOpenRst), + .O(\pCenterTap[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair64" *) + LUT2 #( + .INIT(4'h8)) + \pCenterTap[3]_i_2 + (.I0(\pCenterTap_reg_n_0_[0] ), + .I1(\pCenterTap_reg_n_0_[1] ), + .O(\pCenterTap[3]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \pCenterTap[4]_i_1 + (.I0(plusOp__16[4]), + .I1(\pCenterTap[5]_i_5_n_0 ), + .I2(\pIDLY_CNT_Q_reg_n_0_[3] ), + .I3(pEyeOpenRst), + .O(\pCenterTap[4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair64" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \pCenterTap[4]_i_2 + (.I0(\pCenterTap_reg_n_0_[0] ), + .I1(\pCenterTap_reg_n_0_[1] ), + .I2(\pCenterTap_reg_n_0_[2] ), + .I3(\pCenterTap_reg_n_0_[3] ), + .I4(\pCenterTap_reg_n_0_[4] ), + .O(plusOp__16[4])); + LUT5 #( + .INIT(32'h00030034)) + \pCenterTap[5]_i_1 + (.I0(pFoundEyeFlag), + .I1(pState[4]), + .I2(pState[0]), + .I3(\pCenterTap[5]_i_3_n_0 ), + .I4(pState[3]), + .O(\pCenterTap[5]_i_1_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \pCenterTap[5]_i_2 + (.I0(plusOp__16[5]), + .I1(\pCenterTap[5]_i_5_n_0 ), + .I2(\pIDLY_CNT_Q_reg_n_0_[4] ), + .I3(pEyeOpenRst), + .O(\pCenterTap[5]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \pCenterTap[5]_i_3 + (.I0(pState[5]), + .I1(pState[7]), + .I2(pState[8]), + .I3(pState[6]), + .I4(pState[1]), + .I5(\pState[10]_i_3_n_0 ), + .O(\pCenterTap[5]_i_3_n_0 )); + LUT6 #( + .INIT(64'h7FFFFFFF80000000)) + \pCenterTap[5]_i_4 + (.I0(\pCenterTap_reg_n_0_[0] ), + .I1(\pCenterTap_reg_n_0_[1] ), + .I2(\pCenterTap_reg_n_0_[4] ), + .I3(\pCenterTap_reg_n_0_[3] ), + .I4(\pCenterTap_reg_n_0_[2] ), + .I5(\pCenterTap_reg_n_0_[5] ), + .O(plusOp__16[5])); + LUT6 #( + .INIT(64'hFFFFFFFEFFFAFFFF)) + \pCenterTap[5]_i_5 + (.I0(pState[3]), + .I1(pFoundEyeFlag), + .I2(pIDLY_LD_i_2_n_0), + .I3(\pState[10]_i_3_n_0 ), + .I4(pState[0]), + .I5(pState[4]), + .O(\pCenterTap[5]_i_5_n_0 )); + LUT6 #( + .INIT(64'h0000010000010100)) + \pCenterTap[5]_i_6 + (.I0(pState[3]), + .I1(pIDLY_LD_i_2_n_0), + .I2(\pState[10]_i_3_n_0 ), + .I3(pState[0]), + .I4(pState[4]), + .I5(pFoundEyeFlag), + .O(pEyeOpenRst)); + FDRE \pCenterTap_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(\pCenterTap[0]_i_1_n_0 ), + .Q(\pCenterTap_reg_n_0_[0] ), + .R(1'b0)); + FDRE \pCenterTap_reg[1] + (.C(PixelClk_int), + .CE(\pCenterTap[5]_i_1_n_0 ), + .D(\pCenterTap[1]_i_1_n_0 ), + .Q(\pCenterTap_reg_n_0_[1] ), + .R(1'b0)); + FDRE \pCenterTap_reg[2] + (.C(PixelClk_int), + .CE(\pCenterTap[5]_i_1_n_0 ), + .D(\pCenterTap[2]_i_1_n_0 ), + .Q(\pCenterTap_reg_n_0_[2] ), + .R(1'b0)); + FDRE \pCenterTap_reg[3] + (.C(PixelClk_int), + .CE(\pCenterTap[5]_i_1_n_0 ), + .D(\pCenterTap[3]_i_1_n_0 ), + .Q(\pCenterTap_reg_n_0_[3] ), + .R(1'b0)); + FDRE \pCenterTap_reg[4] + (.C(PixelClk_int), + .CE(\pCenterTap[5]_i_1_n_0 ), + .D(\pCenterTap[4]_i_1_n_0 ), + .Q(\pCenterTap_reg_n_0_[4] ), + .R(1'b0)); + FDRE \pCenterTap_reg[5] + (.C(PixelClk_int), + .CE(\pCenterTap[5]_i_1_n_0 ), + .D(\pCenterTap[5]_i_2_n_0 ), + .Q(\pCenterTap_reg_n_0_[5] ), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair79" *) + LUT1 #( + .INIT(2'h1)) + \pCtlTknCnt[0]_i_1 + (.I0(pCtlTknCnt_reg__0[0]), + .O(p_0_in[0])); + (* SOFT_HLUTNM = "soft_lutpair79" *) + LUT2 #( + .INIT(4'h6)) + \pCtlTknCnt[1]_i_1 + (.I0(pCtlTknCnt_reg__0[0]), + .I1(pCtlTknCnt_reg__0[1]), + .O(p_0_in[1])); + (* SOFT_HLUTNM = "soft_lutpair73" *) + LUT3 #( + .INIT(8'h78)) + \pCtlTknCnt[2]_i_1 + (.I0(pCtlTknCnt_reg__0[1]), + .I1(pCtlTknCnt_reg__0[0]), + .I2(pCtlTknCnt_reg__0[2]), + .O(p_0_in[2])); + (* SOFT_HLUTNM = "soft_lutpair73" *) + LUT4 #( + .INIT(16'h7F80)) + \pCtlTknCnt[3]_i_1 + (.I0(pCtlTknCnt_reg__0[2]), + .I1(pCtlTknCnt_reg__0[0]), + .I2(pCtlTknCnt_reg__0[1]), + .I3(pCtlTknCnt_reg__0[3]), + .O(p_0_in[3])); + (* SOFT_HLUTNM = "soft_lutpair66" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \pCtlTknCnt[4]_i_1 + (.I0(pCtlTknCnt_reg__0[3]), + .I1(pCtlTknCnt_reg__0[1]), + .I2(pCtlTknCnt_reg__0[0]), + .I3(pCtlTknCnt_reg__0[2]), + .I4(pCtlTknCnt_reg__0[4]), + .O(p_0_in[4])); + LUT6 #( + .INIT(64'h7FFFFFFF80000000)) + \pCtlTknCnt[5]_i_1 + (.I0(pCtlTknCnt_reg__0[4]), + .I1(pCtlTknCnt_reg__0[2]), + .I2(pCtlTknCnt_reg__0[0]), + .I3(pCtlTknCnt_reg__0[1]), + .I4(pCtlTknCnt_reg__0[3]), + .I5(pCtlTknCnt_reg__0[5]), + .O(p_0_in[5])); + LUT4 #( + .INIT(16'hFFFD)) + \pCtlTknCnt[6]_i_1 + (.I0(pState[2]), + .I1(pState[9]), + .I2(pState[10]), + .I3(\pCtlTknCnt[6]_i_3_n_0 ), + .O(pCtlTknRst)); + (* SOFT_HLUTNM = "soft_lutpair72" *) + LUT4 #( + .INIT(16'h7F80)) + \pCtlTknCnt[6]_i_2 + (.I0(\pCtlTknCnt[6]_i_4_n_0 ), + .I1(pCtlTknCnt_reg__0[4]), + .I2(pCtlTknCnt_reg__0[5]), + .I3(pCtlTknCnt_reg__0[6]), + .O(p_0_in[6])); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \pCtlTknCnt[6]_i_3 + (.I0(iIn_q_i_2_n_0), + .I1(pState[5]), + .I2(pState[7]), + .I3(pState[8]), + .I4(pState[6]), + .I5(pState[1]), + .O(\pCtlTknCnt[6]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair66" *) + LUT4 #( + .INIT(16'h8000)) + \pCtlTknCnt[6]_i_4 + (.I0(pCtlTknCnt_reg__0[2]), + .I1(pCtlTknCnt_reg__0[0]), + .I2(pCtlTknCnt_reg__0[1]), + .I3(pCtlTknCnt_reg__0[3]), + .O(\pCtlTknCnt[6]_i_4_n_0 )); + FDRE \pCtlTknCnt_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in[0]), + .Q(pCtlTknCnt_reg__0[0]), + .R(pCtlTknRst)); + FDRE \pCtlTknCnt_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in[1]), + .Q(pCtlTknCnt_reg__0[1]), + .R(pCtlTknRst)); + FDRE \pCtlTknCnt_reg[2] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in[2]), + .Q(pCtlTknCnt_reg__0[2]), + .R(pCtlTknRst)); + FDRE \pCtlTknCnt_reg[3] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in[3]), + .Q(pCtlTknCnt_reg__0[3]), + .R(pCtlTknRst)); + FDRE \pCtlTknCnt_reg[4] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in[4]), + .Q(pCtlTknCnt_reg__0[4]), + .R(pCtlTknRst)); + FDRE \pCtlTknCnt_reg[5] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in[5]), + .Q(pCtlTknCnt_reg__0[5]), + .R(pCtlTknRst)); + FDRE \pCtlTknCnt_reg[6] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in[6]), + .Q(pCtlTknCnt_reg__0[6]), + .R(pCtlTknRst)); + LUT6 #( + .INIT(64'hAAAAAAAEAAAAAAA2)) + pCtlTknOvf_i_1 + (.I0(pCtlTknOvf_reg_n_0), + .I1(pState[2]), + .I2(pState[9]), + .I3(pState[10]), + .I4(\pCtlTknCnt[6]_i_3_n_0 ), + .I5(pCtlTknOvf_i_2_n_0), + .O(pCtlTknOvf_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair72" *) + LUT4 #( + .INIT(16'h8000)) + pCtlTknOvf_i_2 + (.I0(pCtlTknCnt_reg__0[4]), + .I1(pCtlTknCnt_reg__0[5]), + .I2(pCtlTknCnt_reg__0[6]), + .I3(\pCtlTknCnt[6]_i_4_n_0 ), + .O(pCtlTknOvf_i_2_n_0)); + FDRE pCtlTknOvf_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pCtlTknOvf_i_1_n_0), + .Q(pCtlTknOvf_reg_n_0), + .R(1'b0)); + FDRE \pDataQ_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(D[0]), + .Q(pDataQ[0]), + .R(1'b0)); + FDRE \pDataQ_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .D(D[1]), + .Q(pDataQ[1]), + .R(1'b0)); + FDRE \pDataQ_reg[2] + (.C(PixelClk_int), + .CE(1'b1), + .D(D[2]), + .Q(pDataQ[2]), + .R(1'b0)); + FDRE \pDataQ_reg[3] + (.C(PixelClk_int), + .CE(1'b1), + .D(D[3]), + .Q(pDataQ[3]), + .R(1'b0)); + FDRE \pDataQ_reg[4] + (.C(PixelClk_int), + .CE(1'b1), + .D(D[4]), + .Q(pDataQ[4]), + .R(1'b0)); + FDRE \pDataQ_reg[5] + (.C(PixelClk_int), + .CE(1'b1), + .D(D[5]), + .Q(pDataQ[5]), + .R(1'b0)); + FDRE \pDataQ_reg[6] + (.C(PixelClk_int), + .CE(1'b1), + .D(D[6]), + .Q(pDataQ[6]), + .R(1'b0)); + FDRE \pDataQ_reg[7] + (.C(PixelClk_int), + .CE(1'b1), + .D(D[7]), + .Q(pDataQ[7]), + .R(1'b0)); + FDRE \pDataQ_reg[8] + (.C(PixelClk_int), + .CE(1'b1), + .D(D[8]), + .Q(pDataQ[8]), + .R(1'b0)); + LUT5 #( + .INIT(32'h82000082)) + pDelayCenter_i_1 + (.I0(pDelayCenter_i_2_n_0), + .I1(\pCenterTap_reg_n_0_[5] ), + .I2(\pIDLY_CNT_Q_reg_n_0_[4] ), + .I3(\pCenterTap_reg_n_0_[4] ), + .I4(\pIDLY_CNT_Q_reg_n_0_[3] ), + .O(pDelayCenter_i_1_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + pDelayCenter_i_2 + (.I0(\pCenterTap_reg_n_0_[3] ), + .I1(\pIDLY_CNT_Q_reg_n_0_[2] ), + .I2(\pCenterTap_reg_n_0_[2] ), + .I3(\pIDLY_CNT_Q_reg_n_0_[1] ), + .I4(\pIDLY_CNT_Q_reg_n_0_[0] ), + .I5(\pCenterTap_reg_n_0_[1] ), + .O(pDelayCenter_i_2_n_0)); + FDRE pDelayCenter_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pDelayCenter_i_1_n_0), + .Q(pDelayCenter), + .R(1'b0)); + LUT5 #( + .INIT(32'h00000001)) + pDelayOvf_i_1 + (.I0(\pIDLY_CNT_Q_reg_n_0_[0] ), + .I1(\pIDLY_CNT_Q_reg_n_0_[1] ), + .I2(\pIDLY_CNT_Q_reg_n_0_[2] ), + .I3(\pIDLY_CNT_Q_reg_n_0_[4] ), + .I4(\pIDLY_CNT_Q_reg_n_0_[3] ), + .O(pDelayOvf_i_1_n_0)); + FDRE pDelayOvf_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pDelayOvf_i_1_n_0), + .Q(pDelayOvf), + .R(1'b0)); + LUT6 #( + .INIT(64'h0000001400000000)) + \pDelayWaitCnt[0]_i_1 + (.I0(pDelayWaitCnt[0]), + .I1(pState[6]), + .I2(pState[8]), + .I3(iIn_q_i_5_n_0), + .I4(pState[1]), + .I5(\pDelayWaitCnt[0]_i_2_n_0 ), + .O(\pDelayWaitCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000000000000001)) + \pDelayWaitCnt[0]_i_2 + (.I0(pState[3]), + .I1(pState[0]), + .I2(pState[4]), + .I3(pState[2]), + .I4(pState[9]), + .I5(pState[10]), + .O(\pDelayWaitCnt[0]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair74" *) + LUT3 #( + .INIT(8'h60)) + \pDelayWaitCnt[1]_i_1 + (.I0(pDelayWaitCnt[1]), + .I1(pDelayWaitCnt[0]), + .I2(p_2_in), + .O(\pDelayWaitCnt[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000000600000000)) + \pDelayWaitCnt[1]_i_2 + (.I0(pState[6]), + .I1(pState[8]), + .I2(pState[7]), + .I3(pState[5]), + .I4(pState[1]), + .I5(\pDelayWaitCnt[0]_i_2_n_0 ), + .O(p_2_in)); + FDRE \pDelayWaitCnt_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(\pDelayWaitCnt[0]_i_1_n_0 ), + .Q(pDelayWaitCnt[0]), + .R(1'b0)); + FDRE \pDelayWaitCnt_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .D(\pDelayWaitCnt[1]_i_1_n_0 ), + .Q(pDelayWaitCnt[1]), + .R(1'b0)); + LUT6 #( + .INIT(64'hCCFCCCCCCC8CCCCC)) + pDelayWaitOvf_i_1 + (.I0(pState[1]), + .I1(pDelayWaitOvf), + .I2(\pDelayWaitCnt[0]_i_2_n_0 ), + .I3(iIn_q_i_5_n_0), + .I4(pDelayWaitOvf_i_2_n_0), + .I5(pDelayWaitOvf_i_3_n_0), + .O(pDelayWaitOvf_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair76" *) + LUT2 #( + .INIT(4'h6)) + pDelayWaitOvf_i_2 + (.I0(pState[6]), + .I1(pState[8]), + .O(pDelayWaitOvf_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair74" *) + LUT3 #( + .INIT(8'h04)) + pDelayWaitOvf_i_3 + (.I0(pState[1]), + .I1(pDelayWaitCnt[1]), + .I2(pDelayWaitCnt[0]), + .O(pDelayWaitOvf_i_3_n_0)); + FDRE pDelayWaitOvf_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pDelayWaitOvf_i_1_n_0), + .Q(pDelayWaitOvf), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair71" *) + LUT4 #( + .INIT(16'h0004)) + pError_i_1 + (.I0(pState[2]), + .I1(pState[10]), + .I2(pState[9]), + .I3(\pCtlTknCnt[6]_i_3_n_0 ), + .O(pError)); + FDRE pError_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pError), + .Q(pAlignErr_q_reg), + .R(1'b0)); + LUT6 #( + .INIT(64'hCCCCCCCCCCC3C80C)) + \pEyeOpenCnt[0]_i_1 + (.I0(pFoundEyeFlag), + .I1(\pEyeOpenCnt_reg_n_0_[0] ), + .I2(pState[0]), + .I3(pState[4]), + .I4(pState[3]), + .I5(\pCenterTap[5]_i_3_n_0 ), + .O(\pEyeOpenCnt[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair61" *) + LUT4 #( + .INIT(16'hBCA0)) + \pEyeOpenCnt[1]_i_1 + (.I0(\pEyeOpenCnt[4]_i_2_n_0 ), + .I1(\pEyeOpenCnt_reg_n_0_[0] ), + .I2(\pEyeOpenCnt_reg_n_0_[1] ), + .I3(pEyeOpenEn__5), + .O(\pEyeOpenCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair61" *) + LUT5 #( + .INIT(32'hBFC0AA00)) + \pEyeOpenCnt[2]_i_1 + (.I0(\pEyeOpenCnt[4]_i_2_n_0 ), + .I1(\pEyeOpenCnt_reg_n_0_[1] ), + .I2(\pEyeOpenCnt_reg_n_0_[0] ), + .I3(\pEyeOpenCnt_reg_n_0_[2] ), + .I4(pEyeOpenEn__5), + .O(\pEyeOpenCnt[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBFFFC000AAAA0000)) + \pEyeOpenCnt[3]_i_1 + (.I0(\pEyeOpenCnt[4]_i_2_n_0 ), + .I1(\pEyeOpenCnt_reg_n_0_[0] ), + .I2(\pEyeOpenCnt_reg_n_0_[1] ), + .I3(\pEyeOpenCnt_reg_n_0_[2] ), + .I4(\pEyeOpenCnt_reg_n_0_[3] ), + .I5(pEyeOpenEn__5), + .O(\pEyeOpenCnt[3]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBFFFC000AAAA0000)) + \pEyeOpenCnt[4]_i_1 + (.I0(\pEyeOpenCnt[4]_i_2_n_0 ), + .I1(\pEyeOpenCnt_reg_n_0_[2] ), + .I2(\pEyeOpenCnt_reg_n_0_[3] ), + .I3(\pEyeOpenCnt[4]_i_3_n_0 ), + .I4(\pEyeOpenCnt_reg_n_0_[4] ), + .I5(pEyeOpenEn__5), + .O(\pEyeOpenCnt[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFEFFFCFFF3)) + \pEyeOpenCnt[4]_i_2 + (.I0(pFoundEyeFlag), + .I1(pState[3]), + .I2(pIDLY_LD_i_2_n_0), + .I3(\pState[10]_i_3_n_0 ), + .I4(pState[0]), + .I5(pState[4]), + .O(\pEyeOpenCnt[4]_i_2_n_0 )); + LUT2 #( + .INIT(4'h8)) + \pEyeOpenCnt[4]_i_3 + (.I0(\pEyeOpenCnt_reg_n_0_[0] ), + .I1(\pEyeOpenCnt_reg_n_0_[1] ), + .O(\pEyeOpenCnt[4]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair63" *) + LUT5 #( + .INIT(32'h00000010)) + \pEyeOpenCnt[4]_i_4 + (.I0(pState[0]), + .I1(pState[4]), + .I2(pState[3]), + .I3(\pState[10]_i_3_n_0 ), + .I4(pIDLY_LD_i_2_n_0), + .O(pEyeOpenEn__5)); + FDRE \pEyeOpenCnt_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(\pEyeOpenCnt[0]_i_1_n_0 ), + .Q(\pEyeOpenCnt_reg_n_0_[0] ), + .R(1'b0)); + FDRE \pEyeOpenCnt_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .D(\pEyeOpenCnt[1]_i_1_n_0 ), + .Q(\pEyeOpenCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE \pEyeOpenCnt_reg[2] + (.C(PixelClk_int), + .CE(1'b1), + .D(\pEyeOpenCnt[2]_i_1_n_0 ), + .Q(\pEyeOpenCnt_reg_n_0_[2] ), + .R(1'b0)); + FDRE \pEyeOpenCnt_reg[3] + (.C(PixelClk_int), + .CE(1'b1), + .D(\pEyeOpenCnt[3]_i_1_n_0 ), + .Q(\pEyeOpenCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE \pEyeOpenCnt_reg[4] + (.C(PixelClk_int), + .CE(1'b1), + .D(\pEyeOpenCnt[4]_i_1_n_0 ), + .Q(\pEyeOpenCnt_reg_n_0_[4] ), + .R(1'b0)); + LUT5 #( + .INIT(32'hABBBA888)) + pFoundEyeFlag_i_1 + (.I0(pFoundEyeFlag_i_2_n_0), + .I1(pIDLY_LD_0), + .I2(pEyeOpenEn__5), + .I3(pFoundEyeFlag_i_3_n_0), + .I4(pFoundEyeFlag), + .O(pFoundEyeFlag_i_1_n_0)); + LUT6 #( + .INIT(64'h1000004000000040)) + pFoundEyeFlag_i_2 + (.I0(pFoundEyeFlag_i_4_n_0), + .I1(\pEyeOpenCnt_reg_n_0_[4] ), + .I2(pState[3]), + .I3(\pEyeOpenCnt_reg_n_0_[0] ), + .I4(\pEyeOpenCnt_reg_n_0_[1] ), + .I5(pFoundJtrFlag), + .O(pFoundEyeFlag_i_2_n_0)); + LUT6 #( + .INIT(64'h0100001000000010)) + pFoundEyeFlag_i_3 + (.I0(\pEyeOpenCnt_reg_n_0_[2] ), + .I1(\pEyeOpenCnt_reg_n_0_[3] ), + .I2(\pEyeOpenCnt_reg_n_0_[4] ), + .I3(\pEyeOpenCnt_reg_n_0_[0] ), + .I4(\pEyeOpenCnt_reg_n_0_[1] ), + .I5(pFoundJtrFlag), + .O(pFoundEyeFlag_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair70" *) + LUT2 #( + .INIT(4'hE)) + pFoundEyeFlag_i_4 + (.I0(\pEyeOpenCnt_reg_n_0_[2] ), + .I1(\pEyeOpenCnt_reg_n_0_[3] ), + .O(pFoundEyeFlag_i_4_n_0)); + FDRE pFoundEyeFlag_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pFoundEyeFlag_i_1_n_0), + .Q(pFoundEyeFlag), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair67" *) + LUT5 #( + .INIT(32'hFEFF0010)) + pFoundJtrFlag_i_1 + (.I0(pState[3]), + .I1(\pCenterTap[5]_i_3_n_0 ), + .I2(pState[4]), + .I3(pState[0]), + .I4(pFoundJtrFlag), + .O(pFoundJtrFlag_i_1_n_0)); + FDRE pFoundJtrFlag_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pFoundJtrFlag_i_1_n_0), + .Q(pFoundJtrFlag), + .R(1'b0)); + LUT6 #( + .INIT(64'h0000000200020000)) + pIDLY_CE_i_1 + (.I0(\pDelayWaitCnt[0]_i_2_n_0 ), + .I1(pState[1]), + .I2(pState[6]), + .I3(pState[8]), + .I4(pState[5]), + .I5(pState[7]), + .O(pIDLY_CE_1)); + FDRE pIDLY_CE_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pIDLY_CE_1), + .Q(pIDLY_CE), + .R(1'b0)); + FDRE \pIDLY_CNT_Q_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(pIDLY_CE_reg_0[0]), + .Q(\pIDLY_CNT_Q_reg_n_0_[0] ), + .R(1'b0)); + FDRE \pIDLY_CNT_Q_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .D(pIDLY_CE_reg_0[1]), + .Q(\pIDLY_CNT_Q_reg_n_0_[1] ), + .R(1'b0)); + FDRE \pIDLY_CNT_Q_reg[2] + (.C(PixelClk_int), + .CE(1'b1), + .D(pIDLY_CE_reg_0[2]), + .Q(\pIDLY_CNT_Q_reg_n_0_[2] ), + .R(1'b0)); + FDRE \pIDLY_CNT_Q_reg[3] + (.C(PixelClk_int), + .CE(1'b1), + .D(pIDLY_CE_reg_0[3]), + .Q(\pIDLY_CNT_Q_reg_n_0_[3] ), + .R(1'b0)); + FDRE \pIDLY_CNT_Q_reg[4] + (.C(PixelClk_int), + .CE(1'b1), + .D(pIDLY_CE_reg_0[4]), + .Q(\pIDLY_CNT_Q_reg_n_0_[4] ), + .R(1'b0)); + LUT6 #( + .INIT(64'hAAAAAAA2AAAEAAAA)) + pIDLY_INC_i_1 + (.I0(pIDLY_INC), + .I1(\pDelayWaitCnt[0]_i_2_n_0 ), + .I2(pState[1]), + .I3(iIn_q_i_3_n_0), + .I4(pState[5]), + .I5(pState[7]), + .O(pIDLY_INC_i_1_n_0)); + FDRE pIDLY_INC_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pIDLY_INC_i_1_n_0), + .Q(pIDLY_INC), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair63" *) + LUT5 #( + .INIT(32'h00000004)) + pIDLY_LD_i_1 + (.I0(pState[4]), + .I1(pState[0]), + .I2(pState[3]), + .I3(pIDLY_LD_i_2_n_0), + .I4(\pState[10]_i_3_n_0 ), + .O(pIDLY_LD_0)); + (* SOFT_HLUTNM = "soft_lutpair69" *) + LUT5 #( + .INIT(32'hFFFFFFFE)) + pIDLY_LD_i_2 + (.I0(pState[1]), + .I1(pState[6]), + .I2(pState[8]), + .I3(pState[7]), + .I4(pState[5]), + .O(pIDLY_LD_i_2_n_0)); + FDRE pIDLY_LD_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pIDLY_LD_0), + .Q(pIDLY_LD), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair68" *) + LUT5 #( + .INIT(32'h00010116)) + pStateNxt + (.I0(pState[0]), + .I1(pState[1]), + .I2(pState[2]), + .I3(pState[3]), + .I4(pState[4]), + .O(pStateNxt_n_0)); + (* SOFT_HLUTNM = "soft_lutpair68" *) + LUT5 #( + .INIT(32'hFFFEFEE8)) + pStateNxt__0 + (.I0(pState[0]), + .I1(pState[1]), + .I2(pState[2]), + .I3(pState[3]), + .I4(pState[4]), + .O(pStateNxt__0_n_0)); + LUT6 #( + .INIT(64'h0000000100010116)) + pStateNxt__1 + (.I0(pState[5]), + .I1(pState[6]), + .I2(pState[7]), + .I3(pState[8]), + .I4(pState[9]), + .I5(pState[10]), + .O(pStateNxt__1_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFEFFFEFEE8)) + pStateNxt__2 + (.I0(pState[5]), + .I1(pState[6]), + .I2(pState[7]), + .I3(pState[8]), + .I4(pState[9]), + .I5(pState[10]), + .O(pStateNxt__2_n_0)); + LUT4 #( + .INIT(16'h0012)) + pStateNxt__3 + (.I0(pStateNxt_n_0), + .I1(pStateNxt__0_n_0), + .I2(pStateNxt__1_n_0), + .I3(pStateNxt__2_n_0), + .O(pStateNxt__3_n_0)); + LUT1 #( + .INIT(2'h1)) + \pState[0]_i_1 + (.I0(pStateNxt__3_n_0), + .O(\pState[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFC8)) + \pState[10]_i_1 + (.I0(\pState[10]_i_3_n_0 ), + .I1(iIn_q_i_3_n_0), + .I2(pDelayWaitOvf), + .I3(\pState[10]_i_4_n_0 ), + .I4(\pState[10]_i_5_n_0 ), + .I5(\pState[10]_i_6_n_0 ), + .O(pStateNxt__4)); + (* SOFT_HLUTNM = "soft_lutpair76" *) + LUT3 #( + .INIT(8'h80)) + \pState[10]_i_2 + (.I0(pDelayOvf), + .I1(pState[6]), + .I2(pStateNxt__3_n_0), + .O(\pState[10]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair75" *) + LUT3 #( + .INIT(8'hFE)) + \pState[10]_i_3 + (.I0(pState[10]), + .I1(pState[9]), + .I2(pState[2]), + .O(\pState[10]_i_3_n_0 )); + LUT6 #( + .INIT(64'h8888888889898988)) + \pState[10]_i_4 + (.I0(pState[10]), + .I1(pState[9]), + .I2(pState[2]), + .I3(out), + .I4(pBlankBegin), + .I5(iIn_q_i_3_n_0), + .O(\pState[10]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFD00FD00FD00)) + \pState[10]_i_5 + (.I0(pTknFlagQ), + .I1(pCtlTknOvf_reg_n_0), + .I2(iIn_q_i_4_n_0), + .I3(pState[2]), + .I4(pState[6]), + .I5(pState[8]), + .O(\pState[10]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFEFEFEEF)) + \pState[10]_i_6 + (.I0(pState[5]), + .I1(pState[7]), + .I2(pState[1]), + .I3(iIn_q_i_3_n_0), + .I4(\pState[10]_i_3_n_0 ), + .I5(iIn_q_i_2_n_0), + .O(\pState[10]_i_6_n_0 )); + LUT6 #( + .INIT(64'hFFFF4F4400000000)) + \pState[1]_i_1 + (.I0(pDelayOvf), + .I1(pState[6]), + .I2(pTknFlagQ), + .I3(pState[2]), + .I4(pState[0]), + .I5(pStateNxt__3_n_0), + .O(\pState[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair65" *) + LUT3 #( + .INIT(8'h80)) + \pState[2]_i_1 + (.I0(pBlankBegin), + .I1(pState[1]), + .I2(pStateNxt__3_n_0), + .O(\pState[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair77" *) + LUT3 #( + .INIT(8'h80)) + \pState[3]_i_1 + (.I0(pState[2]), + .I1(pTknFlagQ), + .I2(pStateNxt__3_n_0), + .O(\pState[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair65" *) + LUT5 #( + .INIT(32'h4040F040)) + \pState[4]_i_1 + (.I0(\pState[5]_i_2_n_0 ), + .I1(pState[3]), + .I2(pStateNxt__3_n_0), + .I3(pState[1]), + .I4(pBlankBegin), + .O(\pState[4]_i_1_n_0 )); + LUT5 #( + .INIT(32'h8080F080)) + \pState[5]_i_1 + (.I0(pState[3]), + .I1(\pState[5]_i_2_n_0 ), + .I2(pStateNxt__3_n_0), + .I3(pState[4]), + .I4(pFoundEyeFlag), + .O(\pState[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair70" *) + LUT5 #( + .INIT(32'hFFFFFEFF)) + \pState[5]_i_2 + (.I0(\pEyeOpenCnt_reg_n_0_[0] ), + .I1(\pEyeOpenCnt_reg_n_0_[2] ), + .I2(\pEyeOpenCnt_reg_n_0_[3] ), + .I3(\pEyeOpenCnt_reg_n_0_[4] ), + .I4(\pEyeOpenCnt_reg_n_0_[1] ), + .O(\pState[5]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair78" *) + LUT2 #( + .INIT(4'h8)) + \pState[6]_i_1 + (.I0(pState[5]), + .I1(pStateNxt__3_n_0), + .O(\pState[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair62" *) + LUT5 #( + .INIT(32'hF0202020)) + \pState[7]_i_1 + (.I0(pState[8]), + .I1(pDelayCenter), + .I2(pStateNxt__3_n_0), + .I3(pState[4]), + .I4(pFoundEyeFlag), + .O(\pState[7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair77" *) + LUT2 #( + .INIT(4'h8)) + \pState[8]_i_1 + (.I0(pState[7]), + .I1(pStateNxt__3_n_0), + .O(\pState[8]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair62" *) + LUT3 #( + .INIT(8'h80)) + \pState[9]_i_1 + (.I0(pDelayCenter), + .I1(pState[8]), + .I2(pStateNxt__3_n_0), + .O(\pState[9]_i_1_n_0 )); + FDSE \pState_reg[0] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[0]_i_1_n_0 ), + .Q(pState[0]), + .S(SR)); + FDRE \pState_reg[10] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[10]_i_2_n_0 ), + .Q(pState[10]), + .R(SR)); + FDRE \pState_reg[1] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[1]_i_1_n_0 ), + .Q(pState[1]), + .R(SR)); + FDRE \pState_reg[2] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[2]_i_1_n_0 ), + .Q(pState[2]), + .R(SR)); + FDRE \pState_reg[3] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[3]_i_1_n_0 ), + .Q(pState[3]), + .R(SR)); + FDRE \pState_reg[4] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[4]_i_1_n_0 ), + .Q(pState[4]), + .R(SR)); + FDRE \pState_reg[5] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[5]_i_1_n_0 ), + .Q(pState[5]), + .R(SR)); + FDRE \pState_reg[6] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[6]_i_1_n_0 ), + .Q(pState[6]), + .R(SR)); + FDRE \pState_reg[7] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[7]_i_1_n_0 ), + .Q(pState[7]), + .R(SR)); + FDRE \pState_reg[8] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[8]_i_1_n_0 ), + .Q(pState[8]), + .R(SR)); + FDRE \pState_reg[9] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[9]_i_1_n_0 ), + .Q(pState[9]), + .R(SR)); + FDRE pTknFlagQ_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pTknFlag), + .Q(pTknFlagQ), + .R(1'b0)); + LUT5 #( + .INIT(32'h30000808)) + pTknFlag_i_1 + (.I0(pTknFlag_i_2_n_0), + .I1(pDataQ[8]), + .I2(pDataQ[0]), + .I3(pTknFlag_i_3_n_0), + .I4(pDataQ[3]), + .O(pTknFlag0)); + LUT6 #( + .INIT(64'h0002000000000000)) + pTknFlag_i_2 + (.I0(pDataQ[4]), + .I1(pDataQ[5]), + .I2(pDataQ[7]), + .I3(pDataQ[1]), + .I4(pDataQ[2]), + .I5(pDataQ[6]), + .O(pTknFlag_i_2_n_0)); + LUT6 #( + .INIT(64'h0000000000004000)) + pTknFlag_i_3 + (.I0(pDataQ[4]), + .I1(pDataQ[5]), + .I2(pDataQ[7]), + .I3(pDataQ[1]), + .I4(pDataQ[2]), + .I5(pDataQ[6]), + .O(pTknFlag_i_3_n_0)); + FDRE pTknFlag_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pTknFlag0), + .Q(pTknFlag), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "PhaseAlign" *) +module Arty_Z7_20_dvi2rgb_0_0_PhaseAlign_12 + (pIDLY_CE, + pIDLY_INC, + pIDLY_LD, + pVld_1, + pAlignErr_q_reg, + iIn_q_reg, + pMeRdy_int_reg, + pBitslip_reg, + PixelClk_int, + out, + pVld_2, + pVld_0, + pAlignErr_q, + D, + pIDLY_CE_reg_0, + SS); + output pIDLY_CE; + output pIDLY_INC; + output pIDLY_LD; + output pVld_1; + output pAlignErr_q_reg; + output iIn_q_reg; + output pMeRdy_int_reg; + output pBitslip_reg; + input PixelClk_int; + input [0:0]out; + input pVld_2; + input pVld_0; + input pAlignErr_q; + input [8:0]D; + input [4:0]pIDLY_CE_reg_0; + input [0:0]SS; + + wire [8:0]D; + wire PixelClk_int; + wire [0:0]SS; + wire iIn_q_i_2__0_n_0; + wire iIn_q_i_3__0_n_0; + wire iIn_q_i_4__0_n_0; + wire iIn_q_i_5__0_n_0; + wire iIn_q_reg; + wire [0:0]out; + wire pAlignErr_q; + wire pAlignErr_q_reg; + wire pAligned; + wire pBitslip_reg; + wire pBlankBegin; + wire pBlankBegin0; + wire \pCenterTap[0]_i_1_n_0 ; + wire \pCenterTap[1]_i_1__0_n_0 ; + wire \pCenterTap[2]_i_1__0_n_0 ; + wire \pCenterTap[3]_i_1__0_n_0 ; + wire \pCenterTap[3]_i_2__0_n_0 ; + wire \pCenterTap[4]_i_1__0_n_0 ; + wire \pCenterTap[5]_i_1__0_n_0 ; + wire \pCenterTap[5]_i_2__0_n_0 ; + wire \pCenterTap[5]_i_3__0_n_0 ; + wire \pCenterTap[5]_i_5__0_n_0 ; + wire \pCenterTap_reg_n_0_[0] ; + wire \pCenterTap_reg_n_0_[1] ; + wire \pCenterTap_reg_n_0_[2] ; + wire \pCenterTap_reg_n_0_[3] ; + wire \pCenterTap_reg_n_0_[4] ; + wire \pCenterTap_reg_n_0_[5] ; + wire \pCtlTknCnt[6]_i_3__0_n_0 ; + wire \pCtlTknCnt[6]_i_4__0_n_0 ; + wire [6:0]pCtlTknCnt_reg__0; + wire pCtlTknOvf_i_1__0_n_0; + wire pCtlTknOvf_i_2__0_n_0; + wire pCtlTknOvf_reg_n_0; + wire pCtlTknRst; + wire \pDataQ_reg_n_0_[0] ; + wire \pDataQ_reg_n_0_[1] ; + wire \pDataQ_reg_n_0_[2] ; + wire \pDataQ_reg_n_0_[3] ; + wire \pDataQ_reg_n_0_[4] ; + wire \pDataQ_reg_n_0_[5] ; + wire \pDataQ_reg_n_0_[6] ; + wire \pDataQ_reg_n_0_[7] ; + wire \pDataQ_reg_n_0_[8] ; + wire pDelayCenter_i_1__0_n_0; + wire pDelayCenter_i_2__0_n_0; + wire pDelayCenter_reg_n_0; + wire pDelayOvf_i_1__0_n_0; + wire pDelayOvf_reg_n_0; + wire [1:0]pDelayWaitCnt; + wire \pDelayWaitCnt[0]_i_1_n_0 ; + wire \pDelayWaitCnt[0]_i_2__0_n_0 ; + wire \pDelayWaitCnt[1]_i_1_n_0 ; + wire pDelayWaitOvf_i_1__0_n_0; + wire pDelayWaitOvf_i_2__0_n_0; + wire pDelayWaitOvf_i_3__0_n_0; + wire pDelayWaitOvf_reg_n_0; + wire pError; + wire \pEyeOpenCnt[0]_i_1__0_n_0 ; + wire \pEyeOpenCnt[1]_i_1__0_n_0 ; + wire \pEyeOpenCnt[2]_i_1__0_n_0 ; + wire \pEyeOpenCnt[3]_i_1__0_n_0 ; + wire \pEyeOpenCnt[4]_i_1__0_n_0 ; + wire \pEyeOpenCnt[4]_i_2__0_n_0 ; + wire \pEyeOpenCnt[4]_i_3__0_n_0 ; + wire \pEyeOpenCnt_reg_n_0_[0] ; + wire \pEyeOpenCnt_reg_n_0_[1] ; + wire \pEyeOpenCnt_reg_n_0_[2] ; + wire \pEyeOpenCnt_reg_n_0_[3] ; + wire \pEyeOpenCnt_reg_n_0_[4] ; + wire pEyeOpenEn__5; + wire pEyeOpenRst; + wire pFoundEyeFlag; + wire pFoundEyeFlag_i_1__0_n_0; + wire pFoundEyeFlag_i_2__0_n_0; + wire pFoundEyeFlag_i_3__0_n_0; + wire pFoundEyeFlag_i_4__0_n_0; + wire pFoundJtrFlag; + wire pFoundJtrFlag_i_1__0_n_0; + wire pIDLY_CE; + wire pIDLY_CE_1; + wire [4:0]pIDLY_CE_reg_0; + wire \pIDLY_CNT_Q_reg_n_0_[0] ; + wire \pIDLY_CNT_Q_reg_n_0_[1] ; + wire \pIDLY_CNT_Q_reg_n_0_[2] ; + wire \pIDLY_CNT_Q_reg_n_0_[3] ; + wire \pIDLY_CNT_Q_reg_n_0_[4] ; + wire pIDLY_INC; + wire pIDLY_INC_i_1__0_n_0; + wire pIDLY_LD; + wire pIDLY_LD_0; + wire pIDLY_LD_i_2__0_n_0; + wire pMeRdy_int_reg; + wire [10:0]pState; + wire pStateNxt__0_n_0; + wire pStateNxt__1_n_0; + wire pStateNxt__2_n_0; + wire pStateNxt__3_n_0; + wire pStateNxt__4; + wire pStateNxt_n_0; + wire \pState[0]_i_1__0_n_0 ; + wire \pState[10]_i_2__0_n_0 ; + wire \pState[10]_i_3__0_n_0 ; + wire \pState[10]_i_4__0_n_0 ; + wire \pState[10]_i_5__0_n_0 ; + wire \pState[10]_i_6__0_n_0 ; + wire \pState[1]_i_1__0_n_0 ; + wire \pState[2]_i_1__0_n_0 ; + wire \pState[3]_i_1__0_n_0 ; + wire \pState[4]_i_1__0_n_0 ; + wire \pState[5]_i_1__0_n_0 ; + wire \pState[5]_i_2__0_n_0 ; + wire \pState[6]_i_1__0_n_0 ; + wire \pState[7]_i_1__0_n_0 ; + wire \pState[8]_i_1__0_n_0 ; + wire \pState[9]_i_1__0_n_0 ; + wire pTknFlag; + wire pTknFlag0; + wire pTknFlagQ; + wire pTknFlag_i_2__0_n_0; + wire pTknFlag_i_3__0_n_0; + wire pVld_0; + wire pVld_1; + wire pVld_2; + wire [6:0]p_0_in; + wire p_2_in; + wire [5:4]plusOp__16; + + LUT6 #( + .INIT(64'hFFFFFFFEFFFEFFFF)) + iIn_q_i_1__0 + (.I0(iIn_q_i_2__0_n_0), + .I1(iIn_q_i_3__0_n_0), + .I2(iIn_q_i_4__0_n_0), + .I3(iIn_q_i_5__0_n_0), + .I4(pState[1]), + .I5(pState[2]), + .O(iIn_q_reg)); + (* SOFT_HLUTNM = "soft_lutpair40" *) + LUT3 #( + .INIT(8'hFE)) + iIn_q_i_2__0 + (.I0(pState[4]), + .I1(pState[0]), + .I2(pState[3]), + .O(iIn_q_i_2__0_n_0)); + (* SOFT_HLUTNM = "soft_lutpair42" *) + LUT2 #( + .INIT(4'hE)) + iIn_q_i_3__0 + (.I0(pState[6]), + .I1(pState[8]), + .O(iIn_q_i_3__0_n_0)); + LUT2 #( + .INIT(4'hE)) + iIn_q_i_4__0 + (.I0(pState[9]), + .I1(pState[10]), + .O(iIn_q_i_4__0_n_0)); + (* SOFT_HLUTNM = "soft_lutpair50" *) + LUT2 #( + .INIT(4'hE)) + iIn_q_i_5__0 + (.I0(pState[5]), + .I1(pState[7]), + .O(iIn_q_i_5__0_n_0)); + (* SOFT_HLUTNM = "soft_lutpair45" *) + LUT4 #( + .INIT(16'h0004)) + pAligned_i_1__0 + (.I0(pState[2]), + .I1(pState[9]), + .I2(pState[10]), + .I3(\pCtlTknCnt[6]_i_3__0_n_0 ), + .O(pAligned)); + FDRE pAligned_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pAligned), + .Q(pVld_1), + .R(1'b0)); + LUT2 #( + .INIT(4'h2)) + pBitslip_i_1__0 + (.I0(pAlignErr_q_reg), + .I1(pAlignErr_q), + .O(pBitslip_reg)); + LUT2 #( + .INIT(4'h2)) + pBlankBegin_i_1__0 + (.I0(pTknFlag), + .I1(pTknFlagQ), + .O(pBlankBegin0)); + FDRE pBlankBegin_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pBlankBegin0), + .Q(pBlankBegin), + .R(1'b0)); + LUT6 #( + .INIT(64'hAAAAAAA5AAAAAFBA)) + \pCenterTap[0]_i_1 + (.I0(\pCenterTap_reg_n_0_[0] ), + .I1(pFoundEyeFlag), + .I2(pState[4]), + .I3(pState[0]), + .I4(\pCenterTap[5]_i_3__0_n_0 ), + .I5(pState[3]), + .O(\pCenterTap[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair38" *) + LUT5 #( + .INIT(32'hFF606060)) + \pCenterTap[1]_i_1__0 + (.I0(\pCenterTap_reg_n_0_[0] ), + .I1(\pCenterTap_reg_n_0_[1] ), + .I2(\pCenterTap[5]_i_5__0_n_0 ), + .I3(\pIDLY_CNT_Q_reg_n_0_[0] ), + .I4(pEyeOpenRst), + .O(\pCenterTap[1]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hFFFF780078007800)) + \pCenterTap[2]_i_1__0 + (.I0(\pCenterTap_reg_n_0_[1] ), + .I1(\pCenterTap_reg_n_0_[0] ), + .I2(\pCenterTap_reg_n_0_[2] ), + .I3(\pCenterTap[5]_i_5__0_n_0 ), + .I4(\pIDLY_CNT_Q_reg_n_0_[1] ), + .I5(pEyeOpenRst), + .O(\pCenterTap[2]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hFFFF780078007800)) + \pCenterTap[3]_i_1__0 + (.I0(\pCenterTap_reg_n_0_[2] ), + .I1(\pCenterTap[3]_i_2__0_n_0 ), + .I2(\pCenterTap_reg_n_0_[3] ), + .I3(\pCenterTap[5]_i_5__0_n_0 ), + .I4(\pIDLY_CNT_Q_reg_n_0_[2] ), + .I5(pEyeOpenRst), + .O(\pCenterTap[3]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair38" *) + LUT2 #( + .INIT(4'h8)) + \pCenterTap[3]_i_2__0 + (.I0(\pCenterTap_reg_n_0_[0] ), + .I1(\pCenterTap_reg_n_0_[1] ), + .O(\pCenterTap[3]_i_2__0_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \pCenterTap[4]_i_1__0 + (.I0(plusOp__16[4]), + .I1(\pCenterTap[5]_i_5__0_n_0 ), + .I2(\pIDLY_CNT_Q_reg_n_0_[3] ), + .I3(pEyeOpenRst), + .O(\pCenterTap[4]_i_1__0_n_0 )); + LUT5 #( + .INIT(32'h7FFF8000)) + \pCenterTap[4]_i_2__0 + (.I0(\pCenterTap_reg_n_0_[0] ), + .I1(\pCenterTap_reg_n_0_[1] ), + .I2(\pCenterTap_reg_n_0_[2] ), + .I3(\pCenterTap_reg_n_0_[3] ), + .I4(\pCenterTap_reg_n_0_[4] ), + .O(plusOp__16[4])); + LUT5 #( + .INIT(32'h00030034)) + \pCenterTap[5]_i_1__0 + (.I0(pFoundEyeFlag), + .I1(pState[4]), + .I2(pState[0]), + .I3(\pCenterTap[5]_i_3__0_n_0 ), + .I4(pState[3]), + .O(\pCenterTap[5]_i_1__0_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \pCenterTap[5]_i_2__0 + (.I0(plusOp__16[5]), + .I1(\pCenterTap[5]_i_5__0_n_0 ), + .I2(\pIDLY_CNT_Q_reg_n_0_[4] ), + .I3(pEyeOpenRst), + .O(\pCenterTap[5]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \pCenterTap[5]_i_3__0 + (.I0(pState[5]), + .I1(pState[7]), + .I2(pState[8]), + .I3(pState[6]), + .I4(pState[1]), + .I5(\pState[10]_i_3__0_n_0 ), + .O(\pCenterTap[5]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'h7FFFFFFF80000000)) + \pCenterTap[5]_i_4__0 + (.I0(\pCenterTap_reg_n_0_[0] ), + .I1(\pCenterTap_reg_n_0_[1] ), + .I2(\pCenterTap_reg_n_0_[4] ), + .I3(\pCenterTap_reg_n_0_[3] ), + .I4(\pCenterTap_reg_n_0_[2] ), + .I5(\pCenterTap_reg_n_0_[5] ), + .O(plusOp__16[5])); + LUT6 #( + .INIT(64'hFFFFFFFEFFFAFFFF)) + \pCenterTap[5]_i_5__0 + (.I0(pState[3]), + .I1(pFoundEyeFlag), + .I2(pIDLY_LD_i_2__0_n_0), + .I3(\pState[10]_i_3__0_n_0 ), + .I4(pState[0]), + .I5(pState[4]), + .O(\pCenterTap[5]_i_5__0_n_0 )); + LUT6 #( + .INIT(64'h0000010000010100)) + \pCenterTap[5]_i_6__0 + (.I0(pState[3]), + .I1(pIDLY_LD_i_2__0_n_0), + .I2(\pState[10]_i_3__0_n_0 ), + .I3(pState[0]), + .I4(pState[4]), + .I5(pFoundEyeFlag), + .O(pEyeOpenRst)); + FDRE \pCenterTap_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(\pCenterTap[0]_i_1_n_0 ), + .Q(\pCenterTap_reg_n_0_[0] ), + .R(1'b0)); + FDRE \pCenterTap_reg[1] + (.C(PixelClk_int), + .CE(\pCenterTap[5]_i_1__0_n_0 ), + .D(\pCenterTap[1]_i_1__0_n_0 ), + .Q(\pCenterTap_reg_n_0_[1] ), + .R(1'b0)); + FDRE \pCenterTap_reg[2] + (.C(PixelClk_int), + .CE(\pCenterTap[5]_i_1__0_n_0 ), + .D(\pCenterTap[2]_i_1__0_n_0 ), + .Q(\pCenterTap_reg_n_0_[2] ), + .R(1'b0)); + FDRE \pCenterTap_reg[3] + (.C(PixelClk_int), + .CE(\pCenterTap[5]_i_1__0_n_0 ), + .D(\pCenterTap[3]_i_1__0_n_0 ), + .Q(\pCenterTap_reg_n_0_[3] ), + .R(1'b0)); + FDRE \pCenterTap_reg[4] + (.C(PixelClk_int), + .CE(\pCenterTap[5]_i_1__0_n_0 ), + .D(\pCenterTap[4]_i_1__0_n_0 ), + .Q(\pCenterTap_reg_n_0_[4] ), + .R(1'b0)); + FDRE \pCenterTap_reg[5] + (.C(PixelClk_int), + .CE(\pCenterTap[5]_i_1__0_n_0 ), + .D(\pCenterTap[5]_i_2__0_n_0 ), + .Q(\pCenterTap_reg_n_0_[5] ), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair51" *) + LUT1 #( + .INIT(2'h1)) + \pCtlTknCnt[0]_i_1__0 + (.I0(pCtlTknCnt_reg__0[0]), + .O(p_0_in[0])); + (* SOFT_HLUTNM = "soft_lutpair51" *) + LUT2 #( + .INIT(4'h6)) + \pCtlTknCnt[1]_i_1__0 + (.I0(pCtlTknCnt_reg__0[0]), + .I1(pCtlTknCnt_reg__0[1]), + .O(p_0_in[1])); + (* SOFT_HLUTNM = "soft_lutpair46" *) + LUT3 #( + .INIT(8'h78)) + \pCtlTknCnt[2]_i_1__0 + (.I0(pCtlTknCnt_reg__0[1]), + .I1(pCtlTknCnt_reg__0[0]), + .I2(pCtlTknCnt_reg__0[2]), + .O(p_0_in[2])); + (* SOFT_HLUTNM = "soft_lutpair46" *) + LUT4 #( + .INIT(16'h7F80)) + \pCtlTknCnt[3]_i_1__0 + (.I0(pCtlTknCnt_reg__0[2]), + .I1(pCtlTknCnt_reg__0[0]), + .I2(pCtlTknCnt_reg__0[1]), + .I3(pCtlTknCnt_reg__0[3]), + .O(p_0_in[3])); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \pCtlTknCnt[4]_i_1__0 + (.I0(pCtlTknCnt_reg__0[3]), + .I1(pCtlTknCnt_reg__0[1]), + .I2(pCtlTknCnt_reg__0[0]), + .I3(pCtlTknCnt_reg__0[2]), + .I4(pCtlTknCnt_reg__0[4]), + .O(p_0_in[4])); + LUT6 #( + .INIT(64'h7FFFFFFF80000000)) + \pCtlTknCnt[5]_i_1__0 + (.I0(pCtlTknCnt_reg__0[4]), + .I1(pCtlTknCnt_reg__0[2]), + .I2(pCtlTknCnt_reg__0[0]), + .I3(pCtlTknCnt_reg__0[1]), + .I4(pCtlTknCnt_reg__0[3]), + .I5(pCtlTknCnt_reg__0[5]), + .O(p_0_in[5])); + LUT4 #( + .INIT(16'hFFFD)) + \pCtlTknCnt[6]_i_1__0 + (.I0(pState[2]), + .I1(pState[9]), + .I2(pState[10]), + .I3(\pCtlTknCnt[6]_i_3__0_n_0 ), + .O(pCtlTknRst)); + (* SOFT_HLUTNM = "soft_lutpair44" *) + LUT4 #( + .INIT(16'h7F80)) + \pCtlTknCnt[6]_i_2__0 + (.I0(\pCtlTknCnt[6]_i_4__0_n_0 ), + .I1(pCtlTknCnt_reg__0[4]), + .I2(pCtlTknCnt_reg__0[5]), + .I3(pCtlTknCnt_reg__0[6]), + .O(p_0_in[6])); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \pCtlTknCnt[6]_i_3__0 + (.I0(iIn_q_i_2__0_n_0), + .I1(pState[5]), + .I2(pState[7]), + .I3(pState[8]), + .I4(pState[6]), + .I5(pState[1]), + .O(\pCtlTknCnt[6]_i_3__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT4 #( + .INIT(16'h8000)) + \pCtlTknCnt[6]_i_4__0 + (.I0(pCtlTknCnt_reg__0[2]), + .I1(pCtlTknCnt_reg__0[0]), + .I2(pCtlTknCnt_reg__0[1]), + .I3(pCtlTknCnt_reg__0[3]), + .O(\pCtlTknCnt[6]_i_4__0_n_0 )); + FDRE \pCtlTknCnt_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in[0]), + .Q(pCtlTknCnt_reg__0[0]), + .R(pCtlTknRst)); + FDRE \pCtlTknCnt_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in[1]), + .Q(pCtlTknCnt_reg__0[1]), + .R(pCtlTknRst)); + FDRE \pCtlTknCnt_reg[2] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in[2]), + .Q(pCtlTknCnt_reg__0[2]), + .R(pCtlTknRst)); + FDRE \pCtlTknCnt_reg[3] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in[3]), + .Q(pCtlTknCnt_reg__0[3]), + .R(pCtlTknRst)); + FDRE \pCtlTknCnt_reg[4] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in[4]), + .Q(pCtlTknCnt_reg__0[4]), + .R(pCtlTknRst)); + FDRE \pCtlTknCnt_reg[5] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in[5]), + .Q(pCtlTknCnt_reg__0[5]), + .R(pCtlTknRst)); + FDRE \pCtlTknCnt_reg[6] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in[6]), + .Q(pCtlTknCnt_reg__0[6]), + .R(pCtlTknRst)); + LUT6 #( + .INIT(64'hAAAAAAAEAAAAAAA2)) + pCtlTknOvf_i_1__0 + (.I0(pCtlTknOvf_reg_n_0), + .I1(pState[2]), + .I2(pState[9]), + .I3(pState[10]), + .I4(\pCtlTknCnt[6]_i_3__0_n_0 ), + .I5(pCtlTknOvf_i_2__0_n_0), + .O(pCtlTknOvf_i_1__0_n_0)); + (* SOFT_HLUTNM = "soft_lutpair44" *) + LUT4 #( + .INIT(16'h8000)) + pCtlTknOvf_i_2__0 + (.I0(pCtlTknCnt_reg__0[4]), + .I1(pCtlTknCnt_reg__0[5]), + .I2(pCtlTknCnt_reg__0[6]), + .I3(\pCtlTknCnt[6]_i_4__0_n_0 ), + .O(pCtlTknOvf_i_2__0_n_0)); + FDRE pCtlTknOvf_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pCtlTknOvf_i_1__0_n_0), + .Q(pCtlTknOvf_reg_n_0), + .R(1'b0)); + FDRE \pDataQ_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(D[0]), + .Q(\pDataQ_reg_n_0_[0] ), + .R(1'b0)); + FDRE \pDataQ_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .D(D[1]), + .Q(\pDataQ_reg_n_0_[1] ), + .R(1'b0)); + FDRE \pDataQ_reg[2] + (.C(PixelClk_int), + .CE(1'b1), + .D(D[2]), + .Q(\pDataQ_reg_n_0_[2] ), + .R(1'b0)); + FDRE \pDataQ_reg[3] + (.C(PixelClk_int), + .CE(1'b1), + .D(D[3]), + .Q(\pDataQ_reg_n_0_[3] ), + .R(1'b0)); + FDRE \pDataQ_reg[4] + (.C(PixelClk_int), + .CE(1'b1), + .D(D[4]), + .Q(\pDataQ_reg_n_0_[4] ), + .R(1'b0)); + FDRE \pDataQ_reg[5] + (.C(PixelClk_int), + .CE(1'b1), + .D(D[5]), + .Q(\pDataQ_reg_n_0_[5] ), + .R(1'b0)); + FDRE \pDataQ_reg[6] + (.C(PixelClk_int), + .CE(1'b1), + .D(D[6]), + .Q(\pDataQ_reg_n_0_[6] ), + .R(1'b0)); + FDRE \pDataQ_reg[7] + (.C(PixelClk_int), + .CE(1'b1), + .D(D[7]), + .Q(\pDataQ_reg_n_0_[7] ), + .R(1'b0)); + FDRE \pDataQ_reg[8] + (.C(PixelClk_int), + .CE(1'b1), + .D(D[8]), + .Q(\pDataQ_reg_n_0_[8] ), + .R(1'b0)); + LUT5 #( + .INIT(32'h82000082)) + pDelayCenter_i_1__0 + (.I0(pDelayCenter_i_2__0_n_0), + .I1(\pCenterTap_reg_n_0_[5] ), + .I2(\pIDLY_CNT_Q_reg_n_0_[4] ), + .I3(\pCenterTap_reg_n_0_[4] ), + .I4(\pIDLY_CNT_Q_reg_n_0_[3] ), + .O(pDelayCenter_i_1__0_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + pDelayCenter_i_2__0 + (.I0(\pCenterTap_reg_n_0_[3] ), + .I1(\pIDLY_CNT_Q_reg_n_0_[2] ), + .I2(\pCenterTap_reg_n_0_[2] ), + .I3(\pIDLY_CNT_Q_reg_n_0_[1] ), + .I4(\pIDLY_CNT_Q_reg_n_0_[0] ), + .I5(\pCenterTap_reg_n_0_[1] ), + .O(pDelayCenter_i_2__0_n_0)); + FDRE pDelayCenter_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pDelayCenter_i_1__0_n_0), + .Q(pDelayCenter_reg_n_0), + .R(1'b0)); + LUT5 #( + .INIT(32'h00000001)) + pDelayOvf_i_1__0 + (.I0(\pIDLY_CNT_Q_reg_n_0_[0] ), + .I1(\pIDLY_CNT_Q_reg_n_0_[1] ), + .I2(\pIDLY_CNT_Q_reg_n_0_[2] ), + .I3(\pIDLY_CNT_Q_reg_n_0_[4] ), + .I4(\pIDLY_CNT_Q_reg_n_0_[3] ), + .O(pDelayOvf_i_1__0_n_0)); + FDRE pDelayOvf_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pDelayOvf_i_1__0_n_0), + .Q(pDelayOvf_reg_n_0), + .R(1'b0)); + LUT6 #( + .INIT(64'h0000001400000000)) + \pDelayWaitCnt[0]_i_1 + (.I0(pDelayWaitCnt[0]), + .I1(pState[6]), + .I2(pState[8]), + .I3(iIn_q_i_5__0_n_0), + .I4(pState[1]), + .I5(\pDelayWaitCnt[0]_i_2__0_n_0 ), + .O(\pDelayWaitCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000000000000001)) + \pDelayWaitCnt[0]_i_2__0 + (.I0(pState[3]), + .I1(pState[0]), + .I2(pState[4]), + .I3(pState[2]), + .I4(pState[9]), + .I5(pState[10]), + .O(\pDelayWaitCnt[0]_i_2__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair47" *) + LUT3 #( + .INIT(8'h60)) + \pDelayWaitCnt[1]_i_1 + (.I0(pDelayWaitCnt[1]), + .I1(pDelayWaitCnt[0]), + .I2(p_2_in), + .O(\pDelayWaitCnt[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000000600000000)) + \pDelayWaitCnt[1]_i_2__0 + (.I0(pState[6]), + .I1(pState[8]), + .I2(pState[7]), + .I3(pState[5]), + .I4(pState[1]), + .I5(\pDelayWaitCnt[0]_i_2__0_n_0 ), + .O(p_2_in)); + FDRE \pDelayWaitCnt_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(\pDelayWaitCnt[0]_i_1_n_0 ), + .Q(pDelayWaitCnt[0]), + .R(1'b0)); + FDRE \pDelayWaitCnt_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .D(\pDelayWaitCnt[1]_i_1_n_0 ), + .Q(pDelayWaitCnt[1]), + .R(1'b0)); + LUT6 #( + .INIT(64'hCCFCCCCCCC8CCCCC)) + pDelayWaitOvf_i_1__0 + (.I0(pState[1]), + .I1(pDelayWaitOvf_reg_n_0), + .I2(\pDelayWaitCnt[0]_i_2__0_n_0 ), + .I3(iIn_q_i_5__0_n_0), + .I4(pDelayWaitOvf_i_2__0_n_0), + .I5(pDelayWaitOvf_i_3__0_n_0), + .O(pDelayWaitOvf_i_1__0_n_0)); + (* SOFT_HLUTNM = "soft_lutpair49" *) + LUT2 #( + .INIT(4'h6)) + pDelayWaitOvf_i_2__0 + (.I0(pState[6]), + .I1(pState[8]), + .O(pDelayWaitOvf_i_2__0_n_0)); + (* SOFT_HLUTNM = "soft_lutpair47" *) + LUT3 #( + .INIT(8'h04)) + pDelayWaitOvf_i_3__0 + (.I0(pState[1]), + .I1(pDelayWaitCnt[1]), + .I2(pDelayWaitCnt[0]), + .O(pDelayWaitOvf_i_3__0_n_0)); + FDRE pDelayWaitOvf_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pDelayWaitOvf_i_1__0_n_0), + .Q(pDelayWaitOvf_reg_n_0), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair45" *) + LUT4 #( + .INIT(16'h0004)) + pError_i_1__0 + (.I0(pState[2]), + .I1(pState[10]), + .I2(pState[9]), + .I3(\pCtlTknCnt[6]_i_3__0_n_0 ), + .O(pError)); + FDRE pError_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pError), + .Q(pAlignErr_q_reg), + .R(1'b0)); + LUT6 #( + .INIT(64'hCCCCCCCCCCC3C80C)) + \pEyeOpenCnt[0]_i_1__0 + (.I0(pFoundEyeFlag), + .I1(\pEyeOpenCnt_reg_n_0_[0] ), + .I2(pState[0]), + .I3(pState[4]), + .I4(pState[3]), + .I5(\pCenterTap[5]_i_3__0_n_0 ), + .O(\pEyeOpenCnt[0]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair37" *) + LUT4 #( + .INIT(16'hBCA0)) + \pEyeOpenCnt[1]_i_1__0 + (.I0(\pEyeOpenCnt[4]_i_2__0_n_0 ), + .I1(\pEyeOpenCnt_reg_n_0_[0] ), + .I2(\pEyeOpenCnt_reg_n_0_[1] ), + .I3(pEyeOpenEn__5), + .O(\pEyeOpenCnt[1]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair37" *) + LUT5 #( + .INIT(32'hBFC0AA00)) + \pEyeOpenCnt[2]_i_1__0 + (.I0(\pEyeOpenCnt[4]_i_2__0_n_0 ), + .I1(\pEyeOpenCnt_reg_n_0_[1] ), + .I2(\pEyeOpenCnt_reg_n_0_[0] ), + .I3(\pEyeOpenCnt_reg_n_0_[2] ), + .I4(pEyeOpenEn__5), + .O(\pEyeOpenCnt[2]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hBFFFC000AAAA0000)) + \pEyeOpenCnt[3]_i_1__0 + (.I0(\pEyeOpenCnt[4]_i_2__0_n_0 ), + .I1(\pEyeOpenCnt_reg_n_0_[0] ), + .I2(\pEyeOpenCnt_reg_n_0_[1] ), + .I3(\pEyeOpenCnt_reg_n_0_[2] ), + .I4(\pEyeOpenCnt_reg_n_0_[3] ), + .I5(pEyeOpenEn__5), + .O(\pEyeOpenCnt[3]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hBFFFC000AAAA0000)) + \pEyeOpenCnt[4]_i_1__0 + (.I0(\pEyeOpenCnt[4]_i_2__0_n_0 ), + .I1(\pEyeOpenCnt_reg_n_0_[2] ), + .I2(\pEyeOpenCnt_reg_n_0_[3] ), + .I3(\pEyeOpenCnt[4]_i_3__0_n_0 ), + .I4(\pEyeOpenCnt_reg_n_0_[4] ), + .I5(pEyeOpenEn__5), + .O(\pEyeOpenCnt[4]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFEFFFCFFF3)) + \pEyeOpenCnt[4]_i_2__0 + (.I0(pFoundEyeFlag), + .I1(pState[3]), + .I2(pIDLY_LD_i_2__0_n_0), + .I3(\pState[10]_i_3__0_n_0 ), + .I4(pState[0]), + .I5(pState[4]), + .O(\pEyeOpenCnt[4]_i_2__0_n_0 )); + LUT2 #( + .INIT(4'h8)) + \pEyeOpenCnt[4]_i_3__0 + (.I0(\pEyeOpenCnt_reg_n_0_[0] ), + .I1(\pEyeOpenCnt_reg_n_0_[1] ), + .O(\pEyeOpenCnt[4]_i_3__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair39" *) + LUT5 #( + .INIT(32'h00000010)) + \pEyeOpenCnt[4]_i_4__0 + (.I0(pState[0]), + .I1(pState[4]), + .I2(pState[3]), + .I3(\pState[10]_i_3__0_n_0 ), + .I4(pIDLY_LD_i_2__0_n_0), + .O(pEyeOpenEn__5)); + FDRE \pEyeOpenCnt_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(\pEyeOpenCnt[0]_i_1__0_n_0 ), + .Q(\pEyeOpenCnt_reg_n_0_[0] ), + .R(1'b0)); + FDRE \pEyeOpenCnt_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .D(\pEyeOpenCnt[1]_i_1__0_n_0 ), + .Q(\pEyeOpenCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE \pEyeOpenCnt_reg[2] + (.C(PixelClk_int), + .CE(1'b1), + .D(\pEyeOpenCnt[2]_i_1__0_n_0 ), + .Q(\pEyeOpenCnt_reg_n_0_[2] ), + .R(1'b0)); + FDRE \pEyeOpenCnt_reg[3] + (.C(PixelClk_int), + .CE(1'b1), + .D(\pEyeOpenCnt[3]_i_1__0_n_0 ), + .Q(\pEyeOpenCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE \pEyeOpenCnt_reg[4] + (.C(PixelClk_int), + .CE(1'b1), + .D(\pEyeOpenCnt[4]_i_1__0_n_0 ), + .Q(\pEyeOpenCnt_reg_n_0_[4] ), + .R(1'b0)); + LUT5 #( + .INIT(32'hABBBA888)) + pFoundEyeFlag_i_1__0 + (.I0(pFoundEyeFlag_i_2__0_n_0), + .I1(pIDLY_LD_0), + .I2(pEyeOpenEn__5), + .I3(pFoundEyeFlag_i_3__0_n_0), + .I4(pFoundEyeFlag), + .O(pFoundEyeFlag_i_1__0_n_0)); + LUT6 #( + .INIT(64'h1000004000000040)) + pFoundEyeFlag_i_2__0 + (.I0(pFoundEyeFlag_i_4__0_n_0), + .I1(\pEyeOpenCnt_reg_n_0_[4] ), + .I2(pState[3]), + .I3(\pEyeOpenCnt_reg_n_0_[0] ), + .I4(\pEyeOpenCnt_reg_n_0_[1] ), + .I5(pFoundJtrFlag), + .O(pFoundEyeFlag_i_2__0_n_0)); + LUT6 #( + .INIT(64'h0100001000000010)) + pFoundEyeFlag_i_3__0 + (.I0(\pEyeOpenCnt_reg_n_0_[2] ), + .I1(\pEyeOpenCnt_reg_n_0_[3] ), + .I2(\pEyeOpenCnt_reg_n_0_[4] ), + .I3(\pEyeOpenCnt_reg_n_0_[0] ), + .I4(\pEyeOpenCnt_reg_n_0_[1] ), + .I5(pFoundJtrFlag), + .O(pFoundEyeFlag_i_3__0_n_0)); + (* SOFT_HLUTNM = "soft_lutpair43" *) + LUT2 #( + .INIT(4'hE)) + pFoundEyeFlag_i_4__0 + (.I0(\pEyeOpenCnt_reg_n_0_[2] ), + .I1(\pEyeOpenCnt_reg_n_0_[3] ), + .O(pFoundEyeFlag_i_4__0_n_0)); + FDRE pFoundEyeFlag_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pFoundEyeFlag_i_1__0_n_0), + .Q(pFoundEyeFlag), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair40" *) + LUT5 #( + .INIT(32'hFEFF0010)) + pFoundJtrFlag_i_1__0 + (.I0(pState[3]), + .I1(\pCenterTap[5]_i_3__0_n_0 ), + .I2(pState[4]), + .I3(pState[0]), + .I4(pFoundJtrFlag), + .O(pFoundJtrFlag_i_1__0_n_0)); + FDRE pFoundJtrFlag_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pFoundJtrFlag_i_1__0_n_0), + .Q(pFoundJtrFlag), + .R(1'b0)); + LUT6 #( + .INIT(64'h0000000200020000)) + pIDLY_CE_i_1__0 + (.I0(\pDelayWaitCnt[0]_i_2__0_n_0 ), + .I1(pState[1]), + .I2(pState[6]), + .I3(pState[8]), + .I4(pState[5]), + .I5(pState[7]), + .O(pIDLY_CE_1)); + FDRE pIDLY_CE_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pIDLY_CE_1), + .Q(pIDLY_CE), + .R(1'b0)); + FDRE \pIDLY_CNT_Q_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(pIDLY_CE_reg_0[0]), + .Q(\pIDLY_CNT_Q_reg_n_0_[0] ), + .R(1'b0)); + FDRE \pIDLY_CNT_Q_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .D(pIDLY_CE_reg_0[1]), + .Q(\pIDLY_CNT_Q_reg_n_0_[1] ), + .R(1'b0)); + FDRE \pIDLY_CNT_Q_reg[2] + (.C(PixelClk_int), + .CE(1'b1), + .D(pIDLY_CE_reg_0[2]), + .Q(\pIDLY_CNT_Q_reg_n_0_[2] ), + .R(1'b0)); + FDRE \pIDLY_CNT_Q_reg[3] + (.C(PixelClk_int), + .CE(1'b1), + .D(pIDLY_CE_reg_0[3]), + .Q(\pIDLY_CNT_Q_reg_n_0_[3] ), + .R(1'b0)); + FDRE \pIDLY_CNT_Q_reg[4] + (.C(PixelClk_int), + .CE(1'b1), + .D(pIDLY_CE_reg_0[4]), + .Q(\pIDLY_CNT_Q_reg_n_0_[4] ), + .R(1'b0)); + LUT6 #( + .INIT(64'hAAAAAAA2AAAEAAAA)) + pIDLY_INC_i_1__0 + (.I0(pIDLY_INC), + .I1(\pDelayWaitCnt[0]_i_2__0_n_0 ), + .I2(pState[1]), + .I3(iIn_q_i_3__0_n_0), + .I4(pState[5]), + .I5(pState[7]), + .O(pIDLY_INC_i_1__0_n_0)); + FDRE pIDLY_INC_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pIDLY_INC_i_1__0_n_0), + .Q(pIDLY_INC), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair39" *) + LUT5 #( + .INIT(32'h00000004)) + pIDLY_LD_i_1__0 + (.I0(pState[4]), + .I1(pState[0]), + .I2(pState[3]), + .I3(pIDLY_LD_i_2__0_n_0), + .I4(\pState[10]_i_3__0_n_0 ), + .O(pIDLY_LD_0)); + (* SOFT_HLUTNM = "soft_lutpair42" *) + LUT5 #( + .INIT(32'hFFFFFFFE)) + pIDLY_LD_i_2__0 + (.I0(pState[1]), + .I1(pState[6]), + .I2(pState[8]), + .I3(pState[7]), + .I4(pState[5]), + .O(pIDLY_LD_i_2__0_n_0)); + FDRE pIDLY_LD_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pIDLY_LD_0), + .Q(pIDLY_LD), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT5 #( + .INIT(32'h00010116)) + pStateNxt + (.I0(pState[0]), + .I1(pState[1]), + .I2(pState[2]), + .I3(pState[3]), + .I4(pState[4]), + .O(pStateNxt_n_0)); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT5 #( + .INIT(32'hFFFEFEE8)) + pStateNxt__0 + (.I0(pState[0]), + .I1(pState[1]), + .I2(pState[2]), + .I3(pState[3]), + .I4(pState[4]), + .O(pStateNxt__0_n_0)); + LUT6 #( + .INIT(64'h0000000100010116)) + pStateNxt__1 + (.I0(pState[5]), + .I1(pState[6]), + .I2(pState[7]), + .I3(pState[8]), + .I4(pState[9]), + .I5(pState[10]), + .O(pStateNxt__1_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFEFFFEFEE8)) + pStateNxt__2 + (.I0(pState[5]), + .I1(pState[6]), + .I2(pState[7]), + .I3(pState[8]), + .I4(pState[9]), + .I5(pState[10]), + .O(pStateNxt__2_n_0)); + LUT4 #( + .INIT(16'h0012)) + pStateNxt__3 + (.I0(pStateNxt_n_0), + .I1(pStateNxt__0_n_0), + .I2(pStateNxt__1_n_0), + .I3(pStateNxt__2_n_0), + .O(pStateNxt__3_n_0)); + LUT1 #( + .INIT(2'h1)) + \pState[0]_i_1__0 + (.I0(pStateNxt__3_n_0), + .O(\pState[0]_i_1__0_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFC8)) + \pState[10]_i_1__0 + (.I0(\pState[10]_i_3__0_n_0 ), + .I1(iIn_q_i_3__0_n_0), + .I2(pDelayWaitOvf_reg_n_0), + .I3(\pState[10]_i_4__0_n_0 ), + .I4(\pState[10]_i_5__0_n_0 ), + .I5(\pState[10]_i_6__0_n_0 ), + .O(pStateNxt__4)); + (* SOFT_HLUTNM = "soft_lutpair49" *) + LUT3 #( + .INIT(8'h80)) + \pState[10]_i_2__0 + (.I0(pDelayOvf_reg_n_0), + .I1(pState[6]), + .I2(pStateNxt__3_n_0), + .O(\pState[10]_i_2__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair48" *) + LUT3 #( + .INIT(8'hFE)) + \pState[10]_i_3__0 + (.I0(pState[10]), + .I1(pState[9]), + .I2(pState[2]), + .O(\pState[10]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'h8888888889898988)) + \pState[10]_i_4__0 + (.I0(pState[10]), + .I1(pState[9]), + .I2(pState[2]), + .I3(out), + .I4(pBlankBegin), + .I5(iIn_q_i_3__0_n_0), + .O(\pState[10]_i_4__0_n_0 )); + LUT6 #( + .INIT(64'hFFFFFD00FD00FD00)) + \pState[10]_i_5__0 + (.I0(pTknFlagQ), + .I1(pCtlTknOvf_reg_n_0), + .I2(iIn_q_i_4__0_n_0), + .I3(pState[2]), + .I4(pState[6]), + .I5(pState[8]), + .O(\pState[10]_i_5__0_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFEFEFEEF)) + \pState[10]_i_6__0 + (.I0(pState[5]), + .I1(pState[7]), + .I2(pState[1]), + .I3(iIn_q_i_3__0_n_0), + .I4(\pState[10]_i_3__0_n_0 ), + .I5(iIn_q_i_2__0_n_0), + .O(\pState[10]_i_6__0_n_0 )); + LUT6 #( + .INIT(64'hFFFF4F4400000000)) + \pState[1]_i_1__0 + (.I0(pDelayOvf_reg_n_0), + .I1(pState[6]), + .I2(pTknFlagQ), + .I3(pState[2]), + .I4(pState[0]), + .I5(pStateNxt__3_n_0), + .O(\pState[1]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair41" *) + LUT3 #( + .INIT(8'h80)) + \pState[2]_i_1__0 + (.I0(pBlankBegin), + .I1(pState[1]), + .I2(pStateNxt__3_n_0), + .O(\pState[2]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair48" *) + LUT3 #( + .INIT(8'h80)) + \pState[3]_i_1__0 + (.I0(pState[2]), + .I1(pTknFlagQ), + .I2(pStateNxt__3_n_0), + .O(\pState[3]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair41" *) + LUT5 #( + .INIT(32'h4040F040)) + \pState[4]_i_1__0 + (.I0(\pState[5]_i_2__0_n_0 ), + .I1(pState[3]), + .I2(pStateNxt__3_n_0), + .I3(pState[1]), + .I4(pBlankBegin), + .O(\pState[4]_i_1__0_n_0 )); + LUT5 #( + .INIT(32'h8080F080)) + \pState[5]_i_1__0 + (.I0(pState[3]), + .I1(\pState[5]_i_2__0_n_0 ), + .I2(pStateNxt__3_n_0), + .I3(pState[4]), + .I4(pFoundEyeFlag), + .O(\pState[5]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair43" *) + LUT5 #( + .INIT(32'hFFFFFEFF)) + \pState[5]_i_2__0 + (.I0(\pEyeOpenCnt_reg_n_0_[0] ), + .I1(\pEyeOpenCnt_reg_n_0_[2] ), + .I2(\pEyeOpenCnt_reg_n_0_[3] ), + .I3(\pEyeOpenCnt_reg_n_0_[4] ), + .I4(\pEyeOpenCnt_reg_n_0_[1] ), + .O(\pState[5]_i_2__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair50" *) + LUT2 #( + .INIT(4'h8)) + \pState[6]_i_1__0 + (.I0(pState[5]), + .I1(pStateNxt__3_n_0), + .O(\pState[6]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT5 #( + .INIT(32'hF0202020)) + \pState[7]_i_1__0 + (.I0(pState[8]), + .I1(pDelayCenter_reg_n_0), + .I2(pStateNxt__3_n_0), + .I3(pState[4]), + .I4(pFoundEyeFlag), + .O(\pState[7]_i_1__0_n_0 )); + LUT2 #( + .INIT(4'h8)) + \pState[8]_i_1__0 + (.I0(pState[7]), + .I1(pStateNxt__3_n_0), + .O(\pState[8]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT3 #( + .INIT(8'h80)) + \pState[9]_i_1__0 + (.I0(pDelayCenter_reg_n_0), + .I1(pState[8]), + .I2(pStateNxt__3_n_0), + .O(\pState[9]_i_1__0_n_0 )); + FDSE \pState_reg[0] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[0]_i_1__0_n_0 ), + .Q(pState[0]), + .S(SS)); + FDRE \pState_reg[10] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[10]_i_2__0_n_0 ), + .Q(pState[10]), + .R(SS)); + FDRE \pState_reg[1] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[1]_i_1__0_n_0 ), + .Q(pState[1]), + .R(SS)); + FDRE \pState_reg[2] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[2]_i_1__0_n_0 ), + .Q(pState[2]), + .R(SS)); + FDRE \pState_reg[3] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[3]_i_1__0_n_0 ), + .Q(pState[3]), + .R(SS)); + FDRE \pState_reg[4] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[4]_i_1__0_n_0 ), + .Q(pState[4]), + .R(SS)); + FDRE \pState_reg[5] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[5]_i_1__0_n_0 ), + .Q(pState[5]), + .R(SS)); + FDRE \pState_reg[6] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[6]_i_1__0_n_0 ), + .Q(pState[6]), + .R(SS)); + FDRE \pState_reg[7] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[7]_i_1__0_n_0 ), + .Q(pState[7]), + .R(SS)); + FDRE \pState_reg[8] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[8]_i_1__0_n_0 ), + .Q(pState[8]), + .R(SS)); + FDRE \pState_reg[9] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[9]_i_1__0_n_0 ), + .Q(pState[9]), + .R(SS)); + FDRE pTknFlagQ_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pTknFlag), + .Q(pTknFlagQ), + .R(1'b0)); + LUT5 #( + .INIT(32'h30000808)) + pTknFlag_i_1__0 + (.I0(pTknFlag_i_2__0_n_0), + .I1(\pDataQ_reg_n_0_[8] ), + .I2(\pDataQ_reg_n_0_[0] ), + .I3(pTknFlag_i_3__0_n_0), + .I4(\pDataQ_reg_n_0_[3] ), + .O(pTknFlag0)); + LUT6 #( + .INIT(64'h0002000000000000)) + pTknFlag_i_2__0 + (.I0(\pDataQ_reg_n_0_[4] ), + .I1(\pDataQ_reg_n_0_[5] ), + .I2(\pDataQ_reg_n_0_[7] ), + .I3(\pDataQ_reg_n_0_[1] ), + .I4(\pDataQ_reg_n_0_[2] ), + .I5(\pDataQ_reg_n_0_[6] ), + .O(pTknFlag_i_2__0_n_0)); + LUT6 #( + .INIT(64'h0000000000004000)) + pTknFlag_i_3__0 + (.I0(\pDataQ_reg_n_0_[4] ), + .I1(\pDataQ_reg_n_0_[5] ), + .I2(\pDataQ_reg_n_0_[7] ), + .I3(\pDataQ_reg_n_0_[1] ), + .I4(\pDataQ_reg_n_0_[2] ), + .I5(\pDataQ_reg_n_0_[6] ), + .O(pTknFlag_i_3__0_n_0)); + FDRE pTknFlag_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pTknFlag0), + .Q(pTknFlag), + .R(1'b0)); + LUT3 #( + .INIT(8'h7F)) + \pWrA[4]_i_1 + (.I0(pVld_1), + .I1(pVld_2), + .I2(pVld_0), + .O(pMeRdy_int_reg)); +endmodule + +(* ORIG_REF_NAME = "PhaseAlign" *) +module Arty_Z7_20_dvi2rgb_0_0_PhaseAlign_19 + (pIDLY_CE, + pIDLY_INC, + pIDLY_LD, + pVld_0, + pAlignErr_q_reg, + iIn_q_reg, + pAllVld, + pBitslip_reg, + PixelClk_int, + out, + pVld_2, + pVld_1, + pAlignErr_q, + D, + pIDLY_CE_reg_0, + SS); + output pIDLY_CE; + output pIDLY_INC; + output pIDLY_LD; + output pVld_0; + output pAlignErr_q_reg; + output iIn_q_reg; + output pAllVld; + output pBitslip_reg; + input PixelClk_int; + input [0:0]out; + input pVld_2; + input pVld_1; + input pAlignErr_q; + input [8:0]D; + input [4:0]pIDLY_CE_reg_0; + input [0:0]SS; + + wire [8:0]D; + wire PixelClk_int; + wire [0:0]SS; + wire iIn_q_i_2__1_n_0; + wire iIn_q_i_3__1_n_0; + wire iIn_q_i_4__1_n_0; + wire iIn_q_i_5__1_n_0; + wire iIn_q_reg; + wire [0:0]out; + wire pAlignErr_q; + wire pAlignErr_q_reg; + wire pAligned; + wire pAllVld; + wire pBitslip_reg; + wire pBlankBegin; + wire pBlankBegin0; + wire \pCenterTap[0]_i_1_n_0 ; + wire \pCenterTap[1]_i_1__1_n_0 ; + wire \pCenterTap[2]_i_1__1_n_0 ; + wire \pCenterTap[3]_i_1__1_n_0 ; + wire \pCenterTap[3]_i_2__1_n_0 ; + wire \pCenterTap[4]_i_1__1_n_0 ; + wire \pCenterTap[5]_i_1__1_n_0 ; + wire \pCenterTap[5]_i_2__1_n_0 ; + wire \pCenterTap[5]_i_3__1_n_0 ; + wire \pCenterTap[5]_i_5__1_n_0 ; + wire \pCenterTap_reg_n_0_[0] ; + wire \pCenterTap_reg_n_0_[1] ; + wire \pCenterTap_reg_n_0_[2] ; + wire \pCenterTap_reg_n_0_[3] ; + wire \pCenterTap_reg_n_0_[4] ; + wire \pCenterTap_reg_n_0_[5] ; + wire \pCtlTknCnt[6]_i_3__1_n_0 ; + wire \pCtlTknCnt[6]_i_4__1_n_0 ; + wire [6:0]pCtlTknCnt_reg__0; + wire pCtlTknOvf_i_1__1_n_0; + wire pCtlTknOvf_i_2__1_n_0; + wire pCtlTknOvf_reg_n_0; + wire pCtlTknRst; + wire \pDataQ_reg_n_0_[0] ; + wire \pDataQ_reg_n_0_[1] ; + wire \pDataQ_reg_n_0_[2] ; + wire \pDataQ_reg_n_0_[3] ; + wire \pDataQ_reg_n_0_[4] ; + wire \pDataQ_reg_n_0_[5] ; + wire \pDataQ_reg_n_0_[6] ; + wire \pDataQ_reg_n_0_[7] ; + wire \pDataQ_reg_n_0_[8] ; + wire pDelayCenter_i_1__1_n_0; + wire pDelayCenter_i_2__1_n_0; + wire pDelayCenter_reg_n_0; + wire pDelayOvf_i_1__1_n_0; + wire pDelayOvf_reg_n_0; + wire [1:0]pDelayWaitCnt; + wire \pDelayWaitCnt[0]_i_1_n_0 ; + wire \pDelayWaitCnt[0]_i_2__1_n_0 ; + wire \pDelayWaitCnt[1]_i_1_n_0 ; + wire pDelayWaitOvf_i_1__1_n_0; + wire pDelayWaitOvf_i_2__1_n_0; + wire pDelayWaitOvf_i_3__1_n_0; + wire pDelayWaitOvf_reg_n_0; + wire pError; + wire \pEyeOpenCnt[0]_i_1__1_n_0 ; + wire \pEyeOpenCnt[1]_i_1__1_n_0 ; + wire \pEyeOpenCnt[2]_i_1__1_n_0 ; + wire \pEyeOpenCnt[3]_i_1__1_n_0 ; + wire \pEyeOpenCnt[4]_i_1__1_n_0 ; + wire \pEyeOpenCnt[4]_i_2__1_n_0 ; + wire \pEyeOpenCnt[4]_i_3__1_n_0 ; + wire \pEyeOpenCnt_reg_n_0_[0] ; + wire \pEyeOpenCnt_reg_n_0_[1] ; + wire \pEyeOpenCnt_reg_n_0_[2] ; + wire \pEyeOpenCnt_reg_n_0_[3] ; + wire \pEyeOpenCnt_reg_n_0_[4] ; + wire pEyeOpenEn__5; + wire pEyeOpenRst; + wire pFoundEyeFlag; + wire pFoundEyeFlag_i_1__1_n_0; + wire pFoundEyeFlag_i_2__1_n_0; + wire pFoundEyeFlag_i_3__1_n_0; + wire pFoundEyeFlag_i_4__1_n_0; + wire pFoundJtrFlag; + wire pFoundJtrFlag_i_1__1_n_0; + wire pIDLY_CE; + wire pIDLY_CE_1; + wire [4:0]pIDLY_CE_reg_0; + wire \pIDLY_CNT_Q_reg_n_0_[0] ; + wire \pIDLY_CNT_Q_reg_n_0_[1] ; + wire \pIDLY_CNT_Q_reg_n_0_[2] ; + wire \pIDLY_CNT_Q_reg_n_0_[3] ; + wire \pIDLY_CNT_Q_reg_n_0_[4] ; + wire pIDLY_INC; + wire pIDLY_INC_i_1__1_n_0; + wire pIDLY_LD; + wire pIDLY_LD_0; + wire pIDLY_LD_i_2__1_n_0; + wire [10:0]pState; + wire pStateNxt__0_n_0; + wire pStateNxt__1_n_0; + wire pStateNxt__2_n_0; + wire pStateNxt__3_n_0; + wire pStateNxt__4; + wire pStateNxt_n_0; + wire \pState[0]_i_1__1_n_0 ; + wire \pState[10]_i_2__1_n_0 ; + wire \pState[10]_i_3__1_n_0 ; + wire \pState[10]_i_4__1_n_0 ; + wire \pState[10]_i_5__1_n_0 ; + wire \pState[10]_i_6__1_n_0 ; + wire \pState[1]_i_1__1_n_0 ; + wire \pState[2]_i_1__1_n_0 ; + wire \pState[3]_i_1__1_n_0 ; + wire \pState[4]_i_1__1_n_0 ; + wire \pState[5]_i_1__1_n_0 ; + wire \pState[5]_i_2__1_n_0 ; + wire \pState[6]_i_1__1_n_0 ; + wire \pState[7]_i_1__1_n_0 ; + wire \pState[8]_i_1__1_n_0 ; + wire \pState[9]_i_1__1_n_0 ; + wire pTknFlag; + wire pTknFlag0; + wire pTknFlagQ; + wire pTknFlag_i_2__1_n_0; + wire pTknFlag_i_3__1_n_0; + wire pVld_0; + wire pVld_1; + wire pVld_2; + wire [6:0]p_0_in; + wire p_2_in; + wire [5:4]plusOp__16; + + LUT6 #( + .INIT(64'hFFFFFFFEFFFEFFFF)) + iIn_q_i_1__1 + (.I0(iIn_q_i_2__1_n_0), + .I1(iIn_q_i_3__1_n_0), + .I2(iIn_q_i_4__1_n_0), + .I3(iIn_q_i_5__1_n_0), + .I4(pState[1]), + .I5(pState[2]), + .O(iIn_q_reg)); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT3 #( + .INIT(8'hFE)) + iIn_q_i_2__1 + (.I0(pState[4]), + .I1(pState[0]), + .I2(pState[3]), + .O(iIn_q_i_2__1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT2 #( + .INIT(4'hE)) + iIn_q_i_3__1 + (.I0(pState[6]), + .I1(pState[8]), + .O(iIn_q_i_3__1_n_0)); + LUT2 #( + .INIT(4'hE)) + iIn_q_i_4__1 + (.I0(pState[9]), + .I1(pState[10]), + .O(iIn_q_i_4__1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT2 #( + .INIT(4'hE)) + iIn_q_i_5__1 + (.I0(pState[5]), + .I1(pState[7]), + .O(iIn_q_i_5__1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT4 #( + .INIT(16'h0004)) + pAligned_i_1__1 + (.I0(pState[2]), + .I1(pState[9]), + .I2(pState[10]), + .I3(\pCtlTknCnt[6]_i_3__1_n_0 ), + .O(pAligned)); + FDRE pAligned_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pAligned), + .Q(pVld_0), + .R(1'b0)); + LUT2 #( + .INIT(4'h2)) + pBitslip_i_1__1 + (.I0(pAlignErr_q_reg), + .I1(pAlignErr_q), + .O(pBitslip_reg)); + LUT2 #( + .INIT(4'h2)) + pBlankBegin_i_1__1 + (.I0(pTknFlag), + .I1(pTknFlagQ), + .O(pBlankBegin0)); + FDRE pBlankBegin_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pBlankBegin0), + .Q(pBlankBegin), + .R(1'b0)); + LUT6 #( + .INIT(64'hAAAAAAA5AAAAAFBA)) + \pCenterTap[0]_i_1 + (.I0(\pCenterTap_reg_n_0_[0] ), + .I1(pFoundEyeFlag), + .I2(pState[4]), + .I3(pState[0]), + .I4(\pCenterTap[5]_i_3__1_n_0 ), + .I5(pState[3]), + .O(\pCenterTap[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT5 #( + .INIT(32'hFF606060)) + \pCenterTap[1]_i_1__1 + (.I0(\pCenterTap_reg_n_0_[0] ), + .I1(\pCenterTap_reg_n_0_[1] ), + .I2(\pCenterTap[5]_i_5__1_n_0 ), + .I3(\pIDLY_CNT_Q_reg_n_0_[0] ), + .I4(pEyeOpenRst), + .O(\pCenterTap[1]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hFFFF780078007800)) + \pCenterTap[2]_i_1__1 + (.I0(\pCenterTap_reg_n_0_[1] ), + .I1(\pCenterTap_reg_n_0_[0] ), + .I2(\pCenterTap_reg_n_0_[2] ), + .I3(\pCenterTap[5]_i_5__1_n_0 ), + .I4(\pIDLY_CNT_Q_reg_n_0_[1] ), + .I5(pEyeOpenRst), + .O(\pCenterTap[2]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hFFFF780078007800)) + \pCenterTap[3]_i_1__1 + (.I0(\pCenterTap_reg_n_0_[2] ), + .I1(\pCenterTap[3]_i_2__1_n_0 ), + .I2(\pCenterTap_reg_n_0_[3] ), + .I3(\pCenterTap[5]_i_5__1_n_0 ), + .I4(\pIDLY_CNT_Q_reg_n_0_[2] ), + .I5(pEyeOpenRst), + .O(\pCenterTap[3]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT2 #( + .INIT(4'h8)) + \pCenterTap[3]_i_2__1 + (.I0(\pCenterTap_reg_n_0_[0] ), + .I1(\pCenterTap_reg_n_0_[1] ), + .O(\pCenterTap[3]_i_2__1_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \pCenterTap[4]_i_1__1 + (.I0(plusOp__16[4]), + .I1(\pCenterTap[5]_i_5__1_n_0 ), + .I2(\pIDLY_CNT_Q_reg_n_0_[3] ), + .I3(pEyeOpenRst), + .O(\pCenterTap[4]_i_1__1_n_0 )); + LUT5 #( + .INIT(32'h7FFF8000)) + \pCenterTap[4]_i_2__1 + (.I0(\pCenterTap_reg_n_0_[0] ), + .I1(\pCenterTap_reg_n_0_[1] ), + .I2(\pCenterTap_reg_n_0_[2] ), + .I3(\pCenterTap_reg_n_0_[3] ), + .I4(\pCenterTap_reg_n_0_[4] ), + .O(plusOp__16[4])); + LUT5 #( + .INIT(32'h00030034)) + \pCenterTap[5]_i_1__1 + (.I0(pFoundEyeFlag), + .I1(pState[4]), + .I2(pState[0]), + .I3(\pCenterTap[5]_i_3__1_n_0 ), + .I4(pState[3]), + .O(\pCenterTap[5]_i_1__1_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \pCenterTap[5]_i_2__1 + (.I0(plusOp__16[5]), + .I1(\pCenterTap[5]_i_5__1_n_0 ), + .I2(\pIDLY_CNT_Q_reg_n_0_[4] ), + .I3(pEyeOpenRst), + .O(\pCenterTap[5]_i_2__1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \pCenterTap[5]_i_3__1 + (.I0(pState[5]), + .I1(pState[7]), + .I2(pState[8]), + .I3(pState[6]), + .I4(pState[1]), + .I5(\pState[10]_i_3__1_n_0 ), + .O(\pCenterTap[5]_i_3__1_n_0 )); + LUT6 #( + .INIT(64'h7FFFFFFF80000000)) + \pCenterTap[5]_i_4__1 + (.I0(\pCenterTap_reg_n_0_[0] ), + .I1(\pCenterTap_reg_n_0_[1] ), + .I2(\pCenterTap_reg_n_0_[4] ), + .I3(\pCenterTap_reg_n_0_[3] ), + .I4(\pCenterTap_reg_n_0_[2] ), + .I5(\pCenterTap_reg_n_0_[5] ), + .O(plusOp__16[5])); + LUT6 #( + .INIT(64'hFFFFFFFEFEFEFFFF)) + \pCenterTap[5]_i_5__1 + (.I0(pState[3]), + .I1(pIDLY_LD_i_2__1_n_0), + .I2(\pState[10]_i_3__1_n_0 ), + .I3(pFoundEyeFlag), + .I4(pState[0]), + .I5(pState[4]), + .O(\pCenterTap[5]_i_5__1_n_0 )); + LUT6 #( + .INIT(64'h0000010000010100)) + \pCenterTap[5]_i_6__1 + (.I0(pState[3]), + .I1(pIDLY_LD_i_2__1_n_0), + .I2(\pState[10]_i_3__1_n_0 ), + .I3(pState[0]), + .I4(pState[4]), + .I5(pFoundEyeFlag), + .O(pEyeOpenRst)); + FDRE \pCenterTap_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(\pCenterTap[0]_i_1_n_0 ), + .Q(\pCenterTap_reg_n_0_[0] ), + .R(1'b0)); + FDRE \pCenterTap_reg[1] + (.C(PixelClk_int), + .CE(\pCenterTap[5]_i_1__1_n_0 ), + .D(\pCenterTap[1]_i_1__1_n_0 ), + .Q(\pCenterTap_reg_n_0_[1] ), + .R(1'b0)); + FDRE \pCenterTap_reg[2] + (.C(PixelClk_int), + .CE(\pCenterTap[5]_i_1__1_n_0 ), + .D(\pCenterTap[2]_i_1__1_n_0 ), + .Q(\pCenterTap_reg_n_0_[2] ), + .R(1'b0)); + FDRE \pCenterTap_reg[3] + (.C(PixelClk_int), + .CE(\pCenterTap[5]_i_1__1_n_0 ), + .D(\pCenterTap[3]_i_1__1_n_0 ), + .Q(\pCenterTap_reg_n_0_[3] ), + .R(1'b0)); + FDRE \pCenterTap_reg[4] + (.C(PixelClk_int), + .CE(\pCenterTap[5]_i_1__1_n_0 ), + .D(\pCenterTap[4]_i_1__1_n_0 ), + .Q(\pCenterTap_reg_n_0_[4] ), + .R(1'b0)); + FDRE \pCenterTap_reg[5] + (.C(PixelClk_int), + .CE(\pCenterTap[5]_i_1__1_n_0 ), + .D(\pCenterTap[5]_i_2__1_n_0 ), + .Q(\pCenterTap_reg_n_0_[5] ), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT1 #( + .INIT(2'h1)) + \pCtlTknCnt[0]_i_1__1 + (.I0(pCtlTknCnt_reg__0[0]), + .O(p_0_in[0])); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT2 #( + .INIT(4'h6)) + \pCtlTknCnt[1]_i_1__1 + (.I0(pCtlTknCnt_reg__0[0]), + .I1(pCtlTknCnt_reg__0[1]), + .O(p_0_in[1])); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT3 #( + .INIT(8'h78)) + \pCtlTknCnt[2]_i_1__1 + (.I0(pCtlTknCnt_reg__0[1]), + .I1(pCtlTknCnt_reg__0[0]), + .I2(pCtlTknCnt_reg__0[2]), + .O(p_0_in[2])); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT4 #( + .INIT(16'h7F80)) + \pCtlTknCnt[3]_i_1__1 + (.I0(pCtlTknCnt_reg__0[2]), + .I1(pCtlTknCnt_reg__0[0]), + .I2(pCtlTknCnt_reg__0[1]), + .I3(pCtlTknCnt_reg__0[3]), + .O(p_0_in[3])); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \pCtlTknCnt[4]_i_1__1 + (.I0(pCtlTknCnt_reg__0[3]), + .I1(pCtlTknCnt_reg__0[1]), + .I2(pCtlTknCnt_reg__0[0]), + .I3(pCtlTknCnt_reg__0[2]), + .I4(pCtlTknCnt_reg__0[4]), + .O(p_0_in[4])); + LUT6 #( + .INIT(64'h7FFFFFFF80000000)) + \pCtlTknCnt[5]_i_1__1 + (.I0(pCtlTknCnt_reg__0[4]), + .I1(pCtlTknCnt_reg__0[2]), + .I2(pCtlTknCnt_reg__0[0]), + .I3(pCtlTknCnt_reg__0[1]), + .I4(pCtlTknCnt_reg__0[3]), + .I5(pCtlTknCnt_reg__0[5]), + .O(p_0_in[5])); + LUT4 #( + .INIT(16'hFFFD)) + \pCtlTknCnt[6]_i_1__1 + (.I0(pState[2]), + .I1(pState[9]), + .I2(pState[10]), + .I3(\pCtlTknCnt[6]_i_3__1_n_0 ), + .O(pCtlTknRst)); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT4 #( + .INIT(16'h7F80)) + \pCtlTknCnt[6]_i_2__1 + (.I0(\pCtlTknCnt[6]_i_4__1_n_0 ), + .I1(pCtlTknCnt_reg__0[4]), + .I2(pCtlTknCnt_reg__0[5]), + .I3(pCtlTknCnt_reg__0[6]), + .O(p_0_in[6])); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \pCtlTknCnt[6]_i_3__1 + (.I0(iIn_q_i_2__1_n_0), + .I1(pState[5]), + .I2(pState[7]), + .I3(pState[8]), + .I4(pState[6]), + .I5(pState[1]), + .O(\pCtlTknCnt[6]_i_3__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT4 #( + .INIT(16'h8000)) + \pCtlTknCnt[6]_i_4__1 + (.I0(pCtlTknCnt_reg__0[2]), + .I1(pCtlTknCnt_reg__0[0]), + .I2(pCtlTknCnt_reg__0[1]), + .I3(pCtlTknCnt_reg__0[3]), + .O(\pCtlTknCnt[6]_i_4__1_n_0 )); + FDRE \pCtlTknCnt_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in[0]), + .Q(pCtlTknCnt_reg__0[0]), + .R(pCtlTknRst)); + FDRE \pCtlTknCnt_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in[1]), + .Q(pCtlTknCnt_reg__0[1]), + .R(pCtlTknRst)); + FDRE \pCtlTknCnt_reg[2] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in[2]), + .Q(pCtlTknCnt_reg__0[2]), + .R(pCtlTknRst)); + FDRE \pCtlTknCnt_reg[3] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in[3]), + .Q(pCtlTknCnt_reg__0[3]), + .R(pCtlTknRst)); + FDRE \pCtlTknCnt_reg[4] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in[4]), + .Q(pCtlTknCnt_reg__0[4]), + .R(pCtlTknRst)); + FDRE \pCtlTknCnt_reg[5] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in[5]), + .Q(pCtlTknCnt_reg__0[5]), + .R(pCtlTknRst)); + FDRE \pCtlTknCnt_reg[6] + (.C(PixelClk_int), + .CE(1'b1), + .D(p_0_in[6]), + .Q(pCtlTknCnt_reg__0[6]), + .R(pCtlTknRst)); + LUT6 #( + .INIT(64'hAAAAAAAEAAAAAAA2)) + pCtlTknOvf_i_1__1 + (.I0(pCtlTknOvf_reg_n_0), + .I1(pState[2]), + .I2(pState[9]), + .I3(pState[10]), + .I4(\pCtlTknCnt[6]_i_3__1_n_0 ), + .I5(pCtlTknOvf_i_2__1_n_0), + .O(pCtlTknOvf_i_1__1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT4 #( + .INIT(16'h8000)) + pCtlTknOvf_i_2__1 + (.I0(pCtlTknCnt_reg__0[4]), + .I1(pCtlTknCnt_reg__0[5]), + .I2(pCtlTknCnt_reg__0[6]), + .I3(\pCtlTknCnt[6]_i_4__1_n_0 ), + .O(pCtlTknOvf_i_2__1_n_0)); + FDRE pCtlTknOvf_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pCtlTknOvf_i_1__1_n_0), + .Q(pCtlTknOvf_reg_n_0), + .R(1'b0)); + FDRE \pDataQ_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(D[0]), + .Q(\pDataQ_reg_n_0_[0] ), + .R(1'b0)); + FDRE \pDataQ_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .D(D[1]), + .Q(\pDataQ_reg_n_0_[1] ), + .R(1'b0)); + FDRE \pDataQ_reg[2] + (.C(PixelClk_int), + .CE(1'b1), + .D(D[2]), + .Q(\pDataQ_reg_n_0_[2] ), + .R(1'b0)); + FDRE \pDataQ_reg[3] + (.C(PixelClk_int), + .CE(1'b1), + .D(D[3]), + .Q(\pDataQ_reg_n_0_[3] ), + .R(1'b0)); + FDRE \pDataQ_reg[4] + (.C(PixelClk_int), + .CE(1'b1), + .D(D[4]), + .Q(\pDataQ_reg_n_0_[4] ), + .R(1'b0)); + FDRE \pDataQ_reg[5] + (.C(PixelClk_int), + .CE(1'b1), + .D(D[5]), + .Q(\pDataQ_reg_n_0_[5] ), + .R(1'b0)); + FDRE \pDataQ_reg[6] + (.C(PixelClk_int), + .CE(1'b1), + .D(D[6]), + .Q(\pDataQ_reg_n_0_[6] ), + .R(1'b0)); + FDRE \pDataQ_reg[7] + (.C(PixelClk_int), + .CE(1'b1), + .D(D[7]), + .Q(\pDataQ_reg_n_0_[7] ), + .R(1'b0)); + FDRE \pDataQ_reg[8] + (.C(PixelClk_int), + .CE(1'b1), + .D(D[8]), + .Q(\pDataQ_reg_n_0_[8] ), + .R(1'b0)); + LUT5 #( + .INIT(32'h82000082)) + pDelayCenter_i_1__1 + (.I0(pDelayCenter_i_2__1_n_0), + .I1(\pCenterTap_reg_n_0_[5] ), + .I2(\pIDLY_CNT_Q_reg_n_0_[4] ), + .I3(\pCenterTap_reg_n_0_[4] ), + .I4(\pIDLY_CNT_Q_reg_n_0_[3] ), + .O(pDelayCenter_i_1__1_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + pDelayCenter_i_2__1 + (.I0(\pCenterTap_reg_n_0_[3] ), + .I1(\pIDLY_CNT_Q_reg_n_0_[2] ), + .I2(\pCenterTap_reg_n_0_[2] ), + .I3(\pIDLY_CNT_Q_reg_n_0_[1] ), + .I4(\pIDLY_CNT_Q_reg_n_0_[0] ), + .I5(\pCenterTap_reg_n_0_[1] ), + .O(pDelayCenter_i_2__1_n_0)); + FDRE pDelayCenter_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pDelayCenter_i_1__1_n_0), + .Q(pDelayCenter_reg_n_0), + .R(1'b0)); + LUT5 #( + .INIT(32'h00000001)) + pDelayOvf_i_1__1 + (.I0(\pIDLY_CNT_Q_reg_n_0_[0] ), + .I1(\pIDLY_CNT_Q_reg_n_0_[1] ), + .I2(\pIDLY_CNT_Q_reg_n_0_[2] ), + .I3(\pIDLY_CNT_Q_reg_n_0_[4] ), + .I4(\pIDLY_CNT_Q_reg_n_0_[3] ), + .O(pDelayOvf_i_1__1_n_0)); + FDRE pDelayOvf_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pDelayOvf_i_1__1_n_0), + .Q(pDelayOvf_reg_n_0), + .R(1'b0)); + LUT6 #( + .INIT(64'h0000001400000000)) + \pDelayWaitCnt[0]_i_1 + (.I0(pDelayWaitCnt[0]), + .I1(pState[6]), + .I2(pState[8]), + .I3(iIn_q_i_5__1_n_0), + .I4(pState[1]), + .I5(\pDelayWaitCnt[0]_i_2__1_n_0 ), + .O(\pDelayWaitCnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000000000000001)) + \pDelayWaitCnt[0]_i_2__1 + (.I0(pState[3]), + .I1(pState[0]), + .I2(pState[4]), + .I3(pState[2]), + .I4(pState[9]), + .I5(pState[10]), + .O(\pDelayWaitCnt[0]_i_2__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT3 #( + .INIT(8'h60)) + \pDelayWaitCnt[1]_i_1 + (.I0(pDelayWaitCnt[1]), + .I1(pDelayWaitCnt[0]), + .I2(p_2_in), + .O(\pDelayWaitCnt[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000000600000000)) + \pDelayWaitCnt[1]_i_2__1 + (.I0(pState[6]), + .I1(pState[8]), + .I2(pState[7]), + .I3(pState[5]), + .I4(pState[1]), + .I5(\pDelayWaitCnt[0]_i_2__1_n_0 ), + .O(p_2_in)); + FDRE \pDelayWaitCnt_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(\pDelayWaitCnt[0]_i_1_n_0 ), + .Q(pDelayWaitCnt[0]), + .R(1'b0)); + FDRE \pDelayWaitCnt_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .D(\pDelayWaitCnt[1]_i_1_n_0 ), + .Q(pDelayWaitCnt[1]), + .R(1'b0)); + LUT6 #( + .INIT(64'hCCFCCCCCCC8CCCCC)) + pDelayWaitOvf_i_1__1 + (.I0(pState[1]), + .I1(pDelayWaitOvf_reg_n_0), + .I2(\pDelayWaitCnt[0]_i_2__1_n_0 ), + .I3(iIn_q_i_5__1_n_0), + .I4(pDelayWaitOvf_i_2__1_n_0), + .I5(pDelayWaitOvf_i_3__1_n_0), + .O(pDelayWaitOvf_i_1__1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT2 #( + .INIT(4'h6)) + pDelayWaitOvf_i_2__1 + (.I0(pState[6]), + .I1(pState[8]), + .O(pDelayWaitOvf_i_2__1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT3 #( + .INIT(8'h04)) + pDelayWaitOvf_i_3__1 + (.I0(pState[1]), + .I1(pDelayWaitCnt[1]), + .I2(pDelayWaitCnt[0]), + .O(pDelayWaitOvf_i_3__1_n_0)); + FDRE pDelayWaitOvf_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pDelayWaitOvf_i_1__1_n_0), + .Q(pDelayWaitOvf_reg_n_0), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT4 #( + .INIT(16'h0004)) + pError_i_1__1 + (.I0(pState[2]), + .I1(pState[10]), + .I2(pState[9]), + .I3(\pCtlTknCnt[6]_i_3__1_n_0 ), + .O(pError)); + FDRE pError_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pError), + .Q(pAlignErr_q_reg), + .R(1'b0)); + LUT6 #( + .INIT(64'hCCCCCCCCCCC3C80C)) + \pEyeOpenCnt[0]_i_1__1 + (.I0(pFoundEyeFlag), + .I1(\pEyeOpenCnt_reg_n_0_[0] ), + .I2(pState[0]), + .I3(pState[4]), + .I4(pState[3]), + .I5(\pCenterTap[5]_i_3__1_n_0 ), + .O(\pEyeOpenCnt[0]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT4 #( + .INIT(16'hBCA0)) + \pEyeOpenCnt[1]_i_1__1 + (.I0(\pEyeOpenCnt[4]_i_2__1_n_0 ), + .I1(\pEyeOpenCnt_reg_n_0_[0] ), + .I2(\pEyeOpenCnt_reg_n_0_[1] ), + .I3(pEyeOpenEn__5), + .O(\pEyeOpenCnt[1]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT5 #( + .INIT(32'hBFC0AA00)) + \pEyeOpenCnt[2]_i_1__1 + (.I0(\pEyeOpenCnt[4]_i_2__1_n_0 ), + .I1(\pEyeOpenCnt_reg_n_0_[1] ), + .I2(\pEyeOpenCnt_reg_n_0_[0] ), + .I3(\pEyeOpenCnt_reg_n_0_[2] ), + .I4(pEyeOpenEn__5), + .O(\pEyeOpenCnt[2]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hBFFFC000AAAA0000)) + \pEyeOpenCnt[3]_i_1__1 + (.I0(\pEyeOpenCnt[4]_i_2__1_n_0 ), + .I1(\pEyeOpenCnt_reg_n_0_[0] ), + .I2(\pEyeOpenCnt_reg_n_0_[1] ), + .I3(\pEyeOpenCnt_reg_n_0_[2] ), + .I4(\pEyeOpenCnt_reg_n_0_[3] ), + .I5(pEyeOpenEn__5), + .O(\pEyeOpenCnt[3]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hBFFFC000AAAA0000)) + \pEyeOpenCnt[4]_i_1__1 + (.I0(\pEyeOpenCnt[4]_i_2__1_n_0 ), + .I1(\pEyeOpenCnt_reg_n_0_[2] ), + .I2(\pEyeOpenCnt_reg_n_0_[3] ), + .I3(\pEyeOpenCnt[4]_i_3__1_n_0 ), + .I4(\pEyeOpenCnt_reg_n_0_[4] ), + .I5(pEyeOpenEn__5), + .O(\pEyeOpenCnt[4]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFEFEFEFDFD)) + \pEyeOpenCnt[4]_i_2__1 + (.I0(pState[3]), + .I1(pIDLY_LD_i_2__1_n_0), + .I2(\pState[10]_i_3__1_n_0 ), + .I3(pFoundEyeFlag), + .I4(pState[0]), + .I5(pState[4]), + .O(\pEyeOpenCnt[4]_i_2__1_n_0 )); + LUT2 #( + .INIT(4'h8)) + \pEyeOpenCnt[4]_i_3__1 + (.I0(\pEyeOpenCnt_reg_n_0_[0] ), + .I1(\pEyeOpenCnt_reg_n_0_[1] ), + .O(\pEyeOpenCnt[4]_i_3__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT5 #( + .INIT(32'h00000010)) + \pEyeOpenCnt[4]_i_4__1 + (.I0(pState[0]), + .I1(pState[4]), + .I2(pState[3]), + .I3(\pState[10]_i_3__1_n_0 ), + .I4(pIDLY_LD_i_2__1_n_0), + .O(pEyeOpenEn__5)); + FDRE \pEyeOpenCnt_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(\pEyeOpenCnt[0]_i_1__1_n_0 ), + .Q(\pEyeOpenCnt_reg_n_0_[0] ), + .R(1'b0)); + FDRE \pEyeOpenCnt_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .D(\pEyeOpenCnt[1]_i_1__1_n_0 ), + .Q(\pEyeOpenCnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE \pEyeOpenCnt_reg[2] + (.C(PixelClk_int), + .CE(1'b1), + .D(\pEyeOpenCnt[2]_i_1__1_n_0 ), + .Q(\pEyeOpenCnt_reg_n_0_[2] ), + .R(1'b0)); + FDRE \pEyeOpenCnt_reg[3] + (.C(PixelClk_int), + .CE(1'b1), + .D(\pEyeOpenCnt[3]_i_1__1_n_0 ), + .Q(\pEyeOpenCnt_reg_n_0_[3] ), + .R(1'b0)); + FDRE \pEyeOpenCnt_reg[4] + (.C(PixelClk_int), + .CE(1'b1), + .D(\pEyeOpenCnt[4]_i_1__1_n_0 ), + .Q(\pEyeOpenCnt_reg_n_0_[4] ), + .R(1'b0)); + LUT3 #( + .INIT(8'h80)) + pFIFO_reg_0_31_0_5_i_1 + (.I0(pVld_0), + .I1(pVld_2), + .I2(pVld_1), + .O(pAllVld)); + LUT5 #( + .INIT(32'hABBBA888)) + pFoundEyeFlag_i_1__1 + (.I0(pFoundEyeFlag_i_2__1_n_0), + .I1(pIDLY_LD_0), + .I2(pEyeOpenEn__5), + .I3(pFoundEyeFlag_i_3__1_n_0), + .I4(pFoundEyeFlag), + .O(pFoundEyeFlag_i_1__1_n_0)); + LUT6 #( + .INIT(64'h1000004000000040)) + pFoundEyeFlag_i_2__1 + (.I0(pFoundEyeFlag_i_4__1_n_0), + .I1(\pEyeOpenCnt_reg_n_0_[4] ), + .I2(pState[3]), + .I3(\pEyeOpenCnt_reg_n_0_[0] ), + .I4(\pEyeOpenCnt_reg_n_0_[1] ), + .I5(pFoundJtrFlag), + .O(pFoundEyeFlag_i_2__1_n_0)); + LUT6 #( + .INIT(64'h0100001000000010)) + pFoundEyeFlag_i_3__1 + (.I0(\pEyeOpenCnt_reg_n_0_[2] ), + .I1(\pEyeOpenCnt_reg_n_0_[3] ), + .I2(\pEyeOpenCnt_reg_n_0_[4] ), + .I3(\pEyeOpenCnt_reg_n_0_[0] ), + .I4(\pEyeOpenCnt_reg_n_0_[1] ), + .I5(pFoundJtrFlag), + .O(pFoundEyeFlag_i_3__1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT2 #( + .INIT(4'hE)) + pFoundEyeFlag_i_4__1 + (.I0(\pEyeOpenCnt_reg_n_0_[2] ), + .I1(\pEyeOpenCnt_reg_n_0_[3] ), + .O(pFoundEyeFlag_i_4__1_n_0)); + FDRE pFoundEyeFlag_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pFoundEyeFlag_i_1__1_n_0), + .Q(pFoundEyeFlag), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT5 #( + .INIT(32'hFEFF0010)) + pFoundJtrFlag_i_1__1 + (.I0(pState[3]), + .I1(\pCenterTap[5]_i_3__1_n_0 ), + .I2(pState[4]), + .I3(pState[0]), + .I4(pFoundJtrFlag), + .O(pFoundJtrFlag_i_1__1_n_0)); + FDRE pFoundJtrFlag_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pFoundJtrFlag_i_1__1_n_0), + .Q(pFoundJtrFlag), + .R(1'b0)); + LUT6 #( + .INIT(64'h0000000200020000)) + pIDLY_CE_i_1__1 + (.I0(\pDelayWaitCnt[0]_i_2__1_n_0 ), + .I1(pState[1]), + .I2(pState[6]), + .I3(pState[8]), + .I4(pState[5]), + .I5(pState[7]), + .O(pIDLY_CE_1)); + FDRE pIDLY_CE_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pIDLY_CE_1), + .Q(pIDLY_CE), + .R(1'b0)); + FDRE \pIDLY_CNT_Q_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(pIDLY_CE_reg_0[0]), + .Q(\pIDLY_CNT_Q_reg_n_0_[0] ), + .R(1'b0)); + FDRE \pIDLY_CNT_Q_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .D(pIDLY_CE_reg_0[1]), + .Q(\pIDLY_CNT_Q_reg_n_0_[1] ), + .R(1'b0)); + FDRE \pIDLY_CNT_Q_reg[2] + (.C(PixelClk_int), + .CE(1'b1), + .D(pIDLY_CE_reg_0[2]), + .Q(\pIDLY_CNT_Q_reg_n_0_[2] ), + .R(1'b0)); + FDRE \pIDLY_CNT_Q_reg[3] + (.C(PixelClk_int), + .CE(1'b1), + .D(pIDLY_CE_reg_0[3]), + .Q(\pIDLY_CNT_Q_reg_n_0_[3] ), + .R(1'b0)); + FDRE \pIDLY_CNT_Q_reg[4] + (.C(PixelClk_int), + .CE(1'b1), + .D(pIDLY_CE_reg_0[4]), + .Q(\pIDLY_CNT_Q_reg_n_0_[4] ), + .R(1'b0)); + LUT6 #( + .INIT(64'hAAAAAAA2AAAEAAAA)) + pIDLY_INC_i_1__1 + (.I0(pIDLY_INC), + .I1(\pDelayWaitCnt[0]_i_2__1_n_0 ), + .I2(pState[1]), + .I3(iIn_q_i_3__1_n_0), + .I4(pState[5]), + .I5(pState[7]), + .O(pIDLY_INC_i_1__1_n_0)); + FDRE pIDLY_INC_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pIDLY_INC_i_1__1_n_0), + .Q(pIDLY_INC), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT5 #( + .INIT(32'h00000004)) + pIDLY_LD_i_1__1 + (.I0(pState[4]), + .I1(pState[0]), + .I2(pState[3]), + .I3(pIDLY_LD_i_2__1_n_0), + .I4(\pState[10]_i_3__1_n_0 ), + .O(pIDLY_LD_0)); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT5 #( + .INIT(32'hFFFFFFFE)) + pIDLY_LD_i_2__1 + (.I0(pState[1]), + .I1(pState[6]), + .I2(pState[8]), + .I3(pState[7]), + .I4(pState[5]), + .O(pIDLY_LD_i_2__1_n_0)); + FDRE pIDLY_LD_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pIDLY_LD_0), + .Q(pIDLY_LD), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT5 #( + .INIT(32'h00010116)) + pStateNxt + (.I0(pState[0]), + .I1(pState[1]), + .I2(pState[2]), + .I3(pState[3]), + .I4(pState[4]), + .O(pStateNxt_n_0)); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT5 #( + .INIT(32'hFFFEFEE8)) + pStateNxt__0 + (.I0(pState[0]), + .I1(pState[1]), + .I2(pState[2]), + .I3(pState[3]), + .I4(pState[4]), + .O(pStateNxt__0_n_0)); + LUT6 #( + .INIT(64'h0000000100010116)) + pStateNxt__1 + (.I0(pState[5]), + .I1(pState[6]), + .I2(pState[7]), + .I3(pState[8]), + .I4(pState[9]), + .I5(pState[10]), + .O(pStateNxt__1_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFEFFFEFEE8)) + pStateNxt__2 + (.I0(pState[5]), + .I1(pState[6]), + .I2(pState[7]), + .I3(pState[8]), + .I4(pState[9]), + .I5(pState[10]), + .O(pStateNxt__2_n_0)); + LUT4 #( + .INIT(16'h0012)) + pStateNxt__3 + (.I0(pStateNxt_n_0), + .I1(pStateNxt__0_n_0), + .I2(pStateNxt__1_n_0), + .I3(pStateNxt__2_n_0), + .O(pStateNxt__3_n_0)); + LUT1 #( + .INIT(2'h1)) + \pState[0]_i_1__1 + (.I0(pStateNxt__3_n_0), + .O(\pState[0]_i_1__1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFC8)) + \pState[10]_i_1__1 + (.I0(\pState[10]_i_3__1_n_0 ), + .I1(iIn_q_i_3__1_n_0), + .I2(pDelayWaitOvf_reg_n_0), + .I3(\pState[10]_i_4__1_n_0 ), + .I4(\pState[10]_i_5__1_n_0 ), + .I5(\pState[10]_i_6__1_n_0 ), + .O(pStateNxt__4)); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT3 #( + .INIT(8'h80)) + \pState[10]_i_2__1 + (.I0(pDelayOvf_reg_n_0), + .I1(pState[6]), + .I2(pStateNxt__3_n_0), + .O(\pState[10]_i_2__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT3 #( + .INIT(8'hFE)) + \pState[10]_i_3__1 + (.I0(pState[10]), + .I1(pState[9]), + .I2(pState[2]), + .O(\pState[10]_i_3__1_n_0 )); + LUT6 #( + .INIT(64'h8888888889898988)) + \pState[10]_i_4__1 + (.I0(pState[10]), + .I1(pState[9]), + .I2(pState[2]), + .I3(out), + .I4(pBlankBegin), + .I5(iIn_q_i_3__1_n_0), + .O(\pState[10]_i_4__1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFD00FD00FD00)) + \pState[10]_i_5__1 + (.I0(pTknFlagQ), + .I1(pCtlTknOvf_reg_n_0), + .I2(iIn_q_i_4__1_n_0), + .I3(pState[2]), + .I4(pState[6]), + .I5(pState[8]), + .O(\pState[10]_i_5__1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFEFEFEEF)) + \pState[10]_i_6__1 + (.I0(pState[5]), + .I1(pState[7]), + .I2(pState[1]), + .I3(iIn_q_i_3__1_n_0), + .I4(\pState[10]_i_3__1_n_0 ), + .I5(iIn_q_i_2__1_n_0), + .O(\pState[10]_i_6__1_n_0 )); + LUT6 #( + .INIT(64'hFFFF4F4400000000)) + \pState[1]_i_1__1 + (.I0(pDelayOvf_reg_n_0), + .I1(pState[6]), + .I2(pTknFlagQ), + .I3(pState[2]), + .I4(pState[0]), + .I5(pStateNxt__3_n_0), + .O(\pState[1]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT3 #( + .INIT(8'h80)) + \pState[2]_i_1__1 + (.I0(pBlankBegin), + .I1(pState[1]), + .I2(pStateNxt__3_n_0), + .O(\pState[2]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT3 #( + .INIT(8'h80)) + \pState[3]_i_1__1 + (.I0(pState[2]), + .I1(pTknFlagQ), + .I2(pStateNxt__3_n_0), + .O(\pState[3]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT5 #( + .INIT(32'h4040F040)) + \pState[4]_i_1__1 + (.I0(\pState[5]_i_2__1_n_0 ), + .I1(pState[3]), + .I2(pStateNxt__3_n_0), + .I3(pState[1]), + .I4(pBlankBegin), + .O(\pState[4]_i_1__1_n_0 )); + LUT5 #( + .INIT(32'h8080F080)) + \pState[5]_i_1__1 + (.I0(pState[3]), + .I1(\pState[5]_i_2__1_n_0 ), + .I2(pStateNxt__3_n_0), + .I3(pState[4]), + .I4(pFoundEyeFlag), + .O(\pState[5]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT5 #( + .INIT(32'hFFFFFEFF)) + \pState[5]_i_2__1 + (.I0(\pEyeOpenCnt_reg_n_0_[0] ), + .I1(\pEyeOpenCnt_reg_n_0_[2] ), + .I2(\pEyeOpenCnt_reg_n_0_[3] ), + .I3(\pEyeOpenCnt_reg_n_0_[4] ), + .I4(\pEyeOpenCnt_reg_n_0_[1] ), + .O(\pState[5]_i_2__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT2 #( + .INIT(4'h8)) + \pState[6]_i_1__1 + (.I0(pState[5]), + .I1(pStateNxt__3_n_0), + .O(\pState[6]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT5 #( + .INIT(32'hF0202020)) + \pState[7]_i_1__1 + (.I0(pState[8]), + .I1(pDelayCenter_reg_n_0), + .I2(pStateNxt__3_n_0), + .I3(pState[4]), + .I4(pFoundEyeFlag), + .O(\pState[7]_i_1__1_n_0 )); + LUT2 #( + .INIT(4'h8)) + \pState[8]_i_1__1 + (.I0(pState[7]), + .I1(pStateNxt__3_n_0), + .O(\pState[8]_i_1__1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT3 #( + .INIT(8'h80)) + \pState[9]_i_1__1 + (.I0(pDelayCenter_reg_n_0), + .I1(pState[8]), + .I2(pStateNxt__3_n_0), + .O(\pState[9]_i_1__1_n_0 )); + FDSE \pState_reg[0] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[0]_i_1__1_n_0 ), + .Q(pState[0]), + .S(SS)); + FDRE \pState_reg[10] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[10]_i_2__1_n_0 ), + .Q(pState[10]), + .R(SS)); + FDRE \pState_reg[1] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[1]_i_1__1_n_0 ), + .Q(pState[1]), + .R(SS)); + FDRE \pState_reg[2] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[2]_i_1__1_n_0 ), + .Q(pState[2]), + .R(SS)); + FDRE \pState_reg[3] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[3]_i_1__1_n_0 ), + .Q(pState[3]), + .R(SS)); + FDRE \pState_reg[4] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[4]_i_1__1_n_0 ), + .Q(pState[4]), + .R(SS)); + FDRE \pState_reg[5] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[5]_i_1__1_n_0 ), + .Q(pState[5]), + .R(SS)); + FDRE \pState_reg[6] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[6]_i_1__1_n_0 ), + .Q(pState[6]), + .R(SS)); + FDRE \pState_reg[7] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[7]_i_1__1_n_0 ), + .Q(pState[7]), + .R(SS)); + FDRE \pState_reg[8] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[8]_i_1__1_n_0 ), + .Q(pState[8]), + .R(SS)); + FDRE \pState_reg[9] + (.C(PixelClk_int), + .CE(pStateNxt__4), + .D(\pState[9]_i_1__1_n_0 ), + .Q(pState[9]), + .R(SS)); + FDRE pTknFlagQ_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pTknFlag), + .Q(pTknFlagQ), + .R(1'b0)); + LUT5 #( + .INIT(32'h30000808)) + pTknFlag_i_1__1 + (.I0(pTknFlag_i_2__1_n_0), + .I1(\pDataQ_reg_n_0_[8] ), + .I2(\pDataQ_reg_n_0_[0] ), + .I3(pTknFlag_i_3__1_n_0), + .I4(\pDataQ_reg_n_0_[3] ), + .O(pTknFlag0)); + LUT6 #( + .INIT(64'h0002000000000000)) + pTknFlag_i_2__1 + (.I0(\pDataQ_reg_n_0_[4] ), + .I1(\pDataQ_reg_n_0_[5] ), + .I2(\pDataQ_reg_n_0_[7] ), + .I3(\pDataQ_reg_n_0_[1] ), + .I4(\pDataQ_reg_n_0_[2] ), + .I5(\pDataQ_reg_n_0_[6] ), + .O(pTknFlag_i_2__1_n_0)); + LUT6 #( + .INIT(64'h0000000000004000)) + pTknFlag_i_3__1 + (.I0(\pDataQ_reg_n_0_[4] ), + .I1(\pDataQ_reg_n_0_[5] ), + .I2(\pDataQ_reg_n_0_[7] ), + .I3(\pDataQ_reg_n_0_[1] ), + .I4(\pDataQ_reg_n_0_[2] ), + .I5(\pDataQ_reg_n_0_[6] ), + .O(pTknFlag_i_3__1_n_0)); + FDRE pTknFlag_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pTknFlag0), + .Q(pTknFlag), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "ResetBridge" *) +module Arty_Z7_20_dvi2rgb_0_0_ResetBridge + (out, + in0, + PixelClk_int); + output [0:0]out; + input in0; + input PixelClk_int; + + wire PixelClk_int; + (* RTL_KEEP = "true" *) wire aRst_int; + wire [0:0]out; + + assign aRst_int = in0; + Arty_Z7_20_dvi2rgb_0_0_SyncAsync_5 SyncAsyncx + (.AS(aRst_int), + .PixelClk_int(PixelClk_int), + .out(out)); +endmodule + +(* ORIG_REF_NAME = "ResetBridge" *) +module Arty_Z7_20_dvi2rgb_0_0_ResetBridge_2 + (SS, + rDlyRst_reg, + aRst_n, + E, + RST, + RefClk); + output [0:0]SS; + output rDlyRst_reg; + input aRst_n; + input [0:0]E; + input RST; + input RefClk; + + wire [0:0]E; + wire RST; + wire RefClk; + wire [0:0]SS; + (* RTL_KEEP = "true" *) wire aRst_int_0; + wire aRst_n; + wire rDlyRst_reg; + + Arty_Z7_20_dvi2rgb_0_0_SyncAsync_4 SyncAsyncx + (.AS(aRst_int_0), + .E(E), + .RST(RST), + .RefClk(RefClk), + .SS(SS), + .rDlyRst_reg(rDlyRst_reg)); + LUT1 #( + .INIT(2'h1)) + aRst_int_inferred_i_1__0 + (.I0(aRst_n), + .O(aRst_int_0)); +endmodule + +(* ORIG_REF_NAME = "ResetBridge" *) +module Arty_Z7_20_dvi2rgb_0_0_ResetBridge_3 + (out, + aDlyLckd, + RefClk); + output [0:0]out; + input aDlyLckd; + input RefClk; + + wire RefClk; + wire aDlyLckd; + (* RTL_KEEP = "true" *) wire aRst_int; + wire [0:0]out; + + Arty_Z7_20_dvi2rgb_0_0_SyncAsync SyncAsyncx + (.AS(aRst_int), + .RefClk(RefClk), + .out(out)); + LUT1 #( + .INIT(2'h1)) + aRst_int_inferred_i_1 + (.I0(aDlyLckd), + .O(aRst_int)); +endmodule + +(* ORIG_REF_NAME = "ResyncToBUFG" *) +module Arty_Z7_20_dvi2rgb_0_0_ResyncToBUFG + (CLK, + vid_pVDE, + vid_pHSync, + vid_pVSync, + vid_pData, + PixelClk_int, + pVde, + pC0, + pC1, + D); + output CLK; + output vid_pVDE; + output vid_pHSync; + output vid_pVSync; + output [23:0]vid_pData; + input PixelClk_int; + input pVde; + input pC0; + input pC1; + input [23:0]D; + + wire CLK; + wire [23:0]D; + wire PixelClk_int; + wire pC0; + wire pC1; + wire pVde; + wire [23:0]vid_pData; + wire vid_pHSync; + wire vid_pVDE; + wire vid_pVSync; + + (* box_type = "PRIMITIVE" *) + BUFG InstBUFG + (.I(PixelClk_int), + .O(CLK)); + FDRE \poData_reg[0] + (.C(CLK), + .CE(1'b1), + .D(D[0]), + .Q(vid_pData[0]), + .R(1'b0)); + FDRE \poData_reg[10] + (.C(CLK), + .CE(1'b1), + .D(D[10]), + .Q(vid_pData[10]), + .R(1'b0)); + FDRE \poData_reg[11] + (.C(CLK), + .CE(1'b1), + .D(D[11]), + .Q(vid_pData[11]), + .R(1'b0)); + FDRE \poData_reg[12] + (.C(CLK), + .CE(1'b1), + .D(D[12]), + .Q(vid_pData[12]), + .R(1'b0)); + FDRE \poData_reg[13] + (.C(CLK), + .CE(1'b1), + .D(D[13]), + .Q(vid_pData[13]), + .R(1'b0)); + FDRE \poData_reg[14] + (.C(CLK), + .CE(1'b1), + .D(D[14]), + .Q(vid_pData[14]), + .R(1'b0)); + FDRE \poData_reg[15] + (.C(CLK), + .CE(1'b1), + .D(D[15]), + .Q(vid_pData[15]), + .R(1'b0)); + FDRE \poData_reg[16] + (.C(CLK), + .CE(1'b1), + .D(D[16]), + .Q(vid_pData[16]), + .R(1'b0)); + FDRE \poData_reg[17] + (.C(CLK), + .CE(1'b1), + .D(D[17]), + .Q(vid_pData[17]), + .R(1'b0)); + FDRE \poData_reg[18] + (.C(CLK), + .CE(1'b1), + .D(D[18]), + .Q(vid_pData[18]), + .R(1'b0)); + FDRE \poData_reg[19] + (.C(CLK), + .CE(1'b1), + .D(D[19]), + .Q(vid_pData[19]), + .R(1'b0)); + FDRE \poData_reg[1] + (.C(CLK), + .CE(1'b1), + .D(D[1]), + .Q(vid_pData[1]), + .R(1'b0)); + FDRE \poData_reg[20] + (.C(CLK), + .CE(1'b1), + .D(D[20]), + .Q(vid_pData[20]), + .R(1'b0)); + FDRE \poData_reg[21] + (.C(CLK), + .CE(1'b1), + .D(D[21]), + .Q(vid_pData[21]), + .R(1'b0)); + FDRE \poData_reg[22] + (.C(CLK), + .CE(1'b1), + .D(D[22]), + .Q(vid_pData[22]), + .R(1'b0)); + FDRE \poData_reg[23] + (.C(CLK), + .CE(1'b1), + .D(D[23]), + .Q(vid_pData[23]), + .R(1'b0)); + FDRE \poData_reg[2] + (.C(CLK), + .CE(1'b1), + .D(D[2]), + .Q(vid_pData[2]), + .R(1'b0)); + FDRE \poData_reg[3] + (.C(CLK), + .CE(1'b1), + .D(D[3]), + .Q(vid_pData[3]), + .R(1'b0)); + FDRE \poData_reg[4] + (.C(CLK), + .CE(1'b1), + .D(D[4]), + .Q(vid_pData[4]), + .R(1'b0)); + FDRE \poData_reg[5] + (.C(CLK), + .CE(1'b1), + .D(D[5]), + .Q(vid_pData[5]), + .R(1'b0)); + FDRE \poData_reg[6] + (.C(CLK), + .CE(1'b1), + .D(D[6]), + .Q(vid_pData[6]), + .R(1'b0)); + FDRE \poData_reg[7] + (.C(CLK), + .CE(1'b1), + .D(D[7]), + .Q(vid_pData[7]), + .R(1'b0)); + FDRE \poData_reg[8] + (.C(CLK), + .CE(1'b1), + .D(D[8]), + .Q(vid_pData[8]), + .R(1'b0)); + FDRE \poData_reg[9] + (.C(CLK), + .CE(1'b1), + .D(D[9]), + .Q(vid_pData[9]), + .R(1'b0)); + FDRE poHSync_reg + (.C(CLK), + .CE(1'b1), + .D(pC0), + .Q(vid_pHSync), + .R(1'b0)); + FDRE poVDE_reg + (.C(CLK), + .CE(1'b1), + .D(pVde), + .Q(vid_pVDE), + .R(1'b0)); + FDRE poVSync_reg + (.C(CLK), + .CE(1'b1), + .D(pC1), + .Q(vid_pVSync), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "SyncAsync" *) +module Arty_Z7_20_dvi2rgb_0_0_SyncAsync + (out, + RefClk, + AS); + output [0:0]out; + input RefClk; + input [0:0]AS; + + wire [0:0]AS; + wire RefClk; + (* async_reg = "true" *) wire [1:0]oSyncStages; + + assign out[0] = oSyncStages[1]; + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDPE #( + .INIT(1'b1)) + \oSyncStages_reg[0] + (.C(RefClk), + .CE(1'b1), + .D(1'b0), + .PRE(AS), + .Q(oSyncStages[0])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDPE #( + .INIT(1'b1)) + \oSyncStages_reg[1] + (.C(RefClk), + .CE(1'b1), + .D(oSyncStages[0]), + .PRE(AS), + .Q(oSyncStages[1])); +endmodule + +(* ORIG_REF_NAME = "SyncAsync" *) +module Arty_Z7_20_dvi2rgb_0_0_SyncAsync_15 + (out, + RefClk, + AS, + D); + output [0:0]out; + input RefClk; + input [0:0]AS; + input [0:0]D; + + wire [0:0]AS; + wire [0:0]D; + wire RefClk; + (* async_reg = "true" *) wire [1:0]oSyncStages; + + assign out[0] = oSyncStages[1]; + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDPE #( + .INIT(1'b1)) + \oSyncStages_reg[0] + (.C(RefClk), + .CE(1'b1), + .D(D), + .PRE(AS), + .Q(oSyncStages[0])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDPE #( + .INIT(1'b1)) + \oSyncStages_reg[1] + (.C(RefClk), + .CE(1'b1), + .D(oSyncStages[0]), + .PRE(AS), + .Q(oSyncStages[1])); +endmodule + +(* ORIG_REF_NAME = "SyncAsync" *) +module Arty_Z7_20_dvi2rgb_0_0_SyncAsync_22 + (out, + RefClk, + AS, + D); + output [0:0]out; + input RefClk; + input [0:0]AS; + input [0:0]D; + + wire [0:0]AS; + wire [0:0]D; + wire RefClk; + (* async_reg = "true" *) wire [1:0]oSyncStages; + + assign out[0] = oSyncStages[1]; + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDPE #( + .INIT(1'b1)) + \oSyncStages_reg[0] + (.C(RefClk), + .CE(1'b1), + .D(D), + .PRE(AS), + .Q(oSyncStages[0])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDPE #( + .INIT(1'b1)) + \oSyncStages_reg[1] + (.C(RefClk), + .CE(1'b1), + .D(oSyncStages[0]), + .PRE(AS), + .Q(oSyncStages[1])); +endmodule + +(* ORIG_REF_NAME = "SyncAsync" *) +module Arty_Z7_20_dvi2rgb_0_0_SyncAsync_4 + (SS, + rDlyRst_reg, + E, + RST, + RefClk, + AS); + output [0:0]SS; + output rDlyRst_reg; + input [0:0]E; + input RST; + input RefClk; + input [0:0]AS; + + wire [0:0]AS; + wire [0:0]E; + wire RST; + wire RefClk; + (* async_reg = "true" *) wire [1:0]oSyncStages; + wire rDlyRst_reg; + + assign SS[0] = oSyncStages[1]; + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDPE #( + .INIT(1'b1)) + \oSyncStages_reg[0] + (.C(RefClk), + .CE(1'b1), + .D(1'b0), + .PRE(AS), + .Q(oSyncStages[0])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDPE #( + .INIT(1'b1)) + \oSyncStages_reg[1] + (.C(RefClk), + .CE(1'b1), + .D(oSyncStages[0]), + .PRE(AS), + .Q(oSyncStages[1])); + LUT3 #( + .INIT(8'hF8)) + rDlyRst_i_1 + (.I0(E), + .I1(RST), + .I2(oSyncStages[1]), + .O(rDlyRst_reg)); +endmodule + +(* ORIG_REF_NAME = "SyncAsync" *) +module Arty_Z7_20_dvi2rgb_0_0_SyncAsync_5 + (out, + PixelClk_int, + AS); + output [0:0]out; + input PixelClk_int; + input [0:0]AS; + + wire [0:0]AS; + wire PixelClk_int; + (* async_reg = "true" *) wire [1:0]oSyncStages; + + assign out[0] = oSyncStages[1]; + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDPE #( + .INIT(1'b1)) + \oSyncStages_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(1'b0), + .PRE(AS), + .Q(oSyncStages[0])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDPE #( + .INIT(1'b1)) + \oSyncStages_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .D(oSyncStages[0]), + .PRE(AS), + .Q(oSyncStages[1])); +endmodule + +(* ORIG_REF_NAME = "SyncAsync" *) +module Arty_Z7_20_dvi2rgb_0_0_SyncAsync_7 + (out, + SS, + \Filter.sIn_q_reg , + RefClk, + DDC_SCL_I); + output [0:0]out; + output [0:0]SS; + input \Filter.sIn_q_reg ; + input RefClk; + input DDC_SCL_I; + + wire DDC_SCL_I; + wire \Filter.sIn_q_reg ; + wire RefClk; + wire [0:0]SS; + (* async_reg = "true" *) wire [1:0]oSyncStages; + + assign out[0] = oSyncStages[1]; + LUT2 #( + .INIT(4'h6)) + \Filter.cntPeriods[3]_i_1__0 + (.I0(oSyncStages[1]), + .I1(\Filter.sIn_q_reg ), + .O(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b1)) + \oSyncStages_reg[0] + (.C(RefClk), + .CE(1'b1), + .D(DDC_SCL_I), + .Q(oSyncStages[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b1)) + \oSyncStages_reg[1] + (.C(RefClk), + .CE(1'b1), + .D(oSyncStages[0]), + .Q(oSyncStages[1]), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "SyncAsync" *) +module Arty_Z7_20_dvi2rgb_0_0_SyncAsync_8 + (out, + SS, + sIn_q, + RefClk, + DDC_SDA_I); + output [0:0]out; + output [0:0]SS; + input sIn_q; + input RefClk; + input DDC_SDA_I; + + wire DDC_SDA_I; + wire RefClk; + wire [0:0]SS; + (* async_reg = "true" *) wire [1:0]oSyncStages; + wire sIn_q; + + assign out[0] = oSyncStages[1]; + LUT2 #( + .INIT(4'h6)) + \Filter.cntPeriods[3]_i_1 + (.I0(oSyncStages[1]), + .I1(sIn_q), + .O(SS)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b1)) + \oSyncStages_reg[0] + (.C(RefClk), + .CE(1'b1), + .D(DDC_SDA_I), + .Q(oSyncStages[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b1)) + \oSyncStages_reg[1] + (.C(RefClk), + .CE(1'b1), + .D(oSyncStages[0]), + .Q(oSyncStages[1]), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "SyncAsync" *) +module Arty_Z7_20_dvi2rgb_0_0_SyncAsync_9 + (out, + RefClk, + \oSyncStages_reg[1]_0 , + D); + output [0:0]out; + input RefClk; + input [0:0]\oSyncStages_reg[1]_0 ; + input [0:0]D; + + wire [0:0]D; + wire RefClk; + (* async_reg = "true" *) wire [1:0]oSyncStages; + wire [0:0]\oSyncStages_reg[1]_0 ; + + assign out[0] = oSyncStages[1]; + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDPE #( + .INIT(1'b1)) + \oSyncStages_reg[0] + (.C(RefClk), + .CE(1'b1), + .D(D), + .PRE(\oSyncStages_reg[1]_0 ), + .Q(oSyncStages[0])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDPE #( + .INIT(1'b1)) + \oSyncStages_reg[1] + (.C(RefClk), + .CE(1'b1), + .D(oSyncStages[0]), + .PRE(\oSyncStages_reg[1]_0 ), + .Q(oSyncStages[1])); +endmodule + +(* ORIG_REF_NAME = "SyncAsync" *) +module Arty_Z7_20_dvi2rgb_0_0_SyncAsync__parameterized0 + (D, + rMMCM_LckdRisingFlag_reg, + rMMCM_LckdFallingFlag_reg, + Q, + RefClk, + \rMMCM_Reset_q_reg[0] ); + output [0:0]D; + output rMMCM_LckdRisingFlag_reg; + output rMMCM_LckdFallingFlag_reg; + input [0:0]Q; + input RefClk; + input [0:0]\rMMCM_Reset_q_reg[0] ; + + wire [0:0]Q; + wire RefClk; + (* async_reg = "true" *) wire [1:0]oSyncStages; + wire rMMCM_LckdFallingFlag_reg; + wire rMMCM_LckdRisingFlag_reg; + wire [0:0]\rMMCM_Reset_q_reg[0] ; + + assign D[0] = oSyncStages[1]; + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \oSyncStages_reg[0] + (.C(RefClk), + .CE(1'b1), + .D(\rMMCM_Reset_q_reg[0] ), + .Q(oSyncStages[0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \oSyncStages_reg[1] + (.C(RefClk), + .CE(1'b1), + .D(oSyncStages[0]), + .Q(oSyncStages[1]), + .R(1'b0)); + LUT2 #( + .INIT(4'h2)) + rMMCM_LckdFallingFlag_i_1 + (.I0(Q), + .I1(oSyncStages[1]), + .O(rMMCM_LckdFallingFlag_reg)); + LUT2 #( + .INIT(4'h2)) + rMMCM_LckdRisingFlag_i_1 + (.I0(oSyncStages[1]), + .I1(Q), + .O(rMMCM_LckdRisingFlag_reg)); +endmodule + +(* ORIG_REF_NAME = "SyncAsync" *) +module Arty_Z7_20_dvi2rgb_0_0_SyncAsync__parameterized1 + (out, + PixelClk_int, + \oSyncStages_reg[1]_0 , + D); + output [0:0]out; + input PixelClk_int; + input [0:0]\oSyncStages_reg[1]_0 ; + input [0:0]D; + + wire [0:0]D; + wire PixelClk_int; + (* async_reg = "true" *) wire [1:0]oSyncStages; + wire [0:0]\oSyncStages_reg[1]_0 ; + + assign out[0] = oSyncStages[1]; + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDCE #( + .INIT(1'b0)) + \oSyncStages_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .CLR(\oSyncStages_reg[1]_0 ), + .D(D), + .Q(oSyncStages[0])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDCE #( + .INIT(1'b0)) + \oSyncStages_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .CLR(\oSyncStages_reg[1]_0 ), + .D(oSyncStages[0]), + .Q(oSyncStages[1])); +endmodule + +(* ORIG_REF_NAME = "SyncAsync" *) +module Arty_Z7_20_dvi2rgb_0_0_SyncAsync__parameterized1_16 + (out, + PixelClk_int, + AS, + D); + output [0:0]out; + input PixelClk_int; + input [0:0]AS; + input [0:0]D; + + wire [0:0]AS; + wire [0:0]D; + wire PixelClk_int; + (* async_reg = "true" *) wire [1:0]oSyncStages; + + assign out[0] = oSyncStages[1]; + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDCE #( + .INIT(1'b0)) + \oSyncStages_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .CLR(AS), + .D(D), + .Q(oSyncStages[0])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDCE #( + .INIT(1'b0)) + \oSyncStages_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .CLR(AS), + .D(oSyncStages[0]), + .Q(oSyncStages[1])); +endmodule + +(* ORIG_REF_NAME = "SyncAsync" *) +module Arty_Z7_20_dvi2rgb_0_0_SyncAsync__parameterized1_23 + (out, + PixelClk_int, + AS, + D); + output [0:0]out; + input PixelClk_int; + input [0:0]AS; + input [0:0]D; + + wire [0:0]AS; + wire [0:0]D; + wire PixelClk_int; + (* async_reg = "true" *) wire [1:0]oSyncStages; + + assign out[0] = oSyncStages[1]; + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDCE #( + .INIT(1'b0)) + \oSyncStages_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .CLR(AS), + .D(D), + .Q(oSyncStages[0])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + FDCE #( + .INIT(1'b0)) + \oSyncStages_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .CLR(AS), + .D(oSyncStages[0]), + .Q(oSyncStages[1])); +endmodule + +(* ORIG_REF_NAME = "SyncBase" *) +module Arty_Z7_20_dvi2rgb_0_0_SyncBase + (out, + iIn_q_reg_0, + iIn_q_reg_1, + iIn_q_reg_2, + iIn_q_reg_3, + RefClk, + \oSyncStages_reg[1] , + rTimeoutCnt_reg, + PixelClk_int); + output [0:0]out; + output iIn_q_reg_0; + output iIn_q_reg_1; + output iIn_q_reg_2; + output iIn_q_reg_3; + input RefClk; + input [0:0]\oSyncStages_reg[1] ; + input [23:0]rTimeoutCnt_reg; + input PixelClk_int; + + wire PixelClk_int; + wire RefClk; + wire iIn_q; + wire iIn_q_reg_0; + wire iIn_q_reg_1; + wire iIn_q_reg_2; + wire iIn_q_reg_3; + wire [0:0]\oSyncStages_reg[1] ; + wire [0:0]out; + wire p_0_out; + wire [23:0]rTimeoutCnt_reg; + + Arty_Z7_20_dvi2rgb_0_0_SyncAsync__parameterized1 SyncAsyncx + (.D(iIn_q), + .PixelClk_int(PixelClk_int), + .\oSyncStages_reg[1]_0 (\oSyncStages_reg[1] ), + .out(out)); + LUT4 #( + .INIT(16'h4000)) + iIn_q_i_1__2 + (.I0(iIn_q_reg_0), + .I1(iIn_q_reg_1), + .I2(iIn_q_reg_2), + .I3(iIn_q_reg_3), + .O(p_0_out)); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFBF)) + iIn_q_i_2__2 + (.I0(rTimeoutCnt_reg[7]), + .I1(rTimeoutCnt_reg[20]), + .I2(rTimeoutCnt_reg[23]), + .I3(rTimeoutCnt_reg[13]), + .I4(rTimeoutCnt_reg[8]), + .I5(rTimeoutCnt_reg[11]), + .O(iIn_q_reg_0)); + LUT6 #( + .INIT(64'h0000000000000001)) + iIn_q_i_3__2 + (.I0(rTimeoutCnt_reg[22]), + .I1(rTimeoutCnt_reg[18]), + .I2(rTimeoutCnt_reg[21]), + .I3(rTimeoutCnt_reg[14]), + .I4(rTimeoutCnt_reg[16]), + .I5(rTimeoutCnt_reg[17]), + .O(iIn_q_reg_1)); + LUT6 #( + .INIT(64'h8000000000000000)) + iIn_q_i_4__2 + (.I0(rTimeoutCnt_reg[12]), + .I1(rTimeoutCnt_reg[15]), + .I2(rTimeoutCnt_reg[19]), + .I3(rTimeoutCnt_reg[10]), + .I4(rTimeoutCnt_reg[6]), + .I5(rTimeoutCnt_reg[9]), + .O(iIn_q_reg_2)); + LUT6 #( + .INIT(64'h8000000000000000)) + iIn_q_i_5__2 + (.I0(rTimeoutCnt_reg[3]), + .I1(rTimeoutCnt_reg[4]), + .I2(rTimeoutCnt_reg[5]), + .I3(rTimeoutCnt_reg[2]), + .I4(rTimeoutCnt_reg[0]), + .I5(rTimeoutCnt_reg[1]), + .O(iIn_q_reg_3)); + FDCE iIn_q_reg + (.C(RefClk), + .CE(1'b1), + .CLR(\oSyncStages_reg[1] ), + .D(p_0_out), + .Q(iIn_q)); +endmodule + +(* ORIG_REF_NAME = "SyncBase" *) +module Arty_Z7_20_dvi2rgb_0_0_SyncBase_13 + (out, + iIn_q_reg_0, + iIn_q_reg_1, + iIn_q_reg_2, + iIn_q_reg_3, + RefClk, + AS, + rTimeoutCnt_reg, + PixelClk_int); + output [0:0]out; + output iIn_q_reg_0; + output iIn_q_reg_1; + output iIn_q_reg_2; + output iIn_q_reg_3; + input RefClk; + input [0:0]AS; + input [23:0]rTimeoutCnt_reg; + input PixelClk_int; + + wire [0:0]AS; + wire PixelClk_int; + wire RefClk; + wire iIn_q_i_1__3_n_0; + wire iIn_q_reg_0; + wire iIn_q_reg_1; + wire iIn_q_reg_2; + wire iIn_q_reg_3; + wire iIn_q_reg_n_0; + wire [0:0]out; + wire [23:0]rTimeoutCnt_reg; + + Arty_Z7_20_dvi2rgb_0_0_SyncAsync__parameterized1_16 SyncAsyncx + (.AS(AS), + .D(iIn_q_reg_n_0), + .PixelClk_int(PixelClk_int), + .out(out)); + LUT4 #( + .INIT(16'h4000)) + iIn_q_i_1__3 + (.I0(iIn_q_reg_0), + .I1(iIn_q_reg_1), + .I2(iIn_q_reg_2), + .I3(iIn_q_reg_3), + .O(iIn_q_i_1__3_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFBF)) + iIn_q_i_2__3 + (.I0(rTimeoutCnt_reg[7]), + .I1(rTimeoutCnt_reg[20]), + .I2(rTimeoutCnt_reg[23]), + .I3(rTimeoutCnt_reg[13]), + .I4(rTimeoutCnt_reg[8]), + .I5(rTimeoutCnt_reg[11]), + .O(iIn_q_reg_0)); + LUT6 #( + .INIT(64'h0000000000000001)) + iIn_q_i_3__3 + (.I0(rTimeoutCnt_reg[22]), + .I1(rTimeoutCnt_reg[18]), + .I2(rTimeoutCnt_reg[21]), + .I3(rTimeoutCnt_reg[14]), + .I4(rTimeoutCnt_reg[16]), + .I5(rTimeoutCnt_reg[17]), + .O(iIn_q_reg_1)); + LUT6 #( + .INIT(64'h8000000000000000)) + iIn_q_i_4__3 + (.I0(rTimeoutCnt_reg[12]), + .I1(rTimeoutCnt_reg[15]), + .I2(rTimeoutCnt_reg[19]), + .I3(rTimeoutCnt_reg[10]), + .I4(rTimeoutCnt_reg[6]), + .I5(rTimeoutCnt_reg[9]), + .O(iIn_q_reg_2)); + LUT6 #( + .INIT(64'h8000000000000000)) + iIn_q_i_5__3 + (.I0(rTimeoutCnt_reg[3]), + .I1(rTimeoutCnt_reg[4]), + .I2(rTimeoutCnt_reg[5]), + .I3(rTimeoutCnt_reg[2]), + .I4(rTimeoutCnt_reg[0]), + .I5(rTimeoutCnt_reg[1]), + .O(iIn_q_reg_3)); + FDCE iIn_q_reg + (.C(RefClk), + .CE(1'b1), + .CLR(AS), + .D(iIn_q_i_1__3_n_0), + .Q(iIn_q_reg_n_0)); +endmodule + +(* ORIG_REF_NAME = "SyncBase" *) +module Arty_Z7_20_dvi2rgb_0_0_SyncBase_20 + (out, + iIn_q_reg_0, + iIn_q_reg_1, + iIn_q_reg_2, + iIn_q_reg_3, + RefClk, + AS, + rTimeoutCnt_reg, + PixelClk_int); + output [0:0]out; + output iIn_q_reg_0; + output iIn_q_reg_1; + output iIn_q_reg_2; + output iIn_q_reg_3; + input RefClk; + input [0:0]AS; + input [23:0]rTimeoutCnt_reg; + input PixelClk_int; + + wire [0:0]AS; + wire PixelClk_int; + wire RefClk; + wire iIn_q_i_1__4_n_0; + wire iIn_q_reg_0; + wire iIn_q_reg_1; + wire iIn_q_reg_2; + wire iIn_q_reg_3; + wire iIn_q_reg_n_0; + wire [0:0]out; + wire [23:0]rTimeoutCnt_reg; + + Arty_Z7_20_dvi2rgb_0_0_SyncAsync__parameterized1_23 SyncAsyncx + (.AS(AS), + .D(iIn_q_reg_n_0), + .PixelClk_int(PixelClk_int), + .out(out)); + LUT4 #( + .INIT(16'h4000)) + iIn_q_i_1__4 + (.I0(iIn_q_reg_0), + .I1(iIn_q_reg_1), + .I2(iIn_q_reg_2), + .I3(iIn_q_reg_3), + .O(iIn_q_i_1__4_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFBF)) + iIn_q_i_2__4 + (.I0(rTimeoutCnt_reg[7]), + .I1(rTimeoutCnt_reg[20]), + .I2(rTimeoutCnt_reg[23]), + .I3(rTimeoutCnt_reg[13]), + .I4(rTimeoutCnt_reg[8]), + .I5(rTimeoutCnt_reg[11]), + .O(iIn_q_reg_0)); + LUT6 #( + .INIT(64'h0000000000000001)) + iIn_q_i_3__4 + (.I0(rTimeoutCnt_reg[22]), + .I1(rTimeoutCnt_reg[18]), + .I2(rTimeoutCnt_reg[21]), + .I3(rTimeoutCnt_reg[14]), + .I4(rTimeoutCnt_reg[16]), + .I5(rTimeoutCnt_reg[17]), + .O(iIn_q_reg_1)); + LUT6 #( + .INIT(64'h8000000000000000)) + iIn_q_i_4__4 + (.I0(rTimeoutCnt_reg[12]), + .I1(rTimeoutCnt_reg[15]), + .I2(rTimeoutCnt_reg[19]), + .I3(rTimeoutCnt_reg[10]), + .I4(rTimeoutCnt_reg[6]), + .I5(rTimeoutCnt_reg[9]), + .O(iIn_q_reg_2)); + LUT6 #( + .INIT(64'h8000000000000000)) + iIn_q_i_5__4 + (.I0(rTimeoutCnt_reg[3]), + .I1(rTimeoutCnt_reg[4]), + .I2(rTimeoutCnt_reg[5]), + .I3(rTimeoutCnt_reg[2]), + .I4(rTimeoutCnt_reg[0]), + .I5(rTimeoutCnt_reg[1]), + .O(iIn_q_reg_3)); + FDCE iIn_q_reg + (.C(RefClk), + .CE(1'b1), + .CLR(AS), + .D(iIn_q_i_1__4_n_0), + .Q(iIn_q_reg_n_0)); +endmodule + +(* ORIG_REF_NAME = "SyncBase" *) +module Arty_Z7_20_dvi2rgb_0_0_SyncBase__parameterized0 + (out, + \pState_reg[1] , + PixelClk_int, + \oSyncStages_reg[1] , + RefClk); + output [0:0]out; + input \pState_reg[1] ; + input PixelClk_int; + input [0:0]\oSyncStages_reg[1] ; + input RefClk; + + wire PixelClk_int; + wire RefClk; + wire iIn_q_reg_n_0; + wire [0:0]\oSyncStages_reg[1] ; + wire [0:0]out; + wire \pState_reg[1] ; + + Arty_Z7_20_dvi2rgb_0_0_SyncAsync_9 SyncAsyncx + (.D(iIn_q_reg_n_0), + .RefClk(RefClk), + .\oSyncStages_reg[1]_0 (\oSyncStages_reg[1] ), + .out(out)); + FDPE iIn_q_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(\pState_reg[1] ), + .PRE(\oSyncStages_reg[1] ), + .Q(iIn_q_reg_n_0)); +endmodule + +(* ORIG_REF_NAME = "SyncBase" *) +module Arty_Z7_20_dvi2rgb_0_0_SyncBase__parameterized0_14 + (out, + \pState_reg[1] , + PixelClk_int, + AS, + RefClk); + output [0:0]out; + input \pState_reg[1] ; + input PixelClk_int; + input [0:0]AS; + input RefClk; + + wire [0:0]AS; + wire PixelClk_int; + wire RefClk; + wire iIn_q_reg_n_0; + wire [0:0]out; + wire \pState_reg[1] ; + + Arty_Z7_20_dvi2rgb_0_0_SyncAsync_15 SyncAsyncx + (.AS(AS), + .D(iIn_q_reg_n_0), + .RefClk(RefClk), + .out(out)); + FDPE iIn_q_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(\pState_reg[1] ), + .PRE(AS), + .Q(iIn_q_reg_n_0)); +endmodule + +(* ORIG_REF_NAME = "SyncBase" *) +module Arty_Z7_20_dvi2rgb_0_0_SyncBase__parameterized0_21 + (out, + \pState_reg[1] , + PixelClk_int, + AS, + RefClk); + output [0:0]out; + input \pState_reg[1] ; + input PixelClk_int; + input [0:0]AS; + input RefClk; + + wire [0:0]AS; + wire PixelClk_int; + wire RefClk; + wire iIn_q_reg_n_0; + wire [0:0]out; + wire \pState_reg[1] ; + + Arty_Z7_20_dvi2rgb_0_0_SyncAsync_22 SyncAsyncx + (.AS(AS), + .D(iIn_q_reg_n_0), + .RefClk(RefClk), + .out(out)); + FDPE iIn_q_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(\pState_reg[1] ), + .PRE(AS), + .Q(iIn_q_reg_n_0)); +endmodule + +(* ORIG_REF_NAME = "TMDS_Clocking" *) +module Arty_Z7_20_dvi2rgb_0_0_TMDS_Clocking + (\pDataQ_reg[8] , + PixelClk_int, + aPixelClkLckd, + in0, + RefClk, + TMDS_Clk_p, + TMDS_Clk_n, + aRst_n); + output \pDataQ_reg[8] ; + output PixelClk_int; + output aPixelClkLckd; + output in0; + input RefClk; + input TMDS_Clk_p; + input TMDS_Clk_n; + input aRst_n; + + wire CLKFBIN; + wire CLK_IN_hdmi_clk; + wire CLK_OUT_5x_hdmi_clk; + wire CLR; + wire LockLostReset_n_1; + wire MMCM_LockSync_n_1; + wire MMCM_LockSync_n_2; + wire PixelClk_int; + wire RST; + wire RefClk; + wire TMDS_Clk_n; + wire TMDS_Clk_p; + wire aDlyLckd; + wire aMMCM_Locked; + wire aPixelClkLckd; + wire aRst_n; + wire in0; + wire \pDataQ_reg[8] ; + wire p_0_in; + wire [0:0]rDlyRstCnt0; + wire \rDlyRstCnt[1]_i_1_n_0 ; + wire \rDlyRstCnt[2]_i_1_n_0 ; + wire \rDlyRstCnt[3]_i_1_n_0 ; + wire \rDlyRstCnt[4]_i_1_n_0 ; + wire \rDlyRstCnt[4]_i_2_n_0 ; + wire [4:0]rDlyRstCnt_reg__0; + wire rLockLostRst; + wire rMMCM_LckdFallingFlag; + wire rMMCM_Locked; + wire \rMMCM_Locked_q_reg_n_0_[0] ; + wire [1:0]rMMCM_Reset_q; + wire \rMMCM_Reset_q[0]_i_1_n_0 ; + wire rRdyRst; + wire NLW_DVI_ClkGenerator_CLKFBOUTB_UNCONNECTED; + wire NLW_DVI_ClkGenerator_CLKFBSTOPPED_UNCONNECTED; + wire NLW_DVI_ClkGenerator_CLKINSTOPPED_UNCONNECTED; + wire NLW_DVI_ClkGenerator_CLKOUT0B_UNCONNECTED; + wire NLW_DVI_ClkGenerator_CLKOUT1_UNCONNECTED; + wire NLW_DVI_ClkGenerator_CLKOUT1B_UNCONNECTED; + wire NLW_DVI_ClkGenerator_CLKOUT2_UNCONNECTED; + wire NLW_DVI_ClkGenerator_CLKOUT2B_UNCONNECTED; + wire NLW_DVI_ClkGenerator_CLKOUT3_UNCONNECTED; + wire NLW_DVI_ClkGenerator_CLKOUT3B_UNCONNECTED; + wire NLW_DVI_ClkGenerator_CLKOUT4_UNCONNECTED; + wire NLW_DVI_ClkGenerator_CLKOUT5_UNCONNECTED; + wire NLW_DVI_ClkGenerator_CLKOUT6_UNCONNECTED; + wire NLW_DVI_ClkGenerator_DRDY_UNCONNECTED; + wire NLW_DVI_ClkGenerator_PSDONE_UNCONNECTED; + wire [15:0]NLW_DVI_ClkGenerator_DO_UNCONNECTED; + + (* box_type = "PRIMITIVE" *) + MMCME2_ADV #( + .BANDWIDTH("OPTIMIZED"), + .CLKFBOUT_MULT_F(10.000000), + .CLKFBOUT_PHASE(0.000000), + .CLKFBOUT_USE_FINE_PS("FALSE"), + .CLKIN1_PERIOD(12.000000), + .CLKIN2_PERIOD(0.000000), + .CLKOUT0_DIVIDE_F(2.000000), + .CLKOUT0_DUTY_CYCLE(0.500000), + .CLKOUT0_PHASE(0.000000), + .CLKOUT0_USE_FINE_PS("FALSE"), + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.500000), + .CLKOUT1_PHASE(0.000000), + .CLKOUT1_USE_FINE_PS("FALSE"), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.500000), + .CLKOUT2_PHASE(0.000000), + .CLKOUT2_USE_FINE_PS("FALSE"), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.500000), + .CLKOUT3_PHASE(0.000000), + .CLKOUT3_USE_FINE_PS("FALSE"), + .CLKOUT4_CASCADE("FALSE"), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.500000), + .CLKOUT4_PHASE(0.000000), + .CLKOUT4_USE_FINE_PS("FALSE"), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.500000), + .CLKOUT5_PHASE(0.000000), + .CLKOUT5_USE_FINE_PS("FALSE"), + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.500000), + .CLKOUT6_PHASE(0.000000), + .CLKOUT6_USE_FINE_PS("FALSE"), + .COMPENSATION("INTERNAL"), + .DIVCLK_DIVIDE(1), + .IS_CLKINSEL_INVERTED(1'b0), + .IS_PSEN_INVERTED(1'b0), + .IS_PSINCDEC_INVERTED(1'b0), + .IS_PWRDWN_INVERTED(1'b0), + .IS_RST_INVERTED(1'b0), + .REF_JITTER1(0.010000), + .REF_JITTER2(0.000000), + .SS_EN("FALSE"), + .SS_MODE("CENTER_HIGH"), + .SS_MOD_PERIOD(10000), + .STARTUP_WAIT("FALSE")) + DVI_ClkGenerator + (.CLKFBIN(CLKFBIN), + .CLKFBOUT(CLKFBIN), + .CLKFBOUTB(NLW_DVI_ClkGenerator_CLKFBOUTB_UNCONNECTED), + .CLKFBSTOPPED(NLW_DVI_ClkGenerator_CLKFBSTOPPED_UNCONNECTED), + .CLKIN1(CLK_IN_hdmi_clk), + .CLKIN2(1'b0), + .CLKINSEL(1'b1), + .CLKINSTOPPED(NLW_DVI_ClkGenerator_CLKINSTOPPED_UNCONNECTED), + .CLKOUT0(CLK_OUT_5x_hdmi_clk), + .CLKOUT0B(NLW_DVI_ClkGenerator_CLKOUT0B_UNCONNECTED), + .CLKOUT1(NLW_DVI_ClkGenerator_CLKOUT1_UNCONNECTED), + .CLKOUT1B(NLW_DVI_ClkGenerator_CLKOUT1B_UNCONNECTED), + .CLKOUT2(NLW_DVI_ClkGenerator_CLKOUT2_UNCONNECTED), + .CLKOUT2B(NLW_DVI_ClkGenerator_CLKOUT2B_UNCONNECTED), + .CLKOUT3(NLW_DVI_ClkGenerator_CLKOUT3_UNCONNECTED), + .CLKOUT3B(NLW_DVI_ClkGenerator_CLKOUT3B_UNCONNECTED), + .CLKOUT4(NLW_DVI_ClkGenerator_CLKOUT4_UNCONNECTED), + .CLKOUT5(NLW_DVI_ClkGenerator_CLKOUT5_UNCONNECTED), + .CLKOUT6(NLW_DVI_ClkGenerator_CLKOUT6_UNCONNECTED), + .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DCLK(1'b0), + .DEN(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DO(NLW_DVI_ClkGenerator_DO_UNCONNECTED[15:0]), + .DRDY(NLW_DVI_ClkGenerator_DRDY_UNCONNECTED), + .DWE(1'b0), + .LOCKED(aMMCM_Locked), + .PSCLK(1'b0), + .PSDONE(NLW_DVI_ClkGenerator_PSDONE_UNCONNECTED), + .PSEN(1'b0), + .PSINCDEC(1'b0), + .PWRDWN(1'b0), + .RST(rMMCM_Reset_q[0])); + (* box_type = "PRIMITIVE" *) + IDELAYCTRL #( + .SIM_DEVICE("7SERIES")) + IDelayCtrlX + (.RDY(aDlyLckd), + .REFCLK(RefClk), + .RST(RST)); + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + (* box_type = "PRIMITIVE" *) + IBUFDS #( + .DQS_BIAS("FALSE")) + InputBuffer + (.I(TMDS_Clk_p), + .IB(TMDS_Clk_n), + .O(CLK_IN_hdmi_clk)); + Arty_Z7_20_dvi2rgb_0_0_ResetBridge_2 LockLostReset + (.E(\rDlyRstCnt[4]_i_1_n_0 ), + .RST(RST), + .RefClk(RefClk), + .SS(rLockLostRst), + .aRst_n(aRst_n), + .rDlyRst_reg(LockLostReset_n_1)); + Arty_Z7_20_dvi2rgb_0_0_SyncAsync__parameterized0 MMCM_LockSync + (.D(rMMCM_Locked), + .Q(p_0_in), + .RefClk(RefClk), + .rMMCM_LckdFallingFlag_reg(MMCM_LockSync_n_2), + .rMMCM_LckdRisingFlag_reg(MMCM_LockSync_n_1), + .\rMMCM_Reset_q_reg[0] (aMMCM_Locked)); + (* box_type = "PRIMITIVE" *) + BUFR #( + .BUFR_DIVIDE("5"), + .SIM_DEVICE("7SERIES")) + PixelClkBuffer + (.CE(1'b1), + .CLR(CLR), + .I(CLK_OUT_5x_hdmi_clk), + .O(PixelClk_int)); + Arty_Z7_20_dvi2rgb_0_0_ResetBridge_3 RdyLostReset + (.RefClk(RefClk), + .aDlyLckd(aDlyLckd), + .out(rRdyRst)); + (* box_type = "PRIMITIVE" *) + BUFIO SerialClkBuffer + (.I(CLK_OUT_5x_hdmi_clk), + .O(\pDataQ_reg[8] )); + FDCE aLocked_reg + (.C(RefClk), + .CE(1'b1), + .CLR(rRdyRst), + .D(\rMMCM_Locked_q_reg_n_0_[0] ), + .Q(aPixelClkLckd)); + LUT1 #( + .INIT(2'h1)) + aRst_int_inferred_i_1__1 + (.I0(aPixelClkLckd), + .O(in0)); + LUT1 #( + .INIT(2'h1)) + \rDlyRstCnt[0]_i_1 + (.I0(rDlyRstCnt_reg__0[0]), + .O(rDlyRstCnt0)); + (* SOFT_HLUTNM = "soft_lutpair95" *) + LUT2 #( + .INIT(4'h9)) + \rDlyRstCnt[1]_i_1 + (.I0(rDlyRstCnt_reg__0[0]), + .I1(rDlyRstCnt_reg__0[1]), + .O(\rDlyRstCnt[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair95" *) + LUT3 #( + .INIT(8'hE1)) + \rDlyRstCnt[2]_i_1 + (.I0(rDlyRstCnt_reg__0[1]), + .I1(rDlyRstCnt_reg__0[0]), + .I2(rDlyRstCnt_reg__0[2]), + .O(\rDlyRstCnt[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair94" *) + LUT4 #( + .INIT(16'hFE01)) + \rDlyRstCnt[3]_i_1 + (.I0(rDlyRstCnt_reg__0[1]), + .I1(rDlyRstCnt_reg__0[0]), + .I2(rDlyRstCnt_reg__0[2]), + .I3(rDlyRstCnt_reg__0[3]), + .O(\rDlyRstCnt[3]_i_1_n_0 )); + LUT5 #( + .INIT(32'hFFFFFFFE)) + \rDlyRstCnt[4]_i_1 + (.I0(rDlyRstCnt_reg__0[2]), + .I1(rDlyRstCnt_reg__0[0]), + .I2(rDlyRstCnt_reg__0[1]), + .I3(rDlyRstCnt_reg__0[3]), + .I4(rDlyRstCnt_reg__0[4]), + .O(\rDlyRstCnt[4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair94" *) + LUT5 #( + .INIT(32'hFFFE0001)) + \rDlyRstCnt[4]_i_2 + (.I0(rDlyRstCnt_reg__0[3]), + .I1(rDlyRstCnt_reg__0[2]), + .I2(rDlyRstCnt_reg__0[0]), + .I3(rDlyRstCnt_reg__0[1]), + .I4(rDlyRstCnt_reg__0[4]), + .O(\rDlyRstCnt[4]_i_2_n_0 )); + FDSE #( + .INIT(1'b1)) + \rDlyRstCnt_reg[0] + (.C(RefClk), + .CE(\rDlyRstCnt[4]_i_1_n_0 ), + .D(rDlyRstCnt0), + .Q(rDlyRstCnt_reg__0[0]), + .S(rLockLostRst)); + FDSE #( + .INIT(1'b1)) + \rDlyRstCnt_reg[1] + (.C(RefClk), + .CE(\rDlyRstCnt[4]_i_1_n_0 ), + .D(\rDlyRstCnt[1]_i_1_n_0 ), + .Q(rDlyRstCnt_reg__0[1]), + .S(rLockLostRst)); + FDSE #( + .INIT(1'b1)) + \rDlyRstCnt_reg[2] + (.C(RefClk), + .CE(\rDlyRstCnt[4]_i_1_n_0 ), + .D(\rDlyRstCnt[2]_i_1_n_0 ), + .Q(rDlyRstCnt_reg__0[2]), + .S(rLockLostRst)); + FDSE #( + .INIT(1'b1)) + \rDlyRstCnt_reg[3] + (.C(RefClk), + .CE(\rDlyRstCnt[4]_i_1_n_0 ), + .D(\rDlyRstCnt[3]_i_1_n_0 ), + .Q(rDlyRstCnt_reg__0[3]), + .S(rLockLostRst)); + FDSE #( + .INIT(1'b1)) + \rDlyRstCnt_reg[4] + (.C(RefClk), + .CE(\rDlyRstCnt[4]_i_1_n_0 ), + .D(\rDlyRstCnt[4]_i_2_n_0 ), + .Q(rDlyRstCnt_reg__0[4]), + .S(rLockLostRst)); + FDRE rDlyRst_reg + (.C(RefClk), + .CE(1'b1), + .D(LockLostReset_n_1), + .Q(RST), + .R(1'b0)); + FDRE rMMCM_LckdFallingFlag_reg + (.C(RefClk), + .CE(1'b1), + .D(MMCM_LockSync_n_2), + .Q(rMMCM_LckdFallingFlag), + .R(1'b0)); + FDRE rMMCM_LckdRisingFlag_reg + (.C(RefClk), + .CE(1'b1), + .D(MMCM_LockSync_n_1), + .Q(CLR), + .R(1'b0)); + FDRE \rMMCM_Locked_q_reg[0] + (.C(RefClk), + .CE(1'b1), + .D(p_0_in), + .Q(\rMMCM_Locked_q_reg_n_0_[0] ), + .R(1'b0)); + FDRE \rMMCM_Locked_q_reg[1] + (.C(RefClk), + .CE(1'b1), + .D(rMMCM_Locked), + .Q(p_0_in), + .R(1'b0)); + LUT2 #( + .INIT(4'hE)) + \rMMCM_Reset_q[0]_i_1 + (.I0(rMMCM_LckdFallingFlag), + .I1(rMMCM_Reset_q[1]), + .O(\rMMCM_Reset_q[0]_i_1_n_0 )); + FDPE \rMMCM_Reset_q_reg[0] + (.C(RefClk), + .CE(1'b1), + .D(\rMMCM_Reset_q[0]_i_1_n_0 ), + .PRE(rLockLostRst), + .Q(rMMCM_Reset_q[0])); + FDPE \rMMCM_Reset_q_reg[1] + (.C(RefClk), + .CE(1'b1), + .D(rMMCM_LckdFallingFlag), + .PRE(rLockLostRst), + .Q(rMMCM_Reset_q[1])); +endmodule + +(* ORIG_REF_NAME = "TMDS_Decoder" *) +module Arty_Z7_20_dvi2rgb_0_0_TMDS_Decoder + (pVde, + pVld_0, + pRdy_0, + pC0, + pC1, + pAllVld, + \pDataIn_reg[7]_0 , + Q, + TMDS_Data_p, + TMDS_Data_n, + PixelClk_int, + \rMMCM_Reset_q_reg[0] , + CLKB, + AS, + RefClk, + SR, + pAligned_reg, + pVld_2, + pVld_1, + pRdy_1, + pRdy_2, + pRst_n, + pAllVldBgnFlag); + output pVde; + output pVld_0; + output pRdy_0; + output pC0; + output pC1; + output pAllVld; + output [0:0]\pDataIn_reg[7]_0 ; + output [7:0]Q; + input [0:0]TMDS_Data_p; + input [0:0]TMDS_Data_n; + input PixelClk_int; + input \rMMCM_Reset_q_reg[0] ; + input CLKB; + input [0:0]AS; + input RefClk; + input [0:0]SR; + input pAligned_reg; + input pVld_2; + input pVld_1; + input pRdy_1; + input pRdy_2; + input pRst_n; + input pAllVldBgnFlag; + + wire [0:0]AS; + wire CLKB; + wire ChannelBondX_n_3; + wire ChannelBondX_n_4; + wire PhaseAlignX_n_4; + wire PhaseAlignX_n_5; + wire PhaseAlignX_n_7; + wire PixelClk_int; + wire [7:0]Q; + wire RefClk; + wire [0:0]SR; + wire SyncBaseOvf_n_1; + wire SyncBaseOvf_n_2; + wire SyncBaseOvf_n_3; + wire SyncBaseOvf_n_4; + wire [0:0]TMDS_Data_n; + wire [0:0]TMDS_Data_p; + wire pAlignErr_q; + wire pAlignRst_i_1__1_n_0; + wire pAlignRst_reg_n_0; + wire pAligned_reg; + wire pAllVld; + wire pAllVldBgnFlag; + wire pBitslip; + wire [1:0]pBitslipCnt; + wire \pBitslipCnt[0]_i_1_n_0 ; + wire \pBitslipCnt[1]_i_1_n_0 ; + wire pC0; + wire pC1; + wire [7:0]pDataIn; + wire [9:0]pDataInRaw; + wire [0:0]\pDataIn_reg[7]_0 ; + wire pIDLY_CE; + wire [4:0]pIDLY_CNT; + wire pIDLY_INC; + wire pIDLY_LD; + wire pRdy_0; + wire pRdy_1; + wire pRdy_2; + wire pRst_n; + wire pTimeoutOvf; + wire pVde; + wire pVde_0; + wire pVld_0; + wire pVld_1; + wire pVld_2; + wire \rMMCM_Reset_q_reg[0] ; + wire \rTimeoutCnt[0]_i_1__1_n_0 ; + wire \rTimeoutCnt[0]_i_3__1_n_0 ; + wire \rTimeoutCnt[0]_i_4__1_n_0 ; + wire \rTimeoutCnt[0]_i_5__1_n_0 ; + wire \rTimeoutCnt[0]_i_6__1_n_0 ; + wire \rTimeoutCnt[12]_i_2__1_n_0 ; + wire \rTimeoutCnt[12]_i_3__1_n_0 ; + wire \rTimeoutCnt[12]_i_4__1_n_0 ; + wire \rTimeoutCnt[12]_i_5__1_n_0 ; + wire \rTimeoutCnt[16]_i_2__1_n_0 ; + wire \rTimeoutCnt[16]_i_3__1_n_0 ; + wire \rTimeoutCnt[16]_i_4__1_n_0 ; + wire \rTimeoutCnt[16]_i_5__1_n_0 ; + wire \rTimeoutCnt[20]_i_2__1_n_0 ; + wire \rTimeoutCnt[20]_i_3__1_n_0 ; + wire \rTimeoutCnt[20]_i_4__1_n_0 ; + wire \rTimeoutCnt[20]_i_5__1_n_0 ; + wire \rTimeoutCnt[4]_i_2__1_n_0 ; + wire \rTimeoutCnt[4]_i_3__1_n_0 ; + wire \rTimeoutCnt[4]_i_4__1_n_0 ; + wire \rTimeoutCnt[4]_i_5__1_n_0 ; + wire \rTimeoutCnt[8]_i_2__1_n_0 ; + wire \rTimeoutCnt[8]_i_3__1_n_0 ; + wire \rTimeoutCnt[8]_i_4__1_n_0 ; + wire \rTimeoutCnt[8]_i_5__1_n_0 ; + wire [23:0]rTimeoutCnt_reg; + wire \rTimeoutCnt_reg[0]_i_2__1_n_0 ; + wire \rTimeoutCnt_reg[0]_i_2__1_n_1 ; + wire \rTimeoutCnt_reg[0]_i_2__1_n_2 ; + wire \rTimeoutCnt_reg[0]_i_2__1_n_3 ; + wire \rTimeoutCnt_reg[0]_i_2__1_n_4 ; + wire \rTimeoutCnt_reg[0]_i_2__1_n_5 ; + wire \rTimeoutCnt_reg[0]_i_2__1_n_6 ; + wire \rTimeoutCnt_reg[0]_i_2__1_n_7 ; + wire \rTimeoutCnt_reg[12]_i_1__1_n_0 ; + wire \rTimeoutCnt_reg[12]_i_1__1_n_1 ; + wire \rTimeoutCnt_reg[12]_i_1__1_n_2 ; + wire \rTimeoutCnt_reg[12]_i_1__1_n_3 ; + wire \rTimeoutCnt_reg[12]_i_1__1_n_4 ; + wire \rTimeoutCnt_reg[12]_i_1__1_n_5 ; + wire \rTimeoutCnt_reg[12]_i_1__1_n_6 ; + wire \rTimeoutCnt_reg[12]_i_1__1_n_7 ; + wire \rTimeoutCnt_reg[16]_i_1__1_n_0 ; + wire \rTimeoutCnt_reg[16]_i_1__1_n_1 ; + wire \rTimeoutCnt_reg[16]_i_1__1_n_2 ; + wire \rTimeoutCnt_reg[16]_i_1__1_n_3 ; + wire \rTimeoutCnt_reg[16]_i_1__1_n_4 ; + wire \rTimeoutCnt_reg[16]_i_1__1_n_5 ; + wire \rTimeoutCnt_reg[16]_i_1__1_n_6 ; + wire \rTimeoutCnt_reg[16]_i_1__1_n_7 ; + wire \rTimeoutCnt_reg[20]_i_1__1_n_1 ; + wire \rTimeoutCnt_reg[20]_i_1__1_n_2 ; + wire \rTimeoutCnt_reg[20]_i_1__1_n_3 ; + wire \rTimeoutCnt_reg[20]_i_1__1_n_4 ; + wire \rTimeoutCnt_reg[20]_i_1__1_n_5 ; + wire \rTimeoutCnt_reg[20]_i_1__1_n_6 ; + wire \rTimeoutCnt_reg[20]_i_1__1_n_7 ; + wire \rTimeoutCnt_reg[4]_i_1__1_n_0 ; + wire \rTimeoutCnt_reg[4]_i_1__1_n_1 ; + wire \rTimeoutCnt_reg[4]_i_1__1_n_2 ; + wire \rTimeoutCnt_reg[4]_i_1__1_n_3 ; + wire \rTimeoutCnt_reg[4]_i_1__1_n_4 ; + wire \rTimeoutCnt_reg[4]_i_1__1_n_5 ; + wire \rTimeoutCnt_reg[4]_i_1__1_n_6 ; + wire \rTimeoutCnt_reg[4]_i_1__1_n_7 ; + wire \rTimeoutCnt_reg[8]_i_1__1_n_0 ; + wire \rTimeoutCnt_reg[8]_i_1__1_n_1 ; + wire \rTimeoutCnt_reg[8]_i_1__1_n_2 ; + wire \rTimeoutCnt_reg[8]_i_1__1_n_3 ; + wire \rTimeoutCnt_reg[8]_i_1__1_n_4 ; + wire \rTimeoutCnt_reg[8]_i_1__1_n_5 ; + wire \rTimeoutCnt_reg[8]_i_1__1_n_6 ; + wire \rTimeoutCnt_reg[8]_i_1__1_n_7 ; + wire rTimeoutRst; + wire [3:3]\NLW_rTimeoutCnt_reg[20]_i_1__1_CO_UNCONNECTED ; + + Arty_Z7_20_dvi2rgb_0_0_ChannelBond_17 ChannelBondX + (.D(pDataIn), + .PixelClk_int(PixelClk_int), + .pAligned_reg(pAligned_reg), + .pAllVld(pAllVld), + .pAllVldBgnFlag(pAllVldBgnFlag), + .pC0(pC0), + .pC0_reg(ChannelBondX_n_4), + .pC1(pC1), + .pC1_reg(ChannelBondX_n_3), + .pDataInRaw(pDataInRaw), + .\pDataIn_reg[7] (\pDataIn_reg[7]_0 ), + .pMeRdy_int_reg_0(pRdy_0), + .pRdy_1(pRdy_1), + .pRdy_2(pRdy_2), + .pVde_0(pVde_0)); + Arty_Z7_20_dvi2rgb_0_0_InputSERDES_18 InputSERDES_X + (.AS(AS), + .CLKB(CLKB), + .D(pIDLY_CNT), + .PixelClk_int(PixelClk_int), + .TMDS_Data_n(TMDS_Data_n), + .TMDS_Data_p(TMDS_Data_p), + .pBitslip(pBitslip), + .pDataInRaw(pDataInRaw), + .pIDLY_CE(pIDLY_CE), + .pIDLY_INC(pIDLY_INC), + .pIDLY_LD(pIDLY_LD), + .\rMMCM_Reset_q_reg[0] (\rMMCM_Reset_q_reg[0] )); + Arty_Z7_20_dvi2rgb_0_0_PhaseAlign_19 PhaseAlignX + (.D(pDataInRaw[8:0]), + .PixelClk_int(PixelClk_int), + .SS(pAlignRst_reg_n_0), + .iIn_q_reg(PhaseAlignX_n_5), + .out(pTimeoutOvf), + .pAlignErr_q(pAlignErr_q), + .pAlignErr_q_reg(PhaseAlignX_n_4), + .pAllVld(pAllVld), + .pBitslip_reg(PhaseAlignX_n_7), + .pIDLY_CE(pIDLY_CE), + .pIDLY_CE_reg_0(pIDLY_CNT), + .pIDLY_INC(pIDLY_INC), + .pIDLY_LD(pIDLY_LD), + .pVld_0(pVld_0), + .pVld_1(pVld_1), + .pVld_2(pVld_2)); + Arty_Z7_20_dvi2rgb_0_0_SyncBase_20 SyncBaseOvf + (.AS(AS), + .PixelClk_int(PixelClk_int), + .RefClk(RefClk), + .iIn_q_reg_0(SyncBaseOvf_n_1), + .iIn_q_reg_1(SyncBaseOvf_n_2), + .iIn_q_reg_2(SyncBaseOvf_n_3), + .iIn_q_reg_3(SyncBaseOvf_n_4), + .out(pTimeoutOvf), + .rTimeoutCnt_reg(rTimeoutCnt_reg)); + Arty_Z7_20_dvi2rgb_0_0_SyncBase__parameterized0_21 SyncBaseRst + (.AS(AS), + .PixelClk_int(PixelClk_int), + .RefClk(RefClk), + .out(rTimeoutRst), + .\pState_reg[1] (PhaseAlignX_n_5)); + FDRE pAlignErr_q_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(PhaseAlignX_n_4), + .Q(pAlignErr_q), + .R(1'b0)); + LUT5 #( + .INIT(32'hFFFDDDDD)) + pAlignRst_i_1__1 + (.I0(pRst_n), + .I1(pBitslip), + .I2(pBitslipCnt[1]), + .I3(pBitslipCnt[0]), + .I4(pAlignRst_reg_n_0), + .O(pAlignRst_i_1__1_n_0)); + FDPE pAlignRst_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pAlignRst_i_1__1_n_0), + .PRE(AS), + .Q(pAlignRst_reg_n_0)); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT3 #( + .INIT(8'h04)) + \pBitslipCnt[0]_i_1 + (.I0(pBitslipCnt[0]), + .I1(pBitslipCnt[1]), + .I2(pBitslip), + .O(\pBitslipCnt[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT3 #( + .INIT(8'hF8)) + \pBitslipCnt[1]_i_1 + (.I0(pBitslipCnt[0]), + .I1(pBitslipCnt[1]), + .I2(pBitslip), + .O(\pBitslipCnt[1]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \pBitslipCnt_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(\pBitslipCnt[0]_i_1_n_0 ), + .Q(pBitslipCnt[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + \pBitslipCnt_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .D(\pBitslipCnt[1]_i_1_n_0 ), + .Q(pBitslipCnt[1]), + .R(1'b0)); + FDRE pBitslip_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(PhaseAlignX_n_7), + .Q(pBitslip), + .R(1'b0)); + FDRE pC0_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(ChannelBondX_n_4), + .Q(pC0), + .R(SR)); + FDRE pC1_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(ChannelBondX_n_3), + .Q(pC1), + .R(SR)); + FDRE \pDataIn_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(pDataIn[0]), + .Q(Q[0]), + .R(SR)); + FDRE \pDataIn_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .D(pDataIn[1]), + .Q(Q[1]), + .R(SR)); + FDRE \pDataIn_reg[2] + (.C(PixelClk_int), + .CE(1'b1), + .D(pDataIn[2]), + .Q(Q[2]), + .R(SR)); + FDRE \pDataIn_reg[3] + (.C(PixelClk_int), + .CE(1'b1), + .D(pDataIn[3]), + .Q(Q[3]), + .R(SR)); + FDRE \pDataIn_reg[4] + (.C(PixelClk_int), + .CE(1'b1), + .D(pDataIn[4]), + .Q(Q[4]), + .R(SR)); + FDRE \pDataIn_reg[5] + (.C(PixelClk_int), + .CE(1'b1), + .D(pDataIn[5]), + .Q(Q[5]), + .R(SR)); + FDRE \pDataIn_reg[6] + (.C(PixelClk_int), + .CE(1'b1), + .D(pDataIn[6]), + .Q(Q[6]), + .R(SR)); + FDRE \pDataIn_reg[7] + (.C(PixelClk_int), + .CE(1'b1), + .D(pDataIn[7]), + .Q(Q[7]), + .R(SR)); + FDRE pVde_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pVde_0), + .Q(pVde), + .R(SR)); + LUT4 #( + .INIT(16'hBFFF)) + \rTimeoutCnt[0]_i_1__1 + (.I0(SyncBaseOvf_n_1), + .I1(SyncBaseOvf_n_2), + .I2(SyncBaseOvf_n_3), + .I3(SyncBaseOvf_n_4), + .O(\rTimeoutCnt[0]_i_1__1_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[0]_i_3__1 + (.I0(rTimeoutCnt_reg[3]), + .O(\rTimeoutCnt[0]_i_3__1_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[0]_i_4__1 + (.I0(rTimeoutCnt_reg[2]), + .O(\rTimeoutCnt[0]_i_4__1_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[0]_i_5__1 + (.I0(rTimeoutCnt_reg[1]), + .O(\rTimeoutCnt[0]_i_5__1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \rTimeoutCnt[0]_i_6__1 + (.I0(rTimeoutCnt_reg[0]), + .O(\rTimeoutCnt[0]_i_6__1_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[12]_i_2__1 + (.I0(rTimeoutCnt_reg[15]), + .O(\rTimeoutCnt[12]_i_2__1_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[12]_i_3__1 + (.I0(rTimeoutCnt_reg[14]), + .O(\rTimeoutCnt[12]_i_3__1_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[12]_i_4__1 + (.I0(rTimeoutCnt_reg[13]), + .O(\rTimeoutCnt[12]_i_4__1_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[12]_i_5__1 + (.I0(rTimeoutCnt_reg[12]), + .O(\rTimeoutCnt[12]_i_5__1_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[16]_i_2__1 + (.I0(rTimeoutCnt_reg[19]), + .O(\rTimeoutCnt[16]_i_2__1_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[16]_i_3__1 + (.I0(rTimeoutCnt_reg[18]), + .O(\rTimeoutCnt[16]_i_3__1_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[16]_i_4__1 + (.I0(rTimeoutCnt_reg[17]), + .O(\rTimeoutCnt[16]_i_4__1_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[16]_i_5__1 + (.I0(rTimeoutCnt_reg[16]), + .O(\rTimeoutCnt[16]_i_5__1_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[20]_i_2__1 + (.I0(rTimeoutCnt_reg[23]), + .O(\rTimeoutCnt[20]_i_2__1_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[20]_i_3__1 + (.I0(rTimeoutCnt_reg[22]), + .O(\rTimeoutCnt[20]_i_3__1_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[20]_i_4__1 + (.I0(rTimeoutCnt_reg[21]), + .O(\rTimeoutCnt[20]_i_4__1_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[20]_i_5__1 + (.I0(rTimeoutCnt_reg[20]), + .O(\rTimeoutCnt[20]_i_5__1_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[4]_i_2__1 + (.I0(rTimeoutCnt_reg[7]), + .O(\rTimeoutCnt[4]_i_2__1_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[4]_i_3__1 + (.I0(rTimeoutCnt_reg[6]), + .O(\rTimeoutCnt[4]_i_3__1_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[4]_i_4__1 + (.I0(rTimeoutCnt_reg[5]), + .O(\rTimeoutCnt[4]_i_4__1_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[4]_i_5__1 + (.I0(rTimeoutCnt_reg[4]), + .O(\rTimeoutCnt[4]_i_5__1_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[8]_i_2__1 + (.I0(rTimeoutCnt_reg[11]), + .O(\rTimeoutCnt[8]_i_2__1_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[8]_i_3__1 + (.I0(rTimeoutCnt_reg[10]), + .O(\rTimeoutCnt[8]_i_3__1_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[8]_i_4__1 + (.I0(rTimeoutCnt_reg[9]), + .O(\rTimeoutCnt[8]_i_4__1_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[8]_i_5__1 + (.I0(rTimeoutCnt_reg[8]), + .O(\rTimeoutCnt[8]_i_5__1_n_0 )); + FDRE \rTimeoutCnt_reg[0] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__1_n_0 ), + .D(\rTimeoutCnt_reg[0]_i_2__1_n_7 ), + .Q(rTimeoutCnt_reg[0]), + .R(rTimeoutRst)); + CARRY4 \rTimeoutCnt_reg[0]_i_2__1 + (.CI(1'b0), + .CO({\rTimeoutCnt_reg[0]_i_2__1_n_0 ,\rTimeoutCnt_reg[0]_i_2__1_n_1 ,\rTimeoutCnt_reg[0]_i_2__1_n_2 ,\rTimeoutCnt_reg[0]_i_2__1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\rTimeoutCnt_reg[0]_i_2__1_n_4 ,\rTimeoutCnt_reg[0]_i_2__1_n_5 ,\rTimeoutCnt_reg[0]_i_2__1_n_6 ,\rTimeoutCnt_reg[0]_i_2__1_n_7 }), + .S({\rTimeoutCnt[0]_i_3__1_n_0 ,\rTimeoutCnt[0]_i_4__1_n_0 ,\rTimeoutCnt[0]_i_5__1_n_0 ,\rTimeoutCnt[0]_i_6__1_n_0 })); + FDRE \rTimeoutCnt_reg[10] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__1_n_0 ), + .D(\rTimeoutCnt_reg[8]_i_1__1_n_5 ), + .Q(rTimeoutCnt_reg[10]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[11] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__1_n_0 ), + .D(\rTimeoutCnt_reg[8]_i_1__1_n_4 ), + .Q(rTimeoutCnt_reg[11]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[12] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__1_n_0 ), + .D(\rTimeoutCnt_reg[12]_i_1__1_n_7 ), + .Q(rTimeoutCnt_reg[12]), + .R(rTimeoutRst)); + CARRY4 \rTimeoutCnt_reg[12]_i_1__1 + (.CI(\rTimeoutCnt_reg[8]_i_1__1_n_0 ), + .CO({\rTimeoutCnt_reg[12]_i_1__1_n_0 ,\rTimeoutCnt_reg[12]_i_1__1_n_1 ,\rTimeoutCnt_reg[12]_i_1__1_n_2 ,\rTimeoutCnt_reg[12]_i_1__1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\rTimeoutCnt_reg[12]_i_1__1_n_4 ,\rTimeoutCnt_reg[12]_i_1__1_n_5 ,\rTimeoutCnt_reg[12]_i_1__1_n_6 ,\rTimeoutCnt_reg[12]_i_1__1_n_7 }), + .S({\rTimeoutCnt[12]_i_2__1_n_0 ,\rTimeoutCnt[12]_i_3__1_n_0 ,\rTimeoutCnt[12]_i_4__1_n_0 ,\rTimeoutCnt[12]_i_5__1_n_0 })); + FDRE \rTimeoutCnt_reg[13] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__1_n_0 ), + .D(\rTimeoutCnt_reg[12]_i_1__1_n_6 ), + .Q(rTimeoutCnt_reg[13]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[14] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__1_n_0 ), + .D(\rTimeoutCnt_reg[12]_i_1__1_n_5 ), + .Q(rTimeoutCnt_reg[14]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[15] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__1_n_0 ), + .D(\rTimeoutCnt_reg[12]_i_1__1_n_4 ), + .Q(rTimeoutCnt_reg[15]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[16] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__1_n_0 ), + .D(\rTimeoutCnt_reg[16]_i_1__1_n_7 ), + .Q(rTimeoutCnt_reg[16]), + .R(rTimeoutRst)); + CARRY4 \rTimeoutCnt_reg[16]_i_1__1 + (.CI(\rTimeoutCnt_reg[12]_i_1__1_n_0 ), + .CO({\rTimeoutCnt_reg[16]_i_1__1_n_0 ,\rTimeoutCnt_reg[16]_i_1__1_n_1 ,\rTimeoutCnt_reg[16]_i_1__1_n_2 ,\rTimeoutCnt_reg[16]_i_1__1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\rTimeoutCnt_reg[16]_i_1__1_n_4 ,\rTimeoutCnt_reg[16]_i_1__1_n_5 ,\rTimeoutCnt_reg[16]_i_1__1_n_6 ,\rTimeoutCnt_reg[16]_i_1__1_n_7 }), + .S({\rTimeoutCnt[16]_i_2__1_n_0 ,\rTimeoutCnt[16]_i_3__1_n_0 ,\rTimeoutCnt[16]_i_4__1_n_0 ,\rTimeoutCnt[16]_i_5__1_n_0 })); + FDRE \rTimeoutCnt_reg[17] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__1_n_0 ), + .D(\rTimeoutCnt_reg[16]_i_1__1_n_6 ), + .Q(rTimeoutCnt_reg[17]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[18] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__1_n_0 ), + .D(\rTimeoutCnt_reg[16]_i_1__1_n_5 ), + .Q(rTimeoutCnt_reg[18]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[19] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__1_n_0 ), + .D(\rTimeoutCnt_reg[16]_i_1__1_n_4 ), + .Q(rTimeoutCnt_reg[19]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[1] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__1_n_0 ), + .D(\rTimeoutCnt_reg[0]_i_2__1_n_6 ), + .Q(rTimeoutCnt_reg[1]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[20] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__1_n_0 ), + .D(\rTimeoutCnt_reg[20]_i_1__1_n_7 ), + .Q(rTimeoutCnt_reg[20]), + .R(rTimeoutRst)); + CARRY4 \rTimeoutCnt_reg[20]_i_1__1 + (.CI(\rTimeoutCnt_reg[16]_i_1__1_n_0 ), + .CO({\NLW_rTimeoutCnt_reg[20]_i_1__1_CO_UNCONNECTED [3],\rTimeoutCnt_reg[20]_i_1__1_n_1 ,\rTimeoutCnt_reg[20]_i_1__1_n_2 ,\rTimeoutCnt_reg[20]_i_1__1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\rTimeoutCnt_reg[20]_i_1__1_n_4 ,\rTimeoutCnt_reg[20]_i_1__1_n_5 ,\rTimeoutCnt_reg[20]_i_1__1_n_6 ,\rTimeoutCnt_reg[20]_i_1__1_n_7 }), + .S({\rTimeoutCnt[20]_i_2__1_n_0 ,\rTimeoutCnt[20]_i_3__1_n_0 ,\rTimeoutCnt[20]_i_4__1_n_0 ,\rTimeoutCnt[20]_i_5__1_n_0 })); + FDRE \rTimeoutCnt_reg[21] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__1_n_0 ), + .D(\rTimeoutCnt_reg[20]_i_1__1_n_6 ), + .Q(rTimeoutCnt_reg[21]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[22] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__1_n_0 ), + .D(\rTimeoutCnt_reg[20]_i_1__1_n_5 ), + .Q(rTimeoutCnt_reg[22]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[23] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__1_n_0 ), + .D(\rTimeoutCnt_reg[20]_i_1__1_n_4 ), + .Q(rTimeoutCnt_reg[23]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[2] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__1_n_0 ), + .D(\rTimeoutCnt_reg[0]_i_2__1_n_5 ), + .Q(rTimeoutCnt_reg[2]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[3] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__1_n_0 ), + .D(\rTimeoutCnt_reg[0]_i_2__1_n_4 ), + .Q(rTimeoutCnt_reg[3]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[4] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__1_n_0 ), + .D(\rTimeoutCnt_reg[4]_i_1__1_n_7 ), + .Q(rTimeoutCnt_reg[4]), + .R(rTimeoutRst)); + CARRY4 \rTimeoutCnt_reg[4]_i_1__1 + (.CI(\rTimeoutCnt_reg[0]_i_2__1_n_0 ), + .CO({\rTimeoutCnt_reg[4]_i_1__1_n_0 ,\rTimeoutCnt_reg[4]_i_1__1_n_1 ,\rTimeoutCnt_reg[4]_i_1__1_n_2 ,\rTimeoutCnt_reg[4]_i_1__1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\rTimeoutCnt_reg[4]_i_1__1_n_4 ,\rTimeoutCnt_reg[4]_i_1__1_n_5 ,\rTimeoutCnt_reg[4]_i_1__1_n_6 ,\rTimeoutCnt_reg[4]_i_1__1_n_7 }), + .S({\rTimeoutCnt[4]_i_2__1_n_0 ,\rTimeoutCnt[4]_i_3__1_n_0 ,\rTimeoutCnt[4]_i_4__1_n_0 ,\rTimeoutCnt[4]_i_5__1_n_0 })); + FDRE \rTimeoutCnt_reg[5] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__1_n_0 ), + .D(\rTimeoutCnt_reg[4]_i_1__1_n_6 ), + .Q(rTimeoutCnt_reg[5]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[6] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__1_n_0 ), + .D(\rTimeoutCnt_reg[4]_i_1__1_n_5 ), + .Q(rTimeoutCnt_reg[6]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[7] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__1_n_0 ), + .D(\rTimeoutCnt_reg[4]_i_1__1_n_4 ), + .Q(rTimeoutCnt_reg[7]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[8] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__1_n_0 ), + .D(\rTimeoutCnt_reg[8]_i_1__1_n_7 ), + .Q(rTimeoutCnt_reg[8]), + .R(rTimeoutRst)); + CARRY4 \rTimeoutCnt_reg[8]_i_1__1 + (.CI(\rTimeoutCnt_reg[4]_i_1__1_n_0 ), + .CO({\rTimeoutCnt_reg[8]_i_1__1_n_0 ,\rTimeoutCnt_reg[8]_i_1__1_n_1 ,\rTimeoutCnt_reg[8]_i_1__1_n_2 ,\rTimeoutCnt_reg[8]_i_1__1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\rTimeoutCnt_reg[8]_i_1__1_n_4 ,\rTimeoutCnt_reg[8]_i_1__1_n_5 ,\rTimeoutCnt_reg[8]_i_1__1_n_6 ,\rTimeoutCnt_reg[8]_i_1__1_n_7 }), + .S({\rTimeoutCnt[8]_i_2__1_n_0 ,\rTimeoutCnt[8]_i_3__1_n_0 ,\rTimeoutCnt[8]_i_4__1_n_0 ,\rTimeoutCnt[8]_i_5__1_n_0 })); + FDRE \rTimeoutCnt_reg[9] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__1_n_0 ), + .D(\rTimeoutCnt_reg[8]_i_1__1_n_6 ), + .Q(rTimeoutCnt_reg[9]), + .R(rTimeoutRst)); +endmodule + +(* ORIG_REF_NAME = "TMDS_Decoder" *) +module Arty_Z7_20_dvi2rgb_0_0_TMDS_Decoder_0 + (pMeRdy_int_reg, + pRdy_1, + pVld_1, + SR, + Q, + TMDS_Data_p, + TMDS_Data_n, + PixelClk_int, + \rMMCM_Reset_q_reg[0] , + CLKB, + AS, + RefClk, + pVld_2, + pVld_0, + pRdy_2, + pRdy_0, + pRst_n, + pAllVldBgnFlag, + pAllVld, + pMeRdy_int_reg_0); + output pMeRdy_int_reg; + output pRdy_1; + output pVld_1; + output [0:0]SR; + output [7:0]Q; + input [0:0]TMDS_Data_p; + input [0:0]TMDS_Data_n; + input PixelClk_int; + input \rMMCM_Reset_q_reg[0] ; + input CLKB; + input [0:0]AS; + input RefClk; + input pVld_2; + input pVld_0; + input pRdy_2; + input pRdy_0; + input pRst_n; + input pAllVldBgnFlag; + input pAllVld; + input [0:0]pMeRdy_int_reg_0; + + wire [0:0]AS; + wire CLKB; + wire PhaseAlignX_n_4; + wire PhaseAlignX_n_5; + wire PhaseAlignX_n_7; + wire PixelClk_int; + wire [7:0]Q; + wire RefClk; + wire [0:0]SR; + wire SyncBaseOvf_n_1; + wire SyncBaseOvf_n_2; + wire SyncBaseOvf_n_3; + wire SyncBaseOvf_n_4; + wire [0:0]TMDS_Data_n; + wire [0:0]TMDS_Data_p; + wire pAlignErr_q; + wire pAlignRst_i_1__0_n_0; + wire pAlignRst_reg_n_0; + wire pAllVld; + wire pAllVldBgnFlag; + wire pBitslip; + wire [1:0]pBitslipCnt; + wire \pBitslipCnt[0]_i_1_n_0 ; + wire \pBitslipCnt[1]_i_1_n_0 ; + wire [7:0]pDataIn; + wire [9:0]pDataInRaw; + wire pIDLY_CE; + wire [4:0]pIDLY_CNT; + wire pIDLY_INC; + wire pIDLY_LD; + wire pMeRdy_int_reg; + wire [0:0]pMeRdy_int_reg_0; + wire pRdy_0; + wire pRdy_1; + wire pRdy_2; + wire pRst_n; + wire pTimeoutOvf; + wire pVld_0; + wire pVld_1; + wire pVld_2; + wire \rMMCM_Reset_q_reg[0] ; + wire \rTimeoutCnt[0]_i_1__0_n_0 ; + wire \rTimeoutCnt[0]_i_3__0_n_0 ; + wire \rTimeoutCnt[0]_i_4__0_n_0 ; + wire \rTimeoutCnt[0]_i_5__0_n_0 ; + wire \rTimeoutCnt[0]_i_6__0_n_0 ; + wire \rTimeoutCnt[12]_i_2__0_n_0 ; + wire \rTimeoutCnt[12]_i_3__0_n_0 ; + wire \rTimeoutCnt[12]_i_4__0_n_0 ; + wire \rTimeoutCnt[12]_i_5__0_n_0 ; + wire \rTimeoutCnt[16]_i_2__0_n_0 ; + wire \rTimeoutCnt[16]_i_3__0_n_0 ; + wire \rTimeoutCnt[16]_i_4__0_n_0 ; + wire \rTimeoutCnt[16]_i_5__0_n_0 ; + wire \rTimeoutCnt[20]_i_2__0_n_0 ; + wire \rTimeoutCnt[20]_i_3__0_n_0 ; + wire \rTimeoutCnt[20]_i_4__0_n_0 ; + wire \rTimeoutCnt[20]_i_5__0_n_0 ; + wire \rTimeoutCnt[4]_i_2__0_n_0 ; + wire \rTimeoutCnt[4]_i_3__0_n_0 ; + wire \rTimeoutCnt[4]_i_4__0_n_0 ; + wire \rTimeoutCnt[4]_i_5__0_n_0 ; + wire \rTimeoutCnt[8]_i_2__0_n_0 ; + wire \rTimeoutCnt[8]_i_3__0_n_0 ; + wire \rTimeoutCnt[8]_i_4__0_n_0 ; + wire \rTimeoutCnt[8]_i_5__0_n_0 ; + wire [23:0]rTimeoutCnt_reg; + wire \rTimeoutCnt_reg[0]_i_2__0_n_0 ; + wire \rTimeoutCnt_reg[0]_i_2__0_n_1 ; + wire \rTimeoutCnt_reg[0]_i_2__0_n_2 ; + wire \rTimeoutCnt_reg[0]_i_2__0_n_3 ; + wire \rTimeoutCnt_reg[0]_i_2__0_n_4 ; + wire \rTimeoutCnt_reg[0]_i_2__0_n_5 ; + wire \rTimeoutCnt_reg[0]_i_2__0_n_6 ; + wire \rTimeoutCnt_reg[0]_i_2__0_n_7 ; + wire \rTimeoutCnt_reg[12]_i_1__0_n_0 ; + wire \rTimeoutCnt_reg[12]_i_1__0_n_1 ; + wire \rTimeoutCnt_reg[12]_i_1__0_n_2 ; + wire \rTimeoutCnt_reg[12]_i_1__0_n_3 ; + wire \rTimeoutCnt_reg[12]_i_1__0_n_4 ; + wire \rTimeoutCnt_reg[12]_i_1__0_n_5 ; + wire \rTimeoutCnt_reg[12]_i_1__0_n_6 ; + wire \rTimeoutCnt_reg[12]_i_1__0_n_7 ; + wire \rTimeoutCnt_reg[16]_i_1__0_n_0 ; + wire \rTimeoutCnt_reg[16]_i_1__0_n_1 ; + wire \rTimeoutCnt_reg[16]_i_1__0_n_2 ; + wire \rTimeoutCnt_reg[16]_i_1__0_n_3 ; + wire \rTimeoutCnt_reg[16]_i_1__0_n_4 ; + wire \rTimeoutCnt_reg[16]_i_1__0_n_5 ; + wire \rTimeoutCnt_reg[16]_i_1__0_n_6 ; + wire \rTimeoutCnt_reg[16]_i_1__0_n_7 ; + wire \rTimeoutCnt_reg[20]_i_1__0_n_1 ; + wire \rTimeoutCnt_reg[20]_i_1__0_n_2 ; + wire \rTimeoutCnt_reg[20]_i_1__0_n_3 ; + wire \rTimeoutCnt_reg[20]_i_1__0_n_4 ; + wire \rTimeoutCnt_reg[20]_i_1__0_n_5 ; + wire \rTimeoutCnt_reg[20]_i_1__0_n_6 ; + wire \rTimeoutCnt_reg[20]_i_1__0_n_7 ; + wire \rTimeoutCnt_reg[4]_i_1__0_n_0 ; + wire \rTimeoutCnt_reg[4]_i_1__0_n_1 ; + wire \rTimeoutCnt_reg[4]_i_1__0_n_2 ; + wire \rTimeoutCnt_reg[4]_i_1__0_n_3 ; + wire \rTimeoutCnt_reg[4]_i_1__0_n_4 ; + wire \rTimeoutCnt_reg[4]_i_1__0_n_5 ; + wire \rTimeoutCnt_reg[4]_i_1__0_n_6 ; + wire \rTimeoutCnt_reg[4]_i_1__0_n_7 ; + wire \rTimeoutCnt_reg[8]_i_1__0_n_0 ; + wire \rTimeoutCnt_reg[8]_i_1__0_n_1 ; + wire \rTimeoutCnt_reg[8]_i_1__0_n_2 ; + wire \rTimeoutCnt_reg[8]_i_1__0_n_3 ; + wire \rTimeoutCnt_reg[8]_i_1__0_n_4 ; + wire \rTimeoutCnt_reg[8]_i_1__0_n_5 ; + wire \rTimeoutCnt_reg[8]_i_1__0_n_6 ; + wire \rTimeoutCnt_reg[8]_i_1__0_n_7 ; + wire rTimeoutRst; + wire [3:3]\NLW_rTimeoutCnt_reg[20]_i_1__0_CO_UNCONNECTED ; + + Arty_Z7_20_dvi2rgb_0_0_ChannelBond_10 ChannelBondX + (.D(pDataIn), + .PixelClk_int(PixelClk_int), + .SR(pMeRdy_int_reg), + .pAllVld(pAllVld), + .pAllVldBgnFlag(pAllVldBgnFlag), + .pDataInRaw(pDataInRaw), + .\pDataIn_reg[7] (SR), + .pMeRdy_int_reg_0(pRdy_1), + .pRdy_0(pRdy_0), + .pRdy_2(pRdy_2)); + Arty_Z7_20_dvi2rgb_0_0_InputSERDES_11 InputSERDES_X + (.AS(AS), + .CLKB(CLKB), + .D(pIDLY_CNT), + .PixelClk_int(PixelClk_int), + .TMDS_Data_n(TMDS_Data_n), + .TMDS_Data_p(TMDS_Data_p), + .pBitslip(pBitslip), + .pDataInRaw(pDataInRaw), + .pIDLY_CE(pIDLY_CE), + .pIDLY_INC(pIDLY_INC), + .pIDLY_LD(pIDLY_LD), + .\rMMCM_Reset_q_reg[0] (\rMMCM_Reset_q_reg[0] )); + Arty_Z7_20_dvi2rgb_0_0_PhaseAlign_12 PhaseAlignX + (.D(pDataInRaw[8:0]), + .PixelClk_int(PixelClk_int), + .SS(pAlignRst_reg_n_0), + .iIn_q_reg(PhaseAlignX_n_5), + .out(pTimeoutOvf), + .pAlignErr_q(pAlignErr_q), + .pAlignErr_q_reg(PhaseAlignX_n_4), + .pBitslip_reg(PhaseAlignX_n_7), + .pIDLY_CE(pIDLY_CE), + .pIDLY_CE_reg_0(pIDLY_CNT), + .pIDLY_INC(pIDLY_INC), + .pIDLY_LD(pIDLY_LD), + .pMeRdy_int_reg(pMeRdy_int_reg), + .pVld_0(pVld_0), + .pVld_1(pVld_1), + .pVld_2(pVld_2)); + Arty_Z7_20_dvi2rgb_0_0_SyncBase_13 SyncBaseOvf + (.AS(AS), + .PixelClk_int(PixelClk_int), + .RefClk(RefClk), + .iIn_q_reg_0(SyncBaseOvf_n_1), + .iIn_q_reg_1(SyncBaseOvf_n_2), + .iIn_q_reg_2(SyncBaseOvf_n_3), + .iIn_q_reg_3(SyncBaseOvf_n_4), + .out(pTimeoutOvf), + .rTimeoutCnt_reg(rTimeoutCnt_reg)); + Arty_Z7_20_dvi2rgb_0_0_SyncBase__parameterized0_14 SyncBaseRst + (.AS(AS), + .PixelClk_int(PixelClk_int), + .RefClk(RefClk), + .out(rTimeoutRst), + .\pState_reg[1] (PhaseAlignX_n_5)); + FDRE pAlignErr_q_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(PhaseAlignX_n_4), + .Q(pAlignErr_q), + .R(1'b0)); + LUT5 #( + .INIT(32'hFFFDDDDD)) + pAlignRst_i_1__0 + (.I0(pRst_n), + .I1(pBitslip), + .I2(pBitslipCnt[1]), + .I3(pBitslipCnt[0]), + .I4(pAlignRst_reg_n_0), + .O(pAlignRst_i_1__0_n_0)); + FDPE pAlignRst_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pAlignRst_i_1__0_n_0), + .PRE(AS), + .Q(pAlignRst_reg_n_0)); + (* SOFT_HLUTNM = "soft_lutpair52" *) + LUT3 #( + .INIT(8'h04)) + \pBitslipCnt[0]_i_1 + (.I0(pBitslipCnt[0]), + .I1(pBitslipCnt[1]), + .I2(pBitslip), + .O(\pBitslipCnt[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair52" *) + LUT3 #( + .INIT(8'hF8)) + \pBitslipCnt[1]_i_1 + (.I0(pBitslipCnt[0]), + .I1(pBitslipCnt[1]), + .I2(pBitslip), + .O(\pBitslipCnt[1]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \pBitslipCnt_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(\pBitslipCnt[0]_i_1_n_0 ), + .Q(pBitslipCnt[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + \pBitslipCnt_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .D(\pBitslipCnt[1]_i_1_n_0 ), + .Q(pBitslipCnt[1]), + .R(1'b0)); + FDRE pBitslip_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(PhaseAlignX_n_7), + .Q(pBitslip), + .R(1'b0)); + FDRE \pDataIn_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(pDataIn[0]), + .Q(Q[0]), + .R(pMeRdy_int_reg_0)); + FDRE \pDataIn_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .D(pDataIn[1]), + .Q(Q[1]), + .R(pMeRdy_int_reg_0)); + FDRE \pDataIn_reg[2] + (.C(PixelClk_int), + .CE(1'b1), + .D(pDataIn[2]), + .Q(Q[2]), + .R(pMeRdy_int_reg_0)); + FDRE \pDataIn_reg[3] + (.C(PixelClk_int), + .CE(1'b1), + .D(pDataIn[3]), + .Q(Q[3]), + .R(pMeRdy_int_reg_0)); + FDRE \pDataIn_reg[4] + (.C(PixelClk_int), + .CE(1'b1), + .D(pDataIn[4]), + .Q(Q[4]), + .R(pMeRdy_int_reg_0)); + FDRE \pDataIn_reg[5] + (.C(PixelClk_int), + .CE(1'b1), + .D(pDataIn[5]), + .Q(Q[5]), + .R(pMeRdy_int_reg_0)); + FDRE \pDataIn_reg[6] + (.C(PixelClk_int), + .CE(1'b1), + .D(pDataIn[6]), + .Q(Q[6]), + .R(pMeRdy_int_reg_0)); + FDRE \pDataIn_reg[7] + (.C(PixelClk_int), + .CE(1'b1), + .D(pDataIn[7]), + .Q(Q[7]), + .R(pMeRdy_int_reg_0)); + LUT4 #( + .INIT(16'hBFFF)) + \rTimeoutCnt[0]_i_1__0 + (.I0(SyncBaseOvf_n_1), + .I1(SyncBaseOvf_n_2), + .I2(SyncBaseOvf_n_3), + .I3(SyncBaseOvf_n_4), + .O(\rTimeoutCnt[0]_i_1__0_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[0]_i_3__0 + (.I0(rTimeoutCnt_reg[3]), + .O(\rTimeoutCnt[0]_i_3__0_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[0]_i_4__0 + (.I0(rTimeoutCnt_reg[2]), + .O(\rTimeoutCnt[0]_i_4__0_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[0]_i_5__0 + (.I0(rTimeoutCnt_reg[1]), + .O(\rTimeoutCnt[0]_i_5__0_n_0 )); + LUT1 #( + .INIT(2'h1)) + \rTimeoutCnt[0]_i_6__0 + (.I0(rTimeoutCnt_reg[0]), + .O(\rTimeoutCnt[0]_i_6__0_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[12]_i_2__0 + (.I0(rTimeoutCnt_reg[15]), + .O(\rTimeoutCnt[12]_i_2__0_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[12]_i_3__0 + (.I0(rTimeoutCnt_reg[14]), + .O(\rTimeoutCnt[12]_i_3__0_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[12]_i_4__0 + (.I0(rTimeoutCnt_reg[13]), + .O(\rTimeoutCnt[12]_i_4__0_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[12]_i_5__0 + (.I0(rTimeoutCnt_reg[12]), + .O(\rTimeoutCnt[12]_i_5__0_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[16]_i_2__0 + (.I0(rTimeoutCnt_reg[19]), + .O(\rTimeoutCnt[16]_i_2__0_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[16]_i_3__0 + (.I0(rTimeoutCnt_reg[18]), + .O(\rTimeoutCnt[16]_i_3__0_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[16]_i_4__0 + (.I0(rTimeoutCnt_reg[17]), + .O(\rTimeoutCnt[16]_i_4__0_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[16]_i_5__0 + (.I0(rTimeoutCnt_reg[16]), + .O(\rTimeoutCnt[16]_i_5__0_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[20]_i_2__0 + (.I0(rTimeoutCnt_reg[23]), + .O(\rTimeoutCnt[20]_i_2__0_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[20]_i_3__0 + (.I0(rTimeoutCnt_reg[22]), + .O(\rTimeoutCnt[20]_i_3__0_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[20]_i_4__0 + (.I0(rTimeoutCnt_reg[21]), + .O(\rTimeoutCnt[20]_i_4__0_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[20]_i_5__0 + (.I0(rTimeoutCnt_reg[20]), + .O(\rTimeoutCnt[20]_i_5__0_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[4]_i_2__0 + (.I0(rTimeoutCnt_reg[7]), + .O(\rTimeoutCnt[4]_i_2__0_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[4]_i_3__0 + (.I0(rTimeoutCnt_reg[6]), + .O(\rTimeoutCnt[4]_i_3__0_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[4]_i_4__0 + (.I0(rTimeoutCnt_reg[5]), + .O(\rTimeoutCnt[4]_i_4__0_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[4]_i_5__0 + (.I0(rTimeoutCnt_reg[4]), + .O(\rTimeoutCnt[4]_i_5__0_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[8]_i_2__0 + (.I0(rTimeoutCnt_reg[11]), + .O(\rTimeoutCnt[8]_i_2__0_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[8]_i_3__0 + (.I0(rTimeoutCnt_reg[10]), + .O(\rTimeoutCnt[8]_i_3__0_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[8]_i_4__0 + (.I0(rTimeoutCnt_reg[9]), + .O(\rTimeoutCnt[8]_i_4__0_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[8]_i_5__0 + (.I0(rTimeoutCnt_reg[8]), + .O(\rTimeoutCnt[8]_i_5__0_n_0 )); + FDRE \rTimeoutCnt_reg[0] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__0_n_0 ), + .D(\rTimeoutCnt_reg[0]_i_2__0_n_7 ), + .Q(rTimeoutCnt_reg[0]), + .R(rTimeoutRst)); + CARRY4 \rTimeoutCnt_reg[0]_i_2__0 + (.CI(1'b0), + .CO({\rTimeoutCnt_reg[0]_i_2__0_n_0 ,\rTimeoutCnt_reg[0]_i_2__0_n_1 ,\rTimeoutCnt_reg[0]_i_2__0_n_2 ,\rTimeoutCnt_reg[0]_i_2__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\rTimeoutCnt_reg[0]_i_2__0_n_4 ,\rTimeoutCnt_reg[0]_i_2__0_n_5 ,\rTimeoutCnt_reg[0]_i_2__0_n_6 ,\rTimeoutCnt_reg[0]_i_2__0_n_7 }), + .S({\rTimeoutCnt[0]_i_3__0_n_0 ,\rTimeoutCnt[0]_i_4__0_n_0 ,\rTimeoutCnt[0]_i_5__0_n_0 ,\rTimeoutCnt[0]_i_6__0_n_0 })); + FDRE \rTimeoutCnt_reg[10] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__0_n_0 ), + .D(\rTimeoutCnt_reg[8]_i_1__0_n_5 ), + .Q(rTimeoutCnt_reg[10]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[11] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__0_n_0 ), + .D(\rTimeoutCnt_reg[8]_i_1__0_n_4 ), + .Q(rTimeoutCnt_reg[11]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[12] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__0_n_0 ), + .D(\rTimeoutCnt_reg[12]_i_1__0_n_7 ), + .Q(rTimeoutCnt_reg[12]), + .R(rTimeoutRst)); + CARRY4 \rTimeoutCnt_reg[12]_i_1__0 + (.CI(\rTimeoutCnt_reg[8]_i_1__0_n_0 ), + .CO({\rTimeoutCnt_reg[12]_i_1__0_n_0 ,\rTimeoutCnt_reg[12]_i_1__0_n_1 ,\rTimeoutCnt_reg[12]_i_1__0_n_2 ,\rTimeoutCnt_reg[12]_i_1__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\rTimeoutCnt_reg[12]_i_1__0_n_4 ,\rTimeoutCnt_reg[12]_i_1__0_n_5 ,\rTimeoutCnt_reg[12]_i_1__0_n_6 ,\rTimeoutCnt_reg[12]_i_1__0_n_7 }), + .S({\rTimeoutCnt[12]_i_2__0_n_0 ,\rTimeoutCnt[12]_i_3__0_n_0 ,\rTimeoutCnt[12]_i_4__0_n_0 ,\rTimeoutCnt[12]_i_5__0_n_0 })); + FDRE \rTimeoutCnt_reg[13] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__0_n_0 ), + .D(\rTimeoutCnt_reg[12]_i_1__0_n_6 ), + .Q(rTimeoutCnt_reg[13]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[14] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__0_n_0 ), + .D(\rTimeoutCnt_reg[12]_i_1__0_n_5 ), + .Q(rTimeoutCnt_reg[14]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[15] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__0_n_0 ), + .D(\rTimeoutCnt_reg[12]_i_1__0_n_4 ), + .Q(rTimeoutCnt_reg[15]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[16] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__0_n_0 ), + .D(\rTimeoutCnt_reg[16]_i_1__0_n_7 ), + .Q(rTimeoutCnt_reg[16]), + .R(rTimeoutRst)); + CARRY4 \rTimeoutCnt_reg[16]_i_1__0 + (.CI(\rTimeoutCnt_reg[12]_i_1__0_n_0 ), + .CO({\rTimeoutCnt_reg[16]_i_1__0_n_0 ,\rTimeoutCnt_reg[16]_i_1__0_n_1 ,\rTimeoutCnt_reg[16]_i_1__0_n_2 ,\rTimeoutCnt_reg[16]_i_1__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\rTimeoutCnt_reg[16]_i_1__0_n_4 ,\rTimeoutCnt_reg[16]_i_1__0_n_5 ,\rTimeoutCnt_reg[16]_i_1__0_n_6 ,\rTimeoutCnt_reg[16]_i_1__0_n_7 }), + .S({\rTimeoutCnt[16]_i_2__0_n_0 ,\rTimeoutCnt[16]_i_3__0_n_0 ,\rTimeoutCnt[16]_i_4__0_n_0 ,\rTimeoutCnt[16]_i_5__0_n_0 })); + FDRE \rTimeoutCnt_reg[17] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__0_n_0 ), + .D(\rTimeoutCnt_reg[16]_i_1__0_n_6 ), + .Q(rTimeoutCnt_reg[17]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[18] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__0_n_0 ), + .D(\rTimeoutCnt_reg[16]_i_1__0_n_5 ), + .Q(rTimeoutCnt_reg[18]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[19] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__0_n_0 ), + .D(\rTimeoutCnt_reg[16]_i_1__0_n_4 ), + .Q(rTimeoutCnt_reg[19]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[1] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__0_n_0 ), + .D(\rTimeoutCnt_reg[0]_i_2__0_n_6 ), + .Q(rTimeoutCnt_reg[1]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[20] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__0_n_0 ), + .D(\rTimeoutCnt_reg[20]_i_1__0_n_7 ), + .Q(rTimeoutCnt_reg[20]), + .R(rTimeoutRst)); + CARRY4 \rTimeoutCnt_reg[20]_i_1__0 + (.CI(\rTimeoutCnt_reg[16]_i_1__0_n_0 ), + .CO({\NLW_rTimeoutCnt_reg[20]_i_1__0_CO_UNCONNECTED [3],\rTimeoutCnt_reg[20]_i_1__0_n_1 ,\rTimeoutCnt_reg[20]_i_1__0_n_2 ,\rTimeoutCnt_reg[20]_i_1__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\rTimeoutCnt_reg[20]_i_1__0_n_4 ,\rTimeoutCnt_reg[20]_i_1__0_n_5 ,\rTimeoutCnt_reg[20]_i_1__0_n_6 ,\rTimeoutCnt_reg[20]_i_1__0_n_7 }), + .S({\rTimeoutCnt[20]_i_2__0_n_0 ,\rTimeoutCnt[20]_i_3__0_n_0 ,\rTimeoutCnt[20]_i_4__0_n_0 ,\rTimeoutCnt[20]_i_5__0_n_0 })); + FDRE \rTimeoutCnt_reg[21] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__0_n_0 ), + .D(\rTimeoutCnt_reg[20]_i_1__0_n_6 ), + .Q(rTimeoutCnt_reg[21]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[22] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__0_n_0 ), + .D(\rTimeoutCnt_reg[20]_i_1__0_n_5 ), + .Q(rTimeoutCnt_reg[22]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[23] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__0_n_0 ), + .D(\rTimeoutCnt_reg[20]_i_1__0_n_4 ), + .Q(rTimeoutCnt_reg[23]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[2] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__0_n_0 ), + .D(\rTimeoutCnt_reg[0]_i_2__0_n_5 ), + .Q(rTimeoutCnt_reg[2]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[3] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__0_n_0 ), + .D(\rTimeoutCnt_reg[0]_i_2__0_n_4 ), + .Q(rTimeoutCnt_reg[3]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[4] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__0_n_0 ), + .D(\rTimeoutCnt_reg[4]_i_1__0_n_7 ), + .Q(rTimeoutCnt_reg[4]), + .R(rTimeoutRst)); + CARRY4 \rTimeoutCnt_reg[4]_i_1__0 + (.CI(\rTimeoutCnt_reg[0]_i_2__0_n_0 ), + .CO({\rTimeoutCnt_reg[4]_i_1__0_n_0 ,\rTimeoutCnt_reg[4]_i_1__0_n_1 ,\rTimeoutCnt_reg[4]_i_1__0_n_2 ,\rTimeoutCnt_reg[4]_i_1__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\rTimeoutCnt_reg[4]_i_1__0_n_4 ,\rTimeoutCnt_reg[4]_i_1__0_n_5 ,\rTimeoutCnt_reg[4]_i_1__0_n_6 ,\rTimeoutCnt_reg[4]_i_1__0_n_7 }), + .S({\rTimeoutCnt[4]_i_2__0_n_0 ,\rTimeoutCnt[4]_i_3__0_n_0 ,\rTimeoutCnt[4]_i_4__0_n_0 ,\rTimeoutCnt[4]_i_5__0_n_0 })); + FDRE \rTimeoutCnt_reg[5] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__0_n_0 ), + .D(\rTimeoutCnt_reg[4]_i_1__0_n_6 ), + .Q(rTimeoutCnt_reg[5]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[6] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__0_n_0 ), + .D(\rTimeoutCnt_reg[4]_i_1__0_n_5 ), + .Q(rTimeoutCnt_reg[6]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[7] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__0_n_0 ), + .D(\rTimeoutCnt_reg[4]_i_1__0_n_4 ), + .Q(rTimeoutCnt_reg[7]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[8] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__0_n_0 ), + .D(\rTimeoutCnt_reg[8]_i_1__0_n_7 ), + .Q(rTimeoutCnt_reg[8]), + .R(rTimeoutRst)); + CARRY4 \rTimeoutCnt_reg[8]_i_1__0 + (.CI(\rTimeoutCnt_reg[4]_i_1__0_n_0 ), + .CO({\rTimeoutCnt_reg[8]_i_1__0_n_0 ,\rTimeoutCnt_reg[8]_i_1__0_n_1 ,\rTimeoutCnt_reg[8]_i_1__0_n_2 ,\rTimeoutCnt_reg[8]_i_1__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\rTimeoutCnt_reg[8]_i_1__0_n_4 ,\rTimeoutCnt_reg[8]_i_1__0_n_5 ,\rTimeoutCnt_reg[8]_i_1__0_n_6 ,\rTimeoutCnt_reg[8]_i_1__0_n_7 }), + .S({\rTimeoutCnt[8]_i_2__0_n_0 ,\rTimeoutCnt[8]_i_3__0_n_0 ,\rTimeoutCnt[8]_i_4__0_n_0 ,\rTimeoutCnt[8]_i_5__0_n_0 })); + FDRE \rTimeoutCnt_reg[9] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1__0_n_0 ), + .D(\rTimeoutCnt_reg[8]_i_1__0_n_6 ), + .Q(rTimeoutCnt_reg[9]), + .R(rTimeoutRst)); +endmodule + +(* ORIG_REF_NAME = "TMDS_Decoder" *) +module Arty_Z7_20_dvi2rgb_0_0_TMDS_Decoder_1 + (pAllVldBgnFlag, + pVld_2, + pRdy_2, + SR, + Q, + TMDS_Data_p, + TMDS_Data_n, + PixelClk_int, + \rMMCM_Reset_q_reg[0] , + CLKB, + out, + RefClk, + pAllVld, + pAligned_reg, + pVld_0, + pVld_1, + pRdy_0, + pRdy_1, + pRst_n, + pMeRdy_int_reg); + output pAllVldBgnFlag; + output pVld_2; + output pRdy_2; + output [0:0]SR; + output [7:0]Q; + input [0:0]TMDS_Data_p; + input [0:0]TMDS_Data_n; + input PixelClk_int; + input \rMMCM_Reset_q_reg[0] ; + input CLKB; + input [0:0]out; + input RefClk; + input pAllVld; + input pAligned_reg; + input pVld_0; + input pVld_1; + input pRdy_0; + input pRdy_1; + input pRst_n; + input [0:0]pMeRdy_int_reg; + + wire CLKB; + wire PhaseAlignX_n_4; + wire PhaseAlignX_n_5; + wire PhaseAlignX_n_7; + wire PixelClk_int; + wire [7:0]Q; + wire RefClk; + wire [0:0]SR; + wire SyncBaseOvf_n_1; + wire SyncBaseOvf_n_2; + wire SyncBaseOvf_n_3; + wire SyncBaseOvf_n_4; + wire [0:0]TMDS_Data_n; + wire [0:0]TMDS_Data_p; + wire [0:0]out; + wire pAlignErr_q; + wire pAlignRst; + wire pAlignRst_i_1_n_0; + wire pAligned_reg; + wire pAllVld; + wire pAllVldBgnFlag; + wire pAllVldBgnFlag0; + wire pAllVld_q; + wire pBitslip; + wire [1:0]pBitslipCnt; + wire \pBitslipCnt[0]_i_1_n_0 ; + wire \pBitslipCnt[1]_i_1_n_0 ; + wire [7:0]pDataIn; + wire [9:0]pDataInRaw; + wire pIDLY_CE; + wire [4:0]pIDLY_CNT; + wire pIDLY_INC; + wire pIDLY_LD; + wire [0:0]pMeRdy_int_reg; + wire pRdy_0; + wire pRdy_1; + wire pRdy_2; + wire pRst_n; + wire pTimeoutOvf; + wire pVld_0; + wire pVld_1; + wire pVld_2; + wire \rMMCM_Reset_q_reg[0] ; + wire \rTimeoutCnt[0]_i_1_n_0 ; + wire \rTimeoutCnt[0]_i_3_n_0 ; + wire \rTimeoutCnt[0]_i_4_n_0 ; + wire \rTimeoutCnt[0]_i_5_n_0 ; + wire \rTimeoutCnt[0]_i_6_n_0 ; + wire \rTimeoutCnt[12]_i_2_n_0 ; + wire \rTimeoutCnt[12]_i_3_n_0 ; + wire \rTimeoutCnt[12]_i_4_n_0 ; + wire \rTimeoutCnt[12]_i_5_n_0 ; + wire \rTimeoutCnt[16]_i_2_n_0 ; + wire \rTimeoutCnt[16]_i_3_n_0 ; + wire \rTimeoutCnt[16]_i_4_n_0 ; + wire \rTimeoutCnt[16]_i_5_n_0 ; + wire \rTimeoutCnt[20]_i_2_n_0 ; + wire \rTimeoutCnt[20]_i_3_n_0 ; + wire \rTimeoutCnt[20]_i_4_n_0 ; + wire \rTimeoutCnt[20]_i_5_n_0 ; + wire \rTimeoutCnt[4]_i_2_n_0 ; + wire \rTimeoutCnt[4]_i_3_n_0 ; + wire \rTimeoutCnt[4]_i_4_n_0 ; + wire \rTimeoutCnt[4]_i_5_n_0 ; + wire \rTimeoutCnt[8]_i_2_n_0 ; + wire \rTimeoutCnt[8]_i_3_n_0 ; + wire \rTimeoutCnt[8]_i_4_n_0 ; + wire \rTimeoutCnt[8]_i_5_n_0 ; + wire [23:0]rTimeoutCnt_reg; + wire \rTimeoutCnt_reg[0]_i_2_n_0 ; + wire \rTimeoutCnt_reg[0]_i_2_n_1 ; + wire \rTimeoutCnt_reg[0]_i_2_n_2 ; + wire \rTimeoutCnt_reg[0]_i_2_n_3 ; + wire \rTimeoutCnt_reg[0]_i_2_n_4 ; + wire \rTimeoutCnt_reg[0]_i_2_n_5 ; + wire \rTimeoutCnt_reg[0]_i_2_n_6 ; + wire \rTimeoutCnt_reg[0]_i_2_n_7 ; + wire \rTimeoutCnt_reg[12]_i_1_n_0 ; + wire \rTimeoutCnt_reg[12]_i_1_n_1 ; + wire \rTimeoutCnt_reg[12]_i_1_n_2 ; + wire \rTimeoutCnt_reg[12]_i_1_n_3 ; + wire \rTimeoutCnt_reg[12]_i_1_n_4 ; + wire \rTimeoutCnt_reg[12]_i_1_n_5 ; + wire \rTimeoutCnt_reg[12]_i_1_n_6 ; + wire \rTimeoutCnt_reg[12]_i_1_n_7 ; + wire \rTimeoutCnt_reg[16]_i_1_n_0 ; + wire \rTimeoutCnt_reg[16]_i_1_n_1 ; + wire \rTimeoutCnt_reg[16]_i_1_n_2 ; + wire \rTimeoutCnt_reg[16]_i_1_n_3 ; + wire \rTimeoutCnt_reg[16]_i_1_n_4 ; + wire \rTimeoutCnt_reg[16]_i_1_n_5 ; + wire \rTimeoutCnt_reg[16]_i_1_n_6 ; + wire \rTimeoutCnt_reg[16]_i_1_n_7 ; + wire \rTimeoutCnt_reg[20]_i_1_n_1 ; + wire \rTimeoutCnt_reg[20]_i_1_n_2 ; + wire \rTimeoutCnt_reg[20]_i_1_n_3 ; + wire \rTimeoutCnt_reg[20]_i_1_n_4 ; + wire \rTimeoutCnt_reg[20]_i_1_n_5 ; + wire \rTimeoutCnt_reg[20]_i_1_n_6 ; + wire \rTimeoutCnt_reg[20]_i_1_n_7 ; + wire \rTimeoutCnt_reg[4]_i_1_n_0 ; + wire \rTimeoutCnt_reg[4]_i_1_n_1 ; + wire \rTimeoutCnt_reg[4]_i_1_n_2 ; + wire \rTimeoutCnt_reg[4]_i_1_n_3 ; + wire \rTimeoutCnt_reg[4]_i_1_n_4 ; + wire \rTimeoutCnt_reg[4]_i_1_n_5 ; + wire \rTimeoutCnt_reg[4]_i_1_n_6 ; + wire \rTimeoutCnt_reg[4]_i_1_n_7 ; + wire \rTimeoutCnt_reg[8]_i_1_n_0 ; + wire \rTimeoutCnt_reg[8]_i_1_n_1 ; + wire \rTimeoutCnt_reg[8]_i_1_n_2 ; + wire \rTimeoutCnt_reg[8]_i_1_n_3 ; + wire \rTimeoutCnt_reg[8]_i_1_n_4 ; + wire \rTimeoutCnt_reg[8]_i_1_n_5 ; + wire \rTimeoutCnt_reg[8]_i_1_n_6 ; + wire \rTimeoutCnt_reg[8]_i_1_n_7 ; + wire rTimeoutRst; + wire [3:3]\NLW_rTimeoutCnt_reg[20]_i_1_CO_UNCONNECTED ; + + Arty_Z7_20_dvi2rgb_0_0_ChannelBond ChannelBondX + (.D(pDataIn), + .PixelClk_int(PixelClk_int), + .SR(SR), + .pAligned_reg(pAligned_reg), + .pAllVld(pAllVld), + .pAllVldBgnFlag(pAllVldBgnFlag), + .pAllVldBgnFlag0(pAllVldBgnFlag0), + .pAllVld_q(pAllVld_q), + .pDataInRaw(pDataInRaw), + .pMeRdy_int_reg_0(pRdy_2), + .pRdy_0(pRdy_0), + .pRdy_1(pRdy_1)); + Arty_Z7_20_dvi2rgb_0_0_InputSERDES InputSERDES_X + (.CLKB(CLKB), + .D(pIDLY_CNT), + .PixelClk_int(PixelClk_int), + .TMDS_Data_n(TMDS_Data_n), + .TMDS_Data_p(TMDS_Data_p), + .out(out), + .pBitslip(pBitslip), + .pDataInRaw(pDataInRaw), + .pIDLY_CE(pIDLY_CE), + .pIDLY_INC(pIDLY_INC), + .pIDLY_LD(pIDLY_LD), + .\rMMCM_Reset_q_reg[0] (\rMMCM_Reset_q_reg[0] )); + Arty_Z7_20_dvi2rgb_0_0_PhaseAlign PhaseAlignX + (.D(pDataInRaw[8:0]), + .PixelClk_int(PixelClk_int), + .SR(pAlignRst), + .iIn_q_reg(PhaseAlignX_n_5), + .out(pTimeoutOvf), + .pAlignErr_q(pAlignErr_q), + .pAlignErr_q_reg(PhaseAlignX_n_4), + .pAllVldBgnFlag0(pAllVldBgnFlag0), + .pAllVld_q(pAllVld_q), + .pBitslip_reg(PhaseAlignX_n_7), + .pIDLY_CE(pIDLY_CE), + .pIDLY_CE_reg_0(pIDLY_CNT), + .pIDLY_INC(pIDLY_INC), + .pIDLY_LD(pIDLY_LD), + .pVld_0(pVld_0), + .pVld_1(pVld_1), + .pVld_2(pVld_2)); + Arty_Z7_20_dvi2rgb_0_0_SyncBase SyncBaseOvf + (.PixelClk_int(PixelClk_int), + .RefClk(RefClk), + .iIn_q_reg_0(SyncBaseOvf_n_1), + .iIn_q_reg_1(SyncBaseOvf_n_2), + .iIn_q_reg_2(SyncBaseOvf_n_3), + .iIn_q_reg_3(SyncBaseOvf_n_4), + .\oSyncStages_reg[1] (out), + .out(pTimeoutOvf), + .rTimeoutCnt_reg(rTimeoutCnt_reg)); + Arty_Z7_20_dvi2rgb_0_0_SyncBase__parameterized0 SyncBaseRst + (.PixelClk_int(PixelClk_int), + .RefClk(RefClk), + .\oSyncStages_reg[1] (out), + .out(rTimeoutRst), + .\pState_reg[1] (PhaseAlignX_n_5)); + FDRE pAlignErr_q_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(PhaseAlignX_n_4), + .Q(pAlignErr_q), + .R(1'b0)); + LUT5 #( + .INIT(32'hFFFDDDDD)) + pAlignRst_i_1 + (.I0(pRst_n), + .I1(pBitslip), + .I2(pBitslipCnt[1]), + .I3(pBitslipCnt[0]), + .I4(pAlignRst), + .O(pAlignRst_i_1_n_0)); + FDPE pAlignRst_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(pAlignRst_i_1_n_0), + .PRE(out), + .Q(pAlignRst)); + (* SOFT_HLUTNM = "soft_lutpair80" *) + LUT3 #( + .INIT(8'h04)) + \pBitslipCnt[0]_i_1 + (.I0(pBitslipCnt[0]), + .I1(pBitslipCnt[1]), + .I2(pBitslip), + .O(\pBitslipCnt[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair80" *) + LUT3 #( + .INIT(8'hF8)) + \pBitslipCnt[1]_i_1 + (.I0(pBitslipCnt[0]), + .I1(pBitslipCnt[1]), + .I2(pBitslip), + .O(\pBitslipCnt[1]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \pBitslipCnt_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(\pBitslipCnt[0]_i_1_n_0 ), + .Q(pBitslipCnt[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + \pBitslipCnt_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .D(\pBitslipCnt[1]_i_1_n_0 ), + .Q(pBitslipCnt[1]), + .R(1'b0)); + FDRE pBitslip_reg + (.C(PixelClk_int), + .CE(1'b1), + .D(PhaseAlignX_n_7), + .Q(pBitslip), + .R(1'b0)); + FDRE \pDataIn_reg[0] + (.C(PixelClk_int), + .CE(1'b1), + .D(pDataIn[0]), + .Q(Q[0]), + .R(pMeRdy_int_reg)); + FDRE \pDataIn_reg[1] + (.C(PixelClk_int), + .CE(1'b1), + .D(pDataIn[1]), + .Q(Q[1]), + .R(pMeRdy_int_reg)); + FDRE \pDataIn_reg[2] + (.C(PixelClk_int), + .CE(1'b1), + .D(pDataIn[2]), + .Q(Q[2]), + .R(pMeRdy_int_reg)); + FDRE \pDataIn_reg[3] + (.C(PixelClk_int), + .CE(1'b1), + .D(pDataIn[3]), + .Q(Q[3]), + .R(pMeRdy_int_reg)); + FDRE \pDataIn_reg[4] + (.C(PixelClk_int), + .CE(1'b1), + .D(pDataIn[4]), + .Q(Q[4]), + .R(pMeRdy_int_reg)); + FDRE \pDataIn_reg[5] + (.C(PixelClk_int), + .CE(1'b1), + .D(pDataIn[5]), + .Q(Q[5]), + .R(pMeRdy_int_reg)); + FDRE \pDataIn_reg[6] + (.C(PixelClk_int), + .CE(1'b1), + .D(pDataIn[6]), + .Q(Q[6]), + .R(pMeRdy_int_reg)); + FDRE \pDataIn_reg[7] + (.C(PixelClk_int), + .CE(1'b1), + .D(pDataIn[7]), + .Q(Q[7]), + .R(pMeRdy_int_reg)); + LUT4 #( + .INIT(16'hBFFF)) + \rTimeoutCnt[0]_i_1 + (.I0(SyncBaseOvf_n_1), + .I1(SyncBaseOvf_n_2), + .I2(SyncBaseOvf_n_3), + .I3(SyncBaseOvf_n_4), + .O(\rTimeoutCnt[0]_i_1_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[0]_i_3 + (.I0(rTimeoutCnt_reg[3]), + .O(\rTimeoutCnt[0]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[0]_i_4 + (.I0(rTimeoutCnt_reg[2]), + .O(\rTimeoutCnt[0]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[0]_i_5 + (.I0(rTimeoutCnt_reg[1]), + .O(\rTimeoutCnt[0]_i_5_n_0 )); + LUT1 #( + .INIT(2'h1)) + \rTimeoutCnt[0]_i_6 + (.I0(rTimeoutCnt_reg[0]), + .O(\rTimeoutCnt[0]_i_6_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[12]_i_2 + (.I0(rTimeoutCnt_reg[15]), + .O(\rTimeoutCnt[12]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[12]_i_3 + (.I0(rTimeoutCnt_reg[14]), + .O(\rTimeoutCnt[12]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[12]_i_4 + (.I0(rTimeoutCnt_reg[13]), + .O(\rTimeoutCnt[12]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[12]_i_5 + (.I0(rTimeoutCnt_reg[12]), + .O(\rTimeoutCnt[12]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[16]_i_2 + (.I0(rTimeoutCnt_reg[19]), + .O(\rTimeoutCnt[16]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[16]_i_3 + (.I0(rTimeoutCnt_reg[18]), + .O(\rTimeoutCnt[16]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[16]_i_4 + (.I0(rTimeoutCnt_reg[17]), + .O(\rTimeoutCnt[16]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[16]_i_5 + (.I0(rTimeoutCnt_reg[16]), + .O(\rTimeoutCnt[16]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[20]_i_2 + (.I0(rTimeoutCnt_reg[23]), + .O(\rTimeoutCnt[20]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[20]_i_3 + (.I0(rTimeoutCnt_reg[22]), + .O(\rTimeoutCnt[20]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[20]_i_4 + (.I0(rTimeoutCnt_reg[21]), + .O(\rTimeoutCnt[20]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[20]_i_5 + (.I0(rTimeoutCnt_reg[20]), + .O(\rTimeoutCnt[20]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[4]_i_2 + (.I0(rTimeoutCnt_reg[7]), + .O(\rTimeoutCnt[4]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[4]_i_3 + (.I0(rTimeoutCnt_reg[6]), + .O(\rTimeoutCnt[4]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[4]_i_4 + (.I0(rTimeoutCnt_reg[5]), + .O(\rTimeoutCnt[4]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[4]_i_5 + (.I0(rTimeoutCnt_reg[4]), + .O(\rTimeoutCnt[4]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[8]_i_2 + (.I0(rTimeoutCnt_reg[11]), + .O(\rTimeoutCnt[8]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[8]_i_3 + (.I0(rTimeoutCnt_reg[10]), + .O(\rTimeoutCnt[8]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[8]_i_4 + (.I0(rTimeoutCnt_reg[9]), + .O(\rTimeoutCnt[8]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \rTimeoutCnt[8]_i_5 + (.I0(rTimeoutCnt_reg[8]), + .O(\rTimeoutCnt[8]_i_5_n_0 )); + FDRE \rTimeoutCnt_reg[0] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1_n_0 ), + .D(\rTimeoutCnt_reg[0]_i_2_n_7 ), + .Q(rTimeoutCnt_reg[0]), + .R(rTimeoutRst)); + CARRY4 \rTimeoutCnt_reg[0]_i_2 + (.CI(1'b0), + .CO({\rTimeoutCnt_reg[0]_i_2_n_0 ,\rTimeoutCnt_reg[0]_i_2_n_1 ,\rTimeoutCnt_reg[0]_i_2_n_2 ,\rTimeoutCnt_reg[0]_i_2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\rTimeoutCnt_reg[0]_i_2_n_4 ,\rTimeoutCnt_reg[0]_i_2_n_5 ,\rTimeoutCnt_reg[0]_i_2_n_6 ,\rTimeoutCnt_reg[0]_i_2_n_7 }), + .S({\rTimeoutCnt[0]_i_3_n_0 ,\rTimeoutCnt[0]_i_4_n_0 ,\rTimeoutCnt[0]_i_5_n_0 ,\rTimeoutCnt[0]_i_6_n_0 })); + FDRE \rTimeoutCnt_reg[10] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1_n_0 ), + .D(\rTimeoutCnt_reg[8]_i_1_n_5 ), + .Q(rTimeoutCnt_reg[10]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[11] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1_n_0 ), + .D(\rTimeoutCnt_reg[8]_i_1_n_4 ), + .Q(rTimeoutCnt_reg[11]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[12] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1_n_0 ), + .D(\rTimeoutCnt_reg[12]_i_1_n_7 ), + .Q(rTimeoutCnt_reg[12]), + .R(rTimeoutRst)); + CARRY4 \rTimeoutCnt_reg[12]_i_1 + (.CI(\rTimeoutCnt_reg[8]_i_1_n_0 ), + .CO({\rTimeoutCnt_reg[12]_i_1_n_0 ,\rTimeoutCnt_reg[12]_i_1_n_1 ,\rTimeoutCnt_reg[12]_i_1_n_2 ,\rTimeoutCnt_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\rTimeoutCnt_reg[12]_i_1_n_4 ,\rTimeoutCnt_reg[12]_i_1_n_5 ,\rTimeoutCnt_reg[12]_i_1_n_6 ,\rTimeoutCnt_reg[12]_i_1_n_7 }), + .S({\rTimeoutCnt[12]_i_2_n_0 ,\rTimeoutCnt[12]_i_3_n_0 ,\rTimeoutCnt[12]_i_4_n_0 ,\rTimeoutCnt[12]_i_5_n_0 })); + FDRE \rTimeoutCnt_reg[13] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1_n_0 ), + .D(\rTimeoutCnt_reg[12]_i_1_n_6 ), + .Q(rTimeoutCnt_reg[13]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[14] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1_n_0 ), + .D(\rTimeoutCnt_reg[12]_i_1_n_5 ), + .Q(rTimeoutCnt_reg[14]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[15] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1_n_0 ), + .D(\rTimeoutCnt_reg[12]_i_1_n_4 ), + .Q(rTimeoutCnt_reg[15]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[16] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1_n_0 ), + .D(\rTimeoutCnt_reg[16]_i_1_n_7 ), + .Q(rTimeoutCnt_reg[16]), + .R(rTimeoutRst)); + CARRY4 \rTimeoutCnt_reg[16]_i_1 + (.CI(\rTimeoutCnt_reg[12]_i_1_n_0 ), + .CO({\rTimeoutCnt_reg[16]_i_1_n_0 ,\rTimeoutCnt_reg[16]_i_1_n_1 ,\rTimeoutCnt_reg[16]_i_1_n_2 ,\rTimeoutCnt_reg[16]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\rTimeoutCnt_reg[16]_i_1_n_4 ,\rTimeoutCnt_reg[16]_i_1_n_5 ,\rTimeoutCnt_reg[16]_i_1_n_6 ,\rTimeoutCnt_reg[16]_i_1_n_7 }), + .S({\rTimeoutCnt[16]_i_2_n_0 ,\rTimeoutCnt[16]_i_3_n_0 ,\rTimeoutCnt[16]_i_4_n_0 ,\rTimeoutCnt[16]_i_5_n_0 })); + FDRE \rTimeoutCnt_reg[17] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1_n_0 ), + .D(\rTimeoutCnt_reg[16]_i_1_n_6 ), + .Q(rTimeoutCnt_reg[17]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[18] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1_n_0 ), + .D(\rTimeoutCnt_reg[16]_i_1_n_5 ), + .Q(rTimeoutCnt_reg[18]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[19] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1_n_0 ), + .D(\rTimeoutCnt_reg[16]_i_1_n_4 ), + .Q(rTimeoutCnt_reg[19]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[1] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1_n_0 ), + .D(\rTimeoutCnt_reg[0]_i_2_n_6 ), + .Q(rTimeoutCnt_reg[1]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[20] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1_n_0 ), + .D(\rTimeoutCnt_reg[20]_i_1_n_7 ), + .Q(rTimeoutCnt_reg[20]), + .R(rTimeoutRst)); + CARRY4 \rTimeoutCnt_reg[20]_i_1 + (.CI(\rTimeoutCnt_reg[16]_i_1_n_0 ), + .CO({\NLW_rTimeoutCnt_reg[20]_i_1_CO_UNCONNECTED [3],\rTimeoutCnt_reg[20]_i_1_n_1 ,\rTimeoutCnt_reg[20]_i_1_n_2 ,\rTimeoutCnt_reg[20]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\rTimeoutCnt_reg[20]_i_1_n_4 ,\rTimeoutCnt_reg[20]_i_1_n_5 ,\rTimeoutCnt_reg[20]_i_1_n_6 ,\rTimeoutCnt_reg[20]_i_1_n_7 }), + .S({\rTimeoutCnt[20]_i_2_n_0 ,\rTimeoutCnt[20]_i_3_n_0 ,\rTimeoutCnt[20]_i_4_n_0 ,\rTimeoutCnt[20]_i_5_n_0 })); + FDRE \rTimeoutCnt_reg[21] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1_n_0 ), + .D(\rTimeoutCnt_reg[20]_i_1_n_6 ), + .Q(rTimeoutCnt_reg[21]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[22] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1_n_0 ), + .D(\rTimeoutCnt_reg[20]_i_1_n_5 ), + .Q(rTimeoutCnt_reg[22]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[23] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1_n_0 ), + .D(\rTimeoutCnt_reg[20]_i_1_n_4 ), + .Q(rTimeoutCnt_reg[23]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[2] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1_n_0 ), + .D(\rTimeoutCnt_reg[0]_i_2_n_5 ), + .Q(rTimeoutCnt_reg[2]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[3] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1_n_0 ), + .D(\rTimeoutCnt_reg[0]_i_2_n_4 ), + .Q(rTimeoutCnt_reg[3]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[4] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1_n_0 ), + .D(\rTimeoutCnt_reg[4]_i_1_n_7 ), + .Q(rTimeoutCnt_reg[4]), + .R(rTimeoutRst)); + CARRY4 \rTimeoutCnt_reg[4]_i_1 + (.CI(\rTimeoutCnt_reg[0]_i_2_n_0 ), + .CO({\rTimeoutCnt_reg[4]_i_1_n_0 ,\rTimeoutCnt_reg[4]_i_1_n_1 ,\rTimeoutCnt_reg[4]_i_1_n_2 ,\rTimeoutCnt_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\rTimeoutCnt_reg[4]_i_1_n_4 ,\rTimeoutCnt_reg[4]_i_1_n_5 ,\rTimeoutCnt_reg[4]_i_1_n_6 ,\rTimeoutCnt_reg[4]_i_1_n_7 }), + .S({\rTimeoutCnt[4]_i_2_n_0 ,\rTimeoutCnt[4]_i_3_n_0 ,\rTimeoutCnt[4]_i_4_n_0 ,\rTimeoutCnt[4]_i_5_n_0 })); + FDRE \rTimeoutCnt_reg[5] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1_n_0 ), + .D(\rTimeoutCnt_reg[4]_i_1_n_6 ), + .Q(rTimeoutCnt_reg[5]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[6] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1_n_0 ), + .D(\rTimeoutCnt_reg[4]_i_1_n_5 ), + .Q(rTimeoutCnt_reg[6]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[7] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1_n_0 ), + .D(\rTimeoutCnt_reg[4]_i_1_n_4 ), + .Q(rTimeoutCnt_reg[7]), + .R(rTimeoutRst)); + FDRE \rTimeoutCnt_reg[8] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1_n_0 ), + .D(\rTimeoutCnt_reg[8]_i_1_n_7 ), + .Q(rTimeoutCnt_reg[8]), + .R(rTimeoutRst)); + CARRY4 \rTimeoutCnt_reg[8]_i_1 + (.CI(\rTimeoutCnt_reg[4]_i_1_n_0 ), + .CO({\rTimeoutCnt_reg[8]_i_1_n_0 ,\rTimeoutCnt_reg[8]_i_1_n_1 ,\rTimeoutCnt_reg[8]_i_1_n_2 ,\rTimeoutCnt_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\rTimeoutCnt_reg[8]_i_1_n_4 ,\rTimeoutCnt_reg[8]_i_1_n_5 ,\rTimeoutCnt_reg[8]_i_1_n_6 ,\rTimeoutCnt_reg[8]_i_1_n_7 }), + .S({\rTimeoutCnt[8]_i_2_n_0 ,\rTimeoutCnt[8]_i_3_n_0 ,\rTimeoutCnt[8]_i_4_n_0 ,\rTimeoutCnt[8]_i_5_n_0 })); + FDRE \rTimeoutCnt_reg[9] + (.C(RefClk), + .CE(\rTimeoutCnt[0]_i_1_n_0 ), + .D(\rTimeoutCnt_reg[8]_i_1_n_6 ), + .Q(rTimeoutCnt_reg[9]), + .R(rTimeoutRst)); +endmodule + +(* ORIG_REF_NAME = "TWI_SlaveCtl" *) +module Arty_Z7_20_dvi2rgb_0_0_TWI_SlaveCtl + (sI2C_End, + sI2C_Done, + rd_wrn_reg_0, + DDC_SDA_T, + E, + D, + RefClk, + Q, + sState, + \sAddr_reg[6] , + \sState_reg[0] , + \sAddr_reg[3] , + \sAddr_reg[4] , + DDC_SDA_I, + DDC_SCL_I); + output sI2C_End; + output sI2C_Done; + output rd_wrn_reg_0; + output DDC_SDA_T; + output [0:0]E; + output [6:0]D; + input RefClk; + input [7:0]Q; + input [1:0]sState; + input [6:0]\sAddr_reg[6] ; + input \sState_reg[0] ; + input \sAddr_reg[3] ; + input \sAddr_reg[4] ; + input DDC_SDA_I; + input DDC_SCL_I; + + wire [6:0]D; + wire DDC_SCL_I; + wire DDC_SDA_I; + wire DDC_SDA_T; + wire DONE_O_i_2_n_0; + wire DONE_O_i_4_n_0; + wire [0:0]E; + wire END_O_i_2_n_0; + wire \FSM_gray_state[0]_i_1_n_0 ; + wire \FSM_gray_state[0]_i_2_n_0 ; + wire \FSM_gray_state[0]_i_3_n_0 ; + wire \FSM_gray_state[0]_i_4_n_0 ; + wire \FSM_gray_state[0]_i_5_n_0 ; + wire \FSM_gray_state[1]_i_1_n_0 ; + wire \FSM_gray_state[1]_i_2_n_0 ; + wire \FSM_gray_state[1]_i_3_n_0 ; + wire \FSM_gray_state[1]_i_4_n_0 ; + wire \FSM_gray_state[1]_i_5_n_0 ; + wire \FSM_gray_state[1]_i_7_n_0 ; + wire \FSM_gray_state[1]_i_9_n_0 ; + wire \FSM_gray_state[2]_i_1_n_0 ; + wire \FSM_gray_state[2]_i_2_n_0 ; + wire \FSM_gray_state[2]_i_3_n_0 ; + wire \FSM_gray_state[2]_i_4_n_0 ; + wire \FSM_gray_state[2]_i_5_n_0 ; + wire \FSM_gray_state[2]_i_6_n_0 ; + wire \FSM_gray_state[2]_i_7_n_0 ; + wire GlitchF_SCL_n_0; + wire GlitchF_SCL_n_1; + wire [7:0]Q; + wire RefClk; + wire SyncSCL_n_1; + wire SyncSDA_n_1; + wire \bitCount[0]_i_1_n_0 ; + wire \bitCount[1]_i_1_n_0 ; + wire \bitCount[2]_i_1_n_0 ; + wire \bitCount[2]_i_2_n_0 ; + wire bitCount__1; + wire \bitCount_reg_n_0_[0] ; + wire \bitCount_reg_n_0_[1] ; + wire \bitCount_reg_n_0_[2] ; + wire dScl; + wire dSda; + wire \dataByte[0]_i_1_n_0 ; + wire \dataByte[0]_i_2_n_0 ; + wire \dataByte[1]_i_1_n_0 ; + wire \dataByte[2]_i_1_n_0 ; + wire \dataByte[3]_i_1_n_0 ; + wire \dataByte[4]_i_1_n_0 ; + wire \dataByte[5]_i_1_n_0 ; + wire \dataByte[6]_i_1_n_0 ; + wire \dataByte[7]_i_1_n_0 ; + wire \dataByte[7]_i_2_n_0 ; + wire \dataByte[7]_i_4_n_0 ; + wire \dataByte[7]_i_5_n_0 ; + wire \dataByte[7]_i_6_n_0 ; + wire \dataByte_reg_n_0_[0] ; + wire \dataByte_reg_n_0_[1] ; + wire \dataByte_reg_n_0_[2] ; + wire \dataByte_reg_n_0_[3] ; + wire \dataByte_reg_n_0_[4] ; + wire \dataByte_reg_n_0_[5] ; + wire \dataByte_reg_n_0_[6] ; + wire \dataByte_reg_n_0_[7] ; + wire ddScl; + wire ddSda; + wire fStart; + wire fStop; + wire iDone; + wire iEnd; + wire p_0_in_0; + wire p_15_in; + wire p_2_in; + wire rd_wrn0; + wire rd_wrn_i_1_n_0; + wire rd_wrn_i_2_n_0; + wire rd_wrn_reg_0; + wire \sAddr_reg[3] ; + wire \sAddr_reg[4] ; + wire [6:0]\sAddr_reg[6] ; + wire sI2C_Done; + wire sI2C_End; + wire sI2C_Stb; + wire sIn_q; + wire sOut; + wire sScl; + wire sSda; + wire [1:0]sState; + wire \sState_reg[0] ; + (* RTL_KEEP = "yes" *) wire [2:0]state; + + LUT4 #( + .INIT(16'hFB7B)) + DDC_SDA_T_INST_0 + (.I0(state[0]), + .I1(state[1]), + .I2(state[2]), + .I3(\dataByte_reg_n_0_[7] ), + .O(DDC_SDA_T)); + LUT6 #( + .INIT(64'hAAAAAAAAAAAAAAEA)) + DONE_O_i_1 + (.I0(DONE_O_i_2_n_0), + .I1(rd_wrn0), + .I2(DONE_O_i_4_n_0), + .I3(\dataByte_reg_n_0_[0] ), + .I4(\dataByte_reg_n_0_[1] ), + .I5(\dataByte_reg_n_0_[2] ), + .O(iDone)); + LUT6 #( + .INIT(64'h2000000008000000)) + DONE_O_i_2 + (.I0(bitCount__1), + .I1(dScl), + .I2(ddScl), + .I3(state[1]), + .I4(state[2]), + .I5(state[0]), + .O(DONE_O_i_2_n_0)); + LUT4 #( + .INIT(16'h0200)) + DONE_O_i_3 + (.I0(rd_wrn_i_2_n_0), + .I1(state[1]), + .I2(state[2]), + .I3(state[0]), + .O(rd_wrn0)); + (* SOFT_HLUTNM = "soft_lutpair89" *) + LUT4 #( + .INIT(16'h0400)) + DONE_O_i_4 + (.I0(\dataByte_reg_n_0_[5] ), + .I1(\dataByte_reg_n_0_[6] ), + .I2(\dataByte_reg_n_0_[3] ), + .I3(\dataByte_reg_n_0_[4] ), + .O(DONE_O_i_4_n_0)); + FDRE DONE_O_reg + (.C(RefClk), + .CE(1'b1), + .D(iDone), + .Q(sI2C_Done), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair87" *) + LUT5 #( + .INIT(32'h4F00F000)) + END_O_i_1 + (.I0(ddScl), + .I1(END_O_i_2_n_0), + .I2(ddSda), + .I3(dScl), + .I4(dSda), + .O(iEnd)); + LUT3 #( + .INIT(8'h04)) + END_O_i_2 + (.I0(state[1]), + .I1(state[2]), + .I2(state[0]), + .O(END_O_i_2_n_0)); + FDRE END_O_reg + (.C(RefClk), + .CE(1'b1), + .D(iEnd), + .Q(sI2C_End), + .R(1'b0)); + LUT6 #( + .INIT(64'h2222222F22222220)) + \FSM_gray_state[0]_i_1 + (.I0(\FSM_gray_state[0]_i_2_n_0 ), + .I1(\FSM_gray_state[0]_i_3_n_0 ), + .I2(\FSM_gray_state[2]_i_3_n_0 ), + .I3(\FSM_gray_state[1]_i_4_n_0 ), + .I4(\FSM_gray_state[2]_i_6_n_0 ), + .I5(state[0]), + .O(\FSM_gray_state[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFD01FDFFFFFFFDFF)) + \FSM_gray_state[0]_i_2 + (.I0(state[2]), + .I1(state[0]), + .I2(state[1]), + .I3(ddSda), + .I4(dScl), + .I5(dSda), + .O(\FSM_gray_state[0]_i_2_n_0 )); + LUT6 #( + .INIT(64'h000000FB00FF00FB)) + \FSM_gray_state[0]_i_3 + (.I0(\FSM_gray_state[1]_i_5_n_0 ), + .I1(\FSM_gray_state[0]_i_4_n_0 ), + .I2(state[2]), + .I3(\FSM_gray_state[0]_i_5_n_0 ), + .I4(state[1]), + .I5(fStart), + .O(\FSM_gray_state[0]_i_3_n_0 )); + LUT3 #( + .INIT(8'h01)) + \FSM_gray_state[0]_i_4 + (.I0(\dataByte_reg_n_0_[1] ), + .I1(\dataByte_reg_n_0_[0] ), + .I2(\dataByte_reg_n_0_[2] ), + .O(\FSM_gray_state[0]_i_4_n_0 )); + LUT4 #( + .INIT(16'h5545)) + \FSM_gray_state[0]_i_5 + (.I0(state[0]), + .I1(state[2]), + .I2(state[1]), + .I3(rd_wrn_reg_0), + .O(\FSM_gray_state[0]_i_5_n_0 )); + LUT6 #( + .INIT(64'h2222222F22222220)) + \FSM_gray_state[1]_i_1 + (.I0(\FSM_gray_state[1]_i_2_n_0 ), + .I1(\FSM_gray_state[1]_i_3_n_0 ), + .I2(\FSM_gray_state[2]_i_3_n_0 ), + .I3(\FSM_gray_state[1]_i_4_n_0 ), + .I4(\FSM_gray_state[2]_i_6_n_0 ), + .I5(state[1]), + .O(\FSM_gray_state[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair90" *) + LUT3 #( + .INIT(8'h40)) + \FSM_gray_state[1]_i_10 + (.I0(ddSda), + .I1(dScl), + .I2(dSda), + .O(fStop)); + LUT6 #( + .INIT(64'hEEEEEEEEEEEEEEEF)) + \FSM_gray_state[1]_i_2 + (.I0(state[2]), + .I1(state[1]), + .I2(\dataByte_reg_n_0_[1] ), + .I3(\dataByte_reg_n_0_[0] ), + .I4(\dataByte_reg_n_0_[2] ), + .I5(\FSM_gray_state[1]_i_5_n_0 ), + .O(\FSM_gray_state[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFAFBFAFFFAF0FFF)) + \FSM_gray_state[1]_i_3 + (.I0(fStart), + .I1(sI2C_Stb), + .I2(\FSM_gray_state[1]_i_7_n_0 ), + .I3(state[0]), + .I4(state[2]), + .I5(state[1]), + .O(\FSM_gray_state[1]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFAFAF8F8FAFAF888)) + \FSM_gray_state[1]_i_4 + (.I0(p_0_in_0), + .I1(rd_wrn_i_2_n_0), + .I2(p_2_in), + .I3(\FSM_gray_state[1]_i_9_n_0 ), + .I4(fStop), + .I5(fStart), + .O(\FSM_gray_state[1]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair89" *) + LUT4 #( + .INIT(16'hFFDF)) + \FSM_gray_state[1]_i_5 + (.I0(\dataByte_reg_n_0_[6] ), + .I1(\dataByte_reg_n_0_[5] ), + .I2(\dataByte_reg_n_0_[4] ), + .I3(\dataByte_reg_n_0_[3] ), + .O(\FSM_gray_state[1]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair85" *) + LUT2 #( + .INIT(4'hE)) + \FSM_gray_state[1]_i_6 + (.I0(sState[1]), + .I1(sState[0]), + .O(sI2C_Stb)); + LUT5 #( + .INIT(32'hF7F7F747)) + \FSM_gray_state[1]_i_7 + (.I0(dSda), + .I1(dScl), + .I2(ddSda), + .I3(state[1]), + .I4(state[0]), + .O(\FSM_gray_state[1]_i_7_n_0 )); + LUT3 #( + .INIT(8'h02)) + \FSM_gray_state[1]_i_8 + (.I0(state[0]), + .I1(state[2]), + .I2(state[1]), + .O(p_0_in_0)); + (* SOFT_HLUTNM = "soft_lutpair86" *) + LUT5 #( + .INIT(32'h00010000)) + \FSM_gray_state[1]_i_9 + (.I0(\bitCount_reg_n_0_[2] ), + .I1(\bitCount_reg_n_0_[1] ), + .I2(\bitCount_reg_n_0_[0] ), + .I3(dScl), + .I4(ddScl), + .O(\FSM_gray_state[1]_i_9_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAABAAAAAAA8)) + \FSM_gray_state[2]_i_1 + (.I0(\FSM_gray_state[2]_i_2_n_0 ), + .I1(\FSM_gray_state[2]_i_3_n_0 ), + .I2(\FSM_gray_state[2]_i_4_n_0 ), + .I3(\FSM_gray_state[2]_i_5_n_0 ), + .I4(\FSM_gray_state[2]_i_6_n_0 ), + .I5(state[2]), + .O(\FSM_gray_state[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hB70000000007B700)) + \FSM_gray_state[2]_i_2 + (.I0(dSda), + .I1(dScl), + .I2(ddSda), + .I3(state[1]), + .I4(state[2]), + .I5(state[0]), + .O(\FSM_gray_state[2]_i_2_n_0 )); + LUT6 #( + .INIT(64'h0000F20000F2F200)) + \FSM_gray_state[2]_i_3 + (.I0(ddScl), + .I1(dScl), + .I2(\FSM_gray_state[2]_i_7_n_0 ), + .I3(state[1]), + .I4(state[2]), + .I5(state[0]), + .O(\FSM_gray_state[2]_i_3_n_0 )); + LUT6 #( + .INIT(64'h0000FF4000000000)) + \FSM_gray_state[2]_i_4 + (.I0(ddSda), + .I1(dScl), + .I2(dSda), + .I3(rd_wrn_i_2_n_0), + .I4(\dataByte[7]_i_6_n_0 ), + .I5(state[0]), + .O(\FSM_gray_state[2]_i_4_n_0 )); + LUT6 #( + .INIT(64'h7B48484800000000)) + \FSM_gray_state[2]_i_5 + (.I0(dSda), + .I1(dScl), + .I2(ddSda), + .I3(bitCount__1), + .I4(ddScl), + .I5(p_2_in), + .O(\FSM_gray_state[2]_i_5_n_0 )); + LUT6 #( + .INIT(64'h00C200C200C20002)) + \FSM_gray_state[2]_i_6 + (.I0(fStart), + .I1(state[1]), + .I2(state[2]), + .I3(state[0]), + .I4(rd_wrn_i_2_n_0), + .I5(\FSM_gray_state[2]_i_7_n_0 ), + .O(\FSM_gray_state[2]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair90" *) + LUT3 #( + .INIT(8'h48)) + \FSM_gray_state[2]_i_7 + (.I0(dSda), + .I1(dScl), + .I2(ddSda), + .O(\FSM_gray_state[2]_i_7_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair91" *) + LUT3 #( + .INIT(8'h01)) + \FSM_gray_state[2]_i_8 + (.I0(\bitCount_reg_n_0_[0] ), + .I1(\bitCount_reg_n_0_[1] ), + .I2(\bitCount_reg_n_0_[2] ), + .O(bitCount__1)); + LUT3 #( + .INIT(8'h80)) + \FSM_gray_state[2]_i_9 + (.I0(state[0]), + .I1(state[2]), + .I2(state[1]), + .O(p_2_in)); + (* KEEP = "yes" *) + FDRE \FSM_gray_state_reg[0] + (.C(RefClk), + .CE(1'b1), + .D(\FSM_gray_state[0]_i_1_n_0 ), + .Q(state[0]), + .R(1'b0)); + (* KEEP = "yes" *) + FDRE \FSM_gray_state_reg[1] + (.C(RefClk), + .CE(1'b1), + .D(\FSM_gray_state[1]_i_1_n_0 ), + .Q(state[1]), + .R(1'b0)); + (* KEEP = "yes" *) + FDRE \FSM_gray_state_reg[2] + (.C(RefClk), + .CE(1'b1), + .D(\FSM_gray_state[2]_i_1_n_0 ), + .Q(state[2]), + .R(1'b0)); + Arty_Z7_20_dvi2rgb_0_0_GlitchFilter GlitchF_SCL + (.\Filter.sOut_reg_0 (GlitchF_SCL_n_0), + .RefClk(RefClk), + .SS(SyncSCL_n_1), + .dScl_reg(GlitchF_SCL_n_1), + .out(sScl)); + Arty_Z7_20_dvi2rgb_0_0_GlitchFilter_6 GlitchF_SDA + (.RefClk(RefClk), + .SS(SyncSDA_n_1), + .out(sSda), + .sIn_q(sIn_q), + .sOut(sOut)); + Arty_Z7_20_dvi2rgb_0_0_SyncAsync_7 SyncSCL + (.DDC_SCL_I(DDC_SCL_I), + .\Filter.sIn_q_reg (GlitchF_SCL_n_0), + .RefClk(RefClk), + .SS(SyncSCL_n_1), + .out(sScl)); + Arty_Z7_20_dvi2rgb_0_0_SyncAsync_8 SyncSDA + (.DDC_SDA_I(DDC_SDA_I), + .RefClk(RefClk), + .SS(SyncSDA_n_1), + .out(sSda), + .sIn_q(sIn_q)); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF666F)) + \bitCount[0]_i_1 + (.I0(\bitCount_reg_n_0_[0] ), + .I1(\dataByte[7]_i_5_n_0 ), + .I2(\dataByte[7]_i_6_n_0 ), + .I3(state[0]), + .I4(fStart), + .I5(\dataByte[7]_i_4_n_0 ), + .O(\bitCount[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFA6)) + \bitCount[1]_i_1 + (.I0(\bitCount_reg_n_0_[1] ), + .I1(\dataByte[7]_i_5_n_0 ), + .I2(\bitCount_reg_n_0_[0] ), + .I3(\dataByte[0]_i_2_n_0 ), + .I4(fStart), + .I5(\dataByte[7]_i_4_n_0 ), + .O(\bitCount[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFA6)) + \bitCount[2]_i_1 + (.I0(\bitCount_reg_n_0_[2] ), + .I1(\dataByte[7]_i_5_n_0 ), + .I2(\bitCount[2]_i_2_n_0 ), + .I3(\dataByte[0]_i_2_n_0 ), + .I4(fStart), + .I5(\dataByte[7]_i_4_n_0 ), + .O(\bitCount[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair91" *) + LUT2 #( + .INIT(4'hE)) + \bitCount[2]_i_2 + (.I0(\bitCount_reg_n_0_[1] ), + .I1(\bitCount_reg_n_0_[0] ), + .O(\bitCount[2]_i_2_n_0 )); + FDRE #( + .INIT(1'b1)) + \bitCount_reg[0] + (.C(RefClk), + .CE(1'b1), + .D(\bitCount[0]_i_1_n_0 ), + .Q(\bitCount_reg_n_0_[0] ), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + \bitCount_reg[1] + (.C(RefClk), + .CE(1'b1), + .D(\bitCount[1]_i_1_n_0 ), + .Q(\bitCount_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b1)) + \bitCount_reg[2] + (.C(RefClk), + .CE(1'b1), + .D(\bitCount[2]_i_1_n_0 ), + .Q(\bitCount_reg_n_0_[2] ), + .R(1'b0)); + FDRE dScl_reg + (.C(RefClk), + .CE(1'b1), + .D(GlitchF_SCL_n_1), + .Q(dScl), + .R(1'b0)); + FDRE dSda_reg + (.C(RefClk), + .CE(1'b1), + .D(sOut), + .Q(dSda), + .R(1'b0)); + LUT6 #( + .INIT(64'hAAAAAAAABBBBA888)) + \dataByte[0]_i_1 + (.I0(Q[0]), + .I1(\dataByte[7]_i_4_n_0 ), + .I2(dScl), + .I3(ddSda), + .I4(dSda), + .I5(\dataByte[0]_i_2_n_0 ), + .O(\dataByte[0]_i_1_n_0 )); + LUT3 #( + .INIT(8'h01)) + \dataByte[0]_i_2 + (.I0(state[0]), + .I1(state[2]), + .I2(state[1]), + .O(\dataByte[0]_i_2_n_0 )); + LUT6 #( + .INIT(64'hABABABAAA8A8A8AA)) + \dataByte[1]_i_1 + (.I0(Q[1]), + .I1(\dataByte[7]_i_4_n_0 ), + .I2(fStart), + .I3(state[0]), + .I4(\dataByte[7]_i_6_n_0 ), + .I5(\dataByte_reg_n_0_[0] ), + .O(\dataByte[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'hABABABAAA8A8A8AA)) + \dataByte[2]_i_1 + (.I0(Q[2]), + .I1(\dataByte[7]_i_4_n_0 ), + .I2(fStart), + .I3(state[0]), + .I4(\dataByte[7]_i_6_n_0 ), + .I5(\dataByte_reg_n_0_[1] ), + .O(\dataByte[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hABABABAAA8A8A8AA)) + \dataByte[3]_i_1 + (.I0(Q[3]), + .I1(\dataByte[7]_i_4_n_0 ), + .I2(fStart), + .I3(state[0]), + .I4(\dataByte[7]_i_6_n_0 ), + .I5(\dataByte_reg_n_0_[2] ), + .O(\dataByte[3]_i_1_n_0 )); + LUT6 #( + .INIT(64'hABABABAAA8A8A8AA)) + \dataByte[4]_i_1 + (.I0(Q[4]), + .I1(\dataByte[7]_i_4_n_0 ), + .I2(fStart), + .I3(state[0]), + .I4(\dataByte[7]_i_6_n_0 ), + .I5(\dataByte_reg_n_0_[3] ), + .O(\dataByte[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'hABABABAAA8A8A8AA)) + \dataByte[5]_i_1 + (.I0(Q[5]), + .I1(\dataByte[7]_i_4_n_0 ), + .I2(fStart), + .I3(state[0]), + .I4(\dataByte[7]_i_6_n_0 ), + .I5(\dataByte_reg_n_0_[4] ), + .O(\dataByte[5]_i_1_n_0 )); + LUT6 #( + .INIT(64'hABABABAAA8A8A8AA)) + \dataByte[6]_i_1 + (.I0(Q[6]), + .I1(\dataByte[7]_i_4_n_0 ), + .I2(fStart), + .I3(state[0]), + .I4(\dataByte[7]_i_6_n_0 ), + .I5(\dataByte_reg_n_0_[5] ), + .O(\dataByte[6]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFF01)) + \dataByte[7]_i_1 + (.I0(state[1]), + .I1(state[2]), + .I2(state[0]), + .I3(fStart), + .I4(\dataByte[7]_i_4_n_0 ), + .I5(\dataByte[7]_i_5_n_0 ), + .O(\dataByte[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hABABABAAA8A8A8AA)) + \dataByte[7]_i_2 + (.I0(Q[7]), + .I1(\dataByte[7]_i_4_n_0 ), + .I2(fStart), + .I3(state[0]), + .I4(\dataByte[7]_i_6_n_0 ), + .I5(\dataByte_reg_n_0_[6] ), + .O(\dataByte[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair87" *) + LUT3 #( + .INIT(8'h08)) + \dataByte[7]_i_3 + (.I0(dScl), + .I1(ddSda), + .I2(dSda), + .O(fStart)); + LUT6 #( + .INIT(64'h0000000000C04400)) + \dataByte[7]_i_4 + (.I0(ddSda), + .I1(p_15_in), + .I2(rd_wrn_reg_0), + .I3(state[2]), + .I4(state[1]), + .I5(state[0]), + .O(\dataByte[7]_i_4_n_0 )); + LUT5 #( + .INIT(32'h00804200)) + \dataByte[7]_i_5 + (.I0(state[0]), + .I1(state[2]), + .I2(state[1]), + .I3(dScl), + .I4(ddScl), + .O(\dataByte[7]_i_5_n_0 )); + LUT2 #( + .INIT(4'hE)) + \dataByte[7]_i_6 + (.I0(state[1]), + .I1(state[2]), + .O(\dataByte[7]_i_6_n_0 )); + LUT2 #( + .INIT(4'h2)) + \dataByte[7]_i_7 + (.I0(ddScl), + .I1(dScl), + .O(p_15_in)); + FDRE \dataByte_reg[0] + (.C(RefClk), + .CE(\dataByte[7]_i_1_n_0 ), + .D(\dataByte[0]_i_1_n_0 ), + .Q(\dataByte_reg_n_0_[0] ), + .R(1'b0)); + FDRE \dataByte_reg[1] + (.C(RefClk), + .CE(\dataByte[7]_i_1_n_0 ), + .D(\dataByte[1]_i_1_n_0 ), + .Q(\dataByte_reg_n_0_[1] ), + .R(1'b0)); + FDRE \dataByte_reg[2] + (.C(RefClk), + .CE(\dataByte[7]_i_1_n_0 ), + .D(\dataByte[2]_i_1_n_0 ), + .Q(\dataByte_reg_n_0_[2] ), + .R(1'b0)); + FDRE \dataByte_reg[3] + (.C(RefClk), + .CE(\dataByte[7]_i_1_n_0 ), + .D(\dataByte[3]_i_1_n_0 ), + .Q(\dataByte_reg_n_0_[3] ), + .R(1'b0)); + FDRE \dataByte_reg[4] + (.C(RefClk), + .CE(\dataByte[7]_i_1_n_0 ), + .D(\dataByte[4]_i_1_n_0 ), + .Q(\dataByte_reg_n_0_[4] ), + .R(1'b0)); + FDRE \dataByte_reg[5] + (.C(RefClk), + .CE(\dataByte[7]_i_1_n_0 ), + .D(\dataByte[5]_i_1_n_0 ), + .Q(\dataByte_reg_n_0_[5] ), + .R(1'b0)); + FDRE \dataByte_reg[6] + (.C(RefClk), + .CE(\dataByte[7]_i_1_n_0 ), + .D(\dataByte[6]_i_1_n_0 ), + .Q(\dataByte_reg_n_0_[6] ), + .R(1'b0)); + FDRE \dataByte_reg[7] + (.C(RefClk), + .CE(\dataByte[7]_i_1_n_0 ), + .D(\dataByte[7]_i_2_n_0 ), + .Q(\dataByte_reg_n_0_[7] ), + .R(1'b0)); + FDRE ddScl_reg + (.C(RefClk), + .CE(1'b1), + .D(dScl), + .Q(ddScl), + .R(1'b0)); + FDRE ddSda_reg + (.C(RefClk), + .CE(1'b1), + .D(dSda), + .Q(ddSda), + .R(1'b0)); + LUT6 #( + .INIT(64'hFFFBFFFF00080000)) + rd_wrn_i_1 + (.I0(dSda), + .I1(rd_wrn_i_2_n_0), + .I2(state[1]), + .I3(state[2]), + .I4(state[0]), + .I5(rd_wrn_reg_0), + .O(rd_wrn_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair86" *) + LUT5 #( + .INIT(32'h00010000)) + rd_wrn_i_2 + (.I0(\bitCount_reg_n_0_[2] ), + .I1(\bitCount_reg_n_0_[1] ), + .I2(\bitCount_reg_n_0_[0] ), + .I3(ddScl), + .I4(dScl), + .O(rd_wrn_i_2_n_0)); + FDRE rd_wrn_reg + (.C(RefClk), + .CE(1'b1), + .D(rd_wrn_i_1_n_0), + .Q(rd_wrn_reg_0), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair88" *) + LUT4 #( + .INIT(16'h80BF)) + \sAddr_rep[0]_i_1 + (.I0(\dataByte_reg_n_0_[0] ), + .I1(sState[0]), + .I2(sState[1]), + .I3(\sAddr_reg[6] [0]), + .O(D[0])); + (* SOFT_HLUTNM = "soft_lutpair85" *) + LUT5 #( + .INIT(32'hF6660666)) + \sAddr_rep[1]_i_1 + (.I0(\sAddr_reg[6] [1]), + .I1(\sAddr_reg[6] [0]), + .I2(sState[0]), + .I3(sState[1]), + .I4(\dataByte_reg_n_0_[1] ), + .O(D[1])); + LUT6 #( + .INIT(64'hFF6A6A6A006A6A6A)) + \sAddr_rep[2]_i_1 + (.I0(\sAddr_reg[6] [2]), + .I1(\sAddr_reg[6] [1]), + .I2(\sAddr_reg[6] [0]), + .I3(sState[0]), + .I4(sState[1]), + .I5(\dataByte_reg_n_0_[2] ), + .O(D[2])); + LUT6 #( + .INIT(64'hFFFF6AAA00006AAA)) + \sAddr_rep[3]_i_1 + (.I0(\sAddr_reg[6] [3]), + .I1(\sAddr_reg[6] [1]), + .I2(\sAddr_reg[6] [0]), + .I3(\sAddr_reg[6] [2]), + .I4(\sState_reg[0] ), + .I5(\dataByte_reg_n_0_[3] ), + .O(D[3])); + LUT5 #( + .INIT(32'hF6660666)) + \sAddr_rep[4]_i_1 + (.I0(\sAddr_reg[6] [4]), + .I1(\sAddr_reg[3] ), + .I2(sState[0]), + .I3(sState[1]), + .I4(\dataByte_reg_n_0_[4] ), + .O(D[4])); + LUT5 #( + .INIT(32'hF6660666)) + \sAddr_rep[5]_i_1 + (.I0(\sAddr_reg[6] [5]), + .I1(\sAddr_reg[4] ), + .I2(sState[0]), + .I3(sState[1]), + .I4(\dataByte_reg_n_0_[5] ), + .O(D[5])); + (* SOFT_HLUTNM = "soft_lutpair88" *) + LUT2 #( + .INIT(4'h8)) + \sAddr_rep[6]_i_1 + (.I0(sI2C_Done), + .I1(sState[0]), + .O(E)); + LUT6 #( + .INIT(64'hFF6A6A6A006A6A6A)) + \sAddr_rep[6]_i_2 + (.I0(\sAddr_reg[6] [6]), + .I1(\sAddr_reg[4] ), + .I2(\sAddr_reg[6] [5]), + .I3(sState[0]), + .I4(sState[1]), + .I5(\dataByte_reg_n_0_[6] ), + .O(D[6])); +endmodule + +(* ORIG_REF_NAME = "dvi2rgb" *) (* kAddBUFG = "TRUE" *) (* kClkRange = "2" *) +(* kEdidFileName = "720p_edid.data" *) (* kEmulateDDC = "TRUE" *) (* kIDLY_TapValuePs = "78" *) +(* kIDLY_TapWidth = "5" *) (* kRstActiveHigh = "FALSE" *) +module Arty_Z7_20_dvi2rgb_0_0_dvi2rgb + (TMDS_Clk_p, + TMDS_Clk_n, + TMDS_Data_p, + TMDS_Data_n, + RefClk, + aRst, + aRst_n, + vid_pData, + vid_pVDE, + vid_pHSync, + vid_pVSync, + PixelClk, + SerialClk, + aPixelClkLckd, + DDC_SDA_I, + DDC_SDA_O, + DDC_SDA_T, + DDC_SCL_I, + DDC_SCL_O, + DDC_SCL_T, + pRst, + pRst_n); + input TMDS_Clk_p; + input TMDS_Clk_n; + input [2:0]TMDS_Data_p; + input [2:0]TMDS_Data_n; + input RefClk; + input aRst; + input aRst_n; + output [23:0]vid_pData; + output vid_pVDE; + output vid_pHSync; + output vid_pVSync; + output PixelClk; + output SerialClk; + output aPixelClkLckd; + input DDC_SDA_I; + output DDC_SDA_O; + output DDC_SDA_T; + input DDC_SCL_I; + output DDC_SCL_O; + output DDC_SCL_T; + input pRst; + input pRst_n; + + wire \ ; + wire \ ; + wire \ChannelBondX/pAllVldBgnFlag ; + wire DDC_SCL_I; + wire DDC_SDA_I; + wire DDC_SDA_T; + wire \DataDecoders[0].DecoderX_n_6 ; + wire \DataDecoders[1].DecoderX_n_0 ; + wire \DataDecoders[1].DecoderX_n_3 ; + wire \DataDecoders[2].DecoderX_n_3 ; + wire PixelClk; + wire PixelClk_int; + wire RefClk; + wire SerialClk; + wire TMDS_Clk_n; + wire TMDS_Clk_p; + wire TMDS_ClockingX_n_3; + wire [2:0]TMDS_Data_n; + wire [2:0]TMDS_Data_p; + wire aPixelClkLckd; + wire aRst_n; + wire pAllVld; + wire pC0; + wire pC1; + wire [7:0]pDataIn; + wire pLockLostRst; + wire pRdy_0; + wire pRdy_1; + wire pRdy_2; + wire pRst_n; + wire pVde; + wire pVld_0; + wire pVld_1; + wire pVld_2; + wire [15:0]piData; + wire [23:0]vid_pData; + wire vid_pHSync; + wire vid_pVDE; + wire vid_pVSync; + + assign DDC_SCL_O = \ ; + assign DDC_SCL_T = \ ; + assign DDC_SDA_O = \ ; + Arty_Z7_20_dvi2rgb_0_0_TMDS_Decoder \DataDecoders[0].DecoderX + (.AS(pLockLostRst), + .CLKB(SerialClk), + .PixelClk_int(PixelClk_int), + .Q(piData[15:8]), + .RefClk(RefClk), + .SR(\DataDecoders[2].DecoderX_n_3 ), + .TMDS_Data_n(TMDS_Data_n[0]), + .TMDS_Data_p(TMDS_Data_p[0]), + .pAligned_reg(\DataDecoders[1].DecoderX_n_0 ), + .pAllVld(pAllVld), + .pAllVldBgnFlag(\ChannelBondX/pAllVldBgnFlag ), + .pC0(pC0), + .pC1(pC1), + .\pDataIn_reg[7]_0 (\DataDecoders[0].DecoderX_n_6 ), + .pRdy_0(pRdy_0), + .pRdy_1(pRdy_1), + .pRdy_2(pRdy_2), + .pRst_n(pRst_n), + .pVde(pVde), + .pVld_0(pVld_0), + .pVld_1(pVld_1), + .pVld_2(pVld_2), + .\rMMCM_Reset_q_reg[0] (SerialClk)); + Arty_Z7_20_dvi2rgb_0_0_TMDS_Decoder_0 \DataDecoders[1].DecoderX + (.AS(pLockLostRst), + .CLKB(SerialClk), + .PixelClk_int(PixelClk_int), + .Q(piData[7:0]), + .RefClk(RefClk), + .SR(\DataDecoders[1].DecoderX_n_3 ), + .TMDS_Data_n(TMDS_Data_n[1]), + .TMDS_Data_p(TMDS_Data_p[1]), + .pAllVld(pAllVld), + .pAllVldBgnFlag(\ChannelBondX/pAllVldBgnFlag ), + .pMeRdy_int_reg(\DataDecoders[1].DecoderX_n_0 ), + .pMeRdy_int_reg_0(\DataDecoders[0].DecoderX_n_6 ), + .pRdy_0(pRdy_0), + .pRdy_1(pRdy_1), + .pRdy_2(pRdy_2), + .pRst_n(pRst_n), + .pVld_0(pVld_0), + .pVld_1(pVld_1), + .pVld_2(pVld_2), + .\rMMCM_Reset_q_reg[0] (SerialClk)); + Arty_Z7_20_dvi2rgb_0_0_TMDS_Decoder_1 \DataDecoders[2].DecoderX + (.CLKB(SerialClk), + .PixelClk_int(PixelClk_int), + .Q(pDataIn), + .RefClk(RefClk), + .SR(\DataDecoders[2].DecoderX_n_3 ), + .TMDS_Data_n(TMDS_Data_n[2]), + .TMDS_Data_p(TMDS_Data_p[2]), + .out(pLockLostRst), + .pAligned_reg(\DataDecoders[1].DecoderX_n_0 ), + .pAllVld(pAllVld), + .pAllVldBgnFlag(\ChannelBondX/pAllVldBgnFlag ), + .pMeRdy_int_reg(\DataDecoders[1].DecoderX_n_3 ), + .pRdy_0(pRdy_0), + .pRdy_1(pRdy_1), + .pRdy_2(pRdy_2), + .pRst_n(pRst_n), + .pVld_0(pVld_0), + .pVld_1(pVld_1), + .pVld_2(pVld_2), + .\rMMCM_Reset_q_reg[0] (SerialClk)); + GND GND + (.G(\ )); + Arty_Z7_20_dvi2rgb_0_0_ResyncToBUFG \GenerateBUFG.ResyncToBUFG_X + (.CLK(PixelClk), + .D({pDataIn,piData}), + .PixelClk_int(PixelClk_int), + .pC0(pC0), + .pC1(pC1), + .pVde(pVde), + .vid_pData(vid_pData), + .vid_pHSync(vid_pHSync), + .vid_pVDE(vid_pVDE), + .vid_pVSync(vid_pVSync)); + Arty_Z7_20_dvi2rgb_0_0_EEPROM_8b \GenerateDDC.DDC_EEPROM + (.DDC_SCL_I(DDC_SCL_I), + .DDC_SDA_I(DDC_SDA_I), + .DDC_SDA_T(DDC_SDA_T), + .RefClk(RefClk)); + Arty_Z7_20_dvi2rgb_0_0_ResetBridge LockLostReset + (.PixelClk_int(PixelClk_int), + .in0(TMDS_ClockingX_n_3), + .out(pLockLostRst)); + Arty_Z7_20_dvi2rgb_0_0_TMDS_Clocking TMDS_ClockingX + (.PixelClk_int(PixelClk_int), + .RefClk(RefClk), + .TMDS_Clk_n(TMDS_Clk_n), + .TMDS_Clk_p(TMDS_Clk_p), + .aPixelClkLckd(aPixelClkLckd), + .aRst_n(aRst_n), + .in0(TMDS_ClockingX_n_3), + .\pDataQ_reg[8] (SerialClk)); + VCC VCC + (.P(\ )); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/Arty_Z7_20_dvi2rgb_0_0_sim_netlist.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/Arty_Z7_20_dvi2rgb_0_0_sim_netlist.vhdl new file mode 100644 index 0000000..76d6808 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/Arty_Z7_20_dvi2rgb_0_0_sim_netlist.vhdl @@ -0,0 +1,14158 @@ +-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +-- Date : Sun Mar 05 18:57:17 2017 +-- Host : WK73 running 64-bit Service Pack 1 (build 7601) +-- Command : write_vhdl -force -mode funcsim +-- c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/Arty_Z7_20_dvi2rgb_0_0_sim_netlist.vhdl +-- Design : Arty_Z7_20_dvi2rgb_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg400-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_ChannelBond is + port ( + pAllVld_q : out STD_LOGIC; + pAllVldBgnFlag : out STD_LOGIC; + pMeRdy_int_reg_0 : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 7 downto 0 ); + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + pAllVld : in STD_LOGIC; + PixelClk_int : in STD_LOGIC; + pAllVldBgnFlag0 : in STD_LOGIC; + pAligned_reg : in STD_LOGIC; + pRdy_0 : in STD_LOGIC; + pRdy_1 : in STD_LOGIC; + pDataInRaw : in STD_LOGIC_VECTOR ( 9 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_ChannelBond : entity is "ChannelBond"; +end Arty_Z7_20_dvi2rgb_0_0_ChannelBond; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_ChannelBond is + signal \^pallvldbgnflag\ : STD_LOGIC; + signal pBlnkBgnFlag : STD_LOGIC; + signal pBlnkBgnFlag_i_1_n_0 : STD_LOGIC; + signal \pDataFIFO_reg_n_0_[9]\ : STD_LOGIC; + signal pDataInBnd : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal \pDataIn[7]_i_3__1_n_0\ : STD_LOGIC; + signal \pDataIn[7]_i_4__1_n_0\ : STD_LOGIC; + signal pMeRdy_int_i_1_n_0 : STD_LOGIC; + signal \^pmerdy_int_reg_0\ : STD_LOGIC; + signal pRdA : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \pRdA_rep[0]_i_1_n_0\ : STD_LOGIC; + signal \pRdA_rep[1]_i_1_n_0\ : STD_LOGIC; + signal \pRdA_rep[2]_i_1_n_0\ : STD_LOGIC; + signal \pRdA_rep[3]_i_1_n_0\ : STD_LOGIC; + signal \pRdA_rep[4]_i_1_n_0\ : STD_LOGIC; + signal pRdEn : STD_LOGIC; + signal pRdEn_i_1_n_0 : STD_LOGIC; + signal pTokenFlag : STD_LOGIC; + signal pTokenFlag0 : STD_LOGIC; + signal pTokenFlag_i_2_n_0 : STD_LOGIC; + signal pTokenFlag_i_3_n_0 : STD_LOGIC; + signal pTokenFlag_q : STD_LOGIC; + signal \pWrA_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \p_0_out__0\ : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal NLW_pFIFO_reg_0_31_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_pFIFO_reg_0_31_6_9_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_pFIFO_reg_0_31_6_9_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \pDataIn[1]_i_1__0\ : label is "soft_lutpair56"; + attribute SOFT_HLUTNM of \pDataIn[2]_i_1__0\ : label is "soft_lutpair56"; + attribute SOFT_HLUTNM of \pDataIn[3]_i_1__0\ : label is "soft_lutpair55"; + attribute SOFT_HLUTNM of \pDataIn[4]_i_1__0\ : label is "soft_lutpair55"; + attribute SOFT_HLUTNM of \pDataIn[6]_i_1__0\ : label is "soft_lutpair57"; + attribute SOFT_HLUTNM of \pDataIn[7]_i_1__0\ : label is "soft_lutpair58"; + attribute SOFT_HLUTNM of \pDataIn[7]_i_2__0\ : label is "soft_lutpair57"; + attribute METHODOLOGY_DRC_VIOS : string; + attribute METHODOLOGY_DRC_VIOS of pFIFO_reg_0_31_0_5 : label is ""; + attribute METHODOLOGY_DRC_VIOS of pFIFO_reg_0_31_6_9 : label is ""; + attribute SOFT_HLUTNM of pMeRdy_int_i_1 : label is "soft_lutpair58"; + attribute SOFT_HLUTNM of \pRdA_rep[1]_i_1\ : label is "soft_lutpair60"; + attribute SOFT_HLUTNM of \pRdA_rep[2]_i_1\ : label is "soft_lutpair60"; + attribute SOFT_HLUTNM of \pRdA_rep[3]_i_1\ : label is "soft_lutpair53"; + attribute SOFT_HLUTNM of \pRdA_rep[4]_i_1\ : label is "soft_lutpair53"; + attribute SOFT_HLUTNM of \pWrA[1]_i_1\ : label is "soft_lutpair59"; + attribute SOFT_HLUTNM of \pWrA[2]_i_1\ : label is "soft_lutpair59"; + attribute SOFT_HLUTNM of \pWrA[3]_i_1\ : label is "soft_lutpair54"; + attribute SOFT_HLUTNM of \pWrA[4]_i_2\ : label is "soft_lutpair54"; +begin + pAllVldBgnFlag <= \^pallvldbgnflag\; + pMeRdy_int_reg_0 <= \^pmerdy_int_reg_0\; +pAllVldBgnFlag_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pAllVldBgnFlag0, + Q => \^pallvldbgnflag\, + R => '0' + ); +pAllVld_q_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pAllVld, + Q => pAllVld_q, + R => '0' + ); +pBlnkBgnFlag_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => pTokenFlag, + I1 => pTokenFlag_q, + O => pBlnkBgnFlag_i_1_n_0 + ); +pBlnkBgnFlag_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pBlnkBgnFlag_i_1_n_0, + Q => pBlnkBgnFlag, + R => '0' + ); +\pDataFIFO_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \p_0_out__0\(0), + Q => pDataInBnd(0), + R => '0' + ); +\pDataFIFO_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \p_0_out__0\(1), + Q => pDataInBnd(1), + R => '0' + ); +\pDataFIFO_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \p_0_out__0\(2), + Q => pDataInBnd(2), + R => '0' + ); +\pDataFIFO_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \p_0_out__0\(3), + Q => pDataInBnd(3), + R => '0' + ); +\pDataFIFO_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \p_0_out__0\(4), + Q => pDataInBnd(4), + R => '0' + ); +\pDataFIFO_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \p_0_out__0\(5), + Q => pDataInBnd(5), + R => '0' + ); +\pDataFIFO_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \p_0_out__0\(6), + Q => pDataInBnd(6), + R => '0' + ); +\pDataFIFO_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \p_0_out__0\(7), + Q => pDataInBnd(7), + R => '0' + ); +\pDataFIFO_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \p_0_out__0\(8), + Q => pDataInBnd(8), + R => '0' + ); +\pDataFIFO_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \p_0_out__0\(9), + Q => \pDataFIFO_reg_n_0_[9]\, + R => '0' + ); +\pDataIn[0]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"60" + ) + port map ( + I0 => \pDataFIFO_reg_n_0_[9]\, + I1 => pDataInBnd(0), + I2 => \pDataIn[7]_i_3__1_n_0\, + O => D(0) + ); +\pDataIn[1]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6090" + ) + port map ( + I0 => pDataInBnd(1), + I1 => pDataInBnd(0), + I2 => \pDataIn[7]_i_3__1_n_0\, + I3 => pDataInBnd(8), + O => D(1) + ); +\pDataIn[2]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6090" + ) + port map ( + I0 => pDataInBnd(2), + I1 => pDataInBnd(1), + I2 => \pDataIn[7]_i_3__1_n_0\, + I3 => pDataInBnd(8), + O => D(2) + ); +\pDataIn[3]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6090" + ) + port map ( + I0 => pDataInBnd(3), + I1 => pDataInBnd(2), + I2 => \pDataIn[7]_i_3__1_n_0\, + I3 => pDataInBnd(8), + O => D(3) + ); +\pDataIn[4]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6090" + ) + port map ( + I0 => pDataInBnd(4), + I1 => pDataInBnd(3), + I2 => \pDataIn[7]_i_3__1_n_0\, + I3 => pDataInBnd(8), + O => D(4) + ); +\pDataIn[5]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6090" + ) + port map ( + I0 => pDataInBnd(5), + I1 => pDataInBnd(4), + I2 => \pDataIn[7]_i_3__1_n_0\, + I3 => pDataInBnd(8), + O => D(5) + ); +\pDataIn[6]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6090" + ) + port map ( + I0 => pDataInBnd(6), + I1 => pDataInBnd(5), + I2 => \pDataIn[7]_i_3__1_n_0\, + I3 => pDataInBnd(8), + O => D(6) + ); +\pDataIn[7]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"7F" + ) + port map ( + I0 => \^pmerdy_int_reg_0\, + I1 => pRdy_0, + I2 => pRdy_1, + O => SR(0) + ); +\pDataIn[7]_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6090" + ) + port map ( + I0 => pDataInBnd(7), + I1 => pDataInBnd(6), + I2 => \pDataIn[7]_i_3__1_n_0\, + I3 => pDataInBnd(8), + O => D(7) + ); +\pDataIn[7]_i_3__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFBDFFF" + ) + port map ( + I0 => pDataInBnd(5), + I1 => pDataInBnd(4), + I2 => pDataInBnd(3), + I3 => pDataInBnd(7), + I4 => pDataInBnd(6), + I5 => \pDataIn[7]_i_4__1_n_0\, + O => \pDataIn[7]_i_3__1_n_0\ + ); +\pDataIn[7]_i_4__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FBBFFFFFFFFFFDDF" + ) + port map ( + I0 => pDataInBnd(2), + I1 => pDataInBnd(3), + I2 => pDataInBnd(7), + I3 => pDataInBnd(8), + I4 => pDataInBnd(0), + I5 => pDataInBnd(1), + O => \pDataIn[7]_i_4__1_n_0\ + ); +pFIFO_reg_0_31_0_5: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 0) => pRdA(4 downto 0), + ADDRB(4 downto 0) => pRdA(4 downto 0), + ADDRC(4 downto 0) => pRdA(4 downto 0), + ADDRD(4 downto 0) => \pWrA_reg__0\(4 downto 0), + DIA(1 downto 0) => pDataInRaw(1 downto 0), + DIB(1 downto 0) => pDataInRaw(3 downto 2), + DIC(1 downto 0) => pDataInRaw(5 downto 4), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \p_0_out__0\(1 downto 0), + DOB(1 downto 0) => \p_0_out__0\(3 downto 2), + DOC(1 downto 0) => \p_0_out__0\(5 downto 4), + DOD(1 downto 0) => NLW_pFIFO_reg_0_31_0_5_DOD_UNCONNECTED(1 downto 0), + WCLK => PixelClk_int, + WE => pAllVld + ); +pFIFO_reg_0_31_6_9: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 0) => pRdA(4 downto 0), + ADDRB(4 downto 0) => pRdA(4 downto 0), + ADDRC(4 downto 0) => pRdA(4 downto 0), + ADDRD(4 downto 0) => \pWrA_reg__0\(4 downto 0), + DIA(1 downto 0) => pDataInRaw(7 downto 6), + DIB(1 downto 0) => pDataInRaw(9 downto 8), + DIC(1 downto 0) => B"00", + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \p_0_out__0\(7 downto 6), + DOB(1 downto 0) => \p_0_out__0\(9 downto 8), + DOC(1 downto 0) => NLW_pFIFO_reg_0_31_6_9_DOC_UNCONNECTED(1 downto 0), + DOD(1 downto 0) => NLW_pFIFO_reg_0_31_6_9_DOD_UNCONNECTED(1 downto 0), + WCLK => PixelClk_int, + WE => pAllVld + ); +pMeRdy_int_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => pBlnkBgnFlag, + I1 => \^pmerdy_int_reg_0\, + O => pMeRdy_int_i_1_n_0 + ); +pMeRdy_int_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pMeRdy_int_i_1_n_0, + Q => \^pmerdy_int_reg_0\, + R => pAligned_reg + ); +\pRdA_reg_rep[0]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => pRdEn, + D => \pRdA_rep[0]_i_1_n_0\, + Q => pRdA(0), + R => pAligned_reg + ); +\pRdA_reg_rep[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => pRdEn, + D => \pRdA_rep[1]_i_1_n_0\, + Q => pRdA(1), + R => pAligned_reg + ); +\pRdA_reg_rep[2]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => pRdEn, + D => \pRdA_rep[2]_i_1_n_0\, + Q => pRdA(2), + R => pAligned_reg + ); +\pRdA_reg_rep[3]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => pRdEn, + D => \pRdA_rep[3]_i_1_n_0\, + Q => pRdA(3), + R => pAligned_reg + ); +\pRdA_reg_rep[4]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => pRdEn, + D => \pRdA_rep[4]_i_1_n_0\, + Q => pRdA(4), + R => pAligned_reg + ); +\pRdA_rep[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => pRdA(0), + O => \pRdA_rep[0]_i_1_n_0\ + ); +\pRdA_rep[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => pRdA(0), + I1 => pRdA(1), + O => \pRdA_rep[1]_i_1_n_0\ + ); +\pRdA_rep[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => pRdA(1), + I1 => pRdA(0), + I2 => pRdA(2), + O => \pRdA_rep[2]_i_1_n_0\ + ); +\pRdA_rep[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => pRdA(0), + I1 => pRdA(1), + I2 => pRdA(2), + I3 => pRdA(3), + O => \pRdA_rep[3]_i_1_n_0\ + ); +\pRdA_rep[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => pRdA(2), + I1 => pRdA(3), + I2 => pRdA(0), + I3 => pRdA(1), + I4 => pRdA(4), + O => \pRdA_rep[4]_i_1_n_0\ + ); +pRdEn_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FBBBBBBBFAAAAAAA" + ) + port map ( + I0 => \^pallvldbgnflag\, + I1 => pBlnkBgnFlag, + I2 => pRdy_1, + I3 => \^pmerdy_int_reg_0\, + I4 => pRdy_0, + I5 => pRdEn, + O => pRdEn_i_1_n_0 + ); +pRdEn_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pRdEn_i_1_n_0, + Q => pRdEn, + R => pAligned_reg + ); +pTokenFlag_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"5555DD5555F55555" + ) + port map ( + I0 => pRdEn, + I1 => pTokenFlag_i_2_n_0, + I2 => pTokenFlag_i_3_n_0, + I3 => pDataInBnd(1), + I4 => pDataInBnd(2), + I5 => pDataInBnd(0), + O => pTokenFlag0 + ); +pTokenFlag_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000002000000000" + ) + port map ( + I0 => pDataInBnd(5), + I1 => pDataInBnd(6), + I2 => pDataInBnd(3), + I3 => pDataInBnd(4), + I4 => pDataInBnd(8), + I5 => pDataInBnd(7), + O => pTokenFlag_i_2_n_0 + ); +pTokenFlag_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000002000000000" + ) + port map ( + I0 => pDataInBnd(6), + I1 => pDataInBnd(5), + I2 => pDataInBnd(4), + I3 => pDataInBnd(3), + I4 => pDataInBnd(7), + I5 => pDataInBnd(8), + O => pTokenFlag_i_3_n_0 + ); +pTokenFlag_q_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pTokenFlag, + Q => pTokenFlag_q, + R => '0' + ); +pTokenFlag_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pTokenFlag0, + Q => pTokenFlag, + R => '0' + ); +\pWrA[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \pWrA_reg__0\(0), + O => \p_0_in__0\(0) + ); +\pWrA[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \pWrA_reg__0\(0), + I1 => \pWrA_reg__0\(1), + O => \p_0_in__0\(1) + ); +\pWrA[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \pWrA_reg__0\(1), + I1 => \pWrA_reg__0\(0), + I2 => \pWrA_reg__0\(2), + O => \p_0_in__0\(2) + ); +\pWrA[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \pWrA_reg__0\(0), + I1 => \pWrA_reg__0\(1), + I2 => \pWrA_reg__0\(2), + I3 => \pWrA_reg__0\(3), + O => \p_0_in__0\(3) + ); +\pWrA[4]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \pWrA_reg__0\(2), + I1 => \pWrA_reg__0\(3), + I2 => \pWrA_reg__0\(0), + I3 => \pWrA_reg__0\(1), + I4 => \pWrA_reg__0\(4), + O => \p_0_in__0\(4) + ); +\pWrA_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \p_0_in__0\(0), + Q => \pWrA_reg__0\(0), + R => pAligned_reg + ); +\pWrA_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \p_0_in__0\(1), + Q => \pWrA_reg__0\(1), + R => pAligned_reg + ); +\pWrA_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \p_0_in__0\(2), + Q => \pWrA_reg__0\(2), + R => pAligned_reg + ); +\pWrA_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \p_0_in__0\(3), + Q => \pWrA_reg__0\(3), + R => pAligned_reg + ); +\pWrA_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \p_0_in__0\(4), + Q => \pWrA_reg__0\(4), + R => pAligned_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_ChannelBond_10 is + port ( + pMeRdy_int_reg_0 : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 7 downto 0 ); + \pDataIn_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + PixelClk_int : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + pRdy_2 : in STD_LOGIC; + pRdy_0 : in STD_LOGIC; + pAllVldBgnFlag : in STD_LOGIC; + pAllVld : in STD_LOGIC; + pDataInRaw : in STD_LOGIC_VECTOR ( 9 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_ChannelBond_10 : entity is "ChannelBond"; +end Arty_Z7_20_dvi2rgb_0_0_ChannelBond_10; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_ChannelBond_10 is + signal pBlnkBgnFlag : STD_LOGIC; + signal \pBlnkBgnFlag_i_1__0_n_0\ : STD_LOGIC; + signal \pDataFIFO_reg_n_0_[9]\ : STD_LOGIC; + signal pDataInBnd : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal \pDataIn[7]_i_3__0_n_0\ : STD_LOGIC; + signal \pDataIn[7]_i_4__0_n_0\ : STD_LOGIC; + signal \pMeRdy_int_i_1__1_n_0\ : STD_LOGIC; + signal \^pmerdy_int_reg_0\ : STD_LOGIC; + signal pRdA : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \pRdA_rep[0]_i_1__1_n_0\ : STD_LOGIC; + signal \pRdA_rep[1]_i_1__1_n_0\ : STD_LOGIC; + signal \pRdA_rep[2]_i_1__1_n_0\ : STD_LOGIC; + signal \pRdA_rep[3]_i_1__1_n_0\ : STD_LOGIC; + signal \pRdA_rep[4]_i_1__1_n_0\ : STD_LOGIC; + signal pRdEn : STD_LOGIC; + signal \pRdEn_i_1__0_n_0\ : STD_LOGIC; + signal pTokenFlag : STD_LOGIC; + signal pTokenFlag0 : STD_LOGIC; + signal \pTokenFlag_i_2__0_n_0\ : STD_LOGIC; + signal \pTokenFlag_i_3__0_n_0\ : STD_LOGIC; + signal pTokenFlag_q : STD_LOGIC; + signal \pWrA_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal p_0_out : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal NLW_pFIFO_reg_0_31_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_pFIFO_reg_0_31_6_9_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_pFIFO_reg_0_31_6_9_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \pDataIn[1]_i_1\ : label is "soft_lutpair29"; + attribute SOFT_HLUTNM of \pDataIn[2]_i_1\ : label is "soft_lutpair29"; + attribute SOFT_HLUTNM of \pDataIn[3]_i_1\ : label is "soft_lutpair28"; + attribute SOFT_HLUTNM of \pDataIn[4]_i_1\ : label is "soft_lutpair28"; + attribute SOFT_HLUTNM of \pDataIn[6]_i_1\ : label is "soft_lutpair30"; + attribute SOFT_HLUTNM of \pDataIn[7]_i_1\ : label is "soft_lutpair31"; + attribute SOFT_HLUTNM of \pDataIn[7]_i_2\ : label is "soft_lutpair30"; + attribute METHODOLOGY_DRC_VIOS : string; + attribute METHODOLOGY_DRC_VIOS of pFIFO_reg_0_31_0_5 : label is ""; + attribute METHODOLOGY_DRC_VIOS of pFIFO_reg_0_31_6_9 : label is ""; + attribute SOFT_HLUTNM of \pMeRdy_int_i_1__1\ : label is "soft_lutpair31"; + attribute SOFT_HLUTNM of \pRdA_rep[1]_i_1__1\ : label is "soft_lutpair33"; + attribute SOFT_HLUTNM of \pRdA_rep[2]_i_1__1\ : label is "soft_lutpair33"; + attribute SOFT_HLUTNM of \pRdA_rep[3]_i_1__1\ : label is "soft_lutpair26"; + attribute SOFT_HLUTNM of \pRdA_rep[4]_i_1__1\ : label is "soft_lutpair26"; + attribute SOFT_HLUTNM of \pWrA[1]_i_1__0\ : label is "soft_lutpair32"; + attribute SOFT_HLUTNM of \pWrA[2]_i_1__0\ : label is "soft_lutpair32"; + attribute SOFT_HLUTNM of \pWrA[3]_i_1__0\ : label is "soft_lutpair27"; + attribute SOFT_HLUTNM of \pWrA[4]_i_1__0\ : label is "soft_lutpair27"; +begin + pMeRdy_int_reg_0 <= \^pmerdy_int_reg_0\; +\pBlnkBgnFlag_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => pTokenFlag, + I1 => pTokenFlag_q, + O => \pBlnkBgnFlag_i_1__0_n_0\ + ); +pBlnkBgnFlag_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pBlnkBgnFlag_i_1__0_n_0\, + Q => pBlnkBgnFlag, + R => '0' + ); +\pDataFIFO_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_out(0), + Q => pDataInBnd(0), + R => '0' + ); +\pDataFIFO_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_out(1), + Q => pDataInBnd(1), + R => '0' + ); +\pDataFIFO_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_out(2), + Q => pDataInBnd(2), + R => '0' + ); +\pDataFIFO_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_out(3), + Q => pDataInBnd(3), + R => '0' + ); +\pDataFIFO_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_out(4), + Q => pDataInBnd(4), + R => '0' + ); +\pDataFIFO_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_out(5), + Q => pDataInBnd(5), + R => '0' + ); +\pDataFIFO_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_out(6), + Q => pDataInBnd(6), + R => '0' + ); +\pDataFIFO_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_out(7), + Q => pDataInBnd(7), + R => '0' + ); +\pDataFIFO_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_out(8), + Q => pDataInBnd(8), + R => '0' + ); +\pDataFIFO_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_out(9), + Q => \pDataFIFO_reg_n_0_[9]\, + R => '0' + ); +\pDataIn[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"60" + ) + port map ( + I0 => \pDataFIFO_reg_n_0_[9]\, + I1 => pDataInBnd(0), + I2 => \pDataIn[7]_i_3__0_n_0\, + O => D(0) + ); +\pDataIn[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6090" + ) + port map ( + I0 => pDataInBnd(1), + I1 => pDataInBnd(0), + I2 => \pDataIn[7]_i_3__0_n_0\, + I3 => pDataInBnd(8), + O => D(1) + ); +\pDataIn[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6090" + ) + port map ( + I0 => pDataInBnd(2), + I1 => pDataInBnd(1), + I2 => \pDataIn[7]_i_3__0_n_0\, + I3 => pDataInBnd(8), + O => D(2) + ); +\pDataIn[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6090" + ) + port map ( + I0 => pDataInBnd(3), + I1 => pDataInBnd(2), + I2 => \pDataIn[7]_i_3__0_n_0\, + I3 => pDataInBnd(8), + O => D(3) + ); +\pDataIn[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6090" + ) + port map ( + I0 => pDataInBnd(4), + I1 => pDataInBnd(3), + I2 => \pDataIn[7]_i_3__0_n_0\, + I3 => pDataInBnd(8), + O => D(4) + ); +\pDataIn[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6090" + ) + port map ( + I0 => pDataInBnd(5), + I1 => pDataInBnd(4), + I2 => \pDataIn[7]_i_3__0_n_0\, + I3 => pDataInBnd(8), + O => D(5) + ); +\pDataIn[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6090" + ) + port map ( + I0 => pDataInBnd(6), + I1 => pDataInBnd(5), + I2 => \pDataIn[7]_i_3__0_n_0\, + I3 => pDataInBnd(8), + O => D(6) + ); +\pDataIn[7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"7F" + ) + port map ( + I0 => \^pmerdy_int_reg_0\, + I1 => pRdy_2, + I2 => pRdy_0, + O => \pDataIn_reg[7]\(0) + ); +\pDataIn[7]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6090" + ) + port map ( + I0 => pDataInBnd(7), + I1 => pDataInBnd(6), + I2 => \pDataIn[7]_i_3__0_n_0\, + I3 => pDataInBnd(8), + O => D(7) + ); +\pDataIn[7]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFBDFFF" + ) + port map ( + I0 => pDataInBnd(5), + I1 => pDataInBnd(4), + I2 => pDataInBnd(3), + I3 => pDataInBnd(7), + I4 => pDataInBnd(6), + I5 => \pDataIn[7]_i_4__0_n_0\, + O => \pDataIn[7]_i_3__0_n_0\ + ); +\pDataIn[7]_i_4__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FBBFFFFFFFFFFDDF" + ) + port map ( + I0 => pDataInBnd(2), + I1 => pDataInBnd(3), + I2 => pDataInBnd(7), + I3 => pDataInBnd(8), + I4 => pDataInBnd(0), + I5 => pDataInBnd(1), + O => \pDataIn[7]_i_4__0_n_0\ + ); +pFIFO_reg_0_31_0_5: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 0) => pRdA(4 downto 0), + ADDRB(4 downto 0) => pRdA(4 downto 0), + ADDRC(4 downto 0) => pRdA(4 downto 0), + ADDRD(4 downto 0) => \pWrA_reg__0\(4 downto 0), + DIA(1 downto 0) => pDataInRaw(1 downto 0), + DIB(1 downto 0) => pDataInRaw(3 downto 2), + DIC(1 downto 0) => pDataInRaw(5 downto 4), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => p_0_out(1 downto 0), + DOB(1 downto 0) => p_0_out(3 downto 2), + DOC(1 downto 0) => p_0_out(5 downto 4), + DOD(1 downto 0) => NLW_pFIFO_reg_0_31_0_5_DOD_UNCONNECTED(1 downto 0), + WCLK => PixelClk_int, + WE => pAllVld + ); +pFIFO_reg_0_31_6_9: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 0) => pRdA(4 downto 0), + ADDRB(4 downto 0) => pRdA(4 downto 0), + ADDRC(4 downto 0) => pRdA(4 downto 0), + ADDRD(4 downto 0) => \pWrA_reg__0\(4 downto 0), + DIA(1 downto 0) => pDataInRaw(7 downto 6), + DIB(1 downto 0) => pDataInRaw(9 downto 8), + DIC(1 downto 0) => B"00", + DID(1 downto 0) => B"00", + DOA(1 downto 0) => p_0_out(7 downto 6), + DOB(1 downto 0) => p_0_out(9 downto 8), + DOC(1 downto 0) => NLW_pFIFO_reg_0_31_6_9_DOC_UNCONNECTED(1 downto 0), + DOD(1 downto 0) => NLW_pFIFO_reg_0_31_6_9_DOD_UNCONNECTED(1 downto 0), + WCLK => PixelClk_int, + WE => pAllVld + ); +\pMeRdy_int_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => pBlnkBgnFlag, + I1 => \^pmerdy_int_reg_0\, + O => \pMeRdy_int_i_1__1_n_0\ + ); +pMeRdy_int_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pMeRdy_int_i_1__1_n_0\, + Q => \^pmerdy_int_reg_0\, + R => SR(0) + ); +\pRdA_reg_rep[0]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => pRdEn, + D => \pRdA_rep[0]_i_1__1_n_0\, + Q => pRdA(0), + R => SR(0) + ); +\pRdA_reg_rep[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => pRdEn, + D => \pRdA_rep[1]_i_1__1_n_0\, + Q => pRdA(1), + R => SR(0) + ); +\pRdA_reg_rep[2]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => pRdEn, + D => \pRdA_rep[2]_i_1__1_n_0\, + Q => pRdA(2), + R => SR(0) + ); +\pRdA_reg_rep[3]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => pRdEn, + D => \pRdA_rep[3]_i_1__1_n_0\, + Q => pRdA(3), + R => SR(0) + ); +\pRdA_reg_rep[4]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => pRdEn, + D => \pRdA_rep[4]_i_1__1_n_0\, + Q => pRdA(4), + R => SR(0) + ); +\pRdA_rep[0]_i_1__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => pRdA(0), + O => \pRdA_rep[0]_i_1__1_n_0\ + ); +\pRdA_rep[1]_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => pRdA(0), + I1 => pRdA(1), + O => \pRdA_rep[1]_i_1__1_n_0\ + ); +\pRdA_rep[2]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => pRdA(1), + I1 => pRdA(0), + I2 => pRdA(2), + O => \pRdA_rep[2]_i_1__1_n_0\ + ); +\pRdA_rep[3]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => pRdA(0), + I1 => pRdA(1), + I2 => pRdA(2), + I3 => pRdA(3), + O => \pRdA_rep[3]_i_1__1_n_0\ + ); +\pRdA_rep[4]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => pRdA(2), + I1 => pRdA(3), + I2 => pRdA(0), + I3 => pRdA(1), + I4 => pRdA(4), + O => \pRdA_rep[4]_i_1__1_n_0\ + ); +\pRdEn_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FBBBBBBBFAAAAAAA" + ) + port map ( + I0 => pAllVldBgnFlag, + I1 => pBlnkBgnFlag, + I2 => pRdy_0, + I3 => \^pmerdy_int_reg_0\, + I4 => pRdy_2, + I5 => pRdEn, + O => \pRdEn_i_1__0_n_0\ + ); +pRdEn_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pRdEn_i_1__0_n_0\, + Q => pRdEn, + R => SR(0) + ); +\pTokenFlag_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5555DD5555F55555" + ) + port map ( + I0 => pRdEn, + I1 => \pTokenFlag_i_2__0_n_0\, + I2 => \pTokenFlag_i_3__0_n_0\, + I3 => pDataInBnd(1), + I4 => pDataInBnd(2), + I5 => pDataInBnd(0), + O => pTokenFlag0 + ); +\pTokenFlag_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000002000000000" + ) + port map ( + I0 => pDataInBnd(5), + I1 => pDataInBnd(6), + I2 => pDataInBnd(3), + I3 => pDataInBnd(4), + I4 => pDataInBnd(8), + I5 => pDataInBnd(7), + O => \pTokenFlag_i_2__0_n_0\ + ); +\pTokenFlag_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000002000000000" + ) + port map ( + I0 => pDataInBnd(6), + I1 => pDataInBnd(5), + I2 => pDataInBnd(4), + I3 => pDataInBnd(3), + I4 => pDataInBnd(7), + I5 => pDataInBnd(8), + O => \pTokenFlag_i_3__0_n_0\ + ); +pTokenFlag_q_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pTokenFlag, + Q => pTokenFlag_q, + R => '0' + ); +pTokenFlag_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pTokenFlag0, + Q => pTokenFlag, + R => '0' + ); +\pWrA[0]_i_1__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \pWrA_reg__0\(0), + O => \p_0_in__0\(0) + ); +\pWrA[1]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \pWrA_reg__0\(0), + I1 => \pWrA_reg__0\(1), + O => \p_0_in__0\(1) + ); +\pWrA[2]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \pWrA_reg__0\(1), + I1 => \pWrA_reg__0\(0), + I2 => \pWrA_reg__0\(2), + O => \p_0_in__0\(2) + ); +\pWrA[3]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \pWrA_reg__0\(0), + I1 => \pWrA_reg__0\(1), + I2 => \pWrA_reg__0\(2), + I3 => \pWrA_reg__0\(3), + O => \p_0_in__0\(3) + ); +\pWrA[4]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \pWrA_reg__0\(2), + I1 => \pWrA_reg__0\(3), + I2 => \pWrA_reg__0\(0), + I3 => \pWrA_reg__0\(1), + I4 => \pWrA_reg__0\(4), + O => \p_0_in__0\(4) + ); +\pWrA_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \p_0_in__0\(0), + Q => \pWrA_reg__0\(0), + R => SR(0) + ); +\pWrA_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \p_0_in__0\(1), + Q => \pWrA_reg__0\(1), + R => SR(0) + ); +\pWrA_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \p_0_in__0\(2), + Q => \pWrA_reg__0\(2), + R => SR(0) + ); +\pWrA_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \p_0_in__0\(3), + Q => \pWrA_reg__0\(3), + R => SR(0) + ); +\pWrA_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \p_0_in__0\(4), + Q => \pWrA_reg__0\(4), + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_ChannelBond_17 is + port ( + pMeRdy_int_reg_0 : out STD_LOGIC; + pVde_0 : out STD_LOGIC; + \pDataIn_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + pC1_reg : out STD_LOGIC; + pC0_reg : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 7 downto 0 ); + PixelClk_int : in STD_LOGIC; + pAligned_reg : in STD_LOGIC; + pRdy_1 : in STD_LOGIC; + pRdy_2 : in STD_LOGIC; + pAllVldBgnFlag : in STD_LOGIC; + pC1 : in STD_LOGIC; + pC0 : in STD_LOGIC; + pAllVld : in STD_LOGIC; + pDataInRaw : in STD_LOGIC_VECTOR ( 9 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_ChannelBond_17 : entity is "ChannelBond"; +end Arty_Z7_20_dvi2rgb_0_0_ChannelBond_17; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_ChannelBond_17 is + signal pBlnkBgnFlag : STD_LOGIC; + signal \pBlnkBgnFlag_i_1__1_n_0\ : STD_LOGIC; + signal pC0_1 : STD_LOGIC; + signal \pDataFIFO_reg_n_0_[9]\ : STD_LOGIC; + signal pDataInBnd : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal \pDataIn[7]_i_3_n_0\ : STD_LOGIC; + signal \pDataIn[7]_i_4_n_0\ : STD_LOGIC; + signal \pMeRdy_int_i_1__0_n_0\ : STD_LOGIC; + signal \^pmerdy_int_reg_0\ : STD_LOGIC; + signal pRdA : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \pRdA_rep[0]_i_1__0_n_0\ : STD_LOGIC; + signal \pRdA_rep[1]_i_1__0_n_0\ : STD_LOGIC; + signal \pRdA_rep[2]_i_1__0_n_0\ : STD_LOGIC; + signal \pRdA_rep[3]_i_1__0_n_0\ : STD_LOGIC; + signal \pRdA_rep[4]_i_1__0_n_0\ : STD_LOGIC; + signal pRdEn : STD_LOGIC; + signal \pRdEn_i_1__1_n_0\ : STD_LOGIC; + signal pTokenFlag : STD_LOGIC; + signal pTokenFlag0 : STD_LOGIC; + signal \pTokenFlag_i_3__1_n_0\ : STD_LOGIC; + signal pTokenFlag_i_4_n_0 : STD_LOGIC; + signal pTokenFlag_q : STD_LOGIC; + signal \pWrA_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal p_0_out : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal NLW_pFIFO_reg_0_31_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_pFIFO_reg_0_31_6_9_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_pFIFO_reg_0_31_6_9_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of pC0_i_1 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of pC1_i_1 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \pDataIn[6]_i_1__1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \pDataIn[7]_i_1__1\ : label is "soft_lutpair5"; + attribute METHODOLOGY_DRC_VIOS : string; + attribute METHODOLOGY_DRC_VIOS of pFIFO_reg_0_31_0_5 : label is ""; + attribute METHODOLOGY_DRC_VIOS of pFIFO_reg_0_31_6_9 : label is ""; + attribute SOFT_HLUTNM of \pMeRdy_int_i_1__0\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \pRdA_rep[1]_i_1__0\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \pRdA_rep[2]_i_1__0\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \pRdA_rep[3]_i_1__0\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \pRdA_rep[4]_i_1__0\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of pVde_i_1 : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \pWrA[1]_i_1__1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \pWrA[2]_i_1__1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \pWrA[3]_i_1__1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \pWrA[4]_i_1__1\ : label is "soft_lutpair1"; +begin + pMeRdy_int_reg_0 <= \^pmerdy_int_reg_0\; +\pBlnkBgnFlag_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => pTokenFlag, + I1 => pTokenFlag_q, + O => \pBlnkBgnFlag_i_1__1_n_0\ + ); +pBlnkBgnFlag_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pBlnkBgnFlag_i_1__1_n_0\, + Q => pBlnkBgnFlag, + R => '0' + ); +pC0_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"74" + ) + port map ( + I0 => pDataInBnd(8), + I1 => pC0_1, + I2 => pC0, + O => pC0_reg + ); +pC1_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"6F60" + ) + port map ( + I0 => \pDataFIFO_reg_n_0_[9]\, + I1 => pDataInBnd(8), + I2 => pC0_1, + I3 => pC1, + O => pC1_reg + ); +\pDataFIFO_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_out(0), + Q => pDataInBnd(0), + R => '0' + ); +\pDataFIFO_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_out(1), + Q => pDataInBnd(1), + R => '0' + ); +\pDataFIFO_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_out(2), + Q => pDataInBnd(2), + R => '0' + ); +\pDataFIFO_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_out(3), + Q => pDataInBnd(3), + R => '0' + ); +\pDataFIFO_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_out(4), + Q => pDataInBnd(4), + R => '0' + ); +\pDataFIFO_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_out(5), + Q => pDataInBnd(5), + R => '0' + ); +\pDataFIFO_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_out(6), + Q => pDataInBnd(6), + R => '0' + ); +\pDataFIFO_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_out(7), + Q => pDataInBnd(7), + R => '0' + ); +\pDataFIFO_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_out(8), + Q => pDataInBnd(8), + R => '0' + ); +\pDataFIFO_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_out(9), + Q => \pDataFIFO_reg_n_0_[9]\, + R => '0' + ); +\pDataIn[0]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0EE0" + ) + port map ( + I0 => \pDataIn[7]_i_3_n_0\, + I1 => \pDataIn[7]_i_4_n_0\, + I2 => \pDataFIFO_reg_n_0_[9]\, + I3 => pDataInBnd(0), + O => D(0) + ); +\pDataIn[1]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0EE0E00E" + ) + port map ( + I0 => \pDataIn[7]_i_3_n_0\, + I1 => \pDataIn[7]_i_4_n_0\, + I2 => pDataInBnd(1), + I3 => pDataInBnd(0), + I4 => pDataInBnd(8), + O => D(1) + ); +\pDataIn[2]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0EE0E00E" + ) + port map ( + I0 => \pDataIn[7]_i_3_n_0\, + I1 => \pDataIn[7]_i_4_n_0\, + I2 => pDataInBnd(2), + I3 => pDataInBnd(1), + I4 => pDataInBnd(8), + O => D(2) + ); +\pDataIn[3]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0EE0E00E" + ) + port map ( + I0 => \pDataIn[7]_i_3_n_0\, + I1 => \pDataIn[7]_i_4_n_0\, + I2 => pDataInBnd(3), + I3 => pDataInBnd(2), + I4 => pDataInBnd(8), + O => D(3) + ); +\pDataIn[4]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0EE0E00E" + ) + port map ( + I0 => \pDataIn[7]_i_3_n_0\, + I1 => \pDataIn[7]_i_4_n_0\, + I2 => pDataInBnd(4), + I3 => pDataInBnd(3), + I4 => pDataInBnd(8), + O => D(4) + ); +\pDataIn[5]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0EE0E00E" + ) + port map ( + I0 => \pDataIn[7]_i_3_n_0\, + I1 => \pDataIn[7]_i_4_n_0\, + I2 => pDataInBnd(5), + I3 => pDataInBnd(4), + I4 => pDataInBnd(8), + O => D(5) + ); +\pDataIn[6]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0EE0E00E" + ) + port map ( + I0 => \pDataIn[7]_i_3_n_0\, + I1 => \pDataIn[7]_i_4_n_0\, + I2 => pDataInBnd(6), + I3 => pDataInBnd(5), + I4 => pDataInBnd(8), + O => D(6) + ); +\pDataIn[7]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"7F" + ) + port map ( + I0 => \^pmerdy_int_reg_0\, + I1 => pRdy_1, + I2 => pRdy_2, + O => \pDataIn_reg[7]\(0) + ); +\pDataIn[7]_i_2__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0EE0E00E" + ) + port map ( + I0 => \pDataIn[7]_i_3_n_0\, + I1 => \pDataIn[7]_i_4_n_0\, + I2 => pDataInBnd(7), + I3 => pDataInBnd(6), + I4 => pDataInBnd(8), + O => D(7) + ); +\pDataIn[7]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFBEFFFF7DFFFF" + ) + port map ( + I0 => pDataInBnd(7), + I1 => pDataInBnd(0), + I2 => pDataInBnd(1), + I3 => pDataInBnd(4), + I4 => pDataInBnd(5), + I5 => pDataInBnd(6), + O => \pDataIn[7]_i_3_n_0\ + ); +\pDataIn[7]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFBBFFDDFFFFF" + ) + port map ( + I0 => pDataInBnd(3), + I1 => pDataInBnd(4), + I2 => pDataInBnd(7), + I3 => pDataInBnd(8), + I4 => pDataInBnd(1), + I5 => pDataInBnd(2), + O => \pDataIn[7]_i_4_n_0\ + ); +pFIFO_reg_0_31_0_5: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 0) => pRdA(4 downto 0), + ADDRB(4 downto 0) => pRdA(4 downto 0), + ADDRC(4 downto 0) => pRdA(4 downto 0), + ADDRD(4 downto 0) => \pWrA_reg__0\(4 downto 0), + DIA(1 downto 0) => pDataInRaw(1 downto 0), + DIB(1 downto 0) => pDataInRaw(3 downto 2), + DIC(1 downto 0) => pDataInRaw(5 downto 4), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => p_0_out(1 downto 0), + DOB(1 downto 0) => p_0_out(3 downto 2), + DOC(1 downto 0) => p_0_out(5 downto 4), + DOD(1 downto 0) => NLW_pFIFO_reg_0_31_0_5_DOD_UNCONNECTED(1 downto 0), + WCLK => PixelClk_int, + WE => pAllVld + ); +pFIFO_reg_0_31_6_9: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 0) => pRdA(4 downto 0), + ADDRB(4 downto 0) => pRdA(4 downto 0), + ADDRC(4 downto 0) => pRdA(4 downto 0), + ADDRD(4 downto 0) => \pWrA_reg__0\(4 downto 0), + DIA(1 downto 0) => pDataInRaw(7 downto 6), + DIB(1 downto 0) => pDataInRaw(9 downto 8), + DIC(1 downto 0) => B"00", + DID(1 downto 0) => B"00", + DOA(1 downto 0) => p_0_out(7 downto 6), + DOB(1 downto 0) => p_0_out(9 downto 8), + DOC(1 downto 0) => NLW_pFIFO_reg_0_31_6_9_DOC_UNCONNECTED(1 downto 0), + DOD(1 downto 0) => NLW_pFIFO_reg_0_31_6_9_DOD_UNCONNECTED(1 downto 0), + WCLK => PixelClk_int, + WE => pAllVld + ); +\pMeRdy_int_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => pBlnkBgnFlag, + I1 => \^pmerdy_int_reg_0\, + O => \pMeRdy_int_i_1__0_n_0\ + ); +pMeRdy_int_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pMeRdy_int_i_1__0_n_0\, + Q => \^pmerdy_int_reg_0\, + R => pAligned_reg + ); +\pRdA_reg_rep[0]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => pRdEn, + D => \pRdA_rep[0]_i_1__0_n_0\, + Q => pRdA(0), + R => pAligned_reg + ); +\pRdA_reg_rep[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => pRdEn, + D => \pRdA_rep[1]_i_1__0_n_0\, + Q => pRdA(1), + R => pAligned_reg + ); +\pRdA_reg_rep[2]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => pRdEn, + D => \pRdA_rep[2]_i_1__0_n_0\, + Q => pRdA(2), + R => pAligned_reg + ); +\pRdA_reg_rep[3]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => pRdEn, + D => \pRdA_rep[3]_i_1__0_n_0\, + Q => pRdA(3), + R => pAligned_reg + ); +\pRdA_reg_rep[4]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => pRdEn, + D => \pRdA_rep[4]_i_1__0_n_0\, + Q => pRdA(4), + R => pAligned_reg + ); +\pRdA_rep[0]_i_1__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => pRdA(0), + O => \pRdA_rep[0]_i_1__0_n_0\ + ); +\pRdA_rep[1]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => pRdA(0), + I1 => pRdA(1), + O => \pRdA_rep[1]_i_1__0_n_0\ + ); +\pRdA_rep[2]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => pRdA(1), + I1 => pRdA(0), + I2 => pRdA(2), + O => \pRdA_rep[2]_i_1__0_n_0\ + ); +\pRdA_rep[3]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => pRdA(0), + I1 => pRdA(1), + I2 => pRdA(2), + I3 => pRdA(3), + O => \pRdA_rep[3]_i_1__0_n_0\ + ); +\pRdA_rep[4]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => pRdA(2), + I1 => pRdA(3), + I2 => pRdA(0), + I3 => pRdA(1), + I4 => pRdA(4), + O => \pRdA_rep[4]_i_1__0_n_0\ + ); +\pRdEn_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FBBBBBBBFAAAAAAA" + ) + port map ( + I0 => pAllVldBgnFlag, + I1 => pBlnkBgnFlag, + I2 => pRdy_2, + I3 => \^pmerdy_int_reg_0\, + I4 => pRdy_1, + I5 => pRdEn, + O => \pRdEn_i_1__1_n_0\ + ); +pRdEn_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pRdEn_i_1__1_n_0\, + Q => pRdEn, + R => pAligned_reg + ); +\pTokenFlag_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => pC0_1, + I1 => pRdEn, + O => pTokenFlag0 + ); +\pTokenFlag_i_2__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30080008" + ) + port map ( + I0 => \pTokenFlag_i_3__1_n_0\, + I1 => pDataInBnd(2), + I2 => pDataInBnd(1), + I3 => pDataInBnd(0), + I4 => pTokenFlag_i_4_n_0, + O => pC0_1 + ); +\pTokenFlag_i_3__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000002000000000" + ) + port map ( + I0 => pDataInBnd(4), + I1 => pDataInBnd(3), + I2 => pDataInBnd(6), + I3 => pDataInBnd(5), + I4 => pDataInBnd(7), + I5 => pDataInBnd(8), + O => \pTokenFlag_i_3__1_n_0\ + ); +pTokenFlag_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000002000000000" + ) + port map ( + I0 => pDataInBnd(3), + I1 => pDataInBnd(4), + I2 => pDataInBnd(5), + I3 => pDataInBnd(6), + I4 => pDataInBnd(8), + I5 => pDataInBnd(7), + O => pTokenFlag_i_4_n_0 + ); +pTokenFlag_q_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pTokenFlag, + Q => pTokenFlag_q, + R => '0' + ); +pTokenFlag_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pTokenFlag0, + Q => pTokenFlag, + R => '0' + ); +pVde_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \pDataIn[7]_i_3_n_0\, + I1 => \pDataIn[7]_i_4_n_0\, + O => pVde_0 + ); +\pWrA[0]_i_1__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \pWrA_reg__0\(0), + O => \p_0_in__0\(0) + ); +\pWrA[1]_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \pWrA_reg__0\(0), + I1 => \pWrA_reg__0\(1), + O => \p_0_in__0\(1) + ); +\pWrA[2]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \pWrA_reg__0\(1), + I1 => \pWrA_reg__0\(0), + I2 => \pWrA_reg__0\(2), + O => \p_0_in__0\(2) + ); +\pWrA[3]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \pWrA_reg__0\(0), + I1 => \pWrA_reg__0\(1), + I2 => \pWrA_reg__0\(2), + I3 => \pWrA_reg__0\(3), + O => \p_0_in__0\(3) + ); +\pWrA[4]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \pWrA_reg__0\(2), + I1 => \pWrA_reg__0\(3), + I2 => \pWrA_reg__0\(0), + I3 => \pWrA_reg__0\(1), + I4 => \pWrA_reg__0\(4), + O => \p_0_in__0\(4) + ); +\pWrA_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \p_0_in__0\(0), + Q => \pWrA_reg__0\(0), + R => pAligned_reg + ); +\pWrA_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \p_0_in__0\(1), + Q => \pWrA_reg__0\(1), + R => pAligned_reg + ); +\pWrA_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \p_0_in__0\(2), + Q => \pWrA_reg__0\(2), + R => pAligned_reg + ); +\pWrA_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \p_0_in__0\(3), + Q => \pWrA_reg__0\(3), + R => pAligned_reg + ); +\pWrA_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \p_0_in__0\(4), + Q => \pWrA_reg__0\(4), + R => pAligned_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_GlitchFilter is + port ( + \Filter.sOut_reg_0\ : out STD_LOGIC; + dScl_reg : out STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + RefClk : in STD_LOGIC; + SS : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_GlitchFilter : entity is "GlitchFilter"; +end Arty_Z7_20_dvi2rgb_0_0_GlitchFilter; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_GlitchFilter is + signal \Filter.cntPeriods[1]_i_1__0_n_0\ : STD_LOGIC; + signal \Filter.cntPeriods[2]_i_1__0_n_0\ : STD_LOGIC; + signal \Filter.cntPeriods[3]_i_2__0_n_0\ : STD_LOGIC; + signal \Filter.cntPeriods[3]_i_3__0_n_0\ : STD_LOGIC; + signal \Filter.cntPeriods_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \Filter.sOut_i_1__0_n_0\ : STD_LOGIC; + signal \^filter.sout_reg_0\ : STD_LOGIC; + signal \^dscl_reg\ : STD_LOGIC; + signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 0 to 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \Filter.cntPeriods[0]_i_1__0\ : label is "soft_lutpair81"; + attribute SOFT_HLUTNM of \Filter.cntPeriods[1]_i_1__0\ : label is "soft_lutpair82"; + attribute SOFT_HLUTNM of \Filter.cntPeriods[2]_i_1__0\ : label is "soft_lutpair82"; + attribute SOFT_HLUTNM of \Filter.cntPeriods[3]_i_3__0\ : label is "soft_lutpair81"; +begin + \Filter.sOut_reg_0\ <= \^filter.sout_reg_0\; + dScl_reg <= \^dscl_reg\; +\Filter.cntPeriods[0]_i_1__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \Filter.cntPeriods_reg__0\(0), + O => \p_0_in__0\(0) + ); +\Filter.cntPeriods[1]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \Filter.cntPeriods_reg__0\(0), + I1 => \Filter.cntPeriods_reg__0\(1), + O => \Filter.cntPeriods[1]_i_1__0_n_0\ + ); +\Filter.cntPeriods[2]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E1" + ) + port map ( + I0 => \Filter.cntPeriods_reg__0\(1), + I1 => \Filter.cntPeriods_reg__0\(0), + I2 => \Filter.cntPeriods_reg__0\(2), + O => \Filter.cntPeriods[2]_i_1__0_n_0\ + ); +\Filter.cntPeriods[3]_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \Filter.cntPeriods_reg__0\(1), + I1 => \Filter.cntPeriods_reg__0\(0), + I2 => \Filter.cntPeriods_reg__0\(2), + I3 => \Filter.cntPeriods_reg__0\(3), + O => \Filter.cntPeriods[3]_i_2__0_n_0\ + ); +\Filter.cntPeriods[3]_i_3__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FE01" + ) + port map ( + I0 => \Filter.cntPeriods_reg__0\(2), + I1 => \Filter.cntPeriods_reg__0\(0), + I2 => \Filter.cntPeriods_reg__0\(1), + I3 => \Filter.cntPeriods_reg__0\(3), + O => \Filter.cntPeriods[3]_i_3__0_n_0\ + ); +\Filter.cntPeriods_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => RefClk, + CE => \Filter.cntPeriods[3]_i_2__0_n_0\, + D => \p_0_in__0\(0), + Q => \Filter.cntPeriods_reg__0\(0), + S => SS(0) + ); +\Filter.cntPeriods_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => RefClk, + CE => \Filter.cntPeriods[3]_i_2__0_n_0\, + D => \Filter.cntPeriods[1]_i_1__0_n_0\, + Q => \Filter.cntPeriods_reg__0\(1), + R => SS(0) + ); +\Filter.cntPeriods_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => RefClk, + CE => \Filter.cntPeriods[3]_i_2__0_n_0\, + D => \Filter.cntPeriods[2]_i_1__0_n_0\, + Q => \Filter.cntPeriods_reg__0\(2), + R => SS(0) + ); +\Filter.cntPeriods_reg[3]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => RefClk, + CE => \Filter.cntPeriods[3]_i_2__0_n_0\, + D => \Filter.cntPeriods[3]_i_3__0_n_0\, + Q => \Filter.cntPeriods_reg__0\(3), + S => SS(0) + ); +\Filter.sIn_q_reg\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => '1', + D => \out\(0), + Q => \^filter.sout_reg_0\, + R => '0' + ); +\Filter.sOut_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFE00000002" + ) + port map ( + I0 => \^filter.sout_reg_0\, + I1 => \Filter.cntPeriods_reg__0\(3), + I2 => \Filter.cntPeriods_reg__0\(2), + I3 => \Filter.cntPeriods_reg__0\(0), + I4 => \Filter.cntPeriods_reg__0\(1), + I5 => \^dscl_reg\, + O => \Filter.sOut_i_1__0_n_0\ + ); +\Filter.sOut_reg\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => '1', + D => \Filter.sOut_i_1__0_n_0\, + Q => \^dscl_reg\, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_GlitchFilter_6 is + port ( + sIn_q : out STD_LOGIC; + sOut : out STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + RefClk : in STD_LOGIC; + SS : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_GlitchFilter_6 : entity is "GlitchFilter"; +end Arty_Z7_20_dvi2rgb_0_0_GlitchFilter_6; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_GlitchFilter_6 is + signal \Filter.cntPeriods[1]_i_1_n_0\ : STD_LOGIC; + signal \Filter.cntPeriods[2]_i_1_n_0\ : STD_LOGIC; + signal \Filter.cntPeriods[3]_i_2_n_0\ : STD_LOGIC; + signal \Filter.cntPeriods[3]_i_3_n_0\ : STD_LOGIC; + signal \Filter.cntPeriods_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \Filter.sOut_i_1_n_0\ : STD_LOGIC; + signal p_0_in : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^sin_q\ : STD_LOGIC; + signal \^sout\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \Filter.cntPeriods[0]_i_1\ : label is "soft_lutpair83"; + attribute SOFT_HLUTNM of \Filter.cntPeriods[1]_i_1\ : label is "soft_lutpair84"; + attribute SOFT_HLUTNM of \Filter.cntPeriods[2]_i_1\ : label is "soft_lutpair84"; + attribute SOFT_HLUTNM of \Filter.cntPeriods[3]_i_3\ : label is "soft_lutpair83"; +begin + sIn_q <= \^sin_q\; + sOut <= \^sout\; +\Filter.cntPeriods[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \Filter.cntPeriods_reg__0\(0), + O => p_0_in(0) + ); +\Filter.cntPeriods[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \Filter.cntPeriods_reg__0\(0), + I1 => \Filter.cntPeriods_reg__0\(1), + O => \Filter.cntPeriods[1]_i_1_n_0\ + ); +\Filter.cntPeriods[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E1" + ) + port map ( + I0 => \Filter.cntPeriods_reg__0\(1), + I1 => \Filter.cntPeriods_reg__0\(0), + I2 => \Filter.cntPeriods_reg__0\(2), + O => \Filter.cntPeriods[2]_i_1_n_0\ + ); +\Filter.cntPeriods[3]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \Filter.cntPeriods_reg__0\(1), + I1 => \Filter.cntPeriods_reg__0\(0), + I2 => \Filter.cntPeriods_reg__0\(2), + I3 => \Filter.cntPeriods_reg__0\(3), + O => \Filter.cntPeriods[3]_i_2_n_0\ + ); +\Filter.cntPeriods[3]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FE01" + ) + port map ( + I0 => \Filter.cntPeriods_reg__0\(2), + I1 => \Filter.cntPeriods_reg__0\(0), + I2 => \Filter.cntPeriods_reg__0\(1), + I3 => \Filter.cntPeriods_reg__0\(3), + O => \Filter.cntPeriods[3]_i_3_n_0\ + ); +\Filter.cntPeriods_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => RefClk, + CE => \Filter.cntPeriods[3]_i_2_n_0\, + D => p_0_in(0), + Q => \Filter.cntPeriods_reg__0\(0), + S => SS(0) + ); +\Filter.cntPeriods_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => RefClk, + CE => \Filter.cntPeriods[3]_i_2_n_0\, + D => \Filter.cntPeriods[1]_i_1_n_0\, + Q => \Filter.cntPeriods_reg__0\(1), + R => SS(0) + ); +\Filter.cntPeriods_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => RefClk, + CE => \Filter.cntPeriods[3]_i_2_n_0\, + D => \Filter.cntPeriods[2]_i_1_n_0\, + Q => \Filter.cntPeriods_reg__0\(2), + R => SS(0) + ); +\Filter.cntPeriods_reg[3]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => RefClk, + CE => \Filter.cntPeriods[3]_i_2_n_0\, + D => \Filter.cntPeriods[3]_i_3_n_0\, + Q => \Filter.cntPeriods_reg__0\(3), + S => SS(0) + ); +\Filter.sIn_q_reg\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => '1', + D => \out\(0), + Q => \^sin_q\, + R => '0' + ); +\Filter.sOut_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFE00000002" + ) + port map ( + I0 => \^sin_q\, + I1 => \Filter.cntPeriods_reg__0\(3), + I2 => \Filter.cntPeriods_reg__0\(2), + I3 => \Filter.cntPeriods_reg__0\(0), + I4 => \Filter.cntPeriods_reg__0\(1), + I5 => \^sout\, + O => \Filter.sOut_i_1_n_0\ + ); +\Filter.sOut_reg\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => '1', + D => \Filter.sOut_i_1_n_0\, + Q => \^sout\, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_InputSERDES is + port ( + D : out STD_LOGIC_VECTOR ( 4 downto 0 ); + pDataInRaw : out STD_LOGIC_VECTOR ( 9 downto 0 ); + TMDS_Data_p : in STD_LOGIC_VECTOR ( 0 to 0 ); + TMDS_Data_n : in STD_LOGIC_VECTOR ( 0 to 0 ); + PixelClk_int : in STD_LOGIC; + pIDLY_CE : in STD_LOGIC; + pIDLY_INC : in STD_LOGIC; + pIDLY_LD : in STD_LOGIC; + pBitslip : in STD_LOGIC; + \rMMCM_Reset_q_reg[0]\ : in STD_LOGIC; + CLKB : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_InputSERDES : entity is "InputSERDES"; +end Arty_Z7_20_dvi2rgb_0_0_InputSERDES; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_InputSERDES is + signal icascade1 : STD_LOGIC; + signal icascade2 : STD_LOGIC; + signal sDataIn : STD_LOGIC; + signal sDataInDly : STD_LOGIC; + signal NLW_DeserializerMaster_O_UNCONNECTED : STD_LOGIC; + signal NLW_DeserializerSlave_O_UNCONNECTED : STD_LOGIC; + signal NLW_DeserializerSlave_Q1_UNCONNECTED : STD_LOGIC; + signal NLW_DeserializerSlave_Q2_UNCONNECTED : STD_LOGIC; + signal NLW_DeserializerSlave_Q5_UNCONNECTED : STD_LOGIC; + signal NLW_DeserializerSlave_Q6_UNCONNECTED : STD_LOGIC; + signal NLW_DeserializerSlave_Q7_UNCONNECTED : STD_LOGIC; + signal NLW_DeserializerSlave_Q8_UNCONNECTED : STD_LOGIC; + signal NLW_DeserializerSlave_SHIFTOUT1_UNCONNECTED : STD_LOGIC; + signal NLW_DeserializerSlave_SHIFTOUT2_UNCONNECTED : STD_LOGIC; + attribute box_type : string; + attribute box_type of DeserializerMaster : label is "PRIMITIVE"; + attribute box_type of DeserializerSlave : label is "PRIMITIVE"; + attribute CAPACITANCE : string; + attribute CAPACITANCE of InputBuffer : label is "DONT_CARE"; + attribute IBUF_DELAY_VALUE : string; + attribute IBUF_DELAY_VALUE of InputBuffer : label is "0"; + attribute IFD_DELAY_VALUE : string; + attribute IFD_DELAY_VALUE of InputBuffer : label is "AUTO"; + attribute box_type of InputBuffer : label is "PRIMITIVE"; + attribute box_type of InputDelay : label is "PRIMITIVE"; +begin +DeserializerMaster: unisim.vcomponents.ISERDESE2 + generic map( + DATA_RATE => "DDR", + DATA_WIDTH => 10, + DYN_CLKDIV_INV_EN => "FALSE", + DYN_CLK_INV_EN => "FALSE", + INIT_Q1 => '0', + INIT_Q2 => '0', + INIT_Q3 => '0', + INIT_Q4 => '0', + INTERFACE_TYPE => "NETWORKING", + IOBDELAY => "IFD", + IS_CLKB_INVERTED => '1', + IS_CLKDIVP_INVERTED => '0', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D_INVERTED => '0', + IS_OCLKB_INVERTED => '0', + IS_OCLK_INVERTED => '0', + NUM_CE => 2, + OFB_USED => "FALSE", + SERDES_MODE => "MASTER", + SRVAL_Q1 => '0', + SRVAL_Q2 => '0', + SRVAL_Q3 => '0', + SRVAL_Q4 => '0' + ) + port map ( + BITSLIP => pBitslip, + CE1 => '1', + CE2 => '1', + CLK => \rMMCM_Reset_q_reg[0]\, + CLKB => CLKB, + CLKDIV => PixelClk_int, + CLKDIVP => '0', + D => '0', + DDLY => sDataInDly, + DYNCLKDIVSEL => '0', + DYNCLKSEL => '0', + O => NLW_DeserializerMaster_O_UNCONNECTED, + OCLK => '0', + OCLKB => '0', + OFB => '0', + Q1 => pDataInRaw(9), + Q2 => pDataInRaw(8), + Q3 => pDataInRaw(7), + Q4 => pDataInRaw(6), + Q5 => pDataInRaw(5), + Q6 => pDataInRaw(4), + Q7 => pDataInRaw(3), + Q8 => pDataInRaw(2), + RST => \out\(0), + SHIFTIN1 => '0', + SHIFTIN2 => '0', + SHIFTOUT1 => icascade1, + SHIFTOUT2 => icascade2 + ); +DeserializerSlave: unisim.vcomponents.ISERDESE2 + generic map( + DATA_RATE => "DDR", + DATA_WIDTH => 10, + DYN_CLKDIV_INV_EN => "FALSE", + DYN_CLK_INV_EN => "FALSE", + INIT_Q1 => '0', + INIT_Q2 => '0', + INIT_Q3 => '0', + INIT_Q4 => '0', + INTERFACE_TYPE => "NETWORKING", + IOBDELAY => "IFD", + IS_CLKB_INVERTED => '1', + IS_CLKDIVP_INVERTED => '0', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D_INVERTED => '0', + IS_OCLKB_INVERTED => '0', + IS_OCLK_INVERTED => '0', + NUM_CE => 2, + OFB_USED => "FALSE", + SERDES_MODE => "SLAVE", + SRVAL_Q1 => '0', + SRVAL_Q2 => '0', + SRVAL_Q3 => '0', + SRVAL_Q4 => '0' + ) + port map ( + BITSLIP => pBitslip, + CE1 => '1', + CE2 => '1', + CLK => \rMMCM_Reset_q_reg[0]\, + CLKB => CLKB, + CLKDIV => PixelClk_int, + CLKDIVP => '0', + D => '0', + DDLY => '0', + DYNCLKDIVSEL => '0', + DYNCLKSEL => '0', + O => NLW_DeserializerSlave_O_UNCONNECTED, + OCLK => '0', + OCLKB => '0', + OFB => '0', + Q1 => NLW_DeserializerSlave_Q1_UNCONNECTED, + Q2 => NLW_DeserializerSlave_Q2_UNCONNECTED, + Q3 => pDataInRaw(1), + Q4 => pDataInRaw(0), + Q5 => NLW_DeserializerSlave_Q5_UNCONNECTED, + Q6 => NLW_DeserializerSlave_Q6_UNCONNECTED, + Q7 => NLW_DeserializerSlave_Q7_UNCONNECTED, + Q8 => NLW_DeserializerSlave_Q8_UNCONNECTED, + RST => \out\(0), + SHIFTIN1 => icascade1, + SHIFTIN2 => icascade2, + SHIFTOUT1 => NLW_DeserializerSlave_SHIFTOUT1_UNCONNECTED, + SHIFTOUT2 => NLW_DeserializerSlave_SHIFTOUT2_UNCONNECTED + ); +InputBuffer: unisim.vcomponents.IBUFDS + generic map( + DQS_BIAS => "FALSE" + ) + port map ( + I => TMDS_Data_p(0), + IB => TMDS_Data_n(0), + O => sDataIn + ); +InputDelay: unisim.vcomponents.IDELAYE2 + generic map( + CINVCTRL_SEL => "FALSE", + DELAY_SRC => "IDATAIN", + HIGH_PERFORMANCE_MODE => "TRUE", + IDELAY_TYPE => "VARIABLE", + IDELAY_VALUE => 0, + IS_C_INVERTED => '0', + IS_DATAIN_INVERTED => '0', + IS_IDATAIN_INVERTED => '0', + PIPE_SEL => "FALSE", + REFCLK_FREQUENCY => 200.000000, + SIGNAL_PATTERN => "DATA" + ) + port map ( + C => PixelClk_int, + CE => pIDLY_CE, + CINVCTRL => '0', + CNTVALUEIN(4 downto 0) => B"00000", + CNTVALUEOUT(4 downto 0) => D(4 downto 0), + DATAIN => '0', + DATAOUT => sDataInDly, + IDATAIN => sDataIn, + INC => pIDLY_INC, + LD => pIDLY_LD, + LDPIPEEN => '0', + REGRST => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_InputSERDES_11 is + port ( + D : out STD_LOGIC_VECTOR ( 4 downto 0 ); + pDataInRaw : out STD_LOGIC_VECTOR ( 9 downto 0 ); + TMDS_Data_p : in STD_LOGIC_VECTOR ( 0 to 0 ); + TMDS_Data_n : in STD_LOGIC_VECTOR ( 0 to 0 ); + PixelClk_int : in STD_LOGIC; + pIDLY_CE : in STD_LOGIC; + pIDLY_INC : in STD_LOGIC; + pIDLY_LD : in STD_LOGIC; + pBitslip : in STD_LOGIC; + \rMMCM_Reset_q_reg[0]\ : in STD_LOGIC; + CLKB : in STD_LOGIC; + AS : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_InputSERDES_11 : entity is "InputSERDES"; +end Arty_Z7_20_dvi2rgb_0_0_InputSERDES_11; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_InputSERDES_11 is + signal icascade1 : STD_LOGIC; + signal icascade2 : STD_LOGIC; + signal sDataIn : STD_LOGIC; + signal sDataInDly : STD_LOGIC; + signal NLW_DeserializerMaster_O_UNCONNECTED : STD_LOGIC; + signal NLW_DeserializerSlave_O_UNCONNECTED : STD_LOGIC; + signal NLW_DeserializerSlave_Q1_UNCONNECTED : STD_LOGIC; + signal NLW_DeserializerSlave_Q2_UNCONNECTED : STD_LOGIC; + signal NLW_DeserializerSlave_Q5_UNCONNECTED : STD_LOGIC; + signal NLW_DeserializerSlave_Q6_UNCONNECTED : STD_LOGIC; + signal NLW_DeserializerSlave_Q7_UNCONNECTED : STD_LOGIC; + signal NLW_DeserializerSlave_Q8_UNCONNECTED : STD_LOGIC; + signal NLW_DeserializerSlave_SHIFTOUT1_UNCONNECTED : STD_LOGIC; + signal NLW_DeserializerSlave_SHIFTOUT2_UNCONNECTED : STD_LOGIC; + attribute box_type : string; + attribute box_type of DeserializerMaster : label is "PRIMITIVE"; + attribute box_type of DeserializerSlave : label is "PRIMITIVE"; + attribute CAPACITANCE : string; + attribute CAPACITANCE of InputBuffer : label is "DONT_CARE"; + attribute IBUF_DELAY_VALUE : string; + attribute IBUF_DELAY_VALUE of InputBuffer : label is "0"; + attribute IFD_DELAY_VALUE : string; + attribute IFD_DELAY_VALUE of InputBuffer : label is "AUTO"; + attribute box_type of InputBuffer : label is "PRIMITIVE"; + attribute box_type of InputDelay : label is "PRIMITIVE"; +begin +DeserializerMaster: unisim.vcomponents.ISERDESE2 + generic map( + DATA_RATE => "DDR", + DATA_WIDTH => 10, + DYN_CLKDIV_INV_EN => "FALSE", + DYN_CLK_INV_EN => "FALSE", + INIT_Q1 => '0', + INIT_Q2 => '0', + INIT_Q3 => '0', + INIT_Q4 => '0', + INTERFACE_TYPE => "NETWORKING", + IOBDELAY => "IFD", + IS_CLKB_INVERTED => '1', + IS_CLKDIVP_INVERTED => '0', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D_INVERTED => '0', + IS_OCLKB_INVERTED => '0', + IS_OCLK_INVERTED => '0', + NUM_CE => 2, + OFB_USED => "FALSE", + SERDES_MODE => "MASTER", + SRVAL_Q1 => '0', + SRVAL_Q2 => '0', + SRVAL_Q3 => '0', + SRVAL_Q4 => '0' + ) + port map ( + BITSLIP => pBitslip, + CE1 => '1', + CE2 => '1', + CLK => \rMMCM_Reset_q_reg[0]\, + CLKB => CLKB, + CLKDIV => PixelClk_int, + CLKDIVP => '0', + D => '0', + DDLY => sDataInDly, + DYNCLKDIVSEL => '0', + DYNCLKSEL => '0', + O => NLW_DeserializerMaster_O_UNCONNECTED, + OCLK => '0', + OCLKB => '0', + OFB => '0', + Q1 => pDataInRaw(9), + Q2 => pDataInRaw(8), + Q3 => pDataInRaw(7), + Q4 => pDataInRaw(6), + Q5 => pDataInRaw(5), + Q6 => pDataInRaw(4), + Q7 => pDataInRaw(3), + Q8 => pDataInRaw(2), + RST => AS(0), + SHIFTIN1 => '0', + SHIFTIN2 => '0', + SHIFTOUT1 => icascade1, + SHIFTOUT2 => icascade2 + ); +DeserializerSlave: unisim.vcomponents.ISERDESE2 + generic map( + DATA_RATE => "DDR", + DATA_WIDTH => 10, + DYN_CLKDIV_INV_EN => "FALSE", + DYN_CLK_INV_EN => "FALSE", + INIT_Q1 => '0', + INIT_Q2 => '0', + INIT_Q3 => '0', + INIT_Q4 => '0', + INTERFACE_TYPE => "NETWORKING", + IOBDELAY => "IFD", + IS_CLKB_INVERTED => '1', + IS_CLKDIVP_INVERTED => '0', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D_INVERTED => '0', + IS_OCLKB_INVERTED => '0', + IS_OCLK_INVERTED => '0', + NUM_CE => 2, + OFB_USED => "FALSE", + SERDES_MODE => "SLAVE", + SRVAL_Q1 => '0', + SRVAL_Q2 => '0', + SRVAL_Q3 => '0', + SRVAL_Q4 => '0' + ) + port map ( + BITSLIP => pBitslip, + CE1 => '1', + CE2 => '1', + CLK => \rMMCM_Reset_q_reg[0]\, + CLKB => CLKB, + CLKDIV => PixelClk_int, + CLKDIVP => '0', + D => '0', + DDLY => '0', + DYNCLKDIVSEL => '0', + DYNCLKSEL => '0', + O => NLW_DeserializerSlave_O_UNCONNECTED, + OCLK => '0', + OCLKB => '0', + OFB => '0', + Q1 => NLW_DeserializerSlave_Q1_UNCONNECTED, + Q2 => NLW_DeserializerSlave_Q2_UNCONNECTED, + Q3 => pDataInRaw(1), + Q4 => pDataInRaw(0), + Q5 => NLW_DeserializerSlave_Q5_UNCONNECTED, + Q6 => NLW_DeserializerSlave_Q6_UNCONNECTED, + Q7 => NLW_DeserializerSlave_Q7_UNCONNECTED, + Q8 => NLW_DeserializerSlave_Q8_UNCONNECTED, + RST => AS(0), + SHIFTIN1 => icascade1, + SHIFTIN2 => icascade2, + SHIFTOUT1 => NLW_DeserializerSlave_SHIFTOUT1_UNCONNECTED, + SHIFTOUT2 => NLW_DeserializerSlave_SHIFTOUT2_UNCONNECTED + ); +InputBuffer: unisim.vcomponents.IBUFDS + generic map( + DQS_BIAS => "FALSE" + ) + port map ( + I => TMDS_Data_p(0), + IB => TMDS_Data_n(0), + O => sDataIn + ); +InputDelay: unisim.vcomponents.IDELAYE2 + generic map( + CINVCTRL_SEL => "FALSE", + DELAY_SRC => "IDATAIN", + HIGH_PERFORMANCE_MODE => "TRUE", + IDELAY_TYPE => "VARIABLE", + IDELAY_VALUE => 0, + IS_C_INVERTED => '0', + IS_DATAIN_INVERTED => '0', + IS_IDATAIN_INVERTED => '0', + PIPE_SEL => "FALSE", + REFCLK_FREQUENCY => 200.000000, + SIGNAL_PATTERN => "DATA" + ) + port map ( + C => PixelClk_int, + CE => pIDLY_CE, + CINVCTRL => '0', + CNTVALUEIN(4 downto 0) => B"00000", + CNTVALUEOUT(4 downto 0) => D(4 downto 0), + DATAIN => '0', + DATAOUT => sDataInDly, + IDATAIN => sDataIn, + INC => pIDLY_INC, + LD => pIDLY_LD, + LDPIPEEN => '0', + REGRST => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_InputSERDES_18 is + port ( + D : out STD_LOGIC_VECTOR ( 4 downto 0 ); + pDataInRaw : out STD_LOGIC_VECTOR ( 9 downto 0 ); + TMDS_Data_p : in STD_LOGIC_VECTOR ( 0 to 0 ); + TMDS_Data_n : in STD_LOGIC_VECTOR ( 0 to 0 ); + PixelClk_int : in STD_LOGIC; + pIDLY_CE : in STD_LOGIC; + pIDLY_INC : in STD_LOGIC; + pIDLY_LD : in STD_LOGIC; + pBitslip : in STD_LOGIC; + \rMMCM_Reset_q_reg[0]\ : in STD_LOGIC; + CLKB : in STD_LOGIC; + AS : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_InputSERDES_18 : entity is "InputSERDES"; +end Arty_Z7_20_dvi2rgb_0_0_InputSERDES_18; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_InputSERDES_18 is + signal icascade1 : STD_LOGIC; + signal icascade2 : STD_LOGIC; + signal sDataIn : STD_LOGIC; + signal sDataInDly : STD_LOGIC; + signal NLW_DeserializerMaster_O_UNCONNECTED : STD_LOGIC; + signal NLW_DeserializerSlave_O_UNCONNECTED : STD_LOGIC; + signal NLW_DeserializerSlave_Q1_UNCONNECTED : STD_LOGIC; + signal NLW_DeserializerSlave_Q2_UNCONNECTED : STD_LOGIC; + signal NLW_DeserializerSlave_Q5_UNCONNECTED : STD_LOGIC; + signal NLW_DeserializerSlave_Q6_UNCONNECTED : STD_LOGIC; + signal NLW_DeserializerSlave_Q7_UNCONNECTED : STD_LOGIC; + signal NLW_DeserializerSlave_Q8_UNCONNECTED : STD_LOGIC; + signal NLW_DeserializerSlave_SHIFTOUT1_UNCONNECTED : STD_LOGIC; + signal NLW_DeserializerSlave_SHIFTOUT2_UNCONNECTED : STD_LOGIC; + attribute box_type : string; + attribute box_type of DeserializerMaster : label is "PRIMITIVE"; + attribute box_type of DeserializerSlave : label is "PRIMITIVE"; + attribute CAPACITANCE : string; + attribute CAPACITANCE of InputBuffer : label is "DONT_CARE"; + attribute IBUF_DELAY_VALUE : string; + attribute IBUF_DELAY_VALUE of InputBuffer : label is "0"; + attribute IFD_DELAY_VALUE : string; + attribute IFD_DELAY_VALUE of InputBuffer : label is "AUTO"; + attribute box_type of InputBuffer : label is "PRIMITIVE"; + attribute box_type of InputDelay : label is "PRIMITIVE"; +begin +DeserializerMaster: unisim.vcomponents.ISERDESE2 + generic map( + DATA_RATE => "DDR", + DATA_WIDTH => 10, + DYN_CLKDIV_INV_EN => "FALSE", + DYN_CLK_INV_EN => "FALSE", + INIT_Q1 => '0', + INIT_Q2 => '0', + INIT_Q3 => '0', + INIT_Q4 => '0', + INTERFACE_TYPE => "NETWORKING", + IOBDELAY => "IFD", + IS_CLKB_INVERTED => '1', + IS_CLKDIVP_INVERTED => '0', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D_INVERTED => '0', + IS_OCLKB_INVERTED => '0', + IS_OCLK_INVERTED => '0', + NUM_CE => 2, + OFB_USED => "FALSE", + SERDES_MODE => "MASTER", + SRVAL_Q1 => '0', + SRVAL_Q2 => '0', + SRVAL_Q3 => '0', + SRVAL_Q4 => '0' + ) + port map ( + BITSLIP => pBitslip, + CE1 => '1', + CE2 => '1', + CLK => \rMMCM_Reset_q_reg[0]\, + CLKB => CLKB, + CLKDIV => PixelClk_int, + CLKDIVP => '0', + D => '0', + DDLY => sDataInDly, + DYNCLKDIVSEL => '0', + DYNCLKSEL => '0', + O => NLW_DeserializerMaster_O_UNCONNECTED, + OCLK => '0', + OCLKB => '0', + OFB => '0', + Q1 => pDataInRaw(9), + Q2 => pDataInRaw(8), + Q3 => pDataInRaw(7), + Q4 => pDataInRaw(6), + Q5 => pDataInRaw(5), + Q6 => pDataInRaw(4), + Q7 => pDataInRaw(3), + Q8 => pDataInRaw(2), + RST => AS(0), + SHIFTIN1 => '0', + SHIFTIN2 => '0', + SHIFTOUT1 => icascade1, + SHIFTOUT2 => icascade2 + ); +DeserializerSlave: unisim.vcomponents.ISERDESE2 + generic map( + DATA_RATE => "DDR", + DATA_WIDTH => 10, + DYN_CLKDIV_INV_EN => "FALSE", + DYN_CLK_INV_EN => "FALSE", + INIT_Q1 => '0', + INIT_Q2 => '0', + INIT_Q3 => '0', + INIT_Q4 => '0', + INTERFACE_TYPE => "NETWORKING", + IOBDELAY => "IFD", + IS_CLKB_INVERTED => '1', + IS_CLKDIVP_INVERTED => '0', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D_INVERTED => '0', + IS_OCLKB_INVERTED => '0', + IS_OCLK_INVERTED => '0', + NUM_CE => 2, + OFB_USED => "FALSE", + SERDES_MODE => "SLAVE", + SRVAL_Q1 => '0', + SRVAL_Q2 => '0', + SRVAL_Q3 => '0', + SRVAL_Q4 => '0' + ) + port map ( + BITSLIP => pBitslip, + CE1 => '1', + CE2 => '1', + CLK => \rMMCM_Reset_q_reg[0]\, + CLKB => CLKB, + CLKDIV => PixelClk_int, + CLKDIVP => '0', + D => '0', + DDLY => '0', + DYNCLKDIVSEL => '0', + DYNCLKSEL => '0', + O => NLW_DeserializerSlave_O_UNCONNECTED, + OCLK => '0', + OCLKB => '0', + OFB => '0', + Q1 => NLW_DeserializerSlave_Q1_UNCONNECTED, + Q2 => NLW_DeserializerSlave_Q2_UNCONNECTED, + Q3 => pDataInRaw(1), + Q4 => pDataInRaw(0), + Q5 => NLW_DeserializerSlave_Q5_UNCONNECTED, + Q6 => NLW_DeserializerSlave_Q6_UNCONNECTED, + Q7 => NLW_DeserializerSlave_Q7_UNCONNECTED, + Q8 => NLW_DeserializerSlave_Q8_UNCONNECTED, + RST => AS(0), + SHIFTIN1 => icascade1, + SHIFTIN2 => icascade2, + SHIFTOUT1 => NLW_DeserializerSlave_SHIFTOUT1_UNCONNECTED, + SHIFTOUT2 => NLW_DeserializerSlave_SHIFTOUT2_UNCONNECTED + ); +InputBuffer: unisim.vcomponents.IBUFDS + generic map( + DQS_BIAS => "FALSE" + ) + port map ( + I => TMDS_Data_p(0), + IB => TMDS_Data_n(0), + O => sDataIn + ); +InputDelay: unisim.vcomponents.IDELAYE2 + generic map( + CINVCTRL_SEL => "FALSE", + DELAY_SRC => "IDATAIN", + HIGH_PERFORMANCE_MODE => "TRUE", + IDELAY_TYPE => "VARIABLE", + IDELAY_VALUE => 0, + IS_C_INVERTED => '0', + IS_DATAIN_INVERTED => '0', + IS_IDATAIN_INVERTED => '0', + PIPE_SEL => "FALSE", + REFCLK_FREQUENCY => 200.000000, + SIGNAL_PATTERN => "DATA" + ) + port map ( + C => PixelClk_int, + CE => pIDLY_CE, + CINVCTRL => '0', + CNTVALUEIN(4 downto 0) => B"00000", + CNTVALUEOUT(4 downto 0) => D(4 downto 0), + DATAIN => '0', + DATAOUT => sDataInDly, + IDATAIN => sDataIn, + INC => pIDLY_INC, + LD => pIDLY_LD, + LDPIPEEN => '0', + REGRST => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_PhaseAlign is + port ( + pIDLY_CE : out STD_LOGIC; + pIDLY_INC : out STD_LOGIC; + pIDLY_LD : out STD_LOGIC; + pVld_2 : out STD_LOGIC; + pAlignErr_q_reg : out STD_LOGIC; + iIn_q_reg : out STD_LOGIC; + pAllVldBgnFlag0 : out STD_LOGIC; + pBitslip_reg : out STD_LOGIC; + PixelClk_int : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + pVld_0 : in STD_LOGIC; + pVld_1 : in STD_LOGIC; + pAllVld_q : in STD_LOGIC; + pAlignErr_q : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 8 downto 0 ); + pIDLY_CE_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_PhaseAlign : entity is "PhaseAlign"; +end Arty_Z7_20_dvi2rgb_0_0_PhaseAlign; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_PhaseAlign is + signal iIn_q_i_2_n_0 : STD_LOGIC; + signal iIn_q_i_3_n_0 : STD_LOGIC; + signal iIn_q_i_4_n_0 : STD_LOGIC; + signal iIn_q_i_5_n_0 : STD_LOGIC; + signal \^palignerr_q_reg\ : STD_LOGIC; + signal pAligned : STD_LOGIC; + signal pBlankBegin : STD_LOGIC; + signal pBlankBegin0 : STD_LOGIC; + signal \pCenterTap[0]_i_1_n_0\ : STD_LOGIC; + signal \pCenterTap[1]_i_1_n_0\ : STD_LOGIC; + signal \pCenterTap[2]_i_1_n_0\ : STD_LOGIC; + signal \pCenterTap[3]_i_1_n_0\ : STD_LOGIC; + signal \pCenterTap[3]_i_2_n_0\ : STD_LOGIC; + signal \pCenterTap[4]_i_1_n_0\ : STD_LOGIC; + signal \pCenterTap[5]_i_1_n_0\ : STD_LOGIC; + signal \pCenterTap[5]_i_2_n_0\ : STD_LOGIC; + signal \pCenterTap[5]_i_3_n_0\ : STD_LOGIC; + signal \pCenterTap[5]_i_5_n_0\ : STD_LOGIC; + signal \pCenterTap_reg_n_0_[0]\ : STD_LOGIC; + signal \pCenterTap_reg_n_0_[1]\ : STD_LOGIC; + signal \pCenterTap_reg_n_0_[2]\ : STD_LOGIC; + signal \pCenterTap_reg_n_0_[3]\ : STD_LOGIC; + signal \pCenterTap_reg_n_0_[4]\ : STD_LOGIC; + signal \pCenterTap_reg_n_0_[5]\ : STD_LOGIC; + signal \pCtlTknCnt[6]_i_3_n_0\ : STD_LOGIC; + signal \pCtlTknCnt[6]_i_4_n_0\ : STD_LOGIC; + signal \pCtlTknCnt_reg__0\ : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal pCtlTknOvf_i_1_n_0 : STD_LOGIC; + signal pCtlTknOvf_i_2_n_0 : STD_LOGIC; + signal pCtlTknOvf_reg_n_0 : STD_LOGIC; + signal pCtlTknRst : STD_LOGIC; + signal pDataQ : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal pDelayCenter : STD_LOGIC; + signal pDelayCenter_i_1_n_0 : STD_LOGIC; + signal pDelayCenter_i_2_n_0 : STD_LOGIC; + signal pDelayOvf : STD_LOGIC; + signal pDelayOvf_i_1_n_0 : STD_LOGIC; + signal pDelayWaitCnt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \pDelayWaitCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \pDelayWaitCnt[0]_i_2_n_0\ : STD_LOGIC; + signal \pDelayWaitCnt[1]_i_1_n_0\ : STD_LOGIC; + signal pDelayWaitOvf : STD_LOGIC; + signal pDelayWaitOvf_i_1_n_0 : STD_LOGIC; + signal pDelayWaitOvf_i_2_n_0 : STD_LOGIC; + signal pDelayWaitOvf_i_3_n_0 : STD_LOGIC; + signal pError : STD_LOGIC; + signal \pEyeOpenCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \pEyeOpenCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \pEyeOpenCnt[2]_i_1_n_0\ : STD_LOGIC; + signal \pEyeOpenCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \pEyeOpenCnt[4]_i_1_n_0\ : STD_LOGIC; + signal \pEyeOpenCnt[4]_i_2_n_0\ : STD_LOGIC; + signal \pEyeOpenCnt[4]_i_3_n_0\ : STD_LOGIC; + signal \pEyeOpenCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \pEyeOpenCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \pEyeOpenCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \pEyeOpenCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \pEyeOpenCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \pEyeOpenEn__5\ : STD_LOGIC; + signal pEyeOpenRst : STD_LOGIC; + signal pFoundEyeFlag : STD_LOGIC; + signal pFoundEyeFlag_i_1_n_0 : STD_LOGIC; + signal pFoundEyeFlag_i_2_n_0 : STD_LOGIC; + signal pFoundEyeFlag_i_3_n_0 : STD_LOGIC; + signal pFoundEyeFlag_i_4_n_0 : STD_LOGIC; + signal pFoundJtrFlag : STD_LOGIC; + signal pFoundJtrFlag_i_1_n_0 : STD_LOGIC; + signal pIDLY_CE_1 : STD_LOGIC; + signal \pIDLY_CNT_Q_reg_n_0_[0]\ : STD_LOGIC; + signal \pIDLY_CNT_Q_reg_n_0_[1]\ : STD_LOGIC; + signal \pIDLY_CNT_Q_reg_n_0_[2]\ : STD_LOGIC; + signal \pIDLY_CNT_Q_reg_n_0_[3]\ : STD_LOGIC; + signal \pIDLY_CNT_Q_reg_n_0_[4]\ : STD_LOGIC; + signal \^pidly_inc\ : STD_LOGIC; + signal pIDLY_INC_i_1_n_0 : STD_LOGIC; + signal pIDLY_LD_0 : STD_LOGIC; + signal pIDLY_LD_i_2_n_0 : STD_LOGIC; + signal pState : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal \pStateNxt__0_n_0\ : STD_LOGIC; + signal \pStateNxt__1_n_0\ : STD_LOGIC; + signal \pStateNxt__2_n_0\ : STD_LOGIC; + signal \pStateNxt__3_n_0\ : STD_LOGIC; + signal \pStateNxt__4\ : STD_LOGIC; + signal pStateNxt_n_0 : STD_LOGIC; + signal \pState[0]_i_1_n_0\ : STD_LOGIC; + signal \pState[10]_i_2_n_0\ : STD_LOGIC; + signal \pState[10]_i_3_n_0\ : STD_LOGIC; + signal \pState[10]_i_4_n_0\ : STD_LOGIC; + signal \pState[10]_i_5_n_0\ : STD_LOGIC; + signal \pState[10]_i_6_n_0\ : STD_LOGIC; + signal \pState[1]_i_1_n_0\ : STD_LOGIC; + signal \pState[2]_i_1_n_0\ : STD_LOGIC; + signal \pState[3]_i_1_n_0\ : STD_LOGIC; + signal \pState[4]_i_1_n_0\ : STD_LOGIC; + signal \pState[5]_i_1_n_0\ : STD_LOGIC; + signal \pState[5]_i_2_n_0\ : STD_LOGIC; + signal \pState[6]_i_1_n_0\ : STD_LOGIC; + signal \pState[7]_i_1_n_0\ : STD_LOGIC; + signal \pState[8]_i_1_n_0\ : STD_LOGIC; + signal \pState[9]_i_1_n_0\ : STD_LOGIC; + signal pTknFlag : STD_LOGIC; + signal pTknFlag0 : STD_LOGIC; + signal pTknFlagQ : STD_LOGIC; + signal pTknFlag_i_2_n_0 : STD_LOGIC; + signal pTknFlag_i_3_n_0 : STD_LOGIC; + signal \^pvld_2\ : STD_LOGIC; + signal p_0_in : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal p_2_in : STD_LOGIC; + signal \plusOp__16\ : STD_LOGIC_VECTOR ( 5 downto 4 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of iIn_q_i_2 : label is "soft_lutpair67"; + attribute SOFT_HLUTNM of iIn_q_i_3 : label is "soft_lutpair69"; + attribute SOFT_HLUTNM of iIn_q_i_4 : label is "soft_lutpair75"; + attribute SOFT_HLUTNM of iIn_q_i_5 : label is "soft_lutpair78"; + attribute SOFT_HLUTNM of pAligned_i_1 : label is "soft_lutpair71"; + attribute SOFT_HLUTNM of \pCenterTap[3]_i_2\ : label is "soft_lutpair64"; + attribute SOFT_HLUTNM of \pCenterTap[4]_i_2\ : label is "soft_lutpair64"; + attribute SOFT_HLUTNM of \pCtlTknCnt[0]_i_1\ : label is "soft_lutpair79"; + attribute SOFT_HLUTNM of \pCtlTknCnt[1]_i_1\ : label is "soft_lutpair79"; + attribute SOFT_HLUTNM of \pCtlTknCnt[2]_i_1\ : label is "soft_lutpair73"; + attribute SOFT_HLUTNM of \pCtlTknCnt[3]_i_1\ : label is "soft_lutpair73"; + attribute SOFT_HLUTNM of \pCtlTknCnt[4]_i_1\ : label is "soft_lutpair66"; + attribute SOFT_HLUTNM of \pCtlTknCnt[6]_i_2\ : label is "soft_lutpair72"; + attribute SOFT_HLUTNM of \pCtlTknCnt[6]_i_4\ : label is "soft_lutpair66"; + attribute SOFT_HLUTNM of pCtlTknOvf_i_2 : label is "soft_lutpair72"; + attribute SOFT_HLUTNM of \pDelayWaitCnt[1]_i_1\ : label is "soft_lutpair74"; + attribute SOFT_HLUTNM of pDelayWaitOvf_i_2 : label is "soft_lutpair76"; + attribute SOFT_HLUTNM of pDelayWaitOvf_i_3 : label is "soft_lutpair74"; + attribute SOFT_HLUTNM of pError_i_1 : label is "soft_lutpair71"; + attribute SOFT_HLUTNM of \pEyeOpenCnt[1]_i_1\ : label is "soft_lutpair61"; + attribute SOFT_HLUTNM of \pEyeOpenCnt[2]_i_1\ : label is "soft_lutpair61"; + attribute SOFT_HLUTNM of \pEyeOpenCnt[4]_i_4\ : label is "soft_lutpair63"; + attribute SOFT_HLUTNM of pFoundEyeFlag_i_4 : label is "soft_lutpair70"; + attribute SOFT_HLUTNM of pFoundJtrFlag_i_1 : label is "soft_lutpair67"; + attribute SOFT_HLUTNM of pIDLY_LD_i_1 : label is "soft_lutpair63"; + attribute SOFT_HLUTNM of pIDLY_LD_i_2 : label is "soft_lutpair69"; + attribute SOFT_HLUTNM of pStateNxt : label is "soft_lutpair68"; + attribute SOFT_HLUTNM of \pStateNxt__0\ : label is "soft_lutpair68"; + attribute SOFT_HLUTNM of \pState[10]_i_2\ : label is "soft_lutpair76"; + attribute SOFT_HLUTNM of \pState[10]_i_3\ : label is "soft_lutpair75"; + attribute SOFT_HLUTNM of \pState[2]_i_1\ : label is "soft_lutpair65"; + attribute SOFT_HLUTNM of \pState[3]_i_1\ : label is "soft_lutpair77"; + attribute SOFT_HLUTNM of \pState[4]_i_1\ : label is "soft_lutpair65"; + attribute SOFT_HLUTNM of \pState[5]_i_2\ : label is "soft_lutpair70"; + attribute SOFT_HLUTNM of \pState[6]_i_1\ : label is "soft_lutpair78"; + attribute SOFT_HLUTNM of \pState[7]_i_1\ : label is "soft_lutpair62"; + attribute SOFT_HLUTNM of \pState[8]_i_1\ : label is "soft_lutpair77"; + attribute SOFT_HLUTNM of \pState[9]_i_1\ : label is "soft_lutpair62"; +begin + pAlignErr_q_reg <= \^palignerr_q_reg\; + pIDLY_INC <= \^pidly_inc\; + pVld_2 <= \^pvld_2\; +iIn_q_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFEFFFEFFFF" + ) + port map ( + I0 => iIn_q_i_2_n_0, + I1 => iIn_q_i_3_n_0, + I2 => iIn_q_i_4_n_0, + I3 => iIn_q_i_5_n_0, + I4 => pState(1), + I5 => pState(2), + O => iIn_q_reg + ); +iIn_q_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => pState(4), + I1 => pState(0), + I2 => pState(3), + O => iIn_q_i_2_n_0 + ); +iIn_q_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => pState(6), + I1 => pState(8), + O => iIn_q_i_3_n_0 + ); +iIn_q_i_4: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => pState(9), + I1 => pState(10), + O => iIn_q_i_4_n_0 + ); +iIn_q_i_5: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => pState(5), + I1 => pState(7), + O => iIn_q_i_5_n_0 + ); +pAligned_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"0004" + ) + port map ( + I0 => pState(2), + I1 => pState(9), + I2 => pState(10), + I3 => \pCtlTknCnt[6]_i_3_n_0\, + O => pAligned + ); +pAligned_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pAligned, + Q => \^pvld_2\, + R => '0' + ); +pAllVldBgnFlag_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"0080" + ) + port map ( + I0 => pVld_0, + I1 => \^pvld_2\, + I2 => pVld_1, + I3 => pAllVld_q, + O => pAllVldBgnFlag0 + ); +pBitslip_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^palignerr_q_reg\, + I1 => pAlignErr_q, + O => pBitslip_reg + ); +pBlankBegin_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => pTknFlag, + I1 => pTknFlagQ, + O => pBlankBegin0 + ); +pBlankBegin_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pBlankBegin0, + Q => pBlankBegin, + R => '0' + ); +\pCenterTap[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAA5AAAAAFBA" + ) + port map ( + I0 => \pCenterTap_reg_n_0_[0]\, + I1 => pFoundEyeFlag, + I2 => pState(4), + I3 => pState(0), + I4 => \pCenterTap[5]_i_3_n_0\, + I5 => pState(3), + O => \pCenterTap[0]_i_1_n_0\ + ); +\pCenterTap[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FF606060" + ) + port map ( + I0 => \pCenterTap_reg_n_0_[0]\, + I1 => \pCenterTap_reg_n_0_[1]\, + I2 => \pCenterTap[5]_i_5_n_0\, + I3 => \pIDLY_CNT_Q_reg_n_0_[0]\, + I4 => pEyeOpenRst, + O => \pCenterTap[1]_i_1_n_0\ + ); +\pCenterTap[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF780078007800" + ) + port map ( + I0 => \pCenterTap_reg_n_0_[1]\, + I1 => \pCenterTap_reg_n_0_[0]\, + I2 => \pCenterTap_reg_n_0_[2]\, + I3 => \pCenterTap[5]_i_5_n_0\, + I4 => \pIDLY_CNT_Q_reg_n_0_[1]\, + I5 => pEyeOpenRst, + O => \pCenterTap[2]_i_1_n_0\ + ); +\pCenterTap[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF780078007800" + ) + port map ( + I0 => \pCenterTap_reg_n_0_[2]\, + I1 => \pCenterTap[3]_i_2_n_0\, + I2 => \pCenterTap_reg_n_0_[3]\, + I3 => \pCenterTap[5]_i_5_n_0\, + I4 => \pIDLY_CNT_Q_reg_n_0_[2]\, + I5 => pEyeOpenRst, + O => \pCenterTap[3]_i_1_n_0\ + ); +\pCenterTap[3]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \pCenterTap_reg_n_0_[0]\, + I1 => \pCenterTap_reg_n_0_[1]\, + O => \pCenterTap[3]_i_2_n_0\ + ); +\pCenterTap[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F888" + ) + port map ( + I0 => \plusOp__16\(4), + I1 => \pCenterTap[5]_i_5_n_0\, + I2 => \pIDLY_CNT_Q_reg_n_0_[3]\, + I3 => pEyeOpenRst, + O => \pCenterTap[4]_i_1_n_0\ + ); +\pCenterTap[4]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \pCenterTap_reg_n_0_[0]\, + I1 => \pCenterTap_reg_n_0_[1]\, + I2 => \pCenterTap_reg_n_0_[2]\, + I3 => \pCenterTap_reg_n_0_[3]\, + I4 => \pCenterTap_reg_n_0_[4]\, + O => \plusOp__16\(4) + ); +\pCenterTap[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00030034" + ) + port map ( + I0 => pFoundEyeFlag, + I1 => pState(4), + I2 => pState(0), + I3 => \pCenterTap[5]_i_3_n_0\, + I4 => pState(3), + O => \pCenterTap[5]_i_1_n_0\ + ); +\pCenterTap[5]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F888" + ) + port map ( + I0 => \plusOp__16\(5), + I1 => \pCenterTap[5]_i_5_n_0\, + I2 => \pIDLY_CNT_Q_reg_n_0_[4]\, + I3 => pEyeOpenRst, + O => \pCenterTap[5]_i_2_n_0\ + ); +\pCenterTap[5]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => pState(5), + I1 => pState(7), + I2 => pState(8), + I3 => pState(6), + I4 => pState(1), + I5 => \pState[10]_i_3_n_0\, + O => \pCenterTap[5]_i_3_n_0\ + ); +\pCenterTap[5]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFFFFFF80000000" + ) + port map ( + I0 => \pCenterTap_reg_n_0_[0]\, + I1 => \pCenterTap_reg_n_0_[1]\, + I2 => \pCenterTap_reg_n_0_[4]\, + I3 => \pCenterTap_reg_n_0_[3]\, + I4 => \pCenterTap_reg_n_0_[2]\, + I5 => \pCenterTap_reg_n_0_[5]\, + O => \plusOp__16\(5) + ); +\pCenterTap[5]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFEFFFAFFFF" + ) + port map ( + I0 => pState(3), + I1 => pFoundEyeFlag, + I2 => pIDLY_LD_i_2_n_0, + I3 => \pState[10]_i_3_n_0\, + I4 => pState(0), + I5 => pState(4), + O => \pCenterTap[5]_i_5_n_0\ + ); +\pCenterTap[5]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000010000010100" + ) + port map ( + I0 => pState(3), + I1 => pIDLY_LD_i_2_n_0, + I2 => \pState[10]_i_3_n_0\, + I3 => pState(0), + I4 => pState(4), + I5 => pFoundEyeFlag, + O => pEyeOpenRst + ); +\pCenterTap_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pCenterTap[0]_i_1_n_0\, + Q => \pCenterTap_reg_n_0_[0]\, + R => '0' + ); +\pCenterTap_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pCenterTap[5]_i_1_n_0\, + D => \pCenterTap[1]_i_1_n_0\, + Q => \pCenterTap_reg_n_0_[1]\, + R => '0' + ); +\pCenterTap_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pCenterTap[5]_i_1_n_0\, + D => \pCenterTap[2]_i_1_n_0\, + Q => \pCenterTap_reg_n_0_[2]\, + R => '0' + ); +\pCenterTap_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pCenterTap[5]_i_1_n_0\, + D => \pCenterTap[3]_i_1_n_0\, + Q => \pCenterTap_reg_n_0_[3]\, + R => '0' + ); +\pCenterTap_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pCenterTap[5]_i_1_n_0\, + D => \pCenterTap[4]_i_1_n_0\, + Q => \pCenterTap_reg_n_0_[4]\, + R => '0' + ); +\pCenterTap_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pCenterTap[5]_i_1_n_0\, + D => \pCenterTap[5]_i_2_n_0\, + Q => \pCenterTap_reg_n_0_[5]\, + R => '0' + ); +\pCtlTknCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \pCtlTknCnt_reg__0\(0), + O => p_0_in(0) + ); +\pCtlTknCnt[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \pCtlTknCnt_reg__0\(0), + I1 => \pCtlTknCnt_reg__0\(1), + O => p_0_in(1) + ); +\pCtlTknCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \pCtlTknCnt_reg__0\(1), + I1 => \pCtlTknCnt_reg__0\(0), + I2 => \pCtlTknCnt_reg__0\(2), + O => p_0_in(2) + ); +\pCtlTknCnt[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \pCtlTknCnt_reg__0\(2), + I1 => \pCtlTknCnt_reg__0\(0), + I2 => \pCtlTknCnt_reg__0\(1), + I3 => \pCtlTknCnt_reg__0\(3), + O => p_0_in(3) + ); +\pCtlTknCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \pCtlTknCnt_reg__0\(3), + I1 => \pCtlTknCnt_reg__0\(1), + I2 => \pCtlTknCnt_reg__0\(0), + I3 => \pCtlTknCnt_reg__0\(2), + I4 => \pCtlTknCnt_reg__0\(4), + O => p_0_in(4) + ); +\pCtlTknCnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFFFFFF80000000" + ) + port map ( + I0 => \pCtlTknCnt_reg__0\(4), + I1 => \pCtlTknCnt_reg__0\(2), + I2 => \pCtlTknCnt_reg__0\(0), + I3 => \pCtlTknCnt_reg__0\(1), + I4 => \pCtlTknCnt_reg__0\(3), + I5 => \pCtlTknCnt_reg__0\(5), + O => p_0_in(5) + ); +\pCtlTknCnt[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFD" + ) + port map ( + I0 => pState(2), + I1 => pState(9), + I2 => pState(10), + I3 => \pCtlTknCnt[6]_i_3_n_0\, + O => pCtlTknRst + ); +\pCtlTknCnt[6]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \pCtlTknCnt[6]_i_4_n_0\, + I1 => \pCtlTknCnt_reg__0\(4), + I2 => \pCtlTknCnt_reg__0\(5), + I3 => \pCtlTknCnt_reg__0\(6), + O => p_0_in(6) + ); +\pCtlTknCnt[6]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => iIn_q_i_2_n_0, + I1 => pState(5), + I2 => pState(7), + I3 => pState(8), + I4 => pState(6), + I5 => pState(1), + O => \pCtlTknCnt[6]_i_3_n_0\ + ); +\pCtlTknCnt[6]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => \pCtlTknCnt_reg__0\(2), + I1 => \pCtlTknCnt_reg__0\(0), + I2 => \pCtlTknCnt_reg__0\(1), + I3 => \pCtlTknCnt_reg__0\(3), + O => \pCtlTknCnt[6]_i_4_n_0\ + ); +\pCtlTknCnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_in(0), + Q => \pCtlTknCnt_reg__0\(0), + R => pCtlTknRst + ); +\pCtlTknCnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_in(1), + Q => \pCtlTknCnt_reg__0\(1), + R => pCtlTknRst + ); +\pCtlTknCnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_in(2), + Q => \pCtlTknCnt_reg__0\(2), + R => pCtlTknRst + ); +\pCtlTknCnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_in(3), + Q => \pCtlTknCnt_reg__0\(3), + R => pCtlTknRst + ); +\pCtlTknCnt_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_in(4), + Q => \pCtlTknCnt_reg__0\(4), + R => pCtlTknRst + ); +\pCtlTknCnt_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_in(5), + Q => \pCtlTknCnt_reg__0\(5), + R => pCtlTknRst + ); +\pCtlTknCnt_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_in(6), + Q => \pCtlTknCnt_reg__0\(6), + R => pCtlTknRst + ); +pCtlTknOvf_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAEAAAAAAA2" + ) + port map ( + I0 => pCtlTknOvf_reg_n_0, + I1 => pState(2), + I2 => pState(9), + I3 => pState(10), + I4 => \pCtlTknCnt[6]_i_3_n_0\, + I5 => pCtlTknOvf_i_2_n_0, + O => pCtlTknOvf_i_1_n_0 + ); +pCtlTknOvf_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => \pCtlTknCnt_reg__0\(4), + I1 => \pCtlTknCnt_reg__0\(5), + I2 => \pCtlTknCnt_reg__0\(6), + I3 => \pCtlTknCnt[6]_i_4_n_0\, + O => pCtlTknOvf_i_2_n_0 + ); +pCtlTknOvf_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pCtlTknOvf_i_1_n_0, + Q => pCtlTknOvf_reg_n_0, + R => '0' + ); +\pDataQ_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => D(0), + Q => pDataQ(0), + R => '0' + ); +\pDataQ_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => D(1), + Q => pDataQ(1), + R => '0' + ); +\pDataQ_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => D(2), + Q => pDataQ(2), + R => '0' + ); +\pDataQ_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => D(3), + Q => pDataQ(3), + R => '0' + ); +\pDataQ_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => D(4), + Q => pDataQ(4), + R => '0' + ); +\pDataQ_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => D(5), + Q => pDataQ(5), + R => '0' + ); +\pDataQ_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => D(6), + Q => pDataQ(6), + R => '0' + ); +\pDataQ_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => D(7), + Q => pDataQ(7), + R => '0' + ); +\pDataQ_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => D(8), + Q => pDataQ(8), + R => '0' + ); +pDelayCenter_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"82000082" + ) + port map ( + I0 => pDelayCenter_i_2_n_0, + I1 => \pCenterTap_reg_n_0_[5]\, + I2 => \pIDLY_CNT_Q_reg_n_0_[4]\, + I3 => \pCenterTap_reg_n_0_[4]\, + I4 => \pIDLY_CNT_Q_reg_n_0_[3]\, + O => pDelayCenter_i_1_n_0 + ); +pDelayCenter_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \pCenterTap_reg_n_0_[3]\, + I1 => \pIDLY_CNT_Q_reg_n_0_[2]\, + I2 => \pCenterTap_reg_n_0_[2]\, + I3 => \pIDLY_CNT_Q_reg_n_0_[1]\, + I4 => \pIDLY_CNT_Q_reg_n_0_[0]\, + I5 => \pCenterTap_reg_n_0_[1]\, + O => pDelayCenter_i_2_n_0 + ); +pDelayCenter_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pDelayCenter_i_1_n_0, + Q => pDelayCenter, + R => '0' + ); +pDelayOvf_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000001" + ) + port map ( + I0 => \pIDLY_CNT_Q_reg_n_0_[0]\, + I1 => \pIDLY_CNT_Q_reg_n_0_[1]\, + I2 => \pIDLY_CNT_Q_reg_n_0_[2]\, + I3 => \pIDLY_CNT_Q_reg_n_0_[4]\, + I4 => \pIDLY_CNT_Q_reg_n_0_[3]\, + O => pDelayOvf_i_1_n_0 + ); +pDelayOvf_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pDelayOvf_i_1_n_0, + Q => pDelayOvf, + R => '0' + ); +\pDelayWaitCnt[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000001400000000" + ) + port map ( + I0 => pDelayWaitCnt(0), + I1 => pState(6), + I2 => pState(8), + I3 => iIn_q_i_5_n_0, + I4 => pState(1), + I5 => \pDelayWaitCnt[0]_i_2_n_0\, + O => \pDelayWaitCnt[0]_i_1_n_0\ + ); +\pDelayWaitCnt[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000001" + ) + port map ( + I0 => pState(3), + I1 => pState(0), + I2 => pState(4), + I3 => pState(2), + I4 => pState(9), + I5 => pState(10), + O => \pDelayWaitCnt[0]_i_2_n_0\ + ); +\pDelayWaitCnt[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"60" + ) + port map ( + I0 => pDelayWaitCnt(1), + I1 => pDelayWaitCnt(0), + I2 => p_2_in, + O => \pDelayWaitCnt[1]_i_1_n_0\ + ); +\pDelayWaitCnt[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000600000000" + ) + port map ( + I0 => pState(6), + I1 => pState(8), + I2 => pState(7), + I3 => pState(5), + I4 => pState(1), + I5 => \pDelayWaitCnt[0]_i_2_n_0\, + O => p_2_in + ); +\pDelayWaitCnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pDelayWaitCnt[0]_i_1_n_0\, + Q => pDelayWaitCnt(0), + R => '0' + ); +\pDelayWaitCnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pDelayWaitCnt[1]_i_1_n_0\, + Q => pDelayWaitCnt(1), + R => '0' + ); +pDelayWaitOvf_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"CCFCCCCCCC8CCCCC" + ) + port map ( + I0 => pState(1), + I1 => pDelayWaitOvf, + I2 => \pDelayWaitCnt[0]_i_2_n_0\, + I3 => iIn_q_i_5_n_0, + I4 => pDelayWaitOvf_i_2_n_0, + I5 => pDelayWaitOvf_i_3_n_0, + O => pDelayWaitOvf_i_1_n_0 + ); +pDelayWaitOvf_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => pState(6), + I1 => pState(8), + O => pDelayWaitOvf_i_2_n_0 + ); +pDelayWaitOvf_i_3: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => pState(1), + I1 => pDelayWaitCnt(1), + I2 => pDelayWaitCnt(0), + O => pDelayWaitOvf_i_3_n_0 + ); +pDelayWaitOvf_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pDelayWaitOvf_i_1_n_0, + Q => pDelayWaitOvf, + R => '0' + ); +pError_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"0004" + ) + port map ( + I0 => pState(2), + I1 => pState(10), + I2 => pState(9), + I3 => \pCtlTknCnt[6]_i_3_n_0\, + O => pError + ); +pError_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pError, + Q => \^palignerr_q_reg\, + R => '0' + ); +\pEyeOpenCnt[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CCCCCCCCCCC3C80C" + ) + port map ( + I0 => pFoundEyeFlag, + I1 => \pEyeOpenCnt_reg_n_0_[0]\, + I2 => pState(0), + I3 => pState(4), + I4 => pState(3), + I5 => \pCenterTap[5]_i_3_n_0\, + O => \pEyeOpenCnt[0]_i_1_n_0\ + ); +\pEyeOpenCnt[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BCA0" + ) + port map ( + I0 => \pEyeOpenCnt[4]_i_2_n_0\, + I1 => \pEyeOpenCnt_reg_n_0_[0]\, + I2 => \pEyeOpenCnt_reg_n_0_[1]\, + I3 => \pEyeOpenEn__5\, + O => \pEyeOpenCnt[1]_i_1_n_0\ + ); +\pEyeOpenCnt[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFC0AA00" + ) + port map ( + I0 => \pEyeOpenCnt[4]_i_2_n_0\, + I1 => \pEyeOpenCnt_reg_n_0_[1]\, + I2 => \pEyeOpenCnt_reg_n_0_[0]\, + I3 => \pEyeOpenCnt_reg_n_0_[2]\, + I4 => \pEyeOpenEn__5\, + O => \pEyeOpenCnt[2]_i_1_n_0\ + ); +\pEyeOpenCnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BFFFC000AAAA0000" + ) + port map ( + I0 => \pEyeOpenCnt[4]_i_2_n_0\, + I1 => \pEyeOpenCnt_reg_n_0_[0]\, + I2 => \pEyeOpenCnt_reg_n_0_[1]\, + I3 => \pEyeOpenCnt_reg_n_0_[2]\, + I4 => \pEyeOpenCnt_reg_n_0_[3]\, + I5 => \pEyeOpenEn__5\, + O => \pEyeOpenCnt[3]_i_1_n_0\ + ); +\pEyeOpenCnt[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BFFFC000AAAA0000" + ) + port map ( + I0 => \pEyeOpenCnt[4]_i_2_n_0\, + I1 => \pEyeOpenCnt_reg_n_0_[2]\, + I2 => \pEyeOpenCnt_reg_n_0_[3]\, + I3 => \pEyeOpenCnt[4]_i_3_n_0\, + I4 => \pEyeOpenCnt_reg_n_0_[4]\, + I5 => \pEyeOpenEn__5\, + O => \pEyeOpenCnt[4]_i_1_n_0\ + ); +\pEyeOpenCnt[4]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFEFFFCFFF3" + ) + port map ( + I0 => pFoundEyeFlag, + I1 => pState(3), + I2 => pIDLY_LD_i_2_n_0, + I3 => \pState[10]_i_3_n_0\, + I4 => pState(0), + I5 => pState(4), + O => \pEyeOpenCnt[4]_i_2_n_0\ + ); +\pEyeOpenCnt[4]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \pEyeOpenCnt_reg_n_0_[0]\, + I1 => \pEyeOpenCnt_reg_n_0_[1]\, + O => \pEyeOpenCnt[4]_i_3_n_0\ + ); +\pEyeOpenCnt[4]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000010" + ) + port map ( + I0 => pState(0), + I1 => pState(4), + I2 => pState(3), + I3 => \pState[10]_i_3_n_0\, + I4 => pIDLY_LD_i_2_n_0, + O => \pEyeOpenEn__5\ + ); +\pEyeOpenCnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pEyeOpenCnt[0]_i_1_n_0\, + Q => \pEyeOpenCnt_reg_n_0_[0]\, + R => '0' + ); +\pEyeOpenCnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pEyeOpenCnt[1]_i_1_n_0\, + Q => \pEyeOpenCnt_reg_n_0_[1]\, + R => '0' + ); +\pEyeOpenCnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pEyeOpenCnt[2]_i_1_n_0\, + Q => \pEyeOpenCnt_reg_n_0_[2]\, + R => '0' + ); +\pEyeOpenCnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pEyeOpenCnt[3]_i_1_n_0\, + Q => \pEyeOpenCnt_reg_n_0_[3]\, + R => '0' + ); +\pEyeOpenCnt_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pEyeOpenCnt[4]_i_1_n_0\, + Q => \pEyeOpenCnt_reg_n_0_[4]\, + R => '0' + ); +pFoundEyeFlag_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"ABBBA888" + ) + port map ( + I0 => pFoundEyeFlag_i_2_n_0, + I1 => pIDLY_LD_0, + I2 => \pEyeOpenEn__5\, + I3 => pFoundEyeFlag_i_3_n_0, + I4 => pFoundEyeFlag, + O => pFoundEyeFlag_i_1_n_0 + ); +pFoundEyeFlag_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"1000004000000040" + ) + port map ( + I0 => pFoundEyeFlag_i_4_n_0, + I1 => \pEyeOpenCnt_reg_n_0_[4]\, + I2 => pState(3), + I3 => \pEyeOpenCnt_reg_n_0_[0]\, + I4 => \pEyeOpenCnt_reg_n_0_[1]\, + I5 => pFoundJtrFlag, + O => pFoundEyeFlag_i_2_n_0 + ); +pFoundEyeFlag_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"0100001000000010" + ) + port map ( + I0 => \pEyeOpenCnt_reg_n_0_[2]\, + I1 => \pEyeOpenCnt_reg_n_0_[3]\, + I2 => \pEyeOpenCnt_reg_n_0_[4]\, + I3 => \pEyeOpenCnt_reg_n_0_[0]\, + I4 => \pEyeOpenCnt_reg_n_0_[1]\, + I5 => pFoundJtrFlag, + O => pFoundEyeFlag_i_3_n_0 + ); +pFoundEyeFlag_i_4: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \pEyeOpenCnt_reg_n_0_[2]\, + I1 => \pEyeOpenCnt_reg_n_0_[3]\, + O => pFoundEyeFlag_i_4_n_0 + ); +pFoundEyeFlag_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pFoundEyeFlag_i_1_n_0, + Q => pFoundEyeFlag, + R => '0' + ); +pFoundJtrFlag_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FEFF0010" + ) + port map ( + I0 => pState(3), + I1 => \pCenterTap[5]_i_3_n_0\, + I2 => pState(4), + I3 => pState(0), + I4 => pFoundJtrFlag, + O => pFoundJtrFlag_i_1_n_0 + ); +pFoundJtrFlag_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pFoundJtrFlag_i_1_n_0, + Q => pFoundJtrFlag, + R => '0' + ); +pIDLY_CE_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000200020000" + ) + port map ( + I0 => \pDelayWaitCnt[0]_i_2_n_0\, + I1 => pState(1), + I2 => pState(6), + I3 => pState(8), + I4 => pState(5), + I5 => pState(7), + O => pIDLY_CE_1 + ); +pIDLY_CE_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pIDLY_CE_1, + Q => pIDLY_CE, + R => '0' + ); +\pIDLY_CNT_Q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pIDLY_CE_reg_0(0), + Q => \pIDLY_CNT_Q_reg_n_0_[0]\, + R => '0' + ); +\pIDLY_CNT_Q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pIDLY_CE_reg_0(1), + Q => \pIDLY_CNT_Q_reg_n_0_[1]\, + R => '0' + ); +\pIDLY_CNT_Q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pIDLY_CE_reg_0(2), + Q => \pIDLY_CNT_Q_reg_n_0_[2]\, + R => '0' + ); +\pIDLY_CNT_Q_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pIDLY_CE_reg_0(3), + Q => \pIDLY_CNT_Q_reg_n_0_[3]\, + R => '0' + ); +\pIDLY_CNT_Q_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pIDLY_CE_reg_0(4), + Q => \pIDLY_CNT_Q_reg_n_0_[4]\, + R => '0' + ); +pIDLY_INC_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAA2AAAEAAAA" + ) + port map ( + I0 => \^pidly_inc\, + I1 => \pDelayWaitCnt[0]_i_2_n_0\, + I2 => pState(1), + I3 => iIn_q_i_3_n_0, + I4 => pState(5), + I5 => pState(7), + O => pIDLY_INC_i_1_n_0 + ); +pIDLY_INC_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pIDLY_INC_i_1_n_0, + Q => \^pidly_inc\, + R => '0' + ); +pIDLY_LD_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000004" + ) + port map ( + I0 => pState(4), + I1 => pState(0), + I2 => pState(3), + I3 => pIDLY_LD_i_2_n_0, + I4 => \pState[10]_i_3_n_0\, + O => pIDLY_LD_0 + ); +pIDLY_LD_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => pState(1), + I1 => pState(6), + I2 => pState(8), + I3 => pState(7), + I4 => pState(5), + O => pIDLY_LD_i_2_n_0 + ); +pIDLY_LD_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pIDLY_LD_0, + Q => pIDLY_LD, + R => '0' + ); +pStateNxt: unisim.vcomponents.LUT5 + generic map( + INIT => X"00010116" + ) + port map ( + I0 => pState(0), + I1 => pState(1), + I2 => pState(2), + I3 => pState(3), + I4 => pState(4), + O => pStateNxt_n_0 + ); +\pStateNxt__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFEFEE8" + ) + port map ( + I0 => pState(0), + I1 => pState(1), + I2 => pState(2), + I3 => pState(3), + I4 => pState(4), + O => \pStateNxt__0_n_0\ + ); +\pStateNxt__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000100010116" + ) + port map ( + I0 => pState(5), + I1 => pState(6), + I2 => pState(7), + I3 => pState(8), + I4 => pState(9), + I5 => pState(10), + O => \pStateNxt__1_n_0\ + ); +\pStateNxt__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFEFFFEFEE8" + ) + port map ( + I0 => pState(5), + I1 => pState(6), + I2 => pState(7), + I3 => pState(8), + I4 => pState(9), + I5 => pState(10), + O => \pStateNxt__2_n_0\ + ); +\pStateNxt__3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0012" + ) + port map ( + I0 => pStateNxt_n_0, + I1 => \pStateNxt__0_n_0\, + I2 => \pStateNxt__1_n_0\, + I3 => \pStateNxt__2_n_0\, + O => \pStateNxt__3_n_0\ + ); +\pState[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \pStateNxt__3_n_0\, + O => \pState[0]_i_1_n_0\ + ); +\pState[10]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFC8" + ) + port map ( + I0 => \pState[10]_i_3_n_0\, + I1 => iIn_q_i_3_n_0, + I2 => pDelayWaitOvf, + I3 => \pState[10]_i_4_n_0\, + I4 => \pState[10]_i_5_n_0\, + I5 => \pState[10]_i_6_n_0\, + O => \pStateNxt__4\ + ); +\pState[10]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => pDelayOvf, + I1 => pState(6), + I2 => \pStateNxt__3_n_0\, + O => \pState[10]_i_2_n_0\ + ); +\pState[10]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => pState(10), + I1 => pState(9), + I2 => pState(2), + O => \pState[10]_i_3_n_0\ + ); +\pState[10]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8888888889898988" + ) + port map ( + I0 => pState(10), + I1 => pState(9), + I2 => pState(2), + I3 => \out\(0), + I4 => pBlankBegin, + I5 => iIn_q_i_3_n_0, + O => \pState[10]_i_4_n_0\ + ); +\pState[10]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFD00FD00FD00" + ) + port map ( + I0 => pTknFlagQ, + I1 => pCtlTknOvf_reg_n_0, + I2 => iIn_q_i_4_n_0, + I3 => pState(2), + I4 => pState(6), + I5 => pState(8), + O => \pState[10]_i_5_n_0\ + ); +\pState[10]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFEFEFEEF" + ) + port map ( + I0 => pState(5), + I1 => pState(7), + I2 => pState(1), + I3 => iIn_q_i_3_n_0, + I4 => \pState[10]_i_3_n_0\, + I5 => iIn_q_i_2_n_0, + O => \pState[10]_i_6_n_0\ + ); +\pState[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF4F4400000000" + ) + port map ( + I0 => pDelayOvf, + I1 => pState(6), + I2 => pTknFlagQ, + I3 => pState(2), + I4 => pState(0), + I5 => \pStateNxt__3_n_0\, + O => \pState[1]_i_1_n_0\ + ); +\pState[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => pBlankBegin, + I1 => pState(1), + I2 => \pStateNxt__3_n_0\, + O => \pState[2]_i_1_n_0\ + ); +\pState[3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => pState(2), + I1 => pTknFlagQ, + I2 => \pStateNxt__3_n_0\, + O => \pState[3]_i_1_n_0\ + ); +\pState[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"4040F040" + ) + port map ( + I0 => \pState[5]_i_2_n_0\, + I1 => pState(3), + I2 => \pStateNxt__3_n_0\, + I3 => pState(1), + I4 => pBlankBegin, + O => \pState[4]_i_1_n_0\ + ); +\pState[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"8080F080" + ) + port map ( + I0 => pState(3), + I1 => \pState[5]_i_2_n_0\, + I2 => \pStateNxt__3_n_0\, + I3 => pState(4), + I4 => pFoundEyeFlag, + O => \pState[5]_i_1_n_0\ + ); +\pState[5]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFEFF" + ) + port map ( + I0 => \pEyeOpenCnt_reg_n_0_[0]\, + I1 => \pEyeOpenCnt_reg_n_0_[2]\, + I2 => \pEyeOpenCnt_reg_n_0_[3]\, + I3 => \pEyeOpenCnt_reg_n_0_[4]\, + I4 => \pEyeOpenCnt_reg_n_0_[1]\, + O => \pState[5]_i_2_n_0\ + ); +\pState[6]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => pState(5), + I1 => \pStateNxt__3_n_0\, + O => \pState[6]_i_1_n_0\ + ); +\pState[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F0202020" + ) + port map ( + I0 => pState(8), + I1 => pDelayCenter, + I2 => \pStateNxt__3_n_0\, + I3 => pState(4), + I4 => pFoundEyeFlag, + O => \pState[7]_i_1_n_0\ + ); +\pState[8]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => pState(7), + I1 => \pStateNxt__3_n_0\, + O => \pState[8]_i_1_n_0\ + ); +\pState[9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => pDelayCenter, + I1 => pState(8), + I2 => \pStateNxt__3_n_0\, + O => \pState[9]_i_1_n_0\ + ); +\pState_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[0]_i_1_n_0\, + Q => pState(0), + S => SR(0) + ); +\pState_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[10]_i_2_n_0\, + Q => pState(10), + R => SR(0) + ); +\pState_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[1]_i_1_n_0\, + Q => pState(1), + R => SR(0) + ); +\pState_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[2]_i_1_n_0\, + Q => pState(2), + R => SR(0) + ); +\pState_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[3]_i_1_n_0\, + Q => pState(3), + R => SR(0) + ); +\pState_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[4]_i_1_n_0\, + Q => pState(4), + R => SR(0) + ); +\pState_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[5]_i_1_n_0\, + Q => pState(5), + R => SR(0) + ); +\pState_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[6]_i_1_n_0\, + Q => pState(6), + R => SR(0) + ); +\pState_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[7]_i_1_n_0\, + Q => pState(7), + R => SR(0) + ); +\pState_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[8]_i_1_n_0\, + Q => pState(8), + R => SR(0) + ); +\pState_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[9]_i_1_n_0\, + Q => pState(9), + R => SR(0) + ); +pTknFlagQ_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pTknFlag, + Q => pTknFlagQ, + R => '0' + ); +pTknFlag_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"30000808" + ) + port map ( + I0 => pTknFlag_i_2_n_0, + I1 => pDataQ(8), + I2 => pDataQ(0), + I3 => pTknFlag_i_3_n_0, + I4 => pDataQ(3), + O => pTknFlag0 + ); +pTknFlag_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"0002000000000000" + ) + port map ( + I0 => pDataQ(4), + I1 => pDataQ(5), + I2 => pDataQ(7), + I3 => pDataQ(1), + I4 => pDataQ(2), + I5 => pDataQ(6), + O => pTknFlag_i_2_n_0 + ); +pTknFlag_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000004000" + ) + port map ( + I0 => pDataQ(4), + I1 => pDataQ(5), + I2 => pDataQ(7), + I3 => pDataQ(1), + I4 => pDataQ(2), + I5 => pDataQ(6), + O => pTknFlag_i_3_n_0 + ); +pTknFlag_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pTknFlag0, + Q => pTknFlag, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_PhaseAlign_12 is + port ( + pIDLY_CE : out STD_LOGIC; + pIDLY_INC : out STD_LOGIC; + pIDLY_LD : out STD_LOGIC; + pVld_1 : out STD_LOGIC; + pAlignErr_q_reg : out STD_LOGIC; + iIn_q_reg : out STD_LOGIC; + pMeRdy_int_reg : out STD_LOGIC; + pBitslip_reg : out STD_LOGIC; + PixelClk_int : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + pVld_2 : in STD_LOGIC; + pVld_0 : in STD_LOGIC; + pAlignErr_q : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 8 downto 0 ); + pIDLY_CE_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 ); + SS : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_PhaseAlign_12 : entity is "PhaseAlign"; +end Arty_Z7_20_dvi2rgb_0_0_PhaseAlign_12; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_PhaseAlign_12 is + signal \iIn_q_i_2__0_n_0\ : STD_LOGIC; + signal \iIn_q_i_3__0_n_0\ : STD_LOGIC; + signal \iIn_q_i_4__0_n_0\ : STD_LOGIC; + signal \iIn_q_i_5__0_n_0\ : STD_LOGIC; + signal \^palignerr_q_reg\ : STD_LOGIC; + signal pAligned : STD_LOGIC; + signal pBlankBegin : STD_LOGIC; + signal pBlankBegin0 : STD_LOGIC; + signal \pCenterTap[0]_i_1_n_0\ : STD_LOGIC; + signal \pCenterTap[1]_i_1__0_n_0\ : STD_LOGIC; + signal \pCenterTap[2]_i_1__0_n_0\ : STD_LOGIC; + signal \pCenterTap[3]_i_1__0_n_0\ : STD_LOGIC; + signal \pCenterTap[3]_i_2__0_n_0\ : STD_LOGIC; + signal \pCenterTap[4]_i_1__0_n_0\ : STD_LOGIC; + signal \pCenterTap[5]_i_1__0_n_0\ : STD_LOGIC; + signal \pCenterTap[5]_i_2__0_n_0\ : STD_LOGIC; + signal \pCenterTap[5]_i_3__0_n_0\ : STD_LOGIC; + signal \pCenterTap[5]_i_5__0_n_0\ : STD_LOGIC; + signal \pCenterTap_reg_n_0_[0]\ : STD_LOGIC; + signal \pCenterTap_reg_n_0_[1]\ : STD_LOGIC; + signal \pCenterTap_reg_n_0_[2]\ : STD_LOGIC; + signal \pCenterTap_reg_n_0_[3]\ : STD_LOGIC; + signal \pCenterTap_reg_n_0_[4]\ : STD_LOGIC; + signal \pCenterTap_reg_n_0_[5]\ : STD_LOGIC; + signal \pCtlTknCnt[6]_i_3__0_n_0\ : STD_LOGIC; + signal \pCtlTknCnt[6]_i_4__0_n_0\ : STD_LOGIC; + signal \pCtlTknCnt_reg__0\ : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal \pCtlTknOvf_i_1__0_n_0\ : STD_LOGIC; + signal \pCtlTknOvf_i_2__0_n_0\ : STD_LOGIC; + signal pCtlTknOvf_reg_n_0 : STD_LOGIC; + signal pCtlTknRst : STD_LOGIC; + signal \pDataQ_reg_n_0_[0]\ : STD_LOGIC; + signal \pDataQ_reg_n_0_[1]\ : STD_LOGIC; + signal \pDataQ_reg_n_0_[2]\ : STD_LOGIC; + signal \pDataQ_reg_n_0_[3]\ : STD_LOGIC; + signal \pDataQ_reg_n_0_[4]\ : STD_LOGIC; + signal \pDataQ_reg_n_0_[5]\ : STD_LOGIC; + signal \pDataQ_reg_n_0_[6]\ : STD_LOGIC; + signal \pDataQ_reg_n_0_[7]\ : STD_LOGIC; + signal \pDataQ_reg_n_0_[8]\ : STD_LOGIC; + signal \pDelayCenter_i_1__0_n_0\ : STD_LOGIC; + signal \pDelayCenter_i_2__0_n_0\ : STD_LOGIC; + signal pDelayCenter_reg_n_0 : STD_LOGIC; + signal \pDelayOvf_i_1__0_n_0\ : STD_LOGIC; + signal pDelayOvf_reg_n_0 : STD_LOGIC; + signal pDelayWaitCnt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \pDelayWaitCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \pDelayWaitCnt[0]_i_2__0_n_0\ : STD_LOGIC; + signal \pDelayWaitCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \pDelayWaitOvf_i_1__0_n_0\ : STD_LOGIC; + signal \pDelayWaitOvf_i_2__0_n_0\ : STD_LOGIC; + signal \pDelayWaitOvf_i_3__0_n_0\ : STD_LOGIC; + signal pDelayWaitOvf_reg_n_0 : STD_LOGIC; + signal pError : STD_LOGIC; + signal \pEyeOpenCnt[0]_i_1__0_n_0\ : STD_LOGIC; + signal \pEyeOpenCnt[1]_i_1__0_n_0\ : STD_LOGIC; + signal \pEyeOpenCnt[2]_i_1__0_n_0\ : STD_LOGIC; + signal \pEyeOpenCnt[3]_i_1__0_n_0\ : STD_LOGIC; + signal \pEyeOpenCnt[4]_i_1__0_n_0\ : STD_LOGIC; + signal \pEyeOpenCnt[4]_i_2__0_n_0\ : STD_LOGIC; + signal \pEyeOpenCnt[4]_i_3__0_n_0\ : STD_LOGIC; + signal \pEyeOpenCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \pEyeOpenCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \pEyeOpenCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \pEyeOpenCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \pEyeOpenCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \pEyeOpenEn__5\ : STD_LOGIC; + signal pEyeOpenRst : STD_LOGIC; + signal pFoundEyeFlag : STD_LOGIC; + signal \pFoundEyeFlag_i_1__0_n_0\ : STD_LOGIC; + signal \pFoundEyeFlag_i_2__0_n_0\ : STD_LOGIC; + signal \pFoundEyeFlag_i_3__0_n_0\ : STD_LOGIC; + signal \pFoundEyeFlag_i_4__0_n_0\ : STD_LOGIC; + signal pFoundJtrFlag : STD_LOGIC; + signal \pFoundJtrFlag_i_1__0_n_0\ : STD_LOGIC; + signal pIDLY_CE_1 : STD_LOGIC; + signal \pIDLY_CNT_Q_reg_n_0_[0]\ : STD_LOGIC; + signal \pIDLY_CNT_Q_reg_n_0_[1]\ : STD_LOGIC; + signal \pIDLY_CNT_Q_reg_n_0_[2]\ : STD_LOGIC; + signal \pIDLY_CNT_Q_reg_n_0_[3]\ : STD_LOGIC; + signal \pIDLY_CNT_Q_reg_n_0_[4]\ : STD_LOGIC; + signal \^pidly_inc\ : STD_LOGIC; + signal \pIDLY_INC_i_1__0_n_0\ : STD_LOGIC; + signal pIDLY_LD_0 : STD_LOGIC; + signal \pIDLY_LD_i_2__0_n_0\ : STD_LOGIC; + signal pState : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal \pStateNxt__0_n_0\ : STD_LOGIC; + signal \pStateNxt__1_n_0\ : STD_LOGIC; + signal \pStateNxt__2_n_0\ : STD_LOGIC; + signal \pStateNxt__3_n_0\ : STD_LOGIC; + signal \pStateNxt__4\ : STD_LOGIC; + signal pStateNxt_n_0 : STD_LOGIC; + signal \pState[0]_i_1__0_n_0\ : STD_LOGIC; + signal \pState[10]_i_2__0_n_0\ : STD_LOGIC; + signal \pState[10]_i_3__0_n_0\ : STD_LOGIC; + signal \pState[10]_i_4__0_n_0\ : STD_LOGIC; + signal \pState[10]_i_5__0_n_0\ : STD_LOGIC; + signal \pState[10]_i_6__0_n_0\ : STD_LOGIC; + signal \pState[1]_i_1__0_n_0\ : STD_LOGIC; + signal \pState[2]_i_1__0_n_0\ : STD_LOGIC; + signal \pState[3]_i_1__0_n_0\ : STD_LOGIC; + signal \pState[4]_i_1__0_n_0\ : STD_LOGIC; + signal \pState[5]_i_1__0_n_0\ : STD_LOGIC; + signal \pState[5]_i_2__0_n_0\ : STD_LOGIC; + signal \pState[6]_i_1__0_n_0\ : STD_LOGIC; + signal \pState[7]_i_1__0_n_0\ : STD_LOGIC; + signal \pState[8]_i_1__0_n_0\ : STD_LOGIC; + signal \pState[9]_i_1__0_n_0\ : STD_LOGIC; + signal pTknFlag : STD_LOGIC; + signal pTknFlag0 : STD_LOGIC; + signal pTknFlagQ : STD_LOGIC; + signal \pTknFlag_i_2__0_n_0\ : STD_LOGIC; + signal \pTknFlag_i_3__0_n_0\ : STD_LOGIC; + signal \^pvld_1\ : STD_LOGIC; + signal p_0_in : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal p_2_in : STD_LOGIC; + signal \plusOp__16\ : STD_LOGIC_VECTOR ( 5 downto 4 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \iIn_q_i_2__0\ : label is "soft_lutpair40"; + attribute SOFT_HLUTNM of \iIn_q_i_3__0\ : label is "soft_lutpair42"; + attribute SOFT_HLUTNM of \iIn_q_i_5__0\ : label is "soft_lutpair50"; + attribute SOFT_HLUTNM of \pAligned_i_1__0\ : label is "soft_lutpair45"; + attribute SOFT_HLUTNM of \pCenterTap[1]_i_1__0\ : label is "soft_lutpair38"; + attribute SOFT_HLUTNM of \pCenterTap[3]_i_2__0\ : label is "soft_lutpair38"; + attribute SOFT_HLUTNM of \pCtlTknCnt[0]_i_1__0\ : label is "soft_lutpair51"; + attribute SOFT_HLUTNM of \pCtlTknCnt[1]_i_1__0\ : label is "soft_lutpair51"; + attribute SOFT_HLUTNM of \pCtlTknCnt[2]_i_1__0\ : label is "soft_lutpair46"; + attribute SOFT_HLUTNM of \pCtlTknCnt[3]_i_1__0\ : label is "soft_lutpair46"; + attribute SOFT_HLUTNM of \pCtlTknCnt[4]_i_1__0\ : label is "soft_lutpair34"; + attribute SOFT_HLUTNM of \pCtlTknCnt[6]_i_2__0\ : label is "soft_lutpair44"; + attribute SOFT_HLUTNM of \pCtlTknCnt[6]_i_4__0\ : label is "soft_lutpair34"; + attribute SOFT_HLUTNM of \pCtlTknOvf_i_2__0\ : label is "soft_lutpair44"; + attribute SOFT_HLUTNM of \pDelayWaitCnt[1]_i_1\ : label is "soft_lutpair47"; + attribute SOFT_HLUTNM of \pDelayWaitOvf_i_2__0\ : label is "soft_lutpair49"; + attribute SOFT_HLUTNM of \pDelayWaitOvf_i_3__0\ : label is "soft_lutpair47"; + attribute SOFT_HLUTNM of \pError_i_1__0\ : label is "soft_lutpair45"; + attribute SOFT_HLUTNM of \pEyeOpenCnt[1]_i_1__0\ : label is "soft_lutpair37"; + attribute SOFT_HLUTNM of \pEyeOpenCnt[2]_i_1__0\ : label is "soft_lutpair37"; + attribute SOFT_HLUTNM of \pEyeOpenCnt[4]_i_4__0\ : label is "soft_lutpair39"; + attribute SOFT_HLUTNM of \pFoundEyeFlag_i_4__0\ : label is "soft_lutpair43"; + attribute SOFT_HLUTNM of \pFoundJtrFlag_i_1__0\ : label is "soft_lutpair40"; + attribute SOFT_HLUTNM of \pIDLY_LD_i_1__0\ : label is "soft_lutpair39"; + attribute SOFT_HLUTNM of \pIDLY_LD_i_2__0\ : label is "soft_lutpair42"; + attribute SOFT_HLUTNM of pStateNxt : label is "soft_lutpair35"; + attribute SOFT_HLUTNM of \pStateNxt__0\ : label is "soft_lutpair35"; + attribute SOFT_HLUTNM of \pState[10]_i_2__0\ : label is "soft_lutpair49"; + attribute SOFT_HLUTNM of \pState[10]_i_3__0\ : label is "soft_lutpair48"; + attribute SOFT_HLUTNM of \pState[2]_i_1__0\ : label is "soft_lutpair41"; + attribute SOFT_HLUTNM of \pState[3]_i_1__0\ : label is "soft_lutpair48"; + attribute SOFT_HLUTNM of \pState[4]_i_1__0\ : label is "soft_lutpair41"; + attribute SOFT_HLUTNM of \pState[5]_i_2__0\ : label is "soft_lutpair43"; + attribute SOFT_HLUTNM of \pState[6]_i_1__0\ : label is "soft_lutpair50"; + attribute SOFT_HLUTNM of \pState[7]_i_1__0\ : label is "soft_lutpair36"; + attribute SOFT_HLUTNM of \pState[9]_i_1__0\ : label is "soft_lutpair36"; +begin + pAlignErr_q_reg <= \^palignerr_q_reg\; + pIDLY_INC <= \^pidly_inc\; + pVld_1 <= \^pvld_1\; +\iIn_q_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFEFFFEFFFF" + ) + port map ( + I0 => \iIn_q_i_2__0_n_0\, + I1 => \iIn_q_i_3__0_n_0\, + I2 => \iIn_q_i_4__0_n_0\, + I3 => \iIn_q_i_5__0_n_0\, + I4 => pState(1), + I5 => pState(2), + O => iIn_q_reg + ); +\iIn_q_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => pState(4), + I1 => pState(0), + I2 => pState(3), + O => \iIn_q_i_2__0_n_0\ + ); +\iIn_q_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => pState(6), + I1 => pState(8), + O => \iIn_q_i_3__0_n_0\ + ); +\iIn_q_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => pState(9), + I1 => pState(10), + O => \iIn_q_i_4__0_n_0\ + ); +\iIn_q_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => pState(5), + I1 => pState(7), + O => \iIn_q_i_5__0_n_0\ + ); +\pAligned_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0004" + ) + port map ( + I0 => pState(2), + I1 => pState(9), + I2 => pState(10), + I3 => \pCtlTknCnt[6]_i_3__0_n_0\, + O => pAligned + ); +pAligned_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pAligned, + Q => \^pvld_1\, + R => '0' + ); +\pBitslip_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^palignerr_q_reg\, + I1 => pAlignErr_q, + O => pBitslip_reg + ); +\pBlankBegin_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => pTknFlag, + I1 => pTknFlagQ, + O => pBlankBegin0 + ); +pBlankBegin_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pBlankBegin0, + Q => pBlankBegin, + R => '0' + ); +\pCenterTap[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAA5AAAAAFBA" + ) + port map ( + I0 => \pCenterTap_reg_n_0_[0]\, + I1 => pFoundEyeFlag, + I2 => pState(4), + I3 => pState(0), + I4 => \pCenterTap[5]_i_3__0_n_0\, + I5 => pState(3), + O => \pCenterTap[0]_i_1_n_0\ + ); +\pCenterTap[1]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FF606060" + ) + port map ( + I0 => \pCenterTap_reg_n_0_[0]\, + I1 => \pCenterTap_reg_n_0_[1]\, + I2 => \pCenterTap[5]_i_5__0_n_0\, + I3 => \pIDLY_CNT_Q_reg_n_0_[0]\, + I4 => pEyeOpenRst, + O => \pCenterTap[1]_i_1__0_n_0\ + ); +\pCenterTap[2]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF780078007800" + ) + port map ( + I0 => \pCenterTap_reg_n_0_[1]\, + I1 => \pCenterTap_reg_n_0_[0]\, + I2 => \pCenterTap_reg_n_0_[2]\, + I3 => \pCenterTap[5]_i_5__0_n_0\, + I4 => \pIDLY_CNT_Q_reg_n_0_[1]\, + I5 => pEyeOpenRst, + O => \pCenterTap[2]_i_1__0_n_0\ + ); +\pCenterTap[3]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF780078007800" + ) + port map ( + I0 => \pCenterTap_reg_n_0_[2]\, + I1 => \pCenterTap[3]_i_2__0_n_0\, + I2 => \pCenterTap_reg_n_0_[3]\, + I3 => \pCenterTap[5]_i_5__0_n_0\, + I4 => \pIDLY_CNT_Q_reg_n_0_[2]\, + I5 => pEyeOpenRst, + O => \pCenterTap[3]_i_1__0_n_0\ + ); +\pCenterTap[3]_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \pCenterTap_reg_n_0_[0]\, + I1 => \pCenterTap_reg_n_0_[1]\, + O => \pCenterTap[3]_i_2__0_n_0\ + ); +\pCenterTap[4]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F888" + ) + port map ( + I0 => \plusOp__16\(4), + I1 => \pCenterTap[5]_i_5__0_n_0\, + I2 => \pIDLY_CNT_Q_reg_n_0_[3]\, + I3 => pEyeOpenRst, + O => \pCenterTap[4]_i_1__0_n_0\ + ); +\pCenterTap[4]_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \pCenterTap_reg_n_0_[0]\, + I1 => \pCenterTap_reg_n_0_[1]\, + I2 => \pCenterTap_reg_n_0_[2]\, + I3 => \pCenterTap_reg_n_0_[3]\, + I4 => \pCenterTap_reg_n_0_[4]\, + O => \plusOp__16\(4) + ); +\pCenterTap[5]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00030034" + ) + port map ( + I0 => pFoundEyeFlag, + I1 => pState(4), + I2 => pState(0), + I3 => \pCenterTap[5]_i_3__0_n_0\, + I4 => pState(3), + O => \pCenterTap[5]_i_1__0_n_0\ + ); +\pCenterTap[5]_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F888" + ) + port map ( + I0 => \plusOp__16\(5), + I1 => \pCenterTap[5]_i_5__0_n_0\, + I2 => \pIDLY_CNT_Q_reg_n_0_[4]\, + I3 => pEyeOpenRst, + O => \pCenterTap[5]_i_2__0_n_0\ + ); +\pCenterTap[5]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => pState(5), + I1 => pState(7), + I2 => pState(8), + I3 => pState(6), + I4 => pState(1), + I5 => \pState[10]_i_3__0_n_0\, + O => \pCenterTap[5]_i_3__0_n_0\ + ); +\pCenterTap[5]_i_4__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFFFFFF80000000" + ) + port map ( + I0 => \pCenterTap_reg_n_0_[0]\, + I1 => \pCenterTap_reg_n_0_[1]\, + I2 => \pCenterTap_reg_n_0_[4]\, + I3 => \pCenterTap_reg_n_0_[3]\, + I4 => \pCenterTap_reg_n_0_[2]\, + I5 => \pCenterTap_reg_n_0_[5]\, + O => \plusOp__16\(5) + ); +\pCenterTap[5]_i_5__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFEFFFAFFFF" + ) + port map ( + I0 => pState(3), + I1 => pFoundEyeFlag, + I2 => \pIDLY_LD_i_2__0_n_0\, + I3 => \pState[10]_i_3__0_n_0\, + I4 => pState(0), + I5 => pState(4), + O => \pCenterTap[5]_i_5__0_n_0\ + ); +\pCenterTap[5]_i_6__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000010000010100" + ) + port map ( + I0 => pState(3), + I1 => \pIDLY_LD_i_2__0_n_0\, + I2 => \pState[10]_i_3__0_n_0\, + I3 => pState(0), + I4 => pState(4), + I5 => pFoundEyeFlag, + O => pEyeOpenRst + ); +\pCenterTap_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pCenterTap[0]_i_1_n_0\, + Q => \pCenterTap_reg_n_0_[0]\, + R => '0' + ); +\pCenterTap_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pCenterTap[5]_i_1__0_n_0\, + D => \pCenterTap[1]_i_1__0_n_0\, + Q => \pCenterTap_reg_n_0_[1]\, + R => '0' + ); +\pCenterTap_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pCenterTap[5]_i_1__0_n_0\, + D => \pCenterTap[2]_i_1__0_n_0\, + Q => \pCenterTap_reg_n_0_[2]\, + R => '0' + ); +\pCenterTap_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pCenterTap[5]_i_1__0_n_0\, + D => \pCenterTap[3]_i_1__0_n_0\, + Q => \pCenterTap_reg_n_0_[3]\, + R => '0' + ); +\pCenterTap_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pCenterTap[5]_i_1__0_n_0\, + D => \pCenterTap[4]_i_1__0_n_0\, + Q => \pCenterTap_reg_n_0_[4]\, + R => '0' + ); +\pCenterTap_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pCenterTap[5]_i_1__0_n_0\, + D => \pCenterTap[5]_i_2__0_n_0\, + Q => \pCenterTap_reg_n_0_[5]\, + R => '0' + ); +\pCtlTknCnt[0]_i_1__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \pCtlTknCnt_reg__0\(0), + O => p_0_in(0) + ); +\pCtlTknCnt[1]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \pCtlTknCnt_reg__0\(0), + I1 => \pCtlTknCnt_reg__0\(1), + O => p_0_in(1) + ); +\pCtlTknCnt[2]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \pCtlTknCnt_reg__0\(1), + I1 => \pCtlTknCnt_reg__0\(0), + I2 => \pCtlTknCnt_reg__0\(2), + O => p_0_in(2) + ); +\pCtlTknCnt[3]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \pCtlTknCnt_reg__0\(2), + I1 => \pCtlTknCnt_reg__0\(0), + I2 => \pCtlTknCnt_reg__0\(1), + I3 => \pCtlTknCnt_reg__0\(3), + O => p_0_in(3) + ); +\pCtlTknCnt[4]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \pCtlTknCnt_reg__0\(3), + I1 => \pCtlTknCnt_reg__0\(1), + I2 => \pCtlTknCnt_reg__0\(0), + I3 => \pCtlTknCnt_reg__0\(2), + I4 => \pCtlTknCnt_reg__0\(4), + O => p_0_in(4) + ); +\pCtlTknCnt[5]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFFFFFF80000000" + ) + port map ( + I0 => \pCtlTknCnt_reg__0\(4), + I1 => \pCtlTknCnt_reg__0\(2), + I2 => \pCtlTknCnt_reg__0\(0), + I3 => \pCtlTknCnt_reg__0\(1), + I4 => \pCtlTknCnt_reg__0\(3), + I5 => \pCtlTknCnt_reg__0\(5), + O => p_0_in(5) + ); +\pCtlTknCnt[6]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFD" + ) + port map ( + I0 => pState(2), + I1 => pState(9), + I2 => pState(10), + I3 => \pCtlTknCnt[6]_i_3__0_n_0\, + O => pCtlTknRst + ); +\pCtlTknCnt[6]_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \pCtlTknCnt[6]_i_4__0_n_0\, + I1 => \pCtlTknCnt_reg__0\(4), + I2 => \pCtlTknCnt_reg__0\(5), + I3 => \pCtlTknCnt_reg__0\(6), + O => p_0_in(6) + ); +\pCtlTknCnt[6]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => \iIn_q_i_2__0_n_0\, + I1 => pState(5), + I2 => pState(7), + I3 => pState(8), + I4 => pState(6), + I5 => pState(1), + O => \pCtlTknCnt[6]_i_3__0_n_0\ + ); +\pCtlTknCnt[6]_i_4__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => \pCtlTknCnt_reg__0\(2), + I1 => \pCtlTknCnt_reg__0\(0), + I2 => \pCtlTknCnt_reg__0\(1), + I3 => \pCtlTknCnt_reg__0\(3), + O => \pCtlTknCnt[6]_i_4__0_n_0\ + ); +\pCtlTknCnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_in(0), + Q => \pCtlTknCnt_reg__0\(0), + R => pCtlTknRst + ); +\pCtlTknCnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_in(1), + Q => \pCtlTknCnt_reg__0\(1), + R => pCtlTknRst + ); +\pCtlTknCnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_in(2), + Q => \pCtlTknCnt_reg__0\(2), + R => pCtlTknRst + ); +\pCtlTknCnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_in(3), + Q => \pCtlTknCnt_reg__0\(3), + R => pCtlTknRst + ); +\pCtlTknCnt_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_in(4), + Q => \pCtlTknCnt_reg__0\(4), + R => pCtlTknRst + ); +\pCtlTknCnt_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_in(5), + Q => \pCtlTknCnt_reg__0\(5), + R => pCtlTknRst + ); +\pCtlTknCnt_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_in(6), + Q => \pCtlTknCnt_reg__0\(6), + R => pCtlTknRst + ); +\pCtlTknOvf_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAEAAAAAAA2" + ) + port map ( + I0 => pCtlTknOvf_reg_n_0, + I1 => pState(2), + I2 => pState(9), + I3 => pState(10), + I4 => \pCtlTknCnt[6]_i_3__0_n_0\, + I5 => \pCtlTknOvf_i_2__0_n_0\, + O => \pCtlTknOvf_i_1__0_n_0\ + ); +\pCtlTknOvf_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => \pCtlTknCnt_reg__0\(4), + I1 => \pCtlTknCnt_reg__0\(5), + I2 => \pCtlTknCnt_reg__0\(6), + I3 => \pCtlTknCnt[6]_i_4__0_n_0\, + O => \pCtlTknOvf_i_2__0_n_0\ + ); +pCtlTknOvf_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pCtlTknOvf_i_1__0_n_0\, + Q => pCtlTknOvf_reg_n_0, + R => '0' + ); +\pDataQ_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => D(0), + Q => \pDataQ_reg_n_0_[0]\, + R => '0' + ); +\pDataQ_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => D(1), + Q => \pDataQ_reg_n_0_[1]\, + R => '0' + ); +\pDataQ_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => D(2), + Q => \pDataQ_reg_n_0_[2]\, + R => '0' + ); +\pDataQ_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => D(3), + Q => \pDataQ_reg_n_0_[3]\, + R => '0' + ); +\pDataQ_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => D(4), + Q => \pDataQ_reg_n_0_[4]\, + R => '0' + ); +\pDataQ_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => D(5), + Q => \pDataQ_reg_n_0_[5]\, + R => '0' + ); +\pDataQ_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => D(6), + Q => \pDataQ_reg_n_0_[6]\, + R => '0' + ); +\pDataQ_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => D(7), + Q => \pDataQ_reg_n_0_[7]\, + R => '0' + ); +\pDataQ_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => D(8), + Q => \pDataQ_reg_n_0_[8]\, + R => '0' + ); +\pDelayCenter_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"82000082" + ) + port map ( + I0 => \pDelayCenter_i_2__0_n_0\, + I1 => \pCenterTap_reg_n_0_[5]\, + I2 => \pIDLY_CNT_Q_reg_n_0_[4]\, + I3 => \pCenterTap_reg_n_0_[4]\, + I4 => \pIDLY_CNT_Q_reg_n_0_[3]\, + O => \pDelayCenter_i_1__0_n_0\ + ); +\pDelayCenter_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \pCenterTap_reg_n_0_[3]\, + I1 => \pIDLY_CNT_Q_reg_n_0_[2]\, + I2 => \pCenterTap_reg_n_0_[2]\, + I3 => \pIDLY_CNT_Q_reg_n_0_[1]\, + I4 => \pIDLY_CNT_Q_reg_n_0_[0]\, + I5 => \pCenterTap_reg_n_0_[1]\, + O => \pDelayCenter_i_2__0_n_0\ + ); +pDelayCenter_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pDelayCenter_i_1__0_n_0\, + Q => pDelayCenter_reg_n_0, + R => '0' + ); +\pDelayOvf_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000001" + ) + port map ( + I0 => \pIDLY_CNT_Q_reg_n_0_[0]\, + I1 => \pIDLY_CNT_Q_reg_n_0_[1]\, + I2 => \pIDLY_CNT_Q_reg_n_0_[2]\, + I3 => \pIDLY_CNT_Q_reg_n_0_[4]\, + I4 => \pIDLY_CNT_Q_reg_n_0_[3]\, + O => \pDelayOvf_i_1__0_n_0\ + ); +pDelayOvf_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pDelayOvf_i_1__0_n_0\, + Q => pDelayOvf_reg_n_0, + R => '0' + ); +\pDelayWaitCnt[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000001400000000" + ) + port map ( + I0 => pDelayWaitCnt(0), + I1 => pState(6), + I2 => pState(8), + I3 => \iIn_q_i_5__0_n_0\, + I4 => pState(1), + I5 => \pDelayWaitCnt[0]_i_2__0_n_0\, + O => \pDelayWaitCnt[0]_i_1_n_0\ + ); +\pDelayWaitCnt[0]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000001" + ) + port map ( + I0 => pState(3), + I1 => pState(0), + I2 => pState(4), + I3 => pState(2), + I4 => pState(9), + I5 => pState(10), + O => \pDelayWaitCnt[0]_i_2__0_n_0\ + ); +\pDelayWaitCnt[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"60" + ) + port map ( + I0 => pDelayWaitCnt(1), + I1 => pDelayWaitCnt(0), + I2 => p_2_in, + O => \pDelayWaitCnt[1]_i_1_n_0\ + ); +\pDelayWaitCnt[1]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000600000000" + ) + port map ( + I0 => pState(6), + I1 => pState(8), + I2 => pState(7), + I3 => pState(5), + I4 => pState(1), + I5 => \pDelayWaitCnt[0]_i_2__0_n_0\, + O => p_2_in + ); +\pDelayWaitCnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pDelayWaitCnt[0]_i_1_n_0\, + Q => pDelayWaitCnt(0), + R => '0' + ); +\pDelayWaitCnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pDelayWaitCnt[1]_i_1_n_0\, + Q => pDelayWaitCnt(1), + R => '0' + ); +\pDelayWaitOvf_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CCFCCCCCCC8CCCCC" + ) + port map ( + I0 => pState(1), + I1 => pDelayWaitOvf_reg_n_0, + I2 => \pDelayWaitCnt[0]_i_2__0_n_0\, + I3 => \iIn_q_i_5__0_n_0\, + I4 => \pDelayWaitOvf_i_2__0_n_0\, + I5 => \pDelayWaitOvf_i_3__0_n_0\, + O => \pDelayWaitOvf_i_1__0_n_0\ + ); +\pDelayWaitOvf_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => pState(6), + I1 => pState(8), + O => \pDelayWaitOvf_i_2__0_n_0\ + ); +\pDelayWaitOvf_i_3__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => pState(1), + I1 => pDelayWaitCnt(1), + I2 => pDelayWaitCnt(0), + O => \pDelayWaitOvf_i_3__0_n_0\ + ); +pDelayWaitOvf_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pDelayWaitOvf_i_1__0_n_0\, + Q => pDelayWaitOvf_reg_n_0, + R => '0' + ); +\pError_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0004" + ) + port map ( + I0 => pState(2), + I1 => pState(10), + I2 => pState(9), + I3 => \pCtlTknCnt[6]_i_3__0_n_0\, + O => pError + ); +pError_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pError, + Q => \^palignerr_q_reg\, + R => '0' + ); +\pEyeOpenCnt[0]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CCCCCCCCCCC3C80C" + ) + port map ( + I0 => pFoundEyeFlag, + I1 => \pEyeOpenCnt_reg_n_0_[0]\, + I2 => pState(0), + I3 => pState(4), + I4 => pState(3), + I5 => \pCenterTap[5]_i_3__0_n_0\, + O => \pEyeOpenCnt[0]_i_1__0_n_0\ + ); +\pEyeOpenCnt[1]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BCA0" + ) + port map ( + I0 => \pEyeOpenCnt[4]_i_2__0_n_0\, + I1 => \pEyeOpenCnt_reg_n_0_[0]\, + I2 => \pEyeOpenCnt_reg_n_0_[1]\, + I3 => \pEyeOpenEn__5\, + O => \pEyeOpenCnt[1]_i_1__0_n_0\ + ); +\pEyeOpenCnt[2]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFC0AA00" + ) + port map ( + I0 => \pEyeOpenCnt[4]_i_2__0_n_0\, + I1 => \pEyeOpenCnt_reg_n_0_[1]\, + I2 => \pEyeOpenCnt_reg_n_0_[0]\, + I3 => \pEyeOpenCnt_reg_n_0_[2]\, + I4 => \pEyeOpenEn__5\, + O => \pEyeOpenCnt[2]_i_1__0_n_0\ + ); +\pEyeOpenCnt[3]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BFFFC000AAAA0000" + ) + port map ( + I0 => \pEyeOpenCnt[4]_i_2__0_n_0\, + I1 => \pEyeOpenCnt_reg_n_0_[0]\, + I2 => \pEyeOpenCnt_reg_n_0_[1]\, + I3 => \pEyeOpenCnt_reg_n_0_[2]\, + I4 => \pEyeOpenCnt_reg_n_0_[3]\, + I5 => \pEyeOpenEn__5\, + O => \pEyeOpenCnt[3]_i_1__0_n_0\ + ); +\pEyeOpenCnt[4]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BFFFC000AAAA0000" + ) + port map ( + I0 => \pEyeOpenCnt[4]_i_2__0_n_0\, + I1 => \pEyeOpenCnt_reg_n_0_[2]\, + I2 => \pEyeOpenCnt_reg_n_0_[3]\, + I3 => \pEyeOpenCnt[4]_i_3__0_n_0\, + I4 => \pEyeOpenCnt_reg_n_0_[4]\, + I5 => \pEyeOpenEn__5\, + O => \pEyeOpenCnt[4]_i_1__0_n_0\ + ); +\pEyeOpenCnt[4]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFEFFFCFFF3" + ) + port map ( + I0 => pFoundEyeFlag, + I1 => pState(3), + I2 => \pIDLY_LD_i_2__0_n_0\, + I3 => \pState[10]_i_3__0_n_0\, + I4 => pState(0), + I5 => pState(4), + O => \pEyeOpenCnt[4]_i_2__0_n_0\ + ); +\pEyeOpenCnt[4]_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \pEyeOpenCnt_reg_n_0_[0]\, + I1 => \pEyeOpenCnt_reg_n_0_[1]\, + O => \pEyeOpenCnt[4]_i_3__0_n_0\ + ); +\pEyeOpenCnt[4]_i_4__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000010" + ) + port map ( + I0 => pState(0), + I1 => pState(4), + I2 => pState(3), + I3 => \pState[10]_i_3__0_n_0\, + I4 => \pIDLY_LD_i_2__0_n_0\, + O => \pEyeOpenEn__5\ + ); +\pEyeOpenCnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pEyeOpenCnt[0]_i_1__0_n_0\, + Q => \pEyeOpenCnt_reg_n_0_[0]\, + R => '0' + ); +\pEyeOpenCnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pEyeOpenCnt[1]_i_1__0_n_0\, + Q => \pEyeOpenCnt_reg_n_0_[1]\, + R => '0' + ); +\pEyeOpenCnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pEyeOpenCnt[2]_i_1__0_n_0\, + Q => \pEyeOpenCnt_reg_n_0_[2]\, + R => '0' + ); +\pEyeOpenCnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pEyeOpenCnt[3]_i_1__0_n_0\, + Q => \pEyeOpenCnt_reg_n_0_[3]\, + R => '0' + ); +\pEyeOpenCnt_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pEyeOpenCnt[4]_i_1__0_n_0\, + Q => \pEyeOpenCnt_reg_n_0_[4]\, + R => '0' + ); +\pFoundEyeFlag_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ABBBA888" + ) + port map ( + I0 => \pFoundEyeFlag_i_2__0_n_0\, + I1 => pIDLY_LD_0, + I2 => \pEyeOpenEn__5\, + I3 => \pFoundEyeFlag_i_3__0_n_0\, + I4 => pFoundEyeFlag, + O => \pFoundEyeFlag_i_1__0_n_0\ + ); +\pFoundEyeFlag_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1000004000000040" + ) + port map ( + I0 => \pFoundEyeFlag_i_4__0_n_0\, + I1 => \pEyeOpenCnt_reg_n_0_[4]\, + I2 => pState(3), + I3 => \pEyeOpenCnt_reg_n_0_[0]\, + I4 => \pEyeOpenCnt_reg_n_0_[1]\, + I5 => pFoundJtrFlag, + O => \pFoundEyeFlag_i_2__0_n_0\ + ); +\pFoundEyeFlag_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0100001000000010" + ) + port map ( + I0 => \pEyeOpenCnt_reg_n_0_[2]\, + I1 => \pEyeOpenCnt_reg_n_0_[3]\, + I2 => \pEyeOpenCnt_reg_n_0_[4]\, + I3 => \pEyeOpenCnt_reg_n_0_[0]\, + I4 => \pEyeOpenCnt_reg_n_0_[1]\, + I5 => pFoundJtrFlag, + O => \pFoundEyeFlag_i_3__0_n_0\ + ); +\pFoundEyeFlag_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \pEyeOpenCnt_reg_n_0_[2]\, + I1 => \pEyeOpenCnt_reg_n_0_[3]\, + O => \pFoundEyeFlag_i_4__0_n_0\ + ); +pFoundEyeFlag_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pFoundEyeFlag_i_1__0_n_0\, + Q => pFoundEyeFlag, + R => '0' + ); +\pFoundJtrFlag_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FEFF0010" + ) + port map ( + I0 => pState(3), + I1 => \pCenterTap[5]_i_3__0_n_0\, + I2 => pState(4), + I3 => pState(0), + I4 => pFoundJtrFlag, + O => \pFoundJtrFlag_i_1__0_n_0\ + ); +pFoundJtrFlag_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pFoundJtrFlag_i_1__0_n_0\, + Q => pFoundJtrFlag, + R => '0' + ); +\pIDLY_CE_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000200020000" + ) + port map ( + I0 => \pDelayWaitCnt[0]_i_2__0_n_0\, + I1 => pState(1), + I2 => pState(6), + I3 => pState(8), + I4 => pState(5), + I5 => pState(7), + O => pIDLY_CE_1 + ); +pIDLY_CE_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pIDLY_CE_1, + Q => pIDLY_CE, + R => '0' + ); +\pIDLY_CNT_Q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pIDLY_CE_reg_0(0), + Q => \pIDLY_CNT_Q_reg_n_0_[0]\, + R => '0' + ); +\pIDLY_CNT_Q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pIDLY_CE_reg_0(1), + Q => \pIDLY_CNT_Q_reg_n_0_[1]\, + R => '0' + ); +\pIDLY_CNT_Q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pIDLY_CE_reg_0(2), + Q => \pIDLY_CNT_Q_reg_n_0_[2]\, + R => '0' + ); +\pIDLY_CNT_Q_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pIDLY_CE_reg_0(3), + Q => \pIDLY_CNT_Q_reg_n_0_[3]\, + R => '0' + ); +\pIDLY_CNT_Q_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pIDLY_CE_reg_0(4), + Q => \pIDLY_CNT_Q_reg_n_0_[4]\, + R => '0' + ); +\pIDLY_INC_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAA2AAAEAAAA" + ) + port map ( + I0 => \^pidly_inc\, + I1 => \pDelayWaitCnt[0]_i_2__0_n_0\, + I2 => pState(1), + I3 => \iIn_q_i_3__0_n_0\, + I4 => pState(5), + I5 => pState(7), + O => \pIDLY_INC_i_1__0_n_0\ + ); +pIDLY_INC_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pIDLY_INC_i_1__0_n_0\, + Q => \^pidly_inc\, + R => '0' + ); +\pIDLY_LD_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000004" + ) + port map ( + I0 => pState(4), + I1 => pState(0), + I2 => pState(3), + I3 => \pIDLY_LD_i_2__0_n_0\, + I4 => \pState[10]_i_3__0_n_0\, + O => pIDLY_LD_0 + ); +\pIDLY_LD_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => pState(1), + I1 => pState(6), + I2 => pState(8), + I3 => pState(7), + I4 => pState(5), + O => \pIDLY_LD_i_2__0_n_0\ + ); +pIDLY_LD_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pIDLY_LD_0, + Q => pIDLY_LD, + R => '0' + ); +pStateNxt: unisim.vcomponents.LUT5 + generic map( + INIT => X"00010116" + ) + port map ( + I0 => pState(0), + I1 => pState(1), + I2 => pState(2), + I3 => pState(3), + I4 => pState(4), + O => pStateNxt_n_0 + ); +\pStateNxt__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFEFEE8" + ) + port map ( + I0 => pState(0), + I1 => pState(1), + I2 => pState(2), + I3 => pState(3), + I4 => pState(4), + O => \pStateNxt__0_n_0\ + ); +\pStateNxt__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000100010116" + ) + port map ( + I0 => pState(5), + I1 => pState(6), + I2 => pState(7), + I3 => pState(8), + I4 => pState(9), + I5 => pState(10), + O => \pStateNxt__1_n_0\ + ); +\pStateNxt__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFEFFFEFEE8" + ) + port map ( + I0 => pState(5), + I1 => pState(6), + I2 => pState(7), + I3 => pState(8), + I4 => pState(9), + I5 => pState(10), + O => \pStateNxt__2_n_0\ + ); +\pStateNxt__3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0012" + ) + port map ( + I0 => pStateNxt_n_0, + I1 => \pStateNxt__0_n_0\, + I2 => \pStateNxt__1_n_0\, + I3 => \pStateNxt__2_n_0\, + O => \pStateNxt__3_n_0\ + ); +\pState[0]_i_1__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \pStateNxt__3_n_0\, + O => \pState[0]_i_1__0_n_0\ + ); +\pState[10]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFC8" + ) + port map ( + I0 => \pState[10]_i_3__0_n_0\, + I1 => \iIn_q_i_3__0_n_0\, + I2 => pDelayWaitOvf_reg_n_0, + I3 => \pState[10]_i_4__0_n_0\, + I4 => \pState[10]_i_5__0_n_0\, + I5 => \pState[10]_i_6__0_n_0\, + O => \pStateNxt__4\ + ); +\pState[10]_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => pDelayOvf_reg_n_0, + I1 => pState(6), + I2 => \pStateNxt__3_n_0\, + O => \pState[10]_i_2__0_n_0\ + ); +\pState[10]_i_3__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => pState(10), + I1 => pState(9), + I2 => pState(2), + O => \pState[10]_i_3__0_n_0\ + ); +\pState[10]_i_4__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8888888889898988" + ) + port map ( + I0 => pState(10), + I1 => pState(9), + I2 => pState(2), + I3 => \out\(0), + I4 => pBlankBegin, + I5 => \iIn_q_i_3__0_n_0\, + O => \pState[10]_i_4__0_n_0\ + ); +\pState[10]_i_5__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFD00FD00FD00" + ) + port map ( + I0 => pTknFlagQ, + I1 => pCtlTknOvf_reg_n_0, + I2 => \iIn_q_i_4__0_n_0\, + I3 => pState(2), + I4 => pState(6), + I5 => pState(8), + O => \pState[10]_i_5__0_n_0\ + ); +\pState[10]_i_6__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFEFEFEEF" + ) + port map ( + I0 => pState(5), + I1 => pState(7), + I2 => pState(1), + I3 => \iIn_q_i_3__0_n_0\, + I4 => \pState[10]_i_3__0_n_0\, + I5 => \iIn_q_i_2__0_n_0\, + O => \pState[10]_i_6__0_n_0\ + ); +\pState[1]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF4F4400000000" + ) + port map ( + I0 => pDelayOvf_reg_n_0, + I1 => pState(6), + I2 => pTknFlagQ, + I3 => pState(2), + I4 => pState(0), + I5 => \pStateNxt__3_n_0\, + O => \pState[1]_i_1__0_n_0\ + ); +\pState[2]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => pBlankBegin, + I1 => pState(1), + I2 => \pStateNxt__3_n_0\, + O => \pState[2]_i_1__0_n_0\ + ); +\pState[3]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => pState(2), + I1 => pTknFlagQ, + I2 => \pStateNxt__3_n_0\, + O => \pState[3]_i_1__0_n_0\ + ); +\pState[4]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"4040F040" + ) + port map ( + I0 => \pState[5]_i_2__0_n_0\, + I1 => pState(3), + I2 => \pStateNxt__3_n_0\, + I3 => pState(1), + I4 => pBlankBegin, + O => \pState[4]_i_1__0_n_0\ + ); +\pState[5]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"8080F080" + ) + port map ( + I0 => pState(3), + I1 => \pState[5]_i_2__0_n_0\, + I2 => \pStateNxt__3_n_0\, + I3 => pState(4), + I4 => pFoundEyeFlag, + O => \pState[5]_i_1__0_n_0\ + ); +\pState[5]_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFEFF" + ) + port map ( + I0 => \pEyeOpenCnt_reg_n_0_[0]\, + I1 => \pEyeOpenCnt_reg_n_0_[2]\, + I2 => \pEyeOpenCnt_reg_n_0_[3]\, + I3 => \pEyeOpenCnt_reg_n_0_[4]\, + I4 => \pEyeOpenCnt_reg_n_0_[1]\, + O => \pState[5]_i_2__0_n_0\ + ); +\pState[6]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => pState(5), + I1 => \pStateNxt__3_n_0\, + O => \pState[6]_i_1__0_n_0\ + ); +\pState[7]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F0202020" + ) + port map ( + I0 => pState(8), + I1 => pDelayCenter_reg_n_0, + I2 => \pStateNxt__3_n_0\, + I3 => pState(4), + I4 => pFoundEyeFlag, + O => \pState[7]_i_1__0_n_0\ + ); +\pState[8]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => pState(7), + I1 => \pStateNxt__3_n_0\, + O => \pState[8]_i_1__0_n_0\ + ); +\pState[9]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => pDelayCenter_reg_n_0, + I1 => pState(8), + I2 => \pStateNxt__3_n_0\, + O => \pState[9]_i_1__0_n_0\ + ); +\pState_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[0]_i_1__0_n_0\, + Q => pState(0), + S => SS(0) + ); +\pState_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[10]_i_2__0_n_0\, + Q => pState(10), + R => SS(0) + ); +\pState_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[1]_i_1__0_n_0\, + Q => pState(1), + R => SS(0) + ); +\pState_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[2]_i_1__0_n_0\, + Q => pState(2), + R => SS(0) + ); +\pState_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[3]_i_1__0_n_0\, + Q => pState(3), + R => SS(0) + ); +\pState_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[4]_i_1__0_n_0\, + Q => pState(4), + R => SS(0) + ); +\pState_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[5]_i_1__0_n_0\, + Q => pState(5), + R => SS(0) + ); +\pState_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[6]_i_1__0_n_0\, + Q => pState(6), + R => SS(0) + ); +\pState_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[7]_i_1__0_n_0\, + Q => pState(7), + R => SS(0) + ); +\pState_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[8]_i_1__0_n_0\, + Q => pState(8), + R => SS(0) + ); +\pState_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[9]_i_1__0_n_0\, + Q => pState(9), + R => SS(0) + ); +pTknFlagQ_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pTknFlag, + Q => pTknFlagQ, + R => '0' + ); +\pTknFlag_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30000808" + ) + port map ( + I0 => \pTknFlag_i_2__0_n_0\, + I1 => \pDataQ_reg_n_0_[8]\, + I2 => \pDataQ_reg_n_0_[0]\, + I3 => \pTknFlag_i_3__0_n_0\, + I4 => \pDataQ_reg_n_0_[3]\, + O => pTknFlag0 + ); +\pTknFlag_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0002000000000000" + ) + port map ( + I0 => \pDataQ_reg_n_0_[4]\, + I1 => \pDataQ_reg_n_0_[5]\, + I2 => \pDataQ_reg_n_0_[7]\, + I3 => \pDataQ_reg_n_0_[1]\, + I4 => \pDataQ_reg_n_0_[2]\, + I5 => \pDataQ_reg_n_0_[6]\, + O => \pTknFlag_i_2__0_n_0\ + ); +\pTknFlag_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000004000" + ) + port map ( + I0 => \pDataQ_reg_n_0_[4]\, + I1 => \pDataQ_reg_n_0_[5]\, + I2 => \pDataQ_reg_n_0_[7]\, + I3 => \pDataQ_reg_n_0_[1]\, + I4 => \pDataQ_reg_n_0_[2]\, + I5 => \pDataQ_reg_n_0_[6]\, + O => \pTknFlag_i_3__0_n_0\ + ); +pTknFlag_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pTknFlag0, + Q => pTknFlag, + R => '0' + ); +\pWrA[4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"7F" + ) + port map ( + I0 => \^pvld_1\, + I1 => pVld_2, + I2 => pVld_0, + O => pMeRdy_int_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_PhaseAlign_19 is + port ( + pIDLY_CE : out STD_LOGIC; + pIDLY_INC : out STD_LOGIC; + pIDLY_LD : out STD_LOGIC; + pVld_0 : out STD_LOGIC; + pAlignErr_q_reg : out STD_LOGIC; + iIn_q_reg : out STD_LOGIC; + pAllVld : out STD_LOGIC; + pBitslip_reg : out STD_LOGIC; + PixelClk_int : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + pVld_2 : in STD_LOGIC; + pVld_1 : in STD_LOGIC; + pAlignErr_q : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 8 downto 0 ); + pIDLY_CE_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 ); + SS : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_PhaseAlign_19 : entity is "PhaseAlign"; +end Arty_Z7_20_dvi2rgb_0_0_PhaseAlign_19; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_PhaseAlign_19 is + signal \iIn_q_i_2__1_n_0\ : STD_LOGIC; + signal \iIn_q_i_3__1_n_0\ : STD_LOGIC; + signal \iIn_q_i_4__1_n_0\ : STD_LOGIC; + signal \iIn_q_i_5__1_n_0\ : STD_LOGIC; + signal \^palignerr_q_reg\ : STD_LOGIC; + signal pAligned : STD_LOGIC; + signal pBlankBegin : STD_LOGIC; + signal pBlankBegin0 : STD_LOGIC; + signal \pCenterTap[0]_i_1_n_0\ : STD_LOGIC; + signal \pCenterTap[1]_i_1__1_n_0\ : STD_LOGIC; + signal \pCenterTap[2]_i_1__1_n_0\ : STD_LOGIC; + signal \pCenterTap[3]_i_1__1_n_0\ : STD_LOGIC; + signal \pCenterTap[3]_i_2__1_n_0\ : STD_LOGIC; + signal \pCenterTap[4]_i_1__1_n_0\ : STD_LOGIC; + signal \pCenterTap[5]_i_1__1_n_0\ : STD_LOGIC; + signal \pCenterTap[5]_i_2__1_n_0\ : STD_LOGIC; + signal \pCenterTap[5]_i_3__1_n_0\ : STD_LOGIC; + signal \pCenterTap[5]_i_5__1_n_0\ : STD_LOGIC; + signal \pCenterTap_reg_n_0_[0]\ : STD_LOGIC; + signal \pCenterTap_reg_n_0_[1]\ : STD_LOGIC; + signal \pCenterTap_reg_n_0_[2]\ : STD_LOGIC; + signal \pCenterTap_reg_n_0_[3]\ : STD_LOGIC; + signal \pCenterTap_reg_n_0_[4]\ : STD_LOGIC; + signal \pCenterTap_reg_n_0_[5]\ : STD_LOGIC; + signal \pCtlTknCnt[6]_i_3__1_n_0\ : STD_LOGIC; + signal \pCtlTknCnt[6]_i_4__1_n_0\ : STD_LOGIC; + signal \pCtlTknCnt_reg__0\ : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal \pCtlTknOvf_i_1__1_n_0\ : STD_LOGIC; + signal \pCtlTknOvf_i_2__1_n_0\ : STD_LOGIC; + signal pCtlTknOvf_reg_n_0 : STD_LOGIC; + signal pCtlTknRst : STD_LOGIC; + signal \pDataQ_reg_n_0_[0]\ : STD_LOGIC; + signal \pDataQ_reg_n_0_[1]\ : STD_LOGIC; + signal \pDataQ_reg_n_0_[2]\ : STD_LOGIC; + signal \pDataQ_reg_n_0_[3]\ : STD_LOGIC; + signal \pDataQ_reg_n_0_[4]\ : STD_LOGIC; + signal \pDataQ_reg_n_0_[5]\ : STD_LOGIC; + signal \pDataQ_reg_n_0_[6]\ : STD_LOGIC; + signal \pDataQ_reg_n_0_[7]\ : STD_LOGIC; + signal \pDataQ_reg_n_0_[8]\ : STD_LOGIC; + signal \pDelayCenter_i_1__1_n_0\ : STD_LOGIC; + signal \pDelayCenter_i_2__1_n_0\ : STD_LOGIC; + signal pDelayCenter_reg_n_0 : STD_LOGIC; + signal \pDelayOvf_i_1__1_n_0\ : STD_LOGIC; + signal pDelayOvf_reg_n_0 : STD_LOGIC; + signal pDelayWaitCnt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \pDelayWaitCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \pDelayWaitCnt[0]_i_2__1_n_0\ : STD_LOGIC; + signal \pDelayWaitCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \pDelayWaitOvf_i_1__1_n_0\ : STD_LOGIC; + signal \pDelayWaitOvf_i_2__1_n_0\ : STD_LOGIC; + signal \pDelayWaitOvf_i_3__1_n_0\ : STD_LOGIC; + signal pDelayWaitOvf_reg_n_0 : STD_LOGIC; + signal pError : STD_LOGIC; + signal \pEyeOpenCnt[0]_i_1__1_n_0\ : STD_LOGIC; + signal \pEyeOpenCnt[1]_i_1__1_n_0\ : STD_LOGIC; + signal \pEyeOpenCnt[2]_i_1__1_n_0\ : STD_LOGIC; + signal \pEyeOpenCnt[3]_i_1__1_n_0\ : STD_LOGIC; + signal \pEyeOpenCnt[4]_i_1__1_n_0\ : STD_LOGIC; + signal \pEyeOpenCnt[4]_i_2__1_n_0\ : STD_LOGIC; + signal \pEyeOpenCnt[4]_i_3__1_n_0\ : STD_LOGIC; + signal \pEyeOpenCnt_reg_n_0_[0]\ : STD_LOGIC; + signal \pEyeOpenCnt_reg_n_0_[1]\ : STD_LOGIC; + signal \pEyeOpenCnt_reg_n_0_[2]\ : STD_LOGIC; + signal \pEyeOpenCnt_reg_n_0_[3]\ : STD_LOGIC; + signal \pEyeOpenCnt_reg_n_0_[4]\ : STD_LOGIC; + signal \pEyeOpenEn__5\ : STD_LOGIC; + signal pEyeOpenRst : STD_LOGIC; + signal pFoundEyeFlag : STD_LOGIC; + signal \pFoundEyeFlag_i_1__1_n_0\ : STD_LOGIC; + signal \pFoundEyeFlag_i_2__1_n_0\ : STD_LOGIC; + signal \pFoundEyeFlag_i_3__1_n_0\ : STD_LOGIC; + signal \pFoundEyeFlag_i_4__1_n_0\ : STD_LOGIC; + signal pFoundJtrFlag : STD_LOGIC; + signal \pFoundJtrFlag_i_1__1_n_0\ : STD_LOGIC; + signal pIDLY_CE_1 : STD_LOGIC; + signal \pIDLY_CNT_Q_reg_n_0_[0]\ : STD_LOGIC; + signal \pIDLY_CNT_Q_reg_n_0_[1]\ : STD_LOGIC; + signal \pIDLY_CNT_Q_reg_n_0_[2]\ : STD_LOGIC; + signal \pIDLY_CNT_Q_reg_n_0_[3]\ : STD_LOGIC; + signal \pIDLY_CNT_Q_reg_n_0_[4]\ : STD_LOGIC; + signal \^pidly_inc\ : STD_LOGIC; + signal \pIDLY_INC_i_1__1_n_0\ : STD_LOGIC; + signal pIDLY_LD_0 : STD_LOGIC; + signal \pIDLY_LD_i_2__1_n_0\ : STD_LOGIC; + signal pState : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal \pStateNxt__0_n_0\ : STD_LOGIC; + signal \pStateNxt__1_n_0\ : STD_LOGIC; + signal \pStateNxt__2_n_0\ : STD_LOGIC; + signal \pStateNxt__3_n_0\ : STD_LOGIC; + signal \pStateNxt__4\ : STD_LOGIC; + signal pStateNxt_n_0 : STD_LOGIC; + signal \pState[0]_i_1__1_n_0\ : STD_LOGIC; + signal \pState[10]_i_2__1_n_0\ : STD_LOGIC; + signal \pState[10]_i_3__1_n_0\ : STD_LOGIC; + signal \pState[10]_i_4__1_n_0\ : STD_LOGIC; + signal \pState[10]_i_5__1_n_0\ : STD_LOGIC; + signal \pState[10]_i_6__1_n_0\ : STD_LOGIC; + signal \pState[1]_i_1__1_n_0\ : STD_LOGIC; + signal \pState[2]_i_1__1_n_0\ : STD_LOGIC; + signal \pState[3]_i_1__1_n_0\ : STD_LOGIC; + signal \pState[4]_i_1__1_n_0\ : STD_LOGIC; + signal \pState[5]_i_1__1_n_0\ : STD_LOGIC; + signal \pState[5]_i_2__1_n_0\ : STD_LOGIC; + signal \pState[6]_i_1__1_n_0\ : STD_LOGIC; + signal \pState[7]_i_1__1_n_0\ : STD_LOGIC; + signal \pState[8]_i_1__1_n_0\ : STD_LOGIC; + signal \pState[9]_i_1__1_n_0\ : STD_LOGIC; + signal pTknFlag : STD_LOGIC; + signal pTknFlag0 : STD_LOGIC; + signal pTknFlagQ : STD_LOGIC; + signal \pTknFlag_i_2__1_n_0\ : STD_LOGIC; + signal \pTknFlag_i_3__1_n_0\ : STD_LOGIC; + signal \^pvld_0\ : STD_LOGIC; + signal p_0_in : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal p_2_in : STD_LOGIC; + signal \plusOp__16\ : STD_LOGIC_VECTOR ( 5 downto 4 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \iIn_q_i_2__1\ : label is "soft_lutpair13"; + attribute SOFT_HLUTNM of \iIn_q_i_3__1\ : label is "soft_lutpair14"; + attribute SOFT_HLUTNM of \iIn_q_i_5__1\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \pAligned_i_1__1\ : label is "soft_lutpair19"; + attribute SOFT_HLUTNM of \pCenterTap[1]_i_1__1\ : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of \pCenterTap[3]_i_2__1\ : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of \pCtlTknCnt[0]_i_1__1\ : label is "soft_lutpair24"; + attribute SOFT_HLUTNM of \pCtlTknCnt[1]_i_1__1\ : label is "soft_lutpair24"; + attribute SOFT_HLUTNM of \pCtlTknCnt[2]_i_1__1\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \pCtlTknCnt[3]_i_1__1\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \pCtlTknCnt[4]_i_1__1\ : label is "soft_lutpair16"; + attribute SOFT_HLUTNM of \pCtlTknCnt[6]_i_2__1\ : label is "soft_lutpair17"; + attribute SOFT_HLUTNM of \pCtlTknCnt[6]_i_4__1\ : label is "soft_lutpair16"; + attribute SOFT_HLUTNM of \pCtlTknOvf_i_2__1\ : label is "soft_lutpair17"; + attribute SOFT_HLUTNM of \pDelayWaitCnt[1]_i_1\ : label is "soft_lutpair20"; + attribute SOFT_HLUTNM of \pDelayWaitOvf_i_2__1\ : label is "soft_lutpair22"; + attribute SOFT_HLUTNM of \pDelayWaitOvf_i_3__1\ : label is "soft_lutpair20"; + attribute SOFT_HLUTNM of \pError_i_1__1\ : label is "soft_lutpair19"; + attribute SOFT_HLUTNM of \pEyeOpenCnt[1]_i_1__1\ : label is "soft_lutpair11"; + attribute SOFT_HLUTNM of \pEyeOpenCnt[2]_i_1__1\ : label is "soft_lutpair11"; + attribute SOFT_HLUTNM of \pEyeOpenCnt[4]_i_4__1\ : label is "soft_lutpair9"; + attribute SOFT_HLUTNM of \pFoundEyeFlag_i_4__1\ : label is "soft_lutpair15"; + attribute SOFT_HLUTNM of \pFoundJtrFlag_i_1__1\ : label is "soft_lutpair13"; + attribute SOFT_HLUTNM of \pIDLY_LD_i_1__1\ : label is "soft_lutpair9"; + attribute SOFT_HLUTNM of \pIDLY_LD_i_2__1\ : label is "soft_lutpair14"; + attribute SOFT_HLUTNM of pStateNxt : label is "soft_lutpair12"; + attribute SOFT_HLUTNM of \pStateNxt__0\ : label is "soft_lutpair12"; + attribute SOFT_HLUTNM of \pState[10]_i_2__1\ : label is "soft_lutpair22"; + attribute SOFT_HLUTNM of \pState[10]_i_3__1\ : label is "soft_lutpair21"; + attribute SOFT_HLUTNM of \pState[2]_i_1__1\ : label is "soft_lutpair10"; + attribute SOFT_HLUTNM of \pState[3]_i_1__1\ : label is "soft_lutpair21"; + attribute SOFT_HLUTNM of \pState[4]_i_1__1\ : label is "soft_lutpair10"; + attribute SOFT_HLUTNM of \pState[5]_i_2__1\ : label is "soft_lutpair15"; + attribute SOFT_HLUTNM of \pState[6]_i_1__1\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \pState[7]_i_1__1\ : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of \pState[9]_i_1__1\ : label is "soft_lutpair8"; +begin + pAlignErr_q_reg <= \^palignerr_q_reg\; + pIDLY_INC <= \^pidly_inc\; + pVld_0 <= \^pvld_0\; +\iIn_q_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFEFFFEFFFF" + ) + port map ( + I0 => \iIn_q_i_2__1_n_0\, + I1 => \iIn_q_i_3__1_n_0\, + I2 => \iIn_q_i_4__1_n_0\, + I3 => \iIn_q_i_5__1_n_0\, + I4 => pState(1), + I5 => pState(2), + O => iIn_q_reg + ); +\iIn_q_i_2__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => pState(4), + I1 => pState(0), + I2 => pState(3), + O => \iIn_q_i_2__1_n_0\ + ); +\iIn_q_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => pState(6), + I1 => pState(8), + O => \iIn_q_i_3__1_n_0\ + ); +\iIn_q_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => pState(9), + I1 => pState(10), + O => \iIn_q_i_4__1_n_0\ + ); +\iIn_q_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => pState(5), + I1 => pState(7), + O => \iIn_q_i_5__1_n_0\ + ); +\pAligned_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0004" + ) + port map ( + I0 => pState(2), + I1 => pState(9), + I2 => pState(10), + I3 => \pCtlTknCnt[6]_i_3__1_n_0\, + O => pAligned + ); +pAligned_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pAligned, + Q => \^pvld_0\, + R => '0' + ); +\pBitslip_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^palignerr_q_reg\, + I1 => pAlignErr_q, + O => pBitslip_reg + ); +\pBlankBegin_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => pTknFlag, + I1 => pTknFlagQ, + O => pBlankBegin0 + ); +pBlankBegin_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pBlankBegin0, + Q => pBlankBegin, + R => '0' + ); +\pCenterTap[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAA5AAAAAFBA" + ) + port map ( + I0 => \pCenterTap_reg_n_0_[0]\, + I1 => pFoundEyeFlag, + I2 => pState(4), + I3 => pState(0), + I4 => \pCenterTap[5]_i_3__1_n_0\, + I5 => pState(3), + O => \pCenterTap[0]_i_1_n_0\ + ); +\pCenterTap[1]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FF606060" + ) + port map ( + I0 => \pCenterTap_reg_n_0_[0]\, + I1 => \pCenterTap_reg_n_0_[1]\, + I2 => \pCenterTap[5]_i_5__1_n_0\, + I3 => \pIDLY_CNT_Q_reg_n_0_[0]\, + I4 => pEyeOpenRst, + O => \pCenterTap[1]_i_1__1_n_0\ + ); +\pCenterTap[2]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF780078007800" + ) + port map ( + I0 => \pCenterTap_reg_n_0_[1]\, + I1 => \pCenterTap_reg_n_0_[0]\, + I2 => \pCenterTap_reg_n_0_[2]\, + I3 => \pCenterTap[5]_i_5__1_n_0\, + I4 => \pIDLY_CNT_Q_reg_n_0_[1]\, + I5 => pEyeOpenRst, + O => \pCenterTap[2]_i_1__1_n_0\ + ); +\pCenterTap[3]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF780078007800" + ) + port map ( + I0 => \pCenterTap_reg_n_0_[2]\, + I1 => \pCenterTap[3]_i_2__1_n_0\, + I2 => \pCenterTap_reg_n_0_[3]\, + I3 => \pCenterTap[5]_i_5__1_n_0\, + I4 => \pIDLY_CNT_Q_reg_n_0_[2]\, + I5 => pEyeOpenRst, + O => \pCenterTap[3]_i_1__1_n_0\ + ); +\pCenterTap[3]_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \pCenterTap_reg_n_0_[0]\, + I1 => \pCenterTap_reg_n_0_[1]\, + O => \pCenterTap[3]_i_2__1_n_0\ + ); +\pCenterTap[4]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F888" + ) + port map ( + I0 => \plusOp__16\(4), + I1 => \pCenterTap[5]_i_5__1_n_0\, + I2 => \pIDLY_CNT_Q_reg_n_0_[3]\, + I3 => pEyeOpenRst, + O => \pCenterTap[4]_i_1__1_n_0\ + ); +\pCenterTap[4]_i_2__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \pCenterTap_reg_n_0_[0]\, + I1 => \pCenterTap_reg_n_0_[1]\, + I2 => \pCenterTap_reg_n_0_[2]\, + I3 => \pCenterTap_reg_n_0_[3]\, + I4 => \pCenterTap_reg_n_0_[4]\, + O => \plusOp__16\(4) + ); +\pCenterTap[5]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00030034" + ) + port map ( + I0 => pFoundEyeFlag, + I1 => pState(4), + I2 => pState(0), + I3 => \pCenterTap[5]_i_3__1_n_0\, + I4 => pState(3), + O => \pCenterTap[5]_i_1__1_n_0\ + ); +\pCenterTap[5]_i_2__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F888" + ) + port map ( + I0 => \plusOp__16\(5), + I1 => \pCenterTap[5]_i_5__1_n_0\, + I2 => \pIDLY_CNT_Q_reg_n_0_[4]\, + I3 => pEyeOpenRst, + O => \pCenterTap[5]_i_2__1_n_0\ + ); +\pCenterTap[5]_i_3__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => pState(5), + I1 => pState(7), + I2 => pState(8), + I3 => pState(6), + I4 => pState(1), + I5 => \pState[10]_i_3__1_n_0\, + O => \pCenterTap[5]_i_3__1_n_0\ + ); +\pCenterTap[5]_i_4__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFFFFFF80000000" + ) + port map ( + I0 => \pCenterTap_reg_n_0_[0]\, + I1 => \pCenterTap_reg_n_0_[1]\, + I2 => \pCenterTap_reg_n_0_[4]\, + I3 => \pCenterTap_reg_n_0_[3]\, + I4 => \pCenterTap_reg_n_0_[2]\, + I5 => \pCenterTap_reg_n_0_[5]\, + O => \plusOp__16\(5) + ); +\pCenterTap[5]_i_5__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFEFEFEFFFF" + ) + port map ( + I0 => pState(3), + I1 => \pIDLY_LD_i_2__1_n_0\, + I2 => \pState[10]_i_3__1_n_0\, + I3 => pFoundEyeFlag, + I4 => pState(0), + I5 => pState(4), + O => \pCenterTap[5]_i_5__1_n_0\ + ); +\pCenterTap[5]_i_6__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000010000010100" + ) + port map ( + I0 => pState(3), + I1 => \pIDLY_LD_i_2__1_n_0\, + I2 => \pState[10]_i_3__1_n_0\, + I3 => pState(0), + I4 => pState(4), + I5 => pFoundEyeFlag, + O => pEyeOpenRst + ); +\pCenterTap_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pCenterTap[0]_i_1_n_0\, + Q => \pCenterTap_reg_n_0_[0]\, + R => '0' + ); +\pCenterTap_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pCenterTap[5]_i_1__1_n_0\, + D => \pCenterTap[1]_i_1__1_n_0\, + Q => \pCenterTap_reg_n_0_[1]\, + R => '0' + ); +\pCenterTap_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pCenterTap[5]_i_1__1_n_0\, + D => \pCenterTap[2]_i_1__1_n_0\, + Q => \pCenterTap_reg_n_0_[2]\, + R => '0' + ); +\pCenterTap_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pCenterTap[5]_i_1__1_n_0\, + D => \pCenterTap[3]_i_1__1_n_0\, + Q => \pCenterTap_reg_n_0_[3]\, + R => '0' + ); +\pCenterTap_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pCenterTap[5]_i_1__1_n_0\, + D => \pCenterTap[4]_i_1__1_n_0\, + Q => \pCenterTap_reg_n_0_[4]\, + R => '0' + ); +\pCenterTap_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pCenterTap[5]_i_1__1_n_0\, + D => \pCenterTap[5]_i_2__1_n_0\, + Q => \pCenterTap_reg_n_0_[5]\, + R => '0' + ); +\pCtlTknCnt[0]_i_1__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \pCtlTknCnt_reg__0\(0), + O => p_0_in(0) + ); +\pCtlTknCnt[1]_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \pCtlTknCnt_reg__0\(0), + I1 => \pCtlTknCnt_reg__0\(1), + O => p_0_in(1) + ); +\pCtlTknCnt[2]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \pCtlTknCnt_reg__0\(1), + I1 => \pCtlTknCnt_reg__0\(0), + I2 => \pCtlTknCnt_reg__0\(2), + O => p_0_in(2) + ); +\pCtlTknCnt[3]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \pCtlTknCnt_reg__0\(2), + I1 => \pCtlTknCnt_reg__0\(0), + I2 => \pCtlTknCnt_reg__0\(1), + I3 => \pCtlTknCnt_reg__0\(3), + O => p_0_in(3) + ); +\pCtlTknCnt[4]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \pCtlTknCnt_reg__0\(3), + I1 => \pCtlTknCnt_reg__0\(1), + I2 => \pCtlTknCnt_reg__0\(0), + I3 => \pCtlTknCnt_reg__0\(2), + I4 => \pCtlTknCnt_reg__0\(4), + O => p_0_in(4) + ); +\pCtlTknCnt[5]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFFFFFF80000000" + ) + port map ( + I0 => \pCtlTknCnt_reg__0\(4), + I1 => \pCtlTknCnt_reg__0\(2), + I2 => \pCtlTknCnt_reg__0\(0), + I3 => \pCtlTknCnt_reg__0\(1), + I4 => \pCtlTknCnt_reg__0\(3), + I5 => \pCtlTknCnt_reg__0\(5), + O => p_0_in(5) + ); +\pCtlTknCnt[6]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFD" + ) + port map ( + I0 => pState(2), + I1 => pState(9), + I2 => pState(10), + I3 => \pCtlTknCnt[6]_i_3__1_n_0\, + O => pCtlTknRst + ); +\pCtlTknCnt[6]_i_2__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \pCtlTknCnt[6]_i_4__1_n_0\, + I1 => \pCtlTknCnt_reg__0\(4), + I2 => \pCtlTknCnt_reg__0\(5), + I3 => \pCtlTknCnt_reg__0\(6), + O => p_0_in(6) + ); +\pCtlTknCnt[6]_i_3__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => \iIn_q_i_2__1_n_0\, + I1 => pState(5), + I2 => pState(7), + I3 => pState(8), + I4 => pState(6), + I5 => pState(1), + O => \pCtlTknCnt[6]_i_3__1_n_0\ + ); +\pCtlTknCnt[6]_i_4__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => \pCtlTknCnt_reg__0\(2), + I1 => \pCtlTknCnt_reg__0\(0), + I2 => \pCtlTknCnt_reg__0\(1), + I3 => \pCtlTknCnt_reg__0\(3), + O => \pCtlTknCnt[6]_i_4__1_n_0\ + ); +\pCtlTknCnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_in(0), + Q => \pCtlTknCnt_reg__0\(0), + R => pCtlTknRst + ); +\pCtlTknCnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_in(1), + Q => \pCtlTknCnt_reg__0\(1), + R => pCtlTknRst + ); +\pCtlTknCnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_in(2), + Q => \pCtlTknCnt_reg__0\(2), + R => pCtlTknRst + ); +\pCtlTknCnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_in(3), + Q => \pCtlTknCnt_reg__0\(3), + R => pCtlTknRst + ); +\pCtlTknCnt_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_in(4), + Q => \pCtlTknCnt_reg__0\(4), + R => pCtlTknRst + ); +\pCtlTknCnt_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_in(5), + Q => \pCtlTknCnt_reg__0\(5), + R => pCtlTknRst + ); +\pCtlTknCnt_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => p_0_in(6), + Q => \pCtlTknCnt_reg__0\(6), + R => pCtlTknRst + ); +\pCtlTknOvf_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAEAAAAAAA2" + ) + port map ( + I0 => pCtlTknOvf_reg_n_0, + I1 => pState(2), + I2 => pState(9), + I3 => pState(10), + I4 => \pCtlTknCnt[6]_i_3__1_n_0\, + I5 => \pCtlTknOvf_i_2__1_n_0\, + O => \pCtlTknOvf_i_1__1_n_0\ + ); +\pCtlTknOvf_i_2__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => \pCtlTknCnt_reg__0\(4), + I1 => \pCtlTknCnt_reg__0\(5), + I2 => \pCtlTknCnt_reg__0\(6), + I3 => \pCtlTknCnt[6]_i_4__1_n_0\, + O => \pCtlTknOvf_i_2__1_n_0\ + ); +pCtlTknOvf_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pCtlTknOvf_i_1__1_n_0\, + Q => pCtlTknOvf_reg_n_0, + R => '0' + ); +\pDataQ_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => D(0), + Q => \pDataQ_reg_n_0_[0]\, + R => '0' + ); +\pDataQ_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => D(1), + Q => \pDataQ_reg_n_0_[1]\, + R => '0' + ); +\pDataQ_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => D(2), + Q => \pDataQ_reg_n_0_[2]\, + R => '0' + ); +\pDataQ_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => D(3), + Q => \pDataQ_reg_n_0_[3]\, + R => '0' + ); +\pDataQ_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => D(4), + Q => \pDataQ_reg_n_0_[4]\, + R => '0' + ); +\pDataQ_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => D(5), + Q => \pDataQ_reg_n_0_[5]\, + R => '0' + ); +\pDataQ_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => D(6), + Q => \pDataQ_reg_n_0_[6]\, + R => '0' + ); +\pDataQ_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => D(7), + Q => \pDataQ_reg_n_0_[7]\, + R => '0' + ); +\pDataQ_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => D(8), + Q => \pDataQ_reg_n_0_[8]\, + R => '0' + ); +\pDelayCenter_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"82000082" + ) + port map ( + I0 => \pDelayCenter_i_2__1_n_0\, + I1 => \pCenterTap_reg_n_0_[5]\, + I2 => \pIDLY_CNT_Q_reg_n_0_[4]\, + I3 => \pCenterTap_reg_n_0_[4]\, + I4 => \pIDLY_CNT_Q_reg_n_0_[3]\, + O => \pDelayCenter_i_1__1_n_0\ + ); +\pDelayCenter_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \pCenterTap_reg_n_0_[3]\, + I1 => \pIDLY_CNT_Q_reg_n_0_[2]\, + I2 => \pCenterTap_reg_n_0_[2]\, + I3 => \pIDLY_CNT_Q_reg_n_0_[1]\, + I4 => \pIDLY_CNT_Q_reg_n_0_[0]\, + I5 => \pCenterTap_reg_n_0_[1]\, + O => \pDelayCenter_i_2__1_n_0\ + ); +pDelayCenter_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pDelayCenter_i_1__1_n_0\, + Q => pDelayCenter_reg_n_0, + R => '0' + ); +\pDelayOvf_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000001" + ) + port map ( + I0 => \pIDLY_CNT_Q_reg_n_0_[0]\, + I1 => \pIDLY_CNT_Q_reg_n_0_[1]\, + I2 => \pIDLY_CNT_Q_reg_n_0_[2]\, + I3 => \pIDLY_CNT_Q_reg_n_0_[4]\, + I4 => \pIDLY_CNT_Q_reg_n_0_[3]\, + O => \pDelayOvf_i_1__1_n_0\ + ); +pDelayOvf_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pDelayOvf_i_1__1_n_0\, + Q => pDelayOvf_reg_n_0, + R => '0' + ); +\pDelayWaitCnt[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000001400000000" + ) + port map ( + I0 => pDelayWaitCnt(0), + I1 => pState(6), + I2 => pState(8), + I3 => \iIn_q_i_5__1_n_0\, + I4 => pState(1), + I5 => \pDelayWaitCnt[0]_i_2__1_n_0\, + O => \pDelayWaitCnt[0]_i_1_n_0\ + ); +\pDelayWaitCnt[0]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000001" + ) + port map ( + I0 => pState(3), + I1 => pState(0), + I2 => pState(4), + I3 => pState(2), + I4 => pState(9), + I5 => pState(10), + O => \pDelayWaitCnt[0]_i_2__1_n_0\ + ); +\pDelayWaitCnt[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"60" + ) + port map ( + I0 => pDelayWaitCnt(1), + I1 => pDelayWaitCnt(0), + I2 => p_2_in, + O => \pDelayWaitCnt[1]_i_1_n_0\ + ); +\pDelayWaitCnt[1]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000600000000" + ) + port map ( + I0 => pState(6), + I1 => pState(8), + I2 => pState(7), + I3 => pState(5), + I4 => pState(1), + I5 => \pDelayWaitCnt[0]_i_2__1_n_0\, + O => p_2_in + ); +\pDelayWaitCnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pDelayWaitCnt[0]_i_1_n_0\, + Q => pDelayWaitCnt(0), + R => '0' + ); +\pDelayWaitCnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pDelayWaitCnt[1]_i_1_n_0\, + Q => pDelayWaitCnt(1), + R => '0' + ); +\pDelayWaitOvf_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CCFCCCCCCC8CCCCC" + ) + port map ( + I0 => pState(1), + I1 => pDelayWaitOvf_reg_n_0, + I2 => \pDelayWaitCnt[0]_i_2__1_n_0\, + I3 => \iIn_q_i_5__1_n_0\, + I4 => \pDelayWaitOvf_i_2__1_n_0\, + I5 => \pDelayWaitOvf_i_3__1_n_0\, + O => \pDelayWaitOvf_i_1__1_n_0\ + ); +\pDelayWaitOvf_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => pState(6), + I1 => pState(8), + O => \pDelayWaitOvf_i_2__1_n_0\ + ); +\pDelayWaitOvf_i_3__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => pState(1), + I1 => pDelayWaitCnt(1), + I2 => pDelayWaitCnt(0), + O => \pDelayWaitOvf_i_3__1_n_0\ + ); +pDelayWaitOvf_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pDelayWaitOvf_i_1__1_n_0\, + Q => pDelayWaitOvf_reg_n_0, + R => '0' + ); +\pError_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0004" + ) + port map ( + I0 => pState(2), + I1 => pState(10), + I2 => pState(9), + I3 => \pCtlTknCnt[6]_i_3__1_n_0\, + O => pError + ); +pError_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pError, + Q => \^palignerr_q_reg\, + R => '0' + ); +\pEyeOpenCnt[0]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CCCCCCCCCCC3C80C" + ) + port map ( + I0 => pFoundEyeFlag, + I1 => \pEyeOpenCnt_reg_n_0_[0]\, + I2 => pState(0), + I3 => pState(4), + I4 => pState(3), + I5 => \pCenterTap[5]_i_3__1_n_0\, + O => \pEyeOpenCnt[0]_i_1__1_n_0\ + ); +\pEyeOpenCnt[1]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BCA0" + ) + port map ( + I0 => \pEyeOpenCnt[4]_i_2__1_n_0\, + I1 => \pEyeOpenCnt_reg_n_0_[0]\, + I2 => \pEyeOpenCnt_reg_n_0_[1]\, + I3 => \pEyeOpenEn__5\, + O => \pEyeOpenCnt[1]_i_1__1_n_0\ + ); +\pEyeOpenCnt[2]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFC0AA00" + ) + port map ( + I0 => \pEyeOpenCnt[4]_i_2__1_n_0\, + I1 => \pEyeOpenCnt_reg_n_0_[1]\, + I2 => \pEyeOpenCnt_reg_n_0_[0]\, + I3 => \pEyeOpenCnt_reg_n_0_[2]\, + I4 => \pEyeOpenEn__5\, + O => \pEyeOpenCnt[2]_i_1__1_n_0\ + ); +\pEyeOpenCnt[3]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BFFFC000AAAA0000" + ) + port map ( + I0 => \pEyeOpenCnt[4]_i_2__1_n_0\, + I1 => \pEyeOpenCnt_reg_n_0_[0]\, + I2 => \pEyeOpenCnt_reg_n_0_[1]\, + I3 => \pEyeOpenCnt_reg_n_0_[2]\, + I4 => \pEyeOpenCnt_reg_n_0_[3]\, + I5 => \pEyeOpenEn__5\, + O => \pEyeOpenCnt[3]_i_1__1_n_0\ + ); +\pEyeOpenCnt[4]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BFFFC000AAAA0000" + ) + port map ( + I0 => \pEyeOpenCnt[4]_i_2__1_n_0\, + I1 => \pEyeOpenCnt_reg_n_0_[2]\, + I2 => \pEyeOpenCnt_reg_n_0_[3]\, + I3 => \pEyeOpenCnt[4]_i_3__1_n_0\, + I4 => \pEyeOpenCnt_reg_n_0_[4]\, + I5 => \pEyeOpenEn__5\, + O => \pEyeOpenCnt[4]_i_1__1_n_0\ + ); +\pEyeOpenCnt[4]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFEFEFEFDFD" + ) + port map ( + I0 => pState(3), + I1 => \pIDLY_LD_i_2__1_n_0\, + I2 => \pState[10]_i_3__1_n_0\, + I3 => pFoundEyeFlag, + I4 => pState(0), + I5 => pState(4), + O => \pEyeOpenCnt[4]_i_2__1_n_0\ + ); +\pEyeOpenCnt[4]_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \pEyeOpenCnt_reg_n_0_[0]\, + I1 => \pEyeOpenCnt_reg_n_0_[1]\, + O => \pEyeOpenCnt[4]_i_3__1_n_0\ + ); +\pEyeOpenCnt[4]_i_4__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000010" + ) + port map ( + I0 => pState(0), + I1 => pState(4), + I2 => pState(3), + I3 => \pState[10]_i_3__1_n_0\, + I4 => \pIDLY_LD_i_2__1_n_0\, + O => \pEyeOpenEn__5\ + ); +\pEyeOpenCnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pEyeOpenCnt[0]_i_1__1_n_0\, + Q => \pEyeOpenCnt_reg_n_0_[0]\, + R => '0' + ); +\pEyeOpenCnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pEyeOpenCnt[1]_i_1__1_n_0\, + Q => \pEyeOpenCnt_reg_n_0_[1]\, + R => '0' + ); +\pEyeOpenCnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pEyeOpenCnt[2]_i_1__1_n_0\, + Q => \pEyeOpenCnt_reg_n_0_[2]\, + R => '0' + ); +\pEyeOpenCnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pEyeOpenCnt[3]_i_1__1_n_0\, + Q => \pEyeOpenCnt_reg_n_0_[3]\, + R => '0' + ); +\pEyeOpenCnt_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pEyeOpenCnt[4]_i_1__1_n_0\, + Q => \pEyeOpenCnt_reg_n_0_[4]\, + R => '0' + ); +pFIFO_reg_0_31_0_5_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \^pvld_0\, + I1 => pVld_2, + I2 => pVld_1, + O => pAllVld + ); +\pFoundEyeFlag_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ABBBA888" + ) + port map ( + I0 => \pFoundEyeFlag_i_2__1_n_0\, + I1 => pIDLY_LD_0, + I2 => \pEyeOpenEn__5\, + I3 => \pFoundEyeFlag_i_3__1_n_0\, + I4 => pFoundEyeFlag, + O => \pFoundEyeFlag_i_1__1_n_0\ + ); +\pFoundEyeFlag_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1000004000000040" + ) + port map ( + I0 => \pFoundEyeFlag_i_4__1_n_0\, + I1 => \pEyeOpenCnt_reg_n_0_[4]\, + I2 => pState(3), + I3 => \pEyeOpenCnt_reg_n_0_[0]\, + I4 => \pEyeOpenCnt_reg_n_0_[1]\, + I5 => pFoundJtrFlag, + O => \pFoundEyeFlag_i_2__1_n_0\ + ); +\pFoundEyeFlag_i_3__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0100001000000010" + ) + port map ( + I0 => \pEyeOpenCnt_reg_n_0_[2]\, + I1 => \pEyeOpenCnt_reg_n_0_[3]\, + I2 => \pEyeOpenCnt_reg_n_0_[4]\, + I3 => \pEyeOpenCnt_reg_n_0_[0]\, + I4 => \pEyeOpenCnt_reg_n_0_[1]\, + I5 => pFoundJtrFlag, + O => \pFoundEyeFlag_i_3__1_n_0\ + ); +\pFoundEyeFlag_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \pEyeOpenCnt_reg_n_0_[2]\, + I1 => \pEyeOpenCnt_reg_n_0_[3]\, + O => \pFoundEyeFlag_i_4__1_n_0\ + ); +pFoundEyeFlag_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pFoundEyeFlag_i_1__1_n_0\, + Q => pFoundEyeFlag, + R => '0' + ); +\pFoundJtrFlag_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FEFF0010" + ) + port map ( + I0 => pState(3), + I1 => \pCenterTap[5]_i_3__1_n_0\, + I2 => pState(4), + I3 => pState(0), + I4 => pFoundJtrFlag, + O => \pFoundJtrFlag_i_1__1_n_0\ + ); +pFoundJtrFlag_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pFoundJtrFlag_i_1__1_n_0\, + Q => pFoundJtrFlag, + R => '0' + ); +\pIDLY_CE_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000200020000" + ) + port map ( + I0 => \pDelayWaitCnt[0]_i_2__1_n_0\, + I1 => pState(1), + I2 => pState(6), + I3 => pState(8), + I4 => pState(5), + I5 => pState(7), + O => pIDLY_CE_1 + ); +pIDLY_CE_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pIDLY_CE_1, + Q => pIDLY_CE, + R => '0' + ); +\pIDLY_CNT_Q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pIDLY_CE_reg_0(0), + Q => \pIDLY_CNT_Q_reg_n_0_[0]\, + R => '0' + ); +\pIDLY_CNT_Q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pIDLY_CE_reg_0(1), + Q => \pIDLY_CNT_Q_reg_n_0_[1]\, + R => '0' + ); +\pIDLY_CNT_Q_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pIDLY_CE_reg_0(2), + Q => \pIDLY_CNT_Q_reg_n_0_[2]\, + R => '0' + ); +\pIDLY_CNT_Q_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pIDLY_CE_reg_0(3), + Q => \pIDLY_CNT_Q_reg_n_0_[3]\, + R => '0' + ); +\pIDLY_CNT_Q_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pIDLY_CE_reg_0(4), + Q => \pIDLY_CNT_Q_reg_n_0_[4]\, + R => '0' + ); +\pIDLY_INC_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAA2AAAEAAAA" + ) + port map ( + I0 => \^pidly_inc\, + I1 => \pDelayWaitCnt[0]_i_2__1_n_0\, + I2 => pState(1), + I3 => \iIn_q_i_3__1_n_0\, + I4 => pState(5), + I5 => pState(7), + O => \pIDLY_INC_i_1__1_n_0\ + ); +pIDLY_INC_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => \pIDLY_INC_i_1__1_n_0\, + Q => \^pidly_inc\, + R => '0' + ); +\pIDLY_LD_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000004" + ) + port map ( + I0 => pState(4), + I1 => pState(0), + I2 => pState(3), + I3 => \pIDLY_LD_i_2__1_n_0\, + I4 => \pState[10]_i_3__1_n_0\, + O => pIDLY_LD_0 + ); +\pIDLY_LD_i_2__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => pState(1), + I1 => pState(6), + I2 => pState(8), + I3 => pState(7), + I4 => pState(5), + O => \pIDLY_LD_i_2__1_n_0\ + ); +pIDLY_LD_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pIDLY_LD_0, + Q => pIDLY_LD, + R => '0' + ); +pStateNxt: unisim.vcomponents.LUT5 + generic map( + INIT => X"00010116" + ) + port map ( + I0 => pState(0), + I1 => pState(1), + I2 => pState(2), + I3 => pState(3), + I4 => pState(4), + O => pStateNxt_n_0 + ); +\pStateNxt__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFEFEE8" + ) + port map ( + I0 => pState(0), + I1 => pState(1), + I2 => pState(2), + I3 => pState(3), + I4 => pState(4), + O => \pStateNxt__0_n_0\ + ); +\pStateNxt__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000100010116" + ) + port map ( + I0 => pState(5), + I1 => pState(6), + I2 => pState(7), + I3 => pState(8), + I4 => pState(9), + I5 => pState(10), + O => \pStateNxt__1_n_0\ + ); +\pStateNxt__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFEFFFEFEE8" + ) + port map ( + I0 => pState(5), + I1 => pState(6), + I2 => pState(7), + I3 => pState(8), + I4 => pState(9), + I5 => pState(10), + O => \pStateNxt__2_n_0\ + ); +\pStateNxt__3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0012" + ) + port map ( + I0 => pStateNxt_n_0, + I1 => \pStateNxt__0_n_0\, + I2 => \pStateNxt__1_n_0\, + I3 => \pStateNxt__2_n_0\, + O => \pStateNxt__3_n_0\ + ); +\pState[0]_i_1__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \pStateNxt__3_n_0\, + O => \pState[0]_i_1__1_n_0\ + ); +\pState[10]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFC8" + ) + port map ( + I0 => \pState[10]_i_3__1_n_0\, + I1 => \iIn_q_i_3__1_n_0\, + I2 => pDelayWaitOvf_reg_n_0, + I3 => \pState[10]_i_4__1_n_0\, + I4 => \pState[10]_i_5__1_n_0\, + I5 => \pState[10]_i_6__1_n_0\, + O => \pStateNxt__4\ + ); +\pState[10]_i_2__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => pDelayOvf_reg_n_0, + I1 => pState(6), + I2 => \pStateNxt__3_n_0\, + O => \pState[10]_i_2__1_n_0\ + ); +\pState[10]_i_3__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => pState(10), + I1 => pState(9), + I2 => pState(2), + O => \pState[10]_i_3__1_n_0\ + ); +\pState[10]_i_4__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8888888889898988" + ) + port map ( + I0 => pState(10), + I1 => pState(9), + I2 => pState(2), + I3 => \out\(0), + I4 => pBlankBegin, + I5 => \iIn_q_i_3__1_n_0\, + O => \pState[10]_i_4__1_n_0\ + ); +\pState[10]_i_5__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFD00FD00FD00" + ) + port map ( + I0 => pTknFlagQ, + I1 => pCtlTknOvf_reg_n_0, + I2 => \iIn_q_i_4__1_n_0\, + I3 => pState(2), + I4 => pState(6), + I5 => pState(8), + O => \pState[10]_i_5__1_n_0\ + ); +\pState[10]_i_6__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFEFEFEEF" + ) + port map ( + I0 => pState(5), + I1 => pState(7), + I2 => pState(1), + I3 => \iIn_q_i_3__1_n_0\, + I4 => \pState[10]_i_3__1_n_0\, + I5 => \iIn_q_i_2__1_n_0\, + O => \pState[10]_i_6__1_n_0\ + ); +\pState[1]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF4F4400000000" + ) + port map ( + I0 => pDelayOvf_reg_n_0, + I1 => pState(6), + I2 => pTknFlagQ, + I3 => pState(2), + I4 => pState(0), + I5 => \pStateNxt__3_n_0\, + O => \pState[1]_i_1__1_n_0\ + ); +\pState[2]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => pBlankBegin, + I1 => pState(1), + I2 => \pStateNxt__3_n_0\, + O => \pState[2]_i_1__1_n_0\ + ); +\pState[3]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => pState(2), + I1 => pTknFlagQ, + I2 => \pStateNxt__3_n_0\, + O => \pState[3]_i_1__1_n_0\ + ); +\pState[4]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"4040F040" + ) + port map ( + I0 => \pState[5]_i_2__1_n_0\, + I1 => pState(3), + I2 => \pStateNxt__3_n_0\, + I3 => pState(1), + I4 => pBlankBegin, + O => \pState[4]_i_1__1_n_0\ + ); +\pState[5]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"8080F080" + ) + port map ( + I0 => pState(3), + I1 => \pState[5]_i_2__1_n_0\, + I2 => \pStateNxt__3_n_0\, + I3 => pState(4), + I4 => pFoundEyeFlag, + O => \pState[5]_i_1__1_n_0\ + ); +\pState[5]_i_2__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFEFF" + ) + port map ( + I0 => \pEyeOpenCnt_reg_n_0_[0]\, + I1 => \pEyeOpenCnt_reg_n_0_[2]\, + I2 => \pEyeOpenCnt_reg_n_0_[3]\, + I3 => \pEyeOpenCnt_reg_n_0_[4]\, + I4 => \pEyeOpenCnt_reg_n_0_[1]\, + O => \pState[5]_i_2__1_n_0\ + ); +\pState[6]_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => pState(5), + I1 => \pStateNxt__3_n_0\, + O => \pState[6]_i_1__1_n_0\ + ); +\pState[7]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F0202020" + ) + port map ( + I0 => pState(8), + I1 => pDelayCenter_reg_n_0, + I2 => \pStateNxt__3_n_0\, + I3 => pState(4), + I4 => pFoundEyeFlag, + O => \pState[7]_i_1__1_n_0\ + ); +\pState[8]_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => pState(7), + I1 => \pStateNxt__3_n_0\, + O => \pState[8]_i_1__1_n_0\ + ); +\pState[9]_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => pDelayCenter_reg_n_0, + I1 => pState(8), + I2 => \pStateNxt__3_n_0\, + O => \pState[9]_i_1__1_n_0\ + ); +\pState_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[0]_i_1__1_n_0\, + Q => pState(0), + S => SS(0) + ); +\pState_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[10]_i_2__1_n_0\, + Q => pState(10), + R => SS(0) + ); +\pState_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[1]_i_1__1_n_0\, + Q => pState(1), + R => SS(0) + ); +\pState_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[2]_i_1__1_n_0\, + Q => pState(2), + R => SS(0) + ); +\pState_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[3]_i_1__1_n_0\, + Q => pState(3), + R => SS(0) + ); +\pState_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[4]_i_1__1_n_0\, + Q => pState(4), + R => SS(0) + ); +\pState_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[5]_i_1__1_n_0\, + Q => pState(5), + R => SS(0) + ); +\pState_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[6]_i_1__1_n_0\, + Q => pState(6), + R => SS(0) + ); +\pState_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[7]_i_1__1_n_0\, + Q => pState(7), + R => SS(0) + ); +\pState_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[8]_i_1__1_n_0\, + Q => pState(8), + R => SS(0) + ); +\pState_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => \pStateNxt__4\, + D => \pState[9]_i_1__1_n_0\, + Q => pState(9), + R => SS(0) + ); +pTknFlagQ_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pTknFlag, + Q => pTknFlagQ, + R => '0' + ); +\pTknFlag_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30000808" + ) + port map ( + I0 => \pTknFlag_i_2__1_n_0\, + I1 => \pDataQ_reg_n_0_[8]\, + I2 => \pDataQ_reg_n_0_[0]\, + I3 => \pTknFlag_i_3__1_n_0\, + I4 => \pDataQ_reg_n_0_[3]\, + O => pTknFlag0 + ); +\pTknFlag_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0002000000000000" + ) + port map ( + I0 => \pDataQ_reg_n_0_[4]\, + I1 => \pDataQ_reg_n_0_[5]\, + I2 => \pDataQ_reg_n_0_[7]\, + I3 => \pDataQ_reg_n_0_[1]\, + I4 => \pDataQ_reg_n_0_[2]\, + I5 => \pDataQ_reg_n_0_[6]\, + O => \pTknFlag_i_2__1_n_0\ + ); +\pTknFlag_i_3__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000004000" + ) + port map ( + I0 => \pDataQ_reg_n_0_[4]\, + I1 => \pDataQ_reg_n_0_[5]\, + I2 => \pDataQ_reg_n_0_[7]\, + I3 => \pDataQ_reg_n_0_[1]\, + I4 => \pDataQ_reg_n_0_[2]\, + I5 => \pDataQ_reg_n_0_[6]\, + O => \pTknFlag_i_3__1_n_0\ + ); +pTknFlag_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pTknFlag0, + Q => pTknFlag, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_ResyncToBUFG is + port ( + CLK : out STD_LOGIC; + vid_pVDE : out STD_LOGIC; + vid_pHSync : out STD_LOGIC; + vid_pVSync : out STD_LOGIC; + vid_pData : out STD_LOGIC_VECTOR ( 23 downto 0 ); + PixelClk_int : in STD_LOGIC; + pVde : in STD_LOGIC; + pC0 : in STD_LOGIC; + pC1 : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 23 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_ResyncToBUFG : entity is "ResyncToBUFG"; +end Arty_Z7_20_dvi2rgb_0_0_ResyncToBUFG; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_ResyncToBUFG is + signal \^clk\ : STD_LOGIC; + attribute box_type : string; + attribute box_type of InstBUFG : label is "PRIMITIVE"; +begin + CLK <= \^clk\; +InstBUFG: unisim.vcomponents.BUFG + port map ( + I => PixelClk_int, + O => \^clk\ + ); +\poData_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => \^clk\, + CE => '1', + D => D(0), + Q => vid_pData(0), + R => '0' + ); +\poData_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => \^clk\, + CE => '1', + D => D(10), + Q => vid_pData(10), + R => '0' + ); +\poData_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => \^clk\, + CE => '1', + D => D(11), + Q => vid_pData(11), + R => '0' + ); +\poData_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => \^clk\, + CE => '1', + D => D(12), + Q => vid_pData(12), + R => '0' + ); +\poData_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => \^clk\, + CE => '1', + D => D(13), + Q => vid_pData(13), + R => '0' + ); +\poData_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => \^clk\, + CE => '1', + D => D(14), + Q => vid_pData(14), + R => '0' + ); +\poData_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => \^clk\, + CE => '1', + D => D(15), + Q => vid_pData(15), + R => '0' + ); +\poData_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => \^clk\, + CE => '1', + D => D(16), + Q => vid_pData(16), + R => '0' + ); +\poData_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => \^clk\, + CE => '1', + D => D(17), + Q => vid_pData(17), + R => '0' + ); +\poData_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => \^clk\, + CE => '1', + D => D(18), + Q => vid_pData(18), + R => '0' + ); +\poData_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => \^clk\, + CE => '1', + D => D(19), + Q => vid_pData(19), + R => '0' + ); +\poData_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => \^clk\, + CE => '1', + D => D(1), + Q => vid_pData(1), + R => '0' + ); +\poData_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => \^clk\, + CE => '1', + D => D(20), + Q => vid_pData(20), + R => '0' + ); +\poData_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => \^clk\, + CE => '1', + D => D(21), + Q => vid_pData(21), + R => '0' + ); +\poData_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => \^clk\, + CE => '1', + D => D(22), + Q => vid_pData(22), + R => '0' + ); +\poData_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => \^clk\, + CE => '1', + D => D(23), + Q => vid_pData(23), + R => '0' + ); +\poData_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => \^clk\, + CE => '1', + D => D(2), + Q => vid_pData(2), + R => '0' + ); +\poData_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => \^clk\, + CE => '1', + D => D(3), + Q => vid_pData(3), + R => '0' + ); +\poData_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => \^clk\, + CE => '1', + D => D(4), + Q => vid_pData(4), + R => '0' + ); +\poData_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => \^clk\, + CE => '1', + D => D(5), + Q => vid_pData(5), + R => '0' + ); +\poData_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => \^clk\, + CE => '1', + D => D(6), + Q => vid_pData(6), + R => '0' + ); +\poData_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => \^clk\, + CE => '1', + D => D(7), + Q => vid_pData(7), + R => '0' + ); +\poData_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => \^clk\, + CE => '1', + D => D(8), + Q => vid_pData(8), + R => '0' + ); +\poData_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => \^clk\, + CE => '1', + D => D(9), + Q => vid_pData(9), + R => '0' + ); +poHSync_reg: unisim.vcomponents.FDRE + port map ( + C => \^clk\, + CE => '1', + D => pC0, + Q => vid_pHSync, + R => '0' + ); +poVDE_reg: unisim.vcomponents.FDRE + port map ( + C => \^clk\, + CE => '1', + D => pVde, + Q => vid_pVDE, + R => '0' + ); +poVSync_reg: unisim.vcomponents.FDRE + port map ( + C => \^clk\, + CE => '1', + D => pC1, + Q => vid_pVSync, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_SyncAsync is + port ( + \out\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + RefClk : in STD_LOGIC; + AS : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_SyncAsync : entity is "SyncAsync"; +end Arty_Z7_20_dvi2rgb_0_0_SyncAsync; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_SyncAsync is + signal oSyncStages : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute async_reg : string; + attribute async_reg of oSyncStages : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \oSyncStages_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \oSyncStages_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \oSyncStages_reg[1]\ : label is std.standard.true; + attribute KEEP of \oSyncStages_reg[1]\ : label is "yes"; +begin + \out\(0) <= oSyncStages(1); +\oSyncStages_reg[0]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => RefClk, + CE => '1', + D => '0', + PRE => AS(0), + Q => oSyncStages(0) + ); +\oSyncStages_reg[1]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => RefClk, + CE => '1', + D => oSyncStages(0), + PRE => AS(0), + Q => oSyncStages(1) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_SyncAsync_15 is + port ( + \out\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + RefClk : in STD_LOGIC; + AS : in STD_LOGIC_VECTOR ( 0 to 0 ); + D : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_SyncAsync_15 : entity is "SyncAsync"; +end Arty_Z7_20_dvi2rgb_0_0_SyncAsync_15; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_SyncAsync_15 is + signal oSyncStages : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute async_reg : string; + attribute async_reg of oSyncStages : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \oSyncStages_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \oSyncStages_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \oSyncStages_reg[1]\ : label is std.standard.true; + attribute KEEP of \oSyncStages_reg[1]\ : label is "yes"; +begin + \out\(0) <= oSyncStages(1); +\oSyncStages_reg[0]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => RefClk, + CE => '1', + D => D(0), + PRE => AS(0), + Q => oSyncStages(0) + ); +\oSyncStages_reg[1]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => RefClk, + CE => '1', + D => oSyncStages(0), + PRE => AS(0), + Q => oSyncStages(1) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_SyncAsync_22 is + port ( + \out\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + RefClk : in STD_LOGIC; + AS : in STD_LOGIC_VECTOR ( 0 to 0 ); + D : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_SyncAsync_22 : entity is "SyncAsync"; +end Arty_Z7_20_dvi2rgb_0_0_SyncAsync_22; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_SyncAsync_22 is + signal oSyncStages : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute async_reg : string; + attribute async_reg of oSyncStages : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \oSyncStages_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \oSyncStages_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \oSyncStages_reg[1]\ : label is std.standard.true; + attribute KEEP of \oSyncStages_reg[1]\ : label is "yes"; +begin + \out\(0) <= oSyncStages(1); +\oSyncStages_reg[0]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => RefClk, + CE => '1', + D => D(0), + PRE => AS(0), + Q => oSyncStages(0) + ); +\oSyncStages_reg[1]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => RefClk, + CE => '1', + D => oSyncStages(0), + PRE => AS(0), + Q => oSyncStages(1) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_SyncAsync_4 is + port ( + SS : out STD_LOGIC_VECTOR ( 0 to 0 ); + rDlyRst_reg : out STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + RST : in STD_LOGIC; + RefClk : in STD_LOGIC; + AS : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_SyncAsync_4 : entity is "SyncAsync"; +end Arty_Z7_20_dvi2rgb_0_0_SyncAsync_4; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_SyncAsync_4 is + signal oSyncStages : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute async_reg : string; + attribute async_reg of oSyncStages : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \oSyncStages_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \oSyncStages_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \oSyncStages_reg[1]\ : label is std.standard.true; + attribute KEEP of \oSyncStages_reg[1]\ : label is "yes"; +begin + SS(0) <= oSyncStages(1); +\oSyncStages_reg[0]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => RefClk, + CE => '1', + D => '0', + PRE => AS(0), + Q => oSyncStages(0) + ); +\oSyncStages_reg[1]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => RefClk, + CE => '1', + D => oSyncStages(0), + PRE => AS(0), + Q => oSyncStages(1) + ); +rDlyRst_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"F8" + ) + port map ( + I0 => E(0), + I1 => RST, + I2 => oSyncStages(1), + O => rDlyRst_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_SyncAsync_5 is + port ( + \out\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + PixelClk_int : in STD_LOGIC; + AS : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_SyncAsync_5 : entity is "SyncAsync"; +end Arty_Z7_20_dvi2rgb_0_0_SyncAsync_5; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_SyncAsync_5 is + signal oSyncStages : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute async_reg : string; + attribute async_reg of oSyncStages : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \oSyncStages_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \oSyncStages_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \oSyncStages_reg[1]\ : label is std.standard.true; + attribute KEEP of \oSyncStages_reg[1]\ : label is "yes"; +begin + \out\(0) <= oSyncStages(1); +\oSyncStages_reg[0]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => PixelClk_int, + CE => '1', + D => '0', + PRE => AS(0), + Q => oSyncStages(0) + ); +\oSyncStages_reg[1]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => PixelClk_int, + CE => '1', + D => oSyncStages(0), + PRE => AS(0), + Q => oSyncStages(1) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_SyncAsync_7 is + port ( + \out\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + SS : out STD_LOGIC_VECTOR ( 0 to 0 ); + \Filter.sIn_q_reg\ : in STD_LOGIC; + RefClk : in STD_LOGIC; + DDC_SCL_I : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_SyncAsync_7 : entity is "SyncAsync"; +end Arty_Z7_20_dvi2rgb_0_0_SyncAsync_7; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_SyncAsync_7 is + signal oSyncStages : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute async_reg : string; + attribute async_reg of oSyncStages : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \oSyncStages_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \oSyncStages_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \oSyncStages_reg[1]\ : label is std.standard.true; + attribute KEEP of \oSyncStages_reg[1]\ : label is "yes"; +begin + \out\(0) <= oSyncStages(1); +\Filter.cntPeriods[3]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => oSyncStages(1), + I1 => \Filter.sIn_q_reg\, + O => SS(0) + ); +\oSyncStages_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => RefClk, + CE => '1', + D => DDC_SCL_I, + Q => oSyncStages(0), + R => '0' + ); +\oSyncStages_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => RefClk, + CE => '1', + D => oSyncStages(0), + Q => oSyncStages(1), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_SyncAsync_8 is + port ( + \out\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + SS : out STD_LOGIC_VECTOR ( 0 to 0 ); + sIn_q : in STD_LOGIC; + RefClk : in STD_LOGIC; + DDC_SDA_I : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_SyncAsync_8 : entity is "SyncAsync"; +end Arty_Z7_20_dvi2rgb_0_0_SyncAsync_8; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_SyncAsync_8 is + signal oSyncStages : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute async_reg : string; + attribute async_reg of oSyncStages : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \oSyncStages_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \oSyncStages_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \oSyncStages_reg[1]\ : label is std.standard.true; + attribute KEEP of \oSyncStages_reg[1]\ : label is "yes"; +begin + \out\(0) <= oSyncStages(1); +\Filter.cntPeriods[3]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => oSyncStages(1), + I1 => sIn_q, + O => SS(0) + ); +\oSyncStages_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => RefClk, + CE => '1', + D => DDC_SDA_I, + Q => oSyncStages(0), + R => '0' + ); +\oSyncStages_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => RefClk, + CE => '1', + D => oSyncStages(0), + Q => oSyncStages(1), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_SyncAsync_9 is + port ( + \out\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + RefClk : in STD_LOGIC; + \oSyncStages_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + D : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_SyncAsync_9 : entity is "SyncAsync"; +end Arty_Z7_20_dvi2rgb_0_0_SyncAsync_9; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_SyncAsync_9 is + signal oSyncStages : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute async_reg : string; + attribute async_reg of oSyncStages : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \oSyncStages_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \oSyncStages_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \oSyncStages_reg[1]\ : label is std.standard.true; + attribute KEEP of \oSyncStages_reg[1]\ : label is "yes"; +begin + \out\(0) <= oSyncStages(1); +\oSyncStages_reg[0]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => RefClk, + CE => '1', + D => D(0), + PRE => \oSyncStages_reg[1]_0\(0), + Q => oSyncStages(0) + ); +\oSyncStages_reg[1]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => RefClk, + CE => '1', + D => oSyncStages(0), + PRE => \oSyncStages_reg[1]_0\(0), + Q => oSyncStages(1) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_dvi2rgb_0_0_SyncAsync__parameterized0\ is + port ( + D : out STD_LOGIC_VECTOR ( 0 to 0 ); + rMMCM_LckdRisingFlag_reg : out STD_LOGIC; + rMMCM_LckdFallingFlag_reg : out STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + RefClk : in STD_LOGIC; + \rMMCM_Reset_q_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_dvi2rgb_0_0_SyncAsync__parameterized0\ : entity is "SyncAsync"; +end \Arty_Z7_20_dvi2rgb_0_0_SyncAsync__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_dvi2rgb_0_0_SyncAsync__parameterized0\ is + signal oSyncStages : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute async_reg : string; + attribute async_reg of oSyncStages : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \oSyncStages_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \oSyncStages_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \oSyncStages_reg[1]\ : label is std.standard.true; + attribute KEEP of \oSyncStages_reg[1]\ : label is "yes"; +begin + D(0) <= oSyncStages(1); +\oSyncStages_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => RefClk, + CE => '1', + D => \rMMCM_Reset_q_reg[0]\(0), + Q => oSyncStages(0), + R => '0' + ); +\oSyncStages_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => RefClk, + CE => '1', + D => oSyncStages(0), + Q => oSyncStages(1), + R => '0' + ); +rMMCM_LckdFallingFlag_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => Q(0), + I1 => oSyncStages(1), + O => rMMCM_LckdFallingFlag_reg + ); +rMMCM_LckdRisingFlag_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => oSyncStages(1), + I1 => Q(0), + O => rMMCM_LckdRisingFlag_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_dvi2rgb_0_0_SyncAsync__parameterized1\ is + port ( + \out\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + PixelClk_int : in STD_LOGIC; + \oSyncStages_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + D : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_dvi2rgb_0_0_SyncAsync__parameterized1\ : entity is "SyncAsync"; +end \Arty_Z7_20_dvi2rgb_0_0_SyncAsync__parameterized1\; + +architecture STRUCTURE of \Arty_Z7_20_dvi2rgb_0_0_SyncAsync__parameterized1\ is + signal oSyncStages : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute async_reg : string; + attribute async_reg of oSyncStages : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \oSyncStages_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \oSyncStages_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \oSyncStages_reg[1]\ : label is std.standard.true; + attribute KEEP of \oSyncStages_reg[1]\ : label is "yes"; +begin + \out\(0) <= oSyncStages(1); +\oSyncStages_reg[0]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => PixelClk_int, + CE => '1', + CLR => \oSyncStages_reg[1]_0\(0), + D => D(0), + Q => oSyncStages(0) + ); +\oSyncStages_reg[1]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => PixelClk_int, + CE => '1', + CLR => \oSyncStages_reg[1]_0\(0), + D => oSyncStages(0), + Q => oSyncStages(1) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_dvi2rgb_0_0_SyncAsync__parameterized1_16\ is + port ( + \out\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + PixelClk_int : in STD_LOGIC; + AS : in STD_LOGIC_VECTOR ( 0 to 0 ); + D : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_dvi2rgb_0_0_SyncAsync__parameterized1_16\ : entity is "SyncAsync"; +end \Arty_Z7_20_dvi2rgb_0_0_SyncAsync__parameterized1_16\; + +architecture STRUCTURE of \Arty_Z7_20_dvi2rgb_0_0_SyncAsync__parameterized1_16\ is + signal oSyncStages : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute async_reg : string; + attribute async_reg of oSyncStages : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \oSyncStages_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \oSyncStages_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \oSyncStages_reg[1]\ : label is std.standard.true; + attribute KEEP of \oSyncStages_reg[1]\ : label is "yes"; +begin + \out\(0) <= oSyncStages(1); +\oSyncStages_reg[0]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => PixelClk_int, + CE => '1', + CLR => AS(0), + D => D(0), + Q => oSyncStages(0) + ); +\oSyncStages_reg[1]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => PixelClk_int, + CE => '1', + CLR => AS(0), + D => oSyncStages(0), + Q => oSyncStages(1) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_dvi2rgb_0_0_SyncAsync__parameterized1_23\ is + port ( + \out\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + PixelClk_int : in STD_LOGIC; + AS : in STD_LOGIC_VECTOR ( 0 to 0 ); + D : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_dvi2rgb_0_0_SyncAsync__parameterized1_23\ : entity is "SyncAsync"; +end \Arty_Z7_20_dvi2rgb_0_0_SyncAsync__parameterized1_23\; + +architecture STRUCTURE of \Arty_Z7_20_dvi2rgb_0_0_SyncAsync__parameterized1_23\ is + signal oSyncStages : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute async_reg : string; + attribute async_reg of oSyncStages : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \oSyncStages_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \oSyncStages_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \oSyncStages_reg[1]\ : label is std.standard.true; + attribute KEEP of \oSyncStages_reg[1]\ : label is "yes"; +begin + \out\(0) <= oSyncStages(1); +\oSyncStages_reg[0]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => PixelClk_int, + CE => '1', + CLR => AS(0), + D => D(0), + Q => oSyncStages(0) + ); +\oSyncStages_reg[1]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => PixelClk_int, + CE => '1', + CLR => AS(0), + D => oSyncStages(0), + Q => oSyncStages(1) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_ResetBridge is + port ( + \out\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + in0 : in STD_LOGIC; + PixelClk_int : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_ResetBridge : entity is "ResetBridge"; +end Arty_Z7_20_dvi2rgb_0_0_ResetBridge; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_ResetBridge is + signal aRst_int : STD_LOGIC; + attribute RTL_KEEP : string; + attribute RTL_KEEP of aRst_int : signal is "true"; +begin + aRst_int <= in0; +SyncAsyncx: entity work.Arty_Z7_20_dvi2rgb_0_0_SyncAsync_5 + port map ( + AS(0) => aRst_int, + PixelClk_int => PixelClk_int, + \out\(0) => \out\(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_ResetBridge_2 is + port ( + SS : out STD_LOGIC_VECTOR ( 0 to 0 ); + rDlyRst_reg : out STD_LOGIC; + aRst_n : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + RST : in STD_LOGIC; + RefClk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_ResetBridge_2 : entity is "ResetBridge"; +end Arty_Z7_20_dvi2rgb_0_0_ResetBridge_2; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_ResetBridge_2 is + signal aRst_int_0 : STD_LOGIC; + attribute RTL_KEEP : string; + attribute RTL_KEEP of aRst_int_0 : signal is "true"; +begin +SyncAsyncx: entity work.Arty_Z7_20_dvi2rgb_0_0_SyncAsync_4 + port map ( + AS(0) => aRst_int_0, + E(0) => E(0), + RST => RST, + RefClk => RefClk, + SS(0) => SS(0), + rDlyRst_reg => rDlyRst_reg + ); +\aRst_int_inferred_i_1__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => aRst_n, + O => aRst_int_0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_ResetBridge_3 is + port ( + \out\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + aDlyLckd : in STD_LOGIC; + RefClk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_ResetBridge_3 : entity is "ResetBridge"; +end Arty_Z7_20_dvi2rgb_0_0_ResetBridge_3; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_ResetBridge_3 is + signal aRst_int : STD_LOGIC; + attribute RTL_KEEP : string; + attribute RTL_KEEP of aRst_int : signal is "true"; +begin +SyncAsyncx: entity work.Arty_Z7_20_dvi2rgb_0_0_SyncAsync + port map ( + AS(0) => aRst_int, + RefClk => RefClk, + \out\(0) => \out\(0) + ); +aRst_int_inferred_i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => aDlyLckd, + O => aRst_int + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_SyncBase is + port ( + \out\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + iIn_q_reg_0 : out STD_LOGIC; + iIn_q_reg_1 : out STD_LOGIC; + iIn_q_reg_2 : out STD_LOGIC; + iIn_q_reg_3 : out STD_LOGIC; + RefClk : in STD_LOGIC; + \oSyncStages_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + rTimeoutCnt_reg : in STD_LOGIC_VECTOR ( 23 downto 0 ); + PixelClk_int : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_SyncBase : entity is "SyncBase"; +end Arty_Z7_20_dvi2rgb_0_0_SyncBase; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_SyncBase is + signal iIn_q : STD_LOGIC; + signal \^iin_q_reg_0\ : STD_LOGIC; + signal \^iin_q_reg_1\ : STD_LOGIC; + signal \^iin_q_reg_2\ : STD_LOGIC; + signal \^iin_q_reg_3\ : STD_LOGIC; + signal p_0_out : STD_LOGIC; +begin + iIn_q_reg_0 <= \^iin_q_reg_0\; + iIn_q_reg_1 <= \^iin_q_reg_1\; + iIn_q_reg_2 <= \^iin_q_reg_2\; + iIn_q_reg_3 <= \^iin_q_reg_3\; +SyncAsyncx: entity work.\Arty_Z7_20_dvi2rgb_0_0_SyncAsync__parameterized1\ + port map ( + D(0) => iIn_q, + PixelClk_int => PixelClk_int, + \oSyncStages_reg[1]_0\(0) => \oSyncStages_reg[1]\(0), + \out\(0) => \out\(0) + ); +\iIn_q_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4000" + ) + port map ( + I0 => \^iin_q_reg_0\, + I1 => \^iin_q_reg_1\, + I2 => \^iin_q_reg_2\, + I3 => \^iin_q_reg_3\, + O => p_0_out + ); +\iIn_q_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFBF" + ) + port map ( + I0 => rTimeoutCnt_reg(7), + I1 => rTimeoutCnt_reg(20), + I2 => rTimeoutCnt_reg(23), + I3 => rTimeoutCnt_reg(13), + I4 => rTimeoutCnt_reg(8), + I5 => rTimeoutCnt_reg(11), + O => \^iin_q_reg_0\ + ); +\iIn_q_i_3__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000001" + ) + port map ( + I0 => rTimeoutCnt_reg(22), + I1 => rTimeoutCnt_reg(18), + I2 => rTimeoutCnt_reg(21), + I3 => rTimeoutCnt_reg(14), + I4 => rTimeoutCnt_reg(16), + I5 => rTimeoutCnt_reg(17), + O => \^iin_q_reg_1\ + ); +\iIn_q_i_4__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => rTimeoutCnt_reg(12), + I1 => rTimeoutCnt_reg(15), + I2 => rTimeoutCnt_reg(19), + I3 => rTimeoutCnt_reg(10), + I4 => rTimeoutCnt_reg(6), + I5 => rTimeoutCnt_reg(9), + O => \^iin_q_reg_2\ + ); +\iIn_q_i_5__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => rTimeoutCnt_reg(3), + I1 => rTimeoutCnt_reg(4), + I2 => rTimeoutCnt_reg(5), + I3 => rTimeoutCnt_reg(2), + I4 => rTimeoutCnt_reg(0), + I5 => rTimeoutCnt_reg(1), + O => \^iin_q_reg_3\ + ); +iIn_q_reg: unisim.vcomponents.FDCE + port map ( + C => RefClk, + CE => '1', + CLR => \oSyncStages_reg[1]\(0), + D => p_0_out, + Q => iIn_q + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_SyncBase_13 is + port ( + \out\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + iIn_q_reg_0 : out STD_LOGIC; + iIn_q_reg_1 : out STD_LOGIC; + iIn_q_reg_2 : out STD_LOGIC; + iIn_q_reg_3 : out STD_LOGIC; + RefClk : in STD_LOGIC; + AS : in STD_LOGIC_VECTOR ( 0 to 0 ); + rTimeoutCnt_reg : in STD_LOGIC_VECTOR ( 23 downto 0 ); + PixelClk_int : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_SyncBase_13 : entity is "SyncBase"; +end Arty_Z7_20_dvi2rgb_0_0_SyncBase_13; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_SyncBase_13 is + signal \iIn_q_i_1__3_n_0\ : STD_LOGIC; + signal \^iin_q_reg_0\ : STD_LOGIC; + signal \^iin_q_reg_1\ : STD_LOGIC; + signal \^iin_q_reg_2\ : STD_LOGIC; + signal \^iin_q_reg_3\ : STD_LOGIC; + signal iIn_q_reg_n_0 : STD_LOGIC; +begin + iIn_q_reg_0 <= \^iin_q_reg_0\; + iIn_q_reg_1 <= \^iin_q_reg_1\; + iIn_q_reg_2 <= \^iin_q_reg_2\; + iIn_q_reg_3 <= \^iin_q_reg_3\; +SyncAsyncx: entity work.\Arty_Z7_20_dvi2rgb_0_0_SyncAsync__parameterized1_16\ + port map ( + AS(0) => AS(0), + D(0) => iIn_q_reg_n_0, + PixelClk_int => PixelClk_int, + \out\(0) => \out\(0) + ); +\iIn_q_i_1__3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4000" + ) + port map ( + I0 => \^iin_q_reg_0\, + I1 => \^iin_q_reg_1\, + I2 => \^iin_q_reg_2\, + I3 => \^iin_q_reg_3\, + O => \iIn_q_i_1__3_n_0\ + ); +\iIn_q_i_2__3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFBF" + ) + port map ( + I0 => rTimeoutCnt_reg(7), + I1 => rTimeoutCnt_reg(20), + I2 => rTimeoutCnt_reg(23), + I3 => rTimeoutCnt_reg(13), + I4 => rTimeoutCnt_reg(8), + I5 => rTimeoutCnt_reg(11), + O => \^iin_q_reg_0\ + ); +\iIn_q_i_3__3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000001" + ) + port map ( + I0 => rTimeoutCnt_reg(22), + I1 => rTimeoutCnt_reg(18), + I2 => rTimeoutCnt_reg(21), + I3 => rTimeoutCnt_reg(14), + I4 => rTimeoutCnt_reg(16), + I5 => rTimeoutCnt_reg(17), + O => \^iin_q_reg_1\ + ); +\iIn_q_i_4__3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => rTimeoutCnt_reg(12), + I1 => rTimeoutCnt_reg(15), + I2 => rTimeoutCnt_reg(19), + I3 => rTimeoutCnt_reg(10), + I4 => rTimeoutCnt_reg(6), + I5 => rTimeoutCnt_reg(9), + O => \^iin_q_reg_2\ + ); +\iIn_q_i_5__3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => rTimeoutCnt_reg(3), + I1 => rTimeoutCnt_reg(4), + I2 => rTimeoutCnt_reg(5), + I3 => rTimeoutCnt_reg(2), + I4 => rTimeoutCnt_reg(0), + I5 => rTimeoutCnt_reg(1), + O => \^iin_q_reg_3\ + ); +iIn_q_reg: unisim.vcomponents.FDCE + port map ( + C => RefClk, + CE => '1', + CLR => AS(0), + D => \iIn_q_i_1__3_n_0\, + Q => iIn_q_reg_n_0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_SyncBase_20 is + port ( + \out\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + iIn_q_reg_0 : out STD_LOGIC; + iIn_q_reg_1 : out STD_LOGIC; + iIn_q_reg_2 : out STD_LOGIC; + iIn_q_reg_3 : out STD_LOGIC; + RefClk : in STD_LOGIC; + AS : in STD_LOGIC_VECTOR ( 0 to 0 ); + rTimeoutCnt_reg : in STD_LOGIC_VECTOR ( 23 downto 0 ); + PixelClk_int : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_SyncBase_20 : entity is "SyncBase"; +end Arty_Z7_20_dvi2rgb_0_0_SyncBase_20; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_SyncBase_20 is + signal \iIn_q_i_1__4_n_0\ : STD_LOGIC; + signal \^iin_q_reg_0\ : STD_LOGIC; + signal \^iin_q_reg_1\ : STD_LOGIC; + signal \^iin_q_reg_2\ : STD_LOGIC; + signal \^iin_q_reg_3\ : STD_LOGIC; + signal iIn_q_reg_n_0 : STD_LOGIC; +begin + iIn_q_reg_0 <= \^iin_q_reg_0\; + iIn_q_reg_1 <= \^iin_q_reg_1\; + iIn_q_reg_2 <= \^iin_q_reg_2\; + iIn_q_reg_3 <= \^iin_q_reg_3\; +SyncAsyncx: entity work.\Arty_Z7_20_dvi2rgb_0_0_SyncAsync__parameterized1_23\ + port map ( + AS(0) => AS(0), + D(0) => iIn_q_reg_n_0, + PixelClk_int => PixelClk_int, + \out\(0) => \out\(0) + ); +\iIn_q_i_1__4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4000" + ) + port map ( + I0 => \^iin_q_reg_0\, + I1 => \^iin_q_reg_1\, + I2 => \^iin_q_reg_2\, + I3 => \^iin_q_reg_3\, + O => \iIn_q_i_1__4_n_0\ + ); +\iIn_q_i_2__4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFBF" + ) + port map ( + I0 => rTimeoutCnt_reg(7), + I1 => rTimeoutCnt_reg(20), + I2 => rTimeoutCnt_reg(23), + I3 => rTimeoutCnt_reg(13), + I4 => rTimeoutCnt_reg(8), + I5 => rTimeoutCnt_reg(11), + O => \^iin_q_reg_0\ + ); +\iIn_q_i_3__4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000001" + ) + port map ( + I0 => rTimeoutCnt_reg(22), + I1 => rTimeoutCnt_reg(18), + I2 => rTimeoutCnt_reg(21), + I3 => rTimeoutCnt_reg(14), + I4 => rTimeoutCnt_reg(16), + I5 => rTimeoutCnt_reg(17), + O => \^iin_q_reg_1\ + ); +\iIn_q_i_4__4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => rTimeoutCnt_reg(12), + I1 => rTimeoutCnt_reg(15), + I2 => rTimeoutCnt_reg(19), + I3 => rTimeoutCnt_reg(10), + I4 => rTimeoutCnt_reg(6), + I5 => rTimeoutCnt_reg(9), + O => \^iin_q_reg_2\ + ); +\iIn_q_i_5__4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => rTimeoutCnt_reg(3), + I1 => rTimeoutCnt_reg(4), + I2 => rTimeoutCnt_reg(5), + I3 => rTimeoutCnt_reg(2), + I4 => rTimeoutCnt_reg(0), + I5 => rTimeoutCnt_reg(1), + O => \^iin_q_reg_3\ + ); +iIn_q_reg: unisim.vcomponents.FDCE + port map ( + C => RefClk, + CE => '1', + CLR => AS(0), + D => \iIn_q_i_1__4_n_0\, + Q => iIn_q_reg_n_0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_dvi2rgb_0_0_SyncBase__parameterized0\ is + port ( + \out\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \pState_reg[1]\ : in STD_LOGIC; + PixelClk_int : in STD_LOGIC; + \oSyncStages_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + RefClk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_dvi2rgb_0_0_SyncBase__parameterized0\ : entity is "SyncBase"; +end \Arty_Z7_20_dvi2rgb_0_0_SyncBase__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_dvi2rgb_0_0_SyncBase__parameterized0\ is + signal iIn_q_reg_n_0 : STD_LOGIC; +begin +SyncAsyncx: entity work.Arty_Z7_20_dvi2rgb_0_0_SyncAsync_9 + port map ( + D(0) => iIn_q_reg_n_0, + RefClk => RefClk, + \oSyncStages_reg[1]_0\(0) => \oSyncStages_reg[1]\(0), + \out\(0) => \out\(0) + ); +iIn_q_reg: unisim.vcomponents.FDPE + port map ( + C => PixelClk_int, + CE => '1', + D => \pState_reg[1]\, + PRE => \oSyncStages_reg[1]\(0), + Q => iIn_q_reg_n_0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_dvi2rgb_0_0_SyncBase__parameterized0_14\ is + port ( + \out\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \pState_reg[1]\ : in STD_LOGIC; + PixelClk_int : in STD_LOGIC; + AS : in STD_LOGIC_VECTOR ( 0 to 0 ); + RefClk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_dvi2rgb_0_0_SyncBase__parameterized0_14\ : entity is "SyncBase"; +end \Arty_Z7_20_dvi2rgb_0_0_SyncBase__parameterized0_14\; + +architecture STRUCTURE of \Arty_Z7_20_dvi2rgb_0_0_SyncBase__parameterized0_14\ is + signal iIn_q_reg_n_0 : STD_LOGIC; +begin +SyncAsyncx: entity work.Arty_Z7_20_dvi2rgb_0_0_SyncAsync_15 + port map ( + AS(0) => AS(0), + D(0) => iIn_q_reg_n_0, + RefClk => RefClk, + \out\(0) => \out\(0) + ); +iIn_q_reg: unisim.vcomponents.FDPE + port map ( + C => PixelClk_int, + CE => '1', + D => \pState_reg[1]\, + PRE => AS(0), + Q => iIn_q_reg_n_0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_dvi2rgb_0_0_SyncBase__parameterized0_21\ is + port ( + \out\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \pState_reg[1]\ : in STD_LOGIC; + PixelClk_int : in STD_LOGIC; + AS : in STD_LOGIC_VECTOR ( 0 to 0 ); + RefClk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_dvi2rgb_0_0_SyncBase__parameterized0_21\ : entity is "SyncBase"; +end \Arty_Z7_20_dvi2rgb_0_0_SyncBase__parameterized0_21\; + +architecture STRUCTURE of \Arty_Z7_20_dvi2rgb_0_0_SyncBase__parameterized0_21\ is + signal iIn_q_reg_n_0 : STD_LOGIC; +begin +SyncAsyncx: entity work.Arty_Z7_20_dvi2rgb_0_0_SyncAsync_22 + port map ( + AS(0) => AS(0), + D(0) => iIn_q_reg_n_0, + RefClk => RefClk, + \out\(0) => \out\(0) + ); +iIn_q_reg: unisim.vcomponents.FDPE + port map ( + C => PixelClk_int, + CE => '1', + D => \pState_reg[1]\, + PRE => AS(0), + Q => iIn_q_reg_n_0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_TWI_SlaveCtl is + port ( + sI2C_End : out STD_LOGIC; + sI2C_Done : out STD_LOGIC; + rd_wrn_reg_0 : out STD_LOGIC; + DDC_SDA_T : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + D : out STD_LOGIC_VECTOR ( 6 downto 0 ); + RefClk : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 7 downto 0 ); + sState : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \sAddr_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); + \sState_reg[0]\ : in STD_LOGIC; + \sAddr_reg[3]\ : in STD_LOGIC; + \sAddr_reg[4]\ : in STD_LOGIC; + DDC_SDA_I : in STD_LOGIC; + DDC_SCL_I : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_TWI_SlaveCtl : entity is "TWI_SlaveCtl"; +end Arty_Z7_20_dvi2rgb_0_0_TWI_SlaveCtl; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_TWI_SlaveCtl is + signal DONE_O_i_2_n_0 : STD_LOGIC; + signal DONE_O_i_4_n_0 : STD_LOGIC; + signal END_O_i_2_n_0 : STD_LOGIC; + signal \FSM_gray_state[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_gray_state[0]_i_2_n_0\ : STD_LOGIC; + signal \FSM_gray_state[0]_i_3_n_0\ : STD_LOGIC; + signal \FSM_gray_state[0]_i_4_n_0\ : STD_LOGIC; + signal \FSM_gray_state[0]_i_5_n_0\ : STD_LOGIC; + signal \FSM_gray_state[1]_i_1_n_0\ : STD_LOGIC; + signal \FSM_gray_state[1]_i_2_n_0\ : STD_LOGIC; + signal \FSM_gray_state[1]_i_3_n_0\ : STD_LOGIC; + signal \FSM_gray_state[1]_i_4_n_0\ : STD_LOGIC; + signal \FSM_gray_state[1]_i_5_n_0\ : STD_LOGIC; + signal \FSM_gray_state[1]_i_7_n_0\ : STD_LOGIC; + signal \FSM_gray_state[1]_i_9_n_0\ : STD_LOGIC; + signal \FSM_gray_state[2]_i_1_n_0\ : STD_LOGIC; + signal \FSM_gray_state[2]_i_2_n_0\ : STD_LOGIC; + signal \FSM_gray_state[2]_i_3_n_0\ : STD_LOGIC; + signal \FSM_gray_state[2]_i_4_n_0\ : STD_LOGIC; + signal \FSM_gray_state[2]_i_5_n_0\ : STD_LOGIC; + signal \FSM_gray_state[2]_i_6_n_0\ : STD_LOGIC; + signal \FSM_gray_state[2]_i_7_n_0\ : STD_LOGIC; + signal GlitchF_SCL_n_0 : STD_LOGIC; + signal GlitchF_SCL_n_1 : STD_LOGIC; + signal SyncSCL_n_1 : STD_LOGIC; + signal SyncSDA_n_1 : STD_LOGIC; + signal \bitCount[0]_i_1_n_0\ : STD_LOGIC; + signal \bitCount[1]_i_1_n_0\ : STD_LOGIC; + signal \bitCount[2]_i_1_n_0\ : STD_LOGIC; + signal \bitCount[2]_i_2_n_0\ : STD_LOGIC; + signal \bitCount__1\ : STD_LOGIC; + signal \bitCount_reg_n_0_[0]\ : STD_LOGIC; + signal \bitCount_reg_n_0_[1]\ : STD_LOGIC; + signal \bitCount_reg_n_0_[2]\ : STD_LOGIC; + signal dScl : STD_LOGIC; + signal dSda : STD_LOGIC; + signal \dataByte[0]_i_1_n_0\ : STD_LOGIC; + signal \dataByte[0]_i_2_n_0\ : STD_LOGIC; + signal \dataByte[1]_i_1_n_0\ : STD_LOGIC; + signal \dataByte[2]_i_1_n_0\ : STD_LOGIC; + signal \dataByte[3]_i_1_n_0\ : STD_LOGIC; + signal \dataByte[4]_i_1_n_0\ : STD_LOGIC; + signal \dataByte[5]_i_1_n_0\ : STD_LOGIC; + signal \dataByte[6]_i_1_n_0\ : STD_LOGIC; + signal \dataByte[7]_i_1_n_0\ : STD_LOGIC; + signal \dataByte[7]_i_2_n_0\ : STD_LOGIC; + signal \dataByte[7]_i_4_n_0\ : STD_LOGIC; + signal \dataByte[7]_i_5_n_0\ : STD_LOGIC; + signal \dataByte[7]_i_6_n_0\ : STD_LOGIC; + signal \dataByte_reg_n_0_[0]\ : STD_LOGIC; + signal \dataByte_reg_n_0_[1]\ : STD_LOGIC; + signal \dataByte_reg_n_0_[2]\ : STD_LOGIC; + signal \dataByte_reg_n_0_[3]\ : STD_LOGIC; + signal \dataByte_reg_n_0_[4]\ : STD_LOGIC; + signal \dataByte_reg_n_0_[5]\ : STD_LOGIC; + signal \dataByte_reg_n_0_[6]\ : STD_LOGIC; + signal \dataByte_reg_n_0_[7]\ : STD_LOGIC; + signal ddScl : STD_LOGIC; + signal ddSda : STD_LOGIC; + signal fStart : STD_LOGIC; + signal fStop : STD_LOGIC; + signal iDone : STD_LOGIC; + signal iEnd : STD_LOGIC; + signal p_0_in_0 : STD_LOGIC; + signal p_15_in : STD_LOGIC; + signal p_2_in : STD_LOGIC; + signal rd_wrn0 : STD_LOGIC; + signal rd_wrn_i_1_n_0 : STD_LOGIC; + signal rd_wrn_i_2_n_0 : STD_LOGIC; + signal \^rd_wrn_reg_0\ : STD_LOGIC; + signal \^si2c_done\ : STD_LOGIC; + signal sI2C_Stb : STD_LOGIC; + signal sIn_q : STD_LOGIC; + signal sOut : STD_LOGIC; + signal sScl : STD_LOGIC; + signal sSda : STD_LOGIC; + signal state : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute RTL_KEEP : string; + attribute RTL_KEEP of state : signal is "yes"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of DONE_O_i_4 : label is "soft_lutpair89"; + attribute SOFT_HLUTNM of END_O_i_1 : label is "soft_lutpair87"; + attribute SOFT_HLUTNM of \FSM_gray_state[1]_i_10\ : label is "soft_lutpair90"; + attribute SOFT_HLUTNM of \FSM_gray_state[1]_i_5\ : label is "soft_lutpair89"; + attribute SOFT_HLUTNM of \FSM_gray_state[1]_i_6\ : label is "soft_lutpair85"; + attribute SOFT_HLUTNM of \FSM_gray_state[1]_i_9\ : label is "soft_lutpair86"; + attribute SOFT_HLUTNM of \FSM_gray_state[2]_i_7\ : label is "soft_lutpair90"; + attribute SOFT_HLUTNM of \FSM_gray_state[2]_i_8\ : label is "soft_lutpair91"; + attribute KEEP : string; + attribute KEEP of \FSM_gray_state_reg[0]\ : label is "yes"; + attribute KEEP of \FSM_gray_state_reg[1]\ : label is "yes"; + attribute KEEP of \FSM_gray_state_reg[2]\ : label is "yes"; + attribute SOFT_HLUTNM of \bitCount[2]_i_2\ : label is "soft_lutpair91"; + attribute SOFT_HLUTNM of \dataByte[7]_i_3\ : label is "soft_lutpair87"; + attribute SOFT_HLUTNM of rd_wrn_i_2 : label is "soft_lutpair86"; + attribute SOFT_HLUTNM of \sAddr_rep[0]_i_1\ : label is "soft_lutpair88"; + attribute SOFT_HLUTNM of \sAddr_rep[1]_i_1\ : label is "soft_lutpair85"; + attribute SOFT_HLUTNM of \sAddr_rep[6]_i_1\ : label is "soft_lutpair88"; +begin + rd_wrn_reg_0 <= \^rd_wrn_reg_0\; + sI2C_Done <= \^si2c_done\; +DDC_SDA_T_INST_0: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB7B" + ) + port map ( + I0 => state(0), + I1 => state(1), + I2 => state(2), + I3 => \dataByte_reg_n_0_[7]\, + O => DDC_SDA_T + ); +DONE_O_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAAAAAAAEA" + ) + port map ( + I0 => DONE_O_i_2_n_0, + I1 => rd_wrn0, + I2 => DONE_O_i_4_n_0, + I3 => \dataByte_reg_n_0_[0]\, + I4 => \dataByte_reg_n_0_[1]\, + I5 => \dataByte_reg_n_0_[2]\, + O => iDone + ); +DONE_O_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"2000000008000000" + ) + port map ( + I0 => \bitCount__1\, + I1 => dScl, + I2 => ddScl, + I3 => state(1), + I4 => state(2), + I5 => state(0), + O => DONE_O_i_2_n_0 + ); +DONE_O_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"0200" + ) + port map ( + I0 => rd_wrn_i_2_n_0, + I1 => state(1), + I2 => state(2), + I3 => state(0), + O => rd_wrn0 + ); +DONE_O_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"0400" + ) + port map ( + I0 => \dataByte_reg_n_0_[5]\, + I1 => \dataByte_reg_n_0_[6]\, + I2 => \dataByte_reg_n_0_[3]\, + I3 => \dataByte_reg_n_0_[4]\, + O => DONE_O_i_4_n_0 + ); +DONE_O_reg: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => '1', + D => iDone, + Q => \^si2c_done\, + R => '0' + ); +END_O_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"4F00F000" + ) + port map ( + I0 => ddScl, + I1 => END_O_i_2_n_0, + I2 => ddSda, + I3 => dScl, + I4 => dSda, + O => iEnd + ); +END_O_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => state(1), + I1 => state(2), + I2 => state(0), + O => END_O_i_2_n_0 + ); +END_O_reg: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => '1', + D => iEnd, + Q => sI2C_End, + R => '0' + ); +\FSM_gray_state[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2222222F22222220" + ) + port map ( + I0 => \FSM_gray_state[0]_i_2_n_0\, + I1 => \FSM_gray_state[0]_i_3_n_0\, + I2 => \FSM_gray_state[2]_i_3_n_0\, + I3 => \FSM_gray_state[1]_i_4_n_0\, + I4 => \FSM_gray_state[2]_i_6_n_0\, + I5 => state(0), + O => \FSM_gray_state[0]_i_1_n_0\ + ); +\FSM_gray_state[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FD01FDFFFFFFFDFF" + ) + port map ( + I0 => state(2), + I1 => state(0), + I2 => state(1), + I3 => ddSda, + I4 => dScl, + I5 => dSda, + O => \FSM_gray_state[0]_i_2_n_0\ + ); +\FSM_gray_state[0]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000FB00FF00FB" + ) + port map ( + I0 => \FSM_gray_state[1]_i_5_n_0\, + I1 => \FSM_gray_state[0]_i_4_n_0\, + I2 => state(2), + I3 => \FSM_gray_state[0]_i_5_n_0\, + I4 => state(1), + I5 => fStart, + O => \FSM_gray_state[0]_i_3_n_0\ + ); +\FSM_gray_state[0]_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"01" + ) + port map ( + I0 => \dataByte_reg_n_0_[1]\, + I1 => \dataByte_reg_n_0_[0]\, + I2 => \dataByte_reg_n_0_[2]\, + O => \FSM_gray_state[0]_i_4_n_0\ + ); +\FSM_gray_state[0]_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"5545" + ) + port map ( + I0 => state(0), + I1 => state(2), + I2 => state(1), + I3 => \^rd_wrn_reg_0\, + O => \FSM_gray_state[0]_i_5_n_0\ + ); +\FSM_gray_state[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2222222F22222220" + ) + port map ( + I0 => \FSM_gray_state[1]_i_2_n_0\, + I1 => \FSM_gray_state[1]_i_3_n_0\, + I2 => \FSM_gray_state[2]_i_3_n_0\, + I3 => \FSM_gray_state[1]_i_4_n_0\, + I4 => \FSM_gray_state[2]_i_6_n_0\, + I5 => state(1), + O => \FSM_gray_state[1]_i_1_n_0\ + ); +\FSM_gray_state[1]_i_10\: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => ddSda, + I1 => dScl, + I2 => dSda, + O => fStop + ); +\FSM_gray_state[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EEEEEEEEEEEEEEEF" + ) + port map ( + I0 => state(2), + I1 => state(1), + I2 => \dataByte_reg_n_0_[1]\, + I3 => \dataByte_reg_n_0_[0]\, + I4 => \dataByte_reg_n_0_[2]\, + I5 => \FSM_gray_state[1]_i_5_n_0\, + O => \FSM_gray_state[1]_i_2_n_0\ + ); +\FSM_gray_state[1]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFAFBFAFFFAF0FFF" + ) + port map ( + I0 => fStart, + I1 => sI2C_Stb, + I2 => \FSM_gray_state[1]_i_7_n_0\, + I3 => state(0), + I4 => state(2), + I5 => state(1), + O => \FSM_gray_state[1]_i_3_n_0\ + ); +\FSM_gray_state[1]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FAFAF8F8FAFAF888" + ) + port map ( + I0 => p_0_in_0, + I1 => rd_wrn_i_2_n_0, + I2 => p_2_in, + I3 => \FSM_gray_state[1]_i_9_n_0\, + I4 => fStop, + I5 => fStart, + O => \FSM_gray_state[1]_i_4_n_0\ + ); +\FSM_gray_state[1]_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFDF" + ) + port map ( + I0 => \dataByte_reg_n_0_[6]\, + I1 => \dataByte_reg_n_0_[5]\, + I2 => \dataByte_reg_n_0_[4]\, + I3 => \dataByte_reg_n_0_[3]\, + O => \FSM_gray_state[1]_i_5_n_0\ + ); +\FSM_gray_state[1]_i_6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => sState(1), + I1 => sState(0), + O => sI2C_Stb + ); +\FSM_gray_state[1]_i_7\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F7F7F747" + ) + port map ( + I0 => dSda, + I1 => dScl, + I2 => ddSda, + I3 => state(1), + I4 => state(0), + O => \FSM_gray_state[1]_i_7_n_0\ + ); +\FSM_gray_state[1]_i_8\: unisim.vcomponents.LUT3 + generic map( + INIT => X"02" + ) + port map ( + I0 => state(0), + I1 => state(2), + I2 => state(1), + O => p_0_in_0 + ); +\FSM_gray_state[1]_i_9\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00010000" + ) + port map ( + I0 => \bitCount_reg_n_0_[2]\, + I1 => \bitCount_reg_n_0_[1]\, + I2 => \bitCount_reg_n_0_[0]\, + I3 => dScl, + I4 => ddScl, + O => \FSM_gray_state[1]_i_9_n_0\ + ); +\FSM_gray_state[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAABAAAAAAA8" + ) + port map ( + I0 => \FSM_gray_state[2]_i_2_n_0\, + I1 => \FSM_gray_state[2]_i_3_n_0\, + I2 => \FSM_gray_state[2]_i_4_n_0\, + I3 => \FSM_gray_state[2]_i_5_n_0\, + I4 => \FSM_gray_state[2]_i_6_n_0\, + I5 => state(2), + O => \FSM_gray_state[2]_i_1_n_0\ + ); +\FSM_gray_state[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"B70000000007B700" + ) + port map ( + I0 => dSda, + I1 => dScl, + I2 => ddSda, + I3 => state(1), + I4 => state(2), + I5 => state(0), + O => \FSM_gray_state[2]_i_2_n_0\ + ); +\FSM_gray_state[2]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000F20000F2F200" + ) + port map ( + I0 => ddScl, + I1 => dScl, + I2 => \FSM_gray_state[2]_i_7_n_0\, + I3 => state(1), + I4 => state(2), + I5 => state(0), + O => \FSM_gray_state[2]_i_3_n_0\ + ); +\FSM_gray_state[2]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000FF4000000000" + ) + port map ( + I0 => ddSda, + I1 => dScl, + I2 => dSda, + I3 => rd_wrn_i_2_n_0, + I4 => \dataByte[7]_i_6_n_0\, + I5 => state(0), + O => \FSM_gray_state[2]_i_4_n_0\ + ); +\FSM_gray_state[2]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7B48484800000000" + ) + port map ( + I0 => dSda, + I1 => dScl, + I2 => ddSda, + I3 => \bitCount__1\, + I4 => ddScl, + I5 => p_2_in, + O => \FSM_gray_state[2]_i_5_n_0\ + ); +\FSM_gray_state[2]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00C200C200C20002" + ) + port map ( + I0 => fStart, + I1 => state(1), + I2 => state(2), + I3 => state(0), + I4 => rd_wrn_i_2_n_0, + I5 => \FSM_gray_state[2]_i_7_n_0\, + O => \FSM_gray_state[2]_i_6_n_0\ + ); +\FSM_gray_state[2]_i_7\: unisim.vcomponents.LUT3 + generic map( + INIT => X"48" + ) + port map ( + I0 => dSda, + I1 => dScl, + I2 => ddSda, + O => \FSM_gray_state[2]_i_7_n_0\ + ); +\FSM_gray_state[2]_i_8\: unisim.vcomponents.LUT3 + generic map( + INIT => X"01" + ) + port map ( + I0 => \bitCount_reg_n_0_[0]\, + I1 => \bitCount_reg_n_0_[1]\, + I2 => \bitCount_reg_n_0_[2]\, + O => \bitCount__1\ + ); +\FSM_gray_state[2]_i_9\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => state(0), + I1 => state(2), + I2 => state(1), + O => p_2_in + ); +\FSM_gray_state_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => '1', + D => \FSM_gray_state[0]_i_1_n_0\, + Q => state(0), + R => '0' + ); +\FSM_gray_state_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => '1', + D => \FSM_gray_state[1]_i_1_n_0\, + Q => state(1), + R => '0' + ); +\FSM_gray_state_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => '1', + D => \FSM_gray_state[2]_i_1_n_0\, + Q => state(2), + R => '0' + ); +GlitchF_SCL: entity work.Arty_Z7_20_dvi2rgb_0_0_GlitchFilter + port map ( + \Filter.sOut_reg_0\ => GlitchF_SCL_n_0, + RefClk => RefClk, + SS(0) => SyncSCL_n_1, + dScl_reg => GlitchF_SCL_n_1, + \out\(0) => sScl + ); +GlitchF_SDA: entity work.Arty_Z7_20_dvi2rgb_0_0_GlitchFilter_6 + port map ( + RefClk => RefClk, + SS(0) => SyncSDA_n_1, + \out\(0) => sSda, + sIn_q => sIn_q, + sOut => sOut + ); +SyncSCL: entity work.Arty_Z7_20_dvi2rgb_0_0_SyncAsync_7 + port map ( + DDC_SCL_I => DDC_SCL_I, + \Filter.sIn_q_reg\ => GlitchF_SCL_n_0, + RefClk => RefClk, + SS(0) => SyncSCL_n_1, + \out\(0) => sScl + ); +SyncSDA: entity work.Arty_Z7_20_dvi2rgb_0_0_SyncAsync_8 + port map ( + DDC_SDA_I => DDC_SDA_I, + RefClk => RefClk, + SS(0) => SyncSDA_n_1, + \out\(0) => sSda, + sIn_q => sIn_q + ); +\bitCount[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFF666F" + ) + port map ( + I0 => \bitCount_reg_n_0_[0]\, + I1 => \dataByte[7]_i_5_n_0\, + I2 => \dataByte[7]_i_6_n_0\, + I3 => state(0), + I4 => fStart, + I5 => \dataByte[7]_i_4_n_0\, + O => \bitCount[0]_i_1_n_0\ + ); +\bitCount[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFA6" + ) + port map ( + I0 => \bitCount_reg_n_0_[1]\, + I1 => \dataByte[7]_i_5_n_0\, + I2 => \bitCount_reg_n_0_[0]\, + I3 => \dataByte[0]_i_2_n_0\, + I4 => fStart, + I5 => \dataByte[7]_i_4_n_0\, + O => \bitCount[1]_i_1_n_0\ + ); +\bitCount[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFA6" + ) + port map ( + I0 => \bitCount_reg_n_0_[2]\, + I1 => \dataByte[7]_i_5_n_0\, + I2 => \bitCount[2]_i_2_n_0\, + I3 => \dataByte[0]_i_2_n_0\, + I4 => fStart, + I5 => \dataByte[7]_i_4_n_0\, + O => \bitCount[2]_i_1_n_0\ + ); +\bitCount[2]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \bitCount_reg_n_0_[1]\, + I1 => \bitCount_reg_n_0_[0]\, + O => \bitCount[2]_i_2_n_0\ + ); +\bitCount_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => RefClk, + CE => '1', + D => \bitCount[0]_i_1_n_0\, + Q => \bitCount_reg_n_0_[0]\, + R => '0' + ); +\bitCount_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => RefClk, + CE => '1', + D => \bitCount[1]_i_1_n_0\, + Q => \bitCount_reg_n_0_[1]\, + R => '0' + ); +\bitCount_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => RefClk, + CE => '1', + D => \bitCount[2]_i_1_n_0\, + Q => \bitCount_reg_n_0_[2]\, + R => '0' + ); +dScl_reg: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => '1', + D => GlitchF_SCL_n_1, + Q => dScl, + R => '0' + ); +dSda_reg: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => '1', + D => sOut, + Q => dSda, + R => '0' + ); +\dataByte[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAABBBBA888" + ) + port map ( + I0 => Q(0), + I1 => \dataByte[7]_i_4_n_0\, + I2 => dScl, + I3 => ddSda, + I4 => dSda, + I5 => \dataByte[0]_i_2_n_0\, + O => \dataByte[0]_i_1_n_0\ + ); +\dataByte[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"01" + ) + port map ( + I0 => state(0), + I1 => state(2), + I2 => state(1), + O => \dataByte[0]_i_2_n_0\ + ); +\dataByte[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"ABABABAAA8A8A8AA" + ) + port map ( + I0 => Q(1), + I1 => \dataByte[7]_i_4_n_0\, + I2 => fStart, + I3 => state(0), + I4 => \dataByte[7]_i_6_n_0\, + I5 => \dataByte_reg_n_0_[0]\, + O => \dataByte[1]_i_1_n_0\ + ); +\dataByte[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"ABABABAAA8A8A8AA" + ) + port map ( + I0 => Q(2), + I1 => \dataByte[7]_i_4_n_0\, + I2 => fStart, + I3 => state(0), + I4 => \dataByte[7]_i_6_n_0\, + I5 => \dataByte_reg_n_0_[1]\, + O => \dataByte[2]_i_1_n_0\ + ); +\dataByte[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"ABABABAAA8A8A8AA" + ) + port map ( + I0 => Q(3), + I1 => \dataByte[7]_i_4_n_0\, + I2 => fStart, + I3 => state(0), + I4 => \dataByte[7]_i_6_n_0\, + I5 => \dataByte_reg_n_0_[2]\, + O => \dataByte[3]_i_1_n_0\ + ); +\dataByte[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"ABABABAAA8A8A8AA" + ) + port map ( + I0 => Q(4), + I1 => \dataByte[7]_i_4_n_0\, + I2 => fStart, + I3 => state(0), + I4 => \dataByte[7]_i_6_n_0\, + I5 => \dataByte_reg_n_0_[3]\, + O => \dataByte[4]_i_1_n_0\ + ); +\dataByte[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"ABABABAAA8A8A8AA" + ) + port map ( + I0 => Q(5), + I1 => \dataByte[7]_i_4_n_0\, + I2 => fStart, + I3 => state(0), + I4 => \dataByte[7]_i_6_n_0\, + I5 => \dataByte_reg_n_0_[4]\, + O => \dataByte[5]_i_1_n_0\ + ); +\dataByte[6]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"ABABABAAA8A8A8AA" + ) + port map ( + I0 => Q(6), + I1 => \dataByte[7]_i_4_n_0\, + I2 => fStart, + I3 => state(0), + I4 => \dataByte[7]_i_6_n_0\, + I5 => \dataByte_reg_n_0_[5]\, + O => \dataByte[6]_i_1_n_0\ + ); +\dataByte[7]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFF01" + ) + port map ( + I0 => state(1), + I1 => state(2), + I2 => state(0), + I3 => fStart, + I4 => \dataByte[7]_i_4_n_0\, + I5 => \dataByte[7]_i_5_n_0\, + O => \dataByte[7]_i_1_n_0\ + ); +\dataByte[7]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"ABABABAAA8A8A8AA" + ) + port map ( + I0 => Q(7), + I1 => \dataByte[7]_i_4_n_0\, + I2 => fStart, + I3 => state(0), + I4 => \dataByte[7]_i_6_n_0\, + I5 => \dataByte_reg_n_0_[6]\, + O => \dataByte[7]_i_2_n_0\ + ); +\dataByte[7]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => dScl, + I1 => ddSda, + I2 => dSda, + O => fStart + ); +\dataByte[7]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000C04400" + ) + port map ( + I0 => ddSda, + I1 => p_15_in, + I2 => \^rd_wrn_reg_0\, + I3 => state(2), + I4 => state(1), + I5 => state(0), + O => \dataByte[7]_i_4_n_0\ + ); +\dataByte[7]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00804200" + ) + port map ( + I0 => state(0), + I1 => state(2), + I2 => state(1), + I3 => dScl, + I4 => ddScl, + O => \dataByte[7]_i_5_n_0\ + ); +\dataByte[7]_i_6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => state(1), + I1 => state(2), + O => \dataByte[7]_i_6_n_0\ + ); +\dataByte[7]_i_7\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => ddScl, + I1 => dScl, + O => p_15_in + ); +\dataByte_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \dataByte[7]_i_1_n_0\, + D => \dataByte[0]_i_1_n_0\, + Q => \dataByte_reg_n_0_[0]\, + R => '0' + ); +\dataByte_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \dataByte[7]_i_1_n_0\, + D => \dataByte[1]_i_1_n_0\, + Q => \dataByte_reg_n_0_[1]\, + R => '0' + ); +\dataByte_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \dataByte[7]_i_1_n_0\, + D => \dataByte[2]_i_1_n_0\, + Q => \dataByte_reg_n_0_[2]\, + R => '0' + ); +\dataByte_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \dataByte[7]_i_1_n_0\, + D => \dataByte[3]_i_1_n_0\, + Q => \dataByte_reg_n_0_[3]\, + R => '0' + ); +\dataByte_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \dataByte[7]_i_1_n_0\, + D => \dataByte[4]_i_1_n_0\, + Q => \dataByte_reg_n_0_[4]\, + R => '0' + ); +\dataByte_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \dataByte[7]_i_1_n_0\, + D => \dataByte[5]_i_1_n_0\, + Q => \dataByte_reg_n_0_[5]\, + R => '0' + ); +\dataByte_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \dataByte[7]_i_1_n_0\, + D => \dataByte[6]_i_1_n_0\, + Q => \dataByte_reg_n_0_[6]\, + R => '0' + ); +\dataByte_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \dataByte[7]_i_1_n_0\, + D => \dataByte[7]_i_2_n_0\, + Q => \dataByte_reg_n_0_[7]\, + R => '0' + ); +ddScl_reg: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => '1', + D => dScl, + Q => ddScl, + R => '0' + ); +ddSda_reg: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => '1', + D => dSda, + Q => ddSda, + R => '0' + ); +rd_wrn_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFBFFFF00080000" + ) + port map ( + I0 => dSda, + I1 => rd_wrn_i_2_n_0, + I2 => state(1), + I3 => state(2), + I4 => state(0), + I5 => \^rd_wrn_reg_0\, + O => rd_wrn_i_1_n_0 + ); +rd_wrn_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"00010000" + ) + port map ( + I0 => \bitCount_reg_n_0_[2]\, + I1 => \bitCount_reg_n_0_[1]\, + I2 => \bitCount_reg_n_0_[0]\, + I3 => ddScl, + I4 => dScl, + O => rd_wrn_i_2_n_0 + ); +rd_wrn_reg: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => '1', + D => rd_wrn_i_1_n_0, + Q => \^rd_wrn_reg_0\, + R => '0' + ); +\sAddr_rep[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"80BF" + ) + port map ( + I0 => \dataByte_reg_n_0_[0]\, + I1 => sState(0), + I2 => sState(1), + I3 => \sAddr_reg[6]\(0), + O => D(0) + ); +\sAddr_rep[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F6660666" + ) + port map ( + I0 => \sAddr_reg[6]\(1), + I1 => \sAddr_reg[6]\(0), + I2 => sState(0), + I3 => sState(1), + I4 => \dataByte_reg_n_0_[1]\, + O => D(1) + ); +\sAddr_rep[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF6A6A6A006A6A6A" + ) + port map ( + I0 => \sAddr_reg[6]\(2), + I1 => \sAddr_reg[6]\(1), + I2 => \sAddr_reg[6]\(0), + I3 => sState(0), + I4 => sState(1), + I5 => \dataByte_reg_n_0_[2]\, + O => D(2) + ); +\sAddr_rep[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF6AAA00006AAA" + ) + port map ( + I0 => \sAddr_reg[6]\(3), + I1 => \sAddr_reg[6]\(1), + I2 => \sAddr_reg[6]\(0), + I3 => \sAddr_reg[6]\(2), + I4 => \sState_reg[0]\, + I5 => \dataByte_reg_n_0_[3]\, + O => D(3) + ); +\sAddr_rep[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F6660666" + ) + port map ( + I0 => \sAddr_reg[6]\(4), + I1 => \sAddr_reg[3]\, + I2 => sState(0), + I3 => sState(1), + I4 => \dataByte_reg_n_0_[4]\, + O => D(4) + ); +\sAddr_rep[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F6660666" + ) + port map ( + I0 => \sAddr_reg[6]\(5), + I1 => \sAddr_reg[4]\, + I2 => sState(0), + I3 => sState(1), + I4 => \dataByte_reg_n_0_[5]\, + O => D(5) + ); +\sAddr_rep[6]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^si2c_done\, + I1 => sState(0), + O => E(0) + ); +\sAddr_rep[6]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF6A6A6A006A6A6A" + ) + port map ( + I0 => \sAddr_reg[6]\(6), + I1 => \sAddr_reg[4]\, + I2 => \sAddr_reg[6]\(5), + I3 => sState(0), + I4 => sState(1), + I5 => \dataByte_reg_n_0_[6]\, + O => D(6) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_EEPROM_8b is + port ( + DDC_SDA_T : out STD_LOGIC; + RefClk : in STD_LOGIC; + DDC_SDA_I : in STD_LOGIC; + DDC_SCL_I : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_EEPROM_8b : entity is "EEPROM_8b"; +end Arty_Z7_20_dvi2rgb_0_0_EEPROM_8b; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_EEPROM_8b is + signal I2C_SlaveController_n_10 : STD_LOGIC; + signal I2C_SlaveController_n_11 : STD_LOGIC; + signal I2C_SlaveController_n_2 : STD_LOGIC; + signal I2C_SlaveController_n_4 : STD_LOGIC; + signal I2C_SlaveController_n_5 : STD_LOGIC; + signal I2C_SlaveController_n_6 : STD_LOGIC; + signal I2C_SlaveController_n_7 : STD_LOGIC; + signal I2C_SlaveController_n_8 : STD_LOGIC; + signal I2C_SlaveController_n_9 : STD_LOGIC; + signal sAddr : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal sAddr_0 : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal \sAddr_rep[3]_i_2_n_0\ : STD_LOGIC; + signal \sAddr_rep[4]_i_2_n_0\ : STD_LOGIC; + signal \sAddr_rep[6]_i_3_n_0\ : STD_LOGIC; + signal sI2C_DataOut : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \sI2C_DataOut[0]_i_2_n_0\ : STD_LOGIC; + signal \sI2C_DataOut[0]_i_3_n_0\ : STD_LOGIC; + signal \sI2C_DataOut[1]_i_2_n_0\ : STD_LOGIC; + signal \sI2C_DataOut[1]_i_3_n_0\ : STD_LOGIC; + signal \sI2C_DataOut[2]_i_2_n_0\ : STD_LOGIC; + signal \sI2C_DataOut[2]_i_3_n_0\ : STD_LOGIC; + signal \sI2C_DataOut[3]_i_2_n_0\ : STD_LOGIC; + signal \sI2C_DataOut[3]_i_3_n_0\ : STD_LOGIC; + signal \sI2C_DataOut[4]_i_2_n_0\ : STD_LOGIC; + signal \sI2C_DataOut[4]_i_3_n_0\ : STD_LOGIC; + signal \sI2C_DataOut[5]_i_2_n_0\ : STD_LOGIC; + signal \sI2C_DataOut[5]_i_3_n_0\ : STD_LOGIC; + signal \sI2C_DataOut[6]_i_2_n_0\ : STD_LOGIC; + signal \sI2C_DataOut[6]_i_3_n_0\ : STD_LOGIC; + signal \sI2C_DataOut[7]_i_2_n_0\ : STD_LOGIC; + signal \sI2C_DataOut[7]_i_3_n_0\ : STD_LOGIC; + signal \sI2C_DataOut_reg[0]_i_1_n_0\ : STD_LOGIC; + signal \sI2C_DataOut_reg[1]_i_1_n_0\ : STD_LOGIC; + signal \sI2C_DataOut_reg[2]_i_1_n_0\ : STD_LOGIC; + signal \sI2C_DataOut_reg[3]_i_1_n_0\ : STD_LOGIC; + signal \sI2C_DataOut_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \sI2C_DataOut_reg[5]_i_1_n_0\ : STD_LOGIC; + signal \sI2C_DataOut_reg[6]_i_1_n_0\ : STD_LOGIC; + signal \sI2C_DataOut_reg[7]_i_1_n_0\ : STD_LOGIC; + signal sI2C_Done : STD_LOGIC; + signal sI2C_End : STD_LOGIC; + signal sState : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \sState[0]_i_1_n_0\ : STD_LOGIC; + signal \sState[1]_i_1_n_0\ : STD_LOGIC; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of \sAddr_reg_rep[0]\ : label is "no"; + attribute equivalent_register_removal of \sAddr_reg_rep[1]\ : label is "no"; + attribute equivalent_register_removal of \sAddr_reg_rep[2]\ : label is "no"; + attribute equivalent_register_removal of \sAddr_reg_rep[3]\ : label is "no"; + attribute equivalent_register_removal of \sAddr_reg_rep[4]\ : label is "no"; + attribute equivalent_register_removal of \sAddr_reg_rep[5]\ : label is "no"; + attribute equivalent_register_removal of \sAddr_reg_rep[6]\ : label is "no"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \sAddr_rep[4]_i_2\ : label is "soft_lutpair93"; + attribute SOFT_HLUTNM of \sAddr_rep[6]_i_3\ : label is "soft_lutpair93"; + attribute SOFT_HLUTNM of \sState[0]_i_1\ : label is "soft_lutpair92"; + attribute SOFT_HLUTNM of \sState[1]_i_1\ : label is "soft_lutpair92"; +begin +I2C_SlaveController: entity work.Arty_Z7_20_dvi2rgb_0_0_TWI_SlaveCtl + port map ( + D(6) => I2C_SlaveController_n_5, + D(5) => I2C_SlaveController_n_6, + D(4) => I2C_SlaveController_n_7, + D(3) => I2C_SlaveController_n_8, + D(2) => I2C_SlaveController_n_9, + D(1) => I2C_SlaveController_n_10, + D(0) => I2C_SlaveController_n_11, + DDC_SCL_I => DDC_SCL_I, + DDC_SDA_I => DDC_SDA_I, + DDC_SDA_T => DDC_SDA_T, + E(0) => I2C_SlaveController_n_4, + Q(7 downto 0) => sI2C_DataOut(7 downto 0), + RefClk => RefClk, + rd_wrn_reg_0 => I2C_SlaveController_n_2, + \sAddr_reg[3]\ => \sAddr_rep[4]_i_2_n_0\, + \sAddr_reg[4]\ => \sAddr_rep[6]_i_3_n_0\, + \sAddr_reg[6]\(6 downto 0) => sAddr(6 downto 0), + sI2C_Done => sI2C_Done, + sI2C_End => sI2C_End, + sState(1 downto 0) => sState(1 downto 0), + \sState_reg[0]\ => \sAddr_rep[3]_i_2_n_0\ + ); +\sAddr_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => I2C_SlaveController_n_4, + D => I2C_SlaveController_n_11, + Q => sAddr(0), + R => '0' + ); +\sAddr_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => I2C_SlaveController_n_4, + D => I2C_SlaveController_n_10, + Q => sAddr(1), + R => '0' + ); +\sAddr_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => I2C_SlaveController_n_4, + D => I2C_SlaveController_n_9, + Q => sAddr(2), + R => '0' + ); +\sAddr_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => I2C_SlaveController_n_4, + D => I2C_SlaveController_n_8, + Q => sAddr(3), + R => '0' + ); +\sAddr_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => I2C_SlaveController_n_4, + D => I2C_SlaveController_n_7, + Q => sAddr(4), + R => '0' + ); +\sAddr_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => I2C_SlaveController_n_4, + D => I2C_SlaveController_n_6, + Q => sAddr(5), + R => '0' + ); +\sAddr_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => I2C_SlaveController_n_4, + D => I2C_SlaveController_n_5, + Q => sAddr(6), + R => '0' + ); +\sAddr_reg_rep[0]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => I2C_SlaveController_n_4, + D => I2C_SlaveController_n_11, + Q => sAddr_0(0), + R => '0' + ); +\sAddr_reg_rep[1]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => I2C_SlaveController_n_4, + D => I2C_SlaveController_n_10, + Q => sAddr_0(1), + R => '0' + ); +\sAddr_reg_rep[2]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => I2C_SlaveController_n_4, + D => I2C_SlaveController_n_9, + Q => sAddr_0(2), + R => '0' + ); +\sAddr_reg_rep[3]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => I2C_SlaveController_n_4, + D => I2C_SlaveController_n_8, + Q => sAddr_0(3), + R => '0' + ); +\sAddr_reg_rep[4]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => I2C_SlaveController_n_4, + D => I2C_SlaveController_n_7, + Q => sAddr_0(4), + R => '0' + ); +\sAddr_reg_rep[5]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => I2C_SlaveController_n_4, + D => I2C_SlaveController_n_6, + Q => sAddr_0(5), + R => '0' + ); +\sAddr_reg_rep[6]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => I2C_SlaveController_n_4, + D => I2C_SlaveController_n_5, + Q => sAddr_0(6), + R => '0' + ); +\sAddr_rep[3]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => sState(0), + I1 => sState(1), + O => \sAddr_rep[3]_i_2_n_0\ + ); +\sAddr_rep[4]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => sAddr(3), + I1 => sAddr(1), + I2 => sAddr(0), + I3 => sAddr(2), + O => \sAddr_rep[4]_i_2_n_0\ + ); +\sAddr_rep[6]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => sAddr(4), + I1 => sAddr(2), + I2 => sAddr(0), + I3 => sAddr(1), + I4 => sAddr(3), + O => \sAddr_rep[6]_i_3_n_0\ + ); +\sI2C_DataOut[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5191505554755126" + ) + port map ( + I0 => sAddr_0(6), + I1 => sAddr_0(0), + I2 => sAddr_0(4), + I3 => sAddr_0(5), + I4 => sAddr_0(1), + I5 => sAddr_0(2), + O => \sI2C_DataOut[0]_i_2_n_0\ + ); +\sI2C_DataOut[0]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"010011114402A000" + ) + port map ( + I0 => sAddr_0(6), + I1 => sAddr_0(0), + I2 => sAddr_0(2), + I3 => sAddr_0(1), + I4 => sAddr_0(4), + I5 => sAddr_0(5), + O => \sI2C_DataOut[0]_i_3_n_0\ + ); +\sI2C_DataOut[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0129004700C50154" + ) + port map ( + I0 => sAddr_0(6), + I1 => sAddr_0(0), + I2 => sAddr_0(4), + I3 => sAddr_0(5), + I4 => sAddr_0(1), + I5 => sAddr_0(2), + O => \sI2C_DataOut[1]_i_2_n_0\ + ); +\sI2C_DataOut[1]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9000104008414090" + ) + port map ( + I0 => sAddr_0(6), + I1 => sAddr_0(0), + I2 => sAddr_0(4), + I3 => sAddr_0(2), + I4 => sAddr_0(1), + I5 => sAddr_0(5), + O => \sI2C_DataOut[1]_i_3_n_0\ + ); +\sI2C_DataOut[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"403900A501A50186" + ) + port map ( + I0 => sAddr_0(6), + I1 => sAddr_0(0), + I2 => sAddr_0(4), + I3 => sAddr_0(5), + I4 => sAddr_0(1), + I5 => sAddr_0(2), + O => \sI2C_DataOut[2]_i_2_n_0\ + ); +\sI2C_DataOut[2]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9100450600008884" + ) + port map ( + I0 => sAddr_0(6), + I1 => sAddr_0(0), + I2 => sAddr_0(1), + I3 => sAddr_0(2), + I4 => sAddr_0(5), + I5 => sAddr_0(4), + O => \sI2C_DataOut[2]_i_3_n_0\ + ); +\sI2C_DataOut[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"40D90105018505E4" + ) + port map ( + I0 => sAddr_0(6), + I1 => sAddr_0(0), + I2 => sAddr_0(4), + I3 => sAddr_0(5), + I4 => sAddr_0(1), + I5 => sAddr_0(2), + O => \sI2C_DataOut[3]_i_2_n_0\ + ); +\sI2C_DataOut[3]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D100100012180074" + ) + port map ( + I0 => sAddr_0(6), + I1 => sAddr_0(0), + I2 => sAddr_0(4), + I3 => sAddr_0(2), + I4 => sAddr_0(1), + I5 => sAddr_0(5), + O => \sI2C_DataOut[3]_i_3_n_0\ + ); +\sI2C_DataOut[4]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"41790067000D0046" + ) + port map ( + I0 => sAddr_0(6), + I1 => sAddr_0(0), + I2 => sAddr_0(4), + I3 => sAddr_0(5), + I4 => sAddr_0(1), + I5 => sAddr_0(2), + O => \sI2C_DataOut[4]_i_2_n_0\ + ); +\sI2C_DataOut[4]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0180510819004811" + ) + port map ( + I0 => sAddr_0(6), + I1 => sAddr_0(0), + I2 => sAddr_0(5), + I3 => sAddr_0(4), + I4 => sAddr_0(2), + I5 => sAddr_0(1), + O => \sI2C_DataOut[4]_i_3_n_0\ + ); +\sI2C_DataOut[5]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0141007504A500A4" + ) + port map ( + I0 => sAddr_0(6), + I1 => sAddr_0(0), + I2 => sAddr_0(4), + I3 => sAddr_0(5), + I4 => sAddr_0(1), + I5 => sAddr_0(2), + O => \sI2C_DataOut[5]_i_2_n_0\ + ); +\sI2C_DataOut[5]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"C5004040626002D8" + ) + port map ( + I0 => sAddr_0(6), + I1 => sAddr_0(4), + I2 => sAddr_0(0), + I3 => sAddr_0(2), + I4 => sAddr_0(1), + I5 => sAddr_0(5), + O => \sI2C_DataOut[5]_i_3_n_0\ + ); +\sI2C_DataOut[6]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000EAAA01041D76" + ) + port map ( + I0 => sAddr_0(6), + I1 => sAddr_0(0), + I2 => sAddr_0(2), + I3 => sAddr_0(1), + I4 => sAddr_0(5), + I5 => sAddr_0(4), + O => \sI2C_DataOut[6]_i_2_n_0\ + ); +\sI2C_DataOut[6]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"940450450A580844" + ) + port map ( + I0 => sAddr_0(6), + I1 => sAddr_0(0), + I2 => sAddr_0(4), + I3 => sAddr_0(1), + I4 => sAddr_0(2), + I5 => sAddr_0(5), + O => \sI2C_DataOut[6]_i_3_n_0\ + ); +\sI2C_DataOut[7]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"01010015000D0004" + ) + port map ( + I0 => sAddr_0(6), + I1 => sAddr_0(0), + I2 => sAddr_0(4), + I3 => sAddr_0(5), + I4 => sAddr_0(1), + I5 => sAddr_0(2), + O => \sI2C_DataOut[7]_i_2_n_0\ + ); +\sI2C_DataOut[7]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8400555514040804" + ) + port map ( + I0 => sAddr_0(6), + I1 => sAddr_0(0), + I2 => sAddr_0(2), + I3 => sAddr_0(1), + I4 => sAddr_0(4), + I5 => sAddr_0(5), + O => \sI2C_DataOut[7]_i_3_n_0\ + ); +\sI2C_DataOut_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => '1', + D => \sI2C_DataOut_reg[0]_i_1_n_0\, + Q => sI2C_DataOut(0), + R => '0' + ); +\sI2C_DataOut_reg[0]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \sI2C_DataOut[0]_i_2_n_0\, + I1 => \sI2C_DataOut[0]_i_3_n_0\, + O => \sI2C_DataOut_reg[0]_i_1_n_0\, + S => sAddr_0(3) + ); +\sI2C_DataOut_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => '1', + D => \sI2C_DataOut_reg[1]_i_1_n_0\, + Q => sI2C_DataOut(1), + R => '0' + ); +\sI2C_DataOut_reg[1]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \sI2C_DataOut[1]_i_2_n_0\, + I1 => \sI2C_DataOut[1]_i_3_n_0\, + O => \sI2C_DataOut_reg[1]_i_1_n_0\, + S => sAddr_0(3) + ); +\sI2C_DataOut_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => '1', + D => \sI2C_DataOut_reg[2]_i_1_n_0\, + Q => sI2C_DataOut(2), + R => '0' + ); +\sI2C_DataOut_reg[2]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \sI2C_DataOut[2]_i_2_n_0\, + I1 => \sI2C_DataOut[2]_i_3_n_0\, + O => \sI2C_DataOut_reg[2]_i_1_n_0\, + S => sAddr_0(3) + ); +\sI2C_DataOut_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => '1', + D => \sI2C_DataOut_reg[3]_i_1_n_0\, + Q => sI2C_DataOut(3), + R => '0' + ); +\sI2C_DataOut_reg[3]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \sI2C_DataOut[3]_i_2_n_0\, + I1 => \sI2C_DataOut[3]_i_3_n_0\, + O => \sI2C_DataOut_reg[3]_i_1_n_0\, + S => sAddr_0(3) + ); +\sI2C_DataOut_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => '1', + D => \sI2C_DataOut_reg[4]_i_1_n_0\, + Q => sI2C_DataOut(4), + R => '0' + ); +\sI2C_DataOut_reg[4]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \sI2C_DataOut[4]_i_2_n_0\, + I1 => \sI2C_DataOut[4]_i_3_n_0\, + O => \sI2C_DataOut_reg[4]_i_1_n_0\, + S => sAddr_0(3) + ); +\sI2C_DataOut_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => '1', + D => \sI2C_DataOut_reg[5]_i_1_n_0\, + Q => sI2C_DataOut(5), + R => '0' + ); +\sI2C_DataOut_reg[5]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \sI2C_DataOut[5]_i_2_n_0\, + I1 => \sI2C_DataOut[5]_i_3_n_0\, + O => \sI2C_DataOut_reg[5]_i_1_n_0\, + S => sAddr_0(3) + ); +\sI2C_DataOut_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => '1', + D => \sI2C_DataOut_reg[6]_i_1_n_0\, + Q => sI2C_DataOut(6), + R => '0' + ); +\sI2C_DataOut_reg[6]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \sI2C_DataOut[6]_i_2_n_0\, + I1 => \sI2C_DataOut[6]_i_3_n_0\, + O => \sI2C_DataOut_reg[6]_i_1_n_0\, + S => sAddr_0(3) + ); +\sI2C_DataOut_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => '1', + D => \sI2C_DataOut_reg[7]_i_1_n_0\, + Q => sI2C_DataOut(7), + R => '0' + ); +\sI2C_DataOut_reg[7]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \sI2C_DataOut[7]_i_2_n_0\, + I1 => \sI2C_DataOut[7]_i_3_n_0\, + O => \sI2C_DataOut_reg[7]_i_1_n_0\, + S => sAddr_0(3) + ); +\sState[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"105C" + ) + port map ( + I0 => sI2C_End, + I1 => sI2C_Done, + I2 => sState(0), + I3 => sState(1), + O => \sState[0]_i_1_n_0\ + ); +\sState[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"33330050" + ) + port map ( + I0 => I2C_SlaveController_n_2, + I1 => sI2C_End, + I2 => sI2C_Done, + I3 => sState(0), + I4 => sState(1), + O => \sState[1]_i_1_n_0\ + ); +\sState_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => '1', + D => \sState[0]_i_1_n_0\, + Q => sState(0), + R => '0' + ); +\sState_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => '1', + D => \sState[1]_i_1_n_0\, + Q => sState(1), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_TMDS_Clocking is + port ( + \pDataQ_reg[8]\ : out STD_LOGIC; + PixelClk_int : out STD_LOGIC; + aPixelClkLckd : out STD_LOGIC; + in0 : out STD_LOGIC; + RefClk : in STD_LOGIC; + TMDS_Clk_p : in STD_LOGIC; + TMDS_Clk_n : in STD_LOGIC; + aRst_n : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_TMDS_Clocking : entity is "TMDS_Clocking"; +end Arty_Z7_20_dvi2rgb_0_0_TMDS_Clocking; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_TMDS_Clocking is + signal CLKFBIN : STD_LOGIC; + signal CLK_IN_hdmi_clk : STD_LOGIC; + signal CLK_OUT_5x_hdmi_clk : STD_LOGIC; + signal CLR : STD_LOGIC; + signal LockLostReset_n_1 : STD_LOGIC; + signal MMCM_LockSync_n_1 : STD_LOGIC; + signal MMCM_LockSync_n_2 : STD_LOGIC; + signal RST : STD_LOGIC; + signal aDlyLckd : STD_LOGIC; + signal aMMCM_Locked : STD_LOGIC; + signal \^apixelclklckd\ : STD_LOGIC; + signal p_0_in : STD_LOGIC; + signal rDlyRstCnt0 : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \rDlyRstCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \rDlyRstCnt[2]_i_1_n_0\ : STD_LOGIC; + signal \rDlyRstCnt[3]_i_1_n_0\ : STD_LOGIC; + signal \rDlyRstCnt[4]_i_1_n_0\ : STD_LOGIC; + signal \rDlyRstCnt[4]_i_2_n_0\ : STD_LOGIC; + signal \rDlyRstCnt_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal rLockLostRst : STD_LOGIC; + signal rMMCM_LckdFallingFlag : STD_LOGIC; + signal rMMCM_Locked : STD_LOGIC; + signal \rMMCM_Locked_q_reg_n_0_[0]\ : STD_LOGIC; + signal rMMCM_Reset_q : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \rMMCM_Reset_q[0]_i_1_n_0\ : STD_LOGIC; + signal rRdyRst : STD_LOGIC; + signal NLW_DVI_ClkGenerator_CLKFBOUTB_UNCONNECTED : STD_LOGIC; + signal NLW_DVI_ClkGenerator_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC; + signal NLW_DVI_ClkGenerator_CLKINSTOPPED_UNCONNECTED : STD_LOGIC; + signal NLW_DVI_ClkGenerator_CLKOUT0B_UNCONNECTED : STD_LOGIC; + signal NLW_DVI_ClkGenerator_CLKOUT1_UNCONNECTED : STD_LOGIC; + signal NLW_DVI_ClkGenerator_CLKOUT1B_UNCONNECTED : STD_LOGIC; + signal NLW_DVI_ClkGenerator_CLKOUT2_UNCONNECTED : STD_LOGIC; + signal NLW_DVI_ClkGenerator_CLKOUT2B_UNCONNECTED : STD_LOGIC; + signal NLW_DVI_ClkGenerator_CLKOUT3_UNCONNECTED : STD_LOGIC; + signal NLW_DVI_ClkGenerator_CLKOUT3B_UNCONNECTED : STD_LOGIC; + signal NLW_DVI_ClkGenerator_CLKOUT4_UNCONNECTED : STD_LOGIC; + signal NLW_DVI_ClkGenerator_CLKOUT5_UNCONNECTED : STD_LOGIC; + signal NLW_DVI_ClkGenerator_CLKOUT6_UNCONNECTED : STD_LOGIC; + signal NLW_DVI_ClkGenerator_DRDY_UNCONNECTED : STD_LOGIC; + signal NLW_DVI_ClkGenerator_PSDONE_UNCONNECTED : STD_LOGIC; + signal NLW_DVI_ClkGenerator_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); + attribute box_type : string; + attribute box_type of DVI_ClkGenerator : label is "PRIMITIVE"; + attribute box_type of IDelayCtrlX : label is "PRIMITIVE"; + attribute CAPACITANCE : string; + attribute CAPACITANCE of InputBuffer : label is "DONT_CARE"; + attribute IBUF_DELAY_VALUE : string; + attribute IBUF_DELAY_VALUE of InputBuffer : label is "0"; + attribute IFD_DELAY_VALUE : string; + attribute IFD_DELAY_VALUE of InputBuffer : label is "AUTO"; + attribute box_type of InputBuffer : label is "PRIMITIVE"; + attribute box_type of PixelClkBuffer : label is "PRIMITIVE"; + attribute box_type of SerialClkBuffer : label is "PRIMITIVE"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \rDlyRstCnt[1]_i_1\ : label is "soft_lutpair95"; + attribute SOFT_HLUTNM of \rDlyRstCnt[2]_i_1\ : label is "soft_lutpair95"; + attribute SOFT_HLUTNM of \rDlyRstCnt[3]_i_1\ : label is "soft_lutpair94"; + attribute SOFT_HLUTNM of \rDlyRstCnt[4]_i_2\ : label is "soft_lutpair94"; +begin + aPixelClkLckd <= \^apixelclklckd\; +DVI_ClkGenerator: unisim.vcomponents.MMCME2_ADV + generic map( + BANDWIDTH => "OPTIMIZED", + CLKFBOUT_MULT_F => 10.000000, + CLKFBOUT_PHASE => 0.000000, + CLKFBOUT_USE_FINE_PS => false, + CLKIN1_PERIOD => 12.000000, + CLKIN2_PERIOD => 0.000000, + CLKOUT0_DIVIDE_F => 2.000000, + CLKOUT0_DUTY_CYCLE => 0.500000, + CLKOUT0_PHASE => 0.000000, + CLKOUT0_USE_FINE_PS => false, + CLKOUT1_DIVIDE => 1, + CLKOUT1_DUTY_CYCLE => 0.500000, + CLKOUT1_PHASE => 0.000000, + CLKOUT1_USE_FINE_PS => false, + CLKOUT2_DIVIDE => 1, + CLKOUT2_DUTY_CYCLE => 0.500000, + CLKOUT2_PHASE => 0.000000, + CLKOUT2_USE_FINE_PS => false, + CLKOUT3_DIVIDE => 1, + CLKOUT3_DUTY_CYCLE => 0.500000, + CLKOUT3_PHASE => 0.000000, + CLKOUT3_USE_FINE_PS => false, + CLKOUT4_CASCADE => false, + CLKOUT4_DIVIDE => 1, + CLKOUT4_DUTY_CYCLE => 0.500000, + CLKOUT4_PHASE => 0.000000, + CLKOUT4_USE_FINE_PS => false, + CLKOUT5_DIVIDE => 1, + CLKOUT5_DUTY_CYCLE => 0.500000, + CLKOUT5_PHASE => 0.000000, + CLKOUT5_USE_FINE_PS => false, + CLKOUT6_DIVIDE => 1, + CLKOUT6_DUTY_CYCLE => 0.500000, + CLKOUT6_PHASE => 0.000000, + CLKOUT6_USE_FINE_PS => false, + COMPENSATION => "INTERNAL", + DIVCLK_DIVIDE => 1, + IS_CLKINSEL_INVERTED => '0', + IS_PSEN_INVERTED => '0', + IS_PSINCDEC_INVERTED => '0', + IS_PWRDWN_INVERTED => '0', + IS_RST_INVERTED => '0', + REF_JITTER1 => 0.010000, + REF_JITTER2 => 0.000000, + SS_EN => "FALSE", + SS_MODE => "CENTER_HIGH", + SS_MOD_PERIOD => 10000, + STARTUP_WAIT => false + ) + port map ( + CLKFBIN => CLKFBIN, + CLKFBOUT => CLKFBIN, + CLKFBOUTB => NLW_DVI_ClkGenerator_CLKFBOUTB_UNCONNECTED, + CLKFBSTOPPED => NLW_DVI_ClkGenerator_CLKFBSTOPPED_UNCONNECTED, + CLKIN1 => CLK_IN_hdmi_clk, + CLKIN2 => '0', + CLKINSEL => '1', + CLKINSTOPPED => NLW_DVI_ClkGenerator_CLKINSTOPPED_UNCONNECTED, + CLKOUT0 => CLK_OUT_5x_hdmi_clk, + CLKOUT0B => NLW_DVI_ClkGenerator_CLKOUT0B_UNCONNECTED, + CLKOUT1 => NLW_DVI_ClkGenerator_CLKOUT1_UNCONNECTED, + CLKOUT1B => NLW_DVI_ClkGenerator_CLKOUT1B_UNCONNECTED, + CLKOUT2 => NLW_DVI_ClkGenerator_CLKOUT2_UNCONNECTED, + CLKOUT2B => NLW_DVI_ClkGenerator_CLKOUT2B_UNCONNECTED, + CLKOUT3 => NLW_DVI_ClkGenerator_CLKOUT3_UNCONNECTED, + CLKOUT3B => NLW_DVI_ClkGenerator_CLKOUT3B_UNCONNECTED, + CLKOUT4 => NLW_DVI_ClkGenerator_CLKOUT4_UNCONNECTED, + CLKOUT5 => NLW_DVI_ClkGenerator_CLKOUT5_UNCONNECTED, + CLKOUT6 => NLW_DVI_ClkGenerator_CLKOUT6_UNCONNECTED, + DADDR(6 downto 0) => B"0000000", + DCLK => '0', + DEN => '0', + DI(15 downto 0) => B"0000000000000000", + DO(15 downto 0) => NLW_DVI_ClkGenerator_DO_UNCONNECTED(15 downto 0), + DRDY => NLW_DVI_ClkGenerator_DRDY_UNCONNECTED, + DWE => '0', + LOCKED => aMMCM_Locked, + PSCLK => '0', + PSDONE => NLW_DVI_ClkGenerator_PSDONE_UNCONNECTED, + PSEN => '0', + PSINCDEC => '0', + PWRDWN => '0', + RST => rMMCM_Reset_q(0) + ); +IDelayCtrlX: unisim.vcomponents.IDELAYCTRL + generic map( + SIM_DEVICE => "7SERIES" + ) + port map ( + RDY => aDlyLckd, + REFCLK => RefClk, + RST => RST + ); +InputBuffer: unisim.vcomponents.IBUFDS + generic map( + DQS_BIAS => "FALSE" + ) + port map ( + I => TMDS_Clk_p, + IB => TMDS_Clk_n, + O => CLK_IN_hdmi_clk + ); +LockLostReset: entity work.Arty_Z7_20_dvi2rgb_0_0_ResetBridge_2 + port map ( + E(0) => \rDlyRstCnt[4]_i_1_n_0\, + RST => RST, + RefClk => RefClk, + SS(0) => rLockLostRst, + aRst_n => aRst_n, + rDlyRst_reg => LockLostReset_n_1 + ); +MMCM_LockSync: entity work.\Arty_Z7_20_dvi2rgb_0_0_SyncAsync__parameterized0\ + port map ( + D(0) => rMMCM_Locked, + Q(0) => p_0_in, + RefClk => RefClk, + rMMCM_LckdFallingFlag_reg => MMCM_LockSync_n_2, + rMMCM_LckdRisingFlag_reg => MMCM_LockSync_n_1, + \rMMCM_Reset_q_reg[0]\(0) => aMMCM_Locked + ); +PixelClkBuffer: unisim.vcomponents.BUFR + generic map( + BUFR_DIVIDE => "5", + SIM_DEVICE => "7SERIES" + ) + port map ( + CE => '1', + CLR => CLR, + I => CLK_OUT_5x_hdmi_clk, + O => PixelClk_int + ); +RdyLostReset: entity work.Arty_Z7_20_dvi2rgb_0_0_ResetBridge_3 + port map ( + RefClk => RefClk, + aDlyLckd => aDlyLckd, + \out\(0) => rRdyRst + ); +SerialClkBuffer: unisim.vcomponents.BUFIO + port map ( + I => CLK_OUT_5x_hdmi_clk, + O => \pDataQ_reg[8]\ + ); +aLocked_reg: unisim.vcomponents.FDCE + port map ( + C => RefClk, + CE => '1', + CLR => rRdyRst, + D => \rMMCM_Locked_q_reg_n_0_[0]\, + Q => \^apixelclklckd\ + ); +\aRst_int_inferred_i_1__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^apixelclklckd\, + O => in0 + ); +\rDlyRstCnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \rDlyRstCnt_reg__0\(0), + O => rDlyRstCnt0(0) + ); +\rDlyRstCnt[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \rDlyRstCnt_reg__0\(0), + I1 => \rDlyRstCnt_reg__0\(1), + O => \rDlyRstCnt[1]_i_1_n_0\ + ); +\rDlyRstCnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E1" + ) + port map ( + I0 => \rDlyRstCnt_reg__0\(1), + I1 => \rDlyRstCnt_reg__0\(0), + I2 => \rDlyRstCnt_reg__0\(2), + O => \rDlyRstCnt[2]_i_1_n_0\ + ); +\rDlyRstCnt[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FE01" + ) + port map ( + I0 => \rDlyRstCnt_reg__0\(1), + I1 => \rDlyRstCnt_reg__0\(0), + I2 => \rDlyRstCnt_reg__0\(2), + I3 => \rDlyRstCnt_reg__0\(3), + O => \rDlyRstCnt[3]_i_1_n_0\ + ); +\rDlyRstCnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => \rDlyRstCnt_reg__0\(2), + I1 => \rDlyRstCnt_reg__0\(0), + I2 => \rDlyRstCnt_reg__0\(1), + I3 => \rDlyRstCnt_reg__0\(3), + I4 => \rDlyRstCnt_reg__0\(4), + O => \rDlyRstCnt[4]_i_1_n_0\ + ); +\rDlyRstCnt[4]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFE0001" + ) + port map ( + I0 => \rDlyRstCnt_reg__0\(3), + I1 => \rDlyRstCnt_reg__0\(2), + I2 => \rDlyRstCnt_reg__0\(0), + I3 => \rDlyRstCnt_reg__0\(1), + I4 => \rDlyRstCnt_reg__0\(4), + O => \rDlyRstCnt[4]_i_2_n_0\ + ); +\rDlyRstCnt_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => RefClk, + CE => \rDlyRstCnt[4]_i_1_n_0\, + D => rDlyRstCnt0(0), + Q => \rDlyRstCnt_reg__0\(0), + S => rLockLostRst + ); +\rDlyRstCnt_reg[1]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => RefClk, + CE => \rDlyRstCnt[4]_i_1_n_0\, + D => \rDlyRstCnt[1]_i_1_n_0\, + Q => \rDlyRstCnt_reg__0\(1), + S => rLockLostRst + ); +\rDlyRstCnt_reg[2]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => RefClk, + CE => \rDlyRstCnt[4]_i_1_n_0\, + D => \rDlyRstCnt[2]_i_1_n_0\, + Q => \rDlyRstCnt_reg__0\(2), + S => rLockLostRst + ); +\rDlyRstCnt_reg[3]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => RefClk, + CE => \rDlyRstCnt[4]_i_1_n_0\, + D => \rDlyRstCnt[3]_i_1_n_0\, + Q => \rDlyRstCnt_reg__0\(3), + S => rLockLostRst + ); +\rDlyRstCnt_reg[4]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => RefClk, + CE => \rDlyRstCnt[4]_i_1_n_0\, + D => \rDlyRstCnt[4]_i_2_n_0\, + Q => \rDlyRstCnt_reg__0\(4), + S => rLockLostRst + ); +rDlyRst_reg: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => '1', + D => LockLostReset_n_1, + Q => RST, + R => '0' + ); +rMMCM_LckdFallingFlag_reg: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => '1', + D => MMCM_LockSync_n_2, + Q => rMMCM_LckdFallingFlag, + R => '0' + ); +rMMCM_LckdRisingFlag_reg: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => '1', + D => MMCM_LockSync_n_1, + Q => CLR, + R => '0' + ); +\rMMCM_Locked_q_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => '1', + D => p_0_in, + Q => \rMMCM_Locked_q_reg_n_0_[0]\, + R => '0' + ); +\rMMCM_Locked_q_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => '1', + D => rMMCM_Locked, + Q => p_0_in, + R => '0' + ); +\rMMCM_Reset_q[0]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => rMMCM_LckdFallingFlag, + I1 => rMMCM_Reset_q(1), + O => \rMMCM_Reset_q[0]_i_1_n_0\ + ); +\rMMCM_Reset_q_reg[0]\: unisim.vcomponents.FDPE + port map ( + C => RefClk, + CE => '1', + D => \rMMCM_Reset_q[0]_i_1_n_0\, + PRE => rLockLostRst, + Q => rMMCM_Reset_q(0) + ); +\rMMCM_Reset_q_reg[1]\: unisim.vcomponents.FDPE + port map ( + C => RefClk, + CE => '1', + D => rMMCM_LckdFallingFlag, + PRE => rLockLostRst, + Q => rMMCM_Reset_q(1) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_TMDS_Decoder is + port ( + pVde : out STD_LOGIC; + pVld_0 : out STD_LOGIC; + pRdy_0 : out STD_LOGIC; + pC0 : out STD_LOGIC; + pC1 : out STD_LOGIC; + pAllVld : out STD_LOGIC; + \pDataIn_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + Q : out STD_LOGIC_VECTOR ( 7 downto 0 ); + TMDS_Data_p : in STD_LOGIC_VECTOR ( 0 to 0 ); + TMDS_Data_n : in STD_LOGIC_VECTOR ( 0 to 0 ); + PixelClk_int : in STD_LOGIC; + \rMMCM_Reset_q_reg[0]\ : in STD_LOGIC; + CLKB : in STD_LOGIC; + AS : in STD_LOGIC_VECTOR ( 0 to 0 ); + RefClk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + pAligned_reg : in STD_LOGIC; + pVld_2 : in STD_LOGIC; + pVld_1 : in STD_LOGIC; + pRdy_1 : in STD_LOGIC; + pRdy_2 : in STD_LOGIC; + pRst_n : in STD_LOGIC; + pAllVldBgnFlag : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_TMDS_Decoder : entity is "TMDS_Decoder"; +end Arty_Z7_20_dvi2rgb_0_0_TMDS_Decoder; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_TMDS_Decoder is + signal ChannelBondX_n_3 : STD_LOGIC; + signal ChannelBondX_n_4 : STD_LOGIC; + signal PhaseAlignX_n_4 : STD_LOGIC; + signal PhaseAlignX_n_5 : STD_LOGIC; + signal PhaseAlignX_n_7 : STD_LOGIC; + signal SyncBaseOvf_n_1 : STD_LOGIC; + signal SyncBaseOvf_n_2 : STD_LOGIC; + signal SyncBaseOvf_n_3 : STD_LOGIC; + signal SyncBaseOvf_n_4 : STD_LOGIC; + signal pAlignErr_q : STD_LOGIC; + signal \pAlignRst_i_1__1_n_0\ : STD_LOGIC; + signal pAlignRst_reg_n_0 : STD_LOGIC; + signal \^pallvld\ : STD_LOGIC; + signal pBitslip : STD_LOGIC; + signal pBitslipCnt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \pBitslipCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \pBitslipCnt[1]_i_1_n_0\ : STD_LOGIC; + signal \^pc0\ : STD_LOGIC; + signal \^pc1\ : STD_LOGIC; + signal pDataIn : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal pDataInRaw : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal pIDLY_CE : STD_LOGIC; + signal pIDLY_CNT : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal pIDLY_INC : STD_LOGIC; + signal pIDLY_LD : STD_LOGIC; + signal pTimeoutOvf : STD_LOGIC; + signal pVde_0 : STD_LOGIC; + signal \rTimeoutCnt[0]_i_1__1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[0]_i_3__1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[0]_i_4__1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[0]_i_5__1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[0]_i_6__1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[12]_i_2__1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[12]_i_3__1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[12]_i_4__1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[12]_i_5__1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[16]_i_2__1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[16]_i_3__1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[16]_i_4__1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[16]_i_5__1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[20]_i_2__1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[20]_i_3__1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[20]_i_4__1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[20]_i_5__1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[4]_i_2__1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[4]_i_3__1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[4]_i_4__1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[4]_i_5__1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[8]_i_2__1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[8]_i_3__1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[8]_i_4__1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[8]_i_5__1_n_0\ : STD_LOGIC; + signal rTimeoutCnt_reg : STD_LOGIC_VECTOR ( 23 downto 0 ); + signal \rTimeoutCnt_reg[0]_i_2__1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt_reg[0]_i_2__1_n_1\ : STD_LOGIC; + signal \rTimeoutCnt_reg[0]_i_2__1_n_2\ : STD_LOGIC; + signal \rTimeoutCnt_reg[0]_i_2__1_n_3\ : STD_LOGIC; + signal \rTimeoutCnt_reg[0]_i_2__1_n_4\ : STD_LOGIC; + signal \rTimeoutCnt_reg[0]_i_2__1_n_5\ : STD_LOGIC; + signal \rTimeoutCnt_reg[0]_i_2__1_n_6\ : STD_LOGIC; + signal \rTimeoutCnt_reg[0]_i_2__1_n_7\ : STD_LOGIC; + signal \rTimeoutCnt_reg[12]_i_1__1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt_reg[12]_i_1__1_n_1\ : STD_LOGIC; + signal \rTimeoutCnt_reg[12]_i_1__1_n_2\ : STD_LOGIC; + signal \rTimeoutCnt_reg[12]_i_1__1_n_3\ : STD_LOGIC; + signal \rTimeoutCnt_reg[12]_i_1__1_n_4\ : STD_LOGIC; + signal \rTimeoutCnt_reg[12]_i_1__1_n_5\ : STD_LOGIC; + signal \rTimeoutCnt_reg[12]_i_1__1_n_6\ : STD_LOGIC; + signal \rTimeoutCnt_reg[12]_i_1__1_n_7\ : STD_LOGIC; + signal \rTimeoutCnt_reg[16]_i_1__1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt_reg[16]_i_1__1_n_1\ : STD_LOGIC; + signal \rTimeoutCnt_reg[16]_i_1__1_n_2\ : STD_LOGIC; + signal \rTimeoutCnt_reg[16]_i_1__1_n_3\ : STD_LOGIC; + signal \rTimeoutCnt_reg[16]_i_1__1_n_4\ : STD_LOGIC; + signal \rTimeoutCnt_reg[16]_i_1__1_n_5\ : STD_LOGIC; + signal \rTimeoutCnt_reg[16]_i_1__1_n_6\ : STD_LOGIC; + signal \rTimeoutCnt_reg[16]_i_1__1_n_7\ : STD_LOGIC; + signal \rTimeoutCnt_reg[20]_i_1__1_n_1\ : STD_LOGIC; + signal \rTimeoutCnt_reg[20]_i_1__1_n_2\ : STD_LOGIC; + signal \rTimeoutCnt_reg[20]_i_1__1_n_3\ : STD_LOGIC; + signal \rTimeoutCnt_reg[20]_i_1__1_n_4\ : STD_LOGIC; + signal \rTimeoutCnt_reg[20]_i_1__1_n_5\ : STD_LOGIC; + signal \rTimeoutCnt_reg[20]_i_1__1_n_6\ : STD_LOGIC; + signal \rTimeoutCnt_reg[20]_i_1__1_n_7\ : STD_LOGIC; + signal \rTimeoutCnt_reg[4]_i_1__1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt_reg[4]_i_1__1_n_1\ : STD_LOGIC; + signal \rTimeoutCnt_reg[4]_i_1__1_n_2\ : STD_LOGIC; + signal \rTimeoutCnt_reg[4]_i_1__1_n_3\ : STD_LOGIC; + signal \rTimeoutCnt_reg[4]_i_1__1_n_4\ : STD_LOGIC; + signal \rTimeoutCnt_reg[4]_i_1__1_n_5\ : STD_LOGIC; + signal \rTimeoutCnt_reg[4]_i_1__1_n_6\ : STD_LOGIC; + signal \rTimeoutCnt_reg[4]_i_1__1_n_7\ : STD_LOGIC; + signal \rTimeoutCnt_reg[8]_i_1__1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt_reg[8]_i_1__1_n_1\ : STD_LOGIC; + signal \rTimeoutCnt_reg[8]_i_1__1_n_2\ : STD_LOGIC; + signal \rTimeoutCnt_reg[8]_i_1__1_n_3\ : STD_LOGIC; + signal \rTimeoutCnt_reg[8]_i_1__1_n_4\ : STD_LOGIC; + signal \rTimeoutCnt_reg[8]_i_1__1_n_5\ : STD_LOGIC; + signal \rTimeoutCnt_reg[8]_i_1__1_n_6\ : STD_LOGIC; + signal \rTimeoutCnt_reg[8]_i_1__1_n_7\ : STD_LOGIC; + signal rTimeoutRst : STD_LOGIC; + signal \NLW_rTimeoutCnt_reg[20]_i_1__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \pBitslipCnt[0]_i_1\ : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of \pBitslipCnt[1]_i_1\ : label is "soft_lutpair25"; +begin + pAllVld <= \^pallvld\; + pC0 <= \^pc0\; + pC1 <= \^pc1\; +ChannelBondX: entity work.Arty_Z7_20_dvi2rgb_0_0_ChannelBond_17 + port map ( + D(7 downto 0) => pDataIn(7 downto 0), + PixelClk_int => PixelClk_int, + pAligned_reg => pAligned_reg, + pAllVld => \^pallvld\, + pAllVldBgnFlag => pAllVldBgnFlag, + pC0 => \^pc0\, + pC0_reg => ChannelBondX_n_4, + pC1 => \^pc1\, + pC1_reg => ChannelBondX_n_3, + pDataInRaw(9 downto 0) => pDataInRaw(9 downto 0), + \pDataIn_reg[7]\(0) => \pDataIn_reg[7]_0\(0), + pMeRdy_int_reg_0 => pRdy_0, + pRdy_1 => pRdy_1, + pRdy_2 => pRdy_2, + pVde_0 => pVde_0 + ); +InputSERDES_X: entity work.Arty_Z7_20_dvi2rgb_0_0_InputSERDES_18 + port map ( + AS(0) => AS(0), + CLKB => CLKB, + D(4 downto 0) => pIDLY_CNT(4 downto 0), + PixelClk_int => PixelClk_int, + TMDS_Data_n(0) => TMDS_Data_n(0), + TMDS_Data_p(0) => TMDS_Data_p(0), + pBitslip => pBitslip, + pDataInRaw(9 downto 0) => pDataInRaw(9 downto 0), + pIDLY_CE => pIDLY_CE, + pIDLY_INC => pIDLY_INC, + pIDLY_LD => pIDLY_LD, + \rMMCM_Reset_q_reg[0]\ => \rMMCM_Reset_q_reg[0]\ + ); +PhaseAlignX: entity work.Arty_Z7_20_dvi2rgb_0_0_PhaseAlign_19 + port map ( + D(8 downto 0) => pDataInRaw(8 downto 0), + PixelClk_int => PixelClk_int, + SS(0) => pAlignRst_reg_n_0, + iIn_q_reg => PhaseAlignX_n_5, + \out\(0) => pTimeoutOvf, + pAlignErr_q => pAlignErr_q, + pAlignErr_q_reg => PhaseAlignX_n_4, + pAllVld => \^pallvld\, + pBitslip_reg => PhaseAlignX_n_7, + pIDLY_CE => pIDLY_CE, + pIDLY_CE_reg_0(4 downto 0) => pIDLY_CNT(4 downto 0), + pIDLY_INC => pIDLY_INC, + pIDLY_LD => pIDLY_LD, + pVld_0 => pVld_0, + pVld_1 => pVld_1, + pVld_2 => pVld_2 + ); +SyncBaseOvf: entity work.Arty_Z7_20_dvi2rgb_0_0_SyncBase_20 + port map ( + AS(0) => AS(0), + PixelClk_int => PixelClk_int, + RefClk => RefClk, + iIn_q_reg_0 => SyncBaseOvf_n_1, + iIn_q_reg_1 => SyncBaseOvf_n_2, + iIn_q_reg_2 => SyncBaseOvf_n_3, + iIn_q_reg_3 => SyncBaseOvf_n_4, + \out\(0) => pTimeoutOvf, + rTimeoutCnt_reg(23 downto 0) => rTimeoutCnt_reg(23 downto 0) + ); +SyncBaseRst: entity work.\Arty_Z7_20_dvi2rgb_0_0_SyncBase__parameterized0_21\ + port map ( + AS(0) => AS(0), + PixelClk_int => PixelClk_int, + RefClk => RefClk, + \out\(0) => rTimeoutRst, + \pState_reg[1]\ => PhaseAlignX_n_5 + ); +pAlignErr_q_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => PhaseAlignX_n_4, + Q => pAlignErr_q, + R => '0' + ); +\pAlignRst_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFDDDDD" + ) + port map ( + I0 => pRst_n, + I1 => pBitslip, + I2 => pBitslipCnt(1), + I3 => pBitslipCnt(0), + I4 => pAlignRst_reg_n_0, + O => \pAlignRst_i_1__1_n_0\ + ); +pAlignRst_reg: unisim.vcomponents.FDPE + port map ( + C => PixelClk_int, + CE => '1', + D => \pAlignRst_i_1__1_n_0\, + PRE => AS(0), + Q => pAlignRst_reg_n_0 + ); +\pBitslipCnt[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => pBitslipCnt(0), + I1 => pBitslipCnt(1), + I2 => pBitslip, + O => \pBitslipCnt[0]_i_1_n_0\ + ); +\pBitslipCnt[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"F8" + ) + port map ( + I0 => pBitslipCnt(0), + I1 => pBitslipCnt(1), + I2 => pBitslip, + O => \pBitslipCnt[1]_i_1_n_0\ + ); +\pBitslipCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => PixelClk_int, + CE => '1', + D => \pBitslipCnt[0]_i_1_n_0\, + Q => pBitslipCnt(0), + R => '0' + ); +\pBitslipCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => PixelClk_int, + CE => '1', + D => \pBitslipCnt[1]_i_1_n_0\, + Q => pBitslipCnt(1), + R => '0' + ); +pBitslip_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => PhaseAlignX_n_7, + Q => pBitslip, + R => '0' + ); +pC0_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => ChannelBondX_n_4, + Q => \^pc0\, + R => SR(0) + ); +pC1_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => ChannelBondX_n_3, + Q => \^pc1\, + R => SR(0) + ); +\pDataIn_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pDataIn(0), + Q => Q(0), + R => SR(0) + ); +\pDataIn_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pDataIn(1), + Q => Q(1), + R => SR(0) + ); +\pDataIn_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pDataIn(2), + Q => Q(2), + R => SR(0) + ); +\pDataIn_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pDataIn(3), + Q => Q(3), + R => SR(0) + ); +\pDataIn_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pDataIn(4), + Q => Q(4), + R => SR(0) + ); +\pDataIn_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pDataIn(5), + Q => Q(5), + R => SR(0) + ); +\pDataIn_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pDataIn(6), + Q => Q(6), + R => SR(0) + ); +\pDataIn_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pDataIn(7), + Q => Q(7), + R => SR(0) + ); +pVde_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pVde_0, + Q => pVde, + R => SR(0) + ); +\rTimeoutCnt[0]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BFFF" + ) + port map ( + I0 => SyncBaseOvf_n_1, + I1 => SyncBaseOvf_n_2, + I2 => SyncBaseOvf_n_3, + I3 => SyncBaseOvf_n_4, + O => \rTimeoutCnt[0]_i_1__1_n_0\ + ); +\rTimeoutCnt[0]_i_3__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(3), + O => \rTimeoutCnt[0]_i_3__1_n_0\ + ); +\rTimeoutCnt[0]_i_4__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(2), + O => \rTimeoutCnt[0]_i_4__1_n_0\ + ); +\rTimeoutCnt[0]_i_5__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(1), + O => \rTimeoutCnt[0]_i_5__1_n_0\ + ); +\rTimeoutCnt[0]_i_6__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => rTimeoutCnt_reg(0), + O => \rTimeoutCnt[0]_i_6__1_n_0\ + ); +\rTimeoutCnt[12]_i_2__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(15), + O => \rTimeoutCnt[12]_i_2__1_n_0\ + ); +\rTimeoutCnt[12]_i_3__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(14), + O => \rTimeoutCnt[12]_i_3__1_n_0\ + ); +\rTimeoutCnt[12]_i_4__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(13), + O => \rTimeoutCnt[12]_i_4__1_n_0\ + ); +\rTimeoutCnt[12]_i_5__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(12), + O => \rTimeoutCnt[12]_i_5__1_n_0\ + ); +\rTimeoutCnt[16]_i_2__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(19), + O => \rTimeoutCnt[16]_i_2__1_n_0\ + ); +\rTimeoutCnt[16]_i_3__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(18), + O => \rTimeoutCnt[16]_i_3__1_n_0\ + ); +\rTimeoutCnt[16]_i_4__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(17), + O => \rTimeoutCnt[16]_i_4__1_n_0\ + ); +\rTimeoutCnt[16]_i_5__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(16), + O => \rTimeoutCnt[16]_i_5__1_n_0\ + ); +\rTimeoutCnt[20]_i_2__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(23), + O => \rTimeoutCnt[20]_i_2__1_n_0\ + ); +\rTimeoutCnt[20]_i_3__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(22), + O => \rTimeoutCnt[20]_i_3__1_n_0\ + ); +\rTimeoutCnt[20]_i_4__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(21), + O => \rTimeoutCnt[20]_i_4__1_n_0\ + ); +\rTimeoutCnt[20]_i_5__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(20), + O => \rTimeoutCnt[20]_i_5__1_n_0\ + ); +\rTimeoutCnt[4]_i_2__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(7), + O => \rTimeoutCnt[4]_i_2__1_n_0\ + ); +\rTimeoutCnt[4]_i_3__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(6), + O => \rTimeoutCnt[4]_i_3__1_n_0\ + ); +\rTimeoutCnt[4]_i_4__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(5), + O => \rTimeoutCnt[4]_i_4__1_n_0\ + ); +\rTimeoutCnt[4]_i_5__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(4), + O => \rTimeoutCnt[4]_i_5__1_n_0\ + ); +\rTimeoutCnt[8]_i_2__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(11), + O => \rTimeoutCnt[8]_i_2__1_n_0\ + ); +\rTimeoutCnt[8]_i_3__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(10), + O => \rTimeoutCnt[8]_i_3__1_n_0\ + ); +\rTimeoutCnt[8]_i_4__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(9), + O => \rTimeoutCnt[8]_i_4__1_n_0\ + ); +\rTimeoutCnt[8]_i_5__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(8), + O => \rTimeoutCnt[8]_i_5__1_n_0\ + ); +\rTimeoutCnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__1_n_0\, + D => \rTimeoutCnt_reg[0]_i_2__1_n_7\, + Q => rTimeoutCnt_reg(0), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[0]_i_2__1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \rTimeoutCnt_reg[0]_i_2__1_n_0\, + CO(2) => \rTimeoutCnt_reg[0]_i_2__1_n_1\, + CO(1) => \rTimeoutCnt_reg[0]_i_2__1_n_2\, + CO(0) => \rTimeoutCnt_reg[0]_i_2__1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \rTimeoutCnt_reg[0]_i_2__1_n_4\, + O(2) => \rTimeoutCnt_reg[0]_i_2__1_n_5\, + O(1) => \rTimeoutCnt_reg[0]_i_2__1_n_6\, + O(0) => \rTimeoutCnt_reg[0]_i_2__1_n_7\, + S(3) => \rTimeoutCnt[0]_i_3__1_n_0\, + S(2) => \rTimeoutCnt[0]_i_4__1_n_0\, + S(1) => \rTimeoutCnt[0]_i_5__1_n_0\, + S(0) => \rTimeoutCnt[0]_i_6__1_n_0\ + ); +\rTimeoutCnt_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__1_n_0\, + D => \rTimeoutCnt_reg[8]_i_1__1_n_5\, + Q => rTimeoutCnt_reg(10), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__1_n_0\, + D => \rTimeoutCnt_reg[8]_i_1__1_n_4\, + Q => rTimeoutCnt_reg(11), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__1_n_0\, + D => \rTimeoutCnt_reg[12]_i_1__1_n_7\, + Q => rTimeoutCnt_reg(12), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[12]_i_1__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \rTimeoutCnt_reg[8]_i_1__1_n_0\, + CO(3) => \rTimeoutCnt_reg[12]_i_1__1_n_0\, + CO(2) => \rTimeoutCnt_reg[12]_i_1__1_n_1\, + CO(1) => \rTimeoutCnt_reg[12]_i_1__1_n_2\, + CO(0) => \rTimeoutCnt_reg[12]_i_1__1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \rTimeoutCnt_reg[12]_i_1__1_n_4\, + O(2) => \rTimeoutCnt_reg[12]_i_1__1_n_5\, + O(1) => \rTimeoutCnt_reg[12]_i_1__1_n_6\, + O(0) => \rTimeoutCnt_reg[12]_i_1__1_n_7\, + S(3) => \rTimeoutCnt[12]_i_2__1_n_0\, + S(2) => \rTimeoutCnt[12]_i_3__1_n_0\, + S(1) => \rTimeoutCnt[12]_i_4__1_n_0\, + S(0) => \rTimeoutCnt[12]_i_5__1_n_0\ + ); +\rTimeoutCnt_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__1_n_0\, + D => \rTimeoutCnt_reg[12]_i_1__1_n_6\, + Q => rTimeoutCnt_reg(13), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__1_n_0\, + D => \rTimeoutCnt_reg[12]_i_1__1_n_5\, + Q => rTimeoutCnt_reg(14), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__1_n_0\, + D => \rTimeoutCnt_reg[12]_i_1__1_n_4\, + Q => rTimeoutCnt_reg(15), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__1_n_0\, + D => \rTimeoutCnt_reg[16]_i_1__1_n_7\, + Q => rTimeoutCnt_reg(16), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[16]_i_1__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \rTimeoutCnt_reg[12]_i_1__1_n_0\, + CO(3) => \rTimeoutCnt_reg[16]_i_1__1_n_0\, + CO(2) => \rTimeoutCnt_reg[16]_i_1__1_n_1\, + CO(1) => \rTimeoutCnt_reg[16]_i_1__1_n_2\, + CO(0) => \rTimeoutCnt_reg[16]_i_1__1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \rTimeoutCnt_reg[16]_i_1__1_n_4\, + O(2) => \rTimeoutCnt_reg[16]_i_1__1_n_5\, + O(1) => \rTimeoutCnt_reg[16]_i_1__1_n_6\, + O(0) => \rTimeoutCnt_reg[16]_i_1__1_n_7\, + S(3) => \rTimeoutCnt[16]_i_2__1_n_0\, + S(2) => \rTimeoutCnt[16]_i_3__1_n_0\, + S(1) => \rTimeoutCnt[16]_i_4__1_n_0\, + S(0) => \rTimeoutCnt[16]_i_5__1_n_0\ + ); +\rTimeoutCnt_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__1_n_0\, + D => \rTimeoutCnt_reg[16]_i_1__1_n_6\, + Q => rTimeoutCnt_reg(17), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__1_n_0\, + D => \rTimeoutCnt_reg[16]_i_1__1_n_5\, + Q => rTimeoutCnt_reg(18), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__1_n_0\, + D => \rTimeoutCnt_reg[16]_i_1__1_n_4\, + Q => rTimeoutCnt_reg(19), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__1_n_0\, + D => \rTimeoutCnt_reg[0]_i_2__1_n_6\, + Q => rTimeoutCnt_reg(1), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__1_n_0\, + D => \rTimeoutCnt_reg[20]_i_1__1_n_7\, + Q => rTimeoutCnt_reg(20), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[20]_i_1__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \rTimeoutCnt_reg[16]_i_1__1_n_0\, + CO(3) => \NLW_rTimeoutCnt_reg[20]_i_1__1_CO_UNCONNECTED\(3), + CO(2) => \rTimeoutCnt_reg[20]_i_1__1_n_1\, + CO(1) => \rTimeoutCnt_reg[20]_i_1__1_n_2\, + CO(0) => \rTimeoutCnt_reg[20]_i_1__1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \rTimeoutCnt_reg[20]_i_1__1_n_4\, + O(2) => \rTimeoutCnt_reg[20]_i_1__1_n_5\, + O(1) => \rTimeoutCnt_reg[20]_i_1__1_n_6\, + O(0) => \rTimeoutCnt_reg[20]_i_1__1_n_7\, + S(3) => \rTimeoutCnt[20]_i_2__1_n_0\, + S(2) => \rTimeoutCnt[20]_i_3__1_n_0\, + S(1) => \rTimeoutCnt[20]_i_4__1_n_0\, + S(0) => \rTimeoutCnt[20]_i_5__1_n_0\ + ); +\rTimeoutCnt_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__1_n_0\, + D => \rTimeoutCnt_reg[20]_i_1__1_n_6\, + Q => rTimeoutCnt_reg(21), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__1_n_0\, + D => \rTimeoutCnt_reg[20]_i_1__1_n_5\, + Q => rTimeoutCnt_reg(22), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__1_n_0\, + D => \rTimeoutCnt_reg[20]_i_1__1_n_4\, + Q => rTimeoutCnt_reg(23), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__1_n_0\, + D => \rTimeoutCnt_reg[0]_i_2__1_n_5\, + Q => rTimeoutCnt_reg(2), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__1_n_0\, + D => \rTimeoutCnt_reg[0]_i_2__1_n_4\, + Q => rTimeoutCnt_reg(3), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__1_n_0\, + D => \rTimeoutCnt_reg[4]_i_1__1_n_7\, + Q => rTimeoutCnt_reg(4), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[4]_i_1__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \rTimeoutCnt_reg[0]_i_2__1_n_0\, + CO(3) => \rTimeoutCnt_reg[4]_i_1__1_n_0\, + CO(2) => \rTimeoutCnt_reg[4]_i_1__1_n_1\, + CO(1) => \rTimeoutCnt_reg[4]_i_1__1_n_2\, + CO(0) => \rTimeoutCnt_reg[4]_i_1__1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \rTimeoutCnt_reg[4]_i_1__1_n_4\, + O(2) => \rTimeoutCnt_reg[4]_i_1__1_n_5\, + O(1) => \rTimeoutCnt_reg[4]_i_1__1_n_6\, + O(0) => \rTimeoutCnt_reg[4]_i_1__1_n_7\, + S(3) => \rTimeoutCnt[4]_i_2__1_n_0\, + S(2) => \rTimeoutCnt[4]_i_3__1_n_0\, + S(1) => \rTimeoutCnt[4]_i_4__1_n_0\, + S(0) => \rTimeoutCnt[4]_i_5__1_n_0\ + ); +\rTimeoutCnt_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__1_n_0\, + D => \rTimeoutCnt_reg[4]_i_1__1_n_6\, + Q => rTimeoutCnt_reg(5), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__1_n_0\, + D => \rTimeoutCnt_reg[4]_i_1__1_n_5\, + Q => rTimeoutCnt_reg(6), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__1_n_0\, + D => \rTimeoutCnt_reg[4]_i_1__1_n_4\, + Q => rTimeoutCnt_reg(7), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__1_n_0\, + D => \rTimeoutCnt_reg[8]_i_1__1_n_7\, + Q => rTimeoutCnt_reg(8), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[8]_i_1__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \rTimeoutCnt_reg[4]_i_1__1_n_0\, + CO(3) => \rTimeoutCnt_reg[8]_i_1__1_n_0\, + CO(2) => \rTimeoutCnt_reg[8]_i_1__1_n_1\, + CO(1) => \rTimeoutCnt_reg[8]_i_1__1_n_2\, + CO(0) => \rTimeoutCnt_reg[8]_i_1__1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \rTimeoutCnt_reg[8]_i_1__1_n_4\, + O(2) => \rTimeoutCnt_reg[8]_i_1__1_n_5\, + O(1) => \rTimeoutCnt_reg[8]_i_1__1_n_6\, + O(0) => \rTimeoutCnt_reg[8]_i_1__1_n_7\, + S(3) => \rTimeoutCnt[8]_i_2__1_n_0\, + S(2) => \rTimeoutCnt[8]_i_3__1_n_0\, + S(1) => \rTimeoutCnt[8]_i_4__1_n_0\, + S(0) => \rTimeoutCnt[8]_i_5__1_n_0\ + ); +\rTimeoutCnt_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__1_n_0\, + D => \rTimeoutCnt_reg[8]_i_1__1_n_6\, + Q => rTimeoutCnt_reg(9), + R => rTimeoutRst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_TMDS_Decoder_0 is + port ( + pMeRdy_int_reg : out STD_LOGIC; + pRdy_1 : out STD_LOGIC; + pVld_1 : out STD_LOGIC; + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + Q : out STD_LOGIC_VECTOR ( 7 downto 0 ); + TMDS_Data_p : in STD_LOGIC_VECTOR ( 0 to 0 ); + TMDS_Data_n : in STD_LOGIC_VECTOR ( 0 to 0 ); + PixelClk_int : in STD_LOGIC; + \rMMCM_Reset_q_reg[0]\ : in STD_LOGIC; + CLKB : in STD_LOGIC; + AS : in STD_LOGIC_VECTOR ( 0 to 0 ); + RefClk : in STD_LOGIC; + pVld_2 : in STD_LOGIC; + pVld_0 : in STD_LOGIC; + pRdy_2 : in STD_LOGIC; + pRdy_0 : in STD_LOGIC; + pRst_n : in STD_LOGIC; + pAllVldBgnFlag : in STD_LOGIC; + pAllVld : in STD_LOGIC; + pMeRdy_int_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_TMDS_Decoder_0 : entity is "TMDS_Decoder"; +end Arty_Z7_20_dvi2rgb_0_0_TMDS_Decoder_0; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_TMDS_Decoder_0 is + signal PhaseAlignX_n_4 : STD_LOGIC; + signal PhaseAlignX_n_5 : STD_LOGIC; + signal PhaseAlignX_n_7 : STD_LOGIC; + signal SyncBaseOvf_n_1 : STD_LOGIC; + signal SyncBaseOvf_n_2 : STD_LOGIC; + signal SyncBaseOvf_n_3 : STD_LOGIC; + signal SyncBaseOvf_n_4 : STD_LOGIC; + signal pAlignErr_q : STD_LOGIC; + signal \pAlignRst_i_1__0_n_0\ : STD_LOGIC; + signal pAlignRst_reg_n_0 : STD_LOGIC; + signal pBitslip : STD_LOGIC; + signal pBitslipCnt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \pBitslipCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \pBitslipCnt[1]_i_1_n_0\ : STD_LOGIC; + signal pDataIn : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal pDataInRaw : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal pIDLY_CE : STD_LOGIC; + signal pIDLY_CNT : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal pIDLY_INC : STD_LOGIC; + signal pIDLY_LD : STD_LOGIC; + signal \^pmerdy_int_reg\ : STD_LOGIC; + signal pTimeoutOvf : STD_LOGIC; + signal \rTimeoutCnt[0]_i_1__0_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[0]_i_3__0_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[0]_i_4__0_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[0]_i_5__0_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[0]_i_6__0_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[12]_i_2__0_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[12]_i_3__0_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[12]_i_4__0_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[12]_i_5__0_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[16]_i_2__0_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[16]_i_3__0_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[16]_i_4__0_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[16]_i_5__0_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[20]_i_2__0_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[20]_i_3__0_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[20]_i_4__0_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[20]_i_5__0_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[4]_i_2__0_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[4]_i_3__0_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[4]_i_4__0_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[4]_i_5__0_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[8]_i_2__0_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[8]_i_3__0_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[8]_i_4__0_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[8]_i_5__0_n_0\ : STD_LOGIC; + signal rTimeoutCnt_reg : STD_LOGIC_VECTOR ( 23 downto 0 ); + signal \rTimeoutCnt_reg[0]_i_2__0_n_0\ : STD_LOGIC; + signal \rTimeoutCnt_reg[0]_i_2__0_n_1\ : STD_LOGIC; + signal \rTimeoutCnt_reg[0]_i_2__0_n_2\ : STD_LOGIC; + signal \rTimeoutCnt_reg[0]_i_2__0_n_3\ : STD_LOGIC; + signal \rTimeoutCnt_reg[0]_i_2__0_n_4\ : STD_LOGIC; + signal \rTimeoutCnt_reg[0]_i_2__0_n_5\ : STD_LOGIC; + signal \rTimeoutCnt_reg[0]_i_2__0_n_6\ : STD_LOGIC; + signal \rTimeoutCnt_reg[0]_i_2__0_n_7\ : STD_LOGIC; + signal \rTimeoutCnt_reg[12]_i_1__0_n_0\ : STD_LOGIC; + signal \rTimeoutCnt_reg[12]_i_1__0_n_1\ : STD_LOGIC; + signal \rTimeoutCnt_reg[12]_i_1__0_n_2\ : STD_LOGIC; + signal \rTimeoutCnt_reg[12]_i_1__0_n_3\ : STD_LOGIC; + signal \rTimeoutCnt_reg[12]_i_1__0_n_4\ : STD_LOGIC; + signal \rTimeoutCnt_reg[12]_i_1__0_n_5\ : STD_LOGIC; + signal \rTimeoutCnt_reg[12]_i_1__0_n_6\ : STD_LOGIC; + signal \rTimeoutCnt_reg[12]_i_1__0_n_7\ : STD_LOGIC; + signal \rTimeoutCnt_reg[16]_i_1__0_n_0\ : STD_LOGIC; + signal \rTimeoutCnt_reg[16]_i_1__0_n_1\ : STD_LOGIC; + signal \rTimeoutCnt_reg[16]_i_1__0_n_2\ : STD_LOGIC; + signal \rTimeoutCnt_reg[16]_i_1__0_n_3\ : STD_LOGIC; + signal \rTimeoutCnt_reg[16]_i_1__0_n_4\ : STD_LOGIC; + signal \rTimeoutCnt_reg[16]_i_1__0_n_5\ : STD_LOGIC; + signal \rTimeoutCnt_reg[16]_i_1__0_n_6\ : STD_LOGIC; + signal \rTimeoutCnt_reg[16]_i_1__0_n_7\ : STD_LOGIC; + signal \rTimeoutCnt_reg[20]_i_1__0_n_1\ : STD_LOGIC; + signal \rTimeoutCnt_reg[20]_i_1__0_n_2\ : STD_LOGIC; + signal \rTimeoutCnt_reg[20]_i_1__0_n_3\ : STD_LOGIC; + signal \rTimeoutCnt_reg[20]_i_1__0_n_4\ : STD_LOGIC; + signal \rTimeoutCnt_reg[20]_i_1__0_n_5\ : STD_LOGIC; + signal \rTimeoutCnt_reg[20]_i_1__0_n_6\ : STD_LOGIC; + signal \rTimeoutCnt_reg[20]_i_1__0_n_7\ : STD_LOGIC; + signal \rTimeoutCnt_reg[4]_i_1__0_n_0\ : STD_LOGIC; + signal \rTimeoutCnt_reg[4]_i_1__0_n_1\ : STD_LOGIC; + signal \rTimeoutCnt_reg[4]_i_1__0_n_2\ : STD_LOGIC; + signal \rTimeoutCnt_reg[4]_i_1__0_n_3\ : STD_LOGIC; + signal \rTimeoutCnt_reg[4]_i_1__0_n_4\ : STD_LOGIC; + signal \rTimeoutCnt_reg[4]_i_1__0_n_5\ : STD_LOGIC; + signal \rTimeoutCnt_reg[4]_i_1__0_n_6\ : STD_LOGIC; + signal \rTimeoutCnt_reg[4]_i_1__0_n_7\ : STD_LOGIC; + signal \rTimeoutCnt_reg[8]_i_1__0_n_0\ : STD_LOGIC; + signal \rTimeoutCnt_reg[8]_i_1__0_n_1\ : STD_LOGIC; + signal \rTimeoutCnt_reg[8]_i_1__0_n_2\ : STD_LOGIC; + signal \rTimeoutCnt_reg[8]_i_1__0_n_3\ : STD_LOGIC; + signal \rTimeoutCnt_reg[8]_i_1__0_n_4\ : STD_LOGIC; + signal \rTimeoutCnt_reg[8]_i_1__0_n_5\ : STD_LOGIC; + signal \rTimeoutCnt_reg[8]_i_1__0_n_6\ : STD_LOGIC; + signal \rTimeoutCnt_reg[8]_i_1__0_n_7\ : STD_LOGIC; + signal rTimeoutRst : STD_LOGIC; + signal \NLW_rTimeoutCnt_reg[20]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \pBitslipCnt[0]_i_1\ : label is "soft_lutpair52"; + attribute SOFT_HLUTNM of \pBitslipCnt[1]_i_1\ : label is "soft_lutpair52"; +begin + pMeRdy_int_reg <= \^pmerdy_int_reg\; +ChannelBondX: entity work.Arty_Z7_20_dvi2rgb_0_0_ChannelBond_10 + port map ( + D(7 downto 0) => pDataIn(7 downto 0), + PixelClk_int => PixelClk_int, + SR(0) => \^pmerdy_int_reg\, + pAllVld => pAllVld, + pAllVldBgnFlag => pAllVldBgnFlag, + pDataInRaw(9 downto 0) => pDataInRaw(9 downto 0), + \pDataIn_reg[7]\(0) => SR(0), + pMeRdy_int_reg_0 => pRdy_1, + pRdy_0 => pRdy_0, + pRdy_2 => pRdy_2 + ); +InputSERDES_X: entity work.Arty_Z7_20_dvi2rgb_0_0_InputSERDES_11 + port map ( + AS(0) => AS(0), + CLKB => CLKB, + D(4 downto 0) => pIDLY_CNT(4 downto 0), + PixelClk_int => PixelClk_int, + TMDS_Data_n(0) => TMDS_Data_n(0), + TMDS_Data_p(0) => TMDS_Data_p(0), + pBitslip => pBitslip, + pDataInRaw(9 downto 0) => pDataInRaw(9 downto 0), + pIDLY_CE => pIDLY_CE, + pIDLY_INC => pIDLY_INC, + pIDLY_LD => pIDLY_LD, + \rMMCM_Reset_q_reg[0]\ => \rMMCM_Reset_q_reg[0]\ + ); +PhaseAlignX: entity work.Arty_Z7_20_dvi2rgb_0_0_PhaseAlign_12 + port map ( + D(8 downto 0) => pDataInRaw(8 downto 0), + PixelClk_int => PixelClk_int, + SS(0) => pAlignRst_reg_n_0, + iIn_q_reg => PhaseAlignX_n_5, + \out\(0) => pTimeoutOvf, + pAlignErr_q => pAlignErr_q, + pAlignErr_q_reg => PhaseAlignX_n_4, + pBitslip_reg => PhaseAlignX_n_7, + pIDLY_CE => pIDLY_CE, + pIDLY_CE_reg_0(4 downto 0) => pIDLY_CNT(4 downto 0), + pIDLY_INC => pIDLY_INC, + pIDLY_LD => pIDLY_LD, + pMeRdy_int_reg => \^pmerdy_int_reg\, + pVld_0 => pVld_0, + pVld_1 => pVld_1, + pVld_2 => pVld_2 + ); +SyncBaseOvf: entity work.Arty_Z7_20_dvi2rgb_0_0_SyncBase_13 + port map ( + AS(0) => AS(0), + PixelClk_int => PixelClk_int, + RefClk => RefClk, + iIn_q_reg_0 => SyncBaseOvf_n_1, + iIn_q_reg_1 => SyncBaseOvf_n_2, + iIn_q_reg_2 => SyncBaseOvf_n_3, + iIn_q_reg_3 => SyncBaseOvf_n_4, + \out\(0) => pTimeoutOvf, + rTimeoutCnt_reg(23 downto 0) => rTimeoutCnt_reg(23 downto 0) + ); +SyncBaseRst: entity work.\Arty_Z7_20_dvi2rgb_0_0_SyncBase__parameterized0_14\ + port map ( + AS(0) => AS(0), + PixelClk_int => PixelClk_int, + RefClk => RefClk, + \out\(0) => rTimeoutRst, + \pState_reg[1]\ => PhaseAlignX_n_5 + ); +pAlignErr_q_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => PhaseAlignX_n_4, + Q => pAlignErr_q, + R => '0' + ); +\pAlignRst_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFDDDDD" + ) + port map ( + I0 => pRst_n, + I1 => pBitslip, + I2 => pBitslipCnt(1), + I3 => pBitslipCnt(0), + I4 => pAlignRst_reg_n_0, + O => \pAlignRst_i_1__0_n_0\ + ); +pAlignRst_reg: unisim.vcomponents.FDPE + port map ( + C => PixelClk_int, + CE => '1', + D => \pAlignRst_i_1__0_n_0\, + PRE => AS(0), + Q => pAlignRst_reg_n_0 + ); +\pBitslipCnt[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => pBitslipCnt(0), + I1 => pBitslipCnt(1), + I2 => pBitslip, + O => \pBitslipCnt[0]_i_1_n_0\ + ); +\pBitslipCnt[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"F8" + ) + port map ( + I0 => pBitslipCnt(0), + I1 => pBitslipCnt(1), + I2 => pBitslip, + O => \pBitslipCnt[1]_i_1_n_0\ + ); +\pBitslipCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => PixelClk_int, + CE => '1', + D => \pBitslipCnt[0]_i_1_n_0\, + Q => pBitslipCnt(0), + R => '0' + ); +\pBitslipCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => PixelClk_int, + CE => '1', + D => \pBitslipCnt[1]_i_1_n_0\, + Q => pBitslipCnt(1), + R => '0' + ); +pBitslip_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => PhaseAlignX_n_7, + Q => pBitslip, + R => '0' + ); +\pDataIn_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pDataIn(0), + Q => Q(0), + R => pMeRdy_int_reg_0(0) + ); +\pDataIn_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pDataIn(1), + Q => Q(1), + R => pMeRdy_int_reg_0(0) + ); +\pDataIn_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pDataIn(2), + Q => Q(2), + R => pMeRdy_int_reg_0(0) + ); +\pDataIn_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pDataIn(3), + Q => Q(3), + R => pMeRdy_int_reg_0(0) + ); +\pDataIn_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pDataIn(4), + Q => Q(4), + R => pMeRdy_int_reg_0(0) + ); +\pDataIn_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pDataIn(5), + Q => Q(5), + R => pMeRdy_int_reg_0(0) + ); +\pDataIn_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pDataIn(6), + Q => Q(6), + R => pMeRdy_int_reg_0(0) + ); +\pDataIn_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pDataIn(7), + Q => Q(7), + R => pMeRdy_int_reg_0(0) + ); +\rTimeoutCnt[0]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BFFF" + ) + port map ( + I0 => SyncBaseOvf_n_1, + I1 => SyncBaseOvf_n_2, + I2 => SyncBaseOvf_n_3, + I3 => SyncBaseOvf_n_4, + O => \rTimeoutCnt[0]_i_1__0_n_0\ + ); +\rTimeoutCnt[0]_i_3__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(3), + O => \rTimeoutCnt[0]_i_3__0_n_0\ + ); +\rTimeoutCnt[0]_i_4__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(2), + O => \rTimeoutCnt[0]_i_4__0_n_0\ + ); +\rTimeoutCnt[0]_i_5__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(1), + O => \rTimeoutCnt[0]_i_5__0_n_0\ + ); +\rTimeoutCnt[0]_i_6__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => rTimeoutCnt_reg(0), + O => \rTimeoutCnt[0]_i_6__0_n_0\ + ); +\rTimeoutCnt[12]_i_2__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(15), + O => \rTimeoutCnt[12]_i_2__0_n_0\ + ); +\rTimeoutCnt[12]_i_3__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(14), + O => \rTimeoutCnt[12]_i_3__0_n_0\ + ); +\rTimeoutCnt[12]_i_4__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(13), + O => \rTimeoutCnt[12]_i_4__0_n_0\ + ); +\rTimeoutCnt[12]_i_5__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(12), + O => \rTimeoutCnt[12]_i_5__0_n_0\ + ); +\rTimeoutCnt[16]_i_2__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(19), + O => \rTimeoutCnt[16]_i_2__0_n_0\ + ); +\rTimeoutCnt[16]_i_3__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(18), + O => \rTimeoutCnt[16]_i_3__0_n_0\ + ); +\rTimeoutCnt[16]_i_4__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(17), + O => \rTimeoutCnt[16]_i_4__0_n_0\ + ); +\rTimeoutCnt[16]_i_5__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(16), + O => \rTimeoutCnt[16]_i_5__0_n_0\ + ); +\rTimeoutCnt[20]_i_2__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(23), + O => \rTimeoutCnt[20]_i_2__0_n_0\ + ); +\rTimeoutCnt[20]_i_3__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(22), + O => \rTimeoutCnt[20]_i_3__0_n_0\ + ); +\rTimeoutCnt[20]_i_4__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(21), + O => \rTimeoutCnt[20]_i_4__0_n_0\ + ); +\rTimeoutCnt[20]_i_5__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(20), + O => \rTimeoutCnt[20]_i_5__0_n_0\ + ); +\rTimeoutCnt[4]_i_2__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(7), + O => \rTimeoutCnt[4]_i_2__0_n_0\ + ); +\rTimeoutCnt[4]_i_3__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(6), + O => \rTimeoutCnt[4]_i_3__0_n_0\ + ); +\rTimeoutCnt[4]_i_4__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(5), + O => \rTimeoutCnt[4]_i_4__0_n_0\ + ); +\rTimeoutCnt[4]_i_5__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(4), + O => \rTimeoutCnt[4]_i_5__0_n_0\ + ); +\rTimeoutCnt[8]_i_2__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(11), + O => \rTimeoutCnt[8]_i_2__0_n_0\ + ); +\rTimeoutCnt[8]_i_3__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(10), + O => \rTimeoutCnt[8]_i_3__0_n_0\ + ); +\rTimeoutCnt[8]_i_4__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(9), + O => \rTimeoutCnt[8]_i_4__0_n_0\ + ); +\rTimeoutCnt[8]_i_5__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(8), + O => \rTimeoutCnt[8]_i_5__0_n_0\ + ); +\rTimeoutCnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__0_n_0\, + D => \rTimeoutCnt_reg[0]_i_2__0_n_7\, + Q => rTimeoutCnt_reg(0), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[0]_i_2__0\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \rTimeoutCnt_reg[0]_i_2__0_n_0\, + CO(2) => \rTimeoutCnt_reg[0]_i_2__0_n_1\, + CO(1) => \rTimeoutCnt_reg[0]_i_2__0_n_2\, + CO(0) => \rTimeoutCnt_reg[0]_i_2__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \rTimeoutCnt_reg[0]_i_2__0_n_4\, + O(2) => \rTimeoutCnt_reg[0]_i_2__0_n_5\, + O(1) => \rTimeoutCnt_reg[0]_i_2__0_n_6\, + O(0) => \rTimeoutCnt_reg[0]_i_2__0_n_7\, + S(3) => \rTimeoutCnt[0]_i_3__0_n_0\, + S(2) => \rTimeoutCnt[0]_i_4__0_n_0\, + S(1) => \rTimeoutCnt[0]_i_5__0_n_0\, + S(0) => \rTimeoutCnt[0]_i_6__0_n_0\ + ); +\rTimeoutCnt_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__0_n_0\, + D => \rTimeoutCnt_reg[8]_i_1__0_n_5\, + Q => rTimeoutCnt_reg(10), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__0_n_0\, + D => \rTimeoutCnt_reg[8]_i_1__0_n_4\, + Q => rTimeoutCnt_reg(11), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__0_n_0\, + D => \rTimeoutCnt_reg[12]_i_1__0_n_7\, + Q => rTimeoutCnt_reg(12), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[12]_i_1__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \rTimeoutCnt_reg[8]_i_1__0_n_0\, + CO(3) => \rTimeoutCnt_reg[12]_i_1__0_n_0\, + CO(2) => \rTimeoutCnt_reg[12]_i_1__0_n_1\, + CO(1) => \rTimeoutCnt_reg[12]_i_1__0_n_2\, + CO(0) => \rTimeoutCnt_reg[12]_i_1__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \rTimeoutCnt_reg[12]_i_1__0_n_4\, + O(2) => \rTimeoutCnt_reg[12]_i_1__0_n_5\, + O(1) => \rTimeoutCnt_reg[12]_i_1__0_n_6\, + O(0) => \rTimeoutCnt_reg[12]_i_1__0_n_7\, + S(3) => \rTimeoutCnt[12]_i_2__0_n_0\, + S(2) => \rTimeoutCnt[12]_i_3__0_n_0\, + S(1) => \rTimeoutCnt[12]_i_4__0_n_0\, + S(0) => \rTimeoutCnt[12]_i_5__0_n_0\ + ); +\rTimeoutCnt_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__0_n_0\, + D => \rTimeoutCnt_reg[12]_i_1__0_n_6\, + Q => rTimeoutCnt_reg(13), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__0_n_0\, + D => \rTimeoutCnt_reg[12]_i_1__0_n_5\, + Q => rTimeoutCnt_reg(14), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__0_n_0\, + D => \rTimeoutCnt_reg[12]_i_1__0_n_4\, + Q => rTimeoutCnt_reg(15), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__0_n_0\, + D => \rTimeoutCnt_reg[16]_i_1__0_n_7\, + Q => rTimeoutCnt_reg(16), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[16]_i_1__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \rTimeoutCnt_reg[12]_i_1__0_n_0\, + CO(3) => \rTimeoutCnt_reg[16]_i_1__0_n_0\, + CO(2) => \rTimeoutCnt_reg[16]_i_1__0_n_1\, + CO(1) => \rTimeoutCnt_reg[16]_i_1__0_n_2\, + CO(0) => \rTimeoutCnt_reg[16]_i_1__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \rTimeoutCnt_reg[16]_i_1__0_n_4\, + O(2) => \rTimeoutCnt_reg[16]_i_1__0_n_5\, + O(1) => \rTimeoutCnt_reg[16]_i_1__0_n_6\, + O(0) => \rTimeoutCnt_reg[16]_i_1__0_n_7\, + S(3) => \rTimeoutCnt[16]_i_2__0_n_0\, + S(2) => \rTimeoutCnt[16]_i_3__0_n_0\, + S(1) => \rTimeoutCnt[16]_i_4__0_n_0\, + S(0) => \rTimeoutCnt[16]_i_5__0_n_0\ + ); +\rTimeoutCnt_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__0_n_0\, + D => \rTimeoutCnt_reg[16]_i_1__0_n_6\, + Q => rTimeoutCnt_reg(17), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__0_n_0\, + D => \rTimeoutCnt_reg[16]_i_1__0_n_5\, + Q => rTimeoutCnt_reg(18), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__0_n_0\, + D => \rTimeoutCnt_reg[16]_i_1__0_n_4\, + Q => rTimeoutCnt_reg(19), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__0_n_0\, + D => \rTimeoutCnt_reg[0]_i_2__0_n_6\, + Q => rTimeoutCnt_reg(1), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__0_n_0\, + D => \rTimeoutCnt_reg[20]_i_1__0_n_7\, + Q => rTimeoutCnt_reg(20), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[20]_i_1__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \rTimeoutCnt_reg[16]_i_1__0_n_0\, + CO(3) => \NLW_rTimeoutCnt_reg[20]_i_1__0_CO_UNCONNECTED\(3), + CO(2) => \rTimeoutCnt_reg[20]_i_1__0_n_1\, + CO(1) => \rTimeoutCnt_reg[20]_i_1__0_n_2\, + CO(0) => \rTimeoutCnt_reg[20]_i_1__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \rTimeoutCnt_reg[20]_i_1__0_n_4\, + O(2) => \rTimeoutCnt_reg[20]_i_1__0_n_5\, + O(1) => \rTimeoutCnt_reg[20]_i_1__0_n_6\, + O(0) => \rTimeoutCnt_reg[20]_i_1__0_n_7\, + S(3) => \rTimeoutCnt[20]_i_2__0_n_0\, + S(2) => \rTimeoutCnt[20]_i_3__0_n_0\, + S(1) => \rTimeoutCnt[20]_i_4__0_n_0\, + S(0) => \rTimeoutCnt[20]_i_5__0_n_0\ + ); +\rTimeoutCnt_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__0_n_0\, + D => \rTimeoutCnt_reg[20]_i_1__0_n_6\, + Q => rTimeoutCnt_reg(21), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__0_n_0\, + D => \rTimeoutCnt_reg[20]_i_1__0_n_5\, + Q => rTimeoutCnt_reg(22), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__0_n_0\, + D => \rTimeoutCnt_reg[20]_i_1__0_n_4\, + Q => rTimeoutCnt_reg(23), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__0_n_0\, + D => \rTimeoutCnt_reg[0]_i_2__0_n_5\, + Q => rTimeoutCnt_reg(2), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__0_n_0\, + D => \rTimeoutCnt_reg[0]_i_2__0_n_4\, + Q => rTimeoutCnt_reg(3), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__0_n_0\, + D => \rTimeoutCnt_reg[4]_i_1__0_n_7\, + Q => rTimeoutCnt_reg(4), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[4]_i_1__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \rTimeoutCnt_reg[0]_i_2__0_n_0\, + CO(3) => \rTimeoutCnt_reg[4]_i_1__0_n_0\, + CO(2) => \rTimeoutCnt_reg[4]_i_1__0_n_1\, + CO(1) => \rTimeoutCnt_reg[4]_i_1__0_n_2\, + CO(0) => \rTimeoutCnt_reg[4]_i_1__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \rTimeoutCnt_reg[4]_i_1__0_n_4\, + O(2) => \rTimeoutCnt_reg[4]_i_1__0_n_5\, + O(1) => \rTimeoutCnt_reg[4]_i_1__0_n_6\, + O(0) => \rTimeoutCnt_reg[4]_i_1__0_n_7\, + S(3) => \rTimeoutCnt[4]_i_2__0_n_0\, + S(2) => \rTimeoutCnt[4]_i_3__0_n_0\, + S(1) => \rTimeoutCnt[4]_i_4__0_n_0\, + S(0) => \rTimeoutCnt[4]_i_5__0_n_0\ + ); +\rTimeoutCnt_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__0_n_0\, + D => \rTimeoutCnt_reg[4]_i_1__0_n_6\, + Q => rTimeoutCnt_reg(5), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__0_n_0\, + D => \rTimeoutCnt_reg[4]_i_1__0_n_5\, + Q => rTimeoutCnt_reg(6), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__0_n_0\, + D => \rTimeoutCnt_reg[4]_i_1__0_n_4\, + Q => rTimeoutCnt_reg(7), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__0_n_0\, + D => \rTimeoutCnt_reg[8]_i_1__0_n_7\, + Q => rTimeoutCnt_reg(8), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[8]_i_1__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \rTimeoutCnt_reg[4]_i_1__0_n_0\, + CO(3) => \rTimeoutCnt_reg[8]_i_1__0_n_0\, + CO(2) => \rTimeoutCnt_reg[8]_i_1__0_n_1\, + CO(1) => \rTimeoutCnt_reg[8]_i_1__0_n_2\, + CO(0) => \rTimeoutCnt_reg[8]_i_1__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \rTimeoutCnt_reg[8]_i_1__0_n_4\, + O(2) => \rTimeoutCnt_reg[8]_i_1__0_n_5\, + O(1) => \rTimeoutCnt_reg[8]_i_1__0_n_6\, + O(0) => \rTimeoutCnt_reg[8]_i_1__0_n_7\, + S(3) => \rTimeoutCnt[8]_i_2__0_n_0\, + S(2) => \rTimeoutCnt[8]_i_3__0_n_0\, + S(1) => \rTimeoutCnt[8]_i_4__0_n_0\, + S(0) => \rTimeoutCnt[8]_i_5__0_n_0\ + ); +\rTimeoutCnt_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1__0_n_0\, + D => \rTimeoutCnt_reg[8]_i_1__0_n_6\, + Q => rTimeoutCnt_reg(9), + R => rTimeoutRst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_TMDS_Decoder_1 is + port ( + pAllVldBgnFlag : out STD_LOGIC; + pVld_2 : out STD_LOGIC; + pRdy_2 : out STD_LOGIC; + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + Q : out STD_LOGIC_VECTOR ( 7 downto 0 ); + TMDS_Data_p : in STD_LOGIC_VECTOR ( 0 to 0 ); + TMDS_Data_n : in STD_LOGIC_VECTOR ( 0 to 0 ); + PixelClk_int : in STD_LOGIC; + \rMMCM_Reset_q_reg[0]\ : in STD_LOGIC; + CLKB : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + RefClk : in STD_LOGIC; + pAllVld : in STD_LOGIC; + pAligned_reg : in STD_LOGIC; + pVld_0 : in STD_LOGIC; + pVld_1 : in STD_LOGIC; + pRdy_0 : in STD_LOGIC; + pRdy_1 : in STD_LOGIC; + pRst_n : in STD_LOGIC; + pMeRdy_int_reg : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_TMDS_Decoder_1 : entity is "TMDS_Decoder"; +end Arty_Z7_20_dvi2rgb_0_0_TMDS_Decoder_1; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_TMDS_Decoder_1 is + signal PhaseAlignX_n_4 : STD_LOGIC; + signal PhaseAlignX_n_5 : STD_LOGIC; + signal PhaseAlignX_n_7 : STD_LOGIC; + signal SyncBaseOvf_n_1 : STD_LOGIC; + signal SyncBaseOvf_n_2 : STD_LOGIC; + signal SyncBaseOvf_n_3 : STD_LOGIC; + signal SyncBaseOvf_n_4 : STD_LOGIC; + signal pAlignErr_q : STD_LOGIC; + signal pAlignRst : STD_LOGIC; + signal pAlignRst_i_1_n_0 : STD_LOGIC; + signal pAllVldBgnFlag0 : STD_LOGIC; + signal pAllVld_q : STD_LOGIC; + signal pBitslip : STD_LOGIC; + signal pBitslipCnt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \pBitslipCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \pBitslipCnt[1]_i_1_n_0\ : STD_LOGIC; + signal pDataIn : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal pDataInRaw : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal pIDLY_CE : STD_LOGIC; + signal pIDLY_CNT : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal pIDLY_INC : STD_LOGIC; + signal pIDLY_LD : STD_LOGIC; + signal pTimeoutOvf : STD_LOGIC; + signal \rTimeoutCnt[0]_i_1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[0]_i_3_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[0]_i_4_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[0]_i_5_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[0]_i_6_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[12]_i_2_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[12]_i_3_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[12]_i_4_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[12]_i_5_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[16]_i_2_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[16]_i_3_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[16]_i_4_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[16]_i_5_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[20]_i_2_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[20]_i_3_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[20]_i_4_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[20]_i_5_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[4]_i_2_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[4]_i_3_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[4]_i_4_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[4]_i_5_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[8]_i_2_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[8]_i_3_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[8]_i_4_n_0\ : STD_LOGIC; + signal \rTimeoutCnt[8]_i_5_n_0\ : STD_LOGIC; + signal rTimeoutCnt_reg : STD_LOGIC_VECTOR ( 23 downto 0 ); + signal \rTimeoutCnt_reg[0]_i_2_n_0\ : STD_LOGIC; + signal \rTimeoutCnt_reg[0]_i_2_n_1\ : STD_LOGIC; + signal \rTimeoutCnt_reg[0]_i_2_n_2\ : STD_LOGIC; + signal \rTimeoutCnt_reg[0]_i_2_n_3\ : STD_LOGIC; + signal \rTimeoutCnt_reg[0]_i_2_n_4\ : STD_LOGIC; + signal \rTimeoutCnt_reg[0]_i_2_n_5\ : STD_LOGIC; + signal \rTimeoutCnt_reg[0]_i_2_n_6\ : STD_LOGIC; + signal \rTimeoutCnt_reg[0]_i_2_n_7\ : STD_LOGIC; + signal \rTimeoutCnt_reg[12]_i_1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt_reg[12]_i_1_n_1\ : STD_LOGIC; + signal \rTimeoutCnt_reg[12]_i_1_n_2\ : STD_LOGIC; + signal \rTimeoutCnt_reg[12]_i_1_n_3\ : STD_LOGIC; + signal \rTimeoutCnt_reg[12]_i_1_n_4\ : STD_LOGIC; + signal \rTimeoutCnt_reg[12]_i_1_n_5\ : STD_LOGIC; + signal \rTimeoutCnt_reg[12]_i_1_n_6\ : STD_LOGIC; + signal \rTimeoutCnt_reg[12]_i_1_n_7\ : STD_LOGIC; + signal \rTimeoutCnt_reg[16]_i_1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt_reg[16]_i_1_n_1\ : STD_LOGIC; + signal \rTimeoutCnt_reg[16]_i_1_n_2\ : STD_LOGIC; + signal \rTimeoutCnt_reg[16]_i_1_n_3\ : STD_LOGIC; + signal \rTimeoutCnt_reg[16]_i_1_n_4\ : STD_LOGIC; + signal \rTimeoutCnt_reg[16]_i_1_n_5\ : STD_LOGIC; + signal \rTimeoutCnt_reg[16]_i_1_n_6\ : STD_LOGIC; + signal \rTimeoutCnt_reg[16]_i_1_n_7\ : STD_LOGIC; + signal \rTimeoutCnt_reg[20]_i_1_n_1\ : STD_LOGIC; + signal \rTimeoutCnt_reg[20]_i_1_n_2\ : STD_LOGIC; + signal \rTimeoutCnt_reg[20]_i_1_n_3\ : STD_LOGIC; + signal \rTimeoutCnt_reg[20]_i_1_n_4\ : STD_LOGIC; + signal \rTimeoutCnt_reg[20]_i_1_n_5\ : STD_LOGIC; + signal \rTimeoutCnt_reg[20]_i_1_n_6\ : STD_LOGIC; + signal \rTimeoutCnt_reg[20]_i_1_n_7\ : STD_LOGIC; + signal \rTimeoutCnt_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \rTimeoutCnt_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \rTimeoutCnt_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \rTimeoutCnt_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \rTimeoutCnt_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \rTimeoutCnt_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \rTimeoutCnt_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \rTimeoutCnt_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \rTimeoutCnt_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \rTimeoutCnt_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \rTimeoutCnt_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \rTimeoutCnt_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \rTimeoutCnt_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \rTimeoutCnt_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \rTimeoutCnt_reg[8]_i_1_n_7\ : STD_LOGIC; + signal rTimeoutRst : STD_LOGIC; + signal \NLW_rTimeoutCnt_reg[20]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \pBitslipCnt[0]_i_1\ : label is "soft_lutpair80"; + attribute SOFT_HLUTNM of \pBitslipCnt[1]_i_1\ : label is "soft_lutpair80"; +begin +ChannelBondX: entity work.Arty_Z7_20_dvi2rgb_0_0_ChannelBond + port map ( + D(7 downto 0) => pDataIn(7 downto 0), + PixelClk_int => PixelClk_int, + SR(0) => SR(0), + pAligned_reg => pAligned_reg, + pAllVld => pAllVld, + pAllVldBgnFlag => pAllVldBgnFlag, + pAllVldBgnFlag0 => pAllVldBgnFlag0, + pAllVld_q => pAllVld_q, + pDataInRaw(9 downto 0) => pDataInRaw(9 downto 0), + pMeRdy_int_reg_0 => pRdy_2, + pRdy_0 => pRdy_0, + pRdy_1 => pRdy_1 + ); +InputSERDES_X: entity work.Arty_Z7_20_dvi2rgb_0_0_InputSERDES + port map ( + CLKB => CLKB, + D(4 downto 0) => pIDLY_CNT(4 downto 0), + PixelClk_int => PixelClk_int, + TMDS_Data_n(0) => TMDS_Data_n(0), + TMDS_Data_p(0) => TMDS_Data_p(0), + \out\(0) => \out\(0), + pBitslip => pBitslip, + pDataInRaw(9 downto 0) => pDataInRaw(9 downto 0), + pIDLY_CE => pIDLY_CE, + pIDLY_INC => pIDLY_INC, + pIDLY_LD => pIDLY_LD, + \rMMCM_Reset_q_reg[0]\ => \rMMCM_Reset_q_reg[0]\ + ); +PhaseAlignX: entity work.Arty_Z7_20_dvi2rgb_0_0_PhaseAlign + port map ( + D(8 downto 0) => pDataInRaw(8 downto 0), + PixelClk_int => PixelClk_int, + SR(0) => pAlignRst, + iIn_q_reg => PhaseAlignX_n_5, + \out\(0) => pTimeoutOvf, + pAlignErr_q => pAlignErr_q, + pAlignErr_q_reg => PhaseAlignX_n_4, + pAllVldBgnFlag0 => pAllVldBgnFlag0, + pAllVld_q => pAllVld_q, + pBitslip_reg => PhaseAlignX_n_7, + pIDLY_CE => pIDLY_CE, + pIDLY_CE_reg_0(4 downto 0) => pIDLY_CNT(4 downto 0), + pIDLY_INC => pIDLY_INC, + pIDLY_LD => pIDLY_LD, + pVld_0 => pVld_0, + pVld_1 => pVld_1, + pVld_2 => pVld_2 + ); +SyncBaseOvf: entity work.Arty_Z7_20_dvi2rgb_0_0_SyncBase + port map ( + PixelClk_int => PixelClk_int, + RefClk => RefClk, + iIn_q_reg_0 => SyncBaseOvf_n_1, + iIn_q_reg_1 => SyncBaseOvf_n_2, + iIn_q_reg_2 => SyncBaseOvf_n_3, + iIn_q_reg_3 => SyncBaseOvf_n_4, + \oSyncStages_reg[1]\(0) => \out\(0), + \out\(0) => pTimeoutOvf, + rTimeoutCnt_reg(23 downto 0) => rTimeoutCnt_reg(23 downto 0) + ); +SyncBaseRst: entity work.\Arty_Z7_20_dvi2rgb_0_0_SyncBase__parameterized0\ + port map ( + PixelClk_int => PixelClk_int, + RefClk => RefClk, + \oSyncStages_reg[1]\(0) => \out\(0), + \out\(0) => rTimeoutRst, + \pState_reg[1]\ => PhaseAlignX_n_5 + ); +pAlignErr_q_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => PhaseAlignX_n_4, + Q => pAlignErr_q, + R => '0' + ); +pAlignRst_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFDDDDD" + ) + port map ( + I0 => pRst_n, + I1 => pBitslip, + I2 => pBitslipCnt(1), + I3 => pBitslipCnt(0), + I4 => pAlignRst, + O => pAlignRst_i_1_n_0 + ); +pAlignRst_reg: unisim.vcomponents.FDPE + port map ( + C => PixelClk_int, + CE => '1', + D => pAlignRst_i_1_n_0, + PRE => \out\(0), + Q => pAlignRst + ); +\pBitslipCnt[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => pBitslipCnt(0), + I1 => pBitslipCnt(1), + I2 => pBitslip, + O => \pBitslipCnt[0]_i_1_n_0\ + ); +\pBitslipCnt[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"F8" + ) + port map ( + I0 => pBitslipCnt(0), + I1 => pBitslipCnt(1), + I2 => pBitslip, + O => \pBitslipCnt[1]_i_1_n_0\ + ); +\pBitslipCnt_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => PixelClk_int, + CE => '1', + D => \pBitslipCnt[0]_i_1_n_0\, + Q => pBitslipCnt(0), + R => '0' + ); +\pBitslipCnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => PixelClk_int, + CE => '1', + D => \pBitslipCnt[1]_i_1_n_0\, + Q => pBitslipCnt(1), + R => '0' + ); +pBitslip_reg: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => PhaseAlignX_n_7, + Q => pBitslip, + R => '0' + ); +\pDataIn_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pDataIn(0), + Q => Q(0), + R => pMeRdy_int_reg(0) + ); +\pDataIn_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pDataIn(1), + Q => Q(1), + R => pMeRdy_int_reg(0) + ); +\pDataIn_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pDataIn(2), + Q => Q(2), + R => pMeRdy_int_reg(0) + ); +\pDataIn_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pDataIn(3), + Q => Q(3), + R => pMeRdy_int_reg(0) + ); +\pDataIn_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pDataIn(4), + Q => Q(4), + R => pMeRdy_int_reg(0) + ); +\pDataIn_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pDataIn(5), + Q => Q(5), + R => pMeRdy_int_reg(0) + ); +\pDataIn_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pDataIn(6), + Q => Q(6), + R => pMeRdy_int_reg(0) + ); +\pDataIn_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => PixelClk_int, + CE => '1', + D => pDataIn(7), + Q => Q(7), + R => pMeRdy_int_reg(0) + ); +\rTimeoutCnt[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BFFF" + ) + port map ( + I0 => SyncBaseOvf_n_1, + I1 => SyncBaseOvf_n_2, + I2 => SyncBaseOvf_n_3, + I3 => SyncBaseOvf_n_4, + O => \rTimeoutCnt[0]_i_1_n_0\ + ); +\rTimeoutCnt[0]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(3), + O => \rTimeoutCnt[0]_i_3_n_0\ + ); +\rTimeoutCnt[0]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(2), + O => \rTimeoutCnt[0]_i_4_n_0\ + ); +\rTimeoutCnt[0]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(1), + O => \rTimeoutCnt[0]_i_5_n_0\ + ); +\rTimeoutCnt[0]_i_6\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => rTimeoutCnt_reg(0), + O => \rTimeoutCnt[0]_i_6_n_0\ + ); +\rTimeoutCnt[12]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(15), + O => \rTimeoutCnt[12]_i_2_n_0\ + ); +\rTimeoutCnt[12]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(14), + O => \rTimeoutCnt[12]_i_3_n_0\ + ); +\rTimeoutCnt[12]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(13), + O => \rTimeoutCnt[12]_i_4_n_0\ + ); +\rTimeoutCnt[12]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(12), + O => \rTimeoutCnt[12]_i_5_n_0\ + ); +\rTimeoutCnt[16]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(19), + O => \rTimeoutCnt[16]_i_2_n_0\ + ); +\rTimeoutCnt[16]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(18), + O => \rTimeoutCnt[16]_i_3_n_0\ + ); +\rTimeoutCnt[16]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(17), + O => \rTimeoutCnt[16]_i_4_n_0\ + ); +\rTimeoutCnt[16]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(16), + O => \rTimeoutCnt[16]_i_5_n_0\ + ); +\rTimeoutCnt[20]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(23), + O => \rTimeoutCnt[20]_i_2_n_0\ + ); +\rTimeoutCnt[20]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(22), + O => \rTimeoutCnt[20]_i_3_n_0\ + ); +\rTimeoutCnt[20]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(21), + O => \rTimeoutCnt[20]_i_4_n_0\ + ); +\rTimeoutCnt[20]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(20), + O => \rTimeoutCnt[20]_i_5_n_0\ + ); +\rTimeoutCnt[4]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(7), + O => \rTimeoutCnt[4]_i_2_n_0\ + ); +\rTimeoutCnt[4]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(6), + O => \rTimeoutCnt[4]_i_3_n_0\ + ); +\rTimeoutCnt[4]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(5), + O => \rTimeoutCnt[4]_i_4_n_0\ + ); +\rTimeoutCnt[4]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(4), + O => \rTimeoutCnt[4]_i_5_n_0\ + ); +\rTimeoutCnt[8]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(11), + O => \rTimeoutCnt[8]_i_2_n_0\ + ); +\rTimeoutCnt[8]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(10), + O => \rTimeoutCnt[8]_i_3_n_0\ + ); +\rTimeoutCnt[8]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(9), + O => \rTimeoutCnt[8]_i_4_n_0\ + ); +\rTimeoutCnt[8]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => rTimeoutCnt_reg(8), + O => \rTimeoutCnt[8]_i_5_n_0\ + ); +\rTimeoutCnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1_n_0\, + D => \rTimeoutCnt_reg[0]_i_2_n_7\, + Q => rTimeoutCnt_reg(0), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[0]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \rTimeoutCnt_reg[0]_i_2_n_0\, + CO(2) => \rTimeoutCnt_reg[0]_i_2_n_1\, + CO(1) => \rTimeoutCnt_reg[0]_i_2_n_2\, + CO(0) => \rTimeoutCnt_reg[0]_i_2_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \rTimeoutCnt_reg[0]_i_2_n_4\, + O(2) => \rTimeoutCnt_reg[0]_i_2_n_5\, + O(1) => \rTimeoutCnt_reg[0]_i_2_n_6\, + O(0) => \rTimeoutCnt_reg[0]_i_2_n_7\, + S(3) => \rTimeoutCnt[0]_i_3_n_0\, + S(2) => \rTimeoutCnt[0]_i_4_n_0\, + S(1) => \rTimeoutCnt[0]_i_5_n_0\, + S(0) => \rTimeoutCnt[0]_i_6_n_0\ + ); +\rTimeoutCnt_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1_n_0\, + D => \rTimeoutCnt_reg[8]_i_1_n_5\, + Q => rTimeoutCnt_reg(10), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1_n_0\, + D => \rTimeoutCnt_reg[8]_i_1_n_4\, + Q => rTimeoutCnt_reg(11), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1_n_0\, + D => \rTimeoutCnt_reg[12]_i_1_n_7\, + Q => rTimeoutCnt_reg(12), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \rTimeoutCnt_reg[8]_i_1_n_0\, + CO(3) => \rTimeoutCnt_reg[12]_i_1_n_0\, + CO(2) => \rTimeoutCnt_reg[12]_i_1_n_1\, + CO(1) => \rTimeoutCnt_reg[12]_i_1_n_2\, + CO(0) => \rTimeoutCnt_reg[12]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \rTimeoutCnt_reg[12]_i_1_n_4\, + O(2) => \rTimeoutCnt_reg[12]_i_1_n_5\, + O(1) => \rTimeoutCnt_reg[12]_i_1_n_6\, + O(0) => \rTimeoutCnt_reg[12]_i_1_n_7\, + S(3) => \rTimeoutCnt[12]_i_2_n_0\, + S(2) => \rTimeoutCnt[12]_i_3_n_0\, + S(1) => \rTimeoutCnt[12]_i_4_n_0\, + S(0) => \rTimeoutCnt[12]_i_5_n_0\ + ); +\rTimeoutCnt_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1_n_0\, + D => \rTimeoutCnt_reg[12]_i_1_n_6\, + Q => rTimeoutCnt_reg(13), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1_n_0\, + D => \rTimeoutCnt_reg[12]_i_1_n_5\, + Q => rTimeoutCnt_reg(14), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1_n_0\, + D => \rTimeoutCnt_reg[12]_i_1_n_4\, + Q => rTimeoutCnt_reg(15), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1_n_0\, + D => \rTimeoutCnt_reg[16]_i_1_n_7\, + Q => rTimeoutCnt_reg(16), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[16]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \rTimeoutCnt_reg[12]_i_1_n_0\, + CO(3) => \rTimeoutCnt_reg[16]_i_1_n_0\, + CO(2) => \rTimeoutCnt_reg[16]_i_1_n_1\, + CO(1) => \rTimeoutCnt_reg[16]_i_1_n_2\, + CO(0) => \rTimeoutCnt_reg[16]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \rTimeoutCnt_reg[16]_i_1_n_4\, + O(2) => \rTimeoutCnt_reg[16]_i_1_n_5\, + O(1) => \rTimeoutCnt_reg[16]_i_1_n_6\, + O(0) => \rTimeoutCnt_reg[16]_i_1_n_7\, + S(3) => \rTimeoutCnt[16]_i_2_n_0\, + S(2) => \rTimeoutCnt[16]_i_3_n_0\, + S(1) => \rTimeoutCnt[16]_i_4_n_0\, + S(0) => \rTimeoutCnt[16]_i_5_n_0\ + ); +\rTimeoutCnt_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1_n_0\, + D => \rTimeoutCnt_reg[16]_i_1_n_6\, + Q => rTimeoutCnt_reg(17), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1_n_0\, + D => \rTimeoutCnt_reg[16]_i_1_n_5\, + Q => rTimeoutCnt_reg(18), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1_n_0\, + D => \rTimeoutCnt_reg[16]_i_1_n_4\, + Q => rTimeoutCnt_reg(19), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1_n_0\, + D => \rTimeoutCnt_reg[0]_i_2_n_6\, + Q => rTimeoutCnt_reg(1), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1_n_0\, + D => \rTimeoutCnt_reg[20]_i_1_n_7\, + Q => rTimeoutCnt_reg(20), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[20]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \rTimeoutCnt_reg[16]_i_1_n_0\, + CO(3) => \NLW_rTimeoutCnt_reg[20]_i_1_CO_UNCONNECTED\(3), + CO(2) => \rTimeoutCnt_reg[20]_i_1_n_1\, + CO(1) => \rTimeoutCnt_reg[20]_i_1_n_2\, + CO(0) => \rTimeoutCnt_reg[20]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \rTimeoutCnt_reg[20]_i_1_n_4\, + O(2) => \rTimeoutCnt_reg[20]_i_1_n_5\, + O(1) => \rTimeoutCnt_reg[20]_i_1_n_6\, + O(0) => \rTimeoutCnt_reg[20]_i_1_n_7\, + S(3) => \rTimeoutCnt[20]_i_2_n_0\, + S(2) => \rTimeoutCnt[20]_i_3_n_0\, + S(1) => \rTimeoutCnt[20]_i_4_n_0\, + S(0) => \rTimeoutCnt[20]_i_5_n_0\ + ); +\rTimeoutCnt_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1_n_0\, + D => \rTimeoutCnt_reg[20]_i_1_n_6\, + Q => rTimeoutCnt_reg(21), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1_n_0\, + D => \rTimeoutCnt_reg[20]_i_1_n_5\, + Q => rTimeoutCnt_reg(22), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1_n_0\, + D => \rTimeoutCnt_reg[20]_i_1_n_4\, + Q => rTimeoutCnt_reg(23), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1_n_0\, + D => \rTimeoutCnt_reg[0]_i_2_n_5\, + Q => rTimeoutCnt_reg(2), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1_n_0\, + D => \rTimeoutCnt_reg[0]_i_2_n_4\, + Q => rTimeoutCnt_reg(3), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1_n_0\, + D => \rTimeoutCnt_reg[4]_i_1_n_7\, + Q => rTimeoutCnt_reg(4), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \rTimeoutCnt_reg[0]_i_2_n_0\, + CO(3) => \rTimeoutCnt_reg[4]_i_1_n_0\, + CO(2) => \rTimeoutCnt_reg[4]_i_1_n_1\, + CO(1) => \rTimeoutCnt_reg[4]_i_1_n_2\, + CO(0) => \rTimeoutCnt_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \rTimeoutCnt_reg[4]_i_1_n_4\, + O(2) => \rTimeoutCnt_reg[4]_i_1_n_5\, + O(1) => \rTimeoutCnt_reg[4]_i_1_n_6\, + O(0) => \rTimeoutCnt_reg[4]_i_1_n_7\, + S(3) => \rTimeoutCnt[4]_i_2_n_0\, + S(2) => \rTimeoutCnt[4]_i_3_n_0\, + S(1) => \rTimeoutCnt[4]_i_4_n_0\, + S(0) => \rTimeoutCnt[4]_i_5_n_0\ + ); +\rTimeoutCnt_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1_n_0\, + D => \rTimeoutCnt_reg[4]_i_1_n_6\, + Q => rTimeoutCnt_reg(5), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1_n_0\, + D => \rTimeoutCnt_reg[4]_i_1_n_5\, + Q => rTimeoutCnt_reg(6), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1_n_0\, + D => \rTimeoutCnt_reg[4]_i_1_n_4\, + Q => rTimeoutCnt_reg(7), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1_n_0\, + D => \rTimeoutCnt_reg[8]_i_1_n_7\, + Q => rTimeoutCnt_reg(8), + R => rTimeoutRst + ); +\rTimeoutCnt_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \rTimeoutCnt_reg[4]_i_1_n_0\, + CO(3) => \rTimeoutCnt_reg[8]_i_1_n_0\, + CO(2) => \rTimeoutCnt_reg[8]_i_1_n_1\, + CO(1) => \rTimeoutCnt_reg[8]_i_1_n_2\, + CO(0) => \rTimeoutCnt_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \rTimeoutCnt_reg[8]_i_1_n_4\, + O(2) => \rTimeoutCnt_reg[8]_i_1_n_5\, + O(1) => \rTimeoutCnt_reg[8]_i_1_n_6\, + O(0) => \rTimeoutCnt_reg[8]_i_1_n_7\, + S(3) => \rTimeoutCnt[8]_i_2_n_0\, + S(2) => \rTimeoutCnt[8]_i_3_n_0\, + S(1) => \rTimeoutCnt[8]_i_4_n_0\, + S(0) => \rTimeoutCnt[8]_i_5_n_0\ + ); +\rTimeoutCnt_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => RefClk, + CE => \rTimeoutCnt[0]_i_1_n_0\, + D => \rTimeoutCnt_reg[8]_i_1_n_6\, + Q => rTimeoutCnt_reg(9), + R => rTimeoutRst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0_dvi2rgb is + port ( + TMDS_Clk_p : in STD_LOGIC; + TMDS_Clk_n : in STD_LOGIC; + TMDS_Data_p : in STD_LOGIC_VECTOR ( 2 downto 0 ); + TMDS_Data_n : in STD_LOGIC_VECTOR ( 2 downto 0 ); + RefClk : in STD_LOGIC; + aRst : in STD_LOGIC; + aRst_n : in STD_LOGIC; + vid_pData : out STD_LOGIC_VECTOR ( 23 downto 0 ); + vid_pVDE : out STD_LOGIC; + vid_pHSync : out STD_LOGIC; + vid_pVSync : out STD_LOGIC; + PixelClk : out STD_LOGIC; + SerialClk : out STD_LOGIC; + aPixelClkLckd : out STD_LOGIC; + DDC_SDA_I : in STD_LOGIC; + DDC_SDA_O : out STD_LOGIC; + DDC_SDA_T : out STD_LOGIC; + DDC_SCL_I : in STD_LOGIC; + DDC_SCL_O : out STD_LOGIC; + DDC_SCL_T : out STD_LOGIC; + pRst : in STD_LOGIC; + pRst_n : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_dvi2rgb_0_0_dvi2rgb : entity is "dvi2rgb"; + attribute kAddBUFG : string; + attribute kAddBUFG of Arty_Z7_20_dvi2rgb_0_0_dvi2rgb : entity is "TRUE"; + attribute kClkRange : integer; + attribute kClkRange of Arty_Z7_20_dvi2rgb_0_0_dvi2rgb : entity is 2; + attribute kEdidFileName : string; + attribute kEdidFileName of Arty_Z7_20_dvi2rgb_0_0_dvi2rgb : entity is "720p_edid.data"; + attribute kEmulateDDC : string; + attribute kEmulateDDC of Arty_Z7_20_dvi2rgb_0_0_dvi2rgb : entity is "TRUE"; + attribute kIDLY_TapValuePs : integer; + attribute kIDLY_TapValuePs of Arty_Z7_20_dvi2rgb_0_0_dvi2rgb : entity is 78; + attribute kIDLY_TapWidth : integer; + attribute kIDLY_TapWidth of Arty_Z7_20_dvi2rgb_0_0_dvi2rgb : entity is 5; + attribute kRstActiveHigh : string; + attribute kRstActiveHigh of Arty_Z7_20_dvi2rgb_0_0_dvi2rgb : entity is "FALSE"; +end Arty_Z7_20_dvi2rgb_0_0_dvi2rgb; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0_dvi2rgb is + signal \\ : STD_LOGIC; + signal \\ : STD_LOGIC; + signal \ChannelBondX/pAllVldBgnFlag\ : STD_LOGIC; + signal \DataDecoders[0].DecoderX_n_6\ : STD_LOGIC; + signal \DataDecoders[1].DecoderX_n_0\ : STD_LOGIC; + signal \DataDecoders[1].DecoderX_n_3\ : STD_LOGIC; + signal \DataDecoders[2].DecoderX_n_3\ : STD_LOGIC; + signal PixelClk_int : STD_LOGIC; + signal \^serialclk\ : STD_LOGIC; + signal TMDS_ClockingX_n_3 : STD_LOGIC; + signal pAllVld : STD_LOGIC; + signal pC0 : STD_LOGIC; + signal pC1 : STD_LOGIC; + signal pDataIn : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal pLockLostRst : STD_LOGIC; + signal pRdy_0 : STD_LOGIC; + signal pRdy_1 : STD_LOGIC; + signal pRdy_2 : STD_LOGIC; + signal pVde : STD_LOGIC; + signal pVld_0 : STD_LOGIC; + signal pVld_1 : STD_LOGIC; + signal pVld_2 : STD_LOGIC; + signal piData : STD_LOGIC_VECTOR ( 15 downto 0 ); +begin + DDC_SCL_O <= \\; + DDC_SCL_T <= \\; + DDC_SDA_O <= \\; + SerialClk <= \^serialclk\; +\DataDecoders[0].DecoderX\: entity work.Arty_Z7_20_dvi2rgb_0_0_TMDS_Decoder + port map ( + AS(0) => pLockLostRst, + CLKB => \^serialclk\, + PixelClk_int => PixelClk_int, + Q(7 downto 0) => piData(15 downto 8), + RefClk => RefClk, + SR(0) => \DataDecoders[2].DecoderX_n_3\, + TMDS_Data_n(0) => TMDS_Data_n(0), + TMDS_Data_p(0) => TMDS_Data_p(0), + pAligned_reg => \DataDecoders[1].DecoderX_n_0\, + pAllVld => pAllVld, + pAllVldBgnFlag => \ChannelBondX/pAllVldBgnFlag\, + pC0 => pC0, + pC1 => pC1, + \pDataIn_reg[7]_0\(0) => \DataDecoders[0].DecoderX_n_6\, + pRdy_0 => pRdy_0, + pRdy_1 => pRdy_1, + pRdy_2 => pRdy_2, + pRst_n => pRst_n, + pVde => pVde, + pVld_0 => pVld_0, + pVld_1 => pVld_1, + pVld_2 => pVld_2, + \rMMCM_Reset_q_reg[0]\ => \^serialclk\ + ); +\DataDecoders[1].DecoderX\: entity work.Arty_Z7_20_dvi2rgb_0_0_TMDS_Decoder_0 + port map ( + AS(0) => pLockLostRst, + CLKB => \^serialclk\, + PixelClk_int => PixelClk_int, + Q(7 downto 0) => piData(7 downto 0), + RefClk => RefClk, + SR(0) => \DataDecoders[1].DecoderX_n_3\, + TMDS_Data_n(0) => TMDS_Data_n(1), + TMDS_Data_p(0) => TMDS_Data_p(1), + pAllVld => pAllVld, + pAllVldBgnFlag => \ChannelBondX/pAllVldBgnFlag\, + pMeRdy_int_reg => \DataDecoders[1].DecoderX_n_0\, + pMeRdy_int_reg_0(0) => \DataDecoders[0].DecoderX_n_6\, + pRdy_0 => pRdy_0, + pRdy_1 => pRdy_1, + pRdy_2 => pRdy_2, + pRst_n => pRst_n, + pVld_0 => pVld_0, + pVld_1 => pVld_1, + pVld_2 => pVld_2, + \rMMCM_Reset_q_reg[0]\ => \^serialclk\ + ); +\DataDecoders[2].DecoderX\: entity work.Arty_Z7_20_dvi2rgb_0_0_TMDS_Decoder_1 + port map ( + CLKB => \^serialclk\, + PixelClk_int => PixelClk_int, + Q(7 downto 0) => pDataIn(7 downto 0), + RefClk => RefClk, + SR(0) => \DataDecoders[2].DecoderX_n_3\, + TMDS_Data_n(0) => TMDS_Data_n(2), + TMDS_Data_p(0) => TMDS_Data_p(2), + \out\(0) => pLockLostRst, + pAligned_reg => \DataDecoders[1].DecoderX_n_0\, + pAllVld => pAllVld, + pAllVldBgnFlag => \ChannelBondX/pAllVldBgnFlag\, + pMeRdy_int_reg(0) => \DataDecoders[1].DecoderX_n_3\, + pRdy_0 => pRdy_0, + pRdy_1 => pRdy_1, + pRdy_2 => pRdy_2, + pRst_n => pRst_n, + pVld_0 => pVld_0, + pVld_1 => pVld_1, + pVld_2 => pVld_2, + \rMMCM_Reset_q_reg[0]\ => \^serialclk\ + ); +GND: unisim.vcomponents.GND + port map ( + G => \\ + ); +\GenerateBUFG.ResyncToBUFG_X\: entity work.Arty_Z7_20_dvi2rgb_0_0_ResyncToBUFG + port map ( + CLK => PixelClk, + D(23 downto 16) => pDataIn(7 downto 0), + D(15 downto 0) => piData(15 downto 0), + PixelClk_int => PixelClk_int, + pC0 => pC0, + pC1 => pC1, + pVde => pVde, + vid_pData(23 downto 0) => vid_pData(23 downto 0), + vid_pHSync => vid_pHSync, + vid_pVDE => vid_pVDE, + vid_pVSync => vid_pVSync + ); +\GenerateDDC.DDC_EEPROM\: entity work.Arty_Z7_20_dvi2rgb_0_0_EEPROM_8b + port map ( + DDC_SCL_I => DDC_SCL_I, + DDC_SDA_I => DDC_SDA_I, + DDC_SDA_T => DDC_SDA_T, + RefClk => RefClk + ); +LockLostReset: entity work.Arty_Z7_20_dvi2rgb_0_0_ResetBridge + port map ( + PixelClk_int => PixelClk_int, + in0 => TMDS_ClockingX_n_3, + \out\(0) => pLockLostRst + ); +TMDS_ClockingX: entity work.Arty_Z7_20_dvi2rgb_0_0_TMDS_Clocking + port map ( + PixelClk_int => PixelClk_int, + RefClk => RefClk, + TMDS_Clk_n => TMDS_Clk_n, + TMDS_Clk_p => TMDS_Clk_p, + aPixelClkLckd => aPixelClkLckd, + aRst_n => aRst_n, + in0 => TMDS_ClockingX_n_3, + \pDataQ_reg[8]\ => \^serialclk\ + ); +VCC: unisim.vcomponents.VCC + port map ( + P => \\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_dvi2rgb_0_0 is + port ( + TMDS_Clk_p : in STD_LOGIC; + TMDS_Clk_n : in STD_LOGIC; + TMDS_Data_p : in STD_LOGIC_VECTOR ( 2 downto 0 ); + TMDS_Data_n : in STD_LOGIC_VECTOR ( 2 downto 0 ); + RefClk : in STD_LOGIC; + aRst_n : in STD_LOGIC; + vid_pData : out STD_LOGIC_VECTOR ( 23 downto 0 ); + vid_pVDE : out STD_LOGIC; + vid_pHSync : out STD_LOGIC; + vid_pVSync : out STD_LOGIC; + PixelClk : out STD_LOGIC; + aPixelClkLckd : out STD_LOGIC; + DDC_SDA_I : in STD_LOGIC; + DDC_SDA_O : out STD_LOGIC; + DDC_SDA_T : out STD_LOGIC; + DDC_SCL_I : in STD_LOGIC; + DDC_SCL_O : out STD_LOGIC; + DDC_SCL_T : out STD_LOGIC; + pRst_n : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of Arty_Z7_20_dvi2rgb_0_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of Arty_Z7_20_dvi2rgb_0_0 : entity is "Arty_Z7_20_dvi2rgb_0_0,dvi2rgb,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of Arty_Z7_20_dvi2rgb_0_0 : entity is "yes"; + attribute x_core_info : string; + attribute x_core_info of Arty_Z7_20_dvi2rgb_0_0 : entity is "dvi2rgb,Vivado 2016.4"; +end Arty_Z7_20_dvi2rgb_0_0; + +architecture STRUCTURE of Arty_Z7_20_dvi2rgb_0_0 is + signal NLW_U0_SerialClk_UNCONNECTED : STD_LOGIC; + attribute kAddBUFG : string; + attribute kAddBUFG of U0 : label is "TRUE"; + attribute kClkRange : integer; + attribute kClkRange of U0 : label is 2; + attribute kEdidFileName : string; + attribute kEdidFileName of U0 : label is "720p_edid.data"; + attribute kEmulateDDC : string; + attribute kEmulateDDC of U0 : label is "TRUE"; + attribute kIDLY_TapValuePs : integer; + attribute kIDLY_TapValuePs of U0 : label is 78; + attribute kIDLY_TapWidth : integer; + attribute kIDLY_TapWidth of U0 : label is 5; + attribute kRstActiveHigh : string; + attribute kRstActiveHigh of U0 : label is "FALSE"; +begin +U0: entity work.Arty_Z7_20_dvi2rgb_0_0_dvi2rgb + port map ( + DDC_SCL_I => DDC_SCL_I, + DDC_SCL_O => DDC_SCL_O, + DDC_SCL_T => DDC_SCL_T, + DDC_SDA_I => DDC_SDA_I, + DDC_SDA_O => DDC_SDA_O, + DDC_SDA_T => DDC_SDA_T, + PixelClk => PixelClk, + RefClk => RefClk, + SerialClk => NLW_U0_SerialClk_UNCONNECTED, + TMDS_Clk_n => TMDS_Clk_n, + TMDS_Clk_p => TMDS_Clk_p, + TMDS_Data_n(2 downto 0) => TMDS_Data_n(2 downto 0), + TMDS_Data_p(2 downto 0) => TMDS_Data_p(2 downto 0), + aPixelClkLckd => aPixelClkLckd, + aRst => '0', + aRst_n => aRst_n, + pRst => '0', + pRst_n => pRst_n, + vid_pData(23 downto 0) => vid_pData(23 downto 0), + vid_pHSync => vid_pHSync, + vid_pVDE => vid_pVDE, + vid_pVSync => vid_pVSync + ); +end STRUCTURE; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/Arty_Z7_20_dvi2rgb_0_0_stub.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/Arty_Z7_20_dvi2rgb_0_0_stub.v new file mode 100644 index 0000000..6e22bf4 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/Arty_Z7_20_dvi2rgb_0_0_stub.v @@ -0,0 +1,40 @@ +// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +// Date : Sun Mar 05 18:57:17 2017 +// Host : WK73 running 64-bit Service Pack 1 (build 7601) +// Command : write_verilog -force -mode synth_stub +// c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/Arty_Z7_20_dvi2rgb_0_0_stub.v +// Design : Arty_Z7_20_dvi2rgb_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg400-1 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "dvi2rgb,Vivado 2016.4" *) +module Arty_Z7_20_dvi2rgb_0_0(TMDS_Clk_p, TMDS_Clk_n, TMDS_Data_p, + TMDS_Data_n, RefClk, aRst_n, vid_pData, vid_pVDE, vid_pHSync, vid_pVSync, PixelClk, + aPixelClkLckd, DDC_SDA_I, DDC_SDA_O, DDC_SDA_T, DDC_SCL_I, DDC_SCL_O, DDC_SCL_T, pRst_n) +/* synthesis syn_black_box black_box_pad_pin="TMDS_Clk_p,TMDS_Clk_n,TMDS_Data_p[2:0],TMDS_Data_n[2:0],RefClk,aRst_n,vid_pData[23:0],vid_pVDE,vid_pHSync,vid_pVSync,PixelClk,aPixelClkLckd,DDC_SDA_I,DDC_SDA_O,DDC_SDA_T,DDC_SCL_I,DDC_SCL_O,DDC_SCL_T,pRst_n" */; + input TMDS_Clk_p; + input TMDS_Clk_n; + input [2:0]TMDS_Data_p; + input [2:0]TMDS_Data_n; + input RefClk; + input aRst_n; + output [23:0]vid_pData; + output vid_pVDE; + output vid_pHSync; + output vid_pVSync; + output PixelClk; + output aPixelClkLckd; + input DDC_SDA_I; + output DDC_SDA_O; + output DDC_SDA_T; + input DDC_SCL_I; + output DDC_SCL_O; + output DDC_SCL_T; + input pRst_n; +endmodule diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/Arty_Z7_20_dvi2rgb_0_0_stub.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/Arty_Z7_20_dvi2rgb_0_0_stub.vhdl new file mode 100644 index 0000000..ebec3fb --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/Arty_Z7_20_dvi2rgb_0_0_stub.vhdl @@ -0,0 +1,48 @@ +-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +-- Date : Sun Mar 05 18:57:17 2017 +-- Host : WK73 running 64-bit Service Pack 1 (build 7601) +-- Command : write_vhdl -force -mode synth_stub +-- c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/Arty_Z7_20_dvi2rgb_0_0_stub.vhdl +-- Design : Arty_Z7_20_dvi2rgb_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg400-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Arty_Z7_20_dvi2rgb_0_0 is + Port ( + TMDS_Clk_p : in STD_LOGIC; + TMDS_Clk_n : in STD_LOGIC; + TMDS_Data_p : in STD_LOGIC_VECTOR ( 2 downto 0 ); + TMDS_Data_n : in STD_LOGIC_VECTOR ( 2 downto 0 ); + RefClk : in STD_LOGIC; + aRst_n : in STD_LOGIC; + vid_pData : out STD_LOGIC_VECTOR ( 23 downto 0 ); + vid_pVDE : out STD_LOGIC; + vid_pHSync : out STD_LOGIC; + vid_pVSync : out STD_LOGIC; + PixelClk : out STD_LOGIC; + aPixelClkLckd : out STD_LOGIC; + DDC_SDA_I : in STD_LOGIC; + DDC_SDA_O : out STD_LOGIC; + DDC_SDA_T : out STD_LOGIC; + DDC_SCL_I : in STD_LOGIC; + DDC_SCL_O : out STD_LOGIC; + DDC_SCL_T : out STD_LOGIC; + pRst_n : in STD_LOGIC + ); + +end Arty_Z7_20_dvi2rgb_0_0; + +architecture stub of Arty_Z7_20_dvi2rgb_0_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "TMDS_Clk_p,TMDS_Clk_n,TMDS_Data_p[2:0],TMDS_Data_n[2:0],RefClk,aRst_n,vid_pData[23:0],vid_pVDE,vid_pHSync,vid_pVSync,PixelClk,aPixelClkLckd,DDC_SDA_I,DDC_SDA_O,DDC_SDA_T,DDC_SCL_I,DDC_SCL_O,DDC_SCL_T,pRst_n"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "dvi2rgb,Vivado 2016.4"; +begin +end; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/sim/Arty_Z7_20_dvi2rgb_0_0.vhd b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/sim/Arty_Z7_20_dvi2rgb_0_0.vhd new file mode 100644 index 0000000..97f992d --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/sim/Arty_Z7_20_dvi2rgb_0_0.vhd @@ -0,0 +1,171 @@ +-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: digilentinc.com:ip:dvi2rgb:1.7 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY Arty_Z7_20_dvi2rgb_0_0 IS + PORT ( + TMDS_Clk_p : IN STD_LOGIC; + TMDS_Clk_n : IN STD_LOGIC; + TMDS_Data_p : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + TMDS_Data_n : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + RefClk : IN STD_LOGIC; + aRst_n : IN STD_LOGIC; + vid_pData : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + vid_pVDE : OUT STD_LOGIC; + vid_pHSync : OUT STD_LOGIC; + vid_pVSync : OUT STD_LOGIC; + PixelClk : OUT STD_LOGIC; + aPixelClkLckd : OUT STD_LOGIC; + DDC_SDA_I : IN STD_LOGIC; + DDC_SDA_O : OUT STD_LOGIC; + DDC_SDA_T : OUT STD_LOGIC; + DDC_SCL_I : IN STD_LOGIC; + DDC_SCL_O : OUT STD_LOGIC; + DDC_SCL_T : OUT STD_LOGIC; + pRst_n : IN STD_LOGIC + ); +END Arty_Z7_20_dvi2rgb_0_0; + +ARCHITECTURE Arty_Z7_20_dvi2rgb_0_0_arch OF Arty_Z7_20_dvi2rgb_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF Arty_Z7_20_dvi2rgb_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT dvi2rgb IS + GENERIC ( + kEmulateDDC : BOOLEAN; + kRstActiveHigh : BOOLEAN; + kClkRange : INTEGER; + kIDLY_TapValuePs : INTEGER; + kIDLY_TapWidth : INTEGER; + kAddBUFG : BOOLEAN; + kEdidFileName : STRING + ); + PORT ( + TMDS_Clk_p : IN STD_LOGIC; + TMDS_Clk_n : IN STD_LOGIC; + TMDS_Data_p : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + TMDS_Data_n : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + RefClk : IN STD_LOGIC; + aRst : IN STD_LOGIC; + aRst_n : IN STD_LOGIC; + vid_pData : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + vid_pVDE : OUT STD_LOGIC; + vid_pHSync : OUT STD_LOGIC; + vid_pVSync : OUT STD_LOGIC; + PixelClk : OUT STD_LOGIC; + SerialClk : OUT STD_LOGIC; + aPixelClkLckd : OUT STD_LOGIC; + DDC_SDA_I : IN STD_LOGIC; + DDC_SDA_O : OUT STD_LOGIC; + DDC_SDA_T : OUT STD_LOGIC; + DDC_SCL_I : IN STD_LOGIC; + DDC_SCL_O : OUT STD_LOGIC; + DDC_SCL_T : OUT STD_LOGIC; + pRst : IN STD_LOGIC; + pRst_n : IN STD_LOGIC + ); + END COMPONENT dvi2rgb; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_INFO OF TMDS_Clk_p: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS CLK_P"; + ATTRIBUTE X_INTERFACE_INFO OF TMDS_Clk_n: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS CLK_N"; + ATTRIBUTE X_INTERFACE_INFO OF TMDS_Data_p: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS DATA_P"; + ATTRIBUTE X_INTERFACE_INFO OF TMDS_Data_n: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS DATA_N"; + ATTRIBUTE X_INTERFACE_INFO OF RefClk: SIGNAL IS "xilinx.com:signal:clock:1.0 RefClk CLK"; + ATTRIBUTE X_INTERFACE_INFO OF aRst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 AsyncRst_n RST"; + ATTRIBUTE X_INTERFACE_INFO OF vid_pData: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB DATA"; + ATTRIBUTE X_INTERFACE_INFO OF vid_pVDE: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB ACTIVE_VIDEO"; + ATTRIBUTE X_INTERFACE_INFO OF vid_pHSync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB HSYNC"; + ATTRIBUTE X_INTERFACE_INFO OF vid_pVSync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB VSYNC"; + ATTRIBUTE X_INTERFACE_INFO OF PixelClk: SIGNAL IS "xilinx.com:signal:clock:1.0 PixelClk CLK"; + ATTRIBUTE X_INTERFACE_INFO OF DDC_SDA_I: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SDA_I"; + ATTRIBUTE X_INTERFACE_INFO OF DDC_SDA_O: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SDA_O"; + ATTRIBUTE X_INTERFACE_INFO OF DDC_SDA_T: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SDA_T"; + ATTRIBUTE X_INTERFACE_INFO OF DDC_SCL_I: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SCL_I"; + ATTRIBUTE X_INTERFACE_INFO OF DDC_SCL_O: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SCL_O"; + ATTRIBUTE X_INTERFACE_INFO OF DDC_SCL_T: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SCL_T"; + ATTRIBUTE X_INTERFACE_INFO OF pRst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 SyncRst_n RST"; +BEGIN + U0 : dvi2rgb + GENERIC MAP ( + kEmulateDDC => true, + kRstActiveHigh => false, + kClkRange => 2, + kIDLY_TapValuePs => 78, + kIDLY_TapWidth => 5, + kAddBUFG => true, + kEdidFileName => "720p_edid.data" + ) + PORT MAP ( + TMDS_Clk_p => TMDS_Clk_p, + TMDS_Clk_n => TMDS_Clk_n, + TMDS_Data_p => TMDS_Data_p, + TMDS_Data_n => TMDS_Data_n, + RefClk => RefClk, + aRst => '0', + aRst_n => aRst_n, + vid_pData => vid_pData, + vid_pVDE => vid_pVDE, + vid_pHSync => vid_pHSync, + vid_pVSync => vid_pVSync, + PixelClk => PixelClk, + aPixelClkLckd => aPixelClkLckd, + DDC_SDA_I => DDC_SDA_I, + DDC_SDA_O => DDC_SDA_O, + DDC_SDA_T => DDC_SDA_T, + DDC_SCL_I => DDC_SCL_I, + DDC_SCL_O => DDC_SCL_O, + DDC_SCL_T => DDC_SCL_T, + pRst => '0', + pRst_n => pRst_n + ); +END Arty_Z7_20_dvi2rgb_0_0_arch; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/1024_edid.data b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/1024_edid.data new file mode 100644 index 0000000..b25791c --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/1024_edid.data @@ -0,0 +1,128 @@ +00000000 +11111111 +11111111 +11111111 +11111111 +11111111 +11111111 +00000000 +00010000 +11101100 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000010 +00011010 +00000001 +00000011 +10100001 +00110011 +00011101 +01111000 +00001010 +11101100 +00011000 +10100011 +01010100 +01000110 +10011000 +00100101 +00001111 +01001000 +01001100 +00100001 +00001000 +00000000 +10110011 +00000000 +11010001 +11000000 +10000001 +10000000 +10000001 +11000000 +10101001 +11000000 +00000001 +00000001 +00000001 +00000001 +00000001 +00000001 +00110000 +00101010 +00000000 +10011000 +01010001 +00000000 +00101010 +01000000 +00110000 +01110000 +00010011 +00000000 +00000000 +00000000 +01010100 +00000000 +00000000 +00011110 +00000000 +00000000 +00000000 +11111100 +00100000 +01000100 +01101001 +01100111 +01101001 +01101100 +01100101 +01101110 +01110100 +01000100 +01010110 +01001001 +00101101 +00110000 +00000000 +00000000 +00000000 +00010000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00010000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00111010 diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/1080_edid.data b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/1080_edid.data new file mode 100644 index 0000000..52f088c --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/1080_edid.data @@ -0,0 +1,128 @@ +00000000 +11111111 +11111111 +11111111 +11111111 +11111111 +11111111 +00000000 +00010000 +11101100 +00000011 +00000000 +00000000 +00000000 +00000000 +00000000 +00000010 +00011010 +00000001 +00000011 +10100001 +00110011 +00011101 +01111000 +00001010 +11101100 +00011000 +10100011 +01010100 +01000110 +10011000 +00100101 +00001111 +01001000 +01001100 +00100001 +00001000 +00000000 +10110011 +00000000 +11010001 +11000000 +10000001 +10000000 +10000001 +11000000 +10101001 +11000000 +00000001 +00000001 +00000001 +00000001 +00000001 +00000001 +00000010 +00111010 +10000000 +00011000 +01110001 +00111000 +00101101 +01000000 +01011000 +00101100 +01000101 +00000000 +10000000 +00111000 +01110100 +00000000 +00000000 +00011110 +00000000 +00000000 +00000000 +11111100 +00100000 +01000100 +01101001 +01100111 +01101001 +01101100 +01100101 +01101110 +01110100 +01000100 +01010110 +01001001 +00101101 +00110011 +00000000 +00000000 +00000000 +00010000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00010000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00001001 diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/720p_edid.data b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/720p_edid.data new file mode 100644 index 0000000..65b3422 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/720p_edid.data @@ -0,0 +1,128 @@ +00000000 +11111111 +11111111 +11111111 +11111111 +11111111 +11111111 +00000000 +00010000 +11101100 +00000010 +00000000 +00000000 +00000000 +00000000 +00000000 +00000010 +00011010 +00000001 +00000011 +10100001 +00110011 +00011101 +01111000 +00001010 +11101100 +00011000 +10100011 +01010100 +01000110 +10011000 +00100101 +00001111 +01001000 +01001100 +00100001 +00001000 +00000000 +10110011 +00000000 +11010001 +11000000 +10000001 +10000000 +10000001 +11000000 +10101001 +11000000 +00000001 +00000001 +00000001 +00000001 +00000001 +00000001 +00000001 +00011101 +00000000 +01110010 +01010001 +11010000 +00011110 +00100000 +01101110 +00101000 +01010101 +00000000 +00000000 +11010000 +01010010 +00000000 +00000000 +00011110 +00000000 +00000000 +00000000 +11111100 +00100000 +01000100 +01101001 +01100111 +01101001 +01101100 +01100101 +01101110 +01110100 +01000100 +01010110 +01001001 +00101101 +00110010 +00000000 +00000000 +00000000 +00010000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00010000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11101110 diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/900p_edid.data b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/900p_edid.data new file mode 100644 index 0000000..09dbd76 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/900p_edid.data @@ -0,0 +1,128 @@ +00000000 +11111111 +11111111 +11111111 +11111111 +11111111 +11111111 +00000000 +00010000 +11101100 +00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +00000010 +00011010 +00000001 +00000011 +10100001 +00110011 +00011101 +01111000 +00001010 +11101100 +00011000 +10100011 +01010100 +01000110 +10011000 +00100101 +00001111 +01001000 +01001100 +00100001 +00001000 +00000000 +10110011 +00000000 +11010001 +11000000 +10000001 +10000000 +10000001 +11000000 +10101001 +11000000 +00000001 +00000001 +00000001 +00000001 +00000001 +00000001 +00101111 +00100110 +01000000 +10100000 +01100000 +10000100 +00011010 +00110000 +00110000 +00100000 +00110101 +00000000 +00000000 +10000100 +01010011 +00000000 +00000000 +00011010 +00000000 +00000000 +00000000 +11111100 +00100000 +01000100 +01101001 +01100111 +01101001 +01101100 +01100101 +01101110 +01110100 +01000100 +01010110 +01001001 +00101101 +00110001 +00000000 +00000000 +00000000 +00010000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00010000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00110001 diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/dvi2rgb.xdc b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/dvi2rgb.xdc new file mode 100644 index 0000000..ea7c2c3 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/dvi2rgb.xdc @@ -0,0 +1,14 @@ +### Clock constraints ### +# Constrain TMDS clock in the top-level project. Constraining it here, even if overridden in the top-level project +# results in [DRC 23-20] Rule violation (PDRC-34) for the maximum MMCM VCO frequency. +# create_clock -period 6.060 [get_ports TMDS_Clk_p] + +### I/O constraints ### +# group data channel IODELAYE2 cells with the IDELAYCTRL +set_property IODELAY_GROUP dvi2rgb_iodelay_grp [get_cells DataDecoders[*].DecoderX/InputSERDES_X/InputDelay] +set_property IODELAY_GROUP dvi2rgb_iodelay_grp [get_cells TMDS_ClockingX/IDelayCtrlX] + +### Asynchronous clock domain crossings ### +set_false_path -through [get_pins -filter {NAME =~ */SyncAsync*/oSyncStages*/PRE || NAME =~ */SyncAsync*/oSyncStages*/CLR} -hier] +set_false_path -through [get_pins -filter {NAME =~ */SyncAsync*/oSyncStages_reg[0]/D} -hier] +set_false_path -through [get_pins -filter {NAME =~ */SyncBase*/iIn_q*/PRE || NAME =~ */SyncBase*/iIn_q*/CLR} -hier] diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/dvi2rgb_ooc.xdc b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/dvi2rgb_ooc.xdc new file mode 100644 index 0000000..b3cf4f7 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/dvi2rgb_ooc.xdc @@ -0,0 +1,2 @@ +create_clock -period 6.060 [get_ports TMDS_Clk_p] +create_clock -period 5.000 [get_ports RefClk] \ No newline at end of file diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/synth/Arty_Z7_20_dvi2rgb_0_0.vhd b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/synth/Arty_Z7_20_dvi2rgb_0_0.vhd new file mode 100644 index 0000000..d4a5a8b --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/synth/Arty_Z7_20_dvi2rgb_0_0.vhd @@ -0,0 +1,175 @@ +-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: digilentinc.com:ip:dvi2rgb:1.7 +-- IP Revision: 1 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY Arty_Z7_20_dvi2rgb_0_0 IS + PORT ( + TMDS_Clk_p : IN STD_LOGIC; + TMDS_Clk_n : IN STD_LOGIC; + TMDS_Data_p : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + TMDS_Data_n : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + RefClk : IN STD_LOGIC; + aRst_n : IN STD_LOGIC; + vid_pData : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + vid_pVDE : OUT STD_LOGIC; + vid_pHSync : OUT STD_LOGIC; + vid_pVSync : OUT STD_LOGIC; + PixelClk : OUT STD_LOGIC; + aPixelClkLckd : OUT STD_LOGIC; + DDC_SDA_I : IN STD_LOGIC; + DDC_SDA_O : OUT STD_LOGIC; + DDC_SDA_T : OUT STD_LOGIC; + DDC_SCL_I : IN STD_LOGIC; + DDC_SCL_O : OUT STD_LOGIC; + DDC_SCL_T : OUT STD_LOGIC; + pRst_n : IN STD_LOGIC + ); +END Arty_Z7_20_dvi2rgb_0_0; + +ARCHITECTURE Arty_Z7_20_dvi2rgb_0_0_arch OF Arty_Z7_20_dvi2rgb_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF Arty_Z7_20_dvi2rgb_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT dvi2rgb IS + GENERIC ( + kEmulateDDC : BOOLEAN; + kRstActiveHigh : BOOLEAN; + kClkRange : INTEGER; + kIDLY_TapValuePs : INTEGER; + kIDLY_TapWidth : INTEGER; + kAddBUFG : BOOLEAN; + kEdidFileName : STRING + ); + PORT ( + TMDS_Clk_p : IN STD_LOGIC; + TMDS_Clk_n : IN STD_LOGIC; + TMDS_Data_p : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + TMDS_Data_n : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + RefClk : IN STD_LOGIC; + aRst : IN STD_LOGIC; + aRst_n : IN STD_LOGIC; + vid_pData : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + vid_pVDE : OUT STD_LOGIC; + vid_pHSync : OUT STD_LOGIC; + vid_pVSync : OUT STD_LOGIC; + PixelClk : OUT STD_LOGIC; + SerialClk : OUT STD_LOGIC; + aPixelClkLckd : OUT STD_LOGIC; + DDC_SDA_I : IN STD_LOGIC; + DDC_SDA_O : OUT STD_LOGIC; + DDC_SDA_T : OUT STD_LOGIC; + DDC_SCL_I : IN STD_LOGIC; + DDC_SCL_O : OUT STD_LOGIC; + DDC_SCL_T : OUT STD_LOGIC; + pRst : IN STD_LOGIC; + pRst_n : IN STD_LOGIC + ); + END COMPONENT dvi2rgb; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF Arty_Z7_20_dvi2rgb_0_0_arch: ARCHITECTURE IS "dvi2rgb,Vivado 2016.4"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF Arty_Z7_20_dvi2rgb_0_0_arch : ARCHITECTURE IS "Arty_Z7_20_dvi2rgb_0_0,dvi2rgb,{}"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_INFO OF TMDS_Clk_p: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS CLK_P"; + ATTRIBUTE X_INTERFACE_INFO OF TMDS_Clk_n: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS CLK_N"; + ATTRIBUTE X_INTERFACE_INFO OF TMDS_Data_p: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS DATA_P"; + ATTRIBUTE X_INTERFACE_INFO OF TMDS_Data_n: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS DATA_N"; + ATTRIBUTE X_INTERFACE_INFO OF RefClk: SIGNAL IS "xilinx.com:signal:clock:1.0 RefClk CLK"; + ATTRIBUTE X_INTERFACE_INFO OF aRst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 AsyncRst_n RST"; + ATTRIBUTE X_INTERFACE_INFO OF vid_pData: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB DATA"; + ATTRIBUTE X_INTERFACE_INFO OF vid_pVDE: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB ACTIVE_VIDEO"; + ATTRIBUTE X_INTERFACE_INFO OF vid_pHSync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB HSYNC"; + ATTRIBUTE X_INTERFACE_INFO OF vid_pVSync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB VSYNC"; + ATTRIBUTE X_INTERFACE_INFO OF PixelClk: SIGNAL IS "xilinx.com:signal:clock:1.0 PixelClk CLK"; + ATTRIBUTE X_INTERFACE_INFO OF DDC_SDA_I: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SDA_I"; + ATTRIBUTE X_INTERFACE_INFO OF DDC_SDA_O: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SDA_O"; + ATTRIBUTE X_INTERFACE_INFO OF DDC_SDA_T: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SDA_T"; + ATTRIBUTE X_INTERFACE_INFO OF DDC_SCL_I: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SCL_I"; + ATTRIBUTE X_INTERFACE_INFO OF DDC_SCL_O: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SCL_O"; + ATTRIBUTE X_INTERFACE_INFO OF DDC_SCL_T: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SCL_T"; + ATTRIBUTE X_INTERFACE_INFO OF pRst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 SyncRst_n RST"; +BEGIN + U0 : dvi2rgb + GENERIC MAP ( + kEmulateDDC => true, + kRstActiveHigh => false, + kClkRange => 2, + kIDLY_TapValuePs => 78, + kIDLY_TapWidth => 5, + kAddBUFG => true, + kEdidFileName => "720p_edid.data" + ) + PORT MAP ( + TMDS_Clk_p => TMDS_Clk_p, + TMDS_Clk_n => TMDS_Clk_n, + TMDS_Data_p => TMDS_Data_p, + TMDS_Data_n => TMDS_Data_n, + RefClk => RefClk, + aRst => '0', + aRst_n => aRst_n, + vid_pData => vid_pData, + vid_pVDE => vid_pVDE, + vid_pHSync => vid_pHSync, + vid_pVSync => vid_pVSync, + PixelClk => PixelClk, + aPixelClkLckd => aPixelClkLckd, + DDC_SDA_I => DDC_SDA_I, + DDC_SDA_O => DDC_SDA_O, + DDC_SDA_T => DDC_SDA_T, + DDC_SCL_I => DDC_SCL_I, + DDC_SCL_O => DDC_SCL_O, + DDC_SCL_T => DDC_SCL_T, + pRst => '0', + pRst_n => pRst_n + ); +END Arty_Z7_20_dvi2rgb_0_0_arch; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/Arty_Z7_20_proc_sys_reset_0_3.dcp b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/Arty_Z7_20_proc_sys_reset_0_3.dcp new file mode 100644 index 0000000..3430f16 Binary files /dev/null and b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/Arty_Z7_20_proc_sys_reset_0_3.dcp differ diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/Arty_Z7_20_proc_sys_reset_0_3.xci b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/Arty_Z7_20_proc_sys_reset_0_3.xci new file mode 100644 index 0000000..c8f3533 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/Arty_Z7_20_proc_sys_reset_0_3.xci @@ -0,0 +1,71 @@ + + + xilinx.com + xci + unknown + 1.0 + + + Arty_Z7_20_proc_sys_reset_0_3 + + + ACTIVE_LOW + + Arty_Z7_20_dvi2rgb_0_0_PixelClk + 100000000 + 0.000 + ACTIVE_LOW + 0 + 4 + 0 + 4 + zynq + 1 + 1 + 1 + 1 + 0 + 4 + 0 + 4 + 1 + 1 + 1 + 1 + Arty_Z7_20_proc_sys_reset_0_3 + Custom + false + zynq + digilentinc.com:arty-z7-20:part0:1.0 + xc7z020 + clg400 + VHDL + + MIXED + -1 + + TRUE + TRUE + 38f290234db962d7 + IP_Integrator + 10 + TRUE + . + + ../../ipshared + 2016.4 + OUT_OF_CONTEXT + + + + + + + + + + + + + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/Arty_Z7_20_proc_sys_reset_0_3.xdc b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/Arty_Z7_20_proc_sys_reset_0_3.xdc new file mode 100644 index 0000000..5b437b2 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/Arty_Z7_20_proc_sys_reset_0_3.xdc @@ -0,0 +1,49 @@ + +# file: Arty_Z7_20_proc_sys_reset_0_3.xdc +# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +set_false_path -to [get_pins -hier *cdc_to*/D] diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/Arty_Z7_20_proc_sys_reset_0_3.xml b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/Arty_Z7_20_proc_sys_reset_0_3.xml new file mode 100644 index 0000000..23ba0e3 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/Arty_Z7_20_proc_sys_reset_0_3.xml @@ -0,0 +1,915 @@ + + + xilinx.com + customized_ip + Arty_Z7_20_proc_sys_reset_0_3 + 1.0 + + + clock + Clock + + + + + + + CLK + + + slowest_sync_clk + + + + + + ASSOCIATED_RESET + mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset + + + FREQ_HZ + Slowest Sync clock frequency + Slowest Synchronous clock frequency + 100000000 + + + PHASE + 0.000 + + + CLK_DOMAIN + Arty_Z7_20_dvi2rgb_0_0_PixelClk + + + ASSOCIATED_BUSIF + + + + + + ext_reset + Ext_Reset + + + + + + + RST + + + ext_reset_in + + + + + + BOARD.ASSOCIATED_PARAM + RESET_BOARD_INTERFACE + + + + required + + + + + + POLARITY + ACTIVE_LOW + + + + + aux_reset + aux_reset + + + + + + + RST + + + aux_reset_in + + + + + + POLARITY + ACTIVE_LOW + + + + + dbg_reset + DBG_Reset + + + + + + + RST + + + mb_debug_sys_rst + + + + + + POLARITY + ACTIVE_HIGH + + + + + mb_rst + MB_rst + + + + + + + RST + + + mb_reset + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + PROCESSOR + + + + + bus_struct_reset + bus_struct_reset + + + + + + + RST + + + bus_struct_reset + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + INTERCONNECT + + + + + interconnect_low_rst + interconnect_low_rst + + + + + + + RST + + + interconnect_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + TYPE + INTERCONNECT + + + + + peripheral_high_rst + peripheral_high_rst + + + + + + + RST + + + peripheral_reset + + + + + + POLARITY + ACTIVE_HIGH + + + TYPE + PERIPHERAL + + + + + peripheral_low_rst + peripheral_low_rst + + + + + + + RST + + + peripheral_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + TYPE + PERIPHERAL + + + + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + + xilinx_vhdlsynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset + + + xilinx_vhdlsynthesis_view_fileset + + + + GENtimestamp + Sun Mar 05 02:51:36 UTC 2017 + + + boundaryCRC + 5be156f1 + + + boundaryCRCversion + 1 + + + customizationCRC + 853e16c8 + + + customizationCRCversion + 6 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + xilinx_synthesisconstraints_view_fileset + + + + GENtimestamp + Sun Mar 05 02:51:36 UTC 2017 + + + boundaryCRC + 5be156f1 + + + boundaryCRCversion + 1 + + + customizationCRC + 853e16c8 + + + customizationCRCversion + 6 + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Sun Mar 05 02:51:36 UTC 2017 + + + boundaryCRC + 5be156f1 + + + boundaryCRCversion + 1 + + + customizationCRC + 853e16c8 + + + customizationCRCversion + 6 + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + GENtimestamp + Fri Feb 24 23:58:23 UTC 2017 + + + boundaryCRC + 5be156f1 + + + boundaryCRCversion + 1 + + + customizationCRC + 0cc647d5 + + + customizationCRCversion + 6 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Sun Mar 05 02:51:36 UTC 2017 + + + boundaryCRC + 5be156f1 + + + boundaryCRCversion + 1 + + + customizationCRC + 0cc647d5 + + + customizationCRCversion + 6 + + + + + xilinx_implementation + Implementation + :vivado.xilinx.com:implementation + + xilinx_implementation_view_fileset + + + + GENtimestamp + Sun Mar 05 02:51:36 UTC 2017 + + + boundaryCRC + 5be156f1 + + + boundaryCRCversion + 1 + + + customizationCRC + 853e16c8 + + + customizationCRCversion + 6 + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Sun Mar 05 02:51:44 UTC 2017 + + + boundaryCRC + 5be156f1 + + + boundaryCRCversion + 1 + + + customizationCRC + 853e16c8 + + + customizationCRCversion + 6 + + + + + + + slowest_sync_clk + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + ext_reset_in + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + aux_reset_in + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + mb_debug_sys_rst + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + dcm_locked + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0x1 + + + + + mb_reset + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0x0 + + + + + bus_struct_reset + + out + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + peripheral_reset + + out + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + interconnect_aresetn + + out + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + peripheral_aresetn + + out + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + + C_FAMILY + zynq + + + C_EXT_RST_WIDTH + Ext Rst Width + 4 + + + C_AUX_RST_WIDTH + Aux Rst Width + 4 + + + C_EXT_RESET_HIGH + Ext Reset High + 0 + + + C_AUX_RESET_HIGH + Aux Reset High + 0 + + + C_NUM_BUS_RST + No. of Bus Reset (Active High) + 1 + + + C_NUM_PERP_RST + No. of Peripheral Reset (Active High) + 1 + + + C_NUM_INTERCONNECT_ARESETN + No. of Interconnect Reset (Active Low) + 1 + + + C_NUM_PERP_ARESETN + No. of Peripheral Reset (Active Low) + 1 + + + + + + choice_list_ac75ef1e + Custom + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset + + ../../ipshared/52cb/hdl/lib_cdc_v1_0_rfs.vhd + vhdlSource + lib_cdc_v1_0_2 + + + + + + + + + + + xilinx_vhdlsynthesis_view_fileset + + ../../ipshared/04b4/hdl/proc_sys_reset_v5_0_vh_rfs.vhd + vhdlSource + proc_sys_reset_v5_0_10 + + + Arty_Z7_20_proc_sys_reset_0_3.xdc + xdc + + + + xilinx_synthesisconstraints_view_fileset + + Arty_Z7_20_proc_sys_reset_0_3_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/Arty_Z7_20_proc_sys_reset_0_3.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset + + ../../ipshared/52cb/hdl/lib_cdc_v1_0_rfs.vhd + vhdlSource + USED_IN_ipstatic + lib_cdc_v1_0_2 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + ../../ipshared/04b4/hdl/proc_sys_reset_v5_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + proc_sys_reset_v5_0_10 + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/Arty_Z7_20_proc_sys_reset_0_3.vhd + vhdlSource + xil_defaultlib + + + + xilinx_implementation_view_fileset + + Arty_Z7_20_proc_sys_reset_0_3_board.xdc + xdc + USED_IN_board + USED_IN_implementation + USED_IN_synthesis + + + + xilinx_externalfiles_view_fileset + + Arty_Z7_20_proc_sys_reset_0_3.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + Arty_Z7_20_proc_sys_reset_0_3_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Arty_Z7_20_proc_sys_reset_0_3_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Arty_Z7_20_proc_sys_reset_0_3_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Arty_Z7_20_proc_sys_reset_0_3_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + + Processor Reset System + + + C_NUM_PERP_ARESETN + No. of Peripheral Reset (Active Low) + 1 + + + C_NUM_INTERCONNECT_ARESETN + No. of Interconnect Reset (Active Low) + 1 + + + C_NUM_PERP_RST + No. of Peripheral Reset (Active High) + 1 + + + C_NUM_BUS_RST + No. of Bus Reset (Active High) + 1 + + + C_AUX_RESET_HIGH + Aux Reset High + 0 + + + C_EXT_RESET_HIGH + Ext Reset High + 0 + + + C_AUX_RST_WIDTH + Aux Rst Width + 4 + + + C_EXT_RST_WIDTH + Ext Rst Width + 4 + + + Component_Name + Arty_Z7_20_proc_sys_reset_0_3 + + + USE_BOARD_FLOW + Generate Board based IO Constraints + false + + + RESET_BOARD_INTERFACE + Custom + + + + + Processor System Reset + 10 + + + + + + + + + 2016.4 + + + + + + + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/Arty_Z7_20_proc_sys_reset_0_3_board.xdc b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/Arty_Z7_20_proc_sys_reset_0_3_board.xdc new file mode 100644 index 0000000..3422a8e --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/Arty_Z7_20_proc_sys_reset_0_3_board.xdc @@ -0,0 +1,2 @@ +#--------------------Physical Constraints----------------- + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/Arty_Z7_20_proc_sys_reset_0_3_ooc.xdc b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/Arty_Z7_20_proc_sys_reset_0_3_ooc.xdc new file mode 100644 index 0000000..4160f21 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/Arty_Z7_20_proc_sys_reset_0_3_ooc.xdc @@ -0,0 +1,57 @@ +# (c) Copyright 2012-2017 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +# DO NOT MODIFY THIS FILE. +# ######################################################### +# +# This XDC is used only in OOC mode for synthesis, implementation +# +# ######################################################### + + +create_clock -period 10 -name slowest_sync_clk [get_ports slowest_sync_clk] + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/Arty_Z7_20_proc_sys_reset_0_3_sim_netlist.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/Arty_Z7_20_proc_sys_reset_0_3_sim_netlist.v new file mode 100644 index 0000000..07f04c1 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/Arty_Z7_20_proc_sys_reset_0_3_sim_netlist.v @@ -0,0 +1,930 @@ +// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +// Date : Fri Feb 24 16:03:30 2017 +// Host : WK73 running 64-bit Service Pack 1 (build 7601) +// Command : write_verilog -force -mode funcsim -rename_top Arty_Z7_20_proc_sys_reset_0_3 -prefix +// Arty_Z7_20_proc_sys_reset_0_3_ Arty_Z7_20_rst_processing_system7_0_100M_0_sim_netlist.v +// Design : Arty_Z7_20_rst_processing_system7_0_100M_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg400-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "Arty_Z7_20_rst_processing_system7_0_100M_0,proc_sys_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "proc_sys_reset,Vivado 2016.4" *) +(* NotValidForBitStream *) +module Arty_Z7_20_proc_sys_reset_0_3 + (slowest_sync_clk, + ext_reset_in, + aux_reset_in, + mb_debug_sys_rst, + dcm_locked, + mb_reset, + bus_struct_reset, + peripheral_reset, + interconnect_aresetn, + peripheral_aresetn); + (* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) input slowest_sync_clk; + (* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) input ext_reset_in; + (* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) input aux_reset_in; + (* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) input mb_debug_sys_rst; + input dcm_locked; + (* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) output mb_reset; + (* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) output [0:0]bus_struct_reset; + (* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) output [0:0]peripheral_reset; + (* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) output [0:0]interconnect_aresetn; + (* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) output [0:0]peripheral_aresetn; + + wire aux_reset_in; + wire [0:0]bus_struct_reset; + wire dcm_locked; + wire ext_reset_in; + wire [0:0]interconnect_aresetn; + wire mb_debug_sys_rst; + wire mb_reset; + wire [0:0]peripheral_aresetn; + wire [0:0]peripheral_reset; + wire slowest_sync_clk; + + (* C_AUX_RESET_HIGH = "1'b0" *) + (* C_AUX_RST_WIDTH = "4" *) + (* C_EXT_RESET_HIGH = "1'b0" *) + (* C_EXT_RST_WIDTH = "4" *) + (* C_FAMILY = "zynq" *) + (* C_NUM_BUS_RST = "1" *) + (* C_NUM_INTERCONNECT_ARESETN = "1" *) + (* C_NUM_PERP_ARESETN = "1" *) + (* C_NUM_PERP_RST = "1" *) + Arty_Z7_20_proc_sys_reset_0_3_proc_sys_reset U0 + (.aux_reset_in(aux_reset_in), + .bus_struct_reset(bus_struct_reset), + .dcm_locked(dcm_locked), + .ext_reset_in(ext_reset_in), + .interconnect_aresetn(interconnect_aresetn), + .mb_debug_sys_rst(mb_debug_sys_rst), + .mb_reset(mb_reset), + .peripheral_aresetn(peripheral_aresetn), + .peripheral_reset(peripheral_reset), + .slowest_sync_clk(slowest_sync_clk)); +endmodule + +module Arty_Z7_20_proc_sys_reset_0_3_cdc_sync + (lpf_asr_reg, + scndry_out, + aux_reset_in, + lpf_asr, + asr_lpf, + p_1_in, + p_2_in, + slowest_sync_clk); + output lpf_asr_reg; + output scndry_out; + input aux_reset_in; + input lpf_asr; + input [0:0]asr_lpf; + input p_1_in; + input p_2_in; + input slowest_sync_clk; + + wire asr_d1; + wire [0:0]asr_lpf; + wire aux_reset_in; + wire lpf_asr; + wire lpf_asr_reg; + wire p_1_in; + wire p_2_in; + wire s_level_out_d1_cdc_to; + wire s_level_out_d2; + wire s_level_out_d3; + wire scndry_out; + wire slowest_sync_clk; + + (* ASYNC_REG *) + (* BOX_TYPE = "PRIMITIVE" *) + (* XILINX_LEGACY_PRIM = "FDR" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(slowest_sync_clk), + .CE(1'b1), + .D(asr_d1), + .Q(s_level_out_d1_cdc_to), + .R(1'b0)); + LUT1 #( + .INIT(2'h1)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1 + (.I0(aux_reset_in), + .O(asr_d1)); + (* ASYNC_REG *) + (* BOX_TYPE = "PRIMITIVE" *) + (* XILINX_LEGACY_PRIM = "FDR" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 + (.C(slowest_sync_clk), + .CE(1'b1), + .D(s_level_out_d1_cdc_to), + .Q(s_level_out_d2), + .R(1'b0)); + (* ASYNC_REG *) + (* BOX_TYPE = "PRIMITIVE" *) + (* XILINX_LEGACY_PRIM = "FDR" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 + (.C(slowest_sync_clk), + .CE(1'b1), + .D(s_level_out_d2), + .Q(s_level_out_d3), + .R(1'b0)); + (* ASYNC_REG *) + (* BOX_TYPE = "PRIMITIVE" *) + (* XILINX_LEGACY_PRIM = "FDR" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 + (.C(slowest_sync_clk), + .CE(1'b1), + .D(s_level_out_d3), + .Q(scndry_out), + .R(1'b0)); + LUT5 #( + .INIT(32'hEAAAAAA8)) + lpf_asr_i_1 + (.I0(lpf_asr), + .I1(asr_lpf), + .I2(scndry_out), + .I3(p_1_in), + .I4(p_2_in), + .O(lpf_asr_reg)); +endmodule + +(* ORIG_REF_NAME = "cdc_sync" *) +module Arty_Z7_20_proc_sys_reset_0_3_cdc_sync_0 + (lpf_exr_reg, + scndry_out, + lpf_exr, + p_3_out, + mb_debug_sys_rst, + ext_reset_in, + slowest_sync_clk); + output lpf_exr_reg; + output scndry_out; + input lpf_exr; + input [2:0]p_3_out; + input mb_debug_sys_rst; + input ext_reset_in; + input slowest_sync_clk; + + wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ; + wire ext_reset_in; + wire lpf_exr; + wire lpf_exr_reg; + wire mb_debug_sys_rst; + wire [2:0]p_3_out; + wire s_level_out_d1_cdc_to; + wire s_level_out_d2; + wire s_level_out_d3; + wire scndry_out; + wire slowest_sync_clk; + + (* ASYNC_REG *) + (* BOX_TYPE = "PRIMITIVE" *) + (* XILINX_LEGACY_PRIM = "FDR" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to + (.C(slowest_sync_clk), + .CE(1'b1), + .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ), + .Q(s_level_out_d1_cdc_to), + .R(1'b0)); + LUT2 #( + .INIT(4'hB)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0 + (.I0(mb_debug_sys_rst), + .I1(ext_reset_in), + .O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 )); + (* ASYNC_REG *) + (* BOX_TYPE = "PRIMITIVE" *) + (* XILINX_LEGACY_PRIM = "FDR" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 + (.C(slowest_sync_clk), + .CE(1'b1), + .D(s_level_out_d1_cdc_to), + .Q(s_level_out_d2), + .R(1'b0)); + (* ASYNC_REG *) + (* BOX_TYPE = "PRIMITIVE" *) + (* XILINX_LEGACY_PRIM = "FDR" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 + (.C(slowest_sync_clk), + .CE(1'b1), + .D(s_level_out_d2), + .Q(s_level_out_d3), + .R(1'b0)); + (* ASYNC_REG *) + (* BOX_TYPE = "PRIMITIVE" *) + (* XILINX_LEGACY_PRIM = "FDR" *) + FDRE #( + .INIT(1'b0)) + \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 + (.C(slowest_sync_clk), + .CE(1'b1), + .D(s_level_out_d3), + .Q(scndry_out), + .R(1'b0)); + LUT5 #( + .INIT(32'hEAAAAAA8)) + lpf_exr_i_1 + (.I0(lpf_exr), + .I1(p_3_out[0]), + .I2(scndry_out), + .I3(p_3_out[1]), + .I4(p_3_out[2]), + .O(lpf_exr_reg)); +endmodule + +module Arty_Z7_20_proc_sys_reset_0_3_lpf + (lpf_int, + slowest_sync_clk, + dcm_locked, + aux_reset_in, + mb_debug_sys_rst, + ext_reset_in); + output lpf_int; + input slowest_sync_clk; + input dcm_locked; + input aux_reset_in; + input mb_debug_sys_rst; + input ext_reset_in; + + wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ; + wire \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ; + wire Q; + wire [0:0]asr_lpf; + wire aux_reset_in; + wire dcm_locked; + wire ext_reset_in; + wire lpf_asr; + wire lpf_exr; + wire lpf_int; + wire lpf_int0__0; + wire mb_debug_sys_rst; + wire p_1_in; + wire p_2_in; + wire p_3_in1_in; + wire [3:0]p_3_out; + wire slowest_sync_clk; + + Arty_Z7_20_proc_sys_reset_0_3_cdc_sync \ACTIVE_LOW_AUX.ACT_LO_AUX + (.asr_lpf(asr_lpf), + .aux_reset_in(aux_reset_in), + .lpf_asr(lpf_asr), + .lpf_asr_reg(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ), + .p_1_in(p_1_in), + .p_2_in(p_2_in), + .scndry_out(p_3_in1_in), + .slowest_sync_clk(slowest_sync_clk)); + Arty_Z7_20_proc_sys_reset_0_3_cdc_sync_0 \ACTIVE_LOW_EXT.ACT_LO_EXT + (.ext_reset_in(ext_reset_in), + .lpf_exr(lpf_exr), + .lpf_exr_reg(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ), + .mb_debug_sys_rst(mb_debug_sys_rst), + .p_3_out(p_3_out[2:0]), + .scndry_out(p_3_out[3]), + .slowest_sync_clk(slowest_sync_clk)); + FDRE #( + .INIT(1'b0)) + \AUX_LPF[1].asr_lpf_reg[1] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(p_3_in1_in), + .Q(p_2_in), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AUX_LPF[2].asr_lpf_reg[2] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(p_2_in), + .Q(p_1_in), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AUX_LPF[3].asr_lpf_reg[3] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(p_1_in), + .Q(asr_lpf), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \EXT_LPF[1].exr_lpf_reg[1] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(p_3_out[3]), + .Q(p_3_out[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \EXT_LPF[2].exr_lpf_reg[2] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(p_3_out[2]), + .Q(p_3_out[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \EXT_LPF[3].exr_lpf_reg[3] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(p_3_out[1]), + .Q(p_3_out[0]), + .R(1'b0)); + (* BOX_TYPE = "PRIMITIVE" *) + (* XILINX_LEGACY_PRIM = "SRL16" *) + (* srl_name = "U0/\EXT_LPF/POR_SRL_I " *) + SRL16E #( + .INIT(16'hFFFF)) + POR_SRL_I + (.A0(1'b1), + .A1(1'b1), + .A2(1'b1), + .A3(1'b1), + .CE(1'b1), + .CLK(slowest_sync_clk), + .D(1'b0), + .Q(Q)); + FDRE #( + .INIT(1'b0)) + lpf_asr_reg + (.C(slowest_sync_clk), + .CE(1'b1), + .D(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ), + .Q(lpf_asr), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + lpf_exr_reg + (.C(slowest_sync_clk), + .CE(1'b1), + .D(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ), + .Q(lpf_exr), + .R(1'b0)); + LUT4 #( + .INIT(16'hFFEF)) + lpf_int0 + (.I0(Q), + .I1(lpf_asr), + .I2(dcm_locked), + .I3(lpf_exr), + .O(lpf_int0__0)); + FDRE #( + .INIT(1'b0)) + lpf_int_reg + (.C(slowest_sync_clk), + .CE(1'b1), + .D(lpf_int0__0), + .Q(lpf_int), + .R(1'b0)); +endmodule + +(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b0" *) +(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "zynq" *) (* C_NUM_BUS_RST = "1" *) +(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *) (* C_NUM_PERP_RST = "1" *) +module Arty_Z7_20_proc_sys_reset_0_3_proc_sys_reset + (slowest_sync_clk, + ext_reset_in, + aux_reset_in, + mb_debug_sys_rst, + dcm_locked, + mb_reset, + bus_struct_reset, + peripheral_reset, + interconnect_aresetn, + peripheral_aresetn); + input slowest_sync_clk; + input ext_reset_in; + input aux_reset_in; + input mb_debug_sys_rst; + input dcm_locked; + output mb_reset; + (* equivalent_register_removal = "no" *) output [0:0]bus_struct_reset; + (* equivalent_register_removal = "no" *) output [0:0]peripheral_reset; + (* equivalent_register_removal = "no" *) output [0:0]interconnect_aresetn; + (* equivalent_register_removal = "no" *) output [0:0]peripheral_aresetn; + + wire Core; + wire SEQ_n_3; + wire SEQ_n_4; + wire aux_reset_in; + wire bsr; + wire [0:0]bus_struct_reset; + wire dcm_locked; + wire ext_reset_in; + wire [0:0]interconnect_aresetn; + wire lpf_int; + wire mb_debug_sys_rst; + wire mb_reset; + wire [0:0]peripheral_aresetn; + wire [0:0]peripheral_reset; + wire pr; + wire slowest_sync_clk; + + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b1)) + \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(SEQ_n_3), + .Q(interconnect_aresetn), + .R(1'b0)); + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b1)) + \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(SEQ_n_4), + .Q(peripheral_aresetn), + .R(1'b0)); + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \BSR_OUT_DFF[0].bus_struct_reset_reg[0] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(bsr), + .Q(bus_struct_reset), + .R(1'b0)); + Arty_Z7_20_proc_sys_reset_0_3_lpf EXT_LPF + (.aux_reset_in(aux_reset_in), + .dcm_locked(dcm_locked), + .ext_reset_in(ext_reset_in), + .lpf_int(lpf_int), + .mb_debug_sys_rst(mb_debug_sys_rst), + .slowest_sync_clk(slowest_sync_clk)); + (* equivalent_register_removal = "no" *) + FDRE #( + .INIT(1'b0)) + \PR_OUT_DFF[0].peripheral_reset_reg[0] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(pr), + .Q(peripheral_reset), + .R(1'b0)); + Arty_Z7_20_proc_sys_reset_0_3_sequence_psr SEQ + (.\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] (SEQ_n_3), + .\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] (SEQ_n_4), + .Core(Core), + .bsr(bsr), + .lpf_int(lpf_int), + .pr(pr), + .slowest_sync_clk(slowest_sync_clk)); + FDRE #( + .INIT(1'b0)) + mb_reset_reg + (.C(slowest_sync_clk), + .CE(1'b1), + .D(Core), + .Q(mb_reset), + .R(1'b0)); +endmodule + +module Arty_Z7_20_proc_sys_reset_0_3_sequence_psr + (Core, + bsr, + pr, + \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] , + \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] , + lpf_int, + slowest_sync_clk); + output Core; + output bsr; + output pr; + output \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ; + output \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ; + input lpf_int; + input slowest_sync_clk; + + wire \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] ; + wire \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] ; + wire Core; + wire Core_i_1_n_0; + wire bsr; + wire \bsr_dec_reg_n_0_[0] ; + wire \bsr_dec_reg_n_0_[2] ; + wire bsr_i_1_n_0; + wire \core_dec[0]_i_1_n_0 ; + wire \core_dec[2]_i_1_n_0 ; + wire \core_dec_reg_n_0_[0] ; + wire \core_dec_reg_n_0_[1] ; + wire from_sys_i_1_n_0; + wire lpf_int; + wire p_0_in; + wire [2:0]p_3_out; + wire [2:0]p_5_out; + wire pr; + wire pr_dec0__0; + wire \pr_dec_reg_n_0_[0] ; + wire \pr_dec_reg_n_0_[2] ; + wire pr_i_1_n_0; + wire seq_clr; + wire [5:0]seq_cnt; + wire seq_cnt_en; + wire slowest_sync_clk; + + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT1 #( + .INIT(2'h1)) + \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1 + (.I0(bsr), + .O(\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0] )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT1 #( + .INIT(2'h1)) + \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1 + (.I0(pr), + .O(\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0] )); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h2)) + Core_i_1 + (.I0(Core), + .I1(p_0_in), + .O(Core_i_1_n_0)); + FDSE #( + .INIT(1'b0)) + Core_reg + (.C(slowest_sync_clk), + .CE(1'b1), + .D(Core_i_1_n_0), + .Q(Core), + .S(lpf_int)); + Arty_Z7_20_proc_sys_reset_0_3_upcnt_n SEQ_COUNTER + (.Q(seq_cnt), + .seq_clr(seq_clr), + .seq_cnt_en(seq_cnt_en), + .slowest_sync_clk(slowest_sync_clk)); + LUT4 #( + .INIT(16'h0804)) + \bsr_dec[0]_i_1 + (.I0(seq_cnt_en), + .I1(seq_cnt[3]), + .I2(seq_cnt[5]), + .I3(seq_cnt[4]), + .O(p_5_out[0])); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h8)) + \bsr_dec[2]_i_1 + (.I0(\core_dec_reg_n_0_[1] ), + .I1(\bsr_dec_reg_n_0_[0] ), + .O(p_5_out[2])); + FDRE #( + .INIT(1'b0)) + \bsr_dec_reg[0] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(p_5_out[0]), + .Q(\bsr_dec_reg_n_0_[0] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \bsr_dec_reg[2] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(p_5_out[2]), + .Q(\bsr_dec_reg_n_0_[2] ), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT2 #( + .INIT(4'h2)) + bsr_i_1 + (.I0(bsr), + .I1(\bsr_dec_reg_n_0_[2] ), + .O(bsr_i_1_n_0)); + FDSE #( + .INIT(1'b0)) + bsr_reg + (.C(slowest_sync_clk), + .CE(1'b1), + .D(bsr_i_1_n_0), + .Q(bsr), + .S(lpf_int)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT4 #( + .INIT(16'h8040)) + \core_dec[0]_i_1 + (.I0(seq_cnt[4]), + .I1(seq_cnt[3]), + .I2(seq_cnt[5]), + .I3(seq_cnt_en), + .O(\core_dec[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h8)) + \core_dec[2]_i_1 + (.I0(\core_dec_reg_n_0_[1] ), + .I1(\core_dec_reg_n_0_[0] ), + .O(\core_dec[2]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \core_dec_reg[0] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(\core_dec[0]_i_1_n_0 ), + .Q(\core_dec_reg_n_0_[0] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \core_dec_reg[1] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(pr_dec0__0), + .Q(\core_dec_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \core_dec_reg[2] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(\core_dec[2]_i_1_n_0 ), + .Q(p_0_in), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h8)) + from_sys_i_1 + (.I0(Core), + .I1(seq_cnt_en), + .O(from_sys_i_1_n_0)); + FDSE #( + .INIT(1'b0)) + from_sys_reg + (.C(slowest_sync_clk), + .CE(1'b1), + .D(from_sys_i_1_n_0), + .Q(seq_cnt_en), + .S(lpf_int)); + LUT4 #( + .INIT(16'h0210)) + pr_dec0 + (.I0(seq_cnt[0]), + .I1(seq_cnt[1]), + .I2(seq_cnt[2]), + .I3(seq_cnt_en), + .O(pr_dec0__0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT4 #( + .INIT(16'h1080)) + \pr_dec[0]_i_1 + (.I0(seq_cnt_en), + .I1(seq_cnt[5]), + .I2(seq_cnt[3]), + .I3(seq_cnt[4]), + .O(p_3_out[0])); + LUT2 #( + .INIT(4'h8)) + \pr_dec[2]_i_1 + (.I0(\core_dec_reg_n_0_[1] ), + .I1(\pr_dec_reg_n_0_[0] ), + .O(p_3_out[2])); + FDRE #( + .INIT(1'b0)) + \pr_dec_reg[0] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(p_3_out[0]), + .Q(\pr_dec_reg_n_0_[0] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \pr_dec_reg[2] + (.C(slowest_sync_clk), + .CE(1'b1), + .D(p_3_out[2]), + .Q(\pr_dec_reg_n_0_[2] ), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h2)) + pr_i_1 + (.I0(pr), + .I1(\pr_dec_reg_n_0_[2] ), + .O(pr_i_1_n_0)); + FDSE #( + .INIT(1'b0)) + pr_reg + (.C(slowest_sync_clk), + .CE(1'b1), + .D(pr_i_1_n_0), + .Q(pr), + .S(lpf_int)); + FDRE #( + .INIT(1'b0)) + seq_clr_reg + (.C(slowest_sync_clk), + .CE(1'b1), + .D(1'b1), + .Q(seq_clr), + .R(lpf_int)); +endmodule + +module Arty_Z7_20_proc_sys_reset_0_3_upcnt_n + (Q, + seq_clr, + seq_cnt_en, + slowest_sync_clk); + output [5:0]Q; + input seq_clr; + input seq_cnt_en; + input slowest_sync_clk; + + wire [5:0]Q; + wire clear; + wire [5:0]q_int0; + wire seq_clr; + wire seq_cnt_en; + wire slowest_sync_clk; + + LUT1 #( + .INIT(2'h1)) + \q_int[0]_i_1 + (.I0(Q[0]), + .O(q_int0[0])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT2 #( + .INIT(4'h6)) + \q_int[1]_i_1 + (.I0(Q[0]), + .I1(Q[1]), + .O(q_int0[1])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT3 #( + .INIT(8'h78)) + \q_int[2]_i_1 + (.I0(Q[0]), + .I1(Q[1]), + .I2(Q[2]), + .O(q_int0[2])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'h7F80)) + \q_int[3]_i_1 + (.I0(Q[1]), + .I1(Q[0]), + .I2(Q[2]), + .I3(Q[3]), + .O(q_int0[3])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \q_int[4]_i_1 + (.I0(Q[2]), + .I1(Q[0]), + .I2(Q[1]), + .I3(Q[3]), + .I4(Q[4]), + .O(q_int0[4])); + LUT1 #( + .INIT(2'h1)) + \q_int[5]_i_1 + (.I0(seq_clr), + .O(clear)); + LUT6 #( + .INIT(64'h7FFFFFFF80000000)) + \q_int[5]_i_2 + (.I0(Q[3]), + .I1(Q[1]), + .I2(Q[0]), + .I3(Q[2]), + .I4(Q[4]), + .I5(Q[5]), + .O(q_int0[5])); + FDRE #( + .INIT(1'b1)) + \q_int_reg[0] + (.C(slowest_sync_clk), + .CE(seq_cnt_en), + .D(q_int0[0]), + .Q(Q[0]), + .R(clear)); + FDRE #( + .INIT(1'b1)) + \q_int_reg[1] + (.C(slowest_sync_clk), + .CE(seq_cnt_en), + .D(q_int0[1]), + .Q(Q[1]), + .R(clear)); + FDRE #( + .INIT(1'b1)) + \q_int_reg[2] + (.C(slowest_sync_clk), + .CE(seq_cnt_en), + .D(q_int0[2]), + .Q(Q[2]), + .R(clear)); + FDRE #( + .INIT(1'b1)) + \q_int_reg[3] + (.C(slowest_sync_clk), + .CE(seq_cnt_en), + .D(q_int0[3]), + .Q(Q[3]), + .R(clear)); + FDRE #( + .INIT(1'b1)) + \q_int_reg[4] + (.C(slowest_sync_clk), + .CE(seq_cnt_en), + .D(q_int0[4]), + .Q(Q[4]), + .R(clear)); + FDRE #( + .INIT(1'b1)) + \q_int_reg[5] + (.C(slowest_sync_clk), + .CE(seq_cnt_en), + .D(q_int0[5]), + .Q(Q[5]), + .R(clear)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/Arty_Z7_20_proc_sys_reset_0_3_sim_netlist.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/Arty_Z7_20_proc_sys_reset_0_3_sim_netlist.vhdl new file mode 100644 index 0000000..c8475b9 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/Arty_Z7_20_proc_sys_reset_0_3_sim_netlist.vhdl @@ -0,0 +1,1069 @@ +-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +-- Date : Fri Feb 24 16:03:31 2017 +-- Host : WK73 running 64-bit Service Pack 1 (build 7601) +-- Command : write_vhdl -force -mode funcsim -rename_top Arty_Z7_20_proc_sys_reset_0_3 -prefix +-- Arty_Z7_20_proc_sys_reset_0_3_ Arty_Z7_20_rst_processing_system7_0_100M_0_sim_netlist.vhdl +-- Design : Arty_Z7_20_rst_processing_system7_0_100M_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg400-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_proc_sys_reset_0_3_cdc_sync is + port ( + lpf_asr_reg : out STD_LOGIC; + scndry_out : out STD_LOGIC; + aux_reset_in : in STD_LOGIC; + lpf_asr : in STD_LOGIC; + asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 ); + p_1_in : in STD_LOGIC; + p_2_in : in STD_LOGIC; + slowest_sync_clk : in STD_LOGIC + ); +end Arty_Z7_20_proc_sys_reset_0_3_cdc_sync; + +architecture STRUCTURE of Arty_Z7_20_proc_sys_reset_0_3_cdc_sync is + signal asr_d1 : STD_LOGIC; + signal s_level_out_d1_cdc_to : STD_LOGIC; + signal s_level_out_d2 : STD_LOGIC; + signal s_level_out_d3 : STD_LOGIC; + signal \^scndry_out\ : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute BOX_TYPE : string; + attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; + attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; + attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; + attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; +begin + scndry_out <= \^scndry_out\; +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => asr_d1, + Q => s_level_out_d1_cdc_to, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => aux_reset_in, + O => asr_d1 + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => s_level_out_d1_cdc_to, + Q => s_level_out_d2, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => s_level_out_d2, + Q => s_level_out_d3, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => s_level_out_d3, + Q => \^scndry_out\, + R => '0' + ); +lpf_asr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"EAAAAAA8" + ) + port map ( + I0 => lpf_asr, + I1 => asr_lpf(0), + I2 => \^scndry_out\, + I3 => p_1_in, + I4 => p_2_in, + O => lpf_asr_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_proc_sys_reset_0_3_cdc_sync_0 is + port ( + lpf_exr_reg : out STD_LOGIC; + scndry_out : out STD_LOGIC; + lpf_exr : in STD_LOGIC; + p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 ); + mb_debug_sys_rst : in STD_LOGIC; + ext_reset_in : in STD_LOGIC; + slowest_sync_clk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_proc_sys_reset_0_3_cdc_sync_0 : entity is "cdc_sync"; +end Arty_Z7_20_proc_sys_reset_0_3_cdc_sync_0; + +architecture STRUCTURE of Arty_Z7_20_proc_sys_reset_0_3_cdc_sync_0 is + signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\ : STD_LOGIC; + signal s_level_out_d1_cdc_to : STD_LOGIC; + signal s_level_out_d2 : STD_LOGIC; + signal s_level_out_d3 : STD_LOGIC; + signal \^scndry_out\ : STD_LOGIC; + attribute ASYNC_REG : boolean; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; + attribute BOX_TYPE : string; + attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; + attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; + attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; + attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; + attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; +begin + scndry_out <= \^scndry_out\; +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\, + Q => s_level_out_d1_cdc_to, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => mb_debug_sys_rst, + I1 => ext_reset_in, + O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\ + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => s_level_out_d1_cdc_to, + Q => s_level_out_d2, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => s_level_out_d2, + Q => s_level_out_d3, + R => '0' + ); +\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => s_level_out_d3, + Q => \^scndry_out\, + R => '0' + ); +lpf_exr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"EAAAAAA8" + ) + port map ( + I0 => lpf_exr, + I1 => p_3_out(0), + I2 => \^scndry_out\, + I3 => p_3_out(1), + I4 => p_3_out(2), + O => lpf_exr_reg + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_proc_sys_reset_0_3_upcnt_n is + port ( + Q : out STD_LOGIC_VECTOR ( 5 downto 0 ); + seq_clr : in STD_LOGIC; + seq_cnt_en : in STD_LOGIC; + slowest_sync_clk : in STD_LOGIC + ); +end Arty_Z7_20_proc_sys_reset_0_3_upcnt_n; + +architecture STRUCTURE of Arty_Z7_20_proc_sys_reset_0_3_upcnt_n is + signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal clear : STD_LOGIC; + signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0"; +begin + Q(5 downto 0) <= \^q\(5 downto 0); +\q_int[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^q\(0), + O => q_int0(0) + ); +\q_int[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^q\(0), + I1 => \^q\(1), + O => q_int0(1) + ); +\q_int[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \^q\(0), + I1 => \^q\(1), + I2 => \^q\(2), + O => q_int0(2) + ); +\q_int[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \^q\(1), + I1 => \^q\(0), + I2 => \^q\(2), + I3 => \^q\(3), + O => q_int0(3) + ); +\q_int[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \^q\(2), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => \^q\(3), + I4 => \^q\(4), + O => q_int0(4) + ); +\q_int[5]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => seq_clr, + O => clear + ); +\q_int[5]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFFFFFF80000000" + ) + port map ( + I0 => \^q\(3), + I1 => \^q\(1), + I2 => \^q\(0), + I3 => \^q\(2), + I4 => \^q\(4), + I5 => \^q\(5), + O => q_int0(5) + ); +\q_int_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => slowest_sync_clk, + CE => seq_cnt_en, + D => q_int0(0), + Q => \^q\(0), + R => clear + ); +\q_int_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => slowest_sync_clk, + CE => seq_cnt_en, + D => q_int0(1), + Q => \^q\(1), + R => clear + ); +\q_int_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => slowest_sync_clk, + CE => seq_cnt_en, + D => q_int0(2), + Q => \^q\(2), + R => clear + ); +\q_int_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => slowest_sync_clk, + CE => seq_cnt_en, + D => q_int0(3), + Q => \^q\(3), + R => clear + ); +\q_int_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => slowest_sync_clk, + CE => seq_cnt_en, + D => q_int0(4), + Q => \^q\(4), + R => clear + ); +\q_int_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => slowest_sync_clk, + CE => seq_cnt_en, + D => q_int0(5), + Q => \^q\(5), + R => clear + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_proc_sys_reset_0_3_lpf is + port ( + lpf_int : out STD_LOGIC; + slowest_sync_clk : in STD_LOGIC; + dcm_locked : in STD_LOGIC; + aux_reset_in : in STD_LOGIC; + mb_debug_sys_rst : in STD_LOGIC; + ext_reset_in : in STD_LOGIC + ); +end Arty_Z7_20_proc_sys_reset_0_3_lpf; + +architecture STRUCTURE of Arty_Z7_20_proc_sys_reset_0_3_lpf is + signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC; + signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC; + signal Q : STD_LOGIC; + signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 ); + signal lpf_asr : STD_LOGIC; + signal lpf_exr : STD_LOGIC; + signal \lpf_int0__0\ : STD_LOGIC; + signal p_1_in : STD_LOGIC; + signal p_2_in : STD_LOGIC; + signal p_3_in1_in : STD_LOGIC; + signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of POR_SRL_I : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16"; + attribute srl_name : string; + attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I "; +begin +\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.Arty_Z7_20_proc_sys_reset_0_3_cdc_sync + port map ( + asr_lpf(0) => asr_lpf(0), + aux_reset_in => aux_reset_in, + lpf_asr => lpf_asr, + lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\, + p_1_in => p_1_in, + p_2_in => p_2_in, + scndry_out => p_3_in1_in, + slowest_sync_clk => slowest_sync_clk + ); +\ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.Arty_Z7_20_proc_sys_reset_0_3_cdc_sync_0 + port map ( + ext_reset_in => ext_reset_in, + lpf_exr => lpf_exr, + lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\, + mb_debug_sys_rst => mb_debug_sys_rst, + p_3_out(2 downto 0) => p_3_out(2 downto 0), + scndry_out => p_3_out(3), + slowest_sync_clk => slowest_sync_clk + ); +\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => p_3_in1_in, + Q => p_2_in, + R => '0' + ); +\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => p_2_in, + Q => p_1_in, + R => '0' + ); +\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => p_1_in, + Q => asr_lpf(0), + R => '0' + ); +\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => p_3_out(3), + Q => p_3_out(2), + R => '0' + ); +\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => p_3_out(2), + Q => p_3_out(1), + R => '0' + ); +\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => p_3_out(1), + Q => p_3_out(0), + R => '0' + ); +POR_SRL_I: unisim.vcomponents.SRL16E + generic map( + INIT => X"FFFF" + ) + port map ( + A0 => '1', + A1 => '1', + A2 => '1', + A3 => '1', + CE => '1', + CLK => slowest_sync_clk, + D => '0', + Q => Q + ); +lpf_asr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\, + Q => lpf_asr, + R => '0' + ); +lpf_exr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\, + Q => lpf_exr, + R => '0' + ); +lpf_int0: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFEF" + ) + port map ( + I0 => Q, + I1 => lpf_asr, + I2 => dcm_locked, + I3 => lpf_exr, + O => \lpf_int0__0\ + ); +lpf_int_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => \lpf_int0__0\, + Q => lpf_int, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_proc_sys_reset_0_3_sequence_psr is + port ( + Core : out STD_LOGIC; + bsr : out STD_LOGIC; + pr : out STD_LOGIC; + \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : out STD_LOGIC; + \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : out STD_LOGIC; + lpf_int : in STD_LOGIC; + slowest_sync_clk : in STD_LOGIC + ); +end Arty_Z7_20_proc_sys_reset_0_3_sequence_psr; + +architecture STRUCTURE of Arty_Z7_20_proc_sys_reset_0_3_sequence_psr is + signal \^core\ : STD_LOGIC; + signal Core_i_1_n_0 : STD_LOGIC; + signal \^bsr\ : STD_LOGIC; + signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC; + signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC; + signal bsr_i_1_n_0 : STD_LOGIC; + signal \core_dec[0]_i_1_n_0\ : STD_LOGIC; + signal \core_dec[2]_i_1_n_0\ : STD_LOGIC; + signal \core_dec_reg_n_0_[0]\ : STD_LOGIC; + signal \core_dec_reg_n_0_[1]\ : STD_LOGIC; + signal from_sys_i_1_n_0 : STD_LOGIC; + signal p_0_in : STD_LOGIC; + signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \^pr\ : STD_LOGIC; + signal \pr_dec0__0\ : STD_LOGIC; + signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC; + signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC; + signal pr_i_1_n_0 : STD_LOGIC; + signal seq_clr : STD_LOGIC; + signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal seq_cnt_en : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4"; +begin + Core <= \^core\; + bsr <= \^bsr\; + pr <= \^pr\; +\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^bsr\, + O => \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ + ); +\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^pr\, + O => \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ + ); +Core_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^core\, + I1 => p_0_in, + O => Core_i_1_n_0 + ); +Core_reg: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => Core_i_1_n_0, + Q => \^core\, + S => lpf_int + ); +SEQ_COUNTER: entity work.Arty_Z7_20_proc_sys_reset_0_3_upcnt_n + port map ( + Q(5 downto 0) => seq_cnt(5 downto 0), + seq_clr => seq_clr, + seq_cnt_en => seq_cnt_en, + slowest_sync_clk => slowest_sync_clk + ); +\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0804" + ) + port map ( + I0 => seq_cnt_en, + I1 => seq_cnt(3), + I2 => seq_cnt(5), + I3 => seq_cnt(4), + O => p_5_out(0) + ); +\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \core_dec_reg_n_0_[1]\, + I1 => \bsr_dec_reg_n_0_[0]\, + O => p_5_out(2) + ); +\bsr_dec_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => p_5_out(0), + Q => \bsr_dec_reg_n_0_[0]\, + R => '0' + ); +\bsr_dec_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => p_5_out(2), + Q => \bsr_dec_reg_n_0_[2]\, + R => '0' + ); +bsr_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^bsr\, + I1 => \bsr_dec_reg_n_0_[2]\, + O => bsr_i_1_n_0 + ); +bsr_reg: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => bsr_i_1_n_0, + Q => \^bsr\, + S => lpf_int + ); +\core_dec[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8040" + ) + port map ( + I0 => seq_cnt(4), + I1 => seq_cnt(3), + I2 => seq_cnt(5), + I3 => seq_cnt_en, + O => \core_dec[0]_i_1_n_0\ + ); +\core_dec[2]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \core_dec_reg_n_0_[1]\, + I1 => \core_dec_reg_n_0_[0]\, + O => \core_dec[2]_i_1_n_0\ + ); +\core_dec_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => \core_dec[0]_i_1_n_0\, + Q => \core_dec_reg_n_0_[0]\, + R => '0' + ); +\core_dec_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => \pr_dec0__0\, + Q => \core_dec_reg_n_0_[1]\, + R => '0' + ); +\core_dec_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => \core_dec[2]_i_1_n_0\, + Q => p_0_in, + R => '0' + ); +from_sys_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^core\, + I1 => seq_cnt_en, + O => from_sys_i_1_n_0 + ); +from_sys_reg: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => from_sys_i_1_n_0, + Q => seq_cnt_en, + S => lpf_int + ); +pr_dec0: unisim.vcomponents.LUT4 + generic map( + INIT => X"0210" + ) + port map ( + I0 => seq_cnt(0), + I1 => seq_cnt(1), + I2 => seq_cnt(2), + I3 => seq_cnt_en, + O => \pr_dec0__0\ + ); +\pr_dec[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"1080" + ) + port map ( + I0 => seq_cnt_en, + I1 => seq_cnt(5), + I2 => seq_cnt(3), + I3 => seq_cnt(4), + O => p_3_out(0) + ); +\pr_dec[2]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \core_dec_reg_n_0_[1]\, + I1 => \pr_dec_reg_n_0_[0]\, + O => p_3_out(2) + ); +\pr_dec_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => p_3_out(0), + Q => \pr_dec_reg_n_0_[0]\, + R => '0' + ); +\pr_dec_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => p_3_out(2), + Q => \pr_dec_reg_n_0_[2]\, + R => '0' + ); +pr_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^pr\, + I1 => \pr_dec_reg_n_0_[2]\, + O => pr_i_1_n_0 + ); +pr_reg: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => pr_i_1_n_0, + Q => \^pr\, + S => lpf_int + ); +seq_clr_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => '1', + Q => seq_clr, + R => lpf_int + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_proc_sys_reset_0_3_proc_sys_reset is + port ( + slowest_sync_clk : in STD_LOGIC; + ext_reset_in : in STD_LOGIC; + aux_reset_in : in STD_LOGIC; + mb_debug_sys_rst : in STD_LOGIC; + dcm_locked : in STD_LOGIC; + mb_reset : out STD_LOGIC; + bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); + peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); + interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); + peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute C_AUX_RESET_HIGH : string; + attribute C_AUX_RESET_HIGH of Arty_Z7_20_proc_sys_reset_0_3_proc_sys_reset : entity is "1'b0"; + attribute C_AUX_RST_WIDTH : integer; + attribute C_AUX_RST_WIDTH of Arty_Z7_20_proc_sys_reset_0_3_proc_sys_reset : entity is 4; + attribute C_EXT_RESET_HIGH : string; + attribute C_EXT_RESET_HIGH of Arty_Z7_20_proc_sys_reset_0_3_proc_sys_reset : entity is "1'b0"; + attribute C_EXT_RST_WIDTH : integer; + attribute C_EXT_RST_WIDTH of Arty_Z7_20_proc_sys_reset_0_3_proc_sys_reset : entity is 4; + attribute C_FAMILY : string; + attribute C_FAMILY of Arty_Z7_20_proc_sys_reset_0_3_proc_sys_reset : entity is "zynq"; + attribute C_NUM_BUS_RST : integer; + attribute C_NUM_BUS_RST of Arty_Z7_20_proc_sys_reset_0_3_proc_sys_reset : entity is 1; + attribute C_NUM_INTERCONNECT_ARESETN : integer; + attribute C_NUM_INTERCONNECT_ARESETN of Arty_Z7_20_proc_sys_reset_0_3_proc_sys_reset : entity is 1; + attribute C_NUM_PERP_ARESETN : integer; + attribute C_NUM_PERP_ARESETN of Arty_Z7_20_proc_sys_reset_0_3_proc_sys_reset : entity is 1; + attribute C_NUM_PERP_RST : integer; + attribute C_NUM_PERP_RST of Arty_Z7_20_proc_sys_reset_0_3_proc_sys_reset : entity is 1; +end Arty_Z7_20_proc_sys_reset_0_3_proc_sys_reset; + +architecture STRUCTURE of Arty_Z7_20_proc_sys_reset_0_3_proc_sys_reset is + signal Core : STD_LOGIC; + signal SEQ_n_3 : STD_LOGIC; + signal SEQ_n_4 : STD_LOGIC; + signal bsr : STD_LOGIC; + signal lpf_int : STD_LOGIC; + signal pr : STD_LOGIC; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : label is "no"; + attribute equivalent_register_removal of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : label is "no"; + attribute equivalent_register_removal of \BSR_OUT_DFF[0].bus_struct_reset_reg[0]\ : label is "no"; + attribute equivalent_register_removal of \PR_OUT_DFF[0].peripheral_reset_reg[0]\ : label is "no"; +begin +\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => SEQ_n_3, + Q => interconnect_aresetn(0), + R => '0' + ); +\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => SEQ_n_4, + Q => peripheral_aresetn(0), + R => '0' + ); +\BSR_OUT_DFF[0].bus_struct_reset_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => bsr, + Q => bus_struct_reset(0), + R => '0' + ); +EXT_LPF: entity work.Arty_Z7_20_proc_sys_reset_0_3_lpf + port map ( + aux_reset_in => aux_reset_in, + dcm_locked => dcm_locked, + ext_reset_in => ext_reset_in, + lpf_int => lpf_int, + mb_debug_sys_rst => mb_debug_sys_rst, + slowest_sync_clk => slowest_sync_clk + ); +\PR_OUT_DFF[0].peripheral_reset_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => pr, + Q => peripheral_reset(0), + R => '0' + ); +SEQ: entity work.Arty_Z7_20_proc_sys_reset_0_3_sequence_psr + port map ( + \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ => SEQ_n_3, + \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ => SEQ_n_4, + Core => Core, + bsr => bsr, + lpf_int => lpf_int, + pr => pr, + slowest_sync_clk => slowest_sync_clk + ); +mb_reset_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => slowest_sync_clk, + CE => '1', + D => Core, + Q => mb_reset, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_proc_sys_reset_0_3 is + port ( + slowest_sync_clk : in STD_LOGIC; + ext_reset_in : in STD_LOGIC; + aux_reset_in : in STD_LOGIC; + mb_debug_sys_rst : in STD_LOGIC; + dcm_locked : in STD_LOGIC; + mb_reset : out STD_LOGIC; + bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); + peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); + interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); + peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of Arty_Z7_20_proc_sys_reset_0_3 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of Arty_Z7_20_proc_sys_reset_0_3 : entity is "Arty_Z7_20_rst_processing_system7_0_100M_0,proc_sys_reset,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of Arty_Z7_20_proc_sys_reset_0_3 : entity is "yes"; + attribute x_core_info : string; + attribute x_core_info of Arty_Z7_20_proc_sys_reset_0_3 : entity is "proc_sys_reset,Vivado 2016.4"; +end Arty_Z7_20_proc_sys_reset_0_3; + +architecture STRUCTURE of Arty_Z7_20_proc_sys_reset_0_3 is + attribute C_AUX_RESET_HIGH : string; + attribute C_AUX_RESET_HIGH of U0 : label is "1'b0"; + attribute C_AUX_RST_WIDTH : integer; + attribute C_AUX_RST_WIDTH of U0 : label is 4; + attribute C_EXT_RESET_HIGH : string; + attribute C_EXT_RESET_HIGH of U0 : label is "1'b0"; + attribute C_EXT_RST_WIDTH : integer; + attribute C_EXT_RST_WIDTH of U0 : label is 4; + attribute C_FAMILY : string; + attribute C_FAMILY of U0 : label is "zynq"; + attribute C_NUM_BUS_RST : integer; + attribute C_NUM_BUS_RST of U0 : label is 1; + attribute C_NUM_INTERCONNECT_ARESETN : integer; + attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1; + attribute C_NUM_PERP_ARESETN : integer; + attribute C_NUM_PERP_ARESETN of U0 : label is 1; + attribute C_NUM_PERP_RST : integer; + attribute C_NUM_PERP_RST of U0 : label is 1; +begin +U0: entity work.Arty_Z7_20_proc_sys_reset_0_3_proc_sys_reset + port map ( + aux_reset_in => aux_reset_in, + bus_struct_reset(0) => bus_struct_reset(0), + dcm_locked => dcm_locked, + ext_reset_in => ext_reset_in, + interconnect_aresetn(0) => interconnect_aresetn(0), + mb_debug_sys_rst => mb_debug_sys_rst, + mb_reset => mb_reset, + peripheral_aresetn(0) => peripheral_aresetn(0), + peripheral_reset(0) => peripheral_reset(0), + slowest_sync_clk => slowest_sync_clk + ); +end STRUCTURE; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/Arty_Z7_20_proc_sys_reset_0_3_stub.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/Arty_Z7_20_proc_sys_reset_0_3_stub.v new file mode 100644 index 0000000..a2838b5 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/Arty_Z7_20_proc_sys_reset_0_3_stub.v @@ -0,0 +1,31 @@ +// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +// Date : Fri Feb 24 16:03:30 2017 +// Host : WK73 running 64-bit Service Pack 1 (build 7601) +// Command : write_verilog -force -mode synth_stub -rename_top Arty_Z7_20_proc_sys_reset_0_3 -prefix +// Arty_Z7_20_proc_sys_reset_0_3_ Arty_Z7_20_rst_processing_system7_0_100M_0_stub.v +// Design : Arty_Z7_20_rst_processing_system7_0_100M_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg400-1 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "proc_sys_reset,Vivado 2016.4" *) +module Arty_Z7_20_proc_sys_reset_0_3(slowest_sync_clk, ext_reset_in, aux_reset_in, + mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset, + interconnect_aresetn, peripheral_aresetn) +/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */; + input slowest_sync_clk; + input ext_reset_in; + input aux_reset_in; + input mb_debug_sys_rst; + input dcm_locked; + output mb_reset; + output [0:0]bus_struct_reset; + output [0:0]peripheral_reset; + output [0:0]interconnect_aresetn; + output [0:0]peripheral_aresetn; +endmodule diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/Arty_Z7_20_proc_sys_reset_0_3_stub.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/Arty_Z7_20_proc_sys_reset_0_3_stub.vhdl new file mode 100644 index 0000000..2d60ffc --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/Arty_Z7_20_proc_sys_reset_0_3_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +-- Date : Fri Feb 24 16:03:30 2017 +-- Host : WK73 running 64-bit Service Pack 1 (build 7601) +-- Command : write_vhdl -force -mode synth_stub -rename_top Arty_Z7_20_proc_sys_reset_0_3 -prefix +-- Arty_Z7_20_proc_sys_reset_0_3_ Arty_Z7_20_rst_processing_system7_0_100M_0_stub.vhdl +-- Design : Arty_Z7_20_rst_processing_system7_0_100M_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg400-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Arty_Z7_20_proc_sys_reset_0_3 is + Port ( + slowest_sync_clk : in STD_LOGIC; + ext_reset_in : in STD_LOGIC; + aux_reset_in : in STD_LOGIC; + mb_debug_sys_rst : in STD_LOGIC; + dcm_locked : in STD_LOGIC; + mb_reset : out STD_LOGIC; + bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); + peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); + interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); + peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + +end Arty_Z7_20_proc_sys_reset_0_3; + +architecture stub of Arty_Z7_20_proc_sys_reset_0_3 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "proc_sys_reset,Vivado 2016.4"; +begin +end; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/sim/Arty_Z7_20_proc_sys_reset_0_3.vhd b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/sim/Arty_Z7_20_proc_sys_reset_0_3.vhd new file mode 100644 index 0000000..102d70f --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/sim/Arty_Z7_20_proc_sys_reset_0_3.vhd @@ -0,0 +1,137 @@ +-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0 +-- IP Revision: 10 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY proc_sys_reset_v5_0_10; +USE proc_sys_reset_v5_0_10.proc_sys_reset; + +ENTITY Arty_Z7_20_proc_sys_reset_0_3 IS + PORT ( + slowest_sync_clk : IN STD_LOGIC; + ext_reset_in : IN STD_LOGIC; + aux_reset_in : IN STD_LOGIC; + mb_debug_sys_rst : IN STD_LOGIC; + dcm_locked : IN STD_LOGIC; + mb_reset : OUT STD_LOGIC; + bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); +END Arty_Z7_20_proc_sys_reset_0_3; + +ARCHITECTURE Arty_Z7_20_proc_sys_reset_0_3_arch OF Arty_Z7_20_proc_sys_reset_0_3 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF Arty_Z7_20_proc_sys_reset_0_3_arch: ARCHITECTURE IS "yes"; + COMPONENT proc_sys_reset IS + GENERIC ( + C_FAMILY : STRING; + C_EXT_RST_WIDTH : INTEGER; + C_AUX_RST_WIDTH : INTEGER; + C_EXT_RESET_HIGH : STD_LOGIC; + C_AUX_RESET_HIGH : STD_LOGIC; + C_NUM_BUS_RST : INTEGER; + C_NUM_PERP_RST : INTEGER; + C_NUM_INTERCONNECT_ARESETN : INTEGER; + C_NUM_PERP_ARESETN : INTEGER + ); + PORT ( + slowest_sync_clk : IN STD_LOGIC; + ext_reset_in : IN STD_LOGIC; + aux_reset_in : IN STD_LOGIC; + mb_debug_sys_rst : IN STD_LOGIC; + dcm_locked : IN STD_LOGIC; + mb_reset : OUT STD_LOGIC; + bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); + END COMPONENT proc_sys_reset; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK"; + ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST"; + ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST"; + ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST"; + ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST"; + ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST"; + ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST"; + ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST"; + ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST"; +BEGIN + U0 : proc_sys_reset + GENERIC MAP ( + C_FAMILY => "zynq", + C_EXT_RST_WIDTH => 4, + C_AUX_RST_WIDTH => 4, + C_EXT_RESET_HIGH => '0', + C_AUX_RESET_HIGH => '0', + C_NUM_BUS_RST => 1, + C_NUM_PERP_RST => 1, + C_NUM_INTERCONNECT_ARESETN => 1, + C_NUM_PERP_ARESETN => 1 + ) + PORT MAP ( + slowest_sync_clk => slowest_sync_clk, + ext_reset_in => ext_reset_in, + aux_reset_in => aux_reset_in, + mb_debug_sys_rst => mb_debug_sys_rst, + dcm_locked => dcm_locked, + mb_reset => mb_reset, + bus_struct_reset => bus_struct_reset, + peripheral_reset => peripheral_reset, + interconnect_aresetn => interconnect_aresetn, + peripheral_aresetn => peripheral_aresetn + ); +END Arty_Z7_20_proc_sys_reset_0_3_arch; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/synth/Arty_Z7_20_proc_sys_reset_0_3.vhd b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/synth/Arty_Z7_20_proc_sys_reset_0_3.vhd new file mode 100644 index 0000000..d195328 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_proc_sys_reset_0_3/synth/Arty_Z7_20_proc_sys_reset_0_3.vhd @@ -0,0 +1,140 @@ +-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0 +-- IP Revision: 10 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY Arty_Z7_20_proc_sys_reset_0_3 IS + PORT ( + slowest_sync_clk : IN STD_LOGIC; + ext_reset_in : IN STD_LOGIC; + aux_reset_in : IN STD_LOGIC; + mb_debug_sys_rst : IN STD_LOGIC; + dcm_locked : IN STD_LOGIC; + mb_reset : OUT STD_LOGIC; + bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); +END Arty_Z7_20_proc_sys_reset_0_3; + +ARCHITECTURE Arty_Z7_20_proc_sys_reset_0_3_arch OF Arty_Z7_20_proc_sys_reset_0_3 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF Arty_Z7_20_proc_sys_reset_0_3_arch: ARCHITECTURE IS "yes"; + COMPONENT proc_sys_reset IS + GENERIC ( + C_FAMILY : STRING; + C_EXT_RST_WIDTH : INTEGER; + C_AUX_RST_WIDTH : INTEGER; + C_EXT_RESET_HIGH : STD_LOGIC; + C_AUX_RESET_HIGH : STD_LOGIC; + C_NUM_BUS_RST : INTEGER; + C_NUM_PERP_RST : INTEGER; + C_NUM_INTERCONNECT_ARESETN : INTEGER; + C_NUM_PERP_ARESETN : INTEGER + ); + PORT ( + slowest_sync_clk : IN STD_LOGIC; + ext_reset_in : IN STD_LOGIC; + aux_reset_in : IN STD_LOGIC; + mb_debug_sys_rst : IN STD_LOGIC; + dcm_locked : IN STD_LOGIC; + mb_reset : OUT STD_LOGIC; + bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); + END COMPONENT proc_sys_reset; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF Arty_Z7_20_proc_sys_reset_0_3_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2016.4"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF Arty_Z7_20_proc_sys_reset_0_3_arch : ARCHITECTURE IS "Arty_Z7_20_proc_sys_reset_0_3,proc_sys_reset,{}"; + ATTRIBUTE CORE_GENERATION_INFO : STRING; + ATTRIBUTE CORE_GENERATION_INFO OF Arty_Z7_20_proc_sys_reset_0_3_arch: ARCHITECTURE IS "Arty_Z7_20_proc_sys_reset_0_3,proc_sys_reset,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=10,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK"; + ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST"; + ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST"; + ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST"; + ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST"; + ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST"; + ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST"; + ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST"; + ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST"; +BEGIN + U0 : proc_sys_reset + GENERIC MAP ( + C_FAMILY => "zynq", + C_EXT_RST_WIDTH => 4, + C_AUX_RST_WIDTH => 4, + C_EXT_RESET_HIGH => '0', + C_AUX_RESET_HIGH => '0', + C_NUM_BUS_RST => 1, + C_NUM_PERP_RST => 1, + C_NUM_INTERCONNECT_ARESETN => 1, + C_NUM_PERP_ARESETN => 1 + ) + PORT MAP ( + slowest_sync_clk => slowest_sync_clk, + ext_reset_in => ext_reset_in, + aux_reset_in => aux_reset_in, + mb_debug_sys_rst => mb_debug_sys_rst, + dcm_locked => dcm_locked, + mb_reset => mb_reset, + bus_struct_reset => bus_struct_reset, + peripheral_reset => peripheral_reset, + interconnect_aresetn => interconnect_aresetn, + peripheral_aresetn => peripheral_aresetn + ); +END Arty_Z7_20_proc_sys_reset_0_3_arch; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0.dcp b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0.dcp index 2ac902b..3c98c23 100644 Binary files a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0.dcp and b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0.dcp differ diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0.xci b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0.xci index bc31b47..d8fb50f 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0.xci +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0.xci @@ -1,2682 +1,1846 @@ - - xilinx.com - xci - unknown - 1.0 - - - Arty_Z7_20_processing_system7_0_0 - - - TDM - 8 - 11 - 11 - true - - true - 8 - - COMPONENTS - ROW_COLUMN_BANK - Single - 1250 - - - Arty_Z7_20_processing_system7_0_0_FCLK_CLK0 - 100000000 - 0.000 - - - Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 - 142857132 - 0.000 - - - Arty_Z7_20_processing_system7_0_0_FCLK_CLK2 - 76923080 - 0.000 - - - Arty_Z7_20_processing_system7_0_0_FCLK_CLK3 - 50000000 - 0.000 - ACTIVE_LOW - 7 - LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH - 32 - 0 - 0 - 0 - Arty_Z7_20_processing_system7_0_0_FCLK_CLK0 - 32 - 100000000 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 12 - 16 - 4 - 4 - 0.000 - AXI3 - READ_WRITE - 0 - 0 - 0 - 0 - 0 - - Arty_Z7_20_processing_system7_0_0_FCLK_CLK0 - 100000000 - 0.000 - 32 - 0 - 0 - 0 - Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 - 64 - 142857132 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 6 - 16 - 1 - 1 - 0.000 - AXI3 - READ_WRITE - 0 - 0 - 0 - 0 - 0 - - Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 - 142857132 - 0.000 - Arty_Z7_20_processing_system7_0_0 - 650.000000 - 23.8095 - 23.8095 - 10.000000 - 10.096154 - 125.000000 - 10.000000 - 100.000000 - 142.857132 - 76.923080 - 50.000000 - 50 - 200.000000 - 200.000000 - 50.000000 - 10.000000 - 166.666672 - 200.000000 - 108.333336 - 108.333336 - 108.333336 - 108.333336 - 108.333336 - 108.333336 - 50 - 100.000000 - 60 - 60 - 108.333336 - 6:2:1 - 650 - 26 - 0xE0008000 - <Select> - 0 - <Select> - 0xE0008FFF - External - 0 - -1 - 0xE0009000 - <Select> - 0 - <Select> - 0xE0009FFF - External - 0 - -1 - IO PLL - 1 - 1 - 100 - 0 - 100000000 - 142857132 - 76923080 - 50000000 - 0 - 0 - 0 - 0 - 667 - 1300.000 - ARM PLL - 2 - 50 - DDR PLL - 52 - 2 - 10.159 - 21 - 1050.000 - HPR(0)/LPR(32) - 15 - 2 - DDR PLL - 2 - 0 - 0 - 0 - 0 - <Select> - <Select> - <Select> - <Select> - <Select> - <Select> - <Select> - <Select> - 0x00100000 - 0x1FFFFFFF - 2 - 4 - 4 - 32 - 0xE000B000 - MIO 16 .. 27 - 1 - MIO 52 .. 53 - 0xE000BFFF - IO PLL - 8 - 1 - 1 - 1000 Mbps - 1 - MIO 9 - 0xE000C000 - <Select> - 0 - <Select> - 0xE000CFFF - IO PLL - 1 - 1 - 0 - 1000 Mbps - 0 - <Select> - 1 - Active Low - Share reset pin - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 1 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - 1 - 0 - 0 - IO PLL - 5 - 2 - IO PLL - 7 - 1 - IO PLL - 13 - 1 - IO PLL - 5 - 4 - TRUE - TRUE - TRUE - TRUE - 100 - 142 - 75 - 50 - 1 - 1 - 1 - 1 - <Select> - <Select> - <Select> - <Select> - <Select> - <Select> - <Select> - <Select> - 0 - 4 - 4 - 0 - 4 - 4 - 0xE000A000 - 1 - 6 - 6 - 0xE000AFFF - 1 - MIO - 0 - 0xE0004000 - 1 - EMIO - 0xE0004FFF - EMIO - 1 - 0 - <Select> - 0xE0005000 - 1 - EMIO - 0xE0005FFF - EMIO - 1 - 0 - <Select> - 108.333336 - 1 - Active Low - Share reset pin - None - 0 - 0 - 20 - 1000.000 - 1 - DIRECT - inout - LVCMOS 3.3V - enabled - slow - inout - LVCMOS 3.3V - enabled - slow - inout - LVCMOS 3.3V - enabled - slow - inout - LVCMOS 3.3V - enabled - slow - inout - LVCMOS 3.3V - enabled - slow - in - LVCMOS 3.3V - enabled - slow - out - LVCMOS 3.3V - enabled - slow - out - LVCMOS 1.8V - enabled - slow - out - LVCMOS 1.8V - enabled - slow - out - LVCMOS 1.8V - enabled - slow - out - LVCMOS 1.8V - enabled - slow - out - LVCMOS 3.3V - enabled - slow - out - LVCMOS 1.8V - enabled - slow - out - LVCMOS 1.8V - enabled - slow - in - LVCMOS 1.8V - enabled - slow - in - LVCMOS 1.8V - enabled - slow - in - LVCMOS 1.8V - enabled - slow - in - LVCMOS 1.8V - enabled - slow - in - LVCMOS 1.8V - enabled - slow - in - LVCMOS 1.8V - enabled - slow - inout - LVCMOS 1.8V - enabled - slow - in - LVCMOS 1.8V - enabled - slow - inout - LVCMOS 3.3V - disabled - slow - out - LVCMOS 1.8V - enabled - slow - in - LVCMOS 1.8V - enabled - slow - inout - LVCMOS 1.8V - enabled - slow - inout - LVCMOS 1.8V - enabled - slow - inout - LVCMOS 1.8V - enabled - slow - inout - LVCMOS 1.8V - enabled - slow - in - LVCMOS 1.8V - enabled - slow - inout - LVCMOS 1.8V - enabled - slow - inout - LVCMOS 1.8V - enabled - slow - inout - LVCMOS 1.8V - enabled - slow - inout - LVCMOS 3.3V - disabled - slow - inout - LVCMOS 1.8V - enabled - slow - inout - LVCMOS 1.8V - enabled - slow - inout - LVCMOS 1.8V - enabled - slow - inout - LVCMOS 1.8V - enabled - slow - inout - LVCMOS 1.8V - enabled - slow - inout - LVCMOS 1.8V - enabled - slow - out - LVCMOS 1.8V - enabled - slow - in - LVCMOS 1.8V - enabled - slow - inout - LVCMOS 1.8V - enabled - slow - inout - LVCMOS 1.8V - enabled - slow - inout - LVCMOS 3.3V - disabled - slow - inout - LVCMOS 1.8V - enabled - slow - inout - LVCMOS 1.8V - enabled - slow - out - LVCMOS 1.8V - enabled - slow - inout - LVCMOS 1.8V - enabled - slow - inout - LVCMOS 3.3V - disabled - slow - out - LVCMOS 3.3V - disabled - slow - out - LVCMOS 3.3V - disabled - slow - out - LVCMOS 3.3V - disabled - slow - out - LVCMOS 3.3V - enabled - slow - 54 - GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#ENET Reset#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0 - gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]#qspi0_sclk#gpio[7]#qspi_fbclk#reset#gpio[10]#gpio[11]#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio - 0 - 10 - 12 - 0 - 12 - 0 - 10 - 12 - 0 - 12 - 1 - 1 - 11 - 1 - 1 - 11 - 1 - 0 - <Select> - <Select> - 0 - 1 - 1 - 11 - 1 - 11 - 1 - 0 - 1 - 1 - 11 - 1 - 11 - 1 - 0 - 0 - <Select> - 0 - <Select> - 0 - <Select> - 0 - <Select> - 0 - <Select> - 0 - <Select> - <Select> - 0 - 1 - 1 - 11 - 1 - 11 - 1 - 0 - 1 - 1 - 11 - 1 - 11 - 1 - 0 - 7 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0.223 - 0.212 - 0.085 - 0.092 - 0.040 - 0.058 - -0.009 - -0.033 - clg400 - IO PLL - 5 - 200 - part0 - 0 - <Select> - 0 - LVCMOS 3.3V - LVCMOS 1.8V - PRODUCTION - 1 - MIO 8 - 0 - <Select> - 1 - MIO 1 .. 6 - 0 - <Select> - 0xFCFFFFFF - IO PLL - 5 - 1 - 200 - MIO 1 .. 6 - 1 - MIO 47 - 0 - <Select> - 0 - <Select> - 1 - MIO 40 .. 45 - 0 - <Select> - 0 - <Select> - 0 - <Select> - 0 - <Select> - 0xE0100000 - 0xE0100FFF - 0xE0101000 - 0xE0101FFF - IO PLL - 20 - 50 - 1 - NA - NA - NA - NA - NA - NA - NA - IO PLL - 1 - 100 - 0 - 0xE0006000 - 1 - EMIO - 1 - EMIO - 1 - EMIO - 0xE0006FFF - 1 - EMIO - 0xE0007000 - 0 - <Select> - 0 - <Select> - 0 - <Select> - 0xE0007FFF - 0 - <Select> - IO PLL - 6 - 166.666666 - 1 - 31 - 31 - 10 - 3 - 10 - 6 - 10 - 6 - 64 - 10 - 6 - 64 - 10 - 6 - 64 - 10 - 6 - 64 - 10 - 6 - External - 1 - 200 - 12 - 128 - 0 - <Select> - 0 - <Select> - 0 - <Select> - 0 - <Select> - 0 - <Select> - 2 - 0 - 8 - <Select> - 0xE0104000 - CPU_1X - 1 - 133.333333 - CPU_1X - 1 - 133.333333 - CPU_1X - 1 - 133.333333 - 0xE0104fff - 0 - <Select> - 0xE0105000 - CPU_1X - 1 - 133.333333 - CPU_1X - 1 - 133.333333 - CPU_1X - 1 - 133.333333 - 0xE0105fff - 0 - <Select> - 50 - 0xE0000000 - 115200 - 0 - <Select> - 0xE0000FFF - 1 - MIO 14 .. 15 - 0xE0001000 - 115200 - 0 - <Select> - 0xE0001FFF - 0 - <Select> - IO PLL - 10 - 100 - 1 - 525.000000 - 0 - 0 - 3 - 8 - 0.223 - 0.212 - 0.085 - 0.092 - 16 Bit - 7 - 25.8 - 80.4535 - 160 - 25.8 - 80.4535 - 160 - 0 - 80.4535 - 160 - 0 - 80.4535 - 160 - 0 - 10 - 6 - 4096 MBits - 15.6 - 105.056 - 160 - 18.8 - 66.904 - 160 - 0 - 89.1715 - 160 - 0 - 113.63 - 160 - 0.040 - 0.058 - -0.009 - -0.033 - 16.5 - 98.503 - 160 - 18 - 68.5855 - 160 - 0 - 90.295 - 160 - 0 - 103.977 - 160 - 16 Bits - Disabled - 1 - 525 - Normal (0-85) - DDR 3 - MT41J256M16 RE-125 - 15 - DDR3_1066F - 1 - 1 - 1 - 40.0 - 35.0 - 48.91 - 7 - 7 - 0 - NA - 0xE0102000 - 0xE0102fff - 1 - 60 - 1 - MIO 46 - MIO 28 .. 39 - 0xE0103000 - 0xE0103fff - 0 - 60 - 0 - <Select> - <Select> - 1 - Active Low - Share reset pin - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 3 - CPU_1X - 1 - 0 - 133.333333 - <Select> - None - zynq - digilentinc.com:arty-z7-20:part0:1.0 - xc7z020 - clg400 - VHDL - - MIXED - -1 - - TRUE - TRUE - IP_Integrator - 3 - TRUE - . - - ../../ipshared - 2016.4 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + xilinx.com + xci + unknown + 1.0 + + + Arty_Z7_20_processing_system7_0_0 + + + TDM + 8 + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + + + Arty_Z7_20_processing_system7_0_0_FCLK_CLK0 + 100000000 + 0.000 + + + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 + 118181816 + 0.000 + + + Arty_Z7_20_processing_system7_0_0_FCLK_CLK2 + 76923080 + 0.000 + + + Arty_Z7_20_processing_system7_0_0_FCLK_CLK3 + 50000000 + 0.000 + ACTIVE_LOW + 8 + LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH + 32 + 0 + 0 + 0 + Arty_Z7_20_processing_system7_0_0_FCLK_CLK0 + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 12 + 16 + 4 + 4 + 0.000 + AXI3 + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + Arty_Z7_20_processing_system7_0_0_FCLK_CLK0 + 100000000 + 0.000 + 32 + 0 + 0 + 0 + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 + 64 + 118181816 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 6 + 16 + 1 + 1 + 0.000 + AXI3 + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 + 118181816 + 0.000 + Arty_Z7_20_processing_system7_0_0 + 650.000000 + 23.8095 + 23.8095 + 10.000000 + 10.096154 + 125.000000 + 10.000000 + 100.000000 + 118.181816 + 76.923080 + 50.000000 + 50 + 200.000000 + 200.000000 + 50.000000 + 10.000000 + 166.666672 + 200.000000 + 108.333336 + 108.333336 + 108.333336 + 108.333336 + 108.333336 + 108.333336 + 50 + 100.000000 + 60 + 60 + 108.333336 + 6:2:1 + 650 + 26 + 0xE0008000 + <Select> + 0 + <Select> + 0xE0008FFF + External + 0 + -1 + 0xE0009000 + <Select> + 0 + <Select> + 0xE0009FFF + External + 0 + -1 + IO PLL + 1 + 1 + 100 + 0 + 100000000 + 118181816 + 76923080 + 50000000 + 0 + 0 + 0 + 0 + 667 + 1300.000 + ARM PLL + 2 + 50 + DDR PLL + 52 + 2 + 10.159 + 21 + 1050.000 + HPR(0)/LPR(32) + 15 + 2 + DDR PLL + 2 + 0 + 0 + 0 + 0 + <Select> + <Select> + <Select> + <Select> + <Select> + <Select> + <Select> + <Select> + 0x00100000 + 0x1FFFFFFF + 2 + 4 + 4 + 32 + 0xE000B000 + MIO 16 .. 27 + 1 + MIO 52 .. 53 + 0xE000BFFF + IO PLL + 8 + 1 + 1 + 1000 Mbps + 1 + MIO 9 + 0xE000C000 + <Select> + 0 + <Select> + 0xE000CFFF + IO PLL + 1 + 1 + 0 + 1000 Mbps + 0 + <Select> + 1 + Active Low + Share reset pin + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + IO PLL + 5 + 2 + ARM PLL + 11 + 1 + IO PLL + 13 + 1 + IO PLL + 5 + 4 + TRUE + TRUE + TRUE + TRUE + 100 + 120 + 75 + 50 + 1 + 1 + 1 + 1 + <Select> + <Select> + <Select> + <Select> + <Select> + <Select> + <Select> + <Select> + 0 + 4 + 4 + 0 + 4 + 4 + 0xE000A000 + 1 + 6 + 6 + 0xE000AFFF + 1 + MIO + 0 + 0xE0004000 + 1 + EMIO + 0xE0004FFF + EMIO + 1 + 0 + <Select> + 0xE0005000 + 1 + EMIO + 0xE0005FFF + EMIO + 1 + 0 + <Select> + 108.333336 + 1 + Active Low + Share reset pin + None + 0 + 0 + 20 + 1000.000 + 1 + DIRECT + inout + LVCMOS 3.3V + enabled + slow + inout + LVCMOS 3.3V + enabled + slow + inout + LVCMOS 3.3V + enabled + slow + inout + LVCMOS 3.3V + enabled + slow + inout + LVCMOS 3.3V + enabled + slow + in + LVCMOS 3.3V + enabled + slow + out + LVCMOS 3.3V + enabled + slow + out + LVCMOS 1.8V + enabled + slow + out + LVCMOS 1.8V + enabled + slow + out + LVCMOS 1.8V + enabled + slow + out + LVCMOS 1.8V + enabled + slow + out + LVCMOS 3.3V + enabled + slow + out + LVCMOS 1.8V + enabled + slow + out + LVCMOS 1.8V + enabled + slow + in + LVCMOS 1.8V + enabled + slow + in + LVCMOS 1.8V + enabled + slow + in + LVCMOS 1.8V + enabled + slow + in + LVCMOS 1.8V + enabled + slow + in + LVCMOS 1.8V + enabled + slow + in + LVCMOS 1.8V + enabled + slow + inout + LVCMOS 1.8V + enabled + slow + in + LVCMOS 1.8V + enabled + slow + inout + LVCMOS 3.3V + disabled + slow + out + LVCMOS 1.8V + enabled + slow + in + LVCMOS 1.8V + enabled + slow + inout + LVCMOS 1.8V + enabled + slow + inout + LVCMOS 1.8V + enabled + slow + inout + LVCMOS 1.8V + enabled + slow + inout + LVCMOS 1.8V + enabled + slow + in + LVCMOS 1.8V + enabled + slow + inout + LVCMOS 1.8V + enabled + slow + inout + LVCMOS 1.8V + enabled + slow + inout + LVCMOS 1.8V + enabled + slow + inout + LVCMOS 3.3V + disabled + slow + inout + LVCMOS 1.8V + enabled + slow + inout + LVCMOS 1.8V + enabled + slow + inout + LVCMOS 1.8V + enabled + slow + inout + LVCMOS 1.8V + enabled + slow + inout + LVCMOS 1.8V + enabled + slow + inout + LVCMOS 1.8V + enabled + slow + out + LVCMOS 1.8V + enabled + slow + in + LVCMOS 1.8V + enabled + slow + inout + LVCMOS 1.8V + enabled + slow + inout + LVCMOS 1.8V + enabled + slow + inout + LVCMOS 3.3V + disabled + slow + inout + LVCMOS 1.8V + enabled + slow + inout + LVCMOS 1.8V + enabled + slow + out + LVCMOS 1.8V + enabled + slow + inout + LVCMOS 1.8V + enabled + slow + inout + LVCMOS 3.3V + disabled + slow + out + LVCMOS 3.3V + disabled + slow + out + LVCMOS 3.3V + disabled + slow + out + LVCMOS 3.3V + disabled + slow + out + LVCMOS 3.3V + enabled + slow + 54 + GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#ENET Reset#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0 + gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]#qspi0_sclk#gpio[7]#qspi_fbclk#reset#gpio[10]#gpio[11]#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio + 0 + 10 + 12 + 0 + 12 + 0 + 10 + 12 + 0 + 12 + 1 + 1 + 11 + 1 + 1 + 11 + 1 + 0 + <Select> + <Select> + 0 + 1 + 1 + 11 + 1 + 11 + 1 + 0 + 1 + 1 + 11 + 1 + 11 + 1 + 0 + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + <Select> + 0 + 1 + 1 + 11 + 1 + 11 + 1 + 0 + 1 + 1 + 11 + 1 + 11 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0.223 + 0.212 + 0.085 + 0.092 + 0.040 + 0.058 + -0.009 + -0.033 + clg400 + IO PLL + 5 + 200 + part0 + 0 + <Select> + 0 + LVCMOS 3.3V + LVCMOS 1.8V + PRODUCTION + 1 + MIO 8 + 0 + <Select> + 1 + MIO 1 .. 6 + 0 + <Select> + 0xFCFFFFFF + IO PLL + 5 + 1 + 200 + MIO 1 .. 6 + 1 + MIO 47 + 0 + <Select> + 0 + <Select> + 1 + MIO 40 .. 45 + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0xE0100000 + 0xE0100FFF + 0xE0101000 + 0xE0101FFF + IO PLL + 20 + 50 + 1 + NA + NA + NA + NA + NA + NA + NA + IO PLL + 1 + 100 + 0 + 0xE0006000 + 1 + EMIO + 1 + EMIO + 1 + EMIO + 0xE0006FFF + 1 + EMIO + 0xE0007000 + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0xE0007FFF + 0 + <Select> + IO PLL + 6 + 166.666666 + 1 + 31 + 31 + 10 + 3 + 10 + 6 + 10 + 6 + 64 + 10 + 6 + 64 + 10 + 6 + 64 + 10 + 6 + 64 + 10 + 6 + External + 1 + 200 + 12 + 128 + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 2 + 0 + 8 + <Select> + 0xE0104000 + CPU_1X + 1 + 133.333333 + CPU_1X + 1 + 133.333333 + CPU_1X + 1 + 133.333333 + 0xE0104fff + 0 + <Select> + 0xE0105000 + CPU_1X + 1 + 133.333333 + CPU_1X + 1 + 133.333333 + CPU_1X + 1 + 133.333333 + 0xE0105fff + 0 + <Select> + 50 + 0xE0000000 + 115200 + 0 + <Select> + 0xE0000FFF + 1 + MIO 14 .. 15 + 0xE0001000 + 115200 + 0 + <Select> + 0xE0001FFF + 0 + <Select> + IO PLL + 10 + 100 + 1 + 525.000000 + 0 + 0 + 3 + 8 + 0.223 + 0.212 + 0.085 + 0.092 + 16 Bit + 7 + 25.8 + 80.4535 + 160 + 25.8 + 80.4535 + 160 + 0 + 80.4535 + 160 + 0 + 80.4535 + 160 + 0 + 10 + 6 + 4096 MBits + 15.6 + 105.056 + 160 + 18.8 + 66.904 + 160 + 0 + 89.1715 + 160 + 0 + 113.63 + 160 + 0.040 + 0.058 + -0.009 + -0.033 + 16.5 + 98.503 + 160 + 18 + 68.5855 + 160 + 0 + 90.295 + 160 + 0 + 103.977 + 160 + 16 Bits + Disabled + 1 + 525 + Normal (0-85) + DDR 3 + MT41J256M16 RE-125 + 15 + DDR3_1066F + 1 + 1 + 1 + 40.0 + 35.0 + 48.91 + 7 + 7 + 0 + NA + 0xE0102000 + 0xE0102fff + 1 + 60 + 1 + MIO 46 + MIO 28 .. 39 + 0xE0103000 + 0xE0103fff + 0 + 60 + 0 + <Select> + <Select> + 1 + Active Low + Share reset pin + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + CPU_1X + 1 + 0 + 133.333333 + <Select> + None + zynq + digilentinc.com:arty-z7-20:part0:1.0 + xc7z020 + clg400 + VHDL + + MIXED + -1 + + TRUE + TRUE + IP_Integrator + 3 + TRUE + . + + ../../ipshared + 2016.4 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0.xdc b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0.xdc index 5e5762b..29afe2b 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0.xdc +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0.xdc @@ -17,18 +17,18 @@ ############################################################################ # Clock constraints # ############################################################################ -create_clock -name clk_fpga_1 -period "7" [get_pins "PS7_i/FCLKCLK[1]"] -set_input_jitter clk_fpga_1 0.21 -#The clocks are asynchronous, user should constrain them appropriately.# -create_clock -name clk_fpga_0 -period "10" [get_pins "PS7_i/FCLKCLK[0]"] -set_input_jitter clk_fpga_0 0.3 -#The clocks are asynchronous, user should constrain them appropriately.# create_clock -name clk_fpga_3 -period "20" [get_pins "PS7_i/FCLKCLK[3]"] set_input_jitter clk_fpga_3 0.6 #The clocks are asynchronous, user should constrain them appropriately.# +create_clock -name clk_fpga_1 -period "8.461" [get_pins "PS7_i/FCLKCLK[1]"] +set_input_jitter clk_fpga_1 0.25383 +#The clocks are asynchronous, user should constrain them appropriately.# create_clock -name clk_fpga_2 -period "12.999" [get_pins "PS7_i/FCLKCLK[2]"] set_input_jitter clk_fpga_2 0.38997 #The clocks are asynchronous, user should constrain them appropriately.# +create_clock -name clk_fpga_0 -period "10" [get_pins "PS7_i/FCLKCLK[0]"] +set_input_jitter clk_fpga_0 0.3 +#The clocks are asynchronous, user should constrain them appropriately.# ############################################################################ diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0.xml b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0.xml index 2da89a6..3859d18 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0.xml +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0.xml @@ -4650,7 +4650,7 @@ FREQ_HZ - 142857132 + 118181816 ID_WIDTH @@ -5823,7 +5823,7 @@ FREQ_HZ - 142857132 + 118181816 PHASE @@ -6897,11 +6897,11 @@ SENSITIVITY - LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH + LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH PortWidth - 7 + 8 @@ -7187,7 +7187,7 @@ FREQ_HZ - 142857132 + 118181816 PHASE @@ -9933,11 +9933,11 @@ GENtimestamp - Mon Feb 27 18:05:22 UTC 2017 + Mon Mar 06 02:55:55 UTC 2017 boundaryCRC - 0129e5c7 + a7a2312e boundaryCRCversion @@ -9945,7 +9945,7 @@ customizationCRC - 7c4943a9 + f6ae4719 customizationCRCversion @@ -9964,11 +9964,11 @@ GENtimestamp - Mon Feb 27 18:05:22 UTC 2017 + Mon Mar 06 02:55:56 UTC 2017 boundaryCRC - 0129e5c7 + a7a2312e boundaryCRCversion @@ -9976,7 +9976,7 @@ customizationCRC - 7c4943a9 + f6ae4719 customizationCRCversion @@ -9994,7 +9994,7 @@ boundaryCRC - 0129e5c7 + a7a2312e boundaryCRCversion @@ -10002,7 +10002,7 @@ customizationCRC - bb96291e + 100c0345 customizationCRCversion @@ -10020,11 +10020,11 @@ GENtimestamp - Mon Feb 27 18:05:22 UTC 2017 + Mon Mar 06 02:55:56 UTC 2017 boundaryCRC - 0129e5c7 + a7a2312e boundaryCRCversion @@ -10032,7 +10032,7 @@ customizationCRC - bb96291e + 100c0345 customizationCRCversion @@ -10050,11 +10050,11 @@ GENtimestamp - Mon Feb 27 18:05:22 UTC 2017 + Mon Mar 06 02:55:56 UTC 2017 boundaryCRC - 0129e5c7 + a7a2312e boundaryCRCversion @@ -10062,7 +10062,7 @@ customizationCRC - bb96291e + 100c0345 customizationCRCversion @@ -10080,11 +10080,11 @@ GENtimestamp - Mon Feb 27 18:06:34 UTC 2017 + Mon Mar 06 02:57:20 UTC 2017 boundaryCRC - 0129e5c7 + a7a2312e boundaryCRCversion @@ -10092,7 +10092,7 @@ customizationCRC - 7c4943a9 + f6ae4719 customizationCRCversion @@ -23562,7 +23562,7 @@ in - 6 + 7 0 @@ -25844,7 +25844,7 @@ C_NUM_F2P_INTR_INPUTS - 7 + 8 C_IRQ_F2P_MODE @@ -28481,7 +28481,7 @@ PCW_FPGA1_PERIPHERAL_FREQMHZ PCW FPGA1 PERIPHERAL FREQMHZ - 142 + 120 PCW_FPGA2_PERIPHERAL_FREQMHZ @@ -28601,7 +28601,7 @@ PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ PCW ACT FPGA1 PERIPHERAL FREQMHZ - 142.857132 + 118.181816 PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ @@ -28651,7 +28651,7 @@ PCW_CLK1_FREQ PCW CLK1 FREQ - 142857132 + 118181816 PCW_CLK2_FREQ @@ -28791,7 +28791,7 @@ PCW_FCLK1_PERIPHERAL_DIVISOR0 CLKPARAM - 7 + 11 @@ -29971,7 +29971,7 @@ PCW_NUM_F2P_INTR_INPUTS PCW NUM F2P INTR INPUTS - 7 + 8 @@ -32288,7 +32288,7 @@ PCW_FCLK1_PERIPHERAL_CLKSRC PCW FCLK1 PERIPHERAL CLKSRC - IO PLL + ARM PLL PCW_FCLK2_PERIPHERAL_CLKSRC @@ -34234,20 +34234,20 @@ - + - + - + - + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0_sim_netlist.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0_sim_netlist.v index 3fd8cb8..0a6d964 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0_sim_netlist.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0_sim_netlist.v @@ -1,7 +1,7 @@ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -// Date : Mon Feb 27 10:06:33 2017 +// Date : Sun Mar 05 18:57:19 2017 // Host : WK73 running 64-bit Service Pack 1 (build 7601) // Command : write_verilog -force -mode funcsim // C:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0_sim_netlist.v @@ -274,7 +274,7 @@ module Arty_Z7_20_processing_system7_0_0 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WID" *) input [5:0]S_AXI_HP0_WID; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WDATA" *) input [63:0]S_AXI_HP0_WDATA; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WSTRB" *) input [7:0]S_AXI_HP0_WSTRB; - (* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *) input [6:0]IRQ_F2P; + (* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *) input [7:0]IRQ_F2P; (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) output FCLK_CLK0; (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK1 CLK" *) output FCLK_CLK1; (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK2 CLK" *) output FCLK_CLK2; @@ -339,7 +339,7 @@ module Arty_Z7_20_processing_system7_0_0 wire I2C1_SDA_I; wire I2C1_SDA_O; wire I2C1_SDA_T; - wire [6:0]IRQ_F2P; + wire [7:0]IRQ_F2P; wire [53:0]MIO; wire M_AXI_GP0_ACLK; wire [31:0]M_AXI_GP0_ARADDR; @@ -861,7 +861,7 @@ PULLUP pullup_MIO_53 (* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP1_ID_WIDTH = "12" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *) - (* C_NUM_F2P_INTR_INPUTS = "7" *) + (* C_NUM_F2P_INTR_INPUTS = "8" *) (* C_PACKAGE_NAME = "clg400" *) (* C_PS7_SI_REV = "PRODUCTION" *) (* C_S_AXI_ACP_ARUSER_VAL = "31" *) @@ -1591,7 +1591,7 @@ endmodule (* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "54" *) (* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP0_ID_WIDTH = "12" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *) (* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP1_ID_WIDTH = "12" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *) -(* C_NUM_F2P_INTR_INPUTS = "7" *) (* C_PACKAGE_NAME = "clg400" *) (* C_PS7_SI_REV = "PRODUCTION" *) +(* C_NUM_F2P_INTR_INPUTS = "8" *) (* C_PACKAGE_NAME = "clg400" *) (* C_PS7_SI_REV = "PRODUCTION" *) (* C_S_AXI_ACP_ARUSER_VAL = "31" *) (* C_S_AXI_ACP_AWUSER_VAL = "31" *) (* C_S_AXI_ACP_ID_WIDTH = "3" *) (* C_S_AXI_GP0_ID_WIDTH = "6" *) (* C_S_AXI_GP1_ID_WIDTH = "6" *) (* C_S_AXI_HP0_DATA_WIDTH = "64" *) (* C_S_AXI_HP0_ID_WIDTH = "6" *) (* C_S_AXI_HP1_DATA_WIDTH = "64" *) (* C_S_AXI_HP1_ID_WIDTH = "6" *) @@ -2872,7 +2872,7 @@ module Arty_Z7_20_processing_system7_0_0_processing_system7_v5_5_processing_syst output IRQ_P2F_SPI1; output IRQ_P2F_UART1; output IRQ_P2F_CAN1; - input [6:0]IRQ_F2P; + input [7:0]IRQ_F2P; input Core0_nFIQ; input Core0_nIRQ; input Core1_nFIQ; @@ -3126,7 +3126,7 @@ module Arty_Z7_20_processing_system7_0_0_processing_system7_v5_5_processing_syst wire I2C1_SDA_O; wire I2C1_SDA_T; wire I2C1_SDA_T_n; - wire [6:0]IRQ_F2P; + wire [7:0]IRQ_F2P; wire IRQ_P2F_CAN0; wire IRQ_P2F_CAN1; wire IRQ_P2F_CTI; @@ -4072,7 +4072,7 @@ module Arty_Z7_20_processing_system7_0_0_processing_system7_v5_5_processing_syst .FTMTP2FDEBUG(FTMT_P2F_DEBUG), .FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}), .FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}), - .IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}), + .IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}), .IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}), .MAXIGP0ACLK(M_AXI_GP0_ACLK), .MAXIGP0ARADDR(M_AXI_GP0_ARADDR), diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0_sim_netlist.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0_sim_netlist.vhdl index c7abb99..f6b7bb6 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0_sim_netlist.vhdl +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0_sim_netlist.vhdl @@ -1,7 +1,7 @@ -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 --- Date : Mon Feb 27 10:06:33 2017 +-- Date : Sun Mar 05 18:57:19 2017 -- Host : WK73 running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim -- C:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0_sim_netlist.vhdl @@ -599,7 +599,7 @@ entity Arty_Z7_20_processing_system7_0_0_processing_system7_v5_5_processing_syst IRQ_P2F_SPI1 : out STD_LOGIC; IRQ_P2F_UART1 : out STD_LOGIC; IRQ_P2F_CAN1 : out STD_LOGIC; - IRQ_F2P : in STD_LOGIC_VECTOR ( 6 downto 0 ); + IRQ_F2P : in STD_LOGIC_VECTOR ( 7 downto 0 ); Core0_nFIQ : in STD_LOGIC; Core0_nIRQ : in STD_LOGIC; Core1_nFIQ : in STD_LOGIC; @@ -751,7 +751,7 @@ entity Arty_Z7_20_processing_system7_0_0_processing_system7_v5_5_processing_syst attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP1_THREAD_ID_WIDTH of Arty_Z7_20_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_NUM_F2P_INTR_INPUTS : integer; - attribute C_NUM_F2P_INTR_INPUTS of Arty_Z7_20_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 7; + attribute C_NUM_F2P_INTR_INPUTS of Arty_Z7_20_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 8; attribute C_PACKAGE_NAME : string; attribute C_PACKAGE_NAME of Arty_Z7_20_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "clg400"; attribute C_PS7_SI_REV : string; @@ -1502,8 +1502,8 @@ PS7_i: unisim.vcomponents.PS7 IRQF2P(18) => Core0_nFIQ, IRQF2P(17) => Core1_nIRQ, IRQF2P(16) => Core0_nIRQ, - IRQF2P(15 downto 7) => B"000000000", - IRQF2P(6 downto 0) => IRQ_F2P(6 downto 0), + IRQF2P(15 downto 8) => B"00000000", + IRQF2P(7 downto 0) => IRQ_F2P(7 downto 0), IRQP2F(28) => IRQ_P2F_DMAC_ABORT, IRQP2F(27) => IRQ_P2F_DMAC7, IRQP2F(26) => IRQ_P2F_DMAC6, @@ -2998,7 +2998,7 @@ entity Arty_Z7_20_processing_system7_0_0 is S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); - IRQ_F2P : in STD_LOGIC_VECTOR ( 6 downto 0 ); + IRQ_F2P : in STD_LOGIC_VECTOR ( 7 downto 0 ); FCLK_CLK0 : out STD_LOGIC; FCLK_CLK1 : out STD_LOGIC; FCLK_CLK2 : out STD_LOGIC; @@ -3339,7 +3339,7 @@ architecture STRUCTURE of Arty_Z7_20_processing_system7_0_0 is attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12; attribute C_NUM_F2P_INTR_INPUTS : integer; - attribute C_NUM_F2P_INTR_INPUTS of inst : label is 7; + attribute C_NUM_F2P_INTR_INPUTS of inst : label is 8; attribute C_PACKAGE_NAME : string; attribute C_PACKAGE_NAME of inst : label is "clg400"; attribute C_PS7_SI_REV : string; @@ -3851,7 +3851,7 @@ inst: entity work.Arty_Z7_20_processing_system7_0_0_processing_system7_v5_5_proc I2C1_SDA_I => I2C1_SDA_I, I2C1_SDA_O => I2C1_SDA_O, I2C1_SDA_T => I2C1_SDA_T, - IRQ_F2P(6 downto 0) => IRQ_F2P(6 downto 0), + IRQ_F2P(7 downto 0) => IRQ_F2P(7 downto 0), IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED, IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED, IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED, diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0_stub.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0_stub.v index e18e105..6c0b412 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0_stub.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0_stub.v @@ -1,7 +1,7 @@ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -// Date : Mon Feb 27 10:06:33 2017 +// Date : Sun Mar 05 18:57:19 2017 // Host : WK73 running 64-bit Service Pack 1 (build 7601) // Command : write_verilog -force -mode synth_stub // C:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0_stub.v @@ -41,7 +41,7 @@ module Arty_Z7_20_processing_system7_0_0(GPIO_I, GPIO_O, GPIO_T, I2C0_SDA_I, I2C DDR_CAS_n, DDR_CKE, DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB) -/* synthesis syn_black_box black_box_pad_pin="GPIO_I[5:0],GPIO_O[5:0],GPIO_T[5:0],I2C0_SDA_I,I2C0_SDA_O,I2C0_SDA_T,I2C0_SCL_I,I2C0_SCL_O,I2C0_SCL_T,I2C1_SDA_I,I2C1_SDA_O,I2C1_SDA_T,I2C1_SCL_I,I2C1_SCL_O,I2C1_SCL_T,SPI0_SCLK_I,SPI0_SCLK_O,SPI0_SCLK_T,SPI0_MOSI_I,SPI0_MOSI_O,SPI0_MOSI_T,SPI0_MISO_I,SPI0_MISO_O,SPI0_MISO_T,SPI0_SS_I,SPI0_SS_O,SPI0_SS1_O,SPI0_SS2_O,SPI0_SS_T,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],S_AXI_HP0_ARREADY,S_AXI_HP0_AWREADY,S_AXI_HP0_BVALID,S_AXI_HP0_RLAST,S_AXI_HP0_RVALID,S_AXI_HP0_WREADY,S_AXI_HP0_BRESP[1:0],S_AXI_HP0_RRESP[1:0],S_AXI_HP0_BID[5:0],S_AXI_HP0_RID[5:0],S_AXI_HP0_RDATA[63:0],S_AXI_HP0_RCOUNT[7:0],S_AXI_HP0_WCOUNT[7:0],S_AXI_HP0_RACOUNT[2:0],S_AXI_HP0_WACOUNT[5:0],S_AXI_HP0_ACLK,S_AXI_HP0_ARVALID,S_AXI_HP0_AWVALID,S_AXI_HP0_BREADY,S_AXI_HP0_RDISSUECAP1_EN,S_AXI_HP0_RREADY,S_AXI_HP0_WLAST,S_AXI_HP0_WRISSUECAP1_EN,S_AXI_HP0_WVALID,S_AXI_HP0_ARBURST[1:0],S_AXI_HP0_ARLOCK[1:0],S_AXI_HP0_ARSIZE[2:0],S_AXI_HP0_AWBURST[1:0],S_AXI_HP0_AWLOCK[1:0],S_AXI_HP0_AWSIZE[2:0],S_AXI_HP0_ARPROT[2:0],S_AXI_HP0_AWPROT[2:0],S_AXI_HP0_ARADDR[31:0],S_AXI_HP0_AWADDR[31:0],S_AXI_HP0_ARCACHE[3:0],S_AXI_HP0_ARLEN[3:0],S_AXI_HP0_ARQOS[3:0],S_AXI_HP0_AWCACHE[3:0],S_AXI_HP0_AWLEN[3:0],S_AXI_HP0_AWQOS[3:0],S_AXI_HP0_ARID[5:0],S_AXI_HP0_AWID[5:0],S_AXI_HP0_WID[5:0],S_AXI_HP0_WDATA[63:0],S_AXI_HP0_WSTRB[7:0],IRQ_F2P[6:0],FCLK_CLK0,FCLK_CLK1,FCLK_CLK2,FCLK_CLK3,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */; +/* synthesis syn_black_box black_box_pad_pin="GPIO_I[5:0],GPIO_O[5:0],GPIO_T[5:0],I2C0_SDA_I,I2C0_SDA_O,I2C0_SDA_T,I2C0_SCL_I,I2C0_SCL_O,I2C0_SCL_T,I2C1_SDA_I,I2C1_SDA_O,I2C1_SDA_T,I2C1_SCL_I,I2C1_SCL_O,I2C1_SCL_T,SPI0_SCLK_I,SPI0_SCLK_O,SPI0_SCLK_T,SPI0_MOSI_I,SPI0_MOSI_O,SPI0_MOSI_T,SPI0_MISO_I,SPI0_MISO_O,SPI0_MISO_T,SPI0_SS_I,SPI0_SS_O,SPI0_SS1_O,SPI0_SS2_O,SPI0_SS_T,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],S_AXI_HP0_ARREADY,S_AXI_HP0_AWREADY,S_AXI_HP0_BVALID,S_AXI_HP0_RLAST,S_AXI_HP0_RVALID,S_AXI_HP0_WREADY,S_AXI_HP0_BRESP[1:0],S_AXI_HP0_RRESP[1:0],S_AXI_HP0_BID[5:0],S_AXI_HP0_RID[5:0],S_AXI_HP0_RDATA[63:0],S_AXI_HP0_RCOUNT[7:0],S_AXI_HP0_WCOUNT[7:0],S_AXI_HP0_RACOUNT[2:0],S_AXI_HP0_WACOUNT[5:0],S_AXI_HP0_ACLK,S_AXI_HP0_ARVALID,S_AXI_HP0_AWVALID,S_AXI_HP0_BREADY,S_AXI_HP0_RDISSUECAP1_EN,S_AXI_HP0_RREADY,S_AXI_HP0_WLAST,S_AXI_HP0_WRISSUECAP1_EN,S_AXI_HP0_WVALID,S_AXI_HP0_ARBURST[1:0],S_AXI_HP0_ARLOCK[1:0],S_AXI_HP0_ARSIZE[2:0],S_AXI_HP0_AWBURST[1:0],S_AXI_HP0_AWLOCK[1:0],S_AXI_HP0_AWSIZE[2:0],S_AXI_HP0_ARPROT[2:0],S_AXI_HP0_AWPROT[2:0],S_AXI_HP0_ARADDR[31:0],S_AXI_HP0_AWADDR[31:0],S_AXI_HP0_ARCACHE[3:0],S_AXI_HP0_ARLEN[3:0],S_AXI_HP0_ARQOS[3:0],S_AXI_HP0_AWCACHE[3:0],S_AXI_HP0_AWLEN[3:0],S_AXI_HP0_AWQOS[3:0],S_AXI_HP0_ARID[5:0],S_AXI_HP0_AWID[5:0],S_AXI_HP0_WID[5:0],S_AXI_HP0_WDATA[63:0],S_AXI_HP0_WSTRB[7:0],IRQ_F2P[7:0],FCLK_CLK0,FCLK_CLK1,FCLK_CLK2,FCLK_CLK3,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */; input [5:0]GPIO_I; output [5:0]GPIO_O; output [5:0]GPIO_T; @@ -158,7 +158,7 @@ module Arty_Z7_20_processing_system7_0_0(GPIO_I, GPIO_O, GPIO_T, I2C0_SDA_I, I2C input [5:0]S_AXI_HP0_WID; input [63:0]S_AXI_HP0_WDATA; input [7:0]S_AXI_HP0_WSTRB; - input [6:0]IRQ_F2P; + input [7:0]IRQ_F2P; output FCLK_CLK0; output FCLK_CLK1; output FCLK_CLK2; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0_stub.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0_stub.vhdl index dc171fb..9ad6304 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0_stub.vhdl +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0_stub.vhdl @@ -1,7 +1,7 @@ -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 --- Date : Mon Feb 27 10:06:33 2017 +-- Date : Sun Mar 05 18:57:19 2017 -- Host : WK73 running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode synth_stub -- C:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/Arty_Z7_20_processing_system7_0_0_stub.vhdl @@ -130,7 +130,7 @@ entity Arty_Z7_20_processing_system7_0_0 is S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); - IRQ_F2P : in STD_LOGIC_VECTOR ( 6 downto 0 ); + IRQ_F2P : in STD_LOGIC_VECTOR ( 7 downto 0 ); FCLK_CLK0 : out STD_LOGIC; FCLK_CLK1 : out STD_LOGIC; FCLK_CLK2 : out STD_LOGIC; @@ -165,7 +165,7 @@ architecture stub of Arty_Z7_20_processing_system7_0_0 is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "GPIO_I[5:0],GPIO_O[5:0],GPIO_T[5:0],I2C0_SDA_I,I2C0_SDA_O,I2C0_SDA_T,I2C0_SCL_I,I2C0_SCL_O,I2C0_SCL_T,I2C1_SDA_I,I2C1_SDA_O,I2C1_SDA_T,I2C1_SCL_I,I2C1_SCL_O,I2C1_SCL_T,SPI0_SCLK_I,SPI0_SCLK_O,SPI0_SCLK_T,SPI0_MOSI_I,SPI0_MOSI_O,SPI0_MOSI_T,SPI0_MISO_I,SPI0_MISO_O,SPI0_MISO_T,SPI0_SS_I,SPI0_SS_O,SPI0_SS1_O,SPI0_SS2_O,SPI0_SS_T,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],S_AXI_HP0_ARREADY,S_AXI_HP0_AWREADY,S_AXI_HP0_BVALID,S_AXI_HP0_RLAST,S_AXI_HP0_RVALID,S_AXI_HP0_WREADY,S_AXI_HP0_BRESP[1:0],S_AXI_HP0_RRESP[1:0],S_AXI_HP0_BID[5:0],S_AXI_HP0_RID[5:0],S_AXI_HP0_RDATA[63:0],S_AXI_HP0_RCOUNT[7:0],S_AXI_HP0_WCOUNT[7:0],S_AXI_HP0_RACOUNT[2:0],S_AXI_HP0_WACOUNT[5:0],S_AXI_HP0_ACLK,S_AXI_HP0_ARVALID,S_AXI_HP0_AWVALID,S_AXI_HP0_BREADY,S_AXI_HP0_RDISSUECAP1_EN,S_AXI_HP0_RREADY,S_AXI_HP0_WLAST,S_AXI_HP0_WRISSUECAP1_EN,S_AXI_HP0_WVALID,S_AXI_HP0_ARBURST[1:0],S_AXI_HP0_ARLOCK[1:0],S_AXI_HP0_ARSIZE[2:0],S_AXI_HP0_AWBURST[1:0],S_AXI_HP0_AWLOCK[1:0],S_AXI_HP0_AWSIZE[2:0],S_AXI_HP0_ARPROT[2:0],S_AXI_HP0_AWPROT[2:0],S_AXI_HP0_ARADDR[31:0],S_AXI_HP0_AWADDR[31:0],S_AXI_HP0_ARCACHE[3:0],S_AXI_HP0_ARLEN[3:0],S_AXI_HP0_ARQOS[3:0],S_AXI_HP0_AWCACHE[3:0],S_AXI_HP0_AWLEN[3:0],S_AXI_HP0_AWQOS[3:0],S_AXI_HP0_ARID[5:0],S_AXI_HP0_AWID[5:0],S_AXI_HP0_WID[5:0],S_AXI_HP0_WDATA[63:0],S_AXI_HP0_WSTRB[7:0],IRQ_F2P[6:0],FCLK_CLK0,FCLK_CLK1,FCLK_CLK2,FCLK_CLK3,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB"; +attribute black_box_pad_pin of stub : architecture is "GPIO_I[5:0],GPIO_O[5:0],GPIO_T[5:0],I2C0_SDA_I,I2C0_SDA_O,I2C0_SDA_T,I2C0_SCL_I,I2C0_SCL_O,I2C0_SCL_T,I2C1_SDA_I,I2C1_SDA_O,I2C1_SDA_T,I2C1_SCL_I,I2C1_SCL_O,I2C1_SCL_T,SPI0_SCLK_I,SPI0_SCLK_O,SPI0_SCLK_T,SPI0_MOSI_I,SPI0_MOSI_O,SPI0_MOSI_T,SPI0_MISO_I,SPI0_MISO_O,SPI0_MISO_T,SPI0_SS_I,SPI0_SS_O,SPI0_SS1_O,SPI0_SS2_O,SPI0_SS_T,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],S_AXI_HP0_ARREADY,S_AXI_HP0_AWREADY,S_AXI_HP0_BVALID,S_AXI_HP0_RLAST,S_AXI_HP0_RVALID,S_AXI_HP0_WREADY,S_AXI_HP0_BRESP[1:0],S_AXI_HP0_RRESP[1:0],S_AXI_HP0_BID[5:0],S_AXI_HP0_RID[5:0],S_AXI_HP0_RDATA[63:0],S_AXI_HP0_RCOUNT[7:0],S_AXI_HP0_WCOUNT[7:0],S_AXI_HP0_RACOUNT[2:0],S_AXI_HP0_WACOUNT[5:0],S_AXI_HP0_ACLK,S_AXI_HP0_ARVALID,S_AXI_HP0_AWVALID,S_AXI_HP0_BREADY,S_AXI_HP0_RDISSUECAP1_EN,S_AXI_HP0_RREADY,S_AXI_HP0_WLAST,S_AXI_HP0_WRISSUECAP1_EN,S_AXI_HP0_WVALID,S_AXI_HP0_ARBURST[1:0],S_AXI_HP0_ARLOCK[1:0],S_AXI_HP0_ARSIZE[2:0],S_AXI_HP0_AWBURST[1:0],S_AXI_HP0_AWLOCK[1:0],S_AXI_HP0_AWSIZE[2:0],S_AXI_HP0_ARPROT[2:0],S_AXI_HP0_AWPROT[2:0],S_AXI_HP0_ARADDR[31:0],S_AXI_HP0_AWADDR[31:0],S_AXI_HP0_ARCACHE[3:0],S_AXI_HP0_ARLEN[3:0],S_AXI_HP0_ARQOS[3:0],S_AXI_HP0_AWCACHE[3:0],S_AXI_HP0_AWLEN[3:0],S_AXI_HP0_AWQOS[3:0],S_AXI_HP0_ARID[5:0],S_AXI_HP0_AWID[5:0],S_AXI_HP0_WID[5:0],S_AXI_HP0_WDATA[63:0],S_AXI_HP0_WSTRB[7:0],IRQ_F2P[7:0],FCLK_CLK0,FCLK_CLK1,FCLK_CLK2,FCLK_CLK3,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2016.4"; begin diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/hdl/verilog/Arty_Z7_20_processing_system7_0_0.hwdef b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/hdl/verilog/Arty_Z7_20_processing_system7_0_0.hwdef index 2805241..8e1ce42 100644 Binary files a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/hdl/verilog/Arty_Z7_20_processing_system7_0_0.hwdef and b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/hdl/verilog/Arty_Z7_20_processing_system7_0_0.hwdef differ diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v index 15568f6..9028682 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v @@ -151,10 +151,10 @@ //------------------------------------------------------------------------------ (*POWER= "/>" *) (* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=525, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=15, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=48.91, PCW_UIPARAM_DDR_T_RAS_MIN=35.0, PCW_UIPARAM_DDR_T_FAW=40.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.040, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.058, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=-0.009, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=-0.033, PCW_UIPARAM_DDR_BOARD_DELAY0=0.223, PCW_UIPARAM_DDR_BOARD_DELAY1=0.212, PCW_UIPARAM_DDR_BOARD_DELAY2=0.085, PCW_UIPARAM_DDR_BOARD_DELAY3=0.092, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=15.6, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=18.8, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=16.5, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=18, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=25.8, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=25.8, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=105.056, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=66.904, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=89.1715, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=113.63, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=98.503, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=68.5855, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=90.295, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=103.977, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=80.4535, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=80.4535, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=80.4535, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=80.4535, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160\ -, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=50, PCW_APU_PERIPHERAL_FREQMHZ=650, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=100, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100, PCW_FPGA1_PERIPHERAL_FREQMHZ=142, PCW_FPGA2_PERIPHERAL_FREQMHZ=75, PCW_FPGA3_PERIPHERAL_FREQMHZ=50, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=26, PCW_IOPLL_CTRL_FBDIV=20, PCW_DDRPLL_CTRL_FBDIV=21, PCW_CPU_CPU_PLL_FREQMHZ=1300.000, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1050.000, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=1, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=10\ +, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=50, PCW_APU_PERIPHERAL_FREQMHZ=650, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=100, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100, PCW_FPGA1_PERIPHERAL_FREQMHZ=120, PCW_FPGA2_PERIPHERAL_FREQMHZ=75, PCW_FPGA3_PERIPHERAL_FREQMHZ=50, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=26, PCW_IOPLL_CTRL_FBDIV=20, PCW_DDRPLL_CTRL_FBDIV=21, PCW_CPU_CPU_PLL_FREQMHZ=1300.000, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1050.000, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=1, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=10\ , PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=10, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3, PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=16 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41J256M16 RE-125, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=4096 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=0, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0\ , PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=1, PCW_QSPI_GRP_FBCLK_IO=MIO 8, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=1, PCW_ENET0_RESET_IO=MIO 9, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=1, PCW_SD0_SD0_IO=MIO 40 .. 45, PCW_SD0_GRP_CD_ENABLE=1, PCW_SD0_GRP_CD_IO=MIO 47, PCW_SD0_GRP_WP_ENABLE=0, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=1, PCW_UART0_UART0_IO=MIO 14 .. 15, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=0, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=1, PCW_SPI0_SPI0_IO=EMIO, PCW_SPI0_GRP_SS0_ENABLE=1, PCW_SPI0_GRP_SS0_IO=EMIO, PCW_SPI0_GRP_SS1_ENABLE=1, PCW_SPI0_GRP_SS1_IO=EMIO, PCW_SPI0_GRP_SS2_ENABLE=1, PCW_SPI0_GRP_SS2_IO=EMIO, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0\ -, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=0, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=1, PCW_USB0_RESET_IO=MIO 46, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=1, PCW_I2C0_I2C0_IO=EMIO, PCW_I2C0_GRP_INT_ENABLE=1, PCW_I2C0_GRP_INT_IO=EMIO, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=1, PCW_I2C1_I2C1_IO=EMIO, PCW_I2C1_GRP_INT_ENABLE=1, PCW_I2C1_GRP_INT_IO=EMIO, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=0, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=1, PCW_GPIO_EMIO_GPIO_IO=6, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External\ +, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=0, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=1, PCW_USB0_RESET_IO=MIO 46, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=1, PCW_I2C0_I2C0_IO=EMIO, PCW_I2C0_GRP_INT_ENABLE=1, PCW_I2C0_GRP_INT_IO=EMIO, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=1, PCW_I2C1_I2C1_IO=EMIO, PCW_I2C1_GRP_INT_ENABLE=1, PCW_I2C1_GRP_INT_IO=EMIO, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=0, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=1, PCW_GPIO_EMIO_GPIO_IO=6, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=ARM PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External\ , PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=1, PCW_FPGA_FCLK2_ENABLE=1, PCW_FPGA_FCLK3_ENABLE=1, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=11, PCW_NOR_SRAM_CS0_T_RC=11, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=11, PCW_NOR_SRAM_CS1_T_RC=11, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=11, PCW_NOR_CS0_T_RC=11, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=11, PCW_NOR_CS1_T_RC=11, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=11\ , PCW_NAND_CYCLES_T_RC=11 }" *) (* HW_HANDOFF = "Arty_Z7_20_processing_system7_0_0.hwdef" *) diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/ps7_init.c b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/ps7_init.c index 78f325d..2d7a45d 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/ps7_init.c +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/ps7_init.c @@ -383,17 +383,17 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U // .. .. EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000180[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x7 - // .. .. ==> 0XF8000180[13:8] = 0x00000007U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U + // .. .. SRCSEL = 0x2 + // .. .. ==> 0XF8000180[5:4] = 0x00000002U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000020U + // .. .. DIVISOR0 = 0xb + // .. .. ==> 0XF8000180[13:8] = 0x0000000BU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000B00U // .. .. DIVISOR1 = 0x1 // .. .. ==> 0XF8000180[25:20] = 0x00000001U // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U // .. .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U), + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100B20U), // .. .. SRCSEL = 0x0 // .. .. ==> 0XF8000190[5:4] = 0x00000000U // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U @@ -4580,17 +4580,17 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U // .. .. EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000180[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x7 - // .. .. ==> 0XF8000180[13:8] = 0x00000007U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U + // .. .. SRCSEL = 0x2 + // .. .. ==> 0XF8000180[5:4] = 0x00000002U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000020U + // .. .. DIVISOR0 = 0xb + // .. .. ==> 0XF8000180[13:8] = 0x0000000BU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000B00U // .. .. DIVISOR1 = 0x1 // .. .. ==> 0XF8000180[25:20] = 0x00000001U // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U // .. .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U), + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100B20U), // .. .. SRCSEL = 0x0 // .. .. ==> 0XF8000190[5:4] = 0x00000000U // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U @@ -8930,17 +8930,17 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U // .. .. EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000180[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x7 - // .. .. ==> 0XF8000180[13:8] = 0x00000007U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U + // .. .. SRCSEL = 0x2 + // .. .. ==> 0XF8000180[5:4] = 0x00000002U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000020U + // .. .. DIVISOR0 = 0xb + // .. .. ==> 0XF8000180[13:8] = 0x0000000BU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000B00U // .. .. DIVISOR1 = 0x1 // .. .. ==> 0XF8000180[25:20] = 0x00000001U // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U // .. .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U), + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100B20U), // .. .. SRCSEL = 0x0 // .. .. ==> 0XF8000190[5:4] = 0x00000000U // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/ps7_init.h b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/ps7_init.h index 82bc39c..c766366 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/ps7_init.h +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/ps7_init.h @@ -109,7 +109,7 @@ extern unsigned long * ps7_peripherals_init_data; #define PCAP_FREQ 200000000 #define TPIU_FREQ 200000000 #define FPGA0_FREQ 100000000 -#define FPGA1_FREQ 142857132 +#define FPGA1_FREQ 118181816 #define FPGA2_FREQ 76923080 #define FPGA3_FREQ 50000000 diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/ps7_init.html b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/ps7_init.html index d2a8ea5..a8efd79 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/ps7_init.html +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/ps7_init.html @@ -1875,10 +1875,10 @@

PS Reference Clock : 50

FPGA1 Freq (MHz) -IO PLL +ARM PLL -142.857132 +118.181816 @@ -7402,10 +7402,10 @@

Register ( slcr )FPGA1_CLK_ 30 -0 +2 -0 +20 Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. @@ -7422,10 +7422,10 @@

Register ( slcr )FPGA1_CLK_ 3f00 -7 +b -700 +b00 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. @@ -7465,7 +7465,7 @@

Register ( slcr )FPGA1_CLK_ -100700 +100b20 PL Clock 1 Output control @@ -54235,10 +54235,10 @@

Register ( slcr )FPGA1_CLK_ 30 -0 +2 -0 +20 Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. @@ -54255,10 +54255,10 @@

Register ( slcr )FPGA1_CLK_ 3f00 -7 +b -700 +b00 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. @@ -54298,7 +54298,7 @@

Register ( slcr )FPGA1_CLK_ -100700 +100b20 PL Clock 1 Output control @@ -102196,10 +102196,10 @@

Register ( slcr )FPGA1_CLK_ 30 -0 +2 -0 +20 Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. @@ -102216,10 +102216,10 @@

Register ( slcr )FPGA1_CLK_ 3f00 -7 +b -700 +b00 Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider @@ -102259,7 +102259,7 @@

Register ( slcr )FPGA1_CLK_ -100700 +100b20 FPGA 1 Output Clock Control diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/ps7_init.tcl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/ps7_init.tcl index 2b51751..9ae98b3 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/ps7_init.tcl +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/ps7_init.tcl @@ -36,7 +36,7 @@ proc ps7_clock_init_data_3_0 {} { mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000170 0x03F03F30 0x00200500 - mask_write 0XF8000180 0x03F03F30 0x00100700 + mask_write 0XF8000180 0x03F03F30 0x00100B20 mask_write 0XF8000190 0x03F03F30 0x00100D00 mask_write 0XF80001A0 0x03F03F30 0x00400500 mask_write 0XF80001C4 0x00000001 0x00000001 @@ -280,7 +280,7 @@ proc ps7_clock_init_data_2_0 {} { mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000170 0x03F03F30 0x00200500 - mask_write 0XF8000180 0x03F03F30 0x00100700 + mask_write 0XF8000180 0x03F03F30 0x00100B20 mask_write 0XF8000190 0x03F03F30 0x00100D00 mask_write 0XF80001A0 0x03F03F30 0x00400500 mask_write 0XF80001C4 0x00000001 0x00000001 @@ -525,7 +525,7 @@ proc ps7_clock_init_data_1_0 {} { mask_write 0XF8000158 0x00003F33 0x00000601 mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000170 0x03F03F30 0x00200500 - mask_write 0XF8000180 0x03F03F30 0x00100700 + mask_write 0XF8000180 0x03F03F30 0x00100B20 mask_write 0XF8000190 0x03F03F30 0x00100D00 mask_write 0XF80001A0 0x03F03F30 0x00400500 mask_write 0XF80001C4 0x00000001 0x00000001 diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/ps7_init_gpl.c b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/ps7_init_gpl.c index 443ff7a..da8e010 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/ps7_init_gpl.c +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/ps7_init_gpl.c @@ -374,17 +374,17 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U // .. .. EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000180[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x7 - // .. .. ==> 0XF8000180[13:8] = 0x00000007U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U + // .. .. SRCSEL = 0x2 + // .. .. ==> 0XF8000180[5:4] = 0x00000002U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000020U + // .. .. DIVISOR0 = 0xb + // .. .. ==> 0XF8000180[13:8] = 0x0000000BU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000B00U // .. .. DIVISOR1 = 0x1 // .. .. ==> 0XF8000180[25:20] = 0x00000001U // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U // .. .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U), + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100B20U), // .. .. SRCSEL = 0x0 // .. .. ==> 0XF8000190[5:4] = 0x00000000U // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U @@ -4571,17 +4571,17 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U // .. .. EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000180[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x7 - // .. .. ==> 0XF8000180[13:8] = 0x00000007U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U + // .. .. SRCSEL = 0x2 + // .. .. ==> 0XF8000180[5:4] = 0x00000002U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000020U + // .. .. DIVISOR0 = 0xb + // .. .. ==> 0XF8000180[13:8] = 0x0000000BU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000B00U // .. .. DIVISOR1 = 0x1 // .. .. ==> 0XF8000180[25:20] = 0x00000001U // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U // .. .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U), + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100B20U), // .. .. SRCSEL = 0x0 // .. .. ==> 0XF8000190[5:4] = 0x00000000U // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U @@ -8921,17 +8921,17 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U // .. .. EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000180[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x7 - // .. .. ==> 0XF8000180[13:8] = 0x00000007U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U + // .. .. SRCSEL = 0x2 + // .. .. ==> 0XF8000180[5:4] = 0x00000002U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000020U + // .. .. DIVISOR0 = 0xb + // .. .. ==> 0XF8000180[13:8] = 0x0000000BU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000B00U // .. .. DIVISOR1 = 0x1 // .. .. ==> 0XF8000180[25:20] = 0x00000001U // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U // .. .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U), + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100B20U), // .. .. SRCSEL = 0x0 // .. .. ==> 0XF8000190[5:4] = 0x00000000U // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/ps7_init_gpl.h b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/ps7_init_gpl.h index 82bc39c..c766366 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/ps7_init_gpl.h +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/ps7_init_gpl.h @@ -109,7 +109,7 @@ extern unsigned long * ps7_peripherals_init_data; #define PCAP_FREQ 200000000 #define TPIU_FREQ 200000000 #define FPGA0_FREQ 100000000 -#define FPGA1_FREQ 142857132 +#define FPGA1_FREQ 118181816 #define FPGA2_FREQ 76923080 #define FPGA3_FREQ 50000000 diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/ps7_parameters.xml b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/ps7_parameters.xml index bc78eb8..984ea21 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/ps7_parameters.xml +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/ps7_parameters.xml @@ -79,8 +79,8 @@ - - + + @@ -93,7 +93,7 @@ - + @@ -630,7 +630,7 @@ - + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/sim/Arty_Z7_20_processing_system7_0_0.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/sim/Arty_Z7_20_processing_system7_0_0.v index 290ed9e..d331b36 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/sim/Arty_Z7_20_processing_system7_0_0.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/sim/Arty_Z7_20_processing_system7_0_0.v @@ -316,7 +316,7 @@ input [5 : 0] S_AXI_HP0_AWID; input [5 : 0] S_AXI_HP0_WID; input [63 : 0] S_AXI_HP0_WDATA; input [7 : 0] S_AXI_HP0_WSTRB; -input [6 : 0] IRQ_F2P; +input [7 : 0] IRQ_F2P; output FCLK_CLK0; output FCLK_CLK1; output FCLK_CLK2; @@ -360,7 +360,7 @@ input PS_PORB; .C_S_AXI_HP3_DATA_WIDTH(64), .C_HIGH_OCM_EN(0), .C_FCLK_CLK0_FREQ(100.0), - .C_FCLK_CLK1_FREQ(142.857132), + .C_FCLK_CLK1_FREQ(118.181816), .C_FCLK_CLK2_FREQ(76.92308), .C_FCLK_CLK3_FREQ(50.0), .C_M_AXI_GP0_ENABLE_STATIC_REMAP(0), diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/synth/Arty_Z7_20_processing_system7_0_0.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/synth/Arty_Z7_20_processing_system7_0_0.v index b5f9434..c726a9d 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/synth/Arty_Z7_20_processing_system7_0_0.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_0/synth/Arty_Z7_20_processing_system7_0_0.v @@ -54,7 +54,7 @@ (* CHECK_LICENSE_TYPE = "Arty_Z7_20_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) (* CORE_GENERATION_INFO = "Arty_Z7_20_processing_system7_0_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=6,C_INCLUDE_ACP_TRANS_CHEC\ K=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C_M\ -_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=7,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=1,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_HP0=1,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=TRUE,C_FCLK_CLK1_BUF=TRUE,C_FCLK_CLK2_BUF=TRUE,C_FCLK_CLK3_BUF=TRUE,C_PACKAGE_NAME=clg400,C_GP0_EN_MODIFIABLE_TXN=0,C_GP1_EN_MODIFIABLE\ +_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=8,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=1,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_HP0=1,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=TRUE,C_FCLK_CLK1_BUF=TRUE,C_FCLK_CLK2_BUF=TRUE,C_FCLK_CLK3_BUF=TRUE,C_PACKAGE_NAME=clg400,C_GP0_EN_MODIFIABLE_TXN=0,C_GP1_EN_MODIFIABLE\ _TXN=0}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) module Arty_Z7_20_processing_system7_0_0 ( @@ -436,7 +436,7 @@ input wire [63 : 0] S_AXI_HP0_WDATA; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WSTRB" *) input wire [7 : 0] S_AXI_HP0_WSTRB; (* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *) -input wire [6 : 0] IRQ_F2P; +input wire [7 : 0] IRQ_F2P; (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) output wire FCLK_CLK0; (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK1 CLK" *) @@ -522,7 +522,7 @@ inout wire PS_PORB; .C_S_AXI_HP3_DATA_WIDTH(64), .C_M_AXI_GP0_THREAD_ID_WIDTH(12), .C_M_AXI_GP1_THREAD_ID_WIDTH(12), - .C_NUM_F2P_INTR_INPUTS(7), + .C_NUM_F2P_INTR_INPUTS(8), .C_IRQ_F2P_MODE("DIRECT"), .C_DQ_WIDTH(32), .C_DQS_WIDTH(4), diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_axi_periph_0/Arty_Z7_20_processing_system7_0_axi_periph_0.xci b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_axi_periph_0/Arty_Z7_20_processing_system7_0_axi_periph_0.xci index 9047172..17d45d2 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_axi_periph_0/Arty_Z7_20_processing_system7_0_axi_periph_0.xci +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_axi_periph_0/Arty_Z7_20_processing_system7_0_axi_periph_0.xci @@ -1,356 +1,362 @@ - - xilinx.com - xci - unknown - 1.0 - - - Arty_Z7_20_processing_system7_0_axi_periph_0 - - - Arty_Z7_20_processing_system7_0_axi_periph_0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 9 - 1 - 2 - 2 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 2 - 32 - zynq - digilentinc.com:arty-z7-20:part0:1.0 - xc7z020 - clg400 - VHDL - - MIXED - -1 - - TRUE - TRUE - IP_Integrator_AppCore - 12 - TRUE - . - - ../../ipshared - 2016.4 - GLOBAL - - - - - - - - - - + + xilinx.com + xci + unknown + 1.0 + + + Arty_Z7_20_processing_system7_0_axi_periph_0 + + + Arty_Z7_20_processing_system7_0_axi_periph_0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 11 + 1 + 2 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 32 + zynq + digilentinc.com:arty-z7-20:part0:1.0 + xc7z020 + clg400 + VHDL + + MIXED + -1 + + TRUE + TRUE + IP_Integrator_AppCore + 12 + TRUE + . + + ../../ipshared + 2016.4 + GLOBAL + + + + + + + + + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_axi_periph_0/Arty_Z7_20_processing_system7_0_axi_periph_0.xml b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_axi_periph_0/Arty_Z7_20_processing_system7_0_axi_periph_0.xml index b0f32d0..92ec64f 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_axi_periph_0/Arty_Z7_20_processing_system7_0_axi_periph_0.xml +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_processing_system7_0_axi_periph_0/Arty_Z7_20_processing_system7_0_axi_periph_0.xml @@ -1,1642 +1,2945 @@ - - xilinx.com - customized_ip - Arty_Z7_20_processing_system7_0_axi_periph_0 - 1.0 - - - choice_list_40181835 - 32 - 64 - 128 - 256 - 512 - 1024 - - - choice_list_661c4a03 - 2 - 4 - 8 - 16 - 32 - 64 - - - choice_pairs_4873554b - 0 - 1 - - - choice_pairs_76d086ea - 0 - 1 - 2 - - - choice_pairs_ab2668a2 - 0 - 1 - 2 - - - choice_pairs_b6c9535e - 0 - 1 - 3 - 4 - - - The AXI Interconnect IP connects one or more AXI memory-mapped master devices to one or more AXI memory mapped slave devices - - - NUM_SI - Number of Slave Interfaces - 1 - - - NUM_MI - Number of Master Interfaces - 9 - - - STRATEGY - Interconnect Optimization Strategy - 0 - - - ENABLE_ADVANCED_OPTIONS - Enable Advanced Configuration Options - 0 - - - ENABLE_PROTOCOL_CHECKERS - Enable Protocol Checkers and mark interfaces for debug - 0 - - - XBAR_DATA_WIDTH - Data Width of the AXI Crossbar - 32 - - - PCHK_WAITS - Maximum number of idle cycles for READY monitoring - 0 - - - PCHK_MAX_RD_BURSTS - Maximum outstanding READ Transactions per ID - 2 - - - PCHK_MAX_WR_BURSTS - Maximum outstanding WRITE Transactions per ID - 2 - - - SYNCHRONIZATION_STAGES - Synchronization Stages - 2 - - - M00_HAS_REGSLICE - Enable Register Slice on interface M00_AXI - 0 - - - M01_HAS_REGSLICE - Enable Register Slice on interface M01_AXI - 0 - - - M02_HAS_REGSLICE - Enable Register Slice on interface M02_AXI - 0 - - - M03_HAS_REGSLICE - Enable Register Slice on interface M03_AXI - 0 - - - M04_HAS_REGSLICE - Enable Register Slice on interface M04_AXI - 0 - - - M05_HAS_REGSLICE - Enable Register Slice on interface M05_AXI - 0 - - - M06_HAS_REGSLICE - Enable Register Slice on interface M06_AXI - 0 - - - M07_HAS_REGSLICE - Enable Register Slice on interface M07_AXI - 0 - - - M08_HAS_REGSLICE - Enable Register Slice on interface M08_AXI - 0 - - - M09_HAS_REGSLICE - Enable Register Slice on interface M09_AXI - 0 - - - M10_HAS_REGSLICE - Enable Register Slice on interface M10_AXI - 0 - - - M11_HAS_REGSLICE - Enable Register Slice on interface M11_AXI - 0 - - - M12_HAS_REGSLICE - Enable Register Slice on interface M12_AXI - 0 - - - M13_HAS_REGSLICE - Enable Register Slice on interface M13_AXI - 0 - - - M14_HAS_REGSLICE - Enable Register Slice on interface M14_AXI - 0 - - - M15_HAS_REGSLICE - Enable Register Slice on interface M15_AXI - 0 - - - M16_HAS_REGSLICE - Enable Register Slice on interface M16_AXI - 0 - - - M17_HAS_REGSLICE - Enable Register Slice on interface M17_AXI - 0 - - - M18_HAS_REGSLICE - Enable Register Slice on interface M18_AXI - 0 - - - M19_HAS_REGSLICE - Enable Register Slice on interface M19_AXI - 0 - - - M20_HAS_REGSLICE - Enable Register Slice on interface M20_AXI - 0 - - - M21_HAS_REGSLICE - Enable Register Slice on interface M21_AXI - 0 - - - M22_HAS_REGSLICE - Enable Register Slice on interface M22_AXI - 0 - - - M23_HAS_REGSLICE - Enable Register Slice on interface M23_AXI - 0 - - - M24_HAS_REGSLICE - Enable Register Slice on interface M24_AXI - 0 - - - M25_HAS_REGSLICE - Enable Register Slice on interface M25_AXI - 0 - - - M26_HAS_REGSLICE - Enable Register Slice on interface M26_AXI - 0 - - - M27_HAS_REGSLICE - Enable Register Slice on interface M27_AXI - 0 - - - M28_HAS_REGSLICE - Enable Register Slice on interface M28_AXI - 0 - - - M29_HAS_REGSLICE - Enable Register Slice on interface M29_AXI - 0 - - - M30_HAS_REGSLICE - Enable Register Slice on interface M30_AXI - 0 - - - M31_HAS_REGSLICE - Enable Register Slice on interface M31_AXI - 0 - - - M32_HAS_REGSLICE - Enable Register Slice on interface M32_AXI - 0 - - - M33_HAS_REGSLICE - Enable Register Slice on interface M33_AXI - 0 - - - M34_HAS_REGSLICE - Enable Register Slice on interface M34_AXI - 0 - - - M35_HAS_REGSLICE - Enable Register Slice on interface M35_AXI - 0 - - - M36_HAS_REGSLICE - Enable Register Slice on interface M36_AXI - 0 - - - M37_HAS_REGSLICE - Enable Register Slice on interface M37_AXI - 0 - - - M38_HAS_REGSLICE - Enable Register Slice on interface M38_AXI - 0 - - - M39_HAS_REGSLICE - Enable Register Slice on interface M39_AXI - 0 - - - M40_HAS_REGSLICE - Enable Register Slice on interface M40_AXI - 0 - - - M41_HAS_REGSLICE - Enable Register Slice on interface M41_AXI - 0 - - - M42_HAS_REGSLICE - Enable Register Slice on interface M42_AXI - 0 - - - M43_HAS_REGSLICE - Enable Register Slice on interface M43_AXI - 0 - - - M44_HAS_REGSLICE - Enable Register Slice on interface M44_AXI - 0 - - - M45_HAS_REGSLICE - Enable Register Slice on interface M45_AXI - 0 - - - M46_HAS_REGSLICE - Enable Register Slice on interface M46_AXI - 0 - - - M47_HAS_REGSLICE - Enable Register Slice on interface M47_AXI - 0 - - - M48_HAS_REGSLICE - Enable Register Slice on interface M48_AXI - 0 - - - M49_HAS_REGSLICE - Enable Register Slice on interface M49_AXI - 0 - - - M50_HAS_REGSLICE - Enable Register Slice on interface M50_AXI - 0 - - - M51_HAS_REGSLICE - Enable Register Slice on interface M51_AXI - 0 - - - M52_HAS_REGSLICE - Enable Register Slice on interface M52_AXI - 0 - - - M53_HAS_REGSLICE - Enable Register Slice on interface M53_AXI - 0 - - - M54_HAS_REGSLICE - Enable Register Slice on interface M54_AXI - 0 - - - M55_HAS_REGSLICE - Enable Register Slice on interface M55_AXI - 0 - - - M56_HAS_REGSLICE - Enable Register Slice on interface M56_AXI - 0 - - - M57_HAS_REGSLICE - Enable Register Slice on interface M57_AXI - 0 - - - M58_HAS_REGSLICE - Enable Register Slice on interface M58_AXI - 0 - - - M59_HAS_REGSLICE - Enable Register Slice on interface M59_AXI - 0 - - - M60_HAS_REGSLICE - Enable Register Slice on interface M60_AXI - 0 - - - M61_HAS_REGSLICE - Enable Register Slice on interface M61_AXI - 0 - - - M62_HAS_REGSLICE - Enable Register Slice on interface M62_AXI - 0 - - - M63_HAS_REGSLICE - Enable Register Slice on interface M63_AXI - 0 - - - M00_HAS_DATA_FIFO - Enable Data FIFO on interface M00_AXI - 0 - - - M01_HAS_DATA_FIFO - Enable Data FIFO on interface M01_AXI - 0 - - - M02_HAS_DATA_FIFO - Enable Data FIFO on interface M02_AXI - 0 - - - M03_HAS_DATA_FIFO - Enable Data FIFO on interface M03_AXI - 0 - - - M04_HAS_DATA_FIFO - Enable Data FIFO on interface M04_AXI - 0 - - - M05_HAS_DATA_FIFO - Enable Data FIFO on interface M05_AXI - 0 - - - M06_HAS_DATA_FIFO - Enable Data FIFO on interface M06_AXI - 0 - - - M07_HAS_DATA_FIFO - Enable Data FIFO on interface M07_AXI - 0 - - - M08_HAS_DATA_FIFO - Enable Data FIFO on interface M08_AXI - 0 - - - M09_HAS_DATA_FIFO - Enable Data FIFO on interface M09_AXI - 0 - - - M10_HAS_DATA_FIFO - Enable Data FIFO on interface M10_AXI - 0 - - - M11_HAS_DATA_FIFO - Enable Data FIFO on interface M11_AXI - 0 - - - M12_HAS_DATA_FIFO - Enable Data FIFO on interface M12_AXI - 0 - - - M13_HAS_DATA_FIFO - Enable Data FIFO on interface M13_AXI - 0 - - - M14_HAS_DATA_FIFO - Enable Data FIFO on interface M14_AXI - 0 - - - M15_HAS_DATA_FIFO - Enable Data FIFO on interface M15_AXI - 0 - - - M16_HAS_DATA_FIFO - Enable Data FIFO on interface M16_AXI - 0 - - - M17_HAS_DATA_FIFO - Enable Data FIFO on interface M17_AXI - 0 - - - M18_HAS_DATA_FIFO - Enable Data FIFO on interface M18_AXI - 0 - - - M19_HAS_DATA_FIFO - Enable Data FIFO on interface M19_AXI - 0 - - - M20_HAS_DATA_FIFO - Enable Data FIFO on interface M20_AXI - 0 - - - M21_HAS_DATA_FIFO - Enable Data FIFO on interface M21_AXI - 0 - - - M22_HAS_DATA_FIFO - Enable Data FIFO on interface M22_AXI - 0 - - - M23_HAS_DATA_FIFO - Enable Data FIFO on interface M23_AXI - 0 - - - M24_HAS_DATA_FIFO - Enable Data FIFO on interface M24_AXI - 0 - - - M25_HAS_DATA_FIFO - Enable Data FIFO on interface M25_AXI - 0 - - - M26_HAS_DATA_FIFO - Enable Data FIFO on interface M26_AXI - 0 - - - M27_HAS_DATA_FIFO - Enable Data FIFO on interface M27_AXI - 0 - - - M28_HAS_DATA_FIFO - Enable Data FIFO on interface M28_AXI - 0 - - - M29_HAS_DATA_FIFO - Enable Data FIFO on interface M29_AXI - 0 - - - M30_HAS_DATA_FIFO - Enable Data FIFO on interface M30_AXI - 0 - - - M31_HAS_DATA_FIFO - Enable Data FIFO on interface M31_AXI - 0 - - - M32_HAS_DATA_FIFO - Enable Data FIFO on interface M32_AXI - 0 - - - M33_HAS_DATA_FIFO - Enable Data FIFO on interface M33_AXI - 0 - - - M34_HAS_DATA_FIFO - Enable Data FIFO on interface M34_AXI - 0 - - - M35_HAS_DATA_FIFO - Enable Data FIFO on interface M35_AXI - 0 - - - M36_HAS_DATA_FIFO - Enable Data FIFO on interface M36_AXI - 0 - - - M37_HAS_DATA_FIFO - Enable Data FIFO on interface M37_AXI - 0 - - - M38_HAS_DATA_FIFO - Enable Data FIFO on interface M38_AXI - 0 - - - M39_HAS_DATA_FIFO - Enable Data FIFO on interface M39_AXI - 0 - - - M40_HAS_DATA_FIFO - Enable Data FIFO on interface M40_AXI - 0 - - - M41_HAS_DATA_FIFO - Enable Data FIFO on interface M41_AXI - 0 - - - M42_HAS_DATA_FIFO - Enable Data FIFO on interface M42_AXI - 0 - - - M43_HAS_DATA_FIFO - Enable Data FIFO on interface M43_AXI - 0 - - - M44_HAS_DATA_FIFO - Enable Data FIFO on interface M44_AXI - 0 - - - M45_HAS_DATA_FIFO - Enable Data FIFO on interface M45_AXI - 0 - - - M46_HAS_DATA_FIFO - Enable Data FIFO on interface M46_AXI - 0 - - - M47_HAS_DATA_FIFO - Enable Data FIFO on interface M47_AXI - 0 - - - M48_HAS_DATA_FIFO - Enable Data FIFO on interface M48_AXI - 0 - - - M49_HAS_DATA_FIFO - Enable Data FIFO on interface M49_AXI - 0 - - - M50_HAS_DATA_FIFO - Enable Data FIFO on interface M50_AXI - 0 - - - M51_HAS_DATA_FIFO - Enable Data FIFO on interface M51_AXI - 0 - - - M52_HAS_DATA_FIFO - Enable Data FIFO on interface M52_AXI - 0 - - - M53_HAS_DATA_FIFO - Enable Data FIFO on interface M53_AXI - 0 - - - M54_HAS_DATA_FIFO - Enable Data FIFO on interface M54_AXI - 0 - - - M55_HAS_DATA_FIFO - Enable Data FIFO on interface M55_AXI - 0 - - - M56_HAS_DATA_FIFO - Enable Data FIFO on interface M56_AXI - 0 - - - M57_HAS_DATA_FIFO - Enable Data FIFO on interface M57_AXI - 0 - - - M58_HAS_DATA_FIFO - Enable Data FIFO on interface M58_AXI - 0 - - - M59_HAS_DATA_FIFO - Enable Data FIFO on interface M59_AXI - 0 - - - M60_HAS_DATA_FIFO - Enable Data FIFO on interface M60_AXI - 0 - - - M61_HAS_DATA_FIFO - Enable Data FIFO on interface M61_AXI - 0 - - - M62_HAS_DATA_FIFO - Enable Data FIFO on interface M62_AXI - 0 - - - M63_HAS_DATA_FIFO - Enable Data FIFO on interface M63_AXI - 0 - - - S00_HAS_REGSLICE - Enable Register Slice on interface S00_AXI - 0 - - - S01_HAS_REGSLICE - Enable Register Slice on interface S01_AXI - 0 - - - S02_HAS_REGSLICE - Enable Register Slice on interface S02_AXI - 0 - - - S03_HAS_REGSLICE - Enable Register Slice on interface S03_AXI - 0 - - - S04_HAS_REGSLICE - Enable Register Slice on interface S04_AXI - 0 - - - S05_HAS_REGSLICE - Enable Register Slice on interface S05_AXI - 0 - - - S06_HAS_REGSLICE - Enable Register Slice on interface S06_AXI - 0 - - - S07_HAS_REGSLICE - Enable Register Slice on interface S07_AXI - 0 - - - S08_HAS_REGSLICE - Enable Register Slice on interface S08_AXI - 0 - - - S09_HAS_REGSLICE - Enable Register Slice on interface S09_AXI - 0 - - - S10_HAS_REGSLICE - Enable Register Slice on interface S10_AXI - 0 - - - S11_HAS_REGSLICE - Enable Register Slice on interface S11_AXI - 0 - - - S12_HAS_REGSLICE - Enable Register Slice on interface S12_AXI - 0 - - - S13_HAS_REGSLICE - Enable Register Slice on interface S13_AXI - 0 - - - S14_HAS_REGSLICE - Enable Register Slice on interface S14_AXI - 0 - - - S15_HAS_REGSLICE - Enable Register Slice on interface S15_AXI - 0 - - - S00_HAS_DATA_FIFO - Enable Data FIFO on interface S00_AXI - 0 - - - S01_HAS_DATA_FIFO - Enable Data FIFO on interface S01_AXI - 0 - - - S02_HAS_DATA_FIFO - Enable Data FIFO on interface S02_AXI - 0 - - - S03_HAS_DATA_FIFO - Enable Data FIFO on interface S03_AXI - 0 - - - S04_HAS_DATA_FIFO - Enable Data FIFO on interface S04_AXI - 0 - - - S05_HAS_DATA_FIFO - Enable Data FIFO on interface S05_AXI - 0 - - - S06_HAS_DATA_FIFO - Enable Data FIFO on interface S06_AXI - 0 - - - S07_HAS_DATA_FIFO - Enable Data FIFO on interface S07_AXI - 0 - - - S08_HAS_DATA_FIFO - Enable Data FIFO on interface S08_AXI - 0 - - - S09_HAS_DATA_FIFO - Enable Data FIFO on interface S09_AXI - 0 - - - S10_HAS_DATA_FIFO - Enable Data FIFO on interface S10_AXI - 0 - - - S11_HAS_DATA_FIFO - Enable Data FIFO on interface S11_AXI - 0 - - - S12_HAS_DATA_FIFO - Enable Data FIFO on interface S12_AXI - 0 - - - S13_HAS_DATA_FIFO - Enable Data FIFO on interface S13_AXI - 0 - - - S14_HAS_DATA_FIFO - Enable Data FIFO on interface S14_AXI - 0 - - - S15_HAS_DATA_FIFO - Enable Data FIFO on interface S15_AXI - 0 - - - M00_ISSUANCE - Incicates whether M00_AXI connects to a secure slave - 0 - - - M01_ISSUANCE - Incicates whether M01_AXI connects to a secure slave - 0 - - - M02_ISSUANCE - Incicates whether M02_AXI connects to a secure slave - 0 - - - M03_ISSUANCE - Incicates whether M03_AXI connects to a secure slave - 0 - - - M04_ISSUANCE - Incicates whether M04_AXI connects to a secure slave - 0 - - - M05_ISSUANCE - Incicates whether M05_AXI connects to a secure slave - 0 - - - M06_ISSUANCE - Incicates whether M06_AXI connects to a secure slave - 0 - - - M07_ISSUANCE - Incicates whether M07_AXI connects to a secure slave - 0 - - - M08_ISSUANCE - Incicates whether M08_AXI connects to a secure slave - 0 - - - M09_ISSUANCE - Incicates whether M09_AXI connects to a secure slave - 0 - - - M10_ISSUANCE - Incicates whether M10_AXI connects to a secure slave - 0 - - - M11_ISSUANCE - Incicates whether M11_AXI connects to a secure slave - 0 - - - M12_ISSUANCE - Incicates whether M12_AXI connects to a secure slave - 0 - - - M13_ISSUANCE - Incicates whether M13_AXI connects to a secure slave - 0 - - - M14_ISSUANCE - Incicates whether M14_AXI connects to a secure slave - 0 - - - M15_ISSUANCE - Incicates whether M15_AXI connects to a secure slave - 0 - - - M16_ISSUANCE - Incicates whether M16_AXI connects to a secure slave - 0 - - - M17_ISSUANCE - Incicates whether M17_AXI connects to a secure slave - 0 - - - M18_ISSUANCE - Incicates whether M18_AXI connects to a secure slave - 0 - - - M19_ISSUANCE - Incicates whether M19_AXI connects to a secure slave - 0 - - - M20_ISSUANCE - Incicates whether M20_AXI connects to a secure slave - 0 - - - M21_ISSUANCE - Incicates whether M21_AXI connects to a secure slave - 0 - - - M22_ISSUANCE - Incicates whether M22_AXI connects to a secure slave - 0 - - - M23_ISSUANCE - Incicates whether M23_AXI connects to a secure slave - 0 - - - M24_ISSUANCE - Incicates whether M24_AXI connects to a secure slave - 0 - - - M25_ISSUANCE - Incicates whether M25_AXI connects to a secure slave - 0 - - - M26_ISSUANCE - Incicates whether M26_AXI connects to a secure slave - 0 - - - M27_ISSUANCE - Incicates whether M27_AXI connects to a secure slave - 0 - - - M28_ISSUANCE - Incicates whether M28_AXI connects to a secure slave - 0 - - - M29_ISSUANCE - Incicates whether M29_AXI connects to a secure slave - 0 - - - M30_ISSUANCE - Incicates whether M30_AXI connects to a secure slave - 0 - - - M31_ISSUANCE - Incicates whether M31_AXI connects to a secure slave - 0 - - - M32_ISSUANCE - Incicates whether M32_AXI connects to a secure slave - 0 - - - M33_ISSUANCE - Incicates whether M33_AXI connects to a secure slave - 0 - - - M34_ISSUANCE - Incicates whether M34_AXI connects to a secure slave - 0 - - - M35_ISSUANCE - Incicates whether M35_AXI connects to a secure slave - 0 - - - M36_ISSUANCE - Incicates whether M36_AXI connects to a secure slave - 0 - - - M37_ISSUANCE - Incicates whether M37_AXI connects to a secure slave - 0 - - - M38_ISSUANCE - Incicates whether M38_AXI connects to a secure slave - 0 - - - M39_ISSUANCE - Incicates whether M39_AXI connects to a secure slave - 0 - - - M40_ISSUANCE - Incicates whether M40_AXI connects to a secure slave - 0 - - - M41_ISSUANCE - Incicates whether M41_AXI connects to a secure slave - 0 - - - M42_ISSUANCE - Incicates whether M42_AXI connects to a secure slave - 0 - - - M43_ISSUANCE - Incicates whether M43_AXI connects to a secure slave - 0 - - - M44_ISSUANCE - Incicates whether M44_AXI connects to a secure slave - 0 - - - M45_ISSUANCE - Incicates whether M45_AXI connects to a secure slave - 0 - - - M46_ISSUANCE - Incicates whether M46_AXI connects to a secure slave - 0 - - - M47_ISSUANCE - Incicates whether M47_AXI connects to a secure slave - 0 - - - M48_ISSUANCE - Incicates whether M48_AXI connects to a secure slave - 0 - - - M49_ISSUANCE - Incicates whether M49_AXI connects to a secure slave - 0 - - - M50_ISSUANCE - Incicates whether M50_AXI connects to a secure slave - 0 - - - M51_ISSUANCE - Incicates whether M51_AXI connects to a secure slave - 0 - - - M52_ISSUANCE - Incicates whether M52_AXI connects to a secure slave - 0 - - - M53_ISSUANCE - Incicates whether M53_AXI connects to a secure slave - 0 - - - M54_ISSUANCE - Incicates whether M54_AXI connects to a secure slave - 0 - - - M55_ISSUANCE - Incicates whether M55_AXI connects to a secure slave - 0 - - - M56_ISSUANCE - Incicates whether M56_AXI connects to a secure slave - 0 - - - M57_ISSUANCE - Incicates whether M57_AXI connects to a secure slave - 0 - - - M58_ISSUANCE - Incicates whether M58_AXI connects to a secure slave - 0 - - - M59_ISSUANCE - Incicates whether M59_AXI connects to a secure slave - 0 - - - M60_ISSUANCE - Incicates whether M60_AXI connects to a secure slave - 0 - - - M61_ISSUANCE - Incicates whether M61_AXI connects to a secure slave - 0 - - - M62_ISSUANCE - Incicates whether M62_AXI connects to a secure slave - 0 - - - M63_ISSUANCE - Incicates whether M63_AXI connects to a secure slave - 0 - - - M00_SECURE - Incicates whether M00_AXI connects to a secure slave - 0 - - - M01_SECURE - Incicates whether M01_AXI connects to a secure slave - 0 - - - M02_SECURE - Incicates whether M02_AXI connects to a secure slave - 0 - - - M03_SECURE - Incicates whether M03_AXI connects to a secure slave - 0 - - - M04_SECURE - Incicates whether M04_AXI connects to a secure slave - 0 - - - M05_SECURE - Incicates whether M05_AXI connects to a secure slave - 0 - - - M06_SECURE - Incicates whether M06_AXI connects to a secure slave - 0 - - - M07_SECURE - Incicates whether M07_AXI connects to a secure slave - 0 - - - M08_SECURE - Incicates whether M08_AXI connects to a secure slave - 0 - - - M09_SECURE - Incicates whether M09_AXI connects to a secure slave - 0 - - - M10_SECURE - Incicates whether M10_AXI connects to a secure slave - 0 - - - M11_SECURE - Incicates whether M11_AXI connects to a secure slave - 0 - - - M12_SECURE - Incicates whether M12_AXI connects to a secure slave - 0 - - - M13_SECURE - Incicates whether M13_AXI connects to a secure slave - 0 - - - M14_SECURE - Incicates whether M14_AXI connects to a secure slave - 0 - - - M15_SECURE - Incicates whether M15_AXI connects to a secure slave - 0 - - - M16_SECURE - Incicates whether M16_AXI connects to a secure slave - 0 - - - M17_SECURE - Incicates whether M17_AXI connects to a secure slave - 0 - - - M18_SECURE - Incicates whether M18_AXI connects to a secure slave - 0 - - - M19_SECURE - Incicates whether M19_AXI connects to a secure slave - 0 - - - M20_SECURE - Incicates whether M20_AXI connects to a secure slave - 0 - - - M21_SECURE - Incicates whether M21_AXI connects to a secure slave - 0 - - - M22_SECURE - Incicates whether M22_AXI connects to a secure slave - 0 - - - M23_SECURE - Incicates whether M23_AXI connects to a secure slave - 0 - - - M24_SECURE - Incicates whether M24_AXI connects to a secure slave - 0 - - - M25_SECURE - Incicates whether M25_AXI connects to a secure slave - 0 - - - M26_SECURE - Incicates whether M26_AXI connects to a secure slave - 0 - - - M27_SECURE - Incicates whether M27_AXI connects to a secure slave - 0 - - - M28_SECURE - Incicates whether M28_AXI connects to a secure slave - 0 - - - M29_SECURE - Incicates whether M29_AXI connects to a secure slave - 0 - - - M30_SECURE - Incicates whether M30_AXI connects to a secure slave - 0 - - - M31_SECURE - Incicates whether M31_AXI connects to a secure slave - 0 - - - M32_SECURE - Incicates whether M32_AXI connects to a secure slave - 0 - - - M33_SECURE - Incicates whether M33_AXI connects to a secure slave - 0 - - - M34_SECURE - Incicates whether M34_AXI connects to a secure slave - 0 - - - M35_SECURE - Incicates whether M35_AXI connects to a secure slave - 0 - - - M36_SECURE - Incicates whether M36_AXI connects to a secure slave - 0 - - - M37_SECURE - Incicates whether M37_AXI connects to a secure slave - 0 - - - M38_SECURE - Incicates whether M38_AXI connects to a secure slave - 0 - - - M39_SECURE - Incicates whether M39_AXI connects to a secure slave - 0 - - - M40_SECURE - Incicates whether M40_AXI connects to a secure slave - 0 - - - M41_SECURE - Incicates whether M41_AXI connects to a secure slave - 0 - - - M42_SECURE - Incicates whether M42_AXI connects to a secure slave - 0 - - - M43_SECURE - Incicates whether M43_AXI connects to a secure slave - 0 - - - M44_SECURE - Incicates whether M44_AXI connects to a secure slave - 0 - - - M45_SECURE - Incicates whether M45_AXI connects to a secure slave - 0 - - - M46_SECURE - Incicates whether M46_AXI connects to a secure slave - 0 - - - M47_SECURE - Incicates whether M47_AXI connects to a secure slave - 0 - - - M48_SECURE - Incicates whether M48_AXI connects to a secure slave - 0 - - - M49_SECURE - Incicates whether M49_AXI connects to a secure slave - 0 - - - M50_SECURE - Incicates whether M50_AXI connects to a secure slave - 0 - - - M51_SECURE - Incicates whether M51_AXI connects to a secure slave - 0 - - - M52_SECURE - Incicates whether M52_AXI connects to a secure slave - 0 - - - M53_SECURE - Incicates whether M53_AXI connects to a secure slave - 0 - - - M54_SECURE - Incicates whether M54_AXI connects to a secure slave - 0 - - - M55_SECURE - Incicates whether M55_AXI connects to a secure slave - 0 - - - M56_SECURE - Incicates whether M56_AXI connects to a secure slave - 0 - - - M57_SECURE - Incicates whether M57_AXI connects to a secure slave - 0 - - - M58_SECURE - Incicates whether M58_AXI connects to a secure slave - 0 - - - M59_SECURE - Incicates whether M59_AXI connects to a secure slave - 0 - - - M60_SECURE - Incicates whether M60_AXI connects to a secure slave - 0 - - - M61_SECURE - Incicates whether M61_AXI connects to a secure slave - 0 - - - M62_SECURE - Incicates whether M62_AXI connects to a secure slave - 0 - - - M63_SECURE - Incicates whether M63_AXI connects to a secure slave - 0 - - - S00_ARB_PRIORITY - Controls S00_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S01_ARB_PRIORITY - Controls S01_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S02_ARB_PRIORITY - Controls S02_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S03_ARB_PRIORITY - Controls S03_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S04_ARB_PRIORITY - Controls S04_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S05_ARB_PRIORITY - Controls S05_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S06_ARB_PRIORITY - Controls S06_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S07_ARB_PRIORITY - Controls S07_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S08_ARB_PRIORITY - Controls S08_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S09_ARB_PRIORITY - Controls S09_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S10_ARB_PRIORITY - Controls S10_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S11_ARB_PRIORITY - Controls S11_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S12_ARB_PRIORITY - Controls S12_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S13_ARB_PRIORITY - Controls S13_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S14_ARB_PRIORITY - Controls S14_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - S15_ARB_PRIORITY - Controls S15_ARB_PRIORITY on SI axi_crossbar instance within interconnect - 0 - - - Component_Name - Arty_Z7_20_processing_system7_0_axi_periph_0 - - - - - AXI Interconnect - 12 - - - - - - 2016.4 - - - - + + xilinx.com + customized_ip + Arty_Z7_20_processing_system7_0_axi_periph_0 + 1.0 + + + choice_list_40181835 + 32 + 64 + 128 + 256 + 512 + 1024 + + + choice_list_661c4a03 + 2 + 4 + 8 + 16 + 32 + 64 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_76d086ea + 0 + 1 + 2 + + + choice_pairs_ab2668a2 + 0 + 1 + 2 + + + choice_pairs_b6c9535e + 0 + 1 + 3 + 4 + + + The AXI Interconnect IP connects one or more AXI memory-mapped master devices to one or more AXI memory mapped slave devices + + + NUM_SI + Number of Slave Interfaces + 1 + + + NUM_MI + Number of Master Interfaces + 11 + + + STRATEGY + Interconnect Optimization Strategy + 0 + + + ENABLE_ADVANCED_OPTIONS + Enable Advanced Configuration Options + 0 + + + ENABLE_PROTOCOL_CHECKERS + Enable Protocol Checkers and mark interfaces for debug + 0 + + + XBAR_DATA_WIDTH + Data Width of the AXI Crossbar + 32 + + + PCHK_WAITS + Maximum number of idle cycles for READY monitoring + 0 + + + PCHK_MAX_RD_BURSTS + Maximum outstanding READ Transactions per ID + 2 + + + PCHK_MAX_WR_BURSTS + Maximum outstanding WRITE Transactions per ID + 2 + + + SYNCHRONIZATION_STAGES + Synchronization Stages + 2 + + + M00_HAS_REGSLICE + Enable Register Slice on interface M00_AXI + 0 + + + M01_HAS_REGSLICE + Enable Register Slice on interface M01_AXI + 0 + + + M02_HAS_REGSLICE + Enable Register Slice on interface M02_AXI + 0 + + + M03_HAS_REGSLICE + Enable Register Slice on interface M03_AXI + 0 + + + M04_HAS_REGSLICE + Enable Register Slice on interface M04_AXI + 0 + + + M05_HAS_REGSLICE + Enable Register Slice on interface M05_AXI + 0 + + + M06_HAS_REGSLICE + Enable Register Slice on interface M06_AXI + 0 + + + M07_HAS_REGSLICE + Enable Register Slice on interface M07_AXI + 0 + + + M08_HAS_REGSLICE + Enable Register Slice on interface M08_AXI + 0 + + + M09_HAS_REGSLICE + Enable Register Slice on interface M09_AXI + 0 + + + M10_HAS_REGSLICE + Enable Register Slice on interface M10_AXI + 0 + + + M11_HAS_REGSLICE + Enable Register Slice on interface M11_AXI + 0 + + + M12_HAS_REGSLICE + Enable Register Slice on interface M12_AXI + 0 + + + M13_HAS_REGSLICE + Enable Register Slice on interface M13_AXI + 0 + + + M14_HAS_REGSLICE + Enable Register Slice on interface M14_AXI + 0 + + + M15_HAS_REGSLICE + Enable Register Slice on interface M15_AXI + 0 + + + M16_HAS_REGSLICE + Enable Register Slice on interface M16_AXI + 0 + + + M17_HAS_REGSLICE + Enable Register Slice on interface M17_AXI + 0 + + + M18_HAS_REGSLICE + Enable Register Slice on interface M18_AXI + 0 + + + M19_HAS_REGSLICE + Enable Register Slice on interface M19_AXI + 0 + + + M20_HAS_REGSLICE + Enable Register Slice on interface M20_AXI + 0 + + + M21_HAS_REGSLICE + Enable Register Slice on interface M21_AXI + 0 + + + M22_HAS_REGSLICE + Enable Register Slice on interface M22_AXI + 0 + + + M23_HAS_REGSLICE + Enable Register Slice on interface M23_AXI + 0 + + + M24_HAS_REGSLICE + Enable Register Slice on interface M24_AXI + 0 + + + M25_HAS_REGSLICE + Enable Register Slice on interface M25_AXI + 0 + + + M26_HAS_REGSLICE + Enable Register Slice on interface M26_AXI + 0 + + + M27_HAS_REGSLICE + Enable Register Slice on interface M27_AXI + 0 + + + M28_HAS_REGSLICE + Enable Register Slice on interface M28_AXI + 0 + + + M29_HAS_REGSLICE + Enable Register Slice on interface M29_AXI + 0 + + + M30_HAS_REGSLICE + Enable Register Slice on interface M30_AXI + 0 + + + M31_HAS_REGSLICE + Enable Register Slice on interface M31_AXI + 0 + + + M32_HAS_REGSLICE + Enable Register Slice on interface M32_AXI + 0 + + + M33_HAS_REGSLICE + Enable Register Slice on interface M33_AXI + 0 + + + M34_HAS_REGSLICE + Enable Register Slice on interface M34_AXI + 0 + + + M35_HAS_REGSLICE + Enable Register Slice on interface M35_AXI + 0 + + + M36_HAS_REGSLICE + Enable Register Slice on interface M36_AXI + 0 + + + M37_HAS_REGSLICE + Enable Register Slice on interface M37_AXI + 0 + + + M38_HAS_REGSLICE + Enable Register Slice on interface M38_AXI + 0 + + + M39_HAS_REGSLICE + Enable Register Slice on interface M39_AXI + 0 + + + M40_HAS_REGSLICE + Enable Register Slice on interface M40_AXI + 0 + + + M41_HAS_REGSLICE + Enable Register Slice on interface M41_AXI + 0 + + + M42_HAS_REGSLICE + Enable Register Slice on interface M42_AXI + 0 + + + M43_HAS_REGSLICE + Enable Register Slice on interface M43_AXI + 0 + + + M44_HAS_REGSLICE + Enable Register Slice on interface M44_AXI + 0 + + + M45_HAS_REGSLICE + Enable Register Slice on interface M45_AXI + 0 + + + M46_HAS_REGSLICE + Enable Register Slice on interface M46_AXI + 0 + + + M47_HAS_REGSLICE + Enable Register Slice on interface M47_AXI + 0 + + + M48_HAS_REGSLICE + Enable Register Slice on interface M48_AXI + 0 + + + M49_HAS_REGSLICE + Enable Register Slice on interface M49_AXI + 0 + + + M50_HAS_REGSLICE + Enable Register Slice on interface M50_AXI + 0 + + + M51_HAS_REGSLICE + Enable Register Slice on interface M51_AXI + 0 + + + M52_HAS_REGSLICE + Enable Register Slice on interface M52_AXI + 0 + + + M53_HAS_REGSLICE + Enable Register Slice on interface M53_AXI + 0 + + + M54_HAS_REGSLICE + Enable Register Slice on interface M54_AXI + 0 + + + M55_HAS_REGSLICE + Enable Register Slice on interface M55_AXI + 0 + + + M56_HAS_REGSLICE + Enable Register Slice on interface M56_AXI + 0 + + + M57_HAS_REGSLICE + Enable Register Slice on interface M57_AXI + 0 + + + M58_HAS_REGSLICE + Enable Register Slice on interface M58_AXI + 0 + + + M59_HAS_REGSLICE + Enable Register Slice on interface M59_AXI + 0 + + + M60_HAS_REGSLICE + Enable Register Slice on interface M60_AXI + 0 + + + M61_HAS_REGSLICE + Enable Register Slice on interface M61_AXI + 0 + + + M62_HAS_REGSLICE + Enable Register Slice on interface M62_AXI + 0 + + + M63_HAS_REGSLICE + Enable Register Slice on interface M63_AXI + 0 + + + M00_HAS_DATA_FIFO + Enable Data FIFO on interface M00_AXI + 0 + + + M01_HAS_DATA_FIFO + Enable Data FIFO on interface M01_AXI + 0 + + + M02_HAS_DATA_FIFO + Enable Data FIFO on interface M02_AXI + 0 + + + M03_HAS_DATA_FIFO + Enable Data FIFO on interface M03_AXI + 0 + + + M04_HAS_DATA_FIFO + Enable Data FIFO on interface M04_AXI + 0 + + + M05_HAS_DATA_FIFO + Enable Data FIFO on interface M05_AXI + 0 + + + M06_HAS_DATA_FIFO + Enable Data FIFO on interface M06_AXI + 0 + + + M07_HAS_DATA_FIFO + Enable Data FIFO on interface M07_AXI + 0 + + + M08_HAS_DATA_FIFO + Enable Data FIFO on interface M08_AXI + 0 + + + M09_HAS_DATA_FIFO + Enable Data FIFO on interface M09_AXI + 0 + + + M10_HAS_DATA_FIFO + Enable Data FIFO on interface M10_AXI + 0 + + + M11_HAS_DATA_FIFO + Enable Data FIFO on interface M11_AXI + 0 + + + M12_HAS_DATA_FIFO + Enable Data FIFO on interface M12_AXI + 0 + + + M13_HAS_DATA_FIFO + Enable Data FIFO on interface M13_AXI + 0 + + + M14_HAS_DATA_FIFO + Enable Data FIFO on interface M14_AXI + 0 + + + M15_HAS_DATA_FIFO + Enable Data FIFO on interface M15_AXI + 0 + + + M16_HAS_DATA_FIFO + Enable Data FIFO on interface M16_AXI + 0 + + + M17_HAS_DATA_FIFO + Enable Data FIFO on interface M17_AXI + 0 + + + M18_HAS_DATA_FIFO + Enable Data FIFO on interface M18_AXI + 0 + + + M19_HAS_DATA_FIFO + Enable Data FIFO on interface M19_AXI + 0 + + + M20_HAS_DATA_FIFO + Enable Data FIFO on interface M20_AXI + 0 + + + M21_HAS_DATA_FIFO + Enable Data FIFO on interface M21_AXI + 0 + + + M22_HAS_DATA_FIFO + Enable Data FIFO on interface M22_AXI + 0 + + + M23_HAS_DATA_FIFO + Enable Data FIFO on interface M23_AXI + 0 + + + M24_HAS_DATA_FIFO + Enable Data FIFO on interface M24_AXI + 0 + + + M25_HAS_DATA_FIFO + Enable Data FIFO on interface M25_AXI + 0 + + + M26_HAS_DATA_FIFO + Enable Data FIFO on interface M26_AXI + 0 + + + M27_HAS_DATA_FIFO + Enable Data FIFO on interface M27_AXI + 0 + + + M28_HAS_DATA_FIFO + Enable Data FIFO on interface M28_AXI + 0 + + + M29_HAS_DATA_FIFO + Enable Data FIFO on interface M29_AXI + 0 + + + M30_HAS_DATA_FIFO + Enable Data FIFO on interface M30_AXI + 0 + + + M31_HAS_DATA_FIFO + Enable Data FIFO on interface M31_AXI + 0 + + + M32_HAS_DATA_FIFO + Enable Data FIFO on interface M32_AXI + 0 + + + M33_HAS_DATA_FIFO + Enable Data FIFO on interface M33_AXI + 0 + + + M34_HAS_DATA_FIFO + Enable Data FIFO on interface M34_AXI + 0 + + + M35_HAS_DATA_FIFO + Enable Data FIFO on interface M35_AXI + 0 + + + M36_HAS_DATA_FIFO + Enable Data FIFO on interface M36_AXI + 0 + + + M37_HAS_DATA_FIFO + Enable Data FIFO on interface M37_AXI + 0 + + + M38_HAS_DATA_FIFO + Enable Data FIFO on interface M38_AXI + 0 + + + M39_HAS_DATA_FIFO + Enable Data FIFO on interface M39_AXI + 0 + + + M40_HAS_DATA_FIFO + Enable Data FIFO on interface M40_AXI + 0 + + + M41_HAS_DATA_FIFO + Enable Data FIFO on interface M41_AXI + 0 + + + M42_HAS_DATA_FIFO + Enable Data FIFO on interface M42_AXI + 0 + + + M43_HAS_DATA_FIFO + Enable Data FIFO on interface M43_AXI + 0 + + + M44_HAS_DATA_FIFO + Enable Data FIFO on interface M44_AXI + 0 + + + M45_HAS_DATA_FIFO + Enable Data FIFO on interface M45_AXI + 0 + + + M46_HAS_DATA_FIFO + Enable Data FIFO on interface M46_AXI + 0 + + + M47_HAS_DATA_FIFO + Enable Data FIFO on interface M47_AXI + 0 + + + M48_HAS_DATA_FIFO + Enable Data FIFO on interface M48_AXI + 0 + + + M49_HAS_DATA_FIFO + Enable Data FIFO on interface M49_AXI + 0 + + + M50_HAS_DATA_FIFO + Enable Data FIFO on interface M50_AXI + 0 + + + M51_HAS_DATA_FIFO + Enable Data FIFO on interface M51_AXI + 0 + + + M52_HAS_DATA_FIFO + Enable Data FIFO on interface M52_AXI + 0 + + + M53_HAS_DATA_FIFO + Enable Data FIFO on interface M53_AXI + 0 + + + M54_HAS_DATA_FIFO + Enable Data FIFO on interface M54_AXI + 0 + + + M55_HAS_DATA_FIFO + Enable Data FIFO on interface M55_AXI + 0 + + + M56_HAS_DATA_FIFO + Enable Data FIFO on interface M56_AXI + 0 + + + M57_HAS_DATA_FIFO + Enable Data FIFO on interface M57_AXI + 0 + + + M58_HAS_DATA_FIFO + Enable Data FIFO on interface M58_AXI + 0 + + + M59_HAS_DATA_FIFO + Enable Data FIFO on interface M59_AXI + 0 + + + M60_HAS_DATA_FIFO + Enable Data FIFO on interface M60_AXI + 0 + + + M61_HAS_DATA_FIFO + Enable Data FIFO on interface M61_AXI + 0 + + + M62_HAS_DATA_FIFO + Enable Data FIFO on interface M62_AXI + 0 + + + M63_HAS_DATA_FIFO + Enable Data FIFO on interface M63_AXI + 0 + + + S00_HAS_REGSLICE + Enable Register Slice on interface S00_AXI + 0 + + + S01_HAS_REGSLICE + Enable Register Slice on interface S01_AXI + 0 + + + S02_HAS_REGSLICE + Enable Register Slice on interface S02_AXI + 0 + + + S03_HAS_REGSLICE + Enable Register Slice on interface S03_AXI + 0 + + + S04_HAS_REGSLICE + Enable Register Slice on interface S04_AXI + 0 + + + S05_HAS_REGSLICE + Enable Register Slice on interface S05_AXI + 0 + + + S06_HAS_REGSLICE + Enable Register Slice on interface S06_AXI + 0 + + + S07_HAS_REGSLICE + Enable Register Slice on interface S07_AXI + 0 + + + S08_HAS_REGSLICE + Enable Register Slice on interface S08_AXI + 0 + + + S09_HAS_REGSLICE + Enable Register Slice on interface S09_AXI + 0 + + + S10_HAS_REGSLICE + Enable Register Slice on interface S10_AXI + 0 + + + S11_HAS_REGSLICE + Enable Register Slice on interface S11_AXI + 0 + + + S12_HAS_REGSLICE + Enable Register Slice on interface S12_AXI + 0 + + + S13_HAS_REGSLICE + Enable Register Slice on interface S13_AXI + 0 + + + S14_HAS_REGSLICE + Enable Register Slice on interface S14_AXI + 0 + + + S15_HAS_REGSLICE + Enable Register Slice on interface S15_AXI + 0 + + + S00_HAS_DATA_FIFO + Enable Data FIFO on interface S00_AXI + 0 + + + S01_HAS_DATA_FIFO + Enable Data FIFO on interface S01_AXI + 0 + + + S02_HAS_DATA_FIFO + Enable Data FIFO on interface S02_AXI + 0 + + + S03_HAS_DATA_FIFO + Enable Data FIFO on interface S03_AXI + 0 + + + S04_HAS_DATA_FIFO + Enable Data FIFO on interface S04_AXI + 0 + + + S05_HAS_DATA_FIFO + Enable Data FIFO on interface S05_AXI + 0 + + + S06_HAS_DATA_FIFO + Enable Data FIFO on interface S06_AXI + 0 + + + S07_HAS_DATA_FIFO + Enable Data FIFO on interface S07_AXI + 0 + + + S08_HAS_DATA_FIFO + Enable Data FIFO on interface S08_AXI + 0 + + + S09_HAS_DATA_FIFO + Enable Data FIFO on interface S09_AXI + 0 + + + S10_HAS_DATA_FIFO + Enable Data FIFO on interface S10_AXI + 0 + + + S11_HAS_DATA_FIFO + Enable Data FIFO on interface S11_AXI + 0 + + + S12_HAS_DATA_FIFO + Enable Data FIFO on interface S12_AXI + 0 + + + S13_HAS_DATA_FIFO + Enable Data FIFO on interface S13_AXI + 0 + + + S14_HAS_DATA_FIFO + Enable Data FIFO on interface S14_AXI + 0 + + + S15_HAS_DATA_FIFO + Enable Data FIFO on interface S15_AXI + 0 + + + M00_ISSUANCE + Incicates whether M00_AXI connects to a secure slave + 0 + + + M01_ISSUANCE + Incicates whether M01_AXI connects to a secure slave + 0 + + + M02_ISSUANCE + Incicates whether M02_AXI connects to a secure slave + 0 + + + M03_ISSUANCE + Incicates whether M03_AXI connects to a secure slave + 0 + + + M04_ISSUANCE + Incicates whether M04_AXI connects to a secure slave + 0 + + + M05_ISSUANCE + Incicates whether M05_AXI connects to a secure slave + 0 + + + M06_ISSUANCE + Incicates whether M06_AXI connects to a secure slave + 0 + + + M07_ISSUANCE + Incicates whether M07_AXI connects to a secure slave + 0 + + + M08_ISSUANCE + Incicates whether M08_AXI connects to a secure slave + 0 + + + M09_ISSUANCE + Incicates whether M09_AXI connects to a secure slave + 0 + + + M10_ISSUANCE + Incicates whether M10_AXI connects to a secure slave + 0 + + + M11_ISSUANCE + Incicates whether M11_AXI connects to a secure slave + 0 + + + M12_ISSUANCE + Incicates whether M12_AXI connects to a secure slave + 0 + + + M13_ISSUANCE + Incicates whether M13_AXI connects to a secure slave + 0 + + + M14_ISSUANCE + Incicates whether M14_AXI connects to a secure slave + 0 + + + M15_ISSUANCE + Incicates whether M15_AXI connects to a secure slave + 0 + + + M16_ISSUANCE + Incicates whether M16_AXI connects to a secure slave + 0 + + + M17_ISSUANCE + Incicates whether M17_AXI connects to a secure slave + 0 + + + M18_ISSUANCE + Incicates whether M18_AXI connects to a secure slave + 0 + + + M19_ISSUANCE + Incicates whether M19_AXI connects to a secure slave + 0 + + + M20_ISSUANCE + Incicates whether M20_AXI connects to a secure slave + 0 + + + M21_ISSUANCE + Incicates whether M21_AXI connects to a secure slave + 0 + + + M22_ISSUANCE + Incicates whether M22_AXI connects to a secure slave + 0 + + + M23_ISSUANCE + Incicates whether M23_AXI connects to a secure slave + 0 + + + M24_ISSUANCE + Incicates whether M24_AXI connects to a secure slave + 0 + + + M25_ISSUANCE + Incicates whether M25_AXI connects to a secure slave + 0 + + + M26_ISSUANCE + Incicates whether M26_AXI connects to a secure slave + 0 + + + M27_ISSUANCE + Incicates whether M27_AXI connects to a secure slave + 0 + + + M28_ISSUANCE + Incicates whether M28_AXI connects to a secure slave + 0 + + + M29_ISSUANCE + Incicates whether M29_AXI connects to a secure slave + 0 + + + M30_ISSUANCE + Incicates whether M30_AXI connects to a secure slave + 0 + + + M31_ISSUANCE + Incicates whether M31_AXI connects to a secure slave + 0 + + + M32_ISSUANCE + Incicates whether M32_AXI connects to a secure slave + 0 + + + M33_ISSUANCE + Incicates whether M33_AXI connects to a secure slave + 0 + + + M34_ISSUANCE + Incicates whether M34_AXI connects to a secure slave + 0 + + + M35_ISSUANCE + Incicates whether M35_AXI connects to a secure slave + 0 + + + M36_ISSUANCE + Incicates whether M36_AXI connects to a secure slave + 0 + + + M37_ISSUANCE + Incicates whether M37_AXI connects to a secure slave + 0 + + + M38_ISSUANCE + Incicates whether M38_AXI connects to a secure slave + 0 + + + M39_ISSUANCE + Incicates whether M39_AXI connects to a secure slave + 0 + + + M40_ISSUANCE + Incicates whether M40_AXI connects to a secure slave + 0 + + + M41_ISSUANCE + Incicates whether M41_AXI connects to a secure slave + 0 + + + M42_ISSUANCE + Incicates whether M42_AXI connects to a secure slave + 0 + + + M43_ISSUANCE + Incicates whether M43_AXI connects to a secure slave + 0 + + + M44_ISSUANCE + Incicates whether M44_AXI connects to a secure slave + 0 + + + M45_ISSUANCE + Incicates whether M45_AXI connects to a secure slave + 0 + + + M46_ISSUANCE + Incicates whether M46_AXI connects to a secure slave + 0 + + + M47_ISSUANCE + Incicates whether M47_AXI connects to a secure slave + 0 + + + M48_ISSUANCE + Incicates whether M48_AXI connects to a secure slave + 0 + + + M49_ISSUANCE + Incicates whether M49_AXI connects to a secure slave + 0 + + + M50_ISSUANCE + Incicates whether M50_AXI connects to a secure slave + 0 + + + M51_ISSUANCE + Incicates whether M51_AXI connects to a secure slave + 0 + + + M52_ISSUANCE + Incicates whether M52_AXI connects to a secure slave + 0 + + + M53_ISSUANCE + Incicates whether M53_AXI connects to a secure slave + 0 + + + M54_ISSUANCE + Incicates whether M54_AXI connects to a secure slave + 0 + + + M55_ISSUANCE + Incicates whether M55_AXI connects to a secure slave + 0 + + + M56_ISSUANCE + Incicates whether M56_AXI connects to a secure slave + 0 + + + M57_ISSUANCE + Incicates whether M57_AXI connects to a secure slave + 0 + + + M58_ISSUANCE + Incicates whether M58_AXI connects to a secure slave + 0 + + + M59_ISSUANCE + Incicates whether M59_AXI connects to a secure slave + 0 + + + M60_ISSUANCE + Incicates whether M60_AXI connects to a secure slave + 0 + + + M61_ISSUANCE + Incicates whether M61_AXI connects to a secure slave + 0 + + + M62_ISSUANCE + Incicates whether M62_AXI connects to a secure slave + 0 + + + M63_ISSUANCE + Incicates whether M63_AXI connects to a secure slave + 0 + + + M00_SECURE + Incicates whether M00_AXI connects to a secure slave + 0 + + + M01_SECURE + Incicates whether M01_AXI connects to a secure slave + 0 + + + M02_SECURE + Incicates whether M02_AXI connects to a secure slave + 0 + + + M03_SECURE + Incicates whether M03_AXI connects to a secure slave + 0 + + + M04_SECURE + Incicates whether M04_AXI connects to a secure slave + 0 + + + M05_SECURE + Incicates whether M05_AXI connects to a secure slave + 0 + + + M06_SECURE + Incicates whether M06_AXI connects to a secure slave + 0 + + + M07_SECURE + Incicates whether M07_AXI connects to a secure slave + 0 + + + M08_SECURE + Incicates whether M08_AXI connects to a secure slave + 0 + + + M09_SECURE + Incicates whether M09_AXI connects to a secure slave + 0 + + + M10_SECURE + Incicates whether M10_AXI connects to a secure slave + 0 + + + M11_SECURE + Incicates whether M11_AXI connects to a secure slave + 0 + + + M12_SECURE + Incicates whether M12_AXI connects to a secure slave + 0 + + + M13_SECURE + Incicates whether M13_AXI connects to a secure slave + 0 + + + M14_SECURE + Incicates whether M14_AXI connects to a secure slave + 0 + + + M15_SECURE + Incicates whether M15_AXI connects to a secure slave + 0 + + + M16_SECURE + Incicates whether M16_AXI connects to a secure slave + 0 + + + M17_SECURE + Incicates whether M17_AXI connects to a secure slave + 0 + + + M18_SECURE + Incicates whether M18_AXI connects to a secure slave + 0 + + + M19_SECURE + Incicates whether M19_AXI connects to a secure slave + 0 + + + M20_SECURE + Incicates whether M20_AXI connects to a secure slave + 0 + + + M21_SECURE + Incicates whether M21_AXI connects to a secure slave + 0 + + + M22_SECURE + Incicates whether M22_AXI connects to a secure slave + 0 + + + M23_SECURE + Incicates whether M23_AXI connects to a secure slave + 0 + + + M24_SECURE + Incicates whether M24_AXI connects to a secure slave + 0 + + + M25_SECURE + Incicates whether M25_AXI connects to a secure slave + 0 + + + M26_SECURE + Incicates whether M26_AXI connects to a secure slave + 0 + + + M27_SECURE + Incicates whether M27_AXI connects to a secure slave + 0 + + + M28_SECURE + Incicates whether M28_AXI connects to a secure slave + 0 + + + M29_SECURE + Incicates whether M29_AXI connects to a secure slave + 0 + + + M30_SECURE + Incicates whether M30_AXI connects to a secure slave + 0 + + + M31_SECURE + Incicates whether M31_AXI connects to a secure slave + 0 + + + M32_SECURE + Incicates whether M32_AXI connects to a secure slave + 0 + + + M33_SECURE + Incicates whether M33_AXI connects to a secure slave + 0 + + + M34_SECURE + Incicates whether M34_AXI connects to a secure slave + 0 + + + M35_SECURE + Incicates whether M35_AXI connects to a secure slave + 0 + + + M36_SECURE + Incicates whether M36_AXI connects to a secure slave + 0 + + + M37_SECURE + Incicates whether M37_AXI connects to a secure slave + 0 + + + M38_SECURE + Incicates whether M38_AXI connects to a secure slave + 0 + + + M39_SECURE + Incicates whether M39_AXI connects to a secure slave + 0 + + + M40_SECURE + Incicates whether M40_AXI connects to a secure slave + 0 + + + M41_SECURE + Incicates whether M41_AXI connects to a secure slave + 0 + + + M42_SECURE + Incicates whether M42_AXI connects to a secure slave + 0 + + + M43_SECURE + Incicates whether M43_AXI connects to a secure slave + 0 + + + M44_SECURE + Incicates whether M44_AXI connects to a secure slave + 0 + + + M45_SECURE + Incicates whether M45_AXI connects to a secure slave + 0 + + + M46_SECURE + Incicates whether M46_AXI connects to a secure slave + 0 + + + M47_SECURE + Incicates whether M47_AXI connects to a secure slave + 0 + + + M48_SECURE + Incicates whether M48_AXI connects to a secure slave + 0 + + + M49_SECURE + Incicates whether M49_AXI connects to a secure slave + 0 + + + M50_SECURE + Incicates whether M50_AXI connects to a secure slave + 0 + + + M51_SECURE + Incicates whether M51_AXI connects to a secure slave + 0 + + + M52_SECURE + Incicates whether M52_AXI connects to a secure slave + 0 + + + M53_SECURE + Incicates whether M53_AXI connects to a secure slave + 0 + + + M54_SECURE + Incicates whether M54_AXI connects to a secure slave + 0 + + + M55_SECURE + Incicates whether M55_AXI connects to a secure slave + 0 + + + M56_SECURE + Incicates whether M56_AXI connects to a secure slave + 0 + + + M57_SECURE + Incicates whether M57_AXI connects to a secure slave + 0 + + + M58_SECURE + Incicates whether M58_AXI connects to a secure slave + 0 + + + M59_SECURE + Incicates whether M59_AXI connects to a secure slave + 0 + + + M60_SECURE + Incicates whether M60_AXI connects to a secure slave + 0 + + + M61_SECURE + Incicates whether M61_AXI connects to a secure slave + 0 + + + M62_SECURE + Incicates whether M62_AXI connects to a secure slave + 0 + + + M63_SECURE + Incicates whether M63_AXI connects to a secure slave + 0 + + + S00_ARB_PRIORITY + Controls S00_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S01_ARB_PRIORITY + Controls S01_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S02_ARB_PRIORITY + Controls S02_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S03_ARB_PRIORITY + Controls S03_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S04_ARB_PRIORITY + Controls S04_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S05_ARB_PRIORITY + Controls S05_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S06_ARB_PRIORITY + Controls S06_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S07_ARB_PRIORITY + Controls S07_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S08_ARB_PRIORITY + Controls S08_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S09_ARB_PRIORITY + Controls S09_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S10_ARB_PRIORITY + Controls S10_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S11_ARB_PRIORITY + Controls S11_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S12_ARB_PRIORITY + Controls S12_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S13_ARB_PRIORITY + Controls S13_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S14_ARB_PRIORITY + Controls S14_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + S15_ARB_PRIORITY + Controls S15_ARB_PRIORITY on SI axi_crossbar instance within interconnect + 0 + + + Component_Name + Arty_Z7_20_processing_system7_0_axi_periph_0 + + + + + AXI Interconnect + 12 + + + + + + 2016.4 + + + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_rst_processing_system7_0_142M_0/Arty_Z7_20_rst_processing_system7_0_142M_0.dcp b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_rst_processing_system7_0_142M_0/Arty_Z7_20_rst_processing_system7_0_142M_0.dcp index ad90419..cd662b3 100644 Binary files a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_rst_processing_system7_0_142M_0/Arty_Z7_20_rst_processing_system7_0_142M_0.dcp and b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_rst_processing_system7_0_142M_0/Arty_Z7_20_rst_processing_system7_0_142M_0.dcp differ diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_rst_processing_system7_0_142M_0/Arty_Z7_20_rst_processing_system7_0_142M_0.xci b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_rst_processing_system7_0_142M_0/Arty_Z7_20_rst_processing_system7_0_142M_0.xci index c80b462..02a4203 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_rst_processing_system7_0_142M_0/Arty_Z7_20_rst_processing_system7_0_142M_0.xci +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_rst_processing_system7_0_142M_0/Arty_Z7_20_rst_processing_system7_0_142M_0.xci @@ -12,7 +12,7 @@ ACTIVE_LOW Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 - 142857132 + 118181816 0.000 ACTIVE_LOW 0 @@ -46,6 +46,7 @@ TRUE TRUE + 38f290234db962d7 IP_Integrator 10 TRUE diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_rst_processing_system7_0_142M_0/Arty_Z7_20_rst_processing_system7_0_142M_0.xml b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_rst_processing_system7_0_142M_0/Arty_Z7_20_rst_processing_system7_0_142M_0.xml index b65c0e6..82b7f9f 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_rst_processing_system7_0_142M_0/Arty_Z7_20_rst_processing_system7_0_142M_0.xml +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_rst_processing_system7_0_142M_0/Arty_Z7_20_rst_processing_system7_0_142M_0.xml @@ -30,7 +30,7 @@ FREQ_HZ Slowest Sync clock frequency Slowest Synchronous clock frequency - 142857132 + 118181816 PHASE @@ -264,6 +264,36 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Mon Mar 06 02:56:06 UTC 2017 + + + boundaryCRC + 778c5560 + + + boundaryCRCversion + 1 + + + customizationCRC + 853e16c8 + + + customizationCRCversion + 6 + + + xilinx_vhdlsynthesis VHDL Synthesis @@ -278,11 +308,11 @@ GENtimestamp - Fri Feb 24 23:58:23 UTC 2017 + Mon Mar 06 02:55:58 UTC 2017 boundaryCRC - 25798b3e + 778c5560 boundaryCRCversion @@ -308,11 +338,11 @@ GENtimestamp - Fri Feb 24 23:58:23 UTC 2017 + Mon Mar 06 02:55:58 UTC 2017 boundaryCRC - 25798b3e + 778c5560 boundaryCRCversion @@ -339,11 +369,11 @@ GENtimestamp - Fri Feb 24 23:58:23 UTC 2017 + Mon Mar 06 02:55:58 UTC 2017 boundaryCRC - 25798b3e + 778c5560 boundaryCRCversion @@ -377,7 +407,7 @@ boundaryCRC - 25798b3e + 778c5560 boundaryCRCversion @@ -404,11 +434,11 @@ GENtimestamp - Fri Feb 24 23:58:23 UTC 2017 + Mon Mar 06 02:55:58 UTC 2017 boundaryCRC - 25798b3e + 778c5560 boundaryCRCversion @@ -434,41 +464,11 @@ GENtimestamp - Fri Feb 24 23:58:24 UTC 2017 - - - boundaryCRC - 25798b3e - - - boundaryCRCversion - 1 - - - customizationCRC - 853e16c8 - - - customizationCRCversion - 6 - - - - - xilinx_externalfiles - External Files - :vivado.xilinx.com:external.files - - xilinx_externalfiles_view_fileset - - - - GENtimestamp - Sat Feb 25 00:04:26 UTC 2017 + Mon Mar 06 02:55:58 UTC 2017 boundaryCRC - 25798b3e + 778c5560 boundaryCRCversion @@ -711,6 +711,42 @@ + + xilinx_externalfiles_view_fileset + + Arty_Z7_20_rst_processing_system7_0_142M_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + Arty_Z7_20_rst_processing_system7_0_142M_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Arty_Z7_20_rst_processing_system7_0_142M_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Arty_Z7_20_rst_processing_system7_0_142M_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Arty_Z7_20_rst_processing_system7_0_142M_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + xilinx_vhdlsynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset @@ -799,42 +835,6 @@ USED_IN_synthesis - - xilinx_externalfiles_view_fileset - - Arty_Z7_20_rst_processing_system7_0_142M_0.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - Arty_Z7_20_rst_processing_system7_0_142M_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - Arty_Z7_20_rst_processing_system7_0_142M_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - Arty_Z7_20_rst_processing_system7_0_142M_0_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - Arty_Z7_20_rst_processing_system7_0_142M_0_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - Processor Reset System diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_rst_processing_system7_0_142M_0/Arty_Z7_20_rst_processing_system7_0_142M_0_ooc.xdc b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_rst_processing_system7_0_142M_0/Arty_Z7_20_rst_processing_system7_0_142M_0_ooc.xdc index 0c103d7..8c0c12e 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_rst_processing_system7_0_142M_0/Arty_Z7_20_rst_processing_system7_0_142M_0_ooc.xdc +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_rst_processing_system7_0_142M_0/Arty_Z7_20_rst_processing_system7_0_142M_0_ooc.xdc @@ -52,6 +52,6 @@ # ######################################################### -create_clock -period 7 -name slowest_sync_clk [get_ports slowest_sync_clk] +create_clock -period 8.462 -name slowest_sync_clk [get_ports slowest_sync_clk] diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0.dcp b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0.dcp index e023afb..24324dc 100644 Binary files a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0.dcp and b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0.dcp differ diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0.xci b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0.xci index 536f5aa..8817175 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0.xci +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0.xci @@ -12,7 +12,7 @@ S_AXI:M_AXI ARESETN Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 - 142857132 + 118181816 0.000 32 0 @@ -20,7 +20,7 @@ 0 Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 64 - 142857132 + 118181816 0 0 0 @@ -31,13 +31,13 @@ 1 0 0 - 16 - 8 + 32 + 2 1 8 1 0.000 - AXI3 + AXI4 READ_ONLY 0 0 @@ -52,7 +52,7 @@ 0 Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 64 - 142857132 + 118181816 0 0 0 @@ -63,13 +63,13 @@ 1 0 0 - 16 - 8 + 32 + 2 1 8 1 0.000 - AXI3 + AXI4 READ_ONLY 0 0 @@ -82,7 +82,7 @@ 1 64 1 - 1 + 0 1 512 bram @@ -100,7 +100,7 @@ Arty_Z7_20_s00_data_fifo_0 64 0 - AXI3 + AXI4 1 512 READ_ONLY @@ -119,7 +119,7 @@ TRUE TRUE - 9242d93e3afba731 + 638eef6dd9c6a322 IP_Integrator 10 TRUE @@ -148,11 +148,12 @@ + - + - + @@ -168,20 +169,20 @@ - + - - - + + + - + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0.xml b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0.xml index dd783c0..d21e756 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0.xml +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0.xml @@ -380,11 +380,11 @@ PROTOCOL - AXI3 + AXI4 FREQ_HZ - 142857132 + 118181816 ID_WIDTH @@ -460,7 +460,7 @@ NUM_READ_OUTSTANDING - 8 + 2 NUM_WRITE_OUTSTANDING @@ -468,7 +468,7 @@ MAX_BURST_LENGTH - 16 + 32 PHASE @@ -871,11 +871,11 @@ PROTOCOL - AXI3 + AXI4 FREQ_HZ - 142857132 + 118181816 ID_WIDTH @@ -951,7 +951,7 @@ NUM_READ_OUTSTANDING - 8 + 2 NUM_WRITE_OUTSTANDING @@ -959,7 +959,7 @@ MAX_BURST_LENGTH - 16 + 32 PHASE @@ -1008,7 +1008,7 @@ FREQ_HZ aclk frequency aclk frequency - 142857132 + 118181816 PHASE @@ -1078,11 +1078,11 @@ GENtimestamp - Mon Feb 27 18:05:27 UTC 2017 + Mon Mar 06 19:44:19 UTC 2017 boundaryCRC - 68828508 + 54441c18 boundaryCRCversion @@ -1090,7 +1090,7 @@ customizationCRC - 6d73f585 + ea6b559e customizationCRCversion @@ -1108,11 +1108,11 @@ GENtimestamp - Mon Feb 27 18:05:27 UTC 2017 + Mon Mar 06 19:44:19 UTC 2017 boundaryCRC - 68828508 + 54441c18 boundaryCRCversion @@ -1120,7 +1120,7 @@ customizationCRC - 6d73f585 + ea6b559e customizationCRCversion @@ -1139,11 +1139,11 @@ GENtimestamp - Mon Feb 27 18:05:27 UTC 2017 + Mon Mar 06 19:44:19 UTC 2017 boundaryCRC - 68828508 + 54441c18 boundaryCRCversion @@ -1151,7 +1151,7 @@ customizationCRC - 6d73f585 + ea6b559e customizationCRCversion @@ -1180,7 +1180,7 @@ boundaryCRC - 68828508 + 54441c18 boundaryCRCversion @@ -1188,7 +1188,7 @@ customizationCRC - c38145c4 + a24610d8 customizationCRCversion @@ -1207,11 +1207,11 @@ GENtimestamp - Mon Feb 27 18:05:27 UTC 2017 + Mon Mar 06 19:44:19 UTC 2017 boundaryCRC - 68828508 + 54441c18 boundaryCRCversion @@ -1219,7 +1219,7 @@ customizationCRC - c38145c4 + a24610d8 customizationCRCversion @@ -1237,11 +1237,11 @@ GENtimestamp - Mon Feb 27 18:05:33 UTC 2017 + Mon Mar 06 19:44:25 UTC 2017 boundaryCRC - 68828508 + 54441c18 boundaryCRCversion @@ -1249,7 +1249,7 @@ customizationCRC - 6d73f585 + ea6b559e customizationCRCversion @@ -1344,7 +1344,7 @@ in - 3 + 7 0 @@ -1355,7 +1355,7 @@ - 0x0 + 0x00 @@ -1425,7 +1425,7 @@ in - 1 + 0 0 @@ -1973,7 +1973,7 @@ in - 3 + 7 0 @@ -1984,7 +1984,7 @@ - 0x0 + 0x00 @@ -2054,7 +2054,7 @@ in - 1 + 0 0 @@ -2152,7 +2152,7 @@ - false + true @@ -2466,7 +2466,7 @@ out - 3 + 7 0 @@ -2538,7 +2538,7 @@ out - 1 + 0 0 @@ -3056,7 +3056,7 @@ out - 3 + 7 0 @@ -3128,7 +3128,7 @@ out - 1 + 0 0 @@ -3214,7 +3214,7 @@ - false + true @@ -3492,7 +3492,7 @@ C_AXI_PROTOCOL - 1 + 0 C_AXI_ID_WIDTH @@ -3773,7 +3773,7 @@ PROTOCOL PROTOCOL - AXI3 + AXI4 READ_WRITE_MODE @@ -3866,11 +3866,12 @@ + - + - + @@ -3886,20 +3887,20 @@ - + - - - + + + - + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0_ooc.xdc b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0_ooc.xdc index ab4e818..6259de8 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0_ooc.xdc +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0_ooc.xdc @@ -52,6 +52,6 @@ # ######################################################### -create_clock -period 7 -name aclk [get_ports aclk] +create_clock -period 8.462 -name aclk [get_ports aclk] diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0_sim_netlist.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0_sim_netlist.v index 570b34b..b2ee807 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0_sim_netlist.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0_sim_netlist.v @@ -1,7 +1,7 @@ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -// Date : Fri Feb 24 16:02:52 2017 +// Date : Sat Mar 04 18:59:58 2017 // Host : WK73 running 64-bit Service Pack 1 (build 7601) // Command : write_verilog -force -mode funcsim -rename_top Arty_Z7_20_s00_data_fifo_0 -prefix // Arty_Z7_20_s00_data_fifo_0_ Arty_Z7_20_s00_data_fifo_0_sim_netlist.v @@ -24,6 +24,7 @@ module Arty_Z7_20_s00_data_fifo_0 s_axi_arlock, s_axi_arcache, s_axi_arprot, + s_axi_arregion, s_axi_arqos, s_axi_arvalid, s_axi_arready, @@ -39,6 +40,7 @@ module Arty_Z7_20_s00_data_fifo_0 m_axi_arlock, m_axi_arcache, m_axi_arprot, + m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, @@ -50,12 +52,13 @@ module Arty_Z7_20_s00_data_fifo_0 (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *) input aclk; (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *) input aresetn; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [31:0]s_axi_araddr; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [3:0]s_axi_arlen; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [7:0]s_axi_arlen; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input [1:0]s_axi_arlock; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input [0:0]s_axi_arlock; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *) input [3:0]s_axi_arregion; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) input [3:0]s_axi_arqos; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready; @@ -65,12 +68,13 @@ module Arty_Z7_20_s00_data_fifo_0 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output [31:0]m_axi_araddr; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *) output [3:0]m_axi_arlen; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *) output [7:0]m_axi_arlen; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *) output [2:0]m_axi_arsize; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *) output [1:0]m_axi_arburst; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *) output [1:0]m_axi_arlock; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *) output [0:0]m_axi_arlock; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *) output [3:0]m_axi_arcache; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output [2:0]m_axi_arprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *) output [3:0]m_axi_arregion; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *) output [3:0]m_axi_arqos; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output m_axi_arvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input m_axi_arready; @@ -85,11 +89,12 @@ module Arty_Z7_20_s00_data_fifo_0 wire [31:0]m_axi_araddr; wire [1:0]m_axi_arburst; wire [3:0]m_axi_arcache; - wire [3:0]m_axi_arlen; - wire [1:0]m_axi_arlock; + wire [7:0]m_axi_arlen; + wire [0:0]m_axi_arlock; wire [2:0]m_axi_arprot; wire [3:0]m_axi_arqos; wire m_axi_arready; + wire [3:0]m_axi_arregion; wire [2:0]m_axi_arsize; wire m_axi_arvalid; wire [63:0]m_axi_rdata; @@ -100,11 +105,12 @@ module Arty_Z7_20_s00_data_fifo_0 wire [31:0]s_axi_araddr; wire [1:0]s_axi_arburst; wire [3:0]s_axi_arcache; - wire [3:0]s_axi_arlen; - wire [1:0]s_axi_arlock; + wire [7:0]s_axi_arlen; + wire [0:0]s_axi_arlock; wire [2:0]s_axi_arprot; wire [3:0]s_axi_arqos; wire s_axi_arready; + wire [3:0]s_axi_arregion; wire [2:0]s_axi_arsize; wire s_axi_arvalid; wire [63:0]s_axi_rdata; @@ -120,14 +126,13 @@ module Arty_Z7_20_s00_data_fifo_0 wire NLW_inst_s_axi_bvalid_UNCONNECTED; wire NLW_inst_s_axi_wready_UNCONNECTED; wire [0:0]NLW_inst_m_axi_arid_UNCONNECTED; - wire [3:0]NLW_inst_m_axi_arregion_UNCONNECTED; wire [0:0]NLW_inst_m_axi_aruser_UNCONNECTED; wire [31:0]NLW_inst_m_axi_awaddr_UNCONNECTED; wire [1:0]NLW_inst_m_axi_awburst_UNCONNECTED; wire [3:0]NLW_inst_m_axi_awcache_UNCONNECTED; wire [0:0]NLW_inst_m_axi_awid_UNCONNECTED; - wire [3:0]NLW_inst_m_axi_awlen_UNCONNECTED; - wire [1:0]NLW_inst_m_axi_awlock_UNCONNECTED; + wire [7:0]NLW_inst_m_axi_awlen_UNCONNECTED; + wire [0:0]NLW_inst_m_axi_awlock_UNCONNECTED; wire [2:0]NLW_inst_m_axi_awprot_UNCONNECTED; wire [3:0]NLW_inst_m_axi_awqos_UNCONNECTED; wire [3:0]NLW_inst_m_axi_awregion_UNCONNECTED; @@ -149,7 +154,7 @@ module Arty_Z7_20_s00_data_fifo_0 (* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) - (* C_AXI_PROTOCOL = "1" *) + (* C_AXI_PROTOCOL = "0" *) (* C_AXI_READ_FIFO_DELAY = "1" *) (* C_AXI_READ_FIFO_DEPTH = "512" *) (* C_AXI_READ_FIFO_TYPE = "bram" *) @@ -165,10 +170,10 @@ module Arty_Z7_20_s00_data_fifo_0 (* P_AXILITE = "2" *) (* P_PRIM_FIFO_TYPE = "512x72" *) (* P_READ_FIFO_DEPTH_LOG = "9" *) - (* P_WIDTH_RACH = "60" *) + (* P_WIDTH_RACH = "63" *) (* P_WIDTH_RDCH = "69" *) - (* P_WIDTH_WACH = "60" *) - (* P_WIDTH_WDCH = "75" *) + (* P_WIDTH_WACH = "63" *) + (* P_WIDTH_WDCH = "74" *) (* P_WIDTH_WRCH = "4" *) (* P_WRITE_FIFO_DEPTH_LOG = "1" *) (* downgradeipidentifiedwarnings = "yes" *) @@ -184,7 +189,7 @@ module Arty_Z7_20_s00_data_fifo_0 .m_axi_arprot(m_axi_arprot), .m_axi_arqos(m_axi_arqos), .m_axi_arready(m_axi_arready), - .m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[3:0]), + .m_axi_arregion(m_axi_arregion), .m_axi_arsize(m_axi_arsize), .m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[0]), .m_axi_arvalid(m_axi_arvalid), @@ -192,8 +197,8 @@ module Arty_Z7_20_s00_data_fifo_0 .m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[1:0]), .m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[3:0]), .m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[0]), - .m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[3:0]), - .m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[1:0]), + .m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[7:0]), + .m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[0]), .m_axi_awprot(NLW_inst_m_axi_awprot_UNCONNECTED[2:0]), .m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[3:0]), .m_axi_awready(1'b0), @@ -229,7 +234,7 @@ module Arty_Z7_20_s00_data_fifo_0 .s_axi_arprot(s_axi_arprot), .s_axi_arqos(s_axi_arqos), .s_axi_arready(s_axi_arready), - .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arregion(s_axi_arregion), .s_axi_arsize(s_axi_arsize), .s_axi_aruser(1'b0), .s_axi_arvalid(s_axi_arvalid), @@ -237,8 +242,8 @@ module Arty_Z7_20_s00_data_fifo_0 .s_axi_awburst({1'b0,1'b1}), .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}), .s_axi_awid(1'b0), - .s_axi_awlen({1'b0,1'b0,1'b0,1'b0}), - .s_axi_awlock({1'b0,1'b0}), + .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_awlock(1'b0), .s_axi_awprot({1'b0,1'b0,1'b0}), .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}), .s_axi_awready(NLW_inst_s_axi_awready_UNCONNECTED), @@ -269,13 +274,13 @@ endmodule (* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) -(* C_AXI_PROTOCOL = "1" *) (* C_AXI_READ_FIFO_DELAY = "1" *) (* C_AXI_READ_FIFO_DEPTH = "512" *) +(* C_AXI_PROTOCOL = "0" *) (* C_AXI_READ_FIFO_DELAY = "1" *) (* C_AXI_READ_FIFO_DEPTH = "512" *) (* C_AXI_READ_FIFO_TYPE = "bram" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *) (* C_AXI_WRITE_FIFO_DELAY = "0" *) (* C_AXI_WRITE_FIFO_DEPTH = "0" *) (* C_AXI_WRITE_FIFO_TYPE = "lut" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_FAMILY = "zynq" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* P_AXI3 = "1" *) (* P_AXI4 = "0" *) (* P_AXILITE = "2" *) -(* P_PRIM_FIFO_TYPE = "512x72" *) (* P_READ_FIFO_DEPTH_LOG = "9" *) (* P_WIDTH_RACH = "60" *) -(* P_WIDTH_RDCH = "69" *) (* P_WIDTH_WACH = "60" *) (* P_WIDTH_WDCH = "75" *) +(* P_PRIM_FIFO_TYPE = "512x72" *) (* P_READ_FIFO_DEPTH_LOG = "9" *) (* P_WIDTH_RACH = "63" *) +(* P_WIDTH_RDCH = "69" *) (* P_WIDTH_WACH = "63" *) (* P_WIDTH_WDCH = "74" *) (* P_WIDTH_WRCH = "4" *) (* P_WRITE_FIFO_DEPTH_LOG = "1" *) module Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo (aclk, @@ -374,10 +379,10 @@ module Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo input aresetn; input [0:0]s_axi_awid; input [31:0]s_axi_awaddr; - input [3:0]s_axi_awlen; + input [7:0]s_axi_awlen; input [2:0]s_axi_awsize; input [1:0]s_axi_awburst; - input [1:0]s_axi_awlock; + input [0:0]s_axi_awlock; input [3:0]s_axi_awcache; input [2:0]s_axi_awprot; input [3:0]s_axi_awregion; @@ -399,10 +404,10 @@ module Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo input s_axi_bready; input [0:0]s_axi_arid; input [31:0]s_axi_araddr; - input [3:0]s_axi_arlen; + input [7:0]s_axi_arlen; input [2:0]s_axi_arsize; input [1:0]s_axi_arburst; - input [1:0]s_axi_arlock; + input [0:0]s_axi_arlock; input [3:0]s_axi_arcache; input [2:0]s_axi_arprot; input [3:0]s_axi_arregion; @@ -419,10 +424,10 @@ module Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo input s_axi_rready; output [0:0]m_axi_awid; output [31:0]m_axi_awaddr; - output [3:0]m_axi_awlen; + output [7:0]m_axi_awlen; output [2:0]m_axi_awsize; output [1:0]m_axi_awburst; - output [1:0]m_axi_awlock; + output [0:0]m_axi_awlock; output [3:0]m_axi_awcache; output [2:0]m_axi_awprot; output [3:0]m_axi_awregion; @@ -444,10 +449,10 @@ module Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo output m_axi_bready; output [0:0]m_axi_arid; output [31:0]m_axi_araddr; - output [3:0]m_axi_arlen; + output [7:0]m_axi_arlen; output [2:0]m_axi_arsize; output [1:0]m_axi_arburst; - output [1:0]m_axi_arlock; + output [0:0]m_axi_arlock; output [3:0]m_axi_arcache; output [2:0]m_axi_arprot; output [3:0]m_axi_arregion; @@ -470,11 +475,12 @@ module Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo wire [1:0]m_axi_arburst; wire [3:0]m_axi_arcache; wire [0:0]m_axi_arid; - wire [3:0]m_axi_arlen; - wire [1:0]m_axi_arlock; + wire [7:0]m_axi_arlen; + wire [0:0]m_axi_arlock; wire [2:0]m_axi_arprot; wire [3:0]m_axi_arqos; wire m_axi_arready; + wire [3:0]m_axi_arregion; wire [2:0]m_axi_arsize; wire [0:0]m_axi_aruser; wire m_axi_arvalid; @@ -495,11 +501,12 @@ module Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo wire [1:0]s_axi_arburst; wire [3:0]s_axi_arcache; wire [0:0]s_axi_arid; - wire [3:0]s_axi_arlen; - wire [1:0]s_axi_arlock; + wire [7:0]s_axi_arlen; + wire [0:0]s_axi_arlock; wire [2:0]s_axi_arprot; wire [3:0]s_axi_arqos; wire s_axi_arready; + wire [3:0]s_axi_arregion; wire [2:0]s_axi_arsize; wire [0:0]s_axi_aruser; wire s_axi_arvalid; @@ -507,10 +514,11 @@ module Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo wire [1:0]s_axi_awburst; wire [3:0]s_axi_awcache; wire [0:0]s_axi_awid; - wire [3:0]s_axi_awlen; - wire [1:0]s_axi_awlock; + wire [7:0]s_axi_awlen; + wire [0:0]s_axi_awlock; wire [2:0]s_axi_awprot; wire [3:0]s_axi_awqos; + wire [3:0]s_axi_awregion; wire [2:0]s_axi_awsize; wire [0:0]s_axi_awuser; wire s_axi_awvalid; @@ -523,7 +531,6 @@ module Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo wire [0:0]s_axi_ruser; wire s_axi_rvalid; wire [63:0]s_axi_wdata; - wire [0:0]s_axi_wid; wire s_axi_wlast; wire [7:0]s_axi_wstrb; wire [0:0]s_axi_wuser; @@ -608,13 +615,12 @@ module Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo wire [10:0]\NLW_gen_fifo.fifo_gen_inst_axis_wr_data_count_UNCONNECTED ; wire [9:0]\NLW_gen_fifo.fifo_gen_inst_data_count_UNCONNECTED ; wire [17:0]\NLW_gen_fifo.fifo_gen_inst_dout_UNCONNECTED ; - wire [3:0]\NLW_gen_fifo.fifo_gen_inst_m_axi_arregion_UNCONNECTED ; wire [31:0]\NLW_gen_fifo.fifo_gen_inst_m_axi_awaddr_UNCONNECTED ; wire [1:0]\NLW_gen_fifo.fifo_gen_inst_m_axi_awburst_UNCONNECTED ; wire [3:0]\NLW_gen_fifo.fifo_gen_inst_m_axi_awcache_UNCONNECTED ; wire [0:0]\NLW_gen_fifo.fifo_gen_inst_m_axi_awid_UNCONNECTED ; - wire [3:0]\NLW_gen_fifo.fifo_gen_inst_m_axi_awlen_UNCONNECTED ; - wire [1:0]\NLW_gen_fifo.fifo_gen_inst_m_axi_awlock_UNCONNECTED ; + wire [7:0]\NLW_gen_fifo.fifo_gen_inst_m_axi_awlen_UNCONNECTED ; + wire [0:0]\NLW_gen_fifo.fifo_gen_inst_m_axi_awlock_UNCONNECTED ; wire [2:0]\NLW_gen_fifo.fifo_gen_inst_m_axi_awprot_UNCONNECTED ; wire [3:0]\NLW_gen_fifo.fifo_gen_inst_m_axi_awqos_UNCONNECTED ; wire [3:0]\NLW_gen_fifo.fifo_gen_inst_m_axi_awregion_UNCONNECTED ; @@ -636,28 +642,21 @@ module Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo wire [0:0]\NLW_gen_fifo.fifo_gen_inst_s_axi_buser_UNCONNECTED ; wire [9:0]\NLW_gen_fifo.fifo_gen_inst_wr_data_count_UNCONNECTED ; - assign m_axi_arregion[3] = \ ; - assign m_axi_arregion[2] = \ ; - assign m_axi_arregion[1] = \ ; - assign m_axi_arregion[0] = \ ; assign m_axi_awaddr[31:0] = s_axi_awaddr; assign m_axi_awburst[1:0] = s_axi_awburst; assign m_axi_awcache[3:0] = s_axi_awcache; assign m_axi_awid[0] = s_axi_awid; - assign m_axi_awlen[3:0] = s_axi_awlen; - assign m_axi_awlock[1:0] = s_axi_awlock; + assign m_axi_awlen[7:0] = s_axi_awlen; + assign m_axi_awlock[0] = s_axi_awlock; assign m_axi_awprot[2:0] = s_axi_awprot; assign m_axi_awqos[3:0] = s_axi_awqos; - assign m_axi_awregion[3] = \ ; - assign m_axi_awregion[2] = \ ; - assign m_axi_awregion[1] = \ ; - assign m_axi_awregion[0] = \ ; + assign m_axi_awregion[3:0] = s_axi_awregion; assign m_axi_awsize[2:0] = s_axi_awsize; assign m_axi_awuser[0] = s_axi_awuser; assign m_axi_awvalid = s_axi_awvalid; assign m_axi_bready = s_axi_bready; assign m_axi_wdata[63:0] = s_axi_wdata; - assign m_axi_wid[0] = s_axi_wid; + assign m_axi_wid[0] = \ ; assign m_axi_wlast = s_axi_wlast; assign m_axi_wstrb[7:0] = s_axi_wstrb; assign m_axi_wuser[0] = s_axi_wuser; @@ -690,10 +689,10 @@ module Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo (* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) - (* C_AXI_LEN_WIDTH = "4" *) - (* C_AXI_LOCK_WIDTH = "2" *) + (* C_AXI_LEN_WIDTH = "8" *) + (* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) - (* C_AXI_TYPE = "3" *) + (* C_AXI_TYPE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "1" *) (* C_COUNT_TYPE = "0" *) @@ -701,11 +700,11 @@ module Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "18" *) (* C_DIN_WIDTH_AXIS = "1" *) - (* C_DIN_WIDTH_RACH = "60" *) + (* C_DIN_WIDTH_RACH = "63" *) (* C_DIN_WIDTH_RDCH = "69" *) - (* C_DIN_WIDTH_WACH = "60" *) - (* C_DIN_WIDTH_WDCH = "75" *) - (* C_DIN_WIDTH_WRCH = "75" *) + (* C_DIN_WIDTH_WACH = "63" *) + (* C_DIN_WIDTH_WDCH = "74" *) + (* C_DIN_WIDTH_WRCH = "74" *) (* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "18" *) (* C_ENABLE_RLOCS = "0" *) @@ -976,7 +975,7 @@ module Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo .m_axi_arprot(m_axi_arprot), .m_axi_arqos(m_axi_arqos), .m_axi_arready(m_axi_arready), - .m_axi_arregion(\NLW_gen_fifo.fifo_gen_inst_m_axi_arregion_UNCONNECTED [3:0]), + .m_axi_arregion(m_axi_arregion), .m_axi_arsize(m_axi_arsize), .m_axi_aruser(m_axi_aruser), .m_axi_arvalid(m_axi_arvalid), @@ -984,8 +983,8 @@ module Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo .m_axi_awburst(\NLW_gen_fifo.fifo_gen_inst_m_axi_awburst_UNCONNECTED [1:0]), .m_axi_awcache(\NLW_gen_fifo.fifo_gen_inst_m_axi_awcache_UNCONNECTED [3:0]), .m_axi_awid(\NLW_gen_fifo.fifo_gen_inst_m_axi_awid_UNCONNECTED [0]), - .m_axi_awlen(\NLW_gen_fifo.fifo_gen_inst_m_axi_awlen_UNCONNECTED [3:0]), - .m_axi_awlock(\NLW_gen_fifo.fifo_gen_inst_m_axi_awlock_UNCONNECTED [1:0]), + .m_axi_awlen(\NLW_gen_fifo.fifo_gen_inst_m_axi_awlen_UNCONNECTED [7:0]), + .m_axi_awlock(\NLW_gen_fifo.fifo_gen_inst_m_axi_awlock_UNCONNECTED [0]), .m_axi_awprot(\NLW_gen_fifo.fifo_gen_inst_m_axi_awprot_UNCONNECTED [2:0]), .m_axi_awqos(\NLW_gen_fifo.fifo_gen_inst_m_axi_awqos_UNCONNECTED [3:0]), .m_axi_awready(1'b0), @@ -1048,7 +1047,7 @@ module Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo .s_axi_arprot(s_axi_arprot), .s_axi_arqos(s_axi_arqos), .s_axi_arready(s_axi_arready), - .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arregion(s_axi_arregion), .s_axi_arsize(s_axi_arsize), .s_axi_aruser(s_axi_aruser), .s_axi_arvalid(s_axi_arvalid), @@ -1056,8 +1055,8 @@ module Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo .s_axi_awburst({1'b0,1'b0}), .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}), .s_axi_awid(1'b0), - .s_axi_awlen({1'b0,1'b0,1'b0,1'b0}), - .s_axi_awlock({1'b0,1'b0}), + .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_awlock(1'b0), .s_axi_awprot({1'b0,1'b0,1'b0}), .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}), .s_axi_awready(\NLW_gen_fifo.fifo_gen_inst_s_axi_awready_UNCONNECTED ), @@ -1121,25 +1120,25 @@ module Arty_Z7_20_s00_data_fifo_0_axi_reg_slice output inverted_reset; output arready_pkt; output m_axi_arvalid; - output [55:0]UNCONN_OUT; + output [62:0]UNCONN_OUT; input s_aclk; input m_axi_arready; input s_aresetn; input [0:0]CO; input out; input \gfwd_rev_pipeline1.s_ready_i_reg_0 ; - input [55:0]D; + input [62:0]D; wire [0:0]CO; - wire [55:0]D; - wire [55:0]UNCONN_OUT; + wire [62:0]D; + wire [62:0]UNCONN_OUT; wire areset_d1; wire arready_pkt; wire extnd_reset; wire \gfwd_rev_pipeline1.m_valid_i_i_1_n_0 ; wire \gfwd_rev_pipeline1.s_ready_i_i_2_n_0 ; wire \gfwd_rev_pipeline1.s_ready_i_reg_0 ; - wire \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ; + wire \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ; wire inverted_reset; wire m_axi_arready; wire m_axi_arvalid; @@ -1158,11 +1157,11 @@ module Arty_Z7_20_s00_data_fifo_0_axi_reg_slice .Q(areset_d1), .R(1'b0)); LUT6 #( - .INIT(64'h000000000000F035)) + .INIT(64'h000000000000CC2E)) \gfwd_rev_pipeline1.m_valid_i_i_1 (.I0(\gfwd_rev_pipeline1.s_ready_i_reg_0 ), - .I1(m_axi_arready), - .I2(m_axi_arvalid), + .I1(m_axi_arvalid), + .I2(m_axi_arready), .I3(areset_d1), .I4(p_0_in), .I5(extnd_reset), @@ -1176,11 +1175,11 @@ module Arty_Z7_20_s00_data_fifo_0_axi_reg_slice .Q(m_axi_arvalid), .R(1'b0)); LUT3 #( - .INIT(8'hF8)) + .INIT(8'hEA)) \gfwd_rev_pipeline1.s_ready_i_i_2 - (.I0(m_axi_arready), + (.I0(areset_d1), .I1(m_axi_arvalid), - .I2(areset_d1), + .I2(m_axi_arready), .O(\gfwd_rev_pipeline1.s_ready_i_i_2_n_0 )); FDRE #( .INIT(1'b0)) @@ -1192,462 +1191,518 @@ module Arty_Z7_20_s00_data_fifo_0_axi_reg_slice .R(1'b0)); LUT1 #( .INIT(2'h1)) - \gfwd_rev_pipeline1.storage_data1[59]_i_1 + \gfwd_rev_pipeline1.storage_data1[62]_i_1 (.I0(m_axi_arvalid), - .O(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 )); - FDRE #( - .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[10] - (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), - .D(D[6]), - .Q(UNCONN_OUT[6]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[11] - (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), - .D(D[7]), - .Q(UNCONN_OUT[7]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[12] - (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), - .D(D[8]), - .Q(UNCONN_OUT[8]), - .R(1'b0)); + .O(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 )); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[13] + \gfwd_rev_pipeline1.storage_data1_reg[0] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), - .D(D[9]), - .Q(UNCONN_OUT[9]), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), + .D(D[0]), + .Q(UNCONN_OUT[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[14] + \gfwd_rev_pipeline1.storage_data1_reg[10] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[10]), .Q(UNCONN_OUT[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[15] + \gfwd_rev_pipeline1.storage_data1_reg[11] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[11]), .Q(UNCONN_OUT[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[16] + \gfwd_rev_pipeline1.storage_data1_reg[12] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[12]), .Q(UNCONN_OUT[12]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[17] + \gfwd_rev_pipeline1.storage_data1_reg[13] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[13]), .Q(UNCONN_OUT[13]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[18] + \gfwd_rev_pipeline1.storage_data1_reg[14] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[14]), .Q(UNCONN_OUT[14]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[19] + \gfwd_rev_pipeline1.storage_data1_reg[15] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[15]), .Q(UNCONN_OUT[15]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[20] + \gfwd_rev_pipeline1.storage_data1_reg[16] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[16]), .Q(UNCONN_OUT[16]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[21] + \gfwd_rev_pipeline1.storage_data1_reg[17] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[17]), .Q(UNCONN_OUT[17]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[22] + \gfwd_rev_pipeline1.storage_data1_reg[18] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[18]), .Q(UNCONN_OUT[18]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[23] + \gfwd_rev_pipeline1.storage_data1_reg[19] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[19]), .Q(UNCONN_OUT[19]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[24] + \gfwd_rev_pipeline1.storage_data1_reg[1] + (.C(s_aclk), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), + .D(D[1]), + .Q(UNCONN_OUT[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gfwd_rev_pipeline1.storage_data1_reg[20] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[20]), .Q(UNCONN_OUT[20]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[25] + \gfwd_rev_pipeline1.storage_data1_reg[21] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[21]), .Q(UNCONN_OUT[21]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[26] + \gfwd_rev_pipeline1.storage_data1_reg[22] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[22]), .Q(UNCONN_OUT[22]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[27] + \gfwd_rev_pipeline1.storage_data1_reg[23] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[23]), .Q(UNCONN_OUT[23]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[28] + \gfwd_rev_pipeline1.storage_data1_reg[24] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[24]), .Q(UNCONN_OUT[24]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[29] + \gfwd_rev_pipeline1.storage_data1_reg[25] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[25]), .Q(UNCONN_OUT[25]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[30] + \gfwd_rev_pipeline1.storage_data1_reg[26] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[26]), .Q(UNCONN_OUT[26]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[31] + \gfwd_rev_pipeline1.storage_data1_reg[27] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[27]), .Q(UNCONN_OUT[27]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[32] + \gfwd_rev_pipeline1.storage_data1_reg[28] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[28]), .Q(UNCONN_OUT[28]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[33] + \gfwd_rev_pipeline1.storage_data1_reg[29] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[29]), .Q(UNCONN_OUT[29]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[34] + \gfwd_rev_pipeline1.storage_data1_reg[2] + (.C(s_aclk), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), + .D(D[2]), + .Q(UNCONN_OUT[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gfwd_rev_pipeline1.storage_data1_reg[30] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[30]), .Q(UNCONN_OUT[30]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[35] + \gfwd_rev_pipeline1.storage_data1_reg[31] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[31]), .Q(UNCONN_OUT[31]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[36] + \gfwd_rev_pipeline1.storage_data1_reg[32] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[32]), .Q(UNCONN_OUT[32]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[37] + \gfwd_rev_pipeline1.storage_data1_reg[33] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[33]), .Q(UNCONN_OUT[33]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[38] + \gfwd_rev_pipeline1.storage_data1_reg[34] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[34]), .Q(UNCONN_OUT[34]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[39] + \gfwd_rev_pipeline1.storage_data1_reg[35] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[35]), .Q(UNCONN_OUT[35]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[40] + \gfwd_rev_pipeline1.storage_data1_reg[36] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[36]), .Q(UNCONN_OUT[36]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[41] + \gfwd_rev_pipeline1.storage_data1_reg[37] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[37]), .Q(UNCONN_OUT[37]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[42] + \gfwd_rev_pipeline1.storage_data1_reg[38] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[38]), .Q(UNCONN_OUT[38]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[43] + \gfwd_rev_pipeline1.storage_data1_reg[39] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[39]), .Q(UNCONN_OUT[39]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[44] + \gfwd_rev_pipeline1.storage_data1_reg[3] + (.C(s_aclk), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), + .D(D[3]), + .Q(UNCONN_OUT[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gfwd_rev_pipeline1.storage_data1_reg[40] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[40]), .Q(UNCONN_OUT[40]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[45] + \gfwd_rev_pipeline1.storage_data1_reg[41] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[41]), .Q(UNCONN_OUT[41]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[46] + \gfwd_rev_pipeline1.storage_data1_reg[42] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[42]), .Q(UNCONN_OUT[42]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[47] + \gfwd_rev_pipeline1.storage_data1_reg[43] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[43]), .Q(UNCONN_OUT[43]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[48] + \gfwd_rev_pipeline1.storage_data1_reg[44] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[44]), .Q(UNCONN_OUT[44]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[49] + \gfwd_rev_pipeline1.storage_data1_reg[45] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[45]), .Q(UNCONN_OUT[45]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[4] - (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), - .D(D[0]), - .Q(UNCONN_OUT[0]), - .R(1'b0)); - FDRE #( - .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[50] + \gfwd_rev_pipeline1.storage_data1_reg[46] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[46]), .Q(UNCONN_OUT[46]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[51] + \gfwd_rev_pipeline1.storage_data1_reg[47] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[47]), .Q(UNCONN_OUT[47]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[52] + \gfwd_rev_pipeline1.storage_data1_reg[48] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[48]), .Q(UNCONN_OUT[48]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[53] + \gfwd_rev_pipeline1.storage_data1_reg[49] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[49]), .Q(UNCONN_OUT[49]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[54] + \gfwd_rev_pipeline1.storage_data1_reg[4] + (.C(s_aclk), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), + .D(D[4]), + .Q(UNCONN_OUT[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gfwd_rev_pipeline1.storage_data1_reg[50] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[50]), .Q(UNCONN_OUT[50]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[55] + \gfwd_rev_pipeline1.storage_data1_reg[51] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[51]), .Q(UNCONN_OUT[51]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[56] + \gfwd_rev_pipeline1.storage_data1_reg[52] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[52]), .Q(UNCONN_OUT[52]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[57] + \gfwd_rev_pipeline1.storage_data1_reg[53] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[53]), .Q(UNCONN_OUT[53]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[58] + \gfwd_rev_pipeline1.storage_data1_reg[54] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[54]), .Q(UNCONN_OUT[54]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \gfwd_rev_pipeline1.storage_data1_reg[59] + \gfwd_rev_pipeline1.storage_data1_reg[55] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), .D(D[55]), .Q(UNCONN_OUT[55]), .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gfwd_rev_pipeline1.storage_data1_reg[56] + (.C(s_aclk), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), + .D(D[56]), + .Q(UNCONN_OUT[56]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gfwd_rev_pipeline1.storage_data1_reg[57] + (.C(s_aclk), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), + .D(D[57]), + .Q(UNCONN_OUT[57]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gfwd_rev_pipeline1.storage_data1_reg[58] + (.C(s_aclk), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), + .D(D[58]), + .Q(UNCONN_OUT[58]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gfwd_rev_pipeline1.storage_data1_reg[59] + (.C(s_aclk), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), + .D(D[59]), + .Q(UNCONN_OUT[59]), + .R(1'b0)); FDRE #( .INIT(1'b0)) \gfwd_rev_pipeline1.storage_data1_reg[5] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), - .D(D[1]), - .Q(UNCONN_OUT[1]), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), + .D(D[5]), + .Q(UNCONN_OUT[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gfwd_rev_pipeline1.storage_data1_reg[60] + (.C(s_aclk), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), + .D(D[60]), + .Q(UNCONN_OUT[60]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gfwd_rev_pipeline1.storage_data1_reg[61] + (.C(s_aclk), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), + .D(D[61]), + .Q(UNCONN_OUT[61]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gfwd_rev_pipeline1.storage_data1_reg[62] + (.C(s_aclk), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), + .D(D[62]), + .Q(UNCONN_OUT[62]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gfwd_rev_pipeline1.storage_data1_reg[6] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), - .D(D[2]), - .Q(UNCONN_OUT[2]), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), + .D(D[6]), + .Q(UNCONN_OUT[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gfwd_rev_pipeline1.storage_data1_reg[7] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), - .D(D[3]), - .Q(UNCONN_OUT[3]), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), + .D(D[7]), + .Q(UNCONN_OUT[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gfwd_rev_pipeline1.storage_data1_reg[8] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), - .D(D[4]), - .Q(UNCONN_OUT[4]), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), + .D(D[8]), + .Q(UNCONN_OUT[8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gfwd_rev_pipeline1.storage_data1_reg[9] (.C(s_aclk), - .CE(\gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0 ), - .D(D[5]), - .Q(UNCONN_OUT[5]), + .CE(\gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0 ), + .D(D[9]), + .Q(UNCONN_OUT[9]), .R(1'b0)); Arty_Z7_20_s00_data_fifo_0_reset_blk_ramfifo__parameterized1 rstblk (.CO(CO), .arready_pkt(arready_pkt), .empty_fwft_i_reg(out), - .\gfwd_rev_pipeline1.m_valid_i_reg (\gfwd_rev_pipeline1.s_ready_i_i_2_n_0 ), + .\gfwd_rev_pipeline1.areset_d1_reg (\gfwd_rev_pipeline1.s_ready_i_i_2_n_0 ), .\gfwd_rev_pipeline1.s_ready_i_reg (rstblk_n_3), .\grstd1.grst_full.grst_f.rst_d3_reg_0 (extnd_reset), .\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg_0 (inverted_reset), @@ -2121,28 +2176,28 @@ endmodule (* ORIG_REF_NAME = "compare" *) module Arty_Z7_20_s00_data_fifo_0_compare__parameterized0 (comp0, - \gcc0.gc0.count_d1_reg[1] , - \gcc0.gc0.count_d1_reg[2] , - \gcc0.gc0.count_d1_reg[5] , - \gcc0.gc0.count_d1_reg[6] , - \gc0.count_d1_reg[8] ); + \gc0.count_d1_reg[0] , + \gc0.count_d1_reg[2] , + \gc0.count_d1_reg[5] , + \gc0.count_d1_reg[7] , + \gcc0.gc0.count_d1_reg[8] ); output comp0; - input \gcc0.gc0.count_d1_reg[1] ; - input \gcc0.gc0.count_d1_reg[2] ; - input \gcc0.gc0.count_d1_reg[5] ; - input \gcc0.gc0.count_d1_reg[6] ; - input \gc0.count_d1_reg[8] ; + input \gc0.count_d1_reg[0] ; + input \gc0.count_d1_reg[2] ; + input \gc0.count_d1_reg[5] ; + input \gc0.count_d1_reg[7] ; + input \gcc0.gc0.count_d1_reg[8] ; wire carrynet_0; wire carrynet_1; wire carrynet_2; wire carrynet_3; wire comp0; - wire \gc0.count_d1_reg[8] ; - wire \gcc0.gc0.count_d1_reg[1] ; - wire \gcc0.gc0.count_d1_reg[2] ; - wire \gcc0.gc0.count_d1_reg[5] ; - wire \gcc0.gc0.count_d1_reg[6] ; + wire \gc0.count_d1_reg[0] ; + wire \gc0.count_d1_reg[2] ; + wire \gc0.count_d1_reg[5] ; + wire \gc0.count_d1_reg[7] ; + wire \gcc0.gc0.count_d1_reg[8] ; wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; @@ -2157,7 +2212,7 @@ module Arty_Z7_20_s00_data_fifo_0_compare__parameterized0 .CYINIT(1'b1), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), - .S({\gcc0.gc0.count_d1_reg[6] ,\gcc0.gc0.count_d1_reg[5] ,\gcc0.gc0.count_d1_reg[2] ,\gcc0.gc0.count_d1_reg[1] })); + .S({\gc0.count_d1_reg[7] ,\gc0.count_d1_reg[5] ,\gc0.count_d1_reg[2] ,\gc0.count_d1_reg[0] })); (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) (* box_type = "PRIMITIVE" *) CARRY4 \gmux.gm[4].gms.ms_CARRY4 @@ -2166,32 +2221,26 @@ module Arty_Z7_20_s00_data_fifo_0_compare__parameterized0 .CYINIT(1'b0), .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}), .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), - .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],\gc0.count_d1_reg[8] })); + .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],\gcc0.gc0.count_d1_reg[8] })); endmodule (* ORIG_REF_NAME = "compare" *) module Arty_Z7_20_s00_data_fifo_0_compare__parameterized1 (ram_empty_i_reg, - \gcc0.gc0.count_d1_reg[0] , - \gcc0.gc0.count_d1_reg[3] , - \gcc0.gc0.count_d1_reg[4] , - \gcc0.gc0.count_d1_reg[6] , + v1_reg_1, \gc0.count_reg[8] , + \gpregsm1.curr_fwft_state_reg[1] , + comp0, ram_full_fb_i_reg, m_axi_rvalid, - \gpregsm1.curr_fwft_state_reg[0] , - comp0, out); output ram_empty_i_reg; - input \gcc0.gc0.count_d1_reg[0] ; - input \gcc0.gc0.count_d1_reg[3] ; - input \gcc0.gc0.count_d1_reg[4] ; - input \gcc0.gc0.count_d1_reg[6] ; + input [3:0]v1_reg_1; input \gc0.count_reg[8] ; + input \gpregsm1.curr_fwft_state_reg[1] ; + input comp0; input ram_full_fb_i_reg; input m_axi_rvalid; - input \gpregsm1.curr_fwft_state_reg[0] ; - input comp0; input out; wire carrynet_0; @@ -2201,15 +2250,12 @@ module Arty_Z7_20_s00_data_fifo_0_compare__parameterized1 wire comp0; wire comp1; wire \gc0.count_reg[8] ; - wire \gcc0.gc0.count_d1_reg[0] ; - wire \gcc0.gc0.count_d1_reg[3] ; - wire \gcc0.gc0.count_d1_reg[4] ; - wire \gcc0.gc0.count_d1_reg[6] ; - wire \gpregsm1.curr_fwft_state_reg[0] ; + wire \gpregsm1.curr_fwft_state_reg[1] ; wire m_axi_rvalid; wire out; wire ram_empty_i_reg; wire ram_full_fb_i_reg; + wire [3:0]v1_reg_1; wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; @@ -2224,7 +2270,7 @@ module Arty_Z7_20_s00_data_fifo_0_compare__parameterized1 .CYINIT(1'b1), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), - .S({\gcc0.gc0.count_d1_reg[6] ,\gcc0.gc0.count_d1_reg[4] ,\gcc0.gc0.count_d1_reg[3] ,\gcc0.gc0.count_d1_reg[0] })); + .S(v1_reg_1)); (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) (* box_type = "PRIMITIVE" *) CARRY4 \gmux.gm[4].gms.ms_CARRY4 @@ -2235,13 +2281,13 @@ module Arty_Z7_20_s00_data_fifo_0_compare__parameterized1 .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],\gc0.count_reg[8] })); LUT6 #( - .INIT(64'hCFCFFFFF8A008A00)) + .INIT(64'hFF0FFFFF22002222)) ram_empty_fb_i_i_1__0 (.I0(comp1), - .I1(ram_full_fb_i_reg), - .I2(m_axi_rvalid), - .I3(\gpregsm1.curr_fwft_state_reg[0] ), - .I4(comp0), + .I1(\gpregsm1.curr_fwft_state_reg[1] ), + .I2(comp0), + .I3(ram_full_fb_i_reg), + .I4(m_axi_rvalid), .I5(out), .O(ram_empty_i_reg)); endmodule @@ -2249,27 +2295,21 @@ endmodule (* ORIG_REF_NAME = "compare" *) module Arty_Z7_20_s00_data_fifo_0_compare__parameterized2 (ram_full_comb, - \gcc0.gc0.count_d1_reg[1] , - \gcc0.gc0.count_d1_reg[2] , - \gcc0.gc0.count_d1_reg[5] , - \gcc0.gc0.count_d1_reg[6] , - \gc0.count_d1_reg[8] , + v1_reg_0, + \gcc0.gc0.count_d1_reg[8] , \grstd1.grst_full.grst_f.rst_d3_reg , - ram_empty_fb_i_reg, - comp1, m_axi_rvalid, - out); + out, + comp1, + ram_empty_fb_i_reg); output ram_full_comb; - input \gcc0.gc0.count_d1_reg[1] ; - input \gcc0.gc0.count_d1_reg[2] ; - input \gcc0.gc0.count_d1_reg[5] ; - input \gcc0.gc0.count_d1_reg[6] ; - input \gc0.count_d1_reg[8] ; + input [3:0]v1_reg_0; + input \gcc0.gc0.count_d1_reg[8] ; input \grstd1.grst_full.grst_f.rst_d3_reg ; - input ram_empty_fb_i_reg; - input comp1; input m_axi_rvalid; input out; + input comp1; + input ram_empty_fb_i_reg; wire carrynet_0; wire carrynet_1; @@ -2277,16 +2317,13 @@ module Arty_Z7_20_s00_data_fifo_0_compare__parameterized2 wire carrynet_3; wire comp0; wire comp1; - wire \gc0.count_d1_reg[8] ; - wire \gcc0.gc0.count_d1_reg[1] ; - wire \gcc0.gc0.count_d1_reg[2] ; - wire \gcc0.gc0.count_d1_reg[5] ; - wire \gcc0.gc0.count_d1_reg[6] ; + wire \gcc0.gc0.count_d1_reg[8] ; wire \grstd1.grst_full.grst_f.rst_d3_reg ; wire m_axi_rvalid; wire out; wire ram_empty_fb_i_reg; wire ram_full_comb; + wire [3:0]v1_reg_0; wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; @@ -2301,7 +2338,7 @@ module Arty_Z7_20_s00_data_fifo_0_compare__parameterized2 .CYINIT(1'b1), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), - .S({\gcc0.gc0.count_d1_reg[6] ,\gcc0.gc0.count_d1_reg[5] ,\gcc0.gc0.count_d1_reg[2] ,\gcc0.gc0.count_d1_reg[1] })); + .S(v1_reg_0)); (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) (* box_type = "PRIMITIVE" *) CARRY4 \gmux.gm[4].gms.ms_CARRY4 @@ -2310,44 +2347,35 @@ module Arty_Z7_20_s00_data_fifo_0_compare__parameterized2 .CYINIT(1'b0), .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}), .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), - .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],\gc0.count_d1_reg[8] })); + .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],\gcc0.gc0.count_d1_reg[8] })); LUT6 #( - .INIT(64'h31313131F0000000)) + .INIT(64'h33F0330011001100)) ram_full_fb_i_i_1__0 (.I0(comp0), .I1(\grstd1.grst_full.grst_f.rst_d3_reg ), - .I2(ram_empty_fb_i_reg), - .I3(comp1), - .I4(m_axi_rvalid), - .I5(out), + .I2(m_axi_rvalid), + .I3(out), + .I4(comp1), + .I5(ram_empty_fb_i_reg), .O(ram_full_comb)); endmodule (* ORIG_REF_NAME = "compare" *) module Arty_Z7_20_s00_data_fifo_0_compare__parameterized3 (comp1, - \gcc0.gc0.count_reg[1] , - \gcc0.gc0.count_reg[3] , - \gcc0.gc0.count_reg[5] , - \gcc0.gc0.count_reg[7] , - \gc0.count_d1_reg[8] ); + v1_reg_1, + \gcc0.gc0.count_reg[8] ); output comp1; - input \gcc0.gc0.count_reg[1] ; - input \gcc0.gc0.count_reg[3] ; - input \gcc0.gc0.count_reg[5] ; - input \gcc0.gc0.count_reg[7] ; - input \gc0.count_d1_reg[8] ; + input [3:0]v1_reg_1; + input \gcc0.gc0.count_reg[8] ; wire carrynet_0; wire carrynet_1; wire carrynet_2; wire carrynet_3; wire comp1; - wire \gc0.count_d1_reg[8] ; - wire \gcc0.gc0.count_reg[1] ; - wire \gcc0.gc0.count_reg[3] ; - wire \gcc0.gc0.count_reg[5] ; - wire \gcc0.gc0.count_reg[7] ; + wire \gcc0.gc0.count_reg[8] ; + wire [3:0]v1_reg_1; wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; @@ -2362,7 +2390,7 @@ module Arty_Z7_20_s00_data_fifo_0_compare__parameterized3 .CYINIT(1'b1), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), - .S({\gcc0.gc0.count_reg[7] ,\gcc0.gc0.count_reg[5] ,\gcc0.gc0.count_reg[3] ,\gcc0.gc0.count_reg[1] })); + .S(v1_reg_1)); (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) (* box_type = "PRIMITIVE" *) CARRY4 \gmux.gm[4].gms.ms_CARRY4 @@ -2371,36 +2399,32 @@ module Arty_Z7_20_s00_data_fifo_0_compare__parameterized3 .CYINIT(1'b0), .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}), .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), - .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],\gc0.count_d1_reg[8] })); + .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],\gcc0.gc0.count_reg[8] })); endmodule module Arty_Z7_20_s00_data_fifo_0_dmem (dout_i, s_aclk, - ram_full_fb_i_reg, + EN, UNCONN_IN, \gc0.count_d1_reg[4] , \gcc0.gc0.count_d1_reg[4] , - \gpregsm1.curr_fwft_state_reg[0] ); - output [55:0]dout_i; + ram_empty_fb_i_reg); + output [62:0]dout_i; input s_aclk; - input [0:0]ram_full_fb_i_reg; - input [55:0]UNCONN_IN; + input EN; + input [62:0]UNCONN_IN; input [4:0]\gc0.count_d1_reg[4] ; input [4:0]\gcc0.gc0.count_d1_reg[4] ; - input [0:0]\gpregsm1.curr_fwft_state_reg[0] ; + input [0:0]ram_empty_fb_i_reg; - wire RAM_reg_0_31_0_5_n_0; - wire RAM_reg_0_31_0_5_n_1; - wire RAM_reg_0_31_0_5_n_2; - wire RAM_reg_0_31_0_5_n_3; - wire [55:0]UNCONN_IN; - wire [55:0]dout_i; + wire EN; + wire [62:0]UNCONN_IN; + wire [62:0]dout_i; wire [4:0]\gc0.count_d1_reg[4] ; wire [4:0]\gcc0.gc0.count_d1_reg[4] ; - wire [0:0]\gpregsm1.curr_fwft_state_reg[0] ; - wire [59:4]p_0_out; - wire [0:0]ram_full_fb_i_reg; + wire [62:0]p_0_out; + wire [0:0]ram_empty_fb_i_reg; wire s_aclk; wire [1:0]NLW_RAM_reg_0_31_0_5_DOD_UNCONNECTED; wire [1:0]NLW_RAM_reg_0_31_12_17_DOD_UNCONNECTED; @@ -2411,6 +2435,9 @@ module Arty_Z7_20_s00_data_fifo_0_dmem wire [1:0]NLW_RAM_reg_0_31_42_47_DOD_UNCONNECTED; wire [1:0]NLW_RAM_reg_0_31_48_53_DOD_UNCONNECTED; wire [1:0]NLW_RAM_reg_0_31_54_59_DOD_UNCONNECTED; + wire [1:1]NLW_RAM_reg_0_31_60_62_DOB_UNCONNECTED; + wire [1:0]NLW_RAM_reg_0_31_60_62_DOC_UNCONNECTED; + wire [1:0]NLW_RAM_reg_0_31_60_62_DOD_UNCONNECTED; wire [1:0]NLW_RAM_reg_0_31_6_11_DOD_UNCONNECTED; (* METHODOLOGY_DRC_VIOS = "" *) @@ -2419,697 +2446,766 @@ module Arty_Z7_20_s00_data_fifo_0_dmem .ADDRB(\gc0.count_d1_reg[4] ), .ADDRC(\gc0.count_d1_reg[4] ), .ADDRD(\gcc0.gc0.count_d1_reg[4] ), - .DIA({1'b0,1'b0}), - .DIB({1'b0,1'b0}), - .DIC(UNCONN_IN[1:0]), + .DIA(UNCONN_IN[1:0]), + .DIB(UNCONN_IN[3:2]), + .DIC(UNCONN_IN[5:4]), .DID({1'b0,1'b0}), - .DOA({RAM_reg_0_31_0_5_n_0,RAM_reg_0_31_0_5_n_1}), - .DOB({RAM_reg_0_31_0_5_n_2,RAM_reg_0_31_0_5_n_3}), + .DOA(p_0_out[1:0]), + .DOB(p_0_out[3:2]), .DOC(p_0_out[5:4]), .DOD(NLW_RAM_reg_0_31_0_5_DOD_UNCONNECTED[1:0]), .WCLK(s_aclk), - .WE(ram_full_fb_i_reg)); + .WE(EN)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M RAM_reg_0_31_12_17 (.ADDRA(\gc0.count_d1_reg[4] ), .ADDRB(\gc0.count_d1_reg[4] ), .ADDRC(\gc0.count_d1_reg[4] ), .ADDRD(\gcc0.gc0.count_d1_reg[4] ), - .DIA(UNCONN_IN[9:8]), - .DIB(UNCONN_IN[11:10]), - .DIC(UNCONN_IN[13:12]), + .DIA(UNCONN_IN[13:12]), + .DIB(UNCONN_IN[15:14]), + .DIC(UNCONN_IN[17:16]), .DID({1'b0,1'b0}), .DOA(p_0_out[13:12]), .DOB(p_0_out[15:14]), .DOC(p_0_out[17:16]), .DOD(NLW_RAM_reg_0_31_12_17_DOD_UNCONNECTED[1:0]), .WCLK(s_aclk), - .WE(ram_full_fb_i_reg)); + .WE(EN)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M RAM_reg_0_31_18_23 (.ADDRA(\gc0.count_d1_reg[4] ), .ADDRB(\gc0.count_d1_reg[4] ), .ADDRC(\gc0.count_d1_reg[4] ), .ADDRD(\gcc0.gc0.count_d1_reg[4] ), - .DIA(UNCONN_IN[15:14]), - .DIB(UNCONN_IN[17:16]), - .DIC(UNCONN_IN[19:18]), + .DIA(UNCONN_IN[19:18]), + .DIB(UNCONN_IN[21:20]), + .DIC(UNCONN_IN[23:22]), .DID({1'b0,1'b0}), .DOA(p_0_out[19:18]), .DOB(p_0_out[21:20]), .DOC(p_0_out[23:22]), .DOD(NLW_RAM_reg_0_31_18_23_DOD_UNCONNECTED[1:0]), .WCLK(s_aclk), - .WE(ram_full_fb_i_reg)); + .WE(EN)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M RAM_reg_0_31_24_29 (.ADDRA(\gc0.count_d1_reg[4] ), .ADDRB(\gc0.count_d1_reg[4] ), .ADDRC(\gc0.count_d1_reg[4] ), .ADDRD(\gcc0.gc0.count_d1_reg[4] ), - .DIA(UNCONN_IN[21:20]), - .DIB(UNCONN_IN[23:22]), - .DIC(UNCONN_IN[25:24]), + .DIA(UNCONN_IN[25:24]), + .DIB(UNCONN_IN[27:26]), + .DIC(UNCONN_IN[29:28]), .DID({1'b0,1'b0}), .DOA(p_0_out[25:24]), .DOB(p_0_out[27:26]), .DOC(p_0_out[29:28]), .DOD(NLW_RAM_reg_0_31_24_29_DOD_UNCONNECTED[1:0]), .WCLK(s_aclk), - .WE(ram_full_fb_i_reg)); + .WE(EN)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M RAM_reg_0_31_30_35 (.ADDRA(\gc0.count_d1_reg[4] ), .ADDRB(\gc0.count_d1_reg[4] ), .ADDRC(\gc0.count_d1_reg[4] ), .ADDRD(\gcc0.gc0.count_d1_reg[4] ), - .DIA(UNCONN_IN[27:26]), - .DIB(UNCONN_IN[29:28]), - .DIC(UNCONN_IN[31:30]), + .DIA(UNCONN_IN[31:30]), + .DIB(UNCONN_IN[33:32]), + .DIC(UNCONN_IN[35:34]), .DID({1'b0,1'b0}), .DOA(p_0_out[31:30]), .DOB(p_0_out[33:32]), .DOC(p_0_out[35:34]), .DOD(NLW_RAM_reg_0_31_30_35_DOD_UNCONNECTED[1:0]), .WCLK(s_aclk), - .WE(ram_full_fb_i_reg)); + .WE(EN)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M RAM_reg_0_31_36_41 (.ADDRA(\gc0.count_d1_reg[4] ), .ADDRB(\gc0.count_d1_reg[4] ), .ADDRC(\gc0.count_d1_reg[4] ), .ADDRD(\gcc0.gc0.count_d1_reg[4] ), - .DIA(UNCONN_IN[33:32]), - .DIB(UNCONN_IN[35:34]), - .DIC(UNCONN_IN[37:36]), + .DIA(UNCONN_IN[37:36]), + .DIB(UNCONN_IN[39:38]), + .DIC(UNCONN_IN[41:40]), .DID({1'b0,1'b0}), .DOA(p_0_out[37:36]), .DOB(p_0_out[39:38]), .DOC(p_0_out[41:40]), .DOD(NLW_RAM_reg_0_31_36_41_DOD_UNCONNECTED[1:0]), .WCLK(s_aclk), - .WE(ram_full_fb_i_reg)); + .WE(EN)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M RAM_reg_0_31_42_47 (.ADDRA(\gc0.count_d1_reg[4] ), .ADDRB(\gc0.count_d1_reg[4] ), .ADDRC(\gc0.count_d1_reg[4] ), .ADDRD(\gcc0.gc0.count_d1_reg[4] ), - .DIA(UNCONN_IN[39:38]), - .DIB(UNCONN_IN[41:40]), - .DIC(UNCONN_IN[43:42]), + .DIA(UNCONN_IN[43:42]), + .DIB(UNCONN_IN[45:44]), + .DIC(UNCONN_IN[47:46]), .DID({1'b0,1'b0}), .DOA(p_0_out[43:42]), .DOB(p_0_out[45:44]), .DOC(p_0_out[47:46]), .DOD(NLW_RAM_reg_0_31_42_47_DOD_UNCONNECTED[1:0]), .WCLK(s_aclk), - .WE(ram_full_fb_i_reg)); + .WE(EN)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M RAM_reg_0_31_48_53 (.ADDRA(\gc0.count_d1_reg[4] ), .ADDRB(\gc0.count_d1_reg[4] ), .ADDRC(\gc0.count_d1_reg[4] ), .ADDRD(\gcc0.gc0.count_d1_reg[4] ), - .DIA(UNCONN_IN[45:44]), - .DIB(UNCONN_IN[47:46]), - .DIC(UNCONN_IN[49:48]), + .DIA(UNCONN_IN[49:48]), + .DIB(UNCONN_IN[51:50]), + .DIC(UNCONN_IN[53:52]), .DID({1'b0,1'b0}), .DOA(p_0_out[49:48]), .DOB(p_0_out[51:50]), .DOC(p_0_out[53:52]), .DOD(NLW_RAM_reg_0_31_48_53_DOD_UNCONNECTED[1:0]), .WCLK(s_aclk), - .WE(ram_full_fb_i_reg)); + .WE(EN)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M RAM_reg_0_31_54_59 (.ADDRA(\gc0.count_d1_reg[4] ), .ADDRB(\gc0.count_d1_reg[4] ), .ADDRC(\gc0.count_d1_reg[4] ), .ADDRD(\gcc0.gc0.count_d1_reg[4] ), - .DIA(UNCONN_IN[51:50]), - .DIB(UNCONN_IN[53:52]), - .DIC(UNCONN_IN[55:54]), + .DIA(UNCONN_IN[55:54]), + .DIB(UNCONN_IN[57:56]), + .DIC(UNCONN_IN[59:58]), .DID({1'b0,1'b0}), .DOA(p_0_out[55:54]), .DOB(p_0_out[57:56]), .DOC(p_0_out[59:58]), .DOD(NLW_RAM_reg_0_31_54_59_DOD_UNCONNECTED[1:0]), .WCLK(s_aclk), - .WE(ram_full_fb_i_reg)); + .WE(EN)); + (* METHODOLOGY_DRC_VIOS = "" *) + RAM32M RAM_reg_0_31_60_62 + (.ADDRA(\gc0.count_d1_reg[4] ), + .ADDRB(\gc0.count_d1_reg[4] ), + .ADDRC(\gc0.count_d1_reg[4] ), + .ADDRD(\gcc0.gc0.count_d1_reg[4] ), + .DIA(UNCONN_IN[61:60]), + .DIB({1'b0,UNCONN_IN[62]}), + .DIC({1'b0,1'b0}), + .DID({1'b0,1'b0}), + .DOA(p_0_out[61:60]), + .DOB({NLW_RAM_reg_0_31_60_62_DOB_UNCONNECTED[1],p_0_out[62]}), + .DOC(NLW_RAM_reg_0_31_60_62_DOC_UNCONNECTED[1:0]), + .DOD(NLW_RAM_reg_0_31_60_62_DOD_UNCONNECTED[1:0]), + .WCLK(s_aclk), + .WE(EN)); (* METHODOLOGY_DRC_VIOS = "" *) RAM32M RAM_reg_0_31_6_11 (.ADDRA(\gc0.count_d1_reg[4] ), .ADDRB(\gc0.count_d1_reg[4] ), .ADDRC(\gc0.count_d1_reg[4] ), .ADDRD(\gcc0.gc0.count_d1_reg[4] ), - .DIA(UNCONN_IN[3:2]), - .DIB(UNCONN_IN[5:4]), - .DIC(UNCONN_IN[7:6]), + .DIA(UNCONN_IN[7:6]), + .DIB(UNCONN_IN[9:8]), + .DIC(UNCONN_IN[11:10]), .DID({1'b0,1'b0}), .DOA(p_0_out[7:6]), .DOB(p_0_out[9:8]), .DOC(p_0_out[11:10]), .DOD(NLW_RAM_reg_0_31_6_11_DOD_UNCONNECTED[1:0]), .WCLK(s_aclk), - .WE(ram_full_fb_i_reg)); + .WE(EN)); + FDRE #( + .INIT(1'b0)) + \gpr1.dout_i_reg[0] + (.C(s_aclk), + .CE(ram_empty_fb_i_reg), + .D(p_0_out[0]), + .Q(dout_i[0]), + .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[10] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[10]), - .Q(dout_i[6]), + .Q(dout_i[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[11] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[11]), - .Q(dout_i[7]), + .Q(dout_i[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[12] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[12]), - .Q(dout_i[8]), + .Q(dout_i[12]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[13] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[13]), - .Q(dout_i[9]), + .Q(dout_i[13]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[14] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[14]), - .Q(dout_i[10]), + .Q(dout_i[14]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[15] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[15]), - .Q(dout_i[11]), + .Q(dout_i[15]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[16] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[16]), - .Q(dout_i[12]), + .Q(dout_i[16]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[17] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[17]), - .Q(dout_i[13]), + .Q(dout_i[17]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[18] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[18]), - .Q(dout_i[14]), + .Q(dout_i[18]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[19] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[19]), - .Q(dout_i[15]), + .Q(dout_i[19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gpr1.dout_i_reg[1] + (.C(s_aclk), + .CE(ram_empty_fb_i_reg), + .D(p_0_out[1]), + .Q(dout_i[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[20] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[20]), - .Q(dout_i[16]), + .Q(dout_i[20]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[21] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[21]), - .Q(dout_i[17]), + .Q(dout_i[21]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[22] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[22]), - .Q(dout_i[18]), + .Q(dout_i[22]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[23] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[23]), - .Q(dout_i[19]), + .Q(dout_i[23]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[24] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[24]), - .Q(dout_i[20]), + .Q(dout_i[24]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[25] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[25]), - .Q(dout_i[21]), + .Q(dout_i[25]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[26] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[26]), - .Q(dout_i[22]), + .Q(dout_i[26]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[27] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[27]), - .Q(dout_i[23]), + .Q(dout_i[27]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[28] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[28]), - .Q(dout_i[24]), + .Q(dout_i[28]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[29] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[29]), - .Q(dout_i[25]), + .Q(dout_i[29]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gpr1.dout_i_reg[2] + (.C(s_aclk), + .CE(ram_empty_fb_i_reg), + .D(p_0_out[2]), + .Q(dout_i[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[30] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[30]), - .Q(dout_i[26]), + .Q(dout_i[30]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[31] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[31]), - .Q(dout_i[27]), + .Q(dout_i[31]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[32] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[32]), - .Q(dout_i[28]), + .Q(dout_i[32]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[33] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[33]), - .Q(dout_i[29]), + .Q(dout_i[33]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[34] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[34]), - .Q(dout_i[30]), + .Q(dout_i[34]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[35] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[35]), - .Q(dout_i[31]), + .Q(dout_i[35]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[36] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[36]), - .Q(dout_i[32]), + .Q(dout_i[36]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[37] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[37]), - .Q(dout_i[33]), + .Q(dout_i[37]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[38] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[38]), - .Q(dout_i[34]), + .Q(dout_i[38]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[39] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[39]), - .Q(dout_i[35]), + .Q(dout_i[39]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gpr1.dout_i_reg[3] + (.C(s_aclk), + .CE(ram_empty_fb_i_reg), + .D(p_0_out[3]), + .Q(dout_i[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[40] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[40]), - .Q(dout_i[36]), + .Q(dout_i[40]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[41] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[41]), - .Q(dout_i[37]), + .Q(dout_i[41]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[42] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[42]), - .Q(dout_i[38]), + .Q(dout_i[42]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[43] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[43]), - .Q(dout_i[39]), + .Q(dout_i[43]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[44] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[44]), - .Q(dout_i[40]), + .Q(dout_i[44]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[45] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[45]), - .Q(dout_i[41]), + .Q(dout_i[45]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[46] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[46]), - .Q(dout_i[42]), + .Q(dout_i[46]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[47] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[47]), - .Q(dout_i[43]), + .Q(dout_i[47]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[48] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[48]), - .Q(dout_i[44]), + .Q(dout_i[48]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[49] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[49]), - .Q(dout_i[45]), + .Q(dout_i[49]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[4] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[4]), - .Q(dout_i[0]), + .Q(dout_i[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[50] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[50]), - .Q(dout_i[46]), + .Q(dout_i[50]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[51] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[51]), - .Q(dout_i[47]), + .Q(dout_i[51]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[52] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[52]), - .Q(dout_i[48]), + .Q(dout_i[52]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[53] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[53]), - .Q(dout_i[49]), + .Q(dout_i[53]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[54] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[54]), - .Q(dout_i[50]), + .Q(dout_i[54]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[55] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[55]), - .Q(dout_i[51]), + .Q(dout_i[55]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[56] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[56]), - .Q(dout_i[52]), + .Q(dout_i[56]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[57] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[57]), - .Q(dout_i[53]), + .Q(dout_i[57]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[58] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[58]), - .Q(dout_i[54]), + .Q(dout_i[58]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[59] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[59]), - .Q(dout_i[55]), + .Q(dout_i[59]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[5] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[5]), - .Q(dout_i[1]), + .Q(dout_i[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gpr1.dout_i_reg[60] + (.C(s_aclk), + .CE(ram_empty_fb_i_reg), + .D(p_0_out[60]), + .Q(dout_i[60]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gpr1.dout_i_reg[61] + (.C(s_aclk), + .CE(ram_empty_fb_i_reg), + .D(p_0_out[61]), + .Q(dout_i[61]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \gpr1.dout_i_reg[62] + (.C(s_aclk), + .CE(ram_empty_fb_i_reg), + .D(p_0_out[62]), + .Q(dout_i[62]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[6] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[6]), - .Q(dout_i[2]), + .Q(dout_i[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[7] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[7]), - .Q(dout_i[3]), + .Q(dout_i[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[8] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[8]), - .Q(dout_i[4]), + .Q(dout_i[8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \gpr1.dout_i_reg[9] (.C(s_aclk), - .CE(\gpregsm1.curr_fwft_state_reg[0] ), + .CE(ram_empty_fb_i_reg), .D(p_0_out[9]), - .Q(dout_i[5]), + .Q(dout_i[9]), .R(1'b0)); endmodule module Arty_Z7_20_s00_data_fifo_0_fifo_generator_ramfifo (out, - S, Q, - \gfwd_rev_pipeline1.s_ready_i_reg , - \gfwd_rev_pipeline1.s_ready_i_reg_0 , D, E, aempty_fwft_i_reg, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3] , + s_axi_arready, + S, DI, + \gfwd_rev_pipeline1.s_ready_i_reg , + \gfwd_rev_pipeline1.s_ready_i_reg_0 , + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0 , \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] , - s_axi_arready, - \gfwd_rev_pipeline1.s_ready_i_reg_1 , - \gfwd_rev_pipeline1.s_ready_i_reg_2 , - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_0 , + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] , s_aclk, inverted_reset, CO, arready_pkt, - s_axi_rready, - empty_fwft_fb_o_i_reg, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] , - rd_fifo_free_space, s_axi_arvalid, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_1 , \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0 , + rd_fifo_free_space, + empty_fwft_fb_o_i_reg, + s_axi_rready, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_1 , UNCONN_IN); output out; - output [3:0]S; - output [55:0]Q; - output [3:0]\gfwd_rev_pipeline1.s_ready_i_reg ; - output [0:0]\gfwd_rev_pipeline1.s_ready_i_reg_0 ; + output [62:0]Q; output [9:0]D; output [0:0]E; output aempty_fwft_i_reg; - output [0:0]DI; - output \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] ; + output \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3] ; output s_axi_arready; - output [3:0]\gfwd_rev_pipeline1.s_ready_i_reg_1 ; - output [0:0]\gfwd_rev_pipeline1.s_ready_i_reg_2 ; - output [0:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_0 ; + output [3:0]S; + output [3:0]DI; + output [0:0]\gfwd_rev_pipeline1.s_ready_i_reg ; + output [0:0]\gfwd_rev_pipeline1.s_ready_i_reg_0 ; + output [3:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0 ; + output [3:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] ; + output [0:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ; input s_aclk; input inverted_reset; input [0:0]CO; input arready_pkt; - input s_axi_rready; - input empty_fwft_fb_o_i_reg; - input [9:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ; - input [9:0]rd_fifo_free_space; input s_axi_arvalid; - input [3:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_1 ; - input [1:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0 ; - input [55:0]UNCONN_IN; + input [9:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0 ; + input [9:0]rd_fifo_free_space; + input empty_fwft_fb_o_i_reg; + input s_axi_rready; + input [1:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_1 ; + input [62:0]UNCONN_IN; wire [0:0]CO; wire [9:0]D; - wire [0:0]DI; + wire [3:0]DI; wire [0:0]E; - wire [55:0]Q; + wire [62:0]Q; wire [3:0]S; - wire [55:0]UNCONN_IN; + wire [62:0]UNCONN_IN; wire aempty_fwft_i_reg; wire arready_pkt; wire empty_fwft_fb_o_i_reg; - wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] ; - wire [0:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_0 ; - wire [3:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_1 ; - wire [9:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ; - wire [1:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0 ; - wire [3:0]\gfwd_rev_pipeline1.s_ready_i_reg ; + wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3] ; + wire [3:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0 ; + wire [3:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] ; + wire [0:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ; + wire [9:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0 ; + wire [1:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_1 ; + wire [0:0]\gfwd_rev_pipeline1.s_ready_i_reg ; wire [0:0]\gfwd_rev_pipeline1.s_ready_i_reg_0 ; - wire [3:0]\gfwd_rev_pipeline1.s_ready_i_reg_1 ; - wire [0:0]\gfwd_rev_pipeline1.s_ready_i_reg_2 ; - wire \gntv_or_sync_fifo.gl0.rd_n_19 ; - wire \gntv_or_sync_fifo.gl0.rd_n_4 ; - wire \gntv_or_sync_fifo.gl0.rd_n_6 ; - wire \gntv_or_sync_fifo.gl0.rd_n_8 ; - wire \gntv_or_sync_fifo.gl0.rd_n_9 ; - wire \gntv_or_sync_fifo.gl0.wr_n_4 ; + wire \gntv_or_sync_fifo.gl0.rd_n_1 ; + wire \gntv_or_sync_fifo.gl0.rd_n_2 ; + wire \gntv_or_sync_fifo.gl0.rd_n_5 ; + wire \gntv_or_sync_fifo.gl0.wr_n_0 ; + wire \gntv_or_sync_fifo.gl0.wr_n_1 ; + wire \gntv_or_sync_fifo.gl0.wr_n_8 ; + wire \gwss.wsts/ram_full_comb ; wire inverted_reset; wire out; wire [4:0]p_0_out_0; wire [4:0]p_11_out; - wire [4:2]p_12_out; - wire p_17_out; - wire ram_rd_en_i; + wire [4:0]p_12_out; wire [9:0]rd_fifo_free_space; + wire [4:0]rd_pntr_plus1; wire [2:0]rd_rst_i; wire rst_full_ff_i; wire s_aclk; @@ -3121,42 +3217,42 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_ramfifo Arty_Z7_20_s00_data_fifo_0_rd_logic \gntv_or_sync_fifo.gl0.rd (.CO(CO), - .E(E), - .Q(p_0_out_0), + .E(\gntv_or_sync_fifo.gl0.rd_n_1 ), + .Q(rd_pntr_plus1), .arready_pkt(arready_pkt), .empty_fwft_fb_o_i_reg(empty_fwft_fb_o_i_reg), - .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0] (\gntv_or_sync_fifo.gl0.rd_n_4 ), - .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] (\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] ), - .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] (\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] [9:4]), - .\gc0.count_reg[4] (ram_rd_en_i), + .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0] (\gntv_or_sync_fifo.gl0.rd_n_2 ), + .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0]_0 (E), + .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3] (\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3] ), + .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0 (\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0 [0]), + .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] (\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0 [9:8]), + .\gc0.count_reg[2] (\gntv_or_sync_fifo.gl0.wr_n_8 ), .\gcc0.gc0.count_d1_reg[4] (p_11_out), .\gcc0.gc0.count_reg[4] (p_12_out), - .\gfwd_rev_pipeline1.s_ready_i_reg (\gfwd_rev_pipeline1.s_ready_i_reg [3:2]), + .\gfwd_rev_pipeline1.s_ready_i_reg (\gfwd_rev_pipeline1.s_ready_i_reg ), .\gfwd_rev_pipeline1.s_ready_i_reg_0 (\gfwd_rev_pipeline1.s_ready_i_reg_0 ), - .\gfwd_rev_pipeline1.s_ready_i_reg_1 (\gfwd_rev_pipeline1.s_ready_i_reg_1 [3:2]), - .\gfwd_rev_pipeline1.s_ready_i_reg_2 (\gfwd_rev_pipeline1.s_ready_i_reg_2 ), - .\gfwd_rev_pipeline1.s_ready_i_reg_3 (aempty_fwft_i_reg), - .\goreg_dm.dout_i_reg[59] (\gntv_or_sync_fifo.gl0.rd_n_9 ), + .\gfwd_rev_pipeline1.s_ready_i_reg_1 (aempty_fwft_i_reg), + .\goreg_dm.dout_i_reg[22] (Q[22]), + .\goreg_dm.dout_i_reg[62] (\gntv_or_sync_fifo.gl0.rd_n_5 ), + .\gpr1.dout_i_reg[1] (p_0_out_0), + .\grstd1.grst_full.grst_f.rst_d3_reg (wr_rst_busy_rach), .\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ({rd_rst_i[2],rd_rst_i[0]}), .out(out), - .ram_empty_fb_i_reg(\gntv_or_sync_fifo.gl0.rd_n_6 ), - .ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.rd_n_8 ), - .ram_full_fb_i_reg_0(\gntv_or_sync_fifo.gl0.rd_n_19 ), - .ram_full_i_reg(\gntv_or_sync_fifo.gl0.wr_n_4 ), + .ram_full_comb(\gwss.wsts/ram_full_comb ), + .ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_0 ), + .ram_full_i_reg(\gntv_or_sync_fifo.gl0.wr_n_1 ), .s_aclk(s_aclk), .s_axi_rready(s_axi_rready)); Arty_Z7_20_s00_data_fifo_0_wr_logic \gntv_or_sync_fifo.gl0.wr (.AR(wr_rst_i), - .E(p_17_out), + .E(\gntv_or_sync_fifo.gl0.wr_n_1 ), .Q(p_12_out), - .\gc0.count_d1_reg[1] (p_0_out_0[1:0]), - .\gc0.count_d1_reg[2] (\gntv_or_sync_fifo.gl0.rd_n_6 ), - .\gc0.count_d1_reg[2]_0 (\gntv_or_sync_fifo.gl0.rd_n_19 ), - .\gpr1.dout_i_reg[5] (p_11_out), - .\grstd1.grst_full.grst_f.rst_d3_reg (wr_rst_busy_rach), - .out(rst_full_ff_i), - .ram_empty_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_4 ), - .ram_empty_fb_i_reg_0(\gntv_or_sync_fifo.gl0.rd_n_8 ), + .\gc0.count_reg[4] (rd_pntr_plus1), + .\gpr1.dout_i_reg[1] (p_11_out), + .\grstd1.grst_full.grst_f.rst_d2_reg (rst_full_ff_i), + .out(\gntv_or_sync_fifo.gl0.wr_n_0 ), + .ram_empty_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_8 ), + .ram_full_comb(\gwss.wsts/ram_full_comb ), .s_aclk(s_aclk), .s_axi_arready(s_axi_arready), .s_axi_arvalid(s_axi_arvalid)); @@ -3164,35 +3260,32 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_ramfifo (.CO(CO), .D(D), .DI(DI), - .E(\gntv_or_sync_fifo.gl0.rd_n_9 ), + .E(\gntv_or_sync_fifo.gl0.rd_n_5 ), + .EN(\gntv_or_sync_fifo.gl0.wr_n_1 ), .Q(Q), .S(S), .UNCONN_IN(UNCONN_IN), .aempty_fwft_i_reg(aempty_fwft_i_reg), .arready_pkt(arready_pkt), - .empty_fwft_fb_o_i_reg(empty_fwft_fb_o_i_reg), - .empty_fwft_i_reg(\gntv_or_sync_fifo.gl0.rd_n_4 ), - .empty_fwft_i_reg_0(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] ), - .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] (\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_0 ), - .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_0 (\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_1 ), - .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] (\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] [8:0]), - .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] (\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0 ), + .empty_fwft_i_reg(\gntv_or_sync_fifo.gl0.rd_n_2 ), + .empty_fwft_i_reg_0(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3] ), + .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3] (\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0 [3:1]), + .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] (\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] ), + .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] (\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0 [8:0]), + .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] (\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ), + .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0 (\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_1 ), .\gc0.count_d1_reg[4] (p_0_out_0), .\gcc0.gc0.count_d1_reg[4] (p_11_out), - .\gfwd_rev_pipeline1.s_ready_i_reg (\gfwd_rev_pipeline1.s_ready_i_reg_1 [1:0]), - .\gfwd_rev_pipeline1.s_ready_i_reg_0 (\gfwd_rev_pipeline1.s_ready_i_reg [1:0]), - .\gpregsm1.curr_fwft_state_reg[0] (ram_rd_en_i), .out(out), - .ram_full_fb_i_reg(p_17_out), + .ram_empty_fb_i_reg(\gntv_or_sync_fifo.gl0.rd_n_1 ), .rd_fifo_free_space(rd_fifo_free_space), - .s_aclk(s_aclk), - .s_axi_rready(s_axi_rready)); + .s_aclk(s_aclk)); Arty_Z7_20_s00_data_fifo_0_reset_blk_ramfifo__parameterized0 rstblk (.\gc0.count_reg[1] ({rd_rst_i[2],rd_rst_i[0]}), .\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i), .inverted_reset(inverted_reset), .out(wr_rst_i), - .ram_full_fb_i_reg(wr_rst_busy_rach), + .ram_full_i_reg(wr_rst_busy_rach), .s_aclk(s_aclk)); endmodule @@ -3208,12 +3301,12 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_ramfifo__parameterized0 DIADI, m_axi_rid, inverted_reset, - Q, s_axi_rready, - arready_pkt, + m_axi_rvalid, CO, + arready_pkt, empty_fwft_i_reg, - m_axi_rvalid); + Q); output out; output [0:0]S; output s_axi_rvalid; @@ -3224,12 +3317,12 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_ramfifo__parameterized0 input [3:0]DIADI; input [0:0]m_axi_rid; input inverted_reset; - input [0:0]Q; input s_axi_rready; - input arready_pkt; + input m_axi_rvalid; input [0:0]CO; + input arready_pkt; input empty_fwft_i_reg; - input m_axi_rvalid; + input [0:0]Q; wire [0:0]CO; wire [3:0]DIADI; @@ -3240,19 +3333,13 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_ramfifo__parameterized0 wire dout_i; wire empty_fwft_i_reg; wire full_fb_rdch; - wire \gntv_or_sync_fifo.gl0.rd_n_21 ; - wire \gntv_or_sync_fifo.gl0.rd_n_23 ; - wire \gntv_or_sync_fifo.gl0.rd_n_3 ; - wire \gntv_or_sync_fifo.gl0.wr_n_10 ; - wire \gntv_or_sync_fifo.gl0.wr_n_11 ; - wire \gntv_or_sync_fifo.gl0.wr_n_12 ; - wire \gntv_or_sync_fifo.gl0.wr_n_13 ; - wire \gntv_or_sync_fifo.gl0.wr_n_15 ; - wire \gntv_or_sync_fifo.gl0.wr_n_16 ; - wire \gntv_or_sync_fifo.gl0.wr_n_17 ; + wire \gntv_or_sync_fifo.gl0.rd_n_11 ; wire \gntv_or_sync_fifo.gl0.wr_n_18 ; wire \gr1.gr1_int.rfwft/fwft_rst_done_q ; wire \gr1.gr1_int.rfwft/p_1_out ; + wire [3:0]\grss.rsts/c2/v1_reg ; + wire [3:0]\gwss.wsts/c0/v1_reg ; + wire [3:0]\gwss.wsts/c1/v1_reg ; wire inverted_reset; wire [63:0]m_axi_rdata; wire [0:0]m_axi_rid; @@ -3261,7 +3348,7 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_ramfifo__parameterized0 wire out; wire [8:0]p_0_out; wire [8:0]p_12_out; - wire [8:8]p_13_out; + wire [7:0]p_13_out; wire p_19_out; wire ram_rd_en_i; wire [7:0]rd_pntr_plus1; @@ -3277,74 +3364,62 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_ramfifo__parameterized0 (.CO(CO), .\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (p_0_out), .E(ram_rd_en_i), - .Q(Q), + .Q(rd_pntr_plus1), .S(S), .SR(\gr1.gr1_int.rfwft/p_1_out ), .arready_pkt(arready_pkt), .empty_fwft_i_reg(empty_fwft_i_reg), .fwft_rst_done_q(\gr1.gr1_int.rfwft/fwft_rst_done_q ), - .\gc0.count_d1_reg[7] (rd_pntr_plus1), - .\gcc0.gc0.count_d1_reg[0] (\gntv_or_sync_fifo.gl0.wr_n_13 ), - .\gcc0.gc0.count_d1_reg[1] (\gntv_or_sync_fifo.gl0.wr_n_15 ), - .\gcc0.gc0.count_d1_reg[2] (\gntv_or_sync_fifo.gl0.wr_n_16 ), - .\gcc0.gc0.count_d1_reg[3] (\gntv_or_sync_fifo.gl0.wr_n_12 ), - .\gcc0.gc0.count_d1_reg[4] (\gntv_or_sync_fifo.gl0.wr_n_11 ), - .\gcc0.gc0.count_d1_reg[5] (\gntv_or_sync_fifo.gl0.wr_n_17 ), - .\gcc0.gc0.count_d1_reg[6] (\gntv_or_sync_fifo.gl0.wr_n_18 ), - .\gcc0.gc0.count_d1_reg[6]_0 (\gntv_or_sync_fifo.gl0.wr_n_10 ), - .\gcc0.gc0.count_d1_reg[8] (p_12_out[8]), - .\gcc0.gc0.count_reg[8] (p_13_out), + .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] (Q), + .\gcc0.gc0.count_d1_reg[8] (\gntv_or_sync_fifo.gl0.wr_n_18 ), + .\gcc0.gc0.count_d1_reg[8]_0 (p_12_out), + .\gcc0.gc0.count_reg[7] (p_13_out), .\goreg_bm.dout_i_reg[68] (dout_i), .m_axi_rvalid(m_axi_rvalid), .\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg (rstblk_n_4), .\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ({rd_rst_i[2],rd_rst_i[0]}), .out(out), .ram_full_fb_i_reg(full_fb_rdch), - .ram_full_i_reg(\gntv_or_sync_fifo.gl0.rd_n_3 ), - .ram_full_i_reg_0(\gntv_or_sync_fifo.gl0.rd_n_21 ), - .ram_full_i_reg_1(\gntv_or_sync_fifo.gl0.rd_n_23 ), + .ram_full_i_reg(\gntv_or_sync_fifo.gl0.rd_n_11 ), .s_aclk(s_aclk), .s_axi_rready(s_axi_rready), - .s_axi_rvalid(s_axi_rvalid)); + .s_axi_rvalid(s_axi_rvalid), + .v1_reg(\gwss.wsts/c0/v1_reg ), + .v1_reg_0(\gwss.wsts/c1/v1_reg ), + .v1_reg_1(\grss.rsts/c2/v1_reg )); Arty_Z7_20_s00_data_fifo_0_wr_logic__parameterized0 \gntv_or_sync_fifo.gl0.wr (.E(p_19_out), .Q(p_12_out), - .\gc0.count_d1_reg[7] (p_0_out[7:0]), - .\gc0.count_d1_reg[8] (\gntv_or_sync_fifo.gl0.rd_n_3 ), - .\gc0.count_d1_reg[8]_0 (\gntv_or_sync_fifo.gl0.rd_n_21 ), + .\gc0.count_d1_reg[8] (p_0_out[8]), .\gc0.count_reg[7] (rd_pntr_plus1), - .\gcc0.gc0.count_d1_reg[8] (p_13_out), + .\gcc0.gc0.count_d1_reg[7] (p_13_out), .\grstd1.grst_full.grst_f.rst_d2_reg (rst_full_ff_i), .\grstd1.grst_full.grst_f.rst_d3_reg (rst_full_gen_i), .m_axi_rready(m_axi_rready), .m_axi_rvalid(m_axi_rvalid), .\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg (rstblk_n_4), .out(full_fb_rdch), - .ram_empty_fb_i_reg(\gntv_or_sync_fifo.gl0.rd_n_23 ), - .ram_empty_i_reg(\gntv_or_sync_fifo.gl0.wr_n_10 ), - .ram_empty_i_reg_0(\gntv_or_sync_fifo.gl0.wr_n_11 ), - .ram_empty_i_reg_1(\gntv_or_sync_fifo.gl0.wr_n_12 ), - .ram_empty_i_reg_2(\gntv_or_sync_fifo.gl0.wr_n_13 ), - .ram_empty_i_reg_3(\gntv_or_sync_fifo.gl0.wr_n_15 ), - .ram_empty_i_reg_4(\gntv_or_sync_fifo.gl0.wr_n_16 ), - .ram_empty_i_reg_5(\gntv_or_sync_fifo.gl0.wr_n_17 ), - .ram_empty_i_reg_6(\gntv_or_sync_fifo.gl0.wr_n_18 ), - .s_aclk(s_aclk)); + .ram_empty_fb_i_reg(\gntv_or_sync_fifo.gl0.rd_n_11 ), + .ram_empty_i_reg(\gntv_or_sync_fifo.gl0.wr_n_18 ), + .s_aclk(s_aclk), + .v1_reg(\grss.rsts/c2/v1_reg ), + .v1_reg_0(\gwss.wsts/c0/v1_reg ), + .v1_reg_1(\gwss.wsts/c1/v1_reg )); Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 \gntv_or_sync_fifo.mem (.DIADI(DIADI), .E(ram_rd_en_i), .Q(p_12_out), .UNCONN_OUT(UNCONN_OUT), .\gc0.count_d1_reg[8] (p_0_out), + .\gpregsm1.curr_fwft_state_reg[0] (dout_i), .m_axi_rdata(m_axi_rdata), .m_axi_rid(m_axi_rid), - .\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] (dout_i), .ram_full_fb_i_reg(p_19_out), .s_aclk(s_aclk)); Arty_Z7_20_s00_data_fifo_0_reset_blk_ramfifo__parameterized2 rstblk (.SR(\gr1.gr1_int.rfwft/p_1_out ), .fwft_rst_done_q(\gr1.gr1_int.rfwft/fwft_rst_done_q ), - .\gcc0.gc0.count_reg[1] (rstblk_n_4), + .\gcc0.gc0.count_d1_reg[0] (rstblk_n_4), .inverted_reset(inverted_reset), .out({rd_rst_i[2],rd_rst_i[0]}), .ram_full_i_reg(rst_full_ff_i), @@ -3354,77 +3429,74 @@ endmodule module Arty_Z7_20_s00_data_fifo_0_fifo_generator_top (out, - S, Q, - \gfwd_rev_pipeline1.s_ready_i_reg , - \gfwd_rev_pipeline1.s_ready_i_reg_0 , D, E, aempty_fwft_i_reg, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3] , + s_axi_arready, + S, DI, + \gfwd_rev_pipeline1.s_ready_i_reg , + \gfwd_rev_pipeline1.s_ready_i_reg_0 , + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0 , \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] , - s_axi_arready, - \gfwd_rev_pipeline1.s_ready_i_reg_1 , - \gfwd_rev_pipeline1.s_ready_i_reg_2 , - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_0 , + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] , s_aclk, inverted_reset, CO, arready_pkt, - s_axi_rready, - empty_fwft_fb_o_i_reg, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] , - rd_fifo_free_space, s_axi_arvalid, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_1 , \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0 , + rd_fifo_free_space, + empty_fwft_fb_o_i_reg, + s_axi_rready, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_1 , UNCONN_IN); output out; - output [3:0]S; - output [55:0]Q; - output [3:0]\gfwd_rev_pipeline1.s_ready_i_reg ; - output [0:0]\gfwd_rev_pipeline1.s_ready_i_reg_0 ; + output [62:0]Q; output [9:0]D; output [0:0]E; output aempty_fwft_i_reg; - output [0:0]DI; - output \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] ; + output \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3] ; output s_axi_arready; - output [3:0]\gfwd_rev_pipeline1.s_ready_i_reg_1 ; - output [0:0]\gfwd_rev_pipeline1.s_ready_i_reg_2 ; - output [0:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_0 ; + output [3:0]S; + output [3:0]DI; + output [0:0]\gfwd_rev_pipeline1.s_ready_i_reg ; + output [0:0]\gfwd_rev_pipeline1.s_ready_i_reg_0 ; + output [3:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0 ; + output [3:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] ; + output [0:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ; input s_aclk; input inverted_reset; input [0:0]CO; input arready_pkt; - input s_axi_rready; - input empty_fwft_fb_o_i_reg; - input [9:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ; - input [9:0]rd_fifo_free_space; input s_axi_arvalid; - input [3:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_1 ; - input [1:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0 ; - input [55:0]UNCONN_IN; + input [9:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0 ; + input [9:0]rd_fifo_free_space; + input empty_fwft_fb_o_i_reg; + input s_axi_rready; + input [1:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_1 ; + input [62:0]UNCONN_IN; wire [0:0]CO; wire [9:0]D; - wire [0:0]DI; + wire [3:0]DI; wire [0:0]E; - wire [55:0]Q; + wire [62:0]Q; wire [3:0]S; - wire [55:0]UNCONN_IN; + wire [62:0]UNCONN_IN; wire aempty_fwft_i_reg; wire arready_pkt; wire empty_fwft_fb_o_i_reg; - wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] ; - wire [0:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_0 ; - wire [3:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_1 ; - wire [9:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ; - wire [1:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0 ; - wire [3:0]\gfwd_rev_pipeline1.s_ready_i_reg ; + wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3] ; + wire [3:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0 ; + wire [3:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] ; + wire [0:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ; + wire [9:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0 ; + wire [1:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_1 ; + wire [0:0]\gfwd_rev_pipeline1.s_ready_i_reg ; wire [0:0]\gfwd_rev_pipeline1.s_ready_i_reg_0 ; - wire [3:0]\gfwd_rev_pipeline1.s_ready_i_reg_1 ; - wire [0:0]\gfwd_rev_pipeline1.s_ready_i_reg_2 ; wire inverted_reset; wire out; wire [9:0]rd_fifo_free_space; @@ -3444,15 +3516,14 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_top .aempty_fwft_i_reg(aempty_fwft_i_reg), .arready_pkt(arready_pkt), .empty_fwft_fb_o_i_reg(empty_fwft_fb_o_i_reg), + .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3] (\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3] ), + .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0 (\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0 ), .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] (\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] ), - .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_0 (\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_0 ), - .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_1 (\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_1 ), .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] (\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ), .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0 (\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0 ), + .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_1 (\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_1 ), .\gfwd_rev_pipeline1.s_ready_i_reg (\gfwd_rev_pipeline1.s_ready_i_reg ), .\gfwd_rev_pipeline1.s_ready_i_reg_0 (\gfwd_rev_pipeline1.s_ready_i_reg_0 ), - .\gfwd_rev_pipeline1.s_ready_i_reg_1 (\gfwd_rev_pipeline1.s_ready_i_reg_1 ), - .\gfwd_rev_pipeline1.s_ready_i_reg_2 (\gfwd_rev_pipeline1.s_ready_i_reg_2 ), .inverted_reset(inverted_reset), .out(out), .rd_fifo_free_space(rd_fifo_free_space), @@ -3474,12 +3545,12 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_top__parameterized0 DIADI, m_axi_rid, inverted_reset, - Q, s_axi_rready, - arready_pkt, + m_axi_rvalid, CO, + arready_pkt, empty_fwft_i_reg, - m_axi_rvalid); + Q); output out; output [0:0]S; output s_axi_rvalid; @@ -3490,12 +3561,12 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_top__parameterized0 input [3:0]DIADI; input [0:0]m_axi_rid; input inverted_reset; - input [0:0]Q; input s_axi_rready; - input arready_pkt; + input m_axi_rvalid; input [0:0]CO; + input arready_pkt; input empty_fwft_i_reg; - input m_axi_rvalid; + input [0:0]Q; wire [0:0]CO; wire [3:0]DIADI; @@ -3539,12 +3610,12 @@ endmodule (* C_AXIS_TID_WIDTH = "8" *) (* C_AXIS_TKEEP_WIDTH = "4" *) (* C_AXIS_TSTRB_WIDTH = "4" *) (* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *) -(* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "4" *) -(* C_AXI_LOCK_WIDTH = "2" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "3" *) +(* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *) +(* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "1" *) (* C_COUNT_TYPE = "0" *) (* C_DATA_COUNT_WIDTH = "10" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "18" *) -(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "60" *) (* C_DIN_WIDTH_RDCH = "69" *) -(* C_DIN_WIDTH_WACH = "60" *) (* C_DIN_WIDTH_WDCH = "75" *) (* C_DIN_WIDTH_WRCH = "75" *) +(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "63" *) (* C_DIN_WIDTH_RDCH = "69" *) +(* C_DIN_WIDTH_WACH = "63" *) (* C_DIN_WIDTH_WDCH = "74" *) (* C_DIN_WIDTH_WRCH = "74" *) (* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "18" *) (* C_ENABLE_RLOCS = "0" *) (* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *) (* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) @@ -3880,10 +3951,10 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 input s_aclk_en; input [0:0]s_axi_awid; input [31:0]s_axi_awaddr; - input [3:0]s_axi_awlen; + input [7:0]s_axi_awlen; input [2:0]s_axi_awsize; input [1:0]s_axi_awburst; - input [1:0]s_axi_awlock; + input [0:0]s_axi_awlock; input [3:0]s_axi_awcache; input [2:0]s_axi_awprot; input [3:0]s_axi_awqos; @@ -3905,10 +3976,10 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 input s_axi_bready; output [0:0]m_axi_awid; output [31:0]m_axi_awaddr; - output [3:0]m_axi_awlen; + output [7:0]m_axi_awlen; output [2:0]m_axi_awsize; output [1:0]m_axi_awburst; - output [1:0]m_axi_awlock; + output [0:0]m_axi_awlock; output [3:0]m_axi_awcache; output [2:0]m_axi_awprot; output [3:0]m_axi_awqos; @@ -3930,10 +4001,10 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 output m_axi_bready; input [0:0]s_axi_arid; input [31:0]s_axi_araddr; - input [3:0]s_axi_arlen; + input [7:0]s_axi_arlen; input [2:0]s_axi_arsize; input [1:0]s_axi_arburst; - input [1:0]s_axi_arlock; + input [0:0]s_axi_arlock; input [3:0]s_axi_arcache; input [2:0]s_axi_arprot; input [3:0]s_axi_arqos; @@ -3950,10 +4021,10 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 input s_axi_rready; output [0:0]m_axi_arid; output [31:0]m_axi_araddr; - output [3:0]m_axi_arlen; + output [7:0]m_axi_arlen; output [2:0]m_axi_arsize; output [1:0]m_axi_arburst; - output [1:0]m_axi_arlock; + output [0:0]m_axi_arlock; output [3:0]m_axi_arcache; output [2:0]m_axi_arprot; output [3:0]m_axi_arqos; @@ -4070,11 +4141,12 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 wire [1:0]m_axi_arburst; wire [3:0]m_axi_arcache; wire [0:0]m_axi_arid; - wire [3:0]m_axi_arlen; - wire [1:0]m_axi_arlock; + wire [7:0]m_axi_arlen; + wire [0:0]m_axi_arlock; wire [2:0]m_axi_arprot; wire [3:0]m_axi_arqos; wire m_axi_arready; + wire [3:0]m_axi_arregion; wire [2:0]m_axi_arsize; wire [0:0]m_axi_aruser; wire m_axi_arvalid; @@ -4091,11 +4163,12 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 wire [1:0]s_axi_arburst; wire [3:0]s_axi_arcache; wire [0:0]s_axi_arid; - wire [3:0]s_axi_arlen; - wire [1:0]s_axi_arlock; + wire [7:0]s_axi_arlen; + wire [0:0]s_axi_arlock; wire [2:0]s_axi_arprot; wire [3:0]s_axi_arqos; wire s_axi_arready; + wire [3:0]s_axi_arregion; wire [2:0]s_axi_arsize; wire [0:0]s_axi_aruser; wire s_axi_arvalid; @@ -4296,10 +4369,6 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 assign dout[0] = \ ; assign empty = \ ; assign full = \ ; - assign m_axi_arregion[3] = \ ; - assign m_axi_arregion[2] = \ ; - assign m_axi_arregion[1] = \ ; - assign m_axi_arregion[0] = \ ; assign m_axi_awaddr[31] = \ ; assign m_axi_awaddr[30] = \ ; assign m_axi_awaddr[29] = \ ; @@ -4339,11 +4408,14 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 assign m_axi_awcache[1] = \ ; assign m_axi_awcache[0] = \ ; assign m_axi_awid[0] = \ ; + assign m_axi_awlen[7] = \ ; + assign m_axi_awlen[6] = \ ; + assign m_axi_awlen[5] = \ ; + assign m_axi_awlen[4] = \ ; assign m_axi_awlen[3] = \ ; assign m_axi_awlen[2] = \ ; assign m_axi_awlen[1] = \ ; assign m_axi_awlen[0] = \ ; - assign m_axi_awlock[1] = \ ; assign m_axi_awlock[0] = \ ; assign m_axi_awprot[2] = \ ; assign m_axi_awprot[1] = \ ; @@ -4568,10 +4640,10 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 GND GND (.G(\ )); Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3_synth inst_fifo_gen - (.DI({s_axi_arid,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arqos,s_axi_aruser}), + (.DI({s_axi_arid,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arqos,s_axi_arregion,s_axi_aruser}), .DIADI({m_axi_rresp,m_axi_ruser,m_axi_rlast}), .Q({s_axi_rid,s_axi_rdata,s_axi_rresp,s_axi_ruser,s_axi_rlast}), - .UNCONN_OUT({m_axi_arid,m_axi_araddr,m_axi_arlen,m_axi_arsize,m_axi_arburst,m_axi_arlock,m_axi_arcache,m_axi_arprot,m_axi_arqos,m_axi_aruser}), + .UNCONN_OUT({m_axi_arid,m_axi_araddr,m_axi_arlen,m_axi_arsize,m_axi_arburst,m_axi_arlock,m_axi_arcache,m_axi_arprot,m_axi_arqos,m_axi_arregion,m_axi_aruser}), .m_axi_arready(m_axi_arready), .m_axi_arvalid(m_axi_arvalid), .m_axi_rdata(m_axi_rdata), @@ -4593,47 +4665,47 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3_synth s_axi_arready, s_axi_rvalid, m_axi_rready, - s_axi_rready, + s_axi_arvalid, s_aclk, m_axi_rdata, DIADI, m_axi_rid, m_axi_arready, DI, + s_axi_rready, m_axi_rvalid, - s_axi_arvalid, s_aresetn); output [68:0]Q; output m_axi_arvalid; - output [55:0]UNCONN_OUT; + output [62:0]UNCONN_OUT; output s_axi_arready; output s_axi_rvalid; output m_axi_rready; - input s_axi_rready; + input s_axi_arvalid; input s_aclk; input [63:0]m_axi_rdata; input [3:0]DIADI; input [0:0]m_axi_rid; input m_axi_arready; - input [55:0]DI; + input [62:0]DI; + input s_axi_rready; input m_axi_rvalid; - input s_axi_arvalid; input s_aresetn; - wire [55:0]DI; + wire [62:0]DI; wire [3:0]DIADI; - wire [3:0]L; + wire [7:0]L; wire [68:0]Q; - wire [55:0]UNCONN_OUT; - wire \_inferred__0/i__carry__0_n_0 ; - wire \_inferred__0/i__carry__0_n_1 ; - wire \_inferred__0/i__carry__0_n_2 ; - wire \_inferred__0/i__carry__0_n_3 ; - wire \_inferred__0/i__carry__1_n_3 ; - wire \_inferred__0/i__carry_n_0 ; - wire \_inferred__0/i__carry_n_1 ; - wire \_inferred__0/i__carry_n_2 ; - wire \_inferred__0/i__carry_n_3 ; + wire [62:0]UNCONN_OUT; + wire _carry__0_n_0; + wire _carry__0_n_1; + wire _carry__0_n_2; + wire _carry__0_n_3; + wire _carry__1_n_3; + wire _carry_n_0; + wire _carry_n_1; + wire _carry_n_2; + wire _carry_n_3; wire arready_pkt; wire arvalid_en; wire arvalid_en0_carry_n_0; @@ -4641,10 +4713,6 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3_synth wire arvalid_en0_carry_n_2; wire arvalid_en0_carry_n_3; wire empty_fb_rdch; - wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_3_n_0 ; - wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_4_n_0 ; - wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_5_n_0 ; - wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_6_n_0 ; wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[9]_i_5_n_0 ; wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[9]_i_6_n_0 ; wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[0] ; @@ -4684,10 +4752,6 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3_synth wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_31 ; wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_32 ; wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_33 ; - wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_34 ; - wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_35 ; - wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_36 ; - wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_37 ; wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_4 ; wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_42 ; wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_43 ; @@ -4713,26 +4777,32 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3_synth wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_61 ; wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_62 ; wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_63 ; - wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_64 ; - wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_65 ; wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_7 ; + wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_74 ; + wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_75 ; wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_76 ; - wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_77 ; wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_78 ; wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_79 ; wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_8 ; + wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_80 ; wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_81 ; wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_82 ; wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_83 ; wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_84 ; wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_85 ; wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_86 ; + wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_87 ; + wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_88 ; + wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_89 ; wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_9 ; + wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_90 ; + wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_91 ; + wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_92 ; + wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_93 ; + wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_94 ; + wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_95 ; + wire \gaxi_full_lite.gread_ch.grach2.axi_rach_n_96 ; wire \gaxi_full_lite.gread_ch.grdch2.axi_rdch_n_1 ; - wire i__carry__0_i_2_n_0; - wire i__carry__0_i_3_n_0; - wire i__carry__1_i_1_n_0; - wire i__carry__1_i_2_n_0; wire inverted_reset; wire m_axi_arready; wire m_axi_arvalid; @@ -4750,72 +4820,52 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3_synth wire s_axi_arvalid; wire s_axi_rready; wire s_axi_rvalid; - wire [3:1]\NLW__inferred__0/i__carry__1_CO_UNCONNECTED ; - wire [3:2]\NLW__inferred__0/i__carry__1_O_UNCONNECTED ; + wire [3:1]NLW__carry__1_CO_UNCONNECTED; + wire [3:2]NLW__carry__1_O_UNCONNECTED; wire [3:0]NLW_arvalid_en0_carry_O_UNCONNECTED; wire [3:1]NLW_arvalid_en0_carry__0_CO_UNCONNECTED; wire [3:0]NLW_arvalid_en0_carry__0_O_UNCONNECTED; (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) - CARRY4 \_inferred__0/i__carry + CARRY4 _carry (.CI(1'b0), - .CO({\_inferred__0/i__carry_n_0 ,\_inferred__0/i__carry_n_1 ,\_inferred__0/i__carry_n_2 ,\_inferred__0/i__carry_n_3 }), + .CO({_carry_n_0,_carry_n_1,_carry_n_2,_carry_n_3}), .CYINIT(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[0] ), - .DI({\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[3] ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[2] ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[1] ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_78 }), + .DI({\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[3] ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[2] ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[1] ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_76 }), .O(rd_fifo_free_space[3:0]), - .S({\gaxi_full_lite.gread_ch.grach2.axi_rach_n_1 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_2 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_3 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_4 })); + .S({\gaxi_full_lite.gread_ch.grach2.axi_rach_n_88 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_89 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_90 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_91 })); (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) - CARRY4 \_inferred__0/i__carry__0 - (.CI(\_inferred__0/i__carry_n_0 ), - .CO({\_inferred__0/i__carry__0_n_0 ,\_inferred__0/i__carry__0_n_1 ,\_inferred__0/i__carry__0_n_2 ,\_inferred__0/i__carry__0_n_3 }), + CARRY4 _carry__0 + (.CI(_carry_n_0), + .CO({_carry__0_n_0,_carry__0_n_1,_carry__0_n_2,_carry__0_n_3}), .CYINIT(1'b0), - .DI({\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[6] ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[5] ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_79 ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[4] }), + .DI({\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[7] ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[6] ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[5] ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[4] }), .O(rd_fifo_free_space[7:4]), - .S({i__carry__0_i_2_n_0,i__carry__0_i_3_n_0,\gaxi_full_lite.gread_ch.grdch2.axi_rdch_n_1 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_86 })); + .S({\gaxi_full_lite.gread_ch.grach2.axi_rach_n_92 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_93 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_94 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_95 })); (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) - CARRY4 \_inferred__0/i__carry__1 - (.CI(\_inferred__0/i__carry__0_n_0 ), - .CO({\NLW__inferred__0/i__carry__1_CO_UNCONNECTED [3:1],\_inferred__0/i__carry__1_n_3 }), + CARRY4 _carry__1 + (.CI(_carry__0_n_0), + .CO({NLW__carry__1_CO_UNCONNECTED[3:1],_carry__1_n_3}), .CYINIT(1'b0), - .DI({1'b0,1'b0,1'b0,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[7] }), - .O({\NLW__inferred__0/i__carry__1_O_UNCONNECTED [3:2],rd_fifo_free_space[9:8]}), - .S({1'b0,1'b0,i__carry__1_i_1_n_0,i__carry__1_i_2_n_0})); + .DI({1'b0,1'b0,1'b0,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[8] }), + .O({NLW__carry__1_O_UNCONNECTED[3:2],rd_fifo_free_space[9:8]}), + .S({1'b0,1'b0,\gaxi_full_lite.gread_ch.grdch2.axi_rdch_n_1 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_96 })); (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY4 arvalid_en0_carry (.CI(1'b0), .CO({arvalid_en0_carry_n_0,arvalid_en0_carry_n_1,arvalid_en0_carry_n_2,arvalid_en0_carry_n_3}), .CYINIT(1'b0), - .DI({\gaxi_full_lite.gread_ch.grach2.axi_rach_n_81 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_82 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_83 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_84 }), + .DI({\gaxi_full_lite.gread_ch.grach2.axi_rach_n_82 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_83 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_84 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_85 }), .O(NLW_arvalid_en0_carry_O_UNCONNECTED[3:0]), - .S({\gaxi_full_lite.gread_ch.grach2.axi_rach_n_61 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_62 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_63 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_64 })); + .S({\gaxi_full_lite.gread_ch.grach2.axi_rach_n_78 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_79 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_80 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_81 })); (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY4 arvalid_en0_carry__0 (.CI(arvalid_en0_carry_n_0), .CO({NLW_arvalid_en0_carry__0_CO_UNCONNECTED[3:1],arvalid_en}), .CYINIT(1'b0), - .DI({1'b0,1'b0,1'b0,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_85 }), + .DI({1'b0,1'b0,1'b0,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_86 }), .O(NLW_arvalid_en0_carry__0_O_UNCONNECTED[3:0]), - .S({1'b0,1'b0,1'b0,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_65 })); - LUT1 #( - .INIT(2'h1)) - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_3 - (.I0(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[7] ), - .O(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_3_n_0 )); - LUT1 #( - .INIT(2'h1)) - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_4 - (.I0(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[6] ), - .O(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_4_n_0 )); - LUT1 #( - .INIT(2'h1)) - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_5 - (.I0(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[5] ), - .O(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_5_n_0 )); - LUT1 #( - .INIT(2'h1)) - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_6 - (.I0(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[4] ), - .O(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_6_n_0 )); + .S({1'b0,1'b0,1'b0,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_87 })); LUT1 #( .INIT(2'h1)) \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[9]_i_5 @@ -4830,7 +4880,7 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3_synth .INIT(1'b0)) \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0] (.C(s_aclk), - .CE(\gaxi_full_lite.gread_ch.grach2.axi_rach_n_76 ), + .CE(\gaxi_full_lite.gread_ch.grach2.axi_rach_n_74 ), .CLR(p_0_out_2), .D(p_1_in[0]), .Q(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[0] )); @@ -4838,7 +4888,7 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3_synth .INIT(1'b0)) \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[1] (.C(s_aclk), - .CE(\gaxi_full_lite.gread_ch.grach2.axi_rach_n_76 ), + .CE(\gaxi_full_lite.gread_ch.grach2.axi_rach_n_74 ), .CLR(p_0_out_2), .D(p_1_in[1]), .Q(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[1] )); @@ -4846,7 +4896,7 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3_synth .INIT(1'b0)) \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[2] (.C(s_aclk), - .CE(\gaxi_full_lite.gread_ch.grach2.axi_rach_n_76 ), + .CE(\gaxi_full_lite.gread_ch.grach2.axi_rach_n_74 ), .CLR(p_0_out_2), .D(p_1_in[2]), .Q(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[2] )); @@ -4854,7 +4904,7 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3_synth .INIT(1'b0)) \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3] (.C(s_aclk), - .CE(\gaxi_full_lite.gread_ch.grach2.axi_rach_n_76 ), + .CE(\gaxi_full_lite.gread_ch.grach2.axi_rach_n_74 ), .CLR(p_0_out_2), .D(p_1_in[3]), .Q(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[3] )); @@ -4862,7 +4912,7 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3_synth .INIT(1'b0)) \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[4] (.C(s_aclk), - .CE(\gaxi_full_lite.gread_ch.grach2.axi_rach_n_76 ), + .CE(\gaxi_full_lite.gread_ch.grach2.axi_rach_n_74 ), .CLR(p_0_out_2), .D(p_1_in[4]), .Q(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[4] )); @@ -4870,7 +4920,7 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3_synth .INIT(1'b0)) \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[5] (.C(s_aclk), - .CE(\gaxi_full_lite.gread_ch.grach2.axi_rach_n_76 ), + .CE(\gaxi_full_lite.gread_ch.grach2.axi_rach_n_74 ), .CLR(p_0_out_2), .D(p_1_in[5]), .Q(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[5] )); @@ -4878,7 +4928,7 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3_synth .INIT(1'b0)) \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[6] (.C(s_aclk), - .CE(\gaxi_full_lite.gread_ch.grach2.axi_rach_n_76 ), + .CE(\gaxi_full_lite.gread_ch.grach2.axi_rach_n_74 ), .CLR(p_0_out_2), .D(p_1_in[6]), .Q(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[6] )); @@ -4886,7 +4936,7 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3_synth .INIT(1'b0)) \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] (.C(s_aclk), - .CE(\gaxi_full_lite.gread_ch.grach2.axi_rach_n_76 ), + .CE(\gaxi_full_lite.gread_ch.grach2.axi_rach_n_74 ), .CLR(p_0_out_2), .D(p_1_in[7]), .Q(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[7] )); @@ -4894,7 +4944,7 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3_synth .INIT(1'b0)) \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] (.C(s_aclk), - .CE(\gaxi_full_lite.gread_ch.grach2.axi_rach_n_76 ), + .CE(\gaxi_full_lite.gread_ch.grach2.axi_rach_n_74 ), .CLR(p_0_out_2), .D(p_1_in[8]), .Q(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[8] )); @@ -4902,30 +4952,29 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3_synth .INIT(1'b0)) \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] (.C(s_aclk), - .CE(\gaxi_full_lite.gread_ch.grach2.axi_rach_n_76 ), + .CE(\gaxi_full_lite.gread_ch.grach2.axi_rach_n_74 ), .D(p_1_in[9]), .PRE(p_0_out_2), .Q(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[9] )); Arty_Z7_20_s00_data_fifo_0_fifo_generator_top \gaxi_full_lite.gread_ch.grach2.axi_rach (.CO(arvalid_en), .D(p_1_in), - .DI(\gaxi_full_lite.gread_ch.grach2.axi_rach_n_78 ), - .E(\gaxi_full_lite.gread_ch.grach2.axi_rach_n_76 ), - .Q({\gaxi_full_lite.gread_ch.grach2.axi_rach_n_5 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_6 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_7 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_8 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_9 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_10 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_11 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_12 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_13 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_14 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_15 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_16 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_17 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_18 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_19 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_20 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_21 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_22 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_23 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_24 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_25 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_26 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_27 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_28 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_29 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_30 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_31 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_32 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_33 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_34 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_35 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_36 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_37 ,L,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_42 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_43 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_44 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_45 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_46 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_47 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_48 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_49 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_50 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_51 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_52 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_53 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_54 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_55 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_56 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_57 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_58 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_59 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_60 }), - .S({\gaxi_full_lite.gread_ch.grach2.axi_rach_n_1 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_2 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_3 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_4 }), + .DI({\gaxi_full_lite.gread_ch.grach2.axi_rach_n_82 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_83 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_84 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_85 }), + .E(\gaxi_full_lite.gread_ch.grach2.axi_rach_n_74 ), + .Q({\gaxi_full_lite.gread_ch.grach2.axi_rach_n_1 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_2 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_3 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_4 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_5 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_6 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_7 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_8 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_9 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_10 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_11 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_12 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_13 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_14 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_15 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_16 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_17 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_18 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_19 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_20 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_21 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_22 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_23 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_24 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_25 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_26 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_27 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_28 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_29 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_30 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_31 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_32 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_33 ,L,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_42 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_43 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_44 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_45 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_46 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_47 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_48 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_49 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_50 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_51 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_52 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_53 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_54 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_55 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_56 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_57 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_58 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_59 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_60 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_61 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_62 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_63 }), + .S({\gaxi_full_lite.gread_ch.grach2.axi_rach_n_78 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_79 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_80 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_81 }), .UNCONN_IN(DI), - .aempty_fwft_i_reg(\gaxi_full_lite.gread_ch.grach2.axi_rach_n_77 ), + .aempty_fwft_i_reg(\gaxi_full_lite.gread_ch.grach2.axi_rach_n_75 ), .arready_pkt(arready_pkt), .empty_fwft_fb_o_i_reg(empty_fb_rdch), - .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] (\gaxi_full_lite.gread_ch.grach2.axi_rach_n_79 ), - .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_0 (\gaxi_full_lite.gread_ch.grach2.axi_rach_n_86 ), - .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_1 ({\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_3_n_0 ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_4_n_0 ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_5_n_0 ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_6_n_0 }), - .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ({\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[9] ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[8] ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[7] ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[6] ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[5] ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[4] ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[3] ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[2] ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[1] ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[0] }), - .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0 ({\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[9]_i_5_n_0 ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[9]_i_6_n_0 }), - .\gfwd_rev_pipeline1.s_ready_i_reg ({\gaxi_full_lite.gread_ch.grach2.axi_rach_n_61 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_62 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_63 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_64 }), - .\gfwd_rev_pipeline1.s_ready_i_reg_0 (\gaxi_full_lite.gread_ch.grach2.axi_rach_n_65 ), - .\gfwd_rev_pipeline1.s_ready_i_reg_1 ({\gaxi_full_lite.gread_ch.grach2.axi_rach_n_81 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_82 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_83 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_84 }), - .\gfwd_rev_pipeline1.s_ready_i_reg_2 (\gaxi_full_lite.gread_ch.grach2.axi_rach_n_85 ), + .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3] (\gaxi_full_lite.gread_ch.grach2.axi_rach_n_76 ), + .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0 ({\gaxi_full_lite.gread_ch.grach2.axi_rach_n_88 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_89 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_90 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_91 }), + .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] ({\gaxi_full_lite.gread_ch.grach2.axi_rach_n_92 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_93 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_94 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_95 }), + .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] (\gaxi_full_lite.gread_ch.grach2.axi_rach_n_96 ), + .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0 ({\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[9] ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[8] ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[7] ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[6] ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[5] ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[4] ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[3] ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[2] ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[1] ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[0] }), + .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_1 ({\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[9]_i_5_n_0 ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[9]_i_6_n_0 }), + .\gfwd_rev_pipeline1.s_ready_i_reg (\gaxi_full_lite.gread_ch.grach2.axi_rach_n_86 ), + .\gfwd_rev_pipeline1.s_ready_i_reg_0 (\gaxi_full_lite.gread_ch.grach2.axi_rach_n_87 ), .inverted_reset(inverted_reset), .out(rach_empty), .rd_fifo_free_space(rd_fifo_free_space), @@ -4935,10 +4984,10 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3_synth .s_axi_rready(s_axi_rready)); Arty_Z7_20_s00_data_fifo_0_axi_reg_slice \gaxi_full_lite.gread_ch.grach2.gaxi_arvld.rach_pkt_reg_slice (.CO(arvalid_en), - .D({\gaxi_full_lite.gread_ch.grach2.axi_rach_n_5 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_6 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_7 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_8 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_9 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_10 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_11 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_12 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_13 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_14 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_15 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_16 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_17 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_18 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_19 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_20 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_21 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_22 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_23 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_24 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_25 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_26 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_27 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_28 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_29 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_30 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_31 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_32 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_33 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_34 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_35 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_36 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_37 ,L,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_42 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_43 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_44 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_45 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_46 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_47 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_48 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_49 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_50 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_51 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_52 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_53 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_54 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_55 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_56 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_57 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_58 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_59 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_60 }), + .D({\gaxi_full_lite.gread_ch.grach2.axi_rach_n_1 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_2 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_3 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_4 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_5 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_6 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_7 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_8 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_9 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_10 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_11 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_12 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_13 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_14 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_15 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_16 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_17 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_18 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_19 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_20 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_21 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_22 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_23 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_24 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_25 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_26 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_27 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_28 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_29 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_30 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_31 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_32 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_33 ,L,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_42 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_43 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_44 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_45 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_46 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_47 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_48 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_49 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_50 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_51 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_52 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_53 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_54 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_55 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_56 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_57 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_58 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_59 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_60 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_61 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_62 ,\gaxi_full_lite.gread_ch.grach2.axi_rach_n_63 }), .UNCONN_OUT(UNCONN_OUT), .arready_pkt(arready_pkt), - .\gfwd_rev_pipeline1.s_ready_i_reg_0 (\gaxi_full_lite.gread_ch.grach2.axi_rach_n_77 ), + .\gfwd_rev_pipeline1.s_ready_i_reg_0 (\gaxi_full_lite.gread_ch.grach2.axi_rach_n_75 ), .inverted_reset(inverted_reset), .m_axi_arready(m_axi_arready), .m_axi_arvalid(m_axi_arvalid), @@ -4948,7 +4997,7 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3_synth Arty_Z7_20_s00_data_fifo_0_fifo_generator_top__parameterized0 \gaxi_full_lite.gread_ch.grdch2.axi_rdch (.CO(arvalid_en), .DIADI(DIADI), - .Q(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[5] ), + .Q(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[9] ), .S(\gaxi_full_lite.gread_ch.grdch2.axi_rdch_n_1 ), .UNCONN_OUT(Q), .arready_pkt(arready_pkt), @@ -4962,30 +5011,6 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3_synth .s_aclk(s_aclk), .s_axi_rready(s_axi_rready), .s_axi_rvalid(s_axi_rvalid)); - LUT2 #( - .INIT(4'h9)) - i__carry__0_i_2 - (.I0(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[6] ), - .I1(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[7] ), - .O(i__carry__0_i_2_n_0)); - LUT2 #( - .INIT(4'h9)) - i__carry__0_i_3 - (.I0(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[5] ), - .I1(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[6] ), - .O(i__carry__0_i_3_n_0)); - LUT2 #( - .INIT(4'h9)) - i__carry__1_i_1 - (.I0(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[8] ), - .I1(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[9] ), - .O(i__carry__1_i_1_n_0)); - LUT2 #( - .INIT(4'h9)) - i__carry__1_i_2 - (.I0(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[7] ), - .I1(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[8] ), - .O(i__carry__1_i_2_n_0)); Arty_Z7_20_s00_data_fifo_0_reset_blk_ramfifo \reset_gen_cc.rstblk_cc (.AR(p_0_out_2), .inverted_reset(inverted_reset), @@ -4993,238 +5018,390 @@ module Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3_synth endmodule module Arty_Z7_20_s00_data_fifo_0_memory - (S, - Q, + (Q, D, - DI, aempty_fwft_i_reg, - \gfwd_rev_pipeline1.s_ready_i_reg , - \gfwd_rev_pipeline1.s_ready_i_reg_0 , + S, + DI, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3] , \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] , - out, - CO, - arready_pkt, - s_axi_rready, - empty_fwft_fb_o_i_reg, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] , \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] , - rd_fifo_free_space, empty_fwft_i_reg, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_0 , - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] , + rd_fifo_free_space, + CO, + arready_pkt, + out, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0 , empty_fwft_i_reg_0, E, s_aclk, - ram_full_fb_i_reg, + EN, UNCONN_IN, \gc0.count_d1_reg[4] , \gcc0.gc0.count_d1_reg[4] , - \gpregsm1.curr_fwft_state_reg[0] ); - output [3:0]S; - output [55:0]Q; + ram_empty_fb_i_reg); + output [62:0]Q; output [9:0]D; - output [0:0]DI; output aempty_fwft_i_reg; - output [1:0]\gfwd_rev_pipeline1.s_ready_i_reg ; - output [1:0]\gfwd_rev_pipeline1.s_ready_i_reg_0 ; - output [0:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] ; - input out; - input [0:0]CO; - input arready_pkt; - input s_axi_rready; - input empty_fwft_fb_o_i_reg; + output [3:0]S; + output [3:0]DI; + output [2:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3] ; + output [3:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] ; + output [0:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ; input [8:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] ; - input [9:0]rd_fifo_free_space; input empty_fwft_i_reg; - input [3:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_0 ; - input [1:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ; + input [9:0]rd_fifo_free_space; + input [0:0]CO; + input arready_pkt; + input out; + input [1:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0 ; input empty_fwft_i_reg_0; input [0:0]E; input s_aclk; - input [0:0]ram_full_fb_i_reg; - input [55:0]UNCONN_IN; + input EN; + input [62:0]UNCONN_IN; input [4:0]\gc0.count_d1_reg[4] ; input [4:0]\gcc0.gc0.count_d1_reg[4] ; - input [0:0]\gpregsm1.curr_fwft_state_reg[0] ; + input [0:0]ram_empty_fb_i_reg; wire [0:0]CO; wire [9:0]D; - wire [0:0]DI; + wire [3:0]DI; wire [0:0]E; - wire [55:0]Q; + wire EN; + wire [62:0]Q; wire [3:0]S; - wire [55:0]UNCONN_IN; + wire [62:0]UNCONN_IN; + wire _carry__0_i_5_n_0; + wire _carry__0_i_6_n_0; + wire _carry__0_i_7_n_0; wire aempty_fwft_i_reg; wire arready_pkt; - wire [59:4]dout_i; - wire empty_fwft_fb_o_i_reg; + wire [62:0]dout_i; wire empty_fwft_i_reg; wire empty_fwft_i_reg_0; wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[3]_i_3_n_0 ; wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[3]_i_4_n_0 ; wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[3]_i_5_n_0 ; wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[3]_i_6_n_0 ; + wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_3_n_0 ; + wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_4_n_0 ; + wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_5_n_0 ; + wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_6_n_0 ; + wire [2:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3] ; wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_i_2_n_0 ; wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_i_2_n_1 ; wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_i_2_n_2 ; wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_i_2_n_3 ; - wire [0:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] ; - wire [3:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_0 ; + wire [3:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] ; wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_i_2_n_0 ; wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_i_2_n_1 ; wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_i_2_n_2 ; wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_i_2_n_3 ; wire [8:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] ; - wire [1:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ; - wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_i_4_n_3 ; + wire [0:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ; + wire [1:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0 ; + wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_i_3_n_3 ; wire [4:0]\gc0.count_d1_reg[4] ; wire [4:0]\gcc0.gc0.count_d1_reg[4] ; - wire [1:0]\gfwd_rev_pipeline1.s_ready_i_reg ; - wire [1:0]\gfwd_rev_pipeline1.s_ready_i_reg_0 ; - wire [0:0]\gpregsm1.curr_fwft_state_reg[0] ; wire [9:0]minusOp; wire out; - wire [0:0]ram_full_fb_i_reg; + wire [0:0]ram_empty_fb_i_reg; wire [9:0]rd_fifo_free_space; wire s_aclk; - wire s_axi_rready; - wire [3:1]\NLW_gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_i_4_CO_UNCONNECTED ; - wire [3:2]\NLW_gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_i_4_O_UNCONNECTED ; + wire [3:1]\NLW_gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_i_3_CO_UNCONNECTED ; + wire [3:2]\NLW_gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_i_3_O_UNCONNECTED ; + LUT5 #( + .INIT(32'h9AFF6500)) + _carry__0_i_1 + (.I0(Q[29]), + .I1(_carry__0_i_5_n_0), + .I2(Q[28]), + .I3(empty_fwft_i_reg_0), + .I4(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [7]), + .O(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] [3])); LUT4 #( - .INIT(16'h22B2)) - arvalid_en0_carry_i_3 - (.I0(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [3]), + .INIT(16'h9F60)) + _carry__0_i_2 + (.I0(Q[28]), + .I1(_carry__0_i_5_n_0), + .I2(empty_fwft_i_reg_0), + .I3(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [6]), + .O(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] [2])); + LUT4 #( + .INIT(16'h9F60)) + _carry__0_i_3 + (.I0(Q[27]), + .I1(_carry__0_i_6_n_0), + .I2(empty_fwft_i_reg_0), + .I3(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [5]), + .O(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] [1])); + LUT4 #( + .INIT(16'h9F60)) + _carry__0_i_4 + (.I0(Q[26]), + .I1(_carry__0_i_7_n_0), + .I2(empty_fwft_i_reg_0), + .I3(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [4]), + .O(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] [0])); + LUT6 #( + .INIT(64'h7FFFFFFFFFFFFFFF)) + _carry__0_i_5 + (.I0(Q[26]), + .I1(Q[24]), + .I2(Q[23]), + .I3(Q[22]), + .I4(Q[25]), + .I5(Q[27]), + .O(_carry__0_i_5_n_0)); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT5 #( + .INIT(32'h7FFFFFFF)) + _carry__0_i_6 + (.I0(Q[25]), + .I1(Q[22]), + .I2(Q[23]), + .I3(Q[24]), + .I4(Q[26]), + .O(_carry__0_i_6_n_0)); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7FFF)) + _carry__0_i_7 + (.I0(Q[24]), + .I1(Q[23]), + .I2(Q[22]), + .I3(Q[25]), + .O(_carry__0_i_7_n_0)); + LUT5 #( + .INIT(32'h40FFBF00)) + _carry__1_i_2 + (.I0(_carry__0_i_5_n_0), + .I1(Q[28]), + .I2(Q[29]), + .I3(empty_fwft_i_reg_0), + .I4(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [8]), + .O(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] )); + LUT6 #( + .INIT(64'h6AAAFFFF95550000)) + _carry_i_2 + (.I0(Q[25]), + .I1(Q[24]), + .I2(Q[23]), + .I3(Q[22]), + .I4(empty_fwft_i_reg_0), + .I5(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [3]), + .O(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3] [2])); + LUT5 #( + .INIT(32'h6AFF9500)) + _carry_i_3 + (.I0(Q[24]), .I1(Q[22]), - .I2(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [2]), - .I3(Q[21]), - .O(\gfwd_rev_pipeline1.s_ready_i_reg [1])); + .I2(Q[23]), + .I3(empty_fwft_i_reg_0), + .I4(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [2]), + .O(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3] [1])); + LUT4 #( + .INIT(16'h6F90)) + _carry_i_4 + (.I0(Q[23]), + .I1(Q[22]), + .I2(empty_fwft_i_reg_0), + .I3(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [1]), + .O(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3] [0])); + LUT4 #( + .INIT(16'h2F02)) + arvalid_en0_carry_i_1 + (.I0(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [6]), + .I1(Q[28]), + .I2(Q[29]), + .I3(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [7]), + .O(DI[3])); LUT4 #( - .INIT(16'h22B2)) + .INIT(16'h2F02)) + arvalid_en0_carry_i_2 + (.I0(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [4]), + .I1(Q[26]), + .I2(Q[27]), + .I3(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [5]), + .O(DI[2])); + LUT4 #( + .INIT(16'h2F02)) + arvalid_en0_carry_i_3 + (.I0(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [2]), + .I1(Q[24]), + .I2(Q[25]), + .I3(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [3]), + .O(DI[1])); + LUT4 #( + .INIT(16'h2F02)) arvalid_en0_carry_i_4 - (.I0(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [1]), - .I1(Q[20]), - .I2(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [0]), - .I3(Q[19]), - .O(\gfwd_rev_pipeline1.s_ready_i_reg [0])); + (.I0(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [0]), + .I1(Q[22]), + .I2(Q[23]), + .I3(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [1]), + .O(DI[0])); + LUT4 #( + .INIT(16'h9009)) + arvalid_en0_carry_i_5 + (.I0(Q[28]), + .I1(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [6]), + .I2(Q[29]), + .I3(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [7]), + .O(S[3])); + LUT4 #( + .INIT(16'h9009)) + arvalid_en0_carry_i_6 + (.I0(Q[26]), + .I1(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [4]), + .I2(Q[27]), + .I3(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [5]), + .O(S[2])); LUT4 #( .INIT(16'h9009)) arvalid_en0_carry_i_7 - (.I0(Q[22]), - .I1(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [3]), - .I2(Q[21]), - .I3(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [2]), - .O(\gfwd_rev_pipeline1.s_ready_i_reg_0 [1])); + (.I0(Q[24]), + .I1(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [2]), + .I2(Q[25]), + .I3(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [3]), + .O(S[1])); LUT4 #( .INIT(16'h9009)) arvalid_en0_carry_i_8 - (.I0(Q[20]), - .I1(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [1]), - .I2(Q[19]), - .I3(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [0]), - .O(\gfwd_rev_pipeline1.s_ready_i_reg_0 [0])); - (* SOFT_HLUTNM = "soft_lutpair8" *) + (.I0(Q[22]), + .I1(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [0]), + .I2(Q[23]), + .I3(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [1]), + .O(S[0])); + (* SOFT_HLUTNM = "soft_lutpair9" *) LUT3 #( .INIT(8'hB8)) \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[0]_i_1 - (.I0(rd_fifo_free_space[0]), + (.I0(minusOp[0]), .I1(empty_fwft_i_reg), - .I2(minusOp[0]), + .I2(rd_fifo_free_space[0]), .O(D[0])); (* SOFT_HLUTNM = "soft_lutpair8" *) LUT3 #( .INIT(8'hB8)) \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[1]_i_1 - (.I0(rd_fifo_free_space[1]), + (.I0(minusOp[1]), .I1(empty_fwft_i_reg), - .I2(minusOp[1]), + .I2(rd_fifo_free_space[1]), .O(D[1])); - (* SOFT_HLUTNM = "soft_lutpair7" *) + (* SOFT_HLUTNM = "soft_lutpair9" *) LUT3 #( .INIT(8'hB8)) \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[2]_i_1 - (.I0(rd_fifo_free_space[2]), + (.I0(minusOp[2]), .I1(empty_fwft_i_reg), - .I2(minusOp[2]), + .I2(rd_fifo_free_space[2]), .O(D[2])); - (* SOFT_HLUTNM = "soft_lutpair7" *) + (* SOFT_HLUTNM = "soft_lutpair8" *) LUT3 #( .INIT(8'hB8)) \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[3]_i_1 - (.I0(rd_fifo_free_space[3]), + (.I0(minusOp[3]), .I1(empty_fwft_i_reg), - .I2(minusOp[3]), + .I2(rd_fifo_free_space[3]), .O(D[3])); LUT2 #( .INIT(4'h9)) \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[3]_i_3 (.I0(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [3]), - .I1(Q[22]), + .I1(Q[25]), .O(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[3]_i_3_n_0 )); LUT2 #( .INIT(4'h9)) \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[3]_i_4 (.I0(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [2]), - .I1(Q[21]), + .I1(Q[24]), .O(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[3]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[3]_i_5 (.I0(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [1]), - .I1(Q[20]), + .I1(Q[23]), .O(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[3]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[3]_i_6 (.I0(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [0]), - .I1(Q[19]), + .I1(Q[22]), .O(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[3]_i_6_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair6" *) + (* SOFT_HLUTNM = "soft_lutpair7" *) LUT3 #( .INIT(8'hB8)) \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[4]_i_1 - (.I0(rd_fifo_free_space[4]), + (.I0(minusOp[4]), .I1(empty_fwft_i_reg), - .I2(minusOp[4]), + .I2(rd_fifo_free_space[4]), .O(D[4])); (* SOFT_HLUTNM = "soft_lutpair5" *) LUT3 #( .INIT(8'hB8)) \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[5]_i_1 - (.I0(rd_fifo_free_space[5]), + (.I0(minusOp[5]), .I1(empty_fwft_i_reg), - .I2(minusOp[5]), + .I2(rd_fifo_free_space[5]), .O(D[5])); (* SOFT_HLUTNM = "soft_lutpair6" *) LUT3 #( .INIT(8'hB8)) \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[6]_i_1 - (.I0(rd_fifo_free_space[6]), + (.I0(minusOp[6]), .I1(empty_fwft_i_reg), - .I2(minusOp[6]), + .I2(rd_fifo_free_space[6]), .O(D[6])); - (* SOFT_HLUTNM = "soft_lutpair5" *) + (* SOFT_HLUTNM = "soft_lutpair7" *) LUT3 #( .INIT(8'hB8)) \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_1 - (.I0(rd_fifo_free_space[7]), + (.I0(minusOp[7]), .I1(empty_fwft_i_reg), - .I2(minusOp[7]), + .I2(rd_fifo_free_space[7]), .O(D[7])); - (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h9)) + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_3 + (.I0(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [7]), + .I1(Q[29]), + .O(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_3_n_0 )); + LUT2 #( + .INIT(4'h9)) + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_4 + (.I0(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [6]), + .I1(Q[28]), + .O(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_4_n_0 )); + LUT2 #( + .INIT(4'h9)) + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_5 + (.I0(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [5]), + .I1(Q[27]), + .O(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_5_n_0 )); + LUT2 #( + .INIT(4'h9)) + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_6 + (.I0(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [4]), + .I1(Q[26]), + .O(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) LUT3 #( .INIT(8'hB8)) \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[8]_i_1 - (.I0(rd_fifo_free_space[8]), + (.I0(minusOp[8]), .I1(empty_fwft_i_reg), - .I2(minusOp[8]), + .I2(rd_fifo_free_space[8]), .O(D[8])); - (* SOFT_HLUTNM = "soft_lutpair4" *) + (* SOFT_HLUTNM = "soft_lutpair5" *) LUT3 #( .INIT(8'hB8)) \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[9]_i_2 - (.I0(rd_fifo_free_space[9]), + (.I0(minusOp[9]), .I1(empty_fwft_i_reg), - .I2(minusOp[9]), + .I2(rd_fifo_free_space[9]), .O(D[9])); (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY4 \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_i_2 @@ -5241,37 +5418,45 @@ module Arty_Z7_20_s00_data_fifo_0_memory .CYINIT(1'b0), .DI(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [7:4]), .O(minusOp[7:4]), - .S(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_0 )); + .S({\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_3_n_0 ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_4_n_0 ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_5_n_0 ,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_6_n_0 })); (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) - CARRY4 \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_i_4 + CARRY4 \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_i_3 (.CI(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_i_2_n_0 ), - .CO({\NLW_gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_i_4_CO_UNCONNECTED [3:1],\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_i_4_n_3 }), + .CO({\NLW_gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_i_3_CO_UNCONNECTED [3:1],\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_i_3_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [8]}), - .O({\NLW_gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_i_4_O_UNCONNECTED [3:2],minusOp[9:8]}), - .S({1'b0,1'b0,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] })); + .O({\NLW_gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_i_3_O_UNCONNECTED [3:2],minusOp[9:8]}), + .S({1'b0,1'b0,\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0 })); Arty_Z7_20_s00_data_fifo_0_dmem \gdm.dm_gen.dm - (.UNCONN_IN(UNCONN_IN), + (.EN(EN), + .UNCONN_IN(UNCONN_IN), .dout_i(dout_i), .\gc0.count_d1_reg[4] (\gc0.count_d1_reg[4] ), .\gcc0.gc0.count_d1_reg[4] (\gcc0.gc0.count_d1_reg[4] ), - .\gpregsm1.curr_fwft_state_reg[0] (\gpregsm1.curr_fwft_state_reg[0] ), - .ram_full_fb_i_reg(ram_full_fb_i_reg), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), .s_aclk(s_aclk)); LUT3 #( - .INIT(8'hF7)) + .INIT(8'h08)) \gfwd_rev_pipeline1.m_valid_i_i_2 - (.I0(arready_pkt), - .I1(CO), + (.I0(CO), + .I1(arready_pkt), .I2(out), .O(aempty_fwft_i_reg)); + FDRE #( + .INIT(1'b0)) + \goreg_dm.dout_i_reg[0] + (.C(s_aclk), + .CE(E), + .D(dout_i[0]), + .Q(Q[0]), + .R(1'b0)); FDRE #( .INIT(1'b0)) \goreg_dm.dout_i_reg[10] (.C(s_aclk), .CE(E), .D(dout_i[10]), - .Q(Q[6]), + .Q(Q[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5279,7 +5464,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[11]), - .Q(Q[7]), + .Q(Q[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5287,7 +5472,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[12]), - .Q(Q[8]), + .Q(Q[12]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5295,7 +5480,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[13]), - .Q(Q[9]), + .Q(Q[13]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5303,7 +5488,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[14]), - .Q(Q[10]), + .Q(Q[14]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5311,7 +5496,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[15]), - .Q(Q[11]), + .Q(Q[15]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5319,7 +5504,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[16]), - .Q(Q[12]), + .Q(Q[16]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5327,7 +5512,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[17]), - .Q(Q[13]), + .Q(Q[17]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5335,7 +5520,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[18]), - .Q(Q[14]), + .Q(Q[18]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5343,15 +5528,23 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[19]), - .Q(Q[15]), + .Q(Q[19]), .R(1'b0)); FDRE #( .INIT(1'b0)) - \goreg_dm.dout_i_reg[20] + \goreg_dm.dout_i_reg[1] (.C(s_aclk), .CE(E), - .D(dout_i[20]), - .Q(Q[16]), + .D(dout_i[1]), + .Q(Q[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \goreg_dm.dout_i_reg[20] + (.C(s_aclk), + .CE(E), + .D(dout_i[20]), + .Q(Q[20]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5359,7 +5552,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[21]), - .Q(Q[17]), + .Q(Q[21]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5367,7 +5560,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[22]), - .Q(Q[18]), + .Q(Q[22]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5375,7 +5568,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[23]), - .Q(Q[19]), + .Q(Q[23]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5383,7 +5576,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[24]), - .Q(Q[20]), + .Q(Q[24]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5391,7 +5584,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[25]), - .Q(Q[21]), + .Q(Q[25]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5399,7 +5592,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[26]), - .Q(Q[22]), + .Q(Q[26]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5407,7 +5600,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[27]), - .Q(Q[23]), + .Q(Q[27]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5415,7 +5608,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[28]), - .Q(Q[24]), + .Q(Q[28]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5423,7 +5616,15 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[29]), - .Q(Q[25]), + .Q(Q[29]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \goreg_dm.dout_i_reg[2] + (.C(s_aclk), + .CE(E), + .D(dout_i[2]), + .Q(Q[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5431,7 +5632,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[30]), - .Q(Q[26]), + .Q(Q[30]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5439,7 +5640,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[31]), - .Q(Q[27]), + .Q(Q[31]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5447,7 +5648,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[32]), - .Q(Q[28]), + .Q(Q[32]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5455,7 +5656,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[33]), - .Q(Q[29]), + .Q(Q[33]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5463,7 +5664,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[34]), - .Q(Q[30]), + .Q(Q[34]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5471,7 +5672,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[35]), - .Q(Q[31]), + .Q(Q[35]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5479,7 +5680,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[36]), - .Q(Q[32]), + .Q(Q[36]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5487,7 +5688,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[37]), - .Q(Q[33]), + .Q(Q[37]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5495,7 +5696,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[38]), - .Q(Q[34]), + .Q(Q[38]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5503,7 +5704,15 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[39]), - .Q(Q[35]), + .Q(Q[39]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \goreg_dm.dout_i_reg[3] + (.C(s_aclk), + .CE(E), + .D(dout_i[3]), + .Q(Q[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5511,7 +5720,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[40]), - .Q(Q[36]), + .Q(Q[40]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5519,7 +5728,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[41]), - .Q(Q[37]), + .Q(Q[41]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5527,7 +5736,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[42]), - .Q(Q[38]), + .Q(Q[42]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5535,7 +5744,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[43]), - .Q(Q[39]), + .Q(Q[43]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5543,7 +5752,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[44]), - .Q(Q[40]), + .Q(Q[44]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5551,7 +5760,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[45]), - .Q(Q[41]), + .Q(Q[45]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5559,7 +5768,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[46]), - .Q(Q[42]), + .Q(Q[46]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5567,7 +5776,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[47]), - .Q(Q[43]), + .Q(Q[47]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5575,7 +5784,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[48]), - .Q(Q[44]), + .Q(Q[48]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5583,7 +5792,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[49]), - .Q(Q[45]), + .Q(Q[49]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5591,7 +5800,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[4]), - .Q(Q[0]), + .Q(Q[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5599,7 +5808,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[50]), - .Q(Q[46]), + .Q(Q[50]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5607,7 +5816,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[51]), - .Q(Q[47]), + .Q(Q[51]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5615,7 +5824,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[52]), - .Q(Q[48]), + .Q(Q[52]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5623,7 +5832,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[53]), - .Q(Q[49]), + .Q(Q[53]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5631,7 +5840,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[54]), - .Q(Q[50]), + .Q(Q[54]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5639,7 +5848,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[55]), - .Q(Q[51]), + .Q(Q[55]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5647,7 +5856,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[56]), - .Q(Q[52]), + .Q(Q[56]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5655,7 +5864,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[57]), - .Q(Q[53]), + .Q(Q[57]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5663,7 +5872,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[58]), - .Q(Q[54]), + .Q(Q[58]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5671,7 +5880,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[59]), - .Q(Q[55]), + .Q(Q[59]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5679,7 +5888,31 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[5]), - .Q(Q[1]), + .Q(Q[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \goreg_dm.dout_i_reg[60] + (.C(s_aclk), + .CE(E), + .D(dout_i[60]), + .Q(Q[60]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \goreg_dm.dout_i_reg[61] + (.C(s_aclk), + .CE(E), + .D(dout_i[61]), + .Q(Q[61]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \goreg_dm.dout_i_reg[62] + (.C(s_aclk), + .CE(E), + .D(dout_i[62]), + .Q(Q[62]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5687,7 +5920,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[6]), - .Q(Q[2]), + .Q(Q[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5695,7 +5928,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[7]), - .Q(Q[3]), + .Q(Q[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5703,7 +5936,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[8]), - .Q(Q[4]), + .Q(Q[8]), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -5711,64 +5944,8 @@ module Arty_Z7_20_s00_data_fifo_0_memory (.C(s_aclk), .CE(E), .D(dout_i[9]), - .Q(Q[5]), + .Q(Q[9]), .R(1'b0)); - LUT6 #( - .INIT(64'hEAAAAAAA15555555)) - i__carry__0_i_5 - (.I0(empty_fwft_i_reg_0), - .I1(Q[22]), - .I2(Q[21]), - .I3(Q[19]), - .I4(Q[20]), - .I5(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [4]), - .O(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] )); - LUT5 #( - .INIT(32'h0000B000)) - i__carry_i_1 - (.I0(empty_fwft_fb_o_i_reg), - .I1(s_axi_rready), - .I2(arready_pkt), - .I3(CO), - .I4(out), - .O(DI)); - LUT6 #( - .INIT(64'hFFFF7F800000807F)) - i__carry_i_2 - (.I0(Q[21]), - .I1(Q[19]), - .I2(Q[20]), - .I3(Q[22]), - .I4(empty_fwft_i_reg_0), - .I5(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [3]), - .O(S[3])); - LUT5 #( - .INIT(32'hFF780087)) - i__carry_i_3 - (.I0(Q[20]), - .I1(Q[19]), - .I2(Q[21]), - .I3(empty_fwft_i_reg_0), - .I4(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [2]), - .O(S[2])); - LUT4 #( - .INIT(16'hF609)) - i__carry_i_4 - (.I0(Q[19]), - .I1(Q[20]), - .I2(empty_fwft_i_reg_0), - .I3(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8] [1]), - .O(S[1])); - LUT6 #( - .INIT(64'hDFFFDFFFFFFFDFFF)) - i__carry_i_5 - (.I0(Q[19]), - .I1(out), - .I2(CO), - .I3(arready_pkt), - .I4(s_axi_rready), - .I5(empty_fwft_fb_o_i_reg), - .O(S[0])); endmodule (* ORIG_REF_NAME = "memory" *) @@ -5782,7 +5959,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 m_axi_rdata, DIADI, m_axi_rid, - \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ); + \gpregsm1.curr_fwft_state_reg[0] ); output [68:0]UNCONN_OUT; input s_aclk; input [0:0]E; @@ -5792,7 +5969,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 input [63:0]m_axi_rdata; input [3:0]DIADI; input [0:0]m_axi_rid; - input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ; + input [0:0]\gpregsm1.curr_fwft_state_reg[0] ; wire [3:0]DIADI; wire [0:0]E; @@ -5800,9 +5977,9 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 wire [68:0]UNCONN_OUT; wire [68:0]doutb; wire [8:0]\gc0.count_d1_reg[8] ; + wire [0:0]\gpregsm1.curr_fwft_state_reg[0] ; wire [63:0]m_axi_rdata; wire [0:0]m_axi_rid; - wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ; wire [0:0]ram_full_fb_i_reg; wire s_aclk; @@ -5820,7 +5997,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[0] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[0]), .Q(UNCONN_OUT[0]), .R(1'b0)); @@ -5828,7 +6005,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[10] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[10]), .Q(UNCONN_OUT[10]), .R(1'b0)); @@ -5836,7 +6013,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[11] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[11]), .Q(UNCONN_OUT[11]), .R(1'b0)); @@ -5844,7 +6021,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[12] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[12]), .Q(UNCONN_OUT[12]), .R(1'b0)); @@ -5852,7 +6029,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[13] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[13]), .Q(UNCONN_OUT[13]), .R(1'b0)); @@ -5860,7 +6037,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[14] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[14]), .Q(UNCONN_OUT[14]), .R(1'b0)); @@ -5868,7 +6045,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[15] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[15]), .Q(UNCONN_OUT[15]), .R(1'b0)); @@ -5876,7 +6053,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[16] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[16]), .Q(UNCONN_OUT[16]), .R(1'b0)); @@ -5884,7 +6061,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[17] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[17]), .Q(UNCONN_OUT[17]), .R(1'b0)); @@ -5892,7 +6069,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[18] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[18]), .Q(UNCONN_OUT[18]), .R(1'b0)); @@ -5900,7 +6077,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[19] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[19]), .Q(UNCONN_OUT[19]), .R(1'b0)); @@ -5908,7 +6085,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[1] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[1]), .Q(UNCONN_OUT[1]), .R(1'b0)); @@ -5916,7 +6093,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[20] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[20]), .Q(UNCONN_OUT[20]), .R(1'b0)); @@ -5924,7 +6101,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[21] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[21]), .Q(UNCONN_OUT[21]), .R(1'b0)); @@ -5932,7 +6109,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[22] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[22]), .Q(UNCONN_OUT[22]), .R(1'b0)); @@ -5940,7 +6117,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[23] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[23]), .Q(UNCONN_OUT[23]), .R(1'b0)); @@ -5948,7 +6125,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[24] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[24]), .Q(UNCONN_OUT[24]), .R(1'b0)); @@ -5956,7 +6133,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[25] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[25]), .Q(UNCONN_OUT[25]), .R(1'b0)); @@ -5964,7 +6141,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[26] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[26]), .Q(UNCONN_OUT[26]), .R(1'b0)); @@ -5972,7 +6149,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[27] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[27]), .Q(UNCONN_OUT[27]), .R(1'b0)); @@ -5980,7 +6157,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[28] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[28]), .Q(UNCONN_OUT[28]), .R(1'b0)); @@ -5988,7 +6165,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[29] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[29]), .Q(UNCONN_OUT[29]), .R(1'b0)); @@ -5996,7 +6173,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[2] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[2]), .Q(UNCONN_OUT[2]), .R(1'b0)); @@ -6004,7 +6181,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[30] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[30]), .Q(UNCONN_OUT[30]), .R(1'b0)); @@ -6012,7 +6189,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[31] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[31]), .Q(UNCONN_OUT[31]), .R(1'b0)); @@ -6020,7 +6197,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[32] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[32]), .Q(UNCONN_OUT[32]), .R(1'b0)); @@ -6028,7 +6205,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[33] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[33]), .Q(UNCONN_OUT[33]), .R(1'b0)); @@ -6036,7 +6213,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[34] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[34]), .Q(UNCONN_OUT[34]), .R(1'b0)); @@ -6044,7 +6221,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[35] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[35]), .Q(UNCONN_OUT[35]), .R(1'b0)); @@ -6052,7 +6229,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[36] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[36]), .Q(UNCONN_OUT[36]), .R(1'b0)); @@ -6060,7 +6237,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[37] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[37]), .Q(UNCONN_OUT[37]), .R(1'b0)); @@ -6068,7 +6245,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[38] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[38]), .Q(UNCONN_OUT[38]), .R(1'b0)); @@ -6076,7 +6253,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[39] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[39]), .Q(UNCONN_OUT[39]), .R(1'b0)); @@ -6084,7 +6261,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[3] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[3]), .Q(UNCONN_OUT[3]), .R(1'b0)); @@ -6092,7 +6269,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[40] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[40]), .Q(UNCONN_OUT[40]), .R(1'b0)); @@ -6100,7 +6277,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[41] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[41]), .Q(UNCONN_OUT[41]), .R(1'b0)); @@ -6108,7 +6285,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[42] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[42]), .Q(UNCONN_OUT[42]), .R(1'b0)); @@ -6116,7 +6293,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[43] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[43]), .Q(UNCONN_OUT[43]), .R(1'b0)); @@ -6124,7 +6301,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[44] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[44]), .Q(UNCONN_OUT[44]), .R(1'b0)); @@ -6132,7 +6309,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[45] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[45]), .Q(UNCONN_OUT[45]), .R(1'b0)); @@ -6140,7 +6317,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[46] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[46]), .Q(UNCONN_OUT[46]), .R(1'b0)); @@ -6148,7 +6325,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[47] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[47]), .Q(UNCONN_OUT[47]), .R(1'b0)); @@ -6156,7 +6333,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[48] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[48]), .Q(UNCONN_OUT[48]), .R(1'b0)); @@ -6164,7 +6341,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[49] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[49]), .Q(UNCONN_OUT[49]), .R(1'b0)); @@ -6172,7 +6349,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[4] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[4]), .Q(UNCONN_OUT[4]), .R(1'b0)); @@ -6180,7 +6357,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[50] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[50]), .Q(UNCONN_OUT[50]), .R(1'b0)); @@ -6188,7 +6365,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[51] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[51]), .Q(UNCONN_OUT[51]), .R(1'b0)); @@ -6196,7 +6373,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[52] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[52]), .Q(UNCONN_OUT[52]), .R(1'b0)); @@ -6204,7 +6381,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[53] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[53]), .Q(UNCONN_OUT[53]), .R(1'b0)); @@ -6212,7 +6389,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[54] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[54]), .Q(UNCONN_OUT[54]), .R(1'b0)); @@ -6220,7 +6397,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[55] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[55]), .Q(UNCONN_OUT[55]), .R(1'b0)); @@ -6228,7 +6405,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[56] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[56]), .Q(UNCONN_OUT[56]), .R(1'b0)); @@ -6236,7 +6413,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[57] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[57]), .Q(UNCONN_OUT[57]), .R(1'b0)); @@ -6244,7 +6421,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[58] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[58]), .Q(UNCONN_OUT[58]), .R(1'b0)); @@ -6252,7 +6429,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[59] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[59]), .Q(UNCONN_OUT[59]), .R(1'b0)); @@ -6260,7 +6437,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[5] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[5]), .Q(UNCONN_OUT[5]), .R(1'b0)); @@ -6268,7 +6445,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[60] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[60]), .Q(UNCONN_OUT[60]), .R(1'b0)); @@ -6276,7 +6453,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[61] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[61]), .Q(UNCONN_OUT[61]), .R(1'b0)); @@ -6284,7 +6461,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[62] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[62]), .Q(UNCONN_OUT[62]), .R(1'b0)); @@ -6292,7 +6469,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[63] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[63]), .Q(UNCONN_OUT[63]), .R(1'b0)); @@ -6300,7 +6477,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[64] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[64]), .Q(UNCONN_OUT[64]), .R(1'b0)); @@ -6308,7 +6485,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[65] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[65]), .Q(UNCONN_OUT[65]), .R(1'b0)); @@ -6316,7 +6493,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[66] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[66]), .Q(UNCONN_OUT[66]), .R(1'b0)); @@ -6324,7 +6501,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[67] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[67]), .Q(UNCONN_OUT[67]), .R(1'b0)); @@ -6332,7 +6509,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[68] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[68]), .Q(UNCONN_OUT[68]), .R(1'b0)); @@ -6340,7 +6517,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[6] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[6]), .Q(UNCONN_OUT[6]), .R(1'b0)); @@ -6348,7 +6525,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[7] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[7]), .Q(UNCONN_OUT[7]), .R(1'b0)); @@ -6356,7 +6533,7 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[8] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[8]), .Q(UNCONN_OUT[8]), .R(1'b0)); @@ -6364,93 +6541,103 @@ module Arty_Z7_20_s00_data_fifo_0_memory__parameterized0 .INIT(1'b0)) \goreg_bm.dout_i_reg[9] (.C(s_aclk), - .CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ), + .CE(\gpregsm1.curr_fwft_state_reg[0] ), .D(doutb[9]), .Q(UNCONN_OUT[9]), .R(1'b0)); endmodule module Arty_Z7_20_s00_data_fifo_0_rd_bin_cntr - (ram_empty_fb_i_reg, - ram_empty_fb_i_reg_0, + (ram_full_comb, + ram_empty_fb_i_reg, Q, + \gpr1.dout_i_reg[1] , ram_full_fb_i_reg, - \gpregsm1.curr_fwft_state_reg[0] , + \grstd1.grst_full.grst_f.rst_d3_reg , + E, ram_full_i_reg, out, - \gcc0.gc0.count_d1_reg[4] , + empty_fwft_i_reg, + \gc0.count_reg[2]_0 , \gcc0.gc0.count_reg[4] , - E, + \gcc0.gc0.count_d1_reg[4] , s_aclk, \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ); + output ram_full_comb; output ram_empty_fb_i_reg; - output ram_empty_fb_i_reg_0; output [4:0]Q; - output ram_full_fb_i_reg; - input \gpregsm1.curr_fwft_state_reg[0] ; - input ram_full_i_reg; + output [4:0]\gpr1.dout_i_reg[1] ; + input ram_full_fb_i_reg; + input \grstd1.grst_full.grst_f.rst_d3_reg ; + input [0:0]E; + input [0:0]ram_full_i_reg; input out; + input empty_fwft_i_reg; + input \gc0.count_reg[2]_0 ; + input [4:0]\gcc0.gc0.count_reg[4] ; input [4:0]\gcc0.gc0.count_d1_reg[4] ; - input [2:0]\gcc0.gc0.count_reg[4] ; - input [0:0]E; input s_aclk; input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ; wire [0:0]E; wire [4:0]Q; + wire empty_fwft_i_reg; + wire \gc0.count_reg[2]_0 ; wire [4:0]\gcc0.gc0.count_d1_reg[4] ; - wire [2:0]\gcc0.gc0.count_reg[4] ; - wire \gpregsm1.curr_fwft_state_reg[0] ; + wire [4:0]\gcc0.gc0.count_reg[4] ; + wire [4:0]\gpr1.dout_i_reg[1] ; + wire \grstd1.grst_full.grst_f.rst_d3_reg ; wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ; wire out; wire [4:0]plusOp; - wire ram_empty_fb_i_i_3_n_0; - wire ram_empty_fb_i_i_6_n_0; - wire ram_empty_fb_i_i_7_n_0; + wire ram_empty_fb_i_i_2__0_n_0; + wire ram_empty_fb_i_i_5_n_0; wire ram_empty_fb_i_reg; - wire ram_empty_fb_i_reg_0; + wire ram_full_comb; + wire ram_full_fb_i_i_2__0_n_0; + wire ram_full_fb_i_i_3_n_0; wire ram_full_fb_i_reg; - wire ram_full_i_reg; - wire [4:0]rd_pntr_plus1; + wire [0:0]ram_full_i_reg; wire s_aclk; LUT1 #( .INIT(2'h1)) \gc0.count[0]_i_1 - (.I0(rd_pntr_plus1[0]), + (.I0(Q[0]), .O(plusOp[0])); - (* SOFT_HLUTNM = "soft_lutpair0" *) + (* SOFT_HLUTNM = "soft_lutpair1" *) LUT2 #( .INIT(4'h6)) \gc0.count[1]_i_1 - (.I0(rd_pntr_plus1[0]), - .I1(rd_pntr_plus1[1]), + (.I0(Q[1]), + .I1(Q[0]), .O(plusOp[1])); + (* SOFT_HLUTNM = "soft_lutpair1" *) LUT3 #( - .INIT(8'h78)) + .INIT(8'h6A)) \gc0.count[2]_i_1 - (.I0(rd_pntr_plus1[1]), - .I1(rd_pntr_plus1[0]), - .I2(rd_pntr_plus1[2]), + (.I0(Q[2]), + .I1(Q[1]), + .I2(Q[0]), .O(plusOp[2])); - (* SOFT_HLUTNM = "soft_lutpair1" *) + (* SOFT_HLUTNM = "soft_lutpair0" *) LUT4 #( .INIT(16'h7F80)) \gc0.count[3]_i_1 - (.I0(rd_pntr_plus1[0]), - .I1(rd_pntr_plus1[1]), - .I2(rd_pntr_plus1[2]), - .I3(rd_pntr_plus1[3]), + (.I0(Q[0]), + .I1(Q[1]), + .I2(Q[2]), + .I3(Q[3]), .O(plusOp[3])); - (* SOFT_HLUTNM = "soft_lutpair1" *) + (* SOFT_HLUTNM = "soft_lutpair0" *) LUT5 #( - .INIT(32'h7FFF8000)) + .INIT(32'h6AAAAAAA)) \gc0.count[4]_i_1 - (.I0(rd_pntr_plus1[2]), - .I1(rd_pntr_plus1[3]), - .I2(rd_pntr_plus1[0]), - .I3(rd_pntr_plus1[1]), - .I4(rd_pntr_plus1[4]), + (.I0(Q[4]), + .I1(Q[0]), + .I2(Q[1]), + .I3(Q[2]), + .I4(Q[3]), .O(plusOp[4])); FDCE #( .INIT(1'b0)) @@ -6458,40 +6645,40 @@ module Arty_Z7_20_s00_data_fifo_0_rd_bin_cntr (.C(s_aclk), .CE(E), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), - .D(rd_pntr_plus1[0]), - .Q(Q[0])); + .D(Q[0]), + .Q(\gpr1.dout_i_reg[1] [0])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[1] (.C(s_aclk), .CE(E), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), - .D(rd_pntr_plus1[1]), - .Q(Q[1])); + .D(Q[1]), + .Q(\gpr1.dout_i_reg[1] [1])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[2] (.C(s_aclk), .CE(E), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), - .D(rd_pntr_plus1[2]), - .Q(Q[2])); + .D(Q[2]), + .Q(\gpr1.dout_i_reg[1] [2])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[3] (.C(s_aclk), .CE(E), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), - .D(rd_pntr_plus1[3]), - .Q(Q[3])); + .D(Q[3]), + .Q(\gpr1.dout_i_reg[1] [3])); FDCE #( .INIT(1'b0)) \gc0.count_d1_reg[4] (.C(s_aclk), .CE(E), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), - .D(rd_pntr_plus1[4]), - .Q(Q[4])); + .D(Q[4]), + .Q(\gpr1.dout_i_reg[1] [4])); FDPE #( .INIT(1'b1)) \gc0.count_reg[0] @@ -6499,7 +6686,7 @@ module Arty_Z7_20_s00_data_fifo_0_rd_bin_cntr .CE(E), .D(plusOp[0]), .PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), - .Q(rd_pntr_plus1[0])); + .Q(Q[0])); FDCE #( .INIT(1'b0)) \gc0.count_reg[1] @@ -6507,7 +6694,7 @@ module Arty_Z7_20_s00_data_fifo_0_rd_bin_cntr .CE(E), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), .D(plusOp[1]), - .Q(rd_pntr_plus1[1])); + .Q(Q[1])); FDCE #( .INIT(1'b0)) \gc0.count_reg[2] @@ -6515,7 +6702,7 @@ module Arty_Z7_20_s00_data_fifo_0_rd_bin_cntr .CE(E), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), .D(plusOp[2]), - .Q(rd_pntr_plus1[2])); + .Q(Q[2])); FDCE #( .INIT(1'b0)) \gc0.count_reg[3] @@ -6523,7 +6710,7 @@ module Arty_Z7_20_s00_data_fifo_0_rd_bin_cntr .CE(E), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), .D(plusOp[3]), - .Q(rd_pntr_plus1[3])); + .Q(Q[3])); FDCE #( .INIT(1'b0)) \gc0.count_reg[4] @@ -6531,254 +6718,264 @@ module Arty_Z7_20_s00_data_fifo_0_rd_bin_cntr .CE(E), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), .D(plusOp[4]), - .Q(rd_pntr_plus1[4])); + .Q(Q[4])); LUT5 #( - .INIT(32'hFF80F080)) + .INIT(32'hD0FFD0D0)) ram_empty_fb_i_i_1 - (.I0(\gpregsm1.curr_fwft_state_reg[0] ), - .I1(ram_empty_fb_i_i_3_n_0), - .I2(ram_full_i_reg), - .I3(out), - .I4(ram_empty_fb_i_reg_0), + (.I0(ram_full_i_reg), + .I1(ram_empty_fb_i_i_2__0_n_0), + .I2(out), + .I3(empty_fwft_i_reg), + .I4(\gc0.count_reg[2]_0 ), .O(ram_empty_fb_i_reg)); - (* SOFT_HLUTNM = "soft_lutpair0" *) LUT5 #( - .INIT(32'h82000082)) - ram_empty_fb_i_i_3 - (.I0(ram_empty_fb_i_i_6_n_0), - .I1(rd_pntr_plus1[0]), + .INIT(32'hFFFF6FF6)) + ram_empty_fb_i_i_2__0 + (.I0(\gcc0.gc0.count_d1_reg[4] [2]), + .I1(\gpr1.dout_i_reg[1] [2]), + .I2(\gcc0.gc0.count_d1_reg[4] [4]), + .I3(\gpr1.dout_i_reg[1] [4]), + .I4(ram_empty_fb_i_i_5_n_0), + .O(ram_empty_fb_i_i_2__0_n_0)); + LUT6 #( + .INIT(64'h6FF6FFFFFFFF6FF6)) + ram_empty_fb_i_i_5 + (.I0(\gpr1.dout_i_reg[1] [3]), + .I1(\gcc0.gc0.count_d1_reg[4] [3]), .I2(\gcc0.gc0.count_d1_reg[4] [0]), - .I3(rd_pntr_plus1[1]), + .I3(\gpr1.dout_i_reg[1] [0]), .I4(\gcc0.gc0.count_d1_reg[4] [1]), - .O(ram_empty_fb_i_i_3_n_0)); + .I5(\gpr1.dout_i_reg[1] [1]), + .O(ram_empty_fb_i_i_5_n_0)); LUT5 #( - .INIT(32'hBEFFFFBE)) - ram_empty_fb_i_i_5 - (.I0(ram_empty_fb_i_i_7_n_0), - .I1(Q[2]), - .I2(\gcc0.gc0.count_d1_reg[4] [2]), - .I3(Q[4]), - .I4(\gcc0.gc0.count_d1_reg[4] [4]), - .O(ram_empty_fb_i_reg_0)); + .INIT(32'h00C055F5)) + ram_full_fb_i_i_1 + (.I0(ram_full_fb_i_i_2__0_n_0), + .I1(ram_empty_fb_i_i_2__0_n_0), + .I2(ram_full_fb_i_reg), + .I3(\grstd1.grst_full.grst_f.rst_d3_reg ), + .I4(E), + .O(ram_full_comb)); LUT6 #( - .INIT(64'h9009000000009009)) - ram_empty_fb_i_i_6 - (.I0(rd_pntr_plus1[2]), - .I1(\gcc0.gc0.count_d1_reg[4] [2]), - .I2(rd_pntr_plus1[4]), - .I3(\gcc0.gc0.count_d1_reg[4] [4]), - .I4(\gcc0.gc0.count_d1_reg[4] [3]), - .I5(rd_pntr_plus1[3]), - .O(ram_empty_fb_i_i_6_n_0)); + .INIT(64'hBEFFFFBEFFFFFFFF)) + ram_full_fb_i_i_2__0 + (.I0(ram_full_fb_i_i_3_n_0), + .I1(\gpr1.dout_i_reg[1] [0]), + .I2(\gcc0.gc0.count_reg[4] [0]), + .I3(\gpr1.dout_i_reg[1] [1]), + .I4(\gcc0.gc0.count_reg[4] [1]), + .I5(ram_full_i_reg), + .O(ram_full_fb_i_i_2__0_n_0)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) - ram_empty_fb_i_i_7 - (.I0(Q[0]), - .I1(\gcc0.gc0.count_d1_reg[4] [0]), - .I2(Q[1]), - .I3(\gcc0.gc0.count_d1_reg[4] [1]), - .I4(\gcc0.gc0.count_d1_reg[4] [3]), - .I5(Q[3]), - .O(ram_empty_fb_i_i_7_n_0)); - LUT6 #( - .INIT(64'h9009000000009009)) - ram_full_fb_i_i_4 - (.I0(Q[2]), - .I1(\gcc0.gc0.count_reg[4] [0]), - .I2(Q[4]), - .I3(\gcc0.gc0.count_reg[4] [2]), - .I4(\gcc0.gc0.count_reg[4] [1]), - .I5(Q[3]), - .O(ram_full_fb_i_reg)); + ram_full_fb_i_i_3 + (.I0(\gpr1.dout_i_reg[1] [3]), + .I1(\gcc0.gc0.count_reg[4] [3]), + .I2(\gcc0.gc0.count_reg[4] [2]), + .I3(\gpr1.dout_i_reg[1] [2]), + .I4(\gcc0.gc0.count_reg[4] [4]), + .I5(\gpr1.dout_i_reg[1] [4]), + .O(ram_full_fb_i_i_3_n_0)); endmodule (* ORIG_REF_NAME = "rd_bin_cntr" *) module Arty_Z7_20_s00_data_fifo_0_rd_bin_cntr__parameterized0 - (ram_full_i_reg, + (ram_empty_i_reg, Q, - ram_empty_i_reg, - ram_full_i_reg_0, + v1_reg, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram , + v1_reg_0, ram_empty_i_reg_0, - \gc0.count_d1_reg[7]_0 , + ram_empty_i_reg_1, + ram_empty_i_reg_2, + ram_empty_i_reg_3, \gcc0.gc0.count_d1_reg[8] , - \gcc0.gc0.count_reg[8] , + \gcc0.gc0.count_reg[7] , \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg , E, s_aclk); - output ram_full_i_reg; - output [8:0]Q; output ram_empty_i_reg; - output ram_full_i_reg_0; + output [7:0]Q; + output [3:0]v1_reg; + output [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; + output [3:0]v1_reg_0; output ram_empty_i_reg_0; - output [7:0]\gc0.count_d1_reg[7]_0 ; - input [0:0]\gcc0.gc0.count_d1_reg[8] ; - input [0:0]\gcc0.gc0.count_reg[8] ; + output ram_empty_i_reg_1; + output ram_empty_i_reg_2; + output ram_empty_i_reg_3; + input [8:0]\gcc0.gc0.count_d1_reg[8] ; + input [7:0]\gcc0.gc0.count_reg[7] ; input \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg ; input [0:0]E; input s_aclk; + wire [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; wire [0:0]E; - wire [8:0]Q; + wire [7:0]Q; wire \gc0.count[8]_i_2_n_0 ; - wire [7:0]\gc0.count_d1_reg[7]_0 ; - wire [0:0]\gcc0.gc0.count_d1_reg[8] ; - wire [0:0]\gcc0.gc0.count_reg[8] ; + wire [8:0]\gcc0.gc0.count_d1_reg[8] ; + wire [7:0]\gcc0.gc0.count_reg[7] ; wire \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg ; wire [8:0]plusOp__1; wire ram_empty_i_reg; wire ram_empty_i_reg_0; - wire ram_full_i_reg; - wire ram_full_i_reg_0; + wire ram_empty_i_reg_1; + wire ram_empty_i_reg_2; + wire ram_empty_i_reg_3; wire [8:8]rd_pntr_plus1; wire s_aclk; + wire [3:0]v1_reg; + wire [3:0]v1_reg_0; LUT1 #( .INIT(2'h1)) \gc0.count[0]_i_1__0 - (.I0(\gc0.count_d1_reg[7]_0 [0]), + (.I0(Q[0]), .O(plusOp__1[0])); LUT2 #( .INIT(4'h6)) \gc0.count[1]_i_1__0 - (.I0(\gc0.count_d1_reg[7]_0 [0]), - .I1(\gc0.count_d1_reg[7]_0 [1]), + (.I0(Q[1]), + .I1(Q[0]), .O(plusOp__1[1])); - (* SOFT_HLUTNM = "soft_lutpair11" *) + (* SOFT_HLUTNM = "soft_lutpair12" *) LUT3 #( - .INIT(8'h78)) + .INIT(8'h6A)) \gc0.count[2]_i_1__0 - (.I0(\gc0.count_d1_reg[7]_0 [1]), - .I1(\gc0.count_d1_reg[7]_0 [0]), - .I2(\gc0.count_d1_reg[7]_0 [2]), + (.I0(Q[2]), + .I1(Q[1]), + .I2(Q[0]), .O(plusOp__1[2])); - (* SOFT_HLUTNM = "soft_lutpair11" *) + (* SOFT_HLUTNM = "soft_lutpair12" *) LUT4 #( .INIT(16'h7F80)) \gc0.count[3]_i_1__0 - (.I0(\gc0.count_d1_reg[7]_0 [2]), - .I1(\gc0.count_d1_reg[7]_0 [0]), - .I2(\gc0.count_d1_reg[7]_0 [1]), - .I3(\gc0.count_d1_reg[7]_0 [3]), + (.I0(Q[0]), + .I1(Q[1]), + .I2(Q[2]), + .I3(Q[3]), .O(plusOp__1[3])); - (* SOFT_HLUTNM = "soft_lutpair10" *) + (* SOFT_HLUTNM = "soft_lutpair11" *) LUT5 #( - .INIT(32'h7FFF8000)) + .INIT(32'h6AAAAAAA)) \gc0.count[4]_i_1__0 - (.I0(\gc0.count_d1_reg[7]_0 [3]), - .I1(\gc0.count_d1_reg[7]_0 [1]), - .I2(\gc0.count_d1_reg[7]_0 [0]), - .I3(\gc0.count_d1_reg[7]_0 [2]), - .I4(\gc0.count_d1_reg[7]_0 [4]), + (.I0(Q[4]), + .I1(Q[0]), + .I2(Q[1]), + .I3(Q[2]), + .I4(Q[3]), .O(plusOp__1[4])); LUT6 #( - .INIT(64'h7FFFFFFF80000000)) + .INIT(64'h6AAAAAAAAAAAAAAA)) \gc0.count[5]_i_1 - (.I0(\gc0.count_d1_reg[7]_0 [4]), - .I1(\gc0.count_d1_reg[7]_0 [2]), - .I2(\gc0.count_d1_reg[7]_0 [0]), - .I3(\gc0.count_d1_reg[7]_0 [1]), - .I4(\gc0.count_d1_reg[7]_0 [3]), - .I5(\gc0.count_d1_reg[7]_0 [5]), + (.I0(Q[5]), + .I1(Q[3]), + .I2(Q[2]), + .I3(Q[1]), + .I4(Q[0]), + .I5(Q[4]), .O(plusOp__1[5])); - LUT3 #( - .INIT(8'h78)) + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT4 #( + .INIT(16'h6AAA)) \gc0.count[6]_i_1 - (.I0(\gc0.count_d1_reg[7]_0 [5]), - .I1(\gc0.count[8]_i_2_n_0 ), - .I2(\gc0.count_d1_reg[7]_0 [6]), + (.I0(Q[6]), + .I1(Q[4]), + .I2(\gc0.count[8]_i_2_n_0 ), + .I3(Q[5]), .O(plusOp__1[6])); - (* SOFT_HLUTNM = "soft_lutpair9" *) - LUT4 #( - .INIT(16'h7F80)) + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT5 #( + .INIT(32'h6AAAAAAA)) \gc0.count[7]_i_1 - (.I0(\gc0.count[8]_i_2_n_0 ), - .I1(\gc0.count_d1_reg[7]_0 [5]), - .I2(\gc0.count_d1_reg[7]_0 [6]), - .I3(\gc0.count_d1_reg[7]_0 [7]), + (.I0(Q[7]), + .I1(Q[5]), + .I2(\gc0.count[8]_i_2_n_0 ), + .I3(Q[4]), + .I4(Q[6]), .O(plusOp__1[7])); - (* SOFT_HLUTNM = "soft_lutpair9" *) - LUT5 #( - .INIT(32'h7FFF8000)) + LUT6 #( + .INIT(64'h6AAAAAAAAAAAAAAA)) \gc0.count[8]_i_1 - (.I0(\gc0.count[8]_i_2_n_0 ), - .I1(\gc0.count_d1_reg[7]_0 [7]), - .I2(\gc0.count_d1_reg[7]_0 [6]), - .I3(\gc0.count_d1_reg[7]_0 [5]), - .I4(rd_pntr_plus1), + (.I0(rd_pntr_plus1), + .I1(Q[6]), + .I2(Q[4]), + .I3(\gc0.count[8]_i_2_n_0 ), + .I4(Q[5]), + .I5(Q[7]), .O(plusOp__1[8])); - (* SOFT_HLUTNM = "soft_lutpair10" *) - LUT5 #( - .INIT(32'h80000000)) + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT4 #( + .INIT(16'h8000)) \gc0.count[8]_i_2 - (.I0(\gc0.count_d1_reg[7]_0 [3]), - .I1(\gc0.count_d1_reg[7]_0 [1]), - .I2(\gc0.count_d1_reg[7]_0 [0]), - .I3(\gc0.count_d1_reg[7]_0 [2]), - .I4(\gc0.count_d1_reg[7]_0 [4]), + (.I0(Q[3]), + .I1(Q[2]), + .I2(Q[1]), + .I3(Q[0]), .O(\gc0.count[8]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gc0.count_d1_reg[0] (.C(s_aclk), .CE(E), - .D(\gc0.count_d1_reg[7]_0 [0]), - .Q(Q[0]), + .D(Q[0]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( .INIT(1'b0)) \gc0.count_d1_reg[1] (.C(s_aclk), .CE(E), - .D(\gc0.count_d1_reg[7]_0 [1]), - .Q(Q[1]), + .D(Q[1]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( .INIT(1'b0)) \gc0.count_d1_reg[2] (.C(s_aclk), .CE(E), - .D(\gc0.count_d1_reg[7]_0 [2]), - .Q(Q[2]), + .D(Q[2]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [2]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( .INIT(1'b0)) \gc0.count_d1_reg[3] (.C(s_aclk), .CE(E), - .D(\gc0.count_d1_reg[7]_0 [3]), - .Q(Q[3]), + .D(Q[3]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [3]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( .INIT(1'b0)) \gc0.count_d1_reg[4] (.C(s_aclk), .CE(E), - .D(\gc0.count_d1_reg[7]_0 [4]), - .Q(Q[4]), + .D(Q[4]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [4]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( .INIT(1'b0)) \gc0.count_d1_reg[5] (.C(s_aclk), .CE(E), - .D(\gc0.count_d1_reg[7]_0 [5]), - .Q(Q[5]), + .D(Q[5]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [5]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( .INIT(1'b0)) \gc0.count_d1_reg[6] (.C(s_aclk), .CE(E), - .D(\gc0.count_d1_reg[7]_0 [6]), - .Q(Q[6]), + .D(Q[6]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [6]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( .INIT(1'b0)) \gc0.count_d1_reg[7] (.C(s_aclk), .CE(E), - .D(\gc0.count_d1_reg[7]_0 [7]), - .Q(Q[7]), + .D(Q[7]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [7]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( .INIT(1'b0)) @@ -6786,7 +6983,7 @@ module Arty_Z7_20_s00_data_fifo_0_rd_bin_cntr__parameterized0 (.C(s_aclk), .CE(E), .D(rd_pntr_plus1), - .Q(Q[8]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [8]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDSE #( .INIT(1'b1)) @@ -6794,7 +6991,7 @@ module Arty_Z7_20_s00_data_fifo_0_rd_bin_cntr__parameterized0 (.C(s_aclk), .CE(E), .D(plusOp__1[0]), - .Q(\gc0.count_d1_reg[7]_0 [0]), + .Q(Q[0]), .S(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( .INIT(1'b0)) @@ -6802,7 +6999,7 @@ module Arty_Z7_20_s00_data_fifo_0_rd_bin_cntr__parameterized0 (.C(s_aclk), .CE(E), .D(plusOp__1[1]), - .Q(\gc0.count_d1_reg[7]_0 [1]), + .Q(Q[1]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( .INIT(1'b0)) @@ -6810,7 +7007,7 @@ module Arty_Z7_20_s00_data_fifo_0_rd_bin_cntr__parameterized0 (.C(s_aclk), .CE(E), .D(plusOp__1[2]), - .Q(\gc0.count_d1_reg[7]_0 [2]), + .Q(Q[2]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( .INIT(1'b0)) @@ -6818,7 +7015,7 @@ module Arty_Z7_20_s00_data_fifo_0_rd_bin_cntr__parameterized0 (.C(s_aclk), .CE(E), .D(plusOp__1[3]), - .Q(\gc0.count_d1_reg[7]_0 [3]), + .Q(Q[3]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( .INIT(1'b0)) @@ -6826,7 +7023,7 @@ module Arty_Z7_20_s00_data_fifo_0_rd_bin_cntr__parameterized0 (.C(s_aclk), .CE(E), .D(plusOp__1[4]), - .Q(\gc0.count_d1_reg[7]_0 [4]), + .Q(Q[4]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( .INIT(1'b0)) @@ -6834,7 +7031,7 @@ module Arty_Z7_20_s00_data_fifo_0_rd_bin_cntr__parameterized0 (.C(s_aclk), .CE(E), .D(plusOp__1[5]), - .Q(\gc0.count_d1_reg[7]_0 [5]), + .Q(Q[5]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( .INIT(1'b0)) @@ -6842,7 +7039,7 @@ module Arty_Z7_20_s00_data_fifo_0_rd_bin_cntr__parameterized0 (.C(s_aclk), .CE(E), .D(plusOp__1[6]), - .Q(\gc0.count_d1_reg[7]_0 [6]), + .Q(Q[6]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( .INIT(1'b0)) @@ -6850,7 +7047,7 @@ module Arty_Z7_20_s00_data_fifo_0_rd_bin_cntr__parameterized0 (.C(s_aclk), .CE(E), .D(plusOp__1[7]), - .Q(\gc0.count_d1_reg[7]_0 [7]), + .Q(Q[7]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( .INIT(1'b0)) @@ -6860,75 +7057,151 @@ module Arty_Z7_20_s00_data_fifo_0_rd_bin_cntr__parameterized0 .D(plusOp__1[8]), .Q(rd_pntr_plus1), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[0].gm1.m1_i_1 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]), + .I1(\gcc0.gc0.count_d1_reg[8] [0]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]), + .I3(\gcc0.gc0.count_d1_reg[8] [1]), + .O(v1_reg[0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[0].gm1.m1_i_1__1 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]), + .I1(\gcc0.gc0.count_reg[7] [0]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]), + .I3(\gcc0.gc0.count_reg[7] [1]), + .O(v1_reg_0[0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[0].gm1.m1_i_1__2 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [0]), + .I1(\gcc0.gc0.count_d1_reg[8] [0]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [1]), + .I3(\gcc0.gc0.count_d1_reg[8] [1]), + .O(ram_empty_i_reg_0)); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[1].gms.ms_i_1 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [2]), + .I1(\gcc0.gc0.count_d1_reg[8] [2]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [3]), + .I3(\gcc0.gc0.count_d1_reg[8] [3]), + .O(v1_reg[1])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[1].gms.ms_i_1__1 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [2]), + .I1(\gcc0.gc0.count_reg[7] [2]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [3]), + .I3(\gcc0.gc0.count_reg[7] [3]), + .O(v1_reg_0[1])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[1].gms.ms_i_1__2 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [2]), + .I1(\gcc0.gc0.count_d1_reg[8] [2]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [3]), + .I3(\gcc0.gc0.count_d1_reg[8] [3]), + .O(ram_empty_i_reg_1)); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[2].gms.ms_i_1 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [5]), + .I1(\gcc0.gc0.count_d1_reg[8] [5]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [4]), + .I3(\gcc0.gc0.count_d1_reg[8] [4]), + .O(v1_reg[2])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[2].gms.ms_i_1__1 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [5]), + .I1(\gcc0.gc0.count_reg[7] [5]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [4]), + .I3(\gcc0.gc0.count_reg[7] [4]), + .O(v1_reg_0[2])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[2].gms.ms_i_1__2 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [5]), + .I1(\gcc0.gc0.count_d1_reg[8] [5]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [4]), + .I3(\gcc0.gc0.count_d1_reg[8] [4]), + .O(ram_empty_i_reg_2)); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[3].gms.ms_i_1 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [7]), + .I1(\gcc0.gc0.count_d1_reg[8] [7]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [6]), + .I3(\gcc0.gc0.count_d1_reg[8] [6]), + .O(v1_reg[3])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[3].gms.ms_i_1__1 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [7]), + .I1(\gcc0.gc0.count_reg[7] [7]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [6]), + .I3(\gcc0.gc0.count_reg[7] [6]), + .O(v1_reg_0[3])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[3].gms.ms_i_1__2 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [7]), + .I1(\gcc0.gc0.count_d1_reg[8] [7]), + .I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram [6]), + .I3(\gcc0.gc0.count_d1_reg[8] [6]), + .O(ram_empty_i_reg_3)); LUT2 #( .INIT(4'h9)) \gmux.gm[4].gms.ms_i_1 - (.I0(Q[8]), - .I1(\gcc0.gc0.count_d1_reg[8] ), - .O(ram_full_i_reg)); - LUT2 #( - .INIT(4'h9)) - \gmux.gm[4].gms.ms_i_1__0 (.I0(rd_pntr_plus1), - .I1(\gcc0.gc0.count_d1_reg[8] ), + .I1(\gcc0.gc0.count_d1_reg[8] [8]), .O(ram_empty_i_reg)); - LUT2 #( - .INIT(4'h9)) - \gmux.gm[4].gms.ms_i_1__1 - (.I0(Q[8]), - .I1(\gcc0.gc0.count_reg[8] ), - .O(ram_full_i_reg_0)); - LUT2 #( - .INIT(4'h9)) - \gmux.gm[4].gms.ms_i_1__2 - (.I0(Q[8]), - .I1(\gcc0.gc0.count_d1_reg[8] ), - .O(ram_empty_i_reg_0)); endmodule module Arty_Z7_20_s00_data_fifo_0_rd_fwft (out, - \gfwd_rev_pipeline1.s_ready_i_reg , - \gfwd_rev_pipeline1.s_ready_i_reg_0 , - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0] , E, - \gc0.count_reg[4] , - ram_full_fb_i_reg, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0] , + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0]_0 , ram_empty_fb_i_reg, - \goreg_dm.dout_i_reg[59] , - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] , - \gfwd_rev_pipeline1.s_ready_i_reg_1 , - \gfwd_rev_pipeline1.s_ready_i_reg_2 , + \goreg_dm.dout_i_reg[62] , + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3] , + \gfwd_rev_pipeline1.s_ready_i_reg , + \gfwd_rev_pipeline1.s_ready_i_reg_0 , + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0 , s_aclk, \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] , - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] , + ram_empty_fb_i_reg_0, CO, arready_pkt, - s_axi_rready, empty_fwft_fb_o_i_reg_0, - \gfwd_rev_pipeline1.s_ready_i_reg_3 , - ram_empty_fb_i_reg_0); + s_axi_rready, + \gfwd_rev_pipeline1.s_ready_i_reg_1 , + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] , + \goreg_dm.dout_i_reg[22] ); output out; - output [1:0]\gfwd_rev_pipeline1.s_ready_i_reg ; - output [0:0]\gfwd_rev_pipeline1.s_ready_i_reg_0 ; - output \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0] ; output [0:0]E; - output [0:0]\gc0.count_reg[4] ; - output ram_full_fb_i_reg; + output \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0] ; + output [0:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0]_0 ; output ram_empty_fb_i_reg; - output [0:0]\goreg_dm.dout_i_reg[59] ; - output \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] ; - output [1:0]\gfwd_rev_pipeline1.s_ready_i_reg_1 ; - output [0:0]\gfwd_rev_pipeline1.s_ready_i_reg_2 ; + output [0:0]\goreg_dm.dout_i_reg[62] ; + output \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3] ; + output [0:0]\gfwd_rev_pipeline1.s_ready_i_reg ; + output [0:0]\gfwd_rev_pipeline1.s_ready_i_reg_0 ; + output [0:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0 ; input s_aclk; input [1:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ; - input [5:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ; + input ram_empty_fb_i_reg_0; input [0:0]CO; input arready_pkt; - input s_axi_rready; input empty_fwft_fb_o_i_reg_0; - input \gfwd_rev_pipeline1.s_ready_i_reg_3 ; - input ram_empty_fb_i_reg_0; + input s_axi_rready; + input \gfwd_rev_pipeline1.s_ready_i_reg_1 ; + input [1:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ; + input [0:0]\goreg_dm.dout_i_reg[22] ; wire [0:0]CO; wire [0:0]E; @@ -6944,33 +7217,52 @@ module Arty_Z7_20_s00_data_fifo_0_rd_fwft (* DONT_TOUCH *) wire empty_fwft_i; wire empty_fwft_i0; wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0] ; - wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] ; - wire [5:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ; - wire [0:0]\gc0.count_reg[4] ; - wire [1:0]\gfwd_rev_pipeline1.s_ready_i_reg ; + wire [0:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0]_0 ; + wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3] ; + wire [0:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0 ; + wire [1:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ; + wire [0:0]\gfwd_rev_pipeline1.s_ready_i_reg ; wire [0:0]\gfwd_rev_pipeline1.s_ready_i_reg_0 ; - wire [1:0]\gfwd_rev_pipeline1.s_ready_i_reg_1 ; - wire [0:0]\gfwd_rev_pipeline1.s_ready_i_reg_2 ; - wire \gfwd_rev_pipeline1.s_ready_i_reg_3 ; - wire [0:0]\goreg_dm.dout_i_reg[59] ; - wire [1:0]next_fwft_state; + wire \gfwd_rev_pipeline1.s_ready_i_reg_1 ; + wire [0:0]\goreg_dm.dout_i_reg[22] ; + wire [0:0]\goreg_dm.dout_i_reg[62] ; + wire \gpregsm1.curr_fwft_state[1]_i_1__0_n_0 ; + wire [0:0]next_fwft_state; wire [1:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ; wire ram_empty_fb_i_reg; wire ram_empty_fb_i_reg_0; - wire ram_full_fb_i_reg; wire s_aclk; wire s_axi_rready; (* DONT_TOUCH *) wire user_valid; assign out = empty_fwft_i; LUT5 #( - .INIT(32'hCE8CCC44)) + .INIT(32'h40004040)) + _carry_i_1 + (.I0(empty_fwft_i), + .I1(arready_pkt), + .I2(CO), + .I3(empty_fwft_fb_o_i_reg_0), + .I4(s_axi_rready), + .O(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3] )); + LUT6 #( + .INIT(64'hBFFFBFBFFFFFFFFF)) + _carry_i_5 + (.I0(empty_fwft_i), + .I1(arready_pkt), + .I2(CO), + .I3(empty_fwft_fb_o_i_reg_0), + .I4(s_axi_rready), + .I5(\goreg_dm.dout_i_reg[22] ), + .O(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0 )); + LUT5 #( + .INIT(32'hEC8CC88C)) aempty_fwft_fb_i_i_1 - (.I0(curr_fwft_state[1]), + (.I0(ram_empty_fb_i_reg_0), .I1(aempty_fwft_fb_i), - .I2(\gfwd_rev_pipeline1.s_ready_i_reg_3 ), - .I3(ram_empty_fb_i_reg_0), - .I4(curr_fwft_state[0]), + .I2(curr_fwft_state[1]), + .I3(curr_fwft_state[0]), + .I4(\gfwd_rev_pipeline1.s_ready_i_reg_1 ), .O(aempty_fwft_i0)); (* DONT_TOUCH *) (* KEEP = "yes" *) @@ -6997,48 +7289,24 @@ module Arty_Z7_20_s00_data_fifo_0_rd_fwft LUT2 #( .INIT(4'hE)) arvalid_en0_carry__0_i_1 - (.I0(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] [5]), - .I1(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] [4]), - .O(\gfwd_rev_pipeline1.s_ready_i_reg_2 )); - LUT2 #( - .INIT(4'h1)) - arvalid_en0_carry__0_i_2 - (.I0(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] [4]), - .I1(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] [5]), - .O(\gfwd_rev_pipeline1.s_ready_i_reg_0 )); - LUT2 #( - .INIT(4'hE)) - arvalid_en0_carry_i_1 - (.I0(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] [2]), - .I1(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] [3]), - .O(\gfwd_rev_pipeline1.s_ready_i_reg_1 [1])); - LUT2 #( - .INIT(4'hE)) - arvalid_en0_carry_i_2 (.I0(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] [0]), .I1(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] [1]), - .O(\gfwd_rev_pipeline1.s_ready_i_reg_1 [0])); - LUT2 #( - .INIT(4'h1)) - arvalid_en0_carry_i_5 - (.I0(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] [3]), - .I1(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] [2]), - .O(\gfwd_rev_pipeline1.s_ready_i_reg [1])); + .O(\gfwd_rev_pipeline1.s_ready_i_reg )); LUT2 #( .INIT(4'h1)) - arvalid_en0_carry_i_6 + arvalid_en0_carry__0_i_2 (.I0(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] [1]), .I1(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] [0]), - .O(\gfwd_rev_pipeline1.s_ready_i_reg [0])); + .O(\gfwd_rev_pipeline1.s_ready_i_reg_0 )); LUT6 #( - .INIT(64'hAAAA0000AAEAAAAA)) + .INIT(64'hFFFF00FF00080000)) empty_fwft_fb_i_i_1 - (.I0(empty_fwft_fb_i), + (.I0(CO), .I1(arready_pkt), - .I2(CO), - .I3(empty_fwft_i), + .I2(empty_fwft_i), + .I3(curr_fwft_state[1]), .I4(curr_fwft_state[0]), - .I5(curr_fwft_state[1]), + .I5(empty_fwft_fb_i), .O(empty_fwft_i0)); (* DONT_TOUCH *) (* KEEP = "yes" *) @@ -7052,14 +7320,14 @@ module Arty_Z7_20_s00_data_fifo_0_rd_fwft .PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [1]), .Q(empty_fwft_fb_i)); LUT6 #( - .INIT(64'hAAAA0000AAEAAAAA)) + .INIT(64'hFFFF00FF00080000)) empty_fwft_fb_o_i_i_1 - (.I0(empty_fwft_fb_o_i), + (.I0(CO), .I1(arready_pkt), - .I2(CO), - .I3(empty_fwft_i), + .I2(empty_fwft_i), + .I3(curr_fwft_state[1]), .I4(curr_fwft_state[0]), - .I5(curr_fwft_state[1]), + .I5(empty_fwft_fb_o_i), .O(empty_fwft_fb_o_i0)); (* DONT_TOUCH *) (* KEEP = "yes" *) @@ -7084,62 +7352,62 @@ module Arty_Z7_20_s00_data_fifo_0_rd_fwft .PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [1]), .Q(empty_fwft_i)); LUT5 #( - .INIT(32'h4040FF40)) + .INIT(32'h40FF4040)) \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[9]_i_1 (.I0(empty_fwft_i), - .I1(CO), - .I2(arready_pkt), - .I3(s_axi_rready), - .I4(empty_fwft_fb_o_i_reg_0), - .O(E)); + .I1(arready_pkt), + .I2(CO), + .I3(empty_fwft_fb_o_i_reg_0), + .I4(s_axi_rready), + .O(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0]_0 )); LUT5 #( - .INIT(32'hFFFFBFFF)) - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[9]_i_3 + .INIT(32'h00400000)) + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[9]_i_4 (.I0(empty_fwft_i), - .I1(CO), - .I2(arready_pkt), - .I3(s_axi_rready), - .I4(empty_fwft_fb_o_i_reg_0), + .I1(arready_pkt), + .I2(CO), + .I3(empty_fwft_fb_o_i_reg_0), + .I4(s_axi_rready), .O(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0] )); LUT6 #( - .INIT(64'h0000000055D5FFFF)) + .INIT(64'h1515151555151515)) \gc0.count_d1[4]_i_1 + (.I0(ram_empty_fb_i_reg_0), + .I1(curr_fwft_state[0]), + .I2(curr_fwft_state[1]), + .I3(CO), + .I4(arready_pkt), + .I5(empty_fwft_i), + .O(E)); + LUT6 #( + .INIT(64'h0000000055D50000)) + \goreg_dm.dout_i[62]_i_1 (.I0(curr_fwft_state[0]), - .I1(arready_pkt), - .I2(CO), + .I1(CO), + .I2(arready_pkt), .I3(empty_fwft_i), .I4(curr_fwft_state[1]), - .I5(ram_empty_fb_i_reg_0), - .O(\gc0.count_reg[4] )); - LUT6 #( - .INIT(64'h0404040444040404)) - \goreg_dm.dout_i[59]_i_1 - (.I0(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [0]), - .I1(curr_fwft_state[1]), - .I2(curr_fwft_state[0]), - .I3(arready_pkt), - .I4(CO), - .I5(empty_fwft_i), - .O(\goreg_dm.dout_i_reg[59] )); + .I5(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [0]), + .O(\goreg_dm.dout_i_reg[62] )); LUT5 #( .INIT(32'hEEEEAEEE)) \gpregsm1.curr_fwft_state[0]_i_1 (.I0(curr_fwft_state[1]), .I1(curr_fwft_state[0]), - .I2(arready_pkt), - .I3(CO), + .I2(CO), + .I3(arready_pkt), .I4(empty_fwft_i), - .O(next_fwft_state[0])); + .O(next_fwft_state)); LUT6 #( - .INIT(64'h8AAA0000FFFFFFFF)) - \gpregsm1.curr_fwft_state[1]_i_1 - (.I0(curr_fwft_state[1]), - .I1(empty_fwft_i), + .INIT(64'h88880888FFFFFFFF)) + \gpregsm1.curr_fwft_state[1]_i_1__0 + (.I0(curr_fwft_state[0]), + .I1(curr_fwft_state[1]), .I2(CO), .I3(arready_pkt), - .I4(curr_fwft_state[0]), + .I4(empty_fwft_i), .I5(ram_empty_fb_i_reg_0), - .O(next_fwft_state[1])); + .O(\gpregsm1.curr_fwft_state[1]_i_1__0_n_0 )); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) @@ -7149,7 +7417,7 @@ module Arty_Z7_20_s00_data_fifo_0_rd_fwft (.C(s_aclk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [1]), - .D(next_fwft_state[0]), + .D(next_fwft_state), .Q(curr_fwft_state[0])); (* DONT_TOUCH *) (* KEEP = "yes" *) @@ -7160,7 +7428,7 @@ module Arty_Z7_20_s00_data_fifo_0_rd_fwft (.C(s_aclk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [1]), - .D(next_fwft_state[1]), + .D(\gpregsm1.curr_fwft_state[1]_i_1__0_n_0 ), .Q(curr_fwft_state[1])); (* DONT_TOUCH *) (* KEEP = "yes" *) @@ -7171,80 +7439,60 @@ module Arty_Z7_20_s00_data_fifo_0_rd_fwft (.C(s_aclk), .CE(1'b1), .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [1]), - .D(next_fwft_state[0]), + .D(next_fwft_state), .Q(user_valid)); LUT5 #( - .INIT(32'hBFBFFFBF)) - i__carry__0_i_1 + .INIT(32'hBF000000)) + ram_empty_fb_i_i_3 (.I0(empty_fwft_i), - .I1(CO), - .I2(arready_pkt), - .I3(s_axi_rready), - .I4(empty_fwft_fb_o_i_reg_0), - .O(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] )); - LUT5 #( - .INIT(32'h55D5FFFF)) - ram_empty_fb_i_i_2 - (.I0(curr_fwft_state[0]), .I1(arready_pkt), .I2(CO), - .I3(empty_fwft_i), - .I4(curr_fwft_state[1]), + .I3(curr_fwft_state[1]), + .I4(curr_fwft_state[0]), .O(ram_empty_fb_i_reg)); - LUT6 #( - .INIT(64'hEAEEEEEEAAAAAAAA)) - ram_full_fb_i_i_3 - (.I0(ram_empty_fb_i_reg_0), - .I1(curr_fwft_state[1]), - .I2(empty_fwft_i), - .I3(CO), - .I4(arready_pkt), - .I5(curr_fwft_state[0]), - .O(ram_full_fb_i_reg)); endmodule (* ORIG_REF_NAME = "rd_fwft" *) module Arty_Z7_20_s00_data_fifo_0_rd_fwft__parameterized0 (out, fwft_rst_done_q, - S, E, ram_full_i_reg, ram_empty_i_reg, \goreg_bm.dout_i_reg[68] , + S, s_axi_rvalid, \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg , s_aclk, \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] , SR, - Q, s_axi_rready, - arready_pkt, + ram_empty_fb_i_reg, CO, + arready_pkt, empty_fwft_i_reg_0, - ram_empty_fb_i_reg); + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ); output out; output fwft_rst_done_q; - output [0:0]S; output [0:0]E; output ram_full_i_reg; output ram_empty_i_reg; output [0:0]\goreg_bm.dout_i_reg[68] ; + output [0:0]S; output s_axi_rvalid; input \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg ; input s_aclk; input [1:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ; input [0:0]SR; - input [0:0]Q; input s_axi_rready; - input arready_pkt; + input ram_empty_fb_i_reg; input [0:0]CO; + input arready_pkt; input empty_fwft_i_reg_0; - input ram_empty_fb_i_reg; + input [0:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ; wire [0:0]CO; wire [0:0]E; - wire [0:0]Q; wire [0:0]S; wire [0:0]SR; (* DONT_TOUCH *) wire aempty_fwft_fb_i; @@ -7260,6 +7508,7 @@ module Arty_Z7_20_s00_data_fifo_0_rd_fwft__parameterized0 wire empty_fwft_i_reg_0; wire fwft_rst_done; wire fwft_rst_done_q; + wire [0:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ; wire \gfwft_rst_done.fwft_rst_done_i_1_n_0 ; wire [0:0]\goreg_bm.dout_i_reg[68] ; wire [1:0]next_fwft_state; @@ -7276,23 +7525,33 @@ module Arty_Z7_20_s00_data_fifo_0_rd_fwft__parameterized0 assign out = empty_fwft_fb_o_i; LUT5 #( - .INIT(32'h000075FF)) + .INIT(32'h00007F77)) \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1 - (.I0(curr_fwft_state[0]), - .I1(empty_fwft_fb_o_i), - .I2(s_axi_rready), - .I3(curr_fwft_state[1]), + (.I0(curr_fwft_state[1]), + .I1(curr_fwft_state[0]), + .I2(empty_fwft_fb_o_i), + .I3(s_axi_rready), .I4(ram_empty_fb_i_reg), .O(E)); LUT6 #( - .INIT(64'hF0F0F8F09090B090)) + .INIT(64'hFFFF2FFF0000D000)) + _carry__1_i_1 + (.I0(s_axi_rready), + .I1(empty_fwft_fb_o_i), + .I2(CO), + .I3(arready_pkt), + .I4(empty_fwft_i_reg_0), + .I5(\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ), + .O(S)); + LUT6 #( + .INIT(64'hA88AA88AEA8AA88A)) aempty_fwft_fb_i_i_1__0 - (.I0(curr_fwft_state[0]), - .I1(curr_fwft_state[1]), - .I2(aempty_fwft_fb_i), - .I3(s_axi_rready), - .I4(empty_fwft_fb_o_i), - .I5(ram_empty_fb_i_reg), + (.I0(aempty_fwft_fb_i), + .I1(ram_empty_fb_i_reg), + .I2(curr_fwft_state[1]), + .I3(curr_fwft_state[0]), + .I4(s_axi_rready), + .I5(empty_fwft_fb_o_i), .O(aempty_fwft_i0)); (* DONT_TOUCH *) (* KEEP = "yes" *) @@ -7317,13 +7576,13 @@ module Arty_Z7_20_s00_data_fifo_0_rd_fwft__parameterized0 .PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [1]), .Q(aempty_fwft_i)); LUT5 #( - .INIT(32'hAA00BAAA)) + .INIT(32'hA2A2B2A2)) empty_fwft_fb_i_i_1__0 (.I0(empty_fwft_fb_i), - .I1(empty_fwft_fb_o_i), - .I2(s_axi_rready), - .I3(curr_fwft_state[0]), - .I4(curr_fwft_state[1]), + .I1(curr_fwft_state[1]), + .I2(curr_fwft_state[0]), + .I3(s_axi_rready), + .I4(empty_fwft_fb_o_i), .O(empty_fwft_i0)); (* DONT_TOUCH *) (* KEEP = "yes" *) @@ -7337,12 +7596,12 @@ module Arty_Z7_20_s00_data_fifo_0_rd_fwft__parameterized0 .PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [1]), .Q(empty_fwft_fb_i)); LUT4 #( - .INIT(16'hA0EA)) + .INIT(16'hF320)) empty_fwft_fb_o_i_i_1__0 - (.I0(empty_fwft_fb_o_i), - .I1(s_axi_rready), + (.I0(s_axi_rready), + .I1(curr_fwft_state[1]), .I2(curr_fwft_state[0]), - .I3(curr_fwft_state[1]), + .I3(empty_fwft_fb_o_i), .O(empty_fwft_fb_o_i_reg0)); (* DONT_TOUCH *) (* KEEP = "yes" *) @@ -7398,29 +7657,29 @@ module Arty_Z7_20_s00_data_fifo_0_rd_fwft__parameterized0 .Q(sckt_rd_rst_fwft), .R(1'b0)); LUT5 #( - .INIT(32'h04440404)) + .INIT(32'h00005D00)) \goreg_bm.dout_i[68]_i_1 - (.I0(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [0]), - .I1(curr_fwft_state[1]), - .I2(curr_fwft_state[0]), - .I3(empty_fwft_fb_o_i), - .I4(s_axi_rready), + (.I0(curr_fwft_state[0]), + .I1(s_axi_rready), + .I2(empty_fwft_fb_o_i), + .I3(curr_fwft_state[1]), + .I4(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [0]), .O(\goreg_bm.dout_i_reg[68] )); LUT4 #( - .INIT(16'hEAEE)) + .INIT(16'hEEAE)) \gpregsm1.curr_fwft_state[0]_i_1__0 (.I0(curr_fwft_state[1]), .I1(curr_fwft_state[0]), - .I2(empty_fwft_fb_o_i), - .I3(s_axi_rready), + .I2(s_axi_rready), + .I3(empty_fwft_fb_o_i), .O(next_fwft_state[0])); LUT5 #( - .INIT(32'hA200FFFF)) + .INIT(32'hD000FFFF)) \gpregsm1.curr_fwft_state[1]_i_2 - (.I0(curr_fwft_state[1]), - .I1(s_axi_rready), - .I2(empty_fwft_fb_o_i), - .I3(curr_fwft_state[0]), + (.I0(s_axi_rready), + .I1(empty_fwft_fb_o_i), + .I2(curr_fwft_state[0]), + .I3(curr_fwft_state[1]), .I4(ram_empty_fb_i_reg), .O(next_fwft_state[1])); (* DONT_TOUCH *) @@ -7456,32 +7715,22 @@ module Arty_Z7_20_s00_data_fifo_0_rd_fwft__parameterized0 .D(next_fwft_state[0]), .Q(user_valid), .R(SR)); - LUT6 #( - .INIT(64'hAAAAAAAA65AAAAAA)) - i__carry__0_i_4 - (.I0(Q), - .I1(empty_fwft_fb_o_i), - .I2(s_axi_rready), - .I3(arready_pkt), - .I4(CO), - .I5(empty_fwft_i_reg_0), - .O(S)); LUT4 #( - .INIT(16'h75FF)) - ram_empty_fb_i_i_2__0 - (.I0(curr_fwft_state[0]), - .I1(empty_fwft_fb_o_i), - .I2(s_axi_rready), - .I3(curr_fwft_state[1]), + .INIT(16'h8088)) + ram_empty_fb_i_i_2 + (.I0(curr_fwft_state[1]), + .I1(curr_fwft_state[0]), + .I2(empty_fwft_fb_o_i), + .I3(s_axi_rready), .O(ram_empty_i_reg)); LUT5 #( - .INIT(32'hEEAEAAAA)) + .INIT(32'hFBAAAAAA)) ram_full_fb_i_i_2 (.I0(ram_empty_fb_i_reg), - .I1(curr_fwft_state[1]), - .I2(s_axi_rready), - .I3(empty_fwft_fb_o_i), - .I4(curr_fwft_state[0]), + .I1(s_axi_rready), + .I2(empty_fwft_fb_o_i), + .I3(curr_fwft_state[0]), + .I4(curr_fwft_state[1]), .O(ram_full_i_reg)); LUT1 #( .INIT(2'h1)) @@ -7492,55 +7741,59 @@ endmodule module Arty_Z7_20_s00_data_fifo_0_rd_logic (out, - \gfwd_rev_pipeline1.s_ready_i_reg , - \gfwd_rev_pipeline1.s_ready_i_reg_0 , - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0] , E, - ram_empty_fb_i_reg, - \gc0.count_reg[4] , - ram_full_fb_i_reg, - \goreg_dm.dout_i_reg[59] , - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] , - \gfwd_rev_pipeline1.s_ready_i_reg_1 , - \gfwd_rev_pipeline1.s_ready_i_reg_2 , + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0] , + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0]_0 , + ram_full_comb, + \goreg_dm.dout_i_reg[62] , + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3] , Q, - ram_full_fb_i_reg_0, + \gfwd_rev_pipeline1.s_ready_i_reg , + \gfwd_rev_pipeline1.s_ready_i_reg_0 , + \gpr1.dout_i_reg[1] , + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0 , s_aclk, \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] , - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] , CO, arready_pkt, - s_axi_rready, empty_fwft_fb_o_i_reg, - \gfwd_rev_pipeline1.s_ready_i_reg_3 , + s_axi_rready, + \gfwd_rev_pipeline1.s_ready_i_reg_1 , + ram_full_fb_i_reg, + \grstd1.grst_full.grst_f.rst_d3_reg , ram_full_i_reg, + \gc0.count_reg[2] , + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] , + \gcc0.gc0.count_reg[4] , \gcc0.gc0.count_d1_reg[4] , - \gcc0.gc0.count_reg[4] ); + \goreg_dm.dout_i_reg[22] ); output out; - output [1:0]\gfwd_rev_pipeline1.s_ready_i_reg ; - output [0:0]\gfwd_rev_pipeline1.s_ready_i_reg_0 ; - output \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0] ; output [0:0]E; - output ram_empty_fb_i_reg; - output [0:0]\gc0.count_reg[4] ; - output ram_full_fb_i_reg; - output [0:0]\goreg_dm.dout_i_reg[59] ; - output \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] ; - output [1:0]\gfwd_rev_pipeline1.s_ready_i_reg_1 ; - output [0:0]\gfwd_rev_pipeline1.s_ready_i_reg_2 ; + output \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0] ; + output [0:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0]_0 ; + output ram_full_comb; + output [0:0]\goreg_dm.dout_i_reg[62] ; + output \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3] ; output [4:0]Q; - output ram_full_fb_i_reg_0; + output [0:0]\gfwd_rev_pipeline1.s_ready_i_reg ; + output [0:0]\gfwd_rev_pipeline1.s_ready_i_reg_0 ; + output [4:0]\gpr1.dout_i_reg[1] ; + output [0:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0 ; input s_aclk; input [1:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ; - input [5:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ; input [0:0]CO; input arready_pkt; - input s_axi_rready; input empty_fwft_fb_o_i_reg; - input \gfwd_rev_pipeline1.s_ready_i_reg_3 ; - input ram_full_i_reg; + input s_axi_rready; + input \gfwd_rev_pipeline1.s_ready_i_reg_1 ; + input ram_full_fb_i_reg; + input \grstd1.grst_full.grst_f.rst_d3_reg ; + input [0:0]ram_full_i_reg; + input \gc0.count_reg[2] ; + input [1:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ; + input [4:0]\gcc0.gc0.count_reg[4] ; input [4:0]\gcc0.gc0.count_d1_reg[4] ; - input [2:0]\gcc0.gc0.count_reg[4] ; + input [0:0]\goreg_dm.dout_i_reg[22] ; wire [0:0]CO; wire [0:0]E; @@ -7548,26 +7801,28 @@ module Arty_Z7_20_s00_data_fifo_0_rd_logic wire arready_pkt; wire empty_fwft_fb_o_i_reg; wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0] ; - wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] ; - wire [5:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ; - wire [0:0]\gc0.count_reg[4] ; + wire [0:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0]_0 ; + wire \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3] ; + wire [0:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0 ; + wire [1:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ; + wire \gc0.count_reg[2] ; wire [4:0]\gcc0.gc0.count_d1_reg[4] ; - wire [2:0]\gcc0.gc0.count_reg[4] ; - wire [1:0]\gfwd_rev_pipeline1.s_ready_i_reg ; + wire [4:0]\gcc0.gc0.count_reg[4] ; + wire [0:0]\gfwd_rev_pipeline1.s_ready_i_reg ; wire [0:0]\gfwd_rev_pipeline1.s_ready_i_reg_0 ; - wire [1:0]\gfwd_rev_pipeline1.s_ready_i_reg_1 ; - wire [0:0]\gfwd_rev_pipeline1.s_ready_i_reg_2 ; - wire \gfwd_rev_pipeline1.s_ready_i_reg_3 ; - wire [0:0]\goreg_dm.dout_i_reg[59] ; - wire \gr1.gr1_int.rfwft_n_8 ; + wire \gfwd_rev_pipeline1.s_ready_i_reg_1 ; + wire [0:0]\goreg_dm.dout_i_reg[22] ; + wire [0:0]\goreg_dm.dout_i_reg[62] ; + wire [4:0]\gpr1.dout_i_reg[1] ; + wire \gr1.gr1_int.rfwft_n_4 ; + wire \grstd1.grst_full.grst_f.rst_d3_reg ; wire [1:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ; wire out; wire p_2_out; - wire ram_empty_fb_i_reg; + wire ram_full_comb; wire ram_full_fb_i_reg; - wire ram_full_fb_i_reg_0; - wire ram_full_i_reg; - wire rpntr_n_0; + wire [0:0]ram_full_i_reg; + wire rpntr_n_1; wire s_aclk; wire s_axi_rready; @@ -7577,38 +7832,40 @@ module Arty_Z7_20_s00_data_fifo_0_rd_logic .arready_pkt(arready_pkt), .empty_fwft_fb_o_i_reg_0(empty_fwft_fb_o_i_reg), .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0] (\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0] ), - .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] (\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7] ), + .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0]_0 (\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0]_0 ), + .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3] (\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3] ), + .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0 (\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0 ), .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] (\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ), - .\gc0.count_reg[4] (\gc0.count_reg[4] ), .\gfwd_rev_pipeline1.s_ready_i_reg (\gfwd_rev_pipeline1.s_ready_i_reg ), .\gfwd_rev_pipeline1.s_ready_i_reg_0 (\gfwd_rev_pipeline1.s_ready_i_reg_0 ), .\gfwd_rev_pipeline1.s_ready_i_reg_1 (\gfwd_rev_pipeline1.s_ready_i_reg_1 ), - .\gfwd_rev_pipeline1.s_ready_i_reg_2 (\gfwd_rev_pipeline1.s_ready_i_reg_2 ), - .\gfwd_rev_pipeline1.s_ready_i_reg_3 (\gfwd_rev_pipeline1.s_ready_i_reg_3 ), - .\goreg_dm.dout_i_reg[59] (\goreg_dm.dout_i_reg[59] ), + .\goreg_dm.dout_i_reg[22] (\goreg_dm.dout_i_reg[22] ), + .\goreg_dm.dout_i_reg[62] (\goreg_dm.dout_i_reg[62] ), .\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), .out(out), - .ram_empty_fb_i_reg(\gr1.gr1_int.rfwft_n_8 ), + .ram_empty_fb_i_reg(\gr1.gr1_int.rfwft_n_4 ), .ram_empty_fb_i_reg_0(p_2_out), - .ram_full_fb_i_reg(ram_full_fb_i_reg), .s_aclk(s_aclk), .s_axi_rready(s_axi_rready)); Arty_Z7_20_s00_data_fifo_0_rd_status_flags_ss \grss.rsts (.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [1]), .out(p_2_out), - .ram_empty_fb_i_reg_0(rpntr_n_0), + .ram_empty_fb_i_reg_0(rpntr_n_1), .s_aclk(s_aclk)); Arty_Z7_20_s00_data_fifo_0_rd_bin_cntr rpntr - (.E(\gc0.count_reg[4] ), + (.E(E), .Q(Q), + .empty_fwft_i_reg(\gr1.gr1_int.rfwft_n_4 ), + .\gc0.count_reg[2]_0 (\gc0.count_reg[2] ), .\gcc0.gc0.count_d1_reg[4] (\gcc0.gc0.count_d1_reg[4] ), .\gcc0.gc0.count_reg[4] (\gcc0.gc0.count_reg[4] ), - .\gpregsm1.curr_fwft_state_reg[0] (\gr1.gr1_int.rfwft_n_8 ), + .\gpr1.dout_i_reg[1] (\gpr1.dout_i_reg[1] ), + .\grstd1.grst_full.grst_f.rst_d3_reg (\grstd1.grst_full.grst_f.rst_d3_reg ), .\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [1]), .out(p_2_out), - .ram_empty_fb_i_reg(rpntr_n_0), - .ram_empty_fb_i_reg_0(ram_empty_fb_i_reg), - .ram_full_fb_i_reg(ram_full_fb_i_reg_0), + .ram_empty_fb_i_reg(rpntr_n_1), + .ram_full_comb(ram_full_comb), + .ram_full_fb_i_reg(ram_full_fb_i_reg), .ram_full_i_reg(ram_full_i_reg), .s_aclk(s_aclk)); endmodule @@ -7617,91 +7874,72 @@ endmodule module Arty_Z7_20_s00_data_fifo_0_rd_logic__parameterized0 (out, fwft_rst_done_q, - S, - ram_full_i_reg, - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram , - \gc0.count_d1_reg[7] , - ram_full_i_reg_0, + Q, E, - ram_full_i_reg_1, + ram_full_i_reg, \goreg_bm.dout_i_reg[68] , + v1_reg, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram , + v1_reg_0, + S, s_axi_rvalid, - \gcc0.gc0.count_d1_reg[1] , - \gcc0.gc0.count_d1_reg[2] , - \gcc0.gc0.count_d1_reg[5] , - \gcc0.gc0.count_d1_reg[6] , - \gcc0.gc0.count_d1_reg[0] , - \gcc0.gc0.count_d1_reg[3] , - \gcc0.gc0.count_d1_reg[4] , - \gcc0.gc0.count_d1_reg[6]_0 , + \gcc0.gc0.count_d1_reg[8] , + v1_reg_1, \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg , s_aclk, \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] , SR, - Q, + \gcc0.gc0.count_d1_reg[8]_0 , s_axi_rready, - arready_pkt, + ram_full_fb_i_reg, + m_axi_rvalid, + \gcc0.gc0.count_reg[7] , CO, + arready_pkt, empty_fwft_i_reg, - \gcc0.gc0.count_d1_reg[8] , - \gcc0.gc0.count_reg[8] , - ram_full_fb_i_reg, - m_axi_rvalid); + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ); output out; output fwft_rst_done_q; - output [0:0]S; - output ram_full_i_reg; - output [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; - output [7:0]\gc0.count_d1_reg[7] ; - output ram_full_i_reg_0; + output [7:0]Q; output [0:0]E; - output ram_full_i_reg_1; + output ram_full_i_reg; output [0:0]\goreg_bm.dout_i_reg[68] ; + output [3:0]v1_reg; + output [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; + output [3:0]v1_reg_0; + output [0:0]S; output s_axi_rvalid; - input \gcc0.gc0.count_d1_reg[1] ; - input \gcc0.gc0.count_d1_reg[2] ; - input \gcc0.gc0.count_d1_reg[5] ; - input \gcc0.gc0.count_d1_reg[6] ; - input \gcc0.gc0.count_d1_reg[0] ; - input \gcc0.gc0.count_d1_reg[3] ; - input \gcc0.gc0.count_d1_reg[4] ; - input \gcc0.gc0.count_d1_reg[6]_0 ; + input \gcc0.gc0.count_d1_reg[8] ; + input [3:0]v1_reg_1; input \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg ; input s_aclk; input [1:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ; input [0:0]SR; - input [0:0]Q; + input [8:0]\gcc0.gc0.count_d1_reg[8]_0 ; input s_axi_rready; - input arready_pkt; - input [0:0]CO; - input empty_fwft_i_reg; - input [0:0]\gcc0.gc0.count_d1_reg[8] ; - input [0:0]\gcc0.gc0.count_reg[8] ; input ram_full_fb_i_reg; input m_axi_rvalid; + input [7:0]\gcc0.gc0.count_reg[7] ; + input [0:0]CO; + input arready_pkt; + input empty_fwft_i_reg; + input [0:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ; wire [0:0]CO; wire [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ; wire [0:0]E; - wire [0:0]Q; + wire [7:0]Q; wire [0:0]S; wire [0:0]SR; wire arready_pkt; wire empty_fwft_i_reg; wire fwft_rst_done_q; - wire [7:0]\gc0.count_d1_reg[7] ; - wire \gcc0.gc0.count_d1_reg[0] ; - wire \gcc0.gc0.count_d1_reg[1] ; - wire \gcc0.gc0.count_d1_reg[2] ; - wire \gcc0.gc0.count_d1_reg[3] ; - wire \gcc0.gc0.count_d1_reg[4] ; - wire \gcc0.gc0.count_d1_reg[5] ; - wire \gcc0.gc0.count_d1_reg[6] ; - wire \gcc0.gc0.count_d1_reg[6]_0 ; - wire [0:0]\gcc0.gc0.count_d1_reg[8] ; - wire [0:0]\gcc0.gc0.count_reg[8] ; + wire [0:0]\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ; + wire \gcc0.gc0.count_d1_reg[8] ; + wire [8:0]\gcc0.gc0.count_d1_reg[8]_0 ; + wire [7:0]\gcc0.gc0.count_reg[7] ; wire [0:0]\goreg_bm.dout_i_reg[68] ; - wire \gr1.gr1_int.rfwft_n_5 ; + wire \gr1.gr1_int.rfwft_n_4 ; wire m_axi_rvalid; wire \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg ; wire [1:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ; @@ -7709,63 +7947,67 @@ module Arty_Z7_20_s00_data_fifo_0_rd_logic__parameterized0 wire p_2_out; wire ram_full_fb_i_reg; wire ram_full_i_reg; - wire ram_full_i_reg_0; - wire ram_full_i_reg_1; - wire rpntr_n_10; - wire rpntr_n_12; + wire rpntr_n_0; + wire rpntr_n_26; + wire rpntr_n_27; + wire rpntr_n_28; + wire rpntr_n_29; wire s_aclk; wire s_axi_rready; wire s_axi_rvalid; + wire [3:0]v1_reg; + wire [3:0]v1_reg_0; + wire [3:0]v1_reg_1; Arty_Z7_20_s00_data_fifo_0_rd_fwft__parameterized0 \gr1.gr1_int.rfwft (.CO(CO), .E(E), - .Q(Q), .S(S), .SR(SR), .arready_pkt(arready_pkt), .empty_fwft_i_reg_0(empty_fwft_i_reg), .fwft_rst_done_q(fwft_rst_done_q), + .\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] (\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9] ), .\goreg_bm.dout_i_reg[68] (\goreg_bm.dout_i_reg[68] ), .\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg (\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg ), .\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), .out(out), .ram_empty_fb_i_reg(p_2_out), - .ram_empty_i_reg(\gr1.gr1_int.rfwft_n_5 ), - .ram_full_i_reg(ram_full_i_reg_1), + .ram_empty_i_reg(\gr1.gr1_int.rfwft_n_4 ), + .ram_full_i_reg(ram_full_i_reg), .s_aclk(s_aclk), .s_axi_rready(s_axi_rready), .s_axi_rvalid(s_axi_rvalid)); Arty_Z7_20_s00_data_fifo_0_rd_status_flags_ss__parameterized0 \grss.rsts - (.\gc0.count_d1_reg[8] (rpntr_n_12), - .\gc0.count_reg[8] (rpntr_n_10), - .\gcc0.gc0.count_d1_reg[0] (\gcc0.gc0.count_d1_reg[0] ), - .\gcc0.gc0.count_d1_reg[1] (\gcc0.gc0.count_d1_reg[1] ), - .\gcc0.gc0.count_d1_reg[2] (\gcc0.gc0.count_d1_reg[2] ), - .\gcc0.gc0.count_d1_reg[3] (\gcc0.gc0.count_d1_reg[3] ), - .\gcc0.gc0.count_d1_reg[4] (\gcc0.gc0.count_d1_reg[4] ), - .\gcc0.gc0.count_d1_reg[5] (\gcc0.gc0.count_d1_reg[5] ), - .\gcc0.gc0.count_d1_reg[6] (\gcc0.gc0.count_d1_reg[6] ), - .\gcc0.gc0.count_d1_reg[6]_0 (\gcc0.gc0.count_d1_reg[6]_0 ), - .\gpregsm1.curr_fwft_state_reg[0] (\gr1.gr1_int.rfwft_n_5 ), + (.\gc0.count_d1_reg[0] (rpntr_n_26), + .\gc0.count_d1_reg[2] (rpntr_n_27), + .\gc0.count_d1_reg[5] (rpntr_n_28), + .\gc0.count_d1_reg[7] (rpntr_n_29), + .\gc0.count_reg[8] (rpntr_n_0), + .\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ), + .\gpregsm1.curr_fwft_state_reg[1] (\gr1.gr1_int.rfwft_n_4 ), .m_axi_rvalid(m_axi_rvalid), .\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg (\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg ), .\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [1]), .out(p_2_out), .ram_full_fb_i_reg(ram_full_fb_i_reg), - .s_aclk(s_aclk)); + .s_aclk(s_aclk), + .v1_reg_1(v1_reg_1)); Arty_Z7_20_s00_data_fifo_0_rd_bin_cntr__parameterized0 rpntr - (.E(E), - .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ), - .\gc0.count_d1_reg[7]_0 (\gc0.count_d1_reg[7] ), - .\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ), - .\gcc0.gc0.count_reg[8] (\gcc0.gc0.count_reg[8] ), + (.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram ), + .E(E), + .Q(Q), + .\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8]_0 ), + .\gcc0.gc0.count_reg[7] (\gcc0.gc0.count_reg[7] ), .\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg (\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg ), - .ram_empty_i_reg(rpntr_n_10), - .ram_empty_i_reg_0(rpntr_n_12), - .ram_full_i_reg(ram_full_i_reg), - .ram_full_i_reg_0(ram_full_i_reg_0), - .s_aclk(s_aclk)); + .ram_empty_i_reg(rpntr_n_0), + .ram_empty_i_reg_0(rpntr_n_26), + .ram_empty_i_reg_1(rpntr_n_27), + .ram_empty_i_reg_2(rpntr_n_28), + .ram_empty_i_reg_3(rpntr_n_29), + .s_aclk(s_aclk), + .v1_reg(v1_reg), + .v1_reg_0(v1_reg_0)); endmodule module Arty_Z7_20_s00_data_fifo_0_rd_status_flags_ss @@ -7812,53 +8054,43 @@ endmodule (* ORIG_REF_NAME = "rd_status_flags_ss" *) module Arty_Z7_20_s00_data_fifo_0_rd_status_flags_ss__parameterized0 (out, - \gcc0.gc0.count_d1_reg[1] , - \gcc0.gc0.count_d1_reg[2] , - \gcc0.gc0.count_d1_reg[5] , - \gcc0.gc0.count_d1_reg[6] , - \gc0.count_d1_reg[8] , - \gcc0.gc0.count_d1_reg[0] , - \gcc0.gc0.count_d1_reg[3] , - \gcc0.gc0.count_d1_reg[4] , - \gcc0.gc0.count_d1_reg[6]_0 , + \gc0.count_d1_reg[0] , + \gc0.count_d1_reg[2] , + \gc0.count_d1_reg[5] , + \gc0.count_d1_reg[7] , + \gcc0.gc0.count_d1_reg[8] , + v1_reg_1, \gc0.count_reg[8] , \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg , s_aclk, \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] , + \gpregsm1.curr_fwft_state_reg[1] , ram_full_fb_i_reg, - m_axi_rvalid, - \gpregsm1.curr_fwft_state_reg[0] ); + m_axi_rvalid); output out; - input \gcc0.gc0.count_d1_reg[1] ; - input \gcc0.gc0.count_d1_reg[2] ; - input \gcc0.gc0.count_d1_reg[5] ; - input \gcc0.gc0.count_d1_reg[6] ; - input \gc0.count_d1_reg[8] ; - input \gcc0.gc0.count_d1_reg[0] ; - input \gcc0.gc0.count_d1_reg[3] ; - input \gcc0.gc0.count_d1_reg[4] ; - input \gcc0.gc0.count_d1_reg[6]_0 ; + input \gc0.count_d1_reg[0] ; + input \gc0.count_d1_reg[2] ; + input \gc0.count_d1_reg[5] ; + input \gc0.count_d1_reg[7] ; + input \gcc0.gc0.count_d1_reg[8] ; + input [3:0]v1_reg_1; input \gc0.count_reg[8] ; input \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg ; input s_aclk; input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ; + input \gpregsm1.curr_fwft_state_reg[1] ; input ram_full_fb_i_reg; input m_axi_rvalid; - input \gpregsm1.curr_fwft_state_reg[0] ; wire c2_n_0; wire comp0; - wire \gc0.count_d1_reg[8] ; + wire \gc0.count_d1_reg[0] ; + wire \gc0.count_d1_reg[2] ; + wire \gc0.count_d1_reg[5] ; + wire \gc0.count_d1_reg[7] ; wire \gc0.count_reg[8] ; - wire \gcc0.gc0.count_d1_reg[0] ; - wire \gcc0.gc0.count_d1_reg[1] ; - wire \gcc0.gc0.count_d1_reg[2] ; - wire \gcc0.gc0.count_d1_reg[3] ; - wire \gcc0.gc0.count_d1_reg[4] ; - wire \gcc0.gc0.count_d1_reg[5] ; - wire \gcc0.gc0.count_d1_reg[6] ; - wire \gcc0.gc0.count_d1_reg[6]_0 ; - wire \gpregsm1.curr_fwft_state_reg[0] ; + wire \gcc0.gc0.count_d1_reg[8] ; + wire \gpregsm1.curr_fwft_state_reg[1] ; wire m_axi_rvalid; wire \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg ; wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ; @@ -7866,27 +8098,25 @@ module Arty_Z7_20_s00_data_fifo_0_rd_status_flags_ss__parameterized0 (* DONT_TOUCH *) wire ram_empty_i; wire ram_full_fb_i_reg; wire s_aclk; + wire [3:0]v1_reg_1; assign out = ram_empty_fb_i; Arty_Z7_20_s00_data_fifo_0_compare__parameterized0 c1 (.comp0(comp0), - .\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ), - .\gcc0.gc0.count_d1_reg[1] (\gcc0.gc0.count_d1_reg[1] ), - .\gcc0.gc0.count_d1_reg[2] (\gcc0.gc0.count_d1_reg[2] ), - .\gcc0.gc0.count_d1_reg[5] (\gcc0.gc0.count_d1_reg[5] ), - .\gcc0.gc0.count_d1_reg[6] (\gcc0.gc0.count_d1_reg[6] )); + .\gc0.count_d1_reg[0] (\gc0.count_d1_reg[0] ), + .\gc0.count_d1_reg[2] (\gc0.count_d1_reg[2] ), + .\gc0.count_d1_reg[5] (\gc0.count_d1_reg[5] ), + .\gc0.count_d1_reg[7] (\gc0.count_d1_reg[7] ), + .\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] )); Arty_Z7_20_s00_data_fifo_0_compare__parameterized1 c2 (.comp0(comp0), .\gc0.count_reg[8] (\gc0.count_reg[8] ), - .\gcc0.gc0.count_d1_reg[0] (\gcc0.gc0.count_d1_reg[0] ), - .\gcc0.gc0.count_d1_reg[3] (\gcc0.gc0.count_d1_reg[3] ), - .\gcc0.gc0.count_d1_reg[4] (\gcc0.gc0.count_d1_reg[4] ), - .\gcc0.gc0.count_d1_reg[6] (\gcc0.gc0.count_d1_reg[6]_0 ), - .\gpregsm1.curr_fwft_state_reg[0] (\gpregsm1.curr_fwft_state_reg[0] ), + .\gpregsm1.curr_fwft_state_reg[1] (\gpregsm1.curr_fwft_state_reg[1] ), .m_axi_rvalid(m_axi_rvalid), .out(ram_empty_fb_i), .ram_empty_i_reg(c2_n_0), - .ram_full_fb_i_reg(ram_full_fb_i_reg)); + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .v1_reg_1(v1_reg_1)); (* DONT_TOUCH *) (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) @@ -8104,13 +8334,13 @@ module Arty_Z7_20_s00_data_fifo_0_reset_blk_ramfifo__parameterized0 (out, \gc0.count_reg[1] , \grstd1.grst_full.grst_f.rst_d3_reg_0 , - ram_full_fb_i_reg, + ram_full_i_reg, s_aclk, inverted_reset); output [0:0]out; output [1:0]\gc0.count_reg[1] ; output \grstd1.grst_full.grst_f.rst_d3_reg_0 ; - output ram_full_fb_i_reg; + output ram_full_i_reg; input s_aclk; input inverted_reset; @@ -8138,7 +8368,7 @@ module Arty_Z7_20_s00_data_fifo_0_reset_blk_ramfifo__parameterized0 assign \gc0.count_reg[1] [0] = rd_rst_reg[0]; assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2; assign out[0] = wr_rst_reg[1]; - assign ram_full_fb_i_reg = rst_d3; + assign ram_full_i_reg = rst_d3; (* ASYNC_REG *) (* KEEP = "yes" *) (* msgon = "true" *) @@ -8328,25 +8558,25 @@ module Arty_Z7_20_s00_data_fifo_0_reset_blk_ramfifo__parameterized1 \gfwd_rev_pipeline1.s_ready_i_reg , s_aclk, s_aresetn, - arready_pkt, + \gfwd_rev_pipeline1.areset_d1_reg , CO, - empty_fwft_i_reg, - \gfwd_rev_pipeline1.m_valid_i_reg ); + arready_pkt, + empty_fwft_i_reg); output [0:0]out; output \grstd1.grst_full.grst_f.rst_d3_reg_0 ; output \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg_0 ; output \gfwd_rev_pipeline1.s_ready_i_reg ; input s_aclk; input s_aresetn; - input arready_pkt; + input \gfwd_rev_pipeline1.areset_d1_reg ; input [0:0]CO; + input arready_pkt; input empty_fwft_i_reg; - input \gfwd_rev_pipeline1.m_valid_i_reg ; wire [0:0]CO; wire arready_pkt; wire empty_fwft_i_reg; - wire \gfwd_rev_pipeline1.m_valid_i_reg ; + wire \gfwd_rev_pipeline1.areset_d1_reg ; wire \gfwd_rev_pipeline1.s_ready_i_reg ; wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ; wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ; @@ -8372,12 +8602,12 @@ module Arty_Z7_20_s00_data_fifo_0_reset_blk_ramfifo__parameterized1 assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2; assign out[0] = wr_rst_reg[0]; LUT6 #( - .INIT(64'h000000000000FFA2)) + .INIT(64'h000000000000FABA)) \gfwd_rev_pipeline1.s_ready_i_i_1 - (.I0(arready_pkt), + (.I0(\gfwd_rev_pipeline1.areset_d1_reg ), .I1(CO), - .I2(empty_fwft_i_reg), - .I3(\gfwd_rev_pipeline1.m_valid_i_reg ), + .I2(arready_pkt), + .I3(empty_fwft_i_reg), .I4(rst_d2), .I5(wr_rst_reg[0]), .O(\gfwd_rev_pipeline1.s_ready_i_reg )); @@ -8561,7 +8791,7 @@ module Arty_Z7_20_s00_data_fifo_0_reset_blk_ramfifo__parameterized2 (out, ram_full_i_reg, ram_full_i_reg_0, - \gcc0.gc0.count_reg[1] , + \gcc0.gc0.count_d1_reg[0] , SR, s_aclk, inverted_reset, @@ -8569,7 +8799,7 @@ module Arty_Z7_20_s00_data_fifo_0_reset_blk_ramfifo__parameterized2 output [1:0]out; output ram_full_i_reg; output ram_full_i_reg_0; - output \gcc0.gc0.count_reg[1] ; + output \gcc0.gc0.count_d1_reg[0] ; output [0:0]SR; input s_aclk; input inverted_reset; @@ -8580,7 +8810,7 @@ module Arty_Z7_20_s00_data_fifo_0_reset_blk_ramfifo__parameterized2 wire \arst_sync_q[2]_7 ; wire \arst_sync_q[3]_8 ; wire fwft_rst_done_q; - wire \gcc0.gc0.count_reg[1] ; + wire \gcc0.gc0.count_d1_reg[0] ; wire \grstd1.grst_full.grst_f.rst_d3_i_1_n_0 ; wire inverted_reset; wire \ngwrdrst.grst.g7serrst.gsckt_wrst.rd_rst_active_i_1_n_0 ; @@ -8621,8 +8851,8 @@ module Arty_Z7_20_s00_data_fifo_0_reset_blk_ramfifo__parameterized2 assign ram_full_i_reg_0 = rst_d3; LUT2 #( .INIT(4'hB)) - \gpregsm1.curr_fwft_state[1]_i_1__0 - (.I0(\gcc0.gc0.count_reg[1] ), + \gpregsm1.curr_fwft_state[1]_i_1 + (.I0(\gcc0.gc0.count_d1_reg[0] ), .I1(fwft_rst_done_q), .O(SR)); (* ASYNC_REG *) @@ -8651,7 +8881,7 @@ module Arty_Z7_20_s00_data_fifo_0_reset_blk_ramfifo__parameterized2 .INIT(4'hE)) \grstd1.grst_full.grst_f.rst_d3_i_1 (.I0(rst_d2), - .I1(\gcc0.gc0.count_reg[1] ), + .I1(\gcc0.gc0.count_d1_reg[0] ), .O(\grstd1.grst_full.grst_f.rst_d3_i_1_n_0 )); (* ASYNC_REG *) (* KEEP = "yes" *) @@ -8693,7 +8923,7 @@ module Arty_Z7_20_s00_data_fifo_0_reset_blk_ramfifo__parameterized2 (.C(s_aclk), .CE(1'b1), .D(p_0_out_n_0), - .Q(\gcc0.gc0.count_reg[1] ), + .Q(\gcc0.gc0.count_d1_reg[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) @@ -9707,88 +9937,72 @@ module Arty_Z7_20_s00_data_fifo_0_synchronizer_ff_9 endmodule module Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr - (ram_full_comb, - Q, - \gpr1.dout_i_reg[5] , + (Q, ram_empty_fb_i_reg, - out, - \grstd1.grst_full.grst_f.rst_d3_reg , - \gc0.count_d1_reg[2] , - \gc0.count_d1_reg[1] , - \gc0.count_d1_reg[2]_0 , - ram_full_i_reg, + \gpr1.dout_i_reg[1] , + \gc0.count_reg[4] , + ram_full_fb_i_reg, E, s_aclk, AR); - output ram_full_comb; - output [2:0]Q; - output [4:0]\gpr1.dout_i_reg[5] ; - input ram_empty_fb_i_reg; - input out; - input \grstd1.grst_full.grst_f.rst_d3_reg ; - input \gc0.count_d1_reg[2] ; - input [1:0]\gc0.count_d1_reg[1] ; - input \gc0.count_d1_reg[2]_0 ; - input ram_full_i_reg; + output [4:0]Q; + output ram_empty_fb_i_reg; + output [4:0]\gpr1.dout_i_reg[1] ; + input [3:0]\gc0.count_reg[4] ; + input ram_full_fb_i_reg; input [0:0]E; input s_aclk; input [0:0]AR; wire [0:0]AR; wire [0:0]E; - wire [2:0]Q; - wire [1:0]\gc0.count_d1_reg[1] ; - wire \gc0.count_d1_reg[2] ; - wire \gc0.count_d1_reg[2]_0 ; - wire [4:0]\gpr1.dout_i_reg[5] ; - wire \grstd1.grst_full.grst_f.rst_d3_reg ; - wire out; - wire [1:0]p_12_out; + wire [4:0]Q; + wire [3:0]\gc0.count_reg[4] ; + wire [4:0]\gpr1.dout_i_reg[1] ; wire [4:0]plusOp__0; + wire ram_empty_fb_i_i_7_n_0; wire ram_empty_fb_i_reg; - wire ram_full_comb; - wire ram_full_fb_i_i_2__0_n_0; - wire ram_full_i_reg; + wire ram_full_fb_i_reg; wire s_aclk; LUT1 #( .INIT(2'h1)) \gcc0.gc0.count[0]_i_1 - (.I0(p_12_out[0]), + (.I0(Q[0]), .O(plusOp__0[0])); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT2 #( .INIT(4'h6)) \gcc0.gc0.count[1]_i_1 - (.I0(p_12_out[0]), - .I1(p_12_out[1]), + (.I0(Q[1]), + .I1(Q[0]), .O(plusOp__0[1])); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT3 #( - .INIT(8'h78)) + .INIT(8'h6A)) \gcc0.gc0.count[2]_i_1 - (.I0(p_12_out[1]), - .I1(p_12_out[0]), + (.I0(Q[2]), + .I1(Q[1]), .I2(Q[0]), .O(plusOp__0[2])); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT4 #( .INIT(16'h7F80)) \gcc0.gc0.count[3]_i_1 - (.I0(p_12_out[0]), - .I1(p_12_out[1]), - .I2(Q[0]), - .I3(Q[1]), + (.I0(Q[0]), + .I1(Q[1]), + .I2(Q[2]), + .I3(Q[3]), .O(plusOp__0[3])); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT5 #( - .INIT(32'h7FFF8000)) + .INIT(32'h6AAAAAAA)) \gcc0.gc0.count[4]_i_1 - (.I0(Q[0]), - .I1(Q[1]), - .I2(p_12_out[0]), - .I3(p_12_out[1]), - .I4(Q[2]), + (.I0(Q[4]), + .I1(Q[0]), + .I2(Q[1]), + .I3(Q[2]), + .I4(Q[3]), .O(plusOp__0[4])); FDCE #( .INIT(1'b0)) @@ -9796,40 +10010,40 @@ module Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr (.C(s_aclk), .CE(E), .CLR(AR), - .D(p_12_out[0]), - .Q(\gpr1.dout_i_reg[5] [0])); + .D(Q[0]), + .Q(\gpr1.dout_i_reg[1] [0])); FDCE #( .INIT(1'b0)) \gcc0.gc0.count_d1_reg[1] (.C(s_aclk), .CE(E), .CLR(AR), - .D(p_12_out[1]), - .Q(\gpr1.dout_i_reg[5] [1])); + .D(Q[1]), + .Q(\gpr1.dout_i_reg[1] [1])); FDCE #( .INIT(1'b0)) \gcc0.gc0.count_d1_reg[2] (.C(s_aclk), .CE(E), .CLR(AR), - .D(Q[0]), - .Q(\gpr1.dout_i_reg[5] [2])); + .D(Q[2]), + .Q(\gpr1.dout_i_reg[1] [2])); FDCE #( .INIT(1'b0)) \gcc0.gc0.count_d1_reg[3] (.C(s_aclk), .CE(E), .CLR(AR), - .D(Q[1]), - .Q(\gpr1.dout_i_reg[5] [3])); + .D(Q[3]), + .Q(\gpr1.dout_i_reg[1] [3])); FDCE #( .INIT(1'b0)) \gcc0.gc0.count_d1_reg[4] (.C(s_aclk), .CE(E), .CLR(AR), - .D(Q[2]), - .Q(\gpr1.dout_i_reg[5] [4])); + .D(Q[4]), + .Q(\gpr1.dout_i_reg[1] [4])); FDPE #( .INIT(1'b1)) \gcc0.gc0.count_reg[0] @@ -9837,7 +10051,7 @@ module Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr .CE(E), .D(plusOp__0[0]), .PRE(AR), - .Q(p_12_out[0])); + .Q(Q[0])); FDCE #( .INIT(1'b0)) \gcc0.gc0.count_reg[1] @@ -9845,7 +10059,7 @@ module Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr .CE(E), .CLR(AR), .D(plusOp__0[1]), - .Q(p_12_out[1])); + .Q(Q[1])); FDCE #( .INIT(1'b0)) \gcc0.gc0.count_reg[2] @@ -9853,7 +10067,7 @@ module Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr .CE(E), .CLR(AR), .D(plusOp__0[2]), - .Q(Q[0])); + .Q(Q[2])); FDCE #( .INIT(1'b0)) \gcc0.gc0.count_reg[3] @@ -9861,7 +10075,7 @@ module Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr .CE(E), .CLR(AR), .D(plusOp__0[3]), - .Q(Q[1])); + .Q(Q[3])); FDCE #( .INIT(1'b0)) \gcc0.gc0.count_reg[4] @@ -9869,26 +10083,25 @@ module Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr .CE(E), .CLR(AR), .D(plusOp__0[4]), - .Q(Q[2])); - LUT5 #( - .INIT(32'h88F888C8)) - ram_full_fb_i_i_1 - (.I0(ram_full_fb_i_i_2__0_n_0), - .I1(ram_empty_fb_i_reg), - .I2(out), - .I3(\grstd1.grst_full.grst_f.rst_d3_reg ), - .I4(\gc0.count_d1_reg[2] ), - .O(ram_full_comb)); + .Q(Q[4])); LUT6 #( - .INIT(64'h0000000090090000)) - ram_full_fb_i_i_2__0 - (.I0(p_12_out[1]), - .I1(\gc0.count_d1_reg[1] [1]), - .I2(p_12_out[0]), - .I3(\gc0.count_d1_reg[1] [0]), - .I4(\gc0.count_d1_reg[2]_0 ), - .I5(ram_full_i_reg), - .O(ram_full_fb_i_i_2__0_n_0)); + .INIT(64'h0000000000009009)) + ram_empty_fb_i_i_4 + (.I0(\gc0.count_reg[4] [2]), + .I1(\gpr1.dout_i_reg[1] [2]), + .I2(\gc0.count_reg[4] [3]), + .I3(\gpr1.dout_i_reg[1] [4]), + .I4(ram_full_fb_i_reg), + .I5(ram_empty_fb_i_i_7_n_0), + .O(ram_empty_fb_i_reg)); + LUT4 #( + .INIT(16'h6FF6)) + ram_empty_fb_i_i_7 + (.I0(\gpr1.dout_i_reg[1] [1]), + .I1(\gc0.count_reg[4] [1]), + .I2(\gpr1.dout_i_reg[1] [0]), + .I3(\gc0.count_reg[4] [0]), + .O(ram_empty_fb_i_i_7_n_0)); endmodule (* ORIG_REF_NAME = "wr_bin_cntr" *) @@ -9896,22 +10109,10 @@ module Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr__parameterized0 (ram_full_i_reg, Q, ram_full_i_reg_0, - ram_full_i_reg_1, - ram_full_i_reg_2, ram_empty_i_reg, - ram_empty_i_reg_0, - ram_empty_i_reg_1, - ram_empty_i_reg_2, - ram_full_i_reg_3, - ram_full_i_reg_4, - ram_full_i_reg_5, - ram_full_i_reg_6, - ram_empty_i_reg_3, - ram_empty_i_reg_4, - ram_empty_i_reg_5, - ram_empty_i_reg_6, - \gcc0.gc0.count_d1_reg[8]_0 , - \gc0.count_d1_reg[7] , + \gcc0.gc0.count_d1_reg[7]_0 , + v1_reg, + \gc0.count_d1_reg[8] , \gc0.count_reg[7] , \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg , E, @@ -9919,22 +10120,10 @@ module Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr__parameterized0 output ram_full_i_reg; output [8:0]Q; output ram_full_i_reg_0; - output ram_full_i_reg_1; - output ram_full_i_reg_2; output ram_empty_i_reg; - output ram_empty_i_reg_0; - output ram_empty_i_reg_1; - output ram_empty_i_reg_2; - output ram_full_i_reg_3; - output ram_full_i_reg_4; - output ram_full_i_reg_5; - output ram_full_i_reg_6; - output ram_empty_i_reg_3; - output ram_empty_i_reg_4; - output ram_empty_i_reg_5; - output ram_empty_i_reg_6; - output [0:0]\gcc0.gc0.count_d1_reg[8]_0 ; - input [7:0]\gc0.count_d1_reg[7] ; + output [7:0]\gcc0.gc0.count_d1_reg[7]_0 ; + output [3:0]v1_reg; + input [0:0]\gc0.count_d1_reg[8] ; input [7:0]\gc0.count_reg[7] ; input \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg ; input [0:0]E; @@ -9942,121 +10131,111 @@ module Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr__parameterized0 wire [0:0]E; wire [8:0]Q; - wire [7:0]\gc0.count_d1_reg[7] ; + wire [0:0]\gc0.count_d1_reg[8] ; wire [7:0]\gc0.count_reg[7] ; wire \gcc0.gc0.count[8]_i_2_n_0 ; - wire [0:0]\gcc0.gc0.count_d1_reg[8]_0 ; + wire [7:0]\gcc0.gc0.count_d1_reg[7]_0 ; wire \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg ; - wire [7:0]p_13_out; + wire [8:8]p_13_out; wire [8:0]plusOp__2; wire ram_empty_i_reg; - wire ram_empty_i_reg_0; - wire ram_empty_i_reg_1; - wire ram_empty_i_reg_2; - wire ram_empty_i_reg_3; - wire ram_empty_i_reg_4; - wire ram_empty_i_reg_5; - wire ram_empty_i_reg_6; wire ram_full_i_reg; wire ram_full_i_reg_0; - wire ram_full_i_reg_1; - wire ram_full_i_reg_2; - wire ram_full_i_reg_3; - wire ram_full_i_reg_4; - wire ram_full_i_reg_5; - wire ram_full_i_reg_6; wire s_aclk; + wire [3:0]v1_reg; LUT1 #( .INIT(2'h1)) \gcc0.gc0.count[0]_i_1__0 - (.I0(p_13_out[0]), + (.I0(\gcc0.gc0.count_d1_reg[7]_0 [0]), .O(plusOp__2[0])); LUT2 #( .INIT(4'h6)) \gcc0.gc0.count[1]_i_1__0 - (.I0(p_13_out[0]), - .I1(p_13_out[1]), + (.I0(\gcc0.gc0.count_d1_reg[7]_0 [1]), + .I1(\gcc0.gc0.count_d1_reg[7]_0 [0]), .O(plusOp__2[1])); - (* SOFT_HLUTNM = "soft_lutpair14" *) + (* SOFT_HLUTNM = "soft_lutpair15" *) LUT3 #( - .INIT(8'h78)) + .INIT(8'h6A)) \gcc0.gc0.count[2]_i_1__0 - (.I0(p_13_out[1]), - .I1(p_13_out[0]), - .I2(p_13_out[2]), + (.I0(\gcc0.gc0.count_d1_reg[7]_0 [2]), + .I1(\gcc0.gc0.count_d1_reg[7]_0 [1]), + .I2(\gcc0.gc0.count_d1_reg[7]_0 [0]), .O(plusOp__2[2])); - (* SOFT_HLUTNM = "soft_lutpair14" *) + (* SOFT_HLUTNM = "soft_lutpair15" *) LUT4 #( .INIT(16'h7F80)) \gcc0.gc0.count[3]_i_1__0 - (.I0(p_13_out[2]), - .I1(p_13_out[0]), - .I2(p_13_out[1]), - .I3(p_13_out[3]), + (.I0(\gcc0.gc0.count_d1_reg[7]_0 [0]), + .I1(\gcc0.gc0.count_d1_reg[7]_0 [1]), + .I2(\gcc0.gc0.count_d1_reg[7]_0 [2]), + .I3(\gcc0.gc0.count_d1_reg[7]_0 [3]), .O(plusOp__2[3])); - (* SOFT_HLUTNM = "soft_lutpair13" *) + (* SOFT_HLUTNM = "soft_lutpair14" *) LUT5 #( - .INIT(32'h7FFF8000)) + .INIT(32'h6AAAAAAA)) \gcc0.gc0.count[4]_i_1__0 - (.I0(p_13_out[3]), - .I1(p_13_out[1]), - .I2(p_13_out[0]), - .I3(p_13_out[2]), - .I4(p_13_out[4]), + (.I0(\gcc0.gc0.count_d1_reg[7]_0 [4]), + .I1(\gcc0.gc0.count_d1_reg[7]_0 [0]), + .I2(\gcc0.gc0.count_d1_reg[7]_0 [1]), + .I3(\gcc0.gc0.count_d1_reg[7]_0 [2]), + .I4(\gcc0.gc0.count_d1_reg[7]_0 [3]), .O(plusOp__2[4])); LUT6 #( - .INIT(64'h7FFFFFFF80000000)) + .INIT(64'h6AAAAAAAAAAAAAAA)) \gcc0.gc0.count[5]_i_1 - (.I0(p_13_out[4]), - .I1(p_13_out[2]), - .I2(p_13_out[0]), - .I3(p_13_out[1]), - .I4(p_13_out[3]), - .I5(p_13_out[5]), + (.I0(\gcc0.gc0.count_d1_reg[7]_0 [5]), + .I1(\gcc0.gc0.count_d1_reg[7]_0 [3]), + .I2(\gcc0.gc0.count_d1_reg[7]_0 [2]), + .I3(\gcc0.gc0.count_d1_reg[7]_0 [1]), + .I4(\gcc0.gc0.count_d1_reg[7]_0 [0]), + .I5(\gcc0.gc0.count_d1_reg[7]_0 [4]), .O(plusOp__2[5])); - LUT3 #( - .INIT(8'h78)) + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT4 #( + .INIT(16'h6AAA)) \gcc0.gc0.count[6]_i_1 - (.I0(p_13_out[5]), - .I1(\gcc0.gc0.count[8]_i_2_n_0 ), - .I2(p_13_out[6]), + (.I0(\gcc0.gc0.count_d1_reg[7]_0 [6]), + .I1(\gcc0.gc0.count_d1_reg[7]_0 [4]), + .I2(\gcc0.gc0.count[8]_i_2_n_0 ), + .I3(\gcc0.gc0.count_d1_reg[7]_0 [5]), .O(plusOp__2[6])); - (* SOFT_HLUTNM = "soft_lutpair12" *) - LUT4 #( - .INIT(16'h7F80)) + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT5 #( + .INIT(32'h6AAAAAAA)) \gcc0.gc0.count[7]_i_1 - (.I0(\gcc0.gc0.count[8]_i_2_n_0 ), - .I1(p_13_out[5]), - .I2(p_13_out[6]), - .I3(p_13_out[7]), + (.I0(\gcc0.gc0.count_d1_reg[7]_0 [7]), + .I1(\gcc0.gc0.count_d1_reg[7]_0 [5]), + .I2(\gcc0.gc0.count[8]_i_2_n_0 ), + .I3(\gcc0.gc0.count_d1_reg[7]_0 [4]), + .I4(\gcc0.gc0.count_d1_reg[7]_0 [6]), .O(plusOp__2[7])); - (* SOFT_HLUTNM = "soft_lutpair12" *) - LUT5 #( - .INIT(32'h7FFF8000)) + LUT6 #( + .INIT(64'h6AAAAAAAAAAAAAAA)) \gcc0.gc0.count[8]_i_1 - (.I0(\gcc0.gc0.count[8]_i_2_n_0 ), - .I1(p_13_out[7]), - .I2(p_13_out[6]), - .I3(p_13_out[5]), - .I4(\gcc0.gc0.count_d1_reg[8]_0 ), + (.I0(p_13_out), + .I1(\gcc0.gc0.count_d1_reg[7]_0 [6]), + .I2(\gcc0.gc0.count_d1_reg[7]_0 [4]), + .I3(\gcc0.gc0.count[8]_i_2_n_0 ), + .I4(\gcc0.gc0.count_d1_reg[7]_0 [5]), + .I5(\gcc0.gc0.count_d1_reg[7]_0 [7]), .O(plusOp__2[8])); - (* SOFT_HLUTNM = "soft_lutpair13" *) - LUT5 #( - .INIT(32'h80000000)) + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT4 #( + .INIT(16'h8000)) \gcc0.gc0.count[8]_i_2 - (.I0(p_13_out[3]), - .I1(p_13_out[1]), - .I2(p_13_out[0]), - .I3(p_13_out[2]), - .I4(p_13_out[4]), + (.I0(\gcc0.gc0.count_d1_reg[7]_0 [3]), + .I1(\gcc0.gc0.count_d1_reg[7]_0 [2]), + .I2(\gcc0.gc0.count_d1_reg[7]_0 [1]), + .I3(\gcc0.gc0.count_d1_reg[7]_0 [0]), .O(\gcc0.gc0.count[8]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gcc0.gc0.count_d1_reg[0] (.C(s_aclk), .CE(E), - .D(p_13_out[0]), + .D(\gcc0.gc0.count_d1_reg[7]_0 [0]), .Q(Q[0]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( @@ -10064,7 +10243,7 @@ module Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr__parameterized0 \gcc0.gc0.count_d1_reg[1] (.C(s_aclk), .CE(E), - .D(p_13_out[1]), + .D(\gcc0.gc0.count_d1_reg[7]_0 [1]), .Q(Q[1]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( @@ -10072,7 +10251,7 @@ module Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr__parameterized0 \gcc0.gc0.count_d1_reg[2] (.C(s_aclk), .CE(E), - .D(p_13_out[2]), + .D(\gcc0.gc0.count_d1_reg[7]_0 [2]), .Q(Q[2]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( @@ -10080,7 +10259,7 @@ module Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr__parameterized0 \gcc0.gc0.count_d1_reg[3] (.C(s_aclk), .CE(E), - .D(p_13_out[3]), + .D(\gcc0.gc0.count_d1_reg[7]_0 [3]), .Q(Q[3]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( @@ -10088,7 +10267,7 @@ module Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr__parameterized0 \gcc0.gc0.count_d1_reg[4] (.C(s_aclk), .CE(E), - .D(p_13_out[4]), + .D(\gcc0.gc0.count_d1_reg[7]_0 [4]), .Q(Q[4]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( @@ -10096,7 +10275,7 @@ module Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr__parameterized0 \gcc0.gc0.count_d1_reg[5] (.C(s_aclk), .CE(E), - .D(p_13_out[5]), + .D(\gcc0.gc0.count_d1_reg[7]_0 [5]), .Q(Q[5]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( @@ -10104,7 +10283,7 @@ module Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr__parameterized0 \gcc0.gc0.count_d1_reg[6] (.C(s_aclk), .CE(E), - .D(p_13_out[6]), + .D(\gcc0.gc0.count_d1_reg[7]_0 [6]), .Q(Q[6]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( @@ -10112,7 +10291,7 @@ module Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr__parameterized0 \gcc0.gc0.count_d1_reg[7] (.C(s_aclk), .CE(E), - .D(p_13_out[7]), + .D(\gcc0.gc0.count_d1_reg[7]_0 [7]), .Q(Q[7]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( @@ -10120,7 +10299,7 @@ module Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr__parameterized0 \gcc0.gc0.count_d1_reg[8] (.C(s_aclk), .CE(E), - .D(\gcc0.gc0.count_d1_reg[8]_0 ), + .D(p_13_out), .Q(Q[8]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDSE #( @@ -10129,7 +10308,7 @@ module Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr__parameterized0 (.C(s_aclk), .CE(E), .D(plusOp__2[0]), - .Q(p_13_out[0]), + .Q(\gcc0.gc0.count_d1_reg[7]_0 [0]), .S(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( .INIT(1'b0)) @@ -10137,7 +10316,7 @@ module Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr__parameterized0 (.C(s_aclk), .CE(E), .D(plusOp__2[1]), - .Q(p_13_out[1]), + .Q(\gcc0.gc0.count_d1_reg[7]_0 [1]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( .INIT(1'b0)) @@ -10145,7 +10324,7 @@ module Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr__parameterized0 (.C(s_aclk), .CE(E), .D(plusOp__2[2]), - .Q(p_13_out[2]), + .Q(\gcc0.gc0.count_d1_reg[7]_0 [2]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( .INIT(1'b0)) @@ -10153,7 +10332,7 @@ module Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr__parameterized0 (.C(s_aclk), .CE(E), .D(plusOp__2[3]), - .Q(p_13_out[3]), + .Q(\gcc0.gc0.count_d1_reg[7]_0 [3]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( .INIT(1'b0)) @@ -10161,7 +10340,7 @@ module Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr__parameterized0 (.C(s_aclk), .CE(E), .D(plusOp__2[4]), - .Q(p_13_out[4]), + .Q(\gcc0.gc0.count_d1_reg[7]_0 [4]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( .INIT(1'b0)) @@ -10169,7 +10348,7 @@ module Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr__parameterized0 (.C(s_aclk), .CE(E), .D(plusOp__2[5]), - .Q(p_13_out[5]), + .Q(\gcc0.gc0.count_d1_reg[7]_0 [5]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( .INIT(1'b0)) @@ -10177,7 +10356,7 @@ module Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr__parameterized0 (.C(s_aclk), .CE(E), .D(plusOp__2[6]), - .Q(p_13_out[6]), + .Q(\gcc0.gc0.count_d1_reg[7]_0 [6]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( .INIT(1'b0)) @@ -10185,7 +10364,7 @@ module Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr__parameterized0 (.C(s_aclk), .CE(E), .D(plusOp__2[7]), - .Q(p_13_out[7]), + .Q(\gcc0.gc0.count_d1_reg[7]_0 [7]), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); FDRE #( .INIT(1'b0)) @@ -10193,16 +10372,8 @@ module Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr__parameterized0 (.C(s_aclk), .CE(E), .D(plusOp__2[8]), - .Q(\gcc0.gc0.count_d1_reg[8]_0 ), + .Q(p_13_out), .R(\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg )); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[0].gm1.m1_i_1 - (.I0(Q[1]), - .I1(\gc0.count_d1_reg[7] [1]), - .I2(Q[0]), - .I3(\gc0.count_d1_reg[7] [0]), - .O(ram_full_i_reg_2)); LUT4 #( .INIT(16'h9009)) \gmux.gm[0].gm1.m1_i_1__0 @@ -10210,163 +10381,86 @@ module Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr__parameterized0 .I1(\gc0.count_reg[7] [0]), .I2(Q[1]), .I3(\gc0.count_reg[7] [1]), - .O(ram_empty_i_reg_2)); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[0].gm1.m1_i_1__1 - (.I0(p_13_out[1]), - .I1(\gc0.count_d1_reg[7] [1]), - .I2(p_13_out[0]), - .I3(\gc0.count_d1_reg[7] [0]), - .O(ram_full_i_reg_6)); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[0].gm1.m1_i_1__2 - (.I0(Q[1]), - .I1(\gc0.count_d1_reg[7] [1]), - .I2(Q[0]), - .I3(\gc0.count_d1_reg[7] [0]), - .O(ram_empty_i_reg_3)); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[1].gms.ms_i_1 - (.I0(Q[2]), - .I1(\gc0.count_d1_reg[7] [2]), - .I2(Q[3]), - .I3(\gc0.count_d1_reg[7] [3]), - .O(ram_full_i_reg_1)); + .O(v1_reg[0])); LUT4 #( .INIT(16'h9009)) \gmux.gm[1].gms.ms_i_1__0 - (.I0(Q[3]), - .I1(\gc0.count_reg[7] [3]), - .I2(Q[2]), - .I3(\gc0.count_reg[7] [2]), - .O(ram_empty_i_reg_1)); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[1].gms.ms_i_1__1 - (.I0(p_13_out[3]), - .I1(\gc0.count_d1_reg[7] [3]), - .I2(p_13_out[2]), - .I3(\gc0.count_d1_reg[7] [2]), - .O(ram_full_i_reg_5)); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[1].gms.ms_i_1__2 (.I0(Q[2]), - .I1(\gc0.count_d1_reg[7] [2]), + .I1(\gc0.count_reg[7] [2]), .I2(Q[3]), - .I3(\gc0.count_d1_reg[7] [3]), - .O(ram_empty_i_reg_4)); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[2].gms.ms_i_1 - (.I0(Q[5]), - .I1(\gc0.count_d1_reg[7] [5]), - .I2(Q[4]), - .I3(\gc0.count_d1_reg[7] [4]), - .O(ram_full_i_reg_0)); + .I3(\gc0.count_reg[7] [3]), + .O(v1_reg[1])); LUT4 #( .INIT(16'h9009)) \gmux.gm[2].gms.ms_i_1__0 - (.I0(Q[4]), - .I1(\gc0.count_reg[7] [4]), - .I2(Q[5]), - .I3(\gc0.count_reg[7] [5]), - .O(ram_empty_i_reg_0)); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[2].gms.ms_i_1__1 - (.I0(p_13_out[5]), - .I1(\gc0.count_d1_reg[7] [5]), - .I2(p_13_out[4]), - .I3(\gc0.count_d1_reg[7] [4]), - .O(ram_full_i_reg_4)); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[2].gms.ms_i_1__2 (.I0(Q[5]), - .I1(\gc0.count_d1_reg[7] [5]), + .I1(\gc0.count_reg[7] [5]), .I2(Q[4]), - .I3(\gc0.count_d1_reg[7] [4]), - .O(ram_empty_i_reg_5)); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[3].gms.ms_i_1 - (.I0(Q[6]), - .I1(\gc0.count_d1_reg[7] [6]), - .I2(Q[7]), - .I3(\gc0.count_d1_reg[7] [7]), - .O(ram_full_i_reg)); + .I3(\gc0.count_reg[7] [4]), + .O(v1_reg[2])); LUT4 #( .INIT(16'h9009)) \gmux.gm[3].gms.ms_i_1__0 - (.I0(Q[6]), - .I1(\gc0.count_reg[7] [6]), - .I2(Q[7]), - .I3(\gc0.count_reg[7] [7]), + (.I0(Q[7]), + .I1(\gc0.count_reg[7] [7]), + .I2(Q[6]), + .I3(\gc0.count_reg[7] [6]), + .O(v1_reg[3])); + LUT2 #( + .INIT(4'h9)) + \gmux.gm[4].gms.ms_i_1__0 + (.I0(Q[8]), + .I1(\gc0.count_d1_reg[8] ), + .O(ram_full_i_reg)); + LUT2 #( + .INIT(4'h9)) + \gmux.gm[4].gms.ms_i_1__1 + (.I0(p_13_out), + .I1(\gc0.count_d1_reg[8] ), + .O(ram_full_i_reg_0)); + LUT2 #( + .INIT(4'h9)) + \gmux.gm[4].gms.ms_i_1__2 + (.I0(Q[8]), + .I1(\gc0.count_d1_reg[8] ), .O(ram_empty_i_reg)); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[3].gms.ms_i_1__1 - (.I0(p_13_out[7]), - .I1(\gc0.count_d1_reg[7] [7]), - .I2(p_13_out[6]), - .I3(\gc0.count_d1_reg[7] [6]), - .O(ram_full_i_reg_3)); - LUT4 #( - .INIT(16'h9009)) - \gmux.gm[3].gms.ms_i_1__2 - (.I0(Q[6]), - .I1(\gc0.count_d1_reg[7] [6]), - .I2(Q[7]), - .I3(\gc0.count_d1_reg[7] [7]), - .O(ram_empty_i_reg_6)); endmodule module Arty_Z7_20_s00_data_fifo_0_wr_logic - (s_axi_arready, + (out, + E, + s_axi_arready, Q, ram_empty_fb_i_reg, - E, - \gpr1.dout_i_reg[5] , + \gpr1.dout_i_reg[1] , + ram_full_comb, s_aclk, - out, - ram_empty_fb_i_reg_0, - \grstd1.grst_full.grst_f.rst_d3_reg , - \gc0.count_d1_reg[2] , - \gc0.count_d1_reg[1] , - \gc0.count_d1_reg[2]_0 , + \grstd1.grst_full.grst_f.rst_d2_reg , s_axi_arvalid, + \gc0.count_reg[4] , AR); + output out; + output [0:0]E; output s_axi_arready; - output [2:0]Q; + output [4:0]Q; output ram_empty_fb_i_reg; - output [0:0]E; - output [4:0]\gpr1.dout_i_reg[5] ; + output [4:0]\gpr1.dout_i_reg[1] ; + input ram_full_comb; input s_aclk; - input out; - input ram_empty_fb_i_reg_0; - input \grstd1.grst_full.grst_f.rst_d3_reg ; - input \gc0.count_d1_reg[2] ; - input [1:0]\gc0.count_d1_reg[1] ; - input \gc0.count_d1_reg[2]_0 ; + input \grstd1.grst_full.grst_f.rst_d2_reg ; input s_axi_arvalid; + input [4:0]\gc0.count_reg[4] ; input [0:0]AR; wire [0:0]AR; wire [0:0]E; - wire [2:0]Q; - wire [1:0]\gc0.count_d1_reg[1] ; - wire \gc0.count_d1_reg[2] ; - wire \gc0.count_d1_reg[2]_0 ; - wire [4:0]\gpr1.dout_i_reg[5] ; - wire \grstd1.grst_full.grst_f.rst_d3_reg ; - wire \gwss.wsts_n_0 ; + wire [4:0]Q; + wire [4:0]\gc0.count_reg[4] ; + wire [4:0]\gpr1.dout_i_reg[1] ; + wire \grstd1.grst_full.grst_f.rst_d2_reg ; + wire \gwss.wsts_n_3 ; wire out; wire ram_empty_fb_i_reg; - wire ram_empty_fb_i_reg_0; wire ram_full_comb; wire s_aclk; wire s_axi_arready; @@ -10374,9 +10468,11 @@ module Arty_Z7_20_s00_data_fifo_0_wr_logic Arty_Z7_20_s00_data_fifo_0_wr_status_flags_ss \gwss.wsts (.E(E), - .\grstd1.grst_full.grst_f.rst_d2_reg (out), - .out(\gwss.wsts_n_0 ), - .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .\gc0.count_reg[3] (\gc0.count_reg[4] [3]), + .\gcc0.gc0.count_d1_reg[3] (\gpr1.dout_i_reg[1] [3]), + .\grstd1.grst_full.grst_f.rst_d2_reg (\grstd1.grst_full.grst_f.rst_d2_reg ), + .out(out), + .ram_empty_fb_i_reg(\gwss.wsts_n_3 ), .ram_full_comb(ram_full_comb), .s_aclk(s_aclk), .s_axi_arready(s_axi_arready), @@ -10385,15 +10481,10 @@ module Arty_Z7_20_s00_data_fifo_0_wr_logic (.AR(AR), .E(E), .Q(Q), - .\gc0.count_d1_reg[1] (\gc0.count_d1_reg[1] ), - .\gc0.count_d1_reg[2] (\gc0.count_d1_reg[2] ), - .\gc0.count_d1_reg[2]_0 (\gc0.count_d1_reg[2]_0 ), - .\gpr1.dout_i_reg[5] (\gpr1.dout_i_reg[5] ), - .\grstd1.grst_full.grst_f.rst_d3_reg (\grstd1.grst_full.grst_f.rst_d3_reg ), - .out(\gwss.wsts_n_0 ), - .ram_empty_fb_i_reg(ram_empty_fb_i_reg_0), - .ram_full_comb(ram_full_comb), - .ram_full_i_reg(ram_empty_fb_i_reg), + .\gc0.count_reg[4] ({\gc0.count_reg[4] [4],\gc0.count_reg[4] [2:0]}), + .\gpr1.dout_i_reg[1] (\gpr1.dout_i_reg[1] ), + .ram_empty_fb_i_reg(ram_empty_fb_i_reg), + .ram_full_fb_i_reg(\gwss.wsts_n_3 ), .s_aclk(s_aclk)); endmodule @@ -10401,58 +10492,44 @@ endmodule module Arty_Z7_20_s00_data_fifo_0_wr_logic__parameterized0 (out, Q, + \gcc0.gc0.count_d1_reg[7] , ram_empty_i_reg, - ram_empty_i_reg_0, - ram_empty_i_reg_1, - ram_empty_i_reg_2, - \gcc0.gc0.count_d1_reg[8] , - ram_empty_i_reg_3, - ram_empty_i_reg_4, - ram_empty_i_reg_5, - ram_empty_i_reg_6, + v1_reg, E, m_axi_rready, - \gc0.count_d1_reg[8] , - \gc0.count_d1_reg[8]_0 , + v1_reg_0, + v1_reg_1, \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg , s_aclk, \grstd1.grst_full.grst_f.rst_d2_reg , - \gc0.count_d1_reg[7] , - \gc0.count_reg[7] , + \gc0.count_d1_reg[8] , \grstd1.grst_full.grst_f.rst_d3_reg , + m_axi_rvalid, ram_empty_fb_i_reg, - m_axi_rvalid); + \gc0.count_reg[7] ); output out; output [8:0]Q; + output [7:0]\gcc0.gc0.count_d1_reg[7] ; output ram_empty_i_reg; - output ram_empty_i_reg_0; - output ram_empty_i_reg_1; - output ram_empty_i_reg_2; - output [0:0]\gcc0.gc0.count_d1_reg[8] ; - output ram_empty_i_reg_3; - output ram_empty_i_reg_4; - output ram_empty_i_reg_5; - output ram_empty_i_reg_6; + output [3:0]v1_reg; output [0:0]E; output m_axi_rready; - input \gc0.count_d1_reg[8] ; - input \gc0.count_d1_reg[8]_0 ; + input [3:0]v1_reg_0; + input [3:0]v1_reg_1; input \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg ; input s_aclk; input \grstd1.grst_full.grst_f.rst_d2_reg ; - input [7:0]\gc0.count_d1_reg[7] ; - input [7:0]\gc0.count_reg[7] ; + input [0:0]\gc0.count_d1_reg[8] ; input \grstd1.grst_full.grst_f.rst_d3_reg ; - input ram_empty_fb_i_reg; input m_axi_rvalid; + input ram_empty_fb_i_reg; + input [7:0]\gc0.count_reg[7] ; wire [0:0]E; wire [8:0]Q; - wire [7:0]\gc0.count_d1_reg[7] ; - wire \gc0.count_d1_reg[8] ; - wire \gc0.count_d1_reg[8]_0 ; + wire [0:0]\gc0.count_d1_reg[8] ; wire [7:0]\gc0.count_reg[7] ; - wire [0:0]\gcc0.gc0.count_d1_reg[8] ; + wire [7:0]\gcc0.gc0.count_d1_reg[7] ; wire \grstd1.grst_full.grst_f.rst_d2_reg ; wire \grstd1.grst_full.grst_f.rst_d3_reg ; wire m_axi_rready; @@ -10461,35 +10538,17 @@ module Arty_Z7_20_s00_data_fifo_0_wr_logic__parameterized0 wire out; wire ram_empty_fb_i_reg; wire ram_empty_i_reg; - wire ram_empty_i_reg_0; - wire ram_empty_i_reg_1; - wire ram_empty_i_reg_2; - wire ram_empty_i_reg_3; - wire ram_empty_i_reg_4; - wire ram_empty_i_reg_5; - wire ram_empty_i_reg_6; wire s_aclk; + wire [3:0]v1_reg; + wire [3:0]v1_reg_0; + wire [3:0]v1_reg_1; wire wpntr_n_0; wire wpntr_n_10; - wire wpntr_n_11; - wire wpntr_n_12; - wire wpntr_n_17; - wire wpntr_n_18; - wire wpntr_n_19; - wire wpntr_n_20; Arty_Z7_20_s00_data_fifo_0_wr_status_flags_ss__parameterized0 \gwss.wsts (.E(E), - .\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ), - .\gc0.count_d1_reg[8]_0 (\gc0.count_d1_reg[8]_0 ), - .\gcc0.gc0.count_d1_reg[1] (wpntr_n_12), - .\gcc0.gc0.count_d1_reg[2] (wpntr_n_11), - .\gcc0.gc0.count_d1_reg[5] (wpntr_n_10), - .\gcc0.gc0.count_d1_reg[6] (wpntr_n_0), - .\gcc0.gc0.count_reg[1] (wpntr_n_20), - .\gcc0.gc0.count_reg[3] (wpntr_n_19), - .\gcc0.gc0.count_reg[5] (wpntr_n_18), - .\gcc0.gc0.count_reg[7] (wpntr_n_17), + .\gcc0.gc0.count_d1_reg[8] (wpntr_n_0), + .\gcc0.gc0.count_reg[8] (wpntr_n_10), .\grstd1.grst_full.grst_f.rst_d2_reg (\grstd1.grst_full.grst_f.rst_d2_reg ), .\grstd1.grst_full.grst_f.rst_d3_reg (\grstd1.grst_full.grst_f.rst_d3_reg ), .m_axi_rready(m_axi_rready), @@ -10497,52 +10556,48 @@ module Arty_Z7_20_s00_data_fifo_0_wr_logic__parameterized0 .\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg (\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg ), .out(out), .ram_empty_fb_i_reg(ram_empty_fb_i_reg), - .s_aclk(s_aclk)); + .s_aclk(s_aclk), + .v1_reg_0(v1_reg_0), + .v1_reg_1(v1_reg_1)); Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr__parameterized0 wpntr (.E(E), .Q(Q), - .\gc0.count_d1_reg[7] (\gc0.count_d1_reg[7] ), + .\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ), .\gc0.count_reg[7] (\gc0.count_reg[7] ), - .\gcc0.gc0.count_d1_reg[8]_0 (\gcc0.gc0.count_d1_reg[8] ), + .\gcc0.gc0.count_d1_reg[7]_0 (\gcc0.gc0.count_d1_reg[7] ), .\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg (\ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg ), .ram_empty_i_reg(ram_empty_i_reg), - .ram_empty_i_reg_0(ram_empty_i_reg_0), - .ram_empty_i_reg_1(ram_empty_i_reg_1), - .ram_empty_i_reg_2(ram_empty_i_reg_2), - .ram_empty_i_reg_3(ram_empty_i_reg_3), - .ram_empty_i_reg_4(ram_empty_i_reg_4), - .ram_empty_i_reg_5(ram_empty_i_reg_5), - .ram_empty_i_reg_6(ram_empty_i_reg_6), .ram_full_i_reg(wpntr_n_0), .ram_full_i_reg_0(wpntr_n_10), - .ram_full_i_reg_1(wpntr_n_11), - .ram_full_i_reg_2(wpntr_n_12), - .ram_full_i_reg_3(wpntr_n_17), - .ram_full_i_reg_4(wpntr_n_18), - .ram_full_i_reg_5(wpntr_n_19), - .ram_full_i_reg_6(wpntr_n_20), - .s_aclk(s_aclk)); + .s_aclk(s_aclk), + .v1_reg(v1_reg)); endmodule module Arty_Z7_20_s00_data_fifo_0_wr_status_flags_ss (out, - s_axi_arready, E, + s_axi_arready, ram_empty_fb_i_reg, ram_full_comb, s_aclk, \grstd1.grst_full.grst_f.rst_d2_reg , - s_axi_arvalid); + s_axi_arvalid, + \gcc0.gc0.count_d1_reg[3] , + \gc0.count_reg[3] ); output out; - output s_axi_arready; output [0:0]E; + output s_axi_arready; output ram_empty_fb_i_reg; input ram_full_comb; input s_aclk; input \grstd1.grst_full.grst_f.rst_d2_reg ; input s_axi_arvalid; + input [0:0]\gcc0.gc0.count_d1_reg[3] ; + input [0:0]\gc0.count_reg[3] ; wire [0:0]E; + wire [0:0]\gc0.count_reg[3] ; + wire [0:0]\gcc0.gc0.count_d1_reg[3] ; wire \grstd1.grst_full.grst_f.rst_d2_reg ; (* DONT_TOUCH *) wire ram_afull_fb; (* DONT_TOUCH *) wire ram_afull_i; @@ -10556,11 +10611,11 @@ module Arty_Z7_20_s00_data_fifo_0_wr_status_flags_ss assign out = ram_full_fb_i; LUT3 #( - .INIT(8'h10)) + .INIT(8'h04)) \gcc0.gc0.count_d1[4]_i_1 - (.I0(ram_full_fb_i), - .I1(ram_full_i), - .I2(s_axi_arvalid), + (.I0(ram_full_i), + .I1(s_axi_arvalid), + .I2(ram_full_fb_i), .O(E)); LUT1 #( .INIT(2'h2)) @@ -10572,12 +10627,14 @@ module Arty_Z7_20_s00_data_fifo_0_wr_status_flags_ss i_1 (.I0(1'b1), .O(ram_afull_fb)); - LUT3 #( - .INIT(8'hFD)) - ram_empty_fb_i_i_4 - (.I0(s_axi_arvalid), - .I1(ram_full_i), - .I2(ram_full_fb_i), + LUT5 #( + .INIT(32'h04FFFF04)) + ram_empty_fb_i_i_6 + (.I0(ram_full_fb_i), + .I1(s_axi_arvalid), + .I2(ram_full_i), + .I3(\gcc0.gc0.count_d1_reg[3] ), + .I4(\gc0.count_reg[3] ), .O(ram_empty_fb_i_reg)); (* DONT_TOUCH *) (* KEEP = "yes" *) @@ -10613,54 +10670,34 @@ module Arty_Z7_20_s00_data_fifo_0_wr_status_flags_ss__parameterized0 (out, E, m_axi_rready, - \gcc0.gc0.count_d1_reg[1] , - \gcc0.gc0.count_d1_reg[2] , - \gcc0.gc0.count_d1_reg[5] , - \gcc0.gc0.count_d1_reg[6] , - \gc0.count_d1_reg[8] , - \gcc0.gc0.count_reg[1] , - \gcc0.gc0.count_reg[3] , - \gcc0.gc0.count_reg[5] , - \gcc0.gc0.count_reg[7] , - \gc0.count_d1_reg[8]_0 , + v1_reg_0, + \gcc0.gc0.count_d1_reg[8] , + v1_reg_1, + \gcc0.gc0.count_reg[8] , \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg , s_aclk, \grstd1.grst_full.grst_f.rst_d2_reg , \grstd1.grst_full.grst_f.rst_d3_reg , - ram_empty_fb_i_reg, - m_axi_rvalid); + m_axi_rvalid, + ram_empty_fb_i_reg); output out; output [0:0]E; output m_axi_rready; - input \gcc0.gc0.count_d1_reg[1] ; - input \gcc0.gc0.count_d1_reg[2] ; - input \gcc0.gc0.count_d1_reg[5] ; - input \gcc0.gc0.count_d1_reg[6] ; - input \gc0.count_d1_reg[8] ; - input \gcc0.gc0.count_reg[1] ; - input \gcc0.gc0.count_reg[3] ; - input \gcc0.gc0.count_reg[5] ; - input \gcc0.gc0.count_reg[7] ; - input \gc0.count_d1_reg[8]_0 ; + input [3:0]v1_reg_0; + input \gcc0.gc0.count_d1_reg[8] ; + input [3:0]v1_reg_1; + input \gcc0.gc0.count_reg[8] ; input \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg ; input s_aclk; input \grstd1.grst_full.grst_f.rst_d2_reg ; input \grstd1.grst_full.grst_f.rst_d3_reg ; - input ram_empty_fb_i_reg; input m_axi_rvalid; + input ram_empty_fb_i_reg; wire [0:0]E; wire comp1; - wire \gc0.count_d1_reg[8] ; - wire \gc0.count_d1_reg[8]_0 ; - wire \gcc0.gc0.count_d1_reg[1] ; - wire \gcc0.gc0.count_d1_reg[2] ; - wire \gcc0.gc0.count_d1_reg[5] ; - wire \gcc0.gc0.count_d1_reg[6] ; - wire \gcc0.gc0.count_reg[1] ; - wire \gcc0.gc0.count_reg[3] ; - wire \gcc0.gc0.count_reg[5] ; - wire \gcc0.gc0.count_reg[7] ; + wire \gcc0.gc0.count_d1_reg[8] ; + wire \gcc0.gc0.count_reg[8] ; wire \grstd1.grst_full.grst_f.rst_d2_reg ; wire \grstd1.grst_full.grst_f.rst_d3_reg ; wire m_axi_rready; @@ -10673,6 +10710,8 @@ module Arty_Z7_20_s00_data_fifo_0_wr_status_flags_ss__parameterized0 (* DONT_TOUCH *) wire ram_full_fb_i; (* DONT_TOUCH *) wire ram_full_i; wire s_aclk; + wire [3:0]v1_reg_0; + wire [3:0]v1_reg_1; assign out = ram_full_fb_i; LUT2 #( @@ -10683,23 +10722,17 @@ module Arty_Z7_20_s00_data_fifo_0_wr_status_flags_ss__parameterized0 .O(E)); Arty_Z7_20_s00_data_fifo_0_compare__parameterized2 c0 (.comp1(comp1), - .\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ), - .\gcc0.gc0.count_d1_reg[1] (\gcc0.gc0.count_d1_reg[1] ), - .\gcc0.gc0.count_d1_reg[2] (\gcc0.gc0.count_d1_reg[2] ), - .\gcc0.gc0.count_d1_reg[5] (\gcc0.gc0.count_d1_reg[5] ), - .\gcc0.gc0.count_d1_reg[6] (\gcc0.gc0.count_d1_reg[6] ), + .\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ), .\grstd1.grst_full.grst_f.rst_d3_reg (\grstd1.grst_full.grst_f.rst_d3_reg ), .m_axi_rvalid(m_axi_rvalid), .out(ram_full_fb_i), .ram_empty_fb_i_reg(ram_empty_fb_i_reg), - .ram_full_comb(ram_full_comb)); + .ram_full_comb(ram_full_comb), + .v1_reg_0(v1_reg_0)); Arty_Z7_20_s00_data_fifo_0_compare__parameterized3 c1 (.comp1(comp1), - .\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8]_0 ), - .\gcc0.gc0.count_reg[1] (\gcc0.gc0.count_reg[1] ), - .\gcc0.gc0.count_reg[3] (\gcc0.gc0.count_reg[3] ), - .\gcc0.gc0.count_reg[5] (\gcc0.gc0.count_reg[5] ), - .\gcc0.gc0.count_reg[7] (\gcc0.gc0.count_reg[7] )); + .\gcc0.gc0.count_reg[8] (\gcc0.gc0.count_reg[8] ), + .v1_reg_1(v1_reg_1)); LUT1 #( .INIT(2'h2)) i_0 diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0_sim_netlist.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0_sim_netlist.vhdl index f0e4069..c60804f 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0_sim_netlist.vhdl +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0_sim_netlist.vhdl @@ -1,7 +1,7 @@ -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 --- Date : Fri Feb 24 16:02:52 2017 +-- Date : Sat Mar 04 18:59:58 2017 -- Host : WK73 running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim -rename_top Arty_Z7_20_s00_data_fifo_0 -prefix -- Arty_Z7_20_s00_data_fifo_0_ Arty_Z7_20_s00_data_fifo_0_sim_netlist.vhdl @@ -298,11 +298,11 @@ use UNISIM.VCOMPONENTS.ALL; entity \Arty_Z7_20_s00_data_fifo_0_compare__parameterized0\ is port ( comp0 : out STD_LOGIC; - \gcc0.gc0.count_d1_reg[1]\ : in STD_LOGIC; - \gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC; - \gcc0.gc0.count_d1_reg[5]\ : in STD_LOGIC; - \gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC; - \gc0.count_d1_reg[8]\ : in STD_LOGIC + \gc0.count_d1_reg[0]\ : in STD_LOGIC; + \gc0.count_d1_reg[2]\ : in STD_LOGIC; + \gc0.count_d1_reg[5]\ : in STD_LOGIC; + \gc0.count_d1_reg[7]\ : in STD_LOGIC; + \gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \Arty_Z7_20_s00_data_fifo_0_compare__parameterized0\ : entity is "compare"; @@ -335,10 +335,10 @@ begin CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0), - S(3) => \gcc0.gc0.count_d1_reg[6]\, - S(2) => \gcc0.gc0.count_d1_reg[5]\, - S(1) => \gcc0.gc0.count_d1_reg[2]\, - S(0) => \gcc0.gc0.count_d1_reg[1]\ + S(3) => \gc0.count_d1_reg[7]\, + S(2) => \gc0.count_d1_reg[5]\, + S(1) => \gc0.count_d1_reg[2]\, + S(0) => \gc0.count_d1_reg[0]\ ); \gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4 port map ( @@ -350,7 +350,7 @@ begin DI(0) => '0', O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1), - S(0) => \gc0.count_d1_reg[8]\ + S(0) => \gcc0.gc0.count_d1_reg[8]\ ); end STRUCTURE; library IEEE; @@ -360,15 +360,12 @@ use UNISIM.VCOMPONENTS.ALL; entity \Arty_Z7_20_s00_data_fifo_0_compare__parameterized1\ is port ( ram_empty_i_reg : out STD_LOGIC; - \gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC; - \gcc0.gc0.count_d1_reg[3]\ : in STD_LOGIC; - \gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC; - \gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC; + v1_reg_1 : in STD_LOGIC_VECTOR ( 3 downto 0 ); \gc0.count_reg[8]\ : in STD_LOGIC; + \gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC; + comp0 : in STD_LOGIC; ram_full_fb_i_reg : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; - \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC; - comp0 : in STD_LOGIC; \out\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; @@ -403,10 +400,7 @@ begin CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0), - S(3) => \gcc0.gc0.count_d1_reg[6]\, - S(2) => \gcc0.gc0.count_d1_reg[4]\, - S(1) => \gcc0.gc0.count_d1_reg[3]\, - S(0) => \gcc0.gc0.count_d1_reg[0]\ + S(3 downto 0) => v1_reg_1(3 downto 0) ); \gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4 port map ( @@ -422,14 +416,14 @@ begin ); \ram_empty_fb_i_i_1__0\: unisim.vcomponents.LUT6 generic map( - INIT => X"CFCFFFFF8A008A00" + INIT => X"FF0FFFFF22002222" ) port map ( I0 => comp1, - I1 => ram_full_fb_i_reg, - I2 => m_axi_rvalid, - I3 => \gpregsm1.curr_fwft_state_reg[0]\, - I4 => comp0, + I1 => \gpregsm1.curr_fwft_state_reg[1]\, + I2 => comp0, + I3 => ram_full_fb_i_reg, + I4 => m_axi_rvalid, I5 => \out\, O => ram_empty_i_reg ); @@ -441,16 +435,13 @@ use UNISIM.VCOMPONENTS.ALL; entity \Arty_Z7_20_s00_data_fifo_0_compare__parameterized2\ is port ( ram_full_comb : out STD_LOGIC; - \gcc0.gc0.count_d1_reg[1]\ : in STD_LOGIC; - \gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC; - \gcc0.gc0.count_d1_reg[5]\ : in STD_LOGIC; - \gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC; - \gc0.count_d1_reg[8]\ : in STD_LOGIC; + v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC; \grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC; - ram_empty_fb_i_reg : in STD_LOGIC; - comp1 : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; - \out\ : in STD_LOGIC + \out\ : in STD_LOGIC; + comp1 : in STD_LOGIC; + ram_empty_fb_i_reg : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \Arty_Z7_20_s00_data_fifo_0_compare__parameterized2\ : entity is "compare"; @@ -484,10 +475,7 @@ begin CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0), - S(3) => \gcc0.gc0.count_d1_reg[6]\, - S(2) => \gcc0.gc0.count_d1_reg[5]\, - S(1) => \gcc0.gc0.count_d1_reg[2]\, - S(0) => \gcc0.gc0.count_d1_reg[1]\ + S(3 downto 0) => v1_reg_0(3 downto 0) ); \gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4 port map ( @@ -499,19 +487,19 @@ begin DI(0) => '0', O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1), - S(0) => \gc0.count_d1_reg[8]\ + S(0) => \gcc0.gc0.count_d1_reg[8]\ ); \ram_full_fb_i_i_1__0\: unisim.vcomponents.LUT6 generic map( - INIT => X"31313131F0000000" + INIT => X"33F0330011001100" ) port map ( I0 => comp0, I1 => \grstd1.grst_full.grst_f.rst_d3_reg\, - I2 => ram_empty_fb_i_reg, - I3 => comp1, - I4 => m_axi_rvalid, - I5 => \out\, + I2 => m_axi_rvalid, + I3 => \out\, + I4 => comp1, + I5 => ram_empty_fb_i_reg, O => ram_full_comb ); end STRUCTURE; @@ -522,11 +510,8 @@ use UNISIM.VCOMPONENTS.ALL; entity \Arty_Z7_20_s00_data_fifo_0_compare__parameterized3\ is port ( comp1 : out STD_LOGIC; - \gcc0.gc0.count_reg[1]\ : in STD_LOGIC; - \gcc0.gc0.count_reg[3]\ : in STD_LOGIC; - \gcc0.gc0.count_reg[5]\ : in STD_LOGIC; - \gcc0.gc0.count_reg[7]\ : in STD_LOGIC; - \gc0.count_d1_reg[8]\ : in STD_LOGIC + v1_reg_1 : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \gcc0.gc0.count_reg[8]\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \Arty_Z7_20_s00_data_fifo_0_compare__parameterized3\ : entity is "compare"; @@ -559,10 +544,7 @@ begin CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0), - S(3) => \gcc0.gc0.count_reg[7]\, - S(2) => \gcc0.gc0.count_reg[5]\, - S(1) => \gcc0.gc0.count_reg[3]\, - S(0) => \gcc0.gc0.count_reg[1]\ + S(3 downto 0) => v1_reg_1(3 downto 0) ); \gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4 port map ( @@ -574,7 +556,7 @@ begin DI(0) => '0', O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1), - S(0) => \gc0.count_d1_reg[8]\ + S(0) => \gcc0.gc0.count_reg[8]\ ); end STRUCTURE; library IEEE; @@ -583,22 +565,18 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20_s00_data_fifo_0_dmem is port ( - dout_i : out STD_LOGIC_VECTOR ( 55 downto 0 ); + dout_i : out STD_LOGIC_VECTOR ( 62 downto 0 ); s_aclk : in STD_LOGIC; - ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); - UNCONN_IN : in STD_LOGIC_VECTOR ( 55 downto 0 ); + EN : in STD_LOGIC; + UNCONN_IN : in STD_LOGIC_VECTOR ( 62 downto 0 ); \gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); \gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); - \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ram_empty_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end Arty_Z7_20_s00_data_fifo_0_dmem; architecture STRUCTURE of Arty_Z7_20_s00_data_fifo_0_dmem is - signal RAM_reg_0_31_0_5_n_0 : STD_LOGIC; - signal RAM_reg_0_31_0_5_n_1 : STD_LOGIC; - signal RAM_reg_0_31_0_5_n_2 : STD_LOGIC; - signal RAM_reg_0_31_0_5_n_3 : STD_LOGIC; - signal p_0_out : STD_LOGIC_VECTOR ( 59 downto 4 ); + signal p_0_out : STD_LOGIC_VECTOR ( 62 downto 0 ); signal NLW_RAM_reg_0_31_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_RAM_reg_0_31_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_RAM_reg_0_31_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); @@ -608,6 +586,9 @@ architecture STRUCTURE of Arty_Z7_20_s00_data_fifo_0_dmem is signal NLW_RAM_reg_0_31_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_RAM_reg_0_31_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_RAM_reg_0_31_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_RAM_reg_0_31_60_62_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); + signal NLW_RAM_reg_0_31_60_62_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_RAM_reg_0_31_60_62_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_RAM_reg_0_31_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute METHODOLOGY_DRC_VIOS : string; attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_31_0_5 : label is ""; @@ -619,6 +600,7 @@ architecture STRUCTURE of Arty_Z7_20_s00_data_fifo_0_dmem is attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_31_42_47 : label is ""; attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_31_48_53 : label is ""; attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_31_54_59 : label is ""; + attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_31_60_62 : label is ""; attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_31_6_11 : label is ""; begin RAM_reg_0_31_0_5: unisim.vcomponents.RAM32M @@ -627,18 +609,16 @@ RAM_reg_0_31_0_5: unisim.vcomponents.RAM32M ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0), - DIA(1 downto 0) => B"00", - DIB(1 downto 0) => B"00", - DIC(1 downto 0) => UNCONN_IN(1 downto 0), + DIA(1 downto 0) => UNCONN_IN(1 downto 0), + DIB(1 downto 0) => UNCONN_IN(3 downto 2), + DIC(1 downto 0) => UNCONN_IN(5 downto 4), DID(1 downto 0) => B"00", - DOA(1) => RAM_reg_0_31_0_5_n_0, - DOA(0) => RAM_reg_0_31_0_5_n_1, - DOB(1) => RAM_reg_0_31_0_5_n_2, - DOB(0) => RAM_reg_0_31_0_5_n_3, + DOA(1 downto 0) => p_0_out(1 downto 0), + DOB(1 downto 0) => p_0_out(3 downto 2), DOC(1 downto 0) => p_0_out(5 downto 4), DOD(1 downto 0) => NLW_RAM_reg_0_31_0_5_DOD_UNCONNECTED(1 downto 0), WCLK => s_aclk, - WE => ram_full_fb_i_reg(0) + WE => EN ); RAM_reg_0_31_12_17: unisim.vcomponents.RAM32M port map ( @@ -646,16 +626,16 @@ RAM_reg_0_31_12_17: unisim.vcomponents.RAM32M ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0), - DIA(1 downto 0) => UNCONN_IN(9 downto 8), - DIB(1 downto 0) => UNCONN_IN(11 downto 10), - DIC(1 downto 0) => UNCONN_IN(13 downto 12), + DIA(1 downto 0) => UNCONN_IN(13 downto 12), + DIB(1 downto 0) => UNCONN_IN(15 downto 14), + DIC(1 downto 0) => UNCONN_IN(17 downto 16), DID(1 downto 0) => B"00", DOA(1 downto 0) => p_0_out(13 downto 12), DOB(1 downto 0) => p_0_out(15 downto 14), DOC(1 downto 0) => p_0_out(17 downto 16), DOD(1 downto 0) => NLW_RAM_reg_0_31_12_17_DOD_UNCONNECTED(1 downto 0), WCLK => s_aclk, - WE => ram_full_fb_i_reg(0) + WE => EN ); RAM_reg_0_31_18_23: unisim.vcomponents.RAM32M port map ( @@ -663,16 +643,16 @@ RAM_reg_0_31_18_23: unisim.vcomponents.RAM32M ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0), - DIA(1 downto 0) => UNCONN_IN(15 downto 14), - DIB(1 downto 0) => UNCONN_IN(17 downto 16), - DIC(1 downto 0) => UNCONN_IN(19 downto 18), + DIA(1 downto 0) => UNCONN_IN(19 downto 18), + DIB(1 downto 0) => UNCONN_IN(21 downto 20), + DIC(1 downto 0) => UNCONN_IN(23 downto 22), DID(1 downto 0) => B"00", DOA(1 downto 0) => p_0_out(19 downto 18), DOB(1 downto 0) => p_0_out(21 downto 20), DOC(1 downto 0) => p_0_out(23 downto 22), DOD(1 downto 0) => NLW_RAM_reg_0_31_18_23_DOD_UNCONNECTED(1 downto 0), WCLK => s_aclk, - WE => ram_full_fb_i_reg(0) + WE => EN ); RAM_reg_0_31_24_29: unisim.vcomponents.RAM32M port map ( @@ -680,16 +660,16 @@ RAM_reg_0_31_24_29: unisim.vcomponents.RAM32M ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0), - DIA(1 downto 0) => UNCONN_IN(21 downto 20), - DIB(1 downto 0) => UNCONN_IN(23 downto 22), - DIC(1 downto 0) => UNCONN_IN(25 downto 24), + DIA(1 downto 0) => UNCONN_IN(25 downto 24), + DIB(1 downto 0) => UNCONN_IN(27 downto 26), + DIC(1 downto 0) => UNCONN_IN(29 downto 28), DID(1 downto 0) => B"00", DOA(1 downto 0) => p_0_out(25 downto 24), DOB(1 downto 0) => p_0_out(27 downto 26), DOC(1 downto 0) => p_0_out(29 downto 28), DOD(1 downto 0) => NLW_RAM_reg_0_31_24_29_DOD_UNCONNECTED(1 downto 0), WCLK => s_aclk, - WE => ram_full_fb_i_reg(0) + WE => EN ); RAM_reg_0_31_30_35: unisim.vcomponents.RAM32M port map ( @@ -697,16 +677,16 @@ RAM_reg_0_31_30_35: unisim.vcomponents.RAM32M ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0), - DIA(1 downto 0) => UNCONN_IN(27 downto 26), - DIB(1 downto 0) => UNCONN_IN(29 downto 28), - DIC(1 downto 0) => UNCONN_IN(31 downto 30), + DIA(1 downto 0) => UNCONN_IN(31 downto 30), + DIB(1 downto 0) => UNCONN_IN(33 downto 32), + DIC(1 downto 0) => UNCONN_IN(35 downto 34), DID(1 downto 0) => B"00", DOA(1 downto 0) => p_0_out(31 downto 30), DOB(1 downto 0) => p_0_out(33 downto 32), DOC(1 downto 0) => p_0_out(35 downto 34), DOD(1 downto 0) => NLW_RAM_reg_0_31_30_35_DOD_UNCONNECTED(1 downto 0), WCLK => s_aclk, - WE => ram_full_fb_i_reg(0) + WE => EN ); RAM_reg_0_31_36_41: unisim.vcomponents.RAM32M port map ( @@ -714,16 +694,16 @@ RAM_reg_0_31_36_41: unisim.vcomponents.RAM32M ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0), - DIA(1 downto 0) => UNCONN_IN(33 downto 32), - DIB(1 downto 0) => UNCONN_IN(35 downto 34), - DIC(1 downto 0) => UNCONN_IN(37 downto 36), + DIA(1 downto 0) => UNCONN_IN(37 downto 36), + DIB(1 downto 0) => UNCONN_IN(39 downto 38), + DIC(1 downto 0) => UNCONN_IN(41 downto 40), DID(1 downto 0) => B"00", DOA(1 downto 0) => p_0_out(37 downto 36), DOB(1 downto 0) => p_0_out(39 downto 38), DOC(1 downto 0) => p_0_out(41 downto 40), DOD(1 downto 0) => NLW_RAM_reg_0_31_36_41_DOD_UNCONNECTED(1 downto 0), WCLK => s_aclk, - WE => ram_full_fb_i_reg(0) + WE => EN ); RAM_reg_0_31_42_47: unisim.vcomponents.RAM32M port map ( @@ -731,16 +711,16 @@ RAM_reg_0_31_42_47: unisim.vcomponents.RAM32M ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0), - DIA(1 downto 0) => UNCONN_IN(39 downto 38), - DIB(1 downto 0) => UNCONN_IN(41 downto 40), - DIC(1 downto 0) => UNCONN_IN(43 downto 42), + DIA(1 downto 0) => UNCONN_IN(43 downto 42), + DIB(1 downto 0) => UNCONN_IN(45 downto 44), + DIC(1 downto 0) => UNCONN_IN(47 downto 46), DID(1 downto 0) => B"00", DOA(1 downto 0) => p_0_out(43 downto 42), DOB(1 downto 0) => p_0_out(45 downto 44), DOC(1 downto 0) => p_0_out(47 downto 46), DOD(1 downto 0) => NLW_RAM_reg_0_31_42_47_DOD_UNCONNECTED(1 downto 0), WCLK => s_aclk, - WE => ram_full_fb_i_reg(0) + WE => EN ); RAM_reg_0_31_48_53: unisim.vcomponents.RAM32M port map ( @@ -748,16 +728,16 @@ RAM_reg_0_31_48_53: unisim.vcomponents.RAM32M ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0), - DIA(1 downto 0) => UNCONN_IN(45 downto 44), - DIB(1 downto 0) => UNCONN_IN(47 downto 46), - DIC(1 downto 0) => UNCONN_IN(49 downto 48), + DIA(1 downto 0) => UNCONN_IN(49 downto 48), + DIB(1 downto 0) => UNCONN_IN(51 downto 50), + DIC(1 downto 0) => UNCONN_IN(53 downto 52), DID(1 downto 0) => B"00", DOA(1 downto 0) => p_0_out(49 downto 48), DOB(1 downto 0) => p_0_out(51 downto 50), DOC(1 downto 0) => p_0_out(53 downto 52), DOD(1 downto 0) => NLW_RAM_reg_0_31_48_53_DOD_UNCONNECTED(1 downto 0), WCLK => s_aclk, - WE => ram_full_fb_i_reg(0) + WE => EN ); RAM_reg_0_31_54_59: unisim.vcomponents.RAM32M port map ( @@ -765,16 +745,35 @@ RAM_reg_0_31_54_59: unisim.vcomponents.RAM32M ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0), - DIA(1 downto 0) => UNCONN_IN(51 downto 50), - DIB(1 downto 0) => UNCONN_IN(53 downto 52), - DIC(1 downto 0) => UNCONN_IN(55 downto 54), + DIA(1 downto 0) => UNCONN_IN(55 downto 54), + DIB(1 downto 0) => UNCONN_IN(57 downto 56), + DIC(1 downto 0) => UNCONN_IN(59 downto 58), DID(1 downto 0) => B"00", DOA(1 downto 0) => p_0_out(55 downto 54), DOB(1 downto 0) => p_0_out(57 downto 56), DOC(1 downto 0) => p_0_out(59 downto 58), DOD(1 downto 0) => NLW_RAM_reg_0_31_54_59_DOD_UNCONNECTED(1 downto 0), WCLK => s_aclk, - WE => ram_full_fb_i_reg(0) + WE => EN + ); +RAM_reg_0_31_60_62: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), + ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), + ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), + ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0), + DIA(1 downto 0) => UNCONN_IN(61 downto 60), + DIB(1) => '0', + DIB(0) => UNCONN_IN(62), + DIC(1 downto 0) => B"00", + DID(1 downto 0) => B"00", + DOA(1 downto 0) => p_0_out(61 downto 60), + DOB(1) => NLW_RAM_reg_0_31_60_62_DOB_UNCONNECTED(1), + DOB(0) => p_0_out(62), + DOC(1 downto 0) => NLW_RAM_reg_0_31_60_62_DOC_UNCONNECTED(1 downto 0), + DOD(1 downto 0) => NLW_RAM_reg_0_31_60_62_DOD_UNCONNECTED(1 downto 0), + WCLK => s_aclk, + WE => EN ); RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M port map ( @@ -782,16 +781,27 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ADDRB(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), ADDRC(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), ADDRD(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0), - DIA(1 downto 0) => UNCONN_IN(3 downto 2), - DIB(1 downto 0) => UNCONN_IN(5 downto 4), - DIC(1 downto 0) => UNCONN_IN(7 downto 6), + DIA(1 downto 0) => UNCONN_IN(7 downto 6), + DIB(1 downto 0) => UNCONN_IN(9 downto 8), + DIC(1 downto 0) => UNCONN_IN(11 downto 10), DID(1 downto 0) => B"00", DOA(1 downto 0) => p_0_out(7 downto 6), DOB(1 downto 0) => p_0_out(9 downto 8), DOC(1 downto 0) => p_0_out(11 downto 10), DOD(1 downto 0) => NLW_RAM_reg_0_31_6_11_DOD_UNCONNECTED(1 downto 0), WCLK => s_aclk, - WE => ram_full_fb_i_reg(0) + WE => EN + ); +\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_aclk, + CE => ram_empty_fb_i_reg(0), + D => p_0_out(0), + Q => dout_i(0), + R => '0' ); \gpr1.dout_i_reg[10]\: unisim.vcomponents.FDRE generic map( @@ -799,9 +809,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(10), - Q => dout_i(6), + Q => dout_i(10), R => '0' ); \gpr1.dout_i_reg[11]\: unisim.vcomponents.FDRE @@ -810,9 +820,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(11), - Q => dout_i(7), + Q => dout_i(11), R => '0' ); \gpr1.dout_i_reg[12]\: unisim.vcomponents.FDRE @@ -821,9 +831,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(12), - Q => dout_i(8), + Q => dout_i(12), R => '0' ); \gpr1.dout_i_reg[13]\: unisim.vcomponents.FDRE @@ -832,9 +842,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(13), - Q => dout_i(9), + Q => dout_i(13), R => '0' ); \gpr1.dout_i_reg[14]\: unisim.vcomponents.FDRE @@ -843,9 +853,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(14), - Q => dout_i(10), + Q => dout_i(14), R => '0' ); \gpr1.dout_i_reg[15]\: unisim.vcomponents.FDRE @@ -854,9 +864,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(15), - Q => dout_i(11), + Q => dout_i(15), R => '0' ); \gpr1.dout_i_reg[16]\: unisim.vcomponents.FDRE @@ -865,9 +875,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(16), - Q => dout_i(12), + Q => dout_i(16), R => '0' ); \gpr1.dout_i_reg[17]\: unisim.vcomponents.FDRE @@ -876,9 +886,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(17), - Q => dout_i(13), + Q => dout_i(17), R => '0' ); \gpr1.dout_i_reg[18]\: unisim.vcomponents.FDRE @@ -887,9 +897,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(18), - Q => dout_i(14), + Q => dout_i(18), R => '0' ); \gpr1.dout_i_reg[19]\: unisim.vcomponents.FDRE @@ -898,9 +908,20 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(19), - Q => dout_i(15), + Q => dout_i(19), + R => '0' + ); +\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_aclk, + CE => ram_empty_fb_i_reg(0), + D => p_0_out(1), + Q => dout_i(1), R => '0' ); \gpr1.dout_i_reg[20]\: unisim.vcomponents.FDRE @@ -909,9 +930,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(20), - Q => dout_i(16), + Q => dout_i(20), R => '0' ); \gpr1.dout_i_reg[21]\: unisim.vcomponents.FDRE @@ -920,9 +941,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(21), - Q => dout_i(17), + Q => dout_i(21), R => '0' ); \gpr1.dout_i_reg[22]\: unisim.vcomponents.FDRE @@ -931,9 +952,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(22), - Q => dout_i(18), + Q => dout_i(22), R => '0' ); \gpr1.dout_i_reg[23]\: unisim.vcomponents.FDRE @@ -942,9 +963,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(23), - Q => dout_i(19), + Q => dout_i(23), R => '0' ); \gpr1.dout_i_reg[24]\: unisim.vcomponents.FDRE @@ -953,9 +974,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(24), - Q => dout_i(20), + Q => dout_i(24), R => '0' ); \gpr1.dout_i_reg[25]\: unisim.vcomponents.FDRE @@ -964,9 +985,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(25), - Q => dout_i(21), + Q => dout_i(25), R => '0' ); \gpr1.dout_i_reg[26]\: unisim.vcomponents.FDRE @@ -975,9 +996,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(26), - Q => dout_i(22), + Q => dout_i(26), R => '0' ); \gpr1.dout_i_reg[27]\: unisim.vcomponents.FDRE @@ -986,9 +1007,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(27), - Q => dout_i(23), + Q => dout_i(27), R => '0' ); \gpr1.dout_i_reg[28]\: unisim.vcomponents.FDRE @@ -997,9 +1018,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(28), - Q => dout_i(24), + Q => dout_i(28), R => '0' ); \gpr1.dout_i_reg[29]\: unisim.vcomponents.FDRE @@ -1008,9 +1029,20 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(29), - Q => dout_i(25), + Q => dout_i(29), + R => '0' + ); +\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_aclk, + CE => ram_empty_fb_i_reg(0), + D => p_0_out(2), + Q => dout_i(2), R => '0' ); \gpr1.dout_i_reg[30]\: unisim.vcomponents.FDRE @@ -1019,9 +1051,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(30), - Q => dout_i(26), + Q => dout_i(30), R => '0' ); \gpr1.dout_i_reg[31]\: unisim.vcomponents.FDRE @@ -1030,9 +1062,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(31), - Q => dout_i(27), + Q => dout_i(31), R => '0' ); \gpr1.dout_i_reg[32]\: unisim.vcomponents.FDRE @@ -1041,9 +1073,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(32), - Q => dout_i(28), + Q => dout_i(32), R => '0' ); \gpr1.dout_i_reg[33]\: unisim.vcomponents.FDRE @@ -1052,9 +1084,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(33), - Q => dout_i(29), + Q => dout_i(33), R => '0' ); \gpr1.dout_i_reg[34]\: unisim.vcomponents.FDRE @@ -1063,9 +1095,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(34), - Q => dout_i(30), + Q => dout_i(34), R => '0' ); \gpr1.dout_i_reg[35]\: unisim.vcomponents.FDRE @@ -1074,9 +1106,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(35), - Q => dout_i(31), + Q => dout_i(35), R => '0' ); \gpr1.dout_i_reg[36]\: unisim.vcomponents.FDRE @@ -1085,9 +1117,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(36), - Q => dout_i(32), + Q => dout_i(36), R => '0' ); \gpr1.dout_i_reg[37]\: unisim.vcomponents.FDRE @@ -1096,9 +1128,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(37), - Q => dout_i(33), + Q => dout_i(37), R => '0' ); \gpr1.dout_i_reg[38]\: unisim.vcomponents.FDRE @@ -1107,9 +1139,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(38), - Q => dout_i(34), + Q => dout_i(38), R => '0' ); \gpr1.dout_i_reg[39]\: unisim.vcomponents.FDRE @@ -1118,9 +1150,20 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(39), - Q => dout_i(35), + Q => dout_i(39), + R => '0' + ); +\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_aclk, + CE => ram_empty_fb_i_reg(0), + D => p_0_out(3), + Q => dout_i(3), R => '0' ); \gpr1.dout_i_reg[40]\: unisim.vcomponents.FDRE @@ -1129,9 +1172,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(40), - Q => dout_i(36), + Q => dout_i(40), R => '0' ); \gpr1.dout_i_reg[41]\: unisim.vcomponents.FDRE @@ -1140,9 +1183,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(41), - Q => dout_i(37), + Q => dout_i(41), R => '0' ); \gpr1.dout_i_reg[42]\: unisim.vcomponents.FDRE @@ -1151,9 +1194,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(42), - Q => dout_i(38), + Q => dout_i(42), R => '0' ); \gpr1.dout_i_reg[43]\: unisim.vcomponents.FDRE @@ -1162,9 +1205,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(43), - Q => dout_i(39), + Q => dout_i(43), R => '0' ); \gpr1.dout_i_reg[44]\: unisim.vcomponents.FDRE @@ -1173,9 +1216,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(44), - Q => dout_i(40), + Q => dout_i(44), R => '0' ); \gpr1.dout_i_reg[45]\: unisim.vcomponents.FDRE @@ -1184,9 +1227,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(45), - Q => dout_i(41), + Q => dout_i(45), R => '0' ); \gpr1.dout_i_reg[46]\: unisim.vcomponents.FDRE @@ -1195,9 +1238,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(46), - Q => dout_i(42), + Q => dout_i(46), R => '0' ); \gpr1.dout_i_reg[47]\: unisim.vcomponents.FDRE @@ -1206,9 +1249,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(47), - Q => dout_i(43), + Q => dout_i(47), R => '0' ); \gpr1.dout_i_reg[48]\: unisim.vcomponents.FDRE @@ -1217,9 +1260,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(48), - Q => dout_i(44), + Q => dout_i(48), R => '0' ); \gpr1.dout_i_reg[49]\: unisim.vcomponents.FDRE @@ -1228,9 +1271,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(49), - Q => dout_i(45), + Q => dout_i(49), R => '0' ); \gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE @@ -1239,9 +1282,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(4), - Q => dout_i(0), + Q => dout_i(4), R => '0' ); \gpr1.dout_i_reg[50]\: unisim.vcomponents.FDRE @@ -1250,9 +1293,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(50), - Q => dout_i(46), + Q => dout_i(50), R => '0' ); \gpr1.dout_i_reg[51]\: unisim.vcomponents.FDRE @@ -1261,9 +1304,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(51), - Q => dout_i(47), + Q => dout_i(51), R => '0' ); \gpr1.dout_i_reg[52]\: unisim.vcomponents.FDRE @@ -1272,9 +1315,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(52), - Q => dout_i(48), + Q => dout_i(52), R => '0' ); \gpr1.dout_i_reg[53]\: unisim.vcomponents.FDRE @@ -1283,9 +1326,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(53), - Q => dout_i(49), + Q => dout_i(53), R => '0' ); \gpr1.dout_i_reg[54]\: unisim.vcomponents.FDRE @@ -1294,9 +1337,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(54), - Q => dout_i(50), + Q => dout_i(54), R => '0' ); \gpr1.dout_i_reg[55]\: unisim.vcomponents.FDRE @@ -1305,9 +1348,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(55), - Q => dout_i(51), + Q => dout_i(55), R => '0' ); \gpr1.dout_i_reg[56]\: unisim.vcomponents.FDRE @@ -1316,9 +1359,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(56), - Q => dout_i(52), + Q => dout_i(56), R => '0' ); \gpr1.dout_i_reg[57]\: unisim.vcomponents.FDRE @@ -1327,9 +1370,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(57), - Q => dout_i(53), + Q => dout_i(57), R => '0' ); \gpr1.dout_i_reg[58]\: unisim.vcomponents.FDRE @@ -1338,9 +1381,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(58), - Q => dout_i(54), + Q => dout_i(58), R => '0' ); \gpr1.dout_i_reg[59]\: unisim.vcomponents.FDRE @@ -1349,9 +1392,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(59), - Q => dout_i(55), + Q => dout_i(59), R => '0' ); \gpr1.dout_i_reg[5]\: unisim.vcomponents.FDRE @@ -1360,9 +1403,42 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(5), - Q => dout_i(1), + Q => dout_i(5), + R => '0' + ); +\gpr1.dout_i_reg[60]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_aclk, + CE => ram_empty_fb_i_reg(0), + D => p_0_out(60), + Q => dout_i(60), + R => '0' + ); +\gpr1.dout_i_reg[61]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_aclk, + CE => ram_empty_fb_i_reg(0), + D => p_0_out(61), + Q => dout_i(61), + R => '0' + ); +\gpr1.dout_i_reg[62]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_aclk, + CE => ram_empty_fb_i_reg(0), + D => p_0_out(62), + Q => dout_i(62), R => '0' ); \gpr1.dout_i_reg[6]\: unisim.vcomponents.FDRE @@ -1371,9 +1447,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(6), - Q => dout_i(2), + Q => dout_i(6), R => '0' ); \gpr1.dout_i_reg[7]\: unisim.vcomponents.FDRE @@ -1382,9 +1458,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(7), - Q => dout_i(3), + Q => dout_i(7), R => '0' ); \gpr1.dout_i_reg[8]\: unisim.vcomponents.FDRE @@ -1393,9 +1469,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(8), - Q => dout_i(4), + Q => dout_i(8), R => '0' ); \gpr1.dout_i_reg[9]\: unisim.vcomponents.FDRE @@ -1404,9 +1480,9 @@ RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M ) port map ( C => s_aclk, - CE => \gpregsm1.curr_fwft_state_reg[0]\(0), + CE => ram_empty_fb_i_reg(0), D => p_0_out(9), - Q => dout_i(5), + Q => dout_i(9), R => '0' ); end STRUCTURE; @@ -1416,16 +1492,19 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20_s00_data_fifo_0_rd_bin_cntr is port ( + ram_full_comb : out STD_LOGIC; ram_empty_fb_i_reg : out STD_LOGIC; - ram_empty_fb_i_reg_0 : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 4 downto 0 ); - ram_full_fb_i_reg : out STD_LOGIC; - \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC; - ram_full_i_reg : in STD_LOGIC; + \gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + ram_full_fb_i_reg : in STD_LOGIC; + \grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + ram_full_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); \out\ : in STD_LOGIC; + empty_fwft_i_reg : in STD_LOGIC; + \gc0.count_reg[2]_0\ : in STD_LOGIC; + \gcc0.gc0.count_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); \gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); - \gcc0.gc0.count_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); - E : in STD_LOGIC_VECTOR ( 0 to 0 ); s_aclk : in STD_LOGIC; \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) ); @@ -1433,26 +1512,26 @@ end Arty_Z7_20_s00_data_fifo_0_rd_bin_cntr; architecture STRUCTURE of Arty_Z7_20_s00_data_fifo_0_rd_bin_cntr is signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \^gpr1.dout_i_reg[1]\ : STD_LOGIC_VECTOR ( 4 downto 0 ); signal plusOp : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal ram_empty_fb_i_i_3_n_0 : STD_LOGIC; - signal ram_empty_fb_i_i_6_n_0 : STD_LOGIC; - signal ram_empty_fb_i_i_7_n_0 : STD_LOGIC; - signal \^ram_empty_fb_i_reg_0\ : STD_LOGIC; - signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \ram_empty_fb_i_i_2__0_n_0\ : STD_LOGIC; + signal ram_empty_fb_i_i_5_n_0 : STD_LOGIC; + signal \ram_full_fb_i_i_2__0_n_0\ : STD_LOGIC; + signal ram_full_fb_i_i_3_n_0 : STD_LOGIC; attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair0"; - attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair1"; - attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair1"; - attribute SOFT_HLUTNM of ram_empty_fb_i_i_3 : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair0"; begin Q(4 downto 0) <= \^q\(4 downto 0); - ram_empty_fb_i_reg_0 <= \^ram_empty_fb_i_reg_0\; + \gpr1.dout_i_reg[1]\(4 downto 0) <= \^gpr1.dout_i_reg[1]\(4 downto 0); \gc0.count[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( - I0 => rd_pntr_plus1(0), + I0 => \^q\(0), O => plusOp(0) ); \gc0.count[1]_i_1\: unisim.vcomponents.LUT2 @@ -1460,41 +1539,41 @@ begin INIT => X"6" ) port map ( - I0 => rd_pntr_plus1(0), - I1 => rd_pntr_plus1(1), + I0 => \^q\(1), + I1 => \^q\(0), O => plusOp(1) ); \gc0.count[2]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"78" + INIT => X"6A" ) port map ( - I0 => rd_pntr_plus1(1), - I1 => rd_pntr_plus1(0), - I2 => rd_pntr_plus1(2), - O => plusOp(2) - ); + I0 => \^q\(2), + I1 => \^q\(1), + I2 => \^q\(0), + O => plusOp(2) + ); \gc0.count[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( - I0 => rd_pntr_plus1(0), - I1 => rd_pntr_plus1(1), - I2 => rd_pntr_plus1(2), - I3 => rd_pntr_plus1(3), + I0 => \^q\(0), + I1 => \^q\(1), + I2 => \^q\(2), + I3 => \^q\(3), O => plusOp(3) ); \gc0.count[4]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"7FFF8000" + INIT => X"6AAAAAAA" ) port map ( - I0 => rd_pntr_plus1(2), - I1 => rd_pntr_plus1(3), - I2 => rd_pntr_plus1(0), - I3 => rd_pntr_plus1(1), - I4 => rd_pntr_plus1(4), + I0 => \^q\(4), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => \^q\(2), + I4 => \^q\(3), O => plusOp(4) ); \gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE @@ -1505,8 +1584,8 @@ begin C => s_aclk, CE => E(0), CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), - D => rd_pntr_plus1(0), - Q => \^q\(0) + D => \^q\(0), + Q => \^gpr1.dout_i_reg[1]\(0) ); \gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE generic map( @@ -1516,8 +1595,8 @@ begin C => s_aclk, CE => E(0), CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), - D => rd_pntr_plus1(1), - Q => \^q\(1) + D => \^q\(1), + Q => \^gpr1.dout_i_reg[1]\(1) ); \gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE generic map( @@ -1527,8 +1606,8 @@ begin C => s_aclk, CE => E(0), CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), - D => rd_pntr_plus1(2), - Q => \^q\(2) + D => \^q\(2), + Q => \^gpr1.dout_i_reg[1]\(2) ); \gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE generic map( @@ -1538,8 +1617,8 @@ begin C => s_aclk, CE => E(0), CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), - D => rd_pntr_plus1(3), - Q => \^q\(3) + D => \^q\(3), + Q => \^gpr1.dout_i_reg[1]\(3) ); \gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE generic map( @@ -1549,8 +1628,8 @@ begin C => s_aclk, CE => E(0), CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), - D => rd_pntr_plus1(4), - Q => \^q\(4) + D => \^q\(4), + Q => \^gpr1.dout_i_reg[1]\(4) ); \gc0.count_reg[0]\: unisim.vcomponents.FDPE generic map( @@ -1561,7 +1640,7 @@ begin CE => E(0), D => plusOp(0), PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), - Q => rd_pntr_plus1(0) + Q => \^q\(0) ); \gc0.count_reg[1]\: unisim.vcomponents.FDCE generic map( @@ -1572,7 +1651,7 @@ begin CE => E(0), CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), D => plusOp(1), - Q => rd_pntr_plus1(1) + Q => \^q\(1) ); \gc0.count_reg[2]\: unisim.vcomponents.FDCE generic map( @@ -1583,7 +1662,7 @@ begin CE => E(0), CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), D => plusOp(2), - Q => rd_pntr_plus1(2) + Q => \^q\(2) ); \gc0.count_reg[3]\: unisim.vcomponents.FDCE generic map( @@ -1594,7 +1673,7 @@ begin CE => E(0), CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), D => plusOp(3), - Q => rd_pntr_plus1(3) + Q => \^q\(3) ); \gc0.count_reg[4]\: unisim.vcomponents.FDCE generic map( @@ -1605,82 +1684,82 @@ begin CE => E(0), CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), D => plusOp(4), - Q => rd_pntr_plus1(4) + Q => \^q\(4) ); ram_empty_fb_i_i_1: unisim.vcomponents.LUT5 generic map( - INIT => X"FF80F080" + INIT => X"D0FFD0D0" ) port map ( - I0 => \gpregsm1.curr_fwft_state_reg[0]\, - I1 => ram_empty_fb_i_i_3_n_0, - I2 => ram_full_i_reg, - I3 => \out\, - I4 => \^ram_empty_fb_i_reg_0\, + I0 => ram_full_i_reg(0), + I1 => \ram_empty_fb_i_i_2__0_n_0\, + I2 => \out\, + I3 => empty_fwft_i_reg, + I4 => \gc0.count_reg[2]_0\, O => ram_empty_fb_i_reg ); -ram_empty_fb_i_i_3: unisim.vcomponents.LUT5 +\ram_empty_fb_i_i_2__0\: unisim.vcomponents.LUT5 generic map( - INIT => X"82000082" + INIT => X"FFFF6FF6" ) port map ( - I0 => ram_empty_fb_i_i_6_n_0, - I1 => rd_pntr_plus1(0), - I2 => \gcc0.gc0.count_d1_reg[4]\(0), - I3 => rd_pntr_plus1(1), - I4 => \gcc0.gc0.count_d1_reg[4]\(1), - O => ram_empty_fb_i_i_3_n_0 + I0 => \gcc0.gc0.count_d1_reg[4]\(2), + I1 => \^gpr1.dout_i_reg[1]\(2), + I2 => \gcc0.gc0.count_d1_reg[4]\(4), + I3 => \^gpr1.dout_i_reg[1]\(4), + I4 => ram_empty_fb_i_i_5_n_0, + O => \ram_empty_fb_i_i_2__0_n_0\ ); -ram_empty_fb_i_i_5: unisim.vcomponents.LUT5 +ram_empty_fb_i_i_5: unisim.vcomponents.LUT6 generic map( - INIT => X"BEFFFFBE" + INIT => X"6FF6FFFFFFFF6FF6" ) port map ( - I0 => ram_empty_fb_i_i_7_n_0, - I1 => \^q\(2), - I2 => \gcc0.gc0.count_d1_reg[4]\(2), - I3 => \^q\(4), - I4 => \gcc0.gc0.count_d1_reg[4]\(4), - O => \^ram_empty_fb_i_reg_0\ + I0 => \^gpr1.dout_i_reg[1]\(3), + I1 => \gcc0.gc0.count_d1_reg[4]\(3), + I2 => \gcc0.gc0.count_d1_reg[4]\(0), + I3 => \^gpr1.dout_i_reg[1]\(0), + I4 => \gcc0.gc0.count_d1_reg[4]\(1), + I5 => \^gpr1.dout_i_reg[1]\(1), + O => ram_empty_fb_i_i_5_n_0 ); -ram_empty_fb_i_i_6: unisim.vcomponents.LUT6 +ram_full_fb_i_i_1: unisim.vcomponents.LUT5 generic map( - INIT => X"9009000000009009" + INIT => X"00C055F5" ) port map ( - I0 => rd_pntr_plus1(2), - I1 => \gcc0.gc0.count_d1_reg[4]\(2), - I2 => rd_pntr_plus1(4), - I3 => \gcc0.gc0.count_d1_reg[4]\(4), - I4 => \gcc0.gc0.count_d1_reg[4]\(3), - I5 => rd_pntr_plus1(3), - O => ram_empty_fb_i_i_6_n_0 + I0 => \ram_full_fb_i_i_2__0_n_0\, + I1 => \ram_empty_fb_i_i_2__0_n_0\, + I2 => ram_full_fb_i_reg, + I3 => \grstd1.grst_full.grst_f.rst_d3_reg\, + I4 => E(0), + O => ram_full_comb ); -ram_empty_fb_i_i_7: unisim.vcomponents.LUT6 +\ram_full_fb_i_i_2__0\: unisim.vcomponents.LUT6 generic map( - INIT => X"6FF6FFFFFFFF6FF6" + INIT => X"BEFFFFBEFFFFFFFF" ) port map ( - I0 => \^q\(0), - I1 => \gcc0.gc0.count_d1_reg[4]\(0), - I2 => \^q\(1), - I3 => \gcc0.gc0.count_d1_reg[4]\(1), - I4 => \gcc0.gc0.count_d1_reg[4]\(3), - I5 => \^q\(3), - O => ram_empty_fb_i_i_7_n_0 + I0 => ram_full_fb_i_i_3_n_0, + I1 => \^gpr1.dout_i_reg[1]\(0), + I2 => \gcc0.gc0.count_reg[4]\(0), + I3 => \^gpr1.dout_i_reg[1]\(1), + I4 => \gcc0.gc0.count_reg[4]\(1), + I5 => ram_full_i_reg(0), + O => \ram_full_fb_i_i_2__0_n_0\ ); -ram_full_fb_i_i_4: unisim.vcomponents.LUT6 +ram_full_fb_i_i_3: unisim.vcomponents.LUT6 generic map( - INIT => X"9009000000009009" + INIT => X"6FF6FFFFFFFF6FF6" ) port map ( - I0 => \^q\(2), - I1 => \gcc0.gc0.count_reg[4]\(0), - I2 => \^q\(4), - I3 => \gcc0.gc0.count_reg[4]\(2), - I4 => \gcc0.gc0.count_reg[4]\(1), - I5 => \^q\(3), - O => ram_full_fb_i_reg + I0 => \^gpr1.dout_i_reg[1]\(3), + I1 => \gcc0.gc0.count_reg[4]\(3), + I2 => \gcc0.gc0.count_reg[4]\(2), + I3 => \^gpr1.dout_i_reg[1]\(2), + I4 => \gcc0.gc0.count_reg[4]\(4), + I5 => \^gpr1.dout_i_reg[1]\(4), + O => ram_full_fb_i_i_3_n_0 ); end STRUCTURE; library IEEE; @@ -1689,14 +1768,17 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \Arty_Z7_20_s00_data_fifo_0_rd_bin_cntr__parameterized0\ is port ( - ram_full_i_reg : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 8 downto 0 ); ram_empty_i_reg : out STD_LOGIC; - ram_full_i_reg_0 : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 7 downto 0 ); + v1_reg : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 ); + v1_reg_0 : out STD_LOGIC_VECTOR ( 3 downto 0 ); ram_empty_i_reg_0 : out STD_LOGIC; - \gc0.count_d1_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); - \gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - \gcc0.gc0.count_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + ram_empty_i_reg_1 : out STD_LOGIC; + ram_empty_i_reg_2 : out STD_LOGIC; + ram_empty_i_reg_3 : out STD_LOGIC; + \gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \gcc0.gc0.count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); s_aclk : in STD_LOGIC @@ -1706,27 +1788,27 @@ entity \Arty_Z7_20_s00_data_fifo_0_rd_bin_cntr__parameterized0\ is end \Arty_Z7_20_s00_data_fifo_0_rd_bin_cntr__parameterized0\; architecture STRUCTURE of \Arty_Z7_20_s00_data_fifo_0_rd_bin_cntr__parameterized0\ is - signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \gc0.count[8]_i_2_n_0\ : STD_LOGIC; - signal \^gc0.count_d1_reg[7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \plusOp__1\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 8 to 8 ); attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \gc0.count[2]_i_1__0\ : label is "soft_lutpair11"; - attribute SOFT_HLUTNM of \gc0.count[3]_i_1__0\ : label is "soft_lutpair11"; - attribute SOFT_HLUTNM of \gc0.count[4]_i_1__0\ : label is "soft_lutpair10"; - attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair9"; - attribute SOFT_HLUTNM of \gc0.count[8]_i_1\ : label is "soft_lutpair9"; - attribute SOFT_HLUTNM of \gc0.count[8]_i_2\ : label is "soft_lutpair10"; + attribute SOFT_HLUTNM of \gc0.count[2]_i_1__0\ : label is "soft_lutpair12"; + attribute SOFT_HLUTNM of \gc0.count[3]_i_1__0\ : label is "soft_lutpair12"; + attribute SOFT_HLUTNM of \gc0.count[4]_i_1__0\ : label is "soft_lutpair11"; + attribute SOFT_HLUTNM of \gc0.count[6]_i_1\ : label is "soft_lutpair10"; + attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair10"; + attribute SOFT_HLUTNM of \gc0.count[8]_i_2\ : label is "soft_lutpair11"; begin - Q(8 downto 0) <= \^q\(8 downto 0); - \gc0.count_d1_reg[7]_0\(7 downto 0) <= \^gc0.count_d1_reg[7]_0\(7 downto 0); + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0) <= \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(8 downto 0); + Q(7 downto 0) <= \^q\(7 downto 0); \gc0.count[0]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( - I0 => \^gc0.count_d1_reg[7]_0\(0), + I0 => \^q\(0), O => \plusOp__1\(0) ); \gc0.count[1]_i_1__0\: unisim.vcomponents.LUT2 @@ -1734,18 +1816,18 @@ begin INIT => X"6" ) port map ( - I0 => \^gc0.count_d1_reg[7]_0\(0), - I1 => \^gc0.count_d1_reg[7]_0\(1), + I0 => \^q\(1), + I1 => \^q\(0), O => \plusOp__1\(1) ); \gc0.count[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => X"78" + INIT => X"6A" ) port map ( - I0 => \^gc0.count_d1_reg[7]_0\(1), - I1 => \^gc0.count_d1_reg[7]_0\(0), - I2 => \^gc0.count_d1_reg[7]_0\(2), + I0 => \^q\(2), + I1 => \^q\(1), + I2 => \^q\(0), O => \plusOp__1\(2) ); \gc0.count[3]_i_1__0\: unisim.vcomponents.LUT4 @@ -1753,80 +1835,82 @@ begin INIT => X"7F80" ) port map ( - I0 => \^gc0.count_d1_reg[7]_0\(2), - I1 => \^gc0.count_d1_reg[7]_0\(0), - I2 => \^gc0.count_d1_reg[7]_0\(1), - I3 => \^gc0.count_d1_reg[7]_0\(3), + I0 => \^q\(0), + I1 => \^q\(1), + I2 => \^q\(2), + I3 => \^q\(3), O => \plusOp__1\(3) ); \gc0.count[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( - INIT => X"7FFF8000" + INIT => X"6AAAAAAA" ) port map ( - I0 => \^gc0.count_d1_reg[7]_0\(3), - I1 => \^gc0.count_d1_reg[7]_0\(1), - I2 => \^gc0.count_d1_reg[7]_0\(0), - I3 => \^gc0.count_d1_reg[7]_0\(2), - I4 => \^gc0.count_d1_reg[7]_0\(4), + I0 => \^q\(4), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => \^q\(2), + I4 => \^q\(3), O => \plusOp__1\(4) ); \gc0.count[5]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"7FFFFFFF80000000" + INIT => X"6AAAAAAAAAAAAAAA" ) port map ( - I0 => \^gc0.count_d1_reg[7]_0\(4), - I1 => \^gc0.count_d1_reg[7]_0\(2), - I2 => \^gc0.count_d1_reg[7]_0\(0), - I3 => \^gc0.count_d1_reg[7]_0\(1), - I4 => \^gc0.count_d1_reg[7]_0\(3), - I5 => \^gc0.count_d1_reg[7]_0\(5), + I0 => \^q\(5), + I1 => \^q\(3), + I2 => \^q\(2), + I3 => \^q\(1), + I4 => \^q\(0), + I5 => \^q\(4), O => \plusOp__1\(5) ); -\gc0.count[6]_i_1\: unisim.vcomponents.LUT3 +\gc0.count[6]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"78" + INIT => X"6AAA" ) port map ( - I0 => \^gc0.count_d1_reg[7]_0\(5), - I1 => \gc0.count[8]_i_2_n_0\, - I2 => \^gc0.count_d1_reg[7]_0\(6), + I0 => \^q\(6), + I1 => \^q\(4), + I2 => \gc0.count[8]_i_2_n_0\, + I3 => \^q\(5), O => \plusOp__1\(6) ); -\gc0.count[7]_i_1\: unisim.vcomponents.LUT4 +\gc0.count[7]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"7F80" + INIT => X"6AAAAAAA" ) port map ( - I0 => \gc0.count[8]_i_2_n_0\, - I1 => \^gc0.count_d1_reg[7]_0\(5), - I2 => \^gc0.count_d1_reg[7]_0\(6), - I3 => \^gc0.count_d1_reg[7]_0\(7), + I0 => \^q\(7), + I1 => \^q\(5), + I2 => \gc0.count[8]_i_2_n_0\, + I3 => \^q\(4), + I4 => \^q\(6), O => \plusOp__1\(7) ); -\gc0.count[8]_i_1\: unisim.vcomponents.LUT5 +\gc0.count[8]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"7FFF8000" + INIT => X"6AAAAAAAAAAAAAAA" ) port map ( - I0 => \gc0.count[8]_i_2_n_0\, - I1 => \^gc0.count_d1_reg[7]_0\(7), - I2 => \^gc0.count_d1_reg[7]_0\(6), - I3 => \^gc0.count_d1_reg[7]_0\(5), - I4 => rd_pntr_plus1(8), + I0 => rd_pntr_plus1(8), + I1 => \^q\(6), + I2 => \^q\(4), + I3 => \gc0.count[8]_i_2_n_0\, + I4 => \^q\(5), + I5 => \^q\(7), O => \plusOp__1\(8) ); -\gc0.count[8]_i_2\: unisim.vcomponents.LUT5 +\gc0.count[8]_i_2\: unisim.vcomponents.LUT4 generic map( - INIT => X"80000000" + INIT => X"8000" ) port map ( - I0 => \^gc0.count_d1_reg[7]_0\(3), - I1 => \^gc0.count_d1_reg[7]_0\(1), - I2 => \^gc0.count_d1_reg[7]_0\(0), - I3 => \^gc0.count_d1_reg[7]_0\(2), - I4 => \^gc0.count_d1_reg[7]_0\(4), + I0 => \^q\(3), + I1 => \^q\(2), + I2 => \^q\(1), + I3 => \^q\(0), O => \gc0.count[8]_i_2_n_0\ ); \gc0.count_d1_reg[0]\: unisim.vcomponents.FDRE @@ -1836,8 +1920,8 @@ begin port map ( C => s_aclk, CE => E(0), - D => \^gc0.count_d1_reg[7]_0\(0), - Q => \^q\(0), + D => \^q\(0), + Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); \gc0.count_d1_reg[1]\: unisim.vcomponents.FDRE @@ -1847,8 +1931,8 @@ begin port map ( C => s_aclk, CE => E(0), - D => \^gc0.count_d1_reg[7]_0\(1), - Q => \^q\(1), + D => \^q\(1), + Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); \gc0.count_d1_reg[2]\: unisim.vcomponents.FDRE @@ -1858,8 +1942,8 @@ begin port map ( C => s_aclk, CE => E(0), - D => \^gc0.count_d1_reg[7]_0\(2), - Q => \^q\(2), + D => \^q\(2), + Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(2), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); \gc0.count_d1_reg[3]\: unisim.vcomponents.FDRE @@ -1869,8 +1953,8 @@ begin port map ( C => s_aclk, CE => E(0), - D => \^gc0.count_d1_reg[7]_0\(3), - Q => \^q\(3), + D => \^q\(3), + Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(3), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); \gc0.count_d1_reg[4]\: unisim.vcomponents.FDRE @@ -1880,8 +1964,8 @@ begin port map ( C => s_aclk, CE => E(0), - D => \^gc0.count_d1_reg[7]_0\(4), - Q => \^q\(4), + D => \^q\(4), + Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(4), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); \gc0.count_d1_reg[5]\: unisim.vcomponents.FDRE @@ -1891,8 +1975,8 @@ begin port map ( C => s_aclk, CE => E(0), - D => \^gc0.count_d1_reg[7]_0\(5), - Q => \^q\(5), + D => \^q\(5), + Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(5), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); \gc0.count_d1_reg[6]\: unisim.vcomponents.FDRE @@ -1902,8 +1986,8 @@ begin port map ( C => s_aclk, CE => E(0), - D => \^gc0.count_d1_reg[7]_0\(6), - Q => \^q\(6), + D => \^q\(6), + Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(6), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); \gc0.count_d1_reg[7]\: unisim.vcomponents.FDRE @@ -1913,8 +1997,8 @@ begin port map ( C => s_aclk, CE => E(0), - D => \^gc0.count_d1_reg[7]_0\(7), - Q => \^q\(7), + D => \^q\(7), + Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(7), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); \gc0.count_d1_reg[8]\: unisim.vcomponents.FDRE @@ -1925,7 +2009,7 @@ begin C => s_aclk, CE => E(0), D => rd_pntr_plus1(8), - Q => \^q\(8), + Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(8), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); \gc0.count_reg[0]\: unisim.vcomponents.FDSE @@ -1936,7 +2020,7 @@ begin C => s_aclk, CE => E(0), D => \plusOp__1\(0), - Q => \^gc0.count_d1_reg[7]_0\(0), + Q => \^q\(0), S => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); \gc0.count_reg[1]\: unisim.vcomponents.FDRE @@ -1947,7 +2031,7 @@ begin C => s_aclk, CE => E(0), D => \plusOp__1\(1), - Q => \^gc0.count_d1_reg[7]_0\(1), + Q => \^q\(1), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); \gc0.count_reg[2]\: unisim.vcomponents.FDRE @@ -1958,7 +2042,7 @@ begin C => s_aclk, CE => E(0), D => \plusOp__1\(2), - Q => \^gc0.count_d1_reg[7]_0\(2), + Q => \^q\(2), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); \gc0.count_reg[3]\: unisim.vcomponents.FDRE @@ -1969,7 +2053,7 @@ begin C => s_aclk, CE => E(0), D => \plusOp__1\(3), - Q => \^gc0.count_d1_reg[7]_0\(3), + Q => \^q\(3), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); \gc0.count_reg[4]\: unisim.vcomponents.FDRE @@ -1980,7 +2064,7 @@ begin C => s_aclk, CE => E(0), D => \plusOp__1\(4), - Q => \^gc0.count_d1_reg[7]_0\(4), + Q => \^q\(4), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); \gc0.count_reg[5]\: unisim.vcomponents.FDRE @@ -1991,7 +2075,7 @@ begin C => s_aclk, CE => E(0), D => \plusOp__1\(5), - Q => \^gc0.count_d1_reg[7]_0\(5), + Q => \^q\(5), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); \gc0.count_reg[6]\: unisim.vcomponents.FDRE @@ -2002,7 +2086,7 @@ begin C => s_aclk, CE => E(0), D => \plusOp__1\(6), - Q => \^gc0.count_d1_reg[7]_0\(6), + Q => \^q\(6), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); \gc0.count_reg[7]\: unisim.vcomponents.FDRE @@ -2013,7 +2097,7 @@ begin C => s_aclk, CE => E(0), D => \plusOp__1\(7), - Q => \^gc0.count_d1_reg[7]_0\(7), + Q => \^q\(7), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); \gc0.count_reg[8]\: unisim.vcomponents.FDRE @@ -2027,41 +2111,146 @@ begin Q => rd_pntr_plus1(8), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); -\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT2 +\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"9" + INIT => X"9009" ) port map ( - I0 => \^q\(8), + I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0), I1 => \gcc0.gc0.count_d1_reg[8]\(0), - O => ram_full_i_reg + I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1), + I3 => \gcc0.gc0.count_d1_reg[8]\(1), + O => v1_reg(0) ); -\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT2 +\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4 generic map( - INIT => X"9" + INIT => X"9009" ) port map ( - I0 => rd_pntr_plus1(8), + I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0), + I1 => \gcc0.gc0.count_reg[7]\(0), + I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1), + I3 => \gcc0.gc0.count_reg[7]\(1), + O => v1_reg_0(0) + ); +\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0), I1 => \gcc0.gc0.count_d1_reg[8]\(0), - O => ram_empty_i_reg + I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1), + I3 => \gcc0.gc0.count_d1_reg[8]\(1), + O => ram_empty_i_reg_0 ); -\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT2 +\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"9" + INIT => X"9009" ) port map ( - I0 => \^q\(8), - I1 => \gcc0.gc0.count_reg[8]\(0), - O => ram_full_i_reg_0 + I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(2), + I1 => \gcc0.gc0.count_d1_reg[8]\(2), + I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(3), + I3 => \gcc0.gc0.count_d1_reg[8]\(3), + O => v1_reg(1) ); -\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT2 +\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(2), + I1 => \gcc0.gc0.count_reg[7]\(2), + I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(3), + I3 => \gcc0.gc0.count_reg[7]\(3), + O => v1_reg_0(1) + ); +\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(2), + I1 => \gcc0.gc0.count_d1_reg[8]\(2), + I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(3), + I3 => \gcc0.gc0.count_d1_reg[8]\(3), + O => ram_empty_i_reg_1 + ); +\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(5), + I1 => \gcc0.gc0.count_d1_reg[8]\(5), + I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(4), + I3 => \gcc0.gc0.count_d1_reg[8]\(4), + O => v1_reg(2) + ); +\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(5), + I1 => \gcc0.gc0.count_reg[7]\(5), + I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(4), + I3 => \gcc0.gc0.count_reg[7]\(4), + O => v1_reg_0(2) + ); +\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(5), + I1 => \gcc0.gc0.count_d1_reg[8]\(5), + I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(4), + I3 => \gcc0.gc0.count_d1_reg[8]\(4), + O => ram_empty_i_reg_2 + ); +\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(7), + I1 => \gcc0.gc0.count_d1_reg[8]\(7), + I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(6), + I3 => \gcc0.gc0.count_d1_reg[8]\(6), + O => v1_reg(3) + ); +\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(7), + I1 => \gcc0.gc0.count_reg[7]\(7), + I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(6), + I3 => \gcc0.gc0.count_reg[7]\(6), + O => v1_reg_0(3) + ); +\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(7), + I1 => \gcc0.gc0.count_d1_reg[8]\(7), + I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(6), + I3 => \gcc0.gc0.count_d1_reg[8]\(6), + O => ram_empty_i_reg_3 + ); +\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( - I0 => \^q\(8), - I1 => \gcc0.gc0.count_d1_reg[8]\(0), - O => ram_empty_i_reg_0 + I0 => rd_pntr_plus1(8), + I1 => \gcc0.gc0.count_d1_reg[8]\(8), + O => ram_empty_i_reg ); end STRUCTURE; library IEEE; @@ -2071,26 +2260,25 @@ use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20_s00_data_fifo_0_rd_fwft is port ( \out\ : out STD_LOGIC; - \gfwd_rev_pipeline1.s_ready_i_reg\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); - \gfwd_rev_pipeline1.s_ready_i_reg_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0]\ : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); - \gc0.count_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - ram_full_fb_i_reg : out STD_LOGIC; + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0]\ : out STD_LOGIC; + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); ram_empty_fb_i_reg : out STD_LOGIC; - \goreg_dm.dout_i_reg[59]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\ : out STD_LOGIC; - \gfwd_rev_pipeline1.s_ready_i_reg_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); - \gfwd_rev_pipeline1.s_ready_i_reg_2\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \goreg_dm.dout_i_reg[62]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]\ : out STD_LOGIC; + \gfwd_rev_pipeline1.s_ready_i_reg\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \gfwd_rev_pipeline1.s_ready_i_reg_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); s_aclk : in STD_LOGIC; \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); + ram_empty_fb_i_reg_0 : in STD_LOGIC; CO : in STD_LOGIC_VECTOR ( 0 to 0 ); arready_pkt : in STD_LOGIC; - s_axi_rready : in STD_LOGIC; empty_fwft_fb_o_i_reg_0 : in STD_LOGIC; - \gfwd_rev_pipeline1.s_ready_i_reg_3\ : in STD_LOGIC; - ram_empty_fb_i_reg_0 : in STD_LOGIC + s_axi_rready : in STD_LOGIC; + \gfwd_rev_pipeline1.s_ready_i_reg_1\ : in STD_LOGIC; + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \goreg_dm.dout_i_reg[22]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end Arty_Z7_20_s00_data_fifo_0_rd_fwft; @@ -2111,7 +2299,8 @@ architecture STRUCTURE of Arty_Z7_20_s00_data_fifo_0_rd_fwft is signal empty_fwft_i : STD_LOGIC; attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true; signal empty_fwft_i0 : STD_LOGIC; - signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \gpregsm1.curr_fwft_state[1]_i_1__0_n_0\ : STD_LOGIC; + signal next_fwft_state : STD_LOGIC_VECTOR ( 0 to 0 ); signal user_valid : STD_LOGIC; attribute DONT_TOUCH of user_valid : signal is std.standard.true; attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true; @@ -2142,16 +2331,41 @@ architecture STRUCTURE of Arty_Z7_20_s00_data_fifo_0_rd_fwft is attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no"; begin \out\ <= empty_fwft_i; +\_carry_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"40004040" + ) + port map ( + I0 => empty_fwft_i, + I1 => arready_pkt, + I2 => CO(0), + I3 => empty_fwft_fb_o_i_reg_0, + I4 => s_axi_rready, + O => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]\ + ); +\_carry_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BFFFBFBFFFFFFFFF" + ) + port map ( + I0 => empty_fwft_i, + I1 => arready_pkt, + I2 => CO(0), + I3 => empty_fwft_fb_o_i_reg_0, + I4 => s_axi_rready, + I5 => \goreg_dm.dout_i_reg[22]\(0), + O => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0\(0) + ); aempty_fwft_fb_i_i_1: unisim.vcomponents.LUT5 generic map( - INIT => X"CE8CCC44" + INIT => X"EC8CC88C" ) port map ( - I0 => curr_fwft_state(1), + I0 => ram_empty_fb_i_reg_0, I1 => aempty_fwft_fb_i, - I2 => \gfwd_rev_pipeline1.s_ready_i_reg_3\, - I3 => ram_empty_fb_i_reg_0, - I4 => curr_fwft_state(0), + I2 => curr_fwft_state(1), + I3 => curr_fwft_state(0), + I4 => \gfwd_rev_pipeline1.s_ready_i_reg_1\, O => aempty_fwft_i0 ); aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE @@ -2177,70 +2391,34 @@ aempty_fwft_i_reg: unisim.vcomponents.FDPE Q => aempty_fwft_i ); \arvalid_en0_carry__0_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"E" - ) - port map ( - I0 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(5), - I1 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(4), - O => \gfwd_rev_pipeline1.s_ready_i_reg_2\(0) - ); -\arvalid_en0_carry__0_i_2\: unisim.vcomponents.LUT2 - generic map( - INIT => X"1" - ) - port map ( - I0 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(4), - I1 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(5), - O => \gfwd_rev_pipeline1.s_ready_i_reg_0\(0) - ); -arvalid_en0_carry_i_1: unisim.vcomponents.LUT2 - generic map( - INIT => X"E" - ) - port map ( - I0 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(2), - I1 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(3), - O => \gfwd_rev_pipeline1.s_ready_i_reg_1\(1) - ); -arvalid_en0_carry_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(0), I1 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(1), - O => \gfwd_rev_pipeline1.s_ready_i_reg_1\(0) - ); -arvalid_en0_carry_i_5: unisim.vcomponents.LUT2 - generic map( - INIT => X"1" - ) - port map ( - I0 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(3), - I1 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(2), - O => \gfwd_rev_pipeline1.s_ready_i_reg\(1) + O => \gfwd_rev_pipeline1.s_ready_i_reg\(0) ); -arvalid_en0_carry_i_6: unisim.vcomponents.LUT2 +\arvalid_en0_carry__0_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(1), I1 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(0), - O => \gfwd_rev_pipeline1.s_ready_i_reg\(0) + O => \gfwd_rev_pipeline1.s_ready_i_reg_0\(0) ); empty_fwft_fb_i_i_1: unisim.vcomponents.LUT6 generic map( - INIT => X"AAAA0000AAEAAAAA" + INIT => X"FFFF00FF00080000" ) port map ( - I0 => empty_fwft_fb_i, + I0 => CO(0), I1 => arready_pkt, - I2 => CO(0), - I3 => empty_fwft_i, + I2 => empty_fwft_i, + I3 => curr_fwft_state(1), I4 => curr_fwft_state(0), - I5 => curr_fwft_state(1), + I5 => empty_fwft_fb_i, O => empty_fwft_i0 ); empty_fwft_fb_i_reg: unisim.vcomponents.FDPE @@ -2256,15 +2434,15 @@ empty_fwft_fb_i_reg: unisim.vcomponents.FDPE ); empty_fwft_fb_o_i_i_1: unisim.vcomponents.LUT6 generic map( - INIT => X"AAAA0000AAEAAAAA" + INIT => X"FFFF00FF00080000" ) port map ( - I0 => empty_fwft_fb_o_i, + I0 => CO(0), I1 => arready_pkt, - I2 => CO(0), - I3 => empty_fwft_i, + I2 => empty_fwft_i, + I3 => curr_fwft_state(1), I4 => curr_fwft_state(0), - I5 => curr_fwft_state(1), + I5 => empty_fwft_fb_o_i, O => empty_fwft_fb_o_i0 ); empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE @@ -2291,53 +2469,53 @@ empty_fwft_i_reg: unisim.vcomponents.FDPE ); \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[9]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"4040FF40" + INIT => X"40FF4040" ) port map ( I0 => empty_fwft_i, - I1 => CO(0), - I2 => arready_pkt, - I3 => s_axi_rready, - I4 => empty_fwft_fb_o_i_reg_0, - O => E(0) + I1 => arready_pkt, + I2 => CO(0), + I3 => empty_fwft_fb_o_i_reg_0, + I4 => s_axi_rready, + O => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0]_0\(0) ); -\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[9]_i_3\: unisim.vcomponents.LUT5 +\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[9]_i_4\: unisim.vcomponents.LUT5 generic map( - INIT => X"FFFFBFFF" + INIT => X"00400000" ) port map ( I0 => empty_fwft_i, - I1 => CO(0), - I2 => arready_pkt, - I3 => s_axi_rready, - I4 => empty_fwft_fb_o_i_reg_0, + I1 => arready_pkt, + I2 => CO(0), + I3 => empty_fwft_fb_o_i_reg_0, + I4 => s_axi_rready, O => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0]\ ); \gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"0000000055D5FFFF" + INIT => X"1515151555151515" ) port map ( - I0 => curr_fwft_state(0), - I1 => arready_pkt, - I2 => CO(0), - I3 => empty_fwft_i, - I4 => curr_fwft_state(1), - I5 => ram_empty_fb_i_reg_0, - O => \gc0.count_reg[4]\(0) + I0 => ram_empty_fb_i_reg_0, + I1 => curr_fwft_state(0), + I2 => curr_fwft_state(1), + I3 => CO(0), + I4 => arready_pkt, + I5 => empty_fwft_i, + O => E(0) ); -\goreg_dm.dout_i[59]_i_1\: unisim.vcomponents.LUT6 +\goreg_dm.dout_i[62]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"0404040444040404" + INIT => X"0000000055D50000" ) port map ( - I0 => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), - I1 => curr_fwft_state(1), - I2 => curr_fwft_state(0), - I3 => arready_pkt, - I4 => CO(0), - I5 => empty_fwft_i, - O => \goreg_dm.dout_i_reg[59]\(0) + I0 => curr_fwft_state(0), + I1 => CO(0), + I2 => arready_pkt, + I3 => empty_fwft_i, + I4 => curr_fwft_state(1), + I5 => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), + O => \goreg_dm.dout_i_reg[62]\(0) ); \gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT5 generic map( @@ -2346,23 +2524,23 @@ empty_fwft_i_reg: unisim.vcomponents.FDPE port map ( I0 => curr_fwft_state(1), I1 => curr_fwft_state(0), - I2 => arready_pkt, - I3 => CO(0), + I2 => CO(0), + I3 => arready_pkt, I4 => empty_fwft_i, O => next_fwft_state(0) ); -\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT6 +\gpregsm1.curr_fwft_state[1]_i_1__0\: unisim.vcomponents.LUT6 generic map( - INIT => X"8AAA0000FFFFFFFF" + INIT => X"88880888FFFFFFFF" ) port map ( - I0 => curr_fwft_state(1), - I1 => empty_fwft_i, + I0 => curr_fwft_state(0), + I1 => curr_fwft_state(1), I2 => CO(0), I3 => arready_pkt, - I4 => curr_fwft_state(0), + I4 => empty_fwft_i, I5 => ram_empty_fb_i_reg_0, - O => next_fwft_state(1) + O => \gpregsm1.curr_fwft_state[1]_i_1__0_n_0\ ); \gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE generic map( @@ -2383,7 +2561,7 @@ empty_fwft_i_reg: unisim.vcomponents.FDPE C => s_aclk, CE => '1', CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1), - D => next_fwft_state(1), + D => \gpregsm1.curr_fwft_state[1]_i_1__0_n_0\, Q => curr_fwft_state(1) ); \gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE @@ -2397,43 +2575,18 @@ empty_fwft_i_reg: unisim.vcomponents.FDPE D => next_fwft_state(0), Q => user_valid ); -\i__carry__0_i_1\: unisim.vcomponents.LUT5 +ram_empty_fb_i_i_3: unisim.vcomponents.LUT5 generic map( - INIT => X"BFBFFFBF" + INIT => X"BF000000" ) port map ( I0 => empty_fwft_i, - I1 => CO(0), - I2 => arready_pkt, - I3 => s_axi_rready, - I4 => empty_fwft_fb_o_i_reg_0, - O => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\ - ); -ram_empty_fb_i_i_2: unisim.vcomponents.LUT5 - generic map( - INIT => X"55D5FFFF" - ) - port map ( - I0 => curr_fwft_state(0), I1 => arready_pkt, I2 => CO(0), - I3 => empty_fwft_i, - I4 => curr_fwft_state(1), + I3 => curr_fwft_state(1), + I4 => curr_fwft_state(0), O => ram_empty_fb_i_reg ); -ram_full_fb_i_i_3: unisim.vcomponents.LUT6 - generic map( - INIT => X"EAEEEEEEAAAAAAAA" - ) - port map ( - I0 => ram_empty_fb_i_reg_0, - I1 => curr_fwft_state(1), - I2 => empty_fwft_i, - I3 => CO(0), - I4 => arready_pkt, - I5 => curr_fwft_state(0), - O => ram_full_fb_i_reg - ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; @@ -2443,22 +2596,22 @@ entity \Arty_Z7_20_s00_data_fifo_0_rd_fwft__parameterized0\ is port ( \out\ : out STD_LOGIC; fwft_rst_done_q : out STD_LOGIC; - S : out STD_LOGIC_VECTOR ( 0 to 0 ); E : out STD_LOGIC_VECTOR ( 0 to 0 ); ram_full_i_reg : out STD_LOGIC; ram_empty_i_reg : out STD_LOGIC; \goreg_bm.dout_i_reg[68]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + S : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rvalid : out STD_LOGIC; \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ : in STD_LOGIC; s_aclk : in STD_LOGIC; \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - Q : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rready : in STD_LOGIC; - arready_pkt : in STD_LOGIC; + ram_empty_fb_i_reg : in STD_LOGIC; CO : in STD_LOGIC_VECTOR ( 0 to 0 ); + arready_pkt : in STD_LOGIC; empty_fwft_i_reg_0 : in STD_LOGIC; - ram_empty_fb_i_reg : in STD_LOGIC + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \Arty_Z7_20_s00_data_fifo_0_rd_fwft__parameterized0\ : entity is "rd_fwft"; @@ -2517,27 +2670,40 @@ begin \out\ <= empty_fwft_fb_o_i; \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"000075FF" + INIT => X"00007F77" ) port map ( - I0 => curr_fwft_state(0), - I1 => empty_fwft_fb_o_i, - I2 => s_axi_rready, - I3 => curr_fwft_state(1), + I0 => curr_fwft_state(1), + I1 => curr_fwft_state(0), + I2 => empty_fwft_fb_o_i, + I3 => s_axi_rready, I4 => ram_empty_fb_i_reg, O => E(0) ); +\_carry__1_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF2FFF0000D000" + ) + port map ( + I0 => s_axi_rready, + I1 => empty_fwft_fb_o_i, + I2 => CO(0), + I3 => arready_pkt, + I4 => empty_fwft_i_reg_0, + I5 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(0), + O => S(0) + ); \aempty_fwft_fb_i_i_1__0\: unisim.vcomponents.LUT6 generic map( - INIT => X"F0F0F8F09090B090" + INIT => X"A88AA88AEA8AA88A" ) port map ( - I0 => curr_fwft_state(0), - I1 => curr_fwft_state(1), - I2 => aempty_fwft_fb_i, - I3 => s_axi_rready, - I4 => empty_fwft_fb_o_i, - I5 => ram_empty_fb_i_reg, + I0 => aempty_fwft_fb_i, + I1 => ram_empty_fb_i_reg, + I2 => curr_fwft_state(1), + I3 => curr_fwft_state(0), + I4 => s_axi_rready, + I5 => empty_fwft_fb_o_i, O => aempty_fwft_i0 ); aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE @@ -2564,14 +2730,14 @@ aempty_fwft_i_reg: unisim.vcomponents.FDPE ); \empty_fwft_fb_i_i_1__0\: unisim.vcomponents.LUT5 generic map( - INIT => X"AA00BAAA" + INIT => X"A2A2B2A2" ) port map ( I0 => empty_fwft_fb_i, - I1 => empty_fwft_fb_o_i, - I2 => s_axi_rready, - I3 => curr_fwft_state(0), - I4 => curr_fwft_state(1), + I1 => curr_fwft_state(1), + I2 => curr_fwft_state(0), + I3 => s_axi_rready, + I4 => empty_fwft_fb_o_i, O => empty_fwft_i0 ); empty_fwft_fb_i_reg: unisim.vcomponents.FDPE @@ -2587,13 +2753,13 @@ empty_fwft_fb_i_reg: unisim.vcomponents.FDPE ); \empty_fwft_fb_o_i_i_1__0\: unisim.vcomponents.LUT4 generic map( - INIT => X"A0EA" + INIT => X"F320" ) port map ( - I0 => empty_fwft_fb_o_i, - I1 => s_axi_rready, + I0 => s_axi_rready, + I1 => curr_fwft_state(1), I2 => curr_fwft_state(0), - I3 => curr_fwft_state(1), + I3 => empty_fwft_fb_o_i, O => empty_fwft_fb_o_i_reg0 ); empty_fwft_fb_o_i_reg: unisim.vcomponents.FDSE @@ -2663,36 +2829,36 @@ empty_fwft_i_reg: unisim.vcomponents.FDPE ); \goreg_bm.dout_i[68]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"04440404" + INIT => X"00005D00" ) port map ( - I0 => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), - I1 => curr_fwft_state(1), - I2 => curr_fwft_state(0), - I3 => empty_fwft_fb_o_i, - I4 => s_axi_rready, + I0 => curr_fwft_state(0), + I1 => s_axi_rready, + I2 => empty_fwft_fb_o_i, + I3 => curr_fwft_state(1), + I4 => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), O => \goreg_bm.dout_i_reg[68]\(0) ); \gpregsm1.curr_fwft_state[0]_i_1__0\: unisim.vcomponents.LUT4 generic map( - INIT => X"EAEE" + INIT => X"EEAE" ) port map ( I0 => curr_fwft_state(1), I1 => curr_fwft_state(0), - I2 => empty_fwft_fb_o_i, - I3 => s_axi_rready, + I2 => s_axi_rready, + I3 => empty_fwft_fb_o_i, O => next_fwft_state(0) ); \gpregsm1.curr_fwft_state[1]_i_2\: unisim.vcomponents.LUT5 generic map( - INIT => X"A200FFFF" + INIT => X"D000FFFF" ) port map ( - I0 => curr_fwft_state(1), - I1 => s_axi_rready, - I2 => empty_fwft_fb_o_i, - I3 => curr_fwft_state(0), + I0 => s_axi_rready, + I1 => empty_fwft_fb_o_i, + I2 => curr_fwft_state(0), + I3 => curr_fwft_state(1), I4 => ram_empty_fb_i_reg, O => next_fwft_state(1) ); @@ -2729,40 +2895,27 @@ empty_fwft_i_reg: unisim.vcomponents.FDPE Q => user_valid, R => SR(0) ); -\i__carry__0_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AAAAAAAA65AAAAAA" - ) - port map ( - I0 => Q(0), - I1 => empty_fwft_fb_o_i, - I2 => s_axi_rready, - I3 => arready_pkt, - I4 => CO(0), - I5 => empty_fwft_i_reg_0, - O => S(0) - ); -\ram_empty_fb_i_i_2__0\: unisim.vcomponents.LUT4 +ram_empty_fb_i_i_2: unisim.vcomponents.LUT4 generic map( - INIT => X"75FF" + INIT => X"8088" ) port map ( - I0 => curr_fwft_state(0), - I1 => empty_fwft_fb_o_i, - I2 => s_axi_rready, - I3 => curr_fwft_state(1), + I0 => curr_fwft_state(1), + I1 => curr_fwft_state(0), + I2 => empty_fwft_fb_o_i, + I3 => s_axi_rready, O => ram_empty_i_reg ); ram_full_fb_i_i_2: unisim.vcomponents.LUT5 generic map( - INIT => X"EEAEAAAA" + INIT => X"FBAAAAAA" ) port map ( I0 => ram_empty_fb_i_reg, - I1 => curr_fwft_state(1), - I2 => s_axi_rready, - I3 => empty_fwft_fb_o_i, - I4 => curr_fwft_state(0), + I1 => s_axi_rready, + I2 => empty_fwft_fb_o_i, + I3 => curr_fwft_state(0), + I4 => curr_fwft_state(1), O => ram_full_i_reg ); s_axi_rvalid_INST_0: unisim.vcomponents.LUT1 @@ -3898,16 +4051,11 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr is port ( - ram_full_comb : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); - \gpr1.dout_i_reg[5]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); - ram_empty_fb_i_reg : in STD_LOGIC; - \out\ : in STD_LOGIC; - \grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC; - \gc0.count_d1_reg[2]\ : in STD_LOGIC; - \gc0.count_d1_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); - \gc0.count_d1_reg[2]_0\ : in STD_LOGIC; - ram_full_i_reg : in STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 4 downto 0 ); + ram_empty_fb_i_reg : out STD_LOGIC; + \gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + \gc0.count_reg[4]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + ram_full_fb_i_reg : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); s_aclk : in STD_LOGIC; AR : in STD_LOGIC_VECTOR ( 0 to 0 ) @@ -3915,23 +4063,24 @@ entity Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr is end Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr; architecture STRUCTURE of Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr is - signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal p_12_out : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \^gpr1.dout_i_reg[1]\ : STD_LOGIC_VECTOR ( 4 downto 0 ); signal \plusOp__0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal \ram_full_fb_i_i_2__0_n_0\ : STD_LOGIC; + signal ram_empty_fb_i_i_7_n_0 : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \gcc0.gc0.count[1]_i_1\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair2"; begin - Q(2 downto 0) <= \^q\(2 downto 0); + Q(4 downto 0) <= \^q\(4 downto 0); + \gpr1.dout_i_reg[1]\(4 downto 0) <= \^gpr1.dout_i_reg[1]\(4 downto 0); \gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( - I0 => p_12_out(0), + I0 => \^q\(0), O => \plusOp__0\(0) ); \gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2 @@ -3939,17 +4088,17 @@ begin INIT => X"6" ) port map ( - I0 => p_12_out(0), - I1 => p_12_out(1), + I0 => \^q\(1), + I1 => \^q\(0), O => \plusOp__0\(1) ); \gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"78" + INIT => X"6A" ) port map ( - I0 => p_12_out(1), - I1 => p_12_out(0), + I0 => \^q\(2), + I1 => \^q\(1), I2 => \^q\(0), O => \plusOp__0\(2) ); @@ -3958,22 +4107,22 @@ begin INIT => X"7F80" ) port map ( - I0 => p_12_out(0), - I1 => p_12_out(1), - I2 => \^q\(0), - I3 => \^q\(1), + I0 => \^q\(0), + I1 => \^q\(1), + I2 => \^q\(2), + I3 => \^q\(3), O => \plusOp__0\(3) ); \gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"7FFF8000" + INIT => X"6AAAAAAA" ) port map ( - I0 => \^q\(0), - I1 => \^q\(1), - I2 => p_12_out(0), - I3 => p_12_out(1), - I4 => \^q\(2), + I0 => \^q\(4), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => \^q\(2), + I4 => \^q\(3), O => \plusOp__0\(4) ); \gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE @@ -3984,8 +4133,8 @@ begin C => s_aclk, CE => E(0), CLR => AR(0), - D => p_12_out(0), - Q => \gpr1.dout_i_reg[5]\(0) + D => \^q\(0), + Q => \^gpr1.dout_i_reg[1]\(0) ); \gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE generic map( @@ -3995,8 +4144,8 @@ begin C => s_aclk, CE => E(0), CLR => AR(0), - D => p_12_out(1), - Q => \gpr1.dout_i_reg[5]\(1) + D => \^q\(1), + Q => \^gpr1.dout_i_reg[1]\(1) ); \gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE generic map( @@ -4006,8 +4155,8 @@ begin C => s_aclk, CE => E(0), CLR => AR(0), - D => \^q\(0), - Q => \gpr1.dout_i_reg[5]\(2) + D => \^q\(2), + Q => \^gpr1.dout_i_reg[1]\(2) ); \gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE generic map( @@ -4017,8 +4166,8 @@ begin C => s_aclk, CE => E(0), CLR => AR(0), - D => \^q\(1), - Q => \gpr1.dout_i_reg[5]\(3) + D => \^q\(3), + Q => \^gpr1.dout_i_reg[1]\(3) ); \gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE generic map( @@ -4028,8 +4177,8 @@ begin C => s_aclk, CE => E(0), CLR => AR(0), - D => \^q\(2), - Q => \gpr1.dout_i_reg[5]\(4) + D => \^q\(4), + Q => \^gpr1.dout_i_reg[1]\(4) ); \gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDPE generic map( @@ -4040,7 +4189,7 @@ begin CE => E(0), D => \plusOp__0\(0), PRE => AR(0), - Q => p_12_out(0) + Q => \^q\(0) ); \gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDCE generic map( @@ -4051,7 +4200,7 @@ begin CE => E(0), CLR => AR(0), D => \plusOp__0\(1), - Q => p_12_out(1) + Q => \^q\(1) ); \gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDCE generic map( @@ -4062,7 +4211,7 @@ begin CE => E(0), CLR => AR(0), D => \plusOp__0\(2), - Q => \^q\(0) + Q => \^q\(2) ); \gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDCE generic map( @@ -4073,7 +4222,7 @@ begin CE => E(0), CLR => AR(0), D => \plusOp__0\(3), - Q => \^q\(1) + Q => \^q\(3) ); \gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDCE generic map( @@ -4084,32 +4233,31 @@ begin CE => E(0), CLR => AR(0), D => \plusOp__0\(4), - Q => \^q\(2) + Q => \^q\(4) ); -ram_full_fb_i_i_1: unisim.vcomponents.LUT5 +ram_empty_fb_i_i_4: unisim.vcomponents.LUT6 generic map( - INIT => X"88F888C8" + INIT => X"0000000000009009" ) port map ( - I0 => \ram_full_fb_i_i_2__0_n_0\, - I1 => ram_empty_fb_i_reg, - I2 => \out\, - I3 => \grstd1.grst_full.grst_f.rst_d3_reg\, - I4 => \gc0.count_d1_reg[2]\, - O => ram_full_comb + I0 => \gc0.count_reg[4]\(2), + I1 => \^gpr1.dout_i_reg[1]\(2), + I2 => \gc0.count_reg[4]\(3), + I3 => \^gpr1.dout_i_reg[1]\(4), + I4 => ram_full_fb_i_reg, + I5 => ram_empty_fb_i_i_7_n_0, + O => ram_empty_fb_i_reg ); -\ram_full_fb_i_i_2__0\: unisim.vcomponents.LUT6 +ram_empty_fb_i_i_7: unisim.vcomponents.LUT4 generic map( - INIT => X"0000000090090000" + INIT => X"6FF6" ) port map ( - I0 => p_12_out(1), - I1 => \gc0.count_d1_reg[1]\(1), - I2 => p_12_out(0), - I3 => \gc0.count_d1_reg[1]\(0), - I4 => \gc0.count_d1_reg[2]_0\, - I5 => ram_full_i_reg, - O => \ram_full_fb_i_i_2__0_n_0\ + I0 => \^gpr1.dout_i_reg[1]\(1), + I1 => \gc0.count_reg[4]\(1), + I2 => \^gpr1.dout_i_reg[1]\(0), + I3 => \gc0.count_reg[4]\(0), + O => ram_empty_fb_i_i_7_n_0 ); end STRUCTURE; library IEEE; @@ -4121,22 +4269,10 @@ entity \Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr__parameterized0\ is ram_full_i_reg : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 8 downto 0 ); ram_full_i_reg_0 : out STD_LOGIC; - ram_full_i_reg_1 : out STD_LOGIC; - ram_full_i_reg_2 : out STD_LOGIC; ram_empty_i_reg : out STD_LOGIC; - ram_empty_i_reg_0 : out STD_LOGIC; - ram_empty_i_reg_1 : out STD_LOGIC; - ram_empty_i_reg_2 : out STD_LOGIC; - ram_full_i_reg_3 : out STD_LOGIC; - ram_full_i_reg_4 : out STD_LOGIC; - ram_full_i_reg_5 : out STD_LOGIC; - ram_full_i_reg_6 : out STD_LOGIC; - ram_empty_i_reg_3 : out STD_LOGIC; - ram_empty_i_reg_4 : out STD_LOGIC; - ram_empty_i_reg_5 : out STD_LOGIC; - ram_empty_i_reg_6 : out STD_LOGIC; - \gcc0.gc0.count_d1_reg[8]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - \gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \gcc0.gc0.count_d1_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); + v1_reg : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \gc0.count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); @@ -4149,25 +4285,25 @@ end \Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr__parameterized0\; architecture STRUCTURE of \Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr__parameterized0\ is signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \gcc0.gc0.count[8]_i_2_n_0\ : STD_LOGIC; - signal \^gcc0.gc0.count_d1_reg[8]_0\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal p_13_out : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \^gcc0.gc0.count_d1_reg[7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal p_13_out : STD_LOGIC_VECTOR ( 8 to 8 ); signal \plusOp__2\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1__0\ : label is "soft_lutpair14"; - attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1__0\ : label is "soft_lutpair14"; - attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1__0\ : label is "soft_lutpair13"; - attribute SOFT_HLUTNM of \gcc0.gc0.count[7]_i_1\ : label is "soft_lutpair12"; - attribute SOFT_HLUTNM of \gcc0.gc0.count[8]_i_1\ : label is "soft_lutpair12"; - attribute SOFT_HLUTNM of \gcc0.gc0.count[8]_i_2\ : label is "soft_lutpair13"; + attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1__0\ : label is "soft_lutpair15"; + attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1__0\ : label is "soft_lutpair15"; + attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1__0\ : label is "soft_lutpair14"; + attribute SOFT_HLUTNM of \gcc0.gc0.count[6]_i_1\ : label is "soft_lutpair13"; + attribute SOFT_HLUTNM of \gcc0.gc0.count[7]_i_1\ : label is "soft_lutpair13"; + attribute SOFT_HLUTNM of \gcc0.gc0.count[8]_i_2\ : label is "soft_lutpair14"; begin Q(8 downto 0) <= \^q\(8 downto 0); - \gcc0.gc0.count_d1_reg[8]_0\(0) <= \^gcc0.gc0.count_d1_reg[8]_0\(0); + \gcc0.gc0.count_d1_reg[7]_0\(7 downto 0) <= \^gcc0.gc0.count_d1_reg[7]_0\(7 downto 0); \gcc0.gc0.count[0]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( - I0 => p_13_out(0), + I0 => \^gcc0.gc0.count_d1_reg[7]_0\(0), O => \plusOp__2\(0) ); \gcc0.gc0.count[1]_i_1__0\: unisim.vcomponents.LUT2 @@ -4175,18 +4311,18 @@ begin INIT => X"6" ) port map ( - I0 => p_13_out(0), - I1 => p_13_out(1), + I0 => \^gcc0.gc0.count_d1_reg[7]_0\(1), + I1 => \^gcc0.gc0.count_d1_reg[7]_0\(0), O => \plusOp__2\(1) ); \gcc0.gc0.count[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( - INIT => X"78" + INIT => X"6A" ) port map ( - I0 => p_13_out(1), - I1 => p_13_out(0), - I2 => p_13_out(2), + I0 => \^gcc0.gc0.count_d1_reg[7]_0\(2), + I1 => \^gcc0.gc0.count_d1_reg[7]_0\(1), + I2 => \^gcc0.gc0.count_d1_reg[7]_0\(0), O => \plusOp__2\(2) ); \gcc0.gc0.count[3]_i_1__0\: unisim.vcomponents.LUT4 @@ -4194,80 +4330,82 @@ begin INIT => X"7F80" ) port map ( - I0 => p_13_out(2), - I1 => p_13_out(0), - I2 => p_13_out(1), - I3 => p_13_out(3), + I0 => \^gcc0.gc0.count_d1_reg[7]_0\(0), + I1 => \^gcc0.gc0.count_d1_reg[7]_0\(1), + I2 => \^gcc0.gc0.count_d1_reg[7]_0\(2), + I3 => \^gcc0.gc0.count_d1_reg[7]_0\(3), O => \plusOp__2\(3) ); \gcc0.gc0.count[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( - INIT => X"7FFF8000" + INIT => X"6AAAAAAA" ) port map ( - I0 => p_13_out(3), - I1 => p_13_out(1), - I2 => p_13_out(0), - I3 => p_13_out(2), - I4 => p_13_out(4), + I0 => \^gcc0.gc0.count_d1_reg[7]_0\(4), + I1 => \^gcc0.gc0.count_d1_reg[7]_0\(0), + I2 => \^gcc0.gc0.count_d1_reg[7]_0\(1), + I3 => \^gcc0.gc0.count_d1_reg[7]_0\(2), + I4 => \^gcc0.gc0.count_d1_reg[7]_0\(3), O => \plusOp__2\(4) ); \gcc0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"7FFFFFFF80000000" + INIT => X"6AAAAAAAAAAAAAAA" ) port map ( - I0 => p_13_out(4), - I1 => p_13_out(2), - I2 => p_13_out(0), - I3 => p_13_out(1), - I4 => p_13_out(3), - I5 => p_13_out(5), + I0 => \^gcc0.gc0.count_d1_reg[7]_0\(5), + I1 => \^gcc0.gc0.count_d1_reg[7]_0\(3), + I2 => \^gcc0.gc0.count_d1_reg[7]_0\(2), + I3 => \^gcc0.gc0.count_d1_reg[7]_0\(1), + I4 => \^gcc0.gc0.count_d1_reg[7]_0\(0), + I5 => \^gcc0.gc0.count_d1_reg[7]_0\(4), O => \plusOp__2\(5) ); -\gcc0.gc0.count[6]_i_1\: unisim.vcomponents.LUT3 +\gcc0.gc0.count[6]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"78" + INIT => X"6AAA" ) port map ( - I0 => p_13_out(5), - I1 => \gcc0.gc0.count[8]_i_2_n_0\, - I2 => p_13_out(6), + I0 => \^gcc0.gc0.count_d1_reg[7]_0\(6), + I1 => \^gcc0.gc0.count_d1_reg[7]_0\(4), + I2 => \gcc0.gc0.count[8]_i_2_n_0\, + I3 => \^gcc0.gc0.count_d1_reg[7]_0\(5), O => \plusOp__2\(6) ); -\gcc0.gc0.count[7]_i_1\: unisim.vcomponents.LUT4 +\gcc0.gc0.count[7]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"7F80" + INIT => X"6AAAAAAA" ) port map ( - I0 => \gcc0.gc0.count[8]_i_2_n_0\, - I1 => p_13_out(5), - I2 => p_13_out(6), - I3 => p_13_out(7), + I0 => \^gcc0.gc0.count_d1_reg[7]_0\(7), + I1 => \^gcc0.gc0.count_d1_reg[7]_0\(5), + I2 => \gcc0.gc0.count[8]_i_2_n_0\, + I3 => \^gcc0.gc0.count_d1_reg[7]_0\(4), + I4 => \^gcc0.gc0.count_d1_reg[7]_0\(6), O => \plusOp__2\(7) ); -\gcc0.gc0.count[8]_i_1\: unisim.vcomponents.LUT5 +\gcc0.gc0.count[8]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"7FFF8000" + INIT => X"6AAAAAAAAAAAAAAA" ) port map ( - I0 => \gcc0.gc0.count[8]_i_2_n_0\, - I1 => p_13_out(7), - I2 => p_13_out(6), - I3 => p_13_out(5), - I4 => \^gcc0.gc0.count_d1_reg[8]_0\(0), + I0 => p_13_out(8), + I1 => \^gcc0.gc0.count_d1_reg[7]_0\(6), + I2 => \^gcc0.gc0.count_d1_reg[7]_0\(4), + I3 => \gcc0.gc0.count[8]_i_2_n_0\, + I4 => \^gcc0.gc0.count_d1_reg[7]_0\(5), + I5 => \^gcc0.gc0.count_d1_reg[7]_0\(7), O => \plusOp__2\(8) ); -\gcc0.gc0.count[8]_i_2\: unisim.vcomponents.LUT5 +\gcc0.gc0.count[8]_i_2\: unisim.vcomponents.LUT4 generic map( - INIT => X"80000000" + INIT => X"8000" ) port map ( - I0 => p_13_out(3), - I1 => p_13_out(1), - I2 => p_13_out(0), - I3 => p_13_out(2), - I4 => p_13_out(4), + I0 => \^gcc0.gc0.count_d1_reg[7]_0\(3), + I1 => \^gcc0.gc0.count_d1_reg[7]_0\(2), + I2 => \^gcc0.gc0.count_d1_reg[7]_0\(1), + I3 => \^gcc0.gc0.count_d1_reg[7]_0\(0), O => \gcc0.gc0.count[8]_i_2_n_0\ ); \gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDRE @@ -4277,7 +4415,7 @@ begin port map ( C => s_aclk, CE => E(0), - D => p_13_out(0), + D => \^gcc0.gc0.count_d1_reg[7]_0\(0), Q => \^q\(0), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); @@ -4288,7 +4426,7 @@ begin port map ( C => s_aclk, CE => E(0), - D => p_13_out(1), + D => \^gcc0.gc0.count_d1_reg[7]_0\(1), Q => \^q\(1), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); @@ -4299,7 +4437,7 @@ begin port map ( C => s_aclk, CE => E(0), - D => p_13_out(2), + D => \^gcc0.gc0.count_d1_reg[7]_0\(2), Q => \^q\(2), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); @@ -4310,7 +4448,7 @@ begin port map ( C => s_aclk, CE => E(0), - D => p_13_out(3), + D => \^gcc0.gc0.count_d1_reg[7]_0\(3), Q => \^q\(3), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); @@ -4321,7 +4459,7 @@ begin port map ( C => s_aclk, CE => E(0), - D => p_13_out(4), + D => \^gcc0.gc0.count_d1_reg[7]_0\(4), Q => \^q\(4), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); @@ -4332,7 +4470,7 @@ begin port map ( C => s_aclk, CE => E(0), - D => p_13_out(5), + D => \^gcc0.gc0.count_d1_reg[7]_0\(5), Q => \^q\(5), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); @@ -4343,7 +4481,7 @@ begin port map ( C => s_aclk, CE => E(0), - D => p_13_out(6), + D => \^gcc0.gc0.count_d1_reg[7]_0\(6), Q => \^q\(6), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); @@ -4354,7 +4492,7 @@ begin port map ( C => s_aclk, CE => E(0), - D => p_13_out(7), + D => \^gcc0.gc0.count_d1_reg[7]_0\(7), Q => \^q\(7), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); @@ -4365,7 +4503,7 @@ begin port map ( C => s_aclk, CE => E(0), - D => \^gcc0.gc0.count_d1_reg[8]_0\(0), + D => p_13_out(8), Q => \^q\(8), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); @@ -4377,7 +4515,7 @@ begin C => s_aclk, CE => E(0), D => \plusOp__2\(0), - Q => p_13_out(0), + Q => \^gcc0.gc0.count_d1_reg[7]_0\(0), S => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); \gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDRE @@ -4388,7 +4526,7 @@ begin C => s_aclk, CE => E(0), D => \plusOp__2\(1), - Q => p_13_out(1), + Q => \^gcc0.gc0.count_d1_reg[7]_0\(1), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); \gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDRE @@ -4399,7 +4537,7 @@ begin C => s_aclk, CE => E(0), D => \plusOp__2\(2), - Q => p_13_out(2), + Q => \^gcc0.gc0.count_d1_reg[7]_0\(2), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); \gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDRE @@ -4410,7 +4548,7 @@ begin C => s_aclk, CE => E(0), D => \plusOp__2\(3), - Q => p_13_out(3), + Q => \^gcc0.gc0.count_d1_reg[7]_0\(3), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); \gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDRE @@ -4421,7 +4559,7 @@ begin C => s_aclk, CE => E(0), D => \plusOp__2\(4), - Q => p_13_out(4), + Q => \^gcc0.gc0.count_d1_reg[7]_0\(4), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); \gcc0.gc0.count_reg[5]\: unisim.vcomponents.FDRE @@ -4432,7 +4570,7 @@ begin C => s_aclk, CE => E(0), D => \plusOp__2\(5), - Q => p_13_out(5), + Q => \^gcc0.gc0.count_d1_reg[7]_0\(5), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); \gcc0.gc0.count_reg[6]\: unisim.vcomponents.FDRE @@ -4443,7 +4581,7 @@ begin C => s_aclk, CE => E(0), D => \plusOp__2\(6), - Q => p_13_out(6), + Q => \^gcc0.gc0.count_d1_reg[7]_0\(6), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); \gcc0.gc0.count_reg[7]\: unisim.vcomponents.FDRE @@ -4454,7 +4592,7 @@ begin C => s_aclk, CE => E(0), D => \plusOp__2\(7), - Q => p_13_out(7), + Q => \^gcc0.gc0.count_d1_reg[7]_0\(7), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); \gcc0.gc0.count_reg[8]\: unisim.vcomponents.FDRE @@ -4465,20 +4603,9 @@ begin C => s_aclk, CE => E(0), D => \plusOp__2\(8), - Q => \^gcc0.gc0.count_d1_reg[8]_0\(0), + Q => p_13_out(8), R => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ ); -\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9009" - ) - port map ( - I0 => \^q\(1), - I1 => \gc0.count_d1_reg[7]\(1), - I2 => \^q\(0), - I3 => \gc0.count_d1_reg[7]\(0), - O => ram_full_i_reg_2 - ); \gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" @@ -4488,161 +4615,67 @@ begin I1 => \gc0.count_reg[7]\(0), I2 => \^q\(1), I3 => \gc0.count_reg[7]\(1), - O => ram_empty_i_reg_2 - ); -\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9009" - ) - port map ( - I0 => p_13_out(1), - I1 => \gc0.count_d1_reg[7]\(1), - I2 => p_13_out(0), - I3 => \gc0.count_d1_reg[7]\(0), - O => ram_full_i_reg_6 - ); -\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9009" - ) - port map ( - I0 => \^q\(1), - I1 => \gc0.count_d1_reg[7]\(1), - I2 => \^q\(0), - I3 => \gc0.count_d1_reg[7]\(0), - O => ram_empty_i_reg_3 - ); -\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9009" - ) - port map ( - I0 => \^q\(2), - I1 => \gc0.count_d1_reg[7]\(2), - I2 => \^q\(3), - I3 => \gc0.count_d1_reg[7]\(3), - O => ram_full_i_reg_1 + O => v1_reg(0) ); \gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9009" - ) - port map ( - I0 => \^q\(3), - I1 => \gc0.count_reg[7]\(3), - I2 => \^q\(2), - I3 => \gc0.count_reg[7]\(2), - O => ram_empty_i_reg_1 - ); -\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9009" - ) - port map ( - I0 => p_13_out(3), - I1 => \gc0.count_d1_reg[7]\(3), - I2 => p_13_out(2), - I3 => \gc0.count_d1_reg[7]\(2), - O => ram_full_i_reg_5 - ); -\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => \^q\(2), - I1 => \gc0.count_d1_reg[7]\(2), + I1 => \gc0.count_reg[7]\(2), I2 => \^q\(3), - I3 => \gc0.count_d1_reg[7]\(3), - O => ram_empty_i_reg_4 - ); -\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9009" - ) - port map ( - I0 => \^q\(5), - I1 => \gc0.count_d1_reg[7]\(5), - I2 => \^q\(4), - I3 => \gc0.count_d1_reg[7]\(4), - O => ram_full_i_reg_0 + I3 => \gc0.count_reg[7]\(3), + O => v1_reg(1) ); \gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9009" - ) - port map ( - I0 => \^q\(4), - I1 => \gc0.count_reg[7]\(4), - I2 => \^q\(5), - I3 => \gc0.count_reg[7]\(5), - O => ram_empty_i_reg_0 - ); -\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"9009" - ) - port map ( - I0 => p_13_out(5), - I1 => \gc0.count_d1_reg[7]\(5), - I2 => p_13_out(4), - I3 => \gc0.count_d1_reg[7]\(4), - O => ram_full_i_reg_4 - ); -\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( I0 => \^q\(5), - I1 => \gc0.count_d1_reg[7]\(5), + I1 => \gc0.count_reg[7]\(5), I2 => \^q\(4), - I3 => \gc0.count_d1_reg[7]\(4), - O => ram_empty_i_reg_5 + I3 => \gc0.count_reg[7]\(4), + O => v1_reg(2) ); -\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4 +\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( - I0 => \^q\(6), - I1 => \gc0.count_d1_reg[7]\(6), - I2 => \^q\(7), - I3 => \gc0.count_d1_reg[7]\(7), - O => ram_full_i_reg + I0 => \^q\(7), + I1 => \gc0.count_reg[7]\(7), + I2 => \^q\(6), + I3 => \gc0.count_reg[7]\(6), + O => v1_reg(3) ); -\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4 +\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT2 generic map( - INIT => X"9009" + INIT => X"9" ) port map ( - I0 => \^q\(6), - I1 => \gc0.count_reg[7]\(6), - I2 => \^q\(7), - I3 => \gc0.count_reg[7]\(7), - O => ram_empty_i_reg + I0 => \^q\(8), + I1 => \gc0.count_d1_reg[8]\(0), + O => ram_full_i_reg ); -\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4 +\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT2 generic map( - INIT => X"9009" + INIT => X"9" ) port map ( - I0 => p_13_out(7), - I1 => \gc0.count_d1_reg[7]\(7), - I2 => p_13_out(6), - I3 => \gc0.count_d1_reg[7]\(6), - O => ram_full_i_reg_3 + I0 => p_13_out(8), + I1 => \gc0.count_d1_reg[8]\(0), + O => ram_full_i_reg_0 ); -\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4 +\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT2 generic map( - INIT => X"9009" + INIT => X"9" ) port map ( - I0 => \^q\(6), - I1 => \gc0.count_d1_reg[7]\(6), - I2 => \^q\(7), - I3 => \gc0.count_d1_reg[7]\(7), - O => ram_empty_i_reg_6 + I0 => \^q\(8), + I1 => \gc0.count_d1_reg[8]\(0), + O => ram_empty_i_reg ); end STRUCTURE; library IEEE; @@ -4652,13 +4685,15 @@ use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20_s00_data_fifo_0_wr_status_flags_ss is port ( \out\ : out STD_LOGIC; - s_axi_arready : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_arready : out STD_LOGIC; ram_empty_fb_i_reg : out STD_LOGIC; ram_full_comb : in STD_LOGIC; s_aclk : in STD_LOGIC; \grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC; - s_axi_arvalid : in STD_LOGIC + s_axi_arvalid : in STD_LOGIC; + \gcc0.gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gc0.count_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end Arty_Z7_20_s00_data_fifo_0_wr_status_flags_ss; @@ -4684,12 +4719,12 @@ begin \out\ <= ram_full_fb_i; \gcc0.gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"10" + INIT => X"04" ) port map ( - I0 => ram_full_fb_i, - I1 => ram_full_i, - I2 => s_axi_arvalid, + I0 => ram_full_i, + I1 => s_axi_arvalid, + I2 => ram_full_fb_i, O => E(0) ); i_0: unisim.vcomponents.LUT1 @@ -4708,14 +4743,16 @@ i_1: unisim.vcomponents.LUT1 I0 => '1', O => ram_afull_fb ); -ram_empty_fb_i_i_4: unisim.vcomponents.LUT3 +ram_empty_fb_i_i_6: unisim.vcomponents.LUT5 generic map( - INIT => X"FD" + INIT => X"04FFFF04" ) port map ( - I0 => s_axi_arvalid, - I1 => ram_full_i, - I2 => ram_full_fb_i, + I0 => ram_full_fb_i, + I1 => s_axi_arvalid, + I2 => ram_full_i, + I3 => \gcc0.gc0.count_d1_reg[3]\(0), + I4 => \gc0.count_reg[3]\(0), O => ram_empty_fb_i_reg ); ram_full_fb_i_reg: unisim.vcomponents.FDPE @@ -4788,42 +4825,46 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20_s00_data_fifo_0_memory is port ( - S : out STD_LOGIC_VECTOR ( 3 downto 0 ); - Q : out STD_LOGIC_VECTOR ( 55 downto 0 ); + Q : out STD_LOGIC_VECTOR ( 62 downto 0 ); D : out STD_LOGIC_VECTOR ( 9 downto 0 ); - DI : out STD_LOGIC_VECTOR ( 0 to 0 ); aempty_fwft_i_reg : out STD_LOGIC; - \gfwd_rev_pipeline1.s_ready_i_reg\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); - \gfwd_rev_pipeline1.s_ready_i_reg_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - \out\ : in STD_LOGIC; - CO : in STD_LOGIC_VECTOR ( 0 to 0 ); - arready_pkt : in STD_LOGIC; - s_axi_rready : in STD_LOGIC; - empty_fwft_fb_o_i_reg : in STD_LOGIC; + S : out STD_LOGIC_VECTOR ( 3 downto 0 ); + DI : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); - rd_fifo_free_space : in STD_LOGIC_VECTOR ( 9 downto 0 ); empty_fwft_i_reg : in STD_LOGIC; - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + rd_fifo_free_space : in STD_LOGIC_VECTOR ( 9 downto 0 ); + CO : in STD_LOGIC_VECTOR ( 0 to 0 ); + arready_pkt : in STD_LOGIC; + \out\ : in STD_LOGIC; + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); empty_fwft_i_reg_0 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); s_aclk : in STD_LOGIC; - ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); - UNCONN_IN : in STD_LOGIC_VECTOR ( 55 downto 0 ); + EN : in STD_LOGIC; + UNCONN_IN : in STD_LOGIC_VECTOR ( 62 downto 0 ); \gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); \gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); - \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ram_empty_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end Arty_Z7_20_s00_data_fifo_0_memory; architecture STRUCTURE of Arty_Z7_20_s00_data_fifo_0_memory is - signal \^q\ : STD_LOGIC_VECTOR ( 55 downto 0 ); - signal dout_i : STD_LOGIC_VECTOR ( 59 downto 4 ); + signal \^q\ : STD_LOGIC_VECTOR ( 62 downto 0 ); + signal \_carry__0_i_5_n_0\ : STD_LOGIC; + signal \_carry__0_i_6_n_0\ : STD_LOGIC; + signal \_carry__0_i_7_n_0\ : STD_LOGIC; + signal dout_i : STD_LOGIC_VECTOR ( 62 downto 0 ); signal \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[3]_i_3_n_0\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[3]_i_4_n_0\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[3]_i_5_n_0\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[3]_i_6_n_0\ : STD_LOGIC; + signal \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_3_n_0\ : STD_LOGIC; + signal \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_4_n_0\ : STD_LOGIC; + signal \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_5_n_0\ : STD_LOGIC; + signal \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_6_n_0\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_i_2_n_0\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_i_2_n_1\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_i_2_n_2\ : STD_LOGIC; @@ -4832,79 +4873,254 @@ architecture STRUCTURE of Arty_Z7_20_s00_data_fifo_0_memory is signal \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_i_2_n_1\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_i_2_n_2\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_i_2_n_3\ : STD_LOGIC; - signal \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_i_4_n_3\ : STD_LOGIC; + signal \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_i_3_n_3\ : STD_LOGIC; signal minusOp : STD_LOGIC_VECTOR ( 9 downto 0 ); - signal \NLW_gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_i_4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW_gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_i_4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[0]_i_1\ : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of \_carry__0_i_6\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \_carry__0_i_7\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[0]_i_1\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[1]_i_1\ : label is "soft_lutpair8"; - attribute SOFT_HLUTNM of \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[2]_i_1\ : label is "soft_lutpair7"; - attribute SOFT_HLUTNM of \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[3]_i_1\ : label is "soft_lutpair7"; - attribute SOFT_HLUTNM of \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[4]_i_1\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[2]_i_1\ : label is "soft_lutpair9"; + attribute SOFT_HLUTNM of \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[3]_i_1\ : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[4]_i_1\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[5]_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[6]_i_1\ : label is "soft_lutpair6"; - attribute SOFT_HLUTNM of \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_1\ : label is "soft_lutpair5"; - attribute SOFT_HLUTNM of \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[8]_i_1\ : label is "soft_lutpair4"; - attribute SOFT_HLUTNM of \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[9]_i_2\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_1\ : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[8]_i_1\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[9]_i_2\ : label is "soft_lutpair5"; attribute METHODOLOGY_DRC_VIOS : string; attribute METHODOLOGY_DRC_VIOS of \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_i_2\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_i_2\ : label is "{SYNTH-8 {cell *THIS*}}"; - attribute METHODOLOGY_DRC_VIOS of \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_i_4\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_i_3\ : label is "{SYNTH-8 {cell *THIS*}}"; begin - Q(55 downto 0) <= \^q\(55 downto 0); -arvalid_en0_carry_i_3: unisim.vcomponents.LUT4 + Q(62 downto 0) <= \^q\(62 downto 0); +\_carry__0_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"22B2" + INIT => X"9AFF6500" ) port map ( - I0 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(3), + I0 => \^q\(29), + I1 => \_carry__0_i_5_n_0\, + I2 => \^q\(28), + I3 => empty_fwft_i_reg_0, + I4 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(7), + O => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\(3) + ); +\_carry__0_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9F60" + ) + port map ( + I0 => \^q\(28), + I1 => \_carry__0_i_5_n_0\, + I2 => empty_fwft_i_reg_0, + I3 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(6), + O => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\(2) + ); +\_carry__0_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9F60" + ) + port map ( + I0 => \^q\(27), + I1 => \_carry__0_i_6_n_0\, + I2 => empty_fwft_i_reg_0, + I3 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(5), + O => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\(1) + ); +\_carry__0_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9F60" + ) + port map ( + I0 => \^q\(26), + I1 => \_carry__0_i_7_n_0\, + I2 => empty_fwft_i_reg_0, + I3 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(4), + O => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\(0) + ); +\_carry__0_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFFFFFFFFFFFFFF" + ) + port map ( + I0 => \^q\(26), + I1 => \^q\(24), + I2 => \^q\(23), + I3 => \^q\(22), + I4 => \^q\(25), + I5 => \^q\(27), + O => \_carry__0_i_5_n_0\ + ); +\_carry__0_i_6\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFFFFFF" + ) + port map ( + I0 => \^q\(25), + I1 => \^q\(22), + I2 => \^q\(23), + I3 => \^q\(24), + I4 => \^q\(26), + O => \_carry__0_i_6_n_0\ + ); +\_carry__0_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => \^q\(24), + I1 => \^q\(23), + I2 => \^q\(22), + I3 => \^q\(25), + O => \_carry__0_i_7_n_0\ + ); +\_carry__1_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"40FFBF00" + ) + port map ( + I0 => \_carry__0_i_5_n_0\, + I1 => \^q\(28), + I2 => \^q\(29), + I3 => empty_fwft_i_reg_0, + I4 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(8), + O => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(0) + ); +\_carry_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"6AAAFFFF95550000" + ) + port map ( + I0 => \^q\(25), + I1 => \^q\(24), + I2 => \^q\(23), + I3 => \^q\(22), + I4 => empty_fwft_i_reg_0, + I5 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(3), + O => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]\(2) + ); +\_carry_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AFF9500" + ) + port map ( + I0 => \^q\(24), + I1 => \^q\(22), + I2 => \^q\(23), + I3 => empty_fwft_i_reg_0, + I4 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(2), + O => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]\(1) + ); +\_carry_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6F90" + ) + port map ( + I0 => \^q\(23), I1 => \^q\(22), - I2 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(2), - I3 => \^q\(21), - O => \gfwd_rev_pipeline1.s_ready_i_reg\(1) + I2 => empty_fwft_i_reg_0, + I3 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(1), + O => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]\(0) + ); +arvalid_en0_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(6), + I1 => \^q\(28), + I2 => \^q\(29), + I3 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(7), + O => DI(3) + ); +arvalid_en0_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(4), + I1 => \^q\(26), + I2 => \^q\(27), + I3 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(5), + O => DI(2) + ); +arvalid_en0_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(2), + I1 => \^q\(24), + I2 => \^q\(25), + I3 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(3), + O => DI(1) ); arvalid_en0_carry_i_4: unisim.vcomponents.LUT4 generic map( - INIT => X"22B2" + INIT => X"2F02" ) port map ( - I0 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(1), - I1 => \^q\(20), - I2 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(0), - I3 => \^q\(19), - O => \gfwd_rev_pipeline1.s_ready_i_reg\(0) + I0 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(0), + I1 => \^q\(22), + I2 => \^q\(23), + I3 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(1), + O => DI(0) + ); +arvalid_en0_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \^q\(28), + I1 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(6), + I2 => \^q\(29), + I3 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(7), + O => S(3) + ); +arvalid_en0_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \^q\(26), + I1 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(4), + I2 => \^q\(27), + I3 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(5), + O => S(2) ); arvalid_en0_carry_i_7: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( - I0 => \^q\(22), - I1 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(3), - I2 => \^q\(21), - I3 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(2), - O => \gfwd_rev_pipeline1.s_ready_i_reg_0\(1) + I0 => \^q\(24), + I1 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(2), + I2 => \^q\(25), + I3 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(3), + O => S(1) ); arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 generic map( INIT => X"9009" ) port map ( - I0 => \^q\(20), - I1 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(1), - I2 => \^q\(19), - I3 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(0), - O => \gfwd_rev_pipeline1.s_ready_i_reg_0\(0) + I0 => \^q\(22), + I1 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(0), + I2 => \^q\(23), + I3 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(1), + O => S(0) ); \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( - I0 => rd_fifo_free_space(0), + I0 => minusOp(0), I1 => empty_fwft_i_reg, - I2 => minusOp(0), + I2 => rd_fifo_free_space(0), O => D(0) ); \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[1]_i_1\: unisim.vcomponents.LUT3 @@ -4912,9 +5128,9 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 INIT => X"B8" ) port map ( - I0 => rd_fifo_free_space(1), + I0 => minusOp(1), I1 => empty_fwft_i_reg, - I2 => minusOp(1), + I2 => rd_fifo_free_space(1), O => D(1) ); \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[2]_i_1\: unisim.vcomponents.LUT3 @@ -4922,9 +5138,9 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 INIT => X"B8" ) port map ( - I0 => rd_fifo_free_space(2), + I0 => minusOp(2), I1 => empty_fwft_i_reg, - I2 => minusOp(2), + I2 => rd_fifo_free_space(2), O => D(2) ); \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[3]_i_1\: unisim.vcomponents.LUT3 @@ -4932,9 +5148,9 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 INIT => X"B8" ) port map ( - I0 => rd_fifo_free_space(3), + I0 => minusOp(3), I1 => empty_fwft_i_reg, - I2 => minusOp(3), + I2 => rd_fifo_free_space(3), O => D(3) ); \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[3]_i_3\: unisim.vcomponents.LUT2 @@ -4943,7 +5159,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 ) port map ( I0 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(3), - I1 => \^q\(22), + I1 => \^q\(25), O => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[3]_i_3_n_0\ ); \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[3]_i_4\: unisim.vcomponents.LUT2 @@ -4952,7 +5168,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 ) port map ( I0 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(2), - I1 => \^q\(21), + I1 => \^q\(24), O => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[3]_i_4_n_0\ ); \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[3]_i_5\: unisim.vcomponents.LUT2 @@ -4961,7 +5177,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 ) port map ( I0 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(1), - I1 => \^q\(20), + I1 => \^q\(23), O => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[3]_i_5_n_0\ ); \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[3]_i_6\: unisim.vcomponents.LUT2 @@ -4970,57 +5186,93 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 ) port map ( I0 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(0), - I1 => \^q\(19), + I1 => \^q\(22), O => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[3]_i_6_n_0\ ); \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[4]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"B8" + INIT => X"B8" + ) + port map ( + I0 => minusOp(4), + I1 => empty_fwft_i_reg, + I2 => rd_fifo_free_space(4), + O => D(4) + ); +\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => minusOp(5), + I1 => empty_fwft_i_reg, + I2 => rd_fifo_free_space(5), + O => D(5) + ); +\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => minusOp(6), + I1 => empty_fwft_i_reg, + I2 => rd_fifo_free_space(6), + O => D(6) + ); +\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => minusOp(7), + I1 => empty_fwft_i_reg, + I2 => rd_fifo_free_space(7), + O => D(7) + ); +\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" ) port map ( - I0 => rd_fifo_free_space(4), - I1 => empty_fwft_i_reg, - I2 => minusOp(4), - O => D(4) + I0 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(7), + I1 => \^q\(29), + O => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_3_n_0\ ); -\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[5]_i_1\: unisim.vcomponents.LUT3 +\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_4\: unisim.vcomponents.LUT2 generic map( - INIT => X"B8" + INIT => X"9" ) port map ( - I0 => rd_fifo_free_space(5), - I1 => empty_fwft_i_reg, - I2 => minusOp(5), - O => D(5) + I0 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(6), + I1 => \^q\(28), + O => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_4_n_0\ ); -\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[6]_i_1\: unisim.vcomponents.LUT3 +\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_5\: unisim.vcomponents.LUT2 generic map( - INIT => X"B8" + INIT => X"9" ) port map ( - I0 => rd_fifo_free_space(6), - I1 => empty_fwft_i_reg, - I2 => minusOp(6), - O => D(6) + I0 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(5), + I1 => \^q\(27), + O => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_5_n_0\ ); -\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_1\: unisim.vcomponents.LUT3 +\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_6\: unisim.vcomponents.LUT2 generic map( - INIT => X"B8" + INIT => X"9" ) port map ( - I0 => rd_fifo_free_space(7), - I1 => empty_fwft_i_reg, - I2 => minusOp(7), - O => D(7) + I0 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(4), + I1 => \^q\(26), + O => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_6_n_0\ ); \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( - I0 => rd_fifo_free_space(8), + I0 => minusOp(8), I1 => empty_fwft_i_reg, - I2 => minusOp(8), + I2 => rd_fifo_free_space(8), O => D(8) ); \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[9]_i_2\: unisim.vcomponents.LUT3 @@ -5028,9 +5280,9 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 INIT => X"B8" ) port map ( - I0 => rd_fifo_free_space(9), + I0 => minusOp(9), I1 => empty_fwft_i_reg, - I2 => minusOp(9), + I2 => rd_fifo_free_space(9), O => D(9) ); \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_i_2\: unisim.vcomponents.CARRY4 @@ -5058,41 +5310,55 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 CYINIT => '0', DI(3 downto 0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(7 downto 4), O(3 downto 0) => minusOp(7 downto 4), - S(3 downto 0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_0\(3 downto 0) + S(3) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_3_n_0\, + S(2) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_4_n_0\, + S(1) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_5_n_0\, + S(0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_6_n_0\ ); -\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_i_4\: unisim.vcomponents.CARRY4 +\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_i_2_n_0\, - CO(3 downto 1) => \NLW_gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_i_4_CO_UNCONNECTED\(3 downto 1), - CO(0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_i_4_n_3\, + CO(3 downto 1) => \NLW_gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_i_3_CO_UNCONNECTED\(3 downto 1), + CO(0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_i_3_n_3\, CYINIT => '0', DI(3 downto 1) => B"000", DI(0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(8), - O(3 downto 2) => \NLW_gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_i_4_O_UNCONNECTED\(3 downto 2), + O(3 downto 2) => \NLW_gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_i_3_O_UNCONNECTED\(3 downto 2), O(1 downto 0) => minusOp(9 downto 8), S(3 downto 2) => B"00", - S(1 downto 0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(1 downto 0) + S(1 downto 0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0\(1 downto 0) ); \gdm.dm_gen.dm\: entity work.Arty_Z7_20_s00_data_fifo_0_dmem port map ( - UNCONN_IN(55 downto 0) => UNCONN_IN(55 downto 0), - dout_i(55 downto 0) => dout_i(59 downto 4), + EN => EN, + UNCONN_IN(62 downto 0) => UNCONN_IN(62 downto 0), + dout_i(62 downto 0) => dout_i(62 downto 0), \gc0.count_d1_reg[4]\(4 downto 0) => \gc0.count_d1_reg[4]\(4 downto 0), \gcc0.gc0.count_d1_reg[4]\(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0), - \gpregsm1.curr_fwft_state_reg[0]\(0) => \gpregsm1.curr_fwft_state_reg[0]\(0), - ram_full_fb_i_reg(0) => ram_full_fb_i_reg(0), + ram_empty_fb_i_reg(0) => ram_empty_fb_i_reg(0), s_aclk => s_aclk ); \gfwd_rev_pipeline1.m_valid_i_i_2\: unisim.vcomponents.LUT3 generic map( - INIT => X"F7" + INIT => X"08" ) port map ( - I0 => arready_pkt, - I1 => CO(0), + I0 => CO(0), + I1 => arready_pkt, I2 => \out\, O => aempty_fwft_i_reg ); +\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_aclk, + CE => E(0), + D => dout_i(0), + Q => \^q\(0), + R => '0' + ); \goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' @@ -5101,7 +5367,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(10), - Q => \^q\(6), + Q => \^q\(10), R => '0' ); \goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDRE @@ -5112,7 +5378,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(11), - Q => \^q\(7), + Q => \^q\(11), R => '0' ); \goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDRE @@ -5123,7 +5389,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(12), - Q => \^q\(8), + Q => \^q\(12), R => '0' ); \goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDRE @@ -5134,7 +5400,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(13), - Q => \^q\(9), + Q => \^q\(13), R => '0' ); \goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDRE @@ -5145,7 +5411,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(14), - Q => \^q\(10), + Q => \^q\(14), R => '0' ); \goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDRE @@ -5156,7 +5422,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(15), - Q => \^q\(11), + Q => \^q\(15), R => '0' ); \goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDRE @@ -5167,7 +5433,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(16), - Q => \^q\(12), + Q => \^q\(16), R => '0' ); \goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDRE @@ -5178,7 +5444,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(17), - Q => \^q\(13), + Q => \^q\(17), R => '0' ); \goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDRE @@ -5189,7 +5455,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(18), - Q => \^q\(14), + Q => \^q\(18), R => '0' ); \goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDRE @@ -5200,7 +5466,18 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(19), - Q => \^q\(15), + Q => \^q\(19), + R => '0' + ); +\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_aclk, + CE => E(0), + D => dout_i(1), + Q => \^q\(1), R => '0' ); \goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDRE @@ -5211,7 +5488,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(20), - Q => \^q\(16), + Q => \^q\(20), R => '0' ); \goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDRE @@ -5222,7 +5499,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(21), - Q => \^q\(17), + Q => \^q\(21), R => '0' ); \goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDRE @@ -5233,7 +5510,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(22), - Q => \^q\(18), + Q => \^q\(22), R => '0' ); \goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDRE @@ -5244,7 +5521,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(23), - Q => \^q\(19), + Q => \^q\(23), R => '0' ); \goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDRE @@ -5255,7 +5532,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(24), - Q => \^q\(20), + Q => \^q\(24), R => '0' ); \goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDRE @@ -5266,7 +5543,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(25), - Q => \^q\(21), + Q => \^q\(25), R => '0' ); \goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDRE @@ -5277,7 +5554,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(26), - Q => \^q\(22), + Q => \^q\(26), R => '0' ); \goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDRE @@ -5288,7 +5565,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(27), - Q => \^q\(23), + Q => \^q\(27), R => '0' ); \goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDRE @@ -5299,7 +5576,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(28), - Q => \^q\(24), + Q => \^q\(28), R => '0' ); \goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDRE @@ -5310,7 +5587,18 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(29), - Q => \^q\(25), + Q => \^q\(29), + R => '0' + ); +\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_aclk, + CE => E(0), + D => dout_i(2), + Q => \^q\(2), R => '0' ); \goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDRE @@ -5321,7 +5609,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(30), - Q => \^q\(26), + Q => \^q\(30), R => '0' ); \goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDRE @@ -5332,7 +5620,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(31), - Q => \^q\(27), + Q => \^q\(31), R => '0' ); \goreg_dm.dout_i_reg[32]\: unisim.vcomponents.FDRE @@ -5343,7 +5631,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(32), - Q => \^q\(28), + Q => \^q\(32), R => '0' ); \goreg_dm.dout_i_reg[33]\: unisim.vcomponents.FDRE @@ -5354,7 +5642,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(33), - Q => \^q\(29), + Q => \^q\(33), R => '0' ); \goreg_dm.dout_i_reg[34]\: unisim.vcomponents.FDRE @@ -5365,7 +5653,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(34), - Q => \^q\(30), + Q => \^q\(34), R => '0' ); \goreg_dm.dout_i_reg[35]\: unisim.vcomponents.FDRE @@ -5376,7 +5664,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(35), - Q => \^q\(31), + Q => \^q\(35), R => '0' ); \goreg_dm.dout_i_reg[36]\: unisim.vcomponents.FDRE @@ -5387,7 +5675,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(36), - Q => \^q\(32), + Q => \^q\(36), R => '0' ); \goreg_dm.dout_i_reg[37]\: unisim.vcomponents.FDRE @@ -5398,7 +5686,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(37), - Q => \^q\(33), + Q => \^q\(37), R => '0' ); \goreg_dm.dout_i_reg[38]\: unisim.vcomponents.FDRE @@ -5409,7 +5697,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(38), - Q => \^q\(34), + Q => \^q\(38), R => '0' ); \goreg_dm.dout_i_reg[39]\: unisim.vcomponents.FDRE @@ -5420,7 +5708,18 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(39), - Q => \^q\(35), + Q => \^q\(39), + R => '0' + ); +\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_aclk, + CE => E(0), + D => dout_i(3), + Q => \^q\(3), R => '0' ); \goreg_dm.dout_i_reg[40]\: unisim.vcomponents.FDRE @@ -5431,7 +5730,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(40), - Q => \^q\(36), + Q => \^q\(40), R => '0' ); \goreg_dm.dout_i_reg[41]\: unisim.vcomponents.FDRE @@ -5442,7 +5741,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(41), - Q => \^q\(37), + Q => \^q\(41), R => '0' ); \goreg_dm.dout_i_reg[42]\: unisim.vcomponents.FDRE @@ -5453,7 +5752,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(42), - Q => \^q\(38), + Q => \^q\(42), R => '0' ); \goreg_dm.dout_i_reg[43]\: unisim.vcomponents.FDRE @@ -5464,7 +5763,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(43), - Q => \^q\(39), + Q => \^q\(43), R => '0' ); \goreg_dm.dout_i_reg[44]\: unisim.vcomponents.FDRE @@ -5475,7 +5774,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(44), - Q => \^q\(40), + Q => \^q\(44), R => '0' ); \goreg_dm.dout_i_reg[45]\: unisim.vcomponents.FDRE @@ -5486,7 +5785,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(45), - Q => \^q\(41), + Q => \^q\(45), R => '0' ); \goreg_dm.dout_i_reg[46]\: unisim.vcomponents.FDRE @@ -5497,7 +5796,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(46), - Q => \^q\(42), + Q => \^q\(46), R => '0' ); \goreg_dm.dout_i_reg[47]\: unisim.vcomponents.FDRE @@ -5508,7 +5807,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(47), - Q => \^q\(43), + Q => \^q\(47), R => '0' ); \goreg_dm.dout_i_reg[48]\: unisim.vcomponents.FDRE @@ -5519,7 +5818,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(48), - Q => \^q\(44), + Q => \^q\(48), R => '0' ); \goreg_dm.dout_i_reg[49]\: unisim.vcomponents.FDRE @@ -5530,7 +5829,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(49), - Q => \^q\(45), + Q => \^q\(49), R => '0' ); \goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDRE @@ -5541,7 +5840,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(4), - Q => \^q\(0), + Q => \^q\(4), R => '0' ); \goreg_dm.dout_i_reg[50]\: unisim.vcomponents.FDRE @@ -5552,7 +5851,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(50), - Q => \^q\(46), + Q => \^q\(50), R => '0' ); \goreg_dm.dout_i_reg[51]\: unisim.vcomponents.FDRE @@ -5563,7 +5862,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(51), - Q => \^q\(47), + Q => \^q\(51), R => '0' ); \goreg_dm.dout_i_reg[52]\: unisim.vcomponents.FDRE @@ -5574,7 +5873,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(52), - Q => \^q\(48), + Q => \^q\(52), R => '0' ); \goreg_dm.dout_i_reg[53]\: unisim.vcomponents.FDRE @@ -5585,7 +5884,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(53), - Q => \^q\(49), + Q => \^q\(53), R => '0' ); \goreg_dm.dout_i_reg[54]\: unisim.vcomponents.FDRE @@ -5596,7 +5895,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(54), - Q => \^q\(50), + Q => \^q\(54), R => '0' ); \goreg_dm.dout_i_reg[55]\: unisim.vcomponents.FDRE @@ -5607,7 +5906,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(55), - Q => \^q\(51), + Q => \^q\(55), R => '0' ); \goreg_dm.dout_i_reg[56]\: unisim.vcomponents.FDRE @@ -5618,7 +5917,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(56), - Q => \^q\(52), + Q => \^q\(56), R => '0' ); \goreg_dm.dout_i_reg[57]\: unisim.vcomponents.FDRE @@ -5629,7 +5928,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(57), - Q => \^q\(53), + Q => \^q\(57), R => '0' ); \goreg_dm.dout_i_reg[58]\: unisim.vcomponents.FDRE @@ -5640,7 +5939,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(58), - Q => \^q\(54), + Q => \^q\(58), R => '0' ); \goreg_dm.dout_i_reg[59]\: unisim.vcomponents.FDRE @@ -5651,7 +5950,7 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(59), - Q => \^q\(55), + Q => \^q\(59), R => '0' ); \goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDRE @@ -5662,126 +5961,85 @@ arvalid_en0_carry_i_8: unisim.vcomponents.LUT4 C => s_aclk, CE => E(0), D => dout_i(5), - Q => \^q\(1), + Q => \^q\(5), R => '0' ); -\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDRE +\goreg_dm.dout_i_reg[60]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, CE => E(0), - D => dout_i(6), - Q => \^q\(2), + D => dout_i(60), + Q => \^q\(60), R => '0' ); -\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDRE +\goreg_dm.dout_i_reg[61]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, CE => E(0), - D => dout_i(7), - Q => \^q\(3), + D => dout_i(61), + Q => \^q\(61), R => '0' ); -\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDRE +\goreg_dm.dout_i_reg[62]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, CE => E(0), - D => dout_i(8), - Q => \^q\(4), + D => dout_i(62), + Q => \^q\(62), R => '0' ); -\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDRE +\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, CE => E(0), - D => dout_i(9), - Q => \^q\(5), + D => dout_i(6), + Q => \^q\(6), R => '0' ); -\i__carry__0_i_5\: unisim.vcomponents.LUT6 - generic map( - INIT => X"EAAAAAAA15555555" - ) - port map ( - I0 => empty_fwft_i_reg_0, - I1 => \^q\(22), - I2 => \^q\(21), - I3 => \^q\(19), - I4 => \^q\(20), - I5 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(4), - O => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\(0) - ); -\i__carry_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"0000B000" - ) - port map ( - I0 => empty_fwft_fb_o_i_reg, - I1 => s_axi_rready, - I2 => arready_pkt, - I3 => CO(0), - I4 => \out\, - O => DI(0) - ); -\i__carry_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFF7F800000807F" - ) - port map ( - I0 => \^q\(21), - I1 => \^q\(19), - I2 => \^q\(20), - I3 => \^q\(22), - I4 => empty_fwft_i_reg_0, - I5 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(3), - O => S(3) - ); -\i__carry_i_3\: unisim.vcomponents.LUT5 +\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDRE generic map( - INIT => X"FF780087" + INIT => '0' ) port map ( - I0 => \^q\(20), - I1 => \^q\(19), - I2 => \^q\(21), - I3 => empty_fwft_i_reg_0, - I4 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(2), - O => S(2) + C => s_aclk, + CE => E(0), + D => dout_i(7), + Q => \^q\(7), + R => '0' ); -\i__carry_i_4\: unisim.vcomponents.LUT4 +\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDRE generic map( - INIT => X"F609" + INIT => '0' ) port map ( - I0 => \^q\(19), - I1 => \^q\(20), - I2 => empty_fwft_i_reg_0, - I3 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(1), - O => S(1) + C => s_aclk, + CE => E(0), + D => dout_i(8), + Q => \^q\(8), + R => '0' ); -\i__carry_i_5\: unisim.vcomponents.LUT6 +\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDRE generic map( - INIT => X"DFFFDFFFFFFFDFFF" + INIT => '0' ) port map ( - I0 => \^q\(19), - I1 => \out\, - I2 => CO(0), - I3 => arready_pkt, - I4 => s_axi_rready, - I5 => empty_fwft_fb_o_i_reg, - O => S(0) + C => s_aclk, + CE => E(0), + D => dout_i(9), + Q => \^q\(9), + R => '0' ); end STRUCTURE; library IEEE; @@ -5791,61 +6049,62 @@ use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20_s00_data_fifo_0_rd_logic is port ( \out\ : out STD_LOGIC; - \gfwd_rev_pipeline1.s_ready_i_reg\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); - \gfwd_rev_pipeline1.s_ready_i_reg_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0]\ : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); - ram_empty_fb_i_reg : out STD_LOGIC; - \gc0.count_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - ram_full_fb_i_reg : out STD_LOGIC; - \goreg_dm.dout_i_reg[59]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\ : out STD_LOGIC; - \gfwd_rev_pipeline1.s_ready_i_reg_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); - \gfwd_rev_pipeline1.s_ready_i_reg_2\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0]\ : out STD_LOGIC; + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + ram_full_comb : out STD_LOGIC; + \goreg_dm.dout_i_reg[62]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 4 downto 0 ); - ram_full_fb_i_reg_0 : out STD_LOGIC; + \gfwd_rev_pipeline1.s_ready_i_reg\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \gfwd_rev_pipeline1.s_ready_i_reg_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); s_aclk : in STD_LOGIC; \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); CO : in STD_LOGIC_VECTOR ( 0 to 0 ); arready_pkt : in STD_LOGIC; - s_axi_rready : in STD_LOGIC; empty_fwft_fb_o_i_reg : in STD_LOGIC; - \gfwd_rev_pipeline1.s_ready_i_reg_3\ : in STD_LOGIC; - ram_full_i_reg : in STD_LOGIC; + s_axi_rready : in STD_LOGIC; + \gfwd_rev_pipeline1.s_ready_i_reg_1\ : in STD_LOGIC; + ram_full_fb_i_reg : in STD_LOGIC; + \grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC; + ram_full_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gc0.count_reg[2]\ : in STD_LOGIC; + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gcc0.gc0.count_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); \gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); - \gcc0.gc0.count_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ) + \goreg_dm.dout_i_reg[22]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end Arty_Z7_20_s00_data_fifo_0_rd_logic; architecture STRUCTURE of Arty_Z7_20_s00_data_fifo_0_rd_logic is - signal \^gc0.count_reg[4]\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \gr1.gr1_int.rfwft_n_8\ : STD_LOGIC; + signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \gr1.gr1_int.rfwft_n_4\ : STD_LOGIC; signal p_2_out : STD_LOGIC; - signal rpntr_n_0 : STD_LOGIC; + signal rpntr_n_1 : STD_LOGIC; begin - \gc0.count_reg[4]\(0) <= \^gc0.count_reg[4]\(0); + E(0) <= \^e\(0); \gr1.gr1_int.rfwft\: entity work.Arty_Z7_20_s00_data_fifo_0_rd_fwft port map ( CO(0) => CO(0), - E(0) => E(0), + E(0) => \^e\(0), arready_pkt => arready_pkt, empty_fwft_fb_o_i_reg_0 => empty_fwft_fb_o_i_reg, \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0]\ => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0]\, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\ => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(5 downto 0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(5 downto 0), - \gc0.count_reg[4]\(0) => \^gc0.count_reg[4]\(0), - \gfwd_rev_pipeline1.s_ready_i_reg\(1 downto 0) => \gfwd_rev_pipeline1.s_ready_i_reg\(1 downto 0), + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0]_0\(0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0]_0\(0), + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]\ => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]\, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0\(0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0\(0), + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(1 downto 0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(1 downto 0), + \gfwd_rev_pipeline1.s_ready_i_reg\(0) => \gfwd_rev_pipeline1.s_ready_i_reg\(0), \gfwd_rev_pipeline1.s_ready_i_reg_0\(0) => \gfwd_rev_pipeline1.s_ready_i_reg_0\(0), - \gfwd_rev_pipeline1.s_ready_i_reg_1\(1 downto 0) => \gfwd_rev_pipeline1.s_ready_i_reg_1\(1 downto 0), - \gfwd_rev_pipeline1.s_ready_i_reg_2\(0) => \gfwd_rev_pipeline1.s_ready_i_reg_2\(0), - \gfwd_rev_pipeline1.s_ready_i_reg_3\ => \gfwd_rev_pipeline1.s_ready_i_reg_3\, - \goreg_dm.dout_i_reg[59]\(0) => \goreg_dm.dout_i_reg[59]\(0), + \gfwd_rev_pipeline1.s_ready_i_reg_1\ => \gfwd_rev_pipeline1.s_ready_i_reg_1\, + \goreg_dm.dout_i_reg[22]\(0) => \goreg_dm.dout_i_reg[22]\(0), + \goreg_dm.dout_i_reg[62]\(0) => \goreg_dm.dout_i_reg[62]\(0), \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1 downto 0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1 downto 0), \out\ => \out\, - ram_empty_fb_i_reg => \gr1.gr1_int.rfwft_n_8\, + ram_empty_fb_i_reg => \gr1.gr1_int.rfwft_n_4\, ram_empty_fb_i_reg_0 => p_2_out, - ram_full_fb_i_reg => ram_full_fb_i_reg, s_aclk => s_aclk, s_axi_rready => s_axi_rready ); @@ -5853,22 +6112,25 @@ begin port map ( \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1), \out\ => p_2_out, - ram_empty_fb_i_reg_0 => rpntr_n_0, + ram_empty_fb_i_reg_0 => rpntr_n_1, s_aclk => s_aclk ); rpntr: entity work.Arty_Z7_20_s00_data_fifo_0_rd_bin_cntr port map ( - E(0) => \^gc0.count_reg[4]\(0), + E(0) => \^e\(0), Q(4 downto 0) => Q(4 downto 0), + empty_fwft_i_reg => \gr1.gr1_int.rfwft_n_4\, + \gc0.count_reg[2]_0\ => \gc0.count_reg[2]\, \gcc0.gc0.count_d1_reg[4]\(4 downto 0) => \gcc0.gc0.count_d1_reg[4]\(4 downto 0), - \gcc0.gc0.count_reg[4]\(2 downto 0) => \gcc0.gc0.count_reg[4]\(2 downto 0), - \gpregsm1.curr_fwft_state_reg[0]\ => \gr1.gr1_int.rfwft_n_8\, + \gcc0.gc0.count_reg[4]\(4 downto 0) => \gcc0.gc0.count_reg[4]\(4 downto 0), + \gpr1.dout_i_reg[1]\(4 downto 0) => \gpr1.dout_i_reg[1]\(4 downto 0), + \grstd1.grst_full.grst_f.rst_d3_reg\ => \grstd1.grst_full.grst_f.rst_d3_reg\, \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1), \out\ => p_2_out, - ram_empty_fb_i_reg => rpntr_n_0, - ram_empty_fb_i_reg_0 => ram_empty_fb_i_reg, - ram_full_fb_i_reg => ram_full_fb_i_reg_0, - ram_full_i_reg => ram_full_i_reg, + ram_empty_fb_i_reg => rpntr_n_1, + ram_full_comb => ram_full_comb, + ram_full_fb_i_reg => ram_full_fb_i_reg, + ram_full_i_reg(0) => ram_full_i_reg(0), s_aclk => s_aclk ); end STRUCTURE; @@ -5879,22 +6141,19 @@ use UNISIM.VCOMPONENTS.ALL; entity \Arty_Z7_20_s00_data_fifo_0_rd_status_flags_ss__parameterized0\ is port ( \out\ : out STD_LOGIC; - \gcc0.gc0.count_d1_reg[1]\ : in STD_LOGIC; - \gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC; - \gcc0.gc0.count_d1_reg[5]\ : in STD_LOGIC; - \gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC; - \gc0.count_d1_reg[8]\ : in STD_LOGIC; - \gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC; - \gcc0.gc0.count_d1_reg[3]\ : in STD_LOGIC; - \gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC; - \gcc0.gc0.count_d1_reg[6]_0\ : in STD_LOGIC; + \gc0.count_d1_reg[0]\ : in STD_LOGIC; + \gc0.count_d1_reg[2]\ : in STD_LOGIC; + \gc0.count_d1_reg[5]\ : in STD_LOGIC; + \gc0.count_d1_reg[7]\ : in STD_LOGIC; + \gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC; + v1_reg_1 : in STD_LOGIC_VECTOR ( 3 downto 0 ); \gc0.count_reg[8]\ : in STD_LOGIC; \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ : in STD_LOGIC; s_aclk : in STD_LOGIC; \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC; ram_full_fb_i_reg : in STD_LOGIC; - m_axi_rvalid : in STD_LOGIC; - \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC + m_axi_rvalid : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \Arty_Z7_20_s00_data_fifo_0_rd_status_flags_ss__parameterized0\ : entity is "rd_status_flags_ss"; @@ -5921,25 +6180,22 @@ begin c1: entity work.\Arty_Z7_20_s00_data_fifo_0_compare__parameterized0\ port map ( comp0 => comp0, - \gc0.count_d1_reg[8]\ => \gc0.count_d1_reg[8]\, - \gcc0.gc0.count_d1_reg[1]\ => \gcc0.gc0.count_d1_reg[1]\, - \gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\, - \gcc0.gc0.count_d1_reg[5]\ => \gcc0.gc0.count_d1_reg[5]\, - \gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\ + \gc0.count_d1_reg[0]\ => \gc0.count_d1_reg[0]\, + \gc0.count_d1_reg[2]\ => \gc0.count_d1_reg[2]\, + \gc0.count_d1_reg[5]\ => \gc0.count_d1_reg[5]\, + \gc0.count_d1_reg[7]\ => \gc0.count_d1_reg[7]\, + \gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\ ); c2: entity work.\Arty_Z7_20_s00_data_fifo_0_compare__parameterized1\ port map ( comp0 => comp0, \gc0.count_reg[8]\ => \gc0.count_reg[8]\, - \gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\, - \gcc0.gc0.count_d1_reg[3]\ => \gcc0.gc0.count_d1_reg[3]\, - \gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\, - \gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]_0\, - \gpregsm1.curr_fwft_state_reg[0]\ => \gpregsm1.curr_fwft_state_reg[0]\, + \gpregsm1.curr_fwft_state_reg[1]\ => \gpregsm1.curr_fwft_state_reg[1]\, m_axi_rvalid => m_axi_rvalid, \out\ => ram_empty_fb_i, ram_empty_i_reg => c2_n_0, - ram_full_fb_i_reg => ram_full_fb_i_reg + ram_full_fb_i_reg => ram_full_fb_i_reg, + v1_reg_1(3 downto 0) => v1_reg_1(3 downto 0) ); ram_empty_fb_i_reg: unisim.vcomponents.FDSE generic map( @@ -6232,7 +6488,7 @@ entity \Arty_Z7_20_s00_data_fifo_0_reset_blk_ramfifo__parameterized0\ is \out\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); \grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC; - ram_full_fb_i_reg : out STD_LOGIC; + ram_full_i_reg : out STD_LOGIC; s_aclk : in STD_LOGIC; inverted_reset : in STD_LOGIC ); @@ -6324,7 +6580,7 @@ begin \gc0.count_reg[1]\(0) <= rd_rst_reg(0); \grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2; \out\(0) <= wr_rst_reg(1); - ram_full_fb_i_reg <= rst_d3; + ram_full_i_reg <= rst_d3; \grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE generic map( INIT => '1' @@ -6531,10 +6787,10 @@ entity \Arty_Z7_20_s00_data_fifo_0_reset_blk_ramfifo__parameterized1\ is \gfwd_rev_pipeline1.s_ready_i_reg\ : out STD_LOGIC; s_aclk : in STD_LOGIC; s_aresetn : in STD_LOGIC; - arready_pkt : in STD_LOGIC; + \gfwd_rev_pipeline1.areset_d1_reg\ : in STD_LOGIC; CO : in STD_LOGIC_VECTOR ( 0 to 0 ); - empty_fwft_i_reg : in STD_LOGIC; - \gfwd_rev_pipeline1.m_valid_i_reg\ : in STD_LOGIC + arready_pkt : in STD_LOGIC; + empty_fwft_i_reg : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \Arty_Z7_20_s00_data_fifo_0_reset_blk_ramfifo__parameterized1\ : entity is "reset_blk_ramfifo"; @@ -6623,13 +6879,13 @@ begin \out\(0) <= wr_rst_reg(0); \gfwd_rev_pipeline1.s_ready_i_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000000000000FFA2" + INIT => X"000000000000FABA" ) port map ( - I0 => arready_pkt, + I0 => \gfwd_rev_pipeline1.areset_d1_reg\, I1 => CO(0), - I2 => empty_fwft_i_reg, - I3 => \gfwd_rev_pipeline1.m_valid_i_reg\, + I2 => arready_pkt, + I3 => empty_fwft_i_reg, I4 => rst_d2, I5 => wr_rst_reg(0), O => \gfwd_rev_pipeline1.s_ready_i_reg\ @@ -6834,7 +7090,7 @@ entity \Arty_Z7_20_s00_data_fifo_0_reset_blk_ramfifo__parameterized2\ is \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); ram_full_i_reg : out STD_LOGIC; ram_full_i_reg_0 : out STD_LOGIC; - \gcc0.gc0.count_reg[1]\ : out STD_LOGIC; + \gcc0.gc0.count_d1_reg[0]\ : out STD_LOGIC; SR : out STD_LOGIC_VECTOR ( 0 to 0 ); s_aclk : in STD_LOGIC; inverted_reset : in STD_LOGIC; @@ -6848,7 +7104,7 @@ architecture STRUCTURE of \Arty_Z7_20_s00_data_fifo_0_reset_blk_ramfifo__paramet signal \arst_sync_q[1]_6\ : STD_LOGIC; signal \arst_sync_q[2]_7\ : STD_LOGIC; signal \arst_sync_q[3]_8\ : STD_LOGIC; - signal \^gcc0.gc0.count_reg[1]\ : STD_LOGIC; + signal \^gcc0.gc0.count_d1_reg[0]\ : STD_LOGIC; signal \grstd1.grst_full.grst_f.rst_d3_i_1_n_0\ : STD_LOGIC; signal \ngwrdrst.grst.g7serrst.gsckt_wrst.rd_rst_active_i_1_n_0\ : STD_LOGIC; signal \ngwrdrst.grst.g7serrst.gsckt_wrst.rd_rst_middle_i_1_n_0\ : STD_LOGIC; @@ -6942,17 +7198,17 @@ architecture STRUCTURE of \Arty_Z7_20_s00_data_fifo_0_reset_blk_ramfifo__paramet attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes"; attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no"; begin - \gcc0.gc0.count_reg[1]\ <= \^gcc0.gc0.count_reg[1]\; + \gcc0.gc0.count_d1_reg[0]\ <= \^gcc0.gc0.count_d1_reg[0]\; \out\(1) <= rd_rst_reg(2); \out\(0) <= rd_rst_reg(0); ram_full_i_reg <= rst_d2; ram_full_i_reg_0 <= rst_d3; -\gpregsm1.curr_fwft_state[1]_i_1__0\: unisim.vcomponents.LUT2 +\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( - I0 => \^gcc0.gc0.count_reg[1]\, + I0 => \^gcc0.gc0.count_d1_reg[0]\, I1 => fwft_rst_done_q, O => SR(0) ); @@ -6984,7 +7240,7 @@ begin ) port map ( I0 => rst_d2, - I1 => \^gcc0.gc0.count_reg[1]\, + I1 => \^gcc0.gc0.count_d1_reg[0]\, O => \grstd1.grst_full.grst_f.rst_d3_i_1_n_0\ ); \grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE @@ -7039,7 +7295,7 @@ begin C => s_aclk, CE => '1', D => p_0_out_n_0, - Q => \^gcc0.gc0.count_reg[1]\, + Q => \^gcc0.gc0.count_d1_reg[0]\, R => '0' ); \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.sckt_wr_rst_i_q_reg\: unisim.vcomponents.FDRE @@ -7304,37 +7560,36 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20_s00_data_fifo_0_wr_logic is port ( + \out\ : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arready : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); + Q : out STD_LOGIC_VECTOR ( 4 downto 0 ); ram_empty_fb_i_reg : out STD_LOGIC; - E : out STD_LOGIC_VECTOR ( 0 to 0 ); - \gpr1.dout_i_reg[5]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + \gpr1.dout_i_reg[1]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + ram_full_comb : in STD_LOGIC; s_aclk : in STD_LOGIC; - \out\ : in STD_LOGIC; - ram_empty_fb_i_reg_0 : in STD_LOGIC; - \grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC; - \gc0.count_d1_reg[2]\ : in STD_LOGIC; - \gc0.count_d1_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); - \gc0.count_d1_reg[2]_0\ : in STD_LOGIC; + \grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; + \gc0.count_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); AR : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end Arty_Z7_20_s00_data_fifo_0_wr_logic; architecture STRUCTURE of Arty_Z7_20_s00_data_fifo_0_wr_logic is signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \gwss.wsts_n_0\ : STD_LOGIC; - signal \^ram_empty_fb_i_reg\ : STD_LOGIC; - signal ram_full_comb : STD_LOGIC; + signal \^gpr1.dout_i_reg[1]\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \gwss.wsts_n_3\ : STD_LOGIC; begin E(0) <= \^e\(0); - ram_empty_fb_i_reg <= \^ram_empty_fb_i_reg\; + \gpr1.dout_i_reg[1]\(4 downto 0) <= \^gpr1.dout_i_reg[1]\(4 downto 0); \gwss.wsts\: entity work.Arty_Z7_20_s00_data_fifo_0_wr_status_flags_ss port map ( E(0) => \^e\(0), - \grstd1.grst_full.grst_f.rst_d2_reg\ => \out\, - \out\ => \gwss.wsts_n_0\, - ram_empty_fb_i_reg => \^ram_empty_fb_i_reg\, + \gc0.count_reg[3]\(0) => \gc0.count_reg[4]\(3), + \gcc0.gc0.count_d1_reg[3]\(0) => \^gpr1.dout_i_reg[1]\(3), + \grstd1.grst_full.grst_f.rst_d2_reg\ => \grstd1.grst_full.grst_f.rst_d2_reg\, + \out\ => \out\, + ram_empty_fb_i_reg => \gwss.wsts_n_3\, ram_full_comb => ram_full_comb, s_aclk => s_aclk, s_axi_arready => s_axi_arready, @@ -7344,16 +7599,12 @@ wpntr: entity work.Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr port map ( AR(0) => AR(0), E(0) => \^e\(0), - Q(2 downto 0) => Q(2 downto 0), - \gc0.count_d1_reg[1]\(1 downto 0) => \gc0.count_d1_reg[1]\(1 downto 0), - \gc0.count_d1_reg[2]\ => \gc0.count_d1_reg[2]\, - \gc0.count_d1_reg[2]_0\ => \gc0.count_d1_reg[2]_0\, - \gpr1.dout_i_reg[5]\(4 downto 0) => \gpr1.dout_i_reg[5]\(4 downto 0), - \grstd1.grst_full.grst_f.rst_d3_reg\ => \grstd1.grst_full.grst_f.rst_d3_reg\, - \out\ => \gwss.wsts_n_0\, - ram_empty_fb_i_reg => ram_empty_fb_i_reg_0, - ram_full_comb => ram_full_comb, - ram_full_i_reg => \^ram_empty_fb_i_reg\, + Q(4 downto 0) => Q(4 downto 0), + \gc0.count_reg[4]\(3) => \gc0.count_reg[4]\(4), + \gc0.count_reg[4]\(2 downto 0) => \gc0.count_reg[4]\(2 downto 0), + \gpr1.dout_i_reg[1]\(4 downto 0) => \^gpr1.dout_i_reg[1]\(4 downto 0), + ram_empty_fb_i_reg => ram_empty_fb_i_reg, + ram_full_fb_i_reg => \gwss.wsts_n_3\, s_aclk => s_aclk ); end STRUCTURE; @@ -7366,22 +7617,16 @@ entity \Arty_Z7_20_s00_data_fifo_0_wr_status_flags_ss__parameterized0\ is \out\ : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_rready : out STD_LOGIC; - \gcc0.gc0.count_d1_reg[1]\ : in STD_LOGIC; - \gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC; - \gcc0.gc0.count_d1_reg[5]\ : in STD_LOGIC; - \gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC; - \gc0.count_d1_reg[8]\ : in STD_LOGIC; - \gcc0.gc0.count_reg[1]\ : in STD_LOGIC; - \gcc0.gc0.count_reg[3]\ : in STD_LOGIC; - \gcc0.gc0.count_reg[5]\ : in STD_LOGIC; - \gcc0.gc0.count_reg[7]\ : in STD_LOGIC; - \gc0.count_d1_reg[8]_0\ : in STD_LOGIC; + v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC; + v1_reg_1 : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \gcc0.gc0.count_reg[8]\ : in STD_LOGIC; \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ : in STD_LOGIC; s_aclk : in STD_LOGIC; \grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC; \grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC; - ram_empty_fb_i_reg : in STD_LOGIC; - m_axi_rvalid : in STD_LOGIC + m_axi_rvalid : in STD_LOGIC; + ram_empty_fb_i_reg : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \Arty_Z7_20_s00_data_fifo_0_wr_status_flags_ss__parameterized0\ : entity is "wr_status_flags_ss"; @@ -7421,25 +7666,19 @@ begin c0: entity work.\Arty_Z7_20_s00_data_fifo_0_compare__parameterized2\ port map ( comp1 => comp1, - \gc0.count_d1_reg[8]\ => \gc0.count_d1_reg[8]\, - \gcc0.gc0.count_d1_reg[1]\ => \gcc0.gc0.count_d1_reg[1]\, - \gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\, - \gcc0.gc0.count_d1_reg[5]\ => \gcc0.gc0.count_d1_reg[5]\, - \gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\, + \gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\, \grstd1.grst_full.grst_f.rst_d3_reg\ => \grstd1.grst_full.grst_f.rst_d3_reg\, m_axi_rvalid => m_axi_rvalid, \out\ => ram_full_fb_i, ram_empty_fb_i_reg => ram_empty_fb_i_reg, - ram_full_comb => ram_full_comb + ram_full_comb => ram_full_comb, + v1_reg_0(3 downto 0) => v1_reg_0(3 downto 0) ); c1: entity work.\Arty_Z7_20_s00_data_fifo_0_compare__parameterized3\ port map ( comp1 => comp1, - \gc0.count_d1_reg[8]\ => \gc0.count_d1_reg[8]_0\, - \gcc0.gc0.count_reg[1]\ => \gcc0.gc0.count_reg[1]\, - \gcc0.gc0.count_reg[3]\ => \gcc0.gc0.count_reg[3]\, - \gcc0.gc0.count_reg[5]\ => \gcc0.gc0.count_reg[5]\, - \gcc0.gc0.count_reg[7]\ => \gcc0.gc0.count_reg[7]\ + \gcc0.gc0.count_reg[8]\ => \gcc0.gc0.count_reg[8]\, + v1_reg_1(3 downto 0) => v1_reg_1(3 downto 0) ); i_0: unisim.vcomponents.LUT1 generic map( @@ -7497,14 +7736,14 @@ entity Arty_Z7_20_s00_data_fifo_0_axi_reg_slice is inverted_reset : out STD_LOGIC; arready_pkt : out STD_LOGIC; m_axi_arvalid : out STD_LOGIC; - UNCONN_OUT : out STD_LOGIC_VECTOR ( 55 downto 0 ); + UNCONN_OUT : out STD_LOGIC_VECTOR ( 62 downto 0 ); s_aclk : in STD_LOGIC; m_axi_arready : in STD_LOGIC; s_aresetn : in STD_LOGIC; CO : in STD_LOGIC_VECTOR ( 0 to 0 ); \out\ : in STD_LOGIC; \gfwd_rev_pipeline1.s_ready_i_reg_0\ : in STD_LOGIC; - D : in STD_LOGIC_VECTOR ( 55 downto 0 ) + D : in STD_LOGIC_VECTOR ( 62 downto 0 ) ); end Arty_Z7_20_s00_data_fifo_0_axi_reg_slice; @@ -7514,7 +7753,7 @@ architecture STRUCTURE of Arty_Z7_20_s00_data_fifo_0_axi_reg_slice is signal extnd_reset : STD_LOGIC; signal \gfwd_rev_pipeline1.m_valid_i_i_1_n_0\ : STD_LOGIC; signal \gfwd_rev_pipeline1.s_ready_i_i_2_n_0\ : STD_LOGIC; - signal \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\ : STD_LOGIC; + signal \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\ : STD_LOGIC; signal \^m_axi_arvalid\ : STD_LOGIC; signal p_0_in : STD_LOGIC; signal rstblk_n_3 : STD_LOGIC; @@ -7534,12 +7773,12 @@ begin ); \gfwd_rev_pipeline1.m_valid_i_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"000000000000F035" + INIT => X"000000000000CC2E" ) port map ( I0 => \gfwd_rev_pipeline1.s_ready_i_reg_0\, - I1 => m_axi_arready, - I2 => \^m_axi_arvalid\, + I1 => \^m_axi_arvalid\, + I2 => m_axi_arready, I3 => areset_d1, I4 => p_0_in, I5 => extnd_reset, @@ -7558,12 +7797,12 @@ begin ); \gfwd_rev_pipeline1.s_ready_i_i_2\: unisim.vcomponents.LUT3 generic map( - INIT => X"F8" + INIT => X"EA" ) port map ( - I0 => m_axi_arready, + I0 => areset_d1, I1 => \^m_axi_arvalid\, - I2 => areset_d1, + I2 => m_axi_arready, O => \gfwd_rev_pipeline1.s_ready_i_i_2_n_0\ ); \gfwd_rev_pipeline1.s_ready_i_reg\: unisim.vcomponents.FDRE @@ -7577,463 +7816,507 @@ begin Q => \^arready_pkt\, R => '0' ); -\gfwd_rev_pipeline1.storage_data1[59]_i_1\: unisim.vcomponents.LUT1 +\gfwd_rev_pipeline1.storage_data1[62]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^m_axi_arvalid\, - O => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\ - ); -\gfwd_rev_pipeline1.storage_data1_reg[10]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, - D => D(6), - Q => UNCONN_OUT(6), - R => '0' - ); -\gfwd_rev_pipeline1.storage_data1_reg[11]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, - D => D(7), - Q => UNCONN_OUT(7), - R => '0' - ); -\gfwd_rev_pipeline1.storage_data1_reg[12]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, - D => D(8), - Q => UNCONN_OUT(8), - R => '0' + O => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\ ); -\gfwd_rev_pipeline1.storage_data1_reg[13]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, - D => D(9), - Q => UNCONN_OUT(9), + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, + D => D(0), + Q => UNCONN_OUT(0), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[14]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(10), Q => UNCONN_OUT(10), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[15]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(11), Q => UNCONN_OUT(11), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[16]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(12), Q => UNCONN_OUT(12), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[17]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(13), Q => UNCONN_OUT(13), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[18]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(14), Q => UNCONN_OUT(14), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[19]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(15), Q => UNCONN_OUT(15), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[20]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(16), Q => UNCONN_OUT(16), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[21]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(17), Q => UNCONN_OUT(17), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[22]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(18), Q => UNCONN_OUT(18), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[23]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(19), Q => UNCONN_OUT(19), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[24]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_aclk, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, + D => D(1), + Q => UNCONN_OUT(1), + R => '0' + ); +\gfwd_rev_pipeline1.storage_data1_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(20), Q => UNCONN_OUT(20), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[25]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(21), Q => UNCONN_OUT(21), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[26]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(22), Q => UNCONN_OUT(22), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[27]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(23), Q => UNCONN_OUT(23), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[28]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(24), Q => UNCONN_OUT(24), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[29]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(25), Q => UNCONN_OUT(25), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[30]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(26), Q => UNCONN_OUT(26), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[31]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(27), Q => UNCONN_OUT(27), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[32]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(28), Q => UNCONN_OUT(28), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[33]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(29), Q => UNCONN_OUT(29), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[34]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_aclk, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, + D => D(2), + Q => UNCONN_OUT(2), + R => '0' + ); +\gfwd_rev_pipeline1.storage_data1_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(30), Q => UNCONN_OUT(30), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[35]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(31), Q => UNCONN_OUT(31), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[36]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[32]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(32), Q => UNCONN_OUT(32), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[37]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[33]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(33), Q => UNCONN_OUT(33), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[38]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[34]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(34), Q => UNCONN_OUT(34), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[39]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[35]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(35), Q => UNCONN_OUT(35), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[40]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[36]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(36), Q => UNCONN_OUT(36), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[41]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[37]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(37), Q => UNCONN_OUT(37), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[42]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[38]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(38), Q => UNCONN_OUT(38), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[43]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[39]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(39), Q => UNCONN_OUT(39), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[44]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, + D => D(3), + Q => UNCONN_OUT(3), + R => '0' + ); +\gfwd_rev_pipeline1.storage_data1_reg[40]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_aclk, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(40), Q => UNCONN_OUT(40), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[45]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[41]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(41), Q => UNCONN_OUT(41), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[46]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[42]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(42), Q => UNCONN_OUT(42), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[47]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[43]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(43), Q => UNCONN_OUT(43), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[48]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[44]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(44), Q => UNCONN_OUT(44), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[49]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[45]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, D => D(45), Q => UNCONN_OUT(45), R => '0' ); +\gfwd_rev_pipeline1.storage_data1_reg[46]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_aclk, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, + D => D(46), + Q => UNCONN_OUT(46), + R => '0' + ); +\gfwd_rev_pipeline1.storage_data1_reg[47]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_aclk, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, + D => D(47), + Q => UNCONN_OUT(47), + R => '0' + ); +\gfwd_rev_pipeline1.storage_data1_reg[48]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_aclk, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, + D => D(48), + Q => UNCONN_OUT(48), + R => '0' + ); +\gfwd_rev_pipeline1.storage_data1_reg[49]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_aclk, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, + D => D(49), + Q => UNCONN_OUT(49), + R => '0' + ); \gfwd_rev_pipeline1.storage_data1_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, - D => D(0), - Q => UNCONN_OUT(0), + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, + D => D(4), + Q => UNCONN_OUT(4), R => '0' ); \gfwd_rev_pipeline1.storage_data1_reg[50]\: unisim.vcomponents.FDRE @@ -8042,9 +8325,9 @@ begin ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, - D => D(46), - Q => UNCONN_OUT(46), + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, + D => D(50), + Q => UNCONN_OUT(50), R => '0' ); \gfwd_rev_pipeline1.storage_data1_reg[51]\: unisim.vcomponents.FDRE @@ -8053,9 +8336,9 @@ begin ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, - D => D(47), - Q => UNCONN_OUT(47), + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, + D => D(51), + Q => UNCONN_OUT(51), R => '0' ); \gfwd_rev_pipeline1.storage_data1_reg[52]\: unisim.vcomponents.FDRE @@ -8064,9 +8347,9 @@ begin ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, - D => D(48), - Q => UNCONN_OUT(48), + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, + D => D(52), + Q => UNCONN_OUT(52), R => '0' ); \gfwd_rev_pipeline1.storage_data1_reg[53]\: unisim.vcomponents.FDRE @@ -8075,9 +8358,9 @@ begin ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, - D => D(49), - Q => UNCONN_OUT(49), + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, + D => D(53), + Q => UNCONN_OUT(53), R => '0' ); \gfwd_rev_pipeline1.storage_data1_reg[54]\: unisim.vcomponents.FDRE @@ -8086,9 +8369,9 @@ begin ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, - D => D(50), - Q => UNCONN_OUT(50), + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, + D => D(54), + Q => UNCONN_OUT(54), R => '0' ); \gfwd_rev_pipeline1.storage_data1_reg[55]\: unisim.vcomponents.FDRE @@ -8097,64 +8380,97 @@ begin ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, - D => D(51), - Q => UNCONN_OUT(51), + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, + D => D(55), + Q => UNCONN_OUT(55), + R => '0' + ); +\gfwd_rev_pipeline1.storage_data1_reg[56]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_aclk, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, + D => D(56), + Q => UNCONN_OUT(56), + R => '0' + ); +\gfwd_rev_pipeline1.storage_data1_reg[57]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_aclk, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, + D => D(57), + Q => UNCONN_OUT(57), + R => '0' + ); +\gfwd_rev_pipeline1.storage_data1_reg[58]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => s_aclk, + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, + D => D(58), + Q => UNCONN_OUT(58), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[56]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[59]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, - D => D(52), - Q => UNCONN_OUT(52), + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, + D => D(59), + Q => UNCONN_OUT(59), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[57]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, - D => D(53), - Q => UNCONN_OUT(53), + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, + D => D(5), + Q => UNCONN_OUT(5), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[58]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[60]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, - D => D(54), - Q => UNCONN_OUT(54), + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, + D => D(60), + Q => UNCONN_OUT(60), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[59]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[61]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, - D => D(55), - Q => UNCONN_OUT(55), + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, + D => D(61), + Q => UNCONN_OUT(61), R => '0' ); -\gfwd_rev_pipeline1.storage_data1_reg[5]\: unisim.vcomponents.FDRE +\gfwd_rev_pipeline1.storage_data1_reg[62]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, - D => D(1), - Q => UNCONN_OUT(1), + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, + D => D(62), + Q => UNCONN_OUT(62), R => '0' ); \gfwd_rev_pipeline1.storage_data1_reg[6]\: unisim.vcomponents.FDRE @@ -8163,9 +8479,9 @@ begin ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, - D => D(2), - Q => UNCONN_OUT(2), + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, + D => D(6), + Q => UNCONN_OUT(6), R => '0' ); \gfwd_rev_pipeline1.storage_data1_reg[7]\: unisim.vcomponents.FDRE @@ -8174,9 +8490,9 @@ begin ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, - D => D(3), - Q => UNCONN_OUT(3), + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, + D => D(7), + Q => UNCONN_OUT(7), R => '0' ); \gfwd_rev_pipeline1.storage_data1_reg[8]\: unisim.vcomponents.FDRE @@ -8185,9 +8501,9 @@ begin ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, - D => D(4), - Q => UNCONN_OUT(4), + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, + D => D(8), + Q => UNCONN_OUT(8), R => '0' ); \gfwd_rev_pipeline1.storage_data1_reg[9]\: unisim.vcomponents.FDRE @@ -8196,9 +8512,9 @@ begin ) port map ( C => s_aclk, - CE => \gfwd_rev_pipeline1.storage_data1[59]_i_1_n_0\, - D => D(5), - Q => UNCONN_OUT(5), + CE => \gfwd_rev_pipeline1.storage_data1[62]_i_1_n_0\, + D => D(9), + Q => UNCONN_OUT(9), R => '0' ); rstblk: entity work.\Arty_Z7_20_s00_data_fifo_0_reset_blk_ramfifo__parameterized1\ @@ -8206,7 +8522,7 @@ rstblk: entity work.\Arty_Z7_20_s00_data_fifo_0_reset_blk_ramfifo__parameterized CO(0) => CO(0), arready_pkt => \^arready_pkt\, empty_fwft_i_reg => \out\, - \gfwd_rev_pipeline1.m_valid_i_reg\ => \gfwd_rev_pipeline1.s_ready_i_i_2_n_0\, + \gfwd_rev_pipeline1.areset_d1_reg\ => \gfwd_rev_pipeline1.s_ready_i_i_2_n_0\, \gfwd_rev_pipeline1.s_ready_i_reg\ => rstblk_n_3, \grstd1.grst_full.grst_f.rst_d3_reg_0\ => extnd_reset, \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg_0\ => inverted_reset, @@ -8255,99 +8571,100 @@ use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20_s00_data_fifo_0_fifo_generator_ramfifo is port ( \out\ : out STD_LOGIC; - S : out STD_LOGIC_VECTOR ( 3 downto 0 ); - Q : out STD_LOGIC_VECTOR ( 55 downto 0 ); - \gfwd_rev_pipeline1.s_ready_i_reg\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); - \gfwd_rev_pipeline1.s_ready_i_reg_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + Q : out STD_LOGIC_VECTOR ( 62 downto 0 ); D : out STD_LOGIC_VECTOR ( 9 downto 0 ); E : out STD_LOGIC_VECTOR ( 0 to 0 ); aempty_fwft_i_reg : out STD_LOGIC; - DI : out STD_LOGIC_VECTOR ( 0 to 0 ); - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\ : out STD_LOGIC; + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]\ : out STD_LOGIC; s_axi_arready : out STD_LOGIC; - \gfwd_rev_pipeline1.s_ready_i_reg_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); - \gfwd_rev_pipeline1.s_ready_i_reg_2\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + S : out STD_LOGIC_VECTOR ( 3 downto 0 ); + DI : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \gfwd_rev_pipeline1.s_ready_i_reg\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \gfwd_rev_pipeline1.s_ready_i_reg_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); s_aclk : in STD_LOGIC; inverted_reset : in STD_LOGIC; CO : in STD_LOGIC_VECTOR ( 0 to 0 ); arready_pkt : in STD_LOGIC; - s_axi_rready : in STD_LOGIC; - empty_fwft_fb_o_i_reg : in STD_LOGIC; - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); - rd_fifo_free_space : in STD_LOGIC_VECTOR ( 9 downto 0 ); s_axi_arvalid : in STD_LOGIC; - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); - UNCONN_IN : in STD_LOGIC_VECTOR ( 55 downto 0 ) + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); + rd_fifo_free_space : in STD_LOGIC_VECTOR ( 9 downto 0 ); + empty_fwft_fb_o_i_reg : in STD_LOGIC; + s_axi_rready : in STD_LOGIC; + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + UNCONN_IN : in STD_LOGIC_VECTOR ( 62 downto 0 ) ); end Arty_Z7_20_s00_data_fifo_0_fifo_generator_ramfifo; architecture STRUCTURE of Arty_Z7_20_s00_data_fifo_0_fifo_generator_ramfifo is + signal \^q\ : STD_LOGIC_VECTOR ( 62 downto 0 ); signal \^aempty_fwft_i_reg\ : STD_LOGIC; - signal \^gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.rd_n_19\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.rd_n_8\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.rd_n_9\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.wr_n_4\ : STD_LOGIC; + signal \^gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd_n_1\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd_n_2\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd_n_5\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.wr_n_0\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.wr_n_1\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.wr_n_8\ : STD_LOGIC; + signal \gwss.wsts/ram_full_comb\ : STD_LOGIC; signal \^out\ : STD_LOGIC; signal p_0_out_0 : STD_LOGIC_VECTOR ( 4 downto 0 ); signal p_11_out : STD_LOGIC_VECTOR ( 4 downto 0 ); - signal p_12_out : STD_LOGIC_VECTOR ( 4 downto 2 ); - signal p_17_out : STD_LOGIC; - signal ram_rd_en_i : STD_LOGIC; + signal p_12_out : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 4 downto 0 ); signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 ); signal rst_full_ff_i : STD_LOGIC; signal wr_rst_busy_rach : STD_LOGIC; signal wr_rst_i : STD_LOGIC_VECTOR ( 1 to 1 ); begin + Q(62 downto 0) <= \^q\(62 downto 0); aempty_fwft_i_reg <= \^aempty_fwft_i_reg\; - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\ <= \^gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\; + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]\ <= \^gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]\; \out\ <= \^out\; \gntv_or_sync_fifo.gl0.rd\: entity work.Arty_Z7_20_s00_data_fifo_0_rd_logic port map ( CO(0) => CO(0), - E(0) => E(0), - Q(4 downto 0) => p_0_out_0(4 downto 0), + E(0) => \gntv_or_sync_fifo.gl0.rd_n_1\, + Q(4 downto 0) => rd_pntr_plus1(4 downto 0), arready_pkt => arready_pkt, empty_fwft_fb_o_i_reg => empty_fwft_fb_o_i_reg, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0]\ => \gntv_or_sync_fifo.gl0.rd_n_4\, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\ => \^gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(5 downto 0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(9 downto 4), - \gc0.count_reg[4]\(0) => ram_rd_en_i, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0]\ => \gntv_or_sync_fifo.gl0.rd_n_2\, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[0]_0\(0) => E(0), + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]\ => \^gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]\, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0\(0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0\(0), + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(1 downto 0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0\(9 downto 8), + \gc0.count_reg[2]\ => \gntv_or_sync_fifo.gl0.wr_n_8\, \gcc0.gc0.count_d1_reg[4]\(4 downto 0) => p_11_out(4 downto 0), - \gcc0.gc0.count_reg[4]\(2 downto 0) => p_12_out(4 downto 2), - \gfwd_rev_pipeline1.s_ready_i_reg\(1 downto 0) => \gfwd_rev_pipeline1.s_ready_i_reg\(3 downto 2), + \gcc0.gc0.count_reg[4]\(4 downto 0) => p_12_out(4 downto 0), + \gfwd_rev_pipeline1.s_ready_i_reg\(0) => \gfwd_rev_pipeline1.s_ready_i_reg\(0), \gfwd_rev_pipeline1.s_ready_i_reg_0\(0) => \gfwd_rev_pipeline1.s_ready_i_reg_0\(0), - \gfwd_rev_pipeline1.s_ready_i_reg_1\(1 downto 0) => \gfwd_rev_pipeline1.s_ready_i_reg_1\(3 downto 2), - \gfwd_rev_pipeline1.s_ready_i_reg_2\(0) => \gfwd_rev_pipeline1.s_ready_i_reg_2\(0), - \gfwd_rev_pipeline1.s_ready_i_reg_3\ => \^aempty_fwft_i_reg\, - \goreg_dm.dout_i_reg[59]\(0) => \gntv_or_sync_fifo.gl0.rd_n_9\, + \gfwd_rev_pipeline1.s_ready_i_reg_1\ => \^aempty_fwft_i_reg\, + \goreg_dm.dout_i_reg[22]\(0) => \^q\(22), + \goreg_dm.dout_i_reg[62]\(0) => \gntv_or_sync_fifo.gl0.rd_n_5\, + \gpr1.dout_i_reg[1]\(4 downto 0) => p_0_out_0(4 downto 0), + \grstd1.grst_full.grst_f.rst_d3_reg\ => wr_rst_busy_rach, \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1) => rd_rst_i(2), \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => rd_rst_i(0), \out\ => \^out\, - ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.rd_n_6\, - ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.rd_n_8\, - ram_full_fb_i_reg_0 => \gntv_or_sync_fifo.gl0.rd_n_19\, - ram_full_i_reg => \gntv_or_sync_fifo.gl0.wr_n_4\, + ram_full_comb => \gwss.wsts/ram_full_comb\, + ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_0\, + ram_full_i_reg(0) => \gntv_or_sync_fifo.gl0.wr_n_1\, s_aclk => s_aclk, s_axi_rready => s_axi_rready ); \gntv_or_sync_fifo.gl0.wr\: entity work.Arty_Z7_20_s00_data_fifo_0_wr_logic port map ( AR(0) => wr_rst_i(1), - E(0) => p_17_out, - Q(2 downto 0) => p_12_out(4 downto 2), - \gc0.count_d1_reg[1]\(1 downto 0) => p_0_out_0(1 downto 0), - \gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.rd_n_6\, - \gc0.count_d1_reg[2]_0\ => \gntv_or_sync_fifo.gl0.rd_n_19\, - \gpr1.dout_i_reg[5]\(4 downto 0) => p_11_out(4 downto 0), - \grstd1.grst_full.grst_f.rst_d3_reg\ => wr_rst_busy_rach, - \out\ => rst_full_ff_i, - ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_4\, - ram_empty_fb_i_reg_0 => \gntv_or_sync_fifo.gl0.rd_n_8\, + E(0) => \gntv_or_sync_fifo.gl0.wr_n_1\, + Q(4 downto 0) => p_12_out(4 downto 0), + \gc0.count_reg[4]\(4 downto 0) => rd_pntr_plus1(4 downto 0), + \gpr1.dout_i_reg[1]\(4 downto 0) => p_11_out(4 downto 0), + \grstd1.grst_full.grst_f.rst_d2_reg\ => rst_full_ff_i, + \out\ => \gntv_or_sync_fifo.gl0.wr_n_0\, + ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_8\, + ram_full_comb => \gwss.wsts/ram_full_comb\, s_aclk => s_aclk, s_axi_arready => s_axi_arready, s_axi_arvalid => s_axi_arvalid @@ -8356,30 +8673,27 @@ begin port map ( CO(0) => CO(0), D(9 downto 0) => D(9 downto 0), - DI(0) => DI(0), - E(0) => \gntv_or_sync_fifo.gl0.rd_n_9\, - Q(55 downto 0) => Q(55 downto 0), + DI(3 downto 0) => DI(3 downto 0), + E(0) => \gntv_or_sync_fifo.gl0.rd_n_5\, + EN => \gntv_or_sync_fifo.gl0.wr_n_1\, + Q(62 downto 0) => \^q\(62 downto 0), S(3 downto 0) => S(3 downto 0), - UNCONN_IN(55 downto 0) => UNCONN_IN(55 downto 0), + UNCONN_IN(62 downto 0) => UNCONN_IN(62 downto 0), aempty_fwft_i_reg => \^aempty_fwft_i_reg\, arready_pkt => arready_pkt, - empty_fwft_fb_o_i_reg => empty_fwft_fb_o_i_reg, - empty_fwft_i_reg => \gntv_or_sync_fifo.gl0.rd_n_4\, - empty_fwft_i_reg_0 => \^gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\(0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_0\(0), - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_0\(3 downto 0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_1\(3 downto 0), - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(8 downto 0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(8 downto 0), - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(1 downto 0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0\(1 downto 0), + empty_fwft_i_reg => \gntv_or_sync_fifo.gl0.rd_n_2\, + empty_fwft_i_reg_0 => \^gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]\, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]\(2 downto 0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0\(3 downto 1), + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\(3 downto 0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\(3 downto 0), + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[8]\(8 downto 0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0\(8 downto 0), + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(0), + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0\(1 downto 0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_1\(1 downto 0), \gc0.count_d1_reg[4]\(4 downto 0) => p_0_out_0(4 downto 0), \gcc0.gc0.count_d1_reg[4]\(4 downto 0) => p_11_out(4 downto 0), - \gfwd_rev_pipeline1.s_ready_i_reg\(1 downto 0) => \gfwd_rev_pipeline1.s_ready_i_reg_1\(1 downto 0), - \gfwd_rev_pipeline1.s_ready_i_reg_0\(1 downto 0) => \gfwd_rev_pipeline1.s_ready_i_reg\(1 downto 0), - \gpregsm1.curr_fwft_state_reg[0]\(0) => ram_rd_en_i, \out\ => \^out\, - ram_full_fb_i_reg(0) => p_17_out, + ram_empty_fb_i_reg(0) => \gntv_or_sync_fifo.gl0.rd_n_1\, rd_fifo_free_space(9 downto 0) => rd_fifo_free_space(9 downto 0), - s_aclk => s_aclk, - s_axi_rready => s_axi_rready + s_aclk => s_aclk ); rstblk: entity work.\Arty_Z7_20_s00_data_fifo_0_reset_blk_ramfifo__parameterized0\ port map ( @@ -8388,7 +8702,7 @@ rstblk: entity work.\Arty_Z7_20_s00_data_fifo_0_reset_blk_ramfifo__parameterized \grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i, inverted_reset => inverted_reset, \out\(0) => wr_rst_i(1), - ram_full_fb_i_reg => wr_rst_busy_rach, + ram_full_i_reg => wr_rst_busy_rach, s_aclk => s_aclk ); end STRUCTURE; @@ -8400,36 +8714,30 @@ entity \Arty_Z7_20_s00_data_fifo_0_rd_logic__parameterized0\ is port ( \out\ : out STD_LOGIC; fwft_rst_done_q : out STD_LOGIC; - S : out STD_LOGIC_VECTOR ( 0 to 0 ); - ram_full_i_reg : out STD_LOGIC; - \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 ); - \gc0.count_d1_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); - ram_full_i_reg_0 : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 7 downto 0 ); E : out STD_LOGIC_VECTOR ( 0 to 0 ); - ram_full_i_reg_1 : out STD_LOGIC; + ram_full_i_reg : out STD_LOGIC; \goreg_bm.dout_i_reg[68]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + v1_reg : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 ); + v1_reg_0 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + S : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rvalid : out STD_LOGIC; - \gcc0.gc0.count_d1_reg[1]\ : in STD_LOGIC; - \gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC; - \gcc0.gc0.count_d1_reg[5]\ : in STD_LOGIC; - \gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC; - \gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC; - \gcc0.gc0.count_d1_reg[3]\ : in STD_LOGIC; - \gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC; - \gcc0.gc0.count_d1_reg[6]_0\ : in STD_LOGIC; + \gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC; + v1_reg_1 : in STD_LOGIC_VECTOR ( 3 downto 0 ); \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ : in STD_LOGIC; s_aclk : in STD_LOGIC; \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gcc0.gc0.count_d1_reg[8]_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); s_axi_rready : in STD_LOGIC; - arready_pkt : in STD_LOGIC; + ram_full_fb_i_reg : in STD_LOGIC; + m_axi_rvalid : in STD_LOGIC; + \gcc0.gc0.count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); CO : in STD_LOGIC_VECTOR ( 0 to 0 ); + arready_pkt : in STD_LOGIC; empty_fwft_i_reg : in STD_LOGIC; - \gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - \gcc0.gc0.count_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); - ram_full_fb_i_reg : in STD_LOGIC; - m_axi_rvalid : in STD_LOGIC + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \Arty_Z7_20_s00_data_fifo_0_rd_logic__parameterized0\ : entity is "rd_logic"; @@ -8437,66 +8745,69 @@ end \Arty_Z7_20_s00_data_fifo_0_rd_logic__parameterized0\; architecture STRUCTURE of \Arty_Z7_20_s00_data_fifo_0_rd_logic__parameterized0\ is signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \gr1.gr1_int.rfwft_n_5\ : STD_LOGIC; + signal \gr1.gr1_int.rfwft_n_4\ : STD_LOGIC; signal p_2_out : STD_LOGIC; - signal rpntr_n_10 : STD_LOGIC; - signal rpntr_n_12 : STD_LOGIC; + signal rpntr_n_0 : STD_LOGIC; + signal rpntr_n_26 : STD_LOGIC; + signal rpntr_n_27 : STD_LOGIC; + signal rpntr_n_28 : STD_LOGIC; + signal rpntr_n_29 : STD_LOGIC; begin E(0) <= \^e\(0); \gr1.gr1_int.rfwft\: entity work.\Arty_Z7_20_s00_data_fifo_0_rd_fwft__parameterized0\ port map ( CO(0) => CO(0), E(0) => \^e\(0), - Q(0) => Q(0), S(0) => S(0), SR(0) => SR(0), arready_pkt => arready_pkt, empty_fwft_i_reg_0 => empty_fwft_i_reg, fwft_rst_done_q => fwft_rst_done_q, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(0), \goreg_bm.dout_i_reg[68]\(0) => \goreg_bm.dout_i_reg[68]\(0), \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\, \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1 downto 0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1 downto 0), \out\ => \out\, ram_empty_fb_i_reg => p_2_out, - ram_empty_i_reg => \gr1.gr1_int.rfwft_n_5\, - ram_full_i_reg => ram_full_i_reg_1, + ram_empty_i_reg => \gr1.gr1_int.rfwft_n_4\, + ram_full_i_reg => ram_full_i_reg, s_aclk => s_aclk, s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid ); \grss.rsts\: entity work.\Arty_Z7_20_s00_data_fifo_0_rd_status_flags_ss__parameterized0\ port map ( - \gc0.count_d1_reg[8]\ => rpntr_n_12, - \gc0.count_reg[8]\ => rpntr_n_10, - \gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\, - \gcc0.gc0.count_d1_reg[1]\ => \gcc0.gc0.count_d1_reg[1]\, - \gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\, - \gcc0.gc0.count_d1_reg[3]\ => \gcc0.gc0.count_d1_reg[3]\, - \gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\, - \gcc0.gc0.count_d1_reg[5]\ => \gcc0.gc0.count_d1_reg[5]\, - \gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\, - \gcc0.gc0.count_d1_reg[6]_0\ => \gcc0.gc0.count_d1_reg[6]_0\, - \gpregsm1.curr_fwft_state_reg[0]\ => \gr1.gr1_int.rfwft_n_5\, + \gc0.count_d1_reg[0]\ => rpntr_n_26, + \gc0.count_d1_reg[2]\ => rpntr_n_27, + \gc0.count_d1_reg[5]\ => rpntr_n_28, + \gc0.count_d1_reg[7]\ => rpntr_n_29, + \gc0.count_reg[8]\ => rpntr_n_0, + \gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\, + \gpregsm1.curr_fwft_state_reg[1]\ => \gr1.gr1_int.rfwft_n_4\, m_axi_rvalid => m_axi_rvalid, \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\, \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1), \out\ => p_2_out, ram_full_fb_i_reg => ram_full_fb_i_reg, - s_aclk => s_aclk + s_aclk => s_aclk, + v1_reg_1(3 downto 0) => v1_reg_1(3 downto 0) ); rpntr: entity work.\Arty_Z7_20_s00_data_fifo_0_rd_bin_cntr__parameterized0\ port map ( + \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0), E(0) => \^e\(0), - Q(8 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0), - \gc0.count_d1_reg[7]_0\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0), - \gcc0.gc0.count_d1_reg[8]\(0) => \gcc0.gc0.count_d1_reg[8]\(0), - \gcc0.gc0.count_reg[8]\(0) => \gcc0.gc0.count_reg[8]\(0), + Q(7 downto 0) => Q(7 downto 0), + \gcc0.gc0.count_d1_reg[8]\(8 downto 0) => \gcc0.gc0.count_d1_reg[8]_0\(8 downto 0), + \gcc0.gc0.count_reg[7]\(7 downto 0) => \gcc0.gc0.count_reg[7]\(7 downto 0), \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\, - ram_empty_i_reg => rpntr_n_10, - ram_empty_i_reg_0 => rpntr_n_12, - ram_full_i_reg => ram_full_i_reg, - ram_full_i_reg_0 => ram_full_i_reg_0, - s_aclk => s_aclk + ram_empty_i_reg => rpntr_n_0, + ram_empty_i_reg_0 => rpntr_n_26, + ram_empty_i_reg_1 => rpntr_n_27, + ram_empty_i_reg_2 => rpntr_n_28, + ram_empty_i_reg_3 => rpntr_n_29, + s_aclk => s_aclk, + v1_reg(3 downto 0) => v1_reg(3 downto 0), + v1_reg_0(3 downto 0) => v1_reg_0(3 downto 0) ); end STRUCTURE; library IEEE; @@ -8507,27 +8818,21 @@ entity \Arty_Z7_20_s00_data_fifo_0_wr_logic__parameterized0\ is port ( \out\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 8 downto 0 ); + \gcc0.gc0.count_d1_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); ram_empty_i_reg : out STD_LOGIC; - ram_empty_i_reg_0 : out STD_LOGIC; - ram_empty_i_reg_1 : out STD_LOGIC; - ram_empty_i_reg_2 : out STD_LOGIC; - \gcc0.gc0.count_d1_reg[8]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - ram_empty_i_reg_3 : out STD_LOGIC; - ram_empty_i_reg_4 : out STD_LOGIC; - ram_empty_i_reg_5 : out STD_LOGIC; - ram_empty_i_reg_6 : out STD_LOGIC; + v1_reg : out STD_LOGIC_VECTOR ( 3 downto 0 ); E : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_rready : out STD_LOGIC; - \gc0.count_d1_reg[8]\ : in STD_LOGIC; - \gc0.count_d1_reg[8]_0\ : in STD_LOGIC; + v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 ); + v1_reg_1 : in STD_LOGIC_VECTOR ( 3 downto 0 ); \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ : in STD_LOGIC; s_aclk : in STD_LOGIC; \grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC; - \gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); - \gc0.count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC; + m_axi_rvalid : in STD_LOGIC; ram_empty_fb_i_reg : in STD_LOGIC; - m_axi_rvalid : in STD_LOGIC + \gc0.count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \Arty_Z7_20_s00_data_fifo_0_wr_logic__parameterized0\ : entity is "wr_logic"; @@ -8537,27 +8842,13 @@ architecture STRUCTURE of \Arty_Z7_20_s00_data_fifo_0_wr_logic__parameterized0\ signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal wpntr_n_0 : STD_LOGIC; signal wpntr_n_10 : STD_LOGIC; - signal wpntr_n_11 : STD_LOGIC; - signal wpntr_n_12 : STD_LOGIC; - signal wpntr_n_17 : STD_LOGIC; - signal wpntr_n_18 : STD_LOGIC; - signal wpntr_n_19 : STD_LOGIC; - signal wpntr_n_20 : STD_LOGIC; begin E(0) <= \^e\(0); \gwss.wsts\: entity work.\Arty_Z7_20_s00_data_fifo_0_wr_status_flags_ss__parameterized0\ port map ( E(0) => \^e\(0), - \gc0.count_d1_reg[8]\ => \gc0.count_d1_reg[8]\, - \gc0.count_d1_reg[8]_0\ => \gc0.count_d1_reg[8]_0\, - \gcc0.gc0.count_d1_reg[1]\ => wpntr_n_12, - \gcc0.gc0.count_d1_reg[2]\ => wpntr_n_11, - \gcc0.gc0.count_d1_reg[5]\ => wpntr_n_10, - \gcc0.gc0.count_d1_reg[6]\ => wpntr_n_0, - \gcc0.gc0.count_reg[1]\ => wpntr_n_20, - \gcc0.gc0.count_reg[3]\ => wpntr_n_19, - \gcc0.gc0.count_reg[5]\ => wpntr_n_18, - \gcc0.gc0.count_reg[7]\ => wpntr_n_17, + \gcc0.gc0.count_d1_reg[8]\ => wpntr_n_0, + \gcc0.gc0.count_reg[8]\ => wpntr_n_10, \grstd1.grst_full.grst_f.rst_d2_reg\ => \grstd1.grst_full.grst_f.rst_d2_reg\, \grstd1.grst_full.grst_f.rst_d3_reg\ => \grstd1.grst_full.grst_f.rst_d3_reg\, m_axi_rready => m_axi_rready, @@ -8565,33 +8856,23 @@ begin \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\, \out\ => \out\, ram_empty_fb_i_reg => ram_empty_fb_i_reg, - s_aclk => s_aclk + s_aclk => s_aclk, + v1_reg_0(3 downto 0) => v1_reg_0(3 downto 0), + v1_reg_1(3 downto 0) => v1_reg_1(3 downto 0) ); wpntr: entity work.\Arty_Z7_20_s00_data_fifo_0_wr_bin_cntr__parameterized0\ port map ( E(0) => \^e\(0), Q(8 downto 0) => Q(8 downto 0), - \gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0), + \gc0.count_d1_reg[8]\(0) => \gc0.count_d1_reg[8]\(0), \gc0.count_reg[7]\(7 downto 0) => \gc0.count_reg[7]\(7 downto 0), - \gcc0.gc0.count_d1_reg[8]_0\(0) => \gcc0.gc0.count_d1_reg[8]\(0), + \gcc0.gc0.count_d1_reg[7]_0\(7 downto 0) => \gcc0.gc0.count_d1_reg[7]\(7 downto 0), \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ => \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\, ram_empty_i_reg => ram_empty_i_reg, - ram_empty_i_reg_0 => ram_empty_i_reg_0, - ram_empty_i_reg_1 => ram_empty_i_reg_1, - ram_empty_i_reg_2 => ram_empty_i_reg_2, - ram_empty_i_reg_3 => ram_empty_i_reg_3, - ram_empty_i_reg_4 => ram_empty_i_reg_4, - ram_empty_i_reg_5 => ram_empty_i_reg_5, - ram_empty_i_reg_6 => ram_empty_i_reg_6, ram_full_i_reg => wpntr_n_0, ram_full_i_reg_0 => wpntr_n_10, - ram_full_i_reg_1 => wpntr_n_11, - ram_full_i_reg_2 => wpntr_n_12, - ram_full_i_reg_3 => wpntr_n_17, - ram_full_i_reg_4 => wpntr_n_18, - ram_full_i_reg_5 => wpntr_n_19, - ram_full_i_reg_6 => wpntr_n_20, - s_aclk => s_aclk + s_aclk => s_aclk, + v1_reg(3 downto 0) => v1_reg(3 downto 0) ); end STRUCTURE; library IEEE; @@ -8634,31 +8915,30 @@ use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20_s00_data_fifo_0_fifo_generator_top is port ( \out\ : out STD_LOGIC; - S : out STD_LOGIC_VECTOR ( 3 downto 0 ); - Q : out STD_LOGIC_VECTOR ( 55 downto 0 ); - \gfwd_rev_pipeline1.s_ready_i_reg\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); - \gfwd_rev_pipeline1.s_ready_i_reg_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + Q : out STD_LOGIC_VECTOR ( 62 downto 0 ); D : out STD_LOGIC_VECTOR ( 9 downto 0 ); E : out STD_LOGIC_VECTOR ( 0 to 0 ); aempty_fwft_i_reg : out STD_LOGIC; - DI : out STD_LOGIC_VECTOR ( 0 to 0 ); - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\ : out STD_LOGIC; + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]\ : out STD_LOGIC; s_axi_arready : out STD_LOGIC; - \gfwd_rev_pipeline1.s_ready_i_reg_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); - \gfwd_rev_pipeline1.s_ready_i_reg_2\ : out STD_LOGIC_VECTOR ( 0 to 0 ); - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + S : out STD_LOGIC_VECTOR ( 3 downto 0 ); + DI : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \gfwd_rev_pipeline1.s_ready_i_reg\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \gfwd_rev_pipeline1.s_ready_i_reg_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); s_aclk : in STD_LOGIC; inverted_reset : in STD_LOGIC; CO : in STD_LOGIC_VECTOR ( 0 to 0 ); arready_pkt : in STD_LOGIC; - s_axi_rready : in STD_LOGIC; - empty_fwft_fb_o_i_reg : in STD_LOGIC; - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); - rd_fifo_free_space : in STD_LOGIC_VECTOR ( 9 downto 0 ); s_axi_arvalid : in STD_LOGIC; - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); - UNCONN_IN : in STD_LOGIC_VECTOR ( 55 downto 0 ) + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); + rd_fifo_free_space : in STD_LOGIC_VECTOR ( 9 downto 0 ); + empty_fwft_fb_o_i_reg : in STD_LOGIC; + s_axi_rready : in STD_LOGIC; + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + UNCONN_IN : in STD_LOGIC_VECTOR ( 62 downto 0 ) ); end Arty_Z7_20_s00_data_fifo_0_fifo_generator_top; @@ -8668,23 +8948,22 @@ begin port map ( CO(0) => CO(0), D(9 downto 0) => D(9 downto 0), - DI(0) => DI(0), + DI(3 downto 0) => DI(3 downto 0), E(0) => E(0), - Q(55 downto 0) => Q(55 downto 0), + Q(62 downto 0) => Q(62 downto 0), S(3 downto 0) => S(3 downto 0), - UNCONN_IN(55 downto 0) => UNCONN_IN(55 downto 0), + UNCONN_IN(62 downto 0) => UNCONN_IN(62 downto 0), aempty_fwft_i_reg => aempty_fwft_i_reg, arready_pkt => arready_pkt, empty_fwft_fb_o_i_reg => empty_fwft_fb_o_i_reg, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\ => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_0\(0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_0\(0), - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_1\(3 downto 0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_1\(3 downto 0), - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(9 downto 0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(9 downto 0), - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0\(1 downto 0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0\(1 downto 0), - \gfwd_rev_pipeline1.s_ready_i_reg\(3 downto 0) => \gfwd_rev_pipeline1.s_ready_i_reg\(3 downto 0), + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]\ => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]\, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0\(3 downto 0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0\(3 downto 0), + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\(3 downto 0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\(3 downto 0), + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(0), + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0\(9 downto 0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0\(9 downto 0), + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_1\(1 downto 0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_1\(1 downto 0), + \gfwd_rev_pipeline1.s_ready_i_reg\(0) => \gfwd_rev_pipeline1.s_ready_i_reg\(0), \gfwd_rev_pipeline1.s_ready_i_reg_0\(0) => \gfwd_rev_pipeline1.s_ready_i_reg_0\(0), - \gfwd_rev_pipeline1.s_ready_i_reg_1\(3 downto 0) => \gfwd_rev_pipeline1.s_ready_i_reg_1\(3 downto 0), - \gfwd_rev_pipeline1.s_ready_i_reg_2\(0) => \gfwd_rev_pipeline1.s_ready_i_reg_2\(0), inverted_reset => inverted_reset, \out\ => \out\, rd_fifo_free_space(9 downto 0) => rd_fifo_free_space(9 downto 0), @@ -8775,7 +9054,7 @@ entity \Arty_Z7_20_s00_data_fifo_0_memory__parameterized0\ is m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); DIADI : in STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 ); - \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + \gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \Arty_Z7_20_s00_data_fifo_0_memory__parameterized0\ : entity is "memory"; @@ -8802,7 +9081,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(0), Q => UNCONN_OUT(0), R => '0' @@ -8813,7 +9092,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(10), Q => UNCONN_OUT(10), R => '0' @@ -8824,7 +9103,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(11), Q => UNCONN_OUT(11), R => '0' @@ -8835,7 +9114,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(12), Q => UNCONN_OUT(12), R => '0' @@ -8846,7 +9125,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(13), Q => UNCONN_OUT(13), R => '0' @@ -8857,7 +9136,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(14), Q => UNCONN_OUT(14), R => '0' @@ -8868,7 +9147,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(15), Q => UNCONN_OUT(15), R => '0' @@ -8879,7 +9158,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(16), Q => UNCONN_OUT(16), R => '0' @@ -8890,7 +9169,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(17), Q => UNCONN_OUT(17), R => '0' @@ -8901,7 +9180,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(18), Q => UNCONN_OUT(18), R => '0' @@ -8912,7 +9191,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(19), Q => UNCONN_OUT(19), R => '0' @@ -8923,7 +9202,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(1), Q => UNCONN_OUT(1), R => '0' @@ -8934,7 +9213,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(20), Q => UNCONN_OUT(20), R => '0' @@ -8945,7 +9224,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(21), Q => UNCONN_OUT(21), R => '0' @@ -8956,7 +9235,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(22), Q => UNCONN_OUT(22), R => '0' @@ -8967,7 +9246,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(23), Q => UNCONN_OUT(23), R => '0' @@ -8978,7 +9257,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(24), Q => UNCONN_OUT(24), R => '0' @@ -8989,7 +9268,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(25), Q => UNCONN_OUT(25), R => '0' @@ -9000,7 +9279,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(26), Q => UNCONN_OUT(26), R => '0' @@ -9011,7 +9290,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(27), Q => UNCONN_OUT(27), R => '0' @@ -9022,7 +9301,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(28), Q => UNCONN_OUT(28), R => '0' @@ -9033,7 +9312,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(29), Q => UNCONN_OUT(29), R => '0' @@ -9044,7 +9323,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(2), Q => UNCONN_OUT(2), R => '0' @@ -9055,7 +9334,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(30), Q => UNCONN_OUT(30), R => '0' @@ -9066,7 +9345,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(31), Q => UNCONN_OUT(31), R => '0' @@ -9077,7 +9356,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(32), Q => UNCONN_OUT(32), R => '0' @@ -9088,7 +9367,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(33), Q => UNCONN_OUT(33), R => '0' @@ -9099,7 +9378,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(34), Q => UNCONN_OUT(34), R => '0' @@ -9110,7 +9389,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(35), Q => UNCONN_OUT(35), R => '0' @@ -9121,7 +9400,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(36), Q => UNCONN_OUT(36), R => '0' @@ -9132,7 +9411,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(37), Q => UNCONN_OUT(37), R => '0' @@ -9143,7 +9422,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(38), Q => UNCONN_OUT(38), R => '0' @@ -9154,7 +9433,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(39), Q => UNCONN_OUT(39), R => '0' @@ -9165,7 +9444,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(3), Q => UNCONN_OUT(3), R => '0' @@ -9176,7 +9455,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(40), Q => UNCONN_OUT(40), R => '0' @@ -9187,7 +9466,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(41), Q => UNCONN_OUT(41), R => '0' @@ -9198,7 +9477,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(42), Q => UNCONN_OUT(42), R => '0' @@ -9209,7 +9488,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(43), Q => UNCONN_OUT(43), R => '0' @@ -9220,7 +9499,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(44), Q => UNCONN_OUT(44), R => '0' @@ -9231,7 +9510,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(45), Q => UNCONN_OUT(45), R => '0' @@ -9242,7 +9521,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(46), Q => UNCONN_OUT(46), R => '0' @@ -9253,7 +9532,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(47), Q => UNCONN_OUT(47), R => '0' @@ -9264,7 +9543,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(48), Q => UNCONN_OUT(48), R => '0' @@ -9275,7 +9554,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(49), Q => UNCONN_OUT(49), R => '0' @@ -9286,7 +9565,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(4), Q => UNCONN_OUT(4), R => '0' @@ -9297,7 +9576,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(50), Q => UNCONN_OUT(50), R => '0' @@ -9308,7 +9587,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(51), Q => UNCONN_OUT(51), R => '0' @@ -9319,7 +9598,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(52), Q => UNCONN_OUT(52), R => '0' @@ -9330,7 +9609,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(53), Q => UNCONN_OUT(53), R => '0' @@ -9341,7 +9620,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(54), Q => UNCONN_OUT(54), R => '0' @@ -9352,7 +9631,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(55), Q => UNCONN_OUT(55), R => '0' @@ -9363,7 +9642,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(56), Q => UNCONN_OUT(56), R => '0' @@ -9374,7 +9653,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(57), Q => UNCONN_OUT(57), R => '0' @@ -9385,7 +9664,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(58), Q => UNCONN_OUT(58), R => '0' @@ -9396,7 +9675,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(59), Q => UNCONN_OUT(59), R => '0' @@ -9407,7 +9686,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(5), Q => UNCONN_OUT(5), R => '0' @@ -9418,7 +9697,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(60), Q => UNCONN_OUT(60), R => '0' @@ -9429,7 +9708,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(61), Q => UNCONN_OUT(61), R => '0' @@ -9440,7 +9719,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(62), Q => UNCONN_OUT(62), R => '0' @@ -9451,7 +9730,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(63), Q => UNCONN_OUT(63), R => '0' @@ -9462,7 +9741,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(64), Q => UNCONN_OUT(64), R => '0' @@ -9473,7 +9752,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(65), Q => UNCONN_OUT(65), R => '0' @@ -9484,7 +9763,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(66), Q => UNCONN_OUT(66), R => '0' @@ -9495,7 +9774,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(67), Q => UNCONN_OUT(67), R => '0' @@ -9506,7 +9785,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(68), Q => UNCONN_OUT(68), R => '0' @@ -9517,7 +9796,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(6), Q => UNCONN_OUT(6), R => '0' @@ -9528,7 +9807,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(7), Q => UNCONN_OUT(7), R => '0' @@ -9539,7 +9818,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(8), Q => UNCONN_OUT(8), R => '0' @@ -9550,7 +9829,7 @@ begin ) port map ( C => s_aclk, - CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0), + CE => \gpregsm1.curr_fwft_state_reg[0]\(0), D => doutb(9), Q => UNCONN_OUT(9), R => '0' @@ -9572,12 +9851,12 @@ entity \Arty_Z7_20_s00_data_fifo_0_fifo_generator_ramfifo__parameterized0\ is DIADI : in STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 ); inverted_reset : in STD_LOGIC; - Q : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rready : in STD_LOGIC; - arready_pkt : in STD_LOGIC; + m_axi_rvalid : in STD_LOGIC; CO : in STD_LOGIC_VECTOR ( 0 to 0 ); + arready_pkt : in STD_LOGIC; empty_fwft_i_reg : in STD_LOGIC; - m_axi_rvalid : in STD_LOGIC + Q : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \Arty_Z7_20_s00_data_fifo_0_fifo_generator_ramfifo__parameterized0\ : entity is "fifo_generator_ramfifo"; @@ -9586,22 +9865,16 @@ end \Arty_Z7_20_s00_data_fifo_0_fifo_generator_ramfifo__parameterized0\; architecture STRUCTURE of \Arty_Z7_20_s00_data_fifo_0_fifo_generator_ramfifo__parameterized0\ is signal dout_i : STD_LOGIC; signal full_fb_rdch : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.rd_n_21\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.rd_n_23\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.rd_n_3\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.wr_n_10\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.wr_n_11\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.wr_n_12\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.wr_n_13\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.wr_n_15\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.wr_n_16\ : STD_LOGIC; - signal \gntv_or_sync_fifo.gl0.wr_n_17\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd_n_11\ : STD_LOGIC; signal \gntv_or_sync_fifo.gl0.wr_n_18\ : STD_LOGIC; signal \gr1.gr1_int.rfwft/fwft_rst_done_q\ : STD_LOGIC; signal \gr1.gr1_int.rfwft/p_1_out\ : STD_LOGIC; + signal \grss.rsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \gwss.wsts/c0/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \gwss.wsts/c1/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal p_0_out : STD_LOGIC_VECTOR ( 8 downto 0 ); signal p_12_out : STD_LOGIC_VECTOR ( 8 downto 0 ); - signal p_13_out : STD_LOGIC_VECTOR ( 8 to 8 ); + signal p_13_out : STD_LOGIC_VECTOR ( 7 downto 0 ); signal p_19_out : STD_LOGIC; signal ram_rd_en_i : STD_LOGIC; signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 7 downto 0 ); @@ -9615,23 +9888,16 @@ begin CO(0) => CO(0), \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0) => p_0_out(8 downto 0), E(0) => ram_rd_en_i, - Q(0) => Q(0), + Q(7 downto 0) => rd_pntr_plus1(7 downto 0), S(0) => S(0), SR(0) => \gr1.gr1_int.rfwft/p_1_out\, arready_pkt => arready_pkt, empty_fwft_i_reg => empty_fwft_i_reg, fwft_rst_done_q => \gr1.gr1_int.rfwft/fwft_rst_done_q\, - \gc0.count_d1_reg[7]\(7 downto 0) => rd_pntr_plus1(7 downto 0), - \gcc0.gc0.count_d1_reg[0]\ => \gntv_or_sync_fifo.gl0.wr_n_13\, - \gcc0.gc0.count_d1_reg[1]\ => \gntv_or_sync_fifo.gl0.wr_n_15\, - \gcc0.gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.wr_n_16\, - \gcc0.gc0.count_d1_reg[3]\ => \gntv_or_sync_fifo.gl0.wr_n_12\, - \gcc0.gc0.count_d1_reg[4]\ => \gntv_or_sync_fifo.gl0.wr_n_11\, - \gcc0.gc0.count_d1_reg[5]\ => \gntv_or_sync_fifo.gl0.wr_n_17\, - \gcc0.gc0.count_d1_reg[6]\ => \gntv_or_sync_fifo.gl0.wr_n_18\, - \gcc0.gc0.count_d1_reg[6]_0\ => \gntv_or_sync_fifo.gl0.wr_n_10\, - \gcc0.gc0.count_d1_reg[8]\(0) => p_12_out(8), - \gcc0.gc0.count_reg[8]\(0) => p_13_out(8), + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(0) => Q(0), + \gcc0.gc0.count_d1_reg[8]\ => \gntv_or_sync_fifo.gl0.wr_n_18\, + \gcc0.gc0.count_d1_reg[8]_0\(8 downto 0) => p_12_out(8 downto 0), + \gcc0.gc0.count_reg[7]\(7 downto 0) => p_13_out(7 downto 0), \goreg_bm.dout_i_reg[68]\(0) => dout_i, m_axi_rvalid => m_axi_rvalid, \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ => rstblk_n_4, @@ -9639,38 +9905,33 @@ begin \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => rd_rst_i(0), \out\ => \out\, ram_full_fb_i_reg => full_fb_rdch, - ram_full_i_reg => \gntv_or_sync_fifo.gl0.rd_n_3\, - ram_full_i_reg_0 => \gntv_or_sync_fifo.gl0.rd_n_21\, - ram_full_i_reg_1 => \gntv_or_sync_fifo.gl0.rd_n_23\, + ram_full_i_reg => \gntv_or_sync_fifo.gl0.rd_n_11\, s_aclk => s_aclk, s_axi_rready => s_axi_rready, - s_axi_rvalid => s_axi_rvalid + s_axi_rvalid => s_axi_rvalid, + v1_reg(3 downto 0) => \gwss.wsts/c0/v1_reg\(3 downto 0), + v1_reg_0(3 downto 0) => \gwss.wsts/c1/v1_reg\(3 downto 0), + v1_reg_1(3 downto 0) => \grss.rsts/c2/v1_reg\(3 downto 0) ); \gntv_or_sync_fifo.gl0.wr\: entity work.\Arty_Z7_20_s00_data_fifo_0_wr_logic__parameterized0\ port map ( E(0) => p_19_out, Q(8 downto 0) => p_12_out(8 downto 0), - \gc0.count_d1_reg[7]\(7 downto 0) => p_0_out(7 downto 0), - \gc0.count_d1_reg[8]\ => \gntv_or_sync_fifo.gl0.rd_n_3\, - \gc0.count_d1_reg[8]_0\ => \gntv_or_sync_fifo.gl0.rd_n_21\, + \gc0.count_d1_reg[8]\(0) => p_0_out(8), \gc0.count_reg[7]\(7 downto 0) => rd_pntr_plus1(7 downto 0), - \gcc0.gc0.count_d1_reg[8]\(0) => p_13_out(8), + \gcc0.gc0.count_d1_reg[7]\(7 downto 0) => p_13_out(7 downto 0), \grstd1.grst_full.grst_f.rst_d2_reg\ => rst_full_ff_i, \grstd1.grst_full.grst_f.rst_d3_reg\ => rst_full_gen_i, m_axi_rready => m_axi_rready, m_axi_rvalid => m_axi_rvalid, \ngwrdrst.grst.g7serrst.gsckt_wrst.gcc_rst.safety_ckt_wr_rst_i_reg\ => rstblk_n_4, \out\ => full_fb_rdch, - ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.rd_n_23\, - ram_empty_i_reg => \gntv_or_sync_fifo.gl0.wr_n_10\, - ram_empty_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_11\, - ram_empty_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_12\, - ram_empty_i_reg_2 => \gntv_or_sync_fifo.gl0.wr_n_13\, - ram_empty_i_reg_3 => \gntv_or_sync_fifo.gl0.wr_n_15\, - ram_empty_i_reg_4 => \gntv_or_sync_fifo.gl0.wr_n_16\, - ram_empty_i_reg_5 => \gntv_or_sync_fifo.gl0.wr_n_17\, - ram_empty_i_reg_6 => \gntv_or_sync_fifo.gl0.wr_n_18\, - s_aclk => s_aclk + ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.rd_n_11\, + ram_empty_i_reg => \gntv_or_sync_fifo.gl0.wr_n_18\, + s_aclk => s_aclk, + v1_reg(3 downto 0) => \grss.rsts/c2/v1_reg\(3 downto 0), + v1_reg_0(3 downto 0) => \gwss.wsts/c0/v1_reg\(3 downto 0), + v1_reg_1(3 downto 0) => \gwss.wsts/c1/v1_reg\(3 downto 0) ); \gntv_or_sync_fifo.mem\: entity work.\Arty_Z7_20_s00_data_fifo_0_memory__parameterized0\ port map ( @@ -9679,9 +9940,9 @@ begin Q(8 downto 0) => p_12_out(8 downto 0), UNCONN_OUT(68 downto 0) => UNCONN_OUT(68 downto 0), \gc0.count_d1_reg[8]\(8 downto 0) => p_0_out(8 downto 0), + \gpregsm1.curr_fwft_state_reg[0]\(0) => dout_i, m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0), m_axi_rid(0) => m_axi_rid(0), - \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0) => dout_i, ram_full_fb_i_reg(0) => p_19_out, s_aclk => s_aclk ); @@ -9689,7 +9950,7 @@ rstblk: entity work.\Arty_Z7_20_s00_data_fifo_0_reset_blk_ramfifo__parameterized port map ( SR(0) => \gr1.gr1_int.rfwft/p_1_out\, fwft_rst_done_q => \gr1.gr1_int.rfwft/fwft_rst_done_q\, - \gcc0.gc0.count_reg[1]\ => rstblk_n_4, + \gcc0.gc0.count_d1_reg[0]\ => rstblk_n_4, inverted_reset => inverted_reset, \out\(1) => rd_rst_i(2), \out\(0) => rd_rst_i(0), @@ -9714,12 +9975,12 @@ entity \Arty_Z7_20_s00_data_fifo_0_fifo_generator_top__parameterized0\ is DIADI : in STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 ); inverted_reset : in STD_LOGIC; - Q : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rready : in STD_LOGIC; - arready_pkt : in STD_LOGIC; + m_axi_rvalid : in STD_LOGIC; CO : in STD_LOGIC_VECTOR ( 0 to 0 ); + arready_pkt : in STD_LOGIC; empty_fwft_i_reg : in STD_LOGIC; - m_axi_rvalid : in STD_LOGIC + Q : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \Arty_Z7_20_s00_data_fifo_0_fifo_generator_top__parameterized0\ : entity is "fifo_generator_top"; @@ -9755,34 +10016,34 @@ entity Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3_synth is port ( Q : out STD_LOGIC_VECTOR ( 68 downto 0 ); m_axi_arvalid : out STD_LOGIC; - UNCONN_OUT : out STD_LOGIC_VECTOR ( 55 downto 0 ); + UNCONN_OUT : out STD_LOGIC_VECTOR ( 62 downto 0 ); s_axi_arready : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; m_axi_rready : out STD_LOGIC; - s_axi_rready : in STD_LOGIC; + s_axi_arvalid : in STD_LOGIC; s_aclk : in STD_LOGIC; m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); DIADI : in STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arready : in STD_LOGIC; - DI : in STD_LOGIC_VECTOR ( 55 downto 0 ); + DI : in STD_LOGIC_VECTOR ( 62 downto 0 ); + s_axi_rready : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; - s_axi_arvalid : in STD_LOGIC; s_aresetn : in STD_LOGIC ); end Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3_synth; architecture STRUCTURE of Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3_synth is - signal L : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal \_inferred__0/i__carry__0_n_0\ : STD_LOGIC; - signal \_inferred__0/i__carry__0_n_1\ : STD_LOGIC; - signal \_inferred__0/i__carry__0_n_2\ : STD_LOGIC; - signal \_inferred__0/i__carry__0_n_3\ : STD_LOGIC; - signal \_inferred__0/i__carry__1_n_3\ : STD_LOGIC; - signal \_inferred__0/i__carry_n_0\ : STD_LOGIC; - signal \_inferred__0/i__carry_n_1\ : STD_LOGIC; - signal \_inferred__0/i__carry_n_2\ : STD_LOGIC; - signal \_inferred__0/i__carry_n_3\ : STD_LOGIC; + signal L : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \_carry__0_n_0\ : STD_LOGIC; + signal \_carry__0_n_1\ : STD_LOGIC; + signal \_carry__0_n_2\ : STD_LOGIC; + signal \_carry__0_n_3\ : STD_LOGIC; + signal \_carry__1_n_3\ : STD_LOGIC; + signal \_carry_n_0\ : STD_LOGIC; + signal \_carry_n_1\ : STD_LOGIC; + signal \_carry_n_2\ : STD_LOGIC; + signal \_carry_n_3\ : STD_LOGIC; signal arready_pkt : STD_LOGIC; signal arvalid_en : STD_LOGIC; signal arvalid_en0_carry_n_0 : STD_LOGIC; @@ -9790,10 +10051,6 @@ architecture STRUCTURE of Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3_synt signal arvalid_en0_carry_n_2 : STD_LOGIC; signal arvalid_en0_carry_n_3 : STD_LOGIC; signal empty_fb_rdch : STD_LOGIC; - signal \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_3_n_0\ : STD_LOGIC; - signal \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_4_n_0\ : STD_LOGIC; - signal \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_5_n_0\ : STD_LOGIC; - signal \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_6_n_0\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[9]_i_5_n_0\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[9]_i_6_n_0\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[0]\ : STD_LOGIC; @@ -9833,10 +10090,6 @@ architecture STRUCTURE of Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3_synt signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_31\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_32\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_33\ : STD_LOGIC; - signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_34\ : STD_LOGIC; - signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_35\ : STD_LOGIC; - signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_36\ : STD_LOGIC; - signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_37\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_4\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_42\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_43\ : STD_LOGIC; @@ -9862,92 +10115,98 @@ architecture STRUCTURE of Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3_synt signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_61\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_62\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_63\ : STD_LOGIC; - signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_64\ : STD_LOGIC; - signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_65\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_7\ : STD_LOGIC; + signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_74\ : STD_LOGIC; + signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_75\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_76\ : STD_LOGIC; - signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_77\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_78\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_79\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_8\ : STD_LOGIC; + signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_80\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_81\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_82\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_83\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_84\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_85\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_86\ : STD_LOGIC; + signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_87\ : STD_LOGIC; + signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_88\ : STD_LOGIC; + signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_89\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_9\ : STD_LOGIC; + signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_90\ : STD_LOGIC; + signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_91\ : STD_LOGIC; + signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_92\ : STD_LOGIC; + signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_93\ : STD_LOGIC; + signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_94\ : STD_LOGIC; + signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_95\ : STD_LOGIC; + signal \gaxi_full_lite.gread_ch.grach2.axi_rach_n_96\ : STD_LOGIC; signal \gaxi_full_lite.gread_ch.grdch2.axi_rdch_n_1\ : STD_LOGIC; - signal \i__carry__0_i_2_n_0\ : STD_LOGIC; - signal \i__carry__0_i_3_n_0\ : STD_LOGIC; - signal \i__carry__1_i_1_n_0\ : STD_LOGIC; - signal \i__carry__1_i_2_n_0\ : STD_LOGIC; signal inverted_reset : STD_LOGIC; signal p_0_out_2 : STD_LOGIC; signal p_1_in : STD_LOGIC_VECTOR ( 9 downto 0 ); signal rach_empty : STD_LOGIC; signal rd_fifo_free_space : STD_LOGIC_VECTOR ( 9 downto 0 ); - signal \NLW__inferred__0/i__carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); - signal \NLW__inferred__0/i__carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW__carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW__carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal NLW_arvalid_en0_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_arvalid_en0_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_arvalid_en0_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); attribute METHODOLOGY_DRC_VIOS : string; - attribute METHODOLOGY_DRC_VIOS of \_inferred__0/i__carry\ : label is "{SYNTH-8 {cell *THIS*}}"; - attribute METHODOLOGY_DRC_VIOS of \_inferred__0/i__carry__0\ : label is "{SYNTH-8 {cell *THIS*}}"; - attribute METHODOLOGY_DRC_VIOS of \_inferred__0/i__carry__1\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \_carry\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \_carry__0\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \_carry__1\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of arvalid_en0_carry : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of \arvalid_en0_carry__0\ : label is "{SYNTH-8 {cell *THIS*}}"; begin -\_inferred__0/i__carry\: unisim.vcomponents.CARRY4 +\_carry\: unisim.vcomponents.CARRY4 port map ( CI => '0', - CO(3) => \_inferred__0/i__carry_n_0\, - CO(2) => \_inferred__0/i__carry_n_1\, - CO(1) => \_inferred__0/i__carry_n_2\, - CO(0) => \_inferred__0/i__carry_n_3\, + CO(3) => \_carry_n_0\, + CO(2) => \_carry_n_1\, + CO(1) => \_carry_n_2\, + CO(0) => \_carry_n_3\, CYINIT => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[0]\, DI(3) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[3]\, DI(2) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[2]\, DI(1) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[1]\, - DI(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_78\, + DI(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_76\, O(3 downto 0) => rd_fifo_free_space(3 downto 0), - S(3) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_1\, - S(2) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_2\, - S(1) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_3\, - S(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_4\ + S(3) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_88\, + S(2) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_89\, + S(1) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_90\, + S(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_91\ ); -\_inferred__0/i__carry__0\: unisim.vcomponents.CARRY4 +\_carry__0\: unisim.vcomponents.CARRY4 port map ( - CI => \_inferred__0/i__carry_n_0\, - CO(3) => \_inferred__0/i__carry__0_n_0\, - CO(2) => \_inferred__0/i__carry__0_n_1\, - CO(1) => \_inferred__0/i__carry__0_n_2\, - CO(0) => \_inferred__0/i__carry__0_n_3\, + CI => \_carry_n_0\, + CO(3) => \_carry__0_n_0\, + CO(2) => \_carry__0_n_1\, + CO(1) => \_carry__0_n_2\, + CO(0) => \_carry__0_n_3\, CYINIT => '0', - DI(3) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[6]\, - DI(2) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[5]\, - DI(1) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_79\, + DI(3) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[7]\, + DI(2) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[6]\, + DI(1) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[5]\, DI(0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[4]\, O(3 downto 0) => rd_fifo_free_space(7 downto 4), - S(3) => \i__carry__0_i_2_n_0\, - S(2) => \i__carry__0_i_3_n_0\, - S(1) => \gaxi_full_lite.gread_ch.grdch2.axi_rdch_n_1\, - S(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_86\ + S(3) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_92\, + S(2) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_93\, + S(1) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_94\, + S(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_95\ ); -\_inferred__0/i__carry__1\: unisim.vcomponents.CARRY4 +\_carry__1\: unisim.vcomponents.CARRY4 port map ( - CI => \_inferred__0/i__carry__0_n_0\, - CO(3 downto 1) => \NLW__inferred__0/i__carry__1_CO_UNCONNECTED\(3 downto 1), - CO(0) => \_inferred__0/i__carry__1_n_3\, + CI => \_carry__0_n_0\, + CO(3 downto 1) => \NLW__carry__1_CO_UNCONNECTED\(3 downto 1), + CO(0) => \_carry__1_n_3\, CYINIT => '0', DI(3 downto 1) => B"000", - DI(0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[7]\, - O(3 downto 2) => \NLW__inferred__0/i__carry__1_O_UNCONNECTED\(3 downto 2), + DI(0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[8]\, + O(3 downto 2) => \NLW__carry__1_O_UNCONNECTED\(3 downto 2), O(1 downto 0) => rd_fifo_free_space(9 downto 8), S(3 downto 2) => B"00", - S(1) => \i__carry__1_i_1_n_0\, - S(0) => \i__carry__1_i_2_n_0\ + S(1) => \gaxi_full_lite.gread_ch.grdch2.axi_rdch_n_1\, + S(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_96\ ); arvalid_en0_carry: unisim.vcomponents.CARRY4 port map ( @@ -9957,15 +10216,15 @@ arvalid_en0_carry: unisim.vcomponents.CARRY4 CO(1) => arvalid_en0_carry_n_2, CO(0) => arvalid_en0_carry_n_3, CYINIT => '0', - DI(3) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_81\, - DI(2) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_82\, - DI(1) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_83\, - DI(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_84\, + DI(3) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_82\, + DI(2) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_83\, + DI(1) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_84\, + DI(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_85\, O(3 downto 0) => NLW_arvalid_en0_carry_O_UNCONNECTED(3 downto 0), - S(3) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_61\, - S(2) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_62\, - S(1) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_63\, - S(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_64\ + S(3) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_78\, + S(2) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_79\, + S(1) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_80\, + S(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_81\ ); \arvalid_en0_carry__0\: unisim.vcomponents.CARRY4 port map ( @@ -9974,42 +10233,10 @@ arvalid_en0_carry: unisim.vcomponents.CARRY4 CO(0) => arvalid_en, CYINIT => '0', DI(3 downto 1) => B"000", - DI(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_85\, + DI(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_86\, O(3 downto 0) => \NLW_arvalid_en0_carry__0_O_UNCONNECTED\(3 downto 0), S(3 downto 1) => B"000", - S(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_65\ - ); -\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_3\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[7]\, - O => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_3_n_0\ - ); -\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_4\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[6]\, - O => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_4_n_0\ - ); -\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_5\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[5]\, - O => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_5_n_0\ - ); -\gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_6\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[4]\, - O => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_6_n_0\ + S(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_87\ ); \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[9]_i_5\: unisim.vcomponents.LUT1 generic map( @@ -10033,7 +10260,7 @@ arvalid_en0_carry: unisim.vcomponents.CARRY4 ) port map ( C => s_aclk, - CE => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_76\, + CE => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_74\, CLR => p_0_out_2, D => p_1_in(0), Q => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[0]\ @@ -10044,7 +10271,7 @@ arvalid_en0_carry: unisim.vcomponents.CARRY4 ) port map ( C => s_aclk, - CE => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_76\, + CE => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_74\, CLR => p_0_out_2, D => p_1_in(1), Q => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[1]\ @@ -10055,7 +10282,7 @@ arvalid_en0_carry: unisim.vcomponents.CARRY4 ) port map ( C => s_aclk, - CE => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_76\, + CE => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_74\, CLR => p_0_out_2, D => p_1_in(2), Q => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[2]\ @@ -10066,7 +10293,7 @@ arvalid_en0_carry: unisim.vcomponents.CARRY4 ) port map ( C => s_aclk, - CE => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_76\, + CE => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_74\, CLR => p_0_out_2, D => p_1_in(3), Q => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[3]\ @@ -10077,7 +10304,7 @@ arvalid_en0_carry: unisim.vcomponents.CARRY4 ) port map ( C => s_aclk, - CE => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_76\, + CE => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_74\, CLR => p_0_out_2, D => p_1_in(4), Q => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[4]\ @@ -10088,7 +10315,7 @@ arvalid_en0_carry: unisim.vcomponents.CARRY4 ) port map ( C => s_aclk, - CE => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_76\, + CE => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_74\, CLR => p_0_out_2, D => p_1_in(5), Q => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[5]\ @@ -10099,7 +10326,7 @@ arvalid_en0_carry: unisim.vcomponents.CARRY4 ) port map ( C => s_aclk, - CE => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_76\, + CE => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_74\, CLR => p_0_out_2, D => p_1_in(6), Q => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[6]\ @@ -10110,7 +10337,7 @@ arvalid_en0_carry: unisim.vcomponents.CARRY4 ) port map ( C => s_aclk, - CE => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_76\, + CE => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_74\, CLR => p_0_out_2, D => p_1_in(7), Q => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[7]\ @@ -10121,7 +10348,7 @@ arvalid_en0_carry: unisim.vcomponents.CARRY4 ) port map ( C => s_aclk, - CE => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_76\, + CE => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_74\, CLR => p_0_out_2, D => p_1_in(8), Q => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[8]\ @@ -10132,7 +10359,7 @@ arvalid_en0_carry: unisim.vcomponents.CARRY4 ) port map ( C => s_aclk, - CE => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_76\, + CE => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_74\, D => p_1_in(9), PRE => p_0_out_2, Q => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[9]\ @@ -10141,97 +10368,99 @@ arvalid_en0_carry: unisim.vcomponents.CARRY4 port map ( CO(0) => arvalid_en, D(9 downto 0) => p_1_in(9 downto 0), - DI(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_78\, - E(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_76\, - Q(55) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_5\, - Q(54) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_6\, - Q(53) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_7\, - Q(52) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_8\, - Q(51) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_9\, - Q(50) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_10\, - Q(49) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_11\, - Q(48) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_12\, - Q(47) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_13\, - Q(46) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_14\, - Q(45) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_15\, - Q(44) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_16\, - Q(43) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_17\, - Q(42) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_18\, - Q(41) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_19\, - Q(40) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_20\, - Q(39) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_21\, - Q(38) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_22\, - Q(37) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_23\, - Q(36) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_24\, - Q(35) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_25\, - Q(34) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_26\, - Q(33) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_27\, - Q(32) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_28\, - Q(31) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_29\, - Q(30) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_30\, - Q(29) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_31\, - Q(28) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_32\, - Q(27) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_33\, - Q(26) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_34\, - Q(25) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_35\, - Q(24) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_36\, - Q(23) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_37\, - Q(22 downto 19) => L(3 downto 0), - Q(18) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_42\, - Q(17) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_43\, - Q(16) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_44\, - Q(15) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_45\, - Q(14) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_46\, - Q(13) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_47\, - Q(12) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_48\, - Q(11) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_49\, - Q(10) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_50\, - Q(9) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_51\, - Q(8) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_52\, - Q(7) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_53\, - Q(6) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_54\, - Q(5) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_55\, - Q(4) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_56\, - Q(3) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_57\, - Q(2) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_58\, - Q(1) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_59\, - Q(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_60\, - S(3) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_1\, - S(2) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_2\, - S(1) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_3\, - S(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_4\, - UNCONN_IN(55 downto 0) => DI(55 downto 0), - aempty_fwft_i_reg => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_77\, + DI(3) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_82\, + DI(2) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_83\, + DI(1) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_84\, + DI(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_85\, + E(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_74\, + Q(62) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_1\, + Q(61) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_2\, + Q(60) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_3\, + Q(59) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_4\, + Q(58) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_5\, + Q(57) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_6\, + Q(56) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_7\, + Q(55) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_8\, + Q(54) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_9\, + Q(53) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_10\, + Q(52) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_11\, + Q(51) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_12\, + Q(50) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_13\, + Q(49) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_14\, + Q(48) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_15\, + Q(47) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_16\, + Q(46) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_17\, + Q(45) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_18\, + Q(44) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_19\, + Q(43) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_20\, + Q(42) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_21\, + Q(41) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_22\, + Q(40) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_23\, + Q(39) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_24\, + Q(38) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_25\, + Q(37) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_26\, + Q(36) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_27\, + Q(35) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_28\, + Q(34) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_29\, + Q(33) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_30\, + Q(32) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_31\, + Q(31) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_32\, + Q(30) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_33\, + Q(29 downto 22) => L(7 downto 0), + Q(21) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_42\, + Q(20) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_43\, + Q(19) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_44\, + Q(18) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_45\, + Q(17) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_46\, + Q(16) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_47\, + Q(15) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_48\, + Q(14) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_49\, + Q(13) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_50\, + Q(12) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_51\, + Q(11) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_52\, + Q(10) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_53\, + Q(9) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_54\, + Q(8) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_55\, + Q(7) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_56\, + Q(6) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_57\, + Q(5) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_58\, + Q(4) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_59\, + Q(3) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_60\, + Q(2) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_61\, + Q(1) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_62\, + Q(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_63\, + S(3) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_78\, + S(2) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_79\, + S(1) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_80\, + S(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_81\, + UNCONN_IN(62 downto 0) => DI(62 downto 0), + aempty_fwft_i_reg => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_75\, arready_pkt => arready_pkt, empty_fwft_fb_o_i_reg => empty_fb_rdch, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\ => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_79\, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_0\(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_86\, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_1\(3) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_3_n_0\, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_1\(2) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_4_n_0\, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_1\(1) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_5_n_0\, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]_1\(0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[7]_i_6_n_0\, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(9) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[9]\, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(8) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[8]\, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(7) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[7]\, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(6) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[6]\, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(5) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[5]\, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(4) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[4]\, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(3) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[3]\, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(2) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[2]\, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(1) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[1]\, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[0]\, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0\(1) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[9]_i_5_n_0\, - \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0\(0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[9]_i_6_n_0\, - \gfwd_rev_pipeline1.s_ready_i_reg\(3) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_61\, - \gfwd_rev_pipeline1.s_ready_i_reg\(2) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_62\, - \gfwd_rev_pipeline1.s_ready_i_reg\(1) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_63\, - \gfwd_rev_pipeline1.s_ready_i_reg\(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_64\, - \gfwd_rev_pipeline1.s_ready_i_reg_0\(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_65\, - \gfwd_rev_pipeline1.s_ready_i_reg_1\(3) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_81\, - \gfwd_rev_pipeline1.s_ready_i_reg_1\(2) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_82\, - \gfwd_rev_pipeline1.s_ready_i_reg_1\(1) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_83\, - \gfwd_rev_pipeline1.s_ready_i_reg_1\(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_84\, - \gfwd_rev_pipeline1.s_ready_i_reg_2\(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_85\, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]\ => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_76\, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0\(3) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_88\, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0\(2) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_89\, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0\(1) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_90\, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[3]_0\(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_91\, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\(3) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_92\, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\(2) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_93\, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\(1) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_94\, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[7]\(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_95\, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]\(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_96\, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0\(9) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[9]\, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0\(8) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[8]\, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0\(7) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[7]\, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0\(6) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[6]\, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0\(5) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[5]\, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0\(4) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[4]\, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0\(3) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[3]\, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0\(2) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[2]\, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0\(1) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[1]\, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_0\(0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[0]\, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_1\(1) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[9]_i_5_n_0\, + \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg[9]_1\(0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space[9]_i_6_n_0\, + \gfwd_rev_pipeline1.s_ready_i_reg\(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_86\, + \gfwd_rev_pipeline1.s_ready_i_reg_0\(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_87\, inverted_reset => inverted_reset, \out\ => rach_empty, rd_fifo_free_space(9 downto 0) => rd_fifo_free_space(9 downto 0), @@ -10243,62 +10472,65 @@ arvalid_en0_carry: unisim.vcomponents.CARRY4 \gaxi_full_lite.gread_ch.grach2.gaxi_arvld.rach_pkt_reg_slice\: entity work.Arty_Z7_20_s00_data_fifo_0_axi_reg_slice port map ( CO(0) => arvalid_en, - D(55) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_5\, - D(54) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_6\, - D(53) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_7\, - D(52) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_8\, - D(51) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_9\, - D(50) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_10\, - D(49) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_11\, - D(48) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_12\, - D(47) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_13\, - D(46) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_14\, - D(45) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_15\, - D(44) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_16\, - D(43) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_17\, - D(42) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_18\, - D(41) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_19\, - D(40) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_20\, - D(39) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_21\, - D(38) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_22\, - D(37) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_23\, - D(36) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_24\, - D(35) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_25\, - D(34) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_26\, - D(33) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_27\, - D(32) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_28\, - D(31) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_29\, - D(30) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_30\, - D(29) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_31\, - D(28) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_32\, - D(27) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_33\, - D(26) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_34\, - D(25) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_35\, - D(24) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_36\, - D(23) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_37\, - D(22 downto 19) => L(3 downto 0), - D(18) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_42\, - D(17) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_43\, - D(16) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_44\, - D(15) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_45\, - D(14) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_46\, - D(13) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_47\, - D(12) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_48\, - D(11) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_49\, - D(10) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_50\, - D(9) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_51\, - D(8) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_52\, - D(7) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_53\, - D(6) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_54\, - D(5) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_55\, - D(4) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_56\, - D(3) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_57\, - D(2) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_58\, - D(1) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_59\, - D(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_60\, - UNCONN_OUT(55 downto 0) => UNCONN_OUT(55 downto 0), + D(62) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_1\, + D(61) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_2\, + D(60) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_3\, + D(59) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_4\, + D(58) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_5\, + D(57) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_6\, + D(56) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_7\, + D(55) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_8\, + D(54) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_9\, + D(53) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_10\, + D(52) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_11\, + D(51) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_12\, + D(50) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_13\, + D(49) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_14\, + D(48) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_15\, + D(47) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_16\, + D(46) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_17\, + D(45) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_18\, + D(44) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_19\, + D(43) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_20\, + D(42) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_21\, + D(41) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_22\, + D(40) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_23\, + D(39) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_24\, + D(38) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_25\, + D(37) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_26\, + D(36) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_27\, + D(35) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_28\, + D(34) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_29\, + D(33) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_30\, + D(32) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_31\, + D(31) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_32\, + D(30) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_33\, + D(29 downto 22) => L(7 downto 0), + D(21) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_42\, + D(20) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_43\, + D(19) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_44\, + D(18) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_45\, + D(17) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_46\, + D(16) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_47\, + D(15) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_48\, + D(14) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_49\, + D(13) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_50\, + D(12) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_51\, + D(11) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_52\, + D(10) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_53\, + D(9) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_54\, + D(8) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_55\, + D(7) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_56\, + D(6) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_57\, + D(5) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_58\, + D(4) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_59\, + D(3) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_60\, + D(2) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_61\, + D(1) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_62\, + D(0) => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_63\, + UNCONN_OUT(62 downto 0) => UNCONN_OUT(62 downto 0), arready_pkt => arready_pkt, - \gfwd_rev_pipeline1.s_ready_i_reg_0\ => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_77\, + \gfwd_rev_pipeline1.s_ready_i_reg_0\ => \gaxi_full_lite.gread_ch.grach2.axi_rach_n_75\, inverted_reset => inverted_reset, m_axi_arready => m_axi_arready, m_axi_arvalid => m_axi_arvalid, @@ -10310,7 +10542,7 @@ arvalid_en0_carry: unisim.vcomponents.CARRY4 port map ( CO(0) => arvalid_en, DIADI(3 downto 0) => DIADI(3 downto 0), - Q(0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[5]\, + Q(0) => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[9]\, S(0) => \gaxi_full_lite.gread_ch.grdch2.axi_rdch_n_1\, UNCONN_OUT(68 downto 0) => Q(68 downto 0), arready_pkt => arready_pkt, @@ -10325,42 +10557,6 @@ arvalid_en0_carry: unisim.vcomponents.CARRY4 s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid ); -\i__carry__0_i_2\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[6]\, - I1 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[7]\, - O => \i__carry__0_i_2_n_0\ - ); -\i__carry__0_i_3\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[5]\, - I1 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[6]\, - O => \i__carry__0_i_3_n_0\ - ); -\i__carry__1_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[8]\, - I1 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[9]\, - O => \i__carry__1_i_1_n_0\ - ); -\i__carry__1_i_2\: unisim.vcomponents.LUT2 - generic map( - INIT => X"9" - ) - port map ( - I0 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[7]\, - I1 => \gaxi_full_lite.gread_ch.gaxi_pkt_fifo_rd.gaxi_mm_cc_pkt_rd.rd_fifo_free_space_reg_n_0_[8]\, - O => \i__carry__1_i_2_n_0\ - ); \reset_gen_cc.rstblk_cc\: entity work.Arty_Z7_20_s00_data_fifo_0_reset_blk_ramfifo port map ( AR(0) => p_0_out_2, @@ -10421,10 +10617,10 @@ entity Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 is s_aclk_en : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); @@ -10446,10 +10642,10 @@ entity Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 is s_axi_bready : in STD_LOGIC; m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); - m_axi_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); - m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); @@ -10471,10 +10667,10 @@ entity Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 is m_axi_bready : out STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); @@ -10491,10 +10687,10 @@ entity Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 is s_axi_rready : in STD_LOGIC; m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); - m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); - m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); @@ -10647,13 +10843,13 @@ entity Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 is attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 : entity is 1; attribute C_AXI_LEN_WIDTH : integer; - attribute C_AXI_LEN_WIDTH of Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 : entity is 4; + attribute C_AXI_LEN_WIDTH of Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 : entity is 8; attribute C_AXI_LOCK_WIDTH : integer; - attribute C_AXI_LOCK_WIDTH of Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 : entity is 2; + attribute C_AXI_LOCK_WIDTH of Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 : entity is 1; attribute C_AXI_RUSER_WIDTH : integer; attribute C_AXI_RUSER_WIDTH of Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 : entity is 1; attribute C_AXI_TYPE : integer; - attribute C_AXI_TYPE of Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 : entity is 3; + attribute C_AXI_TYPE of Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 : entity is 1; attribute C_AXI_WUSER_WIDTH : integer; attribute C_AXI_WUSER_WIDTH of Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 : entity is 1; attribute C_COMMON_CLOCK : integer; @@ -10669,15 +10865,15 @@ entity Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 is attribute C_DIN_WIDTH_AXIS : integer; attribute C_DIN_WIDTH_AXIS of Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 : entity is 1; attribute C_DIN_WIDTH_RACH : integer; - attribute C_DIN_WIDTH_RACH of Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 : entity is 60; + attribute C_DIN_WIDTH_RACH of Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 : entity is 63; attribute C_DIN_WIDTH_RDCH : integer; attribute C_DIN_WIDTH_RDCH of Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 : entity is 69; attribute C_DIN_WIDTH_WACH : integer; - attribute C_DIN_WIDTH_WACH of Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 : entity is 60; + attribute C_DIN_WIDTH_WACH of Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 : entity is 63; attribute C_DIN_WIDTH_WDCH : integer; - attribute C_DIN_WIDTH_WDCH of Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 : entity is 75; + attribute C_DIN_WIDTH_WDCH of Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 : entity is 74; attribute C_DIN_WIDTH_WRCH : integer; - attribute C_DIN_WIDTH_WRCH of Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 : entity is 75; + attribute C_DIN_WIDTH_WRCH of Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 : entity is 74; attribute C_DOUT_RST_VAL : string; attribute C_DOUT_RST_VAL of Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3 : entity is "0"; attribute C_DOUT_WIDTH : integer; @@ -11204,10 +11400,6 @@ begin dout(0) <= \\; empty <= \\; full <= \\; - m_axi_arregion(3) <= \\; - m_axi_arregion(2) <= \\; - m_axi_arregion(1) <= \\; - m_axi_arregion(0) <= \\; m_axi_awaddr(31) <= \\; m_axi_awaddr(30) <= \\; m_axi_awaddr(29) <= \\; @@ -11247,11 +11439,14 @@ begin m_axi_awcache(1) <= \\; m_axi_awcache(0) <= \\; m_axi_awid(0) <= \\; + m_axi_awlen(7) <= \\; + m_axi_awlen(6) <= \\; + m_axi_awlen(5) <= \\; + m_axi_awlen(4) <= \\; m_axi_awlen(3) <= \\; m_axi_awlen(2) <= \\; m_axi_awlen(1) <= \\; m_axi_awlen(0) <= \\; - m_axi_awlock(1) <= \\; m_axi_awlock(0) <= \\; m_axi_awprot(2) <= \\; m_axi_awprot(1) <= \\; @@ -11479,15 +11674,16 @@ GND: unisim.vcomponents.GND ); inst_fifo_gen: entity work.Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3_synth port map ( - DI(55) => s_axi_arid(0), - DI(54 downto 23) => s_axi_araddr(31 downto 0), - DI(22 downto 19) => s_axi_arlen(3 downto 0), - DI(18 downto 16) => s_axi_arsize(2 downto 0), - DI(15 downto 14) => s_axi_arburst(1 downto 0), - DI(13 downto 12) => s_axi_arlock(1 downto 0), - DI(11 downto 8) => s_axi_arcache(3 downto 0), - DI(7 downto 5) => s_axi_arprot(2 downto 0), - DI(4 downto 1) => s_axi_arqos(3 downto 0), + DI(62) => s_axi_arid(0), + DI(61 downto 30) => s_axi_araddr(31 downto 0), + DI(29 downto 22) => s_axi_arlen(7 downto 0), + DI(21 downto 19) => s_axi_arsize(2 downto 0), + DI(18 downto 17) => s_axi_arburst(1 downto 0), + DI(16) => s_axi_arlock(0), + DI(15 downto 12) => s_axi_arcache(3 downto 0), + DI(11 downto 9) => s_axi_arprot(2 downto 0), + DI(8 downto 5) => s_axi_arqos(3 downto 0), + DI(4 downto 1) => s_axi_arregion(3 downto 0), DI(0) => s_axi_aruser(0), DIADI(3 downto 2) => m_axi_rresp(1 downto 0), DIADI(1) => m_axi_ruser(0), @@ -11497,15 +11693,16 @@ inst_fifo_gen: entity work.Arty_Z7_20_s00_data_fifo_0_fifo_generator_v13_1_3_syn Q(3 downto 2) => s_axi_rresp(1 downto 0), Q(1) => s_axi_ruser(0), Q(0) => s_axi_rlast, - UNCONN_OUT(55) => m_axi_arid(0), - UNCONN_OUT(54 downto 23) => m_axi_araddr(31 downto 0), - UNCONN_OUT(22 downto 19) => m_axi_arlen(3 downto 0), - UNCONN_OUT(18 downto 16) => m_axi_arsize(2 downto 0), - UNCONN_OUT(15 downto 14) => m_axi_arburst(1 downto 0), - UNCONN_OUT(13 downto 12) => m_axi_arlock(1 downto 0), - UNCONN_OUT(11 downto 8) => m_axi_arcache(3 downto 0), - UNCONN_OUT(7 downto 5) => m_axi_arprot(2 downto 0), - UNCONN_OUT(4 downto 1) => m_axi_arqos(3 downto 0), + UNCONN_OUT(62) => m_axi_arid(0), + UNCONN_OUT(61 downto 30) => m_axi_araddr(31 downto 0), + UNCONN_OUT(29 downto 22) => m_axi_arlen(7 downto 0), + UNCONN_OUT(21 downto 19) => m_axi_arsize(2 downto 0), + UNCONN_OUT(18 downto 17) => m_axi_arburst(1 downto 0), + UNCONN_OUT(16) => m_axi_arlock(0), + UNCONN_OUT(15 downto 12) => m_axi_arcache(3 downto 0), + UNCONN_OUT(11 downto 9) => m_axi_arprot(2 downto 0), + UNCONN_OUT(8 downto 5) => m_axi_arqos(3 downto 0), + UNCONN_OUT(4 downto 1) => m_axi_arregion(3 downto 0), UNCONN_OUT(0) => m_axi_aruser(0), m_axi_arready => m_axi_arready, m_axi_arvalid => m_axi_arvalid, @@ -11531,10 +11728,10 @@ entity Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo is aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); @@ -11556,10 +11753,10 @@ entity Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo is s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); @@ -11576,10 +11773,10 @@ entity Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo is s_axi_rready : in STD_LOGIC; m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); - m_axi_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); - m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); @@ -11601,10 +11798,10 @@ entity Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo is m_axi_bready : out STD_LOGIC; m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); - m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); - m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); @@ -11633,7 +11830,7 @@ entity Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo is attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo : entity is 1; attribute C_AXI_PROTOCOL : integer; - attribute C_AXI_PROTOCOL of Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo : entity is 1; + attribute C_AXI_PROTOCOL of Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo : entity is 0; attribute C_AXI_READ_FIFO_DELAY : integer; attribute C_AXI_READ_FIFO_DELAY of Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo : entity is 1; attribute C_AXI_READ_FIFO_DEPTH : integer; @@ -11667,13 +11864,13 @@ entity Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo is attribute P_READ_FIFO_DEPTH_LOG : integer; attribute P_READ_FIFO_DEPTH_LOG of Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo : entity is 9; attribute P_WIDTH_RACH : integer; - attribute P_WIDTH_RACH of Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo : entity is 60; + attribute P_WIDTH_RACH of Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo : entity is 63; attribute P_WIDTH_RDCH : integer; attribute P_WIDTH_RDCH of Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo : entity is 69; attribute P_WIDTH_WACH : integer; - attribute P_WIDTH_WACH of Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo : entity is 60; + attribute P_WIDTH_WACH of Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo : entity is 63; attribute P_WIDTH_WDCH : integer; - attribute P_WIDTH_WDCH of Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo : entity is 75; + attribute P_WIDTH_WDCH of Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo : entity is 74; attribute P_WIDTH_WRCH : integer; attribute P_WIDTH_WRCH of Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo : entity is 4; attribute P_WRITE_FIFO_DEPTH_LOG : integer; @@ -11692,16 +11889,16 @@ architecture STRUCTURE of Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_d signal \^s_axi_awburst\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^s_axi_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^s_axi_awid\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \^s_axi_awlen\ : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal \^s_axi_awlock\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^s_axi_awlen\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \^s_axi_awlock\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^s_axi_awprot\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \^s_axi_awqos\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^s_axi_awregion\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^s_axi_awsize\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \^s_axi_awuser\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^s_axi_awvalid\ : STD_LOGIC; signal \^s_axi_bready\ : STD_LOGIC; signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 63 downto 0 ); - signal \^s_axi_wid\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^s_axi_wlast\ : STD_LOGIC; signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \^s_axi_wuser\ : STD_LOGIC_VECTOR ( 0 to 0 ); @@ -11786,13 +11983,12 @@ architecture STRUCTURE of Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_d signal \NLW_gen_fifo.fifo_gen_inst_axis_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 10 downto 0 ); signal \NLW_gen_fifo.fifo_gen_inst_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 ); signal \NLW_gen_fifo.fifo_gen_inst_dout_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 ); - signal \NLW_gen_fifo.fifo_gen_inst_m_axi_arregion_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gen_fifo.fifo_gen_inst_m_axi_awaddr_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_gen_fifo.fifo_gen_inst_m_axi_awburst_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \NLW_gen_fifo.fifo_gen_inst_m_axi_awcache_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gen_fifo.fifo_gen_inst_m_axi_awid_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \NLW_gen_fifo.fifo_gen_inst_m_axi_awlen_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal \NLW_gen_fifo.fifo_gen_inst_m_axi_awlock_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_gen_fifo.fifo_gen_inst_m_axi_awlen_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \NLW_gen_fifo.fifo_gen_inst_m_axi_awlock_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \NLW_gen_fifo.fifo_gen_inst_m_axi_awprot_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_gen_fifo.fifo_gen_inst_m_axi_awqos_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_gen_fifo.fifo_gen_inst_m_axi_awregion_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); @@ -11848,12 +12044,12 @@ architecture STRUCTURE of Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_d attribute C_AXI_DATA_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 64; attribute C_AXI_ID_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 1; attribute C_AXI_LEN_WIDTH : integer; - attribute C_AXI_LEN_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 4; + attribute C_AXI_LEN_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 8; attribute C_AXI_LOCK_WIDTH : integer; - attribute C_AXI_LOCK_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 2; + attribute C_AXI_LOCK_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 1; attribute C_AXI_RUSER_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 1; attribute C_AXI_TYPE : integer; - attribute C_AXI_TYPE of \gen_fifo.fifo_gen_inst\ : label is 3; + attribute C_AXI_TYPE of \gen_fifo.fifo_gen_inst\ : label is 1; attribute C_AXI_WUSER_WIDTH of \gen_fifo.fifo_gen_inst\ : label is 1; attribute C_COMMON_CLOCK : integer; attribute C_COMMON_CLOCK of \gen_fifo.fifo_gen_inst\ : label is 1; @@ -11868,15 +12064,15 @@ architecture STRUCTURE of Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_d attribute C_DIN_WIDTH_AXIS : integer; attribute C_DIN_WIDTH_AXIS of \gen_fifo.fifo_gen_inst\ : label is 1; attribute C_DIN_WIDTH_RACH : integer; - attribute C_DIN_WIDTH_RACH of \gen_fifo.fifo_gen_inst\ : label is 60; + attribute C_DIN_WIDTH_RACH of \gen_fifo.fifo_gen_inst\ : label is 63; attribute C_DIN_WIDTH_RDCH : integer; attribute C_DIN_WIDTH_RDCH of \gen_fifo.fifo_gen_inst\ : label is 69; attribute C_DIN_WIDTH_WACH : integer; - attribute C_DIN_WIDTH_WACH of \gen_fifo.fifo_gen_inst\ : label is 60; + attribute C_DIN_WIDTH_WACH of \gen_fifo.fifo_gen_inst\ : label is 63; attribute C_DIN_WIDTH_WDCH : integer; - attribute C_DIN_WIDTH_WDCH of \gen_fifo.fifo_gen_inst\ : label is 75; + attribute C_DIN_WIDTH_WDCH of \gen_fifo.fifo_gen_inst\ : label is 74; attribute C_DIN_WIDTH_WRCH : integer; - attribute C_DIN_WIDTH_WRCH of \gen_fifo.fifo_gen_inst\ : label is 75; + attribute C_DIN_WIDTH_WRCH of \gen_fifo.fifo_gen_inst\ : label is 74; attribute C_DOUT_RST_VAL : string; attribute C_DOUT_RST_VAL of \gen_fifo.fifo_gen_inst\ : label is "0"; attribute C_DOUT_WIDTH : integer; @@ -12219,42 +12415,35 @@ begin \^s_axi_awburst\(1 downto 0) <= s_axi_awburst(1 downto 0); \^s_axi_awcache\(3 downto 0) <= s_axi_awcache(3 downto 0); \^s_axi_awid\(0) <= s_axi_awid(0); - \^s_axi_awlen\(3 downto 0) <= s_axi_awlen(3 downto 0); - \^s_axi_awlock\(1 downto 0) <= s_axi_awlock(1 downto 0); + \^s_axi_awlen\(7 downto 0) <= s_axi_awlen(7 downto 0); + \^s_axi_awlock\(0) <= s_axi_awlock(0); \^s_axi_awprot\(2 downto 0) <= s_axi_awprot(2 downto 0); \^s_axi_awqos\(3 downto 0) <= s_axi_awqos(3 downto 0); + \^s_axi_awregion\(3 downto 0) <= s_axi_awregion(3 downto 0); \^s_axi_awsize\(2 downto 0) <= s_axi_awsize(2 downto 0); \^s_axi_awuser\(0) <= s_axi_awuser(0); \^s_axi_awvalid\ <= s_axi_awvalid; \^s_axi_bready\ <= s_axi_bready; \^s_axi_wdata\(63 downto 0) <= s_axi_wdata(63 downto 0); - \^s_axi_wid\(0) <= s_axi_wid(0); \^s_axi_wlast\ <= s_axi_wlast; \^s_axi_wstrb\(7 downto 0) <= s_axi_wstrb(7 downto 0); \^s_axi_wuser\(0) <= s_axi_wuser(0); \^s_axi_wvalid\ <= s_axi_wvalid; - m_axi_arregion(3) <= \\; - m_axi_arregion(2) <= \\; - m_axi_arregion(1) <= \\; - m_axi_arregion(0) <= \\; m_axi_awaddr(31 downto 0) <= \^s_axi_awaddr\(31 downto 0); m_axi_awburst(1 downto 0) <= \^s_axi_awburst\(1 downto 0); m_axi_awcache(3 downto 0) <= \^s_axi_awcache\(3 downto 0); m_axi_awid(0) <= \^s_axi_awid\(0); - m_axi_awlen(3 downto 0) <= \^s_axi_awlen\(3 downto 0); - m_axi_awlock(1 downto 0) <= \^s_axi_awlock\(1 downto 0); + m_axi_awlen(7 downto 0) <= \^s_axi_awlen\(7 downto 0); + m_axi_awlock(0) <= \^s_axi_awlock\(0); m_axi_awprot(2 downto 0) <= \^s_axi_awprot\(2 downto 0); m_axi_awqos(3 downto 0) <= \^s_axi_awqos\(3 downto 0); - m_axi_awregion(3) <= \\; - m_axi_awregion(2) <= \\; - m_axi_awregion(1) <= \\; - m_axi_awregion(0) <= \\; + m_axi_awregion(3 downto 0) <= \^s_axi_awregion\(3 downto 0); m_axi_awsize(2 downto 0) <= \^s_axi_awsize\(2 downto 0); m_axi_awuser(0) <= \^s_axi_awuser\(0); m_axi_awvalid <= \^s_axi_awvalid\; m_axi_bready <= \^s_axi_bready\; m_axi_wdata(63 downto 0) <= \^s_axi_wdata\(63 downto 0); - m_axi_wid(0) <= \^s_axi_wid\(0); + m_axi_wid(0) <= \\; m_axi_wlast <= \^s_axi_wlast\; m_axi_wstrb(7 downto 0) <= \^s_axi_wstrb\(7 downto 0); m_axi_wuser(0) <= \^s_axi_wuser\(0); @@ -12369,12 +12558,12 @@ GND: unisim.vcomponents.GND m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0), m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0), m_axi_arid(0) => m_axi_arid(0), - m_axi_arlen(3 downto 0) => m_axi_arlen(3 downto 0), - m_axi_arlock(1 downto 0) => m_axi_arlock(1 downto 0), + m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0), + m_axi_arlock(0) => m_axi_arlock(0), m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0), m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0), m_axi_arready => m_axi_arready, - m_axi_arregion(3 downto 0) => \NLW_gen_fifo.fifo_gen_inst_m_axi_arregion_UNCONNECTED\(3 downto 0), + m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0), m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0), m_axi_aruser(0) => m_axi_aruser(0), m_axi_arvalid => m_axi_arvalid, @@ -12382,8 +12571,8 @@ GND: unisim.vcomponents.GND m_axi_awburst(1 downto 0) => \NLW_gen_fifo.fifo_gen_inst_m_axi_awburst_UNCONNECTED\(1 downto 0), m_axi_awcache(3 downto 0) => \NLW_gen_fifo.fifo_gen_inst_m_axi_awcache_UNCONNECTED\(3 downto 0), m_axi_awid(0) => \NLW_gen_fifo.fifo_gen_inst_m_axi_awid_UNCONNECTED\(0), - m_axi_awlen(3 downto 0) => \NLW_gen_fifo.fifo_gen_inst_m_axi_awlen_UNCONNECTED\(3 downto 0), - m_axi_awlock(1 downto 0) => \NLW_gen_fifo.fifo_gen_inst_m_axi_awlock_UNCONNECTED\(1 downto 0), + m_axi_awlen(7 downto 0) => \NLW_gen_fifo.fifo_gen_inst_m_axi_awlen_UNCONNECTED\(7 downto 0), + m_axi_awlock(0) => \NLW_gen_fifo.fifo_gen_inst_m_axi_awlock_UNCONNECTED\(0), m_axi_awprot(2 downto 0) => \NLW_gen_fifo.fifo_gen_inst_m_axi_awprot_UNCONNECTED\(2 downto 0), m_axi_awqos(3 downto 0) => \NLW_gen_fifo.fifo_gen_inst_m_axi_awqos_UNCONNECTED\(3 downto 0), m_axi_awready => '0', @@ -12441,12 +12630,12 @@ GND: unisim.vcomponents.GND s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0), s_axi_arid(0) => s_axi_arid(0), - s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), - s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0), + s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0), + s_axi_arlock(0) => s_axi_arlock(0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0), s_axi_arready => s_axi_arready, - s_axi_arregion(3 downto 0) => B"0000", + s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0), s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0), s_axi_aruser(0) => s_axi_aruser(0), s_axi_arvalid => s_axi_arvalid, @@ -12454,8 +12643,8 @@ GND: unisim.vcomponents.GND s_axi_awburst(1 downto 0) => B"00", s_axi_awcache(3 downto 0) => B"0000", s_axi_awid(0) => '0', - s_axi_awlen(3 downto 0) => B"0000", - s_axi_awlock(1 downto 0) => B"00", + s_axi_awlen(7 downto 0) => B"00000000", + s_axi_awlock(0) => '0', s_axi_awprot(2 downto 0) => B"000", s_axi_awqos(3 downto 0) => B"0000", s_axi_awready => \NLW_gen_fifo.fifo_gen_inst_s_axi_awready_UNCONNECTED\, @@ -12513,12 +12702,13 @@ entity Arty_Z7_20_s00_data_fifo_0 is aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; @@ -12528,12 +12718,13 @@ entity Arty_Z7_20_s00_data_fifo_0 is s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); - m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); - m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; @@ -12562,14 +12753,13 @@ architecture STRUCTURE of Arty_Z7_20_s00_data_fifo_0 is signal NLW_inst_s_axi_bvalid_UNCONNECTED : STD_LOGIC; signal NLW_inst_s_axi_wready_UNCONNECTED : STD_LOGIC; signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); @@ -12597,7 +12787,7 @@ architecture STRUCTURE of Arty_Z7_20_s00_data_fifo_0 is attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of inst : label is 1; attribute C_AXI_PROTOCOL : integer; - attribute C_AXI_PROTOCOL of inst : label is 1; + attribute C_AXI_PROTOCOL of inst : label is 0; attribute C_AXI_READ_FIFO_DELAY : integer; attribute C_AXI_READ_FIFO_DELAY of inst : label is 1; attribute C_AXI_READ_FIFO_DEPTH : integer; @@ -12629,13 +12819,13 @@ architecture STRUCTURE of Arty_Z7_20_s00_data_fifo_0 is attribute P_READ_FIFO_DEPTH_LOG : integer; attribute P_READ_FIFO_DEPTH_LOG of inst : label is 9; attribute P_WIDTH_RACH : integer; - attribute P_WIDTH_RACH of inst : label is 60; + attribute P_WIDTH_RACH of inst : label is 63; attribute P_WIDTH_RDCH : integer; attribute P_WIDTH_RDCH of inst : label is 69; attribute P_WIDTH_WACH : integer; - attribute P_WIDTH_WACH of inst : label is 60; + attribute P_WIDTH_WACH of inst : label is 63; attribute P_WIDTH_WDCH : integer; - attribute P_WIDTH_WDCH of inst : label is 75; + attribute P_WIDTH_WDCH of inst : label is 74; attribute P_WIDTH_WRCH : integer; attribute P_WIDTH_WRCH of inst : label is 4; attribute P_WRITE_FIFO_DEPTH_LOG : integer; @@ -12650,12 +12840,12 @@ inst: entity work.Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0), m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0), m_axi_arid(0) => NLW_inst_m_axi_arid_UNCONNECTED(0), - m_axi_arlen(3 downto 0) => m_axi_arlen(3 downto 0), - m_axi_arlock(1 downto 0) => m_axi_arlock(1 downto 0), + m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0), + m_axi_arlock(0) => m_axi_arlock(0), m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0), m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0), m_axi_arready => m_axi_arready, - m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0), + m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0), m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0), m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0), m_axi_arvalid => m_axi_arvalid, @@ -12663,8 +12853,8 @@ inst: entity work.Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0), m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0), m_axi_awid(0) => NLW_inst_m_axi_awid_UNCONNECTED(0), - m_axi_awlen(3 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(3 downto 0), - m_axi_awlock(1 downto 0) => NLW_inst_m_axi_awlock_UNCONNECTED(1 downto 0), + m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0), + m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0), m_axi_awprot(2 downto 0) => NLW_inst_m_axi_awprot_UNCONNECTED(2 downto 0), m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0), m_axi_awready => '0', @@ -12695,12 +12885,12 @@ inst: entity work.Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0), s_axi_arid(0) => '0', - s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), - s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0), + s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0), + s_axi_arlock(0) => s_axi_arlock(0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0), s_axi_arready => s_axi_arready, - s_axi_arregion(3 downto 0) => B"0000", + s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0), s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0), s_axi_aruser(0) => '0', s_axi_arvalid => s_axi_arvalid, @@ -12708,8 +12898,8 @@ inst: entity work.Arty_Z7_20_s00_data_fifo_0_axi_data_fifo_v2_1_10_axi_data_fifo s_axi_awburst(1 downto 0) => B"01", s_axi_awcache(3 downto 0) => B"0000", s_axi_awid(0) => '0', - s_axi_awlen(3 downto 0) => B"0000", - s_axi_awlock(1 downto 0) => B"00", + s_axi_awlen(7 downto 0) => B"00000000", + s_axi_awlock(0) => '0', s_axi_awprot(2 downto 0) => B"000", s_axi_awqos(3 downto 0) => B"0000", s_axi_awready => NLW_inst_s_axi_awready_UNCONNECTED, diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0_stub.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0_stub.v index c11e35a..4c8f7be 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0_stub.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0_stub.v @@ -1,7 +1,7 @@ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -// Date : Fri Feb 24 16:02:52 2017 +// Date : Sat Mar 04 18:59:58 2017 // Host : WK73 running 64-bit Service Pack 1 (build 7601) // Command : write_verilog -force -mode synth_stub -rename_top Arty_Z7_20_s00_data_fifo_0 -prefix // Arty_Z7_20_s00_data_fifo_0_ Arty_Z7_20_s00_data_fifo_0_stub.v @@ -15,21 +15,22 @@ // Please paste the declaration into a Verilog source file or add the file as an additional source. (* X_CORE_INFO = "axi_data_fifo_v2_1_10_axi_data_fifo,Vivado 2016.4" *) module Arty_Z7_20_s00_data_fifo_0(aclk, aresetn, s_axi_araddr, s_axi_arlen, - s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arqos, - s_axi_arvalid, s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, - s_axi_rready, m_axi_araddr, m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, - m_axi_arcache, m_axi_arprot, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rdata, - m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready) -/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[63:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_araddr[31:0],m_axi_arlen[3:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[1:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[63:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready" */; + s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arregion, + s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rlast, + s_axi_rvalid, s_axi_rready, m_axi_araddr, m_axi_arlen, m_axi_arsize, m_axi_arburst, + m_axi_arlock, m_axi_arcache, m_axi_arprot, m_axi_arregion, m_axi_arqos, m_axi_arvalid, + m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready) +/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[63:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_araddr[31:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[0:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arregion[3:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[63:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready" */; input aclk; input aresetn; input [31:0]s_axi_araddr; - input [3:0]s_axi_arlen; + input [7:0]s_axi_arlen; input [2:0]s_axi_arsize; input [1:0]s_axi_arburst; - input [1:0]s_axi_arlock; + input [0:0]s_axi_arlock; input [3:0]s_axi_arcache; input [2:0]s_axi_arprot; + input [3:0]s_axi_arregion; input [3:0]s_axi_arqos; input s_axi_arvalid; output s_axi_arready; @@ -39,12 +40,13 @@ module Arty_Z7_20_s00_data_fifo_0(aclk, aresetn, s_axi_araddr, s_axi_arlen, output s_axi_rvalid; input s_axi_rready; output [31:0]m_axi_araddr; - output [3:0]m_axi_arlen; + output [7:0]m_axi_arlen; output [2:0]m_axi_arsize; output [1:0]m_axi_arburst; - output [1:0]m_axi_arlock; + output [0:0]m_axi_arlock; output [3:0]m_axi_arcache; output [2:0]m_axi_arprot; + output [3:0]m_axi_arregion; output [3:0]m_axi_arqos; output m_axi_arvalid; input m_axi_arready; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0_stub.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0_stub.vhdl index 117feb8..340441c 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0_stub.vhdl +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/Arty_Z7_20_s00_data_fifo_0_stub.vhdl @@ -1,7 +1,7 @@ -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 --- Date : Fri Feb 24 16:02:52 2017 +-- Date : Sat Mar 04 18:59:58 2017 -- Host : WK73 running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode synth_stub -rename_top Arty_Z7_20_s00_data_fifo_0 -prefix -- Arty_Z7_20_s00_data_fifo_0_ Arty_Z7_20_s00_data_fifo_0_stub.vhdl @@ -17,12 +17,13 @@ entity Arty_Z7_20_s00_data_fifo_0 is aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); - s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; @@ -32,12 +33,13 @@ entity Arty_Z7_20_s00_data_fifo_0 is s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); - m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); - m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; @@ -54,7 +56,7 @@ architecture stub of Arty_Z7_20_s00_data_fifo_0 is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[63:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_araddr[31:0],m_axi_arlen[3:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[1:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[63:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready"; +attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[63:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_araddr[31:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[0:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arregion[3:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[63:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "axi_data_fifo_v2_1_10_axi_data_fifo,Vivado 2016.4"; begin diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/sim/Arty_Z7_20_s00_data_fifo_0.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/sim/Arty_Z7_20_s00_data_fifo_0.v index d23c4ab..8cd599d 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/sim/Arty_Z7_20_s00_data_fifo_0.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/sim/Arty_Z7_20_s00_data_fifo_0.v @@ -63,6 +63,7 @@ module Arty_Z7_20_s00_data_fifo_0 ( s_axi_arlock, s_axi_arcache, s_axi_arprot, + s_axi_arregion, s_axi_arqos, s_axi_arvalid, s_axi_arready, @@ -78,6 +79,7 @@ module Arty_Z7_20_s00_data_fifo_0 ( m_axi_arlock, m_axi_arcache, m_axi_arprot, + m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, @@ -95,17 +97,19 @@ input wire aresetn; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input wire [31 : 0] s_axi_araddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) -input wire [3 : 0] s_axi_arlen; +input wire [7 : 0] s_axi_arlen; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input wire [2 : 0] s_axi_arsize; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input wire [1 : 0] s_axi_arburst; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) -input wire [1 : 0] s_axi_arlock; +input wire [0 : 0] s_axi_arlock; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input wire [3 : 0] s_axi_arcache; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input wire [2 : 0] s_axi_arprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *) +input wire [3 : 0] s_axi_arregion; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) input wire [3 : 0] s_axi_arqos; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) @@ -125,17 +129,19 @@ input wire s_axi_rready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output wire [31 : 0] m_axi_araddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *) -output wire [3 : 0] m_axi_arlen; +output wire [7 : 0] m_axi_arlen; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *) output wire [2 : 0] m_axi_arsize; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *) output wire [1 : 0] m_axi_arburst; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *) -output wire [1 : 0] m_axi_arlock; +output wire [0 : 0] m_axi_arlock; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *) output wire [3 : 0] m_axi_arcache; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output wire [2 : 0] m_axi_arprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *) +output wire [3 : 0] m_axi_arregion; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *) output wire [3 : 0] m_axi_arqos; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) @@ -155,7 +161,7 @@ output wire m_axi_rready; axi_data_fifo_v2_1_10_axi_data_fifo #( .C_FAMILY("zynq"), - .C_AXI_PROTOCOL(1), + .C_AXI_PROTOCOL(0), .C_AXI_ID_WIDTH(1), .C_AXI_ADDR_WIDTH(32), .C_AXI_DATA_WIDTH(64), @@ -176,10 +182,10 @@ output wire m_axi_rready; .aresetn(aresetn), .s_axi_awid(1'H0), .s_axi_awaddr(32'H00000000), - .s_axi_awlen(4'H0), + .s_axi_awlen(8'H00), .s_axi_awsize(3'H0), .s_axi_awburst(2'H1), - .s_axi_awlock(2'H0), + .s_axi_awlock(1'H0), .s_axi_awcache(4'H0), .s_axi_awprot(3'H0), .s_axi_awregion(4'H0), @@ -207,7 +213,7 @@ output wire m_axi_rready; .s_axi_arlock(s_axi_arlock), .s_axi_arcache(s_axi_arcache), .s_axi_arprot(s_axi_arprot), - .s_axi_arregion(4'H0), + .s_axi_arregion(s_axi_arregion), .s_axi_arqos(s_axi_arqos), .s_axi_aruser(1'H0), .s_axi_arvalid(s_axi_arvalid), @@ -252,7 +258,7 @@ output wire m_axi_rready; .m_axi_arlock(m_axi_arlock), .m_axi_arcache(m_axi_arcache), .m_axi_arprot(m_axi_arprot), - .m_axi_arregion(), + .m_axi_arregion(m_axi_arregion), .m_axi_arqos(m_axi_arqos), .m_axi_aruser(), .m_axi_arvalid(m_axi_arvalid), diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/synth/Arty_Z7_20_s00_data_fifo_0.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/synth/Arty_Z7_20_s00_data_fifo_0.v index 1b4f394..030db57 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/synth/Arty_Z7_20_s00_data_fifo_0.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_data_fifo_0/synth/Arty_Z7_20_s00_data_fifo_0.v @@ -52,7 +52,7 @@ (* X_CORE_INFO = "axi_data_fifo_v2_1_10_axi_data_fifo,Vivado 2016.4" *) (* CHECK_LICENSE_TYPE = "Arty_Z7_20_s00_data_fifo_0,axi_data_fifo_v2_1_10_axi_data_fifo,{}" *) -(* CORE_GENERATION_INFO = "Arty_Z7_20_s00_data_fifo_0,axi_data_fifo_v2_1_10_axi_data_fifo,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_data_fifo,x_ipVersion=2.1,x_ipCoreRevision=10,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXI_PROTOCOL=1,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_WRITE_FIFO_DEPTH=0,C_AXI_WRITE_FIFO_TYPE=lut,C_A\ +(* CORE_GENERATION_INFO = "Arty_Z7_20_s00_data_fifo_0,axi_data_fifo_v2_1_10_axi_data_fifo,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_data_fifo,x_ipVersion=2.1,x_ipCoreRevision=10,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_WRITE_FIFO_DEPTH=0,C_AXI_WRITE_FIFO_TYPE=lut,C_A\ XI_WRITE_FIFO_DELAY=0,C_AXI_READ_FIFO_DEPTH=512,C_AXI_READ_FIFO_TYPE=bram,C_AXI_READ_FIFO_DELAY=1}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) module Arty_Z7_20_s00_data_fifo_0 ( @@ -65,6 +65,7 @@ module Arty_Z7_20_s00_data_fifo_0 ( s_axi_arlock, s_axi_arcache, s_axi_arprot, + s_axi_arregion, s_axi_arqos, s_axi_arvalid, s_axi_arready, @@ -80,6 +81,7 @@ module Arty_Z7_20_s00_data_fifo_0 ( m_axi_arlock, m_axi_arcache, m_axi_arprot, + m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, @@ -97,17 +99,19 @@ input wire aresetn; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input wire [31 : 0] s_axi_araddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) -input wire [3 : 0] s_axi_arlen; +input wire [7 : 0] s_axi_arlen; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input wire [2 : 0] s_axi_arsize; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input wire [1 : 0] s_axi_arburst; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) -input wire [1 : 0] s_axi_arlock; +input wire [0 : 0] s_axi_arlock; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input wire [3 : 0] s_axi_arcache; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input wire [2 : 0] s_axi_arprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *) +input wire [3 : 0] s_axi_arregion; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) input wire [3 : 0] s_axi_arqos; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) @@ -127,17 +131,19 @@ input wire s_axi_rready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output wire [31 : 0] m_axi_araddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *) -output wire [3 : 0] m_axi_arlen; +output wire [7 : 0] m_axi_arlen; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *) output wire [2 : 0] m_axi_arsize; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *) output wire [1 : 0] m_axi_arburst; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *) -output wire [1 : 0] m_axi_arlock; +output wire [0 : 0] m_axi_arlock; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *) output wire [3 : 0] m_axi_arcache; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output wire [2 : 0] m_axi_arprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *) +output wire [3 : 0] m_axi_arregion; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *) output wire [3 : 0] m_axi_arqos; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) @@ -157,7 +163,7 @@ output wire m_axi_rready; axi_data_fifo_v2_1_10_axi_data_fifo #( .C_FAMILY("zynq"), - .C_AXI_PROTOCOL(1), + .C_AXI_PROTOCOL(0), .C_AXI_ID_WIDTH(1), .C_AXI_ADDR_WIDTH(32), .C_AXI_DATA_WIDTH(64), @@ -178,10 +184,10 @@ output wire m_axi_rready; .aresetn(aresetn), .s_axi_awid(1'H0), .s_axi_awaddr(32'H00000000), - .s_axi_awlen(4'H0), + .s_axi_awlen(8'H00), .s_axi_awsize(3'H0), .s_axi_awburst(2'H1), - .s_axi_awlock(2'H0), + .s_axi_awlock(1'H0), .s_axi_awcache(4'H0), .s_axi_awprot(3'H0), .s_axi_awregion(4'H0), @@ -209,7 +215,7 @@ output wire m_axi_rready; .s_axi_arlock(s_axi_arlock), .s_axi_arcache(s_axi_arcache), .s_axi_arprot(s_axi_arprot), - .s_axi_arregion(4'H0), + .s_axi_arregion(s_axi_arregion), .s_axi_arqos(s_axi_arqos), .s_axi_aruser(1'H0), .s_axi_arvalid(s_axi_arvalid), @@ -254,7 +260,7 @@ output wire m_axi_rready; .m_axi_arlock(m_axi_arlock), .m_axi_arcache(m_axi_arcache), .m_axi_arprot(m_axi_arprot), - .m_axi_arregion(), + .m_axi_arregion(m_axi_arregion), .m_axi_arqos(m_axi_arqos), .m_axi_aruser(), .m_axi_arvalid(m_axi_arvalid), diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_regslice_0/Arty_Z7_20_s00_regslice_0.dcp b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_regslice_0/Arty_Z7_20_s00_regslice_0.dcp index 45e6fbd..dad4d1f 100644 Binary files a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_regslice_0/Arty_Z7_20_s00_regslice_0.dcp and b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_regslice_0/Arty_Z7_20_s00_regslice_0.dcp differ diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_regslice_0/Arty_Z7_20_s00_regslice_0.xci b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_regslice_0/Arty_Z7_20_s00_regslice_0.xci index b37c465..ceed405 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_regslice_0/Arty_Z7_20_s00_regslice_0.xci +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_regslice_0/Arty_Z7_20_s00_regslice_0.xci @@ -12,7 +12,7 @@ S_AXI:M_AXI ARESETN Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 - 142857132 + 118181816 0.000 32 0 @@ -20,7 +20,7 @@ 0 Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 64 - 142857132 + 118181816 0 0 0 @@ -31,7 +31,7 @@ 1 0 0 - 16 + 32 2 1 8 @@ -52,7 +52,7 @@ 0 Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 64 - 142857132 + 118181816 0 0 0 @@ -63,7 +63,7 @@ 1 0 0 - 16 + 32 2 1 8 @@ -152,7 +152,7 @@ - + @@ -178,7 +178,7 @@ - + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_regslice_0/Arty_Z7_20_s00_regslice_0.xml b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_regslice_0/Arty_Z7_20_s00_regslice_0.xml index f35cb6d..49d15f5 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_regslice_0/Arty_Z7_20_s00_regslice_0.xml +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_regslice_0/Arty_Z7_20_s00_regslice_0.xml @@ -384,7 +384,7 @@ FREQ_HZ - 142857132 + 118181816 ID_WIDTH @@ -468,7 +468,7 @@ MAX_BURST_LENGTH - 16 + 32 PHASE @@ -875,7 +875,7 @@ FREQ_HZ - 142857132 + 118181816 ID_WIDTH @@ -959,7 +959,7 @@ MAX_BURST_LENGTH - 16 + 32 PHASE @@ -1008,7 +1008,7 @@ FREQ_HZ aclk frequency aclk frequency - 142857132 + 118181816 PHASE @@ -1076,7 +1076,7 @@ boundaryCRC - 04c2375c + 54441c18 boundaryCRCversion @@ -1102,11 +1102,11 @@ GENtimestamp - Mon Feb 27 18:05:26 UTC 2017 + Mon Mar 06 19:44:19 UTC 2017 boundaryCRC - 04c2375c + 54441c18 boundaryCRCversion @@ -1133,11 +1133,11 @@ GENtimestamp - Mon Feb 27 18:05:26 UTC 2017 + Mon Mar 06 19:44:19 UTC 2017 boundaryCRC - 04c2375c + 54441c18 boundaryCRCversion @@ -1171,7 +1171,7 @@ boundaryCRC - 04c2375c + 54441c18 boundaryCRCversion @@ -1198,11 +1198,11 @@ GENtimestamp - Mon Feb 27 18:05:26 UTC 2017 + Mon Mar 06 19:44:19 UTC 2017 boundaryCRC - 04c2375c + 54441c18 boundaryCRCversion @@ -1228,11 +1228,11 @@ GENtimestamp - Mon Feb 27 18:05:32 UTC 2017 + Mon Mar 06 19:44:24 UTC 2017 boundaryCRC - 04c2375c + 54441c18 boundaryCRCversion @@ -3860,7 +3860,7 @@ - + @@ -3886,7 +3886,7 @@ - + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_regslice_0/Arty_Z7_20_s00_regslice_0_ooc.xdc b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_regslice_0/Arty_Z7_20_s00_regslice_0_ooc.xdc index ab4e818..6259de8 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_regslice_0/Arty_Z7_20_s00_regslice_0_ooc.xdc +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_s00_regslice_0/Arty_Z7_20_s00_regslice_0_ooc.xdc @@ -52,6 +52,6 @@ # ######################################################### -create_clock -period 7 -name aclk [get_ports aclk] +create_clock -period 8.462 -name aclk [get_ports aclk] diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0.dcp b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0.dcp index 612ffc1..01add76 100644 Binary files a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0.dcp and b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0.dcp differ diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0.xci b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0.xci index f49b646..dfc77c8 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0.xci +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0.xci @@ -12,10 +12,10 @@ ACTIVE_LOW Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 - 142857132 + 118181816 0.000 Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 - 142857132 + 118181816 0 1 1 @@ -64,6 +64,7 @@ TRUE TRUE + f269da949e3ce7b2 IP_Integrator 5 TRUE diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0.xml b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0.xml index 443252c..ee265cb 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0.xml +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0.xml @@ -89,7 +89,7 @@ FREQ_HZ - 142857132 + 118181816 PHASE @@ -234,7 +234,7 @@ FREQ_HZ vid-in clock frequency vid-in clock frequency - 142857132 + 118181816 PHASE @@ -415,6 +415,36 @@ + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Mon Mar 06 02:56:07 UTC 2017 + + + boundaryCRC + 120655ef + + + boundaryCRCversion + 1 + + + customizationCRC + 7e572638 + + + customizationCRCversion + 6 + + + xilinx_verilogsynthesis Verilog Synthesis @@ -436,7 +466,7 @@ boundaryCRC - 232bb251 + 120655ef boundaryCRCversion @@ -462,11 +492,11 @@ GENtimestamp - Fri Feb 24 23:58:24 UTC 2017 + Mon Mar 06 02:55:58 UTC 2017 boundaryCRC - 232bb251 + 120655ef boundaryCRCversion @@ -493,11 +523,11 @@ GENtimestamp - Fri Feb 24 23:58:24 UTC 2017 + Mon Mar 06 02:55:58 UTC 2017 boundaryCRC - 232bb251 + 120655ef boundaryCRCversion @@ -540,7 +570,7 @@ boundaryCRC - 232bb251 + 120655ef boundaryCRCversion @@ -567,11 +597,11 @@ GENtimestamp - Fri Feb 24 23:58:24 UTC 2017 + Mon Mar 06 02:55:58 UTC 2017 boundaryCRC - 232bb251 + 120655ef boundaryCRCversion @@ -587,36 +617,6 @@ - - xilinx_externalfiles - External Files - :vivado.xilinx.com:external.files - - xilinx_externalfiles_view_fileset - - - - GENtimestamp - Sat Feb 25 00:05:07 UTC 2017 - - - boundaryCRC - 232bb251 - - - boundaryCRCversion - 1 - - - customizationCRC - 7e572638 - - - customizationCRCversion - 6 - - - @@ -1174,6 +1174,42 @@ + + xilinx_externalfiles_view_fileset + + Arty_Z7_20_v_axi4s_vid_out_0_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + Arty_Z7_20_v_axi4s_vid_out_0_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Arty_Z7_20_v_axi4s_vid_out_0_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Arty_Z7_20_v_axi4s_vid_out_0_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Arty_Z7_20_v_axi4s_vid_out_0_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + xilinx_verilogsynthesis_xilinx_com_ip_blk_mem_gen_8_3__ref_view_fileset @@ -1334,42 +1370,6 @@ xil_defaultlib - - xilinx_externalfiles_view_fileset - - Arty_Z7_20_v_axi4s_vid_out_0_0.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - Arty_Z7_20_v_axi4s_vid_out_0_0_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - Arty_Z7_20_v_axi4s_vid_out_0_0_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - Arty_Z7_20_v_axi4s_vid_out_0_0_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - Arty_Z7_20_v_axi4s_vid_out_0_0_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - Video bridge converting AXI4-Stream to native video. diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0_ooc.xdc b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0_ooc.xdc index af51f54..a0422ad 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0_ooc.xdc +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0_ooc.xdc @@ -54,6 +54,6 @@ create_clock -period 10 -name vid_io_out_clk [get_ports vid_io_out_clk] -create_clock -period 7 -name aclk [get_ports aclk] +create_clock -period 8.462 -name aclk [get_ports aclk] diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0_sim_netlist.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0_sim_netlist.v index ba7acd0..2243af2 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0_sim_netlist.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -// Date : Fri Feb 24 16:05:07 2017 +// Date : Fri Feb 24 16:05:05 2017 // Host : WK73 running 64-bit Service Pack 1 (build 7601) -// Command : write_verilog -force -mode funcsim -// c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0_sim_netlist.v +// Command : write_verilog -force -mode funcsim -rename_top Arty_Z7_20_v_axi4s_vid_out_0_0 -prefix +// Arty_Z7_20_v_axi4s_vid_out_0_0_ Arty_Z7_20_v_axi4s_vid_out_0_0_sim_netlist.v // Design : Arty_Z7_20_v_axi4s_vid_out_0_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -157,7 +157,7 @@ endmodule (* C_HAS_ASYNC_CLK = "1" *) (* C_HYSTERESIS_LEVEL = "12" *) (* C_NATIVE_COMPONENT_WIDTH = "8" *) (* C_NATIVE_DATA_WIDTH = "24" *) (* C_PIXELS_PER_CLOCK = "1" *) (* C_SYNC_LOCK_THRESHOLD = "4" *) (* C_S_AXIS_COMPONENT_WIDTH = "8" *) (* C_S_AXIS_TDATA_WIDTH = "24" *) (* C_VTG_MASTER_SLAVE = "1" *) -(* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "v_axi4s_vid_out_v4_0_5" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) module Arty_Z7_20_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_5 (aclk, aclken, @@ -337,7 +337,6 @@ module Arty_Z7_20_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_5 .vtg_vsync(vtg_vsync)); endmodule -(* ORIG_REF_NAME = "v_axi4s_vid_out_v4_0_5_coupler" *) module Arty_Z7_20_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_5_coupler (dout, overflow, @@ -995,7 +994,6 @@ module Arty_Z7_20_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_5_coupler .O(s_axis_video_tready)); endmodule -(* ORIG_REF_NAME = "v_axi4s_vid_out_v4_0_5_formatter" *) module Arty_Z7_20_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_5_formatter (vid_active_video, vid_vsync, @@ -1359,7 +1357,6 @@ module Arty_Z7_20_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_5_formatter .R(1'b0)); endmodule -(* ORIG_REF_NAME = "v_axi4s_vid_out_v4_0_5_sync" *) module Arty_Z7_20_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_5_sync (fifo_eol_dly, fifo_sof_dly, @@ -4349,7 +4346,6 @@ module Arty_Z7_20_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_5_sync .R(vid_io_out_reset)); endmodule -(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *) module Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_generic_cstr (dout, wr_clk, @@ -4418,7 +4414,6 @@ module Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_generic_cstr .wr_clk(wr_clk)); endmodule -(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) module Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_prim_width (dout, wr_clk, @@ -4559,7 +4554,6 @@ module Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_prim_width__parameterized1 .wr_clk(wr_clk)); endmodule -(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) module Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_prim_wrapper (dout, wr_clk, @@ -5330,7 +5324,6 @@ module Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_prim_wrapper__parameterized1 .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); endmodule -(* ORIG_REF_NAME = "blk_mem_gen_top" *) module Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_top (dout, wr_clk, @@ -5377,7 +5370,6 @@ module Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_top .wr_clk(wr_clk)); endmodule -(* ORIG_REF_NAME = "blk_mem_gen_v8_3_5" *) module Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_v8_3_5 (dout, wr_clk, @@ -5424,7 +5416,6 @@ module Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_v8_3_5 .wr_clk(wr_clk)); endmodule -(* ORIG_REF_NAME = "blk_mem_gen_v8_3_5_synth" *) module Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_v8_3_5_synth (dout, wr_clk, @@ -5471,7 +5462,6 @@ module Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_v8_3_5_synth .wr_clk(wr_clk)); endmodule -(* ORIG_REF_NAME = "clk_x_pntrs" *) module Arty_Z7_20_v_axi4s_vid_out_0_0_clk_x_pntrs (S, WR_PNTR_RD, @@ -6010,7 +6000,6 @@ module Arty_Z7_20_v_axi4s_vid_out_0_0_clk_x_pntrs .O(S[0])); endmodule -(* ORIG_REF_NAME = "compare" *) module Arty_Z7_20_v_axi4s_vid_out_0_0_compare (comp1, Q, @@ -6378,7 +6367,6 @@ module Arty_Z7_20_v_axi4s_vid_out_0_0_compare_5 .O(v1_reg[5])); endmodule -(* ORIG_REF_NAME = "fifo_generator_ramfifo" *) module Arty_Z7_20_v_axi4s_vid_out_0_0_fifo_generator_ramfifo (wr_rst_busy, dout, @@ -6516,7 +6504,6 @@ module Arty_Z7_20_v_axi4s_vid_out_0_0_fifo_generator_ramfifo .wr_rst_busy(wr_rst_busy)); endmodule -(* ORIG_REF_NAME = "fifo_generator_top" *) module Arty_Z7_20_v_axi4s_vid_out_0_0_fifo_generator_top (wr_rst_busy, dout, @@ -6642,7 +6629,7 @@ endmodule (* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "12" *) (* C_WR_PNTR_WIDTH_AXIS = "12" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "12" *) (* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "12" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *) -(* C_WR_RESPONSE_LATENCY = "1" *) (* ORIG_REF_NAME = "fifo_generator_v13_1_3" *) +(* C_WR_RESPONSE_LATENCY = "1" *) module Arty_Z7_20_v_axi4s_vid_out_0_0_fifo_generator_v13_1_3 (backup, backup_marker, @@ -7679,7 +7666,6 @@ module Arty_Z7_20_v_axi4s_vid_out_0_0_fifo_generator_v13_1_3 .wr_rst_busy(wr_rst_busy)); endmodule -(* ORIG_REF_NAME = "fifo_generator_v13_1_3_synth" *) module Arty_Z7_20_v_axi4s_vid_out_0_0_fifo_generator_v13_1_3_synth (wr_rst_busy, dout, @@ -7738,7 +7724,6 @@ module Arty_Z7_20_v_axi4s_vid_out_0_0_fifo_generator_v13_1_3_synth .wr_rst_busy(wr_rst_busy)); endmodule -(* ORIG_REF_NAME = "memory" *) module Arty_Z7_20_v_axi4s_vid_out_0_0_memory (dout, wr_clk, @@ -7785,7 +7770,6 @@ module Arty_Z7_20_v_axi4s_vid_out_0_0_memory .wr_clk(wr_clk)); endmodule -(* ORIG_REF_NAME = "rd_bin_cntr" *) module Arty_Z7_20_v_axi4s_vid_out_0_0_rd_bin_cntr (D, Q, @@ -8194,7 +8178,6 @@ module Arty_Z7_20_v_axi4s_vid_out_0_0_rd_bin_cntr .O(I4[9])); endmodule -(* ORIG_REF_NAME = "rd_dc_fwft_ext_as" *) module Arty_Z7_20_v_axi4s_vid_out_0_0_rd_dc_fwft_ext_as (rd_data_count, WR_PNTR_RD, @@ -8553,7 +8536,6 @@ module Arty_Z7_20_v_axi4s_vid_out_0_0_rd_dc_fwft_ext_as .O(plusOp_carry_i_4_n_0)); endmodule -(* ORIG_REF_NAME = "rd_fwft" *) module Arty_Z7_20_v_axi4s_vid_out_0_0_rd_fwft (out, empty, @@ -8762,7 +8744,6 @@ module Arty_Z7_20_v_axi4s_vid_out_0_0_rd_fwft .O(p_1_out)); endmodule -(* ORIG_REF_NAME = "rd_handshaking_flags" *) module Arty_Z7_20_v_axi4s_vid_out_0_0_rd_handshaking_flags (underflow, p_1_out, @@ -8785,7 +8766,6 @@ module Arty_Z7_20_v_axi4s_vid_out_0_0_rd_handshaking_flags .R(1'b0)); endmodule -(* ORIG_REF_NAME = "rd_logic" *) module Arty_Z7_20_v_axi4s_vid_out_0_0_rd_logic (empty, underflow, @@ -8882,7 +8862,6 @@ module Arty_Z7_20_v_axi4s_vid_out_0_0_rd_logic .rd_clk(rd_clk)); endmodule -(* ORIG_REF_NAME = "rd_status_flags_as" *) module Arty_Z7_20_v_axi4s_vid_out_0_0_rd_status_flags_as (out, rd_clk, @@ -8957,7 +8936,6 @@ module Arty_Z7_20_v_axi4s_vid_out_0_0_rd_status_flags_as .Q(ram_empty_i)); endmodule -(* ORIG_REF_NAME = "reset_blk_ramfifo" *) module Arty_Z7_20_v_axi4s_vid_out_0_0_reset_blk_ramfifo (out, \gc0.count_reg[0] , @@ -9180,7 +9158,6 @@ module Arty_Z7_20_v_axi4s_vid_out_0_0_reset_blk_ramfifo .Q(wr_rst_reg[2])); endmodule -(* ORIG_REF_NAME = "synchronizer_ff" *) module Arty_Z7_20_v_axi4s_vid_out_0_0_synchronizer_ff (out, \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg , @@ -10158,7 +10135,6 @@ module Arty_Z7_20_v_axi4s_vid_out_0_0_synchronizer_ff__parameterized3 .O(\gnxpm_cdc.rd_pntr_bin_reg[10] [9])); endmodule -(* ORIG_REF_NAME = "wr_bin_cntr" *) module Arty_Z7_20_v_axi4s_vid_out_0_0_wr_bin_cntr (D, Q, @@ -10666,7 +10642,6 @@ module Arty_Z7_20_v_axi4s_vid_out_0_0_wr_bin_cntr .O(bin2gray[9])); endmodule -(* ORIG_REF_NAME = "wr_handshaking_flags" *) module Arty_Z7_20_v_axi4s_vid_out_0_0_wr_handshaking_flags (overflow, wr_clk, @@ -10703,7 +10678,6 @@ module Arty_Z7_20_v_axi4s_vid_out_0_0_wr_handshaking_flags .R(1'b0)); endmodule -(* ORIG_REF_NAME = "wr_logic" *) module Arty_Z7_20_v_axi4s_vid_out_0_0_wr_logic (full, overflow, @@ -10770,7 +10744,6 @@ module Arty_Z7_20_v_axi4s_vid_out_0_0_wr_logic .wr_clk(wr_clk)); endmodule -(* ORIG_REF_NAME = "wr_status_flags_as" *) module Arty_Z7_20_v_axi4s_vid_out_0_0_wr_status_flags_as (full, out, diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0_sim_netlist.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0_sim_netlist.vhdl index 918f647..b7749ee 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0_sim_netlist.vhdl +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 --- Date : Fri Feb 24 16:05:07 2017 +-- Date : Fri Feb 24 16:05:06 2017 -- Host : WK73 running 64-bit Service Pack 1 (build 7601) --- Command : write_vhdl -force -mode funcsim --- c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0_sim_netlist.vhdl +-- Command : write_vhdl -force -mode funcsim -rename_top Arty_Z7_20_v_axi4s_vid_out_0_0 -prefix +-- Arty_Z7_20_v_axi4s_vid_out_0_0_ Arty_Z7_20_v_axi4s_vid_out_0_0_sim_netlist.vhdl -- Design : Arty_Z7_20_v_axi4s_vid_out_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. @@ -38,8 +38,6 @@ entity Arty_Z7_20_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_5_formatter is E : in STD_LOGIC_VECTOR ( 0 to 0 ); D : in STD_LOGIC_VECTOR ( 23 downto 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_5_formatter : entity is "v_axi4s_vid_out_v4_0_5_formatter"; end Arty_Z7_20_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_5_formatter; architecture STRUCTURE of Arty_Z7_20_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_5_formatter is @@ -476,8 +474,6 @@ entity Arty_Z7_20_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_5_sync is \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); vtg_field_id : in STD_LOGIC ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_5_sync : entity is "v_axi4s_vid_out_v4_0_5_sync"; end Arty_Z7_20_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_5_sync; architecture STRUCTURE of Arty_Z7_20_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_5_sync is @@ -4587,8 +4583,6 @@ entity Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_prim_wrapper is \gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); din : in STD_LOGIC_VECTOR ( 8 downto 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper"; end Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_prim_wrapper; architecture STRUCTURE of Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_prim_wrapper is @@ -5363,8 +5357,6 @@ entity Arty_Z7_20_v_axi4s_vid_out_0_0_compare is Q : in STD_LOGIC_VECTOR ( 11 downto 0 ); RD_PNTR_WR : in STD_LOGIC_VECTOR ( 11 downto 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_v_axi4s_vid_out_0_0_compare : entity is "compare"; end Arty_Z7_20_v_axi4s_vid_out_0_0_compare; architecture STRUCTURE of Arty_Z7_20_v_axi4s_vid_out_0_0_compare is @@ -5866,8 +5858,6 @@ entity Arty_Z7_20_v_axi4s_vid_out_0_0_rd_bin_cntr is rd_clk : in STD_LOGIC; \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_v_axi4s_vid_out_0_0_rd_bin_cntr : entity is "rd_bin_cntr"; end Arty_Z7_20_v_axi4s_vid_out_0_0_rd_bin_cntr; architecture STRUCTURE of Arty_Z7_20_v_axi4s_vid_out_0_0_rd_bin_cntr is @@ -6453,8 +6443,6 @@ entity Arty_Z7_20_v_axi4s_vid_out_0_0_rd_dc_fwft_ext_as is \gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \gpregsm1.user_valid_reg\ : in STD_LOGIC ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_v_axi4s_vid_out_0_0_rd_dc_fwft_ext_as : entity is "rd_dc_fwft_ext_as"; end Arty_Z7_20_v_axi4s_vid_out_0_0_rd_dc_fwft_ext_as; architecture STRUCTURE of Arty_Z7_20_v_axi4s_vid_out_0_0_rd_dc_fwft_ext_as is @@ -6953,8 +6941,6 @@ entity Arty_Z7_20_v_axi4s_vid_out_0_0_rd_fwft is ram_empty_fb_i_reg : in STD_LOGIC; rd_en : in STD_LOGIC ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_v_axi4s_vid_out_0_0_rd_fwft : entity is "rd_fwft"; end Arty_Z7_20_v_axi4s_vid_out_0_0_rd_fwft; architecture STRUCTURE of Arty_Z7_20_v_axi4s_vid_out_0_0_rd_fwft is @@ -7204,8 +7190,6 @@ entity Arty_Z7_20_v_axi4s_vid_out_0_0_rd_handshaking_flags is p_1_out : in STD_LOGIC; rd_clk : in STD_LOGIC ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_v_axi4s_vid_out_0_0_rd_handshaking_flags : entity is "rd_handshaking_flags"; end Arty_Z7_20_v_axi4s_vid_out_0_0_rd_handshaking_flags; architecture STRUCTURE of Arty_Z7_20_v_axi4s_vid_out_0_0_rd_handshaking_flags is @@ -7233,8 +7217,6 @@ entity Arty_Z7_20_v_axi4s_vid_out_0_0_synchronizer_ff is in0 : in STD_LOGIC_VECTOR ( 0 to 0 ); rd_clk : in STD_LOGIC ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_v_axi4s_vid_out_0_0_synchronizer_ff : entity is "synchronizer_ff"; end Arty_Z7_20_v_axi4s_vid_out_0_0_synchronizer_ff; architecture STRUCTURE of Arty_Z7_20_v_axi4s_vid_out_0_0_synchronizer_ff is @@ -8514,8 +8496,6 @@ entity Arty_Z7_20_v_axi4s_vid_out_0_0_wr_bin_cntr is wr_clk : in STD_LOGIC; \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_v_axi4s_vid_out_0_0_wr_bin_cntr : entity is "wr_bin_cntr"; end Arty_Z7_20_v_axi4s_vid_out_0_0_wr_bin_cntr; architecture STRUCTURE of Arty_Z7_20_v_axi4s_vid_out_0_0_wr_bin_cntr is @@ -9231,8 +9211,6 @@ entity Arty_Z7_20_v_axi4s_vid_out_0_0_wr_handshaking_flags is \out\ : in STD_LOGIC; wr_rst_busy : in STD_LOGIC ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_v_axi4s_vid_out_0_0_wr_handshaking_flags : entity is "wr_handshaking_flags"; end Arty_Z7_20_v_axi4s_vid_out_0_0_wr_handshaking_flags; architecture STRUCTURE of Arty_Z7_20_v_axi4s_vid_out_0_0_wr_handshaking_flags is @@ -9277,8 +9255,6 @@ entity Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_prim_width is \gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); din : in STD_LOGIC_VECTOR ( 8 downto 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; end Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_prim_width; architecture STRUCTURE of Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_prim_width is @@ -9390,8 +9366,6 @@ entity Arty_Z7_20_v_axi4s_vid_out_0_0_clk_x_pntrs is \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); I4 : in STD_LOGIC_VECTOR ( 10 downto 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_v_axi4s_vid_out_0_0_clk_x_pntrs : entity is "clk_x_pntrs"; end Arty_Z7_20_v_axi4s_vid_out_0_0_clk_x_pntrs; architecture STRUCTURE of Arty_Z7_20_v_axi4s_vid_out_0_0_clk_x_pntrs is @@ -10110,8 +10084,6 @@ entity Arty_Z7_20_v_axi4s_vid_out_0_0_rd_status_flags_as is Q : in STD_LOGIC_VECTOR ( 11 downto 0 ); D : in STD_LOGIC_VECTOR ( 11 downto 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_v_axi4s_vid_out_0_0_rd_status_flags_as : entity is "rd_status_flags_as"; end Arty_Z7_20_v_axi4s_vid_out_0_0_rd_status_flags_as; architecture STRUCTURE of Arty_Z7_20_v_axi4s_vid_out_0_0_rd_status_flags_as is @@ -10195,8 +10167,6 @@ entity Arty_Z7_20_v_axi4s_vid_out_0_0_reset_blk_ramfifo is wr_clk : in STD_LOGIC; rst : in STD_LOGIC ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_v_axi4s_vid_out_0_0_reset_blk_ramfifo : entity is "reset_blk_ramfifo"; end Arty_Z7_20_v_axi4s_vid_out_0_0_reset_blk_ramfifo; architecture STRUCTURE of Arty_Z7_20_v_axi4s_vid_out_0_0_reset_blk_ramfifo is @@ -10494,8 +10464,6 @@ entity Arty_Z7_20_v_axi4s_vid_out_0_0_wr_status_flags_as is RD_PNTR_WR : in STD_LOGIC_VECTOR ( 11 downto 0 ); D : in STD_LOGIC_VECTOR ( 11 downto 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_v_axi4s_vid_out_0_0_wr_status_flags_as : entity is "wr_status_flags_as"; end Arty_Z7_20_v_axi4s_vid_out_0_0_wr_status_flags_as; architecture STRUCTURE of Arty_Z7_20_v_axi4s_vid_out_0_0_wr_status_flags_as is @@ -10591,8 +10559,6 @@ entity Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_generic_cstr is \gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); din : in STD_LOGIC_VECTOR ( 26 downto 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; end Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_generic_cstr; architecture STRUCTURE of Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_generic_cstr is @@ -10658,8 +10624,6 @@ entity Arty_Z7_20_v_axi4s_vid_out_0_0_rd_logic is \gnxpm_cdc.wr_pntr_bin_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \gnxpm_cdc.wr_pntr_bin_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_v_axi4s_vid_out_0_0_rd_logic : entity is "rd_logic"; end Arty_Z7_20_v_axi4s_vid_out_0_0_rd_logic; architecture STRUCTURE of Arty_Z7_20_v_axi4s_vid_out_0_0_rd_logic is @@ -10746,8 +10710,6 @@ entity Arty_Z7_20_v_axi4s_vid_out_0_0_wr_logic is RD_PNTR_WR : in STD_LOGIC_VECTOR ( 11 downto 0 ); wr_rst_busy : in STD_LOGIC ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_v_axi4s_vid_out_0_0_wr_logic : entity is "wr_logic"; end Arty_Z7_20_v_axi4s_vid_out_0_0_wr_logic; architecture STRUCTURE of Arty_Z7_20_v_axi4s_vid_out_0_0_wr_logic is @@ -10806,8 +10768,6 @@ entity Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_top is \gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); din : in STD_LOGIC_VECTOR ( 26 downto 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_top : entity is "blk_mem_gen_top"; end Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_top; architecture STRUCTURE of Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_top is @@ -10843,8 +10803,6 @@ entity Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_v8_3_5_synth is \gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); din : in STD_LOGIC_VECTOR ( 26 downto 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth"; end Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_v8_3_5_synth; architecture STRUCTURE of Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_v8_3_5_synth is @@ -10880,8 +10838,6 @@ entity Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_v8_3_5 is \gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); din : in STD_LOGIC_VECTOR ( 26 downto 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5"; end Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_v8_3_5; architecture STRUCTURE of Arty_Z7_20_v_axi4s_vid_out_0_0_blk_mem_gen_v8_3_5 is @@ -10917,8 +10873,6 @@ entity Arty_Z7_20_v_axi4s_vid_out_0_0_memory is \gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); din : in STD_LOGIC_VECTOR ( 26 downto 0 ) ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_v_axi4s_vid_out_0_0_memory : entity is "memory"; end Arty_Z7_20_v_axi4s_vid_out_0_0_memory; architecture STRUCTURE of Arty_Z7_20_v_axi4s_vid_out_0_0_memory is @@ -10957,8 +10911,6 @@ entity Arty_Z7_20_v_axi4s_vid_out_0_0_fifo_generator_ramfifo is rst : in STD_LOGIC; rd_en : in STD_LOGIC ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_v_axi4s_vid_out_0_0_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo"; end Arty_Z7_20_v_axi4s_vid_out_0_0_fifo_generator_ramfifo; architecture STRUCTURE of Arty_Z7_20_v_axi4s_vid_out_0_0_fifo_generator_ramfifo is @@ -11129,8 +11081,6 @@ entity Arty_Z7_20_v_axi4s_vid_out_0_0_fifo_generator_top is rst : in STD_LOGIC; rd_en : in STD_LOGIC ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_v_axi4s_vid_out_0_0_fifo_generator_top : entity is "fifo_generator_top"; end Arty_Z7_20_v_axi4s_vid_out_0_0_fifo_generator_top; architecture STRUCTURE of Arty_Z7_20_v_axi4s_vid_out_0_0_fifo_generator_top is @@ -11172,8 +11122,6 @@ entity Arty_Z7_20_v_axi4s_vid_out_0_0_fifo_generator_v13_1_3_synth is rst : in STD_LOGIC; rd_en : in STD_LOGIC ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_v_axi4s_vid_out_0_0_fifo_generator_v13_1_3_synth : entity is "fifo_generator_v13_1_3_synth"; end Arty_Z7_20_v_axi4s_vid_out_0_0_fifo_generator_v13_1_3_synth; architecture STRUCTURE of Arty_Z7_20_v_axi4s_vid_out_0_0_fifo_generator_v13_1_3_synth is @@ -11837,8 +11785,6 @@ entity Arty_Z7_20_v_axi4s_vid_out_0_0_fifo_generator_v13_1_3 is attribute C_WR_PNTR_WIDTH_WRCH of Arty_Z7_20_v_axi4s_vid_out_0_0_fifo_generator_v13_1_3 : entity is 4; attribute C_WR_RESPONSE_LATENCY : integer; attribute C_WR_RESPONSE_LATENCY of Arty_Z7_20_v_axi4s_vid_out_0_0_fifo_generator_v13_1_3 : entity is 1; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_v_axi4s_vid_out_0_0_fifo_generator_v13_1_3 : entity is "fifo_generator_v13_1_3"; end Arty_Z7_20_v_axi4s_vid_out_0_0_fifo_generator_v13_1_3; architecture STRUCTURE of Arty_Z7_20_v_axi4s_vid_out_0_0_fifo_generator_v13_1_3 is @@ -12431,8 +12377,6 @@ entity Arty_Z7_20_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_5_coupler is fifo_eol_dly : in STD_LOGIC; vid_io_out_reset : in STD_LOGIC ); - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_5_coupler : entity is "v_axi4s_vid_out_v4_0_5_coupler"; end Arty_Z7_20_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_5_coupler; architecture STRUCTURE of Arty_Z7_20_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_5_coupler is @@ -13319,8 +13263,6 @@ entity Arty_Z7_20_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_5 is attribute C_VTG_MASTER_SLAVE of Arty_Z7_20_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_5 : entity is 1; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of Arty_Z7_20_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_5 : entity is "yes"; - attribute ORIG_REF_NAME : string; - attribute ORIG_REF_NAME of Arty_Z7_20_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_5 : entity is "v_axi4s_vid_out_v4_0_5"; end Arty_Z7_20_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_5; architecture STRUCTURE of Arty_Z7_20_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_5 is diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0_stub.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0_stub.v index 0f6aa60..86f32cc 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0_stub.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -// Date : Fri Feb 24 16:05:07 2017 +// Date : Fri Feb 24 16:05:05 2017 // Host : WK73 running 64-bit Service Pack 1 (build 7601) -// Command : write_verilog -force -mode synth_stub -// c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0_stub.v +// Command : write_verilog -force -mode synth_stub -rename_top Arty_Z7_20_v_axi4s_vid_out_0_0 -prefix +// Arty_Z7_20_v_axi4s_vid_out_0_0_ Arty_Z7_20_v_axi4s_vid_out_0_0_stub.v // Design : Arty_Z7_20_v_axi4s_vid_out_0_0 // Purpose : Stub declaration of top-level module interface // Device : xc7z020clg400-1 diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0_stub.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0_stub.vhdl index 0c4788a..66c1389 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0_stub.vhdl +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 --- Date : Fri Feb 24 16:05:07 2017 +-- Date : Fri Feb 24 16:05:05 2017 -- Host : WK73 running 64-bit Service Pack 1 (build 7601) --- Command : write_vhdl -force -mode synth_stub --- c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_axi4s_vid_out_0_0/Arty_Z7_20_v_axi4s_vid_out_0_0_stub.vhdl +-- Command : write_vhdl -force -mode synth_stub -rename_top Arty_Z7_20_v_axi4s_vid_out_0_0 -prefix +-- Arty_Z7_20_v_axi4s_vid_out_0_0_ Arty_Z7_20_v_axi4s_vid_out_0_0_stub.vhdl -- Design : Arty_Z7_20_v_axi4s_vid_out_0_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7z020clg400-1 diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0.dcp b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0.dcp new file mode 100644 index 0000000..d75051b Binary files /dev/null and b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0.dcp differ diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0.xci b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0.xci new file mode 100644 index 0000000..fa4ffbe --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0.xci @@ -0,0 +1,183 @@ + + + xilinx.com + xci + unknown + 1.0 + + + Arty_Z7_20_v_rgb2ycrcb_0_0 + + + ACTIVE_LOW + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 + 118181816 + 0.000 + 100000000 + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 + 118181816 + 0 + 1 + 1 + 0 + xilinx.com:interface:datatypes:1.0 {TDATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value xilinx.com:video:G_B_R_444:1.0} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 24} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value rows} size {attribs {resolve_type generated dependency active_rows format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency active_rows_stride format long minimum {} maximum {}} value 24} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 24} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value cols} size {attribs {resolve_type generated dependency active_cols format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency active_cols_stride format long minimum {} maximum {}} value 24} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 24} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} struct {field_G {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value G} enabled {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency video_data_width format long minimum {} maximum {}} value 8} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}} field_B {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value B} enabled {attribs {resolve_type generated dependency video_comp1_enabled format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency video_data_width format long minimum {} maximum {}} value 8} bitoffset {attribs {resolve_type generated dependency video_comp1_offset format long minimum {} maximum {}} value 8} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}} field_R {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value R} enabled {attribs {resolve_type generated dependency video_comp2_enabled format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency video_data_width format long minimum {} maximum {}} value 8} bitoffset {attribs {resolve_type generated dependency video_comp2_offset format long minimum {} maximum {}} value 16} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}}}}}}} TDATA_WIDTH 24} + 0.000 + 3 + 0 + 0 + 1 + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 + 118181816 + 0 + 1 + 1 + 0 + xilinx.com:interface:datatypes:1.0 {TDATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value xilinx.com:video:Y_U_V_444:1.0} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 24} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value rows} size {attribs {resolve_type generated dependency active_rows format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency active_rows_stride format long minimum {} maximum {}} value 24} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 24} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value cols} size {attribs {resolve_type generated dependency active_cols format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency active_cols_stride format long minimum {} maximum {}} value 24} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 24} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} struct {field_Y {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value Y} enabled {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency video_data_width format long minimum {} maximum {}} value 8} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}} field_U {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value U} enabled {attribs {resolve_type generated dependency video_comp1_enabled format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency video_data_width format long minimum {} maximum {}} value 8} bitoffset {attribs {resolve_type generated dependency video_comp1_offset format long minimum {} maximum {}} value 8} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}} field_V {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value V} enabled {attribs {resolve_type generated dependency video_comp2_enabled format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency video_data_width format long minimum {} maximum {}} value 8} bitoffset {attribs {resolve_type generated dependency video_comp2_offset format long minimum {} maximum {}} value 16} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}}}}}}} TDATA_WIDTH 24} + 0.000 + 3 + 0 + 0 + 1 + 19595 + 1280 + 720 + 7471 + 240 + 16 + 128 + 46727 + 240 + 16 + 128 + 36962 + zynq + 0 + 1 + 1 + 0 + 0 + 1280 + 8 + 1 + 24 + 8 + 2 + 24 + 100000000 + 240 + 16 + 16 + 9 + 32 + 1280 + 720 + Arty_Z7_20_v_rgb2ycrcb_0_0 + false + false + false + 16_to_240_for_TV + 8 + SD_ITU_601 + 0.299 + 0.114 + 240 + 16 + 128 + 0.713 + 240 + 16 + 128 + 0.564 + true + true + 240 + 16 + 16 + zynq + digilentinc.com:arty-z7-20:part0:1.0 + xc7z020 + clg400 + VHDL + + MIXED + -1 + + TRUE + TRUE + IP_Integrator + 10 + TRUE + . + + ../../ipshared + 2016.4 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0.xml b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0.xml new file mode 100644 index 0000000..1fa2762 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0.xml @@ -0,0 +1,2109 @@ + + + xilinx.com + customized_ip + Arty_Z7_20_v_rgb2ycrcb_0_0 + 1.0 + + + ctrl + CTRL + + + + + + + ARADDR + + + s_axi_araddr + + + + + ARREADY + + + s_axi_arready + + + + + ARVALID + + + s_axi_arvalid + + + + + AWADDR + + + s_axi_awaddr + + + + + AWREADY + + + s_axi_awready + + + + + AWVALID + + + s_axi_awvalid + + + + + BREADY + + + s_axi_bready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + RDATA + + + s_axi_rdata + + + + + RREADY + + + s_axi_rready + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + WDATA + + + s_axi_wdata + + + + + WREADY + + + s_axi_wready + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + + + false + + + + + + video_out + VIDEO_OUT + + + + + + + TDATA + + + m_axis_video_tdata + + + + + TLAST + + + m_axis_video_tlast + + + + + TREADY + + + m_axis_video_tready + + + + + TUSER + + + m_axis_video_tuser_sof + + + + + TVALID + + + m_axis_video_tvalid + + + + + + TDATA_NUM_BYTES + 3 + + + TDEST_WIDTH + 0 + + + TID_WIDTH + 0 + + + TUSER_WIDTH + 1 + + + HAS_TREADY + 1 + + + HAS_TSTRB + 0 + + + HAS_TKEEP + 0 + + + HAS_TLAST + 1 + + + FREQ_HZ + 118181816 + + + PHASE + 0.000 + + + CLK_DOMAIN + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 + + + LAYERED_METADATA + xilinx.com:interface:datatypes:1.0 {TDATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value xilinx.com:video:Y_U_V_444:1.0} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 24} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value rows} size {attribs {resolve_type generated dependency active_rows format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency active_rows_stride format long minimum {} maximum {}} value 24} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 24} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value cols} size {attribs {resolve_type generated dependency active_cols format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency active_cols_stride format long minimum {} maximum {}} value 24} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 24} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} struct {field_Y {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value Y} enabled {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency video_data_width format long minimum {} maximum {}} value 8} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}} field_U {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value U} enabled {attribs {resolve_type generated dependency video_comp1_enabled format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency video_data_width format long minimum {} maximum {}} value 8} bitoffset {attribs {resolve_type generated dependency video_comp1_offset format long minimum {} maximum {}} value 8} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}} field_V {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value V} enabled {attribs {resolve_type generated dependency video_comp2_enabled format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency video_data_width format long minimum {} maximum {}} value 8} bitoffset {attribs {resolve_type generated dependency video_comp2_offset format long minimum {} maximum {}} value 16} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}}}}}}} TDATA_WIDTH 24} + + + + + video_in + VIDEO_IN + + + + + + + TDATA + + + s_axis_video_tdata + + + + + TLAST + + + s_axis_video_tlast + + + + + TREADY + + + s_axis_video_tready + + + + + TUSER + + + s_axis_video_tuser_sof + + + + + TVALID + + + s_axis_video_tvalid + + + + + + TDATA_NUM_BYTES + 3 + + + TDEST_WIDTH + 0 + + + TID_WIDTH + 0 + + + TUSER_WIDTH + 1 + + + HAS_TREADY + 1 + + + HAS_TSTRB + 0 + + + HAS_TKEEP + 0 + + + HAS_TLAST + 1 + + + FREQ_HZ + 118181816 + + + PHASE + 0.000 + + + CLK_DOMAIN + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 + + + LAYERED_METADATA + xilinx.com:interface:datatypes:1.0 {TDATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value xilinx.com:video:G_B_R_444:1.0} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 24} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value rows} size {attribs {resolve_type generated dependency active_rows format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency active_rows_stride format long minimum {} maximum {}} value 24} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 24} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value cols} size {attribs {resolve_type generated dependency active_cols format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency active_cols_stride format long minimum {} maximum {}} value 24} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 24} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} struct {field_G {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value G} enabled {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency video_data_width format long minimum {} maximum {}} value 8} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}} field_B {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value B} enabled {attribs {resolve_type generated dependency video_comp1_enabled format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency video_data_width format long minimum {} maximum {}} value 8} bitoffset {attribs {resolve_type generated dependency video_comp1_offset format long minimum {} maximum {}} value 8} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}} field_R {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value R} enabled {attribs {resolve_type generated dependency video_comp2_enabled format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency video_data_width format long minimum {} maximum {}} value 8} bitoffset {attribs {resolve_type generated dependency video_comp2_offset format long minimum {} maximum {}} value 16} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}}}}}}} TDATA_WIDTH 24} + + + + + aclk_intf + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + video_in:video_out + + + ASSOCIATED_RESET + aresetn + + + ASSOCIATED_CLKEN + aclken + + + FREQ_HZ + aclk frequency + aclk frequency + 118181816 + + + PHASE + 0.000 + + + CLK_DOMAIN + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 + + + + + s_axi_aclk_intf + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + ctrl + + + ASSOCIATED_RESET + s_axi_aresetn + + + ASSOCIATED_CLKEN + s_axi_aclken + + + FREQ_HZ + s_axi_aclk frequency + s_axi_aclk frequency + 100000000 + + + + + + false + + + + + + aresetn_intf + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s_axi_aresetn_intf + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + false + + + + + + aclken_intf + + + + + + + CE + + + aclken + + + + + + POLARITY + ACTIVE_LOW + + + + + s_axi_aclken_intf + + + + + + + CE + + + s_axi_aclken + + + + + + + false + + + + + + IRQ + irq + + + + + + + INTERRUPT + + + irq + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + false + + + + + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + + xilinx_vhdlsynthesis_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset + + + xilinx_vhdlsynthesis_xilinx_com_ip_v_tc_6_1__ref_view_fileset + + + xilinx_vhdlsynthesis_view_fileset + + + + GENtimestamp + Mon Mar 06 19:29:17 UTC 2017 + + + boundaryCRC + b6887981 + + + boundaryCRCversion + 1 + + + customizationCRC + f32e2ecd + + + customizationCRCversion + 6 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + xilinx_synthesisconstraints_view_fileset + + + + GENtimestamp + Mon Mar 06 19:29:17 UTC 2017 + + + boundaryCRC + b6887981 + + + boundaryCRCversion + 1 + + + customizationCRC + f32e2ecd + + + customizationCRCversion + 6 + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Mon Mar 06 19:29:17 UTC 2017 + + + boundaryCRC + b6887981 + + + boundaryCRCversion + 1 + + + customizationCRC + f32e2ecd + + + customizationCRCversion + 6 + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_v_tc_6_1__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + GENtimestamp + Mon Mar 06 19:29:17 UTC 2017 + + + boundaryCRC + b6887981 + + + boundaryCRCversion + 1 + + + customizationCRC + 717403ef + + + customizationCRCversion + 6 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Mar 06 19:29:17 UTC 2017 + + + boundaryCRC + b6887981 + + + boundaryCRCversion + 1 + + + customizationCRC + 717403ef + + + customizationCRCversion + 6 + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Mon Mar 06 19:30:50 UTC 2017 + + + boundaryCRC + b6887981 + + + boundaryCRCversion + 1 + + + customizationCRC + f32e2ecd + + + customizationCRCversion + 6 + + + + + + + aclk + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + aclken + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + aresetn + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + s_axi_aclk + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + false + + + + + + s_axi_aclken + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + false + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + false + + + + + + intc_if + + out + + 8 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + false + + + + + + irq + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + false + + + + + + s_axis_video_tdata + + in + + 23 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_video_tready + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_video_tvalid + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_video_tlast + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_video_tuser_sof + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_video_tdata + + out + + 23 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_video_tvalid + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_video_tready + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_video_tlast + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_video_tuser_sof + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axi_awaddr + + in + + 8 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_awready + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + false + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_wready + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + false + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + false + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + false + + + + + + s_axi_bready + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_araddr + + in + + 8 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_arready + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + false + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + false + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + false + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + false + + + + + + s_axi_rready + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + + + C_S_AXIS_VIDEO_DATA_WIDTH + 8 + + + C_S_AXIS_VIDEO_FORMAT + 2 + + + C_S_AXIS_VIDEO_TDATA_WIDTH + 24 + + + C_M_AXIS_VIDEO_DATA_WIDTH + 8 + + + C_M_AXIS_VIDEO_FORMAT + 1 + + + C_M_AXIS_VIDEO_TDATA_WIDTH + 24 + + + c_s_axi_addr_width + 9 + + + c_s_axi_data_width + 32 + + + C_HAS_AXI4_LITE + 0 + + + C_HAS_DEBUG + 0 + + + C_HAS_INTC_IF + 0 + + + C_MAX_COLS + 1280 + + + C_ACTIVE_COLS + 1280 + + + C_ACTIVE_ROWS + 720 + + + C_HAS_CLIP + 1 + + + C_HAS_CLAMP + 1 + + + C_ACOEF + 19595 + + + C_BCOEF + 7471 + + + C_CCOEF + 46727 + + + C_DCOEF + 36962 + + + C_YOFFSET + 16 + + + C_CBOFFSET + 128 + + + C_CROFFSET + 128 + + + C_YMAX + 240 + + + C_YMIN + 16 + + + C_CBMAX + 240 + + + C_CBMIN + 16 + + + C_CRMAX + 240 + + + C_CRMIN + 16 + + + C_S_AXI_CLK_FREQ_HZ + 100000000 + + + C_FAMILY + zynq + + + + + + choice_list_0279cec3 + 24 + 32 + 40 + 48 + + + choice_list_64f7fc6d + SD_ITU_601 + HD_ITU_709__1250_PAL + HD_ITU_709__1125_NTSC + YUV + Custom + + + choice_list_8aad6ae4 + 1 + 2 + + + choice_list_d1bb19c4 + 16_to_240_for_TV + 16_to_235_for_Studio_Equipment + 0_to_255_for_Computer_Graphics + + + choice_list_f1407c6a + 8 + 10 + 12 + 16 + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset + + ../../ipshared/0ba0/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd + vhdlSource + axi_lite_ipif_v3_0_4 + + + + + + + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_v_tc_6_1__ref_view_fileset + + ../../ipshared/d9f8/hdl/v_tc_v6_1_vh_rfs.vhd + vhdlSource + v_tc_v6_1_10 + + + + + + + + + + + xilinx_vhdlsynthesis_view_fileset + + Arty_Z7_20_v_rgb2ycrcb_0_0_clocks.xdc + xdc + USED_IN_implementation + USED_IN_synthesis + + processing_order + late + + + + ../../ipshared/953b/hdl/v_rgb2ycrcb_v7_1_vh_rfs.vhd + vhdlSource + v_rgb2ycrcb_v7_1_10 + + + + xilinx_synthesisconstraints_view_fileset + + Arty_Z7_20_v_rgb2ycrcb_0_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/Arty_Z7_20_v_rgb2ycrcb_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset + + ../../ipshared/0ba0/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + axi_lite_ipif_v3_0_4 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_v_tc_6_1__ref_view_fileset + + ../../ipshared/d9f8/hdl/v_tc_v6_1_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + v_tc_v6_1_10 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + ../../ipshared/953b/hdl/v_rgb2ycrcb_v7_1_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + v_rgb2ycrcb_v7_1_10 + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/Arty_Z7_20_v_rgb2ycrcb_0_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_externalfiles_view_fileset + + Arty_Z7_20_v_rgb2ycrcb_0_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + Arty_Z7_20_v_rgb2ycrcb_0_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Arty_Z7_20_v_rgb2ycrcb_0_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Arty_Z7_20_v_rgb2ycrcb_0_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Arty_Z7_20_v_rgb2ycrcb_0_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + The Xilinx RGB to YCrCb Color Space Converter LogiCORE with built-in support for 5 formats and 3 range standards. The implementation is a simplified 3x3 constant coefficient matrix multiplier, which uses only 4 multipliers exploiting the inter-relations of RGB to YCrCb coefficients. The module is optimized to take advantage of multiply-add capabilities of DSP slices. + + + Component_Name + Arty_Z7_20_v_rgb2ycrcb_0_0 + + + + true + + + + + + HAS_AXI4_LITE + Has AXI4 Lite + false + + + + true + + + + + + HAS_DEBUG + Has Debug + false + + + + false + + + + + + HAS_INTC_IF + Has Intc If + false + + + + true + + + + + + S_AXIS_VIDEO_DATA_WIDTH + S Axis Video Data Width + 8 + + + + true + + + + + + ACTIVE_COLS + Active Cols + 1280 + + + + true + + + + + + ACTIVE_ROWS + Active Rows + 720 + + + + true + + + + + + Standard_Sel + Standard Sel + SD_ITU_601 + + + + true + + + + + + Output_Range + Output Range + 16_to_240_for_TV + + + + true + + + + + + acoef + Acoef + 0.299 + + + + false + + + + + + bcoef + Bcoef + 0.114 + + + + false + + + + + + ccoef + Ccoef + 0.713 + + + + false + + + + + + dcoef + Dcoef + 0.564 + + + + false + + + + + + yoffset + Yoffset + 16 + + + + false + + + + + + cboffset + Cboffset + 128 + + + + false + + + + + + croffset + Croffset + 128 + + + + false + + + + + + has_clip + Has Clip + true + + + + false + + + + + + ymax + Ymax + 240 + + + + false + + + + + + cbmax + Cbmax + 240 + + + + false + + + + + + crmax + Crmax + 240 + + + + false + + + + + + has_clamp + Has Clamp + true + + + + false + + + + + + ymin + Ymin + 16 + + + + false + + + + + + cbmin + Cbmin + 16 + + + + false + + + + + + crmin + Crmin + 16 + + + + false + + + + + + + + RGB to YCrCb Color-Space Converter + 10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2016.4 + + + + + + + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0_clocks.xdc b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0_clocks.xdc new file mode 100644 index 0000000..139597f --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0_clocks.xdc @@ -0,0 +1,2 @@ + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0_ooc.xdc b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0_ooc.xdc new file mode 100644 index 0000000..6259de8 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0_ooc.xdc @@ -0,0 +1,57 @@ +# (c) Copyright 2012-2017 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +# DO NOT MODIFY THIS FILE. +# ######################################################### +# +# This XDC is used only in OOC mode for synthesis, implementation +# +# ######################################################### + + +create_clock -period 8.462 -name aclk [get_ports aclk] + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0_sim_netlist.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0_sim_netlist.v new file mode 100644 index 0000000..0910547 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0_sim_netlist.v @@ -0,0 +1,12880 @@ +// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +// Date : Mon Mar 06 11:30:49 2017 +// Host : WK73 running 64-bit Service Pack 1 (build 7601) +// Command : write_verilog -force -mode funcsim +// c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0_sim_netlist.v +// Design : Arty_Z7_20_v_rgb2ycrcb_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg400-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "Arty_Z7_20_v_rgb2ycrcb_0_0,v_rgb2ycrcb,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "v_rgb2ycrcb,Vivado 2016.4" *) +(* NotValidForBitStream *) +module Arty_Z7_20_v_rgb2ycrcb_0_0 + (aclk, + aclken, + aresetn, + s_axis_video_tdata, + s_axis_video_tready, + s_axis_video_tvalid, + s_axis_video_tlast, + s_axis_video_tuser_sof, + m_axis_video_tdata, + m_axis_video_tvalid, + m_axis_video_tready, + m_axis_video_tlast, + m_axis_video_tuser_sof); + (* x_interface_info = "xilinx.com:signal:clock:1.0 aclk_intf CLK" *) input aclk; + (* x_interface_info = "xilinx.com:signal:clockenable:1.0 aclken_intf CE" *) input aclken; + (* x_interface_info = "xilinx.com:signal:reset:1.0 aresetn_intf RST" *) input aresetn; + (* x_interface_info = "xilinx.com:interface:axis:1.0 video_in TDATA" *) input [23:0]s_axis_video_tdata; + (* x_interface_info = "xilinx.com:interface:axis:1.0 video_in TREADY" *) output s_axis_video_tready; + (* x_interface_info = "xilinx.com:interface:axis:1.0 video_in TVALID" *) input s_axis_video_tvalid; + (* x_interface_info = "xilinx.com:interface:axis:1.0 video_in TLAST" *) input s_axis_video_tlast; + (* x_interface_info = "xilinx.com:interface:axis:1.0 video_in TUSER" *) input s_axis_video_tuser_sof; + (* x_interface_info = "xilinx.com:interface:axis:1.0 video_out TDATA" *) output [23:0]m_axis_video_tdata; + (* x_interface_info = "xilinx.com:interface:axis:1.0 video_out TVALID" *) output m_axis_video_tvalid; + (* x_interface_info = "xilinx.com:interface:axis:1.0 video_out TREADY" *) input m_axis_video_tready; + (* x_interface_info = "xilinx.com:interface:axis:1.0 video_out TLAST" *) output m_axis_video_tlast; + (* x_interface_info = "xilinx.com:interface:axis:1.0 video_out TUSER" *) output m_axis_video_tuser_sof; + + wire aclk; + wire aclken; + wire aresetn; + wire [23:0]m_axis_video_tdata; + wire m_axis_video_tlast; + wire m_axis_video_tready; + wire m_axis_video_tuser_sof; + wire m_axis_video_tvalid; + wire [23:0]s_axis_video_tdata; + wire s_axis_video_tlast; + wire s_axis_video_tready; + wire s_axis_video_tuser_sof; + wire s_axis_video_tvalid; + wire NLW_U0_irq_UNCONNECTED; + wire NLW_U0_s_axi_arready_UNCONNECTED; + wire NLW_U0_s_axi_awready_UNCONNECTED; + wire NLW_U0_s_axi_bvalid_UNCONNECTED; + wire NLW_U0_s_axi_rvalid_UNCONNECTED; + wire NLW_U0_s_axi_wready_UNCONNECTED; + wire [8:0]NLW_U0_intc_if_UNCONNECTED; + wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED; + wire [31:0]NLW_U0_s_axi_rdata_UNCONNECTED; + wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED; + + (* C_ACOEF = "19595" *) + (* C_ACTIVE_COLS = "1280" *) + (* C_ACTIVE_ROWS = "720" *) + (* C_BCOEF = "7471" *) + (* C_CBMAX = "240" *) + (* C_CBMIN = "16" *) + (* C_CBOFFSET = "128" *) + (* C_CCOEF = "46727" *) + (* C_CRMAX = "240" *) + (* C_CRMIN = "16" *) + (* C_CROFFSET = "128" *) + (* C_DCOEF = "36962" *) + (* C_FAMILY = "zynq" *) + (* C_HAS_AXI4_LITE = "0" *) + (* C_HAS_CLAMP = "1" *) + (* C_HAS_CLIP = "1" *) + (* C_HAS_DEBUG = "0" *) + (* C_HAS_INTC_IF = "0" *) + (* C_MAX_COLS = "1280" *) + (* C_M_AXIS_VIDEO_DATA_WIDTH = "8" *) + (* C_M_AXIS_VIDEO_FORMAT = "1" *) + (* C_M_AXIS_VIDEO_TDATA_WIDTH = "24" *) + (* C_S_AXIS_VIDEO_DATA_WIDTH = "8" *) + (* C_S_AXIS_VIDEO_FORMAT = "2" *) + (* C_S_AXIS_VIDEO_TDATA_WIDTH = "24" *) + (* C_S_AXI_ADDR_WIDTH = "9" *) + (* C_S_AXI_CLK_FREQ_HZ = "100000000" *) + (* C_S_AXI_DATA_WIDTH = "32" *) + (* C_YMAX = "240" *) + (* C_YMIN = "16" *) + (* C_YOFFSET = "16" *) + (* downgradeipidentifiedwarnings = "yes" *) + Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb U0 + (.aclk(aclk), + .aclken(aclken), + .aresetn(aresetn), + .intc_if(NLW_U0_intc_if_UNCONNECTED[8:0]), + .irq(NLW_U0_irq_UNCONNECTED), + .m_axis_video_tdata(m_axis_video_tdata), + .m_axis_video_tlast(m_axis_video_tlast), + .m_axis_video_tready(m_axis_video_tready), + .m_axis_video_tuser_sof(m_axis_video_tuser_sof), + .m_axis_video_tvalid(m_axis_video_tvalid), + .s_axi_aclk(1'b0), + .s_axi_aclken(1'b1), + .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_aresetn(1'b1), + .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED), + .s_axi_arvalid(1'b0), + .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED), + .s_axi_awvalid(1'b0), + .s_axi_bready(1'b0), + .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]), + .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED), + .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[31:0]), + .s_axi_rready(1'b0), + .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]), + .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED), + .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED), + .s_axi_wstrb({1'b0,1'b0,1'b0,1'b0}), + .s_axi_wvalid(1'b0), + .s_axis_video_tdata(s_axis_video_tdata), + .s_axis_video_tlast(s_axis_video_tlast), + .s_axis_video_tready(s_axis_video_tready), + .s_axis_video_tuser_sof(s_axis_video_tuser_sof), + .s_axis_video_tvalid(s_axis_video_tvalid)); +endmodule + +(* ORIG_REF_NAME = "axi4s_control" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_axi4s_control + (master_en, + eol_late_i_reg_0, + sof_early_i_reg_0, + sof_early_i_reg_1, + da, + intc_if, + fifo_wr_i, + CO, + \col_cnt_reg[1]_0 , + E, + wen, + in_fifo_reset_reg_0, + \col_cnt_reg[12]_0 , + SR, + aclk, + \genr_control_regs[0] , + aclken, + resetn_out, + \write_ptr_int_reg[2] , + \time_control_regs[0] , + \write_ptr_int_reg[2]_0 , + \read_ptr_int_reg[1] , + empty_match_reg, + full_int_reg, + core_d_out, + vid_empty, + \word_count_reg[4] , + t_qb); + output master_en; + output eol_late_i_reg_0; + output sof_early_i_reg_0; + output sof_early_i_reg_1; + output [1:0]da; + output [4:0]intc_if; + output fifo_wr_i; + output [0:0]CO; + output \col_cnt_reg[1]_0 ; + output [0:0]E; + output wen; + output in_fifo_reset_reg_0; + output \col_cnt_reg[12]_0 ; + input [0:0]SR; + input aclk; + input [1:0]\genr_control_regs[0] ; + input aclken; + input resetn_out; + input \write_ptr_int_reg[2] ; + input [25:0]\time_control_regs[0] ; + input \write_ptr_int_reg[2]_0 ; + input \read_ptr_int_reg[1] ; + input empty_match_reg; + input full_int_reg; + input core_d_out; + input vid_empty; + input \word_count_reg[4] ; + input [1:0]t_qb; + + wire [0:0]CO; + wire [0:0]E; + wire [0:0]SR; + wire aclk; + wire aclken; + wire [12:0]active_cols_2; + wire \active_cols_2[11]_i_2_n_0 ; + wire \active_cols_2[11]_i_3_n_0 ; + wire \active_cols_2[11]_i_4_n_0 ; + wire \active_cols_2[11]_i_5_n_0 ; + wire \active_cols_2[12]_i_2_n_0 ; + wire \active_cols_2[3]_i_2_n_0 ; + wire \active_cols_2[3]_i_3_n_0 ; + wire \active_cols_2[3]_i_4_n_0 ; + wire \active_cols_2[3]_i_5_n_0 ; + wire \active_cols_2[7]_i_2_n_0 ; + wire \active_cols_2[7]_i_3_n_0 ; + wire \active_cols_2[7]_i_4_n_0 ; + wire \active_cols_2[7]_i_5_n_0 ; + wire \active_cols_2_reg[11]_i_1_n_0 ; + wire \active_cols_2_reg[11]_i_1_n_1 ; + wire \active_cols_2_reg[11]_i_1_n_2 ; + wire \active_cols_2_reg[11]_i_1_n_3 ; + wire \active_cols_2_reg[11]_i_1_n_4 ; + wire \active_cols_2_reg[11]_i_1_n_5 ; + wire \active_cols_2_reg[11]_i_1_n_6 ; + wire \active_cols_2_reg[11]_i_1_n_7 ; + wire \active_cols_2_reg[12]_i_1_n_7 ; + wire \active_cols_2_reg[3]_i_1_n_0 ; + wire \active_cols_2_reg[3]_i_1_n_1 ; + wire \active_cols_2_reg[3]_i_1_n_2 ; + wire \active_cols_2_reg[3]_i_1_n_3 ; + wire \active_cols_2_reg[3]_i_1_n_4 ; + wire \active_cols_2_reg[3]_i_1_n_5 ; + wire \active_cols_2_reg[3]_i_1_n_6 ; + wire \active_cols_2_reg[3]_i_1_n_7 ; + wire \active_cols_2_reg[7]_i_1_n_0 ; + wire \active_cols_2_reg[7]_i_1_n_1 ; + wire \active_cols_2_reg[7]_i_1_n_2 ; + wire \active_cols_2_reg[7]_i_1_n_3 ; + wire \active_cols_2_reg[7]_i_1_n_4 ; + wire \active_cols_2_reg[7]_i_1_n_5 ; + wire \active_cols_2_reg[7]_i_1_n_6 ; + wire \active_cols_2_reg[7]_i_1_n_7 ; + wire \col_cnt[0]_i_1_n_0 ; + wire \col_cnt[0]_i_2_n_0 ; + wire \col_cnt[10]_i_1_n_0 ; + wire \col_cnt[11]_i_1_n_0 ; + wire \col_cnt[12]_i_15_n_0 ; + wire \col_cnt[12]_i_16_n_0 ; + wire \col_cnt[12]_i_17_n_0 ; + wire \col_cnt[12]_i_18_n_0 ; + wire \col_cnt[12]_i_19_n_0 ; + wire \col_cnt[12]_i_1_n_0 ; + wire \col_cnt[12]_i_20_n_0 ; + wire \col_cnt[12]_i_3_n_0 ; + wire \col_cnt[12]_i_4_n_0 ; + wire \col_cnt[1]_i_1_n_0 ; + wire \col_cnt[1]_i_2_n_0 ; + wire \col_cnt[1]_i_3_n_0 ; + wire \col_cnt[1]_i_4_n_0 ; + wire \col_cnt[2]_i_1_n_0 ; + wire \col_cnt[2]_i_2_n_0 ; + wire \col_cnt[2]_i_3_n_0 ; + wire \col_cnt[3]_i_1_n_0 ; + wire \col_cnt[4]_i_1_n_0 ; + wire \col_cnt[4]_i_3_n_0 ; + wire \col_cnt[4]_i_4_n_0 ; + wire \col_cnt[4]_i_5_n_0 ; + wire \col_cnt[4]_i_6_n_0 ; + wire \col_cnt[5]_i_1_n_0 ; + wire \col_cnt[6]_i_1_n_0 ; + wire \col_cnt[7]_i_1_n_0 ; + wire \col_cnt[8]_i_1_n_0 ; + wire \col_cnt[8]_i_3_n_0 ; + wire \col_cnt[8]_i_4_n_0 ; + wire \col_cnt[8]_i_5_n_0 ; + wire \col_cnt[8]_i_6_n_0 ; + wire \col_cnt[9]_i_1_n_0 ; + wire \col_cnt_reg[12]_0 ; + wire \col_cnt_reg[12]_i_9_n_1 ; + wire \col_cnt_reg[12]_i_9_n_2 ; + wire \col_cnt_reg[12]_i_9_n_3 ; + wire \col_cnt_reg[1]_0 ; + wire \col_cnt_reg[4]_i_2_n_0 ; + wire \col_cnt_reg[4]_i_2_n_1 ; + wire \col_cnt_reg[4]_i_2_n_2 ; + wire \col_cnt_reg[4]_i_2_n_3 ; + wire \col_cnt_reg[8]_i_2_n_0 ; + wire \col_cnt_reg[8]_i_2_n_1 ; + wire \col_cnt_reg[8]_i_2_n_2 ; + wire \col_cnt_reg[8]_i_2_n_3 ; + wire \col_cnt_reg_n_0_[0] ; + wire \col_cnt_reg_n_0_[10] ; + wire \col_cnt_reg_n_0_[11] ; + wire \col_cnt_reg_n_0_[12] ; + wire \col_cnt_reg_n_0_[1] ; + wire \col_cnt_reg_n_0_[2] ; + wire \col_cnt_reg_n_0_[3] ; + wire \col_cnt_reg_n_0_[4] ; + wire \col_cnt_reg_n_0_[5] ; + wire \col_cnt_reg_n_0_[6] ; + wire \col_cnt_reg_n_0_[7] ; + wire \col_cnt_reg_n_0_[8] ; + wire \col_cnt_reg_n_0_[9] ; + wire core_d_out; + wire core_en_i; + wire core_en_i_i_1_n_0; + wire [1:0]da; + wire [12:1]data1; + wire empty_match_reg; + wire eof_i_i_1_n_0; + wire eol_early_i0; + wire eol_early_i_i_1_n_0; + wire eol_early_i_i_4_n_0; + wire eol_expected; + wire eol_expected0; + wire eol_expected_d; + wire eol_expected_d_i_1_n_0; + wire eol_late_i3_out; + wire eol_late_i_i_2_n_0; + wire eol_late_i_i_3_n_0; + wire eol_late_i_reg_0; + wire eqOp; + wire eqOp0_out; + wire eqOp1_out; + wire eqOp_0; + wire eqOp_carry__0_i_1_n_0; + wire eqOp_carry_i_1_n_0; + wire eqOp_carry_i_2_n_0; + wire eqOp_carry_i_3_n_0; + wire eqOp_carry_i_4_n_0; + wire eqOp_carry_n_0; + wire eqOp_carry_n_1; + wire eqOp_carry_n_2; + wire eqOp_carry_n_3; + wire \eqOp_inferred__3/i__carry_n_0 ; + wire \eqOp_inferred__3/i__carry_n_1 ; + wire \eqOp_inferred__3/i__carry_n_2 ; + wire \eqOp_inferred__3/i__carry_n_3 ; + wire \eqOp_inferred__4/i__carry_n_0 ; + wire \eqOp_inferred__4/i__carry_n_1 ; + wire \eqOp_inferred__4/i__carry_n_2 ; + wire \eqOp_inferred__4/i__carry_n_3 ; + wire fifo_rd_d; + wire fifo_rd_d_i_1_n_0; + wire fifo_rd_i; + wire fifo_rd_i0; + wire fifo_rd_i_i_1_n_0; + wire fifo_wr_i; + wire fifo_wr_i_i_10_n_0; + wire fifo_wr_i_i_11_n_0; + wire fifo_wr_i_i_12_n_0; + wire fifo_wr_i_i_13_n_0; + wire fifo_wr_i_i_14_n_0; + wire fifo_wr_i_i_1_n_0; + wire fifo_wr_i_i_4_n_0; + wire fifo_wr_i_i_5_n_0; + wire fifo_wr_i_i_6_n_0; + wire fifo_wr_i_i_7_n_0; + wire fifo_wr_i_i_8_n_0; + wire fifo_wr_i_i_9_n_0; + wire fifo_wr_i_reg_i_2_n_2; + wire fifo_wr_i_reg_i_2_n_3; + wire fifo_wr_i_reg_i_3_n_0; + wire fifo_wr_i_reg_i_3_n_1; + wire fifo_wr_i_reg_i_3_n_2; + wire fifo_wr_i_reg_i_3_n_3; + wire full_int_reg; + wire [1:0]\genr_control_regs[0] ; + wire geqOp; + wire geqOp_carry__0_i_1_n_0; + wire geqOp_carry__0_i_2_n_0; + wire geqOp_carry__0_i_3_n_0; + wire geqOp_carry__0_i_4_n_0; + wire geqOp_carry__0_i_5_n_0; + wire geqOp_carry__0_i_6_n_0; + wire geqOp_carry__0_n_2; + wire geqOp_carry__0_n_3; + wire geqOp_carry_i_1_n_0; + wire geqOp_carry_i_2_n_0; + wire geqOp_carry_i_3_n_0; + wire geqOp_carry_i_4_n_0; + wire geqOp_carry_i_5_n_0; + wire geqOp_carry_i_6_n_0; + wire geqOp_carry_i_7_n_0; + wire geqOp_carry_i_8_n_0; + wire geqOp_carry_n_0; + wire geqOp_carry_n_1; + wire geqOp_carry_n_2; + wire geqOp_carry_n_3; + wire gtOp; + wire gtOp18_in; + wire gtOp19_in; + wire gtOp21_in; + wire gtOp22_in; + wire gtOp_carry__0_i_1_n_0; + wire gtOp_carry__0_i_2_n_0; + wire gtOp_carry__0_i_3_n_0; + wire gtOp_carry__0_i_4_n_0; + wire gtOp_carry__0_i_5_n_0; + wire gtOp_carry__0_i_6_n_0; + wire gtOp_carry__0_n_2; + wire gtOp_carry__0_n_3; + wire gtOp_carry_i_1_n_0; + wire gtOp_carry_i_2_n_0; + wire gtOp_carry_i_3_n_0; + wire gtOp_carry_i_4_n_0; + wire gtOp_carry_i_5_n_0; + wire gtOp_carry_i_6_n_0; + wire gtOp_carry_i_7_n_0; + wire gtOp_carry_i_8_n_0; + wire gtOp_carry_n_0; + wire gtOp_carry_n_1; + wire gtOp_carry_n_2; + wire gtOp_carry_n_3; + wire \gtOp_inferred__0/i__carry__0_n_2 ; + wire \gtOp_inferred__0/i__carry__0_n_3 ; + wire \gtOp_inferred__0/i__carry_n_0 ; + wire \gtOp_inferred__0/i__carry_n_1 ; + wire \gtOp_inferred__0/i__carry_n_2 ; + wire \gtOp_inferred__0/i__carry_n_3 ; + wire \gtOp_inferred__2/i__carry__0_n_2 ; + wire \gtOp_inferred__2/i__carry__0_n_3 ; + wire \gtOp_inferred__2/i__carry_n_0 ; + wire \gtOp_inferred__2/i__carry_n_1 ; + wire \gtOp_inferred__2/i__carry_n_2 ; + wire \gtOp_inferred__2/i__carry_n_3 ; + wire \gtOp_inferred__3/i__carry__0_n_2 ; + wire \gtOp_inferred__3/i__carry__0_n_3 ; + wire \gtOp_inferred__3/i__carry_n_0 ; + wire \gtOp_inferred__3/i__carry_n_1 ; + wire \gtOp_inferred__3/i__carry_n_2 ; + wire \gtOp_inferred__3/i__carry_n_3 ; + wire i__carry__0_i_1__0_n_0; + wire i__carry__0_i_1__1_n_0; + wire i__carry__0_i_1__2_n_0; + wire i__carry__0_i_1__3_n_0; + wire i__carry__0_i_1__4_n_0; + wire i__carry__0_i_1__5_n_0; + wire i__carry__0_i_1__6_n_0; + wire i__carry__0_i_1_n_0; + wire i__carry__0_i_2__0_n_0; + wire i__carry__0_i_2__1_n_0; + wire i__carry__0_i_2__2_n_0; + wire i__carry__0_i_2__3_n_0; + wire i__carry__0_i_2__4_n_0; + wire i__carry__0_i_2_n_0; + wire i__carry__0_i_3__0_n_0; + wire i__carry__0_i_3__1_n_0; + wire i__carry__0_i_3__2_n_0; + wire i__carry__0_i_3__3_n_0; + wire i__carry__0_i_3_n_0; + wire i__carry__0_i_4__0_n_0; + wire i__carry__0_i_4__1_n_0; + wire i__carry__0_i_4__2_n_0; + wire i__carry__0_i_4__3_n_0; + wire i__carry__0_i_4_n_0; + wire i__carry__0_i_5__0_n_0; + wire i__carry__0_i_5__1_n_0; + wire i__carry__0_i_5__2_n_0; + wire i__carry__0_i_5__3_n_0; + wire i__carry__0_i_5_n_0; + wire i__carry__0_i_6__0_n_0; + wire i__carry__0_i_6__1_n_0; + wire i__carry__0_i_6_n_0; + wire i__carry_i_1__0_n_0; + wire i__carry_i_1__1_n_0; + wire i__carry_i_1__2_n_0; + wire i__carry_i_1__3_n_0; + wire i__carry_i_1__4_n_0; + wire i__carry_i_1__5_n_0; + wire i__carry_i_1__6_n_0; + wire i__carry_i_1_n_0; + wire i__carry_i_2__0_n_0; + wire i__carry_i_2__1_n_0; + wire i__carry_i_2__2_n_0; + wire i__carry_i_2__3_n_0; + wire i__carry_i_2__4_n_0; + wire i__carry_i_2__5_n_0; + wire i__carry_i_2__6_n_0; + wire i__carry_i_2_n_0; + wire i__carry_i_3__0_n_0; + wire i__carry_i_3__1_n_0; + wire i__carry_i_3__2_n_0; + wire i__carry_i_3__3_n_0; + wire i__carry_i_3__4_n_0; + wire i__carry_i_3__5_n_0; + wire i__carry_i_3__6_n_0; + wire i__carry_i_3_n_0; + wire i__carry_i_4__0_n_0; + wire i__carry_i_4__1_n_0; + wire i__carry_i_4__2_n_0; + wire i__carry_i_4__3_n_0; + wire i__carry_i_4__4_n_0; + wire i__carry_i_4__5_n_0; + wire i__carry_i_4__6_n_0; + wire i__carry_i_4_n_0; + wire i__carry_i_5__0_n_0; + wire i__carry_i_5__1_n_0; + wire i__carry_i_5__2_n_0; + wire i__carry_i_5__3_n_0; + wire i__carry_i_5__4_n_0; + wire i__carry_i_5_n_0; + wire i__carry_i_6__0_n_0; + wire i__carry_i_6__1_n_0; + wire i__carry_i_6__2_n_0; + wire i__carry_i_6__3_n_0; + wire i__carry_i_6_n_0; + wire i__carry_i_7__0_n_0; + wire i__carry_i_7__1_n_0; + wire i__carry_i_7__2_n_0; + wire i__carry_i_7__3_n_0; + wire i__carry_i_7_n_0; + wire i__carry_i_8__0_n_0; + wire i__carry_i_8__1_n_0; + wire i__carry_i_8__2_n_0; + wire i__carry_i_8_n_0; + wire in_fifo_reset; + wire in_fifo_reset0; + wire in_fifo_reset_i_3_n_0; + wire in_fifo_reset_reg_0; + wire [4:0]intc_if; + wire leqOp16_in; + wire leqOp20_in; + wire leqOp23_in; + wire leqOp_carry__0_i_1_n_0; + wire leqOp_carry__0_i_2_n_0; + wire leqOp_carry__0_i_3_n_0; + wire leqOp_carry__0_i_4_n_0; + wire leqOp_carry__0_i_5_n_0; + wire leqOp_carry__0_i_6_n_0; + wire leqOp_carry__0_n_2; + wire leqOp_carry__0_n_3; + wire leqOp_carry_i_1_n_0; + wire leqOp_carry_i_2_n_0; + wire leqOp_carry_i_3_n_0; + wire leqOp_carry_i_4_n_0; + wire leqOp_carry_i_5_n_0; + wire leqOp_carry_i_6_n_0; + wire leqOp_carry_i_7_n_0; + wire leqOp_carry_i_8_n_0; + wire leqOp_carry_n_0; + wire leqOp_carry_n_1; + wire leqOp_carry_n_2; + wire leqOp_carry_n_3; + wire \leqOp_inferred__0/i__carry__0_n_2 ; + wire \leqOp_inferred__0/i__carry__0_n_3 ; + wire \leqOp_inferred__0/i__carry_n_0 ; + wire \leqOp_inferred__0/i__carry_n_1 ; + wire \leqOp_inferred__0/i__carry_n_2 ; + wire \leqOp_inferred__0/i__carry_n_3 ; + wire \leqOp_inferred__1/i__carry__0_n_2 ; + wire \leqOp_inferred__1/i__carry__0_n_3 ; + wire \leqOp_inferred__1/i__carry_n_0 ; + wire \leqOp_inferred__1/i__carry_n_1 ; + wire \leqOp_inferred__1/i__carry_n_2 ; + wire \leqOp_inferred__1/i__carry_n_3 ; + wire line_cnt_tc_i_1_n_0; + wire line_cnt_tc_i_2_n_0; + wire line_cnt_tc_i_3_n_0; + wire line_cnt_tc_i_4_n_0; + wire line_cnt_tc_i_5_n_0; + wire line_cnt_tc_i_6_n_0; + wire ltOp_carry__0_i_1_n_0; + wire ltOp_carry__0_i_2_n_0; + wire ltOp_carry__0_i_3_n_0; + wire ltOp_carry__0_i_4_n_0; + wire ltOp_carry__0_i_5_n_0; + wire ltOp_carry__0_i_6_n_0; + wire ltOp_carry__0_n_1; + wire ltOp_carry__0_n_2; + wire ltOp_carry__0_n_3; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire \ltOp_inferred__0/i__carry__0_n_3 ; + wire \ltOp_inferred__0/i__carry_n_0 ; + wire \ltOp_inferred__0/i__carry_n_1 ; + wire \ltOp_inferred__0/i__carry_n_2 ; + wire \ltOp_inferred__0/i__carry_n_3 ; + wire master_en; + wire out_fifo_sof0; + wire out_fifo_sof_i_2_n_0; + wire pixel_cnt_tc_i_1_n_0; + wire pixel_cnt_tc_i_3_n_0; + wire pixel_cnt_tc_i_4_n_0; + wire [12:0]plusOp; + wire \read_ptr_int_reg[1] ; + wire resetn_out; + wire row_cnt; + wire \row_cnt[0]_i_1_n_0 ; + wire \row_cnt[0]_i_4_n_0 ; + wire \row_cnt[0]_i_5_n_0 ; + wire \row_cnt[0]_i_6_n_0 ; + wire \row_cnt[0]_i_7_n_0 ; + wire \row_cnt[0]_i_8_n_0 ; + wire \row_cnt[12]_i_2_n_0 ; + wire \row_cnt[4]_i_2_n_0 ; + wire \row_cnt[4]_i_3_n_0 ; + wire \row_cnt[4]_i_4_n_0 ; + wire \row_cnt[4]_i_5_n_0 ; + wire \row_cnt[8]_i_2_n_0 ; + wire \row_cnt[8]_i_3_n_0 ; + wire \row_cnt[8]_i_4_n_0 ; + wire \row_cnt[8]_i_5_n_0 ; + wire [12:0]row_cnt_reg; + wire \row_cnt_reg[0]_i_3_n_0 ; + wire \row_cnt_reg[0]_i_3_n_1 ; + wire \row_cnt_reg[0]_i_3_n_2 ; + wire \row_cnt_reg[0]_i_3_n_3 ; + wire \row_cnt_reg[0]_i_3_n_4 ; + wire \row_cnt_reg[0]_i_3_n_5 ; + wire \row_cnt_reg[0]_i_3_n_6 ; + wire \row_cnt_reg[0]_i_3_n_7 ; + wire \row_cnt_reg[12]_i_1_n_7 ; + wire \row_cnt_reg[4]_i_1_n_0 ; + wire \row_cnt_reg[4]_i_1_n_1 ; + wire \row_cnt_reg[4]_i_1_n_2 ; + wire \row_cnt_reg[4]_i_1_n_3 ; + wire \row_cnt_reg[4]_i_1_n_4 ; + wire \row_cnt_reg[4]_i_1_n_5 ; + wire \row_cnt_reg[4]_i_1_n_6 ; + wire \row_cnt_reg[4]_i_1_n_7 ; + wire \row_cnt_reg[8]_i_1_n_0 ; + wire \row_cnt_reg[8]_i_1_n_1 ; + wire \row_cnt_reg[8]_i_1_n_2 ; + wire \row_cnt_reg[8]_i_1_n_3 ; + wire \row_cnt_reg[8]_i_1_n_4 ; + wire \row_cnt_reg[8]_i_1_n_5 ; + wire \row_cnt_reg[8]_i_1_n_6 ; + wire \row_cnt_reg[8]_i_1_n_7 ; + wire sof_early_i_i_1_n_0; + wire sof_early_i_reg_0; + wire sof_early_i_reg_1; + wire sof_expected; + wire sof_expected0; + wire sof_expected_i_2_n_0; + wire sof_expected_i_3_n_0; + wire sof_expected_i_4_n_0; + wire sof_expected_i_5_n_0; + wire sof_expected_i_6_n_0; + wire sof_expected_i_7_n_0; + wire sof_expected_i_8_n_0; + wire sof_expected_i_9_n_0; + wire sof_late_i2_out; + wire [1:0]t_qb; + wire [25:0]\time_control_regs[0] ; + wire [12:0]total_cols; + wire \total_cols[12]_i_2_n_0 ; + wire \total_cols[12]_i_3_n_0 ; + wire \total_cols[12]_i_4_n_0 ; + wire \total_cols[12]_i_5_n_0 ; + wire \total_cols[4]_i_2_n_0 ; + wire \total_cols[4]_i_3_n_0 ; + wire \total_cols[4]_i_4_n_0 ; + wire \total_cols[4]_i_5_n_0 ; + wire \total_cols[8]_i_2_n_0 ; + wire \total_cols[8]_i_3_n_0 ; + wire \total_cols[8]_i_4_n_0 ; + wire \total_cols[8]_i_5_n_0 ; + wire \total_cols_reg[12]_i_1_n_1 ; + wire \total_cols_reg[12]_i_1_n_2 ; + wire \total_cols_reg[12]_i_1_n_3 ; + wire \total_cols_reg[4]_i_1_n_0 ; + wire \total_cols_reg[4]_i_1_n_1 ; + wire \total_cols_reg[4]_i_1_n_2 ; + wire \total_cols_reg[4]_i_1_n_3 ; + wire \total_cols_reg[8]_i_1_n_0 ; + wire \total_cols_reg[8]_i_1_n_1 ; + wire \total_cols_reg[8]_i_1_n_2 ; + wire \total_cols_reg[8]_i_1_n_3 ; + wire [12:0]total_rows; + wire vid_empty; + wire wen; + wire \word_count_reg[4] ; + wire \write_ptr_int_reg[2] ; + wire \write_ptr_int_reg[2]_0 ; + wire [3:0]\NLW_active_cols_2_reg[12]_i_1_CO_UNCONNECTED ; + wire [3:1]\NLW_active_cols_2_reg[12]_i_1_O_UNCONNECTED ; + wire [3:3]\NLW_col_cnt_reg[12]_i_9_CO_UNCONNECTED ; + wire [3:0]NLW_eqOp_carry_O_UNCONNECTED; + wire [3:1]NLW_eqOp_carry__0_CO_UNCONNECTED; + wire [3:0]NLW_eqOp_carry__0_O_UNCONNECTED; + wire [3:0]\NLW_eqOp_inferred__3/i__carry_O_UNCONNECTED ; + wire [3:1]\NLW_eqOp_inferred__3/i__carry__0_CO_UNCONNECTED ; + wire [3:0]\NLW_eqOp_inferred__3/i__carry__0_O_UNCONNECTED ; + wire [3:0]\NLW_eqOp_inferred__4/i__carry_O_UNCONNECTED ; + wire [3:1]\NLW_eqOp_inferred__4/i__carry__0_CO_UNCONNECTED ; + wire [3:0]\NLW_eqOp_inferred__4/i__carry__0_O_UNCONNECTED ; + wire [3:3]NLW_fifo_wr_i_reg_i_2_CO_UNCONNECTED; + wire [3:0]NLW_fifo_wr_i_reg_i_2_O_UNCONNECTED; + wire [3:0]NLW_fifo_wr_i_reg_i_3_O_UNCONNECTED; + wire [3:0]NLW_geqOp_carry_O_UNCONNECTED; + wire [3:3]NLW_geqOp_carry__0_CO_UNCONNECTED; + wire [3:0]NLW_geqOp_carry__0_O_UNCONNECTED; + wire [3:0]NLW_gtOp_carry_O_UNCONNECTED; + wire [3:3]NLW_gtOp_carry__0_CO_UNCONNECTED; + wire [3:0]NLW_gtOp_carry__0_O_UNCONNECTED; + wire [3:0]\NLW_gtOp_inferred__0/i__carry_O_UNCONNECTED ; + wire [3:3]\NLW_gtOp_inferred__0/i__carry__0_CO_UNCONNECTED ; + wire [3:0]\NLW_gtOp_inferred__0/i__carry__0_O_UNCONNECTED ; + wire [3:0]\NLW_gtOp_inferred__2/i__carry_O_UNCONNECTED ; + wire [3:3]\NLW_gtOp_inferred__2/i__carry__0_CO_UNCONNECTED ; + wire [3:0]\NLW_gtOp_inferred__2/i__carry__0_O_UNCONNECTED ; + wire [3:0]\NLW_gtOp_inferred__3/i__carry_O_UNCONNECTED ; + wire [3:3]\NLW_gtOp_inferred__3/i__carry__0_CO_UNCONNECTED ; + wire [3:0]\NLW_gtOp_inferred__3/i__carry__0_O_UNCONNECTED ; + wire [3:0]NLW_leqOp_carry_O_UNCONNECTED; + wire [3:3]NLW_leqOp_carry__0_CO_UNCONNECTED; + wire [3:0]NLW_leqOp_carry__0_O_UNCONNECTED; + wire [3:0]\NLW_leqOp_inferred__0/i__carry_O_UNCONNECTED ; + wire [3:3]\NLW_leqOp_inferred__0/i__carry__0_CO_UNCONNECTED ; + wire [3:0]\NLW_leqOp_inferred__0/i__carry__0_O_UNCONNECTED ; + wire [3:0]\NLW_leqOp_inferred__1/i__carry_O_UNCONNECTED ; + wire [3:3]\NLW_leqOp_inferred__1/i__carry__0_CO_UNCONNECTED ; + wire [3:0]\NLW_leqOp_inferred__1/i__carry__0_O_UNCONNECTED ; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:3]NLW_ltOp_carry__0_CO_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]\NLW_ltOp_inferred__0/i__carry_O_UNCONNECTED ; + wire [3:2]\NLW_ltOp_inferred__0/i__carry__0_CO_UNCONNECTED ; + wire [3:0]\NLW_ltOp_inferred__0/i__carry__0_O_UNCONNECTED ; + wire [3:0]\NLW_row_cnt_reg[12]_i_1_CO_UNCONNECTED ; + wire [3:1]\NLW_row_cnt_reg[12]_i_1_O_UNCONNECTED ; + wire [3:3]\NLW_total_cols_reg[12]_i_1_CO_UNCONNECTED ; + + LUT6 #( + .INIT(64'h0000000800000000)) + \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_i_1 + (.I0(aclken), + .I1(\genr_control_regs[0] [0]), + .I2(eol_late_i_reg_0), + .I3(full_int_reg), + .I4(core_d_out), + .I5(fifo_wr_i), + .O(wen)); + LUT1 #( + .INIT(2'h2)) + \active_cols_2[11]_i_2 + (.I0(\time_control_regs[0] [11]), + .O(\active_cols_2[11]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \active_cols_2[11]_i_3 + (.I0(\time_control_regs[0] [10]), + .O(\active_cols_2[11]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \active_cols_2[11]_i_4 + (.I0(\time_control_regs[0] [9]), + .O(\active_cols_2[11]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \active_cols_2[11]_i_5 + (.I0(\time_control_regs[0] [8]), + .O(\active_cols_2[11]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \active_cols_2[12]_i_2 + (.I0(\time_control_regs[0] [12]), + .O(\active_cols_2[12]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \active_cols_2[3]_i_2 + (.I0(\time_control_regs[0] [3]), + .O(\active_cols_2[3]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \active_cols_2[3]_i_3 + (.I0(\time_control_regs[0] [2]), + .O(\active_cols_2[3]_i_3_n_0 )); + LUT1 #( + .INIT(2'h1)) + \active_cols_2[3]_i_4 + (.I0(\time_control_regs[0] [1]), + .O(\active_cols_2[3]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \active_cols_2[3]_i_5 + (.I0(\time_control_regs[0] [0]), + .O(\active_cols_2[3]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \active_cols_2[7]_i_2 + (.I0(\time_control_regs[0] [7]), + .O(\active_cols_2[7]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \active_cols_2[7]_i_3 + (.I0(\time_control_regs[0] [6]), + .O(\active_cols_2[7]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \active_cols_2[7]_i_4 + (.I0(\time_control_regs[0] [5]), + .O(\active_cols_2[7]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \active_cols_2[7]_i_5 + (.I0(\time_control_regs[0] [4]), + .O(\active_cols_2[7]_i_5_n_0 )); + FDRE #( + .INIT(1'b0)) + \active_cols_2_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\active_cols_2_reg[3]_i_1_n_7 ), + .Q(active_cols_2[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \active_cols_2_reg[10] + (.C(aclk), + .CE(1'b1), + .D(\active_cols_2_reg[11]_i_1_n_5 ), + .Q(active_cols_2[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \active_cols_2_reg[11] + (.C(aclk), + .CE(1'b1), + .D(\active_cols_2_reg[11]_i_1_n_4 ), + .Q(active_cols_2[11]), + .R(1'b0)); + CARRY4 \active_cols_2_reg[11]_i_1 + (.CI(\active_cols_2_reg[7]_i_1_n_0 ), + .CO({\active_cols_2_reg[11]_i_1_n_0 ,\active_cols_2_reg[11]_i_1_n_1 ,\active_cols_2_reg[11]_i_1_n_2 ,\active_cols_2_reg[11]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\active_cols_2_reg[11]_i_1_n_4 ,\active_cols_2_reg[11]_i_1_n_5 ,\active_cols_2_reg[11]_i_1_n_6 ,\active_cols_2_reg[11]_i_1_n_7 }), + .S({\active_cols_2[11]_i_2_n_0 ,\active_cols_2[11]_i_3_n_0 ,\active_cols_2[11]_i_4_n_0 ,\active_cols_2[11]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \active_cols_2_reg[12] + (.C(aclk), + .CE(1'b1), + .D(\active_cols_2_reg[12]_i_1_n_7 ), + .Q(active_cols_2[12]), + .R(1'b0)); + CARRY4 \active_cols_2_reg[12]_i_1 + (.CI(\active_cols_2_reg[11]_i_1_n_0 ), + .CO(\NLW_active_cols_2_reg[12]_i_1_CO_UNCONNECTED [3:0]), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_active_cols_2_reg[12]_i_1_O_UNCONNECTED [3:1],\active_cols_2_reg[12]_i_1_n_7 }), + .S({1'b0,1'b0,1'b0,\active_cols_2[12]_i_2_n_0 })); + FDRE #( + .INIT(1'b0)) + \active_cols_2_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\active_cols_2_reg[3]_i_1_n_6 ), + .Q(active_cols_2[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \active_cols_2_reg[2] + (.C(aclk), + .CE(1'b1), + .D(\active_cols_2_reg[3]_i_1_n_5 ), + .Q(active_cols_2[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \active_cols_2_reg[3] + (.C(aclk), + .CE(1'b1), + .D(\active_cols_2_reg[3]_i_1_n_4 ), + .Q(active_cols_2[3]), + .R(1'b0)); + CARRY4 \active_cols_2_reg[3]_i_1 + (.CI(1'b0), + .CO({\active_cols_2_reg[3]_i_1_n_0 ,\active_cols_2_reg[3]_i_1_n_1 ,\active_cols_2_reg[3]_i_1_n_2 ,\active_cols_2_reg[3]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,\time_control_regs[0] [1],1'b0}), + .O({\active_cols_2_reg[3]_i_1_n_4 ,\active_cols_2_reg[3]_i_1_n_5 ,\active_cols_2_reg[3]_i_1_n_6 ,\active_cols_2_reg[3]_i_1_n_7 }), + .S({\active_cols_2[3]_i_2_n_0 ,\active_cols_2[3]_i_3_n_0 ,\active_cols_2[3]_i_4_n_0 ,\active_cols_2[3]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \active_cols_2_reg[4] + (.C(aclk), + .CE(1'b1), + .D(\active_cols_2_reg[7]_i_1_n_7 ), + .Q(active_cols_2[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \active_cols_2_reg[5] + (.C(aclk), + .CE(1'b1), + .D(\active_cols_2_reg[7]_i_1_n_6 ), + .Q(active_cols_2[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \active_cols_2_reg[6] + (.C(aclk), + .CE(1'b1), + .D(\active_cols_2_reg[7]_i_1_n_5 ), + .Q(active_cols_2[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \active_cols_2_reg[7] + (.C(aclk), + .CE(1'b1), + .D(\active_cols_2_reg[7]_i_1_n_4 ), + .Q(active_cols_2[7]), + .R(1'b0)); + CARRY4 \active_cols_2_reg[7]_i_1 + (.CI(\active_cols_2_reg[3]_i_1_n_0 ), + .CO({\active_cols_2_reg[7]_i_1_n_0 ,\active_cols_2_reg[7]_i_1_n_1 ,\active_cols_2_reg[7]_i_1_n_2 ,\active_cols_2_reg[7]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\active_cols_2_reg[7]_i_1_n_4 ,\active_cols_2_reg[7]_i_1_n_5 ,\active_cols_2_reg[7]_i_1_n_6 ,\active_cols_2_reg[7]_i_1_n_7 }), + .S({\active_cols_2[7]_i_2_n_0 ,\active_cols_2[7]_i_3_n_0 ,\active_cols_2[7]_i_4_n_0 ,\active_cols_2[7]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \active_cols_2_reg[8] + (.C(aclk), + .CE(1'b1), + .D(\active_cols_2_reg[11]_i_1_n_7 ), + .Q(active_cols_2[8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \active_cols_2_reg[9] + (.C(aclk), + .CE(1'b1), + .D(\active_cols_2_reg[11]_i_1_n_6 ), + .Q(active_cols_2[9]), + .R(1'b0)); + LUT3 #( + .INIT(8'hB8)) + \col_cnt[0]_i_1 + (.I0(\col_cnt[0]_i_2_n_0 ), + .I1(\write_ptr_int_reg[2] ), + .I2(\col_cnt_reg_n_0_[0] ), + .O(\col_cnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'hEFAAEFAAEAAAEFAA)) + \col_cnt[0]_i_2 + (.I0(\col_cnt[1]_i_4_n_0 ), + .I1(active_cols_2[0]), + .I2(eol_late_i3_out), + .I3(\row_cnt[0]_i_4_n_0 ), + .I4(\col_cnt_reg_n_0_[0] ), + .I5(geqOp), + .O(\col_cnt[0]_i_2_n_0 )); + LUT4 #( + .INIT(16'hA808)) + \col_cnt[10]_i_1 + (.I0(\col_cnt[12]_i_4_n_0 ), + .I1(data1[10]), + .I2(eol_late_i3_out), + .I3(active_cols_2[10]), + .O(\col_cnt[10]_i_1_n_0 )); + LUT4 #( + .INIT(16'hA808)) + \col_cnt[11]_i_1 + (.I0(\col_cnt[12]_i_4_n_0 ), + .I1(data1[11]), + .I2(eol_late_i3_out), + .I3(active_cols_2[11]), + .O(\col_cnt[11]_i_1_n_0 )); + LUT3 #( + .INIT(8'h4F)) + \col_cnt[12]_i_1 + (.I0(\col_cnt[12]_i_4_n_0 ), + .I1(\write_ptr_int_reg[2] ), + .I2(resetn_out), + .O(\col_cnt[12]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAAAA0800AAAA0A0A)) + \col_cnt[12]_i_15 + (.I0(\word_count_reg[4] ), + .I1(fifo_rd_i), + .I2(\col_cnt_reg[1]_0 ), + .I3(\genr_control_regs[0] [1]), + .I4(\col_cnt[12]_i_20_n_0 ), + .I5(in_fifo_reset_i_3_n_0), + .O(\col_cnt[12]_i_15_n_0 )); + LUT1 #( + .INIT(2'h2)) + \col_cnt[12]_i_16 + (.I0(\col_cnt_reg_n_0_[12] ), + .O(\col_cnt[12]_i_16_n_0 )); + LUT1 #( + .INIT(2'h2)) + \col_cnt[12]_i_17 + (.I0(\col_cnt_reg_n_0_[11] ), + .O(\col_cnt[12]_i_17_n_0 )); + LUT1 #( + .INIT(2'h2)) + \col_cnt[12]_i_18 + (.I0(\col_cnt_reg_n_0_[10] ), + .O(\col_cnt[12]_i_18_n_0 )); + LUT1 #( + .INIT(2'h2)) + \col_cnt[12]_i_19 + (.I0(\col_cnt_reg_n_0_[9] ), + .O(\col_cnt[12]_i_19_n_0 )); + LUT6 #( + .INIT(64'h8080808000808080)) + \col_cnt[12]_i_20 + (.I0(aclken), + .I1(\genr_control_regs[0] [0]), + .I2(fifo_rd_i), + .I3(in_fifo_reset), + .I4(t_qb[0]), + .I5(eol_expected_d), + .O(\col_cnt[12]_i_20_n_0 )); + LUT4 #( + .INIT(16'hA808)) + \col_cnt[12]_i_3 + (.I0(\col_cnt[12]_i_4_n_0 ), + .I1(data1[12]), + .I2(eol_late_i3_out), + .I3(active_cols_2[12]), + .O(\col_cnt[12]_i_3_n_0 )); + LUT3 #( + .INIT(8'h8A)) + \col_cnt[12]_i_4 + (.I0(\row_cnt[0]_i_4_n_0 ), + .I1(eol_late_i3_out), + .I2(geqOp), + .O(\col_cnt[12]_i_4_n_0 )); + LUT6 #( + .INIT(64'h1515150015151515)) + \col_cnt[12]_i_7 + (.I0(gtOp21_in), + .I1(leqOp23_in), + .I2(gtOp22_in), + .I3(vid_empty), + .I4(\col_cnt[12]_i_15_n_0 ), + .I5(leqOp20_in), + .O(\col_cnt_reg[12]_0 )); + LUT6 #( + .INIT(64'hA0A0A0A0A0A0C000)) + \col_cnt[1]_i_1 + (.I0(\col_cnt_reg_n_0_[1] ), + .I1(\col_cnt[1]_i_2_n_0 ), + .I2(resetn_out), + .I3(\col_cnt[1]_i_3_n_0 ), + .I4(line_cnt_tc_i_3_n_0), + .I5(\col_cnt_reg[1]_0 ), + .O(\col_cnt[1]_i_1_n_0 )); + LUT5 #( + .INIT(32'hEFEAAAAA)) + \col_cnt[1]_i_2 + (.I0(\col_cnt[1]_i_4_n_0 ), + .I1(active_cols_2[1]), + .I2(eol_late_i3_out), + .I3(data1[1]), + .I4(\col_cnt[12]_i_4_n_0 ), + .O(\col_cnt[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFF3F55555555)) + \col_cnt[1]_i_3 + (.I0(sof_early_i_reg_0), + .I1(t_qb[1]), + .I2(in_fifo_reset), + .I3(sof_early_i_reg_1), + .I4(sof_expected), + .I5(fifo_rd_d), + .O(\col_cnt[1]_i_3_n_0 )); + LUT6 #( + .INIT(64'h00DCDCDC00D0D0D0)) + \col_cnt[1]_i_4 + (.I0(sof_early_i_reg_0), + .I1(fifo_rd_d), + .I2(sof_early_i_reg_1), + .I3(t_qb[1]), + .I4(in_fifo_reset), + .I5(sof_expected), + .O(\col_cnt[1]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT3 #( + .INIT(8'hB8)) + \col_cnt[2]_i_1 + (.I0(\col_cnt[2]_i_2_n_0 ), + .I1(\write_ptr_int_reg[2] ), + .I2(\col_cnt_reg_n_0_[2] ), + .O(\col_cnt[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hD555D5DDD555D555)) + \col_cnt[2]_i_2 + (.I0(\col_cnt[2]_i_3_n_0 ), + .I1(\row_cnt[0]_i_4_n_0 ), + .I2(active_cols_2[2]), + .I3(eol_late_i3_out), + .I4(geqOp), + .I5(data1[2]), + .O(\col_cnt[2]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT5 #( + .INIT(32'hB0BBBBBB)) + \col_cnt[2]_i_3 + (.I0(fifo_rd_d), + .I1(sof_early_i_reg_0), + .I2(sof_expected), + .I3(in_fifo_reset), + .I4(t_qb[1]), + .O(\col_cnt[2]_i_3_n_0 )); + LUT4 #( + .INIT(16'hA808)) + \col_cnt[3]_i_1 + (.I0(\col_cnt[12]_i_4_n_0 ), + .I1(data1[3]), + .I2(eol_late_i3_out), + .I3(active_cols_2[3]), + .O(\col_cnt[3]_i_1_n_0 )); + LUT4 #( + .INIT(16'hA808)) + \col_cnt[4]_i_1 + (.I0(\col_cnt[12]_i_4_n_0 ), + .I1(data1[4]), + .I2(eol_late_i3_out), + .I3(active_cols_2[4]), + .O(\col_cnt[4]_i_1_n_0 )); + LUT1 #( + .INIT(2'h2)) + \col_cnt[4]_i_3 + (.I0(\col_cnt_reg_n_0_[4] ), + .O(\col_cnt[4]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \col_cnt[4]_i_4 + (.I0(\col_cnt_reg_n_0_[3] ), + .O(\col_cnt[4]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \col_cnt[4]_i_5 + (.I0(\col_cnt_reg_n_0_[2] ), + .O(\col_cnt[4]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \col_cnt[4]_i_6 + (.I0(\col_cnt_reg_n_0_[1] ), + .O(\col_cnt[4]_i_6_n_0 )); + LUT4 #( + .INIT(16'hA808)) + \col_cnt[5]_i_1 + (.I0(\col_cnt[12]_i_4_n_0 ), + .I1(data1[5]), + .I2(eol_late_i3_out), + .I3(active_cols_2[5]), + .O(\col_cnt[5]_i_1_n_0 )); + LUT4 #( + .INIT(16'hA808)) + \col_cnt[6]_i_1 + (.I0(\col_cnt[12]_i_4_n_0 ), + .I1(data1[6]), + .I2(eol_late_i3_out), + .I3(active_cols_2[6]), + .O(\col_cnt[6]_i_1_n_0 )); + LUT4 #( + .INIT(16'hA808)) + \col_cnt[7]_i_1 + (.I0(\col_cnt[12]_i_4_n_0 ), + .I1(data1[7]), + .I2(eol_late_i3_out), + .I3(active_cols_2[7]), + .O(\col_cnt[7]_i_1_n_0 )); + LUT4 #( + .INIT(16'hA808)) + \col_cnt[8]_i_1 + (.I0(\col_cnt[12]_i_4_n_0 ), + .I1(data1[8]), + .I2(eol_late_i3_out), + .I3(active_cols_2[8]), + .O(\col_cnt[8]_i_1_n_0 )); + LUT1 #( + .INIT(2'h2)) + \col_cnt[8]_i_3 + (.I0(\col_cnt_reg_n_0_[8] ), + .O(\col_cnt[8]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \col_cnt[8]_i_4 + (.I0(\col_cnt_reg_n_0_[7] ), + .O(\col_cnt[8]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \col_cnt[8]_i_5 + (.I0(\col_cnt_reg_n_0_[6] ), + .O(\col_cnt[8]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \col_cnt[8]_i_6 + (.I0(\col_cnt_reg_n_0_[5] ), + .O(\col_cnt[8]_i_6_n_0 )); + LUT4 #( + .INIT(16'hA808)) + \col_cnt[9]_i_1 + (.I0(\col_cnt[12]_i_4_n_0 ), + .I1(data1[9]), + .I2(eol_late_i3_out), + .I3(active_cols_2[9]), + .O(\col_cnt[9]_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \col_cnt_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\col_cnt[0]_i_1_n_0 ), + .Q(\col_cnt_reg_n_0_[0] ), + .S(SR)); + FDRE #( + .INIT(1'b0)) + \col_cnt_reg[10] + (.C(aclk), + .CE(\write_ptr_int_reg[2] ), + .D(\col_cnt[10]_i_1_n_0 ), + .Q(\col_cnt_reg_n_0_[10] ), + .R(\col_cnt[12]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \col_cnt_reg[11] + (.C(aclk), + .CE(\write_ptr_int_reg[2] ), + .D(\col_cnt[11]_i_1_n_0 ), + .Q(\col_cnt_reg_n_0_[11] ), + .R(\col_cnt[12]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \col_cnt_reg[12] + (.C(aclk), + .CE(\write_ptr_int_reg[2] ), + .D(\col_cnt[12]_i_3_n_0 ), + .Q(\col_cnt_reg_n_0_[12] ), + .R(\col_cnt[12]_i_1_n_0 )); + CARRY4 \col_cnt_reg[12]_i_9 + (.CI(\col_cnt_reg[8]_i_2_n_0 ), + .CO({\NLW_col_cnt_reg[12]_i_9_CO_UNCONNECTED [3],\col_cnt_reg[12]_i_9_n_1 ,\col_cnt_reg[12]_i_9_n_2 ,\col_cnt_reg[12]_i_9_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(data1[12:9]), + .S({\col_cnt[12]_i_16_n_0 ,\col_cnt[12]_i_17_n_0 ,\col_cnt[12]_i_18_n_0 ,\col_cnt[12]_i_19_n_0 })); + FDRE #( + .INIT(1'b0)) + \col_cnt_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\col_cnt[1]_i_1_n_0 ), + .Q(\col_cnt_reg_n_0_[1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \col_cnt_reg[2] + (.C(aclk), + .CE(1'b1), + .D(\col_cnt[2]_i_1_n_0 ), + .Q(\col_cnt_reg_n_0_[2] ), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \col_cnt_reg[3] + (.C(aclk), + .CE(\write_ptr_int_reg[2] ), + .D(\col_cnt[3]_i_1_n_0 ), + .Q(\col_cnt_reg_n_0_[3] ), + .R(\col_cnt[12]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \col_cnt_reg[4] + (.C(aclk), + .CE(\write_ptr_int_reg[2] ), + .D(\col_cnt[4]_i_1_n_0 ), + .Q(\col_cnt_reg_n_0_[4] ), + .R(\col_cnt[12]_i_1_n_0 )); + CARRY4 \col_cnt_reg[4]_i_2 + (.CI(1'b0), + .CO({\col_cnt_reg[4]_i_2_n_0 ,\col_cnt_reg[4]_i_2_n_1 ,\col_cnt_reg[4]_i_2_n_2 ,\col_cnt_reg[4]_i_2_n_3 }), + .CYINIT(\col_cnt_reg_n_0_[0] ), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(data1[4:1]), + .S({\col_cnt[4]_i_3_n_0 ,\col_cnt[4]_i_4_n_0 ,\col_cnt[4]_i_5_n_0 ,\col_cnt[4]_i_6_n_0 })); + FDRE #( + .INIT(1'b0)) + \col_cnt_reg[5] + (.C(aclk), + .CE(\write_ptr_int_reg[2] ), + .D(\col_cnt[5]_i_1_n_0 ), + .Q(\col_cnt_reg_n_0_[5] ), + .R(\col_cnt[12]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \col_cnt_reg[6] + (.C(aclk), + .CE(\write_ptr_int_reg[2] ), + .D(\col_cnt[6]_i_1_n_0 ), + .Q(\col_cnt_reg_n_0_[6] ), + .R(\col_cnt[12]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \col_cnt_reg[7] + (.C(aclk), + .CE(\write_ptr_int_reg[2] ), + .D(\col_cnt[7]_i_1_n_0 ), + .Q(\col_cnt_reg_n_0_[7] ), + .R(\col_cnt[12]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \col_cnt_reg[8] + (.C(aclk), + .CE(\write_ptr_int_reg[2] ), + .D(\col_cnt[8]_i_1_n_0 ), + .Q(\col_cnt_reg_n_0_[8] ), + .R(\col_cnt[12]_i_1_n_0 )); + CARRY4 \col_cnt_reg[8]_i_2 + (.CI(\col_cnt_reg[4]_i_2_n_0 ), + .CO({\col_cnt_reg[8]_i_2_n_0 ,\col_cnt_reg[8]_i_2_n_1 ,\col_cnt_reg[8]_i_2_n_2 ,\col_cnt_reg[8]_i_2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(data1[8:5]), + .S({\col_cnt[8]_i_3_n_0 ,\col_cnt[8]_i_4_n_0 ,\col_cnt[8]_i_5_n_0 ,\col_cnt[8]_i_6_n_0 })); + FDRE #( + .INIT(1'b0)) + \col_cnt_reg[9] + (.C(aclk), + .CE(\write_ptr_int_reg[2] ), + .D(\col_cnt[9]_i_1_n_0 ), + .Q(\col_cnt_reg_n_0_[9] ), + .R(\col_cnt[12]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00C0A0A0A0A0A0A0)) + core_en_i_i_1 + (.I0(core_en_i), + .I1(gtOp), + .I2(resetn_out), + .I3(line_cnt_tc_i_3_n_0), + .I4(\genr_control_regs[0] [0]), + .I5(aclken), + .O(core_en_i_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + core_en_i_reg + (.C(aclk), + .CE(1'b1), + .D(core_en_i_i_1_n_0), + .Q(core_en_i), + .R(1'b0)); + LUT6 #( + .INIT(64'hAAAAAAAA00C0AAAA)) + eof_i_i_1 + (.I0(intc_if[0]), + .I1(eqOp1_out), + .I2(eqOp_0), + .I3(line_cnt_tc_i_3_n_0), + .I4(resetn_out), + .I5(\col_cnt_reg[1]_0 ), + .O(eof_i_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + eof_i_reg + (.C(aclk), + .CE(1'b1), + .D(eof_i_i_1_n_0), + .Q(intc_if[0]), + .R(1'b0)); + LUT6 #( + .INIT(64'hA0A000C0A0A0A0A0)) + eol_early_i_i_1 + (.I0(intc_if[4]), + .I1(eol_early_i0), + .I2(resetn_out), + .I3(eol_expected_d), + .I4(\col_cnt_reg[1]_0 ), + .I5(fifo_rd_d), + .O(eol_early_i_i_1_n_0)); + LUT6 #( + .INIT(64'hA1A1A1A1000000A1)) + eol_early_i_i_2 + (.I0(eol_early_i_i_4_n_0), + .I1(sof_early_i_reg_1), + .I2(sof_expected), + .I3(eol_late_i_reg_0), + .I4(eol_late_i_i_2_n_0), + .I5(intc_if[4]), + .O(eol_early_i0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT2 #( + .INIT(4'h7)) + eol_early_i_i_3 + (.I0(aclken), + .I1(\genr_control_regs[0] [0]), + .O(\col_cnt_reg[1]_0 )); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h8)) + eol_early_i_i_4 + (.I0(in_fifo_reset), + .I1(t_qb[1]), + .O(eol_early_i_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + eol_early_i_reg + (.C(aclk), + .CE(1'b1), + .D(eol_early_i_i_1_n_0), + .Q(intc_if[4]), + .R(1'b0)); + LUT5 #( + .INIT(32'hBFFF8000)) + eol_expected_d_i_1 + (.I0(eol_expected), + .I1(fifo_rd_i), + .I2(\genr_control_regs[0] [0]), + .I3(aclken), + .I4(eol_expected_d), + .O(eol_expected_d_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + eol_expected_d_reg + (.C(aclk), + .CE(1'b1), + .D(eol_expected_d_i_1_n_0), + .Q(eol_expected_d), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h2A)) + eol_expected_i_1 + (.I0(eqOp0_out), + .I1(t_qb[1]), + .I2(in_fifo_reset), + .O(eol_expected0)); + FDRE #( + .INIT(1'b0)) + eol_expected_reg + (.C(aclk), + .CE(master_en), + .D(eol_expected0), + .Q(eol_expected), + .R(SR)); + LUT6 #( + .INIT(64'h0AAA8AAA00008000)) + eol_late_i_i_1 + (.I0(eol_late_i_i_2_n_0), + .I1(eol_late_i_i_3_n_0), + .I2(fifo_rd_d), + .I3(eol_expected_d), + .I4(intc_if[4]), + .I5(eol_late_i_reg_0), + .O(eol_late_i3_out)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT2 #( + .INIT(4'h7)) + eol_late_i_i_2 + (.I0(in_fifo_reset), + .I1(t_qb[0]), + .O(eol_late_i_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT4 #( + .INIT(16'hA111)) + eol_late_i_i_3 + (.I0(sof_expected), + .I1(sof_early_i_reg_1), + .I2(in_fifo_reset), + .I3(t_qb[1]), + .O(eol_late_i_i_3_n_0)); + FDRE #( + .INIT(1'b0)) + eol_late_i_reg + (.C(aclk), + .CE(master_en), + .D(eol_late_i3_out), + .Q(eol_late_i_reg_0), + .R(SR)); + CARRY4 eqOp_carry + (.CI(1'b0), + .CO({eqOp_carry_n_0,eqOp_carry_n_1,eqOp_carry_n_2,eqOp_carry_n_3}), + .CYINIT(1'b1), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(NLW_eqOp_carry_O_UNCONNECTED[3:0]), + .S({eqOp_carry_i_1_n_0,eqOp_carry_i_2_n_0,eqOp_carry_i_3_n_0,eqOp_carry_i_4_n_0})); + CARRY4 eqOp_carry__0 + (.CI(eqOp_carry_n_0), + .CO({NLW_eqOp_carry__0_CO_UNCONNECTED[3:1],eqOp0_out}), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(NLW_eqOp_carry__0_O_UNCONNECTED[3:0]), + .S({1'b0,1'b0,1'b0,eqOp_carry__0_i_1_n_0})); + LUT2 #( + .INIT(4'h9)) + eqOp_carry__0_i_1 + (.I0(\time_control_regs[0] [12]), + .I1(\col_cnt_reg_n_0_[12] ), + .O(eqOp_carry__0_i_1_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + eqOp_carry_i_1 + (.I0(\col_cnt_reg_n_0_[10] ), + .I1(\time_control_regs[0] [10]), + .I2(\col_cnt_reg_n_0_[11] ), + .I3(\time_control_regs[0] [11]), + .I4(\time_control_regs[0] [9]), + .I5(\col_cnt_reg_n_0_[9] ), + .O(eqOp_carry_i_1_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + eqOp_carry_i_2 + (.I0(\col_cnt_reg_n_0_[7] ), + .I1(\time_control_regs[0] [7]), + .I2(\col_cnt_reg_n_0_[6] ), + .I3(\time_control_regs[0] [6]), + .I4(\time_control_regs[0] [8]), + .I5(\col_cnt_reg_n_0_[8] ), + .O(eqOp_carry_i_2_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + eqOp_carry_i_3 + (.I0(\col_cnt_reg_n_0_[4] ), + .I1(\time_control_regs[0] [4]), + .I2(\col_cnt_reg_n_0_[5] ), + .I3(\time_control_regs[0] [5]), + .I4(\time_control_regs[0] [3]), + .I5(\col_cnt_reg_n_0_[3] ), + .O(eqOp_carry_i_3_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + eqOp_carry_i_4 + (.I0(\col_cnt_reg_n_0_[1] ), + .I1(\time_control_regs[0] [1]), + .I2(\col_cnt_reg_n_0_[0] ), + .I3(\time_control_regs[0] [0]), + .I4(\time_control_regs[0] [2]), + .I5(\col_cnt_reg_n_0_[2] ), + .O(eqOp_carry_i_4_n_0)); + CARRY4 \eqOp_inferred__3/i__carry + (.CI(1'b0), + .CO({\eqOp_inferred__3/i__carry_n_0 ,\eqOp_inferred__3/i__carry_n_1 ,\eqOp_inferred__3/i__carry_n_2 ,\eqOp_inferred__3/i__carry_n_3 }), + .CYINIT(1'b1), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_eqOp_inferred__3/i__carry_O_UNCONNECTED [3:0]), + .S({i__carry_i_1__0_n_0,i__carry_i_2__0_n_0,i__carry_i_3__0_n_0,i__carry_i_4_n_0})); + CARRY4 \eqOp_inferred__3/i__carry__0 + (.CI(\eqOp_inferred__3/i__carry_n_0 ), + .CO({\NLW_eqOp_inferred__3/i__carry__0_CO_UNCONNECTED [3:1],eqOp1_out}), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_eqOp_inferred__3/i__carry__0_O_UNCONNECTED [3:0]), + .S({1'b0,1'b0,1'b0,i__carry__0_i_1__5_n_0})); + CARRY4 \eqOp_inferred__4/i__carry + (.CI(1'b0), + .CO({\eqOp_inferred__4/i__carry_n_0 ,\eqOp_inferred__4/i__carry_n_1 ,\eqOp_inferred__4/i__carry_n_2 ,\eqOp_inferred__4/i__carry_n_3 }), + .CYINIT(1'b1), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_eqOp_inferred__4/i__carry_O_UNCONNECTED [3:0]), + .S({i__carry_i_1__1_n_0,i__carry_i_2__1_n_0,i__carry_i_3__1_n_0,i__carry_i_4__1_n_0})); + CARRY4 \eqOp_inferred__4/i__carry__0 + (.CI(\eqOp_inferred__4/i__carry_n_0 ), + .CO({\NLW_eqOp_inferred__4/i__carry__0_CO_UNCONNECTED [3:1],eqOp_0}), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_eqOp_inferred__4/i__carry__0_O_UNCONNECTED [3:0]), + .S({1'b0,1'b0,1'b0,i__carry__0_i_1__6_n_0})); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'hBFFF8000)) + fifo_rd_d_i_1 + (.I0(fifo_rd_i), + .I1(resetn_out), + .I2(\genr_control_regs[0] [0]), + .I3(aclken), + .I4(fifo_rd_d), + .O(fifo_rd_d_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + fifo_rd_d_reg + (.C(aclk), + .CE(1'b1), + .D(fifo_rd_d_i_1_n_0), + .Q(fifo_rd_d), + .R(1'b0)); + LUT6 #( + .INIT(64'h00C0A0A0A0A0A0A0)) + fifo_rd_i_i_1 + (.I0(fifo_rd_i), + .I1(fifo_rd_i0), + .I2(resetn_out), + .I3(line_cnt_tc_i_3_n_0), + .I4(\genr_control_regs[0] [0]), + .I5(aclken), + .O(fifo_rd_i_i_1_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFFFFECECEC)) + fifo_rd_i_i_2 + (.I0(fifo_rd_d), + .I1(sof_early_i_reg_1), + .I2(sof_expected), + .I3(leqOp20_in), + .I4(leqOp16_in), + .I5(eol_early_i_i_4_n_0), + .O(fifo_rd_i0)); + FDRE #( + .INIT(1'b0)) + fifo_rd_i_reg + (.C(aclk), + .CE(1'b1), + .D(fifo_rd_i_i_1_n_0), + .Q(fifo_rd_i), + .R(1'b0)); + LUT6 #( + .INIT(64'hAA00AA000000C000)) + fifo_wr_i_i_1 + (.I0(fifo_wr_i), + .I1(gtOp18_in), + .I2(gtOp19_in), + .I3(resetn_out), + .I4(line_cnt_tc_i_3_n_0), + .I5(\col_cnt_reg[1]_0 ), + .O(fifo_wr_i_i_1_n_0)); + LUT2 #( + .INIT(4'hE)) + fifo_wr_i_i_10 + (.I0(\col_cnt_reg_n_0_[5] ), + .I1(\col_cnt_reg_n_0_[4] ), + .O(fifo_wr_i_i_10_n_0)); + LUT2 #( + .INIT(4'h1)) + fifo_wr_i_i_11 + (.I0(\col_cnt_reg_n_0_[6] ), + .I1(\col_cnt_reg_n_0_[7] ), + .O(fifo_wr_i_i_11_n_0)); + LUT2 #( + .INIT(4'h1)) + fifo_wr_i_i_12 + (.I0(\col_cnt_reg_n_0_[4] ), + .I1(\col_cnt_reg_n_0_[5] ), + .O(fifo_wr_i_i_12_n_0)); + LUT2 #( + .INIT(4'h8)) + fifo_wr_i_i_13 + (.I0(\col_cnt_reg_n_0_[2] ), + .I1(\col_cnt_reg_n_0_[3] ), + .O(fifo_wr_i_i_13_n_0)); + LUT2 #( + .INIT(4'h2)) + fifo_wr_i_i_14 + (.I0(\col_cnt_reg_n_0_[0] ), + .I1(\col_cnt_reg_n_0_[1] ), + .O(fifo_wr_i_i_14_n_0)); + LUT2 #( + .INIT(4'hE)) + fifo_wr_i_i_4 + (.I0(\col_cnt_reg_n_0_[11] ), + .I1(\col_cnt_reg_n_0_[10] ), + .O(fifo_wr_i_i_4_n_0)); + LUT2 #( + .INIT(4'hE)) + fifo_wr_i_i_5 + (.I0(\col_cnt_reg_n_0_[9] ), + .I1(\col_cnt_reg_n_0_[8] ), + .O(fifo_wr_i_i_5_n_0)); + LUT1 #( + .INIT(2'h1)) + fifo_wr_i_i_6 + (.I0(\col_cnt_reg_n_0_[12] ), + .O(fifo_wr_i_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + fifo_wr_i_i_7 + (.I0(\col_cnt_reg_n_0_[10] ), + .I1(\col_cnt_reg_n_0_[11] ), + .O(fifo_wr_i_i_7_n_0)); + LUT2 #( + .INIT(4'h1)) + fifo_wr_i_i_8 + (.I0(\col_cnt_reg_n_0_[8] ), + .I1(\col_cnt_reg_n_0_[9] ), + .O(fifo_wr_i_i_8_n_0)); + LUT2 #( + .INIT(4'hE)) + fifo_wr_i_i_9 + (.I0(\col_cnt_reg_n_0_[7] ), + .I1(\col_cnt_reg_n_0_[6] ), + .O(fifo_wr_i_i_9_n_0)); + FDRE #( + .INIT(1'b0)) + fifo_wr_i_reg + (.C(aclk), + .CE(1'b1), + .D(fifo_wr_i_i_1_n_0), + .Q(fifo_wr_i), + .R(1'b0)); + CARRY4 fifo_wr_i_reg_i_2 + (.CI(fifo_wr_i_reg_i_3_n_0), + .CO({NLW_fifo_wr_i_reg_i_2_CO_UNCONNECTED[3],gtOp19_in,fifo_wr_i_reg_i_2_n_2,fifo_wr_i_reg_i_2_n_3}), + .CYINIT(1'b0), + .DI({1'b0,\col_cnt_reg_n_0_[12] ,fifo_wr_i_i_4_n_0,fifo_wr_i_i_5_n_0}), + .O(NLW_fifo_wr_i_reg_i_2_O_UNCONNECTED[3:0]), + .S({1'b0,fifo_wr_i_i_6_n_0,fifo_wr_i_i_7_n_0,fifo_wr_i_i_8_n_0})); + CARRY4 fifo_wr_i_reg_i_3 + (.CI(1'b0), + .CO({fifo_wr_i_reg_i_3_n_0,fifo_wr_i_reg_i_3_n_1,fifo_wr_i_reg_i_3_n_2,fifo_wr_i_reg_i_3_n_3}), + .CYINIT(1'b0), + .DI({fifo_wr_i_i_9_n_0,fifo_wr_i_i_10_n_0,1'b0,\col_cnt_reg_n_0_[1] }), + .O(NLW_fifo_wr_i_reg_i_3_O_UNCONNECTED[3:0]), + .S({fifo_wr_i_i_11_n_0,fifo_wr_i_i_12_n_0,fifo_wr_i_i_13_n_0,fifo_wr_i_i_14_n_0})); + CARRY4 geqOp_carry + (.CI(1'b0), + .CO({geqOp_carry_n_0,geqOp_carry_n_1,geqOp_carry_n_2,geqOp_carry_n_3}), + .CYINIT(1'b1), + .DI({geqOp_carry_i_1_n_0,geqOp_carry_i_2_n_0,geqOp_carry_i_3_n_0,geqOp_carry_i_4_n_0}), + .O(NLW_geqOp_carry_O_UNCONNECTED[3:0]), + .S({geqOp_carry_i_5_n_0,geqOp_carry_i_6_n_0,geqOp_carry_i_7_n_0,geqOp_carry_i_8_n_0})); + CARRY4 geqOp_carry__0 + (.CI(geqOp_carry_n_0), + .CO({NLW_geqOp_carry__0_CO_UNCONNECTED[3],geqOp,geqOp_carry__0_n_2,geqOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({1'b0,geqOp_carry__0_i_1_n_0,geqOp_carry__0_i_2_n_0,geqOp_carry__0_i_3_n_0}), + .O(NLW_geqOp_carry__0_O_UNCONNECTED[3:0]), + .S({1'b0,geqOp_carry__0_i_4_n_0,geqOp_carry__0_i_5_n_0,geqOp_carry__0_i_6_n_0})); + LUT2 #( + .INIT(4'h2)) + geqOp_carry__0_i_1 + (.I0(\col_cnt_reg_n_0_[12] ), + .I1(total_cols[12]), + .O(geqOp_carry__0_i_1_n_0)); + LUT4 #( + .INIT(16'h2F02)) + geqOp_carry__0_i_2 + (.I0(\col_cnt_reg_n_0_[10] ), + .I1(total_cols[10]), + .I2(total_cols[11]), + .I3(\col_cnt_reg_n_0_[11] ), + .O(geqOp_carry__0_i_2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + geqOp_carry__0_i_3 + (.I0(\col_cnt_reg_n_0_[8] ), + .I1(total_cols[8]), + .I2(total_cols[9]), + .I3(\col_cnt_reg_n_0_[9] ), + .O(geqOp_carry__0_i_3_n_0)); + LUT2 #( + .INIT(4'h9)) + geqOp_carry__0_i_4 + (.I0(total_cols[12]), + .I1(\col_cnt_reg_n_0_[12] ), + .O(geqOp_carry__0_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + geqOp_carry__0_i_5 + (.I0(total_cols[10]), + .I1(\col_cnt_reg_n_0_[10] ), + .I2(\col_cnt_reg_n_0_[11] ), + .I3(total_cols[11]), + .O(geqOp_carry__0_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + geqOp_carry__0_i_6 + (.I0(total_cols[9]), + .I1(\col_cnt_reg_n_0_[9] ), + .I2(total_cols[8]), + .I3(\col_cnt_reg_n_0_[8] ), + .O(geqOp_carry__0_i_6_n_0)); + LUT4 #( + .INIT(16'h2F02)) + geqOp_carry_i_1 + (.I0(\col_cnt_reg_n_0_[6] ), + .I1(total_cols[6]), + .I2(total_cols[7]), + .I3(\col_cnt_reg_n_0_[7] ), + .O(geqOp_carry_i_1_n_0)); + LUT4 #( + .INIT(16'h2F02)) + geqOp_carry_i_2 + (.I0(\col_cnt_reg_n_0_[4] ), + .I1(total_cols[4]), + .I2(total_cols[5]), + .I3(\col_cnt_reg_n_0_[5] ), + .O(geqOp_carry_i_2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + geqOp_carry_i_3 + (.I0(\col_cnt_reg_n_0_[2] ), + .I1(total_cols[2]), + .I2(total_cols[3]), + .I3(\col_cnt_reg_n_0_[3] ), + .O(geqOp_carry_i_3_n_0)); + LUT4 #( + .INIT(16'h2F02)) + geqOp_carry_i_4 + (.I0(\col_cnt_reg_n_0_[0] ), + .I1(total_cols[0]), + .I2(total_cols[1]), + .I3(\col_cnt_reg_n_0_[1] ), + .O(geqOp_carry_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + geqOp_carry_i_5 + (.I0(total_cols[6]), + .I1(\col_cnt_reg_n_0_[6] ), + .I2(\col_cnt_reg_n_0_[7] ), + .I3(total_cols[7]), + .O(geqOp_carry_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + geqOp_carry_i_6 + (.I0(total_cols[4]), + .I1(\col_cnt_reg_n_0_[4] ), + .I2(\col_cnt_reg_n_0_[5] ), + .I3(total_cols[5]), + .O(geqOp_carry_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + geqOp_carry_i_7 + (.I0(total_cols[3]), + .I1(\col_cnt_reg_n_0_[3] ), + .I2(total_cols[2]), + .I3(\col_cnt_reg_n_0_[2] ), + .O(geqOp_carry_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + geqOp_carry_i_8 + (.I0(total_cols[0]), + .I1(\col_cnt_reg_n_0_[0] ), + .I2(\col_cnt_reg_n_0_[1] ), + .I3(total_cols[1]), + .O(geqOp_carry_i_8_n_0)); + CARRY4 gtOp_carry + (.CI(1'b0), + .CO({gtOp_carry_n_0,gtOp_carry_n_1,gtOp_carry_n_2,gtOp_carry_n_3}), + .CYINIT(1'b0), + .DI({gtOp_carry_i_1_n_0,gtOp_carry_i_2_n_0,gtOp_carry_i_3_n_0,gtOp_carry_i_4_n_0}), + .O(NLW_gtOp_carry_O_UNCONNECTED[3:0]), + .S({gtOp_carry_i_5_n_0,gtOp_carry_i_6_n_0,gtOp_carry_i_7_n_0,gtOp_carry_i_8_n_0})); + CARRY4 gtOp_carry__0 + (.CI(gtOp_carry_n_0), + .CO({NLW_gtOp_carry__0_CO_UNCONNECTED[3],gtOp22_in,gtOp_carry__0_n_2,gtOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({1'b0,gtOp_carry__0_i_1_n_0,gtOp_carry__0_i_2_n_0,gtOp_carry__0_i_3_n_0}), + .O(NLW_gtOp_carry__0_O_UNCONNECTED[3:0]), + .S({1'b0,gtOp_carry__0_i_4_n_0,gtOp_carry__0_i_5_n_0,gtOp_carry__0_i_6_n_0})); + LUT2 #( + .INIT(4'h2)) + gtOp_carry__0_i_1 + (.I0(\col_cnt_reg_n_0_[12] ), + .I1(\time_control_regs[0] [12]), + .O(gtOp_carry__0_i_1_n_0)); + LUT4 #( + .INIT(16'h2B22)) + gtOp_carry__0_i_2 + (.I0(\col_cnt_reg_n_0_[11] ), + .I1(\time_control_regs[0] [11]), + .I2(\time_control_regs[0] [10]), + .I3(\col_cnt_reg_n_0_[10] ), + .O(gtOp_carry__0_i_2_n_0)); + LUT4 #( + .INIT(16'h40F4)) + gtOp_carry__0_i_3 + (.I0(\time_control_regs[0] [8]), + .I1(\col_cnt_reg_n_0_[8] ), + .I2(\col_cnt_reg_n_0_[9] ), + .I3(\time_control_regs[0] [9]), + .O(gtOp_carry__0_i_3_n_0)); + LUT2 #( + .INIT(4'h9)) + gtOp_carry__0_i_4 + (.I0(\time_control_regs[0] [12]), + .I1(\col_cnt_reg_n_0_[12] ), + .O(gtOp_carry__0_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + gtOp_carry__0_i_5 + (.I0(\time_control_regs[0] [11]), + .I1(\col_cnt_reg_n_0_[11] ), + .I2(\time_control_regs[0] [10]), + .I3(\col_cnt_reg_n_0_[10] ), + .O(gtOp_carry__0_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + gtOp_carry__0_i_6 + (.I0(\time_control_regs[0] [8]), + .I1(\col_cnt_reg_n_0_[8] ), + .I2(\time_control_regs[0] [9]), + .I3(\col_cnt_reg_n_0_[9] ), + .O(gtOp_carry__0_i_6_n_0)); + LUT4 #( + .INIT(16'h2B22)) + gtOp_carry_i_1 + (.I0(\col_cnt_reg_n_0_[7] ), + .I1(\time_control_regs[0] [7]), + .I2(\time_control_regs[0] [6]), + .I3(\col_cnt_reg_n_0_[6] ), + .O(gtOp_carry_i_1_n_0)); + LUT4 #( + .INIT(16'h2B22)) + gtOp_carry_i_2 + (.I0(\col_cnt_reg_n_0_[5] ), + .I1(\time_control_regs[0] [5]), + .I2(\time_control_regs[0] [4]), + .I3(\col_cnt_reg_n_0_[4] ), + .O(gtOp_carry_i_2_n_0)); + LUT4 #( + .INIT(16'h40F4)) + gtOp_carry_i_3 + (.I0(\time_control_regs[0] [2]), + .I1(\col_cnt_reg_n_0_[2] ), + .I2(\col_cnt_reg_n_0_[3] ), + .I3(\time_control_regs[0] [3]), + .O(gtOp_carry_i_3_n_0)); + LUT4 #( + .INIT(16'h2B22)) + gtOp_carry_i_4 + (.I0(\col_cnt_reg_n_0_[1] ), + .I1(\time_control_regs[0] [1]), + .I2(\time_control_regs[0] [0]), + .I3(\col_cnt_reg_n_0_[0] ), + .O(gtOp_carry_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + gtOp_carry_i_5 + (.I0(\time_control_regs[0] [6]), + .I1(\col_cnt_reg_n_0_[6] ), + .I2(\time_control_regs[0] [7]), + .I3(\col_cnt_reg_n_0_[7] ), + .O(gtOp_carry_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + gtOp_carry_i_6 + (.I0(\time_control_regs[0] [5]), + .I1(\col_cnt_reg_n_0_[5] ), + .I2(\time_control_regs[0] [4]), + .I3(\col_cnt_reg_n_0_[4] ), + .O(gtOp_carry_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + gtOp_carry_i_7 + (.I0(\time_control_regs[0] [2]), + .I1(\col_cnt_reg_n_0_[2] ), + .I2(\time_control_regs[0] [3]), + .I3(\col_cnt_reg_n_0_[3] ), + .O(gtOp_carry_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + gtOp_carry_i_8 + (.I0(\time_control_regs[0] [0]), + .I1(\col_cnt_reg_n_0_[0] ), + .I2(\time_control_regs[0] [1]), + .I3(\col_cnt_reg_n_0_[1] ), + .O(gtOp_carry_i_8_n_0)); + CARRY4 \gtOp_inferred__0/i__carry + (.CI(1'b0), + .CO({\gtOp_inferred__0/i__carry_n_0 ,\gtOp_inferred__0/i__carry_n_1 ,\gtOp_inferred__0/i__carry_n_2 ,\gtOp_inferred__0/i__carry_n_3 }), + .CYINIT(1'b0), + .DI({i__carry_i_1__2_n_0,i__carry_i_2__2_n_0,i__carry_i_3__2_n_0,i__carry_i_4__2_n_0}), + .O(\NLW_gtOp_inferred__0/i__carry_O_UNCONNECTED [3:0]), + .S({i__carry_i_5__1_n_0,i__carry_i_6__3_n_0,i__carry_i_7__3_n_0,i__carry_i_8__2_n_0})); + CARRY4 \gtOp_inferred__0/i__carry__0 + (.CI(\gtOp_inferred__0/i__carry_n_0 ), + .CO({\NLW_gtOp_inferred__0/i__carry__0_CO_UNCONNECTED [3],gtOp21_in,\gtOp_inferred__0/i__carry__0_n_2 ,\gtOp_inferred__0/i__carry__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,i__carry__0_i_1__0_n_0,i__carry__0_i_2__0_n_0,i__carry__0_i_3__2_n_0}), + .O(\NLW_gtOp_inferred__0/i__carry__0_O_UNCONNECTED [3:0]), + .S({1'b0,i__carry__0_i_4__2_n_0,i__carry__0_i_5__2_n_0,i__carry__0_i_6__1_n_0})); + CARRY4 \gtOp_inferred__2/i__carry + (.CI(1'b0), + .CO({\gtOp_inferred__2/i__carry_n_0 ,\gtOp_inferred__2/i__carry_n_1 ,\gtOp_inferred__2/i__carry_n_2 ,\gtOp_inferred__2/i__carry_n_3 }), + .CYINIT(1'b0), + .DI({i__carry_i_1__5_n_0,i__carry_i_2__4_n_0,i__carry_i_3__4_n_0,i__carry_i_4__4_n_0}), + .O(\NLW_gtOp_inferred__2/i__carry_O_UNCONNECTED [3:0]), + .S({i__carry_i_5__3_n_0,i__carry_i_6__1_n_0,i__carry_i_7__1_n_0,i__carry_i_8__1_n_0})); + CARRY4 \gtOp_inferred__2/i__carry__0 + (.CI(\gtOp_inferred__2/i__carry_n_0 ), + .CO({\NLW_gtOp_inferred__2/i__carry__0_CO_UNCONNECTED [3],gtOp18_in,\gtOp_inferred__2/i__carry__0_n_2 ,\gtOp_inferred__2/i__carry__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,row_cnt_reg[12],i__carry__0_i_1__2_n_0,i__carry__0_i_2__2_n_0}), + .O(\NLW_gtOp_inferred__2/i__carry__0_O_UNCONNECTED [3:0]), + .S({1'b0,i__carry__0_i_3__0_n_0,i__carry__0_i_4__0_n_0,i__carry__0_i_5__1_n_0})); + CARRY4 \gtOp_inferred__3/i__carry + (.CI(1'b0), + .CO({\gtOp_inferred__3/i__carry_n_0 ,\gtOp_inferred__3/i__carry_n_1 ,\gtOp_inferred__3/i__carry_n_2 ,\gtOp_inferred__3/i__carry_n_3 }), + .CYINIT(1'b0), + .DI({i__carry_i_1__6_n_0,i__carry_i_2__5_n_0,i__carry_i_3__5_n_0,\col_cnt_reg_n_0_[1] }), + .O(\NLW_gtOp_inferred__3/i__carry_O_UNCONNECTED [3:0]), + .S({i__carry_i_4__6_n_0,i__carry_i_5__4_n_0,i__carry_i_6__2_n_0,i__carry_i_7__2_n_0})); + CARRY4 \gtOp_inferred__3/i__carry__0 + (.CI(\gtOp_inferred__3/i__carry_n_0 ), + .CO({\NLW_gtOp_inferred__3/i__carry__0_CO_UNCONNECTED [3],gtOp,\gtOp_inferred__3/i__carry__0_n_2 ,\gtOp_inferred__3/i__carry__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,\col_cnt_reg_n_0_[12] ,i__carry__0_i_1__3_n_0,i__carry__0_i_2__3_n_0}), + .O(\NLW_gtOp_inferred__3/i__carry__0_O_UNCONNECTED [3:0]), + .S({1'b0,i__carry__0_i_3__1_n_0,i__carry__0_i_4_n_0,i__carry__0_i_5__3_n_0})); + LUT2 #( + .INIT(4'h2)) + i__carry__0_i_1 + (.I0(total_cols[12]), + .I1(\col_cnt_reg_n_0_[12] ), + .O(i__carry__0_i_1_n_0)); + LUT2 #( + .INIT(4'h2)) + i__carry__0_i_1__0 + (.I0(row_cnt_reg[12]), + .I1(\time_control_regs[0] [25]), + .O(i__carry__0_i_1__0_n_0)); + LUT2 #( + .INIT(4'h2)) + i__carry__0_i_1__1 + (.I0(\time_control_regs[0] [25]), + .I1(row_cnt_reg[12]), + .O(i__carry__0_i_1__1_n_0)); + LUT2 #( + .INIT(4'hE)) + i__carry__0_i_1__2 + (.I0(row_cnt_reg[11]), + .I1(row_cnt_reg[10]), + .O(i__carry__0_i_1__2_n_0)); + LUT2 #( + .INIT(4'hE)) + i__carry__0_i_1__3 + (.I0(\col_cnt_reg_n_0_[11] ), + .I1(\col_cnt_reg_n_0_[10] ), + .O(i__carry__0_i_1__3_n_0)); + LUT1 #( + .INIT(2'h1)) + i__carry__0_i_1__4 + (.I0(\col_cnt_reg_n_0_[12] ), + .O(i__carry__0_i_1__4_n_0)); + LUT2 #( + .INIT(4'h9)) + i__carry__0_i_1__5 + (.I0(total_cols[12]), + .I1(\col_cnt_reg_n_0_[12] ), + .O(i__carry__0_i_1__5_n_0)); + LUT2 #( + .INIT(4'h9)) + i__carry__0_i_1__6 + (.I0(total_rows[12]), + .I1(row_cnt_reg[12]), + .O(i__carry__0_i_1__6_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry__0_i_2 + (.I0(total_cols[10]), + .I1(\col_cnt_reg_n_0_[10] ), + .I2(\col_cnt_reg_n_0_[11] ), + .I3(total_cols[11]), + .O(i__carry__0_i_2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry__0_i_2__0 + (.I0(row_cnt_reg[10]), + .I1(\time_control_regs[0] [23]), + .I2(\time_control_regs[0] [24]), + .I3(row_cnt_reg[11]), + .O(i__carry__0_i_2__0_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry__0_i_2__1 + (.I0(\time_control_regs[0] [23]), + .I1(row_cnt_reg[10]), + .I2(row_cnt_reg[11]), + .I3(\time_control_regs[0] [24]), + .O(i__carry__0_i_2__1_n_0)); + LUT2 #( + .INIT(4'hE)) + i__carry__0_i_2__2 + (.I0(row_cnt_reg[9]), + .I1(row_cnt_reg[8]), + .O(i__carry__0_i_2__2_n_0)); + LUT2 #( + .INIT(4'hE)) + i__carry__0_i_2__3 + (.I0(\col_cnt_reg_n_0_[9] ), + .I1(\col_cnt_reg_n_0_[8] ), + .O(i__carry__0_i_2__3_n_0)); + LUT2 #( + .INIT(4'h1)) + i__carry__0_i_2__4 + (.I0(\col_cnt_reg_n_0_[10] ), + .I1(\col_cnt_reg_n_0_[11] ), + .O(i__carry__0_i_2__4_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry__0_i_3 + (.I0(total_cols[8]), + .I1(\col_cnt_reg_n_0_[8] ), + .I2(\col_cnt_reg_n_0_[9] ), + .I3(total_cols[9]), + .O(i__carry__0_i_3_n_0)); + LUT1 #( + .INIT(2'h1)) + i__carry__0_i_3__0 + (.I0(row_cnt_reg[12]), + .O(i__carry__0_i_3__0_n_0)); + LUT1 #( + .INIT(2'h1)) + i__carry__0_i_3__1 + (.I0(\col_cnt_reg_n_0_[12] ), + .O(i__carry__0_i_3__1_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry__0_i_3__2 + (.I0(row_cnt_reg[8]), + .I1(\time_control_regs[0] [21]), + .I2(\time_control_regs[0] [22]), + .I3(row_cnt_reg[9]), + .O(i__carry__0_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry__0_i_3__3 + (.I0(\time_control_regs[0] [21]), + .I1(row_cnt_reg[8]), + .I2(row_cnt_reg[9]), + .I3(\time_control_regs[0] [22]), + .O(i__carry__0_i_3__3_n_0)); + LUT2 #( + .INIT(4'h1)) + i__carry__0_i_4 + (.I0(\col_cnt_reg_n_0_[10] ), + .I1(\col_cnt_reg_n_0_[11] ), + .O(i__carry__0_i_4_n_0)); + LUT2 #( + .INIT(4'h1)) + i__carry__0_i_4__0 + (.I0(row_cnt_reg[10]), + .I1(row_cnt_reg[11]), + .O(i__carry__0_i_4__0_n_0)); + LUT2 #( + .INIT(4'h9)) + i__carry__0_i_4__1 + (.I0(\col_cnt_reg_n_0_[12] ), + .I1(total_cols[12]), + .O(i__carry__0_i_4__1_n_0)); + LUT2 #( + .INIT(4'h9)) + i__carry__0_i_4__2 + (.I0(\time_control_regs[0] [25]), + .I1(row_cnt_reg[12]), + .O(i__carry__0_i_4__2_n_0)); + LUT2 #( + .INIT(4'h9)) + i__carry__0_i_4__3 + (.I0(row_cnt_reg[12]), + .I1(\time_control_regs[0] [25]), + .O(i__carry__0_i_4__3_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry__0_i_5 + (.I0(total_cols[10]), + .I1(\col_cnt_reg_n_0_[10] ), + .I2(\col_cnt_reg_n_0_[11] ), + .I3(total_cols[11]), + .O(i__carry__0_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry__0_i_5__0 + (.I0(\time_control_regs[0] [23]), + .I1(row_cnt_reg[10]), + .I2(row_cnt_reg[11]), + .I3(\time_control_regs[0] [24]), + .O(i__carry__0_i_5__0_n_0)); + LUT2 #( + .INIT(4'h1)) + i__carry__0_i_5__1 + (.I0(row_cnt_reg[8]), + .I1(row_cnt_reg[9]), + .O(i__carry__0_i_5__1_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry__0_i_5__2 + (.I0(\time_control_regs[0] [23]), + .I1(row_cnt_reg[10]), + .I2(row_cnt_reg[11]), + .I3(\time_control_regs[0] [24]), + .O(i__carry__0_i_5__2_n_0)); + LUT2 #( + .INIT(4'h1)) + i__carry__0_i_5__3 + (.I0(\col_cnt_reg_n_0_[8] ), + .I1(\col_cnt_reg_n_0_[9] ), + .O(i__carry__0_i_5__3_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry__0_i_6 + (.I0(total_cols[9]), + .I1(\col_cnt_reg_n_0_[9] ), + .I2(total_cols[8]), + .I3(\col_cnt_reg_n_0_[8] ), + .O(i__carry__0_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry__0_i_6__0 + (.I0(\time_control_regs[0] [21]), + .I1(row_cnt_reg[8]), + .I2(row_cnt_reg[9]), + .I3(\time_control_regs[0] [22]), + .O(i__carry__0_i_6__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry__0_i_6__1 + (.I0(\time_control_regs[0] [21]), + .I1(row_cnt_reg[8]), + .I2(row_cnt_reg[9]), + .I3(\time_control_regs[0] [22]), + .O(i__carry__0_i_6__1_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry_i_1 + (.I0(total_cols[6]), + .I1(\col_cnt_reg_n_0_[6] ), + .I2(\col_cnt_reg_n_0_[7] ), + .I3(total_cols[7]), + .O(i__carry_i_1_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + i__carry_i_1__0 + (.I0(total_cols[11]), + .I1(\col_cnt_reg_n_0_[11] ), + .I2(\col_cnt_reg_n_0_[10] ), + .I3(total_cols[10]), + .I4(total_cols[9]), + .I5(\col_cnt_reg_n_0_[9] ), + .O(i__carry_i_1__0_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + i__carry_i_1__1 + (.I0(total_rows[10]), + .I1(row_cnt_reg[10]), + .I2(total_rows[11]), + .I3(row_cnt_reg[11]), + .I4(row_cnt_reg[9]), + .I5(total_rows[9]), + .O(i__carry_i_1__1_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry_i_1__2 + (.I0(row_cnt_reg[6]), + .I1(\time_control_regs[0] [19]), + .I2(\time_control_regs[0] [20]), + .I3(row_cnt_reg[7]), + .O(i__carry_i_1__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry_i_1__3 + (.I0(\time_control_regs[0] [19]), + .I1(row_cnt_reg[6]), + .I2(row_cnt_reg[7]), + .I3(\time_control_regs[0] [20]), + .O(i__carry_i_1__3_n_0)); + LUT2 #( + .INIT(4'h7)) + i__carry_i_1__4 + (.I0(\col_cnt_reg_n_0_[3] ), + .I1(\col_cnt_reg_n_0_[2] ), + .O(i__carry_i_1__4_n_0)); + LUT2 #( + .INIT(4'hE)) + i__carry_i_1__5 + (.I0(row_cnt_reg[7]), + .I1(row_cnt_reg[6]), + .O(i__carry_i_1__5_n_0)); + LUT2 #( + .INIT(4'hE)) + i__carry_i_1__6 + (.I0(\col_cnt_reg_n_0_[7] ), + .I1(\col_cnt_reg_n_0_[6] ), + .O(i__carry_i_1__6_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry_i_2 + (.I0(total_cols[4]), + .I1(\col_cnt_reg_n_0_[4] ), + .I2(\col_cnt_reg_n_0_[5] ), + .I3(total_cols[5]), + .O(i__carry_i_2_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + i__carry_i_2__0 + (.I0(total_cols[7]), + .I1(\col_cnt_reg_n_0_[7] ), + .I2(\col_cnt_reg_n_0_[6] ), + .I3(total_cols[6]), + .I4(total_cols[8]), + .I5(\col_cnt_reg_n_0_[8] ), + .O(i__carry_i_2__0_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + i__carry_i_2__1 + (.I0(total_rows[6]), + .I1(row_cnt_reg[6]), + .I2(total_rows[7]), + .I3(row_cnt_reg[7]), + .I4(row_cnt_reg[8]), + .I5(total_rows[8]), + .O(i__carry_i_2__1_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry_i_2__2 + (.I0(row_cnt_reg[4]), + .I1(\time_control_regs[0] [17]), + .I2(\time_control_regs[0] [18]), + .I3(row_cnt_reg[5]), + .O(i__carry_i_2__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry_i_2__3 + (.I0(\time_control_regs[0] [17]), + .I1(row_cnt_reg[4]), + .I2(row_cnt_reg[5]), + .I3(\time_control_regs[0] [18]), + .O(i__carry_i_2__3_n_0)); + LUT2 #( + .INIT(4'hE)) + i__carry_i_2__4 + (.I0(row_cnt_reg[5]), + .I1(row_cnt_reg[4]), + .O(i__carry_i_2__4_n_0)); + LUT2 #( + .INIT(4'hE)) + i__carry_i_2__5 + (.I0(\col_cnt_reg_n_0_[5] ), + .I1(\col_cnt_reg_n_0_[4] ), + .O(i__carry_i_2__5_n_0)); + LUT2 #( + .INIT(4'h1)) + i__carry_i_2__6 + (.I0(\col_cnt_reg_n_0_[8] ), + .I1(\col_cnt_reg_n_0_[9] ), + .O(i__carry_i_2__6_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry_i_3 + (.I0(total_cols[2]), + .I1(\col_cnt_reg_n_0_[2] ), + .I2(\col_cnt_reg_n_0_[3] ), + .I3(total_cols[3]), + .O(i__carry_i_3_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + i__carry_i_3__0 + (.I0(total_cols[5]), + .I1(\col_cnt_reg_n_0_[5] ), + .I2(\col_cnt_reg_n_0_[4] ), + .I3(total_cols[4]), + .I4(total_cols[3]), + .I5(\col_cnt_reg_n_0_[3] ), + .O(i__carry_i_3__0_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + i__carry_i_3__1 + (.I0(total_rows[4]), + .I1(row_cnt_reg[4]), + .I2(total_rows[5]), + .I3(row_cnt_reg[5]), + .I4(row_cnt_reg[3]), + .I5(total_rows[3]), + .O(i__carry_i_3__1_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry_i_3__2 + (.I0(row_cnt_reg[2]), + .I1(\time_control_regs[0] [15]), + .I2(\time_control_regs[0] [16]), + .I3(row_cnt_reg[3]), + .O(i__carry_i_3__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry_i_3__3 + (.I0(\time_control_regs[0] [15]), + .I1(row_cnt_reg[2]), + .I2(row_cnt_reg[3]), + .I3(\time_control_regs[0] [16]), + .O(i__carry_i_3__3_n_0)); + LUT2 #( + .INIT(4'hE)) + i__carry_i_3__4 + (.I0(row_cnt_reg[3]), + .I1(row_cnt_reg[2]), + .O(i__carry_i_3__4_n_0)); + LUT2 #( + .INIT(4'hE)) + i__carry_i_3__5 + (.I0(\col_cnt_reg_n_0_[3] ), + .I1(\col_cnt_reg_n_0_[2] ), + .O(i__carry_i_3__5_n_0)); + LUT2 #( + .INIT(4'h1)) + i__carry_i_3__6 + (.I0(\col_cnt_reg_n_0_[6] ), + .I1(\col_cnt_reg_n_0_[7] ), + .O(i__carry_i_3__6_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + i__carry_i_4 + (.I0(total_cols[1]), + .I1(\col_cnt_reg_n_0_[1] ), + .I2(\col_cnt_reg_n_0_[0] ), + .I3(total_cols[0]), + .I4(total_cols[2]), + .I5(\col_cnt_reg_n_0_[2] ), + .O(i__carry_i_4_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry_i_4__0 + (.I0(total_cols[0]), + .I1(\col_cnt_reg_n_0_[0] ), + .I2(\col_cnt_reg_n_0_[1] ), + .I3(total_cols[1]), + .O(i__carry_i_4__0_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + i__carry_i_4__1 + (.I0(total_rows[0]), + .I1(row_cnt_reg[0]), + .I2(total_rows[1]), + .I3(row_cnt_reg[1]), + .I4(row_cnt_reg[2]), + .I5(total_rows[2]), + .O(i__carry_i_4__1_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry_i_4__2 + (.I0(row_cnt_reg[0]), + .I1(\time_control_regs[0] [13]), + .I2(\time_control_regs[0] [14]), + .I3(row_cnt_reg[1]), + .O(i__carry_i_4__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry_i_4__3 + (.I0(\time_control_regs[0] [13]), + .I1(row_cnt_reg[0]), + .I2(row_cnt_reg[1]), + .I3(\time_control_regs[0] [14]), + .O(i__carry_i_4__3_n_0)); + LUT2 #( + .INIT(4'hE)) + i__carry_i_4__4 + (.I0(row_cnt_reg[1]), + .I1(row_cnt_reg[0]), + .O(i__carry_i_4__4_n_0)); + LUT2 #( + .INIT(4'h1)) + i__carry_i_4__5 + (.I0(\col_cnt_reg_n_0_[4] ), + .I1(\col_cnt_reg_n_0_[5] ), + .O(i__carry_i_4__5_n_0)); + LUT2 #( + .INIT(4'h1)) + i__carry_i_4__6 + (.I0(\col_cnt_reg_n_0_[6] ), + .I1(\col_cnt_reg_n_0_[7] ), + .O(i__carry_i_4__6_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry_i_5 + (.I0(total_cols[6]), + .I1(\col_cnt_reg_n_0_[6] ), + .I2(\col_cnt_reg_n_0_[7] ), + .I3(total_cols[7]), + .O(i__carry_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry_i_5__0 + (.I0(\time_control_regs[0] [19]), + .I1(row_cnt_reg[6]), + .I2(row_cnt_reg[7]), + .I3(\time_control_regs[0] [20]), + .O(i__carry_i_5__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry_i_5__1 + (.I0(\time_control_regs[0] [19]), + .I1(row_cnt_reg[6]), + .I2(row_cnt_reg[7]), + .I3(\time_control_regs[0] [20]), + .O(i__carry_i_5__1_n_0)); + LUT2 #( + .INIT(4'h8)) + i__carry_i_5__2 + (.I0(\col_cnt_reg_n_0_[2] ), + .I1(\col_cnt_reg_n_0_[3] ), + .O(i__carry_i_5__2_n_0)); + LUT2 #( + .INIT(4'h1)) + i__carry_i_5__3 + (.I0(row_cnt_reg[6]), + .I1(row_cnt_reg[7]), + .O(i__carry_i_5__3_n_0)); + LUT2 #( + .INIT(4'h1)) + i__carry_i_5__4 + (.I0(\col_cnt_reg_n_0_[4] ), + .I1(\col_cnt_reg_n_0_[5] ), + .O(i__carry_i_5__4_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry_i_6 + (.I0(total_cols[4]), + .I1(\col_cnt_reg_n_0_[4] ), + .I2(\col_cnt_reg_n_0_[5] ), + .I3(total_cols[5]), + .O(i__carry_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry_i_6__0 + (.I0(\time_control_regs[0] [17]), + .I1(row_cnt_reg[4]), + .I2(row_cnt_reg[5]), + .I3(\time_control_regs[0] [18]), + .O(i__carry_i_6__0_n_0)); + LUT2 #( + .INIT(4'h1)) + i__carry_i_6__1 + (.I0(row_cnt_reg[4]), + .I1(row_cnt_reg[5]), + .O(i__carry_i_6__1_n_0)); + LUT2 #( + .INIT(4'h1)) + i__carry_i_6__2 + (.I0(\col_cnt_reg_n_0_[2] ), + .I1(\col_cnt_reg_n_0_[3] ), + .O(i__carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry_i_6__3 + (.I0(\time_control_regs[0] [17]), + .I1(row_cnt_reg[4]), + .I2(row_cnt_reg[5]), + .I3(\time_control_regs[0] [18]), + .O(i__carry_i_6__3_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry_i_7 + (.I0(total_cols[3]), + .I1(\col_cnt_reg_n_0_[3] ), + .I2(total_cols[2]), + .I3(\col_cnt_reg_n_0_[2] ), + .O(i__carry_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry_i_7__0 + (.I0(\time_control_regs[0] [15]), + .I1(row_cnt_reg[2]), + .I2(row_cnt_reg[3]), + .I3(\time_control_regs[0] [16]), + .O(i__carry_i_7__0_n_0)); + LUT2 #( + .INIT(4'h1)) + i__carry_i_7__1 + (.I0(row_cnt_reg[2]), + .I1(row_cnt_reg[3]), + .O(i__carry_i_7__1_n_0)); + LUT2 #( + .INIT(4'h2)) + i__carry_i_7__2 + (.I0(\col_cnt_reg_n_0_[0] ), + .I1(\col_cnt_reg_n_0_[1] ), + .O(i__carry_i_7__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry_i_7__3 + (.I0(\time_control_regs[0] [15]), + .I1(row_cnt_reg[2]), + .I2(row_cnt_reg[3]), + .I3(\time_control_regs[0] [16]), + .O(i__carry_i_7__3_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry_i_8 + (.I0(total_cols[0]), + .I1(\col_cnt_reg_n_0_[0] ), + .I2(\col_cnt_reg_n_0_[1] ), + .I3(total_cols[1]), + .O(i__carry_i_8_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry_i_8__0 + (.I0(\time_control_regs[0] [13]), + .I1(row_cnt_reg[0]), + .I2(row_cnt_reg[1]), + .I3(\time_control_regs[0] [14]), + .O(i__carry_i_8__0_n_0)); + LUT2 #( + .INIT(4'h1)) + i__carry_i_8__1 + (.I0(row_cnt_reg[0]), + .I1(row_cnt_reg[1]), + .O(i__carry_i_8__1_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry_i_8__2 + (.I0(\time_control_regs[0] [13]), + .I1(row_cnt_reg[0]), + .I2(row_cnt_reg[1]), + .I3(\time_control_regs[0] [14]), + .O(i__carry_i_8__2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT2 #( + .INIT(4'hB)) + in_fifo_reset_i_1 + (.I0(in_fifo_reset), + .I1(in_fifo_reset_reg_0), + .O(in_fifo_reset0)); + LUT6 #( + .INIT(64'hCECECECECECECEEE)) + in_fifo_reset_i_2 + (.I0(in_fifo_reset_i_3_n_0), + .I1(\col_cnt_reg[1]_0 ), + .I2(fifo_rd_i), + .I3(eol_late_i_i_2_n_0), + .I4(eol_expected_d), + .I5(\genr_control_regs[0] [1]), + .O(in_fifo_reset_reg_0)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h55030303)) + in_fifo_reset_i_3 + (.I0(sof_early_i_reg_1), + .I1(eol_expected_d), + .I2(eol_late_i_reg_0), + .I3(in_fifo_reset), + .I4(t_qb[0]), + .O(in_fifo_reset_i_3_n_0)); + FDRE #( + .INIT(1'b0)) + in_fifo_reset_reg + (.C(aclk), + .CE(master_en), + .D(in_fifo_reset0), + .Q(in_fifo_reset), + .R(SR)); + LUT4 #( + .INIT(16'h0080)) + \intc_if[0]_INST_0 + (.I0(core_en_i), + .I1(aclken), + .I2(\genr_control_regs[0] [0]), + .I3(eol_late_i_reg_0), + .O(E)); + LUT4 #( + .INIT(16'hFFFE)) + \intc_if[4]_INST_0 + (.I0(sof_early_i_reg_1), + .I1(sof_early_i_reg_0), + .I2(intc_if[4]), + .I3(eol_late_i_reg_0), + .O(intc_if[3])); + CARRY4 leqOp_carry + (.CI(1'b0), + .CO({leqOp_carry_n_0,leqOp_carry_n_1,leqOp_carry_n_2,leqOp_carry_n_3}), + .CYINIT(1'b1), + .DI({leqOp_carry_i_1_n_0,leqOp_carry_i_2_n_0,leqOp_carry_i_3_n_0,leqOp_carry_i_4_n_0}), + .O(NLW_leqOp_carry_O_UNCONNECTED[3:0]), + .S({leqOp_carry_i_5_n_0,leqOp_carry_i_6_n_0,leqOp_carry_i_7_n_0,leqOp_carry_i_8_n_0})); + CARRY4 leqOp_carry__0 + (.CI(leqOp_carry_n_0), + .CO({NLW_leqOp_carry__0_CO_UNCONNECTED[3],leqOp20_in,leqOp_carry__0_n_2,leqOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({1'b0,leqOp_carry__0_i_1_n_0,leqOp_carry__0_i_2_n_0,leqOp_carry__0_i_3_n_0}), + .O(NLW_leqOp_carry__0_O_UNCONNECTED[3:0]), + .S({1'b0,leqOp_carry__0_i_4_n_0,leqOp_carry__0_i_5_n_0,leqOp_carry__0_i_6_n_0})); + LUT2 #( + .INIT(4'h2)) + leqOp_carry__0_i_1 + (.I0(\time_control_regs[0] [12]), + .I1(\col_cnt_reg_n_0_[12] ), + .O(leqOp_carry__0_i_1_n_0)); + LUT4 #( + .INIT(16'h20F2)) + leqOp_carry__0_i_2 + (.I0(\time_control_regs[0] [10]), + .I1(\col_cnt_reg_n_0_[10] ), + .I2(\time_control_regs[0] [11]), + .I3(\col_cnt_reg_n_0_[11] ), + .O(leqOp_carry__0_i_2_n_0)); + LUT4 #( + .INIT(16'h40F4)) + leqOp_carry__0_i_3 + (.I0(\col_cnt_reg_n_0_[8] ), + .I1(\time_control_regs[0] [8]), + .I2(\time_control_regs[0] [9]), + .I3(\col_cnt_reg_n_0_[9] ), + .O(leqOp_carry__0_i_3_n_0)); + LUT2 #( + .INIT(4'h9)) + leqOp_carry__0_i_4 + (.I0(\col_cnt_reg_n_0_[12] ), + .I1(\time_control_regs[0] [12]), + .O(leqOp_carry__0_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + leqOp_carry__0_i_5 + (.I0(\time_control_regs[0] [11]), + .I1(\col_cnt_reg_n_0_[11] ), + .I2(\time_control_regs[0] [10]), + .I3(\col_cnt_reg_n_0_[10] ), + .O(leqOp_carry__0_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + leqOp_carry__0_i_6 + (.I0(\time_control_regs[0] [8]), + .I1(\col_cnt_reg_n_0_[8] ), + .I2(\time_control_regs[0] [9]), + .I3(\col_cnt_reg_n_0_[9] ), + .O(leqOp_carry__0_i_6_n_0)); + LUT4 #( + .INIT(16'h20F2)) + leqOp_carry_i_1 + (.I0(\time_control_regs[0] [6]), + .I1(\col_cnt_reg_n_0_[6] ), + .I2(\time_control_regs[0] [7]), + .I3(\col_cnt_reg_n_0_[7] ), + .O(leqOp_carry_i_1_n_0)); + LUT4 #( + .INIT(16'h20F2)) + leqOp_carry_i_2 + (.I0(\time_control_regs[0] [4]), + .I1(\col_cnt_reg_n_0_[4] ), + .I2(\time_control_regs[0] [5]), + .I3(\col_cnt_reg_n_0_[5] ), + .O(leqOp_carry_i_2_n_0)); + LUT4 #( + .INIT(16'h40F4)) + leqOp_carry_i_3 + (.I0(\col_cnt_reg_n_0_[2] ), + .I1(\time_control_regs[0] [2]), + .I2(\time_control_regs[0] [3]), + .I3(\col_cnt_reg_n_0_[3] ), + .O(leqOp_carry_i_3_n_0)); + LUT4 #( + .INIT(16'h20F2)) + leqOp_carry_i_4 + (.I0(\time_control_regs[0] [0]), + .I1(\col_cnt_reg_n_0_[0] ), + .I2(\time_control_regs[0] [1]), + .I3(\col_cnt_reg_n_0_[1] ), + .O(leqOp_carry_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + leqOp_carry_i_5 + (.I0(\time_control_regs[0] [6]), + .I1(\col_cnt_reg_n_0_[6] ), + .I2(\time_control_regs[0] [7]), + .I3(\col_cnt_reg_n_0_[7] ), + .O(leqOp_carry_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + leqOp_carry_i_6 + (.I0(\time_control_regs[0] [5]), + .I1(\col_cnt_reg_n_0_[5] ), + .I2(\time_control_regs[0] [4]), + .I3(\col_cnt_reg_n_0_[4] ), + .O(leqOp_carry_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + leqOp_carry_i_7 + (.I0(\time_control_regs[0] [2]), + .I1(\col_cnt_reg_n_0_[2] ), + .I2(\time_control_regs[0] [3]), + .I3(\col_cnt_reg_n_0_[3] ), + .O(leqOp_carry_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + leqOp_carry_i_8 + (.I0(\time_control_regs[0] [0]), + .I1(\col_cnt_reg_n_0_[0] ), + .I2(\time_control_regs[0] [1]), + .I3(\col_cnt_reg_n_0_[1] ), + .O(leqOp_carry_i_8_n_0)); + CARRY4 \leqOp_inferred__0/i__carry + (.CI(1'b0), + .CO({\leqOp_inferred__0/i__carry_n_0 ,\leqOp_inferred__0/i__carry_n_1 ,\leqOp_inferred__0/i__carry_n_2 ,\leqOp_inferred__0/i__carry_n_3 }), + .CYINIT(1'b1), + .DI({i__carry_i_1_n_0,i__carry_i_2_n_0,i__carry_i_3_n_0,i__carry_i_4__0_n_0}), + .O(\NLW_leqOp_inferred__0/i__carry_O_UNCONNECTED [3:0]), + .S({i__carry_i_5_n_0,i__carry_i_6_n_0,i__carry_i_7_n_0,i__carry_i_8_n_0})); + CARRY4 \leqOp_inferred__0/i__carry__0 + (.CI(\leqOp_inferred__0/i__carry_n_0 ), + .CO({\NLW_leqOp_inferred__0/i__carry__0_CO_UNCONNECTED [3],leqOp23_in,\leqOp_inferred__0/i__carry__0_n_2 ,\leqOp_inferred__0/i__carry__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,i__carry__0_i_1_n_0,i__carry__0_i_2_n_0,i__carry__0_i_3_n_0}), + .O(\NLW_leqOp_inferred__0/i__carry__0_O_UNCONNECTED [3:0]), + .S({1'b0,i__carry__0_i_4__1_n_0,i__carry__0_i_5_n_0,i__carry__0_i_6_n_0})); + CARRY4 \leqOp_inferred__1/i__carry + (.CI(1'b0), + .CO({\leqOp_inferred__1/i__carry_n_0 ,\leqOp_inferred__1/i__carry_n_1 ,\leqOp_inferred__1/i__carry_n_2 ,\leqOp_inferred__1/i__carry_n_3 }), + .CYINIT(1'b1), + .DI({i__carry_i_1__3_n_0,i__carry_i_2__3_n_0,i__carry_i_3__3_n_0,i__carry_i_4__3_n_0}), + .O(\NLW_leqOp_inferred__1/i__carry_O_UNCONNECTED [3:0]), + .S({i__carry_i_5__0_n_0,i__carry_i_6__0_n_0,i__carry_i_7__0_n_0,i__carry_i_8__0_n_0})); + CARRY4 \leqOp_inferred__1/i__carry__0 + (.CI(\leqOp_inferred__1/i__carry_n_0 ), + .CO({\NLW_leqOp_inferred__1/i__carry__0_CO_UNCONNECTED [3],leqOp16_in,\leqOp_inferred__1/i__carry__0_n_2 ,\leqOp_inferred__1/i__carry__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,i__carry__0_i_1__1_n_0,i__carry__0_i_2__1_n_0,i__carry__0_i_3__3_n_0}), + .O(\NLW_leqOp_inferred__1/i__carry__0_O_UNCONNECTED [3:0]), + .S({1'b0,i__carry__0_i_4__3_n_0,i__carry__0_i_5__0_n_0,i__carry__0_i_6__0_n_0})); + LUT6 #( + .INIT(64'hFFFFBFFF00008000)) + line_cnt_tc_i_1 + (.I0(line_cnt_tc_i_2_n_0), + .I1(aclken), + .I2(\genr_control_regs[0] [0]), + .I3(resetn_out), + .I4(line_cnt_tc_i_3_n_0), + .I5(intc_if[2]), + .O(line_cnt_tc_i_1_n_0)); + LUT5 #( + .INIT(32'h20000000)) + line_cnt_tc_i_2 + (.I0(line_cnt_tc_i_4_n_0), + .I1(line_cnt_tc_i_5_n_0), + .I2(row_cnt_reg[9]), + .I3(row_cnt_reg[8]), + .I4(row_cnt_reg[5]), + .O(line_cnt_tc_i_2_n_0)); + LUT6 #( + .INIT(64'hFEFE0000FEFEEEFE)) + line_cnt_tc_i_3 + (.I0(\write_ptr_int_reg[2]_0 ), + .I1(\read_ptr_int_reg[1] ), + .I2(line_cnt_tc_i_6_n_0), + .I3(leqOp20_in), + .I4(empty_match_reg), + .I5(CO), + .O(line_cnt_tc_i_3_n_0)); + LUT6 #( + .INIT(64'h8000000000000000)) + line_cnt_tc_i_4 + (.I0(row_cnt_reg[10]), + .I1(row_cnt_reg[6]), + .I2(row_cnt_reg[0]), + .I3(row_cnt_reg[7]), + .I4(row_cnt_reg[2]), + .I5(row_cnt_reg[11]), + .O(line_cnt_tc_i_4_n_0)); + LUT4 #( + .INIT(16'h7FFF)) + line_cnt_tc_i_5 + (.I0(row_cnt_reg[4]), + .I1(row_cnt_reg[3]), + .I2(row_cnt_reg[12]), + .I3(row_cnt_reg[1]), + .O(line_cnt_tc_i_5_n_0)); + LUT3 #( + .INIT(8'h07)) + line_cnt_tc_i_6 + (.I0(gtOp22_in), + .I1(leqOp23_in), + .I2(gtOp21_in), + .O(line_cnt_tc_i_6_n_0)); + FDRE #( + .INIT(1'b0)) + line_cnt_tc_reg + (.C(aclk), + .CE(1'b1), + .D(line_cnt_tc_i_1_n_0), + .Q(intc_if[2]), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({NLW_ltOp_carry__0_CO_UNCONNECTED[3],ltOp_carry__0_n_1,ltOp_carry__0_n_2,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({1'b0,ltOp_carry__0_i_1_n_0,ltOp_carry__0_i_2_n_0,ltOp_carry__0_i_3_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({1'b0,ltOp_carry__0_i_4_n_0,ltOp_carry__0_i_5_n_0,ltOp_carry__0_i_6_n_0})); + LUT2 #( + .INIT(4'h2)) + ltOp_carry__0_i_1 + (.I0(total_rows[12]), + .I1(row_cnt_reg[12]), + .O(ltOp_carry__0_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__0_i_2 + (.I0(total_rows[11]), + .I1(row_cnt_reg[11]), + .I2(total_rows[10]), + .I3(row_cnt_reg[10]), + .O(ltOp_carry__0_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry__0_i_3 + (.I0(total_rows[9]), + .I1(row_cnt_reg[9]), + .I2(total_rows[8]), + .I3(row_cnt_reg[8]), + .O(ltOp_carry__0_i_3_n_0)); + LUT2 #( + .INIT(4'h9)) + ltOp_carry__0_i_4 + (.I0(row_cnt_reg[12]), + .I1(total_rows[12]), + .O(ltOp_carry__0_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__0_i_5 + (.I0(row_cnt_reg[11]), + .I1(total_rows[11]), + .I2(row_cnt_reg[10]), + .I3(total_rows[10]), + .O(ltOp_carry__0_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__0_i_6 + (.I0(row_cnt_reg[9]), + .I1(total_rows[9]), + .I2(row_cnt_reg[8]), + .I3(total_rows[8]), + .O(ltOp_carry__0_i_6_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry_i_1 + (.I0(total_rows[7]), + .I1(row_cnt_reg[7]), + .I2(total_rows[6]), + .I3(row_cnt_reg[6]), + .O(ltOp_carry_i_1_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry_i_2 + (.I0(total_rows[5]), + .I1(row_cnt_reg[5]), + .I2(total_rows[4]), + .I3(row_cnt_reg[4]), + .O(ltOp_carry_i_2_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry_i_3 + (.I0(total_rows[3]), + .I1(row_cnt_reg[3]), + .I2(total_rows[2]), + .I3(row_cnt_reg[2]), + .O(ltOp_carry_i_3_n_0)); + LUT4 #( + .INIT(16'h22B2)) + ltOp_carry_i_4 + (.I0(total_rows[1]), + .I1(row_cnt_reg[1]), + .I2(total_rows[0]), + .I3(row_cnt_reg[0]), + .O(ltOp_carry_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(row_cnt_reg[7]), + .I1(total_rows[7]), + .I2(row_cnt_reg[6]), + .I3(total_rows[6]), + .O(ltOp_carry_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(row_cnt_reg[5]), + .I1(total_rows[5]), + .I2(row_cnt_reg[4]), + .I3(total_rows[4]), + .O(ltOp_carry_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(row_cnt_reg[3]), + .I1(total_rows[3]), + .I2(row_cnt_reg[2]), + .I3(total_rows[2]), + .O(ltOp_carry_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(row_cnt_reg[1]), + .I1(total_rows[1]), + .I2(row_cnt_reg[0]), + .I3(total_rows[0]), + .O(ltOp_carry_i_8_n_0)); + CARRY4 \ltOp_inferred__0/i__carry + (.CI(1'b0), + .CO({\ltOp_inferred__0/i__carry_n_0 ,\ltOp_inferred__0/i__carry_n_1 ,\ltOp_inferred__0/i__carry_n_2 ,\ltOp_inferred__0/i__carry_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,i__carry_i_1__4_n_0}), + .O(\NLW_ltOp_inferred__0/i__carry_O_UNCONNECTED [3:0]), + .S({i__carry_i_2__6_n_0,i__carry_i_3__6_n_0,i__carry_i_4__5_n_0,i__carry_i_5__2_n_0})); + CARRY4 \ltOp_inferred__0/i__carry__0 + (.CI(\ltOp_inferred__0/i__carry_n_0 ), + .CO({\NLW_ltOp_inferred__0/i__carry__0_CO_UNCONNECTED [3:2],CO,\ltOp_inferred__0/i__carry__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_ltOp_inferred__0/i__carry__0_O_UNCONNECTED [3:0]), + .S({1'b0,1'b0,i__carry__0_i_1__4_n_0,i__carry__0_i_2__4_n_0})); + FDRE #( + .INIT(1'b0)) + out_fifo_eol_reg + (.C(aclk), + .CE(master_en), + .D(eqOp1_out), + .Q(da[0]), + .R(SR)); + LUT6 #( + .INIT(64'h0000000000000008)) + out_fifo_sof_i_1 + (.I0(sof_expected_i_2_n_0), + .I1(out_fifo_sof_i_2_n_0), + .I2(\col_cnt_reg_n_0_[11] ), + .I3(\col_cnt_reg_n_0_[10] ), + .I4(\col_cnt_reg_n_0_[7] ), + .I5(\col_cnt_reg_n_0_[6] ), + .O(out_fifo_sof0)); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h8)) + out_fifo_sof_i_2 + (.I0(\col_cnt_reg_n_0_[2] ), + .I1(\col_cnt_reg_n_0_[3] ), + .O(out_fifo_sof_i_2_n_0)); + FDSE #( + .INIT(1'b0)) + out_fifo_sof_reg + (.C(aclk), + .CE(master_en), + .D(out_fifo_sof0), + .Q(da[1]), + .S(SR)); + LUT6 #( + .INIT(64'hFFFFBFFF00008000)) + pixel_cnt_tc_i_1 + (.I0(eqOp), + .I1(aclken), + .I2(\genr_control_regs[0] [0]), + .I3(resetn_out), + .I4(line_cnt_tc_i_3_n_0), + .I5(intc_if[1]), + .O(pixel_cnt_tc_i_1_n_0)); + LUT5 #( + .INIT(32'h20000000)) + pixel_cnt_tc_i_2 + (.I0(pixel_cnt_tc_i_3_n_0), + .I1(pixel_cnt_tc_i_4_n_0), + .I2(\col_cnt_reg_n_0_[4] ), + .I3(\col_cnt_reg_n_0_[9] ), + .I4(\col_cnt_reg_n_0_[6] ), + .O(eqOp)); + LUT6 #( + .INIT(64'h8000000000000000)) + pixel_cnt_tc_i_3 + (.I0(\col_cnt_reg_n_0_[3] ), + .I1(\col_cnt_reg_n_0_[2] ), + .I2(\col_cnt_reg_n_0_[0] ), + .I3(\col_cnt_reg_n_0_[12] ), + .I4(\col_cnt_reg_n_0_[5] ), + .I5(\col_cnt_reg_n_0_[7] ), + .O(pixel_cnt_tc_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h7FFF)) + pixel_cnt_tc_i_4 + (.I0(\col_cnt_reg_n_0_[10] ), + .I1(\col_cnt_reg_n_0_[8] ), + .I2(\col_cnt_reg_n_0_[11] ), + .I3(\col_cnt_reg_n_0_[1] ), + .O(pixel_cnt_tc_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + pixel_cnt_tc_reg + (.C(aclk), + .CE(1'b1), + .D(pixel_cnt_tc_i_1_n_0), + .Q(intc_if[1]), + .R(1'b0)); + LUT6 #( + .INIT(64'h00000111FFFFFFFF)) + \row_cnt[0]_i_1 + (.I0(\col_cnt_reg[1]_0 ), + .I1(line_cnt_tc_i_3_n_0), + .I2(\row_cnt[0]_i_4_n_0 ), + .I3(ltOp_carry__0_n_1), + .I4(\col_cnt[12]_i_4_n_0 ), + .I5(resetn_out), + .O(\row_cnt[0]_i_1_n_0 )); + LUT5 #( + .INIT(32'h04000000)) + \row_cnt[0]_i_2 + (.I0(eol_late_i3_out), + .I1(geqOp), + .I2(line_cnt_tc_i_3_n_0), + .I3(aclken), + .I4(\genr_control_regs[0] [0]), + .O(row_cnt)); + LUT6 #( + .INIT(64'hC000C33340004555)) + \row_cnt[0]_i_4 + (.I0(sof_early_i_reg_0), + .I1(sof_expected), + .I2(in_fifo_reset), + .I3(t_qb[1]), + .I4(sof_early_i_reg_1), + .I5(fifo_rd_d), + .O(\row_cnt[0]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \row_cnt[0]_i_5 + (.I0(row_cnt_reg[3]), + .O(\row_cnt[0]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \row_cnt[0]_i_6 + (.I0(row_cnt_reg[2]), + .O(\row_cnt[0]_i_6_n_0 )); + LUT1 #( + .INIT(2'h2)) + \row_cnt[0]_i_7 + (.I0(row_cnt_reg[1]), + .O(\row_cnt[0]_i_7_n_0 )); + LUT1 #( + .INIT(2'h1)) + \row_cnt[0]_i_8 + (.I0(row_cnt_reg[0]), + .O(\row_cnt[0]_i_8_n_0 )); + LUT1 #( + .INIT(2'h2)) + \row_cnt[12]_i_2 + (.I0(row_cnt_reg[12]), + .O(\row_cnt[12]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \row_cnt[4]_i_2 + (.I0(row_cnt_reg[7]), + .O(\row_cnt[4]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \row_cnt[4]_i_3 + (.I0(row_cnt_reg[6]), + .O(\row_cnt[4]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \row_cnt[4]_i_4 + (.I0(row_cnt_reg[5]), + .O(\row_cnt[4]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \row_cnt[4]_i_5 + (.I0(row_cnt_reg[4]), + .O(\row_cnt[4]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \row_cnt[8]_i_2 + (.I0(row_cnt_reg[11]), + .O(\row_cnt[8]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \row_cnt[8]_i_3 + (.I0(row_cnt_reg[10]), + .O(\row_cnt[8]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \row_cnt[8]_i_4 + (.I0(row_cnt_reg[9]), + .O(\row_cnt[8]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \row_cnt[8]_i_5 + (.I0(row_cnt_reg[8]), + .O(\row_cnt[8]_i_5_n_0 )); + FDSE #( + .INIT(1'b1)) + \row_cnt_reg[0] + (.C(aclk), + .CE(row_cnt), + .D(\row_cnt_reg[0]_i_3_n_7 ), + .Q(row_cnt_reg[0]), + .S(\row_cnt[0]_i_1_n_0 )); + CARRY4 \row_cnt_reg[0]_i_3 + (.CI(1'b0), + .CO({\row_cnt_reg[0]_i_3_n_0 ,\row_cnt_reg[0]_i_3_n_1 ,\row_cnt_reg[0]_i_3_n_2 ,\row_cnt_reg[0]_i_3_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\row_cnt_reg[0]_i_3_n_4 ,\row_cnt_reg[0]_i_3_n_5 ,\row_cnt_reg[0]_i_3_n_6 ,\row_cnt_reg[0]_i_3_n_7 }), + .S({\row_cnt[0]_i_5_n_0 ,\row_cnt[0]_i_6_n_0 ,\row_cnt[0]_i_7_n_0 ,\row_cnt[0]_i_8_n_0 })); + FDRE #( + .INIT(1'b0)) + \row_cnt_reg[10] + (.C(aclk), + .CE(row_cnt), + .D(\row_cnt_reg[8]_i_1_n_5 ), + .Q(row_cnt_reg[10]), + .R(\row_cnt[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \row_cnt_reg[11] + (.C(aclk), + .CE(row_cnt), + .D(\row_cnt_reg[8]_i_1_n_4 ), + .Q(row_cnt_reg[11]), + .R(\row_cnt[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \row_cnt_reg[12] + (.C(aclk), + .CE(row_cnt), + .D(\row_cnt_reg[12]_i_1_n_7 ), + .Q(row_cnt_reg[12]), + .R(\row_cnt[0]_i_1_n_0 )); + CARRY4 \row_cnt_reg[12]_i_1 + (.CI(\row_cnt_reg[8]_i_1_n_0 ), + .CO(\NLW_row_cnt_reg[12]_i_1_CO_UNCONNECTED [3:0]), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_row_cnt_reg[12]_i_1_O_UNCONNECTED [3:1],\row_cnt_reg[12]_i_1_n_7 }), + .S({1'b0,1'b0,1'b0,\row_cnt[12]_i_2_n_0 })); + FDRE #( + .INIT(1'b0)) + \row_cnt_reg[1] + (.C(aclk), + .CE(row_cnt), + .D(\row_cnt_reg[0]_i_3_n_6 ), + .Q(row_cnt_reg[1]), + .R(\row_cnt[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \row_cnt_reg[2] + (.C(aclk), + .CE(row_cnt), + .D(\row_cnt_reg[0]_i_3_n_5 ), + .Q(row_cnt_reg[2]), + .R(\row_cnt[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \row_cnt_reg[3] + (.C(aclk), + .CE(row_cnt), + .D(\row_cnt_reg[0]_i_3_n_4 ), + .Q(row_cnt_reg[3]), + .R(\row_cnt[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \row_cnt_reg[4] + (.C(aclk), + .CE(row_cnt), + .D(\row_cnt_reg[4]_i_1_n_7 ), + .Q(row_cnt_reg[4]), + .R(\row_cnt[0]_i_1_n_0 )); + CARRY4 \row_cnt_reg[4]_i_1 + (.CI(\row_cnt_reg[0]_i_3_n_0 ), + .CO({\row_cnt_reg[4]_i_1_n_0 ,\row_cnt_reg[4]_i_1_n_1 ,\row_cnt_reg[4]_i_1_n_2 ,\row_cnt_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\row_cnt_reg[4]_i_1_n_4 ,\row_cnt_reg[4]_i_1_n_5 ,\row_cnt_reg[4]_i_1_n_6 ,\row_cnt_reg[4]_i_1_n_7 }), + .S({\row_cnt[4]_i_2_n_0 ,\row_cnt[4]_i_3_n_0 ,\row_cnt[4]_i_4_n_0 ,\row_cnt[4]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \row_cnt_reg[5] + (.C(aclk), + .CE(row_cnt), + .D(\row_cnt_reg[4]_i_1_n_6 ), + .Q(row_cnt_reg[5]), + .R(\row_cnt[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \row_cnt_reg[6] + (.C(aclk), + .CE(row_cnt), + .D(\row_cnt_reg[4]_i_1_n_5 ), + .Q(row_cnt_reg[6]), + .R(\row_cnt[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \row_cnt_reg[7] + (.C(aclk), + .CE(row_cnt), + .D(\row_cnt_reg[4]_i_1_n_4 ), + .Q(row_cnt_reg[7]), + .R(\row_cnt[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \row_cnt_reg[8] + (.C(aclk), + .CE(row_cnt), + .D(\row_cnt_reg[8]_i_1_n_7 ), + .Q(row_cnt_reg[8]), + .R(\row_cnt[0]_i_1_n_0 )); + CARRY4 \row_cnt_reg[8]_i_1 + (.CI(\row_cnt_reg[4]_i_1_n_0 ), + .CO({\row_cnt_reg[8]_i_1_n_0 ,\row_cnt_reg[8]_i_1_n_1 ,\row_cnt_reg[8]_i_1_n_2 ,\row_cnt_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\row_cnt_reg[8]_i_1_n_4 ,\row_cnt_reg[8]_i_1_n_5 ,\row_cnt_reg[8]_i_1_n_6 ,\row_cnt_reg[8]_i_1_n_7 }), + .S({\row_cnt[8]_i_2_n_0 ,\row_cnt[8]_i_3_n_0 ,\row_cnt[8]_i_4_n_0 ,\row_cnt[8]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \row_cnt_reg[9] + (.C(aclk), + .CE(row_cnt), + .D(\row_cnt_reg[8]_i_1_n_6 ), + .Q(row_cnt_reg[9]), + .R(\row_cnt[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h5755555502000000)) + sof_early_i_i_1 + (.I0(fifo_rd_d), + .I1(sof_expected), + .I2(sof_early_i_reg_1), + .I3(in_fifo_reset), + .I4(t_qb[1]), + .I5(sof_early_i_reg_0), + .O(sof_early_i_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + sof_early_i_reg + (.C(aclk), + .CE(master_en), + .D(sof_early_i_i_1_n_0), + .Q(sof_early_i_reg_0), + .R(SR)); + LUT6 #( + .INIT(64'h0000000200000000)) + sof_expected_i_1 + (.I0(sof_expected_i_2_n_0), + .I1(\col_cnt_reg_n_0_[2] ), + .I2(\col_cnt_reg_n_0_[3] ), + .I3(\col_cnt_reg_n_0_[11] ), + .I4(\col_cnt_reg_n_0_[10] ), + .I5(sof_expected_i_3_n_0), + .O(sof_expected0)); + LUT6 #( + .INIT(64'h0000000000020000)) + sof_expected_i_2 + (.I0(sof_expected_i_4_n_0), + .I1(sof_expected_i_5_n_0), + .I2(\col_cnt_reg_n_0_[12] ), + .I3(\col_cnt_reg_n_0_[0] ), + .I4(\col_cnt_reg_n_0_[1] ), + .I5(row_cnt_reg[12]), + .O(sof_expected_i_2_n_0)); + LUT2 #( + .INIT(4'h1)) + sof_expected_i_3 + (.I0(\col_cnt_reg_n_0_[6] ), + .I1(\col_cnt_reg_n_0_[7] ), + .O(sof_expected_i_3_n_0)); + LUT6 #( + .INIT(64'h0004000000000000)) + sof_expected_i_4 + (.I0(row_cnt_reg[1]), + .I1(row_cnt_reg[0]), + .I2(row_cnt_reg[2]), + .I3(row_cnt_reg[3]), + .I4(sof_expected_i_6_n_0), + .I5(sof_expected_i_7_n_0), + .O(sof_expected_i_4_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFDFF)) + sof_expected_i_5 + (.I0(sof_expected_i_8_n_0), + .I1(row_cnt_reg[8]), + .I2(row_cnt_reg[9]), + .I3(sof_expected_i_9_n_0), + .I4(row_cnt_reg[4]), + .I5(row_cnt_reg[5]), + .O(sof_expected_i_5_n_0)); + LUT2 #( + .INIT(4'h1)) + sof_expected_i_6 + (.I0(row_cnt_reg[10]), + .I1(row_cnt_reg[11]), + .O(sof_expected_i_6_n_0)); + LUT2 #( + .INIT(4'h1)) + sof_expected_i_7 + (.I0(row_cnt_reg[6]), + .I1(row_cnt_reg[7]), + .O(sof_expected_i_7_n_0)); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h1)) + sof_expected_i_8 + (.I0(\col_cnt_reg_n_0_[8] ), + .I1(\col_cnt_reg_n_0_[9] ), + .O(sof_expected_i_8_n_0)); + LUT2 #( + .INIT(4'h1)) + sof_expected_i_9 + (.I0(\col_cnt_reg_n_0_[4] ), + .I1(\col_cnt_reg_n_0_[5] ), + .O(sof_expected_i_9_n_0)); + FDRE #( + .INIT(1'b0)) + sof_expected_reg + (.C(aclk), + .CE(master_en), + .D(sof_expected0), + .Q(sof_expected), + .R(SR)); + LUT2 #( + .INIT(4'h8)) + sof_late_i_i_2 + (.I0(\genr_control_regs[0] [0]), + .I1(aclken), + .O(master_en)); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h3F2A3F00)) + sof_late_i_i_3 + (.I0(sof_expected), + .I1(in_fifo_reset), + .I2(t_qb[1]), + .I3(sof_early_i_reg_1), + .I4(fifo_rd_d), + .O(sof_late_i2_out)); + FDRE #( + .INIT(1'b0)) + sof_late_i_reg + (.C(aclk), + .CE(master_en), + .D(sof_late_i2_out), + .Q(sof_early_i_reg_1), + .R(SR)); + LUT1 #( + .INIT(2'h1)) + \total_cols[0]_i_1 + (.I0(\time_control_regs[0] [0]), + .O(plusOp[0])); + LUT1 #( + .INIT(2'h2)) + \total_cols[12]_i_2 + (.I0(\time_control_regs[0] [12]), + .O(\total_cols[12]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \total_cols[12]_i_3 + (.I0(\time_control_regs[0] [11]), + .O(\total_cols[12]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \total_cols[12]_i_4 + (.I0(\time_control_regs[0] [10]), + .O(\total_cols[12]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \total_cols[12]_i_5 + (.I0(\time_control_regs[0] [9]), + .O(\total_cols[12]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \total_cols[4]_i_2 + (.I0(\time_control_regs[0] [4]), + .O(\total_cols[4]_i_2_n_0 )); + LUT1 #( + .INIT(2'h1)) + \total_cols[4]_i_3 + (.I0(\time_control_regs[0] [3]), + .O(\total_cols[4]_i_3_n_0 )); + LUT1 #( + .INIT(2'h1)) + \total_cols[4]_i_4 + (.I0(\time_control_regs[0] [2]), + .O(\total_cols[4]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \total_cols[4]_i_5 + (.I0(\time_control_regs[0] [1]), + .O(\total_cols[4]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \total_cols[8]_i_2 + (.I0(\time_control_regs[0] [8]), + .O(\total_cols[8]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \total_cols[8]_i_3 + (.I0(\time_control_regs[0] [7]), + .O(\total_cols[8]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \total_cols[8]_i_4 + (.I0(\time_control_regs[0] [6]), + .O(\total_cols[8]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \total_cols[8]_i_5 + (.I0(\time_control_regs[0] [5]), + .O(\total_cols[8]_i_5_n_0 )); + FDRE \total_cols_reg[0] + (.C(aclk), + .CE(1'b1), + .D(plusOp[0]), + .Q(total_cols[0]), + .R(1'b0)); + FDRE \total_cols_reg[10] + (.C(aclk), + .CE(1'b1), + .D(plusOp[10]), + .Q(total_cols[10]), + .R(1'b0)); + FDRE \total_cols_reg[11] + (.C(aclk), + .CE(1'b1), + .D(plusOp[11]), + .Q(total_cols[11]), + .R(1'b0)); + FDRE \total_cols_reg[12] + (.C(aclk), + .CE(1'b1), + .D(plusOp[12]), + .Q(total_cols[12]), + .R(1'b0)); + CARRY4 \total_cols_reg[12]_i_1 + (.CI(\total_cols_reg[8]_i_1_n_0 ), + .CO({\NLW_total_cols_reg[12]_i_1_CO_UNCONNECTED [3],\total_cols_reg[12]_i_1_n_1 ,\total_cols_reg[12]_i_1_n_2 ,\total_cols_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(plusOp[12:9]), + .S({\total_cols[12]_i_2_n_0 ,\total_cols[12]_i_3_n_0 ,\total_cols[12]_i_4_n_0 ,\total_cols[12]_i_5_n_0 })); + FDRE \total_cols_reg[1] + (.C(aclk), + .CE(1'b1), + .D(plusOp[1]), + .Q(total_cols[1]), + .R(1'b0)); + FDRE \total_cols_reg[2] + (.C(aclk), + .CE(1'b1), + .D(plusOp[2]), + .Q(total_cols[2]), + .R(1'b0)); + FDRE \total_cols_reg[3] + (.C(aclk), + .CE(1'b1), + .D(plusOp[3]), + .Q(total_cols[3]), + .R(1'b0)); + FDRE \total_cols_reg[4] + (.C(aclk), + .CE(1'b1), + .D(plusOp[4]), + .Q(total_cols[4]), + .R(1'b0)); + CARRY4 \total_cols_reg[4]_i_1 + (.CI(1'b0), + .CO({\total_cols_reg[4]_i_1_n_0 ,\total_cols_reg[4]_i_1_n_1 ,\total_cols_reg[4]_i_1_n_2 ,\total_cols_reg[4]_i_1_n_3 }), + .CYINIT(\time_control_regs[0] [0]), + .DI({1'b0,\time_control_regs[0] [3:2],1'b0}), + .O(plusOp[4:1]), + .S({\total_cols[4]_i_2_n_0 ,\total_cols[4]_i_3_n_0 ,\total_cols[4]_i_4_n_0 ,\total_cols[4]_i_5_n_0 })); + FDRE \total_cols_reg[5] + (.C(aclk), + .CE(1'b1), + .D(plusOp[5]), + .Q(total_cols[5]), + .R(1'b0)); + FDRE \total_cols_reg[6] + (.C(aclk), + .CE(1'b1), + .D(plusOp[6]), + .Q(total_cols[6]), + .R(1'b0)); + FDRE \total_cols_reg[7] + (.C(aclk), + .CE(1'b1), + .D(plusOp[7]), + .Q(total_cols[7]), + .R(1'b0)); + FDRE \total_cols_reg[8] + (.C(aclk), + .CE(1'b1), + .D(plusOp[8]), + .Q(total_cols[8]), + .R(1'b0)); + CARRY4 \total_cols_reg[8]_i_1 + (.CI(\total_cols_reg[4]_i_1_n_0 ), + .CO({\total_cols_reg[8]_i_1_n_0 ,\total_cols_reg[8]_i_1_n_1 ,\total_cols_reg[8]_i_1_n_2 ,\total_cols_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(plusOp[8:5]), + .S({\total_cols[8]_i_2_n_0 ,\total_cols[8]_i_3_n_0 ,\total_cols[8]_i_4_n_0 ,\total_cols[8]_i_5_n_0 })); + FDRE \total_cols_reg[9] + (.C(aclk), + .CE(1'b1), + .D(plusOp[9]), + .Q(total_cols[9]), + .R(1'b0)); + FDRE \total_rows_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\time_control_regs[0] [13]), + .Q(total_rows[0]), + .R(1'b0)); + FDRE \total_rows_reg[10] + (.C(aclk), + .CE(1'b1), + .D(\time_control_regs[0] [23]), + .Q(total_rows[10]), + .R(1'b0)); + FDRE \total_rows_reg[11] + (.C(aclk), + .CE(1'b1), + .D(\time_control_regs[0] [24]), + .Q(total_rows[11]), + .R(1'b0)); + FDRE \total_rows_reg[12] + (.C(aclk), + .CE(1'b1), + .D(\time_control_regs[0] [25]), + .Q(total_rows[12]), + .R(1'b0)); + FDRE \total_rows_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\time_control_regs[0] [14]), + .Q(total_rows[1]), + .R(1'b0)); + FDRE \total_rows_reg[2] + (.C(aclk), + .CE(1'b1), + .D(\time_control_regs[0] [15]), + .Q(total_rows[2]), + .R(1'b0)); + FDRE \total_rows_reg[3] + (.C(aclk), + .CE(1'b1), + .D(\time_control_regs[0] [16]), + .Q(total_rows[3]), + .R(1'b0)); + FDRE \total_rows_reg[4] + (.C(aclk), + .CE(1'b1), + .D(\time_control_regs[0] [17]), + .Q(total_rows[4]), + .R(1'b0)); + FDRE \total_rows_reg[5] + (.C(aclk), + .CE(1'b1), + .D(\time_control_regs[0] [18]), + .Q(total_rows[5]), + .R(1'b0)); + FDRE \total_rows_reg[6] + (.C(aclk), + .CE(1'b1), + .D(\time_control_regs[0] [19]), + .Q(total_rows[6]), + .R(1'b0)); + FDRE \total_rows_reg[7] + (.C(aclk), + .CE(1'b1), + .D(\time_control_regs[0] [20]), + .Q(total_rows[7]), + .R(1'b0)); + FDRE \total_rows_reg[8] + (.C(aclk), + .CE(1'b1), + .D(\time_control_regs[0] [21]), + .Q(total_rows[8]), + .R(1'b0)); + FDRE \total_rows_reg[9] + (.C(aclk), + .CE(1'b1), + .D(\time_control_regs[0] [22]), + .Q(total_rows[9]), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "axis_input_buffer" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_axis_input_buffer + (s_axis_video_tready, + vid_empty, + empty_match_reg, + \col_cnt_reg[12] , + reg_update, + Q, + SR, + master_en, + aclk, + fifo_rd_i_reg, + resetn_out, + \genr_control_regs[0] , + aclken, + s_axis_video_tvalid, + da); + output s_axis_video_tready; + output vid_empty; + output empty_match_reg; + output \col_cnt_reg[12] ; + output reg_update; + output [25:0]Q; + input [0:0]SR; + input master_en; + input aclk; + input fifo_rd_i_reg; + input resetn_out; + input [1:0]\genr_control_regs[0] ; + input aclken; + input s_axis_video_tvalid; + input [25:0]da; + + wire [25:0]Q; + wire [0:0]SR; + wire U_AXIS_SYNC_FIFO_n_2; + wire aclk; + wire aclken; + wire \col_cnt_reg[12] ; + wire [25:0]da; + wire empty_match_reg; + wire fifo_rd_i_reg; + wire [1:0]\genr_control_regs[0] ; + wire master_en; + wire reg_update; + wire resetn_out; + wire s_axis_video_tready; + wire s_axis_video_tvalid; + wire vid_empty; + + Arty_Z7_20_v_rgb2ycrcb_0_0_synch_fifo U_AXIS_SYNC_FIFO + (.Q(Q), + .SR(SR), + .aclk(aclk), + .aclken(aclken), + .\col_cnt_reg[12] (\col_cnt_reg[12] ), + .da(da), + .empty_match_reg_0(vid_empty), + .empty_match_reg_1(empty_match_reg), + .fifo_rd_i_reg(fifo_rd_i_reg), + .\genr_control_regs[0] (\genr_control_regs[0] ), + .reg_update(reg_update), + .resetn_out(resetn_out), + .s_axis_tready_int_reg(U_AXIS_SYNC_FIFO_n_2), + .s_axis_video_tready(s_axis_video_tready), + .s_axis_video_tvalid(s_axis_video_tvalid)); + FDRE s_axis_tready_int_reg + (.C(aclk), + .CE(master_en), + .D(U_AXIS_SYNC_FIFO_n_2), + .Q(s_axis_video_tready), + .R(SR)); +endmodule + +(* ORIG_REF_NAME = "axis_output_buffer" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_axis_output_buffer + (\write_ptr_int_reg[0] , + \col_cnt_reg[12] , + \col_cnt_reg[12]_0 , + \col_cnt_reg[12]_1 , + m_axis_video_tvalid, + Q, + SR, + aclk, + m_axis_video_tready, + aclken_0, + \genr_control_regs[0] , + aclken, + empty_match_reg, + empty_match_reg_0, + CO, + wen, + fifo_wr_i, + core_d_out, + eol_late_i_reg, + da); + output \write_ptr_int_reg[0] ; + output \col_cnt_reg[12] ; + output \col_cnt_reg[12]_0 ; + output \col_cnt_reg[12]_1 ; + output m_axis_video_tvalid; + output [25:0]Q; + input [0:0]SR; + input aclk; + input m_axis_video_tready; + input aclken_0; + input [0:0]\genr_control_regs[0] ; + input aclken; + input empty_match_reg; + input empty_match_reg_0; + input [0:0]CO; + input wen; + input fifo_wr_i; + input core_d_out; + input eol_late_i_reg; + input [25:0]da; + + wire [0:0]CO; + wire [25:0]Q; + wire [0:0]SR; + wire aclk; + wire aclken; + wire aclken_0; + wire \col_cnt_reg[12] ; + wire \col_cnt_reg[12]_0 ; + wire \col_cnt_reg[12]_1 ; + wire core_d_out; + wire [25:0]da; + wire empty_match_reg; + wire empty_match_reg_0; + wire eol_late_i_reg; + wire fifo_wr_i; + wire [0:0]\genr_control_regs[0] ; + wire m_axis_video_tready; + wire m_axis_video_tvalid; + wire wen; + wire \write_ptr_int_reg[0] ; + + Arty_Z7_20_v_rgb2ycrcb_0_0_synch_fifo_fallthru UOSD_AXIS_SYNC_FIFO + (.CO(CO), + .Q(Q), + .SR(SR), + .aclk(aclk), + .aclken(aclken), + .aclken_0(aclken_0), + .\col_cnt_reg[12] (\col_cnt_reg[12] ), + .\col_cnt_reg[12]_0 (\col_cnt_reg[12]_0 ), + .\col_cnt_reg[12]_1 (\col_cnt_reg[12]_1 ), + .core_d_out(core_d_out), + .da(da), + .empty_match_reg(empty_match_reg), + .empty_match_reg_0(empty_match_reg_0), + .eol_late_i_reg(eol_late_i_reg), + .fifo_wr_i(fifo_wr_i), + .\genr_control_regs[0] (\genr_control_regs[0] ), + .m_axis_video_tready(m_axis_video_tready), + .m_axis_video_tvalid(m_axis_video_tvalid), + .wen(wen), + .\write_ptr_int_reg[0]_0 (\write_ptr_int_reg[0] )); +endmodule + +(* ORIG_REF_NAME = "delay" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_delay + (y_intb, + E, + Q, + aclk); + output [7:0]y_intb; + input [0:0]E; + input [7:0]Q; + input aclk; + + wire [0:0]E; + wire [7:0]Q; + wire aclk; + wire \needs_delay.shift_register_reg[3][0]_srl3_n_0 ; + wire \needs_delay.shift_register_reg[3][1]_srl3_n_0 ; + wire \needs_delay.shift_register_reg[3][2]_srl3_n_0 ; + wire \needs_delay.shift_register_reg[3][3]_srl3_n_0 ; + wire \needs_delay.shift_register_reg[3][4]_srl3_n_0 ; + wire \needs_delay.shift_register_reg[3][5]_srl3_n_0 ; + wire \needs_delay.shift_register_reg[3][6]_srl3_n_0 ; + wire \needs_delay.shift_register_reg[3][7]_srl3_n_0 ; + wire [7:0]y_intb; + + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3][0]_srl3 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[3][0]_srl3 + (.A0(1'b0), + .A1(1'b1), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(Q[0]), + .Q(\needs_delay.shift_register_reg[3][0]_srl3_n_0 )); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3][1]_srl3 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[3][1]_srl3 + (.A0(1'b0), + .A1(1'b1), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(Q[1]), + .Q(\needs_delay.shift_register_reg[3][1]_srl3_n_0 )); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3][2]_srl3 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[3][2]_srl3 + (.A0(1'b0), + .A1(1'b1), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(Q[2]), + .Q(\needs_delay.shift_register_reg[3][2]_srl3_n_0 )); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3][3]_srl3 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[3][3]_srl3 + (.A0(1'b0), + .A1(1'b1), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(Q[3]), + .Q(\needs_delay.shift_register_reg[3][3]_srl3_n_0 )); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3][4]_srl3 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[3][4]_srl3 + (.A0(1'b0), + .A1(1'b1), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(Q[4]), + .Q(\needs_delay.shift_register_reg[3][4]_srl3_n_0 )); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3][5]_srl3 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[3][5]_srl3 + (.A0(1'b0), + .A1(1'b1), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(Q[5]), + .Q(\needs_delay.shift_register_reg[3][5]_srl3_n_0 )); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3][6]_srl3 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[3][6]_srl3 + (.A0(1'b0), + .A1(1'b1), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(Q[6]), + .Q(\needs_delay.shift_register_reg[3][6]_srl3_n_0 )); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3][7]_srl3 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[3][7]_srl3 + (.A0(1'b0), + .A1(1'b1), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(Q[7]), + .Q(\needs_delay.shift_register_reg[3][7]_srl3_n_0 )); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[4][0] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[3][0]_srl3_n_0 ), + .Q(y_intb[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[4][1] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[3][1]_srl3_n_0 ), + .Q(y_intb[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[4][2] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[3][2]_srl3_n_0 ), + .Q(y_intb[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[4][3] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[3][3]_srl3_n_0 ), + .Q(y_intb[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[4][4] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[3][4]_srl3_n_0 ), + .Q(y_intb[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[4][5] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[3][5]_srl3_n_0 ), + .Q(y_intb[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[4][6] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[3][6]_srl3_n_0 ), + .Q(y_intb[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[4][7] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[3][7]_srl3_n_0 ), + .Q(y_intb[7]), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "delay" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_delay__parameterized0 + (D, + CO, + E, + Q, + aclk, + s, + \needs_delay.shift_register_reg[1][0] ); + output [7:0]D; + output [0:0]CO; + input [0:0]E; + input [7:0]Q; + input aclk; + input [6:0]s; + input \needs_delay.shift_register_reg[1][0] ; + + wire [0:0]CO; + wire [7:0]D; + wire [0:0]E; + wire [7:0]Q; + wire aclk; + wire [7:0]b_int; + wire \needs_delay.shift_register[1][3]_i_3__2_n_0 ; + wire \needs_delay.shift_register[1][3]_i_4__2_n_0 ; + wire \needs_delay.shift_register[1][3]_i_5__2_n_0 ; + wire \needs_delay.shift_register[1][3]_i_6__0_n_0 ; + wire \needs_delay.shift_register[1][7]_i_2__2_n_0 ; + wire \needs_delay.shift_register[1][7]_i_3__2_n_0 ; + wire \needs_delay.shift_register[1][7]_i_4__2_n_0 ; + wire \needs_delay.shift_register[1][7]_i_5__2_n_0 ; + wire \needs_delay.shift_register_reg[1][0] ; + wire \needs_delay.shift_register_reg[1][3]_i_1__1_n_0 ; + wire \needs_delay.shift_register_reg[1][3]_i_1__1_n_1 ; + wire \needs_delay.shift_register_reg[1][3]_i_1__1_n_2 ; + wire \needs_delay.shift_register_reg[1][3]_i_1__1_n_3 ; + wire \needs_delay.shift_register_reg[1][7]_i_1__1_n_1 ; + wire \needs_delay.shift_register_reg[1][7]_i_1__1_n_2 ; + wire \needs_delay.shift_register_reg[1][7]_i_1__1_n_3 ; + wire \needs_delay.shift_register_reg[4][0]_srl4_n_0 ; + wire \needs_delay.shift_register_reg[4][1]_srl4_n_0 ; + wire \needs_delay.shift_register_reg[4][2]_srl4_n_0 ; + wire \needs_delay.shift_register_reg[4][3]_srl4_n_0 ; + wire \needs_delay.shift_register_reg[4][4]_srl4_n_0 ; + wire \needs_delay.shift_register_reg[4][5]_srl4_n_0 ; + wire \needs_delay.shift_register_reg[4][6]_srl4_n_0 ; + wire \needs_delay.shift_register_reg[4][7]_srl4_n_0 ; + wire [6:0]s; + + LUT2 #( + .INIT(4'h9)) + \needs_delay.shift_register[1][3]_i_3__2 + (.I0(b_int[3]), + .I1(s[2]), + .O(\needs_delay.shift_register[1][3]_i_3__2_n_0 )); + LUT2 #( + .INIT(4'h9)) + \needs_delay.shift_register[1][3]_i_4__2 + (.I0(b_int[2]), + .I1(s[1]), + .O(\needs_delay.shift_register[1][3]_i_4__2_n_0 )); + LUT2 #( + .INIT(4'h9)) + \needs_delay.shift_register[1][3]_i_5__2 + (.I0(b_int[1]), + .I1(s[0]), + .O(\needs_delay.shift_register[1][3]_i_5__2_n_0 )); + LUT1 #( + .INIT(2'h1)) + \needs_delay.shift_register[1][3]_i_6__0 + (.I0(b_int[0]), + .O(\needs_delay.shift_register[1][3]_i_6__0_n_0 )); + LUT2 #( + .INIT(4'h9)) + \needs_delay.shift_register[1][7]_i_2__2 + (.I0(b_int[7]), + .I1(s[6]), + .O(\needs_delay.shift_register[1][7]_i_2__2_n_0 )); + LUT2 #( + .INIT(4'h9)) + \needs_delay.shift_register[1][7]_i_3__2 + (.I0(b_int[6]), + .I1(s[5]), + .O(\needs_delay.shift_register[1][7]_i_3__2_n_0 )); + LUT2 #( + .INIT(4'h9)) + \needs_delay.shift_register[1][7]_i_4__2 + (.I0(b_int[5]), + .I1(s[4]), + .O(\needs_delay.shift_register[1][7]_i_4__2_n_0 )); + LUT2 #( + .INIT(4'h9)) + \needs_delay.shift_register[1][7]_i_5__2 + (.I0(b_int[4]), + .I1(s[3]), + .O(\needs_delay.shift_register[1][7]_i_5__2_n_0 )); + CARRY4 \needs_delay.shift_register_reg[1][3]_i_1__1 + (.CI(1'b0), + .CO({\needs_delay.shift_register_reg[1][3]_i_1__1_n_0 ,\needs_delay.shift_register_reg[1][3]_i_1__1_n_1 ,\needs_delay.shift_register_reg[1][3]_i_1__1_n_2 ,\needs_delay.shift_register_reg[1][3]_i_1__1_n_3 }), + .CYINIT(\needs_delay.shift_register_reg[1][0] ), + .DI(b_int[3:0]), + .O(D[3:0]), + .S({\needs_delay.shift_register[1][3]_i_3__2_n_0 ,\needs_delay.shift_register[1][3]_i_4__2_n_0 ,\needs_delay.shift_register[1][3]_i_5__2_n_0 ,\needs_delay.shift_register[1][3]_i_6__0_n_0 })); + CARRY4 \needs_delay.shift_register_reg[1][7]_i_1__1 + (.CI(\needs_delay.shift_register_reg[1][3]_i_1__1_n_0 ), + .CO({CO,\needs_delay.shift_register_reg[1][7]_i_1__1_n_1 ,\needs_delay.shift_register_reg[1][7]_i_1__1_n_2 ,\needs_delay.shift_register_reg[1][7]_i_1__1_n_3 }), + .CYINIT(1'b0), + .DI(b_int[7:4]), + .O(D[7:4]), + .S({\needs_delay.shift_register[1][7]_i_2__2_n_0 ,\needs_delay.shift_register[1][7]_i_3__2_n_0 ,\needs_delay.shift_register[1][7]_i_4__2_n_0 ,\needs_delay.shift_register[1][7]_i_5__2_n_0 })); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4][0]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[4][0]_srl4 + (.A0(1'b1), + .A1(1'b1), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(Q[0]), + .Q(\needs_delay.shift_register_reg[4][0]_srl4_n_0 )); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4][1]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[4][1]_srl4 + (.A0(1'b1), + .A1(1'b1), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(Q[1]), + .Q(\needs_delay.shift_register_reg[4][1]_srl4_n_0 )); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4][2]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[4][2]_srl4 + (.A0(1'b1), + .A1(1'b1), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(Q[2]), + .Q(\needs_delay.shift_register_reg[4][2]_srl4_n_0 )); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4][3]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[4][3]_srl4 + (.A0(1'b1), + .A1(1'b1), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(Q[3]), + .Q(\needs_delay.shift_register_reg[4][3]_srl4_n_0 )); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4][4]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[4][4]_srl4 + (.A0(1'b1), + .A1(1'b1), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(Q[4]), + .Q(\needs_delay.shift_register_reg[4][4]_srl4_n_0 )); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4][5]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[4][5]_srl4 + (.A0(1'b1), + .A1(1'b1), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(Q[5]), + .Q(\needs_delay.shift_register_reg[4][5]_srl4_n_0 )); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4][6]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[4][6]_srl4 + (.A0(1'b1), + .A1(1'b1), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(Q[6]), + .Q(\needs_delay.shift_register_reg[4][6]_srl4_n_0 )); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4][7]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[4][7]_srl4 + (.A0(1'b1), + .A1(1'b1), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(Q[7]), + .Q(\needs_delay.shift_register_reg[4][7]_srl4_n_0 )); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[5][0] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[4][0]_srl4_n_0 ), + .Q(b_int[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[5][1] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[4][1]_srl4_n_0 ), + .Q(b_int[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[5][2] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[4][2]_srl4_n_0 ), + .Q(b_int[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[5][3] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[4][3]_srl4_n_0 ), + .Q(b_int[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[5][4] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[4][4]_srl4_n_0 ), + .Q(b_int[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[5][5] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[4][5]_srl4_n_0 ), + .Q(b_int[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[5][6] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[4][6]_srl4_n_0 ), + .Q(b_int[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[5][7] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[4][7]_srl4_n_0 ), + .Q(b_int[7]), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "delay" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_delay__parameterized1 + (D, + \needs_delay.shift_register_reg[1][10] , + E, + Q, + aclk, + s, + \needs_delay.shift_register_reg[1][0] ); + output [7:0]D; + output [0:0]\needs_delay.shift_register_reg[1][10] ; + input [0:0]E; + input [7:0]Q; + input aclk; + input [6:0]s; + input \needs_delay.shift_register_reg[1][0] ; + + wire [7:0]D; + wire [0:0]E; + wire [7:0]Q; + wire aclk; + wire \needs_delay.shift_register[1][3]_i_2__2_n_0 ; + wire \needs_delay.shift_register[1][3]_i_3__1_n_0 ; + wire \needs_delay.shift_register[1][3]_i_4__1_n_0 ; + wire \needs_delay.shift_register[1][3]_i_5__0_n_0 ; + wire \needs_delay.shift_register[1][7]_i_2__1_n_0 ; + wire \needs_delay.shift_register[1][7]_i_3__1_n_0 ; + wire \needs_delay.shift_register[1][7]_i_4__1_n_0 ; + wire \needs_delay.shift_register[1][7]_i_5__1_n_0 ; + wire \needs_delay.shift_register_reg[1][0] ; + wire [0:0]\needs_delay.shift_register_reg[1][10] ; + wire \needs_delay.shift_register_reg[1][3]_i_1__2_n_0 ; + wire \needs_delay.shift_register_reg[1][3]_i_1__2_n_1 ; + wire \needs_delay.shift_register_reg[1][3]_i_1__2_n_2 ; + wire \needs_delay.shift_register_reg[1][3]_i_1__2_n_3 ; + wire \needs_delay.shift_register_reg[1][7]_i_1__2_n_1 ; + wire \needs_delay.shift_register_reg[1][7]_i_1__2_n_2 ; + wire \needs_delay.shift_register_reg[1][7]_i_1__2_n_3 ; + wire \needs_delay.shift_register_reg[4][0]_srl4_n_0 ; + wire \needs_delay.shift_register_reg[4][1]_srl4_n_0 ; + wire \needs_delay.shift_register_reg[4][2]_srl4_n_0 ; + wire \needs_delay.shift_register_reg[4][3]_srl4_n_0 ; + wire \needs_delay.shift_register_reg[4][4]_srl4_n_0 ; + wire \needs_delay.shift_register_reg[4][5]_srl4_n_0 ; + wire \needs_delay.shift_register_reg[4][6]_srl4_n_0 ; + wire \needs_delay.shift_register_reg[4][7]_srl4_n_0 ; + wire [7:0]r_int; + wire [6:0]s; + + LUT2 #( + .INIT(4'h9)) + \needs_delay.shift_register[1][3]_i_2__2 + (.I0(r_int[3]), + .I1(s[2]), + .O(\needs_delay.shift_register[1][3]_i_2__2_n_0 )); + LUT2 #( + .INIT(4'h9)) + \needs_delay.shift_register[1][3]_i_3__1 + (.I0(r_int[2]), + .I1(s[1]), + .O(\needs_delay.shift_register[1][3]_i_3__1_n_0 )); + LUT2 #( + .INIT(4'h9)) + \needs_delay.shift_register[1][3]_i_4__1 + (.I0(r_int[1]), + .I1(s[0]), + .O(\needs_delay.shift_register[1][3]_i_4__1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \needs_delay.shift_register[1][3]_i_5__0 + (.I0(r_int[0]), + .O(\needs_delay.shift_register[1][3]_i_5__0_n_0 )); + LUT2 #( + .INIT(4'h9)) + \needs_delay.shift_register[1][7]_i_2__1 + (.I0(r_int[7]), + .I1(s[6]), + .O(\needs_delay.shift_register[1][7]_i_2__1_n_0 )); + LUT2 #( + .INIT(4'h9)) + \needs_delay.shift_register[1][7]_i_3__1 + (.I0(r_int[6]), + .I1(s[5]), + .O(\needs_delay.shift_register[1][7]_i_3__1_n_0 )); + LUT2 #( + .INIT(4'h9)) + \needs_delay.shift_register[1][7]_i_4__1 + (.I0(r_int[5]), + .I1(s[4]), + .O(\needs_delay.shift_register[1][7]_i_4__1_n_0 )); + LUT2 #( + .INIT(4'h9)) + \needs_delay.shift_register[1][7]_i_5__1 + (.I0(r_int[4]), + .I1(s[3]), + .O(\needs_delay.shift_register[1][7]_i_5__1_n_0 )); + CARRY4 \needs_delay.shift_register_reg[1][3]_i_1__2 + (.CI(1'b0), + .CO({\needs_delay.shift_register_reg[1][3]_i_1__2_n_0 ,\needs_delay.shift_register_reg[1][3]_i_1__2_n_1 ,\needs_delay.shift_register_reg[1][3]_i_1__2_n_2 ,\needs_delay.shift_register_reg[1][3]_i_1__2_n_3 }), + .CYINIT(\needs_delay.shift_register_reg[1][0] ), + .DI(r_int[3:0]), + .O(D[3:0]), + .S({\needs_delay.shift_register[1][3]_i_2__2_n_0 ,\needs_delay.shift_register[1][3]_i_3__1_n_0 ,\needs_delay.shift_register[1][3]_i_4__1_n_0 ,\needs_delay.shift_register[1][3]_i_5__0_n_0 })); + CARRY4 \needs_delay.shift_register_reg[1][7]_i_1__2 + (.CI(\needs_delay.shift_register_reg[1][3]_i_1__2_n_0 ), + .CO({\needs_delay.shift_register_reg[1][10] ,\needs_delay.shift_register_reg[1][7]_i_1__2_n_1 ,\needs_delay.shift_register_reg[1][7]_i_1__2_n_2 ,\needs_delay.shift_register_reg[1][7]_i_1__2_n_3 }), + .CYINIT(1'b0), + .DI(r_int[7:4]), + .O(D[7:4]), + .S({\needs_delay.shift_register[1][7]_i_2__1_n_0 ,\needs_delay.shift_register[1][7]_i_3__1_n_0 ,\needs_delay.shift_register[1][7]_i_4__1_n_0 ,\needs_delay.shift_register[1][7]_i_5__1_n_0 })); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4][0]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[4][0]_srl4 + (.A0(1'b1), + .A1(1'b1), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(Q[0]), + .Q(\needs_delay.shift_register_reg[4][0]_srl4_n_0 )); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4][1]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[4][1]_srl4 + (.A0(1'b1), + .A1(1'b1), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(Q[1]), + .Q(\needs_delay.shift_register_reg[4][1]_srl4_n_0 )); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4][2]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[4][2]_srl4 + (.A0(1'b1), + .A1(1'b1), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(Q[2]), + .Q(\needs_delay.shift_register_reg[4][2]_srl4_n_0 )); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4][3]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[4][3]_srl4 + (.A0(1'b1), + .A1(1'b1), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(Q[3]), + .Q(\needs_delay.shift_register_reg[4][3]_srl4_n_0 )); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4][4]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[4][4]_srl4 + (.A0(1'b1), + .A1(1'b1), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(Q[4]), + .Q(\needs_delay.shift_register_reg[4][4]_srl4_n_0 )); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4][5]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[4][5]_srl4 + (.A0(1'b1), + .A1(1'b1), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(Q[5]), + .Q(\needs_delay.shift_register_reg[4][5]_srl4_n_0 )); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4][6]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[4][6]_srl4 + (.A0(1'b1), + .A1(1'b1), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(Q[6]), + .Q(\needs_delay.shift_register_reg[4][6]_srl4_n_0 )); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4][7]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[4][7]_srl4 + (.A0(1'b1), + .A1(1'b1), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(Q[7]), + .Q(\needs_delay.shift_register_reg[4][7]_srl4_n_0 )); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[5][0] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[4][0]_srl4_n_0 ), + .Q(r_int[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[5][1] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[4][1]_srl4_n_0 ), + .Q(r_int[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[5][2] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[4][2]_srl4_n_0 ), + .Q(r_int[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[5][3] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[4][3]_srl4_n_0 ), + .Q(r_int[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[5][4] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[4][4]_srl4_n_0 ), + .Q(r_int[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[5][5] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[4][5]_srl4_n_0 ), + .Q(r_int[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[5][6] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[4][6]_srl4_n_0 ), + .Q(r_int[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[5][7] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[4][7]_srl4_n_0 ), + .Q(r_int[7]), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "delay" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_delay__parameterized2 + (\needs_delay.shift_register_reg[1][9] , + \needs_delay.shift_register_reg[1][8] , + \needs_delay.shift_register_reg[1][7] , + \needs_delay.shift_register_reg[1][6] , + \needs_delay.shift_register_reg[1][5] , + \needs_delay.shift_register_reg[1][4] , + \needs_delay.shift_register_reg[1][3] , + \needs_delay.shift_register_reg[1][2] , + \needs_delay.shift_register_reg[1][1] , + \needs_delay.shift_register_reg[1][0] , + \needs_delay.shift_register_reg[1][9]_0 , + \needs_delay.shift_register_reg[1][9]_1 , + S, + DI, + E, + s, + aclk, + \core_control_regs[0] ); + output \needs_delay.shift_register_reg[1][9] ; + output \needs_delay.shift_register_reg[1][8] ; + output \needs_delay.shift_register_reg[1][7] ; + output \needs_delay.shift_register_reg[1][6] ; + output \needs_delay.shift_register_reg[1][5] ; + output \needs_delay.shift_register_reg[1][4] ; + output \needs_delay.shift_register_reg[1][3] ; + output \needs_delay.shift_register_reg[1][2] ; + output \needs_delay.shift_register_reg[1][1] ; + output \needs_delay.shift_register_reg[1][0] ; + output [0:0]\needs_delay.shift_register_reg[1][9]_0 ; + output [0:0]\needs_delay.shift_register_reg[1][9]_1 ; + output [3:0]S; + output [3:0]DI; + input [0:0]E; + input [9:0]s; + input aclk; + input [7:0]\core_control_regs[0] ; + + wire [3:0]DI; + wire [0:0]E; + wire [3:0]S; + wire aclk; + wire [7:0]\core_control_regs[0] ; + wire \needs_delay.shift_register_reg[1][0] ; + wire \needs_delay.shift_register_reg[1][1] ; + wire \needs_delay.shift_register_reg[1][2] ; + wire \needs_delay.shift_register_reg[1][3] ; + wire \needs_delay.shift_register_reg[1][4] ; + wire \needs_delay.shift_register_reg[1][5] ; + wire \needs_delay.shift_register_reg[1][6] ; + wire \needs_delay.shift_register_reg[1][7] ; + wire \needs_delay.shift_register_reg[1][8] ; + wire \needs_delay.shift_register_reg[1][9] ; + wire [0:0]\needs_delay.shift_register_reg[1][9]_0 ; + wire [0:0]\needs_delay.shift_register_reg[1][9]_1 ; + wire \needs_delay.shift_register_reg[2][0]_srl2_n_0 ; + wire \needs_delay.shift_register_reg[2][1]_srl2_n_0 ; + wire \needs_delay.shift_register_reg[2][2]_srl2_n_0 ; + wire \needs_delay.shift_register_reg[2][3]_srl2_n_0 ; + wire \needs_delay.shift_register_reg[2][4]_srl2_n_0 ; + wire \needs_delay.shift_register_reg[2][5]_srl2_n_0 ; + wire \needs_delay.shift_register_reg[2][6]_srl2_n_0 ; + wire \needs_delay.shift_register_reg[2][7]_srl2_n_0 ; + wire \needs_delay.shift_register_reg[2][8]_srl2_n_0 ; + wire \needs_delay.shift_register_reg[2][9]_srl2_n_0 ; + wire [9:0]s; + + LUT2 #( + .INIT(4'h2)) + gtOp_carry__0_i_1__0 + (.I0(\needs_delay.shift_register_reg[1][8] ), + .I1(\needs_delay.shift_register_reg[1][9] ), + .O(\needs_delay.shift_register_reg[1][9]_0 )); + LUT2 #( + .INIT(4'h1)) + gtOp_carry__0_i_2__0 + (.I0(\needs_delay.shift_register_reg[1][8] ), + .I1(\needs_delay.shift_register_reg[1][9] ), + .O(\needs_delay.shift_register_reg[1][9]_1 )); + LUT4 #( + .INIT(16'h2F02)) + gtOp_carry_i_1__0 + (.I0(\needs_delay.shift_register_reg[1][6] ), + .I1(\core_control_regs[0] [6]), + .I2(\core_control_regs[0] [7]), + .I3(\needs_delay.shift_register_reg[1][7] ), + .O(DI[3])); + LUT4 #( + .INIT(16'h2F02)) + gtOp_carry_i_2__0 + (.I0(\needs_delay.shift_register_reg[1][4] ), + .I1(\core_control_regs[0] [4]), + .I2(\core_control_regs[0] [5]), + .I3(\needs_delay.shift_register_reg[1][5] ), + .O(DI[2])); + LUT4 #( + .INIT(16'h2F02)) + gtOp_carry_i_3__0 + (.I0(\needs_delay.shift_register_reg[1][2] ), + .I1(\core_control_regs[0] [2]), + .I2(\core_control_regs[0] [3]), + .I3(\needs_delay.shift_register_reg[1][3] ), + .O(DI[1])); + LUT4 #( + .INIT(16'h2F02)) + gtOp_carry_i_4__0 + (.I0(\needs_delay.shift_register_reg[1][0] ), + .I1(\core_control_regs[0] [0]), + .I2(\core_control_regs[0] [1]), + .I3(\needs_delay.shift_register_reg[1][1] ), + .O(DI[0])); + LUT4 #( + .INIT(16'h9009)) + gtOp_carry_i_5__0 + (.I0(\needs_delay.shift_register_reg[1][6] ), + .I1(\core_control_regs[0] [6]), + .I2(\needs_delay.shift_register_reg[1][7] ), + .I3(\core_control_regs[0] [7]), + .O(S[3])); + LUT4 #( + .INIT(16'h9009)) + gtOp_carry_i_6__0 + (.I0(\needs_delay.shift_register_reg[1][4] ), + .I1(\core_control_regs[0] [4]), + .I2(\needs_delay.shift_register_reg[1][5] ), + .I3(\core_control_regs[0] [5]), + .O(S[2])); + LUT4 #( + .INIT(16'h9009)) + gtOp_carry_i_7__0 + (.I0(\needs_delay.shift_register_reg[1][2] ), + .I1(\core_control_regs[0] [2]), + .I2(\needs_delay.shift_register_reg[1][3] ), + .I3(\core_control_regs[0] [3]), + .O(S[1])); + LUT4 #( + .INIT(16'h9009)) + gtOp_carry_i_8__0 + (.I0(\needs_delay.shift_register_reg[1][0] ), + .I1(\core_control_regs[0] [0]), + .I2(\needs_delay.shift_register_reg[1][1] ), + .I3(\core_control_regs[0] [1]), + .O(S[0])); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2][0]_srl2 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[2][0]_srl2 + (.A0(1'b1), + .A1(1'b0), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(s[0]), + .Q(\needs_delay.shift_register_reg[2][0]_srl2_n_0 )); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2][1]_srl2 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[2][1]_srl2 + (.A0(1'b1), + .A1(1'b0), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(s[1]), + .Q(\needs_delay.shift_register_reg[2][1]_srl2_n_0 )); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2][2]_srl2 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[2][2]_srl2 + (.A0(1'b1), + .A1(1'b0), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(s[2]), + .Q(\needs_delay.shift_register_reg[2][2]_srl2_n_0 )); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2][3]_srl2 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[2][3]_srl2 + (.A0(1'b1), + .A1(1'b0), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(s[3]), + .Q(\needs_delay.shift_register_reg[2][3]_srl2_n_0 )); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2][4]_srl2 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[2][4]_srl2 + (.A0(1'b1), + .A1(1'b0), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(s[4]), + .Q(\needs_delay.shift_register_reg[2][4]_srl2_n_0 )); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2][5]_srl2 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[2][5]_srl2 + (.A0(1'b1), + .A1(1'b0), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(s[5]), + .Q(\needs_delay.shift_register_reg[2][5]_srl2_n_0 )); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2][6]_srl2 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[2][6]_srl2 + (.A0(1'b1), + .A1(1'b0), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(s[6]), + .Q(\needs_delay.shift_register_reg[2][6]_srl2_n_0 )); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2][7]_srl2 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[2][7]_srl2 + (.A0(1'b1), + .A1(1'b0), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(s[7]), + .Q(\needs_delay.shift_register_reg[2][7]_srl2_n_0 )); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2][8]_srl2 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[2][8]_srl2 + (.A0(1'b1), + .A1(1'b0), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(s[8]), + .Q(\needs_delay.shift_register_reg[2][8]_srl2_n_0 )); + (* srl_bus_name = "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2] " *) + (* srl_name = "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2][9]_srl2 " *) + SRL16E #( + .INIT(16'h0000)) + \needs_delay.shift_register_reg[2][9]_srl2 + (.A0(1'b1), + .A1(1'b0), + .A2(1'b0), + .A3(1'b0), + .CE(E), + .CLK(aclk), + .D(s[9]), + .Q(\needs_delay.shift_register_reg[2][9]_srl2_n_0 )); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[3][0] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[2][0]_srl2_n_0 ), + .Q(\needs_delay.shift_register_reg[1][0] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[3][1] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[2][1]_srl2_n_0 ), + .Q(\needs_delay.shift_register_reg[1][1] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[3][2] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[2][2]_srl2_n_0 ), + .Q(\needs_delay.shift_register_reg[1][2] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[3][3] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[2][3]_srl2_n_0 ), + .Q(\needs_delay.shift_register_reg[1][3] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[3][4] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[2][4]_srl2_n_0 ), + .Q(\needs_delay.shift_register_reg[1][4] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[3][5] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[2][5]_srl2_n_0 ), + .Q(\needs_delay.shift_register_reg[1][5] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[3][6] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[2][6]_srl2_n_0 ), + .Q(\needs_delay.shift_register_reg[1][6] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[3][7] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[2][7]_srl2_n_0 ), + .Q(\needs_delay.shift_register_reg[1][7] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[3][8] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[2][8]_srl2_n_0 ), + .Q(\needs_delay.shift_register_reg[1][8] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[3][9] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[2][9]_srl2_n_0 ), + .Q(\needs_delay.shift_register_reg[1][9] ), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "delay_sclr" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr + (out_s, + p_0_in, + Q, + sclr, + E, + aclk); + output [8:0]out_s; + output [0:0]p_0_in; + input [15:0]Q; + input sclr; + input [0:0]E; + input aclk; + + wire [0:0]E; + wire [15:0]Q; + wire aclk; + wire \needs_delay.shift_register[1][3]_i_3__0_n_0 ; + wire \needs_delay.shift_register[1][3]_i_4__0_n_0 ; + wire \needs_delay.shift_register[1][3]_i_5__1_n_0 ; + wire \needs_delay.shift_register[1][3]_i_6_n_0 ; + wire \needs_delay.shift_register[1][7]_i_2_n_0 ; + wire \needs_delay.shift_register[1][7]_i_3_n_0 ; + wire \needs_delay.shift_register[1][7]_i_4_n_0 ; + wire \needs_delay.shift_register[1][7]_i_5_n_0 ; + wire \needs_delay.shift_register_reg[1][3]_i_1_n_0 ; + wire \needs_delay.shift_register_reg[1][3]_i_1_n_1 ; + wire \needs_delay.shift_register_reg[1][3]_i_1_n_2 ; + wire \needs_delay.shift_register_reg[1][3]_i_1_n_3 ; + wire \needs_delay.shift_register_reg[1][3]_i_1_n_4 ; + wire \needs_delay.shift_register_reg[1][3]_i_1_n_5 ; + wire \needs_delay.shift_register_reg[1][3]_i_1_n_6 ; + wire \needs_delay.shift_register_reg[1][3]_i_1_n_7 ; + wire \needs_delay.shift_register_reg[1][7]_i_1_n_0 ; + wire \needs_delay.shift_register_reg[1][7]_i_1_n_1 ; + wire \needs_delay.shift_register_reg[1][7]_i_1_n_2 ; + wire \needs_delay.shift_register_reg[1][7]_i_1_n_3 ; + wire \needs_delay.shift_register_reg[1][7]_i_1_n_4 ; + wire \needs_delay.shift_register_reg[1][7]_i_1_n_5 ; + wire \needs_delay.shift_register_reg[1][7]_i_1_n_6 ; + wire \needs_delay.shift_register_reg[1][7]_i_1_n_7 ; + wire \needs_delay.shift_register_reg[1][8]_i_1_n_7 ; + wire [8:0]out_s; + wire [0:0]p_0_in; + wire sclr; + wire [3:0]\NLW_needs_delay.shift_register_reg[1][8]_i_1_CO_UNCONNECTED ; + wire [3:1]\NLW_needs_delay.shift_register_reg[1][8]_i_1_O_UNCONNECTED ; + + LUT1 #( + .INIT(2'h1)) + \needs_delay.shift_register[1][3]_i_2 + (.I0(Q[0]), + .O(p_0_in)); + LUT2 #( + .INIT(4'h9)) + \needs_delay.shift_register[1][3]_i_3__0 + (.I0(Q[11]), + .I1(Q[3]), + .O(\needs_delay.shift_register[1][3]_i_3__0_n_0 )); + LUT2 #( + .INIT(4'h9)) + \needs_delay.shift_register[1][3]_i_4__0 + (.I0(Q[10]), + .I1(Q[2]), + .O(\needs_delay.shift_register[1][3]_i_4__0_n_0 )); + LUT2 #( + .INIT(4'h9)) + \needs_delay.shift_register[1][3]_i_5__1 + (.I0(Q[9]), + .I1(Q[1]), + .O(\needs_delay.shift_register[1][3]_i_5__1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \needs_delay.shift_register[1][3]_i_6 + (.I0(Q[8]), + .O(\needs_delay.shift_register[1][3]_i_6_n_0 )); + LUT2 #( + .INIT(4'h9)) + \needs_delay.shift_register[1][7]_i_2 + (.I0(Q[15]), + .I1(Q[7]), + .O(\needs_delay.shift_register[1][7]_i_2_n_0 )); + LUT2 #( + .INIT(4'h9)) + \needs_delay.shift_register[1][7]_i_3 + (.I0(Q[14]), + .I1(Q[6]), + .O(\needs_delay.shift_register[1][7]_i_3_n_0 )); + LUT2 #( + .INIT(4'h9)) + \needs_delay.shift_register[1][7]_i_4 + (.I0(Q[13]), + .I1(Q[5]), + .O(\needs_delay.shift_register[1][7]_i_4_n_0 )); + LUT2 #( + .INIT(4'h9)) + \needs_delay.shift_register[1][7]_i_5 + (.I0(Q[12]), + .I1(Q[4]), + .O(\needs_delay.shift_register[1][7]_i_5_n_0 )); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][0] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[1][3]_i_1_n_7 ), + .Q(out_s[0]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][1] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[1][3]_i_1_n_6 ), + .Q(out_s[1]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][2] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[1][3]_i_1_n_5 ), + .Q(out_s[2]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][3] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[1][3]_i_1_n_4 ), + .Q(out_s[3]), + .R(sclr)); + CARRY4 \needs_delay.shift_register_reg[1][3]_i_1 + (.CI(1'b0), + .CO({\needs_delay.shift_register_reg[1][3]_i_1_n_0 ,\needs_delay.shift_register_reg[1][3]_i_1_n_1 ,\needs_delay.shift_register_reg[1][3]_i_1_n_2 ,\needs_delay.shift_register_reg[1][3]_i_1_n_3 }), + .CYINIT(p_0_in), + .DI(Q[11:8]), + .O({\needs_delay.shift_register_reg[1][3]_i_1_n_4 ,\needs_delay.shift_register_reg[1][3]_i_1_n_5 ,\needs_delay.shift_register_reg[1][3]_i_1_n_6 ,\needs_delay.shift_register_reg[1][3]_i_1_n_7 }), + .S({\needs_delay.shift_register[1][3]_i_3__0_n_0 ,\needs_delay.shift_register[1][3]_i_4__0_n_0 ,\needs_delay.shift_register[1][3]_i_5__1_n_0 ,\needs_delay.shift_register[1][3]_i_6_n_0 })); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][4] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[1][7]_i_1_n_7 ), + .Q(out_s[4]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][5] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[1][7]_i_1_n_6 ), + .Q(out_s[5]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][6] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[1][7]_i_1_n_5 ), + .Q(out_s[6]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][7] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[1][7]_i_1_n_4 ), + .Q(out_s[7]), + .R(sclr)); + CARRY4 \needs_delay.shift_register_reg[1][7]_i_1 + (.CI(\needs_delay.shift_register_reg[1][3]_i_1_n_0 ), + .CO({\needs_delay.shift_register_reg[1][7]_i_1_n_0 ,\needs_delay.shift_register_reg[1][7]_i_1_n_1 ,\needs_delay.shift_register_reg[1][7]_i_1_n_2 ,\needs_delay.shift_register_reg[1][7]_i_1_n_3 }), + .CYINIT(1'b0), + .DI(Q[15:12]), + .O({\needs_delay.shift_register_reg[1][7]_i_1_n_4 ,\needs_delay.shift_register_reg[1][7]_i_1_n_5 ,\needs_delay.shift_register_reg[1][7]_i_1_n_6 ,\needs_delay.shift_register_reg[1][7]_i_1_n_7 }), + .S({\needs_delay.shift_register[1][7]_i_2_n_0 ,\needs_delay.shift_register[1][7]_i_3_n_0 ,\needs_delay.shift_register[1][7]_i_4_n_0 ,\needs_delay.shift_register[1][7]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][8] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[1][8]_i_1_n_7 ), + .Q(out_s[8]), + .R(sclr)); + CARRY4 \needs_delay.shift_register_reg[1][8]_i_1 + (.CI(\needs_delay.shift_register_reg[1][7]_i_1_n_0 ), + .CO(\NLW_needs_delay.shift_register_reg[1][8]_i_1_CO_UNCONNECTED [3:0]), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_needs_delay.shift_register_reg[1][8]_i_1_O_UNCONNECTED [3:1],\needs_delay.shift_register_reg[1][8]_i_1_n_7 }), + .S({1'b0,1'b0,1'b0,1'b1})); +endmodule + +(* ORIG_REF_NAME = "delay_sclr" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr_6 + (out_s, + Q, + sclr, + E, + aclk, + p_0_in); + output [8:0]out_s; + input [14:0]Q; + input sclr; + input [0:0]E; + input aclk; + input [0:0]p_0_in; + + wire [0:0]E; + wire [14:0]Q; + wire aclk; + wire \needs_delay.shift_register[1][3]_i_2__1_n_0 ; + wire \needs_delay.shift_register[1][3]_i_3_n_0 ; + wire \needs_delay.shift_register[1][3]_i_4_n_0 ; + wire \needs_delay.shift_register[1][3]_i_5_n_0 ; + wire \needs_delay.shift_register[1][7]_i_2__0_n_0 ; + wire \needs_delay.shift_register[1][7]_i_3__0_n_0 ; + wire \needs_delay.shift_register[1][7]_i_4__0_n_0 ; + wire \needs_delay.shift_register[1][7]_i_5__0_n_0 ; + wire \needs_delay.shift_register_reg[1][3]_i_1__0_n_0 ; + wire \needs_delay.shift_register_reg[1][3]_i_1__0_n_1 ; + wire \needs_delay.shift_register_reg[1][3]_i_1__0_n_2 ; + wire \needs_delay.shift_register_reg[1][3]_i_1__0_n_3 ; + wire \needs_delay.shift_register_reg[1][3]_i_1__0_n_4 ; + wire \needs_delay.shift_register_reg[1][3]_i_1__0_n_5 ; + wire \needs_delay.shift_register_reg[1][3]_i_1__0_n_6 ; + wire \needs_delay.shift_register_reg[1][3]_i_1__0_n_7 ; + wire \needs_delay.shift_register_reg[1][7]_i_1__0_n_0 ; + wire \needs_delay.shift_register_reg[1][7]_i_1__0_n_1 ; + wire \needs_delay.shift_register_reg[1][7]_i_1__0_n_2 ; + wire \needs_delay.shift_register_reg[1][7]_i_1__0_n_3 ; + wire \needs_delay.shift_register_reg[1][7]_i_1__0_n_4 ; + wire \needs_delay.shift_register_reg[1][7]_i_1__0_n_5 ; + wire \needs_delay.shift_register_reg[1][7]_i_1__0_n_6 ; + wire \needs_delay.shift_register_reg[1][7]_i_1__0_n_7 ; + wire \needs_delay.shift_register_reg[1][8]_i_1__0_n_7 ; + wire [8:0]out_s; + wire [0:0]p_0_in; + wire sclr; + wire [3:0]\NLW_needs_delay.shift_register_reg[1][8]_i_1__0_CO_UNCONNECTED ; + wire [3:1]\NLW_needs_delay.shift_register_reg[1][8]_i_1__0_O_UNCONNECTED ; + + LUT2 #( + .INIT(4'h9)) + \needs_delay.shift_register[1][3]_i_2__1 + (.I0(Q[10]), + .I1(Q[2]), + .O(\needs_delay.shift_register[1][3]_i_2__1_n_0 )); + LUT2 #( + .INIT(4'h9)) + \needs_delay.shift_register[1][3]_i_3 + (.I0(Q[9]), + .I1(Q[1]), + .O(\needs_delay.shift_register[1][3]_i_3_n_0 )); + LUT2 #( + .INIT(4'h9)) + \needs_delay.shift_register[1][3]_i_4 + (.I0(Q[8]), + .I1(Q[0]), + .O(\needs_delay.shift_register[1][3]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \needs_delay.shift_register[1][3]_i_5 + (.I0(Q[7]), + .O(\needs_delay.shift_register[1][3]_i_5_n_0 )); + LUT2 #( + .INIT(4'h9)) + \needs_delay.shift_register[1][7]_i_2__0 + (.I0(Q[14]), + .I1(Q[6]), + .O(\needs_delay.shift_register[1][7]_i_2__0_n_0 )); + LUT2 #( + .INIT(4'h9)) + \needs_delay.shift_register[1][7]_i_3__0 + (.I0(Q[13]), + .I1(Q[5]), + .O(\needs_delay.shift_register[1][7]_i_3__0_n_0 )); + LUT2 #( + .INIT(4'h9)) + \needs_delay.shift_register[1][7]_i_4__0 + (.I0(Q[12]), + .I1(Q[4]), + .O(\needs_delay.shift_register[1][7]_i_4__0_n_0 )); + LUT2 #( + .INIT(4'h9)) + \needs_delay.shift_register[1][7]_i_5__0 + (.I0(Q[11]), + .I1(Q[3]), + .O(\needs_delay.shift_register[1][7]_i_5__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][0] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[1][3]_i_1__0_n_7 ), + .Q(out_s[0]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][1] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[1][3]_i_1__0_n_6 ), + .Q(out_s[1]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][2] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[1][3]_i_1__0_n_5 ), + .Q(out_s[2]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][3] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[1][3]_i_1__0_n_4 ), + .Q(out_s[3]), + .R(sclr)); + CARRY4 \needs_delay.shift_register_reg[1][3]_i_1__0 + (.CI(1'b0), + .CO({\needs_delay.shift_register_reg[1][3]_i_1__0_n_0 ,\needs_delay.shift_register_reg[1][3]_i_1__0_n_1 ,\needs_delay.shift_register_reg[1][3]_i_1__0_n_2 ,\needs_delay.shift_register_reg[1][3]_i_1__0_n_3 }), + .CYINIT(p_0_in), + .DI(Q[10:7]), + .O({\needs_delay.shift_register_reg[1][3]_i_1__0_n_4 ,\needs_delay.shift_register_reg[1][3]_i_1__0_n_5 ,\needs_delay.shift_register_reg[1][3]_i_1__0_n_6 ,\needs_delay.shift_register_reg[1][3]_i_1__0_n_7 }), + .S({\needs_delay.shift_register[1][3]_i_2__1_n_0 ,\needs_delay.shift_register[1][3]_i_3_n_0 ,\needs_delay.shift_register[1][3]_i_4_n_0 ,\needs_delay.shift_register[1][3]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][4] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[1][7]_i_1__0_n_7 ), + .Q(out_s[4]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][5] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[1][7]_i_1__0_n_6 ), + .Q(out_s[5]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][6] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[1][7]_i_1__0_n_5 ), + .Q(out_s[6]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][7] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[1][7]_i_1__0_n_4 ), + .Q(out_s[7]), + .R(sclr)); + CARRY4 \needs_delay.shift_register_reg[1][7]_i_1__0 + (.CI(\needs_delay.shift_register_reg[1][3]_i_1__0_n_0 ), + .CO({\needs_delay.shift_register_reg[1][7]_i_1__0_n_0 ,\needs_delay.shift_register_reg[1][7]_i_1__0_n_1 ,\needs_delay.shift_register_reg[1][7]_i_1__0_n_2 ,\needs_delay.shift_register_reg[1][7]_i_1__0_n_3 }), + .CYINIT(1'b0), + .DI(Q[14:11]), + .O({\needs_delay.shift_register_reg[1][7]_i_1__0_n_4 ,\needs_delay.shift_register_reg[1][7]_i_1__0_n_5 ,\needs_delay.shift_register_reg[1][7]_i_1__0_n_6 ,\needs_delay.shift_register_reg[1][7]_i_1__0_n_7 }), + .S({\needs_delay.shift_register[1][7]_i_2__0_n_0 ,\needs_delay.shift_register[1][7]_i_3__0_n_0 ,\needs_delay.shift_register[1][7]_i_4__0_n_0 ,\needs_delay.shift_register[1][7]_i_5__0_n_0 })); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][8] + (.C(aclk), + .CE(E), + .D(\needs_delay.shift_register_reg[1][8]_i_1__0_n_7 ), + .Q(out_s[8]), + .R(sclr)); + CARRY4 \needs_delay.shift_register_reg[1][8]_i_1__0 + (.CI(\needs_delay.shift_register_reg[1][7]_i_1__0_n_0 ), + .CO(\NLW_needs_delay.shift_register_reg[1][8]_i_1__0_CO_UNCONNECTED [3:0]), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_needs_delay.shift_register_reg[1][8]_i_1__0_O_UNCONNECTED [3:1],\needs_delay.shift_register_reg[1][8]_i_1__0_n_7 }), + .S({1'b0,1'b0,1'b0,1'b1})); +endmodule + +(* ORIG_REF_NAME = "delay_sclr" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized0 + (c, + E, + aclk, + sclr, + s, + \core_control_regs[9] ); + output [25:0]c; + input [0:0]E; + input aclk; + input sclr; + input [8:0]s; + input [16:0]\core_control_regs[9] ; + + wire [0:0]E; + wire aclk; + wire [25:0]c; + wire [16:0]\core_control_regs[9] ; + wire [8:0]s; + wire sclr; + wire \NLW_needs_delay.shift_register_reg[2]_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_needs_delay.shift_register_reg[2]_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_needs_delay.shift_register_reg[2]_OVERFLOW_UNCONNECTED ; + wire \NLW_needs_delay.shift_register_reg[2]_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_needs_delay.shift_register_reg[2]_PATTERNDETECT_UNCONNECTED ; + wire \NLW_needs_delay.shift_register_reg[2]_UNDERFLOW_UNCONNECTED ; + wire [29:0]\NLW_needs_delay.shift_register_reg[2]_ACOUT_UNCONNECTED ; + wire [17:0]\NLW_needs_delay.shift_register_reg[2]_BCOUT_UNCONNECTED ; + wire [3:0]\NLW_needs_delay.shift_register_reg[2]_CARRYOUT_UNCONNECTED ; + wire [47:26]\NLW_needs_delay.shift_register_reg[2]_P_UNCONNECTED ; + wire [47:0]\NLW_needs_delay.shift_register_reg[2]_PCOUT_UNCONNECTED ; + + (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *) + DSP48E1 #( + .ACASCREG(0), + .ADREG(1), + .ALUMODEREG(0), + .AREG(0), + .AUTORESET_PATDET("NO_RESET"), + .A_INPUT("DIRECT"), + .BCASCREG(0), + .BREG(0), + .B_INPUT("DIRECT"), + .CARRYINREG(0), + .CARRYINSELREG(0), + .CREG(1), + .DREG(1), + .INMODEREG(0), + .MASK(48'h3FFFFFFFFFFF), + .MREG(1), + .OPMODEREG(0), + .PATTERN(48'h000000000000), + .PREG(1), + .SEL_MASK("MASK"), + .SEL_PATTERN("PATTERN"), + .USE_DPORT("FALSE"), + .USE_MULT("MULTIPLY"), + .USE_PATTERN_DETECT("NO_PATDET"), + .USE_SIMD("ONE48")) + \needs_delay.shift_register_reg[2] + (.A({\core_control_regs[9] [16],\core_control_regs[9] [16],\core_control_regs[9] [16],\core_control_regs[9] [16],\core_control_regs[9] [16],\core_control_regs[9] [16],\core_control_regs[9] [16],\core_control_regs[9] [16],\core_control_regs[9] [16],\core_control_regs[9] [16],\core_control_regs[9] [16],\core_control_regs[9] [16],\core_control_regs[9] [16],\core_control_regs[9] }), + .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .ACOUT(\NLW_needs_delay.shift_register_reg[2]_ACOUT_UNCONNECTED [29:0]), + .ALUMODE({1'b0,1'b0,1'b0,1'b0}), + .B({s[8],s[8],s[8],s[8],s[8],s[8],s[8],s[8],s[8],s}), + .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .BCOUT(\NLW_needs_delay.shift_register_reg[2]_BCOUT_UNCONNECTED [17:0]), + .C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), + .CARRYCASCIN(1'b0), + .CARRYCASCOUT(\NLW_needs_delay.shift_register_reg[2]_CARRYCASCOUT_UNCONNECTED ), + .CARRYIN(1'b0), + .CARRYINSEL({1'b0,1'b0,1'b0}), + .CARRYOUT(\NLW_needs_delay.shift_register_reg[2]_CARRYOUT_UNCONNECTED [3:0]), + .CEA1(1'b0), + .CEA2(1'b0), + .CEAD(1'b0), + .CEALUMODE(1'b0), + .CEB1(1'b0), + .CEB2(1'b0), + .CEC(1'b0), + .CECARRYIN(1'b0), + .CECTRL(1'b0), + .CED(1'b0), + .CEINMODE(1'b0), + .CEM(E), + .CEP(E), + .CLK(aclk), + .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}), + .MULTSIGNIN(1'b0), + .MULTSIGNOUT(\NLW_needs_delay.shift_register_reg[2]_MULTSIGNOUT_UNCONNECTED ), + .OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}), + .OVERFLOW(\NLW_needs_delay.shift_register_reg[2]_OVERFLOW_UNCONNECTED ), + .P({\NLW_needs_delay.shift_register_reg[2]_P_UNCONNECTED [47:26],c}), + .PATTERNBDETECT(\NLW_needs_delay.shift_register_reg[2]_PATTERNBDETECT_UNCONNECTED ), + .PATTERNDETECT(\NLW_needs_delay.shift_register_reg[2]_PATTERNDETECT_UNCONNECTED ), + .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .PCOUT(\NLW_needs_delay.shift_register_reg[2]_PCOUT_UNCONNECTED [47:0]), + .RSTA(1'b0), + .RSTALLCARRYIN(1'b0), + .RSTALUMODE(1'b0), + .RSTB(1'b0), + .RSTC(1'b0), + .RSTCTRL(1'b0), + .RSTD(1'b0), + .RSTINMODE(1'b0), + .RSTM(sclr), + .RSTP(sclr), + .UNDERFLOW(\NLW_needs_delay.shift_register_reg[2]_UNDERFLOW_UNCONNECTED )); +endmodule + +(* ORIG_REF_NAME = "delay_sclr" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized1 + (a, + D, + \needs_delay.shift_register_reg[1][10] , + \needs_delay.shift_register_reg[1][3]_0 , + Q, + p, + CO, + \needs_delay.shift_register_reg[5][7] , + out, + sclr, + E, + plusOp, + aclk); + output [1:0]a; + output [2:0]D; + output [2:0]\needs_delay.shift_register_reg[1][10] ; + output \needs_delay.shift_register_reg[1][3]_0 ; + output [9:0]Q; + input [1:0]p; + input [0:0]CO; + input [0:0]\needs_delay.shift_register_reg[5][7] ; + input [2:0]out; + input sclr; + input [0:0]E; + input [9:0]plusOp; + input aclk; + + wire [0:0]CO; + wire [2:0]D; + wire [0:0]E; + wire [9:0]Q; + wire [1:0]a; + wire aclk; + wire \needs_delay.shift_register[1][10]_i_2__0_n_0 ; + wire \needs_delay.shift_register[1][10]_i_2__1_n_0 ; + wire \needs_delay.shift_register[1][10]_i_3__0_n_0 ; + wire \needs_delay.shift_register[1][10]_i_3_n_0 ; + wire [2:0]\needs_delay.shift_register_reg[1][10] ; + wire \needs_delay.shift_register_reg[1][10]_i_1__0_n_2 ; + wire \needs_delay.shift_register_reg[1][10]_i_1__0_n_3 ; + wire \needs_delay.shift_register_reg[1][10]_i_1_n_2 ; + wire \needs_delay.shift_register_reg[1][10]_i_1_n_3 ; + wire \needs_delay.shift_register_reg[1][3]_0 ; + wire [0:0]\needs_delay.shift_register_reg[5][7] ; + wire [2:0]out; + wire [1:0]p; + wire [9:0]plusOp; + wire sclr; + wire [3:2]\NLW_needs_delay.shift_register_reg[1][10]_i_1_CO_UNCONNECTED ; + wire [3:3]\NLW_needs_delay.shift_register_reg[1][10]_i_1_O_UNCONNECTED ; + wire [3:2]\NLW_needs_delay.shift_register_reg[1][10]_i_1__0_CO_UNCONNECTED ; + wire [3:3]\NLW_needs_delay.shift_register_reg[1][10]_i_1__0_O_UNCONNECTED ; + + LUT1 #( + .INIT(2'h1)) + \needs_delay.shift_register[1][10]_i_2__0 + (.I0(out[2]), + .O(\needs_delay.shift_register[1][10]_i_2__0_n_0 )); + LUT1 #( + .INIT(2'h1)) + \needs_delay.shift_register[1][10]_i_2__1 + (.I0(out[2]), + .O(\needs_delay.shift_register[1][10]_i_2__1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \needs_delay.shift_register[1][10]_i_3 + (.I0(out[1]), + .O(\needs_delay.shift_register[1][10]_i_3_n_0 )); + LUT1 #( + .INIT(2'h1)) + \needs_delay.shift_register[1][10]_i_3__0 + (.I0(out[1]), + .O(\needs_delay.shift_register[1][10]_i_3__0_n_0 )); + LUT1 #( + .INIT(2'h1)) + \needs_delay.shift_register[1][3]_i_2__0 + (.I0(out[0]), + .O(\needs_delay.shift_register_reg[1][3]_0 )); + LUT1 #( + .INIT(2'h2)) + \needs_delay.shift_register[1][3]_i_5__3 + (.I0(p[0]), + .O(a[0])); + LUT1 #( + .INIT(2'h2)) + \needs_delay.shift_register[1][9]_i_3 + (.I0(p[1]), + .O(a[1])); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][0] + (.C(aclk), + .CE(E), + .D(plusOp[0]), + .Q(Q[0]), + .R(sclr)); + CARRY4 \needs_delay.shift_register_reg[1][10]_i_1 + (.CI(CO), + .CO({\NLW_needs_delay.shift_register_reg[1][10]_i_1_CO_UNCONNECTED [3:2],\needs_delay.shift_register_reg[1][10]_i_1_n_2 ,\needs_delay.shift_register_reg[1][10]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b1,1'b0}), + .O({\NLW_needs_delay.shift_register_reg[1][10]_i_1_O_UNCONNECTED [3],D}), + .S({1'b0,1'b1,\needs_delay.shift_register[1][10]_i_2__0_n_0 ,\needs_delay.shift_register[1][10]_i_3__0_n_0 })); + CARRY4 \needs_delay.shift_register_reg[1][10]_i_1__0 + (.CI(\needs_delay.shift_register_reg[5][7] ), + .CO({\NLW_needs_delay.shift_register_reg[1][10]_i_1__0_CO_UNCONNECTED [3:2],\needs_delay.shift_register_reg[1][10]_i_1__0_n_2 ,\needs_delay.shift_register_reg[1][10]_i_1__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b1,1'b0}), + .O({\NLW_needs_delay.shift_register_reg[1][10]_i_1__0_O_UNCONNECTED [3],\needs_delay.shift_register_reg[1][10] }), + .S({1'b0,1'b1,\needs_delay.shift_register[1][10]_i_2__1_n_0 ,\needs_delay.shift_register[1][10]_i_3_n_0 })); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][1] + (.C(aclk), + .CE(E), + .D(plusOp[1]), + .Q(Q[1]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][2] + (.C(aclk), + .CE(E), + .D(plusOp[2]), + .Q(Q[2]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][3] + (.C(aclk), + .CE(E), + .D(plusOp[3]), + .Q(Q[3]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][4] + (.C(aclk), + .CE(E), + .D(plusOp[4]), + .Q(Q[4]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][5] + (.C(aclk), + .CE(E), + .D(plusOp[5]), + .Q(Q[5]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][6] + (.C(aclk), + .CE(E), + .D(plusOp[6]), + .Q(Q[6]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][7] + (.C(aclk), + .CE(E), + .D(plusOp[7]), + .Q(Q[7]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][8] + (.C(aclk), + .CE(E), + .D(plusOp[8]), + .Q(Q[8]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][9] + (.C(aclk), + .CE(E), + .D(plusOp[9]), + .Q(Q[9]), + .R(sclr)); +endmodule + +(* ORIG_REF_NAME = "delay_sclr" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized2 + (Q, + sclr, + E, + D, + aclk); + output [10:0]Q; + input sclr; + input [0:0]E; + input [10:0]D; + input aclk; + + wire [10:0]D; + wire [0:0]E; + wire [10:0]Q; + wire aclk; + wire sclr; + + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][0] + (.C(aclk), + .CE(E), + .D(D[0]), + .Q(Q[0]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][10] + (.C(aclk), + .CE(E), + .D(D[10]), + .Q(Q[10]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][1] + (.C(aclk), + .CE(E), + .D(D[1]), + .Q(Q[1]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][2] + (.C(aclk), + .CE(E), + .D(D[2]), + .Q(Q[2]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][3] + (.C(aclk), + .CE(E), + .D(D[3]), + .Q(Q[3]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][4] + (.C(aclk), + .CE(E), + .D(D[4]), + .Q(Q[4]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][5] + (.C(aclk), + .CE(E), + .D(D[5]), + .Q(Q[5]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][6] + (.C(aclk), + .CE(E), + .D(D[6]), + .Q(Q[6]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][7] + (.C(aclk), + .CE(E), + .D(D[7]), + .Q(Q[7]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][8] + (.C(aclk), + .CE(E), + .D(D[8]), + .Q(Q[8]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][9] + (.C(aclk), + .CE(E), + .D(D[9]), + .Q(Q[9]), + .R(sclr)); +endmodule + +(* ORIG_REF_NAME = "delay_sclr" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized3 + (Q, + sclr, + E, + D, + aclk); + output [10:0]Q; + input sclr; + input [0:0]E; + input [10:0]D; + input aclk; + + wire [10:0]D; + wire [0:0]E; + wire [10:0]Q; + wire aclk; + wire sclr; + + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][0] + (.C(aclk), + .CE(E), + .D(D[0]), + .Q(Q[0]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][10] + (.C(aclk), + .CE(E), + .D(D[10]), + .Q(Q[10]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][1] + (.C(aclk), + .CE(E), + .D(D[1]), + .Q(Q[1]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][2] + (.C(aclk), + .CE(E), + .D(D[2]), + .Q(Q[2]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][3] + (.C(aclk), + .CE(E), + .D(D[3]), + .Q(Q[3]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][4] + (.C(aclk), + .CE(E), + .D(D[4]), + .Q(Q[4]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][5] + (.C(aclk), + .CE(E), + .D(D[5]), + .Q(Q[5]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][6] + (.C(aclk), + .CE(E), + .D(D[6]), + .Q(Q[6]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][7] + (.C(aclk), + .CE(E), + .D(D[7]), + .Q(Q[7]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][8] + (.C(aclk), + .CE(E), + .D(D[8]), + .Q(Q[8]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][9] + (.C(aclk), + .CE(E), + .D(D[9]), + .Q(Q[9]), + .R(sclr)); +endmodule + +(* ORIG_REF_NAME = "delay_sclr" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized4 + (SR, + Q, + resetn_out, + E, + plusOp, + aclk); + output [0:0]SR; + output [10:0]Q; + input resetn_out; + input [0:0]E; + input [10:0]plusOp; + input aclk; + + wire [0:0]E; + wire [10:0]Q; + wire [0:0]SR; + wire aclk; + wire [10:0]plusOp; + wire resetn_out; + + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][0] + (.C(aclk), + .CE(E), + .D(plusOp[0]), + .Q(Q[0]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][10] + (.C(aclk), + .CE(E), + .D(plusOp[10]), + .Q(Q[10]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][1] + (.C(aclk), + .CE(E), + .D(plusOp[1]), + .Q(Q[1]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][2] + (.C(aclk), + .CE(E), + .D(plusOp[2]), + .Q(Q[2]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][3] + (.C(aclk), + .CE(E), + .D(plusOp[3]), + .Q(Q[3]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][4] + (.C(aclk), + .CE(E), + .D(plusOp[4]), + .Q(Q[4]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][5] + (.C(aclk), + .CE(E), + .D(plusOp[5]), + .Q(Q[5]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][6] + (.C(aclk), + .CE(E), + .D(plusOp[6]), + .Q(Q[6]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][7] + (.C(aclk), + .CE(E), + .D(plusOp[7]), + .Q(Q[7]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][8] + (.C(aclk), + .CE(E), + .D(plusOp[8]), + .Q(Q[8]), + .R(SR)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][9] + (.C(aclk), + .CE(E), + .D(plusOp[9]), + .Q(Q[9]), + .R(SR)); + LUT1 #( + .INIT(2'h1)) + sof_late_i_i_1 + (.I0(resetn_out), + .O(SR)); +endmodule + +(* ORIG_REF_NAME = "delay_sclr" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized5 + (\needs_delay.shift_register_reg[1][7]_0 , + Q, + \needs_delay.shift_register_reg[1][7]_1 , + \needs_delay.shift_register_reg[1][7]_2 , + \core_control_regs[1] , + sclr, + E, + D, + aclk); + output [0:0]\needs_delay.shift_register_reg[1][7]_0 ; + output [8:0]Q; + output [3:0]\needs_delay.shift_register_reg[1][7]_1 ; + output [3:0]\needs_delay.shift_register_reg[1][7]_2 ; + input [7:0]\core_control_regs[1] ; + input sclr; + input [0:0]E; + input [9:0]D; + input aclk; + + wire [9:0]D; + wire [0:0]E; + wire [8:0]Q; + wire aclk; + wire [7:0]\core_control_regs[1] ; + wire [0:0]\needs_delay.shift_register_reg[1][7]_0 ; + wire [3:0]\needs_delay.shift_register_reg[1][7]_1 ; + wire [3:0]\needs_delay.shift_register_reg[1][7]_2 ; + wire \needs_delay.shift_register_reg_n_0_[1][8] ; + wire sclr; + + LUT2 #( + .INIT(4'h1)) + ltOp_carry__0_i_1__0 + (.I0(\needs_delay.shift_register_reg_n_0_[1][8] ), + .I1(Q[8]), + .O(\needs_delay.shift_register_reg[1][7]_0 )); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1__0 + (.I0(\core_control_regs[1] [6]), + .I1(Q[6]), + .I2(Q[7]), + .I3(\core_control_regs[1] [7]), + .O(\needs_delay.shift_register_reg[1][7]_2 [3])); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2__0 + (.I0(\core_control_regs[1] [4]), + .I1(Q[4]), + .I2(Q[5]), + .I3(\core_control_regs[1] [5]), + .O(\needs_delay.shift_register_reg[1][7]_2 [2])); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3__0 + (.I0(\core_control_regs[1] [2]), + .I1(Q[2]), + .I2(Q[3]), + .I3(\core_control_regs[1] [3]), + .O(\needs_delay.shift_register_reg[1][7]_2 [1])); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4__0 + (.I0(\core_control_regs[1] [0]), + .I1(Q[0]), + .I2(Q[1]), + .I3(\core_control_regs[1] [1]), + .O(\needs_delay.shift_register_reg[1][7]_2 [0])); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5__0 + (.I0(\core_control_regs[1] [6]), + .I1(Q[6]), + .I2(\core_control_regs[1] [7]), + .I3(Q[7]), + .O(\needs_delay.shift_register_reg[1][7]_1 [3])); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6__0 + (.I0(\core_control_regs[1] [4]), + .I1(Q[4]), + .I2(\core_control_regs[1] [5]), + .I3(Q[5]), + .O(\needs_delay.shift_register_reg[1][7]_1 [2])); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7__0 + (.I0(\core_control_regs[1] [2]), + .I1(Q[2]), + .I2(\core_control_regs[1] [3]), + .I3(Q[3]), + .O(\needs_delay.shift_register_reg[1][7]_1 [1])); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8__0 + (.I0(\core_control_regs[1] [0]), + .I1(Q[0]), + .I2(\core_control_regs[1] [1]), + .I3(Q[1]), + .O(\needs_delay.shift_register_reg[1][7]_1 [0])); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][0] + (.C(aclk), + .CE(E), + .D(D[0]), + .Q(Q[0]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][1] + (.C(aclk), + .CE(E), + .D(D[1]), + .Q(Q[1]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][2] + (.C(aclk), + .CE(E), + .D(D[2]), + .Q(Q[2]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][3] + (.C(aclk), + .CE(E), + .D(D[3]), + .Q(Q[3]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][4] + (.C(aclk), + .CE(E), + .D(D[4]), + .Q(Q[4]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][5] + (.C(aclk), + .CE(E), + .D(D[5]), + .Q(Q[5]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][6] + (.C(aclk), + .CE(E), + .D(D[6]), + .Q(Q[6]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][7] + (.C(aclk), + .CE(E), + .D(D[7]), + .Q(Q[7]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][8] + (.C(aclk), + .CE(E), + .D(D[8]), + .Q(\needs_delay.shift_register_reg_n_0_[1][8] ), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][9] + (.C(aclk), + .CE(E), + .D(D[9]), + .Q(Q[8]), + .R(sclr)); +endmodule + +(* ORIG_REF_NAME = "delay_sclr" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized5_7 + (DI, + S, + \needs_delay.shift_register_reg[1][7]_0 , + Q, + \needs_delay.shift_register_reg[1][7]_1 , + \needs_delay.shift_register_reg[1][7]_2 , + \needs_delay.shift_register_reg[1][9]_0 , + \needs_delay.shift_register_reg[1][9]_1 , + p, + \core_control_regs[5] , + \core_control_regs[4] , + sclr, + E, + D, + aclk); + output [0:0]DI; + output [0:0]S; + output [0:0]\needs_delay.shift_register_reg[1][7]_0 ; + output [8:0]Q; + output [3:0]\needs_delay.shift_register_reg[1][7]_1 ; + output [3:0]\needs_delay.shift_register_reg[1][7]_2 ; + output [3:0]\needs_delay.shift_register_reg[1][9]_0 ; + output [3:0]\needs_delay.shift_register_reg[1][9]_1 ; + input [9:0]p; + input [7:0]\core_control_regs[5] ; + input [7:0]\core_control_regs[4] ; + input sclr; + input [0:0]E; + input [9:0]D; + input aclk; + + wire [9:0]D; + wire [0:0]DI; + wire [0:0]E; + wire [8:0]Q; + wire [0:0]S; + wire aclk; + wire [7:0]\core_control_regs[4] ; + wire [7:0]\core_control_regs[5] ; + wire [0:0]\needs_delay.shift_register_reg[1][7]_0 ; + wire [3:0]\needs_delay.shift_register_reg[1][7]_1 ; + wire [3:0]\needs_delay.shift_register_reg[1][7]_2 ; + wire [3:0]\needs_delay.shift_register_reg[1][9]_0 ; + wire [3:0]\needs_delay.shift_register_reg[1][9]_1 ; + wire \needs_delay.shift_register_reg_n_0_[1][8] ; + wire [9:0]p; + wire sclr; + + LUT2 #( + .INIT(4'h2)) + gtOp_carry__0_i_1__2 + (.I0(p[8]), + .I1(p[9]), + .O(DI)); + LUT2 #( + .INIT(4'h1)) + gtOp_carry__0_i_2__2 + (.I0(p[8]), + .I1(p[9]), + .O(S)); + LUT4 #( + .INIT(16'h2F02)) + gtOp_carry_i_1__2 + (.I0(p[6]), + .I1(\core_control_regs[4] [6]), + .I2(\core_control_regs[4] [7]), + .I3(p[7]), + .O(\needs_delay.shift_register_reg[1][9]_1 [3])); + LUT4 #( + .INIT(16'h2F02)) + gtOp_carry_i_2__2 + (.I0(p[4]), + .I1(\core_control_regs[4] [4]), + .I2(\core_control_regs[4] [5]), + .I3(p[5]), + .O(\needs_delay.shift_register_reg[1][9]_1 [2])); + LUT4 #( + .INIT(16'h2F02)) + gtOp_carry_i_3__2 + (.I0(p[2]), + .I1(\core_control_regs[4] [2]), + .I2(\core_control_regs[4] [3]), + .I3(p[3]), + .O(\needs_delay.shift_register_reg[1][9]_1 [1])); + LUT4 #( + .INIT(16'h2F02)) + gtOp_carry_i_4__2 + (.I0(p[0]), + .I1(\core_control_regs[4] [0]), + .I2(\core_control_regs[4] [1]), + .I3(p[1]), + .O(\needs_delay.shift_register_reg[1][9]_1 [0])); + LUT4 #( + .INIT(16'h9009)) + gtOp_carry_i_5__2 + (.I0(p[6]), + .I1(\core_control_regs[4] [6]), + .I2(p[7]), + .I3(\core_control_regs[4] [7]), + .O(\needs_delay.shift_register_reg[1][9]_0 [3])); + LUT4 #( + .INIT(16'h9009)) + gtOp_carry_i_6__2 + (.I0(p[4]), + .I1(\core_control_regs[4] [4]), + .I2(p[5]), + .I3(\core_control_regs[4] [5]), + .O(\needs_delay.shift_register_reg[1][9]_0 [2])); + LUT4 #( + .INIT(16'h9009)) + gtOp_carry_i_7__2 + (.I0(p[2]), + .I1(\core_control_regs[4] [2]), + .I2(p[3]), + .I3(\core_control_regs[4] [3]), + .O(\needs_delay.shift_register_reg[1][9]_0 [1])); + LUT4 #( + .INIT(16'h9009)) + gtOp_carry_i_8__2 + (.I0(p[0]), + .I1(\core_control_regs[4] [0]), + .I2(p[1]), + .I3(\core_control_regs[4] [1]), + .O(\needs_delay.shift_register_reg[1][9]_0 [0])); + LUT2 #( + .INIT(4'h1)) + ltOp_carry__0_i_1__2 + (.I0(\needs_delay.shift_register_reg_n_0_[1][8] ), + .I1(Q[8]), + .O(\needs_delay.shift_register_reg[1][7]_0 )); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1__2 + (.I0(\core_control_regs[5] [6]), + .I1(Q[6]), + .I2(Q[7]), + .I3(\core_control_regs[5] [7]), + .O(\needs_delay.shift_register_reg[1][7]_2 [3])); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2__2 + (.I0(\core_control_regs[5] [4]), + .I1(Q[4]), + .I2(Q[5]), + .I3(\core_control_regs[5] [5]), + .O(\needs_delay.shift_register_reg[1][7]_2 [2])); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3__2 + (.I0(\core_control_regs[5] [2]), + .I1(Q[2]), + .I2(Q[3]), + .I3(\core_control_regs[5] [3]), + .O(\needs_delay.shift_register_reg[1][7]_2 [1])); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4__2 + (.I0(\core_control_regs[5] [0]), + .I1(Q[0]), + .I2(Q[1]), + .I3(\core_control_regs[5] [1]), + .O(\needs_delay.shift_register_reg[1][7]_2 [0])); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5__2 + (.I0(\core_control_regs[5] [6]), + .I1(Q[6]), + .I2(\core_control_regs[5] [7]), + .I3(Q[7]), + .O(\needs_delay.shift_register_reg[1][7]_1 [3])); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6__2 + (.I0(\core_control_regs[5] [4]), + .I1(Q[4]), + .I2(\core_control_regs[5] [5]), + .I3(Q[5]), + .O(\needs_delay.shift_register_reg[1][7]_1 [2])); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7__2 + (.I0(\core_control_regs[5] [2]), + .I1(Q[2]), + .I2(\core_control_regs[5] [3]), + .I3(Q[3]), + .O(\needs_delay.shift_register_reg[1][7]_1 [1])); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8__2 + (.I0(\core_control_regs[5] [0]), + .I1(Q[0]), + .I2(\core_control_regs[5] [1]), + .I3(Q[1]), + .O(\needs_delay.shift_register_reg[1][7]_1 [0])); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][0] + (.C(aclk), + .CE(E), + .D(D[0]), + .Q(Q[0]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][1] + (.C(aclk), + .CE(E), + .D(D[1]), + .Q(Q[1]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][2] + (.C(aclk), + .CE(E), + .D(D[2]), + .Q(Q[2]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][3] + (.C(aclk), + .CE(E), + .D(D[3]), + .Q(Q[3]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][4] + (.C(aclk), + .CE(E), + .D(D[4]), + .Q(Q[4]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][5] + (.C(aclk), + .CE(E), + .D(D[5]), + .Q(Q[5]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][6] + (.C(aclk), + .CE(E), + .D(D[6]), + .Q(Q[6]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][7] + (.C(aclk), + .CE(E), + .D(D[7]), + .Q(Q[7]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][8] + (.C(aclk), + .CE(E), + .D(D[8]), + .Q(\needs_delay.shift_register_reg_n_0_[1][8] ), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][9] + (.C(aclk), + .CE(E), + .D(D[9]), + .Q(Q[8]), + .R(sclr)); +endmodule + +(* ORIG_REF_NAME = "delay_sclr" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized5_8 + (DI, + S, + \needs_delay.shift_register_reg[1][7]_0 , + Q, + \needs_delay.shift_register_reg[1][7]_1 , + \needs_delay.shift_register_reg[1][7]_2 , + \needs_delay.shift_register_reg[1][9]_0 , + \needs_delay.shift_register_reg[1][9]_1 , + p, + \core_control_regs[3] , + \core_control_regs[2] , + sclr, + E, + D, + aclk); + output [0:0]DI; + output [0:0]S; + output [0:0]\needs_delay.shift_register_reg[1][7]_0 ; + output [8:0]Q; + output [3:0]\needs_delay.shift_register_reg[1][7]_1 ; + output [3:0]\needs_delay.shift_register_reg[1][7]_2 ; + output [3:0]\needs_delay.shift_register_reg[1][9]_0 ; + output [3:0]\needs_delay.shift_register_reg[1][9]_1 ; + input [9:0]p; + input [7:0]\core_control_regs[3] ; + input [7:0]\core_control_regs[2] ; + input sclr; + input [0:0]E; + input [9:0]D; + input aclk; + + wire [9:0]D; + wire [0:0]DI; + wire [0:0]E; + wire [8:0]Q; + wire [0:0]S; + wire aclk; + wire [7:0]\core_control_regs[2] ; + wire [7:0]\core_control_regs[3] ; + wire [0:0]\needs_delay.shift_register_reg[1][7]_0 ; + wire [3:0]\needs_delay.shift_register_reg[1][7]_1 ; + wire [3:0]\needs_delay.shift_register_reg[1][7]_2 ; + wire [3:0]\needs_delay.shift_register_reg[1][9]_0 ; + wire [3:0]\needs_delay.shift_register_reg[1][9]_1 ; + wire \needs_delay.shift_register_reg_n_0_[1][8] ; + wire [9:0]p; + wire sclr; + + LUT2 #( + .INIT(4'h2)) + gtOp_carry__0_i_1__1 + (.I0(p[8]), + .I1(p[9]), + .O(DI)); + LUT2 #( + .INIT(4'h1)) + gtOp_carry__0_i_2__1 + (.I0(p[8]), + .I1(p[9]), + .O(S)); + LUT4 #( + .INIT(16'h2F02)) + gtOp_carry_i_1__1 + (.I0(p[6]), + .I1(\core_control_regs[2] [6]), + .I2(\core_control_regs[2] [7]), + .I3(p[7]), + .O(\needs_delay.shift_register_reg[1][9]_1 [3])); + LUT4 #( + .INIT(16'h2F02)) + gtOp_carry_i_2__1 + (.I0(p[4]), + .I1(\core_control_regs[2] [4]), + .I2(\core_control_regs[2] [5]), + .I3(p[5]), + .O(\needs_delay.shift_register_reg[1][9]_1 [2])); + LUT4 #( + .INIT(16'h2F02)) + gtOp_carry_i_3__1 + (.I0(p[2]), + .I1(\core_control_regs[2] [2]), + .I2(\core_control_regs[2] [3]), + .I3(p[3]), + .O(\needs_delay.shift_register_reg[1][9]_1 [1])); + LUT4 #( + .INIT(16'h2F02)) + gtOp_carry_i_4__1 + (.I0(p[0]), + .I1(\core_control_regs[2] [0]), + .I2(\core_control_regs[2] [1]), + .I3(p[1]), + .O(\needs_delay.shift_register_reg[1][9]_1 [0])); + LUT4 #( + .INIT(16'h9009)) + gtOp_carry_i_5__1 + (.I0(p[6]), + .I1(\core_control_regs[2] [6]), + .I2(p[7]), + .I3(\core_control_regs[2] [7]), + .O(\needs_delay.shift_register_reg[1][9]_0 [3])); + LUT4 #( + .INIT(16'h9009)) + gtOp_carry_i_6__1 + (.I0(p[4]), + .I1(\core_control_regs[2] [4]), + .I2(p[5]), + .I3(\core_control_regs[2] [5]), + .O(\needs_delay.shift_register_reg[1][9]_0 [2])); + LUT4 #( + .INIT(16'h9009)) + gtOp_carry_i_7__1 + (.I0(p[2]), + .I1(\core_control_regs[2] [2]), + .I2(p[3]), + .I3(\core_control_regs[2] [3]), + .O(\needs_delay.shift_register_reg[1][9]_0 [1])); + LUT4 #( + .INIT(16'h9009)) + gtOp_carry_i_8__1 + (.I0(p[0]), + .I1(\core_control_regs[2] [0]), + .I2(p[1]), + .I3(\core_control_regs[2] [1]), + .O(\needs_delay.shift_register_reg[1][9]_0 [0])); + LUT2 #( + .INIT(4'h1)) + ltOp_carry__0_i_1__1 + (.I0(\needs_delay.shift_register_reg_n_0_[1][8] ), + .I1(Q[8]), + .O(\needs_delay.shift_register_reg[1][7]_0 )); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1__1 + (.I0(\core_control_regs[3] [6]), + .I1(Q[6]), + .I2(Q[7]), + .I3(\core_control_regs[3] [7]), + .O(\needs_delay.shift_register_reg[1][7]_2 [3])); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2__1 + (.I0(\core_control_regs[3] [4]), + .I1(Q[4]), + .I2(Q[5]), + .I3(\core_control_regs[3] [5]), + .O(\needs_delay.shift_register_reg[1][7]_2 [2])); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3__1 + (.I0(\core_control_regs[3] [2]), + .I1(Q[2]), + .I2(Q[3]), + .I3(\core_control_regs[3] [3]), + .O(\needs_delay.shift_register_reg[1][7]_2 [1])); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4__1 + (.I0(\core_control_regs[3] [0]), + .I1(Q[0]), + .I2(Q[1]), + .I3(\core_control_regs[3] [1]), + .O(\needs_delay.shift_register_reg[1][7]_2 [0])); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5__1 + (.I0(\core_control_regs[3] [6]), + .I1(Q[6]), + .I2(\core_control_regs[3] [7]), + .I3(Q[7]), + .O(\needs_delay.shift_register_reg[1][7]_1 [3])); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6__1 + (.I0(\core_control_regs[3] [4]), + .I1(Q[4]), + .I2(\core_control_regs[3] [5]), + .I3(Q[5]), + .O(\needs_delay.shift_register_reg[1][7]_1 [2])); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7__1 + (.I0(\core_control_regs[3] [2]), + .I1(Q[2]), + .I2(\core_control_regs[3] [3]), + .I3(Q[3]), + .O(\needs_delay.shift_register_reg[1][7]_1 [1])); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8__1 + (.I0(\core_control_regs[3] [0]), + .I1(Q[0]), + .I2(\core_control_regs[3] [1]), + .I3(Q[1]), + .O(\needs_delay.shift_register_reg[1][7]_1 [0])); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][0] + (.C(aclk), + .CE(E), + .D(D[0]), + .Q(Q[0]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][1] + (.C(aclk), + .CE(E), + .D(D[1]), + .Q(Q[1]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][2] + (.C(aclk), + .CE(E), + .D(D[2]), + .Q(Q[2]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][3] + (.C(aclk), + .CE(E), + .D(D[3]), + .Q(Q[3]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][4] + (.C(aclk), + .CE(E), + .D(D[4]), + .Q(Q[4]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][5] + (.C(aclk), + .CE(E), + .D(D[5]), + .Q(Q[5]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][6] + (.C(aclk), + .CE(E), + .D(D[6]), + .Q(Q[6]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][7] + (.C(aclk), + .CE(E), + .D(D[7]), + .Q(Q[7]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][8] + (.C(aclk), + .CE(E), + .D(D[8]), + .Q(\needs_delay.shift_register_reg_n_0_[1][8] ), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][9] + (.C(aclk), + .CE(E), + .D(D[9]), + .Q(Q[8]), + .R(sclr)); +endmodule + +(* ORIG_REF_NAME = "delay_sclr" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized6 + (da, + sclr, + E, + D, + aclk); + output [7:0]da; + input sclr; + input [0:0]E; + input [7:0]D; + input aclk; + + wire [7:0]D; + wire [0:0]E; + wire aclk; + wire [7:0]da; + wire sclr; + + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][0] + (.C(aclk), + .CE(E), + .D(D[0]), + .Q(da[0]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][1] + (.C(aclk), + .CE(E), + .D(D[1]), + .Q(da[1]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][2] + (.C(aclk), + .CE(E), + .D(D[2]), + .Q(da[2]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][3] + (.C(aclk), + .CE(E), + .D(D[3]), + .Q(da[3]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][4] + (.C(aclk), + .CE(E), + .D(D[4]), + .Q(da[4]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][5] + (.C(aclk), + .CE(E), + .D(D[5]), + .Q(da[5]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][6] + (.C(aclk), + .CE(E), + .D(D[6]), + .Q(da[6]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][7] + (.C(aclk), + .CE(E), + .D(D[7]), + .Q(da[7]), + .R(sclr)); +endmodule + +(* ORIG_REF_NAME = "delay_sclr" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized6_10 + (da, + sclr, + E, + D, + aclk); + output [7:0]da; + input sclr; + input [0:0]E; + input [7:0]D; + input aclk; + + wire [7:0]D; + wire [0:0]E; + wire aclk; + wire [7:0]da; + wire sclr; + + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][0] + (.C(aclk), + .CE(E), + .D(D[0]), + .Q(da[0]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][1] + (.C(aclk), + .CE(E), + .D(D[1]), + .Q(da[1]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][2] + (.C(aclk), + .CE(E), + .D(D[2]), + .Q(da[2]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][3] + (.C(aclk), + .CE(E), + .D(D[3]), + .Q(da[3]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][4] + (.C(aclk), + .CE(E), + .D(D[4]), + .Q(da[4]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][5] + (.C(aclk), + .CE(E), + .D(D[5]), + .Q(da[5]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][6] + (.C(aclk), + .CE(E), + .D(D[6]), + .Q(da[6]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][7] + (.C(aclk), + .CE(E), + .D(D[7]), + .Q(da[7]), + .R(sclr)); +endmodule + +(* ORIG_REF_NAME = "delay_sclr" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized6_9 + (da, + sclr, + E, + D, + aclk); + output [7:0]da; + input sclr; + input [0:0]E; + input [7:0]D; + input aclk; + + wire [7:0]D; + wire [0:0]E; + wire aclk; + wire [7:0]da; + wire sclr; + + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][0] + (.C(aclk), + .CE(E), + .D(D[0]), + .Q(da[0]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][1] + (.C(aclk), + .CE(E), + .D(D[1]), + .Q(da[1]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][2] + (.C(aclk), + .CE(E), + .D(D[2]), + .Q(da[2]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][3] + (.C(aclk), + .CE(E), + .D(D[3]), + .Q(da[3]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][4] + (.C(aclk), + .CE(E), + .D(D[4]), + .Q(da[4]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][5] + (.C(aclk), + .CE(E), + .D(D[5]), + .Q(da[5]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][6] + (.C(aclk), + .CE(E), + .D(D[6]), + .Q(da[6]), + .R(sclr)); + FDRE #( + .INIT(1'b0)) + \needs_delay.shift_register_reg[1][7] + (.C(aclk), + .CE(E), + .D(D[7]), + .Q(da[7]), + .R(sclr)); +endmodule + +(* ORIG_REF_NAME = "dp_ram" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_dp_ram + (\read_ptr_int_reg[3] , + ADDRA, + m_axis_video_tuser_sof, + Q, + \genr_control_regs[0] , + aclken, + m_axis_video_tready, + axi_fifo_empty, + aclken_0, + aclk, + wen, + da, + \write_ptr_int_reg[3] ); + output \read_ptr_int_reg[3] ; + output [3:0]ADDRA; + output [25:0]m_axis_video_tuser_sof; + input [3:0]Q; + input [0:0]\genr_control_regs[0] ; + input aclken; + input m_axis_video_tready; + input axi_fifo_empty; + input aclken_0; + input aclk; + input wen; + input [25:0]da; + input [3:0]\write_ptr_int_reg[3] ; + + wire [3:0]ADDRA; + wire \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_0 ; + wire \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_1 ; + wire \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_2 ; + wire \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_3 ; + wire \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_4 ; + wire \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_5 ; + wire \GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_0 ; + wire \GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_1 ; + wire \GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_2 ; + wire \GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_3 ; + wire \GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_4 ; + wire \GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_5 ; + wire \GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_0 ; + wire \GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_1 ; + wire \GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_2 ; + wire \GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_3 ; + wire \GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_4 ; + wire \GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_5 ; + wire \GenerateDoutWriteFirstA.mem_reg_0_15_24_25_n_0 ; + wire \GenerateDoutWriteFirstA.mem_reg_0_15_24_25_n_1 ; + wire \GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_0 ; + wire \GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_1 ; + wire \GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_2 ; + wire \GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_3 ; + wire \GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_4 ; + wire \GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_5 ; + wire [3:0]Q; + wire aclk; + wire aclken; + wire aclken_0; + wire axi_fifo_empty; + wire [25:0]da; + wire [0:0]\genr_control_regs[0] ; + wire m_axis_video_tready; + wire [25:0]m_axis_video_tuser_sof; + wire \read_ptr_int_reg[3] ; + wire wen; + wire [3:0]\write_ptr_int_reg[3] ; + wire [1:0]\NLW_GenerateDoutWriteFirstA.mem_reg_0_15_0_5_DOD_UNCONNECTED ; + wire [1:0]\NLW_GenerateDoutWriteFirstA.mem_reg_0_15_12_17_DOD_UNCONNECTED ; + wire [1:0]\NLW_GenerateDoutWriteFirstA.mem_reg_0_15_18_23_DOD_UNCONNECTED ; + wire [1:0]\NLW_GenerateDoutWriteFirstA.mem_reg_0_15_24_25_DOB_UNCONNECTED ; + wire [1:0]\NLW_GenerateDoutWriteFirstA.mem_reg_0_15_24_25_DOC_UNCONNECTED ; + wire [1:0]\NLW_GenerateDoutWriteFirstA.mem_reg_0_15_24_25_DOD_UNCONNECTED ; + wire [1:0]\NLW_GenerateDoutWriteFirstA.mem_reg_0_15_6_11_DOD_UNCONNECTED ; + + (* METHODOLOGY_DRC_VIOS = "" *) + RAM32M #( + .INIT_A(64'h0000000000000000), + .INIT_B(64'h0000000000000000), + .INIT_C(64'h0000000000000000), + .INIT_D(64'h0000000000000000)) + \GenerateDoutWriteFirstA.mem_reg_0_15_0_5 + (.ADDRA({1'b0,ADDRA}), + .ADDRB({1'b0,ADDRA}), + .ADDRC({1'b0,ADDRA}), + .ADDRD({1'b0,\write_ptr_int_reg[3] }), + .DIA(da[1:0]), + .DIB(da[3:2]), + .DIC(da[5:4]), + .DID({1'b0,1'b0}), + .DOA({\GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_0 ,\GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_1 }), + .DOB({\GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_2 ,\GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_3 }), + .DOC({\GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_4 ,\GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_5 }), + .DOD(\NLW_GenerateDoutWriteFirstA.mem_reg_0_15_0_5_DOD_UNCONNECTED [1:0]), + .WCLK(aclk), + .WE(wen)); + LUT3 #( + .INIT(8'h6A)) + \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_i_2 + (.I0(Q[3]), + .I1(Q[2]), + .I2(\read_ptr_int_reg[3] ), + .O(ADDRA[3])); + LUT6 #( + .INIT(64'hAAAAA6AAAAAAAAAA)) + \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_i_3 + (.I0(Q[2]), + .I1(Q[1]), + .I2(axi_fifo_empty), + .I3(m_axis_video_tready), + .I4(aclken_0), + .I5(Q[0]), + .O(ADDRA[2])); + LUT6 #( + .INIT(64'hAAAAAAAA6AAAAAAA)) + \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_i_4 + (.I0(Q[1]), + .I1(Q[0]), + .I2(\genr_control_regs[0] ), + .I3(aclken), + .I4(m_axis_video_tready), + .I5(axi_fifo_empty), + .O(ADDRA[1])); + LUT5 #( + .INIT(32'h9AAAAAAA)) + \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_i_5 + (.I0(Q[0]), + .I1(axi_fifo_empty), + .I2(m_axis_video_tready), + .I3(aclken), + .I4(\genr_control_regs[0] ), + .O(ADDRA[0])); + LUT6 #( + .INIT(64'h0000800000000000)) + \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_i_6__0 + (.I0(Q[0]), + .I1(\genr_control_regs[0] ), + .I2(aclken), + .I3(m_axis_video_tready), + .I4(axi_fifo_empty), + .I5(Q[1]), + .O(\read_ptr_int_reg[3] )); + (* METHODOLOGY_DRC_VIOS = "" *) + RAM32M #( + .INIT_A(64'h0000000000000000), + .INIT_B(64'h0000000000000000), + .INIT_C(64'h0000000000000000), + .INIT_D(64'h0000000000000000)) + \GenerateDoutWriteFirstA.mem_reg_0_15_12_17 + (.ADDRA({1'b0,ADDRA}), + .ADDRB({1'b0,ADDRA}), + .ADDRC({1'b0,ADDRA}), + .ADDRD({1'b0,\write_ptr_int_reg[3] }), + .DIA(da[13:12]), + .DIB(da[15:14]), + .DIC(da[17:16]), + .DID({1'b0,1'b0}), + .DOA({\GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_0 ,\GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_1 }), + .DOB({\GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_2 ,\GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_3 }), + .DOC({\GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_4 ,\GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_5 }), + .DOD(\NLW_GenerateDoutWriteFirstA.mem_reg_0_15_12_17_DOD_UNCONNECTED [1:0]), + .WCLK(aclk), + .WE(wen)); + (* METHODOLOGY_DRC_VIOS = "" *) + RAM32M #( + .INIT_A(64'h0000000000000000), + .INIT_B(64'h0000000000000000), + .INIT_C(64'h0000000000000000), + .INIT_D(64'h0000000000000000)) + \GenerateDoutWriteFirstA.mem_reg_0_15_18_23 + (.ADDRA({1'b0,ADDRA}), + .ADDRB({1'b0,ADDRA}), + .ADDRC({1'b0,ADDRA}), + .ADDRD({1'b0,\write_ptr_int_reg[3] }), + .DIA(da[19:18]), + .DIB(da[21:20]), + .DIC(da[23:22]), + .DID({1'b0,1'b0}), + .DOA({\GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_0 ,\GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_1 }), + .DOB({\GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_2 ,\GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_3 }), + .DOC({\GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_4 ,\GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_5 }), + .DOD(\NLW_GenerateDoutWriteFirstA.mem_reg_0_15_18_23_DOD_UNCONNECTED [1:0]), + .WCLK(aclk), + .WE(wen)); + (* METHODOLOGY_DRC_VIOS = "" *) + RAM32M #( + .INIT_A(64'h0000000000000000), + .INIT_B(64'h0000000000000000), + .INIT_C(64'h0000000000000000), + .INIT_D(64'h0000000000000000)) + \GenerateDoutWriteFirstA.mem_reg_0_15_24_25 + (.ADDRA({1'b0,ADDRA}), + .ADDRB({1'b0,ADDRA}), + .ADDRC({1'b0,ADDRA}), + .ADDRD({1'b0,\write_ptr_int_reg[3] }), + .DIA(da[25:24]), + .DIB({1'b0,1'b0}), + .DIC({1'b0,1'b0}), + .DID({1'b0,1'b0}), + .DOA({\GenerateDoutWriteFirstA.mem_reg_0_15_24_25_n_0 ,\GenerateDoutWriteFirstA.mem_reg_0_15_24_25_n_1 }), + .DOB(\NLW_GenerateDoutWriteFirstA.mem_reg_0_15_24_25_DOB_UNCONNECTED [1:0]), + .DOC(\NLW_GenerateDoutWriteFirstA.mem_reg_0_15_24_25_DOC_UNCONNECTED [1:0]), + .DOD(\NLW_GenerateDoutWriteFirstA.mem_reg_0_15_24_25_DOD_UNCONNECTED [1:0]), + .WCLK(aclk), + .WE(wen)); + (* METHODOLOGY_DRC_VIOS = "" *) + RAM32M #( + .INIT_A(64'h0000000000000000), + .INIT_B(64'h0000000000000000), + .INIT_C(64'h0000000000000000), + .INIT_D(64'h0000000000000000)) + \GenerateDoutWriteFirstA.mem_reg_0_15_6_11 + (.ADDRA({1'b0,ADDRA}), + .ADDRB({1'b0,ADDRA}), + .ADDRC({1'b0,ADDRA}), + .ADDRD({1'b0,\write_ptr_int_reg[3] }), + .DIA(da[7:6]), + .DIB(da[9:8]), + .DIC(da[11:10]), + .DID({1'b0,1'b0}), + .DOA({\GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_0 ,\GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_1 }), + .DOB({\GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_2 ,\GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_3 }), + .DOC({\GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_4 ,\GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_5 }), + .DOD(\NLW_GenerateDoutWriteFirstA.mem_reg_0_15_6_11_DOD_UNCONNECTED [1:0]), + .WCLK(aclk), + .WE(wen)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_1 ), + .Q(m_axis_video_tuser_sof[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[10] + (.C(aclk), + .CE(1'b1), + .D(\GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_5 ), + .Q(m_axis_video_tuser_sof[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[11] + (.C(aclk), + .CE(1'b1), + .D(\GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_4 ), + .Q(m_axis_video_tuser_sof[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[12] + (.C(aclk), + .CE(1'b1), + .D(\GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_1 ), + .Q(m_axis_video_tuser_sof[12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[13] + (.C(aclk), + .CE(1'b1), + .D(\GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_0 ), + .Q(m_axis_video_tuser_sof[13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[14] + (.C(aclk), + .CE(1'b1), + .D(\GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_3 ), + .Q(m_axis_video_tuser_sof[14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[15] + (.C(aclk), + .CE(1'b1), + .D(\GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_2 ), + .Q(m_axis_video_tuser_sof[15]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[16] + (.C(aclk), + .CE(1'b1), + .D(\GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_5 ), + .Q(m_axis_video_tuser_sof[16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[17] + (.C(aclk), + .CE(1'b1), + .D(\GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_4 ), + .Q(m_axis_video_tuser_sof[17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[18] + (.C(aclk), + .CE(1'b1), + .D(\GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_1 ), + .Q(m_axis_video_tuser_sof[18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[19] + (.C(aclk), + .CE(1'b1), + .D(\GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_0 ), + .Q(m_axis_video_tuser_sof[19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_0 ), + .Q(m_axis_video_tuser_sof[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[20] + (.C(aclk), + .CE(1'b1), + .D(\GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_3 ), + .Q(m_axis_video_tuser_sof[20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[21] + (.C(aclk), + .CE(1'b1), + .D(\GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_2 ), + .Q(m_axis_video_tuser_sof[21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[22] + (.C(aclk), + .CE(1'b1), + .D(\GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_5 ), + .Q(m_axis_video_tuser_sof[22]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[23] + (.C(aclk), + .CE(1'b1), + .D(\GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_4 ), + .Q(m_axis_video_tuser_sof[23]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[24] + (.C(aclk), + .CE(1'b1), + .D(\GenerateDoutWriteFirstA.mem_reg_0_15_24_25_n_1 ), + .Q(m_axis_video_tuser_sof[24]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[25] + (.C(aclk), + .CE(1'b1), + .D(\GenerateDoutWriteFirstA.mem_reg_0_15_24_25_n_0 ), + .Q(m_axis_video_tuser_sof[25]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[2] + (.C(aclk), + .CE(1'b1), + .D(\GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_3 ), + .Q(m_axis_video_tuser_sof[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[3] + (.C(aclk), + .CE(1'b1), + .D(\GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_2 ), + .Q(m_axis_video_tuser_sof[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[4] + (.C(aclk), + .CE(1'b1), + .D(\GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_5 ), + .Q(m_axis_video_tuser_sof[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[5] + (.C(aclk), + .CE(1'b1), + .D(\GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_4 ), + .Q(m_axis_video_tuser_sof[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[6] + (.C(aclk), + .CE(1'b1), + .D(\GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_1 ), + .Q(m_axis_video_tuser_sof[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[7] + (.C(aclk), + .CE(1'b1), + .D(\GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_0 ), + .Q(m_axis_video_tuser_sof[7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[8] + (.C(aclk), + .CE(1'b1), + .D(\GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_3 ), + .Q(m_axis_video_tuser_sof[8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[9] + (.C(aclk), + .CE(1'b1), + .D(\GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_2 ), + .Q(m_axis_video_tuser_sof[9]), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "dp_ram" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_dp_ram_11 + (D, + \read_ptr_reg[0] , + p_0_in, + reg_update, + sof_late_i_reg, + Q, + empty_match_reg, + fifo_rd_i_reg, + depth_match_reg, + resetn_out, + \genr_control_regs[0] , + aclken, + s_axis_video_tvalid, + s_axis_video_tready, + aclk, + da, + \write_ptr_reg[3] ); + output [3:0]D; + output \read_ptr_reg[0] ; + output p_0_in; + output reg_update; + output [25:0]sof_late_i_reg; + input [3:0]Q; + input empty_match_reg; + input fifo_rd_i_reg; + input depth_match_reg; + input resetn_out; + input [1:0]\genr_control_regs[0] ; + input aclken; + input s_axis_video_tvalid; + input s_axis_video_tready; + input aclk; + input [25:0]da; + input [3:0]\write_ptr_reg[3] ; + + wire [3:0]D; + wire [3:0]Q; + wire aclk; + wire aclken; + wire [25:0]da; + wire depth_match_reg; + wire empty_match_reg; + wire fifo_rd_i_reg; + wire [1:0]\genr_control_regs[0] ; + wire p_0_in; + wire [25:0]p_2_out; + wire \read_ptr_reg[0] ; + wire reg_update; + wire resetn_out; + wire s_axis_video_tready; + wire s_axis_video_tvalid; + wire [25:0]sof_late_i_reg; + wire [3:0]\write_ptr_reg[3] ; + wire [1:0]\NLW_GenerateDoutWriteFirstA.mem_reg_0_15_0_5_DOD_UNCONNECTED ; + wire [1:0]\NLW_GenerateDoutWriteFirstA.mem_reg_0_15_12_17_DOD_UNCONNECTED ; + wire [1:0]\NLW_GenerateDoutWriteFirstA.mem_reg_0_15_18_23_DOD_UNCONNECTED ; + wire [1:0]\NLW_GenerateDoutWriteFirstA.mem_reg_0_15_24_25_DOB_UNCONNECTED ; + wire [1:0]\NLW_GenerateDoutWriteFirstA.mem_reg_0_15_24_25_DOC_UNCONNECTED ; + wire [1:0]\NLW_GenerateDoutWriteFirstA.mem_reg_0_15_24_25_DOD_UNCONNECTED ; + wire [1:0]\NLW_GenerateDoutWriteFirstA.mem_reg_0_15_6_11_DOD_UNCONNECTED ; + + (* METHODOLOGY_DRC_VIOS = "" *) + RAM32M #( + .INIT_A(64'h0000000000000000), + .INIT_B(64'h0000000000000000), + .INIT_C(64'h0000000000000000), + .INIT_D(64'h0000000000000000)) + \GenerateDoutWriteFirstA.mem_reg_0_15_0_5 + (.ADDRA({1'b0,D}), + .ADDRB({1'b0,D}), + .ADDRC({1'b0,D}), + .ADDRD({1'b0,\write_ptr_reg[3] }), + .DIA(da[1:0]), + .DIB(da[3:2]), + .DIC(da[5:4]), + .DID({1'b0,1'b0}), + .DOA(p_2_out[1:0]), + .DOB(p_2_out[3:2]), + .DOC(p_2_out[5:4]), + .DOD(\NLW_GenerateDoutWriteFirstA.mem_reg_0_15_0_5_DOD_UNCONNECTED [1:0]), + .WCLK(aclk), + .WE(p_0_in)); + LUT6 #( + .INIT(64'h4000000000000000)) + \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_i_1__0 + (.I0(depth_match_reg), + .I1(resetn_out), + .I2(\genr_control_regs[0] [0]), + .I3(aclken), + .I4(s_axis_video_tvalid), + .I5(s_axis_video_tready), + .O(p_0_in)); + LUT5 #( + .INIT(32'h6AAAAAAA)) + \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_i_2__0 + (.I0(Q[3]), + .I1(Q[1]), + .I2(\read_ptr_reg[0] ), + .I3(Q[0]), + .I4(Q[2]), + .O(D[3])); + LUT4 #( + .INIT(16'h6AAA)) + \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_i_3__0 + (.I0(Q[2]), + .I1(Q[0]), + .I2(\read_ptr_reg[0] ), + .I3(Q[1]), + .O(D[2])); + LUT3 #( + .INIT(8'h6A)) + \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_i_4__0 + (.I0(Q[1]), + .I1(\read_ptr_reg[0] ), + .I2(Q[0]), + .O(D[1])); + LUT2 #( + .INIT(4'h6)) + \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_i_5__0 + (.I0(Q[0]), + .I1(\read_ptr_reg[0] ), + .O(D[0])); + LUT2 #( + .INIT(4'h1)) + \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_i_6 + (.I0(empty_match_reg), + .I1(fifo_rd_i_reg), + .O(\read_ptr_reg[0] )); + (* METHODOLOGY_DRC_VIOS = "" *) + RAM32M #( + .INIT_A(64'h0000000000000000), + .INIT_B(64'h0000000000000000), + .INIT_C(64'h0000000000000000), + .INIT_D(64'h0000000000000000)) + \GenerateDoutWriteFirstA.mem_reg_0_15_12_17 + (.ADDRA({1'b0,D}), + .ADDRB({1'b0,D}), + .ADDRC({1'b0,D}), + .ADDRD({1'b0,\write_ptr_reg[3] }), + .DIA(da[13:12]), + .DIB(da[15:14]), + .DIC(da[17:16]), + .DID({1'b0,1'b0}), + .DOA(p_2_out[13:12]), + .DOB(p_2_out[15:14]), + .DOC(p_2_out[17:16]), + .DOD(\NLW_GenerateDoutWriteFirstA.mem_reg_0_15_12_17_DOD_UNCONNECTED [1:0]), + .WCLK(aclk), + .WE(p_0_in)); + (* METHODOLOGY_DRC_VIOS = "" *) + RAM32M #( + .INIT_A(64'h0000000000000000), + .INIT_B(64'h0000000000000000), + .INIT_C(64'h0000000000000000), + .INIT_D(64'h0000000000000000)) + \GenerateDoutWriteFirstA.mem_reg_0_15_18_23 + (.ADDRA({1'b0,D}), + .ADDRB({1'b0,D}), + .ADDRC({1'b0,D}), + .ADDRD({1'b0,\write_ptr_reg[3] }), + .DIA(da[19:18]), + .DIB(da[21:20]), + .DIC(da[23:22]), + .DID({1'b0,1'b0}), + .DOA(p_2_out[19:18]), + .DOB(p_2_out[21:20]), + .DOC(p_2_out[23:22]), + .DOD(\NLW_GenerateDoutWriteFirstA.mem_reg_0_15_18_23_DOD_UNCONNECTED [1:0]), + .WCLK(aclk), + .WE(p_0_in)); + (* METHODOLOGY_DRC_VIOS = "" *) + RAM32M #( + .INIT_A(64'h0000000000000000), + .INIT_B(64'h0000000000000000), + .INIT_C(64'h0000000000000000), + .INIT_D(64'h0000000000000000)) + \GenerateDoutWriteFirstA.mem_reg_0_15_24_25 + (.ADDRA({1'b0,D}), + .ADDRB({1'b0,D}), + .ADDRC({1'b0,D}), + .ADDRD({1'b0,\write_ptr_reg[3] }), + .DIA(da[25:24]), + .DIB({1'b0,1'b0}), + .DIC({1'b0,1'b0}), + .DID({1'b0,1'b0}), + .DOA(p_2_out[25:24]), + .DOB(\NLW_GenerateDoutWriteFirstA.mem_reg_0_15_24_25_DOB_UNCONNECTED [1:0]), + .DOC(\NLW_GenerateDoutWriteFirstA.mem_reg_0_15_24_25_DOC_UNCONNECTED [1:0]), + .DOD(\NLW_GenerateDoutWriteFirstA.mem_reg_0_15_24_25_DOD_UNCONNECTED [1:0]), + .WCLK(aclk), + .WE(p_0_in)); + (* METHODOLOGY_DRC_VIOS = "" *) + RAM32M #( + .INIT_A(64'h0000000000000000), + .INIT_B(64'h0000000000000000), + .INIT_C(64'h0000000000000000), + .INIT_D(64'h0000000000000000)) + \GenerateDoutWriteFirstA.mem_reg_0_15_6_11 + (.ADDRA({1'b0,D}), + .ADDRB({1'b0,D}), + .ADDRC({1'b0,D}), + .ADDRD({1'b0,\write_ptr_reg[3] }), + .DIA(da[7:6]), + .DIB(da[9:8]), + .DIC(da[11:10]), + .DID({1'b0,1'b0}), + .DOA(p_2_out[7:6]), + .DOB(p_2_out[9:8]), + .DOC(p_2_out[11:10]), + .DOD(\NLW_GenerateDoutWriteFirstA.mem_reg_0_15_6_11_DOD_UNCONNECTED [1:0]), + .WCLK(aclk), + .WE(p_0_in)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[0] + (.C(aclk), + .CE(1'b1), + .D(p_2_out[0]), + .Q(sof_late_i_reg[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[10] + (.C(aclk), + .CE(1'b1), + .D(p_2_out[10]), + .Q(sof_late_i_reg[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[11] + (.C(aclk), + .CE(1'b1), + .D(p_2_out[11]), + .Q(sof_late_i_reg[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[12] + (.C(aclk), + .CE(1'b1), + .D(p_2_out[12]), + .Q(sof_late_i_reg[12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[13] + (.C(aclk), + .CE(1'b1), + .D(p_2_out[13]), + .Q(sof_late_i_reg[13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[14] + (.C(aclk), + .CE(1'b1), + .D(p_2_out[14]), + .Q(sof_late_i_reg[14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[15] + (.C(aclk), + .CE(1'b1), + .D(p_2_out[15]), + .Q(sof_late_i_reg[15]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[16] + (.C(aclk), + .CE(1'b1), + .D(p_2_out[16]), + .Q(sof_late_i_reg[16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[17] + (.C(aclk), + .CE(1'b1), + .D(p_2_out[17]), + .Q(sof_late_i_reg[17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[18] + (.C(aclk), + .CE(1'b1), + .D(p_2_out[18]), + .Q(sof_late_i_reg[18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[19] + (.C(aclk), + .CE(1'b1), + .D(p_2_out[19]), + .Q(sof_late_i_reg[19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[1] + (.C(aclk), + .CE(1'b1), + .D(p_2_out[1]), + .Q(sof_late_i_reg[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[20] + (.C(aclk), + .CE(1'b1), + .D(p_2_out[20]), + .Q(sof_late_i_reg[20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[21] + (.C(aclk), + .CE(1'b1), + .D(p_2_out[21]), + .Q(sof_late_i_reg[21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[22] + (.C(aclk), + .CE(1'b1), + .D(p_2_out[22]), + .Q(sof_late_i_reg[22]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[23] + (.C(aclk), + .CE(1'b1), + .D(p_2_out[23]), + .Q(sof_late_i_reg[23]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[24] + (.C(aclk), + .CE(1'b1), + .D(p_2_out[24]), + .Q(sof_late_i_reg[24]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[25] + (.C(aclk), + .CE(1'b1), + .D(p_2_out[25]), + .Q(sof_late_i_reg[25]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[2] + (.C(aclk), + .CE(1'b1), + .D(p_2_out[2]), + .Q(sof_late_i_reg[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[3] + (.C(aclk), + .CE(1'b1), + .D(p_2_out[3]), + .Q(sof_late_i_reg[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[4] + (.C(aclk), + .CE(1'b1), + .D(p_2_out[4]), + .Q(sof_late_i_reg[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[5] + (.C(aclk), + .CE(1'b1), + .D(p_2_out[5]), + .Q(sof_late_i_reg[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[6] + (.C(aclk), + .CE(1'b1), + .D(p_2_out[6]), + .Q(sof_late_i_reg[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[7] + (.C(aclk), + .CE(1'b1), + .D(p_2_out[7]), + .Q(sof_late_i_reg[7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[8] + (.C(aclk), + .CE(1'b1), + .D(p_2_out[8]), + .Q(sof_late_i_reg[8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GenerateDoutWriteFirstB.t_qb_reg[9] + (.C(aclk), + .CE(1'b1), + .D(p_2_out[9]), + .Q(sof_late_i_reg[9]), + .R(1'b0)); + LUT2 #( + .INIT(4'h8)) + U_VIDEO_CTRL_i_1 + (.I0(sof_late_i_reg[25]), + .I1(\genr_control_regs[0] [1]), + .O(reg_update)); +endmodule + +(* CREG = "0" *) (* HAS_C = "1" *) (* IWIDTHA = "9" *) +(* IWIDTHB = "17" *) (* ORIG_REF_NAME = "mac" *) (* OWIDTH = "26" *) +(* ROUND_MODE = "0" *) (* downgradeipidentifiedwarnings = "yes" *) (* mult_style = "pipe_block" *) +(* register_balancing = "yes" *) (* use_dsp48 = "yes" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_mac + (a, + b, + c, + p, + clk, + ce, + sclr); + input [8:0]a; + input [16:0]b; + input [25:0]c; + output [25:0]p; + input clk; + input ce; + input sclr; + + wire [8:0]a; + wire [16:0]b; + wire [25:0]c; + wire ce; + wire clk; + wire [25:0]p; + wire sclr; + wire NLW_mac_reg_CARRYCASCOUT_UNCONNECTED; + wire NLW_mac_reg_MULTSIGNOUT_UNCONNECTED; + wire NLW_mac_reg_OVERFLOW_UNCONNECTED; + wire NLW_mac_reg_PATTERNBDETECT_UNCONNECTED; + wire NLW_mac_reg_PATTERNDETECT_UNCONNECTED; + wire NLW_mac_reg_UNDERFLOW_UNCONNECTED; + wire [29:0]NLW_mac_reg_ACOUT_UNCONNECTED; + wire [17:0]NLW_mac_reg_BCOUT_UNCONNECTED; + wire [3:0]NLW_mac_reg_CARRYOUT_UNCONNECTED; + wire [47:26]NLW_mac_reg_P_UNCONNECTED; + wire [47:0]NLW_mac_reg_PCOUT_UNCONNECTED; + + DSP48E1 #( + .ACASCREG(1), + .ADREG(1), + .ALUMODEREG(0), + .AREG(1), + .AUTORESET_PATDET("NO_RESET"), + .A_INPUT("DIRECT"), + .BCASCREG(1), + .BREG(1), + .B_INPUT("DIRECT"), + .CARRYINREG(0), + .CARRYINSELREG(0), + .CREG(0), + .DREG(1), + .INMODEREG(0), + .MASK(48'h3FFFFFFFFFFF), + .MREG(1), + .OPMODEREG(0), + .PATTERN(48'h000000000000), + .PREG(1), + .SEL_MASK("MASK"), + .SEL_PATTERN("PATTERN"), + .USE_DPORT("FALSE"), + .USE_MULT("MULTIPLY"), + .USE_PATTERN_DETECT("NO_PATDET"), + .USE_SIMD("ONE48")) + mac_reg + (.A({b[16],b[16],b[16],b[16],b[16],b[16],b[16],b[16],b[16],b[16],b[16],b[16],b[16],b}), + .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .ACOUT(NLW_mac_reg_ACOUT_UNCONNECTED[29:0]), + .ALUMODE({1'b0,1'b0,1'b0,1'b0}), + .B({a[8],a[8],a[8],a[8],a[8],a[8],a[8],a[8],a[8],a}), + .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .BCOUT(NLW_mac_reg_BCOUT_UNCONNECTED[17:0]), + .C({c[25],c[25],c[25],c[25],c[25],c[25],c[25],c[25],c[25],c[25],c[25],c[25],c[25],c[25],c[25],c[25],c[25],c[25],c[25],c[25],c[25],c[25],c}), + .CARRYCASCIN(1'b0), + .CARRYCASCOUT(NLW_mac_reg_CARRYCASCOUT_UNCONNECTED), + .CARRYIN(1'b0), + .CARRYINSEL({1'b0,1'b0,1'b0}), + .CARRYOUT(NLW_mac_reg_CARRYOUT_UNCONNECTED[3:0]), + .CEA1(1'b0), + .CEA2(ce), + .CEAD(1'b0), + .CEALUMODE(1'b0), + .CEB1(1'b0), + .CEB2(ce), + .CEC(1'b0), + .CECARRYIN(1'b0), + .CECTRL(1'b0), + .CED(1'b0), + .CEINMODE(1'b0), + .CEM(ce), + .CEP(ce), + .CLK(clk), + .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}), + .MULTSIGNIN(1'b0), + .MULTSIGNOUT(NLW_mac_reg_MULTSIGNOUT_UNCONNECTED), + .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}), + .OVERFLOW(NLW_mac_reg_OVERFLOW_UNCONNECTED), + .P({NLW_mac_reg_P_UNCONNECTED[47:26],p}), + .PATTERNBDETECT(NLW_mac_reg_PATTERNBDETECT_UNCONNECTED), + .PATTERNDETECT(NLW_mac_reg_PATTERNDETECT_UNCONNECTED), + .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .PCOUT(NLW_mac_reg_PCOUT_UNCONNECTED[47:0]), + .RSTA(sclr), + .RSTALLCARRYIN(1'b0), + .RSTALUMODE(1'b0), + .RSTB(sclr), + .RSTC(1'b0), + .RSTCTRL(1'b0), + .RSTD(1'b0), + .RSTINMODE(1'b0), + .RSTM(sclr), + .RSTP(sclr), + .UNDERFLOW(NLW_mac_reg_UNDERFLOW_UNCONNECTED)); +endmodule + +(* CREG = "0" *) (* HAS_C = "1" *) (* IWIDTHA = "11" *) +(* IWIDTHB = "17" *) (* ORIG_REF_NAME = "mac" *) (* OWIDTH = "12" *) +(* ROUND_MODE = "0" *) (* downgradeipidentifiedwarnings = "yes" *) (* mult_style = "pipe_block" *) +(* register_balancing = "yes" *) (* use_dsp48 = "yes" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized0 + (a, + b, + c, + p, + clk, + ce, + sclr); + input [10:0]a; + input [16:0]b; + input [11:0]c; + output [11:0]p; + input clk; + input ce; + input sclr; + + wire [10:0]a; + wire [16:0]b; + wire [11:0]c; + wire ce; + wire clk; + wire mac_reg_n_100; + wire mac_reg_n_101; + wire mac_reg_n_102; + wire mac_reg_n_103; + wire mac_reg_n_104; + wire mac_reg_n_105; + wire mac_reg_n_90; + wire mac_reg_n_91; + wire mac_reg_n_92; + wire mac_reg_n_93; + wire mac_reg_n_94; + wire mac_reg_n_95; + wire mac_reg_n_96; + wire mac_reg_n_97; + wire mac_reg_n_98; + wire mac_reg_n_99; + wire [11:0]p; + wire sclr; + wire NLW_mac_reg_CARRYCASCOUT_UNCONNECTED; + wire NLW_mac_reg_MULTSIGNOUT_UNCONNECTED; + wire NLW_mac_reg_OVERFLOW_UNCONNECTED; + wire NLW_mac_reg_PATTERNBDETECT_UNCONNECTED; + wire NLW_mac_reg_PATTERNDETECT_UNCONNECTED; + wire NLW_mac_reg_UNDERFLOW_UNCONNECTED; + wire [29:0]NLW_mac_reg_ACOUT_UNCONNECTED; + wire [17:0]NLW_mac_reg_BCOUT_UNCONNECTED; + wire [3:0]NLW_mac_reg_CARRYOUT_UNCONNECTED; + wire [47:28]NLW_mac_reg_P_UNCONNECTED; + wire [47:0]NLW_mac_reg_PCOUT_UNCONNECTED; + + DSP48E1 #( + .ACASCREG(1), + .ADREG(1), + .ALUMODEREG(0), + .AREG(1), + .AUTORESET_PATDET("NO_RESET"), + .A_INPUT("DIRECT"), + .BCASCREG(1), + .BREG(1), + .B_INPUT("DIRECT"), + .CARRYINREG(0), + .CARRYINSELREG(0), + .CREG(0), + .DREG(1), + .INMODEREG(0), + .MASK(48'h3FFFFFFFFFFF), + .MREG(1), + .OPMODEREG(0), + .PATTERN(48'h000000000000), + .PREG(1), + .SEL_MASK("MASK"), + .SEL_PATTERN("PATTERN"), + .USE_DPORT("FALSE"), + .USE_MULT("MULTIPLY"), + .USE_PATTERN_DETECT("NO_PATDET"), + .USE_SIMD("ONE48")) + mac_reg + (.A({b[16],b[16],b[16],b[16],b[16],b[16],b[16],b[16],b[16],b[16],b[16],b[16],b[16],b}), + .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .ACOUT(NLW_mac_reg_ACOUT_UNCONNECTED[29:0]), + .ALUMODE({1'b0,1'b0,1'b0,1'b0}), + .B({a[10],a[10],a[10],a[10],a[10],a[10],a[10],a}), + .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .BCOUT(NLW_mac_reg_BCOUT_UNCONNECTED[17:0]), + .C({c[11],c[11],c[11],c[11],c[11],c[11],c[11],c[11],c[11],c[11],c[11],c[11],c[11],c[11],c[11],c[11],c[11],c[11],c[11],c[11],c,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), + .CARRYCASCIN(1'b0), + .CARRYCASCOUT(NLW_mac_reg_CARRYCASCOUT_UNCONNECTED), + .CARRYIN(1'b1), + .CARRYINSEL({1'b0,1'b0,1'b0}), + .CARRYOUT(NLW_mac_reg_CARRYOUT_UNCONNECTED[3:0]), + .CEA1(1'b0), + .CEA2(ce), + .CEAD(1'b0), + .CEALUMODE(1'b0), + .CEB1(1'b0), + .CEB2(ce), + .CEC(1'b0), + .CECARRYIN(1'b0), + .CECTRL(1'b0), + .CED(1'b0), + .CEINMODE(1'b0), + .CEM(ce), + .CEP(ce), + .CLK(clk), + .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}), + .MULTSIGNIN(1'b0), + .MULTSIGNOUT(NLW_mac_reg_MULTSIGNOUT_UNCONNECTED), + .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}), + .OVERFLOW(NLW_mac_reg_OVERFLOW_UNCONNECTED), + .P({NLW_mac_reg_P_UNCONNECTED[47:28],p,mac_reg_n_90,mac_reg_n_91,mac_reg_n_92,mac_reg_n_93,mac_reg_n_94,mac_reg_n_95,mac_reg_n_96,mac_reg_n_97,mac_reg_n_98,mac_reg_n_99,mac_reg_n_100,mac_reg_n_101,mac_reg_n_102,mac_reg_n_103,mac_reg_n_104,mac_reg_n_105}), + .PATTERNBDETECT(NLW_mac_reg_PATTERNBDETECT_UNCONNECTED), + .PATTERNDETECT(NLW_mac_reg_PATTERNDETECT_UNCONNECTED), + .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .PCOUT(NLW_mac_reg_PCOUT_UNCONNECTED[47:0]), + .RSTA(sclr), + .RSTALLCARRYIN(1'b0), + .RSTALUMODE(1'b0), + .RSTB(sclr), + .RSTC(1'b0), + .RSTCTRL(1'b0), + .RSTD(1'b0), + .RSTINMODE(1'b0), + .RSTM(sclr), + .RSTP(sclr), + .UNDERFLOW(NLW_mac_reg_UNDERFLOW_UNCONNECTED)); +endmodule + +(* CREG = "0" *) (* HAS_C = "1" *) (* IWIDTHA = "11" *) +(* IWIDTHB = "17" *) (* ORIG_REF_NAME = "mac" *) (* OWIDTH = "12" *) +(* ROUND_MODE = "0" *) (* downgradeipidentifiedwarnings = "yes" *) (* mult_style = "pipe_block" *) +(* register_balancing = "yes" *) (* use_dsp48 = "yes" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized1 + (a, + b, + c, + p, + clk, + ce, + sclr); + input [10:0]a; + input [16:0]b; + input [11:0]c; + output [11:0]p; + input clk; + input ce; + input sclr; + + wire [10:0]a; + wire [16:0]b; + wire [11:0]c; + wire ce; + wire clk; + wire mac_reg_n_100; + wire mac_reg_n_101; + wire mac_reg_n_102; + wire mac_reg_n_103; + wire mac_reg_n_104; + wire mac_reg_n_105; + wire mac_reg_n_90; + wire mac_reg_n_91; + wire mac_reg_n_92; + wire mac_reg_n_93; + wire mac_reg_n_94; + wire mac_reg_n_95; + wire mac_reg_n_96; + wire mac_reg_n_97; + wire mac_reg_n_98; + wire mac_reg_n_99; + wire [11:0]p; + wire sclr; + wire NLW_mac_reg_CARRYCASCOUT_UNCONNECTED; + wire NLW_mac_reg_MULTSIGNOUT_UNCONNECTED; + wire NLW_mac_reg_OVERFLOW_UNCONNECTED; + wire NLW_mac_reg_PATTERNBDETECT_UNCONNECTED; + wire NLW_mac_reg_PATTERNDETECT_UNCONNECTED; + wire NLW_mac_reg_UNDERFLOW_UNCONNECTED; + wire [29:0]NLW_mac_reg_ACOUT_UNCONNECTED; + wire [17:0]NLW_mac_reg_BCOUT_UNCONNECTED; + wire [3:0]NLW_mac_reg_CARRYOUT_UNCONNECTED; + wire [47:28]NLW_mac_reg_P_UNCONNECTED; + wire [47:0]NLW_mac_reg_PCOUT_UNCONNECTED; + + DSP48E1 #( + .ACASCREG(1), + .ADREG(1), + .ALUMODEREG(0), + .AREG(1), + .AUTORESET_PATDET("NO_RESET"), + .A_INPUT("DIRECT"), + .BCASCREG(1), + .BREG(1), + .B_INPUT("DIRECT"), + .CARRYINREG(0), + .CARRYINSELREG(0), + .CREG(0), + .DREG(1), + .INMODEREG(0), + .MASK(48'h3FFFFFFFFFFF), + .MREG(1), + .OPMODEREG(0), + .PATTERN(48'h000000000000), + .PREG(1), + .SEL_MASK("MASK"), + .SEL_PATTERN("PATTERN"), + .USE_DPORT("FALSE"), + .USE_MULT("MULTIPLY"), + .USE_PATTERN_DETECT("NO_PATDET"), + .USE_SIMD("ONE48")) + mac_reg + (.A({b[16],b[16],b[16],b[16],b[16],b[16],b[16],b[16],b[16],b[16],b[16],b[16],b[16],b}), + .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .ACOUT(NLW_mac_reg_ACOUT_UNCONNECTED[29:0]), + .ALUMODE({1'b0,1'b0,1'b0,1'b0}), + .B({a[10],a[10],a[10],a[10],a[10],a[10],a[10],a}), + .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .BCOUT(NLW_mac_reg_BCOUT_UNCONNECTED[17:0]), + .C({c[11],c[11],c[11],c[11],c[11],c[11],c[11],c[11],c[11],c[11],c[11],c[11],c[11],c[11],c[11],c[11],c[11],c[11],c[11],c[11],c,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), + .CARRYCASCIN(1'b0), + .CARRYCASCOUT(NLW_mac_reg_CARRYCASCOUT_UNCONNECTED), + .CARRYIN(1'b1), + .CARRYINSEL({1'b0,1'b0,1'b0}), + .CARRYOUT(NLW_mac_reg_CARRYOUT_UNCONNECTED[3:0]), + .CEA1(1'b0), + .CEA2(ce), + .CEAD(1'b0), + .CEALUMODE(1'b0), + .CEB1(1'b0), + .CEB2(ce), + .CEC(1'b0), + .CECARRYIN(1'b0), + .CECTRL(1'b0), + .CED(1'b0), + .CEINMODE(1'b0), + .CEM(ce), + .CEP(ce), + .CLK(clk), + .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}), + .MULTSIGNIN(1'b0), + .MULTSIGNOUT(NLW_mac_reg_MULTSIGNOUT_UNCONNECTED), + .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b1}), + .OVERFLOW(NLW_mac_reg_OVERFLOW_UNCONNECTED), + .P({NLW_mac_reg_P_UNCONNECTED[47:28],p,mac_reg_n_90,mac_reg_n_91,mac_reg_n_92,mac_reg_n_93,mac_reg_n_94,mac_reg_n_95,mac_reg_n_96,mac_reg_n_97,mac_reg_n_98,mac_reg_n_99,mac_reg_n_100,mac_reg_n_101,mac_reg_n_102,mac_reg_n_103,mac_reg_n_104,mac_reg_n_105}), + .PATTERNBDETECT(NLW_mac_reg_PATTERNBDETECT_UNCONNECTED), + .PATTERNDETECT(NLW_mac_reg_PATTERNDETECT_UNCONNECTED), + .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .PCOUT(NLW_mac_reg_PCOUT_UNCONNECTED[47:0]), + .RSTA(sclr), + .RSTALLCARRYIN(1'b0), + .RSTALUMODE(1'b0), + .RSTB(sclr), + .RSTC(1'b0), + .RSTCTRL(1'b0), + .RSTD(1'b0), + .RSTINMODE(1'b0), + .RSTM(sclr), + .RSTP(sclr), + .UNDERFLOW(NLW_mac_reg_UNDERFLOW_UNCONNECTED)); +endmodule + +(* ORIG_REF_NAME = "max_sat" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_max_sat + (\needs_delay.shift_register_reg[1][7] , + Q, + S, + DI, + p, + \core_control_regs[3] , + sclr, + E, + aclk, + \core_control_regs[2] ); + output [0:0]\needs_delay.shift_register_reg[1][7] ; + output [8:0]Q; + output [3:0]S; + output [3:0]DI; + input [9:0]p; + input [7:0]\core_control_regs[3] ; + input sclr; + input [0:0]E; + input aclk; + input [7:0]\core_control_regs[2] ; + + wire [3:0]DI; + wire [0:0]E; + wire [8:0]Q; + wire [3:0]S; + wire aclk; + wire [7:0]\core_control_regs[2] ; + wire [7:0]\core_control_regs[3] ; + wire gtOp_carry__0_n_3; + wire gtOp_carry_n_0; + wire gtOp_carry_n_1; + wire gtOp_carry_n_2; + wire gtOp_carry_n_3; + wire \needs_delay.shift_register[1][0]_i_1_n_0 ; + wire \needs_delay.shift_register[1][1]_i_1_n_0 ; + wire \needs_delay.shift_register[1][2]_i_1_n_0 ; + wire \needs_delay.shift_register[1][3]_i_1_n_0 ; + wire \needs_delay.shift_register[1][4]_i_1_n_0 ; + wire \needs_delay.shift_register[1][5]_i_1_n_0 ; + wire \needs_delay.shift_register[1][6]_i_1_n_0 ; + wire \needs_delay.shift_register[1][7]_i_1_n_0 ; + wire \needs_delay.shift_register[1][8]_i_1_n_0 ; + wire \needs_delay.shift_register[1][9]_i_1_n_0 ; + wire [0:0]\needs_delay.shift_register_reg[1][7] ; + wire [9:0]p; + wire reg_n_0; + wire reg_n_1; + wire reg_n_20; + wire reg_n_21; + wire reg_n_22; + wire reg_n_23; + wire reg_n_24; + wire reg_n_25; + wire reg_n_26; + wire reg_n_27; + wire sclr; + wire [3:0]NLW_gtOp_carry_O_UNCONNECTED; + wire [3:1]NLW_gtOp_carry__0_CO_UNCONNECTED; + wire [3:0]NLW_gtOp_carry__0_O_UNCONNECTED; + + CARRY4 gtOp_carry + (.CI(1'b0), + .CO({gtOp_carry_n_0,gtOp_carry_n_1,gtOp_carry_n_2,gtOp_carry_n_3}), + .CYINIT(1'b0), + .DI({reg_n_24,reg_n_25,reg_n_26,reg_n_27}), + .O(NLW_gtOp_carry_O_UNCONNECTED[3:0]), + .S({reg_n_20,reg_n_21,reg_n_22,reg_n_23})); + CARRY4 gtOp_carry__0 + (.CI(gtOp_carry_n_0), + .CO({NLW_gtOp_carry__0_CO_UNCONNECTED[3:1],gtOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,reg_n_0}), + .O(NLW_gtOp_carry__0_O_UNCONNECTED[3:0]), + .S({1'b0,1'b0,1'b0,reg_n_1})); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][0]_i_1 + (.I0(\core_control_regs[2] [0]), + .I1(p[0]), + .I2(gtOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][1]_i_1 + (.I0(\core_control_regs[2] [1]), + .I1(p[1]), + .I2(gtOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][2]_i_1 + (.I0(\core_control_regs[2] [2]), + .I1(p[2]), + .I2(gtOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][3]_i_1 + (.I0(\core_control_regs[2] [3]), + .I1(p[3]), + .I2(gtOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][4]_i_1 + (.I0(\core_control_regs[2] [4]), + .I1(p[4]), + .I2(gtOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][5]_i_1 + (.I0(\core_control_regs[2] [5]), + .I1(p[5]), + .I2(gtOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][6]_i_1 + (.I0(\core_control_regs[2] [6]), + .I1(p[6]), + .I2(gtOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][7]_i_1 + (.I0(\core_control_regs[2] [7]), + .I1(p[7]), + .I2(gtOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT2 #( + .INIT(4'h2)) + \needs_delay.shift_register[1][8]_i_1 + (.I0(p[8]), + .I1(gtOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][8]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT2 #( + .INIT(4'h2)) + \needs_delay.shift_register[1][9]_i_1 + (.I0(p[9]), + .I1(gtOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][9]_i_1_n_0 )); + Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized5_8 \reg + (.D({\needs_delay.shift_register[1][9]_i_1_n_0 ,\needs_delay.shift_register[1][8]_i_1_n_0 ,\needs_delay.shift_register[1][7]_i_1_n_0 ,\needs_delay.shift_register[1][6]_i_1_n_0 ,\needs_delay.shift_register[1][5]_i_1_n_0 ,\needs_delay.shift_register[1][4]_i_1_n_0 ,\needs_delay.shift_register[1][3]_i_1_n_0 ,\needs_delay.shift_register[1][2]_i_1_n_0 ,\needs_delay.shift_register[1][1]_i_1_n_0 ,\needs_delay.shift_register[1][0]_i_1_n_0 }), + .DI(reg_n_0), + .E(E), + .Q(Q), + .S(reg_n_1), + .aclk(aclk), + .\core_control_regs[2] (\core_control_regs[2] ), + .\core_control_regs[3] (\core_control_regs[3] ), + .\needs_delay.shift_register_reg[1][7]_0 (\needs_delay.shift_register_reg[1][7] ), + .\needs_delay.shift_register_reg[1][7]_1 (S), + .\needs_delay.shift_register_reg[1][7]_2 (DI), + .\needs_delay.shift_register_reg[1][9]_0 ({reg_n_20,reg_n_21,reg_n_22,reg_n_23}), + .\needs_delay.shift_register_reg[1][9]_1 ({reg_n_24,reg_n_25,reg_n_26,reg_n_27}), + .p(p), + .sclr(sclr)); +endmodule + +(* ORIG_REF_NAME = "max_sat" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_max_sat_2 + (\needs_delay.shift_register_reg[1][7] , + Q, + S, + DI, + p, + \core_control_regs[5] , + sclr, + E, + aclk, + \core_control_regs[4] ); + output [0:0]\needs_delay.shift_register_reg[1][7] ; + output [8:0]Q; + output [3:0]S; + output [3:0]DI; + input [9:0]p; + input [7:0]\core_control_regs[5] ; + input sclr; + input [0:0]E; + input aclk; + input [7:0]\core_control_regs[4] ; + + wire [3:0]DI; + wire [0:0]E; + wire [8:0]Q; + wire [3:0]S; + wire aclk; + wire [7:0]\core_control_regs[4] ; + wire [7:0]\core_control_regs[5] ; + wire gtOp_carry__0_n_3; + wire gtOp_carry_n_0; + wire gtOp_carry_n_1; + wire gtOp_carry_n_2; + wire gtOp_carry_n_3; + wire \needs_delay.shift_register[1][0]_i_1_n_0 ; + wire \needs_delay.shift_register[1][1]_i_1_n_0 ; + wire \needs_delay.shift_register[1][2]_i_1_n_0 ; + wire \needs_delay.shift_register[1][3]_i_1_n_0 ; + wire \needs_delay.shift_register[1][4]_i_1_n_0 ; + wire \needs_delay.shift_register[1][5]_i_1_n_0 ; + wire \needs_delay.shift_register[1][6]_i_1_n_0 ; + wire \needs_delay.shift_register[1][7]_i_1_n_0 ; + wire \needs_delay.shift_register[1][8]_i_1_n_0 ; + wire \needs_delay.shift_register[1][9]_i_1_n_0 ; + wire [0:0]\needs_delay.shift_register_reg[1][7] ; + wire [9:0]p; + wire reg_n_0; + wire reg_n_1; + wire reg_n_20; + wire reg_n_21; + wire reg_n_22; + wire reg_n_23; + wire reg_n_24; + wire reg_n_25; + wire reg_n_26; + wire reg_n_27; + wire sclr; + wire [3:0]NLW_gtOp_carry_O_UNCONNECTED; + wire [3:1]NLW_gtOp_carry__0_CO_UNCONNECTED; + wire [3:0]NLW_gtOp_carry__0_O_UNCONNECTED; + + CARRY4 gtOp_carry + (.CI(1'b0), + .CO({gtOp_carry_n_0,gtOp_carry_n_1,gtOp_carry_n_2,gtOp_carry_n_3}), + .CYINIT(1'b0), + .DI({reg_n_24,reg_n_25,reg_n_26,reg_n_27}), + .O(NLW_gtOp_carry_O_UNCONNECTED[3:0]), + .S({reg_n_20,reg_n_21,reg_n_22,reg_n_23})); + CARRY4 gtOp_carry__0 + (.CI(gtOp_carry_n_0), + .CO({NLW_gtOp_carry__0_CO_UNCONNECTED[3:1],gtOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,reg_n_0}), + .O(NLW_gtOp_carry__0_O_UNCONNECTED[3:0]), + .S({1'b0,1'b0,1'b0,reg_n_1})); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][0]_i_1 + (.I0(\core_control_regs[4] [0]), + .I1(p[0]), + .I2(gtOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][1]_i_1 + (.I0(\core_control_regs[4] [1]), + .I1(p[1]), + .I2(gtOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][2]_i_1 + (.I0(\core_control_regs[4] [2]), + .I1(p[2]), + .I2(gtOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][3]_i_1 + (.I0(\core_control_regs[4] [3]), + .I1(p[3]), + .I2(gtOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][4]_i_1 + (.I0(\core_control_regs[4] [4]), + .I1(p[4]), + .I2(gtOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][5]_i_1 + (.I0(\core_control_regs[4] [5]), + .I1(p[5]), + .I2(gtOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair37" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][6]_i_1 + (.I0(\core_control_regs[4] [6]), + .I1(p[6]), + .I2(gtOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair37" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][7]_i_1 + (.I0(\core_control_regs[4] [7]), + .I1(p[7]), + .I2(gtOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair38" *) + LUT2 #( + .INIT(4'h2)) + \needs_delay.shift_register[1][8]_i_1 + (.I0(p[8]), + .I1(gtOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][8]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair38" *) + LUT2 #( + .INIT(4'h2)) + \needs_delay.shift_register[1][9]_i_1 + (.I0(p[9]), + .I1(gtOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][9]_i_1_n_0 )); + Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized5_7 \reg + (.D({\needs_delay.shift_register[1][9]_i_1_n_0 ,\needs_delay.shift_register[1][8]_i_1_n_0 ,\needs_delay.shift_register[1][7]_i_1_n_0 ,\needs_delay.shift_register[1][6]_i_1_n_0 ,\needs_delay.shift_register[1][5]_i_1_n_0 ,\needs_delay.shift_register[1][4]_i_1_n_0 ,\needs_delay.shift_register[1][3]_i_1_n_0 ,\needs_delay.shift_register[1][2]_i_1_n_0 ,\needs_delay.shift_register[1][1]_i_1_n_0 ,\needs_delay.shift_register[1][0]_i_1_n_0 }), + .DI(reg_n_0), + .E(E), + .Q(Q), + .S(reg_n_1), + .aclk(aclk), + .\core_control_regs[4] (\core_control_regs[4] ), + .\core_control_regs[5] (\core_control_regs[5] ), + .\needs_delay.shift_register_reg[1][7]_0 (\needs_delay.shift_register_reg[1][7] ), + .\needs_delay.shift_register_reg[1][7]_1 (S), + .\needs_delay.shift_register_reg[1][7]_2 (DI), + .\needs_delay.shift_register_reg[1][9]_0 ({reg_n_20,reg_n_21,reg_n_22,reg_n_23}), + .\needs_delay.shift_register_reg[1][9]_1 ({reg_n_24,reg_n_25,reg_n_26,reg_n_27}), + .p(p), + .sclr(sclr)); +endmodule + +(* ORIG_REF_NAME = "max_sat" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_max_sat_3 + (\needs_delay.shift_register_reg[1][7] , + Q, + \needs_delay.shift_register_reg[1][7]_0 , + \needs_delay.shift_register_reg[1][7]_1 , + DI, + S, + \needs_delay.shift_register_reg[3][8] , + \needs_delay.shift_register_reg[3][8]_0 , + \core_control_regs[1] , + sclr, + E, + aclk, + \core_control_regs[0] , + \needs_delay.shift_register_reg[3][0] , + \needs_delay.shift_register_reg[3][1] , + \needs_delay.shift_register_reg[3][2] , + \needs_delay.shift_register_reg[3][3] , + \needs_delay.shift_register_reg[3][4] , + \needs_delay.shift_register_reg[3][5] , + \needs_delay.shift_register_reg[3][6] , + \needs_delay.shift_register_reg[3][7] , + \needs_delay.shift_register_reg[3][8]_1 , + \needs_delay.shift_register_reg[3][9] ); + output [0:0]\needs_delay.shift_register_reg[1][7] ; + output [8:0]Q; + output [3:0]\needs_delay.shift_register_reg[1][7]_0 ; + output [3:0]\needs_delay.shift_register_reg[1][7]_1 ; + input [3:0]DI; + input [3:0]S; + input [0:0]\needs_delay.shift_register_reg[3][8] ; + input [0:0]\needs_delay.shift_register_reg[3][8]_0 ; + input [7:0]\core_control_regs[1] ; + input sclr; + input [0:0]E; + input aclk; + input [7:0]\core_control_regs[0] ; + input \needs_delay.shift_register_reg[3][0] ; + input \needs_delay.shift_register_reg[3][1] ; + input \needs_delay.shift_register_reg[3][2] ; + input \needs_delay.shift_register_reg[3][3] ; + input \needs_delay.shift_register_reg[3][4] ; + input \needs_delay.shift_register_reg[3][5] ; + input \needs_delay.shift_register_reg[3][6] ; + input \needs_delay.shift_register_reg[3][7] ; + input \needs_delay.shift_register_reg[3][8]_1 ; + input \needs_delay.shift_register_reg[3][9] ; + + wire [3:0]DI; + wire [0:0]E; + wire [8:0]Q; + wire [3:0]S; + wire aclk; + wire [9:0]c; + wire [7:0]\core_control_regs[0] ; + wire [7:0]\core_control_regs[1] ; + wire gtOp; + wire gtOp_carry_n_0; + wire gtOp_carry_n_1; + wire gtOp_carry_n_2; + wire gtOp_carry_n_3; + wire [0:0]\needs_delay.shift_register_reg[1][7] ; + wire [3:0]\needs_delay.shift_register_reg[1][7]_0 ; + wire [3:0]\needs_delay.shift_register_reg[1][7]_1 ; + wire \needs_delay.shift_register_reg[3][0] ; + wire \needs_delay.shift_register_reg[3][1] ; + wire \needs_delay.shift_register_reg[3][2] ; + wire \needs_delay.shift_register_reg[3][3] ; + wire \needs_delay.shift_register_reg[3][4] ; + wire \needs_delay.shift_register_reg[3][5] ; + wire \needs_delay.shift_register_reg[3][6] ; + wire \needs_delay.shift_register_reg[3][7] ; + wire [0:0]\needs_delay.shift_register_reg[3][8] ; + wire [0:0]\needs_delay.shift_register_reg[3][8]_0 ; + wire \needs_delay.shift_register_reg[3][8]_1 ; + wire \needs_delay.shift_register_reg[3][9] ; + wire sclr; + wire [3:0]NLW_gtOp_carry_O_UNCONNECTED; + wire [3:1]NLW_gtOp_carry__0_CO_UNCONNECTED; + wire [3:0]NLW_gtOp_carry__0_O_UNCONNECTED; + + CARRY4 gtOp_carry + (.CI(1'b0), + .CO({gtOp_carry_n_0,gtOp_carry_n_1,gtOp_carry_n_2,gtOp_carry_n_3}), + .CYINIT(1'b0), + .DI(DI), + .O(NLW_gtOp_carry_O_UNCONNECTED[3:0]), + .S(S)); + CARRY4 gtOp_carry__0 + (.CI(gtOp_carry_n_0), + .CO({NLW_gtOp_carry__0_CO_UNCONNECTED[3:1],gtOp}), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,\needs_delay.shift_register_reg[3][8] }), + .O(NLW_gtOp_carry__0_O_UNCONNECTED[3:0]), + .S({1'b0,1'b0,1'b0,\needs_delay.shift_register_reg[3][8]_0 })); + (* SOFT_HLUTNM = "soft_lutpair39" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][0]_i_1 + (.I0(\core_control_regs[0] [0]), + .I1(\needs_delay.shift_register_reg[3][0] ), + .I2(gtOp), + .O(c[0])); + (* SOFT_HLUTNM = "soft_lutpair39" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][1]_i_1 + (.I0(\core_control_regs[0] [1]), + .I1(\needs_delay.shift_register_reg[3][1] ), + .I2(gtOp), + .O(c[1])); + (* SOFT_HLUTNM = "soft_lutpair40" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][2]_i_1 + (.I0(\core_control_regs[0] [2]), + .I1(\needs_delay.shift_register_reg[3][2] ), + .I2(gtOp), + .O(c[2])); + (* SOFT_HLUTNM = "soft_lutpair40" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][3]_i_1 + (.I0(\core_control_regs[0] [3]), + .I1(\needs_delay.shift_register_reg[3][3] ), + .I2(gtOp), + .O(c[3])); + (* SOFT_HLUTNM = "soft_lutpair41" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][4]_i_1 + (.I0(\core_control_regs[0] [4]), + .I1(\needs_delay.shift_register_reg[3][4] ), + .I2(gtOp), + .O(c[4])); + (* SOFT_HLUTNM = "soft_lutpair41" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][5]_i_1 + (.I0(\core_control_regs[0] [5]), + .I1(\needs_delay.shift_register_reg[3][5] ), + .I2(gtOp), + .O(c[5])); + (* SOFT_HLUTNM = "soft_lutpair42" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][6]_i_1 + (.I0(\core_control_regs[0] [6]), + .I1(\needs_delay.shift_register_reg[3][6] ), + .I2(gtOp), + .O(c[6])); + (* SOFT_HLUTNM = "soft_lutpair42" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][7]_i_1 + (.I0(\core_control_regs[0] [7]), + .I1(\needs_delay.shift_register_reg[3][7] ), + .I2(gtOp), + .O(c[7])); + (* SOFT_HLUTNM = "soft_lutpair43" *) + LUT2 #( + .INIT(4'h2)) + \needs_delay.shift_register[1][8]_i_1 + (.I0(\needs_delay.shift_register_reg[3][8]_1 ), + .I1(gtOp), + .O(c[8])); + (* SOFT_HLUTNM = "soft_lutpair43" *) + LUT2 #( + .INIT(4'h2)) + \needs_delay.shift_register[1][9]_i_1 + (.I0(\needs_delay.shift_register_reg[3][9] ), + .I1(gtOp), + .O(c[9])); + Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized5 \reg + (.D(c), + .E(E), + .Q(Q), + .aclk(aclk), + .\core_control_regs[1] (\core_control_regs[1] ), + .\needs_delay.shift_register_reg[1][7]_0 (\needs_delay.shift_register_reg[1][7] ), + .\needs_delay.shift_register_reg[1][7]_1 (\needs_delay.shift_register_reg[1][7]_0 ), + .\needs_delay.shift_register_reg[1][7]_2 (\needs_delay.shift_register_reg[1][7]_1 ), + .sclr(sclr)); +endmodule + +(* ORIG_REF_NAME = "min_sat" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_min_sat + (da, + DI, + S, + Q, + \needs_delay.shift_register_reg[1][8] , + sclr, + E, + aclk, + \core_control_regs[3] ); + output [7:0]da; + input [3:0]DI; + input [3:0]S; + input [8:0]Q; + input [0:0]\needs_delay.shift_register_reg[1][8] ; + input sclr; + input [0:0]E; + input aclk; + input [7:0]\core_control_regs[3] ; + + wire [3:0]DI; + wire [0:0]E; + wire [8:0]Q; + wire [3:0]S; + wire aclk; + wire [7:0]\core_control_regs[3] ; + wire [7:0]da; + wire ltOp_carry__0_n_3; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire \needs_delay.shift_register[1][0]_i_1_n_0 ; + wire \needs_delay.shift_register[1][1]_i_1_n_0 ; + wire \needs_delay.shift_register[1][2]_i_1_n_0 ; + wire \needs_delay.shift_register[1][3]_i_1_n_0 ; + wire \needs_delay.shift_register[1][4]_i_1_n_0 ; + wire \needs_delay.shift_register[1][5]_i_1_n_0 ; + wire \needs_delay.shift_register[1][6]_i_1_n_0 ; + wire \needs_delay.shift_register[1][7]_i_1_n_0 ; + wire [0:0]\needs_delay.shift_register_reg[1][8] ; + wire sclr; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:1]NLW_ltOp_carry__0_CO_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI(DI), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S(S)); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({NLW_ltOp_carry__0_CO_UNCONNECTED[3:1],ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,Q[8]}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({1'b0,1'b0,1'b0,\needs_delay.shift_register_reg[1][8] })); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][0]_i_1 + (.I0(\core_control_regs[3] [0]), + .I1(Q[0]), + .I2(ltOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][1]_i_1 + (.I0(\core_control_regs[3] [1]), + .I1(Q[1]), + .I2(ltOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][2]_i_1 + (.I0(\core_control_regs[3] [2]), + .I1(Q[2]), + .I2(ltOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][3]_i_1 + (.I0(\core_control_regs[3] [3]), + .I1(Q[3]), + .I2(ltOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][4]_i_1 + (.I0(\core_control_regs[3] [4]), + .I1(Q[4]), + .I2(ltOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][5]_i_1 + (.I0(\core_control_regs[3] [5]), + .I1(Q[5]), + .I2(ltOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][6]_i_1 + (.I0(\core_control_regs[3] [6]), + .I1(Q[6]), + .I2(ltOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][7]_i_1 + (.I0(\core_control_regs[3] [7]), + .I1(Q[7]), + .I2(ltOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][7]_i_1_n_0 )); + Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized6_10 \reg + (.D({\needs_delay.shift_register[1][7]_i_1_n_0 ,\needs_delay.shift_register[1][6]_i_1_n_0 ,\needs_delay.shift_register[1][5]_i_1_n_0 ,\needs_delay.shift_register[1][4]_i_1_n_0 ,\needs_delay.shift_register[1][3]_i_1_n_0 ,\needs_delay.shift_register[1][2]_i_1_n_0 ,\needs_delay.shift_register[1][1]_i_1_n_0 ,\needs_delay.shift_register[1][0]_i_1_n_0 }), + .E(E), + .aclk(aclk), + .da(da), + .sclr(sclr)); +endmodule + +(* ORIG_REF_NAME = "min_sat" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_min_sat_0 + (da, + DI, + S, + Q, + \needs_delay.shift_register_reg[1][8] , + sclr, + E, + aclk, + \core_control_regs[5] ); + output [7:0]da; + input [3:0]DI; + input [3:0]S; + input [8:0]Q; + input [0:0]\needs_delay.shift_register_reg[1][8] ; + input sclr; + input [0:0]E; + input aclk; + input [7:0]\core_control_regs[5] ; + + wire [3:0]DI; + wire [0:0]E; + wire [8:0]Q; + wire [3:0]S; + wire aclk; + wire [7:0]\core_control_regs[5] ; + wire [7:0]da; + wire ltOp_carry__0_n_3; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire \needs_delay.shift_register[1][0]_i_1_n_0 ; + wire \needs_delay.shift_register[1][1]_i_1_n_0 ; + wire \needs_delay.shift_register[1][2]_i_1_n_0 ; + wire \needs_delay.shift_register[1][3]_i_1_n_0 ; + wire \needs_delay.shift_register[1][4]_i_1_n_0 ; + wire \needs_delay.shift_register[1][5]_i_1_n_0 ; + wire \needs_delay.shift_register[1][6]_i_1_n_0 ; + wire \needs_delay.shift_register[1][7]_i_1_n_0 ; + wire [0:0]\needs_delay.shift_register_reg[1][8] ; + wire sclr; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:1]NLW_ltOp_carry__0_CO_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI(DI), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S(S)); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({NLW_ltOp_carry__0_CO_UNCONNECTED[3:1],ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,Q[8]}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({1'b0,1'b0,1'b0,\needs_delay.shift_register_reg[1][8] })); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][0]_i_1 + (.I0(\core_control_regs[5] [0]), + .I1(Q[0]), + .I2(ltOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][1]_i_1 + (.I0(\core_control_regs[5] [1]), + .I1(Q[1]), + .I2(ltOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][2]_i_1 + (.I0(\core_control_regs[5] [2]), + .I1(Q[2]), + .I2(ltOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][3]_i_1 + (.I0(\core_control_regs[5] [3]), + .I1(Q[3]), + .I2(ltOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][4]_i_1 + (.I0(\core_control_regs[5] [4]), + .I1(Q[4]), + .I2(ltOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][5]_i_1 + (.I0(\core_control_regs[5] [5]), + .I1(Q[5]), + .I2(ltOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][6]_i_1 + (.I0(\core_control_regs[5] [6]), + .I1(Q[6]), + .I2(ltOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][7]_i_1 + (.I0(\core_control_regs[5] [7]), + .I1(Q[7]), + .I2(ltOp_carry__0_n_3), + .O(\needs_delay.shift_register[1][7]_i_1_n_0 )); + Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized6_9 \reg + (.D({\needs_delay.shift_register[1][7]_i_1_n_0 ,\needs_delay.shift_register[1][6]_i_1_n_0 ,\needs_delay.shift_register[1][5]_i_1_n_0 ,\needs_delay.shift_register[1][4]_i_1_n_0 ,\needs_delay.shift_register[1][3]_i_1_n_0 ,\needs_delay.shift_register[1][2]_i_1_n_0 ,\needs_delay.shift_register[1][1]_i_1_n_0 ,\needs_delay.shift_register[1][0]_i_1_n_0 }), + .E(E), + .aclk(aclk), + .da(da), + .sclr(sclr)); +endmodule + +(* ORIG_REF_NAME = "min_sat" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_min_sat_1 + (da, + DI, + S, + Q, + \needs_delay.shift_register_reg[1][8] , + sclr, + E, + aclk, + \core_control_regs[1] ); + output [7:0]da; + input [3:0]DI; + input [3:0]S; + input [8:0]Q; + input [0:0]\needs_delay.shift_register_reg[1][8] ; + input sclr; + input [0:0]E; + input aclk; + input [7:0]\core_control_regs[1] ; + + wire [3:0]DI; + wire [0:0]E; + wire [8:0]Q; + wire [3:0]S; + wire aclk; + wire [7:0]\core_control_regs[1] ; + wire [7:0]da; + wire ltOp; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire \needs_delay.shift_register[1][0]_i_1_n_0 ; + wire \needs_delay.shift_register[1][1]_i_1_n_0 ; + wire \needs_delay.shift_register[1][2]_i_1_n_0 ; + wire \needs_delay.shift_register[1][3]_i_1_n_0 ; + wire \needs_delay.shift_register[1][4]_i_1_n_0 ; + wire \needs_delay.shift_register[1][5]_i_1_n_0 ; + wire \needs_delay.shift_register[1][6]_i_1_n_0 ; + wire \needs_delay.shift_register[1][7]_i_1_n_0 ; + wire [0:0]\needs_delay.shift_register_reg[1][8] ; + wire sclr; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:1]NLW_ltOp_carry__0_CO_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI(DI), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S(S)); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({NLW_ltOp_carry__0_CO_UNCONNECTED[3:1],ltOp}), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,Q[8]}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({1'b0,1'b0,1'b0,\needs_delay.shift_register_reg[1][8] })); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][0]_i_1 + (.I0(\core_control_regs[1] [0]), + .I1(Q[0]), + .I2(ltOp), + .O(\needs_delay.shift_register[1][0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][1]_i_1 + (.I0(\core_control_regs[1] [1]), + .I1(Q[1]), + .I2(ltOp), + .O(\needs_delay.shift_register[1][1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][2]_i_1 + (.I0(\core_control_regs[1] [2]), + .I1(Q[2]), + .I2(ltOp), + .O(\needs_delay.shift_register[1][2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][3]_i_1 + (.I0(\core_control_regs[1] [3]), + .I1(Q[3]), + .I2(ltOp), + .O(\needs_delay.shift_register[1][3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][4]_i_1 + (.I0(\core_control_regs[1] [4]), + .I1(Q[4]), + .I2(ltOp), + .O(\needs_delay.shift_register[1][4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][5]_i_1 + (.I0(\core_control_regs[1] [5]), + .I1(Q[5]), + .I2(ltOp), + .O(\needs_delay.shift_register[1][5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][6]_i_1 + (.I0(\core_control_regs[1] [6]), + .I1(Q[6]), + .I2(ltOp), + .O(\needs_delay.shift_register[1][6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT3 #( + .INIT(8'hAC)) + \needs_delay.shift_register[1][7]_i_1 + (.I0(\core_control_regs[1] [7]), + .I1(Q[7]), + .I2(ltOp), + .O(\needs_delay.shift_register[1][7]_i_1_n_0 )); + Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized6 \reg + (.D({\needs_delay.shift_register[1][7]_i_1_n_0 ,\needs_delay.shift_register[1][6]_i_1_n_0 ,\needs_delay.shift_register[1][5]_i_1_n_0 ,\needs_delay.shift_register[1][4]_i_1_n_0 ,\needs_delay.shift_register[1][3]_i_1_n_0 ,\needs_delay.shift_register[1][2]_i_1_n_0 ,\needs_delay.shift_register[1][1]_i_1_n_0 ,\needs_delay.shift_register[1][0]_i_1_n_0 }), + .E(E), + .aclk(aclk), + .da(da), + .sclr(sclr)); +endmodule + +(* ORIG_REF_NAME = "mult" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_mult + (c, + E, + aclk, + sclr, + s, + \core_control_regs[9] ); + output [25:0]c; + input [0:0]E; + input aclk; + input sclr; + input [8:0]s; + input [16:0]\core_control_regs[9] ; + + wire [0:0]E; + wire aclk; + wire [25:0]c; + wire [16:0]\core_control_regs[9] ; + wire [8:0]s; + wire sclr; + + Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized0 \reg + (.E(E), + .aclk(aclk), + .c(c), + .\core_control_regs[9] (\core_control_regs[9] ), + .s(s), + .sclr(sclr)); +endmodule + +(* ORIG_REF_NAME = "radd_sub_sclr" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr + (s, + Q, + sclr, + E, + aclk, + p_0_in); + output [8:0]s; + input [14:0]Q; + input sclr; + input [0:0]E; + input aclk; + input [0:0]p_0_in; + + wire [0:0]E; + wire [14:0]Q; + wire aclk; + wire [0:0]p_0_in; + wire [8:0]s; + wire sclr; + + Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no_5 \use_fabric.adder + (.E(E), + .Q(Q), + .aclk(aclk), + .p_0_in(p_0_in), + .s(s), + .sclr(sclr)); +endmodule + +(* ORIG_REF_NAME = "radd_sub_sclr" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_4 + (s, + p_0_in, + Q, + sclr, + E, + aclk); + output [8:0]s; + output [0:0]p_0_in; + input [15:0]Q; + input sclr; + input [0:0]E; + input aclk; + + wire [0:0]E; + wire [15:0]Q; + wire aclk; + wire [0:0]p_0_in; + wire [8:0]s; + wire sclr; + + Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no \use_fabric.adder + (.E(E), + .Q(Q), + .aclk(aclk), + .p_0_in(p_0_in), + .s(s), + .sclr(sclr)); +endmodule + +(* ORIG_REF_NAME = "radd_sub_sclr" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr__parameterized0 + (S, + s, + a, + D, + \needs_delay.shift_register_reg[1][10] , + \needs_delay.shift_register_reg[1][3] , + DI, + \core_control_regs[6] , + p, + CO, + \needs_delay.shift_register_reg[5][7] , + sclr, + E, + aclk, + y_intb); + output [0:0]S; + output [8:0]s; + output [0:0]a; + output [2:0]D; + output [2:0]\needs_delay.shift_register_reg[1][10] ; + output \needs_delay.shift_register_reg[1][3] ; + output [0:0]DI; + input [0:0]\core_control_regs[6] ; + input [8:0]p; + input [0:0]CO; + input [0:0]\needs_delay.shift_register_reg[5][7] ; + input sclr; + input [0:0]E; + input aclk; + input [7:0]y_intb; + + wire [0:0]CO; + wire [2:0]D; + wire [0:0]DI; + wire [0:0]E; + wire [0:0]S; + wire [0:0]a; + wire aclk; + wire [0:0]\core_control_regs[6] ; + wire [2:0]\needs_delay.shift_register_reg[1][10] ; + wire \needs_delay.shift_register_reg[1][3] ; + wire [0:0]\needs_delay.shift_register_reg[5][7] ; + wire [8:0]p; + wire [8:0]s; + wire sclr; + wire [7:0]y_intb; + + Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no__parameterized0 \use_fabric.adder + (.CO(CO), + .D(D), + .DI(DI), + .E(E), + .S(S), + .a(a), + .aclk(aclk), + .\core_control_regs[6] (\core_control_regs[6] ), + .\needs_delay.shift_register_reg[1][10] (\needs_delay.shift_register_reg[1][10] ), + .\needs_delay.shift_register_reg[1][3] (\needs_delay.shift_register_reg[1][3] ), + .\needs_delay.shift_register_reg[5][7] (\needs_delay.shift_register_reg[5][7] ), + .p(p), + .s(s), + .sclr(sclr), + .y_intb(y_intb)); +endmodule + +(* ORIG_REF_NAME = "radd_sub_sclr" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr__parameterized1 + (out, + sclr, + E, + D, + aclk); + output [10:0]out; + input sclr; + input [0:0]E; + input [10:0]D; + input aclk; + + wire [10:0]D; + wire [0:0]E; + wire aclk; + wire [10:0]out; + wire sclr; + + Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no__parameterized1 \use_fabric.adder + (.D(D), + .E(E), + .aclk(aclk), + .out(out), + .sclr(sclr)); +endmodule + +(* ORIG_REF_NAME = "radd_sub_sclr" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr__parameterized2 + (out, + sclr, + E, + D, + aclk); + output [10:0]out; + input sclr; + input [0:0]E; + input [10:0]D; + input aclk; + + wire [10:0]D; + wire [0:0]E; + wire aclk; + wire [10:0]out; + wire sclr; + + Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no__parameterized2 \use_fabric.adder + (.D(D), + .E(E), + .aclk(aclk), + .out(out), + .sclr(sclr)); +endmodule + +(* ORIG_REF_NAME = "radd_sub_sclr" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr__parameterized3 + (SR, + s, + resetn_out, + E, + aclk, + \core_control_regs[6] , + \needs_delay.shift_register_reg[1][8] , + a, + DI, + S); + output [0:0]SR; + output [9:0]s; + input resetn_out; + input [0:0]E; + input aclk; + input [8:0]\core_control_regs[6] ; + input [8:0]\needs_delay.shift_register_reg[1][8] ; + input [0:0]a; + input [0:0]DI; + input [0:0]S; + + wire [0:0]DI; + wire [0:0]E; + wire [0:0]S; + wire [0:0]SR; + wire [0:0]a; + wire aclk; + wire [8:0]\core_control_regs[6] ; + wire [8:0]\needs_delay.shift_register_reg[1][8] ; + wire resetn_out; + wire [9:0]s; + + Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no__parameterized3 \use_fabric.adder + (.DI(DI), + .E(E), + .S(S), + .a(a), + .aclk(aclk), + .\core_control_regs[6] (\core_control_regs[6] ), + .\needs_delay.shift_register_reg[1][8] (\needs_delay.shift_register_reg[1][8] ), + .resetn_out(resetn_out), + .s(s), + .sclr(SR)); +endmodule + +(* ORIG_REF_NAME = "radd_sub_sclr_no" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no + (s, + p_0_in, + Q, + sclr, + E, + aclk); + output [8:0]s; + output [0:0]p_0_in; + input [15:0]Q; + input sclr; + input [0:0]E; + input aclk; + + wire [0:0]E; + wire [15:0]Q; + wire aclk; + (* RTL_KEEP = "true" *) (* USE_DSP48 = "no" *) wire [8:0]out_s; + wire [0:0]p_0_in; + wire sclr; + + assign s[8:0] = out_s; + Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr \reg + (.E(E), + .Q(Q), + .aclk(aclk), + .out_s(out_s), + .p_0_in(p_0_in), + .sclr(sclr)); +endmodule + +(* ORIG_REF_NAME = "radd_sub_sclr_no" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no_5 + (s, + Q, + sclr, + E, + aclk, + p_0_in); + output [8:0]s; + input [14:0]Q; + input sclr; + input [0:0]E; + input aclk; + input [0:0]p_0_in; + + wire [0:0]E; + wire [14:0]Q; + wire aclk; + (* RTL_KEEP = "true" *) (* USE_DSP48 = "no" *) wire [8:0]out_s; + wire [0:0]p_0_in; + wire sclr; + + assign s[8:0] = out_s; + Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr_6 \reg + (.E(E), + .Q(Q), + .aclk(aclk), + .out_s(out_s), + .p_0_in(p_0_in), + .sclr(sclr)); +endmodule + +(* ORIG_REF_NAME = "radd_sub_sclr_no" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no__parameterized0 + (S, + a, + s, + D, + \needs_delay.shift_register_reg[1][10] , + \needs_delay.shift_register_reg[1][3] , + DI, + \core_control_regs[6] , + p, + CO, + \needs_delay.shift_register_reg[5][7] , + sclr, + E, + aclk, + y_intb); + output [0:0]S; + output [0:0]a; + output [8:0]s; + output [2:0]D; + output [2:0]\needs_delay.shift_register_reg[1][10] ; + output \needs_delay.shift_register_reg[1][3] ; + output [0:0]DI; + input [0:0]\core_control_regs[6] ; + input [8:0]p; + input [0:0]CO; + input [0:0]\needs_delay.shift_register_reg[5][7] ; + input sclr; + input [0:0]E; + input aclk; + input [7:0]y_intb; + + wire [0:0]CO; + wire [2:0]D; + wire [0:0]DI; + wire [0:0]E; + wire [0:0]S; + wire [0:0]a; + wire aclk; + wire [0:0]\core_control_regs[6] ; + wire \needs_delay.shift_register[1][3]_i_2_n_0 ; + wire \needs_delay.shift_register[1][3]_i_3_n_0 ; + wire \needs_delay.shift_register[1][3]_i_4_n_0 ; + wire \needs_delay.shift_register[1][7]_i_2_n_0 ; + wire \needs_delay.shift_register[1][7]_i_3_n_0 ; + wire \needs_delay.shift_register[1][7]_i_4_n_0 ; + wire \needs_delay.shift_register[1][7]_i_5_n_0 ; + wire \needs_delay.shift_register[1][9]_i_2_n_0 ; + wire [2:0]\needs_delay.shift_register_reg[1][10] ; + wire \needs_delay.shift_register_reg[1][3] ; + wire \needs_delay.shift_register_reg[1][3]_i_1_n_0 ; + wire \needs_delay.shift_register_reg[1][3]_i_1_n_1 ; + wire \needs_delay.shift_register_reg[1][3]_i_1_n_2 ; + wire \needs_delay.shift_register_reg[1][3]_i_1_n_3 ; + wire \needs_delay.shift_register_reg[1][7]_i_1_n_0 ; + wire \needs_delay.shift_register_reg[1][7]_i_1_n_1 ; + wire \needs_delay.shift_register_reg[1][7]_i_1_n_2 ; + wire \needs_delay.shift_register_reg[1][7]_i_1_n_3 ; + wire \needs_delay.shift_register_reg[1][9]_i_1_n_3 ; + wire [0:0]\needs_delay.shift_register_reg[5][7] ; + (* RTL_KEEP = "true" *) (* USE_DSP48 = "no" *) wire [9:0]out_s; + wire [8:0]p; + wire [9:0]plusOp; + wire reg_n_0; + wire reg_n_1; + wire sclr; + wire [7:0]y_intb; + wire [3:1]\NLW_needs_delay.shift_register_reg[1][9]_i_1_CO_UNCONNECTED ; + wire [3:2]\NLW_needs_delay.shift_register_reg[1][9]_i_1_O_UNCONNECTED ; + + assign s[8:0] = out_s[8:0]; + LUT1 #( + .INIT(2'h1)) + \needs_delay.shift_register[1][10]_i_2 + (.I0(out_s[9]), + .O(DI)); + LUT2 #( + .INIT(4'h6)) + \needs_delay.shift_register[1][10]_i_3__1 + (.I0(out_s[9]), + .I1(\core_control_regs[6] ), + .O(S)); + LUT2 #( + .INIT(4'h6)) + \needs_delay.shift_register[1][3]_i_2 + (.I0(p[3]), + .I1(y_intb[3]), + .O(\needs_delay.shift_register[1][3]_i_2_n_0 )); + LUT2 #( + .INIT(4'h6)) + \needs_delay.shift_register[1][3]_i_3 + (.I0(p[2]), + .I1(y_intb[2]), + .O(\needs_delay.shift_register[1][3]_i_3_n_0 )); + LUT2 #( + .INIT(4'h6)) + \needs_delay.shift_register[1][3]_i_4 + (.I0(p[1]), + .I1(y_intb[1]), + .O(\needs_delay.shift_register[1][3]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \needs_delay.shift_register[1][3]_i_5__4 + (.I0(out_s[0]), + .O(a)); + LUT2 #( + .INIT(4'h6)) + \needs_delay.shift_register[1][7]_i_2 + (.I0(p[7]), + .I1(y_intb[7]), + .O(\needs_delay.shift_register[1][7]_i_2_n_0 )); + LUT2 #( + .INIT(4'h6)) + \needs_delay.shift_register[1][7]_i_3 + (.I0(p[6]), + .I1(y_intb[6]), + .O(\needs_delay.shift_register[1][7]_i_3_n_0 )); + LUT2 #( + .INIT(4'h6)) + \needs_delay.shift_register[1][7]_i_4 + (.I0(p[5]), + .I1(y_intb[5]), + .O(\needs_delay.shift_register[1][7]_i_4_n_0 )); + LUT2 #( + .INIT(4'h6)) + \needs_delay.shift_register[1][7]_i_5 + (.I0(p[4]), + .I1(y_intb[4]), + .O(\needs_delay.shift_register[1][7]_i_5_n_0 )); + LUT1 #( + .INIT(2'h1)) + \needs_delay.shift_register[1][9]_i_2 + (.I0(p[8]), + .O(\needs_delay.shift_register[1][9]_i_2_n_0 )); + CARRY4 \needs_delay.shift_register_reg[1][3]_i_1 + (.CI(1'b0), + .CO({\needs_delay.shift_register_reg[1][3]_i_1_n_0 ,\needs_delay.shift_register_reg[1][3]_i_1_n_1 ,\needs_delay.shift_register_reg[1][3]_i_1_n_2 ,\needs_delay.shift_register_reg[1][3]_i_1_n_3 }), + .CYINIT(y_intb[0]), + .DI(p[3:0]), + .O(plusOp[3:0]), + .S({\needs_delay.shift_register[1][3]_i_2_n_0 ,\needs_delay.shift_register[1][3]_i_3_n_0 ,\needs_delay.shift_register[1][3]_i_4_n_0 ,reg_n_1})); + CARRY4 \needs_delay.shift_register_reg[1][7]_i_1 + (.CI(\needs_delay.shift_register_reg[1][3]_i_1_n_0 ), + .CO({\needs_delay.shift_register_reg[1][7]_i_1_n_0 ,\needs_delay.shift_register_reg[1][7]_i_1_n_1 ,\needs_delay.shift_register_reg[1][7]_i_1_n_2 ,\needs_delay.shift_register_reg[1][7]_i_1_n_3 }), + .CYINIT(1'b0), + .DI(p[7:4]), + .O(plusOp[7:4]), + .S({\needs_delay.shift_register[1][7]_i_2_n_0 ,\needs_delay.shift_register[1][7]_i_3_n_0 ,\needs_delay.shift_register[1][7]_i_4_n_0 ,\needs_delay.shift_register[1][7]_i_5_n_0 })); + CARRY4 \needs_delay.shift_register_reg[1][9]_i_1 + (.CI(\needs_delay.shift_register_reg[1][7]_i_1_n_0 ), + .CO({\NLW_needs_delay.shift_register_reg[1][9]_i_1_CO_UNCONNECTED [3:1],\needs_delay.shift_register_reg[1][9]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,\needs_delay.shift_register[1][9]_i_2_n_0 }), + .O({\NLW_needs_delay.shift_register_reg[1][9]_i_1_O_UNCONNECTED [3:2],plusOp[9:8]}), + .S({1'b0,1'b0,1'b1,reg_n_0})); + Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized1 \reg + (.CO(CO), + .D(D), + .E(E), + .Q(out_s), + .a({reg_n_0,reg_n_1}), + .aclk(aclk), + .\needs_delay.shift_register_reg[1][10] (\needs_delay.shift_register_reg[1][10] ), + .\needs_delay.shift_register_reg[1][3]_0 (\needs_delay.shift_register_reg[1][3] ), + .\needs_delay.shift_register_reg[5][7] (\needs_delay.shift_register_reg[5][7] ), + .out({out_s[9:8],out_s[0]}), + .p({p[8],p[0]}), + .plusOp(plusOp), + .sclr(sclr)); +endmodule + +(* ORIG_REF_NAME = "radd_sub_sclr_no" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no__parameterized1 + (out, + sclr, + E, + D, + aclk); + output [10:0]out; + input sclr; + input [0:0]E; + input [10:0]D; + input aclk; + + wire [10:0]D; + wire [0:0]E; + wire aclk; + (* RTL_KEEP = "true" *) (* USE_DSP48 = "no" *) wire [10:0]out_s; + wire sclr; + + assign out[10:0] = out_s; + Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized2 \reg + (.D(D), + .E(E), + .Q(out_s), + .aclk(aclk), + .sclr(sclr)); +endmodule + +(* ORIG_REF_NAME = "radd_sub_sclr_no" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no__parameterized2 + (out, + sclr, + E, + D, + aclk); + output [10:0]out; + input sclr; + input [0:0]E; + input [10:0]D; + input aclk; + + wire [10:0]D; + wire [0:0]E; + wire aclk; + (* RTL_KEEP = "true" *) (* USE_DSP48 = "no" *) wire [10:0]out_s; + wire sclr; + + assign out[10:0] = out_s; + Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized3 \reg + (.D(D), + .E(E), + .Q(out_s), + .aclk(aclk), + .sclr(sclr)); +endmodule + +(* ORIG_REF_NAME = "radd_sub_sclr_no" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no__parameterized3 + (sclr, + s, + resetn_out, + E, + aclk, + \core_control_regs[6] , + \needs_delay.shift_register_reg[1][8] , + a, + DI, + S); + output sclr; + output [9:0]s; + input resetn_out; + input [0:0]E; + input aclk; + input [8:0]\core_control_regs[6] ; + input [8:0]\needs_delay.shift_register_reg[1][8] ; + input [0:0]a; + input [0:0]DI; + input [0:0]S; + + wire [0:0]DI; + wire [0:0]E; + wire [0:0]S; + wire [0:0]a; + wire aclk; + wire [8:0]\core_control_regs[6] ; + wire \needs_delay.shift_register[1][10]_i_4_n_0 ; + wire \needs_delay.shift_register[1][3]_i_2_n_0 ; + wire \needs_delay.shift_register[1][3]_i_3_n_0 ; + wire \needs_delay.shift_register[1][3]_i_4_n_0 ; + wire \needs_delay.shift_register[1][7]_i_2_n_0 ; + wire \needs_delay.shift_register[1][7]_i_3_n_0 ; + wire \needs_delay.shift_register[1][7]_i_4_n_0 ; + wire \needs_delay.shift_register[1][7]_i_5_n_0 ; + wire \needs_delay.shift_register_reg[1][10]_i_1_n_2 ; + wire \needs_delay.shift_register_reg[1][10]_i_1_n_3 ; + wire \needs_delay.shift_register_reg[1][3]_i_1_n_0 ; + wire \needs_delay.shift_register_reg[1][3]_i_1_n_1 ; + wire \needs_delay.shift_register_reg[1][3]_i_1_n_2 ; + wire \needs_delay.shift_register_reg[1][3]_i_1_n_3 ; + wire \needs_delay.shift_register_reg[1][7]_i_1_n_0 ; + wire \needs_delay.shift_register_reg[1][7]_i_1_n_1 ; + wire \needs_delay.shift_register_reg[1][7]_i_1_n_2 ; + wire \needs_delay.shift_register_reg[1][7]_i_1_n_3 ; + wire [8:0]\needs_delay.shift_register_reg[1][8] ; + (* RTL_KEEP = "true" *) (* USE_DSP48 = "no" *) wire [10:0]out_s; + wire [10:0]plusOp; + wire resetn_out; + wire sclr; + wire [3:2]\NLW_needs_delay.shift_register_reg[1][10]_i_1_CO_UNCONNECTED ; + wire [3:3]\NLW_needs_delay.shift_register_reg[1][10]_i_1_O_UNCONNECTED ; + + assign s[9:0] = out_s[9:0]; + LUT2 #( + .INIT(4'h6)) + \needs_delay.shift_register[1][10]_i_4 + (.I0(\needs_delay.shift_register_reg[1][8] [8]), + .I1(\core_control_regs[6] [8]), + .O(\needs_delay.shift_register[1][10]_i_4_n_0 )); + LUT2 #( + .INIT(4'h6)) + \needs_delay.shift_register[1][3]_i_2 + (.I0(\needs_delay.shift_register_reg[1][8] [3]), + .I1(\core_control_regs[6] [3]), + .O(\needs_delay.shift_register[1][3]_i_2_n_0 )); + LUT2 #( + .INIT(4'h6)) + \needs_delay.shift_register[1][3]_i_3 + (.I0(\needs_delay.shift_register_reg[1][8] [2]), + .I1(\core_control_regs[6] [2]), + .O(\needs_delay.shift_register[1][3]_i_3_n_0 )); + LUT2 #( + .INIT(4'h6)) + \needs_delay.shift_register[1][3]_i_4 + (.I0(\needs_delay.shift_register_reg[1][8] [1]), + .I1(\core_control_regs[6] [1]), + .O(\needs_delay.shift_register[1][3]_i_4_n_0 )); + LUT2 #( + .INIT(4'h6)) + \needs_delay.shift_register[1][7]_i_2 + (.I0(\needs_delay.shift_register_reg[1][8] [7]), + .I1(\core_control_regs[6] [7]), + .O(\needs_delay.shift_register[1][7]_i_2_n_0 )); + LUT2 #( + .INIT(4'h6)) + \needs_delay.shift_register[1][7]_i_3 + (.I0(\needs_delay.shift_register_reg[1][8] [6]), + .I1(\core_control_regs[6] [6]), + .O(\needs_delay.shift_register[1][7]_i_3_n_0 )); + LUT2 #( + .INIT(4'h6)) + \needs_delay.shift_register[1][7]_i_4 + (.I0(\needs_delay.shift_register_reg[1][8] [5]), + .I1(\core_control_regs[6] [5]), + .O(\needs_delay.shift_register[1][7]_i_4_n_0 )); + LUT2 #( + .INIT(4'h6)) + \needs_delay.shift_register[1][7]_i_5 + (.I0(\needs_delay.shift_register_reg[1][8] [4]), + .I1(\core_control_regs[6] [4]), + .O(\needs_delay.shift_register[1][7]_i_5_n_0 )); + CARRY4 \needs_delay.shift_register_reg[1][10]_i_1 + (.CI(\needs_delay.shift_register_reg[1][7]_i_1_n_0 ), + .CO({\NLW_needs_delay.shift_register_reg[1][10]_i_1_CO_UNCONNECTED [3:2],\needs_delay.shift_register_reg[1][10]_i_1_n_2 ,\needs_delay.shift_register_reg[1][10]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,DI,\needs_delay.shift_register_reg[1][8] [8]}), + .O({\NLW_needs_delay.shift_register_reg[1][10]_i_1_O_UNCONNECTED [3],plusOp[10:8]}), + .S({1'b0,1'b1,S,\needs_delay.shift_register[1][10]_i_4_n_0 })); + CARRY4 \needs_delay.shift_register_reg[1][3]_i_1 + (.CI(1'b0), + .CO({\needs_delay.shift_register_reg[1][3]_i_1_n_0 ,\needs_delay.shift_register_reg[1][3]_i_1_n_1 ,\needs_delay.shift_register_reg[1][3]_i_1_n_2 ,\needs_delay.shift_register_reg[1][3]_i_1_n_3 }), + .CYINIT(\core_control_regs[6] [0]), + .DI(\needs_delay.shift_register_reg[1][8] [3:0]), + .O(plusOp[3:0]), + .S({\needs_delay.shift_register[1][3]_i_2_n_0 ,\needs_delay.shift_register[1][3]_i_3_n_0 ,\needs_delay.shift_register[1][3]_i_4_n_0 ,a})); + CARRY4 \needs_delay.shift_register_reg[1][7]_i_1 + (.CI(\needs_delay.shift_register_reg[1][3]_i_1_n_0 ), + .CO({\needs_delay.shift_register_reg[1][7]_i_1_n_0 ,\needs_delay.shift_register_reg[1][7]_i_1_n_1 ,\needs_delay.shift_register_reg[1][7]_i_1_n_2 ,\needs_delay.shift_register_reg[1][7]_i_1_n_3 }), + .CYINIT(1'b0), + .DI(\needs_delay.shift_register_reg[1][8] [7:4]), + .O(plusOp[7:4]), + .S({\needs_delay.shift_register[1][7]_i_2_n_0 ,\needs_delay.shift_register[1][7]_i_3_n_0 ,\needs_delay.shift_register[1][7]_i_4_n_0 ,\needs_delay.shift_register[1][7]_i_5_n_0 })); + Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized4 \reg + (.E(E), + .Q(out_s), + .SR(sclr), + .aclk(aclk), + .plusOp(plusOp), + .resetn_out(resetn_out)); +endmodule + +(* ORIG_REF_NAME = "rgb2ycrcb_core" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_rgb2ycrcb_core + (SR, + da, + \core_control_regs[10] , + aclk, + E, + \core_control_regs[12] , + \core_control_regs[7] , + \core_control_regs[11] , + \core_control_regs[8] , + \core_control_regs[9] , + Q, + \core_control_regs[6] , + resetn_out, + \core_control_regs[0] , + \core_control_regs[1] , + \core_control_regs[2] , + \core_control_regs[3] , + \core_control_regs[4] , + \core_control_regs[5] ); + output [0:0]SR; + output [23:0]da; + input [16:0]\core_control_regs[10] ; + input aclk; + input [0:0]E; + input [16:0]\core_control_regs[12] ; + input [8:0]\core_control_regs[7] ; + input [16:0]\core_control_regs[11] ; + input [8:0]\core_control_regs[8] ; + input [16:0]\core_control_regs[9] ; + input [23:0]Q; + input [8:0]\core_control_regs[6] ; + input resetn_out; + input [7:0]\core_control_regs[0] ; + input [7:0]\core_control_regs[1] ; + input [7:0]\core_control_regs[2] ; + input [7:0]\core_control_regs[3] ; + input [7:0]\core_control_regs[4] ; + input [7:0]\core_control_regs[5] ; + + wire [0:0]E; + wire [23:0]Q; + wire [0:0]SR; + wire aclk; + wire add_aRG_bBG_G_n_0; + wire add_aRG_bBG_G_n_10; + wire add_aRG_bBG_G_n_11; + wire add_aRG_bBG_G_n_12; + wire add_aRG_bBG_G_n_13; + wire add_aRG_bBG_G_n_14; + wire add_aRG_bBG_G_n_15; + wire add_aRG_bBG_G_n_16; + wire add_aRG_bBG_G_n_17; + wire add_aRG_bBG_G_n_18; + wire [8:0]bg; + wire [10:0]by; + wire \clip.max_Cb_n_0 ; + wire \clip.max_Cb_n_1 ; + wire \clip.max_Cb_n_10 ; + wire \clip.max_Cb_n_11 ; + wire \clip.max_Cb_n_12 ; + wire \clip.max_Cb_n_13 ; + wire \clip.max_Cb_n_14 ; + wire \clip.max_Cb_n_15 ; + wire \clip.max_Cb_n_16 ; + wire \clip.max_Cb_n_17 ; + wire \clip.max_Cb_n_2 ; + wire \clip.max_Cb_n_3 ; + wire \clip.max_Cb_n_4 ; + wire \clip.max_Cb_n_5 ; + wire \clip.max_Cb_n_6 ; + wire \clip.max_Cb_n_7 ; + wire \clip.max_Cb_n_8 ; + wire \clip.max_Cb_n_9 ; + wire \clip.max_Cr_n_0 ; + wire \clip.max_Cr_n_1 ; + wire \clip.max_Cr_n_10 ; + wire \clip.max_Cr_n_11 ; + wire \clip.max_Cr_n_12 ; + wire \clip.max_Cr_n_13 ; + wire \clip.max_Cr_n_14 ; + wire \clip.max_Cr_n_15 ; + wire \clip.max_Cr_n_16 ; + wire \clip.max_Cr_n_17 ; + wire \clip.max_Cr_n_2 ; + wire \clip.max_Cr_n_3 ; + wire \clip.max_Cr_n_4 ; + wire \clip.max_Cr_n_5 ; + wire \clip.max_Cr_n_6 ; + wire \clip.max_Cr_n_7 ; + wire \clip.max_Cr_n_8 ; + wire \clip.max_Cr_n_9 ; + wire \clip.max_Y_n_0 ; + wire \clip.max_Y_n_1 ; + wire \clip.max_Y_n_10 ; + wire \clip.max_Y_n_11 ; + wire \clip.max_Y_n_12 ; + wire \clip.max_Y_n_13 ; + wire \clip.max_Y_n_14 ; + wire \clip.max_Y_n_15 ; + wire \clip.max_Y_n_16 ; + wire \clip.max_Y_n_17 ; + wire \clip.max_Y_n_2 ; + wire \clip.max_Y_n_3 ; + wire \clip.max_Y_n_4 ; + wire \clip.max_Y_n_5 ; + wire \clip.max_Y_n_6 ; + wire \clip.max_Y_n_7 ; + wire \clip.max_Y_n_8 ; + wire \clip.max_Y_n_9 ; + wire [7:0]\core_control_regs[0] ; + wire [16:0]\core_control_regs[10] ; + wire [16:0]\core_control_regs[11] ; + wire [16:0]\core_control_regs[12] ; + wire [7:0]\core_control_regs[1] ; + wire [7:0]\core_control_regs[2] ; + wire [7:0]\core_control_regs[3] ; + wire [7:0]\core_control_regs[4] ; + wire [7:0]\core_control_regs[5] ; + wire [8:0]\core_control_regs[6] ; + wire [8:0]\core_control_regs[7] ; + wire [8:0]\core_control_regs[8] ; + wire [16:0]\core_control_regs[9] ; + wire [23:0]da; + wire del_B_n_0; + wire del_B_n_1; + wire del_B_n_2; + wire del_B_n_3; + wire del_B_n_4; + wire del_B_n_5; + wire del_B_n_6; + wire del_B_n_7; + wire del_B_n_8; + wire del_R_n_0; + wire del_R_n_1; + wire del_R_n_2; + wire del_R_n_3; + wire del_R_n_4; + wire del_R_n_5; + wire del_R_n_6; + wire del_R_n_7; + wire del_R_n_8; + wire del_Y_n_0; + wire del_Y_n_1; + wire del_Y_n_10; + wire del_Y_n_11; + wire del_Y_n_12; + wire del_Y_n_13; + wire del_Y_n_14; + wire del_Y_n_15; + wire del_Y_n_16; + wire del_Y_n_17; + wire del_Y_n_18; + wire del_Y_n_19; + wire del_Y_n_2; + wire del_Y_n_3; + wire del_Y_n_4; + wire del_Y_n_5; + wire del_Y_n_6; + wire del_Y_n_7; + wire del_Y_n_8; + wire del_Y_n_9; + wire resetn_out; + wire [8:0]rg; + wire [25:0]rgm; + wire [10:0]ry; + wire [0:0]\use_fabric.adder/p_0_in ; + wire \v4_mac23.mac_cBY_n_10 ; + wire \v4_mac23.mac_cBY_n_11 ; + wire \v4_mac23.mac_cBY_n_2 ; + wire \v4_mac23.mac_cBY_n_3 ; + wire \v4_mac23.mac_cBY_n_4 ; + wire \v4_mac23.mac_cBY_n_5 ; + wire \v4_mac23.mac_cBY_n_6 ; + wire \v4_mac23.mac_cBY_n_7 ; + wire \v4_mac23.mac_cBY_n_8 ; + wire \v4_mac23.mac_cBY_n_9 ; + wire \v4_mac23.mac_cRY_n_10 ; + wire \v4_mac23.mac_cRY_n_11 ; + wire \v4_mac23.mac_cRY_n_2 ; + wire \v4_mac23.mac_cRY_n_3 ; + wire \v4_mac23.mac_cRY_n_4 ; + wire \v4_mac23.mac_cRY_n_5 ; + wire \v4_mac23.mac_cRY_n_6 ; + wire \v4_mac23.mac_cRY_n_7 ; + wire \v4_mac23.mac_cRY_n_8 ; + wire \v4_mac23.mac_cRY_n_9 ; + wire [8:0]y_int; + wire [9:0]y_int_round; + wire [24:16]y_inta_raw; + wire [7:0]y_intb; + wire [25:0]\NLW_v4_mac1.mult_aCr_p_UNCONNECTED ; + wire [11:10]\NLW_v4_mac23.mac_cBY_p_UNCONNECTED ; + wire [11:10]\NLW_v4_mac23.mac_cRY_p_UNCONNECTED ; + + Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr__parameterized0 add_aRG_bBG_G + (.CO(del_B_n_8), + .D({add_aRG_bBG_G_n_11,add_aRG_bBG_G_n_12,add_aRG_bBG_G_n_13}), + .DI(add_aRG_bBG_G_n_18), + .E(E), + .S(add_aRG_bBG_G_n_0), + .a(add_aRG_bBG_G_n_10), + .aclk(aclk), + .\core_control_regs[6] (\core_control_regs[6] [8]), + .\needs_delay.shift_register_reg[1][10] ({add_aRG_bBG_G_n_14,add_aRG_bBG_G_n_15,add_aRG_bBG_G_n_16}), + .\needs_delay.shift_register_reg[1][3] (add_aRG_bBG_G_n_17), + .\needs_delay.shift_register_reg[5][7] (del_R_n_8), + .p(y_inta_raw), + .s(y_int), + .sclr(SR), + .y_intb(y_intb)); + Arty_Z7_20_v_rgb2ycrcb_0_0_min_sat \clamp.min_Cb + (.DI({\clip.max_Cb_n_14 ,\clip.max_Cb_n_15 ,\clip.max_Cb_n_16 ,\clip.max_Cb_n_17 }), + .E(E), + .Q({\clip.max_Cb_n_1 ,\clip.max_Cb_n_2 ,\clip.max_Cb_n_3 ,\clip.max_Cb_n_4 ,\clip.max_Cb_n_5 ,\clip.max_Cb_n_6 ,\clip.max_Cb_n_7 ,\clip.max_Cb_n_8 ,\clip.max_Cb_n_9 }), + .S({\clip.max_Cb_n_10 ,\clip.max_Cb_n_11 ,\clip.max_Cb_n_12 ,\clip.max_Cb_n_13 }), + .aclk(aclk), + .\core_control_regs[3] (\core_control_regs[3] ), + .da(da[15:8]), + .\needs_delay.shift_register_reg[1][8] (\clip.max_Cb_n_0 ), + .sclr(SR)); + Arty_Z7_20_v_rgb2ycrcb_0_0_min_sat_0 \clamp.min_Cr + (.DI({\clip.max_Cr_n_14 ,\clip.max_Cr_n_15 ,\clip.max_Cr_n_16 ,\clip.max_Cr_n_17 }), + .E(E), + .Q({\clip.max_Cr_n_1 ,\clip.max_Cr_n_2 ,\clip.max_Cr_n_3 ,\clip.max_Cr_n_4 ,\clip.max_Cr_n_5 ,\clip.max_Cr_n_6 ,\clip.max_Cr_n_7 ,\clip.max_Cr_n_8 ,\clip.max_Cr_n_9 }), + .S({\clip.max_Cr_n_10 ,\clip.max_Cr_n_11 ,\clip.max_Cr_n_12 ,\clip.max_Cr_n_13 }), + .aclk(aclk), + .\core_control_regs[5] (\core_control_regs[5] ), + .da(da[23:16]), + .\needs_delay.shift_register_reg[1][8] (\clip.max_Cr_n_0 ), + .sclr(SR)); + Arty_Z7_20_v_rgb2ycrcb_0_0_min_sat_1 \clamp.min_Y + (.DI({\clip.max_Y_n_14 ,\clip.max_Y_n_15 ,\clip.max_Y_n_16 ,\clip.max_Y_n_17 }), + .E(E), + .Q({\clip.max_Y_n_1 ,\clip.max_Y_n_2 ,\clip.max_Y_n_3 ,\clip.max_Y_n_4 ,\clip.max_Y_n_5 ,\clip.max_Y_n_6 ,\clip.max_Y_n_7 ,\clip.max_Y_n_8 ,\clip.max_Y_n_9 }), + .S({\clip.max_Y_n_10 ,\clip.max_Y_n_11 ,\clip.max_Y_n_12 ,\clip.max_Y_n_13 }), + .aclk(aclk), + .\core_control_regs[1] (\core_control_regs[1] ), + .da(da[7:0]), + .\needs_delay.shift_register_reg[1][8] (\clip.max_Y_n_0 ), + .sclr(SR)); + Arty_Z7_20_v_rgb2ycrcb_0_0_max_sat \clip.max_Cb + (.DI({\clip.max_Cb_n_14 ,\clip.max_Cb_n_15 ,\clip.max_Cb_n_16 ,\clip.max_Cb_n_17 }), + .E(E), + .Q({\clip.max_Cb_n_1 ,\clip.max_Cb_n_2 ,\clip.max_Cb_n_3 ,\clip.max_Cb_n_4 ,\clip.max_Cb_n_5 ,\clip.max_Cb_n_6 ,\clip.max_Cb_n_7 ,\clip.max_Cb_n_8 ,\clip.max_Cb_n_9 }), + .S({\clip.max_Cb_n_10 ,\clip.max_Cb_n_11 ,\clip.max_Cb_n_12 ,\clip.max_Cb_n_13 }), + .aclk(aclk), + .\core_control_regs[2] (\core_control_regs[2] ), + .\core_control_regs[3] (\core_control_regs[3] ), + .\needs_delay.shift_register_reg[1][7] (\clip.max_Cb_n_0 ), + .p({\v4_mac23.mac_cBY_n_2 ,\v4_mac23.mac_cBY_n_3 ,\v4_mac23.mac_cBY_n_4 ,\v4_mac23.mac_cBY_n_5 ,\v4_mac23.mac_cBY_n_6 ,\v4_mac23.mac_cBY_n_7 ,\v4_mac23.mac_cBY_n_8 ,\v4_mac23.mac_cBY_n_9 ,\v4_mac23.mac_cBY_n_10 ,\v4_mac23.mac_cBY_n_11 }), + .sclr(SR)); + Arty_Z7_20_v_rgb2ycrcb_0_0_max_sat_2 \clip.max_Cr + (.DI({\clip.max_Cr_n_14 ,\clip.max_Cr_n_15 ,\clip.max_Cr_n_16 ,\clip.max_Cr_n_17 }), + .E(E), + .Q({\clip.max_Cr_n_1 ,\clip.max_Cr_n_2 ,\clip.max_Cr_n_3 ,\clip.max_Cr_n_4 ,\clip.max_Cr_n_5 ,\clip.max_Cr_n_6 ,\clip.max_Cr_n_7 ,\clip.max_Cr_n_8 ,\clip.max_Cr_n_9 }), + .S({\clip.max_Cr_n_10 ,\clip.max_Cr_n_11 ,\clip.max_Cr_n_12 ,\clip.max_Cr_n_13 }), + .aclk(aclk), + .\core_control_regs[4] (\core_control_regs[4] ), + .\core_control_regs[5] (\core_control_regs[5] ), + .\needs_delay.shift_register_reg[1][7] (\clip.max_Cr_n_0 ), + .p({\v4_mac23.mac_cRY_n_2 ,\v4_mac23.mac_cRY_n_3 ,\v4_mac23.mac_cRY_n_4 ,\v4_mac23.mac_cRY_n_5 ,\v4_mac23.mac_cRY_n_6 ,\v4_mac23.mac_cRY_n_7 ,\v4_mac23.mac_cRY_n_8 ,\v4_mac23.mac_cRY_n_9 ,\v4_mac23.mac_cRY_n_10 ,\v4_mac23.mac_cRY_n_11 }), + .sclr(SR)); + Arty_Z7_20_v_rgb2ycrcb_0_0_max_sat_3 \clip.max_Y + (.DI({del_Y_n_16,del_Y_n_17,del_Y_n_18,del_Y_n_19}), + .E(E), + .Q({\clip.max_Y_n_1 ,\clip.max_Y_n_2 ,\clip.max_Y_n_3 ,\clip.max_Y_n_4 ,\clip.max_Y_n_5 ,\clip.max_Y_n_6 ,\clip.max_Y_n_7 ,\clip.max_Y_n_8 ,\clip.max_Y_n_9 }), + .S({del_Y_n_12,del_Y_n_13,del_Y_n_14,del_Y_n_15}), + .aclk(aclk), + .\core_control_regs[0] (\core_control_regs[0] ), + .\core_control_regs[1] (\core_control_regs[1] ), + .\needs_delay.shift_register_reg[1][7] (\clip.max_Y_n_0 ), + .\needs_delay.shift_register_reg[1][7]_0 ({\clip.max_Y_n_10 ,\clip.max_Y_n_11 ,\clip.max_Y_n_12 ,\clip.max_Y_n_13 }), + .\needs_delay.shift_register_reg[1][7]_1 ({\clip.max_Y_n_14 ,\clip.max_Y_n_15 ,\clip.max_Y_n_16 ,\clip.max_Y_n_17 }), + .\needs_delay.shift_register_reg[3][0] (del_Y_n_9), + .\needs_delay.shift_register_reg[3][1] (del_Y_n_8), + .\needs_delay.shift_register_reg[3][2] (del_Y_n_7), + .\needs_delay.shift_register_reg[3][3] (del_Y_n_6), + .\needs_delay.shift_register_reg[3][4] (del_Y_n_5), + .\needs_delay.shift_register_reg[3][5] (del_Y_n_4), + .\needs_delay.shift_register_reg[3][6] (del_Y_n_3), + .\needs_delay.shift_register_reg[3][7] (del_Y_n_2), + .\needs_delay.shift_register_reg[3][8] (del_Y_n_10), + .\needs_delay.shift_register_reg[3][8]_0 (del_Y_n_11), + .\needs_delay.shift_register_reg[3][8]_1 (del_Y_n_1), + .\needs_delay.shift_register_reg[3][9] (del_Y_n_0), + .sclr(SR)); + Arty_Z7_20_v_rgb2ycrcb_0_0_delay__parameterized0 del_B + (.CO(del_B_n_8), + .D({del_B_n_0,del_B_n_1,del_B_n_2,del_B_n_3,del_B_n_4,del_B_n_5,del_B_n_6,del_B_n_7}), + .E(E), + .Q(Q[15:8]), + .aclk(aclk), + .\needs_delay.shift_register_reg[1][0] (add_aRG_bBG_G_n_17), + .s(y_int[7:1])); + Arty_Z7_20_v_rgb2ycrcb_0_0_delay del_G + (.E(E), + .Q(Q[7:0]), + .aclk(aclk), + .y_intb(y_intb)); + Arty_Z7_20_v_rgb2ycrcb_0_0_delay__parameterized1 del_R + (.D({del_R_n_0,del_R_n_1,del_R_n_2,del_R_n_3,del_R_n_4,del_R_n_5,del_R_n_6,del_R_n_7}), + .E(E), + .Q(Q[23:16]), + .aclk(aclk), + .\needs_delay.shift_register_reg[1][0] (add_aRG_bBG_G_n_17), + .\needs_delay.shift_register_reg[1][10] (del_R_n_8), + .s(y_int[7:1])); + Arty_Z7_20_v_rgb2ycrcb_0_0_delay__parameterized2 del_Y + (.DI({del_Y_n_16,del_Y_n_17,del_Y_n_18,del_Y_n_19}), + .E(E), + .S({del_Y_n_12,del_Y_n_13,del_Y_n_14,del_Y_n_15}), + .aclk(aclk), + .\core_control_regs[0] (\core_control_regs[0] ), + .\needs_delay.shift_register_reg[1][0] (del_Y_n_9), + .\needs_delay.shift_register_reg[1][1] (del_Y_n_8), + .\needs_delay.shift_register_reg[1][2] (del_Y_n_7), + .\needs_delay.shift_register_reg[1][3] (del_Y_n_6), + .\needs_delay.shift_register_reg[1][4] (del_Y_n_5), + .\needs_delay.shift_register_reg[1][5] (del_Y_n_4), + .\needs_delay.shift_register_reg[1][6] (del_Y_n_3), + .\needs_delay.shift_register_reg[1][7] (del_Y_n_2), + .\needs_delay.shift_register_reg[1][8] (del_Y_n_1), + .\needs_delay.shift_register_reg[1][9] (del_Y_n_0), + .\needs_delay.shift_register_reg[1][9]_0 (del_Y_n_10), + .\needs_delay.shift_register_reg[1][9]_1 (del_Y_n_11), + .s(y_int_round)); + Arty_Z7_20_v_rgb2ycrcb_0_0_mult mult_aRG + (.E(E), + .aclk(aclk), + .c(rgm), + .\core_control_regs[9] (\core_control_regs[9] ), + .s(rg), + .sclr(SR)); + Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr sub_BG + (.E(E), + .Q(Q[15:1]), + .aclk(aclk), + .p_0_in(\use_fabric.adder/p_0_in ), + .s(bg), + .sclr(SR)); + Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr__parameterized1 sub_BY + (.D({add_aRG_bBG_G_n_11,add_aRG_bBG_G_n_12,add_aRG_bBG_G_n_13,del_B_n_0,del_B_n_1,del_B_n_2,del_B_n_3,del_B_n_4,del_B_n_5,del_B_n_6,del_B_n_7}), + .E(E), + .aclk(aclk), + .out(by), + .sclr(SR)); + Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_4 sub_RG + (.E(E), + .Q({Q[23:16],Q[7:0]}), + .aclk(aclk), + .p_0_in(\use_fabric.adder/p_0_in ), + .s(rg), + .sclr(SR)); + Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr__parameterized2 sub_RY + (.D({add_aRG_bBG_G_n_14,add_aRG_bBG_G_n_15,add_aRG_bBG_G_n_16,del_R_n_0,del_R_n_1,del_R_n_2,del_R_n_3,del_R_n_4,del_R_n_5,del_R_n_6,del_R_n_7}), + .E(E), + .aclk(aclk), + .out(ry), + .sclr(SR)); + (* CREG = "0" *) + (* HAS_C = "1" *) + (* IWIDTHA = "9" *) + (* IWIDTHB = "17" *) + (* OWIDTH = "26" *) + (* ROUND_MODE = "0" *) + (* USE_DSP48 = "yes" *) + (* downgradeipidentifiedwarnings = "yes" *) + (* mult_style = "pipe_block" *) + (* register_balancing = "yes" *) + Arty_Z7_20_v_rgb2ycrcb_0_0_mac \v4_mac1.mult_aCr + (.a(bg), + .b(\core_control_regs[10] ), + .c(rgm), + .ce(E), + .clk(aclk), + .p({\NLW_v4_mac1.mult_aCr_p_UNCONNECTED [25],y_inta_raw,\NLW_v4_mac1.mult_aCr_p_UNCONNECTED [15:0]}), + .sclr(SR)); + (* CREG = "0" *) + (* HAS_C = "1" *) + (* IWIDTHA = "11" *) + (* IWIDTHB = "17" *) + (* OWIDTH = "12" *) + (* ROUND_MODE = "0" *) + (* USE_DSP48 = "yes" *) + (* downgradeipidentifiedwarnings = "yes" *) + (* mult_style = "pipe_block" *) + (* register_balancing = "yes" *) + Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized0 \v4_mac23.mac_cBY + (.a(by), + .b(\core_control_regs[12] ), + .c({\core_control_regs[7] [8],\core_control_regs[7] [8],\core_control_regs[7] [8],\core_control_regs[7] }), + .ce(E), + .clk(aclk), + .p({\NLW_v4_mac23.mac_cBY_p_UNCONNECTED [11:10],\v4_mac23.mac_cBY_n_2 ,\v4_mac23.mac_cBY_n_3 ,\v4_mac23.mac_cBY_n_4 ,\v4_mac23.mac_cBY_n_5 ,\v4_mac23.mac_cBY_n_6 ,\v4_mac23.mac_cBY_n_7 ,\v4_mac23.mac_cBY_n_8 ,\v4_mac23.mac_cBY_n_9 ,\v4_mac23.mac_cBY_n_10 ,\v4_mac23.mac_cBY_n_11 }), + .sclr(SR)); + (* CREG = "0" *) + (* HAS_C = "1" *) + (* IWIDTHA = "11" *) + (* IWIDTHB = "17" *) + (* OWIDTH = "12" *) + (* ROUND_MODE = "0" *) + (* USE_DSP48 = "yes" *) + (* downgradeipidentifiedwarnings = "yes" *) + (* mult_style = "pipe_block" *) + (* register_balancing = "yes" *) + Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized1 \v4_mac23.mac_cRY + (.a(ry), + .b(\core_control_regs[11] ), + .c({\core_control_regs[8] [8],\core_control_regs[8] [8],\core_control_regs[8] [8],\core_control_regs[8] }), + .ce(E), + .clk(aclk), + .p({\NLW_v4_mac23.mac_cRY_p_UNCONNECTED [11:10],\v4_mac23.mac_cRY_n_2 ,\v4_mac23.mac_cRY_n_3 ,\v4_mac23.mac_cRY_n_4 ,\v4_mac23.mac_cRY_n_5 ,\v4_mac23.mac_cRY_n_6 ,\v4_mac23.mac_cRY_n_7 ,\v4_mac23.mac_cRY_n_8 ,\v4_mac23.mac_cRY_n_9 ,\v4_mac23.mac_cRY_n_10 ,\v4_mac23.mac_cRY_n_11 }), + .sclr(SR)); + Arty_Z7_20_v_rgb2ycrcb_0_0_round \y_needs_round.round_Y + (.DI(add_aRG_bBG_G_n_18), + .E(E), + .S(add_aRG_bBG_G_n_0), + .a(add_aRG_bBG_G_n_10), + .aclk(aclk), + .\core_control_regs[6] (\core_control_regs[6] ), + .\needs_delay.shift_register_reg[1][8] (y_int), + .resetn_out(resetn_out), + .s(y_int_round), + .sclr(SR)); +endmodule + +(* ORIG_REF_NAME = "rgb2ycrcb_top" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_rgb2ycrcb_top + (\needs_delay.shift_register_reg[1][0] , + s_axis_video_tready, + eol_late_i_reg, + sof_early_i_reg, + sof_early_i_reg_0, + intc_if, + Q, + reg_update, + m_axis_video_tvalid, + \core_control_regs[10] , + aclk, + \core_control_regs[12] , + \core_control_regs[7] , + \core_control_regs[11] , + \core_control_regs[8] , + \core_control_regs[9] , + resetn_out, + \genr_control_regs[0] , + aclken, + m_axis_video_tready, + \core_control_regs[6] , + \time_control_regs[0] , + \core_control_regs[0] , + \core_control_regs[1] , + \core_control_regs[2] , + \core_control_regs[3] , + \core_control_regs[4] , + \core_control_regs[5] , + da, + core_d_out, + s_axis_video_tvalid); + output \needs_delay.shift_register_reg[1][0] ; + output s_axis_video_tready; + output eol_late_i_reg; + output sof_early_i_reg; + output sof_early_i_reg_0; + output [4:0]intc_if; + output [25:0]Q; + output reg_update; + output m_axis_video_tvalid; + input [16:0]\core_control_regs[10] ; + input aclk; + input [16:0]\core_control_regs[12] ; + input [8:0]\core_control_regs[7] ; + input [16:0]\core_control_regs[11] ; + input [8:0]\core_control_regs[8] ; + input [16:0]\core_control_regs[9] ; + input resetn_out; + input [2:0]\genr_control_regs[0] ; + input aclken; + input m_axis_video_tready; + input [8:0]\core_control_regs[6] ; + input [25:0]\time_control_regs[0] ; + input [7:0]\core_control_regs[0] ; + input [7:0]\core_control_regs[1] ; + input [7:0]\core_control_regs[2] ; + input [7:0]\core_control_regs[3] ; + input [7:0]\core_control_regs[4] ; + input [7:0]\core_control_regs[5] ; + input [25:0]da; + input core_d_out; + input s_axis_video_tvalid; + + wire [25:0]Q; + wire \UOSD_AXIS_SYNC_FIFO/wen ; + wire aclk; + wire aclken; + wire axi_control_n_13; + wire axi_control_n_16; + wire axi_control_n_17; + wire axi_in_fifo_n_10; + wire axi_in_fifo_n_11; + wire axi_in_fifo_n_12; + wire axi_in_fifo_n_13; + wire axi_in_fifo_n_14; + wire axi_in_fifo_n_15; + wire axi_in_fifo_n_16; + wire axi_in_fifo_n_17; + wire axi_in_fifo_n_18; + wire axi_in_fifo_n_19; + wire axi_in_fifo_n_2; + wire axi_in_fifo_n_20; + wire axi_in_fifo_n_21; + wire axi_in_fifo_n_22; + wire axi_in_fifo_n_23; + wire axi_in_fifo_n_24; + wire axi_in_fifo_n_25; + wire axi_in_fifo_n_26; + wire axi_in_fifo_n_27; + wire axi_in_fifo_n_28; + wire axi_in_fifo_n_29; + wire axi_in_fifo_n_3; + wire axi_in_fifo_n_30; + wire axi_in_fifo_n_7; + wire axi_in_fifo_n_8; + wire axi_in_fifo_n_9; + wire axi_out_fifo_n_0; + wire axi_out_fifo_n_1; + wire axi_out_fifo_n_2; + wire axi_out_fifo_n_3; + wire [7:0]\core_control_regs[0] ; + wire [16:0]\core_control_regs[10] ; + wire [16:0]\core_control_regs[11] ; + wire [16:0]\core_control_regs[12] ; + wire [7:0]\core_control_regs[1] ; + wire [7:0]\core_control_regs[2] ; + wire [7:0]\core_control_regs[3] ; + wire [7:0]\core_control_regs[4] ; + wire [7:0]\core_control_regs[5] ; + wire [8:0]\core_control_regs[6] ; + wire [8:0]\core_control_regs[7] ; + wire [8:0]\core_control_regs[8] ; + wire [16:0]\core_control_regs[9] ; + wire core_d_out; + wire [25:0]da; + wire eol_late_i_reg; + wire fifo_wr_i; + wire [2:0]\genr_control_regs[0] ; + wire [4:0]intc_if; + wire intcore_n_1; + wire intcore_n_10; + wire intcore_n_11; + wire intcore_n_12; + wire intcore_n_13; + wire intcore_n_14; + wire intcore_n_15; + wire intcore_n_16; + wire intcore_n_17; + wire intcore_n_18; + wire intcore_n_19; + wire intcore_n_2; + wire intcore_n_20; + wire intcore_n_21; + wire intcore_n_22; + wire intcore_n_23; + wire intcore_n_24; + wire intcore_n_3; + wire intcore_n_4; + wire intcore_n_5; + wire intcore_n_6; + wire intcore_n_7; + wire intcore_n_8; + wire intcore_n_9; + wire ltOp; + wire m_axis_video_tready; + wire m_axis_video_tvalid; + wire master_en; + wire \needs_delay.shift_register_reg[1][0] ; + wire out_fifo_eol; + wire out_fifo_sof; + wire reg_update; + wire resetn_out; + wire s_axis_video_tready; + wire s_axis_video_tvalid; + wire sclr; + wire sof_early_i_reg; + wire sof_early_i_reg_0; + wire [25:0]\time_control_regs[0] ; + wire [23:0]vid_data_in_r; + wire vid_empty; + wire vid_eol_in; + wire vid_sof_in; + + Arty_Z7_20_v_rgb2ycrcb_0_0_axi4s_control axi_control + (.CO(ltOp), + .E(\needs_delay.shift_register_reg[1][0] ), + .SR(sclr), + .aclk(aclk), + .aclken(aclken), + .\col_cnt_reg[12]_0 (axi_control_n_17), + .\col_cnt_reg[1]_0 (axi_control_n_13), + .core_d_out(core_d_out), + .da({out_fifo_sof,out_fifo_eol}), + .empty_match_reg(axi_in_fifo_n_3), + .eol_late_i_reg_0(eol_late_i_reg), + .fifo_wr_i(fifo_wr_i), + .full_int_reg(axi_out_fifo_n_0), + .\genr_control_regs[0] ({\genr_control_regs[0] [2],\genr_control_regs[0] [0]}), + .in_fifo_reset_reg_0(axi_control_n_16), + .intc_if(intc_if), + .master_en(master_en), + .\read_ptr_int_reg[1] (axi_out_fifo_n_3), + .resetn_out(resetn_out), + .sof_early_i_reg_0(sof_early_i_reg), + .sof_early_i_reg_1(sof_early_i_reg_0), + .t_qb({vid_sof_in,vid_eol_in}), + .\time_control_regs[0] (\time_control_regs[0] ), + .vid_empty(vid_empty), + .wen(\UOSD_AXIS_SYNC_FIFO/wen ), + .\word_count_reg[4] (axi_in_fifo_n_2), + .\write_ptr_int_reg[2] (axi_out_fifo_n_1), + .\write_ptr_int_reg[2]_0 (axi_out_fifo_n_2)); + Arty_Z7_20_v_rgb2ycrcb_0_0_axis_input_buffer axi_in_fifo + (.Q({vid_sof_in,vid_eol_in,axi_in_fifo_n_7,axi_in_fifo_n_8,axi_in_fifo_n_9,axi_in_fifo_n_10,axi_in_fifo_n_11,axi_in_fifo_n_12,axi_in_fifo_n_13,axi_in_fifo_n_14,axi_in_fifo_n_15,axi_in_fifo_n_16,axi_in_fifo_n_17,axi_in_fifo_n_18,axi_in_fifo_n_19,axi_in_fifo_n_20,axi_in_fifo_n_21,axi_in_fifo_n_22,axi_in_fifo_n_23,axi_in_fifo_n_24,axi_in_fifo_n_25,axi_in_fifo_n_26,axi_in_fifo_n_27,axi_in_fifo_n_28,axi_in_fifo_n_29,axi_in_fifo_n_30}), + .SR(sclr), + .aclk(aclk), + .aclken(aclken), + .\col_cnt_reg[12] (axi_in_fifo_n_3), + .da(da), + .empty_match_reg(axi_in_fifo_n_2), + .fifo_rd_i_reg(axi_control_n_16), + .\genr_control_regs[0] (\genr_control_regs[0] [1:0]), + .master_en(master_en), + .reg_update(reg_update), + .resetn_out(resetn_out), + .s_axis_video_tready(s_axis_video_tready), + .s_axis_video_tvalid(s_axis_video_tvalid), + .vid_empty(vid_empty)); + Arty_Z7_20_v_rgb2ycrcb_0_0_axis_output_buffer axi_out_fifo + (.CO(ltOp), + .Q(Q), + .SR(sclr), + .aclk(aclk), + .aclken(aclken), + .aclken_0(axi_control_n_13), + .\col_cnt_reg[12] (axi_out_fifo_n_1), + .\col_cnt_reg[12]_0 (axi_out_fifo_n_2), + .\col_cnt_reg[12]_1 (axi_out_fifo_n_3), + .core_d_out(core_d_out), + .da({out_fifo_sof,out_fifo_eol,intcore_n_1,intcore_n_2,intcore_n_3,intcore_n_4,intcore_n_5,intcore_n_6,intcore_n_7,intcore_n_8,intcore_n_9,intcore_n_10,intcore_n_11,intcore_n_12,intcore_n_13,intcore_n_14,intcore_n_15,intcore_n_16,intcore_n_17,intcore_n_18,intcore_n_19,intcore_n_20,intcore_n_21,intcore_n_22,intcore_n_23,intcore_n_24}), + .empty_match_reg(axi_control_n_17), + .empty_match_reg_0(axi_in_fifo_n_3), + .eol_late_i_reg(eol_late_i_reg), + .fifo_wr_i(fifo_wr_i), + .\genr_control_regs[0] (\genr_control_regs[0] [0]), + .m_axis_video_tready(m_axis_video_tready), + .m_axis_video_tvalid(m_axis_video_tvalid), + .wen(\UOSD_AXIS_SYNC_FIFO/wen ), + .\write_ptr_int_reg[0] (axi_out_fifo_n_0)); + Arty_Z7_20_v_rgb2ycrcb_0_0_rgb2ycrcb_core intcore + (.E(\needs_delay.shift_register_reg[1][0] ), + .Q(vid_data_in_r), + .SR(sclr), + .aclk(aclk), + .\core_control_regs[0] (\core_control_regs[0] ), + .\core_control_regs[10] (\core_control_regs[10] ), + .\core_control_regs[11] (\core_control_regs[11] ), + .\core_control_regs[12] (\core_control_regs[12] ), + .\core_control_regs[1] (\core_control_regs[1] ), + .\core_control_regs[2] (\core_control_regs[2] ), + .\core_control_regs[3] (\core_control_regs[3] ), + .\core_control_regs[4] (\core_control_regs[4] ), + .\core_control_regs[5] (\core_control_regs[5] ), + .\core_control_regs[6] (\core_control_regs[6] ), + .\core_control_regs[7] (\core_control_regs[7] ), + .\core_control_regs[8] (\core_control_regs[8] ), + .\core_control_regs[9] (\core_control_regs[9] ), + .da({intcore_n_1,intcore_n_2,intcore_n_3,intcore_n_4,intcore_n_5,intcore_n_6,intcore_n_7,intcore_n_8,intcore_n_9,intcore_n_10,intcore_n_11,intcore_n_12,intcore_n_13,intcore_n_14,intcore_n_15,intcore_n_16,intcore_n_17,intcore_n_18,intcore_n_19,intcore_n_20,intcore_n_21,intcore_n_22,intcore_n_23,intcore_n_24}), + .resetn_out(resetn_out)); + FDRE #( + .INIT(1'b0)) + \vid_data_in_r_reg[0] + (.C(aclk), + .CE(\needs_delay.shift_register_reg[1][0] ), + .D(axi_in_fifo_n_30), + .Q(vid_data_in_r[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \vid_data_in_r_reg[10] + (.C(aclk), + .CE(\needs_delay.shift_register_reg[1][0] ), + .D(axi_in_fifo_n_20), + .Q(vid_data_in_r[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \vid_data_in_r_reg[11] + (.C(aclk), + .CE(\needs_delay.shift_register_reg[1][0] ), + .D(axi_in_fifo_n_19), + .Q(vid_data_in_r[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \vid_data_in_r_reg[12] + (.C(aclk), + .CE(\needs_delay.shift_register_reg[1][0] ), + .D(axi_in_fifo_n_18), + .Q(vid_data_in_r[12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \vid_data_in_r_reg[13] + (.C(aclk), + .CE(\needs_delay.shift_register_reg[1][0] ), + .D(axi_in_fifo_n_17), + .Q(vid_data_in_r[13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \vid_data_in_r_reg[14] + (.C(aclk), + .CE(\needs_delay.shift_register_reg[1][0] ), + .D(axi_in_fifo_n_16), + .Q(vid_data_in_r[14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \vid_data_in_r_reg[15] + (.C(aclk), + .CE(\needs_delay.shift_register_reg[1][0] ), + .D(axi_in_fifo_n_15), + .Q(vid_data_in_r[15]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \vid_data_in_r_reg[16] + (.C(aclk), + .CE(\needs_delay.shift_register_reg[1][0] ), + .D(axi_in_fifo_n_14), + .Q(vid_data_in_r[16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \vid_data_in_r_reg[17] + (.C(aclk), + .CE(\needs_delay.shift_register_reg[1][0] ), + .D(axi_in_fifo_n_13), + .Q(vid_data_in_r[17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \vid_data_in_r_reg[18] + (.C(aclk), + .CE(\needs_delay.shift_register_reg[1][0] ), + .D(axi_in_fifo_n_12), + .Q(vid_data_in_r[18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \vid_data_in_r_reg[19] + (.C(aclk), + .CE(\needs_delay.shift_register_reg[1][0] ), + .D(axi_in_fifo_n_11), + .Q(vid_data_in_r[19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \vid_data_in_r_reg[1] + (.C(aclk), + .CE(\needs_delay.shift_register_reg[1][0] ), + .D(axi_in_fifo_n_29), + .Q(vid_data_in_r[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \vid_data_in_r_reg[20] + (.C(aclk), + .CE(\needs_delay.shift_register_reg[1][0] ), + .D(axi_in_fifo_n_10), + .Q(vid_data_in_r[20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \vid_data_in_r_reg[21] + (.C(aclk), + .CE(\needs_delay.shift_register_reg[1][0] ), + .D(axi_in_fifo_n_9), + .Q(vid_data_in_r[21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \vid_data_in_r_reg[22] + (.C(aclk), + .CE(\needs_delay.shift_register_reg[1][0] ), + .D(axi_in_fifo_n_8), + .Q(vid_data_in_r[22]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \vid_data_in_r_reg[23] + (.C(aclk), + .CE(\needs_delay.shift_register_reg[1][0] ), + .D(axi_in_fifo_n_7), + .Q(vid_data_in_r[23]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \vid_data_in_r_reg[2] + (.C(aclk), + .CE(\needs_delay.shift_register_reg[1][0] ), + .D(axi_in_fifo_n_28), + .Q(vid_data_in_r[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \vid_data_in_r_reg[3] + (.C(aclk), + .CE(\needs_delay.shift_register_reg[1][0] ), + .D(axi_in_fifo_n_27), + .Q(vid_data_in_r[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \vid_data_in_r_reg[4] + (.C(aclk), + .CE(\needs_delay.shift_register_reg[1][0] ), + .D(axi_in_fifo_n_26), + .Q(vid_data_in_r[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \vid_data_in_r_reg[5] + (.C(aclk), + .CE(\needs_delay.shift_register_reg[1][0] ), + .D(axi_in_fifo_n_25), + .Q(vid_data_in_r[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \vid_data_in_r_reg[6] + (.C(aclk), + .CE(\needs_delay.shift_register_reg[1][0] ), + .D(axi_in_fifo_n_24), + .Q(vid_data_in_r[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \vid_data_in_r_reg[7] + (.C(aclk), + .CE(\needs_delay.shift_register_reg[1][0] ), + .D(axi_in_fifo_n_23), + .Q(vid_data_in_r[7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \vid_data_in_r_reg[8] + (.C(aclk), + .CE(\needs_delay.shift_register_reg[1][0] ), + .D(axi_in_fifo_n_22), + .Q(vid_data_in_r[8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \vid_data_in_r_reg[9] + (.C(aclk), + .CE(\needs_delay.shift_register_reg[1][0] ), + .D(axi_in_fifo_n_21), + .Q(vid_data_in_r[9]), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "round" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_round + (sclr, + s, + resetn_out, + E, + aclk, + \core_control_regs[6] , + \needs_delay.shift_register_reg[1][8] , + a, + DI, + S); + output sclr; + output [9:0]s; + input resetn_out; + input [0:0]E; + input aclk; + input [8:0]\core_control_regs[6] ; + input [8:0]\needs_delay.shift_register_reg[1][8] ; + input [0:0]a; + input [0:0]DI; + input [0:0]S; + + wire [0:0]DI; + wire [0:0]E; + wire [0:0]S; + wire [0:0]a; + wire aclk; + wire [8:0]\core_control_regs[6] ; + wire [8:0]\needs_delay.shift_register_reg[1][8] ; + wire resetn_out; + wire [9:0]s; + wire sclr; + + Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr__parameterized3 adder + (.DI(DI), + .E(E), + .S(S), + .SR(sclr), + .a(a), + .aclk(aclk), + .\core_control_regs[6] (\core_control_regs[6] ), + .\needs_delay.shift_register_reg[1][8] (\needs_delay.shift_register_reg[1][8] ), + .resetn_out(resetn_out), + .s(s)); +endmodule + +(* ORIG_REF_NAME = "synch_fifo" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_synch_fifo + (empty_match_reg_0, + empty_match_reg_1, + s_axis_tready_int_reg, + \col_cnt_reg[12] , + reg_update, + Q, + SR, + aclk, + fifo_rd_i_reg, + resetn_out, + \genr_control_regs[0] , + aclken, + s_axis_video_tvalid, + s_axis_video_tready, + da); + output empty_match_reg_0; + output empty_match_reg_1; + output s_axis_tready_int_reg; + output \col_cnt_reg[12] ; + output reg_update; + output [25:0]Q; + input [0:0]SR; + input aclk; + input fifo_rd_i_reg; + input resetn_out; + input [1:0]\genr_control_regs[0] ; + input aclken; + input s_axis_video_tvalid; + input s_axis_video_tready; + input [25:0]da; + + wire [25:0]Q; + wire [0:0]SR; + wire aclk; + wire aclken; + wire [3:0]addra; + wire [3:0]addrb; + wire \col_cnt_reg[12] ; + wire [25:0]da; + wire depth_match_i_1_n_0; + wire depth_match_i_2_n_0; + wire depth_match_reg_n_0; + wire empty_match_i_1_n_0; + wire empty_match_i_2_n_0; + wire empty_match_reg_0; + wire empty_match_reg_1; + wire fifo_rd_i_reg; + wire [1:0]\genr_control_regs[0] ; + wire mem1_n_4; + wire p_0_in; + wire [3:0]plusOp__0; + wire [3:0]read_ptr_reg__0; + wire reg_update; + wire resetn_out; + wire s_axis_tready_int_reg; + wire s_axis_video_tready; + wire s_axis_video_tvalid; + wire \word_count[0]_i_1_n_0 ; + wire \word_count[1]_i_1_n_0 ; + wire \word_count[2]_i_1_n_0 ; + wire \word_count[3]_i_1_n_0 ; + wire \word_count[4]_i_1_n_0 ; + wire \word_count[4]_i_2_n_0 ; + wire \word_count[4]_i_3_n_0 ; + wire \word_count_reg_n_0_[0] ; + wire \word_count_reg_n_0_[1] ; + wire \word_count_reg_n_0_[2] ; + wire \word_count_reg_n_0_[3] ; + wire \word_count_reg_n_0_[4] ; + + LUT6 #( + .INIT(64'hAAAAAAAAAAAAAAAB)) + \col_cnt[12]_i_8 + (.I0(empty_match_reg_0), + .I1(fifo_rd_i_reg), + .I2(\word_count_reg_n_0_[4] ), + .I3(\word_count_reg_n_0_[1] ), + .I4(\word_count_reg_n_0_[3] ), + .I5(\word_count_reg_n_0_[2] ), + .O(\col_cnt_reg[12] )); + LUT6 #( + .INIT(64'hA0A0A0B0A000A0A0)) + depth_match_i_1 + (.I0(depth_match_reg_n_0), + .I1(empty_match_i_2_n_0), + .I2(resetn_out), + .I3(depth_match_i_2_n_0), + .I4(\word_count_reg_n_0_[0] ), + .I5(fifo_rd_i_reg), + .O(depth_match_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT4 #( + .INIT(16'hBFFF)) + depth_match_i_2 + (.I0(\word_count_reg_n_0_[4] ), + .I1(\word_count_reg_n_0_[2] ), + .I2(\word_count_reg_n_0_[3] ), + .I3(\word_count_reg_n_0_[1] ), + .O(depth_match_i_2_n_0)); + FDRE depth_match_reg + (.C(aclk), + .CE(1'b1), + .D(depth_match_i_1_n_0), + .Q(depth_match_reg_n_0), + .R(1'b0)); + LUT5 #( + .INIT(32'hFCFF4000)) + empty_match_i_1 + (.I0(fifo_rd_i_reg), + .I1(\word_count_reg_n_0_[0] ), + .I2(empty_match_i_2_n_0), + .I3(empty_match_reg_1), + .I4(empty_match_reg_0), + .O(empty_match_i_1_n_0)); + LUT5 #( + .INIT(32'h7FFFFFFF)) + empty_match_i_2 + (.I0(s_axis_video_tready), + .I1(s_axis_video_tvalid), + .I2(aclken), + .I3(\genr_control_regs[0] [0]), + .I4(resetn_out), + .O(empty_match_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT4 #( + .INIT(16'h0001)) + empty_match_i_3 + (.I0(\word_count_reg_n_0_[4] ), + .I1(\word_count_reg_n_0_[1] ), + .I2(\word_count_reg_n_0_[3] ), + .I3(\word_count_reg_n_0_[2] ), + .O(empty_match_reg_1)); + FDSE empty_match_reg + (.C(aclk), + .CE(1'b1), + .D(empty_match_i_1_n_0), + .Q(empty_match_reg_0), + .S(SR)); + Arty_Z7_20_v_rgb2ycrcb_0_0_dp_ram_11 mem1 + (.D(addrb), + .Q(read_ptr_reg__0), + .aclk(aclk), + .aclken(aclken), + .da(da), + .depth_match_reg(depth_match_reg_n_0), + .empty_match_reg(empty_match_reg_0), + .fifo_rd_i_reg(fifo_rd_i_reg), + .\genr_control_regs[0] (\genr_control_regs[0] ), + .p_0_in(p_0_in), + .\read_ptr_reg[0] (mem1_n_4), + .reg_update(reg_update), + .resetn_out(resetn_out), + .s_axis_video_tready(s_axis_video_tready), + .s_axis_video_tvalid(s_axis_video_tvalid), + .sof_late_i_reg(Q), + .\write_ptr_reg[3] (addra)); + FDSE \read_ptr_reg[0] + (.C(aclk), + .CE(1'b1), + .D(addrb[0]), + .Q(read_ptr_reg__0[0]), + .S(SR)); + FDSE \read_ptr_reg[1] + (.C(aclk), + .CE(1'b1), + .D(addrb[1]), + .Q(read_ptr_reg__0[1]), + .S(SR)); + FDSE \read_ptr_reg[2] + (.C(aclk), + .CE(1'b1), + .D(addrb[2]), + .Q(read_ptr_reg__0[2]), + .S(SR)); + FDSE \read_ptr_reg[3] + (.C(aclk), + .CE(1'b1), + .D(addrb[3]), + .Q(read_ptr_reg__0[3]), + .S(SR)); + LUT4 #( + .INIT(16'h1555)) + s_axis_tready_int_i_1 + (.I0(\word_count_reg_n_0_[4] ), + .I1(\word_count_reg_n_0_[2] ), + .I2(\word_count_reg_n_0_[3] ), + .I3(\word_count_reg_n_0_[1] ), + .O(s_axis_tready_int_reg)); + LUT1 #( + .INIT(2'h1)) + \word_count[0]_i_1 + (.I0(\word_count_reg_n_0_[0] ), + .O(\word_count[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT4 #( + .INIT(16'h9A65)) + \word_count[1]_i_1 + (.I0(\word_count_reg_n_0_[0] ), + .I1(mem1_n_4), + .I2(p_0_in), + .I3(\word_count_reg_n_0_[1] ), + .O(\word_count[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT5 #( + .INIT(32'hDF20F20D)) + \word_count[2]_i_1 + (.I0(p_0_in), + .I1(mem1_n_4), + .I2(\word_count_reg_n_0_[0] ), + .I3(\word_count_reg_n_0_[2] ), + .I4(\word_count_reg_n_0_[1] ), + .O(\word_count[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hDFFF2000FFBA0045)) + \word_count[3]_i_1 + (.I0(\word_count_reg_n_0_[0] ), + .I1(mem1_n_4), + .I2(p_0_in), + .I3(\word_count_reg_n_0_[1] ), + .I4(\word_count_reg_n_0_[3] ), + .I5(\word_count_reg_n_0_[2] ), + .O(\word_count[3]_i_1_n_0 )); + LUT2 #( + .INIT(4'h6)) + \word_count[4]_i_1 + (.I0(p_0_in), + .I1(mem1_n_4), + .O(\word_count[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAA6AAAAAAAAAA9AA)) + \word_count[4]_i_2 + (.I0(\word_count_reg_n_0_[4] ), + .I1(\word_count_reg_n_0_[3] ), + .I2(\word_count_reg_n_0_[0] ), + .I3(\word_count[4]_i_3_n_0 ), + .I4(\word_count_reg_n_0_[1] ), + .I5(\word_count_reg_n_0_[2] ), + .O(\word_count[4]_i_2_n_0 )); + LUT2 #( + .INIT(4'hB)) + \word_count[4]_i_3 + (.I0(mem1_n_4), + .I1(p_0_in), + .O(\word_count[4]_i_3_n_0 )); + FDRE \word_count_reg[0] + (.C(aclk), + .CE(\word_count[4]_i_1_n_0 ), + .D(\word_count[0]_i_1_n_0 ), + .Q(\word_count_reg_n_0_[0] ), + .R(SR)); + FDRE \word_count_reg[1] + (.C(aclk), + .CE(\word_count[4]_i_1_n_0 ), + .D(\word_count[1]_i_1_n_0 ), + .Q(\word_count_reg_n_0_[1] ), + .R(SR)); + FDRE \word_count_reg[2] + (.C(aclk), + .CE(\word_count[4]_i_1_n_0 ), + .D(\word_count[2]_i_1_n_0 ), + .Q(\word_count_reg_n_0_[2] ), + .R(SR)); + FDRE \word_count_reg[3] + (.C(aclk), + .CE(\word_count[4]_i_1_n_0 ), + .D(\word_count[3]_i_1_n_0 ), + .Q(\word_count_reg_n_0_[3] ), + .R(SR)); + FDRE \word_count_reg[4] + (.C(aclk), + .CE(\word_count[4]_i_1_n_0 ), + .D(\word_count[4]_i_2_n_0 ), + .Q(\word_count_reg_n_0_[4] ), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT1 #( + .INIT(2'h1)) + \write_ptr[0]_i_1 + (.I0(addra[0]), + .O(plusOp__0[0])); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT2 #( + .INIT(4'h6)) + \write_ptr[1]_i_1 + (.I0(addra[0]), + .I1(addra[1]), + .O(plusOp__0[1])); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT3 #( + .INIT(8'h6A)) + \write_ptr[2]_i_1 + (.I0(addra[2]), + .I1(addra[1]), + .I2(addra[0]), + .O(plusOp__0[2])); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT4 #( + .INIT(16'h6AAA)) + \write_ptr[3]_i_1 + (.I0(addra[3]), + .I1(addra[0]), + .I2(addra[1]), + .I3(addra[2]), + .O(plusOp__0[3])); + FDRE \write_ptr_reg[0] + (.C(aclk), + .CE(p_0_in), + .D(plusOp__0[0]), + .Q(addra[0]), + .R(SR)); + FDRE \write_ptr_reg[1] + (.C(aclk), + .CE(p_0_in), + .D(plusOp__0[1]), + .Q(addra[1]), + .R(SR)); + FDRE \write_ptr_reg[2] + (.C(aclk), + .CE(p_0_in), + .D(plusOp__0[2]), + .Q(addra[2]), + .R(SR)); + FDRE \write_ptr_reg[3] + (.C(aclk), + .CE(p_0_in), + .D(plusOp__0[3]), + .Q(addra[3]), + .R(SR)); +endmodule + +(* ORIG_REF_NAME = "synch_fifo_fallthru" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_synch_fifo_fallthru + (\write_ptr_int_reg[0]_0 , + \col_cnt_reg[12] , + \col_cnt_reg[12]_0 , + \col_cnt_reg[12]_1 , + m_axis_video_tvalid, + Q, + SR, + aclk, + m_axis_video_tready, + aclken_0, + \genr_control_regs[0] , + aclken, + empty_match_reg, + empty_match_reg_0, + CO, + wen, + fifo_wr_i, + core_d_out, + eol_late_i_reg, + da); + output \write_ptr_int_reg[0]_0 ; + output \col_cnt_reg[12] ; + output \col_cnt_reg[12]_0 ; + output \col_cnt_reg[12]_1 ; + output m_axis_video_tvalid; + output [25:0]Q; + input [0:0]SR; + input aclk; + input m_axis_video_tready; + input aclken_0; + input [0:0]\genr_control_regs[0] ; + input aclken; + input empty_match_reg; + input empty_match_reg_0; + input [0:0]CO; + input wen; + input fifo_wr_i; + input core_d_out; + input eol_late_i_reg; + input [25:0]da; + + wire [0:0]CO; + wire [1:4]L; + wire [25:0]Q; + wire [0:0]SR; + wire aclk; + wire aclken; + wire aclken_0; + wire axi_fifo_empty; + wire \col_cnt[12]_i_10_n_0 ; + wire \col_cnt[12]_i_11_n_0 ; + wire \col_cnt[12]_i_12_n_0 ; + wire \col_cnt[12]_i_13_n_0 ; + wire \col_cnt[12]_i_14_n_0 ; + wire \col_cnt_reg[12] ; + wire \col_cnt_reg[12]_0 ; + wire \col_cnt_reg[12]_1 ; + wire core_d_out; + wire [25:0]da; + wire empty_int_i_1_n_0; + wire empty_int_i_2_n_0; + wire empty_int_i_3_n_0; + wire empty_int_i_4_n_0; + wire empty_int_i_5_n_0; + wire empty_match_reg; + wire empty_match_reg_0; + wire eol_late_i_reg; + wire eqOp0_out; + wire fifo_wr_i; + wire full_int_i_2_n_0; + wire full_int_i_3_n_0; + wire [0:0]\genr_control_regs[0] ; + wire m_axis_video_tready; + wire m_axis_video_tvalid; + wire mem1_n_0; + wire mem1_n_1; + wire mem1_n_2; + wire mem1_n_3; + wire mem1_n_4; + wire p_0_in; + wire p_0_in0_in; + wire p_1_in; + wire p_1_in1_in; + wire \read_ptr_int_reg_n_0_[0] ; + wire \read_ptr_int_reg_n_0_[1] ; + wire \read_ptr_int_reg_n_0_[2] ; + wire \read_ptr_int_reg_n_0_[3] ; + wire wen; + wire \write_ptr_int[0]_i_1_n_0 ; + wire \write_ptr_int[1]_i_1_n_0 ; + wire \write_ptr_int[2]_i_1_n_0 ; + wire \write_ptr_int[3]_i_1_n_0 ; + wire \write_ptr_int_reg[0]_0 ; + + LUT6 #( + .INIT(64'hAE8AAEAEAEAEEFAE)) + \col_cnt[12]_i_10 + (.I0(empty_int_i_4_n_0), + .I1(\read_ptr_int_reg_n_0_[1] ), + .I2(L[3]), + .I3(\read_ptr_int_reg_n_0_[0] ), + .I4(wen), + .I5(L[4]), + .O(\col_cnt[12]_i_10_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT2 #( + .INIT(4'h6)) + \col_cnt[12]_i_11 + (.I0(p_0_in), + .I1(p_1_in1_in), + .O(\col_cnt[12]_i_11_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT3 #( + .INIT(8'h6F)) + \col_cnt[12]_i_12 + (.I0(wen), + .I1(L[4]), + .I2(\read_ptr_int_reg_n_0_[0] ), + .O(\col_cnt[12]_i_12_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT5 #( + .INIT(32'h6AAA9555)) + \col_cnt[12]_i_13 + (.I0(\read_ptr_int_reg_n_0_[2] ), + .I1(L[3]), + .I2(wen), + .I3(L[4]), + .I4(L[2]), + .O(\col_cnt[12]_i_13_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT4 #( + .INIT(16'h9969)) + \col_cnt[12]_i_14 + (.I0(L[1]), + .I1(\read_ptr_int_reg_n_0_[3] ), + .I2(L[2]), + .I3(\read_ptr_int_reg_n_0_[2] ), + .O(\col_cnt[12]_i_14_n_0 )); + LUT6 #( + .INIT(64'h0000000001FF0101)) + \col_cnt[12]_i_2 + (.I0(\col_cnt_reg[12]_0 ), + .I1(\col_cnt_reg[12]_1 ), + .I2(empty_match_reg), + .I3(empty_match_reg_0), + .I4(CO), + .I5(aclken_0), + .O(\col_cnt_reg[12] )); + LUT6 #( + .INIT(64'h2FD002FDFD022FD0)) + \col_cnt[12]_i_5 + (.I0(L[2]), + .I1(\read_ptr_int_reg_n_0_[2] ), + .I2(\col_cnt[12]_i_10_n_0 ), + .I3(\col_cnt[12]_i_11_n_0 ), + .I4(L[1]), + .I5(\read_ptr_int_reg_n_0_[3] ), + .O(\col_cnt_reg[12]_0 )); + LUT6 #( + .INIT(64'h4920000049204920)) + \col_cnt[12]_i_6 + (.I0(\col_cnt[12]_i_12_n_0 ), + .I1(\read_ptr_int_reg_n_0_[1] ), + .I2(\write_ptr_int[1]_i_1_n_0 ), + .I3(\col_cnt[12]_i_13_n_0 ), + .I4(\col_cnt[12]_i_14_n_0 ), + .I5(\col_cnt[12]_i_10_n_0 ), + .O(\col_cnt_reg[12]_1 )); + LUT6 #( + .INIT(64'h0441100010000441)) + empty_int_i_1 + (.I0(empty_int_i_2_n_0), + .I1(L[1]), + .I2(empty_int_i_3_n_0), + .I3(\read_ptr_int_reg_n_0_[3] ), + .I4(p_0_in), + .I5(p_1_in1_in), + .O(empty_int_i_1_n_0)); + LUT6 #( + .INIT(64'hFFBE7DFFBEFFFFBE)) + empty_int_i_2 + (.I0(empty_int_i_4_n_0), + .I1(L[4]), + .I2(mem1_n_4), + .I3(\read_ptr_int_reg_n_0_[1] ), + .I4(L[3]), + .I5(empty_int_i_5_n_0), + .O(empty_int_i_2_n_0)); + LUT6 #( + .INIT(64'h0020000000000000)) + empty_int_i_3 + (.I0(\read_ptr_int_reg_n_0_[1] ), + .I1(axi_fifo_empty), + .I2(m_axis_video_tready), + .I3(aclken_0), + .I4(\read_ptr_int_reg_n_0_[0] ), + .I5(\read_ptr_int_reg_n_0_[2] ), + .O(empty_int_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT2 #( + .INIT(4'h6)) + empty_int_i_4 + (.I0(L[2]), + .I1(\read_ptr_int_reg_n_0_[2] ), + .O(empty_int_i_4_n_0)); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT5 #( + .INIT(32'h40000000)) + empty_int_i_5 + (.I0(axi_fifo_empty), + .I1(m_axis_video_tready), + .I2(aclken), + .I3(\genr_control_regs[0] ), + .I4(\read_ptr_int_reg_n_0_[0] ), + .O(empty_int_i_5_n_0)); + FDSE empty_int_reg + (.C(aclk), + .CE(1'b1), + .D(empty_int_i_1_n_0), + .Q(axi_fifo_empty), + .S(SR)); + LUT6 #( + .INIT(64'h4008080404808040)) + full_int_i_1 + (.I0(\read_ptr_int_reg_n_0_[3] ), + .I1(full_int_i_2_n_0), + .I2(p_0_in), + .I3(L[1]), + .I4(full_int_i_3_n_0), + .I5(p_1_in1_in), + .O(eqOp0_out)); + LUT6 #( + .INIT(64'h0090900060000090)) + full_int_i_2 + (.I0(\read_ptr_int_reg_n_0_[1] ), + .I1(L[3]), + .I2(\col_cnt[12]_i_13_n_0 ), + .I3(L[4]), + .I4(wen), + .I5(\read_ptr_int_reg_n_0_[0] ), + .O(full_int_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT4 #( + .INIT(16'h8000)) + full_int_i_3 + (.I0(L[2]), + .I1(L[4]), + .I2(wen), + .I3(L[3]), + .O(full_int_i_3_n_0)); + FDRE full_int_reg + (.C(aclk), + .CE(1'b1), + .D(eqOp0_out), + .Q(\write_ptr_int_reg[0]_0 ), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT1 #( + .INIT(2'h1)) + m_axis_video_tvalid_INST_0 + (.I0(axi_fifo_empty), + .O(m_axis_video_tvalid)); + Arty_Z7_20_v_rgb2ycrcb_0_0_dp_ram mem1 + (.ADDRA({mem1_n_1,mem1_n_2,mem1_n_3,mem1_n_4}), + .Q({\read_ptr_int_reg_n_0_[3] ,\read_ptr_int_reg_n_0_[2] ,\read_ptr_int_reg_n_0_[1] ,\read_ptr_int_reg_n_0_[0] }), + .aclk(aclk), + .aclken(aclken), + .aclken_0(aclken_0), + .axi_fifo_empty(axi_fifo_empty), + .da(da), + .\genr_control_regs[0] (\genr_control_regs[0] ), + .m_axis_video_tready(m_axis_video_tready), + .m_axis_video_tuser_sof(Q), + .\read_ptr_int_reg[3] (mem1_n_0), + .wen(wen), + .\write_ptr_int_reg[3] ({L[1],L[2],L[3],L[4]})); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT4 #( + .INIT(16'h6AAA)) + \read_ptr_int[4]_i_1 + (.I0(p_0_in), + .I1(\read_ptr_int_reg_n_0_[3] ), + .I2(mem1_n_0), + .I3(\read_ptr_int_reg_n_0_[2] ), + .O(p_0_in0_in)); + FDRE \read_ptr_int_reg[0] + (.C(aclk), + .CE(1'b1), + .D(mem1_n_4), + .Q(\read_ptr_int_reg_n_0_[0] ), + .R(SR)); + FDRE \read_ptr_int_reg[1] + (.C(aclk), + .CE(1'b1), + .D(mem1_n_3), + .Q(\read_ptr_int_reg_n_0_[1] ), + .R(SR)); + FDRE \read_ptr_int_reg[2] + (.C(aclk), + .CE(1'b1), + .D(mem1_n_2), + .Q(\read_ptr_int_reg_n_0_[2] ), + .R(SR)); + FDRE \read_ptr_int_reg[3] + (.C(aclk), + .CE(1'b1), + .D(mem1_n_1), + .Q(\read_ptr_int_reg_n_0_[3] ), + .R(SR)); + FDRE \read_ptr_int_reg[4] + (.C(aclk), + .CE(1'b1), + .D(p_0_in0_in), + .Q(p_0_in), + .R(SR)); + LUT6 #( + .INIT(64'hAAAAAAAAAAAAAAA6)) + \write_ptr_int[0]_i_1 + (.I0(L[4]), + .I1(fifo_wr_i), + .I2(core_d_out), + .I3(\write_ptr_int_reg[0]_0 ), + .I4(eol_late_i_reg), + .I5(aclken_0), + .O(\write_ptr_int[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT3 #( + .INIT(8'h6A)) + \write_ptr_int[1]_i_1 + (.I0(L[3]), + .I1(wen), + .I2(L[4]), + .O(\write_ptr_int[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT4 #( + .INIT(16'h6AAA)) + \write_ptr_int[2]_i_1 + (.I0(L[2]), + .I1(L[4]), + .I2(wen), + .I3(L[3]), + .O(\write_ptr_int[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT5 #( + .INIT(32'h6AAAAAAA)) + \write_ptr_int[3]_i_1 + (.I0(L[1]), + .I1(L[3]), + .I2(wen), + .I3(L[4]), + .I4(L[2]), + .O(\write_ptr_int[3]_i_1_n_0 )); + LUT6 #( + .INIT(64'h6AAAAAAAAAAAAAAA)) + \write_ptr_int[4]_i_1 + (.I0(p_1_in1_in), + .I1(L[2]), + .I2(L[4]), + .I3(wen), + .I4(L[3]), + .I5(L[1]), + .O(p_1_in)); + FDRE \write_ptr_int_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\write_ptr_int[0]_i_1_n_0 ), + .Q(L[4]), + .R(SR)); + FDRE \write_ptr_int_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\write_ptr_int[1]_i_1_n_0 ), + .Q(L[3]), + .R(SR)); + FDRE \write_ptr_int_reg[2] + (.C(aclk), + .CE(1'b1), + .D(\write_ptr_int[2]_i_1_n_0 ), + .Q(L[2]), + .R(SR)); + FDRE \write_ptr_int_reg[3] + (.C(aclk), + .CE(1'b1), + .D(\write_ptr_int[3]_i_1_n_0 ), + .Q(L[1]), + .R(SR)); + FDRE \write_ptr_int_reg[4] + (.C(aclk), + .CE(1'b1), + .D(p_1_in), + .Q(p_1_in1_in), + .R(SR)); +endmodule + +(* C_ACOEF = "19595" *) (* C_ACTIVE_COLS = "1280" *) (* C_ACTIVE_ROWS = "720" *) +(* C_BCOEF = "7471" *) (* C_CBMAX = "240" *) (* C_CBMIN = "16" *) +(* C_CBOFFSET = "128" *) (* C_CCOEF = "46727" *) (* C_CRMAX = "240" *) +(* C_CRMIN = "16" *) (* C_CROFFSET = "128" *) (* C_DCOEF = "36962" *) +(* C_FAMILY = "zynq" *) (* C_HAS_AXI4_LITE = "0" *) (* C_HAS_CLAMP = "1" *) +(* C_HAS_CLIP = "1" *) (* C_HAS_DEBUG = "0" *) (* C_HAS_INTC_IF = "0" *) +(* C_MAX_COLS = "1280" *) (* C_M_AXIS_VIDEO_DATA_WIDTH = "8" *) (* C_M_AXIS_VIDEO_FORMAT = "1" *) +(* C_M_AXIS_VIDEO_TDATA_WIDTH = "24" *) (* C_S_AXIS_VIDEO_DATA_WIDTH = "8" *) (* C_S_AXIS_VIDEO_FORMAT = "2" *) +(* C_S_AXIS_VIDEO_TDATA_WIDTH = "24" *) (* C_S_AXI_ADDR_WIDTH = "9" *) (* C_S_AXI_CLK_FREQ_HZ = "100000000" *) +(* C_S_AXI_DATA_WIDTH = "32" *) (* C_YMAX = "240" *) (* C_YMIN = "16" *) +(* C_YOFFSET = "16" *) (* ORIG_REF_NAME = "v_rgb2ycrcb" *) (* downgradeipidentifiedwarnings = "yes" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb + (s_axi_aclk, + s_axi_aclken, + s_axi_aresetn, + aclk, + aclken, + aresetn, + intc_if, + irq, + s_axis_video_tdata, + s_axis_video_tready, + s_axis_video_tvalid, + s_axis_video_tlast, + s_axis_video_tuser_sof, + m_axis_video_tdata, + m_axis_video_tvalid, + m_axis_video_tready, + m_axis_video_tlast, + m_axis_video_tuser_sof, + s_axi_awaddr, + s_axi_awvalid, + s_axi_awready, + s_axi_wdata, + s_axi_wstrb, + s_axi_wvalid, + s_axi_wready, + s_axi_bresp, + s_axi_bvalid, + s_axi_bready, + s_axi_araddr, + s_axi_arvalid, + s_axi_arready, + s_axi_rdata, + s_axi_rresp, + s_axi_rvalid, + s_axi_rready); + (* sigis = "CLK" *) input s_axi_aclk; + input s_axi_aclken; + (* sigis = "RST" *) input s_axi_aresetn; + (* sigis = "CLK" *) input aclk; + input aclken; + (* sigis = "RST" *) input aresetn; + output [8:0]intc_if; + (* sigis = "INTR_LEVEL_HIGH" *) output irq; + input [23:0]s_axis_video_tdata; + output s_axis_video_tready; + input s_axis_video_tvalid; + input s_axis_video_tlast; + input s_axis_video_tuser_sof; + output [23:0]m_axis_video_tdata; + output m_axis_video_tvalid; + input m_axis_video_tready; + output m_axis_video_tlast; + output m_axis_video_tuser_sof; + input [8:0]s_axi_awaddr; + input s_axi_awvalid; + output s_axi_awready; + input [31:0]s_axi_wdata; + input [3:0]s_axi_wstrb; + input s_axi_wvalid; + output s_axi_wready; + output [1:0]s_axi_bresp; + output s_axi_bvalid; + input s_axi_bready; + input [8:0]s_axi_araddr; + input s_axi_arvalid; + output s_axi_arready; + output [31:0]s_axi_rdata; + output [1:0]s_axi_rresp; + output s_axi_rvalid; + input s_axi_rready; + + wire U_VIDEO_CTRL_n_318; + wire U_VIDEO_CTRL_n_319; + wire U_VIDEO_CTRL_n_320; + wire aclk; + wire aclken; + wire aresetn; + wire [15:0]\core_control_regs[0] ; + wire [16:0]\core_control_regs[10] ; + wire [16:0]\core_control_regs[11] ; + wire [16:0]\core_control_regs[12] ; + wire [15:0]\core_control_regs[1] ; + wire [15:0]\core_control_regs[2] ; + wire [15:0]\core_control_regs[3] ; + wire [15:0]\core_control_regs[4] ; + wire [15:0]\core_control_regs[5] ; + wire [16:0]\core_control_regs[6] ; + wire [16:0]\core_control_regs[7] ; + wire [16:0]\core_control_regs[8] ; + wire [16:0]\core_control_regs[9] ; + wire core_d; + wire [31:0]\genr_control_regs[0] ; + wire [8:0]intc_if; + wire irq; + wire [23:0]m_axis_video_tdata; + wire m_axis_video_tlast; + wire m_axis_video_tready; + wire m_axis_video_tuser_sof; + wire m_axis_video_tvalid; + wire reg_update; + wire resetn; + wire s_axi_aclk; + wire s_axi_aclken; + wire [8:0]s_axi_araddr; + wire s_axi_aresetn; + wire s_axi_arready; + wire s_axi_arvalid; + wire [8:0]s_axi_awaddr; + wire s_axi_awready; + wire s_axi_awvalid; + wire s_axi_bready; + wire [1:0]s_axi_bresp; + wire s_axi_bvalid; + wire [31:0]s_axi_rdata; + wire s_axi_rready; + wire [1:0]s_axi_rresp; + wire s_axi_rvalid; + wire [31:0]s_axi_wdata; + wire s_axi_wready; + wire [3:0]s_axi_wstrb; + wire s_axi_wvalid; + wire [23:0]s_axis_video_tdata; + wire s_axis_video_tlast; + wire s_axis_video_tready; + wire s_axis_video_tuser_sof; + wire s_axis_video_tvalid; + wire [28:0]\time_control_regs[0] ; + wire NLW_U_VIDEO_CTRL_ipif_cs_out_UNCONNECTED; + wire NLW_U_VIDEO_CTRL_ipif_rnw_out_UNCONNECTED; + wire [31:16]\NLW_U_VIDEO_CTRL_core_control_regs[0]_UNCONNECTED ; + wire [31:17]\NLW_U_VIDEO_CTRL_core_control_regs[10]_UNCONNECTED ; + wire [31:17]\NLW_U_VIDEO_CTRL_core_control_regs[11]_UNCONNECTED ; + wire [31:17]\NLW_U_VIDEO_CTRL_core_control_regs[12]_UNCONNECTED ; + wire [31:16]\NLW_U_VIDEO_CTRL_core_control_regs[1]_UNCONNECTED ; + wire [31:16]\NLW_U_VIDEO_CTRL_core_control_regs[2]_UNCONNECTED ; + wire [31:16]\NLW_U_VIDEO_CTRL_core_control_regs[3]_UNCONNECTED ; + wire [31:16]\NLW_U_VIDEO_CTRL_core_control_regs[4]_UNCONNECTED ; + wire [31:16]\NLW_U_VIDEO_CTRL_core_control_regs[5]_UNCONNECTED ; + wire [31:17]\NLW_U_VIDEO_CTRL_core_control_regs[6]_UNCONNECTED ; + wire [31:17]\NLW_U_VIDEO_CTRL_core_control_regs[7]_UNCONNECTED ; + wire [31:17]\NLW_U_VIDEO_CTRL_core_control_regs[8]_UNCONNECTED ; + wire [31:17]\NLW_U_VIDEO_CTRL_core_control_regs[9]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_genr_control_regs[1]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_genr_control_regs[2]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_genr_control_regs[3]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_genr_control_regs[4]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_genr_control_regs[5]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_genr_control_regs[6]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_genr_control_regs[7]_UNCONNECTED ; + wire [8:0]NLW_U_VIDEO_CTRL_ipif_addr_out_UNCONNECTED; + wire [31:0]NLW_U_VIDEO_CTRL_ipif_data_out_UNCONNECTED; + wire [31:29]\NLW_U_VIDEO_CTRL_time_control_regs[0]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_time_control_regs[1]_UNCONNECTED ; + + (* C_COREGEN_PATCH = "0" *) + (* C_CORE_AXI_WRITE = "416'b00000000000000001111111111111111000000000000000011111111111111110000000000000000111111111111111100000000000000001111111111111111000000000000000011111111111111110000000000000000111111111111111100000000000000011111111111111111000000000000000111111111111111110000000000000001111111111111111100000000000000111111111111111111000000000000001111111111111111110000000000000011111111111111111100000000000000111111111111111111" *) + (* C_CORE_DBUFFER = "416'b00000000000000001111111111111111000000000000000011111111111111110000000000000000111111111111111100000000000000001111111111111111000000000000000011111111111111110000000000000000111111111111111100000000000000011111111111111111000000000000000111111111111111110000000000000001111111111111111100000000000000011111111111111111000000000000000111111111111111110000000000000001111111111111111100000000000000011111111111111111" *) + (* C_CORE_DEFAULT = "416'b00000000000000000000000011110000000000000000000000000000000100000000000000000000000000001111000000000000000000000000000000010000000000000000000000000000111100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000100000000000000000000000000000001000000000000000000000000100110010001011000000000000000000011101001011110000000000000000101101101000011100000000000000001001000001100010" *) + (* C_CORE_NUM_REGS = "13" *) + (* C_FAMILY = "zynq" *) + (* C_GENR_AXI_WRITE = "256'b1100000000000000000000000011111100000000000000010000000000001111000000000000000000000000000011110000000000000001000000000000111100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) + (* C_GENR_DBUFFER = "256'b0000000000000000000000000010110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) + (* C_GENR_DEFAULT = "256'b0000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) + (* C_GENR_NUM_REGS = "8" *) + (* C_GENR_SELFCLR = "256'b0000000000000000000000000000000011111111111111111111111111111111111111111111111111111111111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) + (* C_HAS_AXI4_LITE = "0" *) + (* C_HAS_IRQ = "1" *) + (* C_IS_EVAL = "FALSE" *) + (* C_REVISION_NUMBER = "1" *) + (* C_SRESET_LENGTH = "1" *) + (* C_S_AXI_ADDR_WIDTH = "9" *) + (* C_S_AXI_DATA_WIDTH = "32" *) + (* C_TIMEOUT_HOURS = "8" *) + (* C_TIMEOUT_MINS = "0" *) + (* C_TIME_AXI_WRITE = "64'b1111111111111111111111111111111100000000000000000000000000000111" *) + (* C_TIME_DBUFFER = "64'b1111111111111111111111111111111100000000000000000000000000000111" *) + (* C_TIME_DEFAULT = "64'b0000001011010000000001010000000000000000000000000000000000000000" *) + (* C_TIME_NUM_REGS = "2" *) + (* C_VERSION_MAJOR = "7" *) + (* C_VERSION_MINOR = "1" *) + (* C_VERSION_REVISION = "0" *) + (* downgradeipidentifiedwarnings = "yes" *) + Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl U_VIDEO_CTRL + (.aclk(s_axi_aclk), + .aclk_en(s_axi_aclken), + .aresetn(s_axi_aresetn), + .\core_control_regs[0] ({\NLW_U_VIDEO_CTRL_core_control_regs[0]_UNCONNECTED [31:16],\core_control_regs[0] }), + .\core_control_regs[10] ({\NLW_U_VIDEO_CTRL_core_control_regs[10]_UNCONNECTED [31:17],\core_control_regs[10] }), + .\core_control_regs[11] ({\NLW_U_VIDEO_CTRL_core_control_regs[11]_UNCONNECTED [31:17],\core_control_regs[11] }), + .\core_control_regs[12] ({\NLW_U_VIDEO_CTRL_core_control_regs[12]_UNCONNECTED [31:17],\core_control_regs[12] }), + .\core_control_regs[1] ({\NLW_U_VIDEO_CTRL_core_control_regs[1]_UNCONNECTED [31:16],\core_control_regs[1] }), + .\core_control_regs[2] ({\NLW_U_VIDEO_CTRL_core_control_regs[2]_UNCONNECTED [31:16],\core_control_regs[2] }), + .\core_control_regs[3] ({\NLW_U_VIDEO_CTRL_core_control_regs[3]_UNCONNECTED [31:16],\core_control_regs[3] }), + .\core_control_regs[4] ({\NLW_U_VIDEO_CTRL_core_control_regs[4]_UNCONNECTED [31:16],\core_control_regs[4] }), + .\core_control_regs[5] ({\NLW_U_VIDEO_CTRL_core_control_regs[5]_UNCONNECTED [31:16],\core_control_regs[5] }), + .\core_control_regs[6] ({\NLW_U_VIDEO_CTRL_core_control_regs[6]_UNCONNECTED [31:17],\core_control_regs[6] }), + .\core_control_regs[7] ({\NLW_U_VIDEO_CTRL_core_control_regs[7]_UNCONNECTED [31:17],\core_control_regs[7] }), + .\core_control_regs[8] ({\NLW_U_VIDEO_CTRL_core_control_regs[8]_UNCONNECTED [31:17],\core_control_regs[8] }), + .\core_control_regs[9] ({\NLW_U_VIDEO_CTRL_core_control_regs[9]_UNCONNECTED [31:17],\core_control_regs[9] }), + .core_d_out(core_d), + .\core_status_regs[0] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\core_status_regs[10] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\core_status_regs[11] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\core_status_regs[12] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\core_status_regs[1] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\core_status_regs[2] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\core_status_regs[3] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\core_status_regs[4] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\core_status_regs[5] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\core_status_regs[6] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\core_status_regs[7] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\core_status_regs[8] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\core_status_regs[9] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\genr_control_regs[0] (\genr_control_regs[0] ), + .\genr_control_regs[1] (\NLW_U_VIDEO_CTRL_genr_control_regs[1]_UNCONNECTED [31:0]), + .\genr_control_regs[2] (\NLW_U_VIDEO_CTRL_genr_control_regs[2]_UNCONNECTED [31:0]), + .\genr_control_regs[3] (\NLW_U_VIDEO_CTRL_genr_control_regs[3]_UNCONNECTED [31:0]), + .\genr_control_regs[4] (\NLW_U_VIDEO_CTRL_genr_control_regs[4]_UNCONNECTED [31:0]), + .\genr_control_regs[5] (\NLW_U_VIDEO_CTRL_genr_control_regs[5]_UNCONNECTED [31:0]), + .\genr_control_regs[6] (\NLW_U_VIDEO_CTRL_genr_control_regs[6]_UNCONNECTED [31:0]), + .\genr_control_regs[7] (\NLW_U_VIDEO_CTRL_genr_control_regs[7]_UNCONNECTED [31:0]), + .\genr_status_regs[0] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\genr_status_regs[1] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,intc_if[4],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,intc_if[3:0]}), + .\genr_status_regs[2] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,intc_if[8:5]}), + .\genr_status_regs[3] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\genr_status_regs[4] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\genr_status_regs[5] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\genr_status_regs[6] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\genr_status_regs[7] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .ipif_addr_out(NLW_U_VIDEO_CTRL_ipif_addr_out_UNCONNECTED[8:0]), + .ipif_cs_out(NLW_U_VIDEO_CTRL_ipif_cs_out_UNCONNECTED), + .ipif_data_out(NLW_U_VIDEO_CTRL_ipif_data_out_UNCONNECTED[31:0]), + .ipif_rnw_out(NLW_U_VIDEO_CTRL_ipif_rnw_out_UNCONNECTED), + .irq(irq), + .reg_update(reg_update), + .resetn_out(resetn), + .s_axi_araddr(s_axi_araddr), + .s_axi_arready(s_axi_arready), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awready(s_axi_awready), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_bready(s_axi_bready), + .s_axi_bresp(s_axi_bresp), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_rdata(s_axi_rdata), + .s_axi_rready(s_axi_rready), + .s_axi_rresp(s_axi_rresp), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_wdata(s_axi_wdata), + .s_axi_wready(s_axi_wready), + .s_axi_wstrb(s_axi_wstrb), + .s_axi_wvalid(s_axi_wvalid), + .\time_control_regs[0] ({\NLW_U_VIDEO_CTRL_time_control_regs[0]_UNCONNECTED [31:29],\time_control_regs[0] [28:16],U_VIDEO_CTRL_n_318,U_VIDEO_CTRL_n_319,U_VIDEO_CTRL_n_320,\time_control_regs[0] [12:0]}), + .\time_control_regs[1] (\NLW_U_VIDEO_CTRL_time_control_regs[1]_UNCONNECTED [31:0]), + .\time_status_regs[0] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\time_status_regs[1] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .vid_aclk(aclk), + .vid_aclk_en(aclken), + .vid_aresetn(aresetn)); + Arty_Z7_20_v_rgb2ycrcb_0_0_rgb2ycrcb_top rgb2ycrcb_top_inst + (.Q({m_axis_video_tuser_sof,m_axis_video_tlast,m_axis_video_tdata}), + .aclk(aclk), + .aclken(aclken), + .\core_control_regs[0] (\core_control_regs[0] [7:0]), + .\core_control_regs[10] (\core_control_regs[10] ), + .\core_control_regs[11] (\core_control_regs[11] ), + .\core_control_regs[12] (\core_control_regs[12] ), + .\core_control_regs[1] (\core_control_regs[1] [7:0]), + .\core_control_regs[2] (\core_control_regs[2] [7:0]), + .\core_control_regs[3] (\core_control_regs[3] [7:0]), + .\core_control_regs[4] (\core_control_regs[4] [7:0]), + .\core_control_regs[5] (\core_control_regs[5] [7:0]), + .\core_control_regs[6] (\core_control_regs[6] [8:0]), + .\core_control_regs[7] (\core_control_regs[7] [8:0]), + .\core_control_regs[8] (\core_control_regs[8] [8:0]), + .\core_control_regs[9] (\core_control_regs[9] ), + .core_d_out(core_d), + .da({s_axis_video_tuser_sof,s_axis_video_tlast,s_axis_video_tdata}), + .eol_late_i_reg(intc_if[6]), + .\genr_control_regs[0] ({\genr_control_regs[0] [4],\genr_control_regs[0] [1:0]}), + .intc_if(intc_if[5:1]), + .m_axis_video_tready(m_axis_video_tready), + .m_axis_video_tvalid(m_axis_video_tvalid), + .\needs_delay.shift_register_reg[1][0] (intc_if[0]), + .reg_update(reg_update), + .resetn_out(resetn), + .s_axis_video_tready(s_axis_video_tready), + .s_axis_video_tvalid(s_axis_video_tvalid), + .sof_early_i_reg(intc_if[7]), + .sof_early_i_reg_0(intc_if[8]), + .\time_control_regs[0] ({\time_control_regs[0] [28:16],\time_control_regs[0] [12:0]})); +endmodule + +(* C_COREGEN_PATCH = "0" *) (* C_CORE_AXI_WRITE = "416'b00000000000000001111111111111111000000000000000011111111111111110000000000000000111111111111111100000000000000001111111111111111000000000000000011111111111111110000000000000000111111111111111100000000000000011111111111111111000000000000000111111111111111110000000000000001111111111111111100000000000000111111111111111111000000000000001111111111111111110000000000000011111111111111111100000000000000111111111111111111" *) (* C_CORE_DBUFFER = "416'b00000000000000001111111111111111000000000000000011111111111111110000000000000000111111111111111100000000000000001111111111111111000000000000000011111111111111110000000000000000111111111111111100000000000000011111111111111111000000000000000111111111111111110000000000000001111111111111111100000000000000011111111111111111000000000000000111111111111111110000000000000001111111111111111100000000000000011111111111111111" *) +(* C_CORE_DEFAULT = "416'b00000000000000000000000011110000000000000000000000000000000100000000000000000000000000001111000000000000000000000000000000010000000000000000000000000000111100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000100000000000000000000000000000001000000000000000000000000100110010001011000000000000000000011101001011110000000000000000101101101000011100000000000000001001000001100010" *) (* C_CORE_NUM_REGS = "13" *) (* C_FAMILY = "zynq" *) +(* C_GENR_AXI_WRITE = "256'b1100000000000000000000000011111100000000000000010000000000001111000000000000000000000000000011110000000000000001000000000000111100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_GENR_DBUFFER = "256'b0000000000000000000000000010110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_GENR_DEFAULT = "256'b0000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) +(* C_GENR_NUM_REGS = "8" *) (* C_GENR_SELFCLR = "256'b0000000000000000000000000000000011111111111111111111111111111111111111111111111111111111111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_HAS_AXI4_LITE = "0" *) +(* C_HAS_IRQ = "1" *) (* C_IS_EVAL = "FALSE" *) (* C_REVISION_NUMBER = "1" *) +(* C_SRESET_LENGTH = "1" *) (* C_S_AXI_ADDR_WIDTH = "9" *) (* C_S_AXI_DATA_WIDTH = "32" *) +(* C_TIMEOUT_HOURS = "8" *) (* C_TIMEOUT_MINS = "0" *) (* C_TIME_AXI_WRITE = "64'b1111111111111111111111111111111100000000000000000000000000000111" *) +(* C_TIME_DBUFFER = "64'b1111111111111111111111111111111100000000000000000000000000000111" *) (* C_TIME_DEFAULT = "64'b0000001011010000000001010000000000000000000000000000000000000000" *) (* C_TIME_NUM_REGS = "2" *) +(* C_VERSION_MAJOR = "7" *) (* C_VERSION_MINOR = "1" *) (* C_VERSION_REVISION = "0" *) +(* ORIG_REF_NAME = "video_ctrl" *) (* downgradeipidentifiedwarnings = "yes" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl + (aclk, + aclk_en, + aresetn, + vid_aclk, + vid_aclk_en, + vid_aresetn, + reg_update, + irq, + resetn_out, + core_d_out, + ipif_addr_out, + ipif_rnw_out, + ipif_cs_out, + ipif_data_out, + \genr_control_regs[0] , + \genr_control_regs[1] , + \genr_control_regs[2] , + \genr_control_regs[3] , + \genr_control_regs[4] , + \genr_control_regs[5] , + \genr_control_regs[6] , + \genr_control_regs[7] , + \genr_status_regs[0] , + \genr_status_regs[1] , + \genr_status_regs[2] , + \genr_status_regs[3] , + \genr_status_regs[4] , + \genr_status_regs[5] , + \genr_status_regs[6] , + \genr_status_regs[7] , + \time_control_regs[0] , + \time_control_regs[1] , + \time_status_regs[0] , + \time_status_regs[1] , + \core_control_regs[0] , + \core_control_regs[1] , + \core_control_regs[2] , + \core_control_regs[3] , + \core_control_regs[4] , + \core_control_regs[5] , + \core_control_regs[6] , + \core_control_regs[7] , + \core_control_regs[8] , + \core_control_regs[9] , + \core_control_regs[10] , + \core_control_regs[11] , + \core_control_regs[12] , + \core_status_regs[0] , + \core_status_regs[1] , + \core_status_regs[2] , + \core_status_regs[3] , + \core_status_regs[4] , + \core_status_regs[5] , + \core_status_regs[6] , + \core_status_regs[7] , + \core_status_regs[8] , + \core_status_regs[9] , + \core_status_regs[10] , + \core_status_regs[11] , + \core_status_regs[12] , + s_axi_awaddr, + s_axi_awvalid, + s_axi_awready, + s_axi_wdata, + s_axi_wstrb, + s_axi_wvalid, + s_axi_wready, + s_axi_bresp, + s_axi_bvalid, + s_axi_bready, + s_axi_araddr, + s_axi_arvalid, + s_axi_arready, + s_axi_rdata, + s_axi_rresp, + s_axi_rvalid, + s_axi_rready); + input aclk; + input aclk_en; + input aresetn; + input vid_aclk; + input vid_aclk_en; + input vid_aresetn; + input reg_update; + output irq; + output resetn_out; + output core_d_out; + output [8:0]ipif_addr_out; + output ipif_rnw_out; + output ipif_cs_out; + output [31:0]ipif_data_out; + output [31:0]\genr_control_regs[0] ; + output [31:0]\genr_control_regs[1] ; + output [31:0]\genr_control_regs[2] ; + output [31:0]\genr_control_regs[3] ; + output [31:0]\genr_control_regs[4] ; + output [31:0]\genr_control_regs[5] ; + output [31:0]\genr_control_regs[6] ; + output [31:0]\genr_control_regs[7] ; + input [31:0]\genr_status_regs[0] ; + input [31:0]\genr_status_regs[1] ; + input [31:0]\genr_status_regs[2] ; + input [31:0]\genr_status_regs[3] ; + input [31:0]\genr_status_regs[4] ; + input [31:0]\genr_status_regs[5] ; + input [31:0]\genr_status_regs[6] ; + input [31:0]\genr_status_regs[7] ; + output [31:0]\time_control_regs[0] ; + output [31:0]\time_control_regs[1] ; + input [31:0]\time_status_regs[0] ; + input [31:0]\time_status_regs[1] ; + output [31:0]\core_control_regs[0] ; + output [31:0]\core_control_regs[1] ; + output [31:0]\core_control_regs[2] ; + output [31:0]\core_control_regs[3] ; + output [31:0]\core_control_regs[4] ; + output [31:0]\core_control_regs[5] ; + output [31:0]\core_control_regs[6] ; + output [31:0]\core_control_regs[7] ; + output [31:0]\core_control_regs[8] ; + output [31:0]\core_control_regs[9] ; + output [31:0]\core_control_regs[10] ; + output [31:0]\core_control_regs[11] ; + output [31:0]\core_control_regs[12] ; + input [31:0]\core_status_regs[0] ; + input [31:0]\core_status_regs[1] ; + input [31:0]\core_status_regs[2] ; + input [31:0]\core_status_regs[3] ; + input [31:0]\core_status_regs[4] ; + input [31:0]\core_status_regs[5] ; + input [31:0]\core_status_regs[6] ; + input [31:0]\core_status_regs[7] ; + input [31:0]\core_status_regs[8] ; + input [31:0]\core_status_regs[9] ; + input [31:0]\core_status_regs[10] ; + input [31:0]\core_status_regs[11] ; + input [31:0]\core_status_regs[12] ; + input [8:0]s_axi_awaddr; + input s_axi_awvalid; + output s_axi_awready; + input [31:0]s_axi_wdata; + input [3:0]s_axi_wstrb; + input s_axi_wvalid; + output s_axi_wready; + output [1:0]s_axi_bresp; + output s_axi_bvalid; + input s_axi_bready; + input [8:0]s_axi_araddr; + input s_axi_arvalid; + output s_axi_arready; + output [31:0]s_axi_rdata; + output [1:0]s_axi_rresp; + output s_axi_rvalid; + input s_axi_rready; + + wire \ ; + wire \ ; + (* MAX_FANOUT = "128" *) (* RTL_MAX_FANOUT = "found" *) wire [8:0]ipif_addr_out; + wire vid_aresetn; + + assign \core_control_regs[0] [31] = \ ; + assign \core_control_regs[0] [30] = \ ; + assign \core_control_regs[0] [29] = \ ; + assign \core_control_regs[0] [28] = \ ; + assign \core_control_regs[0] [27] = \ ; + assign \core_control_regs[0] [26] = \ ; + assign \core_control_regs[0] [25] = \ ; + assign \core_control_regs[0] [24] = \ ; + assign \core_control_regs[0] [23] = \ ; + assign \core_control_regs[0] [22] = \ ; + assign \core_control_regs[0] [21] = \ ; + assign \core_control_regs[0] [20] = \ ; + assign \core_control_regs[0] [19] = \ ; + assign \core_control_regs[0] [18] = \ ; + assign \core_control_regs[0] [17] = \ ; + assign \core_control_regs[0] [16] = \ ; + assign \core_control_regs[0] [15] = \ ; + assign \core_control_regs[0] [14] = \ ; + assign \core_control_regs[0] [13] = \ ; + assign \core_control_regs[0] [12] = \ ; + assign \core_control_regs[0] [11] = \ ; + assign \core_control_regs[0] [10] = \ ; + assign \core_control_regs[0] [9] = \ ; + assign \core_control_regs[0] [8] = \ ; + assign \core_control_regs[0] [7] = \ ; + assign \core_control_regs[0] [6] = \ ; + assign \core_control_regs[0] [5] = \ ; + assign \core_control_regs[0] [4] = \ ; + assign \core_control_regs[0] [3] = \ ; + assign \core_control_regs[0] [2] = \ ; + assign \core_control_regs[0] [1] = \ ; + assign \core_control_regs[0] [0] = \ ; + assign \core_control_regs[10] [31] = \ ; + assign \core_control_regs[10] [30] = \ ; + assign \core_control_regs[10] [29] = \ ; + assign \core_control_regs[10] [28] = \ ; + assign \core_control_regs[10] [27] = \ ; + assign \core_control_regs[10] [26] = \ ; + assign \core_control_regs[10] [25] = \ ; + assign \core_control_regs[10] [24] = \ ; + assign \core_control_regs[10] [23] = \ ; + assign \core_control_regs[10] [22] = \ ; + assign \core_control_regs[10] [21] = \ ; + assign \core_control_regs[10] [20] = \ ; + assign \core_control_regs[10] [19] = \ ; + assign \core_control_regs[10] [18] = \ ; + assign \core_control_regs[10] [17] = \ ; + assign \core_control_regs[10] [16] = \ ; + assign \core_control_regs[10] [15] = \ ; + assign \core_control_regs[10] [14] = \ ; + assign \core_control_regs[10] [13] = \ ; + assign \core_control_regs[10] [12] = \ ; + assign \core_control_regs[10] [11] = \ ; + assign \core_control_regs[10] [10] = \ ; + assign \core_control_regs[10] [9] = \ ; + assign \core_control_regs[10] [8] = \ ; + assign \core_control_regs[10] [7] = \ ; + assign \core_control_regs[10] [6] = \ ; + assign \core_control_regs[10] [5] = \ ; + assign \core_control_regs[10] [4] = \ ; + assign \core_control_regs[10] [3] = \ ; + assign \core_control_regs[10] [2] = \ ; + assign \core_control_regs[10] [1] = \ ; + assign \core_control_regs[10] [0] = \ ; + assign \core_control_regs[11] [31] = \ ; + assign \core_control_regs[11] [30] = \ ; + assign \core_control_regs[11] [29] = \ ; + assign \core_control_regs[11] [28] = \ ; + assign \core_control_regs[11] [27] = \ ; + assign \core_control_regs[11] [26] = \ ; + assign \core_control_regs[11] [25] = \ ; + assign \core_control_regs[11] [24] = \ ; + assign \core_control_regs[11] [23] = \ ; + assign \core_control_regs[11] [22] = \ ; + assign \core_control_regs[11] [21] = \ ; + assign \core_control_regs[11] [20] = \ ; + assign \core_control_regs[11] [19] = \ ; + assign \core_control_regs[11] [18] = \ ; + assign \core_control_regs[11] [17] = \ ; + assign \core_control_regs[11] [16] = \ ; + assign \core_control_regs[11] [15] = \ ; + assign \core_control_regs[11] [14] = \ ; + assign \core_control_regs[11] [13] = \ ; + assign \core_control_regs[11] [12] = \ ; + assign \core_control_regs[11] [11] = \ ; + assign \core_control_regs[11] [10] = \ ; + assign \core_control_regs[11] [9] = \ ; + assign \core_control_regs[11] [8] = \ ; + assign \core_control_regs[11] [7] = \ ; + assign \core_control_regs[11] [6] = \ ; + assign \core_control_regs[11] [5] = \ ; + assign \core_control_regs[11] [4] = \ ; + assign \core_control_regs[11] [3] = \ ; + assign \core_control_regs[11] [2] = \ ; + assign \core_control_regs[11] [1] = \ ; + assign \core_control_regs[11] [0] = \ ; + assign \core_control_regs[12] [31] = \ ; + assign \core_control_regs[12] [30] = \ ; + assign \core_control_regs[12] [29] = \ ; + assign \core_control_regs[12] [28] = \ ; + assign \core_control_regs[12] [27] = \ ; + assign \core_control_regs[12] [26] = \ ; + assign \core_control_regs[12] [25] = \ ; + assign \core_control_regs[12] [24] = \ ; + assign \core_control_regs[12] [23] = \ ; + assign \core_control_regs[12] [22] = \ ; + assign \core_control_regs[12] [21] = \ ; + assign \core_control_regs[12] [20] = \ ; + assign \core_control_regs[12] [19] = \ ; + assign \core_control_regs[12] [18] = \ ; + assign \core_control_regs[12] [17] = \ ; + assign \core_control_regs[12] [16] = \ ; + assign \core_control_regs[12] [15] = \ ; + assign \core_control_regs[12] [14] = \ ; + assign \core_control_regs[12] [13] = \ ; + assign \core_control_regs[12] [12] = \ ; + assign \core_control_regs[12] [11] = \ ; + assign \core_control_regs[12] [10] = \ ; + assign \core_control_regs[12] [9] = \ ; + assign \core_control_regs[12] [8] = \ ; + assign \core_control_regs[12] [7] = \ ; + assign \core_control_regs[12] [6] = \ ; + assign \core_control_regs[12] [5] = \ ; + assign \core_control_regs[12] [4] = \ ; + assign \core_control_regs[12] [3] = \ ; + assign \core_control_regs[12] [2] = \ ; + assign \core_control_regs[12] [1] = \ ; + assign \core_control_regs[12] [0] = \ ; + assign \core_control_regs[1] [31] = \ ; + assign \core_control_regs[1] [30] = \ ; + assign \core_control_regs[1] [29] = \ ; + assign \core_control_regs[1] [28] = \ ; + assign \core_control_regs[1] [27] = \ ; + assign \core_control_regs[1] [26] = \ ; + assign \core_control_regs[1] [25] = \ ; + assign \core_control_regs[1] [24] = \ ; + assign \core_control_regs[1] [23] = \ ; + assign \core_control_regs[1] [22] = \ ; + assign \core_control_regs[1] [21] = \ ; + assign \core_control_regs[1] [20] = \ ; + assign \core_control_regs[1] [19] = \ ; + assign \core_control_regs[1] [18] = \ ; + assign \core_control_regs[1] [17] = \ ; + assign \core_control_regs[1] [16] = \ ; + assign \core_control_regs[1] [15] = \ ; + assign \core_control_regs[1] [14] = \ ; + assign \core_control_regs[1] [13] = \ ; + assign \core_control_regs[1] [12] = \ ; + assign \core_control_regs[1] [11] = \ ; + assign \core_control_regs[1] [10] = \ ; + assign \core_control_regs[1] [9] = \ ; + assign \core_control_regs[1] [8] = \ ; + assign \core_control_regs[1] [7] = \ ; + assign \core_control_regs[1] [6] = \ ; + assign \core_control_regs[1] [5] = \ ; + assign \core_control_regs[1] [4] = \ ; + assign \core_control_regs[1] [3] = \ ; + assign \core_control_regs[1] [2] = \ ; + assign \core_control_regs[1] [1] = \ ; + assign \core_control_regs[1] [0] = \ ; + assign \core_control_regs[2] [31] = \ ; + assign \core_control_regs[2] [30] = \ ; + assign \core_control_regs[2] [29] = \ ; + assign \core_control_regs[2] [28] = \ ; + assign \core_control_regs[2] [27] = \ ; + assign \core_control_regs[2] [26] = \ ; + assign \core_control_regs[2] [25] = \ ; + assign \core_control_regs[2] [24] = \ ; + assign \core_control_regs[2] [23] = \ ; + assign \core_control_regs[2] [22] = \ ; + assign \core_control_regs[2] [21] = \ ; + assign \core_control_regs[2] [20] = \ ; + assign \core_control_regs[2] [19] = \ ; + assign \core_control_regs[2] [18] = \ ; + assign \core_control_regs[2] [17] = \ ; + assign \core_control_regs[2] [16] = \ ; + assign \core_control_regs[2] [15] = \ ; + assign \core_control_regs[2] [14] = \ ; + assign \core_control_regs[2] [13] = \ ; + assign \core_control_regs[2] [12] = \ ; + assign \core_control_regs[2] [11] = \ ; + assign \core_control_regs[2] [10] = \ ; + assign \core_control_regs[2] [9] = \ ; + assign \core_control_regs[2] [8] = \ ; + assign \core_control_regs[2] [7] = \ ; + assign \core_control_regs[2] [6] = \ ; + assign \core_control_regs[2] [5] = \ ; + assign \core_control_regs[2] [4] = \ ; + assign \core_control_regs[2] [3] = \ ; + assign \core_control_regs[2] [2] = \ ; + assign \core_control_regs[2] [1] = \ ; + assign \core_control_regs[2] [0] = \ ; + assign \core_control_regs[3] [31] = \ ; + assign \core_control_regs[3] [30] = \ ; + assign \core_control_regs[3] [29] = \ ; + assign \core_control_regs[3] [28] = \ ; + assign \core_control_regs[3] [27] = \ ; + assign \core_control_regs[3] [26] = \ ; + assign \core_control_regs[3] [25] = \ ; + assign \core_control_regs[3] [24] = \ ; + assign \core_control_regs[3] [23] = \ ; + assign \core_control_regs[3] [22] = \ ; + assign \core_control_regs[3] [21] = \ ; + assign \core_control_regs[3] [20] = \ ; + assign \core_control_regs[3] [19] = \ ; + assign \core_control_regs[3] [18] = \ ; + assign \core_control_regs[3] [17] = \ ; + assign \core_control_regs[3] [16] = \ ; + assign \core_control_regs[3] [15] = \ ; + assign \core_control_regs[3] [14] = \ ; + assign \core_control_regs[3] [13] = \ ; + assign \core_control_regs[3] [12] = \ ; + assign \core_control_regs[3] [11] = \ ; + assign \core_control_regs[3] [10] = \ ; + assign \core_control_regs[3] [9] = \ ; + assign \core_control_regs[3] [8] = \ ; + assign \core_control_regs[3] [7] = \ ; + assign \core_control_regs[3] [6] = \ ; + assign \core_control_regs[3] [5] = \ ; + assign \core_control_regs[3] [4] = \ ; + assign \core_control_regs[3] [3] = \ ; + assign \core_control_regs[3] [2] = \ ; + assign \core_control_regs[3] [1] = \ ; + assign \core_control_regs[3] [0] = \ ; + assign \core_control_regs[4] [31] = \ ; + assign \core_control_regs[4] [30] = \ ; + assign \core_control_regs[4] [29] = \ ; + assign \core_control_regs[4] [28] = \ ; + assign \core_control_regs[4] [27] = \ ; + assign \core_control_regs[4] [26] = \ ; + assign \core_control_regs[4] [25] = \ ; + assign \core_control_regs[4] [24] = \ ; + assign \core_control_regs[4] [23] = \ ; + assign \core_control_regs[4] [22] = \ ; + assign \core_control_regs[4] [21] = \ ; + assign \core_control_regs[4] [20] = \ ; + assign \core_control_regs[4] [19] = \ ; + assign \core_control_regs[4] [18] = \ ; + assign \core_control_regs[4] [17] = \ ; + assign \core_control_regs[4] [16] = \ ; + assign \core_control_regs[4] [15] = \ ; + assign \core_control_regs[4] [14] = \ ; + assign \core_control_regs[4] [13] = \ ; + assign \core_control_regs[4] [12] = \ ; + assign \core_control_regs[4] [11] = \ ; + assign \core_control_regs[4] [10] = \ ; + assign \core_control_regs[4] [9] = \ ; + assign \core_control_regs[4] [8] = \ ; + assign \core_control_regs[4] [7] = \ ; + assign \core_control_regs[4] [6] = \ ; + assign \core_control_regs[4] [5] = \ ; + assign \core_control_regs[4] [4] = \ ; + assign \core_control_regs[4] [3] = \ ; + assign \core_control_regs[4] [2] = \ ; + assign \core_control_regs[4] [1] = \ ; + assign \core_control_regs[4] [0] = \ ; + assign \core_control_regs[5] [31] = \ ; + assign \core_control_regs[5] [30] = \ ; + assign \core_control_regs[5] [29] = \ ; + assign \core_control_regs[5] [28] = \ ; + assign \core_control_regs[5] [27] = \ ; + assign \core_control_regs[5] [26] = \ ; + assign \core_control_regs[5] [25] = \ ; + assign \core_control_regs[5] [24] = \ ; + assign \core_control_regs[5] [23] = \ ; + assign \core_control_regs[5] [22] = \ ; + assign \core_control_regs[5] [21] = \ ; + assign \core_control_regs[5] [20] = \ ; + assign \core_control_regs[5] [19] = \ ; + assign \core_control_regs[5] [18] = \ ; + assign \core_control_regs[5] [17] = \ ; + assign \core_control_regs[5] [16] = \ ; + assign \core_control_regs[5] [15] = \ ; + assign \core_control_regs[5] [14] = \ ; + assign \core_control_regs[5] [13] = \ ; + assign \core_control_regs[5] [12] = \ ; + assign \core_control_regs[5] [11] = \ ; + assign \core_control_regs[5] [10] = \ ; + assign \core_control_regs[5] [9] = \ ; + assign \core_control_regs[5] [8] = \ ; + assign \core_control_regs[5] [7] = \ ; + assign \core_control_regs[5] [6] = \ ; + assign \core_control_regs[5] [5] = \ ; + assign \core_control_regs[5] [4] = \ ; + assign \core_control_regs[5] [3] = \ ; + assign \core_control_regs[5] [2] = \ ; + assign \core_control_regs[5] [1] = \ ; + assign \core_control_regs[5] [0] = \ ; + assign \core_control_regs[6] [31] = \ ; + assign \core_control_regs[6] [30] = \ ; + assign \core_control_regs[6] [29] = \ ; + assign \core_control_regs[6] [28] = \ ; + assign \core_control_regs[6] [27] = \ ; + assign \core_control_regs[6] [26] = \ ; + assign \core_control_regs[6] [25] = \ ; + assign \core_control_regs[6] [24] = \ ; + assign \core_control_regs[6] [23] = \ ; + assign \core_control_regs[6] [22] = \ ; + assign \core_control_regs[6] [21] = \ ; + assign \core_control_regs[6] [20] = \ ; + assign \core_control_regs[6] [19] = \ ; + assign \core_control_regs[6] [18] = \ ; + assign \core_control_regs[6] [17] = \ ; + assign \core_control_regs[6] [16] = \ ; + assign \core_control_regs[6] [15] = \ ; + assign \core_control_regs[6] [14] = \ ; + assign \core_control_regs[6] [13] = \ ; + assign \core_control_regs[6] [12] = \ ; + assign \core_control_regs[6] [11] = \ ; + assign \core_control_regs[6] [10] = \ ; + assign \core_control_regs[6] [9] = \ ; + assign \core_control_regs[6] [8] = \ ; + assign \core_control_regs[6] [7] = \ ; + assign \core_control_regs[6] [6] = \ ; + assign \core_control_regs[6] [5] = \ ; + assign \core_control_regs[6] [4] = \ ; + assign \core_control_regs[6] [3] = \ ; + assign \core_control_regs[6] [2] = \ ; + assign \core_control_regs[6] [1] = \ ; + assign \core_control_regs[6] [0] = \ ; + assign \core_control_regs[7] [31] = \ ; + assign \core_control_regs[7] [30] = \ ; + assign \core_control_regs[7] [29] = \ ; + assign \core_control_regs[7] [28] = \ ; + assign \core_control_regs[7] [27] = \ ; + assign \core_control_regs[7] [26] = \ ; + assign \core_control_regs[7] [25] = \ ; + assign \core_control_regs[7] [24] = \ ; + assign \core_control_regs[7] [23] = \ ; + assign \core_control_regs[7] [22] = \ ; + assign \core_control_regs[7] [21] = \ ; + assign \core_control_regs[7] [20] = \ ; + assign \core_control_regs[7] [19] = \ ; + assign \core_control_regs[7] [18] = \ ; + assign \core_control_regs[7] [17] = \ ; + assign \core_control_regs[7] [16] = \ ; + assign \core_control_regs[7] [15] = \ ; + assign \core_control_regs[7] [14] = \ ; + assign \core_control_regs[7] [13] = \ ; + assign \core_control_regs[7] [12] = \ ; + assign \core_control_regs[7] [11] = \ ; + assign \core_control_regs[7] [10] = \ ; + assign \core_control_regs[7] [9] = \ ; + assign \core_control_regs[7] [8] = \ ; + assign \core_control_regs[7] [7] = \ ; + assign \core_control_regs[7] [6] = \ ; + assign \core_control_regs[7] [5] = \ ; + assign \core_control_regs[7] [4] = \ ; + assign \core_control_regs[7] [3] = \ ; + assign \core_control_regs[7] [2] = \ ; + assign \core_control_regs[7] [1] = \ ; + assign \core_control_regs[7] [0] = \ ; + assign \core_control_regs[8] [31] = \ ; + assign \core_control_regs[8] [30] = \ ; + assign \core_control_regs[8] [29] = \ ; + assign \core_control_regs[8] [28] = \ ; + assign \core_control_regs[8] [27] = \ ; + assign \core_control_regs[8] [26] = \ ; + assign \core_control_regs[8] [25] = \ ; + assign \core_control_regs[8] [24] = \ ; + assign \core_control_regs[8] [23] = \ ; + assign \core_control_regs[8] [22] = \ ; + assign \core_control_regs[8] [21] = \ ; + assign \core_control_regs[8] [20] = \ ; + assign \core_control_regs[8] [19] = \ ; + assign \core_control_regs[8] [18] = \ ; + assign \core_control_regs[8] [17] = \ ; + assign \core_control_regs[8] [16] = \ ; + assign \core_control_regs[8] [15] = \ ; + assign \core_control_regs[8] [14] = \ ; + assign \core_control_regs[8] [13] = \ ; + assign \core_control_regs[8] [12] = \ ; + assign \core_control_regs[8] [11] = \ ; + assign \core_control_regs[8] [10] = \ ; + assign \core_control_regs[8] [9] = \ ; + assign \core_control_regs[8] [8] = \ ; + assign \core_control_regs[8] [7] = \ ; + assign \core_control_regs[8] [6] = \ ; + assign \core_control_regs[8] [5] = \ ; + assign \core_control_regs[8] [4] = \ ; + assign \core_control_regs[8] [3] = \ ; + assign \core_control_regs[8] [2] = \ ; + assign \core_control_regs[8] [1] = \ ; + assign \core_control_regs[8] [0] = \ ; + assign \core_control_regs[9] [31] = \ ; + assign \core_control_regs[9] [30] = \ ; + assign \core_control_regs[9] [29] = \ ; + assign \core_control_regs[9] [28] = \ ; + assign \core_control_regs[9] [27] = \ ; + assign \core_control_regs[9] [26] = \ ; + assign \core_control_regs[9] [25] = \ ; + assign \core_control_regs[9] [24] = \ ; + assign \core_control_regs[9] [23] = \ ; + assign \core_control_regs[9] [22] = \ ; + assign \core_control_regs[9] [21] = \ ; + assign \core_control_regs[9] [20] = \ ; + assign \core_control_regs[9] [19] = \ ; + assign \core_control_regs[9] [18] = \ ; + assign \core_control_regs[9] [17] = \ ; + assign \core_control_regs[9] [16] = \ ; + assign \core_control_regs[9] [15] = \ ; + assign \core_control_regs[9] [14] = \ ; + assign \core_control_regs[9] [13] = \ ; + assign \core_control_regs[9] [12] = \ ; + assign \core_control_regs[9] [11] = \ ; + assign \core_control_regs[9] [10] = \ ; + assign \core_control_regs[9] [9] = \ ; + assign \core_control_regs[9] [8] = \ ; + assign \core_control_regs[9] [7] = \ ; + assign \core_control_regs[9] [6] = \ ; + assign \core_control_regs[9] [5] = \ ; + assign \core_control_regs[9] [4] = \ ; + assign \core_control_regs[9] [3] = \ ; + assign \core_control_regs[9] [2] = \ ; + assign \core_control_regs[9] [1] = \ ; + assign \core_control_regs[9] [0] = \ ; + assign core_d_out = \ ; + assign \genr_control_regs[0] [31] = \ ; + assign \genr_control_regs[0] [30] = \ ; + assign \genr_control_regs[0] [29] = \ ; + assign \genr_control_regs[0] [28] = \ ; + assign \genr_control_regs[0] [27] = \ ; + assign \genr_control_regs[0] [26] = \ ; + assign \genr_control_regs[0] [25] = \ ; + assign \genr_control_regs[0] [24] = \ ; + assign \genr_control_regs[0] [23] = \ ; + assign \genr_control_regs[0] [22] = \ ; + assign \genr_control_regs[0] [21] = \ ; + assign \genr_control_regs[0] [20] = \ ; + assign \genr_control_regs[0] [19] = \ ; + assign \genr_control_regs[0] [18] = \ ; + assign \genr_control_regs[0] [17] = \ ; + assign \genr_control_regs[0] [16] = \ ; + assign \genr_control_regs[0] [15] = \ ; + assign \genr_control_regs[0] [14] = \ ; + assign \genr_control_regs[0] [13] = \ ; + assign \genr_control_regs[0] [12] = \ ; + assign \genr_control_regs[0] [11] = \ ; + assign \genr_control_regs[0] [10] = \ ; + assign \genr_control_regs[0] [9] = \ ; + assign \genr_control_regs[0] [8] = \ ; + assign \genr_control_regs[0] [7] = \ ; + assign \genr_control_regs[0] [6] = \ ; + assign \genr_control_regs[0] [5] = \ ; + assign \genr_control_regs[0] [4] = \ ; + assign \genr_control_regs[0] [3] = \ ; + assign \genr_control_regs[0] [2] = \ ; + assign \genr_control_regs[0] [1] = \ ; + assign \genr_control_regs[0] [0] = \ ; + assign \genr_control_regs[1] [31] = \ ; + assign \genr_control_regs[1] [30] = \ ; + assign \genr_control_regs[1] [29] = \ ; + assign \genr_control_regs[1] [28] = \ ; + assign \genr_control_regs[1] [27] = \ ; + assign \genr_control_regs[1] [26] = \ ; + assign \genr_control_regs[1] [25] = \ ; + assign \genr_control_regs[1] [24] = \ ; + assign \genr_control_regs[1] [23] = \ ; + assign \genr_control_regs[1] [22] = \ ; + assign \genr_control_regs[1] [21] = \ ; + assign \genr_control_regs[1] [20] = \ ; + assign \genr_control_regs[1] [19] = \ ; + assign \genr_control_regs[1] [18] = \ ; + assign \genr_control_regs[1] [17] = \ ; + assign \genr_control_regs[1] [16] = \ ; + assign \genr_control_regs[1] [15] = \ ; + assign \genr_control_regs[1] [14] = \ ; + assign \genr_control_regs[1] [13] = \ ; + assign \genr_control_regs[1] [12] = \ ; + assign \genr_control_regs[1] [11] = \ ; + assign \genr_control_regs[1] [10] = \ ; + assign \genr_control_regs[1] [9] = \ ; + assign \genr_control_regs[1] [8] = \ ; + assign \genr_control_regs[1] [7] = \ ; + assign \genr_control_regs[1] [6] = \ ; + assign \genr_control_regs[1] [5] = \ ; + assign \genr_control_regs[1] [4] = \ ; + assign \genr_control_regs[1] [3] = \ ; + assign \genr_control_regs[1] [2] = \ ; + assign \genr_control_regs[1] [1] = \ ; + assign \genr_control_regs[1] [0] = \ ; + assign \genr_control_regs[2] [31] = \ ; + assign \genr_control_regs[2] [30] = \ ; + assign \genr_control_regs[2] [29] = \ ; + assign \genr_control_regs[2] [28] = \ ; + assign \genr_control_regs[2] [27] = \ ; + assign \genr_control_regs[2] [26] = \ ; + assign \genr_control_regs[2] [25] = \ ; + assign \genr_control_regs[2] [24] = \ ; + assign \genr_control_regs[2] [23] = \ ; + assign \genr_control_regs[2] [22] = \ ; + assign \genr_control_regs[2] [21] = \ ; + assign \genr_control_regs[2] [20] = \ ; + assign \genr_control_regs[2] [19] = \ ; + assign \genr_control_regs[2] [18] = \ ; + assign \genr_control_regs[2] [17] = \ ; + assign \genr_control_regs[2] [16] = \ ; + assign \genr_control_regs[2] [15] = \ ; + assign \genr_control_regs[2] [14] = \ ; + assign \genr_control_regs[2] [13] = \ ; + assign \genr_control_regs[2] [12] = \ ; + assign \genr_control_regs[2] [11] = \ ; + assign \genr_control_regs[2] [10] = \ ; + assign \genr_control_regs[2] [9] = \ ; + assign \genr_control_regs[2] [8] = \ ; + assign \genr_control_regs[2] [7] = \ ; + assign \genr_control_regs[2] [6] = \ ; + assign \genr_control_regs[2] [5] = \ ; + assign \genr_control_regs[2] [4] = \ ; + assign \genr_control_regs[2] [3] = \ ; + assign \genr_control_regs[2] [2] = \ ; + assign \genr_control_regs[2] [1] = \ ; + assign \genr_control_regs[2] [0] = \ ; + assign \genr_control_regs[3] [31] = \ ; + assign \genr_control_regs[3] [30] = \ ; + assign \genr_control_regs[3] [29] = \ ; + assign \genr_control_regs[3] [28] = \ ; + assign \genr_control_regs[3] [27] = \ ; + assign \genr_control_regs[3] [26] = \ ; + assign \genr_control_regs[3] [25] = \ ; + assign \genr_control_regs[3] [24] = \ ; + assign \genr_control_regs[3] [23] = \ ; + assign \genr_control_regs[3] [22] = \ ; + assign \genr_control_regs[3] [21] = \ ; + assign \genr_control_regs[3] [20] = \ ; + assign \genr_control_regs[3] [19] = \ ; + assign \genr_control_regs[3] [18] = \ ; + assign \genr_control_regs[3] [17] = \ ; + assign \genr_control_regs[3] [16] = \ ; + assign \genr_control_regs[3] [15] = \ ; + assign \genr_control_regs[3] [14] = \ ; + assign \genr_control_regs[3] [13] = \ ; + assign \genr_control_regs[3] [12] = \ ; + assign \genr_control_regs[3] [11] = \ ; + assign \genr_control_regs[3] [10] = \ ; + assign \genr_control_regs[3] [9] = \ ; + assign \genr_control_regs[3] [8] = \ ; + assign \genr_control_regs[3] [7] = \ ; + assign \genr_control_regs[3] [6] = \ ; + assign \genr_control_regs[3] [5] = \ ; + assign \genr_control_regs[3] [4] = \ ; + assign \genr_control_regs[3] [3] = \ ; + assign \genr_control_regs[3] [2] = \ ; + assign \genr_control_regs[3] [1] = \ ; + assign \genr_control_regs[3] [0] = \ ; + assign \genr_control_regs[4] [31] = \ ; + assign \genr_control_regs[4] [30] = \ ; + assign \genr_control_regs[4] [29] = \ ; + assign \genr_control_regs[4] [28] = \ ; + assign \genr_control_regs[4] [27] = \ ; + assign \genr_control_regs[4] [26] = \ ; + assign \genr_control_regs[4] [25] = \ ; + assign \genr_control_regs[4] [24] = \ ; + assign \genr_control_regs[4] [23] = \ ; + assign \genr_control_regs[4] [22] = \ ; + assign \genr_control_regs[4] [21] = \ ; + assign \genr_control_regs[4] [20] = \ ; + assign \genr_control_regs[4] [19] = \ ; + assign \genr_control_regs[4] [18] = \ ; + assign \genr_control_regs[4] [17] = \ ; + assign \genr_control_regs[4] [16] = \ ; + assign \genr_control_regs[4] [15] = \ ; + assign \genr_control_regs[4] [14] = \ ; + assign \genr_control_regs[4] [13] = \ ; + assign \genr_control_regs[4] [12] = \ ; + assign \genr_control_regs[4] [11] = \ ; + assign \genr_control_regs[4] [10] = \ ; + assign \genr_control_regs[4] [9] = \ ; + assign \genr_control_regs[4] [8] = \ ; + assign \genr_control_regs[4] [7] = \ ; + assign \genr_control_regs[4] [6] = \ ; + assign \genr_control_regs[4] [5] = \ ; + assign \genr_control_regs[4] [4] = \ ; + assign \genr_control_regs[4] [3] = \ ; + assign \genr_control_regs[4] [2] = \ ; + assign \genr_control_regs[4] [1] = \ ; + assign \genr_control_regs[4] [0] = \ ; + assign \genr_control_regs[5] [31] = \ ; + assign \genr_control_regs[5] [30] = \ ; + assign \genr_control_regs[5] [29] = \ ; + assign \genr_control_regs[5] [28] = \ ; + assign \genr_control_regs[5] [27] = \ ; + assign \genr_control_regs[5] [26] = \ ; + assign \genr_control_regs[5] [25] = \ ; + assign \genr_control_regs[5] [24] = \ ; + assign \genr_control_regs[5] [23] = \ ; + assign \genr_control_regs[5] [22] = \ ; + assign \genr_control_regs[5] [21] = \ ; + assign \genr_control_regs[5] [20] = \ ; + assign \genr_control_regs[5] [19] = \ ; + assign \genr_control_regs[5] [18] = \ ; + assign \genr_control_regs[5] [17] = \ ; + assign \genr_control_regs[5] [16] = \ ; + assign \genr_control_regs[5] [15] = \ ; + assign \genr_control_regs[5] [14] = \ ; + assign \genr_control_regs[5] [13] = \ ; + assign \genr_control_regs[5] [12] = \ ; + assign \genr_control_regs[5] [11] = \ ; + assign \genr_control_regs[5] [10] = \ ; + assign \genr_control_regs[5] [9] = \ ; + assign \genr_control_regs[5] [8] = \ ; + assign \genr_control_regs[5] [7] = \ ; + assign \genr_control_regs[5] [6] = \ ; + assign \genr_control_regs[5] [5] = \ ; + assign \genr_control_regs[5] [4] = \ ; + assign \genr_control_regs[5] [3] = \ ; + assign \genr_control_regs[5] [2] = \ ; + assign \genr_control_regs[5] [1] = \ ; + assign \genr_control_regs[5] [0] = \ ; + assign \genr_control_regs[6] [31] = \ ; + assign \genr_control_regs[6] [30] = \ ; + assign \genr_control_regs[6] [29] = \ ; + assign \genr_control_regs[6] [28] = \ ; + assign \genr_control_regs[6] [27] = \ ; + assign \genr_control_regs[6] [26] = \ ; + assign \genr_control_regs[6] [25] = \ ; + assign \genr_control_regs[6] [24] = \ ; + assign \genr_control_regs[6] [23] = \ ; + assign \genr_control_regs[6] [22] = \ ; + assign \genr_control_regs[6] [21] = \ ; + assign \genr_control_regs[6] [20] = \ ; + assign \genr_control_regs[6] [19] = \ ; + assign \genr_control_regs[6] [18] = \ ; + assign \genr_control_regs[6] [17] = \ ; + assign \genr_control_regs[6] [16] = \ ; + assign \genr_control_regs[6] [15] = \ ; + assign \genr_control_regs[6] [14] = \ ; + assign \genr_control_regs[6] [13] = \ ; + assign \genr_control_regs[6] [12] = \ ; + assign \genr_control_regs[6] [11] = \ ; + assign \genr_control_regs[6] [10] = \ ; + assign \genr_control_regs[6] [9] = \ ; + assign \genr_control_regs[6] [8] = \ ; + assign \genr_control_regs[6] [7] = \ ; + assign \genr_control_regs[6] [6] = \ ; + assign \genr_control_regs[6] [5] = \ ; + assign \genr_control_regs[6] [4] = \ ; + assign \genr_control_regs[6] [3] = \ ; + assign \genr_control_regs[6] [2] = \ ; + assign \genr_control_regs[6] [1] = \ ; + assign \genr_control_regs[6] [0] = \ ; + assign \genr_control_regs[7] [31] = \ ; + assign \genr_control_regs[7] [30] = \ ; + assign \genr_control_regs[7] [29] = \ ; + assign \genr_control_regs[7] [28] = \ ; + assign \genr_control_regs[7] [27] = \ ; + assign \genr_control_regs[7] [26] = \ ; + assign \genr_control_regs[7] [25] = \ ; + assign \genr_control_regs[7] [24] = \ ; + assign \genr_control_regs[7] [23] = \ ; + assign \genr_control_regs[7] [22] = \ ; + assign \genr_control_regs[7] [21] = \ ; + assign \genr_control_regs[7] [20] = \ ; + assign \genr_control_regs[7] [19] = \ ; + assign \genr_control_regs[7] [18] = \ ; + assign \genr_control_regs[7] [17] = \ ; + assign \genr_control_regs[7] [16] = \ ; + assign \genr_control_regs[7] [15] = \ ; + assign \genr_control_regs[7] [14] = \ ; + assign \genr_control_regs[7] [13] = \ ; + assign \genr_control_regs[7] [12] = \ ; + assign \genr_control_regs[7] [11] = \ ; + assign \genr_control_regs[7] [10] = \ ; + assign \genr_control_regs[7] [9] = \ ; + assign \genr_control_regs[7] [8] = \ ; + assign \genr_control_regs[7] [7] = \ ; + assign \genr_control_regs[7] [6] = \ ; + assign \genr_control_regs[7] [5] = \ ; + assign \genr_control_regs[7] [4] = \ ; + assign \genr_control_regs[7] [3] = \ ; + assign \genr_control_regs[7] [2] = \ ; + assign \genr_control_regs[7] [1] = \ ; + assign \genr_control_regs[7] [0] = \ ; + assign ipif_cs_out = \ ; + assign ipif_data_out[31] = \ ; + assign ipif_data_out[30] = \ ; + assign ipif_data_out[29] = \ ; + assign ipif_data_out[28] = \ ; + assign ipif_data_out[27] = \ ; + assign ipif_data_out[26] = \ ; + assign ipif_data_out[25] = \ ; + assign ipif_data_out[24] = \ ; + assign ipif_data_out[23] = \ ; + assign ipif_data_out[22] = \ ; + assign ipif_data_out[21] = \ ; + assign ipif_data_out[20] = \ ; + assign ipif_data_out[19] = \ ; + assign ipif_data_out[18] = \ ; + assign ipif_data_out[17] = \ ; + assign ipif_data_out[16] = \ ; + assign ipif_data_out[15] = \ ; + assign ipif_data_out[14] = \ ; + assign ipif_data_out[13] = \ ; + assign ipif_data_out[12] = \ ; + assign ipif_data_out[11] = \ ; + assign ipif_data_out[10] = \ ; + assign ipif_data_out[9] = \ ; + assign ipif_data_out[8] = \ ; + assign ipif_data_out[7] = \ ; + assign ipif_data_out[6] = \ ; + assign ipif_data_out[5] = \ ; + assign ipif_data_out[4] = \ ; + assign ipif_data_out[3] = \ ; + assign ipif_data_out[2] = \ ; + assign ipif_data_out[1] = \ ; + assign ipif_data_out[0] = \ ; + assign ipif_rnw_out = \ ; + assign irq = \ ; + assign resetn_out = vid_aresetn; + assign s_axi_arready = \ ; + assign s_axi_awready = \ ; + assign s_axi_bresp[1] = \ ; + assign s_axi_bresp[0] = \ ; + assign s_axi_bvalid = \ ; + assign s_axi_rdata[31] = \ ; + assign s_axi_rdata[30] = \ ; + assign s_axi_rdata[29] = \ ; + assign s_axi_rdata[28] = \ ; + assign s_axi_rdata[27] = \ ; + assign s_axi_rdata[26] = \ ; + assign s_axi_rdata[25] = \ ; + assign s_axi_rdata[24] = \ ; + assign s_axi_rdata[23] = \ ; + assign s_axi_rdata[22] = \ ; + assign s_axi_rdata[21] = \ ; + assign s_axi_rdata[20] = \ ; + assign s_axi_rdata[19] = \ ; + assign s_axi_rdata[18] = \ ; + assign s_axi_rdata[17] = \ ; + assign s_axi_rdata[16] = \ ; + assign s_axi_rdata[15] = \ ; + assign s_axi_rdata[14] = \ ; + assign s_axi_rdata[13] = \ ; + assign s_axi_rdata[12] = \ ; + assign s_axi_rdata[11] = \ ; + assign s_axi_rdata[10] = \ ; + assign s_axi_rdata[9] = \ ; + assign s_axi_rdata[8] = \ ; + assign s_axi_rdata[7] = \ ; + assign s_axi_rdata[6] = \ ; + assign s_axi_rdata[5] = \ ; + assign s_axi_rdata[4] = \ ; + assign s_axi_rdata[3] = \ ; + assign s_axi_rdata[2] = \ ; + assign s_axi_rdata[1] = \ ; + assign s_axi_rdata[0] = \ ; + assign s_axi_rresp[1] = \ ; + assign s_axi_rresp[0] = \ ; + assign s_axi_rvalid = \ ; + assign s_axi_wready = \ ; + assign \time_control_regs[0] [31] = \ ; + assign \time_control_regs[0] [30] = \ ; + assign \time_control_regs[0] [29] = \ ; + assign \time_control_regs[0] [28] = \ ; + assign \time_control_regs[0] [27] = \ ; + assign \time_control_regs[0] [26] = \ ; + assign \time_control_regs[0] [25] = \ ; + assign \time_control_regs[0] [24] = \ ; + assign \time_control_regs[0] [23] = \ ; + assign \time_control_regs[0] [22] = \ ; + assign \time_control_regs[0] [21] = \ ; + assign \time_control_regs[0] [20] = \ ; + assign \time_control_regs[0] [19] = \ ; + assign \time_control_regs[0] [18] = \ ; + assign \time_control_regs[0] [17] = \ ; + assign \time_control_regs[0] [16] = \ ; + assign \time_control_regs[0] [15] = \ ; + assign \time_control_regs[0] [14] = \ ; + assign \time_control_regs[0] [13] = \ ; + assign \time_control_regs[0] [12] = \ ; + assign \time_control_regs[0] [11] = \ ; + assign \time_control_regs[0] [10] = \ ; + assign \time_control_regs[0] [9] = \ ; + assign \time_control_regs[0] [8] = \ ; + assign \time_control_regs[0] [7] = \ ; + assign \time_control_regs[0] [6] = \ ; + assign \time_control_regs[0] [5] = \ ; + assign \time_control_regs[0] [4] = \ ; + assign \time_control_regs[0] [3] = \ ; + assign \time_control_regs[0] [2] = \ ; + assign \time_control_regs[0] [1] = \ ; + assign \time_control_regs[0] [0] = \ ; + assign \time_control_regs[1] [31] = \ ; + assign \time_control_regs[1] [30] = \ ; + assign \time_control_regs[1] [29] = \ ; + assign \time_control_regs[1] [28] = \ ; + assign \time_control_regs[1] [27] = \ ; + assign \time_control_regs[1] [26] = \ ; + assign \time_control_regs[1] [25] = \ ; + assign \time_control_regs[1] [24] = \ ; + assign \time_control_regs[1] [23] = \ ; + assign \time_control_regs[1] [22] = \ ; + assign \time_control_regs[1] [21] = \ ; + assign \time_control_regs[1] [20] = \ ; + assign \time_control_regs[1] [19] = \ ; + assign \time_control_regs[1] [18] = \ ; + assign \time_control_regs[1] [17] = \ ; + assign \time_control_regs[1] [16] = \ ; + assign \time_control_regs[1] [15] = \ ; + assign \time_control_regs[1] [14] = \ ; + assign \time_control_regs[1] [13] = \ ; + assign \time_control_regs[1] [12] = \ ; + assign \time_control_regs[1] [11] = \ ; + assign \time_control_regs[1] [10] = \ ; + assign \time_control_regs[1] [9] = \ ; + assign \time_control_regs[1] [8] = \ ; + assign \time_control_regs[1] [7] = \ ; + assign \time_control_regs[1] [6] = \ ; + assign \time_control_regs[1] [5] = \ ; + assign \time_control_regs[1] [4] = \ ; + assign \time_control_regs[1] [3] = \ ; + assign \time_control_regs[1] [2] = \ ; + assign \time_control_regs[1] [1] = \ ; + assign \time_control_regs[1] [0] = \ ; + GND GND + (.G(\ )); + VCC VCC + (.P(\ )); + LUT1 #( + .INIT(2'h2)) + i_0 + (.I0(1'b0), + .O(ipif_addr_out[8])); + LUT1 #( + .INIT(2'h2)) + i_1 + (.I0(1'b0), + .O(ipif_addr_out[7])); + LUT1 #( + .INIT(2'h2)) + i_2 + (.I0(1'b0), + .O(ipif_addr_out[6])); + LUT1 #( + .INIT(2'h2)) + i_3 + (.I0(1'b0), + .O(ipif_addr_out[5])); + LUT1 #( + .INIT(2'h2)) + i_4 + (.I0(1'b0), + .O(ipif_addr_out[4])); + LUT1 #( + .INIT(2'h2)) + i_5 + (.I0(1'b0), + .O(ipif_addr_out[3])); + LUT1 #( + .INIT(2'h2)) + i_6 + (.I0(1'b0), + .O(ipif_addr_out[2])); + LUT1 #( + .INIT(2'h2)) + i_7 + (.I0(1'b0), + .O(ipif_addr_out[1])); + LUT1 #( + .INIT(2'h2)) + i_8 + (.I0(1'b0), + .O(ipif_addr_out[0])); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0_sim_netlist.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0_sim_netlist.vhdl new file mode 100644 index 0000000..d1d16da --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0_sim_netlist.vhdl @@ -0,0 +1,16305 @@ +-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +-- Date : Mon Mar 06 11:30:49 2017 +-- Host : WK73 running 64-bit Service Pack 1 (build 7601) +-- Command : write_vhdl -force -mode funcsim +-- c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0_sim_netlist.vhdl +-- Design : Arty_Z7_20_v_rgb2ycrcb_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg400-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_rgb2ycrcb_0_0_axi4s_control is + port ( + master_en : out STD_LOGIC; + eol_late_i_reg_0 : out STD_LOGIC; + sof_early_i_reg_0 : out STD_LOGIC; + sof_early_i_reg_1 : out STD_LOGIC; + da : out STD_LOGIC_VECTOR ( 1 downto 0 ); + intc_if : out STD_LOGIC_VECTOR ( 4 downto 0 ); + fifo_wr_i : out STD_LOGIC; + CO : out STD_LOGIC_VECTOR ( 0 to 0 ); + \col_cnt_reg[1]_0\ : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + wen : out STD_LOGIC; + in_fifo_reset_reg_0 : out STD_LOGIC; + \col_cnt_reg[12]_0\ : out STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + aclk : in STD_LOGIC; + \genr_control_regs[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + aclken : in STD_LOGIC; + resetn_out : in STD_LOGIC; + \write_ptr_int_reg[2]\ : in STD_LOGIC; + \time_control_regs[0]\ : in STD_LOGIC_VECTOR ( 25 downto 0 ); + \write_ptr_int_reg[2]_0\ : in STD_LOGIC; + \read_ptr_int_reg[1]\ : in STD_LOGIC; + empty_match_reg : in STD_LOGIC; + full_int_reg : in STD_LOGIC; + core_d_out : in STD_LOGIC; + vid_empty : in STD_LOGIC; + \word_count_reg[4]\ : in STD_LOGIC; + t_qb : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_rgb2ycrcb_0_0_axi4s_control : entity is "axi4s_control"; +end Arty_Z7_20_v_rgb2ycrcb_0_0_axi4s_control; + +architecture STRUCTURE of Arty_Z7_20_v_rgb2ycrcb_0_0_axi4s_control is + signal \^co\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal active_cols_2 : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal \active_cols_2[11]_i_2_n_0\ : STD_LOGIC; + signal \active_cols_2[11]_i_3_n_0\ : STD_LOGIC; + signal \active_cols_2[11]_i_4_n_0\ : STD_LOGIC; + signal \active_cols_2[11]_i_5_n_0\ : STD_LOGIC; + signal \active_cols_2[12]_i_2_n_0\ : STD_LOGIC; + signal \active_cols_2[3]_i_2_n_0\ : STD_LOGIC; + signal \active_cols_2[3]_i_3_n_0\ : STD_LOGIC; + signal \active_cols_2[3]_i_4_n_0\ : STD_LOGIC; + signal \active_cols_2[3]_i_5_n_0\ : STD_LOGIC; + signal \active_cols_2[7]_i_2_n_0\ : STD_LOGIC; + signal \active_cols_2[7]_i_3_n_0\ : STD_LOGIC; + signal \active_cols_2[7]_i_4_n_0\ : STD_LOGIC; + signal \active_cols_2[7]_i_5_n_0\ : STD_LOGIC; + signal \active_cols_2_reg[11]_i_1_n_0\ : STD_LOGIC; + signal \active_cols_2_reg[11]_i_1_n_1\ : STD_LOGIC; + signal \active_cols_2_reg[11]_i_1_n_2\ : STD_LOGIC; + signal \active_cols_2_reg[11]_i_1_n_3\ : STD_LOGIC; + signal \active_cols_2_reg[11]_i_1_n_4\ : STD_LOGIC; + signal \active_cols_2_reg[11]_i_1_n_5\ : STD_LOGIC; + signal \active_cols_2_reg[11]_i_1_n_6\ : STD_LOGIC; + signal \active_cols_2_reg[11]_i_1_n_7\ : STD_LOGIC; + signal \active_cols_2_reg[12]_i_1_n_7\ : STD_LOGIC; + signal \active_cols_2_reg[3]_i_1_n_0\ : STD_LOGIC; + signal \active_cols_2_reg[3]_i_1_n_1\ : STD_LOGIC; + signal \active_cols_2_reg[3]_i_1_n_2\ : STD_LOGIC; + signal \active_cols_2_reg[3]_i_1_n_3\ : STD_LOGIC; + signal \active_cols_2_reg[3]_i_1_n_4\ : STD_LOGIC; + signal \active_cols_2_reg[3]_i_1_n_5\ : STD_LOGIC; + signal \active_cols_2_reg[3]_i_1_n_6\ : STD_LOGIC; + signal \active_cols_2_reg[3]_i_1_n_7\ : STD_LOGIC; + signal \active_cols_2_reg[7]_i_1_n_0\ : STD_LOGIC; + signal \active_cols_2_reg[7]_i_1_n_1\ : STD_LOGIC; + signal \active_cols_2_reg[7]_i_1_n_2\ : STD_LOGIC; + signal \active_cols_2_reg[7]_i_1_n_3\ : STD_LOGIC; + signal \active_cols_2_reg[7]_i_1_n_4\ : STD_LOGIC; + signal \active_cols_2_reg[7]_i_1_n_5\ : STD_LOGIC; + signal \active_cols_2_reg[7]_i_1_n_6\ : STD_LOGIC; + signal \active_cols_2_reg[7]_i_1_n_7\ : STD_LOGIC; + signal \col_cnt[0]_i_1_n_0\ : STD_LOGIC; + signal \col_cnt[0]_i_2_n_0\ : STD_LOGIC; + signal \col_cnt[10]_i_1_n_0\ : STD_LOGIC; + signal \col_cnt[11]_i_1_n_0\ : STD_LOGIC; + signal \col_cnt[12]_i_15_n_0\ : STD_LOGIC; + signal \col_cnt[12]_i_16_n_0\ : STD_LOGIC; + signal \col_cnt[12]_i_17_n_0\ : STD_LOGIC; + signal \col_cnt[12]_i_18_n_0\ : STD_LOGIC; + signal \col_cnt[12]_i_19_n_0\ : STD_LOGIC; + signal \col_cnt[12]_i_1_n_0\ : STD_LOGIC; + signal \col_cnt[12]_i_20_n_0\ : STD_LOGIC; + signal \col_cnt[12]_i_3_n_0\ : STD_LOGIC; + signal \col_cnt[12]_i_4_n_0\ : STD_LOGIC; + signal \col_cnt[1]_i_1_n_0\ : STD_LOGIC; + signal \col_cnt[1]_i_2_n_0\ : STD_LOGIC; + signal \col_cnt[1]_i_3_n_0\ : STD_LOGIC; + signal \col_cnt[1]_i_4_n_0\ : STD_LOGIC; + signal \col_cnt[2]_i_1_n_0\ : STD_LOGIC; + signal \col_cnt[2]_i_2_n_0\ : STD_LOGIC; + signal \col_cnt[2]_i_3_n_0\ : STD_LOGIC; + signal \col_cnt[3]_i_1_n_0\ : STD_LOGIC; + signal \col_cnt[4]_i_1_n_0\ : STD_LOGIC; + signal \col_cnt[4]_i_3_n_0\ : STD_LOGIC; + signal \col_cnt[4]_i_4_n_0\ : STD_LOGIC; + signal \col_cnt[4]_i_5_n_0\ : STD_LOGIC; + signal \col_cnt[4]_i_6_n_0\ : STD_LOGIC; + signal \col_cnt[5]_i_1_n_0\ : STD_LOGIC; + signal \col_cnt[6]_i_1_n_0\ : STD_LOGIC; + signal \col_cnt[7]_i_1_n_0\ : STD_LOGIC; + signal \col_cnt[8]_i_1_n_0\ : STD_LOGIC; + signal \col_cnt[8]_i_3_n_0\ : STD_LOGIC; + signal \col_cnt[8]_i_4_n_0\ : STD_LOGIC; + signal \col_cnt[8]_i_5_n_0\ : STD_LOGIC; + signal \col_cnt[8]_i_6_n_0\ : STD_LOGIC; + signal \col_cnt[9]_i_1_n_0\ : STD_LOGIC; + signal \col_cnt_reg[12]_i_9_n_1\ : STD_LOGIC; + signal \col_cnt_reg[12]_i_9_n_2\ : STD_LOGIC; + signal \col_cnt_reg[12]_i_9_n_3\ : STD_LOGIC; + signal \^col_cnt_reg[1]_0\ : STD_LOGIC; + signal \col_cnt_reg[4]_i_2_n_0\ : STD_LOGIC; + signal \col_cnt_reg[4]_i_2_n_1\ : STD_LOGIC; + signal \col_cnt_reg[4]_i_2_n_2\ : STD_LOGIC; + signal \col_cnt_reg[4]_i_2_n_3\ : STD_LOGIC; + signal \col_cnt_reg[8]_i_2_n_0\ : STD_LOGIC; + signal \col_cnt_reg[8]_i_2_n_1\ : STD_LOGIC; + signal \col_cnt_reg[8]_i_2_n_2\ : STD_LOGIC; + signal \col_cnt_reg[8]_i_2_n_3\ : STD_LOGIC; + signal \col_cnt_reg_n_0_[0]\ : STD_LOGIC; + signal \col_cnt_reg_n_0_[10]\ : STD_LOGIC; + signal \col_cnt_reg_n_0_[11]\ : STD_LOGIC; + signal \col_cnt_reg_n_0_[12]\ : STD_LOGIC; + signal \col_cnt_reg_n_0_[1]\ : STD_LOGIC; + signal \col_cnt_reg_n_0_[2]\ : STD_LOGIC; + signal \col_cnt_reg_n_0_[3]\ : STD_LOGIC; + signal \col_cnt_reg_n_0_[4]\ : STD_LOGIC; + signal \col_cnt_reg_n_0_[5]\ : STD_LOGIC; + signal \col_cnt_reg_n_0_[6]\ : STD_LOGIC; + signal \col_cnt_reg_n_0_[7]\ : STD_LOGIC; + signal \col_cnt_reg_n_0_[8]\ : STD_LOGIC; + signal \col_cnt_reg_n_0_[9]\ : STD_LOGIC; + signal core_en_i : STD_LOGIC; + signal core_en_i_i_1_n_0 : STD_LOGIC; + signal data1 : STD_LOGIC_VECTOR ( 12 downto 1 ); + signal eof_i_i_1_n_0 : STD_LOGIC; + signal eol_early_i0 : STD_LOGIC; + signal eol_early_i_i_1_n_0 : STD_LOGIC; + signal eol_early_i_i_4_n_0 : STD_LOGIC; + signal eol_expected : STD_LOGIC; + signal eol_expected0 : STD_LOGIC; + signal eol_expected_d : STD_LOGIC; + signal eol_expected_d_i_1_n_0 : STD_LOGIC; + signal eol_late_i3_out : STD_LOGIC; + signal eol_late_i_i_2_n_0 : STD_LOGIC; + signal eol_late_i_i_3_n_0 : STD_LOGIC; + signal \^eol_late_i_reg_0\ : STD_LOGIC; + signal eqOp : STD_LOGIC; + signal eqOp0_out : STD_LOGIC; + signal eqOp1_out : STD_LOGIC; + signal eqOp_0 : STD_LOGIC; + signal \eqOp_carry__0_i_1_n_0\ : STD_LOGIC; + signal eqOp_carry_i_1_n_0 : STD_LOGIC; + signal eqOp_carry_i_2_n_0 : STD_LOGIC; + signal eqOp_carry_i_3_n_0 : STD_LOGIC; + signal eqOp_carry_i_4_n_0 : STD_LOGIC; + signal eqOp_carry_n_0 : STD_LOGIC; + signal eqOp_carry_n_1 : STD_LOGIC; + signal eqOp_carry_n_2 : STD_LOGIC; + signal eqOp_carry_n_3 : STD_LOGIC; + signal \eqOp_inferred__3/i__carry_n_0\ : STD_LOGIC; + signal \eqOp_inferred__3/i__carry_n_1\ : STD_LOGIC; + signal \eqOp_inferred__3/i__carry_n_2\ : STD_LOGIC; + signal \eqOp_inferred__3/i__carry_n_3\ : STD_LOGIC; + signal \eqOp_inferred__4/i__carry_n_0\ : STD_LOGIC; + signal \eqOp_inferred__4/i__carry_n_1\ : STD_LOGIC; + signal \eqOp_inferred__4/i__carry_n_2\ : STD_LOGIC; + signal \eqOp_inferred__4/i__carry_n_3\ : STD_LOGIC; + signal fifo_rd_d : STD_LOGIC; + signal fifo_rd_d_i_1_n_0 : STD_LOGIC; + signal fifo_rd_i : STD_LOGIC; + signal fifo_rd_i0 : STD_LOGIC; + signal fifo_rd_i_i_1_n_0 : STD_LOGIC; + signal \^fifo_wr_i\ : STD_LOGIC; + signal fifo_wr_i_i_10_n_0 : STD_LOGIC; + signal fifo_wr_i_i_11_n_0 : STD_LOGIC; + signal fifo_wr_i_i_12_n_0 : STD_LOGIC; + signal fifo_wr_i_i_13_n_0 : STD_LOGIC; + signal fifo_wr_i_i_14_n_0 : STD_LOGIC; + signal fifo_wr_i_i_1_n_0 : STD_LOGIC; + signal fifo_wr_i_i_4_n_0 : STD_LOGIC; + signal fifo_wr_i_i_5_n_0 : STD_LOGIC; + signal fifo_wr_i_i_6_n_0 : STD_LOGIC; + signal fifo_wr_i_i_7_n_0 : STD_LOGIC; + signal fifo_wr_i_i_8_n_0 : STD_LOGIC; + signal fifo_wr_i_i_9_n_0 : STD_LOGIC; + signal fifo_wr_i_reg_i_2_n_2 : STD_LOGIC; + signal fifo_wr_i_reg_i_2_n_3 : STD_LOGIC; + signal fifo_wr_i_reg_i_3_n_0 : STD_LOGIC; + signal fifo_wr_i_reg_i_3_n_1 : STD_LOGIC; + signal fifo_wr_i_reg_i_3_n_2 : STD_LOGIC; + signal fifo_wr_i_reg_i_3_n_3 : STD_LOGIC; + signal geqOp : STD_LOGIC; + signal \geqOp_carry__0_i_1_n_0\ : STD_LOGIC; + signal \geqOp_carry__0_i_2_n_0\ : STD_LOGIC; + signal \geqOp_carry__0_i_3_n_0\ : STD_LOGIC; + signal \geqOp_carry__0_i_4_n_0\ : STD_LOGIC; + signal \geqOp_carry__0_i_5_n_0\ : STD_LOGIC; + signal \geqOp_carry__0_i_6_n_0\ : STD_LOGIC; + signal \geqOp_carry__0_n_2\ : STD_LOGIC; + signal \geqOp_carry__0_n_3\ : STD_LOGIC; + signal geqOp_carry_i_1_n_0 : STD_LOGIC; + signal geqOp_carry_i_2_n_0 : STD_LOGIC; + signal geqOp_carry_i_3_n_0 : STD_LOGIC; + signal geqOp_carry_i_4_n_0 : STD_LOGIC; + signal geqOp_carry_i_5_n_0 : STD_LOGIC; + signal geqOp_carry_i_6_n_0 : STD_LOGIC; + signal geqOp_carry_i_7_n_0 : STD_LOGIC; + signal geqOp_carry_i_8_n_0 : STD_LOGIC; + signal geqOp_carry_n_0 : STD_LOGIC; + signal geqOp_carry_n_1 : STD_LOGIC; + signal geqOp_carry_n_2 : STD_LOGIC; + signal geqOp_carry_n_3 : STD_LOGIC; + signal gtOp : STD_LOGIC; + signal gtOp18_in : STD_LOGIC; + signal gtOp19_in : STD_LOGIC; + signal gtOp21_in : STD_LOGIC; + signal gtOp22_in : STD_LOGIC; + signal \gtOp_carry__0_i_1_n_0\ : STD_LOGIC; + signal \gtOp_carry__0_i_2_n_0\ : STD_LOGIC; + signal \gtOp_carry__0_i_3_n_0\ : STD_LOGIC; + signal \gtOp_carry__0_i_4_n_0\ : STD_LOGIC; + signal \gtOp_carry__0_i_5_n_0\ : STD_LOGIC; + signal \gtOp_carry__0_i_6_n_0\ : STD_LOGIC; + signal \gtOp_carry__0_n_2\ : STD_LOGIC; + signal \gtOp_carry__0_n_3\ : STD_LOGIC; + signal gtOp_carry_i_1_n_0 : STD_LOGIC; + signal gtOp_carry_i_2_n_0 : STD_LOGIC; + signal gtOp_carry_i_3_n_0 : STD_LOGIC; + signal gtOp_carry_i_4_n_0 : STD_LOGIC; + signal gtOp_carry_i_5_n_0 : STD_LOGIC; + signal gtOp_carry_i_6_n_0 : STD_LOGIC; + signal gtOp_carry_i_7_n_0 : STD_LOGIC; + signal gtOp_carry_i_8_n_0 : STD_LOGIC; + signal gtOp_carry_n_0 : STD_LOGIC; + signal gtOp_carry_n_1 : STD_LOGIC; + signal gtOp_carry_n_2 : STD_LOGIC; + signal gtOp_carry_n_3 : STD_LOGIC; + signal \gtOp_inferred__0/i__carry__0_n_2\ : STD_LOGIC; + signal \gtOp_inferred__0/i__carry__0_n_3\ : STD_LOGIC; + signal \gtOp_inferred__0/i__carry_n_0\ : STD_LOGIC; + signal \gtOp_inferred__0/i__carry_n_1\ : STD_LOGIC; + signal \gtOp_inferred__0/i__carry_n_2\ : STD_LOGIC; + signal \gtOp_inferred__0/i__carry_n_3\ : STD_LOGIC; + signal \gtOp_inferred__2/i__carry__0_n_2\ : STD_LOGIC; + signal \gtOp_inferred__2/i__carry__0_n_3\ : STD_LOGIC; + signal \gtOp_inferred__2/i__carry_n_0\ : STD_LOGIC; + signal \gtOp_inferred__2/i__carry_n_1\ : STD_LOGIC; + signal \gtOp_inferred__2/i__carry_n_2\ : STD_LOGIC; + signal \gtOp_inferred__2/i__carry_n_3\ : STD_LOGIC; + signal \gtOp_inferred__3/i__carry__0_n_2\ : STD_LOGIC; + signal \gtOp_inferred__3/i__carry__0_n_3\ : STD_LOGIC; + signal \gtOp_inferred__3/i__carry_n_0\ : STD_LOGIC; + signal \gtOp_inferred__3/i__carry_n_1\ : STD_LOGIC; + signal \gtOp_inferred__3/i__carry_n_2\ : STD_LOGIC; + signal \gtOp_inferred__3/i__carry_n_3\ : STD_LOGIC; + signal \i__carry__0_i_1__0_n_0\ : STD_LOGIC; + signal \i__carry__0_i_1__1_n_0\ : STD_LOGIC; + signal \i__carry__0_i_1__2_n_0\ : STD_LOGIC; + signal \i__carry__0_i_1__3_n_0\ : STD_LOGIC; + signal \i__carry__0_i_1__4_n_0\ : STD_LOGIC; + signal \i__carry__0_i_1__5_n_0\ : STD_LOGIC; + signal \i__carry__0_i_1__6_n_0\ : STD_LOGIC; + signal \i__carry__0_i_1_n_0\ : STD_LOGIC; + signal \i__carry__0_i_2__0_n_0\ : STD_LOGIC; + signal \i__carry__0_i_2__1_n_0\ : STD_LOGIC; + signal \i__carry__0_i_2__2_n_0\ : STD_LOGIC; + signal \i__carry__0_i_2__3_n_0\ : STD_LOGIC; + signal \i__carry__0_i_2__4_n_0\ : STD_LOGIC; + signal \i__carry__0_i_2_n_0\ : STD_LOGIC; + signal \i__carry__0_i_3__0_n_0\ : STD_LOGIC; + signal \i__carry__0_i_3__1_n_0\ : STD_LOGIC; + signal \i__carry__0_i_3__2_n_0\ : STD_LOGIC; + signal \i__carry__0_i_3__3_n_0\ : STD_LOGIC; + signal \i__carry__0_i_3_n_0\ : STD_LOGIC; + signal \i__carry__0_i_4__0_n_0\ : STD_LOGIC; + signal \i__carry__0_i_4__1_n_0\ : STD_LOGIC; + signal \i__carry__0_i_4__2_n_0\ : STD_LOGIC; + signal \i__carry__0_i_4__3_n_0\ : STD_LOGIC; + signal \i__carry__0_i_4_n_0\ : STD_LOGIC; + signal \i__carry__0_i_5__0_n_0\ : STD_LOGIC; + signal \i__carry__0_i_5__1_n_0\ : STD_LOGIC; + signal \i__carry__0_i_5__2_n_0\ : STD_LOGIC; + signal \i__carry__0_i_5__3_n_0\ : STD_LOGIC; + signal \i__carry__0_i_5_n_0\ : STD_LOGIC; + signal \i__carry__0_i_6__0_n_0\ : STD_LOGIC; + signal \i__carry__0_i_6__1_n_0\ : STD_LOGIC; + signal \i__carry__0_i_6_n_0\ : STD_LOGIC; + signal \i__carry_i_1__0_n_0\ : STD_LOGIC; + signal \i__carry_i_1__1_n_0\ : STD_LOGIC; + signal \i__carry_i_1__2_n_0\ : STD_LOGIC; + signal \i__carry_i_1__3_n_0\ : STD_LOGIC; + signal \i__carry_i_1__4_n_0\ : STD_LOGIC; + signal \i__carry_i_1__5_n_0\ : STD_LOGIC; + signal \i__carry_i_1__6_n_0\ : STD_LOGIC; + signal \i__carry_i_1_n_0\ : STD_LOGIC; + signal \i__carry_i_2__0_n_0\ : STD_LOGIC; + signal \i__carry_i_2__1_n_0\ : STD_LOGIC; + signal \i__carry_i_2__2_n_0\ : STD_LOGIC; + signal \i__carry_i_2__3_n_0\ : STD_LOGIC; + signal \i__carry_i_2__4_n_0\ : STD_LOGIC; + signal \i__carry_i_2__5_n_0\ : STD_LOGIC; + signal \i__carry_i_2__6_n_0\ : STD_LOGIC; + signal \i__carry_i_2_n_0\ : STD_LOGIC; + signal \i__carry_i_3__0_n_0\ : STD_LOGIC; + signal \i__carry_i_3__1_n_0\ : STD_LOGIC; + signal \i__carry_i_3__2_n_0\ : STD_LOGIC; + signal \i__carry_i_3__3_n_0\ : STD_LOGIC; + signal \i__carry_i_3__4_n_0\ : STD_LOGIC; + signal \i__carry_i_3__5_n_0\ : STD_LOGIC; + signal \i__carry_i_3__6_n_0\ : STD_LOGIC; + signal \i__carry_i_3_n_0\ : STD_LOGIC; + signal \i__carry_i_4__0_n_0\ : STD_LOGIC; + signal \i__carry_i_4__1_n_0\ : STD_LOGIC; + signal \i__carry_i_4__2_n_0\ : STD_LOGIC; + signal \i__carry_i_4__3_n_0\ : STD_LOGIC; + signal \i__carry_i_4__4_n_0\ : STD_LOGIC; + signal \i__carry_i_4__5_n_0\ : STD_LOGIC; + signal \i__carry_i_4__6_n_0\ : STD_LOGIC; + signal \i__carry_i_4_n_0\ : STD_LOGIC; + signal \i__carry_i_5__0_n_0\ : STD_LOGIC; + signal \i__carry_i_5__1_n_0\ : STD_LOGIC; + signal \i__carry_i_5__2_n_0\ : STD_LOGIC; + signal \i__carry_i_5__3_n_0\ : STD_LOGIC; + signal \i__carry_i_5__4_n_0\ : STD_LOGIC; + signal \i__carry_i_5_n_0\ : STD_LOGIC; + signal \i__carry_i_6__0_n_0\ : STD_LOGIC; + signal \i__carry_i_6__1_n_0\ : STD_LOGIC; + signal \i__carry_i_6__2_n_0\ : STD_LOGIC; + signal \i__carry_i_6__3_n_0\ : STD_LOGIC; + signal \i__carry_i_6_n_0\ : STD_LOGIC; + signal \i__carry_i_7__0_n_0\ : STD_LOGIC; + signal \i__carry_i_7__1_n_0\ : STD_LOGIC; + signal \i__carry_i_7__2_n_0\ : STD_LOGIC; + signal \i__carry_i_7__3_n_0\ : STD_LOGIC; + signal \i__carry_i_7_n_0\ : STD_LOGIC; + signal \i__carry_i_8__0_n_0\ : STD_LOGIC; + signal \i__carry_i_8__1_n_0\ : STD_LOGIC; + signal \i__carry_i_8__2_n_0\ : STD_LOGIC; + signal \i__carry_i_8_n_0\ : STD_LOGIC; + signal in_fifo_reset : STD_LOGIC; + signal in_fifo_reset0 : STD_LOGIC; + signal in_fifo_reset_i_3_n_0 : STD_LOGIC; + signal \^in_fifo_reset_reg_0\ : STD_LOGIC; + signal \^intc_if\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal leqOp16_in : STD_LOGIC; + signal leqOp20_in : STD_LOGIC; + signal leqOp23_in : STD_LOGIC; + signal \leqOp_carry__0_i_1_n_0\ : STD_LOGIC; + signal \leqOp_carry__0_i_2_n_0\ : STD_LOGIC; + signal \leqOp_carry__0_i_3_n_0\ : STD_LOGIC; + signal \leqOp_carry__0_i_4_n_0\ : STD_LOGIC; + signal \leqOp_carry__0_i_5_n_0\ : STD_LOGIC; + signal \leqOp_carry__0_i_6_n_0\ : STD_LOGIC; + signal \leqOp_carry__0_n_2\ : STD_LOGIC; + signal \leqOp_carry__0_n_3\ : STD_LOGIC; + signal leqOp_carry_i_1_n_0 : STD_LOGIC; + signal leqOp_carry_i_2_n_0 : STD_LOGIC; + signal leqOp_carry_i_3_n_0 : STD_LOGIC; + signal leqOp_carry_i_4_n_0 : STD_LOGIC; + signal leqOp_carry_i_5_n_0 : STD_LOGIC; + signal leqOp_carry_i_6_n_0 : STD_LOGIC; + signal leqOp_carry_i_7_n_0 : STD_LOGIC; + signal leqOp_carry_i_8_n_0 : STD_LOGIC; + signal leqOp_carry_n_0 : STD_LOGIC; + signal leqOp_carry_n_1 : STD_LOGIC; + signal leqOp_carry_n_2 : STD_LOGIC; + signal leqOp_carry_n_3 : STD_LOGIC; + signal \leqOp_inferred__0/i__carry__0_n_2\ : STD_LOGIC; + signal \leqOp_inferred__0/i__carry__0_n_3\ : STD_LOGIC; + signal \leqOp_inferred__0/i__carry_n_0\ : STD_LOGIC; + signal \leqOp_inferred__0/i__carry_n_1\ : STD_LOGIC; + signal \leqOp_inferred__0/i__carry_n_2\ : STD_LOGIC; + signal \leqOp_inferred__0/i__carry_n_3\ : STD_LOGIC; + signal \leqOp_inferred__1/i__carry__0_n_2\ : STD_LOGIC; + signal \leqOp_inferred__1/i__carry__0_n_3\ : STD_LOGIC; + signal \leqOp_inferred__1/i__carry_n_0\ : STD_LOGIC; + signal \leqOp_inferred__1/i__carry_n_1\ : STD_LOGIC; + signal \leqOp_inferred__1/i__carry_n_2\ : STD_LOGIC; + signal \leqOp_inferred__1/i__carry_n_3\ : STD_LOGIC; + signal line_cnt_tc_i_1_n_0 : STD_LOGIC; + signal line_cnt_tc_i_2_n_0 : STD_LOGIC; + signal line_cnt_tc_i_3_n_0 : STD_LOGIC; + signal line_cnt_tc_i_4_n_0 : STD_LOGIC; + signal line_cnt_tc_i_5_n_0 : STD_LOGIC; + signal line_cnt_tc_i_6_n_0 : STD_LOGIC; + signal \ltOp_carry__0_i_1_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_2_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_3_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_4_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_5_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_6_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_1\ : STD_LOGIC; + signal \ltOp_carry__0_n_2\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal \ltOp_inferred__0/i__carry__0_n_3\ : STD_LOGIC; + signal \ltOp_inferred__0/i__carry_n_0\ : STD_LOGIC; + signal \ltOp_inferred__0/i__carry_n_1\ : STD_LOGIC; + signal \ltOp_inferred__0/i__carry_n_2\ : STD_LOGIC; + signal \ltOp_inferred__0/i__carry_n_3\ : STD_LOGIC; + signal \^master_en\ : STD_LOGIC; + signal out_fifo_sof0 : STD_LOGIC; + signal out_fifo_sof_i_2_n_0 : STD_LOGIC; + signal pixel_cnt_tc_i_1_n_0 : STD_LOGIC; + signal pixel_cnt_tc_i_3_n_0 : STD_LOGIC; + signal pixel_cnt_tc_i_4_n_0 : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal row_cnt : STD_LOGIC; + signal \row_cnt[0]_i_1_n_0\ : STD_LOGIC; + signal \row_cnt[0]_i_4_n_0\ : STD_LOGIC; + signal \row_cnt[0]_i_5_n_0\ : STD_LOGIC; + signal \row_cnt[0]_i_6_n_0\ : STD_LOGIC; + signal \row_cnt[0]_i_7_n_0\ : STD_LOGIC; + signal \row_cnt[0]_i_8_n_0\ : STD_LOGIC; + signal \row_cnt[12]_i_2_n_0\ : STD_LOGIC; + signal \row_cnt[4]_i_2_n_0\ : STD_LOGIC; + signal \row_cnt[4]_i_3_n_0\ : STD_LOGIC; + signal \row_cnt[4]_i_4_n_0\ : STD_LOGIC; + signal \row_cnt[4]_i_5_n_0\ : STD_LOGIC; + signal \row_cnt[8]_i_2_n_0\ : STD_LOGIC; + signal \row_cnt[8]_i_3_n_0\ : STD_LOGIC; + signal \row_cnt[8]_i_4_n_0\ : STD_LOGIC; + signal \row_cnt[8]_i_5_n_0\ : STD_LOGIC; + signal row_cnt_reg : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal \row_cnt_reg[0]_i_3_n_0\ : STD_LOGIC; + signal \row_cnt_reg[0]_i_3_n_1\ : STD_LOGIC; + signal \row_cnt_reg[0]_i_3_n_2\ : STD_LOGIC; + signal \row_cnt_reg[0]_i_3_n_3\ : STD_LOGIC; + signal \row_cnt_reg[0]_i_3_n_4\ : STD_LOGIC; + signal \row_cnt_reg[0]_i_3_n_5\ : STD_LOGIC; + signal \row_cnt_reg[0]_i_3_n_6\ : STD_LOGIC; + signal \row_cnt_reg[0]_i_3_n_7\ : STD_LOGIC; + signal \row_cnt_reg[12]_i_1_n_7\ : STD_LOGIC; + signal \row_cnt_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \row_cnt_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \row_cnt_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \row_cnt_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \row_cnt_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \row_cnt_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \row_cnt_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \row_cnt_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \row_cnt_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \row_cnt_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \row_cnt_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \row_cnt_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \row_cnt_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \row_cnt_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \row_cnt_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \row_cnt_reg[8]_i_1_n_7\ : STD_LOGIC; + signal sof_early_i_i_1_n_0 : STD_LOGIC; + signal \^sof_early_i_reg_0\ : STD_LOGIC; + signal \^sof_early_i_reg_1\ : STD_LOGIC; + signal sof_expected : STD_LOGIC; + signal sof_expected0 : STD_LOGIC; + signal sof_expected_i_2_n_0 : STD_LOGIC; + signal sof_expected_i_3_n_0 : STD_LOGIC; + signal sof_expected_i_4_n_0 : STD_LOGIC; + signal sof_expected_i_5_n_0 : STD_LOGIC; + signal sof_expected_i_6_n_0 : STD_LOGIC; + signal sof_expected_i_7_n_0 : STD_LOGIC; + signal sof_expected_i_8_n_0 : STD_LOGIC; + signal sof_expected_i_9_n_0 : STD_LOGIC; + signal sof_late_i2_out : STD_LOGIC; + signal total_cols : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal \total_cols[12]_i_2_n_0\ : STD_LOGIC; + signal \total_cols[12]_i_3_n_0\ : STD_LOGIC; + signal \total_cols[12]_i_4_n_0\ : STD_LOGIC; + signal \total_cols[12]_i_5_n_0\ : STD_LOGIC; + signal \total_cols[4]_i_2_n_0\ : STD_LOGIC; + signal \total_cols[4]_i_3_n_0\ : STD_LOGIC; + signal \total_cols[4]_i_4_n_0\ : STD_LOGIC; + signal \total_cols[4]_i_5_n_0\ : STD_LOGIC; + signal \total_cols[8]_i_2_n_0\ : STD_LOGIC; + signal \total_cols[8]_i_3_n_0\ : STD_LOGIC; + signal \total_cols[8]_i_4_n_0\ : STD_LOGIC; + signal \total_cols[8]_i_5_n_0\ : STD_LOGIC; + signal \total_cols_reg[12]_i_1_n_1\ : STD_LOGIC; + signal \total_cols_reg[12]_i_1_n_2\ : STD_LOGIC; + signal \total_cols_reg[12]_i_1_n_3\ : STD_LOGIC; + signal \total_cols_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \total_cols_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \total_cols_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \total_cols_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \total_cols_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \total_cols_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \total_cols_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \total_cols_reg[8]_i_1_n_3\ : STD_LOGIC; + signal total_rows : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal \NLW_active_cols_2_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_active_cols_2_reg[12]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_col_cnt_reg[12]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal NLW_eqOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_eqOp_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_eqOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_eqOp_inferred__3/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_eqOp_inferred__3/i__carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_eqOp_inferred__3/i__carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_eqOp_inferred__4/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_eqOp_inferred__4/i__carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_eqOp_inferred__4/i__carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_wr_i_reg_i_2_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 to 3 ); + signal NLW_fifo_wr_i_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_fifo_wr_i_reg_i_3_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_geqOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_geqOp_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_geqOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_gtOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gtOp_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_gtOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gtOp_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gtOp_inferred__0/i__carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_gtOp_inferred__0/i__carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gtOp_inferred__2/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gtOp_inferred__2/i__carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_gtOp_inferred__2/i__carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gtOp_inferred__3/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gtOp_inferred__3/i__carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_gtOp_inferred__3/i__carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_leqOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_leqOp_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_leqOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_leqOp_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_leqOp_inferred__0/i__carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_leqOp_inferred__0/i__carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_leqOp_inferred__1/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_leqOp_inferred__1/i__carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_leqOp_inferred__1/i__carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_inferred__0/i__carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_ltOp_inferred__0/i__carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_row_cnt_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_row_cnt_reg[12]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_total_cols_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \col_cnt[2]_i_1\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \col_cnt[2]_i_3\ : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of eol_early_i_i_3 : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of eol_early_i_i_4 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of eol_expected_i_1 : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of eol_late_i_i_2 : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of eol_late_i_i_3 : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of fifo_rd_d_i_1 : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of in_fifo_reset_i_1 : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of in_fifo_reset_i_3 : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of out_fifo_sof_i_2 : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of pixel_cnt_tc_i_4 : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of sof_expected_i_8 : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of sof_late_i_i_3 : label is "soft_lutpair1"; +begin + CO(0) <= \^co\(0); + \col_cnt_reg[1]_0\ <= \^col_cnt_reg[1]_0\; + eol_late_i_reg_0 <= \^eol_late_i_reg_0\; + fifo_wr_i <= \^fifo_wr_i\; + in_fifo_reset_reg_0 <= \^in_fifo_reset_reg_0\; + intc_if(4 downto 0) <= \^intc_if\(4 downto 0); + master_en <= \^master_en\; + sof_early_i_reg_0 <= \^sof_early_i_reg_0\; + sof_early_i_reg_1 <= \^sof_early_i_reg_1\; +\GenerateDoutWriteFirstA.mem_reg_0_15_0_5_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000800000000" + ) + port map ( + I0 => aclken, + I1 => \genr_control_regs[0]\(0), + I2 => \^eol_late_i_reg_0\, + I3 => full_int_reg, + I4 => core_d_out, + I5 => \^fifo_wr_i\, + O => wen + ); +\active_cols_2[11]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \time_control_regs[0]\(11), + O => \active_cols_2[11]_i_2_n_0\ + ); +\active_cols_2[11]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \time_control_regs[0]\(10), + O => \active_cols_2[11]_i_3_n_0\ + ); +\active_cols_2[11]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \time_control_regs[0]\(9), + O => \active_cols_2[11]_i_4_n_0\ + ); +\active_cols_2[11]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \time_control_regs[0]\(8), + O => \active_cols_2[11]_i_5_n_0\ + ); +\active_cols_2[12]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \time_control_regs[0]\(12), + O => \active_cols_2[12]_i_2_n_0\ + ); +\active_cols_2[3]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \time_control_regs[0]\(3), + O => \active_cols_2[3]_i_2_n_0\ + ); +\active_cols_2[3]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \time_control_regs[0]\(2), + O => \active_cols_2[3]_i_3_n_0\ + ); +\active_cols_2[3]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \time_control_regs[0]\(1), + O => \active_cols_2[3]_i_4_n_0\ + ); +\active_cols_2[3]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \time_control_regs[0]\(0), + O => \active_cols_2[3]_i_5_n_0\ + ); +\active_cols_2[7]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \time_control_regs[0]\(7), + O => \active_cols_2[7]_i_2_n_0\ + ); +\active_cols_2[7]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \time_control_regs[0]\(6), + O => \active_cols_2[7]_i_3_n_0\ + ); +\active_cols_2[7]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \time_control_regs[0]\(5), + O => \active_cols_2[7]_i_4_n_0\ + ); +\active_cols_2[7]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \time_control_regs[0]\(4), + O => \active_cols_2[7]_i_5_n_0\ + ); +\active_cols_2_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \active_cols_2_reg[3]_i_1_n_7\, + Q => active_cols_2(0), + R => '0' + ); +\active_cols_2_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \active_cols_2_reg[11]_i_1_n_5\, + Q => active_cols_2(10), + R => '0' + ); +\active_cols_2_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \active_cols_2_reg[11]_i_1_n_4\, + Q => active_cols_2(11), + R => '0' + ); +\active_cols_2_reg[11]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \active_cols_2_reg[7]_i_1_n_0\, + CO(3) => \active_cols_2_reg[11]_i_1_n_0\, + CO(2) => \active_cols_2_reg[11]_i_1_n_1\, + CO(1) => \active_cols_2_reg[11]_i_1_n_2\, + CO(0) => \active_cols_2_reg[11]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \active_cols_2_reg[11]_i_1_n_4\, + O(2) => \active_cols_2_reg[11]_i_1_n_5\, + O(1) => \active_cols_2_reg[11]_i_1_n_6\, + O(0) => \active_cols_2_reg[11]_i_1_n_7\, + S(3) => \active_cols_2[11]_i_2_n_0\, + S(2) => \active_cols_2[11]_i_3_n_0\, + S(1) => \active_cols_2[11]_i_4_n_0\, + S(0) => \active_cols_2[11]_i_5_n_0\ + ); +\active_cols_2_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \active_cols_2_reg[12]_i_1_n_7\, + Q => active_cols_2(12), + R => '0' + ); +\active_cols_2_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \active_cols_2_reg[11]_i_1_n_0\, + CO(3 downto 0) => \NLW_active_cols_2_reg[12]_i_1_CO_UNCONNECTED\(3 downto 0), + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 1) => \NLW_active_cols_2_reg[12]_i_1_O_UNCONNECTED\(3 downto 1), + O(0) => \active_cols_2_reg[12]_i_1_n_7\, + S(3 downto 1) => B"000", + S(0) => \active_cols_2[12]_i_2_n_0\ + ); +\active_cols_2_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \active_cols_2_reg[3]_i_1_n_6\, + Q => active_cols_2(1), + R => '0' + ); +\active_cols_2_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \active_cols_2_reg[3]_i_1_n_5\, + Q => active_cols_2(2), + R => '0' + ); +\active_cols_2_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \active_cols_2_reg[3]_i_1_n_4\, + Q => active_cols_2(3), + R => '0' + ); +\active_cols_2_reg[3]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \active_cols_2_reg[3]_i_1_n_0\, + CO(2) => \active_cols_2_reg[3]_i_1_n_1\, + CO(1) => \active_cols_2_reg[3]_i_1_n_2\, + CO(0) => \active_cols_2_reg[3]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1) => \time_control_regs[0]\(1), + DI(0) => '0', + O(3) => \active_cols_2_reg[3]_i_1_n_4\, + O(2) => \active_cols_2_reg[3]_i_1_n_5\, + O(1) => \active_cols_2_reg[3]_i_1_n_6\, + O(0) => \active_cols_2_reg[3]_i_1_n_7\, + S(3) => \active_cols_2[3]_i_2_n_0\, + S(2) => \active_cols_2[3]_i_3_n_0\, + S(1) => \active_cols_2[3]_i_4_n_0\, + S(0) => \active_cols_2[3]_i_5_n_0\ + ); +\active_cols_2_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \active_cols_2_reg[7]_i_1_n_7\, + Q => active_cols_2(4), + R => '0' + ); +\active_cols_2_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \active_cols_2_reg[7]_i_1_n_6\, + Q => active_cols_2(5), + R => '0' + ); +\active_cols_2_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \active_cols_2_reg[7]_i_1_n_5\, + Q => active_cols_2(6), + R => '0' + ); +\active_cols_2_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \active_cols_2_reg[7]_i_1_n_4\, + Q => active_cols_2(7), + R => '0' + ); +\active_cols_2_reg[7]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \active_cols_2_reg[3]_i_1_n_0\, + CO(3) => \active_cols_2_reg[7]_i_1_n_0\, + CO(2) => \active_cols_2_reg[7]_i_1_n_1\, + CO(1) => \active_cols_2_reg[7]_i_1_n_2\, + CO(0) => \active_cols_2_reg[7]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \active_cols_2_reg[7]_i_1_n_4\, + O(2) => \active_cols_2_reg[7]_i_1_n_5\, + O(1) => \active_cols_2_reg[7]_i_1_n_6\, + O(0) => \active_cols_2_reg[7]_i_1_n_7\, + S(3) => \active_cols_2[7]_i_2_n_0\, + S(2) => \active_cols_2[7]_i_3_n_0\, + S(1) => \active_cols_2[7]_i_4_n_0\, + S(0) => \active_cols_2[7]_i_5_n_0\ + ); +\active_cols_2_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \active_cols_2_reg[11]_i_1_n_7\, + Q => active_cols_2(8), + R => '0' + ); +\active_cols_2_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \active_cols_2_reg[11]_i_1_n_6\, + Q => active_cols_2(9), + R => '0' + ); +\col_cnt[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \col_cnt[0]_i_2_n_0\, + I1 => \write_ptr_int_reg[2]\, + I2 => \col_cnt_reg_n_0_[0]\, + O => \col_cnt[0]_i_1_n_0\ + ); +\col_cnt[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EFAAEFAAEAAAEFAA" + ) + port map ( + I0 => \col_cnt[1]_i_4_n_0\, + I1 => active_cols_2(0), + I2 => eol_late_i3_out, + I3 => \row_cnt[0]_i_4_n_0\, + I4 => \col_cnt_reg_n_0_[0]\, + I5 => geqOp, + O => \col_cnt[0]_i_2_n_0\ + ); +\col_cnt[10]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"A808" + ) + port map ( + I0 => \col_cnt[12]_i_4_n_0\, + I1 => data1(10), + I2 => eol_late_i3_out, + I3 => active_cols_2(10), + O => \col_cnt[10]_i_1_n_0\ + ); +\col_cnt[11]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"A808" + ) + port map ( + I0 => \col_cnt[12]_i_4_n_0\, + I1 => data1(11), + I2 => eol_late_i3_out, + I3 => active_cols_2(11), + O => \col_cnt[11]_i_1_n_0\ + ); +\col_cnt[12]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"4F" + ) + port map ( + I0 => \col_cnt[12]_i_4_n_0\, + I1 => \write_ptr_int_reg[2]\, + I2 => resetn_out, + O => \col_cnt[12]_i_1_n_0\ + ); +\col_cnt[12]_i_15\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAA0800AAAA0A0A" + ) + port map ( + I0 => \word_count_reg[4]\, + I1 => fifo_rd_i, + I2 => \^col_cnt_reg[1]_0\, + I3 => \genr_control_regs[0]\(1), + I4 => \col_cnt[12]_i_20_n_0\, + I5 => in_fifo_reset_i_3_n_0, + O => \col_cnt[12]_i_15_n_0\ + ); +\col_cnt[12]_i_16\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \col_cnt_reg_n_0_[12]\, + O => \col_cnt[12]_i_16_n_0\ + ); +\col_cnt[12]_i_17\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \col_cnt_reg_n_0_[11]\, + O => \col_cnt[12]_i_17_n_0\ + ); +\col_cnt[12]_i_18\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \col_cnt_reg_n_0_[10]\, + O => \col_cnt[12]_i_18_n_0\ + ); +\col_cnt[12]_i_19\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \col_cnt_reg_n_0_[9]\, + O => \col_cnt[12]_i_19_n_0\ + ); +\col_cnt[12]_i_20\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8080808000808080" + ) + port map ( + I0 => aclken, + I1 => \genr_control_regs[0]\(0), + I2 => fifo_rd_i, + I3 => in_fifo_reset, + I4 => t_qb(0), + I5 => eol_expected_d, + O => \col_cnt[12]_i_20_n_0\ + ); +\col_cnt[12]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"A808" + ) + port map ( + I0 => \col_cnt[12]_i_4_n_0\, + I1 => data1(12), + I2 => eol_late_i3_out, + I3 => active_cols_2(12), + O => \col_cnt[12]_i_3_n_0\ + ); +\col_cnt[12]_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8A" + ) + port map ( + I0 => \row_cnt[0]_i_4_n_0\, + I1 => eol_late_i3_out, + I2 => geqOp, + O => \col_cnt[12]_i_4_n_0\ + ); +\col_cnt[12]_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1515150015151515" + ) + port map ( + I0 => gtOp21_in, + I1 => leqOp23_in, + I2 => gtOp22_in, + I3 => vid_empty, + I4 => \col_cnt[12]_i_15_n_0\, + I5 => leqOp20_in, + O => \col_cnt_reg[12]_0\ + ); +\col_cnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"A0A0A0A0A0A0C000" + ) + port map ( + I0 => \col_cnt_reg_n_0_[1]\, + I1 => \col_cnt[1]_i_2_n_0\, + I2 => resetn_out, + I3 => \col_cnt[1]_i_3_n_0\, + I4 => line_cnt_tc_i_3_n_0, + I5 => \^col_cnt_reg[1]_0\, + O => \col_cnt[1]_i_1_n_0\ + ); +\col_cnt[1]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EFEAAAAA" + ) + port map ( + I0 => \col_cnt[1]_i_4_n_0\, + I1 => active_cols_2(1), + I2 => eol_late_i3_out, + I3 => data1(1), + I4 => \col_cnt[12]_i_4_n_0\, + O => \col_cnt[1]_i_2_n_0\ + ); +\col_cnt[1]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFF3F55555555" + ) + port map ( + I0 => \^sof_early_i_reg_0\, + I1 => t_qb(1), + I2 => in_fifo_reset, + I3 => \^sof_early_i_reg_1\, + I4 => sof_expected, + I5 => fifo_rd_d, + O => \col_cnt[1]_i_3_n_0\ + ); +\col_cnt[1]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00DCDCDC00D0D0D0" + ) + port map ( + I0 => \^sof_early_i_reg_0\, + I1 => fifo_rd_d, + I2 => \^sof_early_i_reg_1\, + I3 => t_qb(1), + I4 => in_fifo_reset, + I5 => sof_expected, + O => \col_cnt[1]_i_4_n_0\ + ); +\col_cnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \col_cnt[2]_i_2_n_0\, + I1 => \write_ptr_int_reg[2]\, + I2 => \col_cnt_reg_n_0_[2]\, + O => \col_cnt[2]_i_1_n_0\ + ); +\col_cnt[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D555D5DDD555D555" + ) + port map ( + I0 => \col_cnt[2]_i_3_n_0\, + I1 => \row_cnt[0]_i_4_n_0\, + I2 => active_cols_2(2), + I3 => eol_late_i3_out, + I4 => geqOp, + I5 => data1(2), + O => \col_cnt[2]_i_2_n_0\ + ); +\col_cnt[2]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B0BBBBBB" + ) + port map ( + I0 => fifo_rd_d, + I1 => \^sof_early_i_reg_0\, + I2 => sof_expected, + I3 => in_fifo_reset, + I4 => t_qb(1), + O => \col_cnt[2]_i_3_n_0\ + ); +\col_cnt[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"A808" + ) + port map ( + I0 => \col_cnt[12]_i_4_n_0\, + I1 => data1(3), + I2 => eol_late_i3_out, + I3 => active_cols_2(3), + O => \col_cnt[3]_i_1_n_0\ + ); +\col_cnt[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"A808" + ) + port map ( + I0 => \col_cnt[12]_i_4_n_0\, + I1 => data1(4), + I2 => eol_late_i3_out, + I3 => active_cols_2(4), + O => \col_cnt[4]_i_1_n_0\ + ); +\col_cnt[4]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \col_cnt_reg_n_0_[4]\, + O => \col_cnt[4]_i_3_n_0\ + ); +\col_cnt[4]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \col_cnt_reg_n_0_[3]\, + O => \col_cnt[4]_i_4_n_0\ + ); +\col_cnt[4]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \col_cnt_reg_n_0_[2]\, + O => \col_cnt[4]_i_5_n_0\ + ); +\col_cnt[4]_i_6\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \col_cnt_reg_n_0_[1]\, + O => \col_cnt[4]_i_6_n_0\ + ); +\col_cnt[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"A808" + ) + port map ( + I0 => \col_cnt[12]_i_4_n_0\, + I1 => data1(5), + I2 => eol_late_i3_out, + I3 => active_cols_2(5), + O => \col_cnt[5]_i_1_n_0\ + ); +\col_cnt[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"A808" + ) + port map ( + I0 => \col_cnt[12]_i_4_n_0\, + I1 => data1(6), + I2 => eol_late_i3_out, + I3 => active_cols_2(6), + O => \col_cnt[6]_i_1_n_0\ + ); +\col_cnt[7]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"A808" + ) + port map ( + I0 => \col_cnt[12]_i_4_n_0\, + I1 => data1(7), + I2 => eol_late_i3_out, + I3 => active_cols_2(7), + O => \col_cnt[7]_i_1_n_0\ + ); +\col_cnt[8]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"A808" + ) + port map ( + I0 => \col_cnt[12]_i_4_n_0\, + I1 => data1(8), + I2 => eol_late_i3_out, + I3 => active_cols_2(8), + O => \col_cnt[8]_i_1_n_0\ + ); +\col_cnt[8]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \col_cnt_reg_n_0_[8]\, + O => \col_cnt[8]_i_3_n_0\ + ); +\col_cnt[8]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \col_cnt_reg_n_0_[7]\, + O => \col_cnt[8]_i_4_n_0\ + ); +\col_cnt[8]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \col_cnt_reg_n_0_[6]\, + O => \col_cnt[8]_i_5_n_0\ + ); +\col_cnt[8]_i_6\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \col_cnt_reg_n_0_[5]\, + O => \col_cnt[8]_i_6_n_0\ + ); +\col_cnt[9]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"A808" + ) + port map ( + I0 => \col_cnt[12]_i_4_n_0\, + I1 => data1(9), + I2 => eol_late_i3_out, + I3 => active_cols_2(9), + O => \col_cnt[9]_i_1_n_0\ + ); +\col_cnt_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => aclk, + CE => '1', + D => \col_cnt[0]_i_1_n_0\, + Q => \col_cnt_reg_n_0_[0]\, + S => SR(0) + ); +\col_cnt_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \write_ptr_int_reg[2]\, + D => \col_cnt[10]_i_1_n_0\, + Q => \col_cnt_reg_n_0_[10]\, + R => \col_cnt[12]_i_1_n_0\ + ); +\col_cnt_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \write_ptr_int_reg[2]\, + D => \col_cnt[11]_i_1_n_0\, + Q => \col_cnt_reg_n_0_[11]\, + R => \col_cnt[12]_i_1_n_0\ + ); +\col_cnt_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \write_ptr_int_reg[2]\, + D => \col_cnt[12]_i_3_n_0\, + Q => \col_cnt_reg_n_0_[12]\, + R => \col_cnt[12]_i_1_n_0\ + ); +\col_cnt_reg[12]_i_9\: unisim.vcomponents.CARRY4 + port map ( + CI => \col_cnt_reg[8]_i_2_n_0\, + CO(3) => \NLW_col_cnt_reg[12]_i_9_CO_UNCONNECTED\(3), + CO(2) => \col_cnt_reg[12]_i_9_n_1\, + CO(1) => \col_cnt_reg[12]_i_9_n_2\, + CO(0) => \col_cnt_reg[12]_i_9_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => data1(12 downto 9), + S(3) => \col_cnt[12]_i_16_n_0\, + S(2) => \col_cnt[12]_i_17_n_0\, + S(1) => \col_cnt[12]_i_18_n_0\, + S(0) => \col_cnt[12]_i_19_n_0\ + ); +\col_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \col_cnt[1]_i_1_n_0\, + Q => \col_cnt_reg_n_0_[1]\, + R => '0' + ); +\col_cnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \col_cnt[2]_i_1_n_0\, + Q => \col_cnt_reg_n_0_[2]\, + R => SR(0) + ); +\col_cnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \write_ptr_int_reg[2]\, + D => \col_cnt[3]_i_1_n_0\, + Q => \col_cnt_reg_n_0_[3]\, + R => \col_cnt[12]_i_1_n_0\ + ); +\col_cnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \write_ptr_int_reg[2]\, + D => \col_cnt[4]_i_1_n_0\, + Q => \col_cnt_reg_n_0_[4]\, + R => \col_cnt[12]_i_1_n_0\ + ); +\col_cnt_reg[4]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \col_cnt_reg[4]_i_2_n_0\, + CO(2) => \col_cnt_reg[4]_i_2_n_1\, + CO(1) => \col_cnt_reg[4]_i_2_n_2\, + CO(0) => \col_cnt_reg[4]_i_2_n_3\, + CYINIT => \col_cnt_reg_n_0_[0]\, + DI(3 downto 0) => B"0000", + O(3 downto 0) => data1(4 downto 1), + S(3) => \col_cnt[4]_i_3_n_0\, + S(2) => \col_cnt[4]_i_4_n_0\, + S(1) => \col_cnt[4]_i_5_n_0\, + S(0) => \col_cnt[4]_i_6_n_0\ + ); +\col_cnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \write_ptr_int_reg[2]\, + D => \col_cnt[5]_i_1_n_0\, + Q => \col_cnt_reg_n_0_[5]\, + R => \col_cnt[12]_i_1_n_0\ + ); +\col_cnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \write_ptr_int_reg[2]\, + D => \col_cnt[6]_i_1_n_0\, + Q => \col_cnt_reg_n_0_[6]\, + R => \col_cnt[12]_i_1_n_0\ + ); +\col_cnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \write_ptr_int_reg[2]\, + D => \col_cnt[7]_i_1_n_0\, + Q => \col_cnt_reg_n_0_[7]\, + R => \col_cnt[12]_i_1_n_0\ + ); +\col_cnt_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \write_ptr_int_reg[2]\, + D => \col_cnt[8]_i_1_n_0\, + Q => \col_cnt_reg_n_0_[8]\, + R => \col_cnt[12]_i_1_n_0\ + ); +\col_cnt_reg[8]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => \col_cnt_reg[4]_i_2_n_0\, + CO(3) => \col_cnt_reg[8]_i_2_n_0\, + CO(2) => \col_cnt_reg[8]_i_2_n_1\, + CO(1) => \col_cnt_reg[8]_i_2_n_2\, + CO(0) => \col_cnt_reg[8]_i_2_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => data1(8 downto 5), + S(3) => \col_cnt[8]_i_3_n_0\, + S(2) => \col_cnt[8]_i_4_n_0\, + S(1) => \col_cnt[8]_i_5_n_0\, + S(0) => \col_cnt[8]_i_6_n_0\ + ); +\col_cnt_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \write_ptr_int_reg[2]\, + D => \col_cnt[9]_i_1_n_0\, + Q => \col_cnt_reg_n_0_[9]\, + R => \col_cnt[12]_i_1_n_0\ + ); +core_en_i_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"00C0A0A0A0A0A0A0" + ) + port map ( + I0 => core_en_i, + I1 => gtOp, + I2 => resetn_out, + I3 => line_cnt_tc_i_3_n_0, + I4 => \genr_control_regs[0]\(0), + I5 => aclken, + O => core_en_i_i_1_n_0 + ); +core_en_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => core_en_i_i_1_n_0, + Q => core_en_i, + R => '0' + ); +eof_i_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAA00C0AAAA" + ) + port map ( + I0 => \^intc_if\(0), + I1 => eqOp1_out, + I2 => eqOp_0, + I3 => line_cnt_tc_i_3_n_0, + I4 => resetn_out, + I5 => \^col_cnt_reg[1]_0\, + O => eof_i_i_1_n_0 + ); +eof_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => eof_i_i_1_n_0, + Q => \^intc_if\(0), + R => '0' + ); +eol_early_i_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"A0A000C0A0A0A0A0" + ) + port map ( + I0 => \^intc_if\(4), + I1 => eol_early_i0, + I2 => resetn_out, + I3 => eol_expected_d, + I4 => \^col_cnt_reg[1]_0\, + I5 => fifo_rd_d, + O => eol_early_i_i_1_n_0 + ); +eol_early_i_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"A1A1A1A1000000A1" + ) + port map ( + I0 => eol_early_i_i_4_n_0, + I1 => \^sof_early_i_reg_1\, + I2 => sof_expected, + I3 => \^eol_late_i_reg_0\, + I4 => eol_late_i_i_2_n_0, + I5 => \^intc_if\(4), + O => eol_early_i0 + ); +eol_early_i_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"7" + ) + port map ( + I0 => aclken, + I1 => \genr_control_regs[0]\(0), + O => \^col_cnt_reg[1]_0\ + ); +eol_early_i_i_4: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => in_fifo_reset, + I1 => t_qb(1), + O => eol_early_i_i_4_n_0 + ); +eol_early_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => eol_early_i_i_1_n_0, + Q => \^intc_if\(4), + R => '0' + ); +eol_expected_d_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFFF8000" + ) + port map ( + I0 => eol_expected, + I1 => fifo_rd_i, + I2 => \genr_control_regs[0]\(0), + I3 => aclken, + I4 => eol_expected_d, + O => eol_expected_d_i_1_n_0 + ); +eol_expected_d_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => eol_expected_d_i_1_n_0, + Q => eol_expected_d, + R => SR(0) + ); +eol_expected_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"2A" + ) + port map ( + I0 => eqOp0_out, + I1 => t_qb(1), + I2 => in_fifo_reset, + O => eol_expected0 + ); +eol_expected_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^master_en\, + D => eol_expected0, + Q => eol_expected, + R => SR(0) + ); +eol_late_i_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0AAA8AAA00008000" + ) + port map ( + I0 => eol_late_i_i_2_n_0, + I1 => eol_late_i_i_3_n_0, + I2 => fifo_rd_d, + I3 => eol_expected_d, + I4 => \^intc_if\(4), + I5 => \^eol_late_i_reg_0\, + O => eol_late_i3_out + ); +eol_late_i_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"7" + ) + port map ( + I0 => in_fifo_reset, + I1 => t_qb(0), + O => eol_late_i_i_2_n_0 + ); +eol_late_i_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"A111" + ) + port map ( + I0 => sof_expected, + I1 => \^sof_early_i_reg_1\, + I2 => in_fifo_reset, + I3 => t_qb(1), + O => eol_late_i_i_3_n_0 + ); +eol_late_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^master_en\, + D => eol_late_i3_out, + Q => \^eol_late_i_reg_0\, + R => SR(0) + ); +eqOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => eqOp_carry_n_0, + CO(2) => eqOp_carry_n_1, + CO(1) => eqOp_carry_n_2, + CO(0) => eqOp_carry_n_3, + CYINIT => '1', + DI(3 downto 0) => B"0000", + O(3 downto 0) => NLW_eqOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => eqOp_carry_i_1_n_0, + S(2) => eqOp_carry_i_2_n_0, + S(1) => eqOp_carry_i_3_n_0, + S(0) => eqOp_carry_i_4_n_0 + ); +\eqOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => eqOp_carry_n_0, + CO(3 downto 1) => \NLW_eqOp_carry__0_CO_UNCONNECTED\(3 downto 1), + CO(0) => eqOp0_out, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => \NLW_eqOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3 downto 1) => B"000", + S(0) => \eqOp_carry__0_i_1_n_0\ + ); +\eqOp_carry__0_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \time_control_regs[0]\(12), + I1 => \col_cnt_reg_n_0_[12]\, + O => \eqOp_carry__0_i_1_n_0\ + ); +eqOp_carry_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \col_cnt_reg_n_0_[10]\, + I1 => \time_control_regs[0]\(10), + I2 => \col_cnt_reg_n_0_[11]\, + I3 => \time_control_regs[0]\(11), + I4 => \time_control_regs[0]\(9), + I5 => \col_cnt_reg_n_0_[9]\, + O => eqOp_carry_i_1_n_0 + ); +eqOp_carry_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \col_cnt_reg_n_0_[7]\, + I1 => \time_control_regs[0]\(7), + I2 => \col_cnt_reg_n_0_[6]\, + I3 => \time_control_regs[0]\(6), + I4 => \time_control_regs[0]\(8), + I5 => \col_cnt_reg_n_0_[8]\, + O => eqOp_carry_i_2_n_0 + ); +eqOp_carry_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \col_cnt_reg_n_0_[4]\, + I1 => \time_control_regs[0]\(4), + I2 => \col_cnt_reg_n_0_[5]\, + I3 => \time_control_regs[0]\(5), + I4 => \time_control_regs[0]\(3), + I5 => \col_cnt_reg_n_0_[3]\, + O => eqOp_carry_i_3_n_0 + ); +eqOp_carry_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \col_cnt_reg_n_0_[1]\, + I1 => \time_control_regs[0]\(1), + I2 => \col_cnt_reg_n_0_[0]\, + I3 => \time_control_regs[0]\(0), + I4 => \time_control_regs[0]\(2), + I5 => \col_cnt_reg_n_0_[2]\, + O => eqOp_carry_i_4_n_0 + ); +\eqOp_inferred__3/i__carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \eqOp_inferred__3/i__carry_n_0\, + CO(2) => \eqOp_inferred__3/i__carry_n_1\, + CO(1) => \eqOp_inferred__3/i__carry_n_2\, + CO(0) => \eqOp_inferred__3/i__carry_n_3\, + CYINIT => '1', + DI(3 downto 0) => B"0000", + O(3 downto 0) => \NLW_eqOp_inferred__3/i__carry_O_UNCONNECTED\(3 downto 0), + S(3) => \i__carry_i_1__0_n_0\, + S(2) => \i__carry_i_2__0_n_0\, + S(1) => \i__carry_i_3__0_n_0\, + S(0) => \i__carry_i_4_n_0\ + ); +\eqOp_inferred__3/i__carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \eqOp_inferred__3/i__carry_n_0\, + CO(3 downto 1) => \NLW_eqOp_inferred__3/i__carry__0_CO_UNCONNECTED\(3 downto 1), + CO(0) => eqOp1_out, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => \NLW_eqOp_inferred__3/i__carry__0_O_UNCONNECTED\(3 downto 0), + S(3 downto 1) => B"000", + S(0) => \i__carry__0_i_1__5_n_0\ + ); +\eqOp_inferred__4/i__carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \eqOp_inferred__4/i__carry_n_0\, + CO(2) => \eqOp_inferred__4/i__carry_n_1\, + CO(1) => \eqOp_inferred__4/i__carry_n_2\, + CO(0) => \eqOp_inferred__4/i__carry_n_3\, + CYINIT => '1', + DI(3 downto 0) => B"0000", + O(3 downto 0) => \NLW_eqOp_inferred__4/i__carry_O_UNCONNECTED\(3 downto 0), + S(3) => \i__carry_i_1__1_n_0\, + S(2) => \i__carry_i_2__1_n_0\, + S(1) => \i__carry_i_3__1_n_0\, + S(0) => \i__carry_i_4__1_n_0\ + ); +\eqOp_inferred__4/i__carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \eqOp_inferred__4/i__carry_n_0\, + CO(3 downto 1) => \NLW_eqOp_inferred__4/i__carry__0_CO_UNCONNECTED\(3 downto 1), + CO(0) => eqOp_0, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => \NLW_eqOp_inferred__4/i__carry__0_O_UNCONNECTED\(3 downto 0), + S(3 downto 1) => B"000", + S(0) => \i__carry__0_i_1__6_n_0\ + ); +fifo_rd_d_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFFF8000" + ) + port map ( + I0 => fifo_rd_i, + I1 => resetn_out, + I2 => \genr_control_regs[0]\(0), + I3 => aclken, + I4 => fifo_rd_d, + O => fifo_rd_d_i_1_n_0 + ); +fifo_rd_d_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => fifo_rd_d_i_1_n_0, + Q => fifo_rd_d, + R => '0' + ); +fifo_rd_i_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"00C0A0A0A0A0A0A0" + ) + port map ( + I0 => fifo_rd_i, + I1 => fifo_rd_i0, + I2 => resetn_out, + I3 => line_cnt_tc_i_3_n_0, + I4 => \genr_control_regs[0]\(0), + I5 => aclken, + O => fifo_rd_i_i_1_n_0 + ); +fifo_rd_i_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFECECEC" + ) + port map ( + I0 => fifo_rd_d, + I1 => \^sof_early_i_reg_1\, + I2 => sof_expected, + I3 => leqOp20_in, + I4 => leqOp16_in, + I5 => eol_early_i_i_4_n_0, + O => fifo_rd_i0 + ); +fifo_rd_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => fifo_rd_i_i_1_n_0, + Q => fifo_rd_i, + R => '0' + ); +fifo_wr_i_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AA00AA000000C000" + ) + port map ( + I0 => \^fifo_wr_i\, + I1 => gtOp18_in, + I2 => gtOp19_in, + I3 => resetn_out, + I4 => line_cnt_tc_i_3_n_0, + I5 => \^col_cnt_reg[1]_0\, + O => fifo_wr_i_i_1_n_0 + ); +fifo_wr_i_i_10: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \col_cnt_reg_n_0_[5]\, + I1 => \col_cnt_reg_n_0_[4]\, + O => fifo_wr_i_i_10_n_0 + ); +fifo_wr_i_i_11: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \col_cnt_reg_n_0_[6]\, + I1 => \col_cnt_reg_n_0_[7]\, + O => fifo_wr_i_i_11_n_0 + ); +fifo_wr_i_i_12: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \col_cnt_reg_n_0_[4]\, + I1 => \col_cnt_reg_n_0_[5]\, + O => fifo_wr_i_i_12_n_0 + ); +fifo_wr_i_i_13: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \col_cnt_reg_n_0_[2]\, + I1 => \col_cnt_reg_n_0_[3]\, + O => fifo_wr_i_i_13_n_0 + ); +fifo_wr_i_i_14: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \col_cnt_reg_n_0_[0]\, + I1 => \col_cnt_reg_n_0_[1]\, + O => fifo_wr_i_i_14_n_0 + ); +fifo_wr_i_i_4: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \col_cnt_reg_n_0_[11]\, + I1 => \col_cnt_reg_n_0_[10]\, + O => fifo_wr_i_i_4_n_0 + ); +fifo_wr_i_i_5: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \col_cnt_reg_n_0_[9]\, + I1 => \col_cnt_reg_n_0_[8]\, + O => fifo_wr_i_i_5_n_0 + ); +fifo_wr_i_i_6: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \col_cnt_reg_n_0_[12]\, + O => fifo_wr_i_i_6_n_0 + ); +fifo_wr_i_i_7: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \col_cnt_reg_n_0_[10]\, + I1 => \col_cnt_reg_n_0_[11]\, + O => fifo_wr_i_i_7_n_0 + ); +fifo_wr_i_i_8: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \col_cnt_reg_n_0_[8]\, + I1 => \col_cnt_reg_n_0_[9]\, + O => fifo_wr_i_i_8_n_0 + ); +fifo_wr_i_i_9: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \col_cnt_reg_n_0_[7]\, + I1 => \col_cnt_reg_n_0_[6]\, + O => fifo_wr_i_i_9_n_0 + ); +fifo_wr_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => fifo_wr_i_i_1_n_0, + Q => \^fifo_wr_i\, + R => '0' + ); +fifo_wr_i_reg_i_2: unisim.vcomponents.CARRY4 + port map ( + CI => fifo_wr_i_reg_i_3_n_0, + CO(3) => NLW_fifo_wr_i_reg_i_2_CO_UNCONNECTED(3), + CO(2) => gtOp19_in, + CO(1) => fifo_wr_i_reg_i_2_n_2, + CO(0) => fifo_wr_i_reg_i_2_n_3, + CYINIT => '0', + DI(3) => '0', + DI(2) => \col_cnt_reg_n_0_[12]\, + DI(1) => fifo_wr_i_i_4_n_0, + DI(0) => fifo_wr_i_i_5_n_0, + O(3 downto 0) => NLW_fifo_wr_i_reg_i_2_O_UNCONNECTED(3 downto 0), + S(3) => '0', + S(2) => fifo_wr_i_i_6_n_0, + S(1) => fifo_wr_i_i_7_n_0, + S(0) => fifo_wr_i_i_8_n_0 + ); +fifo_wr_i_reg_i_3: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => fifo_wr_i_reg_i_3_n_0, + CO(2) => fifo_wr_i_reg_i_3_n_1, + CO(1) => fifo_wr_i_reg_i_3_n_2, + CO(0) => fifo_wr_i_reg_i_3_n_3, + CYINIT => '0', + DI(3) => fifo_wr_i_i_9_n_0, + DI(2) => fifo_wr_i_i_10_n_0, + DI(1) => '0', + DI(0) => \col_cnt_reg_n_0_[1]\, + O(3 downto 0) => NLW_fifo_wr_i_reg_i_3_O_UNCONNECTED(3 downto 0), + S(3) => fifo_wr_i_i_11_n_0, + S(2) => fifo_wr_i_i_12_n_0, + S(1) => fifo_wr_i_i_13_n_0, + S(0) => fifo_wr_i_i_14_n_0 + ); +geqOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => geqOp_carry_n_0, + CO(2) => geqOp_carry_n_1, + CO(1) => geqOp_carry_n_2, + CO(0) => geqOp_carry_n_3, + CYINIT => '1', + DI(3) => geqOp_carry_i_1_n_0, + DI(2) => geqOp_carry_i_2_n_0, + DI(1) => geqOp_carry_i_3_n_0, + DI(0) => geqOp_carry_i_4_n_0, + O(3 downto 0) => NLW_geqOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => geqOp_carry_i_5_n_0, + S(2) => geqOp_carry_i_6_n_0, + S(1) => geqOp_carry_i_7_n_0, + S(0) => geqOp_carry_i_8_n_0 + ); +\geqOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => geqOp_carry_n_0, + CO(3) => \NLW_geqOp_carry__0_CO_UNCONNECTED\(3), + CO(2) => geqOp, + CO(1) => \geqOp_carry__0_n_2\, + CO(0) => \geqOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => '0', + DI(2) => \geqOp_carry__0_i_1_n_0\, + DI(1) => \geqOp_carry__0_i_2_n_0\, + DI(0) => \geqOp_carry__0_i_3_n_0\, + O(3 downto 0) => \NLW_geqOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => '0', + S(2) => \geqOp_carry__0_i_4_n_0\, + S(1) => \geqOp_carry__0_i_5_n_0\, + S(0) => \geqOp_carry__0_i_6_n_0\ + ); +\geqOp_carry__0_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \col_cnt_reg_n_0_[12]\, + I1 => total_cols(12), + O => \geqOp_carry__0_i_1_n_0\ + ); +\geqOp_carry__0_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \col_cnt_reg_n_0_[10]\, + I1 => total_cols(10), + I2 => total_cols(11), + I3 => \col_cnt_reg_n_0_[11]\, + O => \geqOp_carry__0_i_2_n_0\ + ); +\geqOp_carry__0_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \col_cnt_reg_n_0_[8]\, + I1 => total_cols(8), + I2 => total_cols(9), + I3 => \col_cnt_reg_n_0_[9]\, + O => \geqOp_carry__0_i_3_n_0\ + ); +\geqOp_carry__0_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => total_cols(12), + I1 => \col_cnt_reg_n_0_[12]\, + O => \geqOp_carry__0_i_4_n_0\ + ); +\geqOp_carry__0_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => total_cols(10), + I1 => \col_cnt_reg_n_0_[10]\, + I2 => \col_cnt_reg_n_0_[11]\, + I3 => total_cols(11), + O => \geqOp_carry__0_i_5_n_0\ + ); +\geqOp_carry__0_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => total_cols(9), + I1 => \col_cnt_reg_n_0_[9]\, + I2 => total_cols(8), + I3 => \col_cnt_reg_n_0_[8]\, + O => \geqOp_carry__0_i_6_n_0\ + ); +geqOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \col_cnt_reg_n_0_[6]\, + I1 => total_cols(6), + I2 => total_cols(7), + I3 => \col_cnt_reg_n_0_[7]\, + O => geqOp_carry_i_1_n_0 + ); +geqOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \col_cnt_reg_n_0_[4]\, + I1 => total_cols(4), + I2 => total_cols(5), + I3 => \col_cnt_reg_n_0_[5]\, + O => geqOp_carry_i_2_n_0 + ); +geqOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \col_cnt_reg_n_0_[2]\, + I1 => total_cols(2), + I2 => total_cols(3), + I3 => \col_cnt_reg_n_0_[3]\, + O => geqOp_carry_i_3_n_0 + ); +geqOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \col_cnt_reg_n_0_[0]\, + I1 => total_cols(0), + I2 => total_cols(1), + I3 => \col_cnt_reg_n_0_[1]\, + O => geqOp_carry_i_4_n_0 + ); +geqOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => total_cols(6), + I1 => \col_cnt_reg_n_0_[6]\, + I2 => \col_cnt_reg_n_0_[7]\, + I3 => total_cols(7), + O => geqOp_carry_i_5_n_0 + ); +geqOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => total_cols(4), + I1 => \col_cnt_reg_n_0_[4]\, + I2 => \col_cnt_reg_n_0_[5]\, + I3 => total_cols(5), + O => geqOp_carry_i_6_n_0 + ); +geqOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => total_cols(3), + I1 => \col_cnt_reg_n_0_[3]\, + I2 => total_cols(2), + I3 => \col_cnt_reg_n_0_[2]\, + O => geqOp_carry_i_7_n_0 + ); +geqOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => total_cols(0), + I1 => \col_cnt_reg_n_0_[0]\, + I2 => \col_cnt_reg_n_0_[1]\, + I3 => total_cols(1), + O => geqOp_carry_i_8_n_0 + ); +gtOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => gtOp_carry_n_0, + CO(2) => gtOp_carry_n_1, + CO(1) => gtOp_carry_n_2, + CO(0) => gtOp_carry_n_3, + CYINIT => '0', + DI(3) => gtOp_carry_i_1_n_0, + DI(2) => gtOp_carry_i_2_n_0, + DI(1) => gtOp_carry_i_3_n_0, + DI(0) => gtOp_carry_i_4_n_0, + O(3 downto 0) => NLW_gtOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => gtOp_carry_i_5_n_0, + S(2) => gtOp_carry_i_6_n_0, + S(1) => gtOp_carry_i_7_n_0, + S(0) => gtOp_carry_i_8_n_0 + ); +\gtOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => gtOp_carry_n_0, + CO(3) => \NLW_gtOp_carry__0_CO_UNCONNECTED\(3), + CO(2) => gtOp22_in, + CO(1) => \gtOp_carry__0_n_2\, + CO(0) => \gtOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => '0', + DI(2) => \gtOp_carry__0_i_1_n_0\, + DI(1) => \gtOp_carry__0_i_2_n_0\, + DI(0) => \gtOp_carry__0_i_3_n_0\, + O(3 downto 0) => \NLW_gtOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => '0', + S(2) => \gtOp_carry__0_i_4_n_0\, + S(1) => \gtOp_carry__0_i_5_n_0\, + S(0) => \gtOp_carry__0_i_6_n_0\ + ); +\gtOp_carry__0_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \col_cnt_reg_n_0_[12]\, + I1 => \time_control_regs[0]\(12), + O => \gtOp_carry__0_i_1_n_0\ + ); +\gtOp_carry__0_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2B22" + ) + port map ( + I0 => \col_cnt_reg_n_0_[11]\, + I1 => \time_control_regs[0]\(11), + I2 => \time_control_regs[0]\(10), + I3 => \col_cnt_reg_n_0_[10]\, + O => \gtOp_carry__0_i_2_n_0\ + ); +\gtOp_carry__0_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"40F4" + ) + port map ( + I0 => \time_control_regs[0]\(8), + I1 => \col_cnt_reg_n_0_[8]\, + I2 => \col_cnt_reg_n_0_[9]\, + I3 => \time_control_regs[0]\(9), + O => \gtOp_carry__0_i_3_n_0\ + ); +\gtOp_carry__0_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \time_control_regs[0]\(12), + I1 => \col_cnt_reg_n_0_[12]\, + O => \gtOp_carry__0_i_4_n_0\ + ); +\gtOp_carry__0_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \time_control_regs[0]\(11), + I1 => \col_cnt_reg_n_0_[11]\, + I2 => \time_control_regs[0]\(10), + I3 => \col_cnt_reg_n_0_[10]\, + O => \gtOp_carry__0_i_5_n_0\ + ); +\gtOp_carry__0_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \time_control_regs[0]\(8), + I1 => \col_cnt_reg_n_0_[8]\, + I2 => \time_control_regs[0]\(9), + I3 => \col_cnt_reg_n_0_[9]\, + O => \gtOp_carry__0_i_6_n_0\ + ); +gtOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2B22" + ) + port map ( + I0 => \col_cnt_reg_n_0_[7]\, + I1 => \time_control_regs[0]\(7), + I2 => \time_control_regs[0]\(6), + I3 => \col_cnt_reg_n_0_[6]\, + O => gtOp_carry_i_1_n_0 + ); +gtOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2B22" + ) + port map ( + I0 => \col_cnt_reg_n_0_[5]\, + I1 => \time_control_regs[0]\(5), + I2 => \time_control_regs[0]\(4), + I3 => \col_cnt_reg_n_0_[4]\, + O => gtOp_carry_i_2_n_0 + ); +gtOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"40F4" + ) + port map ( + I0 => \time_control_regs[0]\(2), + I1 => \col_cnt_reg_n_0_[2]\, + I2 => \col_cnt_reg_n_0_[3]\, + I3 => \time_control_regs[0]\(3), + O => gtOp_carry_i_3_n_0 + ); +gtOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2B22" + ) + port map ( + I0 => \col_cnt_reg_n_0_[1]\, + I1 => \time_control_regs[0]\(1), + I2 => \time_control_regs[0]\(0), + I3 => \col_cnt_reg_n_0_[0]\, + O => gtOp_carry_i_4_n_0 + ); +gtOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \time_control_regs[0]\(6), + I1 => \col_cnt_reg_n_0_[6]\, + I2 => \time_control_regs[0]\(7), + I3 => \col_cnt_reg_n_0_[7]\, + O => gtOp_carry_i_5_n_0 + ); +gtOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \time_control_regs[0]\(5), + I1 => \col_cnt_reg_n_0_[5]\, + I2 => \time_control_regs[0]\(4), + I3 => \col_cnt_reg_n_0_[4]\, + O => gtOp_carry_i_6_n_0 + ); +gtOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \time_control_regs[0]\(2), + I1 => \col_cnt_reg_n_0_[2]\, + I2 => \time_control_regs[0]\(3), + I3 => \col_cnt_reg_n_0_[3]\, + O => gtOp_carry_i_7_n_0 + ); +gtOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \time_control_regs[0]\(0), + I1 => \col_cnt_reg_n_0_[0]\, + I2 => \time_control_regs[0]\(1), + I3 => \col_cnt_reg_n_0_[1]\, + O => gtOp_carry_i_8_n_0 + ); +\gtOp_inferred__0/i__carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \gtOp_inferred__0/i__carry_n_0\, + CO(2) => \gtOp_inferred__0/i__carry_n_1\, + CO(1) => \gtOp_inferred__0/i__carry_n_2\, + CO(0) => \gtOp_inferred__0/i__carry_n_3\, + CYINIT => '0', + DI(3) => \i__carry_i_1__2_n_0\, + DI(2) => \i__carry_i_2__2_n_0\, + DI(1) => \i__carry_i_3__2_n_0\, + DI(0) => \i__carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_gtOp_inferred__0/i__carry_O_UNCONNECTED\(3 downto 0), + S(3) => \i__carry_i_5__1_n_0\, + S(2) => \i__carry_i_6__3_n_0\, + S(1) => \i__carry_i_7__3_n_0\, + S(0) => \i__carry_i_8__2_n_0\ + ); +\gtOp_inferred__0/i__carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \gtOp_inferred__0/i__carry_n_0\, + CO(3) => \NLW_gtOp_inferred__0/i__carry__0_CO_UNCONNECTED\(3), + CO(2) => gtOp21_in, + CO(1) => \gtOp_inferred__0/i__carry__0_n_2\, + CO(0) => \gtOp_inferred__0/i__carry__0_n_3\, + CYINIT => '0', + DI(3) => '0', + DI(2) => \i__carry__0_i_1__0_n_0\, + DI(1) => \i__carry__0_i_2__0_n_0\, + DI(0) => \i__carry__0_i_3__2_n_0\, + O(3 downto 0) => \NLW_gtOp_inferred__0/i__carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => '0', + S(2) => \i__carry__0_i_4__2_n_0\, + S(1) => \i__carry__0_i_5__2_n_0\, + S(0) => \i__carry__0_i_6__1_n_0\ + ); +\gtOp_inferred__2/i__carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \gtOp_inferred__2/i__carry_n_0\, + CO(2) => \gtOp_inferred__2/i__carry_n_1\, + CO(1) => \gtOp_inferred__2/i__carry_n_2\, + CO(0) => \gtOp_inferred__2/i__carry_n_3\, + CYINIT => '0', + DI(3) => \i__carry_i_1__5_n_0\, + DI(2) => \i__carry_i_2__4_n_0\, + DI(1) => \i__carry_i_3__4_n_0\, + DI(0) => \i__carry_i_4__4_n_0\, + O(3 downto 0) => \NLW_gtOp_inferred__2/i__carry_O_UNCONNECTED\(3 downto 0), + S(3) => \i__carry_i_5__3_n_0\, + S(2) => \i__carry_i_6__1_n_0\, + S(1) => \i__carry_i_7__1_n_0\, + S(0) => \i__carry_i_8__1_n_0\ + ); +\gtOp_inferred__2/i__carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \gtOp_inferred__2/i__carry_n_0\, + CO(3) => \NLW_gtOp_inferred__2/i__carry__0_CO_UNCONNECTED\(3), + CO(2) => gtOp18_in, + CO(1) => \gtOp_inferred__2/i__carry__0_n_2\, + CO(0) => \gtOp_inferred__2/i__carry__0_n_3\, + CYINIT => '0', + DI(3) => '0', + DI(2) => row_cnt_reg(12), + DI(1) => \i__carry__0_i_1__2_n_0\, + DI(0) => \i__carry__0_i_2__2_n_0\, + O(3 downto 0) => \NLW_gtOp_inferred__2/i__carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => '0', + S(2) => \i__carry__0_i_3__0_n_0\, + S(1) => \i__carry__0_i_4__0_n_0\, + S(0) => \i__carry__0_i_5__1_n_0\ + ); +\gtOp_inferred__3/i__carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \gtOp_inferred__3/i__carry_n_0\, + CO(2) => \gtOp_inferred__3/i__carry_n_1\, + CO(1) => \gtOp_inferred__3/i__carry_n_2\, + CO(0) => \gtOp_inferred__3/i__carry_n_3\, + CYINIT => '0', + DI(3) => \i__carry_i_1__6_n_0\, + DI(2) => \i__carry_i_2__5_n_0\, + DI(1) => \i__carry_i_3__5_n_0\, + DI(0) => \col_cnt_reg_n_0_[1]\, + O(3 downto 0) => \NLW_gtOp_inferred__3/i__carry_O_UNCONNECTED\(3 downto 0), + S(3) => \i__carry_i_4__6_n_0\, + S(2) => \i__carry_i_5__4_n_0\, + S(1) => \i__carry_i_6__2_n_0\, + S(0) => \i__carry_i_7__2_n_0\ + ); +\gtOp_inferred__3/i__carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \gtOp_inferred__3/i__carry_n_0\, + CO(3) => \NLW_gtOp_inferred__3/i__carry__0_CO_UNCONNECTED\(3), + CO(2) => gtOp, + CO(1) => \gtOp_inferred__3/i__carry__0_n_2\, + CO(0) => \gtOp_inferred__3/i__carry__0_n_3\, + CYINIT => '0', + DI(3) => '0', + DI(2) => \col_cnt_reg_n_0_[12]\, + DI(1) => \i__carry__0_i_1__3_n_0\, + DI(0) => \i__carry__0_i_2__3_n_0\, + O(3 downto 0) => \NLW_gtOp_inferred__3/i__carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => '0', + S(2) => \i__carry__0_i_3__1_n_0\, + S(1) => \i__carry__0_i_4_n_0\, + S(0) => \i__carry__0_i_5__3_n_0\ + ); +\i__carry__0_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => total_cols(12), + I1 => \col_cnt_reg_n_0_[12]\, + O => \i__carry__0_i_1_n_0\ + ); +\i__carry__0_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => row_cnt_reg(12), + I1 => \time_control_regs[0]\(25), + O => \i__carry__0_i_1__0_n_0\ + ); +\i__carry__0_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \time_control_regs[0]\(25), + I1 => row_cnt_reg(12), + O => \i__carry__0_i_1__1_n_0\ + ); +\i__carry__0_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => row_cnt_reg(11), + I1 => row_cnt_reg(10), + O => \i__carry__0_i_1__2_n_0\ + ); +\i__carry__0_i_1__3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \col_cnt_reg_n_0_[11]\, + I1 => \col_cnt_reg_n_0_[10]\, + O => \i__carry__0_i_1__3_n_0\ + ); +\i__carry__0_i_1__4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \col_cnt_reg_n_0_[12]\, + O => \i__carry__0_i_1__4_n_0\ + ); +\i__carry__0_i_1__5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => total_cols(12), + I1 => \col_cnt_reg_n_0_[12]\, + O => \i__carry__0_i_1__5_n_0\ + ); +\i__carry__0_i_1__6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => total_rows(12), + I1 => row_cnt_reg(12), + O => \i__carry__0_i_1__6_n_0\ + ); +\i__carry__0_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => total_cols(10), + I1 => \col_cnt_reg_n_0_[10]\, + I2 => \col_cnt_reg_n_0_[11]\, + I3 => total_cols(11), + O => \i__carry__0_i_2_n_0\ + ); +\i__carry__0_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => row_cnt_reg(10), + I1 => \time_control_regs[0]\(23), + I2 => \time_control_regs[0]\(24), + I3 => row_cnt_reg(11), + O => \i__carry__0_i_2__0_n_0\ + ); +\i__carry__0_i_2__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \time_control_regs[0]\(23), + I1 => row_cnt_reg(10), + I2 => row_cnt_reg(11), + I3 => \time_control_regs[0]\(24), + O => \i__carry__0_i_2__1_n_0\ + ); +\i__carry__0_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => row_cnt_reg(9), + I1 => row_cnt_reg(8), + O => \i__carry__0_i_2__2_n_0\ + ); +\i__carry__0_i_2__3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \col_cnt_reg_n_0_[9]\, + I1 => \col_cnt_reg_n_0_[8]\, + O => \i__carry__0_i_2__3_n_0\ + ); +\i__carry__0_i_2__4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \col_cnt_reg_n_0_[10]\, + I1 => \col_cnt_reg_n_0_[11]\, + O => \i__carry__0_i_2__4_n_0\ + ); +\i__carry__0_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => total_cols(8), + I1 => \col_cnt_reg_n_0_[8]\, + I2 => \col_cnt_reg_n_0_[9]\, + I3 => total_cols(9), + O => \i__carry__0_i_3_n_0\ + ); +\i__carry__0_i_3__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => row_cnt_reg(12), + O => \i__carry__0_i_3__0_n_0\ + ); +\i__carry__0_i_3__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \col_cnt_reg_n_0_[12]\, + O => \i__carry__0_i_3__1_n_0\ + ); +\i__carry__0_i_3__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => row_cnt_reg(8), + I1 => \time_control_regs[0]\(21), + I2 => \time_control_regs[0]\(22), + I3 => row_cnt_reg(9), + O => \i__carry__0_i_3__2_n_0\ + ); +\i__carry__0_i_3__3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \time_control_regs[0]\(21), + I1 => row_cnt_reg(8), + I2 => row_cnt_reg(9), + I3 => \time_control_regs[0]\(22), + O => \i__carry__0_i_3__3_n_0\ + ); +\i__carry__0_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \col_cnt_reg_n_0_[10]\, + I1 => \col_cnt_reg_n_0_[11]\, + O => \i__carry__0_i_4_n_0\ + ); +\i__carry__0_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => row_cnt_reg(10), + I1 => row_cnt_reg(11), + O => \i__carry__0_i_4__0_n_0\ + ); +\i__carry__0_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \col_cnt_reg_n_0_[12]\, + I1 => total_cols(12), + O => \i__carry__0_i_4__1_n_0\ + ); +\i__carry__0_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \time_control_regs[0]\(25), + I1 => row_cnt_reg(12), + O => \i__carry__0_i_4__2_n_0\ + ); +\i__carry__0_i_4__3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => row_cnt_reg(12), + I1 => \time_control_regs[0]\(25), + O => \i__carry__0_i_4__3_n_0\ + ); +\i__carry__0_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => total_cols(10), + I1 => \col_cnt_reg_n_0_[10]\, + I2 => \col_cnt_reg_n_0_[11]\, + I3 => total_cols(11), + O => \i__carry__0_i_5_n_0\ + ); +\i__carry__0_i_5__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \time_control_regs[0]\(23), + I1 => row_cnt_reg(10), + I2 => row_cnt_reg(11), + I3 => \time_control_regs[0]\(24), + O => \i__carry__0_i_5__0_n_0\ + ); +\i__carry__0_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => row_cnt_reg(8), + I1 => row_cnt_reg(9), + O => \i__carry__0_i_5__1_n_0\ + ); +\i__carry__0_i_5__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \time_control_regs[0]\(23), + I1 => row_cnt_reg(10), + I2 => row_cnt_reg(11), + I3 => \time_control_regs[0]\(24), + O => \i__carry__0_i_5__2_n_0\ + ); +\i__carry__0_i_5__3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \col_cnt_reg_n_0_[8]\, + I1 => \col_cnt_reg_n_0_[9]\, + O => \i__carry__0_i_5__3_n_0\ + ); +\i__carry__0_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => total_cols(9), + I1 => \col_cnt_reg_n_0_[9]\, + I2 => total_cols(8), + I3 => \col_cnt_reg_n_0_[8]\, + O => \i__carry__0_i_6_n_0\ + ); +\i__carry__0_i_6__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \time_control_regs[0]\(21), + I1 => row_cnt_reg(8), + I2 => row_cnt_reg(9), + I3 => \time_control_regs[0]\(22), + O => \i__carry__0_i_6__0_n_0\ + ); +\i__carry__0_i_6__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \time_control_regs[0]\(21), + I1 => row_cnt_reg(8), + I2 => row_cnt_reg(9), + I3 => \time_control_regs[0]\(22), + O => \i__carry__0_i_6__1_n_0\ + ); +\i__carry_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => total_cols(6), + I1 => \col_cnt_reg_n_0_[6]\, + I2 => \col_cnt_reg_n_0_[7]\, + I3 => total_cols(7), + O => \i__carry_i_1_n_0\ + ); +\i__carry_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => total_cols(11), + I1 => \col_cnt_reg_n_0_[11]\, + I2 => \col_cnt_reg_n_0_[10]\, + I3 => total_cols(10), + I4 => total_cols(9), + I5 => \col_cnt_reg_n_0_[9]\, + O => \i__carry_i_1__0_n_0\ + ); +\i__carry_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => total_rows(10), + I1 => row_cnt_reg(10), + I2 => total_rows(11), + I3 => row_cnt_reg(11), + I4 => row_cnt_reg(9), + I5 => total_rows(9), + O => \i__carry_i_1__1_n_0\ + ); +\i__carry_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => row_cnt_reg(6), + I1 => \time_control_regs[0]\(19), + I2 => \time_control_regs[0]\(20), + I3 => row_cnt_reg(7), + O => \i__carry_i_1__2_n_0\ + ); +\i__carry_i_1__3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \time_control_regs[0]\(19), + I1 => row_cnt_reg(6), + I2 => row_cnt_reg(7), + I3 => \time_control_regs[0]\(20), + O => \i__carry_i_1__3_n_0\ + ); +\i__carry_i_1__4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"7" + ) + port map ( + I0 => \col_cnt_reg_n_0_[3]\, + I1 => \col_cnt_reg_n_0_[2]\, + O => \i__carry_i_1__4_n_0\ + ); +\i__carry_i_1__5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => row_cnt_reg(7), + I1 => row_cnt_reg(6), + O => \i__carry_i_1__5_n_0\ + ); +\i__carry_i_1__6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \col_cnt_reg_n_0_[7]\, + I1 => \col_cnt_reg_n_0_[6]\, + O => \i__carry_i_1__6_n_0\ + ); +\i__carry_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => total_cols(4), + I1 => \col_cnt_reg_n_0_[4]\, + I2 => \col_cnt_reg_n_0_[5]\, + I3 => total_cols(5), + O => \i__carry_i_2_n_0\ + ); +\i__carry_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => total_cols(7), + I1 => \col_cnt_reg_n_0_[7]\, + I2 => \col_cnt_reg_n_0_[6]\, + I3 => total_cols(6), + I4 => total_cols(8), + I5 => \col_cnt_reg_n_0_[8]\, + O => \i__carry_i_2__0_n_0\ + ); +\i__carry_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => total_rows(6), + I1 => row_cnt_reg(6), + I2 => total_rows(7), + I3 => row_cnt_reg(7), + I4 => row_cnt_reg(8), + I5 => total_rows(8), + O => \i__carry_i_2__1_n_0\ + ); +\i__carry_i_2__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => row_cnt_reg(4), + I1 => \time_control_regs[0]\(17), + I2 => \time_control_regs[0]\(18), + I3 => row_cnt_reg(5), + O => \i__carry_i_2__2_n_0\ + ); +\i__carry_i_2__3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \time_control_regs[0]\(17), + I1 => row_cnt_reg(4), + I2 => row_cnt_reg(5), + I3 => \time_control_regs[0]\(18), + O => \i__carry_i_2__3_n_0\ + ); +\i__carry_i_2__4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => row_cnt_reg(5), + I1 => row_cnt_reg(4), + O => \i__carry_i_2__4_n_0\ + ); +\i__carry_i_2__5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \col_cnt_reg_n_0_[5]\, + I1 => \col_cnt_reg_n_0_[4]\, + O => \i__carry_i_2__5_n_0\ + ); +\i__carry_i_2__6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \col_cnt_reg_n_0_[8]\, + I1 => \col_cnt_reg_n_0_[9]\, + O => \i__carry_i_2__6_n_0\ + ); +\i__carry_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => total_cols(2), + I1 => \col_cnt_reg_n_0_[2]\, + I2 => \col_cnt_reg_n_0_[3]\, + I3 => total_cols(3), + O => \i__carry_i_3_n_0\ + ); +\i__carry_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => total_cols(5), + I1 => \col_cnt_reg_n_0_[5]\, + I2 => \col_cnt_reg_n_0_[4]\, + I3 => total_cols(4), + I4 => total_cols(3), + I5 => \col_cnt_reg_n_0_[3]\, + O => \i__carry_i_3__0_n_0\ + ); +\i__carry_i_3__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => total_rows(4), + I1 => row_cnt_reg(4), + I2 => total_rows(5), + I3 => row_cnt_reg(5), + I4 => row_cnt_reg(3), + I5 => total_rows(3), + O => \i__carry_i_3__1_n_0\ + ); +\i__carry_i_3__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => row_cnt_reg(2), + I1 => \time_control_regs[0]\(15), + I2 => \time_control_regs[0]\(16), + I3 => row_cnt_reg(3), + O => \i__carry_i_3__2_n_0\ + ); +\i__carry_i_3__3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \time_control_regs[0]\(15), + I1 => row_cnt_reg(2), + I2 => row_cnt_reg(3), + I3 => \time_control_regs[0]\(16), + O => \i__carry_i_3__3_n_0\ + ); +\i__carry_i_3__4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => row_cnt_reg(3), + I1 => row_cnt_reg(2), + O => \i__carry_i_3__4_n_0\ + ); +\i__carry_i_3__5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \col_cnt_reg_n_0_[3]\, + I1 => \col_cnt_reg_n_0_[2]\, + O => \i__carry_i_3__5_n_0\ + ); +\i__carry_i_3__6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \col_cnt_reg_n_0_[6]\, + I1 => \col_cnt_reg_n_0_[7]\, + O => \i__carry_i_3__6_n_0\ + ); +\i__carry_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => total_cols(1), + I1 => \col_cnt_reg_n_0_[1]\, + I2 => \col_cnt_reg_n_0_[0]\, + I3 => total_cols(0), + I4 => total_cols(2), + I5 => \col_cnt_reg_n_0_[2]\, + O => \i__carry_i_4_n_0\ + ); +\i__carry_i_4__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => total_cols(0), + I1 => \col_cnt_reg_n_0_[0]\, + I2 => \col_cnt_reg_n_0_[1]\, + I3 => total_cols(1), + O => \i__carry_i_4__0_n_0\ + ); +\i__carry_i_4__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => total_rows(0), + I1 => row_cnt_reg(0), + I2 => total_rows(1), + I3 => row_cnt_reg(1), + I4 => row_cnt_reg(2), + I5 => total_rows(2), + O => \i__carry_i_4__1_n_0\ + ); +\i__carry_i_4__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => row_cnt_reg(0), + I1 => \time_control_regs[0]\(13), + I2 => \time_control_regs[0]\(14), + I3 => row_cnt_reg(1), + O => \i__carry_i_4__2_n_0\ + ); +\i__carry_i_4__3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \time_control_regs[0]\(13), + I1 => row_cnt_reg(0), + I2 => row_cnt_reg(1), + I3 => \time_control_regs[0]\(14), + O => \i__carry_i_4__3_n_0\ + ); +\i__carry_i_4__4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => row_cnt_reg(1), + I1 => row_cnt_reg(0), + O => \i__carry_i_4__4_n_0\ + ); +\i__carry_i_4__5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \col_cnt_reg_n_0_[4]\, + I1 => \col_cnt_reg_n_0_[5]\, + O => \i__carry_i_4__5_n_0\ + ); +\i__carry_i_4__6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \col_cnt_reg_n_0_[6]\, + I1 => \col_cnt_reg_n_0_[7]\, + O => \i__carry_i_4__6_n_0\ + ); +\i__carry_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => total_cols(6), + I1 => \col_cnt_reg_n_0_[6]\, + I2 => \col_cnt_reg_n_0_[7]\, + I3 => total_cols(7), + O => \i__carry_i_5_n_0\ + ); +\i__carry_i_5__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \time_control_regs[0]\(19), + I1 => row_cnt_reg(6), + I2 => row_cnt_reg(7), + I3 => \time_control_regs[0]\(20), + O => \i__carry_i_5__0_n_0\ + ); +\i__carry_i_5__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \time_control_regs[0]\(19), + I1 => row_cnt_reg(6), + I2 => row_cnt_reg(7), + I3 => \time_control_regs[0]\(20), + O => \i__carry_i_5__1_n_0\ + ); +\i__carry_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \col_cnt_reg_n_0_[2]\, + I1 => \col_cnt_reg_n_0_[3]\, + O => \i__carry_i_5__2_n_0\ + ); +\i__carry_i_5__3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => row_cnt_reg(6), + I1 => row_cnt_reg(7), + O => \i__carry_i_5__3_n_0\ + ); +\i__carry_i_5__4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \col_cnt_reg_n_0_[4]\, + I1 => \col_cnt_reg_n_0_[5]\, + O => \i__carry_i_5__4_n_0\ + ); +\i__carry_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => total_cols(4), + I1 => \col_cnt_reg_n_0_[4]\, + I2 => \col_cnt_reg_n_0_[5]\, + I3 => total_cols(5), + O => \i__carry_i_6_n_0\ + ); +\i__carry_i_6__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \time_control_regs[0]\(17), + I1 => row_cnt_reg(4), + I2 => row_cnt_reg(5), + I3 => \time_control_regs[0]\(18), + O => \i__carry_i_6__0_n_0\ + ); +\i__carry_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => row_cnt_reg(4), + I1 => row_cnt_reg(5), + O => \i__carry_i_6__1_n_0\ + ); +\i__carry_i_6__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \col_cnt_reg_n_0_[2]\, + I1 => \col_cnt_reg_n_0_[3]\, + O => \i__carry_i_6__2_n_0\ + ); +\i__carry_i_6__3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \time_control_regs[0]\(17), + I1 => row_cnt_reg(4), + I2 => row_cnt_reg(5), + I3 => \time_control_regs[0]\(18), + O => \i__carry_i_6__3_n_0\ + ); +\i__carry_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => total_cols(3), + I1 => \col_cnt_reg_n_0_[3]\, + I2 => total_cols(2), + I3 => \col_cnt_reg_n_0_[2]\, + O => \i__carry_i_7_n_0\ + ); +\i__carry_i_7__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \time_control_regs[0]\(15), + I1 => row_cnt_reg(2), + I2 => row_cnt_reg(3), + I3 => \time_control_regs[0]\(16), + O => \i__carry_i_7__0_n_0\ + ); +\i__carry_i_7__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => row_cnt_reg(2), + I1 => row_cnt_reg(3), + O => \i__carry_i_7__1_n_0\ + ); +\i__carry_i_7__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \col_cnt_reg_n_0_[0]\, + I1 => \col_cnt_reg_n_0_[1]\, + O => \i__carry_i_7__2_n_0\ + ); +\i__carry_i_7__3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \time_control_regs[0]\(15), + I1 => row_cnt_reg(2), + I2 => row_cnt_reg(3), + I3 => \time_control_regs[0]\(16), + O => \i__carry_i_7__3_n_0\ + ); +\i__carry_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => total_cols(0), + I1 => \col_cnt_reg_n_0_[0]\, + I2 => \col_cnt_reg_n_0_[1]\, + I3 => total_cols(1), + O => \i__carry_i_8_n_0\ + ); +\i__carry_i_8__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \time_control_regs[0]\(13), + I1 => row_cnt_reg(0), + I2 => row_cnt_reg(1), + I3 => \time_control_regs[0]\(14), + O => \i__carry_i_8__0_n_0\ + ); +\i__carry_i_8__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => row_cnt_reg(0), + I1 => row_cnt_reg(1), + O => \i__carry_i_8__1_n_0\ + ); +\i__carry_i_8__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \time_control_regs[0]\(13), + I1 => row_cnt_reg(0), + I2 => row_cnt_reg(1), + I3 => \time_control_regs[0]\(14), + O => \i__carry_i_8__2_n_0\ + ); +in_fifo_reset_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => in_fifo_reset, + I1 => \^in_fifo_reset_reg_0\, + O => in_fifo_reset0 + ); +in_fifo_reset_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"CECECECECECECEEE" + ) + port map ( + I0 => in_fifo_reset_i_3_n_0, + I1 => \^col_cnt_reg[1]_0\, + I2 => fifo_rd_i, + I3 => eol_late_i_i_2_n_0, + I4 => eol_expected_d, + I5 => \genr_control_regs[0]\(1), + O => \^in_fifo_reset_reg_0\ + ); +in_fifo_reset_i_3: unisim.vcomponents.LUT5 + generic map( + INIT => X"55030303" + ) + port map ( + I0 => \^sof_early_i_reg_1\, + I1 => eol_expected_d, + I2 => \^eol_late_i_reg_0\, + I3 => in_fifo_reset, + I4 => t_qb(0), + O => in_fifo_reset_i_3_n_0 + ); +in_fifo_reset_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^master_en\, + D => in_fifo_reset0, + Q => in_fifo_reset, + R => SR(0) + ); +\intc_if[0]_INST_0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0080" + ) + port map ( + I0 => core_en_i, + I1 => aclken, + I2 => \genr_control_regs[0]\(0), + I3 => \^eol_late_i_reg_0\, + O => E(0) + ); +\intc_if[4]_INST_0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \^sof_early_i_reg_1\, + I1 => \^sof_early_i_reg_0\, + I2 => \^intc_if\(4), + I3 => \^eol_late_i_reg_0\, + O => \^intc_if\(3) + ); +leqOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => leqOp_carry_n_0, + CO(2) => leqOp_carry_n_1, + CO(1) => leqOp_carry_n_2, + CO(0) => leqOp_carry_n_3, + CYINIT => '1', + DI(3) => leqOp_carry_i_1_n_0, + DI(2) => leqOp_carry_i_2_n_0, + DI(1) => leqOp_carry_i_3_n_0, + DI(0) => leqOp_carry_i_4_n_0, + O(3 downto 0) => NLW_leqOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => leqOp_carry_i_5_n_0, + S(2) => leqOp_carry_i_6_n_0, + S(1) => leqOp_carry_i_7_n_0, + S(0) => leqOp_carry_i_8_n_0 + ); +\leqOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => leqOp_carry_n_0, + CO(3) => \NLW_leqOp_carry__0_CO_UNCONNECTED\(3), + CO(2) => leqOp20_in, + CO(1) => \leqOp_carry__0_n_2\, + CO(0) => \leqOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => '0', + DI(2) => \leqOp_carry__0_i_1_n_0\, + DI(1) => \leqOp_carry__0_i_2_n_0\, + DI(0) => \leqOp_carry__0_i_3_n_0\, + O(3 downto 0) => \NLW_leqOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => '0', + S(2) => \leqOp_carry__0_i_4_n_0\, + S(1) => \leqOp_carry__0_i_5_n_0\, + S(0) => \leqOp_carry__0_i_6_n_0\ + ); +\leqOp_carry__0_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \time_control_regs[0]\(12), + I1 => \col_cnt_reg_n_0_[12]\, + O => \leqOp_carry__0_i_1_n_0\ + ); +\leqOp_carry__0_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"20F2" + ) + port map ( + I0 => \time_control_regs[0]\(10), + I1 => \col_cnt_reg_n_0_[10]\, + I2 => \time_control_regs[0]\(11), + I3 => \col_cnt_reg_n_0_[11]\, + O => \leqOp_carry__0_i_2_n_0\ + ); +\leqOp_carry__0_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"40F4" + ) + port map ( + I0 => \col_cnt_reg_n_0_[8]\, + I1 => \time_control_regs[0]\(8), + I2 => \time_control_regs[0]\(9), + I3 => \col_cnt_reg_n_0_[9]\, + O => \leqOp_carry__0_i_3_n_0\ + ); +\leqOp_carry__0_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \col_cnt_reg_n_0_[12]\, + I1 => \time_control_regs[0]\(12), + O => \leqOp_carry__0_i_4_n_0\ + ); +\leqOp_carry__0_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \time_control_regs[0]\(11), + I1 => \col_cnt_reg_n_0_[11]\, + I2 => \time_control_regs[0]\(10), + I3 => \col_cnt_reg_n_0_[10]\, + O => \leqOp_carry__0_i_5_n_0\ + ); +\leqOp_carry__0_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \time_control_regs[0]\(8), + I1 => \col_cnt_reg_n_0_[8]\, + I2 => \time_control_regs[0]\(9), + I3 => \col_cnt_reg_n_0_[9]\, + O => \leqOp_carry__0_i_6_n_0\ + ); +leqOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"20F2" + ) + port map ( + I0 => \time_control_regs[0]\(6), + I1 => \col_cnt_reg_n_0_[6]\, + I2 => \time_control_regs[0]\(7), + I3 => \col_cnt_reg_n_0_[7]\, + O => leqOp_carry_i_1_n_0 + ); +leqOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"20F2" + ) + port map ( + I0 => \time_control_regs[0]\(4), + I1 => \col_cnt_reg_n_0_[4]\, + I2 => \time_control_regs[0]\(5), + I3 => \col_cnt_reg_n_0_[5]\, + O => leqOp_carry_i_2_n_0 + ); +leqOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"40F4" + ) + port map ( + I0 => \col_cnt_reg_n_0_[2]\, + I1 => \time_control_regs[0]\(2), + I2 => \time_control_regs[0]\(3), + I3 => \col_cnt_reg_n_0_[3]\, + O => leqOp_carry_i_3_n_0 + ); +leqOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"20F2" + ) + port map ( + I0 => \time_control_regs[0]\(0), + I1 => \col_cnt_reg_n_0_[0]\, + I2 => \time_control_regs[0]\(1), + I3 => \col_cnt_reg_n_0_[1]\, + O => leqOp_carry_i_4_n_0 + ); +leqOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \time_control_regs[0]\(6), + I1 => \col_cnt_reg_n_0_[6]\, + I2 => \time_control_regs[0]\(7), + I3 => \col_cnt_reg_n_0_[7]\, + O => leqOp_carry_i_5_n_0 + ); +leqOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \time_control_regs[0]\(5), + I1 => \col_cnt_reg_n_0_[5]\, + I2 => \time_control_regs[0]\(4), + I3 => \col_cnt_reg_n_0_[4]\, + O => leqOp_carry_i_6_n_0 + ); +leqOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \time_control_regs[0]\(2), + I1 => \col_cnt_reg_n_0_[2]\, + I2 => \time_control_regs[0]\(3), + I3 => \col_cnt_reg_n_0_[3]\, + O => leqOp_carry_i_7_n_0 + ); +leqOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \time_control_regs[0]\(0), + I1 => \col_cnt_reg_n_0_[0]\, + I2 => \time_control_regs[0]\(1), + I3 => \col_cnt_reg_n_0_[1]\, + O => leqOp_carry_i_8_n_0 + ); +\leqOp_inferred__0/i__carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \leqOp_inferred__0/i__carry_n_0\, + CO(2) => \leqOp_inferred__0/i__carry_n_1\, + CO(1) => \leqOp_inferred__0/i__carry_n_2\, + CO(0) => \leqOp_inferred__0/i__carry_n_3\, + CYINIT => '1', + DI(3) => \i__carry_i_1_n_0\, + DI(2) => \i__carry_i_2_n_0\, + DI(1) => \i__carry_i_3_n_0\, + DI(0) => \i__carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_leqOp_inferred__0/i__carry_O_UNCONNECTED\(3 downto 0), + S(3) => \i__carry_i_5_n_0\, + S(2) => \i__carry_i_6_n_0\, + S(1) => \i__carry_i_7_n_0\, + S(0) => \i__carry_i_8_n_0\ + ); +\leqOp_inferred__0/i__carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \leqOp_inferred__0/i__carry_n_0\, + CO(3) => \NLW_leqOp_inferred__0/i__carry__0_CO_UNCONNECTED\(3), + CO(2) => leqOp23_in, + CO(1) => \leqOp_inferred__0/i__carry__0_n_2\, + CO(0) => \leqOp_inferred__0/i__carry__0_n_3\, + CYINIT => '0', + DI(3) => '0', + DI(2) => \i__carry__0_i_1_n_0\, + DI(1) => \i__carry__0_i_2_n_0\, + DI(0) => \i__carry__0_i_3_n_0\, + O(3 downto 0) => \NLW_leqOp_inferred__0/i__carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => '0', + S(2) => \i__carry__0_i_4__1_n_0\, + S(1) => \i__carry__0_i_5_n_0\, + S(0) => \i__carry__0_i_6_n_0\ + ); +\leqOp_inferred__1/i__carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \leqOp_inferred__1/i__carry_n_0\, + CO(2) => \leqOp_inferred__1/i__carry_n_1\, + CO(1) => \leqOp_inferred__1/i__carry_n_2\, + CO(0) => \leqOp_inferred__1/i__carry_n_3\, + CYINIT => '1', + DI(3) => \i__carry_i_1__3_n_0\, + DI(2) => \i__carry_i_2__3_n_0\, + DI(1) => \i__carry_i_3__3_n_0\, + DI(0) => \i__carry_i_4__3_n_0\, + O(3 downto 0) => \NLW_leqOp_inferred__1/i__carry_O_UNCONNECTED\(3 downto 0), + S(3) => \i__carry_i_5__0_n_0\, + S(2) => \i__carry_i_6__0_n_0\, + S(1) => \i__carry_i_7__0_n_0\, + S(0) => \i__carry_i_8__0_n_0\ + ); +\leqOp_inferred__1/i__carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \leqOp_inferred__1/i__carry_n_0\, + CO(3) => \NLW_leqOp_inferred__1/i__carry__0_CO_UNCONNECTED\(3), + CO(2) => leqOp16_in, + CO(1) => \leqOp_inferred__1/i__carry__0_n_2\, + CO(0) => \leqOp_inferred__1/i__carry__0_n_3\, + CYINIT => '0', + DI(3) => '0', + DI(2) => \i__carry__0_i_1__1_n_0\, + DI(1) => \i__carry__0_i_2__1_n_0\, + DI(0) => \i__carry__0_i_3__3_n_0\, + O(3 downto 0) => \NLW_leqOp_inferred__1/i__carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => '0', + S(2) => \i__carry__0_i_4__3_n_0\, + S(1) => \i__carry__0_i_5__0_n_0\, + S(0) => \i__carry__0_i_6__0_n_0\ + ); +line_cnt_tc_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFBFFF00008000" + ) + port map ( + I0 => line_cnt_tc_i_2_n_0, + I1 => aclken, + I2 => \genr_control_regs[0]\(0), + I3 => resetn_out, + I4 => line_cnt_tc_i_3_n_0, + I5 => \^intc_if\(2), + O => line_cnt_tc_i_1_n_0 + ); +line_cnt_tc_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"20000000" + ) + port map ( + I0 => line_cnt_tc_i_4_n_0, + I1 => line_cnt_tc_i_5_n_0, + I2 => row_cnt_reg(9), + I3 => row_cnt_reg(8), + I4 => row_cnt_reg(5), + O => line_cnt_tc_i_2_n_0 + ); +line_cnt_tc_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"FEFE0000FEFEEEFE" + ) + port map ( + I0 => \write_ptr_int_reg[2]_0\, + I1 => \read_ptr_int_reg[1]\, + I2 => line_cnt_tc_i_6_n_0, + I3 => leqOp20_in, + I4 => empty_match_reg, + I5 => \^co\(0), + O => line_cnt_tc_i_3_n_0 + ); +line_cnt_tc_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => row_cnt_reg(10), + I1 => row_cnt_reg(6), + I2 => row_cnt_reg(0), + I3 => row_cnt_reg(7), + I4 => row_cnt_reg(2), + I5 => row_cnt_reg(11), + O => line_cnt_tc_i_4_n_0 + ); +line_cnt_tc_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => row_cnt_reg(4), + I1 => row_cnt_reg(3), + I2 => row_cnt_reg(12), + I3 => row_cnt_reg(1), + O => line_cnt_tc_i_5_n_0 + ); +line_cnt_tc_i_6: unisim.vcomponents.LUT3 + generic map( + INIT => X"07" + ) + port map ( + I0 => gtOp22_in, + I1 => leqOp23_in, + I2 => gtOp21_in, + O => line_cnt_tc_i_6_n_0 + ); +line_cnt_tc_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => line_cnt_tc_i_1_n_0, + Q => \^intc_if\(2), + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3) => \NLW_ltOp_carry__0_CO_UNCONNECTED\(3), + CO(2) => \ltOp_carry__0_n_1\, + CO(1) => \ltOp_carry__0_n_2\, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => '0', + DI(2) => \ltOp_carry__0_i_1_n_0\, + DI(1) => \ltOp_carry__0_i_2_n_0\, + DI(0) => \ltOp_carry__0_i_3_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => '0', + S(2) => \ltOp_carry__0_i_4_n_0\, + S(1) => \ltOp_carry__0_i_5_n_0\, + S(0) => \ltOp_carry__0_i_6_n_0\ + ); +\ltOp_carry__0_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => total_rows(12), + I1 => row_cnt_reg(12), + O => \ltOp_carry__0_i_1_n_0\ + ); +\ltOp_carry__0_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => total_rows(11), + I1 => row_cnt_reg(11), + I2 => total_rows(10), + I3 => row_cnt_reg(10), + O => \ltOp_carry__0_i_2_n_0\ + ); +\ltOp_carry__0_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => total_rows(9), + I1 => row_cnt_reg(9), + I2 => total_rows(8), + I3 => row_cnt_reg(8), + O => \ltOp_carry__0_i_3_n_0\ + ); +\ltOp_carry__0_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => row_cnt_reg(12), + I1 => total_rows(12), + O => \ltOp_carry__0_i_4_n_0\ + ); +\ltOp_carry__0_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => row_cnt_reg(11), + I1 => total_rows(11), + I2 => row_cnt_reg(10), + I3 => total_rows(10), + O => \ltOp_carry__0_i_5_n_0\ + ); +\ltOp_carry__0_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => row_cnt_reg(9), + I1 => total_rows(9), + I2 => row_cnt_reg(8), + I3 => total_rows(8), + O => \ltOp_carry__0_i_6_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => total_rows(7), + I1 => row_cnt_reg(7), + I2 => total_rows(6), + I3 => row_cnt_reg(6), + O => ltOp_carry_i_1_n_0 + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => total_rows(5), + I1 => row_cnt_reg(5), + I2 => total_rows(4), + I3 => row_cnt_reg(4), + O => ltOp_carry_i_2_n_0 + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => total_rows(3), + I1 => row_cnt_reg(3), + I2 => total_rows(2), + I3 => row_cnt_reg(2), + O => ltOp_carry_i_3_n_0 + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"22B2" + ) + port map ( + I0 => total_rows(1), + I1 => row_cnt_reg(1), + I2 => total_rows(0), + I3 => row_cnt_reg(0), + O => ltOp_carry_i_4_n_0 + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => row_cnt_reg(7), + I1 => total_rows(7), + I2 => row_cnt_reg(6), + I3 => total_rows(6), + O => ltOp_carry_i_5_n_0 + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => row_cnt_reg(5), + I1 => total_rows(5), + I2 => row_cnt_reg(4), + I3 => total_rows(4), + O => ltOp_carry_i_6_n_0 + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => row_cnt_reg(3), + I1 => total_rows(3), + I2 => row_cnt_reg(2), + I3 => total_rows(2), + O => ltOp_carry_i_7_n_0 + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => row_cnt_reg(1), + I1 => total_rows(1), + I2 => row_cnt_reg(0), + I3 => total_rows(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_inferred__0/i__carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \ltOp_inferred__0/i__carry_n_0\, + CO(2) => \ltOp_inferred__0/i__carry_n_1\, + CO(1) => \ltOp_inferred__0/i__carry_n_2\, + CO(0) => \ltOp_inferred__0/i__carry_n_3\, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => \i__carry_i_1__4_n_0\, + O(3 downto 0) => \NLW_ltOp_inferred__0/i__carry_O_UNCONNECTED\(3 downto 0), + S(3) => \i__carry_i_2__6_n_0\, + S(2) => \i__carry_i_3__6_n_0\, + S(1) => \i__carry_i_4__5_n_0\, + S(0) => \i__carry_i_5__2_n_0\ + ); +\ltOp_inferred__0/i__carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_inferred__0/i__carry_n_0\, + CO(3 downto 2) => \NLW_ltOp_inferred__0/i__carry__0_CO_UNCONNECTED\(3 downto 2), + CO(1) => \^co\(0), + CO(0) => \ltOp_inferred__0/i__carry__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => \NLW_ltOp_inferred__0/i__carry__0_O_UNCONNECTED\(3 downto 0), + S(3 downto 2) => B"00", + S(1) => \i__carry__0_i_1__4_n_0\, + S(0) => \i__carry__0_i_2__4_n_0\ + ); +out_fifo_eol_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^master_en\, + D => eqOp1_out, + Q => da(0), + R => SR(0) + ); +out_fifo_sof_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000008" + ) + port map ( + I0 => sof_expected_i_2_n_0, + I1 => out_fifo_sof_i_2_n_0, + I2 => \col_cnt_reg_n_0_[11]\, + I3 => \col_cnt_reg_n_0_[10]\, + I4 => \col_cnt_reg_n_0_[7]\, + I5 => \col_cnt_reg_n_0_[6]\, + O => out_fifo_sof0 + ); +out_fifo_sof_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \col_cnt_reg_n_0_[2]\, + I1 => \col_cnt_reg_n_0_[3]\, + O => out_fifo_sof_i_2_n_0 + ); +out_fifo_sof_reg: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^master_en\, + D => out_fifo_sof0, + Q => da(1), + S => SR(0) + ); +pixel_cnt_tc_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFBFFF00008000" + ) + port map ( + I0 => eqOp, + I1 => aclken, + I2 => \genr_control_regs[0]\(0), + I3 => resetn_out, + I4 => line_cnt_tc_i_3_n_0, + I5 => \^intc_if\(1), + O => pixel_cnt_tc_i_1_n_0 + ); +pixel_cnt_tc_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"20000000" + ) + port map ( + I0 => pixel_cnt_tc_i_3_n_0, + I1 => pixel_cnt_tc_i_4_n_0, + I2 => \col_cnt_reg_n_0_[4]\, + I3 => \col_cnt_reg_n_0_[9]\, + I4 => \col_cnt_reg_n_0_[6]\, + O => eqOp + ); +pixel_cnt_tc_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => \col_cnt_reg_n_0_[3]\, + I1 => \col_cnt_reg_n_0_[2]\, + I2 => \col_cnt_reg_n_0_[0]\, + I3 => \col_cnt_reg_n_0_[12]\, + I4 => \col_cnt_reg_n_0_[5]\, + I5 => \col_cnt_reg_n_0_[7]\, + O => pixel_cnt_tc_i_3_n_0 + ); +pixel_cnt_tc_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => \col_cnt_reg_n_0_[10]\, + I1 => \col_cnt_reg_n_0_[8]\, + I2 => \col_cnt_reg_n_0_[11]\, + I3 => \col_cnt_reg_n_0_[1]\, + O => pixel_cnt_tc_i_4_n_0 + ); +pixel_cnt_tc_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => pixel_cnt_tc_i_1_n_0, + Q => \^intc_if\(1), + R => '0' + ); +\row_cnt[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000111FFFFFFFF" + ) + port map ( + I0 => \^col_cnt_reg[1]_0\, + I1 => line_cnt_tc_i_3_n_0, + I2 => \row_cnt[0]_i_4_n_0\, + I3 => \ltOp_carry__0_n_1\, + I4 => \col_cnt[12]_i_4_n_0\, + I5 => resetn_out, + O => \row_cnt[0]_i_1_n_0\ + ); +\row_cnt[0]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"04000000" + ) + port map ( + I0 => eol_late_i3_out, + I1 => geqOp, + I2 => line_cnt_tc_i_3_n_0, + I3 => aclken, + I4 => \genr_control_regs[0]\(0), + O => row_cnt + ); +\row_cnt[0]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"C000C33340004555" + ) + port map ( + I0 => \^sof_early_i_reg_0\, + I1 => sof_expected, + I2 => in_fifo_reset, + I3 => t_qb(1), + I4 => \^sof_early_i_reg_1\, + I5 => fifo_rd_d, + O => \row_cnt[0]_i_4_n_0\ + ); +\row_cnt[0]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => row_cnt_reg(3), + O => \row_cnt[0]_i_5_n_0\ + ); +\row_cnt[0]_i_6\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => row_cnt_reg(2), + O => \row_cnt[0]_i_6_n_0\ + ); +\row_cnt[0]_i_7\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => row_cnt_reg(1), + O => \row_cnt[0]_i_7_n_0\ + ); +\row_cnt[0]_i_8\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => row_cnt_reg(0), + O => \row_cnt[0]_i_8_n_0\ + ); +\row_cnt[12]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => row_cnt_reg(12), + O => \row_cnt[12]_i_2_n_0\ + ); +\row_cnt[4]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => row_cnt_reg(7), + O => \row_cnt[4]_i_2_n_0\ + ); +\row_cnt[4]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => row_cnt_reg(6), + O => \row_cnt[4]_i_3_n_0\ + ); +\row_cnt[4]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => row_cnt_reg(5), + O => \row_cnt[4]_i_4_n_0\ + ); +\row_cnt[4]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => row_cnt_reg(4), + O => \row_cnt[4]_i_5_n_0\ + ); +\row_cnt[8]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => row_cnt_reg(11), + O => \row_cnt[8]_i_2_n_0\ + ); +\row_cnt[8]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => row_cnt_reg(10), + O => \row_cnt[8]_i_3_n_0\ + ); +\row_cnt[8]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => row_cnt_reg(9), + O => \row_cnt[8]_i_4_n_0\ + ); +\row_cnt[8]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => row_cnt_reg(8), + O => \row_cnt[8]_i_5_n_0\ + ); +\row_cnt_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => aclk, + CE => row_cnt, + D => \row_cnt_reg[0]_i_3_n_7\, + Q => row_cnt_reg(0), + S => \row_cnt[0]_i_1_n_0\ + ); +\row_cnt_reg[0]_i_3\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \row_cnt_reg[0]_i_3_n_0\, + CO(2) => \row_cnt_reg[0]_i_3_n_1\, + CO(1) => \row_cnt_reg[0]_i_3_n_2\, + CO(0) => \row_cnt_reg[0]_i_3_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \row_cnt_reg[0]_i_3_n_4\, + O(2) => \row_cnt_reg[0]_i_3_n_5\, + O(1) => \row_cnt_reg[0]_i_3_n_6\, + O(0) => \row_cnt_reg[0]_i_3_n_7\, + S(3) => \row_cnt[0]_i_5_n_0\, + S(2) => \row_cnt[0]_i_6_n_0\, + S(1) => \row_cnt[0]_i_7_n_0\, + S(0) => \row_cnt[0]_i_8_n_0\ + ); +\row_cnt_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => row_cnt, + D => \row_cnt_reg[8]_i_1_n_5\, + Q => row_cnt_reg(10), + R => \row_cnt[0]_i_1_n_0\ + ); +\row_cnt_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => row_cnt, + D => \row_cnt_reg[8]_i_1_n_4\, + Q => row_cnt_reg(11), + R => \row_cnt[0]_i_1_n_0\ + ); +\row_cnt_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => row_cnt, + D => \row_cnt_reg[12]_i_1_n_7\, + Q => row_cnt_reg(12), + R => \row_cnt[0]_i_1_n_0\ + ); +\row_cnt_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \row_cnt_reg[8]_i_1_n_0\, + CO(3 downto 0) => \NLW_row_cnt_reg[12]_i_1_CO_UNCONNECTED\(3 downto 0), + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 1) => \NLW_row_cnt_reg[12]_i_1_O_UNCONNECTED\(3 downto 1), + O(0) => \row_cnt_reg[12]_i_1_n_7\, + S(3 downto 1) => B"000", + S(0) => \row_cnt[12]_i_2_n_0\ + ); +\row_cnt_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => row_cnt, + D => \row_cnt_reg[0]_i_3_n_6\, + Q => row_cnt_reg(1), + R => \row_cnt[0]_i_1_n_0\ + ); +\row_cnt_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => row_cnt, + D => \row_cnt_reg[0]_i_3_n_5\, + Q => row_cnt_reg(2), + R => \row_cnt[0]_i_1_n_0\ + ); +\row_cnt_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => row_cnt, + D => \row_cnt_reg[0]_i_3_n_4\, + Q => row_cnt_reg(3), + R => \row_cnt[0]_i_1_n_0\ + ); +\row_cnt_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => row_cnt, + D => \row_cnt_reg[4]_i_1_n_7\, + Q => row_cnt_reg(4), + R => \row_cnt[0]_i_1_n_0\ + ); +\row_cnt_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \row_cnt_reg[0]_i_3_n_0\, + CO(3) => \row_cnt_reg[4]_i_1_n_0\, + CO(2) => \row_cnt_reg[4]_i_1_n_1\, + CO(1) => \row_cnt_reg[4]_i_1_n_2\, + CO(0) => \row_cnt_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \row_cnt_reg[4]_i_1_n_4\, + O(2) => \row_cnt_reg[4]_i_1_n_5\, + O(1) => \row_cnt_reg[4]_i_1_n_6\, + O(0) => \row_cnt_reg[4]_i_1_n_7\, + S(3) => \row_cnt[4]_i_2_n_0\, + S(2) => \row_cnt[4]_i_3_n_0\, + S(1) => \row_cnt[4]_i_4_n_0\, + S(0) => \row_cnt[4]_i_5_n_0\ + ); +\row_cnt_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => row_cnt, + D => \row_cnt_reg[4]_i_1_n_6\, + Q => row_cnt_reg(5), + R => \row_cnt[0]_i_1_n_0\ + ); +\row_cnt_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => row_cnt, + D => \row_cnt_reg[4]_i_1_n_5\, + Q => row_cnt_reg(6), + R => \row_cnt[0]_i_1_n_0\ + ); +\row_cnt_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => row_cnt, + D => \row_cnt_reg[4]_i_1_n_4\, + Q => row_cnt_reg(7), + R => \row_cnt[0]_i_1_n_0\ + ); +\row_cnt_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => row_cnt, + D => \row_cnt_reg[8]_i_1_n_7\, + Q => row_cnt_reg(8), + R => \row_cnt[0]_i_1_n_0\ + ); +\row_cnt_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \row_cnt_reg[4]_i_1_n_0\, + CO(3) => \row_cnt_reg[8]_i_1_n_0\, + CO(2) => \row_cnt_reg[8]_i_1_n_1\, + CO(1) => \row_cnt_reg[8]_i_1_n_2\, + CO(0) => \row_cnt_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \row_cnt_reg[8]_i_1_n_4\, + O(2) => \row_cnt_reg[8]_i_1_n_5\, + O(1) => \row_cnt_reg[8]_i_1_n_6\, + O(0) => \row_cnt_reg[8]_i_1_n_7\, + S(3) => \row_cnt[8]_i_2_n_0\, + S(2) => \row_cnt[8]_i_3_n_0\, + S(1) => \row_cnt[8]_i_4_n_0\, + S(0) => \row_cnt[8]_i_5_n_0\ + ); +\row_cnt_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => row_cnt, + D => \row_cnt_reg[8]_i_1_n_6\, + Q => row_cnt_reg(9), + R => \row_cnt[0]_i_1_n_0\ + ); +sof_early_i_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"5755555502000000" + ) + port map ( + I0 => fifo_rd_d, + I1 => sof_expected, + I2 => \^sof_early_i_reg_1\, + I3 => in_fifo_reset, + I4 => t_qb(1), + I5 => \^sof_early_i_reg_0\, + O => sof_early_i_i_1_n_0 + ); +sof_early_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^master_en\, + D => sof_early_i_i_1_n_0, + Q => \^sof_early_i_reg_0\, + R => SR(0) + ); +sof_expected_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000200000000" + ) + port map ( + I0 => sof_expected_i_2_n_0, + I1 => \col_cnt_reg_n_0_[2]\, + I2 => \col_cnt_reg_n_0_[3]\, + I3 => \col_cnt_reg_n_0_[11]\, + I4 => \col_cnt_reg_n_0_[10]\, + I5 => sof_expected_i_3_n_0, + O => sof_expected0 + ); +sof_expected_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000020000" + ) + port map ( + I0 => sof_expected_i_4_n_0, + I1 => sof_expected_i_5_n_0, + I2 => \col_cnt_reg_n_0_[12]\, + I3 => \col_cnt_reg_n_0_[0]\, + I4 => \col_cnt_reg_n_0_[1]\, + I5 => row_cnt_reg(12), + O => sof_expected_i_2_n_0 + ); +sof_expected_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \col_cnt_reg_n_0_[6]\, + I1 => \col_cnt_reg_n_0_[7]\, + O => sof_expected_i_3_n_0 + ); +sof_expected_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"0004000000000000" + ) + port map ( + I0 => row_cnt_reg(1), + I1 => row_cnt_reg(0), + I2 => row_cnt_reg(2), + I3 => row_cnt_reg(3), + I4 => sof_expected_i_6_n_0, + I5 => sof_expected_i_7_n_0, + O => sof_expected_i_4_n_0 + ); +sof_expected_i_5: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFDFF" + ) + port map ( + I0 => sof_expected_i_8_n_0, + I1 => row_cnt_reg(8), + I2 => row_cnt_reg(9), + I3 => sof_expected_i_9_n_0, + I4 => row_cnt_reg(4), + I5 => row_cnt_reg(5), + O => sof_expected_i_5_n_0 + ); +sof_expected_i_6: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => row_cnt_reg(10), + I1 => row_cnt_reg(11), + O => sof_expected_i_6_n_0 + ); +sof_expected_i_7: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => row_cnt_reg(6), + I1 => row_cnt_reg(7), + O => sof_expected_i_7_n_0 + ); +sof_expected_i_8: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \col_cnt_reg_n_0_[8]\, + I1 => \col_cnt_reg_n_0_[9]\, + O => sof_expected_i_8_n_0 + ); +sof_expected_i_9: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \col_cnt_reg_n_0_[4]\, + I1 => \col_cnt_reg_n_0_[5]\, + O => sof_expected_i_9_n_0 + ); +sof_expected_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^master_en\, + D => sof_expected0, + Q => sof_expected, + R => SR(0) + ); +sof_late_i_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \genr_control_regs[0]\(0), + I1 => aclken, + O => \^master_en\ + ); +sof_late_i_i_3: unisim.vcomponents.LUT5 + generic map( + INIT => X"3F2A3F00" + ) + port map ( + I0 => sof_expected, + I1 => in_fifo_reset, + I2 => t_qb(1), + I3 => \^sof_early_i_reg_1\, + I4 => fifo_rd_d, + O => sof_late_i2_out + ); +sof_late_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^master_en\, + D => sof_late_i2_out, + Q => \^sof_early_i_reg_1\, + R => SR(0) + ); +\total_cols[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \time_control_regs[0]\(0), + O => plusOp(0) + ); +\total_cols[12]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \time_control_regs[0]\(12), + O => \total_cols[12]_i_2_n_0\ + ); +\total_cols[12]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \time_control_regs[0]\(11), + O => \total_cols[12]_i_3_n_0\ + ); +\total_cols[12]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \time_control_regs[0]\(10), + O => \total_cols[12]_i_4_n_0\ + ); +\total_cols[12]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \time_control_regs[0]\(9), + O => \total_cols[12]_i_5_n_0\ + ); +\total_cols[4]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \time_control_regs[0]\(4), + O => \total_cols[4]_i_2_n_0\ + ); +\total_cols[4]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \time_control_regs[0]\(3), + O => \total_cols[4]_i_3_n_0\ + ); +\total_cols[4]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \time_control_regs[0]\(2), + O => \total_cols[4]_i_4_n_0\ + ); +\total_cols[4]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \time_control_regs[0]\(1), + O => \total_cols[4]_i_5_n_0\ + ); +\total_cols[8]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \time_control_regs[0]\(8), + O => \total_cols[8]_i_2_n_0\ + ); +\total_cols[8]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \time_control_regs[0]\(7), + O => \total_cols[8]_i_3_n_0\ + ); +\total_cols[8]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \time_control_regs[0]\(6), + O => \total_cols[8]_i_4_n_0\ + ); +\total_cols[8]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \time_control_regs[0]\(5), + O => \total_cols[8]_i_5_n_0\ + ); +\total_cols_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => plusOp(0), + Q => total_cols(0), + R => '0' + ); +\total_cols_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => plusOp(10), + Q => total_cols(10), + R => '0' + ); +\total_cols_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => plusOp(11), + Q => total_cols(11), + R => '0' + ); +\total_cols_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => plusOp(12), + Q => total_cols(12), + R => '0' + ); +\total_cols_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \total_cols_reg[8]_i_1_n_0\, + CO(3) => \NLW_total_cols_reg[12]_i_1_CO_UNCONNECTED\(3), + CO(2) => \total_cols_reg[12]_i_1_n_1\, + CO(1) => \total_cols_reg[12]_i_1_n_2\, + CO(0) => \total_cols_reg[12]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => plusOp(12 downto 9), + S(3) => \total_cols[12]_i_2_n_0\, + S(2) => \total_cols[12]_i_3_n_0\, + S(1) => \total_cols[12]_i_4_n_0\, + S(0) => \total_cols[12]_i_5_n_0\ + ); +\total_cols_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => plusOp(1), + Q => total_cols(1), + R => '0' + ); +\total_cols_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => plusOp(2), + Q => total_cols(2), + R => '0' + ); +\total_cols_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => plusOp(3), + Q => total_cols(3), + R => '0' + ); +\total_cols_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => plusOp(4), + Q => total_cols(4), + R => '0' + ); +\total_cols_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \total_cols_reg[4]_i_1_n_0\, + CO(2) => \total_cols_reg[4]_i_1_n_1\, + CO(1) => \total_cols_reg[4]_i_1_n_2\, + CO(0) => \total_cols_reg[4]_i_1_n_3\, + CYINIT => \time_control_regs[0]\(0), + DI(3) => '0', + DI(2 downto 1) => \time_control_regs[0]\(3 downto 2), + DI(0) => '0', + O(3 downto 0) => plusOp(4 downto 1), + S(3) => \total_cols[4]_i_2_n_0\, + S(2) => \total_cols[4]_i_3_n_0\, + S(1) => \total_cols[4]_i_4_n_0\, + S(0) => \total_cols[4]_i_5_n_0\ + ); +\total_cols_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => plusOp(5), + Q => total_cols(5), + R => '0' + ); +\total_cols_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => plusOp(6), + Q => total_cols(6), + R => '0' + ); +\total_cols_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => plusOp(7), + Q => total_cols(7), + R => '0' + ); +\total_cols_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => plusOp(8), + Q => total_cols(8), + R => '0' + ); +\total_cols_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \total_cols_reg[4]_i_1_n_0\, + CO(3) => \total_cols_reg[8]_i_1_n_0\, + CO(2) => \total_cols_reg[8]_i_1_n_1\, + CO(1) => \total_cols_reg[8]_i_1_n_2\, + CO(0) => \total_cols_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => plusOp(8 downto 5), + S(3) => \total_cols[8]_i_2_n_0\, + S(2) => \total_cols[8]_i_3_n_0\, + S(1) => \total_cols[8]_i_4_n_0\, + S(0) => \total_cols[8]_i_5_n_0\ + ); +\total_cols_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => plusOp(9), + Q => total_cols(9), + R => '0' + ); +\total_rows_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \time_control_regs[0]\(13), + Q => total_rows(0), + R => '0' + ); +\total_rows_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \time_control_regs[0]\(23), + Q => total_rows(10), + R => '0' + ); +\total_rows_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \time_control_regs[0]\(24), + Q => total_rows(11), + R => '0' + ); +\total_rows_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \time_control_regs[0]\(25), + Q => total_rows(12), + R => '0' + ); +\total_rows_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \time_control_regs[0]\(14), + Q => total_rows(1), + R => '0' + ); +\total_rows_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \time_control_regs[0]\(15), + Q => total_rows(2), + R => '0' + ); +\total_rows_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \time_control_regs[0]\(16), + Q => total_rows(3), + R => '0' + ); +\total_rows_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \time_control_regs[0]\(17), + Q => total_rows(4), + R => '0' + ); +\total_rows_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \time_control_regs[0]\(18), + Q => total_rows(5), + R => '0' + ); +\total_rows_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \time_control_regs[0]\(19), + Q => total_rows(6), + R => '0' + ); +\total_rows_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \time_control_regs[0]\(20), + Q => total_rows(7), + R => '0' + ); +\total_rows_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \time_control_regs[0]\(21), + Q => total_rows(8), + R => '0' + ); +\total_rows_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \time_control_regs[0]\(22), + Q => total_rows(9), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_rgb2ycrcb_0_0_delay is + port ( + y_intb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 7 downto 0 ); + aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_rgb2ycrcb_0_0_delay : entity is "delay"; +end Arty_Z7_20_v_rgb2ycrcb_0_0_delay; + +architecture STRUCTURE of Arty_Z7_20_v_rgb2ycrcb_0_0_delay is + signal \needs_delay.shift_register_reg[3][0]_srl3_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[3][1]_srl3_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[3][2]_srl3_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[3][3]_srl3_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[3][4]_srl3_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[3][5]_srl3_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[3][6]_srl3_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[3][7]_srl3_n_0\ : STD_LOGIC; + attribute srl_bus_name : string; + attribute srl_bus_name of \needs_delay.shift_register_reg[3][0]_srl3\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3] "; + attribute srl_name : string; + attribute srl_name of \needs_delay.shift_register_reg[3][0]_srl3\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3][0]_srl3 "; + attribute srl_bus_name of \needs_delay.shift_register_reg[3][1]_srl3\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3] "; + attribute srl_name of \needs_delay.shift_register_reg[3][1]_srl3\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3][1]_srl3 "; + attribute srl_bus_name of \needs_delay.shift_register_reg[3][2]_srl3\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3] "; + attribute srl_name of \needs_delay.shift_register_reg[3][2]_srl3\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3][2]_srl3 "; + attribute srl_bus_name of \needs_delay.shift_register_reg[3][3]_srl3\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3] "; + attribute srl_name of \needs_delay.shift_register_reg[3][3]_srl3\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3][3]_srl3 "; + attribute srl_bus_name of \needs_delay.shift_register_reg[3][4]_srl3\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3] "; + attribute srl_name of \needs_delay.shift_register_reg[3][4]_srl3\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3][4]_srl3 "; + attribute srl_bus_name of \needs_delay.shift_register_reg[3][5]_srl3\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3] "; + attribute srl_name of \needs_delay.shift_register_reg[3][5]_srl3\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3][5]_srl3 "; + attribute srl_bus_name of \needs_delay.shift_register_reg[3][6]_srl3\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3] "; + attribute srl_name of \needs_delay.shift_register_reg[3][6]_srl3\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3][6]_srl3 "; + attribute srl_bus_name of \needs_delay.shift_register_reg[3][7]_srl3\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3] "; + attribute srl_name of \needs_delay.shift_register_reg[3][7]_srl3\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_G/needs_delay.shift_register_reg[3][7]_srl3 "; +begin +\needs_delay.shift_register_reg[3][0]_srl3\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '0', + A1 => '1', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => Q(0), + Q => \needs_delay.shift_register_reg[3][0]_srl3_n_0\ + ); +\needs_delay.shift_register_reg[3][1]_srl3\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '0', + A1 => '1', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => Q(1), + Q => \needs_delay.shift_register_reg[3][1]_srl3_n_0\ + ); +\needs_delay.shift_register_reg[3][2]_srl3\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '0', + A1 => '1', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => Q(2), + Q => \needs_delay.shift_register_reg[3][2]_srl3_n_0\ + ); +\needs_delay.shift_register_reg[3][3]_srl3\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '0', + A1 => '1', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => Q(3), + Q => \needs_delay.shift_register_reg[3][3]_srl3_n_0\ + ); +\needs_delay.shift_register_reg[3][4]_srl3\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '0', + A1 => '1', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => Q(4), + Q => \needs_delay.shift_register_reg[3][4]_srl3_n_0\ + ); +\needs_delay.shift_register_reg[3][5]_srl3\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '0', + A1 => '1', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => Q(5), + Q => \needs_delay.shift_register_reg[3][5]_srl3_n_0\ + ); +\needs_delay.shift_register_reg[3][6]_srl3\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '0', + A1 => '1', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => Q(6), + Q => \needs_delay.shift_register_reg[3][6]_srl3_n_0\ + ); +\needs_delay.shift_register_reg[3][7]_srl3\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '0', + A1 => '1', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => Q(7), + Q => \needs_delay.shift_register_reg[3][7]_srl3_n_0\ + ); +\needs_delay.shift_register_reg[4][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[3][0]_srl3_n_0\, + Q => y_intb(0), + R => '0' + ); +\needs_delay.shift_register_reg[4][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[3][1]_srl3_n_0\, + Q => y_intb(1), + R => '0' + ); +\needs_delay.shift_register_reg[4][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[3][2]_srl3_n_0\, + Q => y_intb(2), + R => '0' + ); +\needs_delay.shift_register_reg[4][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[3][3]_srl3_n_0\, + Q => y_intb(3), + R => '0' + ); +\needs_delay.shift_register_reg[4][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[3][4]_srl3_n_0\, + Q => y_intb(4), + R => '0' + ); +\needs_delay.shift_register_reg[4][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[3][5]_srl3_n_0\, + Q => y_intb(5), + R => '0' + ); +\needs_delay.shift_register_reg[4][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[3][6]_srl3_n_0\, + Q => y_intb(6), + R => '0' + ); +\needs_delay.shift_register_reg[4][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[3][7]_srl3_n_0\, + Q => y_intb(7), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_rgb2ycrcb_0_0_delay__parameterized0\ is + port ( + D : out STD_LOGIC_VECTOR ( 7 downto 0 ); + CO : out STD_LOGIC_VECTOR ( 0 to 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 7 downto 0 ); + aclk : in STD_LOGIC; + s : in STD_LOGIC_VECTOR ( 6 downto 0 ); + \needs_delay.shift_register_reg[1][0]\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_rgb2ycrcb_0_0_delay__parameterized0\ : entity is "delay"; +end \Arty_Z7_20_v_rgb2ycrcb_0_0_delay__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_v_rgb2ycrcb_0_0_delay__parameterized0\ is + signal b_int : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \needs_delay.shift_register[1][3]_i_3__2_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][3]_i_4__2_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][3]_i_5__2_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][3]_i_6__0_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][7]_i_2__2_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][7]_i_3__2_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][7]_i_4__2_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][7]_i_5__2_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1__1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1__1_n_1\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1__1_n_2\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1__1_n_3\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][7]_i_1__1_n_1\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][7]_i_1__1_n_2\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][7]_i_1__1_n_3\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[4][0]_srl4_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[4][1]_srl4_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[4][2]_srl4_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[4][3]_srl4_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[4][4]_srl4_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[4][5]_srl4_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[4][6]_srl4_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[4][7]_srl4_n_0\ : STD_LOGIC; + attribute srl_bus_name : string; + attribute srl_bus_name of \needs_delay.shift_register_reg[4][0]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4] "; + attribute srl_name : string; + attribute srl_name of \needs_delay.shift_register_reg[4][0]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4][0]_srl4 "; + attribute srl_bus_name of \needs_delay.shift_register_reg[4][1]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4] "; + attribute srl_name of \needs_delay.shift_register_reg[4][1]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4][1]_srl4 "; + attribute srl_bus_name of \needs_delay.shift_register_reg[4][2]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4] "; + attribute srl_name of \needs_delay.shift_register_reg[4][2]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4][2]_srl4 "; + attribute srl_bus_name of \needs_delay.shift_register_reg[4][3]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4] "; + attribute srl_name of \needs_delay.shift_register_reg[4][3]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4][3]_srl4 "; + attribute srl_bus_name of \needs_delay.shift_register_reg[4][4]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4] "; + attribute srl_name of \needs_delay.shift_register_reg[4][4]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4][4]_srl4 "; + attribute srl_bus_name of \needs_delay.shift_register_reg[4][5]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4] "; + attribute srl_name of \needs_delay.shift_register_reg[4][5]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4][5]_srl4 "; + attribute srl_bus_name of \needs_delay.shift_register_reg[4][6]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4] "; + attribute srl_name of \needs_delay.shift_register_reg[4][6]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4][6]_srl4 "; + attribute srl_bus_name of \needs_delay.shift_register_reg[4][7]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4] "; + attribute srl_name of \needs_delay.shift_register_reg[4][7]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_B/needs_delay.shift_register_reg[4][7]_srl4 "; +begin +\needs_delay.shift_register[1][3]_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => b_int(3), + I1 => s(2), + O => \needs_delay.shift_register[1][3]_i_3__2_n_0\ + ); +\needs_delay.shift_register[1][3]_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => b_int(2), + I1 => s(1), + O => \needs_delay.shift_register[1][3]_i_4__2_n_0\ + ); +\needs_delay.shift_register[1][3]_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => b_int(1), + I1 => s(0), + O => \needs_delay.shift_register[1][3]_i_5__2_n_0\ + ); +\needs_delay.shift_register[1][3]_i_6__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => b_int(0), + O => \needs_delay.shift_register[1][3]_i_6__0_n_0\ + ); +\needs_delay.shift_register[1][7]_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => b_int(7), + I1 => s(6), + O => \needs_delay.shift_register[1][7]_i_2__2_n_0\ + ); +\needs_delay.shift_register[1][7]_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => b_int(6), + I1 => s(5), + O => \needs_delay.shift_register[1][7]_i_3__2_n_0\ + ); +\needs_delay.shift_register[1][7]_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => b_int(5), + I1 => s(4), + O => \needs_delay.shift_register[1][7]_i_4__2_n_0\ + ); +\needs_delay.shift_register[1][7]_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => b_int(4), + I1 => s(3), + O => \needs_delay.shift_register[1][7]_i_5__2_n_0\ + ); +\needs_delay.shift_register_reg[1][3]_i_1__1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \needs_delay.shift_register_reg[1][3]_i_1__1_n_0\, + CO(2) => \needs_delay.shift_register_reg[1][3]_i_1__1_n_1\, + CO(1) => \needs_delay.shift_register_reg[1][3]_i_1__1_n_2\, + CO(0) => \needs_delay.shift_register_reg[1][3]_i_1__1_n_3\, + CYINIT => \needs_delay.shift_register_reg[1][0]\, + DI(3 downto 0) => b_int(3 downto 0), + O(3 downto 0) => D(3 downto 0), + S(3) => \needs_delay.shift_register[1][3]_i_3__2_n_0\, + S(2) => \needs_delay.shift_register[1][3]_i_4__2_n_0\, + S(1) => \needs_delay.shift_register[1][3]_i_5__2_n_0\, + S(0) => \needs_delay.shift_register[1][3]_i_6__0_n_0\ + ); +\needs_delay.shift_register_reg[1][7]_i_1__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \needs_delay.shift_register_reg[1][3]_i_1__1_n_0\, + CO(3) => CO(0), + CO(2) => \needs_delay.shift_register_reg[1][7]_i_1__1_n_1\, + CO(1) => \needs_delay.shift_register_reg[1][7]_i_1__1_n_2\, + CO(0) => \needs_delay.shift_register_reg[1][7]_i_1__1_n_3\, + CYINIT => '0', + DI(3 downto 0) => b_int(7 downto 4), + O(3 downto 0) => D(7 downto 4), + S(3) => \needs_delay.shift_register[1][7]_i_2__2_n_0\, + S(2) => \needs_delay.shift_register[1][7]_i_3__2_n_0\, + S(1) => \needs_delay.shift_register[1][7]_i_4__2_n_0\, + S(0) => \needs_delay.shift_register[1][7]_i_5__2_n_0\ + ); +\needs_delay.shift_register_reg[4][0]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '1', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => Q(0), + Q => \needs_delay.shift_register_reg[4][0]_srl4_n_0\ + ); +\needs_delay.shift_register_reg[4][1]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '1', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => Q(1), + Q => \needs_delay.shift_register_reg[4][1]_srl4_n_0\ + ); +\needs_delay.shift_register_reg[4][2]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '1', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => Q(2), + Q => \needs_delay.shift_register_reg[4][2]_srl4_n_0\ + ); +\needs_delay.shift_register_reg[4][3]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '1', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => Q(3), + Q => \needs_delay.shift_register_reg[4][3]_srl4_n_0\ + ); +\needs_delay.shift_register_reg[4][4]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '1', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => Q(4), + Q => \needs_delay.shift_register_reg[4][4]_srl4_n_0\ + ); +\needs_delay.shift_register_reg[4][5]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '1', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => Q(5), + Q => \needs_delay.shift_register_reg[4][5]_srl4_n_0\ + ); +\needs_delay.shift_register_reg[4][6]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '1', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => Q(6), + Q => \needs_delay.shift_register_reg[4][6]_srl4_n_0\ + ); +\needs_delay.shift_register_reg[4][7]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '1', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => Q(7), + Q => \needs_delay.shift_register_reg[4][7]_srl4_n_0\ + ); +\needs_delay.shift_register_reg[5][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[4][0]_srl4_n_0\, + Q => b_int(0), + R => '0' + ); +\needs_delay.shift_register_reg[5][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[4][1]_srl4_n_0\, + Q => b_int(1), + R => '0' + ); +\needs_delay.shift_register_reg[5][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[4][2]_srl4_n_0\, + Q => b_int(2), + R => '0' + ); +\needs_delay.shift_register_reg[5][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[4][3]_srl4_n_0\, + Q => b_int(3), + R => '0' + ); +\needs_delay.shift_register_reg[5][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[4][4]_srl4_n_0\, + Q => b_int(4), + R => '0' + ); +\needs_delay.shift_register_reg[5][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[4][5]_srl4_n_0\, + Q => b_int(5), + R => '0' + ); +\needs_delay.shift_register_reg[5][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[4][6]_srl4_n_0\, + Q => b_int(6), + R => '0' + ); +\needs_delay.shift_register_reg[5][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[4][7]_srl4_n_0\, + Q => b_int(7), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_rgb2ycrcb_0_0_delay__parameterized1\ is + port ( + D : out STD_LOGIC_VECTOR ( 7 downto 0 ); + \needs_delay.shift_register_reg[1][10]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 7 downto 0 ); + aclk : in STD_LOGIC; + s : in STD_LOGIC_VECTOR ( 6 downto 0 ); + \needs_delay.shift_register_reg[1][0]\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_rgb2ycrcb_0_0_delay__parameterized1\ : entity is "delay"; +end \Arty_Z7_20_v_rgb2ycrcb_0_0_delay__parameterized1\; + +architecture STRUCTURE of \Arty_Z7_20_v_rgb2ycrcb_0_0_delay__parameterized1\ is + signal \needs_delay.shift_register[1][3]_i_2__2_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][3]_i_3__1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][3]_i_4__1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][3]_i_5__0_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][7]_i_2__1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][7]_i_3__1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][7]_i_4__1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][7]_i_5__1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1__2_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1__2_n_1\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1__2_n_2\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1__2_n_3\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][7]_i_1__2_n_1\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][7]_i_1__2_n_2\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][7]_i_1__2_n_3\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[4][0]_srl4_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[4][1]_srl4_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[4][2]_srl4_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[4][3]_srl4_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[4][4]_srl4_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[4][5]_srl4_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[4][6]_srl4_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[4][7]_srl4_n_0\ : STD_LOGIC; + signal r_int : STD_LOGIC_VECTOR ( 7 downto 0 ); + attribute srl_bus_name : string; + attribute srl_bus_name of \needs_delay.shift_register_reg[4][0]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4] "; + attribute srl_name : string; + attribute srl_name of \needs_delay.shift_register_reg[4][0]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4][0]_srl4 "; + attribute srl_bus_name of \needs_delay.shift_register_reg[4][1]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4] "; + attribute srl_name of \needs_delay.shift_register_reg[4][1]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4][1]_srl4 "; + attribute srl_bus_name of \needs_delay.shift_register_reg[4][2]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4] "; + attribute srl_name of \needs_delay.shift_register_reg[4][2]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4][2]_srl4 "; + attribute srl_bus_name of \needs_delay.shift_register_reg[4][3]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4] "; + attribute srl_name of \needs_delay.shift_register_reg[4][3]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4][3]_srl4 "; + attribute srl_bus_name of \needs_delay.shift_register_reg[4][4]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4] "; + attribute srl_name of \needs_delay.shift_register_reg[4][4]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4][4]_srl4 "; + attribute srl_bus_name of \needs_delay.shift_register_reg[4][5]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4] "; + attribute srl_name of \needs_delay.shift_register_reg[4][5]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4][5]_srl4 "; + attribute srl_bus_name of \needs_delay.shift_register_reg[4][6]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4] "; + attribute srl_name of \needs_delay.shift_register_reg[4][6]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4][6]_srl4 "; + attribute srl_bus_name of \needs_delay.shift_register_reg[4][7]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4] "; + attribute srl_name of \needs_delay.shift_register_reg[4][7]_srl4\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_R/needs_delay.shift_register_reg[4][7]_srl4 "; +begin +\needs_delay.shift_register[1][3]_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => r_int(3), + I1 => s(2), + O => \needs_delay.shift_register[1][3]_i_2__2_n_0\ + ); +\needs_delay.shift_register[1][3]_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => r_int(2), + I1 => s(1), + O => \needs_delay.shift_register[1][3]_i_3__1_n_0\ + ); +\needs_delay.shift_register[1][3]_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => r_int(1), + I1 => s(0), + O => \needs_delay.shift_register[1][3]_i_4__1_n_0\ + ); +\needs_delay.shift_register[1][3]_i_5__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => r_int(0), + O => \needs_delay.shift_register[1][3]_i_5__0_n_0\ + ); +\needs_delay.shift_register[1][7]_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => r_int(7), + I1 => s(6), + O => \needs_delay.shift_register[1][7]_i_2__1_n_0\ + ); +\needs_delay.shift_register[1][7]_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => r_int(6), + I1 => s(5), + O => \needs_delay.shift_register[1][7]_i_3__1_n_0\ + ); +\needs_delay.shift_register[1][7]_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => r_int(5), + I1 => s(4), + O => \needs_delay.shift_register[1][7]_i_4__1_n_0\ + ); +\needs_delay.shift_register[1][7]_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => r_int(4), + I1 => s(3), + O => \needs_delay.shift_register[1][7]_i_5__1_n_0\ + ); +\needs_delay.shift_register_reg[1][3]_i_1__2\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \needs_delay.shift_register_reg[1][3]_i_1__2_n_0\, + CO(2) => \needs_delay.shift_register_reg[1][3]_i_1__2_n_1\, + CO(1) => \needs_delay.shift_register_reg[1][3]_i_1__2_n_2\, + CO(0) => \needs_delay.shift_register_reg[1][3]_i_1__2_n_3\, + CYINIT => \needs_delay.shift_register_reg[1][0]\, + DI(3 downto 0) => r_int(3 downto 0), + O(3 downto 0) => D(3 downto 0), + S(3) => \needs_delay.shift_register[1][3]_i_2__2_n_0\, + S(2) => \needs_delay.shift_register[1][3]_i_3__1_n_0\, + S(1) => \needs_delay.shift_register[1][3]_i_4__1_n_0\, + S(0) => \needs_delay.shift_register[1][3]_i_5__0_n_0\ + ); +\needs_delay.shift_register_reg[1][7]_i_1__2\: unisim.vcomponents.CARRY4 + port map ( + CI => \needs_delay.shift_register_reg[1][3]_i_1__2_n_0\, + CO(3) => \needs_delay.shift_register_reg[1][10]\(0), + CO(2) => \needs_delay.shift_register_reg[1][7]_i_1__2_n_1\, + CO(1) => \needs_delay.shift_register_reg[1][7]_i_1__2_n_2\, + CO(0) => \needs_delay.shift_register_reg[1][7]_i_1__2_n_3\, + CYINIT => '0', + DI(3 downto 0) => r_int(7 downto 4), + O(3 downto 0) => D(7 downto 4), + S(3) => \needs_delay.shift_register[1][7]_i_2__1_n_0\, + S(2) => \needs_delay.shift_register[1][7]_i_3__1_n_0\, + S(1) => \needs_delay.shift_register[1][7]_i_4__1_n_0\, + S(0) => \needs_delay.shift_register[1][7]_i_5__1_n_0\ + ); +\needs_delay.shift_register_reg[4][0]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '1', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => Q(0), + Q => \needs_delay.shift_register_reg[4][0]_srl4_n_0\ + ); +\needs_delay.shift_register_reg[4][1]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '1', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => Q(1), + Q => \needs_delay.shift_register_reg[4][1]_srl4_n_0\ + ); +\needs_delay.shift_register_reg[4][2]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '1', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => Q(2), + Q => \needs_delay.shift_register_reg[4][2]_srl4_n_0\ + ); +\needs_delay.shift_register_reg[4][3]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '1', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => Q(3), + Q => \needs_delay.shift_register_reg[4][3]_srl4_n_0\ + ); +\needs_delay.shift_register_reg[4][4]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '1', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => Q(4), + Q => \needs_delay.shift_register_reg[4][4]_srl4_n_0\ + ); +\needs_delay.shift_register_reg[4][5]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '1', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => Q(5), + Q => \needs_delay.shift_register_reg[4][5]_srl4_n_0\ + ); +\needs_delay.shift_register_reg[4][6]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '1', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => Q(6), + Q => \needs_delay.shift_register_reg[4][6]_srl4_n_0\ + ); +\needs_delay.shift_register_reg[4][7]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '1', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => Q(7), + Q => \needs_delay.shift_register_reg[4][7]_srl4_n_0\ + ); +\needs_delay.shift_register_reg[5][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[4][0]_srl4_n_0\, + Q => r_int(0), + R => '0' + ); +\needs_delay.shift_register_reg[5][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[4][1]_srl4_n_0\, + Q => r_int(1), + R => '0' + ); +\needs_delay.shift_register_reg[5][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[4][2]_srl4_n_0\, + Q => r_int(2), + R => '0' + ); +\needs_delay.shift_register_reg[5][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[4][3]_srl4_n_0\, + Q => r_int(3), + R => '0' + ); +\needs_delay.shift_register_reg[5][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[4][4]_srl4_n_0\, + Q => r_int(4), + R => '0' + ); +\needs_delay.shift_register_reg[5][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[4][5]_srl4_n_0\, + Q => r_int(5), + R => '0' + ); +\needs_delay.shift_register_reg[5][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[4][6]_srl4_n_0\, + Q => r_int(6), + R => '0' + ); +\needs_delay.shift_register_reg[5][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[4][7]_srl4_n_0\, + Q => r_int(7), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_rgb2ycrcb_0_0_delay__parameterized2\ is + port ( + \needs_delay.shift_register_reg[1][9]\ : out STD_LOGIC; + \needs_delay.shift_register_reg[1][8]\ : out STD_LOGIC; + \needs_delay.shift_register_reg[1][7]\ : out STD_LOGIC; + \needs_delay.shift_register_reg[1][6]\ : out STD_LOGIC; + \needs_delay.shift_register_reg[1][5]\ : out STD_LOGIC; + \needs_delay.shift_register_reg[1][4]\ : out STD_LOGIC; + \needs_delay.shift_register_reg[1][3]\ : out STD_LOGIC; + \needs_delay.shift_register_reg[1][2]\ : out STD_LOGIC; + \needs_delay.shift_register_reg[1][1]\ : out STD_LOGIC; + \needs_delay.shift_register_reg[1][0]\ : out STD_LOGIC; + \needs_delay.shift_register_reg[1][9]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \needs_delay.shift_register_reg[1][9]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + S : out STD_LOGIC_VECTOR ( 3 downto 0 ); + DI : out STD_LOGIC_VECTOR ( 3 downto 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + \^s\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); + aclk : in STD_LOGIC; + \core_control_regs[0]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_rgb2ycrcb_0_0_delay__parameterized2\ : entity is "delay"; +end \Arty_Z7_20_v_rgb2ycrcb_0_0_delay__parameterized2\; + +architecture STRUCTURE of \Arty_Z7_20_v_rgb2ycrcb_0_0_delay__parameterized2\ is + signal \^needs_delay.shift_register_reg[1][0]\ : STD_LOGIC; + signal \^needs_delay.shift_register_reg[1][1]\ : STD_LOGIC; + signal \^needs_delay.shift_register_reg[1][2]\ : STD_LOGIC; + signal \^needs_delay.shift_register_reg[1][3]\ : STD_LOGIC; + signal \^needs_delay.shift_register_reg[1][4]\ : STD_LOGIC; + signal \^needs_delay.shift_register_reg[1][5]\ : STD_LOGIC; + signal \^needs_delay.shift_register_reg[1][6]\ : STD_LOGIC; + signal \^needs_delay.shift_register_reg[1][7]\ : STD_LOGIC; + signal \^needs_delay.shift_register_reg[1][8]\ : STD_LOGIC; + signal \^needs_delay.shift_register_reg[1][9]\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[2][0]_srl2_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[2][1]_srl2_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[2][2]_srl2_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[2][3]_srl2_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[2][4]_srl2_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[2][5]_srl2_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[2][6]_srl2_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[2][7]_srl2_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[2][8]_srl2_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[2][9]_srl2_n_0\ : STD_LOGIC; + attribute srl_bus_name : string; + attribute srl_bus_name of \needs_delay.shift_register_reg[2][0]_srl2\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2] "; + attribute srl_name : string; + attribute srl_name of \needs_delay.shift_register_reg[2][0]_srl2\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2][0]_srl2 "; + attribute srl_bus_name of \needs_delay.shift_register_reg[2][1]_srl2\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2] "; + attribute srl_name of \needs_delay.shift_register_reg[2][1]_srl2\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2][1]_srl2 "; + attribute srl_bus_name of \needs_delay.shift_register_reg[2][2]_srl2\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2] "; + attribute srl_name of \needs_delay.shift_register_reg[2][2]_srl2\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2][2]_srl2 "; + attribute srl_bus_name of \needs_delay.shift_register_reg[2][3]_srl2\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2] "; + attribute srl_name of \needs_delay.shift_register_reg[2][3]_srl2\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2][3]_srl2 "; + attribute srl_bus_name of \needs_delay.shift_register_reg[2][4]_srl2\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2] "; + attribute srl_name of \needs_delay.shift_register_reg[2][4]_srl2\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2][4]_srl2 "; + attribute srl_bus_name of \needs_delay.shift_register_reg[2][5]_srl2\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2] "; + attribute srl_name of \needs_delay.shift_register_reg[2][5]_srl2\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2][5]_srl2 "; + attribute srl_bus_name of \needs_delay.shift_register_reg[2][6]_srl2\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2] "; + attribute srl_name of \needs_delay.shift_register_reg[2][6]_srl2\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2][6]_srl2 "; + attribute srl_bus_name of \needs_delay.shift_register_reg[2][7]_srl2\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2] "; + attribute srl_name of \needs_delay.shift_register_reg[2][7]_srl2\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2][7]_srl2 "; + attribute srl_bus_name of \needs_delay.shift_register_reg[2][8]_srl2\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2] "; + attribute srl_name of \needs_delay.shift_register_reg[2][8]_srl2\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2][8]_srl2 "; + attribute srl_bus_name of \needs_delay.shift_register_reg[2][9]_srl2\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2] "; + attribute srl_name of \needs_delay.shift_register_reg[2][9]_srl2\ : label is "U0/\rgb2ycrcb_top_inst/intcore/del_Y/needs_delay.shift_register_reg[2][9]_srl2 "; +begin + \needs_delay.shift_register_reg[1][0]\ <= \^needs_delay.shift_register_reg[1][0]\; + \needs_delay.shift_register_reg[1][1]\ <= \^needs_delay.shift_register_reg[1][1]\; + \needs_delay.shift_register_reg[1][2]\ <= \^needs_delay.shift_register_reg[1][2]\; + \needs_delay.shift_register_reg[1][3]\ <= \^needs_delay.shift_register_reg[1][3]\; + \needs_delay.shift_register_reg[1][4]\ <= \^needs_delay.shift_register_reg[1][4]\; + \needs_delay.shift_register_reg[1][5]\ <= \^needs_delay.shift_register_reg[1][5]\; + \needs_delay.shift_register_reg[1][6]\ <= \^needs_delay.shift_register_reg[1][6]\; + \needs_delay.shift_register_reg[1][7]\ <= \^needs_delay.shift_register_reg[1][7]\; + \needs_delay.shift_register_reg[1][8]\ <= \^needs_delay.shift_register_reg[1][8]\; + \needs_delay.shift_register_reg[1][9]\ <= \^needs_delay.shift_register_reg[1][9]\; +\gtOp_carry__0_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^needs_delay.shift_register_reg[1][8]\, + I1 => \^needs_delay.shift_register_reg[1][9]\, + O => \needs_delay.shift_register_reg[1][9]_0\(0) + ); +\gtOp_carry__0_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^needs_delay.shift_register_reg[1][8]\, + I1 => \^needs_delay.shift_register_reg[1][9]\, + O => \needs_delay.shift_register_reg[1][9]_1\(0) + ); +\gtOp_carry_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \^needs_delay.shift_register_reg[1][6]\, + I1 => \core_control_regs[0]\(6), + I2 => \core_control_regs[0]\(7), + I3 => \^needs_delay.shift_register_reg[1][7]\, + O => DI(3) + ); +\gtOp_carry_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \^needs_delay.shift_register_reg[1][4]\, + I1 => \core_control_regs[0]\(4), + I2 => \core_control_regs[0]\(5), + I3 => \^needs_delay.shift_register_reg[1][5]\, + O => DI(2) + ); +\gtOp_carry_i_3__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \^needs_delay.shift_register_reg[1][2]\, + I1 => \core_control_regs[0]\(2), + I2 => \core_control_regs[0]\(3), + I3 => \^needs_delay.shift_register_reg[1][3]\, + O => DI(1) + ); +\gtOp_carry_i_4__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \^needs_delay.shift_register_reg[1][0]\, + I1 => \core_control_regs[0]\(0), + I2 => \core_control_regs[0]\(1), + I3 => \^needs_delay.shift_register_reg[1][1]\, + O => DI(0) + ); +\gtOp_carry_i_5__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \^needs_delay.shift_register_reg[1][6]\, + I1 => \core_control_regs[0]\(6), + I2 => \^needs_delay.shift_register_reg[1][7]\, + I3 => \core_control_regs[0]\(7), + O => S(3) + ); +\gtOp_carry_i_6__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \^needs_delay.shift_register_reg[1][4]\, + I1 => \core_control_regs[0]\(4), + I2 => \^needs_delay.shift_register_reg[1][5]\, + I3 => \core_control_regs[0]\(5), + O => S(2) + ); +\gtOp_carry_i_7__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \^needs_delay.shift_register_reg[1][2]\, + I1 => \core_control_regs[0]\(2), + I2 => \^needs_delay.shift_register_reg[1][3]\, + I3 => \core_control_regs[0]\(3), + O => S(1) + ); +\gtOp_carry_i_8__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \^needs_delay.shift_register_reg[1][0]\, + I1 => \core_control_regs[0]\(0), + I2 => \^needs_delay.shift_register_reg[1][1]\, + I3 => \core_control_regs[0]\(1), + O => S(0) + ); +\needs_delay.shift_register_reg[2][0]_srl2\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '0', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => \^s\(0), + Q => \needs_delay.shift_register_reg[2][0]_srl2_n_0\ + ); +\needs_delay.shift_register_reg[2][1]_srl2\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '0', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => \^s\(1), + Q => \needs_delay.shift_register_reg[2][1]_srl2_n_0\ + ); +\needs_delay.shift_register_reg[2][2]_srl2\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '0', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => \^s\(2), + Q => \needs_delay.shift_register_reg[2][2]_srl2_n_0\ + ); +\needs_delay.shift_register_reg[2][3]_srl2\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '0', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => \^s\(3), + Q => \needs_delay.shift_register_reg[2][3]_srl2_n_0\ + ); +\needs_delay.shift_register_reg[2][4]_srl2\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '0', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => \^s\(4), + Q => \needs_delay.shift_register_reg[2][4]_srl2_n_0\ + ); +\needs_delay.shift_register_reg[2][5]_srl2\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '0', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => \^s\(5), + Q => \needs_delay.shift_register_reg[2][5]_srl2_n_0\ + ); +\needs_delay.shift_register_reg[2][6]_srl2\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '0', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => \^s\(6), + Q => \needs_delay.shift_register_reg[2][6]_srl2_n_0\ + ); +\needs_delay.shift_register_reg[2][7]_srl2\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '0', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => \^s\(7), + Q => \needs_delay.shift_register_reg[2][7]_srl2_n_0\ + ); +\needs_delay.shift_register_reg[2][8]_srl2\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '0', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => \^s\(8), + Q => \needs_delay.shift_register_reg[2][8]_srl2_n_0\ + ); +\needs_delay.shift_register_reg[2][9]_srl2\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '0', + A2 => '0', + A3 => '0', + CE => E(0), + CLK => aclk, + D => \^s\(9), + Q => \needs_delay.shift_register_reg[2][9]_srl2_n_0\ + ); +\needs_delay.shift_register_reg[3][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[2][0]_srl2_n_0\, + Q => \^needs_delay.shift_register_reg[1][0]\, + R => '0' + ); +\needs_delay.shift_register_reg[3][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[2][1]_srl2_n_0\, + Q => \^needs_delay.shift_register_reg[1][1]\, + R => '0' + ); +\needs_delay.shift_register_reg[3][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[2][2]_srl2_n_0\, + Q => \^needs_delay.shift_register_reg[1][2]\, + R => '0' + ); +\needs_delay.shift_register_reg[3][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[2][3]_srl2_n_0\, + Q => \^needs_delay.shift_register_reg[1][3]\, + R => '0' + ); +\needs_delay.shift_register_reg[3][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[2][4]_srl2_n_0\, + Q => \^needs_delay.shift_register_reg[1][4]\, + R => '0' + ); +\needs_delay.shift_register_reg[3][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[2][5]_srl2_n_0\, + Q => \^needs_delay.shift_register_reg[1][5]\, + R => '0' + ); +\needs_delay.shift_register_reg[3][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[2][6]_srl2_n_0\, + Q => \^needs_delay.shift_register_reg[1][6]\, + R => '0' + ); +\needs_delay.shift_register_reg[3][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[2][7]_srl2_n_0\, + Q => \^needs_delay.shift_register_reg[1][7]\, + R => '0' + ); +\needs_delay.shift_register_reg[3][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[2][8]_srl2_n_0\, + Q => \^needs_delay.shift_register_reg[1][8]\, + R => '0' + ); +\needs_delay.shift_register_reg[3][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[2][9]_srl2_n_0\, + Q => \^needs_delay.shift_register_reg[1][9]\, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr is + port ( + out_s : out STD_LOGIC_VECTOR ( 8 downto 0 ); + p_0_in : out STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 15 downto 0 ); + sclr : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr : entity is "delay_sclr"; +end Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr; + +architecture STRUCTURE of Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr is + signal \needs_delay.shift_register[1][3]_i_3__0_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][3]_i_4__0_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][3]_i_5__1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][3]_i_6_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][7]_i_2_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][7]_i_3_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][7]_i_4_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][7]_i_5_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1_n_1\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1_n_2\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1_n_3\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1_n_4\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1_n_5\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1_n_6\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1_n_7\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][7]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][7]_i_1_n_1\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][7]_i_1_n_2\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][7]_i_1_n_3\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][7]_i_1_n_4\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][7]_i_1_n_5\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][7]_i_1_n_6\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][7]_i_1_n_7\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][8]_i_1_n_7\ : STD_LOGIC; + signal \^p_0_in\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \NLW_needs_delay.shift_register_reg[1][8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_needs_delay.shift_register_reg[1][8]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); +begin + p_0_in(0) <= \^p_0_in\(0); +\needs_delay.shift_register[1][3]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => Q(0), + O => \^p_0_in\(0) + ); +\needs_delay.shift_register[1][3]_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => Q(11), + I1 => Q(3), + O => \needs_delay.shift_register[1][3]_i_3__0_n_0\ + ); +\needs_delay.shift_register[1][3]_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => Q(10), + I1 => Q(2), + O => \needs_delay.shift_register[1][3]_i_4__0_n_0\ + ); +\needs_delay.shift_register[1][3]_i_5__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => Q(9), + I1 => Q(1), + O => \needs_delay.shift_register[1][3]_i_5__1_n_0\ + ); +\needs_delay.shift_register[1][3]_i_6\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => Q(8), + O => \needs_delay.shift_register[1][3]_i_6_n_0\ + ); +\needs_delay.shift_register[1][7]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => Q(15), + I1 => Q(7), + O => \needs_delay.shift_register[1][7]_i_2_n_0\ + ); +\needs_delay.shift_register[1][7]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => Q(14), + I1 => Q(6), + O => \needs_delay.shift_register[1][7]_i_3_n_0\ + ); +\needs_delay.shift_register[1][7]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => Q(13), + I1 => Q(5), + O => \needs_delay.shift_register[1][7]_i_4_n_0\ + ); +\needs_delay.shift_register[1][7]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => Q(12), + I1 => Q(4), + O => \needs_delay.shift_register[1][7]_i_5_n_0\ + ); +\needs_delay.shift_register_reg[1][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[1][3]_i_1_n_7\, + Q => out_s(0), + R => sclr + ); +\needs_delay.shift_register_reg[1][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[1][3]_i_1_n_6\, + Q => out_s(1), + R => sclr + ); +\needs_delay.shift_register_reg[1][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[1][3]_i_1_n_5\, + Q => out_s(2), + R => sclr + ); +\needs_delay.shift_register_reg[1][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[1][3]_i_1_n_4\, + Q => out_s(3), + R => sclr + ); +\needs_delay.shift_register_reg[1][3]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \needs_delay.shift_register_reg[1][3]_i_1_n_0\, + CO(2) => \needs_delay.shift_register_reg[1][3]_i_1_n_1\, + CO(1) => \needs_delay.shift_register_reg[1][3]_i_1_n_2\, + CO(0) => \needs_delay.shift_register_reg[1][3]_i_1_n_3\, + CYINIT => \^p_0_in\(0), + DI(3 downto 0) => Q(11 downto 8), + O(3) => \needs_delay.shift_register_reg[1][3]_i_1_n_4\, + O(2) => \needs_delay.shift_register_reg[1][3]_i_1_n_5\, + O(1) => \needs_delay.shift_register_reg[1][3]_i_1_n_6\, + O(0) => \needs_delay.shift_register_reg[1][3]_i_1_n_7\, + S(3) => \needs_delay.shift_register[1][3]_i_3__0_n_0\, + S(2) => \needs_delay.shift_register[1][3]_i_4__0_n_0\, + S(1) => \needs_delay.shift_register[1][3]_i_5__1_n_0\, + S(0) => \needs_delay.shift_register[1][3]_i_6_n_0\ + ); +\needs_delay.shift_register_reg[1][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[1][7]_i_1_n_7\, + Q => out_s(4), + R => sclr + ); +\needs_delay.shift_register_reg[1][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[1][7]_i_1_n_6\, + Q => out_s(5), + R => sclr + ); +\needs_delay.shift_register_reg[1][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[1][7]_i_1_n_5\, + Q => out_s(6), + R => sclr + ); +\needs_delay.shift_register_reg[1][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[1][7]_i_1_n_4\, + Q => out_s(7), + R => sclr + ); +\needs_delay.shift_register_reg[1][7]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \needs_delay.shift_register_reg[1][3]_i_1_n_0\, + CO(3) => \needs_delay.shift_register_reg[1][7]_i_1_n_0\, + CO(2) => \needs_delay.shift_register_reg[1][7]_i_1_n_1\, + CO(1) => \needs_delay.shift_register_reg[1][7]_i_1_n_2\, + CO(0) => \needs_delay.shift_register_reg[1][7]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => Q(15 downto 12), + O(3) => \needs_delay.shift_register_reg[1][7]_i_1_n_4\, + O(2) => \needs_delay.shift_register_reg[1][7]_i_1_n_5\, + O(1) => \needs_delay.shift_register_reg[1][7]_i_1_n_6\, + O(0) => \needs_delay.shift_register_reg[1][7]_i_1_n_7\, + S(3) => \needs_delay.shift_register[1][7]_i_2_n_0\, + S(2) => \needs_delay.shift_register[1][7]_i_3_n_0\, + S(1) => \needs_delay.shift_register[1][7]_i_4_n_0\, + S(0) => \needs_delay.shift_register[1][7]_i_5_n_0\ + ); +\needs_delay.shift_register_reg[1][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[1][8]_i_1_n_7\, + Q => out_s(8), + R => sclr + ); +\needs_delay.shift_register_reg[1][8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \needs_delay.shift_register_reg[1][7]_i_1_n_0\, + CO(3 downto 0) => \NLW_needs_delay.shift_register_reg[1][8]_i_1_CO_UNCONNECTED\(3 downto 0), + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 1) => \NLW_needs_delay.shift_register_reg[1][8]_i_1_O_UNCONNECTED\(3 downto 1), + O(0) => \needs_delay.shift_register_reg[1][8]_i_1_n_7\, + S(3 downto 0) => B"0001" + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr_6 is + port ( + out_s : out STD_LOGIC_VECTOR ( 8 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 14 downto 0 ); + sclr : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + aclk : in STD_LOGIC; + p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr_6 : entity is "delay_sclr"; +end Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr_6; + +architecture STRUCTURE of Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr_6 is + signal \needs_delay.shift_register[1][3]_i_2__1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][3]_i_3_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][3]_i_4_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][3]_i_5_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][7]_i_2__0_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][7]_i_3__0_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][7]_i_4__0_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][7]_i_5__0_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1__0_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1__0_n_1\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1__0_n_2\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1__0_n_3\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1__0_n_4\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1__0_n_5\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1__0_n_6\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1__0_n_7\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][7]_i_1__0_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][7]_i_1__0_n_1\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][7]_i_1__0_n_2\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][7]_i_1__0_n_3\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][7]_i_1__0_n_4\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][7]_i_1__0_n_5\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][7]_i_1__0_n_6\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][7]_i_1__0_n_7\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][8]_i_1__0_n_7\ : STD_LOGIC; + signal \NLW_needs_delay.shift_register_reg[1][8]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_needs_delay.shift_register_reg[1][8]_i_1__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); +begin +\needs_delay.shift_register[1][3]_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => Q(10), + I1 => Q(2), + O => \needs_delay.shift_register[1][3]_i_2__1_n_0\ + ); +\needs_delay.shift_register[1][3]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => Q(9), + I1 => Q(1), + O => \needs_delay.shift_register[1][3]_i_3_n_0\ + ); +\needs_delay.shift_register[1][3]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => Q(8), + I1 => Q(0), + O => \needs_delay.shift_register[1][3]_i_4_n_0\ + ); +\needs_delay.shift_register[1][3]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => Q(7), + O => \needs_delay.shift_register[1][3]_i_5_n_0\ + ); +\needs_delay.shift_register[1][7]_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => Q(14), + I1 => Q(6), + O => \needs_delay.shift_register[1][7]_i_2__0_n_0\ + ); +\needs_delay.shift_register[1][7]_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => Q(13), + I1 => Q(5), + O => \needs_delay.shift_register[1][7]_i_3__0_n_0\ + ); +\needs_delay.shift_register[1][7]_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => Q(12), + I1 => Q(4), + O => \needs_delay.shift_register[1][7]_i_4__0_n_0\ + ); +\needs_delay.shift_register[1][7]_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => Q(11), + I1 => Q(3), + O => \needs_delay.shift_register[1][7]_i_5__0_n_0\ + ); +\needs_delay.shift_register_reg[1][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[1][3]_i_1__0_n_7\, + Q => out_s(0), + R => sclr + ); +\needs_delay.shift_register_reg[1][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[1][3]_i_1__0_n_6\, + Q => out_s(1), + R => sclr + ); +\needs_delay.shift_register_reg[1][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[1][3]_i_1__0_n_5\, + Q => out_s(2), + R => sclr + ); +\needs_delay.shift_register_reg[1][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[1][3]_i_1__0_n_4\, + Q => out_s(3), + R => sclr + ); +\needs_delay.shift_register_reg[1][3]_i_1__0\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \needs_delay.shift_register_reg[1][3]_i_1__0_n_0\, + CO(2) => \needs_delay.shift_register_reg[1][3]_i_1__0_n_1\, + CO(1) => \needs_delay.shift_register_reg[1][3]_i_1__0_n_2\, + CO(0) => \needs_delay.shift_register_reg[1][3]_i_1__0_n_3\, + CYINIT => p_0_in(0), + DI(3 downto 0) => Q(10 downto 7), + O(3) => \needs_delay.shift_register_reg[1][3]_i_1__0_n_4\, + O(2) => \needs_delay.shift_register_reg[1][3]_i_1__0_n_5\, + O(1) => \needs_delay.shift_register_reg[1][3]_i_1__0_n_6\, + O(0) => \needs_delay.shift_register_reg[1][3]_i_1__0_n_7\, + S(3) => \needs_delay.shift_register[1][3]_i_2__1_n_0\, + S(2) => \needs_delay.shift_register[1][3]_i_3_n_0\, + S(1) => \needs_delay.shift_register[1][3]_i_4_n_0\, + S(0) => \needs_delay.shift_register[1][3]_i_5_n_0\ + ); +\needs_delay.shift_register_reg[1][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[1][7]_i_1__0_n_7\, + Q => out_s(4), + R => sclr + ); +\needs_delay.shift_register_reg[1][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[1][7]_i_1__0_n_6\, + Q => out_s(5), + R => sclr + ); +\needs_delay.shift_register_reg[1][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[1][7]_i_1__0_n_5\, + Q => out_s(6), + R => sclr + ); +\needs_delay.shift_register_reg[1][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[1][7]_i_1__0_n_4\, + Q => out_s(7), + R => sclr + ); +\needs_delay.shift_register_reg[1][7]_i_1__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \needs_delay.shift_register_reg[1][3]_i_1__0_n_0\, + CO(3) => \needs_delay.shift_register_reg[1][7]_i_1__0_n_0\, + CO(2) => \needs_delay.shift_register_reg[1][7]_i_1__0_n_1\, + CO(1) => \needs_delay.shift_register_reg[1][7]_i_1__0_n_2\, + CO(0) => \needs_delay.shift_register_reg[1][7]_i_1__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => Q(14 downto 11), + O(3) => \needs_delay.shift_register_reg[1][7]_i_1__0_n_4\, + O(2) => \needs_delay.shift_register_reg[1][7]_i_1__0_n_5\, + O(1) => \needs_delay.shift_register_reg[1][7]_i_1__0_n_6\, + O(0) => \needs_delay.shift_register_reg[1][7]_i_1__0_n_7\, + S(3) => \needs_delay.shift_register[1][7]_i_2__0_n_0\, + S(2) => \needs_delay.shift_register[1][7]_i_3__0_n_0\, + S(1) => \needs_delay.shift_register[1][7]_i_4__0_n_0\, + S(0) => \needs_delay.shift_register[1][7]_i_5__0_n_0\ + ); +\needs_delay.shift_register_reg[1][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => \needs_delay.shift_register_reg[1][8]_i_1__0_n_7\, + Q => out_s(8), + R => sclr + ); +\needs_delay.shift_register_reg[1][8]_i_1__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \needs_delay.shift_register_reg[1][7]_i_1__0_n_0\, + CO(3 downto 0) => \NLW_needs_delay.shift_register_reg[1][8]_i_1__0_CO_UNCONNECTED\(3 downto 0), + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 1) => \NLW_needs_delay.shift_register_reg[1][8]_i_1__0_O_UNCONNECTED\(3 downto 1), + O(0) => \needs_delay.shift_register_reg[1][8]_i_1__0_n_7\, + S(3 downto 0) => B"0001" + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized0\ is + port ( + c : out STD_LOGIC_VECTOR ( 25 downto 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + aclk : in STD_LOGIC; + sclr : in STD_LOGIC; + s : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \core_control_regs[9]\ : in STD_LOGIC_VECTOR ( 16 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized0\ : entity is "delay_sclr"; +end \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized0\ is + signal \NLW_needs_delay.shift_register_reg[2]_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_needs_delay.shift_register_reg[2]_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_needs_delay.shift_register_reg[2]_OVERFLOW_UNCONNECTED\ : STD_LOGIC; + signal \NLW_needs_delay.shift_register_reg[2]_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_needs_delay.shift_register_reg[2]_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_needs_delay.shift_register_reg[2]_UNDERFLOW_UNCONNECTED\ : STD_LOGIC; + signal \NLW_needs_delay.shift_register_reg[2]_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 ); + signal \NLW_needs_delay.shift_register_reg[2]_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 ); + signal \NLW_needs_delay.shift_register_reg[2]_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_needs_delay.shift_register_reg[2]_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 26 ); + signal \NLW_needs_delay.shift_register_reg[2]_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 ); + attribute METHODOLOGY_DRC_VIOS : string; + attribute METHODOLOGY_DRC_VIOS of \needs_delay.shift_register_reg[2]\ : label is "{SYNTH-12 {cell *THIS*}}"; +begin +\needs_delay.shift_register_reg[2]\: unisim.vcomponents.DSP48E1 + generic map( + ACASCREG => 0, + ADREG => 1, + ALUMODEREG => 0, + AREG => 0, + AUTORESET_PATDET => "NO_RESET", + A_INPUT => "DIRECT", + BCASCREG => 0, + BREG => 0, + B_INPUT => "DIRECT", + CARRYINREG => 0, + CARRYINSELREG => 0, + CREG => 1, + DREG => 1, + INMODEREG => 0, + MASK => X"3FFFFFFFFFFF", + MREG => 1, + OPMODEREG => 0, + PATTERN => X"000000000000", + PREG => 1, + SEL_MASK => "MASK", + SEL_PATTERN => "PATTERN", + USE_DPORT => false, + USE_MULT => "MULTIPLY", + USE_PATTERN_DETECT => "NO_PATDET", + USE_SIMD => "ONE48" + ) + port map ( + A(29) => \core_control_regs[9]\(16), + A(28) => \core_control_regs[9]\(16), + A(27) => \core_control_regs[9]\(16), + A(26) => \core_control_regs[9]\(16), + A(25) => \core_control_regs[9]\(16), + A(24) => \core_control_regs[9]\(16), + A(23) => \core_control_regs[9]\(16), + A(22) => \core_control_regs[9]\(16), + A(21) => \core_control_regs[9]\(16), + A(20) => \core_control_regs[9]\(16), + A(19) => \core_control_regs[9]\(16), + A(18) => \core_control_regs[9]\(16), + A(17) => \core_control_regs[9]\(16), + A(16 downto 0) => \core_control_regs[9]\(16 downto 0), + ACIN(29 downto 0) => B"000000000000000000000000000000", + ACOUT(29 downto 0) => \NLW_needs_delay.shift_register_reg[2]_ACOUT_UNCONNECTED\(29 downto 0), + ALUMODE(3 downto 0) => B"0000", + B(17) => s(8), + B(16) => s(8), + B(15) => s(8), + B(14) => s(8), + B(13) => s(8), + B(12) => s(8), + B(11) => s(8), + B(10) => s(8), + B(9) => s(8), + B(8 downto 0) => s(8 downto 0), + BCIN(17 downto 0) => B"000000000000000000", + BCOUT(17 downto 0) => \NLW_needs_delay.shift_register_reg[2]_BCOUT_UNCONNECTED\(17 downto 0), + C(47 downto 0) => B"111111111111111111111111111111111111111111111111", + CARRYCASCIN => '0', + CARRYCASCOUT => \NLW_needs_delay.shift_register_reg[2]_CARRYCASCOUT_UNCONNECTED\, + CARRYIN => '0', + CARRYINSEL(2 downto 0) => B"000", + CARRYOUT(3 downto 0) => \NLW_needs_delay.shift_register_reg[2]_CARRYOUT_UNCONNECTED\(3 downto 0), + CEA1 => '0', + CEA2 => '0', + CEAD => '0', + CEALUMODE => '0', + CEB1 => '0', + CEB2 => '0', + CEC => '0', + CECARRYIN => '0', + CECTRL => '0', + CED => '0', + CEINMODE => '0', + CEM => E(0), + CEP => E(0), + CLK => aclk, + D(24 downto 0) => B"0000000000000000000000000", + INMODE(4 downto 0) => B"00000", + MULTSIGNIN => '0', + MULTSIGNOUT => \NLW_needs_delay.shift_register_reg[2]_MULTSIGNOUT_UNCONNECTED\, + OPMODE(6 downto 0) => B"0000101", + OVERFLOW => \NLW_needs_delay.shift_register_reg[2]_OVERFLOW_UNCONNECTED\, + P(47 downto 26) => \NLW_needs_delay.shift_register_reg[2]_P_UNCONNECTED\(47 downto 26), + P(25 downto 0) => c(25 downto 0), + PATTERNBDETECT => \NLW_needs_delay.shift_register_reg[2]_PATTERNBDETECT_UNCONNECTED\, + PATTERNDETECT => \NLW_needs_delay.shift_register_reg[2]_PATTERNDETECT_UNCONNECTED\, + PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000", + PCOUT(47 downto 0) => \NLW_needs_delay.shift_register_reg[2]_PCOUT_UNCONNECTED\(47 downto 0), + RSTA => '0', + RSTALLCARRYIN => '0', + RSTALUMODE => '0', + RSTB => '0', + RSTC => '0', + RSTCTRL => '0', + RSTD => '0', + RSTINMODE => '0', + RSTM => sclr, + RSTP => sclr, + UNDERFLOW => \NLW_needs_delay.shift_register_reg[2]_UNDERFLOW_UNCONNECTED\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized1\ is + port ( + a : out STD_LOGIC_VECTOR ( 1 downto 0 ); + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \needs_delay.shift_register_reg[1][10]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \needs_delay.shift_register_reg[1][3]_0\ : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 9 downto 0 ); + p : in STD_LOGIC_VECTOR ( 1 downto 0 ); + CO : in STD_LOGIC_VECTOR ( 0 to 0 ); + \needs_delay.shift_register_reg[5][7]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + sclr : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + plusOp : in STD_LOGIC_VECTOR ( 9 downto 0 ); + aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized1\ : entity is "delay_sclr"; +end \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized1\; + +architecture STRUCTURE of \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized1\ is + signal \needs_delay.shift_register[1][10]_i_2__0_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][10]_i_2__1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][10]_i_3__0_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][10]_i_3_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][10]_i_1__0_n_2\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][10]_i_1__0_n_3\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][10]_i_1_n_2\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][10]_i_1_n_3\ : STD_LOGIC; + signal \NLW_needs_delay.shift_register_reg[1][10]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_needs_delay.shift_register_reg[1][10]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_needs_delay.shift_register_reg[1][10]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_needs_delay.shift_register_reg[1][10]_i_1__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); +begin +\needs_delay.shift_register[1][10]_i_2__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \out\(2), + O => \needs_delay.shift_register[1][10]_i_2__0_n_0\ + ); +\needs_delay.shift_register[1][10]_i_2__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \out\(2), + O => \needs_delay.shift_register[1][10]_i_2__1_n_0\ + ); +\needs_delay.shift_register[1][10]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \out\(1), + O => \needs_delay.shift_register[1][10]_i_3_n_0\ + ); +\needs_delay.shift_register[1][10]_i_3__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \out\(1), + O => \needs_delay.shift_register[1][10]_i_3__0_n_0\ + ); +\needs_delay.shift_register[1][3]_i_2__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \out\(0), + O => \needs_delay.shift_register_reg[1][3]_0\ + ); +\needs_delay.shift_register[1][3]_i_5__3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => p(0), + O => a(0) + ); +\needs_delay.shift_register[1][9]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => p(1), + O => a(1) + ); +\needs_delay.shift_register_reg[1][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => plusOp(0), + Q => Q(0), + R => sclr + ); +\needs_delay.shift_register_reg[1][10]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => CO(0), + CO(3 downto 2) => \NLW_needs_delay.shift_register_reg[1][10]_i_1_CO_UNCONNECTED\(3 downto 2), + CO(1) => \needs_delay.shift_register_reg[1][10]_i_1_n_2\, + CO(0) => \needs_delay.shift_register_reg[1][10]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0010", + O(3) => \NLW_needs_delay.shift_register_reg[1][10]_i_1_O_UNCONNECTED\(3), + O(2 downto 0) => D(2 downto 0), + S(3 downto 2) => B"01", + S(1) => \needs_delay.shift_register[1][10]_i_2__0_n_0\, + S(0) => \needs_delay.shift_register[1][10]_i_3__0_n_0\ + ); +\needs_delay.shift_register_reg[1][10]_i_1__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \needs_delay.shift_register_reg[5][7]\(0), + CO(3 downto 2) => \NLW_needs_delay.shift_register_reg[1][10]_i_1__0_CO_UNCONNECTED\(3 downto 2), + CO(1) => \needs_delay.shift_register_reg[1][10]_i_1__0_n_2\, + CO(0) => \needs_delay.shift_register_reg[1][10]_i_1__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0010", + O(3) => \NLW_needs_delay.shift_register_reg[1][10]_i_1__0_O_UNCONNECTED\(3), + O(2 downto 0) => \needs_delay.shift_register_reg[1][10]\(2 downto 0), + S(3 downto 2) => B"01", + S(1) => \needs_delay.shift_register[1][10]_i_2__1_n_0\, + S(0) => \needs_delay.shift_register[1][10]_i_3_n_0\ + ); +\needs_delay.shift_register_reg[1][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => plusOp(1), + Q => Q(1), + R => sclr + ); +\needs_delay.shift_register_reg[1][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => plusOp(2), + Q => Q(2), + R => sclr + ); +\needs_delay.shift_register_reg[1][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => plusOp(3), + Q => Q(3), + R => sclr + ); +\needs_delay.shift_register_reg[1][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => plusOp(4), + Q => Q(4), + R => sclr + ); +\needs_delay.shift_register_reg[1][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => plusOp(5), + Q => Q(5), + R => sclr + ); +\needs_delay.shift_register_reg[1][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => plusOp(6), + Q => Q(6), + R => sclr + ); +\needs_delay.shift_register_reg[1][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => plusOp(7), + Q => Q(7), + R => sclr + ); +\needs_delay.shift_register_reg[1][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => plusOp(8), + Q => Q(8), + R => sclr + ); +\needs_delay.shift_register_reg[1][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => plusOp(9), + Q => Q(9), + R => sclr + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized2\ is + port ( + Q : out STD_LOGIC_VECTOR ( 10 downto 0 ); + sclr : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + D : in STD_LOGIC_VECTOR ( 10 downto 0 ); + aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized2\ : entity is "delay_sclr"; +end \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized2\; + +architecture STRUCTURE of \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized2\ is +begin +\needs_delay.shift_register_reg[1][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(0), + Q => Q(0), + R => sclr + ); +\needs_delay.shift_register_reg[1][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(10), + Q => Q(10), + R => sclr + ); +\needs_delay.shift_register_reg[1][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(1), + Q => Q(1), + R => sclr + ); +\needs_delay.shift_register_reg[1][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(2), + Q => Q(2), + R => sclr + ); +\needs_delay.shift_register_reg[1][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(3), + Q => Q(3), + R => sclr + ); +\needs_delay.shift_register_reg[1][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(4), + Q => Q(4), + R => sclr + ); +\needs_delay.shift_register_reg[1][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(5), + Q => Q(5), + R => sclr + ); +\needs_delay.shift_register_reg[1][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(6), + Q => Q(6), + R => sclr + ); +\needs_delay.shift_register_reg[1][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(7), + Q => Q(7), + R => sclr + ); +\needs_delay.shift_register_reg[1][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(8), + Q => Q(8), + R => sclr + ); +\needs_delay.shift_register_reg[1][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(9), + Q => Q(9), + R => sclr + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized3\ is + port ( + Q : out STD_LOGIC_VECTOR ( 10 downto 0 ); + sclr : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + D : in STD_LOGIC_VECTOR ( 10 downto 0 ); + aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized3\ : entity is "delay_sclr"; +end \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized3\; + +architecture STRUCTURE of \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized3\ is +begin +\needs_delay.shift_register_reg[1][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(0), + Q => Q(0), + R => sclr + ); +\needs_delay.shift_register_reg[1][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(10), + Q => Q(10), + R => sclr + ); +\needs_delay.shift_register_reg[1][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(1), + Q => Q(1), + R => sclr + ); +\needs_delay.shift_register_reg[1][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(2), + Q => Q(2), + R => sclr + ); +\needs_delay.shift_register_reg[1][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(3), + Q => Q(3), + R => sclr + ); +\needs_delay.shift_register_reg[1][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(4), + Q => Q(4), + R => sclr + ); +\needs_delay.shift_register_reg[1][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(5), + Q => Q(5), + R => sclr + ); +\needs_delay.shift_register_reg[1][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(6), + Q => Q(6), + R => sclr + ); +\needs_delay.shift_register_reg[1][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(7), + Q => Q(7), + R => sclr + ); +\needs_delay.shift_register_reg[1][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(8), + Q => Q(8), + R => sclr + ); +\needs_delay.shift_register_reg[1][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(9), + Q => Q(9), + R => sclr + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized4\ is + port ( + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + Q : out STD_LOGIC_VECTOR ( 10 downto 0 ); + resetn_out : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + plusOp : in STD_LOGIC_VECTOR ( 10 downto 0 ); + aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized4\ : entity is "delay_sclr"; +end \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized4\; + +architecture STRUCTURE of \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized4\ is + signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); +begin + SR(0) <= \^sr\(0); +\needs_delay.shift_register_reg[1][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => plusOp(0), + Q => Q(0), + R => \^sr\(0) + ); +\needs_delay.shift_register_reg[1][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => plusOp(10), + Q => Q(10), + R => \^sr\(0) + ); +\needs_delay.shift_register_reg[1][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => plusOp(1), + Q => Q(1), + R => \^sr\(0) + ); +\needs_delay.shift_register_reg[1][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => plusOp(2), + Q => Q(2), + R => \^sr\(0) + ); +\needs_delay.shift_register_reg[1][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => plusOp(3), + Q => Q(3), + R => \^sr\(0) + ); +\needs_delay.shift_register_reg[1][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => plusOp(4), + Q => Q(4), + R => \^sr\(0) + ); +\needs_delay.shift_register_reg[1][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => plusOp(5), + Q => Q(5), + R => \^sr\(0) + ); +\needs_delay.shift_register_reg[1][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => plusOp(6), + Q => Q(6), + R => \^sr\(0) + ); +\needs_delay.shift_register_reg[1][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => plusOp(7), + Q => Q(7), + R => \^sr\(0) + ); +\needs_delay.shift_register_reg[1][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => plusOp(8), + Q => Q(8), + R => \^sr\(0) + ); +\needs_delay.shift_register_reg[1][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => plusOp(9), + Q => Q(9), + R => \^sr\(0) + ); +sof_late_i_i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => resetn_out, + O => \^sr\(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized5\ is + port ( + \needs_delay.shift_register_reg[1][7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + Q : out STD_LOGIC_VECTOR ( 8 downto 0 ); + \needs_delay.shift_register_reg[1][7]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \needs_delay.shift_register_reg[1][7]_2\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \core_control_regs[1]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + sclr : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + D : in STD_LOGIC_VECTOR ( 9 downto 0 ); + aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized5\ : entity is "delay_sclr"; +end \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized5\; + +architecture STRUCTURE of \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized5\ is + signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal \needs_delay.shift_register_reg_n_0_[1][8]\ : STD_LOGIC; +begin + Q(8 downto 0) <= \^q\(8 downto 0); +\ltOp_carry__0_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \needs_delay.shift_register_reg_n_0_[1][8]\, + I1 => \^q\(8), + O => \needs_delay.shift_register_reg[1][7]_0\(0) + ); +\ltOp_carry_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \core_control_regs[1]\(6), + I1 => \^q\(6), + I2 => \^q\(7), + I3 => \core_control_regs[1]\(7), + O => \needs_delay.shift_register_reg[1][7]_2\(3) + ); +\ltOp_carry_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \core_control_regs[1]\(4), + I1 => \^q\(4), + I2 => \^q\(5), + I3 => \core_control_regs[1]\(5), + O => \needs_delay.shift_register_reg[1][7]_2\(2) + ); +\ltOp_carry_i_3__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \core_control_regs[1]\(2), + I1 => \^q\(2), + I2 => \^q\(3), + I3 => \core_control_regs[1]\(3), + O => \needs_delay.shift_register_reg[1][7]_2\(1) + ); +\ltOp_carry_i_4__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \core_control_regs[1]\(0), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => \core_control_regs[1]\(1), + O => \needs_delay.shift_register_reg[1][7]_2\(0) + ); +\ltOp_carry_i_5__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \core_control_regs[1]\(6), + I1 => \^q\(6), + I2 => \core_control_regs[1]\(7), + I3 => \^q\(7), + O => \needs_delay.shift_register_reg[1][7]_1\(3) + ); +\ltOp_carry_i_6__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \core_control_regs[1]\(4), + I1 => \^q\(4), + I2 => \core_control_regs[1]\(5), + I3 => \^q\(5), + O => \needs_delay.shift_register_reg[1][7]_1\(2) + ); +\ltOp_carry_i_7__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \core_control_regs[1]\(2), + I1 => \^q\(2), + I2 => \core_control_regs[1]\(3), + I3 => \^q\(3), + O => \needs_delay.shift_register_reg[1][7]_1\(1) + ); +\ltOp_carry_i_8__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \core_control_regs[1]\(0), + I1 => \^q\(0), + I2 => \core_control_regs[1]\(1), + I3 => \^q\(1), + O => \needs_delay.shift_register_reg[1][7]_1\(0) + ); +\needs_delay.shift_register_reg[1][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(0), + Q => \^q\(0), + R => sclr + ); +\needs_delay.shift_register_reg[1][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(1), + Q => \^q\(1), + R => sclr + ); +\needs_delay.shift_register_reg[1][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(2), + Q => \^q\(2), + R => sclr + ); +\needs_delay.shift_register_reg[1][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(3), + Q => \^q\(3), + R => sclr + ); +\needs_delay.shift_register_reg[1][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(4), + Q => \^q\(4), + R => sclr + ); +\needs_delay.shift_register_reg[1][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(5), + Q => \^q\(5), + R => sclr + ); +\needs_delay.shift_register_reg[1][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(6), + Q => \^q\(6), + R => sclr + ); +\needs_delay.shift_register_reg[1][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(7), + Q => \^q\(7), + R => sclr + ); +\needs_delay.shift_register_reg[1][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(8), + Q => \needs_delay.shift_register_reg_n_0_[1][8]\, + R => sclr + ); +\needs_delay.shift_register_reg[1][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(9), + Q => \^q\(8), + R => sclr + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized5_7\ is + port ( + DI : out STD_LOGIC_VECTOR ( 0 to 0 ); + S : out STD_LOGIC_VECTOR ( 0 to 0 ); + \needs_delay.shift_register_reg[1][7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + Q : out STD_LOGIC_VECTOR ( 8 downto 0 ); + \needs_delay.shift_register_reg[1][7]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \needs_delay.shift_register_reg[1][7]_2\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \needs_delay.shift_register_reg[1][9]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \needs_delay.shift_register_reg[1][9]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + p : in STD_LOGIC_VECTOR ( 9 downto 0 ); + \core_control_regs[5]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \core_control_regs[4]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + sclr : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + D : in STD_LOGIC_VECTOR ( 9 downto 0 ); + aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized5_7\ : entity is "delay_sclr"; +end \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized5_7\; + +architecture STRUCTURE of \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized5_7\ is + signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal \needs_delay.shift_register_reg_n_0_[1][8]\ : STD_LOGIC; +begin + Q(8 downto 0) <= \^q\(8 downto 0); +\gtOp_carry__0_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => p(8), + I1 => p(9), + O => DI(0) + ); +\gtOp_carry__0_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => p(8), + I1 => p(9), + O => S(0) + ); +\gtOp_carry_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => p(6), + I1 => \core_control_regs[4]\(6), + I2 => \core_control_regs[4]\(7), + I3 => p(7), + O => \needs_delay.shift_register_reg[1][9]_1\(3) + ); +\gtOp_carry_i_2__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => p(4), + I1 => \core_control_regs[4]\(4), + I2 => \core_control_regs[4]\(5), + I3 => p(5), + O => \needs_delay.shift_register_reg[1][9]_1\(2) + ); +\gtOp_carry_i_3__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => p(2), + I1 => \core_control_regs[4]\(2), + I2 => \core_control_regs[4]\(3), + I3 => p(3), + O => \needs_delay.shift_register_reg[1][9]_1\(1) + ); +\gtOp_carry_i_4__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => p(0), + I1 => \core_control_regs[4]\(0), + I2 => \core_control_regs[4]\(1), + I3 => p(1), + O => \needs_delay.shift_register_reg[1][9]_1\(0) + ); +\gtOp_carry_i_5__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => p(6), + I1 => \core_control_regs[4]\(6), + I2 => p(7), + I3 => \core_control_regs[4]\(7), + O => \needs_delay.shift_register_reg[1][9]_0\(3) + ); +\gtOp_carry_i_6__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => p(4), + I1 => \core_control_regs[4]\(4), + I2 => p(5), + I3 => \core_control_regs[4]\(5), + O => \needs_delay.shift_register_reg[1][9]_0\(2) + ); +\gtOp_carry_i_7__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => p(2), + I1 => \core_control_regs[4]\(2), + I2 => p(3), + I3 => \core_control_regs[4]\(3), + O => \needs_delay.shift_register_reg[1][9]_0\(1) + ); +\gtOp_carry_i_8__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => p(0), + I1 => \core_control_regs[4]\(0), + I2 => p(1), + I3 => \core_control_regs[4]\(1), + O => \needs_delay.shift_register_reg[1][9]_0\(0) + ); +\ltOp_carry__0_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \needs_delay.shift_register_reg_n_0_[1][8]\, + I1 => \^q\(8), + O => \needs_delay.shift_register_reg[1][7]_0\(0) + ); +\ltOp_carry_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \core_control_regs[5]\(6), + I1 => \^q\(6), + I2 => \^q\(7), + I3 => \core_control_regs[5]\(7), + O => \needs_delay.shift_register_reg[1][7]_2\(3) + ); +\ltOp_carry_i_2__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \core_control_regs[5]\(4), + I1 => \^q\(4), + I2 => \^q\(5), + I3 => \core_control_regs[5]\(5), + O => \needs_delay.shift_register_reg[1][7]_2\(2) + ); +\ltOp_carry_i_3__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \core_control_regs[5]\(2), + I1 => \^q\(2), + I2 => \^q\(3), + I3 => \core_control_regs[5]\(3), + O => \needs_delay.shift_register_reg[1][7]_2\(1) + ); +\ltOp_carry_i_4__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \core_control_regs[5]\(0), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => \core_control_regs[5]\(1), + O => \needs_delay.shift_register_reg[1][7]_2\(0) + ); +\ltOp_carry_i_5__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \core_control_regs[5]\(6), + I1 => \^q\(6), + I2 => \core_control_regs[5]\(7), + I3 => \^q\(7), + O => \needs_delay.shift_register_reg[1][7]_1\(3) + ); +\ltOp_carry_i_6__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \core_control_regs[5]\(4), + I1 => \^q\(4), + I2 => \core_control_regs[5]\(5), + I3 => \^q\(5), + O => \needs_delay.shift_register_reg[1][7]_1\(2) + ); +\ltOp_carry_i_7__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \core_control_regs[5]\(2), + I1 => \^q\(2), + I2 => \core_control_regs[5]\(3), + I3 => \^q\(3), + O => \needs_delay.shift_register_reg[1][7]_1\(1) + ); +\ltOp_carry_i_8__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \core_control_regs[5]\(0), + I1 => \^q\(0), + I2 => \core_control_regs[5]\(1), + I3 => \^q\(1), + O => \needs_delay.shift_register_reg[1][7]_1\(0) + ); +\needs_delay.shift_register_reg[1][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(0), + Q => \^q\(0), + R => sclr + ); +\needs_delay.shift_register_reg[1][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(1), + Q => \^q\(1), + R => sclr + ); +\needs_delay.shift_register_reg[1][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(2), + Q => \^q\(2), + R => sclr + ); +\needs_delay.shift_register_reg[1][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(3), + Q => \^q\(3), + R => sclr + ); +\needs_delay.shift_register_reg[1][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(4), + Q => \^q\(4), + R => sclr + ); +\needs_delay.shift_register_reg[1][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(5), + Q => \^q\(5), + R => sclr + ); +\needs_delay.shift_register_reg[1][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(6), + Q => \^q\(6), + R => sclr + ); +\needs_delay.shift_register_reg[1][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(7), + Q => \^q\(7), + R => sclr + ); +\needs_delay.shift_register_reg[1][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(8), + Q => \needs_delay.shift_register_reg_n_0_[1][8]\, + R => sclr + ); +\needs_delay.shift_register_reg[1][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(9), + Q => \^q\(8), + R => sclr + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized5_8\ is + port ( + DI : out STD_LOGIC_VECTOR ( 0 to 0 ); + S : out STD_LOGIC_VECTOR ( 0 to 0 ); + \needs_delay.shift_register_reg[1][7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + Q : out STD_LOGIC_VECTOR ( 8 downto 0 ); + \needs_delay.shift_register_reg[1][7]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \needs_delay.shift_register_reg[1][7]_2\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \needs_delay.shift_register_reg[1][9]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \needs_delay.shift_register_reg[1][9]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + p : in STD_LOGIC_VECTOR ( 9 downto 0 ); + \core_control_regs[3]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \core_control_regs[2]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + sclr : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + D : in STD_LOGIC_VECTOR ( 9 downto 0 ); + aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized5_8\ : entity is "delay_sclr"; +end \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized5_8\; + +architecture STRUCTURE of \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized5_8\ is + signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal \needs_delay.shift_register_reg_n_0_[1][8]\ : STD_LOGIC; +begin + Q(8 downto 0) <= \^q\(8 downto 0); +\gtOp_carry__0_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => p(8), + I1 => p(9), + O => DI(0) + ); +\gtOp_carry__0_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => p(8), + I1 => p(9), + O => S(0) + ); +\gtOp_carry_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => p(6), + I1 => \core_control_regs[2]\(6), + I2 => \core_control_regs[2]\(7), + I3 => p(7), + O => \needs_delay.shift_register_reg[1][9]_1\(3) + ); +\gtOp_carry_i_2__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => p(4), + I1 => \core_control_regs[2]\(4), + I2 => \core_control_regs[2]\(5), + I3 => p(5), + O => \needs_delay.shift_register_reg[1][9]_1\(2) + ); +\gtOp_carry_i_3__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => p(2), + I1 => \core_control_regs[2]\(2), + I2 => \core_control_regs[2]\(3), + I3 => p(3), + O => \needs_delay.shift_register_reg[1][9]_1\(1) + ); +\gtOp_carry_i_4__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => p(0), + I1 => \core_control_regs[2]\(0), + I2 => \core_control_regs[2]\(1), + I3 => p(1), + O => \needs_delay.shift_register_reg[1][9]_1\(0) + ); +\gtOp_carry_i_5__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => p(6), + I1 => \core_control_regs[2]\(6), + I2 => p(7), + I3 => \core_control_regs[2]\(7), + O => \needs_delay.shift_register_reg[1][9]_0\(3) + ); +\gtOp_carry_i_6__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => p(4), + I1 => \core_control_regs[2]\(4), + I2 => p(5), + I3 => \core_control_regs[2]\(5), + O => \needs_delay.shift_register_reg[1][9]_0\(2) + ); +\gtOp_carry_i_7__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => p(2), + I1 => \core_control_regs[2]\(2), + I2 => p(3), + I3 => \core_control_regs[2]\(3), + O => \needs_delay.shift_register_reg[1][9]_0\(1) + ); +\gtOp_carry_i_8__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => p(0), + I1 => \core_control_regs[2]\(0), + I2 => p(1), + I3 => \core_control_regs[2]\(1), + O => \needs_delay.shift_register_reg[1][9]_0\(0) + ); +\ltOp_carry__0_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \needs_delay.shift_register_reg_n_0_[1][8]\, + I1 => \^q\(8), + O => \needs_delay.shift_register_reg[1][7]_0\(0) + ); +\ltOp_carry_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \core_control_regs[3]\(6), + I1 => \^q\(6), + I2 => \^q\(7), + I3 => \core_control_regs[3]\(7), + O => \needs_delay.shift_register_reg[1][7]_2\(3) + ); +\ltOp_carry_i_2__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \core_control_regs[3]\(4), + I1 => \^q\(4), + I2 => \^q\(5), + I3 => \core_control_regs[3]\(5), + O => \needs_delay.shift_register_reg[1][7]_2\(2) + ); +\ltOp_carry_i_3__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \core_control_regs[3]\(2), + I1 => \^q\(2), + I2 => \^q\(3), + I3 => \core_control_regs[3]\(3), + O => \needs_delay.shift_register_reg[1][7]_2\(1) + ); +\ltOp_carry_i_4__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \core_control_regs[3]\(0), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => \core_control_regs[3]\(1), + O => \needs_delay.shift_register_reg[1][7]_2\(0) + ); +\ltOp_carry_i_5__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \core_control_regs[3]\(6), + I1 => \^q\(6), + I2 => \core_control_regs[3]\(7), + I3 => \^q\(7), + O => \needs_delay.shift_register_reg[1][7]_1\(3) + ); +\ltOp_carry_i_6__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \core_control_regs[3]\(4), + I1 => \^q\(4), + I2 => \core_control_regs[3]\(5), + I3 => \^q\(5), + O => \needs_delay.shift_register_reg[1][7]_1\(2) + ); +\ltOp_carry_i_7__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \core_control_regs[3]\(2), + I1 => \^q\(2), + I2 => \core_control_regs[3]\(3), + I3 => \^q\(3), + O => \needs_delay.shift_register_reg[1][7]_1\(1) + ); +\ltOp_carry_i_8__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \core_control_regs[3]\(0), + I1 => \^q\(0), + I2 => \core_control_regs[3]\(1), + I3 => \^q\(1), + O => \needs_delay.shift_register_reg[1][7]_1\(0) + ); +\needs_delay.shift_register_reg[1][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(0), + Q => \^q\(0), + R => sclr + ); +\needs_delay.shift_register_reg[1][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(1), + Q => \^q\(1), + R => sclr + ); +\needs_delay.shift_register_reg[1][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(2), + Q => \^q\(2), + R => sclr + ); +\needs_delay.shift_register_reg[1][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(3), + Q => \^q\(3), + R => sclr + ); +\needs_delay.shift_register_reg[1][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(4), + Q => \^q\(4), + R => sclr + ); +\needs_delay.shift_register_reg[1][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(5), + Q => \^q\(5), + R => sclr + ); +\needs_delay.shift_register_reg[1][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(6), + Q => \^q\(6), + R => sclr + ); +\needs_delay.shift_register_reg[1][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(7), + Q => \^q\(7), + R => sclr + ); +\needs_delay.shift_register_reg[1][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(8), + Q => \needs_delay.shift_register_reg_n_0_[1][8]\, + R => sclr + ); +\needs_delay.shift_register_reg[1][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(9), + Q => \^q\(8), + R => sclr + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized6\ is + port ( + da : out STD_LOGIC_VECTOR ( 7 downto 0 ); + sclr : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + D : in STD_LOGIC_VECTOR ( 7 downto 0 ); + aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized6\ : entity is "delay_sclr"; +end \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized6\; + +architecture STRUCTURE of \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized6\ is +begin +\needs_delay.shift_register_reg[1][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(0), + Q => da(0), + R => sclr + ); +\needs_delay.shift_register_reg[1][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(1), + Q => da(1), + R => sclr + ); +\needs_delay.shift_register_reg[1][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(2), + Q => da(2), + R => sclr + ); +\needs_delay.shift_register_reg[1][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(3), + Q => da(3), + R => sclr + ); +\needs_delay.shift_register_reg[1][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(4), + Q => da(4), + R => sclr + ); +\needs_delay.shift_register_reg[1][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(5), + Q => da(5), + R => sclr + ); +\needs_delay.shift_register_reg[1][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(6), + Q => da(6), + R => sclr + ); +\needs_delay.shift_register_reg[1][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(7), + Q => da(7), + R => sclr + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized6_10\ is + port ( + da : out STD_LOGIC_VECTOR ( 7 downto 0 ); + sclr : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + D : in STD_LOGIC_VECTOR ( 7 downto 0 ); + aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized6_10\ : entity is "delay_sclr"; +end \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized6_10\; + +architecture STRUCTURE of \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized6_10\ is +begin +\needs_delay.shift_register_reg[1][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(0), + Q => da(0), + R => sclr + ); +\needs_delay.shift_register_reg[1][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(1), + Q => da(1), + R => sclr + ); +\needs_delay.shift_register_reg[1][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(2), + Q => da(2), + R => sclr + ); +\needs_delay.shift_register_reg[1][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(3), + Q => da(3), + R => sclr + ); +\needs_delay.shift_register_reg[1][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(4), + Q => da(4), + R => sclr + ); +\needs_delay.shift_register_reg[1][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(5), + Q => da(5), + R => sclr + ); +\needs_delay.shift_register_reg[1][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(6), + Q => da(6), + R => sclr + ); +\needs_delay.shift_register_reg[1][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(7), + Q => da(7), + R => sclr + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized6_9\ is + port ( + da : out STD_LOGIC_VECTOR ( 7 downto 0 ); + sclr : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + D : in STD_LOGIC_VECTOR ( 7 downto 0 ); + aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized6_9\ : entity is "delay_sclr"; +end \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized6_9\; + +architecture STRUCTURE of \Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized6_9\ is +begin +\needs_delay.shift_register_reg[1][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(0), + Q => da(0), + R => sclr + ); +\needs_delay.shift_register_reg[1][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(1), + Q => da(1), + R => sclr + ); +\needs_delay.shift_register_reg[1][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(2), + Q => da(2), + R => sclr + ); +\needs_delay.shift_register_reg[1][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(3), + Q => da(3), + R => sclr + ); +\needs_delay.shift_register_reg[1][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(4), + Q => da(4), + R => sclr + ); +\needs_delay.shift_register_reg[1][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(5), + Q => da(5), + R => sclr + ); +\needs_delay.shift_register_reg[1][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(6), + Q => da(6), + R => sclr + ); +\needs_delay.shift_register_reg[1][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => E(0), + D => D(7), + Q => da(7), + R => sclr + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_rgb2ycrcb_0_0_dp_ram is + port ( + \read_ptr_int_reg[3]\ : out STD_LOGIC; + ADDRA : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axis_video_tuser_sof : out STD_LOGIC_VECTOR ( 25 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \genr_control_regs[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + aclken : in STD_LOGIC; + m_axis_video_tready : in STD_LOGIC; + axi_fifo_empty : in STD_LOGIC; + aclken_0 : in STD_LOGIC; + aclk : in STD_LOGIC; + wen : in STD_LOGIC; + da : in STD_LOGIC_VECTOR ( 25 downto 0 ); + \write_ptr_int_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_rgb2ycrcb_0_0_dp_ram : entity is "dp_ram"; +end Arty_Z7_20_v_rgb2ycrcb_0_0_dp_ram; + +architecture STRUCTURE of Arty_Z7_20_v_rgb2ycrcb_0_0_dp_ram is + signal \^addra\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_0\ : STD_LOGIC; + signal \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_1\ : STD_LOGIC; + signal \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_2\ : STD_LOGIC; + signal \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_3\ : STD_LOGIC; + signal \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_4\ : STD_LOGIC; + signal \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_5\ : STD_LOGIC; + signal \GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_0\ : STD_LOGIC; + signal \GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_1\ : STD_LOGIC; + signal \GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_2\ : STD_LOGIC; + signal \GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_3\ : STD_LOGIC; + signal \GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_4\ : STD_LOGIC; + signal \GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_5\ : STD_LOGIC; + signal \GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_0\ : STD_LOGIC; + signal \GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_1\ : STD_LOGIC; + signal \GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_2\ : STD_LOGIC; + signal \GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_3\ : STD_LOGIC; + signal \GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_4\ : STD_LOGIC; + signal \GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_5\ : STD_LOGIC; + signal \GenerateDoutWriteFirstA.mem_reg_0_15_24_25_n_0\ : STD_LOGIC; + signal \GenerateDoutWriteFirstA.mem_reg_0_15_24_25_n_1\ : STD_LOGIC; + signal \GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_0\ : STD_LOGIC; + signal \GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_1\ : STD_LOGIC; + signal \GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_2\ : STD_LOGIC; + signal \GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_3\ : STD_LOGIC; + signal \GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_4\ : STD_LOGIC; + signal \GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_5\ : STD_LOGIC; + signal \^read_ptr_int_reg[3]\ : STD_LOGIC; + signal \NLW_GenerateDoutWriteFirstA.mem_reg_0_15_0_5_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_GenerateDoutWriteFirstA.mem_reg_0_15_12_17_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_GenerateDoutWriteFirstA.mem_reg_0_15_18_23_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_GenerateDoutWriteFirstA.mem_reg_0_15_24_25_DOB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_GenerateDoutWriteFirstA.mem_reg_0_15_24_25_DOC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_GenerateDoutWriteFirstA.mem_reg_0_15_24_25_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_GenerateDoutWriteFirstA.mem_reg_0_15_6_11_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute METHODOLOGY_DRC_VIOS : string; + attribute METHODOLOGY_DRC_VIOS of \GenerateDoutWriteFirstA.mem_reg_0_15_0_5\ : label is ""; + attribute METHODOLOGY_DRC_VIOS of \GenerateDoutWriteFirstA.mem_reg_0_15_12_17\ : label is ""; + attribute METHODOLOGY_DRC_VIOS of \GenerateDoutWriteFirstA.mem_reg_0_15_18_23\ : label is ""; + attribute METHODOLOGY_DRC_VIOS of \GenerateDoutWriteFirstA.mem_reg_0_15_24_25\ : label is ""; + attribute METHODOLOGY_DRC_VIOS of \GenerateDoutWriteFirstA.mem_reg_0_15_6_11\ : label is ""; +begin + ADDRA(3 downto 0) <= \^addra\(3 downto 0); + \read_ptr_int_reg[3]\ <= \^read_ptr_int_reg[3]\; +\GenerateDoutWriteFirstA.mem_reg_0_15_0_5\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000" + ) + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => \^addra\(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => \^addra\(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => \^addra\(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => \write_ptr_int_reg[3]\(3 downto 0), + DIA(1 downto 0) => da(1 downto 0), + DIB(1 downto 0) => da(3 downto 2), + DIC(1 downto 0) => da(5 downto 4), + DID(1 downto 0) => B"00", + DOA(1) => \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_0\, + DOA(0) => \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_1\, + DOB(1) => \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_2\, + DOB(0) => \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_3\, + DOC(1) => \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_4\, + DOC(0) => \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_5\, + DOD(1 downto 0) => \NLW_GenerateDoutWriteFirstA.mem_reg_0_15_0_5_DOD_UNCONNECTED\(1 downto 0), + WCLK => aclk, + WE => wen + ); +\GenerateDoutWriteFirstA.mem_reg_0_15_0_5_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => Q(3), + I1 => Q(2), + I2 => \^read_ptr_int_reg[3]\, + O => \^addra\(3) + ); +\GenerateDoutWriteFirstA.mem_reg_0_15_0_5_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAA6AAAAAAAAAA" + ) + port map ( + I0 => Q(2), + I1 => Q(1), + I2 => axi_fifo_empty, + I3 => m_axis_video_tready, + I4 => aclken_0, + I5 => Q(0), + O => \^addra\(2) + ); +\GenerateDoutWriteFirstA.mem_reg_0_15_0_5_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAA6AAAAAAA" + ) + port map ( + I0 => Q(1), + I1 => Q(0), + I2 => \genr_control_regs[0]\(0), + I3 => aclken, + I4 => m_axis_video_tready, + I5 => axi_fifo_empty, + O => \^addra\(1) + ); +\GenerateDoutWriteFirstA.mem_reg_0_15_0_5_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"9AAAAAAA" + ) + port map ( + I0 => Q(0), + I1 => axi_fifo_empty, + I2 => m_axis_video_tready, + I3 => aclken, + I4 => \genr_control_regs[0]\(0), + O => \^addra\(0) + ); +\GenerateDoutWriteFirstA.mem_reg_0_15_0_5_i_6__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000800000000000" + ) + port map ( + I0 => Q(0), + I1 => \genr_control_regs[0]\(0), + I2 => aclken, + I3 => m_axis_video_tready, + I4 => axi_fifo_empty, + I5 => Q(1), + O => \^read_ptr_int_reg[3]\ + ); +\GenerateDoutWriteFirstA.mem_reg_0_15_12_17\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000" + ) + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => \^addra\(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => \^addra\(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => \^addra\(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => \write_ptr_int_reg[3]\(3 downto 0), + DIA(1 downto 0) => da(13 downto 12), + DIB(1 downto 0) => da(15 downto 14), + DIC(1 downto 0) => da(17 downto 16), + DID(1 downto 0) => B"00", + DOA(1) => \GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_0\, + DOA(0) => \GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_1\, + DOB(1) => \GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_2\, + DOB(0) => \GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_3\, + DOC(1) => \GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_4\, + DOC(0) => \GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_5\, + DOD(1 downto 0) => \NLW_GenerateDoutWriteFirstA.mem_reg_0_15_12_17_DOD_UNCONNECTED\(1 downto 0), + WCLK => aclk, + WE => wen + ); +\GenerateDoutWriteFirstA.mem_reg_0_15_18_23\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000" + ) + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => \^addra\(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => \^addra\(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => \^addra\(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => \write_ptr_int_reg[3]\(3 downto 0), + DIA(1 downto 0) => da(19 downto 18), + DIB(1 downto 0) => da(21 downto 20), + DIC(1 downto 0) => da(23 downto 22), + DID(1 downto 0) => B"00", + DOA(1) => \GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_0\, + DOA(0) => \GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_1\, + DOB(1) => \GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_2\, + DOB(0) => \GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_3\, + DOC(1) => \GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_4\, + DOC(0) => \GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_5\, + DOD(1 downto 0) => \NLW_GenerateDoutWriteFirstA.mem_reg_0_15_18_23_DOD_UNCONNECTED\(1 downto 0), + WCLK => aclk, + WE => wen + ); +\GenerateDoutWriteFirstA.mem_reg_0_15_24_25\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000" + ) + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => \^addra\(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => \^addra\(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => \^addra\(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => \write_ptr_int_reg[3]\(3 downto 0), + DIA(1 downto 0) => da(25 downto 24), + DIB(1 downto 0) => B"00", + DIC(1 downto 0) => B"00", + DID(1 downto 0) => B"00", + DOA(1) => \GenerateDoutWriteFirstA.mem_reg_0_15_24_25_n_0\, + DOA(0) => \GenerateDoutWriteFirstA.mem_reg_0_15_24_25_n_1\, + DOB(1 downto 0) => \NLW_GenerateDoutWriteFirstA.mem_reg_0_15_24_25_DOB_UNCONNECTED\(1 downto 0), + DOC(1 downto 0) => \NLW_GenerateDoutWriteFirstA.mem_reg_0_15_24_25_DOC_UNCONNECTED\(1 downto 0), + DOD(1 downto 0) => \NLW_GenerateDoutWriteFirstA.mem_reg_0_15_24_25_DOD_UNCONNECTED\(1 downto 0), + WCLK => aclk, + WE => wen + ); +\GenerateDoutWriteFirstA.mem_reg_0_15_6_11\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000" + ) + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => \^addra\(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => \^addra\(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => \^addra\(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => \write_ptr_int_reg[3]\(3 downto 0), + DIA(1 downto 0) => da(7 downto 6), + DIB(1 downto 0) => da(9 downto 8), + DIC(1 downto 0) => da(11 downto 10), + DID(1 downto 0) => B"00", + DOA(1) => \GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_0\, + DOA(0) => \GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_1\, + DOB(1) => \GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_2\, + DOB(0) => \GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_3\, + DOC(1) => \GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_4\, + DOC(0) => \GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_5\, + DOD(1 downto 0) => \NLW_GenerateDoutWriteFirstA.mem_reg_0_15_6_11_DOD_UNCONNECTED\(1 downto 0), + WCLK => aclk, + WE => wen + ); +\GenerateDoutWriteFirstB.t_qb_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_1\, + Q => m_axis_video_tuser_sof(0), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_5\, + Q => m_axis_video_tuser_sof(10), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_4\, + Q => m_axis_video_tuser_sof(11), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_1\, + Q => m_axis_video_tuser_sof(12), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_0\, + Q => m_axis_video_tuser_sof(13), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_3\, + Q => m_axis_video_tuser_sof(14), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_2\, + Q => m_axis_video_tuser_sof(15), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_5\, + Q => m_axis_video_tuser_sof(16), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \GenerateDoutWriteFirstA.mem_reg_0_15_12_17_n_4\, + Q => m_axis_video_tuser_sof(17), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_1\, + Q => m_axis_video_tuser_sof(18), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_0\, + Q => m_axis_video_tuser_sof(19), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_0\, + Q => m_axis_video_tuser_sof(1), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_3\, + Q => m_axis_video_tuser_sof(20), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_2\, + Q => m_axis_video_tuser_sof(21), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_5\, + Q => m_axis_video_tuser_sof(22), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \GenerateDoutWriteFirstA.mem_reg_0_15_18_23_n_4\, + Q => m_axis_video_tuser_sof(23), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \GenerateDoutWriteFirstA.mem_reg_0_15_24_25_n_1\, + Q => m_axis_video_tuser_sof(24), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \GenerateDoutWriteFirstA.mem_reg_0_15_24_25_n_0\, + Q => m_axis_video_tuser_sof(25), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_3\, + Q => m_axis_video_tuser_sof(2), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_2\, + Q => m_axis_video_tuser_sof(3), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_5\, + Q => m_axis_video_tuser_sof(4), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \GenerateDoutWriteFirstA.mem_reg_0_15_0_5_n_4\, + Q => m_axis_video_tuser_sof(5), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_1\, + Q => m_axis_video_tuser_sof(6), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_0\, + Q => m_axis_video_tuser_sof(7), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_3\, + Q => m_axis_video_tuser_sof(8), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \GenerateDoutWriteFirstA.mem_reg_0_15_6_11_n_2\, + Q => m_axis_video_tuser_sof(9), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_rgb2ycrcb_0_0_dp_ram_11 is + port ( + D : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \read_ptr_reg[0]\ : out STD_LOGIC; + p_0_in : out STD_LOGIC; + reg_update : out STD_LOGIC; + sof_late_i_reg : out STD_LOGIC_VECTOR ( 25 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); + empty_match_reg : in STD_LOGIC; + fifo_rd_i_reg : in STD_LOGIC; + depth_match_reg : in STD_LOGIC; + resetn_out : in STD_LOGIC; + \genr_control_regs[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + aclken : in STD_LOGIC; + s_axis_video_tvalid : in STD_LOGIC; + s_axis_video_tready : in STD_LOGIC; + aclk : in STD_LOGIC; + da : in STD_LOGIC_VECTOR ( 25 downto 0 ); + \write_ptr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_rgb2ycrcb_0_0_dp_ram_11 : entity is "dp_ram"; +end Arty_Z7_20_v_rgb2ycrcb_0_0_dp_ram_11; + +architecture STRUCTURE of Arty_Z7_20_v_rgb2ycrcb_0_0_dp_ram_11 is + signal \^d\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^p_0_in\ : STD_LOGIC; + signal p_2_out : STD_LOGIC_VECTOR ( 25 downto 0 ); + signal \^read_ptr_reg[0]\ : STD_LOGIC; + signal \^sof_late_i_reg\ : STD_LOGIC_VECTOR ( 25 downto 0 ); + signal \NLW_GenerateDoutWriteFirstA.mem_reg_0_15_0_5_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_GenerateDoutWriteFirstA.mem_reg_0_15_12_17_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_GenerateDoutWriteFirstA.mem_reg_0_15_18_23_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_GenerateDoutWriteFirstA.mem_reg_0_15_24_25_DOB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_GenerateDoutWriteFirstA.mem_reg_0_15_24_25_DOC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_GenerateDoutWriteFirstA.mem_reg_0_15_24_25_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_GenerateDoutWriteFirstA.mem_reg_0_15_6_11_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute METHODOLOGY_DRC_VIOS : string; + attribute METHODOLOGY_DRC_VIOS of \GenerateDoutWriteFirstA.mem_reg_0_15_0_5\ : label is ""; + attribute METHODOLOGY_DRC_VIOS of \GenerateDoutWriteFirstA.mem_reg_0_15_12_17\ : label is ""; + attribute METHODOLOGY_DRC_VIOS of \GenerateDoutWriteFirstA.mem_reg_0_15_18_23\ : label is ""; + attribute METHODOLOGY_DRC_VIOS of \GenerateDoutWriteFirstA.mem_reg_0_15_24_25\ : label is ""; + attribute METHODOLOGY_DRC_VIOS of \GenerateDoutWriteFirstA.mem_reg_0_15_6_11\ : label is ""; +begin + D(3 downto 0) <= \^d\(3 downto 0); + p_0_in <= \^p_0_in\; + \read_ptr_reg[0]\ <= \^read_ptr_reg[0]\; + sof_late_i_reg(25 downto 0) <= \^sof_late_i_reg\(25 downto 0); +\GenerateDoutWriteFirstA.mem_reg_0_15_0_5\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000" + ) + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => \^d\(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => \^d\(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => \^d\(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => \write_ptr_reg[3]\(3 downto 0), + DIA(1 downto 0) => da(1 downto 0), + DIB(1 downto 0) => da(3 downto 2), + DIC(1 downto 0) => da(5 downto 4), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => p_2_out(1 downto 0), + DOB(1 downto 0) => p_2_out(3 downto 2), + DOC(1 downto 0) => p_2_out(5 downto 4), + DOD(1 downto 0) => \NLW_GenerateDoutWriteFirstA.mem_reg_0_15_0_5_DOD_UNCONNECTED\(1 downto 0), + WCLK => aclk, + WE => \^p_0_in\ + ); +\GenerateDoutWriteFirstA.mem_reg_0_15_0_5_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4000000000000000" + ) + port map ( + I0 => depth_match_reg, + I1 => resetn_out, + I2 => \genr_control_regs[0]\(0), + I3 => aclken, + I4 => s_axis_video_tvalid, + I5 => s_axis_video_tready, + O => \^p_0_in\ + ); +\GenerateDoutWriteFirstA.mem_reg_0_15_0_5_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAAAAAA" + ) + port map ( + I0 => Q(3), + I1 => Q(1), + I2 => \^read_ptr_reg[0]\, + I3 => Q(0), + I4 => Q(2), + O => \^d\(3) + ); +\GenerateDoutWriteFirstA.mem_reg_0_15_0_5_i_3__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => Q(2), + I1 => Q(0), + I2 => \^read_ptr_reg[0]\, + I3 => Q(1), + O => \^d\(2) + ); +\GenerateDoutWriteFirstA.mem_reg_0_15_0_5_i_4__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => Q(1), + I1 => \^read_ptr_reg[0]\, + I2 => Q(0), + O => \^d\(1) + ); +\GenerateDoutWriteFirstA.mem_reg_0_15_0_5_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => Q(0), + I1 => \^read_ptr_reg[0]\, + O => \^d\(0) + ); +\GenerateDoutWriteFirstA.mem_reg_0_15_0_5_i_6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => empty_match_reg, + I1 => fifo_rd_i_reg, + O => \^read_ptr_reg[0]\ + ); +\GenerateDoutWriteFirstA.mem_reg_0_15_12_17\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000" + ) + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => \^d\(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => \^d\(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => \^d\(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => \write_ptr_reg[3]\(3 downto 0), + DIA(1 downto 0) => da(13 downto 12), + DIB(1 downto 0) => da(15 downto 14), + DIC(1 downto 0) => da(17 downto 16), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => p_2_out(13 downto 12), + DOB(1 downto 0) => p_2_out(15 downto 14), + DOC(1 downto 0) => p_2_out(17 downto 16), + DOD(1 downto 0) => \NLW_GenerateDoutWriteFirstA.mem_reg_0_15_12_17_DOD_UNCONNECTED\(1 downto 0), + WCLK => aclk, + WE => \^p_0_in\ + ); +\GenerateDoutWriteFirstA.mem_reg_0_15_18_23\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000" + ) + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => \^d\(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => \^d\(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => \^d\(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => \write_ptr_reg[3]\(3 downto 0), + DIA(1 downto 0) => da(19 downto 18), + DIB(1 downto 0) => da(21 downto 20), + DIC(1 downto 0) => da(23 downto 22), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => p_2_out(19 downto 18), + DOB(1 downto 0) => p_2_out(21 downto 20), + DOC(1 downto 0) => p_2_out(23 downto 22), + DOD(1 downto 0) => \NLW_GenerateDoutWriteFirstA.mem_reg_0_15_18_23_DOD_UNCONNECTED\(1 downto 0), + WCLK => aclk, + WE => \^p_0_in\ + ); +\GenerateDoutWriteFirstA.mem_reg_0_15_24_25\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000" + ) + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => \^d\(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => \^d\(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => \^d\(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => \write_ptr_reg[3]\(3 downto 0), + DIA(1 downto 0) => da(25 downto 24), + DIB(1 downto 0) => B"00", + DIC(1 downto 0) => B"00", + DID(1 downto 0) => B"00", + DOA(1 downto 0) => p_2_out(25 downto 24), + DOB(1 downto 0) => \NLW_GenerateDoutWriteFirstA.mem_reg_0_15_24_25_DOB_UNCONNECTED\(1 downto 0), + DOC(1 downto 0) => \NLW_GenerateDoutWriteFirstA.mem_reg_0_15_24_25_DOC_UNCONNECTED\(1 downto 0), + DOD(1 downto 0) => \NLW_GenerateDoutWriteFirstA.mem_reg_0_15_24_25_DOD_UNCONNECTED\(1 downto 0), + WCLK => aclk, + WE => \^p_0_in\ + ); +\GenerateDoutWriteFirstA.mem_reg_0_15_6_11\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000" + ) + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => \^d\(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => \^d\(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => \^d\(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => \write_ptr_reg[3]\(3 downto 0), + DIA(1 downto 0) => da(7 downto 6), + DIB(1 downto 0) => da(9 downto 8), + DIC(1 downto 0) => da(11 downto 10), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => p_2_out(7 downto 6), + DOB(1 downto 0) => p_2_out(9 downto 8), + DOC(1 downto 0) => p_2_out(11 downto 10), + DOD(1 downto 0) => \NLW_GenerateDoutWriteFirstA.mem_reg_0_15_6_11_DOD_UNCONNECTED\(1 downto 0), + WCLK => aclk, + WE => \^p_0_in\ + ); +\GenerateDoutWriteFirstB.t_qb_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => p_2_out(0), + Q => \^sof_late_i_reg\(0), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => p_2_out(10), + Q => \^sof_late_i_reg\(10), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => p_2_out(11), + Q => \^sof_late_i_reg\(11), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => p_2_out(12), + Q => \^sof_late_i_reg\(12), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => p_2_out(13), + Q => \^sof_late_i_reg\(13), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => p_2_out(14), + Q => \^sof_late_i_reg\(14), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => p_2_out(15), + Q => \^sof_late_i_reg\(15), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => p_2_out(16), + Q => \^sof_late_i_reg\(16), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => p_2_out(17), + Q => \^sof_late_i_reg\(17), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => p_2_out(18), + Q => \^sof_late_i_reg\(18), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => p_2_out(19), + Q => \^sof_late_i_reg\(19), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => p_2_out(1), + Q => \^sof_late_i_reg\(1), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => p_2_out(20), + Q => \^sof_late_i_reg\(20), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => p_2_out(21), + Q => \^sof_late_i_reg\(21), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => p_2_out(22), + Q => \^sof_late_i_reg\(22), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => p_2_out(23), + Q => \^sof_late_i_reg\(23), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => p_2_out(24), + Q => \^sof_late_i_reg\(24), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => p_2_out(25), + Q => \^sof_late_i_reg\(25), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => p_2_out(2), + Q => \^sof_late_i_reg\(2), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => p_2_out(3), + Q => \^sof_late_i_reg\(3), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => p_2_out(4), + Q => \^sof_late_i_reg\(4), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => p_2_out(5), + Q => \^sof_late_i_reg\(5), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => p_2_out(6), + Q => \^sof_late_i_reg\(6), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => p_2_out(7), + Q => \^sof_late_i_reg\(7), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => p_2_out(8), + Q => \^sof_late_i_reg\(8), + R => '0' + ); +\GenerateDoutWriteFirstB.t_qb_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => p_2_out(9), + Q => \^sof_late_i_reg\(9), + R => '0' + ); +U_VIDEO_CTRL_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^sof_late_i_reg\(25), + I1 => \genr_control_regs[0]\(1), + O => reg_update + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_rgb2ycrcb_0_0_mac is + port ( + a : in STD_LOGIC_VECTOR ( 8 downto 0 ); + b : in STD_LOGIC_VECTOR ( 16 downto 0 ); + c : in STD_LOGIC_VECTOR ( 25 downto 0 ); + p : out STD_LOGIC_VECTOR ( 25 downto 0 ); + clk : in STD_LOGIC; + ce : in STD_LOGIC; + sclr : in STD_LOGIC + ); + attribute CREG : integer; + attribute CREG of Arty_Z7_20_v_rgb2ycrcb_0_0_mac : entity is 0; + attribute HAS_C : integer; + attribute HAS_C of Arty_Z7_20_v_rgb2ycrcb_0_0_mac : entity is 1; + attribute IWIDTHA : integer; + attribute IWIDTHA of Arty_Z7_20_v_rgb2ycrcb_0_0_mac : entity is 9; + attribute IWIDTHB : integer; + attribute IWIDTHB of Arty_Z7_20_v_rgb2ycrcb_0_0_mac : entity is 17; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_rgb2ycrcb_0_0_mac : entity is "mac"; + attribute OWIDTH : integer; + attribute OWIDTH of Arty_Z7_20_v_rgb2ycrcb_0_0_mac : entity is 26; + attribute ROUND_MODE : integer; + attribute ROUND_MODE of Arty_Z7_20_v_rgb2ycrcb_0_0_mac : entity is 0; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of Arty_Z7_20_v_rgb2ycrcb_0_0_mac : entity is "yes"; + attribute mult_style : string; + attribute mult_style of Arty_Z7_20_v_rgb2ycrcb_0_0_mac : entity is "pipe_block"; + attribute register_balancing : string; + attribute register_balancing of Arty_Z7_20_v_rgb2ycrcb_0_0_mac : entity is "yes"; + attribute use_dsp48 : string; + attribute use_dsp48 of Arty_Z7_20_v_rgb2ycrcb_0_0_mac : entity is "yes"; +end Arty_Z7_20_v_rgb2ycrcb_0_0_mac; + +architecture STRUCTURE of Arty_Z7_20_v_rgb2ycrcb_0_0_mac is + signal NLW_mac_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC; + signal NLW_mac_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC; + signal NLW_mac_reg_OVERFLOW_UNCONNECTED : STD_LOGIC; + signal NLW_mac_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC; + signal NLW_mac_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC; + signal NLW_mac_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC; + signal NLW_mac_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 ); + signal NLW_mac_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 ); + signal NLW_mac_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_mac_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 26 ); + signal NLW_mac_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 ); +begin +mac_reg: unisim.vcomponents.DSP48E1 + generic map( + ACASCREG => 1, + ADREG => 1, + ALUMODEREG => 0, + AREG => 1, + AUTORESET_PATDET => "NO_RESET", + A_INPUT => "DIRECT", + BCASCREG => 1, + BREG => 1, + B_INPUT => "DIRECT", + CARRYINREG => 0, + CARRYINSELREG => 0, + CREG => 0, + DREG => 1, + INMODEREG => 0, + MASK => X"3FFFFFFFFFFF", + MREG => 1, + OPMODEREG => 0, + PATTERN => X"000000000000", + PREG => 1, + SEL_MASK => "MASK", + SEL_PATTERN => "PATTERN", + USE_DPORT => false, + USE_MULT => "MULTIPLY", + USE_PATTERN_DETECT => "NO_PATDET", + USE_SIMD => "ONE48" + ) + port map ( + A(29) => b(16), + A(28) => b(16), + A(27) => b(16), + A(26) => b(16), + A(25) => b(16), + A(24) => b(16), + A(23) => b(16), + A(22) => b(16), + A(21) => b(16), + A(20) => b(16), + A(19) => b(16), + A(18) => b(16), + A(17) => b(16), + A(16 downto 0) => b(16 downto 0), + ACIN(29 downto 0) => B"000000000000000000000000000000", + ACOUT(29 downto 0) => NLW_mac_reg_ACOUT_UNCONNECTED(29 downto 0), + ALUMODE(3 downto 0) => B"0000", + B(17) => a(8), + B(16) => a(8), + B(15) => a(8), + B(14) => a(8), + B(13) => a(8), + B(12) => a(8), + B(11) => a(8), + B(10) => a(8), + B(9) => a(8), + B(8 downto 0) => a(8 downto 0), + BCIN(17 downto 0) => B"000000000000000000", + BCOUT(17 downto 0) => NLW_mac_reg_BCOUT_UNCONNECTED(17 downto 0), + C(47) => c(25), + C(46) => c(25), + C(45) => c(25), + C(44) => c(25), + C(43) => c(25), + C(42) => c(25), + C(41) => c(25), + C(40) => c(25), + C(39) => c(25), + C(38) => c(25), + C(37) => c(25), + C(36) => c(25), + C(35) => c(25), + C(34) => c(25), + C(33) => c(25), + C(32) => c(25), + C(31) => c(25), + C(30) => c(25), + C(29) => c(25), + C(28) => c(25), + C(27) => c(25), + C(26) => c(25), + C(25 downto 0) => c(25 downto 0), + CARRYCASCIN => '0', + CARRYCASCOUT => NLW_mac_reg_CARRYCASCOUT_UNCONNECTED, + CARRYIN => '0', + CARRYINSEL(2 downto 0) => B"000", + CARRYOUT(3 downto 0) => NLW_mac_reg_CARRYOUT_UNCONNECTED(3 downto 0), + CEA1 => '0', + CEA2 => ce, + CEAD => '0', + CEALUMODE => '0', + CEB1 => '0', + CEB2 => ce, + CEC => '0', + CECARRYIN => '0', + CECTRL => '0', + CED => '0', + CEINMODE => '0', + CEM => ce, + CEP => ce, + CLK => clk, + D(24 downto 0) => B"0000000000000000000000000", + INMODE(4 downto 0) => B"00000", + MULTSIGNIN => '0', + MULTSIGNOUT => NLW_mac_reg_MULTSIGNOUT_UNCONNECTED, + OPMODE(6 downto 0) => B"0110101", + OVERFLOW => NLW_mac_reg_OVERFLOW_UNCONNECTED, + P(47 downto 26) => NLW_mac_reg_P_UNCONNECTED(47 downto 26), + P(25 downto 0) => p(25 downto 0), + PATTERNBDETECT => NLW_mac_reg_PATTERNBDETECT_UNCONNECTED, + PATTERNDETECT => NLW_mac_reg_PATTERNDETECT_UNCONNECTED, + PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000", + PCOUT(47 downto 0) => NLW_mac_reg_PCOUT_UNCONNECTED(47 downto 0), + RSTA => sclr, + RSTALLCARRYIN => '0', + RSTALUMODE => '0', + RSTB => sclr, + RSTC => '0', + RSTCTRL => '0', + RSTD => '0', + RSTINMODE => '0', + RSTM => sclr, + RSTP => sclr, + UNDERFLOW => NLW_mac_reg_UNDERFLOW_UNCONNECTED + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized0\ is + port ( + a : in STD_LOGIC_VECTOR ( 10 downto 0 ); + b : in STD_LOGIC_VECTOR ( 16 downto 0 ); + c : in STD_LOGIC_VECTOR ( 11 downto 0 ); + p : out STD_LOGIC_VECTOR ( 11 downto 0 ); + clk : in STD_LOGIC; + ce : in STD_LOGIC; + sclr : in STD_LOGIC + ); + attribute CREG : integer; + attribute CREG of \Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized0\ : entity is 0; + attribute HAS_C : integer; + attribute HAS_C of \Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized0\ : entity is 1; + attribute IWIDTHA : integer; + attribute IWIDTHA of \Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized0\ : entity is 11; + attribute IWIDTHB : integer; + attribute IWIDTHB of \Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized0\ : entity is 17; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized0\ : entity is "mac"; + attribute OWIDTH : integer; + attribute OWIDTH of \Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized0\ : entity is 12; + attribute ROUND_MODE : integer; + attribute ROUND_MODE of \Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized0\ : entity is 0; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of \Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized0\ : entity is "yes"; + attribute mult_style : string; + attribute mult_style of \Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized0\ : entity is "pipe_block"; + attribute register_balancing : string; + attribute register_balancing of \Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized0\ : entity is "yes"; + attribute use_dsp48 : string; + attribute use_dsp48 of \Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized0\ : entity is "yes"; +end \Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized0\ is + signal mac_reg_n_100 : STD_LOGIC; + signal mac_reg_n_101 : STD_LOGIC; + signal mac_reg_n_102 : STD_LOGIC; + signal mac_reg_n_103 : STD_LOGIC; + signal mac_reg_n_104 : STD_LOGIC; + signal mac_reg_n_105 : STD_LOGIC; + signal mac_reg_n_90 : STD_LOGIC; + signal mac_reg_n_91 : STD_LOGIC; + signal mac_reg_n_92 : STD_LOGIC; + signal mac_reg_n_93 : STD_LOGIC; + signal mac_reg_n_94 : STD_LOGIC; + signal mac_reg_n_95 : STD_LOGIC; + signal mac_reg_n_96 : STD_LOGIC; + signal mac_reg_n_97 : STD_LOGIC; + signal mac_reg_n_98 : STD_LOGIC; + signal mac_reg_n_99 : STD_LOGIC; + signal NLW_mac_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC; + signal NLW_mac_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC; + signal NLW_mac_reg_OVERFLOW_UNCONNECTED : STD_LOGIC; + signal NLW_mac_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC; + signal NLW_mac_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC; + signal NLW_mac_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC; + signal NLW_mac_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 ); + signal NLW_mac_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 ); + signal NLW_mac_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_mac_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 28 ); + signal NLW_mac_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 ); +begin +mac_reg: unisim.vcomponents.DSP48E1 + generic map( + ACASCREG => 1, + ADREG => 1, + ALUMODEREG => 0, + AREG => 1, + AUTORESET_PATDET => "NO_RESET", + A_INPUT => "DIRECT", + BCASCREG => 1, + BREG => 1, + B_INPUT => "DIRECT", + CARRYINREG => 0, + CARRYINSELREG => 0, + CREG => 0, + DREG => 1, + INMODEREG => 0, + MASK => X"3FFFFFFFFFFF", + MREG => 1, + OPMODEREG => 0, + PATTERN => X"000000000000", + PREG => 1, + SEL_MASK => "MASK", + SEL_PATTERN => "PATTERN", + USE_DPORT => false, + USE_MULT => "MULTIPLY", + USE_PATTERN_DETECT => "NO_PATDET", + USE_SIMD => "ONE48" + ) + port map ( + A(29) => b(16), + A(28) => b(16), + A(27) => b(16), + A(26) => b(16), + A(25) => b(16), + A(24) => b(16), + A(23) => b(16), + A(22) => b(16), + A(21) => b(16), + A(20) => b(16), + A(19) => b(16), + A(18) => b(16), + A(17) => b(16), + A(16 downto 0) => b(16 downto 0), + ACIN(29 downto 0) => B"000000000000000000000000000000", + ACOUT(29 downto 0) => NLW_mac_reg_ACOUT_UNCONNECTED(29 downto 0), + ALUMODE(3 downto 0) => B"0000", + B(17) => a(10), + B(16) => a(10), + B(15) => a(10), + B(14) => a(10), + B(13) => a(10), + B(12) => a(10), + B(11) => a(10), + B(10 downto 0) => a(10 downto 0), + BCIN(17 downto 0) => B"000000000000000000", + BCOUT(17 downto 0) => NLW_mac_reg_BCOUT_UNCONNECTED(17 downto 0), + C(47) => c(11), + C(46) => c(11), + C(45) => c(11), + C(44) => c(11), + C(43) => c(11), + C(42) => c(11), + C(41) => c(11), + C(40) => c(11), + C(39) => c(11), + C(38) => c(11), + C(37) => c(11), + C(36) => c(11), + C(35) => c(11), + C(34) => c(11), + C(33) => c(11), + C(32) => c(11), + C(31) => c(11), + C(30) => c(11), + C(29) => c(11), + C(28) => c(11), + C(27 downto 16) => c(11 downto 0), + C(15 downto 0) => B"0111111111111111", + CARRYCASCIN => '0', + CARRYCASCOUT => NLW_mac_reg_CARRYCASCOUT_UNCONNECTED, + CARRYIN => '1', + CARRYINSEL(2 downto 0) => B"000", + CARRYOUT(3 downto 0) => NLW_mac_reg_CARRYOUT_UNCONNECTED(3 downto 0), + CEA1 => '0', + CEA2 => ce, + CEAD => '0', + CEALUMODE => '0', + CEB1 => '0', + CEB2 => ce, + CEC => '0', + CECARRYIN => '0', + CECTRL => '0', + CED => '0', + CEINMODE => '0', + CEM => ce, + CEP => ce, + CLK => clk, + D(24 downto 0) => B"0000000000000000000000000", + INMODE(4 downto 0) => B"00000", + MULTSIGNIN => '0', + MULTSIGNOUT => NLW_mac_reg_MULTSIGNOUT_UNCONNECTED, + OPMODE(6 downto 0) => B"0110101", + OVERFLOW => NLW_mac_reg_OVERFLOW_UNCONNECTED, + P(47 downto 28) => NLW_mac_reg_P_UNCONNECTED(47 downto 28), + P(27 downto 16) => p(11 downto 0), + P(15) => mac_reg_n_90, + P(14) => mac_reg_n_91, + P(13) => mac_reg_n_92, + P(12) => mac_reg_n_93, + P(11) => mac_reg_n_94, + P(10) => mac_reg_n_95, + P(9) => mac_reg_n_96, + P(8) => mac_reg_n_97, + P(7) => mac_reg_n_98, + P(6) => mac_reg_n_99, + P(5) => mac_reg_n_100, + P(4) => mac_reg_n_101, + P(3) => mac_reg_n_102, + P(2) => mac_reg_n_103, + P(1) => mac_reg_n_104, + P(0) => mac_reg_n_105, + PATTERNBDETECT => NLW_mac_reg_PATTERNBDETECT_UNCONNECTED, + PATTERNDETECT => NLW_mac_reg_PATTERNDETECT_UNCONNECTED, + PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000", + PCOUT(47 downto 0) => NLW_mac_reg_PCOUT_UNCONNECTED(47 downto 0), + RSTA => sclr, + RSTALLCARRYIN => '0', + RSTALUMODE => '0', + RSTB => sclr, + RSTC => '0', + RSTCTRL => '0', + RSTD => '0', + RSTINMODE => '0', + RSTM => sclr, + RSTP => sclr, + UNDERFLOW => NLW_mac_reg_UNDERFLOW_UNCONNECTED + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized1\ is + port ( + a : in STD_LOGIC_VECTOR ( 10 downto 0 ); + b : in STD_LOGIC_VECTOR ( 16 downto 0 ); + c : in STD_LOGIC_VECTOR ( 11 downto 0 ); + p : out STD_LOGIC_VECTOR ( 11 downto 0 ); + clk : in STD_LOGIC; + ce : in STD_LOGIC; + sclr : in STD_LOGIC + ); + attribute CREG : integer; + attribute CREG of \Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized1\ : entity is 0; + attribute HAS_C : integer; + attribute HAS_C of \Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized1\ : entity is 1; + attribute IWIDTHA : integer; + attribute IWIDTHA of \Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized1\ : entity is 11; + attribute IWIDTHB : integer; + attribute IWIDTHB of \Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized1\ : entity is 17; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized1\ : entity is "mac"; + attribute OWIDTH : integer; + attribute OWIDTH of \Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized1\ : entity is 12; + attribute ROUND_MODE : integer; + attribute ROUND_MODE of \Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized1\ : entity is 0; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of \Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized1\ : entity is "yes"; + attribute mult_style : string; + attribute mult_style of \Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized1\ : entity is "pipe_block"; + attribute register_balancing : string; + attribute register_balancing of \Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized1\ : entity is "yes"; + attribute use_dsp48 : string; + attribute use_dsp48 of \Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized1\ : entity is "yes"; +end \Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized1\; + +architecture STRUCTURE of \Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized1\ is + signal mac_reg_n_100 : STD_LOGIC; + signal mac_reg_n_101 : STD_LOGIC; + signal mac_reg_n_102 : STD_LOGIC; + signal mac_reg_n_103 : STD_LOGIC; + signal mac_reg_n_104 : STD_LOGIC; + signal mac_reg_n_105 : STD_LOGIC; + signal mac_reg_n_90 : STD_LOGIC; + signal mac_reg_n_91 : STD_LOGIC; + signal mac_reg_n_92 : STD_LOGIC; + signal mac_reg_n_93 : STD_LOGIC; + signal mac_reg_n_94 : STD_LOGIC; + signal mac_reg_n_95 : STD_LOGIC; + signal mac_reg_n_96 : STD_LOGIC; + signal mac_reg_n_97 : STD_LOGIC; + signal mac_reg_n_98 : STD_LOGIC; + signal mac_reg_n_99 : STD_LOGIC; + signal NLW_mac_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC; + signal NLW_mac_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC; + signal NLW_mac_reg_OVERFLOW_UNCONNECTED : STD_LOGIC; + signal NLW_mac_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC; + signal NLW_mac_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC; + signal NLW_mac_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC; + signal NLW_mac_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 ); + signal NLW_mac_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 ); + signal NLW_mac_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_mac_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 28 ); + signal NLW_mac_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 ); +begin +mac_reg: unisim.vcomponents.DSP48E1 + generic map( + ACASCREG => 1, + ADREG => 1, + ALUMODEREG => 0, + AREG => 1, + AUTORESET_PATDET => "NO_RESET", + A_INPUT => "DIRECT", + BCASCREG => 1, + BREG => 1, + B_INPUT => "DIRECT", + CARRYINREG => 0, + CARRYINSELREG => 0, + CREG => 0, + DREG => 1, + INMODEREG => 0, + MASK => X"3FFFFFFFFFFF", + MREG => 1, + OPMODEREG => 0, + PATTERN => X"000000000000", + PREG => 1, + SEL_MASK => "MASK", + SEL_PATTERN => "PATTERN", + USE_DPORT => false, + USE_MULT => "MULTIPLY", + USE_PATTERN_DETECT => "NO_PATDET", + USE_SIMD => "ONE48" + ) + port map ( + A(29) => b(16), + A(28) => b(16), + A(27) => b(16), + A(26) => b(16), + A(25) => b(16), + A(24) => b(16), + A(23) => b(16), + A(22) => b(16), + A(21) => b(16), + A(20) => b(16), + A(19) => b(16), + A(18) => b(16), + A(17) => b(16), + A(16 downto 0) => b(16 downto 0), + ACIN(29 downto 0) => B"000000000000000000000000000000", + ACOUT(29 downto 0) => NLW_mac_reg_ACOUT_UNCONNECTED(29 downto 0), + ALUMODE(3 downto 0) => B"0000", + B(17) => a(10), + B(16) => a(10), + B(15) => a(10), + B(14) => a(10), + B(13) => a(10), + B(12) => a(10), + B(11) => a(10), + B(10 downto 0) => a(10 downto 0), + BCIN(17 downto 0) => B"000000000000000000", + BCOUT(17 downto 0) => NLW_mac_reg_BCOUT_UNCONNECTED(17 downto 0), + C(47) => c(11), + C(46) => c(11), + C(45) => c(11), + C(44) => c(11), + C(43) => c(11), + C(42) => c(11), + C(41) => c(11), + C(40) => c(11), + C(39) => c(11), + C(38) => c(11), + C(37) => c(11), + C(36) => c(11), + C(35) => c(11), + C(34) => c(11), + C(33) => c(11), + C(32) => c(11), + C(31) => c(11), + C(30) => c(11), + C(29) => c(11), + C(28) => c(11), + C(27 downto 16) => c(11 downto 0), + C(15 downto 0) => B"0111111111111111", + CARRYCASCIN => '0', + CARRYCASCOUT => NLW_mac_reg_CARRYCASCOUT_UNCONNECTED, + CARRYIN => '1', + CARRYINSEL(2 downto 0) => B"000", + CARRYOUT(3 downto 0) => NLW_mac_reg_CARRYOUT_UNCONNECTED(3 downto 0), + CEA1 => '0', + CEA2 => ce, + CEAD => '0', + CEALUMODE => '0', + CEB1 => '0', + CEB2 => ce, + CEC => '0', + CECARRYIN => '0', + CECTRL => '0', + CED => '0', + CEINMODE => '0', + CEM => ce, + CEP => ce, + CLK => clk, + D(24 downto 0) => B"0000000000000000000000000", + INMODE(4 downto 0) => B"00000", + MULTSIGNIN => '0', + MULTSIGNOUT => NLW_mac_reg_MULTSIGNOUT_UNCONNECTED, + OPMODE(6 downto 0) => B"0110101", + OVERFLOW => NLW_mac_reg_OVERFLOW_UNCONNECTED, + P(47 downto 28) => NLW_mac_reg_P_UNCONNECTED(47 downto 28), + P(27 downto 16) => p(11 downto 0), + P(15) => mac_reg_n_90, + P(14) => mac_reg_n_91, + P(13) => mac_reg_n_92, + P(12) => mac_reg_n_93, + P(11) => mac_reg_n_94, + P(10) => mac_reg_n_95, + P(9) => mac_reg_n_96, + P(8) => mac_reg_n_97, + P(7) => mac_reg_n_98, + P(6) => mac_reg_n_99, + P(5) => mac_reg_n_100, + P(4) => mac_reg_n_101, + P(3) => mac_reg_n_102, + P(2) => mac_reg_n_103, + P(1) => mac_reg_n_104, + P(0) => mac_reg_n_105, + PATTERNBDETECT => NLW_mac_reg_PATTERNBDETECT_UNCONNECTED, + PATTERNDETECT => NLW_mac_reg_PATTERNDETECT_UNCONNECTED, + PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000", + PCOUT(47 downto 0) => NLW_mac_reg_PCOUT_UNCONNECTED(47 downto 0), + RSTA => sclr, + RSTALLCARRYIN => '0', + RSTALUMODE => '0', + RSTB => sclr, + RSTC => '0', + RSTCTRL => '0', + RSTD => '0', + RSTINMODE => '0', + RSTM => sclr, + RSTP => sclr, + UNDERFLOW => NLW_mac_reg_UNDERFLOW_UNCONNECTED + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl is + port ( + aclk : in STD_LOGIC; + aclk_en : in STD_LOGIC; + aresetn : in STD_LOGIC; + vid_aclk : in STD_LOGIC; + vid_aclk_en : in STD_LOGIC; + vid_aresetn : in STD_LOGIC; + reg_update : in STD_LOGIC; + irq : out STD_LOGIC; + resetn_out : out STD_LOGIC; + core_d_out : out STD_LOGIC; + ipif_addr_out : out STD_LOGIC_VECTOR ( 8 downto 0 ); + ipif_rnw_out : out STD_LOGIC; + ipif_cs_out : out STD_LOGIC; + ipif_data_out : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \genr_control_regs[0]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \genr_control_regs[1]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \genr_control_regs[2]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \genr_control_regs[3]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \genr_control_regs[4]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \genr_control_regs[5]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \genr_control_regs[6]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \genr_control_regs[7]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \genr_status_regs[0]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \genr_status_regs[1]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \genr_status_regs[2]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \genr_status_regs[3]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \genr_status_regs[4]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \genr_status_regs[5]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \genr_status_regs[6]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \genr_status_regs[7]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[0]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[1]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[0]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[1]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_control_regs[0]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_control_regs[1]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_control_regs[2]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_control_regs[3]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_control_regs[4]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_control_regs[5]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_control_regs[6]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_control_regs[7]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_control_regs[8]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_control_regs[9]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_control_regs[10]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_control_regs[11]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_control_regs[12]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_status_regs[0]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_status_regs[1]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_status_regs[2]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_status_regs[3]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_status_regs[4]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_status_regs[5]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_status_regs[6]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_status_regs[7]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_status_regs[8]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_status_regs[9]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_status_regs[10]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_status_regs[11]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_status_regs[12]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_arvalid : in STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rvalid : out STD_LOGIC; + s_axi_rready : in STD_LOGIC + ); + attribute C_COREGEN_PATCH : integer; + attribute C_COREGEN_PATCH of Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl : entity is 0; + attribute C_CORE_AXI_WRITE : string; + attribute C_CORE_AXI_WRITE of Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl : entity is "416'b00000000000000001111111111111111000000000000000011111111111111110000000000000000111111111111111100000000000000001111111111111111000000000000000011111111111111110000000000000000111111111111111100000000000000011111111111111111000000000000000111111111111111110000000000000001111111111111111100000000000000111111111111111111000000000000001111111111111111110000000000000011111111111111111100000000000000111111111111111111"; + attribute C_CORE_DBUFFER : string; + attribute C_CORE_DBUFFER of Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl : entity is "416'b00000000000000001111111111111111000000000000000011111111111111110000000000000000111111111111111100000000000000001111111111111111000000000000000011111111111111110000000000000000111111111111111100000000000000011111111111111111000000000000000111111111111111110000000000000001111111111111111100000000000000011111111111111111000000000000000111111111111111110000000000000001111111111111111100000000000000011111111111111111"; + attribute C_CORE_DEFAULT : string; + attribute C_CORE_DEFAULT of Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl : entity is "416'b00000000000000000000000011110000000000000000000000000000000100000000000000000000000000001111000000000000000000000000000000010000000000000000000000000000111100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000100000000000000000000000000000001000000000000000000000000100110010001011000000000000000000011101001011110000000000000000101101101000011100000000000000001001000001100010"; + attribute C_CORE_NUM_REGS : integer; + attribute C_CORE_NUM_REGS of Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl : entity is 13; + attribute C_FAMILY : string; + attribute C_FAMILY of Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl : entity is "zynq"; + attribute C_GENR_AXI_WRITE : string; + attribute C_GENR_AXI_WRITE of Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl : entity is "256'b1100000000000000000000000011111100000000000000010000000000001111000000000000000000000000000011110000000000000001000000000000111100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute C_GENR_DBUFFER : string; + attribute C_GENR_DBUFFER of Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl : entity is "256'b0000000000000000000000000010110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute C_GENR_DEFAULT : string; + attribute C_GENR_DEFAULT of Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl : entity is "256'b0000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute C_GENR_NUM_REGS : integer; + attribute C_GENR_NUM_REGS of Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl : entity is 8; + attribute C_GENR_SELFCLR : string; + attribute C_GENR_SELFCLR of Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl : entity is "256'b0000000000000000000000000000000011111111111111111111111111111111111111111111111111111111111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute C_HAS_AXI4_LITE : integer; + attribute C_HAS_AXI4_LITE of Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl : entity is 0; + attribute C_HAS_IRQ : integer; + attribute C_HAS_IRQ of Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl : entity is 1; + attribute C_IS_EVAL : string; + attribute C_IS_EVAL of Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl : entity is "FALSE"; + attribute C_REVISION_NUMBER : integer; + attribute C_REVISION_NUMBER of Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl : entity is 1; + attribute C_SRESET_LENGTH : integer; + attribute C_SRESET_LENGTH of Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl : entity is 1; + attribute C_S_AXI_ADDR_WIDTH : integer; + attribute C_S_AXI_ADDR_WIDTH of Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl : entity is 9; + attribute C_S_AXI_DATA_WIDTH : integer; + attribute C_S_AXI_DATA_WIDTH of Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl : entity is 32; + attribute C_TIMEOUT_HOURS : integer; + attribute C_TIMEOUT_HOURS of Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl : entity is 8; + attribute C_TIMEOUT_MINS : integer; + attribute C_TIMEOUT_MINS of Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl : entity is 0; + attribute C_TIME_AXI_WRITE : string; + attribute C_TIME_AXI_WRITE of Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl : entity is "64'b1111111111111111111111111111111100000000000000000000000000000111"; + attribute C_TIME_DBUFFER : string; + attribute C_TIME_DBUFFER of Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl : entity is "64'b1111111111111111111111111111111100000000000000000000000000000111"; + attribute C_TIME_DEFAULT : string; + attribute C_TIME_DEFAULT of Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl : entity is "64'b0000001011010000000001010000000000000000000000000000000000000000"; + attribute C_TIME_NUM_REGS : integer; + attribute C_TIME_NUM_REGS of Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl : entity is 2; + attribute C_VERSION_MAJOR : integer; + attribute C_VERSION_MAJOR of Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl : entity is 7; + attribute C_VERSION_MINOR : integer; + attribute C_VERSION_MINOR of Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl : entity is 1; + attribute C_VERSION_REVISION : integer; + attribute C_VERSION_REVISION of Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl : entity is 0; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl : entity is "video_ctrl"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl : entity is "yes"; +end Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl; + +architecture STRUCTURE of Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl is + signal \\ : STD_LOGIC; + signal \\ : STD_LOGIC; + signal \^vid_aresetn\ : STD_LOGIC; +begin + \^vid_aresetn\ <= vid_aresetn; + \core_control_regs[0]\(31) <= \\; + \core_control_regs[0]\(30) <= \\; + \core_control_regs[0]\(29) <= \\; + \core_control_regs[0]\(28) <= \\; + \core_control_regs[0]\(27) <= \\; + \core_control_regs[0]\(26) <= \\; + \core_control_regs[0]\(25) <= \\; + \core_control_regs[0]\(24) <= \\; + \core_control_regs[0]\(23) <= \\; + \core_control_regs[0]\(22) <= \\; + \core_control_regs[0]\(21) <= \\; + \core_control_regs[0]\(20) <= \\; + \core_control_regs[0]\(19) <= \\; + \core_control_regs[0]\(18) <= \\; + \core_control_regs[0]\(17) <= \\; + \core_control_regs[0]\(16) <= \\; + \core_control_regs[0]\(15) <= \\; + \core_control_regs[0]\(14) <= \\; + \core_control_regs[0]\(13) <= \\; + \core_control_regs[0]\(12) <= \\; + \core_control_regs[0]\(11) <= \\; + \core_control_regs[0]\(10) <= \\; + \core_control_regs[0]\(9) <= \\; + \core_control_regs[0]\(8) <= \\; + \core_control_regs[0]\(7) <= \\; + \core_control_regs[0]\(6) <= \\; + \core_control_regs[0]\(5) <= \\; + \core_control_regs[0]\(4) <= \\; + \core_control_regs[0]\(3) <= \\; + \core_control_regs[0]\(2) <= \\; + \core_control_regs[0]\(1) <= \\; + \core_control_regs[0]\(0) <= \\; + \core_control_regs[10]\(31) <= \\; + \core_control_regs[10]\(30) <= \\; + \core_control_regs[10]\(29) <= \\; + \core_control_regs[10]\(28) <= \\; + \core_control_regs[10]\(27) <= \\; + \core_control_regs[10]\(26) <= \\; + \core_control_regs[10]\(25) <= \\; + \core_control_regs[10]\(24) <= \\; + \core_control_regs[10]\(23) <= \\; + \core_control_regs[10]\(22) <= \\; + \core_control_regs[10]\(21) <= \\; + \core_control_regs[10]\(20) <= \\; + \core_control_regs[10]\(19) <= \\; + \core_control_regs[10]\(18) <= \\; + \core_control_regs[10]\(17) <= \\; + \core_control_regs[10]\(16) <= \\; + \core_control_regs[10]\(15) <= \\; + \core_control_regs[10]\(14) <= \\; + \core_control_regs[10]\(13) <= \\; + \core_control_regs[10]\(12) <= \\; + \core_control_regs[10]\(11) <= \\; + \core_control_regs[10]\(10) <= \\; + \core_control_regs[10]\(9) <= \\; + \core_control_regs[10]\(8) <= \\; + \core_control_regs[10]\(7) <= \\; + \core_control_regs[10]\(6) <= \\; + \core_control_regs[10]\(5) <= \\; + \core_control_regs[10]\(4) <= \\; + \core_control_regs[10]\(3) <= \\; + \core_control_regs[10]\(2) <= \\; + \core_control_regs[10]\(1) <= \\; + \core_control_regs[10]\(0) <= \\; + \core_control_regs[11]\(31) <= \\; + \core_control_regs[11]\(30) <= \\; + \core_control_regs[11]\(29) <= \\; + \core_control_regs[11]\(28) <= \\; + \core_control_regs[11]\(27) <= \\; + \core_control_regs[11]\(26) <= \\; + \core_control_regs[11]\(25) <= \\; + \core_control_regs[11]\(24) <= \\; + \core_control_regs[11]\(23) <= \\; + \core_control_regs[11]\(22) <= \\; + \core_control_regs[11]\(21) <= \\; + \core_control_regs[11]\(20) <= \\; + \core_control_regs[11]\(19) <= \\; + \core_control_regs[11]\(18) <= \\; + \core_control_regs[11]\(17) <= \\; + \core_control_regs[11]\(16) <= \\; + \core_control_regs[11]\(15) <= \\; + \core_control_regs[11]\(14) <= \\; + \core_control_regs[11]\(13) <= \\; + \core_control_regs[11]\(12) <= \\; + \core_control_regs[11]\(11) <= \\; + \core_control_regs[11]\(10) <= \\; + \core_control_regs[11]\(9) <= \\; + \core_control_regs[11]\(8) <= \\; + \core_control_regs[11]\(7) <= \\; + \core_control_regs[11]\(6) <= \\; + \core_control_regs[11]\(5) <= \\; + \core_control_regs[11]\(4) <= \\; + \core_control_regs[11]\(3) <= \\; + \core_control_regs[11]\(2) <= \\; + \core_control_regs[11]\(1) <= \\; + \core_control_regs[11]\(0) <= \\; + \core_control_regs[12]\(31) <= \\; + \core_control_regs[12]\(30) <= \\; + \core_control_regs[12]\(29) <= \\; + \core_control_regs[12]\(28) <= \\; + \core_control_regs[12]\(27) <= \\; + \core_control_regs[12]\(26) <= \\; + \core_control_regs[12]\(25) <= \\; + \core_control_regs[12]\(24) <= \\; + \core_control_regs[12]\(23) <= \\; + \core_control_regs[12]\(22) <= \\; + \core_control_regs[12]\(21) <= \\; + \core_control_regs[12]\(20) <= \\; + \core_control_regs[12]\(19) <= \\; + \core_control_regs[12]\(18) <= \\; + \core_control_regs[12]\(17) <= \\; + \core_control_regs[12]\(16) <= \\; + \core_control_regs[12]\(15) <= \\; + \core_control_regs[12]\(14) <= \\; + \core_control_regs[12]\(13) <= \\; + \core_control_regs[12]\(12) <= \\; + \core_control_regs[12]\(11) <= \\; + \core_control_regs[12]\(10) <= \\; + \core_control_regs[12]\(9) <= \\; + \core_control_regs[12]\(8) <= \\; + \core_control_regs[12]\(7) <= \\; + \core_control_regs[12]\(6) <= \\; + \core_control_regs[12]\(5) <= \\; + \core_control_regs[12]\(4) <= \\; + \core_control_regs[12]\(3) <= \\; + \core_control_regs[12]\(2) <= \\; + \core_control_regs[12]\(1) <= \\; + \core_control_regs[12]\(0) <= \\; + \core_control_regs[1]\(31) <= \\; + \core_control_regs[1]\(30) <= \\; + \core_control_regs[1]\(29) <= \\; + \core_control_regs[1]\(28) <= \\; + \core_control_regs[1]\(27) <= \\; + \core_control_regs[1]\(26) <= \\; + \core_control_regs[1]\(25) <= \\; + \core_control_regs[1]\(24) <= \\; + \core_control_regs[1]\(23) <= \\; + \core_control_regs[1]\(22) <= \\; + \core_control_regs[1]\(21) <= \\; + \core_control_regs[1]\(20) <= \\; + \core_control_regs[1]\(19) <= \\; + \core_control_regs[1]\(18) <= \\; + \core_control_regs[1]\(17) <= \\; + \core_control_regs[1]\(16) <= \\; + \core_control_regs[1]\(15) <= \\; + \core_control_regs[1]\(14) <= \\; + \core_control_regs[1]\(13) <= \\; + \core_control_regs[1]\(12) <= \\; + \core_control_regs[1]\(11) <= \\; + \core_control_regs[1]\(10) <= \\; + \core_control_regs[1]\(9) <= \\; + \core_control_regs[1]\(8) <= \\; + \core_control_regs[1]\(7) <= \\; + \core_control_regs[1]\(6) <= \\; + \core_control_regs[1]\(5) <= \\; + \core_control_regs[1]\(4) <= \\; + \core_control_regs[1]\(3) <= \\; + \core_control_regs[1]\(2) <= \\; + \core_control_regs[1]\(1) <= \\; + \core_control_regs[1]\(0) <= \\; + \core_control_regs[2]\(31) <= \\; + \core_control_regs[2]\(30) <= \\; + \core_control_regs[2]\(29) <= \\; + \core_control_regs[2]\(28) <= \\; + \core_control_regs[2]\(27) <= \\; + \core_control_regs[2]\(26) <= \\; + \core_control_regs[2]\(25) <= \\; + \core_control_regs[2]\(24) <= \\; + \core_control_regs[2]\(23) <= \\; + \core_control_regs[2]\(22) <= \\; + \core_control_regs[2]\(21) <= \\; + \core_control_regs[2]\(20) <= \\; + \core_control_regs[2]\(19) <= \\; + \core_control_regs[2]\(18) <= \\; + \core_control_regs[2]\(17) <= \\; + \core_control_regs[2]\(16) <= \\; + \core_control_regs[2]\(15) <= \\; + \core_control_regs[2]\(14) <= \\; + \core_control_regs[2]\(13) <= \\; + \core_control_regs[2]\(12) <= \\; + \core_control_regs[2]\(11) <= \\; + \core_control_regs[2]\(10) <= \\; + \core_control_regs[2]\(9) <= \\; + \core_control_regs[2]\(8) <= \\; + \core_control_regs[2]\(7) <= \\; + \core_control_regs[2]\(6) <= \\; + \core_control_regs[2]\(5) <= \\; + \core_control_regs[2]\(4) <= \\; + \core_control_regs[2]\(3) <= \\; + \core_control_regs[2]\(2) <= \\; + \core_control_regs[2]\(1) <= \\; + \core_control_regs[2]\(0) <= \\; + \core_control_regs[3]\(31) <= \\; + \core_control_regs[3]\(30) <= \\; + \core_control_regs[3]\(29) <= \\; + \core_control_regs[3]\(28) <= \\; + \core_control_regs[3]\(27) <= \\; + \core_control_regs[3]\(26) <= \\; + \core_control_regs[3]\(25) <= \\; + \core_control_regs[3]\(24) <= \\; + \core_control_regs[3]\(23) <= \\; + \core_control_regs[3]\(22) <= \\; + \core_control_regs[3]\(21) <= \\; + \core_control_regs[3]\(20) <= \\; + \core_control_regs[3]\(19) <= \\; + \core_control_regs[3]\(18) <= \\; + \core_control_regs[3]\(17) <= \\; + \core_control_regs[3]\(16) <= \\; + \core_control_regs[3]\(15) <= \\; + \core_control_regs[3]\(14) <= \\; + \core_control_regs[3]\(13) <= \\; + \core_control_regs[3]\(12) <= \\; + \core_control_regs[3]\(11) <= \\; + \core_control_regs[3]\(10) <= \\; + \core_control_regs[3]\(9) <= \\; + \core_control_regs[3]\(8) <= \\; + \core_control_regs[3]\(7) <= \\; + \core_control_regs[3]\(6) <= \\; + \core_control_regs[3]\(5) <= \\; + \core_control_regs[3]\(4) <= \\; + \core_control_regs[3]\(3) <= \\; + \core_control_regs[3]\(2) <= \\; + \core_control_regs[3]\(1) <= \\; + \core_control_regs[3]\(0) <= \\; + \core_control_regs[4]\(31) <= \\; + \core_control_regs[4]\(30) <= \\; + \core_control_regs[4]\(29) <= \\; + \core_control_regs[4]\(28) <= \\; + \core_control_regs[4]\(27) <= \\; + \core_control_regs[4]\(26) <= \\; + \core_control_regs[4]\(25) <= \\; + \core_control_regs[4]\(24) <= \\; + \core_control_regs[4]\(23) <= \\; + \core_control_regs[4]\(22) <= \\; + \core_control_regs[4]\(21) <= \\; + \core_control_regs[4]\(20) <= \\; + \core_control_regs[4]\(19) <= \\; + \core_control_regs[4]\(18) <= \\; + \core_control_regs[4]\(17) <= \\; + \core_control_regs[4]\(16) <= \\; + \core_control_regs[4]\(15) <= \\; + \core_control_regs[4]\(14) <= \\; + \core_control_regs[4]\(13) <= \\; + \core_control_regs[4]\(12) <= \\; + \core_control_regs[4]\(11) <= \\; + \core_control_regs[4]\(10) <= \\; + \core_control_regs[4]\(9) <= \\; + \core_control_regs[4]\(8) <= \\; + \core_control_regs[4]\(7) <= \\; + \core_control_regs[4]\(6) <= \\; + \core_control_regs[4]\(5) <= \\; + \core_control_regs[4]\(4) <= \\; + \core_control_regs[4]\(3) <= \\; + \core_control_regs[4]\(2) <= \\; + \core_control_regs[4]\(1) <= \\; + \core_control_regs[4]\(0) <= \\; + \core_control_regs[5]\(31) <= \\; + \core_control_regs[5]\(30) <= \\; + \core_control_regs[5]\(29) <= \\; + \core_control_regs[5]\(28) <= \\; + \core_control_regs[5]\(27) <= \\; + \core_control_regs[5]\(26) <= \\; + \core_control_regs[5]\(25) <= \\; + \core_control_regs[5]\(24) <= \\; + \core_control_regs[5]\(23) <= \\; + \core_control_regs[5]\(22) <= \\; + \core_control_regs[5]\(21) <= \\; + \core_control_regs[5]\(20) <= \\; + \core_control_regs[5]\(19) <= \\; + \core_control_regs[5]\(18) <= \\; + \core_control_regs[5]\(17) <= \\; + \core_control_regs[5]\(16) <= \\; + \core_control_regs[5]\(15) <= \\; + \core_control_regs[5]\(14) <= \\; + \core_control_regs[5]\(13) <= \\; + \core_control_regs[5]\(12) <= \\; + \core_control_regs[5]\(11) <= \\; + \core_control_regs[5]\(10) <= \\; + \core_control_regs[5]\(9) <= \\; + \core_control_regs[5]\(8) <= \\; + \core_control_regs[5]\(7) <= \\; + \core_control_regs[5]\(6) <= \\; + \core_control_regs[5]\(5) <= \\; + \core_control_regs[5]\(4) <= \\; + \core_control_regs[5]\(3) <= \\; + \core_control_regs[5]\(2) <= \\; + \core_control_regs[5]\(1) <= \\; + \core_control_regs[5]\(0) <= \\; + \core_control_regs[6]\(31) <= \\; + \core_control_regs[6]\(30) <= \\; + \core_control_regs[6]\(29) <= \\; + \core_control_regs[6]\(28) <= \\; + \core_control_regs[6]\(27) <= \\; + \core_control_regs[6]\(26) <= \\; + \core_control_regs[6]\(25) <= \\; + \core_control_regs[6]\(24) <= \\; + \core_control_regs[6]\(23) <= \\; + \core_control_regs[6]\(22) <= \\; + \core_control_regs[6]\(21) <= \\; + \core_control_regs[6]\(20) <= \\; + \core_control_regs[6]\(19) <= \\; + \core_control_regs[6]\(18) <= \\; + \core_control_regs[6]\(17) <= \\; + \core_control_regs[6]\(16) <= \\; + \core_control_regs[6]\(15) <= \\; + \core_control_regs[6]\(14) <= \\; + \core_control_regs[6]\(13) <= \\; + \core_control_regs[6]\(12) <= \\; + \core_control_regs[6]\(11) <= \\; + \core_control_regs[6]\(10) <= \\; + \core_control_regs[6]\(9) <= \\; + \core_control_regs[6]\(8) <= \\; + \core_control_regs[6]\(7) <= \\; + \core_control_regs[6]\(6) <= \\; + \core_control_regs[6]\(5) <= \\; + \core_control_regs[6]\(4) <= \\; + \core_control_regs[6]\(3) <= \\; + \core_control_regs[6]\(2) <= \\; + \core_control_regs[6]\(1) <= \\; + \core_control_regs[6]\(0) <= \\; + \core_control_regs[7]\(31) <= \\; + \core_control_regs[7]\(30) <= \\; + \core_control_regs[7]\(29) <= \\; + \core_control_regs[7]\(28) <= \\; + \core_control_regs[7]\(27) <= \\; + \core_control_regs[7]\(26) <= \\; + \core_control_regs[7]\(25) <= \\; + \core_control_regs[7]\(24) <= \\; + \core_control_regs[7]\(23) <= \\; + \core_control_regs[7]\(22) <= \\; + \core_control_regs[7]\(21) <= \\; + \core_control_regs[7]\(20) <= \\; + \core_control_regs[7]\(19) <= \\; + \core_control_regs[7]\(18) <= \\; + \core_control_regs[7]\(17) <= \\; + \core_control_regs[7]\(16) <= \\; + \core_control_regs[7]\(15) <= \\; + \core_control_regs[7]\(14) <= \\; + \core_control_regs[7]\(13) <= \\; + \core_control_regs[7]\(12) <= \\; + \core_control_regs[7]\(11) <= \\; + \core_control_regs[7]\(10) <= \\; + \core_control_regs[7]\(9) <= \\; + \core_control_regs[7]\(8) <= \\; + \core_control_regs[7]\(7) <= \\; + \core_control_regs[7]\(6) <= \\; + \core_control_regs[7]\(5) <= \\; + \core_control_regs[7]\(4) <= \\; + \core_control_regs[7]\(3) <= \\; + \core_control_regs[7]\(2) <= \\; + \core_control_regs[7]\(1) <= \\; + \core_control_regs[7]\(0) <= \\; + \core_control_regs[8]\(31) <= \\; + \core_control_regs[8]\(30) <= \\; + \core_control_regs[8]\(29) <= \\; + \core_control_regs[8]\(28) <= \\; + \core_control_regs[8]\(27) <= \\; + \core_control_regs[8]\(26) <= \\; + \core_control_regs[8]\(25) <= \\; + \core_control_regs[8]\(24) <= \\; + \core_control_regs[8]\(23) <= \\; + \core_control_regs[8]\(22) <= \\; + \core_control_regs[8]\(21) <= \\; + \core_control_regs[8]\(20) <= \\; + \core_control_regs[8]\(19) <= \\; + \core_control_regs[8]\(18) <= \\; + \core_control_regs[8]\(17) <= \\; + \core_control_regs[8]\(16) <= \\; + \core_control_regs[8]\(15) <= \\; + \core_control_regs[8]\(14) <= \\; + \core_control_regs[8]\(13) <= \\; + \core_control_regs[8]\(12) <= \\; + \core_control_regs[8]\(11) <= \\; + \core_control_regs[8]\(10) <= \\; + \core_control_regs[8]\(9) <= \\; + \core_control_regs[8]\(8) <= \\; + \core_control_regs[8]\(7) <= \\; + \core_control_regs[8]\(6) <= \\; + \core_control_regs[8]\(5) <= \\; + \core_control_regs[8]\(4) <= \\; + \core_control_regs[8]\(3) <= \\; + \core_control_regs[8]\(2) <= \\; + \core_control_regs[8]\(1) <= \\; + \core_control_regs[8]\(0) <= \\; + \core_control_regs[9]\(31) <= \\; + \core_control_regs[9]\(30) <= \\; + \core_control_regs[9]\(29) <= \\; + \core_control_regs[9]\(28) <= \\; + \core_control_regs[9]\(27) <= \\; + \core_control_regs[9]\(26) <= \\; + \core_control_regs[9]\(25) <= \\; + \core_control_regs[9]\(24) <= \\; + \core_control_regs[9]\(23) <= \\; + \core_control_regs[9]\(22) <= \\; + \core_control_regs[9]\(21) <= \\; + \core_control_regs[9]\(20) <= \\; + \core_control_regs[9]\(19) <= \\; + \core_control_regs[9]\(18) <= \\; + \core_control_regs[9]\(17) <= \\; + \core_control_regs[9]\(16) <= \\; + \core_control_regs[9]\(15) <= \\; + \core_control_regs[9]\(14) <= \\; + \core_control_regs[9]\(13) <= \\; + \core_control_regs[9]\(12) <= \\; + \core_control_regs[9]\(11) <= \\; + \core_control_regs[9]\(10) <= \\; + \core_control_regs[9]\(9) <= \\; + \core_control_regs[9]\(8) <= \\; + \core_control_regs[9]\(7) <= \\; + \core_control_regs[9]\(6) <= \\; + \core_control_regs[9]\(5) <= \\; + \core_control_regs[9]\(4) <= \\; + \core_control_regs[9]\(3) <= \\; + \core_control_regs[9]\(2) <= \\; + \core_control_regs[9]\(1) <= \\; + \core_control_regs[9]\(0) <= \\; + core_d_out <= \\; + \genr_control_regs[0]\(31) <= \\; + \genr_control_regs[0]\(30) <= \\; + \genr_control_regs[0]\(29) <= \\; + \genr_control_regs[0]\(28) <= \\; + \genr_control_regs[0]\(27) <= \\; + \genr_control_regs[0]\(26) <= \\; + \genr_control_regs[0]\(25) <= \\; + \genr_control_regs[0]\(24) <= \\; + \genr_control_regs[0]\(23) <= \\; + \genr_control_regs[0]\(22) <= \\; + \genr_control_regs[0]\(21) <= \\; + \genr_control_regs[0]\(20) <= \\; + \genr_control_regs[0]\(19) <= \\; + \genr_control_regs[0]\(18) <= \\; + \genr_control_regs[0]\(17) <= \\; + \genr_control_regs[0]\(16) <= \\; + \genr_control_regs[0]\(15) <= \\; + \genr_control_regs[0]\(14) <= \\; + \genr_control_regs[0]\(13) <= \\; + \genr_control_regs[0]\(12) <= \\; + \genr_control_regs[0]\(11) <= \\; + \genr_control_regs[0]\(10) <= \\; + \genr_control_regs[0]\(9) <= \\; + \genr_control_regs[0]\(8) <= \\; + \genr_control_regs[0]\(7) <= \\; + \genr_control_regs[0]\(6) <= \\; + \genr_control_regs[0]\(5) <= \\; + \genr_control_regs[0]\(4) <= \\; + \genr_control_regs[0]\(3) <= \\; + \genr_control_regs[0]\(2) <= \\; + \genr_control_regs[0]\(1) <= \\; + \genr_control_regs[0]\(0) <= \\; + \genr_control_regs[1]\(31) <= \\; + \genr_control_regs[1]\(30) <= \\; + \genr_control_regs[1]\(29) <= \\; + \genr_control_regs[1]\(28) <= \\; + \genr_control_regs[1]\(27) <= \\; + \genr_control_regs[1]\(26) <= \\; + \genr_control_regs[1]\(25) <= \\; + \genr_control_regs[1]\(24) <= \\; + \genr_control_regs[1]\(23) <= \\; + \genr_control_regs[1]\(22) <= \\; + \genr_control_regs[1]\(21) <= \\; + \genr_control_regs[1]\(20) <= \\; + \genr_control_regs[1]\(19) <= \\; + \genr_control_regs[1]\(18) <= \\; + \genr_control_regs[1]\(17) <= \\; + \genr_control_regs[1]\(16) <= \\; + \genr_control_regs[1]\(15) <= \\; + \genr_control_regs[1]\(14) <= \\; + \genr_control_regs[1]\(13) <= \\; + \genr_control_regs[1]\(12) <= \\; + \genr_control_regs[1]\(11) <= \\; + \genr_control_regs[1]\(10) <= \\; + \genr_control_regs[1]\(9) <= \\; + \genr_control_regs[1]\(8) <= \\; + \genr_control_regs[1]\(7) <= \\; + \genr_control_regs[1]\(6) <= \\; + \genr_control_regs[1]\(5) <= \\; + \genr_control_regs[1]\(4) <= \\; + \genr_control_regs[1]\(3) <= \\; + \genr_control_regs[1]\(2) <= \\; + \genr_control_regs[1]\(1) <= \\; + \genr_control_regs[1]\(0) <= \\; + \genr_control_regs[2]\(31) <= \\; + \genr_control_regs[2]\(30) <= \\; + \genr_control_regs[2]\(29) <= \\; + \genr_control_regs[2]\(28) <= \\; + \genr_control_regs[2]\(27) <= \\; + \genr_control_regs[2]\(26) <= \\; + \genr_control_regs[2]\(25) <= \\; + \genr_control_regs[2]\(24) <= \\; + \genr_control_regs[2]\(23) <= \\; + \genr_control_regs[2]\(22) <= \\; + \genr_control_regs[2]\(21) <= \\; + \genr_control_regs[2]\(20) <= \\; + \genr_control_regs[2]\(19) <= \\; + \genr_control_regs[2]\(18) <= \\; + \genr_control_regs[2]\(17) <= \\; + \genr_control_regs[2]\(16) <= \\; + \genr_control_regs[2]\(15) <= \\; + \genr_control_regs[2]\(14) <= \\; + \genr_control_regs[2]\(13) <= \\; + \genr_control_regs[2]\(12) <= \\; + \genr_control_regs[2]\(11) <= \\; + \genr_control_regs[2]\(10) <= \\; + \genr_control_regs[2]\(9) <= \\; + \genr_control_regs[2]\(8) <= \\; + \genr_control_regs[2]\(7) <= \\; + \genr_control_regs[2]\(6) <= \\; + \genr_control_regs[2]\(5) <= \\; + \genr_control_regs[2]\(4) <= \\; + \genr_control_regs[2]\(3) <= \\; + \genr_control_regs[2]\(2) <= \\; + \genr_control_regs[2]\(1) <= \\; + \genr_control_regs[2]\(0) <= \\; + \genr_control_regs[3]\(31) <= \\; + \genr_control_regs[3]\(30) <= \\; + \genr_control_regs[3]\(29) <= \\; + \genr_control_regs[3]\(28) <= \\; + \genr_control_regs[3]\(27) <= \\; + \genr_control_regs[3]\(26) <= \\; + \genr_control_regs[3]\(25) <= \\; + \genr_control_regs[3]\(24) <= \\; + \genr_control_regs[3]\(23) <= \\; + \genr_control_regs[3]\(22) <= \\; + \genr_control_regs[3]\(21) <= \\; + \genr_control_regs[3]\(20) <= \\; + \genr_control_regs[3]\(19) <= \\; + \genr_control_regs[3]\(18) <= \\; + \genr_control_regs[3]\(17) <= \\; + \genr_control_regs[3]\(16) <= \\; + \genr_control_regs[3]\(15) <= \\; + \genr_control_regs[3]\(14) <= \\; + \genr_control_regs[3]\(13) <= \\; + \genr_control_regs[3]\(12) <= \\; + \genr_control_regs[3]\(11) <= \\; + \genr_control_regs[3]\(10) <= \\; + \genr_control_regs[3]\(9) <= \\; + \genr_control_regs[3]\(8) <= \\; + \genr_control_regs[3]\(7) <= \\; + \genr_control_regs[3]\(6) <= \\; + \genr_control_regs[3]\(5) <= \\; + \genr_control_regs[3]\(4) <= \\; + \genr_control_regs[3]\(3) <= \\; + \genr_control_regs[3]\(2) <= \\; + \genr_control_regs[3]\(1) <= \\; + \genr_control_regs[3]\(0) <= \\; + \genr_control_regs[4]\(31) <= \\; + \genr_control_regs[4]\(30) <= \\; + \genr_control_regs[4]\(29) <= \\; + \genr_control_regs[4]\(28) <= \\; + \genr_control_regs[4]\(27) <= \\; + \genr_control_regs[4]\(26) <= \\; + \genr_control_regs[4]\(25) <= \\; + \genr_control_regs[4]\(24) <= \\; + \genr_control_regs[4]\(23) <= \\; + \genr_control_regs[4]\(22) <= \\; + \genr_control_regs[4]\(21) <= \\; + \genr_control_regs[4]\(20) <= \\; + \genr_control_regs[4]\(19) <= \\; + \genr_control_regs[4]\(18) <= \\; + \genr_control_regs[4]\(17) <= \\; + \genr_control_regs[4]\(16) <= \\; + \genr_control_regs[4]\(15) <= \\; + \genr_control_regs[4]\(14) <= \\; + \genr_control_regs[4]\(13) <= \\; + \genr_control_regs[4]\(12) <= \\; + \genr_control_regs[4]\(11) <= \\; + \genr_control_regs[4]\(10) <= \\; + \genr_control_regs[4]\(9) <= \\; + \genr_control_regs[4]\(8) <= \\; + \genr_control_regs[4]\(7) <= \\; + \genr_control_regs[4]\(6) <= \\; + \genr_control_regs[4]\(5) <= \\; + \genr_control_regs[4]\(4) <= \\; + \genr_control_regs[4]\(3) <= \\; + \genr_control_regs[4]\(2) <= \\; + \genr_control_regs[4]\(1) <= \\; + \genr_control_regs[4]\(0) <= \\; + \genr_control_regs[5]\(31) <= \\; + \genr_control_regs[5]\(30) <= \\; + \genr_control_regs[5]\(29) <= \\; + \genr_control_regs[5]\(28) <= \\; + \genr_control_regs[5]\(27) <= \\; + \genr_control_regs[5]\(26) <= \\; + \genr_control_regs[5]\(25) <= \\; + \genr_control_regs[5]\(24) <= \\; + \genr_control_regs[5]\(23) <= \\; + \genr_control_regs[5]\(22) <= \\; + \genr_control_regs[5]\(21) <= \\; + \genr_control_regs[5]\(20) <= \\; + \genr_control_regs[5]\(19) <= \\; + \genr_control_regs[5]\(18) <= \\; + \genr_control_regs[5]\(17) <= \\; + \genr_control_regs[5]\(16) <= \\; + \genr_control_regs[5]\(15) <= \\; + \genr_control_regs[5]\(14) <= \\; + \genr_control_regs[5]\(13) <= \\; + \genr_control_regs[5]\(12) <= \\; + \genr_control_regs[5]\(11) <= \\; + \genr_control_regs[5]\(10) <= \\; + \genr_control_regs[5]\(9) <= \\; + \genr_control_regs[5]\(8) <= \\; + \genr_control_regs[5]\(7) <= \\; + \genr_control_regs[5]\(6) <= \\; + \genr_control_regs[5]\(5) <= \\; + \genr_control_regs[5]\(4) <= \\; + \genr_control_regs[5]\(3) <= \\; + \genr_control_regs[5]\(2) <= \\; + \genr_control_regs[5]\(1) <= \\; + \genr_control_regs[5]\(0) <= \\; + \genr_control_regs[6]\(31) <= \\; + \genr_control_regs[6]\(30) <= \\; + \genr_control_regs[6]\(29) <= \\; + \genr_control_regs[6]\(28) <= \\; + \genr_control_regs[6]\(27) <= \\; + \genr_control_regs[6]\(26) <= \\; + \genr_control_regs[6]\(25) <= \\; + \genr_control_regs[6]\(24) <= \\; + \genr_control_regs[6]\(23) <= \\; + \genr_control_regs[6]\(22) <= \\; + \genr_control_regs[6]\(21) <= \\; + \genr_control_regs[6]\(20) <= \\; + \genr_control_regs[6]\(19) <= \\; + \genr_control_regs[6]\(18) <= \\; + \genr_control_regs[6]\(17) <= \\; + \genr_control_regs[6]\(16) <= \\; + \genr_control_regs[6]\(15) <= \\; + \genr_control_regs[6]\(14) <= \\; + \genr_control_regs[6]\(13) <= \\; + \genr_control_regs[6]\(12) <= \\; + \genr_control_regs[6]\(11) <= \\; + \genr_control_regs[6]\(10) <= \\; + \genr_control_regs[6]\(9) <= \\; + \genr_control_regs[6]\(8) <= \\; + \genr_control_regs[6]\(7) <= \\; + \genr_control_regs[6]\(6) <= \\; + \genr_control_regs[6]\(5) <= \\; + \genr_control_regs[6]\(4) <= \\; + \genr_control_regs[6]\(3) <= \\; + \genr_control_regs[6]\(2) <= \\; + \genr_control_regs[6]\(1) <= \\; + \genr_control_regs[6]\(0) <= \\; + \genr_control_regs[7]\(31) <= \\; + \genr_control_regs[7]\(30) <= \\; + \genr_control_regs[7]\(29) <= \\; + \genr_control_regs[7]\(28) <= \\; + \genr_control_regs[7]\(27) <= \\; + \genr_control_regs[7]\(26) <= \\; + \genr_control_regs[7]\(25) <= \\; + \genr_control_regs[7]\(24) <= \\; + \genr_control_regs[7]\(23) <= \\; + \genr_control_regs[7]\(22) <= \\; + \genr_control_regs[7]\(21) <= \\; + \genr_control_regs[7]\(20) <= \\; + \genr_control_regs[7]\(19) <= \\; + \genr_control_regs[7]\(18) <= \\; + \genr_control_regs[7]\(17) <= \\; + \genr_control_regs[7]\(16) <= \\; + \genr_control_regs[7]\(15) <= \\; + \genr_control_regs[7]\(14) <= \\; + \genr_control_regs[7]\(13) <= \\; + \genr_control_regs[7]\(12) <= \\; + \genr_control_regs[7]\(11) <= \\; + \genr_control_regs[7]\(10) <= \\; + \genr_control_regs[7]\(9) <= \\; + \genr_control_regs[7]\(8) <= \\; + \genr_control_regs[7]\(7) <= \\; + \genr_control_regs[7]\(6) <= \\; + \genr_control_regs[7]\(5) <= \\; + \genr_control_regs[7]\(4) <= \\; + \genr_control_regs[7]\(3) <= \\; + \genr_control_regs[7]\(2) <= \\; + \genr_control_regs[7]\(1) <= \\; + \genr_control_regs[7]\(0) <= \\; + ipif_cs_out <= \\; + ipif_data_out(31) <= \\; + ipif_data_out(30) <= \\; + ipif_data_out(29) <= \\; + ipif_data_out(28) <= \\; + ipif_data_out(27) <= \\; + ipif_data_out(26) <= \\; + ipif_data_out(25) <= \\; + ipif_data_out(24) <= \\; + ipif_data_out(23) <= \\; + ipif_data_out(22) <= \\; + ipif_data_out(21) <= \\; + ipif_data_out(20) <= \\; + ipif_data_out(19) <= \\; + ipif_data_out(18) <= \\; + ipif_data_out(17) <= \\; + ipif_data_out(16) <= \\; + ipif_data_out(15) <= \\; + ipif_data_out(14) <= \\; + ipif_data_out(13) <= \\; + ipif_data_out(12) <= \\; + ipif_data_out(11) <= \\; + ipif_data_out(10) <= \\; + ipif_data_out(9) <= \\; + ipif_data_out(8) <= \\; + ipif_data_out(7) <= \\; + ipif_data_out(6) <= \\; + ipif_data_out(5) <= \\; + ipif_data_out(4) <= \\; + ipif_data_out(3) <= \\; + ipif_data_out(2) <= \\; + ipif_data_out(1) <= \\; + ipif_data_out(0) <= \\; + ipif_rnw_out <= \\; + irq <= \\; + resetn_out <= \^vid_aresetn\; + s_axi_arready <= \\; + s_axi_awready <= \\; + s_axi_bresp(1) <= \\; + s_axi_bresp(0) <= \\; + s_axi_bvalid <= \\; + s_axi_rdata(31) <= \\; + s_axi_rdata(30) <= \\; + s_axi_rdata(29) <= \\; + s_axi_rdata(28) <= \\; + s_axi_rdata(27) <= \\; + s_axi_rdata(26) <= \\; + s_axi_rdata(25) <= \\; + s_axi_rdata(24) <= \\; + s_axi_rdata(23) <= \\; + s_axi_rdata(22) <= \\; + s_axi_rdata(21) <= \\; + s_axi_rdata(20) <= \\; + s_axi_rdata(19) <= \\; + s_axi_rdata(18) <= \\; + s_axi_rdata(17) <= \\; + s_axi_rdata(16) <= \\; + s_axi_rdata(15) <= \\; + s_axi_rdata(14) <= \\; + s_axi_rdata(13) <= \\; + s_axi_rdata(12) <= \\; + s_axi_rdata(11) <= \\; + s_axi_rdata(10) <= \\; + s_axi_rdata(9) <= \\; + s_axi_rdata(8) <= \\; + s_axi_rdata(7) <= \\; + s_axi_rdata(6) <= \\; + s_axi_rdata(5) <= \\; + s_axi_rdata(4) <= \\; + s_axi_rdata(3) <= \\; + s_axi_rdata(2) <= \\; + s_axi_rdata(1) <= \\; + s_axi_rdata(0) <= \\; + s_axi_rresp(1) <= \\; + s_axi_rresp(0) <= \\; + s_axi_rvalid <= \\; + s_axi_wready <= \\; + \time_control_regs[0]\(31) <= \\; + \time_control_regs[0]\(30) <= \\; + \time_control_regs[0]\(29) <= \\; + \time_control_regs[0]\(28) <= \\; + \time_control_regs[0]\(27) <= \\; + \time_control_regs[0]\(26) <= \\; + \time_control_regs[0]\(25) <= \\; + \time_control_regs[0]\(24) <= \\; + \time_control_regs[0]\(23) <= \\; + \time_control_regs[0]\(22) <= \\; + \time_control_regs[0]\(21) <= \\; + \time_control_regs[0]\(20) <= \\; + \time_control_regs[0]\(19) <= \\; + \time_control_regs[0]\(18) <= \\; + \time_control_regs[0]\(17) <= \\; + \time_control_regs[0]\(16) <= \\; + \time_control_regs[0]\(15) <= \\; + \time_control_regs[0]\(14) <= \\; + \time_control_regs[0]\(13) <= \\; + \time_control_regs[0]\(12) <= \\; + \time_control_regs[0]\(11) <= \\; + \time_control_regs[0]\(10) <= \\; + \time_control_regs[0]\(9) <= \\; + \time_control_regs[0]\(8) <= \\; + \time_control_regs[0]\(7) <= \\; + \time_control_regs[0]\(6) <= \\; + \time_control_regs[0]\(5) <= \\; + \time_control_regs[0]\(4) <= \\; + \time_control_regs[0]\(3) <= \\; + \time_control_regs[0]\(2) <= \\; + \time_control_regs[0]\(1) <= \\; + \time_control_regs[0]\(0) <= \\; + \time_control_regs[1]\(31) <= \\; + \time_control_regs[1]\(30) <= \\; + \time_control_regs[1]\(29) <= \\; + \time_control_regs[1]\(28) <= \\; + \time_control_regs[1]\(27) <= \\; + \time_control_regs[1]\(26) <= \\; + \time_control_regs[1]\(25) <= \\; + \time_control_regs[1]\(24) <= \\; + \time_control_regs[1]\(23) <= \\; + \time_control_regs[1]\(22) <= \\; + \time_control_regs[1]\(21) <= \\; + \time_control_regs[1]\(20) <= \\; + \time_control_regs[1]\(19) <= \\; + \time_control_regs[1]\(18) <= \\; + \time_control_regs[1]\(17) <= \\; + \time_control_regs[1]\(16) <= \\; + \time_control_regs[1]\(15) <= \\; + \time_control_regs[1]\(14) <= \\; + \time_control_regs[1]\(13) <= \\; + \time_control_regs[1]\(12) <= \\; + \time_control_regs[1]\(11) <= \\; + \time_control_regs[1]\(10) <= \\; + \time_control_regs[1]\(9) <= \\; + \time_control_regs[1]\(8) <= \\; + \time_control_regs[1]\(7) <= \\; + \time_control_regs[1]\(6) <= \\; + \time_control_regs[1]\(5) <= \\; + \time_control_regs[1]\(4) <= \\; + \time_control_regs[1]\(3) <= \\; + \time_control_regs[1]\(2) <= \\; + \time_control_regs[1]\(1) <= \\; + \time_control_regs[1]\(0) <= \\; +GND: unisim.vcomponents.GND + port map ( + G => \\ + ); +VCC: unisim.vcomponents.VCC + port map ( + P => \\ + ); +i_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => ipif_addr_out(8) + ); +i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => ipif_addr_out(7) + ); +i_2: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => ipif_addr_out(6) + ); +i_3: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => ipif_addr_out(5) + ); +i_4: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => ipif_addr_out(4) + ); +i_5: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => ipif_addr_out(3) + ); +i_6: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => ipif_addr_out(2) + ); +i_7: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => ipif_addr_out(1) + ); +i_8: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => ipif_addr_out(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_rgb2ycrcb_0_0_max_sat is + port ( + \needs_delay.shift_register_reg[1][7]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + Q : out STD_LOGIC_VECTOR ( 8 downto 0 ); + S : out STD_LOGIC_VECTOR ( 3 downto 0 ); + DI : out STD_LOGIC_VECTOR ( 3 downto 0 ); + p : in STD_LOGIC_VECTOR ( 9 downto 0 ); + \core_control_regs[3]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + sclr : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + aclk : in STD_LOGIC; + \core_control_regs[2]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_rgb2ycrcb_0_0_max_sat : entity is "max_sat"; +end Arty_Z7_20_v_rgb2ycrcb_0_0_max_sat; + +architecture STRUCTURE of Arty_Z7_20_v_rgb2ycrcb_0_0_max_sat is + signal \gtOp_carry__0_n_3\ : STD_LOGIC; + signal gtOp_carry_n_0 : STD_LOGIC; + signal gtOp_carry_n_1 : STD_LOGIC; + signal gtOp_carry_n_2 : STD_LOGIC; + signal gtOp_carry_n_3 : STD_LOGIC; + signal \needs_delay.shift_register[1][0]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][1]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][2]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][3]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][4]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][5]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][6]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][7]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][8]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][9]_i_1_n_0\ : STD_LOGIC; + signal reg_n_0 : STD_LOGIC; + signal reg_n_1 : STD_LOGIC; + signal reg_n_20 : STD_LOGIC; + signal reg_n_21 : STD_LOGIC; + signal reg_n_22 : STD_LOGIC; + signal reg_n_23 : STD_LOGIC; + signal reg_n_24 : STD_LOGIC; + signal reg_n_25 : STD_LOGIC; + signal reg_n_26 : STD_LOGIC; + signal reg_n_27 : STD_LOGIC; + signal NLW_gtOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gtOp_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_gtOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][0]_i_1\ : label is "soft_lutpair29"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][1]_i_1\ : label is "soft_lutpair29"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][2]_i_1\ : label is "soft_lutpair30"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][3]_i_1\ : label is "soft_lutpair30"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][4]_i_1\ : label is "soft_lutpair31"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][5]_i_1\ : label is "soft_lutpair31"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][6]_i_1\ : label is "soft_lutpair32"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][7]_i_1\ : label is "soft_lutpair32"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][8]_i_1\ : label is "soft_lutpair33"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][9]_i_1\ : label is "soft_lutpair33"; +begin +gtOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => gtOp_carry_n_0, + CO(2) => gtOp_carry_n_1, + CO(1) => gtOp_carry_n_2, + CO(0) => gtOp_carry_n_3, + CYINIT => '0', + DI(3) => reg_n_24, + DI(2) => reg_n_25, + DI(1) => reg_n_26, + DI(0) => reg_n_27, + O(3 downto 0) => NLW_gtOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => reg_n_20, + S(2) => reg_n_21, + S(1) => reg_n_22, + S(0) => reg_n_23 + ); +\gtOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => gtOp_carry_n_0, + CO(3 downto 1) => \NLW_gtOp_carry__0_CO_UNCONNECTED\(3 downto 1), + CO(0) => \gtOp_carry__0_n_3\, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => reg_n_0, + O(3 downto 0) => \NLW_gtOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3 downto 1) => B"000", + S(0) => reg_n_1 + ); +\needs_delay.shift_register[1][0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[2]\(0), + I1 => p(0), + I2 => \gtOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][0]_i_1_n_0\ + ); +\needs_delay.shift_register[1][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[2]\(1), + I1 => p(1), + I2 => \gtOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][1]_i_1_n_0\ + ); +\needs_delay.shift_register[1][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[2]\(2), + I1 => p(2), + I2 => \gtOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][2]_i_1_n_0\ + ); +\needs_delay.shift_register[1][3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[2]\(3), + I1 => p(3), + I2 => \gtOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][3]_i_1_n_0\ + ); +\needs_delay.shift_register[1][4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[2]\(4), + I1 => p(4), + I2 => \gtOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][4]_i_1_n_0\ + ); +\needs_delay.shift_register[1][5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[2]\(5), + I1 => p(5), + I2 => \gtOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][5]_i_1_n_0\ + ); +\needs_delay.shift_register[1][6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[2]\(6), + I1 => p(6), + I2 => \gtOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][6]_i_1_n_0\ + ); +\needs_delay.shift_register[1][7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[2]\(7), + I1 => p(7), + I2 => \gtOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][7]_i_1_n_0\ + ); +\needs_delay.shift_register[1][8]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => p(8), + I1 => \gtOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][8]_i_1_n_0\ + ); +\needs_delay.shift_register[1][9]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => p(9), + I1 => \gtOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][9]_i_1_n_0\ + ); +reg: entity work.\Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized5_8\ + port map ( + D(9) => \needs_delay.shift_register[1][9]_i_1_n_0\, + D(8) => \needs_delay.shift_register[1][8]_i_1_n_0\, + D(7) => \needs_delay.shift_register[1][7]_i_1_n_0\, + D(6) => \needs_delay.shift_register[1][6]_i_1_n_0\, + D(5) => \needs_delay.shift_register[1][5]_i_1_n_0\, + D(4) => \needs_delay.shift_register[1][4]_i_1_n_0\, + D(3) => \needs_delay.shift_register[1][3]_i_1_n_0\, + D(2) => \needs_delay.shift_register[1][2]_i_1_n_0\, + D(1) => \needs_delay.shift_register[1][1]_i_1_n_0\, + D(0) => \needs_delay.shift_register[1][0]_i_1_n_0\, + DI(0) => reg_n_0, + E(0) => E(0), + Q(8 downto 0) => Q(8 downto 0), + S(0) => reg_n_1, + aclk => aclk, + \core_control_regs[2]\(7 downto 0) => \core_control_regs[2]\(7 downto 0), + \core_control_regs[3]\(7 downto 0) => \core_control_regs[3]\(7 downto 0), + \needs_delay.shift_register_reg[1][7]_0\(0) => \needs_delay.shift_register_reg[1][7]\(0), + \needs_delay.shift_register_reg[1][7]_1\(3 downto 0) => S(3 downto 0), + \needs_delay.shift_register_reg[1][7]_2\(3 downto 0) => DI(3 downto 0), + \needs_delay.shift_register_reg[1][9]_0\(3) => reg_n_20, + \needs_delay.shift_register_reg[1][9]_0\(2) => reg_n_21, + \needs_delay.shift_register_reg[1][9]_0\(1) => reg_n_22, + \needs_delay.shift_register_reg[1][9]_0\(0) => reg_n_23, + \needs_delay.shift_register_reg[1][9]_1\(3) => reg_n_24, + \needs_delay.shift_register_reg[1][9]_1\(2) => reg_n_25, + \needs_delay.shift_register_reg[1][9]_1\(1) => reg_n_26, + \needs_delay.shift_register_reg[1][9]_1\(0) => reg_n_27, + p(9 downto 0) => p(9 downto 0), + sclr => sclr + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_rgb2ycrcb_0_0_max_sat_2 is + port ( + \needs_delay.shift_register_reg[1][7]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + Q : out STD_LOGIC_VECTOR ( 8 downto 0 ); + S : out STD_LOGIC_VECTOR ( 3 downto 0 ); + DI : out STD_LOGIC_VECTOR ( 3 downto 0 ); + p : in STD_LOGIC_VECTOR ( 9 downto 0 ); + \core_control_regs[5]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + sclr : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + aclk : in STD_LOGIC; + \core_control_regs[4]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_rgb2ycrcb_0_0_max_sat_2 : entity is "max_sat"; +end Arty_Z7_20_v_rgb2ycrcb_0_0_max_sat_2; + +architecture STRUCTURE of Arty_Z7_20_v_rgb2ycrcb_0_0_max_sat_2 is + signal \gtOp_carry__0_n_3\ : STD_LOGIC; + signal gtOp_carry_n_0 : STD_LOGIC; + signal gtOp_carry_n_1 : STD_LOGIC; + signal gtOp_carry_n_2 : STD_LOGIC; + signal gtOp_carry_n_3 : STD_LOGIC; + signal \needs_delay.shift_register[1][0]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][1]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][2]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][3]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][4]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][5]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][6]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][7]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][8]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][9]_i_1_n_0\ : STD_LOGIC; + signal reg_n_0 : STD_LOGIC; + signal reg_n_1 : STD_LOGIC; + signal reg_n_20 : STD_LOGIC; + signal reg_n_21 : STD_LOGIC; + signal reg_n_22 : STD_LOGIC; + signal reg_n_23 : STD_LOGIC; + signal reg_n_24 : STD_LOGIC; + signal reg_n_25 : STD_LOGIC; + signal reg_n_26 : STD_LOGIC; + signal reg_n_27 : STD_LOGIC; + signal NLW_gtOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gtOp_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_gtOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][0]_i_1\ : label is "soft_lutpair34"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][1]_i_1\ : label is "soft_lutpair34"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][2]_i_1\ : label is "soft_lutpair35"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][3]_i_1\ : label is "soft_lutpair35"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][4]_i_1\ : label is "soft_lutpair36"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][5]_i_1\ : label is "soft_lutpair36"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][6]_i_1\ : label is "soft_lutpair37"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][7]_i_1\ : label is "soft_lutpair37"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][8]_i_1\ : label is "soft_lutpair38"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][9]_i_1\ : label is "soft_lutpair38"; +begin +gtOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => gtOp_carry_n_0, + CO(2) => gtOp_carry_n_1, + CO(1) => gtOp_carry_n_2, + CO(0) => gtOp_carry_n_3, + CYINIT => '0', + DI(3) => reg_n_24, + DI(2) => reg_n_25, + DI(1) => reg_n_26, + DI(0) => reg_n_27, + O(3 downto 0) => NLW_gtOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => reg_n_20, + S(2) => reg_n_21, + S(1) => reg_n_22, + S(0) => reg_n_23 + ); +\gtOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => gtOp_carry_n_0, + CO(3 downto 1) => \NLW_gtOp_carry__0_CO_UNCONNECTED\(3 downto 1), + CO(0) => \gtOp_carry__0_n_3\, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => reg_n_0, + O(3 downto 0) => \NLW_gtOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3 downto 1) => B"000", + S(0) => reg_n_1 + ); +\needs_delay.shift_register[1][0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[4]\(0), + I1 => p(0), + I2 => \gtOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][0]_i_1_n_0\ + ); +\needs_delay.shift_register[1][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[4]\(1), + I1 => p(1), + I2 => \gtOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][1]_i_1_n_0\ + ); +\needs_delay.shift_register[1][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[4]\(2), + I1 => p(2), + I2 => \gtOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][2]_i_1_n_0\ + ); +\needs_delay.shift_register[1][3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[4]\(3), + I1 => p(3), + I2 => \gtOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][3]_i_1_n_0\ + ); +\needs_delay.shift_register[1][4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[4]\(4), + I1 => p(4), + I2 => \gtOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][4]_i_1_n_0\ + ); +\needs_delay.shift_register[1][5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[4]\(5), + I1 => p(5), + I2 => \gtOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][5]_i_1_n_0\ + ); +\needs_delay.shift_register[1][6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[4]\(6), + I1 => p(6), + I2 => \gtOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][6]_i_1_n_0\ + ); +\needs_delay.shift_register[1][7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[4]\(7), + I1 => p(7), + I2 => \gtOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][7]_i_1_n_0\ + ); +\needs_delay.shift_register[1][8]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => p(8), + I1 => \gtOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][8]_i_1_n_0\ + ); +\needs_delay.shift_register[1][9]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => p(9), + I1 => \gtOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][9]_i_1_n_0\ + ); +reg: entity work.\Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized5_7\ + port map ( + D(9) => \needs_delay.shift_register[1][9]_i_1_n_0\, + D(8) => \needs_delay.shift_register[1][8]_i_1_n_0\, + D(7) => \needs_delay.shift_register[1][7]_i_1_n_0\, + D(6) => \needs_delay.shift_register[1][6]_i_1_n_0\, + D(5) => \needs_delay.shift_register[1][5]_i_1_n_0\, + D(4) => \needs_delay.shift_register[1][4]_i_1_n_0\, + D(3) => \needs_delay.shift_register[1][3]_i_1_n_0\, + D(2) => \needs_delay.shift_register[1][2]_i_1_n_0\, + D(1) => \needs_delay.shift_register[1][1]_i_1_n_0\, + D(0) => \needs_delay.shift_register[1][0]_i_1_n_0\, + DI(0) => reg_n_0, + E(0) => E(0), + Q(8 downto 0) => Q(8 downto 0), + S(0) => reg_n_1, + aclk => aclk, + \core_control_regs[4]\(7 downto 0) => \core_control_regs[4]\(7 downto 0), + \core_control_regs[5]\(7 downto 0) => \core_control_regs[5]\(7 downto 0), + \needs_delay.shift_register_reg[1][7]_0\(0) => \needs_delay.shift_register_reg[1][7]\(0), + \needs_delay.shift_register_reg[1][7]_1\(3 downto 0) => S(3 downto 0), + \needs_delay.shift_register_reg[1][7]_2\(3 downto 0) => DI(3 downto 0), + \needs_delay.shift_register_reg[1][9]_0\(3) => reg_n_20, + \needs_delay.shift_register_reg[1][9]_0\(2) => reg_n_21, + \needs_delay.shift_register_reg[1][9]_0\(1) => reg_n_22, + \needs_delay.shift_register_reg[1][9]_0\(0) => reg_n_23, + \needs_delay.shift_register_reg[1][9]_1\(3) => reg_n_24, + \needs_delay.shift_register_reg[1][9]_1\(2) => reg_n_25, + \needs_delay.shift_register_reg[1][9]_1\(1) => reg_n_26, + \needs_delay.shift_register_reg[1][9]_1\(0) => reg_n_27, + p(9 downto 0) => p(9 downto 0), + sclr => sclr + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_rgb2ycrcb_0_0_max_sat_3 is + port ( + \needs_delay.shift_register_reg[1][7]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + Q : out STD_LOGIC_VECTOR ( 8 downto 0 ); + \needs_delay.shift_register_reg[1][7]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \needs_delay.shift_register_reg[1][7]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + DI : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \needs_delay.shift_register_reg[3][8]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \needs_delay.shift_register_reg[3][8]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \core_control_regs[1]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + sclr : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + aclk : in STD_LOGIC; + \core_control_regs[0]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \needs_delay.shift_register_reg[3][0]\ : in STD_LOGIC; + \needs_delay.shift_register_reg[3][1]\ : in STD_LOGIC; + \needs_delay.shift_register_reg[3][2]\ : in STD_LOGIC; + \needs_delay.shift_register_reg[3][3]\ : in STD_LOGIC; + \needs_delay.shift_register_reg[3][4]\ : in STD_LOGIC; + \needs_delay.shift_register_reg[3][5]\ : in STD_LOGIC; + \needs_delay.shift_register_reg[3][6]\ : in STD_LOGIC; + \needs_delay.shift_register_reg[3][7]\ : in STD_LOGIC; + \needs_delay.shift_register_reg[3][8]_1\ : in STD_LOGIC; + \needs_delay.shift_register_reg[3][9]\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_rgb2ycrcb_0_0_max_sat_3 : entity is "max_sat"; +end Arty_Z7_20_v_rgb2ycrcb_0_0_max_sat_3; + +architecture STRUCTURE of Arty_Z7_20_v_rgb2ycrcb_0_0_max_sat_3 is + signal c : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal gtOp : STD_LOGIC; + signal gtOp_carry_n_0 : STD_LOGIC; + signal gtOp_carry_n_1 : STD_LOGIC; + signal gtOp_carry_n_2 : STD_LOGIC; + signal gtOp_carry_n_3 : STD_LOGIC; + signal NLW_gtOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gtOp_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_gtOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][0]_i_1\ : label is "soft_lutpair39"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][1]_i_1\ : label is "soft_lutpair39"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][2]_i_1\ : label is "soft_lutpair40"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][3]_i_1\ : label is "soft_lutpair40"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][4]_i_1\ : label is "soft_lutpair41"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][5]_i_1\ : label is "soft_lutpair41"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][6]_i_1\ : label is "soft_lutpair42"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][7]_i_1\ : label is "soft_lutpair42"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][8]_i_1\ : label is "soft_lutpair43"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][9]_i_1\ : label is "soft_lutpair43"; +begin +gtOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => gtOp_carry_n_0, + CO(2) => gtOp_carry_n_1, + CO(1) => gtOp_carry_n_2, + CO(0) => gtOp_carry_n_3, + CYINIT => '0', + DI(3 downto 0) => DI(3 downto 0), + O(3 downto 0) => NLW_gtOp_carry_O_UNCONNECTED(3 downto 0), + S(3 downto 0) => S(3 downto 0) + ); +\gtOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => gtOp_carry_n_0, + CO(3 downto 1) => \NLW_gtOp_carry__0_CO_UNCONNECTED\(3 downto 1), + CO(0) => gtOp, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => \needs_delay.shift_register_reg[3][8]\(0), + O(3 downto 0) => \NLW_gtOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3 downto 1) => B"000", + S(0) => \needs_delay.shift_register_reg[3][8]_0\(0) + ); +\needs_delay.shift_register[1][0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[0]\(0), + I1 => \needs_delay.shift_register_reg[3][0]\, + I2 => gtOp, + O => c(0) + ); +\needs_delay.shift_register[1][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[0]\(1), + I1 => \needs_delay.shift_register_reg[3][1]\, + I2 => gtOp, + O => c(1) + ); +\needs_delay.shift_register[1][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[0]\(2), + I1 => \needs_delay.shift_register_reg[3][2]\, + I2 => gtOp, + O => c(2) + ); +\needs_delay.shift_register[1][3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[0]\(3), + I1 => \needs_delay.shift_register_reg[3][3]\, + I2 => gtOp, + O => c(3) + ); +\needs_delay.shift_register[1][4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[0]\(4), + I1 => \needs_delay.shift_register_reg[3][4]\, + I2 => gtOp, + O => c(4) + ); +\needs_delay.shift_register[1][5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[0]\(5), + I1 => \needs_delay.shift_register_reg[3][5]\, + I2 => gtOp, + O => c(5) + ); +\needs_delay.shift_register[1][6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[0]\(6), + I1 => \needs_delay.shift_register_reg[3][6]\, + I2 => gtOp, + O => c(6) + ); +\needs_delay.shift_register[1][7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[0]\(7), + I1 => \needs_delay.shift_register_reg[3][7]\, + I2 => gtOp, + O => c(7) + ); +\needs_delay.shift_register[1][8]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \needs_delay.shift_register_reg[3][8]_1\, + I1 => gtOp, + O => c(8) + ); +\needs_delay.shift_register[1][9]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \needs_delay.shift_register_reg[3][9]\, + I1 => gtOp, + O => c(9) + ); +reg: entity work.\Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized5\ + port map ( + D(9 downto 0) => c(9 downto 0), + E(0) => E(0), + Q(8 downto 0) => Q(8 downto 0), + aclk => aclk, + \core_control_regs[1]\(7 downto 0) => \core_control_regs[1]\(7 downto 0), + \needs_delay.shift_register_reg[1][7]_0\(0) => \needs_delay.shift_register_reg[1][7]\(0), + \needs_delay.shift_register_reg[1][7]_1\(3 downto 0) => \needs_delay.shift_register_reg[1][7]_0\(3 downto 0), + \needs_delay.shift_register_reg[1][7]_2\(3 downto 0) => \needs_delay.shift_register_reg[1][7]_1\(3 downto 0), + sclr => sclr + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_rgb2ycrcb_0_0_min_sat is + port ( + da : out STD_LOGIC_VECTOR ( 7 downto 0 ); + DI : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S : in STD_LOGIC_VECTOR ( 3 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \needs_delay.shift_register_reg[1][8]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + sclr : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + aclk : in STD_LOGIC; + \core_control_regs[3]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_rgb2ycrcb_0_0_min_sat : entity is "min_sat"; +end Arty_Z7_20_v_rgb2ycrcb_0_0_min_sat; + +architecture STRUCTURE of Arty_Z7_20_v_rgb2ycrcb_0_0_min_sat is + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal \needs_delay.shift_register[1][0]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][1]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][2]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][3]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][4]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][5]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][6]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][7]_i_1_n_0\ : STD_LOGIC; + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][0]_i_1\ : label is "soft_lutpair17"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][1]_i_1\ : label is "soft_lutpair17"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][2]_i_1\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][3]_i_1\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][4]_i_1\ : label is "soft_lutpair19"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][5]_i_1\ : label is "soft_lutpair19"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][6]_i_1\ : label is "soft_lutpair20"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][7]_i_1\ : label is "soft_lutpair20"; +begin +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3 downto 0) => DI(3 downto 0), + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3 downto 0) => S(3 downto 0) + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3 downto 1) => \NLW_ltOp_carry__0_CO_UNCONNECTED\(3 downto 1), + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => Q(8), + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3 downto 1) => B"000", + S(0) => \needs_delay.shift_register_reg[1][8]\(0) + ); +\needs_delay.shift_register[1][0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[3]\(0), + I1 => Q(0), + I2 => \ltOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][0]_i_1_n_0\ + ); +\needs_delay.shift_register[1][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[3]\(1), + I1 => Q(1), + I2 => \ltOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][1]_i_1_n_0\ + ); +\needs_delay.shift_register[1][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[3]\(2), + I1 => Q(2), + I2 => \ltOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][2]_i_1_n_0\ + ); +\needs_delay.shift_register[1][3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[3]\(3), + I1 => Q(3), + I2 => \ltOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][3]_i_1_n_0\ + ); +\needs_delay.shift_register[1][4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[3]\(4), + I1 => Q(4), + I2 => \ltOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][4]_i_1_n_0\ + ); +\needs_delay.shift_register[1][5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[3]\(5), + I1 => Q(5), + I2 => \ltOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][5]_i_1_n_0\ + ); +\needs_delay.shift_register[1][6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[3]\(6), + I1 => Q(6), + I2 => \ltOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][6]_i_1_n_0\ + ); +\needs_delay.shift_register[1][7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[3]\(7), + I1 => Q(7), + I2 => \ltOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][7]_i_1_n_0\ + ); +reg: entity work.\Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized6_10\ + port map ( + D(7) => \needs_delay.shift_register[1][7]_i_1_n_0\, + D(6) => \needs_delay.shift_register[1][6]_i_1_n_0\, + D(5) => \needs_delay.shift_register[1][5]_i_1_n_0\, + D(4) => \needs_delay.shift_register[1][4]_i_1_n_0\, + D(3) => \needs_delay.shift_register[1][3]_i_1_n_0\, + D(2) => \needs_delay.shift_register[1][2]_i_1_n_0\, + D(1) => \needs_delay.shift_register[1][1]_i_1_n_0\, + D(0) => \needs_delay.shift_register[1][0]_i_1_n_0\, + E(0) => E(0), + aclk => aclk, + da(7 downto 0) => da(7 downto 0), + sclr => sclr + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_rgb2ycrcb_0_0_min_sat_0 is + port ( + da : out STD_LOGIC_VECTOR ( 7 downto 0 ); + DI : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S : in STD_LOGIC_VECTOR ( 3 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \needs_delay.shift_register_reg[1][8]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + sclr : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + aclk : in STD_LOGIC; + \core_control_regs[5]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_rgb2ycrcb_0_0_min_sat_0 : entity is "min_sat"; +end Arty_Z7_20_v_rgb2ycrcb_0_0_min_sat_0; + +architecture STRUCTURE of Arty_Z7_20_v_rgb2ycrcb_0_0_min_sat_0 is + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal \needs_delay.shift_register[1][0]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][1]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][2]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][3]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][4]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][5]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][6]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][7]_i_1_n_0\ : STD_LOGIC; + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][0]_i_1\ : label is "soft_lutpair21"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][1]_i_1\ : label is "soft_lutpair21"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][2]_i_1\ : label is "soft_lutpair22"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][3]_i_1\ : label is "soft_lutpair22"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][4]_i_1\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][5]_i_1\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][6]_i_1\ : label is "soft_lutpair24"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][7]_i_1\ : label is "soft_lutpair24"; +begin +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3 downto 0) => DI(3 downto 0), + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3 downto 0) => S(3 downto 0) + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3 downto 1) => \NLW_ltOp_carry__0_CO_UNCONNECTED\(3 downto 1), + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => Q(8), + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3 downto 1) => B"000", + S(0) => \needs_delay.shift_register_reg[1][8]\(0) + ); +\needs_delay.shift_register[1][0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[5]\(0), + I1 => Q(0), + I2 => \ltOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][0]_i_1_n_0\ + ); +\needs_delay.shift_register[1][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[5]\(1), + I1 => Q(1), + I2 => \ltOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][1]_i_1_n_0\ + ); +\needs_delay.shift_register[1][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[5]\(2), + I1 => Q(2), + I2 => \ltOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][2]_i_1_n_0\ + ); +\needs_delay.shift_register[1][3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[5]\(3), + I1 => Q(3), + I2 => \ltOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][3]_i_1_n_0\ + ); +\needs_delay.shift_register[1][4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[5]\(4), + I1 => Q(4), + I2 => \ltOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][4]_i_1_n_0\ + ); +\needs_delay.shift_register[1][5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[5]\(5), + I1 => Q(5), + I2 => \ltOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][5]_i_1_n_0\ + ); +\needs_delay.shift_register[1][6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[5]\(6), + I1 => Q(6), + I2 => \ltOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][6]_i_1_n_0\ + ); +\needs_delay.shift_register[1][7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[5]\(7), + I1 => Q(7), + I2 => \ltOp_carry__0_n_3\, + O => \needs_delay.shift_register[1][7]_i_1_n_0\ + ); +reg: entity work.\Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized6_9\ + port map ( + D(7) => \needs_delay.shift_register[1][7]_i_1_n_0\, + D(6) => \needs_delay.shift_register[1][6]_i_1_n_0\, + D(5) => \needs_delay.shift_register[1][5]_i_1_n_0\, + D(4) => \needs_delay.shift_register[1][4]_i_1_n_0\, + D(3) => \needs_delay.shift_register[1][3]_i_1_n_0\, + D(2) => \needs_delay.shift_register[1][2]_i_1_n_0\, + D(1) => \needs_delay.shift_register[1][1]_i_1_n_0\, + D(0) => \needs_delay.shift_register[1][0]_i_1_n_0\, + E(0) => E(0), + aclk => aclk, + da(7 downto 0) => da(7 downto 0), + sclr => sclr + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_rgb2ycrcb_0_0_min_sat_1 is + port ( + da : out STD_LOGIC_VECTOR ( 7 downto 0 ); + DI : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S : in STD_LOGIC_VECTOR ( 3 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \needs_delay.shift_register_reg[1][8]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + sclr : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + aclk : in STD_LOGIC; + \core_control_regs[1]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_rgb2ycrcb_0_0_min_sat_1 : entity is "min_sat"; +end Arty_Z7_20_v_rgb2ycrcb_0_0_min_sat_1; + +architecture STRUCTURE of Arty_Z7_20_v_rgb2ycrcb_0_0_min_sat_1 is + signal ltOp : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal \needs_delay.shift_register[1][0]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][1]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][2]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][3]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][4]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][5]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][6]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][7]_i_1_n_0\ : STD_LOGIC; + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][0]_i_1\ : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][1]_i_1\ : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][2]_i_1\ : label is "soft_lutpair26"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][3]_i_1\ : label is "soft_lutpair26"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][4]_i_1\ : label is "soft_lutpair27"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][5]_i_1\ : label is "soft_lutpair27"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][6]_i_1\ : label is "soft_lutpair28"; + attribute SOFT_HLUTNM of \needs_delay.shift_register[1][7]_i_1\ : label is "soft_lutpair28"; +begin +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3 downto 0) => DI(3 downto 0), + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3 downto 0) => S(3 downto 0) + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3 downto 1) => \NLW_ltOp_carry__0_CO_UNCONNECTED\(3 downto 1), + CO(0) => ltOp, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => Q(8), + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3 downto 1) => B"000", + S(0) => \needs_delay.shift_register_reg[1][8]\(0) + ); +\needs_delay.shift_register[1][0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[1]\(0), + I1 => Q(0), + I2 => ltOp, + O => \needs_delay.shift_register[1][0]_i_1_n_0\ + ); +\needs_delay.shift_register[1][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[1]\(1), + I1 => Q(1), + I2 => ltOp, + O => \needs_delay.shift_register[1][1]_i_1_n_0\ + ); +\needs_delay.shift_register[1][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[1]\(2), + I1 => Q(2), + I2 => ltOp, + O => \needs_delay.shift_register[1][2]_i_1_n_0\ + ); +\needs_delay.shift_register[1][3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[1]\(3), + I1 => Q(3), + I2 => ltOp, + O => \needs_delay.shift_register[1][3]_i_1_n_0\ + ); +\needs_delay.shift_register[1][4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[1]\(4), + I1 => Q(4), + I2 => ltOp, + O => \needs_delay.shift_register[1][4]_i_1_n_0\ + ); +\needs_delay.shift_register[1][5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[1]\(5), + I1 => Q(5), + I2 => ltOp, + O => \needs_delay.shift_register[1][5]_i_1_n_0\ + ); +\needs_delay.shift_register[1][6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[1]\(6), + I1 => Q(6), + I2 => ltOp, + O => \needs_delay.shift_register[1][6]_i_1_n_0\ + ); +\needs_delay.shift_register[1][7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \core_control_regs[1]\(7), + I1 => Q(7), + I2 => ltOp, + O => \needs_delay.shift_register[1][7]_i_1_n_0\ + ); +reg: entity work.\Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized6\ + port map ( + D(7) => \needs_delay.shift_register[1][7]_i_1_n_0\, + D(6) => \needs_delay.shift_register[1][6]_i_1_n_0\, + D(5) => \needs_delay.shift_register[1][5]_i_1_n_0\, + D(4) => \needs_delay.shift_register[1][4]_i_1_n_0\, + D(3) => \needs_delay.shift_register[1][3]_i_1_n_0\, + D(2) => \needs_delay.shift_register[1][2]_i_1_n_0\, + D(1) => \needs_delay.shift_register[1][1]_i_1_n_0\, + D(0) => \needs_delay.shift_register[1][0]_i_1_n_0\, + E(0) => E(0), + aclk => aclk, + da(7 downto 0) => da(7 downto 0), + sclr => sclr + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_rgb2ycrcb_0_0_mult is + port ( + c : out STD_LOGIC_VECTOR ( 25 downto 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + aclk : in STD_LOGIC; + sclr : in STD_LOGIC; + s : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \core_control_regs[9]\ : in STD_LOGIC_VECTOR ( 16 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_rgb2ycrcb_0_0_mult : entity is "mult"; +end Arty_Z7_20_v_rgb2ycrcb_0_0_mult; + +architecture STRUCTURE of Arty_Z7_20_v_rgb2ycrcb_0_0_mult is +begin +reg: entity work.\Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized0\ + port map ( + E(0) => E(0), + aclk => aclk, + c(25 downto 0) => c(25 downto 0), + \core_control_regs[9]\(16 downto 0) => \core_control_regs[9]\(16 downto 0), + s(8 downto 0) => s(8 downto 0), + sclr => sclr + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no is + port ( + s : out STD_LOGIC_VECTOR ( 8 downto 0 ); + p_0_in : out STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 15 downto 0 ); + sclr : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no : entity is "radd_sub_sclr_no"; +end Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no; + +architecture STRUCTURE of Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no is + signal out_s : STD_LOGIC_VECTOR ( 8 downto 0 ); + attribute RTL_KEEP : string; + attribute RTL_KEEP of out_s : signal is "true"; + attribute USE_DSP48 : string; + attribute USE_DSP48 of out_s : signal is "no"; +begin + s(8 downto 0) <= out_s(8 downto 0); +reg: entity work.Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr + port map ( + E(0) => E(0), + Q(15 downto 0) => Q(15 downto 0), + aclk => aclk, + out_s(8 downto 0) => out_s(8 downto 0), + p_0_in(0) => p_0_in(0), + sclr => sclr + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no_5 is + port ( + s : out STD_LOGIC_VECTOR ( 8 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 14 downto 0 ); + sclr : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + aclk : in STD_LOGIC; + p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no_5 : entity is "radd_sub_sclr_no"; +end Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no_5; + +architecture STRUCTURE of Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no_5 is + signal out_s : STD_LOGIC_VECTOR ( 8 downto 0 ); + attribute RTL_KEEP : string; + attribute RTL_KEEP of out_s : signal is "true"; + attribute USE_DSP48 : string; + attribute USE_DSP48 of out_s : signal is "no"; +begin + s(8 downto 0) <= out_s(8 downto 0); +reg: entity work.Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr_6 + port map ( + E(0) => E(0), + Q(14 downto 0) => Q(14 downto 0), + aclk => aclk, + out_s(8 downto 0) => out_s(8 downto 0), + p_0_in(0) => p_0_in(0), + sclr => sclr + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no__parameterized0\ is + port ( + S : out STD_LOGIC_VECTOR ( 0 to 0 ); + a : out STD_LOGIC_VECTOR ( 0 to 0 ); + \^s\ : out STD_LOGIC_VECTOR ( 8 downto 0 ); + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \needs_delay.shift_register_reg[1][10]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \needs_delay.shift_register_reg[1][3]\ : out STD_LOGIC; + DI : out STD_LOGIC_VECTOR ( 0 to 0 ); + \core_control_regs[6]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + p : in STD_LOGIC_VECTOR ( 8 downto 0 ); + CO : in STD_LOGIC_VECTOR ( 0 to 0 ); + \needs_delay.shift_register_reg[5][7]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + sclr : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + aclk : in STD_LOGIC; + y_intb : in STD_LOGIC_VECTOR ( 7 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no__parameterized0\ : entity is "radd_sub_sclr_no"; +end \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no__parameterized0\ is + signal \needs_delay.shift_register[1][3]_i_2_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][3]_i_3_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][3]_i_4_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][7]_i_2_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][7]_i_3_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][7]_i_4_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][7]_i_5_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][9]_i_2_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1_n_1\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1_n_2\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1_n_3\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][7]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][7]_i_1_n_1\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][7]_i_1_n_2\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][7]_i_1_n_3\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][9]_i_1_n_3\ : STD_LOGIC; + signal out_s : STD_LOGIC_VECTOR ( 9 downto 0 ); + attribute RTL_KEEP : string; + attribute RTL_KEEP of out_s : signal is "true"; + attribute USE_DSP48 : string; + attribute USE_DSP48 of out_s : signal is "no"; + signal plusOp : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal reg_n_0 : STD_LOGIC; + signal reg_n_1 : STD_LOGIC; + signal \NLW_needs_delay.shift_register_reg[1][9]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_needs_delay.shift_register_reg[1][9]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); +begin + \^s\(8 downto 0) <= out_s(8 downto 0); +\needs_delay.shift_register[1][10]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => out_s(9), + O => DI(0) + ); +\needs_delay.shift_register[1][10]_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => out_s(9), + I1 => \core_control_regs[6]\(0), + O => S(0) + ); +\needs_delay.shift_register[1][3]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => p(3), + I1 => y_intb(3), + O => \needs_delay.shift_register[1][3]_i_2_n_0\ + ); +\needs_delay.shift_register[1][3]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => p(2), + I1 => y_intb(2), + O => \needs_delay.shift_register[1][3]_i_3_n_0\ + ); +\needs_delay.shift_register[1][3]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => p(1), + I1 => y_intb(1), + O => \needs_delay.shift_register[1][3]_i_4_n_0\ + ); +\needs_delay.shift_register[1][3]_i_5__4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => out_s(0), + O => a(0) + ); +\needs_delay.shift_register[1][7]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => p(7), + I1 => y_intb(7), + O => \needs_delay.shift_register[1][7]_i_2_n_0\ + ); +\needs_delay.shift_register[1][7]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => p(6), + I1 => y_intb(6), + O => \needs_delay.shift_register[1][7]_i_3_n_0\ + ); +\needs_delay.shift_register[1][7]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => p(5), + I1 => y_intb(5), + O => \needs_delay.shift_register[1][7]_i_4_n_0\ + ); +\needs_delay.shift_register[1][7]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => p(4), + I1 => y_intb(4), + O => \needs_delay.shift_register[1][7]_i_5_n_0\ + ); +\needs_delay.shift_register[1][9]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => p(8), + O => \needs_delay.shift_register[1][9]_i_2_n_0\ + ); +\needs_delay.shift_register_reg[1][3]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \needs_delay.shift_register_reg[1][3]_i_1_n_0\, + CO(2) => \needs_delay.shift_register_reg[1][3]_i_1_n_1\, + CO(1) => \needs_delay.shift_register_reg[1][3]_i_1_n_2\, + CO(0) => \needs_delay.shift_register_reg[1][3]_i_1_n_3\, + CYINIT => y_intb(0), + DI(3 downto 0) => p(3 downto 0), + O(3 downto 0) => plusOp(3 downto 0), + S(3) => \needs_delay.shift_register[1][3]_i_2_n_0\, + S(2) => \needs_delay.shift_register[1][3]_i_3_n_0\, + S(1) => \needs_delay.shift_register[1][3]_i_4_n_0\, + S(0) => reg_n_1 + ); +\needs_delay.shift_register_reg[1][7]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \needs_delay.shift_register_reg[1][3]_i_1_n_0\, + CO(3) => \needs_delay.shift_register_reg[1][7]_i_1_n_0\, + CO(2) => \needs_delay.shift_register_reg[1][7]_i_1_n_1\, + CO(1) => \needs_delay.shift_register_reg[1][7]_i_1_n_2\, + CO(0) => \needs_delay.shift_register_reg[1][7]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => p(7 downto 4), + O(3 downto 0) => plusOp(7 downto 4), + S(3) => \needs_delay.shift_register[1][7]_i_2_n_0\, + S(2) => \needs_delay.shift_register[1][7]_i_3_n_0\, + S(1) => \needs_delay.shift_register[1][7]_i_4_n_0\, + S(0) => \needs_delay.shift_register[1][7]_i_5_n_0\ + ); +\needs_delay.shift_register_reg[1][9]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \needs_delay.shift_register_reg[1][7]_i_1_n_0\, + CO(3 downto 1) => \NLW_needs_delay.shift_register_reg[1][9]_i_1_CO_UNCONNECTED\(3 downto 1), + CO(0) => \needs_delay.shift_register_reg[1][9]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => \needs_delay.shift_register[1][9]_i_2_n_0\, + O(3 downto 2) => \NLW_needs_delay.shift_register_reg[1][9]_i_1_O_UNCONNECTED\(3 downto 2), + O(1 downto 0) => plusOp(9 downto 8), + S(3 downto 1) => B"001", + S(0) => reg_n_0 + ); +reg: entity work.\Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized1\ + port map ( + CO(0) => CO(0), + D(2 downto 0) => D(2 downto 0), + E(0) => E(0), + Q(9 downto 0) => out_s(9 downto 0), + a(1) => reg_n_0, + a(0) => reg_n_1, + aclk => aclk, + \needs_delay.shift_register_reg[1][10]\(2 downto 0) => \needs_delay.shift_register_reg[1][10]\(2 downto 0), + \needs_delay.shift_register_reg[1][3]_0\ => \needs_delay.shift_register_reg[1][3]\, + \needs_delay.shift_register_reg[5][7]\(0) => \needs_delay.shift_register_reg[5][7]\(0), + \out\(2 downto 1) => out_s(9 downto 8), + \out\(0) => out_s(0), + p(1) => p(8), + p(0) => p(0), + plusOp(9 downto 0) => plusOp(9 downto 0), + sclr => sclr + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no__parameterized1\ is + port ( + \out\ : out STD_LOGIC_VECTOR ( 10 downto 0 ); + sclr : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + D : in STD_LOGIC_VECTOR ( 10 downto 0 ); + aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no__parameterized1\ : entity is "radd_sub_sclr_no"; +end \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no__parameterized1\; + +architecture STRUCTURE of \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no__parameterized1\ is + signal out_s : STD_LOGIC_VECTOR ( 10 downto 0 ); + attribute RTL_KEEP : string; + attribute RTL_KEEP of out_s : signal is "true"; + attribute USE_DSP48 : string; + attribute USE_DSP48 of out_s : signal is "no"; +begin + \out\(10 downto 0) <= out_s(10 downto 0); +reg: entity work.\Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized2\ + port map ( + D(10 downto 0) => D(10 downto 0), + E(0) => E(0), + Q(10 downto 0) => out_s(10 downto 0), + aclk => aclk, + sclr => sclr + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no__parameterized2\ is + port ( + \out\ : out STD_LOGIC_VECTOR ( 10 downto 0 ); + sclr : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + D : in STD_LOGIC_VECTOR ( 10 downto 0 ); + aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no__parameterized2\ : entity is "radd_sub_sclr_no"; +end \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no__parameterized2\; + +architecture STRUCTURE of \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no__parameterized2\ is + signal out_s : STD_LOGIC_VECTOR ( 10 downto 0 ); + attribute RTL_KEEP : string; + attribute RTL_KEEP of out_s : signal is "true"; + attribute USE_DSP48 : string; + attribute USE_DSP48 of out_s : signal is "no"; +begin + \out\(10 downto 0) <= out_s(10 downto 0); +reg: entity work.\Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized3\ + port map ( + D(10 downto 0) => D(10 downto 0), + E(0) => E(0), + Q(10 downto 0) => out_s(10 downto 0), + aclk => aclk, + sclr => sclr + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no__parameterized3\ is + port ( + sclr : out STD_LOGIC; + \^s\ : out STD_LOGIC_VECTOR ( 9 downto 0 ); + resetn_out : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + aclk : in STD_LOGIC; + \core_control_regs[6]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \needs_delay.shift_register_reg[1][8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + a : in STD_LOGIC_VECTOR ( 0 to 0 ); + DI : in STD_LOGIC_VECTOR ( 0 to 0 ); + S : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no__parameterized3\ : entity is "radd_sub_sclr_no"; +end \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no__parameterized3\; + +architecture STRUCTURE of \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no__parameterized3\ is + signal \needs_delay.shift_register[1][10]_i_4_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][3]_i_2_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][3]_i_3_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][3]_i_4_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][7]_i_2_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][7]_i_3_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][7]_i_4_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register[1][7]_i_5_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][10]_i_1_n_2\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][10]_i_1_n_3\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1_n_1\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1_n_2\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][3]_i_1_n_3\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][7]_i_1_n_0\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][7]_i_1_n_1\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][7]_i_1_n_2\ : STD_LOGIC; + signal \needs_delay.shift_register_reg[1][7]_i_1_n_3\ : STD_LOGIC; + signal out_s : STD_LOGIC_VECTOR ( 10 downto 0 ); + attribute RTL_KEEP : string; + attribute RTL_KEEP of out_s : signal is "true"; + attribute USE_DSP48 : string; + attribute USE_DSP48 of out_s : signal is "no"; + signal plusOp : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal \NLW_needs_delay.shift_register_reg[1][10]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_needs_delay.shift_register_reg[1][10]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); +begin + \^s\(9 downto 0) <= out_s(9 downto 0); +\needs_delay.shift_register[1][10]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \needs_delay.shift_register_reg[1][8]\(8), + I1 => \core_control_regs[6]\(8), + O => \needs_delay.shift_register[1][10]_i_4_n_0\ + ); +\needs_delay.shift_register[1][3]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \needs_delay.shift_register_reg[1][8]\(3), + I1 => \core_control_regs[6]\(3), + O => \needs_delay.shift_register[1][3]_i_2_n_0\ + ); +\needs_delay.shift_register[1][3]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \needs_delay.shift_register_reg[1][8]\(2), + I1 => \core_control_regs[6]\(2), + O => \needs_delay.shift_register[1][3]_i_3_n_0\ + ); +\needs_delay.shift_register[1][3]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \needs_delay.shift_register_reg[1][8]\(1), + I1 => \core_control_regs[6]\(1), + O => \needs_delay.shift_register[1][3]_i_4_n_0\ + ); +\needs_delay.shift_register[1][7]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \needs_delay.shift_register_reg[1][8]\(7), + I1 => \core_control_regs[6]\(7), + O => \needs_delay.shift_register[1][7]_i_2_n_0\ + ); +\needs_delay.shift_register[1][7]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \needs_delay.shift_register_reg[1][8]\(6), + I1 => \core_control_regs[6]\(6), + O => \needs_delay.shift_register[1][7]_i_3_n_0\ + ); +\needs_delay.shift_register[1][7]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \needs_delay.shift_register_reg[1][8]\(5), + I1 => \core_control_regs[6]\(5), + O => \needs_delay.shift_register[1][7]_i_4_n_0\ + ); +\needs_delay.shift_register[1][7]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \needs_delay.shift_register_reg[1][8]\(4), + I1 => \core_control_regs[6]\(4), + O => \needs_delay.shift_register[1][7]_i_5_n_0\ + ); +\needs_delay.shift_register_reg[1][10]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \needs_delay.shift_register_reg[1][7]_i_1_n_0\, + CO(3 downto 2) => \NLW_needs_delay.shift_register_reg[1][10]_i_1_CO_UNCONNECTED\(3 downto 2), + CO(1) => \needs_delay.shift_register_reg[1][10]_i_1_n_2\, + CO(0) => \needs_delay.shift_register_reg[1][10]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1) => DI(0), + DI(0) => \needs_delay.shift_register_reg[1][8]\(8), + O(3) => \NLW_needs_delay.shift_register_reg[1][10]_i_1_O_UNCONNECTED\(3), + O(2 downto 0) => plusOp(10 downto 8), + S(3 downto 2) => B"01", + S(1) => S(0), + S(0) => \needs_delay.shift_register[1][10]_i_4_n_0\ + ); +\needs_delay.shift_register_reg[1][3]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \needs_delay.shift_register_reg[1][3]_i_1_n_0\, + CO(2) => \needs_delay.shift_register_reg[1][3]_i_1_n_1\, + CO(1) => \needs_delay.shift_register_reg[1][3]_i_1_n_2\, + CO(0) => \needs_delay.shift_register_reg[1][3]_i_1_n_3\, + CYINIT => \core_control_regs[6]\(0), + DI(3 downto 0) => \needs_delay.shift_register_reg[1][8]\(3 downto 0), + O(3 downto 0) => plusOp(3 downto 0), + S(3) => \needs_delay.shift_register[1][3]_i_2_n_0\, + S(2) => \needs_delay.shift_register[1][3]_i_3_n_0\, + S(1) => \needs_delay.shift_register[1][3]_i_4_n_0\, + S(0) => a(0) + ); +\needs_delay.shift_register_reg[1][7]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \needs_delay.shift_register_reg[1][3]_i_1_n_0\, + CO(3) => \needs_delay.shift_register_reg[1][7]_i_1_n_0\, + CO(2) => \needs_delay.shift_register_reg[1][7]_i_1_n_1\, + CO(1) => \needs_delay.shift_register_reg[1][7]_i_1_n_2\, + CO(0) => \needs_delay.shift_register_reg[1][7]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => \needs_delay.shift_register_reg[1][8]\(7 downto 4), + O(3 downto 0) => plusOp(7 downto 4), + S(3) => \needs_delay.shift_register[1][7]_i_2_n_0\, + S(2) => \needs_delay.shift_register[1][7]_i_3_n_0\, + S(1) => \needs_delay.shift_register[1][7]_i_4_n_0\, + S(0) => \needs_delay.shift_register[1][7]_i_5_n_0\ + ); +reg: entity work.\Arty_Z7_20_v_rgb2ycrcb_0_0_delay_sclr__parameterized4\ + port map ( + E(0) => E(0), + Q(10 downto 0) => out_s(10 downto 0), + SR(0) => sclr, + aclk => aclk, + plusOp(10 downto 0) => plusOp(10 downto 0), + resetn_out => resetn_out + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_rgb2ycrcb_0_0_synch_fifo is + port ( + empty_match_reg_0 : out STD_LOGIC; + empty_match_reg_1 : out STD_LOGIC; + s_axis_tready_int_reg : out STD_LOGIC; + \col_cnt_reg[12]\ : out STD_LOGIC; + reg_update : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 25 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + aclk : in STD_LOGIC; + fifo_rd_i_reg : in STD_LOGIC; + resetn_out : in STD_LOGIC; + \genr_control_regs[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + aclken : in STD_LOGIC; + s_axis_video_tvalid : in STD_LOGIC; + s_axis_video_tready : in STD_LOGIC; + da : in STD_LOGIC_VECTOR ( 25 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_rgb2ycrcb_0_0_synch_fifo : entity is "synch_fifo"; +end Arty_Z7_20_v_rgb2ycrcb_0_0_synch_fifo; + +architecture STRUCTURE of Arty_Z7_20_v_rgb2ycrcb_0_0_synch_fifo is + signal addra : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal addrb : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal depth_match_i_1_n_0 : STD_LOGIC; + signal depth_match_i_2_n_0 : STD_LOGIC; + signal depth_match_reg_n_0 : STD_LOGIC; + signal empty_match_i_1_n_0 : STD_LOGIC; + signal empty_match_i_2_n_0 : STD_LOGIC; + signal \^empty_match_reg_0\ : STD_LOGIC; + signal \^empty_match_reg_1\ : STD_LOGIC; + signal mem1_n_4 : STD_LOGIC; + signal p_0_in : STD_LOGIC; + signal \plusOp__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \read_ptr_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \word_count[0]_i_1_n_0\ : STD_LOGIC; + signal \word_count[1]_i_1_n_0\ : STD_LOGIC; + signal \word_count[2]_i_1_n_0\ : STD_LOGIC; + signal \word_count[3]_i_1_n_0\ : STD_LOGIC; + signal \word_count[4]_i_1_n_0\ : STD_LOGIC; + signal \word_count[4]_i_2_n_0\ : STD_LOGIC; + signal \word_count[4]_i_3_n_0\ : STD_LOGIC; + signal \word_count_reg_n_0_[0]\ : STD_LOGIC; + signal \word_count_reg_n_0_[1]\ : STD_LOGIC; + signal \word_count_reg_n_0_[2]\ : STD_LOGIC; + signal \word_count_reg_n_0_[3]\ : STD_LOGIC; + signal \word_count_reg_n_0_[4]\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of depth_match_i_2 : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of empty_match_i_3 : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of \word_count[1]_i_1\ : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of \word_count[2]_i_1\ : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of \write_ptr[0]_i_1\ : label is "soft_lutpair10"; + attribute SOFT_HLUTNM of \write_ptr[1]_i_1\ : label is "soft_lutpair10"; + attribute SOFT_HLUTNM of \write_ptr[2]_i_1\ : label is "soft_lutpair9"; + attribute SOFT_HLUTNM of \write_ptr[3]_i_1\ : label is "soft_lutpair9"; +begin + empty_match_reg_0 <= \^empty_match_reg_0\; + empty_match_reg_1 <= \^empty_match_reg_1\; +\col_cnt[12]_i_8\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAAAAAAAAB" + ) + port map ( + I0 => \^empty_match_reg_0\, + I1 => fifo_rd_i_reg, + I2 => \word_count_reg_n_0_[4]\, + I3 => \word_count_reg_n_0_[1]\, + I4 => \word_count_reg_n_0_[3]\, + I5 => \word_count_reg_n_0_[2]\, + O => \col_cnt_reg[12]\ + ); +depth_match_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"A0A0A0B0A000A0A0" + ) + port map ( + I0 => depth_match_reg_n_0, + I1 => empty_match_i_2_n_0, + I2 => resetn_out, + I3 => depth_match_i_2_n_0, + I4 => \word_count_reg_n_0_[0]\, + I5 => fifo_rd_i_reg, + O => depth_match_i_1_n_0 + ); +depth_match_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"BFFF" + ) + port map ( + I0 => \word_count_reg_n_0_[4]\, + I1 => \word_count_reg_n_0_[2]\, + I2 => \word_count_reg_n_0_[3]\, + I3 => \word_count_reg_n_0_[1]\, + O => depth_match_i_2_n_0 + ); +depth_match_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => depth_match_i_1_n_0, + Q => depth_match_reg_n_0, + R => '0' + ); +empty_match_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FCFF4000" + ) + port map ( + I0 => fifo_rd_i_reg, + I1 => \word_count_reg_n_0_[0]\, + I2 => empty_match_i_2_n_0, + I3 => \^empty_match_reg_1\, + I4 => \^empty_match_reg_0\, + O => empty_match_i_1_n_0 + ); +empty_match_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFFFFFF" + ) + port map ( + I0 => s_axis_video_tready, + I1 => s_axis_video_tvalid, + I2 => aclken, + I3 => \genr_control_regs[0]\(0), + I4 => resetn_out, + O => empty_match_i_2_n_0 + ); +empty_match_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => \word_count_reg_n_0_[4]\, + I1 => \word_count_reg_n_0_[1]\, + I2 => \word_count_reg_n_0_[3]\, + I3 => \word_count_reg_n_0_[2]\, + O => \^empty_match_reg_1\ + ); +empty_match_reg: unisim.vcomponents.FDSE + port map ( + C => aclk, + CE => '1', + D => empty_match_i_1_n_0, + Q => \^empty_match_reg_0\, + S => SR(0) + ); +mem1: entity work.Arty_Z7_20_v_rgb2ycrcb_0_0_dp_ram_11 + port map ( + D(3 downto 0) => addrb(3 downto 0), + Q(3 downto 0) => \read_ptr_reg__0\(3 downto 0), + aclk => aclk, + aclken => aclken, + da(25 downto 0) => da(25 downto 0), + depth_match_reg => depth_match_reg_n_0, + empty_match_reg => \^empty_match_reg_0\, + fifo_rd_i_reg => fifo_rd_i_reg, + \genr_control_regs[0]\(1 downto 0) => \genr_control_regs[0]\(1 downto 0), + p_0_in => p_0_in, + \read_ptr_reg[0]\ => mem1_n_4, + reg_update => reg_update, + resetn_out => resetn_out, + s_axis_video_tready => s_axis_video_tready, + s_axis_video_tvalid => s_axis_video_tvalid, + sof_late_i_reg(25 downto 0) => Q(25 downto 0), + \write_ptr_reg[3]\(3 downto 0) => addra(3 downto 0) + ); +\read_ptr_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => aclk, + CE => '1', + D => addrb(0), + Q => \read_ptr_reg__0\(0), + S => SR(0) + ); +\read_ptr_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => aclk, + CE => '1', + D => addrb(1), + Q => \read_ptr_reg__0\(1), + S => SR(0) + ); +\read_ptr_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => aclk, + CE => '1', + D => addrb(2), + Q => \read_ptr_reg__0\(2), + S => SR(0) + ); +\read_ptr_reg[3]\: unisim.vcomponents.FDSE + port map ( + C => aclk, + CE => '1', + D => addrb(3), + Q => \read_ptr_reg__0\(3), + S => SR(0) + ); +s_axis_tready_int_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"1555" + ) + port map ( + I0 => \word_count_reg_n_0_[4]\, + I1 => \word_count_reg_n_0_[2]\, + I2 => \word_count_reg_n_0_[3]\, + I3 => \word_count_reg_n_0_[1]\, + O => s_axis_tready_int_reg + ); +\word_count[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \word_count_reg_n_0_[0]\, + O => \word_count[0]_i_1_n_0\ + ); +\word_count[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9A65" + ) + port map ( + I0 => \word_count_reg_n_0_[0]\, + I1 => mem1_n_4, + I2 => p_0_in, + I3 => \word_count_reg_n_0_[1]\, + O => \word_count[1]_i_1_n_0\ + ); +\word_count[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"DF20F20D" + ) + port map ( + I0 => p_0_in, + I1 => mem1_n_4, + I2 => \word_count_reg_n_0_[0]\, + I3 => \word_count_reg_n_0_[2]\, + I4 => \word_count_reg_n_0_[1]\, + O => \word_count[2]_i_1_n_0\ + ); +\word_count[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"DFFF2000FFBA0045" + ) + port map ( + I0 => \word_count_reg_n_0_[0]\, + I1 => mem1_n_4, + I2 => p_0_in, + I3 => \word_count_reg_n_0_[1]\, + I4 => \word_count_reg_n_0_[3]\, + I5 => \word_count_reg_n_0_[2]\, + O => \word_count[3]_i_1_n_0\ + ); +\word_count[4]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => p_0_in, + I1 => mem1_n_4, + O => \word_count[4]_i_1_n_0\ + ); +\word_count[4]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AA6AAAAAAAAAA9AA" + ) + port map ( + I0 => \word_count_reg_n_0_[4]\, + I1 => \word_count_reg_n_0_[3]\, + I2 => \word_count_reg_n_0_[0]\, + I3 => \word_count[4]_i_3_n_0\, + I4 => \word_count_reg_n_0_[1]\, + I5 => \word_count_reg_n_0_[2]\, + O => \word_count[4]_i_2_n_0\ + ); +\word_count[4]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => mem1_n_4, + I1 => p_0_in, + O => \word_count[4]_i_3_n_0\ + ); +\word_count_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \word_count[4]_i_1_n_0\, + D => \word_count[0]_i_1_n_0\, + Q => \word_count_reg_n_0_[0]\, + R => SR(0) + ); +\word_count_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \word_count[4]_i_1_n_0\, + D => \word_count[1]_i_1_n_0\, + Q => \word_count_reg_n_0_[1]\, + R => SR(0) + ); +\word_count_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \word_count[4]_i_1_n_0\, + D => \word_count[2]_i_1_n_0\, + Q => \word_count_reg_n_0_[2]\, + R => SR(0) + ); +\word_count_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \word_count[4]_i_1_n_0\, + D => \word_count[3]_i_1_n_0\, + Q => \word_count_reg_n_0_[3]\, + R => SR(0) + ); +\word_count_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \word_count[4]_i_1_n_0\, + D => \word_count[4]_i_2_n_0\, + Q => \word_count_reg_n_0_[4]\, + R => SR(0) + ); +\write_ptr[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => addra(0), + O => \plusOp__0\(0) + ); +\write_ptr[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => addra(0), + I1 => addra(1), + O => \plusOp__0\(1) + ); +\write_ptr[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => addra(2), + I1 => addra(1), + I2 => addra(0), + O => \plusOp__0\(2) + ); +\write_ptr[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => addra(3), + I1 => addra(0), + I2 => addra(1), + I3 => addra(2), + O => \plusOp__0\(3) + ); +\write_ptr_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in, + D => \plusOp__0\(0), + Q => addra(0), + R => SR(0) + ); +\write_ptr_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in, + D => \plusOp__0\(1), + Q => addra(1), + R => SR(0) + ); +\write_ptr_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in, + D => \plusOp__0\(2), + Q => addra(2), + R => SR(0) + ); +\write_ptr_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_0_in, + D => \plusOp__0\(3), + Q => addra(3), + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_rgb2ycrcb_0_0_synch_fifo_fallthru is + port ( + \write_ptr_int_reg[0]_0\ : out STD_LOGIC; + \col_cnt_reg[12]\ : out STD_LOGIC; + \col_cnt_reg[12]_0\ : out STD_LOGIC; + \col_cnt_reg[12]_1\ : out STD_LOGIC; + m_axis_video_tvalid : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 25 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + aclk : in STD_LOGIC; + m_axis_video_tready : in STD_LOGIC; + aclken_0 : in STD_LOGIC; + \genr_control_regs[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + aclken : in STD_LOGIC; + empty_match_reg : in STD_LOGIC; + empty_match_reg_0 : in STD_LOGIC; + CO : in STD_LOGIC_VECTOR ( 0 to 0 ); + wen : in STD_LOGIC; + fifo_wr_i : in STD_LOGIC; + core_d_out : in STD_LOGIC; + eol_late_i_reg : in STD_LOGIC; + da : in STD_LOGIC_VECTOR ( 25 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_rgb2ycrcb_0_0_synch_fifo_fallthru : entity is "synch_fifo_fallthru"; +end Arty_Z7_20_v_rgb2ycrcb_0_0_synch_fifo_fallthru; + +architecture STRUCTURE of Arty_Z7_20_v_rgb2ycrcb_0_0_synch_fifo_fallthru is + signal L : STD_LOGIC_VECTOR ( 1 to 4 ); + signal axi_fifo_empty : STD_LOGIC; + signal \col_cnt[12]_i_10_n_0\ : STD_LOGIC; + signal \col_cnt[12]_i_11_n_0\ : STD_LOGIC; + signal \col_cnt[12]_i_12_n_0\ : STD_LOGIC; + signal \col_cnt[12]_i_13_n_0\ : STD_LOGIC; + signal \col_cnt[12]_i_14_n_0\ : STD_LOGIC; + signal \^col_cnt_reg[12]_0\ : STD_LOGIC; + signal \^col_cnt_reg[12]_1\ : STD_LOGIC; + signal empty_int_i_1_n_0 : STD_LOGIC; + signal empty_int_i_2_n_0 : STD_LOGIC; + signal empty_int_i_3_n_0 : STD_LOGIC; + signal empty_int_i_4_n_0 : STD_LOGIC; + signal empty_int_i_5_n_0 : STD_LOGIC; + signal eqOp0_out : STD_LOGIC; + signal full_int_i_2_n_0 : STD_LOGIC; + signal full_int_i_3_n_0 : STD_LOGIC; + signal mem1_n_0 : STD_LOGIC; + signal mem1_n_1 : STD_LOGIC; + signal mem1_n_2 : STD_LOGIC; + signal mem1_n_3 : STD_LOGIC; + signal mem1_n_4 : STD_LOGIC; + signal p_0_in : STD_LOGIC; + signal p_0_in0_in : STD_LOGIC; + signal p_1_in : STD_LOGIC; + signal p_1_in1_in : STD_LOGIC; + signal \read_ptr_int_reg_n_0_[0]\ : STD_LOGIC; + signal \read_ptr_int_reg_n_0_[1]\ : STD_LOGIC; + signal \read_ptr_int_reg_n_0_[2]\ : STD_LOGIC; + signal \read_ptr_int_reg_n_0_[3]\ : STD_LOGIC; + signal \write_ptr_int[0]_i_1_n_0\ : STD_LOGIC; + signal \write_ptr_int[1]_i_1_n_0\ : STD_LOGIC; + signal \write_ptr_int[2]_i_1_n_0\ : STD_LOGIC; + signal \write_ptr_int[3]_i_1_n_0\ : STD_LOGIC; + signal \^write_ptr_int_reg[0]_0\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \col_cnt[12]_i_11\ : label is "soft_lutpair14"; + attribute SOFT_HLUTNM of \col_cnt[12]_i_12\ : label is "soft_lutpair16"; + attribute SOFT_HLUTNM of \col_cnt[12]_i_13\ : label is "soft_lutpair11"; + attribute SOFT_HLUTNM of \col_cnt[12]_i_14\ : label is "soft_lutpair15"; + attribute SOFT_HLUTNM of empty_int_i_4 : label is "soft_lutpair15"; + attribute SOFT_HLUTNM of empty_int_i_5 : label is "soft_lutpair13"; + attribute SOFT_HLUTNM of full_int_i_3 : label is "soft_lutpair11"; + attribute SOFT_HLUTNM of m_axis_video_tvalid_INST_0 : label is "soft_lutpair13"; + attribute SOFT_HLUTNM of \read_ptr_int[4]_i_1\ : label is "soft_lutpair14"; + attribute SOFT_HLUTNM of \write_ptr_int[1]_i_1\ : label is "soft_lutpair16"; + attribute SOFT_HLUTNM of \write_ptr_int[2]_i_1\ : label is "soft_lutpair12"; + attribute SOFT_HLUTNM of \write_ptr_int[3]_i_1\ : label is "soft_lutpair12"; +begin + \col_cnt_reg[12]_0\ <= \^col_cnt_reg[12]_0\; + \col_cnt_reg[12]_1\ <= \^col_cnt_reg[12]_1\; + \write_ptr_int_reg[0]_0\ <= \^write_ptr_int_reg[0]_0\; +\col_cnt[12]_i_10\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AE8AAEAEAEAEEFAE" + ) + port map ( + I0 => empty_int_i_4_n_0, + I1 => \read_ptr_int_reg_n_0_[1]\, + I2 => L(3), + I3 => \read_ptr_int_reg_n_0_[0]\, + I4 => wen, + I5 => L(4), + O => \col_cnt[12]_i_10_n_0\ + ); +\col_cnt[12]_i_11\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => p_0_in, + I1 => p_1_in1_in, + O => \col_cnt[12]_i_11_n_0\ + ); +\col_cnt[12]_i_12\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6F" + ) + port map ( + I0 => wen, + I1 => L(4), + I2 => \read_ptr_int_reg_n_0_[0]\, + O => \col_cnt[12]_i_12_n_0\ + ); +\col_cnt[12]_i_13\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAA9555" + ) + port map ( + I0 => \read_ptr_int_reg_n_0_[2]\, + I1 => L(3), + I2 => wen, + I3 => L(4), + I4 => L(2), + O => \col_cnt[12]_i_13_n_0\ + ); +\col_cnt[12]_i_14\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9969" + ) + port map ( + I0 => L(1), + I1 => \read_ptr_int_reg_n_0_[3]\, + I2 => L(2), + I3 => \read_ptr_int_reg_n_0_[2]\, + O => \col_cnt[12]_i_14_n_0\ + ); +\col_cnt[12]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000001FF0101" + ) + port map ( + I0 => \^col_cnt_reg[12]_0\, + I1 => \^col_cnt_reg[12]_1\, + I2 => empty_match_reg, + I3 => empty_match_reg_0, + I4 => CO(0), + I5 => aclken_0, + O => \col_cnt_reg[12]\ + ); +\col_cnt[12]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2FD002FDFD022FD0" + ) + port map ( + I0 => L(2), + I1 => \read_ptr_int_reg_n_0_[2]\, + I2 => \col_cnt[12]_i_10_n_0\, + I3 => \col_cnt[12]_i_11_n_0\, + I4 => L(1), + I5 => \read_ptr_int_reg_n_0_[3]\, + O => \^col_cnt_reg[12]_0\ + ); +\col_cnt[12]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4920000049204920" + ) + port map ( + I0 => \col_cnt[12]_i_12_n_0\, + I1 => \read_ptr_int_reg_n_0_[1]\, + I2 => \write_ptr_int[1]_i_1_n_0\, + I3 => \col_cnt[12]_i_13_n_0\, + I4 => \col_cnt[12]_i_14_n_0\, + I5 => \col_cnt[12]_i_10_n_0\, + O => \^col_cnt_reg[12]_1\ + ); +empty_int_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0441100010000441" + ) + port map ( + I0 => empty_int_i_2_n_0, + I1 => L(1), + I2 => empty_int_i_3_n_0, + I3 => \read_ptr_int_reg_n_0_[3]\, + I4 => p_0_in, + I5 => p_1_in1_in, + O => empty_int_i_1_n_0 + ); +empty_int_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFBE7DFFBEFFFFBE" + ) + port map ( + I0 => empty_int_i_4_n_0, + I1 => L(4), + I2 => mem1_n_4, + I3 => \read_ptr_int_reg_n_0_[1]\, + I4 => L(3), + I5 => empty_int_i_5_n_0, + O => empty_int_i_2_n_0 + ); +empty_int_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"0020000000000000" + ) + port map ( + I0 => \read_ptr_int_reg_n_0_[1]\, + I1 => axi_fifo_empty, + I2 => m_axis_video_tready, + I3 => aclken_0, + I4 => \read_ptr_int_reg_n_0_[0]\, + I5 => \read_ptr_int_reg_n_0_[2]\, + O => empty_int_i_3_n_0 + ); +empty_int_i_4: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => L(2), + I1 => \read_ptr_int_reg_n_0_[2]\, + O => empty_int_i_4_n_0 + ); +empty_int_i_5: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000000" + ) + port map ( + I0 => axi_fifo_empty, + I1 => m_axis_video_tready, + I2 => aclken, + I3 => \genr_control_regs[0]\(0), + I4 => \read_ptr_int_reg_n_0_[0]\, + O => empty_int_i_5_n_0 + ); +empty_int_reg: unisim.vcomponents.FDSE + port map ( + C => aclk, + CE => '1', + D => empty_int_i_1_n_0, + Q => axi_fifo_empty, + S => SR(0) + ); +full_int_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"4008080404808040" + ) + port map ( + I0 => \read_ptr_int_reg_n_0_[3]\, + I1 => full_int_i_2_n_0, + I2 => p_0_in, + I3 => L(1), + I4 => full_int_i_3_n_0, + I5 => p_1_in1_in, + O => eqOp0_out + ); +full_int_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"0090900060000090" + ) + port map ( + I0 => \read_ptr_int_reg_n_0_[1]\, + I1 => L(3), + I2 => \col_cnt[12]_i_13_n_0\, + I3 => L(4), + I4 => wen, + I5 => \read_ptr_int_reg_n_0_[0]\, + O => full_int_i_2_n_0 + ); +full_int_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => L(2), + I1 => L(4), + I2 => wen, + I3 => L(3), + O => full_int_i_3_n_0 + ); +full_int_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => eqOp0_out, + Q => \^write_ptr_int_reg[0]_0\, + R => SR(0) + ); +m_axis_video_tvalid_INST_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => axi_fifo_empty, + O => m_axis_video_tvalid + ); +mem1: entity work.Arty_Z7_20_v_rgb2ycrcb_0_0_dp_ram + port map ( + ADDRA(3) => mem1_n_1, + ADDRA(2) => mem1_n_2, + ADDRA(1) => mem1_n_3, + ADDRA(0) => mem1_n_4, + Q(3) => \read_ptr_int_reg_n_0_[3]\, + Q(2) => \read_ptr_int_reg_n_0_[2]\, + Q(1) => \read_ptr_int_reg_n_0_[1]\, + Q(0) => \read_ptr_int_reg_n_0_[0]\, + aclk => aclk, + aclken => aclken, + aclken_0 => aclken_0, + axi_fifo_empty => axi_fifo_empty, + da(25 downto 0) => da(25 downto 0), + \genr_control_regs[0]\(0) => \genr_control_regs[0]\(0), + m_axis_video_tready => m_axis_video_tready, + m_axis_video_tuser_sof(25 downto 0) => Q(25 downto 0), + \read_ptr_int_reg[3]\ => mem1_n_0, + wen => wen, + \write_ptr_int_reg[3]\(3) => L(1), + \write_ptr_int_reg[3]\(2) => L(2), + \write_ptr_int_reg[3]\(1) => L(3), + \write_ptr_int_reg[3]\(0) => L(4) + ); +\read_ptr_int[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => p_0_in, + I1 => \read_ptr_int_reg_n_0_[3]\, + I2 => mem1_n_0, + I3 => \read_ptr_int_reg_n_0_[2]\, + O => p_0_in0_in + ); +\read_ptr_int_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => mem1_n_4, + Q => \read_ptr_int_reg_n_0_[0]\, + R => SR(0) + ); +\read_ptr_int_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => mem1_n_3, + Q => \read_ptr_int_reg_n_0_[1]\, + R => SR(0) + ); +\read_ptr_int_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => mem1_n_2, + Q => \read_ptr_int_reg_n_0_[2]\, + R => SR(0) + ); +\read_ptr_int_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => mem1_n_1, + Q => \read_ptr_int_reg_n_0_[3]\, + R => SR(0) + ); +\read_ptr_int_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => p_0_in0_in, + Q => p_0_in, + R => SR(0) + ); +\write_ptr_int[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAAAAAAAA6" + ) + port map ( + I0 => L(4), + I1 => fifo_wr_i, + I2 => core_d_out, + I3 => \^write_ptr_int_reg[0]_0\, + I4 => eol_late_i_reg, + I5 => aclken_0, + O => \write_ptr_int[0]_i_1_n_0\ + ); +\write_ptr_int[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => L(3), + I1 => wen, + I2 => L(4), + O => \write_ptr_int[1]_i_1_n_0\ + ); +\write_ptr_int[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => L(2), + I1 => L(4), + I2 => wen, + I3 => L(3), + O => \write_ptr_int[2]_i_1_n_0\ + ); +\write_ptr_int[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAAAAAA" + ) + port map ( + I0 => L(1), + I1 => L(3), + I2 => wen, + I3 => L(4), + I4 => L(2), + O => \write_ptr_int[3]_i_1_n_0\ + ); +\write_ptr_int[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"6AAAAAAAAAAAAAAA" + ) + port map ( + I0 => p_1_in1_in, + I1 => L(2), + I2 => L(4), + I3 => wen, + I4 => L(3), + I5 => L(1), + O => p_1_in + ); +\write_ptr_int_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \write_ptr_int[0]_i_1_n_0\, + Q => L(4), + R => SR(0) + ); +\write_ptr_int_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \write_ptr_int[1]_i_1_n_0\, + Q => L(3), + R => SR(0) + ); +\write_ptr_int_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \write_ptr_int[2]_i_1_n_0\, + Q => L(2), + R => SR(0) + ); +\write_ptr_int_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \write_ptr_int[3]_i_1_n_0\, + Q => L(1), + R => SR(0) + ); +\write_ptr_int_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => p_1_in, + Q => p_1_in1_in, + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_rgb2ycrcb_0_0_axis_input_buffer is + port ( + s_axis_video_tready : out STD_LOGIC; + vid_empty : out STD_LOGIC; + empty_match_reg : out STD_LOGIC; + \col_cnt_reg[12]\ : out STD_LOGIC; + reg_update : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 25 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + master_en : in STD_LOGIC; + aclk : in STD_LOGIC; + fifo_rd_i_reg : in STD_LOGIC; + resetn_out : in STD_LOGIC; + \genr_control_regs[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + aclken : in STD_LOGIC; + s_axis_video_tvalid : in STD_LOGIC; + da : in STD_LOGIC_VECTOR ( 25 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_rgb2ycrcb_0_0_axis_input_buffer : entity is "axis_input_buffer"; +end Arty_Z7_20_v_rgb2ycrcb_0_0_axis_input_buffer; + +architecture STRUCTURE of Arty_Z7_20_v_rgb2ycrcb_0_0_axis_input_buffer is + signal U_AXIS_SYNC_FIFO_n_2 : STD_LOGIC; + signal \^s_axis_video_tready\ : STD_LOGIC; +begin + s_axis_video_tready <= \^s_axis_video_tready\; +U_AXIS_SYNC_FIFO: entity work.Arty_Z7_20_v_rgb2ycrcb_0_0_synch_fifo + port map ( + Q(25 downto 0) => Q(25 downto 0), + SR(0) => SR(0), + aclk => aclk, + aclken => aclken, + \col_cnt_reg[12]\ => \col_cnt_reg[12]\, + da(25 downto 0) => da(25 downto 0), + empty_match_reg_0 => vid_empty, + empty_match_reg_1 => empty_match_reg, + fifo_rd_i_reg => fifo_rd_i_reg, + \genr_control_regs[0]\(1 downto 0) => \genr_control_regs[0]\(1 downto 0), + reg_update => reg_update, + resetn_out => resetn_out, + s_axis_tready_int_reg => U_AXIS_SYNC_FIFO_n_2, + s_axis_video_tready => \^s_axis_video_tready\, + s_axis_video_tvalid => s_axis_video_tvalid + ); +s_axis_tready_int_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => master_en, + D => U_AXIS_SYNC_FIFO_n_2, + Q => \^s_axis_video_tready\, + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_rgb2ycrcb_0_0_axis_output_buffer is + port ( + \write_ptr_int_reg[0]\ : out STD_LOGIC; + \col_cnt_reg[12]\ : out STD_LOGIC; + \col_cnt_reg[12]_0\ : out STD_LOGIC; + \col_cnt_reg[12]_1\ : out STD_LOGIC; + m_axis_video_tvalid : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 25 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + aclk : in STD_LOGIC; + m_axis_video_tready : in STD_LOGIC; + aclken_0 : in STD_LOGIC; + \genr_control_regs[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + aclken : in STD_LOGIC; + empty_match_reg : in STD_LOGIC; + empty_match_reg_0 : in STD_LOGIC; + CO : in STD_LOGIC_VECTOR ( 0 to 0 ); + wen : in STD_LOGIC; + fifo_wr_i : in STD_LOGIC; + core_d_out : in STD_LOGIC; + eol_late_i_reg : in STD_LOGIC; + da : in STD_LOGIC_VECTOR ( 25 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_rgb2ycrcb_0_0_axis_output_buffer : entity is "axis_output_buffer"; +end Arty_Z7_20_v_rgb2ycrcb_0_0_axis_output_buffer; + +architecture STRUCTURE of Arty_Z7_20_v_rgb2ycrcb_0_0_axis_output_buffer is +begin +UOSD_AXIS_SYNC_FIFO: entity work.Arty_Z7_20_v_rgb2ycrcb_0_0_synch_fifo_fallthru + port map ( + CO(0) => CO(0), + Q(25 downto 0) => Q(25 downto 0), + SR(0) => SR(0), + aclk => aclk, + aclken => aclken, + aclken_0 => aclken_0, + \col_cnt_reg[12]\ => \col_cnt_reg[12]\, + \col_cnt_reg[12]_0\ => \col_cnt_reg[12]_0\, + \col_cnt_reg[12]_1\ => \col_cnt_reg[12]_1\, + core_d_out => core_d_out, + da(25 downto 0) => da(25 downto 0), + empty_match_reg => empty_match_reg, + empty_match_reg_0 => empty_match_reg_0, + eol_late_i_reg => eol_late_i_reg, + fifo_wr_i => fifo_wr_i, + \genr_control_regs[0]\(0) => \genr_control_regs[0]\(0), + m_axis_video_tready => m_axis_video_tready, + m_axis_video_tvalid => m_axis_video_tvalid, + wen => wen, + \write_ptr_int_reg[0]_0\ => \write_ptr_int_reg[0]\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr is + port ( + s : out STD_LOGIC_VECTOR ( 8 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 14 downto 0 ); + sclr : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + aclk : in STD_LOGIC; + p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr : entity is "radd_sub_sclr"; +end Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr; + +architecture STRUCTURE of Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr is +begin +\use_fabric.adder\: entity work.Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no_5 + port map ( + E(0) => E(0), + Q(14 downto 0) => Q(14 downto 0), + aclk => aclk, + p_0_in(0) => p_0_in(0), + s(8 downto 0) => s(8 downto 0), + sclr => sclr + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_4 is + port ( + s : out STD_LOGIC_VECTOR ( 8 downto 0 ); + p_0_in : out STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 15 downto 0 ); + sclr : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_4 : entity is "radd_sub_sclr"; +end Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_4; + +architecture STRUCTURE of Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_4 is +begin +\use_fabric.adder\: entity work.Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no + port map ( + E(0) => E(0), + Q(15 downto 0) => Q(15 downto 0), + aclk => aclk, + p_0_in(0) => p_0_in(0), + s(8 downto 0) => s(8 downto 0), + sclr => sclr + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr__parameterized0\ is + port ( + S : out STD_LOGIC_VECTOR ( 0 to 0 ); + \^s\ : out STD_LOGIC_VECTOR ( 8 downto 0 ); + a : out STD_LOGIC_VECTOR ( 0 to 0 ); + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \needs_delay.shift_register_reg[1][10]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \needs_delay.shift_register_reg[1][3]\ : out STD_LOGIC; + DI : out STD_LOGIC_VECTOR ( 0 to 0 ); + \core_control_regs[6]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + p : in STD_LOGIC_VECTOR ( 8 downto 0 ); + CO : in STD_LOGIC_VECTOR ( 0 to 0 ); + \needs_delay.shift_register_reg[5][7]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + sclr : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + aclk : in STD_LOGIC; + y_intb : in STD_LOGIC_VECTOR ( 7 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr__parameterized0\ : entity is "radd_sub_sclr"; +end \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr__parameterized0\ is +begin +\use_fabric.adder\: entity work.\Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no__parameterized0\ + port map ( + CO(0) => CO(0), + D(2 downto 0) => D(2 downto 0), + DI(0) => DI(0), + E(0) => E(0), + S(0) => S(0), + a(0) => a(0), + aclk => aclk, + \core_control_regs[6]\(0) => \core_control_regs[6]\(0), + \needs_delay.shift_register_reg[1][10]\(2 downto 0) => \needs_delay.shift_register_reg[1][10]\(2 downto 0), + \needs_delay.shift_register_reg[1][3]\ => \needs_delay.shift_register_reg[1][3]\, + \needs_delay.shift_register_reg[5][7]\(0) => \needs_delay.shift_register_reg[5][7]\(0), + p(8 downto 0) => p(8 downto 0), + \^s\(8 downto 0) => \^s\(8 downto 0), + sclr => sclr, + y_intb(7 downto 0) => y_intb(7 downto 0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr__parameterized1\ is + port ( + \out\ : out STD_LOGIC_VECTOR ( 10 downto 0 ); + sclr : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + D : in STD_LOGIC_VECTOR ( 10 downto 0 ); + aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr__parameterized1\ : entity is "radd_sub_sclr"; +end \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr__parameterized1\; + +architecture STRUCTURE of \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr__parameterized1\ is +begin +\use_fabric.adder\: entity work.\Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no__parameterized1\ + port map ( + D(10 downto 0) => D(10 downto 0), + E(0) => E(0), + aclk => aclk, + \out\(10 downto 0) => \out\(10 downto 0), + sclr => sclr + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr__parameterized2\ is + port ( + \out\ : out STD_LOGIC_VECTOR ( 10 downto 0 ); + sclr : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + D : in STD_LOGIC_VECTOR ( 10 downto 0 ); + aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr__parameterized2\ : entity is "radd_sub_sclr"; +end \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr__parameterized2\; + +architecture STRUCTURE of \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr__parameterized2\ is +begin +\use_fabric.adder\: entity work.\Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no__parameterized2\ + port map ( + D(10 downto 0) => D(10 downto 0), + E(0) => E(0), + aclk => aclk, + \out\(10 downto 0) => \out\(10 downto 0), + sclr => sclr + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr__parameterized3\ is + port ( + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + \^s\ : out STD_LOGIC_VECTOR ( 9 downto 0 ); + resetn_out : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + aclk : in STD_LOGIC; + \core_control_regs[6]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \needs_delay.shift_register_reg[1][8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + a : in STD_LOGIC_VECTOR ( 0 to 0 ); + DI : in STD_LOGIC_VECTOR ( 0 to 0 ); + S : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr__parameterized3\ : entity is "radd_sub_sclr"; +end \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr__parameterized3\; + +architecture STRUCTURE of \Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr__parameterized3\ is +begin +\use_fabric.adder\: entity work.\Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_no__parameterized3\ + port map ( + DI(0) => DI(0), + E(0) => E(0), + S(0) => S(0), + a(0) => a(0), + aclk => aclk, + \core_control_regs[6]\(8 downto 0) => \core_control_regs[6]\(8 downto 0), + \needs_delay.shift_register_reg[1][8]\(8 downto 0) => \needs_delay.shift_register_reg[1][8]\(8 downto 0), + resetn_out => resetn_out, + \^s\(9 downto 0) => \^s\(9 downto 0), + sclr => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_rgb2ycrcb_0_0_round is + port ( + sclr : out STD_LOGIC; + \^s\ : out STD_LOGIC_VECTOR ( 9 downto 0 ); + resetn_out : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + aclk : in STD_LOGIC; + \core_control_regs[6]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \needs_delay.shift_register_reg[1][8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + a : in STD_LOGIC_VECTOR ( 0 to 0 ); + DI : in STD_LOGIC_VECTOR ( 0 to 0 ); + S : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_rgb2ycrcb_0_0_round : entity is "round"; +end Arty_Z7_20_v_rgb2ycrcb_0_0_round; + +architecture STRUCTURE of Arty_Z7_20_v_rgb2ycrcb_0_0_round is +begin +adder: entity work.\Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr__parameterized3\ + port map ( + DI(0) => DI(0), + E(0) => E(0), + S(0) => S(0), + SR(0) => sclr, + a(0) => a(0), + aclk => aclk, + \core_control_regs[6]\(8 downto 0) => \core_control_regs[6]\(8 downto 0), + \needs_delay.shift_register_reg[1][8]\(8 downto 0) => \needs_delay.shift_register_reg[1][8]\(8 downto 0), + resetn_out => resetn_out, + \^s\(9 downto 0) => \^s\(9 downto 0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_rgb2ycrcb_0_0_rgb2ycrcb_core is + port ( + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + da : out STD_LOGIC_VECTOR ( 23 downto 0 ); + \core_control_regs[10]\ : in STD_LOGIC_VECTOR ( 16 downto 0 ); + aclk : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + \core_control_regs[12]\ : in STD_LOGIC_VECTOR ( 16 downto 0 ); + \core_control_regs[7]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \core_control_regs[11]\ : in STD_LOGIC_VECTOR ( 16 downto 0 ); + \core_control_regs[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \core_control_regs[9]\ : in STD_LOGIC_VECTOR ( 16 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 23 downto 0 ); + \core_control_regs[6]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + resetn_out : in STD_LOGIC; + \core_control_regs[0]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \core_control_regs[1]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \core_control_regs[2]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \core_control_regs[3]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \core_control_regs[4]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \core_control_regs[5]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_rgb2ycrcb_0_0_rgb2ycrcb_core : entity is "rgb2ycrcb_core"; +end Arty_Z7_20_v_rgb2ycrcb_0_0_rgb2ycrcb_core; + +architecture STRUCTURE of Arty_Z7_20_v_rgb2ycrcb_0_0_rgb2ycrcb_core is + signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal add_aRG_bBG_G_n_0 : STD_LOGIC; + signal add_aRG_bBG_G_n_10 : STD_LOGIC; + signal add_aRG_bBG_G_n_11 : STD_LOGIC; + signal add_aRG_bBG_G_n_12 : STD_LOGIC; + signal add_aRG_bBG_G_n_13 : STD_LOGIC; + signal add_aRG_bBG_G_n_14 : STD_LOGIC; + signal add_aRG_bBG_G_n_15 : STD_LOGIC; + signal add_aRG_bBG_G_n_16 : STD_LOGIC; + signal add_aRG_bBG_G_n_17 : STD_LOGIC; + signal add_aRG_bBG_G_n_18 : STD_LOGIC; + signal bg : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal by : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal \clip.max_Cb_n_0\ : STD_LOGIC; + signal \clip.max_Cb_n_1\ : STD_LOGIC; + signal \clip.max_Cb_n_10\ : STD_LOGIC; + signal \clip.max_Cb_n_11\ : STD_LOGIC; + signal \clip.max_Cb_n_12\ : STD_LOGIC; + signal \clip.max_Cb_n_13\ : STD_LOGIC; + signal \clip.max_Cb_n_14\ : STD_LOGIC; + signal \clip.max_Cb_n_15\ : STD_LOGIC; + signal \clip.max_Cb_n_16\ : STD_LOGIC; + signal \clip.max_Cb_n_17\ : STD_LOGIC; + signal \clip.max_Cb_n_2\ : STD_LOGIC; + signal \clip.max_Cb_n_3\ : STD_LOGIC; + signal \clip.max_Cb_n_4\ : STD_LOGIC; + signal \clip.max_Cb_n_5\ : STD_LOGIC; + signal \clip.max_Cb_n_6\ : STD_LOGIC; + signal \clip.max_Cb_n_7\ : STD_LOGIC; + signal \clip.max_Cb_n_8\ : STD_LOGIC; + signal \clip.max_Cb_n_9\ : STD_LOGIC; + signal \clip.max_Cr_n_0\ : STD_LOGIC; + signal \clip.max_Cr_n_1\ : STD_LOGIC; + signal \clip.max_Cr_n_10\ : STD_LOGIC; + signal \clip.max_Cr_n_11\ : STD_LOGIC; + signal \clip.max_Cr_n_12\ : STD_LOGIC; + signal \clip.max_Cr_n_13\ : STD_LOGIC; + signal \clip.max_Cr_n_14\ : STD_LOGIC; + signal \clip.max_Cr_n_15\ : STD_LOGIC; + signal \clip.max_Cr_n_16\ : STD_LOGIC; + signal \clip.max_Cr_n_17\ : STD_LOGIC; + signal \clip.max_Cr_n_2\ : STD_LOGIC; + signal \clip.max_Cr_n_3\ : STD_LOGIC; + signal \clip.max_Cr_n_4\ : STD_LOGIC; + signal \clip.max_Cr_n_5\ : STD_LOGIC; + signal \clip.max_Cr_n_6\ : STD_LOGIC; + signal \clip.max_Cr_n_7\ : STD_LOGIC; + signal \clip.max_Cr_n_8\ : STD_LOGIC; + signal \clip.max_Cr_n_9\ : STD_LOGIC; + signal \clip.max_Y_n_0\ : STD_LOGIC; + signal \clip.max_Y_n_1\ : STD_LOGIC; + signal \clip.max_Y_n_10\ : STD_LOGIC; + signal \clip.max_Y_n_11\ : STD_LOGIC; + signal \clip.max_Y_n_12\ : STD_LOGIC; + signal \clip.max_Y_n_13\ : STD_LOGIC; + signal \clip.max_Y_n_14\ : STD_LOGIC; + signal \clip.max_Y_n_15\ : STD_LOGIC; + signal \clip.max_Y_n_16\ : STD_LOGIC; + signal \clip.max_Y_n_17\ : STD_LOGIC; + signal \clip.max_Y_n_2\ : STD_LOGIC; + signal \clip.max_Y_n_3\ : STD_LOGIC; + signal \clip.max_Y_n_4\ : STD_LOGIC; + signal \clip.max_Y_n_5\ : STD_LOGIC; + signal \clip.max_Y_n_6\ : STD_LOGIC; + signal \clip.max_Y_n_7\ : STD_LOGIC; + signal \clip.max_Y_n_8\ : STD_LOGIC; + signal \clip.max_Y_n_9\ : STD_LOGIC; + signal del_B_n_0 : STD_LOGIC; + signal del_B_n_1 : STD_LOGIC; + signal del_B_n_2 : STD_LOGIC; + signal del_B_n_3 : STD_LOGIC; + signal del_B_n_4 : STD_LOGIC; + signal del_B_n_5 : STD_LOGIC; + signal del_B_n_6 : STD_LOGIC; + signal del_B_n_7 : STD_LOGIC; + signal del_B_n_8 : STD_LOGIC; + signal del_R_n_0 : STD_LOGIC; + signal del_R_n_1 : STD_LOGIC; + signal del_R_n_2 : STD_LOGIC; + signal del_R_n_3 : STD_LOGIC; + signal del_R_n_4 : STD_LOGIC; + signal del_R_n_5 : STD_LOGIC; + signal del_R_n_6 : STD_LOGIC; + signal del_R_n_7 : STD_LOGIC; + signal del_R_n_8 : STD_LOGIC; + signal del_Y_n_0 : STD_LOGIC; + signal del_Y_n_1 : STD_LOGIC; + signal del_Y_n_10 : STD_LOGIC; + signal del_Y_n_11 : STD_LOGIC; + signal del_Y_n_12 : STD_LOGIC; + signal del_Y_n_13 : STD_LOGIC; + signal del_Y_n_14 : STD_LOGIC; + signal del_Y_n_15 : STD_LOGIC; + signal del_Y_n_16 : STD_LOGIC; + signal del_Y_n_17 : STD_LOGIC; + signal del_Y_n_18 : STD_LOGIC; + signal del_Y_n_19 : STD_LOGIC; + signal del_Y_n_2 : STD_LOGIC; + signal del_Y_n_3 : STD_LOGIC; + signal del_Y_n_4 : STD_LOGIC; + signal del_Y_n_5 : STD_LOGIC; + signal del_Y_n_6 : STD_LOGIC; + signal del_Y_n_7 : STD_LOGIC; + signal del_Y_n_8 : STD_LOGIC; + signal del_Y_n_9 : STD_LOGIC; + signal rg : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal rgm : STD_LOGIC_VECTOR ( 25 downto 0 ); + signal ry : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal \use_fabric.adder/p_0_in\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \v4_mac23.mac_cBY_n_10\ : STD_LOGIC; + signal \v4_mac23.mac_cBY_n_11\ : STD_LOGIC; + signal \v4_mac23.mac_cBY_n_2\ : STD_LOGIC; + signal \v4_mac23.mac_cBY_n_3\ : STD_LOGIC; + signal \v4_mac23.mac_cBY_n_4\ : STD_LOGIC; + signal \v4_mac23.mac_cBY_n_5\ : STD_LOGIC; + signal \v4_mac23.mac_cBY_n_6\ : STD_LOGIC; + signal \v4_mac23.mac_cBY_n_7\ : STD_LOGIC; + signal \v4_mac23.mac_cBY_n_8\ : STD_LOGIC; + signal \v4_mac23.mac_cBY_n_9\ : STD_LOGIC; + signal \v4_mac23.mac_cRY_n_10\ : STD_LOGIC; + signal \v4_mac23.mac_cRY_n_11\ : STD_LOGIC; + signal \v4_mac23.mac_cRY_n_2\ : STD_LOGIC; + signal \v4_mac23.mac_cRY_n_3\ : STD_LOGIC; + signal \v4_mac23.mac_cRY_n_4\ : STD_LOGIC; + signal \v4_mac23.mac_cRY_n_5\ : STD_LOGIC; + signal \v4_mac23.mac_cRY_n_6\ : STD_LOGIC; + signal \v4_mac23.mac_cRY_n_7\ : STD_LOGIC; + signal \v4_mac23.mac_cRY_n_8\ : STD_LOGIC; + signal \v4_mac23.mac_cRY_n_9\ : STD_LOGIC; + signal y_int : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal y_int_round : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal y_inta_raw : STD_LOGIC_VECTOR ( 24 downto 16 ); + signal y_intb : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \NLW_v4_mac1.mult_aCr_p_UNCONNECTED\ : STD_LOGIC_VECTOR ( 25 downto 0 ); + signal \NLW_v4_mac23.mac_cBY_p_UNCONNECTED\ : STD_LOGIC_VECTOR ( 11 downto 10 ); + signal \NLW_v4_mac23.mac_cRY_p_UNCONNECTED\ : STD_LOGIC_VECTOR ( 11 downto 10 ); + attribute CREG : integer; + attribute CREG of \v4_mac1.mult_aCr\ : label is 0; + attribute HAS_C : integer; + attribute HAS_C of \v4_mac1.mult_aCr\ : label is 1; + attribute IWIDTHA : integer; + attribute IWIDTHA of \v4_mac1.mult_aCr\ : label is 9; + attribute IWIDTHB : integer; + attribute IWIDTHB of \v4_mac1.mult_aCr\ : label is 17; + attribute OWIDTH : integer; + attribute OWIDTH of \v4_mac1.mult_aCr\ : label is 26; + attribute ROUND_MODE : integer; + attribute ROUND_MODE of \v4_mac1.mult_aCr\ : label is 0; + attribute USE_DSP48 : string; + attribute USE_DSP48 of \v4_mac1.mult_aCr\ : label is "yes"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of \v4_mac1.mult_aCr\ : label is "yes"; + attribute mult_style : string; + attribute mult_style of \v4_mac1.mult_aCr\ : label is "pipe_block"; + attribute register_balancing : string; + attribute register_balancing of \v4_mac1.mult_aCr\ : label is "yes"; + attribute CREG of \v4_mac23.mac_cBY\ : label is 0; + attribute HAS_C of \v4_mac23.mac_cBY\ : label is 1; + attribute IWIDTHA of \v4_mac23.mac_cBY\ : label is 11; + attribute IWIDTHB of \v4_mac23.mac_cBY\ : label is 17; + attribute OWIDTH of \v4_mac23.mac_cBY\ : label is 12; + attribute ROUND_MODE of \v4_mac23.mac_cBY\ : label is 0; + attribute USE_DSP48 of \v4_mac23.mac_cBY\ : label is "yes"; + attribute downgradeipidentifiedwarnings of \v4_mac23.mac_cBY\ : label is "yes"; + attribute mult_style of \v4_mac23.mac_cBY\ : label is "pipe_block"; + attribute register_balancing of \v4_mac23.mac_cBY\ : label is "yes"; + attribute CREG of \v4_mac23.mac_cRY\ : label is 0; + attribute HAS_C of \v4_mac23.mac_cRY\ : label is 1; + attribute IWIDTHA of \v4_mac23.mac_cRY\ : label is 11; + attribute IWIDTHB of \v4_mac23.mac_cRY\ : label is 17; + attribute OWIDTH of \v4_mac23.mac_cRY\ : label is 12; + attribute ROUND_MODE of \v4_mac23.mac_cRY\ : label is 0; + attribute USE_DSP48 of \v4_mac23.mac_cRY\ : label is "yes"; + attribute downgradeipidentifiedwarnings of \v4_mac23.mac_cRY\ : label is "yes"; + attribute mult_style of \v4_mac23.mac_cRY\ : label is "pipe_block"; + attribute register_balancing of \v4_mac23.mac_cRY\ : label is "yes"; +begin + SR(0) <= \^sr\(0); +add_aRG_bBG_G: entity work.\Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr__parameterized0\ + port map ( + CO(0) => del_B_n_8, + D(2) => add_aRG_bBG_G_n_11, + D(1) => add_aRG_bBG_G_n_12, + D(0) => add_aRG_bBG_G_n_13, + DI(0) => add_aRG_bBG_G_n_18, + E(0) => E(0), + S(0) => add_aRG_bBG_G_n_0, + a(0) => add_aRG_bBG_G_n_10, + aclk => aclk, + \core_control_regs[6]\(0) => \core_control_regs[6]\(8), + \needs_delay.shift_register_reg[1][10]\(2) => add_aRG_bBG_G_n_14, + \needs_delay.shift_register_reg[1][10]\(1) => add_aRG_bBG_G_n_15, + \needs_delay.shift_register_reg[1][10]\(0) => add_aRG_bBG_G_n_16, + \needs_delay.shift_register_reg[1][3]\ => add_aRG_bBG_G_n_17, + \needs_delay.shift_register_reg[5][7]\(0) => del_R_n_8, + p(8 downto 0) => y_inta_raw(24 downto 16), + \^s\(8 downto 0) => y_int(8 downto 0), + sclr => \^sr\(0), + y_intb(7 downto 0) => y_intb(7 downto 0) + ); +\clamp.min_Cb\: entity work.Arty_Z7_20_v_rgb2ycrcb_0_0_min_sat + port map ( + DI(3) => \clip.max_Cb_n_14\, + DI(2) => \clip.max_Cb_n_15\, + DI(1) => \clip.max_Cb_n_16\, + DI(0) => \clip.max_Cb_n_17\, + E(0) => E(0), + Q(8) => \clip.max_Cb_n_1\, + Q(7) => \clip.max_Cb_n_2\, + Q(6) => \clip.max_Cb_n_3\, + Q(5) => \clip.max_Cb_n_4\, + Q(4) => \clip.max_Cb_n_5\, + Q(3) => \clip.max_Cb_n_6\, + Q(2) => \clip.max_Cb_n_7\, + Q(1) => \clip.max_Cb_n_8\, + Q(0) => \clip.max_Cb_n_9\, + S(3) => \clip.max_Cb_n_10\, + S(2) => \clip.max_Cb_n_11\, + S(1) => \clip.max_Cb_n_12\, + S(0) => \clip.max_Cb_n_13\, + aclk => aclk, + \core_control_regs[3]\(7 downto 0) => \core_control_regs[3]\(7 downto 0), + da(7 downto 0) => da(15 downto 8), + \needs_delay.shift_register_reg[1][8]\(0) => \clip.max_Cb_n_0\, + sclr => \^sr\(0) + ); +\clamp.min_Cr\: entity work.Arty_Z7_20_v_rgb2ycrcb_0_0_min_sat_0 + port map ( + DI(3) => \clip.max_Cr_n_14\, + DI(2) => \clip.max_Cr_n_15\, + DI(1) => \clip.max_Cr_n_16\, + DI(0) => \clip.max_Cr_n_17\, + E(0) => E(0), + Q(8) => \clip.max_Cr_n_1\, + Q(7) => \clip.max_Cr_n_2\, + Q(6) => \clip.max_Cr_n_3\, + Q(5) => \clip.max_Cr_n_4\, + Q(4) => \clip.max_Cr_n_5\, + Q(3) => \clip.max_Cr_n_6\, + Q(2) => \clip.max_Cr_n_7\, + Q(1) => \clip.max_Cr_n_8\, + Q(0) => \clip.max_Cr_n_9\, + S(3) => \clip.max_Cr_n_10\, + S(2) => \clip.max_Cr_n_11\, + S(1) => \clip.max_Cr_n_12\, + S(0) => \clip.max_Cr_n_13\, + aclk => aclk, + \core_control_regs[5]\(7 downto 0) => \core_control_regs[5]\(7 downto 0), + da(7 downto 0) => da(23 downto 16), + \needs_delay.shift_register_reg[1][8]\(0) => \clip.max_Cr_n_0\, + sclr => \^sr\(0) + ); +\clamp.min_Y\: entity work.Arty_Z7_20_v_rgb2ycrcb_0_0_min_sat_1 + port map ( + DI(3) => \clip.max_Y_n_14\, + DI(2) => \clip.max_Y_n_15\, + DI(1) => \clip.max_Y_n_16\, + DI(0) => \clip.max_Y_n_17\, + E(0) => E(0), + Q(8) => \clip.max_Y_n_1\, + Q(7) => \clip.max_Y_n_2\, + Q(6) => \clip.max_Y_n_3\, + Q(5) => \clip.max_Y_n_4\, + Q(4) => \clip.max_Y_n_5\, + Q(3) => \clip.max_Y_n_6\, + Q(2) => \clip.max_Y_n_7\, + Q(1) => \clip.max_Y_n_8\, + Q(0) => \clip.max_Y_n_9\, + S(3) => \clip.max_Y_n_10\, + S(2) => \clip.max_Y_n_11\, + S(1) => \clip.max_Y_n_12\, + S(0) => \clip.max_Y_n_13\, + aclk => aclk, + \core_control_regs[1]\(7 downto 0) => \core_control_regs[1]\(7 downto 0), + da(7 downto 0) => da(7 downto 0), + \needs_delay.shift_register_reg[1][8]\(0) => \clip.max_Y_n_0\, + sclr => \^sr\(0) + ); +\clip.max_Cb\: entity work.Arty_Z7_20_v_rgb2ycrcb_0_0_max_sat + port map ( + DI(3) => \clip.max_Cb_n_14\, + DI(2) => \clip.max_Cb_n_15\, + DI(1) => \clip.max_Cb_n_16\, + DI(0) => \clip.max_Cb_n_17\, + E(0) => E(0), + Q(8) => \clip.max_Cb_n_1\, + Q(7) => \clip.max_Cb_n_2\, + Q(6) => \clip.max_Cb_n_3\, + Q(5) => \clip.max_Cb_n_4\, + Q(4) => \clip.max_Cb_n_5\, + Q(3) => \clip.max_Cb_n_6\, + Q(2) => \clip.max_Cb_n_7\, + Q(1) => \clip.max_Cb_n_8\, + Q(0) => \clip.max_Cb_n_9\, + S(3) => \clip.max_Cb_n_10\, + S(2) => \clip.max_Cb_n_11\, + S(1) => \clip.max_Cb_n_12\, + S(0) => \clip.max_Cb_n_13\, + aclk => aclk, + \core_control_regs[2]\(7 downto 0) => \core_control_regs[2]\(7 downto 0), + \core_control_regs[3]\(7 downto 0) => \core_control_regs[3]\(7 downto 0), + \needs_delay.shift_register_reg[1][7]\(0) => \clip.max_Cb_n_0\, + p(9) => \v4_mac23.mac_cBY_n_2\, + p(8) => \v4_mac23.mac_cBY_n_3\, + p(7) => \v4_mac23.mac_cBY_n_4\, + p(6) => \v4_mac23.mac_cBY_n_5\, + p(5) => \v4_mac23.mac_cBY_n_6\, + p(4) => \v4_mac23.mac_cBY_n_7\, + p(3) => \v4_mac23.mac_cBY_n_8\, + p(2) => \v4_mac23.mac_cBY_n_9\, + p(1) => \v4_mac23.mac_cBY_n_10\, + p(0) => \v4_mac23.mac_cBY_n_11\, + sclr => \^sr\(0) + ); +\clip.max_Cr\: entity work.Arty_Z7_20_v_rgb2ycrcb_0_0_max_sat_2 + port map ( + DI(3) => \clip.max_Cr_n_14\, + DI(2) => \clip.max_Cr_n_15\, + DI(1) => \clip.max_Cr_n_16\, + DI(0) => \clip.max_Cr_n_17\, + E(0) => E(0), + Q(8) => \clip.max_Cr_n_1\, + Q(7) => \clip.max_Cr_n_2\, + Q(6) => \clip.max_Cr_n_3\, + Q(5) => \clip.max_Cr_n_4\, + Q(4) => \clip.max_Cr_n_5\, + Q(3) => \clip.max_Cr_n_6\, + Q(2) => \clip.max_Cr_n_7\, + Q(1) => \clip.max_Cr_n_8\, + Q(0) => \clip.max_Cr_n_9\, + S(3) => \clip.max_Cr_n_10\, + S(2) => \clip.max_Cr_n_11\, + S(1) => \clip.max_Cr_n_12\, + S(0) => \clip.max_Cr_n_13\, + aclk => aclk, + \core_control_regs[4]\(7 downto 0) => \core_control_regs[4]\(7 downto 0), + \core_control_regs[5]\(7 downto 0) => \core_control_regs[5]\(7 downto 0), + \needs_delay.shift_register_reg[1][7]\(0) => \clip.max_Cr_n_0\, + p(9) => \v4_mac23.mac_cRY_n_2\, + p(8) => \v4_mac23.mac_cRY_n_3\, + p(7) => \v4_mac23.mac_cRY_n_4\, + p(6) => \v4_mac23.mac_cRY_n_5\, + p(5) => \v4_mac23.mac_cRY_n_6\, + p(4) => \v4_mac23.mac_cRY_n_7\, + p(3) => \v4_mac23.mac_cRY_n_8\, + p(2) => \v4_mac23.mac_cRY_n_9\, + p(1) => \v4_mac23.mac_cRY_n_10\, + p(0) => \v4_mac23.mac_cRY_n_11\, + sclr => \^sr\(0) + ); +\clip.max_Y\: entity work.Arty_Z7_20_v_rgb2ycrcb_0_0_max_sat_3 + port map ( + DI(3) => del_Y_n_16, + DI(2) => del_Y_n_17, + DI(1) => del_Y_n_18, + DI(0) => del_Y_n_19, + E(0) => E(0), + Q(8) => \clip.max_Y_n_1\, + Q(7) => \clip.max_Y_n_2\, + Q(6) => \clip.max_Y_n_3\, + Q(5) => \clip.max_Y_n_4\, + Q(4) => \clip.max_Y_n_5\, + Q(3) => \clip.max_Y_n_6\, + Q(2) => \clip.max_Y_n_7\, + Q(1) => \clip.max_Y_n_8\, + Q(0) => \clip.max_Y_n_9\, + S(3) => del_Y_n_12, + S(2) => del_Y_n_13, + S(1) => del_Y_n_14, + S(0) => del_Y_n_15, + aclk => aclk, + \core_control_regs[0]\(7 downto 0) => \core_control_regs[0]\(7 downto 0), + \core_control_regs[1]\(7 downto 0) => \core_control_regs[1]\(7 downto 0), + \needs_delay.shift_register_reg[1][7]\(0) => \clip.max_Y_n_0\, + \needs_delay.shift_register_reg[1][7]_0\(3) => \clip.max_Y_n_10\, + \needs_delay.shift_register_reg[1][7]_0\(2) => \clip.max_Y_n_11\, + \needs_delay.shift_register_reg[1][7]_0\(1) => \clip.max_Y_n_12\, + \needs_delay.shift_register_reg[1][7]_0\(0) => \clip.max_Y_n_13\, + \needs_delay.shift_register_reg[1][7]_1\(3) => \clip.max_Y_n_14\, + \needs_delay.shift_register_reg[1][7]_1\(2) => \clip.max_Y_n_15\, + \needs_delay.shift_register_reg[1][7]_1\(1) => \clip.max_Y_n_16\, + \needs_delay.shift_register_reg[1][7]_1\(0) => \clip.max_Y_n_17\, + \needs_delay.shift_register_reg[3][0]\ => del_Y_n_9, + \needs_delay.shift_register_reg[3][1]\ => del_Y_n_8, + \needs_delay.shift_register_reg[3][2]\ => del_Y_n_7, + \needs_delay.shift_register_reg[3][3]\ => del_Y_n_6, + \needs_delay.shift_register_reg[3][4]\ => del_Y_n_5, + \needs_delay.shift_register_reg[3][5]\ => del_Y_n_4, + \needs_delay.shift_register_reg[3][6]\ => del_Y_n_3, + \needs_delay.shift_register_reg[3][7]\ => del_Y_n_2, + \needs_delay.shift_register_reg[3][8]\(0) => del_Y_n_10, + \needs_delay.shift_register_reg[3][8]_0\(0) => del_Y_n_11, + \needs_delay.shift_register_reg[3][8]_1\ => del_Y_n_1, + \needs_delay.shift_register_reg[3][9]\ => del_Y_n_0, + sclr => \^sr\(0) + ); +del_B: entity work.\Arty_Z7_20_v_rgb2ycrcb_0_0_delay__parameterized0\ + port map ( + CO(0) => del_B_n_8, + D(7) => del_B_n_0, + D(6) => del_B_n_1, + D(5) => del_B_n_2, + D(4) => del_B_n_3, + D(3) => del_B_n_4, + D(2) => del_B_n_5, + D(1) => del_B_n_6, + D(0) => del_B_n_7, + E(0) => E(0), + Q(7 downto 0) => Q(15 downto 8), + aclk => aclk, + \needs_delay.shift_register_reg[1][0]\ => add_aRG_bBG_G_n_17, + s(6 downto 0) => y_int(7 downto 1) + ); +del_G: entity work.Arty_Z7_20_v_rgb2ycrcb_0_0_delay + port map ( + E(0) => E(0), + Q(7 downto 0) => Q(7 downto 0), + aclk => aclk, + y_intb(7 downto 0) => y_intb(7 downto 0) + ); +del_R: entity work.\Arty_Z7_20_v_rgb2ycrcb_0_0_delay__parameterized1\ + port map ( + D(7) => del_R_n_0, + D(6) => del_R_n_1, + D(5) => del_R_n_2, + D(4) => del_R_n_3, + D(3) => del_R_n_4, + D(2) => del_R_n_5, + D(1) => del_R_n_6, + D(0) => del_R_n_7, + E(0) => E(0), + Q(7 downto 0) => Q(23 downto 16), + aclk => aclk, + \needs_delay.shift_register_reg[1][0]\ => add_aRG_bBG_G_n_17, + \needs_delay.shift_register_reg[1][10]\(0) => del_R_n_8, + s(6 downto 0) => y_int(7 downto 1) + ); +del_Y: entity work.\Arty_Z7_20_v_rgb2ycrcb_0_0_delay__parameterized2\ + port map ( + DI(3) => del_Y_n_16, + DI(2) => del_Y_n_17, + DI(1) => del_Y_n_18, + DI(0) => del_Y_n_19, + E(0) => E(0), + S(3) => del_Y_n_12, + S(2) => del_Y_n_13, + S(1) => del_Y_n_14, + S(0) => del_Y_n_15, + aclk => aclk, + \core_control_regs[0]\(7 downto 0) => \core_control_regs[0]\(7 downto 0), + \needs_delay.shift_register_reg[1][0]\ => del_Y_n_9, + \needs_delay.shift_register_reg[1][1]\ => del_Y_n_8, + \needs_delay.shift_register_reg[1][2]\ => del_Y_n_7, + \needs_delay.shift_register_reg[1][3]\ => del_Y_n_6, + \needs_delay.shift_register_reg[1][4]\ => del_Y_n_5, + \needs_delay.shift_register_reg[1][5]\ => del_Y_n_4, + \needs_delay.shift_register_reg[1][6]\ => del_Y_n_3, + \needs_delay.shift_register_reg[1][7]\ => del_Y_n_2, + \needs_delay.shift_register_reg[1][8]\ => del_Y_n_1, + \needs_delay.shift_register_reg[1][9]\ => del_Y_n_0, + \needs_delay.shift_register_reg[1][9]_0\(0) => del_Y_n_10, + \needs_delay.shift_register_reg[1][9]_1\(0) => del_Y_n_11, + \^s\(9 downto 0) => y_int_round(9 downto 0) + ); +mult_aRG: entity work.Arty_Z7_20_v_rgb2ycrcb_0_0_mult + port map ( + E(0) => E(0), + aclk => aclk, + c(25 downto 0) => rgm(25 downto 0), + \core_control_regs[9]\(16 downto 0) => \core_control_regs[9]\(16 downto 0), + s(8 downto 0) => rg(8 downto 0), + sclr => \^sr\(0) + ); +sub_BG: entity work.Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr + port map ( + E(0) => E(0), + Q(14 downto 0) => Q(15 downto 1), + aclk => aclk, + p_0_in(0) => \use_fabric.adder/p_0_in\(0), + s(8 downto 0) => bg(8 downto 0), + sclr => \^sr\(0) + ); +sub_BY: entity work.\Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr__parameterized1\ + port map ( + D(10) => add_aRG_bBG_G_n_11, + D(9) => add_aRG_bBG_G_n_12, + D(8) => add_aRG_bBG_G_n_13, + D(7) => del_B_n_0, + D(6) => del_B_n_1, + D(5) => del_B_n_2, + D(4) => del_B_n_3, + D(3) => del_B_n_4, + D(2) => del_B_n_5, + D(1) => del_B_n_6, + D(0) => del_B_n_7, + E(0) => E(0), + aclk => aclk, + \out\(10 downto 0) => by(10 downto 0), + sclr => \^sr\(0) + ); +sub_RG: entity work.Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr_4 + port map ( + E(0) => E(0), + Q(15 downto 8) => Q(23 downto 16), + Q(7 downto 0) => Q(7 downto 0), + aclk => aclk, + p_0_in(0) => \use_fabric.adder/p_0_in\(0), + s(8 downto 0) => rg(8 downto 0), + sclr => \^sr\(0) + ); +sub_RY: entity work.\Arty_Z7_20_v_rgb2ycrcb_0_0_radd_sub_sclr__parameterized2\ + port map ( + D(10) => add_aRG_bBG_G_n_14, + D(9) => add_aRG_bBG_G_n_15, + D(8) => add_aRG_bBG_G_n_16, + D(7) => del_R_n_0, + D(6) => del_R_n_1, + D(5) => del_R_n_2, + D(4) => del_R_n_3, + D(3) => del_R_n_4, + D(2) => del_R_n_5, + D(1) => del_R_n_6, + D(0) => del_R_n_7, + E(0) => E(0), + aclk => aclk, + \out\(10 downto 0) => ry(10 downto 0), + sclr => \^sr\(0) + ); +\v4_mac1.mult_aCr\: entity work.Arty_Z7_20_v_rgb2ycrcb_0_0_mac + port map ( + a(8 downto 0) => bg(8 downto 0), + b(16 downto 0) => \core_control_regs[10]\(16 downto 0), + c(25 downto 0) => rgm(25 downto 0), + ce => E(0), + clk => aclk, + p(25) => \NLW_v4_mac1.mult_aCr_p_UNCONNECTED\(25), + p(24 downto 16) => y_inta_raw(24 downto 16), + p(15 downto 0) => \NLW_v4_mac1.mult_aCr_p_UNCONNECTED\(15 downto 0), + sclr => \^sr\(0) + ); +\v4_mac23.mac_cBY\: entity work.\Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized0\ + port map ( + a(10 downto 0) => by(10 downto 0), + b(16 downto 0) => \core_control_regs[12]\(16 downto 0), + c(11) => \core_control_regs[7]\(8), + c(10) => \core_control_regs[7]\(8), + c(9) => \core_control_regs[7]\(8), + c(8 downto 0) => \core_control_regs[7]\(8 downto 0), + ce => E(0), + clk => aclk, + p(11 downto 10) => \NLW_v4_mac23.mac_cBY_p_UNCONNECTED\(11 downto 10), + p(9) => \v4_mac23.mac_cBY_n_2\, + p(8) => \v4_mac23.mac_cBY_n_3\, + p(7) => \v4_mac23.mac_cBY_n_4\, + p(6) => \v4_mac23.mac_cBY_n_5\, + p(5) => \v4_mac23.mac_cBY_n_6\, + p(4) => \v4_mac23.mac_cBY_n_7\, + p(3) => \v4_mac23.mac_cBY_n_8\, + p(2) => \v4_mac23.mac_cBY_n_9\, + p(1) => \v4_mac23.mac_cBY_n_10\, + p(0) => \v4_mac23.mac_cBY_n_11\, + sclr => \^sr\(0) + ); +\v4_mac23.mac_cRY\: entity work.\Arty_Z7_20_v_rgb2ycrcb_0_0_mac__parameterized1\ + port map ( + a(10 downto 0) => ry(10 downto 0), + b(16 downto 0) => \core_control_regs[11]\(16 downto 0), + c(11) => \core_control_regs[8]\(8), + c(10) => \core_control_regs[8]\(8), + c(9) => \core_control_regs[8]\(8), + c(8 downto 0) => \core_control_regs[8]\(8 downto 0), + ce => E(0), + clk => aclk, + p(11 downto 10) => \NLW_v4_mac23.mac_cRY_p_UNCONNECTED\(11 downto 10), + p(9) => \v4_mac23.mac_cRY_n_2\, + p(8) => \v4_mac23.mac_cRY_n_3\, + p(7) => \v4_mac23.mac_cRY_n_4\, + p(6) => \v4_mac23.mac_cRY_n_5\, + p(5) => \v4_mac23.mac_cRY_n_6\, + p(4) => \v4_mac23.mac_cRY_n_7\, + p(3) => \v4_mac23.mac_cRY_n_8\, + p(2) => \v4_mac23.mac_cRY_n_9\, + p(1) => \v4_mac23.mac_cRY_n_10\, + p(0) => \v4_mac23.mac_cRY_n_11\, + sclr => \^sr\(0) + ); +\y_needs_round.round_Y\: entity work.Arty_Z7_20_v_rgb2ycrcb_0_0_round + port map ( + DI(0) => add_aRG_bBG_G_n_18, + E(0) => E(0), + S(0) => add_aRG_bBG_G_n_0, + a(0) => add_aRG_bBG_G_n_10, + aclk => aclk, + \core_control_regs[6]\(8 downto 0) => \core_control_regs[6]\(8 downto 0), + \needs_delay.shift_register_reg[1][8]\(8 downto 0) => y_int(8 downto 0), + resetn_out => resetn_out, + \^s\(9 downto 0) => y_int_round(9 downto 0), + sclr => \^sr\(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_rgb2ycrcb_0_0_rgb2ycrcb_top is + port ( + \needs_delay.shift_register_reg[1][0]\ : out STD_LOGIC; + s_axis_video_tready : out STD_LOGIC; + eol_late_i_reg : out STD_LOGIC; + sof_early_i_reg : out STD_LOGIC; + sof_early_i_reg_0 : out STD_LOGIC; + intc_if : out STD_LOGIC_VECTOR ( 4 downto 0 ); + Q : out STD_LOGIC_VECTOR ( 25 downto 0 ); + reg_update : out STD_LOGIC; + m_axis_video_tvalid : out STD_LOGIC; + \core_control_regs[10]\ : in STD_LOGIC_VECTOR ( 16 downto 0 ); + aclk : in STD_LOGIC; + \core_control_regs[12]\ : in STD_LOGIC_VECTOR ( 16 downto 0 ); + \core_control_regs[7]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \core_control_regs[11]\ : in STD_LOGIC_VECTOR ( 16 downto 0 ); + \core_control_regs[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \core_control_regs[9]\ : in STD_LOGIC_VECTOR ( 16 downto 0 ); + resetn_out : in STD_LOGIC; + \genr_control_regs[0]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + aclken : in STD_LOGIC; + m_axis_video_tready : in STD_LOGIC; + \core_control_regs[6]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \time_control_regs[0]\ : in STD_LOGIC_VECTOR ( 25 downto 0 ); + \core_control_regs[0]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \core_control_regs[1]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \core_control_regs[2]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \core_control_regs[3]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \core_control_regs[4]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \core_control_regs[5]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + da : in STD_LOGIC_VECTOR ( 25 downto 0 ); + core_d_out : in STD_LOGIC; + s_axis_video_tvalid : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_rgb2ycrcb_0_0_rgb2ycrcb_top : entity is "rgb2ycrcb_top"; +end Arty_Z7_20_v_rgb2ycrcb_0_0_rgb2ycrcb_top; + +architecture STRUCTURE of Arty_Z7_20_v_rgb2ycrcb_0_0_rgb2ycrcb_top is + signal \UOSD_AXIS_SYNC_FIFO/wen\ : STD_LOGIC; + signal axi_control_n_13 : STD_LOGIC; + signal axi_control_n_16 : STD_LOGIC; + signal axi_control_n_17 : STD_LOGIC; + signal axi_in_fifo_n_10 : STD_LOGIC; + signal axi_in_fifo_n_11 : STD_LOGIC; + signal axi_in_fifo_n_12 : STD_LOGIC; + signal axi_in_fifo_n_13 : STD_LOGIC; + signal axi_in_fifo_n_14 : STD_LOGIC; + signal axi_in_fifo_n_15 : STD_LOGIC; + signal axi_in_fifo_n_16 : STD_LOGIC; + signal axi_in_fifo_n_17 : STD_LOGIC; + signal axi_in_fifo_n_18 : STD_LOGIC; + signal axi_in_fifo_n_19 : STD_LOGIC; + signal axi_in_fifo_n_2 : STD_LOGIC; + signal axi_in_fifo_n_20 : STD_LOGIC; + signal axi_in_fifo_n_21 : STD_LOGIC; + signal axi_in_fifo_n_22 : STD_LOGIC; + signal axi_in_fifo_n_23 : STD_LOGIC; + signal axi_in_fifo_n_24 : STD_LOGIC; + signal axi_in_fifo_n_25 : STD_LOGIC; + signal axi_in_fifo_n_26 : STD_LOGIC; + signal axi_in_fifo_n_27 : STD_LOGIC; + signal axi_in_fifo_n_28 : STD_LOGIC; + signal axi_in_fifo_n_29 : STD_LOGIC; + signal axi_in_fifo_n_3 : STD_LOGIC; + signal axi_in_fifo_n_30 : STD_LOGIC; + signal axi_in_fifo_n_7 : STD_LOGIC; + signal axi_in_fifo_n_8 : STD_LOGIC; + signal axi_in_fifo_n_9 : STD_LOGIC; + signal axi_out_fifo_n_0 : STD_LOGIC; + signal axi_out_fifo_n_1 : STD_LOGIC; + signal axi_out_fifo_n_2 : STD_LOGIC; + signal axi_out_fifo_n_3 : STD_LOGIC; + signal \^eol_late_i_reg\ : STD_LOGIC; + signal fifo_wr_i : STD_LOGIC; + signal intcore_n_1 : STD_LOGIC; + signal intcore_n_10 : STD_LOGIC; + signal intcore_n_11 : STD_LOGIC; + signal intcore_n_12 : STD_LOGIC; + signal intcore_n_13 : STD_LOGIC; + signal intcore_n_14 : STD_LOGIC; + signal intcore_n_15 : STD_LOGIC; + signal intcore_n_16 : STD_LOGIC; + signal intcore_n_17 : STD_LOGIC; + signal intcore_n_18 : STD_LOGIC; + signal intcore_n_19 : STD_LOGIC; + signal intcore_n_2 : STD_LOGIC; + signal intcore_n_20 : STD_LOGIC; + signal intcore_n_21 : STD_LOGIC; + signal intcore_n_22 : STD_LOGIC; + signal intcore_n_23 : STD_LOGIC; + signal intcore_n_24 : STD_LOGIC; + signal intcore_n_3 : STD_LOGIC; + signal intcore_n_4 : STD_LOGIC; + signal intcore_n_5 : STD_LOGIC; + signal intcore_n_6 : STD_LOGIC; + signal intcore_n_7 : STD_LOGIC; + signal intcore_n_8 : STD_LOGIC; + signal intcore_n_9 : STD_LOGIC; + signal ltOp : STD_LOGIC; + signal master_en : STD_LOGIC; + signal \^needs_delay.shift_register_reg[1][0]\ : STD_LOGIC; + signal out_fifo_eol : STD_LOGIC; + signal out_fifo_sof : STD_LOGIC; + signal sclr : STD_LOGIC; + signal vid_data_in_r : STD_LOGIC_VECTOR ( 23 downto 0 ); + signal vid_empty : STD_LOGIC; + signal vid_eol_in : STD_LOGIC; + signal vid_sof_in : STD_LOGIC; +begin + eol_late_i_reg <= \^eol_late_i_reg\; + \needs_delay.shift_register_reg[1][0]\ <= \^needs_delay.shift_register_reg[1][0]\; +axi_control: entity work.Arty_Z7_20_v_rgb2ycrcb_0_0_axi4s_control + port map ( + CO(0) => ltOp, + E(0) => \^needs_delay.shift_register_reg[1][0]\, + SR(0) => sclr, + aclk => aclk, + aclken => aclken, + \col_cnt_reg[12]_0\ => axi_control_n_17, + \col_cnt_reg[1]_0\ => axi_control_n_13, + core_d_out => core_d_out, + da(1) => out_fifo_sof, + da(0) => out_fifo_eol, + empty_match_reg => axi_in_fifo_n_3, + eol_late_i_reg_0 => \^eol_late_i_reg\, + fifo_wr_i => fifo_wr_i, + full_int_reg => axi_out_fifo_n_0, + \genr_control_regs[0]\(1) => \genr_control_regs[0]\(2), + \genr_control_regs[0]\(0) => \genr_control_regs[0]\(0), + in_fifo_reset_reg_0 => axi_control_n_16, + intc_if(4 downto 0) => intc_if(4 downto 0), + master_en => master_en, + \read_ptr_int_reg[1]\ => axi_out_fifo_n_3, + resetn_out => resetn_out, + sof_early_i_reg_0 => sof_early_i_reg, + sof_early_i_reg_1 => sof_early_i_reg_0, + t_qb(1) => vid_sof_in, + t_qb(0) => vid_eol_in, + \time_control_regs[0]\(25 downto 0) => \time_control_regs[0]\(25 downto 0), + vid_empty => vid_empty, + wen => \UOSD_AXIS_SYNC_FIFO/wen\, + \word_count_reg[4]\ => axi_in_fifo_n_2, + \write_ptr_int_reg[2]\ => axi_out_fifo_n_1, + \write_ptr_int_reg[2]_0\ => axi_out_fifo_n_2 + ); +axi_in_fifo: entity work.Arty_Z7_20_v_rgb2ycrcb_0_0_axis_input_buffer + port map ( + Q(25) => vid_sof_in, + Q(24) => vid_eol_in, + Q(23) => axi_in_fifo_n_7, + Q(22) => axi_in_fifo_n_8, + Q(21) => axi_in_fifo_n_9, + Q(20) => axi_in_fifo_n_10, + Q(19) => axi_in_fifo_n_11, + Q(18) => axi_in_fifo_n_12, + Q(17) => axi_in_fifo_n_13, + Q(16) => axi_in_fifo_n_14, + Q(15) => axi_in_fifo_n_15, + Q(14) => axi_in_fifo_n_16, + Q(13) => axi_in_fifo_n_17, + Q(12) => axi_in_fifo_n_18, + Q(11) => axi_in_fifo_n_19, + Q(10) => axi_in_fifo_n_20, + Q(9) => axi_in_fifo_n_21, + Q(8) => axi_in_fifo_n_22, + Q(7) => axi_in_fifo_n_23, + Q(6) => axi_in_fifo_n_24, + Q(5) => axi_in_fifo_n_25, + Q(4) => axi_in_fifo_n_26, + Q(3) => axi_in_fifo_n_27, + Q(2) => axi_in_fifo_n_28, + Q(1) => axi_in_fifo_n_29, + Q(0) => axi_in_fifo_n_30, + SR(0) => sclr, + aclk => aclk, + aclken => aclken, + \col_cnt_reg[12]\ => axi_in_fifo_n_3, + da(25 downto 0) => da(25 downto 0), + empty_match_reg => axi_in_fifo_n_2, + fifo_rd_i_reg => axi_control_n_16, + \genr_control_regs[0]\(1 downto 0) => \genr_control_regs[0]\(1 downto 0), + master_en => master_en, + reg_update => reg_update, + resetn_out => resetn_out, + s_axis_video_tready => s_axis_video_tready, + s_axis_video_tvalid => s_axis_video_tvalid, + vid_empty => vid_empty + ); +axi_out_fifo: entity work.Arty_Z7_20_v_rgb2ycrcb_0_0_axis_output_buffer + port map ( + CO(0) => ltOp, + Q(25 downto 0) => Q(25 downto 0), + SR(0) => sclr, + aclk => aclk, + aclken => aclken, + aclken_0 => axi_control_n_13, + \col_cnt_reg[12]\ => axi_out_fifo_n_1, + \col_cnt_reg[12]_0\ => axi_out_fifo_n_2, + \col_cnt_reg[12]_1\ => axi_out_fifo_n_3, + core_d_out => core_d_out, + da(25) => out_fifo_sof, + da(24) => out_fifo_eol, + da(23) => intcore_n_1, + da(22) => intcore_n_2, + da(21) => intcore_n_3, + da(20) => intcore_n_4, + da(19) => intcore_n_5, + da(18) => intcore_n_6, + da(17) => intcore_n_7, + da(16) => intcore_n_8, + da(15) => intcore_n_9, + da(14) => intcore_n_10, + da(13) => intcore_n_11, + da(12) => intcore_n_12, + da(11) => intcore_n_13, + da(10) => intcore_n_14, + da(9) => intcore_n_15, + da(8) => intcore_n_16, + da(7) => intcore_n_17, + da(6) => intcore_n_18, + da(5) => intcore_n_19, + da(4) => intcore_n_20, + da(3) => intcore_n_21, + da(2) => intcore_n_22, + da(1) => intcore_n_23, + da(0) => intcore_n_24, + empty_match_reg => axi_control_n_17, + empty_match_reg_0 => axi_in_fifo_n_3, + eol_late_i_reg => \^eol_late_i_reg\, + fifo_wr_i => fifo_wr_i, + \genr_control_regs[0]\(0) => \genr_control_regs[0]\(0), + m_axis_video_tready => m_axis_video_tready, + m_axis_video_tvalid => m_axis_video_tvalid, + wen => \UOSD_AXIS_SYNC_FIFO/wen\, + \write_ptr_int_reg[0]\ => axi_out_fifo_n_0 + ); +intcore: entity work.Arty_Z7_20_v_rgb2ycrcb_0_0_rgb2ycrcb_core + port map ( + E(0) => \^needs_delay.shift_register_reg[1][0]\, + Q(23 downto 0) => vid_data_in_r(23 downto 0), + SR(0) => sclr, + aclk => aclk, + \core_control_regs[0]\(7 downto 0) => \core_control_regs[0]\(7 downto 0), + \core_control_regs[10]\(16 downto 0) => \core_control_regs[10]\(16 downto 0), + \core_control_regs[11]\(16 downto 0) => \core_control_regs[11]\(16 downto 0), + \core_control_regs[12]\(16 downto 0) => \core_control_regs[12]\(16 downto 0), + \core_control_regs[1]\(7 downto 0) => \core_control_regs[1]\(7 downto 0), + \core_control_regs[2]\(7 downto 0) => \core_control_regs[2]\(7 downto 0), + \core_control_regs[3]\(7 downto 0) => \core_control_regs[3]\(7 downto 0), + \core_control_regs[4]\(7 downto 0) => \core_control_regs[4]\(7 downto 0), + \core_control_regs[5]\(7 downto 0) => \core_control_regs[5]\(7 downto 0), + \core_control_regs[6]\(8 downto 0) => \core_control_regs[6]\(8 downto 0), + \core_control_regs[7]\(8 downto 0) => \core_control_regs[7]\(8 downto 0), + \core_control_regs[8]\(8 downto 0) => \core_control_regs[8]\(8 downto 0), + \core_control_regs[9]\(16 downto 0) => \core_control_regs[9]\(16 downto 0), + da(23) => intcore_n_1, + da(22) => intcore_n_2, + da(21) => intcore_n_3, + da(20) => intcore_n_4, + da(19) => intcore_n_5, + da(18) => intcore_n_6, + da(17) => intcore_n_7, + da(16) => intcore_n_8, + da(15) => intcore_n_9, + da(14) => intcore_n_10, + da(13) => intcore_n_11, + da(12) => intcore_n_12, + da(11) => intcore_n_13, + da(10) => intcore_n_14, + da(9) => intcore_n_15, + da(8) => intcore_n_16, + da(7) => intcore_n_17, + da(6) => intcore_n_18, + da(5) => intcore_n_19, + da(4) => intcore_n_20, + da(3) => intcore_n_21, + da(2) => intcore_n_22, + da(1) => intcore_n_23, + da(0) => intcore_n_24, + resetn_out => resetn_out + ); +\vid_data_in_r_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^needs_delay.shift_register_reg[1][0]\, + D => axi_in_fifo_n_30, + Q => vid_data_in_r(0), + R => '0' + ); +\vid_data_in_r_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^needs_delay.shift_register_reg[1][0]\, + D => axi_in_fifo_n_20, + Q => vid_data_in_r(10), + R => '0' + ); +\vid_data_in_r_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^needs_delay.shift_register_reg[1][0]\, + D => axi_in_fifo_n_19, + Q => vid_data_in_r(11), + R => '0' + ); +\vid_data_in_r_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^needs_delay.shift_register_reg[1][0]\, + D => axi_in_fifo_n_18, + Q => vid_data_in_r(12), + R => '0' + ); +\vid_data_in_r_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^needs_delay.shift_register_reg[1][0]\, + D => axi_in_fifo_n_17, + Q => vid_data_in_r(13), + R => '0' + ); +\vid_data_in_r_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^needs_delay.shift_register_reg[1][0]\, + D => axi_in_fifo_n_16, + Q => vid_data_in_r(14), + R => '0' + ); +\vid_data_in_r_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^needs_delay.shift_register_reg[1][0]\, + D => axi_in_fifo_n_15, + Q => vid_data_in_r(15), + R => '0' + ); +\vid_data_in_r_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^needs_delay.shift_register_reg[1][0]\, + D => axi_in_fifo_n_14, + Q => vid_data_in_r(16), + R => '0' + ); +\vid_data_in_r_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^needs_delay.shift_register_reg[1][0]\, + D => axi_in_fifo_n_13, + Q => vid_data_in_r(17), + R => '0' + ); +\vid_data_in_r_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^needs_delay.shift_register_reg[1][0]\, + D => axi_in_fifo_n_12, + Q => vid_data_in_r(18), + R => '0' + ); +\vid_data_in_r_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^needs_delay.shift_register_reg[1][0]\, + D => axi_in_fifo_n_11, + Q => vid_data_in_r(19), + R => '0' + ); +\vid_data_in_r_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^needs_delay.shift_register_reg[1][0]\, + D => axi_in_fifo_n_29, + Q => vid_data_in_r(1), + R => '0' + ); +\vid_data_in_r_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^needs_delay.shift_register_reg[1][0]\, + D => axi_in_fifo_n_10, + Q => vid_data_in_r(20), + R => '0' + ); +\vid_data_in_r_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^needs_delay.shift_register_reg[1][0]\, + D => axi_in_fifo_n_9, + Q => vid_data_in_r(21), + R => '0' + ); +\vid_data_in_r_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^needs_delay.shift_register_reg[1][0]\, + D => axi_in_fifo_n_8, + Q => vid_data_in_r(22), + R => '0' + ); +\vid_data_in_r_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^needs_delay.shift_register_reg[1][0]\, + D => axi_in_fifo_n_7, + Q => vid_data_in_r(23), + R => '0' + ); +\vid_data_in_r_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^needs_delay.shift_register_reg[1][0]\, + D => axi_in_fifo_n_28, + Q => vid_data_in_r(2), + R => '0' + ); +\vid_data_in_r_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^needs_delay.shift_register_reg[1][0]\, + D => axi_in_fifo_n_27, + Q => vid_data_in_r(3), + R => '0' + ); +\vid_data_in_r_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^needs_delay.shift_register_reg[1][0]\, + D => axi_in_fifo_n_26, + Q => vid_data_in_r(4), + R => '0' + ); +\vid_data_in_r_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^needs_delay.shift_register_reg[1][0]\, + D => axi_in_fifo_n_25, + Q => vid_data_in_r(5), + R => '0' + ); +\vid_data_in_r_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^needs_delay.shift_register_reg[1][0]\, + D => axi_in_fifo_n_24, + Q => vid_data_in_r(6), + R => '0' + ); +\vid_data_in_r_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^needs_delay.shift_register_reg[1][0]\, + D => axi_in_fifo_n_23, + Q => vid_data_in_r(7), + R => '0' + ); +\vid_data_in_r_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^needs_delay.shift_register_reg[1][0]\, + D => axi_in_fifo_n_22, + Q => vid_data_in_r(8), + R => '0' + ); +\vid_data_in_r_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \^needs_delay.shift_register_reg[1][0]\, + D => axi_in_fifo_n_21, + Q => vid_data_in_r(9), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb is + port ( + s_axi_aclk : in STD_LOGIC; + s_axi_aclken : in STD_LOGIC; + s_axi_aresetn : in STD_LOGIC; + aclk : in STD_LOGIC; + aclken : in STD_LOGIC; + aresetn : in STD_LOGIC; + intc_if : out STD_LOGIC_VECTOR ( 8 downto 0 ); + irq : out STD_LOGIC; + s_axis_video_tdata : in STD_LOGIC_VECTOR ( 23 downto 0 ); + s_axis_video_tready : out STD_LOGIC; + s_axis_video_tvalid : in STD_LOGIC; + s_axis_video_tlast : in STD_LOGIC; + s_axis_video_tuser_sof : in STD_LOGIC; + m_axis_video_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 ); + m_axis_video_tvalid : out STD_LOGIC; + m_axis_video_tready : in STD_LOGIC; + m_axis_video_tlast : out STD_LOGIC; + m_axis_video_tuser_sof : out STD_LOGIC; + s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_arvalid : in STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rvalid : out STD_LOGIC; + s_axi_rready : in STD_LOGIC + ); + attribute C_ACOEF : integer; + attribute C_ACOEF of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is 19595; + attribute C_ACTIVE_COLS : integer; + attribute C_ACTIVE_COLS of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is 1280; + attribute C_ACTIVE_ROWS : integer; + attribute C_ACTIVE_ROWS of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is 720; + attribute C_BCOEF : integer; + attribute C_BCOEF of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is 7471; + attribute C_CBMAX : integer; + attribute C_CBMAX of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is 240; + attribute C_CBMIN : integer; + attribute C_CBMIN of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is 16; + attribute C_CBOFFSET : integer; + attribute C_CBOFFSET of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is 128; + attribute C_CCOEF : integer; + attribute C_CCOEF of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is 46727; + attribute C_CRMAX : integer; + attribute C_CRMAX of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is 240; + attribute C_CRMIN : integer; + attribute C_CRMIN of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is 16; + attribute C_CROFFSET : integer; + attribute C_CROFFSET of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is 128; + attribute C_DCOEF : integer; + attribute C_DCOEF of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is 36962; + attribute C_FAMILY : string; + attribute C_FAMILY of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is "zynq"; + attribute C_HAS_AXI4_LITE : integer; + attribute C_HAS_AXI4_LITE of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is 0; + attribute C_HAS_CLAMP : integer; + attribute C_HAS_CLAMP of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is 1; + attribute C_HAS_CLIP : integer; + attribute C_HAS_CLIP of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is 1; + attribute C_HAS_DEBUG : integer; + attribute C_HAS_DEBUG of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is 0; + attribute C_HAS_INTC_IF : integer; + attribute C_HAS_INTC_IF of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is 0; + attribute C_MAX_COLS : integer; + attribute C_MAX_COLS of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is 1280; + attribute C_M_AXIS_VIDEO_DATA_WIDTH : integer; + attribute C_M_AXIS_VIDEO_DATA_WIDTH of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is 8; + attribute C_M_AXIS_VIDEO_FORMAT : integer; + attribute C_M_AXIS_VIDEO_FORMAT of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is 1; + attribute C_M_AXIS_VIDEO_TDATA_WIDTH : integer; + attribute C_M_AXIS_VIDEO_TDATA_WIDTH of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is 24; + attribute C_S_AXIS_VIDEO_DATA_WIDTH : integer; + attribute C_S_AXIS_VIDEO_DATA_WIDTH of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is 8; + attribute C_S_AXIS_VIDEO_FORMAT : integer; + attribute C_S_AXIS_VIDEO_FORMAT of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is 2; + attribute C_S_AXIS_VIDEO_TDATA_WIDTH : integer; + attribute C_S_AXIS_VIDEO_TDATA_WIDTH of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is 24; + attribute C_S_AXI_ADDR_WIDTH : integer; + attribute C_S_AXI_ADDR_WIDTH of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is 9; + attribute C_S_AXI_CLK_FREQ_HZ : integer; + attribute C_S_AXI_CLK_FREQ_HZ of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is 100000000; + attribute C_S_AXI_DATA_WIDTH : integer; + attribute C_S_AXI_DATA_WIDTH of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is 32; + attribute C_YMAX : integer; + attribute C_YMAX of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is 240; + attribute C_YMIN : integer; + attribute C_YMIN of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is 16; + attribute C_YOFFSET : integer; + attribute C_YOFFSET of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is 16; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is "v_rgb2ycrcb"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb : entity is "yes"; +end Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb; + +architecture STRUCTURE of Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb is + signal U_VIDEO_CTRL_n_318 : STD_LOGIC; + signal U_VIDEO_CTRL_n_319 : STD_LOGIC; + signal U_VIDEO_CTRL_n_320 : STD_LOGIC; + signal \core_control_regs[0]\ : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \core_control_regs[10]\ : STD_LOGIC_VECTOR ( 16 downto 0 ); + signal \core_control_regs[11]\ : STD_LOGIC_VECTOR ( 16 downto 0 ); + signal \core_control_regs[12]\ : STD_LOGIC_VECTOR ( 16 downto 0 ); + signal \core_control_regs[1]\ : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \core_control_regs[2]\ : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \core_control_regs[3]\ : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \core_control_regs[4]\ : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \core_control_regs[5]\ : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal \core_control_regs[6]\ : STD_LOGIC_VECTOR ( 16 downto 0 ); + signal \core_control_regs[7]\ : STD_LOGIC_VECTOR ( 16 downto 0 ); + signal \core_control_regs[8]\ : STD_LOGIC_VECTOR ( 16 downto 0 ); + signal \core_control_regs[9]\ : STD_LOGIC_VECTOR ( 16 downto 0 ); + signal core_d : STD_LOGIC; + signal \genr_control_regs[0]\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \^intc_if\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal reg_update : STD_LOGIC; + signal resetn : STD_LOGIC; + signal \time_control_regs[0]\ : STD_LOGIC_VECTOR ( 28 downto 0 ); + signal NLW_U_VIDEO_CTRL_ipif_cs_out_UNCONNECTED : STD_LOGIC; + signal NLW_U_VIDEO_CTRL_ipif_rnw_out_UNCONNECTED : STD_LOGIC; + signal \NLW_U_VIDEO_CTRL_core_control_regs[0]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 ); + signal \NLW_U_VIDEO_CTRL_core_control_regs[10]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 17 ); + signal \NLW_U_VIDEO_CTRL_core_control_regs[11]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 17 ); + signal \NLW_U_VIDEO_CTRL_core_control_regs[12]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 17 ); + signal \NLW_U_VIDEO_CTRL_core_control_regs[1]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 ); + signal \NLW_U_VIDEO_CTRL_core_control_regs[2]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 ); + signal \NLW_U_VIDEO_CTRL_core_control_regs[3]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 ); + signal \NLW_U_VIDEO_CTRL_core_control_regs[4]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 ); + signal \NLW_U_VIDEO_CTRL_core_control_regs[5]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 ); + signal \NLW_U_VIDEO_CTRL_core_control_regs[6]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 17 ); + signal \NLW_U_VIDEO_CTRL_core_control_regs[7]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 17 ); + signal \NLW_U_VIDEO_CTRL_core_control_regs[8]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 17 ); + signal \NLW_U_VIDEO_CTRL_core_control_regs[9]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 17 ); + signal \NLW_U_VIDEO_CTRL_genr_control_regs[1]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_genr_control_regs[2]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_genr_control_regs[3]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_genr_control_regs[4]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_genr_control_regs[5]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_genr_control_regs[6]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_genr_control_regs[7]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_U_VIDEO_CTRL_ipif_addr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal NLW_U_VIDEO_CTRL_ipif_data_out_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[0]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 29 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[1]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + attribute C_COREGEN_PATCH : integer; + attribute C_COREGEN_PATCH of U_VIDEO_CTRL : label is 0; + attribute C_CORE_AXI_WRITE : string; + attribute C_CORE_AXI_WRITE of U_VIDEO_CTRL : label is "416'b00000000000000001111111111111111000000000000000011111111111111110000000000000000111111111111111100000000000000001111111111111111000000000000000011111111111111110000000000000000111111111111111100000000000000011111111111111111000000000000000111111111111111110000000000000001111111111111111100000000000000111111111111111111000000000000001111111111111111110000000000000011111111111111111100000000000000111111111111111111"; + attribute C_CORE_DBUFFER : string; + attribute C_CORE_DBUFFER of U_VIDEO_CTRL : label is "416'b00000000000000001111111111111111000000000000000011111111111111110000000000000000111111111111111100000000000000001111111111111111000000000000000011111111111111110000000000000000111111111111111100000000000000011111111111111111000000000000000111111111111111110000000000000001111111111111111100000000000000011111111111111111000000000000000111111111111111110000000000000001111111111111111100000000000000011111111111111111"; + attribute C_CORE_DEFAULT : string; + attribute C_CORE_DEFAULT of U_VIDEO_CTRL : label is "416'b00000000000000000000000011110000000000000000000000000000000100000000000000000000000000001111000000000000000000000000000000010000000000000000000000000000111100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000100000000000000000000000000000001000000000000000000000000100110010001011000000000000000000011101001011110000000000000000101101101000011100000000000000001001000001100010"; + attribute C_CORE_NUM_REGS : integer; + attribute C_CORE_NUM_REGS of U_VIDEO_CTRL : label is 13; + attribute C_FAMILY of U_VIDEO_CTRL : label is "zynq"; + attribute C_GENR_AXI_WRITE : string; + attribute C_GENR_AXI_WRITE of U_VIDEO_CTRL : label is "256'b1100000000000000000000000011111100000000000000010000000000001111000000000000000000000000000011110000000000000001000000000000111100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute C_GENR_DBUFFER : string; + attribute C_GENR_DBUFFER of U_VIDEO_CTRL : label is "256'b0000000000000000000000000010110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute C_GENR_DEFAULT : string; + attribute C_GENR_DEFAULT of U_VIDEO_CTRL : label is "256'b0000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute C_GENR_NUM_REGS : integer; + attribute C_GENR_NUM_REGS of U_VIDEO_CTRL : label is 8; + attribute C_GENR_SELFCLR : string; + attribute C_GENR_SELFCLR of U_VIDEO_CTRL : label is "256'b0000000000000000000000000000000011111111111111111111111111111111111111111111111111111111111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute C_HAS_AXI4_LITE of U_VIDEO_CTRL : label is 0; + attribute C_HAS_IRQ : integer; + attribute C_HAS_IRQ of U_VIDEO_CTRL : label is 1; + attribute C_IS_EVAL : string; + attribute C_IS_EVAL of U_VIDEO_CTRL : label is "FALSE"; + attribute C_REVISION_NUMBER : integer; + attribute C_REVISION_NUMBER of U_VIDEO_CTRL : label is 1; + attribute C_SRESET_LENGTH : integer; + attribute C_SRESET_LENGTH of U_VIDEO_CTRL : label is 1; + attribute C_S_AXI_ADDR_WIDTH of U_VIDEO_CTRL : label is 9; + attribute C_S_AXI_DATA_WIDTH of U_VIDEO_CTRL : label is 32; + attribute C_TIMEOUT_HOURS : integer; + attribute C_TIMEOUT_HOURS of U_VIDEO_CTRL : label is 8; + attribute C_TIMEOUT_MINS : integer; + attribute C_TIMEOUT_MINS of U_VIDEO_CTRL : label is 0; + attribute C_TIME_AXI_WRITE : string; + attribute C_TIME_AXI_WRITE of U_VIDEO_CTRL : label is "64'b1111111111111111111111111111111100000000000000000000000000000111"; + attribute C_TIME_DBUFFER : string; + attribute C_TIME_DBUFFER of U_VIDEO_CTRL : label is "64'b1111111111111111111111111111111100000000000000000000000000000111"; + attribute C_TIME_DEFAULT : string; + attribute C_TIME_DEFAULT of U_VIDEO_CTRL : label is "64'b0000001011010000000001010000000000000000000000000000000000000000"; + attribute C_TIME_NUM_REGS : integer; + attribute C_TIME_NUM_REGS of U_VIDEO_CTRL : label is 2; + attribute C_VERSION_MAJOR : integer; + attribute C_VERSION_MAJOR of U_VIDEO_CTRL : label is 7; + attribute C_VERSION_MINOR : integer; + attribute C_VERSION_MINOR of U_VIDEO_CTRL : label is 1; + attribute C_VERSION_REVISION : integer; + attribute C_VERSION_REVISION of U_VIDEO_CTRL : label is 0; + attribute downgradeipidentifiedwarnings of U_VIDEO_CTRL : label is "yes"; +begin + intc_if(8 downto 0) <= \^intc_if\(8 downto 0); +U_VIDEO_CTRL: entity work.Arty_Z7_20_v_rgb2ycrcb_0_0_video_ctrl + port map ( + aclk => s_axi_aclk, + aclk_en => s_axi_aclken, + aresetn => s_axi_aresetn, + \core_control_regs[0]\(31 downto 16) => \NLW_U_VIDEO_CTRL_core_control_regs[0]_UNCONNECTED\(31 downto 16), + \core_control_regs[0]\(15 downto 0) => \core_control_regs[0]\(15 downto 0), + \core_control_regs[10]\(31 downto 17) => \NLW_U_VIDEO_CTRL_core_control_regs[10]_UNCONNECTED\(31 downto 17), + \core_control_regs[10]\(16 downto 0) => \core_control_regs[10]\(16 downto 0), + \core_control_regs[11]\(31 downto 17) => \NLW_U_VIDEO_CTRL_core_control_regs[11]_UNCONNECTED\(31 downto 17), + \core_control_regs[11]\(16 downto 0) => \core_control_regs[11]\(16 downto 0), + \core_control_regs[12]\(31 downto 17) => \NLW_U_VIDEO_CTRL_core_control_regs[12]_UNCONNECTED\(31 downto 17), + \core_control_regs[12]\(16 downto 0) => \core_control_regs[12]\(16 downto 0), + \core_control_regs[1]\(31 downto 16) => \NLW_U_VIDEO_CTRL_core_control_regs[1]_UNCONNECTED\(31 downto 16), + \core_control_regs[1]\(15 downto 0) => \core_control_regs[1]\(15 downto 0), + \core_control_regs[2]\(31 downto 16) => \NLW_U_VIDEO_CTRL_core_control_regs[2]_UNCONNECTED\(31 downto 16), + \core_control_regs[2]\(15 downto 0) => \core_control_regs[2]\(15 downto 0), + \core_control_regs[3]\(31 downto 16) => \NLW_U_VIDEO_CTRL_core_control_regs[3]_UNCONNECTED\(31 downto 16), + \core_control_regs[3]\(15 downto 0) => \core_control_regs[3]\(15 downto 0), + \core_control_regs[4]\(31 downto 16) => \NLW_U_VIDEO_CTRL_core_control_regs[4]_UNCONNECTED\(31 downto 16), + \core_control_regs[4]\(15 downto 0) => \core_control_regs[4]\(15 downto 0), + \core_control_regs[5]\(31 downto 16) => \NLW_U_VIDEO_CTRL_core_control_regs[5]_UNCONNECTED\(31 downto 16), + \core_control_regs[5]\(15 downto 0) => \core_control_regs[5]\(15 downto 0), + \core_control_regs[6]\(31 downto 17) => \NLW_U_VIDEO_CTRL_core_control_regs[6]_UNCONNECTED\(31 downto 17), + \core_control_regs[6]\(16 downto 0) => \core_control_regs[6]\(16 downto 0), + \core_control_regs[7]\(31 downto 17) => \NLW_U_VIDEO_CTRL_core_control_regs[7]_UNCONNECTED\(31 downto 17), + \core_control_regs[7]\(16 downto 0) => \core_control_regs[7]\(16 downto 0), + \core_control_regs[8]\(31 downto 17) => \NLW_U_VIDEO_CTRL_core_control_regs[8]_UNCONNECTED\(31 downto 17), + \core_control_regs[8]\(16 downto 0) => \core_control_regs[8]\(16 downto 0), + \core_control_regs[9]\(31 downto 17) => \NLW_U_VIDEO_CTRL_core_control_regs[9]_UNCONNECTED\(31 downto 17), + \core_control_regs[9]\(16 downto 0) => \core_control_regs[9]\(16 downto 0), + core_d_out => core_d, + \core_status_regs[0]\(31 downto 0) => B"00000000000000000000000000000000", + \core_status_regs[10]\(31 downto 0) => B"00000000000000000000000000000000", + \core_status_regs[11]\(31 downto 0) => B"00000000000000000000000000000000", + \core_status_regs[12]\(31 downto 0) => B"00000000000000000000000000000000", + \core_status_regs[1]\(31 downto 0) => B"00000000000000000000000000000000", + \core_status_regs[2]\(31 downto 0) => B"00000000000000000000000000000000", + \core_status_regs[3]\(31 downto 0) => B"00000000000000000000000000000000", + \core_status_regs[4]\(31 downto 0) => B"00000000000000000000000000000000", + \core_status_regs[5]\(31 downto 0) => B"00000000000000000000000000000000", + \core_status_regs[6]\(31 downto 0) => B"00000000000000000000000000000000", + \core_status_regs[7]\(31 downto 0) => B"00000000000000000000000000000000", + \core_status_regs[8]\(31 downto 0) => B"00000000000000000000000000000000", + \core_status_regs[9]\(31 downto 0) => B"00000000000000000000000000000000", + \genr_control_regs[0]\(31 downto 0) => \genr_control_regs[0]\(31 downto 0), + \genr_control_regs[1]\(31 downto 0) => \NLW_U_VIDEO_CTRL_genr_control_regs[1]_UNCONNECTED\(31 downto 0), + \genr_control_regs[2]\(31 downto 0) => \NLW_U_VIDEO_CTRL_genr_control_regs[2]_UNCONNECTED\(31 downto 0), + \genr_control_regs[3]\(31 downto 0) => \NLW_U_VIDEO_CTRL_genr_control_regs[3]_UNCONNECTED\(31 downto 0), + \genr_control_regs[4]\(31 downto 0) => \NLW_U_VIDEO_CTRL_genr_control_regs[4]_UNCONNECTED\(31 downto 0), + \genr_control_regs[5]\(31 downto 0) => \NLW_U_VIDEO_CTRL_genr_control_regs[5]_UNCONNECTED\(31 downto 0), + \genr_control_regs[6]\(31 downto 0) => \NLW_U_VIDEO_CTRL_genr_control_regs[6]_UNCONNECTED\(31 downto 0), + \genr_control_regs[7]\(31 downto 0) => \NLW_U_VIDEO_CTRL_genr_control_regs[7]_UNCONNECTED\(31 downto 0), + \genr_status_regs[0]\(31 downto 0) => B"00000000000000000000000000000000", + \genr_status_regs[1]\(31 downto 17) => B"000000000000000", + \genr_status_regs[1]\(16) => \^intc_if\(4), + \genr_status_regs[1]\(15 downto 4) => B"000000000000", + \genr_status_regs[1]\(3 downto 0) => \^intc_if\(3 downto 0), + \genr_status_regs[2]\(31 downto 4) => B"0000000000000000000000000000", + \genr_status_regs[2]\(3 downto 0) => \^intc_if\(8 downto 5), + \genr_status_regs[3]\(31 downto 0) => B"00000000000000000000000000000000", + \genr_status_regs[4]\(31 downto 0) => B"00000000000000000000000000000000", + \genr_status_regs[5]\(31 downto 0) => B"00000000000000000000000000000000", + \genr_status_regs[6]\(31 downto 0) => B"00000000000000000000000000000000", + \genr_status_regs[7]\(31 downto 0) => B"00000000000000000000000000000000", + ipif_addr_out(8 downto 0) => NLW_U_VIDEO_CTRL_ipif_addr_out_UNCONNECTED(8 downto 0), + ipif_cs_out => NLW_U_VIDEO_CTRL_ipif_cs_out_UNCONNECTED, + ipif_data_out(31 downto 0) => NLW_U_VIDEO_CTRL_ipif_data_out_UNCONNECTED(31 downto 0), + ipif_rnw_out => NLW_U_VIDEO_CTRL_ipif_rnw_out_UNCONNECTED, + irq => irq, + reg_update => reg_update, + resetn_out => resetn, + s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0), + s_axi_arready => s_axi_arready, + s_axi_arvalid => s_axi_arvalid, + s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0), + s_axi_awready => s_axi_awready, + s_axi_awvalid => s_axi_awvalid, + s_axi_bready => s_axi_bready, + s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0), + s_axi_bvalid => s_axi_bvalid, + s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), + s_axi_rready => s_axi_rready, + s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0), + s_axi_rvalid => s_axi_rvalid, + s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), + s_axi_wready => s_axi_wready, + s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0), + s_axi_wvalid => s_axi_wvalid, + \time_control_regs[0]\(31 downto 29) => \NLW_U_VIDEO_CTRL_time_control_regs[0]_UNCONNECTED\(31 downto 29), + \time_control_regs[0]\(28 downto 16) => \time_control_regs[0]\(28 downto 16), + \time_control_regs[0]\(15) => U_VIDEO_CTRL_n_318, + \time_control_regs[0]\(14) => U_VIDEO_CTRL_n_319, + \time_control_regs[0]\(13) => U_VIDEO_CTRL_n_320, + \time_control_regs[0]\(12 downto 0) => \time_control_regs[0]\(12 downto 0), + \time_control_regs[1]\(31 downto 0) => \NLW_U_VIDEO_CTRL_time_control_regs[1]_UNCONNECTED\(31 downto 0), + \time_status_regs[0]\(31 downto 0) => B"00000000000000000000000000000000", + \time_status_regs[1]\(31 downto 0) => B"00000000000000000000000000000000", + vid_aclk => aclk, + vid_aclk_en => aclken, + vid_aresetn => aresetn + ); +rgb2ycrcb_top_inst: entity work.Arty_Z7_20_v_rgb2ycrcb_0_0_rgb2ycrcb_top + port map ( + Q(25) => m_axis_video_tuser_sof, + Q(24) => m_axis_video_tlast, + Q(23 downto 0) => m_axis_video_tdata(23 downto 0), + aclk => aclk, + aclken => aclken, + \core_control_regs[0]\(7 downto 0) => \core_control_regs[0]\(7 downto 0), + \core_control_regs[10]\(16 downto 0) => \core_control_regs[10]\(16 downto 0), + \core_control_regs[11]\(16 downto 0) => \core_control_regs[11]\(16 downto 0), + \core_control_regs[12]\(16 downto 0) => \core_control_regs[12]\(16 downto 0), + \core_control_regs[1]\(7 downto 0) => \core_control_regs[1]\(7 downto 0), + \core_control_regs[2]\(7 downto 0) => \core_control_regs[2]\(7 downto 0), + \core_control_regs[3]\(7 downto 0) => \core_control_regs[3]\(7 downto 0), + \core_control_regs[4]\(7 downto 0) => \core_control_regs[4]\(7 downto 0), + \core_control_regs[5]\(7 downto 0) => \core_control_regs[5]\(7 downto 0), + \core_control_regs[6]\(8 downto 0) => \core_control_regs[6]\(8 downto 0), + \core_control_regs[7]\(8 downto 0) => \core_control_regs[7]\(8 downto 0), + \core_control_regs[8]\(8 downto 0) => \core_control_regs[8]\(8 downto 0), + \core_control_regs[9]\(16 downto 0) => \core_control_regs[9]\(16 downto 0), + core_d_out => core_d, + da(25) => s_axis_video_tuser_sof, + da(24) => s_axis_video_tlast, + da(23 downto 0) => s_axis_video_tdata(23 downto 0), + eol_late_i_reg => \^intc_if\(6), + \genr_control_regs[0]\(2) => \genr_control_regs[0]\(4), + \genr_control_regs[0]\(1 downto 0) => \genr_control_regs[0]\(1 downto 0), + intc_if(4 downto 0) => \^intc_if\(5 downto 1), + m_axis_video_tready => m_axis_video_tready, + m_axis_video_tvalid => m_axis_video_tvalid, + \needs_delay.shift_register_reg[1][0]\ => \^intc_if\(0), + reg_update => reg_update, + resetn_out => resetn, + s_axis_video_tready => s_axis_video_tready, + s_axis_video_tvalid => s_axis_video_tvalid, + sof_early_i_reg => \^intc_if\(7), + sof_early_i_reg_0 => \^intc_if\(8), + \time_control_regs[0]\(25 downto 13) => \time_control_regs[0]\(28 downto 16), + \time_control_regs[0]\(12 downto 0) => \time_control_regs[0]\(12 downto 0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_rgb2ycrcb_0_0 is + port ( + aclk : in STD_LOGIC; + aclken : in STD_LOGIC; + aresetn : in STD_LOGIC; + s_axis_video_tdata : in STD_LOGIC_VECTOR ( 23 downto 0 ); + s_axis_video_tready : out STD_LOGIC; + s_axis_video_tvalid : in STD_LOGIC; + s_axis_video_tlast : in STD_LOGIC; + s_axis_video_tuser_sof : in STD_LOGIC; + m_axis_video_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 ); + m_axis_video_tvalid : out STD_LOGIC; + m_axis_video_tready : in STD_LOGIC; + m_axis_video_tlast : out STD_LOGIC; + m_axis_video_tuser_sof : out STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of Arty_Z7_20_v_rgb2ycrcb_0_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of Arty_Z7_20_v_rgb2ycrcb_0_0 : entity is "Arty_Z7_20_v_rgb2ycrcb_0_0,v_rgb2ycrcb,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of Arty_Z7_20_v_rgb2ycrcb_0_0 : entity is "yes"; + attribute x_core_info : string; + attribute x_core_info of Arty_Z7_20_v_rgb2ycrcb_0_0 : entity is "v_rgb2ycrcb,Vivado 2016.4"; +end Arty_Z7_20_v_rgb2ycrcb_0_0; + +architecture STRUCTURE of Arty_Z7_20_v_rgb2ycrcb_0_0 is + signal NLW_U0_irq_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; + signal NLW_U0_intc_if_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute C_ACOEF : integer; + attribute C_ACOEF of U0 : label is 19595; + attribute C_ACTIVE_COLS : integer; + attribute C_ACTIVE_COLS of U0 : label is 1280; + attribute C_ACTIVE_ROWS : integer; + attribute C_ACTIVE_ROWS of U0 : label is 720; + attribute C_BCOEF : integer; + attribute C_BCOEF of U0 : label is 7471; + attribute C_CBMAX : integer; + attribute C_CBMAX of U0 : label is 240; + attribute C_CBMIN : integer; + attribute C_CBMIN of U0 : label is 16; + attribute C_CBOFFSET : integer; + attribute C_CBOFFSET of U0 : label is 128; + attribute C_CCOEF : integer; + attribute C_CCOEF of U0 : label is 46727; + attribute C_CRMAX : integer; + attribute C_CRMAX of U0 : label is 240; + attribute C_CRMIN : integer; + attribute C_CRMIN of U0 : label is 16; + attribute C_CROFFSET : integer; + attribute C_CROFFSET of U0 : label is 128; + attribute C_DCOEF : integer; + attribute C_DCOEF of U0 : label is 36962; + attribute C_FAMILY : string; + attribute C_FAMILY of U0 : label is "zynq"; + attribute C_HAS_AXI4_LITE : integer; + attribute C_HAS_AXI4_LITE of U0 : label is 0; + attribute C_HAS_CLAMP : integer; + attribute C_HAS_CLAMP of U0 : label is 1; + attribute C_HAS_CLIP : integer; + attribute C_HAS_CLIP of U0 : label is 1; + attribute C_HAS_DEBUG : integer; + attribute C_HAS_DEBUG of U0 : label is 0; + attribute C_HAS_INTC_IF : integer; + attribute C_HAS_INTC_IF of U0 : label is 0; + attribute C_MAX_COLS : integer; + attribute C_MAX_COLS of U0 : label is 1280; + attribute C_M_AXIS_VIDEO_DATA_WIDTH : integer; + attribute C_M_AXIS_VIDEO_DATA_WIDTH of U0 : label is 8; + attribute C_M_AXIS_VIDEO_FORMAT : integer; + attribute C_M_AXIS_VIDEO_FORMAT of U0 : label is 1; + attribute C_M_AXIS_VIDEO_TDATA_WIDTH : integer; + attribute C_M_AXIS_VIDEO_TDATA_WIDTH of U0 : label is 24; + attribute C_S_AXIS_VIDEO_DATA_WIDTH : integer; + attribute C_S_AXIS_VIDEO_DATA_WIDTH of U0 : label is 8; + attribute C_S_AXIS_VIDEO_FORMAT : integer; + attribute C_S_AXIS_VIDEO_FORMAT of U0 : label is 2; + attribute C_S_AXIS_VIDEO_TDATA_WIDTH : integer; + attribute C_S_AXIS_VIDEO_TDATA_WIDTH of U0 : label is 24; + attribute C_S_AXI_ADDR_WIDTH : integer; + attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9; + attribute C_S_AXI_CLK_FREQ_HZ : integer; + attribute C_S_AXI_CLK_FREQ_HZ of U0 : label is 100000000; + attribute C_S_AXI_DATA_WIDTH : integer; + attribute C_S_AXI_DATA_WIDTH of U0 : label is 32; + attribute C_YMAX : integer; + attribute C_YMAX of U0 : label is 240; + attribute C_YMIN : integer; + attribute C_YMIN of U0 : label is 16; + attribute C_YOFFSET : integer; + attribute C_YOFFSET of U0 : label is 16; + attribute downgradeipidentifiedwarnings of U0 : label is "yes"; +begin +U0: entity work.Arty_Z7_20_v_rgb2ycrcb_0_0_v_rgb2ycrcb + port map ( + aclk => aclk, + aclken => aclken, + aresetn => aresetn, + intc_if(8 downto 0) => NLW_U0_intc_if_UNCONNECTED(8 downto 0), + irq => NLW_U0_irq_UNCONNECTED, + m_axis_video_tdata(23 downto 0) => m_axis_video_tdata(23 downto 0), + m_axis_video_tlast => m_axis_video_tlast, + m_axis_video_tready => m_axis_video_tready, + m_axis_video_tuser_sof => m_axis_video_tuser_sof, + m_axis_video_tvalid => m_axis_video_tvalid, + s_axi_aclk => '0', + s_axi_aclken => '1', + s_axi_araddr(8 downto 0) => B"000000000", + s_axi_aresetn => '1', + s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, + s_axi_arvalid => '0', + s_axi_awaddr(8 downto 0) => B"000000000", + s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, + s_axi_awvalid => '0', + s_axi_bready => '0', + s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), + s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, + s_axi_rdata(31 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(31 downto 0), + s_axi_rready => '0', + s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), + s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, + s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000", + s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, + s_axi_wstrb(3 downto 0) => B"0000", + s_axi_wvalid => '0', + s_axis_video_tdata(23 downto 0) => s_axis_video_tdata(23 downto 0), + s_axis_video_tlast => s_axis_video_tlast, + s_axis_video_tready => s_axis_video_tready, + s_axis_video_tuser_sof => s_axis_video_tuser_sof, + s_axis_video_tvalid => s_axis_video_tvalid + ); +end STRUCTURE; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0_stub.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0_stub.v new file mode 100644 index 0000000..de43b50 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0_stub.v @@ -0,0 +1,35 @@ +// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +// Date : Mon Mar 06 11:30:49 2017 +// Host : WK73 running 64-bit Service Pack 1 (build 7601) +// Command : write_verilog -force -mode synth_stub +// c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0_stub.v +// Design : Arty_Z7_20_v_rgb2ycrcb_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg400-1 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "v_rgb2ycrcb,Vivado 2016.4" *) +module Arty_Z7_20_v_rgb2ycrcb_0_0(aclk, aclken, aresetn, s_axis_video_tdata, + s_axis_video_tready, s_axis_video_tvalid, s_axis_video_tlast, s_axis_video_tuser_sof, + m_axis_video_tdata, m_axis_video_tvalid, m_axis_video_tready, m_axis_video_tlast, + m_axis_video_tuser_sof) +/* synthesis syn_black_box black_box_pad_pin="aclk,aclken,aresetn,s_axis_video_tdata[23:0],s_axis_video_tready,s_axis_video_tvalid,s_axis_video_tlast,s_axis_video_tuser_sof,m_axis_video_tdata[23:0],m_axis_video_tvalid,m_axis_video_tready,m_axis_video_tlast,m_axis_video_tuser_sof" */; + input aclk; + input aclken; + input aresetn; + input [23:0]s_axis_video_tdata; + output s_axis_video_tready; + input s_axis_video_tvalid; + input s_axis_video_tlast; + input s_axis_video_tuser_sof; + output [23:0]m_axis_video_tdata; + output m_axis_video_tvalid; + input m_axis_video_tready; + output m_axis_video_tlast; + output m_axis_video_tuser_sof; +endmodule diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0_stub.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0_stub.vhdl new file mode 100644 index 0000000..f552de4 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0_stub.vhdl @@ -0,0 +1,42 @@ +-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +-- Date : Mon Mar 06 11:30:49 2017 +-- Host : WK73 running 64-bit Service Pack 1 (build 7601) +-- Command : write_vhdl -force -mode synth_stub +-- c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/Arty_Z7_20_v_rgb2ycrcb_0_0_stub.vhdl +-- Design : Arty_Z7_20_v_rgb2ycrcb_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg400-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Arty_Z7_20_v_rgb2ycrcb_0_0 is + Port ( + aclk : in STD_LOGIC; + aclken : in STD_LOGIC; + aresetn : in STD_LOGIC; + s_axis_video_tdata : in STD_LOGIC_VECTOR ( 23 downto 0 ); + s_axis_video_tready : out STD_LOGIC; + s_axis_video_tvalid : in STD_LOGIC; + s_axis_video_tlast : in STD_LOGIC; + s_axis_video_tuser_sof : in STD_LOGIC; + m_axis_video_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 ); + m_axis_video_tvalid : out STD_LOGIC; + m_axis_video_tready : in STD_LOGIC; + m_axis_video_tlast : out STD_LOGIC; + m_axis_video_tuser_sof : out STD_LOGIC + ); + +end Arty_Z7_20_v_rgb2ycrcb_0_0; + +architecture stub of Arty_Z7_20_v_rgb2ycrcb_0_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "aclk,aclken,aresetn,s_axis_video_tdata[23:0],s_axis_video_tready,s_axis_video_tvalid,s_axis_video_tlast,s_axis_video_tuser_sof,m_axis_video_tdata[23:0],m_axis_video_tvalid,m_axis_video_tready,m_axis_video_tlast,m_axis_video_tuser_sof"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "v_rgb2ycrcb,Vivado 2016.4"; +begin +end; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/sim/Arty_Z7_20_v_rgb2ycrcb_0_0.vhd b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/sim/Arty_Z7_20_v_rgb2ycrcb_0_0.vhd new file mode 100644 index 0000000..a48477e --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/sim/Arty_Z7_20_v_rgb2ycrcb_0_0.vhd @@ -0,0 +1,228 @@ +-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:v_rgb2ycrcb:7.1 +-- IP Revision: 10 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY v_rgb2ycrcb_v7_1_10; +USE v_rgb2ycrcb_v7_1_10.v_rgb2ycrcb; + +ENTITY Arty_Z7_20_v_rgb2ycrcb_0_0 IS + PORT ( + aclk : IN STD_LOGIC; + aclken : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + s_axis_video_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + s_axis_video_tready : OUT STD_LOGIC; + s_axis_video_tvalid : IN STD_LOGIC; + s_axis_video_tlast : IN STD_LOGIC; + s_axis_video_tuser_sof : IN STD_LOGIC; + m_axis_video_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + m_axis_video_tvalid : OUT STD_LOGIC; + m_axis_video_tready : IN STD_LOGIC; + m_axis_video_tlast : OUT STD_LOGIC; + m_axis_video_tuser_sof : OUT STD_LOGIC + ); +END Arty_Z7_20_v_rgb2ycrcb_0_0; + +ARCHITECTURE Arty_Z7_20_v_rgb2ycrcb_0_0_arch OF Arty_Z7_20_v_rgb2ycrcb_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF Arty_Z7_20_v_rgb2ycrcb_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT v_rgb2ycrcb IS + GENERIC ( + C_S_AXIS_VIDEO_DATA_WIDTH : INTEGER; + C_S_AXIS_VIDEO_FORMAT : INTEGER; + C_S_AXIS_VIDEO_TDATA_WIDTH : INTEGER; + C_M_AXIS_VIDEO_DATA_WIDTH : INTEGER; + C_M_AXIS_VIDEO_FORMAT : INTEGER; + C_M_AXIS_VIDEO_TDATA_WIDTH : INTEGER; + c_s_axi_addr_width : INTEGER; + c_s_axi_data_width : INTEGER; + C_HAS_AXI4_LITE : INTEGER; + C_HAS_DEBUG : INTEGER; + C_HAS_INTC_IF : INTEGER; + C_MAX_COLS : INTEGER; + C_ACTIVE_COLS : INTEGER; + C_ACTIVE_ROWS : INTEGER; + C_HAS_CLIP : INTEGER; + C_HAS_CLAMP : INTEGER; + C_ACOEF : INTEGER; + C_BCOEF : INTEGER; + C_CCOEF : INTEGER; + C_DCOEF : INTEGER; + C_YOFFSET : INTEGER; + C_CBOFFSET : INTEGER; + C_CROFFSET : INTEGER; + C_YMAX : INTEGER; + C_YMIN : INTEGER; + C_CBMAX : INTEGER; + C_CBMIN : INTEGER; + C_CRMAX : INTEGER; + C_CRMIN : INTEGER; + C_S_AXI_CLK_FREQ_HZ : INTEGER; + C_FAMILY : STRING + ); + PORT ( + aclk : IN STD_LOGIC; + aclken : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + s_axi_aclk : IN STD_LOGIC; + s_axi_aclken : IN STD_LOGIC; + s_axi_aresetn : IN STD_LOGIC; + intc_if : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); + irq : OUT STD_LOGIC; + s_axis_video_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + s_axis_video_tready : OUT STD_LOGIC; + s_axis_video_tvalid : IN STD_LOGIC; + s_axis_video_tlast : IN STD_LOGIC; + s_axis_video_tuser_sof : IN STD_LOGIC; + m_axis_video_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + m_axis_video_tvalid : OUT STD_LOGIC; + m_axis_video_tready : IN STD_LOGIC; + m_axis_video_tlast : OUT STD_LOGIC; + m_axis_video_tuser_sof : OUT STD_LOGIC; + s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_awvalid : IN STD_LOGIC; + s_axi_awready : OUT STD_LOGIC; + s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + s_axi_wvalid : IN STD_LOGIC; + s_axi_wready : OUT STD_LOGIC; + s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_bvalid : OUT STD_LOGIC; + s_axi_bready : IN STD_LOGIC; + s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_arvalid : IN STD_LOGIC; + s_axi_arready : OUT STD_LOGIC; + s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_rvalid : OUT STD_LOGIC; + s_axi_rready : IN STD_LOGIC + ); + END COMPONENT v_rgb2ycrcb; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; + ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE"; + ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn_intf RST"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tuser_sof: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TUSER"; + ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TVALID"; + ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TREADY"; + ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tuser_sof: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TUSER"; +BEGIN + U0 : v_rgb2ycrcb + GENERIC MAP ( + C_S_AXIS_VIDEO_DATA_WIDTH => 8, + C_S_AXIS_VIDEO_FORMAT => 2, + C_S_AXIS_VIDEO_TDATA_WIDTH => 24, + C_M_AXIS_VIDEO_DATA_WIDTH => 8, + C_M_AXIS_VIDEO_FORMAT => 1, + C_M_AXIS_VIDEO_TDATA_WIDTH => 24, + c_s_axi_addr_width => 9, + c_s_axi_data_width => 32, + C_HAS_AXI4_LITE => 0, + C_HAS_DEBUG => 0, + C_HAS_INTC_IF => 0, + C_MAX_COLS => 1280, + C_ACTIVE_COLS => 1280, + C_ACTIVE_ROWS => 720, + C_HAS_CLIP => 1, + C_HAS_CLAMP => 1, + C_ACOEF => 19595, + C_BCOEF => 7471, + C_CCOEF => 46727, + C_DCOEF => 36962, + C_YOFFSET => 16, + C_CBOFFSET => 128, + C_CROFFSET => 128, + C_YMAX => 240, + C_YMIN => 16, + C_CBMAX => 240, + C_CBMIN => 16, + C_CRMAX => 240, + C_CRMIN => 16, + C_S_AXI_CLK_FREQ_HZ => 100000000, + C_FAMILY => "zynq" + ) + PORT MAP ( + aclk => aclk, + aclken => aclken, + aresetn => aresetn, + s_axi_aclk => '0', + s_axi_aclken => '1', + s_axi_aresetn => '1', + s_axis_video_tdata => s_axis_video_tdata, + s_axis_video_tready => s_axis_video_tready, + s_axis_video_tvalid => s_axis_video_tvalid, + s_axis_video_tlast => s_axis_video_tlast, + s_axis_video_tuser_sof => s_axis_video_tuser_sof, + m_axis_video_tdata => m_axis_video_tdata, + m_axis_video_tvalid => m_axis_video_tvalid, + m_axis_video_tready => m_axis_video_tready, + m_axis_video_tlast => m_axis_video_tlast, + m_axis_video_tuser_sof => m_axis_video_tuser_sof, + s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)), + s_axi_awvalid => '0', + s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), + s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), + s_axi_wvalid => '0', + s_axi_bready => '0', + s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)), + s_axi_arvalid => '0', + s_axi_rready => '0' + ); +END Arty_Z7_20_v_rgb2ycrcb_0_0_arch; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/synth/Arty_Z7_20_v_rgb2ycrcb_0_0.vhd b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/synth/Arty_Z7_20_v_rgb2ycrcb_0_0.vhd new file mode 100644 index 0000000..e8ff44d --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_rgb2ycrcb_0_0/synth/Arty_Z7_20_v_rgb2ycrcb_0_0.vhd @@ -0,0 +1,235 @@ +-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:v_rgb2ycrcb:7.1 +-- IP Revision: 10 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY v_rgb2ycrcb_v7_1_10; +USE v_rgb2ycrcb_v7_1_10.v_rgb2ycrcb; + +ENTITY Arty_Z7_20_v_rgb2ycrcb_0_0 IS + PORT ( + aclk : IN STD_LOGIC; + aclken : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + s_axis_video_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + s_axis_video_tready : OUT STD_LOGIC; + s_axis_video_tvalid : IN STD_LOGIC; + s_axis_video_tlast : IN STD_LOGIC; + s_axis_video_tuser_sof : IN STD_LOGIC; + m_axis_video_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + m_axis_video_tvalid : OUT STD_LOGIC; + m_axis_video_tready : IN STD_LOGIC; + m_axis_video_tlast : OUT STD_LOGIC; + m_axis_video_tuser_sof : OUT STD_LOGIC + ); +END Arty_Z7_20_v_rgb2ycrcb_0_0; + +ARCHITECTURE Arty_Z7_20_v_rgb2ycrcb_0_0_arch OF Arty_Z7_20_v_rgb2ycrcb_0_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF Arty_Z7_20_v_rgb2ycrcb_0_0_arch: ARCHITECTURE IS "yes"; + COMPONENT v_rgb2ycrcb IS + GENERIC ( + C_S_AXIS_VIDEO_DATA_WIDTH : INTEGER; + C_S_AXIS_VIDEO_FORMAT : INTEGER; + C_S_AXIS_VIDEO_TDATA_WIDTH : INTEGER; + C_M_AXIS_VIDEO_DATA_WIDTH : INTEGER; + C_M_AXIS_VIDEO_FORMAT : INTEGER; + C_M_AXIS_VIDEO_TDATA_WIDTH : INTEGER; + c_s_axi_addr_width : INTEGER; + c_s_axi_data_width : INTEGER; + C_HAS_AXI4_LITE : INTEGER; + C_HAS_DEBUG : INTEGER; + C_HAS_INTC_IF : INTEGER; + C_MAX_COLS : INTEGER; + C_ACTIVE_COLS : INTEGER; + C_ACTIVE_ROWS : INTEGER; + C_HAS_CLIP : INTEGER; + C_HAS_CLAMP : INTEGER; + C_ACOEF : INTEGER; + C_BCOEF : INTEGER; + C_CCOEF : INTEGER; + C_DCOEF : INTEGER; + C_YOFFSET : INTEGER; + C_CBOFFSET : INTEGER; + C_CROFFSET : INTEGER; + C_YMAX : INTEGER; + C_YMIN : INTEGER; + C_CBMAX : INTEGER; + C_CBMIN : INTEGER; + C_CRMAX : INTEGER; + C_CRMIN : INTEGER; + C_S_AXI_CLK_FREQ_HZ : INTEGER; + C_FAMILY : STRING + ); + PORT ( + aclk : IN STD_LOGIC; + aclken : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + s_axi_aclk : IN STD_LOGIC; + s_axi_aclken : IN STD_LOGIC; + s_axi_aresetn : IN STD_LOGIC; + intc_if : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); + irq : OUT STD_LOGIC; + s_axis_video_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + s_axis_video_tready : OUT STD_LOGIC; + s_axis_video_tvalid : IN STD_LOGIC; + s_axis_video_tlast : IN STD_LOGIC; + s_axis_video_tuser_sof : IN STD_LOGIC; + m_axis_video_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + m_axis_video_tvalid : OUT STD_LOGIC; + m_axis_video_tready : IN STD_LOGIC; + m_axis_video_tlast : OUT STD_LOGIC; + m_axis_video_tuser_sof : OUT STD_LOGIC; + s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_awvalid : IN STD_LOGIC; + s_axi_awready : OUT STD_LOGIC; + s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + s_axi_wvalid : IN STD_LOGIC; + s_axi_wready : OUT STD_LOGIC; + s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_bvalid : OUT STD_LOGIC; + s_axi_bready : IN STD_LOGIC; + s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_arvalid : IN STD_LOGIC; + s_axi_arready : OUT STD_LOGIC; + s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_rvalid : OUT STD_LOGIC; + s_axi_rready : IN STD_LOGIC + ); + END COMPONENT v_rgb2ycrcb; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF Arty_Z7_20_v_rgb2ycrcb_0_0_arch: ARCHITECTURE IS "v_rgb2ycrcb,Vivado 2016.4"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF Arty_Z7_20_v_rgb2ycrcb_0_0_arch : ARCHITECTURE IS "Arty_Z7_20_v_rgb2ycrcb_0_0,v_rgb2ycrcb,{}"; + ATTRIBUTE CORE_GENERATION_INFO : STRING; + ATTRIBUTE CORE_GENERATION_INFO OF Arty_Z7_20_v_rgb2ycrcb_0_0_arch: ARCHITECTURE IS "Arty_Z7_20_v_rgb2ycrcb_0_0,v_rgb2ycrcb,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=v_rgb2ycrcb,x_ipVersion=7.1,x_ipCoreRevision=10,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_S_AXIS_VIDEO_DATA_WIDTH=8,C_S_AXIS_VIDEO_FORMAT=2,C_S_AXIS_VIDEO_TDATA_WIDTH=24,C_M_AXIS_VIDEO_DATA_WIDTH=8,C_M_AXIS_VIDEO_FORMAT=1,C_M_AXIS_VIDEO_TDATA_WIDTH=24,c_s_axi_addr_width=9,c_s_axi_data_width=32,C_HAS_AXI4_LITE=0,C_HAS_DEBUG=0,C_HAS_INTC_IF=0,C_MAX_COLS=1280,C_ACTIVE_COLS=1280,C_ACTIVE_R" & +"OWS=720,C_HAS_CLIP=1,C_HAS_CLAMP=1,C_ACOEF=19595,C_BCOEF=7471,C_CCOEF=46727,C_DCOEF=36962,C_YOFFSET=16,C_CBOFFSET=128,C_CROFFSET=128,C_YMAX=240,C_YMIN=16,C_CBMAX=240,C_CBMIN=16,C_CRMAX=240,C_CRMIN=16,C_S_AXI_CLK_FREQ_HZ=100000000,C_FAMILY=zynq}"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; + ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE"; + ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn_intf RST"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tuser_sof: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TUSER"; + ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TDATA"; + ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TVALID"; + ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TREADY"; + ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TLAST"; + ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tuser_sof: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TUSER"; +BEGIN + U0 : v_rgb2ycrcb + GENERIC MAP ( + C_S_AXIS_VIDEO_DATA_WIDTH => 8, + C_S_AXIS_VIDEO_FORMAT => 2, + C_S_AXIS_VIDEO_TDATA_WIDTH => 24, + C_M_AXIS_VIDEO_DATA_WIDTH => 8, + C_M_AXIS_VIDEO_FORMAT => 1, + C_M_AXIS_VIDEO_TDATA_WIDTH => 24, + c_s_axi_addr_width => 9, + c_s_axi_data_width => 32, + C_HAS_AXI4_LITE => 0, + C_HAS_DEBUG => 0, + C_HAS_INTC_IF => 0, + C_MAX_COLS => 1280, + C_ACTIVE_COLS => 1280, + C_ACTIVE_ROWS => 720, + C_HAS_CLIP => 1, + C_HAS_CLAMP => 1, + C_ACOEF => 19595, + C_BCOEF => 7471, + C_CCOEF => 46727, + C_DCOEF => 36962, + C_YOFFSET => 16, + C_CBOFFSET => 128, + C_CROFFSET => 128, + C_YMAX => 240, + C_YMIN => 16, + C_CBMAX => 240, + C_CBMIN => 16, + C_CRMAX => 240, + C_CRMIN => 16, + C_S_AXI_CLK_FREQ_HZ => 100000000, + C_FAMILY => "zynq" + ) + PORT MAP ( + aclk => aclk, + aclken => aclken, + aresetn => aresetn, + s_axi_aclk => '0', + s_axi_aclken => '1', + s_axi_aresetn => '1', + s_axis_video_tdata => s_axis_video_tdata, + s_axis_video_tready => s_axis_video_tready, + s_axis_video_tvalid => s_axis_video_tvalid, + s_axis_video_tlast => s_axis_video_tlast, + s_axis_video_tuser_sof => s_axis_video_tuser_sof, + m_axis_video_tdata => m_axis_video_tdata, + m_axis_video_tvalid => m_axis_video_tvalid, + m_axis_video_tready => m_axis_video_tready, + m_axis_video_tlast => m_axis_video_tlast, + m_axis_video_tuser_sof => m_axis_video_tuser_sof, + s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)), + s_axi_awvalid => '0', + s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), + s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), + s_axi_wvalid => '0', + s_axi_bready => '0', + s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)), + s_axi_arvalid => '0', + s_axi_rready => '0' + ); +END Arty_Z7_20_v_rgb2ycrcb_0_0_arch; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0.dcp b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0.dcp new file mode 100644 index 0000000..a67f9da Binary files /dev/null and b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0.dcp differ diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0.xci b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0.xci new file mode 100644 index 0000000..06661d2 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0.xci @@ -0,0 +1,284 @@ + + + xilinx.com + xci + unknown + 1.0 + + + Arty_Z7_20_v_tc_1_0 + + + ACTIVE_LOW + Arty_Z7_20_dvi2rgb_0_0_PixelClk + 100000000 + 0.000 + 9 + 0 + 0 + 0 + Arty_Z7_20_processing_system7_0_0_FCLK_CLK0 + 32 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + ACTIVE_LOW + Arty_Z7_20_processing_system7_0_0_FCLK_CLK0 + 100000000 + 0.000 + 1 + 0 + 1 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 1 + 0 + 1280 + 1280 + 750 + 1280 + 1280 + 729 + 724 + 1280 + 1280 + 750 + 1280 + 1280 + 729 + 724 + 0 + 1 + 1280 + 1 + 1 + 1650 + 1 + 1430 + 1 + 1390 + 0 + 720 + 1 + 1 + 2 + 1 + 1 + 1 + 1 + 0 + 2048 + 4096 + 1 + 0 + virtex7 + Arty_Z7_20_v_tc_1_0 + false + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + High + High + 0 + 1280 + 1280 + 750 + 1280 + 1280 + 729 + 724 + 1280 + 1280 + 750 + 1280 + 1280 + 729 + 724 + false + High + 1280 + High + 1650 + 1430 + High + 1390 + false + 720 + High + RGB + High + true + true + false + false + 720p + false + false + true + true + false + true + false + 1 + false + true + true + true + 4096 + 2048 + false + true + true + true + zynq + digilentinc.com:arty-z7-20:part0:1.0 + xc7z020 + clg400 + VHDL + + MIXED + -1 + + TRUE + TRUE + IP_Integrator + 10 + TRUE + . + + ../../ipshared + 2016.4 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0.xml b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0.xml new file mode 100644 index 0000000..79710fb --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0.xml @@ -0,0 +1,3405 @@ + + + xilinx.com + customized_ip + Arty_Z7_20_v_tc_1_0 + 1.0 + + + s_axi_aclk_intf + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + ctrl + + + ASSOCIATED_RESET + s_axi_aresetn + + + ASSOCIATED_CLKEN + s_axi_aclken + + + FREQ_HZ + ctrl clock frequency + ctrl clock frequency + 100000000 + + + PHASE + 0.000 + + + CLK_DOMAIN + Arty_Z7_20_processing_system7_0_0_FCLK_CLK0 + + + + + + true + + + + + + s_axi_aclken_intf + + + + + + + CE + + + s_axi_aclken + + + + + + POLARITY + ACTIVE_LOW + + + + + + true + + + + + + s_axi_aresetn_intf + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + true + + + + + + ctrl + CTRL + AXI4-Lite + + + + + + + ARADDR + + + s_axi_araddr + + + + + ARREADY + + + s_axi_arready + + + + + ARVALID + + + s_axi_arvalid + + + + + AWADDR + + + s_axi_awaddr + + + + + AWREADY + + + s_axi_awready + + + + + AWVALID + + + s_axi_awvalid + + + + + BREADY + + + s_axi_bready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + RDATA + + + s_axi_rdata + + + + + RREADY + + + s_axi_rready + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + WDATA + + + s_axi_wdata + + + + + WREADY + + + s_axi_wready + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + + DATA_WIDTH + 32 + + + PROTOCOL + AXI4LITE + + + FREQ_HZ + 100000000 + + + ID_WIDTH + 0 + + + ADDR_WIDTH + 9 + + + AWUSER_WIDTH + 0 + + + ARUSER_WIDTH + 0 + + + WUSER_WIDTH + 0 + + + RUSER_WIDTH + 0 + + + BUSER_WIDTH + 0 + + + READ_WRITE_MODE + READ_WRITE + + + HAS_BURST + 0 + + + HAS_LOCK + 0 + + + HAS_PROT + 0 + + + HAS_CACHE + 0 + + + HAS_QOS + 0 + + + HAS_REGION + 0 + + + HAS_WSTRB + 1 + + + HAS_BRESP + 1 + + + HAS_RRESP + 1 + + + SUPPORTS_NARROW_BURST + 0 + + + NUM_READ_OUTSTANDING + 1 + + + NUM_WRITE_OUTSTANDING + 1 + + + MAX_BURST_LENGTH + 1 + + + PHASE + 0.000 + + + CLK_DOMAIN + Arty_Z7_20_processing_system7_0_0_FCLK_CLK0 + + + NUM_READ_THREADS + 1 + + + NUM_WRITE_THREADS + 1 + + + RUSER_BITS_PER_BYTE + 0 + + + WUSER_BITS_PER_BYTE + 0 + + + + + + true + + + + + + vtiming_in + VTIMING_IN + VTIMING_IN + + + + + + + ACTIVE_VIDEO + + + active_video_in + + + + + FIELD + + + field_id_in + + + + + HBLANK + + + hblank_in + + + + + HSYNC + + + hsync_in + + + + + VBLANK + + + vblank_in + + + + + VSYNC + + + vsync_in + + + + + + + true + + + + + + vtiming_out + VTIMING_OUT + VTIMING_OUT + + + + + + + ACTIVE_VIDEO + + + active_video_out + + + + + FIELD + + + field_id_out + + + + + HBLANK + + + hblank_out + + + + + HSYNC + + + hsync_out + + + + + VBLANK + + + vblank_out + + + + + VSYNC + + + vsync_out + + + + + + + false + + + + + + clk_intf + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_BUSIF + vtiming_in:vtiming_out + + + ASSOCIATED_RESET + resetn + + + ASSOCIATED_CLKEN + clken + + + FREQ_HZ + vtiming clock frequency + vtiming clock frequency + 100000000 + + + PHASE + 0.000 + + + CLK_DOMAIN + Arty_Z7_20_dvi2rgb_0_0_PixelClk + + + + + resetn_intf + + + + + + + RST + + + resetn + + + + + + POLARITY + ACTIVE_LOW + + + + + clken_intf + + + + + + + CE + + + clken + + + + + + POLARITY + ACTIVE_LOW + + + + + IRQ + irq + + + + + + + INTERRUPT + + + irq + + + + + + SENSITIVITY + LEVEL_HIGH + + + PortWidth + 1 + + + + + + true + + + + + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + + xilinx_vhdlsynthesis_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset + + + xilinx_vhdlsynthesis_view_fileset + + + + GENtimestamp + Fri Feb 24 23:58:24 UTC 2017 + + + boundaryCRC + 2dd40584 + + + boundaryCRCversion + 1 + + + customizationCRC + 6b2d7485 + + + customizationCRCversion + 6 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + xilinx_synthesisconstraints_view_fileset + + + + GENtimestamp + Sun Mar 05 02:51:36 UTC 2017 + + + boundaryCRC + 2dd40584 + + + boundaryCRCversion + 1 + + + customizationCRC + 6b2d7485 + + + customizationCRCversion + 6 + + + + + xilinx_vhdlsynthesiswrapper + VHDL Synthesis Wrapper + vhdlSource:vivado.xilinx.com:synthesis.wrapper + vhdl + + xilinx_vhdlsynthesiswrapper_view_fileset + + + + GENtimestamp + Sun Mar 05 02:51:36 UTC 2017 + + + boundaryCRC + 2dd40584 + + + boundaryCRCversion + 1 + + + customizationCRC + 6b2d7485 + + + customizationCRCversion + 6 + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset + + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + GENtimestamp + Fri Feb 24 23:58:24 UTC 2017 + + + boundaryCRC + 2dd40584 + + + boundaryCRCversion + 1 + + + customizationCRC + 73d13cc3 + + + customizationCRCversion + 6 + + + + + xilinx_vhdlsimulationwrapper + VHDL Simulation Wrapper + vhdlSource:vivado.xilinx.com:simulation.wrapper + vhdl + + xilinx_vhdlsimulationwrapper_view_fileset + + + + GENtimestamp + Sun Mar 05 02:51:36 UTC 2017 + + + boundaryCRC + 2dd40584 + + + boundaryCRCversion + 1 + + + customizationCRC + 73d13cc3 + + + customizationCRCversion + 6 + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Sun Mar 05 02:56:19 UTC 2017 + + + boundaryCRC + 2dd40584 + + + boundaryCRCversion + 1 + + + customizationCRC + 6b2d7485 + + + customizationCRCversion + 6 + + + + + + + clk + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + clken + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + s_axi_aclk + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + true + + + + + + s_axi_aclken + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + true + + + + + + det_clken + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + true + + + + + + gen_clken + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + false + + + + + + intc_if + + out + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + true + + + + + + field_id_in + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + hsync_in + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + true + + + + + + hblank_in + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + vsync_in + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + true + + + + + + vblank_in + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + active_video_in + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + true + + + + + + active_chroma_in + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + field_id_out + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + false + + + + + + hsync_out + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + false + + + + + + hblank_out + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + false + + + + + + vsync_out + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + false + + + + + + vblank_out + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + false + + + + + + active_video_out + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + false + + + + + + active_chroma_out + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + false + + + + + + resetn + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + true + + + + + + s_axi_awaddr + + in + + 8 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + true + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + true + + + + + + s_axi_awready + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + true + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + true + + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + true + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + true + + + + + + s_axi_wready + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + true + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + true + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + true + + + + + + s_axi_bready + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + true + + + + + + s_axi_araddr + + in + + 8 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + true + + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + true + + + + + + s_axi_arready + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + true + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + true + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + true + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + true + + + + + + s_axi_rready + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + true + + + + + + irq + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + true + + + + + + fsync_in + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + fsync_out + + out + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + false + + + + + + + + C_HAS_AXI4_LITE + 1 + + + C_HAS_INTC_IF + 1 + + + C_GEN_INTERLACED + 0 + + + C_GEN_HACTIVE_SIZE + 1280 + + + C_GEN_VACTIVE_SIZE + 720 + + + C_GEN_CPARITY + 0 + + + C_GEN_FIELDID_POLARITY + 1 + + + C_GEN_VBLANK_POLARITY + 1 + + + C_GEN_HBLANK_POLARITY + 1 + + + C_GEN_VSYNC_POLARITY + 1 + + + C_GEN_HSYNC_POLARITY + 1 + + + C_GEN_AVIDEO_POLARITY + 1 + + + C_GEN_ACHROMA_POLARITY + 1 + + + C_GEN_VIDEO_FORMAT + 2 + + + C_GEN_HFRAME_SIZE + 1650 + + + C_GEN_F0_VFRAME_SIZE + 750 + + + C_GEN_F1_VFRAME_SIZE + 750 + + + C_GEN_HSYNC_START + 1390 + + + C_GEN_HSYNC_END + 1430 + + + C_GEN_F0_VBLANK_HSTART + 1280 + + + C_GEN_F0_VBLANK_HEND + 1280 + + + C_GEN_F0_VSYNC_VSTART + 724 + + + C_GEN_F0_VSYNC_VEND + 729 + + + C_GEN_F0_VSYNC_HSTART + 1280 + + + C_GEN_F0_VSYNC_HEND + 1280 + + + C_GEN_F1_VBLANK_HSTART + 1280 + + + C_GEN_F1_VBLANK_HEND + 1280 + + + C_GEN_F1_VSYNC_VSTART + 724 + + + C_GEN_F1_VSYNC_VEND + 729 + + + C_GEN_F1_VSYNC_HSTART + 1280 + + + C_GEN_F1_VSYNC_HEND + 1280 + + + C_FSYNC_HSTART0 + 0 + + + C_FSYNC_VSTART0 + 0 + + + C_FSYNC_HSTART1 + 0 + + + C_FSYNC_VSTART1 + 0 + + + C_FSYNC_HSTART2 + 0 + + + C_FSYNC_VSTART2 + 0 + + + C_FSYNC_HSTART3 + 0 + + + C_FSYNC_VSTART3 + 0 + + + C_FSYNC_HSTART4 + 0 + + + C_FSYNC_VSTART4 + 0 + + + C_FSYNC_HSTART5 + 0 + + + C_FSYNC_VSTART5 + 0 + + + C_FSYNC_HSTART6 + 0 + + + C_FSYNC_VSTART6 + 0 + + + C_FSYNC_HSTART7 + 0 + + + C_FSYNC_VSTART7 + 0 + + + C_FSYNC_HSTART8 + 0 + + + C_FSYNC_VSTART8 + 0 + + + C_FSYNC_HSTART9 + 0 + + + C_FSYNC_VSTART9 + 0 + + + C_FSYNC_HSTART10 + 0 + + + C_FSYNC_VSTART10 + 0 + + + C_FSYNC_HSTART11 + 0 + + + C_FSYNC_VSTART11 + 0 + + + C_FSYNC_HSTART12 + 0 + + + C_FSYNC_VSTART12 + 0 + + + C_FSYNC_HSTART13 + 0 + + + C_FSYNC_VSTART13 + 0 + + + C_FSYNC_HSTART14 + 0 + + + C_FSYNC_VSTART14 + 0 + + + C_FSYNC_HSTART15 + 0 + + + C_FSYNC_VSTART15 + 0 + + + C_MAX_PIXELS + 4096 + + + C_MAX_LINES + 2048 + + + C_NUM_FSYNCS + 1 + + + C_INTERLACE_EN + 0 + + + C_GEN_AUTO_SWITCH + 0 + + + C_DETECT_EN + 1 + + + C_SYNC_EN + 0 + + + C_GENERATE_EN + 0 + + + C_DET_HSYNC_EN + 1 + + + C_DET_VSYNC_EN + 1 + + + C_DET_HBLANK_EN + 0 + + + C_DET_VBLANK_EN + 0 + + + C_DET_AVIDEO_EN + 1 + + + C_DET_ACHROMA_EN + 0 + + + C_GEN_HSYNC_EN + 1 + + + C_GEN_VSYNC_EN + 1 + + + C_GEN_HBLANK_EN + 1 + + + C_GEN_VBLANK_EN + 1 + + + C_GEN_AVIDEO_EN + 1 + + + C_GEN_ACHROMA_EN + 0 + + + C_GEN_FIELDID_EN + 0 + + + C_DET_FIELDID_EN + 0 + + + + + + choice_list_1f1af28c + 128 + 256 + 512 + 1024 + 2048 + 4096 + 8192 + 16384 + + + choice_list_3695f3b8 + Low + High + + + choice_list_48cc9c7b + 480p + 576p + 1080p + 352x288p + 352x576p + 480x576p + 544x576p + 704x576p + 704x480p + 640x480p + 800x600p + 1024x768p + 1280x1024p + 1600x1200p + 720p + Custom + + + choice_list_6e3ded9c + 0 + 1 + 2 + 3 + + + choice_list_7e3ed577 + RGB + YUV_444 + YUV_422 + YUV_420 + + + + + xilinx_vhdlsynthesis_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset + + ../../ipshared/0ba0/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd + vhdlSource + axi_lite_ipif_v3_0_4 + + + + + + + + + + + xilinx_vhdlsynthesis_view_fileset + + Arty_Z7_20_v_tc_1_0_clocks.xdc + xdc + USED_IN_implementation + USED_IN_synthesis + + processing_order + late + + + + ../../ipshared/d9f8/hdl/v_tc_v6_1_vh_rfs.vhd + vhdlSource + v_tc_v6_1_10 + + + + xilinx_synthesisconstraints_view_fileset + + Arty_Z7_20_v_tc_1_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + + xilinx_vhdlsynthesiswrapper_view_fileset + + synth/Arty_Z7_20_v_tc_1_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset + + ../../ipshared/0ba0/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + axi_lite_ipif_v3_0_4 + + + + + + + + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + ../../ipshared/d9f8/hdl/v_tc_v6_1_vh_rfs.vhd + vhdlSource + USED_IN_ipstatic + v_tc_v6_1_10 + + + + xilinx_vhdlsimulationwrapper_view_fileset + + sim/Arty_Z7_20_v_tc_1_0.vhd + vhdlSource + xil_defaultlib + + + + xilinx_externalfiles_view_fileset + + Arty_Z7_20_v_tc_1_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + Arty_Z7_20_v_tc_1_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Arty_Z7_20_v_tc_1_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Arty_Z7_20_v_tc_1_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Arty_Z7_20_v_tc_1_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + The Xilinx Video Timing Controller LogiCORE(TM) is a general purpose video timing generator and detector. Automatic detection of horizontal and vertical front and back porches, sync pulses and active video pixels is provided along with sync and blank pulse polarity detection. Horizontal and vertical blanking and sync pulses are generated including support for programmable pulse polarity. The core is programmable through a comprehensive register set allowing control of various timing generation parameters including horizontal and vertical front and back porch start, active video start, sync start and more. A comprehensive set of interrupt status bits is provided for processor monitoring. + + + Component_Name + Arty_Z7_20_v_tc_1_0 + + + + true + + + + + + C_FAMILY + virtex7 + + + + true + + + + + + HAS_AXI4_LITE + Enable AXI4-Lite Interface + true + + + + true + + + + + + HAS_INTC_IF + Enable INTC Interface + true + + + + true + + + + + + INTERLACE_EN + Interlaved Video Support + false + + + + true + + + + + + SYNC_EN + Enable Generator to Sync to Detector after Reset + false + + + + false + + + + + + max_clocks_per_line + Max Clocks Per Line + 4096 + + + + true + + + + + + max_lines_per_frame + Max Lines Per Frame + 2048 + + + + true + + + + + + VIDEO_MODE + Generator Video Format + 720p + + + + true + + + + + + FSYNC_HSTART0 + Frame Sync 0 Horizontal Start + 0 + + + + true + + + + + + FSYNC_VSTART0 + Frame Sync 0 Vertical Start + 0 + + + + true + + + + + + FSYNC_HSTART1 + Frame Sync 1 Horizontal Start + 0 + + + + false + + + + + + FSYNC_VSTART1 + Frame Sync 1 Vertical Start + 0 + + + + false + + + + + + FSYNC_HSTART2 + Frame Sync 2 Horizontal Start + 0 + + + + false + + + + + + FSYNC_VSTART2 + Frame Sync 2 Vertical Start + 0 + + + + false + + + + + + FSYNC_HSTART3 + Frame Sync 3 Horizontal Start + 0 + + + + false + + + + + + FSYNC_VSTART3 + Frame Sync 3 Vertical Start + 0 + + + + false + + + + + + FSYNC_HSTART4 + Frame Sync 4 Horizontal Start + 0 + + + + false + + + + + + FSYNC_VSTART4 + Frame Sync 4 Vertical Start + 0 + + + + false + + + + + + FSYNC_HSTART5 + Frame Sync 5 Horizontal Start + 0 + + + + false + + + + + + FSYNC_VSTART5 + Frame Sync 5 Vertical Start + 0 + + + + false + + + + + + FSYNC_HSTART6 + Frame Sync 6 Horizontal Start + 0 + + + + false + + + + + + FSYNC_VSTART6 + Frame Sync 6 Vertical Start + 0 + + + + false + + + + + + FSYNC_HSTART7 + Frame Sync 7 Horizontal Start + 0 + + + + false + + + + + + FSYNC_VSTART7 + Frame Sync 7 Vertical Start + 0 + + + + false + + + + + + FSYNC_HSTART8 + Frame Sync 8 Horizontal Start + 0 + + + + false + + + + + + FSYNC_VSTART8 + Frame Sync 8 Vertical Start + 0 + + + + false + + + + + + FSYNC_HSTART9 + Frame Sync 9 Horizontal Start + 0 + + + + false + + + + + + FSYNC_VSTART9 + Frame Sync 9 Vertical Start + 0 + + + + false + + + + + + FSYNC_HSTART10 + Frame Sync 10 Horizontal Start + 0 + + + + false + + + + + + FSYNC_VSTART10 + Frame Sync 10 Vertical Start + 0 + + + + false + + + + + + FSYNC_HSTART11 + Frame Sync 11 Horizontal Start + 0 + + + + false + + + + + + FSYNC_VSTART11 + Frame Sync 11 Vertical Start + 0 + + + + false + + + + + + FSYNC_HSTART12 + Frame Sync 12 Horizontal Start + 0 + + + + false + + + + + + FSYNC_VSTART12 + Frame Sync 12 Vertical Start + 0 + + + + false + + + + + + FSYNC_HSTART13 + Frame Sync 13 Horizontal Start + 0 + + + + false + + + + + + FSYNC_VSTART13 + Frame Sync 13 Vertical Start + 0 + + + + false + + + + + + FSYNC_HSTART14 + Frame Sync 14 Horizontal Start + 0 + + + + false + + + + + + FSYNC_VSTART14 + Frame Sync 14 Vertical Start + 0 + + + + false + + + + + + FSYNC_HSTART15 + Frame Sync 15 Horizontal Start + 0 + + + + false + + + + + + FSYNC_VSTART15 + Frame Sync 15 Vertical Start + 0 + + + + false + + + + + + GEN_F0_VSYNC_VSTART + Generator Vsync Vertical Start + 724 + + + + false + + + + + + GEN_F1_VSYNC_VSTART + Generator Field 1 Vsync Vertical Start + 724 + + + + false + + + + + + GEN_HACTIVE_SIZE + Generator Horizontal Active Size + 1280 + + + + false + + + + + + GEN_HSYNC_END + Generator Horizontal Sync End + 1430 + + + + false + + + + + + GEN_HFRAME_SIZE + Generaotr Horizontal Frame Size + 1650 + + + + false + + + + + + GEN_F0_VSYNC_HSTART + Generator Vsync Horizotnal Start + 1280 + + + + false + + + + + + GEN_F1_VSYNC_HSTART + Generator Field 1 Vsync Horizotnal Start + 1280 + + + + false + + + + + + GEN_F0_VSYNC_HEND + Generator Vsync Horizontal End + 1280 + + + + false + + + + + + GEN_F1_VSYNC_HEND + Generator Field 1 Vsync Horizontal End + 1280 + + + + false + + + + + + GEN_F0_VFRAME_SIZE + Generator Vertical Frame Size + 750 + + + + false + + + + + + GEN_F1_VFRAME_SIZE + Generator Field 1 Vertical Frame Size + 750 + + + + false + + + + + + GEN_F0_VSYNC_VEND + Generator Vsync Veritical End + 729 + + + + false + + + + + + GEN_F1_VSYNC_VEND + Generator Field 1 Vsync Veritical End + 729 + + + + false + + + + + + GEN_F0_VBLANK_HEND + Generator Vblank Horizontal End + 1280 + + + + false + + + + + + GEN_F1_VBLANK_HEND + Generator Field 1 Vblank Horizontal End + 1280 + + + + false + + + + + + GEN_HSYNC_START + Generator Hsync Start + 1390 + + + + false + + + + + + GEN_VACTIVE_SIZE + Generator Vertical Active Size + 720 + + + + false + + + + + + GEN_F0_VBLANK_HSTART + Generator Vblank Horizontal Start + 1280 + + + + false + + + + + + GEN_F1_VBLANK_HSTART + Generator Field 1 Vblank Horizontal Start + 1280 + + + + false + + + + + + GEN_ACHROMA_POLARITY + Generator Active Chroma Polarity + High + + + + false + + + + + + GEN_HSYNC_POLARITY + Generator Hsync Polarity + High + + + + true + + + + + + GEN_VSYNC_POLARITY + Generator Vsync Polarity + High + + + + true + + + + + + GEN_HBLANK_POLARITY + Generator Hblank Polarity + High + + + + true + + + + + + GEN_AVIDEO_POLARITY + Generator Active Video Polarity + High + + + + true + + + + + + GEN_VBLANK_POLARITY + Generator Vblank Polarity + High + + + + true + + + + + + GEN_FIELDID_POLARITY + Generator Field ID Polarity + High + + + + false + + + + + + GEN_INTERLACED + Generate Interlaced + false + + + + false + + + + + + GEN_CPARITY + Generator Chroma Parity + 0 + + + + true + + + + + + GEN_VIDEO_FORMAT + Generator Video Format + RGB + + + + true + + + + + + horizontal_sync_generation + Horizontal Sync Generation + true + + + + false + + + + + + enable_detection + Enable Detection + true + + + + false + + + + + + vertical_blank_generation + Vertical Blank Generation + true + + + + false + + + + + + GEN_FIELDID_EN + Field ID Generation + false + + + + false + + + + + + horizontal_blank_detection + Horizontal Blank Detection + false + + + + true + + + + + + active_chroma_detection + Active Chroma Detection + false + + + + true + + + + + + horizontal_sync_detection + Horizontal Sync Detection + true + + + + true + + + + + + enable_generation + Enable Generation + false + + + + true + + + + + + auto_generation_mode + Auto Generation Mode + false + + + + false + + + + + + vertical_sync_generation + Vertical Sync Generation + true + + + + false + + + + + + active_chroma_generation + Active Chroma Generation + false + + + + false + + + + + + DET_FIELDID_EN + Field ID Detection + false + + + + false + + + + + + vertical_blank_detection + Vertical Blank Detection + false + + + + true + + + + + + active_video_generation + Active Video Generation + true + + + + false + + + + + + vertical_sync_detection + Vertical Sync Detection + true + + + + true + + + + + + horizontal_blank_generation + Horizontal Blank Generation + true + + + + false + + + + + + active_video_detection + Active Video Detection + true + + + + true + + + + + + frame_syncs + Frame Syncs + 1 + + + + true + + + + + + + + Video Timing Controller + 10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2016.4 + + + + + + + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0_clocks.xdc b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0_clocks.xdc new file mode 100644 index 0000000..e25526b --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0_clocks.xdc @@ -0,0 +1,7 @@ + + set video_clk [get_clocks -of [get_ports clk]] + set axilite_clk [get_clocks -of [get_ports s_axi_aclk]] + + set_max_delay -from $video_clk -to [all_registers -clock $axilite_clk] -datapath_only [get_property -min PERIOD $video_clk] + set_max_delay -from $axilite_clk -to [all_registers -clock $video_clk] -datapath_only [get_property -min PERIOD $axilite_clk] + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0_ooc.xdc b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0_ooc.xdc new file mode 100644 index 0000000..b67a996 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0_ooc.xdc @@ -0,0 +1,59 @@ +# (c) Copyright 2012-2017 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +# DO NOT MODIFY THIS FILE. +# ######################################################### +# +# This XDC is used only in OOC mode for synthesis, implementation +# +# ######################################################### + + +create_clock -period 10 -name clk [get_ports clk] + +create_clock -period 10 -name s_axi_aclk [get_ports s_axi_aclk] + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0_sim_netlist.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0_sim_netlist.v new file mode 100644 index 0000000..99a358f --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0_sim_netlist.v @@ -0,0 +1,49215 @@ +// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +// Date : Sat Mar 04 18:56:16 2017 +// Host : WK73 running 64-bit Service Pack 1 (build 7601) +// Command : write_verilog -force -mode funcsim +// c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0_sim_netlist.v +// Design : Arty_Z7_20_v_tc_1_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg400-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "Arty_Z7_20_v_tc_1_0,v_tc,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "v_tc,Vivado 2016.4" *) +(* NotValidForBitStream *) +module Arty_Z7_20_v_tc_1_0 + (clk, + clken, + s_axi_aclk, + s_axi_aclken, + det_clken, + intc_if, + hsync_in, + vsync_in, + active_video_in, + resetn, + s_axi_aresetn, + s_axi_awaddr, + s_axi_awvalid, + s_axi_awready, + s_axi_wdata, + s_axi_wstrb, + s_axi_wvalid, + s_axi_wready, + s_axi_bresp, + s_axi_bvalid, + s_axi_bready, + s_axi_araddr, + s_axi_arvalid, + s_axi_arready, + s_axi_rdata, + s_axi_rresp, + s_axi_rvalid, + s_axi_rready, + irq); + (* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) input clk; + (* x_interface_info = "xilinx.com:signal:clockenable:1.0 clken_intf CE" *) input clken; + (* x_interface_info = "xilinx.com:signal:clock:1.0 s_axi_aclk_intf CLK" *) input s_axi_aclk; + (* x_interface_info = "xilinx.com:signal:clockenable:1.0 s_axi_aclken_intf CE" *) input s_axi_aclken; + input det_clken; + output [31:0]intc_if; + (* x_interface_info = "xilinx.com:interface:video_timing:2.0 vtiming_in HSYNC" *) input hsync_in; + (* x_interface_info = "xilinx.com:interface:video_timing:2.0 vtiming_in VSYNC" *) input vsync_in; + (* x_interface_info = "xilinx.com:interface:video_timing:2.0 vtiming_in ACTIVE_VIDEO" *) input active_video_in; + (* x_interface_info = "xilinx.com:signal:reset:1.0 resetn_intf RST" *) input resetn; + (* x_interface_info = "xilinx.com:signal:reset:1.0 s_axi_aresetn_intf RST" *) input s_axi_aresetn; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 ctrl AWADDR" *) input [8:0]s_axi_awaddr; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 ctrl AWVALID" *) input s_axi_awvalid; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 ctrl AWREADY" *) output s_axi_awready; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 ctrl WDATA" *) input [31:0]s_axi_wdata; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 ctrl WSTRB" *) input [3:0]s_axi_wstrb; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 ctrl WVALID" *) input s_axi_wvalid; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 ctrl WREADY" *) output s_axi_wready; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 ctrl BRESP" *) output [1:0]s_axi_bresp; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 ctrl BVALID" *) output s_axi_bvalid; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 ctrl BREADY" *) input s_axi_bready; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 ctrl ARADDR" *) input [8:0]s_axi_araddr; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 ctrl ARVALID" *) input s_axi_arvalid; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 ctrl ARREADY" *) output s_axi_arready; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 ctrl RDATA" *) output [31:0]s_axi_rdata; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 ctrl RRESP" *) output [1:0]s_axi_rresp; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 ctrl RVALID" *) output s_axi_rvalid; + (* x_interface_info = "xilinx.com:interface:aximm:1.0 ctrl RREADY" *) input s_axi_rready; + (* x_interface_info = "xilinx.com:signal:interrupt:1.0 IRQ INTERRUPT" *) output irq; + + wire active_video_in; + wire clk; + wire clken; + wire det_clken; + wire hsync_in; + wire [31:0]intc_if; + wire irq; + wire resetn; + wire s_axi_aclk; + wire s_axi_aclken; + wire [8:0]s_axi_araddr; + wire s_axi_aresetn; + wire s_axi_arready; + wire s_axi_arvalid; + wire [8:0]s_axi_awaddr; + wire s_axi_awready; + wire s_axi_awvalid; + wire s_axi_bready; + wire [1:0]s_axi_bresp; + wire s_axi_bvalid; + wire [31:0]s_axi_rdata; + wire s_axi_rready; + wire [1:0]s_axi_rresp; + wire s_axi_rvalid; + wire [31:0]s_axi_wdata; + wire s_axi_wready; + wire [3:0]s_axi_wstrb; + wire s_axi_wvalid; + wire vsync_in; + wire NLW_U0_active_chroma_out_UNCONNECTED; + wire NLW_U0_active_video_out_UNCONNECTED; + wire NLW_U0_field_id_out_UNCONNECTED; + wire NLW_U0_hblank_out_UNCONNECTED; + wire NLW_U0_hsync_out_UNCONNECTED; + wire NLW_U0_vblank_out_UNCONNECTED; + wire NLW_U0_vsync_out_UNCONNECTED; + wire [0:0]NLW_U0_fsync_out_UNCONNECTED; + + (* C_CONTROL = "0" *) + (* C_DETECT_EN = "1" *) + (* C_DET_ACHROMA_EN = "0" *) + (* C_DET_AVIDEO_EN = "1" *) + (* C_DET_FIELDID_EN = "0" *) + (* C_DET_HBLANK_EN = "0" *) + (* C_DET_HSYNC_EN = "1" *) + (* C_DET_VBLANK_EN = "0" *) + (* C_DET_VSYNC_EN = "1" *) + (* C_FAMILY = "virtex5" *) + (* C_FSYNC_HSTART0 = "0" *) + (* C_FSYNC_HSTART1 = "0" *) + (* C_FSYNC_HSTART10 = "0" *) + (* C_FSYNC_HSTART11 = "0" *) + (* C_FSYNC_HSTART12 = "0" *) + (* C_FSYNC_HSTART13 = "0" *) + (* C_FSYNC_HSTART14 = "0" *) + (* C_FSYNC_HSTART15 = "0" *) + (* C_FSYNC_HSTART2 = "0" *) + (* C_FSYNC_HSTART3 = "0" *) + (* C_FSYNC_HSTART4 = "0" *) + (* C_FSYNC_HSTART5 = "0" *) + (* C_FSYNC_HSTART6 = "0" *) + (* C_FSYNC_HSTART7 = "0" *) + (* C_FSYNC_HSTART8 = "0" *) + (* C_FSYNC_HSTART9 = "0" *) + (* C_FSYNC_VSTART0 = "0" *) + (* C_FSYNC_VSTART1 = "0" *) + (* C_FSYNC_VSTART10 = "0" *) + (* C_FSYNC_VSTART11 = "0" *) + (* C_FSYNC_VSTART12 = "0" *) + (* C_FSYNC_VSTART13 = "0" *) + (* C_FSYNC_VSTART14 = "0" *) + (* C_FSYNC_VSTART15 = "0" *) + (* C_FSYNC_VSTART2 = "0" *) + (* C_FSYNC_VSTART3 = "0" *) + (* C_FSYNC_VSTART4 = "0" *) + (* C_FSYNC_VSTART5 = "0" *) + (* C_FSYNC_VSTART6 = "0" *) + (* C_FSYNC_VSTART7 = "0" *) + (* C_FSYNC_VSTART8 = "0" *) + (* C_FSYNC_VSTART9 = "0" *) + (* C_GENERATE_EN = "0" *) + (* C_GEN_ACHROMA_EN = "0" *) + (* C_GEN_ACHROMA_POLARITY = "1" *) + (* C_GEN_AUTO_SWITCH = "0" *) + (* C_GEN_AVIDEO_EN = "1" *) + (* C_GEN_AVIDEO_POLARITY = "1" *) + (* C_GEN_CPARITY = "0" *) + (* C_GEN_F0_VBLANK_HEND = "1280" *) + (* C_GEN_F0_VBLANK_HSTART = "1280" *) + (* C_GEN_F0_VFRAME_SIZE = "750" *) + (* C_GEN_F0_VSYNC_HEND = "1280" *) + (* C_GEN_F0_VSYNC_HSTART = "1280" *) + (* C_GEN_F0_VSYNC_VEND = "729" *) + (* C_GEN_F0_VSYNC_VSTART = "724" *) + (* C_GEN_F1_VBLANK_HEND = "1280" *) + (* C_GEN_F1_VBLANK_HSTART = "1280" *) + (* C_GEN_F1_VFRAME_SIZE = "750" *) + (* C_GEN_F1_VSYNC_HEND = "1280" *) + (* C_GEN_F1_VSYNC_HSTART = "1280" *) + (* C_GEN_F1_VSYNC_VEND = "729" *) + (* C_GEN_F1_VSYNC_VSTART = "724" *) + (* C_GEN_FIELDID_EN = "0" *) + (* C_GEN_FIELDID_POLARITY = "1" *) + (* C_GEN_HACTIVE_SIZE = "1280" *) + (* C_GEN_HBLANK_EN = "1" *) + (* C_GEN_HBLANK_POLARITY = "1" *) + (* C_GEN_HFRAME_SIZE = "1650" *) + (* C_GEN_HSYNC_EN = "1" *) + (* C_GEN_HSYNC_END = "1430" *) + (* C_GEN_HSYNC_POLARITY = "1" *) + (* C_GEN_HSYNC_START = "1390" *) + (* C_GEN_INTERLACED = "0" *) + (* C_GEN_VACTIVE_SIZE = "720" *) + (* C_GEN_VBLANK_EN = "1" *) + (* C_GEN_VBLANK_POLARITY = "1" *) + (* C_GEN_VIDEO_FORMAT = "2" *) + (* C_GEN_VSYNC_EN = "1" *) + (* C_GEN_VSYNC_POLARITY = "1" *) + (* C_HAS_AXI4_LITE = "1" *) + (* C_HAS_INTC_IF = "1" *) + (* C_INTERLACE_EN = "0" *) + (* C_IRQEN = "0" *) + (* C_LINE_DELAY = "0" *) + (* C_MAX_LINES = "2048" *) + (* C_MAX_PIXELS = "4096" *) + (* C_NUM_FSYNCS = "1" *) + (* C_PIXEL_DELAY = "0" *) + (* C_SYNC_EN = "0" *) + (* C_S_AXI_ADDR_WIDTH = "9" *) + (* C_S_AXI_CLK_FREQ_HZ = "100000000" *) + (* C_S_AXI_DATA_WIDTH = "32" *) + (* downgradeipidentifiedwarnings = "yes" *) + Arty_Z7_20_v_tc_1_0_v_tc U0 + (.active_chroma_in(1'b0), + .active_chroma_out(NLW_U0_active_chroma_out_UNCONNECTED), + .active_video_in(active_video_in), + .active_video_out(NLW_U0_active_video_out_UNCONNECTED), + .clk(clk), + .clken(clken), + .det_clken(det_clken), + .field_id_in(1'b0), + .field_id_out(NLW_U0_field_id_out_UNCONNECTED), + .fsync_in(1'b0), + .fsync_out(NLW_U0_fsync_out_UNCONNECTED[0]), + .gen_clken(1'b1), + .hblank_in(1'b0), + .hblank_out(NLW_U0_hblank_out_UNCONNECTED), + .hsync_in(hsync_in), + .hsync_out(NLW_U0_hsync_out_UNCONNECTED), + .intc_if(intc_if), + .irq(irq), + .resetn(resetn), + .s_axi_aclk(s_axi_aclk), + .s_axi_aclken(s_axi_aclken), + .s_axi_araddr(s_axi_araddr), + .s_axi_aresetn(s_axi_aresetn), + .s_axi_arready(s_axi_arready), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awready(s_axi_awready), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_bready(s_axi_bready), + .s_axi_bresp(s_axi_bresp), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_rdata(s_axi_rdata), + .s_axi_rready(s_axi_rready), + .s_axi_rresp(s_axi_rresp), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_wdata(s_axi_wdata), + .s_axi_wready(s_axi_wready), + .s_axi_wstrb(s_axi_wstrb), + .s_axi_wvalid(s_axi_wvalid), + .vblank_in(1'b0), + .vblank_out(NLW_U0_vblank_out_UNCONNECTED), + .vsync_in(vsync_in), + .vsync_out(NLW_U0_vsync_out_UNCONNECTED)); +endmodule + +(* ORIG_REF_NAME = "address_decoder" *) +module Arty_Z7_20_v_tc_1_0_address_decoder + (D, + s_axi_arready, + s_axi_wready, + aclk, + ipif_RdAck, + is_read, + ipif_WrAck, + is_write_reg, + Q, + aresetn, + start2_reg, + \bus2ip_addr_i_reg[8] ); + output [1:0]D; + output s_axi_arready; + output s_axi_wready; + input aclk; + input ipif_RdAck; + input is_read; + input ipif_WrAck; + input is_write_reg; + input [9:0]Q; + input aresetn; + input start2_reg; + input [1:0]\bus2ip_addr_i_reg[8] ; + + wire [1:0]D; + wire \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ; + wire \MEM_DECODE_GEN[0].cs_out_i[0]_i_2_n_0 ; + wire \MEM_DECODE_GEN[1].cs_out_i[1]_i_1_n_0 ; + wire [9:0]Q; + wire aclk; + wire aresetn; + wire [1:0]\bus2ip_addr_i_reg[8] ; + wire ipif_RdAck; + wire ipif_WrAck; + wire is_read; + wire is_write_reg; + wire s_axi_arready; + wire s_axi_wready; + wire s_axi_wready_INST_0_i_1_n_0; + wire s_axi_wready_INST_0_i_2_n_0; + wire start2_reg; + + LUT4 #( + .INIT(16'h0008)) + \MEM_DECODE_GEN[0].cs_out_i[0]_i_1 + (.I0(\MEM_DECODE_GEN[0].cs_out_i[0]_i_2_n_0 ), + .I1(aresetn), + .I2(s_axi_arready), + .I3(s_axi_wready), + .O(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 )); + LUT4 #( + .INIT(16'h2F20)) + \MEM_DECODE_GEN[0].cs_out_i[0]_i_2 + (.I0(\bus2ip_addr_i_reg[8] [1]), + .I1(\bus2ip_addr_i_reg[8] [0]), + .I2(start2_reg), + .I3(D[1]), + .O(\MEM_DECODE_GEN[0].cs_out_i[0]_i_2_n_0 )); + FDRE \MEM_DECODE_GEN[0].cs_out_i_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ), + .Q(D[1]), + .R(1'b0)); + LUT6 #( + .INIT(64'h0000000000002E00)) + \MEM_DECODE_GEN[1].cs_out_i[1]_i_1 + (.I0(D[0]), + .I1(start2_reg), + .I2(\bus2ip_addr_i_reg[8] [1]), + .I3(aresetn), + .I4(s_axi_arready), + .I5(s_axi_wready), + .O(\MEM_DECODE_GEN[1].cs_out_i[1]_i_1_n_0 )); + FDRE \MEM_DECODE_GEN[1].cs_out_i_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\MEM_DECODE_GEN[1].cs_out_i[1]_i_1_n_0 ), + .Q(D[0]), + .R(1'b0)); + LUT4 #( + .INIT(16'hAAEA)) + s_axi_arready_INST_0 + (.I0(ipif_RdAck), + .I1(is_read), + .I2(s_axi_wready_INST_0_i_1_n_0), + .I3(s_axi_wready_INST_0_i_2_n_0), + .O(s_axi_arready)); + LUT4 #( + .INIT(16'hAAEA)) + s_axi_wready_INST_0 + (.I0(ipif_WrAck), + .I1(is_write_reg), + .I2(s_axi_wready_INST_0_i_1_n_0), + .I3(s_axi_wready_INST_0_i_2_n_0), + .O(s_axi_wready)); + LUT5 #( + .INIT(32'h00000001)) + s_axi_wready_INST_0_i_1 + (.I0(Q[8]), + .I1(Q[7]), + .I2(Q[4]), + .I3(Q[5]), + .I4(Q[6]), + .O(s_axi_wready_INST_0_i_1_n_0)); + LUT5 #( + .INIT(32'hFFFFFFFB)) + s_axi_wready_INST_0_i_2 + (.I0(Q[1]), + .I1(Q[9]), + .I2(Q[0]), + .I3(Q[3]), + .I4(Q[2]), + .O(s_axi_wready_INST_0_i_2_n_0)); +endmodule + +(* ORIG_REF_NAME = "axi_lite_ipif" *) +module Arty_Z7_20_v_tc_1_0_axi_lite_ipif + (p_0_in, + s_axi_rdata, + s_axi_rresp, + D, + s_axi_arready, + s_axi_rvalid, + s_axi_bvalid, + s_axi_wready, + s_axi_bresp, + s_axi_wvalid, + s_axi_awvalid, + s_axi_arvalid, + aclk, + out_data, + ipif_Error, + s_axi_araddr, + s_axi_awaddr, + aresetn, + s_axi_rready, + s_axi_bready, + ipif_RdAck, + ipif_WrAck); + output p_0_in; + output [31:0]s_axi_rdata; + output [0:0]s_axi_rresp; + output [11:0]D; + output s_axi_arready; + output s_axi_rvalid; + output s_axi_bvalid; + output s_axi_wready; + output [0:0]s_axi_bresp; + input s_axi_wvalid; + input s_axi_awvalid; + input s_axi_arvalid; + input aclk; + input [31:0]out_data; + input ipif_Error; + input [8:0]s_axi_araddr; + input [8:0]s_axi_awaddr; + input aresetn; + input s_axi_rready; + input s_axi_bready; + input ipif_RdAck; + input ipif_WrAck; + + wire [11:0]D; + wire aclk; + wire aresetn; + wire ipif_Error; + wire ipif_RdAck; + wire ipif_WrAck; + wire [31:0]out_data; + wire p_0_in; + wire [8:0]s_axi_araddr; + wire s_axi_arready; + wire s_axi_arvalid; + wire [8:0]s_axi_awaddr; + wire s_axi_awvalid; + wire s_axi_bready; + wire [0:0]s_axi_bresp; + wire s_axi_bvalid; + wire [31:0]s_axi_rdata; + wire s_axi_rready; + wire [0:0]s_axi_rresp; + wire s_axi_rvalid; + wire s_axi_wready; + wire s_axi_wvalid; + + Arty_Z7_20_v_tc_1_0_slave_attachment I_SLAVE_ATTACHMENT + (.D(D), + .aclk(aclk), + .aresetn(aresetn), + .ipif_Error(ipif_Error), + .ipif_RdAck(ipif_RdAck), + .ipif_WrAck(ipif_WrAck), + .out_data(out_data), + .p_0_in(p_0_in), + .s_axi_araddr(s_axi_araddr), + .s_axi_arready(s_axi_arready), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_bready(s_axi_bready), + .s_axi_bresp(s_axi_bresp), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_rdata(s_axi_rdata), + .s_axi_rready(s_axi_rready), + .s_axi_rresp(s_axi_rresp), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_wready(s_axi_wready), + .s_axi_wvalid(s_axi_wvalid)); +endmodule + +(* ORIG_REF_NAME = "slave_attachment" *) +module Arty_Z7_20_v_tc_1_0_slave_attachment + (p_0_in, + s_axi_rdata, + s_axi_rresp, + D, + s_axi_arready, + s_axi_rvalid, + s_axi_bvalid, + s_axi_wready, + s_axi_bresp, + s_axi_wvalid, + s_axi_awvalid, + s_axi_arvalid, + aclk, + out_data, + ipif_Error, + s_axi_araddr, + s_axi_awaddr, + aresetn, + s_axi_rready, + s_axi_bready, + ipif_RdAck, + ipif_WrAck); + output p_0_in; + output [31:0]s_axi_rdata; + output [0:0]s_axi_rresp; + output [11:0]D; + output s_axi_arready; + output s_axi_rvalid; + output s_axi_bvalid; + output s_axi_wready; + output [0:0]s_axi_bresp; + input s_axi_wvalid; + input s_axi_awvalid; + input s_axi_arvalid; + input aclk; + input [31:0]out_data; + input ipif_Error; + input [8:0]s_axi_araddr; + input [8:0]s_axi_awaddr; + input aresetn; + input s_axi_rready; + input s_axi_bready; + input ipif_RdAck; + input ipif_WrAck; + + wire [11:0]D; + wire \INCLUDE_DPHASE_TIMER.dpto_cnt[9]_i_3_n_0 ; + wire [9:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ; + wire aclk; + wire aresetn; + wire \bus2ip_addr_i[0]_i_1_n_0 ; + wire \bus2ip_addr_i[1]_i_1_n_0 ; + wire \bus2ip_addr_i[2]_i_1_n_0 ; + wire \bus2ip_addr_i[3]_i_1_n_0 ; + wire \bus2ip_addr_i[4]_i_1_n_0 ; + wire \bus2ip_addr_i[5]_i_1_n_0 ; + wire \bus2ip_addr_i[6]_i_1_n_0 ; + wire \bus2ip_addr_i[7]_i_1_n_0 ; + wire \bus2ip_addr_i[8]_i_1_n_0 ; + wire \bus2ip_addr_i[8]_i_2_n_0 ; + wire bus2ip_rnw_i06_out; + wire clear; + wire ipif_Error; + wire ipif_RdAck; + wire ipif_WrAck; + wire is_read; + wire is_read_i_1_n_0; + wire is_write; + wire is_write_i_1_n_0; + wire is_write_reg_n_0; + wire [31:0]out_data; + wire p_0_in; + wire [1:0]p_0_out; + wire [9:0]plusOp; + wire rst; + wire [8:0]s_axi_araddr; + wire s_axi_arready; + wire s_axi_arvalid; + wire [8:0]s_axi_awaddr; + wire s_axi_awvalid; + wire s_axi_bready; + wire [0:0]s_axi_bresp; + wire \s_axi_bresp_i[1]_i_1_n_0 ; + wire s_axi_bvalid; + wire s_axi_bvalid_i_i_1_n_0; + wire [31:0]s_axi_rdata; + wire \s_axi_rdata_i[31]_i_1_n_0 ; + wire s_axi_rready; + wire [0:0]s_axi_rresp; + wire s_axi_rvalid; + wire s_axi_rvalid_i_i_1_n_0; + wire s_axi_wready; + wire s_axi_wvalid; + wire start2; + wire start2_i_1_n_0; + wire [1:0]state; + wire state1__2; + wire \state[1]_i_3_n_0 ; + + LUT1 #( + .INIT(2'h1)) + \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1 + (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]), + .O(plusOp[0])); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT2 #( + .INIT(4'h6)) + \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1 + (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]), + .I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]), + .O(plusOp[1])); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h78)) + \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1 + (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]), + .I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]), + .I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]), + .O(plusOp[2])); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT4 #( + .INIT(16'h7F80)) + \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1 + (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]), + .I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]), + .I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]), + .I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]), + .O(plusOp[3])); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \INCLUDE_DPHASE_TIMER.dpto_cnt[4]_i_1 + (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]), + .I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]), + .I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]), + .I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]), + .I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [4]), + .O(plusOp[4])); + LUT6 #( + .INIT(64'h7FFFFFFF80000000)) + \INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_1 + (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]), + .I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]), + .I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]), + .I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]), + .I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [4]), + .I5(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [5]), + .O(plusOp[5])); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h6)) + \INCLUDE_DPHASE_TIMER.dpto_cnt[6]_i_1 + (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt[9]_i_3_n_0 ), + .I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [6]), + .O(plusOp[6])); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h78)) + \INCLUDE_DPHASE_TIMER.dpto_cnt[7]_i_1 + (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt[9]_i_3_n_0 ), + .I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [6]), + .I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [7]), + .O(plusOp[7])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT4 #( + .INIT(16'h7F80)) + \INCLUDE_DPHASE_TIMER.dpto_cnt[8]_i_1 + (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [6]), + .I1(\INCLUDE_DPHASE_TIMER.dpto_cnt[9]_i_3_n_0 ), + .I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [7]), + .I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [8]), + .O(plusOp[8])); + LUT2 #( + .INIT(4'h9)) + \INCLUDE_DPHASE_TIMER.dpto_cnt[9]_i_1 + (.I0(state[0]), + .I1(state[1]), + .O(clear)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \INCLUDE_DPHASE_TIMER.dpto_cnt[9]_i_2 + (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [7]), + .I1(\INCLUDE_DPHASE_TIMER.dpto_cnt[9]_i_3_n_0 ), + .I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [6]), + .I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [8]), + .I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [9]), + .O(plusOp[9])); + LUT6 #( + .INIT(64'h8000000000000000)) + \INCLUDE_DPHASE_TIMER.dpto_cnt[9]_i_3 + (.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [5]), + .I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]), + .I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]), + .I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]), + .I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]), + .I5(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [4]), + .O(\INCLUDE_DPHASE_TIMER.dpto_cnt[9]_i_3_n_0 )); + FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0] + (.C(aclk), + .CE(1'b1), + .D(plusOp[0]), + .Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]), + .R(clear)); + FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1] + (.C(aclk), + .CE(1'b1), + .D(plusOp[1]), + .Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]), + .R(clear)); + FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2] + (.C(aclk), + .CE(1'b1), + .D(plusOp[2]), + .Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]), + .R(clear)); + FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] + (.C(aclk), + .CE(1'b1), + .D(plusOp[3]), + .Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]), + .R(clear)); + FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[4] + (.C(aclk), + .CE(1'b1), + .D(plusOp[4]), + .Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [4]), + .R(clear)); + FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5] + (.C(aclk), + .CE(1'b1), + .D(plusOp[5]), + .Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [5]), + .R(clear)); + FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[6] + (.C(aclk), + .CE(1'b1), + .D(plusOp[6]), + .Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [6]), + .R(clear)); + FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[7] + (.C(aclk), + .CE(1'b1), + .D(plusOp[7]), + .Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [7]), + .R(clear)); + FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[8] + (.C(aclk), + .CE(1'b1), + .D(plusOp[8]), + .Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [8]), + .R(clear)); + FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[9] + (.C(aclk), + .CE(1'b1), + .D(plusOp[9]), + .Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [9]), + .R(clear)); + Arty_Z7_20_v_tc_1_0_address_decoder I_DECODER + (.D(D[10:9]), + .Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ), + .aclk(aclk), + .aresetn(aresetn), + .\bus2ip_addr_i_reg[8] (D[8:7]), + .ipif_RdAck(ipif_RdAck), + .ipif_WrAck(ipif_WrAck), + .is_read(is_read), + .is_write_reg(is_write_reg_n_0), + .s_axi_arready(s_axi_arready), + .s_axi_wready(s_axi_wready), + .start2_reg(start2)); + LUT5 #( + .INIT(32'hCCCACCCC)) + \bus2ip_addr_i[0]_i_1 + (.I0(s_axi_araddr[0]), + .I1(s_axi_awaddr[0]), + .I2(state[0]), + .I3(state[1]), + .I4(s_axi_arvalid), + .O(\bus2ip_addr_i[0]_i_1_n_0 )); + LUT5 #( + .INIT(32'hCCCACCCC)) + \bus2ip_addr_i[1]_i_1 + (.I0(s_axi_araddr[1]), + .I1(s_axi_awaddr[1]), + .I2(state[0]), + .I3(state[1]), + .I4(s_axi_arvalid), + .O(\bus2ip_addr_i[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'hCCCACCCC)) + \bus2ip_addr_i[2]_i_1 + (.I0(s_axi_araddr[2]), + .I1(s_axi_awaddr[2]), + .I2(state[0]), + .I3(state[1]), + .I4(s_axi_arvalid), + .O(\bus2ip_addr_i[2]_i_1_n_0 )); + LUT5 #( + .INIT(32'hCCCACCCC)) + \bus2ip_addr_i[3]_i_1 + (.I0(s_axi_araddr[3]), + .I1(s_axi_awaddr[3]), + .I2(state[0]), + .I3(state[1]), + .I4(s_axi_arvalid), + .O(\bus2ip_addr_i[3]_i_1_n_0 )); + LUT5 #( + .INIT(32'hCCCACCCC)) + \bus2ip_addr_i[4]_i_1 + (.I0(s_axi_araddr[4]), + .I1(s_axi_awaddr[4]), + .I2(state[0]), + .I3(state[1]), + .I4(s_axi_arvalid), + .O(\bus2ip_addr_i[4]_i_1_n_0 )); + LUT5 #( + .INIT(32'hCCCACCCC)) + \bus2ip_addr_i[5]_i_1 + (.I0(s_axi_araddr[5]), + .I1(s_axi_awaddr[5]), + .I2(state[0]), + .I3(state[1]), + .I4(s_axi_arvalid), + .O(\bus2ip_addr_i[5]_i_1_n_0 )); + LUT5 #( + .INIT(32'hCCCACCCC)) + \bus2ip_addr_i[6]_i_1 + (.I0(s_axi_araddr[6]), + .I1(s_axi_awaddr[6]), + .I2(state[0]), + .I3(state[1]), + .I4(s_axi_arvalid), + .O(\bus2ip_addr_i[6]_i_1_n_0 )); + LUT5 #( + .INIT(32'hCCCACCCC)) + \bus2ip_addr_i[7]_i_1 + (.I0(s_axi_araddr[7]), + .I1(s_axi_awaddr[7]), + .I2(state[0]), + .I3(state[1]), + .I4(s_axi_arvalid), + .O(\bus2ip_addr_i[7]_i_1_n_0 )); + LUT5 #( + .INIT(32'h000000EA)) + \bus2ip_addr_i[8]_i_1 + (.I0(s_axi_arvalid), + .I1(s_axi_awvalid), + .I2(s_axi_wvalid), + .I3(state[1]), + .I4(state[0]), + .O(\bus2ip_addr_i[8]_i_1_n_0 )); + LUT5 #( + .INIT(32'hCCCACCCC)) + \bus2ip_addr_i[8]_i_2 + (.I0(s_axi_araddr[8]), + .I1(s_axi_awaddr[8]), + .I2(state[0]), + .I3(state[1]), + .I4(s_axi_arvalid), + .O(\bus2ip_addr_i[8]_i_2_n_0 )); + FDRE \bus2ip_addr_i_reg[0] + (.C(aclk), + .CE(\bus2ip_addr_i[8]_i_1_n_0 ), + .D(\bus2ip_addr_i[0]_i_1_n_0 ), + .Q(D[0]), + .R(rst)); + FDRE \bus2ip_addr_i_reg[1] + (.C(aclk), + .CE(\bus2ip_addr_i[8]_i_1_n_0 ), + .D(\bus2ip_addr_i[1]_i_1_n_0 ), + .Q(D[1]), + .R(rst)); + FDRE \bus2ip_addr_i_reg[2] + (.C(aclk), + .CE(\bus2ip_addr_i[8]_i_1_n_0 ), + .D(\bus2ip_addr_i[2]_i_1_n_0 ), + .Q(D[2]), + .R(rst)); + FDRE \bus2ip_addr_i_reg[3] + (.C(aclk), + .CE(\bus2ip_addr_i[8]_i_1_n_0 ), + .D(\bus2ip_addr_i[3]_i_1_n_0 ), + .Q(D[3]), + .R(rst)); + FDRE \bus2ip_addr_i_reg[4] + (.C(aclk), + .CE(\bus2ip_addr_i[8]_i_1_n_0 ), + .D(\bus2ip_addr_i[4]_i_1_n_0 ), + .Q(D[4]), + .R(rst)); + FDRE \bus2ip_addr_i_reg[5] + (.C(aclk), + .CE(\bus2ip_addr_i[8]_i_1_n_0 ), + .D(\bus2ip_addr_i[5]_i_1_n_0 ), + .Q(D[5]), + .R(rst)); + FDRE \bus2ip_addr_i_reg[6] + (.C(aclk), + .CE(\bus2ip_addr_i[8]_i_1_n_0 ), + .D(\bus2ip_addr_i[6]_i_1_n_0 ), + .Q(D[6]), + .R(rst)); + FDRE \bus2ip_addr_i_reg[7] + (.C(aclk), + .CE(\bus2ip_addr_i[8]_i_1_n_0 ), + .D(\bus2ip_addr_i[7]_i_1_n_0 ), + .Q(D[7]), + .R(rst)); + FDRE \bus2ip_addr_i_reg[8] + (.C(aclk), + .CE(\bus2ip_addr_i[8]_i_1_n_0 ), + .D(\bus2ip_addr_i[8]_i_2_n_0 ), + .Q(D[8]), + .R(rst)); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT3 #( + .INIT(8'h10)) + bus2ip_rnw_i_i_1 + (.I0(state[0]), + .I1(state[1]), + .I2(s_axi_arvalid), + .O(bus2ip_rnw_i06_out)); + FDRE bus2ip_rnw_i_reg + (.C(aclk), + .CE(\bus2ip_addr_i[8]_i_1_n_0 ), + .D(bus2ip_rnw_i06_out), + .Q(D[11]), + .R(rst)); + LUT5 #( + .INIT(32'h3FFA000A)) + is_read_i_1 + (.I0(s_axi_arvalid), + .I1(state1__2), + .I2(state[0]), + .I3(state[1]), + .I4(is_read), + .O(is_read_i_1_n_0)); + FDRE is_read_reg + (.C(aclk), + .CE(1'b1), + .D(is_read_i_1_n_0), + .Q(is_read), + .R(rst)); + LUT6 #( + .INIT(64'h0040FFFF00400000)) + is_write_i_1 + (.I0(s_axi_arvalid), + .I1(s_axi_awvalid), + .I2(s_axi_wvalid), + .I3(state[1]), + .I4(is_write), + .I5(is_write_reg_n_0), + .O(is_write_i_1_n_0)); + LUT6 #( + .INIT(64'hF88800000000FFFF)) + is_write_i_2 + (.I0(s_axi_rvalid), + .I1(s_axi_rready), + .I2(s_axi_bvalid), + .I3(s_axi_bready), + .I4(state[0]), + .I5(state[1]), + .O(is_write)); + FDRE is_write_reg + (.C(aclk), + .CE(1'b1), + .D(is_write_i_1_n_0), + .Q(is_write_reg_n_0), + .R(rst)); + LUT1 #( + .INIT(2'h1)) + rst_i_1 + (.I0(aresetn), + .O(p_0_in)); + FDRE rst_reg + (.C(aclk), + .CE(1'b1), + .D(p_0_in), + .Q(rst), + .R(1'b0)); + LUT4 #( + .INIT(16'hFB08)) + \s_axi_bresp_i[1]_i_1 + (.I0(ipif_Error), + .I1(state[1]), + .I2(state[0]), + .I3(s_axi_bresp), + .O(\s_axi_bresp_i[1]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \s_axi_bresp_i_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\s_axi_bresp_i[1]_i_1_n_0 ), + .Q(s_axi_bresp), + .R(rst)); + LUT5 #( + .INIT(32'h08FF0808)) + s_axi_bvalid_i_i_1 + (.I0(s_axi_wready), + .I1(state[1]), + .I2(state[0]), + .I3(s_axi_bready), + .I4(s_axi_bvalid), + .O(s_axi_bvalid_i_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + s_axi_bvalid_i_reg + (.C(aclk), + .CE(1'b1), + .D(s_axi_bvalid_i_i_1_n_0), + .Q(s_axi_bvalid), + .R(rst)); + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata_i[31]_i_1 + (.I0(state[0]), + .I1(state[1]), + .O(\s_axi_rdata_i[31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[0] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[0]), + .Q(s_axi_rdata[0]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[10] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[10]), + .Q(s_axi_rdata[10]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[11] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[11]), + .Q(s_axi_rdata[11]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[12] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[12]), + .Q(s_axi_rdata[12]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[13] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[13]), + .Q(s_axi_rdata[13]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[14] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[14]), + .Q(s_axi_rdata[14]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[15] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[15]), + .Q(s_axi_rdata[15]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[16] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[16]), + .Q(s_axi_rdata[16]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[17] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[17]), + .Q(s_axi_rdata[17]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[18] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[18]), + .Q(s_axi_rdata[18]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[19] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[19]), + .Q(s_axi_rdata[19]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[1] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[1]), + .Q(s_axi_rdata[1]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[20] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[20]), + .Q(s_axi_rdata[20]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[21] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[21]), + .Q(s_axi_rdata[21]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[22] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[22]), + .Q(s_axi_rdata[22]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[23] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[23]), + .Q(s_axi_rdata[23]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[24] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[24]), + .Q(s_axi_rdata[24]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[25] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[25]), + .Q(s_axi_rdata[25]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[26] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[26]), + .Q(s_axi_rdata[26]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[27] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[27]), + .Q(s_axi_rdata[27]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[28] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[28]), + .Q(s_axi_rdata[28]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[29] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[29]), + .Q(s_axi_rdata[29]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[2] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[2]), + .Q(s_axi_rdata[2]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[30] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[30]), + .Q(s_axi_rdata[30]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[31] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[31]), + .Q(s_axi_rdata[31]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[3] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[3]), + .Q(s_axi_rdata[3]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[4] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[4]), + .Q(s_axi_rdata[4]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[5] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[5]), + .Q(s_axi_rdata[5]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[6] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[6]), + .Q(s_axi_rdata[6]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[7] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[7]), + .Q(s_axi_rdata[7]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[8] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[8]), + .Q(s_axi_rdata[8]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rdata_i_reg[9] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(out_data[9]), + .Q(s_axi_rdata[9]), + .R(rst)); + FDRE #( + .INIT(1'b0)) + \s_axi_rresp_i_reg[1] + (.C(aclk), + .CE(\s_axi_rdata_i[31]_i_1_n_0 ), + .D(ipif_Error), + .Q(s_axi_rresp), + .R(rst)); + LUT5 #( + .INIT(32'h08FF0808)) + s_axi_rvalid_i_i_1 + (.I0(s_axi_arready), + .I1(state[0]), + .I2(state[1]), + .I3(s_axi_rready), + .I4(s_axi_rvalid), + .O(s_axi_rvalid_i_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + s_axi_rvalid_i_reg + (.C(aclk), + .CE(1'b1), + .D(s_axi_rvalid_i_i_1_n_0), + .Q(s_axi_rvalid), + .R(rst)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT5 #( + .INIT(32'h000000F8)) + start2_i_1 + (.I0(s_axi_awvalid), + .I1(s_axi_wvalid), + .I2(s_axi_arvalid), + .I3(state[1]), + .I4(state[0]), + .O(start2_i_1_n_0)); + FDRE start2_reg + (.C(aclk), + .CE(1'b1), + .D(start2_i_1_n_0), + .Q(start2), + .R(rst)); + LUT5 #( + .INIT(32'h77FC44FC)) + \state[0]_i_1 + (.I0(state1__2), + .I1(state[0]), + .I2(s_axi_arvalid), + .I3(state[1]), + .I4(s_axi_wready), + .O(p_0_out[0])); + LUT5 #( + .INIT(32'h5FFC50FC)) + \state[1]_i_1 + (.I0(state1__2), + .I1(\state[1]_i_3_n_0 ), + .I2(state[1]), + .I3(state[0]), + .I4(s_axi_arready), + .O(p_0_out[1])); + LUT4 #( + .INIT(16'hF888)) + \state[1]_i_2 + (.I0(s_axi_bready), + .I1(s_axi_bvalid), + .I2(s_axi_rready), + .I3(s_axi_rvalid), + .O(state1__2)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT3 #( + .INIT(8'h08)) + \state[1]_i_3 + (.I0(s_axi_wvalid), + .I1(s_axi_awvalid), + .I2(s_axi_arvalid), + .O(\state[1]_i_3_n_0 )); + FDRE \state_reg[0] + (.C(aclk), + .CE(1'b1), + .D(p_0_out[0]), + .Q(state[0]), + .R(rst)); + FDRE \state_reg[1] + (.C(aclk), + .CE(1'b1), + .D(p_0_out[1]), + .Q(state[1]), + .R(rst)); +endmodule + +(* ORIG_REF_NAME = "mux_tree" *) +module Arty_Z7_20_v_tc_1_0_mux_tree + (\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] , + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 , + genr_data, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][31]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][30]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][29]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][28]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][27]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][26]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][25]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][24]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][23]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][22]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][21]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][20]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][19]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][18]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][17]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][16]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][15]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][14]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][13]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][12]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][11]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][10]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][9]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][8]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][7]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][6]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][5]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][4]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][3]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][2]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][1]_0 , + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][0]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][31]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][30]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][29]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][28]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][27]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][26]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][25]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][24]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][23]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][22]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][21]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][20]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][19]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][18]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][17]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][16]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][15]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][14]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][13]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][12]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][11]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][10]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][9]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][8]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][7]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][6]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][5]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][4]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][3]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][2]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][1]_0 , + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][0]_0 , + \data_sync_reg[2][34] , + vid_aclk, + ipif_Addr, + \data_sync_reg[2][34]_0 , + \time_status_regs[28] , + Q, + \data_sync_reg[2][34]_1 , + \data_sync_reg[2][34]_2 , + \data_sync_reg[2][34]_3 , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][28] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][27] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][26] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][25] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][24] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][23] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][22] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][21] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][20] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][19] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][18] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][17] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][16] , + \data_sync_reg[2][34]_4 , + \data_sync_reg[2][34]_5 , + \data_sync_reg[2][34]_6 , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][12] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][11] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][10] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][9] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][8] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][7] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][6] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][5] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][4] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][3] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][2] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][1] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][0] , + \data_sync_reg[2][34]_7 , + \data_sync_reg[2][34]_8 , + \data_sync_reg[2][34]_9 , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][27] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][26] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][25] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][24] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][23] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][22] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][21] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][20] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][19] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][18] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][17] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][16] , + \data_sync_reg[2][34]_10 , + \data_sync_reg[2][34]_11 , + \data_sync_reg[2][34]_12 , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][12] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][11] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][10] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][9] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][8] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][7] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][6] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][5] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][4] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][3] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][2] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][1] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][0] , + \data_sync_reg[2][34]_13 , + \data_sync_reg[2][34]_14 , + \data_sync_reg[2][34]_15 , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][27] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][26] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][25] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][24] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][23] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][22] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][21] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][20] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][19] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][18] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][17] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][16] , + \data_sync_reg[2][34]_16 , + \data_sync_reg[2][34]_17 , + \data_sync_reg[2][34]_18 , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][12] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][11] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][10] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][9] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][8] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][7] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][6] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][5] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][4] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][3] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][2] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][1] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][0] , + \data_sync_reg[2][34]_19 , + \data_sync_reg[2][34]_20 , + \data_sync_reg[2][34]_21 , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][27] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][26] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][25] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][24] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][23] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][22] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][21] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][20] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][19] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][18] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][17] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][16] , + \data_sync_reg[2][34]_22 , + \data_sync_reg[2][34]_23 , + \data_sync_reg[2][34]_24 , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][12] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][11] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][10] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][9] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][8] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][7] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][6] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][5] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][4] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][3] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][2] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][1] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][0] , + \data_sync_reg[2][34]_25 , + \data_sync_reg[2][34]_26 , + \data_sync_reg[2][34]_27 , + \data_sync_reg[2][34]_28 , + \data_sync_reg[2][34]_29 , + \data_sync_reg[2][34]_30 , + \data_sync_reg[2][34]_31 , + \data_sync_reg[2][34]_32 , + \data_sync_reg[2][34]_33 , + \data_sync_reg[2][34]_34 , + \data_sync_reg[2][34]_35 , + \data_sync_reg[2][34]_36 , + \data_sync_reg[2][34]_37 , + \data_sync_reg[2][34]_38 , + \data_sync_reg[2][34]_39 , + \data_sync_reg[2][34]_40 , + \data_sync_reg[2][34]_41 , + \data_sync_reg[2][34]_42 , + \data_sync_reg[2][34]_43 , + \data_sync_reg[2][34]_44 , + \data_sync_reg[2][34]_45 , + \data_sync_reg[2][34]_46 , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][8] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][7] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][5] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][4] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][3] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][2] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][1] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][0] , + \data_sync_reg[2][34]_47 , + \data_sync_reg[2][34]_48 , + \data_sync_reg[2][34]_49 , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][27] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][26] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][25] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][24] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][23] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][22] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][21] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][20] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][19] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][18] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][17] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][16] , + \data_sync_reg[2][34]_50 , + \data_sync_reg[2][34]_51 , + \data_sync_reg[2][34]_52 , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][12] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][11] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][10] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][9] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][8] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][7] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][6] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][5] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][4] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][3] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][2] , + \intr_status_int_reg[12] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][0] , + \data_sync_reg[2][34]_53 , + \data_sync_reg[2][34]_54 , + \data_sync_reg[2][34]_55 , + \data_sync_reg[2][34]_56 , + \data_sync_reg[2][34]_57 , + \data_sync_reg[2][34]_58 , + \data_sync_reg[2][34]_59 , + \data_sync_reg[2][34]_60 , + \data_sync_reg[2][34]_61 , + \data_sync_reg[2][34]_62 , + \data_sync_reg[2][34]_63 , + \data_sync_reg[2][34]_64 , + \data_sync_reg[2][34]_65 , + \data_sync_reg[2][34]_66 , + \data_sync_reg[2][34]_67 , + \data_sync_reg[2][34]_68 , + \data_sync_reg[2][34]_69 , + \data_sync_reg[2][34]_70 , + \data_sync_reg[2][34]_71 , + \data_sync_reg[2][34]_72 , + \data_sync_reg[2][34]_73 , + \data_sync_reg[2][34]_74 , + \data_sync_reg[2][34]_75 , + \data_sync_reg[2][34]_76 , + \data_sync_reg[2][34]_77 , + \data_sync_reg[2][34]_78 , + \data_sync_reg[2][34]_79 , + \data_sync_reg[2][34]_80 , + \data_sync_reg[2][34]_81 , + \data_sync_reg[2][34]_82 , + \data_sync_reg[2][34]_83 , + \data_sync_reg[2][34]_84 , + \data_sync_reg[2][34]_85 , + \data_sync_reg[2][34]_86 , + \data_sync_reg[2][34]_87 , + \data_sync_reg[2][34]_88 , + \data_sync_reg[2][34]_89 , + \data_sync_reg[2][34]_90 , + \data_sync_reg[2][34]_91 , + \data_sync_reg[2][34]_92 , + \data_sync_reg[2][34]_93 , + \data_sync_reg[2][34]_94 , + \data_sync_reg[2][34]_95 , + \data_sync_reg[2][34]_96 , + \data_sync_reg[2][34]_97 , + \data_sync_reg[2][34]_98 , + \data_sync_reg[2][34]_99 , + \data_sync_reg[2][34]_100 , + \data_sync_reg[2][34]_101 , + \data_sync_reg[2][34]_102 , + \data_sync_reg[2][34]_103 , + \data_sync_reg[2][34]_104 , + \data_sync_reg[2][34]_105 , + \data_sync_reg[2][34]_106 , + \data_sync_reg[2][34]_107 , + \data_sync_reg[2][34]_108 , + \data_sync_reg[2][34]_109 , + \data_sync_reg[2][34]_110 , + \data_sync_reg[2][34]_111 , + \data_sync_reg[2][34]_112 , + \data_sync_reg[2][34]_113 , + \data_sync_reg[2][34]_114 , + \data_sync_reg[2][34]_115 , + \data_sync_reg[2][34]_116 , + \data_sync_reg[2][34]_117 , + \data_sync_reg[2][34]_118 , + \data_sync_reg[2][34]_119 , + \data_sync_reg[2][34]_120 , + \data_sync_reg[2][34]_121 , + \data_sync_reg[2][34]_122 , + \data_sync_reg[2][34]_123 , + \data_sync_reg[2][34]_124 , + \data_sync_reg[2][34]_125 , + \data_sync_reg[2][34]_126 , + \data_sync_reg[2][34]_127 , + \data_sync_reg[2][34]_128 , + \data_sync_reg[2][34]_129 , + \data_sync_reg[2][34]_130 , + \data_sync_reg[2][34]_131 , + \data_sync_reg[2][34]_132 , + \data_sync_reg[2][34]_133 , + \data_sync_reg[2][34]_134 , + \data_sync_reg[2][34]_135 , + \data_sync_reg[2][34]_136 , + \data_sync_reg[2][34]_137 , + \data_sync_reg[2][34]_138 , + \data_sync_reg[2][34]_139 , + \data_sync_reg[2][34]_140 , + \data_sync_reg[2][34]_141 , + \data_sync_reg[2][34]_142 , + \data_sync_reg[2][34]_143 , + \data_sync_reg[2][34]_144 , + \data_sync_reg[2][34]_145 , + \data_sync_reg[2][34]_146 , + \data_sync_reg[2][34]_147 , + \data_sync_reg[2][34]_148 , + \data_sync_reg[2][34]_149 , + \data_sync_reg[2][34]_150 , + \data_sync_reg[2][34]_151 , + \data_sync_reg[2][34]_152 , + \det_v0bp_start_hori_int2_reg[11] , + \det_v0bp_start_hori_int2_reg[10] , + \det_v0bp_start_hori_int2_reg[9] , + \det_v0bp_start_hori_int2_reg[8] , + \det_v0bp_start_hori_int2_reg[7] , + \det_v0bp_start_hori_int2_reg[6] , + \det_v0bp_start_hori_int2_reg[5] , + \det_v0bp_start_hori_int2_reg[4] , + \det_v0bp_start_hori_int2_reg[3] , + \det_v0bp_start_hori_int2_reg[2] , + \det_v0bp_start_hori_int2_reg[1] , + \det_v0bp_start_hori_int2_reg[0] , + \data_sync_reg[2][34]_153 , + \data_sync_reg[2][34]_154 , + \data_sync_reg[2][34]_155 , + \data_sync_reg[2][34]_156 , + \det_v0sync_start_hori_int2_reg[11] , + \det_v0sync_start_hori_int2_reg[10] , + \det_v0sync_start_hori_int2_reg[9] , + \det_v0sync_start_hori_int2_reg[8] , + \det_v0sync_start_hori_int2_reg[7] , + \det_v0sync_start_hori_int2_reg[6] , + \det_v0sync_start_hori_int2_reg[5] , + \det_v0sync_start_hori_int2_reg[4] , + \det_v0sync_start_hori_int2_reg[3] , + \det_v0sync_start_hori_int2_reg[2] , + \det_v0sync_start_hori_int2_reg[1] , + \det_v0sync_start_hori_int2_reg[0] , + \data_sync_reg[2][34]_157 , + \data_sync_reg[2][34]_158 , + \data_sync_reg[2][34]_159 , + \data_sync_reg[2][34]_160 , + \det_v0active_start_hori_int2_reg[11] , + \det_v0active_start_hori_int2_reg[10] , + \det_v0active_start_hori_int2_reg[9] , + \det_v0active_start_hori_int2_reg[8] , + \det_v0active_start_hori_int2_reg[7] , + \det_v0active_start_hori_int2_reg[6] , + \det_v0active_start_hori_int2_reg[5] , + \det_v0active_start_hori_int2_reg[4] , + \det_v0active_start_hori_int2_reg[3] , + \det_v0active_start_hori_int2_reg[2] , + \det_v0active_start_hori_int2_reg[1] , + \det_v0active_start_hori_int2_reg[0] , + \data_sync_reg[2][34]_161 , + \data_sync_reg[2][34]_162 , + \data_sync_reg[2][34]_163 , + \data_sync_reg[2][34]_164 , + \det_v0fp_start_hori_int2_reg[11] , + \det_v0fp_start_hori_int2_reg[10] , + \det_v0fp_start_hori_int2_reg[9] , + \det_v0fp_start_hori_int2_reg[8] , + \det_v0fp_start_hori_int2_reg[7] , + \det_v0fp_start_hori_int2_reg[6] , + \det_v0fp_start_hori_int2_reg[5] , + \det_v0fp_start_hori_int2_reg[4] , + \det_v0fp_start_hori_int2_reg[3] , + \det_v0fp_start_hori_int2_reg[2] , + \det_v0fp_start_hori_int2_reg[1] , + \det_v0fp_start_hori_int2_reg[0] , + \data_sync_reg[2][34]_165 , + \data_sync_reg[2][34]_166 , + \data_sync_reg[2][34]_167 , + \data_sync_reg[2][34]_168 , + \data_sync_reg[2][34]_169 , + \data_sync_reg[2][34]_170 , + \data_sync_reg[2][34]_171 , + \data_sync_reg[2][34]_172 , + \data_sync_reg[2][34]_173 , + \data_sync_reg[2][34]_174 , + \data_sync_reg[2][34]_175 , + \data_sync_reg[2][34]_176 , + \data_sync_reg[2][34]_177 , + \data_sync_reg[2][34]_178 , + \data_sync_reg[2][34]_179 , + \data_sync_reg[2][34]_180 , + \data_sync_reg[2][34]_181 , + \data_sync_reg[2][34]_182 , + \data_sync_reg[2][34]_183 , + \data_sync_reg[2][34]_184 , + \det_htotal_int2_reg[11] , + \det_v0total_reg[10] , + \det_v0total_reg[9] , + \det_v0total_reg[8] , + \det_v0total_reg[7] , + \det_v0total_reg[6] , + \det_v0total_reg[5] , + \det_v0total_reg[4] , + \det_v0total_reg[3] , + \det_v0total_reg[2] , + \det_v0total_reg[1] , + \det_v0total_reg[0] , + \data_sync_reg[2][34]_185 , + \data_sync_reg[2][34]_186 , + \data_sync_reg[2][34]_187 , + \data_sync_reg[2][34]_188 , + \data_sync_reg[2][34]_189 , + \data_sync_reg[2][34]_190 , + \data_sync_reg[2][34]_191 , + \data_sync_reg[2][34]_192 , + \data_sync_reg[2][34]_193 , + \data_sync_reg[2][34]_194 , + \data_sync_reg[2][34]_195 , + \data_sync_reg[2][34]_196 , + \data_sync_reg[2][34]_197 , + \data_sync_reg[2][34]_198 , + \data_sync_reg[2][34]_199 , + \data_sync_reg[2][34]_200 , + \data_sync_reg[2][34]_201 , + \data_sync_reg[2][34]_202 , + \data_sync_reg[2][34]_203 , + \data_sync_reg[2][34]_204 , + \data_sync_reg[2][34]_205 , + \data_sync_reg[2][34]_206 , + \data_sync_reg[2][34]_207 , + \gen_v0chroma_start_reg[0] , + \data_sync_reg[2][34]_208 , + \data_sync_reg[2][34]_209 , + \data_sync_reg[2][34]_210 , + \DET_HACTIVE.det_active_video_pol_int_reg , + \DET_HSYNC.det_hsync_pol_int_reg , + \DET_VSYNC.det_vsync_pol_int_reg , + \data_sync_reg[2][34]_211 , + \data_sync_reg[2][34]_212 , + \data_sync_reg[2][34]_213 , + \data_sync_reg[2][34]_214 , + \data_sync_reg[2][34]_215 , + \data_sync_reg[2][34]_216 , + \data_sync_reg[2][34]_217 , + \det_v0fp_start_int_reg[10] , + \det_v0fp_start_int_reg[9] , + \det_v0fp_start_int_reg[8] , + \det_v0fp_start_int_reg[7] , + \det_v0fp_start_int_reg[6] , + \det_v0fp_start_int_reg[5] , + \det_v0fp_start_int_reg[4] , + \det_v0fp_start_int_reg[3] , + \det_v0fp_start_int_reg[2] , + \det_v0fp_start_int_reg[1] , + \det_v0fp_start_int_reg[0] , + \data_sync_reg[2][34]_218 , + \data_sync_reg[2][34]_219 , + \data_sync_reg[2][34]_220 , + \data_sync_reg[2][34]_221 , + \det_hfp_start_int2_reg[11] , + \det_hfp_start_int2_reg[10] , + \det_hfp_start_int2_reg[9] , + \det_hfp_start_int2_reg[8] , + \det_hfp_start_int2_reg[7] , + \det_hfp_start_int2_reg[6] , + \det_hfp_start_int2_reg[5] , + \det_hfp_start_int2_reg[4] , + \det_hfp_start_int2_reg[3] , + \intr_status_int_reg[11] , + \intr_status_int_reg[10] , + \intr_status_int_reg[8] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][31] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][30] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][29] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][28] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][27] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][26] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][25] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][24] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][23] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][22] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][21] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][20] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][19] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][18] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][17] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][16] , + \GEN_HAS_IRQ.intr_err_reg[15] , + \GEN_HAS_IRQ.intr_err_reg[14] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][13] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][12] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][11] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][10] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][9] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][8] , + \GEN_HAS_IRQ.intr_err_reg[7] , + \GEN_HAS_IRQ.intr_err_reg[6] , + \GEN_HAS_IRQ.intr_err_reg[5] , + \GEN_HAS_IRQ.intr_err_reg[4] , + \GEN_HAS_IRQ.intr_err_reg[3] , + \GEN_HAS_IRQ.intr_err_reg[2] , + \GEN_HAS_IRQ.intr_err_reg[1] , + \GEN_HAS_IRQ.intr_err_reg[0] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][31] , + \GEN_HAS_IRQ.intr_stat_reg[30] , + \GEN_HAS_IRQ.intr_stat_reg[29] , + \GEN_HAS_IRQ.intr_stat_reg[28] , + \GEN_HAS_IRQ.intr_stat_reg[27] , + \GEN_HAS_IRQ.intr_stat_reg[26] , + \GEN_HAS_IRQ.intr_stat_reg[25] , + \GEN_HAS_IRQ.intr_stat_reg[24] , + \GEN_HAS_IRQ.intr_stat_reg[23] , + \GEN_HAS_IRQ.intr_stat_reg[22] , + \GEN_HAS_IRQ.intr_stat_reg[21] , + \GEN_HAS_IRQ.intr_stat_reg[20] , + \GEN_HAS_IRQ.intr_stat_reg[19] , + \GEN_HAS_IRQ.intr_stat_reg[18] , + \GEN_HAS_IRQ.intr_stat_reg[17] , + \GEN_HAS_IRQ.intr_stat_reg[16] , + \GEN_HAS_IRQ.intr_stat_reg[15] , + \GEN_HAS_IRQ.intr_stat_reg[14] , + \GEN_HAS_IRQ.intr_stat_reg[13] , + \GEN_HAS_IRQ.intr_stat_reg[12] , + \GEN_HAS_IRQ.intr_stat_reg[11] , + \GEN_HAS_IRQ.intr_stat_reg[10] , + \GEN_HAS_IRQ.intr_stat_reg[9] , + \GEN_HAS_IRQ.intr_stat_reg[8] , + \GEN_HAS_IRQ.intr_stat_reg[7] , + \GEN_HAS_IRQ.intr_stat_reg[6] , + \GEN_HAS_IRQ.intr_stat_reg[5] , + \GEN_HAS_IRQ.intr_stat_reg[4] , + \GEN_HAS_IRQ.intr_stat_reg[3] , + \GEN_HAS_IRQ.intr_stat_reg[2] , + \GEN_HAS_IRQ.intr_stat_reg[1] , + \GEN_HAS_IRQ.intr_stat_reg[0] , + \GEN_SEL_DELAY[3].sel_int_reg[3][0] , + \core_status_regs[15] , + \core_status_regs[14] , + \core_status_regs[13] , + \data_sync_reg[2][34]_222 , + \core_status_regs[12] , + \core_status_regs[11] , + \core_status_regs[10] , + \core_status_regs[9] , + \core_status_regs[8] , + core_regs, + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][0] , + \core_status_regs[7] , + \core_status_regs[6] , + \core_status_regs[5] , + \core_status_regs[4] , + \core_status_regs[3] , + \core_status_regs[2] , + \core_status_regs[1] , + \core_status_regs[0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0] ); + output \AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ; + output \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ; + output [31:0]genr_data; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][31]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][30]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][29]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][28]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][27]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][26]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][25]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][24]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][23]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][22]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][21]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][20]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][19]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][18]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][17]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][16]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][15]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][14]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][13]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][12]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][11]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][10]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][9]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][8]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][7]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][6]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][5]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][4]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][3]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][2]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][1]_0 ; + output \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][0]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][31]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][30]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][29]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][28]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][27]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][26]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][25]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][24]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][23]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][22]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][21]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][20]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][19]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][18]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][17]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][16]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][15]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][14]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][13]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][12]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][11]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][10]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][9]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][8]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][7]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][6]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][5]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][4]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][3]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][2]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][1]_0 ; + output \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][0]_0 ; + input \data_sync_reg[2][34] ; + input vid_aclk; + input [4:0]ipif_Addr; + input \data_sync_reg[2][34]_0 ; + input [5:0]\time_status_regs[28] ; + input [25:0]Q; + input \data_sync_reg[2][34]_1 ; + input \data_sync_reg[2][34]_2 ; + input \data_sync_reg[2][34]_3 ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][28] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][27] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][26] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][25] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][24] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][23] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][22] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][21] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][20] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][19] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][18] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][17] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][16] ; + input \data_sync_reg[2][34]_4 ; + input \data_sync_reg[2][34]_5 ; + input \data_sync_reg[2][34]_6 ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][12] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][11] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][10] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][9] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][8] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][7] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][6] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][5] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][4] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][3] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][2] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][1] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][0] ; + input \data_sync_reg[2][34]_7 ; + input \data_sync_reg[2][34]_8 ; + input \data_sync_reg[2][34]_9 ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][27] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][26] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][25] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][24] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][23] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][22] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][21] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][20] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][19] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][18] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][17] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][16] ; + input \data_sync_reg[2][34]_10 ; + input \data_sync_reg[2][34]_11 ; + input \data_sync_reg[2][34]_12 ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][12] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][11] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][10] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][9] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][8] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][7] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][6] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][5] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][4] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][3] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][2] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][1] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][0] ; + input \data_sync_reg[2][34]_13 ; + input \data_sync_reg[2][34]_14 ; + input \data_sync_reg[2][34]_15 ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][27] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][26] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][25] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][24] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][23] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][22] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][21] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][20] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][19] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][18] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][17] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][16] ; + input \data_sync_reg[2][34]_16 ; + input \data_sync_reg[2][34]_17 ; + input \data_sync_reg[2][34]_18 ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][12] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][11] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][10] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][9] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][8] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][7] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][6] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][5] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][4] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][3] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][2] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][1] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][0] ; + input \data_sync_reg[2][34]_19 ; + input \data_sync_reg[2][34]_20 ; + input \data_sync_reg[2][34]_21 ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][27] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][26] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][25] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][24] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][23] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][22] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][21] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][20] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][19] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][18] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][17] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][16] ; + input \data_sync_reg[2][34]_22 ; + input \data_sync_reg[2][34]_23 ; + input \data_sync_reg[2][34]_24 ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][12] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][11] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][10] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][9] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][8] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][7] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][6] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][5] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][4] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][3] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][2] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][1] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][0] ; + input \data_sync_reg[2][34]_25 ; + input \data_sync_reg[2][34]_26 ; + input \data_sync_reg[2][34]_27 ; + input \data_sync_reg[2][34]_28 ; + input \data_sync_reg[2][34]_29 ; + input \data_sync_reg[2][34]_30 ; + input \data_sync_reg[2][34]_31 ; + input \data_sync_reg[2][34]_32 ; + input \data_sync_reg[2][34]_33 ; + input \data_sync_reg[2][34]_34 ; + input \data_sync_reg[2][34]_35 ; + input \data_sync_reg[2][34]_36 ; + input \data_sync_reg[2][34]_37 ; + input \data_sync_reg[2][34]_38 ; + input \data_sync_reg[2][34]_39 ; + input \data_sync_reg[2][34]_40 ; + input \data_sync_reg[2][34]_41 ; + input \data_sync_reg[2][34]_42 ; + input \data_sync_reg[2][34]_43 ; + input \data_sync_reg[2][34]_44 ; + input \data_sync_reg[2][34]_45 ; + input \data_sync_reg[2][34]_46 ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][8] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][7] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][5] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][4] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][3] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][2] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][1] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][0] ; + input \data_sync_reg[2][34]_47 ; + input \data_sync_reg[2][34]_48 ; + input \data_sync_reg[2][34]_49 ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][27] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][26] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][25] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][24] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][23] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][22] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][21] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][20] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][19] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][18] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][17] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][16] ; + input \data_sync_reg[2][34]_50 ; + input \data_sync_reg[2][34]_51 ; + input \data_sync_reg[2][34]_52 ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][12] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][11] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][10] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][9] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][8] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][7] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][6] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][5] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][4] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][3] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][2] ; + input \intr_status_int_reg[12] ; + input \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][0] ; + input \data_sync_reg[2][34]_53 ; + input \data_sync_reg[2][34]_54 ; + input \data_sync_reg[2][34]_55 ; + input \data_sync_reg[2][34]_56 ; + input \data_sync_reg[2][34]_57 ; + input \data_sync_reg[2][34]_58 ; + input \data_sync_reg[2][34]_59 ; + input \data_sync_reg[2][34]_60 ; + input \data_sync_reg[2][34]_61 ; + input \data_sync_reg[2][34]_62 ; + input \data_sync_reg[2][34]_63 ; + input \data_sync_reg[2][34]_64 ; + input \data_sync_reg[2][34]_65 ; + input \data_sync_reg[2][34]_66 ; + input \data_sync_reg[2][34]_67 ; + input \data_sync_reg[2][34]_68 ; + input \data_sync_reg[2][34]_69 ; + input \data_sync_reg[2][34]_70 ; + input \data_sync_reg[2][34]_71 ; + input \data_sync_reg[2][34]_72 ; + input \data_sync_reg[2][34]_73 ; + input \data_sync_reg[2][34]_74 ; + input \data_sync_reg[2][34]_75 ; + input \data_sync_reg[2][34]_76 ; + input \data_sync_reg[2][34]_77 ; + input \data_sync_reg[2][34]_78 ; + input \data_sync_reg[2][34]_79 ; + input \data_sync_reg[2][34]_80 ; + input \data_sync_reg[2][34]_81 ; + input \data_sync_reg[2][34]_82 ; + input \data_sync_reg[2][34]_83 ; + input \data_sync_reg[2][34]_84 ; + input \data_sync_reg[2][34]_85 ; + input \data_sync_reg[2][34]_86 ; + input \data_sync_reg[2][34]_87 ; + input \data_sync_reg[2][34]_88 ; + input \data_sync_reg[2][34]_89 ; + input \data_sync_reg[2][34]_90 ; + input \data_sync_reg[2][34]_91 ; + input \data_sync_reg[2][34]_92 ; + input \data_sync_reg[2][34]_93 ; + input \data_sync_reg[2][34]_94 ; + input \data_sync_reg[2][34]_95 ; + input \data_sync_reg[2][34]_96 ; + input \data_sync_reg[2][34]_97 ; + input \data_sync_reg[2][34]_98 ; + input \data_sync_reg[2][34]_99 ; + input \data_sync_reg[2][34]_100 ; + input \data_sync_reg[2][34]_101 ; + input \data_sync_reg[2][34]_102 ; + input \data_sync_reg[2][34]_103 ; + input \data_sync_reg[2][34]_104 ; + input \data_sync_reg[2][34]_105 ; + input \data_sync_reg[2][34]_106 ; + input \data_sync_reg[2][34]_107 ; + input \data_sync_reg[2][34]_108 ; + input \data_sync_reg[2][34]_109 ; + input \data_sync_reg[2][34]_110 ; + input \data_sync_reg[2][34]_111 ; + input \data_sync_reg[2][34]_112 ; + input \data_sync_reg[2][34]_113 ; + input \data_sync_reg[2][34]_114 ; + input \data_sync_reg[2][34]_115 ; + input \data_sync_reg[2][34]_116 ; + input \data_sync_reg[2][34]_117 ; + input \data_sync_reg[2][34]_118 ; + input \data_sync_reg[2][34]_119 ; + input \data_sync_reg[2][34]_120 ; + input \data_sync_reg[2][34]_121 ; + input \data_sync_reg[2][34]_122 ; + input \data_sync_reg[2][34]_123 ; + input \data_sync_reg[2][34]_124 ; + input \data_sync_reg[2][34]_125 ; + input \data_sync_reg[2][34]_126 ; + input \data_sync_reg[2][34]_127 ; + input \data_sync_reg[2][34]_128 ; + input \data_sync_reg[2][34]_129 ; + input \data_sync_reg[2][34]_130 ; + input \data_sync_reg[2][34]_131 ; + input \data_sync_reg[2][34]_132 ; + input \data_sync_reg[2][34]_133 ; + input \data_sync_reg[2][34]_134 ; + input \data_sync_reg[2][34]_135 ; + input \data_sync_reg[2][34]_136 ; + input \data_sync_reg[2][34]_137 ; + input \data_sync_reg[2][34]_138 ; + input \data_sync_reg[2][34]_139 ; + input \data_sync_reg[2][34]_140 ; + input \data_sync_reg[2][34]_141 ; + input \data_sync_reg[2][34]_142 ; + input \data_sync_reg[2][34]_143 ; + input \data_sync_reg[2][34]_144 ; + input \data_sync_reg[2][34]_145 ; + input \data_sync_reg[2][34]_146 ; + input \data_sync_reg[2][34]_147 ; + input \data_sync_reg[2][34]_148 ; + input \data_sync_reg[2][34]_149 ; + input \data_sync_reg[2][34]_150 ; + input \data_sync_reg[2][34]_151 ; + input \data_sync_reg[2][34]_152 ; + input \det_v0bp_start_hori_int2_reg[11] ; + input \det_v0bp_start_hori_int2_reg[10] ; + input \det_v0bp_start_hori_int2_reg[9] ; + input \det_v0bp_start_hori_int2_reg[8] ; + input \det_v0bp_start_hori_int2_reg[7] ; + input \det_v0bp_start_hori_int2_reg[6] ; + input \det_v0bp_start_hori_int2_reg[5] ; + input \det_v0bp_start_hori_int2_reg[4] ; + input \det_v0bp_start_hori_int2_reg[3] ; + input \det_v0bp_start_hori_int2_reg[2] ; + input \det_v0bp_start_hori_int2_reg[1] ; + input \det_v0bp_start_hori_int2_reg[0] ; + input \data_sync_reg[2][34]_153 ; + input \data_sync_reg[2][34]_154 ; + input \data_sync_reg[2][34]_155 ; + input \data_sync_reg[2][34]_156 ; + input \det_v0sync_start_hori_int2_reg[11] ; + input \det_v0sync_start_hori_int2_reg[10] ; + input \det_v0sync_start_hori_int2_reg[9] ; + input \det_v0sync_start_hori_int2_reg[8] ; + input \det_v0sync_start_hori_int2_reg[7] ; + input \det_v0sync_start_hori_int2_reg[6] ; + input \det_v0sync_start_hori_int2_reg[5] ; + input \det_v0sync_start_hori_int2_reg[4] ; + input \det_v0sync_start_hori_int2_reg[3] ; + input \det_v0sync_start_hori_int2_reg[2] ; + input \det_v0sync_start_hori_int2_reg[1] ; + input \det_v0sync_start_hori_int2_reg[0] ; + input \data_sync_reg[2][34]_157 ; + input \data_sync_reg[2][34]_158 ; + input \data_sync_reg[2][34]_159 ; + input \data_sync_reg[2][34]_160 ; + input \det_v0active_start_hori_int2_reg[11] ; + input \det_v0active_start_hori_int2_reg[10] ; + input \det_v0active_start_hori_int2_reg[9] ; + input \det_v0active_start_hori_int2_reg[8] ; + input \det_v0active_start_hori_int2_reg[7] ; + input \det_v0active_start_hori_int2_reg[6] ; + input \det_v0active_start_hori_int2_reg[5] ; + input \det_v0active_start_hori_int2_reg[4] ; + input \det_v0active_start_hori_int2_reg[3] ; + input \det_v0active_start_hori_int2_reg[2] ; + input \det_v0active_start_hori_int2_reg[1] ; + input \det_v0active_start_hori_int2_reg[0] ; + input \data_sync_reg[2][34]_161 ; + input \data_sync_reg[2][34]_162 ; + input \data_sync_reg[2][34]_163 ; + input \data_sync_reg[2][34]_164 ; + input \det_v0fp_start_hori_int2_reg[11] ; + input \det_v0fp_start_hori_int2_reg[10] ; + input \det_v0fp_start_hori_int2_reg[9] ; + input \det_v0fp_start_hori_int2_reg[8] ; + input \det_v0fp_start_hori_int2_reg[7] ; + input \det_v0fp_start_hori_int2_reg[6] ; + input \det_v0fp_start_hori_int2_reg[5] ; + input \det_v0fp_start_hori_int2_reg[4] ; + input \det_v0fp_start_hori_int2_reg[3] ; + input \det_v0fp_start_hori_int2_reg[2] ; + input \det_v0fp_start_hori_int2_reg[1] ; + input \det_v0fp_start_hori_int2_reg[0] ; + input \data_sync_reg[2][34]_165 ; + input \data_sync_reg[2][34]_166 ; + input \data_sync_reg[2][34]_167 ; + input \data_sync_reg[2][34]_168 ; + input \data_sync_reg[2][34]_169 ; + input \data_sync_reg[2][34]_170 ; + input \data_sync_reg[2][34]_171 ; + input \data_sync_reg[2][34]_172 ; + input \data_sync_reg[2][34]_173 ; + input \data_sync_reg[2][34]_174 ; + input \data_sync_reg[2][34]_175 ; + input \data_sync_reg[2][34]_176 ; + input \data_sync_reg[2][34]_177 ; + input \data_sync_reg[2][34]_178 ; + input \data_sync_reg[2][34]_179 ; + input \data_sync_reg[2][34]_180 ; + input \data_sync_reg[2][34]_181 ; + input \data_sync_reg[2][34]_182 ; + input \data_sync_reg[2][34]_183 ; + input \data_sync_reg[2][34]_184 ; + input \det_htotal_int2_reg[11] ; + input \det_v0total_reg[10] ; + input \det_v0total_reg[9] ; + input \det_v0total_reg[8] ; + input \det_v0total_reg[7] ; + input \det_v0total_reg[6] ; + input \det_v0total_reg[5] ; + input \det_v0total_reg[4] ; + input \det_v0total_reg[3] ; + input \det_v0total_reg[2] ; + input \det_v0total_reg[1] ; + input \det_v0total_reg[0] ; + input \data_sync_reg[2][34]_185 ; + input \data_sync_reg[2][34]_186 ; + input \data_sync_reg[2][34]_187 ; + input \data_sync_reg[2][34]_188 ; + input \data_sync_reg[2][34]_189 ; + input \data_sync_reg[2][34]_190 ; + input \data_sync_reg[2][34]_191 ; + input \data_sync_reg[2][34]_192 ; + input \data_sync_reg[2][34]_193 ; + input \data_sync_reg[2][34]_194 ; + input \data_sync_reg[2][34]_195 ; + input \data_sync_reg[2][34]_196 ; + input \data_sync_reg[2][34]_197 ; + input \data_sync_reg[2][34]_198 ; + input \data_sync_reg[2][34]_199 ; + input \data_sync_reg[2][34]_200 ; + input \data_sync_reg[2][34]_201 ; + input \data_sync_reg[2][34]_202 ; + input \data_sync_reg[2][34]_203 ; + input \data_sync_reg[2][34]_204 ; + input \data_sync_reg[2][34]_205 ; + input \data_sync_reg[2][34]_206 ; + input \data_sync_reg[2][34]_207 ; + input \gen_v0chroma_start_reg[0] ; + input \data_sync_reg[2][34]_208 ; + input \data_sync_reg[2][34]_209 ; + input \data_sync_reg[2][34]_210 ; + input \DET_HACTIVE.det_active_video_pol_int_reg ; + input \DET_HSYNC.det_hsync_pol_int_reg ; + input \DET_VSYNC.det_vsync_pol_int_reg ; + input \data_sync_reg[2][34]_211 ; + input \data_sync_reg[2][34]_212 ; + input \data_sync_reg[2][34]_213 ; + input \data_sync_reg[2][34]_214 ; + input \data_sync_reg[2][34]_215 ; + input \data_sync_reg[2][34]_216 ; + input \data_sync_reg[2][34]_217 ; + input \det_v0fp_start_int_reg[10] ; + input \det_v0fp_start_int_reg[9] ; + input \det_v0fp_start_int_reg[8] ; + input \det_v0fp_start_int_reg[7] ; + input \det_v0fp_start_int_reg[6] ; + input \det_v0fp_start_int_reg[5] ; + input \det_v0fp_start_int_reg[4] ; + input \det_v0fp_start_int_reg[3] ; + input \det_v0fp_start_int_reg[2] ; + input \det_v0fp_start_int_reg[1] ; + input \det_v0fp_start_int_reg[0] ; + input \data_sync_reg[2][34]_218 ; + input \data_sync_reg[2][34]_219 ; + input \data_sync_reg[2][34]_220 ; + input \data_sync_reg[2][34]_221 ; + input \det_hfp_start_int2_reg[11] ; + input \det_hfp_start_int2_reg[10] ; + input \det_hfp_start_int2_reg[9] ; + input \det_hfp_start_int2_reg[8] ; + input \det_hfp_start_int2_reg[7] ; + input \det_hfp_start_int2_reg[6] ; + input \det_hfp_start_int2_reg[5] ; + input \det_hfp_start_int2_reg[4] ; + input \det_hfp_start_int2_reg[3] ; + input \intr_status_int_reg[11] ; + input \intr_status_int_reg[10] ; + input \intr_status_int_reg[8] ; + input \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][31] ; + input \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][30] ; + input \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][29] ; + input \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][28] ; + input \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][27] ; + input \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][26] ; + input \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][25] ; + input \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][24] ; + input \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][23] ; + input \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][22] ; + input \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][21] ; + input \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][20] ; + input \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][19] ; + input \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][18] ; + input \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][17] ; + input \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][16] ; + input \GEN_HAS_IRQ.intr_err_reg[15] ; + input \GEN_HAS_IRQ.intr_err_reg[14] ; + input \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][13] ; + input \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][12] ; + input \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][11] ; + input \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][10] ; + input \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][9] ; + input \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][8] ; + input \GEN_HAS_IRQ.intr_err_reg[7] ; + input \GEN_HAS_IRQ.intr_err_reg[6] ; + input \GEN_HAS_IRQ.intr_err_reg[5] ; + input \GEN_HAS_IRQ.intr_err_reg[4] ; + input \GEN_HAS_IRQ.intr_err_reg[3] ; + input \GEN_HAS_IRQ.intr_err_reg[2] ; + input \GEN_HAS_IRQ.intr_err_reg[1] ; + input \GEN_HAS_IRQ.intr_err_reg[0] ; + input \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][31] ; + input \GEN_HAS_IRQ.intr_stat_reg[30] ; + input \GEN_HAS_IRQ.intr_stat_reg[29] ; + input \GEN_HAS_IRQ.intr_stat_reg[28] ; + input \GEN_HAS_IRQ.intr_stat_reg[27] ; + input \GEN_HAS_IRQ.intr_stat_reg[26] ; + input \GEN_HAS_IRQ.intr_stat_reg[25] ; + input \GEN_HAS_IRQ.intr_stat_reg[24] ; + input \GEN_HAS_IRQ.intr_stat_reg[23] ; + input \GEN_HAS_IRQ.intr_stat_reg[22] ; + input \GEN_HAS_IRQ.intr_stat_reg[21] ; + input \GEN_HAS_IRQ.intr_stat_reg[20] ; + input \GEN_HAS_IRQ.intr_stat_reg[19] ; + input \GEN_HAS_IRQ.intr_stat_reg[18] ; + input \GEN_HAS_IRQ.intr_stat_reg[17] ; + input \GEN_HAS_IRQ.intr_stat_reg[16] ; + input \GEN_HAS_IRQ.intr_stat_reg[15] ; + input \GEN_HAS_IRQ.intr_stat_reg[14] ; + input \GEN_HAS_IRQ.intr_stat_reg[13] ; + input \GEN_HAS_IRQ.intr_stat_reg[12] ; + input \GEN_HAS_IRQ.intr_stat_reg[11] ; + input \GEN_HAS_IRQ.intr_stat_reg[10] ; + input \GEN_HAS_IRQ.intr_stat_reg[9] ; + input \GEN_HAS_IRQ.intr_stat_reg[8] ; + input \GEN_HAS_IRQ.intr_stat_reg[7] ; + input \GEN_HAS_IRQ.intr_stat_reg[6] ; + input \GEN_HAS_IRQ.intr_stat_reg[5] ; + input \GEN_HAS_IRQ.intr_stat_reg[4] ; + input \GEN_HAS_IRQ.intr_stat_reg[3] ; + input \GEN_HAS_IRQ.intr_stat_reg[2] ; + input \GEN_HAS_IRQ.intr_stat_reg[1] ; + input \GEN_HAS_IRQ.intr_stat_reg[0] ; + input \GEN_SEL_DELAY[3].sel_int_reg[3][0] ; + input [8:0]\core_status_regs[15] ; + input [8:0]\core_status_regs[14] ; + input [8:0]\core_status_regs[13] ; + input \data_sync_reg[2][34]_222 ; + input [8:0]\core_status_regs[12] ; + input [8:0]\core_status_regs[11] ; + input [8:0]\core_status_regs[10] ; + input [8:0]\core_status_regs[9] ; + input [8:0]\core_status_regs[8] ; + input [351:0]core_regs; + input [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][0] ; + input [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][0] ; + input [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][0] ; + input [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][0] ; + input [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][0] ; + input [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][0] ; + input [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][0] ; + input [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][0] ; + input [8:0]\core_status_regs[7] ; + input [8:0]\core_status_regs[6] ; + input [8:0]\core_status_regs[5] ; + input [8:0]\core_status_regs[4] ; + input [8:0]\core_status_regs[3] ; + input [8:0]\core_status_regs[2] ; + input [8:0]\core_status_regs[1] ; + input [8:0]\core_status_regs[0] ; + input [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][0] ; + input [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][0] ; + input [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][0] ; + input [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][0] ; + input [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][0] ; + input [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][0] ; + input [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][0] ; + input [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0] ; + + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0] ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][0] ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][0] ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][0] ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][0] ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][0] ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][0] ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][0] ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][0] ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][0] ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][0] ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][0] ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][0] ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][0] ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][0] ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][0] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][31] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][10] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][11] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][12] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][13] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][16] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][17] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][18] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][19] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][20] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][21] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][22] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][23] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][24] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][25] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][26] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][27] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][28] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][29] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][30] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][31] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][8] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][9] ; + wire \AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][0] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][10] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][11] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][12] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][16] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][17] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][18] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][19] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][20] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][21] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][22] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][23] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][24] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][25] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][26] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][27] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][2] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][3] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][4] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][5] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][6] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][7] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][8] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][9] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][7] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][8] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][0] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][1] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][2] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][3] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][4] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][5] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][0] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][10] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][11] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][12] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][16] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][17] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][18] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][19] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][1] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][20] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][21] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][22] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][23] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][24] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][25] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][26] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][27] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][2] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][3] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][4] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][5] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][6] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][7] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][8] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][9] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][0] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][10] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][11] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][12] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][16] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][17] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][18] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][19] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][1] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][20] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][21] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][22] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][23] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][24] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][25] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][26] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][27] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][2] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][3] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][4] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][5] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][6] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][7] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][8] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][9] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][0] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][10] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][11] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][12] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][16] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][17] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][18] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][19] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][1] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][20] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][21] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][22] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][23] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][24] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][25] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][26] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][27] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][2] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][3] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][4] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][5] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][6] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][7] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][8] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][9] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][0] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][10] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][11] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][12] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][16] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][17] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][18] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][19] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][1] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][20] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][21] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][22] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][23] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][24] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][25] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][26] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][27] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][28] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][2] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][3] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][4] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][5] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][6] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][7] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][8] ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][9] ; + wire \DET_HACTIVE.det_active_video_pol_int_reg ; + wire \DET_HSYNC.det_hsync_pol_int_reg ; + wire \DET_VSYNC.det_vsync_pol_int_reg ; + wire \GEN_HAS_IRQ.intr_err_reg[0] ; + wire \GEN_HAS_IRQ.intr_err_reg[14] ; + wire \GEN_HAS_IRQ.intr_err_reg[15] ; + wire \GEN_HAS_IRQ.intr_err_reg[1] ; + wire \GEN_HAS_IRQ.intr_err_reg[2] ; + wire \GEN_HAS_IRQ.intr_err_reg[3] ; + wire \GEN_HAS_IRQ.intr_err_reg[4] ; + wire \GEN_HAS_IRQ.intr_err_reg[5] ; + wire \GEN_HAS_IRQ.intr_err_reg[6] ; + wire \GEN_HAS_IRQ.intr_err_reg[7] ; + wire \GEN_HAS_IRQ.intr_stat_reg[0] ; + wire \GEN_HAS_IRQ.intr_stat_reg[10] ; + wire \GEN_HAS_IRQ.intr_stat_reg[11] ; + wire \GEN_HAS_IRQ.intr_stat_reg[12] ; + wire \GEN_HAS_IRQ.intr_stat_reg[13] ; + wire \GEN_HAS_IRQ.intr_stat_reg[14] ; + wire \GEN_HAS_IRQ.intr_stat_reg[15] ; + wire \GEN_HAS_IRQ.intr_stat_reg[16] ; + wire \GEN_HAS_IRQ.intr_stat_reg[17] ; + wire \GEN_HAS_IRQ.intr_stat_reg[18] ; + wire \GEN_HAS_IRQ.intr_stat_reg[19] ; + wire \GEN_HAS_IRQ.intr_stat_reg[1] ; + wire \GEN_HAS_IRQ.intr_stat_reg[20] ; + wire \GEN_HAS_IRQ.intr_stat_reg[21] ; + wire \GEN_HAS_IRQ.intr_stat_reg[22] ; + wire \GEN_HAS_IRQ.intr_stat_reg[23] ; + wire \GEN_HAS_IRQ.intr_stat_reg[24] ; + wire \GEN_HAS_IRQ.intr_stat_reg[25] ; + wire \GEN_HAS_IRQ.intr_stat_reg[26] ; + wire \GEN_HAS_IRQ.intr_stat_reg[27] ; + wire \GEN_HAS_IRQ.intr_stat_reg[28] ; + wire \GEN_HAS_IRQ.intr_stat_reg[29] ; + wire \GEN_HAS_IRQ.intr_stat_reg[2] ; + wire \GEN_HAS_IRQ.intr_stat_reg[30] ; + wire \GEN_HAS_IRQ.intr_stat_reg[3] ; + wire \GEN_HAS_IRQ.intr_stat_reg[4] ; + wire \GEN_HAS_IRQ.intr_stat_reg[5] ; + wire \GEN_HAS_IRQ.intr_stat_reg[6] ; + wire \GEN_HAS_IRQ.intr_stat_reg[7] ; + wire \GEN_HAS_IRQ.intr_stat_reg[8] ; + wire \GEN_HAS_IRQ.intr_stat_reg[9] ; + wire \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ; + wire \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ; + wire \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] ; + wire \GEN_SEL_DELAY[3].sel_int_reg[3][0] ; + wire \GEN_SEL_DELAY[4].sel_int_reg[4][1]_srl3_n_0 ; + wire \GEN_SEL_DELAY[5].sel_int_reg[5][1]_srl4_n_0 ; + wire \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ; + wire [31:0]\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 ; + wire [31:0]\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 ; + wire [26:26]\GEN_TREE.GEN_BRANCH[33].GEN_MUX_REG.data_out_reg_reg[33]_0 ; + wire [31:0]\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 ; + wire [31:0]\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 ; + wire [31:0]\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 ; + wire [31:0]\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 ; + wire [31:0]\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][0]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][0]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][10]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][11]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][12]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][13]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][14]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][15]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][16]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][16]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][17]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][18]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][19]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][1]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][1]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][20]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][21]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][22]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][23]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][24]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][25]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][25]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][26]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][26]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][27]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][28]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][29]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][2]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][30]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][31]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][3]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][3]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][4]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][5]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][6]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][7]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][8]_0 ; + wire \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][9]_0 ; + wire [31:0]\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 ; + wire [31:0]\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 ; + wire [31:0]\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 ; + wire [31:0]\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 ; + wire [31:0]\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 ; + wire [31:0]\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 ; + wire [31:0]\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 ; + wire [31:0]\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 ; + wire [31:0]\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 ; + wire [31:0]\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 ; + wire [31:0]\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_2__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_3__0_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_3_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][0]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][0]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][10]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][10]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][11]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][11]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][12]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][12]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][13]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][13]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][14]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][14]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][15]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][15]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][16]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][16]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][17]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][17]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][18]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][18]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][19]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][19]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][1]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][1]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][20]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][20]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][21]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][21]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][22]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][22]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][23]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][23]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][24]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][24]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][25]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][25]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][26]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][26]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][27]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][27]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][28]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][28]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][29]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][29]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][2]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][2]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][30]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][30]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][31]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][31]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][3]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][3]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][4]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][4]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][5]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][5]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][6]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][6]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][7]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][7]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][8]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][8]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][9]_0 ; + wire \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][9]_i_1_n_0 ; + wire [31:0]\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][0]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][10]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][11]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][12]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][13]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][14]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][15]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][16]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][17]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][18]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][19]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][1]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][20]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][21]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][22]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][23]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][24]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][25]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][26]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][27]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][28]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][29]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][2]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][30]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][3]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][4]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][5]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][6]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][7]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][8]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][9]_i_1_n_0 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ; + wire [31:0]\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 ; + wire [25:0]Q; + wire [351:0]core_regs; + wire [8:0]\core_status_regs[0] ; + wire [8:0]\core_status_regs[10] ; + wire [8:0]\core_status_regs[11] ; + wire [8:0]\core_status_regs[12] ; + wire [8:0]\core_status_regs[13] ; + wire [8:0]\core_status_regs[14] ; + wire [8:0]\core_status_regs[15] ; + wire [8:0]\core_status_regs[1] ; + wire [8:0]\core_status_regs[2] ; + wire [8:0]\core_status_regs[3] ; + wire [8:0]\core_status_regs[4] ; + wire [8:0]\core_status_regs[5] ; + wire [8:0]\core_status_regs[6] ; + wire [8:0]\core_status_regs[7] ; + wire [8:0]\core_status_regs[8] ; + wire [8:0]\core_status_regs[9] ; + wire \data_sync_reg[2][34] ; + wire \data_sync_reg[2][34]_0 ; + wire \data_sync_reg[2][34]_1 ; + wire \data_sync_reg[2][34]_10 ; + wire \data_sync_reg[2][34]_100 ; + wire \data_sync_reg[2][34]_101 ; + wire \data_sync_reg[2][34]_102 ; + wire \data_sync_reg[2][34]_103 ; + wire \data_sync_reg[2][34]_104 ; + wire \data_sync_reg[2][34]_105 ; + wire \data_sync_reg[2][34]_106 ; + wire \data_sync_reg[2][34]_107 ; + wire \data_sync_reg[2][34]_108 ; + wire \data_sync_reg[2][34]_109 ; + wire \data_sync_reg[2][34]_11 ; + wire \data_sync_reg[2][34]_110 ; + wire \data_sync_reg[2][34]_111 ; + wire \data_sync_reg[2][34]_112 ; + wire \data_sync_reg[2][34]_113 ; + wire \data_sync_reg[2][34]_114 ; + wire \data_sync_reg[2][34]_115 ; + wire \data_sync_reg[2][34]_116 ; + wire \data_sync_reg[2][34]_117 ; + wire \data_sync_reg[2][34]_118 ; + wire \data_sync_reg[2][34]_119 ; + wire \data_sync_reg[2][34]_12 ; + wire \data_sync_reg[2][34]_120 ; + wire \data_sync_reg[2][34]_121 ; + wire \data_sync_reg[2][34]_122 ; + wire \data_sync_reg[2][34]_123 ; + wire \data_sync_reg[2][34]_124 ; + wire \data_sync_reg[2][34]_125 ; + wire \data_sync_reg[2][34]_126 ; + wire \data_sync_reg[2][34]_127 ; + wire \data_sync_reg[2][34]_128 ; + wire \data_sync_reg[2][34]_129 ; + wire \data_sync_reg[2][34]_13 ; + wire \data_sync_reg[2][34]_130 ; + wire \data_sync_reg[2][34]_131 ; + wire \data_sync_reg[2][34]_132 ; + wire \data_sync_reg[2][34]_133 ; + wire \data_sync_reg[2][34]_134 ; + wire \data_sync_reg[2][34]_135 ; + wire \data_sync_reg[2][34]_136 ; + wire \data_sync_reg[2][34]_137 ; + wire \data_sync_reg[2][34]_138 ; + wire \data_sync_reg[2][34]_139 ; + wire \data_sync_reg[2][34]_14 ; + wire \data_sync_reg[2][34]_140 ; + wire \data_sync_reg[2][34]_141 ; + wire \data_sync_reg[2][34]_142 ; + wire \data_sync_reg[2][34]_143 ; + wire \data_sync_reg[2][34]_144 ; + wire \data_sync_reg[2][34]_145 ; + wire \data_sync_reg[2][34]_146 ; + wire \data_sync_reg[2][34]_147 ; + wire \data_sync_reg[2][34]_148 ; + wire \data_sync_reg[2][34]_149 ; + wire \data_sync_reg[2][34]_15 ; + wire \data_sync_reg[2][34]_150 ; + wire \data_sync_reg[2][34]_151 ; + wire \data_sync_reg[2][34]_152 ; + wire \data_sync_reg[2][34]_153 ; + wire \data_sync_reg[2][34]_154 ; + wire \data_sync_reg[2][34]_155 ; + wire \data_sync_reg[2][34]_156 ; + wire \data_sync_reg[2][34]_157 ; + wire \data_sync_reg[2][34]_158 ; + wire \data_sync_reg[2][34]_159 ; + wire \data_sync_reg[2][34]_16 ; + wire \data_sync_reg[2][34]_160 ; + wire \data_sync_reg[2][34]_161 ; + wire \data_sync_reg[2][34]_162 ; + wire \data_sync_reg[2][34]_163 ; + wire \data_sync_reg[2][34]_164 ; + wire \data_sync_reg[2][34]_165 ; + wire \data_sync_reg[2][34]_166 ; + wire \data_sync_reg[2][34]_167 ; + wire \data_sync_reg[2][34]_168 ; + wire \data_sync_reg[2][34]_169 ; + wire \data_sync_reg[2][34]_17 ; + wire \data_sync_reg[2][34]_170 ; + wire \data_sync_reg[2][34]_171 ; + wire \data_sync_reg[2][34]_172 ; + wire \data_sync_reg[2][34]_173 ; + wire \data_sync_reg[2][34]_174 ; + wire \data_sync_reg[2][34]_175 ; + wire \data_sync_reg[2][34]_176 ; + wire \data_sync_reg[2][34]_177 ; + wire \data_sync_reg[2][34]_178 ; + wire \data_sync_reg[2][34]_179 ; + wire \data_sync_reg[2][34]_18 ; + wire \data_sync_reg[2][34]_180 ; + wire \data_sync_reg[2][34]_181 ; + wire \data_sync_reg[2][34]_182 ; + wire \data_sync_reg[2][34]_183 ; + wire \data_sync_reg[2][34]_184 ; + wire \data_sync_reg[2][34]_185 ; + wire \data_sync_reg[2][34]_186 ; + wire \data_sync_reg[2][34]_187 ; + wire \data_sync_reg[2][34]_188 ; + wire \data_sync_reg[2][34]_189 ; + wire \data_sync_reg[2][34]_19 ; + wire \data_sync_reg[2][34]_190 ; + wire \data_sync_reg[2][34]_191 ; + wire \data_sync_reg[2][34]_192 ; + wire \data_sync_reg[2][34]_193 ; + wire \data_sync_reg[2][34]_194 ; + wire \data_sync_reg[2][34]_195 ; + wire \data_sync_reg[2][34]_196 ; + wire \data_sync_reg[2][34]_197 ; + wire \data_sync_reg[2][34]_198 ; + wire \data_sync_reg[2][34]_199 ; + wire \data_sync_reg[2][34]_2 ; + wire \data_sync_reg[2][34]_20 ; + wire \data_sync_reg[2][34]_200 ; + wire \data_sync_reg[2][34]_201 ; + wire \data_sync_reg[2][34]_202 ; + wire \data_sync_reg[2][34]_203 ; + wire \data_sync_reg[2][34]_204 ; + wire \data_sync_reg[2][34]_205 ; + wire \data_sync_reg[2][34]_206 ; + wire \data_sync_reg[2][34]_207 ; + wire \data_sync_reg[2][34]_208 ; + wire \data_sync_reg[2][34]_209 ; + wire \data_sync_reg[2][34]_21 ; + wire \data_sync_reg[2][34]_210 ; + wire \data_sync_reg[2][34]_211 ; + wire \data_sync_reg[2][34]_212 ; + wire \data_sync_reg[2][34]_213 ; + wire \data_sync_reg[2][34]_214 ; + wire \data_sync_reg[2][34]_215 ; + wire \data_sync_reg[2][34]_216 ; + wire \data_sync_reg[2][34]_217 ; + wire \data_sync_reg[2][34]_218 ; + wire \data_sync_reg[2][34]_219 ; + wire \data_sync_reg[2][34]_22 ; + wire \data_sync_reg[2][34]_220 ; + wire \data_sync_reg[2][34]_221 ; + wire \data_sync_reg[2][34]_222 ; + wire \data_sync_reg[2][34]_23 ; + wire \data_sync_reg[2][34]_24 ; + wire \data_sync_reg[2][34]_25 ; + wire \data_sync_reg[2][34]_26 ; + wire \data_sync_reg[2][34]_27 ; + wire \data_sync_reg[2][34]_28 ; + wire \data_sync_reg[2][34]_29 ; + wire \data_sync_reg[2][34]_3 ; + wire \data_sync_reg[2][34]_30 ; + wire \data_sync_reg[2][34]_31 ; + wire \data_sync_reg[2][34]_32 ; + wire \data_sync_reg[2][34]_33 ; + wire \data_sync_reg[2][34]_34 ; + wire \data_sync_reg[2][34]_35 ; + wire \data_sync_reg[2][34]_36 ; + wire \data_sync_reg[2][34]_37 ; + wire \data_sync_reg[2][34]_38 ; + wire \data_sync_reg[2][34]_39 ; + wire \data_sync_reg[2][34]_4 ; + wire \data_sync_reg[2][34]_40 ; + wire \data_sync_reg[2][34]_41 ; + wire \data_sync_reg[2][34]_42 ; + wire \data_sync_reg[2][34]_43 ; + wire \data_sync_reg[2][34]_44 ; + wire \data_sync_reg[2][34]_45 ; + wire \data_sync_reg[2][34]_46 ; + wire \data_sync_reg[2][34]_47 ; + wire \data_sync_reg[2][34]_48 ; + wire \data_sync_reg[2][34]_49 ; + wire \data_sync_reg[2][34]_5 ; + wire \data_sync_reg[2][34]_50 ; + wire \data_sync_reg[2][34]_51 ; + wire \data_sync_reg[2][34]_52 ; + wire \data_sync_reg[2][34]_53 ; + wire \data_sync_reg[2][34]_54 ; + wire \data_sync_reg[2][34]_55 ; + wire \data_sync_reg[2][34]_56 ; + wire \data_sync_reg[2][34]_57 ; + wire \data_sync_reg[2][34]_58 ; + wire \data_sync_reg[2][34]_59 ; + wire \data_sync_reg[2][34]_6 ; + wire \data_sync_reg[2][34]_60 ; + wire \data_sync_reg[2][34]_61 ; + wire \data_sync_reg[2][34]_62 ; + wire \data_sync_reg[2][34]_63 ; + wire \data_sync_reg[2][34]_64 ; + wire \data_sync_reg[2][34]_65 ; + wire \data_sync_reg[2][34]_66 ; + wire \data_sync_reg[2][34]_67 ; + wire \data_sync_reg[2][34]_68 ; + wire \data_sync_reg[2][34]_69 ; + wire \data_sync_reg[2][34]_7 ; + wire \data_sync_reg[2][34]_70 ; + wire \data_sync_reg[2][34]_71 ; + wire \data_sync_reg[2][34]_72 ; + wire \data_sync_reg[2][34]_73 ; + wire \data_sync_reg[2][34]_74 ; + wire \data_sync_reg[2][34]_75 ; + wire \data_sync_reg[2][34]_76 ; + wire \data_sync_reg[2][34]_77 ; + wire \data_sync_reg[2][34]_78 ; + wire \data_sync_reg[2][34]_79 ; + wire \data_sync_reg[2][34]_8 ; + wire \data_sync_reg[2][34]_80 ; + wire \data_sync_reg[2][34]_81 ; + wire \data_sync_reg[2][34]_82 ; + wire \data_sync_reg[2][34]_83 ; + wire \data_sync_reg[2][34]_84 ; + wire \data_sync_reg[2][34]_85 ; + wire \data_sync_reg[2][34]_86 ; + wire \data_sync_reg[2][34]_87 ; + wire \data_sync_reg[2][34]_88 ; + wire \data_sync_reg[2][34]_89 ; + wire \data_sync_reg[2][34]_9 ; + wire \data_sync_reg[2][34]_90 ; + wire \data_sync_reg[2][34]_91 ; + wire \data_sync_reg[2][34]_92 ; + wire \data_sync_reg[2][34]_93 ; + wire \data_sync_reg[2][34]_94 ; + wire \data_sync_reg[2][34]_95 ; + wire \data_sync_reg[2][34]_96 ; + wire \data_sync_reg[2][34]_97 ; + wire \data_sync_reg[2][34]_98 ; + wire \data_sync_reg[2][34]_99 ; + wire \det_hfp_start_int2_reg[10] ; + wire \det_hfp_start_int2_reg[11] ; + wire \det_hfp_start_int2_reg[3] ; + wire \det_hfp_start_int2_reg[4] ; + wire \det_hfp_start_int2_reg[5] ; + wire \det_hfp_start_int2_reg[6] ; + wire \det_hfp_start_int2_reg[7] ; + wire \det_hfp_start_int2_reg[8] ; + wire \det_hfp_start_int2_reg[9] ; + wire \det_htotal_int2_reg[11] ; + wire \det_v0active_start_hori_int2_reg[0] ; + wire \det_v0active_start_hori_int2_reg[10] ; + wire \det_v0active_start_hori_int2_reg[11] ; + wire \det_v0active_start_hori_int2_reg[1] ; + wire \det_v0active_start_hori_int2_reg[2] ; + wire \det_v0active_start_hori_int2_reg[3] ; + wire \det_v0active_start_hori_int2_reg[4] ; + wire \det_v0active_start_hori_int2_reg[5] ; + wire \det_v0active_start_hori_int2_reg[6] ; + wire \det_v0active_start_hori_int2_reg[7] ; + wire \det_v0active_start_hori_int2_reg[8] ; + wire \det_v0active_start_hori_int2_reg[9] ; + wire \det_v0bp_start_hori_int2_reg[0] ; + wire \det_v0bp_start_hori_int2_reg[10] ; + wire \det_v0bp_start_hori_int2_reg[11] ; + wire \det_v0bp_start_hori_int2_reg[1] ; + wire \det_v0bp_start_hori_int2_reg[2] ; + wire \det_v0bp_start_hori_int2_reg[3] ; + wire \det_v0bp_start_hori_int2_reg[4] ; + wire \det_v0bp_start_hori_int2_reg[5] ; + wire \det_v0bp_start_hori_int2_reg[6] ; + wire \det_v0bp_start_hori_int2_reg[7] ; + wire \det_v0bp_start_hori_int2_reg[8] ; + wire \det_v0bp_start_hori_int2_reg[9] ; + wire \det_v0fp_start_hori_int2_reg[0] ; + wire \det_v0fp_start_hori_int2_reg[10] ; + wire \det_v0fp_start_hori_int2_reg[11] ; + wire \det_v0fp_start_hori_int2_reg[1] ; + wire \det_v0fp_start_hori_int2_reg[2] ; + wire \det_v0fp_start_hori_int2_reg[3] ; + wire \det_v0fp_start_hori_int2_reg[4] ; + wire \det_v0fp_start_hori_int2_reg[5] ; + wire \det_v0fp_start_hori_int2_reg[6] ; + wire \det_v0fp_start_hori_int2_reg[7] ; + wire \det_v0fp_start_hori_int2_reg[8] ; + wire \det_v0fp_start_hori_int2_reg[9] ; + wire \det_v0fp_start_int_reg[0] ; + wire \det_v0fp_start_int_reg[10] ; + wire \det_v0fp_start_int_reg[1] ; + wire \det_v0fp_start_int_reg[2] ; + wire \det_v0fp_start_int_reg[3] ; + wire \det_v0fp_start_int_reg[4] ; + wire \det_v0fp_start_int_reg[5] ; + wire \det_v0fp_start_int_reg[6] ; + wire \det_v0fp_start_int_reg[7] ; + wire \det_v0fp_start_int_reg[8] ; + wire \det_v0fp_start_int_reg[9] ; + wire \det_v0sync_start_hori_int2_reg[0] ; + wire \det_v0sync_start_hori_int2_reg[10] ; + wire \det_v0sync_start_hori_int2_reg[11] ; + wire \det_v0sync_start_hori_int2_reg[1] ; + wire \det_v0sync_start_hori_int2_reg[2] ; + wire \det_v0sync_start_hori_int2_reg[3] ; + wire \det_v0sync_start_hori_int2_reg[4] ; + wire \det_v0sync_start_hori_int2_reg[5] ; + wire \det_v0sync_start_hori_int2_reg[6] ; + wire \det_v0sync_start_hori_int2_reg[7] ; + wire \det_v0sync_start_hori_int2_reg[8] ; + wire \det_v0sync_start_hori_int2_reg[9] ; + wire \det_v0total_reg[0] ; + wire \det_v0total_reg[10] ; + wire \det_v0total_reg[1] ; + wire \det_v0total_reg[2] ; + wire \det_v0total_reg[3] ; + wire \det_v0total_reg[4] ; + wire \det_v0total_reg[5] ; + wire \det_v0total_reg[6] ; + wire \det_v0total_reg[7] ; + wire \det_v0total_reg[8] ; + wire \det_v0total_reg[9] ; + wire \gen_v0chroma_start_reg[0] ; + wire [31:0]genr_data; + wire \intr_status_int_reg[10] ; + wire \intr_status_int_reg[11] ; + wire \intr_status_int_reg[12] ; + wire \intr_status_int_reg[8] ; + wire [4:0]ipif_Addr; + wire [0:0]\sel_int[2]_1 ; + wire [5:0]\time_status_regs[28] ; + wire vid_aclk; + + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[0]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [0]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [0]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [0]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[0])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[10]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [10]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [10]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [10]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[10])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[11]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [11]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [11]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [11]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[11])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[12]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [12]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [12]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [12]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[12])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[13]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [13]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [13]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [13]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[13])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[14]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [14]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [14]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [14]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[14])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[15]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [15]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [15]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [15]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[15])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[16]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [16]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [16]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [16]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[16])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[17]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [17]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [17]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [17]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[17])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[18]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [18]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [18]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [18]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[18])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[19]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [19]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [19]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [19]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[19])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[1]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [1]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [1]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [1]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[1])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[20]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [20]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [20]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [20]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[20])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[21]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [21]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [21]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [21]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[21])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[22]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [22]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [22]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [22]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[22])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[23]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [23]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [23]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [23]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[23])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[24]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [24]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [24]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [24]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[24])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[25]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [25]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [25]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [25]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[25])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[26]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [26]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [26]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [26]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[26])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[27]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [27]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [27]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [27]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[27])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[28]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [28]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [28]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [28]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[28])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[29]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [29]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [29]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [29]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[29])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[2]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [2]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [2]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [2]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[2])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[30]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [30]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [30]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [30]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[30])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[31]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [31]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [31]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [31]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[31])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[3]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [3]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [3]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [3]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[3])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[4]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [4]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [4]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [4]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[4])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[5]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [5]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [5]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [5]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[5])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[6]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [6]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [6]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [6]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[6])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[7]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [7]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [7]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [7]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[7])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[8]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [8]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [8]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [8]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[8])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[9]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [9]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [9]), + .I2(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [9]), + .I4(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .O(genr_data[9])); + (* ORIG_CELL_NAME = "GEN_SEL_DELAY[1].sel_int_reg[1][0]" *) + FDRE #( + .INIT(1'b0)) + \GEN_SEL_DELAY[1].sel_int_reg[1][0] + (.C(vid_aclk), + .CE(1'b1), + .D(ipif_Addr[1]), + .Q(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .R(1'b0)); + (* ORIG_CELL_NAME = "GEN_SEL_DELAY[1].sel_int_reg[1][0]" *) + FDRE #( + .INIT(1'b0)) + \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep + (.C(vid_aclk), + .CE(1'b1), + .D(ipif_Addr[1]), + .Q(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .R(1'b0)); + (* ORIG_CELL_NAME = "GEN_SEL_DELAY[2].sel_int_reg[2][0]" *) + FDRE #( + .INIT(1'b0)) + \GEN_SEL_DELAY[2].sel_int_reg[2][0] + (.C(vid_aclk), + .CE(1'b1), + .D(\sel_int[2]_1 ), + .Q(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] ), + .R(1'b0)); + (* ORIG_CELL_NAME = "GEN_SEL_DELAY[2].sel_int_reg[2][0]" *) + FDRE #( + .INIT(1'b0)) + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep + (.C(vid_aclk), + .CE(1'b1), + .D(\sel_int[2]_1 ), + .Q(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_SEL_DELAY[2].sel_int_reg[2][1] + (.C(vid_aclk), + .CE(1'b1), + .D(ipif_Addr[2]), + .Q(\sel_int[2]_1 ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_SEL_DELAY[4].sel_int_reg[4][0] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[4].sel_int_reg[4][1]_srl3_n_0 ), + .Q(\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] ), + .R(1'b0)); + (* srl_bus_name = "U0/U_VIDEO_CTRL/\AXI4_LITE_INTERFACE.GENR_MUX0/GEN_SEL_DELAY[4].sel_int_reg[4] " *) + (* srl_name = "U0/U_VIDEO_CTRL/\AXI4_LITE_INTERFACE.GENR_MUX0/GEN_SEL_DELAY[4].sel_int_reg[4][1]_srl3 " *) + SRL16E #( + .INIT(16'h0000)) + \GEN_SEL_DELAY[4].sel_int_reg[4][1]_srl3 + (.A0(1'b0), + .A1(1'b1), + .A2(1'b0), + .A3(1'b0), + .CE(1'b1), + .CLK(vid_aclk), + .D(ipif_Addr[3]), + .Q(\GEN_SEL_DELAY[4].sel_int_reg[4][1]_srl3_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_SEL_DELAY[5].sel_int_reg[5][0] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[5].sel_int_reg[5][1]_srl4_n_0 ), + .Q(\GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0] ), + .R(1'b0)); + (* srl_bus_name = "U0/U_VIDEO_CTRL/\AXI4_LITE_INTERFACE.GENR_MUX0/GEN_SEL_DELAY[5].sel_int_reg[5] " *) + (* srl_name = "U0/U_VIDEO_CTRL/\AXI4_LITE_INTERFACE.GENR_MUX0/GEN_SEL_DELAY[5].sel_int_reg[5][1]_srl4 " *) + SRL16E #( + .INIT(16'h0000)) + \GEN_SEL_DELAY[5].sel_int_reg[5][1]_srl4 + (.A0(1'b1), + .A1(1'b1), + .A2(1'b0), + .A3(1'b0), + .CE(1'b1), + .CLK(vid_aclk), + .D(ipif_Addr[4]), + .Q(\GEN_SEL_DELAY[5].sel_int_reg[5][1]_srl4_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][0] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[0] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][10] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[10] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][11] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[11] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][12] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[12] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][13] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[13] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][14] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[14] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][15] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[15] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [15]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][16] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[16] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][17] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[17] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][18] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[18] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][19] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[19] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][1] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[1] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][20] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[20] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][21] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[21] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][22] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[22] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [22]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][23] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[23] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [23]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][24] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[24] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [24]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][25] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[25] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [25]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][26] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[26] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [26]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][27] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[27] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [27]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][28] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[28] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [28]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][29] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[29] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [29]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][2] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[2] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][30] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[30] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [30]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][31] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][31] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [31]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][3] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[3] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][4] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[4] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][5] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[5] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][6] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[6] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][7] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[7] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][8] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[8] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][9] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat_reg[9] ), + .Q(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][0] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err_reg[0] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][10] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][10] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][11] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][11] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][12] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][12] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][13] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][13] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][14] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err_reg[14] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][15] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err_reg[15] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [15]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][16] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][16] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][17] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][17] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][18] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][18] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][19] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][19] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][1] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err_reg[1] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][20] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][20] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][21] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][21] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][22] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][22] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [22]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][23] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][23] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [23]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][24] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][24] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [24]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][25] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][25] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [25]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][26] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][26] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [26]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][27] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][27] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [27]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][28] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][28] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [28]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][29] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][29] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [29]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][2] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err_reg[2] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][30] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][30] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [30]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][31] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][31] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [31]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][3] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err_reg[3] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][4] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err_reg[4] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][5] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err_reg[5] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][6] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err_reg[6] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][7] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err_reg[7] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][8] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][8] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][9] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][9] ), + .Q(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[33].GEN_MUX_REG.data_out_reg_reg[33][26] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34] ), + .Q(\GEN_TREE.GEN_BRANCH[33].GEN_MUX_REG.data_out_reg_reg[33]_0 ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][0] + (.C(vid_aclk), + .CE(1'b1), + .D(\intr_status_int_reg[8] ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][10] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_hfp_start_int2_reg[10] ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_hfp_start_int2_reg[11] ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][12] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_221 ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][13] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_220 ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][14] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_219 ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][15] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_218 ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [15]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][16] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0fp_start_int_reg[0] ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][17] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0fp_start_int_reg[1] ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][18] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0fp_start_int_reg[2] ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][19] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0fp_start_int_reg[3] ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][1] + (.C(vid_aclk), + .CE(1'b1), + .D(\intr_status_int_reg[10] ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][20] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0fp_start_int_reg[4] ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][21] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0fp_start_int_reg[5] ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][22] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0fp_start_int_reg[6] ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [22]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][23] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0fp_start_int_reg[7] ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [23]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][24] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0fp_start_int_reg[8] ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [24]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][25] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0fp_start_int_reg[9] ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [25]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][26] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0fp_start_int_reg[10] ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [26]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][27] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_217 ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [27]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][28] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_216 ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [28]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][29] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_215 ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [29]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][2] + (.C(vid_aclk), + .CE(1'b1), + .D(\intr_status_int_reg[11] ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][30] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_214 ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [30]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_213 ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [31]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][3] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_hfp_start_int2_reg[3] ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][4] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_hfp_start_int2_reg[4] ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][5] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_hfp_start_int2_reg[5] ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][6] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_hfp_start_int2_reg[6] ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][7] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_hfp_start_int2_reg[7] ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][8] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_hfp_start_int2_reg[8] ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][9] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_hfp_start_int2_reg[9] ), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][0] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_212 ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][10] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_206 ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][11] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_205 ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][12] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_204 ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][13] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_203 ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][14] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_202 ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][15] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_201 ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [15]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][16] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_200 ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][17] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_199 ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][18] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_198 ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][19] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_197 ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][1] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_211 ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][20] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_196 ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][21] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_195 ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][22] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_194 ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [22]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][23] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_193 ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [23]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][24] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_192 ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [24]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][25] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_191 ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [25]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][26] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_190 ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [26]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][27] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_189 ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [27]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][28] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_188 ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [28]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][29] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_187 ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [29]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][2] + (.C(vid_aclk), + .CE(1'b1), + .D(\DET_VSYNC.det_vsync_pol_int_reg ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][30] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_186 ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [30]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][31] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_185 ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [31]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][3] + (.C(vid_aclk), + .CE(1'b1), + .D(\DET_HSYNC.det_hsync_pol_int_reg ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][4] + (.C(vid_aclk), + .CE(1'b1), + .D(\DET_HACTIVE.det_active_video_pol_int_reg ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][5] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_210 ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][6] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_209 ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][7] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_208 ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][8] + (.C(vid_aclk), + .CE(1'b1), + .D(\gen_v0chroma_start_reg[0] ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][9] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_207 ), + .Q(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][0] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0total_reg[0] ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0total_reg[10] ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][11] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_htotal_int2_reg[11] ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][12] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_184 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][13] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_183 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][14] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_182 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][15] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_181 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [15]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][16] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_180 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][17] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_179 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][18] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_178 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][19] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_177 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][1] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0total_reg[1] ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][20] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_176 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][21] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_175 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][22] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_174 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [22]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][23] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_173 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [23]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][24] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_172 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [24]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][25] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_171 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [25]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][26] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_170 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [26]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][27] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_169 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [27]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][28] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_168 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [28]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][29] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_167 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [29]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][2] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0total_reg[2] ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][30] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_166 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [30]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][31] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_165 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [31]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][3] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0total_reg[3] ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][4] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0total_reg[4] ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][5] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0total_reg[5] ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][6] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0total_reg[6] ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][7] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0total_reg[7] ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][8] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0total_reg[8] ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][9] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0total_reg[9] ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][0] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0fp_start_hori_int2_reg[0] ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][10] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0fp_start_hori_int2_reg[10] ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][11] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0fp_start_hori_int2_reg[11] ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][12] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_164 ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][13] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_163 ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][14] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_162 ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][15] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_161 ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [15]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][16] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0active_start_hori_int2_reg[0] ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][17] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0active_start_hori_int2_reg[1] ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][18] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0active_start_hori_int2_reg[2] ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][19] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0active_start_hori_int2_reg[3] ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][1] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0fp_start_hori_int2_reg[1] ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][20] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0active_start_hori_int2_reg[4] ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][21] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0active_start_hori_int2_reg[5] ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][22] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0active_start_hori_int2_reg[6] ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [22]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][23] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0active_start_hori_int2_reg[7] ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [23]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][24] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0active_start_hori_int2_reg[8] ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [24]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][25] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0active_start_hori_int2_reg[9] ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [25]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][26] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0active_start_hori_int2_reg[10] ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [26]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][27] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0active_start_hori_int2_reg[11] ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [27]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][28] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_160 ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [28]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][29] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_159 ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [29]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][2] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0fp_start_hori_int2_reg[2] ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][30] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_158 ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [30]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][31] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_157 ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [31]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][3] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0fp_start_hori_int2_reg[3] ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][4] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0fp_start_hori_int2_reg[4] ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][5] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0fp_start_hori_int2_reg[5] ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][6] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0fp_start_hori_int2_reg[6] ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][7] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0fp_start_hori_int2_reg[7] ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][8] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0fp_start_hori_int2_reg[8] ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][9] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0fp_start_hori_int2_reg[9] ), + .Q(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][0] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0sync_start_hori_int2_reg[0] ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][10] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0sync_start_hori_int2_reg[10] ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][11] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0sync_start_hori_int2_reg[11] ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][12] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_156 ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][13] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_155 ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][14] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_154 ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][15] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_153 ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [15]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][16] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0bp_start_hori_int2_reg[0] ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][17] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0bp_start_hori_int2_reg[1] ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][18] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0bp_start_hori_int2_reg[2] ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][19] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0bp_start_hori_int2_reg[3] ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][1] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0sync_start_hori_int2_reg[1] ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][20] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0bp_start_hori_int2_reg[4] ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][21] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0bp_start_hori_int2_reg[5] ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][22] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0bp_start_hori_int2_reg[6] ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [22]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][23] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0bp_start_hori_int2_reg[7] ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [23]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][24] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0bp_start_hori_int2_reg[8] ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [24]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][25] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0bp_start_hori_int2_reg[9] ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [25]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][26] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0bp_start_hori_int2_reg[10] ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [26]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][27] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0bp_start_hori_int2_reg[11] ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [27]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][28] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_152 ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [28]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][29] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_151 ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [29]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][2] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0sync_start_hori_int2_reg[2] ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][30] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_150 ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [30]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][31] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_149 ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [31]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][3] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0sync_start_hori_int2_reg[3] ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][4] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0sync_start_hori_int2_reg[4] ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][5] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0sync_start_hori_int2_reg[5] ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][6] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0sync_start_hori_int2_reg[6] ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][7] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0sync_start_hori_int2_reg[7] ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][8] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0sync_start_hori_int2_reg[8] ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][9] + (.C(vid_aclk), + .CE(1'b1), + .D(\det_v0sync_start_hori_int2_reg[9] ), + .Q(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [9]), + .R(1'b0)); + LUT5 #( + .INIT(32'h30BB3088)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[33].GEN_MUX_REG.data_out_reg_reg[33]_0 ), + .I1(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [0]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [0]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_2__0 + (.I0(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][0] ), + .I1(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][0] ), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][0] ), + .I4(\data_sync_reg[2][34]_0 ), + .I5(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0] ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [0]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [0]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [0]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [0]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_3__0 + (.I0(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][0] ), + .I1(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][0] ), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][0] ), + .I4(\data_sync_reg[2][34]_0 ), + .I5(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][0] ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'h88888888BBB888B8)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_2_n_0 ), + .I1(\GEN_SEL_DELAY[3].sel_int_reg[3][0] ), + .I2(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [10]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [10]), + .I5(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [10]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [10]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [10]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [10]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_2__0 + (.I0(core_regs[75]), + .I1(core_regs[53]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[31]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[9]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_3 + (.I0(core_regs[163]), + .I1(core_regs[141]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[119]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[97]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_3_n_0 )); + LUT6 #( + .INIT(64'h88888888BBB888B8)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_2_n_0 ), + .I1(\GEN_SEL_DELAY[3].sel_int_reg[3][0] ), + .I2(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [11]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [11]), + .I5(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [11]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [11]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [11]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [11]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_2__0 + (.I0(core_regs[76]), + .I1(core_regs[54]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[32]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[10]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_3 + (.I0(core_regs[164]), + .I1(core_regs[142]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[120]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[98]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_3_n_0 )); + LUT6 #( + .INIT(64'h88888888BBB888B8)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_2_n_0 ), + .I1(\GEN_SEL_DELAY[3].sel_int_reg[3][0] ), + .I2(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [12]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [12]), + .I5(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [12]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [12]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [12]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [12]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_2__0 + (.I0(\core_status_regs[3] [0]), + .I1(\core_status_regs[2] [0]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[1] [0]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(\core_status_regs[0] [0]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_3 + (.I0(\core_status_regs[7] [0]), + .I1(\core_status_regs[6] [0]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[5] [0]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(\core_status_regs[4] [0]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_3_n_0 )); + LUT6 #( + .INIT(64'h88888888BBB888B8)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_2_n_0 ), + .I1(\GEN_SEL_DELAY[3].sel_int_reg[3][0] ), + .I2(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [13]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [13]), + .I5(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [13]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [13]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [13]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [13]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_2__0 + (.I0(\core_status_regs[3] [1]), + .I1(\core_status_regs[2] [1]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[1] [1]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(\core_status_regs[0] [1]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_3 + (.I0(\core_status_regs[7] [1]), + .I1(\core_status_regs[6] [1]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[5] [1]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(\core_status_regs[4] [1]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_3_n_0 )); + LUT6 #( + .INIT(64'h88888888BBB888B8)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_2_n_0 ), + .I1(\GEN_SEL_DELAY[3].sel_int_reg[3][0] ), + .I2(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [14]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [14]), + .I5(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [14]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [14]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [14]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [14]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_2__0 + (.I0(\core_status_regs[3] [2]), + .I1(\core_status_regs[2] [2]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[1] [2]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(\core_status_regs[0] [2]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_3 + (.I0(\core_status_regs[7] [2]), + .I1(\core_status_regs[6] [2]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[5] [2]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(\core_status_regs[4] [2]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_3_n_0 )); + LUT6 #( + .INIT(64'h88888888BBB888B8)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_2_n_0 ), + .I1(\GEN_SEL_DELAY[3].sel_int_reg[3][0] ), + .I2(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [15]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [15]), + .I5(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [15]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [15]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [15]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [15]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_2__0 + (.I0(\core_status_regs[3] [3]), + .I1(\core_status_regs[2] [3]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[1] [3]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(\core_status_regs[0] [3]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_3 + (.I0(\core_status_regs[7] [3]), + .I1(\core_status_regs[6] [3]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[5] [3]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(\core_status_regs[4] [3]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_3_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[33].GEN_MUX_REG.data_out_reg_reg[33]_0 ), + .I1(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [16]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [16]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_2__0 + (.I0(core_regs[77]), + .I1(core_regs[55]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[33]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[11]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [16]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [16]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [16]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [16]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_3__0 + (.I0(core_regs[165]), + .I1(core_regs[143]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[121]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[99]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'h88888888BBB888B8)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_2_n_0 ), + .I1(\GEN_SEL_DELAY[3].sel_int_reg[3][0] ), + .I2(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [17]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [17]), + .I5(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [17]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [17]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [17]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [17]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_2__0 + (.I0(core_regs[78]), + .I1(core_regs[56]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[34]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[12]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_3 + (.I0(core_regs[166]), + .I1(core_regs[144]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[122]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[100]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_3_n_0 )); + LUT6 #( + .INIT(64'h88888888BBB888B8)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_2_n_0 ), + .I1(\GEN_SEL_DELAY[3].sel_int_reg[3][0] ), + .I2(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [18]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [18]), + .I5(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [18]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [18]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [18]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [18]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_2__0 + (.I0(core_regs[79]), + .I1(core_regs[57]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[35]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[13]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_3 + (.I0(core_regs[167]), + .I1(core_regs[145]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[123]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[101]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_3_n_0 )); + LUT6 #( + .INIT(64'h88888888BBB888B8)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_2_n_0 ), + .I1(\GEN_SEL_DELAY[3].sel_int_reg[3][0] ), + .I2(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [19]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [19]), + .I5(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [19]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [19]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [19]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [19]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_2__0 + (.I0(core_regs[80]), + .I1(core_regs[58]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[36]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[14]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_3 + (.I0(core_regs[168]), + .I1(core_regs[146]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[124]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[102]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_3_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[33].GEN_MUX_REG.data_out_reg_reg[33]_0 ), + .I1(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [1]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [1]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_2__0 + (.I0(core_regs[66]), + .I1(core_regs[44]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[22]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[0]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [1]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [1]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [1]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [1]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_3__0 + (.I0(core_regs[154]), + .I1(core_regs[132]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[110]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[88]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'h88888888BBB888B8)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_2_n_0 ), + .I1(\GEN_SEL_DELAY[3].sel_int_reg[3][0] ), + .I2(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [20]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [20]), + .I5(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [20]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [20]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [20]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [20]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_2__0 + (.I0(core_regs[81]), + .I1(core_regs[59]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[37]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[15]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_3 + (.I0(core_regs[169]), + .I1(core_regs[147]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[125]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[103]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_3_n_0 )); + LUT6 #( + .INIT(64'h88888888BBB888B8)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_2_n_0 ), + .I1(\GEN_SEL_DELAY[3].sel_int_reg[3][0] ), + .I2(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [21]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [21]), + .I5(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [21]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [21]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [21]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [21]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_2__0 + (.I0(core_regs[82]), + .I1(core_regs[60]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[38]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[16]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_3 + (.I0(core_regs[170]), + .I1(core_regs[148]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[126]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[104]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_3_n_0 )); + LUT6 #( + .INIT(64'h88888888BBB888B8)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_2_n_0 ), + .I1(\GEN_SEL_DELAY[3].sel_int_reg[3][0] ), + .I2(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [22]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [22]), + .I5(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [22]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [22]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [22]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [22]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_2__0 + (.I0(core_regs[83]), + .I1(core_regs[61]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[39]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[17]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_3 + (.I0(core_regs[171]), + .I1(core_regs[149]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[127]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[105]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_3_n_0 )); + LUT6 #( + .INIT(64'h88888888BBB888B8)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_2_n_0 ), + .I1(\GEN_SEL_DELAY[3].sel_int_reg[3][0] ), + .I2(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [23]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [23]), + .I5(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [23]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [23]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [23]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [23]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_2__0 + (.I0(core_regs[84]), + .I1(core_regs[62]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[40]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[18]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_3 + (.I0(core_regs[172]), + .I1(core_regs[150]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[128]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[106]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_3_n_0 )); + LUT6 #( + .INIT(64'h88888888BBB888B8)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_2_n_0 ), + .I1(\GEN_SEL_DELAY[3].sel_int_reg[3][0] ), + .I2(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [24]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [24]), + .I5(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [24]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [24]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [24]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [24]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_2__0 + (.I0(core_regs[85]), + .I1(core_regs[63]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[41]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[19]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_3 + (.I0(core_regs[173]), + .I1(core_regs[151]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[129]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[107]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_3_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[33].GEN_MUX_REG.data_out_reg_reg[33]_0 ), + .I1(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [25]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [25]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_2__0 + (.I0(core_regs[86]), + .I1(core_regs[64]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[42]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[20]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [25]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [25]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [25]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [25]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_3__0 + (.I0(core_regs[174]), + .I1(core_regs[152]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[130]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[108]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_3__0_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[33].GEN_MUX_REG.data_out_reg_reg[33]_0 ), + .I1(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [26]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [26]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_2__0 + (.I0(core_regs[87]), + .I1(core_regs[65]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[43]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[21]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [26]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [26]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [26]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [26]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_3__0 + (.I0(core_regs[175]), + .I1(core_regs[153]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[131]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[109]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'h88888888BBB888B8)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_2_n_0 ), + .I1(\GEN_SEL_DELAY[3].sel_int_reg[3][0] ), + .I2(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [27]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [27]), + .I5(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [27]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [27]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [27]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [27]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_2__0 + (.I0(\core_status_regs[3] [4]), + .I1(\core_status_regs[2] [4]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[1] [4]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(\core_status_regs[0] [4]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_3 + (.I0(\core_status_regs[7] [4]), + .I1(\core_status_regs[6] [4]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[5] [4]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(\core_status_regs[4] [4]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_3_n_0 )); + LUT6 #( + .INIT(64'h88888888BBB888B8)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_2_n_0 ), + .I1(\GEN_SEL_DELAY[3].sel_int_reg[3][0] ), + .I2(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [28]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [28]), + .I5(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [28]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [28]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [28]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [28]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_2__0 + (.I0(\core_status_regs[3] [5]), + .I1(\core_status_regs[2] [5]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[1] [5]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(\core_status_regs[0] [5]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_3 + (.I0(\core_status_regs[7] [5]), + .I1(\core_status_regs[6] [5]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[5] [5]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(\core_status_regs[4] [5]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_3_n_0 )); + LUT6 #( + .INIT(64'h88888888BBB888B8)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_2_n_0 ), + .I1(\GEN_SEL_DELAY[3].sel_int_reg[3][0] ), + .I2(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [29]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [29]), + .I5(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [29]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [29]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [29]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [29]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_2__0 + (.I0(\core_status_regs[3] [6]), + .I1(\core_status_regs[2] [6]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[1] [6]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(\core_status_regs[0] [6]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_3 + (.I0(\core_status_regs[7] [6]), + .I1(\core_status_regs[6] [6]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[5] [6]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(\core_status_regs[4] [6]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_3_n_0 )); + LUT6 #( + .INIT(64'h88888888BBB888B8)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_2_n_0 ), + .I1(\GEN_SEL_DELAY[3].sel_int_reg[3][0] ), + .I2(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [2]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [2]), + .I5(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [2]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [2]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [2]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [2]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_2__0 + (.I0(core_regs[67]), + .I1(core_regs[45]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[23]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[1]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_3 + (.I0(core_regs[155]), + .I1(core_regs[133]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[111]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[89]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_3_n_0 )); + LUT6 #( + .INIT(64'h88888888BBB888B8)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_2_n_0 ), + .I1(\GEN_SEL_DELAY[3].sel_int_reg[3][0] ), + .I2(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [30]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [30]), + .I5(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [30]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [30]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [30]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [30]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_2__0 + (.I0(\core_status_regs[3] [7]), + .I1(\core_status_regs[2] [7]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[1] [7]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(\core_status_regs[0] [7]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_3 + (.I0(\core_status_regs[7] [7]), + .I1(\core_status_regs[6] [7]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[5] [7]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(\core_status_regs[4] [7]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_3_n_0 )); + LUT6 #( + .INIT(64'h88888888BBB888B8)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_2_n_0 ), + .I1(\GEN_SEL_DELAY[3].sel_int_reg[3][0] ), + .I2(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [31]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [31]), + .I5(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [31]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [31]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [31]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [31]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_2__0 + (.I0(\core_status_regs[3] [8]), + .I1(\core_status_regs[2] [8]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[1] [8]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(\core_status_regs[0] [8]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_3 + (.I0(\core_status_regs[7] [8]), + .I1(\core_status_regs[6] [8]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[5] [8]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(\core_status_regs[4] [8]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_3_n_0 )); + LUT5 #( + .INIT(32'h30BB3088)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[33].GEN_MUX_REG.data_out_reg_reg[33]_0 ), + .I1(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [3]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [3]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_2__0 + (.I0(core_regs[68]), + .I1(core_regs[46]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[24]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[2]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [3]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [3]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [3]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [3]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_3__0 + (.I0(core_regs[156]), + .I1(core_regs[134]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[112]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[90]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'h88888888BBB888B8)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_2_n_0 ), + .I1(\GEN_SEL_DELAY[3].sel_int_reg[3][0] ), + .I2(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [4]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [4]), + .I5(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [4]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [4]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [4]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [4]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_2__0 + (.I0(core_regs[69]), + .I1(core_regs[47]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[25]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[3]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_3 + (.I0(core_regs[157]), + .I1(core_regs[135]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[113]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[91]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_3_n_0 )); + LUT6 #( + .INIT(64'h88888888BBB888B8)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_2_n_0 ), + .I1(\GEN_SEL_DELAY[3].sel_int_reg[3][0] ), + .I2(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [5]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [5]), + .I5(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [5]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [5]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [5]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [5]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_2__0 + (.I0(core_regs[70]), + .I1(core_regs[48]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[26]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[4]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_3 + (.I0(core_regs[158]), + .I1(core_regs[136]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[114]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[92]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_3_n_0 )); + LUT6 #( + .INIT(64'h88888888BBB888B8)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_2_n_0 ), + .I1(\GEN_SEL_DELAY[3].sel_int_reg[3][0] ), + .I2(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [6]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [6]), + .I5(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [6]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [6]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [6]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [6]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_2__0 + (.I0(core_regs[71]), + .I1(core_regs[49]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[27]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[5]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_3 + (.I0(core_regs[159]), + .I1(core_regs[137]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[115]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[93]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_3_n_0 )); + LUT6 #( + .INIT(64'h88888888BBB888B8)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_2_n_0 ), + .I1(\GEN_SEL_DELAY[3].sel_int_reg[3][0] ), + .I2(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [7]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [7]), + .I5(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [7]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [7]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [7]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [7]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_2__0 + (.I0(core_regs[72]), + .I1(core_regs[50]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[28]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[6]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_3 + (.I0(core_regs[160]), + .I1(core_regs[138]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[116]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[94]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_3_n_0 )); + LUT6 #( + .INIT(64'h88888888BBB888B8)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_2_n_0 ), + .I1(\GEN_SEL_DELAY[3].sel_int_reg[3][0] ), + .I2(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [8]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [8]), + .I5(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [8]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [8]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [8]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [8]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_2__0 + (.I0(core_regs[73]), + .I1(core_regs[51]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[29]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[7]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_3 + (.I0(core_regs[161]), + .I1(core_regs[139]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[117]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[95]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_3_n_0 )); + LUT6 #( + .INIT(64'h88888888BBB888B8)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_2_n_0 ), + .I1(\GEN_SEL_DELAY[3].sel_int_reg[3][0] ), + .I2(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20 [9]), + .I3(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19 [9]), + .I5(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15 [9]), + .I1(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16 [9]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17 [9]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18 [9]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_2__0 + (.I0(core_regs[74]), + .I1(core_regs[52]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[30]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[8]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_3 + (.I0(core_regs[162]), + .I1(core_regs[140]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[118]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[96]), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_3_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][0] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][0]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [0]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][0]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][0]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][0]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][0]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][10] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [10]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][10]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][10]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][11] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [11]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][11]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][11]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][12] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [12]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][12]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][12]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][13] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [13]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][13]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][13]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][14] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [14]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][14]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][14]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][15] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [15]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][15]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][15]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][16] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][16]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [16]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][16]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][16]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][16]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][16]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][17] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [17]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][17]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][17]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][18] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [18]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][18]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][18]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][19] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [19]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][19]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][19]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][1] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][1]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [1]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][1]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][1]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][1]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][1]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][20] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [20]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][20]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][20]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][21] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [21]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][21]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][21]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][22] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [22]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][22]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][22]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][23] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [23]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][23]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][23]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][24] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [24]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][24]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][24]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][25] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][25]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [25]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][25]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][25]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][25]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][25]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][26] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][26]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [26]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][26]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][26]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][26]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][26]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][27] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [27]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][27]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][27]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][28] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [28]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][28]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][28]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][29] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [29]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][29]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][29]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][2] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [2]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][2]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][2]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][30] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [30]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][30]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][30]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][31] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [31]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][31]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][31]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][3] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][3]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [3]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][3]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][3]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][3]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][3]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][4] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [4]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][4]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][4]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][5] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [5]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][5]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][5]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][6] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [6]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][6]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][6]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][7] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [7]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][7]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][7]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][8] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [8]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][8]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][8]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][9] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21 [9]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][9]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][9]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][0] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_148 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][10] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_138 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][11] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_137 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][12] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_136 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][13] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_135 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][14] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_134 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][15] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_133 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [15]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][16] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_132 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][17] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_131 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][18] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_130 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][19] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_129 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][1] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_147 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][20] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_128 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][21] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_127 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][22] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_126 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [22]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][23] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_125 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [23]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][24] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_124 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [24]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][25] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_123 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [25]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][26] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_122 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [26]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][27] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_121 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [27]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][28] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_120 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [28]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][29] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_119 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [29]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][2] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_146 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][30] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_118 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [30]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][31] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_117 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [31]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][3] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_145 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][4] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_144 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][5] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_143 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][6] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_142 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][7] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_141 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][8] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_140 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][9] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_139 ), + .Q(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][0] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_116 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][10] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_106 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][11] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_105 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][12] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_104 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][13] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_103 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][14] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_102 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][15] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_101 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [15]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][16] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_100 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][17] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_99 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][18] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_98 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][19] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_97 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][1] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_115 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][20] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_96 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][21] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_95 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][22] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_94 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [22]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][23] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_93 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [23]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][24] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_92 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [24]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][25] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_91 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [25]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][26] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_90 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [26]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][27] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_89 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [27]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][28] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_88 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [28]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][29] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_87 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [29]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][2] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_114 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][30] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_86 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [30]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][31] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_85 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [31]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][3] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_113 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][4] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_112 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][5] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_111 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][6] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_110 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][7] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_109 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][8] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_108 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][9] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_107 ), + .Q(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][0] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_84 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][10] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_74 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][11] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_73 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][12] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_72 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][13] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_71 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][14] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_70 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][15] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_69 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [15]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][16] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_68 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][17] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_67 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][18] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_66 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][19] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_65 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][1] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_83 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][20] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_64 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][21] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_63 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][22] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_62 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [22]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][23] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_61 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [23]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][24] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_60 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [24]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][25] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_59 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [25]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][26] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_58 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [26]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][27] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_57 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [27]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][28] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_56 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [28]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][29] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_55 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [29]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][2] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_82 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][30] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_54 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [30]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][31] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_53 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [31]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][3] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_81 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][4] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_80 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][5] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_79 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][6] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_78 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][7] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_77 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][8] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_76 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][9] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_75 ), + .Q(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][0] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][0] ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][10] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][10] ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][11] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][11] ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][12] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][12] ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][13] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_52 ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][14] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_51 ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][15] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_50 ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [15]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][16] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][16] ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][17] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][17] ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][18] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][18] ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][19] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][19] ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][1] + (.C(vid_aclk), + .CE(1'b1), + .D(\intr_status_int_reg[12] ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][20] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][20] ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][21] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][21] ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][22] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][22] ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [22]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][23] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][23] ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [23]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][24] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][24] ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [24]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][25] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][25] ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [25]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][26] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][26] ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [26]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][27] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][27] ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [27]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][28] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [28]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][29] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_49 ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [29]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][2] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][2] ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][30] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_48 ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [30]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][31] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_47 ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [31]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][3] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][3] ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][4] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][4] ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][5] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][5] ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][6] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][6] ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][7] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][7] ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][8] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][8] ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][9] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][9] ), + .Q(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][0] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][0] ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][10] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_46 ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][11] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_45 ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][12] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_44 ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][13] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_43 ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][14] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_42 ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][15] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_41 ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [15]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][16] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_40 ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][17] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_39 ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][18] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_38 ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][19] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_37 ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][1] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][1] ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][20] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_36 ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][21] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_35 ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][22] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_34 ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [22]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][23] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_33 ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [23]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][24] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_32 ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [24]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][25] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_31 ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [25]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][26] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_30 ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [26]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][27] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_29 ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [27]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][28] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_28 ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [28]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][29] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_27 ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [29]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][2] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][2] ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][30] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_26 ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [30]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][31] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_25 ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [31]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][3] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][3] ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][4] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][4] ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][5] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][5] ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][6] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6] ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][7] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][7] ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][8] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][8] ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][9] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9] ), + .Q(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][0] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][0] ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][10] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][10] ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][11] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][11] ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][12] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][12] ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][13] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_24 ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][14] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_23 ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][15] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_22 ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [15]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][16] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][16] ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][17] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][17] ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][18] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][18] ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][19] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][19] ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][1] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][1] ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][20] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][20] ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][21] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][21] ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][22] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][22] ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [22]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][23] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][23] ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [23]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][24] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][24] ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [24]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][25] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][25] ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [25]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][26] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][26] ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [26]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][27] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][27] ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [27]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][28] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [28]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][29] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_21 ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [29]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][2] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][2] ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][30] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_20 ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [30]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][31] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_19 ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [31]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][3] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][3] ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][4] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][4] ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][5] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][5] ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][6] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][6] ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][7] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][7] ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][8] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][8] ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][9] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][9] ), + .Q(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][0] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][0] ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][10] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][10] ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][11] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][11] ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][12] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][12] ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][13] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_18 ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][14] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_17 ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][15] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_16 ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [15]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][16] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][16] ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][17] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][17] ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][18] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][18] ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][19] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][19] ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][1] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][1] ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][20] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][20] ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][21] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][21] ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][22] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][22] ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [22]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][23] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][23] ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [23]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][24] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][24] ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [24]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][25] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][25] ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [25]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][26] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][26] ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [26]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][27] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][27] ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [27]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][28] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [28]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][29] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_15 ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [29]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][2] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][2] ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][30] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_14 ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [30]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][31] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_13 ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [31]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][3] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][3] ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][4] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][4] ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][5] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][5] ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][6] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][6] ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][7] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][7] ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][8] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][8] ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][9] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][9] ), + .Q(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][0] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][0] ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][10] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][10] ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][11] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][11] ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][12] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][12] ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][13] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_12 ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][14] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_11 ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][15] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_10 ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [15]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][16] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][16] ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][17] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][17] ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][18] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][18] ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][19] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][19] ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][1] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][1] ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][20] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][20] ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][21] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][21] ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][22] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][22] ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [22]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][23] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][23] ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [23]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][24] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][24] ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [24]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][25] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][25] ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [25]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][26] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][26] ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [26]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][27] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][27] ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [27]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][28] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [28]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][29] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_9 ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [29]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][2] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][2] ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][30] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_8 ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [30]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][31] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_7 ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [31]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][3] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][3] ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][4] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][4] ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][5] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][5] ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][6] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][6] ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][7] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][7] ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][8] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][8] ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][9] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][9] ), + .Q(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][0] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][0] ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][10] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][10] ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][11] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][11] ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][12] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][12] ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][13] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_6 ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][14] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_5 ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][15] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_4 ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [15]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][16] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][16] ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][17] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][17] ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][18] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][18] ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][19] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][19] ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][1] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][1] ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][20] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][20] ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][21] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][21] ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][22] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][22] ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [22]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][23] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][23] ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [23]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][24] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][24] ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [24]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][25] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][25] ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [25]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][26] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][26] ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [26]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][27] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][27] ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [27]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][28] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][28] ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [28]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][29] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_3 ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [29]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][2] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][2] ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][30] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_2 ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [30]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][31] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync_reg[2][34]_1 ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [31]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][3] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][3] ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][4] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][4] ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][5] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][5] ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][6] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][6] ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][7] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][7] ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][8] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][8] ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][9] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][9] ), + .Q(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][0] + (.C(vid_aclk), + .CE(1'b1), + .D(Q[0]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [0]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][10] + (.C(vid_aclk), + .CE(1'b1), + .D(Q[10]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [10]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][11] + (.C(vid_aclk), + .CE(1'b1), + .D(Q[11]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [11]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][12] + (.C(vid_aclk), + .CE(1'b1), + .D(Q[12]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [12]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][13] + (.C(vid_aclk), + .CE(1'b1), + .D(\time_status_regs[28] [0]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [13]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][14] + (.C(vid_aclk), + .CE(1'b1), + .D(\time_status_regs[28] [1]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [14]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][15] + (.C(vid_aclk), + .CE(1'b1), + .D(\time_status_regs[28] [2]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [15]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][16] + (.C(vid_aclk), + .CE(1'b1), + .D(Q[13]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [16]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][17] + (.C(vid_aclk), + .CE(1'b1), + .D(Q[14]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [17]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][18] + (.C(vid_aclk), + .CE(1'b1), + .D(Q[15]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [18]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][19] + (.C(vid_aclk), + .CE(1'b1), + .D(Q[16]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [19]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][1] + (.C(vid_aclk), + .CE(1'b1), + .D(Q[1]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [1]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][20] + (.C(vid_aclk), + .CE(1'b1), + .D(Q[17]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [20]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][21] + (.C(vid_aclk), + .CE(1'b1), + .D(Q[18]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [21]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][22] + (.C(vid_aclk), + .CE(1'b1), + .D(Q[19]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [22]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][23] + (.C(vid_aclk), + .CE(1'b1), + .D(Q[20]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [23]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][24] + (.C(vid_aclk), + .CE(1'b1), + .D(Q[21]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [24]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][25] + (.C(vid_aclk), + .CE(1'b1), + .D(Q[22]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [25]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][26] + (.C(vid_aclk), + .CE(1'b1), + .D(Q[23]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [26]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][27] + (.C(vid_aclk), + .CE(1'b1), + .D(Q[24]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [27]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][28] + (.C(vid_aclk), + .CE(1'b1), + .D(Q[25]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [28]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][29] + (.C(vid_aclk), + .CE(1'b1), + .D(\time_status_regs[28] [3]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [29]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][2] + (.C(vid_aclk), + .CE(1'b1), + .D(Q[2]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [2]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][30] + (.C(vid_aclk), + .CE(1'b1), + .D(\time_status_regs[28] [4]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [30]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][31] + (.C(vid_aclk), + .CE(1'b1), + .D(\time_status_regs[28] [5]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [31]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][3] + (.C(vid_aclk), + .CE(1'b1), + .D(Q[3]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [3]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][4] + (.C(vid_aclk), + .CE(1'b1), + .D(Q[4]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [4]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][5] + (.C(vid_aclk), + .CE(1'b1), + .D(Q[5]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [5]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][6] + (.C(vid_aclk), + .CE(1'b1), + .D(Q[6]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [6]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][7] + (.C(vid_aclk), + .CE(1'b1), + .D(Q[7]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [7]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][8] + (.C(vid_aclk), + .CE(1'b1), + .D(Q[8]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [8]), + .R(ipif_Addr[0])); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][9] + (.C(vid_aclk), + .CE(1'b1), + .D(Q[9]), + .Q(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [9]), + .R(ipif_Addr[0])); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [0]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [0]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [0]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [0]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_2__0 + (.I0(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][0] ), + .I1(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][0] ), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][0] ), + .I4(\data_sync_reg[2][34]_0 ), + .I5(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][0] ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [0]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [0]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [0]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [0]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_3__0 + (.I0(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][0] ), + .I1(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][0] ), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][0] ), + .I4(\data_sync_reg[2][34]_0 ), + .I5(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][0] ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [10]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [10]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [10]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [10]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_2__0 + (.I0(core_regs[251]), + .I1(core_regs[229]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[207]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(core_regs[185]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [10]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [10]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [10]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [10]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_3__0 + (.I0(core_regs[339]), + .I1(core_regs[317]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[295]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(core_regs[273]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [11]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [11]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [11]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [11]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_2__0 + (.I0(core_regs[252]), + .I1(core_regs[230]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[208]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(core_regs[186]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [11]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [11]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [11]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [11]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_3__0 + (.I0(core_regs[340]), + .I1(core_regs[318]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[296]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(core_regs[274]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [12]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [12]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [12]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [12]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_2__0 + (.I0(\core_status_regs[11] [0]), + .I1(\core_status_regs[10] [0]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[9] [0]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(\core_status_regs[8] [0]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [12]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [12]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [12]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [12]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_3__0 + (.I0(\core_status_regs[15] [0]), + .I1(\core_status_regs[14] [0]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[13] [0]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(\core_status_regs[12] [0]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [13]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [13]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [13]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [13]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_2__0 + (.I0(\core_status_regs[11] [1]), + .I1(\core_status_regs[10] [1]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[9] [1]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(\core_status_regs[8] [1]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [13]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [13]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [13]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [13]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_3__0 + (.I0(\core_status_regs[15] [1]), + .I1(\core_status_regs[14] [1]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[13] [1]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(\core_status_regs[12] [1]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [14]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [14]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [14]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [14]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_2__0 + (.I0(\core_status_regs[11] [2]), + .I1(\core_status_regs[10] [2]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[9] [2]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(\core_status_regs[8] [2]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [14]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [14]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [14]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [14]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_3__0 + (.I0(\core_status_regs[15] [2]), + .I1(\core_status_regs[14] [2]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[13] [2]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(\core_status_regs[12] [2]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [15]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [15]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [15]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [15]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_2__0 + (.I0(\core_status_regs[11] [3]), + .I1(\core_status_regs[10] [3]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[9] [3]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(\core_status_regs[8] [3]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [15]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [15]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [15]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [15]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_3__0 + (.I0(\core_status_regs[15] [3]), + .I1(\core_status_regs[14] [3]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[13] [3]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(\core_status_regs[12] [3]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [16]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [16]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [16]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [16]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_2__0 + (.I0(core_regs[253]), + .I1(core_regs[231]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[209]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(core_regs[187]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [16]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [16]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [16]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [16]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_3__0 + (.I0(core_regs[341]), + .I1(core_regs[319]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[297]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(core_regs[275]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [17]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [17]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [17]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [17]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_2__0 + (.I0(core_regs[254]), + .I1(core_regs[232]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[210]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(core_regs[188]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [17]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [17]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [17]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [17]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_3__0 + (.I0(core_regs[342]), + .I1(core_regs[320]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[298]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(core_regs[276]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [18]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [18]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [18]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [18]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_2__0 + (.I0(core_regs[255]), + .I1(core_regs[233]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[211]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(core_regs[189]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [18]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [18]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [18]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [18]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_3__0 + (.I0(core_regs[343]), + .I1(core_regs[321]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[299]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(core_regs[277]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [19]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [19]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [19]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [19]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_2__0 + (.I0(core_regs[256]), + .I1(core_regs[234]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[212]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(core_regs[190]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [19]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [19]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [19]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [19]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_3__0 + (.I0(core_regs[344]), + .I1(core_regs[322]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[300]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(core_regs[278]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [1]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [1]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [1]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [1]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_2__0 + (.I0(core_regs[242]), + .I1(core_regs[220]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[198]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[176]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [1]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [1]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [1]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [1]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_3__0 + (.I0(core_regs[330]), + .I1(core_regs[308]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[286]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[264]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [20]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [20]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [20]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [20]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_2__0 + (.I0(core_regs[257]), + .I1(core_regs[235]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[213]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(core_regs[191]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [20]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [20]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [20]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [20]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_3__0 + (.I0(core_regs[345]), + .I1(core_regs[323]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[301]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(core_regs[279]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [21]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [21]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [21]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [21]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_2__0 + (.I0(core_regs[258]), + .I1(core_regs[236]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[214]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(core_regs[192]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [21]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [21]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [21]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [21]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_3__0 + (.I0(core_regs[346]), + .I1(core_regs[324]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[302]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(core_regs[280]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [22]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [22]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [22]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [22]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_2__0 + (.I0(core_regs[259]), + .I1(core_regs[237]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[215]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(core_regs[193]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [22]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [22]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [22]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [22]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_3__0 + (.I0(core_regs[347]), + .I1(core_regs[325]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[303]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(core_regs[281]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [23]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [23]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [23]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [23]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_2__0 + (.I0(core_regs[260]), + .I1(core_regs[238]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[216]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(core_regs[194]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [23]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [23]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [23]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [23]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_3__0 + (.I0(core_regs[348]), + .I1(core_regs[326]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[304]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(core_regs[282]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [24]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [24]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [24]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [24]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_2__0 + (.I0(core_regs[261]), + .I1(core_regs[239]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[217]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(core_regs[195]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [24]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [24]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [24]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [24]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_3__0 + (.I0(core_regs[349]), + .I1(core_regs[327]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[305]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(core_regs[283]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [25]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [25]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [25]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [25]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_2__0 + (.I0(core_regs[262]), + .I1(core_regs[240]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[218]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(core_regs[196]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [25]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [25]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [25]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [25]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_3__0 + (.I0(core_regs[350]), + .I1(core_regs[328]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[306]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(core_regs[284]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [26]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [26]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [26]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [26]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_2__0 + (.I0(core_regs[263]), + .I1(core_regs[241]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[219]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(core_regs[197]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [26]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [26]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [26]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [26]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_3__0 + (.I0(core_regs[351]), + .I1(core_regs[329]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[307]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(core_regs[285]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [27]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [27]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [27]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [27]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_2__0 + (.I0(\core_status_regs[11] [4]), + .I1(\core_status_regs[10] [4]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[9] [4]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(\core_status_regs[8] [4]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [27]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [27]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [27]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [27]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_3__0 + (.I0(\core_status_regs[15] [4]), + .I1(\core_status_regs[14] [4]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[13] [4]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(\core_status_regs[12] [4]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [28]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [28]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [28]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [28]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_2__0 + (.I0(\core_status_regs[11] [5]), + .I1(\core_status_regs[10] [5]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[9] [5]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(\core_status_regs[8] [5]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [28]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [28]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [28]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [28]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_3__0 + (.I0(\core_status_regs[15] [5]), + .I1(\core_status_regs[14] [5]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[13] [5]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(\core_status_regs[12] [5]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [29]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [29]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [29]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [29]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_2__0 + (.I0(\core_status_regs[11] [6]), + .I1(\core_status_regs[10] [6]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[9] [6]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(\core_status_regs[8] [6]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [29]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [29]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [29]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [29]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_3__0 + (.I0(\core_status_regs[15] [6]), + .I1(\core_status_regs[14] [6]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[13] [6]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(\core_status_regs[12] [6]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [2]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [2]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [2]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [2]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_2__0 + (.I0(core_regs[243]), + .I1(core_regs[221]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[199]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[177]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [2]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [2]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [2]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [2]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_3__0 + (.I0(core_regs[331]), + .I1(core_regs[309]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[287]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[265]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [30]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [30]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [30]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [30]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_2__0 + (.I0(\core_status_regs[11] [7]), + .I1(\core_status_regs[10] [7]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[9] [7]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(\core_status_regs[8] [7]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [30]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [30]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [30]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [30]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_3__0 + (.I0(\core_status_regs[15] [7]), + .I1(\core_status_regs[14] [7]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[13] [7]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(\core_status_regs[12] [7]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [31]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [31]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [31]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [31]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_2__0 + (.I0(\core_status_regs[11] [8]), + .I1(\core_status_regs[10] [8]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[9] [8]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(\core_status_regs[8] [8]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [31]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [31]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [31]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [31]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_3__0 + (.I0(\core_status_regs[15] [8]), + .I1(\core_status_regs[14] [8]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(\core_status_regs[13] [8]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(\core_status_regs[12] [8]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [3]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [3]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [3]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [3]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_2__0 + (.I0(core_regs[244]), + .I1(core_regs[222]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[200]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[178]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [3]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [3]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [3]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [3]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_3__0 + (.I0(core_regs[332]), + .I1(core_regs[310]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[288]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[266]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [4]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [4]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [4]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [4]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_2__0 + (.I0(core_regs[245]), + .I1(core_regs[223]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[201]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[179]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [4]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [4]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [4]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [4]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_3__0 + (.I0(core_regs[333]), + .I1(core_regs[311]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[289]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[267]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [5]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [5]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [5]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [5]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_2__0 + (.I0(core_regs[246]), + .I1(core_regs[224]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[202]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[180]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [5]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [5]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [5]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [5]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_3__0 + (.I0(core_regs[334]), + .I1(core_regs[312]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[290]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[268]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [6]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [6]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [6]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [6]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_2__0 + (.I0(core_regs[247]), + .I1(core_regs[225]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[203]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[181]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [6]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [6]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [6]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [6]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_3__0 + (.I0(core_regs[335]), + .I1(core_regs[313]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[291]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[269]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [7]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [7]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [7]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [7]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_2__0 + (.I0(core_regs[248]), + .I1(core_regs[226]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[204]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[182]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [7]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [7]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [7]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [7]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_3__0 + (.I0(core_regs[336]), + .I1(core_regs[314]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[292]), + .I4(\data_sync_reg[2][34]_0 ), + .I5(core_regs[270]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [8]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [8]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [8]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [8]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_2__0 + (.I0(core_regs[249]), + .I1(core_regs[227]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[205]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(core_regs[183]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [8]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [8]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [8]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [8]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_3__0 + (.I0(core_regs[337]), + .I1(core_regs[315]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[293]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(core_regs[271]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10 [9]), + .I1(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11 [9]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12 [9]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13 [9]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_2__0 + (.I0(core_regs[250]), + .I1(core_regs[228]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[206]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(core_regs[184]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6 [9]), + .I1(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7 [9]), + .I2(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I3(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8 [9]), + .I4(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I5(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9 [9]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAFA0CFCFAFA0C0C0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_3__0 + (.I0(core_regs[338]), + .I1(core_regs[316]), + .I2(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I3(core_regs[294]), + .I4(\data_sync_reg[2][34]_222 ), + .I5(core_regs[272]), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_3__0_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][0] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][0]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [0]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][0]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][0]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][0]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][0]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][10] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][10]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [10]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][10]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][10]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][10]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][10]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][11] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][11]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [11]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][11]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][11]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][11]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][11]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][12] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][12]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [12]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][12]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][12]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][12]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][12]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][13] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][13]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [13]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][13]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][13]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][13]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][13]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][14] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][14]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [14]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][14]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][14]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][14]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][14]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][15] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][15]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [15]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][15]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][15]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][15]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][15]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][16] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][16]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [16]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][16]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][16]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][16]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][16]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][17] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][17]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [17]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][17]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][17]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][17]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][17]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][18] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][18]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [18]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][18]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][18]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][18]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][18]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][19] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][19]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [19]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][19]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][19]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][19]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][19]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][1] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][1]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [1]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][1]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][1]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][1]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][1]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][20] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][20]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [20]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][20]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][20]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][20]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][20]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][21] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][21]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [21]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][21]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][21]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][21]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][21]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][22] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][22]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [22]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][22]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][22]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][22]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][22]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][23] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][23]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [23]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][23]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][23]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][23]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][23]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][24] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][24]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [24]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][24]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][24]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][24]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][24]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][25] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][25]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [25]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][25]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][25]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][25]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][25]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][26] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][26]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [26]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][26]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][26]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][26]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][26]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][27] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][27]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [27]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][27]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][27]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][27]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][27]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][28] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][28]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [28]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][28]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][28]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][28]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][28]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][29] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][29]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [29]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][29]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][29]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][29]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][29]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][2] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][2]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [2]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][2]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][2]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][2]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][2]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][30] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][30]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [30]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][30]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][30]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][30]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][30]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][31] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][31]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [31]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][31]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][31]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][31]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][31]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][3] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][3]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [3]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][3]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][3]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][3]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][3]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][4] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][4]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [4]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][4]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][4]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][4]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][4]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][5] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][5]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [5]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][5]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][5]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][5]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][5]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][6] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][6]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [6]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][6]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][6]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][6]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][6]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][7] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][7]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [7]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][7]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][7]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][7]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][7]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][8] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][8]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [8]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][8]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][8]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][8]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][8]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][9] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][9]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14 [9]), + .R(1'b0)); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][9]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_2_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_3_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][9]_i_1_n_0 ), + .S(\GEN_SEL_DELAY[3].sel_int_reg[3][0] )); + MUXF7 \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][9]_i_1__0 + (.I0(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_2__0_n_0 ), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_3__0_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][9]_0 ), + .S(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][0]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [0]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [0]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [0]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][0]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][10]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [10]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [10]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [10]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][10]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][11]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [11]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [11]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [11]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][11]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][12]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [12]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [12]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [12]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][12]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][13]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [13]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [13]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [13]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][13]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][14]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [14]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [14]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [14]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][14]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][15]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [15]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [15]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [15]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][15]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][16]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [16]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [16]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [16]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][16]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][17]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [17]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [17]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [17]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][17]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][18]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [18]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [18]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [18]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][18]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][19]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [19]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [19]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [19]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][19]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][1]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [1]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [1]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [1]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][1]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][20]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [20]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [20]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [20]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][20]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][21]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [21]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [21]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [21]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][21]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][22]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [22]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [22]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [22]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][22]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][23]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [23]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [23]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [23]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][23]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][24]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [24]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [24]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [24]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][24]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][25]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [25]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [25]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [25]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][25]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][26]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [26]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [26]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [26]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][26]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][27]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [27]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [27]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [27]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][27]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][28]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [28]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [28]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [28]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][28]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][29]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [29]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [29]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [29]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][29]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][2]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [2]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [2]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [2]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][2]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][30]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [30]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [30]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [30]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][30]_i_1_n_0 )); + LUT3 #( + .INIT(8'hEA)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1 + (.I0(\GEN_SEL_DELAY[3].sel_int_reg[3][0] ), + .I1(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I2(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + LUT3 #( + .INIT(8'hFE)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1__0 + (.I0(\GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0] ), + .I1(\GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0] ), + .I2(\data_sync_reg[2][34]_0 ), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [31]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [31]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [31]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_2_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][3]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [3]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [3]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [3]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][3]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][4]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [4]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [4]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [4]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][4]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][5]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [5]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [5]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [5]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][5]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][6]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [6]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [6]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [6]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][6]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][7]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [7]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [7]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [7]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][7]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][8]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [8]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [8]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [8]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][8]_i_1_n_0 )); + LUT5 #( + .INIT(32'hB8BBB888)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][9]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3 [9]), + .I1(\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0 ), + .I2(\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2 [9]), + .I3(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0 ), + .I4(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4 [9]), + .O(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][9]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][0] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][0]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [0]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][10] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][10]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [10]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][11] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][11]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [11]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][12] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][12]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [12]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][13] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][13]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [13]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][14] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][14]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [14]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][15] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][15]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [15]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][16] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][16]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [16]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][17] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][17]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [17]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][18] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][18]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [18]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][19] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][19]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [19]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][1] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][1]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [1]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][20] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][20]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [20]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][21] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][21]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [21]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][22] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][22]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [22]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][23] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][23]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [23]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][24] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][24]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [24]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][25] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][25]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [25]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][26] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][26]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [26]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][27] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][27]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [27]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][28] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][28]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [28]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][29] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][29]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [29]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][2] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][2]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [2]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][30] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][30]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [30]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_2_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [31]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][3] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][3]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [3]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][4] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][4]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [4]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][5] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][5]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [5]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][6] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][6]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [6]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][7] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][7]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [7]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][8] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][8]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [8]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][9] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][9]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5 [9]), + .R(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0 )); +endmodule + +(* ORIG_REF_NAME = "mux_tree" *) +module Arty_Z7_20_v_tc_1_0_mux_tree__parameterized0 + (\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 , + core_data, + ipif_Addr, + vid_aclk, + \GEN_SEL_DELAY[2].sel_int_reg[2][0] , + \core_status_regs[16] , + \core_control_regs[16] , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_0 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_1 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_2 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_3 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_4 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_5 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_6 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_7 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_8 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_9 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_10 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_11 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_12 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_13 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_14 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_15 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_16 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_17 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_18 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_19 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_20 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_21 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_22 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_23 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_24 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_25 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_26 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_27 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_28 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_29 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_30 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_31 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_32 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_33 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_34 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_35 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_36 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_37 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_38 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_39 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_40 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_41 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_42 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_43 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_44 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_45 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_46 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_47 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_48 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_49 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_50 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_51 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_52 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_53 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_54 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_55 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_56 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_57 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_58 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_59 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_60 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_61 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_62 , + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_63 , + \GEN_SEL_DELAY[4].sel_int_reg[4][0] ); + output \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ; + output [31:0]core_data; + input [0:0]ipif_Addr; + input vid_aclk; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0] ; + input [8:0]\core_status_regs[16] ; + input [22:0]\core_control_regs[16] ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_0 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_1 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_2 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_3 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_4 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_5 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_6 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_7 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_8 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_9 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_10 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_11 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_12 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_13 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_14 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_15 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_16 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_17 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_18 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_19 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_20 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_21 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_22 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_23 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_24 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_25 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_26 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_27 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_28 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_29 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_30 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_31 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_32 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_33 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_34 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_35 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_36 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_37 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_38 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_39 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_40 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_41 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_42 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_43 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_44 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_45 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_46 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_47 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_48 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_49 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_50 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_51 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_52 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_53 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_54 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_55 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_56 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_57 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_58 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_59 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_60 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_61 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_62 ; + input \GEN_SEL_DELAY[2].sel_int_reg[2][0]_63 ; + input \GEN_SEL_DELAY[4].sel_int_reg[4][0] ; + + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0] ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_0 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_1 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_10 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_11 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_12 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_13 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_14 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_15 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_16 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_17 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_18 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_19 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_2 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_20 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_21 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_22 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_23 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_24 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_25 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_26 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_27 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_28 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_29 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_3 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_30 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_31 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_32 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_33 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_34 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_35 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_36 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_37 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_38 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_39 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_4 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_40 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_41 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_42 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_43 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_44 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_45 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_46 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_47 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_48 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_49 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_5 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_50 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_51 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_52 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_53 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_54 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_55 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_56 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_57 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_58 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_59 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_6 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_60 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_61 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_62 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_63 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_7 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_8 ; + wire \GEN_SEL_DELAY[2].sel_int_reg[2][0]_9 ; + wire \GEN_SEL_DELAY[3].sel_int_reg[3][1]_srl2_n_0 ; + wire \GEN_SEL_DELAY[4].sel_int_reg[4][0] ; + wire [31:0]\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 ; + wire [31:0]\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 ; + wire \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ; + wire [31:0]\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 ; + wire [22:0]\core_control_regs[16] ; + wire [31:0]core_data; + wire [8:0]\core_status_regs[16] ; + wire [0:0]ipif_Addr; + wire vid_aclk; + + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[0]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [0]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [0]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [0]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[0])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[10]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [10]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [10]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [10]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[10])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[11]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [11]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [11]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [11]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[11])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[12]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [12]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [12]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [12]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[12])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[13]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [13]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [13]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [13]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[13])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[14]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [14]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [14]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [14]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[14])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[15]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [15]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [15]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [15]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[15])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[16]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [16]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [16]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [16]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[16])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[17]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [17]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [17]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [17]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[17])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[18]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [18]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [18]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [18]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[18])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[19]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [19]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [19]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [19]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[19])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[1]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [1]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [1]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [1]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[1])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[20]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [20]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [20]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [20]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[20])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[21]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [21]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [21]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [21]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[21])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[22]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [22]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [22]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [22]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[22])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[23]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [23]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [23]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [23]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[23])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[24]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [24]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [24]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [24]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[24])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[25]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [25]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [25]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [25]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[25])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[26]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [26]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [26]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [26]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[26])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[27]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [27]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [27]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [27]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[27])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[28]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [28]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [28]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [28]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[28])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[29]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [29]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [29]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [29]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[29])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[2]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [2]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [2]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [2]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[2])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[30]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [30]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [30]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [30]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[30])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[31]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [31]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [31]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [31]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[31])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[3]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [3]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [3]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [3]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[3])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[4]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [4]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [4]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [4]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[4])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[5]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [5]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [5]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [5]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[5])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[6]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [6]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [6]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [6]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[6])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[7]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [7]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [7]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [7]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[7])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[8]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [8]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [8]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [8]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[8])); + LUT5 #( + .INIT(32'h0A0ACFC0)) + \AXI4_LITE_INTERFACE.ipif_RdData[9]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [9]), + .I1(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [9]), + .I2(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .I3(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [9]), + .I4(\GEN_SEL_DELAY[4].sel_int_reg[4][0] ), + .O(core_data[9])); + FDRE #( + .INIT(1'b0)) + \GEN_SEL_DELAY[3].sel_int_reg[3][0] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[3].sel_int_reg[3][1]_srl2_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 ), + .R(1'b0)); + (* srl_bus_name = "U0/U_VIDEO_CTRL/\AXI4_LITE_INTERFACE.CORE_MUX0/GEN_SEL_DELAY[3].sel_int_reg[3] " *) + (* srl_name = "U0/U_VIDEO_CTRL/\AXI4_LITE_INTERFACE.CORE_MUX0/GEN_SEL_DELAY[3].sel_int_reg[3][1]_srl2 " *) + SRL16E #( + .INIT(16'h0000)) + \GEN_SEL_DELAY[3].sel_int_reg[3][1]_srl2 + (.A0(1'b1), + .A1(1'b0), + .A2(1'b0), + .A3(1'b0), + .CE(1'b1), + .CLK(vid_aclk), + .D(ipif_Addr), + .Q(\GEN_SEL_DELAY[3].sel_int_reg[3][1]_srl2_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][0] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_63 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][10] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_53 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][11] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_52 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][12] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_51 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][13] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_50 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][14] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_49 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][15] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_48 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [15]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][16] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_47 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][17] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_46 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][18] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_45 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][19] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_44 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][1] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_62 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][20] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_43 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][21] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_42 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][22] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_41 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [22]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][23] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_40 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [23]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][24] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_39 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [24]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][25] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_38 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [25]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][26] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_37 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [26]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][27] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_36 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [27]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][28] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_35 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [28]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][29] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_34 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [29]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][2] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_61 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][30] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_33 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [30]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][31] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_32 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [31]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][3] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_60 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][4] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_59 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][5] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_58 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][6] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_57 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][7] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_56 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][8] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_55 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][9] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_54 ), + .Q(\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2 [9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][0] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_31 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][10] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_21 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][11] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_20 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][12] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_19 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][13] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_18 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][14] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_17 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][15] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_16 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [15]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][16] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_15 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][17] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_14 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][18] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_13 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][19] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_12 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][1] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_30 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][20] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_11 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][21] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_10 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][22] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_9 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [22]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][23] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_8 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [23]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][24] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_7 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [24]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][25] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_6 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [25]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][26] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_5 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [26]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][27] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_4 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [27]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][28] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_3 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [28]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][29] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_2 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [29]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][2] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_29 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][30] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_1 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [30]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][31] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_0 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [31]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][3] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_28 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][4] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_27 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][5] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_26 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][6] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_25 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][7] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_24 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][8] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_23 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][9] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_SEL_DELAY[2].sel_int_reg[2][0]_22 ), + .Q(\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1 [9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][0] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_control_regs[16] [0]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [0]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][10] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_control_regs[16] [10]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [10]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][11] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_control_regs[16] [11]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [11]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][12] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_status_regs[16] [0]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [12]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][13] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_status_regs[16] [1]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [13]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][14] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_status_regs[16] [2]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [14]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][15] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_status_regs[16] [3]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [15]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][16] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_control_regs[16] [12]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [16]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][17] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_control_regs[16] [13]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [17]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][18] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_control_regs[16] [14]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [18]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][19] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_control_regs[16] [15]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [19]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][1] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_control_regs[16] [1]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [1]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][20] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_control_regs[16] [16]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [20]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][21] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_control_regs[16] [17]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [21]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][22] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_control_regs[16] [18]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [22]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][23] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_control_regs[16] [19]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [23]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][24] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_control_regs[16] [20]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [24]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][25] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_control_regs[16] [21]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [25]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][26] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_control_regs[16] [22]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [26]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][27] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_status_regs[16] [4]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [27]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][28] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_status_regs[16] [5]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [28]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][29] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_status_regs[16] [6]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [29]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][2] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_control_regs[16] [2]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [2]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][30] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_status_regs[16] [7]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [30]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_status_regs[16] [8]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [31]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][3] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_control_regs[16] [3]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [3]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][4] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_control_regs[16] [4]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [4]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][5] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_control_regs[16] [5]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [5]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][6] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_control_regs[16] [6]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [6]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][7] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_control_regs[16] [7]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [7]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][8] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_control_regs[16] [8]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [8]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); + FDRE #( + .INIT(1'b0)) + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][9] + (.C(vid_aclk), + .CE(1'b1), + .D(\core_control_regs[16] [9]), + .Q(\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0 [9]), + .R(\GEN_SEL_DELAY[2].sel_int_reg[2][0] )); +endmodule + +(* ORIG_REF_NAME = "tc_detector" *) +module Arty_Z7_20_v_tc_1_0_tc_detector + (det_ce, + Q, + \time_status_regs[6] , + \time_status_regs[3] , + vsync_lock_int, + hsync_lock_int, + active_video_lock_int, + reset, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] , + intr_status_int17_out, + \time_status_regs_int_reg[0] , + \intr_status_int_reg[11] , + all_lock_reg, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10] , + \time_status_regs[8] , + \time_status_regs[7] , + \time_status_regs[9] , + clk, + hsync_in, + active_video_in, + clken, + det_clken, + lost_lock, + resetn_out, + \genr_control_regs[0] , + core_d_out, + det_vblank_d, + det_active_video_d, + intc_if, + vblank_in, + all_lock, + all_lock_d0, + vsync_in); + output det_ce; + output [11:0]Q; + output [23:0]\time_status_regs[6] ; + output [2:0]\time_status_regs[3] ; + output vsync_lock_int; + output hsync_lock_int; + output active_video_lock_int; + output reset; + output [11:0]\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] ; + output intr_status_int17_out; + output [10:0]\time_status_regs_int_reg[0] ; + output \intr_status_int_reg[11] ; + output all_lock_reg; + output [10:0]\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10] ; + output [21:0]\time_status_regs[8] ; + output [23:0]\time_status_regs[7] ; + output [23:0]\time_status_regs[9] ; + input clk; + input hsync_in; + input active_video_in; + input clken; + input det_clken; + input lost_lock; + input resetn_out; + input [1:0]\genr_control_regs[0] ; + input core_d_out; + input det_vblank_d; + input det_active_video_d; + input [0:0]intc_if; + input vblank_in; + input all_lock; + input all_lock_d0; + input vsync_in; + + wire \DET_HACTIVE.DET_AVIDEO_LOCK.det_active_video_lock_int_i_1_n_0 ; + wire \DET_HACTIVE.active_video_count[0]_i_1_n_0 ; + wire \DET_HACTIVE.active_video_count[0]_i_4_n_0 ; + wire \DET_HACTIVE.active_video_count[0]_i_5_n_0 ; + wire \DET_HACTIVE.active_video_count[0]_i_6_n_0 ; + wire \DET_HACTIVE.active_video_count[0]_i_7_n_0 ; + wire \DET_HACTIVE.active_video_count[4]_i_2_n_0 ; + wire \DET_HACTIVE.active_video_count[4]_i_3_n_0 ; + wire \DET_HACTIVE.active_video_count[4]_i_4_n_0 ; + wire \DET_HACTIVE.active_video_count[4]_i_5_n_0 ; + wire \DET_HACTIVE.active_video_count[8]_i_2_n_0 ; + wire \DET_HACTIVE.active_video_count[8]_i_3_n_0 ; + wire \DET_HACTIVE.active_video_count[8]_i_4_n_0 ; + wire \DET_HACTIVE.active_video_count[8]_i_5_n_0 ; + wire [11:0]\DET_HACTIVE.active_video_count_reg ; + wire \DET_HACTIVE.active_video_count_reg[0]_i_3_n_0 ; + wire \DET_HACTIVE.active_video_count_reg[0]_i_3_n_1 ; + wire \DET_HACTIVE.active_video_count_reg[0]_i_3_n_2 ; + wire \DET_HACTIVE.active_video_count_reg[0]_i_3_n_3 ; + wire \DET_HACTIVE.active_video_count_reg[0]_i_3_n_4 ; + wire \DET_HACTIVE.active_video_count_reg[0]_i_3_n_5 ; + wire \DET_HACTIVE.active_video_count_reg[0]_i_3_n_6 ; + wire \DET_HACTIVE.active_video_count_reg[0]_i_3_n_7 ; + wire \DET_HACTIVE.active_video_count_reg[4]_i_1_n_0 ; + wire \DET_HACTIVE.active_video_count_reg[4]_i_1_n_1 ; + wire \DET_HACTIVE.active_video_count_reg[4]_i_1_n_2 ; + wire \DET_HACTIVE.active_video_count_reg[4]_i_1_n_3 ; + wire \DET_HACTIVE.active_video_count_reg[4]_i_1_n_4 ; + wire \DET_HACTIVE.active_video_count_reg[4]_i_1_n_5 ; + wire \DET_HACTIVE.active_video_count_reg[4]_i_1_n_6 ; + wire \DET_HACTIVE.active_video_count_reg[4]_i_1_n_7 ; + wire \DET_HACTIVE.active_video_count_reg[8]_i_1_n_1 ; + wire \DET_HACTIVE.active_video_count_reg[8]_i_1_n_2 ; + wire \DET_HACTIVE.active_video_count_reg[8]_i_1_n_3 ; + wire \DET_HACTIVE.active_video_count_reg[8]_i_1_n_4 ; + wire \DET_HACTIVE.active_video_count_reg[8]_i_1_n_5 ; + wire \DET_HACTIVE.active_video_count_reg[8]_i_1_n_6 ; + wire \DET_HACTIVE.active_video_count_reg[8]_i_1_n_7 ; + wire \DET_HACTIVE.active_video_d2_i_2_n_0 ; + wire \DET_HACTIVE.active_video_d_i_1_n_0 ; + wire \DET_HACTIVE.active_video_rose_i_1_n_0 ; + wire \DET_HACTIVE.active_video_toggled_i_1_n_0 ; + wire \DET_HACTIVE.det_active_video_pol_int_i_1_n_0 ; + wire \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_lock_int_i_1_n_0 ; + wire \DET_HSYNC.det_hsync_pol_int_i_1_n_0 ; + wire \DET_HSYNC.hsync_count[0]_i_1_n_0 ; + wire \DET_HSYNC.hsync_count[0]_i_2_n_0 ; + wire \DET_HSYNC.hsync_count[0]_i_4_n_0 ; + wire \DET_HSYNC.hsync_count[0]_i_5_n_0 ; + wire \DET_HSYNC.hsync_count[0]_i_6_n_0 ; + wire \DET_HSYNC.hsync_count[0]_i_7_n_0 ; + wire \DET_HSYNC.hsync_count[4]_i_2_n_0 ; + wire \DET_HSYNC.hsync_count[4]_i_3_n_0 ; + wire \DET_HSYNC.hsync_count[4]_i_4_n_0 ; + wire \DET_HSYNC.hsync_count[4]_i_5_n_0 ; + wire \DET_HSYNC.hsync_count[8]_i_2_n_0 ; + wire \DET_HSYNC.hsync_count[8]_i_3_n_0 ; + wire \DET_HSYNC.hsync_count[8]_i_4_n_0 ; + wire \DET_HSYNC.hsync_count[8]_i_5_n_0 ; + wire [11:0]\DET_HSYNC.hsync_count_reg ; + wire \DET_HSYNC.hsync_count_reg[0]_i_3_n_0 ; + wire \DET_HSYNC.hsync_count_reg[0]_i_3_n_1 ; + wire \DET_HSYNC.hsync_count_reg[0]_i_3_n_2 ; + wire \DET_HSYNC.hsync_count_reg[0]_i_3_n_3 ; + wire \DET_HSYNC.hsync_count_reg[0]_i_3_n_4 ; + wire \DET_HSYNC.hsync_count_reg[0]_i_3_n_5 ; + wire \DET_HSYNC.hsync_count_reg[0]_i_3_n_6 ; + wire \DET_HSYNC.hsync_count_reg[0]_i_3_n_7 ; + wire \DET_HSYNC.hsync_count_reg[4]_i_1_n_0 ; + wire \DET_HSYNC.hsync_count_reg[4]_i_1_n_1 ; + wire \DET_HSYNC.hsync_count_reg[4]_i_1_n_2 ; + wire \DET_HSYNC.hsync_count_reg[4]_i_1_n_3 ; + wire \DET_HSYNC.hsync_count_reg[4]_i_1_n_4 ; + wire \DET_HSYNC.hsync_count_reg[4]_i_1_n_5 ; + wire \DET_HSYNC.hsync_count_reg[4]_i_1_n_6 ; + wire \DET_HSYNC.hsync_count_reg[4]_i_1_n_7 ; + wire \DET_HSYNC.hsync_count_reg[8]_i_1_n_1 ; + wire \DET_HSYNC.hsync_count_reg[8]_i_1_n_2 ; + wire \DET_HSYNC.hsync_count_reg[8]_i_1_n_3 ; + wire \DET_HSYNC.hsync_count_reg[8]_i_1_n_4 ; + wire \DET_HSYNC.hsync_count_reg[8]_i_1_n_5 ; + wire \DET_HSYNC.hsync_count_reg[8]_i_1_n_6 ; + wire \DET_HSYNC.hsync_count_reg[8]_i_1_n_7 ; + wire \DET_VACTIVE.active_line_d_i_1_n_0 ; + wire \DET_VACTIVE.active_line_i_1_n_0 ; + wire \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0_vsync_lock_i_1_n_0 ; + wire \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0 ; + wire \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_vsync_lock_i_1_n_0 ; + wire \DET_VSYNC.GEN_DET_VSYNC_LOCK.vsync_delay[0]_i_1_n_0 ; + wire \DET_VSYNC.GEN_DET_VSYNC_LOCK.vsync_delay_reg_n_0_[0] ; + wire \DET_VSYNC.det_v0bp_start_int[0]_i_1_n_0 ; + wire \DET_VSYNC.det_v0bp_start_int[10]_i_1_n_0 ; + wire \DET_VSYNC.det_v0bp_start_int[1]_i_1_n_0 ; + wire \DET_VSYNC.det_v0bp_start_int[2]_i_1_n_0 ; + wire \DET_VSYNC.det_v0bp_start_int[3]_i_1_n_0 ; + wire \DET_VSYNC.det_v0bp_start_int[4]_i_1_n_0 ; + wire \DET_VSYNC.det_v0bp_start_int[5]_i_1_n_0 ; + wire \DET_VSYNC.det_v0bp_start_int[6]_i_1_n_0 ; + wire \DET_VSYNC.det_v0bp_start_int[7]_i_1_n_0 ; + wire \DET_VSYNC.det_v0bp_start_int[8]_i_1_n_0 ; + wire \DET_VSYNC.det_v0bp_start_int[9]_i_1_n_0 ; + wire \DET_VSYNC.det_v0sync_start_hori_int[0]_i_1_n_0 ; + wire \DET_VSYNC.det_v0sync_start_hori_int[10]_i_1_n_0 ; + wire \DET_VSYNC.det_v0sync_start_hori_int[11]_i_2_n_0 ; + wire \DET_VSYNC.det_v0sync_start_hori_int[1]_i_1_n_0 ; + wire \DET_VSYNC.det_v0sync_start_hori_int[2]_i_1_n_0 ; + wire \DET_VSYNC.det_v0sync_start_hori_int[3]_i_1_n_0 ; + wire \DET_VSYNC.det_v0sync_start_hori_int[4]_i_1_n_0 ; + wire \DET_VSYNC.det_v0sync_start_hori_int[5]_i_1_n_0 ; + wire \DET_VSYNC.det_v0sync_start_hori_int[6]_i_1_n_0 ; + wire \DET_VSYNC.det_v0sync_start_hori_int[7]_i_1_n_0 ; + wire \DET_VSYNC.det_v0sync_start_hori_int[8]_i_1_n_0 ; + wire \DET_VSYNC.det_v0sync_start_hori_int[9]_i_1_n_0 ; + wire \DET_VSYNC.det_v0sync_start_int[0]_i_1_n_0 ; + wire \DET_VSYNC.det_v0sync_start_int[10]_i_1_n_0 ; + wire \DET_VSYNC.det_v0sync_start_int[1]_i_1_n_0 ; + wire \DET_VSYNC.det_v0sync_start_int[2]_i_1_n_0 ; + wire \DET_VSYNC.det_v0sync_start_int[3]_i_1_n_0 ; + wire \DET_VSYNC.det_v0sync_start_int[4]_i_1_n_0 ; + wire \DET_VSYNC.det_v0sync_start_int[5]_i_1_n_0 ; + wire \DET_VSYNC.det_v0sync_start_int[6]_i_1_n_0 ; + wire \DET_VSYNC.det_v0sync_start_int[7]_i_1_n_0 ; + wire \DET_VSYNC.det_v0sync_start_int[8]_i_1_n_0 ; + wire \DET_VSYNC.det_v0sync_start_int[9]_i_1_n_0 ; + wire \DET_VSYNC.det_vsync_pol_change_i_2_n_0 ; + wire \DET_VSYNC.det_vsync_pol_change_i_3_n_0 ; + wire \DET_VSYNC.det_vsync_pol_int_i_1_n_0 ; + wire \DET_VSYNC.vsync_count[10]_i_1_n_0 ; + wire \DET_VSYNC.vsync_count[10]_i_4_n_0 ; + wire [10:0]\DET_VSYNC.vsync_count_reg__0 ; + wire \DET_VSYNC.vsync_d2_reg_n_0 ; + wire \DET_VSYNC.vsync_d_i_1_n_0 ; + wire \DET_VSYNC.vsync_d_reg_n_0 ; + wire \DET_VSYNC.vsync_rose_i_1_n_0 ; + wire \DET_VSYNC.vsync_toggled_i_1_n_0 ; + wire \DET_VSYNC.vsync_toggled_reg_n_0 ; + wire [11:0]\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] ; + wire [10:0]\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10] ; + wire [0:11]L; + wire [11:0]Q; + wire \_inferred__11/i__carry__0_n_0 ; + wire \_inferred__11/i__carry__0_n_1 ; + wire \_inferred__11/i__carry__0_n_2 ; + wire \_inferred__11/i__carry__0_n_3 ; + wire \_inferred__11/i__carry__1_n_1 ; + wire \_inferred__11/i__carry__1_n_2 ; + wire \_inferred__11/i__carry__1_n_3 ; + wire \_inferred__11/i__carry_n_0 ; + wire \_inferred__11/i__carry_n_1 ; + wire \_inferred__11/i__carry_n_2 ; + wire \_inferred__11/i__carry_n_3 ; + wire \_inferred__8/i__carry__0_n_0 ; + wire \_inferred__8/i__carry__0_n_1 ; + wire \_inferred__8/i__carry__0_n_2 ; + wire \_inferred__8/i__carry__0_n_3 ; + wire \_inferred__8/i__carry__1_n_1 ; + wire \_inferred__8/i__carry__1_n_2 ; + wire \_inferred__8/i__carry__1_n_3 ; + wire \_inferred__8/i__carry_n_0 ; + wire \_inferred__8/i__carry_n_1 ; + wire \_inferred__8/i__carry_n_2 ; + wire \_inferred__8/i__carry_n_3 ; + wire active_line; + wire active_line_d; + wire active_video_count; + wire [11:0]active_video_count_last; + wire active_video_d; + wire active_video_d2; + wire active_video_in; + wire active_video_lock_int; + wire active_video_rose; + wire active_video_toggled; + wire all_lock; + wire all_lock_d0; + wire all_lock_reg; + wire clk; + wire clken; + wire core_d_out; + wire det_active_video_d; + wire det_active_video_pol_change; + wire det_ce; + wire det_clken; + wire [11:0]det_hactive_start_int; + wire det_hactive_start_int_3; + wire [11:0]det_hbp_start_int; + wire det_hbp_start_int_9; + wire [11:0]det_hbp_start_last; + wire [11:0]det_hfp_start_int; + wire det_hfp_start_int_8; + wire det_hsync_pol_change; + wire [11:0]det_hsync_start_int; + wire det_hsync_start_int_2; + wire [11:0]det_hsync_start_last; + wire [11:0]det_htotal_int; + wire \det_htotal_int2[11]_i_2_n_0 ; + wire \det_htotal_int2[11]_i_3_n_0 ; + wire \det_htotal_int2[11]_i_4_n_0 ; + wire \det_htotal_int2[4]_i_2_n_0 ; + wire \det_htotal_int2[4]_i_3_n_0 ; + wire \det_htotal_int2[4]_i_4_n_0 ; + wire \det_htotal_int2[4]_i_5_n_0 ; + wire \det_htotal_int2[8]_i_2_n_0 ; + wire \det_htotal_int2[8]_i_3_n_0 ; + wire \det_htotal_int2[8]_i_4_n_0 ; + wire \det_htotal_int2[8]_i_5_n_0 ; + wire \det_htotal_int2_reg[11]_i_1_n_2 ; + wire \det_htotal_int2_reg[11]_i_1_n_3 ; + wire \det_htotal_int2_reg[4]_i_1_n_0 ; + wire \det_htotal_int2_reg[4]_i_1_n_1 ; + wire \det_htotal_int2_reg[4]_i_1_n_2 ; + wire \det_htotal_int2_reg[4]_i_1_n_3 ; + wire \det_htotal_int2_reg[8]_i_1_n_0 ; + wire \det_htotal_int2_reg[8]_i_1_n_1 ; + wire \det_htotal_int2_reg[8]_i_1_n_2 ; + wire \det_htotal_int2_reg[8]_i_1_n_3 ; + wire \det_htotal_int[11]_i_1_n_0 ; + wire det_v0_vsync_lock; + wire det_v0_vsync_lock__0; + wire [11:1]det_v0active_start_hori_int2; + wire \det_v0active_start_hori_int2[0]_i_10_n_0 ; + wire \det_v0active_start_hori_int2[0]_i_11_n_0 ; + wire \det_v0active_start_hori_int2[0]_i_12_n_0 ; + wire \det_v0active_start_hori_int2[0]_i_13_n_0 ; + wire \det_v0active_start_hori_int2[0]_i_1_n_0 ; + wire \det_v0active_start_hori_int2[0]_i_4_n_0 ; + wire \det_v0active_start_hori_int2[0]_i_5_n_0 ; + wire \det_v0active_start_hori_int2[0]_i_6_n_0 ; + wire \det_v0active_start_hori_int2[0]_i_7_n_0 ; + wire \det_v0active_start_hori_int2[0]_i_8_n_0 ; + wire \det_v0active_start_hori_int2[0]_i_9_n_0 ; + wire \det_v0active_start_hori_int2[11]_i_2_n_0 ; + wire \det_v0active_start_hori_int2[11]_i_3_n_0 ; + wire \det_v0active_start_hori_int2[11]_i_4_n_0 ; + wire \det_v0active_start_hori_int2[11]_i_5_n_0 ; + wire \det_v0active_start_hori_int2[11]_i_6_n_0 ; + wire \det_v0active_start_hori_int2[11]_i_7_n_0 ; + wire \det_v0active_start_hori_int2[11]_i_8_n_0 ; + wire \det_v0active_start_hori_int2[3]_i_2_n_0 ; + wire \det_v0active_start_hori_int2[3]_i_3_n_0 ; + wire \det_v0active_start_hori_int2[3]_i_4_n_0 ; + wire \det_v0active_start_hori_int2[3]_i_5_n_0 ; + wire \det_v0active_start_hori_int2[3]_i_6_n_0 ; + wire \det_v0active_start_hori_int2[3]_i_7_n_0 ; + wire \det_v0active_start_hori_int2[3]_i_8_n_0 ; + wire \det_v0active_start_hori_int2[3]_i_9_n_0 ; + wire \det_v0active_start_hori_int2[7]_i_2_n_0 ; + wire \det_v0active_start_hori_int2[7]_i_3_n_0 ; + wire \det_v0active_start_hori_int2[7]_i_4_n_0 ; + wire \det_v0active_start_hori_int2[7]_i_5_n_0 ; + wire \det_v0active_start_hori_int2[7]_i_6_n_0 ; + wire \det_v0active_start_hori_int2[7]_i_7_n_0 ; + wire \det_v0active_start_hori_int2[7]_i_8_n_0 ; + wire \det_v0active_start_hori_int2[7]_i_9_n_0 ; + wire \det_v0active_start_hori_int2_reg[0]_i_2_n_3 ; + wire \det_v0active_start_hori_int2_reg[0]_i_3_n_0 ; + wire \det_v0active_start_hori_int2_reg[0]_i_3_n_1 ; + wire \det_v0active_start_hori_int2_reg[0]_i_3_n_2 ; + wire \det_v0active_start_hori_int2_reg[0]_i_3_n_3 ; + wire \det_v0active_start_hori_int2_reg[11]_i_1_n_1 ; + wire \det_v0active_start_hori_int2_reg[11]_i_1_n_2 ; + wire \det_v0active_start_hori_int2_reg[11]_i_1_n_3 ; + wire \det_v0active_start_hori_int2_reg[3]_i_1_n_0 ; + wire \det_v0active_start_hori_int2_reg[3]_i_1_n_1 ; + wire \det_v0active_start_hori_int2_reg[3]_i_1_n_2 ; + wire \det_v0active_start_hori_int2_reg[3]_i_1_n_3 ; + wire \det_v0active_start_hori_int2_reg[7]_i_1_n_0 ; + wire \det_v0active_start_hori_int2_reg[7]_i_1_n_1 ; + wire \det_v0active_start_hori_int2_reg[7]_i_1_n_2 ; + wire \det_v0active_start_hori_int2_reg[7]_i_1_n_3 ; + wire [10:0]det_v0active_start_int; + wire det_v0active_start_int_6; + wire [11:0]det_v0bp_start_hori_int; + wire [11:0]det_v0bp_start_hori_int2; + wire [11:0]det_v0bp_start_hori_last; + wire [10:0]det_v0bp_start_int; + wire [10:0]det_v0bp_start_int2; + wire \det_v0bp_start_int2[10]_i_2_n_0 ; + wire \det_v0bp_start_int2[10]_i_3_n_0 ; + wire \det_v0bp_start_int2[10]_i_4_n_0 ; + wire \det_v0bp_start_int2[3]_i_2_n_0 ; + wire \det_v0bp_start_int2[3]_i_3_n_0 ; + wire \det_v0bp_start_int2[3]_i_4_n_0 ; + wire \det_v0bp_start_int2[3]_i_5_n_0 ; + wire \det_v0bp_start_int2[7]_i_2_n_0 ; + wire \det_v0bp_start_int2[7]_i_3_n_0 ; + wire \det_v0bp_start_int2[7]_i_4_n_0 ; + wire \det_v0bp_start_int2[7]_i_5_n_0 ; + wire \det_v0bp_start_int2_reg[10]_i_1_n_2 ; + wire \det_v0bp_start_int2_reg[10]_i_1_n_3 ; + wire \det_v0bp_start_int2_reg[3]_i_1_n_0 ; + wire \det_v0bp_start_int2_reg[3]_i_1_n_1 ; + wire \det_v0bp_start_int2_reg[3]_i_1_n_2 ; + wire \det_v0bp_start_int2_reg[3]_i_1_n_3 ; + wire \det_v0bp_start_int2_reg[7]_i_1_n_0 ; + wire \det_v0bp_start_int2_reg[7]_i_1_n_1 ; + wire \det_v0bp_start_int2_reg[7]_i_1_n_2 ; + wire \det_v0bp_start_int2_reg[7]_i_1_n_3 ; + wire det_v0bp_start_int_7; + wire [10:0]det_v0bp_start_last; + wire [11:1]det_v0fp_start_hori_int2; + wire \det_v0fp_start_hori_int2[0]_i_10_n_0 ; + wire \det_v0fp_start_hori_int2[0]_i_11_n_0 ; + wire \det_v0fp_start_hori_int2[0]_i_12_n_0 ; + wire \det_v0fp_start_hori_int2[0]_i_13_n_0 ; + wire \det_v0fp_start_hori_int2[0]_i_14_n_0 ; + wire \det_v0fp_start_hori_int2[0]_i_1_n_0 ; + wire \det_v0fp_start_hori_int2[0]_i_4_n_0 ; + wire \det_v0fp_start_hori_int2[0]_i_5_n_0 ; + wire \det_v0fp_start_hori_int2[0]_i_6_n_0 ; + wire \det_v0fp_start_hori_int2[0]_i_7_n_0 ; + wire \det_v0fp_start_hori_int2[0]_i_8_n_0 ; + wire \det_v0fp_start_hori_int2[0]_i_9_n_0 ; + wire \det_v0fp_start_hori_int2[11]_i_2_n_0 ; + wire \det_v0fp_start_hori_int2[11]_i_3_n_0 ; + wire \det_v0fp_start_hori_int2[11]_i_4_n_0 ; + wire \det_v0fp_start_hori_int2[11]_i_5_n_0 ; + wire \det_v0fp_start_hori_int2[11]_i_6_n_0 ; + wire \det_v0fp_start_hori_int2[11]_i_7_n_0 ; + wire \det_v0fp_start_hori_int2[11]_i_8_n_0 ; + wire \det_v0fp_start_hori_int2[3]_i_2_n_0 ; + wire \det_v0fp_start_hori_int2[3]_i_3_n_0 ; + wire \det_v0fp_start_hori_int2[3]_i_4_n_0 ; + wire \det_v0fp_start_hori_int2[3]_i_5_n_0 ; + wire \det_v0fp_start_hori_int2[3]_i_6_n_0 ; + wire \det_v0fp_start_hori_int2[3]_i_7_n_0 ; + wire \det_v0fp_start_hori_int2[3]_i_8_n_0 ; + wire \det_v0fp_start_hori_int2[3]_i_9_n_0 ; + wire \det_v0fp_start_hori_int2[7]_i_2_n_0 ; + wire \det_v0fp_start_hori_int2[7]_i_3_n_0 ; + wire \det_v0fp_start_hori_int2[7]_i_4_n_0 ; + wire \det_v0fp_start_hori_int2[7]_i_5_n_0 ; + wire \det_v0fp_start_hori_int2[7]_i_6_n_0 ; + wire \det_v0fp_start_hori_int2[7]_i_7_n_0 ; + wire \det_v0fp_start_hori_int2[7]_i_8_n_0 ; + wire \det_v0fp_start_hori_int2[7]_i_9_n_0 ; + wire \det_v0fp_start_hori_int2_reg[0]_i_2_n_3 ; + wire \det_v0fp_start_hori_int2_reg[0]_i_3_n_0 ; + wire \det_v0fp_start_hori_int2_reg[0]_i_3_n_1 ; + wire \det_v0fp_start_hori_int2_reg[0]_i_3_n_2 ; + wire \det_v0fp_start_hori_int2_reg[0]_i_3_n_3 ; + wire \det_v0fp_start_hori_int2_reg[11]_i_1_n_1 ; + wire \det_v0fp_start_hori_int2_reg[11]_i_1_n_2 ; + wire \det_v0fp_start_hori_int2_reg[11]_i_1_n_3 ; + wire \det_v0fp_start_hori_int2_reg[3]_i_1_n_0 ; + wire \det_v0fp_start_hori_int2_reg[3]_i_1_n_1 ; + wire \det_v0fp_start_hori_int2_reg[3]_i_1_n_2 ; + wire \det_v0fp_start_hori_int2_reg[3]_i_1_n_3 ; + wire \det_v0fp_start_hori_int2_reg[7]_i_1_n_0 ; + wire \det_v0fp_start_hori_int2_reg[7]_i_1_n_1 ; + wire \det_v0fp_start_hori_int2_reg[7]_i_1_n_2 ; + wire \det_v0fp_start_hori_int2_reg[7]_i_1_n_3 ; + wire det_v0fp_start_int; + wire [11:0]det_v0sync_start_hori_int; + wire [11:0]det_v0sync_start_hori_int2; + wire [11:0]det_v0sync_start_hori_last; + wire [10:0]det_v0sync_start_int; + wire [10:0]det_v0sync_start_int2; + wire \det_v0sync_start_int2[10]_i_2_n_0 ; + wire \det_v0sync_start_int2[10]_i_3_n_0 ; + wire \det_v0sync_start_int2[10]_i_4_n_0 ; + wire \det_v0sync_start_int2[3]_i_2_n_0 ; + wire \det_v0sync_start_int2[3]_i_3_n_0 ; + wire \det_v0sync_start_int2[3]_i_4_n_0 ; + wire \det_v0sync_start_int2[3]_i_5_n_0 ; + wire \det_v0sync_start_int2[7]_i_2_n_0 ; + wire \det_v0sync_start_int2[7]_i_3_n_0 ; + wire \det_v0sync_start_int2[7]_i_4_n_0 ; + wire \det_v0sync_start_int2[7]_i_5_n_0 ; + wire \det_v0sync_start_int2_reg[10]_i_1_n_2 ; + wire \det_v0sync_start_int2_reg[10]_i_1_n_3 ; + wire \det_v0sync_start_int2_reg[3]_i_1_n_0 ; + wire \det_v0sync_start_int2_reg[3]_i_1_n_1 ; + wire \det_v0sync_start_int2_reg[3]_i_1_n_2 ; + wire \det_v0sync_start_int2_reg[3]_i_1_n_3 ; + wire \det_v0sync_start_int2_reg[7]_i_1_n_0 ; + wire \det_v0sync_start_int2_reg[7]_i_1_n_1 ; + wire \det_v0sync_start_int2_reg[7]_i_1_n_2 ; + wire \det_v0sync_start_int2_reg[7]_i_1_n_3 ; + wire det_v0sync_start_int_4; + wire [10:0]det_v0sync_start_last; + wire \det_v0total[0]_i_1_n_0 ; + wire \det_v0total[10]_i_1_n_0 ; + wire \det_v0total[10]_i_2_n_0 ; + wire \det_v0total[1]_i_1_n_0 ; + wire \det_v0total[2]_i_1_n_0 ; + wire \det_v0total[3]_i_1_n_0 ; + wire \det_v0total[4]_i_1_n_0 ; + wire \det_v0total[5]_i_1_n_0 ; + wire \det_v0total[6]_i_1_n_0 ; + wire \det_v0total[7]_i_1_n_0 ; + wire \det_v0total[8]_i_1_n_0 ; + wire \det_v0total[9]_i_1_n_0 ; + wire [10:0]det_v0total_int; + wire \det_v0total_int[0]_i_1_n_0 ; + wire \det_v0total_int[10]_i_2_n_0 ; + wire \det_v0total_int[1]_i_1_n_0 ; + wire \det_v0total_int[2]_i_1_n_0 ; + wire \det_v0total_int[3]_i_1_n_0 ; + wire \det_v0total_int[4]_i_1_n_0 ; + wire \det_v0total_int[5]_i_1_n_0 ; + wire \det_v0total_int[6]_i_1_n_0 ; + wire \det_v0total_int[7]_i_1_n_0 ; + wire \det_v0total_int[8]_i_1_n_0 ; + wire \det_v0total_int[9]_i_1_n_0 ; + wire det_v0total_int_5; + wire det_vblank_d; + wire det_vsync_pol_change; + wire found_eof_i_1_n_0; + wire found_eof_reg_n_0; + wire frame_end; + wire frame_end_d; + wire [1:0]\genr_control_regs[0] ; + wire gtOp; + wire gtOp29_in; + wire gtOp_0; + wire gtOp_carry__0_i_1_n_0; + wire gtOp_carry__0_i_2_n_0; + wire gtOp_carry__0_i_3_n_0; + wire gtOp_carry__0_i_4_n_0; + wire gtOp_carry__0_i_5_n_0; + wire gtOp_carry__0_n_2; + wire gtOp_carry__0_n_3; + wire gtOp_carry_i_1_n_0; + wire gtOp_carry_i_2_n_0; + wire gtOp_carry_i_3_n_0; + wire gtOp_carry_i_4_n_0; + wire gtOp_carry_i_5_n_0; + wire gtOp_carry_i_6_n_0; + wire gtOp_carry_i_7_n_0; + wire gtOp_carry_i_8_n_0; + wire gtOp_carry_n_0; + wire gtOp_carry_n_1; + wire gtOp_carry_n_2; + wire gtOp_carry_n_3; + wire \gtOp_inferred__0/i__carry__0_n_2 ; + wire \gtOp_inferred__0/i__carry__0_n_3 ; + wire \gtOp_inferred__0/i__carry_n_0 ; + wire \gtOp_inferred__0/i__carry_n_1 ; + wire \gtOp_inferred__0/i__carry_n_2 ; + wire \gtOp_inferred__0/i__carry_n_3 ; + wire \gtOp_inferred__2/i__carry__0_n_3 ; + wire \gtOp_inferred__2/i__carry_n_0 ; + wire \gtOp_inferred__2/i__carry_n_1 ; + wire \gtOp_inferred__2/i__carry_n_2 ; + wire \gtOp_inferred__2/i__carry_n_3 ; + wire h_count; + wire h_count0__0; + wire h_count1; + wire \h_count[0]_i_1_n_0 ; + wire \h_count[0]_i_4_n_0 ; + wire \h_count[0]_i_5_n_0 ; + wire \h_count[0]_i_6_n_0 ; + wire \h_count[0]_i_7_n_0 ; + wire \h_count[0]_i_8_n_0 ; + wire \h_count[0]_i_9_n_0 ; + wire \h_count[4]_i_2_n_0 ; + wire \h_count[4]_i_3_n_0 ; + wire \h_count[4]_i_4_n_0 ; + wire \h_count[4]_i_5_n_0 ; + wire \h_count[8]_i_2_n_0 ; + wire \h_count[8]_i_3_n_0 ; + wire \h_count[8]_i_4_n_0 ; + wire \h_count[8]_i_5_n_0 ; + wire \h_count_reg[0]_i_3_n_0 ; + wire \h_count_reg[0]_i_3_n_1 ; + wire \h_count_reg[0]_i_3_n_2 ; + wire \h_count_reg[0]_i_3_n_3 ; + wire \h_count_reg[0]_i_3_n_4 ; + wire \h_count_reg[0]_i_3_n_5 ; + wire \h_count_reg[0]_i_3_n_6 ; + wire \h_count_reg[0]_i_3_n_7 ; + wire \h_count_reg[4]_i_1_n_0 ; + wire \h_count_reg[4]_i_1_n_1 ; + wire \h_count_reg[4]_i_1_n_2 ; + wire \h_count_reg[4]_i_1_n_3 ; + wire \h_count_reg[4]_i_1_n_4 ; + wire \h_count_reg[4]_i_1_n_5 ; + wire \h_count_reg[4]_i_1_n_6 ; + wire \h_count_reg[4]_i_1_n_7 ; + wire \h_count_reg[8]_i_1_n_1 ; + wire \h_count_reg[8]_i_1_n_2 ; + wire \h_count_reg[8]_i_1_n_3 ; + wire \h_count_reg[8]_i_1_n_4 ; + wire \h_count_reg[8]_i_1_n_5 ; + wire \h_count_reg[8]_i_1_n_6 ; + wire \h_count_reg[8]_i_1_n_7 ; + wire hsync_d; + wire hsync_d2; + wire hsync_in; + wire hsync_lock_int; + wire i__carry__0_i_1__0_n_0; + wire i__carry__0_i_1__1_n_0; + wire i__carry__0_i_1__2_n_0; + wire i__carry__0_i_1__3_n_0; + wire i__carry__0_i_1__4_n_0; + wire i__carry__0_i_1__5_n_0; + wire i__carry__0_i_1__6_n_0; + wire i__carry__0_i_1_n_0; + wire i__carry__0_i_2__0_n_0; + wire i__carry__0_i_2__1_n_0; + wire i__carry__0_i_2__2_n_0; + wire i__carry__0_i_2__3_n_0; + wire i__carry__0_i_2__4_n_0; + wire i__carry__0_i_2__5_n_0; + wire i__carry__0_i_2__6_n_0; + wire i__carry__0_i_2_n_0; + wire i__carry__0_i_3__0_n_0; + wire i__carry__0_i_3__1_n_0; + wire i__carry__0_i_3__2_n_0; + wire i__carry__0_i_3__3_n_0; + wire i__carry__0_i_3__4_n_0; + wire i__carry__0_i_3__5_n_0; + wire i__carry__0_i_3__6_n_0; + wire i__carry__0_i_3_n_0; + wire i__carry__0_i_4__0_n_0; + wire i__carry__0_i_4__1_n_0; + wire i__carry__0_i_4__2_n_0; + wire i__carry__0_i_4__3_n_0; + wire i__carry__0_i_4__4_n_0; + wire i__carry__0_i_4__5_n_0; + wire i__carry__0_i_4__6_n_0; + wire i__carry__0_i_4_n_0; + wire i__carry__0_i_5__0_n_0; + wire i__carry__0_i_5_n_0; + wire i__carry__1_i_1__0_n_0; + wire i__carry__1_i_1__1_n_0; + wire i__carry__1_i_1__2_n_0; + wire i__carry__1_i_1_n_0; + wire i__carry__1_i_2__0_n_0; + wire i__carry__1_i_2__1_n_0; + wire i__carry__1_i_2__2_n_0; + wire i__carry__1_i_2_n_0; + wire i__carry__1_i_3__0_n_0; + wire i__carry__1_i_3__1_n_0; + wire i__carry__1_i_3__2_n_0; + wire i__carry__1_i_3_n_0; + wire i__carry__1_i_4__0_n_0; + wire i__carry__1_i_4__1_n_0; + wire i__carry__1_i_4__2_n_0; + wire i__carry__1_i_4_n_0; + wire i__carry_i_1__0_n_0; + wire i__carry_i_1__10_n_0; + wire i__carry_i_1__11_n_0; + wire i__carry_i_1__12_n_0; + wire i__carry_i_1__1_n_0; + wire i__carry_i_1__2_n_0; + wire i__carry_i_1__3_n_0; + wire i__carry_i_1__4_n_0; + wire i__carry_i_1__5_n_0; + wire i__carry_i_1__6_n_0; + wire i__carry_i_1__7_n_0; + wire i__carry_i_1__8_n_0; + wire i__carry_i_1__9_n_0; + wire i__carry_i_1_n_0; + wire i__carry_i_2__0_n_0; + wire i__carry_i_2__10_n_0; + wire i__carry_i_2__11_n_0; + wire i__carry_i_2__12_n_0; + wire i__carry_i_2__1_n_0; + wire i__carry_i_2__2_n_0; + wire i__carry_i_2__3_n_0; + wire i__carry_i_2__4_n_0; + wire i__carry_i_2__5_n_0; + wire i__carry_i_2__6_n_0; + wire i__carry_i_2__7_n_0; + wire i__carry_i_2__8_n_0; + wire i__carry_i_2__9_n_0; + wire i__carry_i_2_n_0; + wire i__carry_i_3__0_n_0; + wire i__carry_i_3__10_n_0; + wire i__carry_i_3__11_n_0; + wire i__carry_i_3__12_n_0; + wire i__carry_i_3__1_n_0; + wire i__carry_i_3__2_n_0; + wire i__carry_i_3__3_n_0; + wire i__carry_i_3__4_n_0; + wire i__carry_i_3__5_n_0; + wire i__carry_i_3__6_n_0; + wire i__carry_i_3__7_n_0; + wire i__carry_i_3__8_n_0; + wire i__carry_i_3__9_n_0; + wire i__carry_i_3_n_0; + wire i__carry_i_4__0_n_0; + wire i__carry_i_4__10_n_0; + wire i__carry_i_4__11_n_0; + wire i__carry_i_4__12_n_0; + wire i__carry_i_4__1_n_0; + wire i__carry_i_4__2_n_0; + wire i__carry_i_4__3_n_0; + wire i__carry_i_4__4_n_0; + wire i__carry_i_4__5_n_0; + wire i__carry_i_4__6_n_0; + wire i__carry_i_4__7_n_0; + wire i__carry_i_4__8_n_0; + wire i__carry_i_4__9_n_0; + wire i__carry_i_4_n_0; + wire i__carry_i_5__0_n_0; + wire i__carry_i_5__1_n_0; + wire i__carry_i_5__2_n_0; + wire i__carry_i_5__3_n_0; + wire i__carry_i_5__4_n_0; + wire i__carry_i_5_n_0; + wire i__carry_i_6__0_n_0; + wire i__carry_i_6__1_n_0; + wire i__carry_i_6__2_n_0; + wire i__carry_i_6_n_0; + wire i__carry_i_7__0_n_0; + wire i__carry_i_7__1_n_0; + wire i__carry_i_7__2_n_0; + wire i__carry_i_7_n_0; + wire i__carry_i_8__0_n_0; + wire i__carry_i_8__1_n_0; + wire i__carry_i_8__2_n_0; + wire i__carry_i_8_n_0; + wire [0:0]intc_if; + wire intr_status_int17_out; + wire \intr_status_int_reg[11] ; + wire last_chroma; + wire leqOp; + wire leqOp_1; + wire leqOp_carry__0_i_1_n_0; + wire leqOp_carry__0_i_2_n_0; + wire leqOp_carry__0_i_3_n_0; + wire leqOp_carry__0_i_4_n_0; + wire leqOp_carry__0_i_5_n_0; + wire leqOp_carry__0_n_2; + wire leqOp_carry__0_n_3; + wire leqOp_carry_i_1_n_0; + wire leqOp_carry_i_2_n_0; + wire leqOp_carry_i_3_n_0; + wire leqOp_carry_i_4_n_0; + wire leqOp_carry_i_5_n_0; + wire leqOp_carry_i_6_n_0; + wire leqOp_carry_i_7_n_0; + wire leqOp_carry_i_8_n_0; + wire leqOp_carry_n_0; + wire leqOp_carry_n_1; + wire leqOp_carry_n_2; + wire leqOp_carry_n_3; + wire \leqOp_inferred__0/i__carry__0_n_2 ; + wire \leqOp_inferred__0/i__carry__0_n_3 ; + wire \leqOp_inferred__0/i__carry_n_0 ; + wire \leqOp_inferred__0/i__carry_n_1 ; + wire \leqOp_inferred__0/i__carry_n_2 ; + wire \leqOp_inferred__0/i__carry_n_3 ; + wire line_end; + wire line_end_d_reg_n_0; + wire lost_lock; + wire ltOp; + wire ltOp_carry__0_i_1_n_0; + wire ltOp_carry__0_i_2_n_0; + wire ltOp_carry__0_i_3_n_0; + wire ltOp_carry__0_i_4_n_0; + wire ltOp_carry__0_n_3; + wire ltOp_carry_i_1_n_0; + wire ltOp_carry_i_2_n_0; + wire ltOp_carry_i_3_n_0; + wire ltOp_carry_i_4_n_0; + wire ltOp_carry_i_5_n_0; + wire ltOp_carry_i_6_n_0; + wire ltOp_carry_i_7_n_0; + wire ltOp_carry_i_8_n_0; + wire ltOp_carry_n_0; + wire ltOp_carry_n_1; + wire ltOp_carry_n_2; + wire ltOp_carry_n_3; + wire \ltOp_inferred__0/i__carry__0_n_2 ; + wire \ltOp_inferred__0/i__carry__0_n_3 ; + wire \ltOp_inferred__0/i__carry_n_0 ; + wire \ltOp_inferred__0/i__carry_n_1 ; + wire \ltOp_inferred__0/i__carry_n_2 ; + wire \ltOp_inferred__0/i__carry_n_3 ; + wire [11:0]minusOp0_out; + wire [11:0]minusOp1_out; + wire minusOp_carry__0_i_1_n_0; + wire minusOp_carry__0_i_2_n_0; + wire minusOp_carry__0_i_3_n_0; + wire minusOp_carry__0_i_4_n_0; + wire minusOp_carry__0_n_0; + wire minusOp_carry__0_n_1; + wire minusOp_carry__0_n_2; + wire minusOp_carry__0_n_3; + wire minusOp_carry__1_i_1_n_0; + wire minusOp_carry__1_i_2_n_0; + wire minusOp_carry__1_i_3_n_0; + wire minusOp_carry__1_i_4_n_0; + wire minusOp_carry__1_n_1; + wire minusOp_carry__1_n_2; + wire minusOp_carry__1_n_3; + wire minusOp_carry_i_1_n_0; + wire minusOp_carry_i_2_n_0; + wire minusOp_carry_i_3_n_0; + wire minusOp_carry_i_4_n_0; + wire minusOp_carry_n_0; + wire minusOp_carry_n_1; + wire minusOp_carry_n_2; + wire minusOp_carry_n_3; + wire \minusOp_inferred__0/i__carry__0_n_0 ; + wire \minusOp_inferred__0/i__carry__0_n_1 ; + wire \minusOp_inferred__0/i__carry__0_n_2 ; + wire \minusOp_inferred__0/i__carry__0_n_3 ; + wire \minusOp_inferred__0/i__carry__1_n_1 ; + wire \minusOp_inferred__0/i__carry__1_n_2 ; + wire \minusOp_inferred__0/i__carry__1_n_3 ; + wire \minusOp_inferred__0/i__carry_n_0 ; + wire \minusOp_inferred__0/i__carry_n_1 ; + wire \minusOp_inferred__0/i__carry_n_2 ; + wire \minusOp_inferred__0/i__carry_n_3 ; + wire neqOp; + wire neqOp0_out; + wire neqOp1_out; + wire neqOp2_out; + wire neqOp3_out; + wire neqOp_carry_i_1_n_0; + wire neqOp_carry_i_2_n_0; + wire neqOp_carry_i_3_n_0; + wire neqOp_carry_i_4_n_0; + wire neqOp_carry_n_1; + wire neqOp_carry_n_2; + wire neqOp_carry_n_3; + wire \neqOp_inferred__0/i__carry_n_1 ; + wire \neqOp_inferred__0/i__carry_n_2 ; + wire \neqOp_inferred__0/i__carry_n_3 ; + wire \neqOp_inferred__1/i__carry_n_0 ; + wire \neqOp_inferred__1/i__carry_n_1 ; + wire \neqOp_inferred__1/i__carry_n_2 ; + wire \neqOp_inferred__1/i__carry_n_3 ; + wire \neqOp_inferred__2/i__carry_n_1 ; + wire \neqOp_inferred__2/i__carry_n_2 ; + wire \neqOp_inferred__2/i__carry_n_3 ; + wire \neqOp_inferred__3/i__carry_n_0 ; + wire \neqOp_inferred__3/i__carry_n_1 ; + wire \neqOp_inferred__3/i__carry_n_2 ; + wire \neqOp_inferred__3/i__carry_n_3 ; + wire \neqOp_inferred__4/i__carry_n_1 ; + wire \neqOp_inferred__4/i__carry_n_2 ; + wire \neqOp_inferred__4/i__carry_n_3 ; + wire \neqOp_inferred__5/i__carry_n_1 ; + wire \neqOp_inferred__5/i__carry_n_2 ; + wire \neqOp_inferred__5/i__carry_n_3 ; + wire p_0_in16_in; + wire p_1_in; + wire p_30_out; + wire p_5_out; + wire p_7_out; + wire [11:0]plusOp; + wire [10:0]plusOp__0; + wire [10:0]plusOp__1; + wire \plusOp_inferred__2/i__carry__0_n_0 ; + wire \plusOp_inferred__2/i__carry__0_n_1 ; + wire \plusOp_inferred__2/i__carry__0_n_2 ; + wire \plusOp_inferred__2/i__carry__0_n_3 ; + wire \plusOp_inferred__2/i__carry__0_n_4 ; + wire \plusOp_inferred__2/i__carry__0_n_5 ; + wire \plusOp_inferred__2/i__carry__0_n_6 ; + wire \plusOp_inferred__2/i__carry__0_n_7 ; + wire \plusOp_inferred__2/i__carry__1_n_1 ; + wire \plusOp_inferred__2/i__carry__1_n_2 ; + wire \plusOp_inferred__2/i__carry__1_n_3 ; + wire \plusOp_inferred__2/i__carry__1_n_4 ; + wire \plusOp_inferred__2/i__carry__1_n_5 ; + wire \plusOp_inferred__2/i__carry__1_n_6 ; + wire \plusOp_inferred__2/i__carry__1_n_7 ; + wire \plusOp_inferred__2/i__carry_n_0 ; + wire \plusOp_inferred__2/i__carry_n_1 ; + wire \plusOp_inferred__2/i__carry_n_2 ; + wire \plusOp_inferred__2/i__carry_n_3 ; + wire \plusOp_inferred__2/i__carry_n_4 ; + wire \plusOp_inferred__2/i__carry_n_5 ; + wire \plusOp_inferred__2/i__carry_n_6 ; + wire \plusOp_inferred__2/i__carry_n_7 ; + wire reset; + wire resetn_out; + wire [2:0]\time_status_regs[3] ; + wire [23:0]\time_status_regs[6] ; + wire [23:0]\time_status_regs[7] ; + wire [21:0]\time_status_regs[8] ; + wire [23:0]\time_status_regs[9] ; + wire [10:0]\time_status_regs_int_reg[0] ; + wire top_of_frame141_out; + wire top_of_frame_i_1_n_0; + wire top_of_frame_reg_n_0; + wire \v_count[10]_i_1_n_0 ; + wire \v_count[10]_i_5_n_0 ; + wire [10:0]v_count_last; + wire [10:0]v_count_reg__0; + wire vblank_in; + wire vsync_count; + wire vsync_delay; + wire vsync_in; + wire vsync_lock_int; + wire vsync_rose; + wire [3:3]\NLW_DET_HACTIVE.active_video_count_reg[8]_i_1_CO_UNCONNECTED ; + wire [3:3]\NLW_DET_HSYNC.hsync_count_reg[8]_i_1_CO_UNCONNECTED ; + wire [3:3]\NLW__inferred__11/i__carry__1_CO_UNCONNECTED ; + wire [3:3]\NLW__inferred__8/i__carry__1_CO_UNCONNECTED ; + wire [3:2]\NLW_det_htotal_int2_reg[11]_i_1_CO_UNCONNECTED ; + wire [3:3]\NLW_det_htotal_int2_reg[11]_i_1_O_UNCONNECTED ; + wire [3:1]\NLW_det_v0active_start_hori_int2_reg[0]_i_2_CO_UNCONNECTED ; + wire [3:0]\NLW_det_v0active_start_hori_int2_reg[0]_i_2_O_UNCONNECTED ; + wire [3:0]\NLW_det_v0active_start_hori_int2_reg[0]_i_3_O_UNCONNECTED ; + wire [3:3]\NLW_det_v0active_start_hori_int2_reg[11]_i_1_CO_UNCONNECTED ; + wire [0:0]\NLW_det_v0active_start_hori_int2_reg[3]_i_1_O_UNCONNECTED ; + wire [3:2]\NLW_det_v0bp_start_int2_reg[10]_i_1_CO_UNCONNECTED ; + wire [3:3]\NLW_det_v0bp_start_int2_reg[10]_i_1_O_UNCONNECTED ; + wire [3:1]\NLW_det_v0fp_start_hori_int2_reg[0]_i_2_CO_UNCONNECTED ; + wire [3:0]\NLW_det_v0fp_start_hori_int2_reg[0]_i_2_O_UNCONNECTED ; + wire [3:0]\NLW_det_v0fp_start_hori_int2_reg[0]_i_3_O_UNCONNECTED ; + wire [3:3]\NLW_det_v0fp_start_hori_int2_reg[11]_i_1_CO_UNCONNECTED ; + wire [0:0]\NLW_det_v0fp_start_hori_int2_reg[3]_i_1_O_UNCONNECTED ; + wire [3:2]\NLW_det_v0sync_start_int2_reg[10]_i_1_CO_UNCONNECTED ; + wire [3:3]\NLW_det_v0sync_start_int2_reg[10]_i_1_O_UNCONNECTED ; + wire [3:0]NLW_gtOp_carry_O_UNCONNECTED; + wire [3:3]NLW_gtOp_carry__0_CO_UNCONNECTED; + wire [3:0]NLW_gtOp_carry__0_O_UNCONNECTED; + wire [3:0]\NLW_gtOp_inferred__0/i__carry_O_UNCONNECTED ; + wire [3:3]\NLW_gtOp_inferred__0/i__carry__0_CO_UNCONNECTED ; + wire [3:0]\NLW_gtOp_inferred__0/i__carry__0_O_UNCONNECTED ; + wire [3:0]\NLW_gtOp_inferred__2/i__carry_O_UNCONNECTED ; + wire [3:2]\NLW_gtOp_inferred__2/i__carry__0_CO_UNCONNECTED ; + wire [3:0]\NLW_gtOp_inferred__2/i__carry__0_O_UNCONNECTED ; + wire [3:3]\NLW_h_count_reg[8]_i_1_CO_UNCONNECTED ; + wire [3:0]NLW_leqOp_carry_O_UNCONNECTED; + wire [3:3]NLW_leqOp_carry__0_CO_UNCONNECTED; + wire [3:0]NLW_leqOp_carry__0_O_UNCONNECTED; + wire [3:0]\NLW_leqOp_inferred__0/i__carry_O_UNCONNECTED ; + wire [3:3]\NLW_leqOp_inferred__0/i__carry__0_CO_UNCONNECTED ; + wire [3:0]\NLW_leqOp_inferred__0/i__carry__0_O_UNCONNECTED ; + wire [3:0]NLW_ltOp_carry_O_UNCONNECTED; + wire [3:2]NLW_ltOp_carry__0_CO_UNCONNECTED; + wire [3:0]NLW_ltOp_carry__0_O_UNCONNECTED; + wire [3:0]\NLW_ltOp_inferred__0/i__carry_O_UNCONNECTED ; + wire [3:2]\NLW_ltOp_inferred__0/i__carry__0_CO_UNCONNECTED ; + wire [3:0]\NLW_ltOp_inferred__0/i__carry__0_O_UNCONNECTED ; + wire [3:3]NLW_minusOp_carry__1_CO_UNCONNECTED; + wire [3:3]\NLW_minusOp_inferred__0/i__carry__1_CO_UNCONNECTED ; + wire [3:0]NLW_neqOp_carry_O_UNCONNECTED; + wire [3:0]\NLW_neqOp_inferred__0/i__carry_O_UNCONNECTED ; + wire [3:0]\NLW_neqOp_inferred__1/i__carry_O_UNCONNECTED ; + wire [3:0]\NLW_neqOp_inferred__2/i__carry_O_UNCONNECTED ; + wire [3:0]\NLW_neqOp_inferred__3/i__carry_O_UNCONNECTED ; + wire [3:0]\NLW_neqOp_inferred__4/i__carry_O_UNCONNECTED ; + wire [3:0]\NLW_neqOp_inferred__5/i__carry_O_UNCONNECTED ; + wire [3:3]\NLW_plusOp_inferred__2/i__carry__1_CO_UNCONNECTED ; + + LUT3 #( + .INIT(8'h40)) + \DET_HACTIVE.DET_AVIDEO_LOCK.active_video_count_last[11]_i_1 + (.I0(active_video_d2), + .I1(active_video_d), + .I2(det_ce), + .O(last_chroma)); + FDSE #( + .INIT(1'b0)) + \DET_HACTIVE.DET_AVIDEO_LOCK.active_video_count_last_reg[0] + (.C(clk), + .CE(last_chroma), + .D(\DET_HACTIVE.active_video_count_reg [0]), + .Q(active_video_count_last[0]), + .S(p_5_out)); + FDSE #( + .INIT(1'b0)) + \DET_HACTIVE.DET_AVIDEO_LOCK.active_video_count_last_reg[10] + (.C(clk), + .CE(last_chroma), + .D(\DET_HACTIVE.active_video_count_reg [10]), + .Q(active_video_count_last[10]), + .S(p_5_out)); + FDSE #( + .INIT(1'b0)) + \DET_HACTIVE.DET_AVIDEO_LOCK.active_video_count_last_reg[11] + (.C(clk), + .CE(last_chroma), + .D(\DET_HACTIVE.active_video_count_reg [11]), + .Q(active_video_count_last[11]), + .S(p_5_out)); + FDSE #( + .INIT(1'b0)) + \DET_HACTIVE.DET_AVIDEO_LOCK.active_video_count_last_reg[1] + (.C(clk), + .CE(last_chroma), + .D(\DET_HACTIVE.active_video_count_reg [1]), + .Q(active_video_count_last[1]), + .S(p_5_out)); + FDSE #( + .INIT(1'b0)) + \DET_HACTIVE.DET_AVIDEO_LOCK.active_video_count_last_reg[2] + (.C(clk), + .CE(last_chroma), + .D(\DET_HACTIVE.active_video_count_reg [2]), + .Q(active_video_count_last[2]), + .S(p_5_out)); + FDSE #( + .INIT(1'b0)) + \DET_HACTIVE.DET_AVIDEO_LOCK.active_video_count_last_reg[3] + (.C(clk), + .CE(last_chroma), + .D(\DET_HACTIVE.active_video_count_reg [3]), + .Q(active_video_count_last[3]), + .S(p_5_out)); + FDSE #( + .INIT(1'b0)) + \DET_HACTIVE.DET_AVIDEO_LOCK.active_video_count_last_reg[4] + (.C(clk), + .CE(last_chroma), + .D(\DET_HACTIVE.active_video_count_reg [4]), + .Q(active_video_count_last[4]), + .S(p_5_out)); + FDSE #( + .INIT(1'b0)) + \DET_HACTIVE.DET_AVIDEO_LOCK.active_video_count_last_reg[5] + (.C(clk), + .CE(last_chroma), + .D(\DET_HACTIVE.active_video_count_reg [5]), + .Q(active_video_count_last[5]), + .S(p_5_out)); + FDSE #( + .INIT(1'b0)) + \DET_HACTIVE.DET_AVIDEO_LOCK.active_video_count_last_reg[6] + (.C(clk), + .CE(last_chroma), + .D(\DET_HACTIVE.active_video_count_reg [6]), + .Q(active_video_count_last[6]), + .S(p_5_out)); + FDSE #( + .INIT(1'b0)) + \DET_HACTIVE.DET_AVIDEO_LOCK.active_video_count_last_reg[7] + (.C(clk), + .CE(last_chroma), + .D(\DET_HACTIVE.active_video_count_reg [7]), + .Q(active_video_count_last[7]), + .S(p_5_out)); + FDSE #( + .INIT(1'b0)) + \DET_HACTIVE.DET_AVIDEO_LOCK.active_video_count_last_reg[8] + (.C(clk), + .CE(last_chroma), + .D(\DET_HACTIVE.active_video_count_reg [8]), + .Q(active_video_count_last[8]), + .S(p_5_out)); + FDSE #( + .INIT(1'b0)) + \DET_HACTIVE.DET_AVIDEO_LOCK.active_video_count_last_reg[9] + (.C(clk), + .CE(last_chroma), + .D(\DET_HACTIVE.active_video_count_reg [9]), + .Q(active_video_count_last[9]), + .S(p_5_out)); + LUT6 #( + .INIT(64'h0000000A0003000A)) + \DET_HACTIVE.DET_AVIDEO_LOCK.det_active_video_lock_int_i_1 + (.I0(active_video_lock_int), + .I1(det_active_video_pol_change), + .I2(h_count1), + .I3(lost_lock), + .I4(last_chroma), + .I5(neqOp1_out), + .O(\DET_HACTIVE.DET_AVIDEO_LOCK.det_active_video_lock_int_i_1_n_0 )); + FDRE \DET_HACTIVE.DET_AVIDEO_LOCK.det_active_video_lock_int_reg + (.C(clk), + .CE(1'b1), + .D(\DET_HACTIVE.DET_AVIDEO_LOCK.det_active_video_lock_int_i_1_n_0 ), + .Q(active_video_lock_int), + .R(1'b0)); + LUT4 #( + .INIT(16'hFF08)) + \DET_HACTIVE.active_video_count[0]_i_1 + (.I0(det_ce), + .I1(active_video_d), + .I2(active_video_d2), + .I3(h_count1), + .O(\DET_HACTIVE.active_video_count[0]_i_1_n_0 )); + LUT2 #( + .INIT(4'h8)) + \DET_HACTIVE.active_video_count[0]_i_2 + (.I0(det_ce), + .I1(active_video_d), + .O(active_video_count)); + LUT1 #( + .INIT(2'h2)) + \DET_HACTIVE.active_video_count[0]_i_4 + (.I0(\DET_HACTIVE.active_video_count_reg [3]), + .O(\DET_HACTIVE.active_video_count[0]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \DET_HACTIVE.active_video_count[0]_i_5 + (.I0(\DET_HACTIVE.active_video_count_reg [2]), + .O(\DET_HACTIVE.active_video_count[0]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \DET_HACTIVE.active_video_count[0]_i_6 + (.I0(\DET_HACTIVE.active_video_count_reg [1]), + .O(\DET_HACTIVE.active_video_count[0]_i_6_n_0 )); + LUT1 #( + .INIT(2'h1)) + \DET_HACTIVE.active_video_count[0]_i_7 + (.I0(\DET_HACTIVE.active_video_count_reg [0]), + .O(\DET_HACTIVE.active_video_count[0]_i_7_n_0 )); + LUT1 #( + .INIT(2'h2)) + \DET_HACTIVE.active_video_count[4]_i_2 + (.I0(\DET_HACTIVE.active_video_count_reg [7]), + .O(\DET_HACTIVE.active_video_count[4]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \DET_HACTIVE.active_video_count[4]_i_3 + (.I0(\DET_HACTIVE.active_video_count_reg [6]), + .O(\DET_HACTIVE.active_video_count[4]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \DET_HACTIVE.active_video_count[4]_i_4 + (.I0(\DET_HACTIVE.active_video_count_reg [5]), + .O(\DET_HACTIVE.active_video_count[4]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \DET_HACTIVE.active_video_count[4]_i_5 + (.I0(\DET_HACTIVE.active_video_count_reg [4]), + .O(\DET_HACTIVE.active_video_count[4]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \DET_HACTIVE.active_video_count[8]_i_2 + (.I0(\DET_HACTIVE.active_video_count_reg [11]), + .O(\DET_HACTIVE.active_video_count[8]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \DET_HACTIVE.active_video_count[8]_i_3 + (.I0(\DET_HACTIVE.active_video_count_reg [10]), + .O(\DET_HACTIVE.active_video_count[8]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \DET_HACTIVE.active_video_count[8]_i_4 + (.I0(\DET_HACTIVE.active_video_count_reg [9]), + .O(\DET_HACTIVE.active_video_count[8]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \DET_HACTIVE.active_video_count[8]_i_5 + (.I0(\DET_HACTIVE.active_video_count_reg [8]), + .O(\DET_HACTIVE.active_video_count[8]_i_5_n_0 )); + FDRE #( + .INIT(1'b0)) + \DET_HACTIVE.active_video_count_reg[0] + (.C(clk), + .CE(active_video_count), + .D(\DET_HACTIVE.active_video_count_reg[0]_i_3_n_7 ), + .Q(\DET_HACTIVE.active_video_count_reg [0]), + .R(\DET_HACTIVE.active_video_count[0]_i_1_n_0 )); + CARRY4 \DET_HACTIVE.active_video_count_reg[0]_i_3 + (.CI(1'b0), + .CO({\DET_HACTIVE.active_video_count_reg[0]_i_3_n_0 ,\DET_HACTIVE.active_video_count_reg[0]_i_3_n_1 ,\DET_HACTIVE.active_video_count_reg[0]_i_3_n_2 ,\DET_HACTIVE.active_video_count_reg[0]_i_3_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\DET_HACTIVE.active_video_count_reg[0]_i_3_n_4 ,\DET_HACTIVE.active_video_count_reg[0]_i_3_n_5 ,\DET_HACTIVE.active_video_count_reg[0]_i_3_n_6 ,\DET_HACTIVE.active_video_count_reg[0]_i_3_n_7 }), + .S({\DET_HACTIVE.active_video_count[0]_i_4_n_0 ,\DET_HACTIVE.active_video_count[0]_i_5_n_0 ,\DET_HACTIVE.active_video_count[0]_i_6_n_0 ,\DET_HACTIVE.active_video_count[0]_i_7_n_0 })); + FDRE #( + .INIT(1'b0)) + \DET_HACTIVE.active_video_count_reg[10] + (.C(clk), + .CE(active_video_count), + .D(\DET_HACTIVE.active_video_count_reg[8]_i_1_n_5 ), + .Q(\DET_HACTIVE.active_video_count_reg [10]), + .R(\DET_HACTIVE.active_video_count[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DET_HACTIVE.active_video_count_reg[11] + (.C(clk), + .CE(active_video_count), + .D(\DET_HACTIVE.active_video_count_reg[8]_i_1_n_4 ), + .Q(\DET_HACTIVE.active_video_count_reg [11]), + .R(\DET_HACTIVE.active_video_count[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DET_HACTIVE.active_video_count_reg[1] + (.C(clk), + .CE(active_video_count), + .D(\DET_HACTIVE.active_video_count_reg[0]_i_3_n_6 ), + .Q(\DET_HACTIVE.active_video_count_reg [1]), + .R(\DET_HACTIVE.active_video_count[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DET_HACTIVE.active_video_count_reg[2] + (.C(clk), + .CE(active_video_count), + .D(\DET_HACTIVE.active_video_count_reg[0]_i_3_n_5 ), + .Q(\DET_HACTIVE.active_video_count_reg [2]), + .R(\DET_HACTIVE.active_video_count[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DET_HACTIVE.active_video_count_reg[3] + (.C(clk), + .CE(active_video_count), + .D(\DET_HACTIVE.active_video_count_reg[0]_i_3_n_4 ), + .Q(\DET_HACTIVE.active_video_count_reg [3]), + .R(\DET_HACTIVE.active_video_count[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DET_HACTIVE.active_video_count_reg[4] + (.C(clk), + .CE(active_video_count), + .D(\DET_HACTIVE.active_video_count_reg[4]_i_1_n_7 ), + .Q(\DET_HACTIVE.active_video_count_reg [4]), + .R(\DET_HACTIVE.active_video_count[0]_i_1_n_0 )); + CARRY4 \DET_HACTIVE.active_video_count_reg[4]_i_1 + (.CI(\DET_HACTIVE.active_video_count_reg[0]_i_3_n_0 ), + .CO({\DET_HACTIVE.active_video_count_reg[4]_i_1_n_0 ,\DET_HACTIVE.active_video_count_reg[4]_i_1_n_1 ,\DET_HACTIVE.active_video_count_reg[4]_i_1_n_2 ,\DET_HACTIVE.active_video_count_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\DET_HACTIVE.active_video_count_reg[4]_i_1_n_4 ,\DET_HACTIVE.active_video_count_reg[4]_i_1_n_5 ,\DET_HACTIVE.active_video_count_reg[4]_i_1_n_6 ,\DET_HACTIVE.active_video_count_reg[4]_i_1_n_7 }), + .S({\DET_HACTIVE.active_video_count[4]_i_2_n_0 ,\DET_HACTIVE.active_video_count[4]_i_3_n_0 ,\DET_HACTIVE.active_video_count[4]_i_4_n_0 ,\DET_HACTIVE.active_video_count[4]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \DET_HACTIVE.active_video_count_reg[5] + (.C(clk), + .CE(active_video_count), + .D(\DET_HACTIVE.active_video_count_reg[4]_i_1_n_6 ), + .Q(\DET_HACTIVE.active_video_count_reg [5]), + .R(\DET_HACTIVE.active_video_count[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DET_HACTIVE.active_video_count_reg[6] + (.C(clk), + .CE(active_video_count), + .D(\DET_HACTIVE.active_video_count_reg[4]_i_1_n_5 ), + .Q(\DET_HACTIVE.active_video_count_reg [6]), + .R(\DET_HACTIVE.active_video_count[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DET_HACTIVE.active_video_count_reg[7] + (.C(clk), + .CE(active_video_count), + .D(\DET_HACTIVE.active_video_count_reg[4]_i_1_n_4 ), + .Q(\DET_HACTIVE.active_video_count_reg [7]), + .R(\DET_HACTIVE.active_video_count[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DET_HACTIVE.active_video_count_reg[8] + (.C(clk), + .CE(active_video_count), + .D(\DET_HACTIVE.active_video_count_reg[8]_i_1_n_7 ), + .Q(\DET_HACTIVE.active_video_count_reg [8]), + .R(\DET_HACTIVE.active_video_count[0]_i_1_n_0 )); + CARRY4 \DET_HACTIVE.active_video_count_reg[8]_i_1 + (.CI(\DET_HACTIVE.active_video_count_reg[4]_i_1_n_0 ), + .CO({\NLW_DET_HACTIVE.active_video_count_reg[8]_i_1_CO_UNCONNECTED [3],\DET_HACTIVE.active_video_count_reg[8]_i_1_n_1 ,\DET_HACTIVE.active_video_count_reg[8]_i_1_n_2 ,\DET_HACTIVE.active_video_count_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\DET_HACTIVE.active_video_count_reg[8]_i_1_n_4 ,\DET_HACTIVE.active_video_count_reg[8]_i_1_n_5 ,\DET_HACTIVE.active_video_count_reg[8]_i_1_n_6 ,\DET_HACTIVE.active_video_count_reg[8]_i_1_n_7 }), + .S({\DET_HACTIVE.active_video_count[8]_i_2_n_0 ,\DET_HACTIVE.active_video_count[8]_i_3_n_0 ,\DET_HACTIVE.active_video_count[8]_i_4_n_0 ,\DET_HACTIVE.active_video_count[8]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \DET_HACTIVE.active_video_count_reg[9] + (.C(clk), + .CE(active_video_count), + .D(\DET_HACTIVE.active_video_count_reg[8]_i_1_n_6 ), + .Q(\DET_HACTIVE.active_video_count_reg [9]), + .R(\DET_HACTIVE.active_video_count[0]_i_1_n_0 )); + LUT3 #( + .INIT(8'hF4)) + \DET_HACTIVE.active_video_d2_i_1 + (.I0(\DET_VSYNC.vsync_d2_reg_n_0 ), + .I1(\DET_VSYNC.vsync_d_reg_n_0 ), + .I2(h_count1), + .O(p_7_out)); + LUT3 #( + .INIT(8'hB8)) + \DET_HACTIVE.active_video_d2_i_2 + (.I0(active_video_d), + .I1(det_ce), + .I2(active_video_d2), + .O(\DET_HACTIVE.active_video_d2_i_2_n_0 )); + FDRE \DET_HACTIVE.active_video_d2_reg + (.C(clk), + .CE(1'b1), + .D(\DET_HACTIVE.active_video_d2_i_2_n_0 ), + .Q(active_video_d2), + .R(p_7_out)); + LUT5 #( + .INIT(32'h0000E22E)) + \DET_HACTIVE.active_video_d_i_1 + (.I0(active_video_d), + .I1(det_ce), + .I2(\time_status_regs[3] [2]), + .I3(active_video_in), + .I4(p_7_out), + .O(\DET_HACTIVE.active_video_d_i_1_n_0 )); + FDRE \DET_HACTIVE.active_video_d_reg + (.C(clk), + .CE(1'b1), + .D(\DET_HACTIVE.active_video_d_i_1_n_0 ), + .Q(active_video_d), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair270" *) + LUT5 #( + .INIT(32'h0000BAAA)) + \DET_HACTIVE.active_video_rose_i_1 + (.I0(active_video_rose), + .I1(active_video_d), + .I2(active_video_d2), + .I3(det_ce), + .I4(p_7_out), + .O(\DET_HACTIVE.active_video_rose_i_1_n_0 )); + FDRE \DET_HACTIVE.active_video_rose_reg + (.C(clk), + .CE(1'b1), + .D(\DET_HACTIVE.active_video_rose_i_1_n_0 ), + .Q(active_video_rose), + .R(1'b0)); + LUT6 #( + .INIT(64'h00E200E2000000E2)) + \DET_HACTIVE.active_video_toggled_i_1 + (.I0(active_video_toggled), + .I1(last_chroma), + .I2(active_video_rose), + .I3(h_count1), + .I4(\DET_VSYNC.vsync_d_reg_n_0 ), + .I5(\DET_VSYNC.vsync_d2_reg_n_0 ), + .O(\DET_HACTIVE.active_video_toggled_i_1_n_0 )); + FDRE \DET_HACTIVE.active_video_toggled_reg + (.C(clk), + .CE(1'b1), + .D(\DET_HACTIVE.active_video_toggled_i_1_n_0 ), + .Q(active_video_toggled), + .R(1'b0)); + FDRE \DET_HACTIVE.det_active_video_pol_change_reg + (.C(clk), + .CE(det_ce), + .D(leqOp), + .Q(det_active_video_pol_change), + .R(h_count1)); + LUT5 #( + .INIT(32'hDFFF2000)) + \DET_HACTIVE.det_active_video_pol_int_i_1 + (.I0(active_video_d2), + .I1(active_video_d), + .I2(det_ce), + .I3(det_active_video_pol_change), + .I4(\time_status_regs[3] [2]), + .O(\DET_HACTIVE.det_active_video_pol_int_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \DET_HACTIVE.det_active_video_pol_int_reg + (.C(clk), + .CE(1'b1), + .D(\DET_HACTIVE.det_active_video_pol_int_i_1_n_0 ), + .Q(\time_status_regs[3] [2]), + .S(h_count1)); + LUT2 #( + .INIT(4'hE)) + \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hbp_start_last[11]_i_1 + (.I0(h_count1), + .I1(lost_lock), + .O(p_5_out)); + FDSE \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hbp_start_last_reg[0] + (.C(clk), + .CE(det_hbp_start_int_9), + .D(det_hbp_start_int[0]), + .Q(det_hbp_start_last[0]), + .S(p_5_out)); + FDSE \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hbp_start_last_reg[10] + (.C(clk), + .CE(det_hbp_start_int_9), + .D(det_hbp_start_int[10]), + .Q(det_hbp_start_last[10]), + .S(p_5_out)); + FDSE \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hbp_start_last_reg[11] + (.C(clk), + .CE(det_hbp_start_int_9), + .D(det_hbp_start_int[11]), + .Q(det_hbp_start_last[11]), + .S(p_5_out)); + FDSE \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hbp_start_last_reg[1] + (.C(clk), + .CE(det_hbp_start_int_9), + .D(det_hbp_start_int[1]), + .Q(det_hbp_start_last[1]), + .S(p_5_out)); + FDSE \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hbp_start_last_reg[2] + (.C(clk), + .CE(det_hbp_start_int_9), + .D(det_hbp_start_int[2]), + .Q(det_hbp_start_last[2]), + .S(p_5_out)); + FDSE \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hbp_start_last_reg[3] + (.C(clk), + .CE(det_hbp_start_int_9), + .D(det_hbp_start_int[3]), + .Q(det_hbp_start_last[3]), + .S(p_5_out)); + FDSE \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hbp_start_last_reg[4] + (.C(clk), + .CE(det_hbp_start_int_9), + .D(det_hbp_start_int[4]), + .Q(det_hbp_start_last[4]), + .S(p_5_out)); + FDSE \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hbp_start_last_reg[5] + (.C(clk), + .CE(det_hbp_start_int_9), + .D(det_hbp_start_int[5]), + .Q(det_hbp_start_last[5]), + .S(p_5_out)); + FDSE \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hbp_start_last_reg[6] + (.C(clk), + .CE(det_hbp_start_int_9), + .D(det_hbp_start_int[6]), + .Q(det_hbp_start_last[6]), + .S(p_5_out)); + FDSE \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hbp_start_last_reg[7] + (.C(clk), + .CE(det_hbp_start_int_9), + .D(det_hbp_start_int[7]), + .Q(det_hbp_start_last[7]), + .S(p_5_out)); + FDSE \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hbp_start_last_reg[8] + (.C(clk), + .CE(det_hbp_start_int_9), + .D(det_hbp_start_int[8]), + .Q(det_hbp_start_last[8]), + .S(p_5_out)); + FDSE \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hbp_start_last_reg[9] + (.C(clk), + .CE(det_hbp_start_int_9), + .D(det_hbp_start_int[9]), + .Q(det_hbp_start_last[9]), + .S(p_5_out)); + LUT6 #( + .INIT(64'h000000000A0A0A3A)) + \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_lock_int_i_1 + (.I0(hsync_lock_int), + .I1(det_hsync_pol_change), + .I2(det_ce), + .I3(neqOp2_out), + .I4(neqOp3_out), + .I5(p_5_out), + .O(\DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_lock_int_i_1_n_0 )); + FDRE \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_lock_int_reg + (.C(clk), + .CE(1'b1), + .D(\DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_lock_int_i_1_n_0 ), + .Q(hsync_lock_int), + .R(1'b0)); + FDSE \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_start_last_reg[0] + (.C(clk), + .CE(det_hsync_start_int_2), + .D(det_hsync_start_int[0]), + .Q(det_hsync_start_last[0]), + .S(p_5_out)); + FDSE \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_start_last_reg[10] + (.C(clk), + .CE(det_hsync_start_int_2), + .D(det_hsync_start_int[10]), + .Q(det_hsync_start_last[10]), + .S(p_5_out)); + FDSE \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_start_last_reg[11] + (.C(clk), + .CE(det_hsync_start_int_2), + .D(det_hsync_start_int[11]), + .Q(det_hsync_start_last[11]), + .S(p_5_out)); + FDSE \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_start_last_reg[1] + (.C(clk), + .CE(det_hsync_start_int_2), + .D(det_hsync_start_int[1]), + .Q(det_hsync_start_last[1]), + .S(p_5_out)); + FDSE \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_start_last_reg[2] + (.C(clk), + .CE(det_hsync_start_int_2), + .D(det_hsync_start_int[2]), + .Q(det_hsync_start_last[2]), + .S(p_5_out)); + FDSE \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_start_last_reg[3] + (.C(clk), + .CE(det_hsync_start_int_2), + .D(det_hsync_start_int[3]), + .Q(det_hsync_start_last[3]), + .S(p_5_out)); + FDSE \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_start_last_reg[4] + (.C(clk), + .CE(det_hsync_start_int_2), + .D(det_hsync_start_int[4]), + .Q(det_hsync_start_last[4]), + .S(p_5_out)); + FDSE \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_start_last_reg[5] + (.C(clk), + .CE(det_hsync_start_int_2), + .D(det_hsync_start_int[5]), + .Q(det_hsync_start_last[5]), + .S(p_5_out)); + FDSE \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_start_last_reg[6] + (.C(clk), + .CE(det_hsync_start_int_2), + .D(det_hsync_start_int[6]), + .Q(det_hsync_start_last[6]), + .S(p_5_out)); + FDSE \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_start_last_reg[7] + (.C(clk), + .CE(det_hsync_start_int_2), + .D(det_hsync_start_int[7]), + .Q(det_hsync_start_last[7]), + .S(p_5_out)); + FDSE \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_start_last_reg[8] + (.C(clk), + .CE(det_hsync_start_int_2), + .D(det_hsync_start_int[8]), + .Q(det_hsync_start_last[8]), + .S(p_5_out)); + FDSE \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_start_last_reg[9] + (.C(clk), + .CE(det_hsync_start_int_2), + .D(det_hsync_start_int[9]), + .Q(det_hsync_start_last[9]), + .S(p_5_out)); + LUT3 #( + .INIT(8'h40)) + \DET_HSYNC.det_hbp_start_int[11]_i_1 + (.I0(hsync_d), + .I1(hsync_d2), + .I2(det_ce), + .O(det_hbp_start_int_9)); + FDRE \DET_HSYNC.det_hbp_start_int_reg[0] + (.C(clk), + .CE(det_hbp_start_int_9), + .D(L[11]), + .Q(det_hbp_start_int[0]), + .R(h_count1)); + FDRE \DET_HSYNC.det_hbp_start_int_reg[10] + (.C(clk), + .CE(det_hbp_start_int_9), + .D(L[1]), + .Q(det_hbp_start_int[10]), + .R(h_count1)); + FDRE \DET_HSYNC.det_hbp_start_int_reg[11] + (.C(clk), + .CE(det_hbp_start_int_9), + .D(L[0]), + .Q(det_hbp_start_int[11]), + .R(h_count1)); + FDRE \DET_HSYNC.det_hbp_start_int_reg[1] + (.C(clk), + .CE(det_hbp_start_int_9), + .D(L[10]), + .Q(det_hbp_start_int[1]), + .R(h_count1)); + FDRE \DET_HSYNC.det_hbp_start_int_reg[2] + (.C(clk), + .CE(det_hbp_start_int_9), + .D(L[9]), + .Q(det_hbp_start_int[2]), + .R(h_count1)); + FDRE \DET_HSYNC.det_hbp_start_int_reg[3] + (.C(clk), + .CE(det_hbp_start_int_9), + .D(L[8]), + .Q(det_hbp_start_int[3]), + .R(h_count1)); + FDRE \DET_HSYNC.det_hbp_start_int_reg[4] + (.C(clk), + .CE(det_hbp_start_int_9), + .D(L[7]), + .Q(det_hbp_start_int[4]), + .R(h_count1)); + FDRE \DET_HSYNC.det_hbp_start_int_reg[5] + (.C(clk), + .CE(det_hbp_start_int_9), + .D(L[6]), + .Q(det_hbp_start_int[5]), + .R(h_count1)); + FDRE \DET_HSYNC.det_hbp_start_int_reg[6] + (.C(clk), + .CE(det_hbp_start_int_9), + .D(L[5]), + .Q(det_hbp_start_int[6]), + .R(h_count1)); + FDRE \DET_HSYNC.det_hbp_start_int_reg[7] + (.C(clk), + .CE(det_hbp_start_int_9), + .D(L[4]), + .Q(det_hbp_start_int[7]), + .R(h_count1)); + FDRE \DET_HSYNC.det_hbp_start_int_reg[8] + (.C(clk), + .CE(det_hbp_start_int_9), + .D(L[3]), + .Q(det_hbp_start_int[8]), + .R(h_count1)); + FDRE \DET_HSYNC.det_hbp_start_int_reg[9] + (.C(clk), + .CE(det_hbp_start_int_9), + .D(L[2]), + .Q(det_hbp_start_int[9]), + .R(h_count1)); + FDRE \DET_HSYNC.det_hsync_pol_change_reg + (.C(clk), + .CE(det_ce), + .D(gtOp), + .Q(det_hsync_pol_change), + .R(h_count1)); + LUT5 #( + .INIT(32'hBFFF4000)) + \DET_HSYNC.det_hsync_pol_int_i_1 + (.I0(hsync_d), + .I1(hsync_d2), + .I2(det_ce), + .I3(det_hsync_pol_change), + .I4(\time_status_regs[3] [1]), + .O(\DET_HSYNC.det_hsync_pol_int_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \DET_HSYNC.det_hsync_pol_int_reg + (.C(clk), + .CE(1'b1), + .D(\DET_HSYNC.det_hsync_pol_int_i_1_n_0 ), + .Q(\time_status_regs[3] [1]), + .S(h_count1)); + LUT3 #( + .INIT(8'h40)) + \DET_HSYNC.det_hsync_start_int[11]_i_1 + (.I0(hsync_d2), + .I1(hsync_d), + .I2(det_ce), + .O(det_hsync_start_int_2)); + FDRE \DET_HSYNC.det_hsync_start_int_reg[0] + (.C(clk), + .CE(det_hsync_start_int_2), + .D(L[11]), + .Q(det_hsync_start_int[0]), + .R(h_count1)); + FDRE \DET_HSYNC.det_hsync_start_int_reg[10] + (.C(clk), + .CE(det_hsync_start_int_2), + .D(L[1]), + .Q(det_hsync_start_int[10]), + .R(h_count1)); + FDRE \DET_HSYNC.det_hsync_start_int_reg[11] + (.C(clk), + .CE(det_hsync_start_int_2), + .D(L[0]), + .Q(det_hsync_start_int[11]), + .R(h_count1)); + FDRE \DET_HSYNC.det_hsync_start_int_reg[1] + (.C(clk), + .CE(det_hsync_start_int_2), + .D(L[10]), + .Q(det_hsync_start_int[1]), + .R(h_count1)); + FDRE \DET_HSYNC.det_hsync_start_int_reg[2] + (.C(clk), + .CE(det_hsync_start_int_2), + .D(L[9]), + .Q(det_hsync_start_int[2]), + .R(h_count1)); + FDRE \DET_HSYNC.det_hsync_start_int_reg[3] + (.C(clk), + .CE(det_hsync_start_int_2), + .D(L[8]), + .Q(det_hsync_start_int[3]), + .R(h_count1)); + FDRE \DET_HSYNC.det_hsync_start_int_reg[4] + (.C(clk), + .CE(det_hsync_start_int_2), + .D(L[7]), + .Q(det_hsync_start_int[4]), + .R(h_count1)); + FDRE \DET_HSYNC.det_hsync_start_int_reg[5] + (.C(clk), + .CE(det_hsync_start_int_2), + .D(L[6]), + .Q(det_hsync_start_int[5]), + .R(h_count1)); + FDRE \DET_HSYNC.det_hsync_start_int_reg[6] + (.C(clk), + .CE(det_hsync_start_int_2), + .D(L[5]), + .Q(det_hsync_start_int[6]), + .R(h_count1)); + FDRE \DET_HSYNC.det_hsync_start_int_reg[7] + (.C(clk), + .CE(det_hsync_start_int_2), + .D(L[4]), + .Q(det_hsync_start_int[7]), + .R(h_count1)); + FDRE \DET_HSYNC.det_hsync_start_int_reg[8] + (.C(clk), + .CE(det_hsync_start_int_2), + .D(L[3]), + .Q(det_hsync_start_int[8]), + .R(h_count1)); + FDRE \DET_HSYNC.det_hsync_start_int_reg[9] + (.C(clk), + .CE(det_hsync_start_int_2), + .D(L[2]), + .Q(det_hsync_start_int[9]), + .R(h_count1)); + LUT4 #( + .INIT(16'hAAEA)) + \DET_HSYNC.hsync_count[0]_i_1 + (.I0(h_count1), + .I1(det_ce), + .I2(hsync_d), + .I3(hsync_d2), + .O(\DET_HSYNC.hsync_count[0]_i_1_n_0 )); + LUT2 #( + .INIT(4'h8)) + \DET_HSYNC.hsync_count[0]_i_2 + (.I0(det_ce), + .I1(hsync_d), + .O(\DET_HSYNC.hsync_count[0]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \DET_HSYNC.hsync_count[0]_i_4 + (.I0(\DET_HSYNC.hsync_count_reg [3]), + .O(\DET_HSYNC.hsync_count[0]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \DET_HSYNC.hsync_count[0]_i_5 + (.I0(\DET_HSYNC.hsync_count_reg [2]), + .O(\DET_HSYNC.hsync_count[0]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \DET_HSYNC.hsync_count[0]_i_6 + (.I0(\DET_HSYNC.hsync_count_reg [1]), + .O(\DET_HSYNC.hsync_count[0]_i_6_n_0 )); + LUT1 #( + .INIT(2'h1)) + \DET_HSYNC.hsync_count[0]_i_7 + (.I0(\DET_HSYNC.hsync_count_reg [0]), + .O(\DET_HSYNC.hsync_count[0]_i_7_n_0 )); + LUT1 #( + .INIT(2'h2)) + \DET_HSYNC.hsync_count[4]_i_2 + (.I0(\DET_HSYNC.hsync_count_reg [7]), + .O(\DET_HSYNC.hsync_count[4]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \DET_HSYNC.hsync_count[4]_i_3 + (.I0(\DET_HSYNC.hsync_count_reg [6]), + .O(\DET_HSYNC.hsync_count[4]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \DET_HSYNC.hsync_count[4]_i_4 + (.I0(\DET_HSYNC.hsync_count_reg [5]), + .O(\DET_HSYNC.hsync_count[4]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \DET_HSYNC.hsync_count[4]_i_5 + (.I0(\DET_HSYNC.hsync_count_reg [4]), + .O(\DET_HSYNC.hsync_count[4]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \DET_HSYNC.hsync_count[8]_i_2 + (.I0(\DET_HSYNC.hsync_count_reg [11]), + .O(\DET_HSYNC.hsync_count[8]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \DET_HSYNC.hsync_count[8]_i_3 + (.I0(\DET_HSYNC.hsync_count_reg [10]), + .O(\DET_HSYNC.hsync_count[8]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \DET_HSYNC.hsync_count[8]_i_4 + (.I0(\DET_HSYNC.hsync_count_reg [9]), + .O(\DET_HSYNC.hsync_count[8]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \DET_HSYNC.hsync_count[8]_i_5 + (.I0(\DET_HSYNC.hsync_count_reg [8]), + .O(\DET_HSYNC.hsync_count[8]_i_5_n_0 )); + FDRE #( + .INIT(1'b0)) + \DET_HSYNC.hsync_count_reg[0] + (.C(clk), + .CE(\DET_HSYNC.hsync_count[0]_i_2_n_0 ), + .D(\DET_HSYNC.hsync_count_reg[0]_i_3_n_7 ), + .Q(\DET_HSYNC.hsync_count_reg [0]), + .R(\DET_HSYNC.hsync_count[0]_i_1_n_0 )); + CARRY4 \DET_HSYNC.hsync_count_reg[0]_i_3 + (.CI(1'b0), + .CO({\DET_HSYNC.hsync_count_reg[0]_i_3_n_0 ,\DET_HSYNC.hsync_count_reg[0]_i_3_n_1 ,\DET_HSYNC.hsync_count_reg[0]_i_3_n_2 ,\DET_HSYNC.hsync_count_reg[0]_i_3_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\DET_HSYNC.hsync_count_reg[0]_i_3_n_4 ,\DET_HSYNC.hsync_count_reg[0]_i_3_n_5 ,\DET_HSYNC.hsync_count_reg[0]_i_3_n_6 ,\DET_HSYNC.hsync_count_reg[0]_i_3_n_7 }), + .S({\DET_HSYNC.hsync_count[0]_i_4_n_0 ,\DET_HSYNC.hsync_count[0]_i_5_n_0 ,\DET_HSYNC.hsync_count[0]_i_6_n_0 ,\DET_HSYNC.hsync_count[0]_i_7_n_0 })); + FDRE #( + .INIT(1'b0)) + \DET_HSYNC.hsync_count_reg[10] + (.C(clk), + .CE(\DET_HSYNC.hsync_count[0]_i_2_n_0 ), + .D(\DET_HSYNC.hsync_count_reg[8]_i_1_n_5 ), + .Q(\DET_HSYNC.hsync_count_reg [10]), + .R(\DET_HSYNC.hsync_count[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DET_HSYNC.hsync_count_reg[11] + (.C(clk), + .CE(\DET_HSYNC.hsync_count[0]_i_2_n_0 ), + .D(\DET_HSYNC.hsync_count_reg[8]_i_1_n_4 ), + .Q(\DET_HSYNC.hsync_count_reg [11]), + .R(\DET_HSYNC.hsync_count[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DET_HSYNC.hsync_count_reg[1] + (.C(clk), + .CE(\DET_HSYNC.hsync_count[0]_i_2_n_0 ), + .D(\DET_HSYNC.hsync_count_reg[0]_i_3_n_6 ), + .Q(\DET_HSYNC.hsync_count_reg [1]), + .R(\DET_HSYNC.hsync_count[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DET_HSYNC.hsync_count_reg[2] + (.C(clk), + .CE(\DET_HSYNC.hsync_count[0]_i_2_n_0 ), + .D(\DET_HSYNC.hsync_count_reg[0]_i_3_n_5 ), + .Q(\DET_HSYNC.hsync_count_reg [2]), + .R(\DET_HSYNC.hsync_count[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DET_HSYNC.hsync_count_reg[3] + (.C(clk), + .CE(\DET_HSYNC.hsync_count[0]_i_2_n_0 ), + .D(\DET_HSYNC.hsync_count_reg[0]_i_3_n_4 ), + .Q(\DET_HSYNC.hsync_count_reg [3]), + .R(\DET_HSYNC.hsync_count[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DET_HSYNC.hsync_count_reg[4] + (.C(clk), + .CE(\DET_HSYNC.hsync_count[0]_i_2_n_0 ), + .D(\DET_HSYNC.hsync_count_reg[4]_i_1_n_7 ), + .Q(\DET_HSYNC.hsync_count_reg [4]), + .R(\DET_HSYNC.hsync_count[0]_i_1_n_0 )); + CARRY4 \DET_HSYNC.hsync_count_reg[4]_i_1 + (.CI(\DET_HSYNC.hsync_count_reg[0]_i_3_n_0 ), + .CO({\DET_HSYNC.hsync_count_reg[4]_i_1_n_0 ,\DET_HSYNC.hsync_count_reg[4]_i_1_n_1 ,\DET_HSYNC.hsync_count_reg[4]_i_1_n_2 ,\DET_HSYNC.hsync_count_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\DET_HSYNC.hsync_count_reg[4]_i_1_n_4 ,\DET_HSYNC.hsync_count_reg[4]_i_1_n_5 ,\DET_HSYNC.hsync_count_reg[4]_i_1_n_6 ,\DET_HSYNC.hsync_count_reg[4]_i_1_n_7 }), + .S({\DET_HSYNC.hsync_count[4]_i_2_n_0 ,\DET_HSYNC.hsync_count[4]_i_3_n_0 ,\DET_HSYNC.hsync_count[4]_i_4_n_0 ,\DET_HSYNC.hsync_count[4]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \DET_HSYNC.hsync_count_reg[5] + (.C(clk), + .CE(\DET_HSYNC.hsync_count[0]_i_2_n_0 ), + .D(\DET_HSYNC.hsync_count_reg[4]_i_1_n_6 ), + .Q(\DET_HSYNC.hsync_count_reg [5]), + .R(\DET_HSYNC.hsync_count[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DET_HSYNC.hsync_count_reg[6] + (.C(clk), + .CE(\DET_HSYNC.hsync_count[0]_i_2_n_0 ), + .D(\DET_HSYNC.hsync_count_reg[4]_i_1_n_5 ), + .Q(\DET_HSYNC.hsync_count_reg [6]), + .R(\DET_HSYNC.hsync_count[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DET_HSYNC.hsync_count_reg[7] + (.C(clk), + .CE(\DET_HSYNC.hsync_count[0]_i_2_n_0 ), + .D(\DET_HSYNC.hsync_count_reg[4]_i_1_n_4 ), + .Q(\DET_HSYNC.hsync_count_reg [7]), + .R(\DET_HSYNC.hsync_count[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DET_HSYNC.hsync_count_reg[8] + (.C(clk), + .CE(\DET_HSYNC.hsync_count[0]_i_2_n_0 ), + .D(\DET_HSYNC.hsync_count_reg[8]_i_1_n_7 ), + .Q(\DET_HSYNC.hsync_count_reg [8]), + .R(\DET_HSYNC.hsync_count[0]_i_1_n_0 )); + CARRY4 \DET_HSYNC.hsync_count_reg[8]_i_1 + (.CI(\DET_HSYNC.hsync_count_reg[4]_i_1_n_0 ), + .CO({\NLW_DET_HSYNC.hsync_count_reg[8]_i_1_CO_UNCONNECTED [3],\DET_HSYNC.hsync_count_reg[8]_i_1_n_1 ,\DET_HSYNC.hsync_count_reg[8]_i_1_n_2 ,\DET_HSYNC.hsync_count_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\DET_HSYNC.hsync_count_reg[8]_i_1_n_4 ,\DET_HSYNC.hsync_count_reg[8]_i_1_n_5 ,\DET_HSYNC.hsync_count_reg[8]_i_1_n_6 ,\DET_HSYNC.hsync_count_reg[8]_i_1_n_7 }), + .S({\DET_HSYNC.hsync_count[8]_i_2_n_0 ,\DET_HSYNC.hsync_count[8]_i_3_n_0 ,\DET_HSYNC.hsync_count[8]_i_4_n_0 ,\DET_HSYNC.hsync_count[8]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \DET_HSYNC.hsync_count_reg[9] + (.C(clk), + .CE(\DET_HSYNC.hsync_count[0]_i_2_n_0 ), + .D(\DET_HSYNC.hsync_count_reg[8]_i_1_n_6 ), + .Q(\DET_HSYNC.hsync_count_reg [9]), + .R(\DET_HSYNC.hsync_count[0]_i_1_n_0 )); + FDRE \DET_HSYNC.hsync_d2_reg + (.C(clk), + .CE(det_ce), + .D(hsync_d), + .Q(hsync_d2), + .R(h_count1)); + LUT4 #( + .INIT(16'hF5F7)) + \DET_HSYNC.hsync_d_i_1 + (.I0(resetn_out), + .I1(\genr_control_regs[0] [1]), + .I2(core_d_out), + .I3(\genr_control_regs[0] [0]), + .O(h_count1)); + LUT2 #( + .INIT(4'h8)) + \DET_HSYNC.hsync_d_i_2 + (.I0(clken), + .I1(det_clken), + .O(det_ce)); + (* SOFT_HLUTNM = "soft_lutpair291" *) + LUT2 #( + .INIT(4'h9)) + \DET_HSYNC.hsync_d_i_3 + (.I0(hsync_in), + .I1(\time_status_regs[3] [1]), + .O(line_end)); + FDRE \DET_HSYNC.hsync_d_reg + (.C(clk), + .CE(det_ce), + .D(line_end), + .Q(hsync_d), + .R(h_count1)); + LUT6 #( + .INIT(64'hEFFEFFFF20020000)) + \DET_VACTIVE.active_line_d_i_1 + (.I0(active_line), + .I1(line_end_d_reg_n_0), + .I2(hsync_in), + .I3(\time_status_regs[3] [1]), + .I4(det_ce), + .I5(active_line_d), + .O(\DET_VACTIVE.active_line_d_i_1_n_0 )); + FDRE \DET_VACTIVE.active_line_d_reg + (.C(clk), + .CE(1'b1), + .D(\DET_VACTIVE.active_line_d_i_1_n_0 ), + .Q(active_line_d), + .R(h_count1)); + LUT5 #( + .INIT(32'h77F700C0)) + \DET_VACTIVE.active_line_i_1 + (.I0(line_end_d_reg_n_0), + .I1(det_ce), + .I2(active_video_d), + .I3(active_video_d2), + .I4(active_line), + .O(\DET_VACTIVE.active_line_i_1_n_0 )); + FDRE \DET_VACTIVE.active_line_reg + (.C(clk), + .CE(1'b1), + .D(\DET_VACTIVE.active_line_i_1_n_0 ), + .Q(active_line), + .R(h_count1)); + LUT6 #( + .INIT(64'h0000000C000A000A)) + \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0_vsync_lock_i_1 + (.I0(det_v0_vsync_lock), + .I1(p_1_in), + .I2(h_count1), + .I3(lost_lock), + .I4(det_v0_vsync_lock__0), + .I5(det_ce), + .O(\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0_vsync_lock_i_1_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0_vsync_lock_i_2 + (.I0(\neqOp_inferred__3/i__carry_n_0 ), + .I1(neqOp0_out), + .I2(\neqOp_inferred__1/i__carry_n_0 ), + .I3(neqOp), + .O(det_v0_vsync_lock__0)); + FDRE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0_vsync_lock_reg + (.C(clk), + .CE(1'b1), + .D(\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0_vsync_lock_i_1_n_0 ), + .Q(det_v0_vsync_lock), + .R(1'b0)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_hori_last_reg[0] + (.C(clk), + .CE(vsync_delay), + .D(det_v0bp_start_hori_int[0]), + .Q(det_v0bp_start_hori_last[0]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_hori_last_reg[10] + (.C(clk), + .CE(vsync_delay), + .D(det_v0bp_start_hori_int[10]), + .Q(det_v0bp_start_hori_last[10]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_hori_last_reg[11] + (.C(clk), + .CE(vsync_delay), + .D(det_v0bp_start_hori_int[11]), + .Q(det_v0bp_start_hori_last[11]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_hori_last_reg[1] + (.C(clk), + .CE(vsync_delay), + .D(det_v0bp_start_hori_int[1]), + .Q(det_v0bp_start_hori_last[1]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_hori_last_reg[2] + (.C(clk), + .CE(vsync_delay), + .D(det_v0bp_start_hori_int[2]), + .Q(det_v0bp_start_hori_last[2]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_hori_last_reg[3] + (.C(clk), + .CE(vsync_delay), + .D(det_v0bp_start_hori_int[3]), + .Q(det_v0bp_start_hori_last[3]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_hori_last_reg[4] + (.C(clk), + .CE(vsync_delay), + .D(det_v0bp_start_hori_int[4]), + .Q(det_v0bp_start_hori_last[4]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_hori_last_reg[5] + (.C(clk), + .CE(vsync_delay), + .D(det_v0bp_start_hori_int[5]), + .Q(det_v0bp_start_hori_last[5]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_hori_last_reg[6] + (.C(clk), + .CE(vsync_delay), + .D(det_v0bp_start_hori_int[6]), + .Q(det_v0bp_start_hori_last[6]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_hori_last_reg[7] + (.C(clk), + .CE(vsync_delay), + .D(det_v0bp_start_hori_int[7]), + .Q(det_v0bp_start_hori_last[7]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_hori_last_reg[8] + (.C(clk), + .CE(vsync_delay), + .D(det_v0bp_start_hori_int[8]), + .Q(det_v0bp_start_hori_last[8]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_hori_last_reg[9] + (.C(clk), + .CE(vsync_delay), + .D(det_v0bp_start_hori_int[9]), + .Q(det_v0bp_start_hori_last[9]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_last_reg[0] + (.C(clk), + .CE(vsync_delay), + .D(det_v0bp_start_int[0]), + .Q(det_v0bp_start_last[0]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_last_reg[10] + (.C(clk), + .CE(vsync_delay), + .D(det_v0bp_start_int[10]), + .Q(det_v0bp_start_last[10]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_last_reg[1] + (.C(clk), + .CE(vsync_delay), + .D(det_v0bp_start_int[1]), + .Q(det_v0bp_start_last[1]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_last_reg[2] + (.C(clk), + .CE(vsync_delay), + .D(det_v0bp_start_int[2]), + .Q(det_v0bp_start_last[2]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_last_reg[3] + (.C(clk), + .CE(vsync_delay), + .D(det_v0bp_start_int[3]), + .Q(det_v0bp_start_last[3]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_last_reg[4] + (.C(clk), + .CE(vsync_delay), + .D(det_v0bp_start_int[4]), + .Q(det_v0bp_start_last[4]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_last_reg[5] + (.C(clk), + .CE(vsync_delay), + .D(det_v0bp_start_int[5]), + .Q(det_v0bp_start_last[5]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_last_reg[6] + (.C(clk), + .CE(vsync_delay), + .D(det_v0bp_start_int[6]), + .Q(det_v0bp_start_last[6]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_last_reg[7] + (.C(clk), + .CE(vsync_delay), + .D(det_v0bp_start_int[7]), + .Q(det_v0bp_start_last[7]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_last_reg[8] + (.C(clk), + .CE(vsync_delay), + .D(det_v0bp_start_int[8]), + .Q(det_v0bp_start_last[8]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_last_reg[9] + (.C(clk), + .CE(vsync_delay), + .D(det_v0bp_start_int[9]), + .Q(det_v0bp_start_last[9]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_hori_last_reg[0] + (.C(clk), + .CE(\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0 ), + .D(det_v0sync_start_hori_int[0]), + .Q(det_v0sync_start_hori_last[0]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_hori_last_reg[10] + (.C(clk), + .CE(\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0 ), + .D(det_v0sync_start_hori_int[10]), + .Q(det_v0sync_start_hori_last[10]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_hori_last_reg[11] + (.C(clk), + .CE(\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0 ), + .D(det_v0sync_start_hori_int[11]), + .Q(det_v0sync_start_hori_last[11]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_hori_last_reg[1] + (.C(clk), + .CE(\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0 ), + .D(det_v0sync_start_hori_int[1]), + .Q(det_v0sync_start_hori_last[1]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_hori_last_reg[2] + (.C(clk), + .CE(\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0 ), + .D(det_v0sync_start_hori_int[2]), + .Q(det_v0sync_start_hori_last[2]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_hori_last_reg[3] + (.C(clk), + .CE(\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0 ), + .D(det_v0sync_start_hori_int[3]), + .Q(det_v0sync_start_hori_last[3]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_hori_last_reg[4] + (.C(clk), + .CE(\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0 ), + .D(det_v0sync_start_hori_int[4]), + .Q(det_v0sync_start_hori_last[4]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_hori_last_reg[5] + (.C(clk), + .CE(\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0 ), + .D(det_v0sync_start_hori_int[5]), + .Q(det_v0sync_start_hori_last[5]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_hori_last_reg[6] + (.C(clk), + .CE(\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0 ), + .D(det_v0sync_start_hori_int[6]), + .Q(det_v0sync_start_hori_last[6]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_hori_last_reg[7] + (.C(clk), + .CE(\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0 ), + .D(det_v0sync_start_hori_int[7]), + .Q(det_v0sync_start_hori_last[7]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_hori_last_reg[8] + (.C(clk), + .CE(\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0 ), + .D(det_v0sync_start_hori_int[8]), + .Q(det_v0sync_start_hori_last[8]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_hori_last_reg[9] + (.C(clk), + .CE(\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0 ), + .D(det_v0sync_start_hori_int[9]), + .Q(det_v0sync_start_hori_last[9]), + .S(p_5_out)); + LUT3 #( + .INIT(8'h40)) + \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1 + (.I0(\DET_VSYNC.vsync_d2_reg_n_0 ), + .I1(\DET_VSYNC.vsync_d_reg_n_0 ), + .I2(det_ce), + .O(\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0 )); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last_reg[0] + (.C(clk), + .CE(\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0 ), + .D(det_v0sync_start_int[0]), + .Q(det_v0sync_start_last[0]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last_reg[10] + (.C(clk), + .CE(\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0 ), + .D(det_v0sync_start_int[10]), + .Q(det_v0sync_start_last[10]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last_reg[1] + (.C(clk), + .CE(\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0 ), + .D(det_v0sync_start_int[1]), + .Q(det_v0sync_start_last[1]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last_reg[2] + (.C(clk), + .CE(\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0 ), + .D(det_v0sync_start_int[2]), + .Q(det_v0sync_start_last[2]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last_reg[3] + (.C(clk), + .CE(\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0 ), + .D(det_v0sync_start_int[3]), + .Q(det_v0sync_start_last[3]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last_reg[4] + (.C(clk), + .CE(\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0 ), + .D(det_v0sync_start_int[4]), + .Q(det_v0sync_start_last[4]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last_reg[5] + (.C(clk), + .CE(\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0 ), + .D(det_v0sync_start_int[5]), + .Q(det_v0sync_start_last[5]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last_reg[6] + (.C(clk), + .CE(\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0 ), + .D(det_v0sync_start_int[6]), + .Q(det_v0sync_start_last[6]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last_reg[7] + (.C(clk), + .CE(\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0 ), + .D(det_v0sync_start_int[7]), + .Q(det_v0sync_start_last[7]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last_reg[8] + (.C(clk), + .CE(\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0 ), + .D(det_v0sync_start_int[8]), + .Q(det_v0sync_start_last[8]), + .S(p_5_out)); + FDSE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last_reg[9] + (.C(clk), + .CE(\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0 ), + .D(det_v0sync_start_int[9]), + .Q(det_v0sync_start_last[9]), + .S(p_5_out)); + LUT5 #( + .INIT(32'h000000E2)) + \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_vsync_lock_i_1 + (.I0(vsync_lock_int), + .I1(det_ce), + .I2(det_v0_vsync_lock), + .I3(lost_lock), + .I4(h_count1), + .O(\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_vsync_lock_i_1_n_0 )); + FDRE \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_vsync_lock_reg + (.C(clk), + .CE(1'b1), + .D(\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_vsync_lock_i_1_n_0 ), + .Q(vsync_lock_int), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair287" *) + LUT2 #( + .INIT(4'h2)) + \DET_VSYNC.GEN_DET_VSYNC_LOCK.vsync_delay[0]_i_1 + (.I0(active_video_lock_int), + .I1(det_vsync_pol_change), + .O(\DET_VSYNC.GEN_DET_VSYNC_LOCK.vsync_delay[0]_i_1_n_0 )); + LUT3 #( + .INIT(8'h40)) + \DET_VSYNC.GEN_DET_VSYNC_LOCK.vsync_delay[1]_i_1 + (.I0(\DET_VSYNC.vsync_d_reg_n_0 ), + .I1(\DET_VSYNC.vsync_d2_reg_n_0 ), + .I2(det_ce), + .O(vsync_delay)); + FDRE \DET_VSYNC.GEN_DET_VSYNC_LOCK.vsync_delay_reg[0] + (.C(clk), + .CE(vsync_delay), + .D(\DET_VSYNC.GEN_DET_VSYNC_LOCK.vsync_delay[0]_i_1_n_0 ), + .Q(\DET_VSYNC.GEN_DET_VSYNC_LOCK.vsync_delay_reg_n_0_[0] ), + .R(p_5_out)); + FDRE \DET_VSYNC.GEN_DET_VSYNC_LOCK.vsync_delay_reg[1] + (.C(clk), + .CE(vsync_delay), + .D(\DET_VSYNC.GEN_DET_VSYNC_LOCK.vsync_delay_reg_n_0_[0] ), + .Q(p_1_in), + .R(p_5_out)); + LUT4 #( + .INIT(16'h44C4)) + \DET_VSYNC.det_v0bp_start_hori_int[11]_i_1 + (.I0(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .I1(det_ce), + .I2(\DET_VSYNC.vsync_d2_reg_n_0 ), + .I3(\DET_VSYNC.vsync_d_reg_n_0 ), + .O(det_v0bp_start_int_7)); + FDRE \DET_VSYNC.det_v0bp_start_hori_int_reg[0] + (.C(clk), + .CE(det_v0bp_start_int_7), + .D(\DET_VSYNC.det_v0sync_start_hori_int[0]_i_1_n_0 ), + .Q(det_v0bp_start_hori_int[0]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0bp_start_hori_int_reg[10] + (.C(clk), + .CE(det_v0bp_start_int_7), + .D(\DET_VSYNC.det_v0sync_start_hori_int[10]_i_1_n_0 ), + .Q(det_v0bp_start_hori_int[10]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0bp_start_hori_int_reg[11] + (.C(clk), + .CE(det_v0bp_start_int_7), + .D(\DET_VSYNC.det_v0sync_start_hori_int[11]_i_2_n_0 ), + .Q(det_v0bp_start_hori_int[11]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0bp_start_hori_int_reg[1] + (.C(clk), + .CE(det_v0bp_start_int_7), + .D(\DET_VSYNC.det_v0sync_start_hori_int[1]_i_1_n_0 ), + .Q(det_v0bp_start_hori_int[1]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0bp_start_hori_int_reg[2] + (.C(clk), + .CE(det_v0bp_start_int_7), + .D(\DET_VSYNC.det_v0sync_start_hori_int[2]_i_1_n_0 ), + .Q(det_v0bp_start_hori_int[2]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0bp_start_hori_int_reg[3] + (.C(clk), + .CE(det_v0bp_start_int_7), + .D(\DET_VSYNC.det_v0sync_start_hori_int[3]_i_1_n_0 ), + .Q(det_v0bp_start_hori_int[3]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0bp_start_hori_int_reg[4] + (.C(clk), + .CE(det_v0bp_start_int_7), + .D(\DET_VSYNC.det_v0sync_start_hori_int[4]_i_1_n_0 ), + .Q(det_v0bp_start_hori_int[4]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0bp_start_hori_int_reg[5] + (.C(clk), + .CE(det_v0bp_start_int_7), + .D(\DET_VSYNC.det_v0sync_start_hori_int[5]_i_1_n_0 ), + .Q(det_v0bp_start_hori_int[5]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0bp_start_hori_int_reg[6] + (.C(clk), + .CE(det_v0bp_start_int_7), + .D(\DET_VSYNC.det_v0sync_start_hori_int[6]_i_1_n_0 ), + .Q(det_v0bp_start_hori_int[6]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0bp_start_hori_int_reg[7] + (.C(clk), + .CE(det_v0bp_start_int_7), + .D(\DET_VSYNC.det_v0sync_start_hori_int[7]_i_1_n_0 ), + .Q(det_v0bp_start_hori_int[7]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0bp_start_hori_int_reg[8] + (.C(clk), + .CE(det_v0bp_start_int_7), + .D(\DET_VSYNC.det_v0sync_start_hori_int[8]_i_1_n_0 ), + .Q(det_v0bp_start_hori_int[8]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0bp_start_hori_int_reg[9] + (.C(clk), + .CE(det_v0bp_start_int_7), + .D(\DET_VSYNC.det_v0sync_start_hori_int[9]_i_1_n_0 ), + .Q(det_v0bp_start_hori_int[9]), + .R(h_count1)); + (* SOFT_HLUTNM = "soft_lutpair297" *) + LUT3 #( + .INIT(8'hB8)) + \DET_VSYNC.det_v0bp_start_int[0]_i_1 + (.I0(v_count_reg__0[0]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .I2(det_v0active_start_int[0]), + .O(\DET_VSYNC.det_v0bp_start_int[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair305" *) + LUT3 #( + .INIT(8'hB8)) + \DET_VSYNC.det_v0bp_start_int[10]_i_1 + (.I0(v_count_reg__0[10]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .I2(det_v0active_start_int[10]), + .O(\DET_VSYNC.det_v0bp_start_int[10]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair309" *) + LUT3 #( + .INIT(8'hB8)) + \DET_VSYNC.det_v0bp_start_int[1]_i_1 + (.I0(v_count_reg__0[1]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .I2(det_v0active_start_int[1]), + .O(\DET_VSYNC.det_v0bp_start_int[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair309" *) + LUT3 #( + .INIT(8'hB8)) + \DET_VSYNC.det_v0bp_start_int[2]_i_1 + (.I0(v_count_reg__0[2]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .I2(det_v0active_start_int[2]), + .O(\DET_VSYNC.det_v0bp_start_int[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair301" *) + LUT3 #( + .INIT(8'hB8)) + \DET_VSYNC.det_v0bp_start_int[3]_i_1 + (.I0(v_count_reg__0[3]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .I2(det_v0active_start_int[3]), + .O(\DET_VSYNC.det_v0bp_start_int[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair302" *) + LUT3 #( + .INIT(8'hB8)) + \DET_VSYNC.det_v0bp_start_int[4]_i_1 + (.I0(v_count_reg__0[4]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .I2(det_v0active_start_int[4]), + .O(\DET_VSYNC.det_v0bp_start_int[4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair303" *) + LUT3 #( + .INIT(8'hB8)) + \DET_VSYNC.det_v0bp_start_int[5]_i_1 + (.I0(v_count_reg__0[5]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .I2(det_v0active_start_int[5]), + .O(\DET_VSYNC.det_v0bp_start_int[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair304" *) + LUT3 #( + .INIT(8'hB8)) + \DET_VSYNC.det_v0bp_start_int[6]_i_1 + (.I0(v_count_reg__0[6]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .I2(det_v0active_start_int[6]), + .O(\DET_VSYNC.det_v0bp_start_int[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair305" *) + LUT3 #( + .INIT(8'hB8)) + \DET_VSYNC.det_v0bp_start_int[7]_i_1 + (.I0(v_count_reg__0[7]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .I2(det_v0active_start_int[7]), + .O(\DET_VSYNC.det_v0bp_start_int[7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair306" *) + LUT3 #( + .INIT(8'hB8)) + \DET_VSYNC.det_v0bp_start_int[8]_i_1 + (.I0(v_count_reg__0[8]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .I2(det_v0active_start_int[8]), + .O(\DET_VSYNC.det_v0bp_start_int[8]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair306" *) + LUT3 #( + .INIT(8'hB8)) + \DET_VSYNC.det_v0bp_start_int[9]_i_1 + (.I0(v_count_reg__0[9]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .I2(det_v0active_start_int[9]), + .O(\DET_VSYNC.det_v0bp_start_int[9]_i_1_n_0 )); + FDRE \DET_VSYNC.det_v0bp_start_int_reg[0] + (.C(clk), + .CE(det_v0bp_start_int_7), + .D(\DET_VSYNC.det_v0bp_start_int[0]_i_1_n_0 ), + .Q(det_v0bp_start_int[0]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0bp_start_int_reg[10] + (.C(clk), + .CE(det_v0bp_start_int_7), + .D(\DET_VSYNC.det_v0bp_start_int[10]_i_1_n_0 ), + .Q(det_v0bp_start_int[10]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0bp_start_int_reg[1] + (.C(clk), + .CE(det_v0bp_start_int_7), + .D(\DET_VSYNC.det_v0bp_start_int[1]_i_1_n_0 ), + .Q(det_v0bp_start_int[1]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0bp_start_int_reg[2] + (.C(clk), + .CE(det_v0bp_start_int_7), + .D(\DET_VSYNC.det_v0bp_start_int[2]_i_1_n_0 ), + .Q(det_v0bp_start_int[2]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0bp_start_int_reg[3] + (.C(clk), + .CE(det_v0bp_start_int_7), + .D(\DET_VSYNC.det_v0bp_start_int[3]_i_1_n_0 ), + .Q(det_v0bp_start_int[3]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0bp_start_int_reg[4] + (.C(clk), + .CE(det_v0bp_start_int_7), + .D(\DET_VSYNC.det_v0bp_start_int[4]_i_1_n_0 ), + .Q(det_v0bp_start_int[4]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0bp_start_int_reg[5] + (.C(clk), + .CE(det_v0bp_start_int_7), + .D(\DET_VSYNC.det_v0bp_start_int[5]_i_1_n_0 ), + .Q(det_v0bp_start_int[5]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0bp_start_int_reg[6] + (.C(clk), + .CE(det_v0bp_start_int_7), + .D(\DET_VSYNC.det_v0bp_start_int[6]_i_1_n_0 ), + .Q(det_v0bp_start_int[6]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0bp_start_int_reg[7] + (.C(clk), + .CE(det_v0bp_start_int_7), + .D(\DET_VSYNC.det_v0bp_start_int[7]_i_1_n_0 ), + .Q(det_v0bp_start_int[7]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0bp_start_int_reg[8] + (.C(clk), + .CE(det_v0bp_start_int_7), + .D(\DET_VSYNC.det_v0bp_start_int[8]_i_1_n_0 ), + .Q(det_v0bp_start_int[8]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0bp_start_int_reg[9] + (.C(clk), + .CE(det_v0bp_start_int_7), + .D(\DET_VSYNC.det_v0bp_start_int[9]_i_1_n_0 ), + .Q(det_v0bp_start_int[9]), + .R(h_count1)); + (* SOFT_HLUTNM = "soft_lutpair304" *) + LUT2 #( + .INIT(4'h8)) + \DET_VSYNC.det_v0sync_start_hori_int[0]_i_1 + (.I0(L[11]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .O(\DET_VSYNC.det_v0sync_start_hori_int[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair295" *) + LUT2 #( + .INIT(4'h8)) + \DET_VSYNC.det_v0sync_start_hori_int[10]_i_1 + (.I0(L[1]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .O(\DET_VSYNC.det_v0sync_start_hori_int[10]_i_1_n_0 )); + LUT4 #( + .INIT(16'h44C4)) + \DET_VSYNC.det_v0sync_start_hori_int[11]_i_1 + (.I0(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .I1(det_ce), + .I2(\DET_VSYNC.vsync_d_reg_n_0 ), + .I3(\DET_VSYNC.vsync_d2_reg_n_0 ), + .O(det_v0sync_start_int_4)); + (* SOFT_HLUTNM = "soft_lutpair294" *) + LUT2 #( + .INIT(4'h8)) + \DET_VSYNC.det_v0sync_start_hori_int[11]_i_2 + (.I0(L[0]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .O(\DET_VSYNC.det_v0sync_start_hori_int[11]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair303" *) + LUT2 #( + .INIT(4'h8)) + \DET_VSYNC.det_v0sync_start_hori_int[1]_i_1 + (.I0(L[10]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .O(\DET_VSYNC.det_v0sync_start_hori_int[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair302" *) + LUT2 #( + .INIT(4'h8)) + \DET_VSYNC.det_v0sync_start_hori_int[2]_i_1 + (.I0(L[9]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .O(\DET_VSYNC.det_v0sync_start_hori_int[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair301" *) + LUT2 #( + .INIT(4'h8)) + \DET_VSYNC.det_v0sync_start_hori_int[3]_i_1 + (.I0(L[8]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .O(\DET_VSYNC.det_v0sync_start_hori_int[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair300" *) + LUT2 #( + .INIT(4'h8)) + \DET_VSYNC.det_v0sync_start_hori_int[4]_i_1 + (.I0(L[7]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .O(\DET_VSYNC.det_v0sync_start_hori_int[4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair299" *) + LUT2 #( + .INIT(4'h8)) + \DET_VSYNC.det_v0sync_start_hori_int[5]_i_1 + (.I0(L[6]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .O(\DET_VSYNC.det_v0sync_start_hori_int[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair298" *) + LUT2 #( + .INIT(4'h8)) + \DET_VSYNC.det_v0sync_start_hori_int[6]_i_1 + (.I0(L[5]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .O(\DET_VSYNC.det_v0sync_start_hori_int[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair297" *) + LUT2 #( + .INIT(4'h8)) + \DET_VSYNC.det_v0sync_start_hori_int[7]_i_1 + (.I0(L[4]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .O(\DET_VSYNC.det_v0sync_start_hori_int[7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair278" *) + LUT2 #( + .INIT(4'h8)) + \DET_VSYNC.det_v0sync_start_hori_int[8]_i_1 + (.I0(L[3]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .O(\DET_VSYNC.det_v0sync_start_hori_int[8]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair296" *) + LUT2 #( + .INIT(4'h8)) + \DET_VSYNC.det_v0sync_start_hori_int[9]_i_1 + (.I0(L[2]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .O(\DET_VSYNC.det_v0sync_start_hori_int[9]_i_1_n_0 )); + FDRE \DET_VSYNC.det_v0sync_start_hori_int_reg[0] + (.C(clk), + .CE(det_v0sync_start_int_4), + .D(\DET_VSYNC.det_v0sync_start_hori_int[0]_i_1_n_0 ), + .Q(det_v0sync_start_hori_int[0]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0sync_start_hori_int_reg[10] + (.C(clk), + .CE(det_v0sync_start_int_4), + .D(\DET_VSYNC.det_v0sync_start_hori_int[10]_i_1_n_0 ), + .Q(det_v0sync_start_hori_int[10]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0sync_start_hori_int_reg[11] + (.C(clk), + .CE(det_v0sync_start_int_4), + .D(\DET_VSYNC.det_v0sync_start_hori_int[11]_i_2_n_0 ), + .Q(det_v0sync_start_hori_int[11]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0sync_start_hori_int_reg[1] + (.C(clk), + .CE(det_v0sync_start_int_4), + .D(\DET_VSYNC.det_v0sync_start_hori_int[1]_i_1_n_0 ), + .Q(det_v0sync_start_hori_int[1]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0sync_start_hori_int_reg[2] + (.C(clk), + .CE(det_v0sync_start_int_4), + .D(\DET_VSYNC.det_v0sync_start_hori_int[2]_i_1_n_0 ), + .Q(det_v0sync_start_hori_int[2]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0sync_start_hori_int_reg[3] + (.C(clk), + .CE(det_v0sync_start_int_4), + .D(\DET_VSYNC.det_v0sync_start_hori_int[3]_i_1_n_0 ), + .Q(det_v0sync_start_hori_int[3]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0sync_start_hori_int_reg[4] + (.C(clk), + .CE(det_v0sync_start_int_4), + .D(\DET_VSYNC.det_v0sync_start_hori_int[4]_i_1_n_0 ), + .Q(det_v0sync_start_hori_int[4]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0sync_start_hori_int_reg[5] + (.C(clk), + .CE(det_v0sync_start_int_4), + .D(\DET_VSYNC.det_v0sync_start_hori_int[5]_i_1_n_0 ), + .Q(det_v0sync_start_hori_int[5]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0sync_start_hori_int_reg[6] + (.C(clk), + .CE(det_v0sync_start_int_4), + .D(\DET_VSYNC.det_v0sync_start_hori_int[6]_i_1_n_0 ), + .Q(det_v0sync_start_hori_int[6]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0sync_start_hori_int_reg[7] + (.C(clk), + .CE(det_v0sync_start_int_4), + .D(\DET_VSYNC.det_v0sync_start_hori_int[7]_i_1_n_0 ), + .Q(det_v0sync_start_hori_int[7]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0sync_start_hori_int_reg[8] + (.C(clk), + .CE(det_v0sync_start_int_4), + .D(\DET_VSYNC.det_v0sync_start_hori_int[8]_i_1_n_0 ), + .Q(det_v0sync_start_hori_int[8]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0sync_start_hori_int_reg[9] + (.C(clk), + .CE(det_v0sync_start_int_4), + .D(\DET_VSYNC.det_v0sync_start_hori_int[9]_i_1_n_0 ), + .Q(det_v0sync_start_hori_int[9]), + .R(h_count1)); + (* SOFT_HLUTNM = "soft_lutpair307" *) + LUT3 #( + .INIT(8'hB8)) + \DET_VSYNC.det_v0sync_start_int[0]_i_1 + (.I0(v_count_reg__0[0]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .I2(\time_status_regs_int_reg[0] [0]), + .O(\DET_VSYNC.det_v0sync_start_int[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair307" *) + LUT3 #( + .INIT(8'hB8)) + \DET_VSYNC.det_v0sync_start_int[10]_i_1 + (.I0(v_count_reg__0[10]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .I2(\time_status_regs_int_reg[0] [10]), + .O(\DET_VSYNC.det_v0sync_start_int[10]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair308" *) + LUT3 #( + .INIT(8'hB8)) + \DET_VSYNC.det_v0sync_start_int[1]_i_1 + (.I0(v_count_reg__0[1]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .I2(\time_status_regs_int_reg[0] [1]), + .O(\DET_VSYNC.det_v0sync_start_int[1]_i_1_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \DET_VSYNC.det_v0sync_start_int[2]_i_1 + (.I0(v_count_reg__0[2]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .I2(\time_status_regs_int_reg[0] [2]), + .O(\DET_VSYNC.det_v0sync_start_int[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair295" *) + LUT3 #( + .INIT(8'hB8)) + \DET_VSYNC.det_v0sync_start_int[3]_i_1 + (.I0(v_count_reg__0[3]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .I2(\time_status_regs_int_reg[0] [3]), + .O(\DET_VSYNC.det_v0sync_start_int[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair294" *) + LUT3 #( + .INIT(8'hB8)) + \DET_VSYNC.det_v0sync_start_int[4]_i_1 + (.I0(v_count_reg__0[4]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .I2(\time_status_regs_int_reg[0] [4]), + .O(\DET_VSYNC.det_v0sync_start_int[4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair308" *) + LUT3 #( + .INIT(8'hB8)) + \DET_VSYNC.det_v0sync_start_int[5]_i_1 + (.I0(v_count_reg__0[5]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .I2(\time_status_regs_int_reg[0] [5]), + .O(\DET_VSYNC.det_v0sync_start_int[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair300" *) + LUT3 #( + .INIT(8'hB8)) + \DET_VSYNC.det_v0sync_start_int[6]_i_1 + (.I0(v_count_reg__0[6]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .I2(\time_status_regs_int_reg[0] [6]), + .O(\DET_VSYNC.det_v0sync_start_int[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair299" *) + LUT3 #( + .INIT(8'hB8)) + \DET_VSYNC.det_v0sync_start_int[7]_i_1 + (.I0(v_count_reg__0[7]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .I2(\time_status_regs_int_reg[0] [7]), + .O(\DET_VSYNC.det_v0sync_start_int[7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair298" *) + LUT3 #( + .INIT(8'hB8)) + \DET_VSYNC.det_v0sync_start_int[8]_i_1 + (.I0(v_count_reg__0[8]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .I2(\time_status_regs_int_reg[0] [8]), + .O(\DET_VSYNC.det_v0sync_start_int[8]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair296" *) + LUT3 #( + .INIT(8'hB8)) + \DET_VSYNC.det_v0sync_start_int[9]_i_1 + (.I0(v_count_reg__0[9]), + .I1(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .I2(\time_status_regs_int_reg[0] [9]), + .O(\DET_VSYNC.det_v0sync_start_int[9]_i_1_n_0 )); + FDRE \DET_VSYNC.det_v0sync_start_int_reg[0] + (.C(clk), + .CE(det_v0sync_start_int_4), + .D(\DET_VSYNC.det_v0sync_start_int[0]_i_1_n_0 ), + .Q(det_v0sync_start_int[0]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0sync_start_int_reg[10] + (.C(clk), + .CE(det_v0sync_start_int_4), + .D(\DET_VSYNC.det_v0sync_start_int[10]_i_1_n_0 ), + .Q(det_v0sync_start_int[10]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0sync_start_int_reg[1] + (.C(clk), + .CE(det_v0sync_start_int_4), + .D(\DET_VSYNC.det_v0sync_start_int[1]_i_1_n_0 ), + .Q(det_v0sync_start_int[1]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0sync_start_int_reg[2] + (.C(clk), + .CE(det_v0sync_start_int_4), + .D(\DET_VSYNC.det_v0sync_start_int[2]_i_1_n_0 ), + .Q(det_v0sync_start_int[2]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0sync_start_int_reg[3] + (.C(clk), + .CE(det_v0sync_start_int_4), + .D(\DET_VSYNC.det_v0sync_start_int[3]_i_1_n_0 ), + .Q(det_v0sync_start_int[3]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0sync_start_int_reg[4] + (.C(clk), + .CE(det_v0sync_start_int_4), + .D(\DET_VSYNC.det_v0sync_start_int[4]_i_1_n_0 ), + .Q(det_v0sync_start_int[4]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0sync_start_int_reg[5] + (.C(clk), + .CE(det_v0sync_start_int_4), + .D(\DET_VSYNC.det_v0sync_start_int[5]_i_1_n_0 ), + .Q(det_v0sync_start_int[5]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0sync_start_int_reg[6] + (.C(clk), + .CE(det_v0sync_start_int_4), + .D(\DET_VSYNC.det_v0sync_start_int[6]_i_1_n_0 ), + .Q(det_v0sync_start_int[6]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0sync_start_int_reg[7] + (.C(clk), + .CE(det_v0sync_start_int_4), + .D(\DET_VSYNC.det_v0sync_start_int[7]_i_1_n_0 ), + .Q(det_v0sync_start_int[7]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0sync_start_int_reg[8] + (.C(clk), + .CE(det_v0sync_start_int_4), + .D(\DET_VSYNC.det_v0sync_start_int[8]_i_1_n_0 ), + .Q(det_v0sync_start_int[8]), + .R(h_count1)); + FDRE \DET_VSYNC.det_v0sync_start_int_reg[9] + (.C(clk), + .CE(det_v0sync_start_int_4), + .D(\DET_VSYNC.det_v0sync_start_int[9]_i_1_n_0 ), + .Q(det_v0sync_start_int[9]), + .R(h_count1)); + LUT3 #( + .INIT(8'hE0)) + \DET_VSYNC.det_vsync_pol_change_i_1 + (.I0(\DET_VSYNC.det_vsync_pol_change_i_2_n_0 ), + .I1(det_v0total_int[10]), + .I2(gtOp29_in), + .O(p_30_out)); + LUT6 #( + .INIT(64'hFFFFFFFEFFFEFFFE)) + \DET_VSYNC.det_vsync_pol_change_i_2 + (.I0(\DET_VSYNC.det_vsync_pol_change_i_3_n_0 ), + .I1(det_v0total_int[8]), + .I2(det_v0total_int[7]), + .I3(det_v0total_int[9]), + .I4(det_v0total_int[6]), + .I5(det_v0total_int[5]), + .O(\DET_VSYNC.det_vsync_pol_change_i_2_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAAAAAAAAAA8)) + \DET_VSYNC.det_vsync_pol_change_i_3 + (.I0(det_v0total_int[6]), + .I1(det_v0total_int[3]), + .I2(det_v0total_int[2]), + .I3(det_v0total_int[1]), + .I4(det_v0total_int[0]), + .I5(det_v0total_int[4]), + .O(\DET_VSYNC.det_vsync_pol_change_i_3_n_0 )); + FDRE \DET_VSYNC.det_vsync_pol_change_reg + (.C(clk), + .CE(det_ce), + .D(p_30_out), + .Q(det_vsync_pol_change), + .R(h_count1)); + LUT5 #( + .INIT(32'hDFFF2000)) + \DET_VSYNC.det_vsync_pol_int_i_1 + (.I0(det_vsync_pol_change), + .I1(\DET_VSYNC.vsync_d_reg_n_0 ), + .I2(\DET_VSYNC.vsync_d2_reg_n_0 ), + .I3(det_ce), + .I4(\time_status_regs[3] [0]), + .O(\DET_VSYNC.det_vsync_pol_int_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \DET_VSYNC.det_vsync_pol_int_reg + (.C(clk), + .CE(1'b1), + .D(\DET_VSYNC.det_vsync_pol_int_i_1_n_0 ), + .Q(\time_status_regs[3] [0]), + .S(h_count1)); + LUT1 #( + .INIT(2'h1)) + \DET_VSYNC.vsync_count[0]_i_1 + (.I0(\DET_VSYNC.vsync_count_reg__0 [0]), + .O(plusOp__1[0])); + LUT4 #( + .INIT(16'hFF08)) + \DET_VSYNC.vsync_count[10]_i_1 + (.I0(det_ce), + .I1(\DET_VSYNC.vsync_d_reg_n_0 ), + .I2(\DET_VSYNC.vsync_d2_reg_n_0 ), + .I3(h_count1), + .O(\DET_VSYNC.vsync_count[10]_i_1_n_0 )); + LUT5 #( + .INIT(32'h00820000)) + \DET_VSYNC.vsync_count[10]_i_2 + (.I0(\DET_VSYNC.vsync_d_reg_n_0 ), + .I1(\time_status_regs[3] [1]), + .I2(hsync_in), + .I3(line_end_d_reg_n_0), + .I4(det_ce), + .O(vsync_count)); + LUT6 #( + .INIT(64'h7FFFFFFF80000000)) + \DET_VSYNC.vsync_count[10]_i_3 + (.I0(\DET_VSYNC.vsync_count_reg__0 [8]), + .I1(\DET_VSYNC.vsync_count_reg__0 [6]), + .I2(\DET_VSYNC.vsync_count[10]_i_4_n_0 ), + .I3(\DET_VSYNC.vsync_count_reg__0 [7]), + .I4(\DET_VSYNC.vsync_count_reg__0 [9]), + .I5(\DET_VSYNC.vsync_count_reg__0 [10]), + .O(plusOp__1[10])); + LUT6 #( + .INIT(64'h8000000000000000)) + \DET_VSYNC.vsync_count[10]_i_4 + (.I0(\DET_VSYNC.vsync_count_reg__0 [5]), + .I1(\DET_VSYNC.vsync_count_reg__0 [3]), + .I2(\DET_VSYNC.vsync_count_reg__0 [1]), + .I3(\DET_VSYNC.vsync_count_reg__0 [0]), + .I4(\DET_VSYNC.vsync_count_reg__0 [2]), + .I5(\DET_VSYNC.vsync_count_reg__0 [4]), + .O(\DET_VSYNC.vsync_count[10]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair290" *) + LUT2 #( + .INIT(4'h6)) + \DET_VSYNC.vsync_count[1]_i_1 + (.I0(\DET_VSYNC.vsync_count_reg__0 [0]), + .I1(\DET_VSYNC.vsync_count_reg__0 [1]), + .O(plusOp__1[1])); + (* SOFT_HLUTNM = "soft_lutpair290" *) + LUT3 #( + .INIT(8'h78)) + \DET_VSYNC.vsync_count[2]_i_1 + (.I0(\DET_VSYNC.vsync_count_reg__0 [0]), + .I1(\DET_VSYNC.vsync_count_reg__0 [1]), + .I2(\DET_VSYNC.vsync_count_reg__0 [2]), + .O(plusOp__1[2])); + (* SOFT_HLUTNM = "soft_lutpair273" *) + LUT4 #( + .INIT(16'h7F80)) + \DET_VSYNC.vsync_count[3]_i_1 + (.I0(\DET_VSYNC.vsync_count_reg__0 [1]), + .I1(\DET_VSYNC.vsync_count_reg__0 [0]), + .I2(\DET_VSYNC.vsync_count_reg__0 [2]), + .I3(\DET_VSYNC.vsync_count_reg__0 [3]), + .O(plusOp__1[3])); + (* SOFT_HLUTNM = "soft_lutpair273" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \DET_VSYNC.vsync_count[4]_i_1 + (.I0(\DET_VSYNC.vsync_count_reg__0 [2]), + .I1(\DET_VSYNC.vsync_count_reg__0 [0]), + .I2(\DET_VSYNC.vsync_count_reg__0 [1]), + .I3(\DET_VSYNC.vsync_count_reg__0 [3]), + .I4(\DET_VSYNC.vsync_count_reg__0 [4]), + .O(plusOp__1[4])); + LUT6 #( + .INIT(64'h7FFFFFFF80000000)) + \DET_VSYNC.vsync_count[5]_i_1 + (.I0(\DET_VSYNC.vsync_count_reg__0 [3]), + .I1(\DET_VSYNC.vsync_count_reg__0 [1]), + .I2(\DET_VSYNC.vsync_count_reg__0 [0]), + .I3(\DET_VSYNC.vsync_count_reg__0 [2]), + .I4(\DET_VSYNC.vsync_count_reg__0 [4]), + .I5(\DET_VSYNC.vsync_count_reg__0 [5]), + .O(plusOp__1[5])); + (* SOFT_HLUTNM = "soft_lutpair280" *) + LUT2 #( + .INIT(4'h6)) + \DET_VSYNC.vsync_count[6]_i_1 + (.I0(\DET_VSYNC.vsync_count[10]_i_4_n_0 ), + .I1(\DET_VSYNC.vsync_count_reg__0 [6]), + .O(plusOp__1[6])); + (* SOFT_HLUTNM = "soft_lutpair280" *) + LUT3 #( + .INIT(8'h78)) + \DET_VSYNC.vsync_count[7]_i_1 + (.I0(\DET_VSYNC.vsync_count[10]_i_4_n_0 ), + .I1(\DET_VSYNC.vsync_count_reg__0 [6]), + .I2(\DET_VSYNC.vsync_count_reg__0 [7]), + .O(plusOp__1[7])); + (* SOFT_HLUTNM = "soft_lutpair275" *) + LUT4 #( + .INIT(16'h7F80)) + \DET_VSYNC.vsync_count[8]_i_1 + (.I0(\DET_VSYNC.vsync_count_reg__0 [6]), + .I1(\DET_VSYNC.vsync_count[10]_i_4_n_0 ), + .I2(\DET_VSYNC.vsync_count_reg__0 [7]), + .I3(\DET_VSYNC.vsync_count_reg__0 [8]), + .O(plusOp__1[8])); + (* SOFT_HLUTNM = "soft_lutpair275" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \DET_VSYNC.vsync_count[9]_i_1 + (.I0(\DET_VSYNC.vsync_count_reg__0 [7]), + .I1(\DET_VSYNC.vsync_count[10]_i_4_n_0 ), + .I2(\DET_VSYNC.vsync_count_reg__0 [6]), + .I3(\DET_VSYNC.vsync_count_reg__0 [8]), + .I4(\DET_VSYNC.vsync_count_reg__0 [9]), + .O(plusOp__1[9])); + FDRE #( + .INIT(1'b0)) + \DET_VSYNC.vsync_count_reg[0] + (.C(clk), + .CE(vsync_count), + .D(plusOp__1[0]), + .Q(\DET_VSYNC.vsync_count_reg__0 [0]), + .R(\DET_VSYNC.vsync_count[10]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DET_VSYNC.vsync_count_reg[10] + (.C(clk), + .CE(vsync_count), + .D(plusOp__1[10]), + .Q(\DET_VSYNC.vsync_count_reg__0 [10]), + .R(\DET_VSYNC.vsync_count[10]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DET_VSYNC.vsync_count_reg[1] + (.C(clk), + .CE(vsync_count), + .D(plusOp__1[1]), + .Q(\DET_VSYNC.vsync_count_reg__0 [1]), + .R(\DET_VSYNC.vsync_count[10]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DET_VSYNC.vsync_count_reg[2] + (.C(clk), + .CE(vsync_count), + .D(plusOp__1[2]), + .Q(\DET_VSYNC.vsync_count_reg__0 [2]), + .R(\DET_VSYNC.vsync_count[10]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DET_VSYNC.vsync_count_reg[3] + (.C(clk), + .CE(vsync_count), + .D(plusOp__1[3]), + .Q(\DET_VSYNC.vsync_count_reg__0 [3]), + .R(\DET_VSYNC.vsync_count[10]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DET_VSYNC.vsync_count_reg[4] + (.C(clk), + .CE(vsync_count), + .D(plusOp__1[4]), + .Q(\DET_VSYNC.vsync_count_reg__0 [4]), + .R(\DET_VSYNC.vsync_count[10]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DET_VSYNC.vsync_count_reg[5] + (.C(clk), + .CE(vsync_count), + .D(plusOp__1[5]), + .Q(\DET_VSYNC.vsync_count_reg__0 [5]), + .R(\DET_VSYNC.vsync_count[10]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DET_VSYNC.vsync_count_reg[6] + (.C(clk), + .CE(vsync_count), + .D(plusOp__1[6]), + .Q(\DET_VSYNC.vsync_count_reg__0 [6]), + .R(\DET_VSYNC.vsync_count[10]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DET_VSYNC.vsync_count_reg[7] + (.C(clk), + .CE(vsync_count), + .D(plusOp__1[7]), + .Q(\DET_VSYNC.vsync_count_reg__0 [7]), + .R(\DET_VSYNC.vsync_count[10]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DET_VSYNC.vsync_count_reg[8] + (.C(clk), + .CE(vsync_count), + .D(plusOp__1[8]), + .Q(\DET_VSYNC.vsync_count_reg__0 [8]), + .R(\DET_VSYNC.vsync_count[10]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \DET_VSYNC.vsync_count_reg[9] + (.C(clk), + .CE(vsync_count), + .D(plusOp__1[9]), + .Q(\DET_VSYNC.vsync_count_reg__0 [9]), + .R(\DET_VSYNC.vsync_count[10]_i_1_n_0 )); + FDRE \DET_VSYNC.vsync_d2_reg + (.C(clk), + .CE(det_ce), + .D(\DET_VSYNC.vsync_d_reg_n_0 ), + .Q(\DET_VSYNC.vsync_d2_reg_n_0 ), + .R(h_count1)); + LUT2 #( + .INIT(4'h9)) + \DET_VSYNC.vsync_d_i_1 + (.I0(vsync_in), + .I1(\time_status_regs[3] [0]), + .O(\DET_VSYNC.vsync_d_i_1_n_0 )); + FDRE \DET_VSYNC.vsync_d_reg + (.C(clk), + .CE(det_ce), + .D(\DET_VSYNC.vsync_d_i_1_n_0 ), + .Q(\DET_VSYNC.vsync_d_reg_n_0 ), + .R(h_count1)); + (* SOFT_HLUTNM = "soft_lutpair277" *) + LUT4 #( + .INIT(16'hFF08)) + \DET_VSYNC.vsync_rose_i_1 + (.I0(det_ce), + .I1(\DET_VSYNC.vsync_d_reg_n_0 ), + .I2(\DET_VSYNC.vsync_d2_reg_n_0 ), + .I3(vsync_rose), + .O(\DET_VSYNC.vsync_rose_i_1_n_0 )); + FDRE \DET_VSYNC.vsync_rose_reg + (.C(clk), + .CE(1'b1), + .D(\DET_VSYNC.vsync_rose_i_1_n_0 ), + .Q(vsync_rose), + .R(h_count1)); + (* SOFT_HLUTNM = "soft_lutpair277" *) + LUT5 #( + .INIT(32'hEFFF2000)) + \DET_VSYNC.vsync_toggled_i_1 + (.I0(vsync_rose), + .I1(\DET_VSYNC.vsync_d_reg_n_0 ), + .I2(\DET_VSYNC.vsync_d2_reg_n_0 ), + .I3(det_ce), + .I4(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .O(\DET_VSYNC.vsync_toggled_i_1_n_0 )); + FDRE \DET_VSYNC.vsync_toggled_reg + (.C(clk), + .CE(1'b1), + .D(\DET_VSYNC.vsync_toggled_i_1_n_0 ), + .Q(\DET_VSYNC.vsync_toggled_reg_n_0 ), + .R(h_count1)); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \_inferred__11/i__carry + (.CI(1'b0), + .CO({\_inferred__11/i__carry_n_0 ,\_inferred__11/i__carry_n_1 ,\_inferred__11/i__carry_n_2 ,\_inferred__11/i__carry_n_3 }), + .CYINIT(det_v0bp_start_hori_int[0]), + .DI({det_v0bp_start_hori_int[3:1],i__carry_i_1__4_n_0}), + .O(det_v0bp_start_hori_int2[3:0]), + .S({i__carry_i_2__11_n_0,i__carry_i_3__11_n_0,i__carry_i_4__11_n_0,i__carry_i_5__4_n_0})); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \_inferred__11/i__carry__0 + (.CI(\_inferred__11/i__carry_n_0 ), + .CO({\_inferred__11/i__carry__0_n_0 ,\_inferred__11/i__carry__0_n_1 ,\_inferred__11/i__carry__0_n_2 ,\_inferred__11/i__carry__0_n_3 }), + .CYINIT(1'b0), + .DI(det_v0bp_start_hori_int[7:4]), + .O(det_v0bp_start_hori_int2[7:4]), + .S({i__carry__0_i_1__5_n_0,i__carry__0_i_2__5_n_0,i__carry__0_i_3__5_n_0,i__carry__0_i_4__5_n_0})); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \_inferred__11/i__carry__1 + (.CI(\_inferred__11/i__carry__0_n_0 ), + .CO({\NLW__inferred__11/i__carry__1_CO_UNCONNECTED [3],\_inferred__11/i__carry__1_n_1 ,\_inferred__11/i__carry__1_n_2 ,\_inferred__11/i__carry__1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,det_v0bp_start_hori_int[10:8]}), + .O(det_v0bp_start_hori_int2[11:8]), + .S({i__carry__1_i_1__2_n_0,i__carry__1_i_2__1_n_0,i__carry__1_i_3__1_n_0,i__carry__1_i_4__1_n_0})); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \_inferred__8/i__carry + (.CI(1'b0), + .CO({\_inferred__8/i__carry_n_0 ,\_inferred__8/i__carry_n_1 ,\_inferred__8/i__carry_n_2 ,\_inferred__8/i__carry_n_3 }), + .CYINIT(det_v0sync_start_hori_int[0]), + .DI({det_v0sync_start_hori_int[3:1],i__carry_i_1__3_n_0}), + .O(det_v0sync_start_hori_int2[3:0]), + .S({i__carry_i_2__10_n_0,i__carry_i_3__10_n_0,i__carry_i_4__10_n_0,i__carry_i_5__3_n_0})); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \_inferred__8/i__carry__0 + (.CI(\_inferred__8/i__carry_n_0 ), + .CO({\_inferred__8/i__carry__0_n_0 ,\_inferred__8/i__carry__0_n_1 ,\_inferred__8/i__carry__0_n_2 ,\_inferred__8/i__carry__0_n_3 }), + .CYINIT(1'b0), + .DI(det_v0sync_start_hori_int[7:4]), + .O(det_v0sync_start_hori_int2[7:4]), + .S({i__carry__0_i_1__4_n_0,i__carry__0_i_2__4_n_0,i__carry__0_i_3__4_n_0,i__carry__0_i_4__4_n_0})); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \_inferred__8/i__carry__1 + (.CI(\_inferred__8/i__carry__0_n_0 ), + .CO({\NLW__inferred__8/i__carry__1_CO_UNCONNECTED [3],\_inferred__8/i__carry__1_n_1 ,\_inferred__8/i__carry__1_n_2 ,\_inferred__8/i__carry__1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,det_v0sync_start_hori_int[10:8]}), + .O(det_v0sync_start_hori_int2[11:8]), + .S({i__carry__1_i_1__1_n_0,i__carry__1_i_2__0_n_0,i__carry__1_i_3__0_n_0,i__carry__1_i_4__0_n_0})); + LUT6 #( + .INIT(64'h00000000E2222222)) + all_lock_i_1 + (.I0(all_lock), + .I1(det_ce), + .I2(vsync_lock_int), + .I3(hsync_lock_int), + .I4(active_video_lock_int), + .I5(all_lock_d0), + .O(all_lock_reg)); + LUT4 #( + .INIT(16'h0800)) + \det_hactive_start_int[11]_i_1 + (.I0(det_ce), + .I1(active_video_d), + .I2(active_video_d2), + .I3(active_video_toggled), + .O(det_hactive_start_int_3)); + FDRE \det_hactive_start_int_reg[0] + (.C(clk), + .CE(det_hactive_start_int_3), + .D(L[11]), + .Q(det_hactive_start_int[0]), + .R(h_count1)); + FDRE \det_hactive_start_int_reg[10] + (.C(clk), + .CE(det_hactive_start_int_3), + .D(L[1]), + .Q(det_hactive_start_int[10]), + .R(h_count1)); + FDRE \det_hactive_start_int_reg[11] + (.C(clk), + .CE(det_hactive_start_int_3), + .D(L[0]), + .Q(det_hactive_start_int[11]), + .R(h_count1)); + FDRE \det_hactive_start_int_reg[1] + (.C(clk), + .CE(det_hactive_start_int_3), + .D(L[10]), + .Q(det_hactive_start_int[1]), + .R(h_count1)); + FDRE \det_hactive_start_int_reg[2] + (.C(clk), + .CE(det_hactive_start_int_3), + .D(L[9]), + .Q(det_hactive_start_int[2]), + .R(h_count1)); + FDRE \det_hactive_start_int_reg[3] + (.C(clk), + .CE(det_hactive_start_int_3), + .D(L[8]), + .Q(det_hactive_start_int[3]), + .R(h_count1)); + FDRE \det_hactive_start_int_reg[4] + (.C(clk), + .CE(det_hactive_start_int_3), + .D(L[7]), + .Q(det_hactive_start_int[4]), + .R(h_count1)); + FDRE \det_hactive_start_int_reg[5] + (.C(clk), + .CE(det_hactive_start_int_3), + .D(L[6]), + .Q(det_hactive_start_int[5]), + .R(h_count1)); + FDRE \det_hactive_start_int_reg[6] + (.C(clk), + .CE(det_hactive_start_int_3), + .D(L[5]), + .Q(det_hactive_start_int[6]), + .R(h_count1)); + FDRE \det_hactive_start_int_reg[7] + (.C(clk), + .CE(det_hactive_start_int_3), + .D(L[4]), + .Q(det_hactive_start_int[7]), + .R(h_count1)); + FDRE \det_hactive_start_int_reg[8] + (.C(clk), + .CE(det_hactive_start_int_3), + .D(L[3]), + .Q(det_hactive_start_int[8]), + .R(h_count1)); + FDRE \det_hactive_start_int_reg[9] + (.C(clk), + .CE(det_hactive_start_int_3), + .D(L[2]), + .Q(det_hactive_start_int[9]), + .R(h_count1)); + FDRE \det_hbp_start_int2_reg[0] + (.C(clk), + .CE(det_ce), + .D(\plusOp_inferred__2/i__carry_n_7 ), + .Q(\time_status_regs[6] [12]), + .R(reset)); + FDRE \det_hbp_start_int2_reg[10] + (.C(clk), + .CE(det_ce), + .D(\plusOp_inferred__2/i__carry__1_n_5 ), + .Q(\time_status_regs[6] [22]), + .R(reset)); + FDRE \det_hbp_start_int2_reg[11] + (.C(clk), + .CE(det_ce), + .D(\plusOp_inferred__2/i__carry__1_n_4 ), + .Q(\time_status_regs[6] [23]), + .R(reset)); + FDRE \det_hbp_start_int2_reg[1] + (.C(clk), + .CE(det_ce), + .D(\plusOp_inferred__2/i__carry_n_6 ), + .Q(\time_status_regs[6] [13]), + .R(reset)); + FDRE \det_hbp_start_int2_reg[2] + (.C(clk), + .CE(det_ce), + .D(\plusOp_inferred__2/i__carry_n_5 ), + .Q(\time_status_regs[6] [14]), + .R(reset)); + FDRE \det_hbp_start_int2_reg[3] + (.C(clk), + .CE(det_ce), + .D(\plusOp_inferred__2/i__carry_n_4 ), + .Q(\time_status_regs[6] [15]), + .R(reset)); + FDRE \det_hbp_start_int2_reg[4] + (.C(clk), + .CE(det_ce), + .D(\plusOp_inferred__2/i__carry__0_n_7 ), + .Q(\time_status_regs[6] [16]), + .R(reset)); + FDRE \det_hbp_start_int2_reg[5] + (.C(clk), + .CE(det_ce), + .D(\plusOp_inferred__2/i__carry__0_n_6 ), + .Q(\time_status_regs[6] [17]), + .R(reset)); + FDRE \det_hbp_start_int2_reg[6] + (.C(clk), + .CE(det_ce), + .D(\plusOp_inferred__2/i__carry__0_n_5 ), + .Q(\time_status_regs[6] [18]), + .R(reset)); + FDRE \det_hbp_start_int2_reg[7] + (.C(clk), + .CE(det_ce), + .D(\plusOp_inferred__2/i__carry__0_n_4 ), + .Q(\time_status_regs[6] [19]), + .R(reset)); + FDRE \det_hbp_start_int2_reg[8] + (.C(clk), + .CE(det_ce), + .D(\plusOp_inferred__2/i__carry__1_n_7 ), + .Q(\time_status_regs[6] [20]), + .R(reset)); + FDRE \det_hbp_start_int2_reg[9] + (.C(clk), + .CE(det_ce), + .D(\plusOp_inferred__2/i__carry__1_n_6 ), + .Q(\time_status_regs[6] [21]), + .R(reset)); + FDRE \det_hfp_start_int2_reg[0] + (.C(clk), + .CE(det_ce), + .D(minusOp1_out[0]), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [0]), + .R(reset)); + FDRE \det_hfp_start_int2_reg[10] + (.C(clk), + .CE(det_ce), + .D(minusOp1_out[10]), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [10]), + .R(reset)); + FDRE \det_hfp_start_int2_reg[11] + (.C(clk), + .CE(det_ce), + .D(minusOp1_out[11]), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [11]), + .R(reset)); + FDRE \det_hfp_start_int2_reg[1] + (.C(clk), + .CE(det_ce), + .D(minusOp1_out[1]), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [1]), + .R(reset)); + FDRE \det_hfp_start_int2_reg[2] + (.C(clk), + .CE(det_ce), + .D(minusOp1_out[2]), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [2]), + .R(reset)); + FDRE \det_hfp_start_int2_reg[3] + (.C(clk), + .CE(det_ce), + .D(minusOp1_out[3]), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [3]), + .R(reset)); + FDRE \det_hfp_start_int2_reg[4] + (.C(clk), + .CE(det_ce), + .D(minusOp1_out[4]), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [4]), + .R(reset)); + FDRE \det_hfp_start_int2_reg[5] + (.C(clk), + .CE(det_ce), + .D(minusOp1_out[5]), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [5]), + .R(reset)); + FDRE \det_hfp_start_int2_reg[6] + (.C(clk), + .CE(det_ce), + .D(minusOp1_out[6]), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [6]), + .R(reset)); + FDRE \det_hfp_start_int2_reg[7] + (.C(clk), + .CE(det_ce), + .D(minusOp1_out[7]), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [7]), + .R(reset)); + FDRE \det_hfp_start_int2_reg[8] + (.C(clk), + .CE(det_ce), + .D(minusOp1_out[8]), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [8]), + .R(reset)); + FDRE \det_hfp_start_int2_reg[9] + (.C(clk), + .CE(det_ce), + .D(minusOp1_out[9]), + .Q(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [9]), + .R(reset)); + LUT4 #( + .INIT(16'h0800)) + \det_hfp_start_int[11]_i_1 + (.I0(active_video_toggled), + .I1(det_ce), + .I2(active_video_d), + .I3(active_video_d2), + .O(det_hfp_start_int_8)); + FDRE \det_hfp_start_int_reg[0] + (.C(clk), + .CE(det_hfp_start_int_8), + .D(L[11]), + .Q(det_hfp_start_int[0]), + .R(h_count1)); + FDRE \det_hfp_start_int_reg[10] + (.C(clk), + .CE(det_hfp_start_int_8), + .D(L[1]), + .Q(det_hfp_start_int[10]), + .R(h_count1)); + FDRE \det_hfp_start_int_reg[11] + (.C(clk), + .CE(det_hfp_start_int_8), + .D(L[0]), + .Q(det_hfp_start_int[11]), + .R(h_count1)); + FDRE \det_hfp_start_int_reg[1] + (.C(clk), + .CE(det_hfp_start_int_8), + .D(L[10]), + .Q(det_hfp_start_int[1]), + .R(h_count1)); + FDRE \det_hfp_start_int_reg[2] + (.C(clk), + .CE(det_hfp_start_int_8), + .D(L[9]), + .Q(det_hfp_start_int[2]), + .R(h_count1)); + FDRE \det_hfp_start_int_reg[3] + (.C(clk), + .CE(det_hfp_start_int_8), + .D(L[8]), + .Q(det_hfp_start_int[3]), + .R(h_count1)); + FDRE \det_hfp_start_int_reg[4] + (.C(clk), + .CE(det_hfp_start_int_8), + .D(L[7]), + .Q(det_hfp_start_int[4]), + .R(h_count1)); + FDRE \det_hfp_start_int_reg[5] + (.C(clk), + .CE(det_hfp_start_int_8), + .D(L[6]), + .Q(det_hfp_start_int[5]), + .R(h_count1)); + FDRE \det_hfp_start_int_reg[6] + (.C(clk), + .CE(det_hfp_start_int_8), + .D(L[5]), + .Q(det_hfp_start_int[6]), + .R(h_count1)); + FDRE \det_hfp_start_int_reg[7] + (.C(clk), + .CE(det_hfp_start_int_8), + .D(L[4]), + .Q(det_hfp_start_int[7]), + .R(h_count1)); + FDRE \det_hfp_start_int_reg[8] + (.C(clk), + .CE(det_hfp_start_int_8), + .D(L[3]), + .Q(det_hfp_start_int[8]), + .R(h_count1)); + FDRE \det_hfp_start_int_reg[9] + (.C(clk), + .CE(det_hfp_start_int_8), + .D(L[2]), + .Q(det_hfp_start_int[9]), + .R(h_count1)); + FDRE \det_hsync_start_int2_reg[0] + (.C(clk), + .CE(det_ce), + .D(minusOp0_out[0]), + .Q(\time_status_regs[6] [0]), + .R(reset)); + FDRE \det_hsync_start_int2_reg[10] + (.C(clk), + .CE(det_ce), + .D(minusOp0_out[10]), + .Q(\time_status_regs[6] [10]), + .R(reset)); + FDRE \det_hsync_start_int2_reg[11] + (.C(clk), + .CE(det_ce), + .D(minusOp0_out[11]), + .Q(\time_status_regs[6] [11]), + .R(reset)); + FDRE \det_hsync_start_int2_reg[1] + (.C(clk), + .CE(det_ce), + .D(minusOp0_out[1]), + .Q(\time_status_regs[6] [1]), + .R(reset)); + FDRE \det_hsync_start_int2_reg[2] + (.C(clk), + .CE(det_ce), + .D(minusOp0_out[2]), + .Q(\time_status_regs[6] [2]), + .R(reset)); + FDRE \det_hsync_start_int2_reg[3] + (.C(clk), + .CE(det_ce), + .D(minusOp0_out[3]), + .Q(\time_status_regs[6] [3]), + .R(reset)); + FDRE \det_hsync_start_int2_reg[4] + (.C(clk), + .CE(det_ce), + .D(minusOp0_out[4]), + .Q(\time_status_regs[6] [4]), + .R(reset)); + FDRE \det_hsync_start_int2_reg[5] + (.C(clk), + .CE(det_ce), + .D(minusOp0_out[5]), + .Q(\time_status_regs[6] [5]), + .R(reset)); + FDRE \det_hsync_start_int2_reg[6] + (.C(clk), + .CE(det_ce), + .D(minusOp0_out[6]), + .Q(\time_status_regs[6] [6]), + .R(reset)); + FDRE \det_hsync_start_int2_reg[7] + (.C(clk), + .CE(det_ce), + .D(minusOp0_out[7]), + .Q(\time_status_regs[6] [7]), + .R(reset)); + FDRE \det_hsync_start_int2_reg[8] + (.C(clk), + .CE(det_ce), + .D(minusOp0_out[8]), + .Q(\time_status_regs[6] [8]), + .R(reset)); + FDRE \det_hsync_start_int2_reg[9] + (.C(clk), + .CE(det_ce), + .D(minusOp0_out[9]), + .Q(\time_status_regs[6] [9]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \det_htotal_int2[0]_i_1 + (.I0(det_htotal_int[0]), + .O(plusOp[0])); + LUT1 #( + .INIT(2'h2)) + \det_htotal_int2[11]_i_2 + (.I0(det_htotal_int[11]), + .O(\det_htotal_int2[11]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \det_htotal_int2[11]_i_3 + (.I0(det_htotal_int[10]), + .O(\det_htotal_int2[11]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \det_htotal_int2[11]_i_4 + (.I0(det_htotal_int[9]), + .O(\det_htotal_int2[11]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \det_htotal_int2[4]_i_2 + (.I0(det_htotal_int[4]), + .O(\det_htotal_int2[4]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \det_htotal_int2[4]_i_3 + (.I0(det_htotal_int[3]), + .O(\det_htotal_int2[4]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \det_htotal_int2[4]_i_4 + (.I0(det_htotal_int[2]), + .O(\det_htotal_int2[4]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \det_htotal_int2[4]_i_5 + (.I0(det_htotal_int[1]), + .O(\det_htotal_int2[4]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \det_htotal_int2[8]_i_2 + (.I0(det_htotal_int[8]), + .O(\det_htotal_int2[8]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \det_htotal_int2[8]_i_3 + (.I0(det_htotal_int[7]), + .O(\det_htotal_int2[8]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \det_htotal_int2[8]_i_4 + (.I0(det_htotal_int[6]), + .O(\det_htotal_int2[8]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \det_htotal_int2[8]_i_5 + (.I0(det_htotal_int[5]), + .O(\det_htotal_int2[8]_i_5_n_0 )); + FDRE \det_htotal_int2_reg[0] + (.C(clk), + .CE(det_ce), + .D(plusOp[0]), + .Q(Q[0]), + .R(reset)); + FDRE \det_htotal_int2_reg[10] + (.C(clk), + .CE(det_ce), + .D(plusOp[10]), + .Q(Q[10]), + .R(reset)); + FDRE \det_htotal_int2_reg[11] + (.C(clk), + .CE(det_ce), + .D(plusOp[11]), + .Q(Q[11]), + .R(reset)); + CARRY4 \det_htotal_int2_reg[11]_i_1 + (.CI(\det_htotal_int2_reg[8]_i_1_n_0 ), + .CO({\NLW_det_htotal_int2_reg[11]_i_1_CO_UNCONNECTED [3:2],\det_htotal_int2_reg[11]_i_1_n_2 ,\det_htotal_int2_reg[11]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_det_htotal_int2_reg[11]_i_1_O_UNCONNECTED [3],plusOp[11:9]}), + .S({1'b0,\det_htotal_int2[11]_i_2_n_0 ,\det_htotal_int2[11]_i_3_n_0 ,\det_htotal_int2[11]_i_4_n_0 })); + FDRE \det_htotal_int2_reg[1] + (.C(clk), + .CE(det_ce), + .D(plusOp[1]), + .Q(Q[1]), + .R(reset)); + FDRE \det_htotal_int2_reg[2] + (.C(clk), + .CE(det_ce), + .D(plusOp[2]), + .Q(Q[2]), + .R(reset)); + FDRE \det_htotal_int2_reg[3] + (.C(clk), + .CE(det_ce), + .D(plusOp[3]), + .Q(Q[3]), + .R(reset)); + FDRE \det_htotal_int2_reg[4] + (.C(clk), + .CE(det_ce), + .D(plusOp[4]), + .Q(Q[4]), + .R(reset)); + CARRY4 \det_htotal_int2_reg[4]_i_1 + (.CI(1'b0), + .CO({\det_htotal_int2_reg[4]_i_1_n_0 ,\det_htotal_int2_reg[4]_i_1_n_1 ,\det_htotal_int2_reg[4]_i_1_n_2 ,\det_htotal_int2_reg[4]_i_1_n_3 }), + .CYINIT(det_htotal_int[0]), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(plusOp[4:1]), + .S({\det_htotal_int2[4]_i_2_n_0 ,\det_htotal_int2[4]_i_3_n_0 ,\det_htotal_int2[4]_i_4_n_0 ,\det_htotal_int2[4]_i_5_n_0 })); + FDRE \det_htotal_int2_reg[5] + (.C(clk), + .CE(det_ce), + .D(plusOp[5]), + .Q(Q[5]), + .R(reset)); + FDRE \det_htotal_int2_reg[6] + (.C(clk), + .CE(det_ce), + .D(plusOp[6]), + .Q(Q[6]), + .R(reset)); + FDRE \det_htotal_int2_reg[7] + (.C(clk), + .CE(det_ce), + .D(plusOp[7]), + .Q(Q[7]), + .R(reset)); + FDRE \det_htotal_int2_reg[8] + (.C(clk), + .CE(det_ce), + .D(plusOp[8]), + .Q(Q[8]), + .R(reset)); + CARRY4 \det_htotal_int2_reg[8]_i_1 + (.CI(\det_htotal_int2_reg[4]_i_1_n_0 ), + .CO({\det_htotal_int2_reg[8]_i_1_n_0 ,\det_htotal_int2_reg[8]_i_1_n_1 ,\det_htotal_int2_reg[8]_i_1_n_2 ,\det_htotal_int2_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(plusOp[8:5]), + .S({\det_htotal_int2[8]_i_2_n_0 ,\det_htotal_int2[8]_i_3_n_0 ,\det_htotal_int2[8]_i_4_n_0 ,\det_htotal_int2[8]_i_5_n_0 })); + FDRE \det_htotal_int2_reg[9] + (.C(clk), + .CE(det_ce), + .D(plusOp[9]), + .Q(Q[9]), + .R(reset)); + LUT4 #( + .INIT(16'h2002)) + \det_htotal_int[11]_i_1 + (.I0(det_ce), + .I1(line_end_d_reg_n_0), + .I2(hsync_in), + .I3(\time_status_regs[3] [1]), + .O(\det_htotal_int[11]_i_1_n_0 )); + FDRE \det_htotal_int_reg[0] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(L[11]), + .Q(det_htotal_int[0]), + .R(h_count1)); + FDRE \det_htotal_int_reg[10] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(L[1]), + .Q(det_htotal_int[10]), + .R(h_count1)); + FDRE \det_htotal_int_reg[11] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(L[0]), + .Q(det_htotal_int[11]), + .R(h_count1)); + FDRE \det_htotal_int_reg[1] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(L[10]), + .Q(det_htotal_int[1]), + .R(h_count1)); + FDRE \det_htotal_int_reg[2] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(L[9]), + .Q(det_htotal_int[2]), + .R(h_count1)); + FDRE \det_htotal_int_reg[3] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(L[8]), + .Q(det_htotal_int[3]), + .R(h_count1)); + FDRE \det_htotal_int_reg[4] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(L[7]), + .Q(det_htotal_int[4]), + .R(h_count1)); + FDRE \det_htotal_int_reg[5] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(L[6]), + .Q(det_htotal_int[5]), + .R(h_count1)); + FDRE \det_htotal_int_reg[6] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(L[5]), + .Q(det_htotal_int[6]), + .R(h_count1)); + FDRE \det_htotal_int_reg[7] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(L[4]), + .Q(det_htotal_int[7]), + .R(h_count1)); + FDRE \det_htotal_int_reg[8] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(L[3]), + .Q(det_htotal_int[8]), + .R(h_count1)); + FDRE \det_htotal_int_reg[9] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(L[2]), + .Q(det_htotal_int[9]), + .R(h_count1)); + (* SOFT_HLUTNM = "soft_lutpair292" *) + LUT3 #( + .INIT(8'hE2)) + \det_v0active_start_hori_int2[0]_i_1 + (.I0(det_hactive_start_int[0]), + .I1(\det_v0active_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [0]), + .O(\det_v0active_start_hori_int2[0]_i_1_n_0 )); + LUT2 #( + .INIT(4'h1)) + \det_v0active_start_hori_int2[0]_i_10 + (.I0(det_hactive_start_int[9]), + .I1(det_hactive_start_int[8]), + .O(\det_v0active_start_hori_int2[0]_i_10_n_0 )); + LUT2 #( + .INIT(4'h1)) + \det_v0active_start_hori_int2[0]_i_11 + (.I0(det_hactive_start_int[7]), + .I1(det_hactive_start_int[6]), + .O(\det_v0active_start_hori_int2[0]_i_11_n_0 )); + LUT2 #( + .INIT(4'h1)) + \det_v0active_start_hori_int2[0]_i_12 + (.I0(det_hactive_start_int[5]), + .I1(det_hactive_start_int[4]), + .O(\det_v0active_start_hori_int2[0]_i_12_n_0 )); + LUT2 #( + .INIT(4'h1)) + \det_v0active_start_hori_int2[0]_i_13 + (.I0(det_hactive_start_int[3]), + .I1(det_hactive_start_int[2]), + .O(\det_v0active_start_hori_int2[0]_i_13_n_0 )); + LUT2 #( + .INIT(4'hE)) + \det_v0active_start_hori_int2[0]_i_4 + (.I0(det_hactive_start_int[10]), + .I1(det_hactive_start_int[11]), + .O(\det_v0active_start_hori_int2[0]_i_4_n_0 )); + LUT2 #( + .INIT(4'h1)) + \det_v0active_start_hori_int2[0]_i_5 + (.I0(det_hactive_start_int[11]), + .I1(det_hactive_start_int[10]), + .O(\det_v0active_start_hori_int2[0]_i_5_n_0 )); + LUT2 #( + .INIT(4'hE)) + \det_v0active_start_hori_int2[0]_i_6 + (.I0(det_hactive_start_int[8]), + .I1(det_hactive_start_int[9]), + .O(\det_v0active_start_hori_int2[0]_i_6_n_0 )); + LUT2 #( + .INIT(4'hE)) + \det_v0active_start_hori_int2[0]_i_7 + (.I0(det_hactive_start_int[6]), + .I1(det_hactive_start_int[7]), + .O(\det_v0active_start_hori_int2[0]_i_7_n_0 )); + LUT2 #( + .INIT(4'hE)) + \det_v0active_start_hori_int2[0]_i_8 + (.I0(det_hactive_start_int[4]), + .I1(det_hactive_start_int[5]), + .O(\det_v0active_start_hori_int2[0]_i_8_n_0 )); + LUT2 #( + .INIT(4'hE)) + \det_v0active_start_hori_int2[0]_i_9 + (.I0(det_hactive_start_int[2]), + .I1(det_hactive_start_int[3]), + .O(\det_v0active_start_hori_int2[0]_i_9_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0active_start_hori_int2[11]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [10]), + .I1(\det_v0active_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[10]), + .O(\det_v0active_start_hori_int2[11]_i_2_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0active_start_hori_int2[11]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [9]), + .I1(\det_v0active_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[9]), + .O(\det_v0active_start_hori_int2[11]_i_3_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0active_start_hori_int2[11]_i_4 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [8]), + .I1(\det_v0active_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[8]), + .O(\det_v0active_start_hori_int2[11]_i_4_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0active_start_hori_int2[11]_i_5 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [11]), + .I1(\det_v0active_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[11]), + .O(\det_v0active_start_hori_int2[11]_i_5_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0active_start_hori_int2[11]_i_6 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [10]), + .I1(\det_v0active_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[10]), + .O(\det_v0active_start_hori_int2[11]_i_6_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0active_start_hori_int2[11]_i_7 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [9]), + .I1(\det_v0active_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[9]), + .O(\det_v0active_start_hori_int2[11]_i_7_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0active_start_hori_int2[11]_i_8 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [8]), + .I1(\det_v0active_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[8]), + .O(\det_v0active_start_hori_int2[11]_i_8_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0active_start_hori_int2[3]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [3]), + .I1(\det_v0active_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[3]), + .O(\det_v0active_start_hori_int2[3]_i_2_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0active_start_hori_int2[3]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [2]), + .I1(\det_v0active_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[2]), + .O(\det_v0active_start_hori_int2[3]_i_3_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0active_start_hori_int2[3]_i_4 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [1]), + .I1(\det_v0active_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[1]), + .O(\det_v0active_start_hori_int2[3]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \det_v0active_start_hori_int2[3]_i_5 + (.I0(\det_v0active_start_hori_int2_reg[0]_i_2_n_3 ), + .O(\det_v0active_start_hori_int2[3]_i_5_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0active_start_hori_int2[3]_i_6 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [3]), + .I1(\det_v0active_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[3]), + .O(\det_v0active_start_hori_int2[3]_i_6_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0active_start_hori_int2[3]_i_7 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [2]), + .I1(\det_v0active_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[2]), + .O(\det_v0active_start_hori_int2[3]_i_7_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0active_start_hori_int2[3]_i_8 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [1]), + .I1(\det_v0active_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[1]), + .O(\det_v0active_start_hori_int2[3]_i_8_n_0 )); + LUT3 #( + .INIT(8'hE2)) + \det_v0active_start_hori_int2[3]_i_9 + (.I0(det_hactive_start_int[0]), + .I1(\det_v0active_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [0]), + .O(\det_v0active_start_hori_int2[3]_i_9_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0active_start_hori_int2[7]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [7]), + .I1(\det_v0active_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[7]), + .O(\det_v0active_start_hori_int2[7]_i_2_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0active_start_hori_int2[7]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [6]), + .I1(\det_v0active_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[6]), + .O(\det_v0active_start_hori_int2[7]_i_3_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0active_start_hori_int2[7]_i_4 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [5]), + .I1(\det_v0active_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[5]), + .O(\det_v0active_start_hori_int2[7]_i_4_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0active_start_hori_int2[7]_i_5 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [4]), + .I1(\det_v0active_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[4]), + .O(\det_v0active_start_hori_int2[7]_i_5_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0active_start_hori_int2[7]_i_6 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [7]), + .I1(\det_v0active_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[7]), + .O(\det_v0active_start_hori_int2[7]_i_6_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0active_start_hori_int2[7]_i_7 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [6]), + .I1(\det_v0active_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[6]), + .O(\det_v0active_start_hori_int2[7]_i_7_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0active_start_hori_int2[7]_i_8 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [5]), + .I1(\det_v0active_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[5]), + .O(\det_v0active_start_hori_int2[7]_i_8_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0active_start_hori_int2[7]_i_9 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [4]), + .I1(\det_v0active_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[4]), + .O(\det_v0active_start_hori_int2[7]_i_9_n_0 )); + FDRE \det_v0active_start_hori_int2_reg[0] + (.C(clk), + .CE(det_ce), + .D(\det_v0active_start_hori_int2[0]_i_1_n_0 ), + .Q(\time_status_regs[7] [12]), + .R(reset)); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \det_v0active_start_hori_int2_reg[0]_i_2 + (.CI(\det_v0active_start_hori_int2_reg[0]_i_3_n_0 ), + .CO({\NLW_det_v0active_start_hori_int2_reg[0]_i_2_CO_UNCONNECTED [3:1],\det_v0active_start_hori_int2_reg[0]_i_2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,\det_v0active_start_hori_int2[0]_i_4_n_0 }), + .O(\NLW_det_v0active_start_hori_int2_reg[0]_i_2_O_UNCONNECTED [3:0]), + .S({1'b0,1'b0,1'b0,\det_v0active_start_hori_int2[0]_i_5_n_0 })); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \det_v0active_start_hori_int2_reg[0]_i_3 + (.CI(1'b0), + .CO({\det_v0active_start_hori_int2_reg[0]_i_3_n_0 ,\det_v0active_start_hori_int2_reg[0]_i_3_n_1 ,\det_v0active_start_hori_int2_reg[0]_i_3_n_2 ,\det_v0active_start_hori_int2_reg[0]_i_3_n_3 }), + .CYINIT(\det_v0fp_start_hori_int2[0]_i_6_n_0 ), + .DI({\det_v0active_start_hori_int2[0]_i_6_n_0 ,\det_v0active_start_hori_int2[0]_i_7_n_0 ,\det_v0active_start_hori_int2[0]_i_8_n_0 ,\det_v0active_start_hori_int2[0]_i_9_n_0 }), + .O(\NLW_det_v0active_start_hori_int2_reg[0]_i_3_O_UNCONNECTED [3:0]), + .S({\det_v0active_start_hori_int2[0]_i_10_n_0 ,\det_v0active_start_hori_int2[0]_i_11_n_0 ,\det_v0active_start_hori_int2[0]_i_12_n_0 ,\det_v0active_start_hori_int2[0]_i_13_n_0 })); + FDRE \det_v0active_start_hori_int2_reg[10] + (.C(clk), + .CE(det_ce), + .D(det_v0active_start_hori_int2[10]), + .Q(\time_status_regs[7] [22]), + .R(reset)); + FDRE \det_v0active_start_hori_int2_reg[11] + (.C(clk), + .CE(det_ce), + .D(det_v0active_start_hori_int2[11]), + .Q(\time_status_regs[7] [23]), + .R(reset)); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \det_v0active_start_hori_int2_reg[11]_i_1 + (.CI(\det_v0active_start_hori_int2_reg[7]_i_1_n_0 ), + .CO({\NLW_det_v0active_start_hori_int2_reg[11]_i_1_CO_UNCONNECTED [3],\det_v0active_start_hori_int2_reg[11]_i_1_n_1 ,\det_v0active_start_hori_int2_reg[11]_i_1_n_2 ,\det_v0active_start_hori_int2_reg[11]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,\det_v0active_start_hori_int2[11]_i_2_n_0 ,\det_v0active_start_hori_int2[11]_i_3_n_0 ,\det_v0active_start_hori_int2[11]_i_4_n_0 }), + .O(det_v0active_start_hori_int2[11:8]), + .S({\det_v0active_start_hori_int2[11]_i_5_n_0 ,\det_v0active_start_hori_int2[11]_i_6_n_0 ,\det_v0active_start_hori_int2[11]_i_7_n_0 ,\det_v0active_start_hori_int2[11]_i_8_n_0 })); + FDRE \det_v0active_start_hori_int2_reg[1] + (.C(clk), + .CE(det_ce), + .D(det_v0active_start_hori_int2[1]), + .Q(\time_status_regs[7] [13]), + .R(reset)); + FDRE \det_v0active_start_hori_int2_reg[2] + (.C(clk), + .CE(det_ce), + .D(det_v0active_start_hori_int2[2]), + .Q(\time_status_regs[7] [14]), + .R(reset)); + FDRE \det_v0active_start_hori_int2_reg[3] + (.C(clk), + .CE(det_ce), + .D(det_v0active_start_hori_int2[3]), + .Q(\time_status_regs[7] [15]), + .R(reset)); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \det_v0active_start_hori_int2_reg[3]_i_1 + (.CI(1'b0), + .CO({\det_v0active_start_hori_int2_reg[3]_i_1_n_0 ,\det_v0active_start_hori_int2_reg[3]_i_1_n_1 ,\det_v0active_start_hori_int2_reg[3]_i_1_n_2 ,\det_v0active_start_hori_int2_reg[3]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({\det_v0active_start_hori_int2[3]_i_2_n_0 ,\det_v0active_start_hori_int2[3]_i_3_n_0 ,\det_v0active_start_hori_int2[3]_i_4_n_0 ,\det_v0active_start_hori_int2[3]_i_5_n_0 }), + .O({det_v0active_start_hori_int2[3:1],\NLW_det_v0active_start_hori_int2_reg[3]_i_1_O_UNCONNECTED [0]}), + .S({\det_v0active_start_hori_int2[3]_i_6_n_0 ,\det_v0active_start_hori_int2[3]_i_7_n_0 ,\det_v0active_start_hori_int2[3]_i_8_n_0 ,\det_v0active_start_hori_int2[3]_i_9_n_0 })); + FDRE \det_v0active_start_hori_int2_reg[4] + (.C(clk), + .CE(det_ce), + .D(det_v0active_start_hori_int2[4]), + .Q(\time_status_regs[7] [16]), + .R(reset)); + FDRE \det_v0active_start_hori_int2_reg[5] + (.C(clk), + .CE(det_ce), + .D(det_v0active_start_hori_int2[5]), + .Q(\time_status_regs[7] [17]), + .R(reset)); + FDRE \det_v0active_start_hori_int2_reg[6] + (.C(clk), + .CE(det_ce), + .D(det_v0active_start_hori_int2[6]), + .Q(\time_status_regs[7] [18]), + .R(reset)); + FDRE \det_v0active_start_hori_int2_reg[7] + (.C(clk), + .CE(det_ce), + .D(det_v0active_start_hori_int2[7]), + .Q(\time_status_regs[7] [19]), + .R(reset)); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \det_v0active_start_hori_int2_reg[7]_i_1 + (.CI(\det_v0active_start_hori_int2_reg[3]_i_1_n_0 ), + .CO({\det_v0active_start_hori_int2_reg[7]_i_1_n_0 ,\det_v0active_start_hori_int2_reg[7]_i_1_n_1 ,\det_v0active_start_hori_int2_reg[7]_i_1_n_2 ,\det_v0active_start_hori_int2_reg[7]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({\det_v0active_start_hori_int2[7]_i_2_n_0 ,\det_v0active_start_hori_int2[7]_i_3_n_0 ,\det_v0active_start_hori_int2[7]_i_4_n_0 ,\det_v0active_start_hori_int2[7]_i_5_n_0 }), + .O(det_v0active_start_hori_int2[7:4]), + .S({\det_v0active_start_hori_int2[7]_i_6_n_0 ,\det_v0active_start_hori_int2[7]_i_7_n_0 ,\det_v0active_start_hori_int2[7]_i_8_n_0 ,\det_v0active_start_hori_int2[7]_i_9_n_0 })); + FDRE \det_v0active_start_hori_int2_reg[8] + (.C(clk), + .CE(det_ce), + .D(det_v0active_start_hori_int2[8]), + .Q(\time_status_regs[7] [20]), + .R(reset)); + FDRE \det_v0active_start_hori_int2_reg[9] + (.C(clk), + .CE(det_ce), + .D(det_v0active_start_hori_int2[9]), + .Q(\time_status_regs[7] [21]), + .R(reset)); + LUT6 #( + .INIT(64'h0000000040000040)) + \det_v0active_start_int[10]_i_1 + (.I0(active_line_d), + .I1(active_line), + .I2(det_ce), + .I3(\time_status_regs[3] [1]), + .I4(hsync_in), + .I5(line_end_d_reg_n_0), + .O(det_v0active_start_int_6)); + FDRE \det_v0active_start_int_reg[0] + (.C(clk), + .CE(det_v0active_start_int_6), + .D(v_count_reg__0[0]), + .Q(det_v0active_start_int[0]), + .R(h_count1)); + FDRE \det_v0active_start_int_reg[10] + (.C(clk), + .CE(det_v0active_start_int_6), + .D(v_count_reg__0[10]), + .Q(det_v0active_start_int[10]), + .R(h_count1)); + FDRE \det_v0active_start_int_reg[1] + (.C(clk), + .CE(det_v0active_start_int_6), + .D(v_count_reg__0[1]), + .Q(det_v0active_start_int[1]), + .R(h_count1)); + FDRE \det_v0active_start_int_reg[2] + (.C(clk), + .CE(det_v0active_start_int_6), + .D(v_count_reg__0[2]), + .Q(det_v0active_start_int[2]), + .R(h_count1)); + FDRE \det_v0active_start_int_reg[3] + (.C(clk), + .CE(det_v0active_start_int_6), + .D(v_count_reg__0[3]), + .Q(det_v0active_start_int[3]), + .R(h_count1)); + FDRE \det_v0active_start_int_reg[4] + (.C(clk), + .CE(det_v0active_start_int_6), + .D(v_count_reg__0[4]), + .Q(det_v0active_start_int[4]), + .R(h_count1)); + FDRE \det_v0active_start_int_reg[5] + (.C(clk), + .CE(det_v0active_start_int_6), + .D(v_count_reg__0[5]), + .Q(det_v0active_start_int[5]), + .R(h_count1)); + FDRE \det_v0active_start_int_reg[6] + (.C(clk), + .CE(det_v0active_start_int_6), + .D(v_count_reg__0[6]), + .Q(det_v0active_start_int[6]), + .R(h_count1)); + FDRE \det_v0active_start_int_reg[7] + (.C(clk), + .CE(det_v0active_start_int_6), + .D(v_count_reg__0[7]), + .Q(det_v0active_start_int[7]), + .R(h_count1)); + FDRE \det_v0active_start_int_reg[8] + (.C(clk), + .CE(det_v0active_start_int_6), + .D(v_count_reg__0[8]), + .Q(det_v0active_start_int[8]), + .R(h_count1)); + FDRE \det_v0active_start_int_reg[9] + (.C(clk), + .CE(det_v0active_start_int_6), + .D(v_count_reg__0[9]), + .Q(det_v0active_start_int[9]), + .R(h_count1)); + FDRE \det_v0bp_start_hori_int2_reg[0] + (.C(clk), + .CE(det_ce), + .D(det_v0bp_start_hori_int2[0]), + .Q(\time_status_regs[9] [12]), + .R(reset)); + FDRE \det_v0bp_start_hori_int2_reg[10] + (.C(clk), + .CE(det_ce), + .D(det_v0bp_start_hori_int2[10]), + .Q(\time_status_regs[9] [22]), + .R(reset)); + FDRE \det_v0bp_start_hori_int2_reg[11] + (.C(clk), + .CE(det_ce), + .D(det_v0bp_start_hori_int2[11]), + .Q(\time_status_regs[9] [23]), + .R(reset)); + FDRE \det_v0bp_start_hori_int2_reg[1] + (.C(clk), + .CE(det_ce), + .D(det_v0bp_start_hori_int2[1]), + .Q(\time_status_regs[9] [13]), + .R(reset)); + FDRE \det_v0bp_start_hori_int2_reg[2] + (.C(clk), + .CE(det_ce), + .D(det_v0bp_start_hori_int2[2]), + .Q(\time_status_regs[9] [14]), + .R(reset)); + FDRE \det_v0bp_start_hori_int2_reg[3] + (.C(clk), + .CE(det_ce), + .D(det_v0bp_start_hori_int2[3]), + .Q(\time_status_regs[9] [15]), + .R(reset)); + FDRE \det_v0bp_start_hori_int2_reg[4] + (.C(clk), + .CE(det_ce), + .D(det_v0bp_start_hori_int2[4]), + .Q(\time_status_regs[9] [16]), + .R(reset)); + FDRE \det_v0bp_start_hori_int2_reg[5] + (.C(clk), + .CE(det_ce), + .D(det_v0bp_start_hori_int2[5]), + .Q(\time_status_regs[9] [17]), + .R(reset)); + FDRE \det_v0bp_start_hori_int2_reg[6] + (.C(clk), + .CE(det_ce), + .D(det_v0bp_start_hori_int2[6]), + .Q(\time_status_regs[9] [18]), + .R(reset)); + FDRE \det_v0bp_start_hori_int2_reg[7] + (.C(clk), + .CE(det_ce), + .D(det_v0bp_start_hori_int2[7]), + .Q(\time_status_regs[9] [19]), + .R(reset)); + FDRE \det_v0bp_start_hori_int2_reg[8] + (.C(clk), + .CE(det_ce), + .D(det_v0bp_start_hori_int2[8]), + .Q(\time_status_regs[9] [20]), + .R(reset)); + FDRE \det_v0bp_start_hori_int2_reg[9] + (.C(clk), + .CE(det_ce), + .D(det_v0bp_start_hori_int2[9]), + .Q(\time_status_regs[9] [21]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \det_v0bp_start_int2[10]_i_2 + (.I0(det_v0bp_start_int[10]), + .O(\det_v0bp_start_int2[10]_i_2_n_0 )); + LUT1 #( + .INIT(2'h1)) + \det_v0bp_start_int2[10]_i_3 + (.I0(det_v0bp_start_int[9]), + .O(\det_v0bp_start_int2[10]_i_3_n_0 )); + LUT1 #( + .INIT(2'h1)) + \det_v0bp_start_int2[10]_i_4 + (.I0(det_v0bp_start_int[8]), + .O(\det_v0bp_start_int2[10]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \det_v0bp_start_int2[3]_i_2 + (.I0(det_v0bp_start_int[3]), + .O(\det_v0bp_start_int2[3]_i_2_n_0 )); + LUT1 #( + .INIT(2'h1)) + \det_v0bp_start_int2[3]_i_3 + (.I0(det_v0bp_start_int[2]), + .O(\det_v0bp_start_int2[3]_i_3_n_0 )); + LUT1 #( + .INIT(2'h1)) + \det_v0bp_start_int2[3]_i_4 + (.I0(det_v0bp_start_int[1]), + .O(\det_v0bp_start_int2[3]_i_4_n_0 )); + LUT2 #( + .INIT(4'h9)) + \det_v0bp_start_int2[3]_i_5 + (.I0(det_v0bp_start_int[0]), + .I1(\ltOp_inferred__0/i__carry__0_n_2 ), + .O(\det_v0bp_start_int2[3]_i_5_n_0 )); + LUT1 #( + .INIT(2'h1)) + \det_v0bp_start_int2[7]_i_2 + (.I0(det_v0bp_start_int[7]), + .O(\det_v0bp_start_int2[7]_i_2_n_0 )); + LUT1 #( + .INIT(2'h1)) + \det_v0bp_start_int2[7]_i_3 + (.I0(det_v0bp_start_int[6]), + .O(\det_v0bp_start_int2[7]_i_3_n_0 )); + LUT1 #( + .INIT(2'h1)) + \det_v0bp_start_int2[7]_i_4 + (.I0(det_v0bp_start_int[5]), + .O(\det_v0bp_start_int2[7]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \det_v0bp_start_int2[7]_i_5 + (.I0(det_v0bp_start_int[4]), + .O(\det_v0bp_start_int2[7]_i_5_n_0 )); + FDRE \det_v0bp_start_int2_reg[0] + (.C(clk), + .CE(det_ce), + .D(det_v0bp_start_int2[0]), + .Q(\time_status_regs[8] [11]), + .R(reset)); + FDRE \det_v0bp_start_int2_reg[10] + (.C(clk), + .CE(det_ce), + .D(det_v0bp_start_int2[10]), + .Q(\time_status_regs[8] [21]), + .R(reset)); + CARRY4 \det_v0bp_start_int2_reg[10]_i_1 + (.CI(\det_v0bp_start_int2_reg[7]_i_1_n_0 ), + .CO({\NLW_det_v0bp_start_int2_reg[10]_i_1_CO_UNCONNECTED [3:2],\det_v0bp_start_int2_reg[10]_i_1_n_2 ,\det_v0bp_start_int2_reg[10]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,det_v0bp_start_int[9:8]}), + .O({\NLW_det_v0bp_start_int2_reg[10]_i_1_O_UNCONNECTED [3],det_v0bp_start_int2[10:8]}), + .S({1'b0,\det_v0bp_start_int2[10]_i_2_n_0 ,\det_v0bp_start_int2[10]_i_3_n_0 ,\det_v0bp_start_int2[10]_i_4_n_0 })); + FDRE \det_v0bp_start_int2_reg[1] + (.C(clk), + .CE(det_ce), + .D(det_v0bp_start_int2[1]), + .Q(\time_status_regs[8] [12]), + .R(reset)); + FDRE \det_v0bp_start_int2_reg[2] + (.C(clk), + .CE(det_ce), + .D(det_v0bp_start_int2[2]), + .Q(\time_status_regs[8] [13]), + .R(reset)); + FDRE \det_v0bp_start_int2_reg[3] + (.C(clk), + .CE(det_ce), + .D(det_v0bp_start_int2[3]), + .Q(\time_status_regs[8] [14]), + .R(reset)); + CARRY4 \det_v0bp_start_int2_reg[3]_i_1 + (.CI(1'b0), + .CO({\det_v0bp_start_int2_reg[3]_i_1_n_0 ,\det_v0bp_start_int2_reg[3]_i_1_n_1 ,\det_v0bp_start_int2_reg[3]_i_1_n_2 ,\det_v0bp_start_int2_reg[3]_i_1_n_3 }), + .CYINIT(1'b1), + .DI(det_v0bp_start_int[3:0]), + .O(det_v0bp_start_int2[3:0]), + .S({\det_v0bp_start_int2[3]_i_2_n_0 ,\det_v0bp_start_int2[3]_i_3_n_0 ,\det_v0bp_start_int2[3]_i_4_n_0 ,\det_v0bp_start_int2[3]_i_5_n_0 })); + FDRE \det_v0bp_start_int2_reg[4] + (.C(clk), + .CE(det_ce), + .D(det_v0bp_start_int2[4]), + .Q(\time_status_regs[8] [15]), + .R(reset)); + FDRE \det_v0bp_start_int2_reg[5] + (.C(clk), + .CE(det_ce), + .D(det_v0bp_start_int2[5]), + .Q(\time_status_regs[8] [16]), + .R(reset)); + FDRE \det_v0bp_start_int2_reg[6] + (.C(clk), + .CE(det_ce), + .D(det_v0bp_start_int2[6]), + .Q(\time_status_regs[8] [17]), + .R(reset)); + FDRE \det_v0bp_start_int2_reg[7] + (.C(clk), + .CE(det_ce), + .D(det_v0bp_start_int2[7]), + .Q(\time_status_regs[8] [18]), + .R(reset)); + CARRY4 \det_v0bp_start_int2_reg[7]_i_1 + (.CI(\det_v0bp_start_int2_reg[3]_i_1_n_0 ), + .CO({\det_v0bp_start_int2_reg[7]_i_1_n_0 ,\det_v0bp_start_int2_reg[7]_i_1_n_1 ,\det_v0bp_start_int2_reg[7]_i_1_n_2 ,\det_v0bp_start_int2_reg[7]_i_1_n_3 }), + .CYINIT(1'b0), + .DI(det_v0bp_start_int[7:4]), + .O(det_v0bp_start_int2[7:4]), + .S({\det_v0bp_start_int2[7]_i_2_n_0 ,\det_v0bp_start_int2[7]_i_3_n_0 ,\det_v0bp_start_int2[7]_i_4_n_0 ,\det_v0bp_start_int2[7]_i_5_n_0 })); + FDRE \det_v0bp_start_int2_reg[8] + (.C(clk), + .CE(det_ce), + .D(det_v0bp_start_int2[8]), + .Q(\time_status_regs[8] [19]), + .R(reset)); + FDRE \det_v0bp_start_int2_reg[9] + (.C(clk), + .CE(det_ce), + .D(det_v0bp_start_int2[9]), + .Q(\time_status_regs[8] [20]), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair292" *) + LUT3 #( + .INIT(8'hE2)) + \det_v0fp_start_hori_int2[0]_i_1 + (.I0(det_hactive_start_int[0]), + .I1(\det_v0fp_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [0]), + .O(\det_v0fp_start_hori_int2[0]_i_1_n_0 )); + LUT2 #( + .INIT(4'hE)) + \det_v0fp_start_hori_int2[0]_i_10 + (.I0(det_hactive_start_int[2]), + .I1(det_hactive_start_int[3]), + .O(\det_v0fp_start_hori_int2[0]_i_10_n_0 )); + LUT2 #( + .INIT(4'h1)) + \det_v0fp_start_hori_int2[0]_i_11 + (.I0(det_hactive_start_int[9]), + .I1(det_hactive_start_int[8]), + .O(\det_v0fp_start_hori_int2[0]_i_11_n_0 )); + LUT2 #( + .INIT(4'h1)) + \det_v0fp_start_hori_int2[0]_i_12 + (.I0(det_hactive_start_int[7]), + .I1(det_hactive_start_int[6]), + .O(\det_v0fp_start_hori_int2[0]_i_12_n_0 )); + LUT2 #( + .INIT(4'h1)) + \det_v0fp_start_hori_int2[0]_i_13 + (.I0(det_hactive_start_int[5]), + .I1(det_hactive_start_int[4]), + .O(\det_v0fp_start_hori_int2[0]_i_13_n_0 )); + LUT2 #( + .INIT(4'h1)) + \det_v0fp_start_hori_int2[0]_i_14 + (.I0(det_hactive_start_int[3]), + .I1(det_hactive_start_int[2]), + .O(\det_v0fp_start_hori_int2[0]_i_14_n_0 )); + LUT2 #( + .INIT(4'hE)) + \det_v0fp_start_hori_int2[0]_i_4 + (.I0(det_hactive_start_int[10]), + .I1(det_hactive_start_int[11]), + .O(\det_v0fp_start_hori_int2[0]_i_4_n_0 )); + LUT2 #( + .INIT(4'h1)) + \det_v0fp_start_hori_int2[0]_i_5 + (.I0(det_hactive_start_int[11]), + .I1(det_hactive_start_int[10]), + .O(\det_v0fp_start_hori_int2[0]_i_5_n_0 )); + LUT2 #( + .INIT(4'hE)) + \det_v0fp_start_hori_int2[0]_i_6 + (.I0(det_hactive_start_int[1]), + .I1(det_hactive_start_int[0]), + .O(\det_v0fp_start_hori_int2[0]_i_6_n_0 )); + LUT2 #( + .INIT(4'hE)) + \det_v0fp_start_hori_int2[0]_i_7 + (.I0(det_hactive_start_int[8]), + .I1(det_hactive_start_int[9]), + .O(\det_v0fp_start_hori_int2[0]_i_7_n_0 )); + LUT2 #( + .INIT(4'hE)) + \det_v0fp_start_hori_int2[0]_i_8 + (.I0(det_hactive_start_int[6]), + .I1(det_hactive_start_int[7]), + .O(\det_v0fp_start_hori_int2[0]_i_8_n_0 )); + LUT2 #( + .INIT(4'hE)) + \det_v0fp_start_hori_int2[0]_i_9 + (.I0(det_hactive_start_int[4]), + .I1(det_hactive_start_int[5]), + .O(\det_v0fp_start_hori_int2[0]_i_9_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0fp_start_hori_int2[11]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [10]), + .I1(\det_v0fp_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[10]), + .O(\det_v0fp_start_hori_int2[11]_i_2_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0fp_start_hori_int2[11]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [9]), + .I1(\det_v0fp_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[9]), + .O(\det_v0fp_start_hori_int2[11]_i_3_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0fp_start_hori_int2[11]_i_4 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [8]), + .I1(\det_v0fp_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[8]), + .O(\det_v0fp_start_hori_int2[11]_i_4_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0fp_start_hori_int2[11]_i_5 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [11]), + .I1(\det_v0fp_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[11]), + .O(\det_v0fp_start_hori_int2[11]_i_5_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0fp_start_hori_int2[11]_i_6 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [10]), + .I1(\det_v0fp_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[10]), + .O(\det_v0fp_start_hori_int2[11]_i_6_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0fp_start_hori_int2[11]_i_7 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [9]), + .I1(\det_v0fp_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[9]), + .O(\det_v0fp_start_hori_int2[11]_i_7_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0fp_start_hori_int2[11]_i_8 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [8]), + .I1(\det_v0fp_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[8]), + .O(\det_v0fp_start_hori_int2[11]_i_8_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0fp_start_hori_int2[3]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [3]), + .I1(\det_v0fp_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[3]), + .O(\det_v0fp_start_hori_int2[3]_i_2_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0fp_start_hori_int2[3]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [2]), + .I1(\det_v0fp_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[2]), + .O(\det_v0fp_start_hori_int2[3]_i_3_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0fp_start_hori_int2[3]_i_4 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [1]), + .I1(\det_v0fp_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[1]), + .O(\det_v0fp_start_hori_int2[3]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \det_v0fp_start_hori_int2[3]_i_5 + (.I0(\det_v0fp_start_hori_int2_reg[0]_i_2_n_3 ), + .O(\det_v0fp_start_hori_int2[3]_i_5_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0fp_start_hori_int2[3]_i_6 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [3]), + .I1(\det_v0fp_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[3]), + .O(\det_v0fp_start_hori_int2[3]_i_6_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0fp_start_hori_int2[3]_i_7 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [2]), + .I1(\det_v0fp_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[2]), + .O(\det_v0fp_start_hori_int2[3]_i_7_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0fp_start_hori_int2[3]_i_8 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [1]), + .I1(\det_v0fp_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[1]), + .O(\det_v0fp_start_hori_int2[3]_i_8_n_0 )); + LUT3 #( + .INIT(8'hE2)) + \det_v0fp_start_hori_int2[3]_i_9 + (.I0(det_hactive_start_int[0]), + .I1(\det_v0fp_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [0]), + .O(\det_v0fp_start_hori_int2[3]_i_9_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0fp_start_hori_int2[7]_i_2 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [7]), + .I1(\det_v0fp_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[7]), + .O(\det_v0fp_start_hori_int2[7]_i_2_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0fp_start_hori_int2[7]_i_3 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [6]), + .I1(\det_v0fp_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[6]), + .O(\det_v0fp_start_hori_int2[7]_i_3_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0fp_start_hori_int2[7]_i_4 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [5]), + .I1(\det_v0fp_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[5]), + .O(\det_v0fp_start_hori_int2[7]_i_4_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0fp_start_hori_int2[7]_i_5 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [4]), + .I1(\det_v0fp_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[4]), + .O(\det_v0fp_start_hori_int2[7]_i_5_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0fp_start_hori_int2[7]_i_6 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [7]), + .I1(\det_v0fp_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[7]), + .O(\det_v0fp_start_hori_int2[7]_i_6_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0fp_start_hori_int2[7]_i_7 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [6]), + .I1(\det_v0fp_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[6]), + .O(\det_v0fp_start_hori_int2[7]_i_7_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0fp_start_hori_int2[7]_i_8 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [5]), + .I1(\det_v0fp_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[5]), + .O(\det_v0fp_start_hori_int2[7]_i_8_n_0 )); + LUT3 #( + .INIT(8'h8B)) + \det_v0fp_start_hori_int2[7]_i_9 + (.I0(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [4]), + .I1(\det_v0fp_start_hori_int2_reg[0]_i_2_n_3 ), + .I2(det_hactive_start_int[4]), + .O(\det_v0fp_start_hori_int2[7]_i_9_n_0 )); + FDRE \det_v0fp_start_hori_int2_reg[0] + (.C(clk), + .CE(det_ce), + .D(\det_v0fp_start_hori_int2[0]_i_1_n_0 ), + .Q(\time_status_regs[7] [0]), + .R(reset)); + CARRY4 \det_v0fp_start_hori_int2_reg[0]_i_2 + (.CI(\det_v0fp_start_hori_int2_reg[0]_i_3_n_0 ), + .CO({\NLW_det_v0fp_start_hori_int2_reg[0]_i_2_CO_UNCONNECTED [3:1],\det_v0fp_start_hori_int2_reg[0]_i_2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,\det_v0fp_start_hori_int2[0]_i_4_n_0 }), + .O(\NLW_det_v0fp_start_hori_int2_reg[0]_i_2_O_UNCONNECTED [3:0]), + .S({1'b0,1'b0,1'b0,\det_v0fp_start_hori_int2[0]_i_5_n_0 })); + CARRY4 \det_v0fp_start_hori_int2_reg[0]_i_3 + (.CI(1'b0), + .CO({\det_v0fp_start_hori_int2_reg[0]_i_3_n_0 ,\det_v0fp_start_hori_int2_reg[0]_i_3_n_1 ,\det_v0fp_start_hori_int2_reg[0]_i_3_n_2 ,\det_v0fp_start_hori_int2_reg[0]_i_3_n_3 }), + .CYINIT(\det_v0fp_start_hori_int2[0]_i_6_n_0 ), + .DI({\det_v0fp_start_hori_int2[0]_i_7_n_0 ,\det_v0fp_start_hori_int2[0]_i_8_n_0 ,\det_v0fp_start_hori_int2[0]_i_9_n_0 ,\det_v0fp_start_hori_int2[0]_i_10_n_0 }), + .O(\NLW_det_v0fp_start_hori_int2_reg[0]_i_3_O_UNCONNECTED [3:0]), + .S({\det_v0fp_start_hori_int2[0]_i_11_n_0 ,\det_v0fp_start_hori_int2[0]_i_12_n_0 ,\det_v0fp_start_hori_int2[0]_i_13_n_0 ,\det_v0fp_start_hori_int2[0]_i_14_n_0 })); + FDRE \det_v0fp_start_hori_int2_reg[10] + (.C(clk), + .CE(det_ce), + .D(det_v0fp_start_hori_int2[10]), + .Q(\time_status_regs[7] [10]), + .R(reset)); + FDRE \det_v0fp_start_hori_int2_reg[11] + (.C(clk), + .CE(det_ce), + .D(det_v0fp_start_hori_int2[11]), + .Q(\time_status_regs[7] [11]), + .R(reset)); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \det_v0fp_start_hori_int2_reg[11]_i_1 + (.CI(\det_v0fp_start_hori_int2_reg[7]_i_1_n_0 ), + .CO({\NLW_det_v0fp_start_hori_int2_reg[11]_i_1_CO_UNCONNECTED [3],\det_v0fp_start_hori_int2_reg[11]_i_1_n_1 ,\det_v0fp_start_hori_int2_reg[11]_i_1_n_2 ,\det_v0fp_start_hori_int2_reg[11]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,\det_v0fp_start_hori_int2[11]_i_2_n_0 ,\det_v0fp_start_hori_int2[11]_i_3_n_0 ,\det_v0fp_start_hori_int2[11]_i_4_n_0 }), + .O(det_v0fp_start_hori_int2[11:8]), + .S({\det_v0fp_start_hori_int2[11]_i_5_n_0 ,\det_v0fp_start_hori_int2[11]_i_6_n_0 ,\det_v0fp_start_hori_int2[11]_i_7_n_0 ,\det_v0fp_start_hori_int2[11]_i_8_n_0 })); + FDRE \det_v0fp_start_hori_int2_reg[1] + (.C(clk), + .CE(det_ce), + .D(det_v0fp_start_hori_int2[1]), + .Q(\time_status_regs[7] [1]), + .R(reset)); + FDRE \det_v0fp_start_hori_int2_reg[2] + (.C(clk), + .CE(det_ce), + .D(det_v0fp_start_hori_int2[2]), + .Q(\time_status_regs[7] [2]), + .R(reset)); + FDRE \det_v0fp_start_hori_int2_reg[3] + (.C(clk), + .CE(det_ce), + .D(det_v0fp_start_hori_int2[3]), + .Q(\time_status_regs[7] [3]), + .R(reset)); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \det_v0fp_start_hori_int2_reg[3]_i_1 + (.CI(1'b0), + .CO({\det_v0fp_start_hori_int2_reg[3]_i_1_n_0 ,\det_v0fp_start_hori_int2_reg[3]_i_1_n_1 ,\det_v0fp_start_hori_int2_reg[3]_i_1_n_2 ,\det_v0fp_start_hori_int2_reg[3]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({\det_v0fp_start_hori_int2[3]_i_2_n_0 ,\det_v0fp_start_hori_int2[3]_i_3_n_0 ,\det_v0fp_start_hori_int2[3]_i_4_n_0 ,\det_v0fp_start_hori_int2[3]_i_5_n_0 }), + .O({det_v0fp_start_hori_int2[3:1],\NLW_det_v0fp_start_hori_int2_reg[3]_i_1_O_UNCONNECTED [0]}), + .S({\det_v0fp_start_hori_int2[3]_i_6_n_0 ,\det_v0fp_start_hori_int2[3]_i_7_n_0 ,\det_v0fp_start_hori_int2[3]_i_8_n_0 ,\det_v0fp_start_hori_int2[3]_i_9_n_0 })); + FDRE \det_v0fp_start_hori_int2_reg[4] + (.C(clk), + .CE(det_ce), + .D(det_v0fp_start_hori_int2[4]), + .Q(\time_status_regs[7] [4]), + .R(reset)); + FDRE \det_v0fp_start_hori_int2_reg[5] + (.C(clk), + .CE(det_ce), + .D(det_v0fp_start_hori_int2[5]), + .Q(\time_status_regs[7] [5]), + .R(reset)); + FDRE \det_v0fp_start_hori_int2_reg[6] + (.C(clk), + .CE(det_ce), + .D(det_v0fp_start_hori_int2[6]), + .Q(\time_status_regs[7] [6]), + .R(reset)); + FDRE \det_v0fp_start_hori_int2_reg[7] + (.C(clk), + .CE(det_ce), + .D(det_v0fp_start_hori_int2[7]), + .Q(\time_status_regs[7] [7]), + .R(reset)); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \det_v0fp_start_hori_int2_reg[7]_i_1 + (.CI(\det_v0fp_start_hori_int2_reg[3]_i_1_n_0 ), + .CO({\det_v0fp_start_hori_int2_reg[7]_i_1_n_0 ,\det_v0fp_start_hori_int2_reg[7]_i_1_n_1 ,\det_v0fp_start_hori_int2_reg[7]_i_1_n_2 ,\det_v0fp_start_hori_int2_reg[7]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({\det_v0fp_start_hori_int2[7]_i_2_n_0 ,\det_v0fp_start_hori_int2[7]_i_3_n_0 ,\det_v0fp_start_hori_int2[7]_i_4_n_0 ,\det_v0fp_start_hori_int2[7]_i_5_n_0 }), + .O(det_v0fp_start_hori_int2[7:4]), + .S({\det_v0fp_start_hori_int2[7]_i_6_n_0 ,\det_v0fp_start_hori_int2[7]_i_7_n_0 ,\det_v0fp_start_hori_int2[7]_i_8_n_0 ,\det_v0fp_start_hori_int2[7]_i_9_n_0 })); + FDRE \det_v0fp_start_hori_int2_reg[8] + (.C(clk), + .CE(det_ce), + .D(det_v0fp_start_hori_int2[8]), + .Q(\time_status_regs[7] [8]), + .R(reset)); + FDRE \det_v0fp_start_hori_int2_reg[9] + (.C(clk), + .CE(det_ce), + .D(det_v0fp_start_hori_int2[9]), + .Q(\time_status_regs[7] [9]), + .R(reset)); + LUT6 #( + .INIT(64'h0008000000000008)) + \det_v0fp_start_int[10]_i_1 + (.I0(det_ce), + .I1(active_line_d), + .I2(active_line), + .I3(line_end_d_reg_n_0), + .I4(hsync_in), + .I5(\time_status_regs[3] [1]), + .O(det_v0fp_start_int)); + FDRE \det_v0fp_start_int_reg[0] + (.C(clk), + .CE(det_v0fp_start_int), + .D(v_count_reg__0[0]), + .Q(\time_status_regs_int_reg[0] [0]), + .R(h_count1)); + FDRE \det_v0fp_start_int_reg[10] + (.C(clk), + .CE(det_v0fp_start_int), + .D(v_count_reg__0[10]), + .Q(\time_status_regs_int_reg[0] [10]), + .R(h_count1)); + FDRE \det_v0fp_start_int_reg[1] + (.C(clk), + .CE(det_v0fp_start_int), + .D(v_count_reg__0[1]), + .Q(\time_status_regs_int_reg[0] [1]), + .R(h_count1)); + FDRE \det_v0fp_start_int_reg[2] + (.C(clk), + .CE(det_v0fp_start_int), + .D(v_count_reg__0[2]), + .Q(\time_status_regs_int_reg[0] [2]), + .R(h_count1)); + FDRE \det_v0fp_start_int_reg[3] + (.C(clk), + .CE(det_v0fp_start_int), + .D(v_count_reg__0[3]), + .Q(\time_status_regs_int_reg[0] [3]), + .R(h_count1)); + FDRE \det_v0fp_start_int_reg[4] + (.C(clk), + .CE(det_v0fp_start_int), + .D(v_count_reg__0[4]), + .Q(\time_status_regs_int_reg[0] [4]), + .R(h_count1)); + FDRE \det_v0fp_start_int_reg[5] + (.C(clk), + .CE(det_v0fp_start_int), + .D(v_count_reg__0[5]), + .Q(\time_status_regs_int_reg[0] [5]), + .R(h_count1)); + FDRE \det_v0fp_start_int_reg[6] + (.C(clk), + .CE(det_v0fp_start_int), + .D(v_count_reg__0[6]), + .Q(\time_status_regs_int_reg[0] [6]), + .R(h_count1)); + FDRE \det_v0fp_start_int_reg[7] + (.C(clk), + .CE(det_v0fp_start_int), + .D(v_count_reg__0[7]), + .Q(\time_status_regs_int_reg[0] [7]), + .R(h_count1)); + FDRE \det_v0fp_start_int_reg[8] + (.C(clk), + .CE(det_v0fp_start_int), + .D(v_count_reg__0[8]), + .Q(\time_status_regs_int_reg[0] [8]), + .R(h_count1)); + FDRE \det_v0fp_start_int_reg[9] + (.C(clk), + .CE(det_v0fp_start_int), + .D(v_count_reg__0[9]), + .Q(\time_status_regs_int_reg[0] [9]), + .R(h_count1)); + FDRE \det_v0sync_start_hori_int2_reg[0] + (.C(clk), + .CE(det_ce), + .D(det_v0sync_start_hori_int2[0]), + .Q(\time_status_regs[9] [0]), + .R(reset)); + FDRE \det_v0sync_start_hori_int2_reg[10] + (.C(clk), + .CE(det_ce), + .D(det_v0sync_start_hori_int2[10]), + .Q(\time_status_regs[9] [10]), + .R(reset)); + FDRE \det_v0sync_start_hori_int2_reg[11] + (.C(clk), + .CE(det_ce), + .D(det_v0sync_start_hori_int2[11]), + .Q(\time_status_regs[9] [11]), + .R(reset)); + FDRE \det_v0sync_start_hori_int2_reg[1] + (.C(clk), + .CE(det_ce), + .D(det_v0sync_start_hori_int2[1]), + .Q(\time_status_regs[9] [1]), + .R(reset)); + FDRE \det_v0sync_start_hori_int2_reg[2] + (.C(clk), + .CE(det_ce), + .D(det_v0sync_start_hori_int2[2]), + .Q(\time_status_regs[9] [2]), + .R(reset)); + FDRE \det_v0sync_start_hori_int2_reg[3] + (.C(clk), + .CE(det_ce), + .D(det_v0sync_start_hori_int2[3]), + .Q(\time_status_regs[9] [3]), + .R(reset)); + FDRE \det_v0sync_start_hori_int2_reg[4] + (.C(clk), + .CE(det_ce), + .D(det_v0sync_start_hori_int2[4]), + .Q(\time_status_regs[9] [4]), + .R(reset)); + FDRE \det_v0sync_start_hori_int2_reg[5] + (.C(clk), + .CE(det_ce), + .D(det_v0sync_start_hori_int2[5]), + .Q(\time_status_regs[9] [5]), + .R(reset)); + FDRE \det_v0sync_start_hori_int2_reg[6] + (.C(clk), + .CE(det_ce), + .D(det_v0sync_start_hori_int2[6]), + .Q(\time_status_regs[9] [6]), + .R(reset)); + FDRE \det_v0sync_start_hori_int2_reg[7] + (.C(clk), + .CE(det_ce), + .D(det_v0sync_start_hori_int2[7]), + .Q(\time_status_regs[9] [7]), + .R(reset)); + FDRE \det_v0sync_start_hori_int2_reg[8] + (.C(clk), + .CE(det_ce), + .D(det_v0sync_start_hori_int2[8]), + .Q(\time_status_regs[9] [8]), + .R(reset)); + FDRE \det_v0sync_start_hori_int2_reg[9] + (.C(clk), + .CE(det_ce), + .D(det_v0sync_start_hori_int2[9]), + .Q(\time_status_regs[9] [9]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \det_v0sync_start_int2[10]_i_2 + (.I0(det_v0sync_start_int[10]), + .O(\det_v0sync_start_int2[10]_i_2_n_0 )); + LUT1 #( + .INIT(2'h1)) + \det_v0sync_start_int2[10]_i_3 + (.I0(det_v0sync_start_int[9]), + .O(\det_v0sync_start_int2[10]_i_3_n_0 )); + LUT1 #( + .INIT(2'h1)) + \det_v0sync_start_int2[10]_i_4 + (.I0(det_v0sync_start_int[8]), + .O(\det_v0sync_start_int2[10]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \det_v0sync_start_int2[3]_i_2 + (.I0(det_v0sync_start_int[3]), + .O(\det_v0sync_start_int2[3]_i_2_n_0 )); + LUT1 #( + .INIT(2'h1)) + \det_v0sync_start_int2[3]_i_3 + (.I0(det_v0sync_start_int[2]), + .O(\det_v0sync_start_int2[3]_i_3_n_0 )); + LUT1 #( + .INIT(2'h1)) + \det_v0sync_start_int2[3]_i_4 + (.I0(det_v0sync_start_int[1]), + .O(\det_v0sync_start_int2[3]_i_4_n_0 )); + LUT2 #( + .INIT(4'h9)) + \det_v0sync_start_int2[3]_i_5 + (.I0(det_v0sync_start_int[0]), + .I1(ltOp), + .O(\det_v0sync_start_int2[3]_i_5_n_0 )); + LUT1 #( + .INIT(2'h1)) + \det_v0sync_start_int2[7]_i_2 + (.I0(det_v0sync_start_int[7]), + .O(\det_v0sync_start_int2[7]_i_2_n_0 )); + LUT1 #( + .INIT(2'h1)) + \det_v0sync_start_int2[7]_i_3 + (.I0(det_v0sync_start_int[6]), + .O(\det_v0sync_start_int2[7]_i_3_n_0 )); + LUT1 #( + .INIT(2'h1)) + \det_v0sync_start_int2[7]_i_4 + (.I0(det_v0sync_start_int[5]), + .O(\det_v0sync_start_int2[7]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \det_v0sync_start_int2[7]_i_5 + (.I0(det_v0sync_start_int[4]), + .O(\det_v0sync_start_int2[7]_i_5_n_0 )); + FDRE \det_v0sync_start_int2_reg[0] + (.C(clk), + .CE(det_ce), + .D(det_v0sync_start_int2[0]), + .Q(\time_status_regs[8] [0]), + .R(reset)); + FDRE \det_v0sync_start_int2_reg[10] + (.C(clk), + .CE(det_ce), + .D(det_v0sync_start_int2[10]), + .Q(\time_status_regs[8] [10]), + .R(reset)); + CARRY4 \det_v0sync_start_int2_reg[10]_i_1 + (.CI(\det_v0sync_start_int2_reg[7]_i_1_n_0 ), + .CO({\NLW_det_v0sync_start_int2_reg[10]_i_1_CO_UNCONNECTED [3:2],\det_v0sync_start_int2_reg[10]_i_1_n_2 ,\det_v0sync_start_int2_reg[10]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,det_v0sync_start_int[9:8]}), + .O({\NLW_det_v0sync_start_int2_reg[10]_i_1_O_UNCONNECTED [3],det_v0sync_start_int2[10:8]}), + .S({1'b0,\det_v0sync_start_int2[10]_i_2_n_0 ,\det_v0sync_start_int2[10]_i_3_n_0 ,\det_v0sync_start_int2[10]_i_4_n_0 })); + FDRE \det_v0sync_start_int2_reg[1] + (.C(clk), + .CE(det_ce), + .D(det_v0sync_start_int2[1]), + .Q(\time_status_regs[8] [1]), + .R(reset)); + FDRE \det_v0sync_start_int2_reg[2] + (.C(clk), + .CE(det_ce), + .D(det_v0sync_start_int2[2]), + .Q(\time_status_regs[8] [2]), + .R(reset)); + FDRE \det_v0sync_start_int2_reg[3] + (.C(clk), + .CE(det_ce), + .D(det_v0sync_start_int2[3]), + .Q(\time_status_regs[8] [3]), + .R(reset)); + CARRY4 \det_v0sync_start_int2_reg[3]_i_1 + (.CI(1'b0), + .CO({\det_v0sync_start_int2_reg[3]_i_1_n_0 ,\det_v0sync_start_int2_reg[3]_i_1_n_1 ,\det_v0sync_start_int2_reg[3]_i_1_n_2 ,\det_v0sync_start_int2_reg[3]_i_1_n_3 }), + .CYINIT(1'b1), + .DI(det_v0sync_start_int[3:0]), + .O(det_v0sync_start_int2[3:0]), + .S({\det_v0sync_start_int2[3]_i_2_n_0 ,\det_v0sync_start_int2[3]_i_3_n_0 ,\det_v0sync_start_int2[3]_i_4_n_0 ,\det_v0sync_start_int2[3]_i_5_n_0 })); + FDRE \det_v0sync_start_int2_reg[4] + (.C(clk), + .CE(det_ce), + .D(det_v0sync_start_int2[4]), + .Q(\time_status_regs[8] [4]), + .R(reset)); + FDRE \det_v0sync_start_int2_reg[5] + (.C(clk), + .CE(det_ce), + .D(det_v0sync_start_int2[5]), + .Q(\time_status_regs[8] [5]), + .R(reset)); + FDRE \det_v0sync_start_int2_reg[6] + (.C(clk), + .CE(det_ce), + .D(det_v0sync_start_int2[6]), + .Q(\time_status_regs[8] [6]), + .R(reset)); + FDRE \det_v0sync_start_int2_reg[7] + (.C(clk), + .CE(det_ce), + .D(det_v0sync_start_int2[7]), + .Q(\time_status_regs[8] [7]), + .R(reset)); + CARRY4 \det_v0sync_start_int2_reg[7]_i_1 + (.CI(\det_v0sync_start_int2_reg[3]_i_1_n_0 ), + .CO({\det_v0sync_start_int2_reg[7]_i_1_n_0 ,\det_v0sync_start_int2_reg[7]_i_1_n_1 ,\det_v0sync_start_int2_reg[7]_i_1_n_2 ,\det_v0sync_start_int2_reg[7]_i_1_n_3 }), + .CYINIT(1'b0), + .DI(det_v0sync_start_int[7:4]), + .O(det_v0sync_start_int2[7:4]), + .S({\det_v0sync_start_int2[7]_i_2_n_0 ,\det_v0sync_start_int2[7]_i_3_n_0 ,\det_v0sync_start_int2[7]_i_4_n_0 ,\det_v0sync_start_int2[7]_i_5_n_0 })); + FDRE \det_v0sync_start_int2_reg[8] + (.C(clk), + .CE(det_ce), + .D(det_v0sync_start_int2[8]), + .Q(\time_status_regs[8] [8]), + .R(reset)); + FDRE \det_v0sync_start_int2_reg[9] + (.C(clk), + .CE(det_ce), + .D(det_v0sync_start_int2[9]), + .Q(\time_status_regs[8] [9]), + .R(reset)); + LUT1 #( + .INIT(2'h1)) + \det_v0total[0]_i_1 + (.I0(det_v0total_int[0]), + .O(\det_v0total[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h7FFFFFFF80000000)) + \det_v0total[10]_i_1 + (.I0(det_v0total_int[8]), + .I1(det_v0total_int[6]), + .I2(\det_v0total[10]_i_2_n_0 ), + .I3(det_v0total_int[7]), + .I4(det_v0total_int[9]), + .I5(det_v0total_int[10]), + .O(\det_v0total[10]_i_1_n_0 )); + LUT6 #( + .INIT(64'h8000000000000000)) + \det_v0total[10]_i_2 + (.I0(det_v0total_int[5]), + .I1(det_v0total_int[3]), + .I2(det_v0total_int[1]), + .I3(det_v0total_int[0]), + .I4(det_v0total_int[2]), + .I5(det_v0total_int[4]), + .O(\det_v0total[10]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair293" *) + LUT2 #( + .INIT(4'h6)) + \det_v0total[1]_i_1 + (.I0(det_v0total_int[0]), + .I1(det_v0total_int[1]), + .O(\det_v0total[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair293" *) + LUT3 #( + .INIT(8'h78)) + \det_v0total[2]_i_1 + (.I0(det_v0total_int[0]), + .I1(det_v0total_int[1]), + .I2(det_v0total_int[2]), + .O(\det_v0total[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair274" *) + LUT4 #( + .INIT(16'h7F80)) + \det_v0total[3]_i_1 + (.I0(det_v0total_int[1]), + .I1(det_v0total_int[0]), + .I2(det_v0total_int[2]), + .I3(det_v0total_int[3]), + .O(\det_v0total[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair274" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \det_v0total[4]_i_1 + (.I0(det_v0total_int[2]), + .I1(det_v0total_int[0]), + .I2(det_v0total_int[1]), + .I3(det_v0total_int[3]), + .I4(det_v0total_int[4]), + .O(\det_v0total[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'h7FFFFFFF80000000)) + \det_v0total[5]_i_1 + (.I0(det_v0total_int[3]), + .I1(det_v0total_int[1]), + .I2(det_v0total_int[0]), + .I3(det_v0total_int[2]), + .I4(det_v0total_int[4]), + .I5(det_v0total_int[5]), + .O(\det_v0total[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair281" *) + LUT2 #( + .INIT(4'h6)) + \det_v0total[6]_i_1 + (.I0(\det_v0total[10]_i_2_n_0 ), + .I1(det_v0total_int[6]), + .O(\det_v0total[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair281" *) + LUT3 #( + .INIT(8'h78)) + \det_v0total[7]_i_1 + (.I0(\det_v0total[10]_i_2_n_0 ), + .I1(det_v0total_int[6]), + .I2(det_v0total_int[7]), + .O(\det_v0total[7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair272" *) + LUT4 #( + .INIT(16'h7F80)) + \det_v0total[8]_i_1 + (.I0(det_v0total_int[6]), + .I1(\det_v0total[10]_i_2_n_0 ), + .I2(det_v0total_int[7]), + .I3(det_v0total_int[8]), + .O(\det_v0total[8]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair272" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \det_v0total[9]_i_1 + (.I0(det_v0total_int[7]), + .I1(\det_v0total[10]_i_2_n_0 ), + .I2(det_v0total_int[6]), + .I3(det_v0total_int[8]), + .I4(det_v0total_int[9]), + .O(\det_v0total[9]_i_1_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \det_v0total_int[0]_i_1 + (.I0(v_count_reg__0[0]), + .I1(gtOp_0), + .I2(v_count_last[0]), + .O(\det_v0total_int[0]_i_1_n_0 )); + LUT5 #( + .INIT(32'h00008200)) + \det_v0total_int[10]_i_1 + (.I0(det_ce), + .I1(active_video_in), + .I2(\time_status_regs[3] [2]), + .I3(top_of_frame_reg_n_0), + .I4(frame_end_d), + .O(det_v0total_int_5)); + (* SOFT_HLUTNM = "soft_lutpair282" *) + LUT3 #( + .INIT(8'hB8)) + \det_v0total_int[10]_i_2 + (.I0(v_count_reg__0[10]), + .I1(gtOp_0), + .I2(v_count_last[10]), + .O(\det_v0total_int[10]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair282" *) + LUT3 #( + .INIT(8'hB8)) + \det_v0total_int[1]_i_1 + (.I0(v_count_reg__0[1]), + .I1(gtOp_0), + .I2(v_count_last[1]), + .O(\det_v0total_int[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair286" *) + LUT3 #( + .INIT(8'hB8)) + \det_v0total_int[2]_i_1 + (.I0(v_count_reg__0[2]), + .I1(gtOp_0), + .I2(v_count_last[2]), + .O(\det_v0total_int[2]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair286" *) + LUT3 #( + .INIT(8'hB8)) + \det_v0total_int[3]_i_1 + (.I0(v_count_reg__0[3]), + .I1(gtOp_0), + .I2(v_count_last[3]), + .O(\det_v0total_int[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair283" *) + LUT3 #( + .INIT(8'hB8)) + \det_v0total_int[4]_i_1 + (.I0(v_count_reg__0[4]), + .I1(gtOp_0), + .I2(v_count_last[4]), + .O(\det_v0total_int[4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair285" *) + LUT3 #( + .INIT(8'hB8)) + \det_v0total_int[5]_i_1 + (.I0(v_count_reg__0[5]), + .I1(gtOp_0), + .I2(v_count_last[5]), + .O(\det_v0total_int[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair284" *) + LUT3 #( + .INIT(8'hB8)) + \det_v0total_int[6]_i_1 + (.I0(v_count_reg__0[6]), + .I1(gtOp_0), + .I2(v_count_last[6]), + .O(\det_v0total_int[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair285" *) + LUT3 #( + .INIT(8'hB8)) + \det_v0total_int[7]_i_1 + (.I0(v_count_reg__0[7]), + .I1(gtOp_0), + .I2(v_count_last[7]), + .O(\det_v0total_int[7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair284" *) + LUT3 #( + .INIT(8'hB8)) + \det_v0total_int[8]_i_1 + (.I0(v_count_reg__0[8]), + .I1(gtOp_0), + .I2(v_count_last[8]), + .O(\det_v0total_int[8]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair283" *) + LUT3 #( + .INIT(8'hB8)) + \det_v0total_int[9]_i_1 + (.I0(v_count_reg__0[9]), + .I1(gtOp_0), + .I2(v_count_last[9]), + .O(\det_v0total_int[9]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \det_v0total_int_reg[0] + (.C(clk), + .CE(det_v0total_int_5), + .D(\det_v0total_int[0]_i_1_n_0 ), + .Q(det_v0total_int[0]), + .R(h_count1)); + FDRE #( + .INIT(1'b0)) + \det_v0total_int_reg[10] + (.C(clk), + .CE(det_v0total_int_5), + .D(\det_v0total_int[10]_i_2_n_0 ), + .Q(det_v0total_int[10]), + .R(h_count1)); + FDRE #( + .INIT(1'b0)) + \det_v0total_int_reg[1] + (.C(clk), + .CE(det_v0total_int_5), + .D(\det_v0total_int[1]_i_1_n_0 ), + .Q(det_v0total_int[1]), + .R(h_count1)); + FDRE #( + .INIT(1'b0)) + \det_v0total_int_reg[2] + (.C(clk), + .CE(det_v0total_int_5), + .D(\det_v0total_int[2]_i_1_n_0 ), + .Q(det_v0total_int[2]), + .R(h_count1)); + FDRE #( + .INIT(1'b0)) + \det_v0total_int_reg[3] + (.C(clk), + .CE(det_v0total_int_5), + .D(\det_v0total_int[3]_i_1_n_0 ), + .Q(det_v0total_int[3]), + .R(h_count1)); + FDRE #( + .INIT(1'b0)) + \det_v0total_int_reg[4] + (.C(clk), + .CE(det_v0total_int_5), + .D(\det_v0total_int[4]_i_1_n_0 ), + .Q(det_v0total_int[4]), + .R(h_count1)); + FDRE #( + .INIT(1'b0)) + \det_v0total_int_reg[5] + (.C(clk), + .CE(det_v0total_int_5), + .D(\det_v0total_int[5]_i_1_n_0 ), + .Q(det_v0total_int[5]), + .R(h_count1)); + FDRE #( + .INIT(1'b0)) + \det_v0total_int_reg[6] + (.C(clk), + .CE(det_v0total_int_5), + .D(\det_v0total_int[6]_i_1_n_0 ), + .Q(det_v0total_int[6]), + .R(h_count1)); + FDRE #( + .INIT(1'b0)) + \det_v0total_int_reg[7] + (.C(clk), + .CE(det_v0total_int_5), + .D(\det_v0total_int[7]_i_1_n_0 ), + .Q(det_v0total_int[7]), + .R(h_count1)); + FDRE #( + .INIT(1'b0)) + \det_v0total_int_reg[8] + (.C(clk), + .CE(det_v0total_int_5), + .D(\det_v0total_int[8]_i_1_n_0 ), + .Q(det_v0total_int[8]), + .R(h_count1)); + FDRE #( + .INIT(1'b0)) + \det_v0total_int_reg[9] + (.C(clk), + .CE(det_v0total_int_5), + .D(\det_v0total_int[9]_i_1_n_0 ), + .Q(det_v0total_int[9]), + .R(h_count1)); + FDRE \det_v0total_reg[0] + (.C(clk), + .CE(det_ce), + .D(\det_v0total[0]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10] [0]), + .R(reset)); + FDRE \det_v0total_reg[10] + (.C(clk), + .CE(det_ce), + .D(\det_v0total[10]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10] [10]), + .R(reset)); + FDRE \det_v0total_reg[1] + (.C(clk), + .CE(det_ce), + .D(\det_v0total[1]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10] [1]), + .R(reset)); + FDRE \det_v0total_reg[2] + (.C(clk), + .CE(det_ce), + .D(\det_v0total[2]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10] [2]), + .R(reset)); + FDRE \det_v0total_reg[3] + (.C(clk), + .CE(det_ce), + .D(\det_v0total[3]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10] [3]), + .R(reset)); + FDRE \det_v0total_reg[4] + (.C(clk), + .CE(det_ce), + .D(\det_v0total[4]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10] [4]), + .R(reset)); + FDRE \det_v0total_reg[5] + (.C(clk), + .CE(det_ce), + .D(\det_v0total[5]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10] [5]), + .R(reset)); + FDRE \det_v0total_reg[6] + (.C(clk), + .CE(det_ce), + .D(\det_v0total[6]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10] [6]), + .R(reset)); + FDRE \det_v0total_reg[7] + (.C(clk), + .CE(det_ce), + .D(\det_v0total[7]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10] [7]), + .R(reset)); + FDRE \det_v0total_reg[8] + (.C(clk), + .CE(det_ce), + .D(\det_v0total[8]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10] [8]), + .R(reset)); + FDRE \det_v0total_reg[9] + (.C(clk), + .CE(det_ce), + .D(\det_v0total[9]_i_1_n_0 ), + .Q(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10] [9]), + .R(reset)); + LUT6 #( + .INIT(64'h0000000000EAAAAA)) + found_eof_i_1 + (.I0(found_eof_reg_n_0), + .I1(gtOp_0), + .I2(p_0_in16_in), + .I3(h_count0__0), + .I4(det_ce), + .I5(h_count1), + .O(found_eof_i_1_n_0)); + FDRE found_eof_reg + (.C(clk), + .CE(1'b1), + .D(found_eof_i_1_n_0), + .Q(found_eof_reg_n_0), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair279" *) + LUT3 #( + .INIT(8'h90)) + frame_end_d_i_1 + (.I0(\time_status_regs[3] [2]), + .I1(active_video_in), + .I2(top_of_frame_reg_n_0), + .O(frame_end)); + FDRE frame_end_d_reg + (.C(clk), + .CE(1'b1), + .D(frame_end), + .Q(frame_end_d), + .R(1'b0)); + CARRY4 gtOp_carry + (.CI(1'b0), + .CO({gtOp_carry_n_0,gtOp_carry_n_1,gtOp_carry_n_2,gtOp_carry_n_3}), + .CYINIT(1'b0), + .DI({gtOp_carry_i_1_n_0,gtOp_carry_i_2_n_0,gtOp_carry_i_3_n_0,gtOp_carry_i_4_n_0}), + .O(NLW_gtOp_carry_O_UNCONNECTED[3:0]), + .S({gtOp_carry_i_5_n_0,gtOp_carry_i_6_n_0,gtOp_carry_i_7_n_0,gtOp_carry_i_8_n_0})); + CARRY4 gtOp_carry__0 + (.CI(gtOp_carry_n_0), + .CO({NLW_gtOp_carry__0_CO_UNCONNECTED[3],gtOp,gtOp_carry__0_n_2,gtOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({1'b0,\DET_HSYNC.hsync_count_reg [11],gtOp_carry__0_i_1_n_0,gtOp_carry__0_i_2_n_0}), + .O(NLW_gtOp_carry__0_O_UNCONNECTED[3:0]), + .S({1'b0,gtOp_carry__0_i_3_n_0,gtOp_carry__0_i_4_n_0,gtOp_carry__0_i_5_n_0})); + LUT4 #( + .INIT(16'h2F02)) + gtOp_carry__0_i_1 + (.I0(\DET_HSYNC.hsync_count_reg [9]), + .I1(det_htotal_int[10]), + .I2(det_htotal_int[11]), + .I3(\DET_HSYNC.hsync_count_reg [10]), + .O(gtOp_carry__0_i_1_n_0)); + LUT4 #( + .INIT(16'h2F02)) + gtOp_carry__0_i_2 + (.I0(\DET_HSYNC.hsync_count_reg [7]), + .I1(det_htotal_int[8]), + .I2(det_htotal_int[9]), + .I3(\DET_HSYNC.hsync_count_reg [8]), + .O(gtOp_carry__0_i_2_n_0)); + LUT1 #( + .INIT(2'h1)) + gtOp_carry__0_i_3 + (.I0(\DET_HSYNC.hsync_count_reg [11]), + .O(gtOp_carry__0_i_3_n_0)); + LUT4 #( + .INIT(16'h9009)) + gtOp_carry__0_i_4 + (.I0(det_htotal_int[11]), + .I1(\DET_HSYNC.hsync_count_reg [10]), + .I2(det_htotal_int[10]), + .I3(\DET_HSYNC.hsync_count_reg [9]), + .O(gtOp_carry__0_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + gtOp_carry__0_i_5 + (.I0(det_htotal_int[9]), + .I1(\DET_HSYNC.hsync_count_reg [8]), + .I2(det_htotal_int[8]), + .I3(\DET_HSYNC.hsync_count_reg [7]), + .O(gtOp_carry__0_i_5_n_0)); + LUT4 #( + .INIT(16'h2F02)) + gtOp_carry_i_1 + (.I0(\DET_HSYNC.hsync_count_reg [5]), + .I1(det_htotal_int[6]), + .I2(det_htotal_int[7]), + .I3(\DET_HSYNC.hsync_count_reg [6]), + .O(gtOp_carry_i_1_n_0)); + LUT4 #( + .INIT(16'h2F02)) + gtOp_carry_i_2 + (.I0(\DET_HSYNC.hsync_count_reg [3]), + .I1(det_htotal_int[4]), + .I2(det_htotal_int[5]), + .I3(\DET_HSYNC.hsync_count_reg [4]), + .O(gtOp_carry_i_2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + gtOp_carry_i_3 + (.I0(\DET_HSYNC.hsync_count_reg [1]), + .I1(det_htotal_int[2]), + .I2(det_htotal_int[3]), + .I3(\DET_HSYNC.hsync_count_reg [2]), + .O(gtOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'h2)) + gtOp_carry_i_4 + (.I0(\DET_HSYNC.hsync_count_reg [0]), + .I1(det_htotal_int[1]), + .O(gtOp_carry_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + gtOp_carry_i_5 + (.I0(det_htotal_int[7]), + .I1(\DET_HSYNC.hsync_count_reg [6]), + .I2(det_htotal_int[6]), + .I3(\DET_HSYNC.hsync_count_reg [5]), + .O(gtOp_carry_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + gtOp_carry_i_6 + (.I0(det_htotal_int[5]), + .I1(\DET_HSYNC.hsync_count_reg [4]), + .I2(det_htotal_int[4]), + .I3(\DET_HSYNC.hsync_count_reg [3]), + .O(gtOp_carry_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + gtOp_carry_i_7 + (.I0(det_htotal_int[3]), + .I1(\DET_HSYNC.hsync_count_reg [2]), + .I2(det_htotal_int[2]), + .I3(\DET_HSYNC.hsync_count_reg [1]), + .O(gtOp_carry_i_7_n_0)); + LUT3 #( + .INIT(8'h41)) + gtOp_carry_i_8 + (.I0(det_htotal_int[0]), + .I1(det_htotal_int[1]), + .I2(\DET_HSYNC.hsync_count_reg [0]), + .O(gtOp_carry_i_8_n_0)); + CARRY4 \gtOp_inferred__0/i__carry + (.CI(1'b0), + .CO({\gtOp_inferred__0/i__carry_n_0 ,\gtOp_inferred__0/i__carry_n_1 ,\gtOp_inferred__0/i__carry_n_2 ,\gtOp_inferred__0/i__carry_n_3 }), + .CYINIT(1'b0), + .DI({i__carry_i_1_n_0,i__carry_i_2_n_0,i__carry_i_3_n_0,i__carry_i_4_n_0}), + .O(\NLW_gtOp_inferred__0/i__carry_O_UNCONNECTED [3:0]), + .S({i__carry_i_5__2_n_0,i__carry_i_6__2_n_0,i__carry_i_7__2_n_0,i__carry_i_8__2_n_0})); + CARRY4 \gtOp_inferred__0/i__carry__0 + (.CI(\gtOp_inferred__0/i__carry_n_0 ), + .CO({\NLW_gtOp_inferred__0/i__carry__0_CO_UNCONNECTED [3],gtOp_0,\gtOp_inferred__0/i__carry__0_n_2 ,\gtOp_inferred__0/i__carry__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,L[0],i__carry__0_i_1_n_0,i__carry__0_i_2_n_0}), + .O(\NLW_gtOp_inferred__0/i__carry__0_O_UNCONNECTED [3:0]), + .S({1'b0,i__carry__0_i_3__2_n_0,i__carry__0_i_4__2_n_0,i__carry__0_i_5__0_n_0})); + CARRY4 \gtOp_inferred__2/i__carry + (.CI(1'b0), + .CO({\gtOp_inferred__2/i__carry_n_0 ,\gtOp_inferred__2/i__carry_n_1 ,\gtOp_inferred__2/i__carry_n_2 ,\gtOp_inferred__2/i__carry_n_3 }), + .CYINIT(1'b0), + .DI({i__carry_i_1__1_n_0,i__carry_i_2__1_n_0,i__carry_i_3__1_n_0,i__carry_i_4__1_n_0}), + .O(\NLW_gtOp_inferred__2/i__carry_O_UNCONNECTED [3:0]), + .S({i__carry_i_5__0_n_0,i__carry_i_6__0_n_0,i__carry_i_7__0_n_0,i__carry_i_8__0_n_0})); + CARRY4 \gtOp_inferred__2/i__carry__0 + (.CI(\gtOp_inferred__2/i__carry_n_0 ), + .CO({\NLW_gtOp_inferred__2/i__carry__0_CO_UNCONNECTED [3:2],gtOp29_in,\gtOp_inferred__2/i__carry__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,i__carry__0_i_1__1_n_0,i__carry__0_i_2__1_n_0}), + .O(\NLW_gtOp_inferred__2/i__carry__0_O_UNCONNECTED [3:0]), + .S({1'b0,1'b0,i__carry__0_i_3_n_0,i__carry__0_i_4__0_n_0})); + LUT5 #( + .INIT(32'hAAEBAAAA)) + \h_count[0]_i_1 + (.I0(h_count1), + .I1(\time_status_regs[3] [1]), + .I2(hsync_in), + .I3(line_end_d_reg_n_0), + .I4(det_ce), + .O(\h_count[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAAA2AAAAAAA)) + \h_count[0]_i_2 + (.I0(det_ce), + .I1(L[11]), + .I2(L[10]), + .I3(L[9]), + .I4(L[8]), + .I5(\h_count[0]_i_4_n_0 ), + .O(h_count)); + LUT5 #( + .INIT(32'hFFFF7FFF)) + \h_count[0]_i_4 + (.I0(L[4]), + .I1(L[5]), + .I2(L[6]), + .I3(L[7]), + .I4(\h_count[0]_i_9_n_0 ), + .O(\h_count[0]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \h_count[0]_i_5 + (.I0(L[8]), + .O(\h_count[0]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \h_count[0]_i_6 + (.I0(L[9]), + .O(\h_count[0]_i_6_n_0 )); + LUT1 #( + .INIT(2'h2)) + \h_count[0]_i_7 + (.I0(L[10]), + .O(\h_count[0]_i_7_n_0 )); + LUT1 #( + .INIT(2'h1)) + \h_count[0]_i_8 + (.I0(L[11]), + .O(\h_count[0]_i_8_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair278" *) + LUT4 #( + .INIT(16'h7FFF)) + \h_count[0]_i_9 + (.I0(L[3]), + .I1(L[2]), + .I2(L[0]), + .I3(L[1]), + .O(\h_count[0]_i_9_n_0 )); + LUT1 #( + .INIT(2'h2)) + \h_count[4]_i_2 + (.I0(L[4]), + .O(\h_count[4]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \h_count[4]_i_3 + (.I0(L[5]), + .O(\h_count[4]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \h_count[4]_i_4 + (.I0(L[6]), + .O(\h_count[4]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \h_count[4]_i_5 + (.I0(L[7]), + .O(\h_count[4]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \h_count[8]_i_2 + (.I0(L[0]), + .O(\h_count[8]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \h_count[8]_i_3 + (.I0(L[1]), + .O(\h_count[8]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \h_count[8]_i_4 + (.I0(L[2]), + .O(\h_count[8]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \h_count[8]_i_5 + (.I0(L[3]), + .O(\h_count[8]_i_5_n_0 )); + FDRE #( + .INIT(1'b0)) + \h_count_reg[0] + (.C(clk), + .CE(h_count), + .D(\h_count_reg[0]_i_3_n_7 ), + .Q(L[11]), + .R(\h_count[0]_i_1_n_0 )); + CARRY4 \h_count_reg[0]_i_3 + (.CI(1'b0), + .CO({\h_count_reg[0]_i_3_n_0 ,\h_count_reg[0]_i_3_n_1 ,\h_count_reg[0]_i_3_n_2 ,\h_count_reg[0]_i_3_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\h_count_reg[0]_i_3_n_4 ,\h_count_reg[0]_i_3_n_5 ,\h_count_reg[0]_i_3_n_6 ,\h_count_reg[0]_i_3_n_7 }), + .S({\h_count[0]_i_5_n_0 ,\h_count[0]_i_6_n_0 ,\h_count[0]_i_7_n_0 ,\h_count[0]_i_8_n_0 })); + FDRE #( + .INIT(1'b0)) + \h_count_reg[10] + (.C(clk), + .CE(h_count), + .D(\h_count_reg[8]_i_1_n_5 ), + .Q(L[1]), + .R(\h_count[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \h_count_reg[11] + (.C(clk), + .CE(h_count), + .D(\h_count_reg[8]_i_1_n_4 ), + .Q(L[0]), + .R(\h_count[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \h_count_reg[1] + (.C(clk), + .CE(h_count), + .D(\h_count_reg[0]_i_3_n_6 ), + .Q(L[10]), + .R(\h_count[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \h_count_reg[2] + (.C(clk), + .CE(h_count), + .D(\h_count_reg[0]_i_3_n_5 ), + .Q(L[9]), + .R(\h_count[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \h_count_reg[3] + (.C(clk), + .CE(h_count), + .D(\h_count_reg[0]_i_3_n_4 ), + .Q(L[8]), + .R(\h_count[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \h_count_reg[4] + (.C(clk), + .CE(h_count), + .D(\h_count_reg[4]_i_1_n_7 ), + .Q(L[7]), + .R(\h_count[0]_i_1_n_0 )); + CARRY4 \h_count_reg[4]_i_1 + (.CI(\h_count_reg[0]_i_3_n_0 ), + .CO({\h_count_reg[4]_i_1_n_0 ,\h_count_reg[4]_i_1_n_1 ,\h_count_reg[4]_i_1_n_2 ,\h_count_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\h_count_reg[4]_i_1_n_4 ,\h_count_reg[4]_i_1_n_5 ,\h_count_reg[4]_i_1_n_6 ,\h_count_reg[4]_i_1_n_7 }), + .S({\h_count[4]_i_2_n_0 ,\h_count[4]_i_3_n_0 ,\h_count[4]_i_4_n_0 ,\h_count[4]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \h_count_reg[5] + (.C(clk), + .CE(h_count), + .D(\h_count_reg[4]_i_1_n_6 ), + .Q(L[6]), + .R(\h_count[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \h_count_reg[6] + (.C(clk), + .CE(h_count), + .D(\h_count_reg[4]_i_1_n_5 ), + .Q(L[5]), + .R(\h_count[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \h_count_reg[7] + (.C(clk), + .CE(h_count), + .D(\h_count_reg[4]_i_1_n_4 ), + .Q(L[4]), + .R(\h_count[0]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \h_count_reg[8] + (.C(clk), + .CE(h_count), + .D(\h_count_reg[8]_i_1_n_7 ), + .Q(L[3]), + .R(\h_count[0]_i_1_n_0 )); + CARRY4 \h_count_reg[8]_i_1 + (.CI(\h_count_reg[4]_i_1_n_0 ), + .CO({\NLW_h_count_reg[8]_i_1_CO_UNCONNECTED [3],\h_count_reg[8]_i_1_n_1 ,\h_count_reg[8]_i_1_n_2 ,\h_count_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\h_count_reg[8]_i_1_n_4 ,\h_count_reg[8]_i_1_n_5 ,\h_count_reg[8]_i_1_n_6 ,\h_count_reg[8]_i_1_n_7 }), + .S({\h_count[8]_i_2_n_0 ,\h_count[8]_i_3_n_0 ,\h_count[8]_i_4_n_0 ,\h_count[8]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \h_count_reg[9] + (.C(clk), + .CE(h_count), + .D(\h_count_reg[8]_i_1_n_6 ), + .Q(L[2]), + .R(\h_count[0]_i_1_n_0 )); + LUT4 #( + .INIT(16'h2F02)) + i__carry__0_i_1 + (.I0(L[2]), + .I1(det_htotal_int[10]), + .I2(det_htotal_int[11]), + .I3(L[1]), + .O(i__carry__0_i_1_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry__0_i_1__0 + (.I0(det_htotal_int[10]), + .I1(L[2]), + .I2(L[1]), + .I3(det_htotal_int[11]), + .O(i__carry__0_i_1__0_n_0)); + LUT3 #( + .INIT(8'hF4)) + i__carry__0_i_1__1 + (.I0(det_v0total_int[10]), + .I1(\DET_VSYNC.vsync_count_reg__0 [9]), + .I2(\DET_VSYNC.vsync_count_reg__0 [10]), + .O(i__carry__0_i_1__1_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry__0_i_1__2 + (.I0(det_hactive_start_int[10]), + .I1(det_v0bp_start_hori_int[10]), + .I2(det_v0bp_start_hori_int[11]), + .I3(det_hactive_start_int[11]), + .O(i__carry__0_i_1__2_n_0)); + LUT2 #( + .INIT(4'h6)) + i__carry__0_i_1__3 + (.I0(\time_status_regs[6] [7]), + .I1(det_hbp_start_int[7]), + .O(i__carry__0_i_1__3_n_0)); + LUT4 #( + .INIT(16'h2ED1)) + i__carry__0_i_1__4 + (.I0(det_hactive_start_int[7]), + .I1(ltOp), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [7]), + .I3(det_v0sync_start_hori_int[7]), + .O(i__carry__0_i_1__4_n_0)); + LUT4 #( + .INIT(16'h2ED1)) + i__carry__0_i_1__5 + (.I0(det_hactive_start_int[7]), + .I1(\ltOp_inferred__0/i__carry__0_n_2 ), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [7]), + .I3(det_v0bp_start_hori_int[7]), + .O(i__carry__0_i_1__5_n_0)); + LUT2 #( + .INIT(4'h9)) + i__carry__0_i_1__6 + (.I0(Q[7]), + .I1(det_hactive_start_int[7]), + .O(i__carry__0_i_1__6_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry__0_i_2 + (.I0(L[4]), + .I1(det_htotal_int[8]), + .I2(det_htotal_int[9]), + .I3(L[3]), + .O(i__carry__0_i_2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry__0_i_2__0 + (.I0(det_htotal_int[8]), + .I1(L[4]), + .I2(L[3]), + .I3(det_htotal_int[9]), + .O(i__carry__0_i_2__0_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry__0_i_2__1 + (.I0(\DET_VSYNC.vsync_count_reg__0 [7]), + .I1(det_v0total_int[8]), + .I2(det_v0total_int[9]), + .I3(\DET_VSYNC.vsync_count_reg__0 [8]), + .O(i__carry__0_i_2__1_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry__0_i_2__2 + (.I0(det_hactive_start_int[8]), + .I1(det_v0bp_start_hori_int[8]), + .I2(det_v0bp_start_hori_int[9]), + .I3(det_hactive_start_int[9]), + .O(i__carry__0_i_2__2_n_0)); + LUT2 #( + .INIT(4'h6)) + i__carry__0_i_2__3 + (.I0(\time_status_regs[6] [6]), + .I1(det_hbp_start_int[6]), + .O(i__carry__0_i_2__3_n_0)); + LUT4 #( + .INIT(16'h2ED1)) + i__carry__0_i_2__4 + (.I0(det_hactive_start_int[6]), + .I1(ltOp), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [6]), + .I3(det_v0sync_start_hori_int[6]), + .O(i__carry__0_i_2__4_n_0)); + LUT4 #( + .INIT(16'h2ED1)) + i__carry__0_i_2__5 + (.I0(det_hactive_start_int[6]), + .I1(\ltOp_inferred__0/i__carry__0_n_2 ), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [6]), + .I3(det_v0bp_start_hori_int[6]), + .O(i__carry__0_i_2__5_n_0)); + LUT2 #( + .INIT(4'h9)) + i__carry__0_i_2__6 + (.I0(Q[6]), + .I1(det_hactive_start_int[6]), + .O(i__carry__0_i_2__6_n_0)); + LUT3 #( + .INIT(8'h09)) + i__carry__0_i_3 + (.I0(det_v0total_int[10]), + .I1(\DET_VSYNC.vsync_count_reg__0 [9]), + .I2(\DET_VSYNC.vsync_count_reg__0 [10]), + .O(i__carry__0_i_3_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry__0_i_3__0 + (.I0(det_v0bp_start_hori_int[11]), + .I1(det_hactive_start_int[11]), + .I2(det_v0bp_start_hori_int[10]), + .I3(det_hactive_start_int[10]), + .O(i__carry__0_i_3__0_n_0)); + LUT1 #( + .INIT(2'h1)) + i__carry__0_i_3__1 + (.I0(L[0]), + .O(i__carry__0_i_3__1_n_0)); + LUT1 #( + .INIT(2'h1)) + i__carry__0_i_3__2 + (.I0(L[0]), + .O(i__carry__0_i_3__2_n_0)); + LUT2 #( + .INIT(4'h6)) + i__carry__0_i_3__3 + (.I0(\time_status_regs[6] [5]), + .I1(det_hbp_start_int[5]), + .O(i__carry__0_i_3__3_n_0)); + LUT4 #( + .INIT(16'h2ED1)) + i__carry__0_i_3__4 + (.I0(det_hactive_start_int[5]), + .I1(ltOp), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [5]), + .I3(det_v0sync_start_hori_int[5]), + .O(i__carry__0_i_3__4_n_0)); + LUT4 #( + .INIT(16'h2ED1)) + i__carry__0_i_3__5 + (.I0(det_hactive_start_int[5]), + .I1(\ltOp_inferred__0/i__carry__0_n_2 ), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [5]), + .I3(det_v0bp_start_hori_int[5]), + .O(i__carry__0_i_3__5_n_0)); + LUT2 #( + .INIT(4'h9)) + i__carry__0_i_3__6 + (.I0(Q[5]), + .I1(det_hactive_start_int[5]), + .O(i__carry__0_i_3__6_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry__0_i_4 + (.I0(det_htotal_int[10]), + .I1(L[2]), + .I2(det_htotal_int[11]), + .I3(L[1]), + .O(i__carry__0_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry__0_i_4__0 + (.I0(det_v0total_int[9]), + .I1(\DET_VSYNC.vsync_count_reg__0 [8]), + .I2(det_v0total_int[8]), + .I3(\DET_VSYNC.vsync_count_reg__0 [7]), + .O(i__carry__0_i_4__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry__0_i_4__1 + (.I0(det_v0bp_start_hori_int[9]), + .I1(det_hactive_start_int[9]), + .I2(det_v0bp_start_hori_int[8]), + .I3(det_hactive_start_int[8]), + .O(i__carry__0_i_4__1_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry__0_i_4__2 + (.I0(det_htotal_int[10]), + .I1(L[2]), + .I2(det_htotal_int[11]), + .I3(L[1]), + .O(i__carry__0_i_4__2_n_0)); + LUT2 #( + .INIT(4'h6)) + i__carry__0_i_4__3 + (.I0(\time_status_regs[6] [4]), + .I1(det_hbp_start_int[4]), + .O(i__carry__0_i_4__3_n_0)); + LUT4 #( + .INIT(16'h2ED1)) + i__carry__0_i_4__4 + (.I0(det_hactive_start_int[4]), + .I1(ltOp), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [4]), + .I3(det_v0sync_start_hori_int[4]), + .O(i__carry__0_i_4__4_n_0)); + LUT4 #( + .INIT(16'h2ED1)) + i__carry__0_i_4__5 + (.I0(det_hactive_start_int[4]), + .I1(\ltOp_inferred__0/i__carry__0_n_2 ), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [4]), + .I3(det_v0bp_start_hori_int[4]), + .O(i__carry__0_i_4__5_n_0)); + LUT2 #( + .INIT(4'h9)) + i__carry__0_i_4__6 + (.I0(Q[4]), + .I1(det_hactive_start_int[4]), + .O(i__carry__0_i_4__6_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry__0_i_5 + (.I0(det_htotal_int[8]), + .I1(L[4]), + .I2(det_htotal_int[9]), + .I3(L[3]), + .O(i__carry__0_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry__0_i_5__0 + (.I0(det_htotal_int[8]), + .I1(L[4]), + .I2(det_htotal_int[9]), + .I3(L[3]), + .O(i__carry__0_i_5__0_n_0)); + LUT2 #( + .INIT(4'h9)) + i__carry__1_i_1 + (.I0(Q[11]), + .I1(det_hactive_start_int[11]), + .O(i__carry__1_i_1_n_0)); + LUT2 #( + .INIT(4'h6)) + i__carry__1_i_1__0 + (.I0(\time_status_regs[6] [11]), + .I1(det_hbp_start_int[11]), + .O(i__carry__1_i_1__0_n_0)); + LUT4 #( + .INIT(16'h2ED1)) + i__carry__1_i_1__1 + (.I0(det_hactive_start_int[11]), + .I1(ltOp), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [11]), + .I3(det_v0sync_start_hori_int[11]), + .O(i__carry__1_i_1__1_n_0)); + LUT4 #( + .INIT(16'h2ED1)) + i__carry__1_i_1__2 + (.I0(det_hactive_start_int[11]), + .I1(\ltOp_inferred__0/i__carry__0_n_2 ), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [11]), + .I3(det_v0bp_start_hori_int[11]), + .O(i__carry__1_i_1__2_n_0)); + LUT2 #( + .INIT(4'h6)) + i__carry__1_i_2 + (.I0(\time_status_regs[6] [10]), + .I1(det_hbp_start_int[10]), + .O(i__carry__1_i_2_n_0)); + LUT4 #( + .INIT(16'h2ED1)) + i__carry__1_i_2__0 + (.I0(det_hactive_start_int[10]), + .I1(ltOp), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [10]), + .I3(det_v0sync_start_hori_int[10]), + .O(i__carry__1_i_2__0_n_0)); + LUT4 #( + .INIT(16'h2ED1)) + i__carry__1_i_2__1 + (.I0(det_hactive_start_int[10]), + .I1(\ltOp_inferred__0/i__carry__0_n_2 ), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [10]), + .I3(det_v0bp_start_hori_int[10]), + .O(i__carry__1_i_2__1_n_0)); + LUT2 #( + .INIT(4'h9)) + i__carry__1_i_2__2 + (.I0(Q[10]), + .I1(det_hactive_start_int[10]), + .O(i__carry__1_i_2__2_n_0)); + LUT2 #( + .INIT(4'h6)) + i__carry__1_i_3 + (.I0(\time_status_regs[6] [9]), + .I1(det_hbp_start_int[9]), + .O(i__carry__1_i_3_n_0)); + LUT4 #( + .INIT(16'h2ED1)) + i__carry__1_i_3__0 + (.I0(det_hactive_start_int[9]), + .I1(ltOp), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [9]), + .I3(det_v0sync_start_hori_int[9]), + .O(i__carry__1_i_3__0_n_0)); + LUT4 #( + .INIT(16'h2ED1)) + i__carry__1_i_3__1 + (.I0(det_hactive_start_int[9]), + .I1(\ltOp_inferred__0/i__carry__0_n_2 ), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [9]), + .I3(det_v0bp_start_hori_int[9]), + .O(i__carry__1_i_3__1_n_0)); + LUT2 #( + .INIT(4'h9)) + i__carry__1_i_3__2 + (.I0(Q[9]), + .I1(det_hactive_start_int[9]), + .O(i__carry__1_i_3__2_n_0)); + LUT2 #( + .INIT(4'h6)) + i__carry__1_i_4 + (.I0(\time_status_regs[6] [8]), + .I1(det_hbp_start_int[8]), + .O(i__carry__1_i_4_n_0)); + LUT4 #( + .INIT(16'h2ED1)) + i__carry__1_i_4__0 + (.I0(det_hactive_start_int[8]), + .I1(ltOp), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [8]), + .I3(det_v0sync_start_hori_int[8]), + .O(i__carry__1_i_4__0_n_0)); + LUT4 #( + .INIT(16'h2ED1)) + i__carry__1_i_4__1 + (.I0(det_hactive_start_int[8]), + .I1(\ltOp_inferred__0/i__carry__0_n_2 ), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [8]), + .I3(det_v0bp_start_hori_int[8]), + .O(i__carry__1_i_4__1_n_0)); + LUT2 #( + .INIT(4'h9)) + i__carry__1_i_4__2 + (.I0(Q[8]), + .I1(det_hactive_start_int[8]), + .O(i__carry__1_i_4__2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry_i_1 + (.I0(L[6]), + .I1(det_htotal_int[6]), + .I2(det_htotal_int[7]), + .I3(L[5]), + .O(i__carry_i_1_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry_i_1__0 + (.I0(det_htotal_int[6]), + .I1(L[6]), + .I2(L[5]), + .I3(det_htotal_int[7]), + .O(i__carry_i_1__0_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry_i_1__1 + (.I0(\DET_VSYNC.vsync_count_reg__0 [5]), + .I1(det_v0total_int[6]), + .I2(det_v0total_int[7]), + .I3(\DET_VSYNC.vsync_count_reg__0 [6]), + .O(i__carry_i_1__1_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + i__carry_i_1__10 + (.I0(active_video_count_last[10]), + .I1(\DET_HACTIVE.active_video_count_reg [10]), + .I2(active_video_count_last[9]), + .I3(\DET_HACTIVE.active_video_count_reg [9]), + .I4(\DET_HACTIVE.active_video_count_reg [11]), + .I5(active_video_count_last[11]), + .O(i__carry_i_1__10_n_0)); + LUT2 #( + .INIT(4'h6)) + i__carry_i_1__11 + (.I0(\time_status_regs[6] [3]), + .I1(det_hbp_start_int[3]), + .O(i__carry_i_1__11_n_0)); + LUT2 #( + .INIT(4'h9)) + i__carry_i_1__12 + (.I0(Q[3]), + .I1(det_hactive_start_int[3]), + .O(i__carry_i_1__12_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry_i_1__2 + (.I0(det_hactive_start_int[6]), + .I1(det_v0bp_start_hori_int[6]), + .I2(det_v0bp_start_hori_int[7]), + .I3(det_hactive_start_int[7]), + .O(i__carry_i_1__2_n_0)); + LUT1 #( + .INIT(2'h1)) + i__carry_i_1__3 + (.I0(ltOp), + .O(i__carry_i_1__3_n_0)); + LUT1 #( + .INIT(2'h1)) + i__carry_i_1__4 + (.I0(\ltOp_inferred__0/i__carry__0_n_2 ), + .O(i__carry_i_1__4_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + i__carry_i_1__5 + (.I0(det_hsync_start_last[10]), + .I1(det_hsync_start_int[10]), + .I2(det_hsync_start_last[9]), + .I3(det_hsync_start_int[9]), + .I4(det_hsync_start_int[11]), + .I5(det_hsync_start_last[11]), + .O(i__carry_i_1__5_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry_i_1__6 + (.I0(det_v0bp_start_last[9]), + .I1(det_v0bp_start_int[9]), + .I2(det_v0bp_start_int[10]), + .I3(det_v0bp_start_last[10]), + .O(i__carry_i_1__6_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + i__carry_i_1__7 + (.I0(det_v0bp_start_hori_last[10]), + .I1(det_v0bp_start_hori_int[10]), + .I2(det_v0bp_start_hori_last[9]), + .I3(det_v0bp_start_hori_int[9]), + .I4(det_v0bp_start_hori_int[11]), + .I5(det_v0bp_start_hori_last[11]), + .O(i__carry_i_1__7_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry_i_1__8 + (.I0(det_v0sync_start_last[9]), + .I1(det_v0sync_start_int[9]), + .I2(det_v0sync_start_int[10]), + .I3(det_v0sync_start_last[10]), + .O(i__carry_i_1__8_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + i__carry_i_1__9 + (.I0(det_v0sync_start_hori_last[10]), + .I1(det_v0sync_start_hori_int[10]), + .I2(det_v0sync_start_hori_last[9]), + .I3(det_v0sync_start_hori_int[9]), + .I4(det_v0sync_start_hori_int[11]), + .I5(det_v0sync_start_hori_last[11]), + .O(i__carry_i_1__9_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry_i_2 + (.I0(L[8]), + .I1(det_htotal_int[4]), + .I2(det_htotal_int[5]), + .I3(L[7]), + .O(i__carry_i_2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry_i_2__0 + (.I0(det_htotal_int[4]), + .I1(L[8]), + .I2(L[7]), + .I3(det_htotal_int[5]), + .O(i__carry_i_2__0_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry_i_2__1 + (.I0(\DET_VSYNC.vsync_count_reg__0 [3]), + .I1(det_v0total_int[4]), + .I2(det_v0total_int[5]), + .I3(\DET_VSYNC.vsync_count_reg__0 [4]), + .O(i__carry_i_2__1_n_0)); + LUT4 #( + .INIT(16'h2ED1)) + i__carry_i_2__10 + (.I0(det_hactive_start_int[3]), + .I1(ltOp), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [3]), + .I3(det_v0sync_start_hori_int[3]), + .O(i__carry_i_2__10_n_0)); + LUT4 #( + .INIT(16'h2ED1)) + i__carry_i_2__11 + (.I0(det_hactive_start_int[3]), + .I1(\ltOp_inferred__0/i__carry__0_n_2 ), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [3]), + .I3(det_v0bp_start_hori_int[3]), + .O(i__carry_i_2__11_n_0)); + LUT2 #( + .INIT(4'h9)) + i__carry_i_2__12 + (.I0(Q[2]), + .I1(det_hactive_start_int[2]), + .O(i__carry_i_2__12_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry_i_2__2 + (.I0(det_hactive_start_int[4]), + .I1(det_v0bp_start_hori_int[4]), + .I2(det_v0bp_start_hori_int[5]), + .I3(det_hactive_start_int[5]), + .O(i__carry_i_2__2_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + i__carry_i_2__3 + (.I0(det_hsync_start_last[7]), + .I1(det_hsync_start_int[7]), + .I2(det_hsync_start_last[6]), + .I3(det_hsync_start_int[6]), + .I4(det_hsync_start_int[8]), + .I5(det_hsync_start_last[8]), + .O(i__carry_i_2__3_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + i__carry_i_2__4 + (.I0(det_v0bp_start_last[7]), + .I1(det_v0bp_start_int[7]), + .I2(det_v0bp_start_last[6]), + .I3(det_v0bp_start_int[6]), + .I4(det_v0bp_start_int[8]), + .I5(det_v0bp_start_last[8]), + .O(i__carry_i_2__4_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + i__carry_i_2__5 + (.I0(det_v0bp_start_hori_last[7]), + .I1(det_v0bp_start_hori_int[7]), + .I2(det_v0bp_start_hori_last[6]), + .I3(det_v0bp_start_hori_int[6]), + .I4(det_v0bp_start_hori_int[8]), + .I5(det_v0bp_start_hori_last[8]), + .O(i__carry_i_2__5_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + i__carry_i_2__6 + (.I0(det_v0sync_start_last[7]), + .I1(det_v0sync_start_int[7]), + .I2(det_v0sync_start_last[6]), + .I3(det_v0sync_start_int[6]), + .I4(det_v0sync_start_int[8]), + .I5(det_v0sync_start_last[8]), + .O(i__carry_i_2__6_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + i__carry_i_2__7 + (.I0(det_v0sync_start_hori_last[7]), + .I1(det_v0sync_start_hori_int[7]), + .I2(det_v0sync_start_hori_last[6]), + .I3(det_v0sync_start_hori_int[6]), + .I4(det_v0sync_start_hori_int[8]), + .I5(det_v0sync_start_hori_last[8]), + .O(i__carry_i_2__7_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + i__carry_i_2__8 + (.I0(active_video_count_last[7]), + .I1(\DET_HACTIVE.active_video_count_reg [7]), + .I2(active_video_count_last[6]), + .I3(\DET_HACTIVE.active_video_count_reg [6]), + .I4(\DET_HACTIVE.active_video_count_reg [8]), + .I5(active_video_count_last[8]), + .O(i__carry_i_2__8_n_0)); + LUT2 #( + .INIT(4'h6)) + i__carry_i_2__9 + (.I0(\time_status_regs[6] [2]), + .I1(det_hbp_start_int[2]), + .O(i__carry_i_2__9_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry_i_3 + (.I0(L[10]), + .I1(det_htotal_int[2]), + .I2(det_htotal_int[3]), + .I3(L[9]), + .O(i__carry_i_3_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry_i_3__0 + (.I0(det_htotal_int[2]), + .I1(L[10]), + .I2(L[9]), + .I3(det_htotal_int[3]), + .O(i__carry_i_3__0_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry_i_3__1 + (.I0(\DET_VSYNC.vsync_count_reg__0 [1]), + .I1(det_v0total_int[2]), + .I2(det_v0total_int[3]), + .I3(\DET_VSYNC.vsync_count_reg__0 [2]), + .O(i__carry_i_3__1_n_0)); + LUT4 #( + .INIT(16'h2ED1)) + i__carry_i_3__10 + (.I0(det_hactive_start_int[2]), + .I1(ltOp), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [2]), + .I3(det_v0sync_start_hori_int[2]), + .O(i__carry_i_3__10_n_0)); + LUT4 #( + .INIT(16'h2ED1)) + i__carry_i_3__11 + (.I0(det_hactive_start_int[2]), + .I1(\ltOp_inferred__0/i__carry__0_n_2 ), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [2]), + .I3(det_v0bp_start_hori_int[2]), + .O(i__carry_i_3__11_n_0)); + LUT2 #( + .INIT(4'h9)) + i__carry_i_3__12 + (.I0(Q[1]), + .I1(det_hactive_start_int[1]), + .O(i__carry_i_3__12_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry_i_3__2 + (.I0(det_hactive_start_int[2]), + .I1(det_v0bp_start_hori_int[2]), + .I2(det_v0bp_start_hori_int[3]), + .I3(det_hactive_start_int[3]), + .O(i__carry_i_3__2_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + i__carry_i_3__3 + (.I0(det_hsync_start_last[4]), + .I1(det_hsync_start_int[4]), + .I2(det_hsync_start_last[3]), + .I3(det_hsync_start_int[3]), + .I4(det_hsync_start_int[5]), + .I5(det_hsync_start_last[5]), + .O(i__carry_i_3__3_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + i__carry_i_3__4 + (.I0(det_v0bp_start_last[4]), + .I1(det_v0bp_start_int[4]), + .I2(det_v0bp_start_last[3]), + .I3(det_v0bp_start_int[3]), + .I4(det_v0bp_start_int[5]), + .I5(det_v0bp_start_last[5]), + .O(i__carry_i_3__4_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + i__carry_i_3__5 + (.I0(det_v0bp_start_hori_last[4]), + .I1(det_v0bp_start_hori_int[4]), + .I2(det_v0bp_start_hori_last[3]), + .I3(det_v0bp_start_hori_int[3]), + .I4(det_v0bp_start_hori_int[5]), + .I5(det_v0bp_start_hori_last[5]), + .O(i__carry_i_3__5_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + i__carry_i_3__6 + (.I0(det_v0sync_start_last[4]), + .I1(det_v0sync_start_int[4]), + .I2(det_v0sync_start_last[3]), + .I3(det_v0sync_start_int[3]), + .I4(det_v0sync_start_int[5]), + .I5(det_v0sync_start_last[5]), + .O(i__carry_i_3__6_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + i__carry_i_3__7 + (.I0(det_v0sync_start_hori_last[4]), + .I1(det_v0sync_start_hori_int[4]), + .I2(det_v0sync_start_hori_last[3]), + .I3(det_v0sync_start_hori_int[3]), + .I4(det_v0sync_start_hori_int[5]), + .I5(det_v0sync_start_hori_last[5]), + .O(i__carry_i_3__7_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + i__carry_i_3__8 + (.I0(active_video_count_last[4]), + .I1(\DET_HACTIVE.active_video_count_reg [4]), + .I2(active_video_count_last[3]), + .I3(\DET_HACTIVE.active_video_count_reg [3]), + .I4(\DET_HACTIVE.active_video_count_reg [5]), + .I5(active_video_count_last[5]), + .O(i__carry_i_3__8_n_0)); + LUT2 #( + .INIT(4'h6)) + i__carry_i_3__9 + (.I0(\time_status_regs[6] [1]), + .I1(det_hbp_start_int[1]), + .O(i__carry_i_3__9_n_0)); + LUT2 #( + .INIT(4'h2)) + i__carry_i_4 + (.I0(L[11]), + .I1(det_htotal_int[1]), + .O(i__carry_i_4_n_0)); + LUT3 #( + .INIT(8'hD4)) + i__carry_i_4__0 + (.I0(L[11]), + .I1(det_htotal_int[1]), + .I2(det_htotal_int[0]), + .O(i__carry_i_4__0_n_0)); + LUT2 #( + .INIT(4'h2)) + i__carry_i_4__1 + (.I0(\DET_VSYNC.vsync_count_reg__0 [0]), + .I1(det_v0total_int[1]), + .O(i__carry_i_4__1_n_0)); + LUT4 #( + .INIT(16'h2ED1)) + i__carry_i_4__10 + (.I0(det_hactive_start_int[1]), + .I1(ltOp), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [1]), + .I3(det_v0sync_start_hori_int[1]), + .O(i__carry_i_4__10_n_0)); + LUT4 #( + .INIT(16'h2ED1)) + i__carry_i_4__11 + (.I0(det_hactive_start_int[1]), + .I1(\ltOp_inferred__0/i__carry__0_n_2 ), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [1]), + .I3(det_v0bp_start_hori_int[1]), + .O(i__carry_i_4__11_n_0)); + LUT2 #( + .INIT(4'h9)) + i__carry_i_4__12 + (.I0(Q[0]), + .I1(det_hactive_start_int[0]), + .O(i__carry_i_4__12_n_0)); + LUT4 #( + .INIT(16'h2F02)) + i__carry_i_4__2 + (.I0(det_hactive_start_int[0]), + .I1(det_v0bp_start_hori_int[0]), + .I2(det_v0bp_start_hori_int[1]), + .I3(det_hactive_start_int[1]), + .O(i__carry_i_4__2_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + i__carry_i_4__3 + (.I0(det_hsync_start_last[1]), + .I1(det_hsync_start_int[1]), + .I2(det_hsync_start_last[0]), + .I3(det_hsync_start_int[0]), + .I4(det_hsync_start_int[2]), + .I5(det_hsync_start_last[2]), + .O(i__carry_i_4__3_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + i__carry_i_4__4 + (.I0(det_v0bp_start_last[1]), + .I1(det_v0bp_start_int[1]), + .I2(det_v0bp_start_last[0]), + .I3(det_v0bp_start_int[0]), + .I4(det_v0bp_start_int[2]), + .I5(det_v0bp_start_last[2]), + .O(i__carry_i_4__4_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + i__carry_i_4__5 + (.I0(det_v0bp_start_hori_last[1]), + .I1(det_v0bp_start_hori_int[1]), + .I2(det_v0bp_start_hori_last[0]), + .I3(det_v0bp_start_hori_int[0]), + .I4(det_v0bp_start_hori_int[2]), + .I5(det_v0bp_start_hori_last[2]), + .O(i__carry_i_4__5_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + i__carry_i_4__6 + (.I0(det_v0sync_start_last[1]), + .I1(det_v0sync_start_int[1]), + .I2(det_v0sync_start_last[0]), + .I3(det_v0sync_start_int[0]), + .I4(det_v0sync_start_int[2]), + .I5(det_v0sync_start_last[2]), + .O(i__carry_i_4__6_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + i__carry_i_4__7 + (.I0(det_v0sync_start_hori_last[1]), + .I1(det_v0sync_start_hori_int[1]), + .I2(det_v0sync_start_hori_last[0]), + .I3(det_v0sync_start_hori_int[0]), + .I4(det_v0sync_start_hori_int[2]), + .I5(det_v0sync_start_hori_last[2]), + .O(i__carry_i_4__7_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + i__carry_i_4__8 + (.I0(active_video_count_last[1]), + .I1(\DET_HACTIVE.active_video_count_reg [1]), + .I2(active_video_count_last[0]), + .I3(\DET_HACTIVE.active_video_count_reg [0]), + .I4(\DET_HACTIVE.active_video_count_reg [2]), + .I5(active_video_count_last[2]), + .O(i__carry_i_4__8_n_0)); + LUT2 #( + .INIT(4'h6)) + i__carry_i_4__9 + (.I0(\time_status_regs[6] [0]), + .I1(det_hbp_start_int[0]), + .O(i__carry_i_4__9_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry_i_5 + (.I0(det_htotal_int[6]), + .I1(L[6]), + .I2(det_htotal_int[7]), + .I3(L[5]), + .O(i__carry_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry_i_5__0 + (.I0(det_v0total_int[7]), + .I1(\DET_VSYNC.vsync_count_reg__0 [6]), + .I2(det_v0total_int[6]), + .I3(\DET_VSYNC.vsync_count_reg__0 [5]), + .O(i__carry_i_5__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry_i_5__1 + (.I0(det_v0bp_start_hori_int[7]), + .I1(det_hactive_start_int[7]), + .I2(det_v0bp_start_hori_int[6]), + .I3(det_hactive_start_int[6]), + .O(i__carry_i_5__1_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry_i_5__2 + (.I0(det_htotal_int[6]), + .I1(L[6]), + .I2(det_htotal_int[7]), + .I3(L[5]), + .O(i__carry_i_5__2_n_0)); + LUT3 #( + .INIT(8'hE2)) + i__carry_i_5__3 + (.I0(det_hactive_start_int[0]), + .I1(ltOp), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [0]), + .O(i__carry_i_5__3_n_0)); + LUT3 #( + .INIT(8'hE2)) + i__carry_i_5__4 + (.I0(det_hactive_start_int[0]), + .I1(\ltOp_inferred__0/i__carry__0_n_2 ), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] [0]), + .O(i__carry_i_5__4_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry_i_6 + (.I0(det_htotal_int[4]), + .I1(L[8]), + .I2(det_htotal_int[5]), + .I3(L[7]), + .O(i__carry_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry_i_6__0 + (.I0(det_v0total_int[5]), + .I1(\DET_VSYNC.vsync_count_reg__0 [4]), + .I2(det_v0total_int[4]), + .I3(\DET_VSYNC.vsync_count_reg__0 [3]), + .O(i__carry_i_6__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry_i_6__1 + (.I0(det_v0bp_start_hori_int[5]), + .I1(det_hactive_start_int[5]), + .I2(det_v0bp_start_hori_int[4]), + .I3(det_hactive_start_int[4]), + .O(i__carry_i_6__1_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry_i_6__2 + (.I0(det_htotal_int[4]), + .I1(L[8]), + .I2(det_htotal_int[5]), + .I3(L[7]), + .O(i__carry_i_6__2_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry_i_7 + (.I0(det_htotal_int[2]), + .I1(L[10]), + .I2(det_htotal_int[3]), + .I3(L[9]), + .O(i__carry_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry_i_7__0 + (.I0(det_v0total_int[3]), + .I1(\DET_VSYNC.vsync_count_reg__0 [2]), + .I2(det_v0total_int[2]), + .I3(\DET_VSYNC.vsync_count_reg__0 [1]), + .O(i__carry_i_7__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry_i_7__1 + (.I0(det_v0bp_start_hori_int[3]), + .I1(det_hactive_start_int[3]), + .I2(det_v0bp_start_hori_int[2]), + .I3(det_hactive_start_int[2]), + .O(i__carry_i_7__1_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry_i_7__2 + (.I0(det_htotal_int[2]), + .I1(L[10]), + .I2(det_htotal_int[3]), + .I3(L[9]), + .O(i__carry_i_7__2_n_0)); + LUT3 #( + .INIT(8'h09)) + i__carry_i_8 + (.I0(det_htotal_int[1]), + .I1(L[11]), + .I2(det_htotal_int[0]), + .O(i__carry_i_8_n_0)); + LUT3 #( + .INIT(8'h41)) + i__carry_i_8__0 + (.I0(det_v0total_int[0]), + .I1(det_v0total_int[1]), + .I2(\DET_VSYNC.vsync_count_reg__0 [0]), + .O(i__carry_i_8__0_n_0)); + LUT4 #( + .INIT(16'h9009)) + i__carry_i_8__1 + (.I0(det_v0bp_start_hori_int[1]), + .I1(det_hactive_start_int[1]), + .I2(det_v0bp_start_hori_int[0]), + .I3(det_hactive_start_int[0]), + .O(i__carry_i_8__1_n_0)); + LUT3 #( + .INIT(8'h09)) + i__carry_i_8__2 + (.I0(det_htotal_int[1]), + .I1(L[11]), + .I2(det_htotal_int[0]), + .O(i__carry_i_8__2_n_0)); + LUT1 #( + .INIT(2'h1)) + \intr_error_int[6]_i_1 + (.I0(resetn_out), + .O(reset)); + LUT6 #( + .INIT(64'hFFFF03C057D503C0)) + \intr_status_int[11]_i_2 + (.I0(det_vblank_d), + .I1(active_video_in), + .I2(\time_status_regs[3] [2]), + .I3(det_active_video_d), + .I4(intc_if), + .I5(vblank_in), + .O(\intr_status_int_reg[11] )); + (* SOFT_HLUTNM = "soft_lutpair287" *) + LUT3 #( + .INIT(8'h80)) + \intr_status_int[9]_i_2 + (.I0(active_video_lock_int), + .I1(hsync_lock_int), + .I2(vsync_lock_int), + .O(intr_status_int17_out)); + CARRY4 leqOp_carry + (.CI(1'b0), + .CO({leqOp_carry_n_0,leqOp_carry_n_1,leqOp_carry_n_2,leqOp_carry_n_3}), + .CYINIT(1'b1), + .DI({leqOp_carry_i_1_n_0,leqOp_carry_i_2_n_0,leqOp_carry_i_3_n_0,leqOp_carry_i_4_n_0}), + .O(NLW_leqOp_carry_O_UNCONNECTED[3:0]), + .S({leqOp_carry_i_5_n_0,leqOp_carry_i_6_n_0,leqOp_carry_i_7_n_0,leqOp_carry_i_8_n_0})); + CARRY4 leqOp_carry__0 + (.CI(leqOp_carry_n_0), + .CO({NLW_leqOp_carry__0_CO_UNCONNECTED[3],leqOp,leqOp_carry__0_n_2,leqOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({1'b0,1'b0,leqOp_carry__0_i_1_n_0,leqOp_carry__0_i_2_n_0}), + .O(NLW_leqOp_carry__0_O_UNCONNECTED[3:0]), + .S({1'b0,leqOp_carry__0_i_3_n_0,leqOp_carry__0_i_4_n_0,leqOp_carry__0_i_5_n_0})); + LUT4 #( + .INIT(16'h2F02)) + leqOp_carry__0_i_1 + (.I0(det_htotal_int[10]), + .I1(\DET_HACTIVE.active_video_count_reg [9]), + .I2(\DET_HACTIVE.active_video_count_reg [10]), + .I3(det_htotal_int[11]), + .O(leqOp_carry__0_i_1_n_0)); + LUT4 #( + .INIT(16'h2F02)) + leqOp_carry__0_i_2 + (.I0(det_htotal_int[8]), + .I1(\DET_HACTIVE.active_video_count_reg [7]), + .I2(\DET_HACTIVE.active_video_count_reg [8]), + .I3(det_htotal_int[9]), + .O(leqOp_carry__0_i_2_n_0)); + LUT1 #( + .INIT(2'h1)) + leqOp_carry__0_i_3 + (.I0(\DET_HACTIVE.active_video_count_reg [11]), + .O(leqOp_carry__0_i_3_n_0)); + LUT4 #( + .INIT(16'h9009)) + leqOp_carry__0_i_4 + (.I0(\DET_HACTIVE.active_video_count_reg [10]), + .I1(det_htotal_int[11]), + .I2(\DET_HACTIVE.active_video_count_reg [9]), + .I3(det_htotal_int[10]), + .O(leqOp_carry__0_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + leqOp_carry__0_i_5 + (.I0(\DET_HACTIVE.active_video_count_reg [8]), + .I1(det_htotal_int[9]), + .I2(\DET_HACTIVE.active_video_count_reg [7]), + .I3(det_htotal_int[8]), + .O(leqOp_carry__0_i_5_n_0)); + LUT4 #( + .INIT(16'h2F02)) + leqOp_carry_i_1 + (.I0(det_htotal_int[6]), + .I1(\DET_HACTIVE.active_video_count_reg [5]), + .I2(\DET_HACTIVE.active_video_count_reg [6]), + .I3(det_htotal_int[7]), + .O(leqOp_carry_i_1_n_0)); + LUT4 #( + .INIT(16'h2F02)) + leqOp_carry_i_2 + (.I0(det_htotal_int[4]), + .I1(\DET_HACTIVE.active_video_count_reg [3]), + .I2(\DET_HACTIVE.active_video_count_reg [4]), + .I3(det_htotal_int[5]), + .O(leqOp_carry_i_2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + leqOp_carry_i_3 + (.I0(det_htotal_int[2]), + .I1(\DET_HACTIVE.active_video_count_reg [1]), + .I2(\DET_HACTIVE.active_video_count_reg [2]), + .I3(det_htotal_int[3]), + .O(leqOp_carry_i_3_n_0)); + LUT3 #( + .INIT(8'hD4)) + leqOp_carry_i_4 + (.I0(\DET_HACTIVE.active_video_count_reg [0]), + .I1(det_htotal_int[1]), + .I2(det_htotal_int[0]), + .O(leqOp_carry_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + leqOp_carry_i_5 + (.I0(\DET_HACTIVE.active_video_count_reg [6]), + .I1(det_htotal_int[7]), + .I2(\DET_HACTIVE.active_video_count_reg [5]), + .I3(det_htotal_int[6]), + .O(leqOp_carry_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + leqOp_carry_i_6 + (.I0(\DET_HACTIVE.active_video_count_reg [4]), + .I1(det_htotal_int[5]), + .I2(\DET_HACTIVE.active_video_count_reg [3]), + .I3(det_htotal_int[4]), + .O(leqOp_carry_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + leqOp_carry_i_7 + (.I0(\DET_HACTIVE.active_video_count_reg [2]), + .I1(det_htotal_int[3]), + .I2(\DET_HACTIVE.active_video_count_reg [1]), + .I3(det_htotal_int[2]), + .O(leqOp_carry_i_7_n_0)); + LUT3 #( + .INIT(8'h09)) + leqOp_carry_i_8 + (.I0(det_htotal_int[1]), + .I1(\DET_HACTIVE.active_video_count_reg [0]), + .I2(det_htotal_int[0]), + .O(leqOp_carry_i_8_n_0)); + CARRY4 \leqOp_inferred__0/i__carry + (.CI(1'b0), + .CO({\leqOp_inferred__0/i__carry_n_0 ,\leqOp_inferred__0/i__carry_n_1 ,\leqOp_inferred__0/i__carry_n_2 ,\leqOp_inferred__0/i__carry_n_3 }), + .CYINIT(1'b1), + .DI({i__carry_i_1__0_n_0,i__carry_i_2__0_n_0,i__carry_i_3__0_n_0,i__carry_i_4__0_n_0}), + .O(\NLW_leqOp_inferred__0/i__carry_O_UNCONNECTED [3:0]), + .S({i__carry_i_5_n_0,i__carry_i_6_n_0,i__carry_i_7_n_0,i__carry_i_8_n_0})); + CARRY4 \leqOp_inferred__0/i__carry__0 + (.CI(\leqOp_inferred__0/i__carry_n_0 ), + .CO({\NLW_leqOp_inferred__0/i__carry__0_CO_UNCONNECTED [3],leqOp_1,\leqOp_inferred__0/i__carry__0_n_2 ,\leqOp_inferred__0/i__carry__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,i__carry__0_i_1__0_n_0,i__carry__0_i_2__0_n_0}), + .O(\NLW_leqOp_inferred__0/i__carry__0_O_UNCONNECTED [3:0]), + .S({1'b0,i__carry__0_i_3__1_n_0,i__carry__0_i_4_n_0,i__carry__0_i_5_n_0})); + FDRE line_end_d_reg + (.C(clk), + .CE(1'b1), + .D(line_end), + .Q(line_end_d_reg_n_0), + .R(1'b0)); + CARRY4 ltOp_carry + (.CI(1'b0), + .CO({ltOp_carry_n_0,ltOp_carry_n_1,ltOp_carry_n_2,ltOp_carry_n_3}), + .CYINIT(1'b0), + .DI({ltOp_carry_i_1_n_0,ltOp_carry_i_2_n_0,ltOp_carry_i_3_n_0,ltOp_carry_i_4_n_0}), + .O(NLW_ltOp_carry_O_UNCONNECTED[3:0]), + .S({ltOp_carry_i_5_n_0,ltOp_carry_i_6_n_0,ltOp_carry_i_7_n_0,ltOp_carry_i_8_n_0})); + CARRY4 ltOp_carry__0 + (.CI(ltOp_carry_n_0), + .CO({NLW_ltOp_carry__0_CO_UNCONNECTED[3:2],ltOp,ltOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI({1'b0,1'b0,ltOp_carry__0_i_1_n_0,ltOp_carry__0_i_2_n_0}), + .O(NLW_ltOp_carry__0_O_UNCONNECTED[3:0]), + .S({1'b0,1'b0,ltOp_carry__0_i_3_n_0,ltOp_carry__0_i_4_n_0})); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry__0_i_1 + (.I0(det_hactive_start_int[10]), + .I1(det_v0sync_start_hori_int[10]), + .I2(det_v0sync_start_hori_int[11]), + .I3(det_hactive_start_int[11]), + .O(ltOp_carry__0_i_1_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry__0_i_2 + (.I0(det_hactive_start_int[8]), + .I1(det_v0sync_start_hori_int[8]), + .I2(det_v0sync_start_hori_int[9]), + .I3(det_hactive_start_int[9]), + .O(ltOp_carry__0_i_2_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__0_i_3 + (.I0(det_v0sync_start_hori_int[11]), + .I1(det_hactive_start_int[11]), + .I2(det_v0sync_start_hori_int[10]), + .I3(det_hactive_start_int[10]), + .O(ltOp_carry__0_i_3_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry__0_i_4 + (.I0(det_v0sync_start_hori_int[9]), + .I1(det_hactive_start_int[9]), + .I2(det_v0sync_start_hori_int[8]), + .I3(det_hactive_start_int[8]), + .O(ltOp_carry__0_i_4_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_1 + (.I0(det_hactive_start_int[6]), + .I1(det_v0sync_start_hori_int[6]), + .I2(det_v0sync_start_hori_int[7]), + .I3(det_hactive_start_int[7]), + .O(ltOp_carry_i_1_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_2 + (.I0(det_hactive_start_int[4]), + .I1(det_v0sync_start_hori_int[4]), + .I2(det_v0sync_start_hori_int[5]), + .I3(det_hactive_start_int[5]), + .O(ltOp_carry_i_2_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_3 + (.I0(det_hactive_start_int[2]), + .I1(det_v0sync_start_hori_int[2]), + .I2(det_v0sync_start_hori_int[3]), + .I3(det_hactive_start_int[3]), + .O(ltOp_carry_i_3_n_0)); + LUT4 #( + .INIT(16'h2F02)) + ltOp_carry_i_4 + (.I0(det_hactive_start_int[0]), + .I1(det_v0sync_start_hori_int[0]), + .I2(det_v0sync_start_hori_int[1]), + .I3(det_hactive_start_int[1]), + .O(ltOp_carry_i_4_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_5 + (.I0(det_v0sync_start_hori_int[7]), + .I1(det_hactive_start_int[7]), + .I2(det_v0sync_start_hori_int[6]), + .I3(det_hactive_start_int[6]), + .O(ltOp_carry_i_5_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_6 + (.I0(det_v0sync_start_hori_int[5]), + .I1(det_hactive_start_int[5]), + .I2(det_v0sync_start_hori_int[4]), + .I3(det_hactive_start_int[4]), + .O(ltOp_carry_i_6_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_7 + (.I0(det_v0sync_start_hori_int[3]), + .I1(det_hactive_start_int[3]), + .I2(det_v0sync_start_hori_int[2]), + .I3(det_hactive_start_int[2]), + .O(ltOp_carry_i_7_n_0)); + LUT4 #( + .INIT(16'h9009)) + ltOp_carry_i_8 + (.I0(det_v0sync_start_hori_int[1]), + .I1(det_hactive_start_int[1]), + .I2(det_v0sync_start_hori_int[0]), + .I3(det_hactive_start_int[0]), + .O(ltOp_carry_i_8_n_0)); + CARRY4 \ltOp_inferred__0/i__carry + (.CI(1'b0), + .CO({\ltOp_inferred__0/i__carry_n_0 ,\ltOp_inferred__0/i__carry_n_1 ,\ltOp_inferred__0/i__carry_n_2 ,\ltOp_inferred__0/i__carry_n_3 }), + .CYINIT(1'b0), + .DI({i__carry_i_1__2_n_0,i__carry_i_2__2_n_0,i__carry_i_3__2_n_0,i__carry_i_4__2_n_0}), + .O(\NLW_ltOp_inferred__0/i__carry_O_UNCONNECTED [3:0]), + .S({i__carry_i_5__1_n_0,i__carry_i_6__1_n_0,i__carry_i_7__1_n_0,i__carry_i_8__1_n_0})); + CARRY4 \ltOp_inferred__0/i__carry__0 + (.CI(\ltOp_inferred__0/i__carry_n_0 ), + .CO({\NLW_ltOp_inferred__0/i__carry__0_CO_UNCONNECTED [3:2],\ltOp_inferred__0/i__carry__0_n_2 ,\ltOp_inferred__0/i__carry__0_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,i__carry__0_i_1__2_n_0,i__carry__0_i_2__2_n_0}), + .O(\NLW_ltOp_inferred__0/i__carry__0_O_UNCONNECTED [3:0]), + .S({1'b0,1'b0,i__carry__0_i_3__0_n_0,i__carry__0_i_4__1_n_0})); + CARRY4 minusOp_carry + (.CI(1'b0), + .CO({minusOp_carry_n_0,minusOp_carry_n_1,minusOp_carry_n_2,minusOp_carry_n_3}), + .CYINIT(1'b1), + .DI(det_hfp_start_int[3:0]), + .O(minusOp1_out[3:0]), + .S({minusOp_carry_i_1_n_0,minusOp_carry_i_2_n_0,minusOp_carry_i_3_n_0,minusOp_carry_i_4_n_0})); + CARRY4 minusOp_carry__0 + (.CI(minusOp_carry_n_0), + .CO({minusOp_carry__0_n_0,minusOp_carry__0_n_1,minusOp_carry__0_n_2,minusOp_carry__0_n_3}), + .CYINIT(1'b0), + .DI(det_hfp_start_int[7:4]), + .O(minusOp1_out[7:4]), + .S({minusOp_carry__0_i_1_n_0,minusOp_carry__0_i_2_n_0,minusOp_carry__0_i_3_n_0,minusOp_carry__0_i_4_n_0})); + LUT2 #( + .INIT(4'h9)) + minusOp_carry__0_i_1 + (.I0(det_hfp_start_int[7]), + .I1(det_hactive_start_int[7]), + .O(minusOp_carry__0_i_1_n_0)); + LUT2 #( + .INIT(4'h9)) + minusOp_carry__0_i_2 + (.I0(det_hfp_start_int[6]), + .I1(det_hactive_start_int[6]), + .O(minusOp_carry__0_i_2_n_0)); + LUT2 #( + .INIT(4'h9)) + minusOp_carry__0_i_3 + (.I0(det_hfp_start_int[5]), + .I1(det_hactive_start_int[5]), + .O(minusOp_carry__0_i_3_n_0)); + LUT2 #( + .INIT(4'h9)) + minusOp_carry__0_i_4 + (.I0(det_hfp_start_int[4]), + .I1(det_hactive_start_int[4]), + .O(minusOp_carry__0_i_4_n_0)); + CARRY4 minusOp_carry__1 + (.CI(minusOp_carry__0_n_0), + .CO({NLW_minusOp_carry__1_CO_UNCONNECTED[3],minusOp_carry__1_n_1,minusOp_carry__1_n_2,minusOp_carry__1_n_3}), + .CYINIT(1'b0), + .DI({1'b0,det_hfp_start_int[10:8]}), + .O(minusOp1_out[11:8]), + .S({minusOp_carry__1_i_1_n_0,minusOp_carry__1_i_2_n_0,minusOp_carry__1_i_3_n_0,minusOp_carry__1_i_4_n_0})); + LUT2 #( + .INIT(4'h9)) + minusOp_carry__1_i_1 + (.I0(det_hfp_start_int[11]), + .I1(det_hactive_start_int[11]), + .O(minusOp_carry__1_i_1_n_0)); + LUT2 #( + .INIT(4'h9)) + minusOp_carry__1_i_2 + (.I0(det_hfp_start_int[10]), + .I1(det_hactive_start_int[10]), + .O(minusOp_carry__1_i_2_n_0)); + LUT2 #( + .INIT(4'h9)) + minusOp_carry__1_i_3 + (.I0(det_hfp_start_int[9]), + .I1(det_hactive_start_int[9]), + .O(minusOp_carry__1_i_3_n_0)); + LUT2 #( + .INIT(4'h9)) + minusOp_carry__1_i_4 + (.I0(det_hfp_start_int[8]), + .I1(det_hactive_start_int[8]), + .O(minusOp_carry__1_i_4_n_0)); + LUT2 #( + .INIT(4'h9)) + minusOp_carry_i_1 + (.I0(det_hfp_start_int[3]), + .I1(det_hactive_start_int[3]), + .O(minusOp_carry_i_1_n_0)); + LUT2 #( + .INIT(4'h9)) + minusOp_carry_i_2 + (.I0(det_hfp_start_int[2]), + .I1(det_hactive_start_int[2]), + .O(minusOp_carry_i_2_n_0)); + LUT2 #( + .INIT(4'h9)) + minusOp_carry_i_3 + (.I0(det_hfp_start_int[1]), + .I1(det_hactive_start_int[1]), + .O(minusOp_carry_i_3_n_0)); + LUT2 #( + .INIT(4'h9)) + minusOp_carry_i_4 + (.I0(det_hfp_start_int[0]), + .I1(det_hactive_start_int[0]), + .O(minusOp_carry_i_4_n_0)); + CARRY4 \minusOp_inferred__0/i__carry + (.CI(1'b0), + .CO({\minusOp_inferred__0/i__carry_n_0 ,\minusOp_inferred__0/i__carry_n_1 ,\minusOp_inferred__0/i__carry_n_2 ,\minusOp_inferred__0/i__carry_n_3 }), + .CYINIT(1'b1), + .DI(Q[3:0]), + .O(minusOp0_out[3:0]), + .S({i__carry_i_1__12_n_0,i__carry_i_2__12_n_0,i__carry_i_3__12_n_0,i__carry_i_4__12_n_0})); + CARRY4 \minusOp_inferred__0/i__carry__0 + (.CI(\minusOp_inferred__0/i__carry_n_0 ), + .CO({\minusOp_inferred__0/i__carry__0_n_0 ,\minusOp_inferred__0/i__carry__0_n_1 ,\minusOp_inferred__0/i__carry__0_n_2 ,\minusOp_inferred__0/i__carry__0_n_3 }), + .CYINIT(1'b0), + .DI(Q[7:4]), + .O(minusOp0_out[7:4]), + .S({i__carry__0_i_1__6_n_0,i__carry__0_i_2__6_n_0,i__carry__0_i_3__6_n_0,i__carry__0_i_4__6_n_0})); + CARRY4 \minusOp_inferred__0/i__carry__1 + (.CI(\minusOp_inferred__0/i__carry__0_n_0 ), + .CO({\NLW_minusOp_inferred__0/i__carry__1_CO_UNCONNECTED [3],\minusOp_inferred__0/i__carry__1_n_1 ,\minusOp_inferred__0/i__carry__1_n_2 ,\minusOp_inferred__0/i__carry__1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,Q[10:8]}), + .O(minusOp0_out[11:8]), + .S({i__carry__1_i_1_n_0,i__carry__1_i_2__2_n_0,i__carry__1_i_3__2_n_0,i__carry__1_i_4__2_n_0})); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 neqOp_carry + (.CI(1'b0), + .CO({neqOp2_out,neqOp_carry_n_1,neqOp_carry_n_2,neqOp_carry_n_3}), + .CYINIT(1'b0), + .DI({1'b1,1'b1,1'b1,1'b1}), + .O(NLW_neqOp_carry_O_UNCONNECTED[3:0]), + .S({neqOp_carry_i_1_n_0,neqOp_carry_i_2_n_0,neqOp_carry_i_3_n_0,neqOp_carry_i_4_n_0})); + LUT6 #( + .INIT(64'h9009000000009009)) + neqOp_carry_i_1 + (.I0(det_hbp_start_last[10]), + .I1(det_hbp_start_int[10]), + .I2(det_hbp_start_last[9]), + .I3(det_hbp_start_int[9]), + .I4(det_hbp_start_int[11]), + .I5(det_hbp_start_last[11]), + .O(neqOp_carry_i_1_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + neqOp_carry_i_2 + (.I0(det_hbp_start_last[7]), + .I1(det_hbp_start_int[7]), + .I2(det_hbp_start_last[6]), + .I3(det_hbp_start_int[6]), + .I4(det_hbp_start_int[8]), + .I5(det_hbp_start_last[8]), + .O(neqOp_carry_i_2_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + neqOp_carry_i_3 + (.I0(det_hbp_start_last[4]), + .I1(det_hbp_start_int[4]), + .I2(det_hbp_start_last[3]), + .I3(det_hbp_start_int[3]), + .I4(det_hbp_start_int[5]), + .I5(det_hbp_start_last[5]), + .O(neqOp_carry_i_3_n_0)); + LUT6 #( + .INIT(64'h9009000000009009)) + neqOp_carry_i_4 + (.I0(det_hbp_start_last[1]), + .I1(det_hbp_start_int[1]), + .I2(det_hbp_start_last[0]), + .I3(det_hbp_start_int[0]), + .I4(det_hbp_start_int[2]), + .I5(det_hbp_start_last[2]), + .O(neqOp_carry_i_4_n_0)); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \neqOp_inferred__0/i__carry + (.CI(1'b0), + .CO({neqOp3_out,\neqOp_inferred__0/i__carry_n_1 ,\neqOp_inferred__0/i__carry_n_2 ,\neqOp_inferred__0/i__carry_n_3 }), + .CYINIT(1'b0), + .DI({1'b1,1'b1,1'b1,1'b1}), + .O(\NLW_neqOp_inferred__0/i__carry_O_UNCONNECTED [3:0]), + .S({i__carry_i_1__5_n_0,i__carry_i_2__3_n_0,i__carry_i_3__3_n_0,i__carry_i_4__3_n_0})); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \neqOp_inferred__1/i__carry + (.CI(1'b0), + .CO({\neqOp_inferred__1/i__carry_n_0 ,\neqOp_inferred__1/i__carry_n_1 ,\neqOp_inferred__1/i__carry_n_2 ,\neqOp_inferred__1/i__carry_n_3 }), + .CYINIT(1'b0), + .DI({1'b1,1'b1,1'b1,1'b1}), + .O(\NLW_neqOp_inferred__1/i__carry_O_UNCONNECTED [3:0]), + .S({i__carry_i_1__6_n_0,i__carry_i_2__4_n_0,i__carry_i_3__4_n_0,i__carry_i_4__4_n_0})); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \neqOp_inferred__2/i__carry + (.CI(1'b0), + .CO({neqOp,\neqOp_inferred__2/i__carry_n_1 ,\neqOp_inferred__2/i__carry_n_2 ,\neqOp_inferred__2/i__carry_n_3 }), + .CYINIT(1'b0), + .DI({1'b1,1'b1,1'b1,1'b1}), + .O(\NLW_neqOp_inferred__2/i__carry_O_UNCONNECTED [3:0]), + .S({i__carry_i_1__7_n_0,i__carry_i_2__5_n_0,i__carry_i_3__5_n_0,i__carry_i_4__5_n_0})); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \neqOp_inferred__3/i__carry + (.CI(1'b0), + .CO({\neqOp_inferred__3/i__carry_n_0 ,\neqOp_inferred__3/i__carry_n_1 ,\neqOp_inferred__3/i__carry_n_2 ,\neqOp_inferred__3/i__carry_n_3 }), + .CYINIT(1'b0), + .DI({1'b1,1'b1,1'b1,1'b1}), + .O(\NLW_neqOp_inferred__3/i__carry_O_UNCONNECTED [3:0]), + .S({i__carry_i_1__8_n_0,i__carry_i_2__6_n_0,i__carry_i_3__6_n_0,i__carry_i_4__6_n_0})); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \neqOp_inferred__4/i__carry + (.CI(1'b0), + .CO({neqOp0_out,\neqOp_inferred__4/i__carry_n_1 ,\neqOp_inferred__4/i__carry_n_2 ,\neqOp_inferred__4/i__carry_n_3 }), + .CYINIT(1'b0), + .DI({1'b1,1'b1,1'b1,1'b1}), + .O(\NLW_neqOp_inferred__4/i__carry_O_UNCONNECTED [3:0]), + .S({i__carry_i_1__9_n_0,i__carry_i_2__7_n_0,i__carry_i_3__7_n_0,i__carry_i_4__7_n_0})); + (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) + CARRY4 \neqOp_inferred__5/i__carry + (.CI(1'b0), + .CO({neqOp1_out,\neqOp_inferred__5/i__carry_n_1 ,\neqOp_inferred__5/i__carry_n_2 ,\neqOp_inferred__5/i__carry_n_3 }), + .CYINIT(1'b0), + .DI({1'b1,1'b1,1'b1,1'b1}), + .O(\NLW_neqOp_inferred__5/i__carry_O_UNCONNECTED [3:0]), + .S({i__carry_i_1__10_n_0,i__carry_i_2__8_n_0,i__carry_i_3__8_n_0,i__carry_i_4__8_n_0})); + CARRY4 \plusOp_inferred__2/i__carry + (.CI(1'b0), + .CO({\plusOp_inferred__2/i__carry_n_0 ,\plusOp_inferred__2/i__carry_n_1 ,\plusOp_inferred__2/i__carry_n_2 ,\plusOp_inferred__2/i__carry_n_3 }), + .CYINIT(1'b0), + .DI(\time_status_regs[6] [3:0]), + .O({\plusOp_inferred__2/i__carry_n_4 ,\plusOp_inferred__2/i__carry_n_5 ,\plusOp_inferred__2/i__carry_n_6 ,\plusOp_inferred__2/i__carry_n_7 }), + .S({i__carry_i_1__11_n_0,i__carry_i_2__9_n_0,i__carry_i_3__9_n_0,i__carry_i_4__9_n_0})); + CARRY4 \plusOp_inferred__2/i__carry__0 + (.CI(\plusOp_inferred__2/i__carry_n_0 ), + .CO({\plusOp_inferred__2/i__carry__0_n_0 ,\plusOp_inferred__2/i__carry__0_n_1 ,\plusOp_inferred__2/i__carry__0_n_2 ,\plusOp_inferred__2/i__carry__0_n_3 }), + .CYINIT(1'b0), + .DI(\time_status_regs[6] [7:4]), + .O({\plusOp_inferred__2/i__carry__0_n_4 ,\plusOp_inferred__2/i__carry__0_n_5 ,\plusOp_inferred__2/i__carry__0_n_6 ,\plusOp_inferred__2/i__carry__0_n_7 }), + .S({i__carry__0_i_1__3_n_0,i__carry__0_i_2__3_n_0,i__carry__0_i_3__3_n_0,i__carry__0_i_4__3_n_0})); + CARRY4 \plusOp_inferred__2/i__carry__1 + (.CI(\plusOp_inferred__2/i__carry__0_n_0 ), + .CO({\NLW_plusOp_inferred__2/i__carry__1_CO_UNCONNECTED [3],\plusOp_inferred__2/i__carry__1_n_1 ,\plusOp_inferred__2/i__carry__1_n_2 ,\plusOp_inferred__2/i__carry__1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,\time_status_regs[6] [10:8]}), + .O({\plusOp_inferred__2/i__carry__1_n_4 ,\plusOp_inferred__2/i__carry__1_n_5 ,\plusOp_inferred__2/i__carry__1_n_6 ,\plusOp_inferred__2/i__carry__1_n_7 }), + .S({i__carry__1_i_1__0_n_0,i__carry__1_i_2_n_0,i__carry__1_i_3_n_0,i__carry__1_i_4_n_0})); + LUT6 #( + .INIT(64'h2A3A2A2AFFFFFFFF)) + top_of_frame_i_1 + (.I0(top_of_frame_reg_n_0), + .I1(top_of_frame141_out), + .I2(det_ce), + .I3(\DET_VSYNC.vsync_d2_reg_n_0 ), + .I4(\DET_VSYNC.vsync_d_reg_n_0 ), + .I5(resetn_out), + .O(top_of_frame_i_1_n_0)); + (* SOFT_HLUTNM = "soft_lutpair270" *) + LUT2 #( + .INIT(4'h2)) + top_of_frame_i_2 + (.I0(active_video_d), + .I1(active_video_d2), + .O(top_of_frame141_out)); + FDRE #( + .INIT(1'b1)) + top_of_frame_reg + (.C(clk), + .CE(1'b1), + .D(top_of_frame_i_1_n_0), + .Q(top_of_frame_reg_n_0), + .R(1'b0)); + LUT1 #( + .INIT(2'h1)) + \v_count[0]_i_1 + (.I0(v_count_reg__0[0]), + .O(plusOp__0[0])); + LUT6 #( + .INIT(64'hFFFFFFFFF8A80000)) + \v_count[10]_i_1 + (.I0(h_count0__0), + .I1(found_eof_reg_n_0), + .I2(p_0_in16_in), + .I3(leqOp_1), + .I4(det_ce), + .I5(h_count1), + .O(\v_count[10]_i_1_n_0 )); + LUT6 #( + .INIT(64'h7FFFFFFF80000000)) + \v_count[10]_i_2 + (.I0(v_count_reg__0[8]), + .I1(v_count_reg__0[6]), + .I2(\v_count[10]_i_5_n_0 ), + .I3(v_count_reg__0[7]), + .I4(v_count_reg__0[9]), + .I5(v_count_reg__0[10]), + .O(plusOp__0[10])); + (* SOFT_HLUTNM = "soft_lutpair291" *) + LUT3 #( + .INIT(8'h09)) + \v_count[10]_i_3 + (.I0(\time_status_regs[3] [1]), + .I1(hsync_in), + .I2(line_end_d_reg_n_0), + .O(h_count0__0)); + (* SOFT_HLUTNM = "soft_lutpair279" *) + LUT4 #( + .INIT(16'h4004)) + \v_count[10]_i_4 + (.I0(frame_end_d), + .I1(top_of_frame_reg_n_0), + .I2(\time_status_regs[3] [2]), + .I3(active_video_in), + .O(p_0_in16_in)); + LUT6 #( + .INIT(64'h8000000000000000)) + \v_count[10]_i_5 + (.I0(v_count_reg__0[5]), + .I1(v_count_reg__0[3]), + .I2(v_count_reg__0[1]), + .I3(v_count_reg__0[0]), + .I4(v_count_reg__0[2]), + .I5(v_count_reg__0[4]), + .O(\v_count[10]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair288" *) + LUT2 #( + .INIT(4'h6)) + \v_count[1]_i_1 + (.I0(v_count_reg__0[0]), + .I1(v_count_reg__0[1]), + .O(plusOp__0[1])); + (* SOFT_HLUTNM = "soft_lutpair288" *) + LUT3 #( + .INIT(8'h78)) + \v_count[2]_i_1 + (.I0(v_count_reg__0[0]), + .I1(v_count_reg__0[1]), + .I2(v_count_reg__0[2]), + .O(plusOp__0[2])); + (* SOFT_HLUTNM = "soft_lutpair276" *) + LUT4 #( + .INIT(16'h7F80)) + \v_count[3]_i_1 + (.I0(v_count_reg__0[1]), + .I1(v_count_reg__0[0]), + .I2(v_count_reg__0[2]), + .I3(v_count_reg__0[3]), + .O(plusOp__0[3])); + (* SOFT_HLUTNM = "soft_lutpair276" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \v_count[4]_i_1 + (.I0(v_count_reg__0[2]), + .I1(v_count_reg__0[0]), + .I2(v_count_reg__0[1]), + .I3(v_count_reg__0[3]), + .I4(v_count_reg__0[4]), + .O(plusOp__0[4])); + LUT6 #( + .INIT(64'h7FFFFFFF80000000)) + \v_count[5]_i_1 + (.I0(v_count_reg__0[3]), + .I1(v_count_reg__0[1]), + .I2(v_count_reg__0[0]), + .I3(v_count_reg__0[2]), + .I4(v_count_reg__0[4]), + .I5(v_count_reg__0[5]), + .O(plusOp__0[5])); + (* SOFT_HLUTNM = "soft_lutpair289" *) + LUT2 #( + .INIT(4'h6)) + \v_count[6]_i_1 + (.I0(\v_count[10]_i_5_n_0 ), + .I1(v_count_reg__0[6]), + .O(plusOp__0[6])); + (* SOFT_HLUTNM = "soft_lutpair289" *) + LUT3 #( + .INIT(8'h78)) + \v_count[7]_i_1 + (.I0(\v_count[10]_i_5_n_0 ), + .I1(v_count_reg__0[6]), + .I2(v_count_reg__0[7]), + .O(plusOp__0[7])); + (* SOFT_HLUTNM = "soft_lutpair271" *) + LUT4 #( + .INIT(16'h7F80)) + \v_count[8]_i_1 + (.I0(v_count_reg__0[6]), + .I1(\v_count[10]_i_5_n_0 ), + .I2(v_count_reg__0[7]), + .I3(v_count_reg__0[8]), + .O(plusOp__0[8])); + (* SOFT_HLUTNM = "soft_lutpair271" *) + LUT5 #( + .INIT(32'h7FFF8000)) + \v_count[9]_i_1 + (.I0(v_count_reg__0[7]), + .I1(\v_count[10]_i_5_n_0 ), + .I2(v_count_reg__0[6]), + .I3(v_count_reg__0[8]), + .I4(v_count_reg__0[9]), + .O(plusOp__0[9])); + FDRE #( + .INIT(1'b0)) + \v_count_last_reg[0] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(v_count_reg__0[0]), + .Q(v_count_last[0]), + .R(h_count1)); + FDRE #( + .INIT(1'b0)) + \v_count_last_reg[10] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(v_count_reg__0[10]), + .Q(v_count_last[10]), + .R(h_count1)); + FDRE #( + .INIT(1'b0)) + \v_count_last_reg[1] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(v_count_reg__0[1]), + .Q(v_count_last[1]), + .R(h_count1)); + FDRE #( + .INIT(1'b0)) + \v_count_last_reg[2] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(v_count_reg__0[2]), + .Q(v_count_last[2]), + .R(h_count1)); + FDRE #( + .INIT(1'b0)) + \v_count_last_reg[3] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(v_count_reg__0[3]), + .Q(v_count_last[3]), + .R(h_count1)); + FDRE #( + .INIT(1'b0)) + \v_count_last_reg[4] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(v_count_reg__0[4]), + .Q(v_count_last[4]), + .R(h_count1)); + FDRE #( + .INIT(1'b0)) + \v_count_last_reg[5] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(v_count_reg__0[5]), + .Q(v_count_last[5]), + .R(h_count1)); + FDRE #( + .INIT(1'b0)) + \v_count_last_reg[6] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(v_count_reg__0[6]), + .Q(v_count_last[6]), + .R(h_count1)); + FDRE #( + .INIT(1'b0)) + \v_count_last_reg[7] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(v_count_reg__0[7]), + .Q(v_count_last[7]), + .R(h_count1)); + FDRE #( + .INIT(1'b0)) + \v_count_last_reg[8] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(v_count_reg__0[8]), + .Q(v_count_last[8]), + .R(h_count1)); + FDRE #( + .INIT(1'b0)) + \v_count_last_reg[9] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(v_count_reg__0[9]), + .Q(v_count_last[9]), + .R(h_count1)); + FDRE #( + .INIT(1'b0)) + \v_count_reg[0] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(plusOp__0[0]), + .Q(v_count_reg__0[0]), + .R(\v_count[10]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \v_count_reg[10] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(plusOp__0[10]), + .Q(v_count_reg__0[10]), + .R(\v_count[10]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \v_count_reg[1] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(plusOp__0[1]), + .Q(v_count_reg__0[1]), + .R(\v_count[10]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \v_count_reg[2] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(plusOp__0[2]), + .Q(v_count_reg__0[2]), + .R(\v_count[10]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \v_count_reg[3] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(plusOp__0[3]), + .Q(v_count_reg__0[3]), + .R(\v_count[10]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \v_count_reg[4] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(plusOp__0[4]), + .Q(v_count_reg__0[4]), + .R(\v_count[10]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \v_count_reg[5] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(plusOp__0[5]), + .Q(v_count_reg__0[5]), + .R(\v_count[10]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \v_count_reg[6] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(plusOp__0[6]), + .Q(v_count_reg__0[6]), + .R(\v_count[10]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \v_count_reg[7] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(plusOp__0[7]), + .Q(v_count_reg__0[7]), + .R(\v_count[10]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \v_count_reg[8] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(plusOp__0[8]), + .Q(v_count_reg__0[8]), + .R(\v_count[10]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \v_count_reg[9] + (.C(clk), + .CE(\det_htotal_int[11]_i_1_n_0 ), + .D(plusOp__0[9]), + .Q(v_count_reg__0[9]), + .R(\v_count[10]_i_1_n_0 )); +endmodule + +(* ORIG_REF_NAME = "tc_top" *) +module Arty_Z7_20_v_tc_1_0_tc_top + (Q, + \time_status_regs[6] , + \time_status_regs[3] , + \time_status_regs_int_reg[0] , + intc_if, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10] , + \time_status_regs[8] , + \time_status_regs[7] , + \time_status_regs[9] , + clk, + clken, + active_video_in, + vblank_in, + hsync_in, + det_clken, + resetn_out, + \genr_control_regs[0] , + core_d_out, + vsync_in, + \time_control_regs[19] ); + output [11:0]Q; + output [23:0]\time_status_regs[6] ; + output [2:0]\time_status_regs[3] ; + output [22:0]\time_status_regs_int_reg[0] ; + output [8:0]intc_if; + output [10:0]\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10] ; + output [21:0]\time_status_regs[8] ; + output [23:0]\time_status_regs[7] ; + output [23:0]\time_status_regs[9] ; + input clk; + input clken; + input active_video_in; + input vblank_in; + input hsync_in; + input det_clken; + input resetn_out; + input [2:0]\genr_control_regs[0] ; + input core_d_out; + input vsync_in; + input [0:0]\time_control_regs[19] ; + + wire \GEN_DETECTION.U_tc_DET_n_68 ; + wire \GEN_DETECTION.U_tc_DET_n_69 ; + wire [10:0]\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10] ; + wire [11:0]Q; + wire active_video_in; + wire active_video_lock_int; + wire all_lock; + wire all_lock_d; + wire all_lock_d0; + wire all_lock_d_i_1_n_0; + wire clk; + wire clken; + wire core_d_out; + wire det_active_video_d; + wire det_ce; + wire det_clken; + wire det_vblank_d; + wire detect_en; + wire \detect_en_d_reg[1]_srl2___U_TC_TOP_detect_en_d_reg_r_3_n_0 ; + wire \detect_en_d_reg[2]_U_TC_TOP_detect_en_d_reg_r_4_n_0 ; + wire detect_en_d_reg_gate_n_0; + wire detect_en_d_reg_r_3_n_0; + wire detect_en_d_reg_r_4_n_0; + wire detect_en_d_reg_r_n_0; + wire generate_en; + wire [3:3]generate_en_d; + wire \generate_en_d_reg[1]_srl2___U_TC_TOP_detect_en_d_reg_r_3_n_0 ; + wire \generate_en_d_reg[2]_U_TC_TOP_detect_en_d_reg_r_4_n_0 ; + wire generate_en_d_reg_gate_n_0; + wire [2:0]\genr_control_regs[0] ; + wire hsync_in; + wire hsync_lock_int; + wire [8:0]intc_if; + wire intr_error_int; + wire intr_status_int17_out; + wire \intr_status_int[10]_i_1_n_0 ; + wire \intr_status_int[11]_i_1_n_0 ; + wire \intr_status_int[12]_i_1_n_0 ; + wire \intr_status_int[8]_i_1_n_0 ; + wire \intr_status_int[9]_i_1_n_0 ; + wire lost_lock; + wire lost_lock_i_1_n_0; + wire p_0_in; + wire reset; + wire resetn_out; + wire [0:0]\time_control_regs[19] ; + wire [2:0]\time_status_regs[3] ; + wire [23:0]\time_status_regs[6] ; + wire [23:0]\time_status_regs[7] ; + wire [21:0]\time_status_regs[8] ; + wire [23:0]\time_status_regs[9] ; + wire [22:0]\time_status_regs_int_reg[0] ; + wire vblank_in; + wire vsync_in; + wire vsync_lock_int; + + Arty_Z7_20_v_tc_1_0_tc_detector \GEN_DETECTION.U_tc_DET + (.\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] (\time_status_regs_int_reg[0] [11:0]), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10] (\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10] ), + .Q(Q), + .active_video_in(active_video_in), + .active_video_lock_int(active_video_lock_int), + .all_lock(all_lock), + .all_lock_d0(all_lock_d0), + .all_lock_reg(\GEN_DETECTION.U_tc_DET_n_69 ), + .clk(clk), + .clken(clken), + .core_d_out(core_d_out), + .det_active_video_d(det_active_video_d), + .det_ce(det_ce), + .det_clken(det_clken), + .det_vblank_d(det_vblank_d), + .\genr_control_regs[0] ({\genr_control_regs[0] [2],\genr_control_regs[0] [0]}), + .hsync_in(hsync_in), + .hsync_lock_int(hsync_lock_int), + .intc_if(intc_if[7]), + .intr_status_int17_out(intr_status_int17_out), + .\intr_status_int_reg[11] (\GEN_DETECTION.U_tc_DET_n_68 ), + .lost_lock(lost_lock), + .reset(reset), + .resetn_out(resetn_out), + .\time_status_regs[3] (\time_status_regs[3] ), + .\time_status_regs[6] (\time_status_regs[6] ), + .\time_status_regs[7] (\time_status_regs[7] ), + .\time_status_regs[8] (\time_status_regs[8] ), + .\time_status_regs[9] (\time_status_regs[9] ), + .\time_status_regs_int_reg[0] (\time_status_regs_int_reg[0] [22:12]), + .vblank_in(vblank_in), + .vsync_in(vsync_in), + .vsync_lock_int(vsync_lock_int)); + (* SOFT_HLUTNM = "soft_lutpair310" *) + LUT4 #( + .INIT(16'hFFE2)) + all_lock_d_i_1 + (.I0(all_lock_d), + .I1(det_ce), + .I2(all_lock), + .I3(all_lock_d0), + .O(all_lock_d_i_1_n_0)); + FDRE all_lock_d_reg + (.C(clk), + .CE(1'b1), + .D(all_lock_d_i_1_n_0), + .Q(all_lock_d), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair311" *) + LUT4 #( + .INIT(16'hF5F7)) + all_lock_i_2 + (.I0(resetn_out), + .I1(\genr_control_regs[0] [1]), + .I2(core_d_out), + .I3(\genr_control_regs[0] [0]), + .O(all_lock_d0)); + FDRE all_lock_reg + (.C(clk), + .CE(1'b1), + .D(\GEN_DETECTION.U_tc_DET_n_69 ), + .Q(all_lock), + .R(1'b0)); + FDRE det_active_video_d_reg + (.C(clk), + .CE(clken), + .D(active_video_in), + .Q(det_active_video_d), + .R(reset)); + FDRE det_vblank_d_reg + (.C(clk), + .CE(clken), + .D(vblank_in), + .Q(det_vblank_d), + .R(reset)); + (* srl_bus_name = "U0/\U_TC_TOP/detect_en_d_reg " *) + (* srl_name = "U0/\U_TC_TOP/detect_en_d_reg[1]_srl2___U_TC_TOP_detect_en_d_reg_r_3 " *) + SRL16E \detect_en_d_reg[1]_srl2___U_TC_TOP_detect_en_d_reg_r_3 + (.A0(1'b1), + .A1(1'b0), + .A2(1'b0), + .A3(1'b0), + .CE(clken), + .CLK(clk), + .D(detect_en), + .Q(\detect_en_d_reg[1]_srl2___U_TC_TOP_detect_en_d_reg_r_3_n_0 )); + LUT3 #( + .INIT(8'h32)) + \detect_en_d_reg[1]_srl2___U_TC_TOP_detect_en_d_reg_r_3_i_1 + (.I0(\genr_control_regs[0] [0]), + .I1(core_d_out), + .I2(\genr_control_regs[0] [2]), + .O(detect_en)); + FDRE \detect_en_d_reg[2]_U_TC_TOP_detect_en_d_reg_r_4 + (.C(clk), + .CE(clken), + .D(\detect_en_d_reg[1]_srl2___U_TC_TOP_detect_en_d_reg_r_3_n_0 ), + .Q(\detect_en_d_reg[2]_U_TC_TOP_detect_en_d_reg_r_4_n_0 ), + .R(1'b0)); + FDRE \detect_en_d_reg[3] + (.C(clk), + .CE(clken), + .D(detect_en_d_reg_gate_n_0), + .Q(p_0_in), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair312" *) + LUT2 #( + .INIT(4'h8)) + detect_en_d_reg_gate + (.I0(\detect_en_d_reg[2]_U_TC_TOP_detect_en_d_reg_r_4_n_0 ), + .I1(detect_en_d_reg_r_4_n_0), + .O(detect_en_d_reg_gate_n_0)); + FDRE detect_en_d_reg_r + (.C(clk), + .CE(clken), + .D(1'b1), + .Q(detect_en_d_reg_r_n_0), + .R(reset)); + FDRE detect_en_d_reg_r_3 + (.C(clk), + .CE(clken), + .D(detect_en_d_reg_r_n_0), + .Q(detect_en_d_reg_r_3_n_0), + .R(reset)); + FDRE detect_en_d_reg_r_4 + (.C(clk), + .CE(clken), + .D(detect_en_d_reg_r_3_n_0), + .Q(detect_en_d_reg_r_4_n_0), + .R(reset)); + (* srl_bus_name = "U0/\U_TC_TOP/generate_en_d_reg " *) + (* srl_name = "U0/\U_TC_TOP/generate_en_d_reg[1]_srl2___U_TC_TOP_detect_en_d_reg_r_3 " *) + SRL16E \generate_en_d_reg[1]_srl2___U_TC_TOP_detect_en_d_reg_r_3 + (.A0(1'b1), + .A1(1'b0), + .A2(1'b0), + .A3(1'b0), + .CE(clken), + .CLK(clk), + .D(generate_en), + .Q(\generate_en_d_reg[1]_srl2___U_TC_TOP_detect_en_d_reg_r_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair311" *) + LUT3 #( + .INIT(8'h32)) + \generate_en_d_reg[1]_srl2___U_TC_TOP_detect_en_d_reg_r_3_i_1 + (.I0(\genr_control_regs[0] [0]), + .I1(core_d_out), + .I2(\genr_control_regs[0] [1]), + .O(generate_en)); + FDRE \generate_en_d_reg[2]_U_TC_TOP_detect_en_d_reg_r_4 + (.C(clk), + .CE(clken), + .D(\generate_en_d_reg[1]_srl2___U_TC_TOP_detect_en_d_reg_r_3_n_0 ), + .Q(\generate_en_d_reg[2]_U_TC_TOP_detect_en_d_reg_r_4_n_0 ), + .R(1'b0)); + FDRE \generate_en_d_reg[3] + (.C(clk), + .CE(clken), + .D(generate_en_d_reg_gate_n_0), + .Q(generate_en_d), + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair312" *) + LUT2 #( + .INIT(4'h8)) + generate_en_d_reg_gate + (.I0(\generate_en_d_reg[2]_U_TC_TOP_detect_en_d_reg_r_4_n_0 ), + .I1(detect_en_d_reg_r_4_n_0), + .O(generate_en_d_reg_gate_n_0)); + LUT2 #( + .INIT(4'h8)) + \intr_error_int[6]_i_2 + (.I0(clken), + .I1(p_0_in), + .O(intr_error_int)); + FDRE #( + .INIT(1'b0)) + \intr_error_int_reg[2] + (.C(clk), + .CE(intr_error_int), + .D(vsync_lock_int), + .Q(intc_if[0]), + .R(reset)); + FDRE #( + .INIT(1'b0)) + \intr_error_int_reg[3] + (.C(clk), + .CE(intr_error_int), + .D(hsync_lock_int), + .Q(intc_if[1]), + .R(reset)); + FDRE #( + .INIT(1'b0)) + \intr_error_int_reg[4] + (.C(clk), + .CE(intr_error_int), + .D(active_video_lock_int), + .Q(intc_if[2]), + .R(reset)); + FDRE #( + .INIT(1'b0)) + \intr_error_int_reg[6] + (.C(clk), + .CE(intr_error_int), + .D(1'b1), + .Q(intc_if[3]), + .R(reset)); + LUT5 #( + .INIT(32'h3000AA00)) + \intr_status_int[10]_i_1 + (.I0(intc_if[6]), + .I1(vblank_in), + .I2(p_0_in), + .I3(resetn_out), + .I4(clken), + .O(\intr_status_int[10]_i_1_n_0 )); + LUT6 #( + .INIT(64'hD0FF000080000000)) + \intr_status_int[11]_i_1 + (.I0(active_video_lock_int), + .I1(\GEN_DETECTION.U_tc_DET_n_68 ), + .I2(p_0_in), + .I3(clken), + .I4(resetn_out), + .I5(intc_if[7]), + .O(\intr_status_int[11]_i_1_n_0 )); + LUT5 #( + .INIT(32'h3A000A00)) + \intr_status_int[12]_i_1 + (.I0(intc_if[8]), + .I1(\time_control_regs[19] ), + .I2(clken), + .I3(resetn_out), + .I4(generate_en_d), + .O(\intr_status_int[12]_i_1_n_0 )); + LUT5 #( + .INIT(32'hC000AA00)) + \intr_status_int[8]_i_1 + (.I0(intc_if[4]), + .I1(intr_status_int17_out), + .I2(p_0_in), + .I3(resetn_out), + .I4(clken), + .O(\intr_status_int[8]_i_1_n_0 )); + LUT5 #( + .INIT(32'h3000AA00)) + \intr_status_int[9]_i_1 + (.I0(intc_if[5]), + .I1(intr_status_int17_out), + .I2(p_0_in), + .I3(resetn_out), + .I4(clken), + .O(\intr_status_int[9]_i_1_n_0 )); + FDRE \intr_status_int_reg[10] + (.C(clk), + .CE(1'b1), + .D(\intr_status_int[10]_i_1_n_0 ), + .Q(intc_if[6]), + .R(1'b0)); + FDRE \intr_status_int_reg[11] + (.C(clk), + .CE(1'b1), + .D(\intr_status_int[11]_i_1_n_0 ), + .Q(intc_if[7]), + .R(1'b0)); + FDRE \intr_status_int_reg[12] + (.C(clk), + .CE(1'b1), + .D(\intr_status_int[12]_i_1_n_0 ), + .Q(intc_if[8]), + .R(1'b0)); + FDRE \intr_status_int_reg[8] + (.C(clk), + .CE(1'b1), + .D(\intr_status_int[8]_i_1_n_0 ), + .Q(intc_if[4]), + .R(1'b0)); + FDRE \intr_status_int_reg[9] + (.C(clk), + .CE(1'b1), + .D(\intr_status_int[9]_i_1_n_0 ), + .Q(intc_if[5]), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair310" *) + LUT5 #( + .INIT(32'h00002E22)) + lost_lock_i_1 + (.I0(lost_lock), + .I1(det_ce), + .I2(all_lock), + .I3(all_lock_d), + .I4(all_lock_d0), + .O(lost_lock_i_1_n_0)); + FDRE lost_lock_reg + (.C(clk), + .CE(1'b1), + .D(lost_lock_i_1_n_0), + .Q(lost_lock), + .R(1'b0)); +endmodule + +(* C_CONTROL = "0" *) (* C_DETECT_EN = "1" *) (* C_DET_ACHROMA_EN = "0" *) +(* C_DET_AVIDEO_EN = "1" *) (* C_DET_FIELDID_EN = "0" *) (* C_DET_HBLANK_EN = "0" *) +(* C_DET_HSYNC_EN = "1" *) (* C_DET_VBLANK_EN = "0" *) (* C_DET_VSYNC_EN = "1" *) +(* C_FAMILY = "virtex5" *) (* C_FSYNC_HSTART0 = "0" *) (* C_FSYNC_HSTART1 = "0" *) +(* C_FSYNC_HSTART10 = "0" *) (* C_FSYNC_HSTART11 = "0" *) (* C_FSYNC_HSTART12 = "0" *) +(* C_FSYNC_HSTART13 = "0" *) (* C_FSYNC_HSTART14 = "0" *) (* C_FSYNC_HSTART15 = "0" *) +(* C_FSYNC_HSTART2 = "0" *) (* C_FSYNC_HSTART3 = "0" *) (* C_FSYNC_HSTART4 = "0" *) +(* C_FSYNC_HSTART5 = "0" *) (* C_FSYNC_HSTART6 = "0" *) (* C_FSYNC_HSTART7 = "0" *) +(* C_FSYNC_HSTART8 = "0" *) (* C_FSYNC_HSTART9 = "0" *) (* C_FSYNC_VSTART0 = "0" *) +(* C_FSYNC_VSTART1 = "0" *) (* C_FSYNC_VSTART10 = "0" *) (* C_FSYNC_VSTART11 = "0" *) +(* C_FSYNC_VSTART12 = "0" *) (* C_FSYNC_VSTART13 = "0" *) (* C_FSYNC_VSTART14 = "0" *) +(* C_FSYNC_VSTART15 = "0" *) (* C_FSYNC_VSTART2 = "0" *) (* C_FSYNC_VSTART3 = "0" *) +(* C_FSYNC_VSTART4 = "0" *) (* C_FSYNC_VSTART5 = "0" *) (* C_FSYNC_VSTART6 = "0" *) +(* C_FSYNC_VSTART7 = "0" *) (* C_FSYNC_VSTART8 = "0" *) (* C_FSYNC_VSTART9 = "0" *) +(* C_GENERATE_EN = "0" *) (* C_GEN_ACHROMA_EN = "0" *) (* C_GEN_ACHROMA_POLARITY = "1" *) +(* C_GEN_AUTO_SWITCH = "0" *) (* C_GEN_AVIDEO_EN = "1" *) (* C_GEN_AVIDEO_POLARITY = "1" *) +(* C_GEN_CPARITY = "0" *) (* C_GEN_F0_VBLANK_HEND = "1280" *) (* C_GEN_F0_VBLANK_HSTART = "1280" *) +(* C_GEN_F0_VFRAME_SIZE = "750" *) (* C_GEN_F0_VSYNC_HEND = "1280" *) (* C_GEN_F0_VSYNC_HSTART = "1280" *) +(* C_GEN_F0_VSYNC_VEND = "729" *) (* C_GEN_F0_VSYNC_VSTART = "724" *) (* C_GEN_F1_VBLANK_HEND = "1280" *) +(* C_GEN_F1_VBLANK_HSTART = "1280" *) (* C_GEN_F1_VFRAME_SIZE = "750" *) (* C_GEN_F1_VSYNC_HEND = "1280" *) +(* C_GEN_F1_VSYNC_HSTART = "1280" *) (* C_GEN_F1_VSYNC_VEND = "729" *) (* C_GEN_F1_VSYNC_VSTART = "724" *) +(* C_GEN_FIELDID_EN = "0" *) (* C_GEN_FIELDID_POLARITY = "1" *) (* C_GEN_HACTIVE_SIZE = "1280" *) +(* C_GEN_HBLANK_EN = "1" *) (* C_GEN_HBLANK_POLARITY = "1" *) (* C_GEN_HFRAME_SIZE = "1650" *) +(* C_GEN_HSYNC_EN = "1" *) (* C_GEN_HSYNC_END = "1430" *) (* C_GEN_HSYNC_POLARITY = "1" *) +(* C_GEN_HSYNC_START = "1390" *) (* C_GEN_INTERLACED = "0" *) (* C_GEN_VACTIVE_SIZE = "720" *) +(* C_GEN_VBLANK_EN = "1" *) (* C_GEN_VBLANK_POLARITY = "1" *) (* C_GEN_VIDEO_FORMAT = "2" *) +(* C_GEN_VSYNC_EN = "1" *) (* C_GEN_VSYNC_POLARITY = "1" *) (* C_HAS_AXI4_LITE = "1" *) +(* C_HAS_INTC_IF = "1" *) (* C_INTERLACE_EN = "0" *) (* C_IRQEN = "0" *) +(* C_LINE_DELAY = "0" *) (* C_MAX_LINES = "2048" *) (* C_MAX_PIXELS = "4096" *) +(* C_NUM_FSYNCS = "1" *) (* C_PIXEL_DELAY = "0" *) (* C_SYNC_EN = "0" *) +(* C_S_AXI_ADDR_WIDTH = "9" *) (* C_S_AXI_CLK_FREQ_HZ = "100000000" *) (* C_S_AXI_DATA_WIDTH = "32" *) +(* ORIG_REF_NAME = "v_tc" *) (* downgradeipidentifiedwarnings = "yes" *) +module Arty_Z7_20_v_tc_1_0_v_tc + (s_axi_aclk, + s_axi_aclken, + s_axi_aresetn, + clk, + clken, + resetn, + det_clken, + gen_clken, + intc_if, + hsync_in, + hblank_in, + vsync_in, + vblank_in, + field_id_in, + active_video_in, + active_chroma_in, + fsync_in, + fsync_out, + hsync_out, + hblank_out, + vsync_out, + vblank_out, + field_id_out, + active_video_out, + active_chroma_out, + s_axi_awaddr, + s_axi_awvalid, + s_axi_awready, + s_axi_wdata, + s_axi_wstrb, + s_axi_wvalid, + s_axi_wready, + s_axi_bresp, + s_axi_bvalid, + s_axi_bready, + s_axi_araddr, + s_axi_arvalid, + s_axi_arready, + s_axi_rdata, + s_axi_rresp, + s_axi_rvalid, + s_axi_rready, + irq); + (* sigis = "CLK" *) input s_axi_aclk; + input s_axi_aclken; + (* sigis = "RST" *) input s_axi_aresetn; + (* sigis = "CLK" *) input clk; + input clken; + (* sigis = "RST" *) input resetn; + input det_clken; + input gen_clken; + output [31:0]intc_if; + input hsync_in; + input hblank_in; + input vsync_in; + input vblank_in; + input field_id_in; + input active_video_in; + input active_chroma_in; + input fsync_in; + output [0:0]fsync_out; + output hsync_out; + output hblank_out; + output vsync_out; + output vblank_out; + output field_id_out; + output active_video_out; + output active_chroma_out; + input [8:0]s_axi_awaddr; + input s_axi_awvalid; + output s_axi_awready; + input [31:0]s_axi_wdata; + input [3:0]s_axi_wstrb; + input s_axi_wvalid; + output s_axi_wready; + output [1:0]s_axi_bresp; + output s_axi_bvalid; + input s_axi_bready; + input [8:0]s_axi_araddr; + input s_axi_arvalid; + output s_axi_arready; + output [31:0]s_axi_rdata; + output [1:0]s_axi_rresp; + output s_axi_rvalid; + input s_axi_rready; + (* sigis = "INTR_LEVEL_HIGH" *) output irq; + + wire \ ; + wire U_VIDEO_CTRL_n_1022; + wire U_VIDEO_CTRL_n_1023; + wire U_VIDEO_CTRL_n_1024; + wire U_VIDEO_CTRL_n_1025; + wire U_VIDEO_CTRL_n_1054; + wire U_VIDEO_CTRL_n_1055; + wire U_VIDEO_CTRL_n_1056; + wire U_VIDEO_CTRL_n_1057; + wire U_VIDEO_CTRL_n_1086; + wire U_VIDEO_CTRL_n_1087; + wire U_VIDEO_CTRL_n_1088; + wire U_VIDEO_CTRL_n_1089; + wire U_VIDEO_CTRL_n_1090; + wire U_VIDEO_CTRL_n_1118; + wire U_VIDEO_CTRL_n_1119; + wire U_VIDEO_CTRL_n_1120; + wire U_VIDEO_CTRL_n_1121; + wire U_VIDEO_CTRL_n_1150; + wire U_VIDEO_CTRL_n_1151; + wire U_VIDEO_CTRL_n_1152; + wire U_VIDEO_CTRL_n_1153; + wire U_VIDEO_CTRL_n_1662; + wire U_VIDEO_CTRL_n_1663; + wire U_VIDEO_CTRL_n_1664; + wire U_VIDEO_CTRL_n_1665; + wire U_VIDEO_CTRL_n_734; + wire U_VIDEO_CTRL_n_735; + wire U_VIDEO_CTRL_n_736; + wire U_VIDEO_CTRL_n_737; + wire U_VIDEO_CTRL_n_806; + wire U_VIDEO_CTRL_n_808; + wire U_VIDEO_CTRL_n_809; + wire U_VIDEO_CTRL_n_810; + wire U_VIDEO_CTRL_n_811; + wire U_VIDEO_CTRL_n_894; + wire U_VIDEO_CTRL_n_895; + wire U_VIDEO_CTRL_n_896; + wire U_VIDEO_CTRL_n_897; + wire U_VIDEO_CTRL_n_898; + wire U_VIDEO_CTRL_n_926; + wire U_VIDEO_CTRL_n_927; + wire U_VIDEO_CTRL_n_928; + wire U_VIDEO_CTRL_n_929; + wire U_VIDEO_CTRL_n_958; + wire U_VIDEO_CTRL_n_959; + wire U_VIDEO_CTRL_n_960; + wire U_VIDEO_CTRL_n_961; + wire U_VIDEO_CTRL_n_990; + wire U_VIDEO_CTRL_n_991; + wire U_VIDEO_CTRL_n_992; + wire U_VIDEO_CTRL_n_993; + wire U_VIDEO_CTRL_n_994; + wire active_video_in; + wire clk; + wire clken; + wire [26:0]\core_control_regs[0] ; + wire [26:0]\core_control_regs[16] ; + wire core_d; + wire det_clken; + wire field_id_in; + wire [0:0]gen_v0chroma_start; + wire \gen_v0chroma_start[0]_i_1_n_0 ; + wire [31:0]\genr_control_regs[0] ; + wire hsync_in; + wire [12:2]\^intc_if ; + wire irq; + wire reg_update; + wire resetn; + wire s_axi_aclk; + wire s_axi_aclken; + wire [8:0]s_axi_araddr; + wire s_axi_aresetn; + wire s_axi_arready; + wire s_axi_arvalid; + wire [8:0]s_axi_awaddr; + wire s_axi_awready; + wire s_axi_awvalid; + wire s_axi_bready; + wire [1:0]s_axi_bresp; + wire s_axi_bvalid; + wire [31:0]s_axi_rdata; + wire s_axi_rready; + wire [1:0]s_axi_rresp; + wire s_axi_rvalid; + wire [31:0]s_axi_wdata; + wire s_axi_wready; + wire [3:0]s_axi_wstrb; + wire s_axi_wvalid; + wire [26:0]\time_control_regs[16] ; + wire [9:0]\time_control_regs[18] ; + wire [6:0]\time_control_regs[19] ; + wire [11:0]\time_control_regs[20] ; + wire [26:0]\time_control_regs[21] ; + wire [27:0]\time_control_regs[22] ; + wire [27:0]\time_control_regs[23] ; + wire [26:0]\time_control_regs[24] ; + wire [27:0]\time_control_regs[25] ; + wire [27:0]\time_control_regs[26] ; + wire [26:0]\time_control_regs[27] ; + wire [27:0]\time_control_regs[28] ; + wire [26:0]\time_status_regs_int_reg[0] ; + wire [4:2]\time_status_regs_int_reg[3] ; + wire [11:0]\time_status_regs_int_reg[4] ; + wire [10:0]\time_status_regs_int_reg[5] ; + wire [27:0]\time_status_regs_int_reg[6] ; + wire [27:0]\time_status_regs_int_reg[7] ; + wire [26:0]\time_status_regs_int_reg[8] ; + wire [27:0]\time_status_regs_int_reg[9] ; + wire vblank_in; + (* MAX_FANOUT = "128" *) (* RTL_MAX_FANOUT = "found" *) wire vresetn; + wire vsync_in; + wire NLW_U_VIDEO_CTRL_ipif_cs_out_UNCONNECTED; + wire NLW_U_VIDEO_CTRL_ipif_rnw_out_UNCONNECTED; + wire [31:27]\NLW_U_VIDEO_CTRL_core_control_regs[0]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_core_control_regs[10]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_core_control_regs[11]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_core_control_regs[12]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_core_control_regs[13]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_core_control_regs[14]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_core_control_regs[15]_UNCONNECTED ; + wire [31:27]\NLW_U_VIDEO_CTRL_core_control_regs[16]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_core_control_regs[1]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_core_control_regs[2]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_core_control_regs[3]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_core_control_regs[4]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_core_control_regs[5]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_core_control_regs[6]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_core_control_regs[7]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_core_control_regs[8]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_core_control_regs[9]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_genr_control_regs[1]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_genr_control_regs[2]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_genr_control_regs[3]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_genr_control_regs[4]_UNCONNECTED ; + wire [8:0]NLW_U_VIDEO_CTRL_ipif_addr_out_UNCONNECTED; + wire [31:0]NLW_U_VIDEO_CTRL_ipif_data_out_UNCONNECTED; + wire [31:0]\NLW_U_VIDEO_CTRL_time_control_regs[0]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_time_control_regs[10]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_time_control_regs[11]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_time_control_regs[12]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_time_control_regs[13]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_time_control_regs[14]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_time_control_regs[15]_UNCONNECTED ; + wire [31:27]\NLW_U_VIDEO_CTRL_time_control_regs[16]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_time_control_regs[17]_UNCONNECTED ; + wire [31:10]\NLW_U_VIDEO_CTRL_time_control_regs[18]_UNCONNECTED ; + wire [31:7]\NLW_U_VIDEO_CTRL_time_control_regs[19]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_time_control_regs[1]_UNCONNECTED ; + wire [31:12]\NLW_U_VIDEO_CTRL_time_control_regs[20]_UNCONNECTED ; + wire [31:27]\NLW_U_VIDEO_CTRL_time_control_regs[21]_UNCONNECTED ; + wire [31:28]\NLW_U_VIDEO_CTRL_time_control_regs[22]_UNCONNECTED ; + wire [31:28]\NLW_U_VIDEO_CTRL_time_control_regs[23]_UNCONNECTED ; + wire [31:27]\NLW_U_VIDEO_CTRL_time_control_regs[24]_UNCONNECTED ; + wire [31:28]\NLW_U_VIDEO_CTRL_time_control_regs[25]_UNCONNECTED ; + wire [31:28]\NLW_U_VIDEO_CTRL_time_control_regs[26]_UNCONNECTED ; + wire [31:27]\NLW_U_VIDEO_CTRL_time_control_regs[27]_UNCONNECTED ; + wire [31:28]\NLW_U_VIDEO_CTRL_time_control_regs[28]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_time_control_regs[2]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_time_control_regs[3]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_time_control_regs[4]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_time_control_regs[5]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_time_control_regs[6]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_time_control_regs[7]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_time_control_regs[8]_UNCONNECTED ; + wire [31:0]\NLW_U_VIDEO_CTRL_time_control_regs[9]_UNCONNECTED ; + + assign active_chroma_out = \ ; + assign active_video_out = \ ; + assign field_id_out = \ ; + assign fsync_out[0] = \ ; + assign hblank_out = \ ; + assign hsync_out = \ ; + assign intc_if[31] = \ ; + assign intc_if[30] = \ ; + assign intc_if[29] = \ ; + assign intc_if[28] = \ ; + assign intc_if[27] = \ ; + assign intc_if[26] = \ ; + assign intc_if[25] = \ ; + assign intc_if[24] = \ ; + assign intc_if[23] = \ ; + assign intc_if[22] = \ ; + assign intc_if[21] = \ ; + assign intc_if[20] = \ ; + assign intc_if[19] = \ ; + assign intc_if[18] = \ ; + assign intc_if[17] = \ ; + assign intc_if[16] = \ ; + assign intc_if[15] = \ ; + assign intc_if[14] = \ ; + assign intc_if[13] = \ ; + assign intc_if[12:8] = \^intc_if [12:8]; + assign intc_if[7] = \ ; + assign intc_if[6] = \^intc_if [5]; + assign intc_if[5:2] = \^intc_if [5:2]; + assign intc_if[1] = \^intc_if [5]; + assign intc_if[0] = \^intc_if [5]; + assign vblank_out = \ ; + assign vsync_out = \ ; + GND GND + (.G(\ )); + Arty_Z7_20_v_tc_1_0_tc_top U_TC_TOP + (.\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10] (\time_status_regs_int_reg[5] ), + .Q(\time_status_regs_int_reg[4] ), + .active_video_in(active_video_in), + .clk(clk), + .clken(clken), + .core_d_out(core_d), + .det_clken(det_clken), + .\genr_control_regs[0] ({\genr_control_regs[0] [3:2],\genr_control_regs[0] [0]}), + .hsync_in(hsync_in), + .intc_if({\^intc_if [12:8],\^intc_if [5:2]}), + .resetn_out(vresetn), + .\time_control_regs[19] (\time_control_regs[19] [0]), + .\time_status_regs[3] (\time_status_regs_int_reg[3] ), + .\time_status_regs[6] ({\time_status_regs_int_reg[6] [27:16],\time_status_regs_int_reg[6] [11:0]}), + .\time_status_regs[7] ({\time_status_regs_int_reg[7] [27:16],\time_status_regs_int_reg[7] [11:0]}), + .\time_status_regs[8] ({\time_status_regs_int_reg[8] [26:16],\time_status_regs_int_reg[8] [10:0]}), + .\time_status_regs[9] ({\time_status_regs_int_reg[9] [27:16],\time_status_regs_int_reg[9] [11:0]}), + .\time_status_regs_int_reg[0] ({\time_status_regs_int_reg[0] [26:16],\time_status_regs_int_reg[0] [11:0]}), + .vblank_in(vblank_in), + .vsync_in(vsync_in)); + (* C_COREGEN_PATCH = "0" *) + (* C_CORE_AXI_WRITE = "544'b0000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111" *) + (* C_CORE_DBUFFER = "544'b0000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000000000000000000000000000000" *) + (* C_CORE_DEFAULT = "544'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) + (* C_CORE_NUM_REGS = "17" *) + (* C_FAMILY = "virtex5" *) + (* C_GENR_AXI_WRITE = "160'b1100011111111111111011110010111111111111111111110011111100000000000000000011111100000000000000001111111111111111001111110000000000000000000000000000000000000000" *) + (* C_GENR_DBUFFER = "160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) + (* C_GENR_DEFAULT = "160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) + (* C_GENR_NUM_REGS = "5" *) + (* C_GENR_SELFCLR = "256'b0000000000000000000000000000000011111111111111111111111111111111111111111111111111111111111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) + (* C_HAS_AXI4_LITE = "1" *) + (* C_HAS_IRQ = "1" *) + (* C_IS_EVAL = "FALSE" *) + (* C_REVISION_NUMBER = "11" *) + (* C_SRESET_LENGTH = "2" *) + (* C_S_AXI_ADDR_WIDTH = "9" *) + (* C_S_AXI_DATA_WIDTH = "32" *) + (* C_TIMEOUT_HOURS = "8" *) + (* C_TIMEOUT_MINS = "0" *) + (* C_TIME_AXI_WRITE = "928'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111111110001111111111111000000000000000000000000000000000000000000000000000000111100111100000000000000000000000001111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111" *) + (* C_TIME_DBUFFER = "928'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111111110001111111111111000000000000000000000000000000000000000000000000000000111000000000000000000000000000000000111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111" *) + (* C_TIME_DEFAULT = "928'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010110100000000010100000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000001111111000000000000000000000110011100100000001011101110000000101110111000000101100101100000010101101110000001010000000000000101000000000000001011011001000000101101010000000101000000000000010100000000000001010000000000000101000000000000001011011001000000101101010000000101000000000000010100000000" *) + (* C_TIME_NUM_REGS = "29" *) + (* C_VERSION_MAJOR = "6" *) + (* C_VERSION_MINOR = "1" *) + (* C_VERSION_REVISION = "0" *) + (* downgradeipidentifiedwarnings = "yes" *) + Arty_Z7_20_v_tc_1_0_video_ctrl U_VIDEO_CTRL + (.aclk(s_axi_aclk), + .aclk_en(s_axi_aclken), + .aresetn(s_axi_aresetn), + .\core_control_regs[0] ({\NLW_U_VIDEO_CTRL_core_control_regs[0]_UNCONNECTED [31:27],\core_control_regs[0] [26:16],U_VIDEO_CTRL_n_1150,U_VIDEO_CTRL_n_1151,U_VIDEO_CTRL_n_1152,U_VIDEO_CTRL_n_1153,\core_control_regs[0] [11:0]}), + .\core_control_regs[10] (\NLW_U_VIDEO_CTRL_core_control_regs[10]_UNCONNECTED [31:0]), + .\core_control_regs[11] (\NLW_U_VIDEO_CTRL_core_control_regs[11]_UNCONNECTED [31:0]), + .\core_control_regs[12] (\NLW_U_VIDEO_CTRL_core_control_regs[12]_UNCONNECTED [31:0]), + .\core_control_regs[13] (\NLW_U_VIDEO_CTRL_core_control_regs[13]_UNCONNECTED [31:0]), + .\core_control_regs[14] (\NLW_U_VIDEO_CTRL_core_control_regs[14]_UNCONNECTED [31:0]), + .\core_control_regs[15] (\NLW_U_VIDEO_CTRL_core_control_regs[15]_UNCONNECTED [31:0]), + .\core_control_regs[16] ({\NLW_U_VIDEO_CTRL_core_control_regs[16]_UNCONNECTED [31:27],\core_control_regs[16] [26:16],U_VIDEO_CTRL_n_1662,U_VIDEO_CTRL_n_1663,U_VIDEO_CTRL_n_1664,U_VIDEO_CTRL_n_1665,\core_control_regs[16] [11:0]}), + .\core_control_regs[1] (\NLW_U_VIDEO_CTRL_core_control_regs[1]_UNCONNECTED [31:0]), + .\core_control_regs[2] (\NLW_U_VIDEO_CTRL_core_control_regs[2]_UNCONNECTED [31:0]), + .\core_control_regs[3] (\NLW_U_VIDEO_CTRL_core_control_regs[3]_UNCONNECTED [31:0]), + .\core_control_regs[4] (\NLW_U_VIDEO_CTRL_core_control_regs[4]_UNCONNECTED [31:0]), + .\core_control_regs[5] (\NLW_U_VIDEO_CTRL_core_control_regs[5]_UNCONNECTED [31:0]), + .\core_control_regs[6] (\NLW_U_VIDEO_CTRL_core_control_regs[6]_UNCONNECTED [31:0]), + .\core_control_regs[7] (\NLW_U_VIDEO_CTRL_core_control_regs[7]_UNCONNECTED [31:0]), + .\core_control_regs[8] (\NLW_U_VIDEO_CTRL_core_control_regs[8]_UNCONNECTED [31:0]), + .\core_control_regs[9] (\NLW_U_VIDEO_CTRL_core_control_regs[9]_UNCONNECTED [31:0]), + .core_d_out(core_d), + .\core_status_regs[0] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\core_status_regs[10] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\core_status_regs[11] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\core_status_regs[12] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\core_status_regs[13] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\core_status_regs[14] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\core_status_regs[15] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\core_status_regs[16] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\core_status_regs[1] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\core_status_regs[2] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\core_status_regs[3] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\core_status_regs[4] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\core_status_regs[5] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\core_status_regs[6] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\core_status_regs[7] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\core_status_regs[8] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\core_status_regs[9] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\genr_control_regs[0] (\genr_control_regs[0] ), + .\genr_control_regs[1] (\NLW_U_VIDEO_CTRL_genr_control_regs[1]_UNCONNECTED [31:0]), + .\genr_control_regs[2] (\NLW_U_VIDEO_CTRL_genr_control_regs[2]_UNCONNECTED [31:0]), + .\genr_control_regs[3] (\NLW_U_VIDEO_CTRL_genr_control_regs[3]_UNCONNECTED [31:0]), + .\genr_control_regs[4] (\NLW_U_VIDEO_CTRL_genr_control_regs[4]_UNCONNECTED [31:0]), + .\genr_status_regs[0] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\genr_status_regs[1] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^intc_if [12:8],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\genr_status_regs[2] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^intc_if [5],\^intc_if [5:2],\^intc_if [5],\^intc_if [5],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\genr_status_regs[3] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\genr_status_regs[4] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .ipif_addr_out(NLW_U_VIDEO_CTRL_ipif_addr_out_UNCONNECTED[8:0]), + .ipif_cs_out(NLW_U_VIDEO_CTRL_ipif_cs_out_UNCONNECTED), + .ipif_data_out(NLW_U_VIDEO_CTRL_ipif_data_out_UNCONNECTED[31:0]), + .ipif_rnw_out(NLW_U_VIDEO_CTRL_ipif_rnw_out_UNCONNECTED), + .irq(irq), + .reg_update(reg_update), + .resetn_out(vresetn), + .s_axi_araddr(s_axi_araddr), + .s_axi_arready(s_axi_arready), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awready(s_axi_awready), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_bready(s_axi_bready), + .s_axi_bresp(s_axi_bresp), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_rdata(s_axi_rdata), + .s_axi_rready(s_axi_rready), + .s_axi_rresp(s_axi_rresp), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_wdata(s_axi_wdata), + .s_axi_wready(s_axi_wready), + .s_axi_wstrb(s_axi_wstrb), + .s_axi_wvalid(s_axi_wvalid), + .\time_control_regs[0] (\NLW_U_VIDEO_CTRL_time_control_regs[0]_UNCONNECTED [31:0]), + .\time_control_regs[10] (\NLW_U_VIDEO_CTRL_time_control_regs[10]_UNCONNECTED [31:0]), + .\time_control_regs[11] (\NLW_U_VIDEO_CTRL_time_control_regs[11]_UNCONNECTED [31:0]), + .\time_control_regs[12] (\NLW_U_VIDEO_CTRL_time_control_regs[12]_UNCONNECTED [31:0]), + .\time_control_regs[13] (\NLW_U_VIDEO_CTRL_time_control_regs[13]_UNCONNECTED [31:0]), + .\time_control_regs[14] (\NLW_U_VIDEO_CTRL_time_control_regs[14]_UNCONNECTED [31:0]), + .\time_control_regs[15] (\NLW_U_VIDEO_CTRL_time_control_regs[15]_UNCONNECTED [31:0]), + .\time_control_regs[16] ({\NLW_U_VIDEO_CTRL_time_control_regs[16]_UNCONNECTED [31:27],\time_control_regs[16] [26:16],U_VIDEO_CTRL_n_734,U_VIDEO_CTRL_n_735,U_VIDEO_CTRL_n_736,U_VIDEO_CTRL_n_737,\time_control_regs[16] [11:0]}), + .\time_control_regs[17] (\NLW_U_VIDEO_CTRL_time_control_regs[17]_UNCONNECTED [31:0]), + .\time_control_regs[18] ({\NLW_U_VIDEO_CTRL_time_control_regs[18]_UNCONNECTED [31:10],\time_control_regs[18] [9:8],U_VIDEO_CTRL_n_806,\time_control_regs[18] [6],U_VIDEO_CTRL_n_808,U_VIDEO_CTRL_n_809,U_VIDEO_CTRL_n_810,U_VIDEO_CTRL_n_811,\time_control_regs[18] [1:0]}), + .\time_control_regs[19] ({\NLW_U_VIDEO_CTRL_time_control_regs[19]_UNCONNECTED [31:7],\time_control_regs[19] }), + .\time_control_regs[1] (\NLW_U_VIDEO_CTRL_time_control_regs[1]_UNCONNECTED [31:0]), + .\time_control_regs[20] ({\NLW_U_VIDEO_CTRL_time_control_regs[20]_UNCONNECTED [31:12],\time_control_regs[20] }), + .\time_control_regs[21] ({\NLW_U_VIDEO_CTRL_time_control_regs[21]_UNCONNECTED [31:27],\time_control_regs[21] [26:16],U_VIDEO_CTRL_n_894,U_VIDEO_CTRL_n_895,U_VIDEO_CTRL_n_896,U_VIDEO_CTRL_n_897,U_VIDEO_CTRL_n_898,\time_control_regs[21] [10:0]}), + .\time_control_regs[22] ({\NLW_U_VIDEO_CTRL_time_control_regs[22]_UNCONNECTED [31:28],\time_control_regs[22] [27:16],U_VIDEO_CTRL_n_926,U_VIDEO_CTRL_n_927,U_VIDEO_CTRL_n_928,U_VIDEO_CTRL_n_929,\time_control_regs[22] [11:0]}), + .\time_control_regs[23] ({\NLW_U_VIDEO_CTRL_time_control_regs[23]_UNCONNECTED [31:28],\time_control_regs[23] [27:16],U_VIDEO_CTRL_n_958,U_VIDEO_CTRL_n_959,U_VIDEO_CTRL_n_960,U_VIDEO_CTRL_n_961,\time_control_regs[23] [11:0]}), + .\time_control_regs[24] ({\NLW_U_VIDEO_CTRL_time_control_regs[24]_UNCONNECTED [31:27],\time_control_regs[24] [26:16],U_VIDEO_CTRL_n_990,U_VIDEO_CTRL_n_991,U_VIDEO_CTRL_n_992,U_VIDEO_CTRL_n_993,U_VIDEO_CTRL_n_994,\time_control_regs[24] [10:0]}), + .\time_control_regs[25] ({\NLW_U_VIDEO_CTRL_time_control_regs[25]_UNCONNECTED [31:28],\time_control_regs[25] [27:16],U_VIDEO_CTRL_n_1022,U_VIDEO_CTRL_n_1023,U_VIDEO_CTRL_n_1024,U_VIDEO_CTRL_n_1025,\time_control_regs[25] [11:0]}), + .\time_control_regs[26] ({\NLW_U_VIDEO_CTRL_time_control_regs[26]_UNCONNECTED [31:28],\time_control_regs[26] [27:16],U_VIDEO_CTRL_n_1054,U_VIDEO_CTRL_n_1055,U_VIDEO_CTRL_n_1056,U_VIDEO_CTRL_n_1057,\time_control_regs[26] [11:0]}), + .\time_control_regs[27] ({\NLW_U_VIDEO_CTRL_time_control_regs[27]_UNCONNECTED [31:27],\time_control_regs[27] [26:16],U_VIDEO_CTRL_n_1086,U_VIDEO_CTRL_n_1087,U_VIDEO_CTRL_n_1088,U_VIDEO_CTRL_n_1089,U_VIDEO_CTRL_n_1090,\time_control_regs[27] [10:0]}), + .\time_control_regs[28] ({\NLW_U_VIDEO_CTRL_time_control_regs[28]_UNCONNECTED [31:28],\time_control_regs[28] [27:16],U_VIDEO_CTRL_n_1118,U_VIDEO_CTRL_n_1119,U_VIDEO_CTRL_n_1120,U_VIDEO_CTRL_n_1121,\time_control_regs[28] [11:0]}), + .\time_control_regs[2] (\NLW_U_VIDEO_CTRL_time_control_regs[2]_UNCONNECTED [31:0]), + .\time_control_regs[3] (\NLW_U_VIDEO_CTRL_time_control_regs[3]_UNCONNECTED [31:0]), + .\time_control_regs[4] (\NLW_U_VIDEO_CTRL_time_control_regs[4]_UNCONNECTED [31:0]), + .\time_control_regs[5] (\NLW_U_VIDEO_CTRL_time_control_regs[5]_UNCONNECTED [31:0]), + .\time_control_regs[6] (\NLW_U_VIDEO_CTRL_time_control_regs[6]_UNCONNECTED [31:0]), + .\time_control_regs[7] (\NLW_U_VIDEO_CTRL_time_control_regs[7]_UNCONNECTED [31:0]), + .\time_control_regs[8] (\NLW_U_VIDEO_CTRL_time_control_regs[8]_UNCONNECTED [31:0]), + .\time_control_regs[9] (\NLW_U_VIDEO_CTRL_time_control_regs[9]_UNCONNECTED [31:0]), + .\time_status_regs[0] ({1'b0,1'b0,1'b0,1'b0,1'b0,\time_status_regs_int_reg[0] [26:16],1'b0,1'b0,1'b0,1'b0,\time_status_regs_int_reg[0] [11:0]}), + .\time_status_regs[10] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\time_status_regs[11] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\time_status_regs[12] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\time_status_regs[13] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\time_status_regs[14] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\time_status_regs[15] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\time_status_regs[16] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\time_status_regs[17] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^intc_if [12],1'b0}), + .\time_status_regs[18] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\time_status_regs[19] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\time_status_regs[1] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\^intc_if [11:10],\^intc_if [8]}), + .\time_status_regs[20] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\time_status_regs[21] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\time_status_regs[22] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\time_status_regs[23] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\time_status_regs[24] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\time_status_regs[25] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\time_status_regs[26] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\time_status_regs[27] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\time_status_regs[28] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\time_status_regs[2] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,gen_v0chroma_start,field_id_in,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .\time_status_regs[3] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\time_status_regs_int_reg[3] ,1'b0,1'b0}), + .\time_status_regs[4] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\time_status_regs_int_reg[4] }), + .\time_status_regs[5] ({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\time_status_regs_int_reg[5] }), + .\time_status_regs[6] ({1'b0,1'b0,1'b0,1'b0,\time_status_regs_int_reg[6] [27:16],1'b0,1'b0,1'b0,1'b0,\time_status_regs_int_reg[6] [11:0]}), + .\time_status_regs[7] ({1'b0,1'b0,1'b0,1'b0,\time_status_regs_int_reg[7] [27:16],1'b0,1'b0,1'b0,1'b0,\time_status_regs_int_reg[7] [11:0]}), + .\time_status_regs[8] ({1'b0,1'b0,1'b0,1'b0,1'b0,\time_status_regs_int_reg[8] [26:16],1'b0,1'b0,1'b0,1'b0,1'b0,\time_status_regs_int_reg[8] [10:0]}), + .\time_status_regs[9] ({1'b0,1'b0,1'b0,1'b0,\time_status_regs_int_reg[9] [27:16],1'b0,1'b0,1'b0,1'b0,\time_status_regs_int_reg[9] [11:0]}), + .vid_aclk(clk), + .vid_aclk_en(clken), + .vid_aresetn(resetn)); + LUT3 #( + .INIT(8'hCD)) + U_VIDEO_CTRL_i_1 + (.I0(\genr_control_regs[0] [2]), + .I1(core_d), + .I2(\genr_control_regs[0] [0]), + .O(reg_update)); + LUT6 #( + .INIT(64'hCA0A0A0A00000000)) + \gen_v0chroma_start[0]_i_1 + (.I0(gen_v0chroma_start), + .I1(\time_control_regs[18] [8]), + .I2(clken), + .I3(\time_control_regs[18] [1]), + .I4(\time_control_regs[18] [0]), + .I5(resetn), + .O(\gen_v0chroma_start[0]_i_1_n_0 )); + FDRE \gen_v0chroma_start_reg[0] + (.C(clk), + .CE(1'b1), + .D(\gen_v0chroma_start[0]_i_1_n_0 ), + .Q(gen_v0chroma_start), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "video_clock_cross" *) +module Arty_Z7_20_v_tc_1_0_video_clock_cross + (\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][31] , + out_data, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][30] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][29] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][28] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][27] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][26] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][25] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][24] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][23] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][22] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][21] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][20] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][19] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][18] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][17] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][16] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][13] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][12] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][11] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][10] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][9] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][8] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][21] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][20] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][19] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][18] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][17] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][16] , + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31] , + p_533_out, + p_535_out, + p_456_out, + E, + ipif_Addr, + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][0] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][0] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][0] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][0] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][0] , + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][0] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][0] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][0] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][0] , + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][8] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][0] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][0] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][0] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][0] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][7] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][31] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] , + \GEN_TREE.GEN_BRANCH[33].GEN_MUX_REG.data_out_reg_reg[33][26] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][0] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][1] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][2] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][3] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][4] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][5] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][6] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][7] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][8] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][9] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][10] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][11] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][12] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][13] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][14] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][15] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][16] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][17] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][18] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][19] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][20] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][21] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][22] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][23] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][24] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][25] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][26] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][27] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][28] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][29] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][30] , + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][31] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][0] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][1] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][2] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][3] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][4] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][5] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][6] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][7] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][8] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][9] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][10] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][11] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][12] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][13] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][14] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][15] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][16] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][17] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][18] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][19] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][20] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][21] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][22] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][23] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][24] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][25] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][26] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][27] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][28] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][29] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][30] , + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][31] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][0] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][1] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][2] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][3] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][4] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][5] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][6] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][7] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][8] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][9] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][10] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][11] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][12] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][13] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][14] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][15] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][16] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][17] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][18] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][19] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][20] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][21] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][22] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][23] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][24] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][25] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][26] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][27] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][28] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][29] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][30] , + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][31] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][0] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][1] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][2] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][3] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][4] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][5] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][6] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][7] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][8] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][9] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][10] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][11] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][12] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][13] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][14] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][15] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][16] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][17] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][18] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][19] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][20] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][21] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][22] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][23] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][24] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][25] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][26] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][27] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][28] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][29] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][30] , + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][31] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][0] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][1] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][2] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][3] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][4] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][5] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][6] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][7] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][8] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][9] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][10] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][11] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][12] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][13] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][14] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][15] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][16] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][17] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][18] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][19] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][20] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][21] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][22] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][23] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][24] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][25] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][26] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][27] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][28] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][29] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][30] , + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][31] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][0] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][1] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][2] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][3] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][4] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][5] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][6] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][7] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][8] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][9] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][10] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][11] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][12] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][13] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][14] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][15] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][16] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][17] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][18] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][19] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][20] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][21] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][22] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][23] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][24] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][25] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][26] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][27] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][28] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][29] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][30] , + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][31] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][0] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][1] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][2] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][3] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][4] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][5] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][6] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][7] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][8] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][9] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][10] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][11] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][12] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][13] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][14] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][15] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][16] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][17] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][18] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][19] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][20] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][21] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][22] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][23] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][24] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][25] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][26] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][27] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][28] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][29] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][30] , + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][31] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][0] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][1] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][2] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][3] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][4] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][5] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][6] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][7] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][8] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][9] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][10] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][11] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][12] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][13] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][14] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][15] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][16] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][17] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][18] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][19] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][20] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][21] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][22] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][23] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][24] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][25] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][26] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][27] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][28] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][29] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][30] , + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][31] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][0] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][1] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][2] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][3] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][4] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][5] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][6] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][7] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][8] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][9] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][10] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][11] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][12] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][13] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][14] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][15] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][16] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][17] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][18] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][19] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][20] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][21] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][22] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][23] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][24] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][25] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][26] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][27] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][28] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][29] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][30] , + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][31] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][0] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][1] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][2] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][3] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][4] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][5] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][6] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][7] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][8] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][9] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][10] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][11] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][12] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][13] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][14] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][15] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][16] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][17] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][18] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][19] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][20] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][21] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][22] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][23] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][24] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][25] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][26] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][27] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][28] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][29] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][30] , + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][31] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][0] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][1] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][2] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][3] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][4] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][5] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][6] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][7] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][8] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][9] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][10] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][11] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][12] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][13] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][14] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][15] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][16] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][17] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][18] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][19] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][20] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][21] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][22] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][23] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][24] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][25] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][26] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][27] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][28] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][29] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][30] , + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][31] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][0] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][1] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][2] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][3] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][4] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][5] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][6] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][7] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][8] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][9] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][11] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][12] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][13] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][14] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][15] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][16] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][17] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][18] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][19] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][20] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][21] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][22] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][23] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][24] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][25] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][26] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][27] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][28] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][29] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][30] , + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][31] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][0] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][1] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][2] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][3] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][4] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][5] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][6] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][7] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][8] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][9] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][10] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][11] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][12] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][13] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][14] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][15] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][16] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][17] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][18] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][19] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][20] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][21] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][22] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][23] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][24] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][25] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][26] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][27] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][28] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][29] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][30] , + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][31] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][0] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][1] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][2] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][3] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][4] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][5] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][6] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][7] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][8] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][9] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][10] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][12] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][13] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][14] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][15] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][16] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][17] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][18] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][19] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][20] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][21] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][22] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][23] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][24] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][25] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][26] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][27] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][28] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][29] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][30] , + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31]_0 , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][0] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][1] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][2] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][3] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][4] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][5] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][6] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][7] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][8] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][9] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][10] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][11] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][12] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][13] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][14] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][15] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][16] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][17] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][18] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][19] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][20] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][21] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][22] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][23] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][24] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][25] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][26] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][27] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][28] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][29] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][30] , + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][31] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][0] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][1] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][2] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][3] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][4] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][5] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][6] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][7] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][8] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][9] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][10] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][11] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][12] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][13] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][14] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][15] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][16] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][17] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][18] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][19] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][20] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][21] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][22] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][23] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][24] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][25] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][26] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][27] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][28] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][29] , + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][30] , + \AXI4_LITE_INTERFACE.soft_resetn_reg , + vid_aclk_en, + D, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][21]_0 , + genr_data, + core_data, + vid_aresetn, + \genr_control_regs[0] , + reg_update, + write_ack_int, + Q, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] , + \time_status_regs[27] , + \time_status_regs[26] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] , + \time_status_regs[25] , + \time_status_regs[24] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] , + \time_status_regs[23] , + \time_status_regs[22] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] , + \time_status_regs[21] , + \time_status_regs[20] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9] , + \time_status_regs[18] , + \time_status_regs[19] , + \time_status_regs[17] , + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] , + \time_status_regs[16] , + \time_status_regs[15] , + \time_status_regs[14] , + \time_status_regs[13] , + \time_status_regs[12] , + \time_status_regs[11] , + \time_status_regs[10] , + \time_status_regs[9] , + \time_status_regs[8] , + \time_status_regs[7] , + \time_status_regs[6] , + \time_status_regs[5] , + \time_status_regs[4] , + \time_status_regs[3] , + \time_status_regs[2] , + \time_status_regs[1] , + \time_status_regs[0] , + \genr_status_regs[3] , + intr_err, + \genr_control_regs[3] , + \genr_status_regs_int_reg[1] , + \genr_status_regs[0] , + \AXI4_LITE_INTERFACE.proc_sync1_reg[44] , + vid_aclk); + output \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][31] ; + output [32:0]out_data; + output \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][30] ; + output \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][29] ; + output \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][28] ; + output \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][27] ; + output \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][26] ; + output \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][25] ; + output \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][24] ; + output \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][23] ; + output \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][22] ; + output \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][21] ; + output \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][20] ; + output \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][19] ; + output \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][18] ; + output \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][17] ; + output \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][16] ; + output \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][13] ; + output \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][12] ; + output \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][11] ; + output \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][10] ; + output \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][9] ; + output \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][8] ; + output \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][21] ; + output \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][20] ; + output \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][19] ; + output \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][18] ; + output \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][17] ; + output \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][16] ; + output [31:0]\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] ; + output p_533_out; + output p_535_out; + output p_456_out; + output [0:0]E; + output [8:0]ipif_Addr; + output [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][0] ; + output [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][0] ; + output [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][0] ; + output [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0] ; + output \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ; + output [0:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][0] ; + output [0:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][0] ; + output [0:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][0] ; + output [0:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][0] ; + output [0:0]\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][0] ; + output [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][0] ; + output [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][0] ; + output [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][0] ; + output [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][0] ; + output [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][0] ; + output [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][0] ; + output [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][0] ; + output [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][0] ; + output [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][0] ; + output [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][0] ; + output [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][0] ; + output [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][0] ; + output [0:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][0] ; + output [0:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][0] ; + output [0:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][0] ; + output [0:0]\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][8] ; + output [0:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][0] ; + output [0:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][0] ; + output [0:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][0] ; + output [0:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][0] ; + output [0:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][7] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][31] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ; + output \GEN_TREE.GEN_BRANCH[33].GEN_MUX_REG.data_out_reg_reg[33][26] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][0] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][1] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][2] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][3] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][4] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][5] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][6] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][7] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][8] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][9] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][10] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][11] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][12] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][13] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][14] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][15] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][16] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][17] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][18] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][19] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][20] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][21] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][22] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][23] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][24] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][25] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][26] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][27] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][28] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][29] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][30] ; + output \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][31] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][0] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][1] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][2] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][3] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][4] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][5] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][6] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][7] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][8] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][9] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][10] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][11] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][12] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][13] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][14] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][15] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][16] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][17] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][18] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][19] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][20] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][21] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][22] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][23] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][24] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][25] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][26] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][27] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][28] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][29] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][30] ; + output \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][31] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][0] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][1] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][2] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][3] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][4] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][5] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][6] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][7] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][8] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][9] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][10] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][11] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][12] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][13] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][14] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][15] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][16] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][17] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][18] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][19] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][20] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][21] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][22] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][23] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][24] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][25] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][26] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][27] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][28] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][29] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][30] ; + output \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][31] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][0] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][1] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][2] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][3] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][4] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][5] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][6] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][7] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][8] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][9] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][10] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][11] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][12] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][13] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][14] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][15] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][16] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][17] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][18] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][19] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][20] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][21] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][22] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][23] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][24] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][25] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][26] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][27] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][28] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][29] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][30] ; + output \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][31] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][0] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][1] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][2] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][3] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][4] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][5] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][6] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][7] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][8] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][9] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][10] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][11] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][12] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][13] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][14] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][15] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][16] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][17] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][18] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][19] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][20] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][21] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][22] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][23] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][24] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][25] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][26] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][27] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][28] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][29] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][30] ; + output \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][31] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][0] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][1] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][2] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][3] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][4] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][5] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][6] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][7] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][8] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][9] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][10] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][11] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][12] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][13] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][14] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][15] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][16] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][17] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][18] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][19] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][20] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][21] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][22] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][23] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][24] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][25] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][26] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][27] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][28] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][29] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][30] ; + output \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][31] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][0] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][1] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][2] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][3] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][4] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][5] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][6] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][7] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][8] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][9] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][10] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][11] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][12] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][13] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][14] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][15] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][16] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][17] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][18] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][19] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][20] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][21] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][22] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][23] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][24] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][25] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][26] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][27] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][28] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][29] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][30] ; + output \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][31] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][0] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][1] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][2] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][3] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][4] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][5] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][6] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][7] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][8] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][9] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][10] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][11] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][12] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][13] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][14] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][15] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][16] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][17] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][18] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][19] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][20] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][21] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][22] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][23] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][24] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][25] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][26] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][27] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][28] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][29] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][30] ; + output \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][31] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][0] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][1] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][2] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][3] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][4] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][5] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][6] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][7] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][8] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][9] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][10] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][11] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][12] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][13] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][14] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][15] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][16] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][17] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][18] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][19] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][20] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][21] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][22] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][23] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][24] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][25] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][26] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][27] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][28] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][29] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][30] ; + output \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][31] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][0] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][1] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][2] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][3] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][4] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][5] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][6] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][7] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][8] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][9] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][10] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][11] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][12] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][13] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][14] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][15] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][16] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][17] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][18] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][19] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][20] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][21] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][22] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][23] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][24] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][25] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][26] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][27] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][28] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][29] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][30] ; + output \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][31] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][0] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][1] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][2] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][3] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][4] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][5] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][6] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][7] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][8] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][9] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][10] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][11] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][12] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][13] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][14] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][15] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][16] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][17] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][18] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][19] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][20] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][21] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][22] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][23] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][24] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][25] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][26] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][27] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][28] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][29] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][30] ; + output \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][31] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][0] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][1] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][2] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][3] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][4] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][5] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][6] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][7] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][8] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][9] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][11] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][12] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][13] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][14] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][15] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][16] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][17] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][18] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][19] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][20] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][21] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][22] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][23] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][24] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][25] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][26] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][27] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][28] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][29] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][30] ; + output \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][31] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][0] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][1] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][2] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][3] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][4] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][5] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][6] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][7] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][8] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][9] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][10] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][11] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][12] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][13] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][14] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][15] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][16] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][17] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][18] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][19] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][20] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][21] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][22] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][23] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][24] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][25] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][26] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][27] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][28] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][29] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][30] ; + output \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][31] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][0] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][1] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][2] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][3] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][4] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][5] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][6] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][7] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][8] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][9] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][10] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][12] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][13] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][14] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][15] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][16] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][17] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][18] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][19] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][20] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][21] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][22] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][23] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][24] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][25] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][26] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][27] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][28] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][29] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][30] ; + output \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31]_0 ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][0] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][1] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][2] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][3] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][4] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][5] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][6] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][7] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][8] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][9] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][10] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][11] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][12] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][13] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][14] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][15] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][16] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][17] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][18] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][19] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][20] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][21] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][22] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][23] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][24] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][25] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][26] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][27] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][28] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][29] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][30] ; + output \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][31] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][0] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][1] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][2] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][3] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][4] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][5] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][6] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][7] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][8] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][9] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][10] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][11] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][12] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][13] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][14] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][15] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][16] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][17] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][18] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][19] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][20] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][21] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][22] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][23] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][24] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][25] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][26] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][27] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][28] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][29] ; + output \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][30] ; + input \AXI4_LITE_INTERFACE.soft_resetn_reg ; + input vid_aclk_en; + input [21:0]D; + input [5:0]\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][21]_0 ; + input [31:0]genr_data; + input [31:0]core_data; + input vid_aresetn; + input [24:0]\genr_control_regs[0] ; + input reg_update; + input write_ack_int; + input [25:0]Q; + input [25:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] ; + input [5:0]\time_status_regs[27] ; + input [5:0]\time_status_regs[26] ; + input [25:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] ; + input [25:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] ; + input [5:0]\time_status_regs[25] ; + input [5:0]\time_status_regs[24] ; + input [25:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] ; + input [25:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] ; + input [5:0]\time_status_regs[23] ; + input [5:0]\time_status_regs[22] ; + input [25:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] ; + input [25:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] ; + input [5:0]\time_status_regs[21] ; + input [5:0]\time_status_regs[20] ; + input [6:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6] ; + input [7:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9] ; + input [23:0]\time_status_regs[18] ; + input [24:0]\time_status_regs[19] ; + input [31:0]\time_status_regs[17] ; + input [25:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] ; + input [5:0]\time_status_regs[16] ; + input [31:0]\time_status_regs[15] ; + input [31:0]\time_status_regs[14] ; + input [31:0]\time_status_regs[13] ; + input [31:0]\time_status_regs[12] ; + input [31:0]\time_status_regs[11] ; + input [31:0]\time_status_regs[10] ; + input [31:0]\time_status_regs[9] ; + input [31:0]\time_status_regs[8] ; + input [31:0]\time_status_regs[7] ; + input [31:0]\time_status_regs[6] ; + input [31:0]\time_status_regs[5] ; + input [31:0]\time_status_regs[4] ; + input [31:0]\time_status_regs[3] ; + input [31:0]\time_status_regs[2] ; + input [31:0]\time_status_regs[1] ; + input [31:0]\time_status_regs[0] ; + input [9:0]\genr_status_regs[3] ; + input [31:0]intr_err; + input [21:0]\genr_control_regs[3] ; + input [30:0]\genr_status_regs_int_reg[1] ; + input [6:0]\genr_status_regs[0] ; + input [44:0]\AXI4_LITE_INTERFACE.proc_sync1_reg[44] ; + input vid_aclk; + + wire \AXI4_LITE_INTERFACE.core_control_regs_int[13][26]_i_2_n_0 ; + wire \AXI4_LITE_INTERFACE.core_control_regs_int[16][26]_i_2_n_0 ; + wire \AXI4_LITE_INTERFACE.core_control_regs_int[9][26]_i_2_n_0 ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0] ; + wire \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][0] ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][0] ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][0] ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][0] ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][0] ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][0] ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][0] ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][0] ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][0] ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][0] ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][0] ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][0] ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][0] ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][0] ; + wire [0:0]\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][0] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2_n_0 ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0 ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int[2][21]_i_2_n_0 ; + wire [0:0]\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][0] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][10] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][11] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][12] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][13] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][16] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][17] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][18] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][19] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][20] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][21] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][22] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][23] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][24] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][25] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][26] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][27] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][28] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][29] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][30] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][31] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][8] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][9] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][16] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][17] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][18] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][19] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][20] ; + wire \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][21] ; + wire [5:0]\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][21]_0 ; + wire [0:0]\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][8] ; + wire [31:0]\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] ; + (* shreg_extract = "no" *) wire [44:0]\AXI4_LITE_INTERFACE.proc_sync1_reg[44] ; + wire \AXI4_LITE_INTERFACE.soft_resetn_reg ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int[18][6]_i_2_n_0 ; + wire \AXI4_LITE_INTERFACE.time_control_regs_int[28][28]_i_2_n_0 ; + wire [0:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][0] ; + wire [25:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] ; + wire [0:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][7] ; + wire [7:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9] ; + wire [0:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][0] ; + wire [6:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6] ; + wire [0:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][0] ; + wire [25:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] ; + wire [0:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][0] ; + wire [25:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] ; + wire [0:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][0] ; + wire [25:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] ; + wire [0:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][0] ; + wire [25:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] ; + wire [0:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][0] ; + wire [25:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] ; + wire [0:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][0] ; + wire [25:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] ; + wire [0:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][0] ; + wire [25:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] ; + wire [0:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][0] ; + wire [0:0]\AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][0] ; + wire [21:0]D; + wire [0:0]E; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][0] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][10] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][11] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][12] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][13] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][14] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][15] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][16] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][17] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][18] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][19] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][1] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][20] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][21] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][22] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][23] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][24] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][25] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][26] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][27] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][28] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][29] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][2] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][30] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][31] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][3] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][4] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][5] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][6] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][7] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][8] ; + wire \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][9] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][0] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][10] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][11] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][12] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][13] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][14] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][15] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][16] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][17] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][18] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][19] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][1] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][20] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][21] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][22] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][23] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][24] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][25] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][26] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][27] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][28] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][29] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][2] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][30] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][31] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][3] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][4] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][5] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][6] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][7] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][8] ; + wire \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][9] ; + wire \GEN_TREE.GEN_BRANCH[33].GEN_MUX_REG.data_out_reg_reg[33][26] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][0] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][10] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][12] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][13] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][14] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][15] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][16] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][17] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][18] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][19] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][1] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][20] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][21] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][22] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][23] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][24] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][25] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][26] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][27] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][28] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][29] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][2] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][30] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31]_0 ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][3] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][4] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][5] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][6] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][7] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][8] ; + wire \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][9] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][0] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][10] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][11] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][12] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][13] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][14] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][15] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][16] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][17] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][18] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][19] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][1] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][20] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][21] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][22] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][23] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][24] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][25] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][26] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][27] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][28] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][29] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][2] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][30] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][31] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][3] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][4] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][5] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][6] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][7] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][8] ; + wire \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][9] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][0] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][11] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][12] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][13] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][14] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][15] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][16] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][17] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][18] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][19] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][1] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][20] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][21] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][22] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][23] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][24] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][25] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][26] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][27] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][28] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][29] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][2] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][30] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][31] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][3] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][4] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][5] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][6] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][7] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][8] ; + wire \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][9] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][0] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][10] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][11] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][12] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][13] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][14] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][15] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][16] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][17] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][18] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][19] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][1] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][20] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][21] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][22] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][23] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][24] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][25] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][26] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][27] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][28] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][29] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][2] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][30] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][31] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][3] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][4] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][5] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][6] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][7] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][8] ; + wire \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][9] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][0] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][10] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][11] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][12] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][13] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][14] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][15] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][16] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][17] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][18] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][19] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][1] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][20] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][21] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][22] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][23] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][24] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][25] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][26] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][27] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][28] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][29] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][2] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][30] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][31] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][3] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][4] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][5] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][6] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][7] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][8] ; + wire \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][9] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][0] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][10] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][11] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][12] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][13] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][14] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][15] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][16] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][17] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][18] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][19] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][1] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][20] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][21] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][22] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][23] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][24] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][25] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][26] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][27] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][28] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][29] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][2] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][30] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][31] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][3] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][4] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][5] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][6] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][7] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][8] ; + wire \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][9] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][0] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][10] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][11] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][12] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][13] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][14] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][15] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][16] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][17] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][18] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][19] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][1] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][20] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][21] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][22] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][23] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][24] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][25] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][26] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][27] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][28] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][29] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][2] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][30] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][31] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][3] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][4] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][5] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][6] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][7] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][8] ; + wire \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][9] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][0] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][10] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][11] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][12] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][13] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][14] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][15] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][16] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][17] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][18] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][19] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][1] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][20] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][21] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][22] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][23] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][24] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][25] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][26] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][27] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][28] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][29] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][2] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][30] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][31] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][3] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][4] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][5] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][6] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][7] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][8] ; + wire \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][9] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][0] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][10] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][11] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][12] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][13] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][14] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][15] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][16] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][17] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][18] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][19] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][1] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][20] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][21] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][22] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][23] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][24] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][25] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][26] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][27] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][28] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][29] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][2] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][30] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][31] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][3] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][4] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][5] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][6] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][7] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][8] ; + wire \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][9] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][0] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][10] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][11] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][12] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][13] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][14] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][15] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][16] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][17] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][18] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][19] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][1] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][20] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][21] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][22] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][23] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][24] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][25] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][26] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][27] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][28] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][29] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][2] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][30] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][31] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][3] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][4] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][5] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][6] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][7] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][8] ; + wire \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][9] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][0] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][10] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][11] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][12] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][13] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][14] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][15] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][16] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][17] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][18] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][19] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][1] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][20] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][21] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][22] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][23] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][24] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][25] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][26] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][27] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][28] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][29] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][2] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][30] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][31] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][3] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][4] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][5] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][6] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][7] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][8] ; + wire \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][9] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][0] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][10] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][11] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][12] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][13] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][14] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][15] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][16] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][17] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][18] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][19] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][1] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][20] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][21] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][22] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][23] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][24] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][25] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][26] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][27] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][28] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][29] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][2] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][30] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][31] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][3] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][4] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][5] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][6] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][7] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][8] ; + wire \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][9] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][0] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][10] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][11] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][12] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][13] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][14] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][15] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][16] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][17] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][18] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][19] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][1] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][20] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][21] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][22] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][23] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][24] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][25] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][26] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][27] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][28] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][29] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][2] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][30] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][31] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][3] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][4] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][5] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][6] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][7] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][8] ; + wire \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][9] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][0] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][10] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][11] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][12] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][13] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][14] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][15] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][16] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][17] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][18] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][19] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][1] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][20] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][21] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][22] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][23] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][24] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][25] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][26] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][27] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][28] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][29] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][2] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][30] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][31] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][3] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][4] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][5] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][6] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][7] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][8] ; + wire \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][9] ; + wire [25:0]Q; + wire [31:0]core_data; + (* async_reg = "true" *) (* shift_extract = "NO" *) (* shreg_extract = "no" *) wire [44:0]\data_sync[0]_0 ; + (* async_reg = "true" *) (* shift_extract = "NO" *) (* shreg_extract = "no" *) wire [44:0]\data_sync[1]_1 ; + (* async_reg = "true" *) (* shift_extract = "NO" *) (* shreg_extract = "no" *) wire [44:0]\data_sync[2]_2 ; + wire [24:0]\genr_control_regs[0] ; + wire [21:0]\genr_control_regs[3] ; + wire [31:0]genr_data; + wire [6:0]\genr_status_regs[0] ; + wire [9:0]\genr_status_regs[3] ; + wire [30:0]\genr_status_regs_int_reg[1] ; + wire [31:0]intr_err; + wire [8:0]ipif_Addr; + wire p_456_out; + wire p_533_out; + wire p_535_out; + wire reg_update; + wire [31:0]\time_status_regs[0] ; + wire [31:0]\time_status_regs[10] ; + wire [31:0]\time_status_regs[11] ; + wire [31:0]\time_status_regs[12] ; + wire [31:0]\time_status_regs[13] ; + wire [31:0]\time_status_regs[14] ; + wire [31:0]\time_status_regs[15] ; + wire [5:0]\time_status_regs[16] ; + wire [31:0]\time_status_regs[17] ; + wire [23:0]\time_status_regs[18] ; + wire [24:0]\time_status_regs[19] ; + wire [31:0]\time_status_regs[1] ; + wire [5:0]\time_status_regs[20] ; + wire [5:0]\time_status_regs[21] ; + wire [5:0]\time_status_regs[22] ; + wire [5:0]\time_status_regs[23] ; + wire [5:0]\time_status_regs[24] ; + wire [5:0]\time_status_regs[25] ; + wire [5:0]\time_status_regs[26] ; + wire [5:0]\time_status_regs[27] ; + wire [31:0]\time_status_regs[2] ; + wire [31:0]\time_status_regs[3] ; + wire [31:0]\time_status_regs[4] ; + wire [31:0]\time_status_regs[5] ; + wire [31:0]\time_status_regs[6] ; + wire [31:0]\time_status_regs[7] ; + wire [31:0]\time_status_regs[8] ; + wire [31:0]\time_status_regs[9] ; + wire vid_aclk; + wire vid_aclk_en; + wire vid_aresetn; + wire write_ack_int; + + assign out_data[32] = \data_sync[2]_2 [42]; + assign out_data[31:0] = \data_sync[2]_2 [31:0]; + LUT5 #( + .INIT(32'h00080000)) + \AXI4_LITE_INTERFACE.core_control_regs_int[0][26]_i_1 + (.I0(\data_sync[2]_2 [42]), + .I1(write_ack_int), + .I2(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .I3(ipif_Addr[3]), + .I4(\AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2_n_0 ), + .O(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0] )); + LUT5 #( + .INIT(32'h00800000)) + \AXI4_LITE_INTERFACE.core_control_regs_int[10][26]_i_1 + (.I0(\data_sync[2]_2 [42]), + .I1(write_ack_int), + .I2(ipif_Addr[3]), + .I3(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .I4(\AXI4_LITE_INTERFACE.core_control_regs_int[9][26]_i_2_n_0 ), + .O(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][0] )); + LUT5 #( + .INIT(32'h80000000)) + \AXI4_LITE_INTERFACE.core_control_regs_int[11][26]_i_1 + (.I0(ipif_Addr[3]), + .I1(write_ack_int), + .I2(\data_sync[2]_2 [42]), + .I3(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .I4(\AXI4_LITE_INTERFACE.core_control_regs_int[9][26]_i_2_n_0 ), + .O(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][0] )); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT5 #( + .INIT(32'h20000000)) + \AXI4_LITE_INTERFACE.core_control_regs_int[12][26]_i_1 + (.I0(vid_aclk_en), + .I1(ipif_Addr[6]), + .I2(ipif_Addr[4]), + .I3(ipif_Addr[5]), + .I4(\AXI4_LITE_INTERFACE.core_control_regs_int[16][26]_i_2_n_0 ), + .O(E)); + LUT5 #( + .INIT(32'h40000000)) + \AXI4_LITE_INTERFACE.core_control_regs_int[13][26]_i_1 + (.I0(ipif_Addr[3]), + .I1(write_ack_int), + .I2(\data_sync[2]_2 [42]), + .I3(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .I4(\AXI4_LITE_INTERFACE.core_control_regs_int[13][26]_i_2_n_0 ), + .O(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][0] )); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT4 #( + .INIT(16'h0800)) + \AXI4_LITE_INTERFACE.core_control_regs_int[13][26]_i_2 + (.I0(ipif_Addr[5]), + .I1(ipif_Addr[4]), + .I2(ipif_Addr[6]), + .I3(vid_aclk_en), + .O(\AXI4_LITE_INTERFACE.core_control_regs_int[13][26]_i_2_n_0 )); + LUT5 #( + .INIT(32'h00800000)) + \AXI4_LITE_INTERFACE.core_control_regs_int[14][26]_i_1 + (.I0(\data_sync[2]_2 [42]), + .I1(write_ack_int), + .I2(ipif_Addr[3]), + .I3(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .I4(\AXI4_LITE_INTERFACE.core_control_regs_int[13][26]_i_2_n_0 ), + .O(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][0] )); + LUT5 #( + .INIT(32'h80000000)) + \AXI4_LITE_INTERFACE.core_control_regs_int[15][26]_i_1 + (.I0(ipif_Addr[3]), + .I1(write_ack_int), + .I2(\data_sync[2]_2 [42]), + .I3(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .I4(\AXI4_LITE_INTERFACE.core_control_regs_int[13][26]_i_2_n_0 ), + .O(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][0] )); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT5 #( + .INIT(32'h00080000)) + \AXI4_LITE_INTERFACE.core_control_regs_int[16][26]_i_1 + (.I0(ipif_Addr[6]), + .I1(vid_aclk_en), + .I2(ipif_Addr[4]), + .I3(ipif_Addr[5]), + .I4(\AXI4_LITE_INTERFACE.core_control_regs_int[16][26]_i_2_n_0 ), + .O(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][0] )); + LUT4 #( + .INIT(16'h1000)) + \AXI4_LITE_INTERFACE.core_control_regs_int[16][26]_i_2 + (.I0(ipif_Addr[3]), + .I1(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .I2(write_ack_int), + .I3(\data_sync[2]_2 [42]), + .O(\AXI4_LITE_INTERFACE.core_control_regs_int[16][26]_i_2_n_0 )); + LUT5 #( + .INIT(32'h40000000)) + \AXI4_LITE_INTERFACE.core_control_regs_int[1][26]_i_1 + (.I0(ipif_Addr[3]), + .I1(write_ack_int), + .I2(\data_sync[2]_2 [42]), + .I3(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .I4(\AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2_n_0 ), + .O(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][0] )); + LUT5 #( + .INIT(32'h00800000)) + \AXI4_LITE_INTERFACE.core_control_regs_int[2][26]_i_1 + (.I0(\data_sync[2]_2 [42]), + .I1(write_ack_int), + .I2(ipif_Addr[3]), + .I3(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .I4(\AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2_n_0 ), + .O(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][0] )); + LUT5 #( + .INIT(32'h80000000)) + \AXI4_LITE_INTERFACE.core_control_regs_int[3][26]_i_1 + (.I0(ipif_Addr[3]), + .I1(write_ack_int), + .I2(\data_sync[2]_2 [42]), + .I3(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .I4(\AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2_n_0 ), + .O(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][0] )); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT5 #( + .INIT(32'h00200000)) + \AXI4_LITE_INTERFACE.core_control_regs_int[4][26]_i_1 + (.I0(ipif_Addr[4]), + .I1(ipif_Addr[6]), + .I2(vid_aclk_en), + .I3(ipif_Addr[5]), + .I4(\AXI4_LITE_INTERFACE.core_control_regs_int[16][26]_i_2_n_0 ), + .O(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][0] )); + LUT5 #( + .INIT(32'h40000000)) + \AXI4_LITE_INTERFACE.core_control_regs_int[5][26]_i_1 + (.I0(ipif_Addr[3]), + .I1(write_ack_int), + .I2(\data_sync[2]_2 [42]), + .I3(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .I4(\AXI4_LITE_INTERFACE.time_control_regs_int[28][28]_i_2_n_0 ), + .O(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][0] )); + LUT5 #( + .INIT(32'h00800000)) + \AXI4_LITE_INTERFACE.core_control_regs_int[6][26]_i_1 + (.I0(\data_sync[2]_2 [42]), + .I1(write_ack_int), + .I2(ipif_Addr[3]), + .I3(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .I4(\AXI4_LITE_INTERFACE.time_control_regs_int[28][28]_i_2_n_0 ), + .O(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][0] )); + LUT5 #( + .INIT(32'h80000000)) + \AXI4_LITE_INTERFACE.core_control_regs_int[7][26]_i_1 + (.I0(ipif_Addr[3]), + .I1(write_ack_int), + .I2(\data_sync[2]_2 [42]), + .I3(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .I4(\AXI4_LITE_INTERFACE.time_control_regs_int[28][28]_i_2_n_0 ), + .O(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][0] )); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT5 #( + .INIT(32'h00200000)) + \AXI4_LITE_INTERFACE.core_control_regs_int[8][26]_i_1 + (.I0(vid_aclk_en), + .I1(ipif_Addr[6]), + .I2(ipif_Addr[5]), + .I3(ipif_Addr[4]), + .I4(\AXI4_LITE_INTERFACE.core_control_regs_int[16][26]_i_2_n_0 ), + .O(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][0] )); + LUT5 #( + .INIT(32'h40000000)) + \AXI4_LITE_INTERFACE.core_control_regs_int[9][26]_i_1 + (.I0(ipif_Addr[3]), + .I1(write_ack_int), + .I2(\data_sync[2]_2 [42]), + .I3(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .I4(\AXI4_LITE_INTERFACE.core_control_regs_int[9][26]_i_2_n_0 ), + .O(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][0] )); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT4 #( + .INIT(16'h0400)) + \AXI4_LITE_INTERFACE.core_control_regs_int[9][26]_i_2 + (.I0(ipif_Addr[4]), + .I1(ipif_Addr[5]), + .I2(ipif_Addr[6]), + .I3(vid_aclk_en), + .O(\AXI4_LITE_INTERFACE.core_control_regs_int[9][26]_i_2_n_0 )); + LUT6 #( + .INIT(64'h0000000000000080)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2_n_0 ), + .I1(write_ack_int), + .I2(\data_sync[2]_2 [41]), + .I3(ipif_Addr[7]), + .I4(ipif_Addr[3]), + .I5(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][0] )); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT4 #( + .INIT(16'h0004)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2 + (.I0(ipif_Addr[5]), + .I1(vid_aclk_en), + .I2(ipif_Addr[6]), + .I3(ipif_Addr[4]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2_n_0 )); + (* IS_FANOUT_CONSTRAINED = "1" *) + LUT1 #( + .INIT(2'h2)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_3 + (.I0(\data_sync[2]_2 [34]), + .O(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 )); + LUT6 #( + .INIT(64'hD000D0D080808080)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[1][10]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0 ), + .I1(\data_sync[2]_2 [10]), + .I2(\AXI4_LITE_INTERFACE.soft_resetn_reg ), + .I3(\data_sync[2]_2 [41]), + .I4(vid_aclk_en), + .I5(D[2]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][10] )); + LUT6 #( + .INIT(64'hD000D0D080808080)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[1][11]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0 ), + .I1(\data_sync[2]_2 [11]), + .I2(\AXI4_LITE_INTERFACE.soft_resetn_reg ), + .I3(\data_sync[2]_2 [41]), + .I4(vid_aclk_en), + .I5(D[3]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][11] )); + LUT6 #( + .INIT(64'hD000D0D080808080)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[1][12]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0 ), + .I1(\data_sync[2]_2 [12]), + .I2(\AXI4_LITE_INTERFACE.soft_resetn_reg ), + .I3(\data_sync[2]_2 [41]), + .I4(vid_aclk_en), + .I5(D[4]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][12] )); + LUT6 #( + .INIT(64'hD000D0D080808080)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[1][13]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0 ), + .I1(\data_sync[2]_2 [13]), + .I2(\AXI4_LITE_INTERFACE.soft_resetn_reg ), + .I3(\data_sync[2]_2 [41]), + .I4(vid_aclk_en), + .I5(D[5]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][13] )); + LUT6 #( + .INIT(64'hD000D0D080808080)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[1][16]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0 ), + .I1(\data_sync[2]_2 [16]), + .I2(\AXI4_LITE_INTERFACE.soft_resetn_reg ), + .I3(\data_sync[2]_2 [41]), + .I4(vid_aclk_en), + .I5(D[6]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][16] )); + LUT6 #( + .INIT(64'hD000D0D080808080)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[1][17]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0 ), + .I1(\data_sync[2]_2 [17]), + .I2(\AXI4_LITE_INTERFACE.soft_resetn_reg ), + .I3(\data_sync[2]_2 [41]), + .I4(vid_aclk_en), + .I5(D[7]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][17] )); + LUT6 #( + .INIT(64'hD000D0D080808080)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[1][18]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0 ), + .I1(\data_sync[2]_2 [18]), + .I2(\AXI4_LITE_INTERFACE.soft_resetn_reg ), + .I3(\data_sync[2]_2 [41]), + .I4(vid_aclk_en), + .I5(D[8]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][18] )); + LUT6 #( + .INIT(64'hD000D0D080808080)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[1][19]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0 ), + .I1(\data_sync[2]_2 [19]), + .I2(\AXI4_LITE_INTERFACE.soft_resetn_reg ), + .I3(\data_sync[2]_2 [41]), + .I4(vid_aclk_en), + .I5(D[9]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][19] )); + LUT6 #( + .INIT(64'hD000D0D080808080)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[1][20]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0 ), + .I1(\data_sync[2]_2 [20]), + .I2(\AXI4_LITE_INTERFACE.soft_resetn_reg ), + .I3(\data_sync[2]_2 [41]), + .I4(vid_aclk_en), + .I5(D[10]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][20] )); + LUT6 #( + .INIT(64'hD000D0D080808080)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[1][21]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0 ), + .I1(\data_sync[2]_2 [21]), + .I2(\AXI4_LITE_INTERFACE.soft_resetn_reg ), + .I3(\data_sync[2]_2 [41]), + .I4(vid_aclk_en), + .I5(D[11]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][21] )); + LUT6 #( + .INIT(64'hD000D0D080808080)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[1][22]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0 ), + .I1(\data_sync[2]_2 [22]), + .I2(\AXI4_LITE_INTERFACE.soft_resetn_reg ), + .I3(\data_sync[2]_2 [41]), + .I4(vid_aclk_en), + .I5(D[12]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][22] )); + LUT6 #( + .INIT(64'hD000D0D080808080)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[1][23]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0 ), + .I1(\data_sync[2]_2 [23]), + .I2(\AXI4_LITE_INTERFACE.soft_resetn_reg ), + .I3(\data_sync[2]_2 [41]), + .I4(vid_aclk_en), + .I5(D[13]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][23] )); + LUT6 #( + .INIT(64'hD000D0D080808080)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[1][24]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0 ), + .I1(\data_sync[2]_2 [24]), + .I2(\AXI4_LITE_INTERFACE.soft_resetn_reg ), + .I3(\data_sync[2]_2 [41]), + .I4(vid_aclk_en), + .I5(D[14]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][24] )); + LUT6 #( + .INIT(64'hD000D0D080808080)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[1][25]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0 ), + .I1(\data_sync[2]_2 [25]), + .I2(\AXI4_LITE_INTERFACE.soft_resetn_reg ), + .I3(\data_sync[2]_2 [41]), + .I4(vid_aclk_en), + .I5(D[15]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][25] )); + LUT6 #( + .INIT(64'hD000D0D080808080)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[1][26]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0 ), + .I1(\data_sync[2]_2 [26]), + .I2(\AXI4_LITE_INTERFACE.soft_resetn_reg ), + .I3(\data_sync[2]_2 [41]), + .I4(vid_aclk_en), + .I5(D[16]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][26] )); + LUT6 #( + .INIT(64'hD000D0D080808080)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[1][27]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0 ), + .I1(\data_sync[2]_2 [27]), + .I2(\AXI4_LITE_INTERFACE.soft_resetn_reg ), + .I3(\data_sync[2]_2 [41]), + .I4(vid_aclk_en), + .I5(D[17]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][27] )); + LUT6 #( + .INIT(64'hD000D0D080808080)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[1][28]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0 ), + .I1(\data_sync[2]_2 [28]), + .I2(\AXI4_LITE_INTERFACE.soft_resetn_reg ), + .I3(\data_sync[2]_2 [41]), + .I4(vid_aclk_en), + .I5(D[18]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][28] )); + LUT6 #( + .INIT(64'hD000D0D080808080)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[1][29]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0 ), + .I1(\data_sync[2]_2 [29]), + .I2(\AXI4_LITE_INTERFACE.soft_resetn_reg ), + .I3(\data_sync[2]_2 [41]), + .I4(vid_aclk_en), + .I5(D[19]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][29] )); + LUT6 #( + .INIT(64'hD000D0D080808080)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[1][30]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0 ), + .I1(\data_sync[2]_2 [30]), + .I2(\AXI4_LITE_INTERFACE.soft_resetn_reg ), + .I3(\data_sync[2]_2 [41]), + .I4(vid_aclk_en), + .I5(D[20]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][30] )); + LUT6 #( + .INIT(64'hD000D0D080808080)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0 ), + .I1(\data_sync[2]_2 [31]), + .I2(\AXI4_LITE_INTERFACE.soft_resetn_reg ), + .I3(\data_sync[2]_2 [41]), + .I4(vid_aclk_en), + .I5(D[21]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][31] )); + LUT6 #( + .INIT(64'h0000000040000000)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2 + (.I0(ipif_Addr[3]), + .I1(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .I2(\AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2_n_0 ), + .I3(write_ack_int), + .I4(\data_sync[2]_2 [41]), + .I5(ipif_Addr[7]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0 )); + LUT6 #( + .INIT(64'hD000D0D080808080)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[1][8]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0 ), + .I1(\data_sync[2]_2 [8]), + .I2(\AXI4_LITE_INTERFACE.soft_resetn_reg ), + .I3(\data_sync[2]_2 [41]), + .I4(vid_aclk_en), + .I5(D[0]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][8] )); + LUT6 #( + .INIT(64'hD000D0D080808080)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[1][9]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0 ), + .I1(\data_sync[2]_2 [9]), + .I2(\AXI4_LITE_INTERFACE.soft_resetn_reg ), + .I3(\data_sync[2]_2 [41]), + .I4(vid_aclk_en), + .I5(D[1]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][9] )); + LUT6 #( + .INIT(64'hD000D0D080808080)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[2][16]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[2][21]_i_2_n_0 ), + .I1(\data_sync[2]_2 [16]), + .I2(\AXI4_LITE_INTERFACE.soft_resetn_reg ), + .I3(\data_sync[2]_2 [41]), + .I4(vid_aclk_en), + .I5(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][21]_0 [0]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][16] )); + LUT6 #( + .INIT(64'hD000D0D080808080)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[2][17]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[2][21]_i_2_n_0 ), + .I1(\data_sync[2]_2 [17]), + .I2(\AXI4_LITE_INTERFACE.soft_resetn_reg ), + .I3(\data_sync[2]_2 [41]), + .I4(vid_aclk_en), + .I5(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][21]_0 [1]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][17] )); + LUT6 #( + .INIT(64'hD000D0D080808080)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[2][18]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[2][21]_i_2_n_0 ), + .I1(\data_sync[2]_2 [18]), + .I2(\AXI4_LITE_INTERFACE.soft_resetn_reg ), + .I3(\data_sync[2]_2 [41]), + .I4(vid_aclk_en), + .I5(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][21]_0 [2]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][18] )); + LUT6 #( + .INIT(64'hD000D0D080808080)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[2][19]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[2][21]_i_2_n_0 ), + .I1(\data_sync[2]_2 [19]), + .I2(\AXI4_LITE_INTERFACE.soft_resetn_reg ), + .I3(\data_sync[2]_2 [41]), + .I4(vid_aclk_en), + .I5(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][21]_0 [3]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][19] )); + LUT6 #( + .INIT(64'hD000D0D080808080)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[2][20]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[2][21]_i_2_n_0 ), + .I1(\data_sync[2]_2 [20]), + .I2(\AXI4_LITE_INTERFACE.soft_resetn_reg ), + .I3(\data_sync[2]_2 [41]), + .I4(vid_aclk_en), + .I5(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][21]_0 [4]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][20] )); + LUT6 #( + .INIT(64'hD000D0D080808080)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[2][21]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[2][21]_i_2_n_0 ), + .I1(\data_sync[2]_2 [21]), + .I2(\AXI4_LITE_INTERFACE.soft_resetn_reg ), + .I3(\data_sync[2]_2 [41]), + .I4(vid_aclk_en), + .I5(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][21]_0 [5]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][21] )); + LUT6 #( + .INIT(64'h0000008000000000)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[2][21]_i_2 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2_n_0 ), + .I1(write_ack_int), + .I2(\data_sync[2]_2 [41]), + .I3(ipif_Addr[7]), + .I4(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .I5(ipif_Addr[3]), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int[2][21]_i_2_n_0 )); + LUT6 #( + .INIT(64'h0080000000000000)) + \AXI4_LITE_INTERFACE.genr_control_regs_int[3][31]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2_n_0 ), + .I1(write_ack_int), + .I2(\data_sync[2]_2 [41]), + .I3(ipif_Addr[7]), + .I4(ipif_Addr[3]), + .I5(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .O(\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][8] )); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[0]_i_1 + (.I0(genr_data[0]), + .I1(core_data[0]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [0]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[10]_i_1 + (.I0(genr_data[10]), + .I1(core_data[10]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [10]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[11]_i_1 + (.I0(genr_data[11]), + .I1(core_data[11]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [11]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[12]_i_1 + (.I0(genr_data[12]), + .I1(core_data[12]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [12]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[13]_i_1 + (.I0(genr_data[13]), + .I1(core_data[13]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [13]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[14]_i_1 + (.I0(genr_data[14]), + .I1(core_data[14]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [14]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[15]_i_1 + (.I0(genr_data[15]), + .I1(core_data[15]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [15]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[16]_i_1 + (.I0(genr_data[16]), + .I1(core_data[16]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [16]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[17]_i_1 + (.I0(genr_data[17]), + .I1(core_data[17]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [17]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[18]_i_1 + (.I0(genr_data[18]), + .I1(core_data[18]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [18]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[19]_i_1 + (.I0(genr_data[19]), + .I1(core_data[19]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [19]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[1]_i_1 + (.I0(genr_data[1]), + .I1(core_data[1]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [1]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[20]_i_1 + (.I0(genr_data[20]), + .I1(core_data[20]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [20]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[21]_i_1 + (.I0(genr_data[21]), + .I1(core_data[21]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [21]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[22]_i_1 + (.I0(genr_data[22]), + .I1(core_data[22]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [22]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[23]_i_1 + (.I0(genr_data[23]), + .I1(core_data[23]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [23]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[24]_i_1 + (.I0(genr_data[24]), + .I1(core_data[24]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [24]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[25]_i_1 + (.I0(genr_data[25]), + .I1(core_data[25]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [25]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[26]_i_1 + (.I0(genr_data[26]), + .I1(core_data[26]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [26]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[27]_i_1 + (.I0(genr_data[27]), + .I1(core_data[27]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [27]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[28]_i_1 + (.I0(genr_data[28]), + .I1(core_data[28]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [28]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[29]_i_1 + (.I0(genr_data[29]), + .I1(core_data[29]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [29]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[2]_i_1 + (.I0(genr_data[2]), + .I1(core_data[2]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [2]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[30]_i_1 + (.I0(genr_data[30]), + .I1(core_data[30]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [30]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]_i_1 + (.I0(genr_data[31]), + .I1(core_data[31]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [31]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[3]_i_1 + (.I0(genr_data[3]), + .I1(core_data[3]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [3]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[4]_i_1 + (.I0(genr_data[4]), + .I1(core_data[4]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [4]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[5]_i_1 + (.I0(genr_data[5]), + .I1(core_data[5]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [5]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[6]_i_1 + (.I0(genr_data[6]), + .I1(core_data[6]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [6]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[7]_i_1 + (.I0(genr_data[7]), + .I1(core_data[7]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [7]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[8]_i_1 + (.I0(genr_data[8]), + .I1(core_data[8]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [8]), + .S(\data_sync[2]_2 [42])); + MUXF7 \AXI4_LITE_INTERFACE.ipif_RdData_reg[9]_i_1 + (.I0(genr_data[9]), + .I1(core_data[9]), + .O(\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] [9]), + .S(\data_sync[2]_2 [42])); + LUT3 #( + .INIT(8'hE0)) + \AXI4_LITE_INTERFACE.read_ack_d_reg[2]_srl4___AXI4_LITE_INTERFACE.read_ack_d_reg_r_1_i_1 + (.I0(\data_sync[2]_2 [41]), + .I1(\data_sync[2]_2 [42]), + .I2(\data_sync[2]_2 [43]), + .O(p_535_out)); + LUT5 #( + .INIT(32'h00080808)) + \AXI4_LITE_INTERFACE.soft_resetn_i_1 + (.I0(vid_aresetn), + .I1(\data_sync[2]_2 [44]), + .I2(\genr_control_regs[0] [24]), + .I3(reg_update), + .I4(\genr_control_regs[0] [23]), + .O(p_456_out)); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT5 #( + .INIT(32'h00100000)) + \AXI4_LITE_INTERFACE.time_control_regs_int[16][28]_i_1 + (.I0(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .I1(ipif_Addr[3]), + .I2(ipif_Addr[5]), + .I3(ipif_Addr[4]), + .I4(\AXI4_LITE_INTERFACE.time_control_regs_int[18][6]_i_2_n_0 ), + .O(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][0] )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT5 #( + .INIT(32'h00200000)) + \AXI4_LITE_INTERFACE.time_control_regs_int[18][6]_i_1 + (.I0(ipif_Addr[3]), + .I1(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .I2(ipif_Addr[5]), + .I3(ipif_Addr[4]), + .I4(\AXI4_LITE_INTERFACE.time_control_regs_int[18][6]_i_2_n_0 ), + .O(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][7] )); + LUT5 #( + .INIT(32'h08000000)) + \AXI4_LITE_INTERFACE.time_control_regs_int[18][6]_i_2 + (.I0(vid_aclk_en), + .I1(ipif_Addr[6]), + .I2(ipif_Addr[7]), + .I3(\data_sync[2]_2 [41]), + .I4(write_ack_int), + .O(\AXI4_LITE_INTERFACE.time_control_regs_int[18][6]_i_2_n_0 )); + LUT5 #( + .INIT(32'h00800000)) + \AXI4_LITE_INTERFACE.time_control_regs_int[19][6]_i_1 + (.I0(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .I1(ipif_Addr[3]), + .I2(ipif_Addr[5]), + .I3(ipif_Addr[4]), + .I4(\AXI4_LITE_INTERFACE.time_control_regs_int[18][6]_i_2_n_0 ), + .O(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][0] )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT5 #( + .INIT(32'h00000080)) + \AXI4_LITE_INTERFACE.time_control_regs_int[20][28]_i_1 + (.I0(ipif_Addr[4]), + .I1(ipif_Addr[5]), + .I2(\AXI4_LITE_INTERFACE.time_control_regs_int[18][6]_i_2_n_0 ), + .I3(ipif_Addr[3]), + .I4(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .O(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][0] )); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT5 #( + .INIT(32'h40000000)) + \AXI4_LITE_INTERFACE.time_control_regs_int[21][28]_i_1 + (.I0(ipif_Addr[3]), + .I1(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .I2(ipif_Addr[4]), + .I3(ipif_Addr[5]), + .I4(\AXI4_LITE_INTERFACE.time_control_regs_int[18][6]_i_2_n_0 ), + .O(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][0] )); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT5 #( + .INIT(32'h00800000)) + \AXI4_LITE_INTERFACE.time_control_regs_int[22][28]_i_1 + (.I0(ipif_Addr[4]), + .I1(ipif_Addr[5]), + .I2(\AXI4_LITE_INTERFACE.time_control_regs_int[18][6]_i_2_n_0 ), + .I3(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .I4(ipif_Addr[3]), + .O(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][0] )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT5 #( + .INIT(32'h80000000)) + \AXI4_LITE_INTERFACE.time_control_regs_int[23][28]_i_1 + (.I0(ipif_Addr[4]), + .I1(ipif_Addr[5]), + .I2(\AXI4_LITE_INTERFACE.time_control_regs_int[18][6]_i_2_n_0 ), + .I3(ipif_Addr[3]), + .I4(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .O(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][0] )); + LUT6 #( + .INIT(64'h0000000000008000)) + \AXI4_LITE_INTERFACE.time_control_regs_int[24][28]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2_n_0 ), + .I1(write_ack_int), + .I2(\data_sync[2]_2 [41]), + .I3(ipif_Addr[7]), + .I4(ipif_Addr[3]), + .I5(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .O(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][0] )); + LUT6 #( + .INIT(64'h4000000000000000)) + \AXI4_LITE_INTERFACE.time_control_regs_int[25][28]_i_1 + (.I0(ipif_Addr[3]), + .I1(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .I2(\AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2_n_0 ), + .I3(write_ack_int), + .I4(\data_sync[2]_2 [41]), + .I5(ipif_Addr[7]), + .O(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][0] )); + LUT6 #( + .INIT(64'h0000800000000000)) + \AXI4_LITE_INTERFACE.time_control_regs_int[26][28]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2_n_0 ), + .I1(write_ack_int), + .I2(\data_sync[2]_2 [41]), + .I3(ipif_Addr[7]), + .I4(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .I5(ipif_Addr[3]), + .O(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][0] )); + LUT6 #( + .INIT(64'h8000000000000000)) + \AXI4_LITE_INTERFACE.time_control_regs_int[27][28]_i_1 + (.I0(\AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2_n_0 ), + .I1(write_ack_int), + .I2(\data_sync[2]_2 [41]), + .I3(ipif_Addr[7]), + .I4(ipif_Addr[3]), + .I5(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .O(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][0] )); + LUT6 #( + .INIT(64'h1000000000000000)) + \AXI4_LITE_INTERFACE.time_control_regs_int[28][28]_i_1 + (.I0(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .I1(ipif_Addr[3]), + .I2(write_ack_int), + .I3(\data_sync[2]_2 [41]), + .I4(ipif_Addr[7]), + .I5(\AXI4_LITE_INTERFACE.time_control_regs_int[28][28]_i_2_n_0 ), + .O(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][0] )); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT4 #( + .INIT(16'h0400)) + \AXI4_LITE_INTERFACE.time_control_regs_int[28][28]_i_2 + (.I0(ipif_Addr[5]), + .I1(vid_aclk_en), + .I2(ipif_Addr[6]), + .I3(ipif_Addr[4]), + .O(\AXI4_LITE_INTERFACE.time_control_regs_int[28][28]_i_2_n_0 )); + LUT3 #( + .INIT(8'h0E)) + \AXI4_LITE_INTERFACE.write_ack_e1_i_2 + (.I0(\data_sync[2]_2 [41]), + .I1(\data_sync[2]_2 [42]), + .I2(\data_sync[2]_2 [43]), + .O(p_533_out)); + (* SOFT_HLUTNM = "soft_lutpair253" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][0]_i_1 + (.I0(\genr_status_regs_int_reg[1] [0]), + .I1(\genr_control_regs[0] [0]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][0] )); + (* SOFT_HLUTNM = "soft_lutpair259" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][10]_i_1 + (.I0(\genr_status_regs_int_reg[1] [10]), + .I1(\genr_control_regs[0] [7]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][10] )); + (* SOFT_HLUTNM = "soft_lutpair260" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][11]_i_1 + (.I0(\genr_status_regs_int_reg[1] [11]), + .I1(\genr_control_regs[0] [8]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][11] )); + (* SOFT_HLUTNM = "soft_lutpair260" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][12]_i_1 + (.I0(\genr_status_regs_int_reg[1] [12]), + .I1(\genr_status_regs[0] [3]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][12] )); + (* SOFT_HLUTNM = "soft_lutpair261" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][13]_i_1 + (.I0(\genr_status_regs_int_reg[1] [13]), + .I1(\genr_control_regs[0] [9]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][13] )); + (* SOFT_HLUTNM = "soft_lutpair261" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][14]_i_1 + (.I0(\genr_status_regs_int_reg[1] [14]), + .I1(\genr_control_regs[0] [10]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][14] )); + (* SOFT_HLUTNM = "soft_lutpair254" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][15]_i_1 + (.I0(\genr_status_regs_int_reg[1] [15]), + .I1(\genr_control_regs[0] [11]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][15] )); + (* SOFT_HLUTNM = "soft_lutpair262" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][16]_i_1 + (.I0(\genr_status_regs_int_reg[1] [16]), + .I1(\genr_control_regs[0] [12]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][16] )); + (* SOFT_HLUTNM = "soft_lutpair263" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][17]_i_1 + (.I0(\genr_status_regs_int_reg[1] [17]), + .I1(\genr_control_regs[0] [13]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][17] )); + (* SOFT_HLUTNM = "soft_lutpair263" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][18]_i_1 + (.I0(\genr_status_regs_int_reg[1] [18]), + .I1(\genr_control_regs[0] [14]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][18] )); + (* SOFT_HLUTNM = "soft_lutpair264" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][19]_i_1 + (.I0(\genr_status_regs_int_reg[1] [19]), + .I1(\genr_control_regs[0] [15]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][19] )); + (* SOFT_HLUTNM = "soft_lutpair254" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][1]_i_1 + (.I0(\genr_status_regs_int_reg[1] [1]), + .I1(\genr_control_regs[0] [1]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][1] )); + (* SOFT_HLUTNM = "soft_lutpair264" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][20]_i_1 + (.I0(\genr_status_regs_int_reg[1] [20]), + .I1(\genr_control_regs[0] [16]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][20] )); + (* SOFT_HLUTNM = "soft_lutpair265" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][21]_i_1 + (.I0(\genr_status_regs_int_reg[1] [21]), + .I1(\genr_control_regs[0] [17]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][21] )); + (* SOFT_HLUTNM = "soft_lutpair265" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][22]_i_1 + (.I0(\genr_status_regs_int_reg[1] [22]), + .I1(\genr_control_regs[0] [18]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][22] )); + (* SOFT_HLUTNM = "soft_lutpair266" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][23]_i_1 + (.I0(\genr_status_regs_int_reg[1] [23]), + .I1(\genr_control_regs[0] [19]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][23] )); + (* SOFT_HLUTNM = "soft_lutpair266" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][24]_i_1 + (.I0(\genr_status_regs_int_reg[1] [24]), + .I1(\genr_control_regs[0] [20]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][24] )); + (* SOFT_HLUTNM = "soft_lutpair267" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][25]_i_1 + (.I0(\genr_status_regs_int_reg[1] [25]), + .I1(\genr_control_regs[0] [21]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][25] )); + (* SOFT_HLUTNM = "soft_lutpair267" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][26]_i_1 + (.I0(\genr_status_regs_int_reg[1] [26]), + .I1(\genr_control_regs[0] [22]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][26] )); + (* SOFT_HLUTNM = "soft_lutpair268" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][27]_i_1 + (.I0(\genr_status_regs_int_reg[1] [27]), + .I1(\genr_status_regs[0] [4]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][27] )); + (* SOFT_HLUTNM = "soft_lutpair268" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][28]_i_1 + (.I0(\genr_status_regs_int_reg[1] [28]), + .I1(\genr_status_regs[0] [5]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][28] )); + (* SOFT_HLUTNM = "soft_lutpair262" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][29]_i_1 + (.I0(\genr_status_regs_int_reg[1] [29]), + .I1(\genr_status_regs[0] [6]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][29] )); + (* SOFT_HLUTNM = "soft_lutpair255" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][2]_i_1 + (.I0(\genr_status_regs_int_reg[1] [2]), + .I1(\genr_control_regs[0] [2]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][2] )); + (* SOFT_HLUTNM = "soft_lutpair255" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][30]_i_1 + (.I0(\genr_status_regs_int_reg[1] [30]), + .I1(\genr_control_regs[0] [23]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][30] )); + LUT2 #( + .INIT(4'h2)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][31]_i_1 + (.I0(\genr_control_regs[0] [24]), + .I1(\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][31] )); + (* SOFT_HLUTNM = "soft_lutpair256" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][3]_i_1 + (.I0(\genr_status_regs_int_reg[1] [3]), + .I1(\genr_control_regs[0] [3]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][3] )); + (* SOFT_HLUTNM = "soft_lutpair256" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][4]_i_1 + (.I0(\genr_status_regs_int_reg[1] [4]), + .I1(\genr_status_regs[0] [0]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][4] )); + (* SOFT_HLUTNM = "soft_lutpair257" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][5]_i_1 + (.I0(\genr_status_regs_int_reg[1] [5]), + .I1(\genr_control_regs[0] [4]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][5] )); + (* SOFT_HLUTNM = "soft_lutpair257" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][6]_i_1 + (.I0(\genr_status_regs_int_reg[1] [6]), + .I1(\genr_status_regs[0] [1]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][6] )); + (* SOFT_HLUTNM = "soft_lutpair258" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][7]_i_1 + (.I0(\genr_status_regs_int_reg[1] [7]), + .I1(\genr_status_regs[0] [2]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][7] )); + (* SOFT_HLUTNM = "soft_lutpair258" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][8]_i_1 + (.I0(\genr_status_regs_int_reg[1] [8]), + .I1(\genr_control_regs[0] [5]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][8] )); + (* SOFT_HLUTNM = "soft_lutpair259" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][9]_i_1 + (.I0(\genr_status_regs_int_reg[1] [9]), + .I1(\genr_control_regs[0] [6]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][9] )); + (* SOFT_HLUTNM = "soft_lutpair207" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][0]_i_1 + (.I0(\genr_status_regs[3] [0]), + .I1(intr_err[0]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][0] )); + (* SOFT_HLUTNM = "soft_lutpair243" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][10]_i_1 + (.I0(\genr_control_regs[3] [2]), + .I1(intr_err[10]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][10] )); + (* SOFT_HLUTNM = "soft_lutpair244" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][11]_i_1 + (.I0(\genr_control_regs[3] [3]), + .I1(intr_err[11]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][11] )); + (* SOFT_HLUTNM = "soft_lutpair244" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][12]_i_1 + (.I0(\genr_control_regs[3] [4]), + .I1(intr_err[12]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][12] )); + (* SOFT_HLUTNM = "soft_lutpair245" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][13]_i_1 + (.I0(\genr_control_regs[3] [5]), + .I1(intr_err[13]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][13] )); + (* SOFT_HLUTNM = "soft_lutpair245" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][14]_i_1 + (.I0(\genr_status_regs[3] [8]), + .I1(intr_err[14]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][14] )); + (* SOFT_HLUTNM = "soft_lutpair246" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][15]_i_1 + (.I0(\genr_status_regs[3] [9]), + .I1(intr_err[15]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][15] )); + (* SOFT_HLUTNM = "soft_lutpair246" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][16]_i_1 + (.I0(\genr_control_regs[3] [6]), + .I1(intr_err[16]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][16] )); + (* SOFT_HLUTNM = "soft_lutpair247" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][17]_i_1 + (.I0(\genr_control_regs[3] [7]), + .I1(intr_err[17]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][17] )); + (* SOFT_HLUTNM = "soft_lutpair247" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][18]_i_1 + (.I0(\genr_control_regs[3] [8]), + .I1(intr_err[18]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][18] )); + (* SOFT_HLUTNM = "soft_lutpair248" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][19]_i_1 + (.I0(\genr_control_regs[3] [9]), + .I1(intr_err[19]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][19] )); + (* SOFT_HLUTNM = "soft_lutpair238" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][1]_i_1 + (.I0(\genr_status_regs[3] [1]), + .I1(intr_err[1]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][1] )); + (* SOFT_HLUTNM = "soft_lutpair248" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][20]_i_1 + (.I0(\genr_control_regs[3] [10]), + .I1(intr_err[20]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][20] )); + (* SOFT_HLUTNM = "soft_lutpair249" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][21]_i_1 + (.I0(\genr_control_regs[3] [11]), + .I1(intr_err[21]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][21] )); + (* SOFT_HLUTNM = "soft_lutpair249" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][22]_i_1 + (.I0(\genr_control_regs[3] [12]), + .I1(intr_err[22]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][22] )); + (* SOFT_HLUTNM = "soft_lutpair250" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][23]_i_1 + (.I0(\genr_control_regs[3] [13]), + .I1(intr_err[23]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][23] )); + (* SOFT_HLUTNM = "soft_lutpair250" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][24]_i_1 + (.I0(\genr_control_regs[3] [14]), + .I1(intr_err[24]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][24] )); + (* SOFT_HLUTNM = "soft_lutpair251" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][25]_i_1 + (.I0(\genr_control_regs[3] [15]), + .I1(intr_err[25]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][25] )); + (* SOFT_HLUTNM = "soft_lutpair251" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][26]_i_1 + (.I0(\genr_control_regs[3] [16]), + .I1(intr_err[26]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][26] )); + (* SOFT_HLUTNM = "soft_lutpair252" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][27]_i_1 + (.I0(\genr_control_regs[3] [17]), + .I1(intr_err[27]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][27] )); + (* SOFT_HLUTNM = "soft_lutpair252" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][28]_i_1 + (.I0(\genr_control_regs[3] [18]), + .I1(intr_err[28]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][28] )); + (* SOFT_HLUTNM = "soft_lutpair253" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][29]_i_1 + (.I0(\genr_control_regs[3] [19]), + .I1(intr_err[29]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][29] )); + (* SOFT_HLUTNM = "soft_lutpair239" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][2]_i_1 + (.I0(\genr_status_regs[3] [2]), + .I1(intr_err[2]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][2] )); + (* SOFT_HLUTNM = "soft_lutpair238" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][30]_i_1 + (.I0(\genr_control_regs[3] [20]), + .I1(intr_err[30]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][30] )); + (* SOFT_HLUTNM = "soft_lutpair239" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][31]_i_1 + (.I0(\genr_control_regs[3] [21]), + .I1(intr_err[31]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][31] )); + (* SOFT_HLUTNM = "soft_lutpair240" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][3]_i_1 + (.I0(\genr_status_regs[3] [3]), + .I1(intr_err[3]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][3] )); + (* SOFT_HLUTNM = "soft_lutpair240" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][4]_i_1 + (.I0(\genr_status_regs[3] [4]), + .I1(intr_err[4]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][4] )); + (* SOFT_HLUTNM = "soft_lutpair241" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][5]_i_1 + (.I0(\genr_status_regs[3] [5]), + .I1(intr_err[5]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][5] )); + (* SOFT_HLUTNM = "soft_lutpair241" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][6]_i_1 + (.I0(\genr_status_regs[3] [6]), + .I1(intr_err[6]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][6] )); + (* SOFT_HLUTNM = "soft_lutpair242" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][7]_i_1 + (.I0(\genr_status_regs[3] [7]), + .I1(intr_err[7]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][7] )); + (* SOFT_HLUTNM = "soft_lutpair242" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][8]_i_1 + (.I0(\genr_control_regs[3] [0]), + .I1(intr_err[8]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][8] )); + (* SOFT_HLUTNM = "soft_lutpair243" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][9]_i_1 + (.I0(\genr_control_regs[3] [1]), + .I1(intr_err[9]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][9] )); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT1 #( + .INIT(2'h1)) + \GEN_TREE.GEN_BRANCH[33].GEN_MUX_REG.data_out_reg[33][26]_i_1 + (.I0(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[33].GEN_MUX_REG.data_out_reg_reg[33][26] )); + (* SOFT_HLUTNM = "soft_lutpair223" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][0]_i_1 + (.I0(\time_status_regs[1] [0]), + .I1(\time_status_regs[0] [0]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][0] )); + (* SOFT_HLUTNM = "soft_lutpair228" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][10]_i_1 + (.I0(\time_status_regs[1] [10]), + .I1(\time_status_regs[0] [10]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][10] )); + (* SOFT_HLUTNM = "soft_lutpair228" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][11]_i_1 + (.I0(\time_status_regs[1] [11]), + .I1(\time_status_regs[0] [11]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] )); + (* SOFT_HLUTNM = "soft_lutpair229" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][12]_i_1 + (.I0(\time_status_regs[1] [12]), + .I1(\time_status_regs[0] [12]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][12] )); + (* SOFT_HLUTNM = "soft_lutpair229" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][13]_i_1 + (.I0(\time_status_regs[1] [13]), + .I1(\time_status_regs[0] [13]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][13] )); + (* SOFT_HLUTNM = "soft_lutpair230" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][14]_i_1 + (.I0(\time_status_regs[1] [14]), + .I1(\time_status_regs[0] [14]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][14] )); + (* SOFT_HLUTNM = "soft_lutpair230" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][15]_i_1 + (.I0(\time_status_regs[1] [15]), + .I1(\time_status_regs[0] [15]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][15] )); + (* SOFT_HLUTNM = "soft_lutpair231" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][16]_i_1 + (.I0(\time_status_regs[1] [16]), + .I1(\time_status_regs[0] [16]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][16] )); + (* SOFT_HLUTNM = "soft_lutpair231" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][17]_i_1 + (.I0(\time_status_regs[1] [17]), + .I1(\time_status_regs[0] [17]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][17] )); + (* SOFT_HLUTNM = "soft_lutpair232" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][18]_i_1 + (.I0(\time_status_regs[1] [18]), + .I1(\time_status_regs[0] [18]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][18] )); + (* SOFT_HLUTNM = "soft_lutpair232" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][19]_i_1 + (.I0(\time_status_regs[1] [19]), + .I1(\time_status_regs[0] [19]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][19] )); + (* SOFT_HLUTNM = "soft_lutpair223" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][1]_i_1 + (.I0(\time_status_regs[1] [1]), + .I1(\time_status_regs[0] [1]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][1] )); + (* SOFT_HLUTNM = "soft_lutpair233" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][20]_i_1 + (.I0(\time_status_regs[1] [20]), + .I1(\time_status_regs[0] [20]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][20] )); + (* SOFT_HLUTNM = "soft_lutpair233" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][21]_i_1 + (.I0(\time_status_regs[1] [21]), + .I1(\time_status_regs[0] [21]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][21] )); + (* SOFT_HLUTNM = "soft_lutpair234" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][22]_i_1 + (.I0(\time_status_regs[1] [22]), + .I1(\time_status_regs[0] [22]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][22] )); + (* SOFT_HLUTNM = "soft_lutpair234" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][23]_i_1 + (.I0(\time_status_regs[1] [23]), + .I1(\time_status_regs[0] [23]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][23] )); + (* SOFT_HLUTNM = "soft_lutpair235" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][24]_i_1 + (.I0(\time_status_regs[1] [24]), + .I1(\time_status_regs[0] [24]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][24] )); + (* SOFT_HLUTNM = "soft_lutpair235" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][25]_i_1 + (.I0(\time_status_regs[1] [25]), + .I1(\time_status_regs[0] [25]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][25] )); + (* SOFT_HLUTNM = "soft_lutpair236" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][26]_i_1 + (.I0(\time_status_regs[1] [26]), + .I1(\time_status_regs[0] [26]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][26] )); + (* SOFT_HLUTNM = "soft_lutpair236" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][27]_i_1 + (.I0(\time_status_regs[1] [27]), + .I1(\time_status_regs[0] [27]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][27] )); + (* SOFT_HLUTNM = "soft_lutpair237" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][28]_i_1 + (.I0(\time_status_regs[1] [28]), + .I1(\time_status_regs[0] [28]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][28] )); + (* SOFT_HLUTNM = "soft_lutpair206" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][29]_i_1 + (.I0(\time_status_regs[1] [29]), + .I1(\time_status_regs[0] [29]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][29] )); + (* SOFT_HLUTNM = "soft_lutpair224" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][2]_i_1 + (.I0(\time_status_regs[1] [2]), + .I1(\time_status_regs[0] [2]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][2] )); + (* SOFT_HLUTNM = "soft_lutpair237" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][30]_i_1 + (.I0(\time_status_regs[1] [30]), + .I1(\time_status_regs[0] [30]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][30] )); + (* SOFT_HLUTNM = "soft_lutpair207" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][31]_i_1 + (.I0(\time_status_regs[1] [31]), + .I1(\time_status_regs[0] [31]), + .I2(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31]_0 )); + (* IS_FANOUT_CONSTRAINED = "1" *) + LUT1 #( + .INIT(2'h2)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][31]_i_2 + (.I0(\data_sync[2]_2 [34]), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] )); + (* SOFT_HLUTNM = "soft_lutpair224" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][3]_i_1 + (.I0(\time_status_regs[1] [3]), + .I1(\time_status_regs[0] [3]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][3] )); + (* SOFT_HLUTNM = "soft_lutpair225" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][4]_i_1 + (.I0(\time_status_regs[1] [4]), + .I1(\time_status_regs[0] [4]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][4] )); + (* SOFT_HLUTNM = "soft_lutpair225" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][5]_i_1 + (.I0(\time_status_regs[1] [5]), + .I1(\time_status_regs[0] [5]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][5] )); + (* SOFT_HLUTNM = "soft_lutpair226" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][6]_i_1 + (.I0(\time_status_regs[1] [6]), + .I1(\time_status_regs[0] [6]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][6] )); + (* SOFT_HLUTNM = "soft_lutpair226" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][7]_i_1 + (.I0(\time_status_regs[1] [7]), + .I1(\time_status_regs[0] [7]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][7] )); + (* SOFT_HLUTNM = "soft_lutpair227" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][8]_i_1 + (.I0(\time_status_regs[1] [8]), + .I1(\time_status_regs[0] [8]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][8] )); + (* SOFT_HLUTNM = "soft_lutpair227" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][9]_i_1 + (.I0(\time_status_regs[1] [9]), + .I1(\time_status_regs[0] [9]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][9] )); + (* SOFT_HLUTNM = "soft_lutpair204" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][0]_i_1 + (.I0(\time_status_regs[3] [0]), + .I1(\time_status_regs[2] [0]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][0] )); + (* SOFT_HLUTNM = "soft_lutpair212" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][10]_i_1 + (.I0(\time_status_regs[3] [10]), + .I1(\time_status_regs[2] [10]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][10] )); + (* SOFT_HLUTNM = "soft_lutpair212" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][11]_i_1 + (.I0(\time_status_regs[3] [11]), + .I1(\time_status_regs[2] [11]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][11] )); + (* SOFT_HLUTNM = "soft_lutpair213" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][12]_i_1 + (.I0(\time_status_regs[3] [12]), + .I1(\time_status_regs[2] [12]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][12] )); + (* SOFT_HLUTNM = "soft_lutpair213" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][13]_i_1 + (.I0(\time_status_regs[3] [13]), + .I1(\time_status_regs[2] [13]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][13] )); + (* SOFT_HLUTNM = "soft_lutpair214" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][14]_i_1 + (.I0(\time_status_regs[3] [14]), + .I1(\time_status_regs[2] [14]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][14] )); + (* SOFT_HLUTNM = "soft_lutpair214" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][15]_i_1 + (.I0(\time_status_regs[3] [15]), + .I1(\time_status_regs[2] [15]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][15] )); + (* SOFT_HLUTNM = "soft_lutpair215" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][16]_i_1 + (.I0(\time_status_regs[3] [16]), + .I1(\time_status_regs[2] [16]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][16] )); + (* SOFT_HLUTNM = "soft_lutpair215" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][17]_i_1 + (.I0(\time_status_regs[3] [17]), + .I1(\time_status_regs[2] [17]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][17] )); + (* SOFT_HLUTNM = "soft_lutpair216" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][18]_i_1 + (.I0(\time_status_regs[3] [18]), + .I1(\time_status_regs[2] [18]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][18] )); + (* SOFT_HLUTNM = "soft_lutpair216" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][19]_i_1 + (.I0(\time_status_regs[3] [19]), + .I1(\time_status_regs[2] [19]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][19] )); + (* SOFT_HLUTNM = "soft_lutpair206" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][1]_i_1 + (.I0(\time_status_regs[3] [1]), + .I1(\time_status_regs[2] [1]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][1] )); + (* SOFT_HLUTNM = "soft_lutpair217" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][20]_i_1 + (.I0(\time_status_regs[3] [20]), + .I1(\time_status_regs[2] [20]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][20] )); + (* SOFT_HLUTNM = "soft_lutpair217" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][21]_i_1 + (.I0(\time_status_regs[3] [21]), + .I1(\time_status_regs[2] [21]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][21] )); + (* SOFT_HLUTNM = "soft_lutpair218" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][22]_i_1 + (.I0(\time_status_regs[3] [22]), + .I1(\time_status_regs[2] [22]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][22] )); + (* SOFT_HLUTNM = "soft_lutpair218" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][23]_i_1 + (.I0(\time_status_regs[3] [23]), + .I1(\time_status_regs[2] [23]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][23] )); + (* SOFT_HLUTNM = "soft_lutpair219" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][24]_i_1 + (.I0(\time_status_regs[3] [24]), + .I1(\time_status_regs[2] [24]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][24] )); + (* SOFT_HLUTNM = "soft_lutpair219" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][25]_i_1 + (.I0(\time_status_regs[3] [25]), + .I1(\time_status_regs[2] [25]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][25] )); + (* SOFT_HLUTNM = "soft_lutpair220" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][26]_i_1 + (.I0(\time_status_regs[3] [26]), + .I1(\time_status_regs[2] [26]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][26] )); + (* SOFT_HLUTNM = "soft_lutpair220" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][27]_i_1 + (.I0(\time_status_regs[3] [27]), + .I1(\time_status_regs[2] [27]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][27] )); + (* SOFT_HLUTNM = "soft_lutpair221" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][28]_i_1 + (.I0(\time_status_regs[3] [28]), + .I1(\time_status_regs[2] [28]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][28] )); + (* SOFT_HLUTNM = "soft_lutpair221" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][29]_i_1 + (.I0(\time_status_regs[3] [29]), + .I1(\time_status_regs[2] [29]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][29] )); + (* SOFT_HLUTNM = "soft_lutpair208" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][2]_i_1 + (.I0(\time_status_regs[3] [2]), + .I1(\time_status_regs[2] [2]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][2] )); + (* SOFT_HLUTNM = "soft_lutpair222" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][30]_i_1 + (.I0(\time_status_regs[3] [30]), + .I1(\time_status_regs[2] [30]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][30] )); + (* SOFT_HLUTNM = "soft_lutpair222" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][31]_i_1 + (.I0(\time_status_regs[3] [31]), + .I1(\time_status_regs[2] [31]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][31] )); + (* SOFT_HLUTNM = "soft_lutpair208" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][3]_i_1 + (.I0(\time_status_regs[3] [3]), + .I1(\time_status_regs[2] [3]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][3] )); + (* SOFT_HLUTNM = "soft_lutpair209" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][4]_i_1 + (.I0(\time_status_regs[3] [4]), + .I1(\time_status_regs[2] [4]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][4] )); + (* SOFT_HLUTNM = "soft_lutpair209" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][5]_i_1 + (.I0(\time_status_regs[3] [5]), + .I1(\time_status_regs[2] [5]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][5] )); + (* SOFT_HLUTNM = "soft_lutpair210" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][6]_i_1 + (.I0(\time_status_regs[3] [6]), + .I1(\time_status_regs[2] [6]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][6] )); + (* SOFT_HLUTNM = "soft_lutpair210" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][7]_i_1 + (.I0(\time_status_regs[3] [7]), + .I1(\time_status_regs[2] [7]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][7] )); + (* SOFT_HLUTNM = "soft_lutpair211" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][8]_i_1 + (.I0(\time_status_regs[3] [8]), + .I1(\time_status_regs[2] [8]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][8] )); + (* SOFT_HLUTNM = "soft_lutpair211" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][9]_i_1 + (.I0(\time_status_regs[3] [9]), + .I1(\time_status_regs[2] [9]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][9] )); + (* SOFT_HLUTNM = "soft_lutpair190" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][0]_i_1 + (.I0(\time_status_regs[5] [0]), + .I1(\time_status_regs[4] [0]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][0] )); + (* SOFT_HLUTNM = "soft_lutpair195" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][10]_i_1 + (.I0(\time_status_regs[5] [10]), + .I1(\time_status_regs[4] [10]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10] )); + (* SOFT_HLUTNM = "soft_lutpair196" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][11]_i_1 + (.I0(\time_status_regs[5] [11]), + .I1(\time_status_regs[4] [11]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][11] )); + (* SOFT_HLUTNM = "soft_lutpair196" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][12]_i_1 + (.I0(\time_status_regs[5] [12]), + .I1(\time_status_regs[4] [12]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][12] )); + (* SOFT_HLUTNM = "soft_lutpair197" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][13]_i_1 + (.I0(\time_status_regs[5] [13]), + .I1(\time_status_regs[4] [13]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][13] )); + (* SOFT_HLUTNM = "soft_lutpair197" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][14]_i_1 + (.I0(\time_status_regs[5] [14]), + .I1(\time_status_regs[4] [14]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][14] )); + (* SOFT_HLUTNM = "soft_lutpair198" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][15]_i_1 + (.I0(\time_status_regs[5] [15]), + .I1(\time_status_regs[4] [15]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][15] )); + (* SOFT_HLUTNM = "soft_lutpair198" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][16]_i_1 + (.I0(\time_status_regs[5] [16]), + .I1(\time_status_regs[4] [16]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][16] )); + (* SOFT_HLUTNM = "soft_lutpair199" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][17]_i_1 + (.I0(\time_status_regs[5] [17]), + .I1(\time_status_regs[4] [17]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][17] )); + (* SOFT_HLUTNM = "soft_lutpair199" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][18]_i_1 + (.I0(\time_status_regs[5] [18]), + .I1(\time_status_regs[4] [18]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][18] )); + (* SOFT_HLUTNM = "soft_lutpair200" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][19]_i_1 + (.I0(\time_status_regs[5] [19]), + .I1(\time_status_regs[4] [19]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][19] )); + (* SOFT_HLUTNM = "soft_lutpair191" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][1]_i_1 + (.I0(\time_status_regs[5] [1]), + .I1(\time_status_regs[4] [1]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][1] )); + (* SOFT_HLUTNM = "soft_lutpair200" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][20]_i_1 + (.I0(\time_status_regs[5] [20]), + .I1(\time_status_regs[4] [20]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][20] )); + (* SOFT_HLUTNM = "soft_lutpair201" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][21]_i_1 + (.I0(\time_status_regs[5] [21]), + .I1(\time_status_regs[4] [21]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][21] )); + (* SOFT_HLUTNM = "soft_lutpair201" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][22]_i_1 + (.I0(\time_status_regs[5] [22]), + .I1(\time_status_regs[4] [22]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][22] )); + (* SOFT_HLUTNM = "soft_lutpair202" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][23]_i_1 + (.I0(\time_status_regs[5] [23]), + .I1(\time_status_regs[4] [23]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][23] )); + (* SOFT_HLUTNM = "soft_lutpair202" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][24]_i_1 + (.I0(\time_status_regs[5] [24]), + .I1(\time_status_regs[4] [24]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][24] )); + (* SOFT_HLUTNM = "soft_lutpair203" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][25]_i_1 + (.I0(\time_status_regs[5] [25]), + .I1(\time_status_regs[4] [25]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][25] )); + (* SOFT_HLUTNM = "soft_lutpair203" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][26]_i_1 + (.I0(\time_status_regs[5] [26]), + .I1(\time_status_regs[4] [26]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][26] )); + (* SOFT_HLUTNM = "soft_lutpair142" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][27]_i_1 + (.I0(\time_status_regs[5] [27]), + .I1(\time_status_regs[4] [27]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][27] )); + (* SOFT_HLUTNM = "soft_lutpair204" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][28]_i_1 + (.I0(\time_status_regs[5] [28]), + .I1(\time_status_regs[4] [28]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][28] )); + (* SOFT_HLUTNM = "soft_lutpair205" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][29]_i_1 + (.I0(\time_status_regs[5] [29]), + .I1(\time_status_regs[4] [29]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][29] )); + (* SOFT_HLUTNM = "soft_lutpair191" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][2]_i_1 + (.I0(\time_status_regs[5] [2]), + .I1(\time_status_regs[4] [2]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][2] )); + (* SOFT_HLUTNM = "soft_lutpair205" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][30]_i_1 + (.I0(\time_status_regs[5] [30]), + .I1(\time_status_regs[4] [30]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][30] )); + (* SOFT_HLUTNM = "soft_lutpair143" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][31]_i_1 + (.I0(\time_status_regs[5] [31]), + .I1(\time_status_regs[4] [31]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][31] )); + (* SOFT_HLUTNM = "soft_lutpair192" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][3]_i_1 + (.I0(\time_status_regs[5] [3]), + .I1(\time_status_regs[4] [3]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][3] )); + (* SOFT_HLUTNM = "soft_lutpair192" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][4]_i_1 + (.I0(\time_status_regs[5] [4]), + .I1(\time_status_regs[4] [4]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][4] )); + (* SOFT_HLUTNM = "soft_lutpair193" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][5]_i_1 + (.I0(\time_status_regs[5] [5]), + .I1(\time_status_regs[4] [5]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][5] )); + (* SOFT_HLUTNM = "soft_lutpair193" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][6]_i_1 + (.I0(\time_status_regs[5] [6]), + .I1(\time_status_regs[4] [6]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][6] )); + (* SOFT_HLUTNM = "soft_lutpair194" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][7]_i_1 + (.I0(\time_status_regs[5] [7]), + .I1(\time_status_regs[4] [7]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][7] )); + (* SOFT_HLUTNM = "soft_lutpair194" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][8]_i_1 + (.I0(\time_status_regs[5] [8]), + .I1(\time_status_regs[4] [8]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][8] )); + (* SOFT_HLUTNM = "soft_lutpair195" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][9]_i_1 + (.I0(\time_status_regs[5] [9]), + .I1(\time_status_regs[4] [9]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][9] )); + (* SOFT_HLUTNM = "soft_lutpair175" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][0]_i_1 + (.I0(\time_status_regs[7] [0]), + .I1(\time_status_regs[6] [0]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][0] )); + (* SOFT_HLUTNM = "soft_lutpair180" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][10]_i_1 + (.I0(\time_status_regs[7] [10]), + .I1(\time_status_regs[6] [10]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][10] )); + (* SOFT_HLUTNM = "soft_lutpair181" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][11]_i_1 + (.I0(\time_status_regs[7] [11]), + .I1(\time_status_regs[6] [11]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][11] )); + (* SOFT_HLUTNM = "soft_lutpair181" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][12]_i_1 + (.I0(\time_status_regs[7] [12]), + .I1(\time_status_regs[6] [12]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][12] )); + (* SOFT_HLUTNM = "soft_lutpair182" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][13]_i_1 + (.I0(\time_status_regs[7] [13]), + .I1(\time_status_regs[6] [13]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][13] )); + (* SOFT_HLUTNM = "soft_lutpair182" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][14]_i_1 + (.I0(\time_status_regs[7] [14]), + .I1(\time_status_regs[6] [14]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][14] )); + (* SOFT_HLUTNM = "soft_lutpair142" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][15]_i_1 + (.I0(\time_status_regs[7] [15]), + .I1(\time_status_regs[6] [15]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][15] )); + (* SOFT_HLUTNM = "soft_lutpair143" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][16]_i_1 + (.I0(\time_status_regs[7] [16]), + .I1(\time_status_regs[6] [16]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][16] )); + (* SOFT_HLUTNM = "soft_lutpair183" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][17]_i_1 + (.I0(\time_status_regs[7] [17]), + .I1(\time_status_regs[6] [17]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][17] )); + (* SOFT_HLUTNM = "soft_lutpair183" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][18]_i_1 + (.I0(\time_status_regs[7] [18]), + .I1(\time_status_regs[6] [18]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][18] )); + (* SOFT_HLUTNM = "soft_lutpair184" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][19]_i_1 + (.I0(\time_status_regs[7] [19]), + .I1(\time_status_regs[6] [19]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][19] )); + (* SOFT_HLUTNM = "soft_lutpair176" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][1]_i_1 + (.I0(\time_status_regs[7] [1]), + .I1(\time_status_regs[6] [1]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][1] )); + (* SOFT_HLUTNM = "soft_lutpair184" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][20]_i_1 + (.I0(\time_status_regs[7] [20]), + .I1(\time_status_regs[6] [20]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][20] )); + (* SOFT_HLUTNM = "soft_lutpair185" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][21]_i_1 + (.I0(\time_status_regs[7] [21]), + .I1(\time_status_regs[6] [21]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][21] )); + (* SOFT_HLUTNM = "soft_lutpair185" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][22]_i_1 + (.I0(\time_status_regs[7] [22]), + .I1(\time_status_regs[6] [22]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][22] )); + (* SOFT_HLUTNM = "soft_lutpair186" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][23]_i_1 + (.I0(\time_status_regs[7] [23]), + .I1(\time_status_regs[6] [23]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][23] )); + (* SOFT_HLUTNM = "soft_lutpair186" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][24]_i_1 + (.I0(\time_status_regs[7] [24]), + .I1(\time_status_regs[6] [24]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][24] )); + (* SOFT_HLUTNM = "soft_lutpair187" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][25]_i_1 + (.I0(\time_status_regs[7] [25]), + .I1(\time_status_regs[6] [25]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][25] )); + (* SOFT_HLUTNM = "soft_lutpair187" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][26]_i_1 + (.I0(\time_status_regs[7] [26]), + .I1(\time_status_regs[6] [26]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][26] )); + (* SOFT_HLUTNM = "soft_lutpair188" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][27]_i_1 + (.I0(\time_status_regs[7] [27]), + .I1(\time_status_regs[6] [27]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][27] )); + (* SOFT_HLUTNM = "soft_lutpair188" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][28]_i_1 + (.I0(\time_status_regs[7] [28]), + .I1(\time_status_regs[6] [28]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][28] )); + (* SOFT_HLUTNM = "soft_lutpair189" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][29]_i_1 + (.I0(\time_status_regs[7] [29]), + .I1(\time_status_regs[6] [29]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][29] )); + (* SOFT_HLUTNM = "soft_lutpair176" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][2]_i_1 + (.I0(\time_status_regs[7] [2]), + .I1(\time_status_regs[6] [2]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][2] )); + (* SOFT_HLUTNM = "soft_lutpair189" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][30]_i_1 + (.I0(\time_status_regs[7] [30]), + .I1(\time_status_regs[6] [30]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][30] )); + (* SOFT_HLUTNM = "soft_lutpair190" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_1 + (.I0(\time_status_regs[7] [31]), + .I1(\time_status_regs[6] [31]), + .I2(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][31] )); + (* IS_FANOUT_CONSTRAINED = "1" *) + LUT1 #( + .INIT(2'h2)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2 + (.I0(\data_sync[2]_2 [34]), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair177" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][3]_i_1 + (.I0(\time_status_regs[7] [3]), + .I1(\time_status_regs[6] [3]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][3] )); + (* SOFT_HLUTNM = "soft_lutpair177" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][4]_i_1 + (.I0(\time_status_regs[7] [4]), + .I1(\time_status_regs[6] [4]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][4] )); + (* SOFT_HLUTNM = "soft_lutpair178" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][5]_i_1 + (.I0(\time_status_regs[7] [5]), + .I1(\time_status_regs[6] [5]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][5] )); + (* SOFT_HLUTNM = "soft_lutpair178" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][6]_i_1 + (.I0(\time_status_regs[7] [6]), + .I1(\time_status_regs[6] [6]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][6] )); + (* SOFT_HLUTNM = "soft_lutpair179" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][7]_i_1 + (.I0(\time_status_regs[7] [7]), + .I1(\time_status_regs[6] [7]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][7] )); + (* SOFT_HLUTNM = "soft_lutpair179" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][8]_i_1 + (.I0(\time_status_regs[7] [8]), + .I1(\time_status_regs[6] [8]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][8] )); + (* SOFT_HLUTNM = "soft_lutpair180" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][9]_i_1 + (.I0(\time_status_regs[7] [9]), + .I1(\time_status_regs[6] [9]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][9] )); + (* SOFT_HLUTNM = "soft_lutpair159" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][0]_i_1 + (.I0(\time_status_regs[9] [0]), + .I1(\time_status_regs[8] [0]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][0] )); + (* SOFT_HLUTNM = "soft_lutpair164" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][10]_i_1 + (.I0(\time_status_regs[9] [10]), + .I1(\time_status_regs[8] [10]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][10] )); + (* SOFT_HLUTNM = "soft_lutpair165" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][11]_i_1 + (.I0(\time_status_regs[9] [11]), + .I1(\time_status_regs[8] [11]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][11] )); + (* SOFT_HLUTNM = "soft_lutpair165" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][12]_i_1 + (.I0(\time_status_regs[9] [12]), + .I1(\time_status_regs[8] [12]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][12] )); + (* SOFT_HLUTNM = "soft_lutpair166" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][13]_i_1 + (.I0(\time_status_regs[9] [13]), + .I1(\time_status_regs[8] [13]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][13] )); + (* SOFT_HLUTNM = "soft_lutpair166" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][14]_i_1 + (.I0(\time_status_regs[9] [14]), + .I1(\time_status_regs[8] [14]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][14] )); + (* SOFT_HLUTNM = "soft_lutpair167" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][15]_i_1 + (.I0(\time_status_regs[9] [15]), + .I1(\time_status_regs[8] [15]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][15] )); + (* SOFT_HLUTNM = "soft_lutpair167" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][16]_i_1 + (.I0(\time_status_regs[9] [16]), + .I1(\time_status_regs[8] [16]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][16] )); + (* SOFT_HLUTNM = "soft_lutpair168" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][17]_i_1 + (.I0(\time_status_regs[9] [17]), + .I1(\time_status_regs[8] [17]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][17] )); + (* SOFT_HLUTNM = "soft_lutpair168" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][18]_i_1 + (.I0(\time_status_regs[9] [18]), + .I1(\time_status_regs[8] [18]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][18] )); + (* SOFT_HLUTNM = "soft_lutpair169" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][19]_i_1 + (.I0(\time_status_regs[9] [19]), + .I1(\time_status_regs[8] [19]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][19] )); + (* SOFT_HLUTNM = "soft_lutpair160" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][1]_i_1 + (.I0(\time_status_regs[9] [1]), + .I1(\time_status_regs[8] [1]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][1] )); + (* SOFT_HLUTNM = "soft_lutpair169" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][20]_i_1 + (.I0(\time_status_regs[9] [20]), + .I1(\time_status_regs[8] [20]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][20] )); + (* SOFT_HLUTNM = "soft_lutpair170" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][21]_i_1 + (.I0(\time_status_regs[9] [21]), + .I1(\time_status_regs[8] [21]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][21] )); + (* SOFT_HLUTNM = "soft_lutpair170" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][22]_i_1 + (.I0(\time_status_regs[9] [22]), + .I1(\time_status_regs[8] [22]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][22] )); + (* SOFT_HLUTNM = "soft_lutpair171" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][23]_i_1 + (.I0(\time_status_regs[9] [23]), + .I1(\time_status_regs[8] [23]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][23] )); + (* SOFT_HLUTNM = "soft_lutpair171" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][24]_i_1 + (.I0(\time_status_regs[9] [24]), + .I1(\time_status_regs[8] [24]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][24] )); + (* SOFT_HLUTNM = "soft_lutpair172" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][25]_i_1 + (.I0(\time_status_regs[9] [25]), + .I1(\time_status_regs[8] [25]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][25] )); + (* SOFT_HLUTNM = "soft_lutpair172" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][26]_i_1 + (.I0(\time_status_regs[9] [26]), + .I1(\time_status_regs[8] [26]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][26] )); + (* SOFT_HLUTNM = "soft_lutpair173" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][27]_i_1 + (.I0(\time_status_regs[9] [27]), + .I1(\time_status_regs[8] [27]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][27] )); + (* SOFT_HLUTNM = "soft_lutpair173" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][28]_i_1 + (.I0(\time_status_regs[9] [28]), + .I1(\time_status_regs[8] [28]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][28] )); + (* SOFT_HLUTNM = "soft_lutpair174" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][29]_i_1 + (.I0(\time_status_regs[9] [29]), + .I1(\time_status_regs[8] [29]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][29] )); + (* SOFT_HLUTNM = "soft_lutpair160" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][2]_i_1 + (.I0(\time_status_regs[9] [2]), + .I1(\time_status_regs[8] [2]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][2] )); + (* SOFT_HLUTNM = "soft_lutpair174" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][30]_i_1 + (.I0(\time_status_regs[9] [30]), + .I1(\time_status_regs[8] [30]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][30] )); + (* SOFT_HLUTNM = "soft_lutpair175" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][31]_i_1 + (.I0(\time_status_regs[9] [31]), + .I1(\time_status_regs[8] [31]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][31] )); + (* SOFT_HLUTNM = "soft_lutpair161" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][3]_i_1 + (.I0(\time_status_regs[9] [3]), + .I1(\time_status_regs[8] [3]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][3] )); + (* SOFT_HLUTNM = "soft_lutpair161" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][4]_i_1 + (.I0(\time_status_regs[9] [4]), + .I1(\time_status_regs[8] [4]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][4] )); + (* SOFT_HLUTNM = "soft_lutpair162" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][5]_i_1 + (.I0(\time_status_regs[9] [5]), + .I1(\time_status_regs[8] [5]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][5] )); + (* SOFT_HLUTNM = "soft_lutpair162" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][6]_i_1 + (.I0(\time_status_regs[9] [6]), + .I1(\time_status_regs[8] [6]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][6] )); + (* SOFT_HLUTNM = "soft_lutpair163" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][7]_i_1 + (.I0(\time_status_regs[9] [7]), + .I1(\time_status_regs[8] [7]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][7] )); + (* SOFT_HLUTNM = "soft_lutpair163" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][8]_i_1 + (.I0(\time_status_regs[9] [8]), + .I1(\time_status_regs[8] [8]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][8] )); + (* SOFT_HLUTNM = "soft_lutpair164" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][9]_i_1 + (.I0(\time_status_regs[9] [9]), + .I1(\time_status_regs[8] [9]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][9] )); + (* SOFT_HLUTNM = "soft_lutpair138" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][0]_i_1 + (.I0(\time_status_regs[11] [0]), + .I1(\time_status_regs[10] [0]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][0] )); + (* SOFT_HLUTNM = "soft_lutpair148" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][10]_i_1 + (.I0(\time_status_regs[11] [10]), + .I1(\time_status_regs[10] [10]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][10] )); + (* SOFT_HLUTNM = "soft_lutpair149" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][11]_i_1 + (.I0(\time_status_regs[11] [11]), + .I1(\time_status_regs[10] [11]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][11] )); + (* SOFT_HLUTNM = "soft_lutpair149" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][12]_i_1 + (.I0(\time_status_regs[11] [12]), + .I1(\time_status_regs[10] [12]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][12] )); + (* SOFT_HLUTNM = "soft_lutpair150" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][13]_i_1 + (.I0(\time_status_regs[11] [13]), + .I1(\time_status_regs[10] [13]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][13] )); + (* SOFT_HLUTNM = "soft_lutpair150" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][14]_i_1 + (.I0(\time_status_regs[11] [14]), + .I1(\time_status_regs[10] [14]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][14] )); + (* SOFT_HLUTNM = "soft_lutpair151" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][15]_i_1 + (.I0(\time_status_regs[11] [15]), + .I1(\time_status_regs[10] [15]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][15] )); + (* SOFT_HLUTNM = "soft_lutpair151" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][16]_i_1 + (.I0(\time_status_regs[11] [16]), + .I1(\time_status_regs[10] [16]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][16] )); + (* SOFT_HLUTNM = "soft_lutpair152" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][17]_i_1 + (.I0(\time_status_regs[11] [17]), + .I1(\time_status_regs[10] [17]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][17] )); + (* SOFT_HLUTNM = "soft_lutpair152" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][18]_i_1 + (.I0(\time_status_regs[11] [18]), + .I1(\time_status_regs[10] [18]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][18] )); + (* SOFT_HLUTNM = "soft_lutpair153" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][19]_i_1 + (.I0(\time_status_regs[11] [19]), + .I1(\time_status_regs[10] [19]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][19] )); + (* SOFT_HLUTNM = "soft_lutpair144" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][1]_i_1 + (.I0(\time_status_regs[11] [1]), + .I1(\time_status_regs[10] [1]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][1] )); + (* SOFT_HLUTNM = "soft_lutpair153" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][20]_i_1 + (.I0(\time_status_regs[11] [20]), + .I1(\time_status_regs[10] [20]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][20] )); + (* SOFT_HLUTNM = "soft_lutpair154" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][21]_i_1 + (.I0(\time_status_regs[11] [21]), + .I1(\time_status_regs[10] [21]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][21] )); + (* SOFT_HLUTNM = "soft_lutpair154" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][22]_i_1 + (.I0(\time_status_regs[11] [22]), + .I1(\time_status_regs[10] [22]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][22] )); + (* SOFT_HLUTNM = "soft_lutpair155" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][23]_i_1 + (.I0(\time_status_regs[11] [23]), + .I1(\time_status_regs[10] [23]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][23] )); + (* SOFT_HLUTNM = "soft_lutpair155" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][24]_i_1 + (.I0(\time_status_regs[11] [24]), + .I1(\time_status_regs[10] [24]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][24] )); + (* SOFT_HLUTNM = "soft_lutpair156" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][25]_i_1 + (.I0(\time_status_regs[11] [25]), + .I1(\time_status_regs[10] [25]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][25] )); + (* SOFT_HLUTNM = "soft_lutpair156" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][26]_i_1 + (.I0(\time_status_regs[11] [26]), + .I1(\time_status_regs[10] [26]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][26] )); + (* SOFT_HLUTNM = "soft_lutpair157" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][27]_i_1 + (.I0(\time_status_regs[11] [27]), + .I1(\time_status_regs[10] [27]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][27] )); + (* SOFT_HLUTNM = "soft_lutpair157" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][28]_i_1 + (.I0(\time_status_regs[11] [28]), + .I1(\time_status_regs[10] [28]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][28] )); + (* SOFT_HLUTNM = "soft_lutpair158" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][29]_i_1 + (.I0(\time_status_regs[11] [29]), + .I1(\time_status_regs[10] [29]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][29] )); + (* SOFT_HLUTNM = "soft_lutpair144" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][2]_i_1 + (.I0(\time_status_regs[11] [2]), + .I1(\time_status_regs[10] [2]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][2] )); + (* SOFT_HLUTNM = "soft_lutpair158" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][30]_i_1 + (.I0(\time_status_regs[11] [30]), + .I1(\time_status_regs[10] [30]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][30] )); + (* SOFT_HLUTNM = "soft_lutpair159" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][31]_i_1 + (.I0(\time_status_regs[11] [31]), + .I1(\time_status_regs[10] [31]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][31] )); + (* SOFT_HLUTNM = "soft_lutpair145" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][3]_i_1 + (.I0(\time_status_regs[11] [3]), + .I1(\time_status_regs[10] [3]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][3] )); + (* SOFT_HLUTNM = "soft_lutpair145" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][4]_i_1 + (.I0(\time_status_regs[11] [4]), + .I1(\time_status_regs[10] [4]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][4] )); + (* SOFT_HLUTNM = "soft_lutpair146" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][5]_i_1 + (.I0(\time_status_regs[11] [5]), + .I1(\time_status_regs[10] [5]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][5] )); + (* SOFT_HLUTNM = "soft_lutpair146" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][6]_i_1 + (.I0(\time_status_regs[11] [6]), + .I1(\time_status_regs[10] [6]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][6] )); + (* SOFT_HLUTNM = "soft_lutpair147" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][7]_i_1 + (.I0(\time_status_regs[11] [7]), + .I1(\time_status_regs[10] [7]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][7] )); + (* SOFT_HLUTNM = "soft_lutpair147" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][8]_i_1 + (.I0(\time_status_regs[11] [8]), + .I1(\time_status_regs[10] [8]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][8] )); + (* SOFT_HLUTNM = "soft_lutpair148" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][9]_i_1 + (.I0(\time_status_regs[11] [9]), + .I1(\time_status_regs[10] [9]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][9] )); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][0]_i_1 + (.I0(\time_status_regs[13] [0]), + .I1(\time_status_regs[12] [0]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][0] )); + (* SOFT_HLUTNM = "soft_lutpair131" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][10]_i_1 + (.I0(\time_status_regs[13] [10]), + .I1(\time_status_regs[12] [10]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][10] )); + (* SOFT_HLUTNM = "soft_lutpair132" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][11]_i_1 + (.I0(\time_status_regs[13] [11]), + .I1(\time_status_regs[12] [11]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][11] )); + (* SOFT_HLUTNM = "soft_lutpair132" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][12]_i_1 + (.I0(\time_status_regs[13] [12]), + .I1(\time_status_regs[12] [12]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][12] )); + (* SOFT_HLUTNM = "soft_lutpair133" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][13]_i_1 + (.I0(\time_status_regs[13] [13]), + .I1(\time_status_regs[12] [13]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][13] )); + (* SOFT_HLUTNM = "soft_lutpair133" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][14]_i_1 + (.I0(\time_status_regs[13] [14]), + .I1(\time_status_regs[12] [14]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][14] )); + (* SOFT_HLUTNM = "soft_lutpair134" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][15]_i_1 + (.I0(\time_status_regs[13] [15]), + .I1(\time_status_regs[12] [15]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][15] )); + (* SOFT_HLUTNM = "soft_lutpair134" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][16]_i_1 + (.I0(\time_status_regs[13] [16]), + .I1(\time_status_regs[12] [16]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][16] )); + (* SOFT_HLUTNM = "soft_lutpair135" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][17]_i_1 + (.I0(\time_status_regs[13] [17]), + .I1(\time_status_regs[12] [17]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][17] )); + (* SOFT_HLUTNM = "soft_lutpair135" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][18]_i_1 + (.I0(\time_status_regs[13] [18]), + .I1(\time_status_regs[12] [18]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][18] )); + (* SOFT_HLUTNM = "soft_lutpair136" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][19]_i_1 + (.I0(\time_status_regs[13] [19]), + .I1(\time_status_regs[12] [19]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][19] )); + (* SOFT_HLUTNM = "soft_lutpair127" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][1]_i_1 + (.I0(\time_status_regs[13] [1]), + .I1(\time_status_regs[12] [1]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][1] )); + (* SOFT_HLUTNM = "soft_lutpair136" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][20]_i_1 + (.I0(\time_status_regs[13] [20]), + .I1(\time_status_regs[12] [20]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][20] )); + (* SOFT_HLUTNM = "soft_lutpair137" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][21]_i_1 + (.I0(\time_status_regs[13] [21]), + .I1(\time_status_regs[12] [21]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][21] )); + (* SOFT_HLUTNM = "soft_lutpair137" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][22]_i_1 + (.I0(\time_status_regs[13] [22]), + .I1(\time_status_regs[12] [22]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][22] )); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][23]_i_1 + (.I0(\time_status_regs[13] [23]), + .I1(\time_status_regs[12] [23]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][23] )); + (* SOFT_HLUTNM = "soft_lutpair138" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][24]_i_1 + (.I0(\time_status_regs[13] [24]), + .I1(\time_status_regs[12] [24]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][24] )); + (* SOFT_HLUTNM = "soft_lutpair139" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][25]_i_1 + (.I0(\time_status_regs[13] [25]), + .I1(\time_status_regs[12] [25]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][25] )); + (* SOFT_HLUTNM = "soft_lutpair139" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][26]_i_1 + (.I0(\time_status_regs[13] [26]), + .I1(\time_status_regs[12] [26]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][26] )); + (* SOFT_HLUTNM = "soft_lutpair140" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][27]_i_1 + (.I0(\time_status_regs[13] [27]), + .I1(\time_status_regs[12] [27]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][27] )); + (* SOFT_HLUTNM = "soft_lutpair140" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][28]_i_1 + (.I0(\time_status_regs[13] [28]), + .I1(\time_status_regs[12] [28]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][28] )); + (* SOFT_HLUTNM = "soft_lutpair141" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][29]_i_1 + (.I0(\time_status_regs[13] [29]), + .I1(\time_status_regs[12] [29]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][29] )); + (* SOFT_HLUTNM = "soft_lutpair127" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][2]_i_1 + (.I0(\time_status_regs[13] [2]), + .I1(\time_status_regs[12] [2]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][2] )); + (* SOFT_HLUTNM = "soft_lutpair141" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][30]_i_1 + (.I0(\time_status_regs[13] [30]), + .I1(\time_status_regs[12] [30]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][30] )); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][31]_i_1 + (.I0(\time_status_regs[13] [31]), + .I1(\time_status_regs[12] [31]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][31] )); + (* SOFT_HLUTNM = "soft_lutpair128" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][3]_i_1 + (.I0(\time_status_regs[13] [3]), + .I1(\time_status_regs[12] [3]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][3] )); + (* SOFT_HLUTNM = "soft_lutpair128" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][4]_i_1 + (.I0(\time_status_regs[13] [4]), + .I1(\time_status_regs[12] [4]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][4] )); + (* SOFT_HLUTNM = "soft_lutpair129" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][5]_i_1 + (.I0(\time_status_regs[13] [5]), + .I1(\time_status_regs[12] [5]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][5] )); + (* SOFT_HLUTNM = "soft_lutpair129" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][6]_i_1 + (.I0(\time_status_regs[13] [6]), + .I1(\time_status_regs[12] [6]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][6] )); + (* SOFT_HLUTNM = "soft_lutpair130" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][7]_i_1 + (.I0(\time_status_regs[13] [7]), + .I1(\time_status_regs[12] [7]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][7] )); + (* SOFT_HLUTNM = "soft_lutpair130" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][8]_i_1 + (.I0(\time_status_regs[13] [8]), + .I1(\time_status_regs[12] [8]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][8] )); + (* SOFT_HLUTNM = "soft_lutpair131" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][9]_i_1 + (.I0(\time_status_regs[13] [9]), + .I1(\time_status_regs[12] [9]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][9] )); + (* SOFT_HLUTNM = "soft_lutpair111" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][0]_i_1 + (.I0(\time_status_regs[15] [0]), + .I1(\time_status_regs[14] [0]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][0] )); + (* SOFT_HLUTNM = "soft_lutpair116" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][10]_i_1 + (.I0(\time_status_regs[15] [10]), + .I1(\time_status_regs[14] [10]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][10] )); + (* SOFT_HLUTNM = "soft_lutpair117" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][11]_i_1 + (.I0(\time_status_regs[15] [11]), + .I1(\time_status_regs[14] [11]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][11] )); + (* SOFT_HLUTNM = "soft_lutpair117" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][12]_i_1 + (.I0(\time_status_regs[15] [12]), + .I1(\time_status_regs[14] [12]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][12] )); + (* SOFT_HLUTNM = "soft_lutpair118" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][13]_i_1 + (.I0(\time_status_regs[15] [13]), + .I1(\time_status_regs[14] [13]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][13] )); + (* SOFT_HLUTNM = "soft_lutpair118" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][14]_i_1 + (.I0(\time_status_regs[15] [14]), + .I1(\time_status_regs[14] [14]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][14] )); + (* SOFT_HLUTNM = "soft_lutpair119" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][15]_i_1 + (.I0(\time_status_regs[15] [15]), + .I1(\time_status_regs[14] [15]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][15] )); + (* SOFT_HLUTNM = "soft_lutpair119" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][16]_i_1 + (.I0(\time_status_regs[15] [16]), + .I1(\time_status_regs[14] [16]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][16] )); + (* SOFT_HLUTNM = "soft_lutpair120" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][17]_i_1 + (.I0(\time_status_regs[15] [17]), + .I1(\time_status_regs[14] [17]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][17] )); + (* SOFT_HLUTNM = "soft_lutpair120" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][18]_i_1 + (.I0(\time_status_regs[15] [18]), + .I1(\time_status_regs[14] [18]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][18] )); + (* SOFT_HLUTNM = "soft_lutpair121" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][19]_i_1 + (.I0(\time_status_regs[15] [19]), + .I1(\time_status_regs[14] [19]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][19] )); + (* SOFT_HLUTNM = "soft_lutpair112" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][1]_i_1 + (.I0(\time_status_regs[15] [1]), + .I1(\time_status_regs[14] [1]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][1] )); + (* SOFT_HLUTNM = "soft_lutpair121" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][20]_i_1 + (.I0(\time_status_regs[15] [20]), + .I1(\time_status_regs[14] [20]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][20] )); + (* SOFT_HLUTNM = "soft_lutpair122" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][21]_i_1 + (.I0(\time_status_regs[15] [21]), + .I1(\time_status_regs[14] [21]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][21] )); + (* SOFT_HLUTNM = "soft_lutpair122" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][22]_i_1 + (.I0(\time_status_regs[15] [22]), + .I1(\time_status_regs[14] [22]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][22] )); + (* SOFT_HLUTNM = "soft_lutpair123" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][23]_i_1 + (.I0(\time_status_regs[15] [23]), + .I1(\time_status_regs[14] [23]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][23] )); + (* SOFT_HLUTNM = "soft_lutpair123" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][24]_i_1 + (.I0(\time_status_regs[15] [24]), + .I1(\time_status_regs[14] [24]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][24] )); + (* SOFT_HLUTNM = "soft_lutpair124" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][25]_i_1 + (.I0(\time_status_regs[15] [25]), + .I1(\time_status_regs[14] [25]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][25] )); + (* SOFT_HLUTNM = "soft_lutpair124" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][26]_i_1 + (.I0(\time_status_regs[15] [26]), + .I1(\time_status_regs[14] [26]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][26] )); + (* SOFT_HLUTNM = "soft_lutpair125" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][27]_i_1 + (.I0(\time_status_regs[15] [27]), + .I1(\time_status_regs[14] [27]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][27] )); + (* SOFT_HLUTNM = "soft_lutpair125" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][28]_i_1 + (.I0(\time_status_regs[15] [28]), + .I1(\time_status_regs[14] [28]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][28] )); + (* SOFT_HLUTNM = "soft_lutpair126" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][29]_i_1 + (.I0(\time_status_regs[15] [29]), + .I1(\time_status_regs[14] [29]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][29] )); + (* SOFT_HLUTNM = "soft_lutpair112" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][2]_i_1 + (.I0(\time_status_regs[15] [2]), + .I1(\time_status_regs[14] [2]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][2] )); + (* SOFT_HLUTNM = "soft_lutpair126" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][30]_i_1 + (.I0(\time_status_regs[15] [30]), + .I1(\time_status_regs[14] [30]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][30] )); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_1 + (.I0(\time_status_regs[15] [31]), + .I1(\time_status_regs[14] [31]), + .I2(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][31] )); + (* IS_FANOUT_CONSTRAINED = "1" *) + LUT1 #( + .INIT(2'h2)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2 + (.I0(\data_sync[2]_2 [34]), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair113" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][3]_i_1 + (.I0(\time_status_regs[15] [3]), + .I1(\time_status_regs[14] [3]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][3] )); + (* SOFT_HLUTNM = "soft_lutpair113" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][4]_i_1 + (.I0(\time_status_regs[15] [4]), + .I1(\time_status_regs[14] [4]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][4] )); + (* SOFT_HLUTNM = "soft_lutpair114" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][5]_i_1 + (.I0(\time_status_regs[15] [5]), + .I1(\time_status_regs[14] [5]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][5] )); + (* SOFT_HLUTNM = "soft_lutpair114" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][6]_i_1 + (.I0(\time_status_regs[15] [6]), + .I1(\time_status_regs[14] [6]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][6] )); + (* SOFT_HLUTNM = "soft_lutpair115" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][7]_i_1 + (.I0(\time_status_regs[15] [7]), + .I1(\time_status_regs[14] [7]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][7] )); + (* SOFT_HLUTNM = "soft_lutpair115" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][8]_i_1 + (.I0(\time_status_regs[15] [8]), + .I1(\time_status_regs[14] [8]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][8] )); + (* SOFT_HLUTNM = "soft_lutpair116" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][9]_i_1 + (.I0(\time_status_regs[15] [9]), + .I1(\time_status_regs[14] [9]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][9] )); + (* SOFT_HLUTNM = "soft_lutpair95" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][0]_i_1 + (.I0(\time_status_regs[17] [0]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] [0]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][0] )); + (* SOFT_HLUTNM = "soft_lutpair100" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][10]_i_1 + (.I0(\time_status_regs[17] [10]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] [10]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][10] )); + (* SOFT_HLUTNM = "soft_lutpair101" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][11]_i_1 + (.I0(\time_status_regs[17] [11]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] [11]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][11] )); + (* SOFT_HLUTNM = "soft_lutpair101" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][12]_i_1 + (.I0(\time_status_regs[17] [12]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] [12]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][12] )); + (* SOFT_HLUTNM = "soft_lutpair102" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][13]_i_1 + (.I0(\time_status_regs[17] [13]), + .I1(\time_status_regs[16] [0]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][13] )); + (* SOFT_HLUTNM = "soft_lutpair102" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][14]_i_1 + (.I0(\time_status_regs[17] [14]), + .I1(\time_status_regs[16] [1]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][14] )); + (* SOFT_HLUTNM = "soft_lutpair103" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][15]_i_1 + (.I0(\time_status_regs[17] [15]), + .I1(\time_status_regs[16] [2]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][15] )); + (* SOFT_HLUTNM = "soft_lutpair103" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][16]_i_1 + (.I0(\time_status_regs[17] [16]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] [13]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][16] )); + (* SOFT_HLUTNM = "soft_lutpair104" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][17]_i_1 + (.I0(\time_status_regs[17] [17]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] [14]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][17] )); + (* SOFT_HLUTNM = "soft_lutpair104" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][18]_i_1 + (.I0(\time_status_regs[17] [18]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] [15]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][18] )); + (* SOFT_HLUTNM = "soft_lutpair105" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][19]_i_1 + (.I0(\time_status_regs[17] [19]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] [16]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][19] )); + (* SOFT_HLUTNM = "soft_lutpair96" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][1]_i_1 + (.I0(\time_status_regs[17] [1]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] [1]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][1] )); + (* SOFT_HLUTNM = "soft_lutpair105" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][20]_i_1 + (.I0(\time_status_regs[17] [20]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] [17]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][20] )); + (* SOFT_HLUTNM = "soft_lutpair106" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][21]_i_1 + (.I0(\time_status_regs[17] [21]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] [18]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][21] )); + (* SOFT_HLUTNM = "soft_lutpair106" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][22]_i_1 + (.I0(\time_status_regs[17] [22]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] [19]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][22] )); + (* SOFT_HLUTNM = "soft_lutpair107" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][23]_i_1 + (.I0(\time_status_regs[17] [23]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] [20]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][23] )); + (* SOFT_HLUTNM = "soft_lutpair107" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][24]_i_1 + (.I0(\time_status_regs[17] [24]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] [21]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][24] )); + (* SOFT_HLUTNM = "soft_lutpair108" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][25]_i_1 + (.I0(\time_status_regs[17] [25]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] [22]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][25] )); + (* SOFT_HLUTNM = "soft_lutpair108" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][26]_i_1 + (.I0(\time_status_regs[17] [26]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] [23]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][26] )); + (* SOFT_HLUTNM = "soft_lutpair109" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][27]_i_1 + (.I0(\time_status_regs[17] [27]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] [24]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][27] )); + (* SOFT_HLUTNM = "soft_lutpair109" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][28]_i_1 + (.I0(\time_status_regs[17] [28]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] [25]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][28] )); + (* SOFT_HLUTNM = "soft_lutpair110" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][29]_i_1 + (.I0(\time_status_regs[17] [29]), + .I1(\time_status_regs[16] [3]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][29] )); + (* SOFT_HLUTNM = "soft_lutpair96" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][2]_i_1 + (.I0(\time_status_regs[17] [2]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] [2]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][2] )); + (* SOFT_HLUTNM = "soft_lutpair110" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][30]_i_1 + (.I0(\time_status_regs[17] [30]), + .I1(\time_status_regs[16] [4]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][30] )); + (* SOFT_HLUTNM = "soft_lutpair111" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][31]_i_1 + (.I0(\time_status_regs[17] [31]), + .I1(\time_status_regs[16] [5]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][31] )); + (* SOFT_HLUTNM = "soft_lutpair97" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][3]_i_1 + (.I0(\time_status_regs[17] [3]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] [3]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][3] )); + (* SOFT_HLUTNM = "soft_lutpair97" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][4]_i_1 + (.I0(\time_status_regs[17] [4]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] [4]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][4] )); + (* SOFT_HLUTNM = "soft_lutpair98" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][5]_i_1 + (.I0(\time_status_regs[17] [5]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] [5]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][5] )); + (* SOFT_HLUTNM = "soft_lutpair98" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][6]_i_1 + (.I0(\time_status_regs[17] [6]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] [6]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][6] )); + (* SOFT_HLUTNM = "soft_lutpair99" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][7]_i_1 + (.I0(\time_status_regs[17] [7]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] [7]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][7] )); + (* SOFT_HLUTNM = "soft_lutpair99" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][8]_i_1 + (.I0(\time_status_regs[17] [8]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] [8]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][8] )); + (* SOFT_HLUTNM = "soft_lutpair100" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][9]_i_1 + (.I0(\time_status_regs[17] [9]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] [9]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][9] )); + (* SOFT_HLUTNM = "soft_lutpair79" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][0]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6] [0]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9] [0]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][0] )); + (* SOFT_HLUTNM = "soft_lutpair84" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][10]_i_1 + (.I0(\time_status_regs[19] [3]), + .I1(\time_status_regs[18] [2]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][10] )); + (* SOFT_HLUTNM = "soft_lutpair85" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][11]_i_1 + (.I0(\time_status_regs[19] [4]), + .I1(\time_status_regs[18] [3]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][11] )); + (* SOFT_HLUTNM = "soft_lutpair85" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][12]_i_1 + (.I0(\time_status_regs[19] [5]), + .I1(\time_status_regs[18] [4]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][12] )); + (* SOFT_HLUTNM = "soft_lutpair86" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][13]_i_1 + (.I0(\time_status_regs[19] [6]), + .I1(\time_status_regs[18] [5]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][13] )); + (* SOFT_HLUTNM = "soft_lutpair86" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][14]_i_1 + (.I0(\time_status_regs[19] [7]), + .I1(\time_status_regs[18] [6]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][14] )); + (* SOFT_HLUTNM = "soft_lutpair87" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][15]_i_1 + (.I0(\time_status_regs[19] [8]), + .I1(\time_status_regs[18] [7]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][15] )); + (* SOFT_HLUTNM = "soft_lutpair87" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][16]_i_1 + (.I0(\time_status_regs[19] [9]), + .I1(\time_status_regs[18] [8]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][16] )); + (* SOFT_HLUTNM = "soft_lutpair88" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][17]_i_1 + (.I0(\time_status_regs[19] [10]), + .I1(\time_status_regs[18] [9]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][17] )); + (* SOFT_HLUTNM = "soft_lutpair88" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][18]_i_1 + (.I0(\time_status_regs[19] [11]), + .I1(\time_status_regs[18] [10]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][18] )); + (* SOFT_HLUTNM = "soft_lutpair89" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][19]_i_1 + (.I0(\time_status_regs[19] [12]), + .I1(\time_status_regs[18] [11]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][19] )); + (* SOFT_HLUTNM = "soft_lutpair80" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][1]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6] [1]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9] [1]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][1] )); + (* SOFT_HLUTNM = "soft_lutpair89" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][20]_i_1 + (.I0(\time_status_regs[19] [13]), + .I1(\time_status_regs[18] [12]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][20] )); + (* SOFT_HLUTNM = "soft_lutpair90" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][21]_i_1 + (.I0(\time_status_regs[19] [14]), + .I1(\time_status_regs[18] [13]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][21] )); + (* SOFT_HLUTNM = "soft_lutpair90" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][22]_i_1 + (.I0(\time_status_regs[19] [15]), + .I1(\time_status_regs[18] [14]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][22] )); + (* SOFT_HLUTNM = "soft_lutpair91" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][23]_i_1 + (.I0(\time_status_regs[19] [16]), + .I1(\time_status_regs[18] [15]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][23] )); + (* SOFT_HLUTNM = "soft_lutpair91" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][24]_i_1 + (.I0(\time_status_regs[19] [17]), + .I1(\time_status_regs[18] [16]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][24] )); + (* SOFT_HLUTNM = "soft_lutpair92" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][25]_i_1 + (.I0(\time_status_regs[19] [18]), + .I1(\time_status_regs[18] [17]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][25] )); + (* SOFT_HLUTNM = "soft_lutpair92" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][26]_i_1 + (.I0(\time_status_regs[19] [19]), + .I1(\time_status_regs[18] [18]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][26] )); + (* SOFT_HLUTNM = "soft_lutpair93" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][27]_i_1 + (.I0(\time_status_regs[19] [20]), + .I1(\time_status_regs[18] [19]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][27] )); + (* SOFT_HLUTNM = "soft_lutpair93" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][28]_i_1 + (.I0(\time_status_regs[19] [21]), + .I1(\time_status_regs[18] [20]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][28] )); + (* SOFT_HLUTNM = "soft_lutpair94" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][29]_i_1 + (.I0(\time_status_regs[19] [22]), + .I1(\time_status_regs[18] [21]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][29] )); + (* SOFT_HLUTNM = "soft_lutpair80" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][2]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6] [2]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9] [2]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][2] )); + (* SOFT_HLUTNM = "soft_lutpair94" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][30]_i_1 + (.I0(\time_status_regs[19] [23]), + .I1(\time_status_regs[18] [22]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][30] )); + (* SOFT_HLUTNM = "soft_lutpair95" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][31]_i_1 + (.I0(\time_status_regs[19] [24]), + .I1(\time_status_regs[18] [23]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][31] )); + (* SOFT_HLUTNM = "soft_lutpair81" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][3]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6] [3]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9] [3]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][3] )); + (* SOFT_HLUTNM = "soft_lutpair81" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][4]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6] [4]), + .I1(\time_status_regs[18] [0]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][4] )); + (* SOFT_HLUTNM = "soft_lutpair82" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][5]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6] [5]), + .I1(\time_status_regs[18] [1]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][5] )); + (* SOFT_HLUTNM = "soft_lutpair82" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][6]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6] [6]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9] [4]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][6] )); + (* SOFT_HLUTNM = "soft_lutpair83" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][7]_i_1 + (.I0(\time_status_regs[19] [0]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9] [5]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][7] )); + (* SOFT_HLUTNM = "soft_lutpair83" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][8]_i_1 + (.I0(\time_status_regs[19] [1]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9] [6]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][8] )); + (* SOFT_HLUTNM = "soft_lutpair84" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][9]_i_1 + (.I0(\time_status_regs[19] [2]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9] [7]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][9] )); + (* SOFT_HLUTNM = "soft_lutpair63" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][0]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] [0]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] [0]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][0] )); + (* SOFT_HLUTNM = "soft_lutpair68" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][10]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] [10]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] [10]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][10] )); + (* SOFT_HLUTNM = "soft_lutpair69" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][11]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] [11]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] [11]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][11] )); + (* SOFT_HLUTNM = "soft_lutpair69" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][12]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] [12]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] [12]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][12] )); + (* SOFT_HLUTNM = "soft_lutpair70" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][13]_i_1 + (.I0(\time_status_regs[21] [0]), + .I1(\time_status_regs[20] [0]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][13] )); + (* SOFT_HLUTNM = "soft_lutpair70" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][14]_i_1 + (.I0(\time_status_regs[21] [1]), + .I1(\time_status_regs[20] [1]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][14] )); + (* SOFT_HLUTNM = "soft_lutpair71" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][15]_i_1 + (.I0(\time_status_regs[21] [2]), + .I1(\time_status_regs[20] [2]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][15] )); + (* SOFT_HLUTNM = "soft_lutpair71" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][16]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] [13]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] [13]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][16] )); + (* SOFT_HLUTNM = "soft_lutpair72" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][17]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] [14]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] [14]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][17] )); + (* SOFT_HLUTNM = "soft_lutpair72" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][18]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] [15]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] [15]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][18] )); + (* SOFT_HLUTNM = "soft_lutpair73" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][19]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] [16]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] [16]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][19] )); + (* SOFT_HLUTNM = "soft_lutpair64" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][1]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] [1]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] [1]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][1] )); + (* SOFT_HLUTNM = "soft_lutpair73" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][20]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] [17]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] [17]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][20] )); + (* SOFT_HLUTNM = "soft_lutpair74" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][21]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] [18]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] [18]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][21] )); + (* SOFT_HLUTNM = "soft_lutpair74" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][22]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] [19]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] [19]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][22] )); + (* SOFT_HLUTNM = "soft_lutpair75" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][23]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] [20]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] [20]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][23] )); + (* SOFT_HLUTNM = "soft_lutpair75" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][24]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] [21]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] [21]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][24] )); + (* SOFT_HLUTNM = "soft_lutpair76" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][25]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] [22]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] [22]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][25] )); + (* SOFT_HLUTNM = "soft_lutpair76" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][26]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] [23]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] [23]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][26] )); + (* SOFT_HLUTNM = "soft_lutpair77" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][27]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] [24]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] [24]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][27] )); + (* SOFT_HLUTNM = "soft_lutpair77" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][28]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] [25]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] [25]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][28] )); + (* SOFT_HLUTNM = "soft_lutpair78" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][29]_i_1 + (.I0(\time_status_regs[21] [3]), + .I1(\time_status_regs[20] [3]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][29] )); + (* SOFT_HLUTNM = "soft_lutpair64" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][2]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] [2]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] [2]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][2] )); + (* SOFT_HLUTNM = "soft_lutpair78" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][30]_i_1 + (.I0(\time_status_regs[21] [4]), + .I1(\time_status_regs[20] [4]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][30] )); + (* SOFT_HLUTNM = "soft_lutpair79" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_1 + (.I0(\time_status_regs[21] [5]), + .I1(\time_status_regs[20] [5]), + .I2(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][31] )); + (* IS_FANOUT_CONSTRAINED = "1" *) + LUT1 #( + .INIT(2'h2)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2 + (.I0(\data_sync[2]_2 [34]), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair65" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][3]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] [3]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] [3]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][3] )); + (* SOFT_HLUTNM = "soft_lutpair65" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][4]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] [4]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] [4]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][4] )); + (* SOFT_HLUTNM = "soft_lutpair66" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][5]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] [5]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] [5]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][5] )); + (* SOFT_HLUTNM = "soft_lutpair66" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][6]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] [6]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] [6]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][6] )); + (* SOFT_HLUTNM = "soft_lutpair67" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][7]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] [7]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] [7]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][7] )); + (* SOFT_HLUTNM = "soft_lutpair67" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][8]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] [8]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] [8]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][8] )); + (* SOFT_HLUTNM = "soft_lutpair68" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][9]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] [9]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] [9]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][9] )); + (* SOFT_HLUTNM = "soft_lutpair47" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][0]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] [0]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] [0]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][0] )); + (* SOFT_HLUTNM = "soft_lutpair52" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][10]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] [10]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] [10]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][10] )); + (* SOFT_HLUTNM = "soft_lutpair53" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][11]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] [11]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] [11]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][11] )); + (* SOFT_HLUTNM = "soft_lutpair53" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][12]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] [12]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] [12]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][12] )); + (* SOFT_HLUTNM = "soft_lutpair54" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][13]_i_1 + (.I0(\time_status_regs[23] [0]), + .I1(\time_status_regs[22] [0]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][13] )); + (* SOFT_HLUTNM = "soft_lutpair54" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][14]_i_1 + (.I0(\time_status_regs[23] [1]), + .I1(\time_status_regs[22] [1]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][14] )); + (* SOFT_HLUTNM = "soft_lutpair55" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][15]_i_1 + (.I0(\time_status_regs[23] [2]), + .I1(\time_status_regs[22] [2]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][15] )); + (* SOFT_HLUTNM = "soft_lutpair55" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][16]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] [13]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] [13]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][16] )); + (* SOFT_HLUTNM = "soft_lutpair56" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][17]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] [14]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] [14]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][17] )); + (* SOFT_HLUTNM = "soft_lutpair56" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][18]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] [15]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] [15]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][18] )); + (* SOFT_HLUTNM = "soft_lutpair57" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][19]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] [16]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] [16]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][19] )); + (* SOFT_HLUTNM = "soft_lutpair48" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][1]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] [1]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] [1]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][1] )); + (* SOFT_HLUTNM = "soft_lutpair57" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][20]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] [17]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] [17]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][20] )); + (* SOFT_HLUTNM = "soft_lutpair58" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][21]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] [18]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] [18]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][21] )); + (* SOFT_HLUTNM = "soft_lutpair58" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][22]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] [19]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] [19]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][22] )); + (* SOFT_HLUTNM = "soft_lutpair59" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][23]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] [20]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] [20]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][23] )); + (* SOFT_HLUTNM = "soft_lutpair59" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][24]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] [21]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] [21]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][24] )); + (* SOFT_HLUTNM = "soft_lutpair60" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][25]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] [22]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] [22]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][25] )); + (* SOFT_HLUTNM = "soft_lutpair60" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][26]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] [23]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] [23]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][26] )); + (* SOFT_HLUTNM = "soft_lutpair61" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][27]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] [24]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] [24]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][27] )); + (* SOFT_HLUTNM = "soft_lutpair61" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][28]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] [25]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] [25]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][28] )); + (* SOFT_HLUTNM = "soft_lutpair62" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][29]_i_1 + (.I0(\time_status_regs[23] [3]), + .I1(\time_status_regs[22] [3]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][29] )); + (* SOFT_HLUTNM = "soft_lutpair48" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][2]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] [2]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] [2]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][2] )); + (* SOFT_HLUTNM = "soft_lutpair62" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][30]_i_1 + (.I0(\time_status_regs[23] [4]), + .I1(\time_status_regs[22] [4]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][30] )); + (* SOFT_HLUTNM = "soft_lutpair63" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][31]_i_1 + (.I0(\time_status_regs[23] [5]), + .I1(\time_status_regs[22] [5]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][31] )); + (* SOFT_HLUTNM = "soft_lutpair49" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][3]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] [3]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] [3]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][3] )); + (* SOFT_HLUTNM = "soft_lutpair49" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][4]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] [4]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] [4]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][4] )); + (* SOFT_HLUTNM = "soft_lutpair50" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][5]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] [5]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] [5]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][5] )); + (* SOFT_HLUTNM = "soft_lutpair50" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][6]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] [6]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] [6]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][6] )); + (* SOFT_HLUTNM = "soft_lutpair51" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][7]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] [7]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] [7]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][7] )); + (* SOFT_HLUTNM = "soft_lutpair51" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][8]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] [8]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] [8]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][8] )); + (* SOFT_HLUTNM = "soft_lutpair52" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][9]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] [9]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] [9]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][9] )); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][0]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] [0]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] [0]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][0] )); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][10]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] [10]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] [10]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][10] )); + (* SOFT_HLUTNM = "soft_lutpair37" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][11]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] [11]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] [11]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][11] )); + (* SOFT_HLUTNM = "soft_lutpair37" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][12]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] [12]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] [12]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][12] )); + (* SOFT_HLUTNM = "soft_lutpair38" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][13]_i_1 + (.I0(\time_status_regs[25] [0]), + .I1(\time_status_regs[24] [0]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][13] )); + (* SOFT_HLUTNM = "soft_lutpair38" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][14]_i_1 + (.I0(\time_status_regs[25] [1]), + .I1(\time_status_regs[24] [1]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][14] )); + (* SOFT_HLUTNM = "soft_lutpair39" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][15]_i_1 + (.I0(\time_status_regs[25] [2]), + .I1(\time_status_regs[24] [2]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][15] )); + (* SOFT_HLUTNM = "soft_lutpair39" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][16]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] [13]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] [13]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][16] )); + (* SOFT_HLUTNM = "soft_lutpair40" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][17]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] [14]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] [14]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][17] )); + (* SOFT_HLUTNM = "soft_lutpair40" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][18]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] [15]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] [15]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][18] )); + (* SOFT_HLUTNM = "soft_lutpair41" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][19]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] [16]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] [16]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][19] )); + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][1]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] [1]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] [1]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][1] )); + (* SOFT_HLUTNM = "soft_lutpair41" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][20]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] [17]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] [17]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][20] )); + (* SOFT_HLUTNM = "soft_lutpair42" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][21]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] [18]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] [18]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][21] )); + (* SOFT_HLUTNM = "soft_lutpair42" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][22]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] [19]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] [19]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][22] )); + (* SOFT_HLUTNM = "soft_lutpair43" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][23]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] [20]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] [20]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][23] )); + (* SOFT_HLUTNM = "soft_lutpair43" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][24]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] [21]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] [21]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][24] )); + (* SOFT_HLUTNM = "soft_lutpair44" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][25]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] [22]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] [22]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][25] )); + (* SOFT_HLUTNM = "soft_lutpair44" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][26]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] [23]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] [23]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][26] )); + (* SOFT_HLUTNM = "soft_lutpair45" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][27]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] [24]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] [24]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][27] )); + (* SOFT_HLUTNM = "soft_lutpair45" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][28]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] [25]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] [25]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][28] )); + (* SOFT_HLUTNM = "soft_lutpair46" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][29]_i_1 + (.I0(\time_status_regs[25] [3]), + .I1(\time_status_regs[24] [3]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][29] )); + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][2]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] [2]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] [2]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][2] )); + (* SOFT_HLUTNM = "soft_lutpair46" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][30]_i_1 + (.I0(\time_status_regs[25] [4]), + .I1(\time_status_regs[24] [4]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][30] )); + (* SOFT_HLUTNM = "soft_lutpair47" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][31]_i_1 + (.I0(\time_status_regs[25] [5]), + .I1(\time_status_regs[24] [5]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][31] )); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][3]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] [3]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] [3]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][3] )); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][4]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] [4]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] [4]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][4] )); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][5]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] [5]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] [5]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][5] )); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][6]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] [6]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] [6]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][6] )); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][7]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] [7]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] [7]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][7] )); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][8]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] [8]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] [8]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][8] )); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][9]_i_1 + (.I0(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] [9]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] [9]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][9] )); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][0]_i_1 + (.I0(Q[0]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] [0]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][0] )); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][10]_i_1 + (.I0(Q[10]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] [10]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][10] )); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][11]_i_1 + (.I0(Q[11]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] [11]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][11] )); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][12]_i_1 + (.I0(Q[12]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] [12]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][12] )); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][13]_i_1 + (.I0(\time_status_regs[27] [0]), + .I1(\time_status_regs[26] [0]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][13] )); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][14]_i_1 + (.I0(\time_status_regs[27] [1]), + .I1(\time_status_regs[26] [1]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][14] )); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][15]_i_1 + (.I0(\time_status_regs[27] [2]), + .I1(\time_status_regs[26] [2]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][15] )); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][16]_i_1 + (.I0(Q[13]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] [13]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][16] )); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][17]_i_1 + (.I0(Q[14]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] [14]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][17] )); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][18]_i_1 + (.I0(Q[15]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] [15]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][18] )); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][19]_i_1 + (.I0(Q[16]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] [16]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][19] )); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][1]_i_1 + (.I0(Q[1]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] [1]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][1] )); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][20]_i_1 + (.I0(Q[17]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] [17]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][20] )); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][21]_i_1 + (.I0(Q[18]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] [18]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][21] )); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][22]_i_1 + (.I0(Q[19]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] [19]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][22] )); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][23]_i_1 + (.I0(Q[20]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] [20]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][23] )); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][24]_i_1 + (.I0(Q[21]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] [21]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][24] )); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][25]_i_1 + (.I0(Q[22]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] [22]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][25] )); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][26]_i_1 + (.I0(Q[23]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] [23]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][26] )); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][27]_i_1 + (.I0(Q[24]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] [24]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][27] )); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][28]_i_1 + (.I0(Q[25]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] [25]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][28] )); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][29]_i_1 + (.I0(\time_status_regs[27] [3]), + .I1(\time_status_regs[26] [3]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][29] )); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][2]_i_1 + (.I0(Q[2]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] [2]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][2] )); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][30]_i_1 + (.I0(\time_status_regs[27] [4]), + .I1(\time_status_regs[26] [4]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][30] )); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_1 + (.I0(\time_status_regs[27] [5]), + .I1(\time_status_regs[26] [5]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][31] )); + (* IS_FANOUT_CONSTRAINED = "1" *) + LUT1 #( + .INIT(2'h2)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2 + (.I0(\data_sync[2]_2 [34]), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][3]_i_1 + (.I0(Q[3]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] [3]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][3] )); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][4]_i_1 + (.I0(Q[4]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] [4]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][4] )); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][5]_i_1 + (.I0(Q[5]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] [5]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][5] )); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][6]_i_1 + (.I0(Q[6]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] [6]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][6] )); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][7]_i_1 + (.I0(Q[7]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] [7]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][7] )); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][8]_i_1 + (.I0(Q[8]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] [8]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][8] )); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT3 #( + .INIT(8'hAC)) + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][9]_i_1 + (.I0(Q[9]), + .I1(\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] [9]), + .I2(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0 ), + .O(\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][9] )); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][0] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [0]), + .Q(\data_sync[0]_0 [0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][10] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [10]), + .Q(\data_sync[0]_0 [10]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][11] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [11]), + .Q(\data_sync[0]_0 [11]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][12] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [12]), + .Q(\data_sync[0]_0 [12]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][13] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [13]), + .Q(\data_sync[0]_0 [13]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][14] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [14]), + .Q(\data_sync[0]_0 [14]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][15] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [15]), + .Q(\data_sync[0]_0 [15]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][16] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [16]), + .Q(\data_sync[0]_0 [16]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][17] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [17]), + .Q(\data_sync[0]_0 [17]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][18] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [18]), + .Q(\data_sync[0]_0 [18]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][19] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [19]), + .Q(\data_sync[0]_0 [19]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][1] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [1]), + .Q(\data_sync[0]_0 [1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][20] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [20]), + .Q(\data_sync[0]_0 [20]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][21] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [21]), + .Q(\data_sync[0]_0 [21]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][22] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [22]), + .Q(\data_sync[0]_0 [22]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][23] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [23]), + .Q(\data_sync[0]_0 [23]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][24] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [24]), + .Q(\data_sync[0]_0 [24]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][25] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [25]), + .Q(\data_sync[0]_0 [25]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][26] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [26]), + .Q(\data_sync[0]_0 [26]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][27] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [27]), + .Q(\data_sync[0]_0 [27]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][28] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [28]), + .Q(\data_sync[0]_0 [28]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][29] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [29]), + .Q(\data_sync[0]_0 [29]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][2] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [2]), + .Q(\data_sync[0]_0 [2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][30] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [30]), + .Q(\data_sync[0]_0 [30]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][31] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [31]), + .Q(\data_sync[0]_0 [31]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][32] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [32]), + .Q(\data_sync[0]_0 [32]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][33] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [33]), + .Q(\data_sync[0]_0 [33]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][34] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [34]), + .Q(\data_sync[0]_0 [34]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][35] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [35]), + .Q(\data_sync[0]_0 [35]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][36] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [36]), + .Q(\data_sync[0]_0 [36]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][37] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [37]), + .Q(\data_sync[0]_0 [37]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][38] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [38]), + .Q(\data_sync[0]_0 [38]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][39] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [39]), + .Q(\data_sync[0]_0 [39]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][3] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [3]), + .Q(\data_sync[0]_0 [3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][40] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [40]), + .Q(\data_sync[0]_0 [40]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][41] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [41]), + .Q(\data_sync[0]_0 [41]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][42] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [42]), + .Q(\data_sync[0]_0 [42]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][43] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [43]), + .Q(\data_sync[0]_0 [43]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][44] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [44]), + .Q(\data_sync[0]_0 [44]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][4] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [4]), + .Q(\data_sync[0]_0 [4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][5] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [5]), + .Q(\data_sync[0]_0 [5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][6] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [6]), + .Q(\data_sync[0]_0 [6]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][7] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [7]), + .Q(\data_sync[0]_0 [7]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][8] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [8]), + .Q(\data_sync[0]_0 [8]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][9] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.proc_sync1_reg[44] [9]), + .Q(\data_sync[0]_0 [9]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][0] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [0]), + .Q(\data_sync[1]_1 [0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][10] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [10]), + .Q(\data_sync[1]_1 [10]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][11] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [11]), + .Q(\data_sync[1]_1 [11]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][12] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [12]), + .Q(\data_sync[1]_1 [12]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][13] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [13]), + .Q(\data_sync[1]_1 [13]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][14] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [14]), + .Q(\data_sync[1]_1 [14]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][15] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [15]), + .Q(\data_sync[1]_1 [15]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][16] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [16]), + .Q(\data_sync[1]_1 [16]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][17] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [17]), + .Q(\data_sync[1]_1 [17]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][18] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [18]), + .Q(\data_sync[1]_1 [18]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][19] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [19]), + .Q(\data_sync[1]_1 [19]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][1] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [1]), + .Q(\data_sync[1]_1 [1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][20] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [20]), + .Q(\data_sync[1]_1 [20]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][21] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [21]), + .Q(\data_sync[1]_1 [21]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][22] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [22]), + .Q(\data_sync[1]_1 [22]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][23] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [23]), + .Q(\data_sync[1]_1 [23]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][24] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [24]), + .Q(\data_sync[1]_1 [24]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][25] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [25]), + .Q(\data_sync[1]_1 [25]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][26] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [26]), + .Q(\data_sync[1]_1 [26]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][27] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [27]), + .Q(\data_sync[1]_1 [27]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][28] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [28]), + .Q(\data_sync[1]_1 [28]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][29] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [29]), + .Q(\data_sync[1]_1 [29]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][2] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [2]), + .Q(\data_sync[1]_1 [2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][30] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [30]), + .Q(\data_sync[1]_1 [30]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][31] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [31]), + .Q(\data_sync[1]_1 [31]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][32] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [32]), + .Q(\data_sync[1]_1 [32]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][33] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [33]), + .Q(\data_sync[1]_1 [33]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][34] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [34]), + .Q(\data_sync[1]_1 [34]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][35] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [35]), + .Q(\data_sync[1]_1 [35]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][36] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [36]), + .Q(\data_sync[1]_1 [36]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][37] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [37]), + .Q(\data_sync[1]_1 [37]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][38] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [38]), + .Q(\data_sync[1]_1 [38]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][39] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [39]), + .Q(\data_sync[1]_1 [39]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][3] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [3]), + .Q(\data_sync[1]_1 [3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][40] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [40]), + .Q(\data_sync[1]_1 [40]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][41] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [41]), + .Q(\data_sync[1]_1 [41]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][42] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [42]), + .Q(\data_sync[1]_1 [42]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][43] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [43]), + .Q(\data_sync[1]_1 [43]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][44] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [44]), + .Q(\data_sync[1]_1 [44]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][4] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [4]), + .Q(\data_sync[1]_1 [4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][5] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [5]), + .Q(\data_sync[1]_1 [5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][6] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [6]), + .Q(\data_sync[1]_1 [6]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][7] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [7]), + .Q(\data_sync[1]_1 [7]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][8] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [8]), + .Q(\data_sync[1]_1 [8]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][9] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [9]), + .Q(\data_sync[1]_1 [9]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][0] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [0]), + .Q(\data_sync[2]_2 [0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][10] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [10]), + .Q(\data_sync[2]_2 [10]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][11] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [11]), + .Q(\data_sync[2]_2 [11]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][12] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [12]), + .Q(\data_sync[2]_2 [12]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][13] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [13]), + .Q(\data_sync[2]_2 [13]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][14] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [14]), + .Q(\data_sync[2]_2 [14]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][15] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [15]), + .Q(\data_sync[2]_2 [15]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][16] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [16]), + .Q(\data_sync[2]_2 [16]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][17] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [17]), + .Q(\data_sync[2]_2 [17]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][18] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [18]), + .Q(\data_sync[2]_2 [18]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][19] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [19]), + .Q(\data_sync[2]_2 [19]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][1] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [1]), + .Q(\data_sync[2]_2 [1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][20] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [20]), + .Q(\data_sync[2]_2 [20]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][21] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [21]), + .Q(\data_sync[2]_2 [21]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][22] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [22]), + .Q(\data_sync[2]_2 [22]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][23] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [23]), + .Q(\data_sync[2]_2 [23]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][24] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [24]), + .Q(\data_sync[2]_2 [24]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][25] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [25]), + .Q(\data_sync[2]_2 [25]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][26] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [26]), + .Q(\data_sync[2]_2 [26]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][27] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [27]), + .Q(\data_sync[2]_2 [27]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][28] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [28]), + .Q(\data_sync[2]_2 [28]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][29] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [29]), + .Q(\data_sync[2]_2 [29]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][2] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [2]), + .Q(\data_sync[2]_2 [2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][30] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [30]), + .Q(\data_sync[2]_2 [30]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][31] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [31]), + .Q(\data_sync[2]_2 [31]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][32] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [32]), + .Q(\data_sync[2]_2 [32]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][33] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [33]), + .Q(\data_sync[2]_2 [33]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][34] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [34]), + .Q(\data_sync[2]_2 [34]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][35] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [35]), + .Q(\data_sync[2]_2 [35]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][36] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [36]), + .Q(\data_sync[2]_2 [36]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][37] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [37]), + .Q(\data_sync[2]_2 [37]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][38] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [38]), + .Q(\data_sync[2]_2 [38]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][39] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [39]), + .Q(\data_sync[2]_2 [39]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][3] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [3]), + .Q(\data_sync[2]_2 [3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][40] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [40]), + .Q(\data_sync[2]_2 [40]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][41] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [41]), + .Q(\data_sync[2]_2 [41]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][42] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [42]), + .Q(\data_sync[2]_2 [42]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][43] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [43]), + .Q(\data_sync[2]_2 [43]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][44] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [44]), + .Q(\data_sync[2]_2 [44]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][4] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [4]), + .Q(\data_sync[2]_2 [4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][5] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [5]), + .Q(\data_sync[2]_2 [5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][6] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [6]), + .Q(\data_sync[2]_2 [6]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][7] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [7]), + .Q(\data_sync[2]_2 [7]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][8] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [8]), + .Q(\data_sync[2]_2 [8]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][9] + (.C(vid_aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [9]), + .Q(\data_sync[2]_2 [9]), + .R(1'b0)); + LUT1 #( + .INIT(2'h2)) + ipif_Addr_inferred__0_i_1 + (.I0(\data_sync[2]_2 [40]), + .O(ipif_Addr[8])); + LUT1 #( + .INIT(2'h2)) + ipif_Addr_inferred__0_i_2 + (.I0(\data_sync[2]_2 [39]), + .O(ipif_Addr[7])); + LUT1 #( + .INIT(2'h2)) + ipif_Addr_inferred__0_i_3 + (.I0(\data_sync[2]_2 [38]), + .O(ipif_Addr[6])); + LUT1 #( + .INIT(2'h2)) + ipif_Addr_inferred__0_i_4 + (.I0(\data_sync[2]_2 [37]), + .O(ipif_Addr[5])); + LUT1 #( + .INIT(2'h2)) + ipif_Addr_inferred__0_i_5 + (.I0(\data_sync[2]_2 [36]), + .O(ipif_Addr[4])); + LUT1 #( + .INIT(2'h2)) + ipif_Addr_inferred__0_i_6 + (.I0(\data_sync[2]_2 [35]), + .O(ipif_Addr[3])); + LUT1 #( + .INIT(2'h2)) + ipif_Addr_inferred__0_i_7 + (.I0(\data_sync[2]_2 [34]), + .O(ipif_Addr[2])); + LUT1 #( + .INIT(2'h2)) + ipif_Addr_inferred__0_i_8 + (.I0(\data_sync[2]_2 [33]), + .O(ipif_Addr[1])); + LUT1 #( + .INIT(2'h2)) + ipif_Addr_inferred__0_i_9 + (.I0(\data_sync[2]_2 [32]), + .O(ipif_Addr[0])); +endmodule + +(* ORIG_REF_NAME = "video_clock_cross" *) +module Arty_Z7_20_v_tc_1_0_video_clock_cross__parameterized0 + (p_526_out, + out_data, + p_528_out, + \AXI4_LITE_INTERFACE.ipif_Error_reg , + write_ack_d2, + write_ack_d1, + read_ack_d2, + read_ack_d1, + in_data, + aclk); + output p_526_out; + output [33:0]out_data; + output p_528_out; + output \AXI4_LITE_INTERFACE.ipif_Error_reg ; + input write_ack_d2; + input write_ack_d1; + input read_ack_d2; + input read_ack_d1; + input [33:0]in_data; + input aclk; + + wire \AXI4_LITE_INTERFACE.ipif_Error_reg ; + wire aclk; + (* async_reg = "true" *) (* shift_extract = "NO" *) (* shreg_extract = "no" *) wire [33:0]\data_sync[0]_0 ; + (* async_reg = "true" *) (* shift_extract = "NO" *) (* shreg_extract = "no" *) wire [33:0]\data_sync[1]_1 ; + (* async_reg = "true" *) (* shift_extract = "NO" *) (* shreg_extract = "no" *) wire [33:0]\data_sync[2]_2 ; + (* shreg_extract = "no" *) wire [33:0]in_data; + wire p_526_out; + wire p_528_out; + wire read_ack_d1; + wire read_ack_d2; + wire write_ack_d1; + wire write_ack_d2; + + assign out_data[33:0] = \data_sync[2]_2 ; + LUT6 #( + .INIT(64'hF7F7F7F700F7F7F7)) + \AXI4_LITE_INTERFACE.ipif_Error_i_1 + (.I0(read_ack_d1), + .I1(\data_sync[2]_2 [32]), + .I2(read_ack_d2), + .I3(write_ack_d1), + .I4(\data_sync[2]_2 [33]), + .I5(write_ack_d2), + .O(\AXI4_LITE_INTERFACE.ipif_Error_reg )); + LUT3 #( + .INIT(8'h40)) + \AXI4_LITE_INTERFACE.ipif_RdAck_i_1 + (.I0(read_ack_d2), + .I1(\data_sync[2]_2 [32]), + .I2(read_ack_d1), + .O(p_528_out)); + LUT3 #( + .INIT(8'h40)) + \AXI4_LITE_INTERFACE.ipif_WrAck_i_1 + (.I0(write_ack_d2), + .I1(\data_sync[2]_2 [33]), + .I2(write_ack_d1), + .O(p_526_out)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][0] + (.C(aclk), + .CE(1'b1), + .D(in_data[0]), + .Q(\data_sync[0]_0 [0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][10] + (.C(aclk), + .CE(1'b1), + .D(in_data[10]), + .Q(\data_sync[0]_0 [10]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][11] + (.C(aclk), + .CE(1'b1), + .D(in_data[11]), + .Q(\data_sync[0]_0 [11]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][12] + (.C(aclk), + .CE(1'b1), + .D(in_data[12]), + .Q(\data_sync[0]_0 [12]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][13] + (.C(aclk), + .CE(1'b1), + .D(in_data[13]), + .Q(\data_sync[0]_0 [13]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][14] + (.C(aclk), + .CE(1'b1), + .D(in_data[14]), + .Q(\data_sync[0]_0 [14]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][15] + (.C(aclk), + .CE(1'b1), + .D(in_data[15]), + .Q(\data_sync[0]_0 [15]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][16] + (.C(aclk), + .CE(1'b1), + .D(in_data[16]), + .Q(\data_sync[0]_0 [16]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][17] + (.C(aclk), + .CE(1'b1), + .D(in_data[17]), + .Q(\data_sync[0]_0 [17]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][18] + (.C(aclk), + .CE(1'b1), + .D(in_data[18]), + .Q(\data_sync[0]_0 [18]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][19] + (.C(aclk), + .CE(1'b1), + .D(in_data[19]), + .Q(\data_sync[0]_0 [19]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][1] + (.C(aclk), + .CE(1'b1), + .D(in_data[1]), + .Q(\data_sync[0]_0 [1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][20] + (.C(aclk), + .CE(1'b1), + .D(in_data[20]), + .Q(\data_sync[0]_0 [20]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][21] + (.C(aclk), + .CE(1'b1), + .D(in_data[21]), + .Q(\data_sync[0]_0 [21]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][22] + (.C(aclk), + .CE(1'b1), + .D(in_data[22]), + .Q(\data_sync[0]_0 [22]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][23] + (.C(aclk), + .CE(1'b1), + .D(in_data[23]), + .Q(\data_sync[0]_0 [23]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][24] + (.C(aclk), + .CE(1'b1), + .D(in_data[24]), + .Q(\data_sync[0]_0 [24]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][25] + (.C(aclk), + .CE(1'b1), + .D(in_data[25]), + .Q(\data_sync[0]_0 [25]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][26] + (.C(aclk), + .CE(1'b1), + .D(in_data[26]), + .Q(\data_sync[0]_0 [26]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][27] + (.C(aclk), + .CE(1'b1), + .D(in_data[27]), + .Q(\data_sync[0]_0 [27]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][28] + (.C(aclk), + .CE(1'b1), + .D(in_data[28]), + .Q(\data_sync[0]_0 [28]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][29] + (.C(aclk), + .CE(1'b1), + .D(in_data[29]), + .Q(\data_sync[0]_0 [29]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][2] + (.C(aclk), + .CE(1'b1), + .D(in_data[2]), + .Q(\data_sync[0]_0 [2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][30] + (.C(aclk), + .CE(1'b1), + .D(in_data[30]), + .Q(\data_sync[0]_0 [30]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][31] + (.C(aclk), + .CE(1'b1), + .D(in_data[31]), + .Q(\data_sync[0]_0 [31]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][32] + (.C(aclk), + .CE(1'b1), + .D(in_data[32]), + .Q(\data_sync[0]_0 [32]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][33] + (.C(aclk), + .CE(1'b1), + .D(in_data[33]), + .Q(\data_sync[0]_0 [33]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][3] + (.C(aclk), + .CE(1'b1), + .D(in_data[3]), + .Q(\data_sync[0]_0 [3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][4] + (.C(aclk), + .CE(1'b1), + .D(in_data[4]), + .Q(\data_sync[0]_0 [4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][5] + (.C(aclk), + .CE(1'b1), + .D(in_data[5]), + .Q(\data_sync[0]_0 [5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][6] + (.C(aclk), + .CE(1'b1), + .D(in_data[6]), + .Q(\data_sync[0]_0 [6]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][7] + (.C(aclk), + .CE(1'b1), + .D(in_data[7]), + .Q(\data_sync[0]_0 [7]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][8] + (.C(aclk), + .CE(1'b1), + .D(in_data[8]), + .Q(\data_sync[0]_0 [8]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[0][9] + (.C(aclk), + .CE(1'b1), + .D(in_data[9]), + .Q(\data_sync[0]_0 [9]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][0] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [0]), + .Q(\data_sync[1]_1 [0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][10] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [10]), + .Q(\data_sync[1]_1 [10]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][11] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [11]), + .Q(\data_sync[1]_1 [11]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][12] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [12]), + .Q(\data_sync[1]_1 [12]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][13] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [13]), + .Q(\data_sync[1]_1 [13]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][14] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [14]), + .Q(\data_sync[1]_1 [14]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][15] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [15]), + .Q(\data_sync[1]_1 [15]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][16] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [16]), + .Q(\data_sync[1]_1 [16]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][17] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [17]), + .Q(\data_sync[1]_1 [17]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][18] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [18]), + .Q(\data_sync[1]_1 [18]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][19] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [19]), + .Q(\data_sync[1]_1 [19]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][1] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [1]), + .Q(\data_sync[1]_1 [1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][20] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [20]), + .Q(\data_sync[1]_1 [20]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][21] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [21]), + .Q(\data_sync[1]_1 [21]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][22] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [22]), + .Q(\data_sync[1]_1 [22]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][23] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [23]), + .Q(\data_sync[1]_1 [23]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][24] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [24]), + .Q(\data_sync[1]_1 [24]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][25] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [25]), + .Q(\data_sync[1]_1 [25]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][26] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [26]), + .Q(\data_sync[1]_1 [26]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][27] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [27]), + .Q(\data_sync[1]_1 [27]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][28] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [28]), + .Q(\data_sync[1]_1 [28]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][29] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [29]), + .Q(\data_sync[1]_1 [29]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][2] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [2]), + .Q(\data_sync[1]_1 [2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][30] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [30]), + .Q(\data_sync[1]_1 [30]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][31] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [31]), + .Q(\data_sync[1]_1 [31]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][32] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [32]), + .Q(\data_sync[1]_1 [32]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][33] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [33]), + .Q(\data_sync[1]_1 [33]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][3] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [3]), + .Q(\data_sync[1]_1 [3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][4] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [4]), + .Q(\data_sync[1]_1 [4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][5] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [5]), + .Q(\data_sync[1]_1 [5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][6] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [6]), + .Q(\data_sync[1]_1 [6]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][7] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [7]), + .Q(\data_sync[1]_1 [7]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][8] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [8]), + .Q(\data_sync[1]_1 [8]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[1][9] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[0]_0 [9]), + .Q(\data_sync[1]_1 [9]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][0] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [0]), + .Q(\data_sync[2]_2 [0]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][10] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [10]), + .Q(\data_sync[2]_2 [10]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][11] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [11]), + .Q(\data_sync[2]_2 [11]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][12] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [12]), + .Q(\data_sync[2]_2 [12]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][13] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [13]), + .Q(\data_sync[2]_2 [13]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][14] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [14]), + .Q(\data_sync[2]_2 [14]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][15] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [15]), + .Q(\data_sync[2]_2 [15]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][16] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [16]), + .Q(\data_sync[2]_2 [16]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][17] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [17]), + .Q(\data_sync[2]_2 [17]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][18] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [18]), + .Q(\data_sync[2]_2 [18]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][19] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [19]), + .Q(\data_sync[2]_2 [19]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][1] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [1]), + .Q(\data_sync[2]_2 [1]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][20] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [20]), + .Q(\data_sync[2]_2 [20]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][21] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [21]), + .Q(\data_sync[2]_2 [21]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][22] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [22]), + .Q(\data_sync[2]_2 [22]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][23] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [23]), + .Q(\data_sync[2]_2 [23]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][24] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [24]), + .Q(\data_sync[2]_2 [24]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][25] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [25]), + .Q(\data_sync[2]_2 [25]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][26] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [26]), + .Q(\data_sync[2]_2 [26]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][27] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [27]), + .Q(\data_sync[2]_2 [27]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][28] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [28]), + .Q(\data_sync[2]_2 [28]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][29] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [29]), + .Q(\data_sync[2]_2 [29]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][2] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [2]), + .Q(\data_sync[2]_2 [2]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][30] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [30]), + .Q(\data_sync[2]_2 [30]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][31] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [31]), + .Q(\data_sync[2]_2 [31]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][32] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [32]), + .Q(\data_sync[2]_2 [32]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][33] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [33]), + .Q(\data_sync[2]_2 [33]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][3] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [3]), + .Q(\data_sync[2]_2 [3]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][4] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [4]), + .Q(\data_sync[2]_2 [4]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][5] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [5]), + .Q(\data_sync[2]_2 [5]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][6] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [6]), + .Q(\data_sync[2]_2 [6]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][7] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [7]), + .Q(\data_sync[2]_2 [7]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][8] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [8]), + .Q(\data_sync[2]_2 [8]), + .R(1'b0)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* SHREG_EXTRACT = "no" *) + (* shift_extract = "NO" *) + FDRE \data_sync_reg[2][9] + (.C(aclk), + .CE(1'b1), + .D(\data_sync[1]_1 [9]), + .Q(\data_sync[2]_2 [9]), + .R(1'b0)); +endmodule + +(* C_COREGEN_PATCH = "0" *) (* C_CORE_AXI_WRITE = "544'b0000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111" *) (* C_CORE_DBUFFER = "544'b0000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000000000000000000000000000000" *) +(* C_CORE_DEFAULT = "544'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_CORE_NUM_REGS = "17" *) (* C_FAMILY = "virtex5" *) +(* C_GENR_AXI_WRITE = "160'b1100011111111111111011110010111111111111111111110011111100000000000000000011111100000000000000001111111111111111001111110000000000000000000000000000000000000000" *) (* C_GENR_DBUFFER = "160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_GENR_DEFAULT = "160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) +(* C_GENR_NUM_REGS = "5" *) (* C_GENR_SELFCLR = "256'b0000000000000000000000000000000011111111111111111111111111111111111111111111111111111111111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_HAS_AXI4_LITE = "1" *) +(* C_HAS_IRQ = "1" *) (* C_IS_EVAL = "FALSE" *) (* C_REVISION_NUMBER = "11" *) +(* C_SRESET_LENGTH = "2" *) (* C_S_AXI_ADDR_WIDTH = "9" *) (* C_S_AXI_DATA_WIDTH = "32" *) +(* C_TIMEOUT_HOURS = "8" *) (* C_TIMEOUT_MINS = "0" *) (* C_TIME_AXI_WRITE = "928'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111111110001111111111111000000000000000000000000000000000000000000000000000000111100111100000000000000000000000001111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111" *) +(* C_TIME_DBUFFER = "928'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111111110001111111111111000000000000000000000000000000000000000000000000000000111000000000000000000000000000000000111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111" *) (* C_TIME_DEFAULT = "928'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010110100000000010100000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000001111111000000000000000000000110011100100000001011101110000000101110111000000101100101100000010101101110000001010000000000000101000000000000001011011001000000101101010000000101000000000000010100000000000001010000000000000101000000000000001011011001000000101101010000000101000000000000010100000000" *) (* C_TIME_NUM_REGS = "29" *) +(* C_VERSION_MAJOR = "6" *) (* C_VERSION_MINOR = "1" *) (* C_VERSION_REVISION = "0" *) +(* ORIG_REF_NAME = "video_ctrl" *) (* downgradeipidentifiedwarnings = "yes" *) +module Arty_Z7_20_v_tc_1_0_video_ctrl + (aclk, + aclk_en, + aresetn, + vid_aclk, + vid_aclk_en, + vid_aresetn, + reg_update, + irq, + resetn_out, + core_d_out, + ipif_addr_out, + ipif_rnw_out, + ipif_cs_out, + ipif_data_out, + \genr_control_regs[0] , + \genr_control_regs[1] , + \genr_control_regs[2] , + \genr_control_regs[3] , + \genr_control_regs[4] , + \genr_status_regs[0] , + \genr_status_regs[1] , + \genr_status_regs[2] , + \genr_status_regs[3] , + \genr_status_regs[4] , + \time_control_regs[0] , + \time_control_regs[1] , + \time_control_regs[2] , + \time_control_regs[3] , + \time_control_regs[4] , + \time_control_regs[5] , + \time_control_regs[6] , + \time_control_regs[7] , + \time_control_regs[8] , + \time_control_regs[9] , + \time_control_regs[10] , + \time_control_regs[11] , + \time_control_regs[12] , + \time_control_regs[13] , + \time_control_regs[14] , + \time_control_regs[15] , + \time_control_regs[16] , + \time_control_regs[17] , + \time_control_regs[18] , + \time_control_regs[19] , + \time_control_regs[20] , + \time_control_regs[21] , + \time_control_regs[22] , + \time_control_regs[23] , + \time_control_regs[24] , + \time_control_regs[25] , + \time_control_regs[26] , + \time_control_regs[27] , + \time_control_regs[28] , + \time_status_regs[0] , + \time_status_regs[1] , + \time_status_regs[2] , + \time_status_regs[3] , + \time_status_regs[4] , + \time_status_regs[5] , + \time_status_regs[6] , + \time_status_regs[7] , + \time_status_regs[8] , + \time_status_regs[9] , + \time_status_regs[10] , + \time_status_regs[11] , + \time_status_regs[12] , + \time_status_regs[13] , + \time_status_regs[14] , + \time_status_regs[15] , + \time_status_regs[16] , + \time_status_regs[17] , + \time_status_regs[18] , + \time_status_regs[19] , + \time_status_regs[20] , + \time_status_regs[21] , + \time_status_regs[22] , + \time_status_regs[23] , + \time_status_regs[24] , + \time_status_regs[25] , + \time_status_regs[26] , + \time_status_regs[27] , + \time_status_regs[28] , + \core_control_regs[0] , + \core_control_regs[1] , + \core_control_regs[2] , + \core_control_regs[3] , + \core_control_regs[4] , + \core_control_regs[5] , + \core_control_regs[6] , + \core_control_regs[7] , + \core_control_regs[8] , + \core_control_regs[9] , + \core_control_regs[10] , + \core_control_regs[11] , + \core_control_regs[12] , + \core_control_regs[13] , + \core_control_regs[14] , + \core_control_regs[15] , + \core_control_regs[16] , + \core_status_regs[0] , + \core_status_regs[1] , + \core_status_regs[2] , + \core_status_regs[3] , + \core_status_regs[4] , + \core_status_regs[5] , + \core_status_regs[6] , + \core_status_regs[7] , + \core_status_regs[8] , + \core_status_regs[9] , + \core_status_regs[10] , + \core_status_regs[11] , + \core_status_regs[12] , + \core_status_regs[13] , + \core_status_regs[14] , + \core_status_regs[15] , + \core_status_regs[16] , + s_axi_awaddr, + s_axi_awvalid, + s_axi_awready, + s_axi_wdata, + s_axi_wstrb, + s_axi_wvalid, + s_axi_wready, + s_axi_bresp, + s_axi_bvalid, + s_axi_bready, + s_axi_araddr, + s_axi_arvalid, + s_axi_arready, + s_axi_rdata, + s_axi_rresp, + s_axi_rvalid, + s_axi_rready); + input aclk; + input aclk_en; + input aresetn; + input vid_aclk; + input vid_aclk_en; + input vid_aresetn; + input reg_update; + output irq; + output resetn_out; + output core_d_out; + output [8:0]ipif_addr_out; + output ipif_rnw_out; + output ipif_cs_out; + output [31:0]ipif_data_out; + output [31:0]\genr_control_regs[0] ; + output [31:0]\genr_control_regs[1] ; + output [31:0]\genr_control_regs[2] ; + output [31:0]\genr_control_regs[3] ; + output [31:0]\genr_control_regs[4] ; + input [31:0]\genr_status_regs[0] ; + input [31:0]\genr_status_regs[1] ; + input [31:0]\genr_status_regs[2] ; + input [31:0]\genr_status_regs[3] ; + input [31:0]\genr_status_regs[4] ; + output [31:0]\time_control_regs[0] ; + output [31:0]\time_control_regs[1] ; + output [31:0]\time_control_regs[2] ; + output [31:0]\time_control_regs[3] ; + output [31:0]\time_control_regs[4] ; + output [31:0]\time_control_regs[5] ; + output [31:0]\time_control_regs[6] ; + output [31:0]\time_control_regs[7] ; + output [31:0]\time_control_regs[8] ; + output [31:0]\time_control_regs[9] ; + output [31:0]\time_control_regs[10] ; + output [31:0]\time_control_regs[11] ; + output [31:0]\time_control_regs[12] ; + output [31:0]\time_control_regs[13] ; + output [31:0]\time_control_regs[14] ; + output [31:0]\time_control_regs[15] ; + output [31:0]\time_control_regs[16] ; + output [31:0]\time_control_regs[17] ; + output [31:0]\time_control_regs[18] ; + output [31:0]\time_control_regs[19] ; + output [31:0]\time_control_regs[20] ; + output [31:0]\time_control_regs[21] ; + output [31:0]\time_control_regs[22] ; + output [31:0]\time_control_regs[23] ; + output [31:0]\time_control_regs[24] ; + output [31:0]\time_control_regs[25] ; + output [31:0]\time_control_regs[26] ; + output [31:0]\time_control_regs[27] ; + output [31:0]\time_control_regs[28] ; + input [31:0]\time_status_regs[0] ; + input [31:0]\time_status_regs[1] ; + input [31:0]\time_status_regs[2] ; + input [31:0]\time_status_regs[3] ; + input [31:0]\time_status_regs[4] ; + input [31:0]\time_status_regs[5] ; + input [31:0]\time_status_regs[6] ; + input [31:0]\time_status_regs[7] ; + input [31:0]\time_status_regs[8] ; + input [31:0]\time_status_regs[9] ; + input [31:0]\time_status_regs[10] ; + input [31:0]\time_status_regs[11] ; + input [31:0]\time_status_regs[12] ; + input [31:0]\time_status_regs[13] ; + input [31:0]\time_status_regs[14] ; + input [31:0]\time_status_regs[15] ; + input [31:0]\time_status_regs[16] ; + input [31:0]\time_status_regs[17] ; + input [31:0]\time_status_regs[18] ; + input [31:0]\time_status_regs[19] ; + input [31:0]\time_status_regs[20] ; + input [31:0]\time_status_regs[21] ; + input [31:0]\time_status_regs[22] ; + input [31:0]\time_status_regs[23] ; + input [31:0]\time_status_regs[24] ; + input [31:0]\time_status_regs[25] ; + input [31:0]\time_status_regs[26] ; + input [31:0]\time_status_regs[27] ; + input [31:0]\time_status_regs[28] ; + output [31:0]\core_control_regs[0] ; + output [31:0]\core_control_regs[1] ; + output [31:0]\core_control_regs[2] ; + output [31:0]\core_control_regs[3] ; + output [31:0]\core_control_regs[4] ; + output [31:0]\core_control_regs[5] ; + output [31:0]\core_control_regs[6] ; + output [31:0]\core_control_regs[7] ; + output [31:0]\core_control_regs[8] ; + output [31:0]\core_control_regs[9] ; + output [31:0]\core_control_regs[10] ; + output [31:0]\core_control_regs[11] ; + output [31:0]\core_control_regs[12] ; + output [31:0]\core_control_regs[13] ; + output [31:0]\core_control_regs[14] ; + output [31:0]\core_control_regs[15] ; + output [31:0]\core_control_regs[16] ; + input [31:0]\core_status_regs[0] ; + input [31:0]\core_status_regs[1] ; + input [31:0]\core_status_regs[2] ; + input [31:0]\core_status_regs[3] ; + input [31:0]\core_status_regs[4] ; + input [31:0]\core_status_regs[5] ; + input [31:0]\core_status_regs[6] ; + input [31:0]\core_status_regs[7] ; + input [31:0]\core_status_regs[8] ; + input [31:0]\core_status_regs[9] ; + input [31:0]\core_status_regs[10] ; + input [31:0]\core_status_regs[11] ; + input [31:0]\core_status_regs[12] ; + input [31:0]\core_status_regs[13] ; + input [31:0]\core_status_regs[14] ; + input [31:0]\core_status_regs[15] ; + input [31:0]\core_status_regs[16] ; + input [8:0]s_axi_awaddr; + input s_axi_awvalid; + output s_axi_awready; + input [31:0]s_axi_wdata; + input [3:0]s_axi_wstrb; + input s_axi_wvalid; + output s_axi_wready; + output [1:0]s_axi_bresp; + output s_axi_bvalid; + input s_axi_bready; + input [8:0]s_axi_araddr; + input s_axi_arvalid; + output s_axi_arready; + output [31:0]s_axi_rdata; + output [1:0]s_axi_rresp; + output s_axi_rvalid; + input s_axi_rready; + + wire \ ; + wire \AXI4_LITE_INTERFACE.CORE_MUX0_n_0 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_0 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_1 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_34 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_35 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_36 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_37 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_38 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_39 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_40 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_41 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_42 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_43 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_44 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_45 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_46 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_47 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_48 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_49 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_50 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_51 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_52 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_53 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_54 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_55 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_56 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_57 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_58 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_59 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_60 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_61 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_62 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_63 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_64 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_65 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_66 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_67 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_68 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_69 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_70 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_71 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_72 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_73 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_74 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_75 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_76 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_77 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_78 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_79 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_80 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_81 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_82 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_83 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_84 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_85 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_86 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_87 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_88 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_89 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_90 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_91 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_92 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_93 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_94 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_95 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_96 ; + wire \AXI4_LITE_INTERFACE.GENR_MUX0_n_97 ; + wire \AXI4_LITE_INTERFACE.SYNC2PROCCLK_I_n_36 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_0 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_110 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_137 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_138 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_139 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_140 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_141 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_142 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_143 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_144 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_145 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_146 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_147 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_148 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_149 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_150 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_151 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_152 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_153 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_154 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_155 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_156 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_157 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_158 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_159 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_160 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_161 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_162 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_163 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_164 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_165 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_166 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_167 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_168 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_169 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_170 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_171 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_172 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_173 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_174 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_175 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_176 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_177 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_178 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_179 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_180 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_181 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_182 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_183 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_184 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_185 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_186 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_187 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_188 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_189 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_190 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_191 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_192 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_193 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_194 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_195 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_196 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_197 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_198 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_199 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_200 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_201 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_202 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_203 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_204 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_205 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_206 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_207 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_208 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_209 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_210 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_211 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_212 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_213 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_214 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_215 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_216 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_217 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_218 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_219 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_220 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_221 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_222 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_223 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_224 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_225 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_226 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_227 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_228 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_229 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_230 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_231 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_232 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_233 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_234 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_235 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_236 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_237 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_238 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_239 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_240 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_241 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_242 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_243 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_244 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_245 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_246 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_247 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_248 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_249 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_250 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_251 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_252 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_253 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_254 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_255 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_256 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_257 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_258 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_259 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_260 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_261 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_262 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_263 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_264 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_265 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_266 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_267 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_268 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_269 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_270 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_271 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_272 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_273 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_274 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_275 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_276 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_277 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_278 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_279 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_280 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_281 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_282 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_283 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_284 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_285 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_286 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_287 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_288 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_289 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_290 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_291 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_292 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_293 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_294 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_295 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_296 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_297 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_298 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_299 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_300 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_301 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_302 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_303 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_304 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_305 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_306 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_307 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_308 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_309 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_310 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_311 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_312 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_313 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_314 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_315 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_316 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_317 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_318 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_319 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_320 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_321 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_322 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_323 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_324 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_325 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_326 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_327 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_328 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_329 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_330 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_331 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_332 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_333 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_334 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_335 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_336 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_337 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_338 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_339 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_34 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_340 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_341 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_342 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_343 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_344 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_345 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_346 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_347 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_348 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_349 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_35 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_350 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_351 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_352 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_353 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_354 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_355 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_356 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_357 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_358 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_359 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_36 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_360 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_361 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_362 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_363 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_364 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_365 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_366 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_367 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_368 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_369 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_37 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_370 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_371 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_372 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_373 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_374 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_375 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_376 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_377 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_378 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_379 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_38 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_380 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_381 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_382 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_383 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_384 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_385 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_386 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_387 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_388 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_389 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_39 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_390 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_391 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_392 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_393 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_394 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_395 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_396 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_397 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_398 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_399 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_40 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_400 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_401 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_402 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_403 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_404 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_405 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_406 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_407 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_408 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_409 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_41 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_410 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_411 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_412 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_413 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_414 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_415 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_416 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_417 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_418 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_419 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_42 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_420 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_421 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_422 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_423 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_424 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_425 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_426 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_427 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_428 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_429 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_43 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_430 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_431 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_432 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_433 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_434 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_435 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_436 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_437 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_438 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_439 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_44 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_440 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_441 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_442 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_443 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_444 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_445 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_446 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_447 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_448 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_449 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_45 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_450 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_451 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_452 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_453 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_454 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_455 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_456 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_457 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_458 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_459 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_46 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_460 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_461 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_462 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_463 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_464 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_465 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_466 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_467 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_468 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_469 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_47 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_470 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_471 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_472 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_473 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_474 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_475 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_476 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_477 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_478 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_479 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_48 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_480 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_481 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_482 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_483 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_484 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_485 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_486 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_487 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_488 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_489 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_49 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_490 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_491 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_492 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_493 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_494 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_495 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_496 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_497 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_498 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_499 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_50 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_500 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_501 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_502 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_503 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_504 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_505 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_506 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_507 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_508 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_509 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_51 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_510 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_511 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_512 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_513 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_514 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_515 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_516 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_517 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_518 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_519 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_52 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_520 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_521 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_522 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_523 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_524 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_525 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_526 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_527 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_528 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_529 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_53 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_530 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_531 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_532 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_533 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_534 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_535 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_536 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_537 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_538 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_539 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_54 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_540 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_541 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_542 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_543 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_544 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_545 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_546 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_547 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_548 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_549 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_55 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_550 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_551 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_552 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_553 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_554 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_555 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_556 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_557 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_558 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_559 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_56 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_560 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_561 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_562 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_563 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_564 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_565 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_566 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_567 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_568 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_569 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_57 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_570 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_571 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_572 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_573 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_574 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_575 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_576 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_577 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_578 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_579 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_58 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_580 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_581 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_582 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_583 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_584 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_585 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_586 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_587 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_588 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_589 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_59 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_590 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_591 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_592 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_593 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_594 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_595 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_596 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_597 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_598 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_599 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_60 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_600 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_601 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_602 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_603 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_604 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_605 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_606 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_607 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_608 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_609 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_61 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_610 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_611 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_612 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_613 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_614 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_615 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_616 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_617 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_618 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_619 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_62 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_620 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_621 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_622 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_623 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_624 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_625 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_626 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_627 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_628 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_629 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_63 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_630 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_631 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_632 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_633 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_634 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_635 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_636 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_637 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_638 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_639 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_64 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_640 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_641 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_642 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_643 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_644 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_645 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_646 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_647 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_648 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_649 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_65 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_650 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_66 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_67 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_68 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_69 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_70 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_71 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_72 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_73 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_74 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_75 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_76 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_77 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_78 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_79 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_80 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_81 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_82 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_83 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_84 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_85 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_86 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_87 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_88 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_89 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_90 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_91 ; + wire \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_92 ; + wire \AXI4_LITE_INTERFACE.read_ack_d_reg[2]_srl4___AXI4_LITE_INTERFACE.read_ack_d_reg_r_1_n_0 ; + wire \AXI4_LITE_INTERFACE.read_ack_d_reg[3]_AXI4_LITE_INTERFACE.read_ack_d_reg_r_2_n_0 ; + wire \AXI4_LITE_INTERFACE.read_ack_d_reg_gate_n_0 ; + wire \AXI4_LITE_INTERFACE.read_ack_d_reg_r_0_n_0 ; + wire \AXI4_LITE_INTERFACE.read_ack_d_reg_r_1_n_0 ; + wire \AXI4_LITE_INTERFACE.read_ack_d_reg_r_2_n_0 ; + wire \AXI4_LITE_INTERFACE.read_ack_d_reg_r_n_0 ; + wire \AXI4_LITE_INTERFACE.read_ack_reg_r_n_0 ; + wire \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ; + wire \AXI4_LITE_INTERFACE.write_ack_e1_i_1_n_0 ; + wire \AXI4_LITE_INTERFACE.write_ack_int_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[0]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[10]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[11]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[12]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[13]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[14]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[15]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[16]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[16]_i_2_n_0 ; + wire \GEN_HAS_IRQ.intr_err[17]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[17]_i_2_n_0 ; + wire \GEN_HAS_IRQ.intr_err[18]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[18]_i_2_n_0 ; + wire \GEN_HAS_IRQ.intr_err[19]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[19]_i_2_n_0 ; + wire \GEN_HAS_IRQ.intr_err[1]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[20]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[20]_i_2_n_0 ; + wire \GEN_HAS_IRQ.intr_err[21]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[21]_i_2_n_0 ; + wire \GEN_HAS_IRQ.intr_err[22]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[23]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[24]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[25]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[26]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[27]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[28]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[29]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[2]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[30]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[31]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[3]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[4]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[5]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[6]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[7]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[8]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_err[9]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[0]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[10]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[10]_i_2_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[11]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[11]_i_2_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[12]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[12]_i_2_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[13]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[13]_i_2_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[14]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[15]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[16]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[16]_i_2_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[17]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[17]_i_2_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[18]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[18]_i_2_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[19]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[19]_i_2_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[1]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[20]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[20]_i_2_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[21]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[21]_i_2_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[22]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[22]_i_2_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[23]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[23]_i_2_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[24]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[24]_i_2_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[25]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[25]_i_2_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[26]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[26]_i_2_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[27]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[27]_i_2_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[28]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[28]_i_2_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[29]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[29]_i_2_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[2]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[30]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[30]_i_2_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[31]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[31]_i_2_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[3]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[4]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[5]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[6]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[7]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[8]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[8]_i_2_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[9]_i_1_n_0 ; + wire \GEN_HAS_IRQ.intr_stat[9]_i_2_n_0 ; + wire \GEN_HAS_IRQ.intr_stat_reg_n_0_[31] ; + wire \GEN_HAS_IRQ.irq_i_10_n_0 ; + wire \GEN_HAS_IRQ.irq_i_1_n_0 ; + wire \GEN_HAS_IRQ.irq_i_2_n_0 ; + wire \GEN_HAS_IRQ.irq_i_3_n_0 ; + wire \GEN_HAS_IRQ.irq_i_4_n_0 ; + wire \GEN_HAS_IRQ.irq_i_5_n_0 ; + wire \GEN_HAS_IRQ.irq_i_6_n_0 ; + wire \GEN_HAS_IRQ.irq_i_7_n_0 ; + wire \GEN_HAS_IRQ.irq_i_8_n_0 ; + wire \GEN_HAS_IRQ.irq_i_9_n_0 ; + wire aclk; + wire aclk_en; + wire aresetn; + wire [0:0]\core_control_regs2_int[0] ; + wire [0:0]\core_control_regs2_int[10] ; + wire [0:0]\core_control_regs2_int[11] ; + wire [0:0]\core_control_regs2_int[12] ; + wire [0:0]\core_control_regs2_int[13] ; + wire [0:0]\core_control_regs2_int[14] ; + wire [0:0]\core_control_regs2_int[15] ; + wire [0:0]\core_control_regs2_int[1] ; + wire [0:0]\core_control_regs2_int[2] ; + wire [0:0]\core_control_regs2_int[3] ; + wire [0:0]\core_control_regs2_int[4] ; + wire [0:0]\core_control_regs2_int[5] ; + wire [0:0]\core_control_regs2_int[6] ; + wire [0:0]\core_control_regs2_int[7] ; + wire [0:0]\core_control_regs2_int[8] ; + wire [0:0]\core_control_regs2_int[9] ; + wire [26:0]\^core_control_regs[0] ; + wire [26:0]\^core_control_regs[10] ; + wire [26:0]\^core_control_regs[11] ; + wire [26:0]\^core_control_regs[12] ; + wire [26:0]\^core_control_regs[13] ; + wire [26:0]\^core_control_regs[14] ; + wire [26:0]\^core_control_regs[15] ; + wire [26:0]\^core_control_regs[16] ; + wire [26:0]\^core_control_regs[1] ; + wire [26:0]\^core_control_regs[2] ; + wire [26:0]\^core_control_regs[3] ; + wire [26:0]\^core_control_regs[4] ; + wire [26:0]\^core_control_regs[5] ; + wire [26:0]\^core_control_regs[6] ; + wire [26:0]\^core_control_regs[7] ; + wire [26:0]\^core_control_regs[8] ; + wire [26:0]\^core_control_regs[9] ; + wire [26:26]\core_control_regs_int[0] ; + wire [26:26]\core_control_regs_int[10] ; + wire [26:26]\core_control_regs_int[11] ; + wire [26:26]\core_control_regs_int[12] ; + wire [26:26]\core_control_regs_int[13] ; + wire [26:26]\core_control_regs_int[14] ; + wire [26:26]\core_control_regs_int[15] ; + wire [26:26]\core_control_regs_int[16] ; + wire [26:26]\core_control_regs_int[1] ; + wire [26:26]\core_control_regs_int[2] ; + wire [26:26]\core_control_regs_int[3] ; + wire [26:26]\core_control_regs_int[4] ; + wire [26:26]\core_control_regs_int[5] ; + wire [26:26]\core_control_regs_int[6] ; + wire [26:26]\core_control_regs_int[7] ; + wire [26:26]\core_control_regs_int[8] ; + wire [26:26]\core_control_regs_int[9] ; + wire [31:0]core_data; + wire [506:1]core_regs; + wire [31:0]\core_status_regs[0] ; + wire [31:0]\core_status_regs[10] ; + wire [31:0]\core_status_regs[11] ; + wire [31:0]\core_status_regs[12] ; + wire [31:0]\core_status_regs[13] ; + wire [31:0]\core_status_regs[14] ; + wire [31:0]\core_status_regs[15] ; + wire [31:0]\core_status_regs[16] ; + wire [31:0]\core_status_regs[1] ; + wire [31:0]\core_status_regs[2] ; + wire [31:0]\core_status_regs[3] ; + wire [31:0]\core_status_regs[4] ; + wire [31:0]\core_status_regs[5] ; + wire [31:0]\core_status_regs[6] ; + wire [31:0]\core_status_regs[7] ; + wire [31:0]\core_status_regs[8] ; + wire [31:0]\core_status_regs[9] ; + wire [31:0]\^genr_control_regs[0] ; + wire [31:8]\^genr_control_regs[1] ; + wire [21:16]\^genr_control_regs[2] ; + wire [31:8]\^genr_control_regs[3] ; + wire [31:31]\genr_control_regs_int[0] ; + wire [31:31]\genr_control_regs_int[3] ; + wire [31:0]genr_data; + wire [1180:897]genr_regs; + wire [31:0]\genr_status_regs[0] ; + wire [31:0]\genr_status_regs[1] ; + wire [31:0]\genr_status_regs[2] ; + wire [31:0]\genr_status_regs[3] ; + wire [30:0]\genr_status_regs_int_reg[1] ; + wire [31:0]intr_err; + wire [21:16]intr_err_clr_d; + wire [31:0]intr_err_set_d; + wire [31:8]intr_stat_clr_d; + wire [31:0]intr_stat_set_d; + (* MAX_FANOUT = "128" *) (* RTL_MAX_FANOUT = "found" *) wire [8:0]ipif_Addr; + wire ipif_Error; + wire ipif_RdAck; + wire [31:0]ipif_RdData; + wire ipif_WrAck; + wire ipif_cs_out; + wire [31:0]ipif_data_out; + wire [8:0]ipif_proc_Addr_int; + wire [1:0]ipif_proc_CS; + wire ipif_proc_RNW; + wire ipif_rnw_out; + wire irq; + wire p_0_in; + wire p_0_in_0; + wire p_10_in; + wire p_11_in; + wire p_12_in; + wire p_13_in; + wire [33:0]p_143_out; + wire p_14_in; + wire p_15_in; + wire p_16_in; + wire p_17_in; + wire p_18_in; + wire p_19_in; + wire p_1_in; + wire p_20_in; + wire p_21_in; + wire p_22_in; + wire p_23_in; + wire p_24_in; + wire p_2_in; + wire [6:6]p_2_out; + wire p_3_in; + wire p_456_out; + wire p_4_in; + wire p_526_out; + wire p_528_out; + wire p_533_out; + wire p_534_out; + wire p_535_out; + wire p_5_in; + wire [9:7]p_5_out; + wire p_6_in; + wire p_7_in; + wire p_8_in; + wire [5:0]p_8_out; + wire p_9_in; + wire [44:0]proc_sync1; + wire [4:4]read_ack_d; + wire read_ack_d1; + wire read_ack_d2; + wire reg_update; + wire resetn_out; + wire [8:0]s_axi_araddr; + wire s_axi_arready; + wire s_axi_arvalid; + wire [8:0]s_axi_awaddr; + wire s_axi_awvalid; + wire s_axi_bready; + wire [1:1]\^s_axi_bresp ; + wire s_axi_bvalid; + wire [31:0]s_axi_rdata; + wire s_axi_rready; + wire [1:1]\^s_axi_rresp ; + wire s_axi_rvalid; + wire [31:0]s_axi_wdata; + wire s_axi_wready; + wire s_axi_wvalid; + wire [0:0]\time_control_regs2_int[16] ; + wire [0:0]\time_control_regs2_int[20] ; + wire [0:0]\time_control_regs2_int[21] ; + wire [0:0]\time_control_regs2_int[22] ; + wire [0:0]\time_control_regs2_int[23] ; + wire [0:0]\time_control_regs2_int[24] ; + wire [0:0]\time_control_regs2_int[25] ; + wire [0:0]\time_control_regs2_int[26] ; + wire [0:0]\time_control_regs2_int[27] ; + wire [0:0]\time_control_regs2_int[28] ; + wire [28:0]\^time_control_regs[16] ; + wire [9:0]\^time_control_regs[18] ; + wire [6:0]\^time_control_regs[19] ; + wire [28:0]\^time_control_regs[20] ; + wire [28:0]\^time_control_regs[21] ; + wire [28:0]\^time_control_regs[22] ; + wire [28:0]\^time_control_regs[23] ; + wire [28:0]\^time_control_regs[24] ; + wire [28:0]\^time_control_regs[25] ; + wire [28:0]\^time_control_regs[26] ; + wire [28:0]\^time_control_regs[27] ; + wire [28:0]\^time_control_regs[28] ; + wire [28:28]\time_control_regs_int[16] ; + wire [6:6]\time_control_regs_int[18] ; + wire [28:28]\time_control_regs_int[20] ; + wire [28:28]\time_control_regs_int[21] ; + wire [28:28]\time_control_regs_int[22] ; + wire [28:28]\time_control_regs_int[23] ; + wire [28:28]\time_control_regs_int[24] ; + wire [28:28]\time_control_regs_int[25] ; + wire [28:28]\time_control_regs_int[26] ; + wire [28:28]\time_control_regs_int[27] ; + wire [28:28]\time_control_regs_int[28] ; + wire [31:0]\time_status_regs[0] ; + wire [31:0]\time_status_regs[10] ; + wire [31:0]\time_status_regs[11] ; + wire [31:0]\time_status_regs[12] ; + wire [31:0]\time_status_regs[13] ; + wire [31:0]\time_status_regs[14] ; + wire [31:0]\time_status_regs[15] ; + wire [31:0]\time_status_regs[16] ; + wire [31:0]\time_status_regs[17] ; + wire [31:0]\time_status_regs[18] ; + wire [31:0]\time_status_regs[19] ; + wire [31:0]\time_status_regs[1] ; + wire [31:0]\time_status_regs[20] ; + wire [31:0]\time_status_regs[21] ; + wire [31:0]\time_status_regs[22] ; + wire [31:0]\time_status_regs[23] ; + wire [31:0]\time_status_regs[24] ; + wire [31:0]\time_status_regs[25] ; + wire [31:0]\time_status_regs[26] ; + wire [31:0]\time_status_regs[27] ; + wire [31:0]\time_status_regs[28] ; + wire [31:0]\time_status_regs[2] ; + wire [31:0]\time_status_regs[3] ; + wire [31:0]\time_status_regs[4] ; + wire [31:0]\time_status_regs[5] ; + wire [31:0]\time_status_regs[6] ; + wire [31:0]\time_status_regs[7] ; + wire [31:0]\time_status_regs[8] ; + wire [31:0]\time_status_regs[9] ; + wire vid_aclk; + wire vid_aclk_en; + wire vid_aresetn; + wire write_ack; + wire write_ack_d1; + wire write_ack_d2; + wire write_ack_e1; + wire write_ack_e2; + wire write_ack_int; + + assign \core_control_regs[0] [31] = \ ; + assign \core_control_regs[0] [30] = \ ; + assign \core_control_regs[0] [29] = \ ; + assign \core_control_regs[0] [28] = \ ; + assign \core_control_regs[0] [27] = \ ; + assign \core_control_regs[0] [26:16] = \^core_control_regs[0] [26:16]; + assign \core_control_regs[0] [15] = \ ; + assign \core_control_regs[0] [14] = \ ; + assign \core_control_regs[0] [13] = \ ; + assign \core_control_regs[0] [12] = \ ; + assign \core_control_regs[0] [11:0] = \^core_control_regs[0] [11:0]; + assign \core_control_regs[10] [31] = \ ; + assign \core_control_regs[10] [30] = \ ; + assign \core_control_regs[10] [29] = \ ; + assign \core_control_regs[10] [28] = \ ; + assign \core_control_regs[10] [27] = \ ; + assign \core_control_regs[10] [26:16] = \^core_control_regs[10] [26:16]; + assign \core_control_regs[10] [15] = \ ; + assign \core_control_regs[10] [14] = \ ; + assign \core_control_regs[10] [13] = \ ; + assign \core_control_regs[10] [12] = \ ; + assign \core_control_regs[10] [11:0] = \^core_control_regs[10] [11:0]; + assign \core_control_regs[11] [31] = \ ; + assign \core_control_regs[11] [30] = \ ; + assign \core_control_regs[11] [29] = \ ; + assign \core_control_regs[11] [28] = \ ; + assign \core_control_regs[11] [27] = \ ; + assign \core_control_regs[11] [26:16] = \^core_control_regs[11] [26:16]; + assign \core_control_regs[11] [15] = \ ; + assign \core_control_regs[11] [14] = \ ; + assign \core_control_regs[11] [13] = \ ; + assign \core_control_regs[11] [12] = \ ; + assign \core_control_regs[11] [11:0] = \^core_control_regs[11] [11:0]; + assign \core_control_regs[12] [31] = \ ; + assign \core_control_regs[12] [30] = \ ; + assign \core_control_regs[12] [29] = \ ; + assign \core_control_regs[12] [28] = \ ; + assign \core_control_regs[12] [27] = \ ; + assign \core_control_regs[12] [26:16] = \^core_control_regs[12] [26:16]; + assign \core_control_regs[12] [15] = \ ; + assign \core_control_regs[12] [14] = \ ; + assign \core_control_regs[12] [13] = \ ; + assign \core_control_regs[12] [12] = \ ; + assign \core_control_regs[12] [11:0] = \^core_control_regs[12] [11:0]; + assign \core_control_regs[13] [31] = \ ; + assign \core_control_regs[13] [30] = \ ; + assign \core_control_regs[13] [29] = \ ; + assign \core_control_regs[13] [28] = \ ; + assign \core_control_regs[13] [27] = \ ; + assign \core_control_regs[13] [26:16] = \^core_control_regs[13] [26:16]; + assign \core_control_regs[13] [15] = \ ; + assign \core_control_regs[13] [14] = \ ; + assign \core_control_regs[13] [13] = \ ; + assign \core_control_regs[13] [12] = \ ; + assign \core_control_regs[13] [11:0] = \^core_control_regs[13] [11:0]; + assign \core_control_regs[14] [31] = \ ; + assign \core_control_regs[14] [30] = \ ; + assign \core_control_regs[14] [29] = \ ; + assign \core_control_regs[14] [28] = \ ; + assign \core_control_regs[14] [27] = \ ; + assign \core_control_regs[14] [26:16] = \^core_control_regs[14] [26:16]; + assign \core_control_regs[14] [15] = \ ; + assign \core_control_regs[14] [14] = \ ; + assign \core_control_regs[14] [13] = \ ; + assign \core_control_regs[14] [12] = \ ; + assign \core_control_regs[14] [11:0] = \^core_control_regs[14] [11:0]; + assign \core_control_regs[15] [31] = \ ; + assign \core_control_regs[15] [30] = \ ; + assign \core_control_regs[15] [29] = \ ; + assign \core_control_regs[15] [28] = \ ; + assign \core_control_regs[15] [27] = \ ; + assign \core_control_regs[15] [26:16] = \^core_control_regs[15] [26:16]; + assign \core_control_regs[15] [15] = \ ; + assign \core_control_regs[15] [14] = \ ; + assign \core_control_regs[15] [13] = \ ; + assign \core_control_regs[15] [12] = \ ; + assign \core_control_regs[15] [11:0] = \^core_control_regs[15] [11:0]; + assign \core_control_regs[16] [31] = \ ; + assign \core_control_regs[16] [30] = \ ; + assign \core_control_regs[16] [29] = \ ; + assign \core_control_regs[16] [28] = \ ; + assign \core_control_regs[16] [27] = \ ; + assign \core_control_regs[16] [26:16] = \^core_control_regs[16] [26:16]; + assign \core_control_regs[16] [15] = \ ; + assign \core_control_regs[16] [14] = \ ; + assign \core_control_regs[16] [13] = \ ; + assign \core_control_regs[16] [12] = \ ; + assign \core_control_regs[16] [11:0] = \^core_control_regs[16] [11:0]; + assign \core_control_regs[1] [31] = \ ; + assign \core_control_regs[1] [30] = \ ; + assign \core_control_regs[1] [29] = \ ; + assign \core_control_regs[1] [28] = \ ; + assign \core_control_regs[1] [27] = \ ; + assign \core_control_regs[1] [26:16] = \^core_control_regs[1] [26:16]; + assign \core_control_regs[1] [15] = \ ; + assign \core_control_regs[1] [14] = \ ; + assign \core_control_regs[1] [13] = \ ; + assign \core_control_regs[1] [12] = \ ; + assign \core_control_regs[1] [11:0] = \^core_control_regs[1] [11:0]; + assign \core_control_regs[2] [31] = \ ; + assign \core_control_regs[2] [30] = \ ; + assign \core_control_regs[2] [29] = \ ; + assign \core_control_regs[2] [28] = \ ; + assign \core_control_regs[2] [27] = \ ; + assign \core_control_regs[2] [26:16] = \^core_control_regs[2] [26:16]; + assign \core_control_regs[2] [15] = \ ; + assign \core_control_regs[2] [14] = \ ; + assign \core_control_regs[2] [13] = \ ; + assign \core_control_regs[2] [12] = \ ; + assign \core_control_regs[2] [11:0] = \^core_control_regs[2] [11:0]; + assign \core_control_regs[3] [31] = \ ; + assign \core_control_regs[3] [30] = \ ; + assign \core_control_regs[3] [29] = \ ; + assign \core_control_regs[3] [28] = \ ; + assign \core_control_regs[3] [27] = \ ; + assign \core_control_regs[3] [26:16] = \^core_control_regs[3] [26:16]; + assign \core_control_regs[3] [15] = \ ; + assign \core_control_regs[3] [14] = \ ; + assign \core_control_regs[3] [13] = \ ; + assign \core_control_regs[3] [12] = \ ; + assign \core_control_regs[3] [11:0] = \^core_control_regs[3] [11:0]; + assign \core_control_regs[4] [31] = \ ; + assign \core_control_regs[4] [30] = \ ; + assign \core_control_regs[4] [29] = \ ; + assign \core_control_regs[4] [28] = \ ; + assign \core_control_regs[4] [27] = \ ; + assign \core_control_regs[4] [26:16] = \^core_control_regs[4] [26:16]; + assign \core_control_regs[4] [15] = \ ; + assign \core_control_regs[4] [14] = \ ; + assign \core_control_regs[4] [13] = \ ; + assign \core_control_regs[4] [12] = \ ; + assign \core_control_regs[4] [11:0] = \^core_control_regs[4] [11:0]; + assign \core_control_regs[5] [31] = \ ; + assign \core_control_regs[5] [30] = \ ; + assign \core_control_regs[5] [29] = \ ; + assign \core_control_regs[5] [28] = \ ; + assign \core_control_regs[5] [27] = \ ; + assign \core_control_regs[5] [26:16] = \^core_control_regs[5] [26:16]; + assign \core_control_regs[5] [15] = \ ; + assign \core_control_regs[5] [14] = \ ; + assign \core_control_regs[5] [13] = \ ; + assign \core_control_regs[5] [12] = \ ; + assign \core_control_regs[5] [11:0] = \^core_control_regs[5] [11:0]; + assign \core_control_regs[6] [31] = \ ; + assign \core_control_regs[6] [30] = \ ; + assign \core_control_regs[6] [29] = \ ; + assign \core_control_regs[6] [28] = \ ; + assign \core_control_regs[6] [27] = \ ; + assign \core_control_regs[6] [26:16] = \^core_control_regs[6] [26:16]; + assign \core_control_regs[6] [15] = \ ; + assign \core_control_regs[6] [14] = \ ; + assign \core_control_regs[6] [13] = \ ; + assign \core_control_regs[6] [12] = \ ; + assign \core_control_regs[6] [11:0] = \^core_control_regs[6] [11:0]; + assign \core_control_regs[7] [31] = \ ; + assign \core_control_regs[7] [30] = \ ; + assign \core_control_regs[7] [29] = \ ; + assign \core_control_regs[7] [28] = \ ; + assign \core_control_regs[7] [27] = \ ; + assign \core_control_regs[7] [26:16] = \^core_control_regs[7] [26:16]; + assign \core_control_regs[7] [15] = \ ; + assign \core_control_regs[7] [14] = \ ; + assign \core_control_regs[7] [13] = \ ; + assign \core_control_regs[7] [12] = \ ; + assign \core_control_regs[7] [11:0] = \^core_control_regs[7] [11:0]; + assign \core_control_regs[8] [31] = \ ; + assign \core_control_regs[8] [30] = \ ; + assign \core_control_regs[8] [29] = \ ; + assign \core_control_regs[8] [28] = \ ; + assign \core_control_regs[8] [27] = \ ; + assign \core_control_regs[8] [26:16] = \^core_control_regs[8] [26:16]; + assign \core_control_regs[8] [15] = \ ; + assign \core_control_regs[8] [14] = \ ; + assign \core_control_regs[8] [13] = \ ; + assign \core_control_regs[8] [12] = \ ; + assign \core_control_regs[8] [11:0] = \^core_control_regs[8] [11:0]; + assign \core_control_regs[9] [31] = \ ; + assign \core_control_regs[9] [30] = \ ; + assign \core_control_regs[9] [29] = \ ; + assign \core_control_regs[9] [28] = \ ; + assign \core_control_regs[9] [27] = \ ; + assign \core_control_regs[9] [26:16] = \^core_control_regs[9] [26:16]; + assign \core_control_regs[9] [15] = \ ; + assign \core_control_regs[9] [14] = \ ; + assign \core_control_regs[9] [13] = \ ; + assign \core_control_regs[9] [12] = \ ; + assign \core_control_regs[9] [11:0] = \^core_control_regs[9] [11:0]; + assign core_d_out = \ ; + assign \genr_control_regs[0] [31:30] = \^genr_control_regs[0] [31:30]; + assign \genr_control_regs[0] [29] = \ ; + assign \genr_control_regs[0] [28] = \ ; + assign \genr_control_regs[0] [27] = \ ; + assign \genr_control_regs[0] [26:13] = \^genr_control_regs[0] [26:13]; + assign \genr_control_regs[0] [12] = \ ; + assign \genr_control_regs[0] [11:8] = \^genr_control_regs[0] [11:8]; + assign \genr_control_regs[0] [7] = \ ; + assign \genr_control_regs[0] [6] = \ ; + assign \genr_control_regs[0] [5] = \^genr_control_regs[0] [5]; + assign \genr_control_regs[0] [4] = \ ; + assign \genr_control_regs[0] [3:0] = \^genr_control_regs[0] [3:0]; + assign \genr_control_regs[1] [31:16] = \^genr_control_regs[1] [31:16]; + assign \genr_control_regs[1] [15] = \ ; + assign \genr_control_regs[1] [14] = \ ; + assign \genr_control_regs[1] [13:8] = \^genr_control_regs[1] [13:8]; + assign \genr_control_regs[1] [7] = \ ; + assign \genr_control_regs[1] [6] = \ ; + assign \genr_control_regs[1] [5] = \ ; + assign \genr_control_regs[1] [4] = \ ; + assign \genr_control_regs[1] [3] = \ ; + assign \genr_control_regs[1] [2] = \ ; + assign \genr_control_regs[1] [1] = \ ; + assign \genr_control_regs[1] [0] = \ ; + assign \genr_control_regs[2] [31] = \ ; + assign \genr_control_regs[2] [30] = \ ; + assign \genr_control_regs[2] [29] = \ ; + assign \genr_control_regs[2] [28] = \ ; + assign \genr_control_regs[2] [27] = \ ; + assign \genr_control_regs[2] [26] = \ ; + assign \genr_control_regs[2] [25] = \ ; + assign \genr_control_regs[2] [24] = \ ; + assign \genr_control_regs[2] [23] = \ ; + assign \genr_control_regs[2] [22] = \ ; + assign \genr_control_regs[2] [21:16] = \^genr_control_regs[2] [21:16]; + assign \genr_control_regs[2] [15] = \ ; + assign \genr_control_regs[2] [14] = \ ; + assign \genr_control_regs[2] [13] = \ ; + assign \genr_control_regs[2] [12] = \ ; + assign \genr_control_regs[2] [11] = \ ; + assign \genr_control_regs[2] [10] = \ ; + assign \genr_control_regs[2] [9] = \ ; + assign \genr_control_regs[2] [8] = \ ; + assign \genr_control_regs[2] [7] = \ ; + assign \genr_control_regs[2] [6] = \ ; + assign \genr_control_regs[2] [5] = \ ; + assign \genr_control_regs[2] [4] = \ ; + assign \genr_control_regs[2] [3] = \ ; + assign \genr_control_regs[2] [2] = \ ; + assign \genr_control_regs[2] [1] = \ ; + assign \genr_control_regs[2] [0] = \ ; + assign \genr_control_regs[3] [31:16] = \^genr_control_regs[3] [31:16]; + assign \genr_control_regs[3] [15] = \ ; + assign \genr_control_regs[3] [14] = \ ; + assign \genr_control_regs[3] [13:8] = \^genr_control_regs[3] [13:8]; + assign \genr_control_regs[3] [7] = \ ; + assign \genr_control_regs[3] [6] = \ ; + assign \genr_control_regs[3] [5] = \ ; + assign \genr_control_regs[3] [4] = \ ; + assign \genr_control_regs[3] [3] = \ ; + assign \genr_control_regs[3] [2] = \ ; + assign \genr_control_regs[3] [1] = \ ; + assign \genr_control_regs[3] [0] = \ ; + assign \genr_control_regs[4] [31] = \ ; + assign \genr_control_regs[4] [30] = \ ; + assign \genr_control_regs[4] [29] = \ ; + assign \genr_control_regs[4] [28] = \ ; + assign \genr_control_regs[4] [27] = \ ; + assign \genr_control_regs[4] [26] = \ ; + assign \genr_control_regs[4] [25] = \ ; + assign \genr_control_regs[4] [24] = \ ; + assign \genr_control_regs[4] [23] = \ ; + assign \genr_control_regs[4] [22] = \ ; + assign \genr_control_regs[4] [21] = \ ; + assign \genr_control_regs[4] [20] = \ ; + assign \genr_control_regs[4] [19] = \ ; + assign \genr_control_regs[4] [18] = \ ; + assign \genr_control_regs[4] [17] = \ ; + assign \genr_control_regs[4] [16] = \ ; + assign \genr_control_regs[4] [15] = \ ; + assign \genr_control_regs[4] [14] = \ ; + assign \genr_control_regs[4] [13] = \ ; + assign \genr_control_regs[4] [12] = \ ; + assign \genr_control_regs[4] [11] = \ ; + assign \genr_control_regs[4] [10] = \ ; + assign \genr_control_regs[4] [9] = \ ; + assign \genr_control_regs[4] [8] = \ ; + assign \genr_control_regs[4] [7] = \ ; + assign \genr_control_regs[4] [6] = \ ; + assign \genr_control_regs[4] [5] = \ ; + assign \genr_control_regs[4] [4] = \ ; + assign \genr_control_regs[4] [3] = \ ; + assign \genr_control_regs[4] [2] = \ ; + assign \genr_control_regs[4] [1] = \ ; + assign \genr_control_regs[4] [0] = \ ; + assign ipif_addr_out[8:0] = ipif_Addr; + assign s_axi_awready = s_axi_wready; + assign s_axi_bresp[1] = \^s_axi_bresp [1]; + assign s_axi_bresp[0] = \ ; + assign s_axi_rresp[1] = \^s_axi_rresp [1]; + assign s_axi_rresp[0] = \ ; + assign \time_control_regs[0] [31] = \ ; + assign \time_control_regs[0] [30] = \ ; + assign \time_control_regs[0] [29] = \ ; + assign \time_control_regs[0] [28] = \ ; + assign \time_control_regs[0] [27] = \ ; + assign \time_control_regs[0] [26] = \ ; + assign \time_control_regs[0] [25] = \ ; + assign \time_control_regs[0] [24] = \ ; + assign \time_control_regs[0] [23] = \ ; + assign \time_control_regs[0] [22] = \ ; + assign \time_control_regs[0] [21] = \ ; + assign \time_control_regs[0] [20] = \ ; + assign \time_control_regs[0] [19] = \ ; + assign \time_control_regs[0] [18] = \ ; + assign \time_control_regs[0] [17] = \ ; + assign \time_control_regs[0] [16] = \ ; + assign \time_control_regs[0] [15] = \ ; + assign \time_control_regs[0] [14] = \ ; + assign \time_control_regs[0] [13] = \ ; + assign \time_control_regs[0] [12] = \ ; + assign \time_control_regs[0] [11] = \ ; + assign \time_control_regs[0] [10] = \ ; + assign \time_control_regs[0] [9] = \ ; + assign \time_control_regs[0] [8] = \ ; + assign \time_control_regs[0] [7] = \ ; + assign \time_control_regs[0] [6] = \ ; + assign \time_control_regs[0] [5] = \ ; + assign \time_control_regs[0] [4] = \ ; + assign \time_control_regs[0] [3] = \ ; + assign \time_control_regs[0] [2] = \ ; + assign \time_control_regs[0] [1] = \ ; + assign \time_control_regs[0] [0] = \ ; + assign \time_control_regs[10] [31] = \ ; + assign \time_control_regs[10] [30] = \ ; + assign \time_control_regs[10] [29] = \ ; + assign \time_control_regs[10] [28] = \ ; + assign \time_control_regs[10] [27] = \ ; + assign \time_control_regs[10] [26] = \ ; + assign \time_control_regs[10] [25] = \ ; + assign \time_control_regs[10] [24] = \ ; + assign \time_control_regs[10] [23] = \ ; + assign \time_control_regs[10] [22] = \ ; + assign \time_control_regs[10] [21] = \ ; + assign \time_control_regs[10] [20] = \ ; + assign \time_control_regs[10] [19] = \ ; + assign \time_control_regs[10] [18] = \ ; + assign \time_control_regs[10] [17] = \ ; + assign \time_control_regs[10] [16] = \ ; + assign \time_control_regs[10] [15] = \ ; + assign \time_control_regs[10] [14] = \ ; + assign \time_control_regs[10] [13] = \ ; + assign \time_control_regs[10] [12] = \ ; + assign \time_control_regs[10] [11] = \ ; + assign \time_control_regs[10] [10] = \ ; + assign \time_control_regs[10] [9] = \ ; + assign \time_control_regs[10] [8] = \ ; + assign \time_control_regs[10] [7] = \ ; + assign \time_control_regs[10] [6] = \ ; + assign \time_control_regs[10] [5] = \ ; + assign \time_control_regs[10] [4] = \ ; + assign \time_control_regs[10] [3] = \ ; + assign \time_control_regs[10] [2] = \ ; + assign \time_control_regs[10] [1] = \ ; + assign \time_control_regs[10] [0] = \ ; + assign \time_control_regs[11] [31] = \ ; + assign \time_control_regs[11] [30] = \ ; + assign \time_control_regs[11] [29] = \ ; + assign \time_control_regs[11] [28] = \ ; + assign \time_control_regs[11] [27] = \ ; + assign \time_control_regs[11] [26] = \ ; + assign \time_control_regs[11] [25] = \ ; + assign \time_control_regs[11] [24] = \ ; + assign \time_control_regs[11] [23] = \ ; + assign \time_control_regs[11] [22] = \ ; + assign \time_control_regs[11] [21] = \ ; + assign \time_control_regs[11] [20] = \ ; + assign \time_control_regs[11] [19] = \ ; + assign \time_control_regs[11] [18] = \ ; + assign \time_control_regs[11] [17] = \ ; + assign \time_control_regs[11] [16] = \ ; + assign \time_control_regs[11] [15] = \ ; + assign \time_control_regs[11] [14] = \ ; + assign \time_control_regs[11] [13] = \ ; + assign \time_control_regs[11] [12] = \ ; + assign \time_control_regs[11] [11] = \ ; + assign \time_control_regs[11] [10] = \ ; + assign \time_control_regs[11] [9] = \ ; + assign \time_control_regs[11] [8] = \ ; + assign \time_control_regs[11] [7] = \ ; + assign \time_control_regs[11] [6] = \ ; + assign \time_control_regs[11] [5] = \ ; + assign \time_control_regs[11] [4] = \ ; + assign \time_control_regs[11] [3] = \ ; + assign \time_control_regs[11] [2] = \ ; + assign \time_control_regs[11] [1] = \ ; + assign \time_control_regs[11] [0] = \ ; + assign \time_control_regs[12] [31] = \ ; + assign \time_control_regs[12] [30] = \ ; + assign \time_control_regs[12] [29] = \ ; + assign \time_control_regs[12] [28] = \ ; + assign \time_control_regs[12] [27] = \ ; + assign \time_control_regs[12] [26] = \ ; + assign \time_control_regs[12] [25] = \ ; + assign \time_control_regs[12] [24] = \ ; + assign \time_control_regs[12] [23] = \ ; + assign \time_control_regs[12] [22] = \ ; + assign \time_control_regs[12] [21] = \ ; + assign \time_control_regs[12] [20] = \ ; + assign \time_control_regs[12] [19] = \ ; + assign \time_control_regs[12] [18] = \ ; + assign \time_control_regs[12] [17] = \ ; + assign \time_control_regs[12] [16] = \ ; + assign \time_control_regs[12] [15] = \ ; + assign \time_control_regs[12] [14] = \ ; + assign \time_control_regs[12] [13] = \ ; + assign \time_control_regs[12] [12] = \ ; + assign \time_control_regs[12] [11] = \ ; + assign \time_control_regs[12] [10] = \ ; + assign \time_control_regs[12] [9] = \ ; + assign \time_control_regs[12] [8] = \ ; + assign \time_control_regs[12] [7] = \ ; + assign \time_control_regs[12] [6] = \ ; + assign \time_control_regs[12] [5] = \ ; + assign \time_control_regs[12] [4] = \ ; + assign \time_control_regs[12] [3] = \ ; + assign \time_control_regs[12] [2] = \ ; + assign \time_control_regs[12] [1] = \ ; + assign \time_control_regs[12] [0] = \ ; + assign \time_control_regs[13] [31] = \ ; + assign \time_control_regs[13] [30] = \ ; + assign \time_control_regs[13] [29] = \ ; + assign \time_control_regs[13] [28] = \ ; + assign \time_control_regs[13] [27] = \ ; + assign \time_control_regs[13] [26] = \ ; + assign \time_control_regs[13] [25] = \ ; + assign \time_control_regs[13] [24] = \ ; + assign \time_control_regs[13] [23] = \ ; + assign \time_control_regs[13] [22] = \ ; + assign \time_control_regs[13] [21] = \ ; + assign \time_control_regs[13] [20] = \ ; + assign \time_control_regs[13] [19] = \ ; + assign \time_control_regs[13] [18] = \ ; + assign \time_control_regs[13] [17] = \ ; + assign \time_control_regs[13] [16] = \ ; + assign \time_control_regs[13] [15] = \ ; + assign \time_control_regs[13] [14] = \ ; + assign \time_control_regs[13] [13] = \ ; + assign \time_control_regs[13] [12] = \ ; + assign \time_control_regs[13] [11] = \ ; + assign \time_control_regs[13] [10] = \ ; + assign \time_control_regs[13] [9] = \ ; + assign \time_control_regs[13] [8] = \ ; + assign \time_control_regs[13] [7] = \ ; + assign \time_control_regs[13] [6] = \ ; + assign \time_control_regs[13] [5] = \ ; + assign \time_control_regs[13] [4] = \ ; + assign \time_control_regs[13] [3] = \ ; + assign \time_control_regs[13] [2] = \ ; + assign \time_control_regs[13] [1] = \ ; + assign \time_control_regs[13] [0] = \ ; + assign \time_control_regs[14] [31] = \ ; + assign \time_control_regs[14] [30] = \ ; + assign \time_control_regs[14] [29] = \ ; + assign \time_control_regs[14] [28] = \ ; + assign \time_control_regs[14] [27] = \ ; + assign \time_control_regs[14] [26] = \ ; + assign \time_control_regs[14] [25] = \ ; + assign \time_control_regs[14] [24] = \ ; + assign \time_control_regs[14] [23] = \ ; + assign \time_control_regs[14] [22] = \ ; + assign \time_control_regs[14] [21] = \ ; + assign \time_control_regs[14] [20] = \ ; + assign \time_control_regs[14] [19] = \ ; + assign \time_control_regs[14] [18] = \ ; + assign \time_control_regs[14] [17] = \ ; + assign \time_control_regs[14] [16] = \ ; + assign \time_control_regs[14] [15] = \ ; + assign \time_control_regs[14] [14] = \ ; + assign \time_control_regs[14] [13] = \ ; + assign \time_control_regs[14] [12] = \ ; + assign \time_control_regs[14] [11] = \ ; + assign \time_control_regs[14] [10] = \ ; + assign \time_control_regs[14] [9] = \ ; + assign \time_control_regs[14] [8] = \ ; + assign \time_control_regs[14] [7] = \ ; + assign \time_control_regs[14] [6] = \ ; + assign \time_control_regs[14] [5] = \ ; + assign \time_control_regs[14] [4] = \ ; + assign \time_control_regs[14] [3] = \ ; + assign \time_control_regs[14] [2] = \ ; + assign \time_control_regs[14] [1] = \ ; + assign \time_control_regs[14] [0] = \ ; + assign \time_control_regs[15] [31] = \ ; + assign \time_control_regs[15] [30] = \ ; + assign \time_control_regs[15] [29] = \ ; + assign \time_control_regs[15] [28] = \ ; + assign \time_control_regs[15] [27] = \ ; + assign \time_control_regs[15] [26] = \ ; + assign \time_control_regs[15] [25] = \ ; + assign \time_control_regs[15] [24] = \ ; + assign \time_control_regs[15] [23] = \ ; + assign \time_control_regs[15] [22] = \ ; + assign \time_control_regs[15] [21] = \ ; + assign \time_control_regs[15] [20] = \ ; + assign \time_control_regs[15] [19] = \ ; + assign \time_control_regs[15] [18] = \ ; + assign \time_control_regs[15] [17] = \ ; + assign \time_control_regs[15] [16] = \ ; + assign \time_control_regs[15] [15] = \ ; + assign \time_control_regs[15] [14] = \ ; + assign \time_control_regs[15] [13] = \ ; + assign \time_control_regs[15] [12] = \ ; + assign \time_control_regs[15] [11] = \ ; + assign \time_control_regs[15] [10] = \ ; + assign \time_control_regs[15] [9] = \ ; + assign \time_control_regs[15] [8] = \ ; + assign \time_control_regs[15] [7] = \ ; + assign \time_control_regs[15] [6] = \ ; + assign \time_control_regs[15] [5] = \ ; + assign \time_control_regs[15] [4] = \ ; + assign \time_control_regs[15] [3] = \ ; + assign \time_control_regs[15] [2] = \ ; + assign \time_control_regs[15] [1] = \ ; + assign \time_control_regs[15] [0] = \ ; + assign \time_control_regs[16] [31] = \ ; + assign \time_control_regs[16] [30] = \ ; + assign \time_control_regs[16] [29] = \ ; + assign \time_control_regs[16] [28:16] = \^time_control_regs[16] [28:16]; + assign \time_control_regs[16] [15] = \ ; + assign \time_control_regs[16] [14] = \ ; + assign \time_control_regs[16] [13] = \ ; + assign \time_control_regs[16] [12:0] = \^time_control_regs[16] [12:0]; + assign \time_control_regs[17] [31] = \ ; + assign \time_control_regs[17] [30] = \ ; + assign \time_control_regs[17] [29] = \ ; + assign \time_control_regs[17] [28] = \ ; + assign \time_control_regs[17] [27] = \ ; + assign \time_control_regs[17] [26] = \ ; + assign \time_control_regs[17] [25] = \ ; + assign \time_control_regs[17] [24] = \ ; + assign \time_control_regs[17] [23] = \ ; + assign \time_control_regs[17] [22] = \ ; + assign \time_control_regs[17] [21] = \ ; + assign \time_control_regs[17] [20] = \ ; + assign \time_control_regs[17] [19] = \ ; + assign \time_control_regs[17] [18] = \ ; + assign \time_control_regs[17] [17] = \ ; + assign \time_control_regs[17] [16] = \ ; + assign \time_control_regs[17] [15] = \ ; + assign \time_control_regs[17] [14] = \ ; + assign \time_control_regs[17] [13] = \ ; + assign \time_control_regs[17] [12] = \ ; + assign \time_control_regs[17] [11] = \ ; + assign \time_control_regs[17] [10] = \ ; + assign \time_control_regs[17] [9] = \ ; + assign \time_control_regs[17] [8] = \ ; + assign \time_control_regs[17] [7] = \ ; + assign \time_control_regs[17] [6] = \ ; + assign \time_control_regs[17] [5] = \ ; + assign \time_control_regs[17] [4] = \ ; + assign \time_control_regs[17] [3] = \ ; + assign \time_control_regs[17] [2] = \ ; + assign \time_control_regs[17] [1] = \ ; + assign \time_control_regs[17] [0] = \ ; + assign \time_control_regs[18] [31] = \ ; + assign \time_control_regs[18] [30] = \ ; + assign \time_control_regs[18] [29] = \ ; + assign \time_control_regs[18] [28] = \ ; + assign \time_control_regs[18] [27] = \ ; + assign \time_control_regs[18] [26] = \ ; + assign \time_control_regs[18] [25] = \ ; + assign \time_control_regs[18] [24] = \ ; + assign \time_control_regs[18] [23] = \ ; + assign \time_control_regs[18] [22] = \ ; + assign \time_control_regs[18] [21] = \ ; + assign \time_control_regs[18] [20] = \ ; + assign \time_control_regs[18] [19] = \ ; + assign \time_control_regs[18] [18] = \ ; + assign \time_control_regs[18] [17] = \ ; + assign \time_control_regs[18] [16] = \ ; + assign \time_control_regs[18] [15] = \ ; + assign \time_control_regs[18] [14] = \ ; + assign \time_control_regs[18] [13] = \ ; + assign \time_control_regs[18] [12] = \ ; + assign \time_control_regs[18] [11] = \ ; + assign \time_control_regs[18] [10] = \ ; + assign \time_control_regs[18] [9:6] = \^time_control_regs[18] [9:6]; + assign \time_control_regs[18] [5] = \ ; + assign \time_control_regs[18] [4] = \ ; + assign \time_control_regs[18] [3:0] = \^time_control_regs[18] [3:0]; + assign \time_control_regs[19] [31] = \ ; + assign \time_control_regs[19] [30] = \ ; + assign \time_control_regs[19] [29] = \ ; + assign \time_control_regs[19] [28] = \ ; + assign \time_control_regs[19] [27] = \ ; + assign \time_control_regs[19] [26] = \ ; + assign \time_control_regs[19] [25] = \ ; + assign \time_control_regs[19] [24] = \ ; + assign \time_control_regs[19] [23] = \ ; + assign \time_control_regs[19] [22] = \ ; + assign \time_control_regs[19] [21] = \ ; + assign \time_control_regs[19] [20] = \ ; + assign \time_control_regs[19] [19] = \ ; + assign \time_control_regs[19] [18] = \ ; + assign \time_control_regs[19] [17] = \ ; + assign \time_control_regs[19] [16] = \ ; + assign \time_control_regs[19] [15] = \ ; + assign \time_control_regs[19] [14] = \ ; + assign \time_control_regs[19] [13] = \ ; + assign \time_control_regs[19] [12] = \ ; + assign \time_control_regs[19] [11] = \ ; + assign \time_control_regs[19] [10] = \ ; + assign \time_control_regs[19] [9] = \ ; + assign \time_control_regs[19] [8] = \ ; + assign \time_control_regs[19] [7] = \ ; + assign \time_control_regs[19] [6:0] = \^time_control_regs[19] [6:0]; + assign \time_control_regs[1] [31] = \ ; + assign \time_control_regs[1] [30] = \ ; + assign \time_control_regs[1] [29] = \ ; + assign \time_control_regs[1] [28] = \ ; + assign \time_control_regs[1] [27] = \ ; + assign \time_control_regs[1] [26] = \ ; + assign \time_control_regs[1] [25] = \ ; + assign \time_control_regs[1] [24] = \ ; + assign \time_control_regs[1] [23] = \ ; + assign \time_control_regs[1] [22] = \ ; + assign \time_control_regs[1] [21] = \ ; + assign \time_control_regs[1] [20] = \ ; + assign \time_control_regs[1] [19] = \ ; + assign \time_control_regs[1] [18] = \ ; + assign \time_control_regs[1] [17] = \ ; + assign \time_control_regs[1] [16] = \ ; + assign \time_control_regs[1] [15] = \ ; + assign \time_control_regs[1] [14] = \ ; + assign \time_control_regs[1] [13] = \ ; + assign \time_control_regs[1] [12] = \ ; + assign \time_control_regs[1] [11] = \ ; + assign \time_control_regs[1] [10] = \ ; + assign \time_control_regs[1] [9] = \ ; + assign \time_control_regs[1] [8] = \ ; + assign \time_control_regs[1] [7] = \ ; + assign \time_control_regs[1] [6] = \ ; + assign \time_control_regs[1] [5] = \ ; + assign \time_control_regs[1] [4] = \ ; + assign \time_control_regs[1] [3] = \ ; + assign \time_control_regs[1] [2] = \ ; + assign \time_control_regs[1] [1] = \ ; + assign \time_control_regs[1] [0] = \ ; + assign \time_control_regs[20] [31] = \ ; + assign \time_control_regs[20] [30] = \ ; + assign \time_control_regs[20] [29] = \ ; + assign \time_control_regs[20] [28:16] = \^time_control_regs[20] [28:16]; + assign \time_control_regs[20] [15] = \ ; + assign \time_control_regs[20] [14] = \ ; + assign \time_control_regs[20] [13] = \ ; + assign \time_control_regs[20] [12:0] = \^time_control_regs[20] [12:0]; + assign \time_control_regs[21] [31] = \ ; + assign \time_control_regs[21] [30] = \ ; + assign \time_control_regs[21] [29] = \ ; + assign \time_control_regs[21] [28:16] = \^time_control_regs[21] [28:16]; + assign \time_control_regs[21] [15] = \ ; + assign \time_control_regs[21] [14] = \ ; + assign \time_control_regs[21] [13] = \ ; + assign \time_control_regs[21] [12:0] = \^time_control_regs[21] [12:0]; + assign \time_control_regs[22] [31] = \ ; + assign \time_control_regs[22] [30] = \ ; + assign \time_control_regs[22] [29] = \ ; + assign \time_control_regs[22] [28:16] = \^time_control_regs[22] [28:16]; + assign \time_control_regs[22] [15] = \ ; + assign \time_control_regs[22] [14] = \ ; + assign \time_control_regs[22] [13] = \ ; + assign \time_control_regs[22] [12:0] = \^time_control_regs[22] [12:0]; + assign \time_control_regs[23] [31] = \ ; + assign \time_control_regs[23] [30] = \ ; + assign \time_control_regs[23] [29] = \ ; + assign \time_control_regs[23] [28:16] = \^time_control_regs[23] [28:16]; + assign \time_control_regs[23] [15] = \ ; + assign \time_control_regs[23] [14] = \ ; + assign \time_control_regs[23] [13] = \ ; + assign \time_control_regs[23] [12:0] = \^time_control_regs[23] [12:0]; + assign \time_control_regs[24] [31] = \ ; + assign \time_control_regs[24] [30] = \ ; + assign \time_control_regs[24] [29] = \ ; + assign \time_control_regs[24] [28:16] = \^time_control_regs[24] [28:16]; + assign \time_control_regs[24] [15] = \ ; + assign \time_control_regs[24] [14] = \ ; + assign \time_control_regs[24] [13] = \ ; + assign \time_control_regs[24] [12:0] = \^time_control_regs[24] [12:0]; + assign \time_control_regs[25] [31] = \ ; + assign \time_control_regs[25] [30] = \ ; + assign \time_control_regs[25] [29] = \ ; + assign \time_control_regs[25] [28:16] = \^time_control_regs[25] [28:16]; + assign \time_control_regs[25] [15] = \ ; + assign \time_control_regs[25] [14] = \ ; + assign \time_control_regs[25] [13] = \ ; + assign \time_control_regs[25] [12:0] = \^time_control_regs[25] [12:0]; + assign \time_control_regs[26] [31] = \ ; + assign \time_control_regs[26] [30] = \ ; + assign \time_control_regs[26] [29] = \ ; + assign \time_control_regs[26] [28:16] = \^time_control_regs[26] [28:16]; + assign \time_control_regs[26] [15] = \ ; + assign \time_control_regs[26] [14] = \ ; + assign \time_control_regs[26] [13] = \ ; + assign \time_control_regs[26] [12:0] = \^time_control_regs[26] [12:0]; + assign \time_control_regs[27] [31] = \ ; + assign \time_control_regs[27] [30] = \ ; + assign \time_control_regs[27] [29] = \ ; + assign \time_control_regs[27] [28:16] = \^time_control_regs[27] [28:16]; + assign \time_control_regs[27] [15] = \ ; + assign \time_control_regs[27] [14] = \ ; + assign \time_control_regs[27] [13] = \ ; + assign \time_control_regs[27] [12:0] = \^time_control_regs[27] [12:0]; + assign \time_control_regs[28] [31] = \ ; + assign \time_control_regs[28] [30] = \ ; + assign \time_control_regs[28] [29] = \ ; + assign \time_control_regs[28] [28:16] = \^time_control_regs[28] [28:16]; + assign \time_control_regs[28] [15] = \ ; + assign \time_control_regs[28] [14] = \ ; + assign \time_control_regs[28] [13] = \ ; + assign \time_control_regs[28] [12:0] = \^time_control_regs[28] [12:0]; + assign \time_control_regs[2] [31] = \ ; + assign \time_control_regs[2] [30] = \ ; + assign \time_control_regs[2] [29] = \ ; + assign \time_control_regs[2] [28] = \ ; + assign \time_control_regs[2] [27] = \ ; + assign \time_control_regs[2] [26] = \ ; + assign \time_control_regs[2] [25] = \ ; + assign \time_control_regs[2] [24] = \ ; + assign \time_control_regs[2] [23] = \ ; + assign \time_control_regs[2] [22] = \ ; + assign \time_control_regs[2] [21] = \ ; + assign \time_control_regs[2] [20] = \ ; + assign \time_control_regs[2] [19] = \ ; + assign \time_control_regs[2] [18] = \ ; + assign \time_control_regs[2] [17] = \ ; + assign \time_control_regs[2] [16] = \ ; + assign \time_control_regs[2] [15] = \ ; + assign \time_control_regs[2] [14] = \ ; + assign \time_control_regs[2] [13] = \ ; + assign \time_control_regs[2] [12] = \ ; + assign \time_control_regs[2] [11] = \ ; + assign \time_control_regs[2] [10] = \ ; + assign \time_control_regs[2] [9] = \ ; + assign \time_control_regs[2] [8] = \ ; + assign \time_control_regs[2] [7] = \ ; + assign \time_control_regs[2] [6] = \ ; + assign \time_control_regs[2] [5] = \ ; + assign \time_control_regs[2] [4] = \ ; + assign \time_control_regs[2] [3] = \ ; + assign \time_control_regs[2] [2] = \ ; + assign \time_control_regs[2] [1] = \ ; + assign \time_control_regs[2] [0] = \ ; + assign \time_control_regs[3] [31] = \ ; + assign \time_control_regs[3] [30] = \ ; + assign \time_control_regs[3] [29] = \ ; + assign \time_control_regs[3] [28] = \ ; + assign \time_control_regs[3] [27] = \ ; + assign \time_control_regs[3] [26] = \ ; + assign \time_control_regs[3] [25] = \ ; + assign \time_control_regs[3] [24] = \ ; + assign \time_control_regs[3] [23] = \ ; + assign \time_control_regs[3] [22] = \ ; + assign \time_control_regs[3] [21] = \ ; + assign \time_control_regs[3] [20] = \ ; + assign \time_control_regs[3] [19] = \ ; + assign \time_control_regs[3] [18] = \ ; + assign \time_control_regs[3] [17] = \ ; + assign \time_control_regs[3] [16] = \ ; + assign \time_control_regs[3] [15] = \ ; + assign \time_control_regs[3] [14] = \ ; + assign \time_control_regs[3] [13] = \ ; + assign \time_control_regs[3] [12] = \ ; + assign \time_control_regs[3] [11] = \ ; + assign \time_control_regs[3] [10] = \ ; + assign \time_control_regs[3] [9] = \ ; + assign \time_control_regs[3] [8] = \ ; + assign \time_control_regs[3] [7] = \ ; + assign \time_control_regs[3] [6] = \ ; + assign \time_control_regs[3] [5] = \ ; + assign \time_control_regs[3] [4] = \ ; + assign \time_control_regs[3] [3] = \ ; + assign \time_control_regs[3] [2] = \ ; + assign \time_control_regs[3] [1] = \ ; + assign \time_control_regs[3] [0] = \ ; + assign \time_control_regs[4] [31] = \ ; + assign \time_control_regs[4] [30] = \ ; + assign \time_control_regs[4] [29] = \ ; + assign \time_control_regs[4] [28] = \ ; + assign \time_control_regs[4] [27] = \ ; + assign \time_control_regs[4] [26] = \ ; + assign \time_control_regs[4] [25] = \ ; + assign \time_control_regs[4] [24] = \ ; + assign \time_control_regs[4] [23] = \ ; + assign \time_control_regs[4] [22] = \ ; + assign \time_control_regs[4] [21] = \ ; + assign \time_control_regs[4] [20] = \ ; + assign \time_control_regs[4] [19] = \ ; + assign \time_control_regs[4] [18] = \ ; + assign \time_control_regs[4] [17] = \ ; + assign \time_control_regs[4] [16] = \ ; + assign \time_control_regs[4] [15] = \ ; + assign \time_control_regs[4] [14] = \ ; + assign \time_control_regs[4] [13] = \ ; + assign \time_control_regs[4] [12] = \ ; + assign \time_control_regs[4] [11] = \ ; + assign \time_control_regs[4] [10] = \ ; + assign \time_control_regs[4] [9] = \ ; + assign \time_control_regs[4] [8] = \ ; + assign \time_control_regs[4] [7] = \ ; + assign \time_control_regs[4] [6] = \ ; + assign \time_control_regs[4] [5] = \ ; + assign \time_control_regs[4] [4] = \ ; + assign \time_control_regs[4] [3] = \ ; + assign \time_control_regs[4] [2] = \ ; + assign \time_control_regs[4] [1] = \ ; + assign \time_control_regs[4] [0] = \ ; + assign \time_control_regs[5] [31] = \ ; + assign \time_control_regs[5] [30] = \ ; + assign \time_control_regs[5] [29] = \ ; + assign \time_control_regs[5] [28] = \ ; + assign \time_control_regs[5] [27] = \ ; + assign \time_control_regs[5] [26] = \ ; + assign \time_control_regs[5] [25] = \ ; + assign \time_control_regs[5] [24] = \ ; + assign \time_control_regs[5] [23] = \ ; + assign \time_control_regs[5] [22] = \ ; + assign \time_control_regs[5] [21] = \ ; + assign \time_control_regs[5] [20] = \ ; + assign \time_control_regs[5] [19] = \ ; + assign \time_control_regs[5] [18] = \ ; + assign \time_control_regs[5] [17] = \ ; + assign \time_control_regs[5] [16] = \ ; + assign \time_control_regs[5] [15] = \ ; + assign \time_control_regs[5] [14] = \ ; + assign \time_control_regs[5] [13] = \ ; + assign \time_control_regs[5] [12] = \ ; + assign \time_control_regs[5] [11] = \ ; + assign \time_control_regs[5] [10] = \ ; + assign \time_control_regs[5] [9] = \ ; + assign \time_control_regs[5] [8] = \ ; + assign \time_control_regs[5] [7] = \ ; + assign \time_control_regs[5] [6] = \ ; + assign \time_control_regs[5] [5] = \ ; + assign \time_control_regs[5] [4] = \ ; + assign \time_control_regs[5] [3] = \ ; + assign \time_control_regs[5] [2] = \ ; + assign \time_control_regs[5] [1] = \ ; + assign \time_control_regs[5] [0] = \ ; + assign \time_control_regs[6] [31] = \ ; + assign \time_control_regs[6] [30] = \ ; + assign \time_control_regs[6] [29] = \ ; + assign \time_control_regs[6] [28] = \ ; + assign \time_control_regs[6] [27] = \ ; + assign \time_control_regs[6] [26] = \ ; + assign \time_control_regs[6] [25] = \ ; + assign \time_control_regs[6] [24] = \ ; + assign \time_control_regs[6] [23] = \ ; + assign \time_control_regs[6] [22] = \ ; + assign \time_control_regs[6] [21] = \ ; + assign \time_control_regs[6] [20] = \ ; + assign \time_control_regs[6] [19] = \ ; + assign \time_control_regs[6] [18] = \ ; + assign \time_control_regs[6] [17] = \ ; + assign \time_control_regs[6] [16] = \ ; + assign \time_control_regs[6] [15] = \ ; + assign \time_control_regs[6] [14] = \ ; + assign \time_control_regs[6] [13] = \ ; + assign \time_control_regs[6] [12] = \ ; + assign \time_control_regs[6] [11] = \ ; + assign \time_control_regs[6] [10] = \ ; + assign \time_control_regs[6] [9] = \ ; + assign \time_control_regs[6] [8] = \ ; + assign \time_control_regs[6] [7] = \ ; + assign \time_control_regs[6] [6] = \ ; + assign \time_control_regs[6] [5] = \ ; + assign \time_control_regs[6] [4] = \ ; + assign \time_control_regs[6] [3] = \ ; + assign \time_control_regs[6] [2] = \ ; + assign \time_control_regs[6] [1] = \ ; + assign \time_control_regs[6] [0] = \ ; + assign \time_control_regs[7] [31] = \ ; + assign \time_control_regs[7] [30] = \ ; + assign \time_control_regs[7] [29] = \ ; + assign \time_control_regs[7] [28] = \ ; + assign \time_control_regs[7] [27] = \ ; + assign \time_control_regs[7] [26] = \ ; + assign \time_control_regs[7] [25] = \ ; + assign \time_control_regs[7] [24] = \ ; + assign \time_control_regs[7] [23] = \ ; + assign \time_control_regs[7] [22] = \ ; + assign \time_control_regs[7] [21] = \ ; + assign \time_control_regs[7] [20] = \ ; + assign \time_control_regs[7] [19] = \ ; + assign \time_control_regs[7] [18] = \ ; + assign \time_control_regs[7] [17] = \ ; + assign \time_control_regs[7] [16] = \ ; + assign \time_control_regs[7] [15] = \ ; + assign \time_control_regs[7] [14] = \ ; + assign \time_control_regs[7] [13] = \ ; + assign \time_control_regs[7] [12] = \ ; + assign \time_control_regs[7] [11] = \ ; + assign \time_control_regs[7] [10] = \ ; + assign \time_control_regs[7] [9] = \ ; + assign \time_control_regs[7] [8] = \ ; + assign \time_control_regs[7] [7] = \ ; + assign \time_control_regs[7] [6] = \ ; + assign \time_control_regs[7] [5] = \ ; + assign \time_control_regs[7] [4] = \ ; + assign \time_control_regs[7] [3] = \ ; + assign \time_control_regs[7] [2] = \ ; + assign \time_control_regs[7] [1] = \ ; + assign \time_control_regs[7] [0] = \ ; + assign \time_control_regs[8] [31] = \ ; + assign \time_control_regs[8] [30] = \ ; + assign \time_control_regs[8] [29] = \ ; + assign \time_control_regs[8] [28] = \ ; + assign \time_control_regs[8] [27] = \ ; + assign \time_control_regs[8] [26] = \ ; + assign \time_control_regs[8] [25] = \ ; + assign \time_control_regs[8] [24] = \ ; + assign \time_control_regs[8] [23] = \ ; + assign \time_control_regs[8] [22] = \ ; + assign \time_control_regs[8] [21] = \ ; + assign \time_control_regs[8] [20] = \ ; + assign \time_control_regs[8] [19] = \ ; + assign \time_control_regs[8] [18] = \ ; + assign \time_control_regs[8] [17] = \ ; + assign \time_control_regs[8] [16] = \ ; + assign \time_control_regs[8] [15] = \ ; + assign \time_control_regs[8] [14] = \ ; + assign \time_control_regs[8] [13] = \ ; + assign \time_control_regs[8] [12] = \ ; + assign \time_control_regs[8] [11] = \ ; + assign \time_control_regs[8] [10] = \ ; + assign \time_control_regs[8] [9] = \ ; + assign \time_control_regs[8] [8] = \ ; + assign \time_control_regs[8] [7] = \ ; + assign \time_control_regs[8] [6] = \ ; + assign \time_control_regs[8] [5] = \ ; + assign \time_control_regs[8] [4] = \ ; + assign \time_control_regs[8] [3] = \ ; + assign \time_control_regs[8] [2] = \ ; + assign \time_control_regs[8] [1] = \ ; + assign \time_control_regs[8] [0] = \ ; + assign \time_control_regs[9] [31] = \ ; + assign \time_control_regs[9] [30] = \ ; + assign \time_control_regs[9] [29] = \ ; + assign \time_control_regs[9] [28] = \ ; + assign \time_control_regs[9] [27] = \ ; + assign \time_control_regs[9] [26] = \ ; + assign \time_control_regs[9] [25] = \ ; + assign \time_control_regs[9] [24] = \ ; + assign \time_control_regs[9] [23] = \ ; + assign \time_control_regs[9] [22] = \ ; + assign \time_control_regs[9] [21] = \ ; + assign \time_control_regs[9] [20] = \ ; + assign \time_control_regs[9] [19] = \ ; + assign \time_control_regs[9] [18] = \ ; + assign \time_control_regs[9] [17] = \ ; + assign \time_control_regs[9] [16] = \ ; + assign \time_control_regs[9] [15] = \ ; + assign \time_control_regs[9] [14] = \ ; + assign \time_control_regs[9] [13] = \ ; + assign \time_control_regs[9] [12] = \ ; + assign \time_control_regs[9] [11] = \ ; + assign \time_control_regs[9] [10] = \ ; + assign \time_control_regs[9] [9] = \ ; + assign \time_control_regs[9] [8] = \ ; + assign \time_control_regs[9] [7] = \ ; + assign \time_control_regs[9] [6] = \ ; + assign \time_control_regs[9] [5] = \ ; + assign \time_control_regs[9] [4] = \ ; + assign \time_control_regs[9] [3] = \ ; + assign \time_control_regs[9] [2] = \ ; + assign \time_control_regs[9] [1] = \ ; + assign \time_control_regs[9] [0] = \ ; + Arty_Z7_20_v_tc_1_0_axi_lite_ipif \AXI4_LITE_INTERFACE.AXI_LITE_IPIF_I + (.D({ipif_proc_RNW,ipif_proc_CS,ipif_proc_Addr_int}), + .aclk(aclk), + .aresetn(aresetn), + .ipif_Error(ipif_Error), + .ipif_RdAck(ipif_RdAck), + .ipif_WrAck(ipif_WrAck), + .out_data(p_143_out[31:0]), + .p_0_in(p_0_in_0), + .s_axi_araddr(s_axi_araddr), + .s_axi_arready(s_axi_arready), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_bready(s_axi_bready), + .s_axi_bresp(\^s_axi_bresp ), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_rdata(s_axi_rdata), + .s_axi_rready(s_axi_rready), + .s_axi_rresp(\^s_axi_rresp ), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_wready(s_axi_wready), + .s_axi_wvalid(s_axi_wvalid)); + Arty_Z7_20_v_tc_1_0_mux_tree__parameterized0 \AXI4_LITE_INTERFACE.CORE_MUX0 + (.\GEN_SEL_DELAY[2].sel_int_reg[2][0] (\AXI4_LITE_INTERFACE.GENR_MUX0_n_1 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_34 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_1 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_35 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_10 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_44 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_11 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_45 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_12 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_46 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_13 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_47 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_14 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_48 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_15 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_49 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_16 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_50 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_17 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_51 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_18 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_52 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_19 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_53 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_2 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_36 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_20 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_54 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_21 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_55 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_22 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_56 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_23 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_57 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_24 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_58 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_25 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_59 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_26 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_60 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_27 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_61 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_28 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_62 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_29 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_63 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_3 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_37 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_30 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_64 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_31 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_65 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_32 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_66 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_33 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_67 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_34 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_68 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_35 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_69 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_36 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_70 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_37 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_71 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_38 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_72 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_39 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_73 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_4 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_38 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_40 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_74 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_41 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_75 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_42 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_76 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_43 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_77 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_44 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_78 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_45 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_79 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_46 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_80 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_47 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_81 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_48 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_82 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_49 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_83 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_5 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_39 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_50 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_84 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_51 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_85 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_52 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_86 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_53 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_87 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_54 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_88 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_55 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_89 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_56 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_90 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_57 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_91 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_58 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_92 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_59 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_93 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_6 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_40 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_60 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_94 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_61 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_95 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_62 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_96 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_63 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_97 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_7 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_41 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_8 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_42 ), + .\GEN_SEL_DELAY[2].sel_int_reg[2][0]_9 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_43 ), + .\GEN_SEL_DELAY[4].sel_int_reg[4][0] (\AXI4_LITE_INTERFACE.GENR_MUX0_n_0 ), + .\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 (\AXI4_LITE_INTERFACE.CORE_MUX0_n_0 ), + .\core_control_regs[16] ({\^core_control_regs[16] [26:16],\^core_control_regs[16] [11:0]}), + .core_data(core_data), + .\core_status_regs[16] ({\core_status_regs[16] [31:27],\core_status_regs[16] [15:12]}), + .ipif_Addr(ipif_Addr[5]), + .vid_aclk(vid_aclk)); + Arty_Z7_20_v_tc_1_0_mux_tree \AXI4_LITE_INTERFACE.GENR_MUX0 + (.\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0] (\core_control_regs2_int[0] ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][0] (\core_control_regs2_int[10] ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][0] (\core_control_regs2_int[11] ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][0] (\core_control_regs2_int[12] ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][0] (\core_control_regs2_int[13] ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][0] (\core_control_regs2_int[14] ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][0] (\core_control_regs2_int[15] ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][0] (\core_control_regs2_int[1] ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][0] (\core_control_regs2_int[2] ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][0] (\core_control_regs2_int[3] ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][0] (\core_control_regs2_int[4] ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][0] (\core_control_regs2_int[5] ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][0] (\core_control_regs2_int[6] ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][0] (\core_control_regs2_int[7] ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][0] (\core_control_regs2_int[8] ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][0] (\core_control_regs2_int[9] ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][31] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_137 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_598 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_599 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][12] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_600 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][13] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_601 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][16] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_604 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][17] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_605 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][18] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_606 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][19] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_607 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][20] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_608 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][21] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_609 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][22] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_610 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][23] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_611 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][24] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_612 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][25] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_613 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][26] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_614 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][27] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_615 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][28] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_616 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][29] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_617 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][30] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_618 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][31] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_619 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_596 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_597 ), + .\AXI4_LITE_INTERFACE.ipif_RdData_reg[0] (\AXI4_LITE_INTERFACE.GENR_MUX0_n_0 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_300 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_310 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_311 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][12] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_312 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][16] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_316 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][17] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_317 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][18] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_318 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][19] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_319 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][20] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_320 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][21] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_321 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][22] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_322 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][23] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_323 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][24] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_324 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][25] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_325 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][26] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_326 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][27] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_327 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_328 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][2] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_302 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_303 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_304 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_305 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_306 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_307 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_308 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_309 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_275 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_276 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_277 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_268 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][1] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_269 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][2] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_270 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_271 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_272 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_273 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_274 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_236 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_246 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_247 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][12] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_248 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][16] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_252 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][17] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_253 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][18] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_254 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][19] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_255 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][1] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_237 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][20] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_256 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][21] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_257 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][22] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_258 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][23] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_259 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][24] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_260 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][25] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_261 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][26] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_262 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][27] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_263 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_264 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][2] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_238 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_239 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_240 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_241 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_242 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_243 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_244 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_245 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_204 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_214 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_215 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][12] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_216 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][16] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_220 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][17] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_221 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][18] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_222 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][19] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_223 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][1] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_205 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][20] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_224 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][21] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_225 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][22] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_226 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][23] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_227 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][24] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_228 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][25] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_229 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][26] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_230 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][27] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_231 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_232 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][2] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_206 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_207 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_208 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_209 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_210 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_211 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_212 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_213 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_172 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_182 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_183 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][12] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_184 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][16] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_188 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][17] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_189 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][18] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_190 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][19] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_191 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][1] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_173 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][20] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_192 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][21] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_193 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][22] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_194 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][23] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_195 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][24] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_196 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][25] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_197 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][26] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_198 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][27] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_199 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_200 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][2] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_174 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_175 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_176 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_177 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_178 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_179 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_180 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_181 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_140 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_150 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_151 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][12] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_152 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][16] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_156 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][17] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_157 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][18] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_158 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][19] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_159 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][1] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_141 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][20] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_160 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][21] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_161 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][22] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_162 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][23] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_163 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][24] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_164 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][25] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_165 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][26] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_166 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][27] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_167 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][28] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_168 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][2] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_142 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_143 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_144 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_145 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_146 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_147 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_148 ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_149 ), + .\DET_HACTIVE.det_active_video_pol_int_reg (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_528 ), + .\DET_HSYNC.det_hsync_pol_int_reg (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_527 ), + .\DET_VSYNC.det_vsync_pol_int_reg (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_526 ), + .\GEN_HAS_IRQ.intr_err_reg[0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_588 ), + .\GEN_HAS_IRQ.intr_err_reg[14] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_602 ), + .\GEN_HAS_IRQ.intr_err_reg[15] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_603 ), + .\GEN_HAS_IRQ.intr_err_reg[1] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_589 ), + .\GEN_HAS_IRQ.intr_err_reg[2] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_590 ), + .\GEN_HAS_IRQ.intr_err_reg[3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_591 ), + .\GEN_HAS_IRQ.intr_err_reg[4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_592 ), + .\GEN_HAS_IRQ.intr_err_reg[5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_593 ), + .\GEN_HAS_IRQ.intr_err_reg[6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_594 ), + .\GEN_HAS_IRQ.intr_err_reg[7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_595 ), + .\GEN_HAS_IRQ.intr_stat_reg[0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_620 ), + .\GEN_HAS_IRQ.intr_stat_reg[10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_630 ), + .\GEN_HAS_IRQ.intr_stat_reg[11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_631 ), + .\GEN_HAS_IRQ.intr_stat_reg[12] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_632 ), + .\GEN_HAS_IRQ.intr_stat_reg[13] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_633 ), + .\GEN_HAS_IRQ.intr_stat_reg[14] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_634 ), + .\GEN_HAS_IRQ.intr_stat_reg[15] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_635 ), + .\GEN_HAS_IRQ.intr_stat_reg[16] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_636 ), + .\GEN_HAS_IRQ.intr_stat_reg[17] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_637 ), + .\GEN_HAS_IRQ.intr_stat_reg[18] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_638 ), + .\GEN_HAS_IRQ.intr_stat_reg[19] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_639 ), + .\GEN_HAS_IRQ.intr_stat_reg[1] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_621 ), + .\GEN_HAS_IRQ.intr_stat_reg[20] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_640 ), + .\GEN_HAS_IRQ.intr_stat_reg[21] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_641 ), + .\GEN_HAS_IRQ.intr_stat_reg[22] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_642 ), + .\GEN_HAS_IRQ.intr_stat_reg[23] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_643 ), + .\GEN_HAS_IRQ.intr_stat_reg[24] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_644 ), + .\GEN_HAS_IRQ.intr_stat_reg[25] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_645 ), + .\GEN_HAS_IRQ.intr_stat_reg[26] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_646 ), + .\GEN_HAS_IRQ.intr_stat_reg[27] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_647 ), + .\GEN_HAS_IRQ.intr_stat_reg[28] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_648 ), + .\GEN_HAS_IRQ.intr_stat_reg[29] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_649 ), + .\GEN_HAS_IRQ.intr_stat_reg[2] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_622 ), + .\GEN_HAS_IRQ.intr_stat_reg[30] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_650 ), + .\GEN_HAS_IRQ.intr_stat_reg[3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_623 ), + .\GEN_HAS_IRQ.intr_stat_reg[4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_624 ), + .\GEN_HAS_IRQ.intr_stat_reg[5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_625 ), + .\GEN_HAS_IRQ.intr_stat_reg[6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_626 ), + .\GEN_HAS_IRQ.intr_stat_reg[7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_627 ), + .\GEN_HAS_IRQ.intr_stat_reg[8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_628 ), + .\GEN_HAS_IRQ.intr_stat_reg[9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_629 ), + .\GEN_SEL_DELAY[3].sel_int_reg[3][0] (\AXI4_LITE_INTERFACE.CORE_MUX0_n_0 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][0]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_97 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][10]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_87 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][11]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_86 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][12]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_85 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][13]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_84 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][14]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_83 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][15]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_82 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][16]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_81 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][17]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_80 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][18]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_79 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][19]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_78 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][1]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_96 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][20]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_77 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][21]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_76 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][22]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_75 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][23]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_74 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][24]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_73 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][25]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_72 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][26]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_71 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][27]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_70 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][28]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_69 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][29]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_68 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][2]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_95 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][30]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_67 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][31]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_66 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][3]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_94 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][4]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_93 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][5]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_92 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][6]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_91 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][7]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_90 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][8]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_89 ), + .\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][9]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_88 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][0]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_65 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][10]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_55 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][11]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_54 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][12]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_53 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][13]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_52 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][14]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_51 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][15]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_50 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][16]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_49 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][17]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_48 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][18]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_47 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][19]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_46 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][1]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_64 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][20]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_45 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][21]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_44 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][22]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_43 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][23]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_42 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][24]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_41 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][25]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_40 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][26]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_39 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][27]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_38 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][28]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_37 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][29]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_36 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][2]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_63 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][30]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_35 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][31]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_34 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][3]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_62 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][4]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_61 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][5]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_60 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][6]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_59 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][7]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_58 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][8]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_57 ), + .\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][9]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_56 ), + .\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0 (\AXI4_LITE_INTERFACE.GENR_MUX0_n_1 ), + .Q({genr_regs[1180:1168],genr_regs[1164:1153],\time_control_regs2_int[28] }), + .core_regs({core_regs[506:496],core_regs[491:481],core_regs[474:464],core_regs[459:449],core_regs[442:432],core_regs[427:417],core_regs[410:400],core_regs[395:385],core_regs[378:368],core_regs[363:353],core_regs[346:336],core_regs[331:321],core_regs[314:304],core_regs[299:289],core_regs[282:272],core_regs[267:257],core_regs[250:240],core_regs[235:225],core_regs[218:208],core_regs[203:193],core_regs[186:176],core_regs[171:161],core_regs[154:144],core_regs[139:129],core_regs[122:112],core_regs[107:97],core_regs[90:80],core_regs[75:65],core_regs[58:48],core_regs[43:33],core_regs[26:16],core_regs[11:1]}), + .\core_status_regs[0] ({\core_status_regs[0] [31:27],\core_status_regs[0] [15:12]}), + .\core_status_regs[10] ({\core_status_regs[10] [31:27],\core_status_regs[10] [15:12]}), + .\core_status_regs[11] ({\core_status_regs[11] [31:27],\core_status_regs[11] [15:12]}), + .\core_status_regs[12] ({\core_status_regs[12] [31:27],\core_status_regs[12] [15:12]}), + .\core_status_regs[13] ({\core_status_regs[13] [31:27],\core_status_regs[13] [15:12]}), + .\core_status_regs[14] ({\core_status_regs[14] [31:27],\core_status_regs[14] [15:12]}), + .\core_status_regs[15] ({\core_status_regs[15] [31:27],\core_status_regs[15] [15:12]}), + .\core_status_regs[1] ({\core_status_regs[1] [31:27],\core_status_regs[1] [15:12]}), + .\core_status_regs[2] ({\core_status_regs[2] [31:27],\core_status_regs[2] [15:12]}), + .\core_status_regs[3] ({\core_status_regs[3] [31:27],\core_status_regs[3] [15:12]}), + .\core_status_regs[4] ({\core_status_regs[4] [31:27],\core_status_regs[4] [15:12]}), + .\core_status_regs[5] ({\core_status_regs[5] [31:27],\core_status_regs[5] [15:12]}), + .\core_status_regs[6] ({\core_status_regs[6] [31:27],\core_status_regs[6] [15:12]}), + .\core_status_regs[7] ({\core_status_regs[7] [31:27],\core_status_regs[7] [15:12]}), + .\core_status_regs[8] ({\core_status_regs[8] [31:27],\core_status_regs[8] [15:12]}), + .\core_status_regs[9] ({\core_status_regs[9] [31:27],\core_status_regs[9] [15:12]}), + .\data_sync_reg[2][34] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_139 ), + .\data_sync_reg[2][34]_0 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_110 ), + .\data_sync_reg[2][34]_1 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_171 ), + .\data_sync_reg[2][34]_10 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_187 ), + .\data_sync_reg[2][34]_100 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_380 ), + .\data_sync_reg[2][34]_101 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_379 ), + .\data_sync_reg[2][34]_102 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_378 ), + .\data_sync_reg[2][34]_103 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_377 ), + .\data_sync_reg[2][34]_104 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_376 ), + .\data_sync_reg[2][34]_105 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_375 ), + .\data_sync_reg[2][34]_106 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_374 ), + .\data_sync_reg[2][34]_107 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_373 ), + .\data_sync_reg[2][34]_108 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_372 ), + .\data_sync_reg[2][34]_109 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_371 ), + .\data_sync_reg[2][34]_11 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_186 ), + .\data_sync_reg[2][34]_110 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_370 ), + .\data_sync_reg[2][34]_111 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_369 ), + .\data_sync_reg[2][34]_112 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_368 ), + .\data_sync_reg[2][34]_113 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_367 ), + .\data_sync_reg[2][34]_114 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_366 ), + .\data_sync_reg[2][34]_115 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_365 ), + .\data_sync_reg[2][34]_116 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_364 ), + .\data_sync_reg[2][34]_117 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_427 ), + .\data_sync_reg[2][34]_118 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_426 ), + .\data_sync_reg[2][34]_119 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_425 ), + .\data_sync_reg[2][34]_12 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_185 ), + .\data_sync_reg[2][34]_120 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_424 ), + .\data_sync_reg[2][34]_121 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_423 ), + .\data_sync_reg[2][34]_122 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_422 ), + .\data_sync_reg[2][34]_123 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_421 ), + .\data_sync_reg[2][34]_124 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_420 ), + .\data_sync_reg[2][34]_125 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_419 ), + .\data_sync_reg[2][34]_126 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_418 ), + .\data_sync_reg[2][34]_127 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_417 ), + .\data_sync_reg[2][34]_128 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_416 ), + .\data_sync_reg[2][34]_129 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_415 ), + .\data_sync_reg[2][34]_13 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_235 ), + .\data_sync_reg[2][34]_130 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_414 ), + .\data_sync_reg[2][34]_131 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_413 ), + .\data_sync_reg[2][34]_132 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_412 ), + .\data_sync_reg[2][34]_133 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_411 ), + .\data_sync_reg[2][34]_134 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_410 ), + .\data_sync_reg[2][34]_135 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_409 ), + .\data_sync_reg[2][34]_136 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_408 ), + .\data_sync_reg[2][34]_137 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_407 ), + .\data_sync_reg[2][34]_138 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_406 ), + .\data_sync_reg[2][34]_139 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_405 ), + .\data_sync_reg[2][34]_14 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_234 ), + .\data_sync_reg[2][34]_140 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_404 ), + .\data_sync_reg[2][34]_141 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_403 ), + .\data_sync_reg[2][34]_142 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_402 ), + .\data_sync_reg[2][34]_143 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_401 ), + .\data_sync_reg[2][34]_144 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_400 ), + .\data_sync_reg[2][34]_145 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_399 ), + .\data_sync_reg[2][34]_146 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_398 ), + .\data_sync_reg[2][34]_147 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_397 ), + .\data_sync_reg[2][34]_148 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_396 ), + .\data_sync_reg[2][34]_149 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_459 ), + .\data_sync_reg[2][34]_15 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_233 ), + .\data_sync_reg[2][34]_150 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_458 ), + .\data_sync_reg[2][34]_151 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_457 ), + .\data_sync_reg[2][34]_152 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_456 ), + .\data_sync_reg[2][34]_153 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_443 ), + .\data_sync_reg[2][34]_154 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_442 ), + .\data_sync_reg[2][34]_155 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_441 ), + .\data_sync_reg[2][34]_156 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_440 ), + .\data_sync_reg[2][34]_157 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_491 ), + .\data_sync_reg[2][34]_158 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_490 ), + .\data_sync_reg[2][34]_159 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_489 ), + .\data_sync_reg[2][34]_16 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_219 ), + .\data_sync_reg[2][34]_160 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_488 ), + .\data_sync_reg[2][34]_161 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_475 ), + .\data_sync_reg[2][34]_162 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_474 ), + .\data_sync_reg[2][34]_163 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_473 ), + .\data_sync_reg[2][34]_164 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_472 ), + .\data_sync_reg[2][34]_165 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_523 ), + .\data_sync_reg[2][34]_166 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_522 ), + .\data_sync_reg[2][34]_167 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_521 ), + .\data_sync_reg[2][34]_168 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_520 ), + .\data_sync_reg[2][34]_169 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_519 ), + .\data_sync_reg[2][34]_17 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_218 ), + .\data_sync_reg[2][34]_170 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_518 ), + .\data_sync_reg[2][34]_171 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_517 ), + .\data_sync_reg[2][34]_172 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_516 ), + .\data_sync_reg[2][34]_173 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_515 ), + .\data_sync_reg[2][34]_174 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_514 ), + .\data_sync_reg[2][34]_175 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_513 ), + .\data_sync_reg[2][34]_176 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_512 ), + .\data_sync_reg[2][34]_177 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_511 ), + .\data_sync_reg[2][34]_178 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_510 ), + .\data_sync_reg[2][34]_179 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_509 ), + .\data_sync_reg[2][34]_18 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_217 ), + .\data_sync_reg[2][34]_180 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_508 ), + .\data_sync_reg[2][34]_181 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_507 ), + .\data_sync_reg[2][34]_182 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_506 ), + .\data_sync_reg[2][34]_183 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_505 ), + .\data_sync_reg[2][34]_184 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_504 ), + .\data_sync_reg[2][34]_185 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_555 ), + .\data_sync_reg[2][34]_186 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_554 ), + .\data_sync_reg[2][34]_187 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_553 ), + .\data_sync_reg[2][34]_188 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_552 ), + .\data_sync_reg[2][34]_189 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_551 ), + .\data_sync_reg[2][34]_19 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_267 ), + .\data_sync_reg[2][34]_190 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_550 ), + .\data_sync_reg[2][34]_191 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_549 ), + .\data_sync_reg[2][34]_192 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_548 ), + .\data_sync_reg[2][34]_193 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_547 ), + .\data_sync_reg[2][34]_194 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_546 ), + .\data_sync_reg[2][34]_195 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_545 ), + .\data_sync_reg[2][34]_196 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_544 ), + .\data_sync_reg[2][34]_197 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_543 ), + .\data_sync_reg[2][34]_198 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_542 ), + .\data_sync_reg[2][34]_199 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_541 ), + .\data_sync_reg[2][34]_2 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_170 ), + .\data_sync_reg[2][34]_20 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_266 ), + .\data_sync_reg[2][34]_200 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_540 ), + .\data_sync_reg[2][34]_201 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_539 ), + .\data_sync_reg[2][34]_202 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_538 ), + .\data_sync_reg[2][34]_203 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_537 ), + .\data_sync_reg[2][34]_204 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_536 ), + .\data_sync_reg[2][34]_205 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_535 ), + .\data_sync_reg[2][34]_206 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_534 ), + .\data_sync_reg[2][34]_207 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_533 ), + .\data_sync_reg[2][34]_208 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_531 ), + .\data_sync_reg[2][34]_209 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_530 ), + .\data_sync_reg[2][34]_21 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_265 ), + .\data_sync_reg[2][34]_210 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_529 ), + .\data_sync_reg[2][34]_211 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_525 ), + .\data_sync_reg[2][34]_212 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_524 ), + .\data_sync_reg[2][34]_213 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_587 ), + .\data_sync_reg[2][34]_214 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_586 ), + .\data_sync_reg[2][34]_215 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_585 ), + .\data_sync_reg[2][34]_216 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_584 ), + .\data_sync_reg[2][34]_217 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_583 ), + .\data_sync_reg[2][34]_218 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_571 ), + .\data_sync_reg[2][34]_219 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_570 ), + .\data_sync_reg[2][34]_22 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_251 ), + .\data_sync_reg[2][34]_220 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_569 ), + .\data_sync_reg[2][34]_221 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_568 ), + .\data_sync_reg[2][34]_222 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_138 ), + .\data_sync_reg[2][34]_23 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_250 ), + .\data_sync_reg[2][34]_24 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_249 ), + .\data_sync_reg[2][34]_25 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_299 ), + .\data_sync_reg[2][34]_26 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_298 ), + .\data_sync_reg[2][34]_27 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_297 ), + .\data_sync_reg[2][34]_28 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_296 ), + .\data_sync_reg[2][34]_29 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_295 ), + .\data_sync_reg[2][34]_3 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_169 ), + .\data_sync_reg[2][34]_30 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_294 ), + .\data_sync_reg[2][34]_31 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_293 ), + .\data_sync_reg[2][34]_32 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_292 ), + .\data_sync_reg[2][34]_33 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_291 ), + .\data_sync_reg[2][34]_34 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_290 ), + .\data_sync_reg[2][34]_35 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_289 ), + .\data_sync_reg[2][34]_36 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_288 ), + .\data_sync_reg[2][34]_37 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_287 ), + .\data_sync_reg[2][34]_38 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_286 ), + .\data_sync_reg[2][34]_39 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_285 ), + .\data_sync_reg[2][34]_4 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_155 ), + .\data_sync_reg[2][34]_40 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_284 ), + .\data_sync_reg[2][34]_41 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_283 ), + .\data_sync_reg[2][34]_42 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_282 ), + .\data_sync_reg[2][34]_43 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_281 ), + .\data_sync_reg[2][34]_44 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_280 ), + .\data_sync_reg[2][34]_45 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_279 ), + .\data_sync_reg[2][34]_46 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_278 ), + .\data_sync_reg[2][34]_47 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_331 ), + .\data_sync_reg[2][34]_48 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_330 ), + .\data_sync_reg[2][34]_49 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_329 ), + .\data_sync_reg[2][34]_5 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_154 ), + .\data_sync_reg[2][34]_50 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_315 ), + .\data_sync_reg[2][34]_51 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_314 ), + .\data_sync_reg[2][34]_52 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_313 ), + .\data_sync_reg[2][34]_53 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_363 ), + .\data_sync_reg[2][34]_54 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_362 ), + .\data_sync_reg[2][34]_55 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_361 ), + .\data_sync_reg[2][34]_56 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_360 ), + .\data_sync_reg[2][34]_57 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_359 ), + .\data_sync_reg[2][34]_58 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_358 ), + .\data_sync_reg[2][34]_59 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_357 ), + .\data_sync_reg[2][34]_6 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_153 ), + .\data_sync_reg[2][34]_60 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_356 ), + .\data_sync_reg[2][34]_61 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_355 ), + .\data_sync_reg[2][34]_62 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_354 ), + .\data_sync_reg[2][34]_63 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_353 ), + .\data_sync_reg[2][34]_64 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_352 ), + .\data_sync_reg[2][34]_65 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_351 ), + .\data_sync_reg[2][34]_66 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_350 ), + .\data_sync_reg[2][34]_67 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_349 ), + .\data_sync_reg[2][34]_68 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_348 ), + .\data_sync_reg[2][34]_69 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_347 ), + .\data_sync_reg[2][34]_7 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_203 ), + .\data_sync_reg[2][34]_70 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_346 ), + .\data_sync_reg[2][34]_71 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_345 ), + .\data_sync_reg[2][34]_72 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_344 ), + .\data_sync_reg[2][34]_73 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_343 ), + .\data_sync_reg[2][34]_74 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_342 ), + .\data_sync_reg[2][34]_75 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_341 ), + .\data_sync_reg[2][34]_76 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_340 ), + .\data_sync_reg[2][34]_77 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_339 ), + .\data_sync_reg[2][34]_78 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_338 ), + .\data_sync_reg[2][34]_79 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_337 ), + .\data_sync_reg[2][34]_8 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_202 ), + .\data_sync_reg[2][34]_80 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_336 ), + .\data_sync_reg[2][34]_81 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_335 ), + .\data_sync_reg[2][34]_82 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_334 ), + .\data_sync_reg[2][34]_83 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_333 ), + .\data_sync_reg[2][34]_84 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_332 ), + .\data_sync_reg[2][34]_85 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_395 ), + .\data_sync_reg[2][34]_86 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_394 ), + .\data_sync_reg[2][34]_87 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_393 ), + .\data_sync_reg[2][34]_88 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_392 ), + .\data_sync_reg[2][34]_89 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_391 ), + .\data_sync_reg[2][34]_9 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_201 ), + .\data_sync_reg[2][34]_90 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_390 ), + .\data_sync_reg[2][34]_91 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_389 ), + .\data_sync_reg[2][34]_92 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_388 ), + .\data_sync_reg[2][34]_93 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_387 ), + .\data_sync_reg[2][34]_94 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_386 ), + .\data_sync_reg[2][34]_95 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_385 ), + .\data_sync_reg[2][34]_96 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_384 ), + .\data_sync_reg[2][34]_97 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_383 ), + .\data_sync_reg[2][34]_98 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_382 ), + .\data_sync_reg[2][34]_99 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_381 ), + .\det_hfp_start_int2_reg[10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_566 ), + .\det_hfp_start_int2_reg[11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_567 ), + .\det_hfp_start_int2_reg[3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_559 ), + .\det_hfp_start_int2_reg[4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_560 ), + .\det_hfp_start_int2_reg[5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_561 ), + .\det_hfp_start_int2_reg[6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_562 ), + .\det_hfp_start_int2_reg[7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_563 ), + .\det_hfp_start_int2_reg[8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_564 ), + .\det_hfp_start_int2_reg[9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_565 ), + .\det_htotal_int2_reg[11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_503 ), + .\det_v0active_start_hori_int2_reg[0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_476 ), + .\det_v0active_start_hori_int2_reg[10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_486 ), + .\det_v0active_start_hori_int2_reg[11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_487 ), + .\det_v0active_start_hori_int2_reg[1] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_477 ), + .\det_v0active_start_hori_int2_reg[2] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_478 ), + .\det_v0active_start_hori_int2_reg[3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_479 ), + .\det_v0active_start_hori_int2_reg[4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_480 ), + .\det_v0active_start_hori_int2_reg[5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_481 ), + .\det_v0active_start_hori_int2_reg[6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_482 ), + .\det_v0active_start_hori_int2_reg[7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_483 ), + .\det_v0active_start_hori_int2_reg[8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_484 ), + .\det_v0active_start_hori_int2_reg[9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_485 ), + .\det_v0bp_start_hori_int2_reg[0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_444 ), + .\det_v0bp_start_hori_int2_reg[10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_454 ), + .\det_v0bp_start_hori_int2_reg[11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_455 ), + .\det_v0bp_start_hori_int2_reg[1] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_445 ), + .\det_v0bp_start_hori_int2_reg[2] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_446 ), + .\det_v0bp_start_hori_int2_reg[3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_447 ), + .\det_v0bp_start_hori_int2_reg[4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_448 ), + .\det_v0bp_start_hori_int2_reg[5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_449 ), + .\det_v0bp_start_hori_int2_reg[6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_450 ), + .\det_v0bp_start_hori_int2_reg[7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_451 ), + .\det_v0bp_start_hori_int2_reg[8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_452 ), + .\det_v0bp_start_hori_int2_reg[9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_453 ), + .\det_v0fp_start_hori_int2_reg[0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_460 ), + .\det_v0fp_start_hori_int2_reg[10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_470 ), + .\det_v0fp_start_hori_int2_reg[11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_471 ), + .\det_v0fp_start_hori_int2_reg[1] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_461 ), + .\det_v0fp_start_hori_int2_reg[2] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_462 ), + .\det_v0fp_start_hori_int2_reg[3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_463 ), + .\det_v0fp_start_hori_int2_reg[4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_464 ), + .\det_v0fp_start_hori_int2_reg[5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_465 ), + .\det_v0fp_start_hori_int2_reg[6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_466 ), + .\det_v0fp_start_hori_int2_reg[7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_467 ), + .\det_v0fp_start_hori_int2_reg[8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_468 ), + .\det_v0fp_start_hori_int2_reg[9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_469 ), + .\det_v0fp_start_int_reg[0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_572 ), + .\det_v0fp_start_int_reg[10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_582 ), + .\det_v0fp_start_int_reg[1] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_573 ), + .\det_v0fp_start_int_reg[2] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_574 ), + .\det_v0fp_start_int_reg[3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_575 ), + .\det_v0fp_start_int_reg[4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_576 ), + .\det_v0fp_start_int_reg[5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_577 ), + .\det_v0fp_start_int_reg[6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_578 ), + .\det_v0fp_start_int_reg[7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_579 ), + .\det_v0fp_start_int_reg[8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_580 ), + .\det_v0fp_start_int_reg[9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_581 ), + .\det_v0sync_start_hori_int2_reg[0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_428 ), + .\det_v0sync_start_hori_int2_reg[10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_438 ), + .\det_v0sync_start_hori_int2_reg[11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_439 ), + .\det_v0sync_start_hori_int2_reg[1] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_429 ), + .\det_v0sync_start_hori_int2_reg[2] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_430 ), + .\det_v0sync_start_hori_int2_reg[3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_431 ), + .\det_v0sync_start_hori_int2_reg[4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_432 ), + .\det_v0sync_start_hori_int2_reg[5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_433 ), + .\det_v0sync_start_hori_int2_reg[6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_434 ), + .\det_v0sync_start_hori_int2_reg[7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_435 ), + .\det_v0sync_start_hori_int2_reg[8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_436 ), + .\det_v0sync_start_hori_int2_reg[9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_437 ), + .\det_v0total_reg[0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_492 ), + .\det_v0total_reg[10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_502 ), + .\det_v0total_reg[1] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_493 ), + .\det_v0total_reg[2] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_494 ), + .\det_v0total_reg[3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_495 ), + .\det_v0total_reg[4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_496 ), + .\det_v0total_reg[5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_497 ), + .\det_v0total_reg[6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_498 ), + .\det_v0total_reg[7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_499 ), + .\det_v0total_reg[8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_500 ), + .\det_v0total_reg[9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_501 ), + .\gen_v0chroma_start_reg[0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_532 ), + .genr_data(genr_data), + .\intr_status_int_reg[10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_557 ), + .\intr_status_int_reg[11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_558 ), + .\intr_status_int_reg[12] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_301 ), + .\intr_status_int_reg[8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_556 ), + .ipif_Addr({ipif_Addr[7:6],ipif_Addr[4:2]}), + .\time_status_regs[28] ({\time_status_regs[28] [31:29],\time_status_regs[28] [15:13]}), + .vid_aclk(vid_aclk)); + Arty_Z7_20_v_tc_1_0_video_clock_cross__parameterized0 \AXI4_LITE_INTERFACE.SYNC2PROCCLK_I + (.\AXI4_LITE_INTERFACE.ipif_Error_reg (\AXI4_LITE_INTERFACE.SYNC2PROCCLK_I_n_36 ), + .aclk(aclk), + .in_data({write_ack,read_ack_d,ipif_RdData}), + .out_data(p_143_out), + .p_526_out(p_526_out), + .p_528_out(p_528_out), + .read_ack_d1(read_ack_d1), + .read_ack_d2(read_ack_d2), + .write_ack_d1(write_ack_d1), + .write_ack_d2(write_ack_d2)); + Arty_Z7_20_v_tc_1_0_video_clock_cross \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I + (.\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0] (\core_control_regs_int[0] ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_110 ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][0] (\core_control_regs_int[10] ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][0] (\core_control_regs_int[11] ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][0] (\core_control_regs_int[13] ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][0] (\core_control_regs_int[14] ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][0] (\core_control_regs_int[15] ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][0] (\core_control_regs_int[16] ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][0] (\core_control_regs_int[1] ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][0] (\core_control_regs_int[2] ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][0] (\core_control_regs_int[3] ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][0] (\core_control_regs_int[4] ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][0] (\core_control_regs_int[5] ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][0] (\core_control_regs_int[6] ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][0] (\core_control_regs_int[7] ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][0] (\core_control_regs_int[8] ), + .\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][0] (\core_control_regs_int[9] ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][0] (\genr_control_regs_int[0] ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_52 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_51 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][12] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_50 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][13] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_49 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][16] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_48 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][17] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_47 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][18] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_46 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][19] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_45 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][20] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_44 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][21] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_43 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][22] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_42 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][23] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_41 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][24] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_40 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][25] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_39 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][26] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_38 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][27] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_37 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][28] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_36 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][29] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_35 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][30] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_34 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][31] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_0 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_54 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_53 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][16] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_60 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][17] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_59 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][18] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_58 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][19] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_57 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][20] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_56 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][21] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_55 ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][21]_0 (\^genr_control_regs[2] ), + .\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][8] (\genr_control_regs_int[3] ), + .\AXI4_LITE_INTERFACE.ipif_RdData_reg[31] ({\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_61 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_62 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_63 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_64 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_65 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_66 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_67 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_68 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_69 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_70 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_71 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_72 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_73 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_74 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_75 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_76 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_77 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_78 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_79 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_80 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_81 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_82 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_83 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_84 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_85 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_86 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_87 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_88 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_89 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_90 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_91 ,\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_92 }), + .\AXI4_LITE_INTERFACE.proc_sync1_reg[44] (proc_sync1), + .\AXI4_LITE_INTERFACE.soft_resetn_reg (resetn_out), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][0] (\time_control_regs_int[16] ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] ({p_24_in,p_23_in,p_22_in,p_21_in,p_20_in,p_19_in,p_18_in,p_17_in,p_16_in,p_15_in,p_14_in,p_13_in,p_12_in,p_11_in,p_10_in,p_9_in,p_8_in,p_7_in,p_6_in,p_5_in,p_4_in,p_3_in,p_2_in,p_1_in,p_0_in,\time_control_regs2_int[16] }), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][7] (\time_control_regs_int[18] ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9] ({p_5_out,\^time_control_regs[18] [6],\^time_control_regs[18] [3:0]}), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][0] (p_2_out), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6] ({\^time_control_regs[19] [6],p_8_out}), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][0] (\time_control_regs_int[20] ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] ({genr_regs[924:912],genr_regs[908:897],\time_control_regs2_int[20] }), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][0] (\time_control_regs_int[21] ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] ({genr_regs[956:944],genr_regs[940:929],\time_control_regs2_int[21] }), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][0] (\time_control_regs_int[22] ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] ({genr_regs[988:976],genr_regs[972:961],\time_control_regs2_int[22] }), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][0] (\time_control_regs_int[23] ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] ({genr_regs[1020:1008],genr_regs[1004:993],\time_control_regs2_int[23] }), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][0] (\time_control_regs_int[24] ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] ({genr_regs[1052:1040],genr_regs[1036:1025],\time_control_regs2_int[24] }), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][0] (\time_control_regs_int[25] ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] ({genr_regs[1084:1072],genr_regs[1068:1057],\time_control_regs2_int[25] }), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][0] (\time_control_regs_int[26] ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] ({genr_regs[1116:1104],genr_regs[1100:1089],\time_control_regs2_int[26] }), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][0] (\time_control_regs_int[27] ), + .\AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][0] (\time_control_regs_int[28] ), + .D({\^genr_control_regs[1] [31:16],\^genr_control_regs[1] [13:8]}), + .E(\core_control_regs_int[12] ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_620 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_630 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_631 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][12] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_632 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][13] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_633 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][14] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_634 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][15] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_635 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][16] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_636 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][17] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_637 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][18] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_638 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][19] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_639 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][1] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_621 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][20] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_640 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][21] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_641 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][22] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_642 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][23] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_643 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][24] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_644 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][25] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_645 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][26] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_646 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][27] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_647 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][28] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_648 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][29] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_649 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][2] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_622 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][30] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_650 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][31] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_137 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_623 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_624 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_625 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_626 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_627 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_628 ), + .\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_629 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_588 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_598 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_599 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][12] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_600 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][13] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_601 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][14] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_602 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][15] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_603 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][16] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_604 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][17] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_605 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][18] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_606 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][19] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_607 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][1] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_589 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][20] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_608 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][21] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_609 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][22] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_610 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][23] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_611 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][24] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_612 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][25] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_613 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][26] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_614 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][27] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_615 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][28] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_616 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][29] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_617 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][2] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_590 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][30] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_618 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][31] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_619 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_591 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_592 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_593 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_594 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_595 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_596 ), + .\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_597 ), + .\GEN_TREE.GEN_BRANCH[33].GEN_MUX_REG.data_out_reg_reg[33][26] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_139 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_556 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_566 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_567 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][12] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_568 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][13] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_569 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][14] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_570 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][15] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_571 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][16] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_572 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][17] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_573 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][18] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_574 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][19] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_575 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][1] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_557 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][20] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_576 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][21] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_577 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][22] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_578 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][23] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_579 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][24] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_580 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][25] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_581 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][26] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_582 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][27] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_583 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][28] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_584 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][29] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_585 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][2] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_558 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][30] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_586 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_138 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31]_0 (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_587 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_559 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_560 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_561 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_562 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_563 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_564 ), + .\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_565 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_524 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_534 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_535 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][12] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_536 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][13] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_537 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][14] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_538 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][15] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_539 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][16] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_540 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][17] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_541 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][18] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_542 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][19] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_543 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][1] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_525 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][20] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_544 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][21] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_545 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][22] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_546 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][23] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_547 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][24] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_548 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][25] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_549 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][26] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_550 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][27] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_551 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][28] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_552 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][29] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_553 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][2] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_526 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][30] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_554 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][31] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_555 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_527 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_528 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_529 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_530 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_531 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_532 ), + .\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_533 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_492 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_502 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_503 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][12] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_504 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][13] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_505 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][14] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_506 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][15] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_507 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][16] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_508 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][17] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_509 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][18] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_510 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][19] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_511 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][1] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_493 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][20] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_512 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][21] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_513 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][22] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_514 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][23] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_515 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][24] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_516 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][25] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_517 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][26] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_518 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][27] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_519 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][28] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_520 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][29] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_521 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][2] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_494 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][30] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_522 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][31] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_523 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_495 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_496 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_497 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_498 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_499 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_500 ), + .\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_501 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_460 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_470 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_471 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][12] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_472 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][13] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_473 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][14] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_474 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][15] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_475 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][16] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_476 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][17] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_477 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][18] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_478 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][19] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_479 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][1] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_461 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][20] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_480 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][21] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_481 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][22] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_482 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][23] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_483 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][24] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_484 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][25] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_485 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][26] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_486 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][27] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_487 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][28] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_488 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][29] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_489 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][2] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_462 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][30] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_490 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][31] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_491 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_463 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_464 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_465 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_466 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_467 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_468 ), + .\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_469 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_428 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_438 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_439 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][12] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_440 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][13] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_441 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][14] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_442 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][15] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_443 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][16] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_444 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][17] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_445 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][18] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_446 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][19] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_447 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][1] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_429 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][20] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_448 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][21] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_449 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][22] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_450 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][23] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_451 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][24] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_452 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][25] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_453 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][26] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_454 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][27] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_455 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][28] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_456 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][29] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_457 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][2] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_430 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][30] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_458 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][31] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_459 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_431 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_432 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_433 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_434 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_435 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_436 ), + .\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_437 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_396 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_406 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_407 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][12] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_408 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][13] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_409 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][14] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_410 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][15] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_411 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][16] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_412 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][17] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_413 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][18] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_414 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][19] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_415 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][1] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_397 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][20] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_416 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][21] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_417 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][22] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_418 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][23] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_419 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][24] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_420 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][25] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_421 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][26] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_422 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][27] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_423 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][28] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_424 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][29] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_425 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][2] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_398 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][30] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_426 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][31] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_427 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_399 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_400 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_401 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_402 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_403 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_404 ), + .\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_405 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_364 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_374 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_375 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][12] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_376 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][13] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_377 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][14] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_378 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][15] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_379 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][16] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_380 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][17] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_381 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][18] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_382 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][19] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_383 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][1] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_365 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][20] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_384 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][21] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_385 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][22] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_386 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][23] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_387 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][24] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_388 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][25] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_389 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][26] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_390 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][27] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_391 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][28] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_392 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][29] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_393 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][2] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_366 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][30] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_394 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][31] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_395 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_367 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_368 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_369 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_370 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_371 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_372 ), + .\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_373 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_332 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_342 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_343 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][12] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_344 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][13] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_345 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][14] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_346 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][15] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_347 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][16] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_348 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][17] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_349 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][18] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_350 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][19] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_351 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][1] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_333 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][20] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_352 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][21] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_353 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][22] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_354 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][23] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_355 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][24] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_356 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][25] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_357 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][26] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_358 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][27] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_359 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][28] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_360 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][29] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_361 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][2] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_334 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][30] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_362 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][31] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_363 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_335 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_336 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_337 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_338 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_339 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_340 ), + .\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_341 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_300 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_310 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_311 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][12] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_312 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][13] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_313 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][14] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_314 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][15] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_315 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][16] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_316 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][17] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_317 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][18] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_318 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][19] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_319 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][1] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_301 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][20] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_320 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][21] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_321 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][22] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_322 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][23] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_323 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][24] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_324 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][25] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_325 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][26] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_326 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][27] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_327 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][28] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_328 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][29] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_329 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][2] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_302 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][30] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_330 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][31] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_331 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_303 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_304 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_305 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_306 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_307 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_308 ), + .\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_309 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_268 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_278 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_279 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][12] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_280 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][13] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_281 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][14] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_282 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][15] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_283 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][16] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_284 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][17] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_285 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][18] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_286 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][19] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_287 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][1] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_269 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][20] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_288 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][21] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_289 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][22] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_290 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][23] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_291 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][24] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_292 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][25] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_293 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][26] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_294 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][27] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_295 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][28] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_296 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][29] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_297 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][2] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_270 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][30] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_298 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][31] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_299 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_271 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_272 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_273 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_274 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_275 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_276 ), + .\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_277 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_236 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_246 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_247 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][12] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_248 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][13] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_249 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][14] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_250 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][15] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_251 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][16] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_252 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][17] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_253 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][18] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_254 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][19] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_255 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][1] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_237 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][20] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_256 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][21] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_257 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][22] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_258 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][23] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_259 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][24] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_260 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][25] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_261 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][26] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_262 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][27] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_263 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][28] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_264 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][29] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_265 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][2] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_238 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][30] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_266 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][31] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_267 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_239 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_240 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_241 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_242 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_243 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_244 ), + .\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_245 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_204 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_214 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_215 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][12] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_216 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][13] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_217 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][14] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_218 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][15] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_219 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][16] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_220 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][17] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_221 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][18] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_222 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][19] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_223 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][1] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_205 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][20] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_224 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][21] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_225 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][22] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_226 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][23] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_227 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][24] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_228 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][25] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_229 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][26] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_230 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][27] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_231 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][28] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_232 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][29] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_233 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][2] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_206 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][30] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_234 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][31] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_235 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_207 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_208 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_209 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_210 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_211 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_212 ), + .\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_213 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_172 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_182 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_183 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][12] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_184 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][13] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_185 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][14] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_186 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][15] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_187 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][16] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_188 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][17] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_189 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][18] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_190 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][19] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_191 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][1] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_173 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][20] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_192 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][21] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_193 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][22] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_194 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][23] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_195 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][24] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_196 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][25] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_197 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][26] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_198 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][27] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_199 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][28] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_200 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][29] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_201 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][2] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_174 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][30] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_202 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][31] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_203 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_175 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_176 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_177 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_178 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_179 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_180 ), + .\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_181 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][0] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_140 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][10] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_150 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][11] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_151 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][12] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_152 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][13] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_153 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][14] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_154 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][15] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_155 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][16] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_156 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][17] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_157 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][18] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_158 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][19] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_159 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][1] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_141 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][20] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_160 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][21] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_161 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][22] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_162 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][23] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_163 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][24] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_164 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][25] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_165 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][26] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_166 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][27] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_167 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][28] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_168 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][29] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_169 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][2] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_142 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][30] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_170 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][31] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_171 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][3] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_143 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][4] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_144 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][5] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_145 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][6] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_146 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][7] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_147 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][8] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_148 ), + .\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][9] (\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_149 ), + .Q({genr_regs[1148:1136],genr_regs[1132:1121],\time_control_regs2_int[27] }), + .core_data(core_data), + .\genr_control_regs[0] ({\^genr_control_regs[0] [31:30],\^genr_control_regs[0] [26:13],\^genr_control_regs[0] [11:8],\^genr_control_regs[0] [5],\^genr_control_regs[0] [3:0]}), + .\genr_control_regs[3] ({\^genr_control_regs[3] [31:16],\^genr_control_regs[3] [13:8]}), + .genr_data(genr_data), + .\genr_status_regs[0] ({\genr_status_regs[0] [29:27],\genr_status_regs[0] [12],\genr_status_regs[0] [7:6],\genr_status_regs[0] [4]}), + .\genr_status_regs[3] ({\genr_status_regs[3] [15:14],\genr_status_regs[3] [7:0]}), + .\genr_status_regs_int_reg[1] (\genr_status_regs_int_reg[1] ), + .intr_err(intr_err), + .ipif_Addr(ipif_Addr), + .out_data({ipif_cs_out,ipif_data_out}), + .p_456_out(p_456_out), + .p_533_out(p_533_out), + .p_535_out(p_535_out), + .reg_update(reg_update), + .\time_status_regs[0] (\time_status_regs[0] ), + .\time_status_regs[10] (\time_status_regs[10] ), + .\time_status_regs[11] (\time_status_regs[11] ), + .\time_status_regs[12] (\time_status_regs[12] ), + .\time_status_regs[13] (\time_status_regs[13] ), + .\time_status_regs[14] (\time_status_regs[14] ), + .\time_status_regs[15] (\time_status_regs[15] ), + .\time_status_regs[16] ({\time_status_regs[16] [31:29],\time_status_regs[16] [15:13]}), + .\time_status_regs[17] (\time_status_regs[17] ), + .\time_status_regs[18] ({\time_status_regs[18] [31:10],\time_status_regs[18] [5:4]}), + .\time_status_regs[19] (\time_status_regs[19] [31:7]), + .\time_status_regs[1] (\time_status_regs[1] ), + .\time_status_regs[20] ({\time_status_regs[20] [31:29],\time_status_regs[20] [15:13]}), + .\time_status_regs[21] ({\time_status_regs[21] [31:29],\time_status_regs[21] [15:13]}), + .\time_status_regs[22] ({\time_status_regs[22] [31:29],\time_status_regs[22] [15:13]}), + .\time_status_regs[23] ({\time_status_regs[23] [31:29],\time_status_regs[23] [15:13]}), + .\time_status_regs[24] ({\time_status_regs[24] [31:29],\time_status_regs[24] [15:13]}), + .\time_status_regs[25] ({\time_status_regs[25] [31:29],\time_status_regs[25] [15:13]}), + .\time_status_regs[26] ({\time_status_regs[26] [31:29],\time_status_regs[26] [15:13]}), + .\time_status_regs[27] ({\time_status_regs[27] [31:29],\time_status_regs[27] [15:13]}), + .\time_status_regs[2] (\time_status_regs[2] ), + .\time_status_regs[3] (\time_status_regs[3] ), + .\time_status_regs[4] (\time_status_regs[4] ), + .\time_status_regs[5] (\time_status_regs[5] ), + .\time_status_regs[6] (\time_status_regs[6] ), + .\time_status_regs[7] (\time_status_regs[7] ), + .\time_status_regs[8] (\time_status_regs[8] ), + .\time_status_regs[9] (\time_status_regs[9] ), + .vid_aclk(vid_aclk), + .vid_aclk_en(vid_aclk_en), + .vid_aresetn(vid_aresetn), + .write_ack_int(write_ack_int)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][0] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(\core_control_regs2_int[0] ), + .Q(\^core_control_regs[0] [0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][10] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[10]), + .Q(\^core_control_regs[0] [10]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][11] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[11]), + .Q(\^core_control_regs[0] [11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][16] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[16]), + .Q(\^core_control_regs[0] [16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][17] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[17]), + .Q(\^core_control_regs[0] [17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][18] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[18]), + .Q(\^core_control_regs[0] [18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][19] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[19]), + .Q(\^core_control_regs[0] [19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][1] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[1]), + .Q(\^core_control_regs[0] [1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][20] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[20]), + .Q(\^core_control_regs[0] [20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][21] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[21]), + .Q(\^core_control_regs[0] [21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][22] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[22]), + .Q(\^core_control_regs[0] [22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][23] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[23]), + .Q(\^core_control_regs[0] [23]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][24] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[24]), + .Q(\^core_control_regs[0] [24]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][25] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[25]), + .Q(\^core_control_regs[0] [25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][26] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[26]), + .Q(\^core_control_regs[0] [26]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][2] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[2]), + .Q(\^core_control_regs[0] [2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][3] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[3]), + .Q(\^core_control_regs[0] [3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][4] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[4]), + .Q(\^core_control_regs[0] [4]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][5] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[5]), + .Q(\^core_control_regs[0] [5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][6] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[6]), + .Q(\^core_control_regs[0] [6]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][7] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[7]), + .Q(\^core_control_regs[0] [7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][8] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[8]), + .Q(\^core_control_regs[0] [8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][9] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[9]), + .Q(\^core_control_regs[0] [9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][0] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(\core_control_regs2_int[10] ), + .Q(\^core_control_regs[10] [0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][10] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[330]), + .Q(\^core_control_regs[10] [10]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][11] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[331]), + .Q(\^core_control_regs[10] [11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][16] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[336]), + .Q(\^core_control_regs[10] [16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][17] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[337]), + .Q(\^core_control_regs[10] [17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][18] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[338]), + .Q(\^core_control_regs[10] [18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][19] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[339]), + .Q(\^core_control_regs[10] [19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][1] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[321]), + .Q(\^core_control_regs[10] [1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][20] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[340]), + .Q(\^core_control_regs[10] [20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][21] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[341]), + .Q(\^core_control_regs[10] [21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][22] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[342]), + .Q(\^core_control_regs[10] [22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][23] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[343]), + .Q(\^core_control_regs[10] [23]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][24] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[344]), + .Q(\^core_control_regs[10] [24]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][25] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[345]), + .Q(\^core_control_regs[10] [25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][26] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[346]), + .Q(\^core_control_regs[10] [26]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][2] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[322]), + .Q(\^core_control_regs[10] [2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][3] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[323]), + .Q(\^core_control_regs[10] [3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][4] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[324]), + .Q(\^core_control_regs[10] [4]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][5] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[325]), + .Q(\^core_control_regs[10] [5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][6] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[326]), + .Q(\^core_control_regs[10] [6]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][7] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[327]), + .Q(\^core_control_regs[10] [7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][8] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[328]), + .Q(\^core_control_regs[10] [8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][9] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[329]), + .Q(\^core_control_regs[10] [9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][0] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(\core_control_regs2_int[11] ), + .Q(\^core_control_regs[11] [0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][10] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[362]), + .Q(\^core_control_regs[11] [10]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][11] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[363]), + .Q(\^core_control_regs[11] [11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][16] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[368]), + .Q(\^core_control_regs[11] [16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][17] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[369]), + .Q(\^core_control_regs[11] [17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][18] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[370]), + .Q(\^core_control_regs[11] [18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][19] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[371]), + .Q(\^core_control_regs[11] [19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][1] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[353]), + .Q(\^core_control_regs[11] [1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][20] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[372]), + .Q(\^core_control_regs[11] [20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][21] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[373]), + .Q(\^core_control_regs[11] [21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][22] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[374]), + .Q(\^core_control_regs[11] [22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][23] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[375]), + .Q(\^core_control_regs[11] [23]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][24] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[376]), + .Q(\^core_control_regs[11] [24]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][25] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[377]), + .Q(\^core_control_regs[11] [25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][26] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[378]), + .Q(\^core_control_regs[11] [26]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][2] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[354]), + .Q(\^core_control_regs[11] [2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][3] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[355]), + .Q(\^core_control_regs[11] [3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][4] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[356]), + .Q(\^core_control_regs[11] [4]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][5] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[357]), + .Q(\^core_control_regs[11] [5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][6] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[358]), + .Q(\^core_control_regs[11] [6]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][7] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[359]), + .Q(\^core_control_regs[11] [7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][8] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[360]), + .Q(\^core_control_regs[11] [8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][9] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[361]), + .Q(\^core_control_regs[11] [9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][0] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(\core_control_regs2_int[12] ), + .Q(\^core_control_regs[12] [0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][10] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[394]), + .Q(\^core_control_regs[12] [10]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][11] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[395]), + .Q(\^core_control_regs[12] [11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][16] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[400]), + .Q(\^core_control_regs[12] [16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][17] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[401]), + .Q(\^core_control_regs[12] [17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][18] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[402]), + .Q(\^core_control_regs[12] [18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][19] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[403]), + .Q(\^core_control_regs[12] [19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][1] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[385]), + .Q(\^core_control_regs[12] [1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][20] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[404]), + .Q(\^core_control_regs[12] [20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][21] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[405]), + .Q(\^core_control_regs[12] [21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][22] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[406]), + .Q(\^core_control_regs[12] [22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][23] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[407]), + .Q(\^core_control_regs[12] [23]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][24] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[408]), + .Q(\^core_control_regs[12] [24]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][25] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[409]), + .Q(\^core_control_regs[12] [25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][26] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[410]), + .Q(\^core_control_regs[12] [26]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][2] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[386]), + .Q(\^core_control_regs[12] [2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][3] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[387]), + .Q(\^core_control_regs[12] [3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][4] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[388]), + .Q(\^core_control_regs[12] [4]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][5] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[389]), + .Q(\^core_control_regs[12] [5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][6] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[390]), + .Q(\^core_control_regs[12] [6]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][7] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[391]), + .Q(\^core_control_regs[12] [7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][8] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[392]), + .Q(\^core_control_regs[12] [8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][9] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[393]), + .Q(\^core_control_regs[12] [9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][0] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(\core_control_regs2_int[13] ), + .Q(\^core_control_regs[13] [0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][10] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[426]), + .Q(\^core_control_regs[13] [10]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][11] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[427]), + .Q(\^core_control_regs[13] [11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][16] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[432]), + .Q(\^core_control_regs[13] [16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][17] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[433]), + .Q(\^core_control_regs[13] [17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][18] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[434]), + .Q(\^core_control_regs[13] [18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][19] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[435]), + .Q(\^core_control_regs[13] [19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][1] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[417]), + .Q(\^core_control_regs[13] [1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][20] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[436]), + .Q(\^core_control_regs[13] [20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][21] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[437]), + .Q(\^core_control_regs[13] [21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][22] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[438]), + .Q(\^core_control_regs[13] [22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][23] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[439]), + .Q(\^core_control_regs[13] [23]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][24] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[440]), + .Q(\^core_control_regs[13] [24]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][25] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[441]), + .Q(\^core_control_regs[13] [25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][26] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[442]), + .Q(\^core_control_regs[13] [26]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][2] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[418]), + .Q(\^core_control_regs[13] [2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][3] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[419]), + .Q(\^core_control_regs[13] [3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][4] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[420]), + .Q(\^core_control_regs[13] [4]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][5] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[421]), + .Q(\^core_control_regs[13] [5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][6] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[422]), + .Q(\^core_control_regs[13] [6]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][7] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[423]), + .Q(\^core_control_regs[13] [7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][8] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[424]), + .Q(\^core_control_regs[13] [8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][9] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[425]), + .Q(\^core_control_regs[13] [9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][0] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(\core_control_regs2_int[14] ), + .Q(\^core_control_regs[14] [0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][10] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[458]), + .Q(\^core_control_regs[14] [10]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][11] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[459]), + .Q(\^core_control_regs[14] [11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][16] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[464]), + .Q(\^core_control_regs[14] [16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][17] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[465]), + .Q(\^core_control_regs[14] [17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][18] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[466]), + .Q(\^core_control_regs[14] [18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][19] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[467]), + .Q(\^core_control_regs[14] [19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][1] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[449]), + .Q(\^core_control_regs[14] [1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][20] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[468]), + .Q(\^core_control_regs[14] [20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][21] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[469]), + .Q(\^core_control_regs[14] [21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][22] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[470]), + .Q(\^core_control_regs[14] [22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][23] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[471]), + .Q(\^core_control_regs[14] [23]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][24] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[472]), + .Q(\^core_control_regs[14] [24]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][25] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[473]), + .Q(\^core_control_regs[14] [25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][26] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[474]), + .Q(\^core_control_regs[14] [26]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][2] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[450]), + .Q(\^core_control_regs[14] [2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][3] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[451]), + .Q(\^core_control_regs[14] [3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][4] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[452]), + .Q(\^core_control_regs[14] [4]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][5] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[453]), + .Q(\^core_control_regs[14] [5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][6] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[454]), + .Q(\^core_control_regs[14] [6]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][7] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[455]), + .Q(\^core_control_regs[14] [7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][8] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[456]), + .Q(\^core_control_regs[14] [8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][9] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[457]), + .Q(\^core_control_regs[14] [9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][0] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(\core_control_regs2_int[15] ), + .Q(\^core_control_regs[15] [0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][10] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[490]), + .Q(\^core_control_regs[15] [10]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][11] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[491]), + .Q(\^core_control_regs[15] [11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][16] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[496]), + .Q(\^core_control_regs[15] [16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][17] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[497]), + .Q(\^core_control_regs[15] [17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][18] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[498]), + .Q(\^core_control_regs[15] [18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][19] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[499]), + .Q(\^core_control_regs[15] [19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][1] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[481]), + .Q(\^core_control_regs[15] [1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][20] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[500]), + .Q(\^core_control_regs[15] [20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][21] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[501]), + .Q(\^core_control_regs[15] [21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][22] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[502]), + .Q(\^core_control_regs[15] [22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][23] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[503]), + .Q(\^core_control_regs[15] [23]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][24] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[504]), + .Q(\^core_control_regs[15] [24]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][25] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[505]), + .Q(\^core_control_regs[15] [25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][26] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[506]), + .Q(\^core_control_regs[15] [26]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][2] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[482]), + .Q(\^core_control_regs[15] [2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][3] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[483]), + .Q(\^core_control_regs[15] [3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][4] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[484]), + .Q(\^core_control_regs[15] [4]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][5] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[485]), + .Q(\^core_control_regs[15] [5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][6] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[486]), + .Q(\^core_control_regs[15] [6]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][7] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[487]), + .Q(\^core_control_regs[15] [7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][8] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[488]), + .Q(\^core_control_regs[15] [8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][9] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[489]), + .Q(\^core_control_regs[15] [9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][0] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(\core_control_regs2_int[1] ), + .Q(\^core_control_regs[1] [0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][10] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[42]), + .Q(\^core_control_regs[1] [10]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][11] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[43]), + .Q(\^core_control_regs[1] [11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][16] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[48]), + .Q(\^core_control_regs[1] [16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][17] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[49]), + .Q(\^core_control_regs[1] [17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][18] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[50]), + .Q(\^core_control_regs[1] [18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][19] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[51]), + .Q(\^core_control_regs[1] [19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][1] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[33]), + .Q(\^core_control_regs[1] [1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][20] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[52]), + .Q(\^core_control_regs[1] [20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][21] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[53]), + .Q(\^core_control_regs[1] [21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][22] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[54]), + .Q(\^core_control_regs[1] [22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][23] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[55]), + .Q(\^core_control_regs[1] [23]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][24] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[56]), + .Q(\^core_control_regs[1] [24]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][25] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[57]), + .Q(\^core_control_regs[1] [25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][26] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[58]), + .Q(\^core_control_regs[1] [26]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][2] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[34]), + .Q(\^core_control_regs[1] [2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][3] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[35]), + .Q(\^core_control_regs[1] [3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][4] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[36]), + .Q(\^core_control_regs[1] [4]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][5] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[37]), + .Q(\^core_control_regs[1] [5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][6] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[38]), + .Q(\^core_control_regs[1] [6]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][7] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[39]), + .Q(\^core_control_regs[1] [7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][8] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[40]), + .Q(\^core_control_regs[1] [8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][9] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[41]), + .Q(\^core_control_regs[1] [9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][0] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(\core_control_regs2_int[2] ), + .Q(\^core_control_regs[2] [0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][10] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[74]), + .Q(\^core_control_regs[2] [10]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][11] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[75]), + .Q(\^core_control_regs[2] [11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][16] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[80]), + .Q(\^core_control_regs[2] [16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][17] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[81]), + .Q(\^core_control_regs[2] [17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][18] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[82]), + .Q(\^core_control_regs[2] [18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][19] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[83]), + .Q(\^core_control_regs[2] [19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][1] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[65]), + .Q(\^core_control_regs[2] [1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][20] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[84]), + .Q(\^core_control_regs[2] [20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][21] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[85]), + .Q(\^core_control_regs[2] [21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][22] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[86]), + .Q(\^core_control_regs[2] [22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][23] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[87]), + .Q(\^core_control_regs[2] [23]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][24] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[88]), + .Q(\^core_control_regs[2] [24]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][25] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[89]), + .Q(\^core_control_regs[2] [25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][26] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[90]), + .Q(\^core_control_regs[2] [26]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][2] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[66]), + .Q(\^core_control_regs[2] [2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][3] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[67]), + .Q(\^core_control_regs[2] [3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][4] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[68]), + .Q(\^core_control_regs[2] [4]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][5] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[69]), + .Q(\^core_control_regs[2] [5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][6] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[70]), + .Q(\^core_control_regs[2] [6]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][7] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[71]), + .Q(\^core_control_regs[2] [7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][8] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[72]), + .Q(\^core_control_regs[2] [8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][9] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[73]), + .Q(\^core_control_regs[2] [9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][0] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(\core_control_regs2_int[3] ), + .Q(\^core_control_regs[3] [0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][10] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[106]), + .Q(\^core_control_regs[3] [10]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][11] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[107]), + .Q(\^core_control_regs[3] [11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][16] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[112]), + .Q(\^core_control_regs[3] [16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][17] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[113]), + .Q(\^core_control_regs[3] [17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][18] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[114]), + .Q(\^core_control_regs[3] [18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][19] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[115]), + .Q(\^core_control_regs[3] [19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][1] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[97]), + .Q(\^core_control_regs[3] [1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][20] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[116]), + .Q(\^core_control_regs[3] [20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][21] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[117]), + .Q(\^core_control_regs[3] [21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][22] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[118]), + .Q(\^core_control_regs[3] [22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][23] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[119]), + .Q(\^core_control_regs[3] [23]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][24] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[120]), + .Q(\^core_control_regs[3] [24]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][25] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[121]), + .Q(\^core_control_regs[3] [25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][26] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[122]), + .Q(\^core_control_regs[3] [26]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][2] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[98]), + .Q(\^core_control_regs[3] [2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][3] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[99]), + .Q(\^core_control_regs[3] [3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][4] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[100]), + .Q(\^core_control_regs[3] [4]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][5] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[101]), + .Q(\^core_control_regs[3] [5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][6] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[102]), + .Q(\^core_control_regs[3] [6]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][7] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[103]), + .Q(\^core_control_regs[3] [7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][8] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[104]), + .Q(\^core_control_regs[3] [8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][9] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[105]), + .Q(\^core_control_regs[3] [9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][0] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(\core_control_regs2_int[4] ), + .Q(\^core_control_regs[4] [0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][10] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[138]), + .Q(\^core_control_regs[4] [10]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][11] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[139]), + .Q(\^core_control_regs[4] [11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][16] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[144]), + .Q(\^core_control_regs[4] [16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][17] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[145]), + .Q(\^core_control_regs[4] [17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][18] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[146]), + .Q(\^core_control_regs[4] [18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][19] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[147]), + .Q(\^core_control_regs[4] [19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][1] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[129]), + .Q(\^core_control_regs[4] [1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][20] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[148]), + .Q(\^core_control_regs[4] [20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][21] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[149]), + .Q(\^core_control_regs[4] [21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][22] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[150]), + .Q(\^core_control_regs[4] [22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][23] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[151]), + .Q(\^core_control_regs[4] [23]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][24] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[152]), + .Q(\^core_control_regs[4] [24]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][25] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[153]), + .Q(\^core_control_regs[4] [25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][26] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[154]), + .Q(\^core_control_regs[4] [26]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][2] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[130]), + .Q(\^core_control_regs[4] [2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][3] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[131]), + .Q(\^core_control_regs[4] [3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][4] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[132]), + .Q(\^core_control_regs[4] [4]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][5] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[133]), + .Q(\^core_control_regs[4] [5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][6] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[134]), + .Q(\^core_control_regs[4] [6]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][7] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[135]), + .Q(\^core_control_regs[4] [7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][8] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[136]), + .Q(\^core_control_regs[4] [8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][9] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[137]), + .Q(\^core_control_regs[4] [9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][0] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(\core_control_regs2_int[5] ), + .Q(\^core_control_regs[5] [0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][10] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[170]), + .Q(\^core_control_regs[5] [10]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][11] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[171]), + .Q(\^core_control_regs[5] [11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][16] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[176]), + .Q(\^core_control_regs[5] [16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][17] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[177]), + .Q(\^core_control_regs[5] [17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][18] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[178]), + .Q(\^core_control_regs[5] [18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][19] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[179]), + .Q(\^core_control_regs[5] [19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][1] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[161]), + .Q(\^core_control_regs[5] [1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][20] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[180]), + .Q(\^core_control_regs[5] [20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][21] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[181]), + .Q(\^core_control_regs[5] [21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][22] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[182]), + .Q(\^core_control_regs[5] [22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][23] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[183]), + .Q(\^core_control_regs[5] [23]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][24] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[184]), + .Q(\^core_control_regs[5] [24]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][25] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[185]), + .Q(\^core_control_regs[5] [25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][26] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[186]), + .Q(\^core_control_regs[5] [26]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][2] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[162]), + .Q(\^core_control_regs[5] [2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][3] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[163]), + .Q(\^core_control_regs[5] [3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][4] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[164]), + .Q(\^core_control_regs[5] [4]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][5] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[165]), + .Q(\^core_control_regs[5] [5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][6] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[166]), + .Q(\^core_control_regs[5] [6]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][7] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[167]), + .Q(\^core_control_regs[5] [7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][8] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[168]), + .Q(\^core_control_regs[5] [8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][9] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[169]), + .Q(\^core_control_regs[5] [9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][0] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(\core_control_regs2_int[6] ), + .Q(\^core_control_regs[6] [0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][10] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[202]), + .Q(\^core_control_regs[6] [10]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][11] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[203]), + .Q(\^core_control_regs[6] [11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][16] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[208]), + .Q(\^core_control_regs[6] [16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][17] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[209]), + .Q(\^core_control_regs[6] [17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][18] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[210]), + .Q(\^core_control_regs[6] [18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][19] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[211]), + .Q(\^core_control_regs[6] [19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][1] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[193]), + .Q(\^core_control_regs[6] [1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][20] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[212]), + .Q(\^core_control_regs[6] [20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][21] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[213]), + .Q(\^core_control_regs[6] [21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][22] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[214]), + .Q(\^core_control_regs[6] [22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][23] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[215]), + .Q(\^core_control_regs[6] [23]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][24] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[216]), + .Q(\^core_control_regs[6] [24]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][25] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[217]), + .Q(\^core_control_regs[6] [25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][26] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[218]), + .Q(\^core_control_regs[6] [26]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][2] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[194]), + .Q(\^core_control_regs[6] [2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][3] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[195]), + .Q(\^core_control_regs[6] [3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][4] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[196]), + .Q(\^core_control_regs[6] [4]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][5] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[197]), + .Q(\^core_control_regs[6] [5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][6] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[198]), + .Q(\^core_control_regs[6] [6]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][7] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[199]), + .Q(\^core_control_regs[6] [7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][8] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[200]), + .Q(\^core_control_regs[6] [8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][9] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[201]), + .Q(\^core_control_regs[6] [9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][0] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(\core_control_regs2_int[7] ), + .Q(\^core_control_regs[7] [0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][10] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[234]), + .Q(\^core_control_regs[7] [10]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][11] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[235]), + .Q(\^core_control_regs[7] [11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][16] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[240]), + .Q(\^core_control_regs[7] [16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][17] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[241]), + .Q(\^core_control_regs[7] [17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][18] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[242]), + .Q(\^core_control_regs[7] [18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][19] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[243]), + .Q(\^core_control_regs[7] [19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][1] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[225]), + .Q(\^core_control_regs[7] [1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][20] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[244]), + .Q(\^core_control_regs[7] [20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][21] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[245]), + .Q(\^core_control_regs[7] [21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][22] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[246]), + .Q(\^core_control_regs[7] [22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][23] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[247]), + .Q(\^core_control_regs[7] [23]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][24] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[248]), + .Q(\^core_control_regs[7] [24]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][25] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[249]), + .Q(\^core_control_regs[7] [25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][26] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[250]), + .Q(\^core_control_regs[7] [26]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][2] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[226]), + .Q(\^core_control_regs[7] [2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][3] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[227]), + .Q(\^core_control_regs[7] [3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][4] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[228]), + .Q(\^core_control_regs[7] [4]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][5] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[229]), + .Q(\^core_control_regs[7] [5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][6] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[230]), + .Q(\^core_control_regs[7] [6]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][7] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[231]), + .Q(\^core_control_regs[7] [7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][8] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[232]), + .Q(\^core_control_regs[7] [8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][9] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[233]), + .Q(\^core_control_regs[7] [9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][0] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(\core_control_regs2_int[8] ), + .Q(\^core_control_regs[8] [0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][10] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[266]), + .Q(\^core_control_regs[8] [10]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][11] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[267]), + .Q(\^core_control_regs[8] [11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][16] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[272]), + .Q(\^core_control_regs[8] [16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][17] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[273]), + .Q(\^core_control_regs[8] [17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][18] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[274]), + .Q(\^core_control_regs[8] [18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][19] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[275]), + .Q(\^core_control_regs[8] [19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][1] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[257]), + .Q(\^core_control_regs[8] [1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][20] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[276]), + .Q(\^core_control_regs[8] [20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][21] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[277]), + .Q(\^core_control_regs[8] [21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][22] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[278]), + .Q(\^core_control_regs[8] [22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][23] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[279]), + .Q(\^core_control_regs[8] [23]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][24] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[280]), + .Q(\^core_control_regs[8] [24]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][25] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[281]), + .Q(\^core_control_regs[8] [25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][26] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[282]), + .Q(\^core_control_regs[8] [26]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][2] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[258]), + .Q(\^core_control_regs[8] [2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][3] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[259]), + .Q(\^core_control_regs[8] [3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][4] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[260]), + .Q(\^core_control_regs[8] [4]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][5] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[261]), + .Q(\^core_control_regs[8] [5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][6] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[262]), + .Q(\^core_control_regs[8] [6]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][7] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[263]), + .Q(\^core_control_regs[8] [7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][8] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[264]), + .Q(\^core_control_regs[8] [8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][9] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[265]), + .Q(\^core_control_regs[8] [9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][0] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(\core_control_regs2_int[9] ), + .Q(\^core_control_regs[9] [0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][10] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[298]), + .Q(\^core_control_regs[9] [10]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][11] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[299]), + .Q(\^core_control_regs[9] [11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][16] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[304]), + .Q(\^core_control_regs[9] [16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][17] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[305]), + .Q(\^core_control_regs[9] [17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][18] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[306]), + .Q(\^core_control_regs[9] [18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][19] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[307]), + .Q(\^core_control_regs[9] [19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][1] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[289]), + .Q(\^core_control_regs[9] [1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][20] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[308]), + .Q(\^core_control_regs[9] [20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][21] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[309]), + .Q(\^core_control_regs[9] [21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][22] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[310]), + .Q(\^core_control_regs[9] [22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][23] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[311]), + .Q(\^core_control_regs[9] [23]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][24] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[312]), + .Q(\^core_control_regs[9] [24]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][25] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[313]), + .Q(\^core_control_regs[9] [25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][26] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[314]), + .Q(\^core_control_regs[9] [26]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][2] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[290]), + .Q(\^core_control_regs[9] [2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][3] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[291]), + .Q(\^core_control_regs[9] [3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][4] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[292]), + .Q(\^core_control_regs[9] [4]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][5] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[293]), + .Q(\^core_control_regs[9] [5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][6] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[294]), + .Q(\^core_control_regs[9] [6]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][7] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[295]), + .Q(\^core_control_regs[9] [7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][8] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[296]), + .Q(\^core_control_regs[9] [8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][9] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(core_regs[297]), + .Q(\^core_control_regs[9] [9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0] + (.C(vid_aclk), + .CE(\core_control_regs_int[0] ), + .D(ipif_data_out[0]), + .Q(\core_control_regs2_int[0] ), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][10] + (.C(vid_aclk), + .CE(\core_control_regs_int[0] ), + .D(ipif_data_out[10]), + .Q(core_regs[10]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][11] + (.C(vid_aclk), + .CE(\core_control_regs_int[0] ), + .D(ipif_data_out[11]), + .Q(core_regs[11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][16] + (.C(vid_aclk), + .CE(\core_control_regs_int[0] ), + .D(ipif_data_out[16]), + .Q(core_regs[16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][17] + (.C(vid_aclk), + .CE(\core_control_regs_int[0] ), + .D(ipif_data_out[17]), + .Q(core_regs[17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][18] + (.C(vid_aclk), + .CE(\core_control_regs_int[0] ), + .D(ipif_data_out[18]), + .Q(core_regs[18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][19] + (.C(vid_aclk), + .CE(\core_control_regs_int[0] ), + .D(ipif_data_out[19]), + .Q(core_regs[19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][1] + (.C(vid_aclk), + .CE(\core_control_regs_int[0] ), + .D(ipif_data_out[1]), + .Q(core_regs[1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][20] + (.C(vid_aclk), + .CE(\core_control_regs_int[0] ), + .D(ipif_data_out[20]), + .Q(core_regs[20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][21] + (.C(vid_aclk), + .CE(\core_control_regs_int[0] ), + .D(ipif_data_out[21]), + .Q(core_regs[21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][22] + (.C(vid_aclk), + .CE(\core_control_regs_int[0] ), + .D(ipif_data_out[22]), + .Q(core_regs[22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][23] + (.C(vid_aclk), + .CE(\core_control_regs_int[0] ), + .D(ipif_data_out[23]), + .Q(core_regs[23]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][24] + (.C(vid_aclk), + .CE(\core_control_regs_int[0] ), + .D(ipif_data_out[24]), + .Q(core_regs[24]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][25] + (.C(vid_aclk), + .CE(\core_control_regs_int[0] ), + .D(ipif_data_out[25]), + .Q(core_regs[25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][26] + (.C(vid_aclk), + .CE(\core_control_regs_int[0] ), + .D(ipif_data_out[26]), + .Q(core_regs[26]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][2] + (.C(vid_aclk), + .CE(\core_control_regs_int[0] ), + .D(ipif_data_out[2]), + .Q(core_regs[2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][3] + (.C(vid_aclk), + .CE(\core_control_regs_int[0] ), + .D(ipif_data_out[3]), + .Q(core_regs[3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][4] + (.C(vid_aclk), + .CE(\core_control_regs_int[0] ), + .D(ipif_data_out[4]), + .Q(core_regs[4]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][5] + (.C(vid_aclk), + .CE(\core_control_regs_int[0] ), + .D(ipif_data_out[5]), + .Q(core_regs[5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][6] + (.C(vid_aclk), + .CE(\core_control_regs_int[0] ), + .D(ipif_data_out[6]), + .Q(core_regs[6]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][7] + (.C(vid_aclk), + .CE(\core_control_regs_int[0] ), + .D(ipif_data_out[7]), + .Q(core_regs[7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][8] + (.C(vid_aclk), + .CE(\core_control_regs_int[0] ), + .D(ipif_data_out[8]), + .Q(core_regs[8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][9] + (.C(vid_aclk), + .CE(\core_control_regs_int[0] ), + .D(ipif_data_out[9]), + .Q(core_regs[9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][0] + (.C(vid_aclk), + .CE(\core_control_regs_int[10] ), + .D(ipif_data_out[0]), + .Q(\core_control_regs2_int[10] ), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][10] + (.C(vid_aclk), + .CE(\core_control_regs_int[10] ), + .D(ipif_data_out[10]), + .Q(core_regs[330]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][11] + (.C(vid_aclk), + .CE(\core_control_regs_int[10] ), + .D(ipif_data_out[11]), + .Q(core_regs[331]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][16] + (.C(vid_aclk), + .CE(\core_control_regs_int[10] ), + .D(ipif_data_out[16]), + .Q(core_regs[336]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][17] + (.C(vid_aclk), + .CE(\core_control_regs_int[10] ), + .D(ipif_data_out[17]), + .Q(core_regs[337]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][18] + (.C(vid_aclk), + .CE(\core_control_regs_int[10] ), + .D(ipif_data_out[18]), + .Q(core_regs[338]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][19] + (.C(vid_aclk), + .CE(\core_control_regs_int[10] ), + .D(ipif_data_out[19]), + .Q(core_regs[339]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][1] + (.C(vid_aclk), + .CE(\core_control_regs_int[10] ), + .D(ipif_data_out[1]), + .Q(core_regs[321]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][20] + (.C(vid_aclk), + .CE(\core_control_regs_int[10] ), + .D(ipif_data_out[20]), + .Q(core_regs[340]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][21] + (.C(vid_aclk), + .CE(\core_control_regs_int[10] ), + .D(ipif_data_out[21]), + .Q(core_regs[341]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][22] + (.C(vid_aclk), + .CE(\core_control_regs_int[10] ), + .D(ipif_data_out[22]), + .Q(core_regs[342]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][23] + (.C(vid_aclk), + .CE(\core_control_regs_int[10] ), + .D(ipif_data_out[23]), + .Q(core_regs[343]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][24] + (.C(vid_aclk), + .CE(\core_control_regs_int[10] ), + .D(ipif_data_out[24]), + .Q(core_regs[344]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][25] + (.C(vid_aclk), + .CE(\core_control_regs_int[10] ), + .D(ipif_data_out[25]), + .Q(core_regs[345]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][26] + (.C(vid_aclk), + .CE(\core_control_regs_int[10] ), + .D(ipif_data_out[26]), + .Q(core_regs[346]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][2] + (.C(vid_aclk), + .CE(\core_control_regs_int[10] ), + .D(ipif_data_out[2]), + .Q(core_regs[322]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][3] + (.C(vid_aclk), + .CE(\core_control_regs_int[10] ), + .D(ipif_data_out[3]), + .Q(core_regs[323]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][4] + (.C(vid_aclk), + .CE(\core_control_regs_int[10] ), + .D(ipif_data_out[4]), + .Q(core_regs[324]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][5] + (.C(vid_aclk), + .CE(\core_control_regs_int[10] ), + .D(ipif_data_out[5]), + .Q(core_regs[325]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][6] + (.C(vid_aclk), + .CE(\core_control_regs_int[10] ), + .D(ipif_data_out[6]), + .Q(core_regs[326]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][7] + (.C(vid_aclk), + .CE(\core_control_regs_int[10] ), + .D(ipif_data_out[7]), + .Q(core_regs[327]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][8] + (.C(vid_aclk), + .CE(\core_control_regs_int[10] ), + .D(ipif_data_out[8]), + .Q(core_regs[328]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][9] + (.C(vid_aclk), + .CE(\core_control_regs_int[10] ), + .D(ipif_data_out[9]), + .Q(core_regs[329]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][0] + (.C(vid_aclk), + .CE(\core_control_regs_int[11] ), + .D(ipif_data_out[0]), + .Q(\core_control_regs2_int[11] ), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][10] + (.C(vid_aclk), + .CE(\core_control_regs_int[11] ), + .D(ipif_data_out[10]), + .Q(core_regs[362]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][11] + (.C(vid_aclk), + .CE(\core_control_regs_int[11] ), + .D(ipif_data_out[11]), + .Q(core_regs[363]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][16] + (.C(vid_aclk), + .CE(\core_control_regs_int[11] ), + .D(ipif_data_out[16]), + .Q(core_regs[368]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][17] + (.C(vid_aclk), + .CE(\core_control_regs_int[11] ), + .D(ipif_data_out[17]), + .Q(core_regs[369]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][18] + (.C(vid_aclk), + .CE(\core_control_regs_int[11] ), + .D(ipif_data_out[18]), + .Q(core_regs[370]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][19] + (.C(vid_aclk), + .CE(\core_control_regs_int[11] ), + .D(ipif_data_out[19]), + .Q(core_regs[371]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][1] + (.C(vid_aclk), + .CE(\core_control_regs_int[11] ), + .D(ipif_data_out[1]), + .Q(core_regs[353]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][20] + (.C(vid_aclk), + .CE(\core_control_regs_int[11] ), + .D(ipif_data_out[20]), + .Q(core_regs[372]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][21] + (.C(vid_aclk), + .CE(\core_control_regs_int[11] ), + .D(ipif_data_out[21]), + .Q(core_regs[373]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][22] + (.C(vid_aclk), + .CE(\core_control_regs_int[11] ), + .D(ipif_data_out[22]), + .Q(core_regs[374]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][23] + (.C(vid_aclk), + .CE(\core_control_regs_int[11] ), + .D(ipif_data_out[23]), + .Q(core_regs[375]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][24] + (.C(vid_aclk), + .CE(\core_control_regs_int[11] ), + .D(ipif_data_out[24]), + .Q(core_regs[376]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][25] + (.C(vid_aclk), + .CE(\core_control_regs_int[11] ), + .D(ipif_data_out[25]), + .Q(core_regs[377]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][26] + (.C(vid_aclk), + .CE(\core_control_regs_int[11] ), + .D(ipif_data_out[26]), + .Q(core_regs[378]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][2] + (.C(vid_aclk), + .CE(\core_control_regs_int[11] ), + .D(ipif_data_out[2]), + .Q(core_regs[354]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][3] + (.C(vid_aclk), + .CE(\core_control_regs_int[11] ), + .D(ipif_data_out[3]), + .Q(core_regs[355]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][4] + (.C(vid_aclk), + .CE(\core_control_regs_int[11] ), + .D(ipif_data_out[4]), + .Q(core_regs[356]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][5] + (.C(vid_aclk), + .CE(\core_control_regs_int[11] ), + .D(ipif_data_out[5]), + .Q(core_regs[357]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][6] + (.C(vid_aclk), + .CE(\core_control_regs_int[11] ), + .D(ipif_data_out[6]), + .Q(core_regs[358]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][7] + (.C(vid_aclk), + .CE(\core_control_regs_int[11] ), + .D(ipif_data_out[7]), + .Q(core_regs[359]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][8] + (.C(vid_aclk), + .CE(\core_control_regs_int[11] ), + .D(ipif_data_out[8]), + .Q(core_regs[360]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][9] + (.C(vid_aclk), + .CE(\core_control_regs_int[11] ), + .D(ipif_data_out[9]), + .Q(core_regs[361]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][0] + (.C(vid_aclk), + .CE(\core_control_regs_int[12] ), + .D(ipif_data_out[0]), + .Q(\core_control_regs2_int[12] ), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][10] + (.C(vid_aclk), + .CE(\core_control_regs_int[12] ), + .D(ipif_data_out[10]), + .Q(core_regs[394]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][11] + (.C(vid_aclk), + .CE(\core_control_regs_int[12] ), + .D(ipif_data_out[11]), + .Q(core_regs[395]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][16] + (.C(vid_aclk), + .CE(\core_control_regs_int[12] ), + .D(ipif_data_out[16]), + .Q(core_regs[400]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][17] + (.C(vid_aclk), + .CE(\core_control_regs_int[12] ), + .D(ipif_data_out[17]), + .Q(core_regs[401]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][18] + (.C(vid_aclk), + .CE(\core_control_regs_int[12] ), + .D(ipif_data_out[18]), + .Q(core_regs[402]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][19] + (.C(vid_aclk), + .CE(\core_control_regs_int[12] ), + .D(ipif_data_out[19]), + .Q(core_regs[403]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][1] + (.C(vid_aclk), + .CE(\core_control_regs_int[12] ), + .D(ipif_data_out[1]), + .Q(core_regs[385]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][20] + (.C(vid_aclk), + .CE(\core_control_regs_int[12] ), + .D(ipif_data_out[20]), + .Q(core_regs[404]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][21] + (.C(vid_aclk), + .CE(\core_control_regs_int[12] ), + .D(ipif_data_out[21]), + .Q(core_regs[405]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][22] + (.C(vid_aclk), + .CE(\core_control_regs_int[12] ), + .D(ipif_data_out[22]), + .Q(core_regs[406]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][23] + (.C(vid_aclk), + .CE(\core_control_regs_int[12] ), + .D(ipif_data_out[23]), + .Q(core_regs[407]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][24] + (.C(vid_aclk), + .CE(\core_control_regs_int[12] ), + .D(ipif_data_out[24]), + .Q(core_regs[408]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][25] + (.C(vid_aclk), + .CE(\core_control_regs_int[12] ), + .D(ipif_data_out[25]), + .Q(core_regs[409]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][26] + (.C(vid_aclk), + .CE(\core_control_regs_int[12] ), + .D(ipif_data_out[26]), + .Q(core_regs[410]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][2] + (.C(vid_aclk), + .CE(\core_control_regs_int[12] ), + .D(ipif_data_out[2]), + .Q(core_regs[386]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][3] + (.C(vid_aclk), + .CE(\core_control_regs_int[12] ), + .D(ipif_data_out[3]), + .Q(core_regs[387]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][4] + (.C(vid_aclk), + .CE(\core_control_regs_int[12] ), + .D(ipif_data_out[4]), + .Q(core_regs[388]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][5] + (.C(vid_aclk), + .CE(\core_control_regs_int[12] ), + .D(ipif_data_out[5]), + .Q(core_regs[389]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][6] + (.C(vid_aclk), + .CE(\core_control_regs_int[12] ), + .D(ipif_data_out[6]), + .Q(core_regs[390]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][7] + (.C(vid_aclk), + .CE(\core_control_regs_int[12] ), + .D(ipif_data_out[7]), + .Q(core_regs[391]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][8] + (.C(vid_aclk), + .CE(\core_control_regs_int[12] ), + .D(ipif_data_out[8]), + .Q(core_regs[392]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][9] + (.C(vid_aclk), + .CE(\core_control_regs_int[12] ), + .D(ipif_data_out[9]), + .Q(core_regs[393]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][0] + (.C(vid_aclk), + .CE(\core_control_regs_int[13] ), + .D(ipif_data_out[0]), + .Q(\core_control_regs2_int[13] ), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][10] + (.C(vid_aclk), + .CE(\core_control_regs_int[13] ), + .D(ipif_data_out[10]), + .Q(core_regs[426]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][11] + (.C(vid_aclk), + .CE(\core_control_regs_int[13] ), + .D(ipif_data_out[11]), + .Q(core_regs[427]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][16] + (.C(vid_aclk), + .CE(\core_control_regs_int[13] ), + .D(ipif_data_out[16]), + .Q(core_regs[432]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][17] + (.C(vid_aclk), + .CE(\core_control_regs_int[13] ), + .D(ipif_data_out[17]), + .Q(core_regs[433]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][18] + (.C(vid_aclk), + .CE(\core_control_regs_int[13] ), + .D(ipif_data_out[18]), + .Q(core_regs[434]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][19] + (.C(vid_aclk), + .CE(\core_control_regs_int[13] ), + .D(ipif_data_out[19]), + .Q(core_regs[435]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][1] + (.C(vid_aclk), + .CE(\core_control_regs_int[13] ), + .D(ipif_data_out[1]), + .Q(core_regs[417]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][20] + (.C(vid_aclk), + .CE(\core_control_regs_int[13] ), + .D(ipif_data_out[20]), + .Q(core_regs[436]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][21] + (.C(vid_aclk), + .CE(\core_control_regs_int[13] ), + .D(ipif_data_out[21]), + .Q(core_regs[437]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][22] + (.C(vid_aclk), + .CE(\core_control_regs_int[13] ), + .D(ipif_data_out[22]), + .Q(core_regs[438]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][23] + (.C(vid_aclk), + .CE(\core_control_regs_int[13] ), + .D(ipif_data_out[23]), + .Q(core_regs[439]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][24] + (.C(vid_aclk), + .CE(\core_control_regs_int[13] ), + .D(ipif_data_out[24]), + .Q(core_regs[440]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][25] + (.C(vid_aclk), + .CE(\core_control_regs_int[13] ), + .D(ipif_data_out[25]), + .Q(core_regs[441]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][26] + (.C(vid_aclk), + .CE(\core_control_regs_int[13] ), + .D(ipif_data_out[26]), + .Q(core_regs[442]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][2] + (.C(vid_aclk), + .CE(\core_control_regs_int[13] ), + .D(ipif_data_out[2]), + .Q(core_regs[418]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][3] + (.C(vid_aclk), + .CE(\core_control_regs_int[13] ), + .D(ipif_data_out[3]), + .Q(core_regs[419]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][4] + (.C(vid_aclk), + .CE(\core_control_regs_int[13] ), + .D(ipif_data_out[4]), + .Q(core_regs[420]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][5] + (.C(vid_aclk), + .CE(\core_control_regs_int[13] ), + .D(ipif_data_out[5]), + .Q(core_regs[421]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][6] + (.C(vid_aclk), + .CE(\core_control_regs_int[13] ), + .D(ipif_data_out[6]), + .Q(core_regs[422]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][7] + (.C(vid_aclk), + .CE(\core_control_regs_int[13] ), + .D(ipif_data_out[7]), + .Q(core_regs[423]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][8] + (.C(vid_aclk), + .CE(\core_control_regs_int[13] ), + .D(ipif_data_out[8]), + .Q(core_regs[424]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][9] + (.C(vid_aclk), + .CE(\core_control_regs_int[13] ), + .D(ipif_data_out[9]), + .Q(core_regs[425]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][0] + (.C(vid_aclk), + .CE(\core_control_regs_int[14] ), + .D(ipif_data_out[0]), + .Q(\core_control_regs2_int[14] ), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][10] + (.C(vid_aclk), + .CE(\core_control_regs_int[14] ), + .D(ipif_data_out[10]), + .Q(core_regs[458]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][11] + (.C(vid_aclk), + .CE(\core_control_regs_int[14] ), + .D(ipif_data_out[11]), + .Q(core_regs[459]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][16] + (.C(vid_aclk), + .CE(\core_control_regs_int[14] ), + .D(ipif_data_out[16]), + .Q(core_regs[464]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][17] + (.C(vid_aclk), + .CE(\core_control_regs_int[14] ), + .D(ipif_data_out[17]), + .Q(core_regs[465]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][18] + (.C(vid_aclk), + .CE(\core_control_regs_int[14] ), + .D(ipif_data_out[18]), + .Q(core_regs[466]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][19] + (.C(vid_aclk), + .CE(\core_control_regs_int[14] ), + .D(ipif_data_out[19]), + .Q(core_regs[467]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][1] + (.C(vid_aclk), + .CE(\core_control_regs_int[14] ), + .D(ipif_data_out[1]), + .Q(core_regs[449]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][20] + (.C(vid_aclk), + .CE(\core_control_regs_int[14] ), + .D(ipif_data_out[20]), + .Q(core_regs[468]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][21] + (.C(vid_aclk), + .CE(\core_control_regs_int[14] ), + .D(ipif_data_out[21]), + .Q(core_regs[469]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][22] + (.C(vid_aclk), + .CE(\core_control_regs_int[14] ), + .D(ipif_data_out[22]), + .Q(core_regs[470]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][23] + (.C(vid_aclk), + .CE(\core_control_regs_int[14] ), + .D(ipif_data_out[23]), + .Q(core_regs[471]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][24] + (.C(vid_aclk), + .CE(\core_control_regs_int[14] ), + .D(ipif_data_out[24]), + .Q(core_regs[472]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][25] + (.C(vid_aclk), + .CE(\core_control_regs_int[14] ), + .D(ipif_data_out[25]), + .Q(core_regs[473]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][26] + (.C(vid_aclk), + .CE(\core_control_regs_int[14] ), + .D(ipif_data_out[26]), + .Q(core_regs[474]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][2] + (.C(vid_aclk), + .CE(\core_control_regs_int[14] ), + .D(ipif_data_out[2]), + .Q(core_regs[450]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][3] + (.C(vid_aclk), + .CE(\core_control_regs_int[14] ), + .D(ipif_data_out[3]), + .Q(core_regs[451]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][4] + (.C(vid_aclk), + .CE(\core_control_regs_int[14] ), + .D(ipif_data_out[4]), + .Q(core_regs[452]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][5] + (.C(vid_aclk), + .CE(\core_control_regs_int[14] ), + .D(ipif_data_out[5]), + .Q(core_regs[453]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][6] + (.C(vid_aclk), + .CE(\core_control_regs_int[14] ), + .D(ipif_data_out[6]), + .Q(core_regs[454]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][7] + (.C(vid_aclk), + .CE(\core_control_regs_int[14] ), + .D(ipif_data_out[7]), + .Q(core_regs[455]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][8] + (.C(vid_aclk), + .CE(\core_control_regs_int[14] ), + .D(ipif_data_out[8]), + .Q(core_regs[456]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][9] + (.C(vid_aclk), + .CE(\core_control_regs_int[14] ), + .D(ipif_data_out[9]), + .Q(core_regs[457]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][0] + (.C(vid_aclk), + .CE(\core_control_regs_int[15] ), + .D(ipif_data_out[0]), + .Q(\core_control_regs2_int[15] ), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][10] + (.C(vid_aclk), + .CE(\core_control_regs_int[15] ), + .D(ipif_data_out[10]), + .Q(core_regs[490]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][11] + (.C(vid_aclk), + .CE(\core_control_regs_int[15] ), + .D(ipif_data_out[11]), + .Q(core_regs[491]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][16] + (.C(vid_aclk), + .CE(\core_control_regs_int[15] ), + .D(ipif_data_out[16]), + .Q(core_regs[496]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][17] + (.C(vid_aclk), + .CE(\core_control_regs_int[15] ), + .D(ipif_data_out[17]), + .Q(core_regs[497]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][18] + (.C(vid_aclk), + .CE(\core_control_regs_int[15] ), + .D(ipif_data_out[18]), + .Q(core_regs[498]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][19] + (.C(vid_aclk), + .CE(\core_control_regs_int[15] ), + .D(ipif_data_out[19]), + .Q(core_regs[499]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][1] + (.C(vid_aclk), + .CE(\core_control_regs_int[15] ), + .D(ipif_data_out[1]), + .Q(core_regs[481]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][20] + (.C(vid_aclk), + .CE(\core_control_regs_int[15] ), + .D(ipif_data_out[20]), + .Q(core_regs[500]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][21] + (.C(vid_aclk), + .CE(\core_control_regs_int[15] ), + .D(ipif_data_out[21]), + .Q(core_regs[501]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][22] + (.C(vid_aclk), + .CE(\core_control_regs_int[15] ), + .D(ipif_data_out[22]), + .Q(core_regs[502]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][23] + (.C(vid_aclk), + .CE(\core_control_regs_int[15] ), + .D(ipif_data_out[23]), + .Q(core_regs[503]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][24] + (.C(vid_aclk), + .CE(\core_control_regs_int[15] ), + .D(ipif_data_out[24]), + .Q(core_regs[504]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][25] + (.C(vid_aclk), + .CE(\core_control_regs_int[15] ), + .D(ipif_data_out[25]), + .Q(core_regs[505]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][26] + (.C(vid_aclk), + .CE(\core_control_regs_int[15] ), + .D(ipif_data_out[26]), + .Q(core_regs[506]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][2] + (.C(vid_aclk), + .CE(\core_control_regs_int[15] ), + .D(ipif_data_out[2]), + .Q(core_regs[482]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][3] + (.C(vid_aclk), + .CE(\core_control_regs_int[15] ), + .D(ipif_data_out[3]), + .Q(core_regs[483]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][4] + (.C(vid_aclk), + .CE(\core_control_regs_int[15] ), + .D(ipif_data_out[4]), + .Q(core_regs[484]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][5] + (.C(vid_aclk), + .CE(\core_control_regs_int[15] ), + .D(ipif_data_out[5]), + .Q(core_regs[485]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][6] + (.C(vid_aclk), + .CE(\core_control_regs_int[15] ), + .D(ipif_data_out[6]), + .Q(core_regs[486]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][7] + (.C(vid_aclk), + .CE(\core_control_regs_int[15] ), + .D(ipif_data_out[7]), + .Q(core_regs[487]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][8] + (.C(vid_aclk), + .CE(\core_control_regs_int[15] ), + .D(ipif_data_out[8]), + .Q(core_regs[488]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][9] + (.C(vid_aclk), + .CE(\core_control_regs_int[15] ), + .D(ipif_data_out[9]), + .Q(core_regs[489]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][0] + (.C(vid_aclk), + .CE(\core_control_regs_int[16] ), + .D(ipif_data_out[0]), + .Q(\^core_control_regs[16] [0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][10] + (.C(vid_aclk), + .CE(\core_control_regs_int[16] ), + .D(ipif_data_out[10]), + .Q(\^core_control_regs[16] [10]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][11] + (.C(vid_aclk), + .CE(\core_control_regs_int[16] ), + .D(ipif_data_out[11]), + .Q(\^core_control_regs[16] [11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][16] + (.C(vid_aclk), + .CE(\core_control_regs_int[16] ), + .D(ipif_data_out[16]), + .Q(\^core_control_regs[16] [16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][17] + (.C(vid_aclk), + .CE(\core_control_regs_int[16] ), + .D(ipif_data_out[17]), + .Q(\^core_control_regs[16] [17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][18] + (.C(vid_aclk), + .CE(\core_control_regs_int[16] ), + .D(ipif_data_out[18]), + .Q(\^core_control_regs[16] [18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][19] + (.C(vid_aclk), + .CE(\core_control_regs_int[16] ), + .D(ipif_data_out[19]), + .Q(\^core_control_regs[16] [19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][1] + (.C(vid_aclk), + .CE(\core_control_regs_int[16] ), + .D(ipif_data_out[1]), + .Q(\^core_control_regs[16] [1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][20] + (.C(vid_aclk), + .CE(\core_control_regs_int[16] ), + .D(ipif_data_out[20]), + .Q(\^core_control_regs[16] [20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][21] + (.C(vid_aclk), + .CE(\core_control_regs_int[16] ), + .D(ipif_data_out[21]), + .Q(\^core_control_regs[16] [21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][22] + (.C(vid_aclk), + .CE(\core_control_regs_int[16] ), + .D(ipif_data_out[22]), + .Q(\^core_control_regs[16] [22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][23] + (.C(vid_aclk), + .CE(\core_control_regs_int[16] ), + .D(ipif_data_out[23]), + .Q(\^core_control_regs[16] [23]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][24] + (.C(vid_aclk), + .CE(\core_control_regs_int[16] ), + .D(ipif_data_out[24]), + .Q(\^core_control_regs[16] [24]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][25] + (.C(vid_aclk), + .CE(\core_control_regs_int[16] ), + .D(ipif_data_out[25]), + .Q(\^core_control_regs[16] [25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][26] + (.C(vid_aclk), + .CE(\core_control_regs_int[16] ), + .D(ipif_data_out[26]), + .Q(\^core_control_regs[16] [26]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][2] + (.C(vid_aclk), + .CE(\core_control_regs_int[16] ), + .D(ipif_data_out[2]), + .Q(\^core_control_regs[16] [2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][3] + (.C(vid_aclk), + .CE(\core_control_regs_int[16] ), + .D(ipif_data_out[3]), + .Q(\^core_control_regs[16] [3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][4] + (.C(vid_aclk), + .CE(\core_control_regs_int[16] ), + .D(ipif_data_out[4]), + .Q(\^core_control_regs[16] [4]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][5] + (.C(vid_aclk), + .CE(\core_control_regs_int[16] ), + .D(ipif_data_out[5]), + .Q(\^core_control_regs[16] [5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][6] + (.C(vid_aclk), + .CE(\core_control_regs_int[16] ), + .D(ipif_data_out[6]), + .Q(\^core_control_regs[16] [6]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][7] + (.C(vid_aclk), + .CE(\core_control_regs_int[16] ), + .D(ipif_data_out[7]), + .Q(\^core_control_regs[16] [7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][8] + (.C(vid_aclk), + .CE(\core_control_regs_int[16] ), + .D(ipif_data_out[8]), + .Q(\^core_control_regs[16] [8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][9] + (.C(vid_aclk), + .CE(\core_control_regs_int[16] ), + .D(ipif_data_out[9]), + .Q(\^core_control_regs[16] [9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][0] + (.C(vid_aclk), + .CE(\core_control_regs_int[1] ), + .D(ipif_data_out[0]), + .Q(\core_control_regs2_int[1] ), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][10] + (.C(vid_aclk), + .CE(\core_control_regs_int[1] ), + .D(ipif_data_out[10]), + .Q(core_regs[42]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][11] + (.C(vid_aclk), + .CE(\core_control_regs_int[1] ), + .D(ipif_data_out[11]), + .Q(core_regs[43]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][16] + (.C(vid_aclk), + .CE(\core_control_regs_int[1] ), + .D(ipif_data_out[16]), + .Q(core_regs[48]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][17] + (.C(vid_aclk), + .CE(\core_control_regs_int[1] ), + .D(ipif_data_out[17]), + .Q(core_regs[49]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][18] + (.C(vid_aclk), + .CE(\core_control_regs_int[1] ), + .D(ipif_data_out[18]), + .Q(core_regs[50]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][19] + (.C(vid_aclk), + .CE(\core_control_regs_int[1] ), + .D(ipif_data_out[19]), + .Q(core_regs[51]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][1] + (.C(vid_aclk), + .CE(\core_control_regs_int[1] ), + .D(ipif_data_out[1]), + .Q(core_regs[33]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][20] + (.C(vid_aclk), + .CE(\core_control_regs_int[1] ), + .D(ipif_data_out[20]), + .Q(core_regs[52]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][21] + (.C(vid_aclk), + .CE(\core_control_regs_int[1] ), + .D(ipif_data_out[21]), + .Q(core_regs[53]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][22] + (.C(vid_aclk), + .CE(\core_control_regs_int[1] ), + .D(ipif_data_out[22]), + .Q(core_regs[54]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][23] + (.C(vid_aclk), + .CE(\core_control_regs_int[1] ), + .D(ipif_data_out[23]), + .Q(core_regs[55]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][24] + (.C(vid_aclk), + .CE(\core_control_regs_int[1] ), + .D(ipif_data_out[24]), + .Q(core_regs[56]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][25] + (.C(vid_aclk), + .CE(\core_control_regs_int[1] ), + .D(ipif_data_out[25]), + .Q(core_regs[57]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][26] + (.C(vid_aclk), + .CE(\core_control_regs_int[1] ), + .D(ipif_data_out[26]), + .Q(core_regs[58]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][2] + (.C(vid_aclk), + .CE(\core_control_regs_int[1] ), + .D(ipif_data_out[2]), + .Q(core_regs[34]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][3] + (.C(vid_aclk), + .CE(\core_control_regs_int[1] ), + .D(ipif_data_out[3]), + .Q(core_regs[35]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][4] + (.C(vid_aclk), + .CE(\core_control_regs_int[1] ), + .D(ipif_data_out[4]), + .Q(core_regs[36]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][5] + (.C(vid_aclk), + .CE(\core_control_regs_int[1] ), + .D(ipif_data_out[5]), + .Q(core_regs[37]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][6] + (.C(vid_aclk), + .CE(\core_control_regs_int[1] ), + .D(ipif_data_out[6]), + .Q(core_regs[38]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][7] + (.C(vid_aclk), + .CE(\core_control_regs_int[1] ), + .D(ipif_data_out[7]), + .Q(core_regs[39]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][8] + (.C(vid_aclk), + .CE(\core_control_regs_int[1] ), + .D(ipif_data_out[8]), + .Q(core_regs[40]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][9] + (.C(vid_aclk), + .CE(\core_control_regs_int[1] ), + .D(ipif_data_out[9]), + .Q(core_regs[41]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][0] + (.C(vid_aclk), + .CE(\core_control_regs_int[2] ), + .D(ipif_data_out[0]), + .Q(\core_control_regs2_int[2] ), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][10] + (.C(vid_aclk), + .CE(\core_control_regs_int[2] ), + .D(ipif_data_out[10]), + .Q(core_regs[74]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][11] + (.C(vid_aclk), + .CE(\core_control_regs_int[2] ), + .D(ipif_data_out[11]), + .Q(core_regs[75]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][16] + (.C(vid_aclk), + .CE(\core_control_regs_int[2] ), + .D(ipif_data_out[16]), + .Q(core_regs[80]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][17] + (.C(vid_aclk), + .CE(\core_control_regs_int[2] ), + .D(ipif_data_out[17]), + .Q(core_regs[81]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][18] + (.C(vid_aclk), + .CE(\core_control_regs_int[2] ), + .D(ipif_data_out[18]), + .Q(core_regs[82]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][19] + (.C(vid_aclk), + .CE(\core_control_regs_int[2] ), + .D(ipif_data_out[19]), + .Q(core_regs[83]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][1] + (.C(vid_aclk), + .CE(\core_control_regs_int[2] ), + .D(ipif_data_out[1]), + .Q(core_regs[65]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][20] + (.C(vid_aclk), + .CE(\core_control_regs_int[2] ), + .D(ipif_data_out[20]), + .Q(core_regs[84]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][21] + (.C(vid_aclk), + .CE(\core_control_regs_int[2] ), + .D(ipif_data_out[21]), + .Q(core_regs[85]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][22] + (.C(vid_aclk), + .CE(\core_control_regs_int[2] ), + .D(ipif_data_out[22]), + .Q(core_regs[86]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][23] + (.C(vid_aclk), + .CE(\core_control_regs_int[2] ), + .D(ipif_data_out[23]), + .Q(core_regs[87]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][24] + (.C(vid_aclk), + .CE(\core_control_regs_int[2] ), + .D(ipif_data_out[24]), + .Q(core_regs[88]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][25] + (.C(vid_aclk), + .CE(\core_control_regs_int[2] ), + .D(ipif_data_out[25]), + .Q(core_regs[89]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][26] + (.C(vid_aclk), + .CE(\core_control_regs_int[2] ), + .D(ipif_data_out[26]), + .Q(core_regs[90]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][2] + (.C(vid_aclk), + .CE(\core_control_regs_int[2] ), + .D(ipif_data_out[2]), + .Q(core_regs[66]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][3] + (.C(vid_aclk), + .CE(\core_control_regs_int[2] ), + .D(ipif_data_out[3]), + .Q(core_regs[67]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][4] + (.C(vid_aclk), + .CE(\core_control_regs_int[2] ), + .D(ipif_data_out[4]), + .Q(core_regs[68]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][5] + (.C(vid_aclk), + .CE(\core_control_regs_int[2] ), + .D(ipif_data_out[5]), + .Q(core_regs[69]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][6] + (.C(vid_aclk), + .CE(\core_control_regs_int[2] ), + .D(ipif_data_out[6]), + .Q(core_regs[70]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][7] + (.C(vid_aclk), + .CE(\core_control_regs_int[2] ), + .D(ipif_data_out[7]), + .Q(core_regs[71]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][8] + (.C(vid_aclk), + .CE(\core_control_regs_int[2] ), + .D(ipif_data_out[8]), + .Q(core_regs[72]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][9] + (.C(vid_aclk), + .CE(\core_control_regs_int[2] ), + .D(ipif_data_out[9]), + .Q(core_regs[73]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][0] + (.C(vid_aclk), + .CE(\core_control_regs_int[3] ), + .D(ipif_data_out[0]), + .Q(\core_control_regs2_int[3] ), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][10] + (.C(vid_aclk), + .CE(\core_control_regs_int[3] ), + .D(ipif_data_out[10]), + .Q(core_regs[106]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][11] + (.C(vid_aclk), + .CE(\core_control_regs_int[3] ), + .D(ipif_data_out[11]), + .Q(core_regs[107]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][16] + (.C(vid_aclk), + .CE(\core_control_regs_int[3] ), + .D(ipif_data_out[16]), + .Q(core_regs[112]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][17] + (.C(vid_aclk), + .CE(\core_control_regs_int[3] ), + .D(ipif_data_out[17]), + .Q(core_regs[113]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][18] + (.C(vid_aclk), + .CE(\core_control_regs_int[3] ), + .D(ipif_data_out[18]), + .Q(core_regs[114]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][19] + (.C(vid_aclk), + .CE(\core_control_regs_int[3] ), + .D(ipif_data_out[19]), + .Q(core_regs[115]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][1] + (.C(vid_aclk), + .CE(\core_control_regs_int[3] ), + .D(ipif_data_out[1]), + .Q(core_regs[97]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][20] + (.C(vid_aclk), + .CE(\core_control_regs_int[3] ), + .D(ipif_data_out[20]), + .Q(core_regs[116]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][21] + (.C(vid_aclk), + .CE(\core_control_regs_int[3] ), + .D(ipif_data_out[21]), + .Q(core_regs[117]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][22] + (.C(vid_aclk), + .CE(\core_control_regs_int[3] ), + .D(ipif_data_out[22]), + .Q(core_regs[118]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][23] + (.C(vid_aclk), + .CE(\core_control_regs_int[3] ), + .D(ipif_data_out[23]), + .Q(core_regs[119]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][24] + (.C(vid_aclk), + .CE(\core_control_regs_int[3] ), + .D(ipif_data_out[24]), + .Q(core_regs[120]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][25] + (.C(vid_aclk), + .CE(\core_control_regs_int[3] ), + .D(ipif_data_out[25]), + .Q(core_regs[121]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][26] + (.C(vid_aclk), + .CE(\core_control_regs_int[3] ), + .D(ipif_data_out[26]), + .Q(core_regs[122]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][2] + (.C(vid_aclk), + .CE(\core_control_regs_int[3] ), + .D(ipif_data_out[2]), + .Q(core_regs[98]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][3] + (.C(vid_aclk), + .CE(\core_control_regs_int[3] ), + .D(ipif_data_out[3]), + .Q(core_regs[99]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][4] + (.C(vid_aclk), + .CE(\core_control_regs_int[3] ), + .D(ipif_data_out[4]), + .Q(core_regs[100]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][5] + (.C(vid_aclk), + .CE(\core_control_regs_int[3] ), + .D(ipif_data_out[5]), + .Q(core_regs[101]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][6] + (.C(vid_aclk), + .CE(\core_control_regs_int[3] ), + .D(ipif_data_out[6]), + .Q(core_regs[102]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][7] + (.C(vid_aclk), + .CE(\core_control_regs_int[3] ), + .D(ipif_data_out[7]), + .Q(core_regs[103]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][8] + (.C(vid_aclk), + .CE(\core_control_regs_int[3] ), + .D(ipif_data_out[8]), + .Q(core_regs[104]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][9] + (.C(vid_aclk), + .CE(\core_control_regs_int[3] ), + .D(ipif_data_out[9]), + .Q(core_regs[105]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][0] + (.C(vid_aclk), + .CE(\core_control_regs_int[4] ), + .D(ipif_data_out[0]), + .Q(\core_control_regs2_int[4] ), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][10] + (.C(vid_aclk), + .CE(\core_control_regs_int[4] ), + .D(ipif_data_out[10]), + .Q(core_regs[138]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][11] + (.C(vid_aclk), + .CE(\core_control_regs_int[4] ), + .D(ipif_data_out[11]), + .Q(core_regs[139]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][16] + (.C(vid_aclk), + .CE(\core_control_regs_int[4] ), + .D(ipif_data_out[16]), + .Q(core_regs[144]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][17] + (.C(vid_aclk), + .CE(\core_control_regs_int[4] ), + .D(ipif_data_out[17]), + .Q(core_regs[145]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][18] + (.C(vid_aclk), + .CE(\core_control_regs_int[4] ), + .D(ipif_data_out[18]), + .Q(core_regs[146]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][19] + (.C(vid_aclk), + .CE(\core_control_regs_int[4] ), + .D(ipif_data_out[19]), + .Q(core_regs[147]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][1] + (.C(vid_aclk), + .CE(\core_control_regs_int[4] ), + .D(ipif_data_out[1]), + .Q(core_regs[129]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][20] + (.C(vid_aclk), + .CE(\core_control_regs_int[4] ), + .D(ipif_data_out[20]), + .Q(core_regs[148]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][21] + (.C(vid_aclk), + .CE(\core_control_regs_int[4] ), + .D(ipif_data_out[21]), + .Q(core_regs[149]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][22] + (.C(vid_aclk), + .CE(\core_control_regs_int[4] ), + .D(ipif_data_out[22]), + .Q(core_regs[150]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][23] + (.C(vid_aclk), + .CE(\core_control_regs_int[4] ), + .D(ipif_data_out[23]), + .Q(core_regs[151]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][24] + (.C(vid_aclk), + .CE(\core_control_regs_int[4] ), + .D(ipif_data_out[24]), + .Q(core_regs[152]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][25] + (.C(vid_aclk), + .CE(\core_control_regs_int[4] ), + .D(ipif_data_out[25]), + .Q(core_regs[153]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][26] + (.C(vid_aclk), + .CE(\core_control_regs_int[4] ), + .D(ipif_data_out[26]), + .Q(core_regs[154]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][2] + (.C(vid_aclk), + .CE(\core_control_regs_int[4] ), + .D(ipif_data_out[2]), + .Q(core_regs[130]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][3] + (.C(vid_aclk), + .CE(\core_control_regs_int[4] ), + .D(ipif_data_out[3]), + .Q(core_regs[131]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][4] + (.C(vid_aclk), + .CE(\core_control_regs_int[4] ), + .D(ipif_data_out[4]), + .Q(core_regs[132]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][5] + (.C(vid_aclk), + .CE(\core_control_regs_int[4] ), + .D(ipif_data_out[5]), + .Q(core_regs[133]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][6] + (.C(vid_aclk), + .CE(\core_control_regs_int[4] ), + .D(ipif_data_out[6]), + .Q(core_regs[134]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][7] + (.C(vid_aclk), + .CE(\core_control_regs_int[4] ), + .D(ipif_data_out[7]), + .Q(core_regs[135]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][8] + (.C(vid_aclk), + .CE(\core_control_regs_int[4] ), + .D(ipif_data_out[8]), + .Q(core_regs[136]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][9] + (.C(vid_aclk), + .CE(\core_control_regs_int[4] ), + .D(ipif_data_out[9]), + .Q(core_regs[137]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][0] + (.C(vid_aclk), + .CE(\core_control_regs_int[5] ), + .D(ipif_data_out[0]), + .Q(\core_control_regs2_int[5] ), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][10] + (.C(vid_aclk), + .CE(\core_control_regs_int[5] ), + .D(ipif_data_out[10]), + .Q(core_regs[170]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][11] + (.C(vid_aclk), + .CE(\core_control_regs_int[5] ), + .D(ipif_data_out[11]), + .Q(core_regs[171]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][16] + (.C(vid_aclk), + .CE(\core_control_regs_int[5] ), + .D(ipif_data_out[16]), + .Q(core_regs[176]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][17] + (.C(vid_aclk), + .CE(\core_control_regs_int[5] ), + .D(ipif_data_out[17]), + .Q(core_regs[177]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][18] + (.C(vid_aclk), + .CE(\core_control_regs_int[5] ), + .D(ipif_data_out[18]), + .Q(core_regs[178]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][19] + (.C(vid_aclk), + .CE(\core_control_regs_int[5] ), + .D(ipif_data_out[19]), + .Q(core_regs[179]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][1] + (.C(vid_aclk), + .CE(\core_control_regs_int[5] ), + .D(ipif_data_out[1]), + .Q(core_regs[161]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][20] + (.C(vid_aclk), + .CE(\core_control_regs_int[5] ), + .D(ipif_data_out[20]), + .Q(core_regs[180]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][21] + (.C(vid_aclk), + .CE(\core_control_regs_int[5] ), + .D(ipif_data_out[21]), + .Q(core_regs[181]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][22] + (.C(vid_aclk), + .CE(\core_control_regs_int[5] ), + .D(ipif_data_out[22]), + .Q(core_regs[182]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][23] + (.C(vid_aclk), + .CE(\core_control_regs_int[5] ), + .D(ipif_data_out[23]), + .Q(core_regs[183]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][24] + (.C(vid_aclk), + .CE(\core_control_regs_int[5] ), + .D(ipif_data_out[24]), + .Q(core_regs[184]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][25] + (.C(vid_aclk), + .CE(\core_control_regs_int[5] ), + .D(ipif_data_out[25]), + .Q(core_regs[185]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][26] + (.C(vid_aclk), + .CE(\core_control_regs_int[5] ), + .D(ipif_data_out[26]), + .Q(core_regs[186]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][2] + (.C(vid_aclk), + .CE(\core_control_regs_int[5] ), + .D(ipif_data_out[2]), + .Q(core_regs[162]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][3] + (.C(vid_aclk), + .CE(\core_control_regs_int[5] ), + .D(ipif_data_out[3]), + .Q(core_regs[163]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][4] + (.C(vid_aclk), + .CE(\core_control_regs_int[5] ), + .D(ipif_data_out[4]), + .Q(core_regs[164]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][5] + (.C(vid_aclk), + .CE(\core_control_regs_int[5] ), + .D(ipif_data_out[5]), + .Q(core_regs[165]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][6] + (.C(vid_aclk), + .CE(\core_control_regs_int[5] ), + .D(ipif_data_out[6]), + .Q(core_regs[166]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][7] + (.C(vid_aclk), + .CE(\core_control_regs_int[5] ), + .D(ipif_data_out[7]), + .Q(core_regs[167]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][8] + (.C(vid_aclk), + .CE(\core_control_regs_int[5] ), + .D(ipif_data_out[8]), + .Q(core_regs[168]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][9] + (.C(vid_aclk), + .CE(\core_control_regs_int[5] ), + .D(ipif_data_out[9]), + .Q(core_regs[169]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][0] + (.C(vid_aclk), + .CE(\core_control_regs_int[6] ), + .D(ipif_data_out[0]), + .Q(\core_control_regs2_int[6] ), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][10] + (.C(vid_aclk), + .CE(\core_control_regs_int[6] ), + .D(ipif_data_out[10]), + .Q(core_regs[202]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][11] + (.C(vid_aclk), + .CE(\core_control_regs_int[6] ), + .D(ipif_data_out[11]), + .Q(core_regs[203]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][16] + (.C(vid_aclk), + .CE(\core_control_regs_int[6] ), + .D(ipif_data_out[16]), + .Q(core_regs[208]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][17] + (.C(vid_aclk), + .CE(\core_control_regs_int[6] ), + .D(ipif_data_out[17]), + .Q(core_regs[209]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][18] + (.C(vid_aclk), + .CE(\core_control_regs_int[6] ), + .D(ipif_data_out[18]), + .Q(core_regs[210]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][19] + (.C(vid_aclk), + .CE(\core_control_regs_int[6] ), + .D(ipif_data_out[19]), + .Q(core_regs[211]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][1] + (.C(vid_aclk), + .CE(\core_control_regs_int[6] ), + .D(ipif_data_out[1]), + .Q(core_regs[193]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][20] + (.C(vid_aclk), + .CE(\core_control_regs_int[6] ), + .D(ipif_data_out[20]), + .Q(core_regs[212]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][21] + (.C(vid_aclk), + .CE(\core_control_regs_int[6] ), + .D(ipif_data_out[21]), + .Q(core_regs[213]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][22] + (.C(vid_aclk), + .CE(\core_control_regs_int[6] ), + .D(ipif_data_out[22]), + .Q(core_regs[214]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][23] + (.C(vid_aclk), + .CE(\core_control_regs_int[6] ), + .D(ipif_data_out[23]), + .Q(core_regs[215]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][24] + (.C(vid_aclk), + .CE(\core_control_regs_int[6] ), + .D(ipif_data_out[24]), + .Q(core_regs[216]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][25] + (.C(vid_aclk), + .CE(\core_control_regs_int[6] ), + .D(ipif_data_out[25]), + .Q(core_regs[217]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][26] + (.C(vid_aclk), + .CE(\core_control_regs_int[6] ), + .D(ipif_data_out[26]), + .Q(core_regs[218]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][2] + (.C(vid_aclk), + .CE(\core_control_regs_int[6] ), + .D(ipif_data_out[2]), + .Q(core_regs[194]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][3] + (.C(vid_aclk), + .CE(\core_control_regs_int[6] ), + .D(ipif_data_out[3]), + .Q(core_regs[195]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][4] + (.C(vid_aclk), + .CE(\core_control_regs_int[6] ), + .D(ipif_data_out[4]), + .Q(core_regs[196]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][5] + (.C(vid_aclk), + .CE(\core_control_regs_int[6] ), + .D(ipif_data_out[5]), + .Q(core_regs[197]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][6] + (.C(vid_aclk), + .CE(\core_control_regs_int[6] ), + .D(ipif_data_out[6]), + .Q(core_regs[198]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][7] + (.C(vid_aclk), + .CE(\core_control_regs_int[6] ), + .D(ipif_data_out[7]), + .Q(core_regs[199]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][8] + (.C(vid_aclk), + .CE(\core_control_regs_int[6] ), + .D(ipif_data_out[8]), + .Q(core_regs[200]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][9] + (.C(vid_aclk), + .CE(\core_control_regs_int[6] ), + .D(ipif_data_out[9]), + .Q(core_regs[201]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][0] + (.C(vid_aclk), + .CE(\core_control_regs_int[7] ), + .D(ipif_data_out[0]), + .Q(\core_control_regs2_int[7] ), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][10] + (.C(vid_aclk), + .CE(\core_control_regs_int[7] ), + .D(ipif_data_out[10]), + .Q(core_regs[234]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][11] + (.C(vid_aclk), + .CE(\core_control_regs_int[7] ), + .D(ipif_data_out[11]), + .Q(core_regs[235]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][16] + (.C(vid_aclk), + .CE(\core_control_regs_int[7] ), + .D(ipif_data_out[16]), + .Q(core_regs[240]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][17] + (.C(vid_aclk), + .CE(\core_control_regs_int[7] ), + .D(ipif_data_out[17]), + .Q(core_regs[241]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][18] + (.C(vid_aclk), + .CE(\core_control_regs_int[7] ), + .D(ipif_data_out[18]), + .Q(core_regs[242]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][19] + (.C(vid_aclk), + .CE(\core_control_regs_int[7] ), + .D(ipif_data_out[19]), + .Q(core_regs[243]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][1] + (.C(vid_aclk), + .CE(\core_control_regs_int[7] ), + .D(ipif_data_out[1]), + .Q(core_regs[225]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][20] + (.C(vid_aclk), + .CE(\core_control_regs_int[7] ), + .D(ipif_data_out[20]), + .Q(core_regs[244]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][21] + (.C(vid_aclk), + .CE(\core_control_regs_int[7] ), + .D(ipif_data_out[21]), + .Q(core_regs[245]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][22] + (.C(vid_aclk), + .CE(\core_control_regs_int[7] ), + .D(ipif_data_out[22]), + .Q(core_regs[246]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][23] + (.C(vid_aclk), + .CE(\core_control_regs_int[7] ), + .D(ipif_data_out[23]), + .Q(core_regs[247]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][24] + (.C(vid_aclk), + .CE(\core_control_regs_int[7] ), + .D(ipif_data_out[24]), + .Q(core_regs[248]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][25] + (.C(vid_aclk), + .CE(\core_control_regs_int[7] ), + .D(ipif_data_out[25]), + .Q(core_regs[249]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][26] + (.C(vid_aclk), + .CE(\core_control_regs_int[7] ), + .D(ipif_data_out[26]), + .Q(core_regs[250]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][2] + (.C(vid_aclk), + .CE(\core_control_regs_int[7] ), + .D(ipif_data_out[2]), + .Q(core_regs[226]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][3] + (.C(vid_aclk), + .CE(\core_control_regs_int[7] ), + .D(ipif_data_out[3]), + .Q(core_regs[227]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][4] + (.C(vid_aclk), + .CE(\core_control_regs_int[7] ), + .D(ipif_data_out[4]), + .Q(core_regs[228]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][5] + (.C(vid_aclk), + .CE(\core_control_regs_int[7] ), + .D(ipif_data_out[5]), + .Q(core_regs[229]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][6] + (.C(vid_aclk), + .CE(\core_control_regs_int[7] ), + .D(ipif_data_out[6]), + .Q(core_regs[230]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][7] + (.C(vid_aclk), + .CE(\core_control_regs_int[7] ), + .D(ipif_data_out[7]), + .Q(core_regs[231]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][8] + (.C(vid_aclk), + .CE(\core_control_regs_int[7] ), + .D(ipif_data_out[8]), + .Q(core_regs[232]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][9] + (.C(vid_aclk), + .CE(\core_control_regs_int[7] ), + .D(ipif_data_out[9]), + .Q(core_regs[233]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][0] + (.C(vid_aclk), + .CE(\core_control_regs_int[8] ), + .D(ipif_data_out[0]), + .Q(\core_control_regs2_int[8] ), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][10] + (.C(vid_aclk), + .CE(\core_control_regs_int[8] ), + .D(ipif_data_out[10]), + .Q(core_regs[266]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][11] + (.C(vid_aclk), + .CE(\core_control_regs_int[8] ), + .D(ipif_data_out[11]), + .Q(core_regs[267]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][16] + (.C(vid_aclk), + .CE(\core_control_regs_int[8] ), + .D(ipif_data_out[16]), + .Q(core_regs[272]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][17] + (.C(vid_aclk), + .CE(\core_control_regs_int[8] ), + .D(ipif_data_out[17]), + .Q(core_regs[273]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][18] + (.C(vid_aclk), + .CE(\core_control_regs_int[8] ), + .D(ipif_data_out[18]), + .Q(core_regs[274]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][19] + (.C(vid_aclk), + .CE(\core_control_regs_int[8] ), + .D(ipif_data_out[19]), + .Q(core_regs[275]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][1] + (.C(vid_aclk), + .CE(\core_control_regs_int[8] ), + .D(ipif_data_out[1]), + .Q(core_regs[257]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][20] + (.C(vid_aclk), + .CE(\core_control_regs_int[8] ), + .D(ipif_data_out[20]), + .Q(core_regs[276]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][21] + (.C(vid_aclk), + .CE(\core_control_regs_int[8] ), + .D(ipif_data_out[21]), + .Q(core_regs[277]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][22] + (.C(vid_aclk), + .CE(\core_control_regs_int[8] ), + .D(ipif_data_out[22]), + .Q(core_regs[278]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][23] + (.C(vid_aclk), + .CE(\core_control_regs_int[8] ), + .D(ipif_data_out[23]), + .Q(core_regs[279]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][24] + (.C(vid_aclk), + .CE(\core_control_regs_int[8] ), + .D(ipif_data_out[24]), + .Q(core_regs[280]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][25] + (.C(vid_aclk), + .CE(\core_control_regs_int[8] ), + .D(ipif_data_out[25]), + .Q(core_regs[281]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][26] + (.C(vid_aclk), + .CE(\core_control_regs_int[8] ), + .D(ipif_data_out[26]), + .Q(core_regs[282]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][2] + (.C(vid_aclk), + .CE(\core_control_regs_int[8] ), + .D(ipif_data_out[2]), + .Q(core_regs[258]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][3] + (.C(vid_aclk), + .CE(\core_control_regs_int[8] ), + .D(ipif_data_out[3]), + .Q(core_regs[259]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][4] + (.C(vid_aclk), + .CE(\core_control_regs_int[8] ), + .D(ipif_data_out[4]), + .Q(core_regs[260]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][5] + (.C(vid_aclk), + .CE(\core_control_regs_int[8] ), + .D(ipif_data_out[5]), + .Q(core_regs[261]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][6] + (.C(vid_aclk), + .CE(\core_control_regs_int[8] ), + .D(ipif_data_out[6]), + .Q(core_regs[262]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][7] + (.C(vid_aclk), + .CE(\core_control_regs_int[8] ), + .D(ipif_data_out[7]), + .Q(core_regs[263]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][8] + (.C(vid_aclk), + .CE(\core_control_regs_int[8] ), + .D(ipif_data_out[8]), + .Q(core_regs[264]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][9] + (.C(vid_aclk), + .CE(\core_control_regs_int[8] ), + .D(ipif_data_out[9]), + .Q(core_regs[265]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][0] + (.C(vid_aclk), + .CE(\core_control_regs_int[9] ), + .D(ipif_data_out[0]), + .Q(\core_control_regs2_int[9] ), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][10] + (.C(vid_aclk), + .CE(\core_control_regs_int[9] ), + .D(ipif_data_out[10]), + .Q(core_regs[298]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][11] + (.C(vid_aclk), + .CE(\core_control_regs_int[9] ), + .D(ipif_data_out[11]), + .Q(core_regs[299]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][16] + (.C(vid_aclk), + .CE(\core_control_regs_int[9] ), + .D(ipif_data_out[16]), + .Q(core_regs[304]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][17] + (.C(vid_aclk), + .CE(\core_control_regs_int[9] ), + .D(ipif_data_out[17]), + .Q(core_regs[305]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][18] + (.C(vid_aclk), + .CE(\core_control_regs_int[9] ), + .D(ipif_data_out[18]), + .Q(core_regs[306]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][19] + (.C(vid_aclk), + .CE(\core_control_regs_int[9] ), + .D(ipif_data_out[19]), + .Q(core_regs[307]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][1] + (.C(vid_aclk), + .CE(\core_control_regs_int[9] ), + .D(ipif_data_out[1]), + .Q(core_regs[289]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][20] + (.C(vid_aclk), + .CE(\core_control_regs_int[9] ), + .D(ipif_data_out[20]), + .Q(core_regs[308]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][21] + (.C(vid_aclk), + .CE(\core_control_regs_int[9] ), + .D(ipif_data_out[21]), + .Q(core_regs[309]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][22] + (.C(vid_aclk), + .CE(\core_control_regs_int[9] ), + .D(ipif_data_out[22]), + .Q(core_regs[310]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][23] + (.C(vid_aclk), + .CE(\core_control_regs_int[9] ), + .D(ipif_data_out[23]), + .Q(core_regs[311]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][24] + (.C(vid_aclk), + .CE(\core_control_regs_int[9] ), + .D(ipif_data_out[24]), + .Q(core_regs[312]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][25] + (.C(vid_aclk), + .CE(\core_control_regs_int[9] ), + .D(ipif_data_out[25]), + .Q(core_regs[313]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][26] + (.C(vid_aclk), + .CE(\core_control_regs_int[9] ), + .D(ipif_data_out[26]), + .Q(core_regs[314]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][2] + (.C(vid_aclk), + .CE(\core_control_regs_int[9] ), + .D(ipif_data_out[2]), + .Q(core_regs[290]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][3] + (.C(vid_aclk), + .CE(\core_control_regs_int[9] ), + .D(ipif_data_out[3]), + .Q(core_regs[291]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][4] + (.C(vid_aclk), + .CE(\core_control_regs_int[9] ), + .D(ipif_data_out[4]), + .Q(core_regs[292]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][5] + (.C(vid_aclk), + .CE(\core_control_regs_int[9] ), + .D(ipif_data_out[5]), + .Q(core_regs[293]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][6] + (.C(vid_aclk), + .CE(\core_control_regs_int[9] ), + .D(ipif_data_out[6]), + .Q(core_regs[294]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][7] + (.C(vid_aclk), + .CE(\core_control_regs_int[9] ), + .D(ipif_data_out[7]), + .Q(core_regs[295]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][8] + (.C(vid_aclk), + .CE(\core_control_regs_int[9] ), + .D(ipif_data_out[8]), + .Q(core_regs[296]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][9] + (.C(vid_aclk), + .CE(\core_control_regs_int[9] ), + .D(ipif_data_out[9]), + .Q(core_regs[297]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][0] + (.C(vid_aclk), + .CE(\genr_control_regs_int[0] ), + .D(ipif_data_out[0]), + .Q(\^genr_control_regs[0] [0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][10] + (.C(vid_aclk), + .CE(\genr_control_regs_int[0] ), + .D(ipif_data_out[10]), + .Q(\^genr_control_regs[0] [10]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][11] + (.C(vid_aclk), + .CE(\genr_control_regs_int[0] ), + .D(ipif_data_out[11]), + .Q(\^genr_control_regs[0] [11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][13] + (.C(vid_aclk), + .CE(\genr_control_regs_int[0] ), + .D(ipif_data_out[13]), + .Q(\^genr_control_regs[0] [13]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][14] + (.C(vid_aclk), + .CE(\genr_control_regs_int[0] ), + .D(ipif_data_out[14]), + .Q(\^genr_control_regs[0] [14]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][15] + (.C(vid_aclk), + .CE(\genr_control_regs_int[0] ), + .D(ipif_data_out[15]), + .Q(\^genr_control_regs[0] [15]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][16] + (.C(vid_aclk), + .CE(\genr_control_regs_int[0] ), + .D(ipif_data_out[16]), + .Q(\^genr_control_regs[0] [16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][17] + (.C(vid_aclk), + .CE(\genr_control_regs_int[0] ), + .D(ipif_data_out[17]), + .Q(\^genr_control_regs[0] [17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][18] + (.C(vid_aclk), + .CE(\genr_control_regs_int[0] ), + .D(ipif_data_out[18]), + .Q(\^genr_control_regs[0] [18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][19] + (.C(vid_aclk), + .CE(\genr_control_regs_int[0] ), + .D(ipif_data_out[19]), + .Q(\^genr_control_regs[0] [19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][1] + (.C(vid_aclk), + .CE(\genr_control_regs_int[0] ), + .D(ipif_data_out[1]), + .Q(\^genr_control_regs[0] [1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][20] + (.C(vid_aclk), + .CE(\genr_control_regs_int[0] ), + .D(ipif_data_out[20]), + .Q(\^genr_control_regs[0] [20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][21] + (.C(vid_aclk), + .CE(\genr_control_regs_int[0] ), + .D(ipif_data_out[21]), + .Q(\^genr_control_regs[0] [21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][22] + (.C(vid_aclk), + .CE(\genr_control_regs_int[0] ), + .D(ipif_data_out[22]), + .Q(\^genr_control_regs[0] [22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][23] + (.C(vid_aclk), + .CE(\genr_control_regs_int[0] ), + .D(ipif_data_out[23]), + .Q(\^genr_control_regs[0] [23]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][24] + (.C(vid_aclk), + .CE(\genr_control_regs_int[0] ), + .D(ipif_data_out[24]), + .Q(\^genr_control_regs[0] [24]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][25] + (.C(vid_aclk), + .CE(\genr_control_regs_int[0] ), + .D(ipif_data_out[25]), + .Q(\^genr_control_regs[0] [25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][26] + (.C(vid_aclk), + .CE(\genr_control_regs_int[0] ), + .D(ipif_data_out[26]), + .Q(\^genr_control_regs[0] [26]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][2] + (.C(vid_aclk), + .CE(\genr_control_regs_int[0] ), + .D(ipif_data_out[2]), + .Q(\^genr_control_regs[0] [2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][30] + (.C(vid_aclk), + .CE(\genr_control_regs_int[0] ), + .D(ipif_data_out[30]), + .Q(\^genr_control_regs[0] [30]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][31] + (.C(vid_aclk), + .CE(\genr_control_regs_int[0] ), + .D(ipif_data_out[31]), + .Q(\^genr_control_regs[0] [31]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][3] + (.C(vid_aclk), + .CE(\genr_control_regs_int[0] ), + .D(ipif_data_out[3]), + .Q(\^genr_control_regs[0] [3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][5] + (.C(vid_aclk), + .CE(\genr_control_regs_int[0] ), + .D(ipif_data_out[5]), + .Q(\^genr_control_regs[0] [5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][8] + (.C(vid_aclk), + .CE(\genr_control_regs_int[0] ), + .D(ipif_data_out[8]), + .Q(\^genr_control_regs[0] [8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][9] + (.C(vid_aclk), + .CE(\genr_control_regs_int[0] ), + .D(ipif_data_out[9]), + .Q(\^genr_control_regs[0] [9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][10] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_52 ), + .Q(\^genr_control_regs[1] [10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][11] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_51 ), + .Q(\^genr_control_regs[1] [11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][12] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_50 ), + .Q(\^genr_control_regs[1] [12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][13] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_49 ), + .Q(\^genr_control_regs[1] [13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][16] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_48 ), + .Q(\^genr_control_regs[1] [16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][17] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_47 ), + .Q(\^genr_control_regs[1] [17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][18] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_46 ), + .Q(\^genr_control_regs[1] [18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][19] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_45 ), + .Q(\^genr_control_regs[1] [19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][20] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_44 ), + .Q(\^genr_control_regs[1] [20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][21] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_43 ), + .Q(\^genr_control_regs[1] [21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][22] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_42 ), + .Q(\^genr_control_regs[1] [22]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][23] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_41 ), + .Q(\^genr_control_regs[1] [23]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][24] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_40 ), + .Q(\^genr_control_regs[1] [24]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][25] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_39 ), + .Q(\^genr_control_regs[1] [25]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][26] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_38 ), + .Q(\^genr_control_regs[1] [26]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][27] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_37 ), + .Q(\^genr_control_regs[1] [27]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][28] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_36 ), + .Q(\^genr_control_regs[1] [28]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][29] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_35 ), + .Q(\^genr_control_regs[1] [29]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][30] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_34 ), + .Q(\^genr_control_regs[1] [30]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][31] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_0 ), + .Q(\^genr_control_regs[1] [31]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][8] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_54 ), + .Q(\^genr_control_regs[1] [8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][9] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_53 ), + .Q(\^genr_control_regs[1] [9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][16] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_60 ), + .Q(\^genr_control_regs[2] [16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][17] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_59 ), + .Q(\^genr_control_regs[2] [17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][18] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_58 ), + .Q(\^genr_control_regs[2] [18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][19] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_57 ), + .Q(\^genr_control_regs[2] [19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][20] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_56 ), + .Q(\^genr_control_regs[2] [20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][21] + (.C(vid_aclk), + .CE(1'b1), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_55 ), + .Q(\^genr_control_regs[2] [21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][10] + (.C(vid_aclk), + .CE(\genr_control_regs_int[3] ), + .D(ipif_data_out[10]), + .Q(\^genr_control_regs[3] [10]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][11] + (.C(vid_aclk), + .CE(\genr_control_regs_int[3] ), + .D(ipif_data_out[11]), + .Q(\^genr_control_regs[3] [11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][12] + (.C(vid_aclk), + .CE(\genr_control_regs_int[3] ), + .D(ipif_data_out[12]), + .Q(\^genr_control_regs[3] [12]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][13] + (.C(vid_aclk), + .CE(\genr_control_regs_int[3] ), + .D(ipif_data_out[13]), + .Q(\^genr_control_regs[3] [13]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][16] + (.C(vid_aclk), + .CE(\genr_control_regs_int[3] ), + .D(ipif_data_out[16]), + .Q(\^genr_control_regs[3] [16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][17] + (.C(vid_aclk), + .CE(\genr_control_regs_int[3] ), + .D(ipif_data_out[17]), + .Q(\^genr_control_regs[3] [17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][18] + (.C(vid_aclk), + .CE(\genr_control_regs_int[3] ), + .D(ipif_data_out[18]), + .Q(\^genr_control_regs[3] [18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][19] + (.C(vid_aclk), + .CE(\genr_control_regs_int[3] ), + .D(ipif_data_out[19]), + .Q(\^genr_control_regs[3] [19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][20] + (.C(vid_aclk), + .CE(\genr_control_regs_int[3] ), + .D(ipif_data_out[20]), + .Q(\^genr_control_regs[3] [20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][21] + (.C(vid_aclk), + .CE(\genr_control_regs_int[3] ), + .D(ipif_data_out[21]), + .Q(\^genr_control_regs[3] [21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][22] + (.C(vid_aclk), + .CE(\genr_control_regs_int[3] ), + .D(ipif_data_out[22]), + .Q(\^genr_control_regs[3] [22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][23] + (.C(vid_aclk), + .CE(\genr_control_regs_int[3] ), + .D(ipif_data_out[23]), + .Q(\^genr_control_regs[3] [23]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][24] + (.C(vid_aclk), + .CE(\genr_control_regs_int[3] ), + .D(ipif_data_out[24]), + .Q(\^genr_control_regs[3] [24]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][25] + (.C(vid_aclk), + .CE(\genr_control_regs_int[3] ), + .D(ipif_data_out[25]), + .Q(\^genr_control_regs[3] [25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][26] + (.C(vid_aclk), + .CE(\genr_control_regs_int[3] ), + .D(ipif_data_out[26]), + .Q(\^genr_control_regs[3] [26]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][27] + (.C(vid_aclk), + .CE(\genr_control_regs_int[3] ), + .D(ipif_data_out[27]), + .Q(\^genr_control_regs[3] [27]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][28] + (.C(vid_aclk), + .CE(\genr_control_regs_int[3] ), + .D(ipif_data_out[28]), + .Q(\^genr_control_regs[3] [28]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][29] + (.C(vid_aclk), + .CE(\genr_control_regs_int[3] ), + .D(ipif_data_out[29]), + .Q(\^genr_control_regs[3] [29]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][30] + (.C(vid_aclk), + .CE(\genr_control_regs_int[3] ), + .D(ipif_data_out[30]), + .Q(\^genr_control_regs[3] [30]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][31] + (.C(vid_aclk), + .CE(\genr_control_regs_int[3] ), + .D(ipif_data_out[31]), + .Q(\^genr_control_regs[3] [31]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][8] + (.C(vid_aclk), + .CE(\genr_control_regs_int[3] ), + .D(ipif_data_out[8]), + .Q(\^genr_control_regs[3] [8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][9] + (.C(vid_aclk), + .CE(\genr_control_regs_int[3] ), + .D(ipif_data_out[9]), + .Q(\^genr_control_regs[3] [9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.ipif_Error_reg + (.C(aclk), + .CE(aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2PROCCLK_I_n_36 ), + .Q(ipif_Error), + .S(p_0_in_0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdAck_reg + (.C(aclk), + .CE(aclk_en), + .D(p_528_out), + .Q(ipif_RdAck), + .R(p_0_in_0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[0] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_92 ), + .Q(ipif_RdData[0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[10] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_82 ), + .Q(ipif_RdData[10]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[11] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_81 ), + .Q(ipif_RdData[11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[12] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_80 ), + .Q(ipif_RdData[12]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[13] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_79 ), + .Q(ipif_RdData[13]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[14] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_78 ), + .Q(ipif_RdData[14]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[15] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_77 ), + .Q(ipif_RdData[15]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[16] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_76 ), + .Q(ipif_RdData[16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[17] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_75 ), + .Q(ipif_RdData[17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[18] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_74 ), + .Q(ipif_RdData[18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[19] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_73 ), + .Q(ipif_RdData[19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[1] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_91 ), + .Q(ipif_RdData[1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[20] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_72 ), + .Q(ipif_RdData[20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[21] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_71 ), + .Q(ipif_RdData[21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[22] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_70 ), + .Q(ipif_RdData[22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[23] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_69 ), + .Q(ipif_RdData[23]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[24] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_68 ), + .Q(ipif_RdData[24]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[25] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_67 ), + .Q(ipif_RdData[25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[26] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_66 ), + .Q(ipif_RdData[26]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[27] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_65 ), + .Q(ipif_RdData[27]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[28] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_64 ), + .Q(ipif_RdData[28]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[29] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_63 ), + .Q(ipif_RdData[29]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[2] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_90 ), + .Q(ipif_RdData[2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[30] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_62 ), + .Q(ipif_RdData[30]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_61 ), + .Q(ipif_RdData[31]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[3] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_89 ), + .Q(ipif_RdData[3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[4] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_88 ), + .Q(ipif_RdData[4]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[5] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_87 ), + .Q(ipif_RdData[5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[6] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_86 ), + .Q(ipif_RdData[6]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[7] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_85 ), + .Q(ipif_RdData[7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[8] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_84 ), + .Q(ipif_RdData[8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_RdData_reg[9] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_83 ), + .Q(ipif_RdData[9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.ipif_WrAck_reg + (.C(aclk), + .CE(aclk_en), + .D(p_526_out), + .Q(ipif_WrAck), + .R(p_0_in_0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[0] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[0]), + .Q(proc_sync1[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[10] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[10]), + .Q(proc_sync1[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[11] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[11]), + .Q(proc_sync1[11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[12] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[12]), + .Q(proc_sync1[12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[13] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[13]), + .Q(proc_sync1[13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[14] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[14]), + .Q(proc_sync1[14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[15] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[15]), + .Q(proc_sync1[15]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[16] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[16]), + .Q(proc_sync1[16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[17] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[17]), + .Q(proc_sync1[17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[18] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[18]), + .Q(proc_sync1[18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[19] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[19]), + .Q(proc_sync1[19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[1] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[1]), + .Q(proc_sync1[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[20] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[20]), + .Q(proc_sync1[20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[21] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[21]), + .Q(proc_sync1[21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[22] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[22]), + .Q(proc_sync1[22]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[23] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[23]), + .Q(proc_sync1[23]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[24] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[24]), + .Q(proc_sync1[24]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[25] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[25]), + .Q(proc_sync1[25]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[26] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[26]), + .Q(proc_sync1[26]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[27] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[27]), + .Q(proc_sync1[27]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[28] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[28]), + .Q(proc_sync1[28]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[29] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[29]), + .Q(proc_sync1[29]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[2] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[2]), + .Q(proc_sync1[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[30] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[30]), + .Q(proc_sync1[30]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[31] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[31]), + .Q(proc_sync1[31]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[32] + (.C(aclk), + .CE(1'b1), + .D(ipif_proc_Addr_int[0]), + .Q(proc_sync1[32]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[33] + (.C(aclk), + .CE(1'b1), + .D(ipif_proc_Addr_int[1]), + .Q(proc_sync1[33]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[34] + (.C(aclk), + .CE(1'b1), + .D(ipif_proc_Addr_int[2]), + .Q(proc_sync1[34]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[35] + (.C(aclk), + .CE(1'b1), + .D(ipif_proc_Addr_int[3]), + .Q(proc_sync1[35]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[36] + (.C(aclk), + .CE(1'b1), + .D(ipif_proc_Addr_int[4]), + .Q(proc_sync1[36]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[37] + (.C(aclk), + .CE(1'b1), + .D(ipif_proc_Addr_int[5]), + .Q(proc_sync1[37]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[38] + (.C(aclk), + .CE(1'b1), + .D(ipif_proc_Addr_int[6]), + .Q(proc_sync1[38]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[39] + (.C(aclk), + .CE(1'b1), + .D(ipif_proc_Addr_int[7]), + .Q(proc_sync1[39]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[3] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[3]), + .Q(proc_sync1[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[40] + (.C(aclk), + .CE(1'b1), + .D(ipif_proc_Addr_int[8]), + .Q(proc_sync1[40]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[41] + (.C(aclk), + .CE(1'b1), + .D(ipif_proc_CS[0]), + .Q(proc_sync1[41]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[42] + (.C(aclk), + .CE(1'b1), + .D(ipif_proc_CS[1]), + .Q(proc_sync1[42]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[43] + (.C(aclk), + .CE(1'b1), + .D(ipif_proc_RNW), + .Q(proc_sync1[43]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[44] + (.C(aclk), + .CE(1'b1), + .D(aresetn), + .Q(proc_sync1[44]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[4] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[4]), + .Q(proc_sync1[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[5] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[5]), + .Q(proc_sync1[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[6] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[6]), + .Q(proc_sync1[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[7] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[7]), + .Q(proc_sync1[7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[8] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[8]), + .Q(proc_sync1[8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.proc_sync1_reg[9] + (.C(aclk), + .CE(1'b1), + .D(s_axi_wdata[9]), + .Q(proc_sync1[9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.read_ack_d1_reg + (.C(aclk), + .CE(aclk_en), + .D(p_143_out[32]), + .Q(read_ack_d1), + .R(p_0_in_0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.read_ack_d2_reg + (.C(aclk), + .CE(aclk_en), + .D(read_ack_d1), + .Q(read_ack_d2), + .R(p_0_in_0)); + (* srl_bus_name = "U0/U_VIDEO_CTRL/\AXI4_LITE_INTERFACE.read_ack_d_reg " *) + (* srl_name = "U0/U_VIDEO_CTRL/\AXI4_LITE_INTERFACE.read_ack_d_reg[2]_srl4___AXI4_LITE_INTERFACE.read_ack_d_reg_r_1 " *) + SRL16E #( + .INIT(16'h0000)) + \AXI4_LITE_INTERFACE.read_ack_d_reg[2]_srl4___AXI4_LITE_INTERFACE.read_ack_d_reg_r_1 + (.A0(1'b1), + .A1(1'b1), + .A2(1'b0), + .A3(1'b0), + .CE(vid_aclk_en), + .CLK(vid_aclk), + .D(p_535_out), + .Q(\AXI4_LITE_INTERFACE.read_ack_d_reg[2]_srl4___AXI4_LITE_INTERFACE.read_ack_d_reg_r_1_n_0 )); + FDRE \AXI4_LITE_INTERFACE.read_ack_d_reg[3]_AXI4_LITE_INTERFACE.read_ack_d_reg_r_2 + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.read_ack_d_reg[2]_srl4___AXI4_LITE_INTERFACE.read_ack_d_reg_r_1_n_0 ), + .Q(\AXI4_LITE_INTERFACE.read_ack_d_reg[3]_AXI4_LITE_INTERFACE.read_ack_d_reg_r_2_n_0 ), + .R(1'b0)); + FDRE \AXI4_LITE_INTERFACE.read_ack_d_reg[4] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.read_ack_d_reg_gate_n_0 ), + .Q(read_ack_d), + .R(\AXI4_LITE_INTERFACE.write_ack_e1_i_1_n_0 )); + LUT2 #( + .INIT(4'h8)) + \AXI4_LITE_INTERFACE.read_ack_d_reg_gate + (.I0(\AXI4_LITE_INTERFACE.read_ack_d_reg[3]_AXI4_LITE_INTERFACE.read_ack_d_reg_r_2_n_0 ), + .I1(\AXI4_LITE_INTERFACE.read_ack_d_reg_r_2_n_0 ), + .O(\AXI4_LITE_INTERFACE.read_ack_d_reg_gate_n_0 )); + FDRE \AXI4_LITE_INTERFACE.read_ack_d_reg_r + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.read_ack_reg_r_n_0 ), + .Q(\AXI4_LITE_INTERFACE.read_ack_d_reg_r_n_0 ), + .R(\AXI4_LITE_INTERFACE.write_ack_e1_i_1_n_0 )); + FDRE \AXI4_LITE_INTERFACE.read_ack_d_reg_r_0 + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.read_ack_d_reg_r_n_0 ), + .Q(\AXI4_LITE_INTERFACE.read_ack_d_reg_r_0_n_0 ), + .R(\AXI4_LITE_INTERFACE.write_ack_e1_i_1_n_0 )); + FDRE \AXI4_LITE_INTERFACE.read_ack_d_reg_r_1 + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.read_ack_d_reg_r_0_n_0 ), + .Q(\AXI4_LITE_INTERFACE.read_ack_d_reg_r_1_n_0 ), + .R(\AXI4_LITE_INTERFACE.write_ack_e1_i_1_n_0 )); + FDRE \AXI4_LITE_INTERFACE.read_ack_d_reg_r_2 + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.read_ack_d_reg_r_1_n_0 ), + .Q(\AXI4_LITE_INTERFACE.read_ack_d_reg_r_2_n_0 ), + .R(\AXI4_LITE_INTERFACE.write_ack_e1_i_1_n_0 )); + FDRE \AXI4_LITE_INTERFACE.read_ack_reg_r + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(1'b1), + .Q(\AXI4_LITE_INTERFACE.read_ack_reg_r_n_0 ), + .R(\AXI4_LITE_INTERFACE.write_ack_e1_i_1_n_0 )); + FDRE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.soft_resetn_reg + (.C(vid_aclk), + .CE(1'b1), + .D(p_456_out), + .Q(resetn_out), + .R(1'b0)); + LUT3 #( + .INIT(8'h80)) + \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1 + (.I0(\^genr_control_regs[0] [1]), + .I1(reg_update), + .I2(vid_aclk_en), + .O(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][0] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(\time_control_regs2_int[16] ), + .Q(\^time_control_regs[16] [0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][10] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_9_in), + .Q(\^time_control_regs[16] [10]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][11] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_10_in), + .Q(\^time_control_regs[16] [11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][12] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_11_in), + .Q(\^time_control_regs[16] [12]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][16] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_12_in), + .Q(\^time_control_regs[16] [16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][17] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_13_in), + .Q(\^time_control_regs[16] [17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][18] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_14_in), + .Q(\^time_control_regs[16] [18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][19] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_15_in), + .Q(\^time_control_regs[16] [19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][1] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_0_in), + .Q(\^time_control_regs[16] [1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][20] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_16_in), + .Q(\^time_control_regs[16] [20]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][21] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_17_in), + .Q(\^time_control_regs[16] [21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][22] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_18_in), + .Q(\^time_control_regs[16] [22]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][23] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_19_in), + .Q(\^time_control_regs[16] [23]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][24] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_20_in), + .Q(\^time_control_regs[16] [24]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][25] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_21_in), + .Q(\^time_control_regs[16] [25]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][26] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_22_in), + .Q(\^time_control_regs[16] [26]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][27] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_23_in), + .Q(\^time_control_regs[16] [27]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][28] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_24_in), + .Q(\^time_control_regs[16] [28]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][2] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_1_in), + .Q(\^time_control_regs[16] [2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][3] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_2_in), + .Q(\^time_control_regs[16] [3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][4] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_3_in), + .Q(\^time_control_regs[16] [4]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][5] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_4_in), + .Q(\^time_control_regs[16] [5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][6] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_5_in), + .Q(\^time_control_regs[16] [6]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][7] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_6_in), + .Q(\^time_control_regs[16] [7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][8] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_7_in), + .Q(\^time_control_regs[16] [8]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][9] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_8_in), + .Q(\^time_control_regs[16] [9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[18][7] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_5_out[7]), + .Q(\^time_control_regs[18] [7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[18][8] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_5_out[8]), + .Q(\^time_control_regs[18] [8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[18][9] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_5_out[9]), + .Q(\^time_control_regs[18] [9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[19][0] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_8_out[0]), + .Q(\^time_control_regs[19] [0]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[19][1] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_8_out[1]), + .Q(\^time_control_regs[19] [1]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[19][2] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_8_out[2]), + .Q(\^time_control_regs[19] [2]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[19][3] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_8_out[3]), + .Q(\^time_control_regs[19] [3]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[19][4] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_8_out[4]), + .Q(\^time_control_regs[19] [4]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[19][5] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(p_8_out[5]), + .Q(\^time_control_regs[19] [5]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][0] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(\time_control_regs2_int[20] ), + .Q(\^time_control_regs[20] [0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][10] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[906]), + .Q(\^time_control_regs[20] [10]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][11] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[907]), + .Q(\^time_control_regs[20] [11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][12] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[908]), + .Q(\^time_control_regs[20] [12]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][16] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[912]), + .Q(\^time_control_regs[20] [16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][17] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[913]), + .Q(\^time_control_regs[20] [17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][18] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[914]), + .Q(\^time_control_regs[20] [18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][19] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[915]), + .Q(\^time_control_regs[20] [19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][1] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[897]), + .Q(\^time_control_regs[20] [1]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][20] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[916]), + .Q(\^time_control_regs[20] [20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][21] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[917]), + .Q(\^time_control_regs[20] [21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][22] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[918]), + .Q(\^time_control_regs[20] [22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][23] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[919]), + .Q(\^time_control_regs[20] [23]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][24] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[920]), + .Q(\^time_control_regs[20] [24]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][25] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[921]), + .Q(\^time_control_regs[20] [25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][26] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[922]), + .Q(\^time_control_regs[20] [26]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][27] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[923]), + .Q(\^time_control_regs[20] [27]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][28] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[924]), + .Q(\^time_control_regs[20] [28]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][2] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[898]), + .Q(\^time_control_regs[20] [2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][3] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[899]), + .Q(\^time_control_regs[20] [3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][4] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[900]), + .Q(\^time_control_regs[20] [4]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][5] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[901]), + .Q(\^time_control_regs[20] [5]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][6] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[902]), + .Q(\^time_control_regs[20] [6]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][7] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[903]), + .Q(\^time_control_regs[20] [7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][8] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[904]), + .Q(\^time_control_regs[20] [8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][9] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[905]), + .Q(\^time_control_regs[20] [9]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][0] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(\time_control_regs2_int[21] ), + .Q(\^time_control_regs[21] [0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][10] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[938]), + .Q(\^time_control_regs[21] [10]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][11] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[939]), + .Q(\^time_control_regs[21] [11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][12] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[940]), + .Q(\^time_control_regs[21] [12]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][16] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[944]), + .Q(\^time_control_regs[21] [16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][17] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[945]), + .Q(\^time_control_regs[21] [17]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][18] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[946]), + .Q(\^time_control_regs[21] [18]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][19] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[947]), + .Q(\^time_control_regs[21] [19]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][1] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[929]), + .Q(\^time_control_regs[21] [1]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][20] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[948]), + .Q(\^time_control_regs[21] [20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][21] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[949]), + .Q(\^time_control_regs[21] [21]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][22] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[950]), + .Q(\^time_control_regs[21] [22]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][23] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[951]), + .Q(\^time_control_regs[21] [23]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][24] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[952]), + .Q(\^time_control_regs[21] [24]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][25] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[953]), + .Q(\^time_control_regs[21] [25]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][26] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[954]), + .Q(\^time_control_regs[21] [26]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][27] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[955]), + .Q(\^time_control_regs[21] [27]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][28] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[956]), + .Q(\^time_control_regs[21] [28]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][2] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[930]), + .Q(\^time_control_regs[21] [2]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][3] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[931]), + .Q(\^time_control_regs[21] [3]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][4] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[932]), + .Q(\^time_control_regs[21] [4]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][5] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[933]), + .Q(\^time_control_regs[21] [5]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][6] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[934]), + .Q(\^time_control_regs[21] [6]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][7] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[935]), + .Q(\^time_control_regs[21] [7]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][8] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[936]), + .Q(\^time_control_regs[21] [8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][9] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[937]), + .Q(\^time_control_regs[21] [9]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][0] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(\time_control_regs2_int[22] ), + .Q(\^time_control_regs[22] [0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][10] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[970]), + .Q(\^time_control_regs[22] [10]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][11] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[971]), + .Q(\^time_control_regs[22] [11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][12] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[972]), + .Q(\^time_control_regs[22] [12]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][16] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[976]), + .Q(\^time_control_regs[22] [16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][17] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[977]), + .Q(\^time_control_regs[22] [17]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][18] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[978]), + .Q(\^time_control_regs[22] [18]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][19] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[979]), + .Q(\^time_control_regs[22] [19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][1] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[961]), + .Q(\^time_control_regs[22] [1]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][20] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[980]), + .Q(\^time_control_regs[22] [20]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][21] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[981]), + .Q(\^time_control_regs[22] [21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][22] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[982]), + .Q(\^time_control_regs[22] [22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][23] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[983]), + .Q(\^time_control_regs[22] [23]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][24] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[984]), + .Q(\^time_control_regs[22] [24]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][25] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[985]), + .Q(\^time_control_regs[22] [25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][26] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[986]), + .Q(\^time_control_regs[22] [26]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][27] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[987]), + .Q(\^time_control_regs[22] [27]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][28] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[988]), + .Q(\^time_control_regs[22] [28]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][2] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[962]), + .Q(\^time_control_regs[22] [2]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][3] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[963]), + .Q(\^time_control_regs[22] [3]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][4] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[964]), + .Q(\^time_control_regs[22] [4]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][5] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[965]), + .Q(\^time_control_regs[22] [5]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][6] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[966]), + .Q(\^time_control_regs[22] [6]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][7] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[967]), + .Q(\^time_control_regs[22] [7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][8] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[968]), + .Q(\^time_control_regs[22] [8]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][9] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[969]), + .Q(\^time_control_regs[22] [9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][0] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(\time_control_regs2_int[23] ), + .Q(\^time_control_regs[23] [0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][10] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1002]), + .Q(\^time_control_regs[23] [10]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][11] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1003]), + .Q(\^time_control_regs[23] [11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][12] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1004]), + .Q(\^time_control_regs[23] [12]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][16] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1008]), + .Q(\^time_control_regs[23] [16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][17] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1009]), + .Q(\^time_control_regs[23] [17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][18] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1010]), + .Q(\^time_control_regs[23] [18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][19] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1011]), + .Q(\^time_control_regs[23] [19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][1] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[993]), + .Q(\^time_control_regs[23] [1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][20] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1012]), + .Q(\^time_control_regs[23] [20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][21] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1013]), + .Q(\^time_control_regs[23] [21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][22] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1014]), + .Q(\^time_control_regs[23] [22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][23] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1015]), + .Q(\^time_control_regs[23] [23]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][24] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1016]), + .Q(\^time_control_regs[23] [24]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][25] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1017]), + .Q(\^time_control_regs[23] [25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][26] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1018]), + .Q(\^time_control_regs[23] [26]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][27] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1019]), + .Q(\^time_control_regs[23] [27]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][28] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1020]), + .Q(\^time_control_regs[23] [28]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][2] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[994]), + .Q(\^time_control_regs[23] [2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][3] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[995]), + .Q(\^time_control_regs[23] [3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][4] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[996]), + .Q(\^time_control_regs[23] [4]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][5] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[997]), + .Q(\^time_control_regs[23] [5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][6] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[998]), + .Q(\^time_control_regs[23] [6]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][7] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[999]), + .Q(\^time_control_regs[23] [7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][8] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1000]), + .Q(\^time_control_regs[23] [8]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][9] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1001]), + .Q(\^time_control_regs[23] [9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][0] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(\time_control_regs2_int[24] ), + .Q(\^time_control_regs[24] [0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][10] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1034]), + .Q(\^time_control_regs[24] [10]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][11] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1035]), + .Q(\^time_control_regs[24] [11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][12] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1036]), + .Q(\^time_control_regs[24] [12]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][16] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1040]), + .Q(\^time_control_regs[24] [16]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][17] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1041]), + .Q(\^time_control_regs[24] [17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][18] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1042]), + .Q(\^time_control_regs[24] [18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][19] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1043]), + .Q(\^time_control_regs[24] [19]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][1] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1025]), + .Q(\^time_control_regs[24] [1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][20] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1044]), + .Q(\^time_control_regs[24] [20]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][21] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1045]), + .Q(\^time_control_regs[24] [21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][22] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1046]), + .Q(\^time_control_regs[24] [22]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][23] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1047]), + .Q(\^time_control_regs[24] [23]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][24] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1048]), + .Q(\^time_control_regs[24] [24]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][25] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1049]), + .Q(\^time_control_regs[24] [25]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][26] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1050]), + .Q(\^time_control_regs[24] [26]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][27] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1051]), + .Q(\^time_control_regs[24] [27]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][28] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1052]), + .Q(\^time_control_regs[24] [28]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][2] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1026]), + .Q(\^time_control_regs[24] [2]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][3] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1027]), + .Q(\^time_control_regs[24] [3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][4] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1028]), + .Q(\^time_control_regs[24] [4]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][5] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1029]), + .Q(\^time_control_regs[24] [5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][6] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1030]), + .Q(\^time_control_regs[24] [6]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][7] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1031]), + .Q(\^time_control_regs[24] [7]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][8] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1032]), + .Q(\^time_control_regs[24] [8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][9] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1033]), + .Q(\^time_control_regs[24] [9]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][0] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(\time_control_regs2_int[25] ), + .Q(\^time_control_regs[25] [0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][10] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1066]), + .Q(\^time_control_regs[25] [10]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][11] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1067]), + .Q(\^time_control_regs[25] [11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][12] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1068]), + .Q(\^time_control_regs[25] [12]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][16] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1072]), + .Q(\^time_control_regs[25] [16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][17] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1073]), + .Q(\^time_control_regs[25] [17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][18] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1074]), + .Q(\^time_control_regs[25] [18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][19] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1075]), + .Q(\^time_control_regs[25] [19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][1] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1057]), + .Q(\^time_control_regs[25] [1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][20] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1076]), + .Q(\^time_control_regs[25] [20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][21] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1077]), + .Q(\^time_control_regs[25] [21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][22] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1078]), + .Q(\^time_control_regs[25] [22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][23] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1079]), + .Q(\^time_control_regs[25] [23]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][24] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1080]), + .Q(\^time_control_regs[25] [24]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][25] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1081]), + .Q(\^time_control_regs[25] [25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][26] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1082]), + .Q(\^time_control_regs[25] [26]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][27] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1083]), + .Q(\^time_control_regs[25] [27]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][28] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1084]), + .Q(\^time_control_regs[25] [28]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][2] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1058]), + .Q(\^time_control_regs[25] [2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][3] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1059]), + .Q(\^time_control_regs[25] [3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][4] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1060]), + .Q(\^time_control_regs[25] [4]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][5] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1061]), + .Q(\^time_control_regs[25] [5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][6] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1062]), + .Q(\^time_control_regs[25] [6]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][7] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1063]), + .Q(\^time_control_regs[25] [7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][8] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1064]), + .Q(\^time_control_regs[25] [8]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][9] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1065]), + .Q(\^time_control_regs[25] [9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][0] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(\time_control_regs2_int[26] ), + .Q(\^time_control_regs[26] [0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][10] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1098]), + .Q(\^time_control_regs[26] [10]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][11] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1099]), + .Q(\^time_control_regs[26] [11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][12] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1100]), + .Q(\^time_control_regs[26] [12]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][16] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1104]), + .Q(\^time_control_regs[26] [16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][17] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1105]), + .Q(\^time_control_regs[26] [17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][18] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1106]), + .Q(\^time_control_regs[26] [18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][19] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1107]), + .Q(\^time_control_regs[26] [19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][1] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1089]), + .Q(\^time_control_regs[26] [1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][20] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1108]), + .Q(\^time_control_regs[26] [20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][21] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1109]), + .Q(\^time_control_regs[26] [21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][22] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1110]), + .Q(\^time_control_regs[26] [22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][23] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1111]), + .Q(\^time_control_regs[26] [23]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][24] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1112]), + .Q(\^time_control_regs[26] [24]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][25] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1113]), + .Q(\^time_control_regs[26] [25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][26] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1114]), + .Q(\^time_control_regs[26] [26]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][27] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1115]), + .Q(\^time_control_regs[26] [27]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][28] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1116]), + .Q(\^time_control_regs[26] [28]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][2] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1090]), + .Q(\^time_control_regs[26] [2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][3] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1091]), + .Q(\^time_control_regs[26] [3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][4] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1092]), + .Q(\^time_control_regs[26] [4]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][5] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1093]), + .Q(\^time_control_regs[26] [5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][6] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1094]), + .Q(\^time_control_regs[26] [6]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][7] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1095]), + .Q(\^time_control_regs[26] [7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][8] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1096]), + .Q(\^time_control_regs[26] [8]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][9] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1097]), + .Q(\^time_control_regs[26] [9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][0] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(\time_control_regs2_int[27] ), + .Q(\^time_control_regs[27] [0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][10] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1130]), + .Q(\^time_control_regs[27] [10]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][11] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1131]), + .Q(\^time_control_regs[27] [11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][12] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1132]), + .Q(\^time_control_regs[27] [12]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][16] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1136]), + .Q(\^time_control_regs[27] [16]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][17] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1137]), + .Q(\^time_control_regs[27] [17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][18] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1138]), + .Q(\^time_control_regs[27] [18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][19] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1139]), + .Q(\^time_control_regs[27] [19]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][1] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1121]), + .Q(\^time_control_regs[27] [1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][20] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1140]), + .Q(\^time_control_regs[27] [20]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][21] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1141]), + .Q(\^time_control_regs[27] [21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][22] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1142]), + .Q(\^time_control_regs[27] [22]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][23] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1143]), + .Q(\^time_control_regs[27] [23]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][24] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1144]), + .Q(\^time_control_regs[27] [24]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][25] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1145]), + .Q(\^time_control_regs[27] [25]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][26] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1146]), + .Q(\^time_control_regs[27] [26]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][27] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1147]), + .Q(\^time_control_regs[27] [27]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][28] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1148]), + .Q(\^time_control_regs[27] [28]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][2] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1122]), + .Q(\^time_control_regs[27] [2]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][3] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1123]), + .Q(\^time_control_regs[27] [3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][4] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1124]), + .Q(\^time_control_regs[27] [4]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][5] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1125]), + .Q(\^time_control_regs[27] [5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][6] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1126]), + .Q(\^time_control_regs[27] [6]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][7] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1127]), + .Q(\^time_control_regs[27] [7]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][8] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1128]), + .Q(\^time_control_regs[27] [8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][9] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1129]), + .Q(\^time_control_regs[27] [9]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][0] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(\time_control_regs2_int[28] ), + .Q(\^time_control_regs[28] [0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][10] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1162]), + .Q(\^time_control_regs[28] [10]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][11] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1163]), + .Q(\^time_control_regs[28] [11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][12] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1164]), + .Q(\^time_control_regs[28] [12]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][16] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1168]), + .Q(\^time_control_regs[28] [16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][17] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1169]), + .Q(\^time_control_regs[28] [17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][18] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1170]), + .Q(\^time_control_regs[28] [18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][19] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1171]), + .Q(\^time_control_regs[28] [19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][1] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1153]), + .Q(\^time_control_regs[28] [1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][20] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1172]), + .Q(\^time_control_regs[28] [20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][21] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1173]), + .Q(\^time_control_regs[28] [21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][22] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1174]), + .Q(\^time_control_regs[28] [22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][23] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1175]), + .Q(\^time_control_regs[28] [23]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][24] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1176]), + .Q(\^time_control_regs[28] [24]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][25] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1177]), + .Q(\^time_control_regs[28] [25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][26] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1178]), + .Q(\^time_control_regs[28] [26]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][27] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1179]), + .Q(\^time_control_regs[28] [27]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][28] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1180]), + .Q(\^time_control_regs[28] [28]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][2] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1154]), + .Q(\^time_control_regs[28] [2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][3] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1155]), + .Q(\^time_control_regs[28] [3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][4] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1156]), + .Q(\^time_control_regs[28] [4]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][5] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1157]), + .Q(\^time_control_regs[28] [5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][6] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1158]), + .Q(\^time_control_regs[28] [6]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][7] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1159]), + .Q(\^time_control_regs[28] [7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][8] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1160]), + .Q(\^time_control_regs[28] [8]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][9] + (.C(vid_aclk), + .CE(\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0 ), + .D(genr_regs[1161]), + .Q(\^time_control_regs[28] [9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][0] + (.C(vid_aclk), + .CE(\time_control_regs_int[16] ), + .D(ipif_data_out[0]), + .Q(\time_control_regs2_int[16] ), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][10] + (.C(vid_aclk), + .CE(\time_control_regs_int[16] ), + .D(ipif_data_out[10]), + .Q(p_9_in), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][11] + (.C(vid_aclk), + .CE(\time_control_regs_int[16] ), + .D(ipif_data_out[11]), + .Q(p_10_in), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][12] + (.C(vid_aclk), + .CE(\time_control_regs_int[16] ), + .D(ipif_data_out[12]), + .Q(p_11_in), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][16] + (.C(vid_aclk), + .CE(\time_control_regs_int[16] ), + .D(ipif_data_out[16]), + .Q(p_12_in), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][17] + (.C(vid_aclk), + .CE(\time_control_regs_int[16] ), + .D(ipif_data_out[17]), + .Q(p_13_in), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][18] + (.C(vid_aclk), + .CE(\time_control_regs_int[16] ), + .D(ipif_data_out[18]), + .Q(p_14_in), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][19] + (.C(vid_aclk), + .CE(\time_control_regs_int[16] ), + .D(ipif_data_out[19]), + .Q(p_15_in), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][1] + (.C(vid_aclk), + .CE(\time_control_regs_int[16] ), + .D(ipif_data_out[1]), + .Q(p_0_in), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][20] + (.C(vid_aclk), + .CE(\time_control_regs_int[16] ), + .D(ipif_data_out[20]), + .Q(p_16_in), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][21] + (.C(vid_aclk), + .CE(\time_control_regs_int[16] ), + .D(ipif_data_out[21]), + .Q(p_17_in), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][22] + (.C(vid_aclk), + .CE(\time_control_regs_int[16] ), + .D(ipif_data_out[22]), + .Q(p_18_in), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][23] + (.C(vid_aclk), + .CE(\time_control_regs_int[16] ), + .D(ipif_data_out[23]), + .Q(p_19_in), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][24] + (.C(vid_aclk), + .CE(\time_control_regs_int[16] ), + .D(ipif_data_out[24]), + .Q(p_20_in), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][25] + (.C(vid_aclk), + .CE(\time_control_regs_int[16] ), + .D(ipif_data_out[25]), + .Q(p_21_in), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][26] + (.C(vid_aclk), + .CE(\time_control_regs_int[16] ), + .D(ipif_data_out[26]), + .Q(p_22_in), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][27] + (.C(vid_aclk), + .CE(\time_control_regs_int[16] ), + .D(ipif_data_out[27]), + .Q(p_23_in), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28] + (.C(vid_aclk), + .CE(\time_control_regs_int[16] ), + .D(ipif_data_out[28]), + .Q(p_24_in), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][2] + (.C(vid_aclk), + .CE(\time_control_regs_int[16] ), + .D(ipif_data_out[2]), + .Q(p_1_in), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][3] + (.C(vid_aclk), + .CE(\time_control_regs_int[16] ), + .D(ipif_data_out[3]), + .Q(p_2_in), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][4] + (.C(vid_aclk), + .CE(\time_control_regs_int[16] ), + .D(ipif_data_out[4]), + .Q(p_3_in), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][5] + (.C(vid_aclk), + .CE(\time_control_regs_int[16] ), + .D(ipif_data_out[5]), + .Q(p_4_in), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][6] + (.C(vid_aclk), + .CE(\time_control_regs_int[16] ), + .D(ipif_data_out[6]), + .Q(p_5_in), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][7] + (.C(vid_aclk), + .CE(\time_control_regs_int[16] ), + .D(ipif_data_out[7]), + .Q(p_6_in), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][8] + (.C(vid_aclk), + .CE(\time_control_regs_int[16] ), + .D(ipif_data_out[8]), + .Q(p_7_in), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][9] + (.C(vid_aclk), + .CE(\time_control_regs_int[16] ), + .D(ipif_data_out[9]), + .Q(p_8_in), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][0] + (.C(vid_aclk), + .CE(\time_control_regs_int[18] ), + .D(ipif_data_out[0]), + .Q(\^time_control_regs[18] [0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][1] + (.C(vid_aclk), + .CE(\time_control_regs_int[18] ), + .D(ipif_data_out[1]), + .Q(\^time_control_regs[18] [1]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][2] + (.C(vid_aclk), + .CE(\time_control_regs_int[18] ), + .D(ipif_data_out[2]), + .Q(\^time_control_regs[18] [2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][3] + (.C(vid_aclk), + .CE(\time_control_regs_int[18] ), + .D(ipif_data_out[3]), + .Q(\^time_control_regs[18] [3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][6] + (.C(vid_aclk), + .CE(\time_control_regs_int[18] ), + .D(ipif_data_out[6]), + .Q(\^time_control_regs[18] [6]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][7] + (.C(vid_aclk), + .CE(\time_control_regs_int[18] ), + .D(ipif_data_out[7]), + .Q(p_5_out[7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][8] + (.C(vid_aclk), + .CE(\time_control_regs_int[18] ), + .D(ipif_data_out[8]), + .Q(p_5_out[8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9] + (.C(vid_aclk), + .CE(\time_control_regs_int[18] ), + .D(ipif_data_out[9]), + .Q(p_5_out[9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][0] + (.C(vid_aclk), + .CE(p_2_out), + .D(ipif_data_out[0]), + .Q(p_8_out[0]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][1] + (.C(vid_aclk), + .CE(p_2_out), + .D(ipif_data_out[1]), + .Q(p_8_out[1]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][2] + (.C(vid_aclk), + .CE(p_2_out), + .D(ipif_data_out[2]), + .Q(p_8_out[2]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][3] + (.C(vid_aclk), + .CE(p_2_out), + .D(ipif_data_out[3]), + .Q(p_8_out[3]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][4] + (.C(vid_aclk), + .CE(p_2_out), + .D(ipif_data_out[4]), + .Q(p_8_out[4]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][5] + (.C(vid_aclk), + .CE(p_2_out), + .D(ipif_data_out[5]), + .Q(p_8_out[5]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6] + (.C(vid_aclk), + .CE(p_2_out), + .D(ipif_data_out[6]), + .Q(\^time_control_regs[19] [6]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][0] + (.C(vid_aclk), + .CE(\time_control_regs_int[20] ), + .D(ipif_data_out[0]), + .Q(\time_control_regs2_int[20] ), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][10] + (.C(vid_aclk), + .CE(\time_control_regs_int[20] ), + .D(ipif_data_out[10]), + .Q(genr_regs[906]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][11] + (.C(vid_aclk), + .CE(\time_control_regs_int[20] ), + .D(ipif_data_out[11]), + .Q(genr_regs[907]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][12] + (.C(vid_aclk), + .CE(\time_control_regs_int[20] ), + .D(ipif_data_out[12]), + .Q(genr_regs[908]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][16] + (.C(vid_aclk), + .CE(\time_control_regs_int[20] ), + .D(ipif_data_out[16]), + .Q(genr_regs[912]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][17] + (.C(vid_aclk), + .CE(\time_control_regs_int[20] ), + .D(ipif_data_out[17]), + .Q(genr_regs[913]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][18] + (.C(vid_aclk), + .CE(\time_control_regs_int[20] ), + .D(ipif_data_out[18]), + .Q(genr_regs[914]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][19] + (.C(vid_aclk), + .CE(\time_control_regs_int[20] ), + .D(ipif_data_out[19]), + .Q(genr_regs[915]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][1] + (.C(vid_aclk), + .CE(\time_control_regs_int[20] ), + .D(ipif_data_out[1]), + .Q(genr_regs[897]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][20] + (.C(vid_aclk), + .CE(\time_control_regs_int[20] ), + .D(ipif_data_out[20]), + .Q(genr_regs[916]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][21] + (.C(vid_aclk), + .CE(\time_control_regs_int[20] ), + .D(ipif_data_out[21]), + .Q(genr_regs[917]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][22] + (.C(vid_aclk), + .CE(\time_control_regs_int[20] ), + .D(ipif_data_out[22]), + .Q(genr_regs[918]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][23] + (.C(vid_aclk), + .CE(\time_control_regs_int[20] ), + .D(ipif_data_out[23]), + .Q(genr_regs[919]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][24] + (.C(vid_aclk), + .CE(\time_control_regs_int[20] ), + .D(ipif_data_out[24]), + .Q(genr_regs[920]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][25] + (.C(vid_aclk), + .CE(\time_control_regs_int[20] ), + .D(ipif_data_out[25]), + .Q(genr_regs[921]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][26] + (.C(vid_aclk), + .CE(\time_control_regs_int[20] ), + .D(ipif_data_out[26]), + .Q(genr_regs[922]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][27] + (.C(vid_aclk), + .CE(\time_control_regs_int[20] ), + .D(ipif_data_out[27]), + .Q(genr_regs[923]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28] + (.C(vid_aclk), + .CE(\time_control_regs_int[20] ), + .D(ipif_data_out[28]), + .Q(genr_regs[924]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][2] + (.C(vid_aclk), + .CE(\time_control_regs_int[20] ), + .D(ipif_data_out[2]), + .Q(genr_regs[898]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][3] + (.C(vid_aclk), + .CE(\time_control_regs_int[20] ), + .D(ipif_data_out[3]), + .Q(genr_regs[899]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][4] + (.C(vid_aclk), + .CE(\time_control_regs_int[20] ), + .D(ipif_data_out[4]), + .Q(genr_regs[900]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][5] + (.C(vid_aclk), + .CE(\time_control_regs_int[20] ), + .D(ipif_data_out[5]), + .Q(genr_regs[901]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][6] + (.C(vid_aclk), + .CE(\time_control_regs_int[20] ), + .D(ipif_data_out[6]), + .Q(genr_regs[902]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][7] + (.C(vid_aclk), + .CE(\time_control_regs_int[20] ), + .D(ipif_data_out[7]), + .Q(genr_regs[903]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][8] + (.C(vid_aclk), + .CE(\time_control_regs_int[20] ), + .D(ipif_data_out[8]), + .Q(genr_regs[904]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][9] + (.C(vid_aclk), + .CE(\time_control_regs_int[20] ), + .D(ipif_data_out[9]), + .Q(genr_regs[905]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][0] + (.C(vid_aclk), + .CE(\time_control_regs_int[21] ), + .D(ipif_data_out[0]), + .Q(\time_control_regs2_int[21] ), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][10] + (.C(vid_aclk), + .CE(\time_control_regs_int[21] ), + .D(ipif_data_out[10]), + .Q(genr_regs[938]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][11] + (.C(vid_aclk), + .CE(\time_control_regs_int[21] ), + .D(ipif_data_out[11]), + .Q(genr_regs[939]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][12] + (.C(vid_aclk), + .CE(\time_control_regs_int[21] ), + .D(ipif_data_out[12]), + .Q(genr_regs[940]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][16] + (.C(vid_aclk), + .CE(\time_control_regs_int[21] ), + .D(ipif_data_out[16]), + .Q(genr_regs[944]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][17] + (.C(vid_aclk), + .CE(\time_control_regs_int[21] ), + .D(ipif_data_out[17]), + .Q(genr_regs[945]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][18] + (.C(vid_aclk), + .CE(\time_control_regs_int[21] ), + .D(ipif_data_out[18]), + .Q(genr_regs[946]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][19] + (.C(vid_aclk), + .CE(\time_control_regs_int[21] ), + .D(ipif_data_out[19]), + .Q(genr_regs[947]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][1] + (.C(vid_aclk), + .CE(\time_control_regs_int[21] ), + .D(ipif_data_out[1]), + .Q(genr_regs[929]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][20] + (.C(vid_aclk), + .CE(\time_control_regs_int[21] ), + .D(ipif_data_out[20]), + .Q(genr_regs[948]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][21] + (.C(vid_aclk), + .CE(\time_control_regs_int[21] ), + .D(ipif_data_out[21]), + .Q(genr_regs[949]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][22] + (.C(vid_aclk), + .CE(\time_control_regs_int[21] ), + .D(ipif_data_out[22]), + .Q(genr_regs[950]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][23] + (.C(vid_aclk), + .CE(\time_control_regs_int[21] ), + .D(ipif_data_out[23]), + .Q(genr_regs[951]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][24] + (.C(vid_aclk), + .CE(\time_control_regs_int[21] ), + .D(ipif_data_out[24]), + .Q(genr_regs[952]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][25] + (.C(vid_aclk), + .CE(\time_control_regs_int[21] ), + .D(ipif_data_out[25]), + .Q(genr_regs[953]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][26] + (.C(vid_aclk), + .CE(\time_control_regs_int[21] ), + .D(ipif_data_out[26]), + .Q(genr_regs[954]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][27] + (.C(vid_aclk), + .CE(\time_control_regs_int[21] ), + .D(ipif_data_out[27]), + .Q(genr_regs[955]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28] + (.C(vid_aclk), + .CE(\time_control_regs_int[21] ), + .D(ipif_data_out[28]), + .Q(genr_regs[956]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][2] + (.C(vid_aclk), + .CE(\time_control_regs_int[21] ), + .D(ipif_data_out[2]), + .Q(genr_regs[930]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][3] + (.C(vid_aclk), + .CE(\time_control_regs_int[21] ), + .D(ipif_data_out[3]), + .Q(genr_regs[931]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][4] + (.C(vid_aclk), + .CE(\time_control_regs_int[21] ), + .D(ipif_data_out[4]), + .Q(genr_regs[932]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][5] + (.C(vid_aclk), + .CE(\time_control_regs_int[21] ), + .D(ipif_data_out[5]), + .Q(genr_regs[933]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][6] + (.C(vid_aclk), + .CE(\time_control_regs_int[21] ), + .D(ipif_data_out[6]), + .Q(genr_regs[934]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][7] + (.C(vid_aclk), + .CE(\time_control_regs_int[21] ), + .D(ipif_data_out[7]), + .Q(genr_regs[935]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][8] + (.C(vid_aclk), + .CE(\time_control_regs_int[21] ), + .D(ipif_data_out[8]), + .Q(genr_regs[936]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][9] + (.C(vid_aclk), + .CE(\time_control_regs_int[21] ), + .D(ipif_data_out[9]), + .Q(genr_regs[937]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][0] + (.C(vid_aclk), + .CE(\time_control_regs_int[22] ), + .D(ipif_data_out[0]), + .Q(\time_control_regs2_int[22] ), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][10] + (.C(vid_aclk), + .CE(\time_control_regs_int[22] ), + .D(ipif_data_out[10]), + .Q(genr_regs[970]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][11] + (.C(vid_aclk), + .CE(\time_control_regs_int[22] ), + .D(ipif_data_out[11]), + .Q(genr_regs[971]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][12] + (.C(vid_aclk), + .CE(\time_control_regs_int[22] ), + .D(ipif_data_out[12]), + .Q(genr_regs[972]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][16] + (.C(vid_aclk), + .CE(\time_control_regs_int[22] ), + .D(ipif_data_out[16]), + .Q(genr_regs[976]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][17] + (.C(vid_aclk), + .CE(\time_control_regs_int[22] ), + .D(ipif_data_out[17]), + .Q(genr_regs[977]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][18] + (.C(vid_aclk), + .CE(\time_control_regs_int[22] ), + .D(ipif_data_out[18]), + .Q(genr_regs[978]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][19] + (.C(vid_aclk), + .CE(\time_control_regs_int[22] ), + .D(ipif_data_out[19]), + .Q(genr_regs[979]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][1] + (.C(vid_aclk), + .CE(\time_control_regs_int[22] ), + .D(ipif_data_out[1]), + .Q(genr_regs[961]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][20] + (.C(vid_aclk), + .CE(\time_control_regs_int[22] ), + .D(ipif_data_out[20]), + .Q(genr_regs[980]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][21] + (.C(vid_aclk), + .CE(\time_control_regs_int[22] ), + .D(ipif_data_out[21]), + .Q(genr_regs[981]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][22] + (.C(vid_aclk), + .CE(\time_control_regs_int[22] ), + .D(ipif_data_out[22]), + .Q(genr_regs[982]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][23] + (.C(vid_aclk), + .CE(\time_control_regs_int[22] ), + .D(ipif_data_out[23]), + .Q(genr_regs[983]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][24] + (.C(vid_aclk), + .CE(\time_control_regs_int[22] ), + .D(ipif_data_out[24]), + .Q(genr_regs[984]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][25] + (.C(vid_aclk), + .CE(\time_control_regs_int[22] ), + .D(ipif_data_out[25]), + .Q(genr_regs[985]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][26] + (.C(vid_aclk), + .CE(\time_control_regs_int[22] ), + .D(ipif_data_out[26]), + .Q(genr_regs[986]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][27] + (.C(vid_aclk), + .CE(\time_control_regs_int[22] ), + .D(ipif_data_out[27]), + .Q(genr_regs[987]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28] + (.C(vid_aclk), + .CE(\time_control_regs_int[22] ), + .D(ipif_data_out[28]), + .Q(genr_regs[988]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][2] + (.C(vid_aclk), + .CE(\time_control_regs_int[22] ), + .D(ipif_data_out[2]), + .Q(genr_regs[962]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][3] + (.C(vid_aclk), + .CE(\time_control_regs_int[22] ), + .D(ipif_data_out[3]), + .Q(genr_regs[963]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][4] + (.C(vid_aclk), + .CE(\time_control_regs_int[22] ), + .D(ipif_data_out[4]), + .Q(genr_regs[964]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][5] + (.C(vid_aclk), + .CE(\time_control_regs_int[22] ), + .D(ipif_data_out[5]), + .Q(genr_regs[965]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][6] + (.C(vid_aclk), + .CE(\time_control_regs_int[22] ), + .D(ipif_data_out[6]), + .Q(genr_regs[966]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][7] + (.C(vid_aclk), + .CE(\time_control_regs_int[22] ), + .D(ipif_data_out[7]), + .Q(genr_regs[967]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][8] + (.C(vid_aclk), + .CE(\time_control_regs_int[22] ), + .D(ipif_data_out[8]), + .Q(genr_regs[968]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][9] + (.C(vid_aclk), + .CE(\time_control_regs_int[22] ), + .D(ipif_data_out[9]), + .Q(genr_regs[969]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][0] + (.C(vid_aclk), + .CE(\time_control_regs_int[23] ), + .D(ipif_data_out[0]), + .Q(\time_control_regs2_int[23] ), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][10] + (.C(vid_aclk), + .CE(\time_control_regs_int[23] ), + .D(ipif_data_out[10]), + .Q(genr_regs[1002]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][11] + (.C(vid_aclk), + .CE(\time_control_regs_int[23] ), + .D(ipif_data_out[11]), + .Q(genr_regs[1003]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][12] + (.C(vid_aclk), + .CE(\time_control_regs_int[23] ), + .D(ipif_data_out[12]), + .Q(genr_regs[1004]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][16] + (.C(vid_aclk), + .CE(\time_control_regs_int[23] ), + .D(ipif_data_out[16]), + .Q(genr_regs[1008]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][17] + (.C(vid_aclk), + .CE(\time_control_regs_int[23] ), + .D(ipif_data_out[17]), + .Q(genr_regs[1009]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][18] + (.C(vid_aclk), + .CE(\time_control_regs_int[23] ), + .D(ipif_data_out[18]), + .Q(genr_regs[1010]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][19] + (.C(vid_aclk), + .CE(\time_control_regs_int[23] ), + .D(ipif_data_out[19]), + .Q(genr_regs[1011]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][1] + (.C(vid_aclk), + .CE(\time_control_regs_int[23] ), + .D(ipif_data_out[1]), + .Q(genr_regs[993]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][20] + (.C(vid_aclk), + .CE(\time_control_regs_int[23] ), + .D(ipif_data_out[20]), + .Q(genr_regs[1012]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][21] + (.C(vid_aclk), + .CE(\time_control_regs_int[23] ), + .D(ipif_data_out[21]), + .Q(genr_regs[1013]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][22] + (.C(vid_aclk), + .CE(\time_control_regs_int[23] ), + .D(ipif_data_out[22]), + .Q(genr_regs[1014]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][23] + (.C(vid_aclk), + .CE(\time_control_regs_int[23] ), + .D(ipif_data_out[23]), + .Q(genr_regs[1015]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][24] + (.C(vid_aclk), + .CE(\time_control_regs_int[23] ), + .D(ipif_data_out[24]), + .Q(genr_regs[1016]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][25] + (.C(vid_aclk), + .CE(\time_control_regs_int[23] ), + .D(ipif_data_out[25]), + .Q(genr_regs[1017]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][26] + (.C(vid_aclk), + .CE(\time_control_regs_int[23] ), + .D(ipif_data_out[26]), + .Q(genr_regs[1018]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][27] + (.C(vid_aclk), + .CE(\time_control_regs_int[23] ), + .D(ipif_data_out[27]), + .Q(genr_regs[1019]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28] + (.C(vid_aclk), + .CE(\time_control_regs_int[23] ), + .D(ipif_data_out[28]), + .Q(genr_regs[1020]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][2] + (.C(vid_aclk), + .CE(\time_control_regs_int[23] ), + .D(ipif_data_out[2]), + .Q(genr_regs[994]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][3] + (.C(vid_aclk), + .CE(\time_control_regs_int[23] ), + .D(ipif_data_out[3]), + .Q(genr_regs[995]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][4] + (.C(vid_aclk), + .CE(\time_control_regs_int[23] ), + .D(ipif_data_out[4]), + .Q(genr_regs[996]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][5] + (.C(vid_aclk), + .CE(\time_control_regs_int[23] ), + .D(ipif_data_out[5]), + .Q(genr_regs[997]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][6] + (.C(vid_aclk), + .CE(\time_control_regs_int[23] ), + .D(ipif_data_out[6]), + .Q(genr_regs[998]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][7] + (.C(vid_aclk), + .CE(\time_control_regs_int[23] ), + .D(ipif_data_out[7]), + .Q(genr_regs[999]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][8] + (.C(vid_aclk), + .CE(\time_control_regs_int[23] ), + .D(ipif_data_out[8]), + .Q(genr_regs[1000]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][9] + (.C(vid_aclk), + .CE(\time_control_regs_int[23] ), + .D(ipif_data_out[9]), + .Q(genr_regs[1001]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][0] + (.C(vid_aclk), + .CE(\time_control_regs_int[24] ), + .D(ipif_data_out[0]), + .Q(\time_control_regs2_int[24] ), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][10] + (.C(vid_aclk), + .CE(\time_control_regs_int[24] ), + .D(ipif_data_out[10]), + .Q(genr_regs[1034]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][11] + (.C(vid_aclk), + .CE(\time_control_regs_int[24] ), + .D(ipif_data_out[11]), + .Q(genr_regs[1035]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][12] + (.C(vid_aclk), + .CE(\time_control_regs_int[24] ), + .D(ipif_data_out[12]), + .Q(genr_regs[1036]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][16] + (.C(vid_aclk), + .CE(\time_control_regs_int[24] ), + .D(ipif_data_out[16]), + .Q(genr_regs[1040]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][17] + (.C(vid_aclk), + .CE(\time_control_regs_int[24] ), + .D(ipif_data_out[17]), + .Q(genr_regs[1041]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][18] + (.C(vid_aclk), + .CE(\time_control_regs_int[24] ), + .D(ipif_data_out[18]), + .Q(genr_regs[1042]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][19] + (.C(vid_aclk), + .CE(\time_control_regs_int[24] ), + .D(ipif_data_out[19]), + .Q(genr_regs[1043]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][1] + (.C(vid_aclk), + .CE(\time_control_regs_int[24] ), + .D(ipif_data_out[1]), + .Q(genr_regs[1025]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][20] + (.C(vid_aclk), + .CE(\time_control_regs_int[24] ), + .D(ipif_data_out[20]), + .Q(genr_regs[1044]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][21] + (.C(vid_aclk), + .CE(\time_control_regs_int[24] ), + .D(ipif_data_out[21]), + .Q(genr_regs[1045]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][22] + (.C(vid_aclk), + .CE(\time_control_regs_int[24] ), + .D(ipif_data_out[22]), + .Q(genr_regs[1046]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][23] + (.C(vid_aclk), + .CE(\time_control_regs_int[24] ), + .D(ipif_data_out[23]), + .Q(genr_regs[1047]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][24] + (.C(vid_aclk), + .CE(\time_control_regs_int[24] ), + .D(ipif_data_out[24]), + .Q(genr_regs[1048]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][25] + (.C(vid_aclk), + .CE(\time_control_regs_int[24] ), + .D(ipif_data_out[25]), + .Q(genr_regs[1049]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][26] + (.C(vid_aclk), + .CE(\time_control_regs_int[24] ), + .D(ipif_data_out[26]), + .Q(genr_regs[1050]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][27] + (.C(vid_aclk), + .CE(\time_control_regs_int[24] ), + .D(ipif_data_out[27]), + .Q(genr_regs[1051]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28] + (.C(vid_aclk), + .CE(\time_control_regs_int[24] ), + .D(ipif_data_out[28]), + .Q(genr_regs[1052]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][2] + (.C(vid_aclk), + .CE(\time_control_regs_int[24] ), + .D(ipif_data_out[2]), + .Q(genr_regs[1026]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][3] + (.C(vid_aclk), + .CE(\time_control_regs_int[24] ), + .D(ipif_data_out[3]), + .Q(genr_regs[1027]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][4] + (.C(vid_aclk), + .CE(\time_control_regs_int[24] ), + .D(ipif_data_out[4]), + .Q(genr_regs[1028]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][5] + (.C(vid_aclk), + .CE(\time_control_regs_int[24] ), + .D(ipif_data_out[5]), + .Q(genr_regs[1029]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][6] + (.C(vid_aclk), + .CE(\time_control_regs_int[24] ), + .D(ipif_data_out[6]), + .Q(genr_regs[1030]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][7] + (.C(vid_aclk), + .CE(\time_control_regs_int[24] ), + .D(ipif_data_out[7]), + .Q(genr_regs[1031]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][8] + (.C(vid_aclk), + .CE(\time_control_regs_int[24] ), + .D(ipif_data_out[8]), + .Q(genr_regs[1032]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][9] + (.C(vid_aclk), + .CE(\time_control_regs_int[24] ), + .D(ipif_data_out[9]), + .Q(genr_regs[1033]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][0] + (.C(vid_aclk), + .CE(\time_control_regs_int[25] ), + .D(ipif_data_out[0]), + .Q(\time_control_regs2_int[25] ), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][10] + (.C(vid_aclk), + .CE(\time_control_regs_int[25] ), + .D(ipif_data_out[10]), + .Q(genr_regs[1066]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][11] + (.C(vid_aclk), + .CE(\time_control_regs_int[25] ), + .D(ipif_data_out[11]), + .Q(genr_regs[1067]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][12] + (.C(vid_aclk), + .CE(\time_control_regs_int[25] ), + .D(ipif_data_out[12]), + .Q(genr_regs[1068]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][16] + (.C(vid_aclk), + .CE(\time_control_regs_int[25] ), + .D(ipif_data_out[16]), + .Q(genr_regs[1072]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][17] + (.C(vid_aclk), + .CE(\time_control_regs_int[25] ), + .D(ipif_data_out[17]), + .Q(genr_regs[1073]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][18] + (.C(vid_aclk), + .CE(\time_control_regs_int[25] ), + .D(ipif_data_out[18]), + .Q(genr_regs[1074]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][19] + (.C(vid_aclk), + .CE(\time_control_regs_int[25] ), + .D(ipif_data_out[19]), + .Q(genr_regs[1075]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][1] + (.C(vid_aclk), + .CE(\time_control_regs_int[25] ), + .D(ipif_data_out[1]), + .Q(genr_regs[1057]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][20] + (.C(vid_aclk), + .CE(\time_control_regs_int[25] ), + .D(ipif_data_out[20]), + .Q(genr_regs[1076]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][21] + (.C(vid_aclk), + .CE(\time_control_regs_int[25] ), + .D(ipif_data_out[21]), + .Q(genr_regs[1077]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][22] + (.C(vid_aclk), + .CE(\time_control_regs_int[25] ), + .D(ipif_data_out[22]), + .Q(genr_regs[1078]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][23] + (.C(vid_aclk), + .CE(\time_control_regs_int[25] ), + .D(ipif_data_out[23]), + .Q(genr_regs[1079]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][24] + (.C(vid_aclk), + .CE(\time_control_regs_int[25] ), + .D(ipif_data_out[24]), + .Q(genr_regs[1080]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][25] + (.C(vid_aclk), + .CE(\time_control_regs_int[25] ), + .D(ipif_data_out[25]), + .Q(genr_regs[1081]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][26] + (.C(vid_aclk), + .CE(\time_control_regs_int[25] ), + .D(ipif_data_out[26]), + .Q(genr_regs[1082]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][27] + (.C(vid_aclk), + .CE(\time_control_regs_int[25] ), + .D(ipif_data_out[27]), + .Q(genr_regs[1083]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28] + (.C(vid_aclk), + .CE(\time_control_regs_int[25] ), + .D(ipif_data_out[28]), + .Q(genr_regs[1084]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][2] + (.C(vid_aclk), + .CE(\time_control_regs_int[25] ), + .D(ipif_data_out[2]), + .Q(genr_regs[1058]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][3] + (.C(vid_aclk), + .CE(\time_control_regs_int[25] ), + .D(ipif_data_out[3]), + .Q(genr_regs[1059]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][4] + (.C(vid_aclk), + .CE(\time_control_regs_int[25] ), + .D(ipif_data_out[4]), + .Q(genr_regs[1060]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][5] + (.C(vid_aclk), + .CE(\time_control_regs_int[25] ), + .D(ipif_data_out[5]), + .Q(genr_regs[1061]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][6] + (.C(vid_aclk), + .CE(\time_control_regs_int[25] ), + .D(ipif_data_out[6]), + .Q(genr_regs[1062]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][7] + (.C(vid_aclk), + .CE(\time_control_regs_int[25] ), + .D(ipif_data_out[7]), + .Q(genr_regs[1063]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][8] + (.C(vid_aclk), + .CE(\time_control_regs_int[25] ), + .D(ipif_data_out[8]), + .Q(genr_regs[1064]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][9] + (.C(vid_aclk), + .CE(\time_control_regs_int[25] ), + .D(ipif_data_out[9]), + .Q(genr_regs[1065]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][0] + (.C(vid_aclk), + .CE(\time_control_regs_int[26] ), + .D(ipif_data_out[0]), + .Q(\time_control_regs2_int[26] ), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][10] + (.C(vid_aclk), + .CE(\time_control_regs_int[26] ), + .D(ipif_data_out[10]), + .Q(genr_regs[1098]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][11] + (.C(vid_aclk), + .CE(\time_control_regs_int[26] ), + .D(ipif_data_out[11]), + .Q(genr_regs[1099]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][12] + (.C(vid_aclk), + .CE(\time_control_regs_int[26] ), + .D(ipif_data_out[12]), + .Q(genr_regs[1100]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][16] + (.C(vid_aclk), + .CE(\time_control_regs_int[26] ), + .D(ipif_data_out[16]), + .Q(genr_regs[1104]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][17] + (.C(vid_aclk), + .CE(\time_control_regs_int[26] ), + .D(ipif_data_out[17]), + .Q(genr_regs[1105]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][18] + (.C(vid_aclk), + .CE(\time_control_regs_int[26] ), + .D(ipif_data_out[18]), + .Q(genr_regs[1106]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][19] + (.C(vid_aclk), + .CE(\time_control_regs_int[26] ), + .D(ipif_data_out[19]), + .Q(genr_regs[1107]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][1] + (.C(vid_aclk), + .CE(\time_control_regs_int[26] ), + .D(ipif_data_out[1]), + .Q(genr_regs[1089]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][20] + (.C(vid_aclk), + .CE(\time_control_regs_int[26] ), + .D(ipif_data_out[20]), + .Q(genr_regs[1108]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][21] + (.C(vid_aclk), + .CE(\time_control_regs_int[26] ), + .D(ipif_data_out[21]), + .Q(genr_regs[1109]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][22] + (.C(vid_aclk), + .CE(\time_control_regs_int[26] ), + .D(ipif_data_out[22]), + .Q(genr_regs[1110]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][23] + (.C(vid_aclk), + .CE(\time_control_regs_int[26] ), + .D(ipif_data_out[23]), + .Q(genr_regs[1111]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][24] + (.C(vid_aclk), + .CE(\time_control_regs_int[26] ), + .D(ipif_data_out[24]), + .Q(genr_regs[1112]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][25] + (.C(vid_aclk), + .CE(\time_control_regs_int[26] ), + .D(ipif_data_out[25]), + .Q(genr_regs[1113]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][26] + (.C(vid_aclk), + .CE(\time_control_regs_int[26] ), + .D(ipif_data_out[26]), + .Q(genr_regs[1114]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][27] + (.C(vid_aclk), + .CE(\time_control_regs_int[26] ), + .D(ipif_data_out[27]), + .Q(genr_regs[1115]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28] + (.C(vid_aclk), + .CE(\time_control_regs_int[26] ), + .D(ipif_data_out[28]), + .Q(genr_regs[1116]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][2] + (.C(vid_aclk), + .CE(\time_control_regs_int[26] ), + .D(ipif_data_out[2]), + .Q(genr_regs[1090]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][3] + (.C(vid_aclk), + .CE(\time_control_regs_int[26] ), + .D(ipif_data_out[3]), + .Q(genr_regs[1091]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][4] + (.C(vid_aclk), + .CE(\time_control_regs_int[26] ), + .D(ipif_data_out[4]), + .Q(genr_regs[1092]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][5] + (.C(vid_aclk), + .CE(\time_control_regs_int[26] ), + .D(ipif_data_out[5]), + .Q(genr_regs[1093]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][6] + (.C(vid_aclk), + .CE(\time_control_regs_int[26] ), + .D(ipif_data_out[6]), + .Q(genr_regs[1094]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][7] + (.C(vid_aclk), + .CE(\time_control_regs_int[26] ), + .D(ipif_data_out[7]), + .Q(genr_regs[1095]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][8] + (.C(vid_aclk), + .CE(\time_control_regs_int[26] ), + .D(ipif_data_out[8]), + .Q(genr_regs[1096]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][9] + (.C(vid_aclk), + .CE(\time_control_regs_int[26] ), + .D(ipif_data_out[9]), + .Q(genr_regs[1097]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][0] + (.C(vid_aclk), + .CE(\time_control_regs_int[27] ), + .D(ipif_data_out[0]), + .Q(\time_control_regs2_int[27] ), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][10] + (.C(vid_aclk), + .CE(\time_control_regs_int[27] ), + .D(ipif_data_out[10]), + .Q(genr_regs[1130]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][11] + (.C(vid_aclk), + .CE(\time_control_regs_int[27] ), + .D(ipif_data_out[11]), + .Q(genr_regs[1131]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][12] + (.C(vid_aclk), + .CE(\time_control_regs_int[27] ), + .D(ipif_data_out[12]), + .Q(genr_regs[1132]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][16] + (.C(vid_aclk), + .CE(\time_control_regs_int[27] ), + .D(ipif_data_out[16]), + .Q(genr_regs[1136]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][17] + (.C(vid_aclk), + .CE(\time_control_regs_int[27] ), + .D(ipif_data_out[17]), + .Q(genr_regs[1137]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][18] + (.C(vid_aclk), + .CE(\time_control_regs_int[27] ), + .D(ipif_data_out[18]), + .Q(genr_regs[1138]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][19] + (.C(vid_aclk), + .CE(\time_control_regs_int[27] ), + .D(ipif_data_out[19]), + .Q(genr_regs[1139]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][1] + (.C(vid_aclk), + .CE(\time_control_regs_int[27] ), + .D(ipif_data_out[1]), + .Q(genr_regs[1121]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][20] + (.C(vid_aclk), + .CE(\time_control_regs_int[27] ), + .D(ipif_data_out[20]), + .Q(genr_regs[1140]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][21] + (.C(vid_aclk), + .CE(\time_control_regs_int[27] ), + .D(ipif_data_out[21]), + .Q(genr_regs[1141]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][22] + (.C(vid_aclk), + .CE(\time_control_regs_int[27] ), + .D(ipif_data_out[22]), + .Q(genr_regs[1142]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][23] + (.C(vid_aclk), + .CE(\time_control_regs_int[27] ), + .D(ipif_data_out[23]), + .Q(genr_regs[1143]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][24] + (.C(vid_aclk), + .CE(\time_control_regs_int[27] ), + .D(ipif_data_out[24]), + .Q(genr_regs[1144]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][25] + (.C(vid_aclk), + .CE(\time_control_regs_int[27] ), + .D(ipif_data_out[25]), + .Q(genr_regs[1145]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][26] + (.C(vid_aclk), + .CE(\time_control_regs_int[27] ), + .D(ipif_data_out[26]), + .Q(genr_regs[1146]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][27] + (.C(vid_aclk), + .CE(\time_control_regs_int[27] ), + .D(ipif_data_out[27]), + .Q(genr_regs[1147]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][28] + (.C(vid_aclk), + .CE(\time_control_regs_int[27] ), + .D(ipif_data_out[28]), + .Q(genr_regs[1148]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][2] + (.C(vid_aclk), + .CE(\time_control_regs_int[27] ), + .D(ipif_data_out[2]), + .Q(genr_regs[1122]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][3] + (.C(vid_aclk), + .CE(\time_control_regs_int[27] ), + .D(ipif_data_out[3]), + .Q(genr_regs[1123]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][4] + (.C(vid_aclk), + .CE(\time_control_regs_int[27] ), + .D(ipif_data_out[4]), + .Q(genr_regs[1124]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][5] + (.C(vid_aclk), + .CE(\time_control_regs_int[27] ), + .D(ipif_data_out[5]), + .Q(genr_regs[1125]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][6] + (.C(vid_aclk), + .CE(\time_control_regs_int[27] ), + .D(ipif_data_out[6]), + .Q(genr_regs[1126]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][7] + (.C(vid_aclk), + .CE(\time_control_regs_int[27] ), + .D(ipif_data_out[7]), + .Q(genr_regs[1127]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][8] + (.C(vid_aclk), + .CE(\time_control_regs_int[27] ), + .D(ipif_data_out[8]), + .Q(genr_regs[1128]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][9] + (.C(vid_aclk), + .CE(\time_control_regs_int[27] ), + .D(ipif_data_out[9]), + .Q(genr_regs[1129]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][0] + (.C(vid_aclk), + .CE(\time_control_regs_int[28] ), + .D(ipif_data_out[0]), + .Q(\time_control_regs2_int[28] ), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][10] + (.C(vid_aclk), + .CE(\time_control_regs_int[28] ), + .D(ipif_data_out[10]), + .Q(genr_regs[1162]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][11] + (.C(vid_aclk), + .CE(\time_control_regs_int[28] ), + .D(ipif_data_out[11]), + .Q(genr_regs[1163]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][12] + (.C(vid_aclk), + .CE(\time_control_regs_int[28] ), + .D(ipif_data_out[12]), + .Q(genr_regs[1164]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][16] + (.C(vid_aclk), + .CE(\time_control_regs_int[28] ), + .D(ipif_data_out[16]), + .Q(genr_regs[1168]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][17] + (.C(vid_aclk), + .CE(\time_control_regs_int[28] ), + .D(ipif_data_out[17]), + .Q(genr_regs[1169]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][18] + (.C(vid_aclk), + .CE(\time_control_regs_int[28] ), + .D(ipif_data_out[18]), + .Q(genr_regs[1170]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][19] + (.C(vid_aclk), + .CE(\time_control_regs_int[28] ), + .D(ipif_data_out[19]), + .Q(genr_regs[1171]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][1] + (.C(vid_aclk), + .CE(\time_control_regs_int[28] ), + .D(ipif_data_out[1]), + .Q(genr_regs[1153]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][20] + (.C(vid_aclk), + .CE(\time_control_regs_int[28] ), + .D(ipif_data_out[20]), + .Q(genr_regs[1172]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][21] + (.C(vid_aclk), + .CE(\time_control_regs_int[28] ), + .D(ipif_data_out[21]), + .Q(genr_regs[1173]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][22] + (.C(vid_aclk), + .CE(\time_control_regs_int[28] ), + .D(ipif_data_out[22]), + .Q(genr_regs[1174]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][23] + (.C(vid_aclk), + .CE(\time_control_regs_int[28] ), + .D(ipif_data_out[23]), + .Q(genr_regs[1175]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][24] + (.C(vid_aclk), + .CE(\time_control_regs_int[28] ), + .D(ipif_data_out[24]), + .Q(genr_regs[1176]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][25] + (.C(vid_aclk), + .CE(\time_control_regs_int[28] ), + .D(ipif_data_out[25]), + .Q(genr_regs[1177]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][26] + (.C(vid_aclk), + .CE(\time_control_regs_int[28] ), + .D(ipif_data_out[26]), + .Q(genr_regs[1178]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][27] + (.C(vid_aclk), + .CE(\time_control_regs_int[28] ), + .D(ipif_data_out[27]), + .Q(genr_regs[1179]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][28] + (.C(vid_aclk), + .CE(\time_control_regs_int[28] ), + .D(ipif_data_out[28]), + .Q(genr_regs[1180]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][2] + (.C(vid_aclk), + .CE(\time_control_regs_int[28] ), + .D(ipif_data_out[2]), + .Q(genr_regs[1154]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][3] + (.C(vid_aclk), + .CE(\time_control_regs_int[28] ), + .D(ipif_data_out[3]), + .Q(genr_regs[1155]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][4] + (.C(vid_aclk), + .CE(\time_control_regs_int[28] ), + .D(ipif_data_out[4]), + .Q(genr_regs[1156]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][5] + (.C(vid_aclk), + .CE(\time_control_regs_int[28] ), + .D(ipif_data_out[5]), + .Q(genr_regs[1157]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][6] + (.C(vid_aclk), + .CE(\time_control_regs_int[28] ), + .D(ipif_data_out[6]), + .Q(genr_regs[1158]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][7] + (.C(vid_aclk), + .CE(\time_control_regs_int[28] ), + .D(ipif_data_out[7]), + .Q(genr_regs[1159]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDSE #( + .INIT(1'b1)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][8] + (.C(vid_aclk), + .CE(\time_control_regs_int[28] ), + .D(ipif_data_out[8]), + .Q(genr_regs[1160]), + .S(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][9] + (.C(vid_aclk), + .CE(\time_control_regs_int[28] ), + .D(ipif_data_out[9]), + .Q(genr_regs[1161]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.write_ack_d1_reg + (.C(aclk), + .CE(aclk_en), + .D(p_143_out[33]), + .Q(write_ack_d1), + .R(p_0_in_0)); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.write_ack_d2_reg + (.C(aclk), + .CE(aclk_en), + .D(write_ack_d1), + .Q(write_ack_d2), + .R(p_0_in_0)); + LUT1 #( + .INIT(2'h1)) + \AXI4_LITE_INTERFACE.write_ack_e1_i_1 + (.I0(vid_aresetn), + .O(\AXI4_LITE_INTERFACE.write_ack_e1_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.write_ack_e1_reg + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(p_533_out), + .Q(write_ack_e1), + .R(\AXI4_LITE_INTERFACE.write_ack_e1_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.write_ack_e2_reg + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(write_ack_e1), + .Q(write_ack_e2), + .R(\AXI4_LITE_INTERFACE.write_ack_e1_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair269" *) + LUT2 #( + .INIT(4'h8)) + \AXI4_LITE_INTERFACE.write_ack_i_1 + (.I0(write_ack_e1), + .I1(write_ack_e2), + .O(p_534_out)); + (* SOFT_HLUTNM = "soft_lutpair269" *) + LUT3 #( + .INIT(8'h08)) + \AXI4_LITE_INTERFACE.write_ack_int_i_1 + (.I0(write_ack_e2), + .I1(write_ack_e1), + .I2(write_ack), + .O(\AXI4_LITE_INTERFACE.write_ack_int_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.write_ack_int_reg + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\AXI4_LITE_INTERFACE.write_ack_int_i_1_n_0 ), + .Q(write_ack_int), + .R(\AXI4_LITE_INTERFACE.write_ack_e1_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \AXI4_LITE_INTERFACE.write_ack_reg + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(p_534_out), + .Q(write_ack), + .R(\AXI4_LITE_INTERFACE.write_ack_e1_i_1_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_err[0]_i_1 + (.I0(intr_err_set_d[0]), + .I1(\genr_status_regs[2] [0]), + .I2(vid_aclk_en), + .I3(intr_err[0]), + .O(\GEN_HAS_IRQ.intr_err[0]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_err[10]_i_1 + (.I0(intr_err_set_d[10]), + .I1(\genr_status_regs[2] [10]), + .I2(vid_aclk_en), + .I3(intr_err[10]), + .O(\GEN_HAS_IRQ.intr_err[10]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_err[11]_i_1 + (.I0(intr_err_set_d[11]), + .I1(\genr_status_regs[2] [11]), + .I2(vid_aclk_en), + .I3(intr_err[11]), + .O(\GEN_HAS_IRQ.intr_err[11]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_err[12]_i_1 + (.I0(intr_err_set_d[12]), + .I1(\genr_status_regs[2] [12]), + .I2(vid_aclk_en), + .I3(intr_err[12]), + .O(\GEN_HAS_IRQ.intr_err[12]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_err[13]_i_1 + (.I0(intr_err_set_d[13]), + .I1(\genr_status_regs[2] [13]), + .I2(vid_aclk_en), + .I3(intr_err[13]), + .O(\GEN_HAS_IRQ.intr_err[13]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_err[14]_i_1 + (.I0(intr_err_set_d[14]), + .I1(\genr_status_regs[2] [14]), + .I2(vid_aclk_en), + .I3(intr_err[14]), + .O(\GEN_HAS_IRQ.intr_err[14]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_err[15]_i_1 + (.I0(intr_err_set_d[15]), + .I1(\genr_status_regs[2] [15]), + .I2(vid_aclk_en), + .I3(intr_err[15]), + .O(\GEN_HAS_IRQ.intr_err[15]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBA00AA000000AA00)) + \GEN_HAS_IRQ.intr_err[16]_i_1 + (.I0(intr_err[16]), + .I1(intr_err_set_d[16]), + .I2(\genr_status_regs[2] [16]), + .I3(resetn_out), + .I4(vid_aclk_en), + .I5(\GEN_HAS_IRQ.intr_err[16]_i_2_n_0 ), + .O(\GEN_HAS_IRQ.intr_err[16]_i_1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \GEN_HAS_IRQ.intr_err[16]_i_2 + (.I0(intr_err_clr_d[16]), + .I1(\^genr_control_regs[2] [16]), + .O(\GEN_HAS_IRQ.intr_err[16]_i_2_n_0 )); + LUT6 #( + .INIT(64'hBA00AA000000AA00)) + \GEN_HAS_IRQ.intr_err[17]_i_1 + (.I0(intr_err[17]), + .I1(intr_err_set_d[17]), + .I2(\genr_status_regs[2] [17]), + .I3(resetn_out), + .I4(vid_aclk_en), + .I5(\GEN_HAS_IRQ.intr_err[17]_i_2_n_0 ), + .O(\GEN_HAS_IRQ.intr_err[17]_i_1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \GEN_HAS_IRQ.intr_err[17]_i_2 + (.I0(intr_err_clr_d[17]), + .I1(\^genr_control_regs[2] [17]), + .O(\GEN_HAS_IRQ.intr_err[17]_i_2_n_0 )); + LUT6 #( + .INIT(64'hBA00AA000000AA00)) + \GEN_HAS_IRQ.intr_err[18]_i_1 + (.I0(intr_err[18]), + .I1(intr_err_set_d[18]), + .I2(\genr_status_regs[2] [18]), + .I3(resetn_out), + .I4(vid_aclk_en), + .I5(\GEN_HAS_IRQ.intr_err[18]_i_2_n_0 ), + .O(\GEN_HAS_IRQ.intr_err[18]_i_1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \GEN_HAS_IRQ.intr_err[18]_i_2 + (.I0(intr_err_clr_d[18]), + .I1(\^genr_control_regs[2] [18]), + .O(\GEN_HAS_IRQ.intr_err[18]_i_2_n_0 )); + LUT6 #( + .INIT(64'hBA00AA000000AA00)) + \GEN_HAS_IRQ.intr_err[19]_i_1 + (.I0(intr_err[19]), + .I1(intr_err_set_d[19]), + .I2(\genr_status_regs[2] [19]), + .I3(resetn_out), + .I4(vid_aclk_en), + .I5(\GEN_HAS_IRQ.intr_err[19]_i_2_n_0 ), + .O(\GEN_HAS_IRQ.intr_err[19]_i_1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \GEN_HAS_IRQ.intr_err[19]_i_2 + (.I0(intr_err_clr_d[19]), + .I1(\^genr_control_regs[2] [19]), + .O(\GEN_HAS_IRQ.intr_err[19]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_err[1]_i_1 + (.I0(intr_err_set_d[1]), + .I1(\genr_status_regs[2] [1]), + .I2(vid_aclk_en), + .I3(intr_err[1]), + .O(\GEN_HAS_IRQ.intr_err[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBA00AA000000AA00)) + \GEN_HAS_IRQ.intr_err[20]_i_1 + (.I0(intr_err[20]), + .I1(intr_err_set_d[20]), + .I2(\genr_status_regs[2] [20]), + .I3(resetn_out), + .I4(vid_aclk_en), + .I5(\GEN_HAS_IRQ.intr_err[20]_i_2_n_0 ), + .O(\GEN_HAS_IRQ.intr_err[20]_i_1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \GEN_HAS_IRQ.intr_err[20]_i_2 + (.I0(intr_err_clr_d[20]), + .I1(\^genr_control_regs[2] [20]), + .O(\GEN_HAS_IRQ.intr_err[20]_i_2_n_0 )); + LUT6 #( + .INIT(64'hBA00AA000000AA00)) + \GEN_HAS_IRQ.intr_err[21]_i_1 + (.I0(intr_err[21]), + .I1(intr_err_set_d[21]), + .I2(\genr_status_regs[2] [21]), + .I3(resetn_out), + .I4(vid_aclk_en), + .I5(\GEN_HAS_IRQ.intr_err[21]_i_2_n_0 ), + .O(\GEN_HAS_IRQ.intr_err[21]_i_1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \GEN_HAS_IRQ.intr_err[21]_i_2 + (.I0(intr_err_clr_d[21]), + .I1(\^genr_control_regs[2] [21]), + .O(\GEN_HAS_IRQ.intr_err[21]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_err[22]_i_1 + (.I0(intr_err_set_d[22]), + .I1(\genr_status_regs[2] [22]), + .I2(vid_aclk_en), + .I3(intr_err[22]), + .O(\GEN_HAS_IRQ.intr_err[22]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_err[23]_i_1 + (.I0(intr_err_set_d[23]), + .I1(\genr_status_regs[2] [23]), + .I2(vid_aclk_en), + .I3(intr_err[23]), + .O(\GEN_HAS_IRQ.intr_err[23]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_err[24]_i_1 + (.I0(intr_err_set_d[24]), + .I1(\genr_status_regs[2] [24]), + .I2(vid_aclk_en), + .I3(intr_err[24]), + .O(\GEN_HAS_IRQ.intr_err[24]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_err[25]_i_1 + (.I0(intr_err_set_d[25]), + .I1(\genr_status_regs[2] [25]), + .I2(vid_aclk_en), + .I3(intr_err[25]), + .O(\GEN_HAS_IRQ.intr_err[25]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_err[26]_i_1 + (.I0(intr_err_set_d[26]), + .I1(\genr_status_regs[2] [26]), + .I2(vid_aclk_en), + .I3(intr_err[26]), + .O(\GEN_HAS_IRQ.intr_err[26]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_err[27]_i_1 + (.I0(intr_err_set_d[27]), + .I1(\genr_status_regs[2] [27]), + .I2(vid_aclk_en), + .I3(intr_err[27]), + .O(\GEN_HAS_IRQ.intr_err[27]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_err[28]_i_1 + (.I0(intr_err_set_d[28]), + .I1(\genr_status_regs[2] [28]), + .I2(vid_aclk_en), + .I3(intr_err[28]), + .O(\GEN_HAS_IRQ.intr_err[28]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_err[29]_i_1 + (.I0(intr_err_set_d[29]), + .I1(\genr_status_regs[2] [29]), + .I2(vid_aclk_en), + .I3(intr_err[29]), + .O(\GEN_HAS_IRQ.intr_err[29]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_err[2]_i_1 + (.I0(intr_err_set_d[2]), + .I1(\genr_status_regs[2] [2]), + .I2(vid_aclk_en), + .I3(intr_err[2]), + .O(\GEN_HAS_IRQ.intr_err[2]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_err[30]_i_1 + (.I0(intr_err_set_d[30]), + .I1(\genr_status_regs[2] [30]), + .I2(vid_aclk_en), + .I3(intr_err[30]), + .O(\GEN_HAS_IRQ.intr_err[30]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_err[31]_i_1 + (.I0(intr_err_set_d[31]), + .I1(\genr_status_regs[2] [31]), + .I2(vid_aclk_en), + .I3(intr_err[31]), + .O(\GEN_HAS_IRQ.intr_err[31]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_err[3]_i_1 + (.I0(intr_err_set_d[3]), + .I1(\genr_status_regs[2] [3]), + .I2(vid_aclk_en), + .I3(intr_err[3]), + .O(\GEN_HAS_IRQ.intr_err[3]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_err[4]_i_1 + (.I0(intr_err_set_d[4]), + .I1(\genr_status_regs[2] [4]), + .I2(vid_aclk_en), + .I3(intr_err[4]), + .O(\GEN_HAS_IRQ.intr_err[4]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_err[5]_i_1 + (.I0(intr_err_set_d[5]), + .I1(\genr_status_regs[2] [5]), + .I2(vid_aclk_en), + .I3(intr_err[5]), + .O(\GEN_HAS_IRQ.intr_err[5]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_err[6]_i_1 + (.I0(intr_err_set_d[6]), + .I1(\genr_status_regs[2] [6]), + .I2(vid_aclk_en), + .I3(intr_err[6]), + .O(\GEN_HAS_IRQ.intr_err[6]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_err[7]_i_1 + (.I0(intr_err_set_d[7]), + .I1(\genr_status_regs[2] [7]), + .I2(vid_aclk_en), + .I3(intr_err[7]), + .O(\GEN_HAS_IRQ.intr_err[7]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_err[8]_i_1 + (.I0(intr_err_set_d[8]), + .I1(\genr_status_regs[2] [8]), + .I2(vid_aclk_en), + .I3(intr_err[8]), + .O(\GEN_HAS_IRQ.intr_err[8]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_err[9]_i_1 + (.I0(intr_err_set_d[9]), + .I1(\genr_status_regs[2] [9]), + .I2(vid_aclk_en), + .I3(intr_err[9]), + .O(\GEN_HAS_IRQ.intr_err[9]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_clr_d_reg[16] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\^genr_control_regs[2] [16]), + .Q(intr_err_clr_d[16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_clr_d_reg[17] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\^genr_control_regs[2] [17]), + .Q(intr_err_clr_d[17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_clr_d_reg[18] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\^genr_control_regs[2] [18]), + .Q(intr_err_clr_d[18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_clr_d_reg[19] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\^genr_control_regs[2] [19]), + .Q(intr_err_clr_d[19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_clr_d_reg[20] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\^genr_control_regs[2] [20]), + .Q(intr_err_clr_d[20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_clr_d_reg[21] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\^genr_control_regs[2] [21]), + .Q(intr_err_clr_d[21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[0] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[0]_i_1_n_0 ), + .Q(intr_err[0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[10] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[10]_i_1_n_0 ), + .Q(intr_err[10]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[11] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[11]_i_1_n_0 ), + .Q(intr_err[11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[12] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[12]_i_1_n_0 ), + .Q(intr_err[12]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[13] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[13]_i_1_n_0 ), + .Q(intr_err[13]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[14] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[14]_i_1_n_0 ), + .Q(intr_err[14]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[15] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[15]_i_1_n_0 ), + .Q(intr_err[15]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[16] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[16]_i_1_n_0 ), + .Q(intr_err[16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[17] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[17]_i_1_n_0 ), + .Q(intr_err[17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[18] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[18]_i_1_n_0 ), + .Q(intr_err[18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[19] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[19]_i_1_n_0 ), + .Q(intr_err[19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[1] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[1]_i_1_n_0 ), + .Q(intr_err[1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[20] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[20]_i_1_n_0 ), + .Q(intr_err[20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[21] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[21]_i_1_n_0 ), + .Q(intr_err[21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[22] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[22]_i_1_n_0 ), + .Q(intr_err[22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[23] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[23]_i_1_n_0 ), + .Q(intr_err[23]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[24] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[24]_i_1_n_0 ), + .Q(intr_err[24]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[25] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[25]_i_1_n_0 ), + .Q(intr_err[25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[26] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[26]_i_1_n_0 ), + .Q(intr_err[26]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[27] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[27]_i_1_n_0 ), + .Q(intr_err[27]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[28] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[28]_i_1_n_0 ), + .Q(intr_err[28]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[29] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[29]_i_1_n_0 ), + .Q(intr_err[29]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[2] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[2]_i_1_n_0 ), + .Q(intr_err[2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[30] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[30]_i_1_n_0 ), + .Q(intr_err[30]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[31] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[31]_i_1_n_0 ), + .Q(intr_err[31]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[3] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[3]_i_1_n_0 ), + .Q(intr_err[3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[4] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[4]_i_1_n_0 ), + .Q(intr_err[4]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[5] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[5]_i_1_n_0 ), + .Q(intr_err[5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[6] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[6]_i_1_n_0 ), + .Q(intr_err[6]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[7] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[7]_i_1_n_0 ), + .Q(intr_err[7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[8] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[8]_i_1_n_0 ), + .Q(intr_err[8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_reg[9] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_err[9]_i_1_n_0 ), + .Q(intr_err[9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[0] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [0]), + .Q(intr_err_set_d[0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[10] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [10]), + .Q(intr_err_set_d[10]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[11] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [11]), + .Q(intr_err_set_d[11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[12] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [12]), + .Q(intr_err_set_d[12]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[13] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [13]), + .Q(intr_err_set_d[13]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[14] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [14]), + .Q(intr_err_set_d[14]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[15] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [15]), + .Q(intr_err_set_d[15]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[16] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [16]), + .Q(intr_err_set_d[16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[17] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [17]), + .Q(intr_err_set_d[17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[18] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [18]), + .Q(intr_err_set_d[18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[19] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [19]), + .Q(intr_err_set_d[19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[1] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [1]), + .Q(intr_err_set_d[1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[20] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [20]), + .Q(intr_err_set_d[20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[21] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [21]), + .Q(intr_err_set_d[21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[22] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [22]), + .Q(intr_err_set_d[22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[23] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [23]), + .Q(intr_err_set_d[23]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[24] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [24]), + .Q(intr_err_set_d[24]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[25] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [25]), + .Q(intr_err_set_d[25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[26] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [26]), + .Q(intr_err_set_d[26]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[27] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [27]), + .Q(intr_err_set_d[27]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[28] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [28]), + .Q(intr_err_set_d[28]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[29] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [29]), + .Q(intr_err_set_d[29]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[2] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [2]), + .Q(intr_err_set_d[2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[30] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [30]), + .Q(intr_err_set_d[30]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[31] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [31]), + .Q(intr_err_set_d[31]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[3] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [3]), + .Q(intr_err_set_d[3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[4] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [4]), + .Q(intr_err_set_d[4]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[5] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [5]), + .Q(intr_err_set_d[5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[6] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [6]), + .Q(intr_err_set_d[6]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[7] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [7]), + .Q(intr_err_set_d[7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[8] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [8]), + .Q(intr_err_set_d[8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_err_set_d_reg[9] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[2] [9]), + .Q(intr_err_set_d[9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_stat[0]_i_1 + (.I0(intr_stat_set_d[0]), + .I1(\genr_status_regs[1] [0]), + .I2(vid_aclk_en), + .I3(\genr_status_regs_int_reg[1] [0]), + .O(\GEN_HAS_IRQ.intr_stat[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBA00AA000000AA00)) + \GEN_HAS_IRQ.intr_stat[10]_i_1 + (.I0(\genr_status_regs_int_reg[1] [10]), + .I1(intr_stat_set_d[10]), + .I2(\genr_status_regs[1] [10]), + .I3(resetn_out), + .I4(vid_aclk_en), + .I5(\GEN_HAS_IRQ.intr_stat[10]_i_2_n_0 ), + .O(\GEN_HAS_IRQ.intr_stat[10]_i_1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \GEN_HAS_IRQ.intr_stat[10]_i_2 + (.I0(intr_stat_clr_d[10]), + .I1(\^genr_control_regs[1] [10]), + .O(\GEN_HAS_IRQ.intr_stat[10]_i_2_n_0 )); + LUT6 #( + .INIT(64'hBA00AA000000AA00)) + \GEN_HAS_IRQ.intr_stat[11]_i_1 + (.I0(\genr_status_regs_int_reg[1] [11]), + .I1(intr_stat_set_d[11]), + .I2(\genr_status_regs[1] [11]), + .I3(resetn_out), + .I4(vid_aclk_en), + .I5(\GEN_HAS_IRQ.intr_stat[11]_i_2_n_0 ), + .O(\GEN_HAS_IRQ.intr_stat[11]_i_1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \GEN_HAS_IRQ.intr_stat[11]_i_2 + (.I0(intr_stat_clr_d[11]), + .I1(\^genr_control_regs[1] [11]), + .O(\GEN_HAS_IRQ.intr_stat[11]_i_2_n_0 )); + LUT6 #( + .INIT(64'hBA00AA000000AA00)) + \GEN_HAS_IRQ.intr_stat[12]_i_1 + (.I0(\genr_status_regs_int_reg[1] [12]), + .I1(intr_stat_set_d[12]), + .I2(\genr_status_regs[1] [12]), + .I3(resetn_out), + .I4(vid_aclk_en), + .I5(\GEN_HAS_IRQ.intr_stat[12]_i_2_n_0 ), + .O(\GEN_HAS_IRQ.intr_stat[12]_i_1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \GEN_HAS_IRQ.intr_stat[12]_i_2 + (.I0(intr_stat_clr_d[12]), + .I1(\^genr_control_regs[1] [12]), + .O(\GEN_HAS_IRQ.intr_stat[12]_i_2_n_0 )); + LUT6 #( + .INIT(64'hBA00AA000000AA00)) + \GEN_HAS_IRQ.intr_stat[13]_i_1 + (.I0(\genr_status_regs_int_reg[1] [13]), + .I1(intr_stat_set_d[13]), + .I2(\genr_status_regs[1] [13]), + .I3(resetn_out), + .I4(vid_aclk_en), + .I5(\GEN_HAS_IRQ.intr_stat[13]_i_2_n_0 ), + .O(\GEN_HAS_IRQ.intr_stat[13]_i_1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \GEN_HAS_IRQ.intr_stat[13]_i_2 + (.I0(intr_stat_clr_d[13]), + .I1(\^genr_control_regs[1] [13]), + .O(\GEN_HAS_IRQ.intr_stat[13]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_stat[14]_i_1 + (.I0(intr_stat_set_d[14]), + .I1(\genr_status_regs[1] [14]), + .I2(vid_aclk_en), + .I3(\genr_status_regs_int_reg[1] [14]), + .O(\GEN_HAS_IRQ.intr_stat[14]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_stat[15]_i_1 + (.I0(intr_stat_set_d[15]), + .I1(\genr_status_regs[1] [15]), + .I2(vid_aclk_en), + .I3(\genr_status_regs_int_reg[1] [15]), + .O(\GEN_HAS_IRQ.intr_stat[15]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBA00AA000000AA00)) + \GEN_HAS_IRQ.intr_stat[16]_i_1 + (.I0(\genr_status_regs_int_reg[1] [16]), + .I1(intr_stat_set_d[16]), + .I2(\genr_status_regs[1] [16]), + .I3(resetn_out), + .I4(vid_aclk_en), + .I5(\GEN_HAS_IRQ.intr_stat[16]_i_2_n_0 ), + .O(\GEN_HAS_IRQ.intr_stat[16]_i_1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \GEN_HAS_IRQ.intr_stat[16]_i_2 + (.I0(intr_stat_clr_d[16]), + .I1(\^genr_control_regs[1] [16]), + .O(\GEN_HAS_IRQ.intr_stat[16]_i_2_n_0 )); + LUT6 #( + .INIT(64'hBA00AA000000AA00)) + \GEN_HAS_IRQ.intr_stat[17]_i_1 + (.I0(\genr_status_regs_int_reg[1] [17]), + .I1(intr_stat_set_d[17]), + .I2(\genr_status_regs[1] [17]), + .I3(resetn_out), + .I4(vid_aclk_en), + .I5(\GEN_HAS_IRQ.intr_stat[17]_i_2_n_0 ), + .O(\GEN_HAS_IRQ.intr_stat[17]_i_1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \GEN_HAS_IRQ.intr_stat[17]_i_2 + (.I0(intr_stat_clr_d[17]), + .I1(\^genr_control_regs[1] [17]), + .O(\GEN_HAS_IRQ.intr_stat[17]_i_2_n_0 )); + LUT6 #( + .INIT(64'hBA00AA000000AA00)) + \GEN_HAS_IRQ.intr_stat[18]_i_1 + (.I0(\genr_status_regs_int_reg[1] [18]), + .I1(intr_stat_set_d[18]), + .I2(\genr_status_regs[1] [18]), + .I3(resetn_out), + .I4(vid_aclk_en), + .I5(\GEN_HAS_IRQ.intr_stat[18]_i_2_n_0 ), + .O(\GEN_HAS_IRQ.intr_stat[18]_i_1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \GEN_HAS_IRQ.intr_stat[18]_i_2 + (.I0(intr_stat_clr_d[18]), + .I1(\^genr_control_regs[1] [18]), + .O(\GEN_HAS_IRQ.intr_stat[18]_i_2_n_0 )); + LUT6 #( + .INIT(64'hBA00AA000000AA00)) + \GEN_HAS_IRQ.intr_stat[19]_i_1 + (.I0(\genr_status_regs_int_reg[1] [19]), + .I1(intr_stat_set_d[19]), + .I2(\genr_status_regs[1] [19]), + .I3(resetn_out), + .I4(vid_aclk_en), + .I5(\GEN_HAS_IRQ.intr_stat[19]_i_2_n_0 ), + .O(\GEN_HAS_IRQ.intr_stat[19]_i_1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \GEN_HAS_IRQ.intr_stat[19]_i_2 + (.I0(intr_stat_clr_d[19]), + .I1(\^genr_control_regs[1] [19]), + .O(\GEN_HAS_IRQ.intr_stat[19]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_stat[1]_i_1 + (.I0(intr_stat_set_d[1]), + .I1(\genr_status_regs[1] [1]), + .I2(vid_aclk_en), + .I3(\genr_status_regs_int_reg[1] [1]), + .O(\GEN_HAS_IRQ.intr_stat[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBA00AA000000AA00)) + \GEN_HAS_IRQ.intr_stat[20]_i_1 + (.I0(\genr_status_regs_int_reg[1] [20]), + .I1(intr_stat_set_d[20]), + .I2(\genr_status_regs[1] [20]), + .I3(resetn_out), + .I4(vid_aclk_en), + .I5(\GEN_HAS_IRQ.intr_stat[20]_i_2_n_0 ), + .O(\GEN_HAS_IRQ.intr_stat[20]_i_1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \GEN_HAS_IRQ.intr_stat[20]_i_2 + (.I0(intr_stat_clr_d[20]), + .I1(\^genr_control_regs[1] [20]), + .O(\GEN_HAS_IRQ.intr_stat[20]_i_2_n_0 )); + LUT6 #( + .INIT(64'hBA00AA000000AA00)) + \GEN_HAS_IRQ.intr_stat[21]_i_1 + (.I0(\genr_status_regs_int_reg[1] [21]), + .I1(intr_stat_set_d[21]), + .I2(\genr_status_regs[1] [21]), + .I3(resetn_out), + .I4(vid_aclk_en), + .I5(\GEN_HAS_IRQ.intr_stat[21]_i_2_n_0 ), + .O(\GEN_HAS_IRQ.intr_stat[21]_i_1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \GEN_HAS_IRQ.intr_stat[21]_i_2 + (.I0(intr_stat_clr_d[21]), + .I1(\^genr_control_regs[1] [21]), + .O(\GEN_HAS_IRQ.intr_stat[21]_i_2_n_0 )); + LUT6 #( + .INIT(64'hBA00AA000000AA00)) + \GEN_HAS_IRQ.intr_stat[22]_i_1 + (.I0(\genr_status_regs_int_reg[1] [22]), + .I1(intr_stat_set_d[22]), + .I2(\genr_status_regs[1] [22]), + .I3(resetn_out), + .I4(vid_aclk_en), + .I5(\GEN_HAS_IRQ.intr_stat[22]_i_2_n_0 ), + .O(\GEN_HAS_IRQ.intr_stat[22]_i_1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \GEN_HAS_IRQ.intr_stat[22]_i_2 + (.I0(intr_stat_clr_d[22]), + .I1(\^genr_control_regs[1] [22]), + .O(\GEN_HAS_IRQ.intr_stat[22]_i_2_n_0 )); + LUT6 #( + .INIT(64'hBA00AA000000AA00)) + \GEN_HAS_IRQ.intr_stat[23]_i_1 + (.I0(\genr_status_regs_int_reg[1] [23]), + .I1(intr_stat_set_d[23]), + .I2(\genr_status_regs[1] [23]), + .I3(resetn_out), + .I4(vid_aclk_en), + .I5(\GEN_HAS_IRQ.intr_stat[23]_i_2_n_0 ), + .O(\GEN_HAS_IRQ.intr_stat[23]_i_1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \GEN_HAS_IRQ.intr_stat[23]_i_2 + (.I0(intr_stat_clr_d[23]), + .I1(\^genr_control_regs[1] [23]), + .O(\GEN_HAS_IRQ.intr_stat[23]_i_2_n_0 )); + LUT6 #( + .INIT(64'hBA00AA000000AA00)) + \GEN_HAS_IRQ.intr_stat[24]_i_1 + (.I0(\genr_status_regs_int_reg[1] [24]), + .I1(intr_stat_set_d[24]), + .I2(\genr_status_regs[1] [24]), + .I3(resetn_out), + .I4(vid_aclk_en), + .I5(\GEN_HAS_IRQ.intr_stat[24]_i_2_n_0 ), + .O(\GEN_HAS_IRQ.intr_stat[24]_i_1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \GEN_HAS_IRQ.intr_stat[24]_i_2 + (.I0(intr_stat_clr_d[24]), + .I1(\^genr_control_regs[1] [24]), + .O(\GEN_HAS_IRQ.intr_stat[24]_i_2_n_0 )); + LUT6 #( + .INIT(64'hBA00AA000000AA00)) + \GEN_HAS_IRQ.intr_stat[25]_i_1 + (.I0(\genr_status_regs_int_reg[1] [25]), + .I1(intr_stat_set_d[25]), + .I2(\genr_status_regs[1] [25]), + .I3(resetn_out), + .I4(vid_aclk_en), + .I5(\GEN_HAS_IRQ.intr_stat[25]_i_2_n_0 ), + .O(\GEN_HAS_IRQ.intr_stat[25]_i_1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \GEN_HAS_IRQ.intr_stat[25]_i_2 + (.I0(intr_stat_clr_d[25]), + .I1(\^genr_control_regs[1] [25]), + .O(\GEN_HAS_IRQ.intr_stat[25]_i_2_n_0 )); + LUT6 #( + .INIT(64'hBA00AA000000AA00)) + \GEN_HAS_IRQ.intr_stat[26]_i_1 + (.I0(\genr_status_regs_int_reg[1] [26]), + .I1(intr_stat_set_d[26]), + .I2(\genr_status_regs[1] [26]), + .I3(resetn_out), + .I4(vid_aclk_en), + .I5(\GEN_HAS_IRQ.intr_stat[26]_i_2_n_0 ), + .O(\GEN_HAS_IRQ.intr_stat[26]_i_1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \GEN_HAS_IRQ.intr_stat[26]_i_2 + (.I0(intr_stat_clr_d[26]), + .I1(\^genr_control_regs[1] [26]), + .O(\GEN_HAS_IRQ.intr_stat[26]_i_2_n_0 )); + LUT6 #( + .INIT(64'hBA00AA000000AA00)) + \GEN_HAS_IRQ.intr_stat[27]_i_1 + (.I0(\genr_status_regs_int_reg[1] [27]), + .I1(intr_stat_set_d[27]), + .I2(\genr_status_regs[1] [27]), + .I3(resetn_out), + .I4(vid_aclk_en), + .I5(\GEN_HAS_IRQ.intr_stat[27]_i_2_n_0 ), + .O(\GEN_HAS_IRQ.intr_stat[27]_i_1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \GEN_HAS_IRQ.intr_stat[27]_i_2 + (.I0(intr_stat_clr_d[27]), + .I1(\^genr_control_regs[1] [27]), + .O(\GEN_HAS_IRQ.intr_stat[27]_i_2_n_0 )); + LUT6 #( + .INIT(64'hBA00AA000000AA00)) + \GEN_HAS_IRQ.intr_stat[28]_i_1 + (.I0(\genr_status_regs_int_reg[1] [28]), + .I1(intr_stat_set_d[28]), + .I2(\genr_status_regs[1] [28]), + .I3(resetn_out), + .I4(vid_aclk_en), + .I5(\GEN_HAS_IRQ.intr_stat[28]_i_2_n_0 ), + .O(\GEN_HAS_IRQ.intr_stat[28]_i_1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \GEN_HAS_IRQ.intr_stat[28]_i_2 + (.I0(intr_stat_clr_d[28]), + .I1(\^genr_control_regs[1] [28]), + .O(\GEN_HAS_IRQ.intr_stat[28]_i_2_n_0 )); + LUT6 #( + .INIT(64'hBA00AA000000AA00)) + \GEN_HAS_IRQ.intr_stat[29]_i_1 + (.I0(\genr_status_regs_int_reg[1] [29]), + .I1(intr_stat_set_d[29]), + .I2(\genr_status_regs[1] [29]), + .I3(resetn_out), + .I4(vid_aclk_en), + .I5(\GEN_HAS_IRQ.intr_stat[29]_i_2_n_0 ), + .O(\GEN_HAS_IRQ.intr_stat[29]_i_1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \GEN_HAS_IRQ.intr_stat[29]_i_2 + (.I0(intr_stat_clr_d[29]), + .I1(\^genr_control_regs[1] [29]), + .O(\GEN_HAS_IRQ.intr_stat[29]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_stat[2]_i_1 + (.I0(intr_stat_set_d[2]), + .I1(\genr_status_regs[1] [2]), + .I2(vid_aclk_en), + .I3(\genr_status_regs_int_reg[1] [2]), + .O(\GEN_HAS_IRQ.intr_stat[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBA00AA000000AA00)) + \GEN_HAS_IRQ.intr_stat[30]_i_1 + (.I0(\genr_status_regs_int_reg[1] [30]), + .I1(intr_stat_set_d[30]), + .I2(\genr_status_regs[1] [30]), + .I3(resetn_out), + .I4(vid_aclk_en), + .I5(\GEN_HAS_IRQ.intr_stat[30]_i_2_n_0 ), + .O(\GEN_HAS_IRQ.intr_stat[30]_i_1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \GEN_HAS_IRQ.intr_stat[30]_i_2 + (.I0(intr_stat_clr_d[30]), + .I1(\^genr_control_regs[1] [30]), + .O(\GEN_HAS_IRQ.intr_stat[30]_i_2_n_0 )); + LUT6 #( + .INIT(64'hBA00AA000000AA00)) + \GEN_HAS_IRQ.intr_stat[31]_i_1 + (.I0(\GEN_HAS_IRQ.intr_stat_reg_n_0_[31] ), + .I1(intr_stat_set_d[31]), + .I2(\genr_status_regs[1] [31]), + .I3(resetn_out), + .I4(vid_aclk_en), + .I5(\GEN_HAS_IRQ.intr_stat[31]_i_2_n_0 ), + .O(\GEN_HAS_IRQ.intr_stat[31]_i_1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \GEN_HAS_IRQ.intr_stat[31]_i_2 + (.I0(intr_stat_clr_d[31]), + .I1(\^genr_control_regs[1] [31]), + .O(\GEN_HAS_IRQ.intr_stat[31]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_stat[3]_i_1 + (.I0(intr_stat_set_d[3]), + .I1(\genr_status_regs[1] [3]), + .I2(vid_aclk_en), + .I3(\genr_status_regs_int_reg[1] [3]), + .O(\GEN_HAS_IRQ.intr_stat[3]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_stat[4]_i_1 + (.I0(intr_stat_set_d[4]), + .I1(\genr_status_regs[1] [4]), + .I2(vid_aclk_en), + .I3(\genr_status_regs_int_reg[1] [4]), + .O(\GEN_HAS_IRQ.intr_stat[4]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_stat[5]_i_1 + (.I0(intr_stat_set_d[5]), + .I1(\genr_status_regs[1] [5]), + .I2(vid_aclk_en), + .I3(\genr_status_regs_int_reg[1] [5]), + .O(\GEN_HAS_IRQ.intr_stat[5]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_stat[6]_i_1 + (.I0(intr_stat_set_d[6]), + .I1(\genr_status_regs[1] [6]), + .I2(vid_aclk_en), + .I3(\genr_status_regs_int_reg[1] [6]), + .O(\GEN_HAS_IRQ.intr_stat[6]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFF40)) + \GEN_HAS_IRQ.intr_stat[7]_i_1 + (.I0(intr_stat_set_d[7]), + .I1(\genr_status_regs[1] [7]), + .I2(vid_aclk_en), + .I3(\genr_status_regs_int_reg[1] [7]), + .O(\GEN_HAS_IRQ.intr_stat[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBA00AA000000AA00)) + \GEN_HAS_IRQ.intr_stat[8]_i_1 + (.I0(\genr_status_regs_int_reg[1] [8]), + .I1(intr_stat_set_d[8]), + .I2(\genr_status_regs[1] [8]), + .I3(resetn_out), + .I4(vid_aclk_en), + .I5(\GEN_HAS_IRQ.intr_stat[8]_i_2_n_0 ), + .O(\GEN_HAS_IRQ.intr_stat[8]_i_1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \GEN_HAS_IRQ.intr_stat[8]_i_2 + (.I0(intr_stat_clr_d[8]), + .I1(\^genr_control_regs[1] [8]), + .O(\GEN_HAS_IRQ.intr_stat[8]_i_2_n_0 )); + LUT6 #( + .INIT(64'hBA00AA000000AA00)) + \GEN_HAS_IRQ.intr_stat[9]_i_1 + (.I0(\genr_status_regs_int_reg[1] [9]), + .I1(intr_stat_set_d[9]), + .I2(\genr_status_regs[1] [9]), + .I3(resetn_out), + .I4(vid_aclk_en), + .I5(\GEN_HAS_IRQ.intr_stat[9]_i_2_n_0 ), + .O(\GEN_HAS_IRQ.intr_stat[9]_i_1_n_0 )); + LUT2 #( + .INIT(4'hB)) + \GEN_HAS_IRQ.intr_stat[9]_i_2 + (.I0(intr_stat_clr_d[9]), + .I1(\^genr_control_regs[1] [9]), + .O(\GEN_HAS_IRQ.intr_stat[9]_i_2_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_clr_d_reg[10] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\^genr_control_regs[1] [10]), + .Q(intr_stat_clr_d[10]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_clr_d_reg[11] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\^genr_control_regs[1] [11]), + .Q(intr_stat_clr_d[11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_clr_d_reg[12] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\^genr_control_regs[1] [12]), + .Q(intr_stat_clr_d[12]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_clr_d_reg[13] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\^genr_control_regs[1] [13]), + .Q(intr_stat_clr_d[13]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_clr_d_reg[16] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\^genr_control_regs[1] [16]), + .Q(intr_stat_clr_d[16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_clr_d_reg[17] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\^genr_control_regs[1] [17]), + .Q(intr_stat_clr_d[17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_clr_d_reg[18] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\^genr_control_regs[1] [18]), + .Q(intr_stat_clr_d[18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_clr_d_reg[19] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\^genr_control_regs[1] [19]), + .Q(intr_stat_clr_d[19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_clr_d_reg[20] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\^genr_control_regs[1] [20]), + .Q(intr_stat_clr_d[20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_clr_d_reg[21] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\^genr_control_regs[1] [21]), + .Q(intr_stat_clr_d[21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_clr_d_reg[22] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\^genr_control_regs[1] [22]), + .Q(intr_stat_clr_d[22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_clr_d_reg[23] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\^genr_control_regs[1] [23]), + .Q(intr_stat_clr_d[23]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_clr_d_reg[24] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\^genr_control_regs[1] [24]), + .Q(intr_stat_clr_d[24]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_clr_d_reg[25] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\^genr_control_regs[1] [25]), + .Q(intr_stat_clr_d[25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_clr_d_reg[26] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\^genr_control_regs[1] [26]), + .Q(intr_stat_clr_d[26]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_clr_d_reg[27] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\^genr_control_regs[1] [27]), + .Q(intr_stat_clr_d[27]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_clr_d_reg[28] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\^genr_control_regs[1] [28]), + .Q(intr_stat_clr_d[28]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_clr_d_reg[29] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\^genr_control_regs[1] [29]), + .Q(intr_stat_clr_d[29]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_clr_d_reg[30] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\^genr_control_regs[1] [30]), + .Q(intr_stat_clr_d[30]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_clr_d_reg[31] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\^genr_control_regs[1] [31]), + .Q(intr_stat_clr_d[31]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_clr_d_reg[8] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\^genr_control_regs[1] [8]), + .Q(intr_stat_clr_d[8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_clr_d_reg[9] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\^genr_control_regs[1] [9]), + .Q(intr_stat_clr_d[9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[0] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[0]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[10] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[10]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[11] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[11]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [11]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[12] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[12]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [12]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[13] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[13]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[14] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[14]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [14]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[15] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[15]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [15]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[16] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[16]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [16]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[17] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[17]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [17]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[18] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[18]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [18]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[19] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[19]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [19]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[1] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[1]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[20] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[20]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [20]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[21] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[21]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [21]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[22] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[22]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [22]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[23] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[23]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [23]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[24] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[24]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [24]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[25] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[25]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [25]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[26] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[26]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [26]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[27] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[27]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [27]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[28] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[28]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [28]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[29] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[29]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [29]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[2] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[2]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[30] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[30]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [30]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[31] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[31]_i_1_n_0 ), + .Q(\GEN_HAS_IRQ.intr_stat_reg_n_0_[31] ), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[3] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[3]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[4] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[4]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [4]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[5] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[5]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[6] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[6]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [6]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[7] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[7]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[8] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[8]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [8]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_reg[9] + (.C(vid_aclk), + .CE(1'b1), + .D(\GEN_HAS_IRQ.intr_stat[9]_i_1_n_0 ), + .Q(\genr_status_regs_int_reg[1] [9]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[0] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [0]), + .Q(intr_stat_set_d[0]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[10] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [10]), + .Q(intr_stat_set_d[10]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[11] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [11]), + .Q(intr_stat_set_d[11]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[12] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [12]), + .Q(intr_stat_set_d[12]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[13] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [13]), + .Q(intr_stat_set_d[13]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[14] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [14]), + .Q(intr_stat_set_d[14]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[15] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [15]), + .Q(intr_stat_set_d[15]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[16] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [16]), + .Q(intr_stat_set_d[16]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[17] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [17]), + .Q(intr_stat_set_d[17]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[18] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [18]), + .Q(intr_stat_set_d[18]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[19] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [19]), + .Q(intr_stat_set_d[19]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[1] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [1]), + .Q(intr_stat_set_d[1]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[20] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [20]), + .Q(intr_stat_set_d[20]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[21] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [21]), + .Q(intr_stat_set_d[21]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[22] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [22]), + .Q(intr_stat_set_d[22]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[23] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [23]), + .Q(intr_stat_set_d[23]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[24] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [24]), + .Q(intr_stat_set_d[24]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[25] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [25]), + .Q(intr_stat_set_d[25]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[26] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [26]), + .Q(intr_stat_set_d[26]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[27] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [27]), + .Q(intr_stat_set_d[27]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[28] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [28]), + .Q(intr_stat_set_d[28]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[29] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [29]), + .Q(intr_stat_set_d[29]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[2] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [2]), + .Q(intr_stat_set_d[2]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[30] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [30]), + .Q(intr_stat_set_d[30]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[31] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [31]), + .Q(intr_stat_set_d[31]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[3] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [3]), + .Q(intr_stat_set_d[3]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[4] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [4]), + .Q(intr_stat_set_d[4]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[5] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [5]), + .Q(intr_stat_set_d[5]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[6] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [6]), + .Q(intr_stat_set_d[6]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[7] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [7]), + .Q(intr_stat_set_d[7]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[8] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [8]), + .Q(intr_stat_set_d[8]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \GEN_HAS_IRQ.intr_stat_set_d_reg[9] + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\genr_status_regs[1] [9]), + .Q(intr_stat_set_d[9]), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \GEN_HAS_IRQ.irq_i_1 + (.I0(resetn_out), + .O(\GEN_HAS_IRQ.irq_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \GEN_HAS_IRQ.irq_i_10 + (.I0(\genr_status_regs_int_reg[1] [22]), + .I1(\^genr_control_regs[3] [22]), + .I2(\genr_status_regs_int_reg[1] [21]), + .I3(\^genr_control_regs[3] [21]), + .I4(\^genr_control_regs[3] [20]), + .I5(\genr_status_regs_int_reg[1] [20]), + .O(\GEN_HAS_IRQ.irq_i_10_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \GEN_HAS_IRQ.irq_i_2 + (.I0(\GEN_HAS_IRQ.irq_i_3_n_0 ), + .I1(\GEN_HAS_IRQ.irq_i_4_n_0 ), + .I2(\GEN_HAS_IRQ.irq_i_5_n_0 ), + .I3(\GEN_HAS_IRQ.irq_i_6_n_0 ), + .O(\GEN_HAS_IRQ.irq_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \GEN_HAS_IRQ.irq_i_3 + (.I0(\genr_status_regs_int_reg[1] [11]), + .I1(\^genr_control_regs[3] [11]), + .I2(\genr_status_regs_int_reg[1] [10]), + .I3(\^genr_control_regs[3] [10]), + .I4(\^genr_control_regs[3] [9]), + .I5(\genr_status_regs_int_reg[1] [9]), + .O(\GEN_HAS_IRQ.irq_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \GEN_HAS_IRQ.irq_i_4 + (.I0(\genr_status_regs_int_reg[1] [16]), + .I1(\^genr_control_regs[3] [16]), + .I2(\genr_status_regs_int_reg[1] [13]), + .I3(\^genr_control_regs[3] [13]), + .I4(\^genr_control_regs[3] [12]), + .I5(\genr_status_regs_int_reg[1] [12]), + .O(\GEN_HAS_IRQ.irq_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \GEN_HAS_IRQ.irq_i_5 + (.I0(\genr_status_regs_int_reg[1] [19]), + .I1(\^genr_control_regs[3] [19]), + .I2(\genr_status_regs_int_reg[1] [18]), + .I3(\^genr_control_regs[3] [18]), + .I4(\^genr_control_regs[3] [17]), + .I5(\genr_status_regs_int_reg[1] [17]), + .O(\GEN_HAS_IRQ.irq_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFF8)) + \GEN_HAS_IRQ.irq_i_6 + (.I0(\genr_status_regs_int_reg[1] [8]), + .I1(\^genr_control_regs[3] [8]), + .I2(\GEN_HAS_IRQ.irq_i_7_n_0 ), + .I3(\GEN_HAS_IRQ.irq_i_8_n_0 ), + .I4(\GEN_HAS_IRQ.irq_i_9_n_0 ), + .I5(\GEN_HAS_IRQ.irq_i_10_n_0 ), + .O(\GEN_HAS_IRQ.irq_i_6_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \GEN_HAS_IRQ.irq_i_7 + (.I0(\genr_status_regs_int_reg[1] [28]), + .I1(\^genr_control_regs[3] [28]), + .I2(\genr_status_regs_int_reg[1] [27]), + .I3(\^genr_control_regs[3] [27]), + .I4(\^genr_control_regs[3] [26]), + .I5(\genr_status_regs_int_reg[1] [26]), + .O(\GEN_HAS_IRQ.irq_i_7_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \GEN_HAS_IRQ.irq_i_8 + (.I0(\GEN_HAS_IRQ.intr_stat_reg_n_0_[31] ), + .I1(\^genr_control_regs[3] [31]), + .I2(\genr_status_regs_int_reg[1] [30]), + .I3(\^genr_control_regs[3] [30]), + .I4(\^genr_control_regs[3] [29]), + .I5(\genr_status_regs_int_reg[1] [29]), + .O(\GEN_HAS_IRQ.irq_i_8_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \GEN_HAS_IRQ.irq_i_9 + (.I0(\genr_status_regs_int_reg[1] [25]), + .I1(\^genr_control_regs[3] [25]), + .I2(\genr_status_regs_int_reg[1] [24]), + .I3(\^genr_control_regs[3] [24]), + .I4(\^genr_control_regs[3] [23]), + .I5(\genr_status_regs_int_reg[1] [23]), + .O(\GEN_HAS_IRQ.irq_i_9_n_0 )); + FDRE \GEN_HAS_IRQ.irq_reg + (.C(vid_aclk), + .CE(vid_aclk_en), + .D(\GEN_HAS_IRQ.irq_i_2_n_0 ), + .Q(irq), + .R(\GEN_HAS_IRQ.irq_i_1_n_0 )); + GND GND + (.G(\ )); + LUT1 #( + .INIT(2'h1)) + ipif_rnw_out_INST_0 + (.I0(write_ack_int), + .O(ipif_rnw_out)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0_sim_netlist.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0_sim_netlist.vhdl new file mode 100644 index 0000000..90157a9 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0_sim_netlist.vhdl @@ -0,0 +1,61168 @@ +-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +-- Date : Sat Mar 04 18:56:17 2017 +-- Host : WK73 running 64-bit Service Pack 1 (build 7601) +-- Command : write_vhdl -force -mode funcsim +-- c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0_sim_netlist.vhdl +-- Design : Arty_Z7_20_v_tc_1_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg400-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_tc_1_0_address_decoder is + port ( + D : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arready : out STD_LOGIC; + s_axi_wready : out STD_LOGIC; + aclk : in STD_LOGIC; + ipif_RdAck : in STD_LOGIC; + is_read : in STD_LOGIC; + ipif_WrAck : in STD_LOGIC; + is_write_reg : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 9 downto 0 ); + aresetn : in STD_LOGIC; + start2_reg : in STD_LOGIC; + \bus2ip_addr_i_reg[8]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_tc_1_0_address_decoder : entity is "address_decoder"; +end Arty_Z7_20_v_tc_1_0_address_decoder; + +architecture STRUCTURE of Arty_Z7_20_v_tc_1_0_address_decoder is + signal \^d\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\ : STD_LOGIC; + signal \MEM_DECODE_GEN[0].cs_out_i[0]_i_2_n_0\ : STD_LOGIC; + signal \MEM_DECODE_GEN[1].cs_out_i[1]_i_1_n_0\ : STD_LOGIC; + signal \^s_axi_arready\ : STD_LOGIC; + signal \^s_axi_wready\ : STD_LOGIC; + signal s_axi_wready_INST_0_i_1_n_0 : STD_LOGIC; + signal s_axi_wready_INST_0_i_2_n_0 : STD_LOGIC; +begin + D(1 downto 0) <= \^d\(1 downto 0); + s_axi_arready <= \^s_axi_arready\; + s_axi_wready <= \^s_axi_wready\; +\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0008" + ) + port map ( + I0 => \MEM_DECODE_GEN[0].cs_out_i[0]_i_2_n_0\, + I1 => aresetn, + I2 => \^s_axi_arready\, + I3 => \^s_axi_wready\, + O => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\ + ); +\MEM_DECODE_GEN[0].cs_out_i[0]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F20" + ) + port map ( + I0 => \bus2ip_addr_i_reg[8]\(1), + I1 => \bus2ip_addr_i_reg[8]\(0), + I2 => start2_reg, + I3 => \^d\(1), + O => \MEM_DECODE_GEN[0].cs_out_i[0]_i_2_n_0\ + ); +\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\, + Q => \^d\(1), + R => '0' + ); +\MEM_DECODE_GEN[1].cs_out_i[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000002E00" + ) + port map ( + I0 => \^d\(0), + I1 => start2_reg, + I2 => \bus2ip_addr_i_reg[8]\(1), + I3 => aresetn, + I4 => \^s_axi_arready\, + I5 => \^s_axi_wready\, + O => \MEM_DECODE_GEN[1].cs_out_i[1]_i_1_n_0\ + ); +\MEM_DECODE_GEN[1].cs_out_i_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \MEM_DECODE_GEN[1].cs_out_i[1]_i_1_n_0\, + Q => \^d\(0), + R => '0' + ); +s_axi_arready_INST_0: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAEA" + ) + port map ( + I0 => ipif_RdAck, + I1 => is_read, + I2 => s_axi_wready_INST_0_i_1_n_0, + I3 => s_axi_wready_INST_0_i_2_n_0, + O => \^s_axi_arready\ + ); +s_axi_wready_INST_0: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAEA" + ) + port map ( + I0 => ipif_WrAck, + I1 => is_write_reg, + I2 => s_axi_wready_INST_0_i_1_n_0, + I3 => s_axi_wready_INST_0_i_2_n_0, + O => \^s_axi_wready\ + ); +s_axi_wready_INST_0_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000001" + ) + port map ( + I0 => Q(8), + I1 => Q(7), + I2 => Q(4), + I3 => Q(5), + I4 => Q(6), + O => s_axi_wready_INST_0_i_1_n_0 + ); +s_axi_wready_INST_0_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFB" + ) + port map ( + I0 => Q(1), + I1 => Q(9), + I2 => Q(0), + I3 => Q(3), + I4 => Q(2), + O => s_axi_wready_INST_0_i_2_n_0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_tc_1_0_mux_tree is + port ( + \AXI4_LITE_INTERFACE.ipif_RdData_reg[0]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0\ : out STD_LOGIC; + genr_data : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][31]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][30]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][29]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][28]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][27]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][26]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][25]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][24]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][23]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][22]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][21]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][20]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][19]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][18]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][17]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][16]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][15]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][14]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][13]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][12]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][11]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][10]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][9]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][8]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][7]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][6]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][5]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][4]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][3]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][2]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][1]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][0]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][31]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][30]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][29]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][28]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][27]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][26]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][25]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][24]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][23]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][22]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][21]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][20]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][19]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][18]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][17]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][16]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][15]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][14]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][13]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][12]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][11]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][10]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][9]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][8]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][7]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][6]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][5]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][4]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][3]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][2]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][1]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][0]_0\ : out STD_LOGIC; + \data_sync_reg[2][34]\ : in STD_LOGIC; + vid_aclk : in STD_LOGIC; + ipif_Addr : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \data_sync_reg[2][34]_0\ : in STD_LOGIC; + \time_status_regs[28]\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 25 downto 0 ); + \data_sync_reg[2][34]_1\ : in STD_LOGIC; + \data_sync_reg[2][34]_2\ : in STD_LOGIC; + \data_sync_reg[2][34]_3\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][28]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][27]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][26]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][25]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][24]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][23]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][22]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][21]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][20]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][19]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][18]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][17]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][16]\ : in STD_LOGIC; + \data_sync_reg[2][34]_4\ : in STD_LOGIC; + \data_sync_reg[2][34]_5\ : in STD_LOGIC; + \data_sync_reg[2][34]_6\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][12]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][11]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][10]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][9]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][8]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][7]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][6]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][5]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][4]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][3]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][2]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][1]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][0]\ : in STD_LOGIC; + \data_sync_reg[2][34]_7\ : in STD_LOGIC; + \data_sync_reg[2][34]_8\ : in STD_LOGIC; + \data_sync_reg[2][34]_9\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][27]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][26]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][25]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][24]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][23]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][22]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][21]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][20]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][19]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][18]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][17]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][16]\ : in STD_LOGIC; + \data_sync_reg[2][34]_10\ : in STD_LOGIC; + \data_sync_reg[2][34]_11\ : in STD_LOGIC; + \data_sync_reg[2][34]_12\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][12]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][11]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][10]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][9]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][8]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][7]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][6]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][5]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][4]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][3]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][2]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][1]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][0]\ : in STD_LOGIC; + \data_sync_reg[2][34]_13\ : in STD_LOGIC; + \data_sync_reg[2][34]_14\ : in STD_LOGIC; + \data_sync_reg[2][34]_15\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][27]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][26]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][25]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][24]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][23]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][22]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][21]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][20]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][19]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][18]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][17]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][16]\ : in STD_LOGIC; + \data_sync_reg[2][34]_16\ : in STD_LOGIC; + \data_sync_reg[2][34]_17\ : in STD_LOGIC; + \data_sync_reg[2][34]_18\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][12]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][11]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][10]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][9]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][8]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][7]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][6]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][5]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][4]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][3]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][2]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][1]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][0]\ : in STD_LOGIC; + \data_sync_reg[2][34]_19\ : in STD_LOGIC; + \data_sync_reg[2][34]_20\ : in STD_LOGIC; + \data_sync_reg[2][34]_21\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][27]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][26]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][25]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][24]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][23]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][22]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][21]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][20]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][19]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][18]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][17]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][16]\ : in STD_LOGIC; + \data_sync_reg[2][34]_22\ : in STD_LOGIC; + \data_sync_reg[2][34]_23\ : in STD_LOGIC; + \data_sync_reg[2][34]_24\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][12]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][11]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][10]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][9]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][8]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][7]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][6]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][5]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][4]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][3]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][2]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][1]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][0]\ : in STD_LOGIC; + \data_sync_reg[2][34]_25\ : in STD_LOGIC; + \data_sync_reg[2][34]_26\ : in STD_LOGIC; + \data_sync_reg[2][34]_27\ : in STD_LOGIC; + \data_sync_reg[2][34]_28\ : in STD_LOGIC; + \data_sync_reg[2][34]_29\ : in STD_LOGIC; + \data_sync_reg[2][34]_30\ : in STD_LOGIC; + \data_sync_reg[2][34]_31\ : in STD_LOGIC; + \data_sync_reg[2][34]_32\ : in STD_LOGIC; + \data_sync_reg[2][34]_33\ : in STD_LOGIC; + \data_sync_reg[2][34]_34\ : in STD_LOGIC; + \data_sync_reg[2][34]_35\ : in STD_LOGIC; + \data_sync_reg[2][34]_36\ : in STD_LOGIC; + \data_sync_reg[2][34]_37\ : in STD_LOGIC; + \data_sync_reg[2][34]_38\ : in STD_LOGIC; + \data_sync_reg[2][34]_39\ : in STD_LOGIC; + \data_sync_reg[2][34]_40\ : in STD_LOGIC; + \data_sync_reg[2][34]_41\ : in STD_LOGIC; + \data_sync_reg[2][34]_42\ : in STD_LOGIC; + \data_sync_reg[2][34]_43\ : in STD_LOGIC; + \data_sync_reg[2][34]_44\ : in STD_LOGIC; + \data_sync_reg[2][34]_45\ : in STD_LOGIC; + \data_sync_reg[2][34]_46\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][8]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][7]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][5]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][4]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][3]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][2]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][1]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][0]\ : in STD_LOGIC; + \data_sync_reg[2][34]_47\ : in STD_LOGIC; + \data_sync_reg[2][34]_48\ : in STD_LOGIC; + \data_sync_reg[2][34]_49\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][27]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][26]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][25]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][24]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][23]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][22]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][21]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][20]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][19]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][18]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][17]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][16]\ : in STD_LOGIC; + \data_sync_reg[2][34]_50\ : in STD_LOGIC; + \data_sync_reg[2][34]_51\ : in STD_LOGIC; + \data_sync_reg[2][34]_52\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][12]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][11]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][10]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][9]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][8]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][7]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][6]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][5]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][4]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][3]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][2]\ : in STD_LOGIC; + \intr_status_int_reg[12]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][0]\ : in STD_LOGIC; + \data_sync_reg[2][34]_53\ : in STD_LOGIC; + \data_sync_reg[2][34]_54\ : in STD_LOGIC; + \data_sync_reg[2][34]_55\ : in STD_LOGIC; + \data_sync_reg[2][34]_56\ : in STD_LOGIC; + \data_sync_reg[2][34]_57\ : in STD_LOGIC; + \data_sync_reg[2][34]_58\ : in STD_LOGIC; + \data_sync_reg[2][34]_59\ : in STD_LOGIC; + \data_sync_reg[2][34]_60\ : in STD_LOGIC; + \data_sync_reg[2][34]_61\ : in STD_LOGIC; + \data_sync_reg[2][34]_62\ : in STD_LOGIC; + \data_sync_reg[2][34]_63\ : in STD_LOGIC; + \data_sync_reg[2][34]_64\ : in STD_LOGIC; + \data_sync_reg[2][34]_65\ : in STD_LOGIC; + \data_sync_reg[2][34]_66\ : in STD_LOGIC; + \data_sync_reg[2][34]_67\ : in STD_LOGIC; + \data_sync_reg[2][34]_68\ : in STD_LOGIC; + \data_sync_reg[2][34]_69\ : in STD_LOGIC; + \data_sync_reg[2][34]_70\ : in STD_LOGIC; + \data_sync_reg[2][34]_71\ : in STD_LOGIC; + \data_sync_reg[2][34]_72\ : in STD_LOGIC; + \data_sync_reg[2][34]_73\ : in STD_LOGIC; + \data_sync_reg[2][34]_74\ : in STD_LOGIC; + \data_sync_reg[2][34]_75\ : in STD_LOGIC; + \data_sync_reg[2][34]_76\ : in STD_LOGIC; + \data_sync_reg[2][34]_77\ : in STD_LOGIC; + \data_sync_reg[2][34]_78\ : in STD_LOGIC; + \data_sync_reg[2][34]_79\ : in STD_LOGIC; + \data_sync_reg[2][34]_80\ : in STD_LOGIC; + \data_sync_reg[2][34]_81\ : in STD_LOGIC; + \data_sync_reg[2][34]_82\ : in STD_LOGIC; + \data_sync_reg[2][34]_83\ : in STD_LOGIC; + \data_sync_reg[2][34]_84\ : in STD_LOGIC; + \data_sync_reg[2][34]_85\ : in STD_LOGIC; + \data_sync_reg[2][34]_86\ : in STD_LOGIC; + \data_sync_reg[2][34]_87\ : in STD_LOGIC; + \data_sync_reg[2][34]_88\ : in STD_LOGIC; + \data_sync_reg[2][34]_89\ : in STD_LOGIC; + \data_sync_reg[2][34]_90\ : in STD_LOGIC; + \data_sync_reg[2][34]_91\ : in STD_LOGIC; + \data_sync_reg[2][34]_92\ : in STD_LOGIC; + \data_sync_reg[2][34]_93\ : in STD_LOGIC; + \data_sync_reg[2][34]_94\ : in STD_LOGIC; + \data_sync_reg[2][34]_95\ : in STD_LOGIC; + \data_sync_reg[2][34]_96\ : in STD_LOGIC; + \data_sync_reg[2][34]_97\ : in STD_LOGIC; + \data_sync_reg[2][34]_98\ : in STD_LOGIC; + \data_sync_reg[2][34]_99\ : in STD_LOGIC; + \data_sync_reg[2][34]_100\ : in STD_LOGIC; + \data_sync_reg[2][34]_101\ : in STD_LOGIC; + \data_sync_reg[2][34]_102\ : in STD_LOGIC; + \data_sync_reg[2][34]_103\ : in STD_LOGIC; + \data_sync_reg[2][34]_104\ : in STD_LOGIC; + \data_sync_reg[2][34]_105\ : in STD_LOGIC; + \data_sync_reg[2][34]_106\ : in STD_LOGIC; + \data_sync_reg[2][34]_107\ : in STD_LOGIC; + \data_sync_reg[2][34]_108\ : in STD_LOGIC; + \data_sync_reg[2][34]_109\ : in STD_LOGIC; + \data_sync_reg[2][34]_110\ : in STD_LOGIC; + \data_sync_reg[2][34]_111\ : in STD_LOGIC; + \data_sync_reg[2][34]_112\ : in STD_LOGIC; + \data_sync_reg[2][34]_113\ : in STD_LOGIC; + \data_sync_reg[2][34]_114\ : in STD_LOGIC; + \data_sync_reg[2][34]_115\ : in STD_LOGIC; + \data_sync_reg[2][34]_116\ : in STD_LOGIC; + \data_sync_reg[2][34]_117\ : in STD_LOGIC; + \data_sync_reg[2][34]_118\ : in STD_LOGIC; + \data_sync_reg[2][34]_119\ : in STD_LOGIC; + \data_sync_reg[2][34]_120\ : in STD_LOGIC; + \data_sync_reg[2][34]_121\ : in STD_LOGIC; + \data_sync_reg[2][34]_122\ : in STD_LOGIC; + \data_sync_reg[2][34]_123\ : in STD_LOGIC; + \data_sync_reg[2][34]_124\ : in STD_LOGIC; + \data_sync_reg[2][34]_125\ : in STD_LOGIC; + \data_sync_reg[2][34]_126\ : in STD_LOGIC; + \data_sync_reg[2][34]_127\ : in STD_LOGIC; + \data_sync_reg[2][34]_128\ : in STD_LOGIC; + \data_sync_reg[2][34]_129\ : in STD_LOGIC; + \data_sync_reg[2][34]_130\ : in STD_LOGIC; + \data_sync_reg[2][34]_131\ : in STD_LOGIC; + \data_sync_reg[2][34]_132\ : in STD_LOGIC; + \data_sync_reg[2][34]_133\ : in STD_LOGIC; + \data_sync_reg[2][34]_134\ : in STD_LOGIC; + \data_sync_reg[2][34]_135\ : in STD_LOGIC; + \data_sync_reg[2][34]_136\ : in STD_LOGIC; + \data_sync_reg[2][34]_137\ : in STD_LOGIC; + \data_sync_reg[2][34]_138\ : in STD_LOGIC; + \data_sync_reg[2][34]_139\ : in STD_LOGIC; + \data_sync_reg[2][34]_140\ : in STD_LOGIC; + \data_sync_reg[2][34]_141\ : in STD_LOGIC; + \data_sync_reg[2][34]_142\ : in STD_LOGIC; + \data_sync_reg[2][34]_143\ : in STD_LOGIC; + \data_sync_reg[2][34]_144\ : in STD_LOGIC; + \data_sync_reg[2][34]_145\ : in STD_LOGIC; + \data_sync_reg[2][34]_146\ : in STD_LOGIC; + \data_sync_reg[2][34]_147\ : in STD_LOGIC; + \data_sync_reg[2][34]_148\ : in STD_LOGIC; + \data_sync_reg[2][34]_149\ : in STD_LOGIC; + \data_sync_reg[2][34]_150\ : in STD_LOGIC; + \data_sync_reg[2][34]_151\ : in STD_LOGIC; + \data_sync_reg[2][34]_152\ : in STD_LOGIC; + \det_v0bp_start_hori_int2_reg[11]\ : in STD_LOGIC; + \det_v0bp_start_hori_int2_reg[10]\ : in STD_LOGIC; + \det_v0bp_start_hori_int2_reg[9]\ : in STD_LOGIC; + \det_v0bp_start_hori_int2_reg[8]\ : in STD_LOGIC; + \det_v0bp_start_hori_int2_reg[7]\ : in STD_LOGIC; + \det_v0bp_start_hori_int2_reg[6]\ : in STD_LOGIC; + \det_v0bp_start_hori_int2_reg[5]\ : in STD_LOGIC; + \det_v0bp_start_hori_int2_reg[4]\ : in STD_LOGIC; + \det_v0bp_start_hori_int2_reg[3]\ : in STD_LOGIC; + \det_v0bp_start_hori_int2_reg[2]\ : in STD_LOGIC; + \det_v0bp_start_hori_int2_reg[1]\ : in STD_LOGIC; + \det_v0bp_start_hori_int2_reg[0]\ : in STD_LOGIC; + \data_sync_reg[2][34]_153\ : in STD_LOGIC; + \data_sync_reg[2][34]_154\ : in STD_LOGIC; + \data_sync_reg[2][34]_155\ : in STD_LOGIC; + \data_sync_reg[2][34]_156\ : in STD_LOGIC; + \det_v0sync_start_hori_int2_reg[11]\ : in STD_LOGIC; + \det_v0sync_start_hori_int2_reg[10]\ : in STD_LOGIC; + \det_v0sync_start_hori_int2_reg[9]\ : in STD_LOGIC; + \det_v0sync_start_hori_int2_reg[8]\ : in STD_LOGIC; + \det_v0sync_start_hori_int2_reg[7]\ : in STD_LOGIC; + \det_v0sync_start_hori_int2_reg[6]\ : in STD_LOGIC; + \det_v0sync_start_hori_int2_reg[5]\ : in STD_LOGIC; + \det_v0sync_start_hori_int2_reg[4]\ : in STD_LOGIC; + \det_v0sync_start_hori_int2_reg[3]\ : in STD_LOGIC; + \det_v0sync_start_hori_int2_reg[2]\ : in STD_LOGIC; + \det_v0sync_start_hori_int2_reg[1]\ : in STD_LOGIC; + \det_v0sync_start_hori_int2_reg[0]\ : in STD_LOGIC; + \data_sync_reg[2][34]_157\ : in STD_LOGIC; + \data_sync_reg[2][34]_158\ : in STD_LOGIC; + \data_sync_reg[2][34]_159\ : in STD_LOGIC; + \data_sync_reg[2][34]_160\ : in STD_LOGIC; + \det_v0active_start_hori_int2_reg[11]\ : in STD_LOGIC; + \det_v0active_start_hori_int2_reg[10]\ : in STD_LOGIC; + \det_v0active_start_hori_int2_reg[9]\ : in STD_LOGIC; + \det_v0active_start_hori_int2_reg[8]\ : in STD_LOGIC; + \det_v0active_start_hori_int2_reg[7]\ : in STD_LOGIC; + \det_v0active_start_hori_int2_reg[6]\ : in STD_LOGIC; + \det_v0active_start_hori_int2_reg[5]\ : in STD_LOGIC; + \det_v0active_start_hori_int2_reg[4]\ : in STD_LOGIC; + \det_v0active_start_hori_int2_reg[3]\ : in STD_LOGIC; + \det_v0active_start_hori_int2_reg[2]\ : in STD_LOGIC; + \det_v0active_start_hori_int2_reg[1]\ : in STD_LOGIC; + \det_v0active_start_hori_int2_reg[0]\ : in STD_LOGIC; + \data_sync_reg[2][34]_161\ : in STD_LOGIC; + \data_sync_reg[2][34]_162\ : in STD_LOGIC; + \data_sync_reg[2][34]_163\ : in STD_LOGIC; + \data_sync_reg[2][34]_164\ : in STD_LOGIC; + \det_v0fp_start_hori_int2_reg[11]\ : in STD_LOGIC; + \det_v0fp_start_hori_int2_reg[10]\ : in STD_LOGIC; + \det_v0fp_start_hori_int2_reg[9]\ : in STD_LOGIC; + \det_v0fp_start_hori_int2_reg[8]\ : in STD_LOGIC; + \det_v0fp_start_hori_int2_reg[7]\ : in STD_LOGIC; + \det_v0fp_start_hori_int2_reg[6]\ : in STD_LOGIC; + \det_v0fp_start_hori_int2_reg[5]\ : in STD_LOGIC; + \det_v0fp_start_hori_int2_reg[4]\ : in STD_LOGIC; + \det_v0fp_start_hori_int2_reg[3]\ : in STD_LOGIC; + \det_v0fp_start_hori_int2_reg[2]\ : in STD_LOGIC; + \det_v0fp_start_hori_int2_reg[1]\ : in STD_LOGIC; + \det_v0fp_start_hori_int2_reg[0]\ : in STD_LOGIC; + \data_sync_reg[2][34]_165\ : in STD_LOGIC; + \data_sync_reg[2][34]_166\ : in STD_LOGIC; + \data_sync_reg[2][34]_167\ : in STD_LOGIC; + \data_sync_reg[2][34]_168\ : in STD_LOGIC; + \data_sync_reg[2][34]_169\ : in STD_LOGIC; + \data_sync_reg[2][34]_170\ : in STD_LOGIC; + \data_sync_reg[2][34]_171\ : in STD_LOGIC; + \data_sync_reg[2][34]_172\ : in STD_LOGIC; + \data_sync_reg[2][34]_173\ : in STD_LOGIC; + \data_sync_reg[2][34]_174\ : in STD_LOGIC; + \data_sync_reg[2][34]_175\ : in STD_LOGIC; + \data_sync_reg[2][34]_176\ : in STD_LOGIC; + \data_sync_reg[2][34]_177\ : in STD_LOGIC; + \data_sync_reg[2][34]_178\ : in STD_LOGIC; + \data_sync_reg[2][34]_179\ : in STD_LOGIC; + \data_sync_reg[2][34]_180\ : in STD_LOGIC; + \data_sync_reg[2][34]_181\ : in STD_LOGIC; + \data_sync_reg[2][34]_182\ : in STD_LOGIC; + \data_sync_reg[2][34]_183\ : in STD_LOGIC; + \data_sync_reg[2][34]_184\ : in STD_LOGIC; + \det_htotal_int2_reg[11]\ : in STD_LOGIC; + \det_v0total_reg[10]\ : in STD_LOGIC; + \det_v0total_reg[9]\ : in STD_LOGIC; + \det_v0total_reg[8]\ : in STD_LOGIC; + \det_v0total_reg[7]\ : in STD_LOGIC; + \det_v0total_reg[6]\ : in STD_LOGIC; + \det_v0total_reg[5]\ : in STD_LOGIC; + \det_v0total_reg[4]\ : in STD_LOGIC; + \det_v0total_reg[3]\ : in STD_LOGIC; + \det_v0total_reg[2]\ : in STD_LOGIC; + \det_v0total_reg[1]\ : in STD_LOGIC; + \det_v0total_reg[0]\ : in STD_LOGIC; + \data_sync_reg[2][34]_185\ : in STD_LOGIC; + \data_sync_reg[2][34]_186\ : in STD_LOGIC; + \data_sync_reg[2][34]_187\ : in STD_LOGIC; + \data_sync_reg[2][34]_188\ : in STD_LOGIC; + \data_sync_reg[2][34]_189\ : in STD_LOGIC; + \data_sync_reg[2][34]_190\ : in STD_LOGIC; + \data_sync_reg[2][34]_191\ : in STD_LOGIC; + \data_sync_reg[2][34]_192\ : in STD_LOGIC; + \data_sync_reg[2][34]_193\ : in STD_LOGIC; + \data_sync_reg[2][34]_194\ : in STD_LOGIC; + \data_sync_reg[2][34]_195\ : in STD_LOGIC; + \data_sync_reg[2][34]_196\ : in STD_LOGIC; + \data_sync_reg[2][34]_197\ : in STD_LOGIC; + \data_sync_reg[2][34]_198\ : in STD_LOGIC; + \data_sync_reg[2][34]_199\ : in STD_LOGIC; + \data_sync_reg[2][34]_200\ : in STD_LOGIC; + \data_sync_reg[2][34]_201\ : in STD_LOGIC; + \data_sync_reg[2][34]_202\ : in STD_LOGIC; + \data_sync_reg[2][34]_203\ : in STD_LOGIC; + \data_sync_reg[2][34]_204\ : in STD_LOGIC; + \data_sync_reg[2][34]_205\ : in STD_LOGIC; + \data_sync_reg[2][34]_206\ : in STD_LOGIC; + \data_sync_reg[2][34]_207\ : in STD_LOGIC; + \gen_v0chroma_start_reg[0]\ : in STD_LOGIC; + \data_sync_reg[2][34]_208\ : in STD_LOGIC; + \data_sync_reg[2][34]_209\ : in STD_LOGIC; + \data_sync_reg[2][34]_210\ : in STD_LOGIC; + \DET_HACTIVE.det_active_video_pol_int_reg\ : in STD_LOGIC; + \DET_HSYNC.det_hsync_pol_int_reg\ : in STD_LOGIC; + \DET_VSYNC.det_vsync_pol_int_reg\ : in STD_LOGIC; + \data_sync_reg[2][34]_211\ : in STD_LOGIC; + \data_sync_reg[2][34]_212\ : in STD_LOGIC; + \data_sync_reg[2][34]_213\ : in STD_LOGIC; + \data_sync_reg[2][34]_214\ : in STD_LOGIC; + \data_sync_reg[2][34]_215\ : in STD_LOGIC; + \data_sync_reg[2][34]_216\ : in STD_LOGIC; + \data_sync_reg[2][34]_217\ : in STD_LOGIC; + \det_v0fp_start_int_reg[10]\ : in STD_LOGIC; + \det_v0fp_start_int_reg[9]\ : in STD_LOGIC; + \det_v0fp_start_int_reg[8]\ : in STD_LOGIC; + \det_v0fp_start_int_reg[7]\ : in STD_LOGIC; + \det_v0fp_start_int_reg[6]\ : in STD_LOGIC; + \det_v0fp_start_int_reg[5]\ : in STD_LOGIC; + \det_v0fp_start_int_reg[4]\ : in STD_LOGIC; + \det_v0fp_start_int_reg[3]\ : in STD_LOGIC; + \det_v0fp_start_int_reg[2]\ : in STD_LOGIC; + \det_v0fp_start_int_reg[1]\ : in STD_LOGIC; + \det_v0fp_start_int_reg[0]\ : in STD_LOGIC; + \data_sync_reg[2][34]_218\ : in STD_LOGIC; + \data_sync_reg[2][34]_219\ : in STD_LOGIC; + \data_sync_reg[2][34]_220\ : in STD_LOGIC; + \data_sync_reg[2][34]_221\ : in STD_LOGIC; + \det_hfp_start_int2_reg[11]\ : in STD_LOGIC; + \det_hfp_start_int2_reg[10]\ : in STD_LOGIC; + \det_hfp_start_int2_reg[9]\ : in STD_LOGIC; + \det_hfp_start_int2_reg[8]\ : in STD_LOGIC; + \det_hfp_start_int2_reg[7]\ : in STD_LOGIC; + \det_hfp_start_int2_reg[6]\ : in STD_LOGIC; + \det_hfp_start_int2_reg[5]\ : in STD_LOGIC; + \det_hfp_start_int2_reg[4]\ : in STD_LOGIC; + \det_hfp_start_int2_reg[3]\ : in STD_LOGIC; + \intr_status_int_reg[11]\ : in STD_LOGIC; + \intr_status_int_reg[10]\ : in STD_LOGIC; + \intr_status_int_reg[8]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][31]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][30]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][29]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][28]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][27]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][26]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][25]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][24]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][23]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][22]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][21]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][20]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][19]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][18]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][17]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][16]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_err_reg[15]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_err_reg[14]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][13]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][12]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][11]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][10]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][9]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][8]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_err_reg[7]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_err_reg[6]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_err_reg[5]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_err_reg[4]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_err_reg[3]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_err_reg[2]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_err_reg[1]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_err_reg[0]\ : in STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][31]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[30]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[29]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[28]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[27]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[26]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[25]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[24]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[23]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[22]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[21]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[20]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[19]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[18]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[17]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[16]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[15]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[14]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[13]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[12]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[11]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[10]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[9]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[8]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[7]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[6]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[5]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[4]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[3]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[2]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[1]\ : in STD_LOGIC; + \GEN_HAS_IRQ.intr_stat_reg[0]\ : in STD_LOGIC; + \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ : in STD_LOGIC; + \core_status_regs[15]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \core_status_regs[14]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \core_status_regs[13]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \data_sync_reg[2][34]_222\ : in STD_LOGIC; + \core_status_regs[12]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \core_status_regs[11]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \core_status_regs[10]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \core_status_regs[9]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \core_status_regs[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + core_regs : in STD_LOGIC_VECTOR ( 351 downto 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \core_status_regs[7]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \core_status_regs[6]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \core_status_regs[5]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \core_status_regs[4]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \core_status_regs[3]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \core_status_regs[2]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \core_status_regs[1]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \core_status_regs[0]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_tc_1_0_mux_tree : entity is "mux_tree"; +end Arty_Z7_20_v_tc_1_0_mux_tree; + +architecture STRUCTURE of Arty_Z7_20_v_tc_1_0_mux_tree is + signal \^axi4_lite_interface.ipif_rddata_reg[0]\ : STD_LOGIC; + signal \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\ : STD_LOGIC; + signal \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\ : STD_LOGIC; + signal \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\ : STD_LOGIC; + signal \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ : STD_LOGIC; + signal \GEN_SEL_DELAY[4].sel_int_reg[4][1]_srl3_n_0\ : STD_LOGIC; + signal \GEN_SEL_DELAY[5].sel_int_reg[5][1]_srl4_n_0\ : STD_LOGIC; + signal \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \GEN_TREE.GEN_BRANCH[33].GEN_MUX_REG.data_out_reg_reg[33]_0\ : STD_LOGIC_VECTOR ( 26 to 26 ); + signal \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][0]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][16]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][1]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][25]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][26]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][3]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_2__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_3__0_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_3_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][0]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][10]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][11]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][12]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][13]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][14]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][15]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][16]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][17]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][18]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][19]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][1]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][20]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][21]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][22]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][23]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][24]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][25]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][26]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][27]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][28]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][29]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][2]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][30]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][31]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][3]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][4]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][5]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][6]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][7]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][8]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][9]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][0]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][10]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][11]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][12]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][13]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][14]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][15]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][16]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][17]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][18]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][19]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][1]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][20]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][21]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][22]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][23]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][24]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][25]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][26]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][27]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][28]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][29]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][2]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][30]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][3]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][4]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][5]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][6]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][7]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][8]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][9]_i_1_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \sel_int[2]_1\ : STD_LOGIC_VECTOR ( 0 to 0 ); + attribute ORIG_CELL_NAME : string; + attribute ORIG_CELL_NAME of \GEN_SEL_DELAY[1].sel_int_reg[1][0]\ : label is "GEN_SEL_DELAY[1].sel_int_reg[1][0]"; + attribute ORIG_CELL_NAME of \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep\ : label is "GEN_SEL_DELAY[1].sel_int_reg[1][0]"; + attribute ORIG_CELL_NAME of \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ : label is "GEN_SEL_DELAY[2].sel_int_reg[2][0]"; + attribute ORIG_CELL_NAME of \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep\ : label is "GEN_SEL_DELAY[2].sel_int_reg[2][0]"; + attribute srl_bus_name : string; + attribute srl_bus_name of \GEN_SEL_DELAY[4].sel_int_reg[4][1]_srl3\ : label is "U0/U_VIDEO_CTRL/\AXI4_LITE_INTERFACE.GENR_MUX0/GEN_SEL_DELAY[4].sel_int_reg[4] "; + attribute srl_name : string; + attribute srl_name of \GEN_SEL_DELAY[4].sel_int_reg[4][1]_srl3\ : label is "U0/U_VIDEO_CTRL/\AXI4_LITE_INTERFACE.GENR_MUX0/GEN_SEL_DELAY[4].sel_int_reg[4][1]_srl3 "; + attribute srl_bus_name of \GEN_SEL_DELAY[5].sel_int_reg[5][1]_srl4\ : label is "U0/U_VIDEO_CTRL/\AXI4_LITE_INTERFACE.GENR_MUX0/GEN_SEL_DELAY[5].sel_int_reg[5] "; + attribute srl_name of \GEN_SEL_DELAY[5].sel_int_reg[5][1]_srl4\ : label is "U0/U_VIDEO_CTRL/\AXI4_LITE_INTERFACE.GENR_MUX0/GEN_SEL_DELAY[5].sel_int_reg[5][1]_srl4 "; +begin + \AXI4_LITE_INTERFACE.ipif_RdData_reg[0]\ <= \^axi4_lite_interface.ipif_rddata_reg[0]\; +\AXI4_LITE_INTERFACE.ipif_RdData[0]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(0), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(0), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(0), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(0) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[10]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(10), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(10), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(10), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(10) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[11]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(11), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(11), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(11), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(11) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[12]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(12), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(12), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(12), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(12) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[13]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(13), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(13), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(13), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(13) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[14]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(14), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(14), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(14), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(14) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[15]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(15), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(15), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(15), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(15) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[16]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(16), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(16), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(16), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(16) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[17]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(17), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(17), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(17), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(17) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[18]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(18), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(18), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(18), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(18) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[19]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(19), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(19), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(19), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(19) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[1]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(1), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(1), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(1), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(1) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[20]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(20), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(20), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(20), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(20) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[21]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(21), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(21), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(21), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(21) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[22]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(22), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(22), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(22), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(22) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[23]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(23), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(23), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(23), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(23) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[24]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(24), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(24), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(24), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(24) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[25]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(25), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(25), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(25), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(25) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[26]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(26), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(26), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(26), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(26) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[27]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(27), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(27), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(27), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(27) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[28]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(28), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(28), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(28), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(28) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[29]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(29), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(29), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(29), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(29) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[2]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(2), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(2), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(2), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(2) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[30]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(30), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(30), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(30), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(30) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[31]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(31), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(31), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(31), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(31) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[3]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(3), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(3), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(3), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(3) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[4]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(4), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(4), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(4), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(4) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[5]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(5), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(5), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(5), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(5) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[6]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(6), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(6), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(6), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(6) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[7]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(7), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(7), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(7), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(7) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[8]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(8), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(8), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(8), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(8) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[9]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(9), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(9), + I2 => \^axi4_lite_interface.ipif_rddata_reg[0]\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(9), + I4 => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + O => genr_data(9) + ); +\GEN_SEL_DELAY[1].sel_int_reg[1][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => ipif_Addr(1), + Q => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + R => '0' + ); +\GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => ipif_Addr(1), + Q => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + R => '0' + ); +\GEN_SEL_DELAY[2].sel_int_reg[2][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \sel_int[2]_1\(0), + Q => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\, + R => '0' + ); +\GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \sel_int[2]_1\(0), + Q => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + R => '0' + ); +\GEN_SEL_DELAY[2].sel_int_reg[2][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => ipif_Addr(2), + Q => \sel_int[2]_1\(0), + R => '0' + ); +\GEN_SEL_DELAY[4].sel_int_reg[4][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[4].sel_int_reg[4][1]_srl3_n_0\, + Q => \^axi4_lite_interface.ipif_rddata_reg[0]\, + R => '0' + ); +\GEN_SEL_DELAY[4].sel_int_reg[4][1]_srl3\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '0', + A1 => '1', + A2 => '0', + A3 => '0', + CE => '1', + CLK => vid_aclk, + D => ipif_Addr(3), + Q => \GEN_SEL_DELAY[4].sel_int_reg[4][1]_srl3_n_0\ + ); +\GEN_SEL_DELAY[5].sel_int_reg[5][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[5].sel_int_reg[5][1]_srl4_n_0\, + Q => \GEN_SEL_DELAY[5].sel_int_reg_n_0_[5][0]\, + R => '0' + ); +\GEN_SEL_DELAY[5].sel_int_reg[5][1]_srl4\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '1', + A2 => '0', + A3 => '0', + CE => '1', + CLK => vid_aclk, + D => ipif_Addr(4), + Q => \GEN_SEL_DELAY[5].sel_int_reg[5][1]_srl4_n_0\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[0]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(0), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[10]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(10), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[11]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(11), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[12]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(12), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[13]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(13), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[14]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(14), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[15]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(15), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[16]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(16), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[17]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(17), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[18]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(18), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[19]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(19), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[1]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(1), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[20]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(20), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[21]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(21), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[22]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(22), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[23]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(23), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[24]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(24), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[25]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(25), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[26]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(26), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[27]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(27), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[28]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(28), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[29]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(29), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[2]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(2), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[30]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(30), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][31]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(31), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[3]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(3), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[4]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(4), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[5]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(5), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[6]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(6), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[7]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(7), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[8]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(8), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat_reg[9]\, + Q => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(9), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err_reg[0]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(0), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][10]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(10), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][11]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(11), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][12]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(12), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][13]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(13), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err_reg[14]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(14), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err_reg[15]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(15), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][16]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(16), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][17]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(17), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][18]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(18), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][19]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(19), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err_reg[1]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(1), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][20]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(20), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][21]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(21), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][22]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(22), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][23]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(23), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][24]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(24), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][25]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(25), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][26]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(26), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][27]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(27), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][28]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(28), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][29]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(29), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err_reg[2]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(2), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][30]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(30), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][31]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(31), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err_reg[3]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(3), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err_reg[4]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(4), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err_reg[5]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(5), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err_reg[6]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(6), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err_reg[7]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(7), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][8]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(8), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][9]\, + Q => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(9), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[33].GEN_MUX_REG.data_out_reg_reg[33][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]\, + Q => \GEN_TREE.GEN_BRANCH[33].GEN_MUX_REG.data_out_reg_reg[33]_0\(26), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \intr_status_int_reg[8]\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(0), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_hfp_start_int2_reg[10]\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(10), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_hfp_start_int2_reg[11]\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(11), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_221\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(12), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_220\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(13), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_219\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(14), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_218\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(15), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0fp_start_int_reg[0]\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(16), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0fp_start_int_reg[1]\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(17), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0fp_start_int_reg[2]\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(18), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0fp_start_int_reg[3]\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(19), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \intr_status_int_reg[10]\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(1), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0fp_start_int_reg[4]\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(20), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0fp_start_int_reg[5]\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(21), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0fp_start_int_reg[6]\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(22), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0fp_start_int_reg[7]\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(23), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0fp_start_int_reg[8]\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(24), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0fp_start_int_reg[9]\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(25), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0fp_start_int_reg[10]\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(26), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_217\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(27), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_216\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(28), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_215\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(29), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \intr_status_int_reg[11]\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(2), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_214\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(30), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_213\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(31), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_hfp_start_int2_reg[3]\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(3), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_hfp_start_int2_reg[4]\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(4), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_hfp_start_int2_reg[5]\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(5), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_hfp_start_int2_reg[6]\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(6), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_hfp_start_int2_reg[7]\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(7), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_hfp_start_int2_reg[8]\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(8), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_hfp_start_int2_reg[9]\, + Q => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(9), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_212\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(0), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_206\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(10), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_205\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(11), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_204\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(12), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_203\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(13), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_202\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(14), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_201\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(15), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_200\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(16), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_199\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(17), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_198\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(18), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_197\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(19), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_211\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(1), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_196\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(20), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_195\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(21), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_194\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(22), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_193\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(23), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_192\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(24), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_191\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(25), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_190\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(26), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_189\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(27), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_188\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(28), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_187\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(29), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \DET_VSYNC.det_vsync_pol_int_reg\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(2), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_186\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(30), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_185\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(31), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \DET_HSYNC.det_hsync_pol_int_reg\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(3), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \DET_HACTIVE.det_active_video_pol_int_reg\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(4), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_210\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(5), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_209\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(6), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_208\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(7), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \gen_v0chroma_start_reg[0]\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(8), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_207\, + Q => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(9), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0total_reg[0]\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(0), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0total_reg[10]\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(10), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_htotal_int2_reg[11]\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(11), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_184\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(12), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_183\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(13), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_182\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(14), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_181\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(15), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_180\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(16), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_179\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(17), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_178\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(18), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_177\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(19), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0total_reg[1]\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(1), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_176\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(20), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_175\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(21), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_174\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(22), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_173\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(23), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_172\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(24), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_171\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(25), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_170\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(26), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_169\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(27), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_168\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(28), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_167\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(29), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0total_reg[2]\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(2), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_166\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(30), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_165\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(31), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0total_reg[3]\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(3), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0total_reg[4]\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(4), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0total_reg[5]\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(5), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0total_reg[6]\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(6), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0total_reg[7]\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(7), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0total_reg[8]\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(8), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0total_reg[9]\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(9), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0fp_start_hori_int2_reg[0]\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(0), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0fp_start_hori_int2_reg[10]\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(10), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0fp_start_hori_int2_reg[11]\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(11), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_164\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(12), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_163\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(13), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_162\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(14), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_161\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(15), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0active_start_hori_int2_reg[0]\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(16), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0active_start_hori_int2_reg[1]\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(17), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0active_start_hori_int2_reg[2]\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(18), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0active_start_hori_int2_reg[3]\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(19), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0fp_start_hori_int2_reg[1]\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(1), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0active_start_hori_int2_reg[4]\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(20), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0active_start_hori_int2_reg[5]\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(21), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0active_start_hori_int2_reg[6]\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(22), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0active_start_hori_int2_reg[7]\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(23), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0active_start_hori_int2_reg[8]\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(24), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0active_start_hori_int2_reg[9]\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(25), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0active_start_hori_int2_reg[10]\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(26), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0active_start_hori_int2_reg[11]\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(27), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_160\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(28), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_159\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(29), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0fp_start_hori_int2_reg[2]\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(2), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_158\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(30), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_157\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(31), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0fp_start_hori_int2_reg[3]\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(3), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0fp_start_hori_int2_reg[4]\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(4), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0fp_start_hori_int2_reg[5]\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(5), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0fp_start_hori_int2_reg[6]\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(6), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0fp_start_hori_int2_reg[7]\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(7), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0fp_start_hori_int2_reg[8]\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(8), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0fp_start_hori_int2_reg[9]\, + Q => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(9), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0sync_start_hori_int2_reg[0]\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(0), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0sync_start_hori_int2_reg[10]\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(10), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0sync_start_hori_int2_reg[11]\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(11), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_156\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(12), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_155\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(13), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_154\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(14), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_153\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(15), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0bp_start_hori_int2_reg[0]\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(16), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0bp_start_hori_int2_reg[1]\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(17), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0bp_start_hori_int2_reg[2]\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(18), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0bp_start_hori_int2_reg[3]\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(19), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0sync_start_hori_int2_reg[1]\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(1), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0bp_start_hori_int2_reg[4]\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(20), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0bp_start_hori_int2_reg[5]\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(21), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0bp_start_hori_int2_reg[6]\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(22), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0bp_start_hori_int2_reg[7]\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(23), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0bp_start_hori_int2_reg[8]\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(24), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0bp_start_hori_int2_reg[9]\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(25), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0bp_start_hori_int2_reg[10]\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(26), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0bp_start_hori_int2_reg[11]\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(27), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_152\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(28), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_151\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(29), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0sync_start_hori_int2_reg[2]\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(2), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_150\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(30), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_149\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(31), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0sync_start_hori_int2_reg[3]\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(3), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0sync_start_hori_int2_reg[4]\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(4), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0sync_start_hori_int2_reg[5]\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(5), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0sync_start_hori_int2_reg[6]\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(6), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0sync_start_hori_int2_reg[7]\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(7), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0sync_start_hori_int2_reg[8]\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(8), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \det_v0sync_start_hori_int2_reg[9]\, + Q => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(9), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[33].GEN_MUX_REG.data_out_reg_reg[33]_0\(26), + I1 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(0), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(0), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][0]\(0), + I1 => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][0]\(0), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][0]\(0), + I4 => \data_sync_reg[2][34]_0\, + I5 => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]\(0), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(0), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(0), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(0), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(0), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][0]\(0), + I1 => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][0]\(0), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][0]\(0), + I4 => \data_sync_reg[2][34]_0\, + I5 => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][0]\(0), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888888BBB888B8" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_2_n_0\, + I1 => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\, + I2 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(10), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(10), + I5 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(10), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(10), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(10), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(10), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(75), + I1 => core_regs(53), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(31), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(9), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(163), + I1 => core_regs(141), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(119), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(97), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888888BBB888B8" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_2_n_0\, + I1 => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\, + I2 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(11), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(11), + I5 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(11), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(11), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(11), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(11), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(76), + I1 => core_regs(54), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(32), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(10), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(164), + I1 => core_regs(142), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(120), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(98), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888888BBB888B8" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_2_n_0\, + I1 => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\, + I2 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(12), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(12), + I5 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(12), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(12), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(12), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(12), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[3]\(0), + I1 => \core_status_regs[2]\(0), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[1]\(0), + I4 => \data_sync_reg[2][34]_0\, + I5 => \core_status_regs[0]\(0), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[7]\(0), + I1 => \core_status_regs[6]\(0), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[5]\(0), + I4 => \data_sync_reg[2][34]_0\, + I5 => \core_status_regs[4]\(0), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888888BBB888B8" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_2_n_0\, + I1 => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\, + I2 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(13), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(13), + I5 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(13), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(13), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(13), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(13), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[3]\(1), + I1 => \core_status_regs[2]\(1), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[1]\(1), + I4 => \data_sync_reg[2][34]_0\, + I5 => \core_status_regs[0]\(1), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[7]\(1), + I1 => \core_status_regs[6]\(1), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[5]\(1), + I4 => \data_sync_reg[2][34]_0\, + I5 => \core_status_regs[4]\(1), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888888BBB888B8" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_2_n_0\, + I1 => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\, + I2 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(14), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(14), + I5 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(14), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(14), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(14), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(14), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[3]\(2), + I1 => \core_status_regs[2]\(2), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[1]\(2), + I4 => \data_sync_reg[2][34]_0\, + I5 => \core_status_regs[0]\(2), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[7]\(2), + I1 => \core_status_regs[6]\(2), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[5]\(2), + I4 => \data_sync_reg[2][34]_0\, + I5 => \core_status_regs[4]\(2), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888888BBB888B8" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_2_n_0\, + I1 => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\, + I2 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(15), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(15), + I5 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(15), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(15), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(15), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(15), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[3]\(3), + I1 => \core_status_regs[2]\(3), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[1]\(3), + I4 => \data_sync_reg[2][34]_0\, + I5 => \core_status_regs[0]\(3), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[7]\(3), + I1 => \core_status_regs[6]\(3), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[5]\(3), + I4 => \data_sync_reg[2][34]_0\, + I5 => \core_status_regs[4]\(3), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[33].GEN_MUX_REG.data_out_reg_reg[33]_0\(26), + I1 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(16), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(16), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(77), + I1 => core_regs(55), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(33), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(11), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(16), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(16), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(16), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(16), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(165), + I1 => core_regs(143), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(121), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(99), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888888BBB888B8" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_2_n_0\, + I1 => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\, + I2 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(17), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(17), + I5 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(17), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(17), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(17), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(17), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(78), + I1 => core_regs(56), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(34), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(12), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(166), + I1 => core_regs(144), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(122), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(100), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888888BBB888B8" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_2_n_0\, + I1 => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\, + I2 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(18), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(18), + I5 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(18), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(18), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(18), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(18), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(79), + I1 => core_regs(57), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(35), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(13), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(167), + I1 => core_regs(145), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(123), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(101), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888888BBB888B8" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_2_n_0\, + I1 => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\, + I2 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(19), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(19), + I5 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(19), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(19), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(19), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(19), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(80), + I1 => core_regs(58), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(36), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(14), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(168), + I1 => core_regs(146), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(124), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(102), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[33].GEN_MUX_REG.data_out_reg_reg[33]_0\(26), + I1 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(1), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(1), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(66), + I1 => core_regs(44), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(22), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(0), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(1), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(1), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(1), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(1), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(154), + I1 => core_regs(132), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(110), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(88), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888888BBB888B8" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_2_n_0\, + I1 => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\, + I2 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(20), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(20), + I5 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(20), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(20), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(20), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(20), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(81), + I1 => core_regs(59), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(37), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(15), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(169), + I1 => core_regs(147), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(125), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(103), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888888BBB888B8" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_2_n_0\, + I1 => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\, + I2 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(21), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(21), + I5 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(21), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(21), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(21), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(21), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(82), + I1 => core_regs(60), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(38), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(16), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(170), + I1 => core_regs(148), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(126), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(104), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888888BBB888B8" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_2_n_0\, + I1 => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\, + I2 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(22), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(22), + I5 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(22), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(22), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(22), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(22), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(83), + I1 => core_regs(61), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(39), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(17), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(171), + I1 => core_regs(149), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(127), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(105), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888888BBB888B8" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_2_n_0\, + I1 => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\, + I2 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(23), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(23), + I5 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(23), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(23), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(23), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(23), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(84), + I1 => core_regs(62), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(40), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(18), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(172), + I1 => core_regs(150), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(128), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(106), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888888BBB888B8" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_2_n_0\, + I1 => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\, + I2 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(24), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(24), + I5 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(24), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(24), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(24), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(24), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(85), + I1 => core_regs(63), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(41), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(19), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(173), + I1 => core_regs(151), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(129), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(107), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[33].GEN_MUX_REG.data_out_reg_reg[33]_0\(26), + I1 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(25), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(25), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(86), + I1 => core_regs(64), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(42), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(20), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(25), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(25), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(25), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(25), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(174), + I1 => core_regs(152), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(130), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(108), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[33].GEN_MUX_REG.data_out_reg_reg[33]_0\(26), + I1 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(26), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(26), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(87), + I1 => core_regs(65), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(43), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(21), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(26), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(26), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(26), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(26), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(175), + I1 => core_regs(153), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(131), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(109), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888888BBB888B8" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_2_n_0\, + I1 => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\, + I2 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(27), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(27), + I5 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(27), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(27), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(27), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(27), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[3]\(4), + I1 => \core_status_regs[2]\(4), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[1]\(4), + I4 => \data_sync_reg[2][34]_0\, + I5 => \core_status_regs[0]\(4), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[7]\(4), + I1 => \core_status_regs[6]\(4), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[5]\(4), + I4 => \data_sync_reg[2][34]_0\, + I5 => \core_status_regs[4]\(4), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888888BBB888B8" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_2_n_0\, + I1 => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\, + I2 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(28), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(28), + I5 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(28), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(28), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(28), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(28), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[3]\(5), + I1 => \core_status_regs[2]\(5), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[1]\(5), + I4 => \data_sync_reg[2][34]_0\, + I5 => \core_status_regs[0]\(5), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[7]\(5), + I1 => \core_status_regs[6]\(5), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[5]\(5), + I4 => \data_sync_reg[2][34]_0\, + I5 => \core_status_regs[4]\(5), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888888BBB888B8" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_2_n_0\, + I1 => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\, + I2 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(29), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(29), + I5 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(29), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(29), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(29), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(29), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[3]\(6), + I1 => \core_status_regs[2]\(6), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[1]\(6), + I4 => \data_sync_reg[2][34]_0\, + I5 => \core_status_regs[0]\(6), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[7]\(6), + I1 => \core_status_regs[6]\(6), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[5]\(6), + I4 => \data_sync_reg[2][34]_0\, + I5 => \core_status_regs[4]\(6), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888888BBB888B8" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_2_n_0\, + I1 => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\, + I2 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(2), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(2), + I5 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(2), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(2), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(2), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(2), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(67), + I1 => core_regs(45), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(23), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(1), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(155), + I1 => core_regs(133), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(111), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(89), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888888BBB888B8" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_2_n_0\, + I1 => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\, + I2 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(30), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(30), + I5 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(30), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(30), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(30), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(30), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[3]\(7), + I1 => \core_status_regs[2]\(7), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[1]\(7), + I4 => \data_sync_reg[2][34]_0\, + I5 => \core_status_regs[0]\(7), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[7]\(7), + I1 => \core_status_regs[6]\(7), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[5]\(7), + I4 => \data_sync_reg[2][34]_0\, + I5 => \core_status_regs[4]\(7), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888888BBB888B8" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_2_n_0\, + I1 => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\, + I2 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(31), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(31), + I5 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(31), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(31), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(31), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(31), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[3]\(8), + I1 => \core_status_regs[2]\(8), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[1]\(8), + I4 => \data_sync_reg[2][34]_0\, + I5 => \core_status_regs[0]\(8), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[7]\(8), + I1 => \core_status_regs[6]\(8), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[5]\(8), + I4 => \data_sync_reg[2][34]_0\, + I5 => \core_status_regs[4]\(8), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"30BB3088" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[33].GEN_MUX_REG.data_out_reg_reg[33]_0\(26), + I1 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(3), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(3), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(68), + I1 => core_regs(46), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(24), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(2), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(3), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(3), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(3), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(3), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(156), + I1 => core_regs(134), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(112), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(90), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888888BBB888B8" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_2_n_0\, + I1 => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\, + I2 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(4), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(4), + I5 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(4), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(4), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(4), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(4), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(69), + I1 => core_regs(47), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(25), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(3), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(157), + I1 => core_regs(135), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(113), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(91), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888888BBB888B8" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_2_n_0\, + I1 => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\, + I2 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(5), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(5), + I5 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(5), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(5), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(5), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(5), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(70), + I1 => core_regs(48), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(26), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(4), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(158), + I1 => core_regs(136), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(114), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(92), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888888BBB888B8" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_2_n_0\, + I1 => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\, + I2 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(6), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(6), + I5 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(6), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(6), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(6), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(6), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(71), + I1 => core_regs(49), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(27), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(5), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(159), + I1 => core_regs(137), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(115), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(93), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888888BBB888B8" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_2_n_0\, + I1 => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\, + I2 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(7), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(7), + I5 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(7), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(7), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(7), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(7), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(72), + I1 => core_regs(50), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(28), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(6), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(160), + I1 => core_regs(138), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(116), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(94), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888888BBB888B8" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_2_n_0\, + I1 => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\, + I2 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(8), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(8), + I5 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(8), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(8), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(8), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(8), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(73), + I1 => core_regs(51), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(29), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(7), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(161), + I1 => core_regs(139), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(117), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(95), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888888BBB888B8" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_2_n_0\, + I1 => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\, + I2 => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31]_20\(9), + I3 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32]_19\(9), + I5 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38]_15\(9), + I1 => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37]_16\(9), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36]_17\(9), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35]_18\(9), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(74), + I1 => core_regs(52), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(30), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(8), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(162), + I1 => core_regs(140), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(118), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(96), + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][0]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(0), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][0]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][0]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][0]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][0]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][0]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(10), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][10]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][10]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][10]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(11), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][11]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][11]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][11]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(12), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][12]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][12]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][12]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(13), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][13]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][13]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][13]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(14), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][14]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][14]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][14]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(15), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][15]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][15]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][15]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][16]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(16), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][16]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][16]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][16]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][16]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][16]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(17), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][17]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][17]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][17]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(18), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][18]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][18]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][18]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(19), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][19]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][19]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][19]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][1]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(1), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][1]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][1]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][1]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][1]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][1]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(20), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][20]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][20]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][20]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(21), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][21]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][21]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][21]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(22), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][22]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][22]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][22]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(23), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][23]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][23]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][23]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(24), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][24]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][24]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][24]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][25]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(25), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][25]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][25]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][25]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][25]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][25]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][26]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(26), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][26]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][26]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][26]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][26]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][26]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(27), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][27]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][27]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][27]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(28), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][28]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][28]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][28]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(29), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][29]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][29]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][29]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(2), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][2]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][2]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][2]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(30), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][30]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][30]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][30]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(31), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][31]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][31]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][31]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][3]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(3), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][3]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][3]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][3]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][3]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][3]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(4), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][4]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][4]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][4]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(5), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][5]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][5]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][5]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(6), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][6]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][6]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][6]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(7), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][7]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][7]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][7]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(8), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][8]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][8]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][8]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_21\(9), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][9]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg[3][9]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][9]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_148\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(0), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_138\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(10), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_137\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(11), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_136\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(12), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_135\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(13), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_134\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(14), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_133\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(15), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_132\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(16), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_131\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(17), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_130\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(18), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_129\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(19), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_147\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(1), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_128\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(20), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_127\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(21), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_126\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(22), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_125\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(23), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_124\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(24), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_123\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(25), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_122\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(26), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_121\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(27), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_120\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(28), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_119\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(29), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_146\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(2), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_118\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(30), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_117\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(31), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_145\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(3), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_144\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(4), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_143\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(5), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_142\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(6), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_141\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(7), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_140\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(8), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_139\, + Q => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(9), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_116\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(0), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_106\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(10), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_105\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(11), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_104\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(12), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_103\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(13), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_102\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(14), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_101\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(15), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_100\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(16), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_99\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(17), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_98\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(18), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_97\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(19), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_115\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(1), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_96\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(20), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_95\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(21), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_94\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(22), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_93\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(23), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_92\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(24), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_91\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(25), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_90\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(26), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_89\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(27), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_88\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(28), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_87\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(29), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_114\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(2), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_86\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(30), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_85\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(31), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_113\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(3), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_112\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(4), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_111\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(5), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_110\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(6), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_109\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(7), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_108\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(8), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_107\, + Q => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(9), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_84\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(0), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_74\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(10), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_73\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(11), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_72\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(12), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_71\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(13), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_70\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(14), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_69\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(15), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_68\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(16), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_67\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(17), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_66\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(18), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_65\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(19), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_83\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(1), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_64\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(20), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_63\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(21), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_62\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(22), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_61\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(23), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_60\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(24), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_59\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(25), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_58\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(26), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_57\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(27), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_56\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(28), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_55\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(29), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_82\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(2), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_54\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(30), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_53\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(31), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_81\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(3), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_80\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(4), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_79\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(5), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_78\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(6), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_77\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(7), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_76\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(8), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_75\, + Q => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(9), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][0]\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(0), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][10]\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(10), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][11]\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(11), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][12]\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(12), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_52\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(13), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_51\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(14), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_50\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(15), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][16]\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(16), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][17]\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(17), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][18]\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(18), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][19]\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(19), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \intr_status_int_reg[12]\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(1), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][20]\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(20), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][21]\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(21), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][22]\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(22), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][23]\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(23), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][24]\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(24), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][25]\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(25), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][26]\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(26), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][27]\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(27), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(28), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_49\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(29), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][2]\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(2), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_48\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(30), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_47\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(31), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][3]\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(3), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][4]\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(4), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][5]\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(5), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][6]\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(6), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][7]\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(7), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][8]\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(8), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][9]\, + Q => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(9), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][0]\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(0), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_46\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(10), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_45\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(11), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_44\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(12), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_43\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(13), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_42\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(14), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_41\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(15), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_40\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(16), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_39\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(17), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_38\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(18), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_37\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(19), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][1]\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(1), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_36\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(20), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_35\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(21), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_34\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(22), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_33\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(23), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_32\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(24), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_31\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(25), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_30\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(26), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_29\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(27), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_28\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(28), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_27\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(29), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][2]\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(2), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_26\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(30), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_25\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(31), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][3]\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(3), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][4]\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(4), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][5]\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(5), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6]\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(6), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][7]\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(7), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][8]\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(8), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9]\, + Q => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(9), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][0]\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(0), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][10]\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(10), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][11]\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(11), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][12]\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(12), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_24\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(13), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_23\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(14), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_22\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(15), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][16]\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(16), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][17]\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(17), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][18]\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(18), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][19]\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(19), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][1]\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(1), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][20]\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(20), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][21]\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(21), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][22]\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(22), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][23]\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(23), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][24]\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(24), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][25]\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(25), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][26]\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(26), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][27]\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(27), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(28), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_21\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(29), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][2]\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(2), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_20\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(30), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_19\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(31), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][3]\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(3), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][4]\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(4), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][5]\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(5), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][6]\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(6), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][7]\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(7), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][8]\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(8), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][9]\, + Q => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(9), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][0]\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(0), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][10]\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(10), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][11]\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(11), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][12]\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(12), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_18\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(13), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_17\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(14), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_16\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(15), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][16]\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(16), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][17]\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(17), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][18]\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(18), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][19]\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(19), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][1]\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(1), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][20]\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(20), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][21]\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(21), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][22]\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(22), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][23]\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(23), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][24]\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(24), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][25]\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(25), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][26]\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(26), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][27]\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(27), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(28), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_15\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(29), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][2]\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(2), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_14\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(30), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_13\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(31), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][3]\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(3), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][4]\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(4), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][5]\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(5), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][6]\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(6), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][7]\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(7), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][8]\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(8), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][9]\, + Q => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(9), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][0]\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(0), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][10]\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(10), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][11]\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(11), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][12]\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(12), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_12\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(13), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_11\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(14), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_10\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(15), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][16]\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(16), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][17]\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(17), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][18]\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(18), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][19]\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(19), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][1]\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(1), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][20]\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(20), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][21]\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(21), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][22]\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(22), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][23]\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(23), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][24]\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(24), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][25]\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(25), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][26]\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(26), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][27]\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(27), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(28), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_9\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(29), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][2]\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(2), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_8\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(30), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_7\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(31), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][3]\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(3), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][4]\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(4), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][5]\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(5), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][6]\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(6), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][7]\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(7), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][8]\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(8), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][9]\, + Q => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(9), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][0]\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(0), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][10]\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(10), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][11]\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(11), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][12]\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(12), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_6\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(13), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_5\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(14), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_4\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(15), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][16]\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(16), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][17]\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(17), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][18]\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(18), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][19]\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(19), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][1]\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(1), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][20]\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(20), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][21]\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(21), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][22]\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(22), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][23]\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(23), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][24]\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(24), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][25]\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(25), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][26]\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(26), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][27]\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(27), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][28]\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(28), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_3\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(29), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][2]\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(2), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_2\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(30), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync_reg[2][34]_1\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(31), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][3]\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(3), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][4]\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(4), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][5]\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(5), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][6]\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(6), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][7]\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(7), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][8]\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(8), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][9]\, + Q => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(9), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => Q(0), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(0), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => Q(10), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(10), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => Q(11), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(11), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => Q(12), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(12), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \time_status_regs[28]\(0), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(13), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \time_status_regs[28]\(1), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(14), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \time_status_regs[28]\(2), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(15), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => Q(13), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(16), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => Q(14), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(17), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => Q(15), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(18), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => Q(16), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(19), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => Q(1), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(1), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => Q(17), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(20), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => Q(18), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(21), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => Q(19), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(22), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => Q(20), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(23), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => Q(21), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(24), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => Q(22), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(25), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => Q(23), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(26), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => Q(24), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(27), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => Q(25), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(28), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \time_status_regs[28]\(3), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(29), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => Q(2), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(2), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \time_status_regs[28]\(4), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(30), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \time_status_regs[28]\(5), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(31), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => Q(3), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(3), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => Q(4), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(4), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => Q(5), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(5), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => Q(6), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(6), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => Q(7), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(7), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => Q(8), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(8), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => Q(9), + Q => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(9), + R => ipif_Addr(0) + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(0), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(0), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(0), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(0), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][0]\(0), + I1 => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][0]\(0), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][0]\(0), + I4 => \data_sync_reg[2][34]_0\, + I5 => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][0]\(0), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(0), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(0), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(0), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(0), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][0]\(0), + I1 => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][0]\(0), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][0]\(0), + I4 => \data_sync_reg[2][34]_0\, + I5 => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][0]\(0), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(10), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(10), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(10), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(10), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(251), + I1 => core_regs(229), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(207), + I4 => \data_sync_reg[2][34]_222\, + I5 => core_regs(185), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(10), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(10), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(10), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(10), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(339), + I1 => core_regs(317), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(295), + I4 => \data_sync_reg[2][34]_222\, + I5 => core_regs(273), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(11), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(11), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(11), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(11), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(252), + I1 => core_regs(230), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(208), + I4 => \data_sync_reg[2][34]_222\, + I5 => core_regs(186), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(11), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(11), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(11), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(11), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(340), + I1 => core_regs(318), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(296), + I4 => \data_sync_reg[2][34]_222\, + I5 => core_regs(274), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(12), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(12), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(12), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(12), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[11]\(0), + I1 => \core_status_regs[10]\(0), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[9]\(0), + I4 => \data_sync_reg[2][34]_222\, + I5 => \core_status_regs[8]\(0), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(12), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(12), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(12), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(12), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[15]\(0), + I1 => \core_status_regs[14]\(0), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[13]\(0), + I4 => \data_sync_reg[2][34]_222\, + I5 => \core_status_regs[12]\(0), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(13), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(13), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(13), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(13), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[11]\(1), + I1 => \core_status_regs[10]\(1), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[9]\(1), + I4 => \data_sync_reg[2][34]_222\, + I5 => \core_status_regs[8]\(1), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(13), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(13), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(13), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(13), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[15]\(1), + I1 => \core_status_regs[14]\(1), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[13]\(1), + I4 => \data_sync_reg[2][34]_222\, + I5 => \core_status_regs[12]\(1), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(14), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(14), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(14), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(14), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[11]\(2), + I1 => \core_status_regs[10]\(2), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[9]\(2), + I4 => \data_sync_reg[2][34]_222\, + I5 => \core_status_regs[8]\(2), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(14), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(14), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(14), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(14), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[15]\(2), + I1 => \core_status_regs[14]\(2), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[13]\(2), + I4 => \data_sync_reg[2][34]_222\, + I5 => \core_status_regs[12]\(2), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(15), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(15), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(15), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(15), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[11]\(3), + I1 => \core_status_regs[10]\(3), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[9]\(3), + I4 => \data_sync_reg[2][34]_222\, + I5 => \core_status_regs[8]\(3), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(15), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(15), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(15), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(15), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[15]\(3), + I1 => \core_status_regs[14]\(3), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[13]\(3), + I4 => \data_sync_reg[2][34]_222\, + I5 => \core_status_regs[12]\(3), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(16), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(16), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(16), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(16), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(253), + I1 => core_regs(231), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(209), + I4 => \data_sync_reg[2][34]_222\, + I5 => core_regs(187), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(16), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(16), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(16), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(16), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(341), + I1 => core_regs(319), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(297), + I4 => \data_sync_reg[2][34]_222\, + I5 => core_regs(275), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(17), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(17), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(17), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(17), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(254), + I1 => core_regs(232), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(210), + I4 => \data_sync_reg[2][34]_222\, + I5 => core_regs(188), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(17), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(17), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(17), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(17), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(342), + I1 => core_regs(320), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(298), + I4 => \data_sync_reg[2][34]_222\, + I5 => core_regs(276), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(18), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(18), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(18), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(18), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(255), + I1 => core_regs(233), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(211), + I4 => \data_sync_reg[2][34]_222\, + I5 => core_regs(189), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(18), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(18), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(18), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(18), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(343), + I1 => core_regs(321), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(299), + I4 => \data_sync_reg[2][34]_222\, + I5 => core_regs(277), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(19), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(19), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(19), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(19), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(256), + I1 => core_regs(234), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(212), + I4 => \data_sync_reg[2][34]_222\, + I5 => core_regs(190), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(19), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(19), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(19), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(19), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(344), + I1 => core_regs(322), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(300), + I4 => \data_sync_reg[2][34]_222\, + I5 => core_regs(278), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(1), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(1), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(1), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(1), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(242), + I1 => core_regs(220), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(198), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(176), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(1), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(1), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(1), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(1), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(330), + I1 => core_regs(308), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(286), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(264), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(20), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(20), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(20), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(20), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(257), + I1 => core_regs(235), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(213), + I4 => \data_sync_reg[2][34]_222\, + I5 => core_regs(191), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(20), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(20), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(20), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(20), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(345), + I1 => core_regs(323), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(301), + I4 => \data_sync_reg[2][34]_222\, + I5 => core_regs(279), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(21), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(21), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(21), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(21), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(258), + I1 => core_regs(236), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(214), + I4 => \data_sync_reg[2][34]_222\, + I5 => core_regs(192), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(21), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(21), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(21), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(21), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(346), + I1 => core_regs(324), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(302), + I4 => \data_sync_reg[2][34]_222\, + I5 => core_regs(280), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(22), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(22), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(22), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(22), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(259), + I1 => core_regs(237), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(215), + I4 => \data_sync_reg[2][34]_222\, + I5 => core_regs(193), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(22), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(22), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(22), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(22), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(347), + I1 => core_regs(325), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(303), + I4 => \data_sync_reg[2][34]_222\, + I5 => core_regs(281), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(23), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(23), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(23), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(23), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(260), + I1 => core_regs(238), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(216), + I4 => \data_sync_reg[2][34]_222\, + I5 => core_regs(194), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(23), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(23), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(23), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(23), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(348), + I1 => core_regs(326), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(304), + I4 => \data_sync_reg[2][34]_222\, + I5 => core_regs(282), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(24), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(24), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(24), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(24), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(261), + I1 => core_regs(239), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(217), + I4 => \data_sync_reg[2][34]_222\, + I5 => core_regs(195), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(24), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(24), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(24), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(24), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(349), + I1 => core_regs(327), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(305), + I4 => \data_sync_reg[2][34]_222\, + I5 => core_regs(283), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(25), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(25), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(25), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(25), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(262), + I1 => core_regs(240), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(218), + I4 => \data_sync_reg[2][34]_222\, + I5 => core_regs(196), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(25), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(25), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(25), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(25), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(350), + I1 => core_regs(328), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(306), + I4 => \data_sync_reg[2][34]_222\, + I5 => core_regs(284), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(26), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(26), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(26), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(26), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(263), + I1 => core_regs(241), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(219), + I4 => \data_sync_reg[2][34]_222\, + I5 => core_regs(197), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(26), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(26), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(26), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(26), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(351), + I1 => core_regs(329), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(307), + I4 => \data_sync_reg[2][34]_222\, + I5 => core_regs(285), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(27), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(27), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(27), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(27), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[11]\(4), + I1 => \core_status_regs[10]\(4), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[9]\(4), + I4 => \data_sync_reg[2][34]_222\, + I5 => \core_status_regs[8]\(4), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(27), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(27), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(27), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(27), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[15]\(4), + I1 => \core_status_regs[14]\(4), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[13]\(4), + I4 => \data_sync_reg[2][34]_222\, + I5 => \core_status_regs[12]\(4), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(28), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(28), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(28), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(28), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[11]\(5), + I1 => \core_status_regs[10]\(5), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[9]\(5), + I4 => \data_sync_reg[2][34]_222\, + I5 => \core_status_regs[8]\(5), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(28), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(28), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(28), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(28), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[15]\(5), + I1 => \core_status_regs[14]\(5), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[13]\(5), + I4 => \data_sync_reg[2][34]_222\, + I5 => \core_status_regs[12]\(5), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(29), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(29), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(29), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(29), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[11]\(6), + I1 => \core_status_regs[10]\(6), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[9]\(6), + I4 => \data_sync_reg[2][34]_222\, + I5 => \core_status_regs[8]\(6), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(29), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(29), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(29), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(29), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[15]\(6), + I1 => \core_status_regs[14]\(6), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[13]\(6), + I4 => \data_sync_reg[2][34]_222\, + I5 => \core_status_regs[12]\(6), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(2), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(2), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(2), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(2), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(243), + I1 => core_regs(221), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(199), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(177), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(2), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(2), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(2), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(2), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(331), + I1 => core_regs(309), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(287), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(265), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(30), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(30), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(30), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(30), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[11]\(7), + I1 => \core_status_regs[10]\(7), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[9]\(7), + I4 => \data_sync_reg[2][34]_222\, + I5 => \core_status_regs[8]\(7), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(30), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(30), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(30), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(30), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[15]\(7), + I1 => \core_status_regs[14]\(7), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[13]\(7), + I4 => \data_sync_reg[2][34]_222\, + I5 => \core_status_regs[12]\(7), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(31), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(31), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(31), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(31), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[11]\(8), + I1 => \core_status_regs[10]\(8), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[9]\(8), + I4 => \data_sync_reg[2][34]_222\, + I5 => \core_status_regs[8]\(8), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(31), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(31), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(31), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(31), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \core_status_regs[15]\(8), + I1 => \core_status_regs[14]\(8), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => \core_status_regs[13]\(8), + I4 => \data_sync_reg[2][34]_222\, + I5 => \core_status_regs[12]\(8), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(3), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(3), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(3), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(3), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(244), + I1 => core_regs(222), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(200), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(178), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(3), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(3), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(3), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(3), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(332), + I1 => core_regs(310), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(288), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(266), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(4), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(4), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(4), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(4), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(245), + I1 => core_regs(223), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(201), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(179), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(4), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(4), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(4), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(4), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(333), + I1 => core_regs(311), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(289), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(267), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(5), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(5), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(5), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(5), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(246), + I1 => core_regs(224), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(202), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(180), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(5), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(5), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(5), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(5), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(334), + I1 => core_regs(312), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(290), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(268), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(6), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(6), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(6), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(6), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(247), + I1 => core_regs(225), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(203), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(181), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(6), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(6), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(6), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(6), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(335), + I1 => core_regs(313), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(291), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(269), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(7), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(7), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(7), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(7), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(248), + I1 => core_regs(226), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(204), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(182), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(7), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(7), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(7), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(7), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(336), + I1 => core_regs(314), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(292), + I4 => \data_sync_reg[2][34]_0\, + I5 => core_regs(270), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(8), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(8), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(8), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(8), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(249), + I1 => core_regs(227), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(205), + I4 => \data_sync_reg[2][34]_222\, + I5 => core_regs(183), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(8), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(8), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(8), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(8), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(337), + I1 => core_regs(315), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(293), + I4 => \data_sync_reg[2][34]_222\, + I5 => core_regs(271), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42]_10\(9), + I1 => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41]_11\(9), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40]_12\(9), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39]_13\(9), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(250), + I1 => core_regs(228), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(206), + I4 => \data_sync_reg[2][34]_222\, + I5 => core_regs(184), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_2__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46]_6\(9), + I1 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45]_7\(9), + I2 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I3 => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44]_8\(9), + I4 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I5 => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43]_9\(9), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_3_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AFA0CFCFAFA0C0C0" + ) + port map ( + I0 => core_regs(338), + I1 => core_regs(316), + I2 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I3 => core_regs(294), + I4 => \data_sync_reg[2][34]_222\, + I5 => core_regs(272), + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_3__0_n_0\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][0]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(0), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][0]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][0]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][0]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][0]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][0]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][10]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(10), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][10]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][10]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][10]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][10]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][10]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][11]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(11), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][11]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][11]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][11]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][11]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][11]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][12]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(12), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][12]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][12]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][12]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][12]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][12]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][13]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(13), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][13]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][13]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][13]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][13]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][13]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][14]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(14), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][14]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][14]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][14]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][14]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][14]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][15]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(15), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][15]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][15]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][15]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][15]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][15]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][16]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(16), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][16]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][16]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][16]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][16]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][16]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][17]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(17), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][17]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][17]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][17]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][17]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][17]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][18]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(18), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][18]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][18]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][18]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][18]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][18]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][19]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(19), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][19]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][19]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][19]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][19]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][19]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][1]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(1), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][1]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][1]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][1]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][1]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][1]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][20]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(20), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][20]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][20]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][20]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][20]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][20]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][21]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(21), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][21]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][21]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][21]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][21]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][21]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][22]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(22), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][22]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][22]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][22]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][22]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][22]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][23]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(23), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][23]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][23]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][23]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][23]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][23]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][24]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(24), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][24]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][24]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][24]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][24]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][24]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][25]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(25), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][25]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][25]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][25]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][25]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][25]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][26]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(26), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][26]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][26]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][26]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][26]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][26]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][27]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(27), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][27]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][27]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][27]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][27]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][27]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][28]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(28), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][28]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][28]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][28]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][28]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][28]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][29]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(29), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][29]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][29]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][29]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][29]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][29]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][2]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(2), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][2]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][2]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][2]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][2]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][2]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][30]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(30), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][30]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][30]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][30]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][30]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][30]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][31]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(31), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][31]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][31]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][31]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][31]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][31]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][3]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(3), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][3]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][3]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][3]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][3]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][3]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][4]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(4), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][4]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][4]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][4]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][4]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][4]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][5]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(5), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][5]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][5]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][5]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][5]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][5]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][6]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(6), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][6]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][6]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][6]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][6]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][6]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][7]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(7), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][7]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][7]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][7]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][7]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][7]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][8]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(8), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][8]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][8]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][8]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][8]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][8]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][9]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_14\(9), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][9]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_2_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_3_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][9]_i_1_n_0\, + S => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][9]_i_1__0\: unisim.vcomponents.MUXF7 + port map ( + I0 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_2__0_n_0\, + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg[4][9]_i_3__0_n_0\, + O => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][9]_0\, + S => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(0), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(0), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(0), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][0]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][10]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(10), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(10), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(10), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][10]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][11]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(11), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(11), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(11), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][11]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][12]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(12), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(12), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(12), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][12]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][13]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(13), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(13), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(13), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][13]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][14]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(14), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(14), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(14), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][14]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][15]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(15), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(15), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(15), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][15]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][16]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(16), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(16), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(16), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][16]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][17]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(17), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(17), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(17), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][17]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][18]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(18), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(18), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(18), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][18]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][19]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(19), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(19), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(19), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][19]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(1), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(1), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(1), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][1]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][20]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(20), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(20), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(20), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][20]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][21]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(21), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(21), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(21), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][21]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][22]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(22), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(22), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(22), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][22]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][23]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(23), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(23), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(23), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][23]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][24]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(24), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(24), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(24), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][24]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][25]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(25), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(25), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(25), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][25]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][26]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(26), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(26), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(26), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][26]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][27]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(27), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(27), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(27), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][27]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][28]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(28), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(28), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(28), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][28]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][29]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(29), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(29), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(29), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][29]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(2), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(2), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(2), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][2]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][30]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(30), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(30), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(30), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][30]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"EA" + ) + port map ( + I0 => \GEN_SEL_DELAY[3].sel_int_reg[3][0]\, + I1 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I2 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => \GEN_SEL_DELAY[2].sel_int_reg_n_0_[2][0]\, + I1 => \GEN_SEL_DELAY[1].sel_int_reg_n_0_[1][0]\, + I2 => \data_sync_reg[2][34]_0\, + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(31), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(31), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(31), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(3), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(3), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(3), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][3]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(4), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(4), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(4), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][4]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(5), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(5), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(5), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][5]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(6), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(6), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(6), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][6]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(7), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(7), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(7), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][7]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][8]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(8), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(8), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(8), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][8]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][9]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48]_3\(9), + I1 => \GEN_SEL_DELAY[1].sel_int_reg[1][0]_rep_n_0\, + I2 => \GEN_TREE.GEN_BRANCH[49].GEN_MUX_REG.data_out_reg_reg[49]_2\(9), + I3 => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_rep_n_0\, + I4 => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47]_4\(9), + O => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][9]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][0]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(0), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][10]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(10), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][11]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(11), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][12]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(12), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][13]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(13), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][14]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(14), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][15]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(15), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][16]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(16), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][17]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(17), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][18]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(18), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][19]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(19), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][1]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(1), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][20]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(20), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][21]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(21), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][22]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(22), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][23]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(23), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][24]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(24), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][25]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(25), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][26]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(26), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][27]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(27), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][28]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(28), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][29]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(29), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][2]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(2), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][30]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(30), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_2_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(31), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][3]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(3), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][4]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(4), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][5]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(5), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][6]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(6), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][7]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(7), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][8]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(8), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][9]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_5\(9), + R => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg[5][31]_i_1_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_tc_1_0_mux_tree__parameterized0\ is + port ( + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0\ : out STD_LOGIC; + core_data : out STD_LOGIC_VECTOR ( 31 downto 0 ); + ipif_Addr : in STD_LOGIC_VECTOR ( 0 to 0 ); + vid_aclk : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ : in STD_LOGIC; + \core_status_regs[16]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \core_control_regs[16]\ : in STD_LOGIC_VECTOR ( 22 downto 0 ); + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_0\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_1\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_2\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_3\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_4\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_5\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_6\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_7\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_8\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_9\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_10\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_11\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_12\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_13\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_14\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_15\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_16\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_17\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_18\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_19\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_20\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_21\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_22\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_23\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_24\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_25\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_26\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_27\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_28\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_29\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_30\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_31\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_32\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_33\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_34\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_35\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_36\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_37\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_38\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_39\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_40\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_41\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_42\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_43\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_44\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_45\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_46\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_47\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_48\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_49\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_50\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_51\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_52\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_53\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_54\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_55\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_56\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_57\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_58\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_59\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_60\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_61\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_62\ : in STD_LOGIC; + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_63\ : in STD_LOGIC; + \GEN_SEL_DELAY[4].sel_int_reg[4][0]\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_tc_1_0_mux_tree__parameterized0\ : entity is "mux_tree"; +end \Arty_Z7_20_v_tc_1_0_mux_tree__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_v_tc_1_0_mux_tree__parameterized0\ is + signal \GEN_SEL_DELAY[3].sel_int_reg[3][1]_srl2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + attribute srl_bus_name : string; + attribute srl_bus_name of \GEN_SEL_DELAY[3].sel_int_reg[3][1]_srl2\ : label is "U0/U_VIDEO_CTRL/\AXI4_LITE_INTERFACE.CORE_MUX0/GEN_SEL_DELAY[3].sel_int_reg[3] "; + attribute srl_name : string; + attribute srl_name of \GEN_SEL_DELAY[3].sel_int_reg[3][1]_srl2\ : label is "U0/U_VIDEO_CTRL/\AXI4_LITE_INTERFACE.CORE_MUX0/GEN_SEL_DELAY[3].sel_int_reg[3][1]_srl2 "; +begin + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0\ <= \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\; +\AXI4_LITE_INTERFACE.ipif_RdData[0]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(0), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(0), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(0), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(0) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[10]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(10), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(10), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(10), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(10) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[11]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(11), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(11), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(11), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(11) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[12]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(12), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(12), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(12), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(12) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[13]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(13), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(13), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(13), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(13) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[14]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(14), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(14), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(14), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(14) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[15]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(15), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(15), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(15), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(15) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[16]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(16), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(16), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(16), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(16) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[17]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(17), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(17), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(17), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(17) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[18]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(18), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(18), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(18), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(18) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[19]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(19), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(19), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(19), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(19) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[1]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(1), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(1), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(1), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(1) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[20]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(20), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(20), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(20), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(20) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[21]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(21), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(21), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(21), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(21) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[22]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(22), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(22), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(22), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(22) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[23]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(23), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(23), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(23), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(23) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[24]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(24), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(24), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(24), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(24) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[25]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(25), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(25), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(25), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(25) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[26]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(26), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(26), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(26), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(26) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[27]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(27), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(27), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(27), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(27) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[28]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(28), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(28), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(28), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(28) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[29]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(29), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(29), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(29), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(29) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[2]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(2), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(2), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(2), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(2) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[30]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(30), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(30), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(30), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(30) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[31]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(31), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(31), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(31), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(31) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[3]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(3), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(3), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(3), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(3) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[4]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(4), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(4), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(4), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(4) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[5]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(5), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(5), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(5), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(5) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[6]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(6), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(6), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(6), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(6) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[7]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(7), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(7), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(7), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(7) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[8]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(8), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(8), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(8), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(8) + ); +\AXI4_LITE_INTERFACE.ipif_RdData[9]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0A0ACFC0" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(9), + I1 => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(9), + I2 => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + I3 => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(9), + I4 => \GEN_SEL_DELAY[4].sel_int_reg[4][0]\, + O => core_data(9) + ); +\GEN_SEL_DELAY[3].sel_int_reg[3][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[3].sel_int_reg[3][1]_srl2_n_0\, + Q => \^gen_tree.gen_branch[5].gen_mux_reg.data_out_reg_reg[5][31]_0\, + R => '0' + ); +\GEN_SEL_DELAY[3].sel_int_reg[3][1]_srl2\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '0', + A2 => '0', + A3 => '0', + CE => '1', + CLK => vid_aclk, + D => ipif_Addr(0), + Q => \GEN_SEL_DELAY[3].sel_int_reg[3][1]_srl2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_63\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(0), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_53\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(10), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_52\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(11), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_51\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(12), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_50\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(13), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_49\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(14), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_48\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(15), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_47\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(16), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_46\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(17), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_45\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(18), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_44\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(19), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_62\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(1), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_43\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(20), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_42\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(21), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_41\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(22), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_40\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(23), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_39\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(24), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_38\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(25), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_37\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(26), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_36\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(27), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_35\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(28), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_34\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(29), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_61\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(2), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_33\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(30), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_32\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(31), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_60\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(3), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_59\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(4), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_58\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(5), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_57\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(6), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_56\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(7), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_55\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(8), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_54\, + Q => \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3]_2\(9), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_31\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(0), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_21\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(10), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_20\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(11), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_19\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(12), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_18\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(13), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_17\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(14), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_16\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(15), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_15\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(16), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_14\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(17), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_13\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(18), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_12\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(19), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_30\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(1), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_11\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(20), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_10\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(21), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_9\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(22), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_8\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(23), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_7\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(24), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_6\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(25), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_5\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(26), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_4\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(27), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_3\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(28), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_2\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(29), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_29\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(2), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_1\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(30), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_0\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(31), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_28\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(3), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_27\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(4), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_26\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(5), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_25\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(6), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_24\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(7), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_23\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(8), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_SEL_DELAY[2].sel_int_reg[2][0]_22\, + Q => \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4]_1\(9), + R => '0' + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_control_regs[16]\(0), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(0), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_control_regs[16]\(10), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(10), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_control_regs[16]\(11), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(11), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_status_regs[16]\(0), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(12), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_status_regs[16]\(1), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(13), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_status_regs[16]\(2), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(14), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_status_regs[16]\(3), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(15), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_control_regs[16]\(12), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(16), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_control_regs[16]\(13), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(17), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_control_regs[16]\(14), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(18), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_control_regs[16]\(15), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(19), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_control_regs[16]\(1), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(1), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_control_regs[16]\(16), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(20), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_control_regs[16]\(17), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(21), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_control_regs[16]\(18), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(22), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_control_regs[16]\(19), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(23), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_control_regs[16]\(20), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(24), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_control_regs[16]\(21), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(25), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_control_regs[16]\(22), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(26), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_status_regs[16]\(4), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(27), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_status_regs[16]\(5), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(28), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_status_regs[16]\(6), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(29), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_control_regs[16]\(2), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(2), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_status_regs[16]\(7), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(30), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_status_regs[16]\(8), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(31), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_control_regs[16]\(3), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(3), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_control_regs[16]\(4), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(4), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_control_regs[16]\(5), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(5), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_control_regs[16]\(6), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(6), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_control_regs[16]\(7), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(7), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_control_regs[16]\(8), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(8), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +\GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \core_control_regs[16]\(9), + Q => \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5]_0\(9), + R => \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_tc_1_0_tc_detector is + port ( + det_ce : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 11 downto 0 ); + \time_status_regs[6]\ : out STD_LOGIC_VECTOR ( 23 downto 0 ); + \time_status_regs[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + vsync_lock_int : out STD_LOGIC; + hsync_lock_int : out STD_LOGIC; + active_video_lock_int : out STD_LOGIC; + reset : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); + intr_status_int17_out : out STD_LOGIC; + \time_status_regs_int_reg[0]\ : out STD_LOGIC_VECTOR ( 10 downto 0 ); + \intr_status_int_reg[11]\ : out STD_LOGIC; + all_lock_reg : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10]\ : out STD_LOGIC_VECTOR ( 10 downto 0 ); + \time_status_regs[8]\ : out STD_LOGIC_VECTOR ( 21 downto 0 ); + \time_status_regs[7]\ : out STD_LOGIC_VECTOR ( 23 downto 0 ); + \time_status_regs[9]\ : out STD_LOGIC_VECTOR ( 23 downto 0 ); + clk : in STD_LOGIC; + hsync_in : in STD_LOGIC; + active_video_in : in STD_LOGIC; + clken : in STD_LOGIC; + det_clken : in STD_LOGIC; + lost_lock : in STD_LOGIC; + resetn_out : in STD_LOGIC; + \genr_control_regs[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + core_d_out : in STD_LOGIC; + det_vblank_d : in STD_LOGIC; + det_active_video_d : in STD_LOGIC; + intc_if : in STD_LOGIC_VECTOR ( 0 to 0 ); + vblank_in : in STD_LOGIC; + all_lock : in STD_LOGIC; + all_lock_d0 : in STD_LOGIC; + vsync_in : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_tc_1_0_tc_detector : entity is "tc_detector"; +end Arty_Z7_20_v_tc_1_0_tc_detector; + +architecture STRUCTURE of Arty_Z7_20_v_tc_1_0_tc_detector is + signal \DET_HACTIVE.DET_AVIDEO_LOCK.det_active_video_lock_int_i_1_n_0\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count[0]_i_1_n_0\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count[0]_i_4_n_0\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count[0]_i_5_n_0\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count[0]_i_6_n_0\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count[0]_i_7_n_0\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count[4]_i_2_n_0\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count[4]_i_3_n_0\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count[4]_i_4_n_0\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count[4]_i_5_n_0\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count[8]_i_2_n_0\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count[8]_i_3_n_0\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count[8]_i_4_n_0\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count[8]_i_5_n_0\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \DET_HACTIVE.active_video_count_reg[0]_i_3_n_0\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count_reg[0]_i_3_n_1\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count_reg[0]_i_3_n_2\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count_reg[0]_i_3_n_3\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count_reg[0]_i_3_n_4\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count_reg[0]_i_3_n_5\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count_reg[0]_i_3_n_6\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count_reg[0]_i_3_n_7\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_count_reg[8]_i_1_n_7\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_d2_i_2_n_0\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_d_i_1_n_0\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_rose_i_1_n_0\ : STD_LOGIC; + signal \DET_HACTIVE.active_video_toggled_i_1_n_0\ : STD_LOGIC; + signal \DET_HACTIVE.det_active_video_pol_int_i_1_n_0\ : STD_LOGIC; + signal \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_lock_int_i_1_n_0\ : STD_LOGIC; + signal \DET_HSYNC.det_hsync_pol_int_i_1_n_0\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count[0]_i_1_n_0\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count[0]_i_2_n_0\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count[0]_i_4_n_0\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count[0]_i_5_n_0\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count[0]_i_6_n_0\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count[0]_i_7_n_0\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count[4]_i_2_n_0\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count[4]_i_3_n_0\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count[4]_i_4_n_0\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count[4]_i_5_n_0\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count[8]_i_2_n_0\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count[8]_i_3_n_0\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count[8]_i_4_n_0\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count[8]_i_5_n_0\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \DET_HSYNC.hsync_count_reg[0]_i_3_n_0\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count_reg[0]_i_3_n_1\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count_reg[0]_i_3_n_2\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count_reg[0]_i_3_n_3\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count_reg[0]_i_3_n_4\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count_reg[0]_i_3_n_5\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count_reg[0]_i_3_n_6\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count_reg[0]_i_3_n_7\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \DET_HSYNC.hsync_count_reg[8]_i_1_n_7\ : STD_LOGIC; + signal \DET_VACTIVE.active_line_d_i_1_n_0\ : STD_LOGIC; + signal \DET_VACTIVE.active_line_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0_vsync_lock_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_vsync_lock_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.GEN_DET_VSYNC_LOCK.vsync_delay[0]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.GEN_DET_VSYNC_LOCK.vsync_delay_reg_n_0_[0]\ : STD_LOGIC; + signal \DET_VSYNC.det_v0bp_start_int[0]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0bp_start_int[10]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0bp_start_int[1]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0bp_start_int[2]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0bp_start_int[3]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0bp_start_int[4]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0bp_start_int[5]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0bp_start_int[6]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0bp_start_int[7]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0bp_start_int[8]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0bp_start_int[9]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0sync_start_hori_int[0]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0sync_start_hori_int[10]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0sync_start_hori_int[11]_i_2_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0sync_start_hori_int[1]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0sync_start_hori_int[2]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0sync_start_hori_int[3]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0sync_start_hori_int[4]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0sync_start_hori_int[5]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0sync_start_hori_int[6]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0sync_start_hori_int[7]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0sync_start_hori_int[8]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0sync_start_hori_int[9]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0sync_start_int[0]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0sync_start_int[10]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0sync_start_int[1]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0sync_start_int[2]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0sync_start_int[3]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0sync_start_int[4]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0sync_start_int[5]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0sync_start_int[6]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0sync_start_int[7]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0sync_start_int[8]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_v0sync_start_int[9]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_vsync_pol_change_i_2_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_vsync_pol_change_i_3_n_0\ : STD_LOGIC; + signal \DET_VSYNC.det_vsync_pol_int_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.vsync_count[10]_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.vsync_count[10]_i_4_n_0\ : STD_LOGIC; + signal \DET_VSYNC.vsync_count_reg__0\ : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal \DET_VSYNC.vsync_d2_reg_n_0\ : STD_LOGIC; + signal \DET_VSYNC.vsync_d_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.vsync_d_reg_n_0\ : STD_LOGIC; + signal \DET_VSYNC.vsync_rose_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.vsync_toggled_i_1_n_0\ : STD_LOGIC; + signal \DET_VSYNC.vsync_toggled_reg_n_0\ : STD_LOGIC; + signal \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\ : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal L : STD_LOGIC_VECTOR ( 0 to 11 ); + signal \^q\ : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \_inferred__11/i__carry__0_n_0\ : STD_LOGIC; + signal \_inferred__11/i__carry__0_n_1\ : STD_LOGIC; + signal \_inferred__11/i__carry__0_n_2\ : STD_LOGIC; + signal \_inferred__11/i__carry__0_n_3\ : STD_LOGIC; + signal \_inferred__11/i__carry__1_n_1\ : STD_LOGIC; + signal \_inferred__11/i__carry__1_n_2\ : STD_LOGIC; + signal \_inferred__11/i__carry__1_n_3\ : STD_LOGIC; + signal \_inferred__11/i__carry_n_0\ : STD_LOGIC; + signal \_inferred__11/i__carry_n_1\ : STD_LOGIC; + signal \_inferred__11/i__carry_n_2\ : STD_LOGIC; + signal \_inferred__11/i__carry_n_3\ : STD_LOGIC; + signal \_inferred__8/i__carry__0_n_0\ : STD_LOGIC; + signal \_inferred__8/i__carry__0_n_1\ : STD_LOGIC; + signal \_inferred__8/i__carry__0_n_2\ : STD_LOGIC; + signal \_inferred__8/i__carry__0_n_3\ : STD_LOGIC; + signal \_inferred__8/i__carry__1_n_1\ : STD_LOGIC; + signal \_inferred__8/i__carry__1_n_2\ : STD_LOGIC; + signal \_inferred__8/i__carry__1_n_3\ : STD_LOGIC; + signal \_inferred__8/i__carry_n_0\ : STD_LOGIC; + signal \_inferred__8/i__carry_n_1\ : STD_LOGIC; + signal \_inferred__8/i__carry_n_2\ : STD_LOGIC; + signal \_inferred__8/i__carry_n_3\ : STD_LOGIC; + signal active_line : STD_LOGIC; + signal active_line_d : STD_LOGIC; + signal active_video_count : STD_LOGIC; + signal active_video_count_last : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal active_video_d : STD_LOGIC; + signal active_video_d2 : STD_LOGIC; + signal \^active_video_lock_int\ : STD_LOGIC; + signal active_video_rose : STD_LOGIC; + signal active_video_toggled : STD_LOGIC; + signal det_active_video_pol_change : STD_LOGIC; + signal \^det_ce\ : STD_LOGIC; + signal det_hactive_start_int : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal det_hactive_start_int_3 : STD_LOGIC; + signal det_hbp_start_int : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal det_hbp_start_int_9 : STD_LOGIC; + signal det_hbp_start_last : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal det_hfp_start_int : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal det_hfp_start_int_8 : STD_LOGIC; + signal det_hsync_pol_change : STD_LOGIC; + signal det_hsync_start_int : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal det_hsync_start_int_2 : STD_LOGIC; + signal det_hsync_start_last : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal det_htotal_int : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \det_htotal_int2[11]_i_2_n_0\ : STD_LOGIC; + signal \det_htotal_int2[11]_i_3_n_0\ : STD_LOGIC; + signal \det_htotal_int2[11]_i_4_n_0\ : STD_LOGIC; + signal \det_htotal_int2[4]_i_2_n_0\ : STD_LOGIC; + signal \det_htotal_int2[4]_i_3_n_0\ : STD_LOGIC; + signal \det_htotal_int2[4]_i_4_n_0\ : STD_LOGIC; + signal \det_htotal_int2[4]_i_5_n_0\ : STD_LOGIC; + signal \det_htotal_int2[8]_i_2_n_0\ : STD_LOGIC; + signal \det_htotal_int2[8]_i_3_n_0\ : STD_LOGIC; + signal \det_htotal_int2[8]_i_4_n_0\ : STD_LOGIC; + signal \det_htotal_int2[8]_i_5_n_0\ : STD_LOGIC; + signal \det_htotal_int2_reg[11]_i_1_n_2\ : STD_LOGIC; + signal \det_htotal_int2_reg[11]_i_1_n_3\ : STD_LOGIC; + signal \det_htotal_int2_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \det_htotal_int2_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \det_htotal_int2_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \det_htotal_int2_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \det_htotal_int2_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \det_htotal_int2_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \det_htotal_int2_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \det_htotal_int2_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \det_htotal_int[11]_i_1_n_0\ : STD_LOGIC; + signal det_v0_vsync_lock : STD_LOGIC; + signal \det_v0_vsync_lock__0\ : STD_LOGIC; + signal det_v0active_start_hori_int2 : STD_LOGIC_VECTOR ( 11 downto 1 ); + signal \det_v0active_start_hori_int2[0]_i_10_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[0]_i_11_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[0]_i_12_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[0]_i_13_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[0]_i_1_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[0]_i_4_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[0]_i_5_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[0]_i_6_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[0]_i_7_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[0]_i_8_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[0]_i_9_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[11]_i_2_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[11]_i_3_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[11]_i_4_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[11]_i_5_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[11]_i_6_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[11]_i_7_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[11]_i_8_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[3]_i_2_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[3]_i_3_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[3]_i_4_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[3]_i_5_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[3]_i_6_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[3]_i_7_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[3]_i_8_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[3]_i_9_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[7]_i_2_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[7]_i_3_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[7]_i_4_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[7]_i_5_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[7]_i_6_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[7]_i_7_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[7]_i_8_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2[7]_i_9_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2_reg[0]_i_2_n_3\ : STD_LOGIC; + signal \det_v0active_start_hori_int2_reg[0]_i_3_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2_reg[0]_i_3_n_1\ : STD_LOGIC; + signal \det_v0active_start_hori_int2_reg[0]_i_3_n_2\ : STD_LOGIC; + signal \det_v0active_start_hori_int2_reg[0]_i_3_n_3\ : STD_LOGIC; + signal \det_v0active_start_hori_int2_reg[11]_i_1_n_1\ : STD_LOGIC; + signal \det_v0active_start_hori_int2_reg[11]_i_1_n_2\ : STD_LOGIC; + signal \det_v0active_start_hori_int2_reg[11]_i_1_n_3\ : STD_LOGIC; + signal \det_v0active_start_hori_int2_reg[3]_i_1_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2_reg[3]_i_1_n_1\ : STD_LOGIC; + signal \det_v0active_start_hori_int2_reg[3]_i_1_n_2\ : STD_LOGIC; + signal \det_v0active_start_hori_int2_reg[3]_i_1_n_3\ : STD_LOGIC; + signal \det_v0active_start_hori_int2_reg[7]_i_1_n_0\ : STD_LOGIC; + signal \det_v0active_start_hori_int2_reg[7]_i_1_n_1\ : STD_LOGIC; + signal \det_v0active_start_hori_int2_reg[7]_i_1_n_2\ : STD_LOGIC; + signal \det_v0active_start_hori_int2_reg[7]_i_1_n_3\ : STD_LOGIC; + signal det_v0active_start_int : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal det_v0active_start_int_6 : STD_LOGIC; + signal det_v0bp_start_hori_int : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal det_v0bp_start_hori_int2 : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal det_v0bp_start_hori_last : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal det_v0bp_start_int : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal det_v0bp_start_int2 : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal \det_v0bp_start_int2[10]_i_2_n_0\ : STD_LOGIC; + signal \det_v0bp_start_int2[10]_i_3_n_0\ : STD_LOGIC; + signal \det_v0bp_start_int2[10]_i_4_n_0\ : STD_LOGIC; + signal \det_v0bp_start_int2[3]_i_2_n_0\ : STD_LOGIC; + signal \det_v0bp_start_int2[3]_i_3_n_0\ : STD_LOGIC; + signal \det_v0bp_start_int2[3]_i_4_n_0\ : STD_LOGIC; + signal \det_v0bp_start_int2[3]_i_5_n_0\ : STD_LOGIC; + signal \det_v0bp_start_int2[7]_i_2_n_0\ : STD_LOGIC; + signal \det_v0bp_start_int2[7]_i_3_n_0\ : STD_LOGIC; + signal \det_v0bp_start_int2[7]_i_4_n_0\ : STD_LOGIC; + signal \det_v0bp_start_int2[7]_i_5_n_0\ : STD_LOGIC; + signal \det_v0bp_start_int2_reg[10]_i_1_n_2\ : STD_LOGIC; + signal \det_v0bp_start_int2_reg[10]_i_1_n_3\ : STD_LOGIC; + signal \det_v0bp_start_int2_reg[3]_i_1_n_0\ : STD_LOGIC; + signal \det_v0bp_start_int2_reg[3]_i_1_n_1\ : STD_LOGIC; + signal \det_v0bp_start_int2_reg[3]_i_1_n_2\ : STD_LOGIC; + signal \det_v0bp_start_int2_reg[3]_i_1_n_3\ : STD_LOGIC; + signal \det_v0bp_start_int2_reg[7]_i_1_n_0\ : STD_LOGIC; + signal \det_v0bp_start_int2_reg[7]_i_1_n_1\ : STD_LOGIC; + signal \det_v0bp_start_int2_reg[7]_i_1_n_2\ : STD_LOGIC; + signal \det_v0bp_start_int2_reg[7]_i_1_n_3\ : STD_LOGIC; + signal det_v0bp_start_int_7 : STD_LOGIC; + signal det_v0bp_start_last : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal det_v0fp_start_hori_int2 : STD_LOGIC_VECTOR ( 11 downto 1 ); + signal \det_v0fp_start_hori_int2[0]_i_10_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[0]_i_11_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[0]_i_12_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[0]_i_13_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[0]_i_14_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[0]_i_1_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[0]_i_4_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[0]_i_5_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[0]_i_6_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[0]_i_7_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[0]_i_8_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[0]_i_9_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[11]_i_2_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[11]_i_3_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[11]_i_4_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[11]_i_5_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[11]_i_6_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[11]_i_7_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[11]_i_8_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[3]_i_2_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[3]_i_3_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[3]_i_4_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[3]_i_5_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[3]_i_6_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[3]_i_7_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[3]_i_8_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[3]_i_9_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[7]_i_2_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[7]_i_3_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[7]_i_4_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[7]_i_5_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[7]_i_6_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[7]_i_7_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[7]_i_8_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2[7]_i_9_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2_reg[0]_i_2_n_3\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2_reg[0]_i_3_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2_reg[0]_i_3_n_1\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2_reg[0]_i_3_n_2\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2_reg[0]_i_3_n_3\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2_reg[11]_i_1_n_1\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2_reg[11]_i_1_n_2\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2_reg[11]_i_1_n_3\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2_reg[3]_i_1_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2_reg[3]_i_1_n_1\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2_reg[3]_i_1_n_2\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2_reg[3]_i_1_n_3\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2_reg[7]_i_1_n_0\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2_reg[7]_i_1_n_1\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2_reg[7]_i_1_n_2\ : STD_LOGIC; + signal \det_v0fp_start_hori_int2_reg[7]_i_1_n_3\ : STD_LOGIC; + signal det_v0fp_start_int : STD_LOGIC; + signal det_v0sync_start_hori_int : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal det_v0sync_start_hori_int2 : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal det_v0sync_start_hori_last : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal det_v0sync_start_int : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal det_v0sync_start_int2 : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal \det_v0sync_start_int2[10]_i_2_n_0\ : STD_LOGIC; + signal \det_v0sync_start_int2[10]_i_3_n_0\ : STD_LOGIC; + signal \det_v0sync_start_int2[10]_i_4_n_0\ : STD_LOGIC; + signal \det_v0sync_start_int2[3]_i_2_n_0\ : STD_LOGIC; + signal \det_v0sync_start_int2[3]_i_3_n_0\ : STD_LOGIC; + signal \det_v0sync_start_int2[3]_i_4_n_0\ : STD_LOGIC; + signal \det_v0sync_start_int2[3]_i_5_n_0\ : STD_LOGIC; + signal \det_v0sync_start_int2[7]_i_2_n_0\ : STD_LOGIC; + signal \det_v0sync_start_int2[7]_i_3_n_0\ : STD_LOGIC; + signal \det_v0sync_start_int2[7]_i_4_n_0\ : STD_LOGIC; + signal \det_v0sync_start_int2[7]_i_5_n_0\ : STD_LOGIC; + signal \det_v0sync_start_int2_reg[10]_i_1_n_2\ : STD_LOGIC; + signal \det_v0sync_start_int2_reg[10]_i_1_n_3\ : STD_LOGIC; + signal \det_v0sync_start_int2_reg[3]_i_1_n_0\ : STD_LOGIC; + signal \det_v0sync_start_int2_reg[3]_i_1_n_1\ : STD_LOGIC; + signal \det_v0sync_start_int2_reg[3]_i_1_n_2\ : STD_LOGIC; + signal \det_v0sync_start_int2_reg[3]_i_1_n_3\ : STD_LOGIC; + signal \det_v0sync_start_int2_reg[7]_i_1_n_0\ : STD_LOGIC; + signal \det_v0sync_start_int2_reg[7]_i_1_n_1\ : STD_LOGIC; + signal \det_v0sync_start_int2_reg[7]_i_1_n_2\ : STD_LOGIC; + signal \det_v0sync_start_int2_reg[7]_i_1_n_3\ : STD_LOGIC; + signal det_v0sync_start_int_4 : STD_LOGIC; + signal det_v0sync_start_last : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal \det_v0total[0]_i_1_n_0\ : STD_LOGIC; + signal \det_v0total[10]_i_1_n_0\ : STD_LOGIC; + signal \det_v0total[10]_i_2_n_0\ : STD_LOGIC; + signal \det_v0total[1]_i_1_n_0\ : STD_LOGIC; + signal \det_v0total[2]_i_1_n_0\ : STD_LOGIC; + signal \det_v0total[3]_i_1_n_0\ : STD_LOGIC; + signal \det_v0total[4]_i_1_n_0\ : STD_LOGIC; + signal \det_v0total[5]_i_1_n_0\ : STD_LOGIC; + signal \det_v0total[6]_i_1_n_0\ : STD_LOGIC; + signal \det_v0total[7]_i_1_n_0\ : STD_LOGIC; + signal \det_v0total[8]_i_1_n_0\ : STD_LOGIC; + signal \det_v0total[9]_i_1_n_0\ : STD_LOGIC; + signal det_v0total_int : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal \det_v0total_int[0]_i_1_n_0\ : STD_LOGIC; + signal \det_v0total_int[10]_i_2_n_0\ : STD_LOGIC; + signal \det_v0total_int[1]_i_1_n_0\ : STD_LOGIC; + signal \det_v0total_int[2]_i_1_n_0\ : STD_LOGIC; + signal \det_v0total_int[3]_i_1_n_0\ : STD_LOGIC; + signal \det_v0total_int[4]_i_1_n_0\ : STD_LOGIC; + signal \det_v0total_int[5]_i_1_n_0\ : STD_LOGIC; + signal \det_v0total_int[6]_i_1_n_0\ : STD_LOGIC; + signal \det_v0total_int[7]_i_1_n_0\ : STD_LOGIC; + signal \det_v0total_int[8]_i_1_n_0\ : STD_LOGIC; + signal \det_v0total_int[9]_i_1_n_0\ : STD_LOGIC; + signal det_v0total_int_5 : STD_LOGIC; + signal det_vsync_pol_change : STD_LOGIC; + signal found_eof_i_1_n_0 : STD_LOGIC; + signal found_eof_reg_n_0 : STD_LOGIC; + signal frame_end : STD_LOGIC; + signal frame_end_d : STD_LOGIC; + signal gtOp : STD_LOGIC; + signal gtOp29_in : STD_LOGIC; + signal gtOp_0 : STD_LOGIC; + signal \gtOp_carry__0_i_1_n_0\ : STD_LOGIC; + signal \gtOp_carry__0_i_2_n_0\ : STD_LOGIC; + signal \gtOp_carry__0_i_3_n_0\ : STD_LOGIC; + signal \gtOp_carry__0_i_4_n_0\ : STD_LOGIC; + signal \gtOp_carry__0_i_5_n_0\ : STD_LOGIC; + signal \gtOp_carry__0_n_2\ : STD_LOGIC; + signal \gtOp_carry__0_n_3\ : STD_LOGIC; + signal gtOp_carry_i_1_n_0 : STD_LOGIC; + signal gtOp_carry_i_2_n_0 : STD_LOGIC; + signal gtOp_carry_i_3_n_0 : STD_LOGIC; + signal gtOp_carry_i_4_n_0 : STD_LOGIC; + signal gtOp_carry_i_5_n_0 : STD_LOGIC; + signal gtOp_carry_i_6_n_0 : STD_LOGIC; + signal gtOp_carry_i_7_n_0 : STD_LOGIC; + signal gtOp_carry_i_8_n_0 : STD_LOGIC; + signal gtOp_carry_n_0 : STD_LOGIC; + signal gtOp_carry_n_1 : STD_LOGIC; + signal gtOp_carry_n_2 : STD_LOGIC; + signal gtOp_carry_n_3 : STD_LOGIC; + signal \gtOp_inferred__0/i__carry__0_n_2\ : STD_LOGIC; + signal \gtOp_inferred__0/i__carry__0_n_3\ : STD_LOGIC; + signal \gtOp_inferred__0/i__carry_n_0\ : STD_LOGIC; + signal \gtOp_inferred__0/i__carry_n_1\ : STD_LOGIC; + signal \gtOp_inferred__0/i__carry_n_2\ : STD_LOGIC; + signal \gtOp_inferred__0/i__carry_n_3\ : STD_LOGIC; + signal \gtOp_inferred__2/i__carry__0_n_3\ : STD_LOGIC; + signal \gtOp_inferred__2/i__carry_n_0\ : STD_LOGIC; + signal \gtOp_inferred__2/i__carry_n_1\ : STD_LOGIC; + signal \gtOp_inferred__2/i__carry_n_2\ : STD_LOGIC; + signal \gtOp_inferred__2/i__carry_n_3\ : STD_LOGIC; + signal h_count : STD_LOGIC; + signal \h_count0__0\ : STD_LOGIC; + signal h_count1 : STD_LOGIC; + signal \h_count[0]_i_1_n_0\ : STD_LOGIC; + signal \h_count[0]_i_4_n_0\ : STD_LOGIC; + signal \h_count[0]_i_5_n_0\ : STD_LOGIC; + signal \h_count[0]_i_6_n_0\ : STD_LOGIC; + signal \h_count[0]_i_7_n_0\ : STD_LOGIC; + signal \h_count[0]_i_8_n_0\ : STD_LOGIC; + signal \h_count[0]_i_9_n_0\ : STD_LOGIC; + signal \h_count[4]_i_2_n_0\ : STD_LOGIC; + signal \h_count[4]_i_3_n_0\ : STD_LOGIC; + signal \h_count[4]_i_4_n_0\ : STD_LOGIC; + signal \h_count[4]_i_5_n_0\ : STD_LOGIC; + signal \h_count[8]_i_2_n_0\ : STD_LOGIC; + signal \h_count[8]_i_3_n_0\ : STD_LOGIC; + signal \h_count[8]_i_4_n_0\ : STD_LOGIC; + signal \h_count[8]_i_5_n_0\ : STD_LOGIC; + signal \h_count_reg[0]_i_3_n_0\ : STD_LOGIC; + signal \h_count_reg[0]_i_3_n_1\ : STD_LOGIC; + signal \h_count_reg[0]_i_3_n_2\ : STD_LOGIC; + signal \h_count_reg[0]_i_3_n_3\ : STD_LOGIC; + signal \h_count_reg[0]_i_3_n_4\ : STD_LOGIC; + signal \h_count_reg[0]_i_3_n_5\ : STD_LOGIC; + signal \h_count_reg[0]_i_3_n_6\ : STD_LOGIC; + signal \h_count_reg[0]_i_3_n_7\ : STD_LOGIC; + signal \h_count_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \h_count_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \h_count_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \h_count_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \h_count_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \h_count_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \h_count_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \h_count_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \h_count_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \h_count_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \h_count_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \h_count_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \h_count_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \h_count_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \h_count_reg[8]_i_1_n_7\ : STD_LOGIC; + signal hsync_d : STD_LOGIC; + signal hsync_d2 : STD_LOGIC; + signal \^hsync_lock_int\ : STD_LOGIC; + signal \i__carry__0_i_1__0_n_0\ : STD_LOGIC; + signal \i__carry__0_i_1__1_n_0\ : STD_LOGIC; + signal \i__carry__0_i_1__2_n_0\ : STD_LOGIC; + signal \i__carry__0_i_1__3_n_0\ : STD_LOGIC; + signal \i__carry__0_i_1__4_n_0\ : STD_LOGIC; + signal \i__carry__0_i_1__5_n_0\ : STD_LOGIC; + signal \i__carry__0_i_1__6_n_0\ : STD_LOGIC; + signal \i__carry__0_i_1_n_0\ : STD_LOGIC; + signal \i__carry__0_i_2__0_n_0\ : STD_LOGIC; + signal \i__carry__0_i_2__1_n_0\ : STD_LOGIC; + signal \i__carry__0_i_2__2_n_0\ : STD_LOGIC; + signal \i__carry__0_i_2__3_n_0\ : STD_LOGIC; + signal \i__carry__0_i_2__4_n_0\ : STD_LOGIC; + signal \i__carry__0_i_2__5_n_0\ : STD_LOGIC; + signal \i__carry__0_i_2__6_n_0\ : STD_LOGIC; + signal \i__carry__0_i_2_n_0\ : STD_LOGIC; + signal \i__carry__0_i_3__0_n_0\ : STD_LOGIC; + signal \i__carry__0_i_3__1_n_0\ : STD_LOGIC; + signal \i__carry__0_i_3__2_n_0\ : STD_LOGIC; + signal \i__carry__0_i_3__3_n_0\ : STD_LOGIC; + signal \i__carry__0_i_3__4_n_0\ : STD_LOGIC; + signal \i__carry__0_i_3__5_n_0\ : STD_LOGIC; + signal \i__carry__0_i_3__6_n_0\ : STD_LOGIC; + signal \i__carry__0_i_3_n_0\ : STD_LOGIC; + signal \i__carry__0_i_4__0_n_0\ : STD_LOGIC; + signal \i__carry__0_i_4__1_n_0\ : STD_LOGIC; + signal \i__carry__0_i_4__2_n_0\ : STD_LOGIC; + signal \i__carry__0_i_4__3_n_0\ : STD_LOGIC; + signal \i__carry__0_i_4__4_n_0\ : STD_LOGIC; + signal \i__carry__0_i_4__5_n_0\ : STD_LOGIC; + signal \i__carry__0_i_4__6_n_0\ : STD_LOGIC; + signal \i__carry__0_i_4_n_0\ : STD_LOGIC; + signal \i__carry__0_i_5__0_n_0\ : STD_LOGIC; + signal \i__carry__0_i_5_n_0\ : STD_LOGIC; + signal \i__carry__1_i_1__0_n_0\ : STD_LOGIC; + signal \i__carry__1_i_1__1_n_0\ : STD_LOGIC; + signal \i__carry__1_i_1__2_n_0\ : STD_LOGIC; + signal \i__carry__1_i_1_n_0\ : STD_LOGIC; + signal \i__carry__1_i_2__0_n_0\ : STD_LOGIC; + signal \i__carry__1_i_2__1_n_0\ : STD_LOGIC; + signal \i__carry__1_i_2__2_n_0\ : STD_LOGIC; + signal \i__carry__1_i_2_n_0\ : STD_LOGIC; + signal \i__carry__1_i_3__0_n_0\ : STD_LOGIC; + signal \i__carry__1_i_3__1_n_0\ : STD_LOGIC; + signal \i__carry__1_i_3__2_n_0\ : STD_LOGIC; + signal \i__carry__1_i_3_n_0\ : STD_LOGIC; + signal \i__carry__1_i_4__0_n_0\ : STD_LOGIC; + signal \i__carry__1_i_4__1_n_0\ : STD_LOGIC; + signal \i__carry__1_i_4__2_n_0\ : STD_LOGIC; + signal \i__carry__1_i_4_n_0\ : STD_LOGIC; + signal \i__carry_i_1__0_n_0\ : STD_LOGIC; + signal \i__carry_i_1__10_n_0\ : STD_LOGIC; + signal \i__carry_i_1__11_n_0\ : STD_LOGIC; + signal \i__carry_i_1__12_n_0\ : STD_LOGIC; + signal \i__carry_i_1__1_n_0\ : STD_LOGIC; + signal \i__carry_i_1__2_n_0\ : STD_LOGIC; + signal \i__carry_i_1__3_n_0\ : STD_LOGIC; + signal \i__carry_i_1__4_n_0\ : STD_LOGIC; + signal \i__carry_i_1__5_n_0\ : STD_LOGIC; + signal \i__carry_i_1__6_n_0\ : STD_LOGIC; + signal \i__carry_i_1__7_n_0\ : STD_LOGIC; + signal \i__carry_i_1__8_n_0\ : STD_LOGIC; + signal \i__carry_i_1__9_n_0\ : STD_LOGIC; + signal \i__carry_i_1_n_0\ : STD_LOGIC; + signal \i__carry_i_2__0_n_0\ : STD_LOGIC; + signal \i__carry_i_2__10_n_0\ : STD_LOGIC; + signal \i__carry_i_2__11_n_0\ : STD_LOGIC; + signal \i__carry_i_2__12_n_0\ : STD_LOGIC; + signal \i__carry_i_2__1_n_0\ : STD_LOGIC; + signal \i__carry_i_2__2_n_0\ : STD_LOGIC; + signal \i__carry_i_2__3_n_0\ : STD_LOGIC; + signal \i__carry_i_2__4_n_0\ : STD_LOGIC; + signal \i__carry_i_2__5_n_0\ : STD_LOGIC; + signal \i__carry_i_2__6_n_0\ : STD_LOGIC; + signal \i__carry_i_2__7_n_0\ : STD_LOGIC; + signal \i__carry_i_2__8_n_0\ : STD_LOGIC; + signal \i__carry_i_2__9_n_0\ : STD_LOGIC; + signal \i__carry_i_2_n_0\ : STD_LOGIC; + signal \i__carry_i_3__0_n_0\ : STD_LOGIC; + signal \i__carry_i_3__10_n_0\ : STD_LOGIC; + signal \i__carry_i_3__11_n_0\ : STD_LOGIC; + signal \i__carry_i_3__12_n_0\ : STD_LOGIC; + signal \i__carry_i_3__1_n_0\ : STD_LOGIC; + signal \i__carry_i_3__2_n_0\ : STD_LOGIC; + signal \i__carry_i_3__3_n_0\ : STD_LOGIC; + signal \i__carry_i_3__4_n_0\ : STD_LOGIC; + signal \i__carry_i_3__5_n_0\ : STD_LOGIC; + signal \i__carry_i_3__6_n_0\ : STD_LOGIC; + signal \i__carry_i_3__7_n_0\ : STD_LOGIC; + signal \i__carry_i_3__8_n_0\ : STD_LOGIC; + signal \i__carry_i_3__9_n_0\ : STD_LOGIC; + signal \i__carry_i_3_n_0\ : STD_LOGIC; + signal \i__carry_i_4__0_n_0\ : STD_LOGIC; + signal \i__carry_i_4__10_n_0\ : STD_LOGIC; + signal \i__carry_i_4__11_n_0\ : STD_LOGIC; + signal \i__carry_i_4__12_n_0\ : STD_LOGIC; + signal \i__carry_i_4__1_n_0\ : STD_LOGIC; + signal \i__carry_i_4__2_n_0\ : STD_LOGIC; + signal \i__carry_i_4__3_n_0\ : STD_LOGIC; + signal \i__carry_i_4__4_n_0\ : STD_LOGIC; + signal \i__carry_i_4__5_n_0\ : STD_LOGIC; + signal \i__carry_i_4__6_n_0\ : STD_LOGIC; + signal \i__carry_i_4__7_n_0\ : STD_LOGIC; + signal \i__carry_i_4__8_n_0\ : STD_LOGIC; + signal \i__carry_i_4__9_n_0\ : STD_LOGIC; + signal \i__carry_i_4_n_0\ : STD_LOGIC; + signal \i__carry_i_5__0_n_0\ : STD_LOGIC; + signal \i__carry_i_5__1_n_0\ : STD_LOGIC; + signal \i__carry_i_5__2_n_0\ : STD_LOGIC; + signal \i__carry_i_5__3_n_0\ : STD_LOGIC; + signal \i__carry_i_5__4_n_0\ : STD_LOGIC; + signal \i__carry_i_5_n_0\ : STD_LOGIC; + signal \i__carry_i_6__0_n_0\ : STD_LOGIC; + signal \i__carry_i_6__1_n_0\ : STD_LOGIC; + signal \i__carry_i_6__2_n_0\ : STD_LOGIC; + signal \i__carry_i_6_n_0\ : STD_LOGIC; + signal \i__carry_i_7__0_n_0\ : STD_LOGIC; + signal \i__carry_i_7__1_n_0\ : STD_LOGIC; + signal \i__carry_i_7__2_n_0\ : STD_LOGIC; + signal \i__carry_i_7_n_0\ : STD_LOGIC; + signal \i__carry_i_8__0_n_0\ : STD_LOGIC; + signal \i__carry_i_8__1_n_0\ : STD_LOGIC; + signal \i__carry_i_8__2_n_0\ : STD_LOGIC; + signal \i__carry_i_8_n_0\ : STD_LOGIC; + signal last_chroma : STD_LOGIC; + signal leqOp : STD_LOGIC; + signal leqOp_1 : STD_LOGIC; + signal \leqOp_carry__0_i_1_n_0\ : STD_LOGIC; + signal \leqOp_carry__0_i_2_n_0\ : STD_LOGIC; + signal \leqOp_carry__0_i_3_n_0\ : STD_LOGIC; + signal \leqOp_carry__0_i_4_n_0\ : STD_LOGIC; + signal \leqOp_carry__0_i_5_n_0\ : STD_LOGIC; + signal \leqOp_carry__0_n_2\ : STD_LOGIC; + signal \leqOp_carry__0_n_3\ : STD_LOGIC; + signal leqOp_carry_i_1_n_0 : STD_LOGIC; + signal leqOp_carry_i_2_n_0 : STD_LOGIC; + signal leqOp_carry_i_3_n_0 : STD_LOGIC; + signal leqOp_carry_i_4_n_0 : STD_LOGIC; + signal leqOp_carry_i_5_n_0 : STD_LOGIC; + signal leqOp_carry_i_6_n_0 : STD_LOGIC; + signal leqOp_carry_i_7_n_0 : STD_LOGIC; + signal leqOp_carry_i_8_n_0 : STD_LOGIC; + signal leqOp_carry_n_0 : STD_LOGIC; + signal leqOp_carry_n_1 : STD_LOGIC; + signal leqOp_carry_n_2 : STD_LOGIC; + signal leqOp_carry_n_3 : STD_LOGIC; + signal \leqOp_inferred__0/i__carry__0_n_2\ : STD_LOGIC; + signal \leqOp_inferred__0/i__carry__0_n_3\ : STD_LOGIC; + signal \leqOp_inferred__0/i__carry_n_0\ : STD_LOGIC; + signal \leqOp_inferred__0/i__carry_n_1\ : STD_LOGIC; + signal \leqOp_inferred__0/i__carry_n_2\ : STD_LOGIC; + signal \leqOp_inferred__0/i__carry_n_3\ : STD_LOGIC; + signal line_end : STD_LOGIC; + signal line_end_d_reg_n_0 : STD_LOGIC; + signal ltOp : STD_LOGIC; + signal \ltOp_carry__0_i_1_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_2_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_3_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_i_4_n_0\ : STD_LOGIC; + signal \ltOp_carry__0_n_3\ : STD_LOGIC; + signal ltOp_carry_i_1_n_0 : STD_LOGIC; + signal ltOp_carry_i_2_n_0 : STD_LOGIC; + signal ltOp_carry_i_3_n_0 : STD_LOGIC; + signal ltOp_carry_i_4_n_0 : STD_LOGIC; + signal ltOp_carry_i_5_n_0 : STD_LOGIC; + signal ltOp_carry_i_6_n_0 : STD_LOGIC; + signal ltOp_carry_i_7_n_0 : STD_LOGIC; + signal ltOp_carry_i_8_n_0 : STD_LOGIC; + signal ltOp_carry_n_0 : STD_LOGIC; + signal ltOp_carry_n_1 : STD_LOGIC; + signal ltOp_carry_n_2 : STD_LOGIC; + signal ltOp_carry_n_3 : STD_LOGIC; + signal \ltOp_inferred__0/i__carry__0_n_2\ : STD_LOGIC; + signal \ltOp_inferred__0/i__carry__0_n_3\ : STD_LOGIC; + signal \ltOp_inferred__0/i__carry_n_0\ : STD_LOGIC; + signal \ltOp_inferred__0/i__carry_n_1\ : STD_LOGIC; + signal \ltOp_inferred__0/i__carry_n_2\ : STD_LOGIC; + signal \ltOp_inferred__0/i__carry_n_3\ : STD_LOGIC; + signal minusOp0_out : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal minusOp1_out : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \minusOp_carry__0_i_1_n_0\ : STD_LOGIC; + signal \minusOp_carry__0_i_2_n_0\ : STD_LOGIC; + signal \minusOp_carry__0_i_3_n_0\ : STD_LOGIC; + signal \minusOp_carry__0_i_4_n_0\ : STD_LOGIC; + signal \minusOp_carry__0_n_0\ : STD_LOGIC; + signal \minusOp_carry__0_n_1\ : STD_LOGIC; + signal \minusOp_carry__0_n_2\ : STD_LOGIC; + signal \minusOp_carry__0_n_3\ : STD_LOGIC; + signal \minusOp_carry__1_i_1_n_0\ : STD_LOGIC; + signal \minusOp_carry__1_i_2_n_0\ : STD_LOGIC; + signal \minusOp_carry__1_i_3_n_0\ : STD_LOGIC; + signal \minusOp_carry__1_i_4_n_0\ : STD_LOGIC; + signal \minusOp_carry__1_n_1\ : STD_LOGIC; + signal \minusOp_carry__1_n_2\ : STD_LOGIC; + signal \minusOp_carry__1_n_3\ : STD_LOGIC; + signal minusOp_carry_i_1_n_0 : STD_LOGIC; + signal minusOp_carry_i_2_n_0 : STD_LOGIC; + signal minusOp_carry_i_3_n_0 : STD_LOGIC; + signal minusOp_carry_i_4_n_0 : STD_LOGIC; + signal minusOp_carry_n_0 : STD_LOGIC; + signal minusOp_carry_n_1 : STD_LOGIC; + signal minusOp_carry_n_2 : STD_LOGIC; + signal minusOp_carry_n_3 : STD_LOGIC; + signal \minusOp_inferred__0/i__carry__0_n_0\ : STD_LOGIC; + signal \minusOp_inferred__0/i__carry__0_n_1\ : STD_LOGIC; + signal \minusOp_inferred__0/i__carry__0_n_2\ : STD_LOGIC; + signal \minusOp_inferred__0/i__carry__0_n_3\ : STD_LOGIC; + signal \minusOp_inferred__0/i__carry__1_n_1\ : STD_LOGIC; + signal \minusOp_inferred__0/i__carry__1_n_2\ : STD_LOGIC; + signal \minusOp_inferred__0/i__carry__1_n_3\ : STD_LOGIC; + signal \minusOp_inferred__0/i__carry_n_0\ : STD_LOGIC; + signal \minusOp_inferred__0/i__carry_n_1\ : STD_LOGIC; + signal \minusOp_inferred__0/i__carry_n_2\ : STD_LOGIC; + signal \minusOp_inferred__0/i__carry_n_3\ : STD_LOGIC; + signal neqOp : STD_LOGIC; + signal neqOp0_out : STD_LOGIC; + signal neqOp1_out : STD_LOGIC; + signal neqOp2_out : STD_LOGIC; + signal neqOp3_out : STD_LOGIC; + signal neqOp_carry_i_1_n_0 : STD_LOGIC; + signal neqOp_carry_i_2_n_0 : STD_LOGIC; + signal neqOp_carry_i_3_n_0 : STD_LOGIC; + signal neqOp_carry_i_4_n_0 : STD_LOGIC; + signal neqOp_carry_n_1 : STD_LOGIC; + signal neqOp_carry_n_2 : STD_LOGIC; + signal neqOp_carry_n_3 : STD_LOGIC; + signal \neqOp_inferred__0/i__carry_n_1\ : STD_LOGIC; + signal \neqOp_inferred__0/i__carry_n_2\ : STD_LOGIC; + signal \neqOp_inferred__0/i__carry_n_3\ : STD_LOGIC; + signal \neqOp_inferred__1/i__carry_n_0\ : STD_LOGIC; + signal \neqOp_inferred__1/i__carry_n_1\ : STD_LOGIC; + signal \neqOp_inferred__1/i__carry_n_2\ : STD_LOGIC; + signal \neqOp_inferred__1/i__carry_n_3\ : STD_LOGIC; + signal \neqOp_inferred__2/i__carry_n_1\ : STD_LOGIC; + signal \neqOp_inferred__2/i__carry_n_2\ : STD_LOGIC; + signal \neqOp_inferred__2/i__carry_n_3\ : STD_LOGIC; + signal \neqOp_inferred__3/i__carry_n_0\ : STD_LOGIC; + signal \neqOp_inferred__3/i__carry_n_1\ : STD_LOGIC; + signal \neqOp_inferred__3/i__carry_n_2\ : STD_LOGIC; + signal \neqOp_inferred__3/i__carry_n_3\ : STD_LOGIC; + signal \neqOp_inferred__4/i__carry_n_1\ : STD_LOGIC; + signal \neqOp_inferred__4/i__carry_n_2\ : STD_LOGIC; + signal \neqOp_inferred__4/i__carry_n_3\ : STD_LOGIC; + signal \neqOp_inferred__5/i__carry_n_1\ : STD_LOGIC; + signal \neqOp_inferred__5/i__carry_n_2\ : STD_LOGIC; + signal \neqOp_inferred__5/i__carry_n_3\ : STD_LOGIC; + signal p_0_in16_in : STD_LOGIC; + signal p_1_in : STD_LOGIC; + signal p_30_out : STD_LOGIC; + signal p_5_out : STD_LOGIC; + signal p_7_out : STD_LOGIC; + signal plusOp : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \plusOp__0\ : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal \plusOp__1\ : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal \plusOp_inferred__2/i__carry__0_n_0\ : STD_LOGIC; + signal \plusOp_inferred__2/i__carry__0_n_1\ : STD_LOGIC; + signal \plusOp_inferred__2/i__carry__0_n_2\ : STD_LOGIC; + signal \plusOp_inferred__2/i__carry__0_n_3\ : STD_LOGIC; + signal \plusOp_inferred__2/i__carry__0_n_4\ : STD_LOGIC; + signal \plusOp_inferred__2/i__carry__0_n_5\ : STD_LOGIC; + signal \plusOp_inferred__2/i__carry__0_n_6\ : STD_LOGIC; + signal \plusOp_inferred__2/i__carry__0_n_7\ : STD_LOGIC; + signal \plusOp_inferred__2/i__carry__1_n_1\ : STD_LOGIC; + signal \plusOp_inferred__2/i__carry__1_n_2\ : STD_LOGIC; + signal \plusOp_inferred__2/i__carry__1_n_3\ : STD_LOGIC; + signal \plusOp_inferred__2/i__carry__1_n_4\ : STD_LOGIC; + signal \plusOp_inferred__2/i__carry__1_n_5\ : STD_LOGIC; + signal \plusOp_inferred__2/i__carry__1_n_6\ : STD_LOGIC; + signal \plusOp_inferred__2/i__carry__1_n_7\ : STD_LOGIC; + signal \plusOp_inferred__2/i__carry_n_0\ : STD_LOGIC; + signal \plusOp_inferred__2/i__carry_n_1\ : STD_LOGIC; + signal \plusOp_inferred__2/i__carry_n_2\ : STD_LOGIC; + signal \plusOp_inferred__2/i__carry_n_3\ : STD_LOGIC; + signal \plusOp_inferred__2/i__carry_n_4\ : STD_LOGIC; + signal \plusOp_inferred__2/i__carry_n_5\ : STD_LOGIC; + signal \plusOp_inferred__2/i__carry_n_6\ : STD_LOGIC; + signal \plusOp_inferred__2/i__carry_n_7\ : STD_LOGIC; + signal \^reset\ : STD_LOGIC; + signal \^time_status_regs[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \^time_status_regs[6]\ : STD_LOGIC_VECTOR ( 23 downto 0 ); + signal \^time_status_regs_int_reg[0]\ : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal top_of_frame141_out : STD_LOGIC; + signal top_of_frame_i_1_n_0 : STD_LOGIC; + signal top_of_frame_reg_n_0 : STD_LOGIC; + signal \v_count[10]_i_1_n_0\ : STD_LOGIC; + signal \v_count[10]_i_5_n_0\ : STD_LOGIC; + signal v_count_last : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal \v_count_reg__0\ : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal vsync_count : STD_LOGIC; + signal vsync_delay : STD_LOGIC; + signal \^vsync_lock_int\ : STD_LOGIC; + signal vsync_rose : STD_LOGIC; + signal \NLW_DET_HACTIVE.active_video_count_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_DET_HSYNC.hsync_count_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW__inferred__11/i__carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW__inferred__8/i__carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_det_htotal_int2_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_det_htotal_int2_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_det_v0active_start_hori_int2_reg[0]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_det_v0active_start_hori_int2_reg[0]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_det_v0active_start_hori_int2_reg[0]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_det_v0active_start_hori_int2_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_det_v0active_start_hori_int2_reg[3]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \NLW_det_v0bp_start_int2_reg[10]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_det_v0bp_start_int2_reg[10]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_det_v0fp_start_hori_int2_reg[0]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_det_v0fp_start_hori_int2_reg[0]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_det_v0fp_start_hori_int2_reg[0]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_det_v0fp_start_hori_int2_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_det_v0fp_start_hori_int2_reg[3]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \NLW_det_v0sync_start_int2_reg[10]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_det_v0sync_start_int2_reg[10]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal NLW_gtOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gtOp_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_gtOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gtOp_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gtOp_inferred__0/i__carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_gtOp_inferred__0/i__carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gtOp_inferred__2/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gtOp_inferred__2/i__carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_gtOp_inferred__2/i__carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_h_count_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal NLW_leqOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_leqOp_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_leqOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_leqOp_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_leqOp_inferred__0/i__carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_leqOp_inferred__0/i__carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_ltOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_ltOp_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_ltOp_inferred__0/i__carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_ltOp_inferred__0/i__carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_minusOp_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_minusOp_inferred__0/i__carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal NLW_neqOp_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_neqOp_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_neqOp_inferred__1/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_neqOp_inferred__2/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_neqOp_inferred__3/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_neqOp_inferred__4/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_neqOp_inferred__5/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_plusOp_inferred__2/i__carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \DET_HACTIVE.active_video_rose_i_1\ : label is "soft_lutpair270"; + attribute SOFT_HLUTNM of \DET_HSYNC.hsync_d_i_3\ : label is "soft_lutpair291"; + attribute SOFT_HLUTNM of \DET_VSYNC.GEN_DET_VSYNC_LOCK.vsync_delay[0]_i_1\ : label is "soft_lutpair287"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0bp_start_int[0]_i_1\ : label is "soft_lutpair297"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0bp_start_int[10]_i_1\ : label is "soft_lutpair305"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0bp_start_int[1]_i_1\ : label is "soft_lutpair309"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0bp_start_int[2]_i_1\ : label is "soft_lutpair309"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0bp_start_int[3]_i_1\ : label is "soft_lutpair301"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0bp_start_int[4]_i_1\ : label is "soft_lutpair302"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0bp_start_int[5]_i_1\ : label is "soft_lutpair303"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0bp_start_int[6]_i_1\ : label is "soft_lutpair304"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0bp_start_int[7]_i_1\ : label is "soft_lutpair305"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0bp_start_int[8]_i_1\ : label is "soft_lutpair306"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0bp_start_int[9]_i_1\ : label is "soft_lutpair306"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0sync_start_hori_int[0]_i_1\ : label is "soft_lutpair304"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0sync_start_hori_int[10]_i_1\ : label is "soft_lutpair295"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0sync_start_hori_int[11]_i_2\ : label is "soft_lutpair294"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0sync_start_hori_int[1]_i_1\ : label is "soft_lutpair303"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0sync_start_hori_int[2]_i_1\ : label is "soft_lutpair302"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0sync_start_hori_int[3]_i_1\ : label is "soft_lutpair301"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0sync_start_hori_int[4]_i_1\ : label is "soft_lutpair300"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0sync_start_hori_int[5]_i_1\ : label is "soft_lutpair299"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0sync_start_hori_int[6]_i_1\ : label is "soft_lutpair298"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0sync_start_hori_int[7]_i_1\ : label is "soft_lutpair297"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0sync_start_hori_int[8]_i_1\ : label is "soft_lutpair278"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0sync_start_hori_int[9]_i_1\ : label is "soft_lutpair296"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0sync_start_int[0]_i_1\ : label is "soft_lutpair307"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0sync_start_int[10]_i_1\ : label is "soft_lutpair307"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0sync_start_int[1]_i_1\ : label is "soft_lutpair308"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0sync_start_int[3]_i_1\ : label is "soft_lutpair295"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0sync_start_int[4]_i_1\ : label is "soft_lutpair294"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0sync_start_int[5]_i_1\ : label is "soft_lutpair308"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0sync_start_int[6]_i_1\ : label is "soft_lutpair300"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0sync_start_int[7]_i_1\ : label is "soft_lutpair299"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0sync_start_int[8]_i_1\ : label is "soft_lutpair298"; + attribute SOFT_HLUTNM of \DET_VSYNC.det_v0sync_start_int[9]_i_1\ : label is "soft_lutpair296"; + attribute SOFT_HLUTNM of \DET_VSYNC.vsync_count[1]_i_1\ : label is "soft_lutpair290"; + attribute SOFT_HLUTNM of \DET_VSYNC.vsync_count[2]_i_1\ : label is "soft_lutpair290"; + attribute SOFT_HLUTNM of \DET_VSYNC.vsync_count[3]_i_1\ : label is "soft_lutpair273"; + attribute SOFT_HLUTNM of \DET_VSYNC.vsync_count[4]_i_1\ : label is "soft_lutpair273"; + attribute SOFT_HLUTNM of \DET_VSYNC.vsync_count[6]_i_1\ : label is "soft_lutpair280"; + attribute SOFT_HLUTNM of \DET_VSYNC.vsync_count[7]_i_1\ : label is "soft_lutpair280"; + attribute SOFT_HLUTNM of \DET_VSYNC.vsync_count[8]_i_1\ : label is "soft_lutpair275"; + attribute SOFT_HLUTNM of \DET_VSYNC.vsync_count[9]_i_1\ : label is "soft_lutpair275"; + attribute SOFT_HLUTNM of \DET_VSYNC.vsync_rose_i_1\ : label is "soft_lutpair277"; + attribute SOFT_HLUTNM of \DET_VSYNC.vsync_toggled_i_1\ : label is "soft_lutpair277"; + attribute METHODOLOGY_DRC_VIOS : string; + attribute METHODOLOGY_DRC_VIOS of \_inferred__11/i__carry\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \_inferred__11/i__carry__0\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \_inferred__11/i__carry__1\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \_inferred__8/i__carry\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \_inferred__8/i__carry__0\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \_inferred__8/i__carry__1\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute SOFT_HLUTNM of \det_v0active_start_hori_int2[0]_i_1\ : label is "soft_lutpair292"; + attribute METHODOLOGY_DRC_VIOS of \det_v0active_start_hori_int2_reg[0]_i_2\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \det_v0active_start_hori_int2_reg[0]_i_3\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \det_v0active_start_hori_int2_reg[11]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \det_v0active_start_hori_int2_reg[3]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \det_v0active_start_hori_int2_reg[7]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute SOFT_HLUTNM of \det_v0fp_start_hori_int2[0]_i_1\ : label is "soft_lutpair292"; + attribute METHODOLOGY_DRC_VIOS of \det_v0fp_start_hori_int2_reg[11]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \det_v0fp_start_hori_int2_reg[3]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \det_v0fp_start_hori_int2_reg[7]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute SOFT_HLUTNM of \det_v0total[1]_i_1\ : label is "soft_lutpair293"; + attribute SOFT_HLUTNM of \det_v0total[2]_i_1\ : label is "soft_lutpair293"; + attribute SOFT_HLUTNM of \det_v0total[3]_i_1\ : label is "soft_lutpair274"; + attribute SOFT_HLUTNM of \det_v0total[4]_i_1\ : label is "soft_lutpair274"; + attribute SOFT_HLUTNM of \det_v0total[6]_i_1\ : label is "soft_lutpair281"; + attribute SOFT_HLUTNM of \det_v0total[7]_i_1\ : label is "soft_lutpair281"; + attribute SOFT_HLUTNM of \det_v0total[8]_i_1\ : label is "soft_lutpair272"; + attribute SOFT_HLUTNM of \det_v0total[9]_i_1\ : label is "soft_lutpair272"; + attribute SOFT_HLUTNM of \det_v0total_int[10]_i_2\ : label is "soft_lutpair282"; + attribute SOFT_HLUTNM of \det_v0total_int[1]_i_1\ : label is "soft_lutpair282"; + attribute SOFT_HLUTNM of \det_v0total_int[2]_i_1\ : label is "soft_lutpair286"; + attribute SOFT_HLUTNM of \det_v0total_int[3]_i_1\ : label is "soft_lutpair286"; + attribute SOFT_HLUTNM of \det_v0total_int[4]_i_1\ : label is "soft_lutpair283"; + attribute SOFT_HLUTNM of \det_v0total_int[5]_i_1\ : label is "soft_lutpair285"; + attribute SOFT_HLUTNM of \det_v0total_int[6]_i_1\ : label is "soft_lutpair284"; + attribute SOFT_HLUTNM of \det_v0total_int[7]_i_1\ : label is "soft_lutpair285"; + attribute SOFT_HLUTNM of \det_v0total_int[8]_i_1\ : label is "soft_lutpair284"; + attribute SOFT_HLUTNM of \det_v0total_int[9]_i_1\ : label is "soft_lutpair283"; + attribute SOFT_HLUTNM of frame_end_d_i_1 : label is "soft_lutpair279"; + attribute SOFT_HLUTNM of \h_count[0]_i_9\ : label is "soft_lutpair278"; + attribute SOFT_HLUTNM of \intr_status_int[9]_i_2\ : label is "soft_lutpair287"; + attribute METHODOLOGY_DRC_VIOS of neqOp_carry : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \neqOp_inferred__0/i__carry\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \neqOp_inferred__1/i__carry\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \neqOp_inferred__2/i__carry\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \neqOp_inferred__3/i__carry\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \neqOp_inferred__4/i__carry\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute METHODOLOGY_DRC_VIOS of \neqOp_inferred__5/i__carry\ : label is "{SYNTH-8 {cell *THIS*}}"; + attribute SOFT_HLUTNM of top_of_frame_i_2 : label is "soft_lutpair270"; + attribute SOFT_HLUTNM of \v_count[10]_i_3\ : label is "soft_lutpair291"; + attribute SOFT_HLUTNM of \v_count[10]_i_4\ : label is "soft_lutpair279"; + attribute SOFT_HLUTNM of \v_count[1]_i_1\ : label is "soft_lutpair288"; + attribute SOFT_HLUTNM of \v_count[2]_i_1\ : label is "soft_lutpair288"; + attribute SOFT_HLUTNM of \v_count[3]_i_1\ : label is "soft_lutpair276"; + attribute SOFT_HLUTNM of \v_count[4]_i_1\ : label is "soft_lutpair276"; + attribute SOFT_HLUTNM of \v_count[6]_i_1\ : label is "soft_lutpair289"; + attribute SOFT_HLUTNM of \v_count[7]_i_1\ : label is "soft_lutpair289"; + attribute SOFT_HLUTNM of \v_count[8]_i_1\ : label is "soft_lutpair271"; + attribute SOFT_HLUTNM of \v_count[9]_i_1\ : label is "soft_lutpair271"; +begin + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11]\(11 downto 0) <= \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(11 downto 0); + Q(11 downto 0) <= \^q\(11 downto 0); + active_video_lock_int <= \^active_video_lock_int\; + det_ce <= \^det_ce\; + hsync_lock_int <= \^hsync_lock_int\; + reset <= \^reset\; + \time_status_regs[3]\(2 downto 0) <= \^time_status_regs[3]\(2 downto 0); + \time_status_regs[6]\(23 downto 0) <= \^time_status_regs[6]\(23 downto 0); + \time_status_regs_int_reg[0]\(10 downto 0) <= \^time_status_regs_int_reg[0]\(10 downto 0); + vsync_lock_int <= \^vsync_lock_int\; +\DET_HACTIVE.DET_AVIDEO_LOCK.active_video_count_last[11]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => active_video_d2, + I1 => active_video_d, + I2 => \^det_ce\, + O => last_chroma + ); +\DET_HACTIVE.DET_AVIDEO_LOCK.active_video_count_last_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => last_chroma, + D => \DET_HACTIVE.active_video_count_reg\(0), + Q => active_video_count_last(0), + S => p_5_out + ); +\DET_HACTIVE.DET_AVIDEO_LOCK.active_video_count_last_reg[10]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => last_chroma, + D => \DET_HACTIVE.active_video_count_reg\(10), + Q => active_video_count_last(10), + S => p_5_out + ); +\DET_HACTIVE.DET_AVIDEO_LOCK.active_video_count_last_reg[11]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => last_chroma, + D => \DET_HACTIVE.active_video_count_reg\(11), + Q => active_video_count_last(11), + S => p_5_out + ); +\DET_HACTIVE.DET_AVIDEO_LOCK.active_video_count_last_reg[1]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => last_chroma, + D => \DET_HACTIVE.active_video_count_reg\(1), + Q => active_video_count_last(1), + S => p_5_out + ); +\DET_HACTIVE.DET_AVIDEO_LOCK.active_video_count_last_reg[2]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => last_chroma, + D => \DET_HACTIVE.active_video_count_reg\(2), + Q => active_video_count_last(2), + S => p_5_out + ); +\DET_HACTIVE.DET_AVIDEO_LOCK.active_video_count_last_reg[3]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => last_chroma, + D => \DET_HACTIVE.active_video_count_reg\(3), + Q => active_video_count_last(3), + S => p_5_out + ); +\DET_HACTIVE.DET_AVIDEO_LOCK.active_video_count_last_reg[4]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => last_chroma, + D => \DET_HACTIVE.active_video_count_reg\(4), + Q => active_video_count_last(4), + S => p_5_out + ); +\DET_HACTIVE.DET_AVIDEO_LOCK.active_video_count_last_reg[5]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => last_chroma, + D => \DET_HACTIVE.active_video_count_reg\(5), + Q => active_video_count_last(5), + S => p_5_out + ); +\DET_HACTIVE.DET_AVIDEO_LOCK.active_video_count_last_reg[6]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => last_chroma, + D => \DET_HACTIVE.active_video_count_reg\(6), + Q => active_video_count_last(6), + S => p_5_out + ); +\DET_HACTIVE.DET_AVIDEO_LOCK.active_video_count_last_reg[7]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => last_chroma, + D => \DET_HACTIVE.active_video_count_reg\(7), + Q => active_video_count_last(7), + S => p_5_out + ); +\DET_HACTIVE.DET_AVIDEO_LOCK.active_video_count_last_reg[8]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => last_chroma, + D => \DET_HACTIVE.active_video_count_reg\(8), + Q => active_video_count_last(8), + S => p_5_out + ); +\DET_HACTIVE.DET_AVIDEO_LOCK.active_video_count_last_reg[9]\: unisim.vcomponents.FDSE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => last_chroma, + D => \DET_HACTIVE.active_video_count_reg\(9), + Q => active_video_count_last(9), + S => p_5_out + ); +\DET_HACTIVE.DET_AVIDEO_LOCK.det_active_video_lock_int_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000A0003000A" + ) + port map ( + I0 => \^active_video_lock_int\, + I1 => det_active_video_pol_change, + I2 => h_count1, + I3 => lost_lock, + I4 => last_chroma, + I5 => neqOp1_out, + O => \DET_HACTIVE.DET_AVIDEO_LOCK.det_active_video_lock_int_i_1_n_0\ + ); +\DET_HACTIVE.DET_AVIDEO_LOCK.det_active_video_lock_int_reg\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => '1', + D => \DET_HACTIVE.DET_AVIDEO_LOCK.det_active_video_lock_int_i_1_n_0\, + Q => \^active_video_lock_int\, + R => '0' + ); +\DET_HACTIVE.active_video_count[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF08" + ) + port map ( + I0 => \^det_ce\, + I1 => active_video_d, + I2 => active_video_d2, + I3 => h_count1, + O => \DET_HACTIVE.active_video_count[0]_i_1_n_0\ + ); +\DET_HACTIVE.active_video_count[0]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^det_ce\, + I1 => active_video_d, + O => active_video_count + ); +\DET_HACTIVE.active_video_count[0]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \DET_HACTIVE.active_video_count_reg\(3), + O => \DET_HACTIVE.active_video_count[0]_i_4_n_0\ + ); +\DET_HACTIVE.active_video_count[0]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \DET_HACTIVE.active_video_count_reg\(2), + O => \DET_HACTIVE.active_video_count[0]_i_5_n_0\ + ); +\DET_HACTIVE.active_video_count[0]_i_6\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \DET_HACTIVE.active_video_count_reg\(1), + O => \DET_HACTIVE.active_video_count[0]_i_6_n_0\ + ); +\DET_HACTIVE.active_video_count[0]_i_7\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \DET_HACTIVE.active_video_count_reg\(0), + O => \DET_HACTIVE.active_video_count[0]_i_7_n_0\ + ); +\DET_HACTIVE.active_video_count[4]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \DET_HACTIVE.active_video_count_reg\(7), + O => \DET_HACTIVE.active_video_count[4]_i_2_n_0\ + ); +\DET_HACTIVE.active_video_count[4]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \DET_HACTIVE.active_video_count_reg\(6), + O => \DET_HACTIVE.active_video_count[4]_i_3_n_0\ + ); +\DET_HACTIVE.active_video_count[4]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \DET_HACTIVE.active_video_count_reg\(5), + O => \DET_HACTIVE.active_video_count[4]_i_4_n_0\ + ); +\DET_HACTIVE.active_video_count[4]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \DET_HACTIVE.active_video_count_reg\(4), + O => \DET_HACTIVE.active_video_count[4]_i_5_n_0\ + ); +\DET_HACTIVE.active_video_count[8]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \DET_HACTIVE.active_video_count_reg\(11), + O => \DET_HACTIVE.active_video_count[8]_i_2_n_0\ + ); +\DET_HACTIVE.active_video_count[8]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \DET_HACTIVE.active_video_count_reg\(10), + O => \DET_HACTIVE.active_video_count[8]_i_3_n_0\ + ); +\DET_HACTIVE.active_video_count[8]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \DET_HACTIVE.active_video_count_reg\(9), + O => \DET_HACTIVE.active_video_count[8]_i_4_n_0\ + ); +\DET_HACTIVE.active_video_count[8]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \DET_HACTIVE.active_video_count_reg\(8), + O => \DET_HACTIVE.active_video_count[8]_i_5_n_0\ + ); +\DET_HACTIVE.active_video_count_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => active_video_count, + D => \DET_HACTIVE.active_video_count_reg[0]_i_3_n_7\, + Q => \DET_HACTIVE.active_video_count_reg\(0), + R => \DET_HACTIVE.active_video_count[0]_i_1_n_0\ + ); +\DET_HACTIVE.active_video_count_reg[0]_i_3\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \DET_HACTIVE.active_video_count_reg[0]_i_3_n_0\, + CO(2) => \DET_HACTIVE.active_video_count_reg[0]_i_3_n_1\, + CO(1) => \DET_HACTIVE.active_video_count_reg[0]_i_3_n_2\, + CO(0) => \DET_HACTIVE.active_video_count_reg[0]_i_3_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \DET_HACTIVE.active_video_count_reg[0]_i_3_n_4\, + O(2) => \DET_HACTIVE.active_video_count_reg[0]_i_3_n_5\, + O(1) => \DET_HACTIVE.active_video_count_reg[0]_i_3_n_6\, + O(0) => \DET_HACTIVE.active_video_count_reg[0]_i_3_n_7\, + S(3) => \DET_HACTIVE.active_video_count[0]_i_4_n_0\, + S(2) => \DET_HACTIVE.active_video_count[0]_i_5_n_0\, + S(1) => \DET_HACTIVE.active_video_count[0]_i_6_n_0\, + S(0) => \DET_HACTIVE.active_video_count[0]_i_7_n_0\ + ); +\DET_HACTIVE.active_video_count_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => active_video_count, + D => \DET_HACTIVE.active_video_count_reg[8]_i_1_n_5\, + Q => \DET_HACTIVE.active_video_count_reg\(10), + R => \DET_HACTIVE.active_video_count[0]_i_1_n_0\ + ); +\DET_HACTIVE.active_video_count_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => active_video_count, + D => \DET_HACTIVE.active_video_count_reg[8]_i_1_n_4\, + Q => \DET_HACTIVE.active_video_count_reg\(11), + R => \DET_HACTIVE.active_video_count[0]_i_1_n_0\ + ); +\DET_HACTIVE.active_video_count_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => active_video_count, + D => \DET_HACTIVE.active_video_count_reg[0]_i_3_n_6\, + Q => \DET_HACTIVE.active_video_count_reg\(1), + R => \DET_HACTIVE.active_video_count[0]_i_1_n_0\ + ); +\DET_HACTIVE.active_video_count_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => active_video_count, + D => \DET_HACTIVE.active_video_count_reg[0]_i_3_n_5\, + Q => \DET_HACTIVE.active_video_count_reg\(2), + R => \DET_HACTIVE.active_video_count[0]_i_1_n_0\ + ); +\DET_HACTIVE.active_video_count_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => active_video_count, + D => \DET_HACTIVE.active_video_count_reg[0]_i_3_n_4\, + Q => \DET_HACTIVE.active_video_count_reg\(3), + R => \DET_HACTIVE.active_video_count[0]_i_1_n_0\ + ); +\DET_HACTIVE.active_video_count_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => active_video_count, + D => \DET_HACTIVE.active_video_count_reg[4]_i_1_n_7\, + Q => \DET_HACTIVE.active_video_count_reg\(4), + R => \DET_HACTIVE.active_video_count[0]_i_1_n_0\ + ); +\DET_HACTIVE.active_video_count_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \DET_HACTIVE.active_video_count_reg[0]_i_3_n_0\, + CO(3) => \DET_HACTIVE.active_video_count_reg[4]_i_1_n_0\, + CO(2) => \DET_HACTIVE.active_video_count_reg[4]_i_1_n_1\, + CO(1) => \DET_HACTIVE.active_video_count_reg[4]_i_1_n_2\, + CO(0) => \DET_HACTIVE.active_video_count_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \DET_HACTIVE.active_video_count_reg[4]_i_1_n_4\, + O(2) => \DET_HACTIVE.active_video_count_reg[4]_i_1_n_5\, + O(1) => \DET_HACTIVE.active_video_count_reg[4]_i_1_n_6\, + O(0) => \DET_HACTIVE.active_video_count_reg[4]_i_1_n_7\, + S(3) => \DET_HACTIVE.active_video_count[4]_i_2_n_0\, + S(2) => \DET_HACTIVE.active_video_count[4]_i_3_n_0\, + S(1) => \DET_HACTIVE.active_video_count[4]_i_4_n_0\, + S(0) => \DET_HACTIVE.active_video_count[4]_i_5_n_0\ + ); +\DET_HACTIVE.active_video_count_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => active_video_count, + D => \DET_HACTIVE.active_video_count_reg[4]_i_1_n_6\, + Q => \DET_HACTIVE.active_video_count_reg\(5), + R => \DET_HACTIVE.active_video_count[0]_i_1_n_0\ + ); +\DET_HACTIVE.active_video_count_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => active_video_count, + D => \DET_HACTIVE.active_video_count_reg[4]_i_1_n_5\, + Q => \DET_HACTIVE.active_video_count_reg\(6), + R => \DET_HACTIVE.active_video_count[0]_i_1_n_0\ + ); +\DET_HACTIVE.active_video_count_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => active_video_count, + D => \DET_HACTIVE.active_video_count_reg[4]_i_1_n_4\, + Q => \DET_HACTIVE.active_video_count_reg\(7), + R => \DET_HACTIVE.active_video_count[0]_i_1_n_0\ + ); +\DET_HACTIVE.active_video_count_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => active_video_count, + D => \DET_HACTIVE.active_video_count_reg[8]_i_1_n_7\, + Q => \DET_HACTIVE.active_video_count_reg\(8), + R => \DET_HACTIVE.active_video_count[0]_i_1_n_0\ + ); +\DET_HACTIVE.active_video_count_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \DET_HACTIVE.active_video_count_reg[4]_i_1_n_0\, + CO(3) => \NLW_DET_HACTIVE.active_video_count_reg[8]_i_1_CO_UNCONNECTED\(3), + CO(2) => \DET_HACTIVE.active_video_count_reg[8]_i_1_n_1\, + CO(1) => \DET_HACTIVE.active_video_count_reg[8]_i_1_n_2\, + CO(0) => \DET_HACTIVE.active_video_count_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \DET_HACTIVE.active_video_count_reg[8]_i_1_n_4\, + O(2) => \DET_HACTIVE.active_video_count_reg[8]_i_1_n_5\, + O(1) => \DET_HACTIVE.active_video_count_reg[8]_i_1_n_6\, + O(0) => \DET_HACTIVE.active_video_count_reg[8]_i_1_n_7\, + S(3) => \DET_HACTIVE.active_video_count[8]_i_2_n_0\, + S(2) => \DET_HACTIVE.active_video_count[8]_i_3_n_0\, + S(1) => \DET_HACTIVE.active_video_count[8]_i_4_n_0\, + S(0) => \DET_HACTIVE.active_video_count[8]_i_5_n_0\ + ); +\DET_HACTIVE.active_video_count_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => active_video_count, + D => \DET_HACTIVE.active_video_count_reg[8]_i_1_n_6\, + Q => \DET_HACTIVE.active_video_count_reg\(9), + R => \DET_HACTIVE.active_video_count[0]_i_1_n_0\ + ); +\DET_HACTIVE.active_video_d2_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"F4" + ) + port map ( + I0 => \DET_VSYNC.vsync_d2_reg_n_0\, + I1 => \DET_VSYNC.vsync_d_reg_n_0\, + I2 => h_count1, + O => p_7_out + ); +\DET_HACTIVE.active_video_d2_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => active_video_d, + I1 => \^det_ce\, + I2 => active_video_d2, + O => \DET_HACTIVE.active_video_d2_i_2_n_0\ + ); +\DET_HACTIVE.active_video_d2_reg\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => '1', + D => \DET_HACTIVE.active_video_d2_i_2_n_0\, + Q => active_video_d2, + R => p_7_out + ); +\DET_HACTIVE.active_video_d_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000E22E" + ) + port map ( + I0 => active_video_d, + I1 => \^det_ce\, + I2 => \^time_status_regs[3]\(2), + I3 => active_video_in, + I4 => p_7_out, + O => \DET_HACTIVE.active_video_d_i_1_n_0\ + ); +\DET_HACTIVE.active_video_d_reg\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => '1', + D => \DET_HACTIVE.active_video_d_i_1_n_0\, + Q => active_video_d, + R => '0' + ); +\DET_HACTIVE.active_video_rose_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000BAAA" + ) + port map ( + I0 => active_video_rose, + I1 => active_video_d, + I2 => active_video_d2, + I3 => \^det_ce\, + I4 => p_7_out, + O => \DET_HACTIVE.active_video_rose_i_1_n_0\ + ); +\DET_HACTIVE.active_video_rose_reg\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => '1', + D => \DET_HACTIVE.active_video_rose_i_1_n_0\, + Q => active_video_rose, + R => '0' + ); +\DET_HACTIVE.active_video_toggled_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00E200E2000000E2" + ) + port map ( + I0 => active_video_toggled, + I1 => last_chroma, + I2 => active_video_rose, + I3 => h_count1, + I4 => \DET_VSYNC.vsync_d_reg_n_0\, + I5 => \DET_VSYNC.vsync_d2_reg_n_0\, + O => \DET_HACTIVE.active_video_toggled_i_1_n_0\ + ); +\DET_HACTIVE.active_video_toggled_reg\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => '1', + D => \DET_HACTIVE.active_video_toggled_i_1_n_0\, + Q => active_video_toggled, + R => '0' + ); +\DET_HACTIVE.det_active_video_pol_change_reg\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => leqOp, + Q => det_active_video_pol_change, + R => h_count1 + ); +\DET_HACTIVE.det_active_video_pol_int_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"DFFF2000" + ) + port map ( + I0 => active_video_d2, + I1 => active_video_d, + I2 => \^det_ce\, + I3 => det_active_video_pol_change, + I4 => \^time_status_regs[3]\(2), + O => \DET_HACTIVE.det_active_video_pol_int_i_1_n_0\ + ); +\DET_HACTIVE.det_active_video_pol_int_reg\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => \DET_HACTIVE.det_active_video_pol_int_i_1_n_0\, + Q => \^time_status_regs[3]\(2), + S => h_count1 + ); +\DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hbp_start_last[11]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => h_count1, + I1 => lost_lock, + O => p_5_out + ); +\DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hbp_start_last_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => det_hbp_start_int_9, + D => det_hbp_start_int(0), + Q => det_hbp_start_last(0), + S => p_5_out + ); +\DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hbp_start_last_reg[10]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => det_hbp_start_int_9, + D => det_hbp_start_int(10), + Q => det_hbp_start_last(10), + S => p_5_out + ); +\DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hbp_start_last_reg[11]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => det_hbp_start_int_9, + D => det_hbp_start_int(11), + Q => det_hbp_start_last(11), + S => p_5_out + ); +\DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hbp_start_last_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => det_hbp_start_int_9, + D => det_hbp_start_int(1), + Q => det_hbp_start_last(1), + S => p_5_out + ); +\DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hbp_start_last_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => det_hbp_start_int_9, + D => det_hbp_start_int(2), + Q => det_hbp_start_last(2), + S => p_5_out + ); +\DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hbp_start_last_reg[3]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => det_hbp_start_int_9, + D => det_hbp_start_int(3), + Q => det_hbp_start_last(3), + S => p_5_out + ); +\DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hbp_start_last_reg[4]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => det_hbp_start_int_9, + D => det_hbp_start_int(4), + Q => det_hbp_start_last(4), + S => p_5_out + ); +\DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hbp_start_last_reg[5]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => det_hbp_start_int_9, + D => det_hbp_start_int(5), + Q => det_hbp_start_last(5), + S => p_5_out + ); +\DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hbp_start_last_reg[6]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => det_hbp_start_int_9, + D => det_hbp_start_int(6), + Q => det_hbp_start_last(6), + S => p_5_out + ); +\DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hbp_start_last_reg[7]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => det_hbp_start_int_9, + D => det_hbp_start_int(7), + Q => det_hbp_start_last(7), + S => p_5_out + ); +\DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hbp_start_last_reg[8]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => det_hbp_start_int_9, + D => det_hbp_start_int(8), + Q => det_hbp_start_last(8), + S => p_5_out + ); +\DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hbp_start_last_reg[9]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => det_hbp_start_int_9, + D => det_hbp_start_int(9), + Q => det_hbp_start_last(9), + S => p_5_out + ); +\DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_lock_int_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000A0A0A3A" + ) + port map ( + I0 => \^hsync_lock_int\, + I1 => det_hsync_pol_change, + I2 => \^det_ce\, + I3 => neqOp2_out, + I4 => neqOp3_out, + I5 => p_5_out, + O => \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_lock_int_i_1_n_0\ + ); +\DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_lock_int_reg\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => '1', + D => \DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_lock_int_i_1_n_0\, + Q => \^hsync_lock_int\, + R => '0' + ); +\DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_start_last_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => det_hsync_start_int_2, + D => det_hsync_start_int(0), + Q => det_hsync_start_last(0), + S => p_5_out + ); +\DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_start_last_reg[10]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => det_hsync_start_int_2, + D => det_hsync_start_int(10), + Q => det_hsync_start_last(10), + S => p_5_out + ); +\DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_start_last_reg[11]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => det_hsync_start_int_2, + D => det_hsync_start_int(11), + Q => det_hsync_start_last(11), + S => p_5_out + ); +\DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_start_last_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => det_hsync_start_int_2, + D => det_hsync_start_int(1), + Q => det_hsync_start_last(1), + S => p_5_out + ); +\DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_start_last_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => det_hsync_start_int_2, + D => det_hsync_start_int(2), + Q => det_hsync_start_last(2), + S => p_5_out + ); +\DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_start_last_reg[3]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => det_hsync_start_int_2, + D => det_hsync_start_int(3), + Q => det_hsync_start_last(3), + S => p_5_out + ); +\DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_start_last_reg[4]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => det_hsync_start_int_2, + D => det_hsync_start_int(4), + Q => det_hsync_start_last(4), + S => p_5_out + ); +\DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_start_last_reg[5]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => det_hsync_start_int_2, + D => det_hsync_start_int(5), + Q => det_hsync_start_last(5), + S => p_5_out + ); +\DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_start_last_reg[6]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => det_hsync_start_int_2, + D => det_hsync_start_int(6), + Q => det_hsync_start_last(6), + S => p_5_out + ); +\DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_start_last_reg[7]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => det_hsync_start_int_2, + D => det_hsync_start_int(7), + Q => det_hsync_start_last(7), + S => p_5_out + ); +\DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_start_last_reg[8]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => det_hsync_start_int_2, + D => det_hsync_start_int(8), + Q => det_hsync_start_last(8), + S => p_5_out + ); +\DET_HSYNC.GEN_DET_HSYNC_LOCK.det_hsync_start_last_reg[9]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => det_hsync_start_int_2, + D => det_hsync_start_int(9), + Q => det_hsync_start_last(9), + S => p_5_out + ); +\DET_HSYNC.det_hbp_start_int[11]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => hsync_d, + I1 => hsync_d2, + I2 => \^det_ce\, + O => det_hbp_start_int_9 + ); +\DET_HSYNC.det_hbp_start_int_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hbp_start_int_9, + D => L(11), + Q => det_hbp_start_int(0), + R => h_count1 + ); +\DET_HSYNC.det_hbp_start_int_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hbp_start_int_9, + D => L(1), + Q => det_hbp_start_int(10), + R => h_count1 + ); +\DET_HSYNC.det_hbp_start_int_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hbp_start_int_9, + D => L(0), + Q => det_hbp_start_int(11), + R => h_count1 + ); +\DET_HSYNC.det_hbp_start_int_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hbp_start_int_9, + D => L(10), + Q => det_hbp_start_int(1), + R => h_count1 + ); +\DET_HSYNC.det_hbp_start_int_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hbp_start_int_9, + D => L(9), + Q => det_hbp_start_int(2), + R => h_count1 + ); +\DET_HSYNC.det_hbp_start_int_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hbp_start_int_9, + D => L(8), + Q => det_hbp_start_int(3), + R => h_count1 + ); +\DET_HSYNC.det_hbp_start_int_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hbp_start_int_9, + D => L(7), + Q => det_hbp_start_int(4), + R => h_count1 + ); +\DET_HSYNC.det_hbp_start_int_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hbp_start_int_9, + D => L(6), + Q => det_hbp_start_int(5), + R => h_count1 + ); +\DET_HSYNC.det_hbp_start_int_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hbp_start_int_9, + D => L(5), + Q => det_hbp_start_int(6), + R => h_count1 + ); +\DET_HSYNC.det_hbp_start_int_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hbp_start_int_9, + D => L(4), + Q => det_hbp_start_int(7), + R => h_count1 + ); +\DET_HSYNC.det_hbp_start_int_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hbp_start_int_9, + D => L(3), + Q => det_hbp_start_int(8), + R => h_count1 + ); +\DET_HSYNC.det_hbp_start_int_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hbp_start_int_9, + D => L(2), + Q => det_hbp_start_int(9), + R => h_count1 + ); +\DET_HSYNC.det_hsync_pol_change_reg\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => gtOp, + Q => det_hsync_pol_change, + R => h_count1 + ); +\DET_HSYNC.det_hsync_pol_int_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFFF4000" + ) + port map ( + I0 => hsync_d, + I1 => hsync_d2, + I2 => \^det_ce\, + I3 => det_hsync_pol_change, + I4 => \^time_status_regs[3]\(1), + O => \DET_HSYNC.det_hsync_pol_int_i_1_n_0\ + ); +\DET_HSYNC.det_hsync_pol_int_reg\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => \DET_HSYNC.det_hsync_pol_int_i_1_n_0\, + Q => \^time_status_regs[3]\(1), + S => h_count1 + ); +\DET_HSYNC.det_hsync_start_int[11]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => hsync_d2, + I1 => hsync_d, + I2 => \^det_ce\, + O => det_hsync_start_int_2 + ); +\DET_HSYNC.det_hsync_start_int_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hsync_start_int_2, + D => L(11), + Q => det_hsync_start_int(0), + R => h_count1 + ); +\DET_HSYNC.det_hsync_start_int_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hsync_start_int_2, + D => L(1), + Q => det_hsync_start_int(10), + R => h_count1 + ); +\DET_HSYNC.det_hsync_start_int_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hsync_start_int_2, + D => L(0), + Q => det_hsync_start_int(11), + R => h_count1 + ); +\DET_HSYNC.det_hsync_start_int_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hsync_start_int_2, + D => L(10), + Q => det_hsync_start_int(1), + R => h_count1 + ); +\DET_HSYNC.det_hsync_start_int_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hsync_start_int_2, + D => L(9), + Q => det_hsync_start_int(2), + R => h_count1 + ); +\DET_HSYNC.det_hsync_start_int_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hsync_start_int_2, + D => L(8), + Q => det_hsync_start_int(3), + R => h_count1 + ); +\DET_HSYNC.det_hsync_start_int_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hsync_start_int_2, + D => L(7), + Q => det_hsync_start_int(4), + R => h_count1 + ); +\DET_HSYNC.det_hsync_start_int_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hsync_start_int_2, + D => L(6), + Q => det_hsync_start_int(5), + R => h_count1 + ); +\DET_HSYNC.det_hsync_start_int_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hsync_start_int_2, + D => L(5), + Q => det_hsync_start_int(6), + R => h_count1 + ); +\DET_HSYNC.det_hsync_start_int_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hsync_start_int_2, + D => L(4), + Q => det_hsync_start_int(7), + R => h_count1 + ); +\DET_HSYNC.det_hsync_start_int_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hsync_start_int_2, + D => L(3), + Q => det_hsync_start_int(8), + R => h_count1 + ); +\DET_HSYNC.det_hsync_start_int_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hsync_start_int_2, + D => L(2), + Q => det_hsync_start_int(9), + R => h_count1 + ); +\DET_HSYNC.hsync_count[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAEA" + ) + port map ( + I0 => h_count1, + I1 => \^det_ce\, + I2 => hsync_d, + I3 => hsync_d2, + O => \DET_HSYNC.hsync_count[0]_i_1_n_0\ + ); +\DET_HSYNC.hsync_count[0]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^det_ce\, + I1 => hsync_d, + O => \DET_HSYNC.hsync_count[0]_i_2_n_0\ + ); +\DET_HSYNC.hsync_count[0]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \DET_HSYNC.hsync_count_reg\(3), + O => \DET_HSYNC.hsync_count[0]_i_4_n_0\ + ); +\DET_HSYNC.hsync_count[0]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \DET_HSYNC.hsync_count_reg\(2), + O => \DET_HSYNC.hsync_count[0]_i_5_n_0\ + ); +\DET_HSYNC.hsync_count[0]_i_6\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \DET_HSYNC.hsync_count_reg\(1), + O => \DET_HSYNC.hsync_count[0]_i_6_n_0\ + ); +\DET_HSYNC.hsync_count[0]_i_7\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \DET_HSYNC.hsync_count_reg\(0), + O => \DET_HSYNC.hsync_count[0]_i_7_n_0\ + ); +\DET_HSYNC.hsync_count[4]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \DET_HSYNC.hsync_count_reg\(7), + O => \DET_HSYNC.hsync_count[4]_i_2_n_0\ + ); +\DET_HSYNC.hsync_count[4]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \DET_HSYNC.hsync_count_reg\(6), + O => \DET_HSYNC.hsync_count[4]_i_3_n_0\ + ); +\DET_HSYNC.hsync_count[4]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \DET_HSYNC.hsync_count_reg\(5), + O => \DET_HSYNC.hsync_count[4]_i_4_n_0\ + ); +\DET_HSYNC.hsync_count[4]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \DET_HSYNC.hsync_count_reg\(4), + O => \DET_HSYNC.hsync_count[4]_i_5_n_0\ + ); +\DET_HSYNC.hsync_count[8]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \DET_HSYNC.hsync_count_reg\(11), + O => \DET_HSYNC.hsync_count[8]_i_2_n_0\ + ); +\DET_HSYNC.hsync_count[8]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \DET_HSYNC.hsync_count_reg\(10), + O => \DET_HSYNC.hsync_count[8]_i_3_n_0\ + ); +\DET_HSYNC.hsync_count[8]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \DET_HSYNC.hsync_count_reg\(9), + O => \DET_HSYNC.hsync_count[8]_i_4_n_0\ + ); +\DET_HSYNC.hsync_count[8]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \DET_HSYNC.hsync_count_reg\(8), + O => \DET_HSYNC.hsync_count[8]_i_5_n_0\ + ); +\DET_HSYNC.hsync_count_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \DET_HSYNC.hsync_count[0]_i_2_n_0\, + D => \DET_HSYNC.hsync_count_reg[0]_i_3_n_7\, + Q => \DET_HSYNC.hsync_count_reg\(0), + R => \DET_HSYNC.hsync_count[0]_i_1_n_0\ + ); +\DET_HSYNC.hsync_count_reg[0]_i_3\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \DET_HSYNC.hsync_count_reg[0]_i_3_n_0\, + CO(2) => \DET_HSYNC.hsync_count_reg[0]_i_3_n_1\, + CO(1) => \DET_HSYNC.hsync_count_reg[0]_i_3_n_2\, + CO(0) => \DET_HSYNC.hsync_count_reg[0]_i_3_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \DET_HSYNC.hsync_count_reg[0]_i_3_n_4\, + O(2) => \DET_HSYNC.hsync_count_reg[0]_i_3_n_5\, + O(1) => \DET_HSYNC.hsync_count_reg[0]_i_3_n_6\, + O(0) => \DET_HSYNC.hsync_count_reg[0]_i_3_n_7\, + S(3) => \DET_HSYNC.hsync_count[0]_i_4_n_0\, + S(2) => \DET_HSYNC.hsync_count[0]_i_5_n_0\, + S(1) => \DET_HSYNC.hsync_count[0]_i_6_n_0\, + S(0) => \DET_HSYNC.hsync_count[0]_i_7_n_0\ + ); +\DET_HSYNC.hsync_count_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \DET_HSYNC.hsync_count[0]_i_2_n_0\, + D => \DET_HSYNC.hsync_count_reg[8]_i_1_n_5\, + Q => \DET_HSYNC.hsync_count_reg\(10), + R => \DET_HSYNC.hsync_count[0]_i_1_n_0\ + ); +\DET_HSYNC.hsync_count_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \DET_HSYNC.hsync_count[0]_i_2_n_0\, + D => \DET_HSYNC.hsync_count_reg[8]_i_1_n_4\, + Q => \DET_HSYNC.hsync_count_reg\(11), + R => \DET_HSYNC.hsync_count[0]_i_1_n_0\ + ); +\DET_HSYNC.hsync_count_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \DET_HSYNC.hsync_count[0]_i_2_n_0\, + D => \DET_HSYNC.hsync_count_reg[0]_i_3_n_6\, + Q => \DET_HSYNC.hsync_count_reg\(1), + R => \DET_HSYNC.hsync_count[0]_i_1_n_0\ + ); +\DET_HSYNC.hsync_count_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \DET_HSYNC.hsync_count[0]_i_2_n_0\, + D => \DET_HSYNC.hsync_count_reg[0]_i_3_n_5\, + Q => \DET_HSYNC.hsync_count_reg\(2), + R => \DET_HSYNC.hsync_count[0]_i_1_n_0\ + ); +\DET_HSYNC.hsync_count_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \DET_HSYNC.hsync_count[0]_i_2_n_0\, + D => \DET_HSYNC.hsync_count_reg[0]_i_3_n_4\, + Q => \DET_HSYNC.hsync_count_reg\(3), + R => \DET_HSYNC.hsync_count[0]_i_1_n_0\ + ); +\DET_HSYNC.hsync_count_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \DET_HSYNC.hsync_count[0]_i_2_n_0\, + D => \DET_HSYNC.hsync_count_reg[4]_i_1_n_7\, + Q => \DET_HSYNC.hsync_count_reg\(4), + R => \DET_HSYNC.hsync_count[0]_i_1_n_0\ + ); +\DET_HSYNC.hsync_count_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \DET_HSYNC.hsync_count_reg[0]_i_3_n_0\, + CO(3) => \DET_HSYNC.hsync_count_reg[4]_i_1_n_0\, + CO(2) => \DET_HSYNC.hsync_count_reg[4]_i_1_n_1\, + CO(1) => \DET_HSYNC.hsync_count_reg[4]_i_1_n_2\, + CO(0) => \DET_HSYNC.hsync_count_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \DET_HSYNC.hsync_count_reg[4]_i_1_n_4\, + O(2) => \DET_HSYNC.hsync_count_reg[4]_i_1_n_5\, + O(1) => \DET_HSYNC.hsync_count_reg[4]_i_1_n_6\, + O(0) => \DET_HSYNC.hsync_count_reg[4]_i_1_n_7\, + S(3) => \DET_HSYNC.hsync_count[4]_i_2_n_0\, + S(2) => \DET_HSYNC.hsync_count[4]_i_3_n_0\, + S(1) => \DET_HSYNC.hsync_count[4]_i_4_n_0\, + S(0) => \DET_HSYNC.hsync_count[4]_i_5_n_0\ + ); +\DET_HSYNC.hsync_count_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \DET_HSYNC.hsync_count[0]_i_2_n_0\, + D => \DET_HSYNC.hsync_count_reg[4]_i_1_n_6\, + Q => \DET_HSYNC.hsync_count_reg\(5), + R => \DET_HSYNC.hsync_count[0]_i_1_n_0\ + ); +\DET_HSYNC.hsync_count_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \DET_HSYNC.hsync_count[0]_i_2_n_0\, + D => \DET_HSYNC.hsync_count_reg[4]_i_1_n_5\, + Q => \DET_HSYNC.hsync_count_reg\(6), + R => \DET_HSYNC.hsync_count[0]_i_1_n_0\ + ); +\DET_HSYNC.hsync_count_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \DET_HSYNC.hsync_count[0]_i_2_n_0\, + D => \DET_HSYNC.hsync_count_reg[4]_i_1_n_4\, + Q => \DET_HSYNC.hsync_count_reg\(7), + R => \DET_HSYNC.hsync_count[0]_i_1_n_0\ + ); +\DET_HSYNC.hsync_count_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \DET_HSYNC.hsync_count[0]_i_2_n_0\, + D => \DET_HSYNC.hsync_count_reg[8]_i_1_n_7\, + Q => \DET_HSYNC.hsync_count_reg\(8), + R => \DET_HSYNC.hsync_count[0]_i_1_n_0\ + ); +\DET_HSYNC.hsync_count_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \DET_HSYNC.hsync_count_reg[4]_i_1_n_0\, + CO(3) => \NLW_DET_HSYNC.hsync_count_reg[8]_i_1_CO_UNCONNECTED\(3), + CO(2) => \DET_HSYNC.hsync_count_reg[8]_i_1_n_1\, + CO(1) => \DET_HSYNC.hsync_count_reg[8]_i_1_n_2\, + CO(0) => \DET_HSYNC.hsync_count_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \DET_HSYNC.hsync_count_reg[8]_i_1_n_4\, + O(2) => \DET_HSYNC.hsync_count_reg[8]_i_1_n_5\, + O(1) => \DET_HSYNC.hsync_count_reg[8]_i_1_n_6\, + O(0) => \DET_HSYNC.hsync_count_reg[8]_i_1_n_7\, + S(3) => \DET_HSYNC.hsync_count[8]_i_2_n_0\, + S(2) => \DET_HSYNC.hsync_count[8]_i_3_n_0\, + S(1) => \DET_HSYNC.hsync_count[8]_i_4_n_0\, + S(0) => \DET_HSYNC.hsync_count[8]_i_5_n_0\ + ); +\DET_HSYNC.hsync_count_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \DET_HSYNC.hsync_count[0]_i_2_n_0\, + D => \DET_HSYNC.hsync_count_reg[8]_i_1_n_6\, + Q => \DET_HSYNC.hsync_count_reg\(9), + R => \DET_HSYNC.hsync_count[0]_i_1_n_0\ + ); +\DET_HSYNC.hsync_d2_reg\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => hsync_d, + Q => hsync_d2, + R => h_count1 + ); +\DET_HSYNC.hsync_d_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F5F7" + ) + port map ( + I0 => resetn_out, + I1 => \genr_control_regs[0]\(1), + I2 => core_d_out, + I3 => \genr_control_regs[0]\(0), + O => h_count1 + ); +\DET_HSYNC.hsync_d_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => clken, + I1 => det_clken, + O => \^det_ce\ + ); +\DET_HSYNC.hsync_d_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => hsync_in, + I1 => \^time_status_regs[3]\(1), + O => line_end + ); +\DET_HSYNC.hsync_d_reg\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => line_end, + Q => hsync_d, + R => h_count1 + ); +\DET_VACTIVE.active_line_d_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EFFEFFFF20020000" + ) + port map ( + I0 => active_line, + I1 => line_end_d_reg_n_0, + I2 => hsync_in, + I3 => \^time_status_regs[3]\(1), + I4 => \^det_ce\, + I5 => active_line_d, + O => \DET_VACTIVE.active_line_d_i_1_n_0\ + ); +\DET_VACTIVE.active_line_d_reg\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => '1', + D => \DET_VACTIVE.active_line_d_i_1_n_0\, + Q => active_line_d, + R => h_count1 + ); +\DET_VACTIVE.active_line_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"77F700C0" + ) + port map ( + I0 => line_end_d_reg_n_0, + I1 => \^det_ce\, + I2 => active_video_d, + I3 => active_video_d2, + I4 => active_line, + O => \DET_VACTIVE.active_line_i_1_n_0\ + ); +\DET_VACTIVE.active_line_reg\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => '1', + D => \DET_VACTIVE.active_line_i_1_n_0\, + Q => active_line, + R => h_count1 + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0_vsync_lock_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000C000A000A" + ) + port map ( + I0 => det_v0_vsync_lock, + I1 => p_1_in, + I2 => h_count1, + I3 => lost_lock, + I4 => \det_v0_vsync_lock__0\, + I5 => \^det_ce\, + O => \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0_vsync_lock_i_1_n_0\ + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0_vsync_lock_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \neqOp_inferred__3/i__carry_n_0\, + I1 => neqOp0_out, + I2 => \neqOp_inferred__1/i__carry_n_0\, + I3 => neqOp, + O => \det_v0_vsync_lock__0\ + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0_vsync_lock_reg\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => '1', + D => \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0_vsync_lock_i_1_n_0\, + Q => det_v0_vsync_lock, + R => '0' + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_hori_last_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => vsync_delay, + D => det_v0bp_start_hori_int(0), + Q => det_v0bp_start_hori_last(0), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_hori_last_reg[10]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => vsync_delay, + D => det_v0bp_start_hori_int(10), + Q => det_v0bp_start_hori_last(10), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_hori_last_reg[11]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => vsync_delay, + D => det_v0bp_start_hori_int(11), + Q => det_v0bp_start_hori_last(11), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_hori_last_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => vsync_delay, + D => det_v0bp_start_hori_int(1), + Q => det_v0bp_start_hori_last(1), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_hori_last_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => vsync_delay, + D => det_v0bp_start_hori_int(2), + Q => det_v0bp_start_hori_last(2), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_hori_last_reg[3]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => vsync_delay, + D => det_v0bp_start_hori_int(3), + Q => det_v0bp_start_hori_last(3), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_hori_last_reg[4]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => vsync_delay, + D => det_v0bp_start_hori_int(4), + Q => det_v0bp_start_hori_last(4), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_hori_last_reg[5]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => vsync_delay, + D => det_v0bp_start_hori_int(5), + Q => det_v0bp_start_hori_last(5), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_hori_last_reg[6]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => vsync_delay, + D => det_v0bp_start_hori_int(6), + Q => det_v0bp_start_hori_last(6), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_hori_last_reg[7]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => vsync_delay, + D => det_v0bp_start_hori_int(7), + Q => det_v0bp_start_hori_last(7), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_hori_last_reg[8]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => vsync_delay, + D => det_v0bp_start_hori_int(8), + Q => det_v0bp_start_hori_last(8), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_hori_last_reg[9]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => vsync_delay, + D => det_v0bp_start_hori_int(9), + Q => det_v0bp_start_hori_last(9), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_last_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => vsync_delay, + D => det_v0bp_start_int(0), + Q => det_v0bp_start_last(0), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_last_reg[10]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => vsync_delay, + D => det_v0bp_start_int(10), + Q => det_v0bp_start_last(10), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_last_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => vsync_delay, + D => det_v0bp_start_int(1), + Q => det_v0bp_start_last(1), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_last_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => vsync_delay, + D => det_v0bp_start_int(2), + Q => det_v0bp_start_last(2), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_last_reg[3]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => vsync_delay, + D => det_v0bp_start_int(3), + Q => det_v0bp_start_last(3), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_last_reg[4]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => vsync_delay, + D => det_v0bp_start_int(4), + Q => det_v0bp_start_last(4), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_last_reg[5]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => vsync_delay, + D => det_v0bp_start_int(5), + Q => det_v0bp_start_last(5), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_last_reg[6]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => vsync_delay, + D => det_v0bp_start_int(6), + Q => det_v0bp_start_last(6), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_last_reg[7]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => vsync_delay, + D => det_v0bp_start_int(7), + Q => det_v0bp_start_last(7), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_last_reg[8]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => vsync_delay, + D => det_v0bp_start_int(8), + Q => det_v0bp_start_last(8), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0bp_start_last_reg[9]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => vsync_delay, + D => det_v0bp_start_int(9), + Q => det_v0bp_start_last(9), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_hori_last_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0\, + D => det_v0sync_start_hori_int(0), + Q => det_v0sync_start_hori_last(0), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_hori_last_reg[10]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0\, + D => det_v0sync_start_hori_int(10), + Q => det_v0sync_start_hori_last(10), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_hori_last_reg[11]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0\, + D => det_v0sync_start_hori_int(11), + Q => det_v0sync_start_hori_last(11), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_hori_last_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0\, + D => det_v0sync_start_hori_int(1), + Q => det_v0sync_start_hori_last(1), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_hori_last_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0\, + D => det_v0sync_start_hori_int(2), + Q => det_v0sync_start_hori_last(2), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_hori_last_reg[3]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0\, + D => det_v0sync_start_hori_int(3), + Q => det_v0sync_start_hori_last(3), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_hori_last_reg[4]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0\, + D => det_v0sync_start_hori_int(4), + Q => det_v0sync_start_hori_last(4), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_hori_last_reg[5]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0\, + D => det_v0sync_start_hori_int(5), + Q => det_v0sync_start_hori_last(5), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_hori_last_reg[6]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0\, + D => det_v0sync_start_hori_int(6), + Q => det_v0sync_start_hori_last(6), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_hori_last_reg[7]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0\, + D => det_v0sync_start_hori_int(7), + Q => det_v0sync_start_hori_last(7), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_hori_last_reg[8]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0\, + D => det_v0sync_start_hori_int(8), + Q => det_v0sync_start_hori_last(8), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_hori_last_reg[9]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0\, + D => det_v0sync_start_hori_int(9), + Q => det_v0sync_start_hori_last(9), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => \DET_VSYNC.vsync_d2_reg_n_0\, + I1 => \DET_VSYNC.vsync_d_reg_n_0\, + I2 => \^det_ce\, + O => \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0\ + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0\, + D => det_v0sync_start_int(0), + Q => det_v0sync_start_last(0), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last_reg[10]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0\, + D => det_v0sync_start_int(10), + Q => det_v0sync_start_last(10), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0\, + D => det_v0sync_start_int(1), + Q => det_v0sync_start_last(1), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0\, + D => det_v0sync_start_int(2), + Q => det_v0sync_start_last(2), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last_reg[3]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0\, + D => det_v0sync_start_int(3), + Q => det_v0sync_start_last(3), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last_reg[4]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0\, + D => det_v0sync_start_int(4), + Q => det_v0sync_start_last(4), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last_reg[5]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0\, + D => det_v0sync_start_int(5), + Q => det_v0sync_start_last(5), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last_reg[6]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0\, + D => det_v0sync_start_int(6), + Q => det_v0sync_start_last(6), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last_reg[7]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0\, + D => det_v0sync_start_int(7), + Q => det_v0sync_start_last(7), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last_reg[8]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0\, + D => det_v0sync_start_int(8), + Q => det_v0sync_start_last(8), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last_reg[9]\: unisim.vcomponents.FDSE + port map ( + C => clk, + CE => \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_v0sync_start_last[10]_i_1_n_0\, + D => det_v0sync_start_int(9), + Q => det_v0sync_start_last(9), + S => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_vsync_lock_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000E2" + ) + port map ( + I0 => \^vsync_lock_int\, + I1 => \^det_ce\, + I2 => det_v0_vsync_lock, + I3 => lost_lock, + I4 => h_count1, + O => \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_vsync_lock_i_1_n_0\ + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.det_vsync_lock_reg\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => '1', + D => \DET_VSYNC.GEN_DET_VSYNC_LOCK.det_vsync_lock_i_1_n_0\, + Q => \^vsync_lock_int\, + R => '0' + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.vsync_delay[0]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^active_video_lock_int\, + I1 => det_vsync_pol_change, + O => \DET_VSYNC.GEN_DET_VSYNC_LOCK.vsync_delay[0]_i_1_n_0\ + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.vsync_delay[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => \DET_VSYNC.vsync_d_reg_n_0\, + I1 => \DET_VSYNC.vsync_d2_reg_n_0\, + I2 => \^det_ce\, + O => vsync_delay + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.vsync_delay_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => vsync_delay, + D => \DET_VSYNC.GEN_DET_VSYNC_LOCK.vsync_delay[0]_i_1_n_0\, + Q => \DET_VSYNC.GEN_DET_VSYNC_LOCK.vsync_delay_reg_n_0_[0]\, + R => p_5_out + ); +\DET_VSYNC.GEN_DET_VSYNC_LOCK.vsync_delay_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => vsync_delay, + D => \DET_VSYNC.GEN_DET_VSYNC_LOCK.vsync_delay_reg_n_0_[0]\, + Q => p_1_in, + R => p_5_out + ); +\DET_VSYNC.det_v0bp_start_hori_int[11]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"44C4" + ) + port map ( + I0 => \DET_VSYNC.vsync_toggled_reg_n_0\, + I1 => \^det_ce\, + I2 => \DET_VSYNC.vsync_d2_reg_n_0\, + I3 => \DET_VSYNC.vsync_d_reg_n_0\, + O => det_v0bp_start_int_7 + ); +\DET_VSYNC.det_v0bp_start_hori_int_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0bp_start_int_7, + D => \DET_VSYNC.det_v0sync_start_hori_int[0]_i_1_n_0\, + Q => det_v0bp_start_hori_int(0), + R => h_count1 + ); +\DET_VSYNC.det_v0bp_start_hori_int_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0bp_start_int_7, + D => \DET_VSYNC.det_v0sync_start_hori_int[10]_i_1_n_0\, + Q => det_v0bp_start_hori_int(10), + R => h_count1 + ); +\DET_VSYNC.det_v0bp_start_hori_int_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0bp_start_int_7, + D => \DET_VSYNC.det_v0sync_start_hori_int[11]_i_2_n_0\, + Q => det_v0bp_start_hori_int(11), + R => h_count1 + ); +\DET_VSYNC.det_v0bp_start_hori_int_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0bp_start_int_7, + D => \DET_VSYNC.det_v0sync_start_hori_int[1]_i_1_n_0\, + Q => det_v0bp_start_hori_int(1), + R => h_count1 + ); +\DET_VSYNC.det_v0bp_start_hori_int_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0bp_start_int_7, + D => \DET_VSYNC.det_v0sync_start_hori_int[2]_i_1_n_0\, + Q => det_v0bp_start_hori_int(2), + R => h_count1 + ); +\DET_VSYNC.det_v0bp_start_hori_int_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0bp_start_int_7, + D => \DET_VSYNC.det_v0sync_start_hori_int[3]_i_1_n_0\, + Q => det_v0bp_start_hori_int(3), + R => h_count1 + ); +\DET_VSYNC.det_v0bp_start_hori_int_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0bp_start_int_7, + D => \DET_VSYNC.det_v0sync_start_hori_int[4]_i_1_n_0\, + Q => det_v0bp_start_hori_int(4), + R => h_count1 + ); +\DET_VSYNC.det_v0bp_start_hori_int_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0bp_start_int_7, + D => \DET_VSYNC.det_v0sync_start_hori_int[5]_i_1_n_0\, + Q => det_v0bp_start_hori_int(5), + R => h_count1 + ); +\DET_VSYNC.det_v0bp_start_hori_int_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0bp_start_int_7, + D => \DET_VSYNC.det_v0sync_start_hori_int[6]_i_1_n_0\, + Q => det_v0bp_start_hori_int(6), + R => h_count1 + ); +\DET_VSYNC.det_v0bp_start_hori_int_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0bp_start_int_7, + D => \DET_VSYNC.det_v0sync_start_hori_int[7]_i_1_n_0\, + Q => det_v0bp_start_hori_int(7), + R => h_count1 + ); +\DET_VSYNC.det_v0bp_start_hori_int_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0bp_start_int_7, + D => \DET_VSYNC.det_v0sync_start_hori_int[8]_i_1_n_0\, + Q => det_v0bp_start_hori_int(8), + R => h_count1 + ); +\DET_VSYNC.det_v0bp_start_hori_int_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0bp_start_int_7, + D => \DET_VSYNC.det_v0sync_start_hori_int[9]_i_1_n_0\, + Q => det_v0bp_start_hori_int(9), + R => h_count1 + ); +\DET_VSYNC.det_v0bp_start_int[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(0), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + I2 => det_v0active_start_int(0), + O => \DET_VSYNC.det_v0bp_start_int[0]_i_1_n_0\ + ); +\DET_VSYNC.det_v0bp_start_int[10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(10), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + I2 => det_v0active_start_int(10), + O => \DET_VSYNC.det_v0bp_start_int[10]_i_1_n_0\ + ); +\DET_VSYNC.det_v0bp_start_int[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(1), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + I2 => det_v0active_start_int(1), + O => \DET_VSYNC.det_v0bp_start_int[1]_i_1_n_0\ + ); +\DET_VSYNC.det_v0bp_start_int[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(2), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + I2 => det_v0active_start_int(2), + O => \DET_VSYNC.det_v0bp_start_int[2]_i_1_n_0\ + ); +\DET_VSYNC.det_v0bp_start_int[3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(3), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + I2 => det_v0active_start_int(3), + O => \DET_VSYNC.det_v0bp_start_int[3]_i_1_n_0\ + ); +\DET_VSYNC.det_v0bp_start_int[4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(4), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + I2 => det_v0active_start_int(4), + O => \DET_VSYNC.det_v0bp_start_int[4]_i_1_n_0\ + ); +\DET_VSYNC.det_v0bp_start_int[5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(5), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + I2 => det_v0active_start_int(5), + O => \DET_VSYNC.det_v0bp_start_int[5]_i_1_n_0\ + ); +\DET_VSYNC.det_v0bp_start_int[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(6), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + I2 => det_v0active_start_int(6), + O => \DET_VSYNC.det_v0bp_start_int[6]_i_1_n_0\ + ); +\DET_VSYNC.det_v0bp_start_int[7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(7), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + I2 => det_v0active_start_int(7), + O => \DET_VSYNC.det_v0bp_start_int[7]_i_1_n_0\ + ); +\DET_VSYNC.det_v0bp_start_int[8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(8), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + I2 => det_v0active_start_int(8), + O => \DET_VSYNC.det_v0bp_start_int[8]_i_1_n_0\ + ); +\DET_VSYNC.det_v0bp_start_int[9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(9), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + I2 => det_v0active_start_int(9), + O => \DET_VSYNC.det_v0bp_start_int[9]_i_1_n_0\ + ); +\DET_VSYNC.det_v0bp_start_int_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0bp_start_int_7, + D => \DET_VSYNC.det_v0bp_start_int[0]_i_1_n_0\, + Q => det_v0bp_start_int(0), + R => h_count1 + ); +\DET_VSYNC.det_v0bp_start_int_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0bp_start_int_7, + D => \DET_VSYNC.det_v0bp_start_int[10]_i_1_n_0\, + Q => det_v0bp_start_int(10), + R => h_count1 + ); +\DET_VSYNC.det_v0bp_start_int_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0bp_start_int_7, + D => \DET_VSYNC.det_v0bp_start_int[1]_i_1_n_0\, + Q => det_v0bp_start_int(1), + R => h_count1 + ); +\DET_VSYNC.det_v0bp_start_int_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0bp_start_int_7, + D => \DET_VSYNC.det_v0bp_start_int[2]_i_1_n_0\, + Q => det_v0bp_start_int(2), + R => h_count1 + ); +\DET_VSYNC.det_v0bp_start_int_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0bp_start_int_7, + D => \DET_VSYNC.det_v0bp_start_int[3]_i_1_n_0\, + Q => det_v0bp_start_int(3), + R => h_count1 + ); +\DET_VSYNC.det_v0bp_start_int_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0bp_start_int_7, + D => \DET_VSYNC.det_v0bp_start_int[4]_i_1_n_0\, + Q => det_v0bp_start_int(4), + R => h_count1 + ); +\DET_VSYNC.det_v0bp_start_int_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0bp_start_int_7, + D => \DET_VSYNC.det_v0bp_start_int[5]_i_1_n_0\, + Q => det_v0bp_start_int(5), + R => h_count1 + ); +\DET_VSYNC.det_v0bp_start_int_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0bp_start_int_7, + D => \DET_VSYNC.det_v0bp_start_int[6]_i_1_n_0\, + Q => det_v0bp_start_int(6), + R => h_count1 + ); +\DET_VSYNC.det_v0bp_start_int_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0bp_start_int_7, + D => \DET_VSYNC.det_v0bp_start_int[7]_i_1_n_0\, + Q => det_v0bp_start_int(7), + R => h_count1 + ); +\DET_VSYNC.det_v0bp_start_int_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0bp_start_int_7, + D => \DET_VSYNC.det_v0bp_start_int[8]_i_1_n_0\, + Q => det_v0bp_start_int(8), + R => h_count1 + ); +\DET_VSYNC.det_v0bp_start_int_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0bp_start_int_7, + D => \DET_VSYNC.det_v0bp_start_int[9]_i_1_n_0\, + Q => det_v0bp_start_int(9), + R => h_count1 + ); +\DET_VSYNC.det_v0sync_start_hori_int[0]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => L(11), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + O => \DET_VSYNC.det_v0sync_start_hori_int[0]_i_1_n_0\ + ); +\DET_VSYNC.det_v0sync_start_hori_int[10]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => L(1), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + O => \DET_VSYNC.det_v0sync_start_hori_int[10]_i_1_n_0\ + ); +\DET_VSYNC.det_v0sync_start_hori_int[11]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"44C4" + ) + port map ( + I0 => \DET_VSYNC.vsync_toggled_reg_n_0\, + I1 => \^det_ce\, + I2 => \DET_VSYNC.vsync_d_reg_n_0\, + I3 => \DET_VSYNC.vsync_d2_reg_n_0\, + O => det_v0sync_start_int_4 + ); +\DET_VSYNC.det_v0sync_start_hori_int[11]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => L(0), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + O => \DET_VSYNC.det_v0sync_start_hori_int[11]_i_2_n_0\ + ); +\DET_VSYNC.det_v0sync_start_hori_int[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => L(10), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + O => \DET_VSYNC.det_v0sync_start_hori_int[1]_i_1_n_0\ + ); +\DET_VSYNC.det_v0sync_start_hori_int[2]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => L(9), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + O => \DET_VSYNC.det_v0sync_start_hori_int[2]_i_1_n_0\ + ); +\DET_VSYNC.det_v0sync_start_hori_int[3]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => L(8), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + O => \DET_VSYNC.det_v0sync_start_hori_int[3]_i_1_n_0\ + ); +\DET_VSYNC.det_v0sync_start_hori_int[4]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => L(7), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + O => \DET_VSYNC.det_v0sync_start_hori_int[4]_i_1_n_0\ + ); +\DET_VSYNC.det_v0sync_start_hori_int[5]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => L(6), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + O => \DET_VSYNC.det_v0sync_start_hori_int[5]_i_1_n_0\ + ); +\DET_VSYNC.det_v0sync_start_hori_int[6]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => L(5), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + O => \DET_VSYNC.det_v0sync_start_hori_int[6]_i_1_n_0\ + ); +\DET_VSYNC.det_v0sync_start_hori_int[7]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => L(4), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + O => \DET_VSYNC.det_v0sync_start_hori_int[7]_i_1_n_0\ + ); +\DET_VSYNC.det_v0sync_start_hori_int[8]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => L(3), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + O => \DET_VSYNC.det_v0sync_start_hori_int[8]_i_1_n_0\ + ); +\DET_VSYNC.det_v0sync_start_hori_int[9]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => L(2), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + O => \DET_VSYNC.det_v0sync_start_hori_int[9]_i_1_n_0\ + ); +\DET_VSYNC.det_v0sync_start_hori_int_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0sync_start_int_4, + D => \DET_VSYNC.det_v0sync_start_hori_int[0]_i_1_n_0\, + Q => det_v0sync_start_hori_int(0), + R => h_count1 + ); +\DET_VSYNC.det_v0sync_start_hori_int_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0sync_start_int_4, + D => \DET_VSYNC.det_v0sync_start_hori_int[10]_i_1_n_0\, + Q => det_v0sync_start_hori_int(10), + R => h_count1 + ); +\DET_VSYNC.det_v0sync_start_hori_int_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0sync_start_int_4, + D => \DET_VSYNC.det_v0sync_start_hori_int[11]_i_2_n_0\, + Q => det_v0sync_start_hori_int(11), + R => h_count1 + ); +\DET_VSYNC.det_v0sync_start_hori_int_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0sync_start_int_4, + D => \DET_VSYNC.det_v0sync_start_hori_int[1]_i_1_n_0\, + Q => det_v0sync_start_hori_int(1), + R => h_count1 + ); +\DET_VSYNC.det_v0sync_start_hori_int_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0sync_start_int_4, + D => \DET_VSYNC.det_v0sync_start_hori_int[2]_i_1_n_0\, + Q => det_v0sync_start_hori_int(2), + R => h_count1 + ); +\DET_VSYNC.det_v0sync_start_hori_int_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0sync_start_int_4, + D => \DET_VSYNC.det_v0sync_start_hori_int[3]_i_1_n_0\, + Q => det_v0sync_start_hori_int(3), + R => h_count1 + ); +\DET_VSYNC.det_v0sync_start_hori_int_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0sync_start_int_4, + D => \DET_VSYNC.det_v0sync_start_hori_int[4]_i_1_n_0\, + Q => det_v0sync_start_hori_int(4), + R => h_count1 + ); +\DET_VSYNC.det_v0sync_start_hori_int_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0sync_start_int_4, + D => \DET_VSYNC.det_v0sync_start_hori_int[5]_i_1_n_0\, + Q => det_v0sync_start_hori_int(5), + R => h_count1 + ); +\DET_VSYNC.det_v0sync_start_hori_int_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0sync_start_int_4, + D => \DET_VSYNC.det_v0sync_start_hori_int[6]_i_1_n_0\, + Q => det_v0sync_start_hori_int(6), + R => h_count1 + ); +\DET_VSYNC.det_v0sync_start_hori_int_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0sync_start_int_4, + D => \DET_VSYNC.det_v0sync_start_hori_int[7]_i_1_n_0\, + Q => det_v0sync_start_hori_int(7), + R => h_count1 + ); +\DET_VSYNC.det_v0sync_start_hori_int_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0sync_start_int_4, + D => \DET_VSYNC.det_v0sync_start_hori_int[8]_i_1_n_0\, + Q => det_v0sync_start_hori_int(8), + R => h_count1 + ); +\DET_VSYNC.det_v0sync_start_hori_int_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0sync_start_int_4, + D => \DET_VSYNC.det_v0sync_start_hori_int[9]_i_1_n_0\, + Q => det_v0sync_start_hori_int(9), + R => h_count1 + ); +\DET_VSYNC.det_v0sync_start_int[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(0), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + I2 => \^time_status_regs_int_reg[0]\(0), + O => \DET_VSYNC.det_v0sync_start_int[0]_i_1_n_0\ + ); +\DET_VSYNC.det_v0sync_start_int[10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(10), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + I2 => \^time_status_regs_int_reg[0]\(10), + O => \DET_VSYNC.det_v0sync_start_int[10]_i_1_n_0\ + ); +\DET_VSYNC.det_v0sync_start_int[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(1), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + I2 => \^time_status_regs_int_reg[0]\(1), + O => \DET_VSYNC.det_v0sync_start_int[1]_i_1_n_0\ + ); +\DET_VSYNC.det_v0sync_start_int[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(2), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + I2 => \^time_status_regs_int_reg[0]\(2), + O => \DET_VSYNC.det_v0sync_start_int[2]_i_1_n_0\ + ); +\DET_VSYNC.det_v0sync_start_int[3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(3), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + I2 => \^time_status_regs_int_reg[0]\(3), + O => \DET_VSYNC.det_v0sync_start_int[3]_i_1_n_0\ + ); +\DET_VSYNC.det_v0sync_start_int[4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(4), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + I2 => \^time_status_regs_int_reg[0]\(4), + O => \DET_VSYNC.det_v0sync_start_int[4]_i_1_n_0\ + ); +\DET_VSYNC.det_v0sync_start_int[5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(5), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + I2 => \^time_status_regs_int_reg[0]\(5), + O => \DET_VSYNC.det_v0sync_start_int[5]_i_1_n_0\ + ); +\DET_VSYNC.det_v0sync_start_int[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(6), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + I2 => \^time_status_regs_int_reg[0]\(6), + O => \DET_VSYNC.det_v0sync_start_int[6]_i_1_n_0\ + ); +\DET_VSYNC.det_v0sync_start_int[7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(7), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + I2 => \^time_status_regs_int_reg[0]\(7), + O => \DET_VSYNC.det_v0sync_start_int[7]_i_1_n_0\ + ); +\DET_VSYNC.det_v0sync_start_int[8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(8), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + I2 => \^time_status_regs_int_reg[0]\(8), + O => \DET_VSYNC.det_v0sync_start_int[8]_i_1_n_0\ + ); +\DET_VSYNC.det_v0sync_start_int[9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(9), + I1 => \DET_VSYNC.vsync_toggled_reg_n_0\, + I2 => \^time_status_regs_int_reg[0]\(9), + O => \DET_VSYNC.det_v0sync_start_int[9]_i_1_n_0\ + ); +\DET_VSYNC.det_v0sync_start_int_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0sync_start_int_4, + D => \DET_VSYNC.det_v0sync_start_int[0]_i_1_n_0\, + Q => det_v0sync_start_int(0), + R => h_count1 + ); +\DET_VSYNC.det_v0sync_start_int_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0sync_start_int_4, + D => \DET_VSYNC.det_v0sync_start_int[10]_i_1_n_0\, + Q => det_v0sync_start_int(10), + R => h_count1 + ); +\DET_VSYNC.det_v0sync_start_int_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0sync_start_int_4, + D => \DET_VSYNC.det_v0sync_start_int[1]_i_1_n_0\, + Q => det_v0sync_start_int(1), + R => h_count1 + ); +\DET_VSYNC.det_v0sync_start_int_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0sync_start_int_4, + D => \DET_VSYNC.det_v0sync_start_int[2]_i_1_n_0\, + Q => det_v0sync_start_int(2), + R => h_count1 + ); +\DET_VSYNC.det_v0sync_start_int_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0sync_start_int_4, + D => \DET_VSYNC.det_v0sync_start_int[3]_i_1_n_0\, + Q => det_v0sync_start_int(3), + R => h_count1 + ); +\DET_VSYNC.det_v0sync_start_int_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0sync_start_int_4, + D => \DET_VSYNC.det_v0sync_start_int[4]_i_1_n_0\, + Q => det_v0sync_start_int(4), + R => h_count1 + ); +\DET_VSYNC.det_v0sync_start_int_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0sync_start_int_4, + D => \DET_VSYNC.det_v0sync_start_int[5]_i_1_n_0\, + Q => det_v0sync_start_int(5), + R => h_count1 + ); +\DET_VSYNC.det_v0sync_start_int_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0sync_start_int_4, + D => \DET_VSYNC.det_v0sync_start_int[6]_i_1_n_0\, + Q => det_v0sync_start_int(6), + R => h_count1 + ); +\DET_VSYNC.det_v0sync_start_int_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0sync_start_int_4, + D => \DET_VSYNC.det_v0sync_start_int[7]_i_1_n_0\, + Q => det_v0sync_start_int(7), + R => h_count1 + ); +\DET_VSYNC.det_v0sync_start_int_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0sync_start_int_4, + D => \DET_VSYNC.det_v0sync_start_int[8]_i_1_n_0\, + Q => det_v0sync_start_int(8), + R => h_count1 + ); +\DET_VSYNC.det_v0sync_start_int_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0sync_start_int_4, + D => \DET_VSYNC.det_v0sync_start_int[9]_i_1_n_0\, + Q => det_v0sync_start_int(9), + R => h_count1 + ); +\DET_VSYNC.det_vsync_pol_change_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E0" + ) + port map ( + I0 => \DET_VSYNC.det_vsync_pol_change_i_2_n_0\, + I1 => det_v0total_int(10), + I2 => gtOp29_in, + O => p_30_out + ); +\DET_VSYNC.det_vsync_pol_change_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFEFFFEFFFE" + ) + port map ( + I0 => \DET_VSYNC.det_vsync_pol_change_i_3_n_0\, + I1 => det_v0total_int(8), + I2 => det_v0total_int(7), + I3 => det_v0total_int(9), + I4 => det_v0total_int(6), + I5 => det_v0total_int(5), + O => \DET_VSYNC.det_vsync_pol_change_i_2_n_0\ + ); +\DET_VSYNC.det_vsync_pol_change_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAAAAAAAA8" + ) + port map ( + I0 => det_v0total_int(6), + I1 => det_v0total_int(3), + I2 => det_v0total_int(2), + I3 => det_v0total_int(1), + I4 => det_v0total_int(0), + I5 => det_v0total_int(4), + O => \DET_VSYNC.det_vsync_pol_change_i_3_n_0\ + ); +\DET_VSYNC.det_vsync_pol_change_reg\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => p_30_out, + Q => det_vsync_pol_change, + R => h_count1 + ); +\DET_VSYNC.det_vsync_pol_int_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"DFFF2000" + ) + port map ( + I0 => det_vsync_pol_change, + I1 => \DET_VSYNC.vsync_d_reg_n_0\, + I2 => \DET_VSYNC.vsync_d2_reg_n_0\, + I3 => \^det_ce\, + I4 => \^time_status_regs[3]\(0), + O => \DET_VSYNC.det_vsync_pol_int_i_1_n_0\ + ); +\DET_VSYNC.det_vsync_pol_int_reg\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => \DET_VSYNC.det_vsync_pol_int_i_1_n_0\, + Q => \^time_status_regs[3]\(0), + S => h_count1 + ); +\DET_VSYNC.vsync_count[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \DET_VSYNC.vsync_count_reg__0\(0), + O => \plusOp__1\(0) + ); +\DET_VSYNC.vsync_count[10]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF08" + ) + port map ( + I0 => \^det_ce\, + I1 => \DET_VSYNC.vsync_d_reg_n_0\, + I2 => \DET_VSYNC.vsync_d2_reg_n_0\, + I3 => h_count1, + O => \DET_VSYNC.vsync_count[10]_i_1_n_0\ + ); +\DET_VSYNC.vsync_count[10]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00820000" + ) + port map ( + I0 => \DET_VSYNC.vsync_d_reg_n_0\, + I1 => \^time_status_regs[3]\(1), + I2 => hsync_in, + I3 => line_end_d_reg_n_0, + I4 => \^det_ce\, + O => vsync_count + ); +\DET_VSYNC.vsync_count[10]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFFFFFF80000000" + ) + port map ( + I0 => \DET_VSYNC.vsync_count_reg__0\(8), + I1 => \DET_VSYNC.vsync_count_reg__0\(6), + I2 => \DET_VSYNC.vsync_count[10]_i_4_n_0\, + I3 => \DET_VSYNC.vsync_count_reg__0\(7), + I4 => \DET_VSYNC.vsync_count_reg__0\(9), + I5 => \DET_VSYNC.vsync_count_reg__0\(10), + O => \plusOp__1\(10) + ); +\DET_VSYNC.vsync_count[10]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => \DET_VSYNC.vsync_count_reg__0\(5), + I1 => \DET_VSYNC.vsync_count_reg__0\(3), + I2 => \DET_VSYNC.vsync_count_reg__0\(1), + I3 => \DET_VSYNC.vsync_count_reg__0\(0), + I4 => \DET_VSYNC.vsync_count_reg__0\(2), + I5 => \DET_VSYNC.vsync_count_reg__0\(4), + O => \DET_VSYNC.vsync_count[10]_i_4_n_0\ + ); +\DET_VSYNC.vsync_count[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \DET_VSYNC.vsync_count_reg__0\(0), + I1 => \DET_VSYNC.vsync_count_reg__0\(1), + O => \plusOp__1\(1) + ); +\DET_VSYNC.vsync_count[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \DET_VSYNC.vsync_count_reg__0\(0), + I1 => \DET_VSYNC.vsync_count_reg__0\(1), + I2 => \DET_VSYNC.vsync_count_reg__0\(2), + O => \plusOp__1\(2) + ); +\DET_VSYNC.vsync_count[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \DET_VSYNC.vsync_count_reg__0\(1), + I1 => \DET_VSYNC.vsync_count_reg__0\(0), + I2 => \DET_VSYNC.vsync_count_reg__0\(2), + I3 => \DET_VSYNC.vsync_count_reg__0\(3), + O => \plusOp__1\(3) + ); +\DET_VSYNC.vsync_count[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \DET_VSYNC.vsync_count_reg__0\(2), + I1 => \DET_VSYNC.vsync_count_reg__0\(0), + I2 => \DET_VSYNC.vsync_count_reg__0\(1), + I3 => \DET_VSYNC.vsync_count_reg__0\(3), + I4 => \DET_VSYNC.vsync_count_reg__0\(4), + O => \plusOp__1\(4) + ); +\DET_VSYNC.vsync_count[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFFFFFF80000000" + ) + port map ( + I0 => \DET_VSYNC.vsync_count_reg__0\(3), + I1 => \DET_VSYNC.vsync_count_reg__0\(1), + I2 => \DET_VSYNC.vsync_count_reg__0\(0), + I3 => \DET_VSYNC.vsync_count_reg__0\(2), + I4 => \DET_VSYNC.vsync_count_reg__0\(4), + I5 => \DET_VSYNC.vsync_count_reg__0\(5), + O => \plusOp__1\(5) + ); +\DET_VSYNC.vsync_count[6]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \DET_VSYNC.vsync_count[10]_i_4_n_0\, + I1 => \DET_VSYNC.vsync_count_reg__0\(6), + O => \plusOp__1\(6) + ); +\DET_VSYNC.vsync_count[7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \DET_VSYNC.vsync_count[10]_i_4_n_0\, + I1 => \DET_VSYNC.vsync_count_reg__0\(6), + I2 => \DET_VSYNC.vsync_count_reg__0\(7), + O => \plusOp__1\(7) + ); +\DET_VSYNC.vsync_count[8]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \DET_VSYNC.vsync_count_reg__0\(6), + I1 => \DET_VSYNC.vsync_count[10]_i_4_n_0\, + I2 => \DET_VSYNC.vsync_count_reg__0\(7), + I3 => \DET_VSYNC.vsync_count_reg__0\(8), + O => \plusOp__1\(8) + ); +\DET_VSYNC.vsync_count[9]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \DET_VSYNC.vsync_count_reg__0\(7), + I1 => \DET_VSYNC.vsync_count[10]_i_4_n_0\, + I2 => \DET_VSYNC.vsync_count_reg__0\(6), + I3 => \DET_VSYNC.vsync_count_reg__0\(8), + I4 => \DET_VSYNC.vsync_count_reg__0\(9), + O => \plusOp__1\(9) + ); +\DET_VSYNC.vsync_count_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => vsync_count, + D => \plusOp__1\(0), + Q => \DET_VSYNC.vsync_count_reg__0\(0), + R => \DET_VSYNC.vsync_count[10]_i_1_n_0\ + ); +\DET_VSYNC.vsync_count_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => vsync_count, + D => \plusOp__1\(10), + Q => \DET_VSYNC.vsync_count_reg__0\(10), + R => \DET_VSYNC.vsync_count[10]_i_1_n_0\ + ); +\DET_VSYNC.vsync_count_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => vsync_count, + D => \plusOp__1\(1), + Q => \DET_VSYNC.vsync_count_reg__0\(1), + R => \DET_VSYNC.vsync_count[10]_i_1_n_0\ + ); +\DET_VSYNC.vsync_count_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => vsync_count, + D => \plusOp__1\(2), + Q => \DET_VSYNC.vsync_count_reg__0\(2), + R => \DET_VSYNC.vsync_count[10]_i_1_n_0\ + ); +\DET_VSYNC.vsync_count_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => vsync_count, + D => \plusOp__1\(3), + Q => \DET_VSYNC.vsync_count_reg__0\(3), + R => \DET_VSYNC.vsync_count[10]_i_1_n_0\ + ); +\DET_VSYNC.vsync_count_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => vsync_count, + D => \plusOp__1\(4), + Q => \DET_VSYNC.vsync_count_reg__0\(4), + R => \DET_VSYNC.vsync_count[10]_i_1_n_0\ + ); +\DET_VSYNC.vsync_count_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => vsync_count, + D => \plusOp__1\(5), + Q => \DET_VSYNC.vsync_count_reg__0\(5), + R => \DET_VSYNC.vsync_count[10]_i_1_n_0\ + ); +\DET_VSYNC.vsync_count_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => vsync_count, + D => \plusOp__1\(6), + Q => \DET_VSYNC.vsync_count_reg__0\(6), + R => \DET_VSYNC.vsync_count[10]_i_1_n_0\ + ); +\DET_VSYNC.vsync_count_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => vsync_count, + D => \plusOp__1\(7), + Q => \DET_VSYNC.vsync_count_reg__0\(7), + R => \DET_VSYNC.vsync_count[10]_i_1_n_0\ + ); +\DET_VSYNC.vsync_count_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => vsync_count, + D => \plusOp__1\(8), + Q => \DET_VSYNC.vsync_count_reg__0\(8), + R => \DET_VSYNC.vsync_count[10]_i_1_n_0\ + ); +\DET_VSYNC.vsync_count_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => vsync_count, + D => \plusOp__1\(9), + Q => \DET_VSYNC.vsync_count_reg__0\(9), + R => \DET_VSYNC.vsync_count[10]_i_1_n_0\ + ); +\DET_VSYNC.vsync_d2_reg\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => \DET_VSYNC.vsync_d_reg_n_0\, + Q => \DET_VSYNC.vsync_d2_reg_n_0\, + R => h_count1 + ); +\DET_VSYNC.vsync_d_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => vsync_in, + I1 => \^time_status_regs[3]\(0), + O => \DET_VSYNC.vsync_d_i_1_n_0\ + ); +\DET_VSYNC.vsync_d_reg\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => \DET_VSYNC.vsync_d_i_1_n_0\, + Q => \DET_VSYNC.vsync_d_reg_n_0\, + R => h_count1 + ); +\DET_VSYNC.vsync_rose_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF08" + ) + port map ( + I0 => \^det_ce\, + I1 => \DET_VSYNC.vsync_d_reg_n_0\, + I2 => \DET_VSYNC.vsync_d2_reg_n_0\, + I3 => vsync_rose, + O => \DET_VSYNC.vsync_rose_i_1_n_0\ + ); +\DET_VSYNC.vsync_rose_reg\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => '1', + D => \DET_VSYNC.vsync_rose_i_1_n_0\, + Q => vsync_rose, + R => h_count1 + ); +\DET_VSYNC.vsync_toggled_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EFFF2000" + ) + port map ( + I0 => vsync_rose, + I1 => \DET_VSYNC.vsync_d_reg_n_0\, + I2 => \DET_VSYNC.vsync_d2_reg_n_0\, + I3 => \^det_ce\, + I4 => \DET_VSYNC.vsync_toggled_reg_n_0\, + O => \DET_VSYNC.vsync_toggled_i_1_n_0\ + ); +\DET_VSYNC.vsync_toggled_reg\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => '1', + D => \DET_VSYNC.vsync_toggled_i_1_n_0\, + Q => \DET_VSYNC.vsync_toggled_reg_n_0\, + R => h_count1 + ); +\_inferred__11/i__carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \_inferred__11/i__carry_n_0\, + CO(2) => \_inferred__11/i__carry_n_1\, + CO(1) => \_inferred__11/i__carry_n_2\, + CO(0) => \_inferred__11/i__carry_n_3\, + CYINIT => det_v0bp_start_hori_int(0), + DI(3 downto 1) => det_v0bp_start_hori_int(3 downto 1), + DI(0) => \i__carry_i_1__4_n_0\, + O(3 downto 0) => det_v0bp_start_hori_int2(3 downto 0), + S(3) => \i__carry_i_2__11_n_0\, + S(2) => \i__carry_i_3__11_n_0\, + S(1) => \i__carry_i_4__11_n_0\, + S(0) => \i__carry_i_5__4_n_0\ + ); +\_inferred__11/i__carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \_inferred__11/i__carry_n_0\, + CO(3) => \_inferred__11/i__carry__0_n_0\, + CO(2) => \_inferred__11/i__carry__0_n_1\, + CO(1) => \_inferred__11/i__carry__0_n_2\, + CO(0) => \_inferred__11/i__carry__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => det_v0bp_start_hori_int(7 downto 4), + O(3 downto 0) => det_v0bp_start_hori_int2(7 downto 4), + S(3) => \i__carry__0_i_1__5_n_0\, + S(2) => \i__carry__0_i_2__5_n_0\, + S(1) => \i__carry__0_i_3__5_n_0\, + S(0) => \i__carry__0_i_4__5_n_0\ + ); +\_inferred__11/i__carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \_inferred__11/i__carry__0_n_0\, + CO(3) => \NLW__inferred__11/i__carry__1_CO_UNCONNECTED\(3), + CO(2) => \_inferred__11/i__carry__1_n_1\, + CO(1) => \_inferred__11/i__carry__1_n_2\, + CO(0) => \_inferred__11/i__carry__1_n_3\, + CYINIT => '0', + DI(3) => '0', + DI(2 downto 0) => det_v0bp_start_hori_int(10 downto 8), + O(3 downto 0) => det_v0bp_start_hori_int2(11 downto 8), + S(3) => \i__carry__1_i_1__2_n_0\, + S(2) => \i__carry__1_i_2__1_n_0\, + S(1) => \i__carry__1_i_3__1_n_0\, + S(0) => \i__carry__1_i_4__1_n_0\ + ); +\_inferred__8/i__carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \_inferred__8/i__carry_n_0\, + CO(2) => \_inferred__8/i__carry_n_1\, + CO(1) => \_inferred__8/i__carry_n_2\, + CO(0) => \_inferred__8/i__carry_n_3\, + CYINIT => det_v0sync_start_hori_int(0), + DI(3 downto 1) => det_v0sync_start_hori_int(3 downto 1), + DI(0) => \i__carry_i_1__3_n_0\, + O(3 downto 0) => det_v0sync_start_hori_int2(3 downto 0), + S(3) => \i__carry_i_2__10_n_0\, + S(2) => \i__carry_i_3__10_n_0\, + S(1) => \i__carry_i_4__10_n_0\, + S(0) => \i__carry_i_5__3_n_0\ + ); +\_inferred__8/i__carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \_inferred__8/i__carry_n_0\, + CO(3) => \_inferred__8/i__carry__0_n_0\, + CO(2) => \_inferred__8/i__carry__0_n_1\, + CO(1) => \_inferred__8/i__carry__0_n_2\, + CO(0) => \_inferred__8/i__carry__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => det_v0sync_start_hori_int(7 downto 4), + O(3 downto 0) => det_v0sync_start_hori_int2(7 downto 4), + S(3) => \i__carry__0_i_1__4_n_0\, + S(2) => \i__carry__0_i_2__4_n_0\, + S(1) => \i__carry__0_i_3__4_n_0\, + S(0) => \i__carry__0_i_4__4_n_0\ + ); +\_inferred__8/i__carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \_inferred__8/i__carry__0_n_0\, + CO(3) => \NLW__inferred__8/i__carry__1_CO_UNCONNECTED\(3), + CO(2) => \_inferred__8/i__carry__1_n_1\, + CO(1) => \_inferred__8/i__carry__1_n_2\, + CO(0) => \_inferred__8/i__carry__1_n_3\, + CYINIT => '0', + DI(3) => '0', + DI(2 downto 0) => det_v0sync_start_hori_int(10 downto 8), + O(3 downto 0) => det_v0sync_start_hori_int2(11 downto 8), + S(3) => \i__carry__1_i_1__1_n_0\, + S(2) => \i__carry__1_i_2__0_n_0\, + S(1) => \i__carry__1_i_3__0_n_0\, + S(0) => \i__carry__1_i_4__0_n_0\ + ); +all_lock_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000E2222222" + ) + port map ( + I0 => all_lock, + I1 => \^det_ce\, + I2 => \^vsync_lock_int\, + I3 => \^hsync_lock_int\, + I4 => \^active_video_lock_int\, + I5 => all_lock_d0, + O => all_lock_reg + ); +\det_hactive_start_int[11]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0800" + ) + port map ( + I0 => \^det_ce\, + I1 => active_video_d, + I2 => active_video_d2, + I3 => active_video_toggled, + O => det_hactive_start_int_3 + ); +\det_hactive_start_int_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hactive_start_int_3, + D => L(11), + Q => det_hactive_start_int(0), + R => h_count1 + ); +\det_hactive_start_int_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hactive_start_int_3, + D => L(1), + Q => det_hactive_start_int(10), + R => h_count1 + ); +\det_hactive_start_int_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hactive_start_int_3, + D => L(0), + Q => det_hactive_start_int(11), + R => h_count1 + ); +\det_hactive_start_int_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hactive_start_int_3, + D => L(10), + Q => det_hactive_start_int(1), + R => h_count1 + ); +\det_hactive_start_int_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hactive_start_int_3, + D => L(9), + Q => det_hactive_start_int(2), + R => h_count1 + ); +\det_hactive_start_int_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hactive_start_int_3, + D => L(8), + Q => det_hactive_start_int(3), + R => h_count1 + ); +\det_hactive_start_int_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hactive_start_int_3, + D => L(7), + Q => det_hactive_start_int(4), + R => h_count1 + ); +\det_hactive_start_int_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hactive_start_int_3, + D => L(6), + Q => det_hactive_start_int(5), + R => h_count1 + ); +\det_hactive_start_int_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hactive_start_int_3, + D => L(5), + Q => det_hactive_start_int(6), + R => h_count1 + ); +\det_hactive_start_int_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hactive_start_int_3, + D => L(4), + Q => det_hactive_start_int(7), + R => h_count1 + ); +\det_hactive_start_int_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hactive_start_int_3, + D => L(3), + Q => det_hactive_start_int(8), + R => h_count1 + ); +\det_hactive_start_int_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hactive_start_int_3, + D => L(2), + Q => det_hactive_start_int(9), + R => h_count1 + ); +\det_hbp_start_int2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => \plusOp_inferred__2/i__carry_n_7\, + Q => \^time_status_regs[6]\(12), + R => \^reset\ + ); +\det_hbp_start_int2_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => \plusOp_inferred__2/i__carry__1_n_5\, + Q => \^time_status_regs[6]\(22), + R => \^reset\ + ); +\det_hbp_start_int2_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => \plusOp_inferred__2/i__carry__1_n_4\, + Q => \^time_status_regs[6]\(23), + R => \^reset\ + ); +\det_hbp_start_int2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => \plusOp_inferred__2/i__carry_n_6\, + Q => \^time_status_regs[6]\(13), + R => \^reset\ + ); +\det_hbp_start_int2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => \plusOp_inferred__2/i__carry_n_5\, + Q => \^time_status_regs[6]\(14), + R => \^reset\ + ); +\det_hbp_start_int2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => \plusOp_inferred__2/i__carry_n_4\, + Q => \^time_status_regs[6]\(15), + R => \^reset\ + ); +\det_hbp_start_int2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => \plusOp_inferred__2/i__carry__0_n_7\, + Q => \^time_status_regs[6]\(16), + R => \^reset\ + ); +\det_hbp_start_int2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => \plusOp_inferred__2/i__carry__0_n_6\, + Q => \^time_status_regs[6]\(17), + R => \^reset\ + ); +\det_hbp_start_int2_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => \plusOp_inferred__2/i__carry__0_n_5\, + Q => \^time_status_regs[6]\(18), + R => \^reset\ + ); +\det_hbp_start_int2_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => \plusOp_inferred__2/i__carry__0_n_4\, + Q => \^time_status_regs[6]\(19), + R => \^reset\ + ); +\det_hbp_start_int2_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => \plusOp_inferred__2/i__carry__1_n_7\, + Q => \^time_status_regs[6]\(20), + R => \^reset\ + ); +\det_hbp_start_int2_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => \plusOp_inferred__2/i__carry__1_n_6\, + Q => \^time_status_regs[6]\(21), + R => \^reset\ + ); +\det_hfp_start_int2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => minusOp1_out(0), + Q => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(0), + R => \^reset\ + ); +\det_hfp_start_int2_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => minusOp1_out(10), + Q => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(10), + R => \^reset\ + ); +\det_hfp_start_int2_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => minusOp1_out(11), + Q => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(11), + R => \^reset\ + ); +\det_hfp_start_int2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => minusOp1_out(1), + Q => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(1), + R => \^reset\ + ); +\det_hfp_start_int2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => minusOp1_out(2), + Q => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(2), + R => \^reset\ + ); +\det_hfp_start_int2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => minusOp1_out(3), + Q => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(3), + R => \^reset\ + ); +\det_hfp_start_int2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => minusOp1_out(4), + Q => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(4), + R => \^reset\ + ); +\det_hfp_start_int2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => minusOp1_out(5), + Q => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(5), + R => \^reset\ + ); +\det_hfp_start_int2_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => minusOp1_out(6), + Q => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(6), + R => \^reset\ + ); +\det_hfp_start_int2_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => minusOp1_out(7), + Q => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(7), + R => \^reset\ + ); +\det_hfp_start_int2_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => minusOp1_out(8), + Q => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(8), + R => \^reset\ + ); +\det_hfp_start_int2_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => minusOp1_out(9), + Q => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(9), + R => \^reset\ + ); +\det_hfp_start_int[11]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0800" + ) + port map ( + I0 => active_video_toggled, + I1 => \^det_ce\, + I2 => active_video_d, + I3 => active_video_d2, + O => det_hfp_start_int_8 + ); +\det_hfp_start_int_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hfp_start_int_8, + D => L(11), + Q => det_hfp_start_int(0), + R => h_count1 + ); +\det_hfp_start_int_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hfp_start_int_8, + D => L(1), + Q => det_hfp_start_int(10), + R => h_count1 + ); +\det_hfp_start_int_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hfp_start_int_8, + D => L(0), + Q => det_hfp_start_int(11), + R => h_count1 + ); +\det_hfp_start_int_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hfp_start_int_8, + D => L(10), + Q => det_hfp_start_int(1), + R => h_count1 + ); +\det_hfp_start_int_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hfp_start_int_8, + D => L(9), + Q => det_hfp_start_int(2), + R => h_count1 + ); +\det_hfp_start_int_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hfp_start_int_8, + D => L(8), + Q => det_hfp_start_int(3), + R => h_count1 + ); +\det_hfp_start_int_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hfp_start_int_8, + D => L(7), + Q => det_hfp_start_int(4), + R => h_count1 + ); +\det_hfp_start_int_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hfp_start_int_8, + D => L(6), + Q => det_hfp_start_int(5), + R => h_count1 + ); +\det_hfp_start_int_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hfp_start_int_8, + D => L(5), + Q => det_hfp_start_int(6), + R => h_count1 + ); +\det_hfp_start_int_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hfp_start_int_8, + D => L(4), + Q => det_hfp_start_int(7), + R => h_count1 + ); +\det_hfp_start_int_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hfp_start_int_8, + D => L(3), + Q => det_hfp_start_int(8), + R => h_count1 + ); +\det_hfp_start_int_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_hfp_start_int_8, + D => L(2), + Q => det_hfp_start_int(9), + R => h_count1 + ); +\det_hsync_start_int2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => minusOp0_out(0), + Q => \^time_status_regs[6]\(0), + R => \^reset\ + ); +\det_hsync_start_int2_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => minusOp0_out(10), + Q => \^time_status_regs[6]\(10), + R => \^reset\ + ); +\det_hsync_start_int2_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => minusOp0_out(11), + Q => \^time_status_regs[6]\(11), + R => \^reset\ + ); +\det_hsync_start_int2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => minusOp0_out(1), + Q => \^time_status_regs[6]\(1), + R => \^reset\ + ); +\det_hsync_start_int2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => minusOp0_out(2), + Q => \^time_status_regs[6]\(2), + R => \^reset\ + ); +\det_hsync_start_int2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => minusOp0_out(3), + Q => \^time_status_regs[6]\(3), + R => \^reset\ + ); +\det_hsync_start_int2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => minusOp0_out(4), + Q => \^time_status_regs[6]\(4), + R => \^reset\ + ); +\det_hsync_start_int2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => minusOp0_out(5), + Q => \^time_status_regs[6]\(5), + R => \^reset\ + ); +\det_hsync_start_int2_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => minusOp0_out(6), + Q => \^time_status_regs[6]\(6), + R => \^reset\ + ); +\det_hsync_start_int2_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => minusOp0_out(7), + Q => \^time_status_regs[6]\(7), + R => \^reset\ + ); +\det_hsync_start_int2_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => minusOp0_out(8), + Q => \^time_status_regs[6]\(8), + R => \^reset\ + ); +\det_hsync_start_int2_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => minusOp0_out(9), + Q => \^time_status_regs[6]\(9), + R => \^reset\ + ); +\det_htotal_int2[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_htotal_int(0), + O => plusOp(0) + ); +\det_htotal_int2[11]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => det_htotal_int(11), + O => \det_htotal_int2[11]_i_2_n_0\ + ); +\det_htotal_int2[11]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => det_htotal_int(10), + O => \det_htotal_int2[11]_i_3_n_0\ + ); +\det_htotal_int2[11]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => det_htotal_int(9), + O => \det_htotal_int2[11]_i_4_n_0\ + ); +\det_htotal_int2[4]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => det_htotal_int(4), + O => \det_htotal_int2[4]_i_2_n_0\ + ); +\det_htotal_int2[4]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => det_htotal_int(3), + O => \det_htotal_int2[4]_i_3_n_0\ + ); +\det_htotal_int2[4]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => det_htotal_int(2), + O => \det_htotal_int2[4]_i_4_n_0\ + ); +\det_htotal_int2[4]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => det_htotal_int(1), + O => \det_htotal_int2[4]_i_5_n_0\ + ); +\det_htotal_int2[8]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => det_htotal_int(8), + O => \det_htotal_int2[8]_i_2_n_0\ + ); +\det_htotal_int2[8]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => det_htotal_int(7), + O => \det_htotal_int2[8]_i_3_n_0\ + ); +\det_htotal_int2[8]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => det_htotal_int(6), + O => \det_htotal_int2[8]_i_4_n_0\ + ); +\det_htotal_int2[8]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => det_htotal_int(5), + O => \det_htotal_int2[8]_i_5_n_0\ + ); +\det_htotal_int2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => plusOp(0), + Q => \^q\(0), + R => \^reset\ + ); +\det_htotal_int2_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => plusOp(10), + Q => \^q\(10), + R => \^reset\ + ); +\det_htotal_int2_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => plusOp(11), + Q => \^q\(11), + R => \^reset\ + ); +\det_htotal_int2_reg[11]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \det_htotal_int2_reg[8]_i_1_n_0\, + CO(3 downto 2) => \NLW_det_htotal_int2_reg[11]_i_1_CO_UNCONNECTED\(3 downto 2), + CO(1) => \det_htotal_int2_reg[11]_i_1_n_2\, + CO(0) => \det_htotal_int2_reg[11]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \NLW_det_htotal_int2_reg[11]_i_1_O_UNCONNECTED\(3), + O(2 downto 0) => plusOp(11 downto 9), + S(3) => '0', + S(2) => \det_htotal_int2[11]_i_2_n_0\, + S(1) => \det_htotal_int2[11]_i_3_n_0\, + S(0) => \det_htotal_int2[11]_i_4_n_0\ + ); +\det_htotal_int2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => plusOp(1), + Q => \^q\(1), + R => \^reset\ + ); +\det_htotal_int2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => plusOp(2), + Q => \^q\(2), + R => \^reset\ + ); +\det_htotal_int2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => plusOp(3), + Q => \^q\(3), + R => \^reset\ + ); +\det_htotal_int2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => plusOp(4), + Q => \^q\(4), + R => \^reset\ + ); +\det_htotal_int2_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \det_htotal_int2_reg[4]_i_1_n_0\, + CO(2) => \det_htotal_int2_reg[4]_i_1_n_1\, + CO(1) => \det_htotal_int2_reg[4]_i_1_n_2\, + CO(0) => \det_htotal_int2_reg[4]_i_1_n_3\, + CYINIT => det_htotal_int(0), + DI(3 downto 0) => B"0000", + O(3 downto 0) => plusOp(4 downto 1), + S(3) => \det_htotal_int2[4]_i_2_n_0\, + S(2) => \det_htotal_int2[4]_i_3_n_0\, + S(1) => \det_htotal_int2[4]_i_4_n_0\, + S(0) => \det_htotal_int2[4]_i_5_n_0\ + ); +\det_htotal_int2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => plusOp(5), + Q => \^q\(5), + R => \^reset\ + ); +\det_htotal_int2_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => plusOp(6), + Q => \^q\(6), + R => \^reset\ + ); +\det_htotal_int2_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => plusOp(7), + Q => \^q\(7), + R => \^reset\ + ); +\det_htotal_int2_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => plusOp(8), + Q => \^q\(8), + R => \^reset\ + ); +\det_htotal_int2_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \det_htotal_int2_reg[4]_i_1_n_0\, + CO(3) => \det_htotal_int2_reg[8]_i_1_n_0\, + CO(2) => \det_htotal_int2_reg[8]_i_1_n_1\, + CO(1) => \det_htotal_int2_reg[8]_i_1_n_2\, + CO(0) => \det_htotal_int2_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => plusOp(8 downto 5), + S(3) => \det_htotal_int2[8]_i_2_n_0\, + S(2) => \det_htotal_int2[8]_i_3_n_0\, + S(1) => \det_htotal_int2[8]_i_4_n_0\, + S(0) => \det_htotal_int2[8]_i_5_n_0\ + ); +\det_htotal_int2_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => plusOp(9), + Q => \^q\(9), + R => \^reset\ + ); +\det_htotal_int[11]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2002" + ) + port map ( + I0 => \^det_ce\, + I1 => line_end_d_reg_n_0, + I2 => hsync_in, + I3 => \^time_status_regs[3]\(1), + O => \det_htotal_int[11]_i_1_n_0\ + ); +\det_htotal_int_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => L(11), + Q => det_htotal_int(0), + R => h_count1 + ); +\det_htotal_int_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => L(1), + Q => det_htotal_int(10), + R => h_count1 + ); +\det_htotal_int_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => L(0), + Q => det_htotal_int(11), + R => h_count1 + ); +\det_htotal_int_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => L(10), + Q => det_htotal_int(1), + R => h_count1 + ); +\det_htotal_int_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => L(9), + Q => det_htotal_int(2), + R => h_count1 + ); +\det_htotal_int_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => L(8), + Q => det_htotal_int(3), + R => h_count1 + ); +\det_htotal_int_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => L(7), + Q => det_htotal_int(4), + R => h_count1 + ); +\det_htotal_int_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => L(6), + Q => det_htotal_int(5), + R => h_count1 + ); +\det_htotal_int_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => L(5), + Q => det_htotal_int(6), + R => h_count1 + ); +\det_htotal_int_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => L(4), + Q => det_htotal_int(7), + R => h_count1 + ); +\det_htotal_int_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => L(3), + Q => det_htotal_int(8), + R => h_count1 + ); +\det_htotal_int_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => L(2), + Q => det_htotal_int(9), + R => h_count1 + ); +\det_v0active_start_hori_int2[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E2" + ) + port map ( + I0 => det_hactive_start_int(0), + I1 => \det_v0active_start_hori_int2_reg[0]_i_2_n_3\, + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(0), + O => \det_v0active_start_hori_int2[0]_i_1_n_0\ + ); +\det_v0active_start_hori_int2[0]_i_10\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_hactive_start_int(9), + I1 => det_hactive_start_int(8), + O => \det_v0active_start_hori_int2[0]_i_10_n_0\ + ); +\det_v0active_start_hori_int2[0]_i_11\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_hactive_start_int(7), + I1 => det_hactive_start_int(6), + O => \det_v0active_start_hori_int2[0]_i_11_n_0\ + ); +\det_v0active_start_hori_int2[0]_i_12\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_hactive_start_int(5), + I1 => det_hactive_start_int(4), + O => \det_v0active_start_hori_int2[0]_i_12_n_0\ + ); +\det_v0active_start_hori_int2[0]_i_13\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_hactive_start_int(3), + I1 => det_hactive_start_int(2), + O => \det_v0active_start_hori_int2[0]_i_13_n_0\ + ); +\det_v0active_start_hori_int2[0]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => det_hactive_start_int(10), + I1 => det_hactive_start_int(11), + O => \det_v0active_start_hori_int2[0]_i_4_n_0\ + ); +\det_v0active_start_hori_int2[0]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_hactive_start_int(11), + I1 => det_hactive_start_int(10), + O => \det_v0active_start_hori_int2[0]_i_5_n_0\ + ); +\det_v0active_start_hori_int2[0]_i_6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => det_hactive_start_int(8), + I1 => det_hactive_start_int(9), + O => \det_v0active_start_hori_int2[0]_i_6_n_0\ + ); +\det_v0active_start_hori_int2[0]_i_7\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => det_hactive_start_int(6), + I1 => det_hactive_start_int(7), + O => \det_v0active_start_hori_int2[0]_i_7_n_0\ + ); +\det_v0active_start_hori_int2[0]_i_8\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => det_hactive_start_int(4), + I1 => det_hactive_start_int(5), + O => \det_v0active_start_hori_int2[0]_i_8_n_0\ + ); +\det_v0active_start_hori_int2[0]_i_9\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => det_hactive_start_int(2), + I1 => det_hactive_start_int(3), + O => \det_v0active_start_hori_int2[0]_i_9_n_0\ + ); +\det_v0active_start_hori_int2[11]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(10), + I1 => \det_v0active_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(10), + O => \det_v0active_start_hori_int2[11]_i_2_n_0\ + ); +\det_v0active_start_hori_int2[11]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(9), + I1 => \det_v0active_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(9), + O => \det_v0active_start_hori_int2[11]_i_3_n_0\ + ); +\det_v0active_start_hori_int2[11]_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(8), + I1 => \det_v0active_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(8), + O => \det_v0active_start_hori_int2[11]_i_4_n_0\ + ); +\det_v0active_start_hori_int2[11]_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(11), + I1 => \det_v0active_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(11), + O => \det_v0active_start_hori_int2[11]_i_5_n_0\ + ); +\det_v0active_start_hori_int2[11]_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(10), + I1 => \det_v0active_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(10), + O => \det_v0active_start_hori_int2[11]_i_6_n_0\ + ); +\det_v0active_start_hori_int2[11]_i_7\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(9), + I1 => \det_v0active_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(9), + O => \det_v0active_start_hori_int2[11]_i_7_n_0\ + ); +\det_v0active_start_hori_int2[11]_i_8\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(8), + I1 => \det_v0active_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(8), + O => \det_v0active_start_hori_int2[11]_i_8_n_0\ + ); +\det_v0active_start_hori_int2[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(3), + I1 => \det_v0active_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(3), + O => \det_v0active_start_hori_int2[3]_i_2_n_0\ + ); +\det_v0active_start_hori_int2[3]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(2), + I1 => \det_v0active_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(2), + O => \det_v0active_start_hori_int2[3]_i_3_n_0\ + ); +\det_v0active_start_hori_int2[3]_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(1), + I1 => \det_v0active_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(1), + O => \det_v0active_start_hori_int2[3]_i_4_n_0\ + ); +\det_v0active_start_hori_int2[3]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \det_v0active_start_hori_int2_reg[0]_i_2_n_3\, + O => \det_v0active_start_hori_int2[3]_i_5_n_0\ + ); +\det_v0active_start_hori_int2[3]_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(3), + I1 => \det_v0active_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(3), + O => \det_v0active_start_hori_int2[3]_i_6_n_0\ + ); +\det_v0active_start_hori_int2[3]_i_7\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(2), + I1 => \det_v0active_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(2), + O => \det_v0active_start_hori_int2[3]_i_7_n_0\ + ); +\det_v0active_start_hori_int2[3]_i_8\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(1), + I1 => \det_v0active_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(1), + O => \det_v0active_start_hori_int2[3]_i_8_n_0\ + ); +\det_v0active_start_hori_int2[3]_i_9\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E2" + ) + port map ( + I0 => det_hactive_start_int(0), + I1 => \det_v0active_start_hori_int2_reg[0]_i_2_n_3\, + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(0), + O => \det_v0active_start_hori_int2[3]_i_9_n_0\ + ); +\det_v0active_start_hori_int2[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(7), + I1 => \det_v0active_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(7), + O => \det_v0active_start_hori_int2[7]_i_2_n_0\ + ); +\det_v0active_start_hori_int2[7]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(6), + I1 => \det_v0active_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(6), + O => \det_v0active_start_hori_int2[7]_i_3_n_0\ + ); +\det_v0active_start_hori_int2[7]_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(5), + I1 => \det_v0active_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(5), + O => \det_v0active_start_hori_int2[7]_i_4_n_0\ + ); +\det_v0active_start_hori_int2[7]_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(4), + I1 => \det_v0active_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(4), + O => \det_v0active_start_hori_int2[7]_i_5_n_0\ + ); +\det_v0active_start_hori_int2[7]_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(7), + I1 => \det_v0active_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(7), + O => \det_v0active_start_hori_int2[7]_i_6_n_0\ + ); +\det_v0active_start_hori_int2[7]_i_7\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(6), + I1 => \det_v0active_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(6), + O => \det_v0active_start_hori_int2[7]_i_7_n_0\ + ); +\det_v0active_start_hori_int2[7]_i_8\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(5), + I1 => \det_v0active_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(5), + O => \det_v0active_start_hori_int2[7]_i_8_n_0\ + ); +\det_v0active_start_hori_int2[7]_i_9\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(4), + I1 => \det_v0active_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(4), + O => \det_v0active_start_hori_int2[7]_i_9_n_0\ + ); +\det_v0active_start_hori_int2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => \det_v0active_start_hori_int2[0]_i_1_n_0\, + Q => \time_status_regs[7]\(12), + R => \^reset\ + ); +\det_v0active_start_hori_int2_reg[0]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => \det_v0active_start_hori_int2_reg[0]_i_3_n_0\, + CO(3 downto 1) => \NLW_det_v0active_start_hori_int2_reg[0]_i_2_CO_UNCONNECTED\(3 downto 1), + CO(0) => \det_v0active_start_hori_int2_reg[0]_i_2_n_3\, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => \det_v0active_start_hori_int2[0]_i_4_n_0\, + O(3 downto 0) => \NLW_det_v0active_start_hori_int2_reg[0]_i_2_O_UNCONNECTED\(3 downto 0), + S(3 downto 1) => B"000", + S(0) => \det_v0active_start_hori_int2[0]_i_5_n_0\ + ); +\det_v0active_start_hori_int2_reg[0]_i_3\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \det_v0active_start_hori_int2_reg[0]_i_3_n_0\, + CO(2) => \det_v0active_start_hori_int2_reg[0]_i_3_n_1\, + CO(1) => \det_v0active_start_hori_int2_reg[0]_i_3_n_2\, + CO(0) => \det_v0active_start_hori_int2_reg[0]_i_3_n_3\, + CYINIT => \det_v0fp_start_hori_int2[0]_i_6_n_0\, + DI(3) => \det_v0active_start_hori_int2[0]_i_6_n_0\, + DI(2) => \det_v0active_start_hori_int2[0]_i_7_n_0\, + DI(1) => \det_v0active_start_hori_int2[0]_i_8_n_0\, + DI(0) => \det_v0active_start_hori_int2[0]_i_9_n_0\, + O(3 downto 0) => \NLW_det_v0active_start_hori_int2_reg[0]_i_3_O_UNCONNECTED\(3 downto 0), + S(3) => \det_v0active_start_hori_int2[0]_i_10_n_0\, + S(2) => \det_v0active_start_hori_int2[0]_i_11_n_0\, + S(1) => \det_v0active_start_hori_int2[0]_i_12_n_0\, + S(0) => \det_v0active_start_hori_int2[0]_i_13_n_0\ + ); +\det_v0active_start_hori_int2_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0active_start_hori_int2(10), + Q => \time_status_regs[7]\(22), + R => \^reset\ + ); +\det_v0active_start_hori_int2_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0active_start_hori_int2(11), + Q => \time_status_regs[7]\(23), + R => \^reset\ + ); +\det_v0active_start_hori_int2_reg[11]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \det_v0active_start_hori_int2_reg[7]_i_1_n_0\, + CO(3) => \NLW_det_v0active_start_hori_int2_reg[11]_i_1_CO_UNCONNECTED\(3), + CO(2) => \det_v0active_start_hori_int2_reg[11]_i_1_n_1\, + CO(1) => \det_v0active_start_hori_int2_reg[11]_i_1_n_2\, + CO(0) => \det_v0active_start_hori_int2_reg[11]_i_1_n_3\, + CYINIT => '0', + DI(3) => '0', + DI(2) => \det_v0active_start_hori_int2[11]_i_2_n_0\, + DI(1) => \det_v0active_start_hori_int2[11]_i_3_n_0\, + DI(0) => \det_v0active_start_hori_int2[11]_i_4_n_0\, + O(3 downto 0) => det_v0active_start_hori_int2(11 downto 8), + S(3) => \det_v0active_start_hori_int2[11]_i_5_n_0\, + S(2) => \det_v0active_start_hori_int2[11]_i_6_n_0\, + S(1) => \det_v0active_start_hori_int2[11]_i_7_n_0\, + S(0) => \det_v0active_start_hori_int2[11]_i_8_n_0\ + ); +\det_v0active_start_hori_int2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0active_start_hori_int2(1), + Q => \time_status_regs[7]\(13), + R => \^reset\ + ); +\det_v0active_start_hori_int2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0active_start_hori_int2(2), + Q => \time_status_regs[7]\(14), + R => \^reset\ + ); +\det_v0active_start_hori_int2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0active_start_hori_int2(3), + Q => \time_status_regs[7]\(15), + R => \^reset\ + ); +\det_v0active_start_hori_int2_reg[3]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \det_v0active_start_hori_int2_reg[3]_i_1_n_0\, + CO(2) => \det_v0active_start_hori_int2_reg[3]_i_1_n_1\, + CO(1) => \det_v0active_start_hori_int2_reg[3]_i_1_n_2\, + CO(0) => \det_v0active_start_hori_int2_reg[3]_i_1_n_3\, + CYINIT => '0', + DI(3) => \det_v0active_start_hori_int2[3]_i_2_n_0\, + DI(2) => \det_v0active_start_hori_int2[3]_i_3_n_0\, + DI(1) => \det_v0active_start_hori_int2[3]_i_4_n_0\, + DI(0) => \det_v0active_start_hori_int2[3]_i_5_n_0\, + O(3 downto 1) => det_v0active_start_hori_int2(3 downto 1), + O(0) => \NLW_det_v0active_start_hori_int2_reg[3]_i_1_O_UNCONNECTED\(0), + S(3) => \det_v0active_start_hori_int2[3]_i_6_n_0\, + S(2) => \det_v0active_start_hori_int2[3]_i_7_n_0\, + S(1) => \det_v0active_start_hori_int2[3]_i_8_n_0\, + S(0) => \det_v0active_start_hori_int2[3]_i_9_n_0\ + ); +\det_v0active_start_hori_int2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0active_start_hori_int2(4), + Q => \time_status_regs[7]\(16), + R => \^reset\ + ); +\det_v0active_start_hori_int2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0active_start_hori_int2(5), + Q => \time_status_regs[7]\(17), + R => \^reset\ + ); +\det_v0active_start_hori_int2_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0active_start_hori_int2(6), + Q => \time_status_regs[7]\(18), + R => \^reset\ + ); +\det_v0active_start_hori_int2_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0active_start_hori_int2(7), + Q => \time_status_regs[7]\(19), + R => \^reset\ + ); +\det_v0active_start_hori_int2_reg[7]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \det_v0active_start_hori_int2_reg[3]_i_1_n_0\, + CO(3) => \det_v0active_start_hori_int2_reg[7]_i_1_n_0\, + CO(2) => \det_v0active_start_hori_int2_reg[7]_i_1_n_1\, + CO(1) => \det_v0active_start_hori_int2_reg[7]_i_1_n_2\, + CO(0) => \det_v0active_start_hori_int2_reg[7]_i_1_n_3\, + CYINIT => '0', + DI(3) => \det_v0active_start_hori_int2[7]_i_2_n_0\, + DI(2) => \det_v0active_start_hori_int2[7]_i_3_n_0\, + DI(1) => \det_v0active_start_hori_int2[7]_i_4_n_0\, + DI(0) => \det_v0active_start_hori_int2[7]_i_5_n_0\, + O(3 downto 0) => det_v0active_start_hori_int2(7 downto 4), + S(3) => \det_v0active_start_hori_int2[7]_i_6_n_0\, + S(2) => \det_v0active_start_hori_int2[7]_i_7_n_0\, + S(1) => \det_v0active_start_hori_int2[7]_i_8_n_0\, + S(0) => \det_v0active_start_hori_int2[7]_i_9_n_0\ + ); +\det_v0active_start_hori_int2_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0active_start_hori_int2(8), + Q => \time_status_regs[7]\(20), + R => \^reset\ + ); +\det_v0active_start_hori_int2_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0active_start_hori_int2(9), + Q => \time_status_regs[7]\(21), + R => \^reset\ + ); +\det_v0active_start_int[10]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000040000040" + ) + port map ( + I0 => active_line_d, + I1 => active_line, + I2 => \^det_ce\, + I3 => \^time_status_regs[3]\(1), + I4 => hsync_in, + I5 => line_end_d_reg_n_0, + O => det_v0active_start_int_6 + ); +\det_v0active_start_int_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0active_start_int_6, + D => \v_count_reg__0\(0), + Q => det_v0active_start_int(0), + R => h_count1 + ); +\det_v0active_start_int_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0active_start_int_6, + D => \v_count_reg__0\(10), + Q => det_v0active_start_int(10), + R => h_count1 + ); +\det_v0active_start_int_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0active_start_int_6, + D => \v_count_reg__0\(1), + Q => det_v0active_start_int(1), + R => h_count1 + ); +\det_v0active_start_int_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0active_start_int_6, + D => \v_count_reg__0\(2), + Q => det_v0active_start_int(2), + R => h_count1 + ); +\det_v0active_start_int_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0active_start_int_6, + D => \v_count_reg__0\(3), + Q => det_v0active_start_int(3), + R => h_count1 + ); +\det_v0active_start_int_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0active_start_int_6, + D => \v_count_reg__0\(4), + Q => det_v0active_start_int(4), + R => h_count1 + ); +\det_v0active_start_int_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0active_start_int_6, + D => \v_count_reg__0\(5), + Q => det_v0active_start_int(5), + R => h_count1 + ); +\det_v0active_start_int_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0active_start_int_6, + D => \v_count_reg__0\(6), + Q => det_v0active_start_int(6), + R => h_count1 + ); +\det_v0active_start_int_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0active_start_int_6, + D => \v_count_reg__0\(7), + Q => det_v0active_start_int(7), + R => h_count1 + ); +\det_v0active_start_int_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0active_start_int_6, + D => \v_count_reg__0\(8), + Q => det_v0active_start_int(8), + R => h_count1 + ); +\det_v0active_start_int_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0active_start_int_6, + D => \v_count_reg__0\(9), + Q => det_v0active_start_int(9), + R => h_count1 + ); +\det_v0bp_start_hori_int2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0bp_start_hori_int2(0), + Q => \time_status_regs[9]\(12), + R => \^reset\ + ); +\det_v0bp_start_hori_int2_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0bp_start_hori_int2(10), + Q => \time_status_regs[9]\(22), + R => \^reset\ + ); +\det_v0bp_start_hori_int2_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0bp_start_hori_int2(11), + Q => \time_status_regs[9]\(23), + R => \^reset\ + ); +\det_v0bp_start_hori_int2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0bp_start_hori_int2(1), + Q => \time_status_regs[9]\(13), + R => \^reset\ + ); +\det_v0bp_start_hori_int2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0bp_start_hori_int2(2), + Q => \time_status_regs[9]\(14), + R => \^reset\ + ); +\det_v0bp_start_hori_int2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0bp_start_hori_int2(3), + Q => \time_status_regs[9]\(15), + R => \^reset\ + ); +\det_v0bp_start_hori_int2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0bp_start_hori_int2(4), + Q => \time_status_regs[9]\(16), + R => \^reset\ + ); +\det_v0bp_start_hori_int2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0bp_start_hori_int2(5), + Q => \time_status_regs[9]\(17), + R => \^reset\ + ); +\det_v0bp_start_hori_int2_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0bp_start_hori_int2(6), + Q => \time_status_regs[9]\(18), + R => \^reset\ + ); +\det_v0bp_start_hori_int2_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0bp_start_hori_int2(7), + Q => \time_status_regs[9]\(19), + R => \^reset\ + ); +\det_v0bp_start_hori_int2_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0bp_start_hori_int2(8), + Q => \time_status_regs[9]\(20), + R => \^reset\ + ); +\det_v0bp_start_hori_int2_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0bp_start_hori_int2(9), + Q => \time_status_regs[9]\(21), + R => \^reset\ + ); +\det_v0bp_start_int2[10]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_v0bp_start_int(10), + O => \det_v0bp_start_int2[10]_i_2_n_0\ + ); +\det_v0bp_start_int2[10]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_v0bp_start_int(9), + O => \det_v0bp_start_int2[10]_i_3_n_0\ + ); +\det_v0bp_start_int2[10]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_v0bp_start_int(8), + O => \det_v0bp_start_int2[10]_i_4_n_0\ + ); +\det_v0bp_start_int2[3]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_v0bp_start_int(3), + O => \det_v0bp_start_int2[3]_i_2_n_0\ + ); +\det_v0bp_start_int2[3]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_v0bp_start_int(2), + O => \det_v0bp_start_int2[3]_i_3_n_0\ + ); +\det_v0bp_start_int2[3]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_v0bp_start_int(1), + O => \det_v0bp_start_int2[3]_i_4_n_0\ + ); +\det_v0bp_start_int2[3]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => det_v0bp_start_int(0), + I1 => \ltOp_inferred__0/i__carry__0_n_2\, + O => \det_v0bp_start_int2[3]_i_5_n_0\ + ); +\det_v0bp_start_int2[7]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_v0bp_start_int(7), + O => \det_v0bp_start_int2[7]_i_2_n_0\ + ); +\det_v0bp_start_int2[7]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_v0bp_start_int(6), + O => \det_v0bp_start_int2[7]_i_3_n_0\ + ); +\det_v0bp_start_int2[7]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_v0bp_start_int(5), + O => \det_v0bp_start_int2[7]_i_4_n_0\ + ); +\det_v0bp_start_int2[7]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_v0bp_start_int(4), + O => \det_v0bp_start_int2[7]_i_5_n_0\ + ); +\det_v0bp_start_int2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0bp_start_int2(0), + Q => \time_status_regs[8]\(11), + R => \^reset\ + ); +\det_v0bp_start_int2_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0bp_start_int2(10), + Q => \time_status_regs[8]\(21), + R => \^reset\ + ); +\det_v0bp_start_int2_reg[10]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \det_v0bp_start_int2_reg[7]_i_1_n_0\, + CO(3 downto 2) => \NLW_det_v0bp_start_int2_reg[10]_i_1_CO_UNCONNECTED\(3 downto 2), + CO(1) => \det_v0bp_start_int2_reg[10]_i_1_n_2\, + CO(0) => \det_v0bp_start_int2_reg[10]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1 downto 0) => det_v0bp_start_int(9 downto 8), + O(3) => \NLW_det_v0bp_start_int2_reg[10]_i_1_O_UNCONNECTED\(3), + O(2 downto 0) => det_v0bp_start_int2(10 downto 8), + S(3) => '0', + S(2) => \det_v0bp_start_int2[10]_i_2_n_0\, + S(1) => \det_v0bp_start_int2[10]_i_3_n_0\, + S(0) => \det_v0bp_start_int2[10]_i_4_n_0\ + ); +\det_v0bp_start_int2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0bp_start_int2(1), + Q => \time_status_regs[8]\(12), + R => \^reset\ + ); +\det_v0bp_start_int2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0bp_start_int2(2), + Q => \time_status_regs[8]\(13), + R => \^reset\ + ); +\det_v0bp_start_int2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0bp_start_int2(3), + Q => \time_status_regs[8]\(14), + R => \^reset\ + ); +\det_v0bp_start_int2_reg[3]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \det_v0bp_start_int2_reg[3]_i_1_n_0\, + CO(2) => \det_v0bp_start_int2_reg[3]_i_1_n_1\, + CO(1) => \det_v0bp_start_int2_reg[3]_i_1_n_2\, + CO(0) => \det_v0bp_start_int2_reg[3]_i_1_n_3\, + CYINIT => '1', + DI(3 downto 0) => det_v0bp_start_int(3 downto 0), + O(3 downto 0) => det_v0bp_start_int2(3 downto 0), + S(3) => \det_v0bp_start_int2[3]_i_2_n_0\, + S(2) => \det_v0bp_start_int2[3]_i_3_n_0\, + S(1) => \det_v0bp_start_int2[3]_i_4_n_0\, + S(0) => \det_v0bp_start_int2[3]_i_5_n_0\ + ); +\det_v0bp_start_int2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0bp_start_int2(4), + Q => \time_status_regs[8]\(15), + R => \^reset\ + ); +\det_v0bp_start_int2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0bp_start_int2(5), + Q => \time_status_regs[8]\(16), + R => \^reset\ + ); +\det_v0bp_start_int2_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0bp_start_int2(6), + Q => \time_status_regs[8]\(17), + R => \^reset\ + ); +\det_v0bp_start_int2_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0bp_start_int2(7), + Q => \time_status_regs[8]\(18), + R => \^reset\ + ); +\det_v0bp_start_int2_reg[7]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \det_v0bp_start_int2_reg[3]_i_1_n_0\, + CO(3) => \det_v0bp_start_int2_reg[7]_i_1_n_0\, + CO(2) => \det_v0bp_start_int2_reg[7]_i_1_n_1\, + CO(1) => \det_v0bp_start_int2_reg[7]_i_1_n_2\, + CO(0) => \det_v0bp_start_int2_reg[7]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => det_v0bp_start_int(7 downto 4), + O(3 downto 0) => det_v0bp_start_int2(7 downto 4), + S(3) => \det_v0bp_start_int2[7]_i_2_n_0\, + S(2) => \det_v0bp_start_int2[7]_i_3_n_0\, + S(1) => \det_v0bp_start_int2[7]_i_4_n_0\, + S(0) => \det_v0bp_start_int2[7]_i_5_n_0\ + ); +\det_v0bp_start_int2_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0bp_start_int2(8), + Q => \time_status_regs[8]\(19), + R => \^reset\ + ); +\det_v0bp_start_int2_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0bp_start_int2(9), + Q => \time_status_regs[8]\(20), + R => \^reset\ + ); +\det_v0fp_start_hori_int2[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E2" + ) + port map ( + I0 => det_hactive_start_int(0), + I1 => \det_v0fp_start_hori_int2_reg[0]_i_2_n_3\, + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(0), + O => \det_v0fp_start_hori_int2[0]_i_1_n_0\ + ); +\det_v0fp_start_hori_int2[0]_i_10\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => det_hactive_start_int(2), + I1 => det_hactive_start_int(3), + O => \det_v0fp_start_hori_int2[0]_i_10_n_0\ + ); +\det_v0fp_start_hori_int2[0]_i_11\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_hactive_start_int(9), + I1 => det_hactive_start_int(8), + O => \det_v0fp_start_hori_int2[0]_i_11_n_0\ + ); +\det_v0fp_start_hori_int2[0]_i_12\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_hactive_start_int(7), + I1 => det_hactive_start_int(6), + O => \det_v0fp_start_hori_int2[0]_i_12_n_0\ + ); +\det_v0fp_start_hori_int2[0]_i_13\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_hactive_start_int(5), + I1 => det_hactive_start_int(4), + O => \det_v0fp_start_hori_int2[0]_i_13_n_0\ + ); +\det_v0fp_start_hori_int2[0]_i_14\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_hactive_start_int(3), + I1 => det_hactive_start_int(2), + O => \det_v0fp_start_hori_int2[0]_i_14_n_0\ + ); +\det_v0fp_start_hori_int2[0]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => det_hactive_start_int(10), + I1 => det_hactive_start_int(11), + O => \det_v0fp_start_hori_int2[0]_i_4_n_0\ + ); +\det_v0fp_start_hori_int2[0]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_hactive_start_int(11), + I1 => det_hactive_start_int(10), + O => \det_v0fp_start_hori_int2[0]_i_5_n_0\ + ); +\det_v0fp_start_hori_int2[0]_i_6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => det_hactive_start_int(1), + I1 => det_hactive_start_int(0), + O => \det_v0fp_start_hori_int2[0]_i_6_n_0\ + ); +\det_v0fp_start_hori_int2[0]_i_7\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => det_hactive_start_int(8), + I1 => det_hactive_start_int(9), + O => \det_v0fp_start_hori_int2[0]_i_7_n_0\ + ); +\det_v0fp_start_hori_int2[0]_i_8\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => det_hactive_start_int(6), + I1 => det_hactive_start_int(7), + O => \det_v0fp_start_hori_int2[0]_i_8_n_0\ + ); +\det_v0fp_start_hori_int2[0]_i_9\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => det_hactive_start_int(4), + I1 => det_hactive_start_int(5), + O => \det_v0fp_start_hori_int2[0]_i_9_n_0\ + ); +\det_v0fp_start_hori_int2[11]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(10), + I1 => \det_v0fp_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(10), + O => \det_v0fp_start_hori_int2[11]_i_2_n_0\ + ); +\det_v0fp_start_hori_int2[11]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(9), + I1 => \det_v0fp_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(9), + O => \det_v0fp_start_hori_int2[11]_i_3_n_0\ + ); +\det_v0fp_start_hori_int2[11]_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(8), + I1 => \det_v0fp_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(8), + O => \det_v0fp_start_hori_int2[11]_i_4_n_0\ + ); +\det_v0fp_start_hori_int2[11]_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(11), + I1 => \det_v0fp_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(11), + O => \det_v0fp_start_hori_int2[11]_i_5_n_0\ + ); +\det_v0fp_start_hori_int2[11]_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(10), + I1 => \det_v0fp_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(10), + O => \det_v0fp_start_hori_int2[11]_i_6_n_0\ + ); +\det_v0fp_start_hori_int2[11]_i_7\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(9), + I1 => \det_v0fp_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(9), + O => \det_v0fp_start_hori_int2[11]_i_7_n_0\ + ); +\det_v0fp_start_hori_int2[11]_i_8\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(8), + I1 => \det_v0fp_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(8), + O => \det_v0fp_start_hori_int2[11]_i_8_n_0\ + ); +\det_v0fp_start_hori_int2[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(3), + I1 => \det_v0fp_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(3), + O => \det_v0fp_start_hori_int2[3]_i_2_n_0\ + ); +\det_v0fp_start_hori_int2[3]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(2), + I1 => \det_v0fp_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(2), + O => \det_v0fp_start_hori_int2[3]_i_3_n_0\ + ); +\det_v0fp_start_hori_int2[3]_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(1), + I1 => \det_v0fp_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(1), + O => \det_v0fp_start_hori_int2[3]_i_4_n_0\ + ); +\det_v0fp_start_hori_int2[3]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \det_v0fp_start_hori_int2_reg[0]_i_2_n_3\, + O => \det_v0fp_start_hori_int2[3]_i_5_n_0\ + ); +\det_v0fp_start_hori_int2[3]_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(3), + I1 => \det_v0fp_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(3), + O => \det_v0fp_start_hori_int2[3]_i_6_n_0\ + ); +\det_v0fp_start_hori_int2[3]_i_7\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(2), + I1 => \det_v0fp_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(2), + O => \det_v0fp_start_hori_int2[3]_i_7_n_0\ + ); +\det_v0fp_start_hori_int2[3]_i_8\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(1), + I1 => \det_v0fp_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(1), + O => \det_v0fp_start_hori_int2[3]_i_8_n_0\ + ); +\det_v0fp_start_hori_int2[3]_i_9\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E2" + ) + port map ( + I0 => det_hactive_start_int(0), + I1 => \det_v0fp_start_hori_int2_reg[0]_i_2_n_3\, + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(0), + O => \det_v0fp_start_hori_int2[3]_i_9_n_0\ + ); +\det_v0fp_start_hori_int2[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(7), + I1 => \det_v0fp_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(7), + O => \det_v0fp_start_hori_int2[7]_i_2_n_0\ + ); +\det_v0fp_start_hori_int2[7]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(6), + I1 => \det_v0fp_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(6), + O => \det_v0fp_start_hori_int2[7]_i_3_n_0\ + ); +\det_v0fp_start_hori_int2[7]_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(5), + I1 => \det_v0fp_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(5), + O => \det_v0fp_start_hori_int2[7]_i_4_n_0\ + ); +\det_v0fp_start_hori_int2[7]_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(4), + I1 => \det_v0fp_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(4), + O => \det_v0fp_start_hori_int2[7]_i_5_n_0\ + ); +\det_v0fp_start_hori_int2[7]_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(7), + I1 => \det_v0fp_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(7), + O => \det_v0fp_start_hori_int2[7]_i_6_n_0\ + ); +\det_v0fp_start_hori_int2[7]_i_7\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(6), + I1 => \det_v0fp_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(6), + O => \det_v0fp_start_hori_int2[7]_i_7_n_0\ + ); +\det_v0fp_start_hori_int2[7]_i_8\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(5), + I1 => \det_v0fp_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(5), + O => \det_v0fp_start_hori_int2[7]_i_8_n_0\ + ); +\det_v0fp_start_hori_int2[7]_i_9\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8B" + ) + port map ( + I0 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(4), + I1 => \det_v0fp_start_hori_int2_reg[0]_i_2_n_3\, + I2 => det_hactive_start_int(4), + O => \det_v0fp_start_hori_int2[7]_i_9_n_0\ + ); +\det_v0fp_start_hori_int2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => \det_v0fp_start_hori_int2[0]_i_1_n_0\, + Q => \time_status_regs[7]\(0), + R => \^reset\ + ); +\det_v0fp_start_hori_int2_reg[0]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => \det_v0fp_start_hori_int2_reg[0]_i_3_n_0\, + CO(3 downto 1) => \NLW_det_v0fp_start_hori_int2_reg[0]_i_2_CO_UNCONNECTED\(3 downto 1), + CO(0) => \det_v0fp_start_hori_int2_reg[0]_i_2_n_3\, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => \det_v0fp_start_hori_int2[0]_i_4_n_0\, + O(3 downto 0) => \NLW_det_v0fp_start_hori_int2_reg[0]_i_2_O_UNCONNECTED\(3 downto 0), + S(3 downto 1) => B"000", + S(0) => \det_v0fp_start_hori_int2[0]_i_5_n_0\ + ); +\det_v0fp_start_hori_int2_reg[0]_i_3\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \det_v0fp_start_hori_int2_reg[0]_i_3_n_0\, + CO(2) => \det_v0fp_start_hori_int2_reg[0]_i_3_n_1\, + CO(1) => \det_v0fp_start_hori_int2_reg[0]_i_3_n_2\, + CO(0) => \det_v0fp_start_hori_int2_reg[0]_i_3_n_3\, + CYINIT => \det_v0fp_start_hori_int2[0]_i_6_n_0\, + DI(3) => \det_v0fp_start_hori_int2[0]_i_7_n_0\, + DI(2) => \det_v0fp_start_hori_int2[0]_i_8_n_0\, + DI(1) => \det_v0fp_start_hori_int2[0]_i_9_n_0\, + DI(0) => \det_v0fp_start_hori_int2[0]_i_10_n_0\, + O(3 downto 0) => \NLW_det_v0fp_start_hori_int2_reg[0]_i_3_O_UNCONNECTED\(3 downto 0), + S(3) => \det_v0fp_start_hori_int2[0]_i_11_n_0\, + S(2) => \det_v0fp_start_hori_int2[0]_i_12_n_0\, + S(1) => \det_v0fp_start_hori_int2[0]_i_13_n_0\, + S(0) => \det_v0fp_start_hori_int2[0]_i_14_n_0\ + ); +\det_v0fp_start_hori_int2_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0fp_start_hori_int2(10), + Q => \time_status_regs[7]\(10), + R => \^reset\ + ); +\det_v0fp_start_hori_int2_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0fp_start_hori_int2(11), + Q => \time_status_regs[7]\(11), + R => \^reset\ + ); +\det_v0fp_start_hori_int2_reg[11]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \det_v0fp_start_hori_int2_reg[7]_i_1_n_0\, + CO(3) => \NLW_det_v0fp_start_hori_int2_reg[11]_i_1_CO_UNCONNECTED\(3), + CO(2) => \det_v0fp_start_hori_int2_reg[11]_i_1_n_1\, + CO(1) => \det_v0fp_start_hori_int2_reg[11]_i_1_n_2\, + CO(0) => \det_v0fp_start_hori_int2_reg[11]_i_1_n_3\, + CYINIT => '0', + DI(3) => '0', + DI(2) => \det_v0fp_start_hori_int2[11]_i_2_n_0\, + DI(1) => \det_v0fp_start_hori_int2[11]_i_3_n_0\, + DI(0) => \det_v0fp_start_hori_int2[11]_i_4_n_0\, + O(3 downto 0) => det_v0fp_start_hori_int2(11 downto 8), + S(3) => \det_v0fp_start_hori_int2[11]_i_5_n_0\, + S(2) => \det_v0fp_start_hori_int2[11]_i_6_n_0\, + S(1) => \det_v0fp_start_hori_int2[11]_i_7_n_0\, + S(0) => \det_v0fp_start_hori_int2[11]_i_8_n_0\ + ); +\det_v0fp_start_hori_int2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0fp_start_hori_int2(1), + Q => \time_status_regs[7]\(1), + R => \^reset\ + ); +\det_v0fp_start_hori_int2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0fp_start_hori_int2(2), + Q => \time_status_regs[7]\(2), + R => \^reset\ + ); +\det_v0fp_start_hori_int2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0fp_start_hori_int2(3), + Q => \time_status_regs[7]\(3), + R => \^reset\ + ); +\det_v0fp_start_hori_int2_reg[3]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \det_v0fp_start_hori_int2_reg[3]_i_1_n_0\, + CO(2) => \det_v0fp_start_hori_int2_reg[3]_i_1_n_1\, + CO(1) => \det_v0fp_start_hori_int2_reg[3]_i_1_n_2\, + CO(0) => \det_v0fp_start_hori_int2_reg[3]_i_1_n_3\, + CYINIT => '0', + DI(3) => \det_v0fp_start_hori_int2[3]_i_2_n_0\, + DI(2) => \det_v0fp_start_hori_int2[3]_i_3_n_0\, + DI(1) => \det_v0fp_start_hori_int2[3]_i_4_n_0\, + DI(0) => \det_v0fp_start_hori_int2[3]_i_5_n_0\, + O(3 downto 1) => det_v0fp_start_hori_int2(3 downto 1), + O(0) => \NLW_det_v0fp_start_hori_int2_reg[3]_i_1_O_UNCONNECTED\(0), + S(3) => \det_v0fp_start_hori_int2[3]_i_6_n_0\, + S(2) => \det_v0fp_start_hori_int2[3]_i_7_n_0\, + S(1) => \det_v0fp_start_hori_int2[3]_i_8_n_0\, + S(0) => \det_v0fp_start_hori_int2[3]_i_9_n_0\ + ); +\det_v0fp_start_hori_int2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0fp_start_hori_int2(4), + Q => \time_status_regs[7]\(4), + R => \^reset\ + ); +\det_v0fp_start_hori_int2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0fp_start_hori_int2(5), + Q => \time_status_regs[7]\(5), + R => \^reset\ + ); +\det_v0fp_start_hori_int2_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0fp_start_hori_int2(6), + Q => \time_status_regs[7]\(6), + R => \^reset\ + ); +\det_v0fp_start_hori_int2_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0fp_start_hori_int2(7), + Q => \time_status_regs[7]\(7), + R => \^reset\ + ); +\det_v0fp_start_hori_int2_reg[7]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \det_v0fp_start_hori_int2_reg[3]_i_1_n_0\, + CO(3) => \det_v0fp_start_hori_int2_reg[7]_i_1_n_0\, + CO(2) => \det_v0fp_start_hori_int2_reg[7]_i_1_n_1\, + CO(1) => \det_v0fp_start_hori_int2_reg[7]_i_1_n_2\, + CO(0) => \det_v0fp_start_hori_int2_reg[7]_i_1_n_3\, + CYINIT => '0', + DI(3) => \det_v0fp_start_hori_int2[7]_i_2_n_0\, + DI(2) => \det_v0fp_start_hori_int2[7]_i_3_n_0\, + DI(1) => \det_v0fp_start_hori_int2[7]_i_4_n_0\, + DI(0) => \det_v0fp_start_hori_int2[7]_i_5_n_0\, + O(3 downto 0) => det_v0fp_start_hori_int2(7 downto 4), + S(3) => \det_v0fp_start_hori_int2[7]_i_6_n_0\, + S(2) => \det_v0fp_start_hori_int2[7]_i_7_n_0\, + S(1) => \det_v0fp_start_hori_int2[7]_i_8_n_0\, + S(0) => \det_v0fp_start_hori_int2[7]_i_9_n_0\ + ); +\det_v0fp_start_hori_int2_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0fp_start_hori_int2(8), + Q => \time_status_regs[7]\(8), + R => \^reset\ + ); +\det_v0fp_start_hori_int2_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0fp_start_hori_int2(9), + Q => \time_status_regs[7]\(9), + R => \^reset\ + ); +\det_v0fp_start_int[10]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0008000000000008" + ) + port map ( + I0 => \^det_ce\, + I1 => active_line_d, + I2 => active_line, + I3 => line_end_d_reg_n_0, + I4 => hsync_in, + I5 => \^time_status_regs[3]\(1), + O => det_v0fp_start_int + ); +\det_v0fp_start_int_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0fp_start_int, + D => \v_count_reg__0\(0), + Q => \^time_status_regs_int_reg[0]\(0), + R => h_count1 + ); +\det_v0fp_start_int_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0fp_start_int, + D => \v_count_reg__0\(10), + Q => \^time_status_regs_int_reg[0]\(10), + R => h_count1 + ); +\det_v0fp_start_int_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0fp_start_int, + D => \v_count_reg__0\(1), + Q => \^time_status_regs_int_reg[0]\(1), + R => h_count1 + ); +\det_v0fp_start_int_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0fp_start_int, + D => \v_count_reg__0\(2), + Q => \^time_status_regs_int_reg[0]\(2), + R => h_count1 + ); +\det_v0fp_start_int_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0fp_start_int, + D => \v_count_reg__0\(3), + Q => \^time_status_regs_int_reg[0]\(3), + R => h_count1 + ); +\det_v0fp_start_int_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0fp_start_int, + D => \v_count_reg__0\(4), + Q => \^time_status_regs_int_reg[0]\(4), + R => h_count1 + ); +\det_v0fp_start_int_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0fp_start_int, + D => \v_count_reg__0\(5), + Q => \^time_status_regs_int_reg[0]\(5), + R => h_count1 + ); +\det_v0fp_start_int_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0fp_start_int, + D => \v_count_reg__0\(6), + Q => \^time_status_regs_int_reg[0]\(6), + R => h_count1 + ); +\det_v0fp_start_int_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0fp_start_int, + D => \v_count_reg__0\(7), + Q => \^time_status_regs_int_reg[0]\(7), + R => h_count1 + ); +\det_v0fp_start_int_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0fp_start_int, + D => \v_count_reg__0\(8), + Q => \^time_status_regs_int_reg[0]\(8), + R => h_count1 + ); +\det_v0fp_start_int_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => det_v0fp_start_int, + D => \v_count_reg__0\(9), + Q => \^time_status_regs_int_reg[0]\(9), + R => h_count1 + ); +\det_v0sync_start_hori_int2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0sync_start_hori_int2(0), + Q => \time_status_regs[9]\(0), + R => \^reset\ + ); +\det_v0sync_start_hori_int2_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0sync_start_hori_int2(10), + Q => \time_status_regs[9]\(10), + R => \^reset\ + ); +\det_v0sync_start_hori_int2_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0sync_start_hori_int2(11), + Q => \time_status_regs[9]\(11), + R => \^reset\ + ); +\det_v0sync_start_hori_int2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0sync_start_hori_int2(1), + Q => \time_status_regs[9]\(1), + R => \^reset\ + ); +\det_v0sync_start_hori_int2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0sync_start_hori_int2(2), + Q => \time_status_regs[9]\(2), + R => \^reset\ + ); +\det_v0sync_start_hori_int2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0sync_start_hori_int2(3), + Q => \time_status_regs[9]\(3), + R => \^reset\ + ); +\det_v0sync_start_hori_int2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0sync_start_hori_int2(4), + Q => \time_status_regs[9]\(4), + R => \^reset\ + ); +\det_v0sync_start_hori_int2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0sync_start_hori_int2(5), + Q => \time_status_regs[9]\(5), + R => \^reset\ + ); +\det_v0sync_start_hori_int2_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0sync_start_hori_int2(6), + Q => \time_status_regs[9]\(6), + R => \^reset\ + ); +\det_v0sync_start_hori_int2_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0sync_start_hori_int2(7), + Q => \time_status_regs[9]\(7), + R => \^reset\ + ); +\det_v0sync_start_hori_int2_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0sync_start_hori_int2(8), + Q => \time_status_regs[9]\(8), + R => \^reset\ + ); +\det_v0sync_start_hori_int2_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0sync_start_hori_int2(9), + Q => \time_status_regs[9]\(9), + R => \^reset\ + ); +\det_v0sync_start_int2[10]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_v0sync_start_int(10), + O => \det_v0sync_start_int2[10]_i_2_n_0\ + ); +\det_v0sync_start_int2[10]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_v0sync_start_int(9), + O => \det_v0sync_start_int2[10]_i_3_n_0\ + ); +\det_v0sync_start_int2[10]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_v0sync_start_int(8), + O => \det_v0sync_start_int2[10]_i_4_n_0\ + ); +\det_v0sync_start_int2[3]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_v0sync_start_int(3), + O => \det_v0sync_start_int2[3]_i_2_n_0\ + ); +\det_v0sync_start_int2[3]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_v0sync_start_int(2), + O => \det_v0sync_start_int2[3]_i_3_n_0\ + ); +\det_v0sync_start_int2[3]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_v0sync_start_int(1), + O => \det_v0sync_start_int2[3]_i_4_n_0\ + ); +\det_v0sync_start_int2[3]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => det_v0sync_start_int(0), + I1 => ltOp, + O => \det_v0sync_start_int2[3]_i_5_n_0\ + ); +\det_v0sync_start_int2[7]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_v0sync_start_int(7), + O => \det_v0sync_start_int2[7]_i_2_n_0\ + ); +\det_v0sync_start_int2[7]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_v0sync_start_int(6), + O => \det_v0sync_start_int2[7]_i_3_n_0\ + ); +\det_v0sync_start_int2[7]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_v0sync_start_int(5), + O => \det_v0sync_start_int2[7]_i_4_n_0\ + ); +\det_v0sync_start_int2[7]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_v0sync_start_int(4), + O => \det_v0sync_start_int2[7]_i_5_n_0\ + ); +\det_v0sync_start_int2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0sync_start_int2(0), + Q => \time_status_regs[8]\(0), + R => \^reset\ + ); +\det_v0sync_start_int2_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0sync_start_int2(10), + Q => \time_status_regs[8]\(10), + R => \^reset\ + ); +\det_v0sync_start_int2_reg[10]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \det_v0sync_start_int2_reg[7]_i_1_n_0\, + CO(3 downto 2) => \NLW_det_v0sync_start_int2_reg[10]_i_1_CO_UNCONNECTED\(3 downto 2), + CO(1) => \det_v0sync_start_int2_reg[10]_i_1_n_2\, + CO(0) => \det_v0sync_start_int2_reg[10]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1 downto 0) => det_v0sync_start_int(9 downto 8), + O(3) => \NLW_det_v0sync_start_int2_reg[10]_i_1_O_UNCONNECTED\(3), + O(2 downto 0) => det_v0sync_start_int2(10 downto 8), + S(3) => '0', + S(2) => \det_v0sync_start_int2[10]_i_2_n_0\, + S(1) => \det_v0sync_start_int2[10]_i_3_n_0\, + S(0) => \det_v0sync_start_int2[10]_i_4_n_0\ + ); +\det_v0sync_start_int2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0sync_start_int2(1), + Q => \time_status_regs[8]\(1), + R => \^reset\ + ); +\det_v0sync_start_int2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0sync_start_int2(2), + Q => \time_status_regs[8]\(2), + R => \^reset\ + ); +\det_v0sync_start_int2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0sync_start_int2(3), + Q => \time_status_regs[8]\(3), + R => \^reset\ + ); +\det_v0sync_start_int2_reg[3]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \det_v0sync_start_int2_reg[3]_i_1_n_0\, + CO(2) => \det_v0sync_start_int2_reg[3]_i_1_n_1\, + CO(1) => \det_v0sync_start_int2_reg[3]_i_1_n_2\, + CO(0) => \det_v0sync_start_int2_reg[3]_i_1_n_3\, + CYINIT => '1', + DI(3 downto 0) => det_v0sync_start_int(3 downto 0), + O(3 downto 0) => det_v0sync_start_int2(3 downto 0), + S(3) => \det_v0sync_start_int2[3]_i_2_n_0\, + S(2) => \det_v0sync_start_int2[3]_i_3_n_0\, + S(1) => \det_v0sync_start_int2[3]_i_4_n_0\, + S(0) => \det_v0sync_start_int2[3]_i_5_n_0\ + ); +\det_v0sync_start_int2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0sync_start_int2(4), + Q => \time_status_regs[8]\(4), + R => \^reset\ + ); +\det_v0sync_start_int2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0sync_start_int2(5), + Q => \time_status_regs[8]\(5), + R => \^reset\ + ); +\det_v0sync_start_int2_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0sync_start_int2(6), + Q => \time_status_regs[8]\(6), + R => \^reset\ + ); +\det_v0sync_start_int2_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0sync_start_int2(7), + Q => \time_status_regs[8]\(7), + R => \^reset\ + ); +\det_v0sync_start_int2_reg[7]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \det_v0sync_start_int2_reg[3]_i_1_n_0\, + CO(3) => \det_v0sync_start_int2_reg[7]_i_1_n_0\, + CO(2) => \det_v0sync_start_int2_reg[7]_i_1_n_1\, + CO(1) => \det_v0sync_start_int2_reg[7]_i_1_n_2\, + CO(0) => \det_v0sync_start_int2_reg[7]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => det_v0sync_start_int(7 downto 4), + O(3 downto 0) => det_v0sync_start_int2(7 downto 4), + S(3) => \det_v0sync_start_int2[7]_i_2_n_0\, + S(2) => \det_v0sync_start_int2[7]_i_3_n_0\, + S(1) => \det_v0sync_start_int2[7]_i_4_n_0\, + S(0) => \det_v0sync_start_int2[7]_i_5_n_0\ + ); +\det_v0sync_start_int2_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0sync_start_int2(8), + Q => \time_status_regs[8]\(8), + R => \^reset\ + ); +\det_v0sync_start_int2_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => det_v0sync_start_int2(9), + Q => \time_status_regs[8]\(9), + R => \^reset\ + ); +\det_v0total[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => det_v0total_int(0), + O => \det_v0total[0]_i_1_n_0\ + ); +\det_v0total[10]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFFFFFF80000000" + ) + port map ( + I0 => det_v0total_int(8), + I1 => det_v0total_int(6), + I2 => \det_v0total[10]_i_2_n_0\, + I3 => det_v0total_int(7), + I4 => det_v0total_int(9), + I5 => det_v0total_int(10), + O => \det_v0total[10]_i_1_n_0\ + ); +\det_v0total[10]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => det_v0total_int(5), + I1 => det_v0total_int(3), + I2 => det_v0total_int(1), + I3 => det_v0total_int(0), + I4 => det_v0total_int(2), + I5 => det_v0total_int(4), + O => \det_v0total[10]_i_2_n_0\ + ); +\det_v0total[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => det_v0total_int(0), + I1 => det_v0total_int(1), + O => \det_v0total[1]_i_1_n_0\ + ); +\det_v0total[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => det_v0total_int(0), + I1 => det_v0total_int(1), + I2 => det_v0total_int(2), + O => \det_v0total[2]_i_1_n_0\ + ); +\det_v0total[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => det_v0total_int(1), + I1 => det_v0total_int(0), + I2 => det_v0total_int(2), + I3 => det_v0total_int(3), + O => \det_v0total[3]_i_1_n_0\ + ); +\det_v0total[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => det_v0total_int(2), + I1 => det_v0total_int(0), + I2 => det_v0total_int(1), + I3 => det_v0total_int(3), + I4 => det_v0total_int(4), + O => \det_v0total[4]_i_1_n_0\ + ); +\det_v0total[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFFFFFF80000000" + ) + port map ( + I0 => det_v0total_int(3), + I1 => det_v0total_int(1), + I2 => det_v0total_int(0), + I3 => det_v0total_int(2), + I4 => det_v0total_int(4), + I5 => det_v0total_int(5), + O => \det_v0total[5]_i_1_n_0\ + ); +\det_v0total[6]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \det_v0total[10]_i_2_n_0\, + I1 => det_v0total_int(6), + O => \det_v0total[6]_i_1_n_0\ + ); +\det_v0total[7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \det_v0total[10]_i_2_n_0\, + I1 => det_v0total_int(6), + I2 => det_v0total_int(7), + O => \det_v0total[7]_i_1_n_0\ + ); +\det_v0total[8]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => det_v0total_int(6), + I1 => \det_v0total[10]_i_2_n_0\, + I2 => det_v0total_int(7), + I3 => det_v0total_int(8), + O => \det_v0total[8]_i_1_n_0\ + ); +\det_v0total[9]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => det_v0total_int(7), + I1 => \det_v0total[10]_i_2_n_0\, + I2 => det_v0total_int(6), + I3 => det_v0total_int(8), + I4 => det_v0total_int(9), + O => \det_v0total[9]_i_1_n_0\ + ); +\det_v0total_int[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(0), + I1 => gtOp_0, + I2 => v_count_last(0), + O => \det_v0total_int[0]_i_1_n_0\ + ); +\det_v0total_int[10]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00008200" + ) + port map ( + I0 => \^det_ce\, + I1 => active_video_in, + I2 => \^time_status_regs[3]\(2), + I3 => top_of_frame_reg_n_0, + I4 => frame_end_d, + O => det_v0total_int_5 + ); +\det_v0total_int[10]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(10), + I1 => gtOp_0, + I2 => v_count_last(10), + O => \det_v0total_int[10]_i_2_n_0\ + ); +\det_v0total_int[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(1), + I1 => gtOp_0, + I2 => v_count_last(1), + O => \det_v0total_int[1]_i_1_n_0\ + ); +\det_v0total_int[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(2), + I1 => gtOp_0, + I2 => v_count_last(2), + O => \det_v0total_int[2]_i_1_n_0\ + ); +\det_v0total_int[3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(3), + I1 => gtOp_0, + I2 => v_count_last(3), + O => \det_v0total_int[3]_i_1_n_0\ + ); +\det_v0total_int[4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(4), + I1 => gtOp_0, + I2 => v_count_last(4), + O => \det_v0total_int[4]_i_1_n_0\ + ); +\det_v0total_int[5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(5), + I1 => gtOp_0, + I2 => v_count_last(5), + O => \det_v0total_int[5]_i_1_n_0\ + ); +\det_v0total_int[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(6), + I1 => gtOp_0, + I2 => v_count_last(6), + O => \det_v0total_int[6]_i_1_n_0\ + ); +\det_v0total_int[7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(7), + I1 => gtOp_0, + I2 => v_count_last(7), + O => \det_v0total_int[7]_i_1_n_0\ + ); +\det_v0total_int[8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(8), + I1 => gtOp_0, + I2 => v_count_last(8), + O => \det_v0total_int[8]_i_1_n_0\ + ); +\det_v0total_int[9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \v_count_reg__0\(9), + I1 => gtOp_0, + I2 => v_count_last(9), + O => \det_v0total_int[9]_i_1_n_0\ + ); +\det_v0total_int_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => det_v0total_int_5, + D => \det_v0total_int[0]_i_1_n_0\, + Q => det_v0total_int(0), + R => h_count1 + ); +\det_v0total_int_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => det_v0total_int_5, + D => \det_v0total_int[10]_i_2_n_0\, + Q => det_v0total_int(10), + R => h_count1 + ); +\det_v0total_int_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => det_v0total_int_5, + D => \det_v0total_int[1]_i_1_n_0\, + Q => det_v0total_int(1), + R => h_count1 + ); +\det_v0total_int_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => det_v0total_int_5, + D => \det_v0total_int[2]_i_1_n_0\, + Q => det_v0total_int(2), + R => h_count1 + ); +\det_v0total_int_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => det_v0total_int_5, + D => \det_v0total_int[3]_i_1_n_0\, + Q => det_v0total_int(3), + R => h_count1 + ); +\det_v0total_int_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => det_v0total_int_5, + D => \det_v0total_int[4]_i_1_n_0\, + Q => det_v0total_int(4), + R => h_count1 + ); +\det_v0total_int_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => det_v0total_int_5, + D => \det_v0total_int[5]_i_1_n_0\, + Q => det_v0total_int(5), + R => h_count1 + ); +\det_v0total_int_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => det_v0total_int_5, + D => \det_v0total_int[6]_i_1_n_0\, + Q => det_v0total_int(6), + R => h_count1 + ); +\det_v0total_int_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => det_v0total_int_5, + D => \det_v0total_int[7]_i_1_n_0\, + Q => det_v0total_int(7), + R => h_count1 + ); +\det_v0total_int_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => det_v0total_int_5, + D => \det_v0total_int[8]_i_1_n_0\, + Q => det_v0total_int(8), + R => h_count1 + ); +\det_v0total_int_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => det_v0total_int_5, + D => \det_v0total_int[9]_i_1_n_0\, + Q => det_v0total_int(9), + R => h_count1 + ); +\det_v0total_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => \det_v0total[0]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10]\(0), + R => \^reset\ + ); +\det_v0total_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => \det_v0total[10]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10]\(10), + R => \^reset\ + ); +\det_v0total_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => \det_v0total[1]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10]\(1), + R => \^reset\ + ); +\det_v0total_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => \det_v0total[2]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10]\(2), + R => \^reset\ + ); +\det_v0total_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => \det_v0total[3]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10]\(3), + R => \^reset\ + ); +\det_v0total_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => \det_v0total[4]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10]\(4), + R => \^reset\ + ); +\det_v0total_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => \det_v0total[5]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10]\(5), + R => \^reset\ + ); +\det_v0total_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => \det_v0total[6]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10]\(6), + R => \^reset\ + ); +\det_v0total_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => \det_v0total[7]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10]\(7), + R => \^reset\ + ); +\det_v0total_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => \det_v0total[8]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10]\(8), + R => \^reset\ + ); +\det_v0total_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => \^det_ce\, + D => \det_v0total[9]_i_1_n_0\, + Q => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10]\(9), + R => \^reset\ + ); +found_eof_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000EAAAAA" + ) + port map ( + I0 => found_eof_reg_n_0, + I1 => gtOp_0, + I2 => p_0_in16_in, + I3 => \h_count0__0\, + I4 => \^det_ce\, + I5 => h_count1, + O => found_eof_i_1_n_0 + ); +found_eof_reg: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => '1', + D => found_eof_i_1_n_0, + Q => found_eof_reg_n_0, + R => '0' + ); +frame_end_d_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"90" + ) + port map ( + I0 => \^time_status_regs[3]\(2), + I1 => active_video_in, + I2 => top_of_frame_reg_n_0, + O => frame_end + ); +frame_end_d_reg: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => '1', + D => frame_end, + Q => frame_end_d, + R => '0' + ); +gtOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => gtOp_carry_n_0, + CO(2) => gtOp_carry_n_1, + CO(1) => gtOp_carry_n_2, + CO(0) => gtOp_carry_n_3, + CYINIT => '0', + DI(3) => gtOp_carry_i_1_n_0, + DI(2) => gtOp_carry_i_2_n_0, + DI(1) => gtOp_carry_i_3_n_0, + DI(0) => gtOp_carry_i_4_n_0, + O(3 downto 0) => NLW_gtOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => gtOp_carry_i_5_n_0, + S(2) => gtOp_carry_i_6_n_0, + S(1) => gtOp_carry_i_7_n_0, + S(0) => gtOp_carry_i_8_n_0 + ); +\gtOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => gtOp_carry_n_0, + CO(3) => \NLW_gtOp_carry__0_CO_UNCONNECTED\(3), + CO(2) => gtOp, + CO(1) => \gtOp_carry__0_n_2\, + CO(0) => \gtOp_carry__0_n_3\, + CYINIT => '0', + DI(3) => '0', + DI(2) => \DET_HSYNC.hsync_count_reg\(11), + DI(1) => \gtOp_carry__0_i_1_n_0\, + DI(0) => \gtOp_carry__0_i_2_n_0\, + O(3 downto 0) => \NLW_gtOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => '0', + S(2) => \gtOp_carry__0_i_3_n_0\, + S(1) => \gtOp_carry__0_i_4_n_0\, + S(0) => \gtOp_carry__0_i_5_n_0\ + ); +\gtOp_carry__0_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \DET_HSYNC.hsync_count_reg\(9), + I1 => det_htotal_int(10), + I2 => det_htotal_int(11), + I3 => \DET_HSYNC.hsync_count_reg\(10), + O => \gtOp_carry__0_i_1_n_0\ + ); +\gtOp_carry__0_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \DET_HSYNC.hsync_count_reg\(7), + I1 => det_htotal_int(8), + I2 => det_htotal_int(9), + I3 => \DET_HSYNC.hsync_count_reg\(8), + O => \gtOp_carry__0_i_2_n_0\ + ); +\gtOp_carry__0_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \DET_HSYNC.hsync_count_reg\(11), + O => \gtOp_carry__0_i_3_n_0\ + ); +\gtOp_carry__0_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_htotal_int(11), + I1 => \DET_HSYNC.hsync_count_reg\(10), + I2 => det_htotal_int(10), + I3 => \DET_HSYNC.hsync_count_reg\(9), + O => \gtOp_carry__0_i_4_n_0\ + ); +\gtOp_carry__0_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_htotal_int(9), + I1 => \DET_HSYNC.hsync_count_reg\(8), + I2 => det_htotal_int(8), + I3 => \DET_HSYNC.hsync_count_reg\(7), + O => \gtOp_carry__0_i_5_n_0\ + ); +gtOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \DET_HSYNC.hsync_count_reg\(5), + I1 => det_htotal_int(6), + I2 => det_htotal_int(7), + I3 => \DET_HSYNC.hsync_count_reg\(6), + O => gtOp_carry_i_1_n_0 + ); +gtOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \DET_HSYNC.hsync_count_reg\(3), + I1 => det_htotal_int(4), + I2 => det_htotal_int(5), + I3 => \DET_HSYNC.hsync_count_reg\(4), + O => gtOp_carry_i_2_n_0 + ); +gtOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \DET_HSYNC.hsync_count_reg\(1), + I1 => det_htotal_int(2), + I2 => det_htotal_int(3), + I3 => \DET_HSYNC.hsync_count_reg\(2), + O => gtOp_carry_i_3_n_0 + ); +gtOp_carry_i_4: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \DET_HSYNC.hsync_count_reg\(0), + I1 => det_htotal_int(1), + O => gtOp_carry_i_4_n_0 + ); +gtOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_htotal_int(7), + I1 => \DET_HSYNC.hsync_count_reg\(6), + I2 => det_htotal_int(6), + I3 => \DET_HSYNC.hsync_count_reg\(5), + O => gtOp_carry_i_5_n_0 + ); +gtOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_htotal_int(5), + I1 => \DET_HSYNC.hsync_count_reg\(4), + I2 => det_htotal_int(4), + I3 => \DET_HSYNC.hsync_count_reg\(3), + O => gtOp_carry_i_6_n_0 + ); +gtOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_htotal_int(3), + I1 => \DET_HSYNC.hsync_count_reg\(2), + I2 => det_htotal_int(2), + I3 => \DET_HSYNC.hsync_count_reg\(1), + O => gtOp_carry_i_7_n_0 + ); +gtOp_carry_i_8: unisim.vcomponents.LUT3 + generic map( + INIT => X"41" + ) + port map ( + I0 => det_htotal_int(0), + I1 => det_htotal_int(1), + I2 => \DET_HSYNC.hsync_count_reg\(0), + O => gtOp_carry_i_8_n_0 + ); +\gtOp_inferred__0/i__carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \gtOp_inferred__0/i__carry_n_0\, + CO(2) => \gtOp_inferred__0/i__carry_n_1\, + CO(1) => \gtOp_inferred__0/i__carry_n_2\, + CO(0) => \gtOp_inferred__0/i__carry_n_3\, + CYINIT => '0', + DI(3) => \i__carry_i_1_n_0\, + DI(2) => \i__carry_i_2_n_0\, + DI(1) => \i__carry_i_3_n_0\, + DI(0) => \i__carry_i_4_n_0\, + O(3 downto 0) => \NLW_gtOp_inferred__0/i__carry_O_UNCONNECTED\(3 downto 0), + S(3) => \i__carry_i_5__2_n_0\, + S(2) => \i__carry_i_6__2_n_0\, + S(1) => \i__carry_i_7__2_n_0\, + S(0) => \i__carry_i_8__2_n_0\ + ); +\gtOp_inferred__0/i__carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \gtOp_inferred__0/i__carry_n_0\, + CO(3) => \NLW_gtOp_inferred__0/i__carry__0_CO_UNCONNECTED\(3), + CO(2) => gtOp_0, + CO(1) => \gtOp_inferred__0/i__carry__0_n_2\, + CO(0) => \gtOp_inferred__0/i__carry__0_n_3\, + CYINIT => '0', + DI(3) => '0', + DI(2) => L(0), + DI(1) => \i__carry__0_i_1_n_0\, + DI(0) => \i__carry__0_i_2_n_0\, + O(3 downto 0) => \NLW_gtOp_inferred__0/i__carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => '0', + S(2) => \i__carry__0_i_3__2_n_0\, + S(1) => \i__carry__0_i_4__2_n_0\, + S(0) => \i__carry__0_i_5__0_n_0\ + ); +\gtOp_inferred__2/i__carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \gtOp_inferred__2/i__carry_n_0\, + CO(2) => \gtOp_inferred__2/i__carry_n_1\, + CO(1) => \gtOp_inferred__2/i__carry_n_2\, + CO(0) => \gtOp_inferred__2/i__carry_n_3\, + CYINIT => '0', + DI(3) => \i__carry_i_1__1_n_0\, + DI(2) => \i__carry_i_2__1_n_0\, + DI(1) => \i__carry_i_3__1_n_0\, + DI(0) => \i__carry_i_4__1_n_0\, + O(3 downto 0) => \NLW_gtOp_inferred__2/i__carry_O_UNCONNECTED\(3 downto 0), + S(3) => \i__carry_i_5__0_n_0\, + S(2) => \i__carry_i_6__0_n_0\, + S(1) => \i__carry_i_7__0_n_0\, + S(0) => \i__carry_i_8__0_n_0\ + ); +\gtOp_inferred__2/i__carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \gtOp_inferred__2/i__carry_n_0\, + CO(3 downto 2) => \NLW_gtOp_inferred__2/i__carry__0_CO_UNCONNECTED\(3 downto 2), + CO(1) => gtOp29_in, + CO(0) => \gtOp_inferred__2/i__carry__0_n_3\, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1) => \i__carry__0_i_1__1_n_0\, + DI(0) => \i__carry__0_i_2__1_n_0\, + O(3 downto 0) => \NLW_gtOp_inferred__2/i__carry__0_O_UNCONNECTED\(3 downto 0), + S(3 downto 2) => B"00", + S(1) => \i__carry__0_i_3_n_0\, + S(0) => \i__carry__0_i_4__0_n_0\ + ); +\h_count[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAEBAAAA" + ) + port map ( + I0 => h_count1, + I1 => \^time_status_regs[3]\(1), + I2 => hsync_in, + I3 => line_end_d_reg_n_0, + I4 => \^det_ce\, + O => \h_count[0]_i_1_n_0\ + ); +\h_count[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAA2AAAAAAA" + ) + port map ( + I0 => \^det_ce\, + I1 => L(11), + I2 => L(10), + I3 => L(9), + I4 => L(8), + I5 => \h_count[0]_i_4_n_0\, + O => h_count + ); +\h_count[0]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF7FFF" + ) + port map ( + I0 => L(4), + I1 => L(5), + I2 => L(6), + I3 => L(7), + I4 => \h_count[0]_i_9_n_0\, + O => \h_count[0]_i_4_n_0\ + ); +\h_count[0]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => L(8), + O => \h_count[0]_i_5_n_0\ + ); +\h_count[0]_i_6\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => L(9), + O => \h_count[0]_i_6_n_0\ + ); +\h_count[0]_i_7\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => L(10), + O => \h_count[0]_i_7_n_0\ + ); +\h_count[0]_i_8\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => L(11), + O => \h_count[0]_i_8_n_0\ + ); +\h_count[0]_i_9\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => L(3), + I1 => L(2), + I2 => L(0), + I3 => L(1), + O => \h_count[0]_i_9_n_0\ + ); +\h_count[4]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => L(4), + O => \h_count[4]_i_2_n_0\ + ); +\h_count[4]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => L(5), + O => \h_count[4]_i_3_n_0\ + ); +\h_count[4]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => L(6), + O => \h_count[4]_i_4_n_0\ + ); +\h_count[4]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => L(7), + O => \h_count[4]_i_5_n_0\ + ); +\h_count[8]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => L(0), + O => \h_count[8]_i_2_n_0\ + ); +\h_count[8]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => L(1), + O => \h_count[8]_i_3_n_0\ + ); +\h_count[8]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => L(2), + O => \h_count[8]_i_4_n_0\ + ); +\h_count[8]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => L(3), + O => \h_count[8]_i_5_n_0\ + ); +\h_count_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => h_count, + D => \h_count_reg[0]_i_3_n_7\, + Q => L(11), + R => \h_count[0]_i_1_n_0\ + ); +\h_count_reg[0]_i_3\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \h_count_reg[0]_i_3_n_0\, + CO(2) => \h_count_reg[0]_i_3_n_1\, + CO(1) => \h_count_reg[0]_i_3_n_2\, + CO(0) => \h_count_reg[0]_i_3_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \h_count_reg[0]_i_3_n_4\, + O(2) => \h_count_reg[0]_i_3_n_5\, + O(1) => \h_count_reg[0]_i_3_n_6\, + O(0) => \h_count_reg[0]_i_3_n_7\, + S(3) => \h_count[0]_i_5_n_0\, + S(2) => \h_count[0]_i_6_n_0\, + S(1) => \h_count[0]_i_7_n_0\, + S(0) => \h_count[0]_i_8_n_0\ + ); +\h_count_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => h_count, + D => \h_count_reg[8]_i_1_n_5\, + Q => L(1), + R => \h_count[0]_i_1_n_0\ + ); +\h_count_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => h_count, + D => \h_count_reg[8]_i_1_n_4\, + Q => L(0), + R => \h_count[0]_i_1_n_0\ + ); +\h_count_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => h_count, + D => \h_count_reg[0]_i_3_n_6\, + Q => L(10), + R => \h_count[0]_i_1_n_0\ + ); +\h_count_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => h_count, + D => \h_count_reg[0]_i_3_n_5\, + Q => L(9), + R => \h_count[0]_i_1_n_0\ + ); +\h_count_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => h_count, + D => \h_count_reg[0]_i_3_n_4\, + Q => L(8), + R => \h_count[0]_i_1_n_0\ + ); +\h_count_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => h_count, + D => \h_count_reg[4]_i_1_n_7\, + Q => L(7), + R => \h_count[0]_i_1_n_0\ + ); +\h_count_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \h_count_reg[0]_i_3_n_0\, + CO(3) => \h_count_reg[4]_i_1_n_0\, + CO(2) => \h_count_reg[4]_i_1_n_1\, + CO(1) => \h_count_reg[4]_i_1_n_2\, + CO(0) => \h_count_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \h_count_reg[4]_i_1_n_4\, + O(2) => \h_count_reg[4]_i_1_n_5\, + O(1) => \h_count_reg[4]_i_1_n_6\, + O(0) => \h_count_reg[4]_i_1_n_7\, + S(3) => \h_count[4]_i_2_n_0\, + S(2) => \h_count[4]_i_3_n_0\, + S(1) => \h_count[4]_i_4_n_0\, + S(0) => \h_count[4]_i_5_n_0\ + ); +\h_count_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => h_count, + D => \h_count_reg[4]_i_1_n_6\, + Q => L(6), + R => \h_count[0]_i_1_n_0\ + ); +\h_count_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => h_count, + D => \h_count_reg[4]_i_1_n_5\, + Q => L(5), + R => \h_count[0]_i_1_n_0\ + ); +\h_count_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => h_count, + D => \h_count_reg[4]_i_1_n_4\, + Q => L(4), + R => \h_count[0]_i_1_n_0\ + ); +\h_count_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => h_count, + D => \h_count_reg[8]_i_1_n_7\, + Q => L(3), + R => \h_count[0]_i_1_n_0\ + ); +\h_count_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \h_count_reg[4]_i_1_n_0\, + CO(3) => \NLW_h_count_reg[8]_i_1_CO_UNCONNECTED\(3), + CO(2) => \h_count_reg[8]_i_1_n_1\, + CO(1) => \h_count_reg[8]_i_1_n_2\, + CO(0) => \h_count_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \h_count_reg[8]_i_1_n_4\, + O(2) => \h_count_reg[8]_i_1_n_5\, + O(1) => \h_count_reg[8]_i_1_n_6\, + O(0) => \h_count_reg[8]_i_1_n_7\, + S(3) => \h_count[8]_i_2_n_0\, + S(2) => \h_count[8]_i_3_n_0\, + S(1) => \h_count[8]_i_4_n_0\, + S(0) => \h_count[8]_i_5_n_0\ + ); +\h_count_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => h_count, + D => \h_count_reg[8]_i_1_n_6\, + Q => L(2), + R => \h_count[0]_i_1_n_0\ + ); +\i__carry__0_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => L(2), + I1 => det_htotal_int(10), + I2 => det_htotal_int(11), + I3 => L(1), + O => \i__carry__0_i_1_n_0\ + ); +\i__carry__0_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => det_htotal_int(10), + I1 => L(2), + I2 => L(1), + I3 => det_htotal_int(11), + O => \i__carry__0_i_1__0_n_0\ + ); +\i__carry__0_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"F4" + ) + port map ( + I0 => det_v0total_int(10), + I1 => \DET_VSYNC.vsync_count_reg__0\(9), + I2 => \DET_VSYNC.vsync_count_reg__0\(10), + O => \i__carry__0_i_1__1_n_0\ + ); +\i__carry__0_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => det_hactive_start_int(10), + I1 => det_v0bp_start_hori_int(10), + I2 => det_v0bp_start_hori_int(11), + I3 => det_hactive_start_int(11), + O => \i__carry__0_i_1__2_n_0\ + ); +\i__carry__0_i_1__3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^time_status_regs[6]\(7), + I1 => det_hbp_start_int(7), + O => \i__carry__0_i_1__3_n_0\ + ); +\i__carry__0_i_1__4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2ED1" + ) + port map ( + I0 => det_hactive_start_int(7), + I1 => ltOp, + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(7), + I3 => det_v0sync_start_hori_int(7), + O => \i__carry__0_i_1__4_n_0\ + ); +\i__carry__0_i_1__5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2ED1" + ) + port map ( + I0 => det_hactive_start_int(7), + I1 => \ltOp_inferred__0/i__carry__0_n_2\, + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(7), + I3 => det_v0bp_start_hori_int(7), + O => \i__carry__0_i_1__5_n_0\ + ); +\i__carry__0_i_1__6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \^q\(7), + I1 => det_hactive_start_int(7), + O => \i__carry__0_i_1__6_n_0\ + ); +\i__carry__0_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => L(4), + I1 => det_htotal_int(8), + I2 => det_htotal_int(9), + I3 => L(3), + O => \i__carry__0_i_2_n_0\ + ); +\i__carry__0_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => det_htotal_int(8), + I1 => L(4), + I2 => L(3), + I3 => det_htotal_int(9), + O => \i__carry__0_i_2__0_n_0\ + ); +\i__carry__0_i_2__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \DET_VSYNC.vsync_count_reg__0\(7), + I1 => det_v0total_int(8), + I2 => det_v0total_int(9), + I3 => \DET_VSYNC.vsync_count_reg__0\(8), + O => \i__carry__0_i_2__1_n_0\ + ); +\i__carry__0_i_2__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => det_hactive_start_int(8), + I1 => det_v0bp_start_hori_int(8), + I2 => det_v0bp_start_hori_int(9), + I3 => det_hactive_start_int(9), + O => \i__carry__0_i_2__2_n_0\ + ); +\i__carry__0_i_2__3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^time_status_regs[6]\(6), + I1 => det_hbp_start_int(6), + O => \i__carry__0_i_2__3_n_0\ + ); +\i__carry__0_i_2__4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2ED1" + ) + port map ( + I0 => det_hactive_start_int(6), + I1 => ltOp, + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(6), + I3 => det_v0sync_start_hori_int(6), + O => \i__carry__0_i_2__4_n_0\ + ); +\i__carry__0_i_2__5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2ED1" + ) + port map ( + I0 => det_hactive_start_int(6), + I1 => \ltOp_inferred__0/i__carry__0_n_2\, + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(6), + I3 => det_v0bp_start_hori_int(6), + O => \i__carry__0_i_2__5_n_0\ + ); +\i__carry__0_i_2__6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \^q\(6), + I1 => det_hactive_start_int(6), + O => \i__carry__0_i_2__6_n_0\ + ); +\i__carry__0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"09" + ) + port map ( + I0 => det_v0total_int(10), + I1 => \DET_VSYNC.vsync_count_reg__0\(9), + I2 => \DET_VSYNC.vsync_count_reg__0\(10), + O => \i__carry__0_i_3_n_0\ + ); +\i__carry__0_i_3__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_v0bp_start_hori_int(11), + I1 => det_hactive_start_int(11), + I2 => det_v0bp_start_hori_int(10), + I3 => det_hactive_start_int(10), + O => \i__carry__0_i_3__0_n_0\ + ); +\i__carry__0_i_3__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => L(0), + O => \i__carry__0_i_3__1_n_0\ + ); +\i__carry__0_i_3__2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => L(0), + O => \i__carry__0_i_3__2_n_0\ + ); +\i__carry__0_i_3__3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^time_status_regs[6]\(5), + I1 => det_hbp_start_int(5), + O => \i__carry__0_i_3__3_n_0\ + ); +\i__carry__0_i_3__4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2ED1" + ) + port map ( + I0 => det_hactive_start_int(5), + I1 => ltOp, + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(5), + I3 => det_v0sync_start_hori_int(5), + O => \i__carry__0_i_3__4_n_0\ + ); +\i__carry__0_i_3__5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2ED1" + ) + port map ( + I0 => det_hactive_start_int(5), + I1 => \ltOp_inferred__0/i__carry__0_n_2\, + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(5), + I3 => det_v0bp_start_hori_int(5), + O => \i__carry__0_i_3__5_n_0\ + ); +\i__carry__0_i_3__6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \^q\(5), + I1 => det_hactive_start_int(5), + O => \i__carry__0_i_3__6_n_0\ + ); +\i__carry__0_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_htotal_int(10), + I1 => L(2), + I2 => det_htotal_int(11), + I3 => L(1), + O => \i__carry__0_i_4_n_0\ + ); +\i__carry__0_i_4__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_v0total_int(9), + I1 => \DET_VSYNC.vsync_count_reg__0\(8), + I2 => det_v0total_int(8), + I3 => \DET_VSYNC.vsync_count_reg__0\(7), + O => \i__carry__0_i_4__0_n_0\ + ); +\i__carry__0_i_4__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_v0bp_start_hori_int(9), + I1 => det_hactive_start_int(9), + I2 => det_v0bp_start_hori_int(8), + I3 => det_hactive_start_int(8), + O => \i__carry__0_i_4__1_n_0\ + ); +\i__carry__0_i_4__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_htotal_int(10), + I1 => L(2), + I2 => det_htotal_int(11), + I3 => L(1), + O => \i__carry__0_i_4__2_n_0\ + ); +\i__carry__0_i_4__3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^time_status_regs[6]\(4), + I1 => det_hbp_start_int(4), + O => \i__carry__0_i_4__3_n_0\ + ); +\i__carry__0_i_4__4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2ED1" + ) + port map ( + I0 => det_hactive_start_int(4), + I1 => ltOp, + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(4), + I3 => det_v0sync_start_hori_int(4), + O => \i__carry__0_i_4__4_n_0\ + ); +\i__carry__0_i_4__5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2ED1" + ) + port map ( + I0 => det_hactive_start_int(4), + I1 => \ltOp_inferred__0/i__carry__0_n_2\, + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(4), + I3 => det_v0bp_start_hori_int(4), + O => \i__carry__0_i_4__5_n_0\ + ); +\i__carry__0_i_4__6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \^q\(4), + I1 => det_hactive_start_int(4), + O => \i__carry__0_i_4__6_n_0\ + ); +\i__carry__0_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_htotal_int(8), + I1 => L(4), + I2 => det_htotal_int(9), + I3 => L(3), + O => \i__carry__0_i_5_n_0\ + ); +\i__carry__0_i_5__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_htotal_int(8), + I1 => L(4), + I2 => det_htotal_int(9), + I3 => L(3), + O => \i__carry__0_i_5__0_n_0\ + ); +\i__carry__1_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \^q\(11), + I1 => det_hactive_start_int(11), + O => \i__carry__1_i_1_n_0\ + ); +\i__carry__1_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^time_status_regs[6]\(11), + I1 => det_hbp_start_int(11), + O => \i__carry__1_i_1__0_n_0\ + ); +\i__carry__1_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2ED1" + ) + port map ( + I0 => det_hactive_start_int(11), + I1 => ltOp, + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(11), + I3 => det_v0sync_start_hori_int(11), + O => \i__carry__1_i_1__1_n_0\ + ); +\i__carry__1_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2ED1" + ) + port map ( + I0 => det_hactive_start_int(11), + I1 => \ltOp_inferred__0/i__carry__0_n_2\, + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(11), + I3 => det_v0bp_start_hori_int(11), + O => \i__carry__1_i_1__2_n_0\ + ); +\i__carry__1_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^time_status_regs[6]\(10), + I1 => det_hbp_start_int(10), + O => \i__carry__1_i_2_n_0\ + ); +\i__carry__1_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2ED1" + ) + port map ( + I0 => det_hactive_start_int(10), + I1 => ltOp, + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(10), + I3 => det_v0sync_start_hori_int(10), + O => \i__carry__1_i_2__0_n_0\ + ); +\i__carry__1_i_2__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2ED1" + ) + port map ( + I0 => det_hactive_start_int(10), + I1 => \ltOp_inferred__0/i__carry__0_n_2\, + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(10), + I3 => det_v0bp_start_hori_int(10), + O => \i__carry__1_i_2__1_n_0\ + ); +\i__carry__1_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \^q\(10), + I1 => det_hactive_start_int(10), + O => \i__carry__1_i_2__2_n_0\ + ); +\i__carry__1_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^time_status_regs[6]\(9), + I1 => det_hbp_start_int(9), + O => \i__carry__1_i_3_n_0\ + ); +\i__carry__1_i_3__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2ED1" + ) + port map ( + I0 => det_hactive_start_int(9), + I1 => ltOp, + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(9), + I3 => det_v0sync_start_hori_int(9), + O => \i__carry__1_i_3__0_n_0\ + ); +\i__carry__1_i_3__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2ED1" + ) + port map ( + I0 => det_hactive_start_int(9), + I1 => \ltOp_inferred__0/i__carry__0_n_2\, + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(9), + I3 => det_v0bp_start_hori_int(9), + O => \i__carry__1_i_3__1_n_0\ + ); +\i__carry__1_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \^q\(9), + I1 => det_hactive_start_int(9), + O => \i__carry__1_i_3__2_n_0\ + ); +\i__carry__1_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^time_status_regs[6]\(8), + I1 => det_hbp_start_int(8), + O => \i__carry__1_i_4_n_0\ + ); +\i__carry__1_i_4__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2ED1" + ) + port map ( + I0 => det_hactive_start_int(8), + I1 => ltOp, + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(8), + I3 => det_v0sync_start_hori_int(8), + O => \i__carry__1_i_4__0_n_0\ + ); +\i__carry__1_i_4__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2ED1" + ) + port map ( + I0 => det_hactive_start_int(8), + I1 => \ltOp_inferred__0/i__carry__0_n_2\, + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(8), + I3 => det_v0bp_start_hori_int(8), + O => \i__carry__1_i_4__1_n_0\ + ); +\i__carry__1_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \^q\(8), + I1 => det_hactive_start_int(8), + O => \i__carry__1_i_4__2_n_0\ + ); +\i__carry_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => L(6), + I1 => det_htotal_int(6), + I2 => det_htotal_int(7), + I3 => L(5), + O => \i__carry_i_1_n_0\ + ); +\i__carry_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => det_htotal_int(6), + I1 => L(6), + I2 => L(5), + I3 => det_htotal_int(7), + O => \i__carry_i_1__0_n_0\ + ); +\i__carry_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \DET_VSYNC.vsync_count_reg__0\(5), + I1 => det_v0total_int(6), + I2 => det_v0total_int(7), + I3 => \DET_VSYNC.vsync_count_reg__0\(6), + O => \i__carry_i_1__1_n_0\ + ); +\i__carry_i_1__10\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => active_video_count_last(10), + I1 => \DET_HACTIVE.active_video_count_reg\(10), + I2 => active_video_count_last(9), + I3 => \DET_HACTIVE.active_video_count_reg\(9), + I4 => \DET_HACTIVE.active_video_count_reg\(11), + I5 => active_video_count_last(11), + O => \i__carry_i_1__10_n_0\ + ); +\i__carry_i_1__11\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^time_status_regs[6]\(3), + I1 => det_hbp_start_int(3), + O => \i__carry_i_1__11_n_0\ + ); +\i__carry_i_1__12\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \^q\(3), + I1 => det_hactive_start_int(3), + O => \i__carry_i_1__12_n_0\ + ); +\i__carry_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => det_hactive_start_int(6), + I1 => det_v0bp_start_hori_int(6), + I2 => det_v0bp_start_hori_int(7), + I3 => det_hactive_start_int(7), + O => \i__carry_i_1__2_n_0\ + ); +\i__carry_i_1__3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => ltOp, + O => \i__carry_i_1__3_n_0\ + ); +\i__carry_i_1__4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \ltOp_inferred__0/i__carry__0_n_2\, + O => \i__carry_i_1__4_n_0\ + ); +\i__carry_i_1__5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => det_hsync_start_last(10), + I1 => det_hsync_start_int(10), + I2 => det_hsync_start_last(9), + I3 => det_hsync_start_int(9), + I4 => det_hsync_start_int(11), + I5 => det_hsync_start_last(11), + O => \i__carry_i_1__5_n_0\ + ); +\i__carry_i_1__6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_v0bp_start_last(9), + I1 => det_v0bp_start_int(9), + I2 => det_v0bp_start_int(10), + I3 => det_v0bp_start_last(10), + O => \i__carry_i_1__6_n_0\ + ); +\i__carry_i_1__7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => det_v0bp_start_hori_last(10), + I1 => det_v0bp_start_hori_int(10), + I2 => det_v0bp_start_hori_last(9), + I3 => det_v0bp_start_hori_int(9), + I4 => det_v0bp_start_hori_int(11), + I5 => det_v0bp_start_hori_last(11), + O => \i__carry_i_1__7_n_0\ + ); +\i__carry_i_1__8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_v0sync_start_last(9), + I1 => det_v0sync_start_int(9), + I2 => det_v0sync_start_int(10), + I3 => det_v0sync_start_last(10), + O => \i__carry_i_1__8_n_0\ + ); +\i__carry_i_1__9\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => det_v0sync_start_hori_last(10), + I1 => det_v0sync_start_hori_int(10), + I2 => det_v0sync_start_hori_last(9), + I3 => det_v0sync_start_hori_int(9), + I4 => det_v0sync_start_hori_int(11), + I5 => det_v0sync_start_hori_last(11), + O => \i__carry_i_1__9_n_0\ + ); +\i__carry_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => L(8), + I1 => det_htotal_int(4), + I2 => det_htotal_int(5), + I3 => L(7), + O => \i__carry_i_2_n_0\ + ); +\i__carry_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => det_htotal_int(4), + I1 => L(8), + I2 => L(7), + I3 => det_htotal_int(5), + O => \i__carry_i_2__0_n_0\ + ); +\i__carry_i_2__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \DET_VSYNC.vsync_count_reg__0\(3), + I1 => det_v0total_int(4), + I2 => det_v0total_int(5), + I3 => \DET_VSYNC.vsync_count_reg__0\(4), + O => \i__carry_i_2__1_n_0\ + ); +\i__carry_i_2__10\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2ED1" + ) + port map ( + I0 => det_hactive_start_int(3), + I1 => ltOp, + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(3), + I3 => det_v0sync_start_hori_int(3), + O => \i__carry_i_2__10_n_0\ + ); +\i__carry_i_2__11\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2ED1" + ) + port map ( + I0 => det_hactive_start_int(3), + I1 => \ltOp_inferred__0/i__carry__0_n_2\, + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(3), + I3 => det_v0bp_start_hori_int(3), + O => \i__carry_i_2__11_n_0\ + ); +\i__carry_i_2__12\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \^q\(2), + I1 => det_hactive_start_int(2), + O => \i__carry_i_2__12_n_0\ + ); +\i__carry_i_2__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => det_hactive_start_int(4), + I1 => det_v0bp_start_hori_int(4), + I2 => det_v0bp_start_hori_int(5), + I3 => det_hactive_start_int(5), + O => \i__carry_i_2__2_n_0\ + ); +\i__carry_i_2__3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => det_hsync_start_last(7), + I1 => det_hsync_start_int(7), + I2 => det_hsync_start_last(6), + I3 => det_hsync_start_int(6), + I4 => det_hsync_start_int(8), + I5 => det_hsync_start_last(8), + O => \i__carry_i_2__3_n_0\ + ); +\i__carry_i_2__4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => det_v0bp_start_last(7), + I1 => det_v0bp_start_int(7), + I2 => det_v0bp_start_last(6), + I3 => det_v0bp_start_int(6), + I4 => det_v0bp_start_int(8), + I5 => det_v0bp_start_last(8), + O => \i__carry_i_2__4_n_0\ + ); +\i__carry_i_2__5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => det_v0bp_start_hori_last(7), + I1 => det_v0bp_start_hori_int(7), + I2 => det_v0bp_start_hori_last(6), + I3 => det_v0bp_start_hori_int(6), + I4 => det_v0bp_start_hori_int(8), + I5 => det_v0bp_start_hori_last(8), + O => \i__carry_i_2__5_n_0\ + ); +\i__carry_i_2__6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => det_v0sync_start_last(7), + I1 => det_v0sync_start_int(7), + I2 => det_v0sync_start_last(6), + I3 => det_v0sync_start_int(6), + I4 => det_v0sync_start_int(8), + I5 => det_v0sync_start_last(8), + O => \i__carry_i_2__6_n_0\ + ); +\i__carry_i_2__7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => det_v0sync_start_hori_last(7), + I1 => det_v0sync_start_hori_int(7), + I2 => det_v0sync_start_hori_last(6), + I3 => det_v0sync_start_hori_int(6), + I4 => det_v0sync_start_hori_int(8), + I5 => det_v0sync_start_hori_last(8), + O => \i__carry_i_2__7_n_0\ + ); +\i__carry_i_2__8\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => active_video_count_last(7), + I1 => \DET_HACTIVE.active_video_count_reg\(7), + I2 => active_video_count_last(6), + I3 => \DET_HACTIVE.active_video_count_reg\(6), + I4 => \DET_HACTIVE.active_video_count_reg\(8), + I5 => active_video_count_last(8), + O => \i__carry_i_2__8_n_0\ + ); +\i__carry_i_2__9\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^time_status_regs[6]\(2), + I1 => det_hbp_start_int(2), + O => \i__carry_i_2__9_n_0\ + ); +\i__carry_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => L(10), + I1 => det_htotal_int(2), + I2 => det_htotal_int(3), + I3 => L(9), + O => \i__carry_i_3_n_0\ + ); +\i__carry_i_3__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => det_htotal_int(2), + I1 => L(10), + I2 => L(9), + I3 => det_htotal_int(3), + O => \i__carry_i_3__0_n_0\ + ); +\i__carry_i_3__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => \DET_VSYNC.vsync_count_reg__0\(1), + I1 => det_v0total_int(2), + I2 => det_v0total_int(3), + I3 => \DET_VSYNC.vsync_count_reg__0\(2), + O => \i__carry_i_3__1_n_0\ + ); +\i__carry_i_3__10\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2ED1" + ) + port map ( + I0 => det_hactive_start_int(2), + I1 => ltOp, + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(2), + I3 => det_v0sync_start_hori_int(2), + O => \i__carry_i_3__10_n_0\ + ); +\i__carry_i_3__11\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2ED1" + ) + port map ( + I0 => det_hactive_start_int(2), + I1 => \ltOp_inferred__0/i__carry__0_n_2\, + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(2), + I3 => det_v0bp_start_hori_int(2), + O => \i__carry_i_3__11_n_0\ + ); +\i__carry_i_3__12\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \^q\(1), + I1 => det_hactive_start_int(1), + O => \i__carry_i_3__12_n_0\ + ); +\i__carry_i_3__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => det_hactive_start_int(2), + I1 => det_v0bp_start_hori_int(2), + I2 => det_v0bp_start_hori_int(3), + I3 => det_hactive_start_int(3), + O => \i__carry_i_3__2_n_0\ + ); +\i__carry_i_3__3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => det_hsync_start_last(4), + I1 => det_hsync_start_int(4), + I2 => det_hsync_start_last(3), + I3 => det_hsync_start_int(3), + I4 => det_hsync_start_int(5), + I5 => det_hsync_start_last(5), + O => \i__carry_i_3__3_n_0\ + ); +\i__carry_i_3__4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => det_v0bp_start_last(4), + I1 => det_v0bp_start_int(4), + I2 => det_v0bp_start_last(3), + I3 => det_v0bp_start_int(3), + I4 => det_v0bp_start_int(5), + I5 => det_v0bp_start_last(5), + O => \i__carry_i_3__4_n_0\ + ); +\i__carry_i_3__5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => det_v0bp_start_hori_last(4), + I1 => det_v0bp_start_hori_int(4), + I2 => det_v0bp_start_hori_last(3), + I3 => det_v0bp_start_hori_int(3), + I4 => det_v0bp_start_hori_int(5), + I5 => det_v0bp_start_hori_last(5), + O => \i__carry_i_3__5_n_0\ + ); +\i__carry_i_3__6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => det_v0sync_start_last(4), + I1 => det_v0sync_start_int(4), + I2 => det_v0sync_start_last(3), + I3 => det_v0sync_start_int(3), + I4 => det_v0sync_start_int(5), + I5 => det_v0sync_start_last(5), + O => \i__carry_i_3__6_n_0\ + ); +\i__carry_i_3__7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => det_v0sync_start_hori_last(4), + I1 => det_v0sync_start_hori_int(4), + I2 => det_v0sync_start_hori_last(3), + I3 => det_v0sync_start_hori_int(3), + I4 => det_v0sync_start_hori_int(5), + I5 => det_v0sync_start_hori_last(5), + O => \i__carry_i_3__7_n_0\ + ); +\i__carry_i_3__8\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => active_video_count_last(4), + I1 => \DET_HACTIVE.active_video_count_reg\(4), + I2 => active_video_count_last(3), + I3 => \DET_HACTIVE.active_video_count_reg\(3), + I4 => \DET_HACTIVE.active_video_count_reg\(5), + I5 => active_video_count_last(5), + O => \i__carry_i_3__8_n_0\ + ); +\i__carry_i_3__9\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^time_status_regs[6]\(1), + I1 => det_hbp_start_int(1), + O => \i__carry_i_3__9_n_0\ + ); +\i__carry_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => L(11), + I1 => det_htotal_int(1), + O => \i__carry_i_4_n_0\ + ); +\i__carry_i_4__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"D4" + ) + port map ( + I0 => L(11), + I1 => det_htotal_int(1), + I2 => det_htotal_int(0), + O => \i__carry_i_4__0_n_0\ + ); +\i__carry_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \DET_VSYNC.vsync_count_reg__0\(0), + I1 => det_v0total_int(1), + O => \i__carry_i_4__1_n_0\ + ); +\i__carry_i_4__10\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2ED1" + ) + port map ( + I0 => det_hactive_start_int(1), + I1 => ltOp, + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(1), + I3 => det_v0sync_start_hori_int(1), + O => \i__carry_i_4__10_n_0\ + ); +\i__carry_i_4__11\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2ED1" + ) + port map ( + I0 => det_hactive_start_int(1), + I1 => \ltOp_inferred__0/i__carry__0_n_2\, + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(1), + I3 => det_v0bp_start_hori_int(1), + O => \i__carry_i_4__11_n_0\ + ); +\i__carry_i_4__12\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \^q\(0), + I1 => det_hactive_start_int(0), + O => \i__carry_i_4__12_n_0\ + ); +\i__carry_i_4__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => det_hactive_start_int(0), + I1 => det_v0bp_start_hori_int(0), + I2 => det_v0bp_start_hori_int(1), + I3 => det_hactive_start_int(1), + O => \i__carry_i_4__2_n_0\ + ); +\i__carry_i_4__3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => det_hsync_start_last(1), + I1 => det_hsync_start_int(1), + I2 => det_hsync_start_last(0), + I3 => det_hsync_start_int(0), + I4 => det_hsync_start_int(2), + I5 => det_hsync_start_last(2), + O => \i__carry_i_4__3_n_0\ + ); +\i__carry_i_4__4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => det_v0bp_start_last(1), + I1 => det_v0bp_start_int(1), + I2 => det_v0bp_start_last(0), + I3 => det_v0bp_start_int(0), + I4 => det_v0bp_start_int(2), + I5 => det_v0bp_start_last(2), + O => \i__carry_i_4__4_n_0\ + ); +\i__carry_i_4__5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => det_v0bp_start_hori_last(1), + I1 => det_v0bp_start_hori_int(1), + I2 => det_v0bp_start_hori_last(0), + I3 => det_v0bp_start_hori_int(0), + I4 => det_v0bp_start_hori_int(2), + I5 => det_v0bp_start_hori_last(2), + O => \i__carry_i_4__5_n_0\ + ); +\i__carry_i_4__6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => det_v0sync_start_last(1), + I1 => det_v0sync_start_int(1), + I2 => det_v0sync_start_last(0), + I3 => det_v0sync_start_int(0), + I4 => det_v0sync_start_int(2), + I5 => det_v0sync_start_last(2), + O => \i__carry_i_4__6_n_0\ + ); +\i__carry_i_4__7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => det_v0sync_start_hori_last(1), + I1 => det_v0sync_start_hori_int(1), + I2 => det_v0sync_start_hori_last(0), + I3 => det_v0sync_start_hori_int(0), + I4 => det_v0sync_start_hori_int(2), + I5 => det_v0sync_start_hori_last(2), + O => \i__carry_i_4__7_n_0\ + ); +\i__carry_i_4__8\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => active_video_count_last(1), + I1 => \DET_HACTIVE.active_video_count_reg\(1), + I2 => active_video_count_last(0), + I3 => \DET_HACTIVE.active_video_count_reg\(0), + I4 => \DET_HACTIVE.active_video_count_reg\(2), + I5 => active_video_count_last(2), + O => \i__carry_i_4__8_n_0\ + ); +\i__carry_i_4__9\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^time_status_regs[6]\(0), + I1 => det_hbp_start_int(0), + O => \i__carry_i_4__9_n_0\ + ); +\i__carry_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_htotal_int(6), + I1 => L(6), + I2 => det_htotal_int(7), + I3 => L(5), + O => \i__carry_i_5_n_0\ + ); +\i__carry_i_5__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_v0total_int(7), + I1 => \DET_VSYNC.vsync_count_reg__0\(6), + I2 => det_v0total_int(6), + I3 => \DET_VSYNC.vsync_count_reg__0\(5), + O => \i__carry_i_5__0_n_0\ + ); +\i__carry_i_5__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_v0bp_start_hori_int(7), + I1 => det_hactive_start_int(7), + I2 => det_v0bp_start_hori_int(6), + I3 => det_hactive_start_int(6), + O => \i__carry_i_5__1_n_0\ + ); +\i__carry_i_5__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_htotal_int(6), + I1 => L(6), + I2 => det_htotal_int(7), + I3 => L(5), + O => \i__carry_i_5__2_n_0\ + ); +\i__carry_i_5__3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E2" + ) + port map ( + I0 => det_hactive_start_int(0), + I1 => ltOp, + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(0), + O => \i__carry_i_5__3_n_0\ + ); +\i__carry_i_5__4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E2" + ) + port map ( + I0 => det_hactive_start_int(0), + I1 => \ltOp_inferred__0/i__carry__0_n_2\, + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][11]\(0), + O => \i__carry_i_5__4_n_0\ + ); +\i__carry_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_htotal_int(4), + I1 => L(8), + I2 => det_htotal_int(5), + I3 => L(7), + O => \i__carry_i_6_n_0\ + ); +\i__carry_i_6__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_v0total_int(5), + I1 => \DET_VSYNC.vsync_count_reg__0\(4), + I2 => det_v0total_int(4), + I3 => \DET_VSYNC.vsync_count_reg__0\(3), + O => \i__carry_i_6__0_n_0\ + ); +\i__carry_i_6__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_v0bp_start_hori_int(5), + I1 => det_hactive_start_int(5), + I2 => det_v0bp_start_hori_int(4), + I3 => det_hactive_start_int(4), + O => \i__carry_i_6__1_n_0\ + ); +\i__carry_i_6__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_htotal_int(4), + I1 => L(8), + I2 => det_htotal_int(5), + I3 => L(7), + O => \i__carry_i_6__2_n_0\ + ); +\i__carry_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_htotal_int(2), + I1 => L(10), + I2 => det_htotal_int(3), + I3 => L(9), + O => \i__carry_i_7_n_0\ + ); +\i__carry_i_7__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_v0total_int(3), + I1 => \DET_VSYNC.vsync_count_reg__0\(2), + I2 => det_v0total_int(2), + I3 => \DET_VSYNC.vsync_count_reg__0\(1), + O => \i__carry_i_7__0_n_0\ + ); +\i__carry_i_7__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_v0bp_start_hori_int(3), + I1 => det_hactive_start_int(3), + I2 => det_v0bp_start_hori_int(2), + I3 => det_hactive_start_int(2), + O => \i__carry_i_7__1_n_0\ + ); +\i__carry_i_7__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_htotal_int(2), + I1 => L(10), + I2 => det_htotal_int(3), + I3 => L(9), + O => \i__carry_i_7__2_n_0\ + ); +\i__carry_i_8\: unisim.vcomponents.LUT3 + generic map( + INIT => X"09" + ) + port map ( + I0 => det_htotal_int(1), + I1 => L(11), + I2 => det_htotal_int(0), + O => \i__carry_i_8_n_0\ + ); +\i__carry_i_8__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"41" + ) + port map ( + I0 => det_v0total_int(0), + I1 => det_v0total_int(1), + I2 => \DET_VSYNC.vsync_count_reg__0\(0), + O => \i__carry_i_8__0_n_0\ + ); +\i__carry_i_8__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_v0bp_start_hori_int(1), + I1 => det_hactive_start_int(1), + I2 => det_v0bp_start_hori_int(0), + I3 => det_hactive_start_int(0), + O => \i__carry_i_8__1_n_0\ + ); +\i__carry_i_8__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"09" + ) + port map ( + I0 => det_htotal_int(1), + I1 => L(11), + I2 => det_htotal_int(0), + O => \i__carry_i_8__2_n_0\ + ); +\intr_error_int[6]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => resetn_out, + O => \^reset\ + ); +\intr_status_int[11]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF03C057D503C0" + ) + port map ( + I0 => det_vblank_d, + I1 => active_video_in, + I2 => \^time_status_regs[3]\(2), + I3 => det_active_video_d, + I4 => intc_if(0), + I5 => vblank_in, + O => \intr_status_int_reg[11]\ + ); +\intr_status_int[9]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \^active_video_lock_int\, + I1 => \^hsync_lock_int\, + I2 => \^vsync_lock_int\, + O => intr_status_int17_out + ); +leqOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => leqOp_carry_n_0, + CO(2) => leqOp_carry_n_1, + CO(1) => leqOp_carry_n_2, + CO(0) => leqOp_carry_n_3, + CYINIT => '1', + DI(3) => leqOp_carry_i_1_n_0, + DI(2) => leqOp_carry_i_2_n_0, + DI(1) => leqOp_carry_i_3_n_0, + DI(0) => leqOp_carry_i_4_n_0, + O(3 downto 0) => NLW_leqOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => leqOp_carry_i_5_n_0, + S(2) => leqOp_carry_i_6_n_0, + S(1) => leqOp_carry_i_7_n_0, + S(0) => leqOp_carry_i_8_n_0 + ); +\leqOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => leqOp_carry_n_0, + CO(3) => \NLW_leqOp_carry__0_CO_UNCONNECTED\(3), + CO(2) => leqOp, + CO(1) => \leqOp_carry__0_n_2\, + CO(0) => \leqOp_carry__0_n_3\, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1) => \leqOp_carry__0_i_1_n_0\, + DI(0) => \leqOp_carry__0_i_2_n_0\, + O(3 downto 0) => \NLW_leqOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => '0', + S(2) => \leqOp_carry__0_i_3_n_0\, + S(1) => \leqOp_carry__0_i_4_n_0\, + S(0) => \leqOp_carry__0_i_5_n_0\ + ); +\leqOp_carry__0_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => det_htotal_int(10), + I1 => \DET_HACTIVE.active_video_count_reg\(9), + I2 => \DET_HACTIVE.active_video_count_reg\(10), + I3 => det_htotal_int(11), + O => \leqOp_carry__0_i_1_n_0\ + ); +\leqOp_carry__0_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => det_htotal_int(8), + I1 => \DET_HACTIVE.active_video_count_reg\(7), + I2 => \DET_HACTIVE.active_video_count_reg\(8), + I3 => det_htotal_int(9), + O => \leqOp_carry__0_i_2_n_0\ + ); +\leqOp_carry__0_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \DET_HACTIVE.active_video_count_reg\(11), + O => \leqOp_carry__0_i_3_n_0\ + ); +\leqOp_carry__0_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \DET_HACTIVE.active_video_count_reg\(10), + I1 => det_htotal_int(11), + I2 => \DET_HACTIVE.active_video_count_reg\(9), + I3 => det_htotal_int(10), + O => \leqOp_carry__0_i_4_n_0\ + ); +\leqOp_carry__0_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \DET_HACTIVE.active_video_count_reg\(8), + I1 => det_htotal_int(9), + I2 => \DET_HACTIVE.active_video_count_reg\(7), + I3 => det_htotal_int(8), + O => \leqOp_carry__0_i_5_n_0\ + ); +leqOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => det_htotal_int(6), + I1 => \DET_HACTIVE.active_video_count_reg\(5), + I2 => \DET_HACTIVE.active_video_count_reg\(6), + I3 => det_htotal_int(7), + O => leqOp_carry_i_1_n_0 + ); +leqOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => det_htotal_int(4), + I1 => \DET_HACTIVE.active_video_count_reg\(3), + I2 => \DET_HACTIVE.active_video_count_reg\(4), + I3 => det_htotal_int(5), + O => leqOp_carry_i_2_n_0 + ); +leqOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => det_htotal_int(2), + I1 => \DET_HACTIVE.active_video_count_reg\(1), + I2 => \DET_HACTIVE.active_video_count_reg\(2), + I3 => det_htotal_int(3), + O => leqOp_carry_i_3_n_0 + ); +leqOp_carry_i_4: unisim.vcomponents.LUT3 + generic map( + INIT => X"D4" + ) + port map ( + I0 => \DET_HACTIVE.active_video_count_reg\(0), + I1 => det_htotal_int(1), + I2 => det_htotal_int(0), + O => leqOp_carry_i_4_n_0 + ); +leqOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \DET_HACTIVE.active_video_count_reg\(6), + I1 => det_htotal_int(7), + I2 => \DET_HACTIVE.active_video_count_reg\(5), + I3 => det_htotal_int(6), + O => leqOp_carry_i_5_n_0 + ); +leqOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \DET_HACTIVE.active_video_count_reg\(4), + I1 => det_htotal_int(5), + I2 => \DET_HACTIVE.active_video_count_reg\(3), + I3 => det_htotal_int(4), + O => leqOp_carry_i_6_n_0 + ); +leqOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => \DET_HACTIVE.active_video_count_reg\(2), + I1 => det_htotal_int(3), + I2 => \DET_HACTIVE.active_video_count_reg\(1), + I3 => det_htotal_int(2), + O => leqOp_carry_i_7_n_0 + ); +leqOp_carry_i_8: unisim.vcomponents.LUT3 + generic map( + INIT => X"09" + ) + port map ( + I0 => det_htotal_int(1), + I1 => \DET_HACTIVE.active_video_count_reg\(0), + I2 => det_htotal_int(0), + O => leqOp_carry_i_8_n_0 + ); +\leqOp_inferred__0/i__carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \leqOp_inferred__0/i__carry_n_0\, + CO(2) => \leqOp_inferred__0/i__carry_n_1\, + CO(1) => \leqOp_inferred__0/i__carry_n_2\, + CO(0) => \leqOp_inferred__0/i__carry_n_3\, + CYINIT => '1', + DI(3) => \i__carry_i_1__0_n_0\, + DI(2) => \i__carry_i_2__0_n_0\, + DI(1) => \i__carry_i_3__0_n_0\, + DI(0) => \i__carry_i_4__0_n_0\, + O(3 downto 0) => \NLW_leqOp_inferred__0/i__carry_O_UNCONNECTED\(3 downto 0), + S(3) => \i__carry_i_5_n_0\, + S(2) => \i__carry_i_6_n_0\, + S(1) => \i__carry_i_7_n_0\, + S(0) => \i__carry_i_8_n_0\ + ); +\leqOp_inferred__0/i__carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \leqOp_inferred__0/i__carry_n_0\, + CO(3) => \NLW_leqOp_inferred__0/i__carry__0_CO_UNCONNECTED\(3), + CO(2) => leqOp_1, + CO(1) => \leqOp_inferred__0/i__carry__0_n_2\, + CO(0) => \leqOp_inferred__0/i__carry__0_n_3\, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1) => \i__carry__0_i_1__0_n_0\, + DI(0) => \i__carry__0_i_2__0_n_0\, + O(3 downto 0) => \NLW_leqOp_inferred__0/i__carry__0_O_UNCONNECTED\(3 downto 0), + S(3) => '0', + S(2) => \i__carry__0_i_3__1_n_0\, + S(1) => \i__carry__0_i_4_n_0\, + S(0) => \i__carry__0_i_5_n_0\ + ); +line_end_d_reg: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => '1', + D => line_end, + Q => line_end_d_reg_n_0, + R => '0' + ); +ltOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => ltOp_carry_n_0, + CO(2) => ltOp_carry_n_1, + CO(1) => ltOp_carry_n_2, + CO(0) => ltOp_carry_n_3, + CYINIT => '0', + DI(3) => ltOp_carry_i_1_n_0, + DI(2) => ltOp_carry_i_2_n_0, + DI(1) => ltOp_carry_i_3_n_0, + DI(0) => ltOp_carry_i_4_n_0, + O(3 downto 0) => NLW_ltOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => ltOp_carry_i_5_n_0, + S(2) => ltOp_carry_i_6_n_0, + S(1) => ltOp_carry_i_7_n_0, + S(0) => ltOp_carry_i_8_n_0 + ); +\ltOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => ltOp_carry_n_0, + CO(3 downto 2) => \NLW_ltOp_carry__0_CO_UNCONNECTED\(3 downto 2), + CO(1) => ltOp, + CO(0) => \ltOp_carry__0_n_3\, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1) => \ltOp_carry__0_i_1_n_0\, + DI(0) => \ltOp_carry__0_i_2_n_0\, + O(3 downto 0) => \NLW_ltOp_carry__0_O_UNCONNECTED\(3 downto 0), + S(3 downto 2) => B"00", + S(1) => \ltOp_carry__0_i_3_n_0\, + S(0) => \ltOp_carry__0_i_4_n_0\ + ); +\ltOp_carry__0_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => det_hactive_start_int(10), + I1 => det_v0sync_start_hori_int(10), + I2 => det_v0sync_start_hori_int(11), + I3 => det_hactive_start_int(11), + O => \ltOp_carry__0_i_1_n_0\ + ); +\ltOp_carry__0_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => det_hactive_start_int(8), + I1 => det_v0sync_start_hori_int(8), + I2 => det_v0sync_start_hori_int(9), + I3 => det_hactive_start_int(9), + O => \ltOp_carry__0_i_2_n_0\ + ); +\ltOp_carry__0_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_v0sync_start_hori_int(11), + I1 => det_hactive_start_int(11), + I2 => det_v0sync_start_hori_int(10), + I3 => det_hactive_start_int(10), + O => \ltOp_carry__0_i_3_n_0\ + ); +\ltOp_carry__0_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_v0sync_start_hori_int(9), + I1 => det_hactive_start_int(9), + I2 => det_v0sync_start_hori_int(8), + I3 => det_hactive_start_int(8), + O => \ltOp_carry__0_i_4_n_0\ + ); +ltOp_carry_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => det_hactive_start_int(6), + I1 => det_v0sync_start_hori_int(6), + I2 => det_v0sync_start_hori_int(7), + I3 => det_hactive_start_int(7), + O => ltOp_carry_i_1_n_0 + ); +ltOp_carry_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => det_hactive_start_int(4), + I1 => det_v0sync_start_hori_int(4), + I2 => det_v0sync_start_hori_int(5), + I3 => det_hactive_start_int(5), + O => ltOp_carry_i_2_n_0 + ); +ltOp_carry_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => det_hactive_start_int(2), + I1 => det_v0sync_start_hori_int(2), + I2 => det_v0sync_start_hori_int(3), + I3 => det_hactive_start_int(3), + O => ltOp_carry_i_3_n_0 + ); +ltOp_carry_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => det_hactive_start_int(0), + I1 => det_v0sync_start_hori_int(0), + I2 => det_v0sync_start_hori_int(1), + I3 => det_hactive_start_int(1), + O => ltOp_carry_i_4_n_0 + ); +ltOp_carry_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_v0sync_start_hori_int(7), + I1 => det_hactive_start_int(7), + I2 => det_v0sync_start_hori_int(6), + I3 => det_hactive_start_int(6), + O => ltOp_carry_i_5_n_0 + ); +ltOp_carry_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_v0sync_start_hori_int(5), + I1 => det_hactive_start_int(5), + I2 => det_v0sync_start_hori_int(4), + I3 => det_hactive_start_int(4), + O => ltOp_carry_i_6_n_0 + ); +ltOp_carry_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_v0sync_start_hori_int(3), + I1 => det_hactive_start_int(3), + I2 => det_v0sync_start_hori_int(2), + I3 => det_hactive_start_int(2), + O => ltOp_carry_i_7_n_0 + ); +ltOp_carry_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => det_v0sync_start_hori_int(1), + I1 => det_hactive_start_int(1), + I2 => det_v0sync_start_hori_int(0), + I3 => det_hactive_start_int(0), + O => ltOp_carry_i_8_n_0 + ); +\ltOp_inferred__0/i__carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \ltOp_inferred__0/i__carry_n_0\, + CO(2) => \ltOp_inferred__0/i__carry_n_1\, + CO(1) => \ltOp_inferred__0/i__carry_n_2\, + CO(0) => \ltOp_inferred__0/i__carry_n_3\, + CYINIT => '0', + DI(3) => \i__carry_i_1__2_n_0\, + DI(2) => \i__carry_i_2__2_n_0\, + DI(1) => \i__carry_i_3__2_n_0\, + DI(0) => \i__carry_i_4__2_n_0\, + O(3 downto 0) => \NLW_ltOp_inferred__0/i__carry_O_UNCONNECTED\(3 downto 0), + S(3) => \i__carry_i_5__1_n_0\, + S(2) => \i__carry_i_6__1_n_0\, + S(1) => \i__carry_i_7__1_n_0\, + S(0) => \i__carry_i_8__1_n_0\ + ); +\ltOp_inferred__0/i__carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \ltOp_inferred__0/i__carry_n_0\, + CO(3 downto 2) => \NLW_ltOp_inferred__0/i__carry__0_CO_UNCONNECTED\(3 downto 2), + CO(1) => \ltOp_inferred__0/i__carry__0_n_2\, + CO(0) => \ltOp_inferred__0/i__carry__0_n_3\, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1) => \i__carry__0_i_1__2_n_0\, + DI(0) => \i__carry__0_i_2__2_n_0\, + O(3 downto 0) => \NLW_ltOp_inferred__0/i__carry__0_O_UNCONNECTED\(3 downto 0), + S(3 downto 2) => B"00", + S(1) => \i__carry__0_i_3__0_n_0\, + S(0) => \i__carry__0_i_4__1_n_0\ + ); +minusOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => minusOp_carry_n_0, + CO(2) => minusOp_carry_n_1, + CO(1) => minusOp_carry_n_2, + CO(0) => minusOp_carry_n_3, + CYINIT => '1', + DI(3 downto 0) => det_hfp_start_int(3 downto 0), + O(3 downto 0) => minusOp1_out(3 downto 0), + S(3) => minusOp_carry_i_1_n_0, + S(2) => minusOp_carry_i_2_n_0, + S(1) => minusOp_carry_i_3_n_0, + S(0) => minusOp_carry_i_4_n_0 + ); +\minusOp_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => minusOp_carry_n_0, + CO(3) => \minusOp_carry__0_n_0\, + CO(2) => \minusOp_carry__0_n_1\, + CO(1) => \minusOp_carry__0_n_2\, + CO(0) => \minusOp_carry__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => det_hfp_start_int(7 downto 4), + O(3 downto 0) => minusOp1_out(7 downto 4), + S(3) => \minusOp_carry__0_i_1_n_0\, + S(2) => \minusOp_carry__0_i_2_n_0\, + S(1) => \minusOp_carry__0_i_3_n_0\, + S(0) => \minusOp_carry__0_i_4_n_0\ + ); +\minusOp_carry__0_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => det_hfp_start_int(7), + I1 => det_hactive_start_int(7), + O => \minusOp_carry__0_i_1_n_0\ + ); +\minusOp_carry__0_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => det_hfp_start_int(6), + I1 => det_hactive_start_int(6), + O => \minusOp_carry__0_i_2_n_0\ + ); +\minusOp_carry__0_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => det_hfp_start_int(5), + I1 => det_hactive_start_int(5), + O => \minusOp_carry__0_i_3_n_0\ + ); +\minusOp_carry__0_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => det_hfp_start_int(4), + I1 => det_hactive_start_int(4), + O => \minusOp_carry__0_i_4_n_0\ + ); +\minusOp_carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minusOp_carry__0_n_0\, + CO(3) => \NLW_minusOp_carry__1_CO_UNCONNECTED\(3), + CO(2) => \minusOp_carry__1_n_1\, + CO(1) => \minusOp_carry__1_n_2\, + CO(0) => \minusOp_carry__1_n_3\, + CYINIT => '0', + DI(3) => '0', + DI(2 downto 0) => det_hfp_start_int(10 downto 8), + O(3 downto 0) => minusOp1_out(11 downto 8), + S(3) => \minusOp_carry__1_i_1_n_0\, + S(2) => \minusOp_carry__1_i_2_n_0\, + S(1) => \minusOp_carry__1_i_3_n_0\, + S(0) => \minusOp_carry__1_i_4_n_0\ + ); +\minusOp_carry__1_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => det_hfp_start_int(11), + I1 => det_hactive_start_int(11), + O => \minusOp_carry__1_i_1_n_0\ + ); +\minusOp_carry__1_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => det_hfp_start_int(10), + I1 => det_hactive_start_int(10), + O => \minusOp_carry__1_i_2_n_0\ + ); +\minusOp_carry__1_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => det_hfp_start_int(9), + I1 => det_hactive_start_int(9), + O => \minusOp_carry__1_i_3_n_0\ + ); +\minusOp_carry__1_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => det_hfp_start_int(8), + I1 => det_hactive_start_int(8), + O => \minusOp_carry__1_i_4_n_0\ + ); +minusOp_carry_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => det_hfp_start_int(3), + I1 => det_hactive_start_int(3), + O => minusOp_carry_i_1_n_0 + ); +minusOp_carry_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => det_hfp_start_int(2), + I1 => det_hactive_start_int(2), + O => minusOp_carry_i_2_n_0 + ); +minusOp_carry_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => det_hfp_start_int(1), + I1 => det_hactive_start_int(1), + O => minusOp_carry_i_3_n_0 + ); +minusOp_carry_i_4: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => det_hfp_start_int(0), + I1 => det_hactive_start_int(0), + O => minusOp_carry_i_4_n_0 + ); +\minusOp_inferred__0/i__carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \minusOp_inferred__0/i__carry_n_0\, + CO(2) => \minusOp_inferred__0/i__carry_n_1\, + CO(1) => \minusOp_inferred__0/i__carry_n_2\, + CO(0) => \minusOp_inferred__0/i__carry_n_3\, + CYINIT => '1', + DI(3 downto 0) => \^q\(3 downto 0), + O(3 downto 0) => minusOp0_out(3 downto 0), + S(3) => \i__carry_i_1__12_n_0\, + S(2) => \i__carry_i_2__12_n_0\, + S(1) => \i__carry_i_3__12_n_0\, + S(0) => \i__carry_i_4__12_n_0\ + ); +\minusOp_inferred__0/i__carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \minusOp_inferred__0/i__carry_n_0\, + CO(3) => \minusOp_inferred__0/i__carry__0_n_0\, + CO(2) => \minusOp_inferred__0/i__carry__0_n_1\, + CO(1) => \minusOp_inferred__0/i__carry__0_n_2\, + CO(0) => \minusOp_inferred__0/i__carry__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => \^q\(7 downto 4), + O(3 downto 0) => minusOp0_out(7 downto 4), + S(3) => \i__carry__0_i_1__6_n_0\, + S(2) => \i__carry__0_i_2__6_n_0\, + S(1) => \i__carry__0_i_3__6_n_0\, + S(0) => \i__carry__0_i_4__6_n_0\ + ); +\minusOp_inferred__0/i__carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \minusOp_inferred__0/i__carry__0_n_0\, + CO(3) => \NLW_minusOp_inferred__0/i__carry__1_CO_UNCONNECTED\(3), + CO(2) => \minusOp_inferred__0/i__carry__1_n_1\, + CO(1) => \minusOp_inferred__0/i__carry__1_n_2\, + CO(0) => \minusOp_inferred__0/i__carry__1_n_3\, + CYINIT => '0', + DI(3) => '0', + DI(2 downto 0) => \^q\(10 downto 8), + O(3 downto 0) => minusOp0_out(11 downto 8), + S(3) => \i__carry__1_i_1_n_0\, + S(2) => \i__carry__1_i_2__2_n_0\, + S(1) => \i__carry__1_i_3__2_n_0\, + S(0) => \i__carry__1_i_4__2_n_0\ + ); +neqOp_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => neqOp2_out, + CO(2) => neqOp_carry_n_1, + CO(1) => neqOp_carry_n_2, + CO(0) => neqOp_carry_n_3, + CYINIT => '0', + DI(3 downto 0) => B"1111", + O(3 downto 0) => NLW_neqOp_carry_O_UNCONNECTED(3 downto 0), + S(3) => neqOp_carry_i_1_n_0, + S(2) => neqOp_carry_i_2_n_0, + S(1) => neqOp_carry_i_3_n_0, + S(0) => neqOp_carry_i_4_n_0 + ); +neqOp_carry_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => det_hbp_start_last(10), + I1 => det_hbp_start_int(10), + I2 => det_hbp_start_last(9), + I3 => det_hbp_start_int(9), + I4 => det_hbp_start_int(11), + I5 => det_hbp_start_last(11), + O => neqOp_carry_i_1_n_0 + ); +neqOp_carry_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => det_hbp_start_last(7), + I1 => det_hbp_start_int(7), + I2 => det_hbp_start_last(6), + I3 => det_hbp_start_int(6), + I4 => det_hbp_start_int(8), + I5 => det_hbp_start_last(8), + O => neqOp_carry_i_2_n_0 + ); +neqOp_carry_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => det_hbp_start_last(4), + I1 => det_hbp_start_int(4), + I2 => det_hbp_start_last(3), + I3 => det_hbp_start_int(3), + I4 => det_hbp_start_int(5), + I5 => det_hbp_start_last(5), + O => neqOp_carry_i_3_n_0 + ); +neqOp_carry_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => det_hbp_start_last(1), + I1 => det_hbp_start_int(1), + I2 => det_hbp_start_last(0), + I3 => det_hbp_start_int(0), + I4 => det_hbp_start_int(2), + I5 => det_hbp_start_last(2), + O => neqOp_carry_i_4_n_0 + ); +\neqOp_inferred__0/i__carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => neqOp3_out, + CO(2) => \neqOp_inferred__0/i__carry_n_1\, + CO(1) => \neqOp_inferred__0/i__carry_n_2\, + CO(0) => \neqOp_inferred__0/i__carry_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"1111", + O(3 downto 0) => \NLW_neqOp_inferred__0/i__carry_O_UNCONNECTED\(3 downto 0), + S(3) => \i__carry_i_1__5_n_0\, + S(2) => \i__carry_i_2__3_n_0\, + S(1) => \i__carry_i_3__3_n_0\, + S(0) => \i__carry_i_4__3_n_0\ + ); +\neqOp_inferred__1/i__carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \neqOp_inferred__1/i__carry_n_0\, + CO(2) => \neqOp_inferred__1/i__carry_n_1\, + CO(1) => \neqOp_inferred__1/i__carry_n_2\, + CO(0) => \neqOp_inferred__1/i__carry_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"1111", + O(3 downto 0) => \NLW_neqOp_inferred__1/i__carry_O_UNCONNECTED\(3 downto 0), + S(3) => \i__carry_i_1__6_n_0\, + S(2) => \i__carry_i_2__4_n_0\, + S(1) => \i__carry_i_3__4_n_0\, + S(0) => \i__carry_i_4__4_n_0\ + ); +\neqOp_inferred__2/i__carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => neqOp, + CO(2) => \neqOp_inferred__2/i__carry_n_1\, + CO(1) => \neqOp_inferred__2/i__carry_n_2\, + CO(0) => \neqOp_inferred__2/i__carry_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"1111", + O(3 downto 0) => \NLW_neqOp_inferred__2/i__carry_O_UNCONNECTED\(3 downto 0), + S(3) => \i__carry_i_1__7_n_0\, + S(2) => \i__carry_i_2__5_n_0\, + S(1) => \i__carry_i_3__5_n_0\, + S(0) => \i__carry_i_4__5_n_0\ + ); +\neqOp_inferred__3/i__carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \neqOp_inferred__3/i__carry_n_0\, + CO(2) => \neqOp_inferred__3/i__carry_n_1\, + CO(1) => \neqOp_inferred__3/i__carry_n_2\, + CO(0) => \neqOp_inferred__3/i__carry_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"1111", + O(3 downto 0) => \NLW_neqOp_inferred__3/i__carry_O_UNCONNECTED\(3 downto 0), + S(3) => \i__carry_i_1__8_n_0\, + S(2) => \i__carry_i_2__6_n_0\, + S(1) => \i__carry_i_3__6_n_0\, + S(0) => \i__carry_i_4__6_n_0\ + ); +\neqOp_inferred__4/i__carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => neqOp0_out, + CO(2) => \neqOp_inferred__4/i__carry_n_1\, + CO(1) => \neqOp_inferred__4/i__carry_n_2\, + CO(0) => \neqOp_inferred__4/i__carry_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"1111", + O(3 downto 0) => \NLW_neqOp_inferred__4/i__carry_O_UNCONNECTED\(3 downto 0), + S(3) => \i__carry_i_1__9_n_0\, + S(2) => \i__carry_i_2__7_n_0\, + S(1) => \i__carry_i_3__7_n_0\, + S(0) => \i__carry_i_4__7_n_0\ + ); +\neqOp_inferred__5/i__carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => neqOp1_out, + CO(2) => \neqOp_inferred__5/i__carry_n_1\, + CO(1) => \neqOp_inferred__5/i__carry_n_2\, + CO(0) => \neqOp_inferred__5/i__carry_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"1111", + O(3 downto 0) => \NLW_neqOp_inferred__5/i__carry_O_UNCONNECTED\(3 downto 0), + S(3) => \i__carry_i_1__10_n_0\, + S(2) => \i__carry_i_2__8_n_0\, + S(1) => \i__carry_i_3__8_n_0\, + S(0) => \i__carry_i_4__8_n_0\ + ); +\plusOp_inferred__2/i__carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \plusOp_inferred__2/i__carry_n_0\, + CO(2) => \plusOp_inferred__2/i__carry_n_1\, + CO(1) => \plusOp_inferred__2/i__carry_n_2\, + CO(0) => \plusOp_inferred__2/i__carry_n_3\, + CYINIT => '0', + DI(3 downto 0) => \^time_status_regs[6]\(3 downto 0), + O(3) => \plusOp_inferred__2/i__carry_n_4\, + O(2) => \plusOp_inferred__2/i__carry_n_5\, + O(1) => \plusOp_inferred__2/i__carry_n_6\, + O(0) => \plusOp_inferred__2/i__carry_n_7\, + S(3) => \i__carry_i_1__11_n_0\, + S(2) => \i__carry_i_2__9_n_0\, + S(1) => \i__carry_i_3__9_n_0\, + S(0) => \i__carry_i_4__9_n_0\ + ); +\plusOp_inferred__2/i__carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \plusOp_inferred__2/i__carry_n_0\, + CO(3) => \plusOp_inferred__2/i__carry__0_n_0\, + CO(2) => \plusOp_inferred__2/i__carry__0_n_1\, + CO(1) => \plusOp_inferred__2/i__carry__0_n_2\, + CO(0) => \plusOp_inferred__2/i__carry__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => \^time_status_regs[6]\(7 downto 4), + O(3) => \plusOp_inferred__2/i__carry__0_n_4\, + O(2) => \plusOp_inferred__2/i__carry__0_n_5\, + O(1) => \plusOp_inferred__2/i__carry__0_n_6\, + O(0) => \plusOp_inferred__2/i__carry__0_n_7\, + S(3) => \i__carry__0_i_1__3_n_0\, + S(2) => \i__carry__0_i_2__3_n_0\, + S(1) => \i__carry__0_i_3__3_n_0\, + S(0) => \i__carry__0_i_4__3_n_0\ + ); +\plusOp_inferred__2/i__carry__1\: unisim.vcomponents.CARRY4 + port map ( + CI => \plusOp_inferred__2/i__carry__0_n_0\, + CO(3) => \NLW_plusOp_inferred__2/i__carry__1_CO_UNCONNECTED\(3), + CO(2) => \plusOp_inferred__2/i__carry__1_n_1\, + CO(1) => \plusOp_inferred__2/i__carry__1_n_2\, + CO(0) => \plusOp_inferred__2/i__carry__1_n_3\, + CYINIT => '0', + DI(3) => '0', + DI(2 downto 0) => \^time_status_regs[6]\(10 downto 8), + O(3) => \plusOp_inferred__2/i__carry__1_n_4\, + O(2) => \plusOp_inferred__2/i__carry__1_n_5\, + O(1) => \plusOp_inferred__2/i__carry__1_n_6\, + O(0) => \plusOp_inferred__2/i__carry__1_n_7\, + S(3) => \i__carry__1_i_1__0_n_0\, + S(2) => \i__carry__1_i_2_n_0\, + S(1) => \i__carry__1_i_3_n_0\, + S(0) => \i__carry__1_i_4_n_0\ + ); +top_of_frame_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"2A3A2A2AFFFFFFFF" + ) + port map ( + I0 => top_of_frame_reg_n_0, + I1 => top_of_frame141_out, + I2 => \^det_ce\, + I3 => \DET_VSYNC.vsync_d2_reg_n_0\, + I4 => \DET_VSYNC.vsync_d_reg_n_0\, + I5 => resetn_out, + O => top_of_frame_i_1_n_0 + ); +top_of_frame_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => active_video_d, + I1 => active_video_d2, + O => top_of_frame141_out + ); +top_of_frame_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => clk, + CE => '1', + D => top_of_frame_i_1_n_0, + Q => top_of_frame_reg_n_0, + R => '0' + ); +\v_count[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \v_count_reg__0\(0), + O => \plusOp__0\(0) + ); +\v_count[10]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFF8A80000" + ) + port map ( + I0 => \h_count0__0\, + I1 => found_eof_reg_n_0, + I2 => p_0_in16_in, + I3 => leqOp_1, + I4 => \^det_ce\, + I5 => h_count1, + O => \v_count[10]_i_1_n_0\ + ); +\v_count[10]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFFFFFF80000000" + ) + port map ( + I0 => \v_count_reg__0\(8), + I1 => \v_count_reg__0\(6), + I2 => \v_count[10]_i_5_n_0\, + I3 => \v_count_reg__0\(7), + I4 => \v_count_reg__0\(9), + I5 => \v_count_reg__0\(10), + O => \plusOp__0\(10) + ); +\v_count[10]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"09" + ) + port map ( + I0 => \^time_status_regs[3]\(1), + I1 => hsync_in, + I2 => line_end_d_reg_n_0, + O => \h_count0__0\ + ); +\v_count[10]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4004" + ) + port map ( + I0 => frame_end_d, + I1 => top_of_frame_reg_n_0, + I2 => \^time_status_regs[3]\(2), + I3 => active_video_in, + O => p_0_in16_in + ); +\v_count[10]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => \v_count_reg__0\(5), + I1 => \v_count_reg__0\(3), + I2 => \v_count_reg__0\(1), + I3 => \v_count_reg__0\(0), + I4 => \v_count_reg__0\(2), + I5 => \v_count_reg__0\(4), + O => \v_count[10]_i_5_n_0\ + ); +\v_count[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \v_count_reg__0\(0), + I1 => \v_count_reg__0\(1), + O => \plusOp__0\(1) + ); +\v_count[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \v_count_reg__0\(0), + I1 => \v_count_reg__0\(1), + I2 => \v_count_reg__0\(2), + O => \plusOp__0\(2) + ); +\v_count[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \v_count_reg__0\(1), + I1 => \v_count_reg__0\(0), + I2 => \v_count_reg__0\(2), + I3 => \v_count_reg__0\(3), + O => \plusOp__0\(3) + ); +\v_count[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \v_count_reg__0\(2), + I1 => \v_count_reg__0\(0), + I2 => \v_count_reg__0\(1), + I3 => \v_count_reg__0\(3), + I4 => \v_count_reg__0\(4), + O => \plusOp__0\(4) + ); +\v_count[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFFFFFF80000000" + ) + port map ( + I0 => \v_count_reg__0\(3), + I1 => \v_count_reg__0\(1), + I2 => \v_count_reg__0\(0), + I3 => \v_count_reg__0\(2), + I4 => \v_count_reg__0\(4), + I5 => \v_count_reg__0\(5), + O => \plusOp__0\(5) + ); +\v_count[6]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \v_count[10]_i_5_n_0\, + I1 => \v_count_reg__0\(6), + O => \plusOp__0\(6) + ); +\v_count[7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \v_count[10]_i_5_n_0\, + I1 => \v_count_reg__0\(6), + I2 => \v_count_reg__0\(7), + O => \plusOp__0\(7) + ); +\v_count[8]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \v_count_reg__0\(6), + I1 => \v_count[10]_i_5_n_0\, + I2 => \v_count_reg__0\(7), + I3 => \v_count_reg__0\(8), + O => \plusOp__0\(8) + ); +\v_count[9]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \v_count_reg__0\(7), + I1 => \v_count[10]_i_5_n_0\, + I2 => \v_count_reg__0\(6), + I3 => \v_count_reg__0\(8), + I4 => \v_count_reg__0\(9), + O => \plusOp__0\(9) + ); +\v_count_last_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => \v_count_reg__0\(0), + Q => v_count_last(0), + R => h_count1 + ); +\v_count_last_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => \v_count_reg__0\(10), + Q => v_count_last(10), + R => h_count1 + ); +\v_count_last_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => \v_count_reg__0\(1), + Q => v_count_last(1), + R => h_count1 + ); +\v_count_last_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => \v_count_reg__0\(2), + Q => v_count_last(2), + R => h_count1 + ); +\v_count_last_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => \v_count_reg__0\(3), + Q => v_count_last(3), + R => h_count1 + ); +\v_count_last_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => \v_count_reg__0\(4), + Q => v_count_last(4), + R => h_count1 + ); +\v_count_last_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => \v_count_reg__0\(5), + Q => v_count_last(5), + R => h_count1 + ); +\v_count_last_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => \v_count_reg__0\(6), + Q => v_count_last(6), + R => h_count1 + ); +\v_count_last_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => \v_count_reg__0\(7), + Q => v_count_last(7), + R => h_count1 + ); +\v_count_last_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => \v_count_reg__0\(8), + Q => v_count_last(8), + R => h_count1 + ); +\v_count_last_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => \v_count_reg__0\(9), + Q => v_count_last(9), + R => h_count1 + ); +\v_count_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => \plusOp__0\(0), + Q => \v_count_reg__0\(0), + R => \v_count[10]_i_1_n_0\ + ); +\v_count_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => \plusOp__0\(10), + Q => \v_count_reg__0\(10), + R => \v_count[10]_i_1_n_0\ + ); +\v_count_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => \plusOp__0\(1), + Q => \v_count_reg__0\(1), + R => \v_count[10]_i_1_n_0\ + ); +\v_count_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => \plusOp__0\(2), + Q => \v_count_reg__0\(2), + R => \v_count[10]_i_1_n_0\ + ); +\v_count_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => \plusOp__0\(3), + Q => \v_count_reg__0\(3), + R => \v_count[10]_i_1_n_0\ + ); +\v_count_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => \plusOp__0\(4), + Q => \v_count_reg__0\(4), + R => \v_count[10]_i_1_n_0\ + ); +\v_count_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => \plusOp__0\(5), + Q => \v_count_reg__0\(5), + R => \v_count[10]_i_1_n_0\ + ); +\v_count_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => \plusOp__0\(6), + Q => \v_count_reg__0\(6), + R => \v_count[10]_i_1_n_0\ + ); +\v_count_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => \plusOp__0\(7), + Q => \v_count_reg__0\(7), + R => \v_count[10]_i_1_n_0\ + ); +\v_count_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => \plusOp__0\(8), + Q => \v_count_reg__0\(8), + R => \v_count[10]_i_1_n_0\ + ); +\v_count_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => \det_htotal_int[11]_i_1_n_0\, + D => \plusOp__0\(9), + Q => \v_count_reg__0\(9), + R => \v_count[10]_i_1_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_tc_1_0_video_clock_cross is + port ( + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][31]\ : out STD_LOGIC; + out_data : out STD_LOGIC_VECTOR ( 32 downto 0 ); + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][30]\ : out STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][29]\ : out STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][28]\ : out STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][27]\ : out STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][26]\ : out STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][25]\ : out STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][24]\ : out STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][23]\ : out STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][22]\ : out STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][21]\ : out STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][20]\ : out STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][19]\ : out STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][18]\ : out STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][17]\ : out STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][16]\ : out STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][13]\ : out STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][12]\ : out STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][11]\ : out STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][10]\ : out STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][9]\ : out STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][8]\ : out STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][21]\ : out STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][20]\ : out STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][19]\ : out STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][18]\ : out STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][17]\ : out STD_LOGIC; + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][16]\ : out STD_LOGIC; + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + p_533_out : out STD_LOGIC; + p_535_out : out STD_LOGIC; + p_456_out : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + ipif_Addr : out STD_LOGIC_VECTOR ( 8 downto 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0\ : out STD_LOGIC; + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][8]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][7]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][31]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[33].GEN_MUX_REG.data_out_reg_reg[33][26]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][0]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][1]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][2]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][3]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][4]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][5]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][6]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][7]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][8]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][9]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][10]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][11]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][12]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][13]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][14]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][15]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][16]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][17]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][18]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][19]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][20]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][21]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][22]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][23]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][24]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][25]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][26]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][27]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][28]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][29]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][30]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][31]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][0]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][1]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][2]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][3]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][4]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][5]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][6]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][7]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][8]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][9]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][10]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][11]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][12]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][13]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][14]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][15]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][16]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][17]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][18]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][19]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][20]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][21]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][22]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][23]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][24]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][25]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][26]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][27]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][28]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][29]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][30]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][31]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][0]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][1]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][2]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][3]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][4]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][5]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][6]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][7]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][8]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][9]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][10]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][11]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][12]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][13]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][14]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][15]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][16]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][17]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][18]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][19]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][20]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][21]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][22]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][23]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][24]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][25]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][26]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][27]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][28]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][29]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][30]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][31]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][0]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][1]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][2]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][3]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][4]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][5]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][6]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][7]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][8]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][9]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][10]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][11]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][12]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][13]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][14]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][15]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][16]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][17]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][18]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][19]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][20]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][21]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][22]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][23]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][24]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][25]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][26]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][27]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][28]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][29]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][30]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][31]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][0]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][1]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][2]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][3]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][4]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][5]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][6]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][7]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][8]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][9]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][10]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][11]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][12]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][13]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][14]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][15]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][16]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][17]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][18]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][19]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][20]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][21]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][22]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][23]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][24]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][25]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][26]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][27]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][28]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][29]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][30]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][31]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][0]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][1]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][2]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][3]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][4]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][5]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][6]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][7]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][8]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][9]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][10]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][11]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][12]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][13]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][14]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][15]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][16]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][17]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][18]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][19]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][20]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][21]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][22]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][23]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][24]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][25]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][26]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][27]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][28]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][29]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][30]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][31]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][0]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][1]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][2]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][3]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][4]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][5]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][6]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][7]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][8]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][9]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][10]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][11]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][12]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][13]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][14]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][15]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][16]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][17]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][18]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][19]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][20]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][21]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][22]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][23]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][24]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][25]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][26]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][27]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][28]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][29]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][30]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][31]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][0]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][1]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][2]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][3]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][4]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][5]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][6]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][7]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][8]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][9]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][10]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][11]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][12]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][13]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][14]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][15]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][16]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][17]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][18]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][19]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][20]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][21]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][22]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][23]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][24]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][25]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][26]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][27]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][28]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][29]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][30]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][31]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][0]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][1]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][2]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][3]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][4]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][5]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][6]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][7]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][8]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][9]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][10]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][11]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][12]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][13]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][14]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][15]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][16]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][17]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][18]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][19]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][20]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][21]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][22]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][23]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][24]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][25]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][26]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][27]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][28]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][29]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][30]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][31]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][0]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][1]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][2]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][3]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][4]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][5]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][6]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][7]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][8]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][9]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][10]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][11]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][12]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][13]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][14]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][15]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][16]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][17]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][18]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][19]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][20]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][21]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][22]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][23]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][24]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][25]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][26]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][27]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][28]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][29]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][30]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][31]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][0]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][1]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][2]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][3]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][4]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][5]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][6]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][7]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][8]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][9]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][10]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][11]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][12]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][13]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][14]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][15]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][16]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][17]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][18]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][19]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][20]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][21]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][22]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][23]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][24]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][25]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][26]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][27]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][28]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][29]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][30]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][31]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][0]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][1]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][2]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][3]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][4]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][5]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][6]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][7]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][8]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][9]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][11]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][12]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][13]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][14]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][15]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][16]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][17]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][18]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][19]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][20]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][21]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][22]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][23]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][24]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][25]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][26]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][27]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][28]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][29]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][30]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][31]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][0]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][1]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][2]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][3]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][4]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][5]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][6]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][7]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][8]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][9]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][10]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][11]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][12]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][13]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][14]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][15]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][16]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][17]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][18]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][19]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][20]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][21]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][22]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][23]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][24]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][25]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][26]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][27]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][28]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][29]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][30]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][31]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][0]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][1]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][2]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][3]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][4]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][5]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][6]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][7]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][8]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][9]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][10]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][12]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][13]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][14]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][15]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][16]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][17]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][18]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][19]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][20]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][21]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][22]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][23]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][24]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][25]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][26]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][27]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][28]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][29]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][30]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31]_0\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][0]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][1]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][2]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][3]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][4]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][5]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][6]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][7]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][8]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][9]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][10]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][11]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][12]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][13]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][14]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][15]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][16]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][17]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][18]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][19]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][20]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][21]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][22]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][23]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][24]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][25]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][26]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][27]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][28]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][29]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][30]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][31]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][0]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][1]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][2]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][3]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][4]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][5]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][6]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][7]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][8]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][9]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][10]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][11]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][12]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][13]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][14]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][15]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][16]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][17]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][18]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][19]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][20]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][21]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][22]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][23]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][24]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][25]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][26]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][27]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][28]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][29]\ : out STD_LOGIC; + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][30]\ : out STD_LOGIC; + \AXI4_LITE_INTERFACE.soft_resetn_reg\ : in STD_LOGIC; + vid_aclk_en : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 21 downto 0 ); + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][21]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); + genr_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); + core_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); + vid_aresetn : in STD_LOGIC; + \genr_control_regs[0]\ : in STD_LOGIC_VECTOR ( 24 downto 0 ); + reg_update : in STD_LOGIC; + write_ack_int : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 25 downto 0 ); + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\ : in STD_LOGIC_VECTOR ( 25 downto 0 ); + \time_status_regs[27]\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); + \time_status_regs[26]\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\ : in STD_LOGIC_VECTOR ( 25 downto 0 ); + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\ : in STD_LOGIC_VECTOR ( 25 downto 0 ); + \time_status_regs[25]\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); + \time_status_regs[24]\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\ : in STD_LOGIC_VECTOR ( 25 downto 0 ); + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\ : in STD_LOGIC_VECTOR ( 25 downto 0 ); + \time_status_regs[23]\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); + \time_status_regs[22]\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\ : in STD_LOGIC_VECTOR ( 25 downto 0 ); + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\ : in STD_LOGIC_VECTOR ( 25 downto 0 ); + \time_status_regs[21]\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); + \time_status_regs[20]\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \time_status_regs[18]\ : in STD_LOGIC_VECTOR ( 23 downto 0 ); + \time_status_regs[19]\ : in STD_LOGIC_VECTOR ( 24 downto 0 ); + \time_status_regs[17]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\ : in STD_LOGIC_VECTOR ( 25 downto 0 ); + \time_status_regs[16]\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); + \time_status_regs[15]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[14]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[13]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[12]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[11]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[10]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[9]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[8]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[7]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[6]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[5]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[4]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[3]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[2]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[1]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[0]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \genr_status_regs[3]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); + intr_err : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \genr_control_regs[3]\ : in STD_LOGIC_VECTOR ( 21 downto 0 ); + \genr_status_regs_int_reg[1]\ : in STD_LOGIC_VECTOR ( 30 downto 0 ); + \genr_status_regs[0]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); + \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\ : in STD_LOGIC_VECTOR ( 44 downto 0 ); + vid_aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_tc_1_0_video_clock_cross : entity is "video_clock_cross"; +end Arty_Z7_20_v_tc_1_0_video_clock_cross; + +architecture STRUCTURE of Arty_Z7_20_v_tc_1_0_video_clock_cross is + signal \AXI4_LITE_INTERFACE.core_control_regs_int[13][26]_i_2_n_0\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.core_control_regs_int[16][26]_i_2_n_0\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.core_control_regs_int[9][26]_i_2_n_0\ : STD_LOGIC; + signal \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2_n_0\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.genr_control_regs_int[2][21]_i_2_n_0\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.time_control_regs_int[18][6]_i_2_n_0\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.time_control_regs_int[28][28]_i_2_n_0\ : STD_LOGIC; + signal \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\ : STD_LOGIC; + signal \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\ : STD_LOGIC; + signal \data_sync[0]_0\ : STD_LOGIC_VECTOR ( 44 downto 0 ); + attribute async_reg : string; + attribute async_reg of \data_sync[0]_0\ : signal is "true"; + attribute shift_extract : string; + attribute shift_extract of \data_sync[0]_0\ : signal is "NO"; + attribute shreg_extract : string; + attribute shreg_extract of \data_sync[0]_0\ : signal is "no"; + signal \data_sync[1]_1\ : STD_LOGIC_VECTOR ( 44 downto 0 ); + attribute async_reg of \data_sync[1]_1\ : signal is "true"; + attribute shift_extract of \data_sync[1]_1\ : signal is "NO"; + attribute shreg_extract of \data_sync[1]_1\ : signal is "no"; + signal \data_sync[2]_2\ : STD_LOGIC_VECTOR ( 44 downto 0 ); + attribute async_reg of \data_sync[2]_2\ : signal is "true"; + attribute shift_extract of \data_sync[2]_2\ : signal is "NO"; + attribute shreg_extract of \data_sync[2]_2\ : signal is "no"; + signal \^ipif_addr\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \AXI4_LITE_INTERFACE.core_control_regs_int[12][26]_i_1\ : label is "soft_lutpair9"; + attribute SOFT_HLUTNM of \AXI4_LITE_INTERFACE.core_control_regs_int[13][26]_i_2\ : label is "soft_lutpair11"; + attribute SOFT_HLUTNM of \AXI4_LITE_INTERFACE.core_control_regs_int[16][26]_i_1\ : label is "soft_lutpair10"; + attribute SOFT_HLUTNM of \AXI4_LITE_INTERFACE.core_control_regs_int[4][26]_i_1\ : label is "soft_lutpair10"; + attribute SOFT_HLUTNM of \AXI4_LITE_INTERFACE.core_control_regs_int[8][26]_i_1\ : label is "soft_lutpair9"; + attribute SOFT_HLUTNM of \AXI4_LITE_INTERFACE.core_control_regs_int[9][26]_i_2\ : label is "soft_lutpair12"; + attribute SOFT_HLUTNM of \AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2\ : label is "soft_lutpair11"; + attribute IS_FANOUT_CONSTRAINED : integer; + attribute IS_FANOUT_CONSTRAINED of \AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_3\ : label is 1; + attribute SOFT_HLUTNM of \AXI4_LITE_INTERFACE.time_control_regs_int[16][28]_i_1\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \AXI4_LITE_INTERFACE.time_control_regs_int[18][6]_i_1\ : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of \AXI4_LITE_INTERFACE.time_control_regs_int[20][28]_i_1\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \AXI4_LITE_INTERFACE.time_control_regs_int[21][28]_i_1\ : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of \AXI4_LITE_INTERFACE.time_control_regs_int[22][28]_i_1\ : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of \AXI4_LITE_INTERFACE.time_control_regs_int[23][28]_i_1\ : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of \AXI4_LITE_INTERFACE.time_control_regs_int[28][28]_i_2\ : label is "soft_lutpair12"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][0]_i_1\ : label is "soft_lutpair253"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][10]_i_1\ : label is "soft_lutpair259"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][11]_i_1\ : label is "soft_lutpair260"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][12]_i_1\ : label is "soft_lutpair260"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][13]_i_1\ : label is "soft_lutpair261"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][14]_i_1\ : label is "soft_lutpair261"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][15]_i_1\ : label is "soft_lutpair254"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][16]_i_1\ : label is "soft_lutpair262"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][17]_i_1\ : label is "soft_lutpair263"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][18]_i_1\ : label is "soft_lutpair263"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][19]_i_1\ : label is "soft_lutpair264"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][1]_i_1\ : label is "soft_lutpair254"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][20]_i_1\ : label is "soft_lutpair264"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][21]_i_1\ : label is "soft_lutpair265"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][22]_i_1\ : label is "soft_lutpair265"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][23]_i_1\ : label is "soft_lutpair266"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][24]_i_1\ : label is "soft_lutpair266"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][25]_i_1\ : label is "soft_lutpair267"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][26]_i_1\ : label is "soft_lutpair267"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][27]_i_1\ : label is "soft_lutpair268"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][28]_i_1\ : label is "soft_lutpair268"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][29]_i_1\ : label is "soft_lutpair262"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][2]_i_1\ : label is "soft_lutpair255"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][30]_i_1\ : label is "soft_lutpair255"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][3]_i_1\ : label is "soft_lutpair256"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][4]_i_1\ : label is "soft_lutpair256"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][5]_i_1\ : label is "soft_lutpair257"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][6]_i_1\ : label is "soft_lutpair257"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][7]_i_1\ : label is "soft_lutpair258"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][8]_i_1\ : label is "soft_lutpair258"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][9]_i_1\ : label is "soft_lutpair259"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][0]_i_1\ : label is "soft_lutpair207"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][10]_i_1\ : label is "soft_lutpair243"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][11]_i_1\ : label is "soft_lutpair244"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][12]_i_1\ : label is "soft_lutpair244"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][13]_i_1\ : label is "soft_lutpair245"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][14]_i_1\ : label is "soft_lutpair245"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][15]_i_1\ : label is "soft_lutpair246"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][16]_i_1\ : label is "soft_lutpair246"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][17]_i_1\ : label is "soft_lutpair247"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][18]_i_1\ : label is "soft_lutpair247"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][19]_i_1\ : label is "soft_lutpair248"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][1]_i_1\ : label is "soft_lutpair238"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][20]_i_1\ : label is "soft_lutpair248"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][21]_i_1\ : label is "soft_lutpair249"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][22]_i_1\ : label is "soft_lutpair249"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][23]_i_1\ : label is "soft_lutpair250"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][24]_i_1\ : label is "soft_lutpair250"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][25]_i_1\ : label is "soft_lutpair251"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][26]_i_1\ : label is "soft_lutpair251"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][27]_i_1\ : label is "soft_lutpair252"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][28]_i_1\ : label is "soft_lutpair252"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][29]_i_1\ : label is "soft_lutpair253"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][2]_i_1\ : label is "soft_lutpair239"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][30]_i_1\ : label is "soft_lutpair238"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][31]_i_1\ : label is "soft_lutpair239"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][3]_i_1\ : label is "soft_lutpair240"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][4]_i_1\ : label is "soft_lutpair240"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][5]_i_1\ : label is "soft_lutpair241"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][6]_i_1\ : label is "soft_lutpair241"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][7]_i_1\ : label is "soft_lutpair242"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][8]_i_1\ : label is "soft_lutpair242"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][9]_i_1\ : label is "soft_lutpair243"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[33].GEN_MUX_REG.data_out_reg[33][26]_i_1\ : label is "soft_lutpair15"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][0]_i_1\ : label is "soft_lutpair223"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][10]_i_1\ : label is "soft_lutpair228"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][11]_i_1\ : label is "soft_lutpair228"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][12]_i_1\ : label is "soft_lutpair229"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][13]_i_1\ : label is "soft_lutpair229"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][14]_i_1\ : label is "soft_lutpair230"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][15]_i_1\ : label is "soft_lutpair230"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][16]_i_1\ : label is "soft_lutpair231"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][17]_i_1\ : label is "soft_lutpair231"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][18]_i_1\ : label is "soft_lutpair232"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][19]_i_1\ : label is "soft_lutpair232"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][1]_i_1\ : label is "soft_lutpair223"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][20]_i_1\ : label is "soft_lutpair233"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][21]_i_1\ : label is "soft_lutpair233"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][22]_i_1\ : label is "soft_lutpair234"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][23]_i_1\ : label is "soft_lutpair234"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][24]_i_1\ : label is "soft_lutpair235"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][25]_i_1\ : label is "soft_lutpair235"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][26]_i_1\ : label is "soft_lutpair236"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][27]_i_1\ : label is "soft_lutpair236"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][28]_i_1\ : label is "soft_lutpair237"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][29]_i_1\ : label is "soft_lutpair206"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][2]_i_1\ : label is "soft_lutpair224"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][30]_i_1\ : label is "soft_lutpair237"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][31]_i_1\ : label is "soft_lutpair207"; + attribute IS_FANOUT_CONSTRAINED of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][31]_i_2\ : label is 1; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][3]_i_1\ : label is "soft_lutpair224"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][4]_i_1\ : label is "soft_lutpair225"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][5]_i_1\ : label is "soft_lutpair225"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][6]_i_1\ : label is "soft_lutpair226"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][7]_i_1\ : label is "soft_lutpair226"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][8]_i_1\ : label is "soft_lutpair227"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][9]_i_1\ : label is "soft_lutpair227"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][0]_i_1\ : label is "soft_lutpair204"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][10]_i_1\ : label is "soft_lutpair212"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][11]_i_1\ : label is "soft_lutpair212"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][12]_i_1\ : label is "soft_lutpair213"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][13]_i_1\ : label is "soft_lutpair213"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][14]_i_1\ : label is "soft_lutpair214"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][15]_i_1\ : label is "soft_lutpair214"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][16]_i_1\ : label is "soft_lutpair215"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][17]_i_1\ : label is "soft_lutpair215"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][18]_i_1\ : label is "soft_lutpair216"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][19]_i_1\ : label is "soft_lutpair216"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][1]_i_1\ : label is "soft_lutpair206"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][20]_i_1\ : label is "soft_lutpair217"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][21]_i_1\ : label is "soft_lutpair217"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][22]_i_1\ : label is "soft_lutpair218"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][23]_i_1\ : label is "soft_lutpair218"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][24]_i_1\ : label is "soft_lutpair219"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][25]_i_1\ : label is "soft_lutpair219"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][26]_i_1\ : label is "soft_lutpair220"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][27]_i_1\ : label is "soft_lutpair220"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][28]_i_1\ : label is "soft_lutpair221"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][29]_i_1\ : label is "soft_lutpair221"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][2]_i_1\ : label is "soft_lutpair208"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][30]_i_1\ : label is "soft_lutpair222"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][31]_i_1\ : label is "soft_lutpair222"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][3]_i_1\ : label is "soft_lutpair208"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][4]_i_1\ : label is "soft_lutpair209"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][5]_i_1\ : label is "soft_lutpair209"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][6]_i_1\ : label is "soft_lutpair210"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][7]_i_1\ : label is "soft_lutpair210"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][8]_i_1\ : label is "soft_lutpair211"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][9]_i_1\ : label is "soft_lutpair211"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][0]_i_1\ : label is "soft_lutpair190"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][10]_i_1\ : label is "soft_lutpair195"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][11]_i_1\ : label is "soft_lutpair196"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][12]_i_1\ : label is "soft_lutpair196"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][13]_i_1\ : label is "soft_lutpair197"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][14]_i_1\ : label is "soft_lutpair197"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][15]_i_1\ : label is "soft_lutpair198"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][16]_i_1\ : label is "soft_lutpair198"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][17]_i_1\ : label is "soft_lutpair199"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][18]_i_1\ : label is "soft_lutpair199"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][19]_i_1\ : label is "soft_lutpair200"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][1]_i_1\ : label is "soft_lutpair191"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][20]_i_1\ : label is "soft_lutpair200"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][21]_i_1\ : label is "soft_lutpair201"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][22]_i_1\ : label is "soft_lutpair201"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][23]_i_1\ : label is "soft_lutpair202"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][24]_i_1\ : label is "soft_lutpair202"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][25]_i_1\ : label is "soft_lutpair203"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][26]_i_1\ : label is "soft_lutpair203"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][27]_i_1\ : label is "soft_lutpair142"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][28]_i_1\ : label is "soft_lutpair204"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][29]_i_1\ : label is "soft_lutpair205"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][2]_i_1\ : label is "soft_lutpair191"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][30]_i_1\ : label is "soft_lutpair205"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][31]_i_1\ : label is "soft_lutpair143"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][3]_i_1\ : label is "soft_lutpair192"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][4]_i_1\ : label is "soft_lutpair192"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][5]_i_1\ : label is "soft_lutpair193"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][6]_i_1\ : label is "soft_lutpair193"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][7]_i_1\ : label is "soft_lutpair194"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][8]_i_1\ : label is "soft_lutpair194"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][9]_i_1\ : label is "soft_lutpair195"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][0]_i_1\ : label is "soft_lutpair175"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][10]_i_1\ : label is "soft_lutpair180"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][11]_i_1\ : label is "soft_lutpair181"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][12]_i_1\ : label is "soft_lutpair181"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][13]_i_1\ : label is "soft_lutpair182"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][14]_i_1\ : label is "soft_lutpair182"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][15]_i_1\ : label is "soft_lutpair142"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][16]_i_1\ : label is "soft_lutpair143"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][17]_i_1\ : label is "soft_lutpair183"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][18]_i_1\ : label is "soft_lutpair183"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][19]_i_1\ : label is "soft_lutpair184"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][1]_i_1\ : label is "soft_lutpair176"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][20]_i_1\ : label is "soft_lutpair184"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][21]_i_1\ : label is "soft_lutpair185"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][22]_i_1\ : label is "soft_lutpair185"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][23]_i_1\ : label is "soft_lutpair186"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][24]_i_1\ : label is "soft_lutpair186"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][25]_i_1\ : label is "soft_lutpair187"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][26]_i_1\ : label is "soft_lutpair187"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][27]_i_1\ : label is "soft_lutpair188"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][28]_i_1\ : label is "soft_lutpair188"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][29]_i_1\ : label is "soft_lutpair189"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][2]_i_1\ : label is "soft_lutpair176"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][30]_i_1\ : label is "soft_lutpair189"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_1\ : label is "soft_lutpair190"; + attribute IS_FANOUT_CONSTRAINED of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2\ : label is 1; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][3]_i_1\ : label is "soft_lutpair177"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][4]_i_1\ : label is "soft_lutpair177"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][5]_i_1\ : label is "soft_lutpair178"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][6]_i_1\ : label is "soft_lutpair178"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][7]_i_1\ : label is "soft_lutpair179"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][8]_i_1\ : label is "soft_lutpair179"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][9]_i_1\ : label is "soft_lutpair180"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][0]_i_1\ : label is "soft_lutpair159"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][10]_i_1\ : label is "soft_lutpair164"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][11]_i_1\ : label is "soft_lutpair165"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][12]_i_1\ : label is "soft_lutpair165"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][13]_i_1\ : label is "soft_lutpair166"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][14]_i_1\ : label is "soft_lutpair166"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][15]_i_1\ : label is "soft_lutpair167"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][16]_i_1\ : label is "soft_lutpair167"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][17]_i_1\ : label is "soft_lutpair168"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][18]_i_1\ : label is "soft_lutpair168"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][19]_i_1\ : label is "soft_lutpair169"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][1]_i_1\ : label is "soft_lutpair160"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][20]_i_1\ : label is "soft_lutpair169"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][21]_i_1\ : label is "soft_lutpair170"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][22]_i_1\ : label is "soft_lutpair170"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][23]_i_1\ : label is "soft_lutpair171"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][24]_i_1\ : label is "soft_lutpair171"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][25]_i_1\ : label is "soft_lutpair172"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][26]_i_1\ : label is "soft_lutpair172"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][27]_i_1\ : label is "soft_lutpair173"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][28]_i_1\ : label is "soft_lutpair173"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][29]_i_1\ : label is "soft_lutpair174"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][2]_i_1\ : label is "soft_lutpair160"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][30]_i_1\ : label is "soft_lutpair174"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][31]_i_1\ : label is "soft_lutpair175"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][3]_i_1\ : label is "soft_lutpair161"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][4]_i_1\ : label is "soft_lutpair161"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][5]_i_1\ : label is "soft_lutpair162"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][6]_i_1\ : label is "soft_lutpair162"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][7]_i_1\ : label is "soft_lutpair163"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][8]_i_1\ : label is "soft_lutpair163"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][9]_i_1\ : label is "soft_lutpair164"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][0]_i_1\ : label is "soft_lutpair138"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][10]_i_1\ : label is "soft_lutpair148"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][11]_i_1\ : label is "soft_lutpair149"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][12]_i_1\ : label is "soft_lutpair149"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][13]_i_1\ : label is "soft_lutpair150"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][14]_i_1\ : label is "soft_lutpair150"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][15]_i_1\ : label is "soft_lutpair151"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][16]_i_1\ : label is "soft_lutpair151"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][17]_i_1\ : label is "soft_lutpair152"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][18]_i_1\ : label is "soft_lutpair152"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][19]_i_1\ : label is "soft_lutpair153"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][1]_i_1\ : label is "soft_lutpair144"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][20]_i_1\ : label is "soft_lutpair153"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][21]_i_1\ : label is "soft_lutpair154"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][22]_i_1\ : label is "soft_lutpair154"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][23]_i_1\ : label is "soft_lutpair155"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][24]_i_1\ : label is "soft_lutpair155"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][25]_i_1\ : label is "soft_lutpair156"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][26]_i_1\ : label is "soft_lutpair156"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][27]_i_1\ : label is "soft_lutpair157"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][28]_i_1\ : label is "soft_lutpair157"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][29]_i_1\ : label is "soft_lutpair158"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][2]_i_1\ : label is "soft_lutpair144"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][30]_i_1\ : label is "soft_lutpair158"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][31]_i_1\ : label is "soft_lutpair159"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][3]_i_1\ : label is "soft_lutpair145"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][4]_i_1\ : label is "soft_lutpair145"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][5]_i_1\ : label is "soft_lutpair146"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][6]_i_1\ : label is "soft_lutpair146"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][7]_i_1\ : label is "soft_lutpair147"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][8]_i_1\ : label is "soft_lutpair147"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][9]_i_1\ : label is "soft_lutpair148"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][0]_i_1\ : label is "soft_lutpair14"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][10]_i_1\ : label is "soft_lutpair131"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][11]_i_1\ : label is "soft_lutpair132"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][12]_i_1\ : label is "soft_lutpair132"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][13]_i_1\ : label is "soft_lutpair133"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][14]_i_1\ : label is "soft_lutpair133"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][15]_i_1\ : label is "soft_lutpair134"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][16]_i_1\ : label is "soft_lutpair134"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][17]_i_1\ : label is "soft_lutpair135"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][18]_i_1\ : label is "soft_lutpair135"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][19]_i_1\ : label is "soft_lutpair136"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][1]_i_1\ : label is "soft_lutpair127"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][20]_i_1\ : label is "soft_lutpair136"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][21]_i_1\ : label is "soft_lutpair137"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][22]_i_1\ : label is "soft_lutpair137"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][23]_i_1\ : label is "soft_lutpair13"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][24]_i_1\ : label is "soft_lutpair138"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][25]_i_1\ : label is "soft_lutpair139"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][26]_i_1\ : label is "soft_lutpair139"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][27]_i_1\ : label is "soft_lutpair140"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][28]_i_1\ : label is "soft_lutpair140"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][29]_i_1\ : label is "soft_lutpair141"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][2]_i_1\ : label is "soft_lutpair127"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][30]_i_1\ : label is "soft_lutpair141"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][31]_i_1\ : label is "soft_lutpair14"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][3]_i_1\ : label is "soft_lutpair128"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][4]_i_1\ : label is "soft_lutpair128"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][5]_i_1\ : label is "soft_lutpair129"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][6]_i_1\ : label is "soft_lutpair129"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][7]_i_1\ : label is "soft_lutpair130"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][8]_i_1\ : label is "soft_lutpair130"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][9]_i_1\ : label is "soft_lutpair131"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][0]_i_1\ : label is "soft_lutpair111"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][10]_i_1\ : label is "soft_lutpair116"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][11]_i_1\ : label is "soft_lutpair117"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][12]_i_1\ : label is "soft_lutpair117"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][13]_i_1\ : label is "soft_lutpair118"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][14]_i_1\ : label is "soft_lutpair118"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][15]_i_1\ : label is "soft_lutpair119"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][16]_i_1\ : label is "soft_lutpair119"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][17]_i_1\ : label is "soft_lutpair120"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][18]_i_1\ : label is "soft_lutpair120"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][19]_i_1\ : label is "soft_lutpair121"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][1]_i_1\ : label is "soft_lutpair112"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][20]_i_1\ : label is "soft_lutpair121"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][21]_i_1\ : label is "soft_lutpair122"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][22]_i_1\ : label is "soft_lutpair122"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][23]_i_1\ : label is "soft_lutpair123"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][24]_i_1\ : label is "soft_lutpair123"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][25]_i_1\ : label is "soft_lutpair124"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][26]_i_1\ : label is "soft_lutpair124"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][27]_i_1\ : label is "soft_lutpair125"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][28]_i_1\ : label is "soft_lutpair125"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][29]_i_1\ : label is "soft_lutpair126"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][2]_i_1\ : label is "soft_lutpair112"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][30]_i_1\ : label is "soft_lutpair126"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_1\ : label is "soft_lutpair13"; + attribute IS_FANOUT_CONSTRAINED of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2\ : label is 1; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][3]_i_1\ : label is "soft_lutpair113"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][4]_i_1\ : label is "soft_lutpair113"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][5]_i_1\ : label is "soft_lutpair114"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][6]_i_1\ : label is "soft_lutpair114"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][7]_i_1\ : label is "soft_lutpair115"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][8]_i_1\ : label is "soft_lutpair115"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][9]_i_1\ : label is "soft_lutpair116"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][0]_i_1\ : label is "soft_lutpair95"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][10]_i_1\ : label is "soft_lutpair100"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][11]_i_1\ : label is "soft_lutpair101"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][12]_i_1\ : label is "soft_lutpair101"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][13]_i_1\ : label is "soft_lutpair102"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][14]_i_1\ : label is "soft_lutpair102"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][15]_i_1\ : label is "soft_lutpair103"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][16]_i_1\ : label is "soft_lutpair103"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][17]_i_1\ : label is "soft_lutpair104"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][18]_i_1\ : label is "soft_lutpair104"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][19]_i_1\ : label is "soft_lutpair105"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][1]_i_1\ : label is "soft_lutpair96"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][20]_i_1\ : label is "soft_lutpair105"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][21]_i_1\ : label is "soft_lutpair106"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][22]_i_1\ : label is "soft_lutpair106"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][23]_i_1\ : label is "soft_lutpair107"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][24]_i_1\ : label is "soft_lutpair107"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][25]_i_1\ : label is "soft_lutpair108"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][26]_i_1\ : label is "soft_lutpair108"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][27]_i_1\ : label is "soft_lutpair109"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][28]_i_1\ : label is "soft_lutpair109"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][29]_i_1\ : label is "soft_lutpair110"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][2]_i_1\ : label is "soft_lutpair96"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][30]_i_1\ : label is "soft_lutpair110"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][31]_i_1\ : label is "soft_lutpair111"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][3]_i_1\ : label is "soft_lutpair97"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][4]_i_1\ : label is "soft_lutpair97"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][5]_i_1\ : label is "soft_lutpair98"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][6]_i_1\ : label is "soft_lutpair98"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][7]_i_1\ : label is "soft_lutpair99"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][8]_i_1\ : label is "soft_lutpair99"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][9]_i_1\ : label is "soft_lutpair100"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][0]_i_1\ : label is "soft_lutpair79"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][10]_i_1\ : label is "soft_lutpair84"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][11]_i_1\ : label is "soft_lutpair85"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][12]_i_1\ : label is "soft_lutpair85"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][13]_i_1\ : label is "soft_lutpair86"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][14]_i_1\ : label is "soft_lutpair86"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][15]_i_1\ : label is "soft_lutpair87"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][16]_i_1\ : label is "soft_lutpair87"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][17]_i_1\ : label is "soft_lutpair88"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][18]_i_1\ : label is "soft_lutpair88"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][19]_i_1\ : label is "soft_lutpair89"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][1]_i_1\ : label is "soft_lutpair80"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][20]_i_1\ : label is "soft_lutpair89"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][21]_i_1\ : label is "soft_lutpair90"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][22]_i_1\ : label is "soft_lutpair90"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][23]_i_1\ : label is "soft_lutpair91"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][24]_i_1\ : label is "soft_lutpair91"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][25]_i_1\ : label is "soft_lutpair92"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][26]_i_1\ : label is "soft_lutpair92"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][27]_i_1\ : label is "soft_lutpair93"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][28]_i_1\ : label is "soft_lutpair93"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][29]_i_1\ : label is "soft_lutpair94"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][2]_i_1\ : label is "soft_lutpair80"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][30]_i_1\ : label is "soft_lutpair94"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][31]_i_1\ : label is "soft_lutpair95"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][3]_i_1\ : label is "soft_lutpair81"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][4]_i_1\ : label is "soft_lutpair81"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][5]_i_1\ : label is "soft_lutpair82"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][6]_i_1\ : label is "soft_lutpair82"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][7]_i_1\ : label is "soft_lutpair83"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][8]_i_1\ : label is "soft_lutpair83"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][9]_i_1\ : label is "soft_lutpair84"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][0]_i_1\ : label is "soft_lutpair63"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][10]_i_1\ : label is "soft_lutpair68"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][11]_i_1\ : label is "soft_lutpair69"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][12]_i_1\ : label is "soft_lutpair69"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][13]_i_1\ : label is "soft_lutpair70"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][14]_i_1\ : label is "soft_lutpair70"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][15]_i_1\ : label is "soft_lutpair71"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][16]_i_1\ : label is "soft_lutpair71"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][17]_i_1\ : label is "soft_lutpair72"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][18]_i_1\ : label is "soft_lutpair72"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][19]_i_1\ : label is "soft_lutpair73"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][1]_i_1\ : label is "soft_lutpair64"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][20]_i_1\ : label is "soft_lutpair73"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][21]_i_1\ : label is "soft_lutpair74"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][22]_i_1\ : label is "soft_lutpair74"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][23]_i_1\ : label is "soft_lutpair75"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][24]_i_1\ : label is "soft_lutpair75"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][25]_i_1\ : label is "soft_lutpair76"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][26]_i_1\ : label is "soft_lutpair76"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][27]_i_1\ : label is "soft_lutpair77"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][28]_i_1\ : label is "soft_lutpair77"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][29]_i_1\ : label is "soft_lutpair78"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][2]_i_1\ : label is "soft_lutpair64"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][30]_i_1\ : label is "soft_lutpair78"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_1\ : label is "soft_lutpair79"; + attribute IS_FANOUT_CONSTRAINED of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2\ : label is 1; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][3]_i_1\ : label is "soft_lutpair65"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][4]_i_1\ : label is "soft_lutpair65"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][5]_i_1\ : label is "soft_lutpair66"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][6]_i_1\ : label is "soft_lutpair66"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][7]_i_1\ : label is "soft_lutpair67"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][8]_i_1\ : label is "soft_lutpair67"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][9]_i_1\ : label is "soft_lutpair68"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][0]_i_1\ : label is "soft_lutpair47"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][10]_i_1\ : label is "soft_lutpair52"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][11]_i_1\ : label is "soft_lutpair53"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][12]_i_1\ : label is "soft_lutpair53"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][13]_i_1\ : label is "soft_lutpair54"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][14]_i_1\ : label is "soft_lutpair54"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][15]_i_1\ : label is "soft_lutpair55"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][16]_i_1\ : label is "soft_lutpair55"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][17]_i_1\ : label is "soft_lutpair56"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][18]_i_1\ : label is "soft_lutpair56"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][19]_i_1\ : label is "soft_lutpair57"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][1]_i_1\ : label is "soft_lutpair48"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][20]_i_1\ : label is "soft_lutpair57"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][21]_i_1\ : label is "soft_lutpair58"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][22]_i_1\ : label is "soft_lutpair58"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][23]_i_1\ : label is "soft_lutpair59"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][24]_i_1\ : label is "soft_lutpair59"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][25]_i_1\ : label is "soft_lutpair60"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][26]_i_1\ : label is "soft_lutpair60"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][27]_i_1\ : label is "soft_lutpair61"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][28]_i_1\ : label is "soft_lutpair61"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][29]_i_1\ : label is "soft_lutpair62"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][2]_i_1\ : label is "soft_lutpair48"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][30]_i_1\ : label is "soft_lutpair62"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][31]_i_1\ : label is "soft_lutpair63"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][3]_i_1\ : label is "soft_lutpair49"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][4]_i_1\ : label is "soft_lutpair49"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][5]_i_1\ : label is "soft_lutpair50"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][6]_i_1\ : label is "soft_lutpair50"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][7]_i_1\ : label is "soft_lutpair51"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][8]_i_1\ : label is "soft_lutpair51"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][9]_i_1\ : label is "soft_lutpair52"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][0]_i_1\ : label is "soft_lutpair31"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][10]_i_1\ : label is "soft_lutpair36"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][11]_i_1\ : label is "soft_lutpair37"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][12]_i_1\ : label is "soft_lutpair37"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][13]_i_1\ : label is "soft_lutpair38"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][14]_i_1\ : label is "soft_lutpair38"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][15]_i_1\ : label is "soft_lutpair39"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][16]_i_1\ : label is "soft_lutpair39"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][17]_i_1\ : label is "soft_lutpair40"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][18]_i_1\ : label is "soft_lutpair40"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][19]_i_1\ : label is "soft_lutpair41"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][1]_i_1\ : label is "soft_lutpair32"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][20]_i_1\ : label is "soft_lutpair41"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][21]_i_1\ : label is "soft_lutpair42"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][22]_i_1\ : label is "soft_lutpair42"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][23]_i_1\ : label is "soft_lutpair43"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][24]_i_1\ : label is "soft_lutpair43"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][25]_i_1\ : label is "soft_lutpair44"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][26]_i_1\ : label is "soft_lutpair44"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][27]_i_1\ : label is "soft_lutpair45"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][28]_i_1\ : label is "soft_lutpair45"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][29]_i_1\ : label is "soft_lutpair46"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][2]_i_1\ : label is "soft_lutpair32"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][30]_i_1\ : label is "soft_lutpair46"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][31]_i_1\ : label is "soft_lutpair47"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][3]_i_1\ : label is "soft_lutpair33"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][4]_i_1\ : label is "soft_lutpair33"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][5]_i_1\ : label is "soft_lutpair34"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][6]_i_1\ : label is "soft_lutpair34"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][7]_i_1\ : label is "soft_lutpair35"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][8]_i_1\ : label is "soft_lutpair35"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][9]_i_1\ : label is "soft_lutpair36"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][0]_i_1\ : label is "soft_lutpair15"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][10]_i_1\ : label is "soft_lutpair20"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][11]_i_1\ : label is "soft_lutpair21"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][12]_i_1\ : label is "soft_lutpair21"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][13]_i_1\ : label is "soft_lutpair22"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][14]_i_1\ : label is "soft_lutpair22"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][15]_i_1\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][16]_i_1\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][17]_i_1\ : label is "soft_lutpair24"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][18]_i_1\ : label is "soft_lutpair24"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][19]_i_1\ : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][1]_i_1\ : label is "soft_lutpair16"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][20]_i_1\ : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][21]_i_1\ : label is "soft_lutpair26"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][22]_i_1\ : label is "soft_lutpair26"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][23]_i_1\ : label is "soft_lutpair27"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][24]_i_1\ : label is "soft_lutpair27"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][25]_i_1\ : label is "soft_lutpair28"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][26]_i_1\ : label is "soft_lutpair28"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][27]_i_1\ : label is "soft_lutpair29"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][28]_i_1\ : label is "soft_lutpair29"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][29]_i_1\ : label is "soft_lutpair30"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][2]_i_1\ : label is "soft_lutpair16"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][30]_i_1\ : label is "soft_lutpair30"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_1\ : label is "soft_lutpair31"; + attribute IS_FANOUT_CONSTRAINED of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2\ : label is 1; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][3]_i_1\ : label is "soft_lutpair17"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][4]_i_1\ : label is "soft_lutpair17"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][5]_i_1\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][6]_i_1\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][7]_i_1\ : label is "soft_lutpair19"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][8]_i_1\ : label is "soft_lutpair19"; + attribute SOFT_HLUTNM of \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][9]_i_1\ : label is "soft_lutpair20"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \data_sync_reg[0][0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \data_sync_reg[0][0]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][0]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][10]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][10]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][10]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][11]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][11]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][11]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][12]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][12]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][12]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][13]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][13]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][13]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][14]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][14]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][14]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][15]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][15]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][15]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][16]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][16]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][16]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][16]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][17]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][17]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][17]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][17]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][18]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][18]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][18]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][18]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][19]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][19]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][19]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][19]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][1]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][1]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][1]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][20]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][20]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][20]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][20]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][21]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][21]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][21]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][21]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][22]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][22]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][22]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][22]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][23]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][23]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][23]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][23]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][24]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][24]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][24]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][24]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][25]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][25]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][25]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][25]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][26]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][26]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][26]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][26]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][27]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][27]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][27]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][27]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][28]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][28]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][28]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][28]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][29]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][29]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][29]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][29]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][2]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][2]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][2]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][30]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][30]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][30]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][30]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][31]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][31]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][31]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][31]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][32]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][32]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][32]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][32]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][33]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][33]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][33]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][33]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][34]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][34]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][34]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][34]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][35]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][35]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][35]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][35]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][36]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][36]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][36]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][36]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][37]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][37]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][37]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][37]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][38]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][38]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][38]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][38]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][39]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][39]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][39]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][39]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][3]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][3]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][3]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][40]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][40]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][40]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][40]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][41]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][41]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][41]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][41]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][42]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][42]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][42]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][42]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][43]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][43]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][43]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][43]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][44]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][44]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][44]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][44]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][4]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][4]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][4]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][5]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][5]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][5]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][6]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][6]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][6]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][7]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][7]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][7]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][8]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][8]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][8]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][9]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][9]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][9]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][9]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][0]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][0]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][0]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][10]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][10]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][10]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][11]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][11]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][11]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][12]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][12]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][12]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][13]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][13]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][13]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][14]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][14]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][14]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][15]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][15]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][15]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][16]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][16]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][16]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][16]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][17]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][17]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][17]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][17]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][18]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][18]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][18]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][18]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][19]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][19]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][19]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][19]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][1]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][1]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][1]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][20]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][20]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][20]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][20]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][21]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][21]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][21]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][21]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][22]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][22]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][22]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][22]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][23]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][23]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][23]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][23]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][24]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][24]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][24]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][24]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][25]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][25]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][25]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][25]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][26]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][26]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][26]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][26]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][27]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][27]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][27]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][27]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][28]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][28]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][28]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][28]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][29]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][29]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][29]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][29]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][2]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][2]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][2]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][30]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][30]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][30]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][30]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][31]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][31]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][31]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][31]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][32]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][32]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][32]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][32]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][33]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][33]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][33]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][33]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][34]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][34]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][34]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][34]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][35]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][35]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][35]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][35]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][36]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][36]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][36]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][36]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][37]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][37]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][37]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][37]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][38]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][38]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][38]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][38]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][39]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][39]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][39]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][39]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][3]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][3]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][3]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][40]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][40]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][40]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][40]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][41]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][41]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][41]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][41]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][42]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][42]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][42]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][42]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][43]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][43]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][43]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][43]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][44]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][44]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][44]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][44]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][4]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][4]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][4]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][5]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][5]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][5]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][6]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][6]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][6]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][7]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][7]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][7]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][8]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][8]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][8]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][9]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][9]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][9]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][9]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][0]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][0]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][0]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][10]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][10]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][10]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][11]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][11]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][11]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][12]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][12]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][12]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][13]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][13]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][13]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][14]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][14]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][14]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][15]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][15]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][15]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][16]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][16]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][16]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][16]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][17]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][17]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][17]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][17]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][18]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][18]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][18]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][18]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][19]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][19]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][19]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][19]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][1]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][1]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][1]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][20]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][20]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][20]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][20]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][21]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][21]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][21]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][21]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][22]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][22]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][22]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][22]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][23]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][23]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][23]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][23]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][24]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][24]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][24]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][24]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][25]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][25]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][25]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][25]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][26]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][26]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][26]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][26]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][27]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][27]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][27]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][27]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][28]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][28]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][28]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][28]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][29]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][29]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][29]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][29]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][2]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][2]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][2]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][30]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][30]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][30]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][30]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][31]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][31]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][31]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][31]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][32]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][32]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][32]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][32]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][33]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][33]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][33]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][33]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][34]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][34]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][34]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][34]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][35]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][35]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][35]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][35]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][36]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][36]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][36]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][36]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][37]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][37]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][37]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][37]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][38]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][38]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][38]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][38]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][39]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][39]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][39]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][39]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][3]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][3]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][3]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][40]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][40]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][40]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][40]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][41]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][41]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][41]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][41]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][42]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][42]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][42]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][42]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][43]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][43]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][43]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][43]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][44]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][44]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][44]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][44]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][4]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][4]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][4]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][5]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][5]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][5]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][6]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][6]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][6]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][7]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][7]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][7]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][8]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][8]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][8]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][9]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][9]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][9]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][9]\ : label is "NO"; +begin + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0\ <= \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\; + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31]\ <= \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\; + ipif_Addr(8 downto 0) <= \^ipif_addr\(8 downto 0); + out_data(32) <= \data_sync[2]_2\(42); + out_data(31 downto 0) <= \data_sync[2]_2\(31 downto 0); +\AXI4_LITE_INTERFACE.core_control_regs_int[0][26]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00080000" + ) + port map ( + I0 => \data_sync[2]_2\(42), + I1 => write_ack_int, + I2 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + I3 => \^ipif_addr\(3), + I4 => \AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2_n_0\, + O => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]\(0) + ); +\AXI4_LITE_INTERFACE.core_control_regs_int[10][26]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00800000" + ) + port map ( + I0 => \data_sync[2]_2\(42), + I1 => write_ack_int, + I2 => \^ipif_addr\(3), + I3 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + I4 => \AXI4_LITE_INTERFACE.core_control_regs_int[9][26]_i_2_n_0\, + O => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][0]\(0) + ); +\AXI4_LITE_INTERFACE.core_control_regs_int[11][26]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \^ipif_addr\(3), + I1 => write_ack_int, + I2 => \data_sync[2]_2\(42), + I3 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + I4 => \AXI4_LITE_INTERFACE.core_control_regs_int[9][26]_i_2_n_0\, + O => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][0]\(0) + ); +\AXI4_LITE_INTERFACE.core_control_regs_int[12][26]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"20000000" + ) + port map ( + I0 => vid_aclk_en, + I1 => \^ipif_addr\(6), + I2 => \^ipif_addr\(4), + I3 => \^ipif_addr\(5), + I4 => \AXI4_LITE_INTERFACE.core_control_regs_int[16][26]_i_2_n_0\, + O => E(0) + ); +\AXI4_LITE_INTERFACE.core_control_regs_int[13][26]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000000" + ) + port map ( + I0 => \^ipif_addr\(3), + I1 => write_ack_int, + I2 => \data_sync[2]_2\(42), + I3 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + I4 => \AXI4_LITE_INTERFACE.core_control_regs_int[13][26]_i_2_n_0\, + O => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][0]\(0) + ); +\AXI4_LITE_INTERFACE.core_control_regs_int[13][26]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0800" + ) + port map ( + I0 => \^ipif_addr\(5), + I1 => \^ipif_addr\(4), + I2 => \^ipif_addr\(6), + I3 => vid_aclk_en, + O => \AXI4_LITE_INTERFACE.core_control_regs_int[13][26]_i_2_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int[14][26]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00800000" + ) + port map ( + I0 => \data_sync[2]_2\(42), + I1 => write_ack_int, + I2 => \^ipif_addr\(3), + I3 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + I4 => \AXI4_LITE_INTERFACE.core_control_regs_int[13][26]_i_2_n_0\, + O => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][0]\(0) + ); +\AXI4_LITE_INTERFACE.core_control_regs_int[15][26]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \^ipif_addr\(3), + I1 => write_ack_int, + I2 => \data_sync[2]_2\(42), + I3 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + I4 => \AXI4_LITE_INTERFACE.core_control_regs_int[13][26]_i_2_n_0\, + O => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][0]\(0) + ); +\AXI4_LITE_INTERFACE.core_control_regs_int[16][26]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00080000" + ) + port map ( + I0 => \^ipif_addr\(6), + I1 => vid_aclk_en, + I2 => \^ipif_addr\(4), + I3 => \^ipif_addr\(5), + I4 => \AXI4_LITE_INTERFACE.core_control_regs_int[16][26]_i_2_n_0\, + O => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][0]\(0) + ); +\AXI4_LITE_INTERFACE.core_control_regs_int[16][26]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"1000" + ) + port map ( + I0 => \^ipif_addr\(3), + I1 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + I2 => write_ack_int, + I3 => \data_sync[2]_2\(42), + O => \AXI4_LITE_INTERFACE.core_control_regs_int[16][26]_i_2_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int[1][26]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000000" + ) + port map ( + I0 => \^ipif_addr\(3), + I1 => write_ack_int, + I2 => \data_sync[2]_2\(42), + I3 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + I4 => \AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2_n_0\, + O => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][0]\(0) + ); +\AXI4_LITE_INTERFACE.core_control_regs_int[2][26]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00800000" + ) + port map ( + I0 => \data_sync[2]_2\(42), + I1 => write_ack_int, + I2 => \^ipif_addr\(3), + I3 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + I4 => \AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2_n_0\, + O => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][0]\(0) + ); +\AXI4_LITE_INTERFACE.core_control_regs_int[3][26]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \^ipif_addr\(3), + I1 => write_ack_int, + I2 => \data_sync[2]_2\(42), + I3 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + I4 => \AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2_n_0\, + O => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][0]\(0) + ); +\AXI4_LITE_INTERFACE.core_control_regs_int[4][26]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00200000" + ) + port map ( + I0 => \^ipif_addr\(4), + I1 => \^ipif_addr\(6), + I2 => vid_aclk_en, + I3 => \^ipif_addr\(5), + I4 => \AXI4_LITE_INTERFACE.core_control_regs_int[16][26]_i_2_n_0\, + O => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][0]\(0) + ); +\AXI4_LITE_INTERFACE.core_control_regs_int[5][26]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000000" + ) + port map ( + I0 => \^ipif_addr\(3), + I1 => write_ack_int, + I2 => \data_sync[2]_2\(42), + I3 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + I4 => \AXI4_LITE_INTERFACE.time_control_regs_int[28][28]_i_2_n_0\, + O => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][0]\(0) + ); +\AXI4_LITE_INTERFACE.core_control_regs_int[6][26]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00800000" + ) + port map ( + I0 => \data_sync[2]_2\(42), + I1 => write_ack_int, + I2 => \^ipif_addr\(3), + I3 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + I4 => \AXI4_LITE_INTERFACE.time_control_regs_int[28][28]_i_2_n_0\, + O => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][0]\(0) + ); +\AXI4_LITE_INTERFACE.core_control_regs_int[7][26]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \^ipif_addr\(3), + I1 => write_ack_int, + I2 => \data_sync[2]_2\(42), + I3 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + I4 => \AXI4_LITE_INTERFACE.time_control_regs_int[28][28]_i_2_n_0\, + O => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][0]\(0) + ); +\AXI4_LITE_INTERFACE.core_control_regs_int[8][26]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00200000" + ) + port map ( + I0 => vid_aclk_en, + I1 => \^ipif_addr\(6), + I2 => \^ipif_addr\(5), + I3 => \^ipif_addr\(4), + I4 => \AXI4_LITE_INTERFACE.core_control_regs_int[16][26]_i_2_n_0\, + O => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][0]\(0) + ); +\AXI4_LITE_INTERFACE.core_control_regs_int[9][26]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000000" + ) + port map ( + I0 => \^ipif_addr\(3), + I1 => write_ack_int, + I2 => \data_sync[2]_2\(42), + I3 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + I4 => \AXI4_LITE_INTERFACE.core_control_regs_int[9][26]_i_2_n_0\, + O => \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][0]\(0) + ); +\AXI4_LITE_INTERFACE.core_control_regs_int[9][26]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0400" + ) + port map ( + I0 => \^ipif_addr\(4), + I1 => \^ipif_addr\(5), + I2 => \^ipif_addr\(6), + I3 => vid_aclk_en, + O => \AXI4_LITE_INTERFACE.core_control_regs_int[9][26]_i_2_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000080" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2_n_0\, + I1 => write_ack_int, + I2 => \data_sync[2]_2\(41), + I3 => \^ipif_addr\(7), + I4 => \^ipif_addr\(3), + I5 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + O => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][0]\(0) + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0004" + ) + port map ( + I0 => \^ipif_addr\(5), + I1 => vid_aclk_en, + I2 => \^ipif_addr\(6), + I3 => \^ipif_addr\(4), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \data_sync[2]_2\(34), + O => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[1][10]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000D0D080808080" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0\, + I1 => \data_sync[2]_2\(10), + I2 => \AXI4_LITE_INTERFACE.soft_resetn_reg\, + I3 => \data_sync[2]_2\(41), + I4 => vid_aclk_en, + I5 => D(2), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][10]\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[1][11]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000D0D080808080" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0\, + I1 => \data_sync[2]_2\(11), + I2 => \AXI4_LITE_INTERFACE.soft_resetn_reg\, + I3 => \data_sync[2]_2\(41), + I4 => vid_aclk_en, + I5 => D(3), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][11]\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[1][12]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000D0D080808080" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0\, + I1 => \data_sync[2]_2\(12), + I2 => \AXI4_LITE_INTERFACE.soft_resetn_reg\, + I3 => \data_sync[2]_2\(41), + I4 => vid_aclk_en, + I5 => D(4), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][12]\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[1][13]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000D0D080808080" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0\, + I1 => \data_sync[2]_2\(13), + I2 => \AXI4_LITE_INTERFACE.soft_resetn_reg\, + I3 => \data_sync[2]_2\(41), + I4 => vid_aclk_en, + I5 => D(5), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][13]\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[1][16]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000D0D080808080" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0\, + I1 => \data_sync[2]_2\(16), + I2 => \AXI4_LITE_INTERFACE.soft_resetn_reg\, + I3 => \data_sync[2]_2\(41), + I4 => vid_aclk_en, + I5 => D(6), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][16]\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[1][17]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000D0D080808080" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0\, + I1 => \data_sync[2]_2\(17), + I2 => \AXI4_LITE_INTERFACE.soft_resetn_reg\, + I3 => \data_sync[2]_2\(41), + I4 => vid_aclk_en, + I5 => D(7), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][17]\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[1][18]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000D0D080808080" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0\, + I1 => \data_sync[2]_2\(18), + I2 => \AXI4_LITE_INTERFACE.soft_resetn_reg\, + I3 => \data_sync[2]_2\(41), + I4 => vid_aclk_en, + I5 => D(8), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][18]\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[1][19]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000D0D080808080" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0\, + I1 => \data_sync[2]_2\(19), + I2 => \AXI4_LITE_INTERFACE.soft_resetn_reg\, + I3 => \data_sync[2]_2\(41), + I4 => vid_aclk_en, + I5 => D(9), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][19]\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[1][20]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000D0D080808080" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0\, + I1 => \data_sync[2]_2\(20), + I2 => \AXI4_LITE_INTERFACE.soft_resetn_reg\, + I3 => \data_sync[2]_2\(41), + I4 => vid_aclk_en, + I5 => D(10), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][20]\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[1][21]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000D0D080808080" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0\, + I1 => \data_sync[2]_2\(21), + I2 => \AXI4_LITE_INTERFACE.soft_resetn_reg\, + I3 => \data_sync[2]_2\(41), + I4 => vid_aclk_en, + I5 => D(11), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][21]\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[1][22]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000D0D080808080" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0\, + I1 => \data_sync[2]_2\(22), + I2 => \AXI4_LITE_INTERFACE.soft_resetn_reg\, + I3 => \data_sync[2]_2\(41), + I4 => vid_aclk_en, + I5 => D(12), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][22]\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[1][23]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000D0D080808080" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0\, + I1 => \data_sync[2]_2\(23), + I2 => \AXI4_LITE_INTERFACE.soft_resetn_reg\, + I3 => \data_sync[2]_2\(41), + I4 => vid_aclk_en, + I5 => D(13), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][23]\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[1][24]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000D0D080808080" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0\, + I1 => \data_sync[2]_2\(24), + I2 => \AXI4_LITE_INTERFACE.soft_resetn_reg\, + I3 => \data_sync[2]_2\(41), + I4 => vid_aclk_en, + I5 => D(14), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][24]\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[1][25]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000D0D080808080" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0\, + I1 => \data_sync[2]_2\(25), + I2 => \AXI4_LITE_INTERFACE.soft_resetn_reg\, + I3 => \data_sync[2]_2\(41), + I4 => vid_aclk_en, + I5 => D(15), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][25]\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[1][26]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000D0D080808080" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0\, + I1 => \data_sync[2]_2\(26), + I2 => \AXI4_LITE_INTERFACE.soft_resetn_reg\, + I3 => \data_sync[2]_2\(41), + I4 => vid_aclk_en, + I5 => D(16), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][26]\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[1][27]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000D0D080808080" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0\, + I1 => \data_sync[2]_2\(27), + I2 => \AXI4_LITE_INTERFACE.soft_resetn_reg\, + I3 => \data_sync[2]_2\(41), + I4 => vid_aclk_en, + I5 => D(17), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][27]\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[1][28]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000D0D080808080" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0\, + I1 => \data_sync[2]_2\(28), + I2 => \AXI4_LITE_INTERFACE.soft_resetn_reg\, + I3 => \data_sync[2]_2\(41), + I4 => vid_aclk_en, + I5 => D(18), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][28]\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[1][29]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000D0D080808080" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0\, + I1 => \data_sync[2]_2\(29), + I2 => \AXI4_LITE_INTERFACE.soft_resetn_reg\, + I3 => \data_sync[2]_2\(41), + I4 => vid_aclk_en, + I5 => D(19), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][29]\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[1][30]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000D0D080808080" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0\, + I1 => \data_sync[2]_2\(30), + I2 => \AXI4_LITE_INTERFACE.soft_resetn_reg\, + I3 => \data_sync[2]_2\(41), + I4 => vid_aclk_en, + I5 => D(20), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][30]\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000D0D080808080" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0\, + I1 => \data_sync[2]_2\(31), + I2 => \AXI4_LITE_INTERFACE.soft_resetn_reg\, + I3 => \data_sync[2]_2\(41), + I4 => vid_aclk_en, + I5 => D(21), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][31]\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000040000000" + ) + port map ( + I0 => \^ipif_addr\(3), + I1 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + I2 => \AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2_n_0\, + I3 => write_ack_int, + I4 => \data_sync[2]_2\(41), + I5 => \^ipif_addr\(7), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[1][8]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000D0D080808080" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0\, + I1 => \data_sync[2]_2\(8), + I2 => \AXI4_LITE_INTERFACE.soft_resetn_reg\, + I3 => \data_sync[2]_2\(41), + I4 => vid_aclk_en, + I5 => D(0), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][8]\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[1][9]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000D0D080808080" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[1][31]_i_2_n_0\, + I1 => \data_sync[2]_2\(9), + I2 => \AXI4_LITE_INTERFACE.soft_resetn_reg\, + I3 => \data_sync[2]_2\(41), + I4 => vid_aclk_en, + I5 => D(1), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][9]\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[2][16]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000D0D080808080" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[2][21]_i_2_n_0\, + I1 => \data_sync[2]_2\(16), + I2 => \AXI4_LITE_INTERFACE.soft_resetn_reg\, + I3 => \data_sync[2]_2\(41), + I4 => vid_aclk_en, + I5 => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][21]_0\(0), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][16]\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[2][17]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000D0D080808080" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[2][21]_i_2_n_0\, + I1 => \data_sync[2]_2\(17), + I2 => \AXI4_LITE_INTERFACE.soft_resetn_reg\, + I3 => \data_sync[2]_2\(41), + I4 => vid_aclk_en, + I5 => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][21]_0\(1), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][17]\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[2][18]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000D0D080808080" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[2][21]_i_2_n_0\, + I1 => \data_sync[2]_2\(18), + I2 => \AXI4_LITE_INTERFACE.soft_resetn_reg\, + I3 => \data_sync[2]_2\(41), + I4 => vid_aclk_en, + I5 => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][21]_0\(2), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][18]\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[2][19]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000D0D080808080" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[2][21]_i_2_n_0\, + I1 => \data_sync[2]_2\(19), + I2 => \AXI4_LITE_INTERFACE.soft_resetn_reg\, + I3 => \data_sync[2]_2\(41), + I4 => vid_aclk_en, + I5 => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][21]_0\(3), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][19]\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[2][20]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000D0D080808080" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[2][21]_i_2_n_0\, + I1 => \data_sync[2]_2\(20), + I2 => \AXI4_LITE_INTERFACE.soft_resetn_reg\, + I3 => \data_sync[2]_2\(41), + I4 => vid_aclk_en, + I5 => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][21]_0\(4), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][20]\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[2][21]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000D0D080808080" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[2][21]_i_2_n_0\, + I1 => \data_sync[2]_2\(21), + I2 => \AXI4_LITE_INTERFACE.soft_resetn_reg\, + I3 => \data_sync[2]_2\(41), + I4 => vid_aclk_en, + I5 => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][21]_0\(5), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][21]\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[2][21]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000008000000000" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2_n_0\, + I1 => write_ack_int, + I2 => \data_sync[2]_2\(41), + I3 => \^ipif_addr\(7), + I4 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + I5 => \^ipif_addr\(3), + O => \AXI4_LITE_INTERFACE.genr_control_regs_int[2][21]_i_2_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int[3][31]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0080000000000000" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2_n_0\, + I1 => write_ack_int, + I2 => \data_sync[2]_2\(41), + I3 => \^ipif_addr\(7), + I4 => \^ipif_addr\(3), + I5 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + O => \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][8]\(0) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[0]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(0), + I1 => core_data(0), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(0), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[10]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(10), + I1 => core_data(10), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(10), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[11]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(11), + I1 => core_data(11), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(11), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[12]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(12), + I1 => core_data(12), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(12), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[13]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(13), + I1 => core_data(13), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(13), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[14]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(14), + I1 => core_data(14), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(14), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[15]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(15), + I1 => core_data(15), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(15), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[16]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(16), + I1 => core_data(16), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(16), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[17]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(17), + I1 => core_data(17), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(17), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[18]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(18), + I1 => core_data(18), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(18), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[19]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(19), + I1 => core_data(19), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(19), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[1]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(1), + I1 => core_data(1), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(1), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[20]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(20), + I1 => core_data(20), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(20), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[21]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(21), + I1 => core_data(21), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(21), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[22]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(22), + I1 => core_data(22), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(22), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[23]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(23), + I1 => core_data(23), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(23), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[24]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(24), + I1 => core_data(24), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(24), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[25]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(25), + I1 => core_data(25), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(25), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[26]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(26), + I1 => core_data(26), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(26), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[27]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(27), + I1 => core_data(27), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(27), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[28]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(28), + I1 => core_data(28), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(28), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[29]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(29), + I1 => core_data(29), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(29), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[2]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(2), + I1 => core_data(2), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(2), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[30]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(30), + I1 => core_data(30), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(30), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[31]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(31), + I1 => core_data(31), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(31), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[3]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(3), + I1 => core_data(3), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(3), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[4]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(4), + I1 => core_data(4), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(4), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[5]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(5), + I1 => core_data(5), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(5), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[6]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(6), + I1 => core_data(6), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(6), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[7]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(7), + I1 => core_data(7), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(7), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[8]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(8), + I1 => core_data(8), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(8), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[9]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => genr_data(9), + I1 => core_data(9), + O => \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(9), + S => \data_sync[2]_2\(42) + ); +\AXI4_LITE_INTERFACE.read_ack_d_reg[2]_srl4___AXI4_LITE_INTERFACE.read_ack_d_reg_r_1_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E0" + ) + port map ( + I0 => \data_sync[2]_2\(41), + I1 => \data_sync[2]_2\(42), + I2 => \data_sync[2]_2\(43), + O => p_535_out + ); +\AXI4_LITE_INTERFACE.soft_resetn_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00080808" + ) + port map ( + I0 => vid_aresetn, + I1 => \data_sync[2]_2\(44), + I2 => \genr_control_regs[0]\(24), + I3 => reg_update, + I4 => \genr_control_regs[0]\(23), + O => p_456_out + ); +\AXI4_LITE_INTERFACE.time_control_regs_int[16][28]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00100000" + ) + port map ( + I0 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + I1 => \^ipif_addr\(3), + I2 => \^ipif_addr\(5), + I3 => \^ipif_addr\(4), + I4 => \AXI4_LITE_INTERFACE.time_control_regs_int[18][6]_i_2_n_0\, + O => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][0]\(0) + ); +\AXI4_LITE_INTERFACE.time_control_regs_int[18][6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00200000" + ) + port map ( + I0 => \^ipif_addr\(3), + I1 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + I2 => \^ipif_addr\(5), + I3 => \^ipif_addr\(4), + I4 => \AXI4_LITE_INTERFACE.time_control_regs_int[18][6]_i_2_n_0\, + O => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][7]\(0) + ); +\AXI4_LITE_INTERFACE.time_control_regs_int[18][6]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"08000000" + ) + port map ( + I0 => vid_aclk_en, + I1 => \^ipif_addr\(6), + I2 => \^ipif_addr\(7), + I3 => \data_sync[2]_2\(41), + I4 => write_ack_int, + O => \AXI4_LITE_INTERFACE.time_control_regs_int[18][6]_i_2_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int[19][6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00800000" + ) + port map ( + I0 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + I1 => \^ipif_addr\(3), + I2 => \^ipif_addr\(5), + I3 => \^ipif_addr\(4), + I4 => \AXI4_LITE_INTERFACE.time_control_regs_int[18][6]_i_2_n_0\, + O => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][0]\(0) + ); +\AXI4_LITE_INTERFACE.time_control_regs_int[20][28]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000080" + ) + port map ( + I0 => \^ipif_addr\(4), + I1 => \^ipif_addr\(5), + I2 => \AXI4_LITE_INTERFACE.time_control_regs_int[18][6]_i_2_n_0\, + I3 => \^ipif_addr\(3), + I4 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + O => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][0]\(0) + ); +\AXI4_LITE_INTERFACE.time_control_regs_int[21][28]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000000" + ) + port map ( + I0 => \^ipif_addr\(3), + I1 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + I2 => \^ipif_addr\(4), + I3 => \^ipif_addr\(5), + I4 => \AXI4_LITE_INTERFACE.time_control_regs_int[18][6]_i_2_n_0\, + O => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][0]\(0) + ); +\AXI4_LITE_INTERFACE.time_control_regs_int[22][28]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00800000" + ) + port map ( + I0 => \^ipif_addr\(4), + I1 => \^ipif_addr\(5), + I2 => \AXI4_LITE_INTERFACE.time_control_regs_int[18][6]_i_2_n_0\, + I3 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + I4 => \^ipif_addr\(3), + O => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][0]\(0) + ); +\AXI4_LITE_INTERFACE.time_control_regs_int[23][28]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \^ipif_addr\(4), + I1 => \^ipif_addr\(5), + I2 => \AXI4_LITE_INTERFACE.time_control_regs_int[18][6]_i_2_n_0\, + I3 => \^ipif_addr\(3), + I4 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + O => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][0]\(0) + ); +\AXI4_LITE_INTERFACE.time_control_regs_int[24][28]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000008000" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2_n_0\, + I1 => write_ack_int, + I2 => \data_sync[2]_2\(41), + I3 => \^ipif_addr\(7), + I4 => \^ipif_addr\(3), + I5 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + O => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][0]\(0) + ); +\AXI4_LITE_INTERFACE.time_control_regs_int[25][28]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4000000000000000" + ) + port map ( + I0 => \^ipif_addr\(3), + I1 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + I2 => \AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2_n_0\, + I3 => write_ack_int, + I4 => \data_sync[2]_2\(41), + I5 => \^ipif_addr\(7), + O => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][0]\(0) + ); +\AXI4_LITE_INTERFACE.time_control_regs_int[26][28]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000800000000000" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2_n_0\, + I1 => write_ack_int, + I2 => \data_sync[2]_2\(41), + I3 => \^ipif_addr\(7), + I4 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + I5 => \^ipif_addr\(3), + O => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][0]\(0) + ); +\AXI4_LITE_INTERFACE.time_control_regs_int[27][28]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.genr_control_regs_int[0][31]_i_2_n_0\, + I1 => write_ack_int, + I2 => \data_sync[2]_2\(41), + I3 => \^ipif_addr\(7), + I4 => \^ipif_addr\(3), + I5 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + O => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][0]\(0) + ); +\AXI4_LITE_INTERFACE.time_control_regs_int[28][28]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1000000000000000" + ) + port map ( + I0 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + I1 => \^ipif_addr\(3), + I2 => write_ack_int, + I3 => \data_sync[2]_2\(41), + I4 => \^ipif_addr\(7), + I5 => \AXI4_LITE_INTERFACE.time_control_regs_int[28][28]_i_2_n_0\, + O => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][0]\(0) + ); +\AXI4_LITE_INTERFACE.time_control_regs_int[28][28]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0400" + ) + port map ( + I0 => \^ipif_addr\(5), + I1 => vid_aclk_en, + I2 => \^ipif_addr\(6), + I3 => \^ipif_addr\(4), + O => \AXI4_LITE_INTERFACE.time_control_regs_int[28][28]_i_2_n_0\ + ); +\AXI4_LITE_INTERFACE.write_ack_e1_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => \data_sync[2]_2\(41), + I1 => \data_sync[2]_2\(42), + I2 => \data_sync[2]_2\(43), + O => p_533_out + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(0), + I1 => \genr_control_regs[0]\(0), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][0]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(10), + I1 => \genr_control_regs[0]\(7), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][10]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][11]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(11), + I1 => \genr_control_regs[0]\(8), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][11]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][12]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(12), + I1 => \genr_status_regs[0]\(3), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][12]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][13]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(13), + I1 => \genr_control_regs[0]\(9), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][13]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][14]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(14), + I1 => \genr_control_regs[0]\(10), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][14]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][15]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(15), + I1 => \genr_control_regs[0]\(11), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][15]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][16]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(16), + I1 => \genr_control_regs[0]\(12), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][16]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][17]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(17), + I1 => \genr_control_regs[0]\(13), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][17]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][18]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(18), + I1 => \genr_control_regs[0]\(14), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][18]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][19]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(19), + I1 => \genr_control_regs[0]\(15), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][19]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(1), + I1 => \genr_control_regs[0]\(1), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][1]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][20]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(20), + I1 => \genr_control_regs[0]\(16), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][20]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][21]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(21), + I1 => \genr_control_regs[0]\(17), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][21]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][22]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(22), + I1 => \genr_control_regs[0]\(18), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][22]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][23]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(23), + I1 => \genr_control_regs[0]\(19), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][23]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][24]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(24), + I1 => \genr_control_regs[0]\(20), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][24]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][25]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(25), + I1 => \genr_control_regs[0]\(21), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][25]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][26]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(26), + I1 => \genr_control_regs[0]\(22), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][26]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][27]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(27), + I1 => \genr_status_regs[0]\(4), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][27]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][28]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(28), + I1 => \genr_status_regs[0]\(5), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][28]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][29]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(29), + I1 => \genr_status_regs[0]\(6), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][29]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(2), + I1 => \genr_control_regs[0]\(2), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][2]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][30]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(30), + I1 => \genr_control_regs[0]\(23), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][30]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][31]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \genr_control_regs[0]\(24), + I1 => \^axi4_lite_interface.core_control_regs_int_reg[0][0]_0\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][31]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(3), + I1 => \genr_control_regs[0]\(3), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][3]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(4), + I1 => \genr_status_regs[0]\(0), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][4]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(5), + I1 => \genr_control_regs[0]\(4), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][5]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(6), + I1 => \genr_status_regs[0]\(1), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][6]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(7), + I1 => \genr_status_regs[0]\(2), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][7]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(8), + I1 => \genr_control_regs[0]\(5), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][8]\ + ); +\GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg[31][9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(9), + I1 => \genr_control_regs[0]\(6), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][9]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs[3]\(0), + I1 => intr_err(0), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][0]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_control_regs[3]\(2), + I1 => intr_err(10), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][10]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][11]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_control_regs[3]\(3), + I1 => intr_err(11), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][11]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][12]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_control_regs[3]\(4), + I1 => intr_err(12), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][12]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][13]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_control_regs[3]\(5), + I1 => intr_err(13), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][13]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][14]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs[3]\(8), + I1 => intr_err(14), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][14]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][15]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs[3]\(9), + I1 => intr_err(15), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][15]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][16]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_control_regs[3]\(6), + I1 => intr_err(16), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][16]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][17]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_control_regs[3]\(7), + I1 => intr_err(17), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][17]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][18]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_control_regs[3]\(8), + I1 => intr_err(18), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][18]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][19]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_control_regs[3]\(9), + I1 => intr_err(19), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][19]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs[3]\(1), + I1 => intr_err(1), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][1]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][20]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_control_regs[3]\(10), + I1 => intr_err(20), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][20]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][21]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_control_regs[3]\(11), + I1 => intr_err(21), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][21]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][22]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_control_regs[3]\(12), + I1 => intr_err(22), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][22]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][23]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_control_regs[3]\(13), + I1 => intr_err(23), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][23]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][24]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_control_regs[3]\(14), + I1 => intr_err(24), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][24]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][25]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_control_regs[3]\(15), + I1 => intr_err(25), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][25]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][26]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_control_regs[3]\(16), + I1 => intr_err(26), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][26]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][27]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_control_regs[3]\(17), + I1 => intr_err(27), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][27]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][28]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_control_regs[3]\(18), + I1 => intr_err(28), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][28]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][29]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_control_regs[3]\(19), + I1 => intr_err(29), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][29]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs[3]\(2), + I1 => intr_err(2), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][2]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][30]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_control_regs[3]\(20), + I1 => intr_err(30), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][30]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][31]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_control_regs[3]\(21), + I1 => intr_err(31), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][31]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs[3]\(3), + I1 => intr_err(3), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][3]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs[3]\(4), + I1 => intr_err(4), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][4]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs[3]\(5), + I1 => intr_err(5), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][5]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs[3]\(6), + I1 => intr_err(6), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][6]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_status_regs[3]\(7), + I1 => intr_err(7), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][7]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_control_regs[3]\(0), + I1 => intr_err(8), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][8]\ + ); +\GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg[32][9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \genr_control_regs[3]\(1), + I1 => intr_err(9), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][9]\ + ); +\GEN_TREE.GEN_BRANCH[33].GEN_MUX_REG.data_out_reg[33][26]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[33].GEN_MUX_REG.data_out_reg_reg[33][26]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(0), + I1 => \time_status_regs[0]\(0), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][0]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(10), + I1 => \time_status_regs[0]\(10), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][10]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][11]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(11), + I1 => \time_status_regs[0]\(11), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][12]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(12), + I1 => \time_status_regs[0]\(12), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][12]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][13]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(13), + I1 => \time_status_regs[0]\(13), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][13]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][14]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(14), + I1 => \time_status_regs[0]\(14), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][14]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][15]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(15), + I1 => \time_status_regs[0]\(15), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][15]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][16]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(16), + I1 => \time_status_regs[0]\(16), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][16]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][17]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(17), + I1 => \time_status_regs[0]\(17), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][17]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][18]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(18), + I1 => \time_status_regs[0]\(18), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][18]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][19]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(19), + I1 => \time_status_regs[0]\(19), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][19]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(1), + I1 => \time_status_regs[0]\(1), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][1]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][20]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(20), + I1 => \time_status_regs[0]\(20), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][20]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][21]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(21), + I1 => \time_status_regs[0]\(21), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][21]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][22]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(22), + I1 => \time_status_regs[0]\(22), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][22]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][23]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(23), + I1 => \time_status_regs[0]\(23), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][23]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][24]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(24), + I1 => \time_status_regs[0]\(24), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][24]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][25]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(25), + I1 => \time_status_regs[0]\(25), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][25]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][26]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(26), + I1 => \time_status_regs[0]\(26), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][26]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][27]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(27), + I1 => \time_status_regs[0]\(27), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][27]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][28]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(28), + I1 => \time_status_regs[0]\(28), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][28]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][29]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(29), + I1 => \time_status_regs[0]\(29), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][29]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(2), + I1 => \time_status_regs[0]\(2), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][2]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][30]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(30), + I1 => \time_status_regs[0]\(30), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][30]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][31]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(31), + I1 => \time_status_regs[0]\(31), + I2 => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31]_0\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][31]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \data_sync[2]_2\(34), + O => \^gen_tree.gen_branch[35].gen_mux_reg.data_out_reg_reg[35][31]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(3), + I1 => \time_status_regs[0]\(3), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][3]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(4), + I1 => \time_status_regs[0]\(4), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][4]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(5), + I1 => \time_status_regs[0]\(5), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][5]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(6), + I1 => \time_status_regs[0]\(6), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][6]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(7), + I1 => \time_status_regs[0]\(7), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][7]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(8), + I1 => \time_status_regs[0]\(8), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][8]\ + ); +\GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg[35][9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[1]\(9), + I1 => \time_status_regs[0]\(9), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][9]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(0), + I1 => \time_status_regs[2]\(0), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][0]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(10), + I1 => \time_status_regs[2]\(10), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][10]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][11]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(11), + I1 => \time_status_regs[2]\(11), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][11]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][12]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(12), + I1 => \time_status_regs[2]\(12), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][12]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][13]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(13), + I1 => \time_status_regs[2]\(13), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][13]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][14]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(14), + I1 => \time_status_regs[2]\(14), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][14]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][15]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(15), + I1 => \time_status_regs[2]\(15), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][15]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][16]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(16), + I1 => \time_status_regs[2]\(16), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][16]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][17]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(17), + I1 => \time_status_regs[2]\(17), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][17]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][18]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(18), + I1 => \time_status_regs[2]\(18), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][18]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][19]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(19), + I1 => \time_status_regs[2]\(19), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][19]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(1), + I1 => \time_status_regs[2]\(1), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][1]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][20]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(20), + I1 => \time_status_regs[2]\(20), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][20]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][21]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(21), + I1 => \time_status_regs[2]\(21), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][21]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][22]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(22), + I1 => \time_status_regs[2]\(22), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][22]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][23]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(23), + I1 => \time_status_regs[2]\(23), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][23]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][24]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(24), + I1 => \time_status_regs[2]\(24), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][24]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][25]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(25), + I1 => \time_status_regs[2]\(25), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][25]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][26]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(26), + I1 => \time_status_regs[2]\(26), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][26]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][27]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(27), + I1 => \time_status_regs[2]\(27), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][27]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][28]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(28), + I1 => \time_status_regs[2]\(28), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][28]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][29]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(29), + I1 => \time_status_regs[2]\(29), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][29]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(2), + I1 => \time_status_regs[2]\(2), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][2]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][30]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(30), + I1 => \time_status_regs[2]\(30), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][30]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][31]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(31), + I1 => \time_status_regs[2]\(31), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][31]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(3), + I1 => \time_status_regs[2]\(3), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][3]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(4), + I1 => \time_status_regs[2]\(4), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][4]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(5), + I1 => \time_status_regs[2]\(5), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][5]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(6), + I1 => \time_status_regs[2]\(6), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][6]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(7), + I1 => \time_status_regs[2]\(7), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][7]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(8), + I1 => \time_status_regs[2]\(8), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][8]\ + ); +\GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg[36][9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[3]\(9), + I1 => \time_status_regs[2]\(9), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][9]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(0), + I1 => \time_status_regs[4]\(0), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][0]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(10), + I1 => \time_status_regs[4]\(10), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][11]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(11), + I1 => \time_status_regs[4]\(11), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][11]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][12]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(12), + I1 => \time_status_regs[4]\(12), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][12]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][13]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(13), + I1 => \time_status_regs[4]\(13), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][13]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][14]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(14), + I1 => \time_status_regs[4]\(14), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][14]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][15]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(15), + I1 => \time_status_regs[4]\(15), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][15]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][16]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(16), + I1 => \time_status_regs[4]\(16), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][16]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][17]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(17), + I1 => \time_status_regs[4]\(17), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][17]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][18]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(18), + I1 => \time_status_regs[4]\(18), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][18]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][19]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(19), + I1 => \time_status_regs[4]\(19), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][19]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(1), + I1 => \time_status_regs[4]\(1), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][1]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][20]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(20), + I1 => \time_status_regs[4]\(20), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][20]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][21]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(21), + I1 => \time_status_regs[4]\(21), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][21]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][22]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(22), + I1 => \time_status_regs[4]\(22), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][22]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][23]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(23), + I1 => \time_status_regs[4]\(23), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][23]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][24]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(24), + I1 => \time_status_regs[4]\(24), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][24]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][25]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(25), + I1 => \time_status_regs[4]\(25), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][25]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][26]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(26), + I1 => \time_status_regs[4]\(26), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][26]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][27]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(27), + I1 => \time_status_regs[4]\(27), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][27]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][28]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(28), + I1 => \time_status_regs[4]\(28), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][28]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][29]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(29), + I1 => \time_status_regs[4]\(29), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][29]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(2), + I1 => \time_status_regs[4]\(2), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][2]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][30]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(30), + I1 => \time_status_regs[4]\(30), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][30]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][31]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(31), + I1 => \time_status_regs[4]\(31), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][31]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(3), + I1 => \time_status_regs[4]\(3), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][3]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(4), + I1 => \time_status_regs[4]\(4), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][4]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(5), + I1 => \time_status_regs[4]\(5), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][5]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(6), + I1 => \time_status_regs[4]\(6), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][6]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(7), + I1 => \time_status_regs[4]\(7), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][7]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(8), + I1 => \time_status_regs[4]\(8), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][8]\ + ); +\GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg[37][9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[5]\(9), + I1 => \time_status_regs[4]\(9), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][9]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(0), + I1 => \time_status_regs[6]\(0), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][0]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(10), + I1 => \time_status_regs[6]\(10), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][10]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][11]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(11), + I1 => \time_status_regs[6]\(11), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][11]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][12]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(12), + I1 => \time_status_regs[6]\(12), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][12]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][13]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(13), + I1 => \time_status_regs[6]\(13), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][13]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][14]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(14), + I1 => \time_status_regs[6]\(14), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][14]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][15]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(15), + I1 => \time_status_regs[6]\(15), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][15]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][16]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(16), + I1 => \time_status_regs[6]\(16), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][16]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][17]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(17), + I1 => \time_status_regs[6]\(17), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][17]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][18]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(18), + I1 => \time_status_regs[6]\(18), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][18]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][19]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(19), + I1 => \time_status_regs[6]\(19), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][19]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(1), + I1 => \time_status_regs[6]\(1), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][1]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][20]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(20), + I1 => \time_status_regs[6]\(20), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][20]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][21]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(21), + I1 => \time_status_regs[6]\(21), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][21]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][22]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(22), + I1 => \time_status_regs[6]\(22), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][22]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][23]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(23), + I1 => \time_status_regs[6]\(23), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][23]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][24]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(24), + I1 => \time_status_regs[6]\(24), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][24]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][25]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(25), + I1 => \time_status_regs[6]\(25), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][25]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][26]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(26), + I1 => \time_status_regs[6]\(26), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][26]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][27]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(27), + I1 => \time_status_regs[6]\(27), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][27]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][28]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(28), + I1 => \time_status_regs[6]\(28), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][28]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][29]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(29), + I1 => \time_status_regs[6]\(29), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][29]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(2), + I1 => \time_status_regs[6]\(2), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][2]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][30]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(30), + I1 => \time_status_regs[6]\(30), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][30]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(31), + I1 => \time_status_regs[6]\(31), + I2 => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][31]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \data_sync[2]_2\(34), + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][31]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(3), + I1 => \time_status_regs[6]\(3), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][3]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(4), + I1 => \time_status_regs[6]\(4), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][4]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(5), + I1 => \time_status_regs[6]\(5), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][5]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(6), + I1 => \time_status_regs[6]\(6), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][6]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(7), + I1 => \time_status_regs[6]\(7), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][7]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(8), + I1 => \time_status_regs[6]\(8), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][8]\ + ); +\GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg[38][9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[7]\(9), + I1 => \time_status_regs[6]\(9), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][9]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(0), + I1 => \time_status_regs[8]\(0), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][0]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(10), + I1 => \time_status_regs[8]\(10), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][10]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][11]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(11), + I1 => \time_status_regs[8]\(11), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][11]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][12]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(12), + I1 => \time_status_regs[8]\(12), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][12]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][13]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(13), + I1 => \time_status_regs[8]\(13), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][13]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][14]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(14), + I1 => \time_status_regs[8]\(14), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][14]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][15]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(15), + I1 => \time_status_regs[8]\(15), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][15]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][16]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(16), + I1 => \time_status_regs[8]\(16), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][16]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][17]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(17), + I1 => \time_status_regs[8]\(17), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][17]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][18]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(18), + I1 => \time_status_regs[8]\(18), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][18]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][19]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(19), + I1 => \time_status_regs[8]\(19), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][19]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(1), + I1 => \time_status_regs[8]\(1), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][1]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][20]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(20), + I1 => \time_status_regs[8]\(20), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][20]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][21]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(21), + I1 => \time_status_regs[8]\(21), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][21]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][22]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(22), + I1 => \time_status_regs[8]\(22), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][22]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][23]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(23), + I1 => \time_status_regs[8]\(23), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][23]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][24]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(24), + I1 => \time_status_regs[8]\(24), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][24]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][25]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(25), + I1 => \time_status_regs[8]\(25), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][25]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][26]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(26), + I1 => \time_status_regs[8]\(26), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][26]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][27]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(27), + I1 => \time_status_regs[8]\(27), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][27]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][28]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(28), + I1 => \time_status_regs[8]\(28), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][28]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][29]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(29), + I1 => \time_status_regs[8]\(29), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][29]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(2), + I1 => \time_status_regs[8]\(2), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][2]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][30]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(30), + I1 => \time_status_regs[8]\(30), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][30]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][31]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(31), + I1 => \time_status_regs[8]\(31), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][31]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(3), + I1 => \time_status_regs[8]\(3), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][3]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(4), + I1 => \time_status_regs[8]\(4), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][4]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(5), + I1 => \time_status_regs[8]\(5), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][5]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(6), + I1 => \time_status_regs[8]\(6), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][6]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(7), + I1 => \time_status_regs[8]\(7), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][7]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(8), + I1 => \time_status_regs[8]\(8), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][8]\ + ); +\GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg[39][9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[9]\(9), + I1 => \time_status_regs[8]\(9), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][9]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(0), + I1 => \time_status_regs[10]\(0), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][0]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(10), + I1 => \time_status_regs[10]\(10), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][10]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][11]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(11), + I1 => \time_status_regs[10]\(11), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][11]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][12]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(12), + I1 => \time_status_regs[10]\(12), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][12]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][13]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(13), + I1 => \time_status_regs[10]\(13), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][13]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][14]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(14), + I1 => \time_status_regs[10]\(14), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][14]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][15]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(15), + I1 => \time_status_regs[10]\(15), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][15]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][16]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(16), + I1 => \time_status_regs[10]\(16), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][16]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][17]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(17), + I1 => \time_status_regs[10]\(17), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][17]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][18]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(18), + I1 => \time_status_regs[10]\(18), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][18]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][19]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(19), + I1 => \time_status_regs[10]\(19), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][19]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(1), + I1 => \time_status_regs[10]\(1), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][1]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][20]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(20), + I1 => \time_status_regs[10]\(20), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][20]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][21]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(21), + I1 => \time_status_regs[10]\(21), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][21]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][22]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(22), + I1 => \time_status_regs[10]\(22), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][22]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][23]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(23), + I1 => \time_status_regs[10]\(23), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][23]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][24]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(24), + I1 => \time_status_regs[10]\(24), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][24]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][25]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(25), + I1 => \time_status_regs[10]\(25), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][25]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][26]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(26), + I1 => \time_status_regs[10]\(26), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][26]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][27]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(27), + I1 => \time_status_regs[10]\(27), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][27]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][28]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(28), + I1 => \time_status_regs[10]\(28), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][28]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][29]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(29), + I1 => \time_status_regs[10]\(29), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][29]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(2), + I1 => \time_status_regs[10]\(2), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][2]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][30]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(30), + I1 => \time_status_regs[10]\(30), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][30]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][31]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(31), + I1 => \time_status_regs[10]\(31), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][31]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(3), + I1 => \time_status_regs[10]\(3), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][3]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(4), + I1 => \time_status_regs[10]\(4), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][4]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(5), + I1 => \time_status_regs[10]\(5), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][5]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(6), + I1 => \time_status_regs[10]\(6), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][6]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(7), + I1 => \time_status_regs[10]\(7), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][7]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(8), + I1 => \time_status_regs[10]\(8), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][8]\ + ); +\GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg[40][9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[11]\(9), + I1 => \time_status_regs[10]\(9), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][9]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(0), + I1 => \time_status_regs[12]\(0), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][0]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(10), + I1 => \time_status_regs[12]\(10), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][10]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][11]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(11), + I1 => \time_status_regs[12]\(11), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][11]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][12]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(12), + I1 => \time_status_regs[12]\(12), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][12]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][13]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(13), + I1 => \time_status_regs[12]\(13), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][13]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][14]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(14), + I1 => \time_status_regs[12]\(14), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][14]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][15]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(15), + I1 => \time_status_regs[12]\(15), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][15]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][16]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(16), + I1 => \time_status_regs[12]\(16), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][16]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][17]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(17), + I1 => \time_status_regs[12]\(17), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][17]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][18]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(18), + I1 => \time_status_regs[12]\(18), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][18]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][19]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(19), + I1 => \time_status_regs[12]\(19), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][19]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(1), + I1 => \time_status_regs[12]\(1), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][1]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][20]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(20), + I1 => \time_status_regs[12]\(20), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][20]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][21]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(21), + I1 => \time_status_regs[12]\(21), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][21]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][22]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(22), + I1 => \time_status_regs[12]\(22), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][22]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][23]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(23), + I1 => \time_status_regs[12]\(23), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][23]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][24]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(24), + I1 => \time_status_regs[12]\(24), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][24]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][25]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(25), + I1 => \time_status_regs[12]\(25), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][25]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][26]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(26), + I1 => \time_status_regs[12]\(26), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][26]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][27]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(27), + I1 => \time_status_regs[12]\(27), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][27]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][28]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(28), + I1 => \time_status_regs[12]\(28), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][28]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][29]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(29), + I1 => \time_status_regs[12]\(29), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][29]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(2), + I1 => \time_status_regs[12]\(2), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][2]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][30]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(30), + I1 => \time_status_regs[12]\(30), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][30]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][31]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(31), + I1 => \time_status_regs[12]\(31), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][31]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(3), + I1 => \time_status_regs[12]\(3), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][3]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(4), + I1 => \time_status_regs[12]\(4), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][4]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(5), + I1 => \time_status_regs[12]\(5), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][5]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(6), + I1 => \time_status_regs[12]\(6), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][6]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(7), + I1 => \time_status_regs[12]\(7), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][7]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(8), + I1 => \time_status_regs[12]\(8), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][8]\ + ); +\GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg[41][9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[13]\(9), + I1 => \time_status_regs[12]\(9), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][9]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(0), + I1 => \time_status_regs[14]\(0), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][0]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(10), + I1 => \time_status_regs[14]\(10), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][10]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][11]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(11), + I1 => \time_status_regs[14]\(11), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][11]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][12]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(12), + I1 => \time_status_regs[14]\(12), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][12]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][13]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(13), + I1 => \time_status_regs[14]\(13), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][13]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][14]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(14), + I1 => \time_status_regs[14]\(14), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][14]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][15]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(15), + I1 => \time_status_regs[14]\(15), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][15]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][16]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(16), + I1 => \time_status_regs[14]\(16), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][16]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][17]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(17), + I1 => \time_status_regs[14]\(17), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][17]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][18]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(18), + I1 => \time_status_regs[14]\(18), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][18]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][19]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(19), + I1 => \time_status_regs[14]\(19), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][19]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(1), + I1 => \time_status_regs[14]\(1), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][1]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][20]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(20), + I1 => \time_status_regs[14]\(20), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][20]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][21]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(21), + I1 => \time_status_regs[14]\(21), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][21]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][22]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(22), + I1 => \time_status_regs[14]\(22), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][22]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][23]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(23), + I1 => \time_status_regs[14]\(23), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][23]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][24]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(24), + I1 => \time_status_regs[14]\(24), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][24]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][25]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(25), + I1 => \time_status_regs[14]\(25), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][25]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][26]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(26), + I1 => \time_status_regs[14]\(26), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][26]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][27]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(27), + I1 => \time_status_regs[14]\(27), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][27]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][28]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(28), + I1 => \time_status_regs[14]\(28), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][28]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][29]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(29), + I1 => \time_status_regs[14]\(29), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][29]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(2), + I1 => \time_status_regs[14]\(2), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][2]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][30]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(30), + I1 => \time_status_regs[14]\(30), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][30]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(31), + I1 => \time_status_regs[14]\(31), + I2 => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][31]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \data_sync[2]_2\(34), + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][31]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(3), + I1 => \time_status_regs[14]\(3), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][3]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(4), + I1 => \time_status_regs[14]\(4), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][4]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(5), + I1 => \time_status_regs[14]\(5), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][5]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(6), + I1 => \time_status_regs[14]\(6), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][6]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(7), + I1 => \time_status_regs[14]\(7), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][7]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(8), + I1 => \time_status_regs[14]\(8), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][8]\ + ); +\GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg[42][9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[15]\(9), + I1 => \time_status_regs[14]\(9), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][9]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(0), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(0), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][0]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(10), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(10), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][10]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][11]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(11), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(11), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][11]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][12]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(12), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(12), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][12]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][13]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(13), + I1 => \time_status_regs[16]\(0), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][13]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][14]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(14), + I1 => \time_status_regs[16]\(1), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][14]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][15]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(15), + I1 => \time_status_regs[16]\(2), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][15]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][16]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(16), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(13), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][16]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][17]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(17), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(14), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][17]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][18]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(18), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(15), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][18]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][19]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(19), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(16), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][19]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(1), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(1), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][1]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][20]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(20), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(17), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][20]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][21]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(21), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(18), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][21]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][22]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(22), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(19), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][22]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][23]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(23), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(20), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][23]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][24]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(24), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(21), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][24]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][25]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(25), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(22), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][25]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][26]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(26), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(23), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][26]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][27]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(27), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(24), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][27]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][28]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(28), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(25), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][28]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][29]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(29), + I1 => \time_status_regs[16]\(3), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][29]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(2), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(2), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][2]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][30]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(30), + I1 => \time_status_regs[16]\(4), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][30]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][31]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(31), + I1 => \time_status_regs[16]\(5), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][31]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(3), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(3), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][3]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(4), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(4), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][4]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(5), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(5), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][5]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(6), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(6), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][6]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(7), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(7), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][7]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(8), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(8), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][8]\ + ); +\GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg[43][9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[17]\(9), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(9), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][9]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6]\(0), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9]\(0), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][0]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[19]\(3), + I1 => \time_status_regs[18]\(2), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][10]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][11]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[19]\(4), + I1 => \time_status_regs[18]\(3), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][11]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][12]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[19]\(5), + I1 => \time_status_regs[18]\(4), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][12]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][13]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[19]\(6), + I1 => \time_status_regs[18]\(5), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][13]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][14]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[19]\(7), + I1 => \time_status_regs[18]\(6), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][14]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][15]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[19]\(8), + I1 => \time_status_regs[18]\(7), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][15]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][16]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[19]\(9), + I1 => \time_status_regs[18]\(8), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][16]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][17]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[19]\(10), + I1 => \time_status_regs[18]\(9), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][17]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][18]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[19]\(11), + I1 => \time_status_regs[18]\(10), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][18]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][19]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[19]\(12), + I1 => \time_status_regs[18]\(11), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][19]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6]\(1), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9]\(1), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][1]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][20]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[19]\(13), + I1 => \time_status_regs[18]\(12), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][20]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][21]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[19]\(14), + I1 => \time_status_regs[18]\(13), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][21]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][22]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[19]\(15), + I1 => \time_status_regs[18]\(14), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][22]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][23]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[19]\(16), + I1 => \time_status_regs[18]\(15), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][23]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][24]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[19]\(17), + I1 => \time_status_regs[18]\(16), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][24]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][25]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[19]\(18), + I1 => \time_status_regs[18]\(17), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][25]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][26]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[19]\(19), + I1 => \time_status_regs[18]\(18), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][26]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][27]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[19]\(20), + I1 => \time_status_regs[18]\(19), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][27]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][28]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[19]\(21), + I1 => \time_status_regs[18]\(20), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][28]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][29]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[19]\(22), + I1 => \time_status_regs[18]\(21), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][29]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6]\(2), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9]\(2), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][2]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][30]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[19]\(23), + I1 => \time_status_regs[18]\(22), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][30]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][31]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[19]\(24), + I1 => \time_status_regs[18]\(23), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][31]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6]\(3), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9]\(3), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][3]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6]\(4), + I1 => \time_status_regs[18]\(0), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][4]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6]\(5), + I1 => \time_status_regs[18]\(1), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][5]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6]\(6), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9]\(4), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][6]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[19]\(0), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9]\(5), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][7]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[19]\(1), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9]\(6), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][8]\ + ); +\GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg[44][9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[19]\(2), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9]\(7), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][9]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\(0), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\(0), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][0]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\(10), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\(10), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][10]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][11]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\(11), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\(11), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][11]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][12]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\(12), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\(12), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][12]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][13]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[21]\(0), + I1 => \time_status_regs[20]\(0), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][13]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][14]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[21]\(1), + I1 => \time_status_regs[20]\(1), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][14]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][15]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[21]\(2), + I1 => \time_status_regs[20]\(2), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][15]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][16]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\(13), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\(13), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][16]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][17]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\(14), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\(14), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][17]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][18]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\(15), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\(15), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][18]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][19]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\(16), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\(16), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][19]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\(1), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\(1), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][1]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][20]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\(17), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\(17), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][20]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][21]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\(18), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\(18), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][21]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][22]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\(19), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\(19), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][22]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][23]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\(20), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\(20), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][23]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][24]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\(21), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\(21), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][24]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][25]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\(22), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\(22), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][25]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][26]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\(23), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\(23), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][26]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][27]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\(24), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\(24), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][27]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][28]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\(25), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\(25), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][28]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][29]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[21]\(3), + I1 => \time_status_regs[20]\(3), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][29]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\(2), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\(2), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][2]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][30]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[21]\(4), + I1 => \time_status_regs[20]\(4), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][30]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[21]\(5), + I1 => \time_status_regs[20]\(5), + I2 => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][31]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \data_sync[2]_2\(34), + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][31]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\(3), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\(3), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][3]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\(4), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\(4), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][4]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\(5), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\(5), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][5]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\(6), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\(6), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][6]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\(7), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\(7), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][7]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\(8), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\(8), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][8]\ + ); +\GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg[45][9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\(9), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\(9), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][9]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\(0), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\(0), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][0]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\(10), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\(10), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][10]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][11]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\(11), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\(11), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][11]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][12]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\(12), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\(12), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][12]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][13]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[23]\(0), + I1 => \time_status_regs[22]\(0), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][13]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][14]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[23]\(1), + I1 => \time_status_regs[22]\(1), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][14]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][15]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[23]\(2), + I1 => \time_status_regs[22]\(2), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][15]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][16]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\(13), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\(13), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][16]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][17]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\(14), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\(14), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][17]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][18]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\(15), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\(15), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][18]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][19]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\(16), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\(16), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][19]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\(1), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\(1), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][1]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][20]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\(17), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\(17), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][20]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][21]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\(18), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\(18), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][21]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][22]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\(19), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\(19), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][22]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][23]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\(20), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\(20), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][23]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][24]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\(21), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\(21), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][24]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][25]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\(22), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\(22), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][25]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][26]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\(23), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\(23), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][26]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][27]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\(24), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\(24), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][27]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][28]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\(25), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\(25), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][28]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][29]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[23]\(3), + I1 => \time_status_regs[22]\(3), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][29]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\(2), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\(2), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][2]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][30]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[23]\(4), + I1 => \time_status_regs[22]\(4), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][30]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][31]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[23]\(5), + I1 => \time_status_regs[22]\(5), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][31]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\(3), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\(3), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][3]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\(4), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\(4), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][4]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\(5), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\(5), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][5]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\(6), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\(6), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][6]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\(7), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\(7), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][7]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\(8), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\(8), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][8]\ + ); +\GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg[46][9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\(9), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\(9), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][9]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\(0), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\(0), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][0]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\(10), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\(10), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][10]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][11]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\(11), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\(11), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][11]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][12]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\(12), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\(12), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][12]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][13]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[25]\(0), + I1 => \time_status_regs[24]\(0), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][13]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][14]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[25]\(1), + I1 => \time_status_regs[24]\(1), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][14]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][15]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[25]\(2), + I1 => \time_status_regs[24]\(2), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][15]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][16]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\(13), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\(13), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][16]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][17]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\(14), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\(14), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][17]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][18]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\(15), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\(15), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][18]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][19]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\(16), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\(16), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][19]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\(1), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\(1), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][1]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][20]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\(17), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\(17), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][20]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][21]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\(18), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\(18), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][21]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][22]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\(19), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\(19), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][22]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][23]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\(20), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\(20), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][23]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][24]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\(21), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\(21), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][24]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][25]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\(22), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\(22), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][25]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][26]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\(23), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\(23), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][26]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][27]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\(24), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\(24), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][27]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][28]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\(25), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\(25), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][28]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][29]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[25]\(3), + I1 => \time_status_regs[24]\(3), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][29]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\(2), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\(2), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][2]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][30]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[25]\(4), + I1 => \time_status_regs[24]\(4), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][30]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][31]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[25]\(5), + I1 => \time_status_regs[24]\(5), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][31]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\(3), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\(3), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][3]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\(4), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\(4), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][4]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\(5), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\(5), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][5]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\(6), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\(6), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][6]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\(7), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\(7), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][7]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\(8), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\(8), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][8]\ + ); +\GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg[47][9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\(9), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\(9), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][9]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(0), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\(0), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][0]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(10), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\(10), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][10]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][11]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(11), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\(11), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][11]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][12]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(12), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\(12), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][12]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][13]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[27]\(0), + I1 => \time_status_regs[26]\(0), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][13]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][14]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[27]\(1), + I1 => \time_status_regs[26]\(1), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][14]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][15]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[27]\(2), + I1 => \time_status_regs[26]\(2), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][15]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][16]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(13), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\(13), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][16]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][17]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(14), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\(14), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][17]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][18]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(15), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\(15), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][18]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][19]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(16), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\(16), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][19]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(1), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\(1), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][1]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][20]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(17), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\(17), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][20]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][21]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(18), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\(18), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][21]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][22]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(19), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\(19), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][22]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][23]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(20), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\(20), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][23]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][24]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(21), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\(21), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][24]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][25]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(22), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\(22), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][25]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][26]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(23), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\(23), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][26]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][27]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(24), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\(24), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][27]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][28]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(25), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\(25), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][28]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][29]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[27]\(3), + I1 => \time_status_regs[26]\(3), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][29]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(2), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\(2), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][2]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][30]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[27]\(4), + I1 => \time_status_regs[26]\(4), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][30]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \time_status_regs[27]\(5), + I1 => \time_status_regs[26]\(5), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][31]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \data_sync[2]_2\(34), + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(3), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\(3), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][3]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(4), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\(4), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][4]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(5), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\(5), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][5]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(6), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\(6), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][6]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(7), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\(7), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][7]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(8), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\(8), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][8]\ + ); +\GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(9), + I1 => \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\(9), + I2 => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg[48][31]_i_2_n_0\, + O => \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][9]\ + ); +\data_sync_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(0), + Q => \data_sync[0]_0\(0), + R => '0' + ); +\data_sync_reg[0][10]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(10), + Q => \data_sync[0]_0\(10), + R => '0' + ); +\data_sync_reg[0][11]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(11), + Q => \data_sync[0]_0\(11), + R => '0' + ); +\data_sync_reg[0][12]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(12), + Q => \data_sync[0]_0\(12), + R => '0' + ); +\data_sync_reg[0][13]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(13), + Q => \data_sync[0]_0\(13), + R => '0' + ); +\data_sync_reg[0][14]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(14), + Q => \data_sync[0]_0\(14), + R => '0' + ); +\data_sync_reg[0][15]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(15), + Q => \data_sync[0]_0\(15), + R => '0' + ); +\data_sync_reg[0][16]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(16), + Q => \data_sync[0]_0\(16), + R => '0' + ); +\data_sync_reg[0][17]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(17), + Q => \data_sync[0]_0\(17), + R => '0' + ); +\data_sync_reg[0][18]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(18), + Q => \data_sync[0]_0\(18), + R => '0' + ); +\data_sync_reg[0][19]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(19), + Q => \data_sync[0]_0\(19), + R => '0' + ); +\data_sync_reg[0][1]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(1), + Q => \data_sync[0]_0\(1), + R => '0' + ); +\data_sync_reg[0][20]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(20), + Q => \data_sync[0]_0\(20), + R => '0' + ); +\data_sync_reg[0][21]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(21), + Q => \data_sync[0]_0\(21), + R => '0' + ); +\data_sync_reg[0][22]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(22), + Q => \data_sync[0]_0\(22), + R => '0' + ); +\data_sync_reg[0][23]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(23), + Q => \data_sync[0]_0\(23), + R => '0' + ); +\data_sync_reg[0][24]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(24), + Q => \data_sync[0]_0\(24), + R => '0' + ); +\data_sync_reg[0][25]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(25), + Q => \data_sync[0]_0\(25), + R => '0' + ); +\data_sync_reg[0][26]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(26), + Q => \data_sync[0]_0\(26), + R => '0' + ); +\data_sync_reg[0][27]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(27), + Q => \data_sync[0]_0\(27), + R => '0' + ); +\data_sync_reg[0][28]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(28), + Q => \data_sync[0]_0\(28), + R => '0' + ); +\data_sync_reg[0][29]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(29), + Q => \data_sync[0]_0\(29), + R => '0' + ); +\data_sync_reg[0][2]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(2), + Q => \data_sync[0]_0\(2), + R => '0' + ); +\data_sync_reg[0][30]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(30), + Q => \data_sync[0]_0\(30), + R => '0' + ); +\data_sync_reg[0][31]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(31), + Q => \data_sync[0]_0\(31), + R => '0' + ); +\data_sync_reg[0][32]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(32), + Q => \data_sync[0]_0\(32), + R => '0' + ); +\data_sync_reg[0][33]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(33), + Q => \data_sync[0]_0\(33), + R => '0' + ); +\data_sync_reg[0][34]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(34), + Q => \data_sync[0]_0\(34), + R => '0' + ); +\data_sync_reg[0][35]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(35), + Q => \data_sync[0]_0\(35), + R => '0' + ); +\data_sync_reg[0][36]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(36), + Q => \data_sync[0]_0\(36), + R => '0' + ); +\data_sync_reg[0][37]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(37), + Q => \data_sync[0]_0\(37), + R => '0' + ); +\data_sync_reg[0][38]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(38), + Q => \data_sync[0]_0\(38), + R => '0' + ); +\data_sync_reg[0][39]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(39), + Q => \data_sync[0]_0\(39), + R => '0' + ); +\data_sync_reg[0][3]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(3), + Q => \data_sync[0]_0\(3), + R => '0' + ); +\data_sync_reg[0][40]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(40), + Q => \data_sync[0]_0\(40), + R => '0' + ); +\data_sync_reg[0][41]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(41), + Q => \data_sync[0]_0\(41), + R => '0' + ); +\data_sync_reg[0][42]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(42), + Q => \data_sync[0]_0\(42), + R => '0' + ); +\data_sync_reg[0][43]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(43), + Q => \data_sync[0]_0\(43), + R => '0' + ); +\data_sync_reg[0][44]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(44), + Q => \data_sync[0]_0\(44), + R => '0' + ); +\data_sync_reg[0][4]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(4), + Q => \data_sync[0]_0\(4), + R => '0' + ); +\data_sync_reg[0][5]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(5), + Q => \data_sync[0]_0\(5), + R => '0' + ); +\data_sync_reg[0][6]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(6), + Q => \data_sync[0]_0\(6), + R => '0' + ); +\data_sync_reg[0][7]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(7), + Q => \data_sync[0]_0\(7), + R => '0' + ); +\data_sync_reg[0][8]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(8), + Q => \data_sync[0]_0\(8), + R => '0' + ); +\data_sync_reg[0][9]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(9), + Q => \data_sync[0]_0\(9), + R => '0' + ); +\data_sync_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(0), + Q => \data_sync[1]_1\(0), + R => '0' + ); +\data_sync_reg[1][10]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(10), + Q => \data_sync[1]_1\(10), + R => '0' + ); +\data_sync_reg[1][11]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(11), + Q => \data_sync[1]_1\(11), + R => '0' + ); +\data_sync_reg[1][12]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(12), + Q => \data_sync[1]_1\(12), + R => '0' + ); +\data_sync_reg[1][13]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(13), + Q => \data_sync[1]_1\(13), + R => '0' + ); +\data_sync_reg[1][14]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(14), + Q => \data_sync[1]_1\(14), + R => '0' + ); +\data_sync_reg[1][15]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(15), + Q => \data_sync[1]_1\(15), + R => '0' + ); +\data_sync_reg[1][16]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(16), + Q => \data_sync[1]_1\(16), + R => '0' + ); +\data_sync_reg[1][17]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(17), + Q => \data_sync[1]_1\(17), + R => '0' + ); +\data_sync_reg[1][18]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(18), + Q => \data_sync[1]_1\(18), + R => '0' + ); +\data_sync_reg[1][19]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(19), + Q => \data_sync[1]_1\(19), + R => '0' + ); +\data_sync_reg[1][1]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(1), + Q => \data_sync[1]_1\(1), + R => '0' + ); +\data_sync_reg[1][20]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(20), + Q => \data_sync[1]_1\(20), + R => '0' + ); +\data_sync_reg[1][21]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(21), + Q => \data_sync[1]_1\(21), + R => '0' + ); +\data_sync_reg[1][22]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(22), + Q => \data_sync[1]_1\(22), + R => '0' + ); +\data_sync_reg[1][23]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(23), + Q => \data_sync[1]_1\(23), + R => '0' + ); +\data_sync_reg[1][24]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(24), + Q => \data_sync[1]_1\(24), + R => '0' + ); +\data_sync_reg[1][25]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(25), + Q => \data_sync[1]_1\(25), + R => '0' + ); +\data_sync_reg[1][26]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(26), + Q => \data_sync[1]_1\(26), + R => '0' + ); +\data_sync_reg[1][27]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(27), + Q => \data_sync[1]_1\(27), + R => '0' + ); +\data_sync_reg[1][28]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(28), + Q => \data_sync[1]_1\(28), + R => '0' + ); +\data_sync_reg[1][29]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(29), + Q => \data_sync[1]_1\(29), + R => '0' + ); +\data_sync_reg[1][2]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(2), + Q => \data_sync[1]_1\(2), + R => '0' + ); +\data_sync_reg[1][30]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(30), + Q => \data_sync[1]_1\(30), + R => '0' + ); +\data_sync_reg[1][31]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(31), + Q => \data_sync[1]_1\(31), + R => '0' + ); +\data_sync_reg[1][32]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(32), + Q => \data_sync[1]_1\(32), + R => '0' + ); +\data_sync_reg[1][33]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(33), + Q => \data_sync[1]_1\(33), + R => '0' + ); +\data_sync_reg[1][34]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(34), + Q => \data_sync[1]_1\(34), + R => '0' + ); +\data_sync_reg[1][35]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(35), + Q => \data_sync[1]_1\(35), + R => '0' + ); +\data_sync_reg[1][36]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(36), + Q => \data_sync[1]_1\(36), + R => '0' + ); +\data_sync_reg[1][37]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(37), + Q => \data_sync[1]_1\(37), + R => '0' + ); +\data_sync_reg[1][38]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(38), + Q => \data_sync[1]_1\(38), + R => '0' + ); +\data_sync_reg[1][39]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(39), + Q => \data_sync[1]_1\(39), + R => '0' + ); +\data_sync_reg[1][3]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(3), + Q => \data_sync[1]_1\(3), + R => '0' + ); +\data_sync_reg[1][40]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(40), + Q => \data_sync[1]_1\(40), + R => '0' + ); +\data_sync_reg[1][41]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(41), + Q => \data_sync[1]_1\(41), + R => '0' + ); +\data_sync_reg[1][42]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(42), + Q => \data_sync[1]_1\(42), + R => '0' + ); +\data_sync_reg[1][43]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(43), + Q => \data_sync[1]_1\(43), + R => '0' + ); +\data_sync_reg[1][44]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(44), + Q => \data_sync[1]_1\(44), + R => '0' + ); +\data_sync_reg[1][4]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(4), + Q => \data_sync[1]_1\(4), + R => '0' + ); +\data_sync_reg[1][5]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(5), + Q => \data_sync[1]_1\(5), + R => '0' + ); +\data_sync_reg[1][6]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(6), + Q => \data_sync[1]_1\(6), + R => '0' + ); +\data_sync_reg[1][7]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(7), + Q => \data_sync[1]_1\(7), + R => '0' + ); +\data_sync_reg[1][8]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(8), + Q => \data_sync[1]_1\(8), + R => '0' + ); +\data_sync_reg[1][9]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[0]_0\(9), + Q => \data_sync[1]_1\(9), + R => '0' + ); +\data_sync_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(0), + Q => \data_sync[2]_2\(0), + R => '0' + ); +\data_sync_reg[2][10]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(10), + Q => \data_sync[2]_2\(10), + R => '0' + ); +\data_sync_reg[2][11]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(11), + Q => \data_sync[2]_2\(11), + R => '0' + ); +\data_sync_reg[2][12]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(12), + Q => \data_sync[2]_2\(12), + R => '0' + ); +\data_sync_reg[2][13]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(13), + Q => \data_sync[2]_2\(13), + R => '0' + ); +\data_sync_reg[2][14]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(14), + Q => \data_sync[2]_2\(14), + R => '0' + ); +\data_sync_reg[2][15]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(15), + Q => \data_sync[2]_2\(15), + R => '0' + ); +\data_sync_reg[2][16]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(16), + Q => \data_sync[2]_2\(16), + R => '0' + ); +\data_sync_reg[2][17]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(17), + Q => \data_sync[2]_2\(17), + R => '0' + ); +\data_sync_reg[2][18]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(18), + Q => \data_sync[2]_2\(18), + R => '0' + ); +\data_sync_reg[2][19]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(19), + Q => \data_sync[2]_2\(19), + R => '0' + ); +\data_sync_reg[2][1]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(1), + Q => \data_sync[2]_2\(1), + R => '0' + ); +\data_sync_reg[2][20]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(20), + Q => \data_sync[2]_2\(20), + R => '0' + ); +\data_sync_reg[2][21]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(21), + Q => \data_sync[2]_2\(21), + R => '0' + ); +\data_sync_reg[2][22]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(22), + Q => \data_sync[2]_2\(22), + R => '0' + ); +\data_sync_reg[2][23]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(23), + Q => \data_sync[2]_2\(23), + R => '0' + ); +\data_sync_reg[2][24]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(24), + Q => \data_sync[2]_2\(24), + R => '0' + ); +\data_sync_reg[2][25]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(25), + Q => \data_sync[2]_2\(25), + R => '0' + ); +\data_sync_reg[2][26]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(26), + Q => \data_sync[2]_2\(26), + R => '0' + ); +\data_sync_reg[2][27]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(27), + Q => \data_sync[2]_2\(27), + R => '0' + ); +\data_sync_reg[2][28]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(28), + Q => \data_sync[2]_2\(28), + R => '0' + ); +\data_sync_reg[2][29]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(29), + Q => \data_sync[2]_2\(29), + R => '0' + ); +\data_sync_reg[2][2]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(2), + Q => \data_sync[2]_2\(2), + R => '0' + ); +\data_sync_reg[2][30]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(30), + Q => \data_sync[2]_2\(30), + R => '0' + ); +\data_sync_reg[2][31]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(31), + Q => \data_sync[2]_2\(31), + R => '0' + ); +\data_sync_reg[2][32]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(32), + Q => \data_sync[2]_2\(32), + R => '0' + ); +\data_sync_reg[2][33]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(33), + Q => \data_sync[2]_2\(33), + R => '0' + ); +\data_sync_reg[2][34]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(34), + Q => \data_sync[2]_2\(34), + R => '0' + ); +\data_sync_reg[2][35]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(35), + Q => \data_sync[2]_2\(35), + R => '0' + ); +\data_sync_reg[2][36]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(36), + Q => \data_sync[2]_2\(36), + R => '0' + ); +\data_sync_reg[2][37]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(37), + Q => \data_sync[2]_2\(37), + R => '0' + ); +\data_sync_reg[2][38]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(38), + Q => \data_sync[2]_2\(38), + R => '0' + ); +\data_sync_reg[2][39]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(39), + Q => \data_sync[2]_2\(39), + R => '0' + ); +\data_sync_reg[2][3]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(3), + Q => \data_sync[2]_2\(3), + R => '0' + ); +\data_sync_reg[2][40]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(40), + Q => \data_sync[2]_2\(40), + R => '0' + ); +\data_sync_reg[2][41]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(41), + Q => \data_sync[2]_2\(41), + R => '0' + ); +\data_sync_reg[2][42]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(42), + Q => \data_sync[2]_2\(42), + R => '0' + ); +\data_sync_reg[2][43]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(43), + Q => \data_sync[2]_2\(43), + R => '0' + ); +\data_sync_reg[2][44]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(44), + Q => \data_sync[2]_2\(44), + R => '0' + ); +\data_sync_reg[2][4]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(4), + Q => \data_sync[2]_2\(4), + R => '0' + ); +\data_sync_reg[2][5]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(5), + Q => \data_sync[2]_2\(5), + R => '0' + ); +\data_sync_reg[2][6]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(6), + Q => \data_sync[2]_2\(6), + R => '0' + ); +\data_sync_reg[2][7]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(7), + Q => \data_sync[2]_2\(7), + R => '0' + ); +\data_sync_reg[2][8]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(8), + Q => \data_sync[2]_2\(8), + R => '0' + ); +\data_sync_reg[2][9]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => '1', + D => \data_sync[1]_1\(9), + Q => \data_sync[2]_2\(9), + R => '0' + ); +\ipif_Addr_inferred__0_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \data_sync[2]_2\(40), + O => \^ipif_addr\(8) + ); +\ipif_Addr_inferred__0_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \data_sync[2]_2\(39), + O => \^ipif_addr\(7) + ); +\ipif_Addr_inferred__0_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \data_sync[2]_2\(38), + O => \^ipif_addr\(6) + ); +\ipif_Addr_inferred__0_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \data_sync[2]_2\(37), + O => \^ipif_addr\(5) + ); +\ipif_Addr_inferred__0_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \data_sync[2]_2\(36), + O => \^ipif_addr\(4) + ); +\ipif_Addr_inferred__0_i_6\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \data_sync[2]_2\(35), + O => \^ipif_addr\(3) + ); +\ipif_Addr_inferred__0_i_7\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \data_sync[2]_2\(34), + O => \^ipif_addr\(2) + ); +\ipif_Addr_inferred__0_i_8\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \data_sync[2]_2\(33), + O => \^ipif_addr\(1) + ); +\ipif_Addr_inferred__0_i_9\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \data_sync[2]_2\(32), + O => \^ipif_addr\(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_tc_1_0_video_clock_cross__parameterized0\ is + port ( + p_526_out : out STD_LOGIC; + out_data : out STD_LOGIC_VECTOR ( 33 downto 0 ); + p_528_out : out STD_LOGIC; + \AXI4_LITE_INTERFACE.ipif_Error_reg\ : out STD_LOGIC; + write_ack_d2 : in STD_LOGIC; + write_ack_d1 : in STD_LOGIC; + read_ack_d2 : in STD_LOGIC; + read_ack_d1 : in STD_LOGIC; + in_data : in STD_LOGIC_VECTOR ( 33 downto 0 ); + aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_tc_1_0_video_clock_cross__parameterized0\ : entity is "video_clock_cross"; +end \Arty_Z7_20_v_tc_1_0_video_clock_cross__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_v_tc_1_0_video_clock_cross__parameterized0\ is + signal \data_sync[0]_0\ : STD_LOGIC_VECTOR ( 33 downto 0 ); + attribute async_reg : string; + attribute async_reg of \data_sync[0]_0\ : signal is "true"; + attribute shift_extract : string; + attribute shift_extract of \data_sync[0]_0\ : signal is "NO"; + attribute shreg_extract : string; + attribute shreg_extract of \data_sync[0]_0\ : signal is "no"; + signal \data_sync[1]_1\ : STD_LOGIC_VECTOR ( 33 downto 0 ); + attribute async_reg of \data_sync[1]_1\ : signal is "true"; + attribute shift_extract of \data_sync[1]_1\ : signal is "NO"; + attribute shreg_extract of \data_sync[1]_1\ : signal is "no"; + signal \data_sync[2]_2\ : STD_LOGIC_VECTOR ( 33 downto 0 ); + attribute async_reg of \data_sync[2]_2\ : signal is "true"; + attribute shift_extract of \data_sync[2]_2\ : signal is "NO"; + attribute shreg_extract of \data_sync[2]_2\ : signal is "no"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \data_sync_reg[0][0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \data_sync_reg[0][0]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][0]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][10]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][10]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][10]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][11]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][11]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][11]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][12]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][12]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][12]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][13]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][13]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][13]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][14]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][14]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][14]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][15]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][15]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][15]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][16]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][16]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][16]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][16]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][17]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][17]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][17]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][17]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][18]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][18]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][18]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][18]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][19]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][19]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][19]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][19]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][1]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][1]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][1]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][20]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][20]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][20]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][20]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][21]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][21]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][21]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][21]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][22]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][22]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][22]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][22]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][23]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][23]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][23]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][23]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][24]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][24]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][24]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][24]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][25]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][25]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][25]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][25]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][26]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][26]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][26]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][26]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][27]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][27]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][27]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][27]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][28]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][28]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][28]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][28]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][29]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][29]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][29]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][29]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][2]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][2]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][2]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][30]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][30]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][30]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][30]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][31]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][31]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][31]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][31]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][32]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][32]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][32]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][32]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][33]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][33]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][33]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][33]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][3]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][3]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][3]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][4]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][4]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][4]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][5]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][5]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][5]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][6]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][6]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][6]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][7]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][7]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][7]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][8]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][8]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][8]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[0][9]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[0][9]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[0][9]\ : label is "no"; + attribute shift_extract of \data_sync_reg[0][9]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][0]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][0]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][0]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][10]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][10]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][10]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][11]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][11]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][11]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][12]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][12]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][12]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][13]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][13]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][13]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][14]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][14]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][14]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][15]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][15]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][15]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][16]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][16]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][16]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][16]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][17]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][17]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][17]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][17]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][18]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][18]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][18]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][18]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][19]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][19]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][19]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][19]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][1]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][1]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][1]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][20]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][20]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][20]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][20]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][21]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][21]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][21]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][21]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][22]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][22]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][22]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][22]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][23]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][23]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][23]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][23]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][24]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][24]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][24]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][24]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][25]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][25]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][25]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][25]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][26]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][26]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][26]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][26]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][27]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][27]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][27]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][27]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][28]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][28]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][28]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][28]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][29]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][29]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][29]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][29]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][2]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][2]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][2]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][30]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][30]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][30]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][30]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][31]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][31]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][31]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][31]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][32]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][32]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][32]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][32]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][33]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][33]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][33]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][33]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][3]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][3]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][3]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][4]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][4]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][4]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][5]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][5]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][5]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][6]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][6]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][6]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][7]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][7]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][7]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][8]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][8]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][8]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[1][9]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[1][9]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[1][9]\ : label is "no"; + attribute shift_extract of \data_sync_reg[1][9]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][0]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][0]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][0]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][0]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][10]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][10]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][10]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][10]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][11]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][11]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][11]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][11]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][12]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][12]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][12]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][12]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][13]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][13]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][13]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][13]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][14]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][14]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][14]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][14]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][15]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][15]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][15]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][15]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][16]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][16]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][16]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][16]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][17]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][17]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][17]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][17]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][18]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][18]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][18]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][18]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][19]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][19]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][19]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][19]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][1]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][1]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][1]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][1]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][20]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][20]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][20]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][20]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][21]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][21]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][21]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][21]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][22]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][22]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][22]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][22]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][23]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][23]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][23]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][23]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][24]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][24]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][24]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][24]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][25]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][25]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][25]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][25]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][26]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][26]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][26]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][26]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][27]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][27]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][27]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][27]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][28]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][28]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][28]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][28]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][29]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][29]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][29]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][29]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][2]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][2]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][2]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][2]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][30]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][30]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][30]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][30]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][31]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][31]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][31]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][31]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][32]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][32]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][32]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][32]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][33]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][33]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][33]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][33]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][3]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][3]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][3]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][3]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][4]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][4]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][4]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][4]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][5]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][5]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][5]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][5]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][6]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][6]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][6]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][6]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][7]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][7]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][7]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][7]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][8]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][8]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][8]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][8]\ : label is "NO"; + attribute ASYNC_REG_boolean of \data_sync_reg[2][9]\ : label is std.standard.true; + attribute KEEP of \data_sync_reg[2][9]\ : label is "yes"; + attribute SHREG_EXTRACT of \data_sync_reg[2][9]\ : label is "no"; + attribute shift_extract of \data_sync_reg[2][9]\ : label is "NO"; +begin + out_data(33 downto 0) <= \data_sync[2]_2\(33 downto 0); +\AXI4_LITE_INTERFACE.ipif_Error_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F7F7F7F700F7F7F7" + ) + port map ( + I0 => read_ack_d1, + I1 => \data_sync[2]_2\(32), + I2 => read_ack_d2, + I3 => write_ack_d1, + I4 => \data_sync[2]_2\(33), + I5 => write_ack_d2, + O => \AXI4_LITE_INTERFACE.ipif_Error_reg\ + ); +\AXI4_LITE_INTERFACE.ipif_RdAck_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => read_ack_d2, + I1 => \data_sync[2]_2\(32), + I2 => read_ack_d1, + O => p_528_out + ); +\AXI4_LITE_INTERFACE.ipif_WrAck_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => write_ack_d2, + I1 => \data_sync[2]_2\(33), + I2 => write_ack_d1, + O => p_526_out + ); +\data_sync_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(0), + Q => \data_sync[0]_0\(0), + R => '0' + ); +\data_sync_reg[0][10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(10), + Q => \data_sync[0]_0\(10), + R => '0' + ); +\data_sync_reg[0][11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(11), + Q => \data_sync[0]_0\(11), + R => '0' + ); +\data_sync_reg[0][12]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(12), + Q => \data_sync[0]_0\(12), + R => '0' + ); +\data_sync_reg[0][13]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(13), + Q => \data_sync[0]_0\(13), + R => '0' + ); +\data_sync_reg[0][14]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(14), + Q => \data_sync[0]_0\(14), + R => '0' + ); +\data_sync_reg[0][15]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(15), + Q => \data_sync[0]_0\(15), + R => '0' + ); +\data_sync_reg[0][16]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(16), + Q => \data_sync[0]_0\(16), + R => '0' + ); +\data_sync_reg[0][17]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(17), + Q => \data_sync[0]_0\(17), + R => '0' + ); +\data_sync_reg[0][18]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(18), + Q => \data_sync[0]_0\(18), + R => '0' + ); +\data_sync_reg[0][19]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(19), + Q => \data_sync[0]_0\(19), + R => '0' + ); +\data_sync_reg[0][1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(1), + Q => \data_sync[0]_0\(1), + R => '0' + ); +\data_sync_reg[0][20]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(20), + Q => \data_sync[0]_0\(20), + R => '0' + ); +\data_sync_reg[0][21]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(21), + Q => \data_sync[0]_0\(21), + R => '0' + ); +\data_sync_reg[0][22]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(22), + Q => \data_sync[0]_0\(22), + R => '0' + ); +\data_sync_reg[0][23]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(23), + Q => \data_sync[0]_0\(23), + R => '0' + ); +\data_sync_reg[0][24]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(24), + Q => \data_sync[0]_0\(24), + R => '0' + ); +\data_sync_reg[0][25]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(25), + Q => \data_sync[0]_0\(25), + R => '0' + ); +\data_sync_reg[0][26]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(26), + Q => \data_sync[0]_0\(26), + R => '0' + ); +\data_sync_reg[0][27]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(27), + Q => \data_sync[0]_0\(27), + R => '0' + ); +\data_sync_reg[0][28]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(28), + Q => \data_sync[0]_0\(28), + R => '0' + ); +\data_sync_reg[0][29]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(29), + Q => \data_sync[0]_0\(29), + R => '0' + ); +\data_sync_reg[0][2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(2), + Q => \data_sync[0]_0\(2), + R => '0' + ); +\data_sync_reg[0][30]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(30), + Q => \data_sync[0]_0\(30), + R => '0' + ); +\data_sync_reg[0][31]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(31), + Q => \data_sync[0]_0\(31), + R => '0' + ); +\data_sync_reg[0][32]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(32), + Q => \data_sync[0]_0\(32), + R => '0' + ); +\data_sync_reg[0][33]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(33), + Q => \data_sync[0]_0\(33), + R => '0' + ); +\data_sync_reg[0][3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(3), + Q => \data_sync[0]_0\(3), + R => '0' + ); +\data_sync_reg[0][4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(4), + Q => \data_sync[0]_0\(4), + R => '0' + ); +\data_sync_reg[0][5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(5), + Q => \data_sync[0]_0\(5), + R => '0' + ); +\data_sync_reg[0][6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(6), + Q => \data_sync[0]_0\(6), + R => '0' + ); +\data_sync_reg[0][7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(7), + Q => \data_sync[0]_0\(7), + R => '0' + ); +\data_sync_reg[0][8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(8), + Q => \data_sync[0]_0\(8), + R => '0' + ); +\data_sync_reg[0][9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => in_data(9), + Q => \data_sync[0]_0\(9), + R => '0' + ); +\data_sync_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(0), + Q => \data_sync[1]_1\(0), + R => '0' + ); +\data_sync_reg[1][10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(10), + Q => \data_sync[1]_1\(10), + R => '0' + ); +\data_sync_reg[1][11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(11), + Q => \data_sync[1]_1\(11), + R => '0' + ); +\data_sync_reg[1][12]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(12), + Q => \data_sync[1]_1\(12), + R => '0' + ); +\data_sync_reg[1][13]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(13), + Q => \data_sync[1]_1\(13), + R => '0' + ); +\data_sync_reg[1][14]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(14), + Q => \data_sync[1]_1\(14), + R => '0' + ); +\data_sync_reg[1][15]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(15), + Q => \data_sync[1]_1\(15), + R => '0' + ); +\data_sync_reg[1][16]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(16), + Q => \data_sync[1]_1\(16), + R => '0' + ); +\data_sync_reg[1][17]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(17), + Q => \data_sync[1]_1\(17), + R => '0' + ); +\data_sync_reg[1][18]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(18), + Q => \data_sync[1]_1\(18), + R => '0' + ); +\data_sync_reg[1][19]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(19), + Q => \data_sync[1]_1\(19), + R => '0' + ); +\data_sync_reg[1][1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(1), + Q => \data_sync[1]_1\(1), + R => '0' + ); +\data_sync_reg[1][20]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(20), + Q => \data_sync[1]_1\(20), + R => '0' + ); +\data_sync_reg[1][21]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(21), + Q => \data_sync[1]_1\(21), + R => '0' + ); +\data_sync_reg[1][22]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(22), + Q => \data_sync[1]_1\(22), + R => '0' + ); +\data_sync_reg[1][23]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(23), + Q => \data_sync[1]_1\(23), + R => '0' + ); +\data_sync_reg[1][24]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(24), + Q => \data_sync[1]_1\(24), + R => '0' + ); +\data_sync_reg[1][25]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(25), + Q => \data_sync[1]_1\(25), + R => '0' + ); +\data_sync_reg[1][26]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(26), + Q => \data_sync[1]_1\(26), + R => '0' + ); +\data_sync_reg[1][27]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(27), + Q => \data_sync[1]_1\(27), + R => '0' + ); +\data_sync_reg[1][28]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(28), + Q => \data_sync[1]_1\(28), + R => '0' + ); +\data_sync_reg[1][29]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(29), + Q => \data_sync[1]_1\(29), + R => '0' + ); +\data_sync_reg[1][2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(2), + Q => \data_sync[1]_1\(2), + R => '0' + ); +\data_sync_reg[1][30]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(30), + Q => \data_sync[1]_1\(30), + R => '0' + ); +\data_sync_reg[1][31]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(31), + Q => \data_sync[1]_1\(31), + R => '0' + ); +\data_sync_reg[1][32]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(32), + Q => \data_sync[1]_1\(32), + R => '0' + ); +\data_sync_reg[1][33]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(33), + Q => \data_sync[1]_1\(33), + R => '0' + ); +\data_sync_reg[1][3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(3), + Q => \data_sync[1]_1\(3), + R => '0' + ); +\data_sync_reg[1][4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(4), + Q => \data_sync[1]_1\(4), + R => '0' + ); +\data_sync_reg[1][5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(5), + Q => \data_sync[1]_1\(5), + R => '0' + ); +\data_sync_reg[1][6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(6), + Q => \data_sync[1]_1\(6), + R => '0' + ); +\data_sync_reg[1][7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(7), + Q => \data_sync[1]_1\(7), + R => '0' + ); +\data_sync_reg[1][8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(8), + Q => \data_sync[1]_1\(8), + R => '0' + ); +\data_sync_reg[1][9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[0]_0\(9), + Q => \data_sync[1]_1\(9), + R => '0' + ); +\data_sync_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(0), + Q => \data_sync[2]_2\(0), + R => '0' + ); +\data_sync_reg[2][10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(10), + Q => \data_sync[2]_2\(10), + R => '0' + ); +\data_sync_reg[2][11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(11), + Q => \data_sync[2]_2\(11), + R => '0' + ); +\data_sync_reg[2][12]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(12), + Q => \data_sync[2]_2\(12), + R => '0' + ); +\data_sync_reg[2][13]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(13), + Q => \data_sync[2]_2\(13), + R => '0' + ); +\data_sync_reg[2][14]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(14), + Q => \data_sync[2]_2\(14), + R => '0' + ); +\data_sync_reg[2][15]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(15), + Q => \data_sync[2]_2\(15), + R => '0' + ); +\data_sync_reg[2][16]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(16), + Q => \data_sync[2]_2\(16), + R => '0' + ); +\data_sync_reg[2][17]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(17), + Q => \data_sync[2]_2\(17), + R => '0' + ); +\data_sync_reg[2][18]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(18), + Q => \data_sync[2]_2\(18), + R => '0' + ); +\data_sync_reg[2][19]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(19), + Q => \data_sync[2]_2\(19), + R => '0' + ); +\data_sync_reg[2][1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(1), + Q => \data_sync[2]_2\(1), + R => '0' + ); +\data_sync_reg[2][20]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(20), + Q => \data_sync[2]_2\(20), + R => '0' + ); +\data_sync_reg[2][21]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(21), + Q => \data_sync[2]_2\(21), + R => '0' + ); +\data_sync_reg[2][22]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(22), + Q => \data_sync[2]_2\(22), + R => '0' + ); +\data_sync_reg[2][23]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(23), + Q => \data_sync[2]_2\(23), + R => '0' + ); +\data_sync_reg[2][24]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(24), + Q => \data_sync[2]_2\(24), + R => '0' + ); +\data_sync_reg[2][25]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(25), + Q => \data_sync[2]_2\(25), + R => '0' + ); +\data_sync_reg[2][26]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(26), + Q => \data_sync[2]_2\(26), + R => '0' + ); +\data_sync_reg[2][27]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(27), + Q => \data_sync[2]_2\(27), + R => '0' + ); +\data_sync_reg[2][28]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(28), + Q => \data_sync[2]_2\(28), + R => '0' + ); +\data_sync_reg[2][29]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(29), + Q => \data_sync[2]_2\(29), + R => '0' + ); +\data_sync_reg[2][2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(2), + Q => \data_sync[2]_2\(2), + R => '0' + ); +\data_sync_reg[2][30]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(30), + Q => \data_sync[2]_2\(30), + R => '0' + ); +\data_sync_reg[2][31]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(31), + Q => \data_sync[2]_2\(31), + R => '0' + ); +\data_sync_reg[2][32]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(32), + Q => \data_sync[2]_2\(32), + R => '0' + ); +\data_sync_reg[2][33]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(33), + Q => \data_sync[2]_2\(33), + R => '0' + ); +\data_sync_reg[2][3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(3), + Q => \data_sync[2]_2\(3), + R => '0' + ); +\data_sync_reg[2][4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(4), + Q => \data_sync[2]_2\(4), + R => '0' + ); +\data_sync_reg[2][5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(5), + Q => \data_sync[2]_2\(5), + R => '0' + ); +\data_sync_reg[2][6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(6), + Q => \data_sync[2]_2\(6), + R => '0' + ); +\data_sync_reg[2][7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(7), + Q => \data_sync[2]_2\(7), + R => '0' + ); +\data_sync_reg[2][8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(8), + Q => \data_sync[2]_2\(8), + R => '0' + ); +\data_sync_reg[2][9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \data_sync[1]_1\(9), + Q => \data_sync[2]_2\(9), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_tc_1_0_slave_attachment is + port ( + p_0_in : out STD_LOGIC; + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 ); + D : out STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_arready : out STD_LOGIC; + s_axi_rvalid : out STD_LOGIC; + s_axi_bvalid : out STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wvalid : in STD_LOGIC; + s_axi_awvalid : in STD_LOGIC; + s_axi_arvalid : in STD_LOGIC; + aclk : in STD_LOGIC; + out_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); + ipif_Error : in STD_LOGIC; + s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + aresetn : in STD_LOGIC; + s_axi_rready : in STD_LOGIC; + s_axi_bready : in STD_LOGIC; + ipif_RdAck : in STD_LOGIC; + ipif_WrAck : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_tc_1_0_slave_attachment : entity is "slave_attachment"; +end Arty_Z7_20_v_tc_1_0_slave_attachment; + +architecture STRUCTURE of Arty_Z7_20_v_tc_1_0_slave_attachment is + signal \^d\ : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \INCLUDE_DPHASE_TIMER.dpto_cnt[9]_i_3_n_0\ : STD_LOGIC; + signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal \bus2ip_addr_i[0]_i_1_n_0\ : STD_LOGIC; + signal \bus2ip_addr_i[1]_i_1_n_0\ : STD_LOGIC; + signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC; + signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC; + signal \bus2ip_addr_i[4]_i_1_n_0\ : STD_LOGIC; + signal \bus2ip_addr_i[5]_i_1_n_0\ : STD_LOGIC; + signal \bus2ip_addr_i[6]_i_1_n_0\ : STD_LOGIC; + signal \bus2ip_addr_i[7]_i_1_n_0\ : STD_LOGIC; + signal \bus2ip_addr_i[8]_i_1_n_0\ : STD_LOGIC; + signal \bus2ip_addr_i[8]_i_2_n_0\ : STD_LOGIC; + signal bus2ip_rnw_i06_out : STD_LOGIC; + signal clear : STD_LOGIC; + signal is_read : STD_LOGIC; + signal is_read_i_1_n_0 : STD_LOGIC; + signal is_write : STD_LOGIC; + signal is_write_i_1_n_0 : STD_LOGIC; + signal is_write_reg_n_0 : STD_LOGIC; + signal \^p_0_in\ : STD_LOGIC; + signal p_0_out : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal plusOp : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal rst : STD_LOGIC; + signal \^s_axi_arready\ : STD_LOGIC; + signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \s_axi_bresp_i[1]_i_1_n_0\ : STD_LOGIC; + signal \^s_axi_bvalid\ : STD_LOGIC; + signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC; + signal \s_axi_rdata_i[31]_i_1_n_0\ : STD_LOGIC; + signal \^s_axi_rvalid\ : STD_LOGIC; + signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC; + signal \^s_axi_wready\ : STD_LOGIC; + signal start2 : STD_LOGIC; + signal start2_i_1_n_0 : STD_LOGIC; + signal state : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \state1__2\ : STD_LOGIC; + signal \state[1]_i_3_n_0\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[4]_i_1\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[6]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[7]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[8]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[9]_i_2\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \bus2ip_addr_i[2]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair3"; +begin + D(11 downto 0) <= \^d\(11 downto 0); + p_0_in <= \^p_0_in\; + s_axi_arready <= \^s_axi_arready\; + s_axi_bresp(0) <= \^s_axi_bresp\(0); + s_axi_bvalid <= \^s_axi_bvalid\; + s_axi_rvalid <= \^s_axi_rvalid\; + s_axi_wready <= \^s_axi_wready\; +\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), + O => plusOp(0) + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), + I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), + O => plusOp(1) + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), + I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), + I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), + O => plusOp(2) + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), + I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), + I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), + I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3), + O => plusOp(3) + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), + I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), + I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), + I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3), + I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4), + O => plusOp(4) + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFFFFFF80000000" + ) + port map ( + I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3), + I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), + I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), + I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), + I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4), + I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(5), + O => plusOp(5) + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt[6]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt[9]_i_3_n_0\, + I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(6), + O => plusOp(6) + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt[7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt[9]_i_3_n_0\, + I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(6), + I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(7), + O => plusOp(7) + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt[8]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(6), + I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt[9]_i_3_n_0\, + I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(7), + I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(8), + O => plusOp(8) + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt[9]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => state(0), + I1 => state(1), + O => clear + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt[9]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(7), + I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt[9]_i_3_n_0\, + I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(6), + I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(8), + I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(9), + O => plusOp(9) + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt[9]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(5), + I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3), + I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), + I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), + I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), + I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4), + O => \INCLUDE_DPHASE_TIMER.dpto_cnt[9]_i_3_n_0\ + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => plusOp(0), + Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), + R => clear + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => plusOp(1), + Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), + R => clear + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => plusOp(2), + Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), + R => clear + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => plusOp(3), + Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3), + R => clear + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => plusOp(4), + Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4), + R => clear + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => plusOp(5), + Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(5), + R => clear + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => plusOp(6), + Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(6), + R => clear + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => plusOp(7), + Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(7), + R => clear + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => plusOp(8), + Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(8), + R => clear + ); +\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => plusOp(9), + Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(9), + R => clear + ); +I_DECODER: entity work.Arty_Z7_20_v_tc_1_0_address_decoder + port map ( + D(1 downto 0) => \^d\(10 downto 9), + Q(9 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(9 downto 0), + aclk => aclk, + aresetn => aresetn, + \bus2ip_addr_i_reg[8]\(1 downto 0) => \^d\(8 downto 7), + ipif_RdAck => ipif_RdAck, + ipif_WrAck => ipif_WrAck, + is_read => is_read, + is_write_reg => is_write_reg_n_0, + s_axi_arready => \^s_axi_arready\, + s_axi_wready => \^s_axi_wready\, + start2_reg => start2 + ); +\bus2ip_addr_i[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"CCCACCCC" + ) + port map ( + I0 => s_axi_araddr(0), + I1 => s_axi_awaddr(0), + I2 => state(0), + I3 => state(1), + I4 => s_axi_arvalid, + O => \bus2ip_addr_i[0]_i_1_n_0\ + ); +\bus2ip_addr_i[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"CCCACCCC" + ) + port map ( + I0 => s_axi_araddr(1), + I1 => s_axi_awaddr(1), + I2 => state(0), + I3 => state(1), + I4 => s_axi_arvalid, + O => \bus2ip_addr_i[1]_i_1_n_0\ + ); +\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"CCCACCCC" + ) + port map ( + I0 => s_axi_araddr(2), + I1 => s_axi_awaddr(2), + I2 => state(0), + I3 => state(1), + I4 => s_axi_arvalid, + O => \bus2ip_addr_i[2]_i_1_n_0\ + ); +\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"CCCACCCC" + ) + port map ( + I0 => s_axi_araddr(3), + I1 => s_axi_awaddr(3), + I2 => state(0), + I3 => state(1), + I4 => s_axi_arvalid, + O => \bus2ip_addr_i[3]_i_1_n_0\ + ); +\bus2ip_addr_i[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"CCCACCCC" + ) + port map ( + I0 => s_axi_araddr(4), + I1 => s_axi_awaddr(4), + I2 => state(0), + I3 => state(1), + I4 => s_axi_arvalid, + O => \bus2ip_addr_i[4]_i_1_n_0\ + ); +\bus2ip_addr_i[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"CCCACCCC" + ) + port map ( + I0 => s_axi_araddr(5), + I1 => s_axi_awaddr(5), + I2 => state(0), + I3 => state(1), + I4 => s_axi_arvalid, + O => \bus2ip_addr_i[5]_i_1_n_0\ + ); +\bus2ip_addr_i[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"CCCACCCC" + ) + port map ( + I0 => s_axi_araddr(6), + I1 => s_axi_awaddr(6), + I2 => state(0), + I3 => state(1), + I4 => s_axi_arvalid, + O => \bus2ip_addr_i[6]_i_1_n_0\ + ); +\bus2ip_addr_i[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"CCCACCCC" + ) + port map ( + I0 => s_axi_araddr(7), + I1 => s_axi_awaddr(7), + I2 => state(0), + I3 => state(1), + I4 => s_axi_arvalid, + O => \bus2ip_addr_i[7]_i_1_n_0\ + ); +\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000EA" + ) + port map ( + I0 => s_axi_arvalid, + I1 => s_axi_awvalid, + I2 => s_axi_wvalid, + I3 => state(1), + I4 => state(0), + O => \bus2ip_addr_i[8]_i_1_n_0\ + ); +\bus2ip_addr_i[8]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"CCCACCCC" + ) + port map ( + I0 => s_axi_araddr(8), + I1 => s_axi_awaddr(8), + I2 => state(0), + I3 => state(1), + I4 => s_axi_arvalid, + O => \bus2ip_addr_i[8]_i_2_n_0\ + ); +\bus2ip_addr_i_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \bus2ip_addr_i[8]_i_1_n_0\, + D => \bus2ip_addr_i[0]_i_1_n_0\, + Q => \^d\(0), + R => rst + ); +\bus2ip_addr_i_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \bus2ip_addr_i[8]_i_1_n_0\, + D => \bus2ip_addr_i[1]_i_1_n_0\, + Q => \^d\(1), + R => rst + ); +\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \bus2ip_addr_i[8]_i_1_n_0\, + D => \bus2ip_addr_i[2]_i_1_n_0\, + Q => \^d\(2), + R => rst + ); +\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \bus2ip_addr_i[8]_i_1_n_0\, + D => \bus2ip_addr_i[3]_i_1_n_0\, + Q => \^d\(3), + R => rst + ); +\bus2ip_addr_i_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \bus2ip_addr_i[8]_i_1_n_0\, + D => \bus2ip_addr_i[4]_i_1_n_0\, + Q => \^d\(4), + R => rst + ); +\bus2ip_addr_i_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \bus2ip_addr_i[8]_i_1_n_0\, + D => \bus2ip_addr_i[5]_i_1_n_0\, + Q => \^d\(5), + R => rst + ); +\bus2ip_addr_i_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \bus2ip_addr_i[8]_i_1_n_0\, + D => \bus2ip_addr_i[6]_i_1_n_0\, + Q => \^d\(6), + R => rst + ); +\bus2ip_addr_i_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \bus2ip_addr_i[8]_i_1_n_0\, + D => \bus2ip_addr_i[7]_i_1_n_0\, + Q => \^d\(7), + R => rst + ); +\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \bus2ip_addr_i[8]_i_1_n_0\, + D => \bus2ip_addr_i[8]_i_2_n_0\, + Q => \^d\(8), + R => rst + ); +bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"10" + ) + port map ( + I0 => state(0), + I1 => state(1), + I2 => s_axi_arvalid, + O => bus2ip_rnw_i06_out + ); +bus2ip_rnw_i_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \bus2ip_addr_i[8]_i_1_n_0\, + D => bus2ip_rnw_i06_out, + Q => \^d\(11), + R => rst + ); +is_read_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"3FFA000A" + ) + port map ( + I0 => s_axi_arvalid, + I1 => \state1__2\, + I2 => state(0), + I3 => state(1), + I4 => is_read, + O => is_read_i_1_n_0 + ); +is_read_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => is_read_i_1_n_0, + Q => is_read, + R => rst + ); +is_write_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0040FFFF00400000" + ) + port map ( + I0 => s_axi_arvalid, + I1 => s_axi_awvalid, + I2 => s_axi_wvalid, + I3 => state(1), + I4 => is_write, + I5 => is_write_reg_n_0, + O => is_write_i_1_n_0 + ); +is_write_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"F88800000000FFFF" + ) + port map ( + I0 => \^s_axi_rvalid\, + I1 => s_axi_rready, + I2 => \^s_axi_bvalid\, + I3 => s_axi_bready, + I4 => state(0), + I5 => state(1), + O => is_write + ); +is_write_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => is_write_i_1_n_0, + Q => is_write_reg_n_0, + R => rst + ); +rst_i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => aresetn, + O => \^p_0_in\ + ); +rst_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \^p_0_in\, + Q => rst, + R => '0' + ); +\s_axi_bresp_i[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => ipif_Error, + I1 => state(1), + I2 => state(0), + I3 => \^s_axi_bresp\(0), + O => \s_axi_bresp_i[1]_i_1_n_0\ + ); +\s_axi_bresp_i_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \s_axi_bresp_i[1]_i_1_n_0\, + Q => \^s_axi_bresp\(0), + R => rst + ); +s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"08FF0808" + ) + port map ( + I0 => \^s_axi_wready\, + I1 => state(1), + I2 => state(0), + I3 => s_axi_bready, + I4 => \^s_axi_bvalid\, + O => s_axi_bvalid_i_i_1_n_0 + ); +s_axi_bvalid_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_bvalid_i_i_1_n_0, + Q => \^s_axi_bvalid\, + R => rst + ); +\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => state(0), + I1 => state(1), + O => \s_axi_rdata_i[31]_i_1_n_0\ + ); +\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(0), + Q => s_axi_rdata(0), + R => rst + ); +\s_axi_rdata_i_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(10), + Q => s_axi_rdata(10), + R => rst + ); +\s_axi_rdata_i_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(11), + Q => s_axi_rdata(11), + R => rst + ); +\s_axi_rdata_i_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(12), + Q => s_axi_rdata(12), + R => rst + ); +\s_axi_rdata_i_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(13), + Q => s_axi_rdata(13), + R => rst + ); +\s_axi_rdata_i_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(14), + Q => s_axi_rdata(14), + R => rst + ); +\s_axi_rdata_i_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(15), + Q => s_axi_rdata(15), + R => rst + ); +\s_axi_rdata_i_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(16), + Q => s_axi_rdata(16), + R => rst + ); +\s_axi_rdata_i_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(17), + Q => s_axi_rdata(17), + R => rst + ); +\s_axi_rdata_i_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(18), + Q => s_axi_rdata(18), + R => rst + ); +\s_axi_rdata_i_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(19), + Q => s_axi_rdata(19), + R => rst + ); +\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(1), + Q => s_axi_rdata(1), + R => rst + ); +\s_axi_rdata_i_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(20), + Q => s_axi_rdata(20), + R => rst + ); +\s_axi_rdata_i_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(21), + Q => s_axi_rdata(21), + R => rst + ); +\s_axi_rdata_i_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(22), + Q => s_axi_rdata(22), + R => rst + ); +\s_axi_rdata_i_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(23), + Q => s_axi_rdata(23), + R => rst + ); +\s_axi_rdata_i_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(24), + Q => s_axi_rdata(24), + R => rst + ); +\s_axi_rdata_i_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(25), + Q => s_axi_rdata(25), + R => rst + ); +\s_axi_rdata_i_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(26), + Q => s_axi_rdata(26), + R => rst + ); +\s_axi_rdata_i_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(27), + Q => s_axi_rdata(27), + R => rst + ); +\s_axi_rdata_i_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(28), + Q => s_axi_rdata(28), + R => rst + ); +\s_axi_rdata_i_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(29), + Q => s_axi_rdata(29), + R => rst + ); +\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(2), + Q => s_axi_rdata(2), + R => rst + ); +\s_axi_rdata_i_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(30), + Q => s_axi_rdata(30), + R => rst + ); +\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(31), + Q => s_axi_rdata(31), + R => rst + ); +\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(3), + Q => s_axi_rdata(3), + R => rst + ); +\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(4), + Q => s_axi_rdata(4), + R => rst + ); +\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(5), + Q => s_axi_rdata(5), + R => rst + ); +\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(6), + Q => s_axi_rdata(6), + R => rst + ); +\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(7), + Q => s_axi_rdata(7), + R => rst + ); +\s_axi_rdata_i_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(8), + Q => s_axi_rdata(8), + R => rst + ); +\s_axi_rdata_i_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => out_data(9), + Q => s_axi_rdata(9), + R => rst + ); +\s_axi_rresp_i_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \s_axi_rdata_i[31]_i_1_n_0\, + D => ipif_Error, + Q => s_axi_rresp(0), + R => rst + ); +s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"08FF0808" + ) + port map ( + I0 => \^s_axi_arready\, + I1 => state(0), + I2 => state(1), + I3 => s_axi_rready, + I4 => \^s_axi_rvalid\, + O => s_axi_rvalid_i_i_1_n_0 + ); +s_axi_rvalid_i_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_rvalid_i_i_1_n_0, + Q => \^s_axi_rvalid\, + R => rst + ); +start2_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000F8" + ) + port map ( + I0 => s_axi_awvalid, + I1 => s_axi_wvalid, + I2 => s_axi_arvalid, + I3 => state(1), + I4 => state(0), + O => start2_i_1_n_0 + ); +start2_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => start2_i_1_n_0, + Q => start2, + R => rst + ); +\state[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"77FC44FC" + ) + port map ( + I0 => \state1__2\, + I1 => state(0), + I2 => s_axi_arvalid, + I3 => state(1), + I4 => \^s_axi_wready\, + O => p_0_out(0) + ); +\state[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"5FFC50FC" + ) + port map ( + I0 => \state1__2\, + I1 => \state[1]_i_3_n_0\, + I2 => state(1), + I3 => state(0), + I4 => \^s_axi_arready\, + O => p_0_out(1) + ); +\state[1]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F888" + ) + port map ( + I0 => s_axi_bready, + I1 => \^s_axi_bvalid\, + I2 => s_axi_rready, + I3 => \^s_axi_rvalid\, + O => \state1__2\ + ); +\state[1]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => s_axi_wvalid, + I1 => s_axi_awvalid, + I2 => s_axi_arvalid, + O => \state[1]_i_3_n_0\ + ); +\state_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => p_0_out(0), + Q => state(0), + R => rst + ); +\state_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => p_0_out(1), + Q => state(1), + R => rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_tc_1_0_tc_top is + port ( + Q : out STD_LOGIC_VECTOR ( 11 downto 0 ); + \time_status_regs[6]\ : out STD_LOGIC_VECTOR ( 23 downto 0 ); + \time_status_regs[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \time_status_regs_int_reg[0]\ : out STD_LOGIC_VECTOR ( 22 downto 0 ); + intc_if : out STD_LOGIC_VECTOR ( 8 downto 0 ); + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10]\ : out STD_LOGIC_VECTOR ( 10 downto 0 ); + \time_status_regs[8]\ : out STD_LOGIC_VECTOR ( 21 downto 0 ); + \time_status_regs[7]\ : out STD_LOGIC_VECTOR ( 23 downto 0 ); + \time_status_regs[9]\ : out STD_LOGIC_VECTOR ( 23 downto 0 ); + clk : in STD_LOGIC; + clken : in STD_LOGIC; + active_video_in : in STD_LOGIC; + vblank_in : in STD_LOGIC; + hsync_in : in STD_LOGIC; + det_clken : in STD_LOGIC; + resetn_out : in STD_LOGIC; + \genr_control_regs[0]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + core_d_out : in STD_LOGIC; + vsync_in : in STD_LOGIC; + \time_control_regs[19]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_tc_1_0_tc_top : entity is "tc_top"; +end Arty_Z7_20_v_tc_1_0_tc_top; + +architecture STRUCTURE of Arty_Z7_20_v_tc_1_0_tc_top is + signal \GEN_DETECTION.U_tc_DET_n_68\ : STD_LOGIC; + signal \GEN_DETECTION.U_tc_DET_n_69\ : STD_LOGIC; + signal active_video_lock_int : STD_LOGIC; + signal all_lock : STD_LOGIC; + signal all_lock_d : STD_LOGIC; + signal all_lock_d0 : STD_LOGIC; + signal all_lock_d_i_1_n_0 : STD_LOGIC; + signal det_active_video_d : STD_LOGIC; + signal det_ce : STD_LOGIC; + signal det_vblank_d : STD_LOGIC; + signal detect_en : STD_LOGIC; + signal \detect_en_d_reg[1]_srl2___U_TC_TOP_detect_en_d_reg_r_3_n_0\ : STD_LOGIC; + signal \detect_en_d_reg[2]_U_TC_TOP_detect_en_d_reg_r_4_n_0\ : STD_LOGIC; + signal detect_en_d_reg_gate_n_0 : STD_LOGIC; + signal detect_en_d_reg_r_3_n_0 : STD_LOGIC; + signal detect_en_d_reg_r_4_n_0 : STD_LOGIC; + signal detect_en_d_reg_r_n_0 : STD_LOGIC; + signal generate_en : STD_LOGIC; + signal generate_en_d : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \generate_en_d_reg[1]_srl2___U_TC_TOP_detect_en_d_reg_r_3_n_0\ : STD_LOGIC; + signal \generate_en_d_reg[2]_U_TC_TOP_detect_en_d_reg_r_4_n_0\ : STD_LOGIC; + signal generate_en_d_reg_gate_n_0 : STD_LOGIC; + signal hsync_lock_int : STD_LOGIC; + signal \^intc_if\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal intr_error_int : STD_LOGIC; + signal intr_status_int17_out : STD_LOGIC; + signal \intr_status_int[10]_i_1_n_0\ : STD_LOGIC; + signal \intr_status_int[11]_i_1_n_0\ : STD_LOGIC; + signal \intr_status_int[12]_i_1_n_0\ : STD_LOGIC; + signal \intr_status_int[8]_i_1_n_0\ : STD_LOGIC; + signal \intr_status_int[9]_i_1_n_0\ : STD_LOGIC; + signal lost_lock : STD_LOGIC; + signal lost_lock_i_1_n_0 : STD_LOGIC; + signal p_0_in : STD_LOGIC; + signal reset : STD_LOGIC; + signal vsync_lock_int : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of all_lock_d_i_1 : label is "soft_lutpair310"; + attribute SOFT_HLUTNM of all_lock_i_2 : label is "soft_lutpair311"; + attribute srl_bus_name : string; + attribute srl_bus_name of \detect_en_d_reg[1]_srl2___U_TC_TOP_detect_en_d_reg_r_3\ : label is "U0/\U_TC_TOP/detect_en_d_reg "; + attribute srl_name : string; + attribute srl_name of \detect_en_d_reg[1]_srl2___U_TC_TOP_detect_en_d_reg_r_3\ : label is "U0/\U_TC_TOP/detect_en_d_reg[1]_srl2___U_TC_TOP_detect_en_d_reg_r_3 "; + attribute SOFT_HLUTNM of detect_en_d_reg_gate : label is "soft_lutpair312"; + attribute srl_bus_name of \generate_en_d_reg[1]_srl2___U_TC_TOP_detect_en_d_reg_r_3\ : label is "U0/\U_TC_TOP/generate_en_d_reg "; + attribute srl_name of \generate_en_d_reg[1]_srl2___U_TC_TOP_detect_en_d_reg_r_3\ : label is "U0/\U_TC_TOP/generate_en_d_reg[1]_srl2___U_TC_TOP_detect_en_d_reg_r_3 "; + attribute SOFT_HLUTNM of \generate_en_d_reg[1]_srl2___U_TC_TOP_detect_en_d_reg_r_3_i_1\ : label is "soft_lutpair311"; + attribute SOFT_HLUTNM of generate_en_d_reg_gate : label is "soft_lutpair312"; + attribute SOFT_HLUTNM of lost_lock_i_1 : label is "soft_lutpair310"; +begin + intc_if(8 downto 0) <= \^intc_if\(8 downto 0); +\GEN_DETECTION.U_tc_DET\: entity work.Arty_Z7_20_v_tc_1_0_tc_detector + port map ( + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11]\(11 downto 0) => \time_status_regs_int_reg[0]\(11 downto 0), + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10]\(10 downto 0) => \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10]\(10 downto 0), + Q(11 downto 0) => Q(11 downto 0), + active_video_in => active_video_in, + active_video_lock_int => active_video_lock_int, + all_lock => all_lock, + all_lock_d0 => all_lock_d0, + all_lock_reg => \GEN_DETECTION.U_tc_DET_n_69\, + clk => clk, + clken => clken, + core_d_out => core_d_out, + det_active_video_d => det_active_video_d, + det_ce => det_ce, + det_clken => det_clken, + det_vblank_d => det_vblank_d, + \genr_control_regs[0]\(1) => \genr_control_regs[0]\(2), + \genr_control_regs[0]\(0) => \genr_control_regs[0]\(0), + hsync_in => hsync_in, + hsync_lock_int => hsync_lock_int, + intc_if(0) => \^intc_if\(7), + intr_status_int17_out => intr_status_int17_out, + \intr_status_int_reg[11]\ => \GEN_DETECTION.U_tc_DET_n_68\, + lost_lock => lost_lock, + reset => reset, + resetn_out => resetn_out, + \time_status_regs[3]\(2 downto 0) => \time_status_regs[3]\(2 downto 0), + \time_status_regs[6]\(23 downto 0) => \time_status_regs[6]\(23 downto 0), + \time_status_regs[7]\(23 downto 0) => \time_status_regs[7]\(23 downto 0), + \time_status_regs[8]\(21 downto 0) => \time_status_regs[8]\(21 downto 0), + \time_status_regs[9]\(23 downto 0) => \time_status_regs[9]\(23 downto 0), + \time_status_regs_int_reg[0]\(10 downto 0) => \time_status_regs_int_reg[0]\(22 downto 12), + vblank_in => vblank_in, + vsync_in => vsync_in, + vsync_lock_int => vsync_lock_int + ); +all_lock_d_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFE2" + ) + port map ( + I0 => all_lock_d, + I1 => det_ce, + I2 => all_lock, + I3 => all_lock_d0, + O => all_lock_d_i_1_n_0 + ); +all_lock_d_reg: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => '1', + D => all_lock_d_i_1_n_0, + Q => all_lock_d, + R => '0' + ); +all_lock_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"F5F7" + ) + port map ( + I0 => resetn_out, + I1 => \genr_control_regs[0]\(1), + I2 => core_d_out, + I3 => \genr_control_regs[0]\(0), + O => all_lock_d0 + ); +all_lock_reg: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => '1', + D => \GEN_DETECTION.U_tc_DET_n_69\, + Q => all_lock, + R => '0' + ); +det_active_video_d_reg: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => clken, + D => active_video_in, + Q => det_active_video_d, + R => reset + ); +det_vblank_d_reg: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => clken, + D => vblank_in, + Q => det_vblank_d, + R => reset + ); +\detect_en_d_reg[1]_srl2___U_TC_TOP_detect_en_d_reg_r_3\: unisim.vcomponents.SRL16E + port map ( + A0 => '1', + A1 => '0', + A2 => '0', + A3 => '0', + CE => clken, + CLK => clk, + D => detect_en, + Q => \detect_en_d_reg[1]_srl2___U_TC_TOP_detect_en_d_reg_r_3_n_0\ + ); +\detect_en_d_reg[1]_srl2___U_TC_TOP_detect_en_d_reg_r_3_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"32" + ) + port map ( + I0 => \genr_control_regs[0]\(0), + I1 => core_d_out, + I2 => \genr_control_regs[0]\(2), + O => detect_en + ); +\detect_en_d_reg[2]_U_TC_TOP_detect_en_d_reg_r_4\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => clken, + D => \detect_en_d_reg[1]_srl2___U_TC_TOP_detect_en_d_reg_r_3_n_0\, + Q => \detect_en_d_reg[2]_U_TC_TOP_detect_en_d_reg_r_4_n_0\, + R => '0' + ); +\detect_en_d_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => clken, + D => detect_en_d_reg_gate_n_0, + Q => p_0_in, + R => reset + ); +detect_en_d_reg_gate: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \detect_en_d_reg[2]_U_TC_TOP_detect_en_d_reg_r_4_n_0\, + I1 => detect_en_d_reg_r_4_n_0, + O => detect_en_d_reg_gate_n_0 + ); +detect_en_d_reg_r: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => clken, + D => '1', + Q => detect_en_d_reg_r_n_0, + R => reset + ); +detect_en_d_reg_r_3: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => clken, + D => detect_en_d_reg_r_n_0, + Q => detect_en_d_reg_r_3_n_0, + R => reset + ); +detect_en_d_reg_r_4: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => clken, + D => detect_en_d_reg_r_3_n_0, + Q => detect_en_d_reg_r_4_n_0, + R => reset + ); +\generate_en_d_reg[1]_srl2___U_TC_TOP_detect_en_d_reg_r_3\: unisim.vcomponents.SRL16E + port map ( + A0 => '1', + A1 => '0', + A2 => '0', + A3 => '0', + CE => clken, + CLK => clk, + D => generate_en, + Q => \generate_en_d_reg[1]_srl2___U_TC_TOP_detect_en_d_reg_r_3_n_0\ + ); +\generate_en_d_reg[1]_srl2___U_TC_TOP_detect_en_d_reg_r_3_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"32" + ) + port map ( + I0 => \genr_control_regs[0]\(0), + I1 => core_d_out, + I2 => \genr_control_regs[0]\(1), + O => generate_en + ); +\generate_en_d_reg[2]_U_TC_TOP_detect_en_d_reg_r_4\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => clken, + D => \generate_en_d_reg[1]_srl2___U_TC_TOP_detect_en_d_reg_r_3_n_0\, + Q => \generate_en_d_reg[2]_U_TC_TOP_detect_en_d_reg_r_4_n_0\, + R => '0' + ); +\generate_en_d_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => clken, + D => generate_en_d_reg_gate_n_0, + Q => generate_en_d(3), + R => reset + ); +generate_en_d_reg_gate: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \generate_en_d_reg[2]_U_TC_TOP_detect_en_d_reg_r_4_n_0\, + I1 => detect_en_d_reg_r_4_n_0, + O => generate_en_d_reg_gate_n_0 + ); +\intr_error_int[6]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => clken, + I1 => p_0_in, + O => intr_error_int + ); +\intr_error_int_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => intr_error_int, + D => vsync_lock_int, + Q => \^intc_if\(0), + R => reset + ); +\intr_error_int_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => intr_error_int, + D => hsync_lock_int, + Q => \^intc_if\(1), + R => reset + ); +\intr_error_int_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => intr_error_int, + D => active_video_lock_int, + Q => \^intc_if\(2), + R => reset + ); +\intr_error_int_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => clk, + CE => intr_error_int, + D => '1', + Q => \^intc_if\(3), + R => reset + ); +\intr_status_int[10]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"3000AA00" + ) + port map ( + I0 => \^intc_if\(6), + I1 => vblank_in, + I2 => p_0_in, + I3 => resetn_out, + I4 => clken, + O => \intr_status_int[10]_i_1_n_0\ + ); +\intr_status_int[11]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D0FF000080000000" + ) + port map ( + I0 => active_video_lock_int, + I1 => \GEN_DETECTION.U_tc_DET_n_68\, + I2 => p_0_in, + I3 => clken, + I4 => resetn_out, + I5 => \^intc_if\(7), + O => \intr_status_int[11]_i_1_n_0\ + ); +\intr_status_int[12]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"3A000A00" + ) + port map ( + I0 => \^intc_if\(8), + I1 => \time_control_regs[19]\(0), + I2 => clken, + I3 => resetn_out, + I4 => generate_en_d(3), + O => \intr_status_int[12]_i_1_n_0\ + ); +\intr_status_int[8]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"C000AA00" + ) + port map ( + I0 => \^intc_if\(4), + I1 => intr_status_int17_out, + I2 => p_0_in, + I3 => resetn_out, + I4 => clken, + O => \intr_status_int[8]_i_1_n_0\ + ); +\intr_status_int[9]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"3000AA00" + ) + port map ( + I0 => \^intc_if\(5), + I1 => intr_status_int17_out, + I2 => p_0_in, + I3 => resetn_out, + I4 => clken, + O => \intr_status_int[9]_i_1_n_0\ + ); +\intr_status_int_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => '1', + D => \intr_status_int[10]_i_1_n_0\, + Q => \^intc_if\(6), + R => '0' + ); +\intr_status_int_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => '1', + D => \intr_status_int[11]_i_1_n_0\, + Q => \^intc_if\(7), + R => '0' + ); +\intr_status_int_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => '1', + D => \intr_status_int[12]_i_1_n_0\, + Q => \^intc_if\(8), + R => '0' + ); +\intr_status_int_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => '1', + D => \intr_status_int[8]_i_1_n_0\, + Q => \^intc_if\(4), + R => '0' + ); +\intr_status_int_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => '1', + D => \intr_status_int[9]_i_1_n_0\, + Q => \^intc_if\(5), + R => '0' + ); +lost_lock_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"00002E22" + ) + port map ( + I0 => lost_lock, + I1 => det_ce, + I2 => all_lock, + I3 => all_lock_d, + I4 => all_lock_d0, + O => lost_lock_i_1_n_0 + ); +lost_lock_reg: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => '1', + D => lost_lock_i_1_n_0, + Q => lost_lock, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_tc_1_0_axi_lite_ipif is + port ( + p_0_in : out STD_LOGIC; + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 ); + D : out STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_arready : out STD_LOGIC; + s_axi_rvalid : out STD_LOGIC; + s_axi_bvalid : out STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wvalid : in STD_LOGIC; + s_axi_awvalid : in STD_LOGIC; + s_axi_arvalid : in STD_LOGIC; + aclk : in STD_LOGIC; + out_data : in STD_LOGIC_VECTOR ( 31 downto 0 ); + ipif_Error : in STD_LOGIC; + s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + aresetn : in STD_LOGIC; + s_axi_rready : in STD_LOGIC; + s_axi_bready : in STD_LOGIC; + ipif_RdAck : in STD_LOGIC; + ipif_WrAck : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_tc_1_0_axi_lite_ipif : entity is "axi_lite_ipif"; +end Arty_Z7_20_v_tc_1_0_axi_lite_ipif; + +architecture STRUCTURE of Arty_Z7_20_v_tc_1_0_axi_lite_ipif is +begin +I_SLAVE_ATTACHMENT: entity work.Arty_Z7_20_v_tc_1_0_slave_attachment + port map ( + D(11 downto 0) => D(11 downto 0), + aclk => aclk, + aresetn => aresetn, + ipif_Error => ipif_Error, + ipif_RdAck => ipif_RdAck, + ipif_WrAck => ipif_WrAck, + out_data(31 downto 0) => out_data(31 downto 0), + p_0_in => p_0_in, + s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0), + s_axi_arready => s_axi_arready, + s_axi_arvalid => s_axi_arvalid, + s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0), + s_axi_awvalid => s_axi_awvalid, + s_axi_bready => s_axi_bready, + s_axi_bresp(0) => s_axi_bresp(0), + s_axi_bvalid => s_axi_bvalid, + s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), + s_axi_rready => s_axi_rready, + s_axi_rresp(0) => s_axi_rresp(0), + s_axi_rvalid => s_axi_rvalid, + s_axi_wready => s_axi_wready, + s_axi_wvalid => s_axi_wvalid + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_tc_1_0_video_ctrl is + port ( + aclk : in STD_LOGIC; + aclk_en : in STD_LOGIC; + aresetn : in STD_LOGIC; + vid_aclk : in STD_LOGIC; + vid_aclk_en : in STD_LOGIC; + vid_aresetn : in STD_LOGIC; + reg_update : in STD_LOGIC; + irq : out STD_LOGIC; + resetn_out : out STD_LOGIC; + core_d_out : out STD_LOGIC; + ipif_addr_out : out STD_LOGIC_VECTOR ( 8 downto 0 ); + ipif_rnw_out : out STD_LOGIC; + ipif_cs_out : out STD_LOGIC; + ipif_data_out : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \genr_control_regs[0]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \genr_control_regs[1]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \genr_control_regs[2]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \genr_control_regs[3]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \genr_control_regs[4]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \genr_status_regs[0]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \genr_status_regs[1]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \genr_status_regs[2]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \genr_status_regs[3]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \genr_status_regs[4]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[0]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[1]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[2]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[3]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[4]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[5]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[6]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[7]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[8]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[9]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[10]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[11]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[12]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[13]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[14]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[15]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[16]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[17]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[18]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[19]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[20]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[21]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[22]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[23]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[24]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[25]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[26]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[27]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_control_regs[28]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[0]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[1]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[2]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[3]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[4]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[5]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[6]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[7]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[8]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[9]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[10]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[11]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[12]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[13]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[14]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[15]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[16]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[17]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[18]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[19]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[20]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[21]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[22]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[23]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[24]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[25]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[26]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[27]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \time_status_regs[28]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_control_regs[0]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_control_regs[1]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_control_regs[2]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_control_regs[3]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_control_regs[4]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_control_regs[5]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_control_regs[6]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_control_regs[7]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_control_regs[8]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_control_regs[9]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_control_regs[10]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_control_regs[11]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_control_regs[12]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_control_regs[13]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_control_regs[14]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_control_regs[15]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_control_regs[16]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_status_regs[0]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_status_regs[1]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_status_regs[2]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_status_regs[3]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_status_regs[4]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_status_regs[5]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_status_regs[6]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_status_regs[7]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_status_regs[8]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_status_regs[9]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_status_regs[10]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_status_regs[11]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_status_regs[12]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_status_regs[13]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_status_regs[14]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_status_regs[15]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \core_status_regs[16]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_arvalid : in STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rvalid : out STD_LOGIC; + s_axi_rready : in STD_LOGIC + ); + attribute C_COREGEN_PATCH : integer; + attribute C_COREGEN_PATCH of Arty_Z7_20_v_tc_1_0_video_ctrl : entity is 0; + attribute C_CORE_AXI_WRITE : string; + attribute C_CORE_AXI_WRITE of Arty_Z7_20_v_tc_1_0_video_ctrl : entity is "544'b0000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111"; + attribute C_CORE_DBUFFER : string; + attribute C_CORE_DBUFFER of Arty_Z7_20_v_tc_1_0_video_ctrl : entity is "544'b0000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000000000000000000000000000000"; + attribute C_CORE_DEFAULT : string; + attribute C_CORE_DEFAULT of Arty_Z7_20_v_tc_1_0_video_ctrl : entity is "544'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute C_CORE_NUM_REGS : integer; + attribute C_CORE_NUM_REGS of Arty_Z7_20_v_tc_1_0_video_ctrl : entity is 17; + attribute C_FAMILY : string; + attribute C_FAMILY of Arty_Z7_20_v_tc_1_0_video_ctrl : entity is "virtex5"; + attribute C_GENR_AXI_WRITE : string; + attribute C_GENR_AXI_WRITE of Arty_Z7_20_v_tc_1_0_video_ctrl : entity is "160'b1100011111111111111011110010111111111111111111110011111100000000000000000011111100000000000000001111111111111111001111110000000000000000000000000000000000000000"; + attribute C_GENR_DBUFFER : string; + attribute C_GENR_DBUFFER of Arty_Z7_20_v_tc_1_0_video_ctrl : entity is "160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute C_GENR_DEFAULT : string; + attribute C_GENR_DEFAULT of Arty_Z7_20_v_tc_1_0_video_ctrl : entity is "160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute C_GENR_NUM_REGS : integer; + attribute C_GENR_NUM_REGS of Arty_Z7_20_v_tc_1_0_video_ctrl : entity is 5; + attribute C_GENR_SELFCLR : string; + attribute C_GENR_SELFCLR of Arty_Z7_20_v_tc_1_0_video_ctrl : entity is "256'b0000000000000000000000000000000011111111111111111111111111111111111111111111111111111111111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute C_HAS_AXI4_LITE : integer; + attribute C_HAS_AXI4_LITE of Arty_Z7_20_v_tc_1_0_video_ctrl : entity is 1; + attribute C_HAS_IRQ : integer; + attribute C_HAS_IRQ of Arty_Z7_20_v_tc_1_0_video_ctrl : entity is 1; + attribute C_IS_EVAL : string; + attribute C_IS_EVAL of Arty_Z7_20_v_tc_1_0_video_ctrl : entity is "FALSE"; + attribute C_REVISION_NUMBER : integer; + attribute C_REVISION_NUMBER of Arty_Z7_20_v_tc_1_0_video_ctrl : entity is 11; + attribute C_SRESET_LENGTH : integer; + attribute C_SRESET_LENGTH of Arty_Z7_20_v_tc_1_0_video_ctrl : entity is 2; + attribute C_S_AXI_ADDR_WIDTH : integer; + attribute C_S_AXI_ADDR_WIDTH of Arty_Z7_20_v_tc_1_0_video_ctrl : entity is 9; + attribute C_S_AXI_DATA_WIDTH : integer; + attribute C_S_AXI_DATA_WIDTH of Arty_Z7_20_v_tc_1_0_video_ctrl : entity is 32; + attribute C_TIMEOUT_HOURS : integer; + attribute C_TIMEOUT_HOURS of Arty_Z7_20_v_tc_1_0_video_ctrl : entity is 8; + attribute C_TIMEOUT_MINS : integer; + attribute C_TIMEOUT_MINS of Arty_Z7_20_v_tc_1_0_video_ctrl : entity is 0; + attribute C_TIME_AXI_WRITE : string; + attribute C_TIME_AXI_WRITE of Arty_Z7_20_v_tc_1_0_video_ctrl : entity is "928'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111111110001111111111111000000000000000000000000000000000000000000000000000000111100111100000000000000000000000001111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111"; + attribute C_TIME_DBUFFER : string; + attribute C_TIME_DBUFFER of Arty_Z7_20_v_tc_1_0_video_ctrl : entity is "928'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111111110001111111111111000000000000000000000000000000000000000000000000000000111000000000000000000000000000000000111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111"; + attribute C_TIME_DEFAULT : string; + attribute C_TIME_DEFAULT of Arty_Z7_20_v_tc_1_0_video_ctrl : entity is "928'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010110100000000010100000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000001111111000000000000000000000110011100100000001011101110000000101110111000000101100101100000010101101110000001010000000000000101000000000000001011011001000000101101010000000101000000000000010100000000000001010000000000000101000000000000001011011001000000101101010000000101000000000000010100000000"; + attribute C_TIME_NUM_REGS : integer; + attribute C_TIME_NUM_REGS of Arty_Z7_20_v_tc_1_0_video_ctrl : entity is 29; + attribute C_VERSION_MAJOR : integer; + attribute C_VERSION_MAJOR of Arty_Z7_20_v_tc_1_0_video_ctrl : entity is 6; + attribute C_VERSION_MINOR : integer; + attribute C_VERSION_MINOR of Arty_Z7_20_v_tc_1_0_video_ctrl : entity is 1; + attribute C_VERSION_REVISION : integer; + attribute C_VERSION_REVISION of Arty_Z7_20_v_tc_1_0_video_ctrl : entity is 0; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_tc_1_0_video_ctrl : entity is "video_ctrl"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of Arty_Z7_20_v_tc_1_0_video_ctrl : entity is "yes"; +end Arty_Z7_20_v_tc_1_0_video_ctrl; + +architecture STRUCTURE of Arty_Z7_20_v_tc_1_0_video_ctrl is + signal \\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.CORE_MUX0_n_0\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_0\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_1\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_34\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_35\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_36\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_37\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_38\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_39\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_40\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_41\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_42\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_43\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_44\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_45\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_46\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_47\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_48\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_49\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_50\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_51\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_52\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_53\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_54\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_55\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_56\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_57\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_58\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_59\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_60\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_61\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_62\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_63\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_64\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_65\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_66\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_67\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_68\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_69\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_70\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_71\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_72\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_73\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_74\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_75\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_76\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_77\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_78\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_79\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_80\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_81\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_82\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_83\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_84\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_85\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_86\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_87\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_88\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_89\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_90\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_91\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_92\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_93\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_94\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_95\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_96\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.GENR_MUX0_n_97\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2PROCCLK_I_n_36\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_0\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_110\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_137\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_138\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_139\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_140\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_141\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_142\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_143\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_144\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_145\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_146\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_147\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_148\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_149\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_150\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_151\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_152\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_153\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_154\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_155\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_156\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_157\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_158\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_159\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_160\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_161\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_162\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_163\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_164\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_165\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_166\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_167\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_168\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_169\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_170\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_171\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_172\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_173\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_174\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_175\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_176\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_177\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_178\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_179\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_180\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_181\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_182\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_183\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_184\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_185\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_186\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_187\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_188\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_189\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_190\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_191\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_192\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_193\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_194\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_195\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_196\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_197\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_198\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_199\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_200\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_201\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_202\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_203\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_204\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_205\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_206\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_207\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_208\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_209\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_210\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_211\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_212\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_213\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_214\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_215\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_216\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_217\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_218\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_219\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_220\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_221\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_222\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_223\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_224\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_225\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_226\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_227\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_228\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_229\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_230\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_231\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_232\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_233\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_234\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_235\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_236\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_237\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_238\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_239\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_240\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_241\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_242\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_243\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_244\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_245\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_246\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_247\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_248\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_249\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_250\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_251\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_252\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_253\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_254\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_255\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_256\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_257\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_258\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_259\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_260\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_261\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_262\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_263\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_264\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_265\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_266\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_267\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_268\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_269\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_270\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_271\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_272\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_273\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_274\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_275\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_276\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_277\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_278\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_279\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_280\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_281\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_282\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_283\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_284\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_285\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_286\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_287\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_288\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_289\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_290\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_291\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_292\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_293\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_294\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_295\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_296\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_297\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_298\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_299\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_300\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_301\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_302\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_303\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_304\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_305\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_306\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_307\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_308\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_309\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_310\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_311\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_312\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_313\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_314\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_315\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_316\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_317\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_318\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_319\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_320\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_321\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_322\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_323\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_324\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_325\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_326\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_327\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_328\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_329\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_330\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_331\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_332\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_333\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_334\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_335\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_336\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_337\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_338\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_339\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_34\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_340\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_341\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_342\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_343\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_344\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_345\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_346\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_347\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_348\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_349\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_35\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_350\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_351\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_352\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_353\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_354\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_355\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_356\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_357\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_358\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_359\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_36\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_360\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_361\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_362\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_363\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_364\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_365\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_366\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_367\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_368\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_369\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_37\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_370\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_371\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_372\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_373\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_374\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_375\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_376\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_377\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_378\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_379\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_38\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_380\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_381\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_382\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_383\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_384\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_385\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_386\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_387\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_388\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_389\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_39\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_390\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_391\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_392\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_393\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_394\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_395\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_396\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_397\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_398\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_399\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_40\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_400\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_401\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_402\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_403\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_404\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_405\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_406\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_407\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_408\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_409\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_41\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_410\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_411\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_412\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_413\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_414\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_415\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_416\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_417\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_418\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_419\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_42\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_420\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_421\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_422\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_423\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_424\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_425\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_426\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_427\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_428\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_429\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_43\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_430\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_431\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_432\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_433\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_434\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_435\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_436\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_437\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_438\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_439\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_44\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_440\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_441\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_442\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_443\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_444\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_445\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_446\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_447\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_448\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_449\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_45\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_450\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_451\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_452\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_453\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_454\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_455\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_456\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_457\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_458\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_459\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_46\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_460\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_461\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_462\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_463\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_464\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_465\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_466\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_467\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_468\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_469\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_47\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_470\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_471\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_472\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_473\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_474\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_475\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_476\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_477\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_478\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_479\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_48\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_480\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_481\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_482\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_483\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_484\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_485\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_486\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_487\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_488\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_489\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_49\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_490\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_491\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_492\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_493\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_494\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_495\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_496\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_497\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_498\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_499\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_50\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_500\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_501\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_502\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_503\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_504\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_505\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_506\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_507\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_508\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_509\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_51\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_510\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_511\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_512\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_513\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_514\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_515\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_516\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_517\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_518\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_519\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_52\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_520\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_521\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_522\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_523\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_524\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_525\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_526\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_527\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_528\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_529\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_53\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_530\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_531\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_532\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_533\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_534\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_535\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_536\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_537\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_538\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_539\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_54\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_540\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_541\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_542\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_543\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_544\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_545\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_546\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_547\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_548\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_549\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_55\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_550\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_551\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_552\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_553\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_554\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_555\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_556\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_557\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_558\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_559\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_56\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_560\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_561\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_562\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_563\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_564\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_565\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_566\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_567\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_568\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_569\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_57\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_570\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_571\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_572\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_573\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_574\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_575\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_576\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_577\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_578\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_579\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_58\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_580\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_581\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_582\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_583\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_584\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_585\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_586\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_587\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_588\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_589\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_59\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_590\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_591\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_592\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_593\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_594\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_595\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_596\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_597\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_598\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_599\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_60\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_600\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_601\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_602\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_603\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_604\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_605\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_606\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_607\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_608\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_609\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_61\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_610\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_611\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_612\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_613\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_614\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_615\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_616\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_617\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_618\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_619\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_62\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_620\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_621\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_622\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_623\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_624\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_625\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_626\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_627\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_628\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_629\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_63\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_630\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_631\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_632\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_633\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_634\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_635\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_636\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_637\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_638\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_639\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_64\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_640\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_641\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_642\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_643\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_644\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_645\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_646\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_647\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_648\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_649\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_65\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_650\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_66\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_67\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_68\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_69\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_70\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_71\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_72\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_73\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_74\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_75\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_76\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_77\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_78\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_79\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_80\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_81\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_82\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_83\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_84\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_85\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_86\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_87\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_88\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_89\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_90\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_91\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_92\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.read_ack_d_reg[2]_srl4___AXI4_LITE_INTERFACE.read_ack_d_reg_r_1_n_0\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.read_ack_d_reg[3]_AXI4_LITE_INTERFACE.read_ack_d_reg_r_2_n_0\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.read_ack_d_reg_gate_n_0\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.read_ack_d_reg_r_0_n_0\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.read_ack_d_reg_r_1_n_0\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.read_ack_d_reg_r_2_n_0\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.read_ack_d_reg_r_n_0\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.read_ack_reg_r_n_0\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.write_ack_e1_i_1_n_0\ : STD_LOGIC; + signal \AXI4_LITE_INTERFACE.write_ack_int_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[0]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[10]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[11]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[12]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[13]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[14]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[15]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[16]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[16]_i_2_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[17]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[17]_i_2_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[18]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[18]_i_2_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[19]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[19]_i_2_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[1]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[20]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[20]_i_2_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[21]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[21]_i_2_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[22]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[23]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[24]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[25]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[26]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[27]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[28]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[29]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[2]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[30]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[31]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[3]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[4]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[5]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[6]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[7]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[8]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_err[9]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[0]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[10]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[10]_i_2_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[11]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[11]_i_2_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[12]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[12]_i_2_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[13]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[13]_i_2_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[14]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[15]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[16]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[16]_i_2_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[17]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[17]_i_2_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[18]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[18]_i_2_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[19]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[19]_i_2_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[1]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[20]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[20]_i_2_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[21]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[21]_i_2_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[22]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[22]_i_2_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[23]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[23]_i_2_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[24]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[24]_i_2_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[25]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[25]_i_2_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[26]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[26]_i_2_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[27]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[27]_i_2_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[28]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[28]_i_2_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[29]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[29]_i_2_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[2]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[30]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[30]_i_2_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[31]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[31]_i_2_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[3]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[4]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[5]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[6]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[7]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[8]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[8]_i_2_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[9]_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat[9]_i_2_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.intr_stat_reg_n_0_[31]\ : STD_LOGIC; + signal \GEN_HAS_IRQ.irq_i_10_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.irq_i_1_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.irq_i_2_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.irq_i_3_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.irq_i_4_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.irq_i_5_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.irq_i_6_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.irq_i_7_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.irq_i_8_n_0\ : STD_LOGIC; + signal \GEN_HAS_IRQ.irq_i_9_n_0\ : STD_LOGIC; + signal \core_control_regs2_int[0]\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \core_control_regs2_int[10]\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \core_control_regs2_int[11]\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \core_control_regs2_int[12]\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \core_control_regs2_int[13]\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \core_control_regs2_int[14]\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \core_control_regs2_int[15]\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \core_control_regs2_int[1]\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \core_control_regs2_int[2]\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \core_control_regs2_int[3]\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \core_control_regs2_int[4]\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \core_control_regs2_int[5]\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \core_control_regs2_int[6]\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \core_control_regs2_int[7]\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \core_control_regs2_int[8]\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \core_control_regs2_int[9]\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^core_control_regs[0]\ : STD_LOGIC_VECTOR ( 26 downto 0 ); + signal \^core_control_regs[10]\ : STD_LOGIC_VECTOR ( 26 downto 0 ); + signal \^core_control_regs[11]\ : STD_LOGIC_VECTOR ( 26 downto 0 ); + signal \^core_control_regs[12]\ : STD_LOGIC_VECTOR ( 26 downto 0 ); + signal \^core_control_regs[13]\ : STD_LOGIC_VECTOR ( 26 downto 0 ); + signal \^core_control_regs[14]\ : STD_LOGIC_VECTOR ( 26 downto 0 ); + signal \^core_control_regs[15]\ : STD_LOGIC_VECTOR ( 26 downto 0 ); + signal \^core_control_regs[16]\ : STD_LOGIC_VECTOR ( 26 downto 0 ); + signal \^core_control_regs[1]\ : STD_LOGIC_VECTOR ( 26 downto 0 ); + signal \^core_control_regs[2]\ : STD_LOGIC_VECTOR ( 26 downto 0 ); + signal \^core_control_regs[3]\ : STD_LOGIC_VECTOR ( 26 downto 0 ); + signal \^core_control_regs[4]\ : STD_LOGIC_VECTOR ( 26 downto 0 ); + signal \^core_control_regs[5]\ : STD_LOGIC_VECTOR ( 26 downto 0 ); + signal \^core_control_regs[6]\ : STD_LOGIC_VECTOR ( 26 downto 0 ); + signal \^core_control_regs[7]\ : STD_LOGIC_VECTOR ( 26 downto 0 ); + signal \^core_control_regs[8]\ : STD_LOGIC_VECTOR ( 26 downto 0 ); + signal \^core_control_regs[9]\ : STD_LOGIC_VECTOR ( 26 downto 0 ); + signal \core_control_regs_int[0]\ : STD_LOGIC_VECTOR ( 26 to 26 ); + signal \core_control_regs_int[10]\ : STD_LOGIC_VECTOR ( 26 to 26 ); + signal \core_control_regs_int[11]\ : STD_LOGIC_VECTOR ( 26 to 26 ); + signal \core_control_regs_int[12]\ : STD_LOGIC_VECTOR ( 26 to 26 ); + signal \core_control_regs_int[13]\ : STD_LOGIC_VECTOR ( 26 to 26 ); + signal \core_control_regs_int[14]\ : STD_LOGIC_VECTOR ( 26 to 26 ); + signal \core_control_regs_int[15]\ : STD_LOGIC_VECTOR ( 26 to 26 ); + signal \core_control_regs_int[16]\ : STD_LOGIC_VECTOR ( 26 to 26 ); + signal \core_control_regs_int[1]\ : STD_LOGIC_VECTOR ( 26 to 26 ); + signal \core_control_regs_int[2]\ : STD_LOGIC_VECTOR ( 26 to 26 ); + signal \core_control_regs_int[3]\ : STD_LOGIC_VECTOR ( 26 to 26 ); + signal \core_control_regs_int[4]\ : STD_LOGIC_VECTOR ( 26 to 26 ); + signal \core_control_regs_int[5]\ : STD_LOGIC_VECTOR ( 26 to 26 ); + signal \core_control_regs_int[6]\ : STD_LOGIC_VECTOR ( 26 to 26 ); + signal \core_control_regs_int[7]\ : STD_LOGIC_VECTOR ( 26 to 26 ); + signal \core_control_regs_int[8]\ : STD_LOGIC_VECTOR ( 26 to 26 ); + signal \core_control_regs_int[9]\ : STD_LOGIC_VECTOR ( 26 to 26 ); + signal core_data : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal core_regs : STD_LOGIC_VECTOR ( 506 downto 1 ); + signal \^genr_control_regs[0]\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \^genr_control_regs[1]\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \^genr_control_regs[2]\ : STD_LOGIC_VECTOR ( 21 downto 16 ); + signal \^genr_control_regs[3]\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \genr_control_regs_int[0]\ : STD_LOGIC_VECTOR ( 31 to 31 ); + signal \genr_control_regs_int[3]\ : STD_LOGIC_VECTOR ( 31 to 31 ); + signal genr_data : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal genr_regs : STD_LOGIC_VECTOR ( 1180 downto 897 ); + signal \genr_status_regs_int_reg[1]\ : STD_LOGIC_VECTOR ( 30 downto 0 ); + signal intr_err : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal intr_err_clr_d : STD_LOGIC_VECTOR ( 21 downto 16 ); + signal intr_err_set_d : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal intr_stat_clr_d : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal intr_stat_set_d : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ipif_Addr : STD_LOGIC_VECTOR ( 8 downto 0 ); + attribute MAX_FANOUT : string; + attribute MAX_FANOUT of ipif_Addr : signal is "128"; + attribute RTL_MAX_FANOUT : string; + attribute RTL_MAX_FANOUT of ipif_Addr : signal is "found"; + signal ipif_Error : STD_LOGIC; + signal ipif_RdAck : STD_LOGIC; + signal ipif_RdData : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ipif_WrAck : STD_LOGIC; + signal \^ipif_data_out\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal ipif_proc_Addr_int : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal ipif_proc_CS : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ipif_proc_RNW : STD_LOGIC; + signal p_0_in : STD_LOGIC; + signal p_0_in_0 : STD_LOGIC; + signal p_10_in : STD_LOGIC; + signal p_11_in : STD_LOGIC; + signal p_12_in : STD_LOGIC; + signal p_13_in : STD_LOGIC; + signal p_143_out : STD_LOGIC_VECTOR ( 33 downto 0 ); + signal p_14_in : STD_LOGIC; + signal p_15_in : STD_LOGIC; + signal p_16_in : STD_LOGIC; + signal p_17_in : STD_LOGIC; + signal p_18_in : STD_LOGIC; + signal p_19_in : STD_LOGIC; + signal p_1_in : STD_LOGIC; + signal p_20_in : STD_LOGIC; + signal p_21_in : STD_LOGIC; + signal p_22_in : STD_LOGIC; + signal p_23_in : STD_LOGIC; + signal p_24_in : STD_LOGIC; + signal p_2_in : STD_LOGIC; + signal p_2_out : STD_LOGIC_VECTOR ( 6 to 6 ); + signal p_3_in : STD_LOGIC; + signal p_456_out : STD_LOGIC; + signal p_4_in : STD_LOGIC; + signal p_526_out : STD_LOGIC; + signal p_528_out : STD_LOGIC; + signal p_533_out : STD_LOGIC; + signal p_534_out : STD_LOGIC; + signal p_535_out : STD_LOGIC; + signal p_5_in : STD_LOGIC; + signal p_5_out : STD_LOGIC_VECTOR ( 9 downto 7 ); + signal p_6_in : STD_LOGIC; + signal p_7_in : STD_LOGIC; + signal p_8_in : STD_LOGIC; + signal p_8_out : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal p_9_in : STD_LOGIC; + signal proc_sync1 : STD_LOGIC_VECTOR ( 44 downto 0 ); + signal read_ack_d : STD_LOGIC_VECTOR ( 4 to 4 ); + signal read_ack_d1 : STD_LOGIC; + signal read_ack_d2 : STD_LOGIC; + signal \^resetn_out\ : STD_LOGIC; + signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 1 to 1 ); + signal \^s_axi_rresp\ : STD_LOGIC_VECTOR ( 1 to 1 ); + signal \^s_axi_wready\ : STD_LOGIC; + signal \time_control_regs2_int[16]\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \time_control_regs2_int[20]\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \time_control_regs2_int[21]\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \time_control_regs2_int[22]\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \time_control_regs2_int[23]\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \time_control_regs2_int[24]\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \time_control_regs2_int[25]\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \time_control_regs2_int[26]\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \time_control_regs2_int[27]\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \time_control_regs2_int[28]\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^time_control_regs[16]\ : STD_LOGIC_VECTOR ( 28 downto 0 ); + signal \^time_control_regs[18]\ : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal \^time_control_regs[19]\ : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal \^time_control_regs[20]\ : STD_LOGIC_VECTOR ( 28 downto 0 ); + signal \^time_control_regs[21]\ : STD_LOGIC_VECTOR ( 28 downto 0 ); + signal \^time_control_regs[22]\ : STD_LOGIC_VECTOR ( 28 downto 0 ); + signal \^time_control_regs[23]\ : STD_LOGIC_VECTOR ( 28 downto 0 ); + signal \^time_control_regs[24]\ : STD_LOGIC_VECTOR ( 28 downto 0 ); + signal \^time_control_regs[25]\ : STD_LOGIC_VECTOR ( 28 downto 0 ); + signal \^time_control_regs[26]\ : STD_LOGIC_VECTOR ( 28 downto 0 ); + signal \^time_control_regs[27]\ : STD_LOGIC_VECTOR ( 28 downto 0 ); + signal \^time_control_regs[28]\ : STD_LOGIC_VECTOR ( 28 downto 0 ); + signal \time_control_regs_int[16]\ : STD_LOGIC_VECTOR ( 28 to 28 ); + signal \time_control_regs_int[18]\ : STD_LOGIC_VECTOR ( 6 to 6 ); + signal \time_control_regs_int[20]\ : STD_LOGIC_VECTOR ( 28 to 28 ); + signal \time_control_regs_int[21]\ : STD_LOGIC_VECTOR ( 28 to 28 ); + signal \time_control_regs_int[22]\ : STD_LOGIC_VECTOR ( 28 to 28 ); + signal \time_control_regs_int[23]\ : STD_LOGIC_VECTOR ( 28 to 28 ); + signal \time_control_regs_int[24]\ : STD_LOGIC_VECTOR ( 28 to 28 ); + signal \time_control_regs_int[25]\ : STD_LOGIC_VECTOR ( 28 to 28 ); + signal \time_control_regs_int[26]\ : STD_LOGIC_VECTOR ( 28 to 28 ); + signal \time_control_regs_int[27]\ : STD_LOGIC_VECTOR ( 28 to 28 ); + signal \time_control_regs_int[28]\ : STD_LOGIC_VECTOR ( 28 to 28 ); + signal write_ack : STD_LOGIC; + signal write_ack_d1 : STD_LOGIC; + signal write_ack_d2 : STD_LOGIC; + signal write_ack_e1 : STD_LOGIC; + signal write_ack_e2 : STD_LOGIC; + signal write_ack_int : STD_LOGIC; + attribute srl_bus_name : string; + attribute srl_bus_name of \AXI4_LITE_INTERFACE.read_ack_d_reg[2]_srl4___AXI4_LITE_INTERFACE.read_ack_d_reg_r_1\ : label is "U0/U_VIDEO_CTRL/\AXI4_LITE_INTERFACE.read_ack_d_reg "; + attribute srl_name : string; + attribute srl_name of \AXI4_LITE_INTERFACE.read_ack_d_reg[2]_srl4___AXI4_LITE_INTERFACE.read_ack_d_reg_r_1\ : label is "U0/U_VIDEO_CTRL/\AXI4_LITE_INTERFACE.read_ack_d_reg[2]_srl4___AXI4_LITE_INTERFACE.read_ack_d_reg_r_1 "; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \AXI4_LITE_INTERFACE.write_ack_i_1\ : label is "soft_lutpair269"; + attribute SOFT_HLUTNM of \AXI4_LITE_INTERFACE.write_ack_int_i_1\ : label is "soft_lutpair269"; +begin + \core_control_regs[0]\(31) <= \\; + \core_control_regs[0]\(30) <= \\; + \core_control_regs[0]\(29) <= \\; + \core_control_regs[0]\(28) <= \\; + \core_control_regs[0]\(27) <= \\; + \core_control_regs[0]\(26 downto 16) <= \^core_control_regs[0]\(26 downto 16); + \core_control_regs[0]\(15) <= \\; + \core_control_regs[0]\(14) <= \\; + \core_control_regs[0]\(13) <= \\; + \core_control_regs[0]\(12) <= \\; + \core_control_regs[0]\(11 downto 0) <= \^core_control_regs[0]\(11 downto 0); + \core_control_regs[10]\(31) <= \\; + \core_control_regs[10]\(30) <= \\; + \core_control_regs[10]\(29) <= \\; + \core_control_regs[10]\(28) <= \\; + \core_control_regs[10]\(27) <= \\; + \core_control_regs[10]\(26 downto 16) <= \^core_control_regs[10]\(26 downto 16); + \core_control_regs[10]\(15) <= \\; + \core_control_regs[10]\(14) <= \\; + \core_control_regs[10]\(13) <= \\; + \core_control_regs[10]\(12) <= \\; + \core_control_regs[10]\(11 downto 0) <= \^core_control_regs[10]\(11 downto 0); + \core_control_regs[11]\(31) <= \\; + \core_control_regs[11]\(30) <= \\; + \core_control_regs[11]\(29) <= \\; + \core_control_regs[11]\(28) <= \\; + \core_control_regs[11]\(27) <= \\; + \core_control_regs[11]\(26 downto 16) <= \^core_control_regs[11]\(26 downto 16); + \core_control_regs[11]\(15) <= \\; + \core_control_regs[11]\(14) <= \\; + \core_control_regs[11]\(13) <= \\; + \core_control_regs[11]\(12) <= \\; + \core_control_regs[11]\(11 downto 0) <= \^core_control_regs[11]\(11 downto 0); + \core_control_regs[12]\(31) <= \\; + \core_control_regs[12]\(30) <= \\; + \core_control_regs[12]\(29) <= \\; + \core_control_regs[12]\(28) <= \\; + \core_control_regs[12]\(27) <= \\; + \core_control_regs[12]\(26 downto 16) <= \^core_control_regs[12]\(26 downto 16); + \core_control_regs[12]\(15) <= \\; + \core_control_regs[12]\(14) <= \\; + \core_control_regs[12]\(13) <= \\; + \core_control_regs[12]\(12) <= \\; + \core_control_regs[12]\(11 downto 0) <= \^core_control_regs[12]\(11 downto 0); + \core_control_regs[13]\(31) <= \\; + \core_control_regs[13]\(30) <= \\; + \core_control_regs[13]\(29) <= \\; + \core_control_regs[13]\(28) <= \\; + \core_control_regs[13]\(27) <= \\; + \core_control_regs[13]\(26 downto 16) <= \^core_control_regs[13]\(26 downto 16); + \core_control_regs[13]\(15) <= \\; + \core_control_regs[13]\(14) <= \\; + \core_control_regs[13]\(13) <= \\; + \core_control_regs[13]\(12) <= \\; + \core_control_regs[13]\(11 downto 0) <= \^core_control_regs[13]\(11 downto 0); + \core_control_regs[14]\(31) <= \\; + \core_control_regs[14]\(30) <= \\; + \core_control_regs[14]\(29) <= \\; + \core_control_regs[14]\(28) <= \\; + \core_control_regs[14]\(27) <= \\; + \core_control_regs[14]\(26 downto 16) <= \^core_control_regs[14]\(26 downto 16); + \core_control_regs[14]\(15) <= \\; + \core_control_regs[14]\(14) <= \\; + \core_control_regs[14]\(13) <= \\; + \core_control_regs[14]\(12) <= \\; + \core_control_regs[14]\(11 downto 0) <= \^core_control_regs[14]\(11 downto 0); + \core_control_regs[15]\(31) <= \\; + \core_control_regs[15]\(30) <= \\; + \core_control_regs[15]\(29) <= \\; + \core_control_regs[15]\(28) <= \\; + \core_control_regs[15]\(27) <= \\; + \core_control_regs[15]\(26 downto 16) <= \^core_control_regs[15]\(26 downto 16); + \core_control_regs[15]\(15) <= \\; + \core_control_regs[15]\(14) <= \\; + \core_control_regs[15]\(13) <= \\; + \core_control_regs[15]\(12) <= \\; + \core_control_regs[15]\(11 downto 0) <= \^core_control_regs[15]\(11 downto 0); + \core_control_regs[16]\(31) <= \\; + \core_control_regs[16]\(30) <= \\; + \core_control_regs[16]\(29) <= \\; + \core_control_regs[16]\(28) <= \\; + \core_control_regs[16]\(27) <= \\; + \core_control_regs[16]\(26 downto 16) <= \^core_control_regs[16]\(26 downto 16); + \core_control_regs[16]\(15) <= \\; + \core_control_regs[16]\(14) <= \\; + \core_control_regs[16]\(13) <= \\; + \core_control_regs[16]\(12) <= \\; + \core_control_regs[16]\(11 downto 0) <= \^core_control_regs[16]\(11 downto 0); + \core_control_regs[1]\(31) <= \\; + \core_control_regs[1]\(30) <= \\; + \core_control_regs[1]\(29) <= \\; + \core_control_regs[1]\(28) <= \\; + \core_control_regs[1]\(27) <= \\; + \core_control_regs[1]\(26 downto 16) <= \^core_control_regs[1]\(26 downto 16); + \core_control_regs[1]\(15) <= \\; + \core_control_regs[1]\(14) <= \\; + \core_control_regs[1]\(13) <= \\; + \core_control_regs[1]\(12) <= \\; + \core_control_regs[1]\(11 downto 0) <= \^core_control_regs[1]\(11 downto 0); + \core_control_regs[2]\(31) <= \\; + \core_control_regs[2]\(30) <= \\; + \core_control_regs[2]\(29) <= \\; + \core_control_regs[2]\(28) <= \\; + \core_control_regs[2]\(27) <= \\; + \core_control_regs[2]\(26 downto 16) <= \^core_control_regs[2]\(26 downto 16); + \core_control_regs[2]\(15) <= \\; + \core_control_regs[2]\(14) <= \\; + \core_control_regs[2]\(13) <= \\; + \core_control_regs[2]\(12) <= \\; + \core_control_regs[2]\(11 downto 0) <= \^core_control_regs[2]\(11 downto 0); + \core_control_regs[3]\(31) <= \\; + \core_control_regs[3]\(30) <= \\; + \core_control_regs[3]\(29) <= \\; + \core_control_regs[3]\(28) <= \\; + \core_control_regs[3]\(27) <= \\; + \core_control_regs[3]\(26 downto 16) <= \^core_control_regs[3]\(26 downto 16); + \core_control_regs[3]\(15) <= \\; + \core_control_regs[3]\(14) <= \\; + \core_control_regs[3]\(13) <= \\; + \core_control_regs[3]\(12) <= \\; + \core_control_regs[3]\(11 downto 0) <= \^core_control_regs[3]\(11 downto 0); + \core_control_regs[4]\(31) <= \\; + \core_control_regs[4]\(30) <= \\; + \core_control_regs[4]\(29) <= \\; + \core_control_regs[4]\(28) <= \\; + \core_control_regs[4]\(27) <= \\; + \core_control_regs[4]\(26 downto 16) <= \^core_control_regs[4]\(26 downto 16); + \core_control_regs[4]\(15) <= \\; + \core_control_regs[4]\(14) <= \\; + \core_control_regs[4]\(13) <= \\; + \core_control_regs[4]\(12) <= \\; + \core_control_regs[4]\(11 downto 0) <= \^core_control_regs[4]\(11 downto 0); + \core_control_regs[5]\(31) <= \\; + \core_control_regs[5]\(30) <= \\; + \core_control_regs[5]\(29) <= \\; + \core_control_regs[5]\(28) <= \\; + \core_control_regs[5]\(27) <= \\; + \core_control_regs[5]\(26 downto 16) <= \^core_control_regs[5]\(26 downto 16); + \core_control_regs[5]\(15) <= \\; + \core_control_regs[5]\(14) <= \\; + \core_control_regs[5]\(13) <= \\; + \core_control_regs[5]\(12) <= \\; + \core_control_regs[5]\(11 downto 0) <= \^core_control_regs[5]\(11 downto 0); + \core_control_regs[6]\(31) <= \\; + \core_control_regs[6]\(30) <= \\; + \core_control_regs[6]\(29) <= \\; + \core_control_regs[6]\(28) <= \\; + \core_control_regs[6]\(27) <= \\; + \core_control_regs[6]\(26 downto 16) <= \^core_control_regs[6]\(26 downto 16); + \core_control_regs[6]\(15) <= \\; + \core_control_regs[6]\(14) <= \\; + \core_control_regs[6]\(13) <= \\; + \core_control_regs[6]\(12) <= \\; + \core_control_regs[6]\(11 downto 0) <= \^core_control_regs[6]\(11 downto 0); + \core_control_regs[7]\(31) <= \\; + \core_control_regs[7]\(30) <= \\; + \core_control_regs[7]\(29) <= \\; + \core_control_regs[7]\(28) <= \\; + \core_control_regs[7]\(27) <= \\; + \core_control_regs[7]\(26 downto 16) <= \^core_control_regs[7]\(26 downto 16); + \core_control_regs[7]\(15) <= \\; + \core_control_regs[7]\(14) <= \\; + \core_control_regs[7]\(13) <= \\; + \core_control_regs[7]\(12) <= \\; + \core_control_regs[7]\(11 downto 0) <= \^core_control_regs[7]\(11 downto 0); + \core_control_regs[8]\(31) <= \\; + \core_control_regs[8]\(30) <= \\; + \core_control_regs[8]\(29) <= \\; + \core_control_regs[8]\(28) <= \\; + \core_control_regs[8]\(27) <= \\; + \core_control_regs[8]\(26 downto 16) <= \^core_control_regs[8]\(26 downto 16); + \core_control_regs[8]\(15) <= \\; + \core_control_regs[8]\(14) <= \\; + \core_control_regs[8]\(13) <= \\; + \core_control_regs[8]\(12) <= \\; + \core_control_regs[8]\(11 downto 0) <= \^core_control_regs[8]\(11 downto 0); + \core_control_regs[9]\(31) <= \\; + \core_control_regs[9]\(30) <= \\; + \core_control_regs[9]\(29) <= \\; + \core_control_regs[9]\(28) <= \\; + \core_control_regs[9]\(27) <= \\; + \core_control_regs[9]\(26 downto 16) <= \^core_control_regs[9]\(26 downto 16); + \core_control_regs[9]\(15) <= \\; + \core_control_regs[9]\(14) <= \\; + \core_control_regs[9]\(13) <= \\; + \core_control_regs[9]\(12) <= \\; + \core_control_regs[9]\(11 downto 0) <= \^core_control_regs[9]\(11 downto 0); + core_d_out <= \\; + \genr_control_regs[0]\(31 downto 30) <= \^genr_control_regs[0]\(31 downto 30); + \genr_control_regs[0]\(29) <= \\; + \genr_control_regs[0]\(28) <= \\; + \genr_control_regs[0]\(27) <= \\; + \genr_control_regs[0]\(26 downto 13) <= \^genr_control_regs[0]\(26 downto 13); + \genr_control_regs[0]\(12) <= \\; + \genr_control_regs[0]\(11 downto 8) <= \^genr_control_regs[0]\(11 downto 8); + \genr_control_regs[0]\(7) <= \\; + \genr_control_regs[0]\(6) <= \\; + \genr_control_regs[0]\(5) <= \^genr_control_regs[0]\(5); + \genr_control_regs[0]\(4) <= \\; + \genr_control_regs[0]\(3 downto 0) <= \^genr_control_regs[0]\(3 downto 0); + \genr_control_regs[1]\(31 downto 16) <= \^genr_control_regs[1]\(31 downto 16); + \genr_control_regs[1]\(15) <= \\; + \genr_control_regs[1]\(14) <= \\; + \genr_control_regs[1]\(13 downto 8) <= \^genr_control_regs[1]\(13 downto 8); + \genr_control_regs[1]\(7) <= \\; + \genr_control_regs[1]\(6) <= \\; + \genr_control_regs[1]\(5) <= \\; + \genr_control_regs[1]\(4) <= \\; + \genr_control_regs[1]\(3) <= \\; + \genr_control_regs[1]\(2) <= \\; + \genr_control_regs[1]\(1) <= \\; + \genr_control_regs[1]\(0) <= \\; + \genr_control_regs[2]\(31) <= \\; + \genr_control_regs[2]\(30) <= \\; + \genr_control_regs[2]\(29) <= \\; + \genr_control_regs[2]\(28) <= \\; + \genr_control_regs[2]\(27) <= \\; + \genr_control_regs[2]\(26) <= \\; + \genr_control_regs[2]\(25) <= \\; + \genr_control_regs[2]\(24) <= \\; + \genr_control_regs[2]\(23) <= \\; + \genr_control_regs[2]\(22) <= \\; + \genr_control_regs[2]\(21 downto 16) <= \^genr_control_regs[2]\(21 downto 16); + \genr_control_regs[2]\(15) <= \\; + \genr_control_regs[2]\(14) <= \\; + \genr_control_regs[2]\(13) <= \\; + \genr_control_regs[2]\(12) <= \\; + \genr_control_regs[2]\(11) <= \\; + \genr_control_regs[2]\(10) <= \\; + \genr_control_regs[2]\(9) <= \\; + \genr_control_regs[2]\(8) <= \\; + \genr_control_regs[2]\(7) <= \\; + \genr_control_regs[2]\(6) <= \\; + \genr_control_regs[2]\(5) <= \\; + \genr_control_regs[2]\(4) <= \\; + \genr_control_regs[2]\(3) <= \\; + \genr_control_regs[2]\(2) <= \\; + \genr_control_regs[2]\(1) <= \\; + \genr_control_regs[2]\(0) <= \\; + \genr_control_regs[3]\(31 downto 16) <= \^genr_control_regs[3]\(31 downto 16); + \genr_control_regs[3]\(15) <= \\; + \genr_control_regs[3]\(14) <= \\; + \genr_control_regs[3]\(13 downto 8) <= \^genr_control_regs[3]\(13 downto 8); + \genr_control_regs[3]\(7) <= \\; + \genr_control_regs[3]\(6) <= \\; + \genr_control_regs[3]\(5) <= \\; + \genr_control_regs[3]\(4) <= \\; + \genr_control_regs[3]\(3) <= \\; + \genr_control_regs[3]\(2) <= \\; + \genr_control_regs[3]\(1) <= \\; + \genr_control_regs[3]\(0) <= \\; + \genr_control_regs[4]\(31) <= \\; + \genr_control_regs[4]\(30) <= \\; + \genr_control_regs[4]\(29) <= \\; + \genr_control_regs[4]\(28) <= \\; + \genr_control_regs[4]\(27) <= \\; + \genr_control_regs[4]\(26) <= \\; + \genr_control_regs[4]\(25) <= \\; + \genr_control_regs[4]\(24) <= \\; + \genr_control_regs[4]\(23) <= \\; + \genr_control_regs[4]\(22) <= \\; + \genr_control_regs[4]\(21) <= \\; + \genr_control_regs[4]\(20) <= \\; + \genr_control_regs[4]\(19) <= \\; + \genr_control_regs[4]\(18) <= \\; + \genr_control_regs[4]\(17) <= \\; + \genr_control_regs[4]\(16) <= \\; + \genr_control_regs[4]\(15) <= \\; + \genr_control_regs[4]\(14) <= \\; + \genr_control_regs[4]\(13) <= \\; + \genr_control_regs[4]\(12) <= \\; + \genr_control_regs[4]\(11) <= \\; + \genr_control_regs[4]\(10) <= \\; + \genr_control_regs[4]\(9) <= \\; + \genr_control_regs[4]\(8) <= \\; + \genr_control_regs[4]\(7) <= \\; + \genr_control_regs[4]\(6) <= \\; + \genr_control_regs[4]\(5) <= \\; + \genr_control_regs[4]\(4) <= \\; + \genr_control_regs[4]\(3) <= \\; + \genr_control_regs[4]\(2) <= \\; + \genr_control_regs[4]\(1) <= \\; + \genr_control_regs[4]\(0) <= \\; + ipif_addr_out(8 downto 0) <= ipif_Addr(8 downto 0); + ipif_data_out(31 downto 0) <= \^ipif_data_out\(31 downto 0); + resetn_out <= \^resetn_out\; + s_axi_awready <= \^s_axi_wready\; + s_axi_bresp(1) <= \^s_axi_bresp\(1); + s_axi_bresp(0) <= \\; + s_axi_rresp(1) <= \^s_axi_rresp\(1); + s_axi_rresp(0) <= \\; + s_axi_wready <= \^s_axi_wready\; + \time_control_regs[0]\(31) <= \\; + \time_control_regs[0]\(30) <= \\; + \time_control_regs[0]\(29) <= \\; + \time_control_regs[0]\(28) <= \\; + \time_control_regs[0]\(27) <= \\; + \time_control_regs[0]\(26) <= \\; + \time_control_regs[0]\(25) <= \\; + \time_control_regs[0]\(24) <= \\; + \time_control_regs[0]\(23) <= \\; + \time_control_regs[0]\(22) <= \\; + \time_control_regs[0]\(21) <= \\; + \time_control_regs[0]\(20) <= \\; + \time_control_regs[0]\(19) <= \\; + \time_control_regs[0]\(18) <= \\; + \time_control_regs[0]\(17) <= \\; + \time_control_regs[0]\(16) <= \\; + \time_control_regs[0]\(15) <= \\; + \time_control_regs[0]\(14) <= \\; + \time_control_regs[0]\(13) <= \\; + \time_control_regs[0]\(12) <= \\; + \time_control_regs[0]\(11) <= \\; + \time_control_regs[0]\(10) <= \\; + \time_control_regs[0]\(9) <= \\; + \time_control_regs[0]\(8) <= \\; + \time_control_regs[0]\(7) <= \\; + \time_control_regs[0]\(6) <= \\; + \time_control_regs[0]\(5) <= \\; + \time_control_regs[0]\(4) <= \\; + \time_control_regs[0]\(3) <= \\; + \time_control_regs[0]\(2) <= \\; + \time_control_regs[0]\(1) <= \\; + \time_control_regs[0]\(0) <= \\; + \time_control_regs[10]\(31) <= \\; + \time_control_regs[10]\(30) <= \\; + \time_control_regs[10]\(29) <= \\; + \time_control_regs[10]\(28) <= \\; + \time_control_regs[10]\(27) <= \\; + \time_control_regs[10]\(26) <= \\; + \time_control_regs[10]\(25) <= \\; + \time_control_regs[10]\(24) <= \\; + \time_control_regs[10]\(23) <= \\; + \time_control_regs[10]\(22) <= \\; + \time_control_regs[10]\(21) <= \\; + \time_control_regs[10]\(20) <= \\; + \time_control_regs[10]\(19) <= \\; + \time_control_regs[10]\(18) <= \\; + \time_control_regs[10]\(17) <= \\; + \time_control_regs[10]\(16) <= \\; + \time_control_regs[10]\(15) <= \\; + \time_control_regs[10]\(14) <= \\; + \time_control_regs[10]\(13) <= \\; + \time_control_regs[10]\(12) <= \\; + \time_control_regs[10]\(11) <= \\; + \time_control_regs[10]\(10) <= \\; + \time_control_regs[10]\(9) <= \\; + \time_control_regs[10]\(8) <= \\; + \time_control_regs[10]\(7) <= \\; + \time_control_regs[10]\(6) <= \\; + \time_control_regs[10]\(5) <= \\; + \time_control_regs[10]\(4) <= \\; + \time_control_regs[10]\(3) <= \\; + \time_control_regs[10]\(2) <= \\; + \time_control_regs[10]\(1) <= \\; + \time_control_regs[10]\(0) <= \\; + \time_control_regs[11]\(31) <= \\; + \time_control_regs[11]\(30) <= \\; + \time_control_regs[11]\(29) <= \\; + \time_control_regs[11]\(28) <= \\; + \time_control_regs[11]\(27) <= \\; + \time_control_regs[11]\(26) <= \\; + \time_control_regs[11]\(25) <= \\; + \time_control_regs[11]\(24) <= \\; + \time_control_regs[11]\(23) <= \\; + \time_control_regs[11]\(22) <= \\; + \time_control_regs[11]\(21) <= \\; + \time_control_regs[11]\(20) <= \\; + \time_control_regs[11]\(19) <= \\; + \time_control_regs[11]\(18) <= \\; + \time_control_regs[11]\(17) <= \\; + \time_control_regs[11]\(16) <= \\; + \time_control_regs[11]\(15) <= \\; + \time_control_regs[11]\(14) <= \\; + \time_control_regs[11]\(13) <= \\; + \time_control_regs[11]\(12) <= \\; + \time_control_regs[11]\(11) <= \\; + \time_control_regs[11]\(10) <= \\; + \time_control_regs[11]\(9) <= \\; + \time_control_regs[11]\(8) <= \\; + \time_control_regs[11]\(7) <= \\; + \time_control_regs[11]\(6) <= \\; + \time_control_regs[11]\(5) <= \\; + \time_control_regs[11]\(4) <= \\; + \time_control_regs[11]\(3) <= \\; + \time_control_regs[11]\(2) <= \\; + \time_control_regs[11]\(1) <= \\; + \time_control_regs[11]\(0) <= \\; + \time_control_regs[12]\(31) <= \\; + \time_control_regs[12]\(30) <= \\; + \time_control_regs[12]\(29) <= \\; + \time_control_regs[12]\(28) <= \\; + \time_control_regs[12]\(27) <= \\; + \time_control_regs[12]\(26) <= \\; + \time_control_regs[12]\(25) <= \\; + \time_control_regs[12]\(24) <= \\; + \time_control_regs[12]\(23) <= \\; + \time_control_regs[12]\(22) <= \\; + \time_control_regs[12]\(21) <= \\; + \time_control_regs[12]\(20) <= \\; + \time_control_regs[12]\(19) <= \\; + \time_control_regs[12]\(18) <= \\; + \time_control_regs[12]\(17) <= \\; + \time_control_regs[12]\(16) <= \\; + \time_control_regs[12]\(15) <= \\; + \time_control_regs[12]\(14) <= \\; + \time_control_regs[12]\(13) <= \\; + \time_control_regs[12]\(12) <= \\; + \time_control_regs[12]\(11) <= \\; + \time_control_regs[12]\(10) <= \\; + \time_control_regs[12]\(9) <= \\; + \time_control_regs[12]\(8) <= \\; + \time_control_regs[12]\(7) <= \\; + \time_control_regs[12]\(6) <= \\; + \time_control_regs[12]\(5) <= \\; + \time_control_regs[12]\(4) <= \\; + \time_control_regs[12]\(3) <= \\; + \time_control_regs[12]\(2) <= \\; + \time_control_regs[12]\(1) <= \\; + \time_control_regs[12]\(0) <= \\; + \time_control_regs[13]\(31) <= \\; + \time_control_regs[13]\(30) <= \\; + \time_control_regs[13]\(29) <= \\; + \time_control_regs[13]\(28) <= \\; + \time_control_regs[13]\(27) <= \\; + \time_control_regs[13]\(26) <= \\; + \time_control_regs[13]\(25) <= \\; + \time_control_regs[13]\(24) <= \\; + \time_control_regs[13]\(23) <= \\; + \time_control_regs[13]\(22) <= \\; + \time_control_regs[13]\(21) <= \\; + \time_control_regs[13]\(20) <= \\; + \time_control_regs[13]\(19) <= \\; + \time_control_regs[13]\(18) <= \\; + \time_control_regs[13]\(17) <= \\; + \time_control_regs[13]\(16) <= \\; + \time_control_regs[13]\(15) <= \\; + \time_control_regs[13]\(14) <= \\; + \time_control_regs[13]\(13) <= \\; + \time_control_regs[13]\(12) <= \\; + \time_control_regs[13]\(11) <= \\; + \time_control_regs[13]\(10) <= \\; + \time_control_regs[13]\(9) <= \\; + \time_control_regs[13]\(8) <= \\; + \time_control_regs[13]\(7) <= \\; + \time_control_regs[13]\(6) <= \\; + \time_control_regs[13]\(5) <= \\; + \time_control_regs[13]\(4) <= \\; + \time_control_regs[13]\(3) <= \\; + \time_control_regs[13]\(2) <= \\; + \time_control_regs[13]\(1) <= \\; + \time_control_regs[13]\(0) <= \\; + \time_control_regs[14]\(31) <= \\; + \time_control_regs[14]\(30) <= \\; + \time_control_regs[14]\(29) <= \\; + \time_control_regs[14]\(28) <= \\; + \time_control_regs[14]\(27) <= \\; + \time_control_regs[14]\(26) <= \\; + \time_control_regs[14]\(25) <= \\; + \time_control_regs[14]\(24) <= \\; + \time_control_regs[14]\(23) <= \\; + \time_control_regs[14]\(22) <= \\; + \time_control_regs[14]\(21) <= \\; + \time_control_regs[14]\(20) <= \\; + \time_control_regs[14]\(19) <= \\; + \time_control_regs[14]\(18) <= \\; + \time_control_regs[14]\(17) <= \\; + \time_control_regs[14]\(16) <= \\; + \time_control_regs[14]\(15) <= \\; + \time_control_regs[14]\(14) <= \\; + \time_control_regs[14]\(13) <= \\; + \time_control_regs[14]\(12) <= \\; + \time_control_regs[14]\(11) <= \\; + \time_control_regs[14]\(10) <= \\; + \time_control_regs[14]\(9) <= \\; + \time_control_regs[14]\(8) <= \\; + \time_control_regs[14]\(7) <= \\; + \time_control_regs[14]\(6) <= \\; + \time_control_regs[14]\(5) <= \\; + \time_control_regs[14]\(4) <= \\; + \time_control_regs[14]\(3) <= \\; + \time_control_regs[14]\(2) <= \\; + \time_control_regs[14]\(1) <= \\; + \time_control_regs[14]\(0) <= \\; + \time_control_regs[15]\(31) <= \\; + \time_control_regs[15]\(30) <= \\; + \time_control_regs[15]\(29) <= \\; + \time_control_regs[15]\(28) <= \\; + \time_control_regs[15]\(27) <= \\; + \time_control_regs[15]\(26) <= \\; + \time_control_regs[15]\(25) <= \\; + \time_control_regs[15]\(24) <= \\; + \time_control_regs[15]\(23) <= \\; + \time_control_regs[15]\(22) <= \\; + \time_control_regs[15]\(21) <= \\; + \time_control_regs[15]\(20) <= \\; + \time_control_regs[15]\(19) <= \\; + \time_control_regs[15]\(18) <= \\; + \time_control_regs[15]\(17) <= \\; + \time_control_regs[15]\(16) <= \\; + \time_control_regs[15]\(15) <= \\; + \time_control_regs[15]\(14) <= \\; + \time_control_regs[15]\(13) <= \\; + \time_control_regs[15]\(12) <= \\; + \time_control_regs[15]\(11) <= \\; + \time_control_regs[15]\(10) <= \\; + \time_control_regs[15]\(9) <= \\; + \time_control_regs[15]\(8) <= \\; + \time_control_regs[15]\(7) <= \\; + \time_control_regs[15]\(6) <= \\; + \time_control_regs[15]\(5) <= \\; + \time_control_regs[15]\(4) <= \\; + \time_control_regs[15]\(3) <= \\; + \time_control_regs[15]\(2) <= \\; + \time_control_regs[15]\(1) <= \\; + \time_control_regs[15]\(0) <= \\; + \time_control_regs[16]\(31) <= \\; + \time_control_regs[16]\(30) <= \\; + \time_control_regs[16]\(29) <= \\; + \time_control_regs[16]\(28 downto 16) <= \^time_control_regs[16]\(28 downto 16); + \time_control_regs[16]\(15) <= \\; + \time_control_regs[16]\(14) <= \\; + \time_control_regs[16]\(13) <= \\; + \time_control_regs[16]\(12 downto 0) <= \^time_control_regs[16]\(12 downto 0); + \time_control_regs[17]\(31) <= \\; + \time_control_regs[17]\(30) <= \\; + \time_control_regs[17]\(29) <= \\; + \time_control_regs[17]\(28) <= \\; + \time_control_regs[17]\(27) <= \\; + \time_control_regs[17]\(26) <= \\; + \time_control_regs[17]\(25) <= \\; + \time_control_regs[17]\(24) <= \\; + \time_control_regs[17]\(23) <= \\; + \time_control_regs[17]\(22) <= \\; + \time_control_regs[17]\(21) <= \\; + \time_control_regs[17]\(20) <= \\; + \time_control_regs[17]\(19) <= \\; + \time_control_regs[17]\(18) <= \\; + \time_control_regs[17]\(17) <= \\; + \time_control_regs[17]\(16) <= \\; + \time_control_regs[17]\(15) <= \\; + \time_control_regs[17]\(14) <= \\; + \time_control_regs[17]\(13) <= \\; + \time_control_regs[17]\(12) <= \\; + \time_control_regs[17]\(11) <= \\; + \time_control_regs[17]\(10) <= \\; + \time_control_regs[17]\(9) <= \\; + \time_control_regs[17]\(8) <= \\; + \time_control_regs[17]\(7) <= \\; + \time_control_regs[17]\(6) <= \\; + \time_control_regs[17]\(5) <= \\; + \time_control_regs[17]\(4) <= \\; + \time_control_regs[17]\(3) <= \\; + \time_control_regs[17]\(2) <= \\; + \time_control_regs[17]\(1) <= \\; + \time_control_regs[17]\(0) <= \\; + \time_control_regs[18]\(31) <= \\; + \time_control_regs[18]\(30) <= \\; + \time_control_regs[18]\(29) <= \\; + \time_control_regs[18]\(28) <= \\; + \time_control_regs[18]\(27) <= \\; + \time_control_regs[18]\(26) <= \\; + \time_control_regs[18]\(25) <= \\; + \time_control_regs[18]\(24) <= \\; + \time_control_regs[18]\(23) <= \\; + \time_control_regs[18]\(22) <= \\; + \time_control_regs[18]\(21) <= \\; + \time_control_regs[18]\(20) <= \\; + \time_control_regs[18]\(19) <= \\; + \time_control_regs[18]\(18) <= \\; + \time_control_regs[18]\(17) <= \\; + \time_control_regs[18]\(16) <= \\; + \time_control_regs[18]\(15) <= \\; + \time_control_regs[18]\(14) <= \\; + \time_control_regs[18]\(13) <= \\; + \time_control_regs[18]\(12) <= \\; + \time_control_regs[18]\(11) <= \\; + \time_control_regs[18]\(10) <= \\; + \time_control_regs[18]\(9 downto 6) <= \^time_control_regs[18]\(9 downto 6); + \time_control_regs[18]\(5) <= \\; + \time_control_regs[18]\(4) <= \\; + \time_control_regs[18]\(3 downto 0) <= \^time_control_regs[18]\(3 downto 0); + \time_control_regs[19]\(31) <= \\; + \time_control_regs[19]\(30) <= \\; + \time_control_regs[19]\(29) <= \\; + \time_control_regs[19]\(28) <= \\; + \time_control_regs[19]\(27) <= \\; + \time_control_regs[19]\(26) <= \\; + \time_control_regs[19]\(25) <= \\; + \time_control_regs[19]\(24) <= \\; + \time_control_regs[19]\(23) <= \\; + \time_control_regs[19]\(22) <= \\; + \time_control_regs[19]\(21) <= \\; + \time_control_regs[19]\(20) <= \\; + \time_control_regs[19]\(19) <= \\; + \time_control_regs[19]\(18) <= \\; + \time_control_regs[19]\(17) <= \\; + \time_control_regs[19]\(16) <= \\; + \time_control_regs[19]\(15) <= \\; + \time_control_regs[19]\(14) <= \\; + \time_control_regs[19]\(13) <= \\; + \time_control_regs[19]\(12) <= \\; + \time_control_regs[19]\(11) <= \\; + \time_control_regs[19]\(10) <= \\; + \time_control_regs[19]\(9) <= \\; + \time_control_regs[19]\(8) <= \\; + \time_control_regs[19]\(7) <= \\; + \time_control_regs[19]\(6 downto 0) <= \^time_control_regs[19]\(6 downto 0); + \time_control_regs[1]\(31) <= \\; + \time_control_regs[1]\(30) <= \\; + \time_control_regs[1]\(29) <= \\; + \time_control_regs[1]\(28) <= \\; + \time_control_regs[1]\(27) <= \\; + \time_control_regs[1]\(26) <= \\; + \time_control_regs[1]\(25) <= \\; + \time_control_regs[1]\(24) <= \\; + \time_control_regs[1]\(23) <= \\; + \time_control_regs[1]\(22) <= \\; + \time_control_regs[1]\(21) <= \\; + \time_control_regs[1]\(20) <= \\; + \time_control_regs[1]\(19) <= \\; + \time_control_regs[1]\(18) <= \\; + \time_control_regs[1]\(17) <= \\; + \time_control_regs[1]\(16) <= \\; + \time_control_regs[1]\(15) <= \\; + \time_control_regs[1]\(14) <= \\; + \time_control_regs[1]\(13) <= \\; + \time_control_regs[1]\(12) <= \\; + \time_control_regs[1]\(11) <= \\; + \time_control_regs[1]\(10) <= \\; + \time_control_regs[1]\(9) <= \\; + \time_control_regs[1]\(8) <= \\; + \time_control_regs[1]\(7) <= \\; + \time_control_regs[1]\(6) <= \\; + \time_control_regs[1]\(5) <= \\; + \time_control_regs[1]\(4) <= \\; + \time_control_regs[1]\(3) <= \\; + \time_control_regs[1]\(2) <= \\; + \time_control_regs[1]\(1) <= \\; + \time_control_regs[1]\(0) <= \\; + \time_control_regs[20]\(31) <= \\; + \time_control_regs[20]\(30) <= \\; + \time_control_regs[20]\(29) <= \\; + \time_control_regs[20]\(28 downto 16) <= \^time_control_regs[20]\(28 downto 16); + \time_control_regs[20]\(15) <= \\; + \time_control_regs[20]\(14) <= \\; + \time_control_regs[20]\(13) <= \\; + \time_control_regs[20]\(12 downto 0) <= \^time_control_regs[20]\(12 downto 0); + \time_control_regs[21]\(31) <= \\; + \time_control_regs[21]\(30) <= \\; + \time_control_regs[21]\(29) <= \\; + \time_control_regs[21]\(28 downto 16) <= \^time_control_regs[21]\(28 downto 16); + \time_control_regs[21]\(15) <= \\; + \time_control_regs[21]\(14) <= \\; + \time_control_regs[21]\(13) <= \\; + \time_control_regs[21]\(12 downto 0) <= \^time_control_regs[21]\(12 downto 0); + \time_control_regs[22]\(31) <= \\; + \time_control_regs[22]\(30) <= \\; + \time_control_regs[22]\(29) <= \\; + \time_control_regs[22]\(28 downto 16) <= \^time_control_regs[22]\(28 downto 16); + \time_control_regs[22]\(15) <= \\; + \time_control_regs[22]\(14) <= \\; + \time_control_regs[22]\(13) <= \\; + \time_control_regs[22]\(12 downto 0) <= \^time_control_regs[22]\(12 downto 0); + \time_control_regs[23]\(31) <= \\; + \time_control_regs[23]\(30) <= \\; + \time_control_regs[23]\(29) <= \\; + \time_control_regs[23]\(28 downto 16) <= \^time_control_regs[23]\(28 downto 16); + \time_control_regs[23]\(15) <= \\; + \time_control_regs[23]\(14) <= \\; + \time_control_regs[23]\(13) <= \\; + \time_control_regs[23]\(12 downto 0) <= \^time_control_regs[23]\(12 downto 0); + \time_control_regs[24]\(31) <= \\; + \time_control_regs[24]\(30) <= \\; + \time_control_regs[24]\(29) <= \\; + \time_control_regs[24]\(28 downto 16) <= \^time_control_regs[24]\(28 downto 16); + \time_control_regs[24]\(15) <= \\; + \time_control_regs[24]\(14) <= \\; + \time_control_regs[24]\(13) <= \\; + \time_control_regs[24]\(12 downto 0) <= \^time_control_regs[24]\(12 downto 0); + \time_control_regs[25]\(31) <= \\; + \time_control_regs[25]\(30) <= \\; + \time_control_regs[25]\(29) <= \\; + \time_control_regs[25]\(28 downto 16) <= \^time_control_regs[25]\(28 downto 16); + \time_control_regs[25]\(15) <= \\; + \time_control_regs[25]\(14) <= \\; + \time_control_regs[25]\(13) <= \\; + \time_control_regs[25]\(12 downto 0) <= \^time_control_regs[25]\(12 downto 0); + \time_control_regs[26]\(31) <= \\; + \time_control_regs[26]\(30) <= \\; + \time_control_regs[26]\(29) <= \\; + \time_control_regs[26]\(28 downto 16) <= \^time_control_regs[26]\(28 downto 16); + \time_control_regs[26]\(15) <= \\; + \time_control_regs[26]\(14) <= \\; + \time_control_regs[26]\(13) <= \\; + \time_control_regs[26]\(12 downto 0) <= \^time_control_regs[26]\(12 downto 0); + \time_control_regs[27]\(31) <= \\; + \time_control_regs[27]\(30) <= \\; + \time_control_regs[27]\(29) <= \\; + \time_control_regs[27]\(28 downto 16) <= \^time_control_regs[27]\(28 downto 16); + \time_control_regs[27]\(15) <= \\; + \time_control_regs[27]\(14) <= \\; + \time_control_regs[27]\(13) <= \\; + \time_control_regs[27]\(12 downto 0) <= \^time_control_regs[27]\(12 downto 0); + \time_control_regs[28]\(31) <= \\; + \time_control_regs[28]\(30) <= \\; + \time_control_regs[28]\(29) <= \\; + \time_control_regs[28]\(28 downto 16) <= \^time_control_regs[28]\(28 downto 16); + \time_control_regs[28]\(15) <= \\; + \time_control_regs[28]\(14) <= \\; + \time_control_regs[28]\(13) <= \\; + \time_control_regs[28]\(12 downto 0) <= \^time_control_regs[28]\(12 downto 0); + \time_control_regs[2]\(31) <= \\; + \time_control_regs[2]\(30) <= \\; + \time_control_regs[2]\(29) <= \\; + \time_control_regs[2]\(28) <= \\; + \time_control_regs[2]\(27) <= \\; + \time_control_regs[2]\(26) <= \\; + \time_control_regs[2]\(25) <= \\; + \time_control_regs[2]\(24) <= \\; + \time_control_regs[2]\(23) <= \\; + \time_control_regs[2]\(22) <= \\; + \time_control_regs[2]\(21) <= \\; + \time_control_regs[2]\(20) <= \\; + \time_control_regs[2]\(19) <= \\; + \time_control_regs[2]\(18) <= \\; + \time_control_regs[2]\(17) <= \\; + \time_control_regs[2]\(16) <= \\; + \time_control_regs[2]\(15) <= \\; + \time_control_regs[2]\(14) <= \\; + \time_control_regs[2]\(13) <= \\; + \time_control_regs[2]\(12) <= \\; + \time_control_regs[2]\(11) <= \\; + \time_control_regs[2]\(10) <= \\; + \time_control_regs[2]\(9) <= \\; + \time_control_regs[2]\(8) <= \\; + \time_control_regs[2]\(7) <= \\; + \time_control_regs[2]\(6) <= \\; + \time_control_regs[2]\(5) <= \\; + \time_control_regs[2]\(4) <= \\; + \time_control_regs[2]\(3) <= \\; + \time_control_regs[2]\(2) <= \\; + \time_control_regs[2]\(1) <= \\; + \time_control_regs[2]\(0) <= \\; + \time_control_regs[3]\(31) <= \\; + \time_control_regs[3]\(30) <= \\; + \time_control_regs[3]\(29) <= \\; + \time_control_regs[3]\(28) <= \\; + \time_control_regs[3]\(27) <= \\; + \time_control_regs[3]\(26) <= \\; + \time_control_regs[3]\(25) <= \\; + \time_control_regs[3]\(24) <= \\; + \time_control_regs[3]\(23) <= \\; + \time_control_regs[3]\(22) <= \\; + \time_control_regs[3]\(21) <= \\; + \time_control_regs[3]\(20) <= \\; + \time_control_regs[3]\(19) <= \\; + \time_control_regs[3]\(18) <= \\; + \time_control_regs[3]\(17) <= \\; + \time_control_regs[3]\(16) <= \\; + \time_control_regs[3]\(15) <= \\; + \time_control_regs[3]\(14) <= \\; + \time_control_regs[3]\(13) <= \\; + \time_control_regs[3]\(12) <= \\; + \time_control_regs[3]\(11) <= \\; + \time_control_regs[3]\(10) <= \\; + \time_control_regs[3]\(9) <= \\; + \time_control_regs[3]\(8) <= \\; + \time_control_regs[3]\(7) <= \\; + \time_control_regs[3]\(6) <= \\; + \time_control_regs[3]\(5) <= \\; + \time_control_regs[3]\(4) <= \\; + \time_control_regs[3]\(3) <= \\; + \time_control_regs[3]\(2) <= \\; + \time_control_regs[3]\(1) <= \\; + \time_control_regs[3]\(0) <= \\; + \time_control_regs[4]\(31) <= \\; + \time_control_regs[4]\(30) <= \\; + \time_control_regs[4]\(29) <= \\; + \time_control_regs[4]\(28) <= \\; + \time_control_regs[4]\(27) <= \\; + \time_control_regs[4]\(26) <= \\; + \time_control_regs[4]\(25) <= \\; + \time_control_regs[4]\(24) <= \\; + \time_control_regs[4]\(23) <= \\; + \time_control_regs[4]\(22) <= \\; + \time_control_regs[4]\(21) <= \\; + \time_control_regs[4]\(20) <= \\; + \time_control_regs[4]\(19) <= \\; + \time_control_regs[4]\(18) <= \\; + \time_control_regs[4]\(17) <= \\; + \time_control_regs[4]\(16) <= \\; + \time_control_regs[4]\(15) <= \\; + \time_control_regs[4]\(14) <= \\; + \time_control_regs[4]\(13) <= \\; + \time_control_regs[4]\(12) <= \\; + \time_control_regs[4]\(11) <= \\; + \time_control_regs[4]\(10) <= \\; + \time_control_regs[4]\(9) <= \\; + \time_control_regs[4]\(8) <= \\; + \time_control_regs[4]\(7) <= \\; + \time_control_regs[4]\(6) <= \\; + \time_control_regs[4]\(5) <= \\; + \time_control_regs[4]\(4) <= \\; + \time_control_regs[4]\(3) <= \\; + \time_control_regs[4]\(2) <= \\; + \time_control_regs[4]\(1) <= \\; + \time_control_regs[4]\(0) <= \\; + \time_control_regs[5]\(31) <= \\; + \time_control_regs[5]\(30) <= \\; + \time_control_regs[5]\(29) <= \\; + \time_control_regs[5]\(28) <= \\; + \time_control_regs[5]\(27) <= \\; + \time_control_regs[5]\(26) <= \\; + \time_control_regs[5]\(25) <= \\; + \time_control_regs[5]\(24) <= \\; + \time_control_regs[5]\(23) <= \\; + \time_control_regs[5]\(22) <= \\; + \time_control_regs[5]\(21) <= \\; + \time_control_regs[5]\(20) <= \\; + \time_control_regs[5]\(19) <= \\; + \time_control_regs[5]\(18) <= \\; + \time_control_regs[5]\(17) <= \\; + \time_control_regs[5]\(16) <= \\; + \time_control_regs[5]\(15) <= \\; + \time_control_regs[5]\(14) <= \\; + \time_control_regs[5]\(13) <= \\; + \time_control_regs[5]\(12) <= \\; + \time_control_regs[5]\(11) <= \\; + \time_control_regs[5]\(10) <= \\; + \time_control_regs[5]\(9) <= \\; + \time_control_regs[5]\(8) <= \\; + \time_control_regs[5]\(7) <= \\; + \time_control_regs[5]\(6) <= \\; + \time_control_regs[5]\(5) <= \\; + \time_control_regs[5]\(4) <= \\; + \time_control_regs[5]\(3) <= \\; + \time_control_regs[5]\(2) <= \\; + \time_control_regs[5]\(1) <= \\; + \time_control_regs[5]\(0) <= \\; + \time_control_regs[6]\(31) <= \\; + \time_control_regs[6]\(30) <= \\; + \time_control_regs[6]\(29) <= \\; + \time_control_regs[6]\(28) <= \\; + \time_control_regs[6]\(27) <= \\; + \time_control_regs[6]\(26) <= \\; + \time_control_regs[6]\(25) <= \\; + \time_control_regs[6]\(24) <= \\; + \time_control_regs[6]\(23) <= \\; + \time_control_regs[6]\(22) <= \\; + \time_control_regs[6]\(21) <= \\; + \time_control_regs[6]\(20) <= \\; + \time_control_regs[6]\(19) <= \\; + \time_control_regs[6]\(18) <= \\; + \time_control_regs[6]\(17) <= \\; + \time_control_regs[6]\(16) <= \\; + \time_control_regs[6]\(15) <= \\; + \time_control_regs[6]\(14) <= \\; + \time_control_regs[6]\(13) <= \\; + \time_control_regs[6]\(12) <= \\; + \time_control_regs[6]\(11) <= \\; + \time_control_regs[6]\(10) <= \\; + \time_control_regs[6]\(9) <= \\; + \time_control_regs[6]\(8) <= \\; + \time_control_regs[6]\(7) <= \\; + \time_control_regs[6]\(6) <= \\; + \time_control_regs[6]\(5) <= \\; + \time_control_regs[6]\(4) <= \\; + \time_control_regs[6]\(3) <= \\; + \time_control_regs[6]\(2) <= \\; + \time_control_regs[6]\(1) <= \\; + \time_control_regs[6]\(0) <= \\; + \time_control_regs[7]\(31) <= \\; + \time_control_regs[7]\(30) <= \\; + \time_control_regs[7]\(29) <= \\; + \time_control_regs[7]\(28) <= \\; + \time_control_regs[7]\(27) <= \\; + \time_control_regs[7]\(26) <= \\; + \time_control_regs[7]\(25) <= \\; + \time_control_regs[7]\(24) <= \\; + \time_control_regs[7]\(23) <= \\; + \time_control_regs[7]\(22) <= \\; + \time_control_regs[7]\(21) <= \\; + \time_control_regs[7]\(20) <= \\; + \time_control_regs[7]\(19) <= \\; + \time_control_regs[7]\(18) <= \\; + \time_control_regs[7]\(17) <= \\; + \time_control_regs[7]\(16) <= \\; + \time_control_regs[7]\(15) <= \\; + \time_control_regs[7]\(14) <= \\; + \time_control_regs[7]\(13) <= \\; + \time_control_regs[7]\(12) <= \\; + \time_control_regs[7]\(11) <= \\; + \time_control_regs[7]\(10) <= \\; + \time_control_regs[7]\(9) <= \\; + \time_control_regs[7]\(8) <= \\; + \time_control_regs[7]\(7) <= \\; + \time_control_regs[7]\(6) <= \\; + \time_control_regs[7]\(5) <= \\; + \time_control_regs[7]\(4) <= \\; + \time_control_regs[7]\(3) <= \\; + \time_control_regs[7]\(2) <= \\; + \time_control_regs[7]\(1) <= \\; + \time_control_regs[7]\(0) <= \\; + \time_control_regs[8]\(31) <= \\; + \time_control_regs[8]\(30) <= \\; + \time_control_regs[8]\(29) <= \\; + \time_control_regs[8]\(28) <= \\; + \time_control_regs[8]\(27) <= \\; + \time_control_regs[8]\(26) <= \\; + \time_control_regs[8]\(25) <= \\; + \time_control_regs[8]\(24) <= \\; + \time_control_regs[8]\(23) <= \\; + \time_control_regs[8]\(22) <= \\; + \time_control_regs[8]\(21) <= \\; + \time_control_regs[8]\(20) <= \\; + \time_control_regs[8]\(19) <= \\; + \time_control_regs[8]\(18) <= \\; + \time_control_regs[8]\(17) <= \\; + \time_control_regs[8]\(16) <= \\; + \time_control_regs[8]\(15) <= \\; + \time_control_regs[8]\(14) <= \\; + \time_control_regs[8]\(13) <= \\; + \time_control_regs[8]\(12) <= \\; + \time_control_regs[8]\(11) <= \\; + \time_control_regs[8]\(10) <= \\; + \time_control_regs[8]\(9) <= \\; + \time_control_regs[8]\(8) <= \\; + \time_control_regs[8]\(7) <= \\; + \time_control_regs[8]\(6) <= \\; + \time_control_regs[8]\(5) <= \\; + \time_control_regs[8]\(4) <= \\; + \time_control_regs[8]\(3) <= \\; + \time_control_regs[8]\(2) <= \\; + \time_control_regs[8]\(1) <= \\; + \time_control_regs[8]\(0) <= \\; + \time_control_regs[9]\(31) <= \\; + \time_control_regs[9]\(30) <= \\; + \time_control_regs[9]\(29) <= \\; + \time_control_regs[9]\(28) <= \\; + \time_control_regs[9]\(27) <= \\; + \time_control_regs[9]\(26) <= \\; + \time_control_regs[9]\(25) <= \\; + \time_control_regs[9]\(24) <= \\; + \time_control_regs[9]\(23) <= \\; + \time_control_regs[9]\(22) <= \\; + \time_control_regs[9]\(21) <= \\; + \time_control_regs[9]\(20) <= \\; + \time_control_regs[9]\(19) <= \\; + \time_control_regs[9]\(18) <= \\; + \time_control_regs[9]\(17) <= \\; + \time_control_regs[9]\(16) <= \\; + \time_control_regs[9]\(15) <= \\; + \time_control_regs[9]\(14) <= \\; + \time_control_regs[9]\(13) <= \\; + \time_control_regs[9]\(12) <= \\; + \time_control_regs[9]\(11) <= \\; + \time_control_regs[9]\(10) <= \\; + \time_control_regs[9]\(9) <= \\; + \time_control_regs[9]\(8) <= \\; + \time_control_regs[9]\(7) <= \\; + \time_control_regs[9]\(6) <= \\; + \time_control_regs[9]\(5) <= \\; + \time_control_regs[9]\(4) <= \\; + \time_control_regs[9]\(3) <= \\; + \time_control_regs[9]\(2) <= \\; + \time_control_regs[9]\(1) <= \\; + \time_control_regs[9]\(0) <= \\; +\AXI4_LITE_INTERFACE.AXI_LITE_IPIF_I\: entity work.Arty_Z7_20_v_tc_1_0_axi_lite_ipif + port map ( + D(11) => ipif_proc_RNW, + D(10 downto 9) => ipif_proc_CS(1 downto 0), + D(8 downto 0) => ipif_proc_Addr_int(8 downto 0), + aclk => aclk, + aresetn => aresetn, + ipif_Error => ipif_Error, + ipif_RdAck => ipif_RdAck, + ipif_WrAck => ipif_WrAck, + out_data(31 downto 0) => p_143_out(31 downto 0), + p_0_in => p_0_in_0, + s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0), + s_axi_arready => s_axi_arready, + s_axi_arvalid => s_axi_arvalid, + s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0), + s_axi_awvalid => s_axi_awvalid, + s_axi_bready => s_axi_bready, + s_axi_bresp(0) => \^s_axi_bresp\(1), + s_axi_bvalid => s_axi_bvalid, + s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), + s_axi_rready => s_axi_rready, + s_axi_rresp(0) => \^s_axi_rresp\(1), + s_axi_rvalid => s_axi_rvalid, + s_axi_wready => \^s_axi_wready\, + s_axi_wvalid => s_axi_wvalid + ); +\AXI4_LITE_INTERFACE.CORE_MUX0\: entity work.\Arty_Z7_20_v_tc_1_0_mux_tree__parameterized0\ + port map ( + \GEN_SEL_DELAY[2].sel_int_reg[2][0]\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_1\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_34\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_1\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_35\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_10\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_44\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_11\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_45\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_12\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_46\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_13\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_47\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_14\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_48\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_15\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_49\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_16\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_50\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_17\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_51\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_18\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_52\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_19\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_53\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_2\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_36\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_20\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_54\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_21\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_55\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_22\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_56\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_23\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_57\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_24\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_58\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_25\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_59\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_26\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_60\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_27\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_61\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_28\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_62\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_29\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_63\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_3\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_37\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_30\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_64\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_31\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_65\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_32\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_66\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_33\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_67\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_34\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_68\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_35\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_69\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_36\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_70\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_37\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_71\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_38\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_72\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_39\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_73\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_4\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_38\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_40\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_74\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_41\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_75\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_42\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_76\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_43\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_77\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_44\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_78\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_45\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_79\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_46\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_80\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_47\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_81\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_48\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_82\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_49\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_83\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_5\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_39\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_50\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_84\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_51\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_85\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_52\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_86\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_53\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_87\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_54\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_88\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_55\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_89\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_56\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_90\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_57\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_91\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_58\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_92\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_59\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_93\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_6\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_40\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_60\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_94\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_61\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_95\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_62\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_96\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_63\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_97\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_7\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_41\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_8\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_42\, + \GEN_SEL_DELAY[2].sel_int_reg[2][0]_9\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_43\, + \GEN_SEL_DELAY[4].sel_int_reg[4][0]\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_0\, + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0\ => \AXI4_LITE_INTERFACE.CORE_MUX0_n_0\, + \core_control_regs[16]\(22 downto 12) => \^core_control_regs[16]\(26 downto 16), + \core_control_regs[16]\(11 downto 0) => \^core_control_regs[16]\(11 downto 0), + core_data(31 downto 0) => core_data(31 downto 0), + \core_status_regs[16]\(8 downto 4) => \core_status_regs[16]\(31 downto 27), + \core_status_regs[16]\(3 downto 0) => \core_status_regs[16]\(15 downto 12), + ipif_Addr(0) => ipif_Addr(5), + vid_aclk => vid_aclk + ); +\AXI4_LITE_INTERFACE.GENR_MUX0\: entity work.Arty_Z7_20_v_tc_1_0_mux_tree + port map ( + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]\(0) => \core_control_regs2_int[0]\(0), + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][0]\(0) => \core_control_regs2_int[10]\(0), + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][0]\(0) => \core_control_regs2_int[11]\(0), + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][0]\(0) => \core_control_regs2_int[12]\(0), + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][0]\(0) => \core_control_regs2_int[13]\(0), + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][0]\(0) => \core_control_regs2_int[14]\(0), + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][0]\(0) => \core_control_regs2_int[15]\(0), + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][0]\(0) => \core_control_regs2_int[1]\(0), + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][0]\(0) => \core_control_regs2_int[2]\(0), + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][0]\(0) => \core_control_regs2_int[3]\(0), + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][0]\(0) => \core_control_regs2_int[4]\(0), + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][0]\(0) => \core_control_regs2_int[5]\(0), + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][0]\(0) => \core_control_regs2_int[6]\(0), + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][0]\(0) => \core_control_regs2_int[7]\(0), + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][0]\(0) => \core_control_regs2_int[8]\(0), + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][0]\(0) => \core_control_regs2_int[9]\(0), + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][31]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_137\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_598\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_599\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][12]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_600\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][13]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_601\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][16]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_604\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][17]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_605\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][18]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_606\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][19]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_607\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][20]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_608\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][21]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_609\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][22]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_610\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][23]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_611\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][24]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_612\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][25]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_613\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][26]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_614\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][27]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_615\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][28]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_616\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][29]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_617\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][30]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_618\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][31]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_619\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_596\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_597\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[0]\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_0\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_300\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_310\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_311\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][12]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_312\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][16]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_316\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][17]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_317\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][18]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_318\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][19]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_319\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][20]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_320\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][21]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_321\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][22]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_322\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][23]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_323\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][24]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_324\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][25]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_325\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][26]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_326\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][27]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_327\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_328\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][2]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_302\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_303\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_304\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_305\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_306\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_307\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_308\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_309\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_275\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_276\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_277\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_268\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][1]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_269\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][2]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_270\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_271\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_272\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_273\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_274\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_236\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_246\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_247\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][12]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_248\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][16]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_252\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][17]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_253\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][18]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_254\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][19]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_255\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][1]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_237\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][20]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_256\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][21]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_257\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][22]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_258\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][23]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_259\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][24]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_260\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][25]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_261\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][26]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_262\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][27]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_263\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_264\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][2]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_238\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_239\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_240\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_241\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_242\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_243\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_244\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_245\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_204\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_214\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_215\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][12]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_216\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][16]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_220\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][17]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_221\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][18]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_222\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][19]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_223\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][1]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_205\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][20]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_224\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][21]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_225\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][22]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_226\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][23]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_227\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][24]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_228\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][25]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_229\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][26]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_230\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][27]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_231\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_232\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][2]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_206\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_207\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_208\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_209\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_210\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_211\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_212\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_213\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_172\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_182\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_183\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][12]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_184\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][16]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_188\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][17]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_189\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][18]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_190\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][19]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_191\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][1]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_173\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][20]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_192\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][21]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_193\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][22]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_194\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][23]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_195\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][24]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_196\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][25]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_197\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][26]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_198\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][27]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_199\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_200\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][2]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_174\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_175\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_176\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_177\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_178\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_179\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_180\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_181\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_140\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_150\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_151\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][12]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_152\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][16]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_156\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][17]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_157\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][18]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_158\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][19]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_159\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][1]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_141\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][20]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_160\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][21]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_161\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][22]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_162\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][23]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_163\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][24]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_164\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][25]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_165\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][26]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_166\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][27]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_167\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][28]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_168\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][2]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_142\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_143\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_144\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_145\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_146\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_147\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_148\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_149\, + \DET_HACTIVE.det_active_video_pol_int_reg\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_528\, + \DET_HSYNC.det_hsync_pol_int_reg\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_527\, + \DET_VSYNC.det_vsync_pol_int_reg\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_526\, + \GEN_HAS_IRQ.intr_err_reg[0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_588\, + \GEN_HAS_IRQ.intr_err_reg[14]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_602\, + \GEN_HAS_IRQ.intr_err_reg[15]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_603\, + \GEN_HAS_IRQ.intr_err_reg[1]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_589\, + \GEN_HAS_IRQ.intr_err_reg[2]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_590\, + \GEN_HAS_IRQ.intr_err_reg[3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_591\, + \GEN_HAS_IRQ.intr_err_reg[4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_592\, + \GEN_HAS_IRQ.intr_err_reg[5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_593\, + \GEN_HAS_IRQ.intr_err_reg[6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_594\, + \GEN_HAS_IRQ.intr_err_reg[7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_595\, + \GEN_HAS_IRQ.intr_stat_reg[0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_620\, + \GEN_HAS_IRQ.intr_stat_reg[10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_630\, + \GEN_HAS_IRQ.intr_stat_reg[11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_631\, + \GEN_HAS_IRQ.intr_stat_reg[12]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_632\, + \GEN_HAS_IRQ.intr_stat_reg[13]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_633\, + \GEN_HAS_IRQ.intr_stat_reg[14]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_634\, + \GEN_HAS_IRQ.intr_stat_reg[15]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_635\, + \GEN_HAS_IRQ.intr_stat_reg[16]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_636\, + \GEN_HAS_IRQ.intr_stat_reg[17]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_637\, + \GEN_HAS_IRQ.intr_stat_reg[18]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_638\, + \GEN_HAS_IRQ.intr_stat_reg[19]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_639\, + \GEN_HAS_IRQ.intr_stat_reg[1]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_621\, + \GEN_HAS_IRQ.intr_stat_reg[20]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_640\, + \GEN_HAS_IRQ.intr_stat_reg[21]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_641\, + \GEN_HAS_IRQ.intr_stat_reg[22]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_642\, + \GEN_HAS_IRQ.intr_stat_reg[23]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_643\, + \GEN_HAS_IRQ.intr_stat_reg[24]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_644\, + \GEN_HAS_IRQ.intr_stat_reg[25]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_645\, + \GEN_HAS_IRQ.intr_stat_reg[26]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_646\, + \GEN_HAS_IRQ.intr_stat_reg[27]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_647\, + \GEN_HAS_IRQ.intr_stat_reg[28]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_648\, + \GEN_HAS_IRQ.intr_stat_reg[29]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_649\, + \GEN_HAS_IRQ.intr_stat_reg[2]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_622\, + \GEN_HAS_IRQ.intr_stat_reg[30]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_650\, + \GEN_HAS_IRQ.intr_stat_reg[3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_623\, + \GEN_HAS_IRQ.intr_stat_reg[4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_624\, + \GEN_HAS_IRQ.intr_stat_reg[5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_625\, + \GEN_HAS_IRQ.intr_stat_reg[6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_626\, + \GEN_HAS_IRQ.intr_stat_reg[7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_627\, + \GEN_HAS_IRQ.intr_stat_reg[8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_628\, + \GEN_HAS_IRQ.intr_stat_reg[9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_629\, + \GEN_SEL_DELAY[3].sel_int_reg[3][0]\ => \AXI4_LITE_INTERFACE.CORE_MUX0_n_0\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][0]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_97\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][10]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_87\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][11]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_86\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][12]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_85\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][13]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_84\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][14]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_83\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][15]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_82\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][16]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_81\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][17]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_80\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][18]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_79\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][19]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_78\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][1]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_96\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][20]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_77\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][21]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_76\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][22]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_75\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][23]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_74\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][24]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_73\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][25]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_72\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][26]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_71\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][27]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_70\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][28]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_69\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][29]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_68\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][2]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_95\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][30]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_67\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][31]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_66\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][3]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_94\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][4]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_93\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][5]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_92\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][6]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_91\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][7]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_90\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][8]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_89\, + \GEN_TREE.GEN_BRANCH[3].GEN_MUX_REG.data_out_reg_reg[3][9]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_88\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][0]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_65\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][10]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_55\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][11]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_54\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][12]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_53\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][13]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_52\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][14]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_51\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][15]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_50\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][16]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_49\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][17]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_48\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][18]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_47\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][19]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_46\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][1]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_64\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][20]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_45\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][21]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_44\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][22]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_43\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][23]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_42\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][24]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_41\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][25]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_40\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][26]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_39\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][27]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_38\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][28]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_37\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][29]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_36\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][2]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_63\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][30]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_35\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][31]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_34\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][3]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_62\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][4]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_61\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][5]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_60\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][6]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_59\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][7]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_58\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][8]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_57\, + \GEN_TREE.GEN_BRANCH[4].GEN_MUX_REG.data_out_reg_reg[4][9]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_56\, + \GEN_TREE.GEN_BRANCH[5].GEN_MUX_REG.data_out_reg_reg[5][31]_0\ => \AXI4_LITE_INTERFACE.GENR_MUX0_n_1\, + Q(25 downto 13) => genr_regs(1180 downto 1168), + Q(12 downto 1) => genr_regs(1164 downto 1153), + Q(0) => \time_control_regs2_int[28]\(0), + core_regs(351 downto 341) => core_regs(506 downto 496), + core_regs(340 downto 330) => core_regs(491 downto 481), + core_regs(329 downto 319) => core_regs(474 downto 464), + core_regs(318 downto 308) => core_regs(459 downto 449), + core_regs(307 downto 297) => core_regs(442 downto 432), + core_regs(296 downto 286) => core_regs(427 downto 417), + core_regs(285 downto 275) => core_regs(410 downto 400), + core_regs(274 downto 264) => core_regs(395 downto 385), + core_regs(263 downto 253) => core_regs(378 downto 368), + core_regs(252 downto 242) => core_regs(363 downto 353), + core_regs(241 downto 231) => core_regs(346 downto 336), + core_regs(230 downto 220) => core_regs(331 downto 321), + core_regs(219 downto 209) => core_regs(314 downto 304), + core_regs(208 downto 198) => core_regs(299 downto 289), + core_regs(197 downto 187) => core_regs(282 downto 272), + core_regs(186 downto 176) => core_regs(267 downto 257), + core_regs(175 downto 165) => core_regs(250 downto 240), + core_regs(164 downto 154) => core_regs(235 downto 225), + core_regs(153 downto 143) => core_regs(218 downto 208), + core_regs(142 downto 132) => core_regs(203 downto 193), + core_regs(131 downto 121) => core_regs(186 downto 176), + core_regs(120 downto 110) => core_regs(171 downto 161), + core_regs(109 downto 99) => core_regs(154 downto 144), + core_regs(98 downto 88) => core_regs(139 downto 129), + core_regs(87 downto 77) => core_regs(122 downto 112), + core_regs(76 downto 66) => core_regs(107 downto 97), + core_regs(65 downto 55) => core_regs(90 downto 80), + core_regs(54 downto 44) => core_regs(75 downto 65), + core_regs(43 downto 33) => core_regs(58 downto 48), + core_regs(32 downto 22) => core_regs(43 downto 33), + core_regs(21 downto 11) => core_regs(26 downto 16), + core_regs(10 downto 0) => core_regs(11 downto 1), + \core_status_regs[0]\(8 downto 4) => \core_status_regs[0]\(31 downto 27), + \core_status_regs[0]\(3 downto 0) => \core_status_regs[0]\(15 downto 12), + \core_status_regs[10]\(8 downto 4) => \core_status_regs[10]\(31 downto 27), + \core_status_regs[10]\(3 downto 0) => \core_status_regs[10]\(15 downto 12), + \core_status_regs[11]\(8 downto 4) => \core_status_regs[11]\(31 downto 27), + \core_status_regs[11]\(3 downto 0) => \core_status_regs[11]\(15 downto 12), + \core_status_regs[12]\(8 downto 4) => \core_status_regs[12]\(31 downto 27), + \core_status_regs[12]\(3 downto 0) => \core_status_regs[12]\(15 downto 12), + \core_status_regs[13]\(8 downto 4) => \core_status_regs[13]\(31 downto 27), + \core_status_regs[13]\(3 downto 0) => \core_status_regs[13]\(15 downto 12), + \core_status_regs[14]\(8 downto 4) => \core_status_regs[14]\(31 downto 27), + \core_status_regs[14]\(3 downto 0) => \core_status_regs[14]\(15 downto 12), + \core_status_regs[15]\(8 downto 4) => \core_status_regs[15]\(31 downto 27), + \core_status_regs[15]\(3 downto 0) => \core_status_regs[15]\(15 downto 12), + \core_status_regs[1]\(8 downto 4) => \core_status_regs[1]\(31 downto 27), + \core_status_regs[1]\(3 downto 0) => \core_status_regs[1]\(15 downto 12), + \core_status_regs[2]\(8 downto 4) => \core_status_regs[2]\(31 downto 27), + \core_status_regs[2]\(3 downto 0) => \core_status_regs[2]\(15 downto 12), + \core_status_regs[3]\(8 downto 4) => \core_status_regs[3]\(31 downto 27), + \core_status_regs[3]\(3 downto 0) => \core_status_regs[3]\(15 downto 12), + \core_status_regs[4]\(8 downto 4) => \core_status_regs[4]\(31 downto 27), + \core_status_regs[4]\(3 downto 0) => \core_status_regs[4]\(15 downto 12), + \core_status_regs[5]\(8 downto 4) => \core_status_regs[5]\(31 downto 27), + \core_status_regs[5]\(3 downto 0) => \core_status_regs[5]\(15 downto 12), + \core_status_regs[6]\(8 downto 4) => \core_status_regs[6]\(31 downto 27), + \core_status_regs[6]\(3 downto 0) => \core_status_regs[6]\(15 downto 12), + \core_status_regs[7]\(8 downto 4) => \core_status_regs[7]\(31 downto 27), + \core_status_regs[7]\(3 downto 0) => \core_status_regs[7]\(15 downto 12), + \core_status_regs[8]\(8 downto 4) => \core_status_regs[8]\(31 downto 27), + \core_status_regs[8]\(3 downto 0) => \core_status_regs[8]\(15 downto 12), + \core_status_regs[9]\(8 downto 4) => \core_status_regs[9]\(31 downto 27), + \core_status_regs[9]\(3 downto 0) => \core_status_regs[9]\(15 downto 12), + \data_sync_reg[2][34]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_139\, + \data_sync_reg[2][34]_0\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_110\, + \data_sync_reg[2][34]_1\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_171\, + \data_sync_reg[2][34]_10\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_187\, + \data_sync_reg[2][34]_100\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_380\, + \data_sync_reg[2][34]_101\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_379\, + \data_sync_reg[2][34]_102\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_378\, + \data_sync_reg[2][34]_103\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_377\, + \data_sync_reg[2][34]_104\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_376\, + \data_sync_reg[2][34]_105\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_375\, + \data_sync_reg[2][34]_106\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_374\, + \data_sync_reg[2][34]_107\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_373\, + \data_sync_reg[2][34]_108\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_372\, + \data_sync_reg[2][34]_109\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_371\, + \data_sync_reg[2][34]_11\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_186\, + \data_sync_reg[2][34]_110\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_370\, + \data_sync_reg[2][34]_111\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_369\, + \data_sync_reg[2][34]_112\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_368\, + \data_sync_reg[2][34]_113\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_367\, + \data_sync_reg[2][34]_114\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_366\, + \data_sync_reg[2][34]_115\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_365\, + \data_sync_reg[2][34]_116\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_364\, + \data_sync_reg[2][34]_117\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_427\, + \data_sync_reg[2][34]_118\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_426\, + \data_sync_reg[2][34]_119\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_425\, + \data_sync_reg[2][34]_12\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_185\, + \data_sync_reg[2][34]_120\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_424\, + \data_sync_reg[2][34]_121\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_423\, + \data_sync_reg[2][34]_122\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_422\, + \data_sync_reg[2][34]_123\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_421\, + \data_sync_reg[2][34]_124\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_420\, + \data_sync_reg[2][34]_125\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_419\, + \data_sync_reg[2][34]_126\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_418\, + \data_sync_reg[2][34]_127\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_417\, + \data_sync_reg[2][34]_128\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_416\, + \data_sync_reg[2][34]_129\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_415\, + \data_sync_reg[2][34]_13\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_235\, + \data_sync_reg[2][34]_130\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_414\, + \data_sync_reg[2][34]_131\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_413\, + \data_sync_reg[2][34]_132\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_412\, + \data_sync_reg[2][34]_133\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_411\, + \data_sync_reg[2][34]_134\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_410\, + \data_sync_reg[2][34]_135\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_409\, + \data_sync_reg[2][34]_136\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_408\, + \data_sync_reg[2][34]_137\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_407\, + \data_sync_reg[2][34]_138\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_406\, + \data_sync_reg[2][34]_139\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_405\, + \data_sync_reg[2][34]_14\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_234\, + \data_sync_reg[2][34]_140\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_404\, + \data_sync_reg[2][34]_141\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_403\, + \data_sync_reg[2][34]_142\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_402\, + \data_sync_reg[2][34]_143\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_401\, + \data_sync_reg[2][34]_144\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_400\, + \data_sync_reg[2][34]_145\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_399\, + \data_sync_reg[2][34]_146\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_398\, + \data_sync_reg[2][34]_147\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_397\, + \data_sync_reg[2][34]_148\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_396\, + \data_sync_reg[2][34]_149\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_459\, + \data_sync_reg[2][34]_15\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_233\, + \data_sync_reg[2][34]_150\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_458\, + \data_sync_reg[2][34]_151\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_457\, + \data_sync_reg[2][34]_152\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_456\, + \data_sync_reg[2][34]_153\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_443\, + \data_sync_reg[2][34]_154\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_442\, + \data_sync_reg[2][34]_155\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_441\, + \data_sync_reg[2][34]_156\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_440\, + \data_sync_reg[2][34]_157\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_491\, + \data_sync_reg[2][34]_158\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_490\, + \data_sync_reg[2][34]_159\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_489\, + \data_sync_reg[2][34]_16\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_219\, + \data_sync_reg[2][34]_160\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_488\, + \data_sync_reg[2][34]_161\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_475\, + \data_sync_reg[2][34]_162\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_474\, + \data_sync_reg[2][34]_163\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_473\, + \data_sync_reg[2][34]_164\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_472\, + \data_sync_reg[2][34]_165\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_523\, + \data_sync_reg[2][34]_166\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_522\, + \data_sync_reg[2][34]_167\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_521\, + \data_sync_reg[2][34]_168\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_520\, + \data_sync_reg[2][34]_169\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_519\, + \data_sync_reg[2][34]_17\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_218\, + \data_sync_reg[2][34]_170\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_518\, + \data_sync_reg[2][34]_171\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_517\, + \data_sync_reg[2][34]_172\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_516\, + \data_sync_reg[2][34]_173\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_515\, + \data_sync_reg[2][34]_174\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_514\, + \data_sync_reg[2][34]_175\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_513\, + \data_sync_reg[2][34]_176\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_512\, + \data_sync_reg[2][34]_177\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_511\, + \data_sync_reg[2][34]_178\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_510\, + \data_sync_reg[2][34]_179\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_509\, + \data_sync_reg[2][34]_18\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_217\, + \data_sync_reg[2][34]_180\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_508\, + \data_sync_reg[2][34]_181\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_507\, + \data_sync_reg[2][34]_182\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_506\, + \data_sync_reg[2][34]_183\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_505\, + \data_sync_reg[2][34]_184\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_504\, + \data_sync_reg[2][34]_185\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_555\, + \data_sync_reg[2][34]_186\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_554\, + \data_sync_reg[2][34]_187\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_553\, + \data_sync_reg[2][34]_188\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_552\, + \data_sync_reg[2][34]_189\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_551\, + \data_sync_reg[2][34]_19\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_267\, + \data_sync_reg[2][34]_190\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_550\, + \data_sync_reg[2][34]_191\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_549\, + \data_sync_reg[2][34]_192\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_548\, + \data_sync_reg[2][34]_193\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_547\, + \data_sync_reg[2][34]_194\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_546\, + \data_sync_reg[2][34]_195\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_545\, + \data_sync_reg[2][34]_196\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_544\, + \data_sync_reg[2][34]_197\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_543\, + \data_sync_reg[2][34]_198\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_542\, + \data_sync_reg[2][34]_199\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_541\, + \data_sync_reg[2][34]_2\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_170\, + \data_sync_reg[2][34]_20\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_266\, + \data_sync_reg[2][34]_200\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_540\, + \data_sync_reg[2][34]_201\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_539\, + \data_sync_reg[2][34]_202\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_538\, + \data_sync_reg[2][34]_203\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_537\, + \data_sync_reg[2][34]_204\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_536\, + \data_sync_reg[2][34]_205\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_535\, + \data_sync_reg[2][34]_206\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_534\, + \data_sync_reg[2][34]_207\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_533\, + \data_sync_reg[2][34]_208\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_531\, + \data_sync_reg[2][34]_209\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_530\, + \data_sync_reg[2][34]_21\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_265\, + \data_sync_reg[2][34]_210\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_529\, + \data_sync_reg[2][34]_211\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_525\, + \data_sync_reg[2][34]_212\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_524\, + \data_sync_reg[2][34]_213\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_587\, + \data_sync_reg[2][34]_214\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_586\, + \data_sync_reg[2][34]_215\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_585\, + \data_sync_reg[2][34]_216\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_584\, + \data_sync_reg[2][34]_217\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_583\, + \data_sync_reg[2][34]_218\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_571\, + \data_sync_reg[2][34]_219\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_570\, + \data_sync_reg[2][34]_22\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_251\, + \data_sync_reg[2][34]_220\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_569\, + \data_sync_reg[2][34]_221\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_568\, + \data_sync_reg[2][34]_222\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_138\, + \data_sync_reg[2][34]_23\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_250\, + \data_sync_reg[2][34]_24\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_249\, + \data_sync_reg[2][34]_25\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_299\, + \data_sync_reg[2][34]_26\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_298\, + \data_sync_reg[2][34]_27\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_297\, + \data_sync_reg[2][34]_28\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_296\, + \data_sync_reg[2][34]_29\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_295\, + \data_sync_reg[2][34]_3\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_169\, + \data_sync_reg[2][34]_30\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_294\, + \data_sync_reg[2][34]_31\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_293\, + \data_sync_reg[2][34]_32\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_292\, + \data_sync_reg[2][34]_33\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_291\, + \data_sync_reg[2][34]_34\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_290\, + \data_sync_reg[2][34]_35\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_289\, + \data_sync_reg[2][34]_36\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_288\, + \data_sync_reg[2][34]_37\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_287\, + \data_sync_reg[2][34]_38\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_286\, + \data_sync_reg[2][34]_39\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_285\, + \data_sync_reg[2][34]_4\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_155\, + \data_sync_reg[2][34]_40\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_284\, + \data_sync_reg[2][34]_41\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_283\, + \data_sync_reg[2][34]_42\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_282\, + \data_sync_reg[2][34]_43\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_281\, + \data_sync_reg[2][34]_44\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_280\, + \data_sync_reg[2][34]_45\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_279\, + \data_sync_reg[2][34]_46\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_278\, + \data_sync_reg[2][34]_47\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_331\, + \data_sync_reg[2][34]_48\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_330\, + \data_sync_reg[2][34]_49\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_329\, + \data_sync_reg[2][34]_5\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_154\, + \data_sync_reg[2][34]_50\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_315\, + \data_sync_reg[2][34]_51\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_314\, + \data_sync_reg[2][34]_52\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_313\, + \data_sync_reg[2][34]_53\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_363\, + \data_sync_reg[2][34]_54\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_362\, + \data_sync_reg[2][34]_55\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_361\, + \data_sync_reg[2][34]_56\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_360\, + \data_sync_reg[2][34]_57\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_359\, + \data_sync_reg[2][34]_58\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_358\, + \data_sync_reg[2][34]_59\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_357\, + \data_sync_reg[2][34]_6\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_153\, + \data_sync_reg[2][34]_60\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_356\, + \data_sync_reg[2][34]_61\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_355\, + \data_sync_reg[2][34]_62\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_354\, + \data_sync_reg[2][34]_63\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_353\, + \data_sync_reg[2][34]_64\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_352\, + \data_sync_reg[2][34]_65\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_351\, + \data_sync_reg[2][34]_66\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_350\, + \data_sync_reg[2][34]_67\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_349\, + \data_sync_reg[2][34]_68\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_348\, + \data_sync_reg[2][34]_69\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_347\, + \data_sync_reg[2][34]_7\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_203\, + \data_sync_reg[2][34]_70\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_346\, + \data_sync_reg[2][34]_71\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_345\, + \data_sync_reg[2][34]_72\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_344\, + \data_sync_reg[2][34]_73\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_343\, + \data_sync_reg[2][34]_74\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_342\, + \data_sync_reg[2][34]_75\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_341\, + \data_sync_reg[2][34]_76\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_340\, + \data_sync_reg[2][34]_77\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_339\, + \data_sync_reg[2][34]_78\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_338\, + \data_sync_reg[2][34]_79\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_337\, + \data_sync_reg[2][34]_8\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_202\, + \data_sync_reg[2][34]_80\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_336\, + \data_sync_reg[2][34]_81\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_335\, + \data_sync_reg[2][34]_82\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_334\, + \data_sync_reg[2][34]_83\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_333\, + \data_sync_reg[2][34]_84\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_332\, + \data_sync_reg[2][34]_85\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_395\, + \data_sync_reg[2][34]_86\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_394\, + \data_sync_reg[2][34]_87\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_393\, + \data_sync_reg[2][34]_88\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_392\, + \data_sync_reg[2][34]_89\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_391\, + \data_sync_reg[2][34]_9\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_201\, + \data_sync_reg[2][34]_90\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_390\, + \data_sync_reg[2][34]_91\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_389\, + \data_sync_reg[2][34]_92\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_388\, + \data_sync_reg[2][34]_93\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_387\, + \data_sync_reg[2][34]_94\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_386\, + \data_sync_reg[2][34]_95\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_385\, + \data_sync_reg[2][34]_96\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_384\, + \data_sync_reg[2][34]_97\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_383\, + \data_sync_reg[2][34]_98\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_382\, + \data_sync_reg[2][34]_99\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_381\, + \det_hfp_start_int2_reg[10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_566\, + \det_hfp_start_int2_reg[11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_567\, + \det_hfp_start_int2_reg[3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_559\, + \det_hfp_start_int2_reg[4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_560\, + \det_hfp_start_int2_reg[5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_561\, + \det_hfp_start_int2_reg[6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_562\, + \det_hfp_start_int2_reg[7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_563\, + \det_hfp_start_int2_reg[8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_564\, + \det_hfp_start_int2_reg[9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_565\, + \det_htotal_int2_reg[11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_503\, + \det_v0active_start_hori_int2_reg[0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_476\, + \det_v0active_start_hori_int2_reg[10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_486\, + \det_v0active_start_hori_int2_reg[11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_487\, + \det_v0active_start_hori_int2_reg[1]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_477\, + \det_v0active_start_hori_int2_reg[2]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_478\, + \det_v0active_start_hori_int2_reg[3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_479\, + \det_v0active_start_hori_int2_reg[4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_480\, + \det_v0active_start_hori_int2_reg[5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_481\, + \det_v0active_start_hori_int2_reg[6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_482\, + \det_v0active_start_hori_int2_reg[7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_483\, + \det_v0active_start_hori_int2_reg[8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_484\, + \det_v0active_start_hori_int2_reg[9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_485\, + \det_v0bp_start_hori_int2_reg[0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_444\, + \det_v0bp_start_hori_int2_reg[10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_454\, + \det_v0bp_start_hori_int2_reg[11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_455\, + \det_v0bp_start_hori_int2_reg[1]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_445\, + \det_v0bp_start_hori_int2_reg[2]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_446\, + \det_v0bp_start_hori_int2_reg[3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_447\, + \det_v0bp_start_hori_int2_reg[4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_448\, + \det_v0bp_start_hori_int2_reg[5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_449\, + \det_v0bp_start_hori_int2_reg[6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_450\, + \det_v0bp_start_hori_int2_reg[7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_451\, + \det_v0bp_start_hori_int2_reg[8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_452\, + \det_v0bp_start_hori_int2_reg[9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_453\, + \det_v0fp_start_hori_int2_reg[0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_460\, + \det_v0fp_start_hori_int2_reg[10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_470\, + \det_v0fp_start_hori_int2_reg[11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_471\, + \det_v0fp_start_hori_int2_reg[1]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_461\, + \det_v0fp_start_hori_int2_reg[2]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_462\, + \det_v0fp_start_hori_int2_reg[3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_463\, + \det_v0fp_start_hori_int2_reg[4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_464\, + \det_v0fp_start_hori_int2_reg[5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_465\, + \det_v0fp_start_hori_int2_reg[6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_466\, + \det_v0fp_start_hori_int2_reg[7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_467\, + \det_v0fp_start_hori_int2_reg[8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_468\, + \det_v0fp_start_hori_int2_reg[9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_469\, + \det_v0fp_start_int_reg[0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_572\, + \det_v0fp_start_int_reg[10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_582\, + \det_v0fp_start_int_reg[1]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_573\, + \det_v0fp_start_int_reg[2]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_574\, + \det_v0fp_start_int_reg[3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_575\, + \det_v0fp_start_int_reg[4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_576\, + \det_v0fp_start_int_reg[5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_577\, + \det_v0fp_start_int_reg[6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_578\, + \det_v0fp_start_int_reg[7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_579\, + \det_v0fp_start_int_reg[8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_580\, + \det_v0fp_start_int_reg[9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_581\, + \det_v0sync_start_hori_int2_reg[0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_428\, + \det_v0sync_start_hori_int2_reg[10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_438\, + \det_v0sync_start_hori_int2_reg[11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_439\, + \det_v0sync_start_hori_int2_reg[1]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_429\, + \det_v0sync_start_hori_int2_reg[2]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_430\, + \det_v0sync_start_hori_int2_reg[3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_431\, + \det_v0sync_start_hori_int2_reg[4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_432\, + \det_v0sync_start_hori_int2_reg[5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_433\, + \det_v0sync_start_hori_int2_reg[6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_434\, + \det_v0sync_start_hori_int2_reg[7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_435\, + \det_v0sync_start_hori_int2_reg[8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_436\, + \det_v0sync_start_hori_int2_reg[9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_437\, + \det_v0total_reg[0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_492\, + \det_v0total_reg[10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_502\, + \det_v0total_reg[1]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_493\, + \det_v0total_reg[2]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_494\, + \det_v0total_reg[3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_495\, + \det_v0total_reg[4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_496\, + \det_v0total_reg[5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_497\, + \det_v0total_reg[6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_498\, + \det_v0total_reg[7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_499\, + \det_v0total_reg[8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_500\, + \det_v0total_reg[9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_501\, + \gen_v0chroma_start_reg[0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_532\, + genr_data(31 downto 0) => genr_data(31 downto 0), + \intr_status_int_reg[10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_557\, + \intr_status_int_reg[11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_558\, + \intr_status_int_reg[12]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_301\, + \intr_status_int_reg[8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_556\, + ipif_Addr(4 downto 3) => ipif_Addr(7 downto 6), + ipif_Addr(2 downto 0) => ipif_Addr(4 downto 2), + \time_status_regs[28]\(5 downto 3) => \time_status_regs[28]\(31 downto 29), + \time_status_regs[28]\(2 downto 0) => \time_status_regs[28]\(15 downto 13), + vid_aclk => vid_aclk + ); +\AXI4_LITE_INTERFACE.SYNC2PROCCLK_I\: entity work.\Arty_Z7_20_v_tc_1_0_video_clock_cross__parameterized0\ + port map ( + \AXI4_LITE_INTERFACE.ipif_Error_reg\ => \AXI4_LITE_INTERFACE.SYNC2PROCCLK_I_n_36\, + aclk => aclk, + in_data(33) => write_ack, + in_data(32) => read_ack_d(4), + in_data(31 downto 0) => ipif_RdData(31 downto 0), + out_data(33 downto 0) => p_143_out(33 downto 0), + p_526_out => p_526_out, + p_528_out => p_528_out, + read_ack_d1 => read_ack_d1, + read_ack_d2 => read_ack_d2, + write_ack_d1 => write_ack_d1, + write_ack_d2 => write_ack_d2 + ); +\AXI4_LITE_INTERFACE.SYNC2VIDCLK_I\: entity work.Arty_Z7_20_v_tc_1_0_video_clock_cross + port map ( + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]\(0) => \core_control_regs_int[0]\(26), + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]_0\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_110\, + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][0]\(0) => \core_control_regs_int[10]\(26), + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][0]\(0) => \core_control_regs_int[11]\(26), + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][0]\(0) => \core_control_regs_int[13]\(26), + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][0]\(0) => \core_control_regs_int[14]\(26), + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][0]\(0) => \core_control_regs_int[15]\(26), + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][0]\(0) => \core_control_regs_int[16]\(26), + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][0]\(0) => \core_control_regs_int[1]\(26), + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][0]\(0) => \core_control_regs_int[2]\(26), + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][0]\(0) => \core_control_regs_int[3]\(26), + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][0]\(0) => \core_control_regs_int[4]\(26), + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][0]\(0) => \core_control_regs_int[5]\(26), + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][0]\(0) => \core_control_regs_int[6]\(26), + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][0]\(0) => \core_control_regs_int[7]\(26), + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][0]\(0) => \core_control_regs_int[8]\(26), + \AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][0]\(0) => \core_control_regs_int[9]\(26), + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][0]\(0) => \genr_control_regs_int[0]\(31), + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_52\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_51\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][12]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_50\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][13]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_49\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][16]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_48\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][17]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_47\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][18]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_46\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][19]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_45\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][20]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_44\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][21]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_43\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][22]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_42\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][23]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_41\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][24]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_40\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][25]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_39\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][26]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_38\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][27]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_37\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][28]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_36\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][29]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_35\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][30]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_34\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][31]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_0\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_54\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_53\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][16]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_60\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][17]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_59\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][18]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_58\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][19]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_57\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][20]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_56\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][21]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_55\, + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][21]_0\(5 downto 0) => \^genr_control_regs[2]\(21 downto 16), + \AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][8]\(0) => \genr_control_regs_int[3]\(31), + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(31) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_61\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(30) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_62\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(29) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_63\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(28) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_64\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(27) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_65\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(26) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_66\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(25) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_67\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(24) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_68\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(23) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_69\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(22) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_70\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(21) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_71\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(20) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_72\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(19) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_73\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(18) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_74\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(17) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_75\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(16) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_76\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(15) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_77\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(14) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_78\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(13) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_79\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(12) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_80\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(11) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_81\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(10) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_82\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(9) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_83\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(8) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_84\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(7) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_85\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(6) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_86\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(5) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_87\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(4) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_88\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(3) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_89\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(2) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_90\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(1) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_91\, + \AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\(0) => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_92\, + \AXI4_LITE_INTERFACE.proc_sync1_reg[44]\(44 downto 0) => proc_sync1(44 downto 0), + \AXI4_LITE_INTERFACE.soft_resetn_reg\ => \^resetn_out\, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][0]\(0) => \time_control_regs_int[16]\(28), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(25) => p_24_in, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(24) => p_23_in, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(23) => p_22_in, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(22) => p_21_in, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(21) => p_20_in, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(20) => p_19_in, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(19) => p_18_in, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(18) => p_17_in, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(17) => p_16_in, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(16) => p_15_in, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(15) => p_14_in, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(14) => p_13_in, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(13) => p_12_in, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(12) => p_11_in, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(11) => p_10_in, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(10) => p_9_in, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(9) => p_8_in, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(8) => p_7_in, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(7) => p_6_in, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(6) => p_5_in, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(5) => p_4_in, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(4) => p_3_in, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(3) => p_2_in, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(2) => p_1_in, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(1) => p_0_in, + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\(0) => \time_control_regs2_int[16]\(0), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][7]\(0) => \time_control_regs_int[18]\(6), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9]\(7 downto 5) => p_5_out(9 downto 7), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9]\(4) => \^time_control_regs[18]\(6), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9]\(3 downto 0) => \^time_control_regs[18]\(3 downto 0), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][0]\(0) => p_2_out(6), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6]\(6) => \^time_control_regs[19]\(6), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6]\(5 downto 0) => p_8_out(5 downto 0), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][0]\(0) => \time_control_regs_int[20]\(28), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\(25 downto 13) => genr_regs(924 downto 912), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\(12 downto 1) => genr_regs(908 downto 897), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\(0) => \time_control_regs2_int[20]\(0), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][0]\(0) => \time_control_regs_int[21]\(28), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\(25 downto 13) => genr_regs(956 downto 944), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\(12 downto 1) => genr_regs(940 downto 929), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\(0) => \time_control_regs2_int[21]\(0), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][0]\(0) => \time_control_regs_int[22]\(28), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\(25 downto 13) => genr_regs(988 downto 976), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\(12 downto 1) => genr_regs(972 downto 961), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\(0) => \time_control_regs2_int[22]\(0), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][0]\(0) => \time_control_regs_int[23]\(28), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\(25 downto 13) => genr_regs(1020 downto 1008), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\(12 downto 1) => genr_regs(1004 downto 993), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\(0) => \time_control_regs2_int[23]\(0), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][0]\(0) => \time_control_regs_int[24]\(28), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\(25 downto 13) => genr_regs(1052 downto 1040), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\(12 downto 1) => genr_regs(1036 downto 1025), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\(0) => \time_control_regs2_int[24]\(0), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][0]\(0) => \time_control_regs_int[25]\(28), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\(25 downto 13) => genr_regs(1084 downto 1072), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\(12 downto 1) => genr_regs(1068 downto 1057), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\(0) => \time_control_regs2_int[25]\(0), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][0]\(0) => \time_control_regs_int[26]\(28), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\(25 downto 13) => genr_regs(1116 downto 1104), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\(12 downto 1) => genr_regs(1100 downto 1089), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\(0) => \time_control_regs2_int[26]\(0), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][0]\(0) => \time_control_regs_int[27]\(28), + \AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][0]\(0) => \time_control_regs_int[28]\(28), + D(21 downto 6) => \^genr_control_regs[1]\(31 downto 16), + D(5 downto 0) => \^genr_control_regs[1]\(13 downto 8), + E(0) => \core_control_regs_int[12]\(26), + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_620\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_630\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_631\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][12]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_632\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][13]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_633\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][14]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_634\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][15]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_635\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][16]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_636\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][17]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_637\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][18]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_638\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][19]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_639\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][1]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_621\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][20]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_640\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][21]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_641\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][22]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_642\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][23]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_643\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][24]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_644\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][25]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_645\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][26]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_646\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][27]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_647\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][28]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_648\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][29]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_649\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][2]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_622\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][30]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_650\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][31]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_137\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_623\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_624\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_625\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_626\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_627\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_628\, + \GEN_TREE.GEN_BRANCH[31].GEN_MUX_REG.data_out_reg_reg[31][9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_629\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_588\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_598\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_599\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][12]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_600\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][13]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_601\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][14]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_602\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][15]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_603\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][16]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_604\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][17]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_605\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][18]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_606\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][19]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_607\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][1]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_589\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][20]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_608\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][21]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_609\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][22]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_610\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][23]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_611\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][24]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_612\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][25]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_613\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][26]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_614\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][27]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_615\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][28]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_616\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][29]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_617\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][2]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_590\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][30]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_618\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][31]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_619\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_591\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_592\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_593\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_594\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_595\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_596\, + \GEN_TREE.GEN_BRANCH[32].GEN_MUX_REG.data_out_reg_reg[32][9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_597\, + \GEN_TREE.GEN_BRANCH[33].GEN_MUX_REG.data_out_reg_reg[33][26]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_139\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_556\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_566\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_567\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][12]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_568\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][13]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_569\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][14]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_570\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][15]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_571\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][16]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_572\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][17]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_573\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][18]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_574\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][19]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_575\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][1]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_557\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][20]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_576\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][21]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_577\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][22]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_578\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][23]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_579\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][24]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_580\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][25]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_581\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][26]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_582\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][27]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_583\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][28]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_584\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][29]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_585\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][2]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_558\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][30]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_586\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_138\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][31]_0\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_587\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_559\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_560\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_561\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_562\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_563\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_564\, + \GEN_TREE.GEN_BRANCH[35].GEN_MUX_REG.data_out_reg_reg[35][9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_565\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_524\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_534\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_535\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][12]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_536\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][13]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_537\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][14]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_538\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][15]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_539\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][16]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_540\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][17]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_541\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][18]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_542\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][19]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_543\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][1]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_525\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][20]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_544\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][21]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_545\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][22]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_546\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][23]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_547\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][24]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_548\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][25]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_549\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][26]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_550\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][27]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_551\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][28]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_552\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][29]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_553\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][2]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_526\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][30]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_554\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][31]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_555\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_527\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_528\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_529\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_530\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_531\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_532\, + \GEN_TREE.GEN_BRANCH[36].GEN_MUX_REG.data_out_reg_reg[36][9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_533\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_492\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_502\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_503\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][12]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_504\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][13]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_505\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][14]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_506\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][15]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_507\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][16]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_508\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][17]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_509\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][18]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_510\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][19]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_511\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][1]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_493\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][20]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_512\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][21]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_513\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][22]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_514\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][23]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_515\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][24]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_516\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][25]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_517\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][26]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_518\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][27]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_519\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][28]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_520\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][29]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_521\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][2]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_494\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][30]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_522\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][31]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_523\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_495\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_496\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_497\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_498\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_499\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_500\, + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_501\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_460\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_470\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_471\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][12]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_472\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][13]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_473\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][14]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_474\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][15]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_475\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][16]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_476\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][17]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_477\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][18]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_478\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][19]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_479\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][1]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_461\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][20]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_480\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][21]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_481\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][22]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_482\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][23]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_483\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][24]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_484\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][25]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_485\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][26]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_486\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][27]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_487\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][28]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_488\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][29]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_489\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][2]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_462\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][30]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_490\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][31]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_491\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_463\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_464\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_465\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_466\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_467\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_468\, + \GEN_TREE.GEN_BRANCH[38].GEN_MUX_REG.data_out_reg_reg[38][9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_469\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_428\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_438\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_439\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][12]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_440\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][13]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_441\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][14]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_442\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][15]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_443\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][16]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_444\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][17]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_445\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][18]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_446\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][19]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_447\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][1]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_429\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][20]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_448\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][21]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_449\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][22]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_450\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][23]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_451\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][24]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_452\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][25]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_453\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][26]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_454\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][27]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_455\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][28]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_456\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][29]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_457\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][2]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_430\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][30]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_458\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][31]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_459\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_431\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_432\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_433\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_434\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_435\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_436\, + \GEN_TREE.GEN_BRANCH[39].GEN_MUX_REG.data_out_reg_reg[39][9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_437\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_396\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_406\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_407\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][12]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_408\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][13]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_409\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][14]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_410\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][15]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_411\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][16]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_412\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][17]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_413\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][18]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_414\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][19]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_415\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][1]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_397\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][20]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_416\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][21]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_417\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][22]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_418\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][23]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_419\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][24]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_420\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][25]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_421\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][26]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_422\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][27]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_423\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][28]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_424\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][29]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_425\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][2]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_398\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][30]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_426\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][31]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_427\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_399\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_400\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_401\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_402\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_403\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_404\, + \GEN_TREE.GEN_BRANCH[40].GEN_MUX_REG.data_out_reg_reg[40][9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_405\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_364\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_374\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_375\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][12]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_376\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][13]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_377\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][14]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_378\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][15]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_379\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][16]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_380\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][17]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_381\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][18]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_382\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][19]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_383\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][1]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_365\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][20]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_384\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][21]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_385\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][22]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_386\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][23]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_387\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][24]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_388\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][25]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_389\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][26]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_390\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][27]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_391\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][28]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_392\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][29]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_393\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][2]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_366\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][30]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_394\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][31]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_395\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_367\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_368\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_369\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_370\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_371\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_372\, + \GEN_TREE.GEN_BRANCH[41].GEN_MUX_REG.data_out_reg_reg[41][9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_373\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_332\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_342\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_343\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][12]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_344\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][13]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_345\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][14]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_346\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][15]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_347\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][16]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_348\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][17]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_349\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][18]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_350\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][19]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_351\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][1]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_333\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][20]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_352\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][21]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_353\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][22]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_354\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][23]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_355\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][24]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_356\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][25]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_357\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][26]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_358\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][27]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_359\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][28]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_360\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][29]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_361\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][2]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_334\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][30]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_362\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][31]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_363\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_335\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_336\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_337\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_338\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_339\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_340\, + \GEN_TREE.GEN_BRANCH[42].GEN_MUX_REG.data_out_reg_reg[42][9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_341\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_300\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_310\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_311\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][12]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_312\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][13]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_313\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][14]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_314\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][15]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_315\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][16]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_316\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][17]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_317\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][18]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_318\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][19]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_319\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][1]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_301\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][20]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_320\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][21]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_321\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][22]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_322\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][23]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_323\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][24]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_324\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][25]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_325\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][26]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_326\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][27]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_327\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][28]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_328\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][29]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_329\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][2]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_302\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][30]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_330\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][31]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_331\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_303\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_304\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_305\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_306\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_307\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_308\, + \GEN_TREE.GEN_BRANCH[43].GEN_MUX_REG.data_out_reg_reg[43][9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_309\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_268\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_278\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_279\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][12]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_280\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][13]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_281\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][14]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_282\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][15]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_283\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][16]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_284\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][17]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_285\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][18]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_286\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][19]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_287\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][1]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_269\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][20]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_288\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][21]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_289\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][22]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_290\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][23]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_291\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][24]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_292\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][25]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_293\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][26]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_294\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][27]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_295\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][28]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_296\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][29]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_297\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][2]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_270\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][30]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_298\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][31]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_299\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_271\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_272\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_273\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_274\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_275\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_276\, + \GEN_TREE.GEN_BRANCH[44].GEN_MUX_REG.data_out_reg_reg[44][9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_277\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_236\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_246\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_247\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][12]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_248\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][13]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_249\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][14]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_250\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][15]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_251\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][16]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_252\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][17]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_253\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][18]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_254\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][19]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_255\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][1]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_237\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][20]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_256\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][21]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_257\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][22]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_258\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][23]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_259\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][24]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_260\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][25]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_261\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][26]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_262\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][27]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_263\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][28]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_264\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][29]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_265\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][2]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_238\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][30]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_266\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][31]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_267\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_239\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_240\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_241\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_242\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_243\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_244\, + \GEN_TREE.GEN_BRANCH[45].GEN_MUX_REG.data_out_reg_reg[45][9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_245\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_204\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_214\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_215\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][12]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_216\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][13]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_217\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][14]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_218\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][15]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_219\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][16]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_220\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][17]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_221\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][18]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_222\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][19]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_223\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][1]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_205\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][20]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_224\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][21]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_225\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][22]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_226\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][23]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_227\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][24]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_228\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][25]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_229\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][26]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_230\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][27]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_231\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][28]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_232\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][29]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_233\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][2]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_206\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][30]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_234\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][31]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_235\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_207\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_208\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_209\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_210\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_211\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_212\, + \GEN_TREE.GEN_BRANCH[46].GEN_MUX_REG.data_out_reg_reg[46][9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_213\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_172\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_182\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_183\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][12]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_184\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][13]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_185\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][14]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_186\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][15]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_187\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][16]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_188\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][17]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_189\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][18]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_190\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][19]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_191\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][1]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_173\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][20]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_192\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][21]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_193\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][22]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_194\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][23]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_195\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][24]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_196\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][25]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_197\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][26]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_198\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][27]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_199\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][28]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_200\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][29]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_201\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][2]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_174\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][30]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_202\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][31]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_203\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_175\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_176\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_177\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_178\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_179\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_180\, + \GEN_TREE.GEN_BRANCH[47].GEN_MUX_REG.data_out_reg_reg[47][9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_181\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][0]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_140\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][10]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_150\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][11]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_151\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][12]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_152\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][13]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_153\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][14]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_154\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][15]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_155\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][16]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_156\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][17]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_157\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][18]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_158\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][19]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_159\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][1]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_141\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][20]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_160\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][21]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_161\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][22]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_162\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][23]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_163\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][24]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_164\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][25]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_165\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][26]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_166\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][27]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_167\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][28]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_168\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][29]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_169\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][2]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_142\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][30]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_170\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][31]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_171\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][3]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_143\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][4]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_144\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][5]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_145\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][6]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_146\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][7]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_147\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][8]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_148\, + \GEN_TREE.GEN_BRANCH[48].GEN_MUX_REG.data_out_reg_reg[48][9]\ => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_149\, + Q(25 downto 13) => genr_regs(1148 downto 1136), + Q(12 downto 1) => genr_regs(1132 downto 1121), + Q(0) => \time_control_regs2_int[27]\(0), + core_data(31 downto 0) => core_data(31 downto 0), + \genr_control_regs[0]\(24 downto 23) => \^genr_control_regs[0]\(31 downto 30), + \genr_control_regs[0]\(22 downto 9) => \^genr_control_regs[0]\(26 downto 13), + \genr_control_regs[0]\(8 downto 5) => \^genr_control_regs[0]\(11 downto 8), + \genr_control_regs[0]\(4) => \^genr_control_regs[0]\(5), + \genr_control_regs[0]\(3 downto 0) => \^genr_control_regs[0]\(3 downto 0), + \genr_control_regs[3]\(21 downto 6) => \^genr_control_regs[3]\(31 downto 16), + \genr_control_regs[3]\(5 downto 0) => \^genr_control_regs[3]\(13 downto 8), + genr_data(31 downto 0) => genr_data(31 downto 0), + \genr_status_regs[0]\(6 downto 4) => \genr_status_regs[0]\(29 downto 27), + \genr_status_regs[0]\(3) => \genr_status_regs[0]\(12), + \genr_status_regs[0]\(2 downto 1) => \genr_status_regs[0]\(7 downto 6), + \genr_status_regs[0]\(0) => \genr_status_regs[0]\(4), + \genr_status_regs[3]\(9 downto 8) => \genr_status_regs[3]\(15 downto 14), + \genr_status_regs[3]\(7 downto 0) => \genr_status_regs[3]\(7 downto 0), + \genr_status_regs_int_reg[1]\(30 downto 0) => \genr_status_regs_int_reg[1]\(30 downto 0), + intr_err(31 downto 0) => intr_err(31 downto 0), + ipif_Addr(8 downto 0) => ipif_Addr(8 downto 0), + out_data(32) => ipif_cs_out, + out_data(31 downto 0) => \^ipif_data_out\(31 downto 0), + p_456_out => p_456_out, + p_533_out => p_533_out, + p_535_out => p_535_out, + reg_update => reg_update, + \time_status_regs[0]\(31 downto 0) => \time_status_regs[0]\(31 downto 0), + \time_status_regs[10]\(31 downto 0) => \time_status_regs[10]\(31 downto 0), + \time_status_regs[11]\(31 downto 0) => \time_status_regs[11]\(31 downto 0), + \time_status_regs[12]\(31 downto 0) => \time_status_regs[12]\(31 downto 0), + \time_status_regs[13]\(31 downto 0) => \time_status_regs[13]\(31 downto 0), + \time_status_regs[14]\(31 downto 0) => \time_status_regs[14]\(31 downto 0), + \time_status_regs[15]\(31 downto 0) => \time_status_regs[15]\(31 downto 0), + \time_status_regs[16]\(5 downto 3) => \time_status_regs[16]\(31 downto 29), + \time_status_regs[16]\(2 downto 0) => \time_status_regs[16]\(15 downto 13), + \time_status_regs[17]\(31 downto 0) => \time_status_regs[17]\(31 downto 0), + \time_status_regs[18]\(23 downto 2) => \time_status_regs[18]\(31 downto 10), + \time_status_regs[18]\(1 downto 0) => \time_status_regs[18]\(5 downto 4), + \time_status_regs[19]\(24 downto 0) => \time_status_regs[19]\(31 downto 7), + \time_status_regs[1]\(31 downto 0) => \time_status_regs[1]\(31 downto 0), + \time_status_regs[20]\(5 downto 3) => \time_status_regs[20]\(31 downto 29), + \time_status_regs[20]\(2 downto 0) => \time_status_regs[20]\(15 downto 13), + \time_status_regs[21]\(5 downto 3) => \time_status_regs[21]\(31 downto 29), + \time_status_regs[21]\(2 downto 0) => \time_status_regs[21]\(15 downto 13), + \time_status_regs[22]\(5 downto 3) => \time_status_regs[22]\(31 downto 29), + \time_status_regs[22]\(2 downto 0) => \time_status_regs[22]\(15 downto 13), + \time_status_regs[23]\(5 downto 3) => \time_status_regs[23]\(31 downto 29), + \time_status_regs[23]\(2 downto 0) => \time_status_regs[23]\(15 downto 13), + \time_status_regs[24]\(5 downto 3) => \time_status_regs[24]\(31 downto 29), + \time_status_regs[24]\(2 downto 0) => \time_status_regs[24]\(15 downto 13), + \time_status_regs[25]\(5 downto 3) => \time_status_regs[25]\(31 downto 29), + \time_status_regs[25]\(2 downto 0) => \time_status_regs[25]\(15 downto 13), + \time_status_regs[26]\(5 downto 3) => \time_status_regs[26]\(31 downto 29), + \time_status_regs[26]\(2 downto 0) => \time_status_regs[26]\(15 downto 13), + \time_status_regs[27]\(5 downto 3) => \time_status_regs[27]\(31 downto 29), + \time_status_regs[27]\(2 downto 0) => \time_status_regs[27]\(15 downto 13), + \time_status_regs[2]\(31 downto 0) => \time_status_regs[2]\(31 downto 0), + \time_status_regs[3]\(31 downto 0) => \time_status_regs[3]\(31 downto 0), + \time_status_regs[4]\(31 downto 0) => \time_status_regs[4]\(31 downto 0), + \time_status_regs[5]\(31 downto 0) => \time_status_regs[5]\(31 downto 0), + \time_status_regs[6]\(31 downto 0) => \time_status_regs[6]\(31 downto 0), + \time_status_regs[7]\(31 downto 0) => \time_status_regs[7]\(31 downto 0), + \time_status_regs[8]\(31 downto 0) => \time_status_regs[8]\(31 downto 0), + \time_status_regs[9]\(31 downto 0) => \time_status_regs[9]\(31 downto 0), + vid_aclk => vid_aclk, + vid_aclk_en => vid_aclk_en, + vid_aresetn => vid_aresetn, + write_ack_int => write_ack_int + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => \core_control_regs2_int[0]\(0), + Q => \^core_control_regs[0]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(10), + Q => \^core_control_regs[0]\(10), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(11), + Q => \^core_control_regs[0]\(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(16), + Q => \^core_control_regs[0]\(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(17), + Q => \^core_control_regs[0]\(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(18), + Q => \^core_control_regs[0]\(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(19), + Q => \^core_control_regs[0]\(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(1), + Q => \^core_control_regs[0]\(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(20), + Q => \^core_control_regs[0]\(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(21), + Q => \^core_control_regs[0]\(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(22), + Q => \^core_control_regs[0]\(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(23), + Q => \^core_control_regs[0]\(23), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(24), + Q => \^core_control_regs[0]\(24), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(25), + Q => \^core_control_regs[0]\(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(26), + Q => \^core_control_regs[0]\(26), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(2), + Q => \^core_control_regs[0]\(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(3), + Q => \^core_control_regs[0]\(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(4), + Q => \^core_control_regs[0]\(4), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(5), + Q => \^core_control_regs[0]\(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(6), + Q => \^core_control_regs[0]\(6), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(7), + Q => \^core_control_regs[0]\(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(8), + Q => \^core_control_regs[0]\(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[0][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(9), + Q => \^core_control_regs[0]\(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => \core_control_regs2_int[10]\(0), + Q => \^core_control_regs[10]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(330), + Q => \^core_control_regs[10]\(10), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(331), + Q => \^core_control_regs[10]\(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(336), + Q => \^core_control_regs[10]\(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(337), + Q => \^core_control_regs[10]\(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(338), + Q => \^core_control_regs[10]\(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(339), + Q => \^core_control_regs[10]\(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(321), + Q => \^core_control_regs[10]\(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(340), + Q => \^core_control_regs[10]\(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(341), + Q => \^core_control_regs[10]\(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(342), + Q => \^core_control_regs[10]\(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(343), + Q => \^core_control_regs[10]\(23), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(344), + Q => \^core_control_regs[10]\(24), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(345), + Q => \^core_control_regs[10]\(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(346), + Q => \^core_control_regs[10]\(26), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(322), + Q => \^core_control_regs[10]\(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(323), + Q => \^core_control_regs[10]\(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(324), + Q => \^core_control_regs[10]\(4), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(325), + Q => \^core_control_regs[10]\(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(326), + Q => \^core_control_regs[10]\(6), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(327), + Q => \^core_control_regs[10]\(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(328), + Q => \^core_control_regs[10]\(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[10][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(329), + Q => \^core_control_regs[10]\(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => \core_control_regs2_int[11]\(0), + Q => \^core_control_regs[11]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(362), + Q => \^core_control_regs[11]\(10), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(363), + Q => \^core_control_regs[11]\(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(368), + Q => \^core_control_regs[11]\(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(369), + Q => \^core_control_regs[11]\(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(370), + Q => \^core_control_regs[11]\(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(371), + Q => \^core_control_regs[11]\(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(353), + Q => \^core_control_regs[11]\(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(372), + Q => \^core_control_regs[11]\(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(373), + Q => \^core_control_regs[11]\(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(374), + Q => \^core_control_regs[11]\(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(375), + Q => \^core_control_regs[11]\(23), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(376), + Q => \^core_control_regs[11]\(24), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(377), + Q => \^core_control_regs[11]\(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(378), + Q => \^core_control_regs[11]\(26), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(354), + Q => \^core_control_regs[11]\(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(355), + Q => \^core_control_regs[11]\(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(356), + Q => \^core_control_regs[11]\(4), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(357), + Q => \^core_control_regs[11]\(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(358), + Q => \^core_control_regs[11]\(6), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(359), + Q => \^core_control_regs[11]\(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(360), + Q => \^core_control_regs[11]\(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[11][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(361), + Q => \^core_control_regs[11]\(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => \core_control_regs2_int[12]\(0), + Q => \^core_control_regs[12]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(394), + Q => \^core_control_regs[12]\(10), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(395), + Q => \^core_control_regs[12]\(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(400), + Q => \^core_control_regs[12]\(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(401), + Q => \^core_control_regs[12]\(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(402), + Q => \^core_control_regs[12]\(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(403), + Q => \^core_control_regs[12]\(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(385), + Q => \^core_control_regs[12]\(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(404), + Q => \^core_control_regs[12]\(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(405), + Q => \^core_control_regs[12]\(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(406), + Q => \^core_control_regs[12]\(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(407), + Q => \^core_control_regs[12]\(23), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(408), + Q => \^core_control_regs[12]\(24), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(409), + Q => \^core_control_regs[12]\(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(410), + Q => \^core_control_regs[12]\(26), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(386), + Q => \^core_control_regs[12]\(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(387), + Q => \^core_control_regs[12]\(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(388), + Q => \^core_control_regs[12]\(4), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(389), + Q => \^core_control_regs[12]\(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(390), + Q => \^core_control_regs[12]\(6), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(391), + Q => \^core_control_regs[12]\(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(392), + Q => \^core_control_regs[12]\(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[12][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(393), + Q => \^core_control_regs[12]\(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => \core_control_regs2_int[13]\(0), + Q => \^core_control_regs[13]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(426), + Q => \^core_control_regs[13]\(10), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(427), + Q => \^core_control_regs[13]\(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(432), + Q => \^core_control_regs[13]\(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(433), + Q => \^core_control_regs[13]\(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(434), + Q => \^core_control_regs[13]\(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(435), + Q => \^core_control_regs[13]\(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(417), + Q => \^core_control_regs[13]\(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(436), + Q => \^core_control_regs[13]\(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(437), + Q => \^core_control_regs[13]\(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(438), + Q => \^core_control_regs[13]\(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(439), + Q => \^core_control_regs[13]\(23), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(440), + Q => \^core_control_regs[13]\(24), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(441), + Q => \^core_control_regs[13]\(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(442), + Q => \^core_control_regs[13]\(26), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(418), + Q => \^core_control_regs[13]\(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(419), + Q => \^core_control_regs[13]\(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(420), + Q => \^core_control_regs[13]\(4), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(421), + Q => \^core_control_regs[13]\(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(422), + Q => \^core_control_regs[13]\(6), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(423), + Q => \^core_control_regs[13]\(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(424), + Q => \^core_control_regs[13]\(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[13][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(425), + Q => \^core_control_regs[13]\(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => \core_control_regs2_int[14]\(0), + Q => \^core_control_regs[14]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(458), + Q => \^core_control_regs[14]\(10), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(459), + Q => \^core_control_regs[14]\(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(464), + Q => \^core_control_regs[14]\(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(465), + Q => \^core_control_regs[14]\(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(466), + Q => \^core_control_regs[14]\(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(467), + Q => \^core_control_regs[14]\(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(449), + Q => \^core_control_regs[14]\(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(468), + Q => \^core_control_regs[14]\(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(469), + Q => \^core_control_regs[14]\(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(470), + Q => \^core_control_regs[14]\(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(471), + Q => \^core_control_regs[14]\(23), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(472), + Q => \^core_control_regs[14]\(24), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(473), + Q => \^core_control_regs[14]\(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(474), + Q => \^core_control_regs[14]\(26), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(450), + Q => \^core_control_regs[14]\(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(451), + Q => \^core_control_regs[14]\(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(452), + Q => \^core_control_regs[14]\(4), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(453), + Q => \^core_control_regs[14]\(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(454), + Q => \^core_control_regs[14]\(6), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(455), + Q => \^core_control_regs[14]\(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(456), + Q => \^core_control_regs[14]\(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[14][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(457), + Q => \^core_control_regs[14]\(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => \core_control_regs2_int[15]\(0), + Q => \^core_control_regs[15]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(490), + Q => \^core_control_regs[15]\(10), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(491), + Q => \^core_control_regs[15]\(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(496), + Q => \^core_control_regs[15]\(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(497), + Q => \^core_control_regs[15]\(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(498), + Q => \^core_control_regs[15]\(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(499), + Q => \^core_control_regs[15]\(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(481), + Q => \^core_control_regs[15]\(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(500), + Q => \^core_control_regs[15]\(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(501), + Q => \^core_control_regs[15]\(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(502), + Q => \^core_control_regs[15]\(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(503), + Q => \^core_control_regs[15]\(23), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(504), + Q => \^core_control_regs[15]\(24), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(505), + Q => \^core_control_regs[15]\(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(506), + Q => \^core_control_regs[15]\(26), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(482), + Q => \^core_control_regs[15]\(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(483), + Q => \^core_control_regs[15]\(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(484), + Q => \^core_control_regs[15]\(4), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(485), + Q => \^core_control_regs[15]\(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(486), + Q => \^core_control_regs[15]\(6), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(487), + Q => \^core_control_regs[15]\(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(488), + Q => \^core_control_regs[15]\(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[15][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(489), + Q => \^core_control_regs[15]\(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => \core_control_regs2_int[1]\(0), + Q => \^core_control_regs[1]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(42), + Q => \^core_control_regs[1]\(10), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(43), + Q => \^core_control_regs[1]\(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(48), + Q => \^core_control_regs[1]\(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(49), + Q => \^core_control_regs[1]\(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(50), + Q => \^core_control_regs[1]\(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(51), + Q => \^core_control_regs[1]\(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(33), + Q => \^core_control_regs[1]\(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(52), + Q => \^core_control_regs[1]\(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(53), + Q => \^core_control_regs[1]\(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(54), + Q => \^core_control_regs[1]\(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(55), + Q => \^core_control_regs[1]\(23), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(56), + Q => \^core_control_regs[1]\(24), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(57), + Q => \^core_control_regs[1]\(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(58), + Q => \^core_control_regs[1]\(26), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(34), + Q => \^core_control_regs[1]\(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(35), + Q => \^core_control_regs[1]\(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(36), + Q => \^core_control_regs[1]\(4), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(37), + Q => \^core_control_regs[1]\(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(38), + Q => \^core_control_regs[1]\(6), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(39), + Q => \^core_control_regs[1]\(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(40), + Q => \^core_control_regs[1]\(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[1][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(41), + Q => \^core_control_regs[1]\(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => \core_control_regs2_int[2]\(0), + Q => \^core_control_regs[2]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(74), + Q => \^core_control_regs[2]\(10), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(75), + Q => \^core_control_regs[2]\(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(80), + Q => \^core_control_regs[2]\(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(81), + Q => \^core_control_regs[2]\(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(82), + Q => \^core_control_regs[2]\(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(83), + Q => \^core_control_regs[2]\(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(65), + Q => \^core_control_regs[2]\(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(84), + Q => \^core_control_regs[2]\(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(85), + Q => \^core_control_regs[2]\(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(86), + Q => \^core_control_regs[2]\(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(87), + Q => \^core_control_regs[2]\(23), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(88), + Q => \^core_control_regs[2]\(24), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(89), + Q => \^core_control_regs[2]\(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(90), + Q => \^core_control_regs[2]\(26), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(66), + Q => \^core_control_regs[2]\(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(67), + Q => \^core_control_regs[2]\(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(68), + Q => \^core_control_regs[2]\(4), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(69), + Q => \^core_control_regs[2]\(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(70), + Q => \^core_control_regs[2]\(6), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(71), + Q => \^core_control_regs[2]\(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(72), + Q => \^core_control_regs[2]\(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[2][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(73), + Q => \^core_control_regs[2]\(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => \core_control_regs2_int[3]\(0), + Q => \^core_control_regs[3]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(106), + Q => \^core_control_regs[3]\(10), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(107), + Q => \^core_control_regs[3]\(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(112), + Q => \^core_control_regs[3]\(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(113), + Q => \^core_control_regs[3]\(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(114), + Q => \^core_control_regs[3]\(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(115), + Q => \^core_control_regs[3]\(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(97), + Q => \^core_control_regs[3]\(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(116), + Q => \^core_control_regs[3]\(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(117), + Q => \^core_control_regs[3]\(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(118), + Q => \^core_control_regs[3]\(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(119), + Q => \^core_control_regs[3]\(23), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(120), + Q => \^core_control_regs[3]\(24), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(121), + Q => \^core_control_regs[3]\(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(122), + Q => \^core_control_regs[3]\(26), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(98), + Q => \^core_control_regs[3]\(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(99), + Q => \^core_control_regs[3]\(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(100), + Q => \^core_control_regs[3]\(4), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(101), + Q => \^core_control_regs[3]\(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(102), + Q => \^core_control_regs[3]\(6), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(103), + Q => \^core_control_regs[3]\(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(104), + Q => \^core_control_regs[3]\(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[3][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(105), + Q => \^core_control_regs[3]\(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => \core_control_regs2_int[4]\(0), + Q => \^core_control_regs[4]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(138), + Q => \^core_control_regs[4]\(10), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(139), + Q => \^core_control_regs[4]\(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(144), + Q => \^core_control_regs[4]\(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(145), + Q => \^core_control_regs[4]\(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(146), + Q => \^core_control_regs[4]\(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(147), + Q => \^core_control_regs[4]\(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(129), + Q => \^core_control_regs[4]\(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(148), + Q => \^core_control_regs[4]\(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(149), + Q => \^core_control_regs[4]\(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(150), + Q => \^core_control_regs[4]\(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(151), + Q => \^core_control_regs[4]\(23), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(152), + Q => \^core_control_regs[4]\(24), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(153), + Q => \^core_control_regs[4]\(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(154), + Q => \^core_control_regs[4]\(26), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(130), + Q => \^core_control_regs[4]\(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(131), + Q => \^core_control_regs[4]\(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(132), + Q => \^core_control_regs[4]\(4), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(133), + Q => \^core_control_regs[4]\(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(134), + Q => \^core_control_regs[4]\(6), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(135), + Q => \^core_control_regs[4]\(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(136), + Q => \^core_control_regs[4]\(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[4][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(137), + Q => \^core_control_regs[4]\(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => \core_control_regs2_int[5]\(0), + Q => \^core_control_regs[5]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(170), + Q => \^core_control_regs[5]\(10), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(171), + Q => \^core_control_regs[5]\(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(176), + Q => \^core_control_regs[5]\(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(177), + Q => \^core_control_regs[5]\(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(178), + Q => \^core_control_regs[5]\(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(179), + Q => \^core_control_regs[5]\(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(161), + Q => \^core_control_regs[5]\(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(180), + Q => \^core_control_regs[5]\(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(181), + Q => \^core_control_regs[5]\(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(182), + Q => \^core_control_regs[5]\(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(183), + Q => \^core_control_regs[5]\(23), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(184), + Q => \^core_control_regs[5]\(24), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(185), + Q => \^core_control_regs[5]\(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(186), + Q => \^core_control_regs[5]\(26), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(162), + Q => \^core_control_regs[5]\(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(163), + Q => \^core_control_regs[5]\(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(164), + Q => \^core_control_regs[5]\(4), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(165), + Q => \^core_control_regs[5]\(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(166), + Q => \^core_control_regs[5]\(6), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(167), + Q => \^core_control_regs[5]\(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(168), + Q => \^core_control_regs[5]\(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[5][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(169), + Q => \^core_control_regs[5]\(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => \core_control_regs2_int[6]\(0), + Q => \^core_control_regs[6]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(202), + Q => \^core_control_regs[6]\(10), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(203), + Q => \^core_control_regs[6]\(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(208), + Q => \^core_control_regs[6]\(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(209), + Q => \^core_control_regs[6]\(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(210), + Q => \^core_control_regs[6]\(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(211), + Q => \^core_control_regs[6]\(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(193), + Q => \^core_control_regs[6]\(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(212), + Q => \^core_control_regs[6]\(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(213), + Q => \^core_control_regs[6]\(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(214), + Q => \^core_control_regs[6]\(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(215), + Q => \^core_control_regs[6]\(23), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(216), + Q => \^core_control_regs[6]\(24), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(217), + Q => \^core_control_regs[6]\(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(218), + Q => \^core_control_regs[6]\(26), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(194), + Q => \^core_control_regs[6]\(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(195), + Q => \^core_control_regs[6]\(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(196), + Q => \^core_control_regs[6]\(4), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(197), + Q => \^core_control_regs[6]\(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(198), + Q => \^core_control_regs[6]\(6), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(199), + Q => \^core_control_regs[6]\(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(200), + Q => \^core_control_regs[6]\(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[6][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(201), + Q => \^core_control_regs[6]\(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => \core_control_regs2_int[7]\(0), + Q => \^core_control_regs[7]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(234), + Q => \^core_control_regs[7]\(10), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(235), + Q => \^core_control_regs[7]\(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(240), + Q => \^core_control_regs[7]\(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(241), + Q => \^core_control_regs[7]\(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(242), + Q => \^core_control_regs[7]\(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(243), + Q => \^core_control_regs[7]\(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(225), + Q => \^core_control_regs[7]\(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(244), + Q => \^core_control_regs[7]\(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(245), + Q => \^core_control_regs[7]\(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(246), + Q => \^core_control_regs[7]\(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(247), + Q => \^core_control_regs[7]\(23), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(248), + Q => \^core_control_regs[7]\(24), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(249), + Q => \^core_control_regs[7]\(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(250), + Q => \^core_control_regs[7]\(26), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(226), + Q => \^core_control_regs[7]\(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(227), + Q => \^core_control_regs[7]\(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(228), + Q => \^core_control_regs[7]\(4), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(229), + Q => \^core_control_regs[7]\(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(230), + Q => \^core_control_regs[7]\(6), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(231), + Q => \^core_control_regs[7]\(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(232), + Q => \^core_control_regs[7]\(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[7][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(233), + Q => \^core_control_regs[7]\(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => \core_control_regs2_int[8]\(0), + Q => \^core_control_regs[8]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(266), + Q => \^core_control_regs[8]\(10), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(267), + Q => \^core_control_regs[8]\(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(272), + Q => \^core_control_regs[8]\(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(273), + Q => \^core_control_regs[8]\(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(274), + Q => \^core_control_regs[8]\(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(275), + Q => \^core_control_regs[8]\(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(257), + Q => \^core_control_regs[8]\(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(276), + Q => \^core_control_regs[8]\(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(277), + Q => \^core_control_regs[8]\(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(278), + Q => \^core_control_regs[8]\(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(279), + Q => \^core_control_regs[8]\(23), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(280), + Q => \^core_control_regs[8]\(24), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(281), + Q => \^core_control_regs[8]\(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(282), + Q => \^core_control_regs[8]\(26), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(258), + Q => \^core_control_regs[8]\(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(259), + Q => \^core_control_regs[8]\(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(260), + Q => \^core_control_regs[8]\(4), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(261), + Q => \^core_control_regs[8]\(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(262), + Q => \^core_control_regs[8]\(6), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(263), + Q => \^core_control_regs[8]\(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(264), + Q => \^core_control_regs[8]\(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[8][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(265), + Q => \^core_control_regs[8]\(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => \core_control_regs2_int[9]\(0), + Q => \^core_control_regs[9]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(298), + Q => \^core_control_regs[9]\(10), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(299), + Q => \^core_control_regs[9]\(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(304), + Q => \^core_control_regs[9]\(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(305), + Q => \^core_control_regs[9]\(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(306), + Q => \^core_control_regs[9]\(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(307), + Q => \^core_control_regs[9]\(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(289), + Q => \^core_control_regs[9]\(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(308), + Q => \^core_control_regs[9]\(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(309), + Q => \^core_control_regs[9]\(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(310), + Q => \^core_control_regs[9]\(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(311), + Q => \^core_control_regs[9]\(23), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(312), + Q => \^core_control_regs[9]\(24), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(313), + Q => \^core_control_regs[9]\(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(314), + Q => \^core_control_regs[9]\(26), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(290), + Q => \^core_control_regs[9]\(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(291), + Q => \^core_control_regs[9]\(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(292), + Q => \^core_control_regs[9]\(4), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(293), + Q => \^core_control_regs[9]\(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(294), + Q => \^core_control_regs[9]\(6), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(295), + Q => \^core_control_regs[9]\(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(296), + Q => \^core_control_regs[9]\(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs2_int_reg[9][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => core_regs(297), + Q => \^core_control_regs[9]\(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[0]\(26), + D => \^ipif_data_out\(0), + Q => \core_control_regs2_int[0]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[0]\(26), + D => \^ipif_data_out\(10), + Q => core_regs(10), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[0]\(26), + D => \^ipif_data_out\(11), + Q => core_regs(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[0]\(26), + D => \^ipif_data_out\(16), + Q => core_regs(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[0]\(26), + D => \^ipif_data_out\(17), + Q => core_regs(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[0]\(26), + D => \^ipif_data_out\(18), + Q => core_regs(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[0]\(26), + D => \^ipif_data_out\(19), + Q => core_regs(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[0]\(26), + D => \^ipif_data_out\(1), + Q => core_regs(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[0]\(26), + D => \^ipif_data_out\(20), + Q => core_regs(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[0]\(26), + D => \^ipif_data_out\(21), + Q => core_regs(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[0]\(26), + D => \^ipif_data_out\(22), + Q => core_regs(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[0]\(26), + D => \^ipif_data_out\(23), + Q => core_regs(23), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[0]\(26), + D => \^ipif_data_out\(24), + Q => core_regs(24), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[0]\(26), + D => \^ipif_data_out\(25), + Q => core_regs(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[0]\(26), + D => \^ipif_data_out\(26), + Q => core_regs(26), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[0]\(26), + D => \^ipif_data_out\(2), + Q => core_regs(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[0]\(26), + D => \^ipif_data_out\(3), + Q => core_regs(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[0]\(26), + D => \^ipif_data_out\(4), + Q => core_regs(4), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[0]\(26), + D => \^ipif_data_out\(5), + Q => core_regs(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[0]\(26), + D => \^ipif_data_out\(6), + Q => core_regs(6), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[0]\(26), + D => \^ipif_data_out\(7), + Q => core_regs(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[0]\(26), + D => \^ipif_data_out\(8), + Q => core_regs(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[0][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[0]\(26), + D => \^ipif_data_out\(9), + Q => core_regs(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[10]\(26), + D => \^ipif_data_out\(0), + Q => \core_control_regs2_int[10]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[10]\(26), + D => \^ipif_data_out\(10), + Q => core_regs(330), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[10]\(26), + D => \^ipif_data_out\(11), + Q => core_regs(331), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[10]\(26), + D => \^ipif_data_out\(16), + Q => core_regs(336), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[10]\(26), + D => \^ipif_data_out\(17), + Q => core_regs(337), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[10]\(26), + D => \^ipif_data_out\(18), + Q => core_regs(338), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[10]\(26), + D => \^ipif_data_out\(19), + Q => core_regs(339), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[10]\(26), + D => \^ipif_data_out\(1), + Q => core_regs(321), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[10]\(26), + D => \^ipif_data_out\(20), + Q => core_regs(340), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[10]\(26), + D => \^ipif_data_out\(21), + Q => core_regs(341), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[10]\(26), + D => \^ipif_data_out\(22), + Q => core_regs(342), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[10]\(26), + D => \^ipif_data_out\(23), + Q => core_regs(343), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[10]\(26), + D => \^ipif_data_out\(24), + Q => core_regs(344), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[10]\(26), + D => \^ipif_data_out\(25), + Q => core_regs(345), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[10]\(26), + D => \^ipif_data_out\(26), + Q => core_regs(346), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[10]\(26), + D => \^ipif_data_out\(2), + Q => core_regs(322), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[10]\(26), + D => \^ipif_data_out\(3), + Q => core_regs(323), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[10]\(26), + D => \^ipif_data_out\(4), + Q => core_regs(324), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[10]\(26), + D => \^ipif_data_out\(5), + Q => core_regs(325), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[10]\(26), + D => \^ipif_data_out\(6), + Q => core_regs(326), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[10]\(26), + D => \^ipif_data_out\(7), + Q => core_regs(327), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[10]\(26), + D => \^ipif_data_out\(8), + Q => core_regs(328), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[10][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[10]\(26), + D => \^ipif_data_out\(9), + Q => core_regs(329), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[11]\(26), + D => \^ipif_data_out\(0), + Q => \core_control_regs2_int[11]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[11]\(26), + D => \^ipif_data_out\(10), + Q => core_regs(362), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[11]\(26), + D => \^ipif_data_out\(11), + Q => core_regs(363), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[11]\(26), + D => \^ipif_data_out\(16), + Q => core_regs(368), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[11]\(26), + D => \^ipif_data_out\(17), + Q => core_regs(369), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[11]\(26), + D => \^ipif_data_out\(18), + Q => core_regs(370), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[11]\(26), + D => \^ipif_data_out\(19), + Q => core_regs(371), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[11]\(26), + D => \^ipif_data_out\(1), + Q => core_regs(353), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[11]\(26), + D => \^ipif_data_out\(20), + Q => core_regs(372), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[11]\(26), + D => \^ipif_data_out\(21), + Q => core_regs(373), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[11]\(26), + D => \^ipif_data_out\(22), + Q => core_regs(374), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[11]\(26), + D => \^ipif_data_out\(23), + Q => core_regs(375), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[11]\(26), + D => \^ipif_data_out\(24), + Q => core_regs(376), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[11]\(26), + D => \^ipif_data_out\(25), + Q => core_regs(377), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[11]\(26), + D => \^ipif_data_out\(26), + Q => core_regs(378), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[11]\(26), + D => \^ipif_data_out\(2), + Q => core_regs(354), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[11]\(26), + D => \^ipif_data_out\(3), + Q => core_regs(355), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[11]\(26), + D => \^ipif_data_out\(4), + Q => core_regs(356), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[11]\(26), + D => \^ipif_data_out\(5), + Q => core_regs(357), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[11]\(26), + D => \^ipif_data_out\(6), + Q => core_regs(358), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[11]\(26), + D => \^ipif_data_out\(7), + Q => core_regs(359), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[11]\(26), + D => \^ipif_data_out\(8), + Q => core_regs(360), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[11][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[11]\(26), + D => \^ipif_data_out\(9), + Q => core_regs(361), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[12]\(26), + D => \^ipif_data_out\(0), + Q => \core_control_regs2_int[12]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[12]\(26), + D => \^ipif_data_out\(10), + Q => core_regs(394), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[12]\(26), + D => \^ipif_data_out\(11), + Q => core_regs(395), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[12]\(26), + D => \^ipif_data_out\(16), + Q => core_regs(400), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[12]\(26), + D => \^ipif_data_out\(17), + Q => core_regs(401), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[12]\(26), + D => \^ipif_data_out\(18), + Q => core_regs(402), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[12]\(26), + D => \^ipif_data_out\(19), + Q => core_regs(403), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[12]\(26), + D => \^ipif_data_out\(1), + Q => core_regs(385), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[12]\(26), + D => \^ipif_data_out\(20), + Q => core_regs(404), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[12]\(26), + D => \^ipif_data_out\(21), + Q => core_regs(405), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[12]\(26), + D => \^ipif_data_out\(22), + Q => core_regs(406), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[12]\(26), + D => \^ipif_data_out\(23), + Q => core_regs(407), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[12]\(26), + D => \^ipif_data_out\(24), + Q => core_regs(408), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[12]\(26), + D => \^ipif_data_out\(25), + Q => core_regs(409), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[12]\(26), + D => \^ipif_data_out\(26), + Q => core_regs(410), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[12]\(26), + D => \^ipif_data_out\(2), + Q => core_regs(386), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[12]\(26), + D => \^ipif_data_out\(3), + Q => core_regs(387), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[12]\(26), + D => \^ipif_data_out\(4), + Q => core_regs(388), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[12]\(26), + D => \^ipif_data_out\(5), + Q => core_regs(389), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[12]\(26), + D => \^ipif_data_out\(6), + Q => core_regs(390), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[12]\(26), + D => \^ipif_data_out\(7), + Q => core_regs(391), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[12]\(26), + D => \^ipif_data_out\(8), + Q => core_regs(392), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[12][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[12]\(26), + D => \^ipif_data_out\(9), + Q => core_regs(393), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[13]\(26), + D => \^ipif_data_out\(0), + Q => \core_control_regs2_int[13]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[13]\(26), + D => \^ipif_data_out\(10), + Q => core_regs(426), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[13]\(26), + D => \^ipif_data_out\(11), + Q => core_regs(427), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[13]\(26), + D => \^ipif_data_out\(16), + Q => core_regs(432), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[13]\(26), + D => \^ipif_data_out\(17), + Q => core_regs(433), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[13]\(26), + D => \^ipif_data_out\(18), + Q => core_regs(434), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[13]\(26), + D => \^ipif_data_out\(19), + Q => core_regs(435), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[13]\(26), + D => \^ipif_data_out\(1), + Q => core_regs(417), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[13]\(26), + D => \^ipif_data_out\(20), + Q => core_regs(436), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[13]\(26), + D => \^ipif_data_out\(21), + Q => core_regs(437), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[13]\(26), + D => \^ipif_data_out\(22), + Q => core_regs(438), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[13]\(26), + D => \^ipif_data_out\(23), + Q => core_regs(439), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[13]\(26), + D => \^ipif_data_out\(24), + Q => core_regs(440), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[13]\(26), + D => \^ipif_data_out\(25), + Q => core_regs(441), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[13]\(26), + D => \^ipif_data_out\(26), + Q => core_regs(442), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[13]\(26), + D => \^ipif_data_out\(2), + Q => core_regs(418), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[13]\(26), + D => \^ipif_data_out\(3), + Q => core_regs(419), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[13]\(26), + D => \^ipif_data_out\(4), + Q => core_regs(420), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[13]\(26), + D => \^ipif_data_out\(5), + Q => core_regs(421), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[13]\(26), + D => \^ipif_data_out\(6), + Q => core_regs(422), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[13]\(26), + D => \^ipif_data_out\(7), + Q => core_regs(423), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[13]\(26), + D => \^ipif_data_out\(8), + Q => core_regs(424), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[13][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[13]\(26), + D => \^ipif_data_out\(9), + Q => core_regs(425), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[14]\(26), + D => \^ipif_data_out\(0), + Q => \core_control_regs2_int[14]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[14]\(26), + D => \^ipif_data_out\(10), + Q => core_regs(458), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[14]\(26), + D => \^ipif_data_out\(11), + Q => core_regs(459), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[14]\(26), + D => \^ipif_data_out\(16), + Q => core_regs(464), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[14]\(26), + D => \^ipif_data_out\(17), + Q => core_regs(465), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[14]\(26), + D => \^ipif_data_out\(18), + Q => core_regs(466), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[14]\(26), + D => \^ipif_data_out\(19), + Q => core_regs(467), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[14]\(26), + D => \^ipif_data_out\(1), + Q => core_regs(449), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[14]\(26), + D => \^ipif_data_out\(20), + Q => core_regs(468), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[14]\(26), + D => \^ipif_data_out\(21), + Q => core_regs(469), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[14]\(26), + D => \^ipif_data_out\(22), + Q => core_regs(470), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[14]\(26), + D => \^ipif_data_out\(23), + Q => core_regs(471), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[14]\(26), + D => \^ipif_data_out\(24), + Q => core_regs(472), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[14]\(26), + D => \^ipif_data_out\(25), + Q => core_regs(473), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[14]\(26), + D => \^ipif_data_out\(26), + Q => core_regs(474), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[14]\(26), + D => \^ipif_data_out\(2), + Q => core_regs(450), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[14]\(26), + D => \^ipif_data_out\(3), + Q => core_regs(451), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[14]\(26), + D => \^ipif_data_out\(4), + Q => core_regs(452), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[14]\(26), + D => \^ipif_data_out\(5), + Q => core_regs(453), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[14]\(26), + D => \^ipif_data_out\(6), + Q => core_regs(454), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[14]\(26), + D => \^ipif_data_out\(7), + Q => core_regs(455), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[14]\(26), + D => \^ipif_data_out\(8), + Q => core_regs(456), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[14][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[14]\(26), + D => \^ipif_data_out\(9), + Q => core_regs(457), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[15]\(26), + D => \^ipif_data_out\(0), + Q => \core_control_regs2_int[15]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[15]\(26), + D => \^ipif_data_out\(10), + Q => core_regs(490), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[15]\(26), + D => \^ipif_data_out\(11), + Q => core_regs(491), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[15]\(26), + D => \^ipif_data_out\(16), + Q => core_regs(496), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[15]\(26), + D => \^ipif_data_out\(17), + Q => core_regs(497), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[15]\(26), + D => \^ipif_data_out\(18), + Q => core_regs(498), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[15]\(26), + D => \^ipif_data_out\(19), + Q => core_regs(499), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[15]\(26), + D => \^ipif_data_out\(1), + Q => core_regs(481), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[15]\(26), + D => \^ipif_data_out\(20), + Q => core_regs(500), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[15]\(26), + D => \^ipif_data_out\(21), + Q => core_regs(501), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[15]\(26), + D => \^ipif_data_out\(22), + Q => core_regs(502), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[15]\(26), + D => \^ipif_data_out\(23), + Q => core_regs(503), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[15]\(26), + D => \^ipif_data_out\(24), + Q => core_regs(504), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[15]\(26), + D => \^ipif_data_out\(25), + Q => core_regs(505), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[15]\(26), + D => \^ipif_data_out\(26), + Q => core_regs(506), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[15]\(26), + D => \^ipif_data_out\(2), + Q => core_regs(482), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[15]\(26), + D => \^ipif_data_out\(3), + Q => core_regs(483), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[15]\(26), + D => \^ipif_data_out\(4), + Q => core_regs(484), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[15]\(26), + D => \^ipif_data_out\(5), + Q => core_regs(485), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[15]\(26), + D => \^ipif_data_out\(6), + Q => core_regs(486), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[15]\(26), + D => \^ipif_data_out\(7), + Q => core_regs(487), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[15]\(26), + D => \^ipif_data_out\(8), + Q => core_regs(488), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[15][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[15]\(26), + D => \^ipif_data_out\(9), + Q => core_regs(489), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[16]\(26), + D => \^ipif_data_out\(0), + Q => \^core_control_regs[16]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[16]\(26), + D => \^ipif_data_out\(10), + Q => \^core_control_regs[16]\(10), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[16]\(26), + D => \^ipif_data_out\(11), + Q => \^core_control_regs[16]\(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[16]\(26), + D => \^ipif_data_out\(16), + Q => \^core_control_regs[16]\(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[16]\(26), + D => \^ipif_data_out\(17), + Q => \^core_control_regs[16]\(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[16]\(26), + D => \^ipif_data_out\(18), + Q => \^core_control_regs[16]\(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[16]\(26), + D => \^ipif_data_out\(19), + Q => \^core_control_regs[16]\(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[16]\(26), + D => \^ipif_data_out\(1), + Q => \^core_control_regs[16]\(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[16]\(26), + D => \^ipif_data_out\(20), + Q => \^core_control_regs[16]\(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[16]\(26), + D => \^ipif_data_out\(21), + Q => \^core_control_regs[16]\(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[16]\(26), + D => \^ipif_data_out\(22), + Q => \^core_control_regs[16]\(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[16]\(26), + D => \^ipif_data_out\(23), + Q => \^core_control_regs[16]\(23), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[16]\(26), + D => \^ipif_data_out\(24), + Q => \^core_control_regs[16]\(24), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[16]\(26), + D => \^ipif_data_out\(25), + Q => \^core_control_regs[16]\(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[16]\(26), + D => \^ipif_data_out\(26), + Q => \^core_control_regs[16]\(26), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[16]\(26), + D => \^ipif_data_out\(2), + Q => \^core_control_regs[16]\(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[16]\(26), + D => \^ipif_data_out\(3), + Q => \^core_control_regs[16]\(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[16]\(26), + D => \^ipif_data_out\(4), + Q => \^core_control_regs[16]\(4), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[16]\(26), + D => \^ipif_data_out\(5), + Q => \^core_control_regs[16]\(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[16]\(26), + D => \^ipif_data_out\(6), + Q => \^core_control_regs[16]\(6), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[16]\(26), + D => \^ipif_data_out\(7), + Q => \^core_control_regs[16]\(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[16]\(26), + D => \^ipif_data_out\(8), + Q => \^core_control_regs[16]\(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[16][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[16]\(26), + D => \^ipif_data_out\(9), + Q => \^core_control_regs[16]\(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[1]\(26), + D => \^ipif_data_out\(0), + Q => \core_control_regs2_int[1]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[1]\(26), + D => \^ipif_data_out\(10), + Q => core_regs(42), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[1]\(26), + D => \^ipif_data_out\(11), + Q => core_regs(43), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[1]\(26), + D => \^ipif_data_out\(16), + Q => core_regs(48), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[1]\(26), + D => \^ipif_data_out\(17), + Q => core_regs(49), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[1]\(26), + D => \^ipif_data_out\(18), + Q => core_regs(50), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[1]\(26), + D => \^ipif_data_out\(19), + Q => core_regs(51), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[1]\(26), + D => \^ipif_data_out\(1), + Q => core_regs(33), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[1]\(26), + D => \^ipif_data_out\(20), + Q => core_regs(52), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[1]\(26), + D => \^ipif_data_out\(21), + Q => core_regs(53), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[1]\(26), + D => \^ipif_data_out\(22), + Q => core_regs(54), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[1]\(26), + D => \^ipif_data_out\(23), + Q => core_regs(55), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[1]\(26), + D => \^ipif_data_out\(24), + Q => core_regs(56), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[1]\(26), + D => \^ipif_data_out\(25), + Q => core_regs(57), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[1]\(26), + D => \^ipif_data_out\(26), + Q => core_regs(58), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[1]\(26), + D => \^ipif_data_out\(2), + Q => core_regs(34), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[1]\(26), + D => \^ipif_data_out\(3), + Q => core_regs(35), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[1]\(26), + D => \^ipif_data_out\(4), + Q => core_regs(36), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[1]\(26), + D => \^ipif_data_out\(5), + Q => core_regs(37), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[1]\(26), + D => \^ipif_data_out\(6), + Q => core_regs(38), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[1]\(26), + D => \^ipif_data_out\(7), + Q => core_regs(39), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[1]\(26), + D => \^ipif_data_out\(8), + Q => core_regs(40), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[1][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[1]\(26), + D => \^ipif_data_out\(9), + Q => core_regs(41), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[2]\(26), + D => \^ipif_data_out\(0), + Q => \core_control_regs2_int[2]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[2]\(26), + D => \^ipif_data_out\(10), + Q => core_regs(74), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[2]\(26), + D => \^ipif_data_out\(11), + Q => core_regs(75), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[2]\(26), + D => \^ipif_data_out\(16), + Q => core_regs(80), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[2]\(26), + D => \^ipif_data_out\(17), + Q => core_regs(81), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[2]\(26), + D => \^ipif_data_out\(18), + Q => core_regs(82), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[2]\(26), + D => \^ipif_data_out\(19), + Q => core_regs(83), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[2]\(26), + D => \^ipif_data_out\(1), + Q => core_regs(65), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[2]\(26), + D => \^ipif_data_out\(20), + Q => core_regs(84), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[2]\(26), + D => \^ipif_data_out\(21), + Q => core_regs(85), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[2]\(26), + D => \^ipif_data_out\(22), + Q => core_regs(86), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[2]\(26), + D => \^ipif_data_out\(23), + Q => core_regs(87), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[2]\(26), + D => \^ipif_data_out\(24), + Q => core_regs(88), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[2]\(26), + D => \^ipif_data_out\(25), + Q => core_regs(89), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[2]\(26), + D => \^ipif_data_out\(26), + Q => core_regs(90), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[2]\(26), + D => \^ipif_data_out\(2), + Q => core_regs(66), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[2]\(26), + D => \^ipif_data_out\(3), + Q => core_regs(67), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[2]\(26), + D => \^ipif_data_out\(4), + Q => core_regs(68), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[2]\(26), + D => \^ipif_data_out\(5), + Q => core_regs(69), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[2]\(26), + D => \^ipif_data_out\(6), + Q => core_regs(70), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[2]\(26), + D => \^ipif_data_out\(7), + Q => core_regs(71), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[2]\(26), + D => \^ipif_data_out\(8), + Q => core_regs(72), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[2][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[2]\(26), + D => \^ipif_data_out\(9), + Q => core_regs(73), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[3]\(26), + D => \^ipif_data_out\(0), + Q => \core_control_regs2_int[3]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[3]\(26), + D => \^ipif_data_out\(10), + Q => core_regs(106), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[3]\(26), + D => \^ipif_data_out\(11), + Q => core_regs(107), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[3]\(26), + D => \^ipif_data_out\(16), + Q => core_regs(112), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[3]\(26), + D => \^ipif_data_out\(17), + Q => core_regs(113), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[3]\(26), + D => \^ipif_data_out\(18), + Q => core_regs(114), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[3]\(26), + D => \^ipif_data_out\(19), + Q => core_regs(115), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[3]\(26), + D => \^ipif_data_out\(1), + Q => core_regs(97), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[3]\(26), + D => \^ipif_data_out\(20), + Q => core_regs(116), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[3]\(26), + D => \^ipif_data_out\(21), + Q => core_regs(117), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[3]\(26), + D => \^ipif_data_out\(22), + Q => core_regs(118), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[3]\(26), + D => \^ipif_data_out\(23), + Q => core_regs(119), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[3]\(26), + D => \^ipif_data_out\(24), + Q => core_regs(120), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[3]\(26), + D => \^ipif_data_out\(25), + Q => core_regs(121), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[3]\(26), + D => \^ipif_data_out\(26), + Q => core_regs(122), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[3]\(26), + D => \^ipif_data_out\(2), + Q => core_regs(98), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[3]\(26), + D => \^ipif_data_out\(3), + Q => core_regs(99), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[3]\(26), + D => \^ipif_data_out\(4), + Q => core_regs(100), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[3]\(26), + D => \^ipif_data_out\(5), + Q => core_regs(101), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[3]\(26), + D => \^ipif_data_out\(6), + Q => core_regs(102), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[3]\(26), + D => \^ipif_data_out\(7), + Q => core_regs(103), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[3]\(26), + D => \^ipif_data_out\(8), + Q => core_regs(104), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[3][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[3]\(26), + D => \^ipif_data_out\(9), + Q => core_regs(105), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[4]\(26), + D => \^ipif_data_out\(0), + Q => \core_control_regs2_int[4]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[4]\(26), + D => \^ipif_data_out\(10), + Q => core_regs(138), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[4]\(26), + D => \^ipif_data_out\(11), + Q => core_regs(139), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[4]\(26), + D => \^ipif_data_out\(16), + Q => core_regs(144), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[4]\(26), + D => \^ipif_data_out\(17), + Q => core_regs(145), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[4]\(26), + D => \^ipif_data_out\(18), + Q => core_regs(146), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[4]\(26), + D => \^ipif_data_out\(19), + Q => core_regs(147), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[4]\(26), + D => \^ipif_data_out\(1), + Q => core_regs(129), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[4]\(26), + D => \^ipif_data_out\(20), + Q => core_regs(148), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[4]\(26), + D => \^ipif_data_out\(21), + Q => core_regs(149), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[4]\(26), + D => \^ipif_data_out\(22), + Q => core_regs(150), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[4]\(26), + D => \^ipif_data_out\(23), + Q => core_regs(151), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[4]\(26), + D => \^ipif_data_out\(24), + Q => core_regs(152), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[4]\(26), + D => \^ipif_data_out\(25), + Q => core_regs(153), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[4]\(26), + D => \^ipif_data_out\(26), + Q => core_regs(154), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[4]\(26), + D => \^ipif_data_out\(2), + Q => core_regs(130), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[4]\(26), + D => \^ipif_data_out\(3), + Q => core_regs(131), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[4]\(26), + D => \^ipif_data_out\(4), + Q => core_regs(132), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[4]\(26), + D => \^ipif_data_out\(5), + Q => core_regs(133), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[4]\(26), + D => \^ipif_data_out\(6), + Q => core_regs(134), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[4]\(26), + D => \^ipif_data_out\(7), + Q => core_regs(135), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[4]\(26), + D => \^ipif_data_out\(8), + Q => core_regs(136), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[4][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[4]\(26), + D => \^ipif_data_out\(9), + Q => core_regs(137), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[5]\(26), + D => \^ipif_data_out\(0), + Q => \core_control_regs2_int[5]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[5]\(26), + D => \^ipif_data_out\(10), + Q => core_regs(170), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[5]\(26), + D => \^ipif_data_out\(11), + Q => core_regs(171), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[5]\(26), + D => \^ipif_data_out\(16), + Q => core_regs(176), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[5]\(26), + D => \^ipif_data_out\(17), + Q => core_regs(177), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[5]\(26), + D => \^ipif_data_out\(18), + Q => core_regs(178), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[5]\(26), + D => \^ipif_data_out\(19), + Q => core_regs(179), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[5]\(26), + D => \^ipif_data_out\(1), + Q => core_regs(161), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[5]\(26), + D => \^ipif_data_out\(20), + Q => core_regs(180), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[5]\(26), + D => \^ipif_data_out\(21), + Q => core_regs(181), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[5]\(26), + D => \^ipif_data_out\(22), + Q => core_regs(182), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[5]\(26), + D => \^ipif_data_out\(23), + Q => core_regs(183), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[5]\(26), + D => \^ipif_data_out\(24), + Q => core_regs(184), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[5]\(26), + D => \^ipif_data_out\(25), + Q => core_regs(185), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[5]\(26), + D => \^ipif_data_out\(26), + Q => core_regs(186), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[5]\(26), + D => \^ipif_data_out\(2), + Q => core_regs(162), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[5]\(26), + D => \^ipif_data_out\(3), + Q => core_regs(163), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[5]\(26), + D => \^ipif_data_out\(4), + Q => core_regs(164), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[5]\(26), + D => \^ipif_data_out\(5), + Q => core_regs(165), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[5]\(26), + D => \^ipif_data_out\(6), + Q => core_regs(166), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[5]\(26), + D => \^ipif_data_out\(7), + Q => core_regs(167), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[5]\(26), + D => \^ipif_data_out\(8), + Q => core_regs(168), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[5][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[5]\(26), + D => \^ipif_data_out\(9), + Q => core_regs(169), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[6]\(26), + D => \^ipif_data_out\(0), + Q => \core_control_regs2_int[6]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[6]\(26), + D => \^ipif_data_out\(10), + Q => core_regs(202), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[6]\(26), + D => \^ipif_data_out\(11), + Q => core_regs(203), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[6]\(26), + D => \^ipif_data_out\(16), + Q => core_regs(208), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[6]\(26), + D => \^ipif_data_out\(17), + Q => core_regs(209), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[6]\(26), + D => \^ipif_data_out\(18), + Q => core_regs(210), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[6]\(26), + D => \^ipif_data_out\(19), + Q => core_regs(211), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[6]\(26), + D => \^ipif_data_out\(1), + Q => core_regs(193), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[6]\(26), + D => \^ipif_data_out\(20), + Q => core_regs(212), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[6]\(26), + D => \^ipif_data_out\(21), + Q => core_regs(213), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[6]\(26), + D => \^ipif_data_out\(22), + Q => core_regs(214), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[6]\(26), + D => \^ipif_data_out\(23), + Q => core_regs(215), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[6]\(26), + D => \^ipif_data_out\(24), + Q => core_regs(216), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[6]\(26), + D => \^ipif_data_out\(25), + Q => core_regs(217), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[6]\(26), + D => \^ipif_data_out\(26), + Q => core_regs(218), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[6]\(26), + D => \^ipif_data_out\(2), + Q => core_regs(194), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[6]\(26), + D => \^ipif_data_out\(3), + Q => core_regs(195), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[6]\(26), + D => \^ipif_data_out\(4), + Q => core_regs(196), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[6]\(26), + D => \^ipif_data_out\(5), + Q => core_regs(197), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[6]\(26), + D => \^ipif_data_out\(6), + Q => core_regs(198), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[6]\(26), + D => \^ipif_data_out\(7), + Q => core_regs(199), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[6]\(26), + D => \^ipif_data_out\(8), + Q => core_regs(200), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[6][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[6]\(26), + D => \^ipif_data_out\(9), + Q => core_regs(201), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[7]\(26), + D => \^ipif_data_out\(0), + Q => \core_control_regs2_int[7]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[7]\(26), + D => \^ipif_data_out\(10), + Q => core_regs(234), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[7]\(26), + D => \^ipif_data_out\(11), + Q => core_regs(235), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[7]\(26), + D => \^ipif_data_out\(16), + Q => core_regs(240), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[7]\(26), + D => \^ipif_data_out\(17), + Q => core_regs(241), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[7]\(26), + D => \^ipif_data_out\(18), + Q => core_regs(242), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[7]\(26), + D => \^ipif_data_out\(19), + Q => core_regs(243), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[7]\(26), + D => \^ipif_data_out\(1), + Q => core_regs(225), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[7]\(26), + D => \^ipif_data_out\(20), + Q => core_regs(244), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[7]\(26), + D => \^ipif_data_out\(21), + Q => core_regs(245), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[7]\(26), + D => \^ipif_data_out\(22), + Q => core_regs(246), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[7]\(26), + D => \^ipif_data_out\(23), + Q => core_regs(247), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[7]\(26), + D => \^ipif_data_out\(24), + Q => core_regs(248), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[7]\(26), + D => \^ipif_data_out\(25), + Q => core_regs(249), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[7]\(26), + D => \^ipif_data_out\(26), + Q => core_regs(250), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[7]\(26), + D => \^ipif_data_out\(2), + Q => core_regs(226), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[7]\(26), + D => \^ipif_data_out\(3), + Q => core_regs(227), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[7]\(26), + D => \^ipif_data_out\(4), + Q => core_regs(228), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[7]\(26), + D => \^ipif_data_out\(5), + Q => core_regs(229), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[7]\(26), + D => \^ipif_data_out\(6), + Q => core_regs(230), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[7]\(26), + D => \^ipif_data_out\(7), + Q => core_regs(231), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[7]\(26), + D => \^ipif_data_out\(8), + Q => core_regs(232), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[7][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[7]\(26), + D => \^ipif_data_out\(9), + Q => core_regs(233), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[8]\(26), + D => \^ipif_data_out\(0), + Q => \core_control_regs2_int[8]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[8]\(26), + D => \^ipif_data_out\(10), + Q => core_regs(266), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[8]\(26), + D => \^ipif_data_out\(11), + Q => core_regs(267), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[8]\(26), + D => \^ipif_data_out\(16), + Q => core_regs(272), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[8]\(26), + D => \^ipif_data_out\(17), + Q => core_regs(273), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[8]\(26), + D => \^ipif_data_out\(18), + Q => core_regs(274), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[8]\(26), + D => \^ipif_data_out\(19), + Q => core_regs(275), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[8]\(26), + D => \^ipif_data_out\(1), + Q => core_regs(257), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[8]\(26), + D => \^ipif_data_out\(20), + Q => core_regs(276), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[8]\(26), + D => \^ipif_data_out\(21), + Q => core_regs(277), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[8]\(26), + D => \^ipif_data_out\(22), + Q => core_regs(278), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[8]\(26), + D => \^ipif_data_out\(23), + Q => core_regs(279), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[8]\(26), + D => \^ipif_data_out\(24), + Q => core_regs(280), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[8]\(26), + D => \^ipif_data_out\(25), + Q => core_regs(281), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[8]\(26), + D => \^ipif_data_out\(26), + Q => core_regs(282), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[8]\(26), + D => \^ipif_data_out\(2), + Q => core_regs(258), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[8]\(26), + D => \^ipif_data_out\(3), + Q => core_regs(259), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[8]\(26), + D => \^ipif_data_out\(4), + Q => core_regs(260), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[8]\(26), + D => \^ipif_data_out\(5), + Q => core_regs(261), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[8]\(26), + D => \^ipif_data_out\(6), + Q => core_regs(262), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[8]\(26), + D => \^ipif_data_out\(7), + Q => core_regs(263), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[8]\(26), + D => \^ipif_data_out\(8), + Q => core_regs(264), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[8][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[8]\(26), + D => \^ipif_data_out\(9), + Q => core_regs(265), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[9]\(26), + D => \^ipif_data_out\(0), + Q => \core_control_regs2_int[9]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[9]\(26), + D => \^ipif_data_out\(10), + Q => core_regs(298), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[9]\(26), + D => \^ipif_data_out\(11), + Q => core_regs(299), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[9]\(26), + D => \^ipif_data_out\(16), + Q => core_regs(304), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[9]\(26), + D => \^ipif_data_out\(17), + Q => core_regs(305), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[9]\(26), + D => \^ipif_data_out\(18), + Q => core_regs(306), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[9]\(26), + D => \^ipif_data_out\(19), + Q => core_regs(307), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[9]\(26), + D => \^ipif_data_out\(1), + Q => core_regs(289), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[9]\(26), + D => \^ipif_data_out\(20), + Q => core_regs(308), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[9]\(26), + D => \^ipif_data_out\(21), + Q => core_regs(309), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[9]\(26), + D => \^ipif_data_out\(22), + Q => core_regs(310), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[9]\(26), + D => \^ipif_data_out\(23), + Q => core_regs(311), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[9]\(26), + D => \^ipif_data_out\(24), + Q => core_regs(312), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[9]\(26), + D => \^ipif_data_out\(25), + Q => core_regs(313), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[9]\(26), + D => \^ipif_data_out\(26), + Q => core_regs(314), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[9]\(26), + D => \^ipif_data_out\(2), + Q => core_regs(290), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[9]\(26), + D => \^ipif_data_out\(3), + Q => core_regs(291), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[9]\(26), + D => \^ipif_data_out\(4), + Q => core_regs(292), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[9]\(26), + D => \^ipif_data_out\(5), + Q => core_regs(293), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[9]\(26), + D => \^ipif_data_out\(6), + Q => core_regs(294), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[9]\(26), + D => \^ipif_data_out\(7), + Q => core_regs(295), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[9]\(26), + D => \^ipif_data_out\(8), + Q => core_regs(296), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.core_control_regs_int_reg[9][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \core_control_regs_int[9]\(26), + D => \^ipif_data_out\(9), + Q => core_regs(297), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[0]\(31), + D => \^ipif_data_out\(0), + Q => \^genr_control_regs[0]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[0]\(31), + D => \^ipif_data_out\(10), + Q => \^genr_control_regs[0]\(10), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[0]\(31), + D => \^ipif_data_out\(11), + Q => \^genr_control_regs[0]\(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[0]\(31), + D => \^ipif_data_out\(13), + Q => \^genr_control_regs[0]\(13), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[0]\(31), + D => \^ipif_data_out\(14), + Q => \^genr_control_regs[0]\(14), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[0]\(31), + D => \^ipif_data_out\(15), + Q => \^genr_control_regs[0]\(15), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[0]\(31), + D => \^ipif_data_out\(16), + Q => \^genr_control_regs[0]\(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[0]\(31), + D => \^ipif_data_out\(17), + Q => \^genr_control_regs[0]\(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[0]\(31), + D => \^ipif_data_out\(18), + Q => \^genr_control_regs[0]\(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[0]\(31), + D => \^ipif_data_out\(19), + Q => \^genr_control_regs[0]\(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[0]\(31), + D => \^ipif_data_out\(1), + Q => \^genr_control_regs[0]\(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[0]\(31), + D => \^ipif_data_out\(20), + Q => \^genr_control_regs[0]\(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[0]\(31), + D => \^ipif_data_out\(21), + Q => \^genr_control_regs[0]\(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[0]\(31), + D => \^ipif_data_out\(22), + Q => \^genr_control_regs[0]\(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[0]\(31), + D => \^ipif_data_out\(23), + Q => \^genr_control_regs[0]\(23), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[0]\(31), + D => \^ipif_data_out\(24), + Q => \^genr_control_regs[0]\(24), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[0]\(31), + D => \^ipif_data_out\(25), + Q => \^genr_control_regs[0]\(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[0]\(31), + D => \^ipif_data_out\(26), + Q => \^genr_control_regs[0]\(26), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[0]\(31), + D => \^ipif_data_out\(2), + Q => \^genr_control_regs[0]\(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[0]\(31), + D => \^ipif_data_out\(30), + Q => \^genr_control_regs[0]\(30), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[0]\(31), + D => \^ipif_data_out\(31), + Q => \^genr_control_regs[0]\(31), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[0]\(31), + D => \^ipif_data_out\(3), + Q => \^genr_control_regs[0]\(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[0]\(31), + D => \^ipif_data_out\(5), + Q => \^genr_control_regs[0]\(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[0]\(31), + D => \^ipif_data_out\(8), + Q => \^genr_control_regs[0]\(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[0][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[0]\(31), + D => \^ipif_data_out\(9), + Q => \^genr_control_regs[0]\(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_52\, + Q => \^genr_control_regs[1]\(10), + R => '0' + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_51\, + Q => \^genr_control_regs[1]\(11), + R => '0' + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_50\, + Q => \^genr_control_regs[1]\(12), + R => '0' + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_49\, + Q => \^genr_control_regs[1]\(13), + R => '0' + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_48\, + Q => \^genr_control_regs[1]\(16), + R => '0' + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_47\, + Q => \^genr_control_regs[1]\(17), + R => '0' + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_46\, + Q => \^genr_control_regs[1]\(18), + R => '0' + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_45\, + Q => \^genr_control_regs[1]\(19), + R => '0' + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_44\, + Q => \^genr_control_regs[1]\(20), + R => '0' + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_43\, + Q => \^genr_control_regs[1]\(21), + R => '0' + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_42\, + Q => \^genr_control_regs[1]\(22), + R => '0' + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_41\, + Q => \^genr_control_regs[1]\(23), + R => '0' + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_40\, + Q => \^genr_control_regs[1]\(24), + R => '0' + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_39\, + Q => \^genr_control_regs[1]\(25), + R => '0' + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_38\, + Q => \^genr_control_regs[1]\(26), + R => '0' + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_37\, + Q => \^genr_control_regs[1]\(27), + R => '0' + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_36\, + Q => \^genr_control_regs[1]\(28), + R => '0' + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_35\, + Q => \^genr_control_regs[1]\(29), + R => '0' + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_34\, + Q => \^genr_control_regs[1]\(30), + R => '0' + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_0\, + Q => \^genr_control_regs[1]\(31), + R => '0' + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_54\, + Q => \^genr_control_regs[1]\(8), + R => '0' + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[1][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_53\, + Q => \^genr_control_regs[1]\(9), + R => '0' + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_60\, + Q => \^genr_control_regs[2]\(16), + R => '0' + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_59\, + Q => \^genr_control_regs[2]\(17), + R => '0' + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_58\, + Q => \^genr_control_regs[2]\(18), + R => '0' + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_57\, + Q => \^genr_control_regs[2]\(19), + R => '0' + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_56\, + Q => \^genr_control_regs[2]\(20), + R => '0' + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[2][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_55\, + Q => \^genr_control_regs[2]\(21), + R => '0' + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[3]\(31), + D => \^ipif_data_out\(10), + Q => \^genr_control_regs[3]\(10), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[3]\(31), + D => \^ipif_data_out\(11), + Q => \^genr_control_regs[3]\(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[3]\(31), + D => \^ipif_data_out\(12), + Q => \^genr_control_regs[3]\(12), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[3]\(31), + D => \^ipif_data_out\(13), + Q => \^genr_control_regs[3]\(13), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[3]\(31), + D => \^ipif_data_out\(16), + Q => \^genr_control_regs[3]\(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[3]\(31), + D => \^ipif_data_out\(17), + Q => \^genr_control_regs[3]\(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[3]\(31), + D => \^ipif_data_out\(18), + Q => \^genr_control_regs[3]\(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[3]\(31), + D => \^ipif_data_out\(19), + Q => \^genr_control_regs[3]\(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[3]\(31), + D => \^ipif_data_out\(20), + Q => \^genr_control_regs[3]\(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[3]\(31), + D => \^ipif_data_out\(21), + Q => \^genr_control_regs[3]\(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[3]\(31), + D => \^ipif_data_out\(22), + Q => \^genr_control_regs[3]\(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[3]\(31), + D => \^ipif_data_out\(23), + Q => \^genr_control_regs[3]\(23), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[3]\(31), + D => \^ipif_data_out\(24), + Q => \^genr_control_regs[3]\(24), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[3]\(31), + D => \^ipif_data_out\(25), + Q => \^genr_control_regs[3]\(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[3]\(31), + D => \^ipif_data_out\(26), + Q => \^genr_control_regs[3]\(26), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[3]\(31), + D => \^ipif_data_out\(27), + Q => \^genr_control_regs[3]\(27), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[3]\(31), + D => \^ipif_data_out\(28), + Q => \^genr_control_regs[3]\(28), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[3]\(31), + D => \^ipif_data_out\(29), + Q => \^genr_control_regs[3]\(29), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[3]\(31), + D => \^ipif_data_out\(30), + Q => \^genr_control_regs[3]\(30), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[3]\(31), + D => \^ipif_data_out\(31), + Q => \^genr_control_regs[3]\(31), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[3]\(31), + D => \^ipif_data_out\(8), + Q => \^genr_control_regs[3]\(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.genr_control_regs_int_reg[3][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \genr_control_regs_int[3]\(31), + D => \^ipif_data_out\(9), + Q => \^genr_control_regs[3]\(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_Error_reg\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => aclk, + CE => aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2PROCCLK_I_n_36\, + Q => ipif_Error, + S => p_0_in_0 + ); +\AXI4_LITE_INTERFACE.ipif_RdAck_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => aclk_en, + D => p_528_out, + Q => ipif_RdAck, + R => p_0_in_0 + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_92\, + Q => ipif_RdData(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_82\, + Q => ipif_RdData(10), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_81\, + Q => ipif_RdData(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_80\, + Q => ipif_RdData(12), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_79\, + Q => ipif_RdData(13), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_78\, + Q => ipif_RdData(14), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_77\, + Q => ipif_RdData(15), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_76\, + Q => ipif_RdData(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_75\, + Q => ipif_RdData(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_74\, + Q => ipif_RdData(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_73\, + Q => ipif_RdData(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_91\, + Q => ipif_RdData(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_72\, + Q => ipif_RdData(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_71\, + Q => ipif_RdData(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_70\, + Q => ipif_RdData(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_69\, + Q => ipif_RdData(23), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_68\, + Q => ipif_RdData(24), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_67\, + Q => ipif_RdData(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_66\, + Q => ipif_RdData(26), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_65\, + Q => ipif_RdData(27), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_64\, + Q => ipif_RdData(28), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_63\, + Q => ipif_RdData(29), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_90\, + Q => ipif_RdData(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_62\, + Q => ipif_RdData(30), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_61\, + Q => ipif_RdData(31), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_89\, + Q => ipif_RdData(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_88\, + Q => ipif_RdData(4), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_87\, + Q => ipif_RdData(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_86\, + Q => ipif_RdData(6), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_85\, + Q => ipif_RdData(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_84\, + Q => ipif_RdData(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_RdData_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.SYNC2VIDCLK_I_n_83\, + Q => ipif_RdData(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.ipif_WrAck_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => aclk_en, + D => p_526_out, + Q => ipif_WrAck, + R => p_0_in_0 + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(0), + Q => proc_sync1(0), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(10), + Q => proc_sync1(10), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(11), + Q => proc_sync1(11), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(12), + Q => proc_sync1(12), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(13), + Q => proc_sync1(13), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(14), + Q => proc_sync1(14), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(15), + Q => proc_sync1(15), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(16), + Q => proc_sync1(16), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(17), + Q => proc_sync1(17), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(18), + Q => proc_sync1(18), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(19), + Q => proc_sync1(19), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(1), + Q => proc_sync1(1), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(20), + Q => proc_sync1(20), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(21), + Q => proc_sync1(21), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(22), + Q => proc_sync1(22), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(23), + Q => proc_sync1(23), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(24), + Q => proc_sync1(24), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(25), + Q => proc_sync1(25), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(26), + Q => proc_sync1(26), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(27), + Q => proc_sync1(27), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(28), + Q => proc_sync1(28), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(29), + Q => proc_sync1(29), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(2), + Q => proc_sync1(2), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(30), + Q => proc_sync1(30), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(31), + Q => proc_sync1(31), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[32]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => ipif_proc_Addr_int(0), + Q => proc_sync1(32), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[33]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => ipif_proc_Addr_int(1), + Q => proc_sync1(33), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[34]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => ipif_proc_Addr_int(2), + Q => proc_sync1(34), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[35]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => ipif_proc_Addr_int(3), + Q => proc_sync1(35), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[36]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => ipif_proc_Addr_int(4), + Q => proc_sync1(36), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[37]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => ipif_proc_Addr_int(5), + Q => proc_sync1(37), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[38]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => ipif_proc_Addr_int(6), + Q => proc_sync1(38), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[39]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => ipif_proc_Addr_int(7), + Q => proc_sync1(39), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(3), + Q => proc_sync1(3), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[40]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => ipif_proc_Addr_int(8), + Q => proc_sync1(40), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[41]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => ipif_proc_CS(0), + Q => proc_sync1(41), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[42]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => ipif_proc_CS(1), + Q => proc_sync1(42), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[43]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => ipif_proc_RNW, + Q => proc_sync1(43), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[44]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => aresetn, + Q => proc_sync1(44), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(4), + Q => proc_sync1(4), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(5), + Q => proc_sync1(5), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(6), + Q => proc_sync1(6), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(7), + Q => proc_sync1(7), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(8), + Q => proc_sync1(8), + R => '0' + ); +\AXI4_LITE_INTERFACE.proc_sync1_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => s_axi_wdata(9), + Q => proc_sync1(9), + R => '0' + ); +\AXI4_LITE_INTERFACE.read_ack_d1_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => aclk_en, + D => p_143_out(32), + Q => read_ack_d1, + R => p_0_in_0 + ); +\AXI4_LITE_INTERFACE.read_ack_d2_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => aclk_en, + D => read_ack_d1, + Q => read_ack_d2, + R => p_0_in_0 + ); +\AXI4_LITE_INTERFACE.read_ack_d_reg[2]_srl4___AXI4_LITE_INTERFACE.read_ack_d_reg_r_1\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000" + ) + port map ( + A0 => '1', + A1 => '1', + A2 => '0', + A3 => '0', + CE => vid_aclk_en, + CLK => vid_aclk, + D => p_535_out, + Q => \AXI4_LITE_INTERFACE.read_ack_d_reg[2]_srl4___AXI4_LITE_INTERFACE.read_ack_d_reg_r_1_n_0\ + ); +\AXI4_LITE_INTERFACE.read_ack_d_reg[3]_AXI4_LITE_INTERFACE.read_ack_d_reg_r_2\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.read_ack_d_reg[2]_srl4___AXI4_LITE_INTERFACE.read_ack_d_reg_r_1_n_0\, + Q => \AXI4_LITE_INTERFACE.read_ack_d_reg[3]_AXI4_LITE_INTERFACE.read_ack_d_reg_r_2_n_0\, + R => '0' + ); +\AXI4_LITE_INTERFACE.read_ack_d_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.read_ack_d_reg_gate_n_0\, + Q => read_ack_d(4), + R => \AXI4_LITE_INTERFACE.write_ack_e1_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.read_ack_d_reg_gate\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \AXI4_LITE_INTERFACE.read_ack_d_reg[3]_AXI4_LITE_INTERFACE.read_ack_d_reg_r_2_n_0\, + I1 => \AXI4_LITE_INTERFACE.read_ack_d_reg_r_2_n_0\, + O => \AXI4_LITE_INTERFACE.read_ack_d_reg_gate_n_0\ + ); +\AXI4_LITE_INTERFACE.read_ack_d_reg_r\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.read_ack_reg_r_n_0\, + Q => \AXI4_LITE_INTERFACE.read_ack_d_reg_r_n_0\, + R => \AXI4_LITE_INTERFACE.write_ack_e1_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.read_ack_d_reg_r_0\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.read_ack_d_reg_r_n_0\, + Q => \AXI4_LITE_INTERFACE.read_ack_d_reg_r_0_n_0\, + R => \AXI4_LITE_INTERFACE.write_ack_e1_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.read_ack_d_reg_r_1\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.read_ack_d_reg_r_0_n_0\, + Q => \AXI4_LITE_INTERFACE.read_ack_d_reg_r_1_n_0\, + R => \AXI4_LITE_INTERFACE.write_ack_e1_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.read_ack_d_reg_r_2\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.read_ack_d_reg_r_1_n_0\, + Q => \AXI4_LITE_INTERFACE.read_ack_d_reg_r_2_n_0\, + R => \AXI4_LITE_INTERFACE.write_ack_e1_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.read_ack_reg_r\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => '1', + Q => \AXI4_LITE_INTERFACE.read_ack_reg_r_n_0\, + R => \AXI4_LITE_INTERFACE.write_ack_e1_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.soft_resetn_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => '1', + D => p_456_out, + Q => \^resetn_out\, + R => '0' + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \^genr_control_regs[0]\(1), + I1 => reg_update, + I2 => vid_aclk_en, + O => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => \time_control_regs2_int[16]\(0), + Q => \^time_control_regs[16]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][10]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_9_in, + Q => \^time_control_regs[16]\(10), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_10_in, + Q => \^time_control_regs[16]\(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_11_in, + Q => \^time_control_regs[16]\(12), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_12_in, + Q => \^time_control_regs[16]\(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_13_in, + Q => \^time_control_regs[16]\(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_14_in, + Q => \^time_control_regs[16]\(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_15_in, + Q => \^time_control_regs[16]\(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_0_in, + Q => \^time_control_regs[16]\(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][20]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_16_in, + Q => \^time_control_regs[16]\(20), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_17_in, + Q => \^time_control_regs[16]\(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][22]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_18_in, + Q => \^time_control_regs[16]\(22), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][23]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_19_in, + Q => \^time_control_regs[16]\(23), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_20_in, + Q => \^time_control_regs[16]\(24), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][25]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_21_in, + Q => \^time_control_regs[16]\(25), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_22_in, + Q => \^time_control_regs[16]\(26), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_23_in, + Q => \^time_control_regs[16]\(27), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_24_in, + Q => \^time_control_regs[16]\(28), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_1_in, + Q => \^time_control_regs[16]\(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_2_in, + Q => \^time_control_regs[16]\(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_3_in, + Q => \^time_control_regs[16]\(4), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_4_in, + Q => \^time_control_regs[16]\(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_5_in, + Q => \^time_control_regs[16]\(6), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_6_in, + Q => \^time_control_regs[16]\(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][8]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_7_in, + Q => \^time_control_regs[16]\(8), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[16][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_8_in, + Q => \^time_control_regs[16]\(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[18][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_5_out(7), + Q => \^time_control_regs[18]\(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[18][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_5_out(8), + Q => \^time_control_regs[18]\(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[18][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_5_out(9), + Q => \^time_control_regs[18]\(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[19][0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_8_out(0), + Q => \^time_control_regs[19]\(0), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[19][1]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_8_out(1), + Q => \^time_control_regs[19]\(1), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[19][2]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_8_out(2), + Q => \^time_control_regs[19]\(2), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[19][3]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_8_out(3), + Q => \^time_control_regs[19]\(3), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[19][4]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_8_out(4), + Q => \^time_control_regs[19]\(4), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[19][5]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => p_8_out(5), + Q => \^time_control_regs[19]\(5), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => \time_control_regs2_int[20]\(0), + Q => \^time_control_regs[20]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][10]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(906), + Q => \^time_control_regs[20]\(10), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(907), + Q => \^time_control_regs[20]\(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(908), + Q => \^time_control_regs[20]\(12), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(912), + Q => \^time_control_regs[20]\(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(913), + Q => \^time_control_regs[20]\(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(914), + Q => \^time_control_regs[20]\(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(915), + Q => \^time_control_regs[20]\(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][1]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(897), + Q => \^time_control_regs[20]\(1), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(916), + Q => \^time_control_regs[20]\(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(917), + Q => \^time_control_regs[20]\(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(918), + Q => \^time_control_regs[20]\(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(919), + Q => \^time_control_regs[20]\(23), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(920), + Q => \^time_control_regs[20]\(24), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(921), + Q => \^time_control_regs[20]\(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(922), + Q => \^time_control_regs[20]\(26), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(923), + Q => \^time_control_regs[20]\(27), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(924), + Q => \^time_control_regs[20]\(28), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(898), + Q => \^time_control_regs[20]\(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(899), + Q => \^time_control_regs[20]\(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][4]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(900), + Q => \^time_control_regs[20]\(4), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][5]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(901), + Q => \^time_control_regs[20]\(5), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][6]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(902), + Q => \^time_control_regs[20]\(6), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(903), + Q => \^time_control_regs[20]\(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(904), + Q => \^time_control_regs[20]\(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[20][9]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(905), + Q => \^time_control_regs[20]\(9), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => \time_control_regs2_int[21]\(0), + Q => \^time_control_regs[21]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(938), + Q => \^time_control_regs[21]\(10), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(939), + Q => \^time_control_regs[21]\(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(940), + Q => \^time_control_regs[21]\(12), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(944), + Q => \^time_control_regs[21]\(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][17]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(945), + Q => \^time_control_regs[21]\(17), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][18]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(946), + Q => \^time_control_regs[21]\(18), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][19]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(947), + Q => \^time_control_regs[21]\(19), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][1]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(929), + Q => \^time_control_regs[21]\(1), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(948), + Q => \^time_control_regs[21]\(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][21]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(949), + Q => \^time_control_regs[21]\(21), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][22]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(950), + Q => \^time_control_regs[21]\(22), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][23]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(951), + Q => \^time_control_regs[21]\(23), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(952), + Q => \^time_control_regs[21]\(24), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][25]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(953), + Q => \^time_control_regs[21]\(25), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(954), + Q => \^time_control_regs[21]\(26), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(955), + Q => \^time_control_regs[21]\(27), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(956), + Q => \^time_control_regs[21]\(28), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][2]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(930), + Q => \^time_control_regs[21]\(2), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][3]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(931), + Q => \^time_control_regs[21]\(3), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(932), + Q => \^time_control_regs[21]\(4), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][5]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(933), + Q => \^time_control_regs[21]\(5), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][6]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(934), + Q => \^time_control_regs[21]\(6), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][7]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(935), + Q => \^time_control_regs[21]\(7), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(936), + Q => \^time_control_regs[21]\(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[21][9]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(937), + Q => \^time_control_regs[21]\(9), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => \time_control_regs2_int[22]\(0), + Q => \^time_control_regs[22]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][10]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(970), + Q => \^time_control_regs[22]\(10), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(971), + Q => \^time_control_regs[22]\(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(972), + Q => \^time_control_regs[22]\(12), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(976), + Q => \^time_control_regs[22]\(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][17]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(977), + Q => \^time_control_regs[22]\(17), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][18]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(978), + Q => \^time_control_regs[22]\(18), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(979), + Q => \^time_control_regs[22]\(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][1]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(961), + Q => \^time_control_regs[22]\(1), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][20]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(980), + Q => \^time_control_regs[22]\(20), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(981), + Q => \^time_control_regs[22]\(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(982), + Q => \^time_control_regs[22]\(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][23]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(983), + Q => \^time_control_regs[22]\(23), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][24]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(984), + Q => \^time_control_regs[22]\(24), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(985), + Q => \^time_control_regs[22]\(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][26]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(986), + Q => \^time_control_regs[22]\(26), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(987), + Q => \^time_control_regs[22]\(27), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(988), + Q => \^time_control_regs[22]\(28), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][2]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(962), + Q => \^time_control_regs[22]\(2), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][3]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(963), + Q => \^time_control_regs[22]\(3), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(964), + Q => \^time_control_regs[22]\(4), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][5]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(965), + Q => \^time_control_regs[22]\(5), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][6]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(966), + Q => \^time_control_regs[22]\(6), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(967), + Q => \^time_control_regs[22]\(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][8]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(968), + Q => \^time_control_regs[22]\(8), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[22][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(969), + Q => \^time_control_regs[22]\(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => \time_control_regs2_int[23]\(0), + Q => \^time_control_regs[23]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][10]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1002), + Q => \^time_control_regs[23]\(10), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1003), + Q => \^time_control_regs[23]\(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1004), + Q => \^time_control_regs[23]\(12), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1008), + Q => \^time_control_regs[23]\(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1009), + Q => \^time_control_regs[23]\(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1010), + Q => \^time_control_regs[23]\(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1011), + Q => \^time_control_regs[23]\(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(993), + Q => \^time_control_regs[23]\(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1012), + Q => \^time_control_regs[23]\(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1013), + Q => \^time_control_regs[23]\(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1014), + Q => \^time_control_regs[23]\(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1015), + Q => \^time_control_regs[23]\(23), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][24]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1016), + Q => \^time_control_regs[23]\(24), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1017), + Q => \^time_control_regs[23]\(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][26]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1018), + Q => \^time_control_regs[23]\(26), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1019), + Q => \^time_control_regs[23]\(27), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1020), + Q => \^time_control_regs[23]\(28), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(994), + Q => \^time_control_regs[23]\(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(995), + Q => \^time_control_regs[23]\(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(996), + Q => \^time_control_regs[23]\(4), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(997), + Q => \^time_control_regs[23]\(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(998), + Q => \^time_control_regs[23]\(6), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(999), + Q => \^time_control_regs[23]\(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][8]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1000), + Q => \^time_control_regs[23]\(8), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[23][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1001), + Q => \^time_control_regs[23]\(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => \time_control_regs2_int[24]\(0), + Q => \^time_control_regs[24]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1034), + Q => \^time_control_regs[24]\(10), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1035), + Q => \^time_control_regs[24]\(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1036), + Q => \^time_control_regs[24]\(12), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][16]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1040), + Q => \^time_control_regs[24]\(16), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1041), + Q => \^time_control_regs[24]\(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1042), + Q => \^time_control_regs[24]\(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][19]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1043), + Q => \^time_control_regs[24]\(19), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1025), + Q => \^time_control_regs[24]\(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][20]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1044), + Q => \^time_control_regs[24]\(20), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1045), + Q => \^time_control_regs[24]\(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][22]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1046), + Q => \^time_control_regs[24]\(22), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][23]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1047), + Q => \^time_control_regs[24]\(23), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1048), + Q => \^time_control_regs[24]\(24), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][25]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1049), + Q => \^time_control_regs[24]\(25), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1050), + Q => \^time_control_regs[24]\(26), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1051), + Q => \^time_control_regs[24]\(27), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1052), + Q => \^time_control_regs[24]\(28), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][2]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1026), + Q => \^time_control_regs[24]\(2), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1027), + Q => \^time_control_regs[24]\(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][4]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1028), + Q => \^time_control_regs[24]\(4), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1029), + Q => \^time_control_regs[24]\(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][6]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1030), + Q => \^time_control_regs[24]\(6), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][7]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1031), + Q => \^time_control_regs[24]\(7), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1032), + Q => \^time_control_regs[24]\(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[24][9]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1033), + Q => \^time_control_regs[24]\(9), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => \time_control_regs2_int[25]\(0), + Q => \^time_control_regs[25]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][10]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1066), + Q => \^time_control_regs[25]\(10), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1067), + Q => \^time_control_regs[25]\(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1068), + Q => \^time_control_regs[25]\(12), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1072), + Q => \^time_control_regs[25]\(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1073), + Q => \^time_control_regs[25]\(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1074), + Q => \^time_control_regs[25]\(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1075), + Q => \^time_control_regs[25]\(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1057), + Q => \^time_control_regs[25]\(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1076), + Q => \^time_control_regs[25]\(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1077), + Q => \^time_control_regs[25]\(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1078), + Q => \^time_control_regs[25]\(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1079), + Q => \^time_control_regs[25]\(23), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][24]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1080), + Q => \^time_control_regs[25]\(24), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1081), + Q => \^time_control_regs[25]\(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][26]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1082), + Q => \^time_control_regs[25]\(26), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1083), + Q => \^time_control_regs[25]\(27), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1084), + Q => \^time_control_regs[25]\(28), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1058), + Q => \^time_control_regs[25]\(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1059), + Q => \^time_control_regs[25]\(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1060), + Q => \^time_control_regs[25]\(4), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1061), + Q => \^time_control_regs[25]\(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1062), + Q => \^time_control_regs[25]\(6), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1063), + Q => \^time_control_regs[25]\(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][8]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1064), + Q => \^time_control_regs[25]\(8), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[25][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1065), + Q => \^time_control_regs[25]\(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => \time_control_regs2_int[26]\(0), + Q => \^time_control_regs[26]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][10]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1098), + Q => \^time_control_regs[26]\(10), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1099), + Q => \^time_control_regs[26]\(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1100), + Q => \^time_control_regs[26]\(12), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1104), + Q => \^time_control_regs[26]\(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1105), + Q => \^time_control_regs[26]\(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1106), + Q => \^time_control_regs[26]\(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1107), + Q => \^time_control_regs[26]\(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1089), + Q => \^time_control_regs[26]\(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1108), + Q => \^time_control_regs[26]\(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1109), + Q => \^time_control_regs[26]\(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1110), + Q => \^time_control_regs[26]\(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1111), + Q => \^time_control_regs[26]\(23), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][24]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1112), + Q => \^time_control_regs[26]\(24), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1113), + Q => \^time_control_regs[26]\(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][26]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1114), + Q => \^time_control_regs[26]\(26), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1115), + Q => \^time_control_regs[26]\(27), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1116), + Q => \^time_control_regs[26]\(28), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1090), + Q => \^time_control_regs[26]\(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1091), + Q => \^time_control_regs[26]\(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1092), + Q => \^time_control_regs[26]\(4), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1093), + Q => \^time_control_regs[26]\(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1094), + Q => \^time_control_regs[26]\(6), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1095), + Q => \^time_control_regs[26]\(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][8]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1096), + Q => \^time_control_regs[26]\(8), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[26][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1097), + Q => \^time_control_regs[26]\(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => \time_control_regs2_int[27]\(0), + Q => \^time_control_regs[27]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1130), + Q => \^time_control_regs[27]\(10), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1131), + Q => \^time_control_regs[27]\(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1132), + Q => \^time_control_regs[27]\(12), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][16]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1136), + Q => \^time_control_regs[27]\(16), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1137), + Q => \^time_control_regs[27]\(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1138), + Q => \^time_control_regs[27]\(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][19]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1139), + Q => \^time_control_regs[27]\(19), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1121), + Q => \^time_control_regs[27]\(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][20]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1140), + Q => \^time_control_regs[27]\(20), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1141), + Q => \^time_control_regs[27]\(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][22]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1142), + Q => \^time_control_regs[27]\(22), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][23]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1143), + Q => \^time_control_regs[27]\(23), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1144), + Q => \^time_control_regs[27]\(24), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][25]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1145), + Q => \^time_control_regs[27]\(25), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1146), + Q => \^time_control_regs[27]\(26), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1147), + Q => \^time_control_regs[27]\(27), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1148), + Q => \^time_control_regs[27]\(28), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][2]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1122), + Q => \^time_control_regs[27]\(2), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1123), + Q => \^time_control_regs[27]\(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][4]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1124), + Q => \^time_control_regs[27]\(4), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1125), + Q => \^time_control_regs[27]\(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][6]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1126), + Q => \^time_control_regs[27]\(6), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][7]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1127), + Q => \^time_control_regs[27]\(7), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1128), + Q => \^time_control_regs[27]\(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[27][9]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1129), + Q => \^time_control_regs[27]\(9), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => \time_control_regs2_int[28]\(0), + Q => \^time_control_regs[28]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][10]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1162), + Q => \^time_control_regs[28]\(10), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1163), + Q => \^time_control_regs[28]\(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1164), + Q => \^time_control_regs[28]\(12), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1168), + Q => \^time_control_regs[28]\(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1169), + Q => \^time_control_regs[28]\(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1170), + Q => \^time_control_regs[28]\(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1171), + Q => \^time_control_regs[28]\(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1153), + Q => \^time_control_regs[28]\(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1172), + Q => \^time_control_regs[28]\(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1173), + Q => \^time_control_regs[28]\(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1174), + Q => \^time_control_regs[28]\(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1175), + Q => \^time_control_regs[28]\(23), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][24]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1176), + Q => \^time_control_regs[28]\(24), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1177), + Q => \^time_control_regs[28]\(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][26]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1178), + Q => \^time_control_regs[28]\(26), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1179), + Q => \^time_control_regs[28]\(27), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1180), + Q => \^time_control_regs[28]\(28), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1154), + Q => \^time_control_regs[28]\(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1155), + Q => \^time_control_regs[28]\(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1156), + Q => \^time_control_regs[28]\(4), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1157), + Q => \^time_control_regs[28]\(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1158), + Q => \^time_control_regs[28]\(6), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1159), + Q => \^time_control_regs[28]\(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][8]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1160), + Q => \^time_control_regs[28]\(8), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs2_int_reg[28][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \AXI4_LITE_INTERFACE.time_control_regs2_int[16][28]_i_1_n_0\, + D => genr_regs(1161), + Q => \^time_control_regs[28]\(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[16]\(28), + D => \^ipif_data_out\(0), + Q => \time_control_regs2_int[16]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][10]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[16]\(28), + D => \^ipif_data_out\(10), + Q => p_9_in, + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[16]\(28), + D => \^ipif_data_out\(11), + Q => p_10_in, + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[16]\(28), + D => \^ipif_data_out\(12), + Q => p_11_in, + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[16]\(28), + D => \^ipif_data_out\(16), + Q => p_12_in, + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[16]\(28), + D => \^ipif_data_out\(17), + Q => p_13_in, + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[16]\(28), + D => \^ipif_data_out\(18), + Q => p_14_in, + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[16]\(28), + D => \^ipif_data_out\(19), + Q => p_15_in, + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[16]\(28), + D => \^ipif_data_out\(1), + Q => p_0_in, + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][20]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[16]\(28), + D => \^ipif_data_out\(20), + Q => p_16_in, + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[16]\(28), + D => \^ipif_data_out\(21), + Q => p_17_in, + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][22]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[16]\(28), + D => \^ipif_data_out\(22), + Q => p_18_in, + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][23]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[16]\(28), + D => \^ipif_data_out\(23), + Q => p_19_in, + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[16]\(28), + D => \^ipif_data_out\(24), + Q => p_20_in, + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][25]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[16]\(28), + D => \^ipif_data_out\(25), + Q => p_21_in, + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[16]\(28), + D => \^ipif_data_out\(26), + Q => p_22_in, + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[16]\(28), + D => \^ipif_data_out\(27), + Q => p_23_in, + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[16]\(28), + D => \^ipif_data_out\(28), + Q => p_24_in, + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[16]\(28), + D => \^ipif_data_out\(2), + Q => p_1_in, + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[16]\(28), + D => \^ipif_data_out\(3), + Q => p_2_in, + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[16]\(28), + D => \^ipif_data_out\(4), + Q => p_3_in, + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[16]\(28), + D => \^ipif_data_out\(5), + Q => p_4_in, + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[16]\(28), + D => \^ipif_data_out\(6), + Q => p_5_in, + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[16]\(28), + D => \^ipif_data_out\(7), + Q => p_6_in, + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][8]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[16]\(28), + D => \^ipif_data_out\(8), + Q => p_7_in, + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[16][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[16]\(28), + D => \^ipif_data_out\(9), + Q => p_8_in, + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[18]\(6), + D => \^ipif_data_out\(0), + Q => \^time_control_regs[18]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][1]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[18]\(6), + D => \^ipif_data_out\(1), + Q => \^time_control_regs[18]\(1), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[18]\(6), + D => \^ipif_data_out\(2), + Q => \^time_control_regs[18]\(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[18]\(6), + D => \^ipif_data_out\(3), + Q => \^time_control_regs[18]\(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[18]\(6), + D => \^ipif_data_out\(6), + Q => \^time_control_regs[18]\(6), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[18]\(6), + D => \^ipif_data_out\(7), + Q => p_5_out(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[18]\(6), + D => \^ipif_data_out\(8), + Q => p_5_out(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[18][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[18]\(6), + D => \^ipif_data_out\(9), + Q => p_5_out(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => p_2_out(6), + D => \^ipif_data_out\(0), + Q => p_8_out(0), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][1]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => p_2_out(6), + D => \^ipif_data_out\(1), + Q => p_8_out(1), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][2]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => p_2_out(6), + D => \^ipif_data_out\(2), + Q => p_8_out(2), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][3]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => p_2_out(6), + D => \^ipif_data_out\(3), + Q => p_8_out(3), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][4]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => p_2_out(6), + D => \^ipif_data_out\(4), + Q => p_8_out(4), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][5]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => p_2_out(6), + D => \^ipif_data_out\(5), + Q => p_8_out(5), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[19][6]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => p_2_out(6), + D => \^ipif_data_out\(6), + Q => \^time_control_regs[19]\(6), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[20]\(28), + D => \^ipif_data_out\(0), + Q => \time_control_regs2_int[20]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][10]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[20]\(28), + D => \^ipif_data_out\(10), + Q => genr_regs(906), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[20]\(28), + D => \^ipif_data_out\(11), + Q => genr_regs(907), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[20]\(28), + D => \^ipif_data_out\(12), + Q => genr_regs(908), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[20]\(28), + D => \^ipif_data_out\(16), + Q => genr_regs(912), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[20]\(28), + D => \^ipif_data_out\(17), + Q => genr_regs(913), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[20]\(28), + D => \^ipif_data_out\(18), + Q => genr_regs(914), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[20]\(28), + D => \^ipif_data_out\(19), + Q => genr_regs(915), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][1]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[20]\(28), + D => \^ipif_data_out\(1), + Q => genr_regs(897), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[20]\(28), + D => \^ipif_data_out\(20), + Q => genr_regs(916), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[20]\(28), + D => \^ipif_data_out\(21), + Q => genr_regs(917), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[20]\(28), + D => \^ipif_data_out\(22), + Q => genr_regs(918), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[20]\(28), + D => \^ipif_data_out\(23), + Q => genr_regs(919), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[20]\(28), + D => \^ipif_data_out\(24), + Q => genr_regs(920), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[20]\(28), + D => \^ipif_data_out\(25), + Q => genr_regs(921), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[20]\(28), + D => \^ipif_data_out\(26), + Q => genr_regs(922), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[20]\(28), + D => \^ipif_data_out\(27), + Q => genr_regs(923), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[20]\(28), + D => \^ipif_data_out\(28), + Q => genr_regs(924), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[20]\(28), + D => \^ipif_data_out\(2), + Q => genr_regs(898), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[20]\(28), + D => \^ipif_data_out\(3), + Q => genr_regs(899), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][4]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[20]\(28), + D => \^ipif_data_out\(4), + Q => genr_regs(900), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][5]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[20]\(28), + D => \^ipif_data_out\(5), + Q => genr_regs(901), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][6]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[20]\(28), + D => \^ipif_data_out\(6), + Q => genr_regs(902), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[20]\(28), + D => \^ipif_data_out\(7), + Q => genr_regs(903), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[20]\(28), + D => \^ipif_data_out\(8), + Q => genr_regs(904), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[20][9]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[20]\(28), + D => \^ipif_data_out\(9), + Q => genr_regs(905), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[21]\(28), + D => \^ipif_data_out\(0), + Q => \time_control_regs2_int[21]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[21]\(28), + D => \^ipif_data_out\(10), + Q => genr_regs(938), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[21]\(28), + D => \^ipif_data_out\(11), + Q => genr_regs(939), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[21]\(28), + D => \^ipif_data_out\(12), + Q => genr_regs(940), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[21]\(28), + D => \^ipif_data_out\(16), + Q => genr_regs(944), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][17]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[21]\(28), + D => \^ipif_data_out\(17), + Q => genr_regs(945), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][18]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[21]\(28), + D => \^ipif_data_out\(18), + Q => genr_regs(946), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][19]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[21]\(28), + D => \^ipif_data_out\(19), + Q => genr_regs(947), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][1]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[21]\(28), + D => \^ipif_data_out\(1), + Q => genr_regs(929), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[21]\(28), + D => \^ipif_data_out\(20), + Q => genr_regs(948), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][21]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[21]\(28), + D => \^ipif_data_out\(21), + Q => genr_regs(949), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][22]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[21]\(28), + D => \^ipif_data_out\(22), + Q => genr_regs(950), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][23]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[21]\(28), + D => \^ipif_data_out\(23), + Q => genr_regs(951), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[21]\(28), + D => \^ipif_data_out\(24), + Q => genr_regs(952), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][25]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[21]\(28), + D => \^ipif_data_out\(25), + Q => genr_regs(953), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[21]\(28), + D => \^ipif_data_out\(26), + Q => genr_regs(954), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[21]\(28), + D => \^ipif_data_out\(27), + Q => genr_regs(955), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[21]\(28), + D => \^ipif_data_out\(28), + Q => genr_regs(956), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][2]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[21]\(28), + D => \^ipif_data_out\(2), + Q => genr_regs(930), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][3]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[21]\(28), + D => \^ipif_data_out\(3), + Q => genr_regs(931), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[21]\(28), + D => \^ipif_data_out\(4), + Q => genr_regs(932), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][5]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[21]\(28), + D => \^ipif_data_out\(5), + Q => genr_regs(933), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][6]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[21]\(28), + D => \^ipif_data_out\(6), + Q => genr_regs(934), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][7]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[21]\(28), + D => \^ipif_data_out\(7), + Q => genr_regs(935), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[21]\(28), + D => \^ipif_data_out\(8), + Q => genr_regs(936), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[21][9]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[21]\(28), + D => \^ipif_data_out\(9), + Q => genr_regs(937), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[22]\(28), + D => \^ipif_data_out\(0), + Q => \time_control_regs2_int[22]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][10]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[22]\(28), + D => \^ipif_data_out\(10), + Q => genr_regs(970), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[22]\(28), + D => \^ipif_data_out\(11), + Q => genr_regs(971), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[22]\(28), + D => \^ipif_data_out\(12), + Q => genr_regs(972), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[22]\(28), + D => \^ipif_data_out\(16), + Q => genr_regs(976), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][17]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[22]\(28), + D => \^ipif_data_out\(17), + Q => genr_regs(977), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][18]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[22]\(28), + D => \^ipif_data_out\(18), + Q => genr_regs(978), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[22]\(28), + D => \^ipif_data_out\(19), + Q => genr_regs(979), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][1]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[22]\(28), + D => \^ipif_data_out\(1), + Q => genr_regs(961), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][20]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[22]\(28), + D => \^ipif_data_out\(20), + Q => genr_regs(980), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[22]\(28), + D => \^ipif_data_out\(21), + Q => genr_regs(981), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[22]\(28), + D => \^ipif_data_out\(22), + Q => genr_regs(982), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][23]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[22]\(28), + D => \^ipif_data_out\(23), + Q => genr_regs(983), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][24]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[22]\(28), + D => \^ipif_data_out\(24), + Q => genr_regs(984), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[22]\(28), + D => \^ipif_data_out\(25), + Q => genr_regs(985), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][26]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[22]\(28), + D => \^ipif_data_out\(26), + Q => genr_regs(986), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[22]\(28), + D => \^ipif_data_out\(27), + Q => genr_regs(987), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[22]\(28), + D => \^ipif_data_out\(28), + Q => genr_regs(988), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][2]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[22]\(28), + D => \^ipif_data_out\(2), + Q => genr_regs(962), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][3]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[22]\(28), + D => \^ipif_data_out\(3), + Q => genr_regs(963), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[22]\(28), + D => \^ipif_data_out\(4), + Q => genr_regs(964), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][5]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[22]\(28), + D => \^ipif_data_out\(5), + Q => genr_regs(965), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][6]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[22]\(28), + D => \^ipif_data_out\(6), + Q => genr_regs(966), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[22]\(28), + D => \^ipif_data_out\(7), + Q => genr_regs(967), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][8]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[22]\(28), + D => \^ipif_data_out\(8), + Q => genr_regs(968), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[22][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[22]\(28), + D => \^ipif_data_out\(9), + Q => genr_regs(969), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[23]\(28), + D => \^ipif_data_out\(0), + Q => \time_control_regs2_int[23]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][10]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[23]\(28), + D => \^ipif_data_out\(10), + Q => genr_regs(1002), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[23]\(28), + D => \^ipif_data_out\(11), + Q => genr_regs(1003), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[23]\(28), + D => \^ipif_data_out\(12), + Q => genr_regs(1004), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[23]\(28), + D => \^ipif_data_out\(16), + Q => genr_regs(1008), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[23]\(28), + D => \^ipif_data_out\(17), + Q => genr_regs(1009), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[23]\(28), + D => \^ipif_data_out\(18), + Q => genr_regs(1010), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[23]\(28), + D => \^ipif_data_out\(19), + Q => genr_regs(1011), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[23]\(28), + D => \^ipif_data_out\(1), + Q => genr_regs(993), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[23]\(28), + D => \^ipif_data_out\(20), + Q => genr_regs(1012), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[23]\(28), + D => \^ipif_data_out\(21), + Q => genr_regs(1013), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[23]\(28), + D => \^ipif_data_out\(22), + Q => genr_regs(1014), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[23]\(28), + D => \^ipif_data_out\(23), + Q => genr_regs(1015), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][24]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[23]\(28), + D => \^ipif_data_out\(24), + Q => genr_regs(1016), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[23]\(28), + D => \^ipif_data_out\(25), + Q => genr_regs(1017), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][26]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[23]\(28), + D => \^ipif_data_out\(26), + Q => genr_regs(1018), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[23]\(28), + D => \^ipif_data_out\(27), + Q => genr_regs(1019), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[23]\(28), + D => \^ipif_data_out\(28), + Q => genr_regs(1020), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[23]\(28), + D => \^ipif_data_out\(2), + Q => genr_regs(994), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[23]\(28), + D => \^ipif_data_out\(3), + Q => genr_regs(995), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[23]\(28), + D => \^ipif_data_out\(4), + Q => genr_regs(996), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[23]\(28), + D => \^ipif_data_out\(5), + Q => genr_regs(997), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[23]\(28), + D => \^ipif_data_out\(6), + Q => genr_regs(998), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[23]\(28), + D => \^ipif_data_out\(7), + Q => genr_regs(999), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][8]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[23]\(28), + D => \^ipif_data_out\(8), + Q => genr_regs(1000), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[23][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[23]\(28), + D => \^ipif_data_out\(9), + Q => genr_regs(1001), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[24]\(28), + D => \^ipif_data_out\(0), + Q => \time_control_regs2_int[24]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[24]\(28), + D => \^ipif_data_out\(10), + Q => genr_regs(1034), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[24]\(28), + D => \^ipif_data_out\(11), + Q => genr_regs(1035), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[24]\(28), + D => \^ipif_data_out\(12), + Q => genr_regs(1036), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][16]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[24]\(28), + D => \^ipif_data_out\(16), + Q => genr_regs(1040), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[24]\(28), + D => \^ipif_data_out\(17), + Q => genr_regs(1041), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[24]\(28), + D => \^ipif_data_out\(18), + Q => genr_regs(1042), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][19]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[24]\(28), + D => \^ipif_data_out\(19), + Q => genr_regs(1043), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[24]\(28), + D => \^ipif_data_out\(1), + Q => genr_regs(1025), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][20]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[24]\(28), + D => \^ipif_data_out\(20), + Q => genr_regs(1044), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[24]\(28), + D => \^ipif_data_out\(21), + Q => genr_regs(1045), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][22]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[24]\(28), + D => \^ipif_data_out\(22), + Q => genr_regs(1046), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][23]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[24]\(28), + D => \^ipif_data_out\(23), + Q => genr_regs(1047), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[24]\(28), + D => \^ipif_data_out\(24), + Q => genr_regs(1048), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][25]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[24]\(28), + D => \^ipif_data_out\(25), + Q => genr_regs(1049), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[24]\(28), + D => \^ipif_data_out\(26), + Q => genr_regs(1050), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[24]\(28), + D => \^ipif_data_out\(27), + Q => genr_regs(1051), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[24]\(28), + D => \^ipif_data_out\(28), + Q => genr_regs(1052), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][2]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[24]\(28), + D => \^ipif_data_out\(2), + Q => genr_regs(1026), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[24]\(28), + D => \^ipif_data_out\(3), + Q => genr_regs(1027), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][4]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[24]\(28), + D => \^ipif_data_out\(4), + Q => genr_regs(1028), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[24]\(28), + D => \^ipif_data_out\(5), + Q => genr_regs(1029), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][6]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[24]\(28), + D => \^ipif_data_out\(6), + Q => genr_regs(1030), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][7]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[24]\(28), + D => \^ipif_data_out\(7), + Q => genr_regs(1031), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[24]\(28), + D => \^ipif_data_out\(8), + Q => genr_regs(1032), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[24][9]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[24]\(28), + D => \^ipif_data_out\(9), + Q => genr_regs(1033), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[25]\(28), + D => \^ipif_data_out\(0), + Q => \time_control_regs2_int[25]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][10]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[25]\(28), + D => \^ipif_data_out\(10), + Q => genr_regs(1066), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[25]\(28), + D => \^ipif_data_out\(11), + Q => genr_regs(1067), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[25]\(28), + D => \^ipif_data_out\(12), + Q => genr_regs(1068), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[25]\(28), + D => \^ipif_data_out\(16), + Q => genr_regs(1072), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[25]\(28), + D => \^ipif_data_out\(17), + Q => genr_regs(1073), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[25]\(28), + D => \^ipif_data_out\(18), + Q => genr_regs(1074), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[25]\(28), + D => \^ipif_data_out\(19), + Q => genr_regs(1075), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[25]\(28), + D => \^ipif_data_out\(1), + Q => genr_regs(1057), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[25]\(28), + D => \^ipif_data_out\(20), + Q => genr_regs(1076), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[25]\(28), + D => \^ipif_data_out\(21), + Q => genr_regs(1077), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[25]\(28), + D => \^ipif_data_out\(22), + Q => genr_regs(1078), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[25]\(28), + D => \^ipif_data_out\(23), + Q => genr_regs(1079), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][24]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[25]\(28), + D => \^ipif_data_out\(24), + Q => genr_regs(1080), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[25]\(28), + D => \^ipif_data_out\(25), + Q => genr_regs(1081), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][26]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[25]\(28), + D => \^ipif_data_out\(26), + Q => genr_regs(1082), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[25]\(28), + D => \^ipif_data_out\(27), + Q => genr_regs(1083), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[25]\(28), + D => \^ipif_data_out\(28), + Q => genr_regs(1084), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[25]\(28), + D => \^ipif_data_out\(2), + Q => genr_regs(1058), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[25]\(28), + D => \^ipif_data_out\(3), + Q => genr_regs(1059), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[25]\(28), + D => \^ipif_data_out\(4), + Q => genr_regs(1060), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[25]\(28), + D => \^ipif_data_out\(5), + Q => genr_regs(1061), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[25]\(28), + D => \^ipif_data_out\(6), + Q => genr_regs(1062), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[25]\(28), + D => \^ipif_data_out\(7), + Q => genr_regs(1063), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][8]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[25]\(28), + D => \^ipif_data_out\(8), + Q => genr_regs(1064), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[25][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[25]\(28), + D => \^ipif_data_out\(9), + Q => genr_regs(1065), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[26]\(28), + D => \^ipif_data_out\(0), + Q => \time_control_regs2_int[26]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][10]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[26]\(28), + D => \^ipif_data_out\(10), + Q => genr_regs(1098), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[26]\(28), + D => \^ipif_data_out\(11), + Q => genr_regs(1099), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[26]\(28), + D => \^ipif_data_out\(12), + Q => genr_regs(1100), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[26]\(28), + D => \^ipif_data_out\(16), + Q => genr_regs(1104), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[26]\(28), + D => \^ipif_data_out\(17), + Q => genr_regs(1105), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[26]\(28), + D => \^ipif_data_out\(18), + Q => genr_regs(1106), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[26]\(28), + D => \^ipif_data_out\(19), + Q => genr_regs(1107), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[26]\(28), + D => \^ipif_data_out\(1), + Q => genr_regs(1089), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[26]\(28), + D => \^ipif_data_out\(20), + Q => genr_regs(1108), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[26]\(28), + D => \^ipif_data_out\(21), + Q => genr_regs(1109), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[26]\(28), + D => \^ipif_data_out\(22), + Q => genr_regs(1110), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[26]\(28), + D => \^ipif_data_out\(23), + Q => genr_regs(1111), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][24]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[26]\(28), + D => \^ipif_data_out\(24), + Q => genr_regs(1112), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[26]\(28), + D => \^ipif_data_out\(25), + Q => genr_regs(1113), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][26]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[26]\(28), + D => \^ipif_data_out\(26), + Q => genr_regs(1114), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[26]\(28), + D => \^ipif_data_out\(27), + Q => genr_regs(1115), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[26]\(28), + D => \^ipif_data_out\(28), + Q => genr_regs(1116), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[26]\(28), + D => \^ipif_data_out\(2), + Q => genr_regs(1090), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[26]\(28), + D => \^ipif_data_out\(3), + Q => genr_regs(1091), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[26]\(28), + D => \^ipif_data_out\(4), + Q => genr_regs(1092), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[26]\(28), + D => \^ipif_data_out\(5), + Q => genr_regs(1093), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[26]\(28), + D => \^ipif_data_out\(6), + Q => genr_regs(1094), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[26]\(28), + D => \^ipif_data_out\(7), + Q => genr_regs(1095), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][8]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[26]\(28), + D => \^ipif_data_out\(8), + Q => genr_regs(1096), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[26][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[26]\(28), + D => \^ipif_data_out\(9), + Q => genr_regs(1097), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[27]\(28), + D => \^ipif_data_out\(0), + Q => \time_control_regs2_int[27]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[27]\(28), + D => \^ipif_data_out\(10), + Q => genr_regs(1130), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[27]\(28), + D => \^ipif_data_out\(11), + Q => genr_regs(1131), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[27]\(28), + D => \^ipif_data_out\(12), + Q => genr_regs(1132), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][16]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[27]\(28), + D => \^ipif_data_out\(16), + Q => genr_regs(1136), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[27]\(28), + D => \^ipif_data_out\(17), + Q => genr_regs(1137), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[27]\(28), + D => \^ipif_data_out\(18), + Q => genr_regs(1138), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][19]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[27]\(28), + D => \^ipif_data_out\(19), + Q => genr_regs(1139), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[27]\(28), + D => \^ipif_data_out\(1), + Q => genr_regs(1121), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][20]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[27]\(28), + D => \^ipif_data_out\(20), + Q => genr_regs(1140), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[27]\(28), + D => \^ipif_data_out\(21), + Q => genr_regs(1141), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][22]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[27]\(28), + D => \^ipif_data_out\(22), + Q => genr_regs(1142), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][23]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[27]\(28), + D => \^ipif_data_out\(23), + Q => genr_regs(1143), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[27]\(28), + D => \^ipif_data_out\(24), + Q => genr_regs(1144), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][25]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[27]\(28), + D => \^ipif_data_out\(25), + Q => genr_regs(1145), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[27]\(28), + D => \^ipif_data_out\(26), + Q => genr_regs(1146), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[27]\(28), + D => \^ipif_data_out\(27), + Q => genr_regs(1147), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[27]\(28), + D => \^ipif_data_out\(28), + Q => genr_regs(1148), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][2]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[27]\(28), + D => \^ipif_data_out\(2), + Q => genr_regs(1122), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[27]\(28), + D => \^ipif_data_out\(3), + Q => genr_regs(1123), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][4]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[27]\(28), + D => \^ipif_data_out\(4), + Q => genr_regs(1124), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[27]\(28), + D => \^ipif_data_out\(5), + Q => genr_regs(1125), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][6]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[27]\(28), + D => \^ipif_data_out\(6), + Q => genr_regs(1126), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][7]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[27]\(28), + D => \^ipif_data_out\(7), + Q => genr_regs(1127), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[27]\(28), + D => \^ipif_data_out\(8), + Q => genr_regs(1128), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[27][9]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[27]\(28), + D => \^ipif_data_out\(9), + Q => genr_regs(1129), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[28]\(28), + D => \^ipif_data_out\(0), + Q => \time_control_regs2_int[28]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][10]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[28]\(28), + D => \^ipif_data_out\(10), + Q => genr_regs(1162), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[28]\(28), + D => \^ipif_data_out\(11), + Q => genr_regs(1163), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[28]\(28), + D => \^ipif_data_out\(12), + Q => genr_regs(1164), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[28]\(28), + D => \^ipif_data_out\(16), + Q => genr_regs(1168), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[28]\(28), + D => \^ipif_data_out\(17), + Q => genr_regs(1169), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[28]\(28), + D => \^ipif_data_out\(18), + Q => genr_regs(1170), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[28]\(28), + D => \^ipif_data_out\(19), + Q => genr_regs(1171), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[28]\(28), + D => \^ipif_data_out\(1), + Q => genr_regs(1153), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[28]\(28), + D => \^ipif_data_out\(20), + Q => genr_regs(1172), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[28]\(28), + D => \^ipif_data_out\(21), + Q => genr_regs(1173), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[28]\(28), + D => \^ipif_data_out\(22), + Q => genr_regs(1174), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[28]\(28), + D => \^ipif_data_out\(23), + Q => genr_regs(1175), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][24]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[28]\(28), + D => \^ipif_data_out\(24), + Q => genr_regs(1176), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[28]\(28), + D => \^ipif_data_out\(25), + Q => genr_regs(1177), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][26]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[28]\(28), + D => \^ipif_data_out\(26), + Q => genr_regs(1178), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[28]\(28), + D => \^ipif_data_out\(27), + Q => genr_regs(1179), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[28]\(28), + D => \^ipif_data_out\(28), + Q => genr_regs(1180), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[28]\(28), + D => \^ipif_data_out\(2), + Q => genr_regs(1154), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[28]\(28), + D => \^ipif_data_out\(3), + Q => genr_regs(1155), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[28]\(28), + D => \^ipif_data_out\(4), + Q => genr_regs(1156), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[28]\(28), + D => \^ipif_data_out\(5), + Q => genr_regs(1157), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[28]\(28), + D => \^ipif_data_out\(6), + Q => genr_regs(1158), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[28]\(28), + D => \^ipif_data_out\(7), + Q => genr_regs(1159), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][8]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[28]\(28), + D => \^ipif_data_out\(8), + Q => genr_regs(1160), + S => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.time_control_regs_int_reg[28][9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => \time_control_regs_int[28]\(28), + D => \^ipif_data_out\(9), + Q => genr_regs(1161), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.write_ack_d1_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => aclk_en, + D => p_143_out(33), + Q => write_ack_d1, + R => p_0_in_0 + ); +\AXI4_LITE_INTERFACE.write_ack_d2_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => aclk_en, + D => write_ack_d1, + Q => write_ack_d2, + R => p_0_in_0 + ); +\AXI4_LITE_INTERFACE.write_ack_e1_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => vid_aresetn, + O => \AXI4_LITE_INTERFACE.write_ack_e1_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.write_ack_e1_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => p_533_out, + Q => write_ack_e1, + R => \AXI4_LITE_INTERFACE.write_ack_e1_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.write_ack_e2_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => write_ack_e1, + Q => write_ack_e2, + R => \AXI4_LITE_INTERFACE.write_ack_e1_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.write_ack_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => write_ack_e1, + I1 => write_ack_e2, + O => p_534_out + ); +\AXI4_LITE_INTERFACE.write_ack_int_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => write_ack_e2, + I1 => write_ack_e1, + I2 => write_ack, + O => \AXI4_LITE_INTERFACE.write_ack_int_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.write_ack_int_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \AXI4_LITE_INTERFACE.write_ack_int_i_1_n_0\, + Q => write_ack_int, + R => \AXI4_LITE_INTERFACE.write_ack_e1_i_1_n_0\ + ); +\AXI4_LITE_INTERFACE.write_ack_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => p_534_out, + Q => write_ack, + R => \AXI4_LITE_INTERFACE.write_ack_e1_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_err_set_d(0), + I1 => \genr_status_regs[2]\(0), + I2 => vid_aclk_en, + I3 => intr_err(0), + O => \GEN_HAS_IRQ.intr_err[0]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[10]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_err_set_d(10), + I1 => \genr_status_regs[2]\(10), + I2 => vid_aclk_en, + I3 => intr_err(10), + O => \GEN_HAS_IRQ.intr_err[10]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[11]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_err_set_d(11), + I1 => \genr_status_regs[2]\(11), + I2 => vid_aclk_en, + I3 => intr_err(11), + O => \GEN_HAS_IRQ.intr_err[11]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[12]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_err_set_d(12), + I1 => \genr_status_regs[2]\(12), + I2 => vid_aclk_en, + I3 => intr_err(12), + O => \GEN_HAS_IRQ.intr_err[12]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[13]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_err_set_d(13), + I1 => \genr_status_regs[2]\(13), + I2 => vid_aclk_en, + I3 => intr_err(13), + O => \GEN_HAS_IRQ.intr_err[13]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[14]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_err_set_d(14), + I1 => \genr_status_regs[2]\(14), + I2 => vid_aclk_en, + I3 => intr_err(14), + O => \GEN_HAS_IRQ.intr_err[14]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[15]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_err_set_d(15), + I1 => \genr_status_regs[2]\(15), + I2 => vid_aclk_en, + I3 => intr_err(15), + O => \GEN_HAS_IRQ.intr_err[15]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[16]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA00AA000000AA00" + ) + port map ( + I0 => intr_err(16), + I1 => intr_err_set_d(16), + I2 => \genr_status_regs[2]\(16), + I3 => \^resetn_out\, + I4 => vid_aclk_en, + I5 => \GEN_HAS_IRQ.intr_err[16]_i_2_n_0\, + O => \GEN_HAS_IRQ.intr_err[16]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[16]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => intr_err_clr_d(16), + I1 => \^genr_control_regs[2]\(16), + O => \GEN_HAS_IRQ.intr_err[16]_i_2_n_0\ + ); +\GEN_HAS_IRQ.intr_err[17]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA00AA000000AA00" + ) + port map ( + I0 => intr_err(17), + I1 => intr_err_set_d(17), + I2 => \genr_status_regs[2]\(17), + I3 => \^resetn_out\, + I4 => vid_aclk_en, + I5 => \GEN_HAS_IRQ.intr_err[17]_i_2_n_0\, + O => \GEN_HAS_IRQ.intr_err[17]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[17]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => intr_err_clr_d(17), + I1 => \^genr_control_regs[2]\(17), + O => \GEN_HAS_IRQ.intr_err[17]_i_2_n_0\ + ); +\GEN_HAS_IRQ.intr_err[18]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA00AA000000AA00" + ) + port map ( + I0 => intr_err(18), + I1 => intr_err_set_d(18), + I2 => \genr_status_regs[2]\(18), + I3 => \^resetn_out\, + I4 => vid_aclk_en, + I5 => \GEN_HAS_IRQ.intr_err[18]_i_2_n_0\, + O => \GEN_HAS_IRQ.intr_err[18]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[18]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => intr_err_clr_d(18), + I1 => \^genr_control_regs[2]\(18), + O => \GEN_HAS_IRQ.intr_err[18]_i_2_n_0\ + ); +\GEN_HAS_IRQ.intr_err[19]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA00AA000000AA00" + ) + port map ( + I0 => intr_err(19), + I1 => intr_err_set_d(19), + I2 => \genr_status_regs[2]\(19), + I3 => \^resetn_out\, + I4 => vid_aclk_en, + I5 => \GEN_HAS_IRQ.intr_err[19]_i_2_n_0\, + O => \GEN_HAS_IRQ.intr_err[19]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[19]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => intr_err_clr_d(19), + I1 => \^genr_control_regs[2]\(19), + O => \GEN_HAS_IRQ.intr_err[19]_i_2_n_0\ + ); +\GEN_HAS_IRQ.intr_err[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_err_set_d(1), + I1 => \genr_status_regs[2]\(1), + I2 => vid_aclk_en, + I3 => intr_err(1), + O => \GEN_HAS_IRQ.intr_err[1]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[20]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA00AA000000AA00" + ) + port map ( + I0 => intr_err(20), + I1 => intr_err_set_d(20), + I2 => \genr_status_regs[2]\(20), + I3 => \^resetn_out\, + I4 => vid_aclk_en, + I5 => \GEN_HAS_IRQ.intr_err[20]_i_2_n_0\, + O => \GEN_HAS_IRQ.intr_err[20]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[20]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => intr_err_clr_d(20), + I1 => \^genr_control_regs[2]\(20), + O => \GEN_HAS_IRQ.intr_err[20]_i_2_n_0\ + ); +\GEN_HAS_IRQ.intr_err[21]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA00AA000000AA00" + ) + port map ( + I0 => intr_err(21), + I1 => intr_err_set_d(21), + I2 => \genr_status_regs[2]\(21), + I3 => \^resetn_out\, + I4 => vid_aclk_en, + I5 => \GEN_HAS_IRQ.intr_err[21]_i_2_n_0\, + O => \GEN_HAS_IRQ.intr_err[21]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[21]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => intr_err_clr_d(21), + I1 => \^genr_control_regs[2]\(21), + O => \GEN_HAS_IRQ.intr_err[21]_i_2_n_0\ + ); +\GEN_HAS_IRQ.intr_err[22]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_err_set_d(22), + I1 => \genr_status_regs[2]\(22), + I2 => vid_aclk_en, + I3 => intr_err(22), + O => \GEN_HAS_IRQ.intr_err[22]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[23]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_err_set_d(23), + I1 => \genr_status_regs[2]\(23), + I2 => vid_aclk_en, + I3 => intr_err(23), + O => \GEN_HAS_IRQ.intr_err[23]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[24]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_err_set_d(24), + I1 => \genr_status_regs[2]\(24), + I2 => vid_aclk_en, + I3 => intr_err(24), + O => \GEN_HAS_IRQ.intr_err[24]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[25]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_err_set_d(25), + I1 => \genr_status_regs[2]\(25), + I2 => vid_aclk_en, + I3 => intr_err(25), + O => \GEN_HAS_IRQ.intr_err[25]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[26]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_err_set_d(26), + I1 => \genr_status_regs[2]\(26), + I2 => vid_aclk_en, + I3 => intr_err(26), + O => \GEN_HAS_IRQ.intr_err[26]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[27]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_err_set_d(27), + I1 => \genr_status_regs[2]\(27), + I2 => vid_aclk_en, + I3 => intr_err(27), + O => \GEN_HAS_IRQ.intr_err[27]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[28]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_err_set_d(28), + I1 => \genr_status_regs[2]\(28), + I2 => vid_aclk_en, + I3 => intr_err(28), + O => \GEN_HAS_IRQ.intr_err[28]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[29]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_err_set_d(29), + I1 => \genr_status_regs[2]\(29), + I2 => vid_aclk_en, + I3 => intr_err(29), + O => \GEN_HAS_IRQ.intr_err[29]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_err_set_d(2), + I1 => \genr_status_regs[2]\(2), + I2 => vid_aclk_en, + I3 => intr_err(2), + O => \GEN_HAS_IRQ.intr_err[2]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[30]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_err_set_d(30), + I1 => \genr_status_regs[2]\(30), + I2 => vid_aclk_en, + I3 => intr_err(30), + O => \GEN_HAS_IRQ.intr_err[30]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[31]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_err_set_d(31), + I1 => \genr_status_regs[2]\(31), + I2 => vid_aclk_en, + I3 => intr_err(31), + O => \GEN_HAS_IRQ.intr_err[31]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_err_set_d(3), + I1 => \genr_status_regs[2]\(3), + I2 => vid_aclk_en, + I3 => intr_err(3), + O => \GEN_HAS_IRQ.intr_err[3]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_err_set_d(4), + I1 => \genr_status_regs[2]\(4), + I2 => vid_aclk_en, + I3 => intr_err(4), + O => \GEN_HAS_IRQ.intr_err[4]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_err_set_d(5), + I1 => \genr_status_regs[2]\(5), + I2 => vid_aclk_en, + I3 => intr_err(5), + O => \GEN_HAS_IRQ.intr_err[5]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_err_set_d(6), + I1 => \genr_status_regs[2]\(6), + I2 => vid_aclk_en, + I3 => intr_err(6), + O => \GEN_HAS_IRQ.intr_err[6]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[7]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_err_set_d(7), + I1 => \genr_status_regs[2]\(7), + I2 => vid_aclk_en, + I3 => intr_err(7), + O => \GEN_HAS_IRQ.intr_err[7]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[8]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_err_set_d(8), + I1 => \genr_status_regs[2]\(8), + I2 => vid_aclk_en, + I3 => intr_err(8), + O => \GEN_HAS_IRQ.intr_err[8]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err[9]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_err_set_d(9), + I1 => \genr_status_regs[2]\(9), + I2 => vid_aclk_en, + I3 => intr_err(9), + O => \GEN_HAS_IRQ.intr_err[9]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_clr_d_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \^genr_control_regs[2]\(16), + Q => intr_err_clr_d(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_clr_d_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \^genr_control_regs[2]\(17), + Q => intr_err_clr_d(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_clr_d_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \^genr_control_regs[2]\(18), + Q => intr_err_clr_d(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_clr_d_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \^genr_control_regs[2]\(19), + Q => intr_err_clr_d(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_clr_d_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \^genr_control_regs[2]\(20), + Q => intr_err_clr_d(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_clr_d_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \^genr_control_regs[2]\(21), + Q => intr_err_clr_d(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[0]_i_1_n_0\, + Q => intr_err(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[10]_i_1_n_0\, + Q => intr_err(10), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[11]_i_1_n_0\, + Q => intr_err(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[12]_i_1_n_0\, + Q => intr_err(12), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[13]_i_1_n_0\, + Q => intr_err(13), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[14]_i_1_n_0\, + Q => intr_err(14), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[15]_i_1_n_0\, + Q => intr_err(15), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[16]_i_1_n_0\, + Q => intr_err(16), + R => '0' + ); +\GEN_HAS_IRQ.intr_err_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[17]_i_1_n_0\, + Q => intr_err(17), + R => '0' + ); +\GEN_HAS_IRQ.intr_err_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[18]_i_1_n_0\, + Q => intr_err(18), + R => '0' + ); +\GEN_HAS_IRQ.intr_err_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[19]_i_1_n_0\, + Q => intr_err(19), + R => '0' + ); +\GEN_HAS_IRQ.intr_err_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[1]_i_1_n_0\, + Q => intr_err(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[20]_i_1_n_0\, + Q => intr_err(20), + R => '0' + ); +\GEN_HAS_IRQ.intr_err_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[21]_i_1_n_0\, + Q => intr_err(21), + R => '0' + ); +\GEN_HAS_IRQ.intr_err_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[22]_i_1_n_0\, + Q => intr_err(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[23]_i_1_n_0\, + Q => intr_err(23), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[24]_i_1_n_0\, + Q => intr_err(24), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[25]_i_1_n_0\, + Q => intr_err(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[26]_i_1_n_0\, + Q => intr_err(26), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[27]_i_1_n_0\, + Q => intr_err(27), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[28]_i_1_n_0\, + Q => intr_err(28), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[29]_i_1_n_0\, + Q => intr_err(29), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[2]_i_1_n_0\, + Q => intr_err(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[30]_i_1_n_0\, + Q => intr_err(30), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[31]_i_1_n_0\, + Q => intr_err(31), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[3]_i_1_n_0\, + Q => intr_err(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[4]_i_1_n_0\, + Q => intr_err(4), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[5]_i_1_n_0\, + Q => intr_err(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[6]_i_1_n_0\, + Q => intr_err(6), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[7]_i_1_n_0\, + Q => intr_err(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[8]_i_1_n_0\, + Q => intr_err(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_err[9]_i_1_n_0\, + Q => intr_err(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(0), + Q => intr_err_set_d(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(10), + Q => intr_err_set_d(10), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(11), + Q => intr_err_set_d(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(12), + Q => intr_err_set_d(12), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(13), + Q => intr_err_set_d(13), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(14), + Q => intr_err_set_d(14), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(15), + Q => intr_err_set_d(15), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(16), + Q => intr_err_set_d(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(17), + Q => intr_err_set_d(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(18), + Q => intr_err_set_d(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(19), + Q => intr_err_set_d(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(1), + Q => intr_err_set_d(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(20), + Q => intr_err_set_d(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(21), + Q => intr_err_set_d(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(22), + Q => intr_err_set_d(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(23), + Q => intr_err_set_d(23), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(24), + Q => intr_err_set_d(24), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(25), + Q => intr_err_set_d(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(26), + Q => intr_err_set_d(26), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(27), + Q => intr_err_set_d(27), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(28), + Q => intr_err_set_d(28), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(29), + Q => intr_err_set_d(29), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(2), + Q => intr_err_set_d(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(30), + Q => intr_err_set_d(30), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(31), + Q => intr_err_set_d(31), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(3), + Q => intr_err_set_d(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(4), + Q => intr_err_set_d(4), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(5), + Q => intr_err_set_d(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(6), + Q => intr_err_set_d(6), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(7), + Q => intr_err_set_d(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(8), + Q => intr_err_set_d(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_err_set_d_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[2]\(9), + Q => intr_err_set_d(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_stat_set_d(0), + I1 => \genr_status_regs[1]\(0), + I2 => vid_aclk_en, + I3 => \genr_status_regs_int_reg[1]\(0), + O => \GEN_HAS_IRQ.intr_stat[0]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[10]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA00AA000000AA00" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(10), + I1 => intr_stat_set_d(10), + I2 => \genr_status_regs[1]\(10), + I3 => \^resetn_out\, + I4 => vid_aclk_en, + I5 => \GEN_HAS_IRQ.intr_stat[10]_i_2_n_0\, + O => \GEN_HAS_IRQ.intr_stat[10]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[10]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => intr_stat_clr_d(10), + I1 => \^genr_control_regs[1]\(10), + O => \GEN_HAS_IRQ.intr_stat[10]_i_2_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[11]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA00AA000000AA00" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(11), + I1 => intr_stat_set_d(11), + I2 => \genr_status_regs[1]\(11), + I3 => \^resetn_out\, + I4 => vid_aclk_en, + I5 => \GEN_HAS_IRQ.intr_stat[11]_i_2_n_0\, + O => \GEN_HAS_IRQ.intr_stat[11]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[11]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => intr_stat_clr_d(11), + I1 => \^genr_control_regs[1]\(11), + O => \GEN_HAS_IRQ.intr_stat[11]_i_2_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[12]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA00AA000000AA00" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(12), + I1 => intr_stat_set_d(12), + I2 => \genr_status_regs[1]\(12), + I3 => \^resetn_out\, + I4 => vid_aclk_en, + I5 => \GEN_HAS_IRQ.intr_stat[12]_i_2_n_0\, + O => \GEN_HAS_IRQ.intr_stat[12]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[12]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => intr_stat_clr_d(12), + I1 => \^genr_control_regs[1]\(12), + O => \GEN_HAS_IRQ.intr_stat[12]_i_2_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[13]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA00AA000000AA00" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(13), + I1 => intr_stat_set_d(13), + I2 => \genr_status_regs[1]\(13), + I3 => \^resetn_out\, + I4 => vid_aclk_en, + I5 => \GEN_HAS_IRQ.intr_stat[13]_i_2_n_0\, + O => \GEN_HAS_IRQ.intr_stat[13]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[13]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => intr_stat_clr_d(13), + I1 => \^genr_control_regs[1]\(13), + O => \GEN_HAS_IRQ.intr_stat[13]_i_2_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[14]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_stat_set_d(14), + I1 => \genr_status_regs[1]\(14), + I2 => vid_aclk_en, + I3 => \genr_status_regs_int_reg[1]\(14), + O => \GEN_HAS_IRQ.intr_stat[14]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[15]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_stat_set_d(15), + I1 => \genr_status_regs[1]\(15), + I2 => vid_aclk_en, + I3 => \genr_status_regs_int_reg[1]\(15), + O => \GEN_HAS_IRQ.intr_stat[15]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[16]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA00AA000000AA00" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(16), + I1 => intr_stat_set_d(16), + I2 => \genr_status_regs[1]\(16), + I3 => \^resetn_out\, + I4 => vid_aclk_en, + I5 => \GEN_HAS_IRQ.intr_stat[16]_i_2_n_0\, + O => \GEN_HAS_IRQ.intr_stat[16]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[16]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => intr_stat_clr_d(16), + I1 => \^genr_control_regs[1]\(16), + O => \GEN_HAS_IRQ.intr_stat[16]_i_2_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[17]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA00AA000000AA00" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(17), + I1 => intr_stat_set_d(17), + I2 => \genr_status_regs[1]\(17), + I3 => \^resetn_out\, + I4 => vid_aclk_en, + I5 => \GEN_HAS_IRQ.intr_stat[17]_i_2_n_0\, + O => \GEN_HAS_IRQ.intr_stat[17]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[17]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => intr_stat_clr_d(17), + I1 => \^genr_control_regs[1]\(17), + O => \GEN_HAS_IRQ.intr_stat[17]_i_2_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[18]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA00AA000000AA00" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(18), + I1 => intr_stat_set_d(18), + I2 => \genr_status_regs[1]\(18), + I3 => \^resetn_out\, + I4 => vid_aclk_en, + I5 => \GEN_HAS_IRQ.intr_stat[18]_i_2_n_0\, + O => \GEN_HAS_IRQ.intr_stat[18]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[18]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => intr_stat_clr_d(18), + I1 => \^genr_control_regs[1]\(18), + O => \GEN_HAS_IRQ.intr_stat[18]_i_2_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[19]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA00AA000000AA00" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(19), + I1 => intr_stat_set_d(19), + I2 => \genr_status_regs[1]\(19), + I3 => \^resetn_out\, + I4 => vid_aclk_en, + I5 => \GEN_HAS_IRQ.intr_stat[19]_i_2_n_0\, + O => \GEN_HAS_IRQ.intr_stat[19]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[19]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => intr_stat_clr_d(19), + I1 => \^genr_control_regs[1]\(19), + O => \GEN_HAS_IRQ.intr_stat[19]_i_2_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_stat_set_d(1), + I1 => \genr_status_regs[1]\(1), + I2 => vid_aclk_en, + I3 => \genr_status_regs_int_reg[1]\(1), + O => \GEN_HAS_IRQ.intr_stat[1]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[20]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA00AA000000AA00" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(20), + I1 => intr_stat_set_d(20), + I2 => \genr_status_regs[1]\(20), + I3 => \^resetn_out\, + I4 => vid_aclk_en, + I5 => \GEN_HAS_IRQ.intr_stat[20]_i_2_n_0\, + O => \GEN_HAS_IRQ.intr_stat[20]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[20]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => intr_stat_clr_d(20), + I1 => \^genr_control_regs[1]\(20), + O => \GEN_HAS_IRQ.intr_stat[20]_i_2_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[21]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA00AA000000AA00" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(21), + I1 => intr_stat_set_d(21), + I2 => \genr_status_regs[1]\(21), + I3 => \^resetn_out\, + I4 => vid_aclk_en, + I5 => \GEN_HAS_IRQ.intr_stat[21]_i_2_n_0\, + O => \GEN_HAS_IRQ.intr_stat[21]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[21]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => intr_stat_clr_d(21), + I1 => \^genr_control_regs[1]\(21), + O => \GEN_HAS_IRQ.intr_stat[21]_i_2_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[22]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA00AA000000AA00" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(22), + I1 => intr_stat_set_d(22), + I2 => \genr_status_regs[1]\(22), + I3 => \^resetn_out\, + I4 => vid_aclk_en, + I5 => \GEN_HAS_IRQ.intr_stat[22]_i_2_n_0\, + O => \GEN_HAS_IRQ.intr_stat[22]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[22]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => intr_stat_clr_d(22), + I1 => \^genr_control_regs[1]\(22), + O => \GEN_HAS_IRQ.intr_stat[22]_i_2_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[23]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA00AA000000AA00" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(23), + I1 => intr_stat_set_d(23), + I2 => \genr_status_regs[1]\(23), + I3 => \^resetn_out\, + I4 => vid_aclk_en, + I5 => \GEN_HAS_IRQ.intr_stat[23]_i_2_n_0\, + O => \GEN_HAS_IRQ.intr_stat[23]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[23]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => intr_stat_clr_d(23), + I1 => \^genr_control_regs[1]\(23), + O => \GEN_HAS_IRQ.intr_stat[23]_i_2_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[24]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA00AA000000AA00" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(24), + I1 => intr_stat_set_d(24), + I2 => \genr_status_regs[1]\(24), + I3 => \^resetn_out\, + I4 => vid_aclk_en, + I5 => \GEN_HAS_IRQ.intr_stat[24]_i_2_n_0\, + O => \GEN_HAS_IRQ.intr_stat[24]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[24]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => intr_stat_clr_d(24), + I1 => \^genr_control_regs[1]\(24), + O => \GEN_HAS_IRQ.intr_stat[24]_i_2_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[25]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA00AA000000AA00" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(25), + I1 => intr_stat_set_d(25), + I2 => \genr_status_regs[1]\(25), + I3 => \^resetn_out\, + I4 => vid_aclk_en, + I5 => \GEN_HAS_IRQ.intr_stat[25]_i_2_n_0\, + O => \GEN_HAS_IRQ.intr_stat[25]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[25]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => intr_stat_clr_d(25), + I1 => \^genr_control_regs[1]\(25), + O => \GEN_HAS_IRQ.intr_stat[25]_i_2_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[26]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA00AA000000AA00" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(26), + I1 => intr_stat_set_d(26), + I2 => \genr_status_regs[1]\(26), + I3 => \^resetn_out\, + I4 => vid_aclk_en, + I5 => \GEN_HAS_IRQ.intr_stat[26]_i_2_n_0\, + O => \GEN_HAS_IRQ.intr_stat[26]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[26]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => intr_stat_clr_d(26), + I1 => \^genr_control_regs[1]\(26), + O => \GEN_HAS_IRQ.intr_stat[26]_i_2_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[27]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA00AA000000AA00" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(27), + I1 => intr_stat_set_d(27), + I2 => \genr_status_regs[1]\(27), + I3 => \^resetn_out\, + I4 => vid_aclk_en, + I5 => \GEN_HAS_IRQ.intr_stat[27]_i_2_n_0\, + O => \GEN_HAS_IRQ.intr_stat[27]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[27]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => intr_stat_clr_d(27), + I1 => \^genr_control_regs[1]\(27), + O => \GEN_HAS_IRQ.intr_stat[27]_i_2_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[28]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA00AA000000AA00" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(28), + I1 => intr_stat_set_d(28), + I2 => \genr_status_regs[1]\(28), + I3 => \^resetn_out\, + I4 => vid_aclk_en, + I5 => \GEN_HAS_IRQ.intr_stat[28]_i_2_n_0\, + O => \GEN_HAS_IRQ.intr_stat[28]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[28]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => intr_stat_clr_d(28), + I1 => \^genr_control_regs[1]\(28), + O => \GEN_HAS_IRQ.intr_stat[28]_i_2_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[29]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA00AA000000AA00" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(29), + I1 => intr_stat_set_d(29), + I2 => \genr_status_regs[1]\(29), + I3 => \^resetn_out\, + I4 => vid_aclk_en, + I5 => \GEN_HAS_IRQ.intr_stat[29]_i_2_n_0\, + O => \GEN_HAS_IRQ.intr_stat[29]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[29]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => intr_stat_clr_d(29), + I1 => \^genr_control_regs[1]\(29), + O => \GEN_HAS_IRQ.intr_stat[29]_i_2_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_stat_set_d(2), + I1 => \genr_status_regs[1]\(2), + I2 => vid_aclk_en, + I3 => \genr_status_regs_int_reg[1]\(2), + O => \GEN_HAS_IRQ.intr_stat[2]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[30]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA00AA000000AA00" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(30), + I1 => intr_stat_set_d(30), + I2 => \genr_status_regs[1]\(30), + I3 => \^resetn_out\, + I4 => vid_aclk_en, + I5 => \GEN_HAS_IRQ.intr_stat[30]_i_2_n_0\, + O => \GEN_HAS_IRQ.intr_stat[30]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[30]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => intr_stat_clr_d(30), + I1 => \^genr_control_regs[1]\(30), + O => \GEN_HAS_IRQ.intr_stat[30]_i_2_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[31]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA00AA000000AA00" + ) + port map ( + I0 => \GEN_HAS_IRQ.intr_stat_reg_n_0_[31]\, + I1 => intr_stat_set_d(31), + I2 => \genr_status_regs[1]\(31), + I3 => \^resetn_out\, + I4 => vid_aclk_en, + I5 => \GEN_HAS_IRQ.intr_stat[31]_i_2_n_0\, + O => \GEN_HAS_IRQ.intr_stat[31]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[31]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => intr_stat_clr_d(31), + I1 => \^genr_control_regs[1]\(31), + O => \GEN_HAS_IRQ.intr_stat[31]_i_2_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_stat_set_d(3), + I1 => \genr_status_regs[1]\(3), + I2 => vid_aclk_en, + I3 => \genr_status_regs_int_reg[1]\(3), + O => \GEN_HAS_IRQ.intr_stat[3]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_stat_set_d(4), + I1 => \genr_status_regs[1]\(4), + I2 => vid_aclk_en, + I3 => \genr_status_regs_int_reg[1]\(4), + O => \GEN_HAS_IRQ.intr_stat[4]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_stat_set_d(5), + I1 => \genr_status_regs[1]\(5), + I2 => vid_aclk_en, + I3 => \genr_status_regs_int_reg[1]\(5), + O => \GEN_HAS_IRQ.intr_stat[5]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_stat_set_d(6), + I1 => \genr_status_regs[1]\(6), + I2 => vid_aclk_en, + I3 => \genr_status_regs_int_reg[1]\(6), + O => \GEN_HAS_IRQ.intr_stat[6]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[7]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF40" + ) + port map ( + I0 => intr_stat_set_d(7), + I1 => \genr_status_regs[1]\(7), + I2 => vid_aclk_en, + I3 => \genr_status_regs_int_reg[1]\(7), + O => \GEN_HAS_IRQ.intr_stat[7]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[8]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA00AA000000AA00" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(8), + I1 => intr_stat_set_d(8), + I2 => \genr_status_regs[1]\(8), + I3 => \^resetn_out\, + I4 => vid_aclk_en, + I5 => \GEN_HAS_IRQ.intr_stat[8]_i_2_n_0\, + O => \GEN_HAS_IRQ.intr_stat[8]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[8]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => intr_stat_clr_d(8), + I1 => \^genr_control_regs[1]\(8), + O => \GEN_HAS_IRQ.intr_stat[8]_i_2_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[9]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA00AA000000AA00" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(9), + I1 => intr_stat_set_d(9), + I2 => \genr_status_regs[1]\(9), + I3 => \^resetn_out\, + I4 => vid_aclk_en, + I5 => \GEN_HAS_IRQ.intr_stat[9]_i_2_n_0\, + O => \GEN_HAS_IRQ.intr_stat[9]_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat[9]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => intr_stat_clr_d(9), + I1 => \^genr_control_regs[1]\(9), + O => \GEN_HAS_IRQ.intr_stat[9]_i_2_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_clr_d_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \^genr_control_regs[1]\(10), + Q => intr_stat_clr_d(10), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_clr_d_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \^genr_control_regs[1]\(11), + Q => intr_stat_clr_d(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_clr_d_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \^genr_control_regs[1]\(12), + Q => intr_stat_clr_d(12), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_clr_d_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \^genr_control_regs[1]\(13), + Q => intr_stat_clr_d(13), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_clr_d_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \^genr_control_regs[1]\(16), + Q => intr_stat_clr_d(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_clr_d_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \^genr_control_regs[1]\(17), + Q => intr_stat_clr_d(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_clr_d_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \^genr_control_regs[1]\(18), + Q => intr_stat_clr_d(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_clr_d_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \^genr_control_regs[1]\(19), + Q => intr_stat_clr_d(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_clr_d_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \^genr_control_regs[1]\(20), + Q => intr_stat_clr_d(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_clr_d_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \^genr_control_regs[1]\(21), + Q => intr_stat_clr_d(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_clr_d_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \^genr_control_regs[1]\(22), + Q => intr_stat_clr_d(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_clr_d_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \^genr_control_regs[1]\(23), + Q => intr_stat_clr_d(23), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_clr_d_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \^genr_control_regs[1]\(24), + Q => intr_stat_clr_d(24), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_clr_d_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \^genr_control_regs[1]\(25), + Q => intr_stat_clr_d(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_clr_d_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \^genr_control_regs[1]\(26), + Q => intr_stat_clr_d(26), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_clr_d_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \^genr_control_regs[1]\(27), + Q => intr_stat_clr_d(27), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_clr_d_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \^genr_control_regs[1]\(28), + Q => intr_stat_clr_d(28), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_clr_d_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \^genr_control_regs[1]\(29), + Q => intr_stat_clr_d(29), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_clr_d_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \^genr_control_regs[1]\(30), + Q => intr_stat_clr_d(30), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_clr_d_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \^genr_control_regs[1]\(31), + Q => intr_stat_clr_d(31), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_clr_d_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \^genr_control_regs[1]\(8), + Q => intr_stat_clr_d(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_clr_d_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \^genr_control_regs[1]\(9), + Q => intr_stat_clr_d(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[0]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[10]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(10), + R => '0' + ); +\GEN_HAS_IRQ.intr_stat_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[11]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(11), + R => '0' + ); +\GEN_HAS_IRQ.intr_stat_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[12]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(12), + R => '0' + ); +\GEN_HAS_IRQ.intr_stat_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[13]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(13), + R => '0' + ); +\GEN_HAS_IRQ.intr_stat_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[14]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(14), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[15]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(15), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[16]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(16), + R => '0' + ); +\GEN_HAS_IRQ.intr_stat_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[17]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(17), + R => '0' + ); +\GEN_HAS_IRQ.intr_stat_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[18]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(18), + R => '0' + ); +\GEN_HAS_IRQ.intr_stat_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[19]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(19), + R => '0' + ); +\GEN_HAS_IRQ.intr_stat_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[1]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[20]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(20), + R => '0' + ); +\GEN_HAS_IRQ.intr_stat_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[21]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(21), + R => '0' + ); +\GEN_HAS_IRQ.intr_stat_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[22]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(22), + R => '0' + ); +\GEN_HAS_IRQ.intr_stat_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[23]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(23), + R => '0' + ); +\GEN_HAS_IRQ.intr_stat_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[24]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(24), + R => '0' + ); +\GEN_HAS_IRQ.intr_stat_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[25]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(25), + R => '0' + ); +\GEN_HAS_IRQ.intr_stat_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[26]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(26), + R => '0' + ); +\GEN_HAS_IRQ.intr_stat_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[27]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(27), + R => '0' + ); +\GEN_HAS_IRQ.intr_stat_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[28]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(28), + R => '0' + ); +\GEN_HAS_IRQ.intr_stat_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[29]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(29), + R => '0' + ); +\GEN_HAS_IRQ.intr_stat_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[2]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[30]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(30), + R => '0' + ); +\GEN_HAS_IRQ.intr_stat_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[31]_i_1_n_0\, + Q => \GEN_HAS_IRQ.intr_stat_reg_n_0_[31]\, + R => '0' + ); +\GEN_HAS_IRQ.intr_stat_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[3]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[4]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(4), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[5]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[6]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(6), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[7]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[8]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(8), + R => '0' + ); +\GEN_HAS_IRQ.intr_stat_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => '1', + D => \GEN_HAS_IRQ.intr_stat[9]_i_1_n_0\, + Q => \genr_status_regs_int_reg[1]\(9), + R => '0' + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(0), + Q => intr_stat_set_d(0), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(10), + Q => intr_stat_set_d(10), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(11), + Q => intr_stat_set_d(11), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(12), + Q => intr_stat_set_d(12), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(13), + Q => intr_stat_set_d(13), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(14), + Q => intr_stat_set_d(14), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(15), + Q => intr_stat_set_d(15), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(16), + Q => intr_stat_set_d(16), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(17), + Q => intr_stat_set_d(17), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(18), + Q => intr_stat_set_d(18), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(19), + Q => intr_stat_set_d(19), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(1), + Q => intr_stat_set_d(1), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(20), + Q => intr_stat_set_d(20), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(21), + Q => intr_stat_set_d(21), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(22), + Q => intr_stat_set_d(22), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(23), + Q => intr_stat_set_d(23), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(24), + Q => intr_stat_set_d(24), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(25), + Q => intr_stat_set_d(25), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(26), + Q => intr_stat_set_d(26), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(27), + Q => intr_stat_set_d(27), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[28]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(28), + Q => intr_stat_set_d(28), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(29), + Q => intr_stat_set_d(29), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(2), + Q => intr_stat_set_d(2), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[30]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(30), + Q => intr_stat_set_d(30), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(31), + Q => intr_stat_set_d(31), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(3), + Q => intr_stat_set_d(3), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(4), + Q => intr_stat_set_d(4), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(5), + Q => intr_stat_set_d(5), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(6), + Q => intr_stat_set_d(6), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(7), + Q => intr_stat_set_d(7), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(8), + Q => intr_stat_set_d(8), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.intr_stat_set_d_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \genr_status_regs[1]\(9), + Q => intr_stat_set_d(9), + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.irq_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^resetn_out\, + O => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +\GEN_HAS_IRQ.irq_i_10\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(22), + I1 => \^genr_control_regs[3]\(22), + I2 => \genr_status_regs_int_reg[1]\(21), + I3 => \^genr_control_regs[3]\(21), + I4 => \^genr_control_regs[3]\(20), + I5 => \genr_status_regs_int_reg[1]\(20), + O => \GEN_HAS_IRQ.irq_i_10_n_0\ + ); +\GEN_HAS_IRQ.irq_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \GEN_HAS_IRQ.irq_i_3_n_0\, + I1 => \GEN_HAS_IRQ.irq_i_4_n_0\, + I2 => \GEN_HAS_IRQ.irq_i_5_n_0\, + I3 => \GEN_HAS_IRQ.irq_i_6_n_0\, + O => \GEN_HAS_IRQ.irq_i_2_n_0\ + ); +\GEN_HAS_IRQ.irq_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(11), + I1 => \^genr_control_regs[3]\(11), + I2 => \genr_status_regs_int_reg[1]\(10), + I3 => \^genr_control_regs[3]\(10), + I4 => \^genr_control_regs[3]\(9), + I5 => \genr_status_regs_int_reg[1]\(9), + O => \GEN_HAS_IRQ.irq_i_3_n_0\ + ); +\GEN_HAS_IRQ.irq_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(16), + I1 => \^genr_control_regs[3]\(16), + I2 => \genr_status_regs_int_reg[1]\(13), + I3 => \^genr_control_regs[3]\(13), + I4 => \^genr_control_regs[3]\(12), + I5 => \genr_status_regs_int_reg[1]\(12), + O => \GEN_HAS_IRQ.irq_i_4_n_0\ + ); +\GEN_HAS_IRQ.irq_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(19), + I1 => \^genr_control_regs[3]\(19), + I2 => \genr_status_regs_int_reg[1]\(18), + I3 => \^genr_control_regs[3]\(18), + I4 => \^genr_control_regs[3]\(17), + I5 => \genr_status_regs_int_reg[1]\(17), + O => \GEN_HAS_IRQ.irq_i_5_n_0\ + ); +\GEN_HAS_IRQ.irq_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFF8" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(8), + I1 => \^genr_control_regs[3]\(8), + I2 => \GEN_HAS_IRQ.irq_i_7_n_0\, + I3 => \GEN_HAS_IRQ.irq_i_8_n_0\, + I4 => \GEN_HAS_IRQ.irq_i_9_n_0\, + I5 => \GEN_HAS_IRQ.irq_i_10_n_0\, + O => \GEN_HAS_IRQ.irq_i_6_n_0\ + ); +\GEN_HAS_IRQ.irq_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(28), + I1 => \^genr_control_regs[3]\(28), + I2 => \genr_status_regs_int_reg[1]\(27), + I3 => \^genr_control_regs[3]\(27), + I4 => \^genr_control_regs[3]\(26), + I5 => \genr_status_regs_int_reg[1]\(26), + O => \GEN_HAS_IRQ.irq_i_7_n_0\ + ); +\GEN_HAS_IRQ.irq_i_8\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \GEN_HAS_IRQ.intr_stat_reg_n_0_[31]\, + I1 => \^genr_control_regs[3]\(31), + I2 => \genr_status_regs_int_reg[1]\(30), + I3 => \^genr_control_regs[3]\(30), + I4 => \^genr_control_regs[3]\(29), + I5 => \genr_status_regs_int_reg[1]\(29), + O => \GEN_HAS_IRQ.irq_i_8_n_0\ + ); +\GEN_HAS_IRQ.irq_i_9\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF888F888F888" + ) + port map ( + I0 => \genr_status_regs_int_reg[1]\(25), + I1 => \^genr_control_regs[3]\(25), + I2 => \genr_status_regs_int_reg[1]\(24), + I3 => \^genr_control_regs[3]\(24), + I4 => \^genr_control_regs[3]\(23), + I5 => \genr_status_regs_int_reg[1]\(23), + O => \GEN_HAS_IRQ.irq_i_9_n_0\ + ); +\GEN_HAS_IRQ.irq_reg\: unisim.vcomponents.FDRE + port map ( + C => vid_aclk, + CE => vid_aclk_en, + D => \GEN_HAS_IRQ.irq_i_2_n_0\, + Q => irq, + R => \GEN_HAS_IRQ.irq_i_1_n_0\ + ); +GND: unisim.vcomponents.GND + port map ( + G => \\ + ); +ipif_rnw_out_INST_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => write_ack_int, + O => ipif_rnw_out + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_tc_1_0_v_tc is + port ( + s_axi_aclk : in STD_LOGIC; + s_axi_aclken : in STD_LOGIC; + s_axi_aresetn : in STD_LOGIC; + clk : in STD_LOGIC; + clken : in STD_LOGIC; + resetn : in STD_LOGIC; + det_clken : in STD_LOGIC; + gen_clken : in STD_LOGIC; + intc_if : out STD_LOGIC_VECTOR ( 31 downto 0 ); + hsync_in : in STD_LOGIC; + hblank_in : in STD_LOGIC; + vsync_in : in STD_LOGIC; + vblank_in : in STD_LOGIC; + field_id_in : in STD_LOGIC; + active_video_in : in STD_LOGIC; + active_chroma_in : in STD_LOGIC; + fsync_in : in STD_LOGIC; + fsync_out : out STD_LOGIC_VECTOR ( 0 to 0 ); + hsync_out : out STD_LOGIC; + hblank_out : out STD_LOGIC; + vsync_out : out STD_LOGIC; + vblank_out : out STD_LOGIC; + field_id_out : out STD_LOGIC; + active_video_out : out STD_LOGIC; + active_chroma_out : out STD_LOGIC; + s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_arvalid : in STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rvalid : out STD_LOGIC; + s_axi_rready : in STD_LOGIC; + irq : out STD_LOGIC + ); + attribute C_CONTROL : integer; + attribute C_CONTROL of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_DETECT_EN : integer; + attribute C_DETECT_EN of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1; + attribute C_DET_ACHROMA_EN : integer; + attribute C_DET_ACHROMA_EN of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_DET_AVIDEO_EN : integer; + attribute C_DET_AVIDEO_EN of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1; + attribute C_DET_FIELDID_EN : integer; + attribute C_DET_FIELDID_EN of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_DET_HBLANK_EN : integer; + attribute C_DET_HBLANK_EN of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_DET_HSYNC_EN : integer; + attribute C_DET_HSYNC_EN of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1; + attribute C_DET_VBLANK_EN : integer; + attribute C_DET_VBLANK_EN of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_DET_VSYNC_EN : integer; + attribute C_DET_VSYNC_EN of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1; + attribute C_FAMILY : string; + attribute C_FAMILY of Arty_Z7_20_v_tc_1_0_v_tc : entity is "virtex5"; + attribute C_FSYNC_HSTART0 : integer; + attribute C_FSYNC_HSTART0 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_HSTART1 : integer; + attribute C_FSYNC_HSTART1 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_HSTART10 : integer; + attribute C_FSYNC_HSTART10 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_HSTART11 : integer; + attribute C_FSYNC_HSTART11 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_HSTART12 : integer; + attribute C_FSYNC_HSTART12 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_HSTART13 : integer; + attribute C_FSYNC_HSTART13 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_HSTART14 : integer; + attribute C_FSYNC_HSTART14 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_HSTART15 : integer; + attribute C_FSYNC_HSTART15 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_HSTART2 : integer; + attribute C_FSYNC_HSTART2 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_HSTART3 : integer; + attribute C_FSYNC_HSTART3 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_HSTART4 : integer; + attribute C_FSYNC_HSTART4 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_HSTART5 : integer; + attribute C_FSYNC_HSTART5 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_HSTART6 : integer; + attribute C_FSYNC_HSTART6 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_HSTART7 : integer; + attribute C_FSYNC_HSTART7 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_HSTART8 : integer; + attribute C_FSYNC_HSTART8 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_HSTART9 : integer; + attribute C_FSYNC_HSTART9 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_VSTART0 : integer; + attribute C_FSYNC_VSTART0 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_VSTART1 : integer; + attribute C_FSYNC_VSTART1 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_VSTART10 : integer; + attribute C_FSYNC_VSTART10 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_VSTART11 : integer; + attribute C_FSYNC_VSTART11 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_VSTART12 : integer; + attribute C_FSYNC_VSTART12 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_VSTART13 : integer; + attribute C_FSYNC_VSTART13 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_VSTART14 : integer; + attribute C_FSYNC_VSTART14 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_VSTART15 : integer; + attribute C_FSYNC_VSTART15 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_VSTART2 : integer; + attribute C_FSYNC_VSTART2 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_VSTART3 : integer; + attribute C_FSYNC_VSTART3 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_VSTART4 : integer; + attribute C_FSYNC_VSTART4 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_VSTART5 : integer; + attribute C_FSYNC_VSTART5 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_VSTART6 : integer; + attribute C_FSYNC_VSTART6 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_VSTART7 : integer; + attribute C_FSYNC_VSTART7 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_VSTART8 : integer; + attribute C_FSYNC_VSTART8 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_FSYNC_VSTART9 : integer; + attribute C_FSYNC_VSTART9 of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_GENERATE_EN : integer; + attribute C_GENERATE_EN of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_GEN_ACHROMA_EN : integer; + attribute C_GEN_ACHROMA_EN of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_GEN_ACHROMA_POLARITY : integer; + attribute C_GEN_ACHROMA_POLARITY of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1; + attribute C_GEN_AUTO_SWITCH : integer; + attribute C_GEN_AUTO_SWITCH of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_GEN_AVIDEO_EN : integer; + attribute C_GEN_AVIDEO_EN of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1; + attribute C_GEN_AVIDEO_POLARITY : integer; + attribute C_GEN_AVIDEO_POLARITY of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1; + attribute C_GEN_CPARITY : integer; + attribute C_GEN_CPARITY of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_GEN_F0_VBLANK_HEND : integer; + attribute C_GEN_F0_VBLANK_HEND of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1280; + attribute C_GEN_F0_VBLANK_HSTART : integer; + attribute C_GEN_F0_VBLANK_HSTART of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1280; + attribute C_GEN_F0_VFRAME_SIZE : integer; + attribute C_GEN_F0_VFRAME_SIZE of Arty_Z7_20_v_tc_1_0_v_tc : entity is 750; + attribute C_GEN_F0_VSYNC_HEND : integer; + attribute C_GEN_F0_VSYNC_HEND of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1280; + attribute C_GEN_F0_VSYNC_HSTART : integer; + attribute C_GEN_F0_VSYNC_HSTART of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1280; + attribute C_GEN_F0_VSYNC_VEND : integer; + attribute C_GEN_F0_VSYNC_VEND of Arty_Z7_20_v_tc_1_0_v_tc : entity is 729; + attribute C_GEN_F0_VSYNC_VSTART : integer; + attribute C_GEN_F0_VSYNC_VSTART of Arty_Z7_20_v_tc_1_0_v_tc : entity is 724; + attribute C_GEN_F1_VBLANK_HEND : integer; + attribute C_GEN_F1_VBLANK_HEND of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1280; + attribute C_GEN_F1_VBLANK_HSTART : integer; + attribute C_GEN_F1_VBLANK_HSTART of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1280; + attribute C_GEN_F1_VFRAME_SIZE : integer; + attribute C_GEN_F1_VFRAME_SIZE of Arty_Z7_20_v_tc_1_0_v_tc : entity is 750; + attribute C_GEN_F1_VSYNC_HEND : integer; + attribute C_GEN_F1_VSYNC_HEND of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1280; + attribute C_GEN_F1_VSYNC_HSTART : integer; + attribute C_GEN_F1_VSYNC_HSTART of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1280; + attribute C_GEN_F1_VSYNC_VEND : integer; + attribute C_GEN_F1_VSYNC_VEND of Arty_Z7_20_v_tc_1_0_v_tc : entity is 729; + attribute C_GEN_F1_VSYNC_VSTART : integer; + attribute C_GEN_F1_VSYNC_VSTART of Arty_Z7_20_v_tc_1_0_v_tc : entity is 724; + attribute C_GEN_FIELDID_EN : integer; + attribute C_GEN_FIELDID_EN of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_GEN_FIELDID_POLARITY : integer; + attribute C_GEN_FIELDID_POLARITY of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1; + attribute C_GEN_HACTIVE_SIZE : integer; + attribute C_GEN_HACTIVE_SIZE of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1280; + attribute C_GEN_HBLANK_EN : integer; + attribute C_GEN_HBLANK_EN of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1; + attribute C_GEN_HBLANK_POLARITY : integer; + attribute C_GEN_HBLANK_POLARITY of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1; + attribute C_GEN_HFRAME_SIZE : integer; + attribute C_GEN_HFRAME_SIZE of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1650; + attribute C_GEN_HSYNC_EN : integer; + attribute C_GEN_HSYNC_EN of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1; + attribute C_GEN_HSYNC_END : integer; + attribute C_GEN_HSYNC_END of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1430; + attribute C_GEN_HSYNC_POLARITY : integer; + attribute C_GEN_HSYNC_POLARITY of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1; + attribute C_GEN_HSYNC_START : integer; + attribute C_GEN_HSYNC_START of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1390; + attribute C_GEN_INTERLACED : integer; + attribute C_GEN_INTERLACED of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_GEN_VACTIVE_SIZE : integer; + attribute C_GEN_VACTIVE_SIZE of Arty_Z7_20_v_tc_1_0_v_tc : entity is 720; + attribute C_GEN_VBLANK_EN : integer; + attribute C_GEN_VBLANK_EN of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1; + attribute C_GEN_VBLANK_POLARITY : integer; + attribute C_GEN_VBLANK_POLARITY of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1; + attribute C_GEN_VIDEO_FORMAT : integer; + attribute C_GEN_VIDEO_FORMAT of Arty_Z7_20_v_tc_1_0_v_tc : entity is 2; + attribute C_GEN_VSYNC_EN : integer; + attribute C_GEN_VSYNC_EN of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1; + attribute C_GEN_VSYNC_POLARITY : integer; + attribute C_GEN_VSYNC_POLARITY of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1; + attribute C_HAS_AXI4_LITE : integer; + attribute C_HAS_AXI4_LITE of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1; + attribute C_HAS_INTC_IF : integer; + attribute C_HAS_INTC_IF of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1; + attribute C_INTERLACE_EN : integer; + attribute C_INTERLACE_EN of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_IRQEN : integer; + attribute C_IRQEN of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_LINE_DELAY : integer; + attribute C_LINE_DELAY of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_MAX_LINES : integer; + attribute C_MAX_LINES of Arty_Z7_20_v_tc_1_0_v_tc : entity is 2048; + attribute C_MAX_PIXELS : integer; + attribute C_MAX_PIXELS of Arty_Z7_20_v_tc_1_0_v_tc : entity is 4096; + attribute C_NUM_FSYNCS : integer; + attribute C_NUM_FSYNCS of Arty_Z7_20_v_tc_1_0_v_tc : entity is 1; + attribute C_PIXEL_DELAY : integer; + attribute C_PIXEL_DELAY of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_SYNC_EN : integer; + attribute C_SYNC_EN of Arty_Z7_20_v_tc_1_0_v_tc : entity is 0; + attribute C_S_AXI_ADDR_WIDTH : integer; + attribute C_S_AXI_ADDR_WIDTH of Arty_Z7_20_v_tc_1_0_v_tc : entity is 9; + attribute C_S_AXI_CLK_FREQ_HZ : integer; + attribute C_S_AXI_CLK_FREQ_HZ of Arty_Z7_20_v_tc_1_0_v_tc : entity is 100000000; + attribute C_S_AXI_DATA_WIDTH : integer; + attribute C_S_AXI_DATA_WIDTH of Arty_Z7_20_v_tc_1_0_v_tc : entity is 32; + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_tc_1_0_v_tc : entity is "v_tc"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of Arty_Z7_20_v_tc_1_0_v_tc : entity is "yes"; +end Arty_Z7_20_v_tc_1_0_v_tc; + +architecture STRUCTURE of Arty_Z7_20_v_tc_1_0_v_tc is + signal \\ : STD_LOGIC; + signal U_VIDEO_CTRL_n_1022 : STD_LOGIC; + signal U_VIDEO_CTRL_n_1023 : STD_LOGIC; + signal U_VIDEO_CTRL_n_1024 : STD_LOGIC; + signal U_VIDEO_CTRL_n_1025 : STD_LOGIC; + signal U_VIDEO_CTRL_n_1054 : STD_LOGIC; + signal U_VIDEO_CTRL_n_1055 : STD_LOGIC; + signal U_VIDEO_CTRL_n_1056 : STD_LOGIC; + signal U_VIDEO_CTRL_n_1057 : STD_LOGIC; + signal U_VIDEO_CTRL_n_1086 : STD_LOGIC; + signal U_VIDEO_CTRL_n_1087 : STD_LOGIC; + signal U_VIDEO_CTRL_n_1088 : STD_LOGIC; + signal U_VIDEO_CTRL_n_1089 : STD_LOGIC; + signal U_VIDEO_CTRL_n_1090 : STD_LOGIC; + signal U_VIDEO_CTRL_n_1118 : STD_LOGIC; + signal U_VIDEO_CTRL_n_1119 : STD_LOGIC; + signal U_VIDEO_CTRL_n_1120 : STD_LOGIC; + signal U_VIDEO_CTRL_n_1121 : STD_LOGIC; + signal U_VIDEO_CTRL_n_1150 : STD_LOGIC; + signal U_VIDEO_CTRL_n_1151 : STD_LOGIC; + signal U_VIDEO_CTRL_n_1152 : STD_LOGIC; + signal U_VIDEO_CTRL_n_1153 : STD_LOGIC; + signal U_VIDEO_CTRL_n_1662 : STD_LOGIC; + signal U_VIDEO_CTRL_n_1663 : STD_LOGIC; + signal U_VIDEO_CTRL_n_1664 : STD_LOGIC; + signal U_VIDEO_CTRL_n_1665 : STD_LOGIC; + signal U_VIDEO_CTRL_n_734 : STD_LOGIC; + signal U_VIDEO_CTRL_n_735 : STD_LOGIC; + signal U_VIDEO_CTRL_n_736 : STD_LOGIC; + signal U_VIDEO_CTRL_n_737 : STD_LOGIC; + signal U_VIDEO_CTRL_n_806 : STD_LOGIC; + signal U_VIDEO_CTRL_n_808 : STD_LOGIC; + signal U_VIDEO_CTRL_n_809 : STD_LOGIC; + signal U_VIDEO_CTRL_n_810 : STD_LOGIC; + signal U_VIDEO_CTRL_n_811 : STD_LOGIC; + signal U_VIDEO_CTRL_n_894 : STD_LOGIC; + signal U_VIDEO_CTRL_n_895 : STD_LOGIC; + signal U_VIDEO_CTRL_n_896 : STD_LOGIC; + signal U_VIDEO_CTRL_n_897 : STD_LOGIC; + signal U_VIDEO_CTRL_n_898 : STD_LOGIC; + signal U_VIDEO_CTRL_n_926 : STD_LOGIC; + signal U_VIDEO_CTRL_n_927 : STD_LOGIC; + signal U_VIDEO_CTRL_n_928 : STD_LOGIC; + signal U_VIDEO_CTRL_n_929 : STD_LOGIC; + signal U_VIDEO_CTRL_n_958 : STD_LOGIC; + signal U_VIDEO_CTRL_n_959 : STD_LOGIC; + signal U_VIDEO_CTRL_n_960 : STD_LOGIC; + signal U_VIDEO_CTRL_n_961 : STD_LOGIC; + signal U_VIDEO_CTRL_n_990 : STD_LOGIC; + signal U_VIDEO_CTRL_n_991 : STD_LOGIC; + signal U_VIDEO_CTRL_n_992 : STD_LOGIC; + signal U_VIDEO_CTRL_n_993 : STD_LOGIC; + signal U_VIDEO_CTRL_n_994 : STD_LOGIC; + signal \core_control_regs[0]\ : STD_LOGIC_VECTOR ( 26 downto 0 ); + signal \core_control_regs[16]\ : STD_LOGIC_VECTOR ( 26 downto 0 ); + signal core_d : STD_LOGIC; + signal gen_v0chroma_start : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \gen_v0chroma_start[0]_i_1_n_0\ : STD_LOGIC; + signal \genr_control_regs[0]\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \^intc_if\ : STD_LOGIC_VECTOR ( 12 downto 2 ); + signal reg_update : STD_LOGIC; + signal \time_control_regs[16]\ : STD_LOGIC_VECTOR ( 26 downto 0 ); + signal \time_control_regs[18]\ : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal \time_control_regs[19]\ : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal \time_control_regs[20]\ : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \time_control_regs[21]\ : STD_LOGIC_VECTOR ( 26 downto 0 ); + signal \time_control_regs[22]\ : STD_LOGIC_VECTOR ( 27 downto 0 ); + signal \time_control_regs[23]\ : STD_LOGIC_VECTOR ( 27 downto 0 ); + signal \time_control_regs[24]\ : STD_LOGIC_VECTOR ( 26 downto 0 ); + signal \time_control_regs[25]\ : STD_LOGIC_VECTOR ( 27 downto 0 ); + signal \time_control_regs[26]\ : STD_LOGIC_VECTOR ( 27 downto 0 ); + signal \time_control_regs[27]\ : STD_LOGIC_VECTOR ( 26 downto 0 ); + signal \time_control_regs[28]\ : STD_LOGIC_VECTOR ( 27 downto 0 ); + signal \time_status_regs_int_reg[0]\ : STD_LOGIC_VECTOR ( 26 downto 0 ); + signal \time_status_regs_int_reg[3]\ : STD_LOGIC_VECTOR ( 4 downto 2 ); + signal \time_status_regs_int_reg[4]\ : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \time_status_regs_int_reg[5]\ : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal \time_status_regs_int_reg[6]\ : STD_LOGIC_VECTOR ( 27 downto 0 ); + signal \time_status_regs_int_reg[7]\ : STD_LOGIC_VECTOR ( 27 downto 0 ); + signal \time_status_regs_int_reg[8]\ : STD_LOGIC_VECTOR ( 26 downto 0 ); + signal \time_status_regs_int_reg[9]\ : STD_LOGIC_VECTOR ( 27 downto 0 ); + signal vresetn : STD_LOGIC; + attribute MAX_FANOUT : string; + attribute MAX_FANOUT of vresetn : signal is "128"; + attribute RTL_MAX_FANOUT : string; + attribute RTL_MAX_FANOUT of vresetn : signal is "found"; + signal NLW_U_VIDEO_CTRL_ipif_cs_out_UNCONNECTED : STD_LOGIC; + signal NLW_U_VIDEO_CTRL_ipif_rnw_out_UNCONNECTED : STD_LOGIC; + signal \NLW_U_VIDEO_CTRL_core_control_regs[0]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 27 ); + signal \NLW_U_VIDEO_CTRL_core_control_regs[10]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_core_control_regs[11]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_core_control_regs[12]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_core_control_regs[13]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_core_control_regs[14]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_core_control_regs[15]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_core_control_regs[16]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 27 ); + signal \NLW_U_VIDEO_CTRL_core_control_regs[1]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_core_control_regs[2]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_core_control_regs[3]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_core_control_regs[4]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_core_control_regs[5]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_core_control_regs[6]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_core_control_regs[7]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_core_control_regs[8]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_core_control_regs[9]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_genr_control_regs[1]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_genr_control_regs[2]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_genr_control_regs[3]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_genr_control_regs[4]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_U_VIDEO_CTRL_ipif_addr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal NLW_U_VIDEO_CTRL_ipif_data_out_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[0]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[10]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[11]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[12]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[13]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[14]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[15]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[16]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 27 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[17]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[18]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 10 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[19]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 7 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[1]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[20]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 12 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[21]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 27 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[22]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 28 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[23]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 28 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[24]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 27 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[25]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 28 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[26]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 28 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[27]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 27 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[28]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 28 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[2]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[3]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[4]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[5]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[6]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[7]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[8]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_U_VIDEO_CTRL_time_control_regs[9]_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + attribute C_COREGEN_PATCH : integer; + attribute C_COREGEN_PATCH of U_VIDEO_CTRL : label is 0; + attribute C_CORE_AXI_WRITE : string; + attribute C_CORE_AXI_WRITE of U_VIDEO_CTRL : label is "544'b0000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111"; + attribute C_CORE_DBUFFER : string; + attribute C_CORE_DBUFFER of U_VIDEO_CTRL : label is "544'b0000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000111111111110000111111111111000001111111111100001111111111110000011111111111000011111111111100000000000000000000000000000000"; + attribute C_CORE_DEFAULT : string; + attribute C_CORE_DEFAULT of U_VIDEO_CTRL : label is "544'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute C_CORE_NUM_REGS : integer; + attribute C_CORE_NUM_REGS of U_VIDEO_CTRL : label is 17; + attribute C_FAMILY of U_VIDEO_CTRL : label is "virtex5"; + attribute C_GENR_AXI_WRITE : string; + attribute C_GENR_AXI_WRITE of U_VIDEO_CTRL : label is "160'b1100011111111111111011110010111111111111111111110011111100000000000000000011111100000000000000001111111111111111001111110000000000000000000000000000000000000000"; + attribute C_GENR_DBUFFER : string; + attribute C_GENR_DBUFFER of U_VIDEO_CTRL : label is "160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute C_GENR_DEFAULT : string; + attribute C_GENR_DEFAULT of U_VIDEO_CTRL : label is "160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute C_GENR_NUM_REGS : integer; + attribute C_GENR_NUM_REGS of U_VIDEO_CTRL : label is 5; + attribute C_GENR_SELFCLR : string; + attribute C_GENR_SELFCLR of U_VIDEO_CTRL : label is "256'b0000000000000000000000000000000011111111111111111111111111111111111111111111111111111111111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute C_HAS_AXI4_LITE of U_VIDEO_CTRL : label is 1; + attribute C_HAS_IRQ : integer; + attribute C_HAS_IRQ of U_VIDEO_CTRL : label is 1; + attribute C_IS_EVAL : string; + attribute C_IS_EVAL of U_VIDEO_CTRL : label is "FALSE"; + attribute C_REVISION_NUMBER : integer; + attribute C_REVISION_NUMBER of U_VIDEO_CTRL : label is 11; + attribute C_SRESET_LENGTH : integer; + attribute C_SRESET_LENGTH of U_VIDEO_CTRL : label is 2; + attribute C_S_AXI_ADDR_WIDTH of U_VIDEO_CTRL : label is 9; + attribute C_S_AXI_DATA_WIDTH of U_VIDEO_CTRL : label is 32; + attribute C_TIMEOUT_HOURS : integer; + attribute C_TIMEOUT_HOURS of U_VIDEO_CTRL : label is 8; + attribute C_TIMEOUT_MINS : integer; + attribute C_TIMEOUT_MINS of U_VIDEO_CTRL : label is 0; + attribute C_TIME_AXI_WRITE : string; + attribute C_TIME_AXI_WRITE of U_VIDEO_CTRL : label is "928'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111111110001111111111111000000000000000000000000000000000000000000000000000000111100111100000000000000000000000001111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111"; + attribute C_TIME_DBUFFER : string; + attribute C_TIME_DBUFFER of U_VIDEO_CTRL : label is "928'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111111110001111111111111000000000000000000000000000000000000000000000000000000111000000000000000000000000000000000111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111000111111111111100011111111111110001111111111111"; + attribute C_TIME_DEFAULT : string; + attribute C_TIME_DEFAULT of U_VIDEO_CTRL : label is "928'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010110100000000010100000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000001111111000000000000000000000110011100100000001011101110000000101110111000000101100101100000010101101110000001010000000000000101000000000000001011011001000000101101010000000101000000000000010100000000000001010000000000000101000000000000001011011001000000101101010000000101000000000000010100000000"; + attribute C_TIME_NUM_REGS : integer; + attribute C_TIME_NUM_REGS of U_VIDEO_CTRL : label is 29; + attribute C_VERSION_MAJOR : integer; + attribute C_VERSION_MAJOR of U_VIDEO_CTRL : label is 6; + attribute C_VERSION_MINOR : integer; + attribute C_VERSION_MINOR of U_VIDEO_CTRL : label is 1; + attribute C_VERSION_REVISION : integer; + attribute C_VERSION_REVISION of U_VIDEO_CTRL : label is 0; + attribute downgradeipidentifiedwarnings of U_VIDEO_CTRL : label is "yes"; +begin + active_chroma_out <= \\; + active_video_out <= \\; + field_id_out <= \\; + fsync_out(0) <= \\; + hblank_out <= \\; + hsync_out <= \\; + intc_if(31) <= \\; + intc_if(30) <= \\; + intc_if(29) <= \\; + intc_if(28) <= \\; + intc_if(27) <= \\; + intc_if(26) <= \\; + intc_if(25) <= \\; + intc_if(24) <= \\; + intc_if(23) <= \\; + intc_if(22) <= \\; + intc_if(21) <= \\; + intc_if(20) <= \\; + intc_if(19) <= \\; + intc_if(18) <= \\; + intc_if(17) <= \\; + intc_if(16) <= \\; + intc_if(15) <= \\; + intc_if(14) <= \\; + intc_if(13) <= \\; + intc_if(12 downto 8) <= \^intc_if\(12 downto 8); + intc_if(7) <= \\; + intc_if(6) <= \^intc_if\(5); + intc_if(5 downto 2) <= \^intc_if\(5 downto 2); + intc_if(1) <= \^intc_if\(5); + intc_if(0) <= \^intc_if\(5); + vblank_out <= \\; + vsync_out <= \\; +GND: unisim.vcomponents.GND + port map ( + G => \\ + ); +U_TC_TOP: entity work.Arty_Z7_20_v_tc_1_0_tc_top + port map ( + \GEN_TREE.GEN_BRANCH[37].GEN_MUX_REG.data_out_reg_reg[37][10]\(10 downto 0) => \time_status_regs_int_reg[5]\(10 downto 0), + Q(11 downto 0) => \time_status_regs_int_reg[4]\(11 downto 0), + active_video_in => active_video_in, + clk => clk, + clken => clken, + core_d_out => core_d, + det_clken => det_clken, + \genr_control_regs[0]\(2 downto 1) => \genr_control_regs[0]\(3 downto 2), + \genr_control_regs[0]\(0) => \genr_control_regs[0]\(0), + hsync_in => hsync_in, + intc_if(8 downto 4) => \^intc_if\(12 downto 8), + intc_if(3 downto 0) => \^intc_if\(5 downto 2), + resetn_out => vresetn, + \time_control_regs[19]\(0) => \time_control_regs[19]\(0), + \time_status_regs[3]\(2 downto 0) => \time_status_regs_int_reg[3]\(4 downto 2), + \time_status_regs[6]\(23 downto 12) => \time_status_regs_int_reg[6]\(27 downto 16), + \time_status_regs[6]\(11 downto 0) => \time_status_regs_int_reg[6]\(11 downto 0), + \time_status_regs[7]\(23 downto 12) => \time_status_regs_int_reg[7]\(27 downto 16), + \time_status_regs[7]\(11 downto 0) => \time_status_regs_int_reg[7]\(11 downto 0), + \time_status_regs[8]\(21 downto 11) => \time_status_regs_int_reg[8]\(26 downto 16), + \time_status_regs[8]\(10 downto 0) => \time_status_regs_int_reg[8]\(10 downto 0), + \time_status_regs[9]\(23 downto 12) => \time_status_regs_int_reg[9]\(27 downto 16), + \time_status_regs[9]\(11 downto 0) => \time_status_regs_int_reg[9]\(11 downto 0), + \time_status_regs_int_reg[0]\(22 downto 12) => \time_status_regs_int_reg[0]\(26 downto 16), + \time_status_regs_int_reg[0]\(11 downto 0) => \time_status_regs_int_reg[0]\(11 downto 0), + vblank_in => vblank_in, + vsync_in => vsync_in + ); +U_VIDEO_CTRL: entity work.Arty_Z7_20_v_tc_1_0_video_ctrl + port map ( + aclk => s_axi_aclk, + aclk_en => s_axi_aclken, + aresetn => s_axi_aresetn, + \core_control_regs[0]\(31 downto 27) => \NLW_U_VIDEO_CTRL_core_control_regs[0]_UNCONNECTED\(31 downto 27), + \core_control_regs[0]\(26 downto 16) => \core_control_regs[0]\(26 downto 16), + \core_control_regs[0]\(15) => U_VIDEO_CTRL_n_1150, + \core_control_regs[0]\(14) => U_VIDEO_CTRL_n_1151, + \core_control_regs[0]\(13) => U_VIDEO_CTRL_n_1152, + \core_control_regs[0]\(12) => U_VIDEO_CTRL_n_1153, + \core_control_regs[0]\(11 downto 0) => \core_control_regs[0]\(11 downto 0), + \core_control_regs[10]\(31 downto 0) => \NLW_U_VIDEO_CTRL_core_control_regs[10]_UNCONNECTED\(31 downto 0), + \core_control_regs[11]\(31 downto 0) => \NLW_U_VIDEO_CTRL_core_control_regs[11]_UNCONNECTED\(31 downto 0), + \core_control_regs[12]\(31 downto 0) => \NLW_U_VIDEO_CTRL_core_control_regs[12]_UNCONNECTED\(31 downto 0), + \core_control_regs[13]\(31 downto 0) => \NLW_U_VIDEO_CTRL_core_control_regs[13]_UNCONNECTED\(31 downto 0), + \core_control_regs[14]\(31 downto 0) => \NLW_U_VIDEO_CTRL_core_control_regs[14]_UNCONNECTED\(31 downto 0), + \core_control_regs[15]\(31 downto 0) => \NLW_U_VIDEO_CTRL_core_control_regs[15]_UNCONNECTED\(31 downto 0), + \core_control_regs[16]\(31 downto 27) => \NLW_U_VIDEO_CTRL_core_control_regs[16]_UNCONNECTED\(31 downto 27), + \core_control_regs[16]\(26 downto 16) => \core_control_regs[16]\(26 downto 16), + \core_control_regs[16]\(15) => U_VIDEO_CTRL_n_1662, + \core_control_regs[16]\(14) => U_VIDEO_CTRL_n_1663, + \core_control_regs[16]\(13) => U_VIDEO_CTRL_n_1664, + \core_control_regs[16]\(12) => U_VIDEO_CTRL_n_1665, + \core_control_regs[16]\(11 downto 0) => \core_control_regs[16]\(11 downto 0), + \core_control_regs[1]\(31 downto 0) => \NLW_U_VIDEO_CTRL_core_control_regs[1]_UNCONNECTED\(31 downto 0), + \core_control_regs[2]\(31 downto 0) => \NLW_U_VIDEO_CTRL_core_control_regs[2]_UNCONNECTED\(31 downto 0), + \core_control_regs[3]\(31 downto 0) => \NLW_U_VIDEO_CTRL_core_control_regs[3]_UNCONNECTED\(31 downto 0), + \core_control_regs[4]\(31 downto 0) => \NLW_U_VIDEO_CTRL_core_control_regs[4]_UNCONNECTED\(31 downto 0), + \core_control_regs[5]\(31 downto 0) => \NLW_U_VIDEO_CTRL_core_control_regs[5]_UNCONNECTED\(31 downto 0), + \core_control_regs[6]\(31 downto 0) => \NLW_U_VIDEO_CTRL_core_control_regs[6]_UNCONNECTED\(31 downto 0), + \core_control_regs[7]\(31 downto 0) => \NLW_U_VIDEO_CTRL_core_control_regs[7]_UNCONNECTED\(31 downto 0), + \core_control_regs[8]\(31 downto 0) => \NLW_U_VIDEO_CTRL_core_control_regs[8]_UNCONNECTED\(31 downto 0), + \core_control_regs[9]\(31 downto 0) => \NLW_U_VIDEO_CTRL_core_control_regs[9]_UNCONNECTED\(31 downto 0), + core_d_out => core_d, + \core_status_regs[0]\(31 downto 0) => B"00000000000000000000000000000000", + \core_status_regs[10]\(31 downto 0) => B"00000000000000000000000000000000", + \core_status_regs[11]\(31 downto 0) => B"00000000000000000000000000000000", + \core_status_regs[12]\(31 downto 0) => B"00000000000000000000000000000000", + \core_status_regs[13]\(31 downto 0) => B"00000000000000000000000000000000", + \core_status_regs[14]\(31 downto 0) => B"00000000000000000000000000000000", + \core_status_regs[15]\(31 downto 0) => B"00000000000000000000000000000000", + \core_status_regs[16]\(31 downto 0) => B"00000000000000000000000000000000", + \core_status_regs[1]\(31 downto 0) => B"00000000000000000000000000000000", + \core_status_regs[2]\(31 downto 0) => B"00000000000000000000000000000000", + \core_status_regs[3]\(31 downto 0) => B"00000000000000000000000000000000", + \core_status_regs[4]\(31 downto 0) => B"00000000000000000000000000000000", + \core_status_regs[5]\(31 downto 0) => B"00000000000000000000000000000000", + \core_status_regs[6]\(31 downto 0) => B"00000000000000000000000000000000", + \core_status_regs[7]\(31 downto 0) => B"00000000000000000000000000000000", + \core_status_regs[8]\(31 downto 0) => B"00000000000000000000000000000000", + \core_status_regs[9]\(31 downto 0) => B"00000000000000000000000000000000", + \genr_control_regs[0]\(31 downto 0) => \genr_control_regs[0]\(31 downto 0), + \genr_control_regs[1]\(31 downto 0) => \NLW_U_VIDEO_CTRL_genr_control_regs[1]_UNCONNECTED\(31 downto 0), + \genr_control_regs[2]\(31 downto 0) => \NLW_U_VIDEO_CTRL_genr_control_regs[2]_UNCONNECTED\(31 downto 0), + \genr_control_regs[3]\(31 downto 0) => \NLW_U_VIDEO_CTRL_genr_control_regs[3]_UNCONNECTED\(31 downto 0), + \genr_control_regs[4]\(31 downto 0) => \NLW_U_VIDEO_CTRL_genr_control_regs[4]_UNCONNECTED\(31 downto 0), + \genr_status_regs[0]\(31 downto 0) => B"00000000000000000000000000000000", + \genr_status_regs[1]\(31 downto 13) => B"0000000000000000000", + \genr_status_regs[1]\(12 downto 8) => \^intc_if\(12 downto 8), + \genr_status_regs[1]\(7 downto 0) => B"00000000", + \genr_status_regs[2]\(31 downto 23) => B"000000000", + \genr_status_regs[2]\(22) => \^intc_if\(5), + \genr_status_regs[2]\(21 downto 18) => \^intc_if\(5 downto 2), + \genr_status_regs[2]\(17) => \^intc_if\(5), + \genr_status_regs[2]\(16) => \^intc_if\(5), + \genr_status_regs[2]\(15 downto 0) => B"0000000000000000", + \genr_status_regs[3]\(31 downto 0) => B"00000000000000000000000000000000", + \genr_status_regs[4]\(31 downto 0) => B"00000000000000000000000000000000", + ipif_addr_out(8 downto 0) => NLW_U_VIDEO_CTRL_ipif_addr_out_UNCONNECTED(8 downto 0), + ipif_cs_out => NLW_U_VIDEO_CTRL_ipif_cs_out_UNCONNECTED, + ipif_data_out(31 downto 0) => NLW_U_VIDEO_CTRL_ipif_data_out_UNCONNECTED(31 downto 0), + ipif_rnw_out => NLW_U_VIDEO_CTRL_ipif_rnw_out_UNCONNECTED, + irq => irq, + reg_update => reg_update, + resetn_out => vresetn, + s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0), + s_axi_arready => s_axi_arready, + s_axi_arvalid => s_axi_arvalid, + s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0), + s_axi_awready => s_axi_awready, + s_axi_awvalid => s_axi_awvalid, + s_axi_bready => s_axi_bready, + s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0), + s_axi_bvalid => s_axi_bvalid, + s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), + s_axi_rready => s_axi_rready, + s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0), + s_axi_rvalid => s_axi_rvalid, + s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), + s_axi_wready => s_axi_wready, + s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0), + s_axi_wvalid => s_axi_wvalid, + \time_control_regs[0]\(31 downto 0) => \NLW_U_VIDEO_CTRL_time_control_regs[0]_UNCONNECTED\(31 downto 0), + \time_control_regs[10]\(31 downto 0) => \NLW_U_VIDEO_CTRL_time_control_regs[10]_UNCONNECTED\(31 downto 0), + \time_control_regs[11]\(31 downto 0) => \NLW_U_VIDEO_CTRL_time_control_regs[11]_UNCONNECTED\(31 downto 0), + \time_control_regs[12]\(31 downto 0) => \NLW_U_VIDEO_CTRL_time_control_regs[12]_UNCONNECTED\(31 downto 0), + \time_control_regs[13]\(31 downto 0) => \NLW_U_VIDEO_CTRL_time_control_regs[13]_UNCONNECTED\(31 downto 0), + \time_control_regs[14]\(31 downto 0) => \NLW_U_VIDEO_CTRL_time_control_regs[14]_UNCONNECTED\(31 downto 0), + \time_control_regs[15]\(31 downto 0) => \NLW_U_VIDEO_CTRL_time_control_regs[15]_UNCONNECTED\(31 downto 0), + \time_control_regs[16]\(31 downto 27) => \NLW_U_VIDEO_CTRL_time_control_regs[16]_UNCONNECTED\(31 downto 27), + \time_control_regs[16]\(26 downto 16) => \time_control_regs[16]\(26 downto 16), + \time_control_regs[16]\(15) => U_VIDEO_CTRL_n_734, + \time_control_regs[16]\(14) => U_VIDEO_CTRL_n_735, + \time_control_regs[16]\(13) => U_VIDEO_CTRL_n_736, + \time_control_regs[16]\(12) => U_VIDEO_CTRL_n_737, + \time_control_regs[16]\(11 downto 0) => \time_control_regs[16]\(11 downto 0), + \time_control_regs[17]\(31 downto 0) => \NLW_U_VIDEO_CTRL_time_control_regs[17]_UNCONNECTED\(31 downto 0), + \time_control_regs[18]\(31 downto 10) => \NLW_U_VIDEO_CTRL_time_control_regs[18]_UNCONNECTED\(31 downto 10), + \time_control_regs[18]\(9 downto 8) => \time_control_regs[18]\(9 downto 8), + \time_control_regs[18]\(7) => U_VIDEO_CTRL_n_806, + \time_control_regs[18]\(6) => \time_control_regs[18]\(6), + \time_control_regs[18]\(5) => U_VIDEO_CTRL_n_808, + \time_control_regs[18]\(4) => U_VIDEO_CTRL_n_809, + \time_control_regs[18]\(3) => U_VIDEO_CTRL_n_810, + \time_control_regs[18]\(2) => U_VIDEO_CTRL_n_811, + \time_control_regs[18]\(1 downto 0) => \time_control_regs[18]\(1 downto 0), + \time_control_regs[19]\(31 downto 7) => \NLW_U_VIDEO_CTRL_time_control_regs[19]_UNCONNECTED\(31 downto 7), + \time_control_regs[19]\(6 downto 0) => \time_control_regs[19]\(6 downto 0), + \time_control_regs[1]\(31 downto 0) => \NLW_U_VIDEO_CTRL_time_control_regs[1]_UNCONNECTED\(31 downto 0), + \time_control_regs[20]\(31 downto 12) => \NLW_U_VIDEO_CTRL_time_control_regs[20]_UNCONNECTED\(31 downto 12), + \time_control_regs[20]\(11 downto 0) => \time_control_regs[20]\(11 downto 0), + \time_control_regs[21]\(31 downto 27) => \NLW_U_VIDEO_CTRL_time_control_regs[21]_UNCONNECTED\(31 downto 27), + \time_control_regs[21]\(26 downto 16) => \time_control_regs[21]\(26 downto 16), + \time_control_regs[21]\(15) => U_VIDEO_CTRL_n_894, + \time_control_regs[21]\(14) => U_VIDEO_CTRL_n_895, + \time_control_regs[21]\(13) => U_VIDEO_CTRL_n_896, + \time_control_regs[21]\(12) => U_VIDEO_CTRL_n_897, + \time_control_regs[21]\(11) => U_VIDEO_CTRL_n_898, + \time_control_regs[21]\(10 downto 0) => \time_control_regs[21]\(10 downto 0), + \time_control_regs[22]\(31 downto 28) => \NLW_U_VIDEO_CTRL_time_control_regs[22]_UNCONNECTED\(31 downto 28), + \time_control_regs[22]\(27 downto 16) => \time_control_regs[22]\(27 downto 16), + \time_control_regs[22]\(15) => U_VIDEO_CTRL_n_926, + \time_control_regs[22]\(14) => U_VIDEO_CTRL_n_927, + \time_control_regs[22]\(13) => U_VIDEO_CTRL_n_928, + \time_control_regs[22]\(12) => U_VIDEO_CTRL_n_929, + \time_control_regs[22]\(11 downto 0) => \time_control_regs[22]\(11 downto 0), + \time_control_regs[23]\(31 downto 28) => \NLW_U_VIDEO_CTRL_time_control_regs[23]_UNCONNECTED\(31 downto 28), + \time_control_regs[23]\(27 downto 16) => \time_control_regs[23]\(27 downto 16), + \time_control_regs[23]\(15) => U_VIDEO_CTRL_n_958, + \time_control_regs[23]\(14) => U_VIDEO_CTRL_n_959, + \time_control_regs[23]\(13) => U_VIDEO_CTRL_n_960, + \time_control_regs[23]\(12) => U_VIDEO_CTRL_n_961, + \time_control_regs[23]\(11 downto 0) => \time_control_regs[23]\(11 downto 0), + \time_control_regs[24]\(31 downto 27) => \NLW_U_VIDEO_CTRL_time_control_regs[24]_UNCONNECTED\(31 downto 27), + \time_control_regs[24]\(26 downto 16) => \time_control_regs[24]\(26 downto 16), + \time_control_regs[24]\(15) => U_VIDEO_CTRL_n_990, + \time_control_regs[24]\(14) => U_VIDEO_CTRL_n_991, + \time_control_regs[24]\(13) => U_VIDEO_CTRL_n_992, + \time_control_regs[24]\(12) => U_VIDEO_CTRL_n_993, + \time_control_regs[24]\(11) => U_VIDEO_CTRL_n_994, + \time_control_regs[24]\(10 downto 0) => \time_control_regs[24]\(10 downto 0), + \time_control_regs[25]\(31 downto 28) => \NLW_U_VIDEO_CTRL_time_control_regs[25]_UNCONNECTED\(31 downto 28), + \time_control_regs[25]\(27 downto 16) => \time_control_regs[25]\(27 downto 16), + \time_control_regs[25]\(15) => U_VIDEO_CTRL_n_1022, + \time_control_regs[25]\(14) => U_VIDEO_CTRL_n_1023, + \time_control_regs[25]\(13) => U_VIDEO_CTRL_n_1024, + \time_control_regs[25]\(12) => U_VIDEO_CTRL_n_1025, + \time_control_regs[25]\(11 downto 0) => \time_control_regs[25]\(11 downto 0), + \time_control_regs[26]\(31 downto 28) => \NLW_U_VIDEO_CTRL_time_control_regs[26]_UNCONNECTED\(31 downto 28), + \time_control_regs[26]\(27 downto 16) => \time_control_regs[26]\(27 downto 16), + \time_control_regs[26]\(15) => U_VIDEO_CTRL_n_1054, + \time_control_regs[26]\(14) => U_VIDEO_CTRL_n_1055, + \time_control_regs[26]\(13) => U_VIDEO_CTRL_n_1056, + \time_control_regs[26]\(12) => U_VIDEO_CTRL_n_1057, + \time_control_regs[26]\(11 downto 0) => \time_control_regs[26]\(11 downto 0), + \time_control_regs[27]\(31 downto 27) => \NLW_U_VIDEO_CTRL_time_control_regs[27]_UNCONNECTED\(31 downto 27), + \time_control_regs[27]\(26 downto 16) => \time_control_regs[27]\(26 downto 16), + \time_control_regs[27]\(15) => U_VIDEO_CTRL_n_1086, + \time_control_regs[27]\(14) => U_VIDEO_CTRL_n_1087, + \time_control_regs[27]\(13) => U_VIDEO_CTRL_n_1088, + \time_control_regs[27]\(12) => U_VIDEO_CTRL_n_1089, + \time_control_regs[27]\(11) => U_VIDEO_CTRL_n_1090, + \time_control_regs[27]\(10 downto 0) => \time_control_regs[27]\(10 downto 0), + \time_control_regs[28]\(31 downto 28) => \NLW_U_VIDEO_CTRL_time_control_regs[28]_UNCONNECTED\(31 downto 28), + \time_control_regs[28]\(27 downto 16) => \time_control_regs[28]\(27 downto 16), + \time_control_regs[28]\(15) => U_VIDEO_CTRL_n_1118, + \time_control_regs[28]\(14) => U_VIDEO_CTRL_n_1119, + \time_control_regs[28]\(13) => U_VIDEO_CTRL_n_1120, + \time_control_regs[28]\(12) => U_VIDEO_CTRL_n_1121, + \time_control_regs[28]\(11 downto 0) => \time_control_regs[28]\(11 downto 0), + \time_control_regs[2]\(31 downto 0) => \NLW_U_VIDEO_CTRL_time_control_regs[2]_UNCONNECTED\(31 downto 0), + \time_control_regs[3]\(31 downto 0) => \NLW_U_VIDEO_CTRL_time_control_regs[3]_UNCONNECTED\(31 downto 0), + \time_control_regs[4]\(31 downto 0) => \NLW_U_VIDEO_CTRL_time_control_regs[4]_UNCONNECTED\(31 downto 0), + \time_control_regs[5]\(31 downto 0) => \NLW_U_VIDEO_CTRL_time_control_regs[5]_UNCONNECTED\(31 downto 0), + \time_control_regs[6]\(31 downto 0) => \NLW_U_VIDEO_CTRL_time_control_regs[6]_UNCONNECTED\(31 downto 0), + \time_control_regs[7]\(31 downto 0) => \NLW_U_VIDEO_CTRL_time_control_regs[7]_UNCONNECTED\(31 downto 0), + \time_control_regs[8]\(31 downto 0) => \NLW_U_VIDEO_CTRL_time_control_regs[8]_UNCONNECTED\(31 downto 0), + \time_control_regs[9]\(31 downto 0) => \NLW_U_VIDEO_CTRL_time_control_regs[9]_UNCONNECTED\(31 downto 0), + \time_status_regs[0]\(31 downto 27) => B"00000", + \time_status_regs[0]\(26 downto 16) => \time_status_regs_int_reg[0]\(26 downto 16), + \time_status_regs[0]\(15 downto 12) => B"0000", + \time_status_regs[0]\(11 downto 0) => \time_status_regs_int_reg[0]\(11 downto 0), + \time_status_regs[10]\(31 downto 0) => B"00000000000000000000000000000000", + \time_status_regs[11]\(31 downto 0) => B"00000000000000000000000000000000", + \time_status_regs[12]\(31 downto 0) => B"00000000000000000000000000000000", + \time_status_regs[13]\(31 downto 0) => B"00000000000000000000000000000000", + \time_status_regs[14]\(31 downto 0) => B"00000000000000000000000000000000", + \time_status_regs[15]\(31 downto 0) => B"00000000000000000000000000000000", + \time_status_regs[16]\(31 downto 0) => B"00000000000000000000000000000000", + \time_status_regs[17]\(31 downto 2) => B"000000000000000000000000000000", + \time_status_regs[17]\(1) => \^intc_if\(12), + \time_status_regs[17]\(0) => '0', + \time_status_regs[18]\(31 downto 0) => B"00000000000000000000000000000000", + \time_status_regs[19]\(31 downto 0) => B"00000000000000000000000000000000", + \time_status_regs[1]\(31 downto 3) => B"00000000000000000000000000000", + \time_status_regs[1]\(2 downto 1) => \^intc_if\(11 downto 10), + \time_status_regs[1]\(0) => \^intc_if\(8), + \time_status_regs[20]\(31 downto 0) => B"00000000000000000000000000000000", + \time_status_regs[21]\(31 downto 0) => B"00000000000000000000000000000000", + \time_status_regs[22]\(31 downto 0) => B"00000000000000000000000000000000", + \time_status_regs[23]\(31 downto 0) => B"00000000000000000000000000000000", + \time_status_regs[24]\(31 downto 0) => B"00000000000000000000000000000000", + \time_status_regs[25]\(31 downto 0) => B"00000000000000000000000000000000", + \time_status_regs[26]\(31 downto 0) => B"00000000000000000000000000000000", + \time_status_regs[27]\(31 downto 0) => B"00000000000000000000000000000000", + \time_status_regs[28]\(31 downto 0) => B"00000000000000000000000000000000", + \time_status_regs[2]\(31 downto 9) => B"00000000000000000000000", + \time_status_regs[2]\(8) => gen_v0chroma_start(0), + \time_status_regs[2]\(7) => field_id_in, + \time_status_regs[2]\(6 downto 0) => B"0000000", + \time_status_regs[3]\(31 downto 5) => B"000000000000000000000000000", + \time_status_regs[3]\(4 downto 2) => \time_status_regs_int_reg[3]\(4 downto 2), + \time_status_regs[3]\(1 downto 0) => B"00", + \time_status_regs[4]\(31 downto 12) => B"00000000000000000000", + \time_status_regs[4]\(11 downto 0) => \time_status_regs_int_reg[4]\(11 downto 0), + \time_status_regs[5]\(31 downto 11) => B"000000000000000000000", + \time_status_regs[5]\(10 downto 0) => \time_status_regs_int_reg[5]\(10 downto 0), + \time_status_regs[6]\(31 downto 28) => B"0000", + \time_status_regs[6]\(27 downto 16) => \time_status_regs_int_reg[6]\(27 downto 16), + \time_status_regs[6]\(15 downto 12) => B"0000", + \time_status_regs[6]\(11 downto 0) => \time_status_regs_int_reg[6]\(11 downto 0), + \time_status_regs[7]\(31 downto 28) => B"0000", + \time_status_regs[7]\(27 downto 16) => \time_status_regs_int_reg[7]\(27 downto 16), + \time_status_regs[7]\(15 downto 12) => B"0000", + \time_status_regs[7]\(11 downto 0) => \time_status_regs_int_reg[7]\(11 downto 0), + \time_status_regs[8]\(31 downto 27) => B"00000", + \time_status_regs[8]\(26 downto 16) => \time_status_regs_int_reg[8]\(26 downto 16), + \time_status_regs[8]\(15 downto 11) => B"00000", + \time_status_regs[8]\(10 downto 0) => \time_status_regs_int_reg[8]\(10 downto 0), + \time_status_regs[9]\(31 downto 28) => B"0000", + \time_status_regs[9]\(27 downto 16) => \time_status_regs_int_reg[9]\(27 downto 16), + \time_status_regs[9]\(15 downto 12) => B"0000", + \time_status_regs[9]\(11 downto 0) => \time_status_regs_int_reg[9]\(11 downto 0), + vid_aclk => clk, + vid_aclk_en => clken, + vid_aresetn => resetn + ); +U_VIDEO_CTRL_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"CD" + ) + port map ( + I0 => \genr_control_regs[0]\(2), + I1 => core_d, + I2 => \genr_control_regs[0]\(0), + O => reg_update + ); +\gen_v0chroma_start[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CA0A0A0A00000000" + ) + port map ( + I0 => gen_v0chroma_start(0), + I1 => \time_control_regs[18]\(8), + I2 => clken, + I3 => \time_control_regs[18]\(1), + I4 => \time_control_regs[18]\(0), + I5 => resetn, + O => \gen_v0chroma_start[0]_i_1_n_0\ + ); +\gen_v0chroma_start_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => clk, + CE => '1', + D => \gen_v0chroma_start[0]_i_1_n_0\, + Q => gen_v0chroma_start(0), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_tc_1_0 is + port ( + clk : in STD_LOGIC; + clken : in STD_LOGIC; + s_axi_aclk : in STD_LOGIC; + s_axi_aclken : in STD_LOGIC; + det_clken : in STD_LOGIC; + intc_if : out STD_LOGIC_VECTOR ( 31 downto 0 ); + hsync_in : in STD_LOGIC; + vsync_in : in STD_LOGIC; + active_video_in : in STD_LOGIC; + resetn : in STD_LOGIC; + s_axi_aresetn : in STD_LOGIC; + s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_arvalid : in STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rvalid : out STD_LOGIC; + s_axi_rready : in STD_LOGIC; + irq : out STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of Arty_Z7_20_v_tc_1_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of Arty_Z7_20_v_tc_1_0 : entity is "Arty_Z7_20_v_tc_1_0,v_tc,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of Arty_Z7_20_v_tc_1_0 : entity is "yes"; + attribute x_core_info : string; + attribute x_core_info of Arty_Z7_20_v_tc_1_0 : entity is "v_tc,Vivado 2016.4"; +end Arty_Z7_20_v_tc_1_0; + +architecture STRUCTURE of Arty_Z7_20_v_tc_1_0 is + signal NLW_U0_active_chroma_out_UNCONNECTED : STD_LOGIC; + signal NLW_U0_active_video_out_UNCONNECTED : STD_LOGIC; + signal NLW_U0_field_id_out_UNCONNECTED : STD_LOGIC; + signal NLW_U0_hblank_out_UNCONNECTED : STD_LOGIC; + signal NLW_U0_hsync_out_UNCONNECTED : STD_LOGIC; + signal NLW_U0_vblank_out_UNCONNECTED : STD_LOGIC; + signal NLW_U0_vsync_out_UNCONNECTED : STD_LOGIC; + signal NLW_U0_fsync_out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + attribute C_CONTROL : integer; + attribute C_CONTROL of U0 : label is 0; + attribute C_DETECT_EN : integer; + attribute C_DETECT_EN of U0 : label is 1; + attribute C_DET_ACHROMA_EN : integer; + attribute C_DET_ACHROMA_EN of U0 : label is 0; + attribute C_DET_AVIDEO_EN : integer; + attribute C_DET_AVIDEO_EN of U0 : label is 1; + attribute C_DET_FIELDID_EN : integer; + attribute C_DET_FIELDID_EN of U0 : label is 0; + attribute C_DET_HBLANK_EN : integer; + attribute C_DET_HBLANK_EN of U0 : label is 0; + attribute C_DET_HSYNC_EN : integer; + attribute C_DET_HSYNC_EN of U0 : label is 1; + attribute C_DET_VBLANK_EN : integer; + attribute C_DET_VBLANK_EN of U0 : label is 0; + attribute C_DET_VSYNC_EN : integer; + attribute C_DET_VSYNC_EN of U0 : label is 1; + attribute C_FAMILY : string; + attribute C_FAMILY of U0 : label is "virtex5"; + attribute C_FSYNC_HSTART0 : integer; + attribute C_FSYNC_HSTART0 of U0 : label is 0; + attribute C_FSYNC_HSTART1 : integer; + attribute C_FSYNC_HSTART1 of U0 : label is 0; + attribute C_FSYNC_HSTART10 : integer; + attribute C_FSYNC_HSTART10 of U0 : label is 0; + attribute C_FSYNC_HSTART11 : integer; + attribute C_FSYNC_HSTART11 of U0 : label is 0; + attribute C_FSYNC_HSTART12 : integer; + attribute C_FSYNC_HSTART12 of U0 : label is 0; + attribute C_FSYNC_HSTART13 : integer; + attribute C_FSYNC_HSTART13 of U0 : label is 0; + attribute C_FSYNC_HSTART14 : integer; + attribute C_FSYNC_HSTART14 of U0 : label is 0; + attribute C_FSYNC_HSTART15 : integer; + attribute C_FSYNC_HSTART15 of U0 : label is 0; + attribute C_FSYNC_HSTART2 : integer; + attribute C_FSYNC_HSTART2 of U0 : label is 0; + attribute C_FSYNC_HSTART3 : integer; + attribute C_FSYNC_HSTART3 of U0 : label is 0; + attribute C_FSYNC_HSTART4 : integer; + attribute C_FSYNC_HSTART4 of U0 : label is 0; + attribute C_FSYNC_HSTART5 : integer; + attribute C_FSYNC_HSTART5 of U0 : label is 0; + attribute C_FSYNC_HSTART6 : integer; + attribute C_FSYNC_HSTART6 of U0 : label is 0; + attribute C_FSYNC_HSTART7 : integer; + attribute C_FSYNC_HSTART7 of U0 : label is 0; + attribute C_FSYNC_HSTART8 : integer; + attribute C_FSYNC_HSTART8 of U0 : label is 0; + attribute C_FSYNC_HSTART9 : integer; + attribute C_FSYNC_HSTART9 of U0 : label is 0; + attribute C_FSYNC_VSTART0 : integer; + attribute C_FSYNC_VSTART0 of U0 : label is 0; + attribute C_FSYNC_VSTART1 : integer; + attribute C_FSYNC_VSTART1 of U0 : label is 0; + attribute C_FSYNC_VSTART10 : integer; + attribute C_FSYNC_VSTART10 of U0 : label is 0; + attribute C_FSYNC_VSTART11 : integer; + attribute C_FSYNC_VSTART11 of U0 : label is 0; + attribute C_FSYNC_VSTART12 : integer; + attribute C_FSYNC_VSTART12 of U0 : label is 0; + attribute C_FSYNC_VSTART13 : integer; + attribute C_FSYNC_VSTART13 of U0 : label is 0; + attribute C_FSYNC_VSTART14 : integer; + attribute C_FSYNC_VSTART14 of U0 : label is 0; + attribute C_FSYNC_VSTART15 : integer; + attribute C_FSYNC_VSTART15 of U0 : label is 0; + attribute C_FSYNC_VSTART2 : integer; + attribute C_FSYNC_VSTART2 of U0 : label is 0; + attribute C_FSYNC_VSTART3 : integer; + attribute C_FSYNC_VSTART3 of U0 : label is 0; + attribute C_FSYNC_VSTART4 : integer; + attribute C_FSYNC_VSTART4 of U0 : label is 0; + attribute C_FSYNC_VSTART5 : integer; + attribute C_FSYNC_VSTART5 of U0 : label is 0; + attribute C_FSYNC_VSTART6 : integer; + attribute C_FSYNC_VSTART6 of U0 : label is 0; + attribute C_FSYNC_VSTART7 : integer; + attribute C_FSYNC_VSTART7 of U0 : label is 0; + attribute C_FSYNC_VSTART8 : integer; + attribute C_FSYNC_VSTART8 of U0 : label is 0; + attribute C_FSYNC_VSTART9 : integer; + attribute C_FSYNC_VSTART9 of U0 : label is 0; + attribute C_GENERATE_EN : integer; + attribute C_GENERATE_EN of U0 : label is 0; + attribute C_GEN_ACHROMA_EN : integer; + attribute C_GEN_ACHROMA_EN of U0 : label is 0; + attribute C_GEN_ACHROMA_POLARITY : integer; + attribute C_GEN_ACHROMA_POLARITY of U0 : label is 1; + attribute C_GEN_AUTO_SWITCH : integer; + attribute C_GEN_AUTO_SWITCH of U0 : label is 0; + attribute C_GEN_AVIDEO_EN : integer; + attribute C_GEN_AVIDEO_EN of U0 : label is 1; + attribute C_GEN_AVIDEO_POLARITY : integer; + attribute C_GEN_AVIDEO_POLARITY of U0 : label is 1; + attribute C_GEN_CPARITY : integer; + attribute C_GEN_CPARITY of U0 : label is 0; + attribute C_GEN_F0_VBLANK_HEND : integer; + attribute C_GEN_F0_VBLANK_HEND of U0 : label is 1280; + attribute C_GEN_F0_VBLANK_HSTART : integer; + attribute C_GEN_F0_VBLANK_HSTART of U0 : label is 1280; + attribute C_GEN_F0_VFRAME_SIZE : integer; + attribute C_GEN_F0_VFRAME_SIZE of U0 : label is 750; + attribute C_GEN_F0_VSYNC_HEND : integer; + attribute C_GEN_F0_VSYNC_HEND of U0 : label is 1280; + attribute C_GEN_F0_VSYNC_HSTART : integer; + attribute C_GEN_F0_VSYNC_HSTART of U0 : label is 1280; + attribute C_GEN_F0_VSYNC_VEND : integer; + attribute C_GEN_F0_VSYNC_VEND of U0 : label is 729; + attribute C_GEN_F0_VSYNC_VSTART : integer; + attribute C_GEN_F0_VSYNC_VSTART of U0 : label is 724; + attribute C_GEN_F1_VBLANK_HEND : integer; + attribute C_GEN_F1_VBLANK_HEND of U0 : label is 1280; + attribute C_GEN_F1_VBLANK_HSTART : integer; + attribute C_GEN_F1_VBLANK_HSTART of U0 : label is 1280; + attribute C_GEN_F1_VFRAME_SIZE : integer; + attribute C_GEN_F1_VFRAME_SIZE of U0 : label is 750; + attribute C_GEN_F1_VSYNC_HEND : integer; + attribute C_GEN_F1_VSYNC_HEND of U0 : label is 1280; + attribute C_GEN_F1_VSYNC_HSTART : integer; + attribute C_GEN_F1_VSYNC_HSTART of U0 : label is 1280; + attribute C_GEN_F1_VSYNC_VEND : integer; + attribute C_GEN_F1_VSYNC_VEND of U0 : label is 729; + attribute C_GEN_F1_VSYNC_VSTART : integer; + attribute C_GEN_F1_VSYNC_VSTART of U0 : label is 724; + attribute C_GEN_FIELDID_EN : integer; + attribute C_GEN_FIELDID_EN of U0 : label is 0; + attribute C_GEN_FIELDID_POLARITY : integer; + attribute C_GEN_FIELDID_POLARITY of U0 : label is 1; + attribute C_GEN_HACTIVE_SIZE : integer; + attribute C_GEN_HACTIVE_SIZE of U0 : label is 1280; + attribute C_GEN_HBLANK_EN : integer; + attribute C_GEN_HBLANK_EN of U0 : label is 1; + attribute C_GEN_HBLANK_POLARITY : integer; + attribute C_GEN_HBLANK_POLARITY of U0 : label is 1; + attribute C_GEN_HFRAME_SIZE : integer; + attribute C_GEN_HFRAME_SIZE of U0 : label is 1650; + attribute C_GEN_HSYNC_EN : integer; + attribute C_GEN_HSYNC_EN of U0 : label is 1; + attribute C_GEN_HSYNC_END : integer; + attribute C_GEN_HSYNC_END of U0 : label is 1430; + attribute C_GEN_HSYNC_POLARITY : integer; + attribute C_GEN_HSYNC_POLARITY of U0 : label is 1; + attribute C_GEN_HSYNC_START : integer; + attribute C_GEN_HSYNC_START of U0 : label is 1390; + attribute C_GEN_INTERLACED : integer; + attribute C_GEN_INTERLACED of U0 : label is 0; + attribute C_GEN_VACTIVE_SIZE : integer; + attribute C_GEN_VACTIVE_SIZE of U0 : label is 720; + attribute C_GEN_VBLANK_EN : integer; + attribute C_GEN_VBLANK_EN of U0 : label is 1; + attribute C_GEN_VBLANK_POLARITY : integer; + attribute C_GEN_VBLANK_POLARITY of U0 : label is 1; + attribute C_GEN_VIDEO_FORMAT : integer; + attribute C_GEN_VIDEO_FORMAT of U0 : label is 2; + attribute C_GEN_VSYNC_EN : integer; + attribute C_GEN_VSYNC_EN of U0 : label is 1; + attribute C_GEN_VSYNC_POLARITY : integer; + attribute C_GEN_VSYNC_POLARITY of U0 : label is 1; + attribute C_HAS_AXI4_LITE : integer; + attribute C_HAS_AXI4_LITE of U0 : label is 1; + attribute C_HAS_INTC_IF : integer; + attribute C_HAS_INTC_IF of U0 : label is 1; + attribute C_INTERLACE_EN : integer; + attribute C_INTERLACE_EN of U0 : label is 0; + attribute C_IRQEN : integer; + attribute C_IRQEN of U0 : label is 0; + attribute C_LINE_DELAY : integer; + attribute C_LINE_DELAY of U0 : label is 0; + attribute C_MAX_LINES : integer; + attribute C_MAX_LINES of U0 : label is 2048; + attribute C_MAX_PIXELS : integer; + attribute C_MAX_PIXELS of U0 : label is 4096; + attribute C_NUM_FSYNCS : integer; + attribute C_NUM_FSYNCS of U0 : label is 1; + attribute C_PIXEL_DELAY : integer; + attribute C_PIXEL_DELAY of U0 : label is 0; + attribute C_SYNC_EN : integer; + attribute C_SYNC_EN of U0 : label is 0; + attribute C_S_AXI_ADDR_WIDTH : integer; + attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9; + attribute C_S_AXI_CLK_FREQ_HZ : integer; + attribute C_S_AXI_CLK_FREQ_HZ of U0 : label is 100000000; + attribute C_S_AXI_DATA_WIDTH : integer; + attribute C_S_AXI_DATA_WIDTH of U0 : label is 32; + attribute downgradeipidentifiedwarnings of U0 : label is "yes"; +begin +U0: entity work.Arty_Z7_20_v_tc_1_0_v_tc + port map ( + active_chroma_in => '0', + active_chroma_out => NLW_U0_active_chroma_out_UNCONNECTED, + active_video_in => active_video_in, + active_video_out => NLW_U0_active_video_out_UNCONNECTED, + clk => clk, + clken => clken, + det_clken => det_clken, + field_id_in => '0', + field_id_out => NLW_U0_field_id_out_UNCONNECTED, + fsync_in => '0', + fsync_out(0) => NLW_U0_fsync_out_UNCONNECTED(0), + gen_clken => '1', + hblank_in => '0', + hblank_out => NLW_U0_hblank_out_UNCONNECTED, + hsync_in => hsync_in, + hsync_out => NLW_U0_hsync_out_UNCONNECTED, + intc_if(31 downto 0) => intc_if(31 downto 0), + irq => irq, + resetn => resetn, + s_axi_aclk => s_axi_aclk, + s_axi_aclken => s_axi_aclken, + s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0), + s_axi_aresetn => s_axi_aresetn, + s_axi_arready => s_axi_arready, + s_axi_arvalid => s_axi_arvalid, + s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0), + s_axi_awready => s_axi_awready, + s_axi_awvalid => s_axi_awvalid, + s_axi_bready => s_axi_bready, + s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0), + s_axi_bvalid => s_axi_bvalid, + s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), + s_axi_rready => s_axi_rready, + s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0), + s_axi_rvalid => s_axi_rvalid, + s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), + s_axi_wready => s_axi_wready, + s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0), + s_axi_wvalid => s_axi_wvalid, + vblank_in => '0', + vblank_out => NLW_U0_vblank_out_UNCONNECTED, + vsync_in => vsync_in, + vsync_out => NLW_U0_vsync_out_UNCONNECTED + ); +end STRUCTURE; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0_stub.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0_stub.v new file mode 100644 index 0000000..68cabb2 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0_stub.v @@ -0,0 +1,52 @@ +// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +// Date : Sat Mar 04 18:56:16 2017 +// Host : WK73 running 64-bit Service Pack 1 (build 7601) +// Command : write_verilog -force -mode synth_stub +// c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0_stub.v +// Design : Arty_Z7_20_v_tc_1_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg400-1 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "v_tc,Vivado 2016.4" *) +module Arty_Z7_20_v_tc_1_0(clk, clken, s_axi_aclk, s_axi_aclken, det_clken, + intc_if, hsync_in, vsync_in, active_video_in, resetn, s_axi_aresetn, s_axi_awaddr, + s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, + s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready, + s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, irq) +/* synthesis syn_black_box black_box_pad_pin="clk,clken,s_axi_aclk,s_axi_aclken,det_clken,intc_if[31:0],hsync_in,vsync_in,active_video_in,resetn,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,irq" */; + input clk; + input clken; + input s_axi_aclk; + input s_axi_aclken; + input det_clken; + output [31:0]intc_if; + input hsync_in; + input vsync_in; + input active_video_in; + input resetn; + input s_axi_aresetn; + input [8:0]s_axi_awaddr; + input s_axi_awvalid; + output s_axi_awready; + input [31:0]s_axi_wdata; + input [3:0]s_axi_wstrb; + input s_axi_wvalid; + output s_axi_wready; + output [1:0]s_axi_bresp; + output s_axi_bvalid; + input s_axi_bready; + input [8:0]s_axi_araddr; + input s_axi_arvalid; + output s_axi_arready; + output [31:0]s_axi_rdata; + output [1:0]s_axi_rresp; + output s_axi_rvalid; + input s_axi_rready; + output irq; +endmodule diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0_stub.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0_stub.vhdl new file mode 100644 index 0000000..74b0f28 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0_stub.vhdl @@ -0,0 +1,58 @@ +-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +-- Date : Sat Mar 04 18:56:16 2017 +-- Host : WK73 running 64-bit Service Pack 1 (build 7601) +-- Command : write_vhdl -force -mode synth_stub +-- c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/Arty_Z7_20_v_tc_1_0_stub.vhdl +-- Design : Arty_Z7_20_v_tc_1_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg400-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Arty_Z7_20_v_tc_1_0 is + Port ( + clk : in STD_LOGIC; + clken : in STD_LOGIC; + s_axi_aclk : in STD_LOGIC; + s_axi_aclken : in STD_LOGIC; + det_clken : in STD_LOGIC; + intc_if : out STD_LOGIC_VECTOR ( 31 downto 0 ); + hsync_in : in STD_LOGIC; + vsync_in : in STD_LOGIC; + active_video_in : in STD_LOGIC; + resetn : in STD_LOGIC; + s_axi_aresetn : in STD_LOGIC; + s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_arvalid : in STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rvalid : out STD_LOGIC; + s_axi_rready : in STD_LOGIC; + irq : out STD_LOGIC + ); + +end Arty_Z7_20_v_tc_1_0; + +architecture stub of Arty_Z7_20_v_tc_1_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,clken,s_axi_aclk,s_axi_aclken,det_clken,intc_if[31:0],hsync_in,vsync_in,active_video_in,resetn,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,irq"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "v_tc,Vivado 2016.4"; +begin +end; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/sim/Arty_Z7_20_v_tc_1_0.vhd b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/sim/Arty_Z7_20_v_tc_1_0.vhd new file mode 100644 index 0000000..e407ddc --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/sim/Arty_Z7_20_v_tc_1_0.vhd @@ -0,0 +1,384 @@ +-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:v_tc:6.1 +-- IP Revision: 10 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY v_tc_v6_1_10; +USE v_tc_v6_1_10.v_tc; + +ENTITY Arty_Z7_20_v_tc_1_0 IS + PORT ( + clk : IN STD_LOGIC; + clken : IN STD_LOGIC; + s_axi_aclk : IN STD_LOGIC; + s_axi_aclken : IN STD_LOGIC; + det_clken : IN STD_LOGIC; + intc_if : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + hsync_in : IN STD_LOGIC; + vsync_in : IN STD_LOGIC; + active_video_in : IN STD_LOGIC; + resetn : IN STD_LOGIC; + s_axi_aresetn : IN STD_LOGIC; + s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_awvalid : IN STD_LOGIC; + s_axi_awready : OUT STD_LOGIC; + s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + s_axi_wvalid : IN STD_LOGIC; + s_axi_wready : OUT STD_LOGIC; + s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_bvalid : OUT STD_LOGIC; + s_axi_bready : IN STD_LOGIC; + s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_arvalid : IN STD_LOGIC; + s_axi_arready : OUT STD_LOGIC; + s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_rvalid : OUT STD_LOGIC; + s_axi_rready : IN STD_LOGIC; + irq : OUT STD_LOGIC + ); +END Arty_Z7_20_v_tc_1_0; + +ARCHITECTURE Arty_Z7_20_v_tc_1_0_arch OF Arty_Z7_20_v_tc_1_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF Arty_Z7_20_v_tc_1_0_arch: ARCHITECTURE IS "yes"; + COMPONENT v_tc IS + GENERIC ( + C_HAS_AXI4_LITE : INTEGER; + C_HAS_INTC_IF : INTEGER; + C_GEN_INTERLACED : INTEGER; + C_GEN_HACTIVE_SIZE : INTEGER; + C_GEN_VACTIVE_SIZE : INTEGER; + C_GEN_CPARITY : INTEGER; + C_GEN_FIELDID_POLARITY : INTEGER; + C_GEN_VBLANK_POLARITY : INTEGER; + C_GEN_HBLANK_POLARITY : INTEGER; + C_GEN_VSYNC_POLARITY : INTEGER; + C_GEN_HSYNC_POLARITY : INTEGER; + C_GEN_AVIDEO_POLARITY : INTEGER; + C_GEN_ACHROMA_POLARITY : INTEGER; + C_GEN_VIDEO_FORMAT : INTEGER; + C_GEN_HFRAME_SIZE : INTEGER; + C_GEN_F0_VFRAME_SIZE : INTEGER; + C_GEN_F1_VFRAME_SIZE : INTEGER; + C_GEN_HSYNC_START : INTEGER; + C_GEN_HSYNC_END : INTEGER; + C_GEN_F0_VBLANK_HSTART : INTEGER; + C_GEN_F0_VBLANK_HEND : INTEGER; + C_GEN_F0_VSYNC_VSTART : INTEGER; + C_GEN_F0_VSYNC_VEND : INTEGER; + C_GEN_F0_VSYNC_HSTART : INTEGER; + C_GEN_F0_VSYNC_HEND : INTEGER; + C_GEN_F1_VBLANK_HSTART : INTEGER; + C_GEN_F1_VBLANK_HEND : INTEGER; + C_GEN_F1_VSYNC_VSTART : INTEGER; + C_GEN_F1_VSYNC_VEND : INTEGER; + C_GEN_F1_VSYNC_HSTART : INTEGER; + C_GEN_F1_VSYNC_HEND : INTEGER; + C_FSYNC_HSTART0 : INTEGER; + C_FSYNC_VSTART0 : INTEGER; + C_FSYNC_HSTART1 : INTEGER; + C_FSYNC_VSTART1 : INTEGER; + C_FSYNC_HSTART2 : INTEGER; + C_FSYNC_VSTART2 : INTEGER; + C_FSYNC_HSTART3 : INTEGER; + C_FSYNC_VSTART3 : INTEGER; + C_FSYNC_HSTART4 : INTEGER; + C_FSYNC_VSTART4 : INTEGER; + C_FSYNC_HSTART5 : INTEGER; + C_FSYNC_VSTART5 : INTEGER; + C_FSYNC_HSTART6 : INTEGER; + C_FSYNC_VSTART6 : INTEGER; + C_FSYNC_HSTART7 : INTEGER; + C_FSYNC_VSTART7 : INTEGER; + C_FSYNC_HSTART8 : INTEGER; + C_FSYNC_VSTART8 : INTEGER; + C_FSYNC_HSTART9 : INTEGER; + C_FSYNC_VSTART9 : INTEGER; + C_FSYNC_HSTART10 : INTEGER; + C_FSYNC_VSTART10 : INTEGER; + C_FSYNC_HSTART11 : INTEGER; + C_FSYNC_VSTART11 : INTEGER; + C_FSYNC_HSTART12 : INTEGER; + C_FSYNC_VSTART12 : INTEGER; + C_FSYNC_HSTART13 : INTEGER; + C_FSYNC_VSTART13 : INTEGER; + C_FSYNC_HSTART14 : INTEGER; + C_FSYNC_VSTART14 : INTEGER; + C_FSYNC_HSTART15 : INTEGER; + C_FSYNC_VSTART15 : INTEGER; + C_MAX_PIXELS : INTEGER; + C_MAX_LINES : INTEGER; + C_NUM_FSYNCS : INTEGER; + C_INTERLACE_EN : INTEGER; + C_GEN_AUTO_SWITCH : INTEGER; + C_DETECT_EN : INTEGER; + C_SYNC_EN : INTEGER; + C_GENERATE_EN : INTEGER; + C_DET_HSYNC_EN : INTEGER; + C_DET_VSYNC_EN : INTEGER; + C_DET_HBLANK_EN : INTEGER; + C_DET_VBLANK_EN : INTEGER; + C_DET_AVIDEO_EN : INTEGER; + C_DET_ACHROMA_EN : INTEGER; + C_GEN_HSYNC_EN : INTEGER; + C_GEN_VSYNC_EN : INTEGER; + C_GEN_HBLANK_EN : INTEGER; + C_GEN_VBLANK_EN : INTEGER; + C_GEN_AVIDEO_EN : INTEGER; + C_GEN_ACHROMA_EN : INTEGER; + C_GEN_FIELDID_EN : INTEGER; + C_DET_FIELDID_EN : INTEGER + ); + PORT ( + clk : IN STD_LOGIC; + clken : IN STD_LOGIC; + s_axi_aclk : IN STD_LOGIC; + s_axi_aclken : IN STD_LOGIC; + det_clken : IN STD_LOGIC; + gen_clken : IN STD_LOGIC; + intc_if : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + field_id_in : IN STD_LOGIC; + hsync_in : IN STD_LOGIC; + hblank_in : IN STD_LOGIC; + vsync_in : IN STD_LOGIC; + vblank_in : IN STD_LOGIC; + active_video_in : IN STD_LOGIC; + active_chroma_in : IN STD_LOGIC; + field_id_out : OUT STD_LOGIC; + hsync_out : OUT STD_LOGIC; + hblank_out : OUT STD_LOGIC; + vsync_out : OUT STD_LOGIC; + vblank_out : OUT STD_LOGIC; + active_video_out : OUT STD_LOGIC; + active_chroma_out : OUT STD_LOGIC; + resetn : IN STD_LOGIC; + s_axi_aresetn : IN STD_LOGIC; + s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_awvalid : IN STD_LOGIC; + s_axi_awready : OUT STD_LOGIC; + s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + s_axi_wvalid : IN STD_LOGIC; + s_axi_wready : OUT STD_LOGIC; + s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_bvalid : OUT STD_LOGIC; + s_axi_bready : IN STD_LOGIC; + s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_arvalid : IN STD_LOGIC; + s_axi_arready : OUT STD_LOGIC; + s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_rvalid : OUT STD_LOGIC; + s_axi_rready : IN STD_LOGIC; + irq : OUT STD_LOGIC; + fsync_in : IN STD_LOGIC; + fsync_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); + END COMPONENT v_tc; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK"; + ATTRIBUTE X_INTERFACE_INFO OF clken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 clken_intf CE"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk_intf CLK"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 s_axi_aclken_intf CE"; + ATTRIBUTE X_INTERFACE_INFO OF hsync_in: SIGNAL IS "xilinx.com:interface:video_timing:2.0 vtiming_in HSYNC"; + ATTRIBUTE X_INTERFACE_INFO OF vsync_in: SIGNAL IS "xilinx.com:interface:video_timing:2.0 vtiming_in VSYNC"; + ATTRIBUTE X_INTERFACE_INFO OF active_video_in: SIGNAL IS "xilinx.com:interface:video_timing:2.0 vtiming_in ACTIVE_VIDEO"; + ATTRIBUTE X_INTERFACE_INFO OF resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 resetn_intf RST"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_axi_aresetn_intf RST"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl AWADDR"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl AWVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl AWREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WDATA"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WSTRB"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl BRESP"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl BVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl BREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl ARADDR"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl ARVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl ARREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RDATA"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RRESP"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RREADY"; + ATTRIBUTE X_INTERFACE_INFO OF irq: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IRQ INTERRUPT"; +BEGIN + U0 : v_tc + GENERIC MAP ( + C_HAS_AXI4_LITE => 1, + C_HAS_INTC_IF => 1, + C_GEN_INTERLACED => 0, + C_GEN_HACTIVE_SIZE => 1280, + C_GEN_VACTIVE_SIZE => 720, + C_GEN_CPARITY => 0, + C_GEN_FIELDID_POLARITY => 1, + C_GEN_VBLANK_POLARITY => 1, + C_GEN_HBLANK_POLARITY => 1, + C_GEN_VSYNC_POLARITY => 1, + C_GEN_HSYNC_POLARITY => 1, + C_GEN_AVIDEO_POLARITY => 1, + C_GEN_ACHROMA_POLARITY => 1, + C_GEN_VIDEO_FORMAT => 2, + C_GEN_HFRAME_SIZE => 1650, + C_GEN_F0_VFRAME_SIZE => 750, + C_GEN_F1_VFRAME_SIZE => 750, + C_GEN_HSYNC_START => 1390, + C_GEN_HSYNC_END => 1430, + C_GEN_F0_VBLANK_HSTART => 1280, + C_GEN_F0_VBLANK_HEND => 1280, + C_GEN_F0_VSYNC_VSTART => 724, + C_GEN_F0_VSYNC_VEND => 729, + C_GEN_F0_VSYNC_HSTART => 1280, + C_GEN_F0_VSYNC_HEND => 1280, + C_GEN_F1_VBLANK_HSTART => 1280, + C_GEN_F1_VBLANK_HEND => 1280, + C_GEN_F1_VSYNC_VSTART => 724, + C_GEN_F1_VSYNC_VEND => 729, + C_GEN_F1_VSYNC_HSTART => 1280, + C_GEN_F1_VSYNC_HEND => 1280, + C_FSYNC_HSTART0 => 0, + C_FSYNC_VSTART0 => 0, + C_FSYNC_HSTART1 => 0, + C_FSYNC_VSTART1 => 0, + C_FSYNC_HSTART2 => 0, + C_FSYNC_VSTART2 => 0, + C_FSYNC_HSTART3 => 0, + C_FSYNC_VSTART3 => 0, + C_FSYNC_HSTART4 => 0, + C_FSYNC_VSTART4 => 0, + C_FSYNC_HSTART5 => 0, + C_FSYNC_VSTART5 => 0, + C_FSYNC_HSTART6 => 0, + C_FSYNC_VSTART6 => 0, + C_FSYNC_HSTART7 => 0, + C_FSYNC_VSTART7 => 0, + C_FSYNC_HSTART8 => 0, + C_FSYNC_VSTART8 => 0, + C_FSYNC_HSTART9 => 0, + C_FSYNC_VSTART9 => 0, + C_FSYNC_HSTART10 => 0, + C_FSYNC_VSTART10 => 0, + C_FSYNC_HSTART11 => 0, + C_FSYNC_VSTART11 => 0, + C_FSYNC_HSTART12 => 0, + C_FSYNC_VSTART12 => 0, + C_FSYNC_HSTART13 => 0, + C_FSYNC_VSTART13 => 0, + C_FSYNC_HSTART14 => 0, + C_FSYNC_VSTART14 => 0, + C_FSYNC_HSTART15 => 0, + C_FSYNC_VSTART15 => 0, + C_MAX_PIXELS => 4096, + C_MAX_LINES => 2048, + C_NUM_FSYNCS => 1, + C_INTERLACE_EN => 0, + C_GEN_AUTO_SWITCH => 0, + C_DETECT_EN => 1, + C_SYNC_EN => 0, + C_GENERATE_EN => 0, + C_DET_HSYNC_EN => 1, + C_DET_VSYNC_EN => 1, + C_DET_HBLANK_EN => 0, + C_DET_VBLANK_EN => 0, + C_DET_AVIDEO_EN => 1, + C_DET_ACHROMA_EN => 0, + C_GEN_HSYNC_EN => 1, + C_GEN_VSYNC_EN => 1, + C_GEN_HBLANK_EN => 1, + C_GEN_VBLANK_EN => 1, + C_GEN_AVIDEO_EN => 1, + C_GEN_ACHROMA_EN => 0, + C_GEN_FIELDID_EN => 0, + C_DET_FIELDID_EN => 0 + ) + PORT MAP ( + clk => clk, + clken => clken, + s_axi_aclk => s_axi_aclk, + s_axi_aclken => s_axi_aclken, + det_clken => det_clken, + gen_clken => '1', + intc_if => intc_if, + field_id_in => '0', + hsync_in => hsync_in, + hblank_in => '0', + vsync_in => vsync_in, + vblank_in => '0', + active_video_in => active_video_in, + active_chroma_in => '0', + resetn => resetn, + s_axi_aresetn => s_axi_aresetn, + s_axi_awaddr => s_axi_awaddr, + s_axi_awvalid => s_axi_awvalid, + s_axi_awready => s_axi_awready, + s_axi_wdata => s_axi_wdata, + s_axi_wstrb => s_axi_wstrb, + s_axi_wvalid => s_axi_wvalid, + s_axi_wready => s_axi_wready, + s_axi_bresp => s_axi_bresp, + s_axi_bvalid => s_axi_bvalid, + s_axi_bready => s_axi_bready, + s_axi_araddr => s_axi_araddr, + s_axi_arvalid => s_axi_arvalid, + s_axi_arready => s_axi_arready, + s_axi_rdata => s_axi_rdata, + s_axi_rresp => s_axi_rresp, + s_axi_rvalid => s_axi_rvalid, + s_axi_rready => s_axi_rready, + irq => irq, + fsync_in => '0' + ); +END Arty_Z7_20_v_tc_1_0_arch; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/synth/Arty_Z7_20_v_tc_1_0.vhd b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/synth/Arty_Z7_20_v_tc_1_0.vhd new file mode 100644 index 0000000..aea8f83 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_tc_1_0/synth/Arty_Z7_20_v_tc_1_0.vhd @@ -0,0 +1,393 @@ +-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:v_tc:6.1 +-- IP Revision: 10 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY v_tc_v6_1_10; +USE v_tc_v6_1_10.v_tc; + +ENTITY Arty_Z7_20_v_tc_1_0 IS + PORT ( + clk : IN STD_LOGIC; + clken : IN STD_LOGIC; + s_axi_aclk : IN STD_LOGIC; + s_axi_aclken : IN STD_LOGIC; + det_clken : IN STD_LOGIC; + intc_if : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + hsync_in : IN STD_LOGIC; + vsync_in : IN STD_LOGIC; + active_video_in : IN STD_LOGIC; + resetn : IN STD_LOGIC; + s_axi_aresetn : IN STD_LOGIC; + s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_awvalid : IN STD_LOGIC; + s_axi_awready : OUT STD_LOGIC; + s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + s_axi_wvalid : IN STD_LOGIC; + s_axi_wready : OUT STD_LOGIC; + s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_bvalid : OUT STD_LOGIC; + s_axi_bready : IN STD_LOGIC; + s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_arvalid : IN STD_LOGIC; + s_axi_arready : OUT STD_LOGIC; + s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_rvalid : OUT STD_LOGIC; + s_axi_rready : IN STD_LOGIC; + irq : OUT STD_LOGIC + ); +END Arty_Z7_20_v_tc_1_0; + +ARCHITECTURE Arty_Z7_20_v_tc_1_0_arch OF Arty_Z7_20_v_tc_1_0 IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF Arty_Z7_20_v_tc_1_0_arch: ARCHITECTURE IS "yes"; + COMPONENT v_tc IS + GENERIC ( + C_HAS_AXI4_LITE : INTEGER; + C_HAS_INTC_IF : INTEGER; + C_GEN_INTERLACED : INTEGER; + C_GEN_HACTIVE_SIZE : INTEGER; + C_GEN_VACTIVE_SIZE : INTEGER; + C_GEN_CPARITY : INTEGER; + C_GEN_FIELDID_POLARITY : INTEGER; + C_GEN_VBLANK_POLARITY : INTEGER; + C_GEN_HBLANK_POLARITY : INTEGER; + C_GEN_VSYNC_POLARITY : INTEGER; + C_GEN_HSYNC_POLARITY : INTEGER; + C_GEN_AVIDEO_POLARITY : INTEGER; + C_GEN_ACHROMA_POLARITY : INTEGER; + C_GEN_VIDEO_FORMAT : INTEGER; + C_GEN_HFRAME_SIZE : INTEGER; + C_GEN_F0_VFRAME_SIZE : INTEGER; + C_GEN_F1_VFRAME_SIZE : INTEGER; + C_GEN_HSYNC_START : INTEGER; + C_GEN_HSYNC_END : INTEGER; + C_GEN_F0_VBLANK_HSTART : INTEGER; + C_GEN_F0_VBLANK_HEND : INTEGER; + C_GEN_F0_VSYNC_VSTART : INTEGER; + C_GEN_F0_VSYNC_VEND : INTEGER; + C_GEN_F0_VSYNC_HSTART : INTEGER; + C_GEN_F0_VSYNC_HEND : INTEGER; + C_GEN_F1_VBLANK_HSTART : INTEGER; + C_GEN_F1_VBLANK_HEND : INTEGER; + C_GEN_F1_VSYNC_VSTART : INTEGER; + C_GEN_F1_VSYNC_VEND : INTEGER; + C_GEN_F1_VSYNC_HSTART : INTEGER; + C_GEN_F1_VSYNC_HEND : INTEGER; + C_FSYNC_HSTART0 : INTEGER; + C_FSYNC_VSTART0 : INTEGER; + C_FSYNC_HSTART1 : INTEGER; + C_FSYNC_VSTART1 : INTEGER; + C_FSYNC_HSTART2 : INTEGER; + C_FSYNC_VSTART2 : INTEGER; + C_FSYNC_HSTART3 : INTEGER; + C_FSYNC_VSTART3 : INTEGER; + C_FSYNC_HSTART4 : INTEGER; + C_FSYNC_VSTART4 : INTEGER; + C_FSYNC_HSTART5 : INTEGER; + C_FSYNC_VSTART5 : INTEGER; + C_FSYNC_HSTART6 : INTEGER; + C_FSYNC_VSTART6 : INTEGER; + C_FSYNC_HSTART7 : INTEGER; + C_FSYNC_VSTART7 : INTEGER; + C_FSYNC_HSTART8 : INTEGER; + C_FSYNC_VSTART8 : INTEGER; + C_FSYNC_HSTART9 : INTEGER; + C_FSYNC_VSTART9 : INTEGER; + C_FSYNC_HSTART10 : INTEGER; + C_FSYNC_VSTART10 : INTEGER; + C_FSYNC_HSTART11 : INTEGER; + C_FSYNC_VSTART11 : INTEGER; + C_FSYNC_HSTART12 : INTEGER; + C_FSYNC_VSTART12 : INTEGER; + C_FSYNC_HSTART13 : INTEGER; + C_FSYNC_VSTART13 : INTEGER; + C_FSYNC_HSTART14 : INTEGER; + C_FSYNC_VSTART14 : INTEGER; + C_FSYNC_HSTART15 : INTEGER; + C_FSYNC_VSTART15 : INTEGER; + C_MAX_PIXELS : INTEGER; + C_MAX_LINES : INTEGER; + C_NUM_FSYNCS : INTEGER; + C_INTERLACE_EN : INTEGER; + C_GEN_AUTO_SWITCH : INTEGER; + C_DETECT_EN : INTEGER; + C_SYNC_EN : INTEGER; + C_GENERATE_EN : INTEGER; + C_DET_HSYNC_EN : INTEGER; + C_DET_VSYNC_EN : INTEGER; + C_DET_HBLANK_EN : INTEGER; + C_DET_VBLANK_EN : INTEGER; + C_DET_AVIDEO_EN : INTEGER; + C_DET_ACHROMA_EN : INTEGER; + C_GEN_HSYNC_EN : INTEGER; + C_GEN_VSYNC_EN : INTEGER; + C_GEN_HBLANK_EN : INTEGER; + C_GEN_VBLANK_EN : INTEGER; + C_GEN_AVIDEO_EN : INTEGER; + C_GEN_ACHROMA_EN : INTEGER; + C_GEN_FIELDID_EN : INTEGER; + C_DET_FIELDID_EN : INTEGER + ); + PORT ( + clk : IN STD_LOGIC; + clken : IN STD_LOGIC; + s_axi_aclk : IN STD_LOGIC; + s_axi_aclken : IN STD_LOGIC; + det_clken : IN STD_LOGIC; + gen_clken : IN STD_LOGIC; + intc_if : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + field_id_in : IN STD_LOGIC; + hsync_in : IN STD_LOGIC; + hblank_in : IN STD_LOGIC; + vsync_in : IN STD_LOGIC; + vblank_in : IN STD_LOGIC; + active_video_in : IN STD_LOGIC; + active_chroma_in : IN STD_LOGIC; + field_id_out : OUT STD_LOGIC; + hsync_out : OUT STD_LOGIC; + hblank_out : OUT STD_LOGIC; + vsync_out : OUT STD_LOGIC; + vblank_out : OUT STD_LOGIC; + active_video_out : OUT STD_LOGIC; + active_chroma_out : OUT STD_LOGIC; + resetn : IN STD_LOGIC; + s_axi_aresetn : IN STD_LOGIC; + s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_awvalid : IN STD_LOGIC; + s_axi_awready : OUT STD_LOGIC; + s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + s_axi_wvalid : IN STD_LOGIC; + s_axi_wready : OUT STD_LOGIC; + s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_bvalid : OUT STD_LOGIC; + s_axi_bready : IN STD_LOGIC; + s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + s_axi_arvalid : IN STD_LOGIC; + s_axi_arready : OUT STD_LOGIC; + s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + s_axi_rvalid : OUT STD_LOGIC; + s_axi_rready : IN STD_LOGIC; + irq : OUT STD_LOGIC; + fsync_in : IN STD_LOGIC; + fsync_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); + END COMPONENT v_tc; + ATTRIBUTE X_CORE_INFO : STRING; + ATTRIBUTE X_CORE_INFO OF Arty_Z7_20_v_tc_1_0_arch: ARCHITECTURE IS "v_tc,Vivado 2016.4"; + ATTRIBUTE CHECK_LICENSE_TYPE : STRING; + ATTRIBUTE CHECK_LICENSE_TYPE OF Arty_Z7_20_v_tc_1_0_arch : ARCHITECTURE IS "Arty_Z7_20_v_tc_1_0,v_tc,{}"; + ATTRIBUTE CORE_GENERATION_INFO : STRING; + ATTRIBUTE CORE_GENERATION_INFO OF Arty_Z7_20_v_tc_1_0_arch: ARCHITECTURE IS "Arty_Z7_20_v_tc_1_0,v_tc,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=v_tc,x_ipVersion=6.1,x_ipCoreRevision=10,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_HAS_AXI4_LITE=1,C_HAS_INTC_IF=1,C_GEN_INTERLACED=0,C_GEN_HACTIVE_SIZE=1280,C_GEN_VACTIVE_SIZE=720,C_GEN_CPARITY=0,C_GEN_FIELDID_POLARITY=1,C_GEN_VBLANK_POLARITY=1,C_GEN_HBLANK_POLARITY=1,C_GEN_VSYNC_POLARITY=1,C_GEN_HSYNC_POLARITY=1,C_GEN_AVIDEO_POLARITY=1,C_GEN_ACHROMA_POLARITY=1,C_GEN_VIDEO_FORMAT=2,C_GEN_HFRAME_SIZ" & +"E=1650,C_GEN_F0_VFRAME_SIZE=750,C_GEN_F1_VFRAME_SIZE=750,C_GEN_HSYNC_START=1390,C_GEN_HSYNC_END=1430,C_GEN_F0_VBLANK_HSTART=1280,C_GEN_F0_VBLANK_HEND=1280,C_GEN_F0_VSYNC_VSTART=724,C_GEN_F0_VSYNC_VEND=729,C_GEN_F0_VSYNC_HSTART=1280,C_GEN_F0_VSYNC_HEND=1280,C_GEN_F1_VBLANK_HSTART=1280,C_GEN_F1_VBLANK_HEND=1280,C_GEN_F1_VSYNC_VSTART=724,C_GEN_F1_VSYNC_VEND=729,C_GEN_F1_VSYNC_HSTART=1280,C_GEN_F1_VSYNC_HEND=1280,C_FSYNC_HSTART0=0,C_FSYNC_VSTART0=0,C_FSYNC_HSTART1=0,C_FSYNC_VSTART1=0,C_FSYNC_HSTART2" & +"=0,C_FSYNC_VSTART2=0,C_FSYNC_HSTART3=0,C_FSYNC_VSTART3=0,C_FSYNC_HSTART4=0,C_FSYNC_VSTART4=0,C_FSYNC_HSTART5=0,C_FSYNC_VSTART5=0,C_FSYNC_HSTART6=0,C_FSYNC_VSTART6=0,C_FSYNC_HSTART7=0,C_FSYNC_VSTART7=0,C_FSYNC_HSTART8=0,C_FSYNC_VSTART8=0,C_FSYNC_HSTART9=0,C_FSYNC_VSTART9=0,C_FSYNC_HSTART10=0,C_FSYNC_VSTART10=0,C_FSYNC_HSTART11=0,C_FSYNC_VSTART11=0,C_FSYNC_HSTART12=0,C_FSYNC_VSTART12=0,C_FSYNC_HSTART13=0,C_FSYNC_VSTART13=0,C_FSYNC_HSTART14=0,C_FSYNC_VSTART14=0,C_FSYNC_HSTART15=0,C_FSYNC_VSTART15=0" & +",C_MAX_PIXELS=4096,C_MAX_LINES=2048,C_NUM_FSYNCS=1,C_INTERLACE_EN=0,C_GEN_AUTO_SWITCH=0,C_DETECT_EN=1,C_SYNC_EN=0,C_GENERATE_EN=0,C_DET_HSYNC_EN=1,C_DET_VSYNC_EN=1,C_DET_HBLANK_EN=0,C_DET_VBLANK_EN=0,C_DET_AVIDEO_EN=1,C_DET_ACHROMA_EN=0,C_GEN_HSYNC_EN=1,C_GEN_VSYNC_EN=1,C_GEN_HBLANK_EN=1,C_GEN_VBLANK_EN=1,C_GEN_AVIDEO_EN=1,C_GEN_ACHROMA_EN=0,C_GEN_FIELDID_EN=0,C_DET_FIELDID_EN=0}"; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK"; + ATTRIBUTE X_INTERFACE_INFO OF clken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 clken_intf CE"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk_intf CLK"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 s_axi_aclken_intf CE"; + ATTRIBUTE X_INTERFACE_INFO OF hsync_in: SIGNAL IS "xilinx.com:interface:video_timing:2.0 vtiming_in HSYNC"; + ATTRIBUTE X_INTERFACE_INFO OF vsync_in: SIGNAL IS "xilinx.com:interface:video_timing:2.0 vtiming_in VSYNC"; + ATTRIBUTE X_INTERFACE_INFO OF active_video_in: SIGNAL IS "xilinx.com:interface:video_timing:2.0 vtiming_in ACTIVE_VIDEO"; + ATTRIBUTE X_INTERFACE_INFO OF resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 resetn_intf RST"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_axi_aresetn_intf RST"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl AWADDR"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl AWVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl AWREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WDATA"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WSTRB"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl BRESP"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl BVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl BREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl ARADDR"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl ARVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl ARREADY"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RDATA"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RRESP"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RREADY"; + ATTRIBUTE X_INTERFACE_INFO OF irq: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IRQ INTERRUPT"; +BEGIN + U0 : v_tc + GENERIC MAP ( + C_HAS_AXI4_LITE => 1, + C_HAS_INTC_IF => 1, + C_GEN_INTERLACED => 0, + C_GEN_HACTIVE_SIZE => 1280, + C_GEN_VACTIVE_SIZE => 720, + C_GEN_CPARITY => 0, + C_GEN_FIELDID_POLARITY => 1, + C_GEN_VBLANK_POLARITY => 1, + C_GEN_HBLANK_POLARITY => 1, + C_GEN_VSYNC_POLARITY => 1, + C_GEN_HSYNC_POLARITY => 1, + C_GEN_AVIDEO_POLARITY => 1, + C_GEN_ACHROMA_POLARITY => 1, + C_GEN_VIDEO_FORMAT => 2, + C_GEN_HFRAME_SIZE => 1650, + C_GEN_F0_VFRAME_SIZE => 750, + C_GEN_F1_VFRAME_SIZE => 750, + C_GEN_HSYNC_START => 1390, + C_GEN_HSYNC_END => 1430, + C_GEN_F0_VBLANK_HSTART => 1280, + C_GEN_F0_VBLANK_HEND => 1280, + C_GEN_F0_VSYNC_VSTART => 724, + C_GEN_F0_VSYNC_VEND => 729, + C_GEN_F0_VSYNC_HSTART => 1280, + C_GEN_F0_VSYNC_HEND => 1280, + C_GEN_F1_VBLANK_HSTART => 1280, + C_GEN_F1_VBLANK_HEND => 1280, + C_GEN_F1_VSYNC_VSTART => 724, + C_GEN_F1_VSYNC_VEND => 729, + C_GEN_F1_VSYNC_HSTART => 1280, + C_GEN_F1_VSYNC_HEND => 1280, + C_FSYNC_HSTART0 => 0, + C_FSYNC_VSTART0 => 0, + C_FSYNC_HSTART1 => 0, + C_FSYNC_VSTART1 => 0, + C_FSYNC_HSTART2 => 0, + C_FSYNC_VSTART2 => 0, + C_FSYNC_HSTART3 => 0, + C_FSYNC_VSTART3 => 0, + C_FSYNC_HSTART4 => 0, + C_FSYNC_VSTART4 => 0, + C_FSYNC_HSTART5 => 0, + C_FSYNC_VSTART5 => 0, + C_FSYNC_HSTART6 => 0, + C_FSYNC_VSTART6 => 0, + C_FSYNC_HSTART7 => 0, + C_FSYNC_VSTART7 => 0, + C_FSYNC_HSTART8 => 0, + C_FSYNC_VSTART8 => 0, + C_FSYNC_HSTART9 => 0, + C_FSYNC_VSTART9 => 0, + C_FSYNC_HSTART10 => 0, + C_FSYNC_VSTART10 => 0, + C_FSYNC_HSTART11 => 0, + C_FSYNC_VSTART11 => 0, + C_FSYNC_HSTART12 => 0, + C_FSYNC_VSTART12 => 0, + C_FSYNC_HSTART13 => 0, + C_FSYNC_VSTART13 => 0, + C_FSYNC_HSTART14 => 0, + C_FSYNC_VSTART14 => 0, + C_FSYNC_HSTART15 => 0, + C_FSYNC_VSTART15 => 0, + C_MAX_PIXELS => 4096, + C_MAX_LINES => 2048, + C_NUM_FSYNCS => 1, + C_INTERLACE_EN => 0, + C_GEN_AUTO_SWITCH => 0, + C_DETECT_EN => 1, + C_SYNC_EN => 0, + C_GENERATE_EN => 0, + C_DET_HSYNC_EN => 1, + C_DET_VSYNC_EN => 1, + C_DET_HBLANK_EN => 0, + C_DET_VBLANK_EN => 0, + C_DET_AVIDEO_EN => 1, + C_DET_ACHROMA_EN => 0, + C_GEN_HSYNC_EN => 1, + C_GEN_VSYNC_EN => 1, + C_GEN_HBLANK_EN => 1, + C_GEN_VBLANK_EN => 1, + C_GEN_AVIDEO_EN => 1, + C_GEN_ACHROMA_EN => 0, + C_GEN_FIELDID_EN => 0, + C_DET_FIELDID_EN => 0 + ) + PORT MAP ( + clk => clk, + clken => clken, + s_axi_aclk => s_axi_aclk, + s_axi_aclken => s_axi_aclken, + det_clken => det_clken, + gen_clken => '1', + intc_if => intc_if, + field_id_in => '0', + hsync_in => hsync_in, + hblank_in => '0', + vsync_in => vsync_in, + vblank_in => '0', + active_video_in => active_video_in, + active_chroma_in => '0', + resetn => resetn, + s_axi_aresetn => s_axi_aresetn, + s_axi_awaddr => s_axi_awaddr, + s_axi_awvalid => s_axi_awvalid, + s_axi_awready => s_axi_awready, + s_axi_wdata => s_axi_wdata, + s_axi_wstrb => s_axi_wstrb, + s_axi_wvalid => s_axi_wvalid, + s_axi_wready => s_axi_wready, + s_axi_bresp => s_axi_bresp, + s_axi_bvalid => s_axi_bvalid, + s_axi_bready => s_axi_bready, + s_axi_araddr => s_axi_araddr, + s_axi_arvalid => s_axi_arvalid, + s_axi_arready => s_axi_arready, + s_axi_rdata => s_axi_rdata, + s_axi_rresp => s_axi_rresp, + s_axi_rvalid => s_axi_rvalid, + s_axi_rready => s_axi_rready, + irq => irq, + fsync_in => '0' + ); +END Arty_Z7_20_v_tc_1_0_arch; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/Arty_Z7_20_v_vid_in_axi4s_0_0.dcp b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/Arty_Z7_20_v_vid_in_axi4s_0_0.dcp new file mode 100644 index 0000000..ef24dd9 Binary files /dev/null and b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/Arty_Z7_20_v_vid_in_axi4s_0_0.dcp differ diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/Arty_Z7_20_v_vid_in_axi4s_0_0.xci b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/Arty_Z7_20_v_vid_in_axi4s_0_0.xci new file mode 100644 index 0000000..8c8453e --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/Arty_Z7_20_v_vid_in_axi4s_0_0.xci @@ -0,0 +1,96 @@ + + + xilinx.com + xci + unknown + 1.0 + + + Arty_Z7_20_v_vid_in_axi4s_0_0 + + + ACTIVE_LOW + + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 + 118181816 + 0.000 + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 + 118181816 + 0 + 1 + 1 + 0 + xilinx.com:interface:datatypes:1.0 {TDATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value xilinx.com:video:G_B_R_444:1.0} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 24} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value rows} size {attribs {resolve_type generated dependency active_rows format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency active_rows_stride format long minimum {} maximum {}} value 24} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 24} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value cols} size {attribs {resolve_type generated dependency active_cols format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency active_cols_stride format long minimum {} maximum {}} value 24} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 24} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} struct {field_G {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value G} enabled {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency video_data_width format long minimum {} maximum {}} value 8} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}} field_B {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value B} enabled {attribs {resolve_type generated dependency video_comp1_enabled format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency video_data_width format long minimum {} maximum {}} value 8} bitoffset {attribs {resolve_type generated dependency video_comp1_offset format long minimum {} maximum {}} value 8} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}} field_R {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value R} enabled {attribs {resolve_type generated dependency video_comp2_enabled format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency video_data_width format long minimum {} maximum {}} value 8} bitoffset {attribs {resolve_type generated dependency video_comp2_offset format long minimum {} maximum {}} value 16} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}}}}}}} TDATA_WIDTH 24} + 0.000 + 3 + 0 + 0 + 1 + ACTIVE_LOW + + Arty_Z7_20_dvi2rgb_0_0_PixelClk + 100000000 + 0.000 + 12 + 3 + zynq + 1 + 8 + 24 + 8 + 24 + 1 + 12 + 1 + 8 + 2 + 8 + 1 + Arty_Z7_20_v_vid_in_axi4s_0_0 + zynq + digilentinc.com:arty-z7-20:part0:1.0 + xc7z020 + clg400 + VHDL + + MIXED + -1 + + TRUE + TRUE + 91c144ee895ff769 + IP_Integrator + 5 + TRUE + . + + ../../ipshared + 2016.4 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/Arty_Z7_20_v_vid_in_axi4s_0_0.xml b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/Arty_Z7_20_v_vid_in_axi4s_0_0.xml new file mode 100644 index 0000000..dd87128 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/Arty_Z7_20_v_vid_in_axi4s_0_0.xml @@ -0,0 +1,1399 @@ + + + xilinx.com + customized_ip + Arty_Z7_20_v_vid_in_axi4s_0_0 + 1.0 + + + video_out + VIDEO_OUT + Output Bus. Video over AXI4-Stream + + + + + + + TDATA + + + m_axis_video_tdata + + + + + TLAST + + + m_axis_video_tlast + + + + + TREADY + + + m_axis_video_tready + + + + + TUSER + + + m_axis_video_tuser + + + + + TVALID + + + m_axis_video_tvalid + + + + + + TDATA_NUM_BYTES + 3 + + + TDEST_WIDTH + 0 + + + TID_WIDTH + 0 + + + TUSER_WIDTH + 1 + + + HAS_TREADY + 1 + + + HAS_TSTRB + 0 + + + HAS_TKEEP + 0 + + + HAS_TLAST + 1 + + + FREQ_HZ + 118181816 + + + PHASE + 0.000 + + + CLK_DOMAIN + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 + + + LAYERED_METADATA + xilinx.com:interface:datatypes:1.0 {TDATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value xilinx.com:video:G_B_R_444:1.0} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 24} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value rows} size {attribs {resolve_type generated dependency active_rows format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency active_rows_stride format long minimum {} maximum {}} value 24} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 24} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value cols} size {attribs {resolve_type generated dependency active_cols format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency active_cols_stride format long minimum {} maximum {}} value 24} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 24} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} struct {field_G {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value G} enabled {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency video_data_width format long minimum {} maximum {}} value 8} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}} field_B {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value B} enabled {attribs {resolve_type generated dependency video_comp1_enabled format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency video_data_width format long minimum {} maximum {}} value 8} bitoffset {attribs {resolve_type generated dependency video_comp1_offset format long minimum {} maximum {}} value 8} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}} field_R {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value R} enabled {attribs {resolve_type generated dependency video_comp2_enabled format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency video_data_width format long minimum {} maximum {}} value 8} bitoffset {attribs {resolve_type generated dependency video_comp2_offset format long minimum {} maximum {}} value 16} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}}}}}}} TDATA_WIDTH 24} + + + + + vtiming_out + VTIMING_OUT + Video sync and timing signals + + + + + + + ACTIVE_VIDEO + + + vtd_active_video + + + + + FIELD + + + vtd_field_id + + + + + HBLANK + + + vtd_hblank + + + + + HSYNC + + + vtd_hsync + + + + + VBLANK + + + vtd_vblank + + + + + VSYNC + + + vtd_vsync + + + + + + vid_io_in_clk_intf + + + + + + + CLK + + + vid_io_in_clk + + + + + + ASSOCIATED_BUSIF + vid_io_in + + + FREQ_HZ + vid-in clock frequency + vid-in clock frequency + 100000000 + + + PHASE + 0.000 + + + CLK_DOMAIN + Arty_Z7_20_dvi2rgb_0_0_PixelClk + + + ASSOCIATED_RESET + + + + + + + true + + + + + + aclk_intf + + + + + + + CLK + + + aclk + + + + + + ASSOCIATED_BUSIF + video_out + + + FREQ_HZ + vid-out clock frequency + vid-out clock frequency + 118181816 + + + PHASE + 0.000 + + + CLK_DOMAIN + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 + + + ASSOCIATED_RESET + + + + + + aresetn_intf + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + vid_io_in_ce_intf + + + + + + + CE + + + vid_io_in_ce + + + + + + POLARITY + ACTIVE_LOW + + + + + aclken_intf + + + + + + + CE + + + aclken + + + + + + POLARITY + ACTIVE_LOW + + + + + vid_io_in + VID_IO_IN + Input bus. Video data, sync, and timing. + + + + + + + ACTIVE_VIDEO + + + vid_active_video + + + + + DATA + + + vid_data + + + + + FIELD + + + vid_field_id + + + + + HBLANK + + + vid_hblank + + + + + HSYNC + + + vid_hsync + + + + + VBLANK + + + vid_vblank + + + + + VSYNC + + + vid_vsync + + + + + + vid_io_in_reset_intf + RST + system reset + + + + + + + RST + + + vid_io_in_reset + + + + + + POLARITY + ACTIVE_HIGH + + + + + + true + + + + + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Mon Mar 06 02:56:08 UTC 2017 + + + boundaryCRC + d8c9dac4 + + + boundaryCRCversion + 1 + + + customizationCRC + 67f35dce + + + customizationCRCversion + 6 + + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + + xilinx_verilogsynthesis_xilinx_com_ip_blk_mem_gen_8_3__ref_view_fileset + + + xilinx_verilogsynthesis_xilinx_com_ip_fifo_generator_13_1__ref_view_fileset + + + xilinx_verilogsynthesis_view_fileset + + + + GENtimestamp + Fri Feb 24 23:58:24 UTC 2017 + + + boundaryCRC + d8c9dac4 + + + boundaryCRCversion + 1 + + + customizationCRC + 67f35dce + + + customizationCRCversion + 6 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + xilinx_synthesisconstraints_view_fileset + + + + GENtimestamp + Mon Mar 06 02:55:59 UTC 2017 + + + boundaryCRC + d8c9dac4 + + + boundaryCRCversion + 1 + + + customizationCRC + 67f35dce + + + customizationCRCversion + 6 + + + + + xilinx_verilogsynthesiswrapper + Verilog Synthesis Wrapper + verilogSource:vivado.xilinx.com:synthesis.wrapper + verilog + + xilinx_verilogsynthesiswrapper_view_fileset + + + + GENtimestamp + Mon Mar 06 02:55:59 UTC 2017 + + + boundaryCRC + d8c9dac4 + + + boundaryCRCversion + 1 + + + customizationCRC + 67f35dce + + + customizationCRCversion + 6 + + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_fifo_generator_13_1__ref_view_fileset + + + xilinx_verilogbehavioralsimulation_view_fileset + + + + GENtimestamp + Fri Feb 24 23:58:24 UTC 2017 + + + boundaryCRC + d8c9dac4 + + + boundaryCRCversion + 1 + + + customizationCRC + 4b9ed761 + + + customizationCRCversion + 6 + + + + + xilinx_verilogsimulationwrapper + Verilog Simulation Wrapper + verilogSource:vivado.xilinx.com:simulation.wrapper + verilog + + xilinx_verilogsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Mar 06 02:55:59 UTC 2017 + + + boundaryCRC + d8c9dac4 + + + boundaryCRCversion + 1 + + + customizationCRC + 4b9ed761 + + + customizationCRCversion + 6 + + + + + + + vid_io_in_clk + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + vid_io_in_ce + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 1 + + + + + vid_io_in_reset + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + + true + + + + + + vid_active_video + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + vid_vblank + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + vid_hblank + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + vid_vsync + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + vid_hsync + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + vid_field_id + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0 + + + + + vid_data + + in + + 23 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + aclk + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + aclken + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 1 + + + + + aresetn + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 1 + + + + + m_axis_video_tdata + + out + + 23 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axis_video_tvalid + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axis_video_tready + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axis_video_tuser + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axis_video_tlast + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + fid + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + vtd_active_video + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + vtd_vblank + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + vtd_hblank + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + vtd_vsync + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + vtd_hsync + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + vtd_field_id + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + overflow + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + underflow + + out + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + axis_enable + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 1 + + + + + + + C_FAMILY + zynq + + + C_PIXELS_PER_CLOCK + Pixels Per Clock + 1 + + + C_COMPONENTS_PER_PIXEL + Components Per pixel + 3 + + + C_M_AXIS_COMPONENT_WIDTH + Output Component Width + 8 + + + C_NATIVE_COMPONENT_WIDTH + Input Component Width + 8 + + + C_NATIVE_DATA_WIDTH + Native Video Input Data Width + 24 + + + C_M_AXIS_TDATA_WIDTH + AXI4S Video Output Data Width + 24 + + + C_HAS_ASYNC_CLK + Clock Mode + 1 + + + C_ADDR_WIDTH + Address Width + 12 + + + + + + choice_list_aa031417 + 1 + 2 + 3 + 4 + + + choice_list_dd2843c6 + 1 + 2 + 4 + 8 + + + choice_list_f1407c6a + 8 + 10 + 12 + 16 + + + choice_pairs_1d612f7f + 0 + 1 + + + choice_pairs_2ccd4550 + 5 + 10 + 11 + 12 + 13 + + + choice_pairs_702fcbbd + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + + + + + xilinx_externalfiles_view_fileset + + Arty_Z7_20_v_vid_in_axi4s_0_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + Arty_Z7_20_v_vid_in_axi4s_0_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Arty_Z7_20_v_vid_in_axi4s_0_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Arty_Z7_20_v_vid_in_axi4s_0_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Arty_Z7_20_v_vid_in_axi4s_0_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx_verilogsynthesis_xilinx_com_ip_blk_mem_gen_8_3__ref_view_fileset + + ../../ipshared/6273/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd + vhdlSource + blk_mem_gen_v8_3_5 + + + + + + + + + + + xilinx_verilogsynthesis_xilinx_com_ip_fifo_generator_13_1__ref_view_fileset + + ../../ipshared/564d/hdl/fifo_generator_v13_1_vhsyn_rfs.vhd + vhdlSource + fifo_generator_v13_1_3 + + + + + + + + + + + xilinx_verilogsynthesis_view_fileset + + Arty_Z7_20_v_vid_in_axi4s_0_0_clocks.xdc + xdc + USED_IN_implementation + USED_IN_synthesis + + processing_order + late + + + + ../../ipshared/3c71/hdl/v_vid_in_axi4s_v4_0_vl_rfs.v + verilogSource + v_vid_in_axi4s_v4_0_5 + + + + xilinx_synthesisconstraints_view_fileset + + Arty_Z7_20_v_vid_in_axi4s_0_0_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/Arty_Z7_20_v_vid_in_axi4s_0_0.v + verilogSource + xil_defaultlib + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_fifo_generator_13_1__ref_view_fileset + + ../../ipshared/564d/simulation/fifo_generator_vlog_beh.v + verilogSource + USED_IN_ipstatic + fifo_generator_v13_1_3 + fifo_generator_vlog_beh + + + ../../ipshared/564d/hdl/fifo_generator_v13_1_rfs.vhd + vhdlSource + USED_IN_ipstatic + fifo_generator_v13_1_3 + + + ../../ipshared/564d/hdl/fifo_generator_v13_1_rfs.v + verilogSource + USED_IN_ipstatic + fifo_generator_v13_1_3 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + ../../ipshared/3c71/hdl/v_vid_in_axi4s_v4_0_vl_rfs.v + verilogSource + USED_IN_ipstatic + v_vid_in_axi4s_v4_0_5 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/Arty_Z7_20_v_vid_in_axi4s_0_0.v + verilogSource + xil_defaultlib + + + + Video bridge converting native video to AXI4-Stream. + + + Component_Name + Arty_Z7_20_v_vid_in_axi4s_0_0 + + + + true + + + + + + C_PIXELS_PER_CLOCK + Pixels Per Clock + 1 + + + + true + + + + + + C_M_AXIS_VIDEO_FORMAT + Video Format + 2 + + + + true + + + + + + C_M_AXIS_VIDEO_DATA_WIDTH + Output Component Width + 8 + + + + true + + + + + + C_NATIVE_COMPONENT_WIDTH + Input Component Width + 8 + + + + true + + + + + + C_HAS_ASYNC_CLK + Clock Mode + 1 + + + + true + + + + + + C_ADDR_WIDTH + Address Width + 12 + + + + true + + + + + + + + Video In to AXI4-Stream + 5 + + + + + + + + + + + + + + + + + + + + + + 2016.4 + + + + + + + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/Arty_Z7_20_v_vid_in_axi4s_0_0_clocks.xdc b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/Arty_Z7_20_v_vid_in_axi4s_0_0_clocks.xdc new file mode 100644 index 0000000..cc0c5dd --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/Arty_Z7_20_v_vid_in_axi4s_0_0_clocks.xdc @@ -0,0 +1,17 @@ + +#------------------------------------------------------------------------------# +# Native FIFO Constraints # +#------------------------------------------------------------------------------# +set fg_root {COUPLER_INST/FIFO_INST} +set wr_clock [get_clocks -of_objects [get_ports vid_io_in_clk]] +set rd_clock [get_clocks -of_objects [get_ports aclk]] + +# Set max delay on cross clock domain path for Block RAM based FIFO +set_max_delay -from [get_cells ${fg_root}/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*rd_pntr_gc_reg[*]] -to [get_cells ${fg_root}/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[*].wr_stg_inst/Q_reg_reg[*]] -datapath_only [get_property -min PERIOD $rd_clock] +set_max_delay -from [get_cells ${fg_root}/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*wr_pntr_gc_reg[*]] -to [get_cells ${fg_root}/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[*].rd_stg_inst/Q_reg_reg[*]] -datapath_only [get_property -min PERIOD $wr_clock] + +# Set false path on the reset synchronizers +set_false_path -through [get_ports aresetn] -to [get_pins -hierarchical -filter {NAME =~ */COUPLER_INST/FIFO_INST/inst_fifo_gen/gconvfifo.rf/grf.rf/*rstblk*/*PRE*}] +set_false_path -through [get_ports vid_io_in_reset] -to [get_pins -hierarchical -filter {NAME =~ */COUPLER_INST/FIFO_INST/inst_fifo_gen/gconvfifo.rf/grf.rf/*rstblk*/*PRE*}] +set_false_path -from [get_cells -hierarchical -filter {NAME =~ */COUPLER_INST/FIFO_INST/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/*rst_reg_reg[*]}] + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/Arty_Z7_20_v_vid_in_axi4s_0_0_ooc.xdc b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/Arty_Z7_20_v_vid_in_axi4s_0_0_ooc.xdc new file mode 100644 index 0000000..9b64826 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/Arty_Z7_20_v_vid_in_axi4s_0_0_ooc.xdc @@ -0,0 +1,59 @@ +# (c) Copyright 2012-2017 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +# DO NOT MODIFY THIS FILE. +# ######################################################### +# +# This XDC is used only in OOC mode for synthesis, implementation +# +# ######################################################### + + +create_clock -period 10 -name vid_io_in_clk [get_ports vid_io_in_clk] + +create_clock -period 8.462 -name aclk [get_ports aclk] + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/Arty_Z7_20_v_vid_in_axi4s_0_0_sim_netlist.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/Arty_Z7_20_v_vid_in_axi4s_0_0_sim_netlist.v new file mode 100644 index 0000000..9d4a48b --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/Arty_Z7_20_v_vid_in_axi4s_0_0_sim_netlist.v @@ -0,0 +1,7779 @@ +// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +// Date : Sat Mar 04 18:56:32 2017 +// Host : WK73 running 64-bit Service Pack 1 (build 7601) +// Command : write_verilog -force -mode funcsim -rename_top Arty_Z7_20_v_vid_in_axi4s_0_0 -prefix +// Arty_Z7_20_v_vid_in_axi4s_0_0_ Arty_Z7_20_v_vid_in_axi4s_0_0_sim_netlist.v +// Design : Arty_Z7_20_v_vid_in_axi4s_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg400-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "Arty_Z7_20_v_vid_in_axi4s_0_0,v_vid_in_axi4s_v4_0_5,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "v_vid_in_axi4s_v4_0_5,Vivado 2016.4" *) +(* NotValidForBitStream *) +module Arty_Z7_20_v_vid_in_axi4s_0_0 + (vid_io_in_clk, + vid_io_in_ce, + vid_io_in_reset, + vid_active_video, + vid_vblank, + vid_hblank, + vid_vsync, + vid_hsync, + vid_field_id, + vid_data, + aclk, + aclken, + aresetn, + m_axis_video_tdata, + m_axis_video_tvalid, + m_axis_video_tready, + m_axis_video_tuser, + m_axis_video_tlast, + fid, + vtd_active_video, + vtd_vblank, + vtd_hblank, + vtd_vsync, + vtd_hsync, + vtd_field_id, + overflow, + underflow, + axis_enable); + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 vid_io_in_clk_intf CLK" *) input vid_io_in_clk; + (* X_INTERFACE_INFO = "xilinx.com:signal:clockenable:1.0 vid_io_in_ce_intf CE" *) input vid_io_in_ce; + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 vid_io_in_reset_intf RST" *) input vid_io_in_reset; + (* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 vid_io_in ACTIVE_VIDEO" *) input vid_active_video; + (* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 vid_io_in VBLANK" *) input vid_vblank; + (* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 vid_io_in HBLANK" *) input vid_hblank; + (* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 vid_io_in VSYNC" *) input vid_vsync; + (* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 vid_io_in HSYNC" *) input vid_hsync; + (* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 vid_io_in FIELD" *) input vid_field_id; + (* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 vid_io_in DATA" *) input [23:0]vid_data; + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk_intf CLK" *) input aclk; + (* X_INTERFACE_INFO = "xilinx.com:signal:clockenable:1.0 aclken_intf CE" *) input aclken; + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn_intf RST" *) input aresetn; + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 video_out TDATA" *) output [23:0]m_axis_video_tdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 video_out TVALID" *) output m_axis_video_tvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 video_out TREADY" *) input m_axis_video_tready; + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 video_out TUSER" *) output m_axis_video_tuser; + (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 video_out TLAST" *) output m_axis_video_tlast; + output fid; + (* X_INTERFACE_INFO = "xilinx.com:interface:video_timing:2.0 vtiming_out ACTIVE_VIDEO" *) output vtd_active_video; + (* X_INTERFACE_INFO = "xilinx.com:interface:video_timing:2.0 vtiming_out VBLANK" *) output vtd_vblank; + (* X_INTERFACE_INFO = "xilinx.com:interface:video_timing:2.0 vtiming_out HBLANK" *) output vtd_hblank; + (* X_INTERFACE_INFO = "xilinx.com:interface:video_timing:2.0 vtiming_out VSYNC" *) output vtd_vsync; + (* X_INTERFACE_INFO = "xilinx.com:interface:video_timing:2.0 vtiming_out HSYNC" *) output vtd_hsync; + (* X_INTERFACE_INFO = "xilinx.com:interface:video_timing:2.0 vtiming_out FIELD" *) output vtd_field_id; + output overflow; + output underflow; + input axis_enable; + + wire aclk; + wire aclken; + wire aresetn; + wire axis_enable; + wire fid; + wire [23:0]m_axis_video_tdata; + wire m_axis_video_tlast; + wire m_axis_video_tready; + wire m_axis_video_tuser; + wire m_axis_video_tvalid; + wire overflow; + wire underflow; + wire vid_active_video; + wire [23:0]vid_data; + wire vid_field_id; + wire vid_hblank; + wire vid_hsync; + wire vid_io_in_ce; + wire vid_io_in_clk; + wire vid_io_in_reset; + wire vid_vblank; + wire vid_vsync; + wire vtd_active_video; + wire vtd_field_id; + wire vtd_hblank; + wire vtd_hsync; + wire vtd_vblank; + wire vtd_vsync; + + (* C_ADDR_WIDTH = "12" *) + (* C_COMPONENTS_PER_PIXEL = "3" *) + (* C_FAMILY = "zynq" *) + (* C_HAS_ASYNC_CLK = "1" *) + (* C_M_AXIS_COMPONENT_WIDTH = "8" *) + (* C_M_AXIS_TDATA_WIDTH = "24" *) + (* C_NATIVE_COMPONENT_WIDTH = "8" *) + (* C_NATIVE_DATA_WIDTH = "24" *) + (* C_PIXELS_PER_CLOCK = "1" *) + (* DowngradeIPIdentifiedWarnings = "yes" *) + Arty_Z7_20_v_vid_in_axi4s_0_0_v_vid_in_axi4s_v4_0_5 inst + (.aclk(aclk), + .aclken(aclken), + .aresetn(aresetn), + .axis_enable(axis_enable), + .fid(fid), + .m_axis_video_tdata(m_axis_video_tdata), + .m_axis_video_tlast(m_axis_video_tlast), + .m_axis_video_tready(m_axis_video_tready), + .m_axis_video_tuser(m_axis_video_tuser), + .m_axis_video_tvalid(m_axis_video_tvalid), + .overflow(overflow), + .underflow(underflow), + .vid_active_video(vid_active_video), + .vid_data(vid_data), + .vid_field_id(vid_field_id), + .vid_hblank(vid_hblank), + .vid_hsync(vid_hsync), + .vid_io_in_ce(vid_io_in_ce), + .vid_io_in_clk(vid_io_in_clk), + .vid_io_in_reset(vid_io_in_reset), + .vid_vblank(vid_vblank), + .vid_vsync(vid_vsync), + .vtd_active_video(vtd_active_video), + .vtd_field_id(vtd_field_id), + .vtd_hblank(vtd_hblank), + .vtd_hsync(vtd_hsync), + .vtd_vblank(vtd_vblank), + .vtd_vsync(vtd_vsync)); +endmodule + +(* C_ADDR_WIDTH = "12" *) (* C_COMPONENTS_PER_PIXEL = "3" *) (* C_FAMILY = "zynq" *) +(* C_HAS_ASYNC_CLK = "1" *) (* C_M_AXIS_COMPONENT_WIDTH = "8" *) (* C_M_AXIS_TDATA_WIDTH = "24" *) +(* C_NATIVE_COMPONENT_WIDTH = "8" *) (* C_NATIVE_DATA_WIDTH = "24" *) (* C_PIXELS_PER_CLOCK = "1" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module Arty_Z7_20_v_vid_in_axi4s_0_0_v_vid_in_axi4s_v4_0_5 + (vid_io_in_clk, + vid_io_in_ce, + vid_io_in_reset, + vid_active_video, + vid_vblank, + vid_hblank, + vid_vsync, + vid_hsync, + vid_field_id, + vid_data, + aclk, + aclken, + aresetn, + m_axis_video_tdata, + m_axis_video_tvalid, + m_axis_video_tready, + m_axis_video_tuser, + m_axis_video_tlast, + fid, + vtd_active_video, + vtd_vblank, + vtd_hblank, + vtd_vsync, + vtd_hsync, + vtd_field_id, + overflow, + underflow, + axis_enable); + input vid_io_in_clk; + input vid_io_in_ce; + input vid_io_in_reset; + input vid_active_video; + input vid_vblank; + input vid_hblank; + input vid_vsync; + input vid_hsync; + input vid_field_id; + input [23:0]vid_data; + input aclk; + input aclken; + input aresetn; + output [23:0]m_axis_video_tdata; + output m_axis_video_tvalid; + input m_axis_video_tready; + output m_axis_video_tuser; + output m_axis_video_tlast; + output fid; + output vtd_active_video; + output vtd_vblank; + output vtd_hblank; + output vtd_vsync; + output vtd_hsync; + output vtd_field_id; + output overflow; + output underflow; + input axis_enable; + + wire FORMATTER_INST_n_34; + wire aclk; + wire aclken; + wire aresetn; + wire axis_enable; + wire de_3; + wire fid; + wire [26:0]idf_data; + wire [23:0]m_axis_video_tdata; + wire m_axis_video_tlast; + wire m_axis_video_tready; + wire m_axis_video_tuser; + wire m_axis_video_tvalid; + wire overflow; + wire underflow; + wire vid_active_video; + wire [23:0]vid_data; + wire vid_field_id; + wire vid_hblank; + wire vid_hsync; + wire vid_io_in_ce; + wire vid_io_in_clk; + wire vid_io_in_reset; + wire vid_vblank; + wire vid_vsync; + wire vtd_active_video; + wire vtd_field_id; + wire vtd_hblank; + wire vtd_hsync; + wire vtd_vblank; + wire vtd_vsync; + + Arty_Z7_20_v_vid_in_axi4s_0_0_v_vid_in_axi4s_v4_0_5_coupler COUPLER_INST + (.FIFO_WR_DATA(idf_data), + .aclk(aclk), + .aclken(aclken), + .aresetn(aresetn), + .de_3(de_3), + .dout({fid,m_axis_video_tuser,m_axis_video_tlast,m_axis_video_tdata}), + .m_axis_video_tready(m_axis_video_tready), + .m_axis_video_tvalid(m_axis_video_tvalid), + .overflow(overflow), + .underflow(underflow), + .vid_io_in_ce(vid_io_in_ce), + .vid_io_in_clk(vid_io_in_clk), + .vid_io_in_reset(vid_io_in_reset), + .vtd_locked_reg(FORMATTER_INST_n_34)); + Arty_Z7_20_v_vid_in_axi4s_0_0_v_vid_in_axi4s_v4_0_5_formatter FORMATTER_INST + (.FIFO_WR_DATA(idf_data), + .axis_enable(axis_enable), + .de_3(de_3), + .vid_active_video(vid_active_video), + .vid_data(vid_data), + .vid_field_id(vid_field_id), + .vid_hblank(vid_hblank), + .vid_hsync(vid_hsync), + .vid_io_in_ce(vid_io_in_ce), + .vid_io_in_clk(vid_io_in_clk), + .vid_io_in_reset(vid_io_in_reset), + .vid_vblank(vid_vblank), + .vid_vsync(vid_vsync), + .vtd_active_video(vtd_active_video), + .vtd_field_id(vtd_field_id), + .vtd_hblank(vtd_hblank), + .vtd_hsync(vtd_hsync), + .vtd_locked_reg_0(FORMATTER_INST_n_34), + .vtd_vblank(vtd_vblank), + .vtd_vsync(vtd_vsync)); +endmodule + +module Arty_Z7_20_v_vid_in_axi4s_0_0_v_vid_in_axi4s_v4_0_5_coupler + (dout, + overflow, + m_axis_video_tvalid, + underflow, + vid_io_in_clk, + aclk, + FIFO_WR_DATA, + aclken, + m_axis_video_tready, + vid_io_in_reset, + de_3, + vtd_locked_reg, + vid_io_in_ce, + aresetn); + output [26:0]dout; + output overflow; + output m_axis_video_tvalid; + output underflow; + input vid_io_in_clk; + input aclk; + input [26:0]FIFO_WR_DATA; + input aclken; + input m_axis_video_tready; + input vid_io_in_reset; + input de_3; + input vtd_locked_reg; + input vid_io_in_ce; + input aresetn; + + wire FIFO_INST_i_1_n_0; + wire [26:0]FIFO_WR_DATA; + wire aclk; + wire aclken; + wire aresetn; + wire de_3; + wire [26:0]dout; + wire empty_i; + wire m_axis_video_tready; + wire m_axis_video_tvalid; + wire overflow; + wire rd_en_i__0; + wire underflow; + wire vid_io_in_ce; + wire vid_io_in_clk; + wire vid_io_in_reset; + wire vtd_locked_reg; + wire wr_en_i__0; + wire wr_rst_busy_i; + wire NLW_FIFO_INST_almost_empty_UNCONNECTED; + wire NLW_FIFO_INST_almost_full_UNCONNECTED; + wire NLW_FIFO_INST_axi_ar_dbiterr_UNCONNECTED; + wire NLW_FIFO_INST_axi_ar_overflow_UNCONNECTED; + wire NLW_FIFO_INST_axi_ar_prog_empty_UNCONNECTED; + wire NLW_FIFO_INST_axi_ar_prog_full_UNCONNECTED; + wire NLW_FIFO_INST_axi_ar_sbiterr_UNCONNECTED; + wire NLW_FIFO_INST_axi_ar_underflow_UNCONNECTED; + wire NLW_FIFO_INST_axi_aw_dbiterr_UNCONNECTED; + wire NLW_FIFO_INST_axi_aw_overflow_UNCONNECTED; + wire NLW_FIFO_INST_axi_aw_prog_empty_UNCONNECTED; + wire NLW_FIFO_INST_axi_aw_prog_full_UNCONNECTED; + wire NLW_FIFO_INST_axi_aw_sbiterr_UNCONNECTED; + wire NLW_FIFO_INST_axi_aw_underflow_UNCONNECTED; + wire NLW_FIFO_INST_axi_b_dbiterr_UNCONNECTED; + wire NLW_FIFO_INST_axi_b_overflow_UNCONNECTED; + wire NLW_FIFO_INST_axi_b_prog_empty_UNCONNECTED; + wire NLW_FIFO_INST_axi_b_prog_full_UNCONNECTED; + wire NLW_FIFO_INST_axi_b_sbiterr_UNCONNECTED; + wire NLW_FIFO_INST_axi_b_underflow_UNCONNECTED; + wire NLW_FIFO_INST_axi_r_dbiterr_UNCONNECTED; + wire NLW_FIFO_INST_axi_r_overflow_UNCONNECTED; + wire NLW_FIFO_INST_axi_r_prog_empty_UNCONNECTED; + wire NLW_FIFO_INST_axi_r_prog_full_UNCONNECTED; + wire NLW_FIFO_INST_axi_r_sbiterr_UNCONNECTED; + wire NLW_FIFO_INST_axi_r_underflow_UNCONNECTED; + wire NLW_FIFO_INST_axi_w_dbiterr_UNCONNECTED; + wire NLW_FIFO_INST_axi_w_overflow_UNCONNECTED; + wire NLW_FIFO_INST_axi_w_prog_empty_UNCONNECTED; + wire NLW_FIFO_INST_axi_w_prog_full_UNCONNECTED; + wire NLW_FIFO_INST_axi_w_sbiterr_UNCONNECTED; + wire NLW_FIFO_INST_axi_w_underflow_UNCONNECTED; + wire NLW_FIFO_INST_axis_dbiterr_UNCONNECTED; + wire NLW_FIFO_INST_axis_overflow_UNCONNECTED; + wire NLW_FIFO_INST_axis_prog_empty_UNCONNECTED; + wire NLW_FIFO_INST_axis_prog_full_UNCONNECTED; + wire NLW_FIFO_INST_axis_sbiterr_UNCONNECTED; + wire NLW_FIFO_INST_axis_underflow_UNCONNECTED; + wire NLW_FIFO_INST_dbiterr_UNCONNECTED; + wire NLW_FIFO_INST_full_UNCONNECTED; + wire NLW_FIFO_INST_m_axi_arvalid_UNCONNECTED; + wire NLW_FIFO_INST_m_axi_awvalid_UNCONNECTED; + wire NLW_FIFO_INST_m_axi_bready_UNCONNECTED; + wire NLW_FIFO_INST_m_axi_rready_UNCONNECTED; + wire NLW_FIFO_INST_m_axi_wlast_UNCONNECTED; + wire NLW_FIFO_INST_m_axi_wvalid_UNCONNECTED; + wire NLW_FIFO_INST_m_axis_tlast_UNCONNECTED; + wire NLW_FIFO_INST_m_axis_tvalid_UNCONNECTED; + wire NLW_FIFO_INST_prog_empty_UNCONNECTED; + wire NLW_FIFO_INST_prog_full_UNCONNECTED; + wire NLW_FIFO_INST_rd_rst_busy_UNCONNECTED; + wire NLW_FIFO_INST_s_axi_arready_UNCONNECTED; + wire NLW_FIFO_INST_s_axi_awready_UNCONNECTED; + wire NLW_FIFO_INST_s_axi_bvalid_UNCONNECTED; + wire NLW_FIFO_INST_s_axi_rlast_UNCONNECTED; + wire NLW_FIFO_INST_s_axi_rvalid_UNCONNECTED; + wire NLW_FIFO_INST_s_axi_wready_UNCONNECTED; + wire NLW_FIFO_INST_s_axis_tready_UNCONNECTED; + wire NLW_FIFO_INST_sbiterr_UNCONNECTED; + wire NLW_FIFO_INST_wr_ack_UNCONNECTED; + wire [4:0]NLW_FIFO_INST_axi_ar_data_count_UNCONNECTED; + wire [4:0]NLW_FIFO_INST_axi_ar_rd_data_count_UNCONNECTED; + wire [4:0]NLW_FIFO_INST_axi_ar_wr_data_count_UNCONNECTED; + wire [4:0]NLW_FIFO_INST_axi_aw_data_count_UNCONNECTED; + wire [4:0]NLW_FIFO_INST_axi_aw_rd_data_count_UNCONNECTED; + wire [4:0]NLW_FIFO_INST_axi_aw_wr_data_count_UNCONNECTED; + wire [4:0]NLW_FIFO_INST_axi_b_data_count_UNCONNECTED; + wire [4:0]NLW_FIFO_INST_axi_b_rd_data_count_UNCONNECTED; + wire [4:0]NLW_FIFO_INST_axi_b_wr_data_count_UNCONNECTED; + wire [12:0]NLW_FIFO_INST_axi_r_data_count_UNCONNECTED; + wire [12:0]NLW_FIFO_INST_axi_r_rd_data_count_UNCONNECTED; + wire [12:0]NLW_FIFO_INST_axi_r_wr_data_count_UNCONNECTED; + wire [12:0]NLW_FIFO_INST_axi_w_data_count_UNCONNECTED; + wire [12:0]NLW_FIFO_INST_axi_w_rd_data_count_UNCONNECTED; + wire [12:0]NLW_FIFO_INST_axi_w_wr_data_count_UNCONNECTED; + wire [12:0]NLW_FIFO_INST_axis_data_count_UNCONNECTED; + wire [12:0]NLW_FIFO_INST_axis_rd_data_count_UNCONNECTED; + wire [12:0]NLW_FIFO_INST_axis_wr_data_count_UNCONNECTED; + wire [12:0]NLW_FIFO_INST_data_count_UNCONNECTED; + wire [31:0]NLW_FIFO_INST_m_axi_araddr_UNCONNECTED; + wire [1:0]NLW_FIFO_INST_m_axi_arburst_UNCONNECTED; + wire [3:0]NLW_FIFO_INST_m_axi_arcache_UNCONNECTED; + wire [0:0]NLW_FIFO_INST_m_axi_arid_UNCONNECTED; + wire [7:0]NLW_FIFO_INST_m_axi_arlen_UNCONNECTED; + wire [0:0]NLW_FIFO_INST_m_axi_arlock_UNCONNECTED; + wire [2:0]NLW_FIFO_INST_m_axi_arprot_UNCONNECTED; + wire [3:0]NLW_FIFO_INST_m_axi_arqos_UNCONNECTED; + wire [3:0]NLW_FIFO_INST_m_axi_arregion_UNCONNECTED; + wire [2:0]NLW_FIFO_INST_m_axi_arsize_UNCONNECTED; + wire [0:0]NLW_FIFO_INST_m_axi_aruser_UNCONNECTED; + wire [31:0]NLW_FIFO_INST_m_axi_awaddr_UNCONNECTED; + wire [1:0]NLW_FIFO_INST_m_axi_awburst_UNCONNECTED; + wire [3:0]NLW_FIFO_INST_m_axi_awcache_UNCONNECTED; + wire [0:0]NLW_FIFO_INST_m_axi_awid_UNCONNECTED; + wire [7:0]NLW_FIFO_INST_m_axi_awlen_UNCONNECTED; + wire [0:0]NLW_FIFO_INST_m_axi_awlock_UNCONNECTED; + wire [2:0]NLW_FIFO_INST_m_axi_awprot_UNCONNECTED; + wire [3:0]NLW_FIFO_INST_m_axi_awqos_UNCONNECTED; + wire [3:0]NLW_FIFO_INST_m_axi_awregion_UNCONNECTED; + wire [2:0]NLW_FIFO_INST_m_axi_awsize_UNCONNECTED; + wire [0:0]NLW_FIFO_INST_m_axi_awuser_UNCONNECTED; + wire [63:0]NLW_FIFO_INST_m_axi_wdata_UNCONNECTED; + wire [0:0]NLW_FIFO_INST_m_axi_wid_UNCONNECTED; + wire [7:0]NLW_FIFO_INST_m_axi_wstrb_UNCONNECTED; + wire [0:0]NLW_FIFO_INST_m_axi_wuser_UNCONNECTED; + wire [7:0]NLW_FIFO_INST_m_axis_tdata_UNCONNECTED; + wire [0:0]NLW_FIFO_INST_m_axis_tdest_UNCONNECTED; + wire [0:0]NLW_FIFO_INST_m_axis_tid_UNCONNECTED; + wire [0:0]NLW_FIFO_INST_m_axis_tkeep_UNCONNECTED; + wire [0:0]NLW_FIFO_INST_m_axis_tstrb_UNCONNECTED; + wire [3:0]NLW_FIFO_INST_m_axis_tuser_UNCONNECTED; + wire [12:0]NLW_FIFO_INST_rd_data_count_UNCONNECTED; + wire [0:0]NLW_FIFO_INST_s_axi_bid_UNCONNECTED; + wire [1:0]NLW_FIFO_INST_s_axi_bresp_UNCONNECTED; + wire [0:0]NLW_FIFO_INST_s_axi_buser_UNCONNECTED; + wire [63:0]NLW_FIFO_INST_s_axi_rdata_UNCONNECTED; + wire [0:0]NLW_FIFO_INST_s_axi_rid_UNCONNECTED; + wire [1:0]NLW_FIFO_INST_s_axi_rresp_UNCONNECTED; + wire [0:0]NLW_FIFO_INST_s_axi_ruser_UNCONNECTED; + wire [12:0]NLW_FIFO_INST_wr_data_count_UNCONNECTED; + + (* C_ADD_NGC_CONSTRAINT = "0" *) + (* C_APPLICATION_TYPE_AXIS = "0" *) + (* C_APPLICATION_TYPE_RACH = "0" *) + (* C_APPLICATION_TYPE_RDCH = "0" *) + (* C_APPLICATION_TYPE_WACH = "0" *) + (* C_APPLICATION_TYPE_WDCH = "0" *) + (* C_APPLICATION_TYPE_WRCH = "0" *) + (* C_AXIS_TDATA_WIDTH = "8" *) + (* C_AXIS_TDEST_WIDTH = "1" *) + (* C_AXIS_TID_WIDTH = "1" *) + (* C_AXIS_TKEEP_WIDTH = "1" *) + (* C_AXIS_TSTRB_WIDTH = "1" *) + (* C_AXIS_TUSER_WIDTH = "4" *) + (* C_AXIS_TYPE = "0" *) + (* C_AXI_ADDR_WIDTH = "32" *) + (* C_AXI_ARUSER_WIDTH = "1" *) + (* C_AXI_AWUSER_WIDTH = "1" *) + (* C_AXI_BUSER_WIDTH = "1" *) + (* C_AXI_DATA_WIDTH = "64" *) + (* C_AXI_ID_WIDTH = "1" *) + (* C_AXI_LEN_WIDTH = "8" *) + (* C_AXI_LOCK_WIDTH = "1" *) + (* C_AXI_RUSER_WIDTH = "1" *) + (* C_AXI_TYPE = "1" *) + (* C_AXI_WUSER_WIDTH = "1" *) + (* C_COMMON_CLOCK = "0" *) + (* C_COUNT_TYPE = "0" *) + (* C_DATA_COUNT_WIDTH = "13" *) + (* C_DEFAULT_VALUE = "BlankString" *) + (* C_DIN_WIDTH = "27" *) + (* C_DIN_WIDTH_AXIS = "1" *) + (* C_DIN_WIDTH_RACH = "32" *) + (* C_DIN_WIDTH_RDCH = "64" *) + (* C_DIN_WIDTH_WACH = "32" *) + (* C_DIN_WIDTH_WDCH = "64" *) + (* C_DIN_WIDTH_WRCH = "2" *) + (* C_DOUT_RST_VAL = "0" *) + (* C_DOUT_WIDTH = "27" *) + (* C_ENABLE_RLOCS = "0" *) + (* C_ENABLE_RST_SYNC = "1" *) + (* C_EN_SAFETY_CKT = "0" *) + (* C_ERROR_INJECTION_TYPE = "0" *) + (* C_ERROR_INJECTION_TYPE_AXIS = "0" *) + (* C_ERROR_INJECTION_TYPE_RACH = "0" *) + (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) + (* C_ERROR_INJECTION_TYPE_WACH = "0" *) + (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) + (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) + (* C_FAMILY = "zynq" *) + (* C_FULL_FLAGS_RST_VAL = "1" *) + (* C_HAS_ALMOST_EMPTY = "0" *) + (* C_HAS_ALMOST_FULL = "0" *) + (* C_HAS_AXIS_TDATA = "1" *) + (* C_HAS_AXIS_TDEST = "0" *) + (* C_HAS_AXIS_TID = "0" *) + (* C_HAS_AXIS_TKEEP = "0" *) + (* C_HAS_AXIS_TLAST = "0" *) + (* C_HAS_AXIS_TREADY = "1" *) + (* C_HAS_AXIS_TSTRB = "0" *) + (* C_HAS_AXIS_TUSER = "1" *) + (* C_HAS_AXI_ARUSER = "0" *) + (* C_HAS_AXI_AWUSER = "0" *) + (* C_HAS_AXI_BUSER = "0" *) + (* C_HAS_AXI_ID = "0" *) + (* C_HAS_AXI_RD_CHANNEL = "1" *) + (* C_HAS_AXI_RUSER = "0" *) + (* C_HAS_AXI_WR_CHANNEL = "1" *) + (* C_HAS_AXI_WUSER = "0" *) + (* C_HAS_BACKUP = "0" *) + (* C_HAS_DATA_COUNT = "0" *) + (* C_HAS_DATA_COUNTS_AXIS = "0" *) + (* C_HAS_DATA_COUNTS_RACH = "0" *) + (* C_HAS_DATA_COUNTS_RDCH = "0" *) + (* C_HAS_DATA_COUNTS_WACH = "0" *) + (* C_HAS_DATA_COUNTS_WDCH = "0" *) + (* C_HAS_DATA_COUNTS_WRCH = "0" *) + (* C_HAS_INT_CLK = "0" *) + (* C_HAS_MASTER_CE = "0" *) + (* C_HAS_MEMINIT_FILE = "0" *) + (* C_HAS_OVERFLOW = "1" *) + (* C_HAS_PROG_FLAGS_AXIS = "0" *) + (* C_HAS_PROG_FLAGS_RACH = "0" *) + (* C_HAS_PROG_FLAGS_RDCH = "0" *) + (* C_HAS_PROG_FLAGS_WACH = "0" *) + (* C_HAS_PROG_FLAGS_WDCH = "0" *) + (* C_HAS_PROG_FLAGS_WRCH = "0" *) + (* C_HAS_RD_DATA_COUNT = "1" *) + (* C_HAS_RD_RST = "0" *) + (* C_HAS_RST = "1" *) + (* C_HAS_SLAVE_CE = "0" *) + (* C_HAS_SRST = "0" *) + (* C_HAS_UNDERFLOW = "1" *) + (* C_HAS_VALID = "1" *) + (* C_HAS_WR_ACK = "0" *) + (* C_HAS_WR_DATA_COUNT = "1" *) + (* C_HAS_WR_RST = "0" *) + (* C_IMPLEMENTATION_TYPE = "2" *) + (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) + (* C_IMPLEMENTATION_TYPE_RACH = "1" *) + (* C_IMPLEMENTATION_TYPE_RDCH = "1" *) + (* C_IMPLEMENTATION_TYPE_WACH = "1" *) + (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) + (* C_IMPLEMENTATION_TYPE_WRCH = "1" *) + (* C_INIT_WR_PNTR_VAL = "0" *) + (* C_INTERFACE_TYPE = "0" *) + (* C_MEMORY_TYPE = "1" *) + (* C_MIF_FILE_NAME = "BlankString" *) + (* C_MSGON_VAL = "1" *) + (* C_OPTIMIZATION_MODE = "0" *) + (* C_OVERFLOW_LOW = "0" *) + (* C_POWER_SAVING_MODE = "0" *) + (* C_PRELOAD_LATENCY = "0" *) + (* C_PRELOAD_REGS = "1" *) + (* C_PRIM_FIFO_TYPE = "1kx36" *) + (* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) + (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) + (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *) + (* C_PRIM_FIFO_TYPE_WACH = "512x36" *) + (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) + (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL = "4" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) + (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) + (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "5" *) + (* C_PROG_EMPTY_TYPE = "0" *) + (* C_PROG_EMPTY_TYPE_AXIS = "0" *) + (* C_PROG_EMPTY_TYPE_RACH = "0" *) + (* C_PROG_EMPTY_TYPE_RDCH = "0" *) + (* C_PROG_EMPTY_TYPE_WACH = "0" *) + (* C_PROG_EMPTY_TYPE_WDCH = "0" *) + (* C_PROG_EMPTY_TYPE_WRCH = "0" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL = "4095" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) + (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) + (* C_PROG_FULL_THRESH_NEGATE_VAL = "4094" *) + (* C_PROG_FULL_TYPE = "0" *) + (* C_PROG_FULL_TYPE_AXIS = "0" *) + (* C_PROG_FULL_TYPE_RACH = "0" *) + (* C_PROG_FULL_TYPE_RDCH = "0" *) + (* C_PROG_FULL_TYPE_WACH = "0" *) + (* C_PROG_FULL_TYPE_WDCH = "0" *) + (* C_PROG_FULL_TYPE_WRCH = "0" *) + (* C_RACH_TYPE = "0" *) + (* C_RDCH_TYPE = "0" *) + (* C_RD_DATA_COUNT_WIDTH = "13" *) + (* C_RD_DEPTH = "4096" *) + (* C_RD_FREQ = "1" *) + (* C_RD_PNTR_WIDTH = "12" *) + (* C_REG_SLICE_MODE_AXIS = "0" *) + (* C_REG_SLICE_MODE_RACH = "0" *) + (* C_REG_SLICE_MODE_RDCH = "0" *) + (* C_REG_SLICE_MODE_WACH = "0" *) + (* C_REG_SLICE_MODE_WDCH = "0" *) + (* C_REG_SLICE_MODE_WRCH = "0" *) + (* C_SELECT_XPM = "0" *) + (* C_SYNCHRONIZER_STAGE = "2" *) + (* C_UNDERFLOW_LOW = "0" *) + (* C_USE_COMMON_OVERFLOW = "0" *) + (* C_USE_COMMON_UNDERFLOW = "0" *) + (* C_USE_DEFAULT_SETTINGS = "0" *) + (* C_USE_DOUT_RST = "1" *) + (* C_USE_ECC = "0" *) + (* C_USE_ECC_AXIS = "0" *) + (* C_USE_ECC_RACH = "0" *) + (* C_USE_ECC_RDCH = "0" *) + (* C_USE_ECC_WACH = "0" *) + (* C_USE_ECC_WDCH = "0" *) + (* C_USE_ECC_WRCH = "0" *) + (* C_USE_EMBEDDED_REG = "1" *) + (* C_USE_FIFO16_FLAGS = "0" *) + (* C_USE_FWFT_DATA_COUNT = "1" *) + (* C_USE_PIPELINE_REG = "0" *) + (* C_VALID_LOW = "0" *) + (* C_WACH_TYPE = "0" *) + (* C_WDCH_TYPE = "0" *) + (* C_WRCH_TYPE = "0" *) + (* C_WR_ACK_LOW = "0" *) + (* C_WR_DATA_COUNT_WIDTH = "13" *) + (* C_WR_DEPTH = "4096" *) + (* C_WR_DEPTH_AXIS = "1024" *) + (* C_WR_DEPTH_RACH = "16" *) + (* C_WR_DEPTH_RDCH = "1024" *) + (* C_WR_DEPTH_WACH = "16" *) + (* C_WR_DEPTH_WDCH = "1024" *) + (* C_WR_DEPTH_WRCH = "16" *) + (* C_WR_FREQ = "1" *) + (* C_WR_PNTR_WIDTH = "12" *) + (* C_WR_PNTR_WIDTH_AXIS = "12" *) + (* C_WR_PNTR_WIDTH_RACH = "4" *) + (* C_WR_PNTR_WIDTH_RDCH = "12" *) + (* C_WR_PNTR_WIDTH_WACH = "4" *) + (* C_WR_PNTR_WIDTH_WDCH = "12" *) + (* C_WR_PNTR_WIDTH_WRCH = "4" *) + (* C_WR_RESPONSE_LATENCY = "1" *) + Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 FIFO_INST + (.almost_empty(NLW_FIFO_INST_almost_empty_UNCONNECTED), + .almost_full(NLW_FIFO_INST_almost_full_UNCONNECTED), + .axi_ar_data_count(NLW_FIFO_INST_axi_ar_data_count_UNCONNECTED[4:0]), + .axi_ar_dbiterr(NLW_FIFO_INST_axi_ar_dbiterr_UNCONNECTED), + .axi_ar_injectdbiterr(1'b0), + .axi_ar_injectsbiterr(1'b0), + .axi_ar_overflow(NLW_FIFO_INST_axi_ar_overflow_UNCONNECTED), + .axi_ar_prog_empty(NLW_FIFO_INST_axi_ar_prog_empty_UNCONNECTED), + .axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), + .axi_ar_prog_full(NLW_FIFO_INST_axi_ar_prog_full_UNCONNECTED), + .axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), + .axi_ar_rd_data_count(NLW_FIFO_INST_axi_ar_rd_data_count_UNCONNECTED[4:0]), + .axi_ar_sbiterr(NLW_FIFO_INST_axi_ar_sbiterr_UNCONNECTED), + .axi_ar_underflow(NLW_FIFO_INST_axi_ar_underflow_UNCONNECTED), + .axi_ar_wr_data_count(NLW_FIFO_INST_axi_ar_wr_data_count_UNCONNECTED[4:0]), + .axi_aw_data_count(NLW_FIFO_INST_axi_aw_data_count_UNCONNECTED[4:0]), + .axi_aw_dbiterr(NLW_FIFO_INST_axi_aw_dbiterr_UNCONNECTED), + .axi_aw_injectdbiterr(1'b0), + .axi_aw_injectsbiterr(1'b0), + .axi_aw_overflow(NLW_FIFO_INST_axi_aw_overflow_UNCONNECTED), + .axi_aw_prog_empty(NLW_FIFO_INST_axi_aw_prog_empty_UNCONNECTED), + .axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), + .axi_aw_prog_full(NLW_FIFO_INST_axi_aw_prog_full_UNCONNECTED), + .axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), + .axi_aw_rd_data_count(NLW_FIFO_INST_axi_aw_rd_data_count_UNCONNECTED[4:0]), + .axi_aw_sbiterr(NLW_FIFO_INST_axi_aw_sbiterr_UNCONNECTED), + .axi_aw_underflow(NLW_FIFO_INST_axi_aw_underflow_UNCONNECTED), + .axi_aw_wr_data_count(NLW_FIFO_INST_axi_aw_wr_data_count_UNCONNECTED[4:0]), + .axi_b_data_count(NLW_FIFO_INST_axi_b_data_count_UNCONNECTED[4:0]), + .axi_b_dbiterr(NLW_FIFO_INST_axi_b_dbiterr_UNCONNECTED), + .axi_b_injectdbiterr(1'b0), + .axi_b_injectsbiterr(1'b0), + .axi_b_overflow(NLW_FIFO_INST_axi_b_overflow_UNCONNECTED), + .axi_b_prog_empty(NLW_FIFO_INST_axi_b_prog_empty_UNCONNECTED), + .axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), + .axi_b_prog_full(NLW_FIFO_INST_axi_b_prog_full_UNCONNECTED), + .axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), + .axi_b_rd_data_count(NLW_FIFO_INST_axi_b_rd_data_count_UNCONNECTED[4:0]), + .axi_b_sbiterr(NLW_FIFO_INST_axi_b_sbiterr_UNCONNECTED), + .axi_b_underflow(NLW_FIFO_INST_axi_b_underflow_UNCONNECTED), + .axi_b_wr_data_count(NLW_FIFO_INST_axi_b_wr_data_count_UNCONNECTED[4:0]), + .axi_r_data_count(NLW_FIFO_INST_axi_r_data_count_UNCONNECTED[12:0]), + .axi_r_dbiterr(NLW_FIFO_INST_axi_r_dbiterr_UNCONNECTED), + .axi_r_injectdbiterr(1'b0), + .axi_r_injectsbiterr(1'b0), + .axi_r_overflow(NLW_FIFO_INST_axi_r_overflow_UNCONNECTED), + .axi_r_prog_empty(NLW_FIFO_INST_axi_r_prog_empty_UNCONNECTED), + .axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .axi_r_prog_full(NLW_FIFO_INST_axi_r_prog_full_UNCONNECTED), + .axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .axi_r_rd_data_count(NLW_FIFO_INST_axi_r_rd_data_count_UNCONNECTED[12:0]), + .axi_r_sbiterr(NLW_FIFO_INST_axi_r_sbiterr_UNCONNECTED), + .axi_r_underflow(NLW_FIFO_INST_axi_r_underflow_UNCONNECTED), + .axi_r_wr_data_count(NLW_FIFO_INST_axi_r_wr_data_count_UNCONNECTED[12:0]), + .axi_w_data_count(NLW_FIFO_INST_axi_w_data_count_UNCONNECTED[12:0]), + .axi_w_dbiterr(NLW_FIFO_INST_axi_w_dbiterr_UNCONNECTED), + .axi_w_injectdbiterr(1'b0), + .axi_w_injectsbiterr(1'b0), + .axi_w_overflow(NLW_FIFO_INST_axi_w_overflow_UNCONNECTED), + .axi_w_prog_empty(NLW_FIFO_INST_axi_w_prog_empty_UNCONNECTED), + .axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .axi_w_prog_full(NLW_FIFO_INST_axi_w_prog_full_UNCONNECTED), + .axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .axi_w_rd_data_count(NLW_FIFO_INST_axi_w_rd_data_count_UNCONNECTED[12:0]), + .axi_w_sbiterr(NLW_FIFO_INST_axi_w_sbiterr_UNCONNECTED), + .axi_w_underflow(NLW_FIFO_INST_axi_w_underflow_UNCONNECTED), + .axi_w_wr_data_count(NLW_FIFO_INST_axi_w_wr_data_count_UNCONNECTED[12:0]), + .axis_data_count(NLW_FIFO_INST_axis_data_count_UNCONNECTED[12:0]), + .axis_dbiterr(NLW_FIFO_INST_axis_dbiterr_UNCONNECTED), + .axis_injectdbiterr(1'b0), + .axis_injectsbiterr(1'b0), + .axis_overflow(NLW_FIFO_INST_axis_overflow_UNCONNECTED), + .axis_prog_empty(NLW_FIFO_INST_axis_prog_empty_UNCONNECTED), + .axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .axis_prog_full(NLW_FIFO_INST_axis_prog_full_UNCONNECTED), + .axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .axis_rd_data_count(NLW_FIFO_INST_axis_rd_data_count_UNCONNECTED[12:0]), + .axis_sbiterr(NLW_FIFO_INST_axis_sbiterr_UNCONNECTED), + .axis_underflow(NLW_FIFO_INST_axis_underflow_UNCONNECTED), + .axis_wr_data_count(NLW_FIFO_INST_axis_wr_data_count_UNCONNECTED[12:0]), + .backup(1'b0), + .backup_marker(1'b0), + .clk(1'b0), + .data_count(NLW_FIFO_INST_data_count_UNCONNECTED[12:0]), + .dbiterr(NLW_FIFO_INST_dbiterr_UNCONNECTED), + .din(FIFO_WR_DATA), + .dout(dout), + .empty(empty_i), + .full(NLW_FIFO_INST_full_UNCONNECTED), + .injectdbiterr(1'b0), + .injectsbiterr(1'b0), + .int_clk(1'b0), + .m_aclk(1'b0), + .m_aclk_en(1'b0), + .m_axi_araddr(NLW_FIFO_INST_m_axi_araddr_UNCONNECTED[31:0]), + .m_axi_arburst(NLW_FIFO_INST_m_axi_arburst_UNCONNECTED[1:0]), + .m_axi_arcache(NLW_FIFO_INST_m_axi_arcache_UNCONNECTED[3:0]), + .m_axi_arid(NLW_FIFO_INST_m_axi_arid_UNCONNECTED[0]), + .m_axi_arlen(NLW_FIFO_INST_m_axi_arlen_UNCONNECTED[7:0]), + .m_axi_arlock(NLW_FIFO_INST_m_axi_arlock_UNCONNECTED[0]), + .m_axi_arprot(NLW_FIFO_INST_m_axi_arprot_UNCONNECTED[2:0]), + .m_axi_arqos(NLW_FIFO_INST_m_axi_arqos_UNCONNECTED[3:0]), + .m_axi_arready(1'b0), + .m_axi_arregion(NLW_FIFO_INST_m_axi_arregion_UNCONNECTED[3:0]), + .m_axi_arsize(NLW_FIFO_INST_m_axi_arsize_UNCONNECTED[2:0]), + .m_axi_aruser(NLW_FIFO_INST_m_axi_aruser_UNCONNECTED[0]), + .m_axi_arvalid(NLW_FIFO_INST_m_axi_arvalid_UNCONNECTED), + .m_axi_awaddr(NLW_FIFO_INST_m_axi_awaddr_UNCONNECTED[31:0]), + .m_axi_awburst(NLW_FIFO_INST_m_axi_awburst_UNCONNECTED[1:0]), + .m_axi_awcache(NLW_FIFO_INST_m_axi_awcache_UNCONNECTED[3:0]), + .m_axi_awid(NLW_FIFO_INST_m_axi_awid_UNCONNECTED[0]), + .m_axi_awlen(NLW_FIFO_INST_m_axi_awlen_UNCONNECTED[7:0]), + .m_axi_awlock(NLW_FIFO_INST_m_axi_awlock_UNCONNECTED[0]), + .m_axi_awprot(NLW_FIFO_INST_m_axi_awprot_UNCONNECTED[2:0]), + .m_axi_awqos(NLW_FIFO_INST_m_axi_awqos_UNCONNECTED[3:0]), + .m_axi_awready(1'b0), + .m_axi_awregion(NLW_FIFO_INST_m_axi_awregion_UNCONNECTED[3:0]), + .m_axi_awsize(NLW_FIFO_INST_m_axi_awsize_UNCONNECTED[2:0]), + .m_axi_awuser(NLW_FIFO_INST_m_axi_awuser_UNCONNECTED[0]), + .m_axi_awvalid(NLW_FIFO_INST_m_axi_awvalid_UNCONNECTED), + .m_axi_bid(1'b0), + .m_axi_bready(NLW_FIFO_INST_m_axi_bready_UNCONNECTED), + .m_axi_bresp({1'b0,1'b0}), + .m_axi_buser(1'b0), + .m_axi_bvalid(1'b0), + .m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .m_axi_rid(1'b0), + .m_axi_rlast(1'b0), + .m_axi_rready(NLW_FIFO_INST_m_axi_rready_UNCONNECTED), + .m_axi_rresp({1'b0,1'b0}), + .m_axi_ruser(1'b0), + .m_axi_rvalid(1'b0), + .m_axi_wdata(NLW_FIFO_INST_m_axi_wdata_UNCONNECTED[63:0]), + .m_axi_wid(NLW_FIFO_INST_m_axi_wid_UNCONNECTED[0]), + .m_axi_wlast(NLW_FIFO_INST_m_axi_wlast_UNCONNECTED), + .m_axi_wready(1'b0), + .m_axi_wstrb(NLW_FIFO_INST_m_axi_wstrb_UNCONNECTED[7:0]), + .m_axi_wuser(NLW_FIFO_INST_m_axi_wuser_UNCONNECTED[0]), + .m_axi_wvalid(NLW_FIFO_INST_m_axi_wvalid_UNCONNECTED), + .m_axis_tdata(NLW_FIFO_INST_m_axis_tdata_UNCONNECTED[7:0]), + .m_axis_tdest(NLW_FIFO_INST_m_axis_tdest_UNCONNECTED[0]), + .m_axis_tid(NLW_FIFO_INST_m_axis_tid_UNCONNECTED[0]), + .m_axis_tkeep(NLW_FIFO_INST_m_axis_tkeep_UNCONNECTED[0]), + .m_axis_tlast(NLW_FIFO_INST_m_axis_tlast_UNCONNECTED), + .m_axis_tready(1'b0), + .m_axis_tstrb(NLW_FIFO_INST_m_axis_tstrb_UNCONNECTED[0]), + .m_axis_tuser(NLW_FIFO_INST_m_axis_tuser_UNCONNECTED[3:0]), + .m_axis_tvalid(NLW_FIFO_INST_m_axis_tvalid_UNCONNECTED), + .overflow(overflow), + .prog_empty(NLW_FIFO_INST_prog_empty_UNCONNECTED), + .prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_full(NLW_FIFO_INST_prog_full_UNCONNECTED), + .prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .rd_clk(aclk), + .rd_data_count(NLW_FIFO_INST_rd_data_count_UNCONNECTED[12:0]), + .rd_en(rd_en_i__0), + .rd_rst(1'b0), + .rd_rst_busy(NLW_FIFO_INST_rd_rst_busy_UNCONNECTED), + .rst(FIFO_INST_i_1_n_0), + .s_aclk(1'b0), + .s_aclk_en(1'b0), + .s_aresetn(1'b0), + .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_arburst({1'b0,1'b0}), + .s_axi_arcache({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arid(1'b0), + .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_arlock(1'b0), + .s_axi_arprot({1'b0,1'b0,1'b0}), + .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arready(NLW_FIFO_INST_s_axi_arready_UNCONNECTED), + .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arsize({1'b0,1'b0,1'b0}), + .s_axi_aruser(1'b0), + .s_axi_arvalid(1'b0), + .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_awburst({1'b0,1'b0}), + .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awid(1'b0), + .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_awlock(1'b0), + .s_axi_awprot({1'b0,1'b0,1'b0}), + .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awready(NLW_FIFO_INST_s_axi_awready_UNCONNECTED), + .s_axi_awregion({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awsize({1'b0,1'b0,1'b0}), + .s_axi_awuser(1'b0), + .s_axi_awvalid(1'b0), + .s_axi_bid(NLW_FIFO_INST_s_axi_bid_UNCONNECTED[0]), + .s_axi_bready(1'b0), + .s_axi_bresp(NLW_FIFO_INST_s_axi_bresp_UNCONNECTED[1:0]), + .s_axi_buser(NLW_FIFO_INST_s_axi_buser_UNCONNECTED[0]), + .s_axi_bvalid(NLW_FIFO_INST_s_axi_bvalid_UNCONNECTED), + .s_axi_rdata(NLW_FIFO_INST_s_axi_rdata_UNCONNECTED[63:0]), + .s_axi_rid(NLW_FIFO_INST_s_axi_rid_UNCONNECTED[0]), + .s_axi_rlast(NLW_FIFO_INST_s_axi_rlast_UNCONNECTED), + .s_axi_rready(1'b0), + .s_axi_rresp(NLW_FIFO_INST_s_axi_rresp_UNCONNECTED[1:0]), + .s_axi_ruser(NLW_FIFO_INST_s_axi_ruser_UNCONNECTED[0]), + .s_axi_rvalid(NLW_FIFO_INST_s_axi_rvalid_UNCONNECTED), + .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_wid(1'b0), + .s_axi_wlast(1'b0), + .s_axi_wready(NLW_FIFO_INST_s_axi_wready_UNCONNECTED), + .s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axi_wuser(1'b0), + .s_axi_wvalid(1'b0), + .s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .s_axis_tdest(1'b0), + .s_axis_tid(1'b0), + .s_axis_tkeep(1'b0), + .s_axis_tlast(1'b0), + .s_axis_tready(NLW_FIFO_INST_s_axis_tready_UNCONNECTED), + .s_axis_tstrb(1'b0), + .s_axis_tuser({1'b0,1'b0,1'b0,1'b0}), + .s_axis_tvalid(1'b0), + .sbiterr(NLW_FIFO_INST_sbiterr_UNCONNECTED), + .sleep(1'b0), + .srst(1'b0), + .underflow(underflow), + .valid(m_axis_video_tvalid), + .wr_ack(NLW_FIFO_INST_wr_ack_UNCONNECTED), + .wr_clk(vid_io_in_clk), + .wr_data_count(NLW_FIFO_INST_wr_data_count_UNCONNECTED[12:0]), + .wr_en(wr_en_i__0), + .wr_rst(1'b0), + .wr_rst_busy(wr_rst_busy_i)); + LUT2 #( + .INIT(4'hB)) + FIFO_INST_i_1 + (.I0(vid_io_in_reset), + .I1(aresetn), + .O(FIFO_INST_i_1_n_0)); + LUT4 #( + .INIT(16'h2000)) + rd_en_i + (.I0(aclken), + .I1(empty_i), + .I2(m_axis_video_tvalid), + .I3(m_axis_video_tready), + .O(rd_en_i__0)); + LUT5 #( + .INIT(32'h10000000)) + wr_en_i + (.I0(wr_rst_busy_i), + .I1(vid_io_in_reset), + .I2(de_3), + .I3(vtd_locked_reg), + .I4(vid_io_in_ce), + .O(wr_en_i__0)); +endmodule + +module Arty_Z7_20_v_vid_in_axi4s_0_0_v_vid_in_axi4s_v4_0_5_formatter + (vtd_vblank, + vtd_vsync, + vtd_active_video, + vtd_hblank, + vtd_hsync, + vtd_field_id, + FIFO_WR_DATA, + de_3, + vtd_locked_reg_0, + vid_io_in_reset, + vid_io_in_ce, + vid_active_video, + vid_io_in_clk, + vid_vblank, + vid_hblank, + vid_vsync, + vid_hsync, + vid_field_id, + vid_data, + axis_enable); + output vtd_vblank; + output vtd_vsync; + output vtd_active_video; + output vtd_hblank; + output vtd_hsync; + output vtd_field_id; + output [26:0]FIFO_WR_DATA; + output de_3; + output vtd_locked_reg_0; + input vid_io_in_reset; + input vid_io_in_ce; + input vid_active_video; + input vid_io_in_clk; + input vid_vblank; + input vid_hblank; + input vid_vsync; + input vid_hsync; + input vid_field_id; + input [23:0]vid_data; + input axis_enable; + + wire [26:0]FIFO_WR_DATA; + wire axis_enable; + wire [23:0]data_1; + wire [23:0]data_2; + wire de_2; + wire de_3; + wire eol_i_1_n_0; + wire field_id_2; + wire sof; + wire sof0; + wire v_blank_sync_1; + wire v_blank_sync_2; + wire vert_blanking_intvl_i_1_n_0; + wire vert_blanking_intvl_reg_n_0; + wire vid_active_video; + wire [23:0]vid_data; + wire vid_field_id; + wire vid_hblank; + wire vid_hsync; + wire vid_io_in_ce; + wire vid_io_in_clk; + wire vid_io_in_reset; + wire vid_vblank; + wire vid_vsync; + wire vtd_active_video; + wire vtd_field_id; + wire vtd_hblank; + wire vtd_hsync; + wire vtd_locked_i_1_n_0; + wire vtd_locked_reg_0; + wire vtd_vblank; + wire vtd_vsync; + + FDRE #( + .INIT(1'b0)) + \data_1_reg[0] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vid_data[0]), + .Q(data_1[0]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_1_reg[10] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vid_data[10]), + .Q(data_1[10]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_1_reg[11] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vid_data[11]), + .Q(data_1[11]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_1_reg[12] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vid_data[12]), + .Q(data_1[12]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_1_reg[13] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vid_data[13]), + .Q(data_1[13]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_1_reg[14] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vid_data[14]), + .Q(data_1[14]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_1_reg[15] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vid_data[15]), + .Q(data_1[15]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_1_reg[16] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vid_data[16]), + .Q(data_1[16]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_1_reg[17] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vid_data[17]), + .Q(data_1[17]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_1_reg[18] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vid_data[18]), + .Q(data_1[18]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_1_reg[19] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vid_data[19]), + .Q(data_1[19]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_1_reg[1] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vid_data[1]), + .Q(data_1[1]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_1_reg[20] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vid_data[20]), + .Q(data_1[20]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_1_reg[21] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vid_data[21]), + .Q(data_1[21]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_1_reg[22] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vid_data[22]), + .Q(data_1[22]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_1_reg[23] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vid_data[23]), + .Q(data_1[23]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_1_reg[2] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vid_data[2]), + .Q(data_1[2]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_1_reg[3] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vid_data[3]), + .Q(data_1[3]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_1_reg[4] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vid_data[4]), + .Q(data_1[4]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_1_reg[5] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vid_data[5]), + .Q(data_1[5]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_1_reg[6] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vid_data[6]), + .Q(data_1[6]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_1_reg[7] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vid_data[7]), + .Q(data_1[7]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_1_reg[8] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vid_data[8]), + .Q(data_1[8]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_1_reg[9] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vid_data[9]), + .Q(data_1[9]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_2_reg[0] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_1[0]), + .Q(data_2[0]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_2_reg[10] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_1[10]), + .Q(data_2[10]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_2_reg[11] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_1[11]), + .Q(data_2[11]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_2_reg[12] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_1[12]), + .Q(data_2[12]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_2_reg[13] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_1[13]), + .Q(data_2[13]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_2_reg[14] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_1[14]), + .Q(data_2[14]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_2_reg[15] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_1[15]), + .Q(data_2[15]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_2_reg[16] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_1[16]), + .Q(data_2[16]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_2_reg[17] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_1[17]), + .Q(data_2[17]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_2_reg[18] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_1[18]), + .Q(data_2[18]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_2_reg[19] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_1[19]), + .Q(data_2[19]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_2_reg[1] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_1[1]), + .Q(data_2[1]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_2_reg[20] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_1[20]), + .Q(data_2[20]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_2_reg[21] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_1[21]), + .Q(data_2[21]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_2_reg[22] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_1[22]), + .Q(data_2[22]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_2_reg[23] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_1[23]), + .Q(data_2[23]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_2_reg[2] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_1[2]), + .Q(data_2[2]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_2_reg[3] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_1[3]), + .Q(data_2[3]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_2_reg[4] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_1[4]), + .Q(data_2[4]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_2_reg[5] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_1[5]), + .Q(data_2[5]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_2_reg[6] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_1[6]), + .Q(data_2[6]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_2_reg[7] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_1[7]), + .Q(data_2[7]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_2_reg[8] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_1[8]), + .Q(data_2[8]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_2_reg[9] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_1[9]), + .Q(data_2[9]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_3_reg[0] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_2[0]), + .Q(FIFO_WR_DATA[0]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_3_reg[10] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_2[10]), + .Q(FIFO_WR_DATA[10]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_3_reg[11] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_2[11]), + .Q(FIFO_WR_DATA[11]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_3_reg[12] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_2[12]), + .Q(FIFO_WR_DATA[12]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_3_reg[13] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_2[13]), + .Q(FIFO_WR_DATA[13]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_3_reg[14] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_2[14]), + .Q(FIFO_WR_DATA[14]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_3_reg[15] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_2[15]), + .Q(FIFO_WR_DATA[15]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_3_reg[16] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_2[16]), + .Q(FIFO_WR_DATA[16]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_3_reg[17] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_2[17]), + .Q(FIFO_WR_DATA[17]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_3_reg[18] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_2[18]), + .Q(FIFO_WR_DATA[18]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_3_reg[19] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_2[19]), + .Q(FIFO_WR_DATA[19]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_3_reg[1] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_2[1]), + .Q(FIFO_WR_DATA[1]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_3_reg[20] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_2[20]), + .Q(FIFO_WR_DATA[20]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_3_reg[21] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_2[21]), + .Q(FIFO_WR_DATA[21]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_3_reg[22] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_2[22]), + .Q(FIFO_WR_DATA[22]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_3_reg[23] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_2[23]), + .Q(FIFO_WR_DATA[23]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_3_reg[2] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_2[2]), + .Q(FIFO_WR_DATA[2]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_3_reg[3] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_2[3]), + .Q(FIFO_WR_DATA[3]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_3_reg[4] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_2[4]), + .Q(FIFO_WR_DATA[4]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_3_reg[5] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_2[5]), + .Q(FIFO_WR_DATA[5]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_3_reg[6] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_2[6]), + .Q(FIFO_WR_DATA[6]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_3_reg[7] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_2[7]), + .Q(FIFO_WR_DATA[7]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_3_reg[8] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_2[8]), + .Q(FIFO_WR_DATA[8]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + \data_3_reg[9] + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(data_2[9]), + .Q(FIFO_WR_DATA[9]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + de_1_reg + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vid_active_video), + .Q(vtd_active_video), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + de_2_reg + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vtd_active_video), + .Q(de_2), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + de_3_reg + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(de_2), + .Q(de_3), + .R(vid_io_in_reset)); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT2 #( + .INIT(4'h2)) + eol_i_1 + (.I0(de_2), + .I1(vtd_active_video), + .O(eol_i_1_n_0)); + FDRE eol_reg + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(eol_i_1_n_0), + .Q(FIFO_WR_DATA[24]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + field_id_1_reg + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vid_field_id), + .Q(vtd_field_id), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + field_id_2_reg + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vtd_field_id), + .Q(field_id_2), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + field_id_3_reg + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(field_id_2), + .Q(FIFO_WR_DATA[26]), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + hblank_1_reg + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vid_hblank), + .Q(vtd_hblank), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + hsync_1_reg + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vid_hsync), + .Q(vtd_hsync), + .R(vid_io_in_reset)); + FDRE sof_1_reg + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(sof), + .Q(FIFO_WR_DATA[25]), + .R(vid_io_in_reset)); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT3 #( + .INIT(8'h40)) + sof_i_1 + (.I0(de_2), + .I1(vtd_active_video), + .I2(vert_blanking_intvl_reg_n_0), + .O(sof0)); + FDRE sof_reg + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(sof0), + .Q(sof), + .R(vid_io_in_reset)); + LUT2 #( + .INIT(4'hE)) + v_blank_sync_2_i_1 + (.I0(vtd_vblank), + .I1(vtd_vsync), + .O(v_blank_sync_1)); + FDRE #( + .INIT(1'b0)) + v_blank_sync_2_reg + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(v_blank_sync_1), + .Q(v_blank_sync_2), + .R(vid_io_in_reset)); + FDRE #( + .INIT(1'b0)) + vblank_1_reg + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vid_vblank), + .Q(vtd_vblank), + .R(vid_io_in_reset)); + LUT6 #( + .INIT(64'hB0B0F0F0FFB0F0F0)) + vert_blanking_intvl_i_1 + (.I0(de_2), + .I1(vtd_active_video), + .I2(vert_blanking_intvl_reg_n_0), + .I3(v_blank_sync_1), + .I4(vid_io_in_ce), + .I5(v_blank_sync_2), + .O(vert_blanking_intvl_i_1_n_0)); + FDRE #( + .INIT(1'b0)) + vert_blanking_intvl_reg + (.C(vid_io_in_clk), + .CE(1'b1), + .D(vert_blanking_intvl_i_1_n_0), + .Q(vert_blanking_intvl_reg_n_0), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + vsync_1_reg + (.C(vid_io_in_clk), + .CE(vid_io_in_ce), + .D(vid_vsync), + .Q(vtd_vsync), + .R(vid_io_in_reset)); + LUT6 #( + .INIT(64'h00000000BAAA0000)) + vtd_locked_i_1 + (.I0(vtd_locked_reg_0), + .I1(FIFO_WR_DATA[25]), + .I2(vid_io_in_ce), + .I3(sof), + .I4(axis_enable), + .I5(vid_io_in_reset), + .O(vtd_locked_i_1_n_0)); + FDRE vtd_locked_reg + (.C(vid_io_in_clk), + .CE(1'b1), + .D(vtd_locked_i_1_n_0), + .Q(vtd_locked_reg_0), + .R(1'b0)); +endmodule + +module Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_generic_cstr + (dout, + wr_clk, + rd_clk, + ram_full_fb_i_reg, + tmp_ram_rd_en, + tmp_ram_regout_en, + out, + Q, + \gc0.count_d1_reg[11] , + din); + output [26:0]dout; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input tmp_ram_rd_en; + input tmp_ram_regout_en; + input [0:0]out; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [26:0]din; + + wire [11:0]Q; + wire [26:0]din; + wire [26:0]dout; + wire [11:0]\gc0.count_d1_reg[11] ; + wire [0:0]out; + wire ram_full_fb_i_reg; + wire rd_clk; + wire tmp_ram_rd_en; + wire tmp_ram_regout_en; + wire wr_clk; + + Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_width \ramloop[0].ram.r + (.Q(Q), + .din(din[8:0]), + .dout(dout[8:0]), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .out(out), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .tmp_ram_rd_en(tmp_ram_rd_en), + .tmp_ram_regout_en(tmp_ram_regout_en), + .wr_clk(wr_clk)); + Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r + (.Q(Q), + .din(din[17:9]), + .dout(dout[17:9]), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .out(out), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .tmp_ram_rd_en(tmp_ram_rd_en), + .tmp_ram_regout_en(tmp_ram_regout_en), + .wr_clk(wr_clk)); + Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r + (.Q(Q), + .din(din[26:18]), + .dout(dout[26:18]), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .out(out), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .tmp_ram_rd_en(tmp_ram_rd_en), + .tmp_ram_regout_en(tmp_ram_regout_en), + .wr_clk(wr_clk)); +endmodule + +module Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_width + (dout, + wr_clk, + rd_clk, + ram_full_fb_i_reg, + tmp_ram_rd_en, + tmp_ram_regout_en, + out, + Q, + \gc0.count_d1_reg[11] , + din); + output [8:0]dout; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input tmp_ram_rd_en; + input tmp_ram_regout_en; + input [0:0]out; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + + wire [11:0]Q; + wire [8:0]din; + wire [8:0]dout; + wire [11:0]\gc0.count_d1_reg[11] ; + wire [0:0]out; + wire ram_full_fb_i_reg; + wire rd_clk; + wire tmp_ram_rd_en; + wire tmp_ram_regout_en; + wire wr_clk; + + Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_wrapper \prim_noinit.ram + (.Q(Q), + .din(din), + .dout(dout), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .out(out), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .tmp_ram_rd_en(tmp_ram_rd_en), + .tmp_ram_regout_en(tmp_ram_regout_en), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_width__parameterized0 + (dout, + wr_clk, + rd_clk, + ram_full_fb_i_reg, + tmp_ram_rd_en, + tmp_ram_regout_en, + out, + Q, + \gc0.count_d1_reg[11] , + din); + output [8:0]dout; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input tmp_ram_rd_en; + input tmp_ram_regout_en; + input [0:0]out; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + + wire [11:0]Q; + wire [8:0]din; + wire [8:0]dout; + wire [11:0]\gc0.count_d1_reg[11] ; + wire [0:0]out; + wire ram_full_fb_i_reg; + wire rd_clk; + wire tmp_ram_rd_en; + wire tmp_ram_regout_en; + wire wr_clk; + + Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram + (.Q(Q), + .din(din), + .dout(dout), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .out(out), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .tmp_ram_rd_en(tmp_ram_rd_en), + .tmp_ram_regout_en(tmp_ram_regout_en), + .wr_clk(wr_clk)); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) +module Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_width__parameterized1 + (dout, + wr_clk, + rd_clk, + ram_full_fb_i_reg, + tmp_ram_rd_en, + tmp_ram_regout_en, + out, + Q, + \gc0.count_d1_reg[11] , + din); + output [8:0]dout; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input tmp_ram_rd_en; + input tmp_ram_regout_en; + input [0:0]out; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + + wire [11:0]Q; + wire [8:0]din; + wire [8:0]dout; + wire [11:0]\gc0.count_d1_reg[11] ; + wire [0:0]out; + wire ram_full_fb_i_reg; + wire rd_clk; + wire tmp_ram_rd_en; + wire tmp_ram_regout_en; + wire wr_clk; + + Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_wrapper__parameterized1 \prim_noinit.ram + (.Q(Q), + .din(din), + .dout(dout), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .out(out), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .tmp_ram_rd_en(tmp_ram_rd_en), + .tmp_ram_regout_en(tmp_ram_regout_en), + .wr_clk(wr_clk)); +endmodule + +module Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_wrapper + (dout, + wr_clk, + rd_clk, + ram_full_fb_i_reg, + tmp_ram_rd_en, + tmp_ram_regout_en, + out, + Q, + \gc0.count_d1_reg[11] , + din); + output [8:0]dout; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input tmp_ram_rd_en; + input tmp_ram_regout_en; + input [0:0]out; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + + wire [11:0]Q; + wire [8:0]din; + wire [8:0]dout; + wire [11:0]\gc0.count_d1_reg[11] ; + wire [0:0]out; + wire ram_full_fb_i_reg; + wire rd_clk; + wire tmp_ram_rd_en; + wire tmp_ram_regout_en; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(1), + .DOB_REG(1), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ram_full_fb_i_reg), + .ENBWREN(tmp_ram_rd_en), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(tmp_ram_regout_en), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(out), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_wrapper__parameterized0 + (dout, + wr_clk, + rd_clk, + ram_full_fb_i_reg, + tmp_ram_rd_en, + tmp_ram_regout_en, + out, + Q, + \gc0.count_d1_reg[11] , + din); + output [8:0]dout; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input tmp_ram_rd_en; + input tmp_ram_regout_en; + input [0:0]out; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + + wire [11:0]Q; + wire [8:0]din; + wire [8:0]dout; + wire [11:0]\gc0.count_d1_reg[11] ; + wire [0:0]out; + wire ram_full_fb_i_reg; + wire rd_clk; + wire tmp_ram_rd_en; + wire tmp_ram_regout_en; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(1), + .DOB_REG(1), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ram_full_fb_i_reg), + .ENBWREN(tmp_ram_rd_en), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(tmp_ram_regout_en), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(out), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) +module Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_wrapper__parameterized1 + (dout, + wr_clk, + rd_clk, + ram_full_fb_i_reg, + tmp_ram_rd_en, + tmp_ram_regout_en, + out, + Q, + \gc0.count_d1_reg[11] , + din); + output [8:0]dout; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input tmp_ram_rd_en; + input tmp_ram_regout_en; + input [0:0]out; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [8:0]din; + + wire [11:0]Q; + wire [8:0]din; + wire [8:0]dout; + wire [11:0]\gc0.count_d1_reg[11] ; + wire [0:0]out; + wire ram_full_fb_i_reg; + wire rd_clk; + wire tmp_ram_rd_en; + wire tmp_ram_regout_en; + wire wr_clk; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ; + wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ; + wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ; + wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ; + wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ; + wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ; + wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ; + wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ; + + (* CLOCK_DOMAINS = "INDEPENDENT" *) + (* box_type = "PRIMITIVE" *) + RAMB36E1 #( + .DOA_REG(1), + .DOB_REG(1), + .EN_ECC_READ("FALSE"), + .EN_ECC_WRITE("FALSE"), + .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(36'h000000000), + .INIT_B(36'h000000000), + .INIT_FILE("NONE"), + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(1'b0), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_EXTENSION_A("NONE"), + .RAM_EXTENSION_B("NONE"), + .RAM_MODE("TDP"), + .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), + .READ_WIDTH_A(9), + .READ_WIDTH_B(9), + .RSTREG_PRIORITY_A("REGCE"), + .RSTREG_PRIORITY_B("REGCE"), + .SIM_COLLISION_CHECK("ALL"), + .SIM_DEVICE("7SERIES"), + .SRVAL_A(36'h000000000), + .SRVAL_B(36'h000000000), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .WRITE_WIDTH_A(9), + .WRITE_WIDTH_B(9)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram + (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}), + .ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ), + .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ), + .CLKARDCLK(wr_clk), + .CLKBWRCLK(rd_clk), + .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ), + .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}), + .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DIPADIP({1'b0,1'b0,1'b0,din[8]}), + .DIPBDIP({1'b0,1'b0,1'b0,1'b0}), + .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]), + .DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}), + .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]), + .DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}), + .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]), + .ENARDEN(ram_full_fb_i_reg), + .ENBWREN(tmp_ram_rd_en), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]), + .REGCEAREGCE(1'b0), + .REGCEB(tmp_ram_regout_en), + .RSTRAMARSTRAM(1'b0), + .RSTRAMB(1'b0), + .RSTREGARSTREG(1'b0), + .RSTREGB(out), + .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ), + .WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}), + .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0})); +endmodule + +module Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_top + (dout, + wr_clk, + rd_clk, + ram_full_fb_i_reg, + tmp_ram_rd_en, + tmp_ram_regout_en, + out, + Q, + \gc0.count_d1_reg[11] , + din); + output [26:0]dout; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input tmp_ram_rd_en; + input tmp_ram_regout_en; + input [0:0]out; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [26:0]din; + + wire [11:0]Q; + wire [26:0]din; + wire [26:0]dout; + wire [11:0]\gc0.count_d1_reg[11] ; + wire [0:0]out; + wire ram_full_fb_i_reg; + wire rd_clk; + wire tmp_ram_rd_en; + wire tmp_ram_regout_en; + wire wr_clk; + + Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_generic_cstr \valid.cstr + (.Q(Q), + .din(din), + .dout(dout), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .out(out), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .tmp_ram_rd_en(tmp_ram_rd_en), + .tmp_ram_regout_en(tmp_ram_regout_en), + .wr_clk(wr_clk)); +endmodule + +module Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_v8_3_5 + (dout, + wr_clk, + rd_clk, + ram_full_fb_i_reg, + tmp_ram_rd_en, + tmp_ram_regout_en, + out, + Q, + \gc0.count_d1_reg[11] , + din); + output [26:0]dout; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input tmp_ram_rd_en; + input tmp_ram_regout_en; + input [0:0]out; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [26:0]din; + + wire [11:0]Q; + wire [26:0]din; + wire [26:0]dout; + wire [11:0]\gc0.count_d1_reg[11] ; + wire [0:0]out; + wire ram_full_fb_i_reg; + wire rd_clk; + wire tmp_ram_rd_en; + wire tmp_ram_regout_en; + wire wr_clk; + + Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen + (.Q(Q), + .din(din), + .dout(dout), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .out(out), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .tmp_ram_rd_en(tmp_ram_rd_en), + .tmp_ram_regout_en(tmp_ram_regout_en), + .wr_clk(wr_clk)); +endmodule + +module Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_v8_3_5_synth + (dout, + wr_clk, + rd_clk, + ram_full_fb_i_reg, + tmp_ram_rd_en, + tmp_ram_regout_en, + out, + Q, + \gc0.count_d1_reg[11] , + din); + output [26:0]dout; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input tmp_ram_rd_en; + input tmp_ram_regout_en; + input [0:0]out; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [26:0]din; + + wire [11:0]Q; + wire [26:0]din; + wire [26:0]dout; + wire [11:0]\gc0.count_d1_reg[11] ; + wire [0:0]out; + wire ram_full_fb_i_reg; + wire rd_clk; + wire tmp_ram_rd_en; + wire tmp_ram_regout_en; + wire wr_clk; + + Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen + (.Q(Q), + .din(din), + .dout(dout), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .out(out), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .tmp_ram_rd_en(tmp_ram_rd_en), + .tmp_ram_regout_en(tmp_ram_regout_en), + .wr_clk(wr_clk)); +endmodule + +module Arty_Z7_20_v_vid_in_axi4s_0_0_clk_x_pntrs + (WR_PNTR_RD, + RD_PNTR_WR, + bin2gray, + wr_clk, + AR, + rd_clk, + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] , + I4); + output [11:0]WR_PNTR_RD; + output [11:0]RD_PNTR_WR; + input [11:0]bin2gray; + input wr_clk; + input [0:0]AR; + input rd_clk; + input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ; + input [11:0]I4; + + wire [0:0]AR; + wire [11:0]I4; + wire [11:0]RD_PNTR_WR; + wire [11:0]WR_PNTR_RD; + wire [11:0]bin2gray; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_10 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_11 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ; + wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 ; + wire [9:0]gray2bin; + wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ; + wire p_0_out; + wire [11:0]p_3_out; + wire [11:0]p_4_out; + wire [11:11]p_5_out; + wire [11:11]p_6_out; + wire rd_clk; + wire [11:0]rd_pntr_gc; + wire wr_clk; + wire [11:0]wr_pntr_gc; + + Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff__parameterized0 \gnxpm_cdc.gsync_stage[1].rd_stg_inst + (.D(p_3_out), + .Q(wr_pntr_gc), + .\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .rd_clk(rd_clk)); + Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff__parameterized1 \gnxpm_cdc.gsync_stage[1].wr_stg_inst + (.AR(AR), + .D(p_4_out), + .Q(rd_pntr_gc), + .wr_clk(wr_clk)); + Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff__parameterized2 \gnxpm_cdc.gsync_stage[2].rd_stg_inst + (.D(p_3_out), + .\gnxpm_cdc.wr_pntr_bin_reg[10] ({p_0_out,gray2bin}), + .\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .out(p_5_out), + .rd_clk(rd_clk)); + Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff__parameterized3 \gnxpm_cdc.gsync_stage[2].wr_stg_inst + (.AR(AR), + .D(p_4_out), + .\gnxpm_cdc.rd_pntr_bin_reg[10] ({\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_10 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_11 }), + .out(p_6_out), + .wr_clk(wr_clk)); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[0] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_11 ), + .Q(RD_PNTR_WR[0])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[10] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ), + .Q(RD_PNTR_WR[10])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[11] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(p_6_out), + .Q(RD_PNTR_WR[11])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[1] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_10 ), + .Q(RD_PNTR_WR[1])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[2] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 ), + .Q(RD_PNTR_WR[2])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[3] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ), + .Q(RD_PNTR_WR[3])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[4] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ), + .Q(RD_PNTR_WR[4])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[5] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ), + .Q(RD_PNTR_WR[5])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[6] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ), + .Q(RD_PNTR_WR[6])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[7] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ), + .Q(RD_PNTR_WR[7])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[8] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ), + .Q(RD_PNTR_WR[8])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_bin_reg[9] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ), + .Q(RD_PNTR_WR[9])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[0] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(I4[0]), + .Q(rd_pntr_gc[0])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[10] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(I4[10]), + .Q(rd_pntr_gc[10])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[11] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(I4[11]), + .Q(rd_pntr_gc[11])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[1] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(I4[1]), + .Q(rd_pntr_gc[1])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[2] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(I4[2]), + .Q(rd_pntr_gc[2])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[3] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(I4[3]), + .Q(rd_pntr_gc[3])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[4] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(I4[4]), + .Q(rd_pntr_gc[4])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[5] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(I4[5]), + .Q(rd_pntr_gc[5])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[6] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(I4[6]), + .Q(rd_pntr_gc[6])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[7] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(I4[7]), + .Q(rd_pntr_gc[7])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[8] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(I4[8]), + .Q(rd_pntr_gc[8])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.rd_pntr_gc_reg[9] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(I4[9]), + .Q(rd_pntr_gc[9])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[0] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(gray2bin[0]), + .Q(WR_PNTR_RD[0])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[10] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(p_0_out), + .Q(WR_PNTR_RD[10])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[11] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(p_5_out), + .Q(WR_PNTR_RD[11])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[1] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(gray2bin[1]), + .Q(WR_PNTR_RD[1])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[2] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(gray2bin[2]), + .Q(WR_PNTR_RD[2])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[3] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(gray2bin[3]), + .Q(WR_PNTR_RD[3])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[4] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(gray2bin[4]), + .Q(WR_PNTR_RD[4])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[5] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(gray2bin[5]), + .Q(WR_PNTR_RD[5])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[6] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(gray2bin[6]), + .Q(WR_PNTR_RD[6])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[7] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(gray2bin[7]), + .Q(WR_PNTR_RD[7])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[8] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(gray2bin[8]), + .Q(WR_PNTR_RD[8])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_bin_reg[9] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(gray2bin[9]), + .Q(WR_PNTR_RD[9])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[0] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(bin2gray[0]), + .Q(wr_pntr_gc[0])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[10] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(bin2gray[10]), + .Q(wr_pntr_gc[10])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[11] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(bin2gray[11]), + .Q(wr_pntr_gc[11])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[1] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(bin2gray[1]), + .Q(wr_pntr_gc[1])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[2] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(bin2gray[2]), + .Q(wr_pntr_gc[2])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[3] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(bin2gray[3]), + .Q(wr_pntr_gc[3])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[4] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(bin2gray[4]), + .Q(wr_pntr_gc[4])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[5] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(bin2gray[5]), + .Q(wr_pntr_gc[5])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[6] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(bin2gray[6]), + .Q(wr_pntr_gc[6])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[7] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(bin2gray[7]), + .Q(wr_pntr_gc[7])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[8] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(bin2gray[8]), + .Q(wr_pntr_gc[8])); + FDCE #( + .INIT(1'b0)) + \gnxpm_cdc.wr_pntr_gc_reg[9] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(bin2gray[9]), + .Q(wr_pntr_gc[9])); +endmodule + +module Arty_Z7_20_v_vid_in_axi4s_0_0_compare + (comp1, + Q, + RD_PNTR_WR); + output comp1; + input [11:0]Q; + input [11:0]RD_PNTR_WR; + + wire [11:0]Q; + wire [11:0]RD_PNTR_WR; + wire carrynet_0; + wire carrynet_1; + wire carrynet_2; + wire carrynet_3; + wire carrynet_4; + wire comp1; + wire [5:0]v1_reg; + wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; + wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; + wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; + wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ; + wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; + + (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) + (* box_type = "PRIMITIVE" *) + CARRY4 \gmux.gm[0].gm1.m1_CARRY4 + (.CI(1'b0), + .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}), + .CYINIT(1'b1), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), + .S(v1_reg[3:0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[0].gm1.m1_i_1 + (.I0(Q[0]), + .I1(RD_PNTR_WR[0]), + .I2(Q[1]), + .I3(RD_PNTR_WR[1]), + .O(v1_reg[0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[1].gms.ms_i_1 + (.I0(Q[2]), + .I1(RD_PNTR_WR[2]), + .I2(Q[3]), + .I3(RD_PNTR_WR[3]), + .O(v1_reg[1])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[2].gms.ms_i_1 + (.I0(Q[4]), + .I1(RD_PNTR_WR[4]), + .I2(Q[5]), + .I3(RD_PNTR_WR[5]), + .O(v1_reg[2])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[3].gms.ms_i_1 + (.I0(Q[6]), + .I1(RD_PNTR_WR[6]), + .I2(Q[7]), + .I3(RD_PNTR_WR[7]), + .O(v1_reg[3])); + (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) + (* box_type = "PRIMITIVE" *) + CARRY4 \gmux.gm[4].gms.ms_CARRY4 + (.CI(carrynet_3), + .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp1,carrynet_4}), + .CYINIT(1'b0), + .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}), + .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), + .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],v1_reg[5:4]})); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[4].gms.ms_i_1 + (.I0(Q[8]), + .I1(RD_PNTR_WR[8]), + .I2(Q[9]), + .I3(RD_PNTR_WR[9]), + .O(v1_reg[4])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[5].gms.ms_i_1 + (.I0(Q[10]), + .I1(RD_PNTR_WR[10]), + .I2(Q[11]), + .I3(RD_PNTR_WR[11]), + .O(v1_reg[5])); +endmodule + +(* ORIG_REF_NAME = "compare" *) +module Arty_Z7_20_v_vid_in_axi4s_0_0_compare_3 + (comp2, + D, + RD_PNTR_WR); + output comp2; + input [11:0]D; + input [11:0]RD_PNTR_WR; + + wire [11:0]D; + wire [11:0]RD_PNTR_WR; + wire carrynet_0; + wire carrynet_1; + wire carrynet_2; + wire carrynet_3; + wire carrynet_4; + wire comp2; + wire [5:0]v1_reg; + wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; + wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; + wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; + wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ; + wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; + + (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) + (* box_type = "PRIMITIVE" *) + CARRY4 \gmux.gm[0].gm1.m1_CARRY4 + (.CI(1'b0), + .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}), + .CYINIT(1'b1), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), + .S(v1_reg[3:0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[0].gm1.m1_i_1 + (.I0(D[0]), + .I1(RD_PNTR_WR[0]), + .I2(D[1]), + .I3(RD_PNTR_WR[1]), + .O(v1_reg[0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[1].gms.ms_i_1 + (.I0(D[2]), + .I1(RD_PNTR_WR[2]), + .I2(D[3]), + .I3(RD_PNTR_WR[3]), + .O(v1_reg[1])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[2].gms.ms_i_1 + (.I0(D[4]), + .I1(RD_PNTR_WR[4]), + .I2(D[5]), + .I3(RD_PNTR_WR[5]), + .O(v1_reg[2])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[3].gms.ms_i_1 + (.I0(D[6]), + .I1(RD_PNTR_WR[6]), + .I2(D[7]), + .I3(RD_PNTR_WR[7]), + .O(v1_reg[3])); + (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) + (* box_type = "PRIMITIVE" *) + CARRY4 \gmux.gm[4].gms.ms_CARRY4 + (.CI(carrynet_3), + .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp2,carrynet_4}), + .CYINIT(1'b0), + .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}), + .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), + .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],v1_reg[5:4]})); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[4].gms.ms_i_1 + (.I0(D[8]), + .I1(RD_PNTR_WR[8]), + .I2(D[9]), + .I3(RD_PNTR_WR[9]), + .O(v1_reg[4])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[5].gms.ms_i_1 + (.I0(D[10]), + .I1(RD_PNTR_WR[10]), + .I2(D[11]), + .I3(RD_PNTR_WR[11]), + .O(v1_reg[5])); +endmodule + +(* ORIG_REF_NAME = "compare" *) +module Arty_Z7_20_v_vid_in_axi4s_0_0_compare_4 + (comp0, + WR_PNTR_RD, + Q); + output comp0; + input [11:0]WR_PNTR_RD; + input [11:0]Q; + + wire [11:0]Q; + wire [11:0]WR_PNTR_RD; + wire carrynet_0; + wire carrynet_1; + wire carrynet_2; + wire carrynet_3; + wire carrynet_4; + wire comp0; + wire [5:0]v1_reg; + wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; + wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; + wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; + wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ; + wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; + + (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) + (* box_type = "PRIMITIVE" *) + CARRY4 \gmux.gm[0].gm1.m1_CARRY4 + (.CI(1'b0), + .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}), + .CYINIT(1'b1), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), + .S(v1_reg[3:0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[0].gm1.m1_i_1 + (.I0(WR_PNTR_RD[0]), + .I1(Q[0]), + .I2(WR_PNTR_RD[1]), + .I3(Q[1]), + .O(v1_reg[0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[1].gms.ms_i_1 + (.I0(WR_PNTR_RD[2]), + .I1(Q[2]), + .I2(WR_PNTR_RD[3]), + .I3(Q[3]), + .O(v1_reg[1])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[2].gms.ms_i_1 + (.I0(WR_PNTR_RD[4]), + .I1(Q[4]), + .I2(WR_PNTR_RD[5]), + .I3(Q[5]), + .O(v1_reg[2])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[3].gms.ms_i_1 + (.I0(WR_PNTR_RD[6]), + .I1(Q[6]), + .I2(WR_PNTR_RD[7]), + .I3(Q[7]), + .O(v1_reg[3])); + (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) + (* box_type = "PRIMITIVE" *) + CARRY4 \gmux.gm[4].gms.ms_CARRY4 + (.CI(carrynet_3), + .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp0,carrynet_4}), + .CYINIT(1'b0), + .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}), + .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), + .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],v1_reg[5:4]})); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[4].gms.ms_i_1 + (.I0(WR_PNTR_RD[8]), + .I1(Q[8]), + .I2(WR_PNTR_RD[9]), + .I3(Q[9]), + .O(v1_reg[4])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[5].gms.ms_i_1 + (.I0(WR_PNTR_RD[10]), + .I1(Q[10]), + .I2(WR_PNTR_RD[11]), + .I3(Q[11]), + .O(v1_reg[5])); +endmodule + +(* ORIG_REF_NAME = "compare" *) +module Arty_Z7_20_v_vid_in_axi4s_0_0_compare_5 + (comp1, + WR_PNTR_RD, + D); + output comp1; + input [11:0]WR_PNTR_RD; + input [11:0]D; + + wire [11:0]D; + wire [11:0]WR_PNTR_RD; + wire carrynet_0; + wire carrynet_1; + wire carrynet_2; + wire carrynet_3; + wire carrynet_4; + wire comp1; + wire [5:0]v1_reg; + wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ; + wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ; + wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ; + wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ; + wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ; + + (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) + (* box_type = "PRIMITIVE" *) + CARRY4 \gmux.gm[0].gm1.m1_CARRY4 + (.CI(1'b0), + .CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}), + .CYINIT(1'b1), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]), + .S(v1_reg[3:0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[0].gm1.m1_i_1 + (.I0(WR_PNTR_RD[0]), + .I1(D[0]), + .I2(WR_PNTR_RD[1]), + .I3(D[1]), + .O(v1_reg[0])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[1].gms.ms_i_1 + (.I0(WR_PNTR_RD[2]), + .I1(D[2]), + .I2(WR_PNTR_RD[3]), + .I3(D[3]), + .O(v1_reg[1])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[2].gms.ms_i_1 + (.I0(WR_PNTR_RD[4]), + .I1(D[4]), + .I2(WR_PNTR_RD[5]), + .I3(D[5]), + .O(v1_reg[2])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[3].gms.ms_i_1 + (.I0(WR_PNTR_RD[6]), + .I1(D[6]), + .I2(WR_PNTR_RD[7]), + .I3(D[7]), + .O(v1_reg[3])); + (* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *) + (* box_type = "PRIMITIVE" *) + CARRY4 \gmux.gm[4].gms.ms_CARRY4 + (.CI(carrynet_3), + .CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp1,carrynet_4}), + .CYINIT(1'b0), + .DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}), + .O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]), + .S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],v1_reg[5:4]})); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[4].gms.ms_i_1 + (.I0(WR_PNTR_RD[8]), + .I1(D[8]), + .I2(WR_PNTR_RD[9]), + .I3(D[9]), + .O(v1_reg[4])); + LUT4 #( + .INIT(16'h9009)) + \gmux.gm[5].gms.ms_i_1 + (.I0(WR_PNTR_RD[10]), + .I1(D[10]), + .I2(WR_PNTR_RD[11]), + .I3(D[11]), + .O(v1_reg[5])); +endmodule + +module Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_ramfifo + (wr_rst_busy, + dout, + empty, + valid, + underflow, + overflow, + wr_en, + wr_clk, + rd_clk, + din, + rst, + rd_en); + output wr_rst_busy; + output [26:0]dout; + output empty; + output valid; + output underflow; + output overflow; + input wr_en; + input wr_clk; + input rd_clk; + input [26:0]din; + input rst; + input rd_en; + + wire [10:0]bin2gray; + wire [26:0]din; + wire [26:0]dout; + wire empty; + wire \gntv_or_sync_fifo.gl0.rd_n_15 ; + wire \gntv_or_sync_fifo.gl0.rd_n_16 ; + wire \gntv_or_sync_fifo.gl0.rd_n_17 ; + wire \gntv_or_sync_fifo.gl0.rd_n_18 ; + wire \gntv_or_sync_fifo.gl0.rd_n_19 ; + wire \gntv_or_sync_fifo.gl0.rd_n_20 ; + wire \gntv_or_sync_fifo.gl0.rd_n_21 ; + wire \gntv_or_sync_fifo.gl0.rd_n_22 ; + wire \gntv_or_sync_fifo.gl0.rd_n_23 ; + wire \gntv_or_sync_fifo.gl0.rd_n_24 ; + wire \gntv_or_sync_fifo.gl0.rd_n_25 ; + wire \gntv_or_sync_fifo.gl0.wr_n_1 ; + wire overflow; + wire [11:0]p_0_out; + wire [11:0]p_12_out; + wire [11:0]p_22_out; + wire [11:0]p_23_out; + wire rd_clk; + wire rd_en; + wire [2:0]rd_rst_i; + wire rst; + wire rst_full_ff_i; + wire tmp_ram_rd_en; + wire tmp_ram_regout_en; + wire underflow; + wire valid; + wire wr_clk; + wire wr_en; + wire wr_rst_busy; + wire [1:0]wr_rst_i; + + Arty_Z7_20_v_vid_in_axi4s_0_0_clk_x_pntrs \gntv_or_sync_fifo.gcx.clkx + (.AR(wr_rst_i[0]), + .I4({p_0_out[11],\gntv_or_sync_fifo.gl0.rd_n_15 ,\gntv_or_sync_fifo.gl0.rd_n_16 ,\gntv_or_sync_fifo.gl0.rd_n_17 ,\gntv_or_sync_fifo.gl0.rd_n_18 ,\gntv_or_sync_fifo.gl0.rd_n_19 ,\gntv_or_sync_fifo.gl0.rd_n_20 ,\gntv_or_sync_fifo.gl0.rd_n_21 ,\gntv_or_sync_fifo.gl0.rd_n_22 ,\gntv_or_sync_fifo.gl0.rd_n_23 ,\gntv_or_sync_fifo.gl0.rd_n_24 ,\gntv_or_sync_fifo.gl0.rd_n_25 }), + .RD_PNTR_WR(p_23_out), + .WR_PNTR_RD(p_22_out), + .bin2gray({p_12_out[11],bin2gray}), + .\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]), + .rd_clk(rd_clk), + .wr_clk(wr_clk)); + Arty_Z7_20_v_vid_in_axi4s_0_0_rd_logic \gntv_or_sync_fifo.gl0.rd + (.I4({\gntv_or_sync_fifo.gl0.rd_n_15 ,\gntv_or_sync_fifo.gl0.rd_n_16 ,\gntv_or_sync_fifo.gl0.rd_n_17 ,\gntv_or_sync_fifo.gl0.rd_n_18 ,\gntv_or_sync_fifo.gl0.rd_n_19 ,\gntv_or_sync_fifo.gl0.rd_n_20 ,\gntv_or_sync_fifo.gl0.rd_n_21 ,\gntv_or_sync_fifo.gl0.rd_n_22 ,\gntv_or_sync_fifo.gl0.rd_n_23 ,\gntv_or_sync_fifo.gl0.rd_n_24 ,\gntv_or_sync_fifo.gl0.rd_n_25 }), + .Q(p_0_out), + .WR_PNTR_RD(p_22_out), + .empty(empty), + .out({rd_rst_i[2],rd_rst_i[0]}), + .rd_clk(rd_clk), + .rd_en(rd_en), + .tmp_ram_rd_en(tmp_ram_rd_en), + .tmp_ram_regout_en(tmp_ram_regout_en), + .underflow(underflow), + .valid(valid)); + Arty_Z7_20_v_vid_in_axi4s_0_0_wr_logic \gntv_or_sync_fifo.gl0.wr + (.Q(p_12_out), + .RD_PNTR_WR(p_23_out), + .bin2gray(bin2gray), + .\gic0.gc0.count_d1_reg[11] (\gntv_or_sync_fifo.gl0.wr_n_1 ), + .\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] (wr_rst_i[1]), + .out(rst_full_ff_i), + .overflow(overflow), + .wr_clk(wr_clk), + .wr_en(wr_en), + .wr_rst_busy(wr_rst_busy)); + Arty_Z7_20_v_vid_in_axi4s_0_0_memory \gntv_or_sync_fifo.mem + (.Q(p_12_out), + .din(din), + .dout(dout), + .\gc0.count_d1_reg[11] (p_0_out), + .out(rd_rst_i[0]), + .ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_1 ), + .rd_clk(rd_clk), + .tmp_ram_rd_en(tmp_ram_rd_en), + .tmp_ram_regout_en(tmp_ram_regout_en), + .wr_clk(wr_clk)); + Arty_Z7_20_v_vid_in_axi4s_0_0_reset_blk_ramfifo rstblk + (.\gc0.count_reg[0] (rd_rst_i), + .\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i), + .out(wr_rst_i), + .rd_clk(rd_clk), + .rst(rst), + .wr_clk(wr_clk), + .wr_rst_busy(wr_rst_busy)); +endmodule + +module Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_top + (wr_rst_busy, + dout, + empty, + valid, + underflow, + overflow, + wr_en, + wr_clk, + rd_clk, + din, + rst, + rd_en); + output wr_rst_busy; + output [26:0]dout; + output empty; + output valid; + output underflow; + output overflow; + input wr_en; + input wr_clk; + input rd_clk; + input [26:0]din; + input rst; + input rd_en; + + wire [26:0]din; + wire [26:0]dout; + wire empty; + wire overflow; + wire rd_clk; + wire rd_en; + wire rst; + wire underflow; + wire valid; + wire wr_clk; + wire wr_en; + wire wr_rst_busy; + + Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_ramfifo \grf.rf + (.din(din), + .dout(dout), + .empty(empty), + .overflow(overflow), + .rd_clk(rd_clk), + .rd_en(rd_en), + .rst(rst), + .underflow(underflow), + .valid(valid), + .wr_clk(wr_clk), + .wr_en(wr_en), + .wr_rst_busy(wr_rst_busy)); +endmodule + +(* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *) +(* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *) +(* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *) +(* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *) +(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *) +(* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *) +(* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *) +(* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *) +(* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *) +(* C_DATA_COUNT_WIDTH = "13" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "27" *) +(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *) +(* C_DIN_WIDTH_WACH = "32" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *) +(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "27" *) (* C_ENABLE_RLOCS = "0" *) +(* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *) +(* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) +(* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) +(* C_FAMILY = "zynq" *) (* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *) +(* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *) +(* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *) +(* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *) +(* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *) +(* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *) +(* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *) +(* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *) +(* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *) +(* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *) +(* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "1" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *) +(* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *) +(* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "1" *) +(* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *) (* C_HAS_SLAVE_CE = "0" *) +(* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "1" *) (* C_HAS_VALID = "1" *) +(* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "1" *) (* C_HAS_WR_RST = "0" *) +(* C_IMPLEMENTATION_TYPE = "2" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *) +(* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) +(* C_IMPLEMENTATION_TYPE_WRCH = "1" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *) +(* C_MEMORY_TYPE = "1" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *) +(* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *) +(* C_PRELOAD_LATENCY = "0" *) (* C_PRELOAD_REGS = "1" *) (* C_PRIM_FIFO_TYPE = "1kx36" *) +(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *) +(* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) +(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "4" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) +(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) +(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "5" *) (* C_PROG_EMPTY_TYPE = "0" *) +(* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *) +(* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *) +(* C_PROG_FULL_THRESH_ASSERT_VAL = "4095" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) +(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) +(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "4094" *) (* C_PROG_FULL_TYPE = "0" *) +(* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *) +(* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *) +(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "13" *) +(* C_RD_DEPTH = "4096" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "12" *) +(* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *) +(* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *) +(* C_SELECT_XPM = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_UNDERFLOW_LOW = "0" *) +(* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *) +(* C_USE_DOUT_RST = "1" *) (* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *) +(* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *) +(* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "1" *) +(* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "1" *) (* C_USE_PIPELINE_REG = "0" *) +(* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *) +(* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "13" *) +(* C_WR_DEPTH = "4096" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *) +(* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *) +(* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "12" *) +(* C_WR_PNTR_WIDTH_AXIS = "12" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "12" *) +(* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "12" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *) +(* C_WR_RESPONSE_LATENCY = "1" *) +module Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 + (backup, + backup_marker, + clk, + rst, + srst, + wr_clk, + wr_rst, + rd_clk, + rd_rst, + din, + wr_en, + rd_en, + prog_empty_thresh, + prog_empty_thresh_assert, + prog_empty_thresh_negate, + prog_full_thresh, + prog_full_thresh_assert, + prog_full_thresh_negate, + int_clk, + injectdbiterr, + injectsbiterr, + sleep, + dout, + full, + almost_full, + wr_ack, + overflow, + empty, + almost_empty, + valid, + underflow, + data_count, + rd_data_count, + wr_data_count, + prog_full, + prog_empty, + sbiterr, + dbiterr, + wr_rst_busy, + rd_rst_busy, + m_aclk, + s_aclk, + s_aresetn, + m_aclk_en, + s_aclk_en, + s_axi_awid, + s_axi_awaddr, + s_axi_awlen, + s_axi_awsize, + s_axi_awburst, + s_axi_awlock, + s_axi_awcache, + s_axi_awprot, + s_axi_awqos, + s_axi_awregion, + s_axi_awuser, + s_axi_awvalid, + s_axi_awready, + s_axi_wid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wlast, + s_axi_wuser, + s_axi_wvalid, + s_axi_wready, + s_axi_bid, + s_axi_bresp, + s_axi_buser, + s_axi_bvalid, + s_axi_bready, + m_axi_awid, + m_axi_awaddr, + m_axi_awlen, + m_axi_awsize, + m_axi_awburst, + m_axi_awlock, + m_axi_awcache, + m_axi_awprot, + m_axi_awqos, + m_axi_awregion, + m_axi_awuser, + m_axi_awvalid, + m_axi_awready, + m_axi_wid, + m_axi_wdata, + m_axi_wstrb, + m_axi_wlast, + m_axi_wuser, + m_axi_wvalid, + m_axi_wready, + m_axi_bid, + m_axi_bresp, + m_axi_buser, + m_axi_bvalid, + m_axi_bready, + s_axi_arid, + s_axi_araddr, + s_axi_arlen, + s_axi_arsize, + s_axi_arburst, + s_axi_arlock, + s_axi_arcache, + s_axi_arprot, + s_axi_arqos, + s_axi_arregion, + s_axi_aruser, + s_axi_arvalid, + s_axi_arready, + s_axi_rid, + s_axi_rdata, + s_axi_rresp, + s_axi_rlast, + s_axi_ruser, + s_axi_rvalid, + s_axi_rready, + m_axi_arid, + m_axi_araddr, + m_axi_arlen, + m_axi_arsize, + m_axi_arburst, + m_axi_arlock, + m_axi_arcache, + m_axi_arprot, + m_axi_arqos, + m_axi_arregion, + m_axi_aruser, + m_axi_arvalid, + m_axi_arready, + m_axi_rid, + m_axi_rdata, + m_axi_rresp, + m_axi_rlast, + m_axi_ruser, + m_axi_rvalid, + m_axi_rready, + s_axis_tvalid, + s_axis_tready, + s_axis_tdata, + s_axis_tstrb, + s_axis_tkeep, + s_axis_tlast, + s_axis_tid, + s_axis_tdest, + s_axis_tuser, + m_axis_tvalid, + m_axis_tready, + m_axis_tdata, + m_axis_tstrb, + m_axis_tkeep, + m_axis_tlast, + m_axis_tid, + m_axis_tdest, + m_axis_tuser, + axi_aw_injectsbiterr, + axi_aw_injectdbiterr, + axi_aw_prog_full_thresh, + axi_aw_prog_empty_thresh, + axi_aw_data_count, + axi_aw_wr_data_count, + axi_aw_rd_data_count, + axi_aw_sbiterr, + axi_aw_dbiterr, + axi_aw_overflow, + axi_aw_underflow, + axi_aw_prog_full, + axi_aw_prog_empty, + axi_w_injectsbiterr, + axi_w_injectdbiterr, + axi_w_prog_full_thresh, + axi_w_prog_empty_thresh, + axi_w_data_count, + axi_w_wr_data_count, + axi_w_rd_data_count, + axi_w_sbiterr, + axi_w_dbiterr, + axi_w_overflow, + axi_w_underflow, + axi_w_prog_full, + axi_w_prog_empty, + axi_b_injectsbiterr, + axi_b_injectdbiterr, + axi_b_prog_full_thresh, + axi_b_prog_empty_thresh, + axi_b_data_count, + axi_b_wr_data_count, + axi_b_rd_data_count, + axi_b_sbiterr, + axi_b_dbiterr, + axi_b_overflow, + axi_b_underflow, + axi_b_prog_full, + axi_b_prog_empty, + axi_ar_injectsbiterr, + axi_ar_injectdbiterr, + axi_ar_prog_full_thresh, + axi_ar_prog_empty_thresh, + axi_ar_data_count, + axi_ar_wr_data_count, + axi_ar_rd_data_count, + axi_ar_sbiterr, + axi_ar_dbiterr, + axi_ar_overflow, + axi_ar_underflow, + axi_ar_prog_full, + axi_ar_prog_empty, + axi_r_injectsbiterr, + axi_r_injectdbiterr, + axi_r_prog_full_thresh, + axi_r_prog_empty_thresh, + axi_r_data_count, + axi_r_wr_data_count, + axi_r_rd_data_count, + axi_r_sbiterr, + axi_r_dbiterr, + axi_r_overflow, + axi_r_underflow, + axi_r_prog_full, + axi_r_prog_empty, + axis_injectsbiterr, + axis_injectdbiterr, + axis_prog_full_thresh, + axis_prog_empty_thresh, + axis_data_count, + axis_wr_data_count, + axis_rd_data_count, + axis_sbiterr, + axis_dbiterr, + axis_overflow, + axis_underflow, + axis_prog_full, + axis_prog_empty); + input backup; + input backup_marker; + input clk; + input rst; + input srst; + input wr_clk; + input wr_rst; + input rd_clk; + input rd_rst; + input [26:0]din; + input wr_en; + input rd_en; + input [11:0]prog_empty_thresh; + input [11:0]prog_empty_thresh_assert; + input [11:0]prog_empty_thresh_negate; + input [11:0]prog_full_thresh; + input [11:0]prog_full_thresh_assert; + input [11:0]prog_full_thresh_negate; + input int_clk; + input injectdbiterr; + input injectsbiterr; + input sleep; + output [26:0]dout; + output full; + output almost_full; + output wr_ack; + output overflow; + output empty; + output almost_empty; + output valid; + output underflow; + output [12:0]data_count; + output [12:0]rd_data_count; + output [12:0]wr_data_count; + output prog_full; + output prog_empty; + output sbiterr; + output dbiterr; + output wr_rst_busy; + output rd_rst_busy; + input m_aclk; + input s_aclk; + input s_aresetn; + input m_aclk_en; + input s_aclk_en; + input [0:0]s_axi_awid; + input [31:0]s_axi_awaddr; + input [7:0]s_axi_awlen; + input [2:0]s_axi_awsize; + input [1:0]s_axi_awburst; + input [0:0]s_axi_awlock; + input [3:0]s_axi_awcache; + input [2:0]s_axi_awprot; + input [3:0]s_axi_awqos; + input [3:0]s_axi_awregion; + input [0:0]s_axi_awuser; + input s_axi_awvalid; + output s_axi_awready; + input [0:0]s_axi_wid; + input [63:0]s_axi_wdata; + input [7:0]s_axi_wstrb; + input s_axi_wlast; + input [0:0]s_axi_wuser; + input s_axi_wvalid; + output s_axi_wready; + output [0:0]s_axi_bid; + output [1:0]s_axi_bresp; + output [0:0]s_axi_buser; + output s_axi_bvalid; + input s_axi_bready; + output [0:0]m_axi_awid; + output [31:0]m_axi_awaddr; + output [7:0]m_axi_awlen; + output [2:0]m_axi_awsize; + output [1:0]m_axi_awburst; + output [0:0]m_axi_awlock; + output [3:0]m_axi_awcache; + output [2:0]m_axi_awprot; + output [3:0]m_axi_awqos; + output [3:0]m_axi_awregion; + output [0:0]m_axi_awuser; + output m_axi_awvalid; + input m_axi_awready; + output [0:0]m_axi_wid; + output [63:0]m_axi_wdata; + output [7:0]m_axi_wstrb; + output m_axi_wlast; + output [0:0]m_axi_wuser; + output m_axi_wvalid; + input m_axi_wready; + input [0:0]m_axi_bid; + input [1:0]m_axi_bresp; + input [0:0]m_axi_buser; + input m_axi_bvalid; + output m_axi_bready; + input [0:0]s_axi_arid; + input [31:0]s_axi_araddr; + input [7:0]s_axi_arlen; + input [2:0]s_axi_arsize; + input [1:0]s_axi_arburst; + input [0:0]s_axi_arlock; + input [3:0]s_axi_arcache; + input [2:0]s_axi_arprot; + input [3:0]s_axi_arqos; + input [3:0]s_axi_arregion; + input [0:0]s_axi_aruser; + input s_axi_arvalid; + output s_axi_arready; + output [0:0]s_axi_rid; + output [63:0]s_axi_rdata; + output [1:0]s_axi_rresp; + output s_axi_rlast; + output [0:0]s_axi_ruser; + output s_axi_rvalid; + input s_axi_rready; + output [0:0]m_axi_arid; + output [31:0]m_axi_araddr; + output [7:0]m_axi_arlen; + output [2:0]m_axi_arsize; + output [1:0]m_axi_arburst; + output [0:0]m_axi_arlock; + output [3:0]m_axi_arcache; + output [2:0]m_axi_arprot; + output [3:0]m_axi_arqos; + output [3:0]m_axi_arregion; + output [0:0]m_axi_aruser; + output m_axi_arvalid; + input m_axi_arready; + input [0:0]m_axi_rid; + input [63:0]m_axi_rdata; + input [1:0]m_axi_rresp; + input m_axi_rlast; + input [0:0]m_axi_ruser; + input m_axi_rvalid; + output m_axi_rready; + input s_axis_tvalid; + output s_axis_tready; + input [7:0]s_axis_tdata; + input [0:0]s_axis_tstrb; + input [0:0]s_axis_tkeep; + input s_axis_tlast; + input [0:0]s_axis_tid; + input [0:0]s_axis_tdest; + input [3:0]s_axis_tuser; + output m_axis_tvalid; + input m_axis_tready; + output [7:0]m_axis_tdata; + output [0:0]m_axis_tstrb; + output [0:0]m_axis_tkeep; + output m_axis_tlast; + output [0:0]m_axis_tid; + output [0:0]m_axis_tdest; + output [3:0]m_axis_tuser; + input axi_aw_injectsbiterr; + input axi_aw_injectdbiterr; + input [3:0]axi_aw_prog_full_thresh; + input [3:0]axi_aw_prog_empty_thresh; + output [4:0]axi_aw_data_count; + output [4:0]axi_aw_wr_data_count; + output [4:0]axi_aw_rd_data_count; + output axi_aw_sbiterr; + output axi_aw_dbiterr; + output axi_aw_overflow; + output axi_aw_underflow; + output axi_aw_prog_full; + output axi_aw_prog_empty; + input axi_w_injectsbiterr; + input axi_w_injectdbiterr; + input [11:0]axi_w_prog_full_thresh; + input [11:0]axi_w_prog_empty_thresh; + output [12:0]axi_w_data_count; + output [12:0]axi_w_wr_data_count; + output [12:0]axi_w_rd_data_count; + output axi_w_sbiterr; + output axi_w_dbiterr; + output axi_w_overflow; + output axi_w_underflow; + output axi_w_prog_full; + output axi_w_prog_empty; + input axi_b_injectsbiterr; + input axi_b_injectdbiterr; + input [3:0]axi_b_prog_full_thresh; + input [3:0]axi_b_prog_empty_thresh; + output [4:0]axi_b_data_count; + output [4:0]axi_b_wr_data_count; + output [4:0]axi_b_rd_data_count; + output axi_b_sbiterr; + output axi_b_dbiterr; + output axi_b_overflow; + output axi_b_underflow; + output axi_b_prog_full; + output axi_b_prog_empty; + input axi_ar_injectsbiterr; + input axi_ar_injectdbiterr; + input [3:0]axi_ar_prog_full_thresh; + input [3:0]axi_ar_prog_empty_thresh; + output [4:0]axi_ar_data_count; + output [4:0]axi_ar_wr_data_count; + output [4:0]axi_ar_rd_data_count; + output axi_ar_sbiterr; + output axi_ar_dbiterr; + output axi_ar_overflow; + output axi_ar_underflow; + output axi_ar_prog_full; + output axi_ar_prog_empty; + input axi_r_injectsbiterr; + input axi_r_injectdbiterr; + input [11:0]axi_r_prog_full_thresh; + input [11:0]axi_r_prog_empty_thresh; + output [12:0]axi_r_data_count; + output [12:0]axi_r_wr_data_count; + output [12:0]axi_r_rd_data_count; + output axi_r_sbiterr; + output axi_r_dbiterr; + output axi_r_overflow; + output axi_r_underflow; + output axi_r_prog_full; + output axi_r_prog_empty; + input axis_injectsbiterr; + input axis_injectdbiterr; + input [11:0]axis_prog_full_thresh; + input [11:0]axis_prog_empty_thresh; + output [12:0]axis_data_count; + output [12:0]axis_wr_data_count; + output [12:0]axis_rd_data_count; + output axis_sbiterr; + output axis_dbiterr; + output axis_overflow; + output axis_underflow; + output axis_prog_full; + output axis_prog_empty; + + wire \ ; + wire [26:0]din; + wire [26:0]dout; + wire empty; + wire overflow; + wire rd_clk; + wire rd_en; + wire rst; + wire underflow; + wire valid; + wire wr_clk; + wire wr_en; + wire wr_rst_busy; + + assign almost_empty = \ ; + assign almost_full = \ ; + assign axi_ar_data_count[4] = \ ; + assign axi_ar_data_count[3] = \ ; + assign axi_ar_data_count[2] = \ ; + assign axi_ar_data_count[1] = \ ; + assign axi_ar_data_count[0] = \ ; + assign axi_ar_dbiterr = \ ; + assign axi_ar_overflow = \ ; + assign axi_ar_prog_empty = \ ; + assign axi_ar_prog_full = \ ; + assign axi_ar_rd_data_count[4] = \ ; + assign axi_ar_rd_data_count[3] = \ ; + assign axi_ar_rd_data_count[2] = \ ; + assign axi_ar_rd_data_count[1] = \ ; + assign axi_ar_rd_data_count[0] = \ ; + assign axi_ar_sbiterr = \ ; + assign axi_ar_underflow = \ ; + assign axi_ar_wr_data_count[4] = \ ; + assign axi_ar_wr_data_count[3] = \ ; + assign axi_ar_wr_data_count[2] = \ ; + assign axi_ar_wr_data_count[1] = \ ; + assign axi_ar_wr_data_count[0] = \ ; + assign axi_aw_data_count[4] = \ ; + assign axi_aw_data_count[3] = \ ; + assign axi_aw_data_count[2] = \ ; + assign axi_aw_data_count[1] = \ ; + assign axi_aw_data_count[0] = \ ; + assign axi_aw_dbiterr = \ ; + assign axi_aw_overflow = \ ; + assign axi_aw_prog_empty = \ ; + assign axi_aw_prog_full = \ ; + assign axi_aw_rd_data_count[4] = \ ; + assign axi_aw_rd_data_count[3] = \ ; + assign axi_aw_rd_data_count[2] = \ ; + assign axi_aw_rd_data_count[1] = \ ; + assign axi_aw_rd_data_count[0] = \ ; + assign axi_aw_sbiterr = \ ; + assign axi_aw_underflow = \ ; + assign axi_aw_wr_data_count[4] = \ ; + assign axi_aw_wr_data_count[3] = \ ; + assign axi_aw_wr_data_count[2] = \ ; + assign axi_aw_wr_data_count[1] = \ ; + assign axi_aw_wr_data_count[0] = \ ; + assign axi_b_data_count[4] = \ ; + assign axi_b_data_count[3] = \ ; + assign axi_b_data_count[2] = \ ; + assign axi_b_data_count[1] = \ ; + assign axi_b_data_count[0] = \ ; + assign axi_b_dbiterr = \ ; + assign axi_b_overflow = \ ; + assign axi_b_prog_empty = \ ; + assign axi_b_prog_full = \ ; + assign axi_b_rd_data_count[4] = \ ; + assign axi_b_rd_data_count[3] = \ ; + assign axi_b_rd_data_count[2] = \ ; + assign axi_b_rd_data_count[1] = \ ; + assign axi_b_rd_data_count[0] = \ ; + assign axi_b_sbiterr = \ ; + assign axi_b_underflow = \ ; + assign axi_b_wr_data_count[4] = \ ; + assign axi_b_wr_data_count[3] = \ ; + assign axi_b_wr_data_count[2] = \ ; + assign axi_b_wr_data_count[1] = \ ; + assign axi_b_wr_data_count[0] = \ ; + assign axi_r_data_count[12] = \ ; + assign axi_r_data_count[11] = \ ; + assign axi_r_data_count[10] = \ ; + assign axi_r_data_count[9] = \ ; + assign axi_r_data_count[8] = \ ; + assign axi_r_data_count[7] = \ ; + assign axi_r_data_count[6] = \ ; + assign axi_r_data_count[5] = \ ; + assign axi_r_data_count[4] = \ ; + assign axi_r_data_count[3] = \ ; + assign axi_r_data_count[2] = \ ; + assign axi_r_data_count[1] = \ ; + assign axi_r_data_count[0] = \ ; + assign axi_r_dbiterr = \ ; + assign axi_r_overflow = \ ; + assign axi_r_prog_empty = \ ; + assign axi_r_prog_full = \ ; + assign axi_r_rd_data_count[12] = \ ; + assign axi_r_rd_data_count[11] = \ ; + assign axi_r_rd_data_count[10] = \ ; + assign axi_r_rd_data_count[9] = \ ; + assign axi_r_rd_data_count[8] = \ ; + assign axi_r_rd_data_count[7] = \ ; + assign axi_r_rd_data_count[6] = \ ; + assign axi_r_rd_data_count[5] = \ ; + assign axi_r_rd_data_count[4] = \ ; + assign axi_r_rd_data_count[3] = \ ; + assign axi_r_rd_data_count[2] = \ ; + assign axi_r_rd_data_count[1] = \ ; + assign axi_r_rd_data_count[0] = \ ; + assign axi_r_sbiterr = \ ; + assign axi_r_underflow = \ ; + assign axi_r_wr_data_count[12] = \ ; + assign axi_r_wr_data_count[11] = \ ; + assign axi_r_wr_data_count[10] = \ ; + assign axi_r_wr_data_count[9] = \ ; + assign axi_r_wr_data_count[8] = \ ; + assign axi_r_wr_data_count[7] = \ ; + assign axi_r_wr_data_count[6] = \ ; + assign axi_r_wr_data_count[5] = \ ; + assign axi_r_wr_data_count[4] = \ ; + assign axi_r_wr_data_count[3] = \ ; + assign axi_r_wr_data_count[2] = \ ; + assign axi_r_wr_data_count[1] = \ ; + assign axi_r_wr_data_count[0] = \ ; + assign axi_w_data_count[12] = \ ; + assign axi_w_data_count[11] = \ ; + assign axi_w_data_count[10] = \ ; + assign axi_w_data_count[9] = \ ; + assign axi_w_data_count[8] = \ ; + assign axi_w_data_count[7] = \ ; + assign axi_w_data_count[6] = \ ; + assign axi_w_data_count[5] = \ ; + assign axi_w_data_count[4] = \ ; + assign axi_w_data_count[3] = \ ; + assign axi_w_data_count[2] = \ ; + assign axi_w_data_count[1] = \ ; + assign axi_w_data_count[0] = \ ; + assign axi_w_dbiterr = \ ; + assign axi_w_overflow = \ ; + assign axi_w_prog_empty = \ ; + assign axi_w_prog_full = \ ; + assign axi_w_rd_data_count[12] = \ ; + assign axi_w_rd_data_count[11] = \ ; + assign axi_w_rd_data_count[10] = \ ; + assign axi_w_rd_data_count[9] = \ ; + assign axi_w_rd_data_count[8] = \ ; + assign axi_w_rd_data_count[7] = \ ; + assign axi_w_rd_data_count[6] = \ ; + assign axi_w_rd_data_count[5] = \ ; + assign axi_w_rd_data_count[4] = \ ; + assign axi_w_rd_data_count[3] = \ ; + assign axi_w_rd_data_count[2] = \ ; + assign axi_w_rd_data_count[1] = \ ; + assign axi_w_rd_data_count[0] = \ ; + assign axi_w_sbiterr = \ ; + assign axi_w_underflow = \ ; + assign axi_w_wr_data_count[12] = \ ; + assign axi_w_wr_data_count[11] = \ ; + assign axi_w_wr_data_count[10] = \ ; + assign axi_w_wr_data_count[9] = \ ; + assign axi_w_wr_data_count[8] = \ ; + assign axi_w_wr_data_count[7] = \ ; + assign axi_w_wr_data_count[6] = \ ; + assign axi_w_wr_data_count[5] = \ ; + assign axi_w_wr_data_count[4] = \ ; + assign axi_w_wr_data_count[3] = \ ; + assign axi_w_wr_data_count[2] = \ ; + assign axi_w_wr_data_count[1] = \ ; + assign axi_w_wr_data_count[0] = \ ; + assign axis_data_count[12] = \ ; + assign axis_data_count[11] = \ ; + assign axis_data_count[10] = \ ; + assign axis_data_count[9] = \ ; + assign axis_data_count[8] = \ ; + assign axis_data_count[7] = \ ; + assign axis_data_count[6] = \ ; + assign axis_data_count[5] = \ ; + assign axis_data_count[4] = \ ; + assign axis_data_count[3] = \ ; + assign axis_data_count[2] = \ ; + assign axis_data_count[1] = \ ; + assign axis_data_count[0] = \ ; + assign axis_dbiterr = \ ; + assign axis_overflow = \ ; + assign axis_prog_empty = \ ; + assign axis_prog_full = \ ; + assign axis_rd_data_count[12] = \ ; + assign axis_rd_data_count[11] = \ ; + assign axis_rd_data_count[10] = \ ; + assign axis_rd_data_count[9] = \ ; + assign axis_rd_data_count[8] = \ ; + assign axis_rd_data_count[7] = \ ; + assign axis_rd_data_count[6] = \ ; + assign axis_rd_data_count[5] = \ ; + assign axis_rd_data_count[4] = \ ; + assign axis_rd_data_count[3] = \ ; + assign axis_rd_data_count[2] = \ ; + assign axis_rd_data_count[1] = \ ; + assign axis_rd_data_count[0] = \ ; + assign axis_sbiterr = \ ; + assign axis_underflow = \ ; + assign axis_wr_data_count[12] = \ ; + assign axis_wr_data_count[11] = \ ; + assign axis_wr_data_count[10] = \ ; + assign axis_wr_data_count[9] = \ ; + assign axis_wr_data_count[8] = \ ; + assign axis_wr_data_count[7] = \ ; + assign axis_wr_data_count[6] = \ ; + assign axis_wr_data_count[5] = \ ; + assign axis_wr_data_count[4] = \ ; + assign axis_wr_data_count[3] = \ ; + assign axis_wr_data_count[2] = \ ; + assign axis_wr_data_count[1] = \ ; + assign axis_wr_data_count[0] = \ ; + assign data_count[12] = \ ; + assign data_count[11] = \ ; + assign data_count[10] = \ ; + assign data_count[9] = \ ; + assign data_count[8] = \ ; + assign data_count[7] = \ ; + assign data_count[6] = \ ; + assign data_count[5] = \ ; + assign data_count[4] = \ ; + assign data_count[3] = \ ; + assign data_count[2] = \ ; + assign data_count[1] = \ ; + assign data_count[0] = \ ; + assign dbiterr = \ ; + assign full = \ ; + assign m_axi_araddr[31] = \ ; + assign m_axi_araddr[30] = \ ; + assign m_axi_araddr[29] = \ ; + assign m_axi_araddr[28] = \ ; + assign m_axi_araddr[27] = \ ; + assign m_axi_araddr[26] = \ ; + assign m_axi_araddr[25] = \ ; + assign m_axi_araddr[24] = \ ; + assign m_axi_araddr[23] = \ ; + assign m_axi_araddr[22] = \ ; + assign m_axi_araddr[21] = \ ; + assign m_axi_araddr[20] = \ ; + assign m_axi_araddr[19] = \ ; + assign m_axi_araddr[18] = \ ; + assign m_axi_araddr[17] = \ ; + assign m_axi_araddr[16] = \ ; + assign m_axi_araddr[15] = \ ; + assign m_axi_araddr[14] = \ ; + assign m_axi_araddr[13] = \ ; + assign m_axi_araddr[12] = \ ; + assign m_axi_araddr[11] = \ ; + assign m_axi_araddr[10] = \ ; + assign m_axi_araddr[9] = \ ; + assign m_axi_araddr[8] = \ ; + assign m_axi_araddr[7] = \ ; + assign m_axi_araddr[6] = \ ; + assign m_axi_araddr[5] = \ ; + assign m_axi_araddr[4] = \ ; + assign m_axi_araddr[3] = \ ; + assign m_axi_araddr[2] = \ ; + assign m_axi_araddr[1] = \ ; + assign m_axi_araddr[0] = \ ; + assign m_axi_arburst[1] = \ ; + assign m_axi_arburst[0] = \ ; + assign m_axi_arcache[3] = \ ; + assign m_axi_arcache[2] = \ ; + assign m_axi_arcache[1] = \ ; + assign m_axi_arcache[0] = \ ; + assign m_axi_arid[0] = \ ; + assign m_axi_arlen[7] = \ ; + assign m_axi_arlen[6] = \ ; + assign m_axi_arlen[5] = \ ; + assign m_axi_arlen[4] = \ ; + assign m_axi_arlen[3] = \ ; + assign m_axi_arlen[2] = \ ; + assign m_axi_arlen[1] = \ ; + assign m_axi_arlen[0] = \ ; + assign m_axi_arlock[0] = \ ; + assign m_axi_arprot[2] = \ ; + assign m_axi_arprot[1] = \ ; + assign m_axi_arprot[0] = \ ; + assign m_axi_arqos[3] = \ ; + assign m_axi_arqos[2] = \ ; + assign m_axi_arqos[1] = \ ; + assign m_axi_arqos[0] = \ ; + assign m_axi_arregion[3] = \ ; + assign m_axi_arregion[2] = \ ; + assign m_axi_arregion[1] = \ ; + assign m_axi_arregion[0] = \ ; + assign m_axi_arsize[2] = \ ; + assign m_axi_arsize[1] = \ ; + assign m_axi_arsize[0] = \ ; + assign m_axi_aruser[0] = \ ; + assign m_axi_arvalid = \ ; + assign m_axi_awaddr[31] = \ ; + assign m_axi_awaddr[30] = \ ; + assign m_axi_awaddr[29] = \ ; + assign m_axi_awaddr[28] = \ ; + assign m_axi_awaddr[27] = \ ; + assign m_axi_awaddr[26] = \ ; + assign m_axi_awaddr[25] = \ ; + assign m_axi_awaddr[24] = \ ; + assign m_axi_awaddr[23] = \ ; + assign m_axi_awaddr[22] = \ ; + assign m_axi_awaddr[21] = \ ; + assign m_axi_awaddr[20] = \ ; + assign m_axi_awaddr[19] = \ ; + assign m_axi_awaddr[18] = \ ; + assign m_axi_awaddr[17] = \ ; + assign m_axi_awaddr[16] = \ ; + assign m_axi_awaddr[15] = \ ; + assign m_axi_awaddr[14] = \ ; + assign m_axi_awaddr[13] = \ ; + assign m_axi_awaddr[12] = \ ; + assign m_axi_awaddr[11] = \ ; + assign m_axi_awaddr[10] = \ ; + assign m_axi_awaddr[9] = \ ; + assign m_axi_awaddr[8] = \ ; + assign m_axi_awaddr[7] = \ ; + assign m_axi_awaddr[6] = \ ; + assign m_axi_awaddr[5] = \ ; + assign m_axi_awaddr[4] = \ ; + assign m_axi_awaddr[3] = \ ; + assign m_axi_awaddr[2] = \ ; + assign m_axi_awaddr[1] = \ ; + assign m_axi_awaddr[0] = \ ; + assign m_axi_awburst[1] = \ ; + assign m_axi_awburst[0] = \ ; + assign m_axi_awcache[3] = \ ; + assign m_axi_awcache[2] = \ ; + assign m_axi_awcache[1] = \ ; + assign m_axi_awcache[0] = \ ; + assign m_axi_awid[0] = \ ; + assign m_axi_awlen[7] = \ ; + assign m_axi_awlen[6] = \ ; + assign m_axi_awlen[5] = \ ; + assign m_axi_awlen[4] = \ ; + assign m_axi_awlen[3] = \ ; + assign m_axi_awlen[2] = \ ; + assign m_axi_awlen[1] = \ ; + assign m_axi_awlen[0] = \ ; + assign m_axi_awlock[0] = \ ; + assign m_axi_awprot[2] = \ ; + assign m_axi_awprot[1] = \ ; + assign m_axi_awprot[0] = \ ; + assign m_axi_awqos[3] = \ ; + assign m_axi_awqos[2] = \ ; + assign m_axi_awqos[1] = \ ; + assign m_axi_awqos[0] = \ ; + assign m_axi_awregion[3] = \ ; + assign m_axi_awregion[2] = \ ; + assign m_axi_awregion[1] = \ ; + assign m_axi_awregion[0] = \ ; + assign m_axi_awsize[2] = \ ; + assign m_axi_awsize[1] = \ ; + assign m_axi_awsize[0] = \ ; + assign m_axi_awuser[0] = \ ; + assign m_axi_awvalid = \ ; + assign m_axi_bready = \ ; + assign m_axi_rready = \ ; + assign m_axi_wdata[63] = \ ; + assign m_axi_wdata[62] = \ ; + assign m_axi_wdata[61] = \ ; + assign m_axi_wdata[60] = \ ; + assign m_axi_wdata[59] = \ ; + assign m_axi_wdata[58] = \ ; + assign m_axi_wdata[57] = \ ; + assign m_axi_wdata[56] = \ ; + assign m_axi_wdata[55] = \ ; + assign m_axi_wdata[54] = \ ; + assign m_axi_wdata[53] = \ ; + assign m_axi_wdata[52] = \ ; + assign m_axi_wdata[51] = \ ; + assign m_axi_wdata[50] = \ ; + assign m_axi_wdata[49] = \ ; + assign m_axi_wdata[48] = \ ; + assign m_axi_wdata[47] = \ ; + assign m_axi_wdata[46] = \ ; + assign m_axi_wdata[45] = \ ; + assign m_axi_wdata[44] = \ ; + assign m_axi_wdata[43] = \ ; + assign m_axi_wdata[42] = \ ; + assign m_axi_wdata[41] = \ ; + assign m_axi_wdata[40] = \ ; + assign m_axi_wdata[39] = \ ; + assign m_axi_wdata[38] = \ ; + assign m_axi_wdata[37] = \ ; + assign m_axi_wdata[36] = \ ; + assign m_axi_wdata[35] = \ ; + assign m_axi_wdata[34] = \ ; + assign m_axi_wdata[33] = \ ; + assign m_axi_wdata[32] = \ ; + assign m_axi_wdata[31] = \ ; + assign m_axi_wdata[30] = \ ; + assign m_axi_wdata[29] = \ ; + assign m_axi_wdata[28] = \ ; + assign m_axi_wdata[27] = \ ; + assign m_axi_wdata[26] = \ ; + assign m_axi_wdata[25] = \ ; + assign m_axi_wdata[24] = \ ; + assign m_axi_wdata[23] = \ ; + assign m_axi_wdata[22] = \ ; + assign m_axi_wdata[21] = \ ; + assign m_axi_wdata[20] = \ ; + assign m_axi_wdata[19] = \ ; + assign m_axi_wdata[18] = \ ; + assign m_axi_wdata[17] = \ ; + assign m_axi_wdata[16] = \ ; + assign m_axi_wdata[15] = \ ; + assign m_axi_wdata[14] = \ ; + assign m_axi_wdata[13] = \ ; + assign m_axi_wdata[12] = \ ; + assign m_axi_wdata[11] = \ ; + assign m_axi_wdata[10] = \ ; + assign m_axi_wdata[9] = \ ; + assign m_axi_wdata[8] = \ ; + assign m_axi_wdata[7] = \ ; + assign m_axi_wdata[6] = \ ; + assign m_axi_wdata[5] = \ ; + assign m_axi_wdata[4] = \ ; + assign m_axi_wdata[3] = \ ; + assign m_axi_wdata[2] = \ ; + assign m_axi_wdata[1] = \ ; + assign m_axi_wdata[0] = \ ; + assign m_axi_wid[0] = \ ; + assign m_axi_wlast = \ ; + assign m_axi_wstrb[7] = \ ; + assign m_axi_wstrb[6] = \ ; + assign m_axi_wstrb[5] = \ ; + assign m_axi_wstrb[4] = \ ; + assign m_axi_wstrb[3] = \ ; + assign m_axi_wstrb[2] = \ ; + assign m_axi_wstrb[1] = \ ; + assign m_axi_wstrb[0] = \ ; + assign m_axi_wuser[0] = \ ; + assign m_axi_wvalid = \ ; + assign m_axis_tdata[7] = \ ; + assign m_axis_tdata[6] = \ ; + assign m_axis_tdata[5] = \ ; + assign m_axis_tdata[4] = \ ; + assign m_axis_tdata[3] = \ ; + assign m_axis_tdata[2] = \ ; + assign m_axis_tdata[1] = \ ; + assign m_axis_tdata[0] = \ ; + assign m_axis_tdest[0] = \ ; + assign m_axis_tid[0] = \ ; + assign m_axis_tkeep[0] = \ ; + assign m_axis_tlast = \ ; + assign m_axis_tstrb[0] = \ ; + assign m_axis_tuser[3] = \ ; + assign m_axis_tuser[2] = \ ; + assign m_axis_tuser[1] = \ ; + assign m_axis_tuser[0] = \ ; + assign m_axis_tvalid = \ ; + assign prog_empty = \ ; + assign prog_full = \ ; + assign rd_data_count[12] = \ ; + assign rd_data_count[11] = \ ; + assign rd_data_count[10] = \ ; + assign rd_data_count[9] = \ ; + assign rd_data_count[8] = \ ; + assign rd_data_count[7] = \ ; + assign rd_data_count[6] = \ ; + assign rd_data_count[5] = \ ; + assign rd_data_count[4] = \ ; + assign rd_data_count[3] = \ ; + assign rd_data_count[2] = \ ; + assign rd_data_count[1] = \ ; + assign rd_data_count[0] = \ ; + assign rd_rst_busy = \ ; + assign s_axi_arready = \ ; + assign s_axi_awready = \ ; + assign s_axi_bid[0] = \ ; + assign s_axi_bresp[1] = \ ; + assign s_axi_bresp[0] = \ ; + assign s_axi_buser[0] = \ ; + assign s_axi_bvalid = \ ; + assign s_axi_rdata[63] = \ ; + assign s_axi_rdata[62] = \ ; + assign s_axi_rdata[61] = \ ; + assign s_axi_rdata[60] = \ ; + assign s_axi_rdata[59] = \ ; + assign s_axi_rdata[58] = \ ; + assign s_axi_rdata[57] = \ ; + assign s_axi_rdata[56] = \ ; + assign s_axi_rdata[55] = \ ; + assign s_axi_rdata[54] = \ ; + assign s_axi_rdata[53] = \ ; + assign s_axi_rdata[52] = \ ; + assign s_axi_rdata[51] = \ ; + assign s_axi_rdata[50] = \ ; + assign s_axi_rdata[49] = \ ; + assign s_axi_rdata[48] = \ ; + assign s_axi_rdata[47] = \ ; + assign s_axi_rdata[46] = \ ; + assign s_axi_rdata[45] = \ ; + assign s_axi_rdata[44] = \ ; + assign s_axi_rdata[43] = \ ; + assign s_axi_rdata[42] = \ ; + assign s_axi_rdata[41] = \ ; + assign s_axi_rdata[40] = \ ; + assign s_axi_rdata[39] = \ ; + assign s_axi_rdata[38] = \ ; + assign s_axi_rdata[37] = \ ; + assign s_axi_rdata[36] = \ ; + assign s_axi_rdata[35] = \ ; + assign s_axi_rdata[34] = \ ; + assign s_axi_rdata[33] = \ ; + assign s_axi_rdata[32] = \ ; + assign s_axi_rdata[31] = \ ; + assign s_axi_rdata[30] = \ ; + assign s_axi_rdata[29] = \ ; + assign s_axi_rdata[28] = \ ; + assign s_axi_rdata[27] = \ ; + assign s_axi_rdata[26] = \ ; + assign s_axi_rdata[25] = \ ; + assign s_axi_rdata[24] = \ ; + assign s_axi_rdata[23] = \ ; + assign s_axi_rdata[22] = \ ; + assign s_axi_rdata[21] = \ ; + assign s_axi_rdata[20] = \ ; + assign s_axi_rdata[19] = \ ; + assign s_axi_rdata[18] = \ ; + assign s_axi_rdata[17] = \ ; + assign s_axi_rdata[16] = \ ; + assign s_axi_rdata[15] = \ ; + assign s_axi_rdata[14] = \ ; + assign s_axi_rdata[13] = \ ; + assign s_axi_rdata[12] = \ ; + assign s_axi_rdata[11] = \ ; + assign s_axi_rdata[10] = \ ; + assign s_axi_rdata[9] = \ ; + assign s_axi_rdata[8] = \ ; + assign s_axi_rdata[7] = \ ; + assign s_axi_rdata[6] = \ ; + assign s_axi_rdata[5] = \ ; + assign s_axi_rdata[4] = \ ; + assign s_axi_rdata[3] = \ ; + assign s_axi_rdata[2] = \ ; + assign s_axi_rdata[1] = \ ; + assign s_axi_rdata[0] = \ ; + assign s_axi_rid[0] = \ ; + assign s_axi_rlast = \ ; + assign s_axi_rresp[1] = \ ; + assign s_axi_rresp[0] = \ ; + assign s_axi_ruser[0] = \ ; + assign s_axi_rvalid = \ ; + assign s_axi_wready = \ ; + assign s_axis_tready = \ ; + assign sbiterr = \ ; + assign wr_ack = \ ; + assign wr_data_count[12] = \ ; + assign wr_data_count[11] = \ ; + assign wr_data_count[10] = \ ; + assign wr_data_count[9] = \ ; + assign wr_data_count[8] = \ ; + assign wr_data_count[7] = \ ; + assign wr_data_count[6] = \ ; + assign wr_data_count[5] = \ ; + assign wr_data_count[4] = \ ; + assign wr_data_count[3] = \ ; + assign wr_data_count[2] = \ ; + assign wr_data_count[1] = \ ; + assign wr_data_count[0] = \ ; + GND GND + (.G(\ )); + Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3_synth inst_fifo_gen + (.din(din), + .dout(dout), + .empty(empty), + .overflow(overflow), + .rd_clk(rd_clk), + .rd_en(rd_en), + .rst(rst), + .underflow(underflow), + .valid(valid), + .wr_clk(wr_clk), + .wr_en(wr_en), + .wr_rst_busy(wr_rst_busy)); +endmodule + +module Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3_synth + (wr_rst_busy, + dout, + empty, + valid, + underflow, + overflow, + wr_en, + wr_clk, + rd_clk, + din, + rst, + rd_en); + output wr_rst_busy; + output [26:0]dout; + output empty; + output valid; + output underflow; + output overflow; + input wr_en; + input wr_clk; + input rd_clk; + input [26:0]din; + input rst; + input rd_en; + + wire [26:0]din; + wire [26:0]dout; + wire empty; + wire overflow; + wire rd_clk; + wire rd_en; + wire rst; + wire underflow; + wire valid; + wire wr_clk; + wire wr_en; + wire wr_rst_busy; + + Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_top \gconvfifo.rf + (.din(din), + .dout(dout), + .empty(empty), + .overflow(overflow), + .rd_clk(rd_clk), + .rd_en(rd_en), + .rst(rst), + .underflow(underflow), + .valid(valid), + .wr_clk(wr_clk), + .wr_en(wr_en), + .wr_rst_busy(wr_rst_busy)); +endmodule + +module Arty_Z7_20_v_vid_in_axi4s_0_0_memory + (dout, + wr_clk, + rd_clk, + ram_full_fb_i_reg, + tmp_ram_rd_en, + tmp_ram_regout_en, + out, + Q, + \gc0.count_d1_reg[11] , + din); + output [26:0]dout; + input wr_clk; + input rd_clk; + input ram_full_fb_i_reg; + input tmp_ram_rd_en; + input tmp_ram_regout_en; + input [0:0]out; + input [11:0]Q; + input [11:0]\gc0.count_d1_reg[11] ; + input [26:0]din; + + wire [11:0]Q; + wire [26:0]din; + wire [26:0]dout; + wire [11:0]\gc0.count_d1_reg[11] ; + wire [0:0]out; + wire ram_full_fb_i_reg; + wire rd_clk; + wire tmp_ram_rd_en; + wire tmp_ram_regout_en; + wire wr_clk; + + Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_v8_3_5 \gbm.gbmg.gbmgb.ngecc.bmg + (.Q(Q), + .din(din), + .dout(dout), + .\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ), + .out(out), + .ram_full_fb_i_reg(ram_full_fb_i_reg), + .rd_clk(rd_clk), + .tmp_ram_rd_en(tmp_ram_rd_en), + .tmp_ram_regout_en(tmp_ram_regout_en), + .wr_clk(wr_clk)); +endmodule + +module Arty_Z7_20_v_vid_in_axi4s_0_0_rd_bin_cntr + (D, + Q, + I4, + p_7_out, + rd_clk, + out); + output [11:0]D; + output [11:0]Q; + output [10:0]I4; + input p_7_out; + input rd_clk; + input [0:0]out; + + wire [11:0]D; + wire [10:0]I4; + wire [11:0]Q; + wire \gc0.count[0]_i_2_n_0 ; + wire \gc0.count[0]_i_3_n_0 ; + wire \gc0.count[0]_i_4_n_0 ; + wire \gc0.count[0]_i_5_n_0 ; + wire \gc0.count[4]_i_2_n_0 ; + wire \gc0.count[4]_i_3_n_0 ; + wire \gc0.count[4]_i_4_n_0 ; + wire \gc0.count[4]_i_5_n_0 ; + wire \gc0.count[8]_i_2_n_0 ; + wire \gc0.count[8]_i_3_n_0 ; + wire \gc0.count[8]_i_4_n_0 ; + wire \gc0.count[8]_i_5_n_0 ; + wire \gc0.count_reg[0]_i_1_n_0 ; + wire \gc0.count_reg[0]_i_1_n_1 ; + wire \gc0.count_reg[0]_i_1_n_2 ; + wire \gc0.count_reg[0]_i_1_n_3 ; + wire \gc0.count_reg[0]_i_1_n_4 ; + wire \gc0.count_reg[0]_i_1_n_5 ; + wire \gc0.count_reg[0]_i_1_n_6 ; + wire \gc0.count_reg[0]_i_1_n_7 ; + wire \gc0.count_reg[4]_i_1_n_0 ; + wire \gc0.count_reg[4]_i_1_n_1 ; + wire \gc0.count_reg[4]_i_1_n_2 ; + wire \gc0.count_reg[4]_i_1_n_3 ; + wire \gc0.count_reg[4]_i_1_n_4 ; + wire \gc0.count_reg[4]_i_1_n_5 ; + wire \gc0.count_reg[4]_i_1_n_6 ; + wire \gc0.count_reg[4]_i_1_n_7 ; + wire \gc0.count_reg[8]_i_1_n_1 ; + wire \gc0.count_reg[8]_i_1_n_2 ; + wire \gc0.count_reg[8]_i_1_n_3 ; + wire \gc0.count_reg[8]_i_1_n_4 ; + wire \gc0.count_reg[8]_i_1_n_5 ; + wire \gc0.count_reg[8]_i_1_n_6 ; + wire \gc0.count_reg[8]_i_1_n_7 ; + wire [0:0]out; + wire p_7_out; + wire rd_clk; + wire [3:3]\NLW_gc0.count_reg[8]_i_1_CO_UNCONNECTED ; + + LUT1 #( + .INIT(2'h2)) + \gc0.count[0]_i_2 + (.I0(D[3]), + .O(\gc0.count[0]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[0]_i_3 + (.I0(D[2]), + .O(\gc0.count[0]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[0]_i_4 + (.I0(D[1]), + .O(\gc0.count[0]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \gc0.count[0]_i_5 + (.I0(D[0]), + .O(\gc0.count[0]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[4]_i_2 + (.I0(D[7]), + .O(\gc0.count[4]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[4]_i_3 + (.I0(D[6]), + .O(\gc0.count[4]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[4]_i_4 + (.I0(D[5]), + .O(\gc0.count[4]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[4]_i_5 + (.I0(D[4]), + .O(\gc0.count[4]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[8]_i_2 + (.I0(D[11]), + .O(\gc0.count[8]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[8]_i_3 + (.I0(D[10]), + .O(\gc0.count[8]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[8]_i_4 + (.I0(D[9]), + .O(\gc0.count[8]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gc0.count[8]_i_5 + (.I0(D[8]), + .O(\gc0.count[8]_i_5_n_0 )); + FDCE #( + .INIT(1'b0)) + \gc0.count_d1_reg[0] + (.C(rd_clk), + .CE(p_7_out), + .CLR(out), + .D(D[0]), + .Q(Q[0])); + FDCE #( + .INIT(1'b0)) + \gc0.count_d1_reg[10] + (.C(rd_clk), + .CE(p_7_out), + .CLR(out), + .D(D[10]), + .Q(Q[10])); + FDCE #( + .INIT(1'b0)) + \gc0.count_d1_reg[11] + (.C(rd_clk), + .CE(p_7_out), + .CLR(out), + .D(D[11]), + .Q(Q[11])); + FDCE #( + .INIT(1'b0)) + \gc0.count_d1_reg[1] + (.C(rd_clk), + .CE(p_7_out), + .CLR(out), + .D(D[1]), + .Q(Q[1])); + FDCE #( + .INIT(1'b0)) + \gc0.count_d1_reg[2] + (.C(rd_clk), + .CE(p_7_out), + .CLR(out), + .D(D[2]), + .Q(Q[2])); + FDCE #( + .INIT(1'b0)) + \gc0.count_d1_reg[3] + (.C(rd_clk), + .CE(p_7_out), + .CLR(out), + .D(D[3]), + .Q(Q[3])); + FDCE #( + .INIT(1'b0)) + \gc0.count_d1_reg[4] + (.C(rd_clk), + .CE(p_7_out), + .CLR(out), + .D(D[4]), + .Q(Q[4])); + FDCE #( + .INIT(1'b0)) + \gc0.count_d1_reg[5] + (.C(rd_clk), + .CE(p_7_out), + .CLR(out), + .D(D[5]), + .Q(Q[5])); + FDCE #( + .INIT(1'b0)) + \gc0.count_d1_reg[6] + (.C(rd_clk), + .CE(p_7_out), + .CLR(out), + .D(D[6]), + .Q(Q[6])); + FDCE #( + .INIT(1'b0)) + \gc0.count_d1_reg[7] + (.C(rd_clk), + .CE(p_7_out), + .CLR(out), + .D(D[7]), + .Q(Q[7])); + FDCE #( + .INIT(1'b0)) + \gc0.count_d1_reg[8] + (.C(rd_clk), + .CE(p_7_out), + .CLR(out), + .D(D[8]), + .Q(Q[8])); + FDCE #( + .INIT(1'b0)) + \gc0.count_d1_reg[9] + (.C(rd_clk), + .CE(p_7_out), + .CLR(out), + .D(D[9]), + .Q(Q[9])); + FDPE #( + .INIT(1'b1)) + \gc0.count_reg[0] + (.C(rd_clk), + .CE(p_7_out), + .D(\gc0.count_reg[0]_i_1_n_7 ), + .PRE(out), + .Q(D[0])); + CARRY4 \gc0.count_reg[0]_i_1 + (.CI(1'b0), + .CO({\gc0.count_reg[0]_i_1_n_0 ,\gc0.count_reg[0]_i_1_n_1 ,\gc0.count_reg[0]_i_1_n_2 ,\gc0.count_reg[0]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\gc0.count_reg[0]_i_1_n_4 ,\gc0.count_reg[0]_i_1_n_5 ,\gc0.count_reg[0]_i_1_n_6 ,\gc0.count_reg[0]_i_1_n_7 }), + .S({\gc0.count[0]_i_2_n_0 ,\gc0.count[0]_i_3_n_0 ,\gc0.count[0]_i_4_n_0 ,\gc0.count[0]_i_5_n_0 })); + FDCE #( + .INIT(1'b0)) + \gc0.count_reg[10] + (.C(rd_clk), + .CE(p_7_out), + .CLR(out), + .D(\gc0.count_reg[8]_i_1_n_5 ), + .Q(D[10])); + FDCE #( + .INIT(1'b0)) + \gc0.count_reg[11] + (.C(rd_clk), + .CE(p_7_out), + .CLR(out), + .D(\gc0.count_reg[8]_i_1_n_4 ), + .Q(D[11])); + FDCE #( + .INIT(1'b0)) + \gc0.count_reg[1] + (.C(rd_clk), + .CE(p_7_out), + .CLR(out), + .D(\gc0.count_reg[0]_i_1_n_6 ), + .Q(D[1])); + FDCE #( + .INIT(1'b0)) + \gc0.count_reg[2] + (.C(rd_clk), + .CE(p_7_out), + .CLR(out), + .D(\gc0.count_reg[0]_i_1_n_5 ), + .Q(D[2])); + FDCE #( + .INIT(1'b0)) + \gc0.count_reg[3] + (.C(rd_clk), + .CE(p_7_out), + .CLR(out), + .D(\gc0.count_reg[0]_i_1_n_4 ), + .Q(D[3])); + FDCE #( + .INIT(1'b0)) + \gc0.count_reg[4] + (.C(rd_clk), + .CE(p_7_out), + .CLR(out), + .D(\gc0.count_reg[4]_i_1_n_7 ), + .Q(D[4])); + CARRY4 \gc0.count_reg[4]_i_1 + (.CI(\gc0.count_reg[0]_i_1_n_0 ), + .CO({\gc0.count_reg[4]_i_1_n_0 ,\gc0.count_reg[4]_i_1_n_1 ,\gc0.count_reg[4]_i_1_n_2 ,\gc0.count_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\gc0.count_reg[4]_i_1_n_4 ,\gc0.count_reg[4]_i_1_n_5 ,\gc0.count_reg[4]_i_1_n_6 ,\gc0.count_reg[4]_i_1_n_7 }), + .S({\gc0.count[4]_i_2_n_0 ,\gc0.count[4]_i_3_n_0 ,\gc0.count[4]_i_4_n_0 ,\gc0.count[4]_i_5_n_0 })); + FDCE #( + .INIT(1'b0)) + \gc0.count_reg[5] + (.C(rd_clk), + .CE(p_7_out), + .CLR(out), + .D(\gc0.count_reg[4]_i_1_n_6 ), + .Q(D[5])); + FDCE #( + .INIT(1'b0)) + \gc0.count_reg[6] + (.C(rd_clk), + .CE(p_7_out), + .CLR(out), + .D(\gc0.count_reg[4]_i_1_n_5 ), + .Q(D[6])); + FDCE #( + .INIT(1'b0)) + \gc0.count_reg[7] + (.C(rd_clk), + .CE(p_7_out), + .CLR(out), + .D(\gc0.count_reg[4]_i_1_n_4 ), + .Q(D[7])); + FDCE #( + .INIT(1'b0)) + \gc0.count_reg[8] + (.C(rd_clk), + .CE(p_7_out), + .CLR(out), + .D(\gc0.count_reg[8]_i_1_n_7 ), + .Q(D[8])); + CARRY4 \gc0.count_reg[8]_i_1 + (.CI(\gc0.count_reg[4]_i_1_n_0 ), + .CO({\NLW_gc0.count_reg[8]_i_1_CO_UNCONNECTED [3],\gc0.count_reg[8]_i_1_n_1 ,\gc0.count_reg[8]_i_1_n_2 ,\gc0.count_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\gc0.count_reg[8]_i_1_n_4 ,\gc0.count_reg[8]_i_1_n_5 ,\gc0.count_reg[8]_i_1_n_6 ,\gc0.count_reg[8]_i_1_n_7 }), + .S({\gc0.count[8]_i_2_n_0 ,\gc0.count[8]_i_3_n_0 ,\gc0.count[8]_i_4_n_0 ,\gc0.count[8]_i_5_n_0 })); + FDCE #( + .INIT(1'b0)) + \gc0.count_reg[9] + (.C(rd_clk), + .CE(p_7_out), + .CLR(out), + .D(\gc0.count_reg[8]_i_1_n_6 ), + .Q(D[9])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[0]_i_1 + (.I0(Q[0]), + .I1(Q[1]), + .O(I4[0])); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[10]_i_1 + (.I0(Q[10]), + .I1(Q[11]), + .O(I4[10])); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[1]_i_1 + (.I0(Q[1]), + .I1(Q[2]), + .O(I4[1])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[2]_i_1 + (.I0(Q[2]), + .I1(Q[3]), + .O(I4[2])); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[3]_i_1 + (.I0(Q[3]), + .I1(Q[4]), + .O(I4[3])); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[4]_i_1 + (.I0(Q[4]), + .I1(Q[5]), + .O(I4[4])); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[5]_i_1 + (.I0(Q[5]), + .I1(Q[6]), + .O(I4[5])); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[6]_i_1 + (.I0(Q[6]), + .I1(Q[7]), + .O(I4[6])); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[7]_i_1 + (.I0(Q[7]), + .I1(Q[8]), + .O(I4[7])); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[8]_i_1 + (.I0(Q[8]), + .I1(Q[9]), + .O(I4[8])); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_gc[9]_i_1 + (.I0(Q[9]), + .I1(Q[10]), + .O(I4[9])); +endmodule + +module Arty_Z7_20_v_vid_in_axi4s_0_0_rd_fwft + (out, + empty, + valid, + p_7_out, + tmp_ram_regout_en, + p_1_out, + tmp_ram_rd_en, + rd_clk, + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] , + ram_empty_fb_i_reg, + rd_en); + output [1:0]out; + output empty; + output valid; + output p_7_out; + output tmp_ram_regout_en; + output p_1_out; + output tmp_ram_rd_en; + input rd_clk; + input [1:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ; + input ram_empty_fb_i_reg; + input rd_en; + + (* DONT_TOUCH *) wire aempty_fwft_fb_i; + (* DONT_TOUCH *) wire aempty_fwft_i; + wire aempty_fwft_i0__0; + (* DONT_TOUCH *) wire [1:0]curr_fwft_state; + (* DONT_TOUCH *) wire empty_fwft_fb_i; + (* DONT_TOUCH *) wire empty_fwft_fb_o_i; + wire empty_fwft_fb_o_i0; + (* DONT_TOUCH *) wire empty_fwft_i; + wire empty_fwft_i0; + wire [1:0]next_fwft_state; + wire [1:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ; + wire p_1_out; + wire p_7_out; + wire ram_empty_fb_i_reg; + wire rd_clk; + wire rd_en; + wire tmp_ram_rd_en; + wire tmp_ram_regout_en; + (* DONT_TOUCH *) wire user_valid; + + assign empty = empty_fwft_i; + assign out[1:0] = curr_fwft_state; + assign valid = user_valid; + LUT5 #( + .INIT(32'hBABBBBBB)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2 + (.I0(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [0]), + .I1(ram_empty_fb_i_reg), + .I2(rd_en), + .I3(curr_fwft_state[0]), + .I4(curr_fwft_state[1]), + .O(tmp_ram_rd_en)); + LUT4 #( + .INIT(16'hFFB0)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_3 + (.I0(rd_en), + .I1(curr_fwft_state[0]), + .I2(curr_fwft_state[1]), + .I3(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [0]), + .O(tmp_ram_regout_en)); + LUT4 #( + .INIT(16'h00BF)) + RAM_RD_EN_FWFT + (.I0(rd_en), + .I1(curr_fwft_state[0]), + .I2(curr_fwft_state[1]), + .I3(ram_empty_fb_i_reg), + .O(p_7_out)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + aempty_fwft_fb_i_reg + (.C(rd_clk), + .CE(1'b1), + .D(aempty_fwft_i0__0), + .PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [1]), + .Q(aempty_fwft_fb_i)); + LUT5 #( + .INIT(32'hEEFD8000)) + aempty_fwft_i0 + (.I0(curr_fwft_state[0]), + .I1(ram_empty_fb_i_reg), + .I2(rd_en), + .I3(curr_fwft_state[1]), + .I4(aempty_fwft_fb_i), + .O(aempty_fwft_i0__0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + aempty_fwft_i_reg + (.C(rd_clk), + .CE(1'b1), + .D(aempty_fwft_i0__0), + .PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [1]), + .Q(aempty_fwft_i)); + LUT4 #( + .INIT(16'hF320)) + empty_fwft_fb_i_i_1 + (.I0(rd_en), + .I1(curr_fwft_state[1]), + .I2(curr_fwft_state[0]), + .I3(empty_fwft_fb_i), + .O(empty_fwft_i0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + empty_fwft_fb_i_reg + (.C(rd_clk), + .CE(1'b1), + .D(empty_fwft_i0), + .PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [1]), + .Q(empty_fwft_fb_i)); + LUT4 #( + .INIT(16'hF320)) + empty_fwft_fb_o_i_i_1 + (.I0(rd_en), + .I1(curr_fwft_state[1]), + .I2(curr_fwft_state[0]), + .I3(empty_fwft_fb_o_i), + .O(empty_fwft_fb_o_i0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + empty_fwft_fb_o_i_reg + (.C(rd_clk), + .CE(1'b1), + .D(empty_fwft_fb_o_i0), + .PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [1]), + .Q(empty_fwft_fb_o_i)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + empty_fwft_i_reg + (.C(rd_clk), + .CE(1'b1), + .D(empty_fwft_i0), + .PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [1]), + .Q(empty_fwft_i)); + LUT3 #( + .INIT(8'hBA)) + \gpregsm1.curr_fwft_state[0]_i_1 + (.I0(curr_fwft_state[1]), + .I1(rd_en), + .I2(curr_fwft_state[0]), + .O(next_fwft_state[0])); + LUT4 #( + .INIT(16'h20FF)) + \gpregsm1.curr_fwft_state[1]_i_1 + (.I0(curr_fwft_state[1]), + .I1(rd_en), + .I2(curr_fwft_state[0]), + .I3(ram_empty_fb_i_reg), + .O(next_fwft_state[1])); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDCE #( + .INIT(1'b0)) + \gpregsm1.curr_fwft_state_reg[0] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [1]), + .D(next_fwft_state[0]), + .Q(curr_fwft_state[0])); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDCE #( + .INIT(1'b0)) + \gpregsm1.curr_fwft_state_reg[1] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [1]), + .D(next_fwft_state[1]), + .Q(curr_fwft_state[1])); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDCE #( + .INIT(1'b0)) + \gpregsm1.user_valid_reg + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] [1]), + .D(next_fwft_state[0]), + .Q(user_valid)); + LUT2 #( + .INIT(4'h8)) + \guf.guf1.underflow_i_i_1 + (.I0(rd_en), + .I1(empty_fwft_i), + .O(p_1_out)); +endmodule + +module Arty_Z7_20_v_vid_in_axi4s_0_0_rd_handshaking_flags + (underflow, + p_1_out, + rd_clk); + output underflow; + input p_1_out; + input rd_clk; + + wire p_1_out; + wire rd_clk; + wire underflow; + + FDRE #( + .INIT(1'b0)) + \guf.guf1.underflow_i_reg + (.C(rd_clk), + .CE(1'b1), + .D(p_1_out), + .Q(underflow), + .R(1'b0)); +endmodule + +module Arty_Z7_20_v_vid_in_axi4s_0_0_rd_logic + (empty, + valid, + underflow, + Q, + I4, + tmp_ram_regout_en, + tmp_ram_rd_en, + rd_clk, + out, + WR_PNTR_RD, + rd_en); + output empty; + output valid; + output underflow; + output [11:0]Q; + output [10:0]I4; + output tmp_ram_regout_en; + output tmp_ram_rd_en; + input rd_clk; + input [1:0]out; + input [11:0]WR_PNTR_RD; + input rd_en; + + wire [10:0]I4; + wire [11:0]Q; + wire [11:0]WR_PNTR_RD; + wire empty; + wire [1:0]out; + wire [0:0]p_0_in; + wire p_1_out; + wire p_2_out; + wire p_3_out; + wire p_7_out; + wire rd_clk; + wire rd_en; + wire [11:0]rd_pntr_plus1; + wire tmp_ram_rd_en; + wire tmp_ram_regout_en; + wire underflow; + wire valid; + + Arty_Z7_20_v_vid_in_axi4s_0_0_rd_fwft \gr1.gr1_int.rfwft + (.empty(empty), + .\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (out), + .out({p_3_out,p_0_in}), + .p_1_out(p_1_out), + .p_7_out(p_7_out), + .ram_empty_fb_i_reg(p_2_out), + .rd_clk(rd_clk), + .rd_en(rd_en), + .tmp_ram_rd_en(tmp_ram_rd_en), + .tmp_ram_regout_en(tmp_ram_regout_en), + .valid(valid)); + Arty_Z7_20_v_vid_in_axi4s_0_0_rd_status_flags_as \gras.rsts + (.D(rd_pntr_plus1), + .Q(Q), + .WR_PNTR_RD(WR_PNTR_RD), + .\gpregsm1.curr_fwft_state_reg[1] ({p_3_out,p_0_in}), + .\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (out[1]), + .out(p_2_out), + .rd_clk(rd_clk), + .rd_en(rd_en)); + Arty_Z7_20_v_vid_in_axi4s_0_0_rd_handshaking_flags \grhf.rhf + (.p_1_out(p_1_out), + .rd_clk(rd_clk), + .underflow(underflow)); + Arty_Z7_20_v_vid_in_axi4s_0_0_rd_bin_cntr rpntr + (.D(rd_pntr_plus1), + .I4(I4), + .Q(Q), + .out(out[1]), + .p_7_out(p_7_out), + .rd_clk(rd_clk)); +endmodule + +module Arty_Z7_20_v_vid_in_axi4s_0_0_rd_status_flags_as + (out, + rd_clk, + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] , + rd_en, + \gpregsm1.curr_fwft_state_reg[1] , + WR_PNTR_RD, + Q, + D); + output out; + input rd_clk; + input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ; + input rd_en; + input [1:0]\gpregsm1.curr_fwft_state_reg[1] ; + input [11:0]WR_PNTR_RD; + input [11:0]Q; + input [11:0]D; + + wire [11:0]D; + wire [11:0]Q; + wire [11:0]WR_PNTR_RD; + wire comp0; + wire comp1; + wire [1:0]\gpregsm1.curr_fwft_state_reg[1] ; + wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ; + (* DONT_TOUCH *) wire ram_empty_fb_i; + (* DONT_TOUCH *) wire ram_empty_i; + wire ram_empty_i0_n_0; + wire rd_clk; + wire rd_en; + + assign out = ram_empty_fb_i; + Arty_Z7_20_v_vid_in_axi4s_0_0_compare_4 c0 + (.Q(Q), + .WR_PNTR_RD(WR_PNTR_RD), + .comp0(comp0)); + Arty_Z7_20_v_vid_in_axi4s_0_0_compare_5 c1 + (.D(D), + .WR_PNTR_RD(WR_PNTR_RD), + .comp1(comp1)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + ram_empty_fb_i_reg + (.C(rd_clk), + .CE(1'b1), + .D(ram_empty_i0_n_0), + .PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), + .Q(ram_empty_fb_i)); + LUT6 #( + .INIT(64'hAAAAEFFFAAAAAAAA)) + ram_empty_i0 + (.I0(comp0), + .I1(rd_en), + .I2(\gpregsm1.curr_fwft_state_reg[1] [0]), + .I3(\gpregsm1.curr_fwft_state_reg[1] [1]), + .I4(ram_empty_fb_i), + .I5(comp1), + .O(ram_empty_i0_n_0)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + ram_empty_i_reg + (.C(rd_clk), + .CE(1'b1), + .D(ram_empty_i0_n_0), + .PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ), + .Q(ram_empty_i)); +endmodule + +module Arty_Z7_20_v_vid_in_axi4s_0_0_reset_blk_ramfifo + (out, + \gc0.count_reg[0] , + \grstd1.grst_full.grst_f.rst_d3_reg_0 , + wr_rst_busy, + rd_clk, + wr_clk, + rst); + output [1:0]out; + output [2:0]\gc0.count_reg[0] ; + output \grstd1.grst_full.grst_f.rst_d3_reg_0 ; + output wr_rst_busy; + input rd_clk; + input wr_clk; + input rst; + + wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ; + wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ; + wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ; + wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ; + wire p_7_out; + wire p_8_out; + wire rd_clk; + wire rd_rst_asreg; + (* DONT_TOUCH *) wire [2:0]rd_rst_reg; + wire rst; + (* async_reg = "true" *) (* msgon = "true" *) wire rst_d1; + (* async_reg = "true" *) (* msgon = "true" *) wire rst_d2; + (* async_reg = "true" *) (* msgon = "true" *) wire rst_d3; + (* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1; + (* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2; + (* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1; + (* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2; + wire wr_clk; + wire wr_rst_asreg; + (* DONT_TOUCH *) wire [2:0]wr_rst_reg; + + assign \gc0.count_reg[0] [2:0] = rd_rst_reg; + assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2; + assign out[1:0] = wr_rst_reg[1:0]; + assign wr_rst_busy = rst_d3; + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDPE #( + .INIT(1'b1)) + \grstd1.grst_full.grst_f.rst_d1_reg + (.C(wr_clk), + .CE(1'b1), + .D(1'b0), + .PRE(rst_wr_reg2), + .Q(rst_d1)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDPE #( + .INIT(1'b1)) + \grstd1.grst_full.grst_f.rst_d2_reg + (.C(wr_clk), + .CE(1'b1), + .D(rst_d1), + .PRE(rst_wr_reg2), + .Q(rst_d2)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDPE #( + .INIT(1'b1)) + \grstd1.grst_full.grst_f.rst_d3_reg + (.C(wr_clk), + .CE(1'b1), + .D(rst_d2), + .PRE(rst_wr_reg2), + .Q(rst_d3)); + Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst + (.in0(rd_rst_asreg), + .\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg (\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ), + .out(p_7_out), + .rd_clk(rd_clk)); + Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff_0 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst + (.in0(wr_rst_asreg), + .\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg (\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ), + .out(p_8_out), + .wr_clk(wr_clk)); + Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff_1 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst + (.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ), + .in0(rd_rst_asreg), + .out(p_7_out), + .rd_clk(rd_clk)); + Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff_2 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst + (.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ), + .in0(wr_rst_asreg), + .out(p_8_out), + .wr_clk(wr_clk)); + FDPE #( + .INIT(1'b1)) + \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg + (.C(rd_clk), + .CE(1'b1), + .D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ), + .PRE(rst_rd_reg2), + .Q(rd_rst_asreg)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] + (.C(rd_clk), + .CE(1'b1), + .D(1'b0), + .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ), + .Q(rd_rst_reg[0])); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] + (.C(rd_clk), + .CE(1'b1), + .D(1'b0), + .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ), + .Q(rd_rst_reg[1])); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] + (.C(rd_clk), + .CE(1'b1), + .D(1'b0), + .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ), + .Q(rd_rst_reg[2])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDPE #( + .INIT(1'b0)) + \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg + (.C(rd_clk), + .CE(1'b1), + .D(1'b0), + .PRE(rst), + .Q(rst_rd_reg1)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDPE #( + .INIT(1'b0)) + \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg + (.C(rd_clk), + .CE(1'b1), + .D(rst_rd_reg1), + .PRE(rst), + .Q(rst_rd_reg2)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDPE #( + .INIT(1'b0)) + \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg + (.C(wr_clk), + .CE(1'b1), + .D(1'b0), + .PRE(rst), + .Q(rst_wr_reg1)); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDPE #( + .INIT(1'b0)) + \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg + (.C(wr_clk), + .CE(1'b1), + .D(rst_wr_reg1), + .PRE(rst), + .Q(rst_wr_reg2)); + FDPE #( + .INIT(1'b1)) + \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg + (.C(wr_clk), + .CE(1'b1), + .D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ), + .PRE(rst_wr_reg2), + .Q(wr_rst_asreg)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] + (.C(wr_clk), + .CE(1'b1), + .D(1'b0), + .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ), + .Q(wr_rst_reg[0])); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] + (.C(wr_clk), + .CE(1'b1), + .D(1'b0), + .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ), + .Q(wr_rst_reg[1])); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2] + (.C(wr_clk), + .CE(1'b1), + .D(1'b0), + .PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ), + .Q(wr_rst_reg[2])); +endmodule + +module Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff + (out, + \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg , + in0, + rd_clk); + output out; + output \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ; + input [0:0]in0; + input rd_clk; + + (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; + wire [0:0]in0; + wire \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ; + wire rd_clk; + + assign out = Q_reg; + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[0] + (.C(rd_clk), + .CE(1'b1), + .D(in0), + .Q(Q_reg), + .R(1'b0)); + LUT2 #( + .INIT(4'h2)) + \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1 + (.I0(in0), + .I1(Q_reg), + .O(\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg )); +endmodule + +(* ORIG_REF_NAME = "synchronizer_ff" *) +module Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff_0 + (out, + \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg , + in0, + wr_clk); + output out; + output \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ; + input [0:0]in0; + input wr_clk; + + (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; + wire [0:0]in0; + wire \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ; + wire wr_clk; + + assign out = Q_reg; + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[0] + (.C(wr_clk), + .CE(1'b1), + .D(in0), + .Q(Q_reg), + .R(1'b0)); + LUT2 #( + .INIT(4'h2)) + \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1 + (.I0(in0), + .I1(Q_reg), + .O(\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg )); +endmodule + +(* ORIG_REF_NAME = "synchronizer_ff" *) +module Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff_1 + (AS, + out, + rd_clk, + in0); + output [0:0]AS; + input out; + input rd_clk; + input [0:0]in0; + + wire [0:0]AS; + (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; + wire [0:0]in0; + wire out; + wire rd_clk; + + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[0] + (.C(rd_clk), + .CE(1'b1), + .D(out), + .Q(Q_reg), + .R(1'b0)); + LUT2 #( + .INIT(4'h2)) + \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 + (.I0(in0), + .I1(Q_reg), + .O(AS)); +endmodule + +(* ORIG_REF_NAME = "synchronizer_ff" *) +module Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff_2 + (AS, + out, + wr_clk, + in0); + output [0:0]AS; + input out; + input wr_clk; + input [0:0]in0; + + wire [0:0]AS; + (* async_reg = "true" *) (* msgon = "true" *) wire Q_reg; + wire [0:0]in0; + wire out; + wire wr_clk; + + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDRE #( + .INIT(1'b0)) + \Q_reg_reg[0] + (.C(wr_clk), + .CE(1'b1), + .D(out), + .Q(Q_reg), + .R(1'b0)); + LUT2 #( + .INIT(4'h2)) + \ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1 + (.I0(in0), + .I1(Q_reg), + .O(AS)); +endmodule + +(* ORIG_REF_NAME = "synchronizer_ff" *) +module Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff__parameterized0 + (D, + Q, + rd_clk, + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ); + output [11:0]D; + input [11:0]Q; + input rd_clk; + input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ; + + wire [11:0]Q; + (* async_reg = "true" *) (* msgon = "true" *) wire [11:0]Q_reg; + wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ; + wire rd_clk; + + assign D[11:0] = Q_reg; + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[0] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(Q[0]), + .Q(Q_reg[0])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[10] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(Q[10]), + .Q(Q_reg[10])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[11] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(Q[11]), + .Q(Q_reg[11])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[1] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(Q[1]), + .Q(Q_reg[1])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[2] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(Q[2]), + .Q(Q_reg[2])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[3] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(Q[3]), + .Q(Q_reg[3])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[4] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(Q[4]), + .Q(Q_reg[4])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[5] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(Q[5]), + .Q(Q_reg[5])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[6] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(Q[6]), + .Q(Q_reg[6])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[7] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(Q[7]), + .Q(Q_reg[7])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[8] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(Q[8]), + .Q(Q_reg[8])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[9] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(Q[9]), + .Q(Q_reg[9])); +endmodule + +(* ORIG_REF_NAME = "synchronizer_ff" *) +module Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff__parameterized1 + (D, + Q, + wr_clk, + AR); + output [11:0]D; + input [11:0]Q; + input wr_clk; + input [0:0]AR; + + wire [0:0]AR; + wire [11:0]Q; + (* async_reg = "true" *) (* msgon = "true" *) wire [11:0]Q_reg; + wire wr_clk; + + assign D[11:0] = Q_reg; + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[0] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(Q[0]), + .Q(Q_reg[0])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[10] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(Q[10]), + .Q(Q_reg[10])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[11] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(Q[11]), + .Q(Q_reg[11])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[1] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(Q[1]), + .Q(Q_reg[1])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[2] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(Q[2]), + .Q(Q_reg[2])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[3] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(Q[3]), + .Q(Q_reg[3])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[4] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(Q[4]), + .Q(Q_reg[4])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[5] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(Q[5]), + .Q(Q_reg[5])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[6] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(Q[6]), + .Q(Q_reg[6])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[7] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(Q[7]), + .Q(Q_reg[7])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[8] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(Q[8]), + .Q(Q_reg[8])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[9] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(Q[9]), + .Q(Q_reg[9])); +endmodule + +(* ORIG_REF_NAME = "synchronizer_ff" *) +module Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff__parameterized2 + (out, + \gnxpm_cdc.wr_pntr_bin_reg[10] , + D, + rd_clk, + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ); + output [0:0]out; + output [10:0]\gnxpm_cdc.wr_pntr_bin_reg[10] ; + input [11:0]D; + input rd_clk; + input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ; + + wire [11:0]D; + (* async_reg = "true" *) (* msgon = "true" *) wire [11:0]Q_reg; + wire \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0 ; + wire \gnxpm_cdc.wr_pntr_bin[1]_i_2_n_0 ; + wire [10:0]\gnxpm_cdc.wr_pntr_bin_reg[10] ; + wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ; + wire rd_clk; + + assign out[0] = Q_reg[11]; + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[0] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(D[0]), + .Q(Q_reg[0])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[10] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(D[10]), + .Q(Q_reg[10])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[11] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(D[11]), + .Q(Q_reg[11])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[1] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(D[1]), + .Q(Q_reg[1])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[2] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(D[2]), + .Q(Q_reg[2])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[3] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(D[3]), + .Q(Q_reg[3])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[4] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(D[4]), + .Q(Q_reg[4])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[5] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(D[5]), + .Q(Q_reg[5])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[6] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(D[6]), + .Q(Q_reg[6])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[7] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(D[7]), + .Q(Q_reg[7])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[8] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(D[8]), + .Q(Q_reg[8])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[9] + (.C(rd_clk), + .CE(1'b1), + .CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ), + .D(D[9]), + .Q(Q_reg[9])); + LUT5 #( + .INIT(32'h96696996)) + \gnxpm_cdc.wr_pntr_bin[0]_i_1 + (.I0(\gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0 ), + .I1(Q_reg[1]), + .I2(Q_reg[0]), + .I3(Q_reg[2]), + .I4(\gnxpm_cdc.wr_pntr_bin_reg[10] [6]), + .O(\gnxpm_cdc.wr_pntr_bin_reg[10] [0])); + LUT3 #( + .INIT(8'h96)) + \gnxpm_cdc.wr_pntr_bin[0]_i_2 + (.I0(Q_reg[4]), + .I1(Q_reg[3]), + .I2(Q_reg[5]), + .O(\gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0 )); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_bin[10]_i_1 + (.I0(Q_reg[10]), + .I1(Q_reg[11]), + .O(\gnxpm_cdc.wr_pntr_bin_reg[10] [10])); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.wr_pntr_bin[1]_i_1 + (.I0(\gnxpm_cdc.wr_pntr_bin[1]_i_2_n_0 ), + .I1(Q_reg[6]), + .I2(Q_reg[2]), + .I3(Q_reg[1]), + .I4(Q_reg[3]), + .I5(\gnxpm_cdc.wr_pntr_bin_reg[10] [7]), + .O(\gnxpm_cdc.wr_pntr_bin_reg[10] [1])); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_bin[1]_i_2 + (.I0(Q_reg[4]), + .I1(Q_reg[5]), + .O(\gnxpm_cdc.wr_pntr_bin[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.wr_pntr_bin[2]_i_1 + (.I0(Q_reg[5]), + .I1(Q_reg[6]), + .I2(Q_reg[3]), + .I3(Q_reg[2]), + .I4(Q_reg[4]), + .I5(\gnxpm_cdc.wr_pntr_bin_reg[10] [7]), + .O(\gnxpm_cdc.wr_pntr_bin_reg[10] [2])); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.wr_pntr_bin[3]_i_1 + (.I0(Q_reg[6]), + .I1(Q_reg[7]), + .I2(Q_reg[4]), + .I3(Q_reg[3]), + .I4(Q_reg[5]), + .I5(\gnxpm_cdc.wr_pntr_bin_reg[10] [8]), + .O(\gnxpm_cdc.wr_pntr_bin_reg[10] [3])); + LUT5 #( + .INIT(32'h96696996)) + \gnxpm_cdc.wr_pntr_bin[4]_i_1 + (.I0(Q_reg[6]), + .I1(Q_reg[7]), + .I2(Q_reg[4]), + .I3(Q_reg[5]), + .I4(\gnxpm_cdc.wr_pntr_bin_reg[10] [8]), + .O(\gnxpm_cdc.wr_pntr_bin_reg[10] [4])); + LUT5 #( + .INIT(32'h96696996)) + \gnxpm_cdc.wr_pntr_bin[5]_i_1 + (.I0(Q_reg[7]), + .I1(Q_reg[8]), + .I2(Q_reg[5]), + .I3(Q_reg[6]), + .I4(\gnxpm_cdc.wr_pntr_bin_reg[10] [9]), + .O(\gnxpm_cdc.wr_pntr_bin_reg[10] [5])); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.wr_pntr_bin[6]_i_1 + (.I0(Q_reg[8]), + .I1(Q_reg[6]), + .I2(Q_reg[7]), + .I3(Q_reg[11]), + .I4(Q_reg[9]), + .I5(Q_reg[10]), + .O(\gnxpm_cdc.wr_pntr_bin_reg[10] [6])); + LUT5 #( + .INIT(32'h96696996)) + \gnxpm_cdc.wr_pntr_bin[7]_i_1 + (.I0(Q_reg[9]), + .I1(Q_reg[7]), + .I2(Q_reg[8]), + .I3(Q_reg[11]), + .I4(Q_reg[10]), + .O(\gnxpm_cdc.wr_pntr_bin_reg[10] [7])); + LUT4 #( + .INIT(16'h6996)) + \gnxpm_cdc.wr_pntr_bin[8]_i_1 + (.I0(Q_reg[9]), + .I1(Q_reg[8]), + .I2(Q_reg[11]), + .I3(Q_reg[10]), + .O(\gnxpm_cdc.wr_pntr_bin_reg[10] [8])); + LUT3 #( + .INIT(8'h96)) + \gnxpm_cdc.wr_pntr_bin[9]_i_1 + (.I0(Q_reg[10]), + .I1(Q_reg[9]), + .I2(Q_reg[11]), + .O(\gnxpm_cdc.wr_pntr_bin_reg[10] [9])); +endmodule + +(* ORIG_REF_NAME = "synchronizer_ff" *) +module Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff__parameterized3 + (out, + \gnxpm_cdc.rd_pntr_bin_reg[10] , + D, + wr_clk, + AR); + output [0:0]out; + output [10:0]\gnxpm_cdc.rd_pntr_bin_reg[10] ; + input [11:0]D; + input wr_clk; + input [0:0]AR; + + wire [0:0]AR; + wire [11:0]D; + (* async_reg = "true" *) (* msgon = "true" *) wire [11:0]Q_reg; + wire \gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0 ; + wire \gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0 ; + wire [10:0]\gnxpm_cdc.rd_pntr_bin_reg[10] ; + wire wr_clk; + + assign out[0] = Q_reg[11]; + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[0] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(D[0]), + .Q(Q_reg[0])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[10] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(D[10]), + .Q(Q_reg[10])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[11] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(D[11]), + .Q(Q_reg[11])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[1] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(D[1]), + .Q(Q_reg[1])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[2] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(D[2]), + .Q(Q_reg[2])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[3] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(D[3]), + .Q(Q_reg[3])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[4] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(D[4]), + .Q(Q_reg[4])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[5] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(D[5]), + .Q(Q_reg[5])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[6] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(D[6]), + .Q(Q_reg[6])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[7] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(D[7]), + .Q(Q_reg[7])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[8] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(D[8]), + .Q(Q_reg[8])); + (* ASYNC_REG *) + (* KEEP = "yes" *) + (* msgon = "true" *) + FDCE #( + .INIT(1'b0)) + \Q_reg_reg[9] + (.C(wr_clk), + .CE(1'b1), + .CLR(AR), + .D(D[9]), + .Q(Q_reg[9])); + LUT5 #( + .INIT(32'h96696996)) + \gnxpm_cdc.rd_pntr_bin[0]_i_1 + (.I0(\gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0 ), + .I1(Q_reg[1]), + .I2(Q_reg[0]), + .I3(Q_reg[2]), + .I4(\gnxpm_cdc.rd_pntr_bin_reg[10] [6]), + .O(\gnxpm_cdc.rd_pntr_bin_reg[10] [0])); + LUT3 #( + .INIT(8'h96)) + \gnxpm_cdc.rd_pntr_bin[0]_i_2 + (.I0(Q_reg[4]), + .I1(Q_reg[3]), + .I2(Q_reg[5]), + .O(\gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0 )); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_bin[10]_i_1 + (.I0(Q_reg[10]), + .I1(Q_reg[11]), + .O(\gnxpm_cdc.rd_pntr_bin_reg[10] [10])); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.rd_pntr_bin[1]_i_1 + (.I0(\gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0 ), + .I1(Q_reg[6]), + .I2(Q_reg[2]), + .I3(Q_reg[1]), + .I4(Q_reg[3]), + .I5(\gnxpm_cdc.rd_pntr_bin_reg[10] [7]), + .O(\gnxpm_cdc.rd_pntr_bin_reg[10] [1])); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.rd_pntr_bin[1]_i_2 + (.I0(Q_reg[4]), + .I1(Q_reg[5]), + .O(\gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.rd_pntr_bin[2]_i_1 + (.I0(Q_reg[5]), + .I1(Q_reg[6]), + .I2(Q_reg[3]), + .I3(Q_reg[2]), + .I4(Q_reg[4]), + .I5(\gnxpm_cdc.rd_pntr_bin_reg[10] [7]), + .O(\gnxpm_cdc.rd_pntr_bin_reg[10] [2])); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.rd_pntr_bin[3]_i_1 + (.I0(Q_reg[6]), + .I1(Q_reg[7]), + .I2(Q_reg[4]), + .I3(Q_reg[3]), + .I4(Q_reg[5]), + .I5(\gnxpm_cdc.rd_pntr_bin_reg[10] [8]), + .O(\gnxpm_cdc.rd_pntr_bin_reg[10] [3])); + LUT5 #( + .INIT(32'h96696996)) + \gnxpm_cdc.rd_pntr_bin[4]_i_1 + (.I0(Q_reg[6]), + .I1(Q_reg[7]), + .I2(Q_reg[4]), + .I3(Q_reg[5]), + .I4(\gnxpm_cdc.rd_pntr_bin_reg[10] [8]), + .O(\gnxpm_cdc.rd_pntr_bin_reg[10] [4])); + LUT5 #( + .INIT(32'h96696996)) + \gnxpm_cdc.rd_pntr_bin[5]_i_1 + (.I0(Q_reg[7]), + .I1(Q_reg[8]), + .I2(Q_reg[5]), + .I3(Q_reg[6]), + .I4(\gnxpm_cdc.rd_pntr_bin_reg[10] [9]), + .O(\gnxpm_cdc.rd_pntr_bin_reg[10] [5])); + LUT6 #( + .INIT(64'h6996966996696996)) + \gnxpm_cdc.rd_pntr_bin[6]_i_1 + (.I0(Q_reg[8]), + .I1(Q_reg[6]), + .I2(Q_reg[7]), + .I3(Q_reg[11]), + .I4(Q_reg[9]), + .I5(Q_reg[10]), + .O(\gnxpm_cdc.rd_pntr_bin_reg[10] [6])); + LUT5 #( + .INIT(32'h96696996)) + \gnxpm_cdc.rd_pntr_bin[7]_i_1 + (.I0(Q_reg[9]), + .I1(Q_reg[7]), + .I2(Q_reg[8]), + .I3(Q_reg[11]), + .I4(Q_reg[10]), + .O(\gnxpm_cdc.rd_pntr_bin_reg[10] [7])); + LUT4 #( + .INIT(16'h6996)) + \gnxpm_cdc.rd_pntr_bin[8]_i_1 + (.I0(Q_reg[9]), + .I1(Q_reg[8]), + .I2(Q_reg[11]), + .I3(Q_reg[10]), + .O(\gnxpm_cdc.rd_pntr_bin_reg[10] [8])); + LUT3 #( + .INIT(8'h96)) + \gnxpm_cdc.rd_pntr_bin[9]_i_1 + (.I0(Q_reg[10]), + .I1(Q_reg[9]), + .I2(Q_reg[11]), + .O(\gnxpm_cdc.rd_pntr_bin_reg[10] [9])); +endmodule + +module Arty_Z7_20_v_vid_in_axi4s_0_0_wr_bin_cntr + (D, + Q, + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram , + bin2gray, + ram_full_fb_i_reg, + wr_clk, + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ); + output [11:0]D; + output [11:0]Q; + output [11:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + output [10:0]bin2gray; + input ram_full_fb_i_reg; + input wr_clk; + input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ; + + wire [11:0]D; + wire [11:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ; + wire [11:0]Q; + wire [10:0]bin2gray; + wire \gic0.gc0.count[0]_i_2_n_0 ; + wire \gic0.gc0.count[0]_i_3_n_0 ; + wire \gic0.gc0.count[0]_i_4_n_0 ; + wire \gic0.gc0.count[0]_i_5_n_0 ; + wire \gic0.gc0.count[4]_i_2_n_0 ; + wire \gic0.gc0.count[4]_i_3_n_0 ; + wire \gic0.gc0.count[4]_i_4_n_0 ; + wire \gic0.gc0.count[4]_i_5_n_0 ; + wire \gic0.gc0.count[8]_i_2_n_0 ; + wire \gic0.gc0.count[8]_i_3_n_0 ; + wire \gic0.gc0.count[8]_i_4_n_0 ; + wire \gic0.gc0.count[8]_i_5_n_0 ; + wire \gic0.gc0.count_reg[0]_i_1_n_0 ; + wire \gic0.gc0.count_reg[0]_i_1_n_1 ; + wire \gic0.gc0.count_reg[0]_i_1_n_2 ; + wire \gic0.gc0.count_reg[0]_i_1_n_3 ; + wire \gic0.gc0.count_reg[0]_i_1_n_4 ; + wire \gic0.gc0.count_reg[0]_i_1_n_5 ; + wire \gic0.gc0.count_reg[0]_i_1_n_6 ; + wire \gic0.gc0.count_reg[0]_i_1_n_7 ; + wire \gic0.gc0.count_reg[4]_i_1_n_0 ; + wire \gic0.gc0.count_reg[4]_i_1_n_1 ; + wire \gic0.gc0.count_reg[4]_i_1_n_2 ; + wire \gic0.gc0.count_reg[4]_i_1_n_3 ; + wire \gic0.gc0.count_reg[4]_i_1_n_4 ; + wire \gic0.gc0.count_reg[4]_i_1_n_5 ; + wire \gic0.gc0.count_reg[4]_i_1_n_6 ; + wire \gic0.gc0.count_reg[4]_i_1_n_7 ; + wire \gic0.gc0.count_reg[8]_i_1_n_1 ; + wire \gic0.gc0.count_reg[8]_i_1_n_2 ; + wire \gic0.gc0.count_reg[8]_i_1_n_3 ; + wire \gic0.gc0.count_reg[8]_i_1_n_4 ; + wire \gic0.gc0.count_reg[8]_i_1_n_5 ; + wire \gic0.gc0.count_reg[8]_i_1_n_6 ; + wire \gic0.gc0.count_reg[8]_i_1_n_7 ; + wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ; + wire ram_full_fb_i_reg; + wire wr_clk; + wire [3:3]\NLW_gic0.gc0.count_reg[8]_i_1_CO_UNCONNECTED ; + + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[0]_i_2 + (.I0(D[3]), + .O(\gic0.gc0.count[0]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[0]_i_3 + (.I0(D[2]), + .O(\gic0.gc0.count[0]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[0]_i_4 + (.I0(D[1]), + .O(\gic0.gc0.count[0]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \gic0.gc0.count[0]_i_5 + (.I0(D[0]), + .O(\gic0.gc0.count[0]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[4]_i_2 + (.I0(D[7]), + .O(\gic0.gc0.count[4]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[4]_i_3 + (.I0(D[6]), + .O(\gic0.gc0.count[4]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[4]_i_4 + (.I0(D[5]), + .O(\gic0.gc0.count[4]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[4]_i_5 + (.I0(D[4]), + .O(\gic0.gc0.count[4]_i_5_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[8]_i_2 + (.I0(D[11]), + .O(\gic0.gc0.count[8]_i_2_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[8]_i_3 + (.I0(D[10]), + .O(\gic0.gc0.count[8]_i_3_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[8]_i_4 + (.I0(D[9]), + .O(\gic0.gc0.count[8]_i_4_n_0 )); + LUT1 #( + .INIT(2'h2)) + \gic0.gc0.count[8]_i_5 + (.I0(D[8]), + .O(\gic0.gc0.count[8]_i_5_n_0 )); + FDPE #( + .INIT(1'b1)) + \gic0.gc0.count_d1_reg[0] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(D[0]), + .PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .Q(Q[0])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[10] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(D[10]), + .Q(Q[10])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[11] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(D[11]), + .Q(Q[11])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[1] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(D[1]), + .Q(Q[1])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[2] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(D[2]), + .Q(Q[2])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[3] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(D[3]), + .Q(Q[3])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[4] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(D[4]), + .Q(Q[4])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[5] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(D[5]), + .Q(Q[5])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[6] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(D[6]), + .Q(Q[6])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[7] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(D[7]), + .Q(Q[7])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[8] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(D[8]), + .Q(Q[8])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_d1_reg[9] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(D[9]), + .Q(Q[9])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[0] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(Q[0]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[10] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(Q[10]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [10])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[11] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(Q[11]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [11])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[1] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(Q[1]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[2] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(Q[2]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[3] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(Q[3]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[4] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(Q[4]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[5] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(Q[5]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[6] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(Q[6]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[7] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(Q[7]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[8] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(Q[8]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_d2_reg[9] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(Q[9]), + .Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[0] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(\gic0.gc0.count_reg[0]_i_1_n_7 ), + .Q(D[0])); + CARRY4 \gic0.gc0.count_reg[0]_i_1 + (.CI(1'b0), + .CO({\gic0.gc0.count_reg[0]_i_1_n_0 ,\gic0.gc0.count_reg[0]_i_1_n_1 ,\gic0.gc0.count_reg[0]_i_1_n_2 ,\gic0.gc0.count_reg[0]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\gic0.gc0.count_reg[0]_i_1_n_4 ,\gic0.gc0.count_reg[0]_i_1_n_5 ,\gic0.gc0.count_reg[0]_i_1_n_6 ,\gic0.gc0.count_reg[0]_i_1_n_7 }), + .S({\gic0.gc0.count[0]_i_2_n_0 ,\gic0.gc0.count[0]_i_3_n_0 ,\gic0.gc0.count[0]_i_4_n_0 ,\gic0.gc0.count[0]_i_5_n_0 })); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[10] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(\gic0.gc0.count_reg[8]_i_1_n_5 ), + .Q(D[10])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[11] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(\gic0.gc0.count_reg[8]_i_1_n_4 ), + .Q(D[11])); + FDPE #( + .INIT(1'b1)) + \gic0.gc0.count_reg[1] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .D(\gic0.gc0.count_reg[0]_i_1_n_6 ), + .PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .Q(D[1])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[2] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(\gic0.gc0.count_reg[0]_i_1_n_5 ), + .Q(D[2])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[3] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(\gic0.gc0.count_reg[0]_i_1_n_4 ), + .Q(D[3])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[4] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(\gic0.gc0.count_reg[4]_i_1_n_7 ), + .Q(D[4])); + CARRY4 \gic0.gc0.count_reg[4]_i_1 + (.CI(\gic0.gc0.count_reg[0]_i_1_n_0 ), + .CO({\gic0.gc0.count_reg[4]_i_1_n_0 ,\gic0.gc0.count_reg[4]_i_1_n_1 ,\gic0.gc0.count_reg[4]_i_1_n_2 ,\gic0.gc0.count_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\gic0.gc0.count_reg[4]_i_1_n_4 ,\gic0.gc0.count_reg[4]_i_1_n_5 ,\gic0.gc0.count_reg[4]_i_1_n_6 ,\gic0.gc0.count_reg[4]_i_1_n_7 }), + .S({\gic0.gc0.count[4]_i_2_n_0 ,\gic0.gc0.count[4]_i_3_n_0 ,\gic0.gc0.count[4]_i_4_n_0 ,\gic0.gc0.count[4]_i_5_n_0 })); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[5] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(\gic0.gc0.count_reg[4]_i_1_n_6 ), + .Q(D[5])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[6] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(\gic0.gc0.count_reg[4]_i_1_n_5 ), + .Q(D[6])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[7] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(\gic0.gc0.count_reg[4]_i_1_n_4 ), + .Q(D[7])); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[8] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(\gic0.gc0.count_reg[8]_i_1_n_7 ), + .Q(D[8])); + CARRY4 \gic0.gc0.count_reg[8]_i_1 + (.CI(\gic0.gc0.count_reg[4]_i_1_n_0 ), + .CO({\NLW_gic0.gc0.count_reg[8]_i_1_CO_UNCONNECTED [3],\gic0.gc0.count_reg[8]_i_1_n_1 ,\gic0.gc0.count_reg[8]_i_1_n_2 ,\gic0.gc0.count_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\gic0.gc0.count_reg[8]_i_1_n_4 ,\gic0.gc0.count_reg[8]_i_1_n_5 ,\gic0.gc0.count_reg[8]_i_1_n_6 ,\gic0.gc0.count_reg[8]_i_1_n_7 }), + .S({\gic0.gc0.count[8]_i_2_n_0 ,\gic0.gc0.count[8]_i_3_n_0 ,\gic0.gc0.count[8]_i_4_n_0 ,\gic0.gc0.count[8]_i_5_n_0 })); + FDCE #( + .INIT(1'b0)) + \gic0.gc0.count_reg[9] + (.C(wr_clk), + .CE(ram_full_fb_i_reg), + .CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .D(\gic0.gc0.count_reg[8]_i_1_n_6 ), + .Q(D[9])); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[0]_i_1 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]), + .O(bin2gray[0])); + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[10]_i_1 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [10]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [11]), + .O(bin2gray[10])); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[1]_i_1 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]), + .O(bin2gray[1])); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[2]_i_1 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]), + .O(bin2gray[2])); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[3]_i_1 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]), + .O(bin2gray[3])); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[4]_i_1 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]), + .O(bin2gray[4])); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[5]_i_1 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]), + .O(bin2gray[5])); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[6]_i_1 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]), + .O(bin2gray[6])); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[7]_i_1 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]), + .O(bin2gray[7])); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[8]_i_1 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]), + .O(bin2gray[8])); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT2 #( + .INIT(4'h6)) + \gnxpm_cdc.wr_pntr_gc[9]_i_1 + (.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]), + .I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [10]), + .O(bin2gray[9])); +endmodule + +module Arty_Z7_20_v_vid_in_axi4s_0_0_wr_handshaking_flags + (overflow, + wr_clk, + wr_en, + out, + wr_rst_busy); + output overflow; + input wr_clk; + input wr_en; + input out; + input wr_rst_busy; + + wire \/i__n_0 ; + wire out; + wire overflow; + wire wr_clk; + wire wr_en; + wire wr_rst_busy; + + LUT3 #( + .INIT(8'hA8)) + \/i_ + (.I0(wr_en), + .I1(out), + .I2(wr_rst_busy), + .O(\/i__n_0 )); + FDRE #( + .INIT(1'b0)) + \gof.gof1.overflow_i_reg + (.C(wr_clk), + .CE(1'b1), + .D(\/i__n_0 ), + .Q(overflow), + .R(1'b0)); +endmodule + +module Arty_Z7_20_v_vid_in_axi4s_0_0_wr_logic + (overflow, + \gic0.gc0.count_d1_reg[11] , + Q, + bin2gray, + wr_clk, + out, + wr_en, + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] , + RD_PNTR_WR, + wr_rst_busy); + output overflow; + output \gic0.gc0.count_d1_reg[11] ; + output [11:0]Q; + output [10:0]bin2gray; + input wr_clk; + input out; + input wr_en; + input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ; + input [11:0]RD_PNTR_WR; + input wr_rst_busy; + + wire [11:0]Q; + wire [11:0]RD_PNTR_WR; + wire [10:0]bin2gray; + wire \gic0.gc0.count_d1_reg[11] ; + wire \gwas.wsts_n_0 ; + wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ; + wire out; + wire overflow; + wire [11:0]p_13_out; + wire wr_clk; + wire wr_en; + wire [11:0]wr_pntr_plus2; + wire wr_rst_busy; + + Arty_Z7_20_v_vid_in_axi4s_0_0_wr_status_flags_as \gwas.wsts + (.D(wr_pntr_plus2), + .Q(p_13_out), + .RD_PNTR_WR(RD_PNTR_WR), + .\gic0.gc0.count_d1_reg[11] (\gic0.gc0.count_d1_reg[11] ), + .\grstd1.grst_full.grst_f.rst_d2_reg (out), + .out(\gwas.wsts_n_0 ), + .wr_clk(wr_clk), + .wr_en(wr_en), + .wr_rst_busy(wr_rst_busy)); + Arty_Z7_20_v_vid_in_axi4s_0_0_wr_handshaking_flags \gwhf.whf + (.out(\gwas.wsts_n_0 ), + .overflow(overflow), + .wr_clk(wr_clk), + .wr_en(wr_en), + .wr_rst_busy(wr_rst_busy)); + Arty_Z7_20_v_vid_in_axi4s_0_0_wr_bin_cntr wpntr + (.D(wr_pntr_plus2), + .\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (Q), + .Q(p_13_out), + .bin2gray(bin2gray), + .\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ), + .ram_full_fb_i_reg(\gic0.gc0.count_d1_reg[11] ), + .wr_clk(wr_clk)); +endmodule + +module Arty_Z7_20_v_vid_in_axi4s_0_0_wr_status_flags_as + (out, + \gic0.gc0.count_d1_reg[11] , + wr_clk, + \grstd1.grst_full.grst_f.rst_d2_reg , + wr_rst_busy, + wr_en, + Q, + RD_PNTR_WR, + D); + output out; + output \gic0.gc0.count_d1_reg[11] ; + input wr_clk; + input \grstd1.grst_full.grst_f.rst_d2_reg ; + input wr_rst_busy; + input wr_en; + input [11:0]Q; + input [11:0]RD_PNTR_WR; + input [11:0]D; + + wire \/i__n_0 ; + wire [11:0]D; + wire [11:0]Q; + wire [11:0]RD_PNTR_WR; + wire comp1; + wire comp2; + wire \gic0.gc0.count_d1_reg[11] ; + wire \grstd1.grst_full.grst_f.rst_d2_reg ; + (* DONT_TOUCH *) wire ram_full_fb_i; + (* DONT_TOUCH *) wire ram_full_i; + wire wr_clk; + wire wr_en; + wire wr_rst_busy; + + assign out = ram_full_fb_i; + LUT5 #( + .INIT(32'h55550400)) + \/i_ + (.I0(wr_rst_busy), + .I1(comp2), + .I2(ram_full_fb_i), + .I3(wr_en), + .I4(comp1), + .O(\/i__n_0 )); + LUT2 #( + .INIT(4'h2)) + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1 + (.I0(wr_en), + .I1(ram_full_fb_i), + .O(\gic0.gc0.count_d1_reg[11] )); + Arty_Z7_20_v_vid_in_axi4s_0_0_compare c1 + (.Q(Q), + .RD_PNTR_WR(RD_PNTR_WR), + .comp1(comp1)); + Arty_Z7_20_v_vid_in_axi4s_0_0_compare_3 c2 + (.D(D), + .RD_PNTR_WR(RD_PNTR_WR), + .comp2(comp2)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + ram_full_fb_i_reg + (.C(wr_clk), + .CE(1'b1), + .D(\/i__n_0 ), + .PRE(\grstd1.grst_full.grst_f.rst_d2_reg ), + .Q(ram_full_fb_i)); + (* DONT_TOUCH *) + (* KEEP = "yes" *) + (* equivalent_register_removal = "no" *) + FDPE #( + .INIT(1'b1)) + ram_full_i_reg + (.C(wr_clk), + .CE(1'b1), + .D(\/i__n_0 ), + .PRE(\grstd1.grst_full.grst_f.rst_d2_reg ), + .Q(ram_full_i)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/Arty_Z7_20_v_vid_in_axi4s_0_0_sim_netlist.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/Arty_Z7_20_v_vid_in_axi4s_0_0_sim_netlist.vhdl new file mode 100644 index 0000000..812eceb --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/Arty_Z7_20_v_vid_in_axi4s_0_0_sim_netlist.vhdl @@ -0,0 +1,9229 @@ +-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +-- Date : Sat Mar 04 18:56:32 2017 +-- Host : WK73 running 64-bit Service Pack 1 (build 7601) +-- Command : write_vhdl -force -mode funcsim -rename_top Arty_Z7_20_v_vid_in_axi4s_0_0 -prefix +-- Arty_Z7_20_v_vid_in_axi4s_0_0_ Arty_Z7_20_v_vid_in_axi4s_0_0_sim_netlist.vhdl +-- Design : Arty_Z7_20_v_vid_in_axi4s_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg400-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_v_vid_in_axi4s_v4_0_5_formatter is + port ( + vtd_vblank : out STD_LOGIC; + vtd_vsync : out STD_LOGIC; + vtd_active_video : out STD_LOGIC; + vtd_hblank : out STD_LOGIC; + vtd_hsync : out STD_LOGIC; + vtd_field_id : out STD_LOGIC; + FIFO_WR_DATA : out STD_LOGIC_VECTOR ( 26 downto 0 ); + de_3 : out STD_LOGIC; + vtd_locked_reg_0 : out STD_LOGIC; + vid_io_in_reset : in STD_LOGIC; + vid_io_in_ce : in STD_LOGIC; + vid_active_video : in STD_LOGIC; + vid_io_in_clk : in STD_LOGIC; + vid_vblank : in STD_LOGIC; + vid_hblank : in STD_LOGIC; + vid_vsync : in STD_LOGIC; + vid_hsync : in STD_LOGIC; + vid_field_id : in STD_LOGIC; + vid_data : in STD_LOGIC_VECTOR ( 23 downto 0 ); + axis_enable : in STD_LOGIC + ); +end Arty_Z7_20_v_vid_in_axi4s_0_0_v_vid_in_axi4s_v4_0_5_formatter; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_v_vid_in_axi4s_v4_0_5_formatter is + signal \^fifo_wr_data\ : STD_LOGIC_VECTOR ( 26 downto 0 ); + signal data_1 : STD_LOGIC_VECTOR ( 23 downto 0 ); + signal data_2 : STD_LOGIC_VECTOR ( 23 downto 0 ); + signal de_2 : STD_LOGIC; + signal eol_i_1_n_0 : STD_LOGIC; + signal field_id_2 : STD_LOGIC; + signal sof : STD_LOGIC; + signal sof0 : STD_LOGIC; + signal v_blank_sync_1 : STD_LOGIC; + signal v_blank_sync_2 : STD_LOGIC; + signal vert_blanking_intvl_i_1_n_0 : STD_LOGIC; + signal vert_blanking_intvl_reg_n_0 : STD_LOGIC; + signal \^vtd_active_video\ : STD_LOGIC; + signal \^vtd_field_id\ : STD_LOGIC; + signal vtd_locked_i_1_n_0 : STD_LOGIC; + signal \^vtd_locked_reg_0\ : STD_LOGIC; + signal \^vtd_vblank\ : STD_LOGIC; + signal \^vtd_vsync\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of eol_i_1 : label is "soft_lutpair10"; + attribute SOFT_HLUTNM of sof_i_1 : label is "soft_lutpair10"; +begin + FIFO_WR_DATA(26 downto 0) <= \^fifo_wr_data\(26 downto 0); + vtd_active_video <= \^vtd_active_video\; + vtd_field_id <= \^vtd_field_id\; + vtd_locked_reg_0 <= \^vtd_locked_reg_0\; + vtd_vblank <= \^vtd_vblank\; + vtd_vsync <= \^vtd_vsync\; +\data_1_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => vid_data(0), + Q => data_1(0), + R => vid_io_in_reset + ); +\data_1_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => vid_data(10), + Q => data_1(10), + R => vid_io_in_reset + ); +\data_1_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => vid_data(11), + Q => data_1(11), + R => vid_io_in_reset + ); +\data_1_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => vid_data(12), + Q => data_1(12), + R => vid_io_in_reset + ); +\data_1_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => vid_data(13), + Q => data_1(13), + R => vid_io_in_reset + ); +\data_1_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => vid_data(14), + Q => data_1(14), + R => vid_io_in_reset + ); +\data_1_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => vid_data(15), + Q => data_1(15), + R => vid_io_in_reset + ); +\data_1_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => vid_data(16), + Q => data_1(16), + R => vid_io_in_reset + ); +\data_1_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => vid_data(17), + Q => data_1(17), + R => vid_io_in_reset + ); +\data_1_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => vid_data(18), + Q => data_1(18), + R => vid_io_in_reset + ); +\data_1_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => vid_data(19), + Q => data_1(19), + R => vid_io_in_reset + ); +\data_1_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => vid_data(1), + Q => data_1(1), + R => vid_io_in_reset + ); +\data_1_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => vid_data(20), + Q => data_1(20), + R => vid_io_in_reset + ); +\data_1_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => vid_data(21), + Q => data_1(21), + R => vid_io_in_reset + ); +\data_1_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => vid_data(22), + Q => data_1(22), + R => vid_io_in_reset + ); +\data_1_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => vid_data(23), + Q => data_1(23), + R => vid_io_in_reset + ); +\data_1_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => vid_data(2), + Q => data_1(2), + R => vid_io_in_reset + ); +\data_1_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => vid_data(3), + Q => data_1(3), + R => vid_io_in_reset + ); +\data_1_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => vid_data(4), + Q => data_1(4), + R => vid_io_in_reset + ); +\data_1_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => vid_data(5), + Q => data_1(5), + R => vid_io_in_reset + ); +\data_1_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => vid_data(6), + Q => data_1(6), + R => vid_io_in_reset + ); +\data_1_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => vid_data(7), + Q => data_1(7), + R => vid_io_in_reset + ); +\data_1_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => vid_data(8), + Q => data_1(8), + R => vid_io_in_reset + ); +\data_1_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => vid_data(9), + Q => data_1(9), + R => vid_io_in_reset + ); +\data_2_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_1(0), + Q => data_2(0), + R => vid_io_in_reset + ); +\data_2_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_1(10), + Q => data_2(10), + R => vid_io_in_reset + ); +\data_2_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_1(11), + Q => data_2(11), + R => vid_io_in_reset + ); +\data_2_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_1(12), + Q => data_2(12), + R => vid_io_in_reset + ); +\data_2_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_1(13), + Q => data_2(13), + R => vid_io_in_reset + ); +\data_2_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_1(14), + Q => data_2(14), + R => vid_io_in_reset + ); +\data_2_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_1(15), + Q => data_2(15), + R => vid_io_in_reset + ); +\data_2_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_1(16), + Q => data_2(16), + R => vid_io_in_reset + ); +\data_2_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_1(17), + Q => data_2(17), + R => vid_io_in_reset + ); +\data_2_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_1(18), + Q => data_2(18), + R => vid_io_in_reset + ); +\data_2_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_1(19), + Q => data_2(19), + R => vid_io_in_reset + ); +\data_2_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_1(1), + Q => data_2(1), + R => vid_io_in_reset + ); +\data_2_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_1(20), + Q => data_2(20), + R => vid_io_in_reset + ); +\data_2_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_1(21), + Q => data_2(21), + R => vid_io_in_reset + ); +\data_2_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_1(22), + Q => data_2(22), + R => vid_io_in_reset + ); +\data_2_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_1(23), + Q => data_2(23), + R => vid_io_in_reset + ); +\data_2_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_1(2), + Q => data_2(2), + R => vid_io_in_reset + ); +\data_2_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_1(3), + Q => data_2(3), + R => vid_io_in_reset + ); +\data_2_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_1(4), + Q => data_2(4), + R => vid_io_in_reset + ); +\data_2_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_1(5), + Q => data_2(5), + R => vid_io_in_reset + ); +\data_2_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_1(6), + Q => data_2(6), + R => vid_io_in_reset + ); +\data_2_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_1(7), + Q => data_2(7), + R => vid_io_in_reset + ); +\data_2_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_1(8), + Q => data_2(8), + R => vid_io_in_reset + ); +\data_2_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_1(9), + Q => data_2(9), + R => vid_io_in_reset + ); +\data_3_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_2(0), + Q => \^fifo_wr_data\(0), + R => vid_io_in_reset + ); +\data_3_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_2(10), + Q => \^fifo_wr_data\(10), + R => vid_io_in_reset + ); +\data_3_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_2(11), + Q => \^fifo_wr_data\(11), + R => vid_io_in_reset + ); +\data_3_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_2(12), + Q => \^fifo_wr_data\(12), + R => vid_io_in_reset + ); +\data_3_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_2(13), + Q => \^fifo_wr_data\(13), + R => vid_io_in_reset + ); +\data_3_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_2(14), + Q => \^fifo_wr_data\(14), + R => vid_io_in_reset + ); +\data_3_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_2(15), + Q => \^fifo_wr_data\(15), + R => vid_io_in_reset + ); +\data_3_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_2(16), + Q => \^fifo_wr_data\(16), + R => vid_io_in_reset + ); +\data_3_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_2(17), + Q => \^fifo_wr_data\(17), + R => vid_io_in_reset + ); +\data_3_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_2(18), + Q => \^fifo_wr_data\(18), + R => vid_io_in_reset + ); +\data_3_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_2(19), + Q => \^fifo_wr_data\(19), + R => vid_io_in_reset + ); +\data_3_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_2(1), + Q => \^fifo_wr_data\(1), + R => vid_io_in_reset + ); +\data_3_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_2(20), + Q => \^fifo_wr_data\(20), + R => vid_io_in_reset + ); +\data_3_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_2(21), + Q => \^fifo_wr_data\(21), + R => vid_io_in_reset + ); +\data_3_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_2(22), + Q => \^fifo_wr_data\(22), + R => vid_io_in_reset + ); +\data_3_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_2(23), + Q => \^fifo_wr_data\(23), + R => vid_io_in_reset + ); +\data_3_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_2(2), + Q => \^fifo_wr_data\(2), + R => vid_io_in_reset + ); +\data_3_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_2(3), + Q => \^fifo_wr_data\(3), + R => vid_io_in_reset + ); +\data_3_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_2(4), + Q => \^fifo_wr_data\(4), + R => vid_io_in_reset + ); +\data_3_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_2(5), + Q => \^fifo_wr_data\(5), + R => vid_io_in_reset + ); +\data_3_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_2(6), + Q => \^fifo_wr_data\(6), + R => vid_io_in_reset + ); +\data_3_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_2(7), + Q => \^fifo_wr_data\(7), + R => vid_io_in_reset + ); +\data_3_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_2(8), + Q => \^fifo_wr_data\(8), + R => vid_io_in_reset + ); +\data_3_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => data_2(9), + Q => \^fifo_wr_data\(9), + R => vid_io_in_reset + ); +de_1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => vid_active_video, + Q => \^vtd_active_video\, + R => vid_io_in_reset + ); +de_2_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => \^vtd_active_video\, + Q => de_2, + R => vid_io_in_reset + ); +de_3_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => de_2, + Q => de_3, + R => vid_io_in_reset + ); +eol_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => de_2, + I1 => \^vtd_active_video\, + O => eol_i_1_n_0 + ); +eol_reg: unisim.vcomponents.FDRE + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => eol_i_1_n_0, + Q => \^fifo_wr_data\(24), + R => vid_io_in_reset + ); +field_id_1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => vid_field_id, + Q => \^vtd_field_id\, + R => vid_io_in_reset + ); +field_id_2_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => \^vtd_field_id\, + Q => field_id_2, + R => vid_io_in_reset + ); +field_id_3_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => field_id_2, + Q => \^fifo_wr_data\(26), + R => vid_io_in_reset + ); +hblank_1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => vid_hblank, + Q => vtd_hblank, + R => vid_io_in_reset + ); +hsync_1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => vid_hsync, + Q => vtd_hsync, + R => vid_io_in_reset + ); +sof_1_reg: unisim.vcomponents.FDRE + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => sof, + Q => \^fifo_wr_data\(25), + R => vid_io_in_reset + ); +sof_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => de_2, + I1 => \^vtd_active_video\, + I2 => vert_blanking_intvl_reg_n_0, + O => sof0 + ); +sof_reg: unisim.vcomponents.FDRE + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => sof0, + Q => sof, + R => vid_io_in_reset + ); +v_blank_sync_2_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^vtd_vblank\, + I1 => \^vtd_vsync\, + O => v_blank_sync_1 + ); +v_blank_sync_2_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => v_blank_sync_1, + Q => v_blank_sync_2, + R => vid_io_in_reset + ); +vblank_1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => vid_vblank, + Q => \^vtd_vblank\, + R => vid_io_in_reset + ); +vert_blanking_intvl_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"B0B0F0F0FFB0F0F0" + ) + port map ( + I0 => de_2, + I1 => \^vtd_active_video\, + I2 => vert_blanking_intvl_reg_n_0, + I3 => v_blank_sync_1, + I4 => vid_io_in_ce, + I5 => v_blank_sync_2, + O => vert_blanking_intvl_i_1_n_0 + ); +vert_blanking_intvl_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => '1', + D => vert_blanking_intvl_i_1_n_0, + Q => vert_blanking_intvl_reg_n_0, + R => '0' + ); +vsync_1_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => vid_io_in_clk, + CE => vid_io_in_ce, + D => vid_vsync, + Q => \^vtd_vsync\, + R => vid_io_in_reset + ); +vtd_locked_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000BAAA0000" + ) + port map ( + I0 => \^vtd_locked_reg_0\, + I1 => \^fifo_wr_data\(25), + I2 => vid_io_in_ce, + I3 => sof, + I4 => axis_enable, + I5 => vid_io_in_reset, + O => vtd_locked_i_1_n_0 + ); +vtd_locked_reg: unisim.vcomponents.FDRE + port map ( + C => vid_io_in_clk, + CE => '1', + D => vtd_locked_i_1_n_0, + Q => \^vtd_locked_reg_0\, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_wrapper is + port ( + dout : out STD_LOGIC_VECTOR ( 8 downto 0 ); + wr_clk : in STD_LOGIC; + rd_clk : in STD_LOGIC; + ram_full_fb_i_reg : in STD_LOGIC; + tmp_ram_rd_en : in STD_LOGIC; + tmp_ram_regout_en : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); + din : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); +end Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_wrapper; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_wrapper is + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + attribute CLOCK_DOMAINS : string; + attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT"; + attribute box_type : string; + attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; +begin +\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 + generic map( + DOA_REG => 1, + DOB_REG => 1, + EN_ECC_READ => false, + EN_ECC_WRITE => false, + INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_A => X"000000000", + INIT_B => X"000000000", + INIT_FILE => "NONE", + IS_CLKARDCLK_INVERTED => '0', + IS_CLKBWRCLK_INVERTED => '0', + IS_ENARDEN_INVERTED => '0', + IS_ENBWREN_INVERTED => '0', + IS_RSTRAMARSTRAM_INVERTED => '0', + IS_RSTRAMB_INVERTED => '0', + IS_RSTREGARSTREG_INVERTED => '0', + IS_RSTREGB_INVERTED => '0', + RAM_EXTENSION_A => "NONE", + RAM_EXTENSION_B => "NONE", + RAM_MODE => "TDP", + RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", + READ_WIDTH_A => 9, + READ_WIDTH_B => 9, + RSTREG_PRIORITY_A => "REGCE", + RSTREG_PRIORITY_B => "REGCE", + SIM_COLLISION_CHECK => "ALL", + SIM_DEVICE => "7SERIES", + SRVAL_A => X"000000000", + SRVAL_B => X"000000000", + WRITE_MODE_A => "WRITE_FIRST", + WRITE_MODE_B => "WRITE_FIRST", + WRITE_WIDTH_A => 9, + WRITE_WIDTH_B => 9 + ) + port map ( + ADDRARDADDR(15) => '1', + ADDRARDADDR(14 downto 3) => Q(11 downto 0), + ADDRARDADDR(2 downto 0) => B"111", + ADDRBWRADDR(15) => '1', + ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0), + ADDRBWRADDR(2 downto 0) => B"111", + CASCADEINA => '0', + CASCADEINB => '0', + CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, + CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, + CLKARDCLK => wr_clk, + CLKBWRCLK => rd_clk, + DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, + DIADI(31 downto 8) => B"000000000000000000000000", + DIADI(7 downto 0) => din(7 downto 0), + DIBDI(31 downto 0) => B"00000000000000000000000000000000", + DIPADIP(3 downto 1) => B"000", + DIPADIP(0) => din(8), + DIPBDIP(3 downto 0) => B"0000", + DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0), + DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8), + DOBDO(7 downto 0) => dout(7 downto 0), + DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0), + DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1), + DOPBDOP(0) => dout(8), + ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), + ENARDEN => ram_full_fb_i_reg, + ENBWREN => tmp_ram_rd_en, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), + REGCEAREGCE => '0', + REGCEB => tmp_ram_regout_en, + RSTRAMARSTRAM => '0', + RSTRAMB => '0', + RSTREGARSTREG => '0', + RSTREGB => \out\(0), + SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, + WEA(3) => ram_full_fb_i_reg, + WEA(2) => ram_full_fb_i_reg, + WEA(1) => ram_full_fb_i_reg, + WEA(0) => ram_full_fb_i_reg, + WEBWE(7 downto 0) => B"00000000" + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_wrapper__parameterized0\ is + port ( + dout : out STD_LOGIC_VECTOR ( 8 downto 0 ); + wr_clk : in STD_LOGIC; + rd_clk : in STD_LOGIC; + ram_full_fb_i_reg : in STD_LOGIC; + tmp_ram_rd_en : in STD_LOGIC; + tmp_ram_regout_en : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); + din : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper"; +end \Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_wrapper__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_wrapper__parameterized0\ is + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + attribute CLOCK_DOMAINS : string; + attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT"; + attribute box_type : string; + attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; +begin +\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 + generic map( + DOA_REG => 1, + DOB_REG => 1, + EN_ECC_READ => false, + EN_ECC_WRITE => false, + INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_A => X"000000000", + INIT_B => X"000000000", + INIT_FILE => "NONE", + IS_CLKARDCLK_INVERTED => '0', + IS_CLKBWRCLK_INVERTED => '0', + IS_ENARDEN_INVERTED => '0', + IS_ENBWREN_INVERTED => '0', + IS_RSTRAMARSTRAM_INVERTED => '0', + IS_RSTRAMB_INVERTED => '0', + IS_RSTREGARSTREG_INVERTED => '0', + IS_RSTREGB_INVERTED => '0', + RAM_EXTENSION_A => "NONE", + RAM_EXTENSION_B => "NONE", + RAM_MODE => "TDP", + RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", + READ_WIDTH_A => 9, + READ_WIDTH_B => 9, + RSTREG_PRIORITY_A => "REGCE", + RSTREG_PRIORITY_B => "REGCE", + SIM_COLLISION_CHECK => "ALL", + SIM_DEVICE => "7SERIES", + SRVAL_A => X"000000000", + SRVAL_B => X"000000000", + WRITE_MODE_A => "WRITE_FIRST", + WRITE_MODE_B => "WRITE_FIRST", + WRITE_WIDTH_A => 9, + WRITE_WIDTH_B => 9 + ) + port map ( + ADDRARDADDR(15) => '1', + ADDRARDADDR(14 downto 3) => Q(11 downto 0), + ADDRARDADDR(2 downto 0) => B"111", + ADDRBWRADDR(15) => '1', + ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0), + ADDRBWRADDR(2 downto 0) => B"111", + CASCADEINA => '0', + CASCADEINB => '0', + CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, + CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, + CLKARDCLK => wr_clk, + CLKBWRCLK => rd_clk, + DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, + DIADI(31 downto 8) => B"000000000000000000000000", + DIADI(7 downto 0) => din(7 downto 0), + DIBDI(31 downto 0) => B"00000000000000000000000000000000", + DIPADIP(3 downto 1) => B"000", + DIPADIP(0) => din(8), + DIPBDIP(3 downto 0) => B"0000", + DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0), + DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8), + DOBDO(7 downto 0) => dout(7 downto 0), + DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0), + DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1), + DOPBDOP(0) => dout(8), + ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), + ENARDEN => ram_full_fb_i_reg, + ENBWREN => tmp_ram_rd_en, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), + REGCEAREGCE => '0', + REGCEB => tmp_ram_regout_en, + RSTRAMARSTRAM => '0', + RSTRAMB => '0', + RSTREGARSTREG => '0', + RSTREGB => \out\(0), + SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, + WEA(3) => ram_full_fb_i_reg, + WEA(2) => ram_full_fb_i_reg, + WEA(1) => ram_full_fb_i_reg, + WEA(0) => ram_full_fb_i_reg, + WEBWE(7 downto 0) => B"00000000" + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_wrapper__parameterized1\ is + port ( + dout : out STD_LOGIC_VECTOR ( 8 downto 0 ); + wr_clk : in STD_LOGIC; + rd_clk : in STD_LOGIC; + ram_full_fb_i_reg : in STD_LOGIC; + tmp_ram_rd_en : in STD_LOGIC; + tmp_ram_regout_en : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); + din : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_wrapper__parameterized1\ : entity is "blk_mem_gen_prim_wrapper"; +end \Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_wrapper__parameterized1\; + +architecture STRUCTURE of \Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_wrapper__parameterized1\ is + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + attribute CLOCK_DOMAINS : string; + attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT"; + attribute box_type : string; + attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; +begin +\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 + generic map( + DOA_REG => 1, + DOB_REG => 1, + EN_ECC_READ => false, + EN_ECC_WRITE => false, + INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_A => X"000000000", + INIT_B => X"000000000", + INIT_FILE => "NONE", + IS_CLKARDCLK_INVERTED => '0', + IS_CLKBWRCLK_INVERTED => '0', + IS_ENARDEN_INVERTED => '0', + IS_ENBWREN_INVERTED => '0', + IS_RSTRAMARSTRAM_INVERTED => '0', + IS_RSTRAMB_INVERTED => '0', + IS_RSTREGARSTREG_INVERTED => '0', + IS_RSTREGB_INVERTED => '0', + RAM_EXTENSION_A => "NONE", + RAM_EXTENSION_B => "NONE", + RAM_MODE => "TDP", + RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", + READ_WIDTH_A => 9, + READ_WIDTH_B => 9, + RSTREG_PRIORITY_A => "REGCE", + RSTREG_PRIORITY_B => "REGCE", + SIM_COLLISION_CHECK => "ALL", + SIM_DEVICE => "7SERIES", + SRVAL_A => X"000000000", + SRVAL_B => X"000000000", + WRITE_MODE_A => "WRITE_FIRST", + WRITE_MODE_B => "WRITE_FIRST", + WRITE_WIDTH_A => 9, + WRITE_WIDTH_B => 9 + ) + port map ( + ADDRARDADDR(15) => '1', + ADDRARDADDR(14 downto 3) => Q(11 downto 0), + ADDRARDADDR(2 downto 0) => B"111", + ADDRBWRADDR(15) => '1', + ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0), + ADDRBWRADDR(2 downto 0) => B"111", + CASCADEINA => '0', + CASCADEINB => '0', + CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, + CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, + CLKARDCLK => wr_clk, + CLKBWRCLK => rd_clk, + DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, + DIADI(31 downto 8) => B"000000000000000000000000", + DIADI(7 downto 0) => din(7 downto 0), + DIBDI(31 downto 0) => B"00000000000000000000000000000000", + DIPADIP(3 downto 1) => B"000", + DIPADIP(0) => din(8), + DIPBDIP(3 downto 0) => B"0000", + DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0), + DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8), + DOBDO(7 downto 0) => dout(7 downto 0), + DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0), + DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1), + DOPBDOP(0) => dout(8), + ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), + ENARDEN => ram_full_fb_i_reg, + ENBWREN => tmp_ram_rd_en, + INJECTDBITERR => '0', + INJECTSBITERR => '0', + RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), + REGCEAREGCE => '0', + REGCEB => tmp_ram_regout_en, + RSTRAMARSTRAM => '0', + RSTRAMB => '0', + RSTREGARSTREG => '0', + RSTREGB => \out\(0), + SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, + WEA(3) => ram_full_fb_i_reg, + WEA(2) => ram_full_fb_i_reg, + WEA(1) => ram_full_fb_i_reg, + WEA(0) => ram_full_fb_i_reg, + WEBWE(7 downto 0) => B"00000000" + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_compare is + port ( + comp1 : out STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 11 downto 0 ); + RD_PNTR_WR : in STD_LOGIC_VECTOR ( 11 downto 0 ) + ); +end Arty_Z7_20_v_vid_in_axi4s_0_0_compare; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_compare is + signal carrynet_0 : STD_LOGIC; + signal carrynet_1 : STD_LOGIC; + signal carrynet_2 : STD_LOGIC; + signal carrynet_3 : STD_LOGIC; + signal carrynet_4 : STD_LOGIC; + signal v1_reg : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)"; + attribute box_type : string; + attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)"; + attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE"; +begin +\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => carrynet_3, + CO(2) => carrynet_2, + CO(1) => carrynet_1, + CO(0) => carrynet_0, + CYINIT => '1', + DI(3 downto 0) => B"0000", + O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0), + S(3 downto 0) => v1_reg(3 downto 0) + ); +\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => Q(0), + I1 => RD_PNTR_WR(0), + I2 => Q(1), + I3 => RD_PNTR_WR(1), + O => v1_reg(0) + ); +\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => Q(2), + I1 => RD_PNTR_WR(2), + I2 => Q(3), + I3 => RD_PNTR_WR(3), + O => v1_reg(1) + ); +\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => Q(4), + I1 => RD_PNTR_WR(4), + I2 => Q(5), + I3 => RD_PNTR_WR(5), + O => v1_reg(2) + ); +\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => Q(6), + I1 => RD_PNTR_WR(6), + I2 => Q(7), + I3 => RD_PNTR_WR(7), + O => v1_reg(3) + ); +\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4 + port map ( + CI => carrynet_3, + CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2), + CO(1) => comp1, + CO(0) => carrynet_4, + CYINIT => '0', + DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2), + DI(1 downto 0) => B"00", + O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0), + S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2), + S(1 downto 0) => v1_reg(5 downto 4) + ); +\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => Q(8), + I1 => RD_PNTR_WR(8), + I2 => Q(9), + I3 => RD_PNTR_WR(9), + O => v1_reg(4) + ); +\gmux.gm[5].gms.ms_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => Q(10), + I1 => RD_PNTR_WR(10), + I2 => Q(11), + I3 => RD_PNTR_WR(11), + O => v1_reg(5) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_compare_3 is + port ( + comp2 : out STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 11 downto 0 ); + RD_PNTR_WR : in STD_LOGIC_VECTOR ( 11 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_vid_in_axi4s_0_0_compare_3 : entity is "compare"; +end Arty_Z7_20_v_vid_in_axi4s_0_0_compare_3; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_compare_3 is + signal carrynet_0 : STD_LOGIC; + signal carrynet_1 : STD_LOGIC; + signal carrynet_2 : STD_LOGIC; + signal carrynet_3 : STD_LOGIC; + signal carrynet_4 : STD_LOGIC; + signal v1_reg : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)"; + attribute box_type : string; + attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)"; + attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE"; +begin +\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => carrynet_3, + CO(2) => carrynet_2, + CO(1) => carrynet_1, + CO(0) => carrynet_0, + CYINIT => '1', + DI(3 downto 0) => B"0000", + O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0), + S(3 downto 0) => v1_reg(3 downto 0) + ); +\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => D(0), + I1 => RD_PNTR_WR(0), + I2 => D(1), + I3 => RD_PNTR_WR(1), + O => v1_reg(0) + ); +\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => D(2), + I1 => RD_PNTR_WR(2), + I2 => D(3), + I3 => RD_PNTR_WR(3), + O => v1_reg(1) + ); +\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => D(4), + I1 => RD_PNTR_WR(4), + I2 => D(5), + I3 => RD_PNTR_WR(5), + O => v1_reg(2) + ); +\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => D(6), + I1 => RD_PNTR_WR(6), + I2 => D(7), + I3 => RD_PNTR_WR(7), + O => v1_reg(3) + ); +\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4 + port map ( + CI => carrynet_3, + CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2), + CO(1) => comp2, + CO(0) => carrynet_4, + CYINIT => '0', + DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2), + DI(1 downto 0) => B"00", + O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0), + S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2), + S(1 downto 0) => v1_reg(5 downto 4) + ); +\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => D(8), + I1 => RD_PNTR_WR(8), + I2 => D(9), + I3 => RD_PNTR_WR(9), + O => v1_reg(4) + ); +\gmux.gm[5].gms.ms_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => D(10), + I1 => RD_PNTR_WR(10), + I2 => D(11), + I3 => RD_PNTR_WR(11), + O => v1_reg(5) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_compare_4 is + port ( + comp0 : out STD_LOGIC; + WR_PNTR_RD : in STD_LOGIC_VECTOR ( 11 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 11 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_vid_in_axi4s_0_0_compare_4 : entity is "compare"; +end Arty_Z7_20_v_vid_in_axi4s_0_0_compare_4; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_compare_4 is + signal carrynet_0 : STD_LOGIC; + signal carrynet_1 : STD_LOGIC; + signal carrynet_2 : STD_LOGIC; + signal carrynet_3 : STD_LOGIC; + signal carrynet_4 : STD_LOGIC; + signal v1_reg : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)"; + attribute box_type : string; + attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)"; + attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE"; +begin +\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => carrynet_3, + CO(2) => carrynet_2, + CO(1) => carrynet_1, + CO(0) => carrynet_0, + CYINIT => '1', + DI(3 downto 0) => B"0000", + O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0), + S(3 downto 0) => v1_reg(3 downto 0) + ); +\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => WR_PNTR_RD(0), + I1 => Q(0), + I2 => WR_PNTR_RD(1), + I3 => Q(1), + O => v1_reg(0) + ); +\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => WR_PNTR_RD(2), + I1 => Q(2), + I2 => WR_PNTR_RD(3), + I3 => Q(3), + O => v1_reg(1) + ); +\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => WR_PNTR_RD(4), + I1 => Q(4), + I2 => WR_PNTR_RD(5), + I3 => Q(5), + O => v1_reg(2) + ); +\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => WR_PNTR_RD(6), + I1 => Q(6), + I2 => WR_PNTR_RD(7), + I3 => Q(7), + O => v1_reg(3) + ); +\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4 + port map ( + CI => carrynet_3, + CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2), + CO(1) => comp0, + CO(0) => carrynet_4, + CYINIT => '0', + DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2), + DI(1 downto 0) => B"00", + O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0), + S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2), + S(1 downto 0) => v1_reg(5 downto 4) + ); +\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => WR_PNTR_RD(8), + I1 => Q(8), + I2 => WR_PNTR_RD(9), + I3 => Q(9), + O => v1_reg(4) + ); +\gmux.gm[5].gms.ms_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => WR_PNTR_RD(10), + I1 => Q(10), + I2 => WR_PNTR_RD(11), + I3 => Q(11), + O => v1_reg(5) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_compare_5 is + port ( + comp1 : out STD_LOGIC; + WR_PNTR_RD : in STD_LOGIC_VECTOR ( 11 downto 0 ); + D : in STD_LOGIC_VECTOR ( 11 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_vid_in_axi4s_0_0_compare_5 : entity is "compare"; +end Arty_Z7_20_v_vid_in_axi4s_0_0_compare_5; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_compare_5 is + signal carrynet_0 : STD_LOGIC; + signal carrynet_1 : STD_LOGIC; + signal carrynet_2 : STD_LOGIC; + signal carrynet_3 : STD_LOGIC; + signal carrynet_4 : STD_LOGIC; + signal v1_reg : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)"; + attribute box_type : string; + attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)"; + attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE"; +begin +\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => carrynet_3, + CO(2) => carrynet_2, + CO(1) => carrynet_1, + CO(0) => carrynet_0, + CYINIT => '1', + DI(3 downto 0) => B"0000", + O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0), + S(3 downto 0) => v1_reg(3 downto 0) + ); +\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => WR_PNTR_RD(0), + I1 => D(0), + I2 => WR_PNTR_RD(1), + I3 => D(1), + O => v1_reg(0) + ); +\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => WR_PNTR_RD(2), + I1 => D(2), + I2 => WR_PNTR_RD(3), + I3 => D(3), + O => v1_reg(1) + ); +\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => WR_PNTR_RD(4), + I1 => D(4), + I2 => WR_PNTR_RD(5), + I3 => D(5), + O => v1_reg(2) + ); +\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => WR_PNTR_RD(6), + I1 => D(6), + I2 => WR_PNTR_RD(7), + I3 => D(7), + O => v1_reg(3) + ); +\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4 + port map ( + CI => carrynet_3, + CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2), + CO(1) => comp1, + CO(0) => carrynet_4, + CYINIT => '0', + DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2), + DI(1 downto 0) => B"00", + O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0), + S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2), + S(1 downto 0) => v1_reg(5 downto 4) + ); +\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => WR_PNTR_RD(8), + I1 => D(8), + I2 => WR_PNTR_RD(9), + I3 => D(9), + O => v1_reg(4) + ); +\gmux.gm[5].gms.ms_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => WR_PNTR_RD(10), + I1 => D(10), + I2 => WR_PNTR_RD(11), + I3 => D(11), + O => v1_reg(5) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_rd_bin_cntr is + port ( + D : out STD_LOGIC_VECTOR ( 11 downto 0 ); + Q : out STD_LOGIC_VECTOR ( 11 downto 0 ); + I4 : out STD_LOGIC_VECTOR ( 10 downto 0 ); + p_7_out : in STD_LOGIC; + rd_clk : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); +end Arty_Z7_20_v_vid_in_axi4s_0_0_rd_bin_cntr; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_rd_bin_cntr is + signal \^d\ : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \^q\ : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \gc0.count[0]_i_2_n_0\ : STD_LOGIC; + signal \gc0.count[0]_i_3_n_0\ : STD_LOGIC; + signal \gc0.count[0]_i_4_n_0\ : STD_LOGIC; + signal \gc0.count[0]_i_5_n_0\ : STD_LOGIC; + signal \gc0.count[4]_i_2_n_0\ : STD_LOGIC; + signal \gc0.count[4]_i_3_n_0\ : STD_LOGIC; + signal \gc0.count[4]_i_4_n_0\ : STD_LOGIC; + signal \gc0.count[4]_i_5_n_0\ : STD_LOGIC; + signal \gc0.count[8]_i_2_n_0\ : STD_LOGIC; + signal \gc0.count[8]_i_3_n_0\ : STD_LOGIC; + signal \gc0.count[8]_i_4_n_0\ : STD_LOGIC; + signal \gc0.count[8]_i_5_n_0\ : STD_LOGIC; + signal \gc0.count_reg[0]_i_1_n_0\ : STD_LOGIC; + signal \gc0.count_reg[0]_i_1_n_1\ : STD_LOGIC; + signal \gc0.count_reg[0]_i_1_n_2\ : STD_LOGIC; + signal \gc0.count_reg[0]_i_1_n_3\ : STD_LOGIC; + signal \gc0.count_reg[0]_i_1_n_4\ : STD_LOGIC; + signal \gc0.count_reg[0]_i_1_n_5\ : STD_LOGIC; + signal \gc0.count_reg[0]_i_1_n_6\ : STD_LOGIC; + signal \gc0.count_reg[0]_i_1_n_7\ : STD_LOGIC; + signal \gc0.count_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \gc0.count_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \gc0.count_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \gc0.count_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \gc0.count_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \gc0.count_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \gc0.count_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \gc0.count_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \gc0.count_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \gc0.count_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \gc0.count_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \gc0.count_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \gc0.count_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \gc0.count_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \gc0.count_reg[8]_i_1_n_7\ : STD_LOGIC; + signal \NLW_gc0.count_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[1]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[3]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[4]_i_1\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[5]_i_1\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[6]_i_1\ : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[7]_i_1\ : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[8]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[9]_i_1\ : label is "soft_lutpair4"; +begin + D(11 downto 0) <= \^d\(11 downto 0); + Q(11 downto 0) <= \^q\(11 downto 0); +\gc0.count[0]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^d\(3), + O => \gc0.count[0]_i_2_n_0\ + ); +\gc0.count[0]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^d\(2), + O => \gc0.count[0]_i_3_n_0\ + ); +\gc0.count[0]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^d\(1), + O => \gc0.count[0]_i_4_n_0\ + ); +\gc0.count[0]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^d\(0), + O => \gc0.count[0]_i_5_n_0\ + ); +\gc0.count[4]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^d\(7), + O => \gc0.count[4]_i_2_n_0\ + ); +\gc0.count[4]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^d\(6), + O => \gc0.count[4]_i_3_n_0\ + ); +\gc0.count[4]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^d\(5), + O => \gc0.count[4]_i_4_n_0\ + ); +\gc0.count[4]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^d\(4), + O => \gc0.count[4]_i_5_n_0\ + ); +\gc0.count[8]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^d\(11), + O => \gc0.count[8]_i_2_n_0\ + ); +\gc0.count[8]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^d\(10), + O => \gc0.count[8]_i_3_n_0\ + ); +\gc0.count[8]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^d\(9), + O => \gc0.count[8]_i_4_n_0\ + ); +\gc0.count[8]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^d\(8), + O => \gc0.count[8]_i_5_n_0\ + ); +\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => p_7_out, + CLR => \out\(0), + D => \^d\(0), + Q => \^q\(0) + ); +\gc0.count_d1_reg[10]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => p_7_out, + CLR => \out\(0), + D => \^d\(10), + Q => \^q\(10) + ); +\gc0.count_d1_reg[11]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => p_7_out, + CLR => \out\(0), + D => \^d\(11), + Q => \^q\(11) + ); +\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => p_7_out, + CLR => \out\(0), + D => \^d\(1), + Q => \^q\(1) + ); +\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => p_7_out, + CLR => \out\(0), + D => \^d\(2), + Q => \^q\(2) + ); +\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => p_7_out, + CLR => \out\(0), + D => \^d\(3), + Q => \^q\(3) + ); +\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => p_7_out, + CLR => \out\(0), + D => \^d\(4), + Q => \^q\(4) + ); +\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => p_7_out, + CLR => \out\(0), + D => \^d\(5), + Q => \^q\(5) + ); +\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => p_7_out, + CLR => \out\(0), + D => \^d\(6), + Q => \^q\(6) + ); +\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => p_7_out, + CLR => \out\(0), + D => \^d\(7), + Q => \^q\(7) + ); +\gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => p_7_out, + CLR => \out\(0), + D => \^d\(8), + Q => \^q\(8) + ); +\gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => p_7_out, + CLR => \out\(0), + D => \^d\(9), + Q => \^q\(9) + ); +\gc0.count_reg[0]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => rd_clk, + CE => p_7_out, + D => \gc0.count_reg[0]_i_1_n_7\, + PRE => \out\(0), + Q => \^d\(0) + ); +\gc0.count_reg[0]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \gc0.count_reg[0]_i_1_n_0\, + CO(2) => \gc0.count_reg[0]_i_1_n_1\, + CO(1) => \gc0.count_reg[0]_i_1_n_2\, + CO(0) => \gc0.count_reg[0]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \gc0.count_reg[0]_i_1_n_4\, + O(2) => \gc0.count_reg[0]_i_1_n_5\, + O(1) => \gc0.count_reg[0]_i_1_n_6\, + O(0) => \gc0.count_reg[0]_i_1_n_7\, + S(3) => \gc0.count[0]_i_2_n_0\, + S(2) => \gc0.count[0]_i_3_n_0\, + S(1) => \gc0.count[0]_i_4_n_0\, + S(0) => \gc0.count[0]_i_5_n_0\ + ); +\gc0.count_reg[10]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => p_7_out, + CLR => \out\(0), + D => \gc0.count_reg[8]_i_1_n_5\, + Q => \^d\(10) + ); +\gc0.count_reg[11]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => p_7_out, + CLR => \out\(0), + D => \gc0.count_reg[8]_i_1_n_4\, + Q => \^d\(11) + ); +\gc0.count_reg[1]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => p_7_out, + CLR => \out\(0), + D => \gc0.count_reg[0]_i_1_n_6\, + Q => \^d\(1) + ); +\gc0.count_reg[2]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => p_7_out, + CLR => \out\(0), + D => \gc0.count_reg[0]_i_1_n_5\, + Q => \^d\(2) + ); +\gc0.count_reg[3]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => p_7_out, + CLR => \out\(0), + D => \gc0.count_reg[0]_i_1_n_4\, + Q => \^d\(3) + ); +\gc0.count_reg[4]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => p_7_out, + CLR => \out\(0), + D => \gc0.count_reg[4]_i_1_n_7\, + Q => \^d\(4) + ); +\gc0.count_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \gc0.count_reg[0]_i_1_n_0\, + CO(3) => \gc0.count_reg[4]_i_1_n_0\, + CO(2) => \gc0.count_reg[4]_i_1_n_1\, + CO(1) => \gc0.count_reg[4]_i_1_n_2\, + CO(0) => \gc0.count_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \gc0.count_reg[4]_i_1_n_4\, + O(2) => \gc0.count_reg[4]_i_1_n_5\, + O(1) => \gc0.count_reg[4]_i_1_n_6\, + O(0) => \gc0.count_reg[4]_i_1_n_7\, + S(3) => \gc0.count[4]_i_2_n_0\, + S(2) => \gc0.count[4]_i_3_n_0\, + S(1) => \gc0.count[4]_i_4_n_0\, + S(0) => \gc0.count[4]_i_5_n_0\ + ); +\gc0.count_reg[5]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => p_7_out, + CLR => \out\(0), + D => \gc0.count_reg[4]_i_1_n_6\, + Q => \^d\(5) + ); +\gc0.count_reg[6]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => p_7_out, + CLR => \out\(0), + D => \gc0.count_reg[4]_i_1_n_5\, + Q => \^d\(6) + ); +\gc0.count_reg[7]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => p_7_out, + CLR => \out\(0), + D => \gc0.count_reg[4]_i_1_n_4\, + Q => \^d\(7) + ); +\gc0.count_reg[8]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => p_7_out, + CLR => \out\(0), + D => \gc0.count_reg[8]_i_1_n_7\, + Q => \^d\(8) + ); +\gc0.count_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \gc0.count_reg[4]_i_1_n_0\, + CO(3) => \NLW_gc0.count_reg[8]_i_1_CO_UNCONNECTED\(3), + CO(2) => \gc0.count_reg[8]_i_1_n_1\, + CO(1) => \gc0.count_reg[8]_i_1_n_2\, + CO(0) => \gc0.count_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \gc0.count_reg[8]_i_1_n_4\, + O(2) => \gc0.count_reg[8]_i_1_n_5\, + O(1) => \gc0.count_reg[8]_i_1_n_6\, + O(0) => \gc0.count_reg[8]_i_1_n_7\, + S(3) => \gc0.count[8]_i_2_n_0\, + S(2) => \gc0.count[8]_i_3_n_0\, + S(1) => \gc0.count[8]_i_4_n_0\, + S(0) => \gc0.count[8]_i_5_n_0\ + ); +\gc0.count_reg[9]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => p_7_out, + CLR => \out\(0), + D => \gc0.count_reg[8]_i_1_n_6\, + Q => \^d\(9) + ); +\gnxpm_cdc.rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^q\(0), + I1 => \^q\(1), + O => I4(0) + ); +\gnxpm_cdc.rd_pntr_gc[10]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^q\(10), + I1 => \^q\(11), + O => I4(10) + ); +\gnxpm_cdc.rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^q\(1), + I1 => \^q\(2), + O => I4(1) + ); +\gnxpm_cdc.rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^q\(2), + I1 => \^q\(3), + O => I4(2) + ); +\gnxpm_cdc.rd_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^q\(3), + I1 => \^q\(4), + O => I4(3) + ); +\gnxpm_cdc.rd_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^q\(4), + I1 => \^q\(5), + O => I4(4) + ); +\gnxpm_cdc.rd_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^q\(5), + I1 => \^q\(6), + O => I4(5) + ); +\gnxpm_cdc.rd_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^q\(6), + I1 => \^q\(7), + O => I4(6) + ); +\gnxpm_cdc.rd_pntr_gc[7]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^q\(7), + I1 => \^q\(8), + O => I4(7) + ); +\gnxpm_cdc.rd_pntr_gc[8]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^q\(8), + I1 => \^q\(9), + O => I4(8) + ); +\gnxpm_cdc.rd_pntr_gc[9]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^q\(9), + I1 => \^q\(10), + O => I4(9) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_rd_fwft is + port ( + \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + empty : out STD_LOGIC; + valid : out STD_LOGIC; + p_7_out : out STD_LOGIC; + tmp_ram_regout_en : out STD_LOGIC; + p_1_out : out STD_LOGIC; + tmp_ram_rd_en : out STD_LOGIC; + rd_clk : in STD_LOGIC; + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + ram_empty_fb_i_reg : in STD_LOGIC; + rd_en : in STD_LOGIC + ); +end Arty_Z7_20_v_vid_in_axi4s_0_0_rd_fwft; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_rd_fwft is + signal aempty_fwft_fb_i : STD_LOGIC; + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true; + signal aempty_fwft_i : STD_LOGIC; + attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true; + signal \aempty_fwft_i0__0\ : STD_LOGIC; + signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true; + signal empty_fwft_fb_i : STD_LOGIC; + attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true; + signal empty_fwft_fb_o_i : STD_LOGIC; + attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true; + signal empty_fwft_fb_o_i0 : STD_LOGIC; + signal empty_fwft_i : STD_LOGIC; + attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true; + signal empty_fwft_i0 : STD_LOGIC; + signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal user_valid : STD_LOGIC; + attribute DONT_TOUCH of user_valid : signal is std.standard.true; + attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of aempty_fwft_fb_i_reg : label is "yes"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no"; + attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true; + attribute KEEP of aempty_fwft_i_reg : label is "yes"; + attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no"; + attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true; + attribute KEEP of empty_fwft_fb_i_reg : label is "yes"; + attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no"; + attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true; + attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes"; + attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no"; + attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true; + attribute KEEP of empty_fwft_i_reg : label is "yes"; + attribute equivalent_register_removal of empty_fwft_i_reg : label is "no"; + attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true; + attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes"; + attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no"; + attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true; + attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes"; + attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no"; + attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true; + attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes"; + attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no"; +begin + empty <= empty_fwft_i; + \out\(1 downto 0) <= curr_fwft_state(1 downto 0); + valid <= user_valid; +\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BABBBBBB" + ) + port map ( + I0 => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), + I1 => ram_empty_fb_i_reg, + I2 => rd_en, + I3 => curr_fwft_state(0), + I4 => curr_fwft_state(1), + O => tmp_ram_rd_en + ); +\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFB0" + ) + port map ( + I0 => rd_en, + I1 => curr_fwft_state(0), + I2 => curr_fwft_state(1), + I3 => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), + O => tmp_ram_regout_en + ); +RAM_RD_EN_FWFT: unisim.vcomponents.LUT4 + generic map( + INIT => X"00BF" + ) + port map ( + I0 => rd_en, + I1 => curr_fwft_state(0), + I2 => curr_fwft_state(1), + I3 => ram_empty_fb_i_reg, + O => p_7_out + ); +aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => rd_clk, + CE => '1', + D => \aempty_fwft_i0__0\, + PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1), + Q => aempty_fwft_fb_i + ); +aempty_fwft_i0: unisim.vcomponents.LUT5 + generic map( + INIT => X"EEFD8000" + ) + port map ( + I0 => curr_fwft_state(0), + I1 => ram_empty_fb_i_reg, + I2 => rd_en, + I3 => curr_fwft_state(1), + I4 => aempty_fwft_fb_i, + O => \aempty_fwft_i0__0\ + ); +aempty_fwft_i_reg: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => rd_clk, + CE => '1', + D => \aempty_fwft_i0__0\, + PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1), + Q => aempty_fwft_i + ); +empty_fwft_fb_i_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"F320" + ) + port map ( + I0 => rd_en, + I1 => curr_fwft_state(1), + I2 => curr_fwft_state(0), + I3 => empty_fwft_fb_i, + O => empty_fwft_i0 + ); +empty_fwft_fb_i_reg: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => rd_clk, + CE => '1', + D => empty_fwft_i0, + PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1), + Q => empty_fwft_fb_i + ); +empty_fwft_fb_o_i_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"F320" + ) + port map ( + I0 => rd_en, + I1 => curr_fwft_state(1), + I2 => curr_fwft_state(0), + I3 => empty_fwft_fb_o_i, + O => empty_fwft_fb_o_i0 + ); +empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => rd_clk, + CE => '1', + D => empty_fwft_fb_o_i0, + PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1), + Q => empty_fwft_fb_o_i + ); +empty_fwft_i_reg: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => rd_clk, + CE => '1', + D => empty_fwft_i0, + PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1), + Q => empty_fwft_i + ); +\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"BA" + ) + port map ( + I0 => curr_fwft_state(1), + I1 => rd_en, + I2 => curr_fwft_state(0), + O => next_fwft_state(0) + ); +\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"20FF" + ) + port map ( + I0 => curr_fwft_state(1), + I1 => rd_en, + I2 => curr_fwft_state(0), + I3 => ram_empty_fb_i_reg, + O => next_fwft_state(1) + ); +\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1), + D => next_fwft_state(0), + Q => curr_fwft_state(0) + ); +\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1), + D => next_fwft_state(1), + Q => curr_fwft_state(1) + ); +\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1), + D => next_fwft_state(0), + Q => user_valid + ); +\guf.guf1.underflow_i_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => rd_en, + I1 => empty_fwft_i, + O => p_1_out + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_rd_handshaking_flags is + port ( + underflow : out STD_LOGIC; + p_1_out : in STD_LOGIC; + rd_clk : in STD_LOGIC + ); +end Arty_Z7_20_v_vid_in_axi4s_0_0_rd_handshaking_flags; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_rd_handshaking_flags is +begin +\guf.guf1.underflow_i_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + D => p_1_out, + Q => underflow, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff is + port ( + \out\ : out STD_LOGIC; + \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : out STD_LOGIC; + in0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + rd_clk : in STD_LOGIC + ); +end Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff is + signal Q_reg : STD_LOGIC; + attribute async_reg : string; + attribute async_reg of Q_reg : signal is "true"; + attribute msgon : string; + attribute msgon of Q_reg : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; + attribute msgon of \Q_reg_reg[0]\ : label is "true"; +begin + \out\ <= Q_reg; +\Q_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + D => in0(0), + Q => Q_reg, + R => '0' + ); +\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => in0(0), + I1 => Q_reg, + O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff_0 is + port ( + \out\ : out STD_LOGIC; + \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : out STD_LOGIC; + in0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + wr_clk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff_0 : entity is "synchronizer_ff"; +end Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff_0; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff_0 is + signal Q_reg : STD_LOGIC; + attribute async_reg : string; + attribute async_reg of Q_reg : signal is "true"; + attribute msgon : string; + attribute msgon of Q_reg : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; + attribute msgon of \Q_reg_reg[0]\ : label is "true"; +begin + \out\ <= Q_reg; +\Q_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + D => in0(0), + Q => Q_reg, + R => '0' + ); +\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => in0(0), + I1 => Q_reg, + O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff_1 is + port ( + AS : out STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : in STD_LOGIC; + rd_clk : in STD_LOGIC; + in0 : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff_1 : entity is "synchronizer_ff"; +end Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff_1; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff_1 is + signal Q_reg : STD_LOGIC; + attribute async_reg : string; + attribute async_reg of Q_reg : signal is "true"; + attribute msgon : string; + attribute msgon of Q_reg : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; + attribute msgon of \Q_reg_reg[0]\ : label is "true"; +begin +\Q_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + D => \out\, + Q => Q_reg, + R => '0' + ); +\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => in0(0), + I1 => Q_reg, + O => AS(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff_2 is + port ( + AS : out STD_LOGIC_VECTOR ( 0 to 0 ); + \out\ : in STD_LOGIC; + wr_clk : in STD_LOGIC; + in0 : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff_2 : entity is "synchronizer_ff"; +end Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff_2; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff_2 is + signal Q_reg : STD_LOGIC; + attribute async_reg : string; + attribute async_reg of Q_reg : signal is "true"; + attribute msgon : string; + attribute msgon of Q_reg : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; + attribute msgon of \Q_reg_reg[0]\ : label is "true"; +begin +\Q_reg_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + D => \out\, + Q => Q_reg, + R => '0' + ); +\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => in0(0), + I1 => Q_reg, + O => AS(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff__parameterized0\ is + port ( + D : out STD_LOGIC_VECTOR ( 11 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 11 downto 0 ); + rd_clk : in STD_LOGIC; + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff__parameterized0\ : entity is "synchronizer_ff"; +end \Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff__parameterized0\ is + signal Q_reg : STD_LOGIC_VECTOR ( 11 downto 0 ); + attribute async_reg : string; + attribute async_reg of Q_reg : signal is "true"; + attribute msgon : string; + attribute msgon of Q_reg : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; + attribute msgon of \Q_reg_reg[0]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[10]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[10]\ : label is "yes"; + attribute msgon of \Q_reg_reg[10]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[11]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[11]\ : label is "yes"; + attribute msgon of \Q_reg_reg[11]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[1]\ : label is "yes"; + attribute msgon of \Q_reg_reg[1]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[2]\ : label is "yes"; + attribute msgon of \Q_reg_reg[2]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[3]\ : label is "yes"; + attribute msgon of \Q_reg_reg[3]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[4]\ : label is "yes"; + attribute msgon of \Q_reg_reg[4]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[5]\ : label is "yes"; + attribute msgon of \Q_reg_reg[5]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[6]\ : label is "yes"; + attribute msgon of \Q_reg_reg[6]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[7]\ : label is "yes"; + attribute msgon of \Q_reg_reg[7]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[8]\ : label is "yes"; + attribute msgon of \Q_reg_reg[8]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[9]\ : label is "yes"; + attribute msgon of \Q_reg_reg[9]\ : label is "true"; +begin + D(11 downto 0) <= Q_reg(11 downto 0); +\Q_reg_reg[0]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => Q(0), + Q => Q_reg(0) + ); +\Q_reg_reg[10]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => Q(10), + Q => Q_reg(10) + ); +\Q_reg_reg[11]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => Q(11), + Q => Q_reg(11) + ); +\Q_reg_reg[1]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => Q(1), + Q => Q_reg(1) + ); +\Q_reg_reg[2]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => Q(2), + Q => Q_reg(2) + ); +\Q_reg_reg[3]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => Q(3), + Q => Q_reg(3) + ); +\Q_reg_reg[4]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => Q(4), + Q => Q_reg(4) + ); +\Q_reg_reg[5]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => Q(5), + Q => Q_reg(5) + ); +\Q_reg_reg[6]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => Q(6), + Q => Q_reg(6) + ); +\Q_reg_reg[7]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => Q(7), + Q => Q_reg(7) + ); +\Q_reg_reg[8]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => Q(8), + Q => Q_reg(8) + ); +\Q_reg_reg[9]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => Q(9), + Q => Q_reg(9) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff__parameterized1\ is + port ( + D : out STD_LOGIC_VECTOR ( 11 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 11 downto 0 ); + wr_clk : in STD_LOGIC; + AR : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff__parameterized1\ : entity is "synchronizer_ff"; +end \Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff__parameterized1\; + +architecture STRUCTURE of \Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff__parameterized1\ is + signal Q_reg : STD_LOGIC_VECTOR ( 11 downto 0 ); + attribute async_reg : string; + attribute async_reg of Q_reg : signal is "true"; + attribute msgon : string; + attribute msgon of Q_reg : signal is "true"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; + attribute msgon of \Q_reg_reg[0]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[10]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[10]\ : label is "yes"; + attribute msgon of \Q_reg_reg[10]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[11]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[11]\ : label is "yes"; + attribute msgon of \Q_reg_reg[11]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[1]\ : label is "yes"; + attribute msgon of \Q_reg_reg[1]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[2]\ : label is "yes"; + attribute msgon of \Q_reg_reg[2]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[3]\ : label is "yes"; + attribute msgon of \Q_reg_reg[3]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[4]\ : label is "yes"; + attribute msgon of \Q_reg_reg[4]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[5]\ : label is "yes"; + attribute msgon of \Q_reg_reg[5]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[6]\ : label is "yes"; + attribute msgon of \Q_reg_reg[6]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[7]\ : label is "yes"; + attribute msgon of \Q_reg_reg[7]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[8]\ : label is "yes"; + attribute msgon of \Q_reg_reg[8]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[9]\ : label is "yes"; + attribute msgon of \Q_reg_reg[9]\ : label is "true"; +begin + D(11 downto 0) <= Q_reg(11 downto 0); +\Q_reg_reg[0]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => Q(0), + Q => Q_reg(0) + ); +\Q_reg_reg[10]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => Q(10), + Q => Q_reg(10) + ); +\Q_reg_reg[11]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => Q(11), + Q => Q_reg(11) + ); +\Q_reg_reg[1]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => Q(1), + Q => Q_reg(1) + ); +\Q_reg_reg[2]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => Q(2), + Q => Q_reg(2) + ); +\Q_reg_reg[3]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => Q(3), + Q => Q_reg(3) + ); +\Q_reg_reg[4]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => Q(4), + Q => Q_reg(4) + ); +\Q_reg_reg[5]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => Q(5), + Q => Q_reg(5) + ); +\Q_reg_reg[6]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => Q(6), + Q => Q_reg(6) + ); +\Q_reg_reg[7]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => Q(7), + Q => Q_reg(7) + ); +\Q_reg_reg[8]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => Q(8), + Q => Q_reg(8) + ); +\Q_reg_reg[9]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => Q(9), + Q => Q_reg(9) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff__parameterized2\ is + port ( + \out\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \gnxpm_cdc.wr_pntr_bin_reg[10]\ : out STD_LOGIC_VECTOR ( 10 downto 0 ); + D : in STD_LOGIC_VECTOR ( 11 downto 0 ); + rd_clk : in STD_LOGIC; + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff__parameterized2\ : entity is "synchronizer_ff"; +end \Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff__parameterized2\; + +architecture STRUCTURE of \Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff__parameterized2\ is + signal Q_reg : STD_LOGIC_VECTOR ( 11 downto 0 ); + attribute async_reg : string; + attribute async_reg of Q_reg : signal is "true"; + attribute msgon : string; + attribute msgon of Q_reg : signal is "true"; + signal \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0\ : STD_LOGIC; + signal \gnxpm_cdc.wr_pntr_bin[1]_i_2_n_0\ : STD_LOGIC; + signal \^gnxpm_cdc.wr_pntr_bin_reg[10]\ : STD_LOGIC_VECTOR ( 10 downto 0 ); + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; + attribute msgon of \Q_reg_reg[0]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[10]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[10]\ : label is "yes"; + attribute msgon of \Q_reg_reg[10]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[11]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[11]\ : label is "yes"; + attribute msgon of \Q_reg_reg[11]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[1]\ : label is "yes"; + attribute msgon of \Q_reg_reg[1]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[2]\ : label is "yes"; + attribute msgon of \Q_reg_reg[2]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[3]\ : label is "yes"; + attribute msgon of \Q_reg_reg[3]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[4]\ : label is "yes"; + attribute msgon of \Q_reg_reg[4]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[5]\ : label is "yes"; + attribute msgon of \Q_reg_reg[5]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[6]\ : label is "yes"; + attribute msgon of \Q_reg_reg[6]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[7]\ : label is "yes"; + attribute msgon of \Q_reg_reg[7]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[8]\ : label is "yes"; + attribute msgon of \Q_reg_reg[8]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[9]\ : label is "yes"; + attribute msgon of \Q_reg_reg[9]\ : label is "true"; +begin + \gnxpm_cdc.wr_pntr_bin_reg[10]\(10 downto 0) <= \^gnxpm_cdc.wr_pntr_bin_reg[10]\(10 downto 0); + \out\(0) <= Q_reg(11); +\Q_reg_reg[0]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => D(0), + Q => Q_reg(0) + ); +\Q_reg_reg[10]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => D(10), + Q => Q_reg(10) + ); +\Q_reg_reg[11]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => D(11), + Q => Q_reg(11) + ); +\Q_reg_reg[1]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => D(1), + Q => Q_reg(1) + ); +\Q_reg_reg[2]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => D(2), + Q => Q_reg(2) + ); +\Q_reg_reg[3]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => D(3), + Q => Q_reg(3) + ); +\Q_reg_reg[4]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => D(4), + Q => Q_reg(4) + ); +\Q_reg_reg[5]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => D(5), + Q => Q_reg(5) + ); +\Q_reg_reg[6]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => D(6), + Q => Q_reg(6) + ); +\Q_reg_reg[7]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => D(7), + Q => Q_reg(7) + ); +\Q_reg_reg[8]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => D(8), + Q => Q_reg(8) + ); +\Q_reg_reg[9]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => D(9), + Q => Q_reg(9) + ); +\gnxpm_cdc.wr_pntr_bin[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"96696996" + ) + port map ( + I0 => \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0\, + I1 => Q_reg(1), + I2 => Q_reg(0), + I3 => Q_reg(2), + I4 => \^gnxpm_cdc.wr_pntr_bin_reg[10]\(6), + O => \^gnxpm_cdc.wr_pntr_bin_reg[10]\(0) + ); +\gnxpm_cdc.wr_pntr_bin[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"96" + ) + port map ( + I0 => Q_reg(4), + I1 => Q_reg(3), + I2 => Q_reg(5), + O => \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0\ + ); +\gnxpm_cdc.wr_pntr_bin[10]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => Q_reg(10), + I1 => Q_reg(11), + O => \^gnxpm_cdc.wr_pntr_bin_reg[10]\(10) + ); +\gnxpm_cdc.wr_pntr_bin[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"6996966996696996" + ) + port map ( + I0 => \gnxpm_cdc.wr_pntr_bin[1]_i_2_n_0\, + I1 => Q_reg(6), + I2 => Q_reg(2), + I3 => Q_reg(1), + I4 => Q_reg(3), + I5 => \^gnxpm_cdc.wr_pntr_bin_reg[10]\(7), + O => \^gnxpm_cdc.wr_pntr_bin_reg[10]\(1) + ); +\gnxpm_cdc.wr_pntr_bin[1]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => Q_reg(4), + I1 => Q_reg(5), + O => \gnxpm_cdc.wr_pntr_bin[1]_i_2_n_0\ + ); +\gnxpm_cdc.wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"6996966996696996" + ) + port map ( + I0 => Q_reg(5), + I1 => Q_reg(6), + I2 => Q_reg(3), + I3 => Q_reg(2), + I4 => Q_reg(4), + I5 => \^gnxpm_cdc.wr_pntr_bin_reg[10]\(7), + O => \^gnxpm_cdc.wr_pntr_bin_reg[10]\(2) + ); +\gnxpm_cdc.wr_pntr_bin[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"6996966996696996" + ) + port map ( + I0 => Q_reg(6), + I1 => Q_reg(7), + I2 => Q_reg(4), + I3 => Q_reg(3), + I4 => Q_reg(5), + I5 => \^gnxpm_cdc.wr_pntr_bin_reg[10]\(8), + O => \^gnxpm_cdc.wr_pntr_bin_reg[10]\(3) + ); +\gnxpm_cdc.wr_pntr_bin[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"96696996" + ) + port map ( + I0 => Q_reg(6), + I1 => Q_reg(7), + I2 => Q_reg(4), + I3 => Q_reg(5), + I4 => \^gnxpm_cdc.wr_pntr_bin_reg[10]\(8), + O => \^gnxpm_cdc.wr_pntr_bin_reg[10]\(4) + ); +\gnxpm_cdc.wr_pntr_bin[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"96696996" + ) + port map ( + I0 => Q_reg(7), + I1 => Q_reg(8), + I2 => Q_reg(5), + I3 => Q_reg(6), + I4 => \^gnxpm_cdc.wr_pntr_bin_reg[10]\(9), + O => \^gnxpm_cdc.wr_pntr_bin_reg[10]\(5) + ); +\gnxpm_cdc.wr_pntr_bin[6]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"6996966996696996" + ) + port map ( + I0 => Q_reg(8), + I1 => Q_reg(6), + I2 => Q_reg(7), + I3 => Q_reg(11), + I4 => Q_reg(9), + I5 => Q_reg(10), + O => \^gnxpm_cdc.wr_pntr_bin_reg[10]\(6) + ); +\gnxpm_cdc.wr_pntr_bin[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"96696996" + ) + port map ( + I0 => Q_reg(9), + I1 => Q_reg(7), + I2 => Q_reg(8), + I3 => Q_reg(11), + I4 => Q_reg(10), + O => \^gnxpm_cdc.wr_pntr_bin_reg[10]\(7) + ); +\gnxpm_cdc.wr_pntr_bin[8]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6996" + ) + port map ( + I0 => Q_reg(9), + I1 => Q_reg(8), + I2 => Q_reg(11), + I3 => Q_reg(10), + O => \^gnxpm_cdc.wr_pntr_bin_reg[10]\(8) + ); +\gnxpm_cdc.wr_pntr_bin[9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"96" + ) + port map ( + I0 => Q_reg(10), + I1 => Q_reg(9), + I2 => Q_reg(11), + O => \^gnxpm_cdc.wr_pntr_bin_reg[10]\(9) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff__parameterized3\ is + port ( + \out\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \gnxpm_cdc.rd_pntr_bin_reg[10]\ : out STD_LOGIC_VECTOR ( 10 downto 0 ); + D : in STD_LOGIC_VECTOR ( 11 downto 0 ); + wr_clk : in STD_LOGIC; + AR : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff__parameterized3\ : entity is "synchronizer_ff"; +end \Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff__parameterized3\; + +architecture STRUCTURE of \Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff__parameterized3\ is + signal Q_reg : STD_LOGIC_VECTOR ( 11 downto 0 ); + attribute async_reg : string; + attribute async_reg of Q_reg : signal is "true"; + attribute msgon : string; + attribute msgon of Q_reg : signal is "true"; + signal \gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0\ : STD_LOGIC; + signal \gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0\ : STD_LOGIC; + signal \^gnxpm_cdc.rd_pntr_bin_reg[10]\ : STD_LOGIC_VECTOR ( 10 downto 0 ); + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \Q_reg_reg[0]\ : label is "yes"; + attribute msgon of \Q_reg_reg[0]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[10]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[10]\ : label is "yes"; + attribute msgon of \Q_reg_reg[10]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[11]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[11]\ : label is "yes"; + attribute msgon of \Q_reg_reg[11]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[1]\ : label is "yes"; + attribute msgon of \Q_reg_reg[1]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[2]\ : label is "yes"; + attribute msgon of \Q_reg_reg[2]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[3]\ : label is "yes"; + attribute msgon of \Q_reg_reg[3]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[4]\ : label is "yes"; + attribute msgon of \Q_reg_reg[4]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[5]\ : label is "yes"; + attribute msgon of \Q_reg_reg[5]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[6]\ : label is "yes"; + attribute msgon of \Q_reg_reg[6]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[7]\ : label is "yes"; + attribute msgon of \Q_reg_reg[7]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[8]\ : label is "yes"; + attribute msgon of \Q_reg_reg[8]\ : label is "true"; + attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true; + attribute KEEP of \Q_reg_reg[9]\ : label is "yes"; + attribute msgon of \Q_reg_reg[9]\ : label is "true"; +begin + \gnxpm_cdc.rd_pntr_bin_reg[10]\(10 downto 0) <= \^gnxpm_cdc.rd_pntr_bin_reg[10]\(10 downto 0); + \out\(0) <= Q_reg(11); +\Q_reg_reg[0]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => D(0), + Q => Q_reg(0) + ); +\Q_reg_reg[10]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => D(10), + Q => Q_reg(10) + ); +\Q_reg_reg[11]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => D(11), + Q => Q_reg(11) + ); +\Q_reg_reg[1]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => D(1), + Q => Q_reg(1) + ); +\Q_reg_reg[2]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => D(2), + Q => Q_reg(2) + ); +\Q_reg_reg[3]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => D(3), + Q => Q_reg(3) + ); +\Q_reg_reg[4]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => D(4), + Q => Q_reg(4) + ); +\Q_reg_reg[5]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => D(5), + Q => Q_reg(5) + ); +\Q_reg_reg[6]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => D(6), + Q => Q_reg(6) + ); +\Q_reg_reg[7]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => D(7), + Q => Q_reg(7) + ); +\Q_reg_reg[8]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => D(8), + Q => Q_reg(8) + ); +\Q_reg_reg[9]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => D(9), + Q => Q_reg(9) + ); +\gnxpm_cdc.rd_pntr_bin[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"96696996" + ) + port map ( + I0 => \gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0\, + I1 => Q_reg(1), + I2 => Q_reg(0), + I3 => Q_reg(2), + I4 => \^gnxpm_cdc.rd_pntr_bin_reg[10]\(6), + O => \^gnxpm_cdc.rd_pntr_bin_reg[10]\(0) + ); +\gnxpm_cdc.rd_pntr_bin[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"96" + ) + port map ( + I0 => Q_reg(4), + I1 => Q_reg(3), + I2 => Q_reg(5), + O => \gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0\ + ); +\gnxpm_cdc.rd_pntr_bin[10]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => Q_reg(10), + I1 => Q_reg(11), + O => \^gnxpm_cdc.rd_pntr_bin_reg[10]\(10) + ); +\gnxpm_cdc.rd_pntr_bin[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"6996966996696996" + ) + port map ( + I0 => \gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0\, + I1 => Q_reg(6), + I2 => Q_reg(2), + I3 => Q_reg(1), + I4 => Q_reg(3), + I5 => \^gnxpm_cdc.rd_pntr_bin_reg[10]\(7), + O => \^gnxpm_cdc.rd_pntr_bin_reg[10]\(1) + ); +\gnxpm_cdc.rd_pntr_bin[1]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => Q_reg(4), + I1 => Q_reg(5), + O => \gnxpm_cdc.rd_pntr_bin[1]_i_2_n_0\ + ); +\gnxpm_cdc.rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"6996966996696996" + ) + port map ( + I0 => Q_reg(5), + I1 => Q_reg(6), + I2 => Q_reg(3), + I3 => Q_reg(2), + I4 => Q_reg(4), + I5 => \^gnxpm_cdc.rd_pntr_bin_reg[10]\(7), + O => \^gnxpm_cdc.rd_pntr_bin_reg[10]\(2) + ); +\gnxpm_cdc.rd_pntr_bin[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"6996966996696996" + ) + port map ( + I0 => Q_reg(6), + I1 => Q_reg(7), + I2 => Q_reg(4), + I3 => Q_reg(3), + I4 => Q_reg(5), + I5 => \^gnxpm_cdc.rd_pntr_bin_reg[10]\(8), + O => \^gnxpm_cdc.rd_pntr_bin_reg[10]\(3) + ); +\gnxpm_cdc.rd_pntr_bin[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"96696996" + ) + port map ( + I0 => Q_reg(6), + I1 => Q_reg(7), + I2 => Q_reg(4), + I3 => Q_reg(5), + I4 => \^gnxpm_cdc.rd_pntr_bin_reg[10]\(8), + O => \^gnxpm_cdc.rd_pntr_bin_reg[10]\(4) + ); +\gnxpm_cdc.rd_pntr_bin[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"96696996" + ) + port map ( + I0 => Q_reg(7), + I1 => Q_reg(8), + I2 => Q_reg(5), + I3 => Q_reg(6), + I4 => \^gnxpm_cdc.rd_pntr_bin_reg[10]\(9), + O => \^gnxpm_cdc.rd_pntr_bin_reg[10]\(5) + ); +\gnxpm_cdc.rd_pntr_bin[6]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"6996966996696996" + ) + port map ( + I0 => Q_reg(8), + I1 => Q_reg(6), + I2 => Q_reg(7), + I3 => Q_reg(11), + I4 => Q_reg(9), + I5 => Q_reg(10), + O => \^gnxpm_cdc.rd_pntr_bin_reg[10]\(6) + ); +\gnxpm_cdc.rd_pntr_bin[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"96696996" + ) + port map ( + I0 => Q_reg(9), + I1 => Q_reg(7), + I2 => Q_reg(8), + I3 => Q_reg(11), + I4 => Q_reg(10), + O => \^gnxpm_cdc.rd_pntr_bin_reg[10]\(7) + ); +\gnxpm_cdc.rd_pntr_bin[8]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6996" + ) + port map ( + I0 => Q_reg(9), + I1 => Q_reg(8), + I2 => Q_reg(11), + I3 => Q_reg(10), + O => \^gnxpm_cdc.rd_pntr_bin_reg[10]\(8) + ); +\gnxpm_cdc.rd_pntr_bin[9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"96" + ) + port map ( + I0 => Q_reg(10), + I1 => Q_reg(9), + I2 => Q_reg(11), + O => \^gnxpm_cdc.rd_pntr_bin_reg[10]\(9) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_wr_bin_cntr is + port ( + D : out STD_LOGIC_VECTOR ( 11 downto 0 ); + Q : out STD_LOGIC_VECTOR ( 11 downto 0 ); + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); + bin2gray : out STD_LOGIC_VECTOR ( 10 downto 0 ); + ram_full_fb_i_reg : in STD_LOGIC; + wr_clk : in STD_LOGIC; + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); +end Arty_Z7_20_v_vid_in_axi4s_0_0_wr_bin_cntr; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_wr_bin_cntr is + signal \^d\ : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \^device_7series.no_bmm_info.sdp.simple_prim36.ram\ : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \^q\ : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \gic0.gc0.count[0]_i_2_n_0\ : STD_LOGIC; + signal \gic0.gc0.count[0]_i_3_n_0\ : STD_LOGIC; + signal \gic0.gc0.count[0]_i_4_n_0\ : STD_LOGIC; + signal \gic0.gc0.count[0]_i_5_n_0\ : STD_LOGIC; + signal \gic0.gc0.count[4]_i_2_n_0\ : STD_LOGIC; + signal \gic0.gc0.count[4]_i_3_n_0\ : STD_LOGIC; + signal \gic0.gc0.count[4]_i_4_n_0\ : STD_LOGIC; + signal \gic0.gc0.count[4]_i_5_n_0\ : STD_LOGIC; + signal \gic0.gc0.count[8]_i_2_n_0\ : STD_LOGIC; + signal \gic0.gc0.count[8]_i_3_n_0\ : STD_LOGIC; + signal \gic0.gc0.count[8]_i_4_n_0\ : STD_LOGIC; + signal \gic0.gc0.count[8]_i_5_n_0\ : STD_LOGIC; + signal \gic0.gc0.count_reg[0]_i_1_n_0\ : STD_LOGIC; + signal \gic0.gc0.count_reg[0]_i_1_n_1\ : STD_LOGIC; + signal \gic0.gc0.count_reg[0]_i_1_n_2\ : STD_LOGIC; + signal \gic0.gc0.count_reg[0]_i_1_n_3\ : STD_LOGIC; + signal \gic0.gc0.count_reg[0]_i_1_n_4\ : STD_LOGIC; + signal \gic0.gc0.count_reg[0]_i_1_n_5\ : STD_LOGIC; + signal \gic0.gc0.count_reg[0]_i_1_n_6\ : STD_LOGIC; + signal \gic0.gc0.count_reg[0]_i_1_n_7\ : STD_LOGIC; + signal \gic0.gc0.count_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \gic0.gc0.count_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \gic0.gc0.count_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \gic0.gc0.count_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \gic0.gc0.count_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \gic0.gc0.count_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \gic0.gc0.count_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \gic0.gc0.count_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \gic0.gc0.count_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \gic0.gc0.count_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \gic0.gc0.count_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \gic0.gc0.count_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \gic0.gc0.count_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \gic0.gc0.count_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \gic0.gc0.count_reg[8]_i_1_n_7\ : STD_LOGIC; + signal \NLW_gic0.gc0.count_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[0]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[2]_i_1\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[3]_i_1\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[4]_i_1\ : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[5]_i_1\ : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[6]_i_1\ : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[7]_i_1\ : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[8]_i_1\ : label is "soft_lutpair9"; + attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[9]_i_1\ : label is "soft_lutpair9"; +begin + D(11 downto 0) <= \^d\(11 downto 0); + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(11 downto 0) <= \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(11 downto 0); + Q(11 downto 0) <= \^q\(11 downto 0); +\gic0.gc0.count[0]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^d\(3), + O => \gic0.gc0.count[0]_i_2_n_0\ + ); +\gic0.gc0.count[0]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^d\(2), + O => \gic0.gc0.count[0]_i_3_n_0\ + ); +\gic0.gc0.count[0]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^d\(1), + O => \gic0.gc0.count[0]_i_4_n_0\ + ); +\gic0.gc0.count[0]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^d\(0), + O => \gic0.gc0.count[0]_i_5_n_0\ + ); +\gic0.gc0.count[4]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^d\(7), + O => \gic0.gc0.count[4]_i_2_n_0\ + ); +\gic0.gc0.count[4]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^d\(6), + O => \gic0.gc0.count[4]_i_3_n_0\ + ); +\gic0.gc0.count[4]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^d\(5), + O => \gic0.gc0.count[4]_i_4_n_0\ + ); +\gic0.gc0.count[4]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^d\(4), + O => \gic0.gc0.count[4]_i_5_n_0\ + ); +\gic0.gc0.count[8]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^d\(11), + O => \gic0.gc0.count[8]_i_2_n_0\ + ); +\gic0.gc0.count[8]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^d\(10), + O => \gic0.gc0.count[8]_i_3_n_0\ + ); +\gic0.gc0.count[8]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^d\(9), + O => \gic0.gc0.count[8]_i_4_n_0\ + ); +\gic0.gc0.count[8]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^d\(8), + O => \gic0.gc0.count[8]_i_5_n_0\ + ); +\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + D => \^d\(0), + PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + Q => \^q\(0) + ); +\gic0.gc0.count_d1_reg[10]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \^d\(10), + Q => \^q\(10) + ); +\gic0.gc0.count_d1_reg[11]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \^d\(11), + Q => \^q\(11) + ); +\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \^d\(1), + Q => \^q\(1) + ); +\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \^d\(2), + Q => \^q\(2) + ); +\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \^d\(3), + Q => \^q\(3) + ); +\gic0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \^d\(4), + Q => \^q\(4) + ); +\gic0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \^d\(5), + Q => \^q\(5) + ); +\gic0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \^d\(6), + Q => \^q\(6) + ); +\gic0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \^d\(7), + Q => \^q\(7) + ); +\gic0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \^d\(8), + Q => \^q\(8) + ); +\gic0.gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \^d\(9), + Q => \^q\(9) + ); +\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \^q\(0), + Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(0) + ); +\gic0.gc0.count_d2_reg[10]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \^q\(10), + Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(10) + ); +\gic0.gc0.count_d2_reg[11]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \^q\(11), + Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(11) + ); +\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \^q\(1), + Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(1) + ); +\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \^q\(2), + Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(2) + ); +\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \^q\(3), + Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(3) + ); +\gic0.gc0.count_d2_reg[4]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \^q\(4), + Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(4) + ); +\gic0.gc0.count_d2_reg[5]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \^q\(5), + Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(5) + ); +\gic0.gc0.count_d2_reg[6]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \^q\(6), + Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(6) + ); +\gic0.gc0.count_d2_reg[7]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \^q\(7), + Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(7) + ); +\gic0.gc0.count_d2_reg[8]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \^q\(8), + Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(8) + ); +\gic0.gc0.count_d2_reg[9]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \^q\(9), + Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9) + ); +\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \gic0.gc0.count_reg[0]_i_1_n_7\, + Q => \^d\(0) + ); +\gic0.gc0.count_reg[0]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \gic0.gc0.count_reg[0]_i_1_n_0\, + CO(2) => \gic0.gc0.count_reg[0]_i_1_n_1\, + CO(1) => \gic0.gc0.count_reg[0]_i_1_n_2\, + CO(0) => \gic0.gc0.count_reg[0]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \gic0.gc0.count_reg[0]_i_1_n_4\, + O(2) => \gic0.gc0.count_reg[0]_i_1_n_5\, + O(1) => \gic0.gc0.count_reg[0]_i_1_n_6\, + O(0) => \gic0.gc0.count_reg[0]_i_1_n_7\, + S(3) => \gic0.gc0.count[0]_i_2_n_0\, + S(2) => \gic0.gc0.count[0]_i_3_n_0\, + S(1) => \gic0.gc0.count[0]_i_4_n_0\, + S(0) => \gic0.gc0.count[0]_i_5_n_0\ + ); +\gic0.gc0.count_reg[10]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \gic0.gc0.count_reg[8]_i_1_n_5\, + Q => \^d\(10) + ); +\gic0.gc0.count_reg[11]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \gic0.gc0.count_reg[8]_i_1_n_4\, + Q => \^d\(11) + ); +\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + D => \gic0.gc0.count_reg[0]_i_1_n_6\, + PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + Q => \^d\(1) + ); +\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \gic0.gc0.count_reg[0]_i_1_n_5\, + Q => \^d\(2) + ); +\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \gic0.gc0.count_reg[0]_i_1_n_4\, + Q => \^d\(3) + ); +\gic0.gc0.count_reg[4]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \gic0.gc0.count_reg[4]_i_1_n_7\, + Q => \^d\(4) + ); +\gic0.gc0.count_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \gic0.gc0.count_reg[0]_i_1_n_0\, + CO(3) => \gic0.gc0.count_reg[4]_i_1_n_0\, + CO(2) => \gic0.gc0.count_reg[4]_i_1_n_1\, + CO(1) => \gic0.gc0.count_reg[4]_i_1_n_2\, + CO(0) => \gic0.gc0.count_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \gic0.gc0.count_reg[4]_i_1_n_4\, + O(2) => \gic0.gc0.count_reg[4]_i_1_n_5\, + O(1) => \gic0.gc0.count_reg[4]_i_1_n_6\, + O(0) => \gic0.gc0.count_reg[4]_i_1_n_7\, + S(3) => \gic0.gc0.count[4]_i_2_n_0\, + S(2) => \gic0.gc0.count[4]_i_3_n_0\, + S(1) => \gic0.gc0.count[4]_i_4_n_0\, + S(0) => \gic0.gc0.count[4]_i_5_n_0\ + ); +\gic0.gc0.count_reg[5]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \gic0.gc0.count_reg[4]_i_1_n_6\, + Q => \^d\(5) + ); +\gic0.gc0.count_reg[6]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \gic0.gc0.count_reg[4]_i_1_n_5\, + Q => \^d\(6) + ); +\gic0.gc0.count_reg[7]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \gic0.gc0.count_reg[4]_i_1_n_4\, + Q => \^d\(7) + ); +\gic0.gc0.count_reg[8]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \gic0.gc0.count_reg[8]_i_1_n_7\, + Q => \^d\(8) + ); +\gic0.gc0.count_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \gic0.gc0.count_reg[4]_i_1_n_0\, + CO(3) => \NLW_gic0.gc0.count_reg[8]_i_1_CO_UNCONNECTED\(3), + CO(2) => \gic0.gc0.count_reg[8]_i_1_n_1\, + CO(1) => \gic0.gc0.count_reg[8]_i_1_n_2\, + CO(0) => \gic0.gc0.count_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \gic0.gc0.count_reg[8]_i_1_n_4\, + O(2) => \gic0.gc0.count_reg[8]_i_1_n_5\, + O(1) => \gic0.gc0.count_reg[8]_i_1_n_6\, + O(0) => \gic0.gc0.count_reg[8]_i_1_n_7\, + S(3) => \gic0.gc0.count[8]_i_2_n_0\, + S(2) => \gic0.gc0.count[8]_i_3_n_0\, + S(1) => \gic0.gc0.count[8]_i_4_n_0\, + S(0) => \gic0.gc0.count[8]_i_5_n_0\ + ); +\gic0.gc0.count_reg[9]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => ram_full_fb_i_reg, + CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + D => \gic0.gc0.count_reg[8]_i_1_n_6\, + Q => \^d\(9) + ); +\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(0), + I1 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(1), + O => bin2gray(0) + ); +\gnxpm_cdc.wr_pntr_gc[10]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(10), + I1 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(11), + O => bin2gray(10) + ); +\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(1), + I1 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(2), + O => bin2gray(1) + ); +\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(2), + I1 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(3), + O => bin2gray(2) + ); +\gnxpm_cdc.wr_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(3), + I1 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(4), + O => bin2gray(3) + ); +\gnxpm_cdc.wr_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(4), + I1 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(5), + O => bin2gray(4) + ); +\gnxpm_cdc.wr_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(5), + I1 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(6), + O => bin2gray(5) + ); +\gnxpm_cdc.wr_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(6), + I1 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(7), + O => bin2gray(6) + ); +\gnxpm_cdc.wr_pntr_gc[7]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(7), + I1 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(8), + O => bin2gray(7) + ); +\gnxpm_cdc.wr_pntr_gc[8]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(8), + I1 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9), + O => bin2gray(8) + ); +\gnxpm_cdc.wr_pntr_gc[9]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9), + I1 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(10), + O => bin2gray(9) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_wr_handshaking_flags is + port ( + overflow : out STD_LOGIC; + wr_clk : in STD_LOGIC; + wr_en : in STD_LOGIC; + \out\ : in STD_LOGIC; + wr_rst_busy : in STD_LOGIC + ); +end Arty_Z7_20_v_vid_in_axi4s_0_0_wr_handshaking_flags; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_wr_handshaking_flags is + signal \/i__n_0\ : STD_LOGIC; +begin +\/i_\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => wr_en, + I1 => \out\, + I2 => wr_rst_busy, + O => \/i__n_0\ + ); +\gof.gof1.overflow_i_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + D => \/i__n_0\, + Q => overflow, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_width is + port ( + dout : out STD_LOGIC_VECTOR ( 8 downto 0 ); + wr_clk : in STD_LOGIC; + rd_clk : in STD_LOGIC; + ram_full_fb_i_reg : in STD_LOGIC; + tmp_ram_rd_en : in STD_LOGIC; + tmp_ram_regout_en : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); + din : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); +end Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_width; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_width is +begin +\prim_noinit.ram\: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_wrapper + port map ( + Q(11 downto 0) => Q(11 downto 0), + din(8 downto 0) => din(8 downto 0), + dout(8 downto 0) => dout(8 downto 0), + \gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0), + \out\(0) => \out\(0), + ram_full_fb_i_reg => ram_full_fb_i_reg, + rd_clk => rd_clk, + tmp_ram_rd_en => tmp_ram_rd_en, + tmp_ram_regout_en => tmp_ram_regout_en, + wr_clk => wr_clk + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_width__parameterized0\ is + port ( + dout : out STD_LOGIC_VECTOR ( 8 downto 0 ); + wr_clk : in STD_LOGIC; + rd_clk : in STD_LOGIC; + ram_full_fb_i_reg : in STD_LOGIC; + tmp_ram_rd_en : in STD_LOGIC; + tmp_ram_regout_en : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); + din : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width"; +end \Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_width__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_width__parameterized0\ is +begin +\prim_noinit.ram\: entity work.\Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_wrapper__parameterized0\ + port map ( + Q(11 downto 0) => Q(11 downto 0), + din(8 downto 0) => din(8 downto 0), + dout(8 downto 0) => dout(8 downto 0), + \gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0), + \out\(0) => \out\(0), + ram_full_fb_i_reg => ram_full_fb_i_reg, + rd_clk => rd_clk, + tmp_ram_rd_en => tmp_ram_rd_en, + tmp_ram_regout_en => tmp_ram_regout_en, + wr_clk => wr_clk + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_width__parameterized1\ is + port ( + dout : out STD_LOGIC_VECTOR ( 8 downto 0 ); + wr_clk : in STD_LOGIC; + rd_clk : in STD_LOGIC; + ram_full_fb_i_reg : in STD_LOGIC; + tmp_ram_rd_en : in STD_LOGIC; + tmp_ram_regout_en : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); + din : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width"; +end \Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_width__parameterized1\; + +architecture STRUCTURE of \Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_width__parameterized1\ is +begin +\prim_noinit.ram\: entity work.\Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_wrapper__parameterized1\ + port map ( + Q(11 downto 0) => Q(11 downto 0), + din(8 downto 0) => din(8 downto 0), + dout(8 downto 0) => dout(8 downto 0), + \gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0), + \out\(0) => \out\(0), + ram_full_fb_i_reg => ram_full_fb_i_reg, + rd_clk => rd_clk, + tmp_ram_rd_en => tmp_ram_rd_en, + tmp_ram_regout_en => tmp_ram_regout_en, + wr_clk => wr_clk + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_clk_x_pntrs is + port ( + WR_PNTR_RD : out STD_LOGIC_VECTOR ( 11 downto 0 ); + RD_PNTR_WR : out STD_LOGIC_VECTOR ( 11 downto 0 ); + bin2gray : in STD_LOGIC_VECTOR ( 11 downto 0 ); + wr_clk : in STD_LOGIC; + AR : in STD_LOGIC_VECTOR ( 0 to 0 ); + rd_clk : in STD_LOGIC; + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + I4 : in STD_LOGIC_VECTOR ( 11 downto 0 ) + ); +end Arty_Z7_20_v_vid_in_axi4s_0_0_clk_x_pntrs; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_clk_x_pntrs is + signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1\ : STD_LOGIC; + signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_10\ : STD_LOGIC; + signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_11\ : STD_LOGIC; + signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2\ : STD_LOGIC; + signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3\ : STD_LOGIC; + signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\ : STD_LOGIC; + signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5\ : STD_LOGIC; + signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6\ : STD_LOGIC; + signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7\ : STD_LOGIC; + signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8\ : STD_LOGIC; + signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9\ : STD_LOGIC; + signal gray2bin : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal p_0_out : STD_LOGIC; + signal p_3_out : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal p_4_out : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal p_5_out : STD_LOGIC_VECTOR ( 11 to 11 ); + signal p_6_out : STD_LOGIC_VECTOR ( 11 to 11 ); + signal rd_pntr_gc : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal wr_pntr_gc : STD_LOGIC_VECTOR ( 11 downto 0 ); +begin +\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff__parameterized0\ + port map ( + D(11 downto 0) => p_3_out(11 downto 0), + Q(11 downto 0) => wr_pntr_gc(11 downto 0), + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + rd_clk => rd_clk + ); +\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff__parameterized1\ + port map ( + AR(0) => AR(0), + D(11 downto 0) => p_4_out(11 downto 0), + Q(11 downto 0) => rd_pntr_gc(11 downto 0), + wr_clk => wr_clk + ); +\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff__parameterized2\ + port map ( + D(11 downto 0) => p_3_out(11 downto 0), + \gnxpm_cdc.wr_pntr_bin_reg[10]\(10) => p_0_out, + \gnxpm_cdc.wr_pntr_bin_reg[10]\(9 downto 0) => gray2bin(9 downto 0), + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + \out\(0) => p_5_out(11), + rd_clk => rd_clk + ); +\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff__parameterized3\ + port map ( + AR(0) => AR(0), + D(11 downto 0) => p_4_out(11 downto 0), + \gnxpm_cdc.rd_pntr_bin_reg[10]\(10) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1\, + \gnxpm_cdc.rd_pntr_bin_reg[10]\(9) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2\, + \gnxpm_cdc.rd_pntr_bin_reg[10]\(8) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3\, + \gnxpm_cdc.rd_pntr_bin_reg[10]\(7) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\, + \gnxpm_cdc.rd_pntr_bin_reg[10]\(6) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5\, + \gnxpm_cdc.rd_pntr_bin_reg[10]\(5) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6\, + \gnxpm_cdc.rd_pntr_bin_reg[10]\(4) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7\, + \gnxpm_cdc.rd_pntr_bin_reg[10]\(3) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8\, + \gnxpm_cdc.rd_pntr_bin_reg[10]\(2) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9\, + \gnxpm_cdc.rd_pntr_bin_reg[10]\(1) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_10\, + \gnxpm_cdc.rd_pntr_bin_reg[10]\(0) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_11\, + \out\(0) => p_6_out(11), + wr_clk => wr_clk + ); +\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_11\, + Q => RD_PNTR_WR(0) + ); +\gnxpm_cdc.rd_pntr_bin_reg[10]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1\, + Q => RD_PNTR_WR(10) + ); +\gnxpm_cdc.rd_pntr_bin_reg[11]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => p_6_out(11), + Q => RD_PNTR_WR(11) + ); +\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_10\, + Q => RD_PNTR_WR(1) + ); +\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9\, + Q => RD_PNTR_WR(2) + ); +\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8\, + Q => RD_PNTR_WR(3) + ); +\gnxpm_cdc.rd_pntr_bin_reg[4]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7\, + Q => RD_PNTR_WR(4) + ); +\gnxpm_cdc.rd_pntr_bin_reg[5]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6\, + Q => RD_PNTR_WR(5) + ); +\gnxpm_cdc.rd_pntr_bin_reg[6]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5\, + Q => RD_PNTR_WR(6) + ); +\gnxpm_cdc.rd_pntr_bin_reg[7]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\, + Q => RD_PNTR_WR(7) + ); +\gnxpm_cdc.rd_pntr_bin_reg[8]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3\, + Q => RD_PNTR_WR(8) + ); +\gnxpm_cdc.rd_pntr_bin_reg[9]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2\, + Q => RD_PNTR_WR(9) + ); +\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => I4(0), + Q => rd_pntr_gc(0) + ); +\gnxpm_cdc.rd_pntr_gc_reg[10]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => I4(10), + Q => rd_pntr_gc(10) + ); +\gnxpm_cdc.rd_pntr_gc_reg[11]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => I4(11), + Q => rd_pntr_gc(11) + ); +\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => I4(1), + Q => rd_pntr_gc(1) + ); +\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => I4(2), + Q => rd_pntr_gc(2) + ); +\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => I4(3), + Q => rd_pntr_gc(3) + ); +\gnxpm_cdc.rd_pntr_gc_reg[4]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => I4(4), + Q => rd_pntr_gc(4) + ); +\gnxpm_cdc.rd_pntr_gc_reg[5]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => I4(5), + Q => rd_pntr_gc(5) + ); +\gnxpm_cdc.rd_pntr_gc_reg[6]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => I4(6), + Q => rd_pntr_gc(6) + ); +\gnxpm_cdc.rd_pntr_gc_reg[7]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => I4(7), + Q => rd_pntr_gc(7) + ); +\gnxpm_cdc.rd_pntr_gc_reg[8]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => I4(8), + Q => rd_pntr_gc(8) + ); +\gnxpm_cdc.rd_pntr_gc_reg[9]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => I4(9), + Q => rd_pntr_gc(9) + ); +\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => gray2bin(0), + Q => WR_PNTR_RD(0) + ); +\gnxpm_cdc.wr_pntr_bin_reg[10]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => p_0_out, + Q => WR_PNTR_RD(10) + ); +\gnxpm_cdc.wr_pntr_bin_reg[11]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => p_5_out(11), + Q => WR_PNTR_RD(11) + ); +\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => gray2bin(1), + Q => WR_PNTR_RD(1) + ); +\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => gray2bin(2), + Q => WR_PNTR_RD(2) + ); +\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => gray2bin(3), + Q => WR_PNTR_RD(3) + ); +\gnxpm_cdc.wr_pntr_bin_reg[4]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => gray2bin(4), + Q => WR_PNTR_RD(4) + ); +\gnxpm_cdc.wr_pntr_bin_reg[5]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => gray2bin(5), + Q => WR_PNTR_RD(5) + ); +\gnxpm_cdc.wr_pntr_bin_reg[6]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => gray2bin(6), + Q => WR_PNTR_RD(6) + ); +\gnxpm_cdc.wr_pntr_bin_reg[7]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => gray2bin(7), + Q => WR_PNTR_RD(7) + ); +\gnxpm_cdc.wr_pntr_bin_reg[8]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => gray2bin(8), + Q => WR_PNTR_RD(8) + ); +\gnxpm_cdc.wr_pntr_bin_reg[9]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0), + D => gray2bin(9), + Q => WR_PNTR_RD(9) + ); +\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => bin2gray(0), + Q => wr_pntr_gc(0) + ); +\gnxpm_cdc.wr_pntr_gc_reg[10]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => bin2gray(10), + Q => wr_pntr_gc(10) + ); +\gnxpm_cdc.wr_pntr_gc_reg[11]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => bin2gray(11), + Q => wr_pntr_gc(11) + ); +\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => bin2gray(1), + Q => wr_pntr_gc(1) + ); +\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => bin2gray(2), + Q => wr_pntr_gc(2) + ); +\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => bin2gray(3), + Q => wr_pntr_gc(3) + ); +\gnxpm_cdc.wr_pntr_gc_reg[4]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => bin2gray(4), + Q => wr_pntr_gc(4) + ); +\gnxpm_cdc.wr_pntr_gc_reg[5]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => bin2gray(5), + Q => wr_pntr_gc(5) + ); +\gnxpm_cdc.wr_pntr_gc_reg[6]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => bin2gray(6), + Q => wr_pntr_gc(6) + ); +\gnxpm_cdc.wr_pntr_gc_reg[7]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => bin2gray(7), + Q => wr_pntr_gc(7) + ); +\gnxpm_cdc.wr_pntr_gc_reg[8]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => bin2gray(8), + Q => wr_pntr_gc(8) + ); +\gnxpm_cdc.wr_pntr_gc_reg[9]\: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + CLR => AR(0), + D => bin2gray(9), + Q => wr_pntr_gc(9) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_rd_status_flags_as is + port ( + \out\ : out STD_LOGIC; + rd_clk : in STD_LOGIC; + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + rd_en : in STD_LOGIC; + \gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + WR_PNTR_RD : in STD_LOGIC_VECTOR ( 11 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 11 downto 0 ); + D : in STD_LOGIC_VECTOR ( 11 downto 0 ) + ); +end Arty_Z7_20_v_vid_in_axi4s_0_0_rd_status_flags_as; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_rd_status_flags_as is + signal comp0 : STD_LOGIC; + signal comp1 : STD_LOGIC; + signal ram_empty_fb_i : STD_LOGIC; + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true; + signal ram_empty_i : STD_LOGIC; + attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true; + signal ram_empty_i0_n_0 : STD_LOGIC; + attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of ram_empty_fb_i_reg : label is "yes"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no"; + attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true; + attribute KEEP of ram_empty_i_reg : label is "yes"; + attribute equivalent_register_removal of ram_empty_i_reg : label is "no"; +begin + \out\ <= ram_empty_fb_i; +c0: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_compare_4 + port map ( + Q(11 downto 0) => Q(11 downto 0), + WR_PNTR_RD(11 downto 0) => WR_PNTR_RD(11 downto 0), + comp0 => comp0 + ); +c1: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_compare_5 + port map ( + D(11 downto 0) => D(11 downto 0), + WR_PNTR_RD(11 downto 0) => WR_PNTR_RD(11 downto 0), + comp1 => comp1 + ); +ram_empty_fb_i_reg: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => rd_clk, + CE => '1', + D => ram_empty_i0_n_0, + PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), + Q => ram_empty_fb_i + ); +ram_empty_i0: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAEFFFAAAAAAAA" + ) + port map ( + I0 => comp0, + I1 => rd_en, + I2 => \gpregsm1.curr_fwft_state_reg[1]\(0), + I3 => \gpregsm1.curr_fwft_state_reg[1]\(1), + I4 => ram_empty_fb_i, + I5 => comp1, + O => ram_empty_i0_n_0 + ); +ram_empty_i_reg: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => rd_clk, + CE => '1', + D => ram_empty_i0_n_0, + PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0), + Q => ram_empty_i + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_reset_blk_ramfifo is + port ( + \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gc0.count_reg[0]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC; + wr_rst_busy : out STD_LOGIC; + rd_clk : in STD_LOGIC; + wr_clk : in STD_LOGIC; + rst : in STD_LOGIC + ); +end Arty_Z7_20_v_vid_in_axi4s_0_0_reset_blk_ramfifo; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_reset_blk_ramfifo is + signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\ : STD_LOGIC; + signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\ : STD_LOGIC; + signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\ : STD_LOGIC; + signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\ : STD_LOGIC; + signal p_7_out : STD_LOGIC; + signal p_8_out : STD_LOGIC; + signal rd_rst_asreg : STD_LOGIC; + signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true; + signal rst_d1 : STD_LOGIC; + attribute async_reg : string; + attribute async_reg of rst_d1 : signal is "true"; + attribute msgon : string; + attribute msgon of rst_d1 : signal is "true"; + signal rst_d2 : STD_LOGIC; + attribute async_reg of rst_d2 : signal is "true"; + attribute msgon of rst_d2 : signal is "true"; + signal rst_d3 : STD_LOGIC; + attribute async_reg of rst_d3 : signal is "true"; + attribute msgon of rst_d3 : signal is "true"; + signal rst_rd_reg1 : STD_LOGIC; + attribute async_reg of rst_rd_reg1 : signal is "true"; + attribute msgon of rst_rd_reg1 : signal is "true"; + signal rst_rd_reg2 : STD_LOGIC; + attribute async_reg of rst_rd_reg2 : signal is "true"; + attribute msgon of rst_rd_reg2 : signal is "true"; + signal rst_wr_reg1 : STD_LOGIC; + attribute async_reg of rst_wr_reg1 : signal is "true"; + attribute msgon of rst_wr_reg1 : signal is "true"; + signal rst_wr_reg2 : STD_LOGIC; + attribute async_reg of rst_wr_reg2 : signal is "true"; + attribute msgon of rst_wr_reg2 : signal is "true"; + signal wr_rst_asreg : STD_LOGIC; + signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes"; + attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true"; + attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true; + attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes"; + attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true"; + attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true; + attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes"; + attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true"; + attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no"; + attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes"; + attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no"; + attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes"; + attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no"; + attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes"; + attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true"; + attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes"; + attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true"; + attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes"; + attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true"; + attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes"; + attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true"; + attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes"; + attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no"; + attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes"; + attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no"; + attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true; + attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes"; + attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no"; +begin + \gc0.count_reg[0]\(2 downto 0) <= rd_rst_reg(2 downto 0); + \grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2; + \out\(1 downto 0) <= wr_rst_reg(1 downto 0); + wr_rst_busy <= rst_d3; +\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => wr_clk, + CE => '1', + D => '0', + PRE => rst_wr_reg2, + Q => rst_d1 + ); +\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => wr_clk, + CE => '1', + D => rst_d1, + PRE => rst_wr_reg2, + Q => rst_d2 + ); +\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => wr_clk, + CE => '1', + D => rst_d2, + PRE => rst_wr_reg2, + Q => rst_d3 + ); +\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff + port map ( + in0(0) => rd_rst_asreg, + \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\, + \out\ => p_7_out, + rd_clk => rd_clk + ); +\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff_0 + port map ( + in0(0) => wr_rst_asreg, + \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\, + \out\ => p_8_out, + wr_clk => wr_clk + ); +\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff_1 + port map ( + AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\, + in0(0) => rd_rst_asreg, + \out\ => p_7_out, + rd_clk => rd_clk + ); +\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_synchronizer_ff_2 + port map ( + AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\, + in0(0) => wr_rst_asreg, + \out\ => p_8_out, + wr_clk => wr_clk + ); +\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => rd_clk, + CE => '1', + D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\, + PRE => rst_rd_reg2, + Q => rd_rst_asreg + ); +\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => rd_clk, + CE => '1', + D => '0', + PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\, + Q => rd_rst_reg(0) + ); +\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => rd_clk, + CE => '1', + D => '0', + PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\, + Q => rd_rst_reg(1) + ); +\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => rd_clk, + CE => '1', + D => '0', + PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\, + Q => rd_rst_reg(2) + ); +\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + D => '0', + PRE => rst, + Q => rst_rd_reg1 + ); +\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '0' + ) + port map ( + C => rd_clk, + CE => '1', + D => rst_rd_reg1, + PRE => rst, + Q => rst_rd_reg2 + ); +\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + D => '0', + PRE => rst, + Q => rst_wr_reg1 + ); +\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '0' + ) + port map ( + C => wr_clk, + CE => '1', + D => rst_wr_reg1, + PRE => rst, + Q => rst_wr_reg2 + ); +\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => wr_clk, + CE => '1', + D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\, + PRE => rst_wr_reg2, + Q => wr_rst_asreg + ); +\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => wr_clk, + CE => '1', + D => '0', + PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\, + Q => wr_rst_reg(0) + ); +\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => wr_clk, + CE => '1', + D => '0', + PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\, + Q => wr_rst_reg(1) + ); +\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => wr_clk, + CE => '1', + D => '0', + PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\, + Q => wr_rst_reg(2) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_wr_status_flags_as is + port ( + \out\ : out STD_LOGIC; + \gic0.gc0.count_d1_reg[11]\ : out STD_LOGIC; + wr_clk : in STD_LOGIC; + \grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC; + wr_rst_busy : in STD_LOGIC; + wr_en : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 11 downto 0 ); + RD_PNTR_WR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + D : in STD_LOGIC_VECTOR ( 11 downto 0 ) + ); +end Arty_Z7_20_v_vid_in_axi4s_0_0_wr_status_flags_as; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_wr_status_flags_as is + signal \/i__n_0\ : STD_LOGIC; + signal comp1 : STD_LOGIC; + signal comp2 : STD_LOGIC; + signal ram_full_fb_i : STD_LOGIC; + attribute DONT_TOUCH : boolean; + attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true; + signal ram_full_i : STD_LOGIC; + attribute DONT_TOUCH of ram_full_i : signal is std.standard.true; + attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of ram_full_fb_i_reg : label is "yes"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no"; + attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true; + attribute KEEP of ram_full_i_reg : label is "yes"; + attribute equivalent_register_removal of ram_full_i_reg : label is "no"; +begin + \out\ <= ram_full_fb_i; +\/i_\: unisim.vcomponents.LUT5 + generic map( + INIT => X"55550400" + ) + port map ( + I0 => wr_rst_busy, + I1 => comp2, + I2 => ram_full_fb_i, + I3 => wr_en, + I4 => comp1, + O => \/i__n_0\ + ); +\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => wr_en, + I1 => ram_full_fb_i, + O => \gic0.gc0.count_d1_reg[11]\ + ); +c1: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_compare + port map ( + Q(11 downto 0) => Q(11 downto 0), + RD_PNTR_WR(11 downto 0) => RD_PNTR_WR(11 downto 0), + comp1 => comp1 + ); +c2: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_compare_3 + port map ( + D(11 downto 0) => D(11 downto 0), + RD_PNTR_WR(11 downto 0) => RD_PNTR_WR(11 downto 0), + comp2 => comp2 + ); +ram_full_fb_i_reg: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => wr_clk, + CE => '1', + D => \/i__n_0\, + PRE => \grstd1.grst_full.grst_f.rst_d2_reg\, + Q => ram_full_fb_i + ); +ram_full_i_reg: unisim.vcomponents.FDPE + generic map( + INIT => '1' + ) + port map ( + C => wr_clk, + CE => '1', + D => \/i__n_0\, + PRE => \grstd1.grst_full.grst_f.rst_d2_reg\, + Q => ram_full_i + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_generic_cstr is + port ( + dout : out STD_LOGIC_VECTOR ( 26 downto 0 ); + wr_clk : in STD_LOGIC; + rd_clk : in STD_LOGIC; + ram_full_fb_i_reg : in STD_LOGIC; + tmp_ram_rd_en : in STD_LOGIC; + tmp_ram_regout_en : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); + din : in STD_LOGIC_VECTOR ( 26 downto 0 ) + ); +end Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_generic_cstr; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_generic_cstr is +begin +\ramloop[0].ram.r\: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_width + port map ( + Q(11 downto 0) => Q(11 downto 0), + din(8 downto 0) => din(8 downto 0), + dout(8 downto 0) => dout(8 downto 0), + \gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0), + \out\(0) => \out\(0), + ram_full_fb_i_reg => ram_full_fb_i_reg, + rd_clk => rd_clk, + tmp_ram_rd_en => tmp_ram_rd_en, + tmp_ram_regout_en => tmp_ram_regout_en, + wr_clk => wr_clk + ); +\ramloop[1].ram.r\: entity work.\Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_width__parameterized0\ + port map ( + Q(11 downto 0) => Q(11 downto 0), + din(8 downto 0) => din(17 downto 9), + dout(8 downto 0) => dout(17 downto 9), + \gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0), + \out\(0) => \out\(0), + ram_full_fb_i_reg => ram_full_fb_i_reg, + rd_clk => rd_clk, + tmp_ram_rd_en => tmp_ram_rd_en, + tmp_ram_regout_en => tmp_ram_regout_en, + wr_clk => wr_clk + ); +\ramloop[2].ram.r\: entity work.\Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_prim_width__parameterized1\ + port map ( + Q(11 downto 0) => Q(11 downto 0), + din(8 downto 0) => din(26 downto 18), + dout(8 downto 0) => dout(26 downto 18), + \gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0), + \out\(0) => \out\(0), + ram_full_fb_i_reg => ram_full_fb_i_reg, + rd_clk => rd_clk, + tmp_ram_rd_en => tmp_ram_rd_en, + tmp_ram_regout_en => tmp_ram_regout_en, + wr_clk => wr_clk + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_rd_logic is + port ( + empty : out STD_LOGIC; + valid : out STD_LOGIC; + underflow : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 11 downto 0 ); + I4 : out STD_LOGIC_VECTOR ( 10 downto 0 ); + tmp_ram_regout_en : out STD_LOGIC; + tmp_ram_rd_en : out STD_LOGIC; + rd_clk : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + WR_PNTR_RD : in STD_LOGIC_VECTOR ( 11 downto 0 ); + rd_en : in STD_LOGIC + ); +end Arty_Z7_20_v_vid_in_axi4s_0_0_rd_logic; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_rd_logic is + signal \^q\ : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal p_0_in : STD_LOGIC_VECTOR ( 0 to 0 ); + signal p_1_out : STD_LOGIC; + signal p_2_out : STD_LOGIC; + signal p_3_out : STD_LOGIC; + signal p_7_out : STD_LOGIC; + signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 11 downto 0 ); +begin + Q(11 downto 0) <= \^q\(11 downto 0); +\gr1.gr1_int.rfwft\: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_rd_fwft + port map ( + empty => empty, + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(1 downto 0) => \out\(1 downto 0), + \out\(1) => p_3_out, + \out\(0) => p_0_in(0), + p_1_out => p_1_out, + p_7_out => p_7_out, + ram_empty_fb_i_reg => p_2_out, + rd_clk => rd_clk, + rd_en => rd_en, + tmp_ram_rd_en => tmp_ram_rd_en, + tmp_ram_regout_en => tmp_ram_regout_en, + valid => valid + ); +\gras.rsts\: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_rd_status_flags_as + port map ( + D(11 downto 0) => rd_pntr_plus1(11 downto 0), + Q(11 downto 0) => \^q\(11 downto 0), + WR_PNTR_RD(11 downto 0) => WR_PNTR_RD(11 downto 0), + \gpregsm1.curr_fwft_state_reg[1]\(1) => p_3_out, + \gpregsm1.curr_fwft_state_reg[1]\(0) => p_0_in(0), + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1), + \out\ => p_2_out, + rd_clk => rd_clk, + rd_en => rd_en + ); +\grhf.rhf\: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_rd_handshaking_flags + port map ( + p_1_out => p_1_out, + rd_clk => rd_clk, + underflow => underflow + ); +rpntr: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_rd_bin_cntr + port map ( + D(11 downto 0) => rd_pntr_plus1(11 downto 0), + I4(10 downto 0) => I4(10 downto 0), + Q(11 downto 0) => \^q\(11 downto 0), + \out\(0) => \out\(1), + p_7_out => p_7_out, + rd_clk => rd_clk + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_wr_logic is + port ( + overflow : out STD_LOGIC; + \gic0.gc0.count_d1_reg[11]\ : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 11 downto 0 ); + bin2gray : out STD_LOGIC_VECTOR ( 10 downto 0 ); + wr_clk : in STD_LOGIC; + \out\ : in STD_LOGIC; + wr_en : in STD_LOGIC; + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + RD_PNTR_WR : in STD_LOGIC_VECTOR ( 11 downto 0 ); + wr_rst_busy : in STD_LOGIC + ); +end Arty_Z7_20_v_vid_in_axi4s_0_0_wr_logic; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_wr_logic is + signal \^gic0.gc0.count_d1_reg[11]\ : STD_LOGIC; + signal \gwas.wsts_n_0\ : STD_LOGIC; + signal p_13_out : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 11 downto 0 ); +begin + \gic0.gc0.count_d1_reg[11]\ <= \^gic0.gc0.count_d1_reg[11]\; +\gwas.wsts\: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_wr_status_flags_as + port map ( + D(11 downto 0) => wr_pntr_plus2(11 downto 0), + Q(11 downto 0) => p_13_out(11 downto 0), + RD_PNTR_WR(11 downto 0) => RD_PNTR_WR(11 downto 0), + \gic0.gc0.count_d1_reg[11]\ => \^gic0.gc0.count_d1_reg[11]\, + \grstd1.grst_full.grst_f.rst_d2_reg\ => \out\, + \out\ => \gwas.wsts_n_0\, + wr_clk => wr_clk, + wr_en => wr_en, + wr_rst_busy => wr_rst_busy + ); +\gwhf.whf\: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_wr_handshaking_flags + port map ( + \out\ => \gwas.wsts_n_0\, + overflow => overflow, + wr_clk => wr_clk, + wr_en => wr_en, + wr_rst_busy => wr_rst_busy + ); +wpntr: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_wr_bin_cntr + port map ( + D(11 downto 0) => wr_pntr_plus2(11 downto 0), + \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(11 downto 0) => Q(11 downto 0), + Q(11 downto 0) => p_13_out(11 downto 0), + bin2gray(10 downto 0) => bin2gray(10 downto 0), + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0), + ram_full_fb_i_reg => \^gic0.gc0.count_d1_reg[11]\, + wr_clk => wr_clk + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_top is + port ( + dout : out STD_LOGIC_VECTOR ( 26 downto 0 ); + wr_clk : in STD_LOGIC; + rd_clk : in STD_LOGIC; + ram_full_fb_i_reg : in STD_LOGIC; + tmp_ram_rd_en : in STD_LOGIC; + tmp_ram_regout_en : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); + din : in STD_LOGIC_VECTOR ( 26 downto 0 ) + ); +end Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_top; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_top is +begin +\valid.cstr\: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_generic_cstr + port map ( + Q(11 downto 0) => Q(11 downto 0), + din(26 downto 0) => din(26 downto 0), + dout(26 downto 0) => dout(26 downto 0), + \gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0), + \out\(0) => \out\(0), + ram_full_fb_i_reg => ram_full_fb_i_reg, + rd_clk => rd_clk, + tmp_ram_rd_en => tmp_ram_rd_en, + tmp_ram_regout_en => tmp_ram_regout_en, + wr_clk => wr_clk + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_v8_3_5_synth is + port ( + dout : out STD_LOGIC_VECTOR ( 26 downto 0 ); + wr_clk : in STD_LOGIC; + rd_clk : in STD_LOGIC; + ram_full_fb_i_reg : in STD_LOGIC; + tmp_ram_rd_en : in STD_LOGIC; + tmp_ram_regout_en : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); + din : in STD_LOGIC_VECTOR ( 26 downto 0 ) + ); +end Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_v8_3_5_synth; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_v8_3_5_synth is +begin +\gnbram.gnativebmg.native_blk_mem_gen\: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_top + port map ( + Q(11 downto 0) => Q(11 downto 0), + din(26 downto 0) => din(26 downto 0), + dout(26 downto 0) => dout(26 downto 0), + \gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0), + \out\(0) => \out\(0), + ram_full_fb_i_reg => ram_full_fb_i_reg, + rd_clk => rd_clk, + tmp_ram_rd_en => tmp_ram_rd_en, + tmp_ram_regout_en => tmp_ram_regout_en, + wr_clk => wr_clk + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_v8_3_5 is + port ( + dout : out STD_LOGIC_VECTOR ( 26 downto 0 ); + wr_clk : in STD_LOGIC; + rd_clk : in STD_LOGIC; + ram_full_fb_i_reg : in STD_LOGIC; + tmp_ram_rd_en : in STD_LOGIC; + tmp_ram_regout_en : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); + din : in STD_LOGIC_VECTOR ( 26 downto 0 ) + ); +end Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_v8_3_5; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_v8_3_5 is +begin +inst_blk_mem_gen: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_v8_3_5_synth + port map ( + Q(11 downto 0) => Q(11 downto 0), + din(26 downto 0) => din(26 downto 0), + dout(26 downto 0) => dout(26 downto 0), + \gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0), + \out\(0) => \out\(0), + ram_full_fb_i_reg => ram_full_fb_i_reg, + rd_clk => rd_clk, + tmp_ram_rd_en => tmp_ram_rd_en, + tmp_ram_regout_en => tmp_ram_regout_en, + wr_clk => wr_clk + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_memory is + port ( + dout : out STD_LOGIC_VECTOR ( 26 downto 0 ); + wr_clk : in STD_LOGIC; + rd_clk : in STD_LOGIC; + ram_full_fb_i_reg : in STD_LOGIC; + tmp_ram_rd_en : in STD_LOGIC; + tmp_ram_regout_en : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); + din : in STD_LOGIC_VECTOR ( 26 downto 0 ) + ); +end Arty_Z7_20_v_vid_in_axi4s_0_0_memory; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_memory is +begin +\gbm.gbmg.gbmgb.ngecc.bmg\: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_blk_mem_gen_v8_3_5 + port map ( + Q(11 downto 0) => Q(11 downto 0), + din(26 downto 0) => din(26 downto 0), + dout(26 downto 0) => dout(26 downto 0), + \gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0), + \out\(0) => \out\(0), + ram_full_fb_i_reg => ram_full_fb_i_reg, + rd_clk => rd_clk, + tmp_ram_rd_en => tmp_ram_rd_en, + tmp_ram_regout_en => tmp_ram_regout_en, + wr_clk => wr_clk + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_ramfifo is + port ( + wr_rst_busy : out STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 26 downto 0 ); + empty : out STD_LOGIC; + valid : out STD_LOGIC; + underflow : out STD_LOGIC; + overflow : out STD_LOGIC; + wr_en : in STD_LOGIC; + wr_clk : in STD_LOGIC; + rd_clk : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 26 downto 0 ); + rst : in STD_LOGIC; + rd_en : in STD_LOGIC + ); +end Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_ramfifo; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_ramfifo is + signal bin2gray : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal \gntv_or_sync_fifo.gl0.rd_n_15\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd_n_16\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd_n_17\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd_n_18\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd_n_19\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd_n_20\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd_n_21\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd_n_22\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd_n_23\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd_n_24\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.rd_n_25\ : STD_LOGIC; + signal \gntv_or_sync_fifo.gl0.wr_n_1\ : STD_LOGIC; + signal p_0_out : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal p_12_out : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal p_22_out : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal p_23_out : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal rst_full_ff_i : STD_LOGIC; + signal tmp_ram_rd_en : STD_LOGIC; + signal tmp_ram_regout_en : STD_LOGIC; + signal \^wr_rst_busy\ : STD_LOGIC; + signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 ); +begin + wr_rst_busy <= \^wr_rst_busy\; +\gntv_or_sync_fifo.gcx.clkx\: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_clk_x_pntrs + port map ( + AR(0) => wr_rst_i(0), + I4(11) => p_0_out(11), + I4(10) => \gntv_or_sync_fifo.gl0.rd_n_15\, + I4(9) => \gntv_or_sync_fifo.gl0.rd_n_16\, + I4(8) => \gntv_or_sync_fifo.gl0.rd_n_17\, + I4(7) => \gntv_or_sync_fifo.gl0.rd_n_18\, + I4(6) => \gntv_or_sync_fifo.gl0.rd_n_19\, + I4(5) => \gntv_or_sync_fifo.gl0.rd_n_20\, + I4(4) => \gntv_or_sync_fifo.gl0.rd_n_21\, + I4(3) => \gntv_or_sync_fifo.gl0.rd_n_22\, + I4(2) => \gntv_or_sync_fifo.gl0.rd_n_23\, + I4(1) => \gntv_or_sync_fifo.gl0.rd_n_24\, + I4(0) => \gntv_or_sync_fifo.gl0.rd_n_25\, + RD_PNTR_WR(11 downto 0) => p_23_out(11 downto 0), + WR_PNTR_RD(11 downto 0) => p_22_out(11 downto 0), + bin2gray(11) => p_12_out(11), + bin2gray(10 downto 0) => bin2gray(10 downto 0), + \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1), + rd_clk => rd_clk, + wr_clk => wr_clk + ); +\gntv_or_sync_fifo.gl0.rd\: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_rd_logic + port map ( + I4(10) => \gntv_or_sync_fifo.gl0.rd_n_15\, + I4(9) => \gntv_or_sync_fifo.gl0.rd_n_16\, + I4(8) => \gntv_or_sync_fifo.gl0.rd_n_17\, + I4(7) => \gntv_or_sync_fifo.gl0.rd_n_18\, + I4(6) => \gntv_or_sync_fifo.gl0.rd_n_19\, + I4(5) => \gntv_or_sync_fifo.gl0.rd_n_20\, + I4(4) => \gntv_or_sync_fifo.gl0.rd_n_21\, + I4(3) => \gntv_or_sync_fifo.gl0.rd_n_22\, + I4(2) => \gntv_or_sync_fifo.gl0.rd_n_23\, + I4(1) => \gntv_or_sync_fifo.gl0.rd_n_24\, + I4(0) => \gntv_or_sync_fifo.gl0.rd_n_25\, + Q(11 downto 0) => p_0_out(11 downto 0), + WR_PNTR_RD(11 downto 0) => p_22_out(11 downto 0), + empty => empty, + \out\(1) => rd_rst_i(2), + \out\(0) => rd_rst_i(0), + rd_clk => rd_clk, + rd_en => rd_en, + tmp_ram_rd_en => tmp_ram_rd_en, + tmp_ram_regout_en => tmp_ram_regout_en, + underflow => underflow, + valid => valid + ); +\gntv_or_sync_fifo.gl0.wr\: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_wr_logic + port map ( + Q(11 downto 0) => p_12_out(11 downto 0), + RD_PNTR_WR(11 downto 0) => p_23_out(11 downto 0), + bin2gray(10 downto 0) => bin2gray(10 downto 0), + \gic0.gc0.count_d1_reg[11]\ => \gntv_or_sync_fifo.gl0.wr_n_1\, + \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => wr_rst_i(1), + \out\ => rst_full_ff_i, + overflow => overflow, + wr_clk => wr_clk, + wr_en => wr_en, + wr_rst_busy => \^wr_rst_busy\ + ); +\gntv_or_sync_fifo.mem\: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_memory + port map ( + Q(11 downto 0) => p_12_out(11 downto 0), + din(26 downto 0) => din(26 downto 0), + dout(26 downto 0) => dout(26 downto 0), + \gc0.count_d1_reg[11]\(11 downto 0) => p_0_out(11 downto 0), + \out\(0) => rd_rst_i(0), + ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_1\, + rd_clk => rd_clk, + tmp_ram_rd_en => tmp_ram_rd_en, + tmp_ram_regout_en => tmp_ram_regout_en, + wr_clk => wr_clk + ); +rstblk: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_reset_blk_ramfifo + port map ( + \gc0.count_reg[0]\(2 downto 0) => rd_rst_i(2 downto 0), + \grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i, + \out\(1 downto 0) => wr_rst_i(1 downto 0), + rd_clk => rd_clk, + rst => rst, + wr_clk => wr_clk, + wr_rst_busy => \^wr_rst_busy\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_top is + port ( + wr_rst_busy : out STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 26 downto 0 ); + empty : out STD_LOGIC; + valid : out STD_LOGIC; + underflow : out STD_LOGIC; + overflow : out STD_LOGIC; + wr_en : in STD_LOGIC; + wr_clk : in STD_LOGIC; + rd_clk : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 26 downto 0 ); + rst : in STD_LOGIC; + rd_en : in STD_LOGIC + ); +end Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_top; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_top is +begin +\grf.rf\: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_ramfifo + port map ( + din(26 downto 0) => din(26 downto 0), + dout(26 downto 0) => dout(26 downto 0), + empty => empty, + overflow => overflow, + rd_clk => rd_clk, + rd_en => rd_en, + rst => rst, + underflow => underflow, + valid => valid, + wr_clk => wr_clk, + wr_en => wr_en, + wr_rst_busy => wr_rst_busy + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3_synth is + port ( + wr_rst_busy : out STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 26 downto 0 ); + empty : out STD_LOGIC; + valid : out STD_LOGIC; + underflow : out STD_LOGIC; + overflow : out STD_LOGIC; + wr_en : in STD_LOGIC; + wr_clk : in STD_LOGIC; + rd_clk : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 26 downto 0 ); + rst : in STD_LOGIC; + rd_en : in STD_LOGIC + ); +end Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3_synth; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3_synth is +begin +\gconvfifo.rf\: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_top + port map ( + din(26 downto 0) => din(26 downto 0), + dout(26 downto 0) => dout(26 downto 0), + empty => empty, + overflow => overflow, + rd_clk => rd_clk, + rd_en => rd_en, + rst => rst, + underflow => underflow, + valid => valid, + wr_clk => wr_clk, + wr_en => wr_en, + wr_rst_busy => wr_rst_busy + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 is + port ( + backup : in STD_LOGIC; + backup_marker : in STD_LOGIC; + clk : in STD_LOGIC; + rst : in STD_LOGIC; + srst : in STD_LOGIC; + wr_clk : in STD_LOGIC; + wr_rst : in STD_LOGIC; + rd_clk : in STD_LOGIC; + rd_rst : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 26 downto 0 ); + wr_en : in STD_LOGIC; + rd_en : in STD_LOGIC; + prog_empty_thresh : in STD_LOGIC_VECTOR ( 11 downto 0 ); + prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 11 downto 0 ); + prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 11 downto 0 ); + prog_full_thresh : in STD_LOGIC_VECTOR ( 11 downto 0 ); + prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 11 downto 0 ); + prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 11 downto 0 ); + int_clk : in STD_LOGIC; + injectdbiterr : in STD_LOGIC; + injectsbiterr : in STD_LOGIC; + sleep : in STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 26 downto 0 ); + full : out STD_LOGIC; + almost_full : out STD_LOGIC; + wr_ack : out STD_LOGIC; + overflow : out STD_LOGIC; + empty : out STD_LOGIC; + almost_empty : out STD_LOGIC; + valid : out STD_LOGIC; + underflow : out STD_LOGIC; + data_count : out STD_LOGIC_VECTOR ( 12 downto 0 ); + rd_data_count : out STD_LOGIC_VECTOR ( 12 downto 0 ); + wr_data_count : out STD_LOGIC_VECTOR ( 12 downto 0 ); + prog_full : out STD_LOGIC; + prog_empty : out STD_LOGIC; + sbiterr : out STD_LOGIC; + dbiterr : out STD_LOGIC; + wr_rst_busy : out STD_LOGIC; + rd_rst_busy : out STD_LOGIC; + m_aclk : in STD_LOGIC; + s_aclk : in STD_LOGIC; + s_aresetn : in STD_LOGIC; + m_aclk_en : in STD_LOGIC; + s_aclk_en : in STD_LOGIC; + s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_wlast : in STD_LOGIC; + s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awvalid : out STD_LOGIC; + m_axi_awready : in STD_LOGIC; + m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_wlast : out STD_LOGIC; + m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_wvalid : out STD_LOGIC; + m_axi_wready : in STD_LOGIC; + m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_bvalid : in STD_LOGIC; + m_axi_bready : out STD_LOGIC; + s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_arvalid : in STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rlast : out STD_LOGIC; + s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rvalid : out STD_LOGIC; + s_axi_rready : in STD_LOGIC; + m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_arvalid : out STD_LOGIC; + m_axi_arready : in STD_LOGIC; + m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_rlast : in STD_LOGIC; + m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rvalid : in STD_LOGIC; + m_axi_rready : out STD_LOGIC; + s_axis_tvalid : in STD_LOGIC; + s_axis_tready : out STD_LOGIC; + s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axis_tlast : in STD_LOGIC; + s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axis_tvalid : out STD_LOGIC; + m_axis_tready : in STD_LOGIC; + m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axis_tlast : out STD_LOGIC; + m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 ); + axi_aw_injectsbiterr : in STD_LOGIC; + axi_aw_injectdbiterr : in STD_LOGIC; + axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); + axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); + axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); + axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); + axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); + axi_aw_sbiterr : out STD_LOGIC; + axi_aw_dbiterr : out STD_LOGIC; + axi_aw_overflow : out STD_LOGIC; + axi_aw_underflow : out STD_LOGIC; + axi_aw_prog_full : out STD_LOGIC; + axi_aw_prog_empty : out STD_LOGIC; + axi_w_injectsbiterr : in STD_LOGIC; + axi_w_injectdbiterr : in STD_LOGIC; + axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 11 downto 0 ); + axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 11 downto 0 ); + axi_w_data_count : out STD_LOGIC_VECTOR ( 12 downto 0 ); + axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 12 downto 0 ); + axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 12 downto 0 ); + axi_w_sbiterr : out STD_LOGIC; + axi_w_dbiterr : out STD_LOGIC; + axi_w_overflow : out STD_LOGIC; + axi_w_underflow : out STD_LOGIC; + axi_w_prog_full : out STD_LOGIC; + axi_w_prog_empty : out STD_LOGIC; + axi_b_injectsbiterr : in STD_LOGIC; + axi_b_injectdbiterr : in STD_LOGIC; + axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); + axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); + axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); + axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); + axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); + axi_b_sbiterr : out STD_LOGIC; + axi_b_dbiterr : out STD_LOGIC; + axi_b_overflow : out STD_LOGIC; + axi_b_underflow : out STD_LOGIC; + axi_b_prog_full : out STD_LOGIC; + axi_b_prog_empty : out STD_LOGIC; + axi_ar_injectsbiterr : in STD_LOGIC; + axi_ar_injectdbiterr : in STD_LOGIC; + axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); + axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 ); + axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); + axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); + axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ); + axi_ar_sbiterr : out STD_LOGIC; + axi_ar_dbiterr : out STD_LOGIC; + axi_ar_overflow : out STD_LOGIC; + axi_ar_underflow : out STD_LOGIC; + axi_ar_prog_full : out STD_LOGIC; + axi_ar_prog_empty : out STD_LOGIC; + axi_r_injectsbiterr : in STD_LOGIC; + axi_r_injectdbiterr : in STD_LOGIC; + axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 11 downto 0 ); + axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 11 downto 0 ); + axi_r_data_count : out STD_LOGIC_VECTOR ( 12 downto 0 ); + axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 12 downto 0 ); + axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 12 downto 0 ); + axi_r_sbiterr : out STD_LOGIC; + axi_r_dbiterr : out STD_LOGIC; + axi_r_overflow : out STD_LOGIC; + axi_r_underflow : out STD_LOGIC; + axi_r_prog_full : out STD_LOGIC; + axi_r_prog_empty : out STD_LOGIC; + axis_injectsbiterr : in STD_LOGIC; + axis_injectdbiterr : in STD_LOGIC; + axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 11 downto 0 ); + axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 11 downto 0 ); + axis_data_count : out STD_LOGIC_VECTOR ( 12 downto 0 ); + axis_wr_data_count : out STD_LOGIC_VECTOR ( 12 downto 0 ); + axis_rd_data_count : out STD_LOGIC_VECTOR ( 12 downto 0 ); + axis_sbiterr : out STD_LOGIC; + axis_dbiterr : out STD_LOGIC; + axis_overflow : out STD_LOGIC; + axis_underflow : out STD_LOGIC; + axis_prog_full : out STD_LOGIC; + axis_prog_empty : out STD_LOGIC + ); + attribute C_ADD_NGC_CONSTRAINT : integer; + attribute C_ADD_NGC_CONSTRAINT of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_APPLICATION_TYPE_AXIS : integer; + attribute C_APPLICATION_TYPE_AXIS of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_APPLICATION_TYPE_RACH : integer; + attribute C_APPLICATION_TYPE_RACH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_APPLICATION_TYPE_RDCH : integer; + attribute C_APPLICATION_TYPE_RDCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_APPLICATION_TYPE_WACH : integer; + attribute C_APPLICATION_TYPE_WACH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_APPLICATION_TYPE_WDCH : integer; + attribute C_APPLICATION_TYPE_WDCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_APPLICATION_TYPE_WRCH : integer; + attribute C_APPLICATION_TYPE_WRCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_AXIS_TDATA_WIDTH : integer; + attribute C_AXIS_TDATA_WIDTH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 8; + attribute C_AXIS_TDEST_WIDTH : integer; + attribute C_AXIS_TDEST_WIDTH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_AXIS_TID_WIDTH : integer; + attribute C_AXIS_TID_WIDTH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_AXIS_TKEEP_WIDTH : integer; + attribute C_AXIS_TKEEP_WIDTH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_AXIS_TSTRB_WIDTH : integer; + attribute C_AXIS_TSTRB_WIDTH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_AXIS_TUSER_WIDTH : integer; + attribute C_AXIS_TUSER_WIDTH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 4; + attribute C_AXIS_TYPE : integer; + attribute C_AXIS_TYPE of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_AXI_ADDR_WIDTH : integer; + attribute C_AXI_ADDR_WIDTH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 32; + attribute C_AXI_ARUSER_WIDTH : integer; + attribute C_AXI_ARUSER_WIDTH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_AXI_AWUSER_WIDTH : integer; + attribute C_AXI_AWUSER_WIDTH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_AXI_BUSER_WIDTH : integer; + attribute C_AXI_BUSER_WIDTH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_AXI_DATA_WIDTH : integer; + attribute C_AXI_DATA_WIDTH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 64; + attribute C_AXI_ID_WIDTH : integer; + attribute C_AXI_ID_WIDTH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_AXI_LEN_WIDTH : integer; + attribute C_AXI_LEN_WIDTH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 8; + attribute C_AXI_LOCK_WIDTH : integer; + attribute C_AXI_LOCK_WIDTH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_AXI_RUSER_WIDTH : integer; + attribute C_AXI_RUSER_WIDTH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_AXI_TYPE : integer; + attribute C_AXI_TYPE of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_AXI_WUSER_WIDTH : integer; + attribute C_AXI_WUSER_WIDTH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_COMMON_CLOCK : integer; + attribute C_COMMON_CLOCK of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_COUNT_TYPE : integer; + attribute C_COUNT_TYPE of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_DATA_COUNT_WIDTH : integer; + attribute C_DATA_COUNT_WIDTH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 13; + attribute C_DEFAULT_VALUE : string; + attribute C_DEFAULT_VALUE of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is "BlankString"; + attribute C_DIN_WIDTH : integer; + attribute C_DIN_WIDTH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 27; + attribute C_DIN_WIDTH_AXIS : integer; + attribute C_DIN_WIDTH_AXIS of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_DIN_WIDTH_RACH : integer; + attribute C_DIN_WIDTH_RACH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 32; + attribute C_DIN_WIDTH_RDCH : integer; + attribute C_DIN_WIDTH_RDCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 64; + attribute C_DIN_WIDTH_WACH : integer; + attribute C_DIN_WIDTH_WACH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 32; + attribute C_DIN_WIDTH_WDCH : integer; + attribute C_DIN_WIDTH_WDCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 64; + attribute C_DIN_WIDTH_WRCH : integer; + attribute C_DIN_WIDTH_WRCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 2; + attribute C_DOUT_RST_VAL : string; + attribute C_DOUT_RST_VAL of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is "0"; + attribute C_DOUT_WIDTH : integer; + attribute C_DOUT_WIDTH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 27; + attribute C_ENABLE_RLOCS : integer; + attribute C_ENABLE_RLOCS of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_ENABLE_RST_SYNC : integer; + attribute C_ENABLE_RST_SYNC of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_EN_SAFETY_CKT : integer; + attribute C_EN_SAFETY_CKT of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_ERROR_INJECTION_TYPE : integer; + attribute C_ERROR_INJECTION_TYPE of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_ERROR_INJECTION_TYPE_AXIS : integer; + attribute C_ERROR_INJECTION_TYPE_AXIS of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_ERROR_INJECTION_TYPE_RACH : integer; + attribute C_ERROR_INJECTION_TYPE_RACH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_ERROR_INJECTION_TYPE_RDCH : integer; + attribute C_ERROR_INJECTION_TYPE_RDCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_ERROR_INJECTION_TYPE_WACH : integer; + attribute C_ERROR_INJECTION_TYPE_WACH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_ERROR_INJECTION_TYPE_WDCH : integer; + attribute C_ERROR_INJECTION_TYPE_WDCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_ERROR_INJECTION_TYPE_WRCH : integer; + attribute C_ERROR_INJECTION_TYPE_WRCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_FAMILY : string; + attribute C_FAMILY of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is "zynq"; + attribute C_FULL_FLAGS_RST_VAL : integer; + attribute C_FULL_FLAGS_RST_VAL of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_HAS_ALMOST_EMPTY : integer; + attribute C_HAS_ALMOST_EMPTY of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_ALMOST_FULL : integer; + attribute C_HAS_ALMOST_FULL of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXIS_TDATA : integer; + attribute C_HAS_AXIS_TDATA of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_HAS_AXIS_TDEST : integer; + attribute C_HAS_AXIS_TDEST of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXIS_TID : integer; + attribute C_HAS_AXIS_TID of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXIS_TKEEP : integer; + attribute C_HAS_AXIS_TKEEP of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXIS_TLAST : integer; + attribute C_HAS_AXIS_TLAST of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXIS_TREADY : integer; + attribute C_HAS_AXIS_TREADY of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_HAS_AXIS_TSTRB : integer; + attribute C_HAS_AXIS_TSTRB of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXIS_TUSER : integer; + attribute C_HAS_AXIS_TUSER of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_HAS_AXI_ARUSER : integer; + attribute C_HAS_AXI_ARUSER of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXI_AWUSER : integer; + attribute C_HAS_AXI_AWUSER of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXI_BUSER : integer; + attribute C_HAS_AXI_BUSER of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXI_ID : integer; + attribute C_HAS_AXI_ID of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXI_RD_CHANNEL : integer; + attribute C_HAS_AXI_RD_CHANNEL of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_HAS_AXI_RUSER : integer; + attribute C_HAS_AXI_RUSER of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_AXI_WR_CHANNEL : integer; + attribute C_HAS_AXI_WR_CHANNEL of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_HAS_AXI_WUSER : integer; + attribute C_HAS_AXI_WUSER of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_BACKUP : integer; + attribute C_HAS_BACKUP of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_DATA_COUNT : integer; + attribute C_HAS_DATA_COUNT of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_DATA_COUNTS_AXIS : integer; + attribute C_HAS_DATA_COUNTS_AXIS of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_DATA_COUNTS_RACH : integer; + attribute C_HAS_DATA_COUNTS_RACH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_DATA_COUNTS_RDCH : integer; + attribute C_HAS_DATA_COUNTS_RDCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_DATA_COUNTS_WACH : integer; + attribute C_HAS_DATA_COUNTS_WACH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_DATA_COUNTS_WDCH : integer; + attribute C_HAS_DATA_COUNTS_WDCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_DATA_COUNTS_WRCH : integer; + attribute C_HAS_DATA_COUNTS_WRCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_INT_CLK : integer; + attribute C_HAS_INT_CLK of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_MASTER_CE : integer; + attribute C_HAS_MASTER_CE of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_MEMINIT_FILE : integer; + attribute C_HAS_MEMINIT_FILE of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_OVERFLOW : integer; + attribute C_HAS_OVERFLOW of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_HAS_PROG_FLAGS_AXIS : integer; + attribute C_HAS_PROG_FLAGS_AXIS of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_PROG_FLAGS_RACH : integer; + attribute C_HAS_PROG_FLAGS_RACH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_PROG_FLAGS_RDCH : integer; + attribute C_HAS_PROG_FLAGS_RDCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_PROG_FLAGS_WACH : integer; + attribute C_HAS_PROG_FLAGS_WACH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_PROG_FLAGS_WDCH : integer; + attribute C_HAS_PROG_FLAGS_WDCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_PROG_FLAGS_WRCH : integer; + attribute C_HAS_PROG_FLAGS_WRCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_RD_DATA_COUNT : integer; + attribute C_HAS_RD_DATA_COUNT of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_HAS_RD_RST : integer; + attribute C_HAS_RD_RST of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_RST : integer; + attribute C_HAS_RST of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_HAS_SLAVE_CE : integer; + attribute C_HAS_SLAVE_CE of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_SRST : integer; + attribute C_HAS_SRST of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_UNDERFLOW : integer; + attribute C_HAS_UNDERFLOW of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_HAS_VALID : integer; + attribute C_HAS_VALID of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_HAS_WR_ACK : integer; + attribute C_HAS_WR_ACK of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_HAS_WR_DATA_COUNT : integer; + attribute C_HAS_WR_DATA_COUNT of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_HAS_WR_RST : integer; + attribute C_HAS_WR_RST of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_IMPLEMENTATION_TYPE : integer; + attribute C_IMPLEMENTATION_TYPE of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 2; + attribute C_IMPLEMENTATION_TYPE_AXIS : integer; + attribute C_IMPLEMENTATION_TYPE_AXIS of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_IMPLEMENTATION_TYPE_RACH : integer; + attribute C_IMPLEMENTATION_TYPE_RACH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_IMPLEMENTATION_TYPE_RDCH : integer; + attribute C_IMPLEMENTATION_TYPE_RDCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_IMPLEMENTATION_TYPE_WACH : integer; + attribute C_IMPLEMENTATION_TYPE_WACH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_IMPLEMENTATION_TYPE_WDCH : integer; + attribute C_IMPLEMENTATION_TYPE_WDCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_IMPLEMENTATION_TYPE_WRCH : integer; + attribute C_IMPLEMENTATION_TYPE_WRCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_INIT_WR_PNTR_VAL : integer; + attribute C_INIT_WR_PNTR_VAL of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_INTERFACE_TYPE : integer; + attribute C_INTERFACE_TYPE of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_MEMORY_TYPE : integer; + attribute C_MEMORY_TYPE of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_MIF_FILE_NAME : string; + attribute C_MIF_FILE_NAME of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is "BlankString"; + attribute C_MSGON_VAL : integer; + attribute C_MSGON_VAL of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_OPTIMIZATION_MODE : integer; + attribute C_OPTIMIZATION_MODE of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_OVERFLOW_LOW : integer; + attribute C_OVERFLOW_LOW of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_POWER_SAVING_MODE : integer; + attribute C_POWER_SAVING_MODE of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PRELOAD_LATENCY : integer; + attribute C_PRELOAD_LATENCY of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PRELOAD_REGS : integer; + attribute C_PRELOAD_REGS of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_PRIM_FIFO_TYPE : string; + attribute C_PRIM_FIFO_TYPE of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is "1kx36"; + attribute C_PRIM_FIFO_TYPE_AXIS : string; + attribute C_PRIM_FIFO_TYPE_AXIS of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is "1kx18"; + attribute C_PRIM_FIFO_TYPE_RACH : string; + attribute C_PRIM_FIFO_TYPE_RACH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is "512x36"; + attribute C_PRIM_FIFO_TYPE_RDCH : string; + attribute C_PRIM_FIFO_TYPE_RDCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is "1kx36"; + attribute C_PRIM_FIFO_TYPE_WACH : string; + attribute C_PRIM_FIFO_TYPE_WACH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is "512x36"; + attribute C_PRIM_FIFO_TYPE_WDCH : string; + attribute C_PRIM_FIFO_TYPE_WDCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is "1kx36"; + attribute C_PRIM_FIFO_TYPE_WRCH : string; + attribute C_PRIM_FIFO_TYPE_WRCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is "512x36"; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 4; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1022; + attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer; + attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 5; + attribute C_PROG_EMPTY_TYPE : integer; + attribute C_PROG_EMPTY_TYPE of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_EMPTY_TYPE_AXIS : integer; + attribute C_PROG_EMPTY_TYPE_AXIS of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_EMPTY_TYPE_RACH : integer; + attribute C_PROG_EMPTY_TYPE_RACH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_EMPTY_TYPE_RDCH : integer; + attribute C_PROG_EMPTY_TYPE_RDCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_EMPTY_TYPE_WACH : integer; + attribute C_PROG_EMPTY_TYPE_WACH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_EMPTY_TYPE_WDCH : integer; + attribute C_PROG_EMPTY_TYPE_WDCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_EMPTY_TYPE_WRCH : integer; + attribute C_PROG_EMPTY_TYPE_WRCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 4095; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1023; + attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer; + attribute C_PROG_FULL_THRESH_NEGATE_VAL of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 4094; + attribute C_PROG_FULL_TYPE : integer; + attribute C_PROG_FULL_TYPE of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_FULL_TYPE_AXIS : integer; + attribute C_PROG_FULL_TYPE_AXIS of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_FULL_TYPE_RACH : integer; + attribute C_PROG_FULL_TYPE_RACH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_FULL_TYPE_RDCH : integer; + attribute C_PROG_FULL_TYPE_RDCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_FULL_TYPE_WACH : integer; + attribute C_PROG_FULL_TYPE_WACH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_FULL_TYPE_WDCH : integer; + attribute C_PROG_FULL_TYPE_WDCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_PROG_FULL_TYPE_WRCH : integer; + attribute C_PROG_FULL_TYPE_WRCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_RACH_TYPE : integer; + attribute C_RACH_TYPE of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_RDCH_TYPE : integer; + attribute C_RDCH_TYPE of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_RD_DATA_COUNT_WIDTH : integer; + attribute C_RD_DATA_COUNT_WIDTH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 13; + attribute C_RD_DEPTH : integer; + attribute C_RD_DEPTH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 4096; + attribute C_RD_FREQ : integer; + attribute C_RD_FREQ of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_RD_PNTR_WIDTH : integer; + attribute C_RD_PNTR_WIDTH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 12; + attribute C_REG_SLICE_MODE_AXIS : integer; + attribute C_REG_SLICE_MODE_AXIS of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_REG_SLICE_MODE_RACH : integer; + attribute C_REG_SLICE_MODE_RACH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_REG_SLICE_MODE_RDCH : integer; + attribute C_REG_SLICE_MODE_RDCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_REG_SLICE_MODE_WACH : integer; + attribute C_REG_SLICE_MODE_WACH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_REG_SLICE_MODE_WDCH : integer; + attribute C_REG_SLICE_MODE_WDCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_REG_SLICE_MODE_WRCH : integer; + attribute C_REG_SLICE_MODE_WRCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_SELECT_XPM : integer; + attribute C_SELECT_XPM of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_SYNCHRONIZER_STAGE : integer; + attribute C_SYNCHRONIZER_STAGE of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 2; + attribute C_UNDERFLOW_LOW : integer; + attribute C_UNDERFLOW_LOW of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_COMMON_OVERFLOW : integer; + attribute C_USE_COMMON_OVERFLOW of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_COMMON_UNDERFLOW : integer; + attribute C_USE_COMMON_UNDERFLOW of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_DEFAULT_SETTINGS : integer; + attribute C_USE_DEFAULT_SETTINGS of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_DOUT_RST : integer; + attribute C_USE_DOUT_RST of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_USE_ECC : integer; + attribute C_USE_ECC of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_ECC_AXIS : integer; + attribute C_USE_ECC_AXIS of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_ECC_RACH : integer; + attribute C_USE_ECC_RACH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_ECC_RDCH : integer; + attribute C_USE_ECC_RDCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_ECC_WACH : integer; + attribute C_USE_ECC_WACH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_ECC_WDCH : integer; + attribute C_USE_ECC_WDCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_ECC_WRCH : integer; + attribute C_USE_ECC_WRCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_EMBEDDED_REG : integer; + attribute C_USE_EMBEDDED_REG of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_USE_FIFO16_FLAGS : integer; + attribute C_USE_FIFO16_FLAGS of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_USE_FWFT_DATA_COUNT : integer; + attribute C_USE_FWFT_DATA_COUNT of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_USE_PIPELINE_REG : integer; + attribute C_USE_PIPELINE_REG of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_VALID_LOW : integer; + attribute C_VALID_LOW of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_WACH_TYPE : integer; + attribute C_WACH_TYPE of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_WDCH_TYPE : integer; + attribute C_WDCH_TYPE of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_WRCH_TYPE : integer; + attribute C_WRCH_TYPE of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_WR_ACK_LOW : integer; + attribute C_WR_ACK_LOW of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 0; + attribute C_WR_DATA_COUNT_WIDTH : integer; + attribute C_WR_DATA_COUNT_WIDTH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 13; + attribute C_WR_DEPTH : integer; + attribute C_WR_DEPTH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 4096; + attribute C_WR_DEPTH_AXIS : integer; + attribute C_WR_DEPTH_AXIS of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1024; + attribute C_WR_DEPTH_RACH : integer; + attribute C_WR_DEPTH_RACH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 16; + attribute C_WR_DEPTH_RDCH : integer; + attribute C_WR_DEPTH_RDCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1024; + attribute C_WR_DEPTH_WACH : integer; + attribute C_WR_DEPTH_WACH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 16; + attribute C_WR_DEPTH_WDCH : integer; + attribute C_WR_DEPTH_WDCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1024; + attribute C_WR_DEPTH_WRCH : integer; + attribute C_WR_DEPTH_WRCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 16; + attribute C_WR_FREQ : integer; + attribute C_WR_FREQ of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; + attribute C_WR_PNTR_WIDTH : integer; + attribute C_WR_PNTR_WIDTH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 12; + attribute C_WR_PNTR_WIDTH_AXIS : integer; + attribute C_WR_PNTR_WIDTH_AXIS of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 12; + attribute C_WR_PNTR_WIDTH_RACH : integer; + attribute C_WR_PNTR_WIDTH_RACH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 4; + attribute C_WR_PNTR_WIDTH_RDCH : integer; + attribute C_WR_PNTR_WIDTH_RDCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 12; + attribute C_WR_PNTR_WIDTH_WACH : integer; + attribute C_WR_PNTR_WIDTH_WACH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 4; + attribute C_WR_PNTR_WIDTH_WDCH : integer; + attribute C_WR_PNTR_WIDTH_WDCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 12; + attribute C_WR_PNTR_WIDTH_WRCH : integer; + attribute C_WR_PNTR_WIDTH_WRCH of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 4; + attribute C_WR_RESPONSE_LATENCY : integer; + attribute C_WR_RESPONSE_LATENCY of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 : entity is 1; +end Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 is + signal \\ : STD_LOGIC; +begin + almost_empty <= \\; + almost_full <= \\; + axi_ar_data_count(4) <= \\; + axi_ar_data_count(3) <= \\; + axi_ar_data_count(2) <= \\; + axi_ar_data_count(1) <= \\; + axi_ar_data_count(0) <= \\; + axi_ar_dbiterr <= \\; + axi_ar_overflow <= \\; + axi_ar_prog_empty <= \\; + axi_ar_prog_full <= \\; + axi_ar_rd_data_count(4) <= \\; + axi_ar_rd_data_count(3) <= \\; + axi_ar_rd_data_count(2) <= \\; + axi_ar_rd_data_count(1) <= \\; + axi_ar_rd_data_count(0) <= \\; + axi_ar_sbiterr <= \\; + axi_ar_underflow <= \\; + axi_ar_wr_data_count(4) <= \\; + axi_ar_wr_data_count(3) <= \\; + axi_ar_wr_data_count(2) <= \\; + axi_ar_wr_data_count(1) <= \\; + axi_ar_wr_data_count(0) <= \\; + axi_aw_data_count(4) <= \\; + axi_aw_data_count(3) <= \\; + axi_aw_data_count(2) <= \\; + axi_aw_data_count(1) <= \\; + axi_aw_data_count(0) <= \\; + axi_aw_dbiterr <= \\; + axi_aw_overflow <= \\; + axi_aw_prog_empty <= \\; + axi_aw_prog_full <= \\; + axi_aw_rd_data_count(4) <= \\; + axi_aw_rd_data_count(3) <= \\; + axi_aw_rd_data_count(2) <= \\; + axi_aw_rd_data_count(1) <= \\; + axi_aw_rd_data_count(0) <= \\; + axi_aw_sbiterr <= \\; + axi_aw_underflow <= \\; + axi_aw_wr_data_count(4) <= \\; + axi_aw_wr_data_count(3) <= \\; + axi_aw_wr_data_count(2) <= \\; + axi_aw_wr_data_count(1) <= \\; + axi_aw_wr_data_count(0) <= \\; + axi_b_data_count(4) <= \\; + axi_b_data_count(3) <= \\; + axi_b_data_count(2) <= \\; + axi_b_data_count(1) <= \\; + axi_b_data_count(0) <= \\; + axi_b_dbiterr <= \\; + axi_b_overflow <= \\; + axi_b_prog_empty <= \\; + axi_b_prog_full <= \\; + axi_b_rd_data_count(4) <= \\; + axi_b_rd_data_count(3) <= \\; + axi_b_rd_data_count(2) <= \\; + axi_b_rd_data_count(1) <= \\; + axi_b_rd_data_count(0) <= \\; + axi_b_sbiterr <= \\; + axi_b_underflow <= \\; + axi_b_wr_data_count(4) <= \\; + axi_b_wr_data_count(3) <= \\; + axi_b_wr_data_count(2) <= \\; + axi_b_wr_data_count(1) <= \\; + axi_b_wr_data_count(0) <= \\; + axi_r_data_count(12) <= \\; + axi_r_data_count(11) <= \\; + axi_r_data_count(10) <= \\; + axi_r_data_count(9) <= \\; + axi_r_data_count(8) <= \\; + axi_r_data_count(7) <= \\; + axi_r_data_count(6) <= \\; + axi_r_data_count(5) <= \\; + axi_r_data_count(4) <= \\; + axi_r_data_count(3) <= \\; + axi_r_data_count(2) <= \\; + axi_r_data_count(1) <= \\; + axi_r_data_count(0) <= \\; + axi_r_dbiterr <= \\; + axi_r_overflow <= \\; + axi_r_prog_empty <= \\; + axi_r_prog_full <= \\; + axi_r_rd_data_count(12) <= \\; + axi_r_rd_data_count(11) <= \\; + axi_r_rd_data_count(10) <= \\; + axi_r_rd_data_count(9) <= \\; + axi_r_rd_data_count(8) <= \\; + axi_r_rd_data_count(7) <= \\; + axi_r_rd_data_count(6) <= \\; + axi_r_rd_data_count(5) <= \\; + axi_r_rd_data_count(4) <= \\; + axi_r_rd_data_count(3) <= \\; + axi_r_rd_data_count(2) <= \\; + axi_r_rd_data_count(1) <= \\; + axi_r_rd_data_count(0) <= \\; + axi_r_sbiterr <= \\; + axi_r_underflow <= \\; + axi_r_wr_data_count(12) <= \\; + axi_r_wr_data_count(11) <= \\; + axi_r_wr_data_count(10) <= \\; + axi_r_wr_data_count(9) <= \\; + axi_r_wr_data_count(8) <= \\; + axi_r_wr_data_count(7) <= \\; + axi_r_wr_data_count(6) <= \\; + axi_r_wr_data_count(5) <= \\; + axi_r_wr_data_count(4) <= \\; + axi_r_wr_data_count(3) <= \\; + axi_r_wr_data_count(2) <= \\; + axi_r_wr_data_count(1) <= \\; + axi_r_wr_data_count(0) <= \\; + axi_w_data_count(12) <= \\; + axi_w_data_count(11) <= \\; + axi_w_data_count(10) <= \\; + axi_w_data_count(9) <= \\; + axi_w_data_count(8) <= \\; + axi_w_data_count(7) <= \\; + axi_w_data_count(6) <= \\; + axi_w_data_count(5) <= \\; + axi_w_data_count(4) <= \\; + axi_w_data_count(3) <= \\; + axi_w_data_count(2) <= \\; + axi_w_data_count(1) <= \\; + axi_w_data_count(0) <= \\; + axi_w_dbiterr <= \\; + axi_w_overflow <= \\; + axi_w_prog_empty <= \\; + axi_w_prog_full <= \\; + axi_w_rd_data_count(12) <= \\; + axi_w_rd_data_count(11) <= \\; + axi_w_rd_data_count(10) <= \\; + axi_w_rd_data_count(9) <= \\; + axi_w_rd_data_count(8) <= \\; + axi_w_rd_data_count(7) <= \\; + axi_w_rd_data_count(6) <= \\; + axi_w_rd_data_count(5) <= \\; + axi_w_rd_data_count(4) <= \\; + axi_w_rd_data_count(3) <= \\; + axi_w_rd_data_count(2) <= \\; + axi_w_rd_data_count(1) <= \\; + axi_w_rd_data_count(0) <= \\; + axi_w_sbiterr <= \\; + axi_w_underflow <= \\; + axi_w_wr_data_count(12) <= \\; + axi_w_wr_data_count(11) <= \\; + axi_w_wr_data_count(10) <= \\; + axi_w_wr_data_count(9) <= \\; + axi_w_wr_data_count(8) <= \\; + axi_w_wr_data_count(7) <= \\; + axi_w_wr_data_count(6) <= \\; + axi_w_wr_data_count(5) <= \\; + axi_w_wr_data_count(4) <= \\; + axi_w_wr_data_count(3) <= \\; + axi_w_wr_data_count(2) <= \\; + axi_w_wr_data_count(1) <= \\; + axi_w_wr_data_count(0) <= \\; + axis_data_count(12) <= \\; + axis_data_count(11) <= \\; + axis_data_count(10) <= \\; + axis_data_count(9) <= \\; + axis_data_count(8) <= \\; + axis_data_count(7) <= \\; + axis_data_count(6) <= \\; + axis_data_count(5) <= \\; + axis_data_count(4) <= \\; + axis_data_count(3) <= \\; + axis_data_count(2) <= \\; + axis_data_count(1) <= \\; + axis_data_count(0) <= \\; + axis_dbiterr <= \\; + axis_overflow <= \\; + axis_prog_empty <= \\; + axis_prog_full <= \\; + axis_rd_data_count(12) <= \\; + axis_rd_data_count(11) <= \\; + axis_rd_data_count(10) <= \\; + axis_rd_data_count(9) <= \\; + axis_rd_data_count(8) <= \\; + axis_rd_data_count(7) <= \\; + axis_rd_data_count(6) <= \\; + axis_rd_data_count(5) <= \\; + axis_rd_data_count(4) <= \\; + axis_rd_data_count(3) <= \\; + axis_rd_data_count(2) <= \\; + axis_rd_data_count(1) <= \\; + axis_rd_data_count(0) <= \\; + axis_sbiterr <= \\; + axis_underflow <= \\; + axis_wr_data_count(12) <= \\; + axis_wr_data_count(11) <= \\; + axis_wr_data_count(10) <= \\; + axis_wr_data_count(9) <= \\; + axis_wr_data_count(8) <= \\; + axis_wr_data_count(7) <= \\; + axis_wr_data_count(6) <= \\; + axis_wr_data_count(5) <= \\; + axis_wr_data_count(4) <= \\; + axis_wr_data_count(3) <= \\; + axis_wr_data_count(2) <= \\; + axis_wr_data_count(1) <= \\; + axis_wr_data_count(0) <= \\; + data_count(12) <= \\; + data_count(11) <= \\; + data_count(10) <= \\; + data_count(9) <= \\; + data_count(8) <= \\; + data_count(7) <= \\; + data_count(6) <= \\; + data_count(5) <= \\; + data_count(4) <= \\; + data_count(3) <= \\; + data_count(2) <= \\; + data_count(1) <= \\; + data_count(0) <= \\; + dbiterr <= \\; + full <= \\; + m_axi_araddr(31) <= \\; + m_axi_araddr(30) <= \\; + m_axi_araddr(29) <= \\; + m_axi_araddr(28) <= \\; + m_axi_araddr(27) <= \\; + m_axi_araddr(26) <= \\; + m_axi_araddr(25) <= \\; + m_axi_araddr(24) <= \\; + m_axi_araddr(23) <= \\; + m_axi_araddr(22) <= \\; + m_axi_araddr(21) <= \\; + m_axi_araddr(20) <= \\; + m_axi_araddr(19) <= \\; + m_axi_araddr(18) <= \\; + m_axi_araddr(17) <= \\; + m_axi_araddr(16) <= \\; + m_axi_araddr(15) <= \\; + m_axi_araddr(14) <= \\; + m_axi_araddr(13) <= \\; + m_axi_araddr(12) <= \\; + m_axi_araddr(11) <= \\; + m_axi_araddr(10) <= \\; + m_axi_araddr(9) <= \\; + m_axi_araddr(8) <= \\; + m_axi_araddr(7) <= \\; + m_axi_araddr(6) <= \\; + m_axi_araddr(5) <= \\; + m_axi_araddr(4) <= \\; + m_axi_araddr(3) <= \\; + m_axi_araddr(2) <= \\; + m_axi_araddr(1) <= \\; + m_axi_araddr(0) <= \\; + m_axi_arburst(1) <= \\; + m_axi_arburst(0) <= \\; + m_axi_arcache(3) <= \\; + m_axi_arcache(2) <= \\; + m_axi_arcache(1) <= \\; + m_axi_arcache(0) <= \\; + m_axi_arid(0) <= \\; + m_axi_arlen(7) <= \\; + m_axi_arlen(6) <= \\; + m_axi_arlen(5) <= \\; + m_axi_arlen(4) <= \\; + m_axi_arlen(3) <= \\; + m_axi_arlen(2) <= \\; + m_axi_arlen(1) <= \\; + m_axi_arlen(0) <= \\; + m_axi_arlock(0) <= \\; + m_axi_arprot(2) <= \\; + m_axi_arprot(1) <= \\; + m_axi_arprot(0) <= \\; + m_axi_arqos(3) <= \\; + m_axi_arqos(2) <= \\; + m_axi_arqos(1) <= \\; + m_axi_arqos(0) <= \\; + m_axi_arregion(3) <= \\; + m_axi_arregion(2) <= \\; + m_axi_arregion(1) <= \\; + m_axi_arregion(0) <= \\; + m_axi_arsize(2) <= \\; + m_axi_arsize(1) <= \\; + m_axi_arsize(0) <= \\; + m_axi_aruser(0) <= \\; + m_axi_arvalid <= \\; + m_axi_awaddr(31) <= \\; + m_axi_awaddr(30) <= \\; + m_axi_awaddr(29) <= \\; + m_axi_awaddr(28) <= \\; + m_axi_awaddr(27) <= \\; + m_axi_awaddr(26) <= \\; + m_axi_awaddr(25) <= \\; + m_axi_awaddr(24) <= \\; + m_axi_awaddr(23) <= \\; + m_axi_awaddr(22) <= \\; + m_axi_awaddr(21) <= \\; + m_axi_awaddr(20) <= \\; + m_axi_awaddr(19) <= \\; + m_axi_awaddr(18) <= \\; + m_axi_awaddr(17) <= \\; + m_axi_awaddr(16) <= \\; + m_axi_awaddr(15) <= \\; + m_axi_awaddr(14) <= \\; + m_axi_awaddr(13) <= \\; + m_axi_awaddr(12) <= \\; + m_axi_awaddr(11) <= \\; + m_axi_awaddr(10) <= \\; + m_axi_awaddr(9) <= \\; + m_axi_awaddr(8) <= \\; + m_axi_awaddr(7) <= \\; + m_axi_awaddr(6) <= \\; + m_axi_awaddr(5) <= \\; + m_axi_awaddr(4) <= \\; + m_axi_awaddr(3) <= \\; + m_axi_awaddr(2) <= \\; + m_axi_awaddr(1) <= \\; + m_axi_awaddr(0) <= \\; + m_axi_awburst(1) <= \\; + m_axi_awburst(0) <= \\; + m_axi_awcache(3) <= \\; + m_axi_awcache(2) <= \\; + m_axi_awcache(1) <= \\; + m_axi_awcache(0) <= \\; + m_axi_awid(0) <= \\; + m_axi_awlen(7) <= \\; + m_axi_awlen(6) <= \\; + m_axi_awlen(5) <= \\; + m_axi_awlen(4) <= \\; + m_axi_awlen(3) <= \\; + m_axi_awlen(2) <= \\; + m_axi_awlen(1) <= \\; + m_axi_awlen(0) <= \\; + m_axi_awlock(0) <= \\; + m_axi_awprot(2) <= \\; + m_axi_awprot(1) <= \\; + m_axi_awprot(0) <= \\; + m_axi_awqos(3) <= \\; + m_axi_awqos(2) <= \\; + m_axi_awqos(1) <= \\; + m_axi_awqos(0) <= \\; + m_axi_awregion(3) <= \\; + m_axi_awregion(2) <= \\; + m_axi_awregion(1) <= \\; + m_axi_awregion(0) <= \\; + m_axi_awsize(2) <= \\; + m_axi_awsize(1) <= \\; + m_axi_awsize(0) <= \\; + m_axi_awuser(0) <= \\; + m_axi_awvalid <= \\; + m_axi_bready <= \\; + m_axi_rready <= \\; + m_axi_wdata(63) <= \\; + m_axi_wdata(62) <= \\; + m_axi_wdata(61) <= \\; + m_axi_wdata(60) <= \\; + m_axi_wdata(59) <= \\; + m_axi_wdata(58) <= \\; + m_axi_wdata(57) <= \\; + m_axi_wdata(56) <= \\; + m_axi_wdata(55) <= \\; + m_axi_wdata(54) <= \\; + m_axi_wdata(53) <= \\; + m_axi_wdata(52) <= \\; + m_axi_wdata(51) <= \\; + m_axi_wdata(50) <= \\; + m_axi_wdata(49) <= \\; + m_axi_wdata(48) <= \\; + m_axi_wdata(47) <= \\; + m_axi_wdata(46) <= \\; + m_axi_wdata(45) <= \\; + m_axi_wdata(44) <= \\; + m_axi_wdata(43) <= \\; + m_axi_wdata(42) <= \\; + m_axi_wdata(41) <= \\; + m_axi_wdata(40) <= \\; + m_axi_wdata(39) <= \\; + m_axi_wdata(38) <= \\; + m_axi_wdata(37) <= \\; + m_axi_wdata(36) <= \\; + m_axi_wdata(35) <= \\; + m_axi_wdata(34) <= \\; + m_axi_wdata(33) <= \\; + m_axi_wdata(32) <= \\; + m_axi_wdata(31) <= \\; + m_axi_wdata(30) <= \\; + m_axi_wdata(29) <= \\; + m_axi_wdata(28) <= \\; + m_axi_wdata(27) <= \\; + m_axi_wdata(26) <= \\; + m_axi_wdata(25) <= \\; + m_axi_wdata(24) <= \\; + m_axi_wdata(23) <= \\; + m_axi_wdata(22) <= \\; + m_axi_wdata(21) <= \\; + m_axi_wdata(20) <= \\; + m_axi_wdata(19) <= \\; + m_axi_wdata(18) <= \\; + m_axi_wdata(17) <= \\; + m_axi_wdata(16) <= \\; + m_axi_wdata(15) <= \\; + m_axi_wdata(14) <= \\; + m_axi_wdata(13) <= \\; + m_axi_wdata(12) <= \\; + m_axi_wdata(11) <= \\; + m_axi_wdata(10) <= \\; + m_axi_wdata(9) <= \\; + m_axi_wdata(8) <= \\; + m_axi_wdata(7) <= \\; + m_axi_wdata(6) <= \\; + m_axi_wdata(5) <= \\; + m_axi_wdata(4) <= \\; + m_axi_wdata(3) <= \\; + m_axi_wdata(2) <= \\; + m_axi_wdata(1) <= \\; + m_axi_wdata(0) <= \\; + m_axi_wid(0) <= \\; + m_axi_wlast <= \\; + m_axi_wstrb(7) <= \\; + m_axi_wstrb(6) <= \\; + m_axi_wstrb(5) <= \\; + m_axi_wstrb(4) <= \\; + m_axi_wstrb(3) <= \\; + m_axi_wstrb(2) <= \\; + m_axi_wstrb(1) <= \\; + m_axi_wstrb(0) <= \\; + m_axi_wuser(0) <= \\; + m_axi_wvalid <= \\; + m_axis_tdata(7) <= \\; + m_axis_tdata(6) <= \\; + m_axis_tdata(5) <= \\; + m_axis_tdata(4) <= \\; + m_axis_tdata(3) <= \\; + m_axis_tdata(2) <= \\; + m_axis_tdata(1) <= \\; + m_axis_tdata(0) <= \\; + m_axis_tdest(0) <= \\; + m_axis_tid(0) <= \\; + m_axis_tkeep(0) <= \\; + m_axis_tlast <= \\; + m_axis_tstrb(0) <= \\; + m_axis_tuser(3) <= \\; + m_axis_tuser(2) <= \\; + m_axis_tuser(1) <= \\; + m_axis_tuser(0) <= \\; + m_axis_tvalid <= \\; + prog_empty <= \\; + prog_full <= \\; + rd_data_count(12) <= \\; + rd_data_count(11) <= \\; + rd_data_count(10) <= \\; + rd_data_count(9) <= \\; + rd_data_count(8) <= \\; + rd_data_count(7) <= \\; + rd_data_count(6) <= \\; + rd_data_count(5) <= \\; + rd_data_count(4) <= \\; + rd_data_count(3) <= \\; + rd_data_count(2) <= \\; + rd_data_count(1) <= \\; + rd_data_count(0) <= \\; + rd_rst_busy <= \\; + s_axi_arready <= \\; + s_axi_awready <= \\; + s_axi_bid(0) <= \\; + s_axi_bresp(1) <= \\; + s_axi_bresp(0) <= \\; + s_axi_buser(0) <= \\; + s_axi_bvalid <= \\; + s_axi_rdata(63) <= \\; + s_axi_rdata(62) <= \\; + s_axi_rdata(61) <= \\; + s_axi_rdata(60) <= \\; + s_axi_rdata(59) <= \\; + s_axi_rdata(58) <= \\; + s_axi_rdata(57) <= \\; + s_axi_rdata(56) <= \\; + s_axi_rdata(55) <= \\; + s_axi_rdata(54) <= \\; + s_axi_rdata(53) <= \\; + s_axi_rdata(52) <= \\; + s_axi_rdata(51) <= \\; + s_axi_rdata(50) <= \\; + s_axi_rdata(49) <= \\; + s_axi_rdata(48) <= \\; + s_axi_rdata(47) <= \\; + s_axi_rdata(46) <= \\; + s_axi_rdata(45) <= \\; + s_axi_rdata(44) <= \\; + s_axi_rdata(43) <= \\; + s_axi_rdata(42) <= \\; + s_axi_rdata(41) <= \\; + s_axi_rdata(40) <= \\; + s_axi_rdata(39) <= \\; + s_axi_rdata(38) <= \\; + s_axi_rdata(37) <= \\; + s_axi_rdata(36) <= \\; + s_axi_rdata(35) <= \\; + s_axi_rdata(34) <= \\; + s_axi_rdata(33) <= \\; + s_axi_rdata(32) <= \\; + s_axi_rdata(31) <= \\; + s_axi_rdata(30) <= \\; + s_axi_rdata(29) <= \\; + s_axi_rdata(28) <= \\; + s_axi_rdata(27) <= \\; + s_axi_rdata(26) <= \\; + s_axi_rdata(25) <= \\; + s_axi_rdata(24) <= \\; + s_axi_rdata(23) <= \\; + s_axi_rdata(22) <= \\; + s_axi_rdata(21) <= \\; + s_axi_rdata(20) <= \\; + s_axi_rdata(19) <= \\; + s_axi_rdata(18) <= \\; + s_axi_rdata(17) <= \\; + s_axi_rdata(16) <= \\; + s_axi_rdata(15) <= \\; + s_axi_rdata(14) <= \\; + s_axi_rdata(13) <= \\; + s_axi_rdata(12) <= \\; + s_axi_rdata(11) <= \\; + s_axi_rdata(10) <= \\; + s_axi_rdata(9) <= \\; + s_axi_rdata(8) <= \\; + s_axi_rdata(7) <= \\; + s_axi_rdata(6) <= \\; + s_axi_rdata(5) <= \\; + s_axi_rdata(4) <= \\; + s_axi_rdata(3) <= \\; + s_axi_rdata(2) <= \\; + s_axi_rdata(1) <= \\; + s_axi_rdata(0) <= \\; + s_axi_rid(0) <= \\; + s_axi_rlast <= \\; + s_axi_rresp(1) <= \\; + s_axi_rresp(0) <= \\; + s_axi_ruser(0) <= \\; + s_axi_rvalid <= \\; + s_axi_wready <= \\; + s_axis_tready <= \\; + sbiterr <= \\; + wr_ack <= \\; + wr_data_count(12) <= \\; + wr_data_count(11) <= \\; + wr_data_count(10) <= \\; + wr_data_count(9) <= \\; + wr_data_count(8) <= \\; + wr_data_count(7) <= \\; + wr_data_count(6) <= \\; + wr_data_count(5) <= \\; + wr_data_count(4) <= \\; + wr_data_count(3) <= \\; + wr_data_count(2) <= \\; + wr_data_count(1) <= \\; + wr_data_count(0) <= \\; +GND: unisim.vcomponents.GND + port map ( + G => \\ + ); +inst_fifo_gen: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3_synth + port map ( + din(26 downto 0) => din(26 downto 0), + dout(26 downto 0) => dout(26 downto 0), + empty => empty, + overflow => overflow, + rd_clk => rd_clk, + rd_en => rd_en, + rst => rst, + underflow => underflow, + valid => valid, + wr_clk => wr_clk, + wr_en => wr_en, + wr_rst_busy => wr_rst_busy + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_v_vid_in_axi4s_v4_0_5_coupler is + port ( + dout : out STD_LOGIC_VECTOR ( 26 downto 0 ); + overflow : out STD_LOGIC; + m_axis_video_tvalid : out STD_LOGIC; + underflow : out STD_LOGIC; + vid_io_in_clk : in STD_LOGIC; + aclk : in STD_LOGIC; + FIFO_WR_DATA : in STD_LOGIC_VECTOR ( 26 downto 0 ); + aclken : in STD_LOGIC; + m_axis_video_tready : in STD_LOGIC; + vid_io_in_reset : in STD_LOGIC; + de_3 : in STD_LOGIC; + vtd_locked_reg : in STD_LOGIC; + vid_io_in_ce : in STD_LOGIC; + aresetn : in STD_LOGIC + ); +end Arty_Z7_20_v_vid_in_axi4s_0_0_v_vid_in_axi4s_v4_0_5_coupler; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_v_vid_in_axi4s_v4_0_5_coupler is + signal FIFO_INST_i_1_n_0 : STD_LOGIC; + signal empty_i : STD_LOGIC; + signal \^m_axis_video_tvalid\ : STD_LOGIC; + signal \rd_en_i__0\ : STD_LOGIC; + signal \wr_en_i__0\ : STD_LOGIC; + signal wr_rst_busy_i : STD_LOGIC; + signal NLW_FIFO_INST_almost_empty_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_almost_full_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_ar_overflow_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_ar_prog_full_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_ar_underflow_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_aw_overflow_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_aw_prog_full_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_aw_underflow_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_b_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_b_overflow_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_b_prog_empty_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_b_prog_full_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_b_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_b_underflow_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_r_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_r_overflow_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_r_prog_empty_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_r_prog_full_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_r_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_r_underflow_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_w_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_w_overflow_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_w_prog_empty_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_w_prog_full_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_w_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_w_underflow_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axis_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axis_overflow_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axis_prog_empty_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axis_prog_full_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axis_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axis_underflow_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_full_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_m_axi_arvalid_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_m_axi_awvalid_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_m_axi_bready_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_m_axi_rready_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_m_axi_wlast_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_m_axi_wvalid_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_m_axis_tlast_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_m_axis_tvalid_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_prog_empty_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_prog_full_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_rd_rst_busy_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_s_axi_arready_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_s_axi_awready_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_s_axi_bvalid_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_s_axi_rlast_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_s_axi_rvalid_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_s_axi_wready_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_s_axis_tready_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_wr_ack_UNCONNECTED : STD_LOGIC; + signal NLW_FIFO_INST_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_FIFO_INST_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_FIFO_INST_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_FIFO_INST_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_FIFO_INST_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_FIFO_INST_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_FIFO_INST_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_FIFO_INST_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_FIFO_INST_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_FIFO_INST_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal NLW_FIFO_INST_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal NLW_FIFO_INST_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal NLW_FIFO_INST_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal NLW_FIFO_INST_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal NLW_FIFO_INST_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal NLW_FIFO_INST_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal NLW_FIFO_INST_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal NLW_FIFO_INST_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal NLW_FIFO_INST_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal NLW_FIFO_INST_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_FIFO_INST_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_FIFO_INST_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_FIFO_INST_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_FIFO_INST_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_FIFO_INST_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_FIFO_INST_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_FIFO_INST_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_FIFO_INST_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_FIFO_INST_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_FIFO_INST_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_FIFO_INST_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_FIFO_INST_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_FIFO_INST_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_FIFO_INST_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_FIFO_INST_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_FIFO_INST_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_FIFO_INST_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_FIFO_INST_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_FIFO_INST_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_FIFO_INST_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_FIFO_INST_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_FIFO_INST_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal NLW_FIFO_INST_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_FIFO_INST_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_FIFO_INST_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_FIFO_INST_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_FIFO_INST_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_FIFO_INST_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_FIFO_INST_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_FIFO_INST_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_FIFO_INST_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_FIFO_INST_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 12 downto 0 ); + signal NLW_FIFO_INST_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_FIFO_INST_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_FIFO_INST_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_FIFO_INST_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal NLW_FIFO_INST_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_FIFO_INST_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_FIFO_INST_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_FIFO_INST_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 12 downto 0 ); + attribute C_ADD_NGC_CONSTRAINT : integer; + attribute C_ADD_NGC_CONSTRAINT of FIFO_INST : label is 0; + attribute C_APPLICATION_TYPE_AXIS : integer; + attribute C_APPLICATION_TYPE_AXIS of FIFO_INST : label is 0; + attribute C_APPLICATION_TYPE_RACH : integer; + attribute C_APPLICATION_TYPE_RACH of FIFO_INST : label is 0; + attribute C_APPLICATION_TYPE_RDCH : integer; + attribute C_APPLICATION_TYPE_RDCH of FIFO_INST : label is 0; + attribute C_APPLICATION_TYPE_WACH : integer; + attribute C_APPLICATION_TYPE_WACH of FIFO_INST : label is 0; + attribute C_APPLICATION_TYPE_WDCH : integer; + attribute C_APPLICATION_TYPE_WDCH of FIFO_INST : label is 0; + attribute C_APPLICATION_TYPE_WRCH : integer; + attribute C_APPLICATION_TYPE_WRCH of FIFO_INST : label is 0; + attribute C_AXIS_TDATA_WIDTH : integer; + attribute C_AXIS_TDATA_WIDTH of FIFO_INST : label is 8; + attribute C_AXIS_TDEST_WIDTH : integer; + attribute C_AXIS_TDEST_WIDTH of FIFO_INST : label is 1; + attribute C_AXIS_TID_WIDTH : integer; + attribute C_AXIS_TID_WIDTH of FIFO_INST : label is 1; + attribute C_AXIS_TKEEP_WIDTH : integer; + attribute C_AXIS_TKEEP_WIDTH of FIFO_INST : label is 1; + attribute C_AXIS_TSTRB_WIDTH : integer; + attribute C_AXIS_TSTRB_WIDTH of FIFO_INST : label is 1; + attribute C_AXIS_TUSER_WIDTH : integer; + attribute C_AXIS_TUSER_WIDTH of FIFO_INST : label is 4; + attribute C_AXIS_TYPE : integer; + attribute C_AXIS_TYPE of FIFO_INST : label is 0; + attribute C_AXI_ADDR_WIDTH : integer; + attribute C_AXI_ADDR_WIDTH of FIFO_INST : label is 32; + attribute C_AXI_ARUSER_WIDTH : integer; + attribute C_AXI_ARUSER_WIDTH of FIFO_INST : label is 1; + attribute C_AXI_AWUSER_WIDTH : integer; + attribute C_AXI_AWUSER_WIDTH of FIFO_INST : label is 1; + attribute C_AXI_BUSER_WIDTH : integer; + attribute C_AXI_BUSER_WIDTH of FIFO_INST : label is 1; + attribute C_AXI_DATA_WIDTH : integer; + attribute C_AXI_DATA_WIDTH of FIFO_INST : label is 64; + attribute C_AXI_ID_WIDTH : integer; + attribute C_AXI_ID_WIDTH of FIFO_INST : label is 1; + attribute C_AXI_LEN_WIDTH : integer; + attribute C_AXI_LEN_WIDTH of FIFO_INST : label is 8; + attribute C_AXI_LOCK_WIDTH : integer; + attribute C_AXI_LOCK_WIDTH of FIFO_INST : label is 1; + attribute C_AXI_RUSER_WIDTH : integer; + attribute C_AXI_RUSER_WIDTH of FIFO_INST : label is 1; + attribute C_AXI_TYPE : integer; + attribute C_AXI_TYPE of FIFO_INST : label is 1; + attribute C_AXI_WUSER_WIDTH : integer; + attribute C_AXI_WUSER_WIDTH of FIFO_INST : label is 1; + attribute C_COMMON_CLOCK : integer; + attribute C_COMMON_CLOCK of FIFO_INST : label is 0; + attribute C_COUNT_TYPE : integer; + attribute C_COUNT_TYPE of FIFO_INST : label is 0; + attribute C_DATA_COUNT_WIDTH : integer; + attribute C_DATA_COUNT_WIDTH of FIFO_INST : label is 13; + attribute C_DEFAULT_VALUE : string; + attribute C_DEFAULT_VALUE of FIFO_INST : label is "BlankString"; + attribute C_DIN_WIDTH : integer; + attribute C_DIN_WIDTH of FIFO_INST : label is 27; + attribute C_DIN_WIDTH_AXIS : integer; + attribute C_DIN_WIDTH_AXIS of FIFO_INST : label is 1; + attribute C_DIN_WIDTH_RACH : integer; + attribute C_DIN_WIDTH_RACH of FIFO_INST : label is 32; + attribute C_DIN_WIDTH_RDCH : integer; + attribute C_DIN_WIDTH_RDCH of FIFO_INST : label is 64; + attribute C_DIN_WIDTH_WACH : integer; + attribute C_DIN_WIDTH_WACH of FIFO_INST : label is 32; + attribute C_DIN_WIDTH_WDCH : integer; + attribute C_DIN_WIDTH_WDCH of FIFO_INST : label is 64; + attribute C_DIN_WIDTH_WRCH : integer; + attribute C_DIN_WIDTH_WRCH of FIFO_INST : label is 2; + attribute C_DOUT_RST_VAL : string; + attribute C_DOUT_RST_VAL of FIFO_INST : label is "0"; + attribute C_DOUT_WIDTH : integer; + attribute C_DOUT_WIDTH of FIFO_INST : label is 27; + attribute C_ENABLE_RLOCS : integer; + attribute C_ENABLE_RLOCS of FIFO_INST : label is 0; + attribute C_ENABLE_RST_SYNC : integer; + attribute C_ENABLE_RST_SYNC of FIFO_INST : label is 1; + attribute C_EN_SAFETY_CKT : integer; + attribute C_EN_SAFETY_CKT of FIFO_INST : label is 0; + attribute C_ERROR_INJECTION_TYPE : integer; + attribute C_ERROR_INJECTION_TYPE of FIFO_INST : label is 0; + attribute C_ERROR_INJECTION_TYPE_AXIS : integer; + attribute C_ERROR_INJECTION_TYPE_AXIS of FIFO_INST : label is 0; + attribute C_ERROR_INJECTION_TYPE_RACH : integer; + attribute C_ERROR_INJECTION_TYPE_RACH of FIFO_INST : label is 0; + attribute C_ERROR_INJECTION_TYPE_RDCH : integer; + attribute C_ERROR_INJECTION_TYPE_RDCH of FIFO_INST : label is 0; + attribute C_ERROR_INJECTION_TYPE_WACH : integer; + attribute C_ERROR_INJECTION_TYPE_WACH of FIFO_INST : label is 0; + attribute C_ERROR_INJECTION_TYPE_WDCH : integer; + attribute C_ERROR_INJECTION_TYPE_WDCH of FIFO_INST : label is 0; + attribute C_ERROR_INJECTION_TYPE_WRCH : integer; + attribute C_ERROR_INJECTION_TYPE_WRCH of FIFO_INST : label is 0; + attribute C_FAMILY : string; + attribute C_FAMILY of FIFO_INST : label is "zynq"; + attribute C_FULL_FLAGS_RST_VAL : integer; + attribute C_FULL_FLAGS_RST_VAL of FIFO_INST : label is 1; + attribute C_HAS_ALMOST_EMPTY : integer; + attribute C_HAS_ALMOST_EMPTY of FIFO_INST : label is 0; + attribute C_HAS_ALMOST_FULL : integer; + attribute C_HAS_ALMOST_FULL of FIFO_INST : label is 0; + attribute C_HAS_AXIS_TDATA : integer; + attribute C_HAS_AXIS_TDATA of FIFO_INST : label is 1; + attribute C_HAS_AXIS_TDEST : integer; + attribute C_HAS_AXIS_TDEST of FIFO_INST : label is 0; + attribute C_HAS_AXIS_TID : integer; + attribute C_HAS_AXIS_TID of FIFO_INST : label is 0; + attribute C_HAS_AXIS_TKEEP : integer; + attribute C_HAS_AXIS_TKEEP of FIFO_INST : label is 0; + attribute C_HAS_AXIS_TLAST : integer; + attribute C_HAS_AXIS_TLAST of FIFO_INST : label is 0; + attribute C_HAS_AXIS_TREADY : integer; + attribute C_HAS_AXIS_TREADY of FIFO_INST : label is 1; + attribute C_HAS_AXIS_TSTRB : integer; + attribute C_HAS_AXIS_TSTRB of FIFO_INST : label is 0; + attribute C_HAS_AXIS_TUSER : integer; + attribute C_HAS_AXIS_TUSER of FIFO_INST : label is 1; + attribute C_HAS_AXI_ARUSER : integer; + attribute C_HAS_AXI_ARUSER of FIFO_INST : label is 0; + attribute C_HAS_AXI_AWUSER : integer; + attribute C_HAS_AXI_AWUSER of FIFO_INST : label is 0; + attribute C_HAS_AXI_BUSER : integer; + attribute C_HAS_AXI_BUSER of FIFO_INST : label is 0; + attribute C_HAS_AXI_ID : integer; + attribute C_HAS_AXI_ID of FIFO_INST : label is 0; + attribute C_HAS_AXI_RD_CHANNEL : integer; + attribute C_HAS_AXI_RD_CHANNEL of FIFO_INST : label is 1; + attribute C_HAS_AXI_RUSER : integer; + attribute C_HAS_AXI_RUSER of FIFO_INST : label is 0; + attribute C_HAS_AXI_WR_CHANNEL : integer; + attribute C_HAS_AXI_WR_CHANNEL of FIFO_INST : label is 1; + attribute C_HAS_AXI_WUSER : integer; + attribute C_HAS_AXI_WUSER of FIFO_INST : label is 0; + attribute C_HAS_BACKUP : integer; + attribute C_HAS_BACKUP of FIFO_INST : label is 0; + attribute C_HAS_DATA_COUNT : integer; + attribute C_HAS_DATA_COUNT of FIFO_INST : label is 0; + attribute C_HAS_DATA_COUNTS_AXIS : integer; + attribute C_HAS_DATA_COUNTS_AXIS of FIFO_INST : label is 0; + attribute C_HAS_DATA_COUNTS_RACH : integer; + attribute C_HAS_DATA_COUNTS_RACH of FIFO_INST : label is 0; + attribute C_HAS_DATA_COUNTS_RDCH : integer; + attribute C_HAS_DATA_COUNTS_RDCH of FIFO_INST : label is 0; + attribute C_HAS_DATA_COUNTS_WACH : integer; + attribute C_HAS_DATA_COUNTS_WACH of FIFO_INST : label is 0; + attribute C_HAS_DATA_COUNTS_WDCH : integer; + attribute C_HAS_DATA_COUNTS_WDCH of FIFO_INST : label is 0; + attribute C_HAS_DATA_COUNTS_WRCH : integer; + attribute C_HAS_DATA_COUNTS_WRCH of FIFO_INST : label is 0; + attribute C_HAS_INT_CLK : integer; + attribute C_HAS_INT_CLK of FIFO_INST : label is 0; + attribute C_HAS_MASTER_CE : integer; + attribute C_HAS_MASTER_CE of FIFO_INST : label is 0; + attribute C_HAS_MEMINIT_FILE : integer; + attribute C_HAS_MEMINIT_FILE of FIFO_INST : label is 0; + attribute C_HAS_OVERFLOW : integer; + attribute C_HAS_OVERFLOW of FIFO_INST : label is 1; + attribute C_HAS_PROG_FLAGS_AXIS : integer; + attribute C_HAS_PROG_FLAGS_AXIS of FIFO_INST : label is 0; + attribute C_HAS_PROG_FLAGS_RACH : integer; + attribute C_HAS_PROG_FLAGS_RACH of FIFO_INST : label is 0; + attribute C_HAS_PROG_FLAGS_RDCH : integer; + attribute C_HAS_PROG_FLAGS_RDCH of FIFO_INST : label is 0; + attribute C_HAS_PROG_FLAGS_WACH : integer; + attribute C_HAS_PROG_FLAGS_WACH of FIFO_INST : label is 0; + attribute C_HAS_PROG_FLAGS_WDCH : integer; + attribute C_HAS_PROG_FLAGS_WDCH of FIFO_INST : label is 0; + attribute C_HAS_PROG_FLAGS_WRCH : integer; + attribute C_HAS_PROG_FLAGS_WRCH of FIFO_INST : label is 0; + attribute C_HAS_RD_DATA_COUNT : integer; + attribute C_HAS_RD_DATA_COUNT of FIFO_INST : label is 1; + attribute C_HAS_RD_RST : integer; + attribute C_HAS_RD_RST of FIFO_INST : label is 0; + attribute C_HAS_RST : integer; + attribute C_HAS_RST of FIFO_INST : label is 1; + attribute C_HAS_SLAVE_CE : integer; + attribute C_HAS_SLAVE_CE of FIFO_INST : label is 0; + attribute C_HAS_SRST : integer; + attribute C_HAS_SRST of FIFO_INST : label is 0; + attribute C_HAS_UNDERFLOW : integer; + attribute C_HAS_UNDERFLOW of FIFO_INST : label is 1; + attribute C_HAS_VALID : integer; + attribute C_HAS_VALID of FIFO_INST : label is 1; + attribute C_HAS_WR_ACK : integer; + attribute C_HAS_WR_ACK of FIFO_INST : label is 0; + attribute C_HAS_WR_DATA_COUNT : integer; + attribute C_HAS_WR_DATA_COUNT of FIFO_INST : label is 1; + attribute C_HAS_WR_RST : integer; + attribute C_HAS_WR_RST of FIFO_INST : label is 0; + attribute C_IMPLEMENTATION_TYPE : integer; + attribute C_IMPLEMENTATION_TYPE of FIFO_INST : label is 2; + attribute C_IMPLEMENTATION_TYPE_AXIS : integer; + attribute C_IMPLEMENTATION_TYPE_AXIS of FIFO_INST : label is 1; + attribute C_IMPLEMENTATION_TYPE_RACH : integer; + attribute C_IMPLEMENTATION_TYPE_RACH of FIFO_INST : label is 1; + attribute C_IMPLEMENTATION_TYPE_RDCH : integer; + attribute C_IMPLEMENTATION_TYPE_RDCH of FIFO_INST : label is 1; + attribute C_IMPLEMENTATION_TYPE_WACH : integer; + attribute C_IMPLEMENTATION_TYPE_WACH of FIFO_INST : label is 1; + attribute C_IMPLEMENTATION_TYPE_WDCH : integer; + attribute C_IMPLEMENTATION_TYPE_WDCH of FIFO_INST : label is 1; + attribute C_IMPLEMENTATION_TYPE_WRCH : integer; + attribute C_IMPLEMENTATION_TYPE_WRCH of FIFO_INST : label is 1; + attribute C_INIT_WR_PNTR_VAL : integer; + attribute C_INIT_WR_PNTR_VAL of FIFO_INST : label is 0; + attribute C_INTERFACE_TYPE : integer; + attribute C_INTERFACE_TYPE of FIFO_INST : label is 0; + attribute C_MEMORY_TYPE : integer; + attribute C_MEMORY_TYPE of FIFO_INST : label is 1; + attribute C_MIF_FILE_NAME : string; + attribute C_MIF_FILE_NAME of FIFO_INST : label is "BlankString"; + attribute C_MSGON_VAL : integer; + attribute C_MSGON_VAL of FIFO_INST : label is 1; + attribute C_OPTIMIZATION_MODE : integer; + attribute C_OPTIMIZATION_MODE of FIFO_INST : label is 0; + attribute C_OVERFLOW_LOW : integer; + attribute C_OVERFLOW_LOW of FIFO_INST : label is 0; + attribute C_POWER_SAVING_MODE : integer; + attribute C_POWER_SAVING_MODE of FIFO_INST : label is 0; + attribute C_PRELOAD_LATENCY : integer; + attribute C_PRELOAD_LATENCY of FIFO_INST : label is 0; + attribute C_PRELOAD_REGS : integer; + attribute C_PRELOAD_REGS of FIFO_INST : label is 1; + attribute C_PRIM_FIFO_TYPE : string; + attribute C_PRIM_FIFO_TYPE of FIFO_INST : label is "1kx36"; + attribute C_PRIM_FIFO_TYPE_AXIS : string; + attribute C_PRIM_FIFO_TYPE_AXIS of FIFO_INST : label is "1kx18"; + attribute C_PRIM_FIFO_TYPE_RACH : string; + attribute C_PRIM_FIFO_TYPE_RACH of FIFO_INST : label is "512x36"; + attribute C_PRIM_FIFO_TYPE_RDCH : string; + attribute C_PRIM_FIFO_TYPE_RDCH of FIFO_INST : label is "1kx36"; + attribute C_PRIM_FIFO_TYPE_WACH : string; + attribute C_PRIM_FIFO_TYPE_WACH of FIFO_INST : label is "512x36"; + attribute C_PRIM_FIFO_TYPE_WDCH : string; + attribute C_PRIM_FIFO_TYPE_WDCH of FIFO_INST : label is "1kx36"; + attribute C_PRIM_FIFO_TYPE_WRCH : string; + attribute C_PRIM_FIFO_TYPE_WRCH of FIFO_INST : label is "512x36"; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of FIFO_INST : label is 4; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of FIFO_INST : label is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of FIFO_INST : label is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of FIFO_INST : label is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of FIFO_INST : label is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of FIFO_INST : label is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of FIFO_INST : label is 1022; + attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer; + attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of FIFO_INST : label is 5; + attribute C_PROG_EMPTY_TYPE : integer; + attribute C_PROG_EMPTY_TYPE of FIFO_INST : label is 0; + attribute C_PROG_EMPTY_TYPE_AXIS : integer; + attribute C_PROG_EMPTY_TYPE_AXIS of FIFO_INST : label is 0; + attribute C_PROG_EMPTY_TYPE_RACH : integer; + attribute C_PROG_EMPTY_TYPE_RACH of FIFO_INST : label is 0; + attribute C_PROG_EMPTY_TYPE_RDCH : integer; + attribute C_PROG_EMPTY_TYPE_RDCH of FIFO_INST : label is 0; + attribute C_PROG_EMPTY_TYPE_WACH : integer; + attribute C_PROG_EMPTY_TYPE_WACH of FIFO_INST : label is 0; + attribute C_PROG_EMPTY_TYPE_WDCH : integer; + attribute C_PROG_EMPTY_TYPE_WDCH of FIFO_INST : label is 0; + attribute C_PROG_EMPTY_TYPE_WRCH : integer; + attribute C_PROG_EMPTY_TYPE_WRCH of FIFO_INST : label is 0; + attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL of FIFO_INST : label is 4095; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of FIFO_INST : label is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of FIFO_INST : label is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of FIFO_INST : label is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of FIFO_INST : label is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of FIFO_INST : label is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of FIFO_INST : label is 1023; + attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer; + attribute C_PROG_FULL_THRESH_NEGATE_VAL of FIFO_INST : label is 4094; + attribute C_PROG_FULL_TYPE : integer; + attribute C_PROG_FULL_TYPE of FIFO_INST : label is 0; + attribute C_PROG_FULL_TYPE_AXIS : integer; + attribute C_PROG_FULL_TYPE_AXIS of FIFO_INST : label is 0; + attribute C_PROG_FULL_TYPE_RACH : integer; + attribute C_PROG_FULL_TYPE_RACH of FIFO_INST : label is 0; + attribute C_PROG_FULL_TYPE_RDCH : integer; + attribute C_PROG_FULL_TYPE_RDCH of FIFO_INST : label is 0; + attribute C_PROG_FULL_TYPE_WACH : integer; + attribute C_PROG_FULL_TYPE_WACH of FIFO_INST : label is 0; + attribute C_PROG_FULL_TYPE_WDCH : integer; + attribute C_PROG_FULL_TYPE_WDCH of FIFO_INST : label is 0; + attribute C_PROG_FULL_TYPE_WRCH : integer; + attribute C_PROG_FULL_TYPE_WRCH of FIFO_INST : label is 0; + attribute C_RACH_TYPE : integer; + attribute C_RACH_TYPE of FIFO_INST : label is 0; + attribute C_RDCH_TYPE : integer; + attribute C_RDCH_TYPE of FIFO_INST : label is 0; + attribute C_RD_DATA_COUNT_WIDTH : integer; + attribute C_RD_DATA_COUNT_WIDTH of FIFO_INST : label is 13; + attribute C_RD_DEPTH : integer; + attribute C_RD_DEPTH of FIFO_INST : label is 4096; + attribute C_RD_FREQ : integer; + attribute C_RD_FREQ of FIFO_INST : label is 1; + attribute C_RD_PNTR_WIDTH : integer; + attribute C_RD_PNTR_WIDTH of FIFO_INST : label is 12; + attribute C_REG_SLICE_MODE_AXIS : integer; + attribute C_REG_SLICE_MODE_AXIS of FIFO_INST : label is 0; + attribute C_REG_SLICE_MODE_RACH : integer; + attribute C_REG_SLICE_MODE_RACH of FIFO_INST : label is 0; + attribute C_REG_SLICE_MODE_RDCH : integer; + attribute C_REG_SLICE_MODE_RDCH of FIFO_INST : label is 0; + attribute C_REG_SLICE_MODE_WACH : integer; + attribute C_REG_SLICE_MODE_WACH of FIFO_INST : label is 0; + attribute C_REG_SLICE_MODE_WDCH : integer; + attribute C_REG_SLICE_MODE_WDCH of FIFO_INST : label is 0; + attribute C_REG_SLICE_MODE_WRCH : integer; + attribute C_REG_SLICE_MODE_WRCH of FIFO_INST : label is 0; + attribute C_SELECT_XPM : integer; + attribute C_SELECT_XPM of FIFO_INST : label is 0; + attribute C_SYNCHRONIZER_STAGE : integer; + attribute C_SYNCHRONIZER_STAGE of FIFO_INST : label is 2; + attribute C_UNDERFLOW_LOW : integer; + attribute C_UNDERFLOW_LOW of FIFO_INST : label is 0; + attribute C_USE_COMMON_OVERFLOW : integer; + attribute C_USE_COMMON_OVERFLOW of FIFO_INST : label is 0; + attribute C_USE_COMMON_UNDERFLOW : integer; + attribute C_USE_COMMON_UNDERFLOW of FIFO_INST : label is 0; + attribute C_USE_DEFAULT_SETTINGS : integer; + attribute C_USE_DEFAULT_SETTINGS of FIFO_INST : label is 0; + attribute C_USE_DOUT_RST : integer; + attribute C_USE_DOUT_RST of FIFO_INST : label is 1; + attribute C_USE_ECC : integer; + attribute C_USE_ECC of FIFO_INST : label is 0; + attribute C_USE_ECC_AXIS : integer; + attribute C_USE_ECC_AXIS of FIFO_INST : label is 0; + attribute C_USE_ECC_RACH : integer; + attribute C_USE_ECC_RACH of FIFO_INST : label is 0; + attribute C_USE_ECC_RDCH : integer; + attribute C_USE_ECC_RDCH of FIFO_INST : label is 0; + attribute C_USE_ECC_WACH : integer; + attribute C_USE_ECC_WACH of FIFO_INST : label is 0; + attribute C_USE_ECC_WDCH : integer; + attribute C_USE_ECC_WDCH of FIFO_INST : label is 0; + attribute C_USE_ECC_WRCH : integer; + attribute C_USE_ECC_WRCH of FIFO_INST : label is 0; + attribute C_USE_EMBEDDED_REG : integer; + attribute C_USE_EMBEDDED_REG of FIFO_INST : label is 1; + attribute C_USE_FIFO16_FLAGS : integer; + attribute C_USE_FIFO16_FLAGS of FIFO_INST : label is 0; + attribute C_USE_FWFT_DATA_COUNT : integer; + attribute C_USE_FWFT_DATA_COUNT of FIFO_INST : label is 1; + attribute C_USE_PIPELINE_REG : integer; + attribute C_USE_PIPELINE_REG of FIFO_INST : label is 0; + attribute C_VALID_LOW : integer; + attribute C_VALID_LOW of FIFO_INST : label is 0; + attribute C_WACH_TYPE : integer; + attribute C_WACH_TYPE of FIFO_INST : label is 0; + attribute C_WDCH_TYPE : integer; + attribute C_WDCH_TYPE of FIFO_INST : label is 0; + attribute C_WRCH_TYPE : integer; + attribute C_WRCH_TYPE of FIFO_INST : label is 0; + attribute C_WR_ACK_LOW : integer; + attribute C_WR_ACK_LOW of FIFO_INST : label is 0; + attribute C_WR_DATA_COUNT_WIDTH : integer; + attribute C_WR_DATA_COUNT_WIDTH of FIFO_INST : label is 13; + attribute C_WR_DEPTH : integer; + attribute C_WR_DEPTH of FIFO_INST : label is 4096; + attribute C_WR_DEPTH_AXIS : integer; + attribute C_WR_DEPTH_AXIS of FIFO_INST : label is 1024; + attribute C_WR_DEPTH_RACH : integer; + attribute C_WR_DEPTH_RACH of FIFO_INST : label is 16; + attribute C_WR_DEPTH_RDCH : integer; + attribute C_WR_DEPTH_RDCH of FIFO_INST : label is 1024; + attribute C_WR_DEPTH_WACH : integer; + attribute C_WR_DEPTH_WACH of FIFO_INST : label is 16; + attribute C_WR_DEPTH_WDCH : integer; + attribute C_WR_DEPTH_WDCH of FIFO_INST : label is 1024; + attribute C_WR_DEPTH_WRCH : integer; + attribute C_WR_DEPTH_WRCH of FIFO_INST : label is 16; + attribute C_WR_FREQ : integer; + attribute C_WR_FREQ of FIFO_INST : label is 1; + attribute C_WR_PNTR_WIDTH : integer; + attribute C_WR_PNTR_WIDTH of FIFO_INST : label is 12; + attribute C_WR_PNTR_WIDTH_AXIS : integer; + attribute C_WR_PNTR_WIDTH_AXIS of FIFO_INST : label is 12; + attribute C_WR_PNTR_WIDTH_RACH : integer; + attribute C_WR_PNTR_WIDTH_RACH of FIFO_INST : label is 4; + attribute C_WR_PNTR_WIDTH_RDCH : integer; + attribute C_WR_PNTR_WIDTH_RDCH of FIFO_INST : label is 12; + attribute C_WR_PNTR_WIDTH_WACH : integer; + attribute C_WR_PNTR_WIDTH_WACH of FIFO_INST : label is 4; + attribute C_WR_PNTR_WIDTH_WDCH : integer; + attribute C_WR_PNTR_WIDTH_WDCH of FIFO_INST : label is 12; + attribute C_WR_PNTR_WIDTH_WRCH : integer; + attribute C_WR_PNTR_WIDTH_WRCH of FIFO_INST : label is 4; + attribute C_WR_RESPONSE_LATENCY : integer; + attribute C_WR_RESPONSE_LATENCY of FIFO_INST : label is 1; +begin + m_axis_video_tvalid <= \^m_axis_video_tvalid\; +FIFO_INST: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_fifo_generator_v13_1_3 + port map ( + almost_empty => NLW_FIFO_INST_almost_empty_UNCONNECTED, + almost_full => NLW_FIFO_INST_almost_full_UNCONNECTED, + axi_ar_data_count(4 downto 0) => NLW_FIFO_INST_axi_ar_data_count_UNCONNECTED(4 downto 0), + axi_ar_dbiterr => NLW_FIFO_INST_axi_ar_dbiterr_UNCONNECTED, + axi_ar_injectdbiterr => '0', + axi_ar_injectsbiterr => '0', + axi_ar_overflow => NLW_FIFO_INST_axi_ar_overflow_UNCONNECTED, + axi_ar_prog_empty => NLW_FIFO_INST_axi_ar_prog_empty_UNCONNECTED, + axi_ar_prog_empty_thresh(3 downto 0) => B"0000", + axi_ar_prog_full => NLW_FIFO_INST_axi_ar_prog_full_UNCONNECTED, + axi_ar_prog_full_thresh(3 downto 0) => B"0000", + axi_ar_rd_data_count(4 downto 0) => NLW_FIFO_INST_axi_ar_rd_data_count_UNCONNECTED(4 downto 0), + axi_ar_sbiterr => NLW_FIFO_INST_axi_ar_sbiterr_UNCONNECTED, + axi_ar_underflow => NLW_FIFO_INST_axi_ar_underflow_UNCONNECTED, + axi_ar_wr_data_count(4 downto 0) => NLW_FIFO_INST_axi_ar_wr_data_count_UNCONNECTED(4 downto 0), + axi_aw_data_count(4 downto 0) => NLW_FIFO_INST_axi_aw_data_count_UNCONNECTED(4 downto 0), + axi_aw_dbiterr => NLW_FIFO_INST_axi_aw_dbiterr_UNCONNECTED, + axi_aw_injectdbiterr => '0', + axi_aw_injectsbiterr => '0', + axi_aw_overflow => NLW_FIFO_INST_axi_aw_overflow_UNCONNECTED, + axi_aw_prog_empty => NLW_FIFO_INST_axi_aw_prog_empty_UNCONNECTED, + axi_aw_prog_empty_thresh(3 downto 0) => B"0000", + axi_aw_prog_full => NLW_FIFO_INST_axi_aw_prog_full_UNCONNECTED, + axi_aw_prog_full_thresh(3 downto 0) => B"0000", + axi_aw_rd_data_count(4 downto 0) => NLW_FIFO_INST_axi_aw_rd_data_count_UNCONNECTED(4 downto 0), + axi_aw_sbiterr => NLW_FIFO_INST_axi_aw_sbiterr_UNCONNECTED, + axi_aw_underflow => NLW_FIFO_INST_axi_aw_underflow_UNCONNECTED, + axi_aw_wr_data_count(4 downto 0) => NLW_FIFO_INST_axi_aw_wr_data_count_UNCONNECTED(4 downto 0), + axi_b_data_count(4 downto 0) => NLW_FIFO_INST_axi_b_data_count_UNCONNECTED(4 downto 0), + axi_b_dbiterr => NLW_FIFO_INST_axi_b_dbiterr_UNCONNECTED, + axi_b_injectdbiterr => '0', + axi_b_injectsbiterr => '0', + axi_b_overflow => NLW_FIFO_INST_axi_b_overflow_UNCONNECTED, + axi_b_prog_empty => NLW_FIFO_INST_axi_b_prog_empty_UNCONNECTED, + axi_b_prog_empty_thresh(3 downto 0) => B"0000", + axi_b_prog_full => NLW_FIFO_INST_axi_b_prog_full_UNCONNECTED, + axi_b_prog_full_thresh(3 downto 0) => B"0000", + axi_b_rd_data_count(4 downto 0) => NLW_FIFO_INST_axi_b_rd_data_count_UNCONNECTED(4 downto 0), + axi_b_sbiterr => NLW_FIFO_INST_axi_b_sbiterr_UNCONNECTED, + axi_b_underflow => NLW_FIFO_INST_axi_b_underflow_UNCONNECTED, + axi_b_wr_data_count(4 downto 0) => NLW_FIFO_INST_axi_b_wr_data_count_UNCONNECTED(4 downto 0), + axi_r_data_count(12 downto 0) => NLW_FIFO_INST_axi_r_data_count_UNCONNECTED(12 downto 0), + axi_r_dbiterr => NLW_FIFO_INST_axi_r_dbiterr_UNCONNECTED, + axi_r_injectdbiterr => '0', + axi_r_injectsbiterr => '0', + axi_r_overflow => NLW_FIFO_INST_axi_r_overflow_UNCONNECTED, + axi_r_prog_empty => NLW_FIFO_INST_axi_r_prog_empty_UNCONNECTED, + axi_r_prog_empty_thresh(11 downto 0) => B"000000000000", + axi_r_prog_full => NLW_FIFO_INST_axi_r_prog_full_UNCONNECTED, + axi_r_prog_full_thresh(11 downto 0) => B"000000000000", + axi_r_rd_data_count(12 downto 0) => NLW_FIFO_INST_axi_r_rd_data_count_UNCONNECTED(12 downto 0), + axi_r_sbiterr => NLW_FIFO_INST_axi_r_sbiterr_UNCONNECTED, + axi_r_underflow => NLW_FIFO_INST_axi_r_underflow_UNCONNECTED, + axi_r_wr_data_count(12 downto 0) => NLW_FIFO_INST_axi_r_wr_data_count_UNCONNECTED(12 downto 0), + axi_w_data_count(12 downto 0) => NLW_FIFO_INST_axi_w_data_count_UNCONNECTED(12 downto 0), + axi_w_dbiterr => NLW_FIFO_INST_axi_w_dbiterr_UNCONNECTED, + axi_w_injectdbiterr => '0', + axi_w_injectsbiterr => '0', + axi_w_overflow => NLW_FIFO_INST_axi_w_overflow_UNCONNECTED, + axi_w_prog_empty => NLW_FIFO_INST_axi_w_prog_empty_UNCONNECTED, + axi_w_prog_empty_thresh(11 downto 0) => B"000000000000", + axi_w_prog_full => NLW_FIFO_INST_axi_w_prog_full_UNCONNECTED, + axi_w_prog_full_thresh(11 downto 0) => B"000000000000", + axi_w_rd_data_count(12 downto 0) => NLW_FIFO_INST_axi_w_rd_data_count_UNCONNECTED(12 downto 0), + axi_w_sbiterr => NLW_FIFO_INST_axi_w_sbiterr_UNCONNECTED, + axi_w_underflow => NLW_FIFO_INST_axi_w_underflow_UNCONNECTED, + axi_w_wr_data_count(12 downto 0) => NLW_FIFO_INST_axi_w_wr_data_count_UNCONNECTED(12 downto 0), + axis_data_count(12 downto 0) => NLW_FIFO_INST_axis_data_count_UNCONNECTED(12 downto 0), + axis_dbiterr => NLW_FIFO_INST_axis_dbiterr_UNCONNECTED, + axis_injectdbiterr => '0', + axis_injectsbiterr => '0', + axis_overflow => NLW_FIFO_INST_axis_overflow_UNCONNECTED, + axis_prog_empty => NLW_FIFO_INST_axis_prog_empty_UNCONNECTED, + axis_prog_empty_thresh(11 downto 0) => B"000000000000", + axis_prog_full => NLW_FIFO_INST_axis_prog_full_UNCONNECTED, + axis_prog_full_thresh(11 downto 0) => B"000000000000", + axis_rd_data_count(12 downto 0) => NLW_FIFO_INST_axis_rd_data_count_UNCONNECTED(12 downto 0), + axis_sbiterr => NLW_FIFO_INST_axis_sbiterr_UNCONNECTED, + axis_underflow => NLW_FIFO_INST_axis_underflow_UNCONNECTED, + axis_wr_data_count(12 downto 0) => NLW_FIFO_INST_axis_wr_data_count_UNCONNECTED(12 downto 0), + backup => '0', + backup_marker => '0', + clk => '0', + data_count(12 downto 0) => NLW_FIFO_INST_data_count_UNCONNECTED(12 downto 0), + dbiterr => NLW_FIFO_INST_dbiterr_UNCONNECTED, + din(26 downto 0) => FIFO_WR_DATA(26 downto 0), + dout(26 downto 0) => dout(26 downto 0), + empty => empty_i, + full => NLW_FIFO_INST_full_UNCONNECTED, + injectdbiterr => '0', + injectsbiterr => '0', + int_clk => '0', + m_aclk => '0', + m_aclk_en => '0', + m_axi_araddr(31 downto 0) => NLW_FIFO_INST_m_axi_araddr_UNCONNECTED(31 downto 0), + m_axi_arburst(1 downto 0) => NLW_FIFO_INST_m_axi_arburst_UNCONNECTED(1 downto 0), + m_axi_arcache(3 downto 0) => NLW_FIFO_INST_m_axi_arcache_UNCONNECTED(3 downto 0), + m_axi_arid(0) => NLW_FIFO_INST_m_axi_arid_UNCONNECTED(0), + m_axi_arlen(7 downto 0) => NLW_FIFO_INST_m_axi_arlen_UNCONNECTED(7 downto 0), + m_axi_arlock(0) => NLW_FIFO_INST_m_axi_arlock_UNCONNECTED(0), + m_axi_arprot(2 downto 0) => NLW_FIFO_INST_m_axi_arprot_UNCONNECTED(2 downto 0), + m_axi_arqos(3 downto 0) => NLW_FIFO_INST_m_axi_arqos_UNCONNECTED(3 downto 0), + m_axi_arready => '0', + m_axi_arregion(3 downto 0) => NLW_FIFO_INST_m_axi_arregion_UNCONNECTED(3 downto 0), + m_axi_arsize(2 downto 0) => NLW_FIFO_INST_m_axi_arsize_UNCONNECTED(2 downto 0), + m_axi_aruser(0) => NLW_FIFO_INST_m_axi_aruser_UNCONNECTED(0), + m_axi_arvalid => NLW_FIFO_INST_m_axi_arvalid_UNCONNECTED, + m_axi_awaddr(31 downto 0) => NLW_FIFO_INST_m_axi_awaddr_UNCONNECTED(31 downto 0), + m_axi_awburst(1 downto 0) => NLW_FIFO_INST_m_axi_awburst_UNCONNECTED(1 downto 0), + m_axi_awcache(3 downto 0) => NLW_FIFO_INST_m_axi_awcache_UNCONNECTED(3 downto 0), + m_axi_awid(0) => NLW_FIFO_INST_m_axi_awid_UNCONNECTED(0), + m_axi_awlen(7 downto 0) => NLW_FIFO_INST_m_axi_awlen_UNCONNECTED(7 downto 0), + m_axi_awlock(0) => NLW_FIFO_INST_m_axi_awlock_UNCONNECTED(0), + m_axi_awprot(2 downto 0) => NLW_FIFO_INST_m_axi_awprot_UNCONNECTED(2 downto 0), + m_axi_awqos(3 downto 0) => NLW_FIFO_INST_m_axi_awqos_UNCONNECTED(3 downto 0), + m_axi_awready => '0', + m_axi_awregion(3 downto 0) => NLW_FIFO_INST_m_axi_awregion_UNCONNECTED(3 downto 0), + m_axi_awsize(2 downto 0) => NLW_FIFO_INST_m_axi_awsize_UNCONNECTED(2 downto 0), + m_axi_awuser(0) => NLW_FIFO_INST_m_axi_awuser_UNCONNECTED(0), + m_axi_awvalid => NLW_FIFO_INST_m_axi_awvalid_UNCONNECTED, + m_axi_bid(0) => '0', + m_axi_bready => NLW_FIFO_INST_m_axi_bready_UNCONNECTED, + m_axi_bresp(1 downto 0) => B"00", + m_axi_buser(0) => '0', + m_axi_bvalid => '0', + m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + m_axi_rid(0) => '0', + m_axi_rlast => '0', + m_axi_rready => NLW_FIFO_INST_m_axi_rready_UNCONNECTED, + m_axi_rresp(1 downto 0) => B"00", + m_axi_ruser(0) => '0', + m_axi_rvalid => '0', + m_axi_wdata(63 downto 0) => NLW_FIFO_INST_m_axi_wdata_UNCONNECTED(63 downto 0), + m_axi_wid(0) => NLW_FIFO_INST_m_axi_wid_UNCONNECTED(0), + m_axi_wlast => NLW_FIFO_INST_m_axi_wlast_UNCONNECTED, + m_axi_wready => '0', + m_axi_wstrb(7 downto 0) => NLW_FIFO_INST_m_axi_wstrb_UNCONNECTED(7 downto 0), + m_axi_wuser(0) => NLW_FIFO_INST_m_axi_wuser_UNCONNECTED(0), + m_axi_wvalid => NLW_FIFO_INST_m_axi_wvalid_UNCONNECTED, + m_axis_tdata(7 downto 0) => NLW_FIFO_INST_m_axis_tdata_UNCONNECTED(7 downto 0), + m_axis_tdest(0) => NLW_FIFO_INST_m_axis_tdest_UNCONNECTED(0), + m_axis_tid(0) => NLW_FIFO_INST_m_axis_tid_UNCONNECTED(0), + m_axis_tkeep(0) => NLW_FIFO_INST_m_axis_tkeep_UNCONNECTED(0), + m_axis_tlast => NLW_FIFO_INST_m_axis_tlast_UNCONNECTED, + m_axis_tready => '0', + m_axis_tstrb(0) => NLW_FIFO_INST_m_axis_tstrb_UNCONNECTED(0), + m_axis_tuser(3 downto 0) => NLW_FIFO_INST_m_axis_tuser_UNCONNECTED(3 downto 0), + m_axis_tvalid => NLW_FIFO_INST_m_axis_tvalid_UNCONNECTED, + overflow => overflow, + prog_empty => NLW_FIFO_INST_prog_empty_UNCONNECTED, + prog_empty_thresh(11 downto 0) => B"000000000000", + prog_empty_thresh_assert(11 downto 0) => B"000000000000", + prog_empty_thresh_negate(11 downto 0) => B"000000000000", + prog_full => NLW_FIFO_INST_prog_full_UNCONNECTED, + prog_full_thresh(11 downto 0) => B"000000000000", + prog_full_thresh_assert(11 downto 0) => B"000000000000", + prog_full_thresh_negate(11 downto 0) => B"000000000000", + rd_clk => aclk, + rd_data_count(12 downto 0) => NLW_FIFO_INST_rd_data_count_UNCONNECTED(12 downto 0), + rd_en => \rd_en_i__0\, + rd_rst => '0', + rd_rst_busy => NLW_FIFO_INST_rd_rst_busy_UNCONNECTED, + rst => FIFO_INST_i_1_n_0, + s_aclk => '0', + s_aclk_en => '0', + s_aresetn => '0', + s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", + s_axi_arburst(1 downto 0) => B"00", + s_axi_arcache(3 downto 0) => B"0000", + s_axi_arid(0) => '0', + s_axi_arlen(7 downto 0) => B"00000000", + s_axi_arlock(0) => '0', + s_axi_arprot(2 downto 0) => B"000", + s_axi_arqos(3 downto 0) => B"0000", + s_axi_arready => NLW_FIFO_INST_s_axi_arready_UNCONNECTED, + s_axi_arregion(3 downto 0) => B"0000", + s_axi_arsize(2 downto 0) => B"000", + s_axi_aruser(0) => '0', + s_axi_arvalid => '0', + s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", + s_axi_awburst(1 downto 0) => B"00", + s_axi_awcache(3 downto 0) => B"0000", + s_axi_awid(0) => '0', + s_axi_awlen(7 downto 0) => B"00000000", + s_axi_awlock(0) => '0', + s_axi_awprot(2 downto 0) => B"000", + s_axi_awqos(3 downto 0) => B"0000", + s_axi_awready => NLW_FIFO_INST_s_axi_awready_UNCONNECTED, + s_axi_awregion(3 downto 0) => B"0000", + s_axi_awsize(2 downto 0) => B"000", + s_axi_awuser(0) => '0', + s_axi_awvalid => '0', + s_axi_bid(0) => NLW_FIFO_INST_s_axi_bid_UNCONNECTED(0), + s_axi_bready => '0', + s_axi_bresp(1 downto 0) => NLW_FIFO_INST_s_axi_bresp_UNCONNECTED(1 downto 0), + s_axi_buser(0) => NLW_FIFO_INST_s_axi_buser_UNCONNECTED(0), + s_axi_bvalid => NLW_FIFO_INST_s_axi_bvalid_UNCONNECTED, + s_axi_rdata(63 downto 0) => NLW_FIFO_INST_s_axi_rdata_UNCONNECTED(63 downto 0), + s_axi_rid(0) => NLW_FIFO_INST_s_axi_rid_UNCONNECTED(0), + s_axi_rlast => NLW_FIFO_INST_s_axi_rlast_UNCONNECTED, + s_axi_rready => '0', + s_axi_rresp(1 downto 0) => NLW_FIFO_INST_s_axi_rresp_UNCONNECTED(1 downto 0), + s_axi_ruser(0) => NLW_FIFO_INST_s_axi_ruser_UNCONNECTED(0), + s_axi_rvalid => NLW_FIFO_INST_s_axi_rvalid_UNCONNECTED, + s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + s_axi_wid(0) => '0', + s_axi_wlast => '0', + s_axi_wready => NLW_FIFO_INST_s_axi_wready_UNCONNECTED, + s_axi_wstrb(7 downto 0) => B"00000000", + s_axi_wuser(0) => '0', + s_axi_wvalid => '0', + s_axis_tdata(7 downto 0) => B"00000000", + s_axis_tdest(0) => '0', + s_axis_tid(0) => '0', + s_axis_tkeep(0) => '0', + s_axis_tlast => '0', + s_axis_tready => NLW_FIFO_INST_s_axis_tready_UNCONNECTED, + s_axis_tstrb(0) => '0', + s_axis_tuser(3 downto 0) => B"0000", + s_axis_tvalid => '0', + sbiterr => NLW_FIFO_INST_sbiterr_UNCONNECTED, + sleep => '0', + srst => '0', + underflow => underflow, + valid => \^m_axis_video_tvalid\, + wr_ack => NLW_FIFO_INST_wr_ack_UNCONNECTED, + wr_clk => vid_io_in_clk, + wr_data_count(12 downto 0) => NLW_FIFO_INST_wr_data_count_UNCONNECTED(12 downto 0), + wr_en => \wr_en_i__0\, + wr_rst => '0', + wr_rst_busy => wr_rst_busy_i + ); +FIFO_INST_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => vid_io_in_reset, + I1 => aresetn, + O => FIFO_INST_i_1_n_0 + ); +rd_en_i: unisim.vcomponents.LUT4 + generic map( + INIT => X"2000" + ) + port map ( + I0 => aclken, + I1 => empty_i, + I2 => \^m_axis_video_tvalid\, + I3 => m_axis_video_tready, + O => \rd_en_i__0\ + ); +wr_en_i: unisim.vcomponents.LUT5 + generic map( + INIT => X"10000000" + ) + port map ( + I0 => wr_rst_busy_i, + I1 => vid_io_in_reset, + I2 => de_3, + I3 => vtd_locked_reg, + I4 => vid_io_in_ce, + O => \wr_en_i__0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0_v_vid_in_axi4s_v4_0_5 is + port ( + vid_io_in_clk : in STD_LOGIC; + vid_io_in_ce : in STD_LOGIC; + vid_io_in_reset : in STD_LOGIC; + vid_active_video : in STD_LOGIC; + vid_vblank : in STD_LOGIC; + vid_hblank : in STD_LOGIC; + vid_vsync : in STD_LOGIC; + vid_hsync : in STD_LOGIC; + vid_field_id : in STD_LOGIC; + vid_data : in STD_LOGIC_VECTOR ( 23 downto 0 ); + aclk : in STD_LOGIC; + aclken : in STD_LOGIC; + aresetn : in STD_LOGIC; + m_axis_video_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 ); + m_axis_video_tvalid : out STD_LOGIC; + m_axis_video_tready : in STD_LOGIC; + m_axis_video_tuser : out STD_LOGIC; + m_axis_video_tlast : out STD_LOGIC; + fid : out STD_LOGIC; + vtd_active_video : out STD_LOGIC; + vtd_vblank : out STD_LOGIC; + vtd_hblank : out STD_LOGIC; + vtd_vsync : out STD_LOGIC; + vtd_hsync : out STD_LOGIC; + vtd_field_id : out STD_LOGIC; + overflow : out STD_LOGIC; + underflow : out STD_LOGIC; + axis_enable : in STD_LOGIC + ); + attribute C_ADDR_WIDTH : integer; + attribute C_ADDR_WIDTH of Arty_Z7_20_v_vid_in_axi4s_0_0_v_vid_in_axi4s_v4_0_5 : entity is 12; + attribute C_COMPONENTS_PER_PIXEL : integer; + attribute C_COMPONENTS_PER_PIXEL of Arty_Z7_20_v_vid_in_axi4s_0_0_v_vid_in_axi4s_v4_0_5 : entity is 3; + attribute C_FAMILY : string; + attribute C_FAMILY of Arty_Z7_20_v_vid_in_axi4s_0_0_v_vid_in_axi4s_v4_0_5 : entity is "zynq"; + attribute C_HAS_ASYNC_CLK : integer; + attribute C_HAS_ASYNC_CLK of Arty_Z7_20_v_vid_in_axi4s_0_0_v_vid_in_axi4s_v4_0_5 : entity is 1; + attribute C_M_AXIS_COMPONENT_WIDTH : integer; + attribute C_M_AXIS_COMPONENT_WIDTH of Arty_Z7_20_v_vid_in_axi4s_0_0_v_vid_in_axi4s_v4_0_5 : entity is 8; + attribute C_M_AXIS_TDATA_WIDTH : integer; + attribute C_M_AXIS_TDATA_WIDTH of Arty_Z7_20_v_vid_in_axi4s_0_0_v_vid_in_axi4s_v4_0_5 : entity is 24; + attribute C_NATIVE_COMPONENT_WIDTH : integer; + attribute C_NATIVE_COMPONENT_WIDTH of Arty_Z7_20_v_vid_in_axi4s_0_0_v_vid_in_axi4s_v4_0_5 : entity is 8; + attribute C_NATIVE_DATA_WIDTH : integer; + attribute C_NATIVE_DATA_WIDTH of Arty_Z7_20_v_vid_in_axi4s_0_0_v_vid_in_axi4s_v4_0_5 : entity is 24; + attribute C_PIXELS_PER_CLOCK : integer; + attribute C_PIXELS_PER_CLOCK of Arty_Z7_20_v_vid_in_axi4s_0_0_v_vid_in_axi4s_v4_0_5 : entity is 1; + attribute DowngradeIPIdentifiedWarnings : string; + attribute DowngradeIPIdentifiedWarnings of Arty_Z7_20_v_vid_in_axi4s_0_0_v_vid_in_axi4s_v4_0_5 : entity is "yes"; +end Arty_Z7_20_v_vid_in_axi4s_0_0_v_vid_in_axi4s_v4_0_5; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0_v_vid_in_axi4s_v4_0_5 is + signal FORMATTER_INST_n_34 : STD_LOGIC; + signal de_3 : STD_LOGIC; + signal idf_data : STD_LOGIC_VECTOR ( 26 downto 0 ); +begin +COUPLER_INST: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_v_vid_in_axi4s_v4_0_5_coupler + port map ( + FIFO_WR_DATA(26 downto 0) => idf_data(26 downto 0), + aclk => aclk, + aclken => aclken, + aresetn => aresetn, + de_3 => de_3, + dout(26) => fid, + dout(25) => m_axis_video_tuser, + dout(24) => m_axis_video_tlast, + dout(23 downto 0) => m_axis_video_tdata(23 downto 0), + m_axis_video_tready => m_axis_video_tready, + m_axis_video_tvalid => m_axis_video_tvalid, + overflow => overflow, + underflow => underflow, + vid_io_in_ce => vid_io_in_ce, + vid_io_in_clk => vid_io_in_clk, + vid_io_in_reset => vid_io_in_reset, + vtd_locked_reg => FORMATTER_INST_n_34 + ); +FORMATTER_INST: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_v_vid_in_axi4s_v4_0_5_formatter + port map ( + FIFO_WR_DATA(26 downto 0) => idf_data(26 downto 0), + axis_enable => axis_enable, + de_3 => de_3, + vid_active_video => vid_active_video, + vid_data(23 downto 0) => vid_data(23 downto 0), + vid_field_id => vid_field_id, + vid_hblank => vid_hblank, + vid_hsync => vid_hsync, + vid_io_in_ce => vid_io_in_ce, + vid_io_in_clk => vid_io_in_clk, + vid_io_in_reset => vid_io_in_reset, + vid_vblank => vid_vblank, + vid_vsync => vid_vsync, + vtd_active_video => vtd_active_video, + vtd_field_id => vtd_field_id, + vtd_hblank => vtd_hblank, + vtd_hsync => vtd_hsync, + vtd_locked_reg_0 => FORMATTER_INST_n_34, + vtd_vblank => vtd_vblank, + vtd_vsync => vtd_vsync + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_v_vid_in_axi4s_0_0 is + port ( + vid_io_in_clk : in STD_LOGIC; + vid_io_in_ce : in STD_LOGIC; + vid_io_in_reset : in STD_LOGIC; + vid_active_video : in STD_LOGIC; + vid_vblank : in STD_LOGIC; + vid_hblank : in STD_LOGIC; + vid_vsync : in STD_LOGIC; + vid_hsync : in STD_LOGIC; + vid_field_id : in STD_LOGIC; + vid_data : in STD_LOGIC_VECTOR ( 23 downto 0 ); + aclk : in STD_LOGIC; + aclken : in STD_LOGIC; + aresetn : in STD_LOGIC; + m_axis_video_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 ); + m_axis_video_tvalid : out STD_LOGIC; + m_axis_video_tready : in STD_LOGIC; + m_axis_video_tuser : out STD_LOGIC; + m_axis_video_tlast : out STD_LOGIC; + fid : out STD_LOGIC; + vtd_active_video : out STD_LOGIC; + vtd_vblank : out STD_LOGIC; + vtd_hblank : out STD_LOGIC; + vtd_vsync : out STD_LOGIC; + vtd_hsync : out STD_LOGIC; + vtd_field_id : out STD_LOGIC; + overflow : out STD_LOGIC; + underflow : out STD_LOGIC; + axis_enable : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of Arty_Z7_20_v_vid_in_axi4s_0_0 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of Arty_Z7_20_v_vid_in_axi4s_0_0 : entity is "Arty_Z7_20_v_vid_in_axi4s_0_0,v_vid_in_axi4s_v4_0_5,{}"; + attribute DowngradeIPIdentifiedWarnings : string; + attribute DowngradeIPIdentifiedWarnings of Arty_Z7_20_v_vid_in_axi4s_0_0 : entity is "yes"; + attribute X_CORE_INFO : string; + attribute X_CORE_INFO of Arty_Z7_20_v_vid_in_axi4s_0_0 : entity is "v_vid_in_axi4s_v4_0_5,Vivado 2016.4"; +end Arty_Z7_20_v_vid_in_axi4s_0_0; + +architecture STRUCTURE of Arty_Z7_20_v_vid_in_axi4s_0_0 is + attribute C_ADDR_WIDTH : integer; + attribute C_ADDR_WIDTH of inst : label is 12; + attribute C_COMPONENTS_PER_PIXEL : integer; + attribute C_COMPONENTS_PER_PIXEL of inst : label is 3; + attribute C_FAMILY : string; + attribute C_FAMILY of inst : label is "zynq"; + attribute C_HAS_ASYNC_CLK : integer; + attribute C_HAS_ASYNC_CLK of inst : label is 1; + attribute C_M_AXIS_COMPONENT_WIDTH : integer; + attribute C_M_AXIS_COMPONENT_WIDTH of inst : label is 8; + attribute C_M_AXIS_TDATA_WIDTH : integer; + attribute C_M_AXIS_TDATA_WIDTH of inst : label is 24; + attribute C_NATIVE_COMPONENT_WIDTH : integer; + attribute C_NATIVE_COMPONENT_WIDTH of inst : label is 8; + attribute C_NATIVE_DATA_WIDTH : integer; + attribute C_NATIVE_DATA_WIDTH of inst : label is 24; + attribute C_PIXELS_PER_CLOCK : integer; + attribute C_PIXELS_PER_CLOCK of inst : label is 1; + attribute DowngradeIPIdentifiedWarnings of inst : label is "yes"; +begin +inst: entity work.Arty_Z7_20_v_vid_in_axi4s_0_0_v_vid_in_axi4s_v4_0_5 + port map ( + aclk => aclk, + aclken => aclken, + aresetn => aresetn, + axis_enable => axis_enable, + fid => fid, + m_axis_video_tdata(23 downto 0) => m_axis_video_tdata(23 downto 0), + m_axis_video_tlast => m_axis_video_tlast, + m_axis_video_tready => m_axis_video_tready, + m_axis_video_tuser => m_axis_video_tuser, + m_axis_video_tvalid => m_axis_video_tvalid, + overflow => overflow, + underflow => underflow, + vid_active_video => vid_active_video, + vid_data(23 downto 0) => vid_data(23 downto 0), + vid_field_id => vid_field_id, + vid_hblank => vid_hblank, + vid_hsync => vid_hsync, + vid_io_in_ce => vid_io_in_ce, + vid_io_in_clk => vid_io_in_clk, + vid_io_in_reset => vid_io_in_reset, + vid_vblank => vid_vblank, + vid_vsync => vid_vsync, + vtd_active_video => vtd_active_video, + vtd_field_id => vtd_field_id, + vtd_hblank => vtd_hblank, + vtd_hsync => vtd_hsync, + vtd_vblank => vtd_vblank, + vtd_vsync => vtd_vsync + ); +end STRUCTURE; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/Arty_Z7_20_v_vid_in_axi4s_0_0_stub.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/Arty_Z7_20_v_vid_in_axi4s_0_0_stub.v new file mode 100644 index 0000000..79631db --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/Arty_Z7_20_v_vid_in_axi4s_0_0_stub.v @@ -0,0 +1,51 @@ +// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +// Date : Sat Mar 04 18:56:32 2017 +// Host : WK73 running 64-bit Service Pack 1 (build 7601) +// Command : write_verilog -force -mode synth_stub -rename_top Arty_Z7_20_v_vid_in_axi4s_0_0 -prefix +// Arty_Z7_20_v_vid_in_axi4s_0_0_ Arty_Z7_20_v_vid_in_axi4s_0_0_stub.v +// Design : Arty_Z7_20_v_vid_in_axi4s_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg400-1 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "v_vid_in_axi4s_v4_0_5,Vivado 2016.4" *) +module Arty_Z7_20_v_vid_in_axi4s_0_0(vid_io_in_clk, vid_io_in_ce, vid_io_in_reset, + vid_active_video, vid_vblank, vid_hblank, vid_vsync, vid_hsync, vid_field_id, vid_data, aclk, + aclken, aresetn, m_axis_video_tdata, m_axis_video_tvalid, m_axis_video_tready, + m_axis_video_tuser, m_axis_video_tlast, fid, vtd_active_video, vtd_vblank, vtd_hblank, + vtd_vsync, vtd_hsync, vtd_field_id, overflow, underflow, axis_enable) +/* synthesis syn_black_box black_box_pad_pin="vid_io_in_clk,vid_io_in_ce,vid_io_in_reset,vid_active_video,vid_vblank,vid_hblank,vid_vsync,vid_hsync,vid_field_id,vid_data[23:0],aclk,aclken,aresetn,m_axis_video_tdata[23:0],m_axis_video_tvalid,m_axis_video_tready,m_axis_video_tuser,m_axis_video_tlast,fid,vtd_active_video,vtd_vblank,vtd_hblank,vtd_vsync,vtd_hsync,vtd_field_id,overflow,underflow,axis_enable" */; + input vid_io_in_clk; + input vid_io_in_ce; + input vid_io_in_reset; + input vid_active_video; + input vid_vblank; + input vid_hblank; + input vid_vsync; + input vid_hsync; + input vid_field_id; + input [23:0]vid_data; + input aclk; + input aclken; + input aresetn; + output [23:0]m_axis_video_tdata; + output m_axis_video_tvalid; + input m_axis_video_tready; + output m_axis_video_tuser; + output m_axis_video_tlast; + output fid; + output vtd_active_video; + output vtd_vblank; + output vtd_hblank; + output vtd_vsync; + output vtd_hsync; + output vtd_field_id; + output overflow; + output underflow; + input axis_enable; +endmodule diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/Arty_Z7_20_v_vid_in_axi4s_0_0_stub.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/Arty_Z7_20_v_vid_in_axi4s_0_0_stub.vhdl new file mode 100644 index 0000000..d01891a --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/Arty_Z7_20_v_vid_in_axi4s_0_0_stub.vhdl @@ -0,0 +1,57 @@ +-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +-- Date : Sat Mar 04 18:56:32 2017 +-- Host : WK73 running 64-bit Service Pack 1 (build 7601) +-- Command : write_vhdl -force -mode synth_stub -rename_top Arty_Z7_20_v_vid_in_axi4s_0_0 -prefix +-- Arty_Z7_20_v_vid_in_axi4s_0_0_ Arty_Z7_20_v_vid_in_axi4s_0_0_stub.vhdl +-- Design : Arty_Z7_20_v_vid_in_axi4s_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg400-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Arty_Z7_20_v_vid_in_axi4s_0_0 is + Port ( + vid_io_in_clk : in STD_LOGIC; + vid_io_in_ce : in STD_LOGIC; + vid_io_in_reset : in STD_LOGIC; + vid_active_video : in STD_LOGIC; + vid_vblank : in STD_LOGIC; + vid_hblank : in STD_LOGIC; + vid_vsync : in STD_LOGIC; + vid_hsync : in STD_LOGIC; + vid_field_id : in STD_LOGIC; + vid_data : in STD_LOGIC_VECTOR ( 23 downto 0 ); + aclk : in STD_LOGIC; + aclken : in STD_LOGIC; + aresetn : in STD_LOGIC; + m_axis_video_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 ); + m_axis_video_tvalid : out STD_LOGIC; + m_axis_video_tready : in STD_LOGIC; + m_axis_video_tuser : out STD_LOGIC; + m_axis_video_tlast : out STD_LOGIC; + fid : out STD_LOGIC; + vtd_active_video : out STD_LOGIC; + vtd_vblank : out STD_LOGIC; + vtd_hblank : out STD_LOGIC; + vtd_vsync : out STD_LOGIC; + vtd_hsync : out STD_LOGIC; + vtd_field_id : out STD_LOGIC; + overflow : out STD_LOGIC; + underflow : out STD_LOGIC; + axis_enable : in STD_LOGIC + ); + +end Arty_Z7_20_v_vid_in_axi4s_0_0; + +architecture stub of Arty_Z7_20_v_vid_in_axi4s_0_0 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "vid_io_in_clk,vid_io_in_ce,vid_io_in_reset,vid_active_video,vid_vblank,vid_hblank,vid_vsync,vid_hsync,vid_field_id,vid_data[23:0],aclk,aclken,aresetn,m_axis_video_tdata[23:0],m_axis_video_tvalid,m_axis_video_tready,m_axis_video_tuser,m_axis_video_tlast,fid,vtd_active_video,vtd_vblank,vtd_hblank,vtd_vsync,vtd_hsync,vtd_field_id,overflow,underflow,axis_enable"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "v_vid_in_axi4s_v4_0_5,Vivado 2016.4"; +begin +end; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/sim/Arty_Z7_20_v_vid_in_axi4s_0_0.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/sim/Arty_Z7_20_v_vid_in_axi4s_0_0.v new file mode 100644 index 0000000..7506745 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/sim/Arty_Z7_20_v_vid_in_axi4s_0_0.v @@ -0,0 +1,180 @@ +// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:v_vid_in_axi4s:4.0 +// IP Revision: 5 + +`timescale 1ns/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module Arty_Z7_20_v_vid_in_axi4s_0_0 ( + vid_io_in_clk, + vid_io_in_ce, + vid_io_in_reset, + vid_active_video, + vid_vblank, + vid_hblank, + vid_vsync, + vid_hsync, + vid_field_id, + vid_data, + aclk, + aclken, + aresetn, + m_axis_video_tdata, + m_axis_video_tvalid, + m_axis_video_tready, + m_axis_video_tuser, + m_axis_video_tlast, + fid, + vtd_active_video, + vtd_vblank, + vtd_hblank, + vtd_vsync, + vtd_hsync, + vtd_field_id, + overflow, + underflow, + axis_enable +); + +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 vid_io_in_clk_intf CLK" *) +input wire vid_io_in_clk; +(* X_INTERFACE_INFO = "xilinx.com:signal:clockenable:1.0 vid_io_in_ce_intf CE" *) +input wire vid_io_in_ce; +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 vid_io_in_reset_intf RST" *) +input wire vid_io_in_reset; +(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 vid_io_in ACTIVE_VIDEO" *) +input wire vid_active_video; +(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 vid_io_in VBLANK" *) +input wire vid_vblank; +(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 vid_io_in HBLANK" *) +input wire vid_hblank; +(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 vid_io_in VSYNC" *) +input wire vid_vsync; +(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 vid_io_in HSYNC" *) +input wire vid_hsync; +(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 vid_io_in FIELD" *) +input wire vid_field_id; +(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 vid_io_in DATA" *) +input wire [23 : 0] vid_data; +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk_intf CLK" *) +input wire aclk; +(* X_INTERFACE_INFO = "xilinx.com:signal:clockenable:1.0 aclken_intf CE" *) +input wire aclken; +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn_intf RST" *) +input wire aresetn; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 video_out TDATA" *) +output wire [23 : 0] m_axis_video_tdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 video_out TVALID" *) +output wire m_axis_video_tvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 video_out TREADY" *) +input wire m_axis_video_tready; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 video_out TUSER" *) +output wire m_axis_video_tuser; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 video_out TLAST" *) +output wire m_axis_video_tlast; +output wire fid; +(* X_INTERFACE_INFO = "xilinx.com:interface:video_timing:2.0 vtiming_out ACTIVE_VIDEO" *) +output wire vtd_active_video; +(* X_INTERFACE_INFO = "xilinx.com:interface:video_timing:2.0 vtiming_out VBLANK" *) +output wire vtd_vblank; +(* X_INTERFACE_INFO = "xilinx.com:interface:video_timing:2.0 vtiming_out HBLANK" *) +output wire vtd_hblank; +(* X_INTERFACE_INFO = "xilinx.com:interface:video_timing:2.0 vtiming_out VSYNC" *) +output wire vtd_vsync; +(* X_INTERFACE_INFO = "xilinx.com:interface:video_timing:2.0 vtiming_out HSYNC" *) +output wire vtd_hsync; +(* X_INTERFACE_INFO = "xilinx.com:interface:video_timing:2.0 vtiming_out FIELD" *) +output wire vtd_field_id; +output wire overflow; +output wire underflow; +input wire axis_enable; + + v_vid_in_axi4s_v4_0_5 #( + .C_FAMILY("zynq"), + .C_PIXELS_PER_CLOCK(1), + .C_COMPONENTS_PER_PIXEL(3), + .C_M_AXIS_COMPONENT_WIDTH(8), + .C_NATIVE_COMPONENT_WIDTH(8), + .C_NATIVE_DATA_WIDTH(24), + .C_M_AXIS_TDATA_WIDTH(24), + .C_HAS_ASYNC_CLK(1), + .C_ADDR_WIDTH(12) + ) inst ( + .vid_io_in_clk(vid_io_in_clk), + .vid_io_in_ce(vid_io_in_ce), + .vid_io_in_reset(vid_io_in_reset), + .vid_active_video(vid_active_video), + .vid_vblank(vid_vblank), + .vid_hblank(vid_hblank), + .vid_vsync(vid_vsync), + .vid_hsync(vid_hsync), + .vid_field_id(vid_field_id), + .vid_data(vid_data), + .aclk(aclk), + .aclken(aclken), + .aresetn(aresetn), + .m_axis_video_tdata(m_axis_video_tdata), + .m_axis_video_tvalid(m_axis_video_tvalid), + .m_axis_video_tready(m_axis_video_tready), + .m_axis_video_tuser(m_axis_video_tuser), + .m_axis_video_tlast(m_axis_video_tlast), + .fid(fid), + .vtd_active_video(vtd_active_video), + .vtd_vblank(vtd_vblank), + .vtd_hblank(vtd_hblank), + .vtd_vsync(vtd_vsync), + .vtd_hsync(vtd_hsync), + .vtd_field_id(vtd_field_id), + .overflow(overflow), + .underflow(underflow), + .axis_enable(axis_enable) + ); +endmodule diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/synth/Arty_Z7_20_v_vid_in_axi4s_0_0.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/synth/Arty_Z7_20_v_vid_in_axi4s_0_0.v new file mode 100644 index 0000000..a731341 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_v_vid_in_axi4s_0_0/synth/Arty_Z7_20_v_vid_in_axi4s_0_0.v @@ -0,0 +1,181 @@ +// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:v_vid_in_axi4s:4.0 +// IP Revision: 5 + +(* X_CORE_INFO = "v_vid_in_axi4s_v4_0_5,Vivado 2016.4" *) +(* CHECK_LICENSE_TYPE = "Arty_Z7_20_v_vid_in_axi4s_0_0,v_vid_in_axi4s_v4_0_5,{}" *) +(* CORE_GENERATION_INFO = "Arty_Z7_20_v_vid_in_axi4s_0_0,v_vid_in_axi4s_v4_0_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=v_vid_in_axi4s,x_ipVersion=4.0,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_PIXELS_PER_CLOCK=1,C_COMPONENTS_PER_PIXEL=3,C_M_AXIS_COMPONENT_WIDTH=8,C_NATIVE_COMPONENT_WIDTH=8,C_NATIVE_DATA_WIDTH=24,C_M_AXIS_TDATA_WIDTH=24,C_HAS_ASYNC_CLK=1,C_ADDR_WIDTH=12}" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module Arty_Z7_20_v_vid_in_axi4s_0_0 ( + vid_io_in_clk, + vid_io_in_ce, + vid_io_in_reset, + vid_active_video, + vid_vblank, + vid_hblank, + vid_vsync, + vid_hsync, + vid_field_id, + vid_data, + aclk, + aclken, + aresetn, + m_axis_video_tdata, + m_axis_video_tvalid, + m_axis_video_tready, + m_axis_video_tuser, + m_axis_video_tlast, + fid, + vtd_active_video, + vtd_vblank, + vtd_hblank, + vtd_vsync, + vtd_hsync, + vtd_field_id, + overflow, + underflow, + axis_enable +); + +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 vid_io_in_clk_intf CLK" *) +input wire vid_io_in_clk; +(* X_INTERFACE_INFO = "xilinx.com:signal:clockenable:1.0 vid_io_in_ce_intf CE" *) +input wire vid_io_in_ce; +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 vid_io_in_reset_intf RST" *) +input wire vid_io_in_reset; +(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 vid_io_in ACTIVE_VIDEO" *) +input wire vid_active_video; +(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 vid_io_in VBLANK" *) +input wire vid_vblank; +(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 vid_io_in HBLANK" *) +input wire vid_hblank; +(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 vid_io_in VSYNC" *) +input wire vid_vsync; +(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 vid_io_in HSYNC" *) +input wire vid_hsync; +(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 vid_io_in FIELD" *) +input wire vid_field_id; +(* X_INTERFACE_INFO = "xilinx.com:interface:vid_io:1.0 vid_io_in DATA" *) +input wire [23 : 0] vid_data; +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk_intf CLK" *) +input wire aclk; +(* X_INTERFACE_INFO = "xilinx.com:signal:clockenable:1.0 aclken_intf CE" *) +input wire aclken; +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn_intf RST" *) +input wire aresetn; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 video_out TDATA" *) +output wire [23 : 0] m_axis_video_tdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 video_out TVALID" *) +output wire m_axis_video_tvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 video_out TREADY" *) +input wire m_axis_video_tready; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 video_out TUSER" *) +output wire m_axis_video_tuser; +(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 video_out TLAST" *) +output wire m_axis_video_tlast; +output wire fid; +(* X_INTERFACE_INFO = "xilinx.com:interface:video_timing:2.0 vtiming_out ACTIVE_VIDEO" *) +output wire vtd_active_video; +(* X_INTERFACE_INFO = "xilinx.com:interface:video_timing:2.0 vtiming_out VBLANK" *) +output wire vtd_vblank; +(* X_INTERFACE_INFO = "xilinx.com:interface:video_timing:2.0 vtiming_out HBLANK" *) +output wire vtd_hblank; +(* X_INTERFACE_INFO = "xilinx.com:interface:video_timing:2.0 vtiming_out VSYNC" *) +output wire vtd_vsync; +(* X_INTERFACE_INFO = "xilinx.com:interface:video_timing:2.0 vtiming_out HSYNC" *) +output wire vtd_hsync; +(* X_INTERFACE_INFO = "xilinx.com:interface:video_timing:2.0 vtiming_out FIELD" *) +output wire vtd_field_id; +output wire overflow; +output wire underflow; +input wire axis_enable; + + v_vid_in_axi4s_v4_0_5 #( + .C_FAMILY("zynq"), + .C_PIXELS_PER_CLOCK(1), + .C_COMPONENTS_PER_PIXEL(3), + .C_M_AXIS_COMPONENT_WIDTH(8), + .C_NATIVE_COMPONENT_WIDTH(8), + .C_NATIVE_DATA_WIDTH(24), + .C_M_AXIS_TDATA_WIDTH(24), + .C_HAS_ASYNC_CLK(1), + .C_ADDR_WIDTH(12) + ) inst ( + .vid_io_in_clk(vid_io_in_clk), + .vid_io_in_ce(vid_io_in_ce), + .vid_io_in_reset(vid_io_in_reset), + .vid_active_video(vid_active_video), + .vid_vblank(vid_vblank), + .vid_hblank(vid_hblank), + .vid_vsync(vid_vsync), + .vid_hsync(vid_hsync), + .vid_field_id(vid_field_id), + .vid_data(vid_data), + .aclk(aclk), + .aclken(aclken), + .aresetn(aresetn), + .m_axis_video_tdata(m_axis_video_tdata), + .m_axis_video_tvalid(m_axis_video_tvalid), + .m_axis_video_tready(m_axis_video_tready), + .m_axis_video_tuser(m_axis_video_tuser), + .m_axis_video_tlast(m_axis_video_tlast), + .fid(fid), + .vtd_active_video(vtd_active_video), + .vtd_vblank(vtd_vblank), + .vtd_hblank(vtd_hblank), + .vtd_vsync(vtd_vsync), + .vtd_hsync(vtd_hsync), + .vtd_field_id(vtd_field_id), + .overflow(overflow), + .underflow(underflow), + .axis_enable(axis_enable) + ); +endmodule diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0.dcp b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0.dcp index 6f5bc82..87923f7 100644 Binary files a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0.dcp and b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0.dcp differ diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0.xci b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0.xci index 6915203..7dd7e0d 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0.xci +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0.xci @@ -284,6 +284,66 @@ 0 0 0 + 32 + 0 + 0 + 0 + Arty_Z7_20_processing_system7_0_0_FCLK_CLK0 + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + Arty_Z7_20_processing_system7_0_0_FCLK_CLK0 + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 ACTIVE_LOW INTERCONNECT 32 @@ -328,15 +388,15 @@ 1 0 zynq - 0x000000100000001000000010000000100000001000000010000000100000001000000010 - 0x00000000412400000000000043c2000000000000412300000000000043c100000000000043c000000000000043000000000000004122000000000000412100000000000041200000 - 0x000000010000000100000001000000010000000100000001000000010000000100000001 - 0x000000010000000100000001000000010000000100000001000000010000000100000001 - 0x000000000000000000000000000000000000000000000000000000000000000000000000 - 0x000000010000000100000001000000010000000100000001000000010000000100000001 - 0x000000010000000100000001000000010000000100000001000000010000000100000001 + 0x0000001000000010000000100000001000000010000000100000001000000010000000100000001000000010 + 0x00000000412500000000000043c3000000000000412400000000000043c2000000000000412300000000000043c100000000000043c000000000000043000000000000004122000000000000412100000000000041200000 + 0x0000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 + 0x0000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 + 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + 0x0000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 + 0x0000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 1 - 9 + 11 1 1 0x00000000 @@ -966,8 +1026,8 @@ 1 0 1 - 0 - 0xffffffffffffffff + 16 + 0x0000000043C30000 0 0xffffffffffffffff 0 @@ -1034,8 +1094,8 @@ 1 0 1 - 0 - 0xffffffffffffffff + 16 + 0x0000000041250000 0 0xffffffffffffffff 0 @@ -1442,7 +1502,7 @@ 1 0 1 - 9 + 11 1 AXI4LITE 0 @@ -1714,6 +1774,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -1778,6 +1866,14 @@ + + + + + + + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0.xml b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0.xml index 6f3f386..62327f7 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0.xml +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0.xml @@ -12165,10 +12165,132 @@ + + + DATA_WIDTH + 32 + + + PROTOCOL + AXI4LITE + + + FREQ_HZ + 100000000 + + + ID_WIDTH + 0 + + + ADDR_WIDTH + 32 + + + AWUSER_WIDTH + 0 + + + ARUSER_WIDTH + 0 + + + WUSER_WIDTH + 0 + + + RUSER_WIDTH + 0 + + + BUSER_WIDTH + 0 + + + READ_WRITE_MODE + READ_WRITE + + + HAS_BURST + 0 + + + HAS_LOCK + 0 + + + HAS_PROT + 1 + + + HAS_CACHE + 0 + + + HAS_QOS + 0 + + + HAS_REGION + 0 + + + HAS_WSTRB + 1 + + + HAS_BRESP + 1 + + + HAS_RRESP + 1 + + + SUPPORTS_NARROW_BURST + 0 + + + NUM_READ_OUTSTANDING + 1 + + + NUM_WRITE_OUTSTANDING + 1 + + + MAX_BURST_LENGTH + 1 + + + PHASE + 0.000 + + + CLK_DOMAIN + Arty_Z7_20_processing_system7_0_0_FCLK_CLK0 + + + NUM_READ_THREADS + 1 + + + NUM_WRITE_THREADS + 1 + + + RUSER_BITS_PER_BYTE + 0 + + + WUSER_BITS_PER_BYTE + 0 + + - false + true @@ -13253,10 +13375,132 @@ + + + DATA_WIDTH + 32 + + + PROTOCOL + AXI4LITE + + + FREQ_HZ + 100000000 + + + ID_WIDTH + 0 + + + ADDR_WIDTH + 32 + + + AWUSER_WIDTH + 0 + + + ARUSER_WIDTH + 0 + + + WUSER_WIDTH + 0 + + + RUSER_WIDTH + 0 + + + BUSER_WIDTH + 0 + + + READ_WRITE_MODE + READ_WRITE + + + HAS_BURST + 0 + + + HAS_LOCK + 0 + + + HAS_PROT + 1 + + + HAS_CACHE + 0 + + + HAS_QOS + 0 + + + HAS_REGION + 0 + + + HAS_WSTRB + 1 + + + HAS_BRESP + 1 + + + HAS_RRESP + 1 + + + SUPPORTS_NARROW_BURST + 0 + + + NUM_READ_OUTSTANDING + 1 + + + NUM_WRITE_OUTSTANDING + 1 + + + MAX_BURST_LENGTH + 1 + + + PHASE + 0.000 + + + CLK_DOMAIN + Arty_Z7_20_processing_system7_0_0_FCLK_CLK0 + + + NUM_READ_THREADS + 1 + + + NUM_WRITE_THREADS + 1 + + + RUSER_BITS_PER_BYTE + 0 + + + WUSER_BITS_PER_BYTE + 0 + + - false + true @@ -18737,7 +18981,7 @@ boundaryCRC - 4b89b2c2 + 955970d6 boundaryCRCversion @@ -18745,7 +18989,7 @@ customizationCRC - 0b490ba8 + b018a0d2 customizationCRCversion @@ -18763,11 +19007,11 @@ GENtimestamp - Fri Feb 24 23:58:22 UTC 2017 + Sun Mar 05 02:51:32 UTC 2017 boundaryCRC - 4b89b2c2 + 955970d6 boundaryCRCversion @@ -18775,7 +19019,7 @@ customizationCRC - 0b490ba8 + b018a0d2 customizationCRCversion @@ -18794,11 +19038,11 @@ GENtimestamp - Fri Feb 24 23:58:22 UTC 2017 + Sun Mar 05 02:51:32 UTC 2017 boundaryCRC - 4b89b2c2 + 955970d6 boundaryCRCversion @@ -18806,7 +19050,7 @@ customizationCRC - 0b490ba8 + b018a0d2 customizationCRCversion @@ -18844,7 +19088,7 @@ boundaryCRC - 4b89b2c2 + 955970d6 boundaryCRCversion @@ -18852,7 +19096,7 @@ customizationCRC - 6ec31968 + ad27d890 customizationCRCversion @@ -18871,11 +19115,11 @@ GENtimestamp - Fri Feb 24 23:58:22 UTC 2017 + Sun Mar 05 02:51:32 UTC 2017 boundaryCRC - 4b89b2c2 + 955970d6 boundaryCRCversion @@ -18883,7 +19127,7 @@ customizationCRC - 6ec31968 + ad27d890 customizationCRCversion @@ -18901,11 +19145,11 @@ GENtimestamp - Sat Feb 25 00:02:41 UTC 2017 + Sun Mar 05 02:54:14 UTC 2017 boundaryCRC - 4b89b2c2 + 955970d6 boundaryCRCversion @@ -18913,7 +19157,7 @@ customizationCRC - 0b490ba8 + b018a0d2 customizationCRCversion @@ -19978,7 +20222,7 @@ out - 8 + 10 0 @@ -20002,7 +20246,7 @@ out - 287 + 351 0 @@ -20019,7 +20263,7 @@ out - 71 + 87 0 @@ -20043,7 +20287,7 @@ out - 26 + 32 0 @@ -20067,7 +20311,7 @@ out - 17 + 21 0 @@ -20091,7 +20335,7 @@ out - 8 + 10 0 @@ -20115,7 +20359,7 @@ out - 35 + 43 0 @@ -20139,7 +20383,7 @@ out - 26 + 32 0 @@ -20156,7 +20400,7 @@ out - 35 + 43 0 @@ -20180,7 +20424,7 @@ out - 35 + 43 0 @@ -20204,7 +20448,7 @@ out - 8 + 10 0 @@ -20228,7 +20472,7 @@ out - 8 + 10 0 @@ -20252,7 +20496,7 @@ in - 8 + 10 0 @@ -20272,7 +20516,7 @@ out - 8 + 10 0 @@ -20296,7 +20540,7 @@ out - 287 + 351 0 @@ -20313,7 +20557,7 @@ out - 35 + 43 0 @@ -20330,7 +20574,7 @@ out - 8 + 10 0 @@ -20354,7 +20598,7 @@ out - 8 + 10 0 @@ -20378,7 +20622,7 @@ out - 8 + 10 0 @@ -20402,7 +20646,7 @@ in - 8 + 10 0 @@ -20422,7 +20666,7 @@ in - 8 + 10 0 @@ -20449,7 +20693,7 @@ in - 17 + 21 0 @@ -20460,7 +20704,7 @@ - 0x00000 + 0x000000 @@ -20469,7 +20713,7 @@ in - 8 + 10 0 @@ -20496,7 +20740,7 @@ in - 8 + 10 0 @@ -20523,7 +20767,7 @@ out - 8 + 10 0 @@ -20540,7 +20784,7 @@ out - 8 + 10 0 @@ -20564,7 +20808,7 @@ out - 287 + 351 0 @@ -20581,7 +20825,7 @@ out - 71 + 87 0 @@ -20605,7 +20849,7 @@ out - 26 + 32 0 @@ -20629,7 +20873,7 @@ out - 17 + 21 0 @@ -20653,7 +20897,7 @@ out - 8 + 10 0 @@ -20677,7 +20921,7 @@ out - 35 + 43 0 @@ -20701,7 +20945,7 @@ out - 26 + 32 0 @@ -20718,7 +20962,7 @@ out - 35 + 43 0 @@ -20742,7 +20986,7 @@ out - 35 + 43 0 @@ -20766,7 +21010,7 @@ out - 8 + 10 0 @@ -20790,7 +21034,7 @@ out - 8 + 10 0 @@ -20814,7 +21058,7 @@ in - 8 + 10 0 @@ -20834,7 +21078,7 @@ in - 8 + 10 0 @@ -20861,7 +21105,7 @@ in - 287 + 351 0 @@ -20872,7 +21116,7 @@ - 0x000000000000000000000000000000000000000000000000000000000000000000000000 + 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 @@ -20881,7 +21125,7 @@ in - 17 + 21 0 @@ -20892,7 +21136,7 @@ - 0x00000 + 0x000000 @@ -20901,7 +21145,7 @@ in - 8 + 10 0 @@ -20912,7 +21156,7 @@ - 0x1FF + 0x7FF @@ -20928,7 +21172,7 @@ in - 8 + 10 0 @@ -20955,7 +21199,7 @@ in - 8 + 10 0 @@ -20982,7 +21226,7 @@ out - 8 + 10 0 @@ -21006,7 +21250,7 @@ C_NUM_MASTER_SLOTS - 9 + 11 C_AXI_ID_WIDTH @@ -21030,11 +21274,11 @@ C_M_AXI_BASE_ADDR - 0x00000000412400000000000043c2000000000000412300000000000043c100000000000043c000000000000043000000000000004122000000000000412100000000000041200000 + 0x00000000412500000000000043c3000000000000412400000000000043c2000000000000412300000000000043c100000000000043c000000000000043000000000000004122000000000000412100000000000041200000 C_M_AXI_ADDR_WIDTH - 0x000000100000001000000010000000100000001000000010000000100000001000000010 + 0x0000001000000010000000100000001000000010000000100000001000000010000000100000001000000010 C_S_AXI_BASE_ID @@ -21070,11 +21314,11 @@ C_M_AXI_WRITE_CONNECTIVITY - 0x000000010000000100000001000000010000000100000001000000010000000100000001 + 0x0000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 C_M_AXI_READ_CONNECTIVITY - 0x000000010000000100000001000000010000000100000001000000010000000100000001 + 0x0000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 C_R_REGISTER @@ -21094,11 +21338,11 @@ C_M_AXI_WRITE_ISSUING - 0x000000010000000100000001000000010000000100000001000000010000000100000001 + 0x0000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 C_M_AXI_READ_ISSUING - 0x000000010000000100000001000000010000000100000001000000010000000100000001 + 0x0000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 C_S_AXI_ARB_PRIORITY @@ -21106,7 +21350,7 @@ C_M_AXI_SECURE - 0x000000000000000000000000000000000000000000000000000000000000000000000000 + 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C_CONNECTIVITY_MODE @@ -21485,7 +21729,7 @@ NUM_MI Number of Master Interfaces - 9 + 11 @@ -28473,7 +28717,7 @@ - true + false @@ -28485,7 +28729,7 @@ - true + false @@ -28665,7 +28909,7 @@ - true + false @@ -28677,7 +28921,7 @@ - true + false @@ -31433,7 +31677,7 @@ M09_A00_BASE_ADDR My M09_A00_BASE_ADDR - 0xffffffffffffffff + 0x0000000043C30000 @@ -31625,7 +31869,7 @@ M10_A00_BASE_ADDR My M10_A00_BASE_ADDR - 0xffffffffffffffff + 0x0000000041250000 @@ -34505,7 +34749,7 @@ M09_A00_ADDR_WIDTH My M09_A00_ADDR_WIDTH - 0 + 16 @@ -34697,7 +34941,7 @@ M10_A00_ADDR_WIDTH My M10_A00_ADDR_WIDTH - 0 + 16 @@ -36002,6 +36246,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -36066,6 +36338,14 @@ + + + + + + + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0_sim_netlist.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0_sim_netlist.v index 17a598c..dfeb91c 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0_sim_netlist.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -// Date : Fri Feb 24 16:02:41 2017 +// Date : Sat Mar 04 18:54:13 2017 // Host : WK73 running 64-bit Service Pack 1 (build 7601) // Command : write_verilog -force -mode funcsim -// c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0_sim_netlist.v +// C:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0_sim_netlist.v // Design : Arty_Z7_20_xbar_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -76,47 +76,47 @@ module Arty_Z7_20_xbar_0 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *) output [1:0]s_axi_rresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *) output [0:0]s_axi_rvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) input [0:0]s_axi_rready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI AWADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI AWADDR [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI AWADDR [31:0] [223:192], xilinx.com:interface:aximm:1.0 M07_AXI AWADDR [31:0] [255:224], xilinx.com:interface:aximm:1.0 M08_AXI AWADDR [31:0] [287:256]" *) output [287:0]m_axi_awaddr; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI AWPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI AWPROT [2:0] [17:15], xilinx.com:interface:aximm:1.0 M06_AXI AWPROT [2:0] [20:18], xilinx.com:interface:aximm:1.0 M07_AXI AWPROT [2:0] [23:21], xilinx.com:interface:aximm:1.0 M08_AXI AWPROT [2:0] [26:24]" *) output [26:0]m_axi_awprot; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI AWVALID [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI AWVALID [0:0] [7:7], xilinx.com:interface:aximm:1.0 M08_AXI AWVALID [0:0] [8:8]" *) output [8:0]m_axi_awvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI AWREADY [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI AWREADY [0:0] [7:7], xilinx.com:interface:aximm:1.0 M08_AXI AWREADY [0:0] [8:8]" *) input [8:0]m_axi_awready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI WDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI WDATA [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI WDATA [31:0] [223:192], xilinx.com:interface:aximm:1.0 M07_AXI WDATA [31:0] [255:224], xilinx.com:interface:aximm:1.0 M08_AXI WDATA [31:0] [287:256]" *) output [287:0]m_axi_wdata; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12], xilinx.com:interface:aximm:1.0 M04_AXI WSTRB [3:0] [19:16], xilinx.com:interface:aximm:1.0 M05_AXI WSTRB [3:0] [23:20], xilinx.com:interface:aximm:1.0 M06_AXI WSTRB [3:0] [27:24], xilinx.com:interface:aximm:1.0 M07_AXI WSTRB [3:0] [31:28], xilinx.com:interface:aximm:1.0 M08_AXI WSTRB [3:0] [35:32]" *) output [35:0]m_axi_wstrb; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI WVALID [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI WVALID [0:0] [7:7], xilinx.com:interface:aximm:1.0 M08_AXI WVALID [0:0] [8:8]" *) output [8:0]m_axi_wvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI WREADY [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI WREADY [0:0] [7:7], xilinx.com:interface:aximm:1.0 M08_AXI WREADY [0:0] [8:8]" *) input [8:0]m_axi_wready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI BRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI BRESP [1:0] [11:10], xilinx.com:interface:aximm:1.0 M06_AXI BRESP [1:0] [13:12], xilinx.com:interface:aximm:1.0 M07_AXI BRESP [1:0] [15:14], xilinx.com:interface:aximm:1.0 M08_AXI BRESP [1:0] [17:16]" *) input [17:0]m_axi_bresp; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI BVALID [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI BVALID [0:0] [7:7], xilinx.com:interface:aximm:1.0 M08_AXI BVALID [0:0] [8:8]" *) input [8:0]m_axi_bvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI BREADY [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI BREADY [0:0] [7:7], xilinx.com:interface:aximm:1.0 M08_AXI BREADY [0:0] [8:8]" *) output [8:0]m_axi_bready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI ARADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI ARADDR [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI ARADDR [31:0] [223:192], xilinx.com:interface:aximm:1.0 M07_AXI ARADDR [31:0] [255:224], xilinx.com:interface:aximm:1.0 M08_AXI ARADDR [31:0] [287:256]" *) output [287:0]m_axi_araddr; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI ARPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI ARPROT [2:0] [17:15], xilinx.com:interface:aximm:1.0 M06_AXI ARPROT [2:0] [20:18], xilinx.com:interface:aximm:1.0 M07_AXI ARPROT [2:0] [23:21], xilinx.com:interface:aximm:1.0 M08_AXI ARPROT [2:0] [26:24]" *) output [26:0]m_axi_arprot; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI ARVALID [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI ARVALID [0:0] [7:7], xilinx.com:interface:aximm:1.0 M08_AXI ARVALID [0:0] [8:8]" *) output [8:0]m_axi_arvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI ARREADY [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI ARREADY [0:0] [7:7], xilinx.com:interface:aximm:1.0 M08_AXI ARREADY [0:0] [8:8]" *) input [8:0]m_axi_arready; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI RDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI RDATA [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI RDATA [31:0] [223:192], xilinx.com:interface:aximm:1.0 M07_AXI RDATA [31:0] [255:224], xilinx.com:interface:aximm:1.0 M08_AXI RDATA [31:0] [287:256]" *) input [287:0]m_axi_rdata; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI RRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI RRESP [1:0] [11:10], xilinx.com:interface:aximm:1.0 M06_AXI RRESP [1:0] [13:12], xilinx.com:interface:aximm:1.0 M07_AXI RRESP [1:0] [15:14], xilinx.com:interface:aximm:1.0 M08_AXI RRESP [1:0] [17:16]" *) input [17:0]m_axi_rresp; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI RVALID [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI RVALID [0:0] [7:7], xilinx.com:interface:aximm:1.0 M08_AXI RVALID [0:0] [8:8]" *) input [8:0]m_axi_rvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI RREADY [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI RREADY [0:0] [7:7], xilinx.com:interface:aximm:1.0 M08_AXI RREADY [0:0] [8:8]" *) output [8:0]m_axi_rready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI AWADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI AWADDR [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI AWADDR [31:0] [223:192], xilinx.com:interface:aximm:1.0 M07_AXI AWADDR [31:0] [255:224], xilinx.com:interface:aximm:1.0 M08_AXI AWADDR [31:0] [287:256], xilinx.com:interface:aximm:1.0 M09_AXI AWADDR [31:0] [319:288], xilinx.com:interface:aximm:1.0 M10_AXI AWADDR [31:0] [351:320]" *) output [351:0]m_axi_awaddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI AWPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI AWPROT [2:0] [17:15], xilinx.com:interface:aximm:1.0 M06_AXI AWPROT [2:0] [20:18], xilinx.com:interface:aximm:1.0 M07_AXI AWPROT [2:0] [23:21], xilinx.com:interface:aximm:1.0 M08_AXI AWPROT [2:0] [26:24], xilinx.com:interface:aximm:1.0 M09_AXI AWPROT [2:0] [29:27], xilinx.com:interface:aximm:1.0 M10_AXI AWPROT [2:0] [32:30]" *) output [32:0]m_axi_awprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI AWVALID [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI AWVALID [0:0] [7:7], xilinx.com:interface:aximm:1.0 M08_AXI AWVALID [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI AWVALID [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI AWVALID [0:0] [10:10]" *) output [10:0]m_axi_awvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI AWREADY [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI AWREADY [0:0] [7:7], xilinx.com:interface:aximm:1.0 M08_AXI AWREADY [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI AWREADY [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI AWREADY [0:0] [10:10]" *) input [10:0]m_axi_awready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI WDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI WDATA [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI WDATA [31:0] [223:192], xilinx.com:interface:aximm:1.0 M07_AXI WDATA [31:0] [255:224], xilinx.com:interface:aximm:1.0 M08_AXI WDATA [31:0] [287:256], xilinx.com:interface:aximm:1.0 M09_AXI WDATA [31:0] [319:288], xilinx.com:interface:aximm:1.0 M10_AXI WDATA [31:0] [351:320]" *) output [351:0]m_axi_wdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12], xilinx.com:interface:aximm:1.0 M04_AXI WSTRB [3:0] [19:16], xilinx.com:interface:aximm:1.0 M05_AXI WSTRB [3:0] [23:20], xilinx.com:interface:aximm:1.0 M06_AXI WSTRB [3:0] [27:24], xilinx.com:interface:aximm:1.0 M07_AXI WSTRB [3:0] [31:28], xilinx.com:interface:aximm:1.0 M08_AXI WSTRB [3:0] [35:32], xilinx.com:interface:aximm:1.0 M09_AXI WSTRB [3:0] [39:36], xilinx.com:interface:aximm:1.0 M10_AXI WSTRB [3:0] [43:40]" *) output [43:0]m_axi_wstrb; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI WVALID [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI WVALID [0:0] [7:7], xilinx.com:interface:aximm:1.0 M08_AXI WVALID [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI WVALID [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI WVALID [0:0] [10:10]" *) output [10:0]m_axi_wvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI WREADY [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI WREADY [0:0] [7:7], xilinx.com:interface:aximm:1.0 M08_AXI WREADY [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI WREADY [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI WREADY [0:0] [10:10]" *) input [10:0]m_axi_wready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI BRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI BRESP [1:0] [11:10], xilinx.com:interface:aximm:1.0 M06_AXI BRESP [1:0] [13:12], xilinx.com:interface:aximm:1.0 M07_AXI BRESP [1:0] [15:14], xilinx.com:interface:aximm:1.0 M08_AXI BRESP [1:0] [17:16], xilinx.com:interface:aximm:1.0 M09_AXI BRESP [1:0] [19:18], xilinx.com:interface:aximm:1.0 M10_AXI BRESP [1:0] [21:20]" *) input [21:0]m_axi_bresp; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI BVALID [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI BVALID [0:0] [7:7], xilinx.com:interface:aximm:1.0 M08_AXI BVALID [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI BVALID [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI BVALID [0:0] [10:10]" *) input [10:0]m_axi_bvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI BREADY [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI BREADY [0:0] [7:7], xilinx.com:interface:aximm:1.0 M08_AXI BREADY [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI BREADY [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI BREADY [0:0] [10:10]" *) output [10:0]m_axi_bready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI ARADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI ARADDR [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI ARADDR [31:0] [223:192], xilinx.com:interface:aximm:1.0 M07_AXI ARADDR [31:0] [255:224], xilinx.com:interface:aximm:1.0 M08_AXI ARADDR [31:0] [287:256], xilinx.com:interface:aximm:1.0 M09_AXI ARADDR [31:0] [319:288], xilinx.com:interface:aximm:1.0 M10_AXI ARADDR [31:0] [351:320]" *) output [351:0]m_axi_araddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI ARPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI ARPROT [2:0] [17:15], xilinx.com:interface:aximm:1.0 M06_AXI ARPROT [2:0] [20:18], xilinx.com:interface:aximm:1.0 M07_AXI ARPROT [2:0] [23:21], xilinx.com:interface:aximm:1.0 M08_AXI ARPROT [2:0] [26:24], xilinx.com:interface:aximm:1.0 M09_AXI ARPROT [2:0] [29:27], xilinx.com:interface:aximm:1.0 M10_AXI ARPROT [2:0] [32:30]" *) output [32:0]m_axi_arprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI ARVALID [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI ARVALID [0:0] [7:7], xilinx.com:interface:aximm:1.0 M08_AXI ARVALID [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI ARVALID [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI ARVALID [0:0] [10:10]" *) output [10:0]m_axi_arvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI ARREADY [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI ARREADY [0:0] [7:7], xilinx.com:interface:aximm:1.0 M08_AXI ARREADY [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI ARREADY [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI ARREADY [0:0] [10:10]" *) input [10:0]m_axi_arready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI RDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI RDATA [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI RDATA [31:0] [223:192], xilinx.com:interface:aximm:1.0 M07_AXI RDATA [31:0] [255:224], xilinx.com:interface:aximm:1.0 M08_AXI RDATA [31:0] [287:256], xilinx.com:interface:aximm:1.0 M09_AXI RDATA [31:0] [319:288], xilinx.com:interface:aximm:1.0 M10_AXI RDATA [31:0] [351:320]" *) input [351:0]m_axi_rdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI RRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI RRESP [1:0] [11:10], xilinx.com:interface:aximm:1.0 M06_AXI RRESP [1:0] [13:12], xilinx.com:interface:aximm:1.0 M07_AXI RRESP [1:0] [15:14], xilinx.com:interface:aximm:1.0 M08_AXI RRESP [1:0] [17:16], xilinx.com:interface:aximm:1.0 M09_AXI RRESP [1:0] [19:18], xilinx.com:interface:aximm:1.0 M10_AXI RRESP [1:0] [21:20]" *) input [21:0]m_axi_rresp; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI RVALID [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI RVALID [0:0] [7:7], xilinx.com:interface:aximm:1.0 M08_AXI RVALID [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI RVALID [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI RVALID [0:0] [10:10]" *) input [10:0]m_axi_rvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI RREADY [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI RREADY [0:0] [7:7], xilinx.com:interface:aximm:1.0 M08_AXI RREADY [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI RREADY [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI RREADY [0:0] [10:10]" *) output [10:0]m_axi_rready; wire aclk; wire aresetn; - wire [287:0]m_axi_araddr; - wire [26:0]m_axi_arprot; - wire [8:0]m_axi_arready; - wire [8:0]m_axi_arvalid; - wire [287:0]m_axi_awaddr; - wire [26:0]m_axi_awprot; - wire [8:0]m_axi_awready; - wire [8:0]m_axi_awvalid; - wire [8:0]m_axi_bready; - wire [17:0]m_axi_bresp; - wire [8:0]m_axi_bvalid; - wire [287:0]m_axi_rdata; - wire [8:0]m_axi_rready; - wire [17:0]m_axi_rresp; - wire [8:0]m_axi_rvalid; - wire [287:0]m_axi_wdata; - wire [8:0]m_axi_wready; - wire [35:0]m_axi_wstrb; - wire [8:0]m_axi_wvalid; + wire [351:0]m_axi_araddr; + wire [32:0]m_axi_arprot; + wire [10:0]m_axi_arready; + wire [10:0]m_axi_arvalid; + wire [351:0]m_axi_awaddr; + wire [32:0]m_axi_awprot; + wire [10:0]m_axi_awready; + wire [10:0]m_axi_awvalid; + wire [10:0]m_axi_bready; + wire [21:0]m_axi_bresp; + wire [10:0]m_axi_bvalid; + wire [351:0]m_axi_rdata; + wire [10:0]m_axi_rready; + wire [21:0]m_axi_rresp; + wire [10:0]m_axi_rvalid; + wire [351:0]m_axi_wdata; + wire [10:0]m_axi_wready; + wire [43:0]m_axi_wstrb; + wire [10:0]m_axi_wvalid; wire [31:0]s_axi_araddr; wire [2:0]s_axi_arprot; wire [0:0]s_axi_arready; @@ -136,27 +136,27 @@ module Arty_Z7_20_xbar_0 wire [0:0]s_axi_wready; wire [3:0]s_axi_wstrb; wire [0:0]s_axi_wvalid; - wire [17:0]NLW_inst_m_axi_arburst_UNCONNECTED; - wire [35:0]NLW_inst_m_axi_arcache_UNCONNECTED; - wire [8:0]NLW_inst_m_axi_arid_UNCONNECTED; - wire [71:0]NLW_inst_m_axi_arlen_UNCONNECTED; - wire [8:0]NLW_inst_m_axi_arlock_UNCONNECTED; - wire [35:0]NLW_inst_m_axi_arqos_UNCONNECTED; - wire [35:0]NLW_inst_m_axi_arregion_UNCONNECTED; - wire [26:0]NLW_inst_m_axi_arsize_UNCONNECTED; - wire [8:0]NLW_inst_m_axi_aruser_UNCONNECTED; - wire [17:0]NLW_inst_m_axi_awburst_UNCONNECTED; - wire [35:0]NLW_inst_m_axi_awcache_UNCONNECTED; - wire [8:0]NLW_inst_m_axi_awid_UNCONNECTED; - wire [71:0]NLW_inst_m_axi_awlen_UNCONNECTED; - wire [8:0]NLW_inst_m_axi_awlock_UNCONNECTED; - wire [35:0]NLW_inst_m_axi_awqos_UNCONNECTED; - wire [35:0]NLW_inst_m_axi_awregion_UNCONNECTED; - wire [26:0]NLW_inst_m_axi_awsize_UNCONNECTED; - wire [8:0]NLW_inst_m_axi_awuser_UNCONNECTED; - wire [8:0]NLW_inst_m_axi_wid_UNCONNECTED; - wire [8:0]NLW_inst_m_axi_wlast_UNCONNECTED; - wire [8:0]NLW_inst_m_axi_wuser_UNCONNECTED; + wire [21:0]NLW_inst_m_axi_arburst_UNCONNECTED; + wire [43:0]NLW_inst_m_axi_arcache_UNCONNECTED; + wire [10:0]NLW_inst_m_axi_arid_UNCONNECTED; + wire [87:0]NLW_inst_m_axi_arlen_UNCONNECTED; + wire [10:0]NLW_inst_m_axi_arlock_UNCONNECTED; + wire [43:0]NLW_inst_m_axi_arqos_UNCONNECTED; + wire [43:0]NLW_inst_m_axi_arregion_UNCONNECTED; + wire [32:0]NLW_inst_m_axi_arsize_UNCONNECTED; + wire [10:0]NLW_inst_m_axi_aruser_UNCONNECTED; + wire [21:0]NLW_inst_m_axi_awburst_UNCONNECTED; + wire [43:0]NLW_inst_m_axi_awcache_UNCONNECTED; + wire [10:0]NLW_inst_m_axi_awid_UNCONNECTED; + wire [87:0]NLW_inst_m_axi_awlen_UNCONNECTED; + wire [10:0]NLW_inst_m_axi_awlock_UNCONNECTED; + wire [43:0]NLW_inst_m_axi_awqos_UNCONNECTED; + wire [43:0]NLW_inst_m_axi_awregion_UNCONNECTED; + wire [32:0]NLW_inst_m_axi_awsize_UNCONNECTED; + wire [10:0]NLW_inst_m_axi_awuser_UNCONNECTED; + wire [10:0]NLW_inst_m_axi_wid_UNCONNECTED; + wire [10:0]NLW_inst_m_axi_wlast_UNCONNECTED; + wire [10:0]NLW_inst_m_axi_wuser_UNCONNECTED; wire [0:0]NLW_inst_s_axi_bid_UNCONNECTED; wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED; wire [0:0]NLW_inst_s_axi_rid_UNCONNECTED; @@ -176,15 +176,15 @@ module Arty_Z7_20_xbar_0 (* C_CONNECTIVITY_MODE = "0" *) (* C_DEBUG = "1" *) (* C_FAMILY = "zynq" *) - (* C_M_AXI_ADDR_WIDTH = "288'b000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000" *) - (* C_M_AXI_BASE_ADDR = "576'b000000000000000000000000000000000100000100100100000000000000000000000000000000000000000000000000010000111100001000000000000000000000000000000000000000000000000001000001001000110000000000000000000000000000000000000000000000000100001111000001000000000000000000000000000000000000000000000000010000111100000000000000000000000000000000000000000000000000000001000011000000000000000000000000000000000000000000000000000000000100000100100010000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000" *) - (* C_M_AXI_READ_CONNECTIVITY = "288'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) - (* C_M_AXI_READ_ISSUING = "288'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) - (* C_M_AXI_SECURE = "288'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) - (* C_M_AXI_WRITE_CONNECTIVITY = "288'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) - (* C_M_AXI_WRITE_ISSUING = "288'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) + (* C_M_AXI_ADDR_WIDTH = "352'b0000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000" *) + (* C_M_AXI_BASE_ADDR = "704'b00000000000000000000000000000000010000010010010100000000000000000000000000000000000000000000000001000011110000110000000000000000000000000000000000000000000000000100000100100100000000000000000000000000000000000000000000000000010000111100001000000000000000000000000000000000000000000000000001000001001000110000000000000000000000000000000000000000000000000100001111000001000000000000000000000000000000000000000000000000010000111100000000000000000000000000000000000000000000000000000001000011000000000000000000000000000000000000000000000000000000000100000100100010000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000" *) + (* C_M_AXI_READ_CONNECTIVITY = "352'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) + (* C_M_AXI_READ_ISSUING = "352'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) + (* C_M_AXI_SECURE = "352'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) + (* C_M_AXI_WRITE_CONNECTIVITY = "352'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) + (* C_M_AXI_WRITE_ISSUING = "352'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_NUM_ADDR_RANGES = "1" *) - (* C_NUM_MASTER_SLOTS = "9" *) + (* C_NUM_MASTER_SLOTS = "11" *) (* C_NUM_SLAVE_SLOTS = "1" *) (* C_R_REGISTER = "1" *) (* C_S_AXI_ARB_PRIORITY = "0" *) @@ -203,9 +203,9 @@ module Arty_Z7_20_xbar_0 (* P_INCR = "2'b01" *) (* P_LEN = "8" *) (* P_LOCK = "1" *) - (* P_M_AXI_ERR_MODE = "288'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) - (* P_M_AXI_SUPPORTS_READ = "9'b111111111" *) - (* P_M_AXI_SUPPORTS_WRITE = "9'b111111111" *) + (* P_M_AXI_ERR_MODE = "352'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) + (* P_M_AXI_SUPPORTS_READ = "11'b11111111111" *) + (* P_M_AXI_SUPPORTS_WRITE = "11'b11111111111" *) (* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *) (* P_RANGE_CHECK = "1" *) (* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) @@ -216,49 +216,49 @@ module Arty_Z7_20_xbar_0 (.aclk(aclk), .aresetn(aresetn), .m_axi_araddr(m_axi_araddr), - .m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[17:0]), - .m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[35:0]), - .m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[8:0]), - .m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[71:0]), - .m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[8:0]), + .m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[21:0]), + .m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[43:0]), + .m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[10:0]), + .m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[87:0]), + .m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[10:0]), .m_axi_arprot(m_axi_arprot), - .m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[35:0]), + .m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[43:0]), .m_axi_arready(m_axi_arready), - .m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[35:0]), - .m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[26:0]), - .m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[8:0]), + .m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[43:0]), + .m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[32:0]), + .m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[10:0]), .m_axi_arvalid(m_axi_arvalid), .m_axi_awaddr(m_axi_awaddr), - .m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[17:0]), - .m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[35:0]), - .m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[8:0]), - .m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[71:0]), - .m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[8:0]), + .m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[21:0]), + .m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[43:0]), + .m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[10:0]), + .m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[87:0]), + .m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[10:0]), .m_axi_awprot(m_axi_awprot), - .m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[35:0]), + .m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[43:0]), .m_axi_awready(m_axi_awready), - .m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[35:0]), - .m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[26:0]), - .m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[8:0]), + .m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[43:0]), + .m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[32:0]), + .m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[10:0]), .m_axi_awvalid(m_axi_awvalid), - .m_axi_bid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .m_axi_bid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .m_axi_bready(m_axi_bready), .m_axi_bresp(m_axi_bresp), - .m_axi_buser({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .m_axi_buser({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .m_axi_bvalid(m_axi_bvalid), .m_axi_rdata(m_axi_rdata), - .m_axi_rid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), - .m_axi_rlast({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), + .m_axi_rid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .m_axi_rlast({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .m_axi_rready(m_axi_rready), .m_axi_rresp(m_axi_rresp), - .m_axi_ruser({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .m_axi_ruser({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .m_axi_rvalid(m_axi_rvalid), .m_axi_wdata(m_axi_wdata), - .m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[8:0]), - .m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED[8:0]), + .m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[10:0]), + .m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED[10:0]), .m_axi_wready(m_axi_wready), .m_axi_wstrb(m_axi_wstrb), - .m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[8:0]), + .m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[10:0]), .m_axi_wvalid(m_axi_wvalid), .s_axi_araddr(s_axi_araddr), .s_axi_arburst({1'b0,1'b0}), @@ -307,228 +307,229 @@ endmodule (* ORIG_REF_NAME = "axi_crossbar_v2_1_12_addr_arbiter_sasd" *) module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_addr_arbiter_sasd - (m_valid_i, - SR, + (reset, + m_valid_i, aa_grant_rnw, + \m_atarget_enc_reg[1] , \m_atarget_enc_reg[0] , \m_atarget_enc_reg[3] , + s_axi_bvalid, + m_ready_d0, + m_ready_d0_0, + \m_ready_d_reg[2] , + s_axi_wready, + m_axi_bready, \m_ready_d_reg[1] , + \gen_axilite.s_axi_bvalid_i_reg , + m_axi_awvalid, + \gen_axilite.s_axi_bvalid_i_reg_0 , + m_axi_wvalid, + \gen_axilite.s_axi_bvalid_i_reg_1 , + s_ready_i_reg, E, \m_ready_d_reg[0] , - \gen_axilite.s_axi_bvalid_i_reg , \m_ready_d_reg[1]_0 , \m_ready_d_reg[0]_0 , + m_axi_arvalid, + \gen_axilite.s_axi_rvalid_i_reg , s_axi_awready, - D, - \m_atarget_enc_reg[2] , - Q, s_axi_arready, - mi_arready_mux, - \m_ready_d_reg[1]_1 , - \m_ready_d_reg[1]_2 , - m_axi_arvalid, - aa_rvalid, - aa_awready, - mi_awready_mux, - m_axi_bready, - s_axi_wready, - aa_wready, - s_axi_bvalid, - aa_bvalid, s_axi_rvalid, - p_4_in, - m_axi_wvalid, - m_axi_awvalid, - \gen_axilite.s_axi_bvalid_i_reg_0 , + D, + \m_axi_arprot[2] , + \m_atarget_enc_reg[2] , + \gen_axilite.s_axi_bvalid_i_reg_2 , aclk, m_ready_d, - m_atarget_enc, - s_axi_rready, - sr_rvalid, - m_ready_d_0, - aresetn_d, - m_axi_arready, - \gen_axilite.s_axi_arready_i_reg , - \m_atarget_hot_reg[9] , - m_axi_rvalid, - \gen_axilite.s_axi_rvalid_i_reg , - \gen_axilite.s_axi_bvalid_i_reg_1 , - s_axi_bready, - \gen_axilite.s_axi_awready_i_reg , - s_axi_wvalid, - \gen_axilite.s_axi_awready_i_reg_0 , - m_axi_awready, \m_atarget_enc_reg[2]_0 , - m_axi_wready, + \m_payload_i_reg[0] , + \m_ready_d_reg[0]_1 , \m_atarget_enc_reg[2]_1 , \m_atarget_enc_reg[2]_2 , - m_axi_bvalid, + \m_atarget_enc_reg[3]_0 , + s_axi_wvalid, + \m_atarget_enc_reg[3]_1 , \m_atarget_enc_reg[2]_3 , - s_axi_araddr, - s_axi_awaddr, - s_axi_arvalid, + Q, + s_axi_bready, + \m_atarget_enc_reg[2]_4 , + m_axi_awready, + m_atarget_enc, + \m_atarget_enc_reg[2]_5 , + \m_atarget_enc_reg[3]_2 , + \m_atarget_enc_reg[3]_3 , + m_ready_d_1, + s_axi_rready, + sr_rvalid, + aresetn_d, + \m_payload_i_reg[0]_0 , + \m_atarget_enc_reg[2]_6 , + \m_atarget_enc_reg[2]_7 , + \m_atarget_enc_reg[3]_4 , + \m_atarget_enc_reg[2]_8 , s_axi_arprot, + s_axi_arvalid, s_axi_awprot, - mi_bvalid, + s_axi_araddr, + s_axi_awaddr, mi_wready, - \m_ready_d_reg[0]_1 , + mi_bvalid, s_axi_awvalid); + output reset; output m_valid_i; - output [0:0]SR; output aa_grant_rnw; + output \m_atarget_enc_reg[1] ; output \m_atarget_enc_reg[0] ; output \m_atarget_enc_reg[3] ; + output [0:0]s_axi_bvalid; + output [0:0]m_ready_d0; + output [0:0]m_ready_d0_0; + output \m_ready_d_reg[2] ; + output [0:0]s_axi_wready; + output [10:0]m_axi_bready; output \m_ready_d_reg[1] ; + output \gen_axilite.s_axi_bvalid_i_reg ; + output [10:0]m_axi_awvalid; + output \gen_axilite.s_axi_bvalid_i_reg_0 ; + output [10:0]m_axi_wvalid; + output \gen_axilite.s_axi_bvalid_i_reg_1 ; + output s_ready_i_reg; output [0:0]E; output \m_ready_d_reg[0] ; - output \gen_axilite.s_axi_bvalid_i_reg ; output \m_ready_d_reg[1]_0 ; output \m_ready_d_reg[0]_0 ; + output [10:0]m_axi_arvalid; + output \gen_axilite.s_axi_rvalid_i_reg ; output [0:0]s_axi_awready; - output [9:0]D; - output [1:0]\m_atarget_enc_reg[2] ; - output [34:0]Q; output [0:0]s_axi_arready; - output mi_arready_mux; - output \m_ready_d_reg[1]_1 ; - output \m_ready_d_reg[1]_2 ; - output [8:0]m_axi_arvalid; - output aa_rvalid; - output aa_awready; - output mi_awready_mux; - output [8:0]m_axi_bready; - output [0:0]s_axi_wready; - output aa_wready; - output [0:0]s_axi_bvalid; - output aa_bvalid; output [0:0]s_axi_rvalid; - output p_4_in; - output [8:0]m_axi_wvalid; - output [8:0]m_axi_awvalid; - output \gen_axilite.s_axi_bvalid_i_reg_0 ; + output [11:0]D; + output [34:0]\m_axi_arprot[2] ; + output \m_atarget_enc_reg[2] ; + output \gen_axilite.s_axi_bvalid_i_reg_2 ; input aclk; - input [1:0]m_ready_d; - input [3:0]m_atarget_enc; - input [0:0]s_axi_rready; - input sr_rvalid; - input [2:0]m_ready_d_0; - input aresetn_d; - input [6:0]m_axi_arready; - input \gen_axilite.s_axi_arready_i_reg ; - input [9:0]\m_atarget_hot_reg[9] ; - input [6:0]m_axi_rvalid; - input \gen_axilite.s_axi_rvalid_i_reg ; - input \gen_axilite.s_axi_bvalid_i_reg_1 ; - input [0:0]s_axi_bready; - input \gen_axilite.s_axi_awready_i_reg ; - input [0:0]s_axi_wvalid; - input \gen_axilite.s_axi_awready_i_reg_0 ; - input [6:0]m_axi_awready; + input [2:0]m_ready_d; input \m_atarget_enc_reg[2]_0 ; - input [6:0]m_axi_wready; + input \m_payload_i_reg[0] ; + input \m_ready_d_reg[0]_1 ; input \m_atarget_enc_reg[2]_1 ; input \m_atarget_enc_reg[2]_2 ; - input [6:0]m_axi_bvalid; + input \m_atarget_enc_reg[3]_0 ; + input [0:0]s_axi_wvalid; + input \m_atarget_enc_reg[3]_1 ; input \m_atarget_enc_reg[2]_3 ; - input [31:0]s_axi_araddr; - input [31:0]s_axi_awaddr; - input [0:0]s_axi_arvalid; + input [11:0]Q; + input [0:0]s_axi_bready; + input \m_atarget_enc_reg[2]_4 ; + input [4:0]m_axi_awready; + input [3:0]m_atarget_enc; + input \m_atarget_enc_reg[2]_5 ; + input \m_atarget_enc_reg[3]_2 ; + input \m_atarget_enc_reg[3]_3 ; + input [1:0]m_ready_d_1; + input [0:0]s_axi_rready; + input sr_rvalid; + input aresetn_d; + input [0:0]\m_payload_i_reg[0]_0 ; + input \m_atarget_enc_reg[2]_6 ; + input \m_atarget_enc_reg[2]_7 ; + input \m_atarget_enc_reg[3]_4 ; + input \m_atarget_enc_reg[2]_8 ; input [2:0]s_axi_arprot; + input [0:0]s_axi_arvalid; input [2:0]s_axi_awprot; - input [0:0]mi_bvalid; + input [31:0]s_axi_araddr; + input [31:0]s_axi_awaddr; input [0:0]mi_wready; - input \m_ready_d_reg[0]_1 ; + input [0:0]mi_bvalid; input [0:0]s_axi_awvalid; - wire [9:0]D; + wire [11:0]D; wire [0:0]E; - wire [34:0]Q; - wire [0:0]SR; - wire aa_awready; - wire aa_bvalid; + wire [11:0]Q; wire aa_grant_any; wire aa_grant_rnw; - wire aa_rvalid; - wire aa_wready; wire aclk; wire aresetn_d; - wire \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0 ; - wire \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1 ; - wire \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2 ; - wire \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3 ; - wire \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_4 ; - wire \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_5 ; - wire \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_6 ; - wire \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_7 ; - wire \gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3__4 ; - wire \gen_addr_decoder.addr_decoder_inst/gen_target[7].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ; - wire \gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ; - wire \gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ; - wire \gen_axilite.s_axi_arready_i_reg ; - wire \gen_axilite.s_axi_awready_i_reg ; - wire \gen_axilite.s_axi_awready_i_reg_0 ; wire \gen_axilite.s_axi_bvalid_i_reg ; wire \gen_axilite.s_axi_bvalid_i_reg_0 ; wire \gen_axilite.s_axi_bvalid_i_reg_1 ; + wire \gen_axilite.s_axi_bvalid_i_reg_2 ; wire \gen_axilite.s_axi_rvalid_i_reg ; wire \gen_no_arbiter.grant_rnw_i_1_n_0 ; wire \gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ; - wire \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ; wire \gen_no_arbiter.m_valid_i_i_1_n_0 ; + wire \gen_no_arbiter.m_valid_i_i_2_n_0 ; wire [3:0]m_atarget_enc; - wire \m_atarget_enc[2]_i_3_n_0 ; + wire \m_atarget_enc[0]_i_2_n_0 ; + wire \m_atarget_enc[0]_i_3_n_0 ; + wire \m_atarget_enc[1]_i_2_n_0 ; + wire \m_atarget_enc[1]_i_3_n_0 ; + wire \m_atarget_enc[3]_i_2_n_0 ; + wire \m_atarget_enc[3]_i_3_n_0 ; + wire \m_atarget_enc[3]_i_4_n_0 ; wire \m_atarget_enc_reg[0] ; - wire [1:0]\m_atarget_enc_reg[2] ; + wire \m_atarget_enc_reg[1] ; + wire \m_atarget_enc_reg[2] ; wire \m_atarget_enc_reg[2]_0 ; wire \m_atarget_enc_reg[2]_1 ; wire \m_atarget_enc_reg[2]_2 ; wire \m_atarget_enc_reg[2]_3 ; + wire \m_atarget_enc_reg[2]_4 ; + wire \m_atarget_enc_reg[2]_5 ; + wire \m_atarget_enc_reg[2]_6 ; + wire \m_atarget_enc_reg[2]_7 ; + wire \m_atarget_enc_reg[2]_8 ; wire \m_atarget_enc_reg[3] ; + wire \m_atarget_enc_reg[3]_0 ; + wire \m_atarget_enc_reg[3]_1 ; + wire \m_atarget_enc_reg[3]_2 ; + wire \m_atarget_enc_reg[3]_3 ; + wire \m_atarget_enc_reg[3]_4 ; + wire \m_atarget_hot[0]_i_2_n_0 ; + wire \m_atarget_hot[10]_i_2_n_0 ; + wire \m_atarget_hot[10]_i_3_n_0 ; + wire \m_atarget_hot[11]_i_2_n_0 ; + wire \m_atarget_hot[11]_i_3_n_0 ; + wire \m_atarget_hot[11]_i_4_n_0 ; + wire \m_atarget_hot[1]_i_2_n_0 ; + wire \m_atarget_hot[2]_i_2_n_0 ; + wire \m_atarget_hot[3]_i_2_n_0 ; + wire \m_atarget_hot[3]_i_3_n_0 ; + wire \m_atarget_hot[4]_i_2_n_0 ; + wire \m_atarget_hot[4]_i_3_n_0 ; + wire \m_atarget_hot[5]_i_2_n_0 ; + wire \m_atarget_hot[6]_i_2_n_0 ; + wire \m_atarget_hot[7]_i_2_n_0 ; wire \m_atarget_hot[8]_i_2_n_0 ; - wire \m_atarget_hot[9]_i_3_n_0 ; - wire \m_atarget_hot[9]_i_6_n_0 ; - wire \m_atarget_hot[9]_i_7_n_0 ; - wire \m_atarget_hot[9]_i_8_n_0 ; - wire [9:0]\m_atarget_hot_reg[9] ; - wire [6:0]m_axi_arready; - wire [8:0]m_axi_arvalid; - wire [6:0]m_axi_awready; - wire [8:0]m_axi_awvalid; - wire [8:0]m_axi_bready; - wire [6:0]m_axi_bvalid; - wire [6:0]m_axi_rvalid; - wire [6:0]m_axi_wready; - wire [8:0]m_axi_wvalid; - wire [1:0]m_ready_d; - wire \m_ready_d[1]_i_7_n_0 ; - wire \m_ready_d[1]_i_8_n_0 ; - wire \m_ready_d[2]_i_10_n_0 ; - wire \m_ready_d[2]_i_11_n_0 ; - wire \m_ready_d[2]_i_4_n_0 ; + wire \m_atarget_hot[9]_i_2_n_0 ; + wire [34:0]\m_axi_arprot[2] ; + wire [10:0]m_axi_arvalid; + wire [4:0]m_axi_awready; + wire [10:0]m_axi_awvalid; + wire [10:0]m_axi_bready; + wire [10:0]m_axi_wvalid; + wire \m_payload_i_reg[0] ; + wire [0:0]\m_payload_i_reg[0]_0 ; + wire [2:0]m_ready_d; + wire [0:0]m_ready_d0; + wire [0:0]m_ready_d0_0; wire \m_ready_d[2]_i_6_n_0 ; wire \m_ready_d[2]_i_7_n_0 ; - wire [2:0]m_ready_d_0; + wire \m_ready_d[2]_i_8_n_0 ; + wire [1:0]m_ready_d_1; wire \m_ready_d_reg[0] ; wire \m_ready_d_reg[0]_0 ; wire \m_ready_d_reg[0]_1 ; wire \m_ready_d_reg[1] ; wire \m_ready_d_reg[1]_0 ; - wire \m_ready_d_reg[1]_1 ; - wire \m_ready_d_reg[1]_2 ; + wire \m_ready_d_reg[2] ; wire m_valid_i; - wire m_valid_i_i_3_n_0; - wire m_valid_i_i_4_n_0; - wire m_valid_i_i_5_n_0; - wire m_valid_i_i_6_n_0; - wire match; - wire mi_arready_mux; - wire mi_awready_mux; + wire m_valid_i4_out; wire [0:0]mi_bvalid; wire [0:0]mi_wready; wire p_0_in1_in; - wire [1:0]p_0_out__0; - wire p_3_in; - wire p_4_in; + wire reset; wire [48:1]s_amesg; wire \s_arvalid_reg[0]_i_1_n_0 ; wire \s_arvalid_reg_reg_n_0_[0] ; @@ -544,65 +545,68 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_addr_arbiter_sasd wire [0:0]s_axi_awvalid; wire [0:0]s_axi_bready; wire [0:0]s_axi_bvalid; - wire \s_axi_bvalid[0]_INST_0_i_2_n_0 ; - wire \s_axi_bvalid[0]_INST_0_i_4_n_0 ; - wire \s_axi_bvalid[0]_INST_0_i_5_n_0 ; wire [0:0]s_axi_rready; wire [0:0]s_axi_rvalid; wire [0:0]s_axi_wready; + wire \s_axi_wready[0]_INST_0_i_1_n_0 ; wire \s_axi_wready[0]_INST_0_i_2_n_0 ; - wire \s_axi_wready[0]_INST_0_i_4_n_0 ; - wire \s_axi_wready[0]_INST_0_i_5_n_0 ; wire [0:0]s_axi_wvalid; wire s_ready_i; - wire s_ready_i0; + wire s_ready_i_reg; wire sr_rvalid; - wire [3:0]target_mi_enc; LUT6 #( - .INIT(64'h7C4C4C4C4C4C4C4C)) + .INIT(64'hAFAFAFAF30000000)) \gen_axilite.s_axi_bvalid_i_i_1 - (.I0(p_3_in), - .I1(mi_bvalid), - .I2(\m_atarget_hot_reg[9] [9]), - .I3(p_4_in), - .I4(\gen_axilite.s_axi_bvalid_i_reg ), - .I5(mi_wready), - .O(\gen_axilite.s_axi_bvalid_i_reg_0 )); - (* SOFT_HLUTNM = "soft_lutpair2" *) - LUT4 #( - .INIT(16'h0020)) - \gen_axilite.s_axi_bvalid_i_i_2 - (.I0(s_axi_bready), - .I1(m_ready_d_0[0]), - .I2(m_valid_i), - .I3(aa_grant_rnw), - .O(p_3_in)); + (.I0(\gen_axilite.s_axi_bvalid_i_reg ), + .I1(\gen_axilite.s_axi_bvalid_i_reg_0 ), + .I2(Q[11]), + .I3(\gen_axilite.s_axi_bvalid_i_reg_1 ), + .I4(mi_wready), + .I5(mi_bvalid), + .O(\gen_axilite.s_axi_bvalid_i_reg_2 )); (* SOFT_HLUTNM = "soft_lutpair0" *) LUT4 #( - .INIT(16'h0400)) + .INIT(16'hFBFF)) + \gen_axilite.s_axi_bvalid_i_i_2 + (.I0(aa_grant_rnw), + .I1(m_valid_i), + .I2(m_ready_d[0]), + .I3(s_axi_bready), + .O(\gen_axilite.s_axi_bvalid_i_reg )); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT3 #( + .INIT(8'hFB)) \gen_axilite.s_axi_bvalid_i_i_3 - (.I0(m_ready_d_0[1]), + (.I0(m_ready_d[2]), .I1(m_valid_i), .I2(aa_grant_rnw), - .I3(s_axi_wvalid), - .O(p_4_in)); - (* SOFT_HLUTNM = "soft_lutpair15" *) - LUT3 #( - .INIT(8'h04)) + .O(\gen_axilite.s_axi_bvalid_i_reg_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT4 #( + .INIT(16'h0040)) \gen_axilite.s_axi_bvalid_i_i_4 - (.I0(aa_grant_rnw), + (.I0(m_ready_d[1]), + .I1(s_axi_wvalid), + .I2(m_valid_i), + .I3(aa_grant_rnw), + .O(\gen_axilite.s_axi_bvalid_i_reg_1 )); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT3 #( + .INIT(8'h40)) + \gen_axilite.s_axi_rvalid_i_i_2 + (.I0(m_ready_d_1[1]), .I1(m_valid_i), - .I2(m_ready_d_0[2]), - .O(\gen_axilite.s_axi_bvalid_i_reg )); + .I2(aa_grant_rnw), + .O(\gen_axilite.s_axi_rvalid_i_reg )); LUT6 #( - .INIT(64'hFFFFFF4700000044)) + .INIT(64'hFDFDFCFF01010000)) \gen_no_arbiter.grant_rnw_i_1 (.I0(s_awvalid_reg), - .I1(s_axi_arvalid), - .I2(s_axi_awvalid), - .I3(aa_grant_any), - .I4(m_valid_i), + .I1(m_valid_i), + .I2(aa_grant_any), + .I3(s_axi_awvalid), + .I4(s_axi_arvalid), .I5(aa_grant_rnw), .O(\gen_no_arbiter.grant_rnw_i_1_n_0 )); FDRE \gen_no_arbiter.grant_rnw_reg @@ -610,1460 +614,1431 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_addr_arbiter_sasd .CE(1'b1), .D(\gen_no_arbiter.grant_rnw_i_1_n_0 ), .Q(aa_grant_rnw), - .R(SR)); + .R(reset)); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[10]_i_1 (.I0(s_axi_araddr[9]), - .I1(s_axi_awaddr[9]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[9]), .O(s_amesg[10])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[11]_i_1 (.I0(s_axi_araddr[10]), - .I1(s_axi_awaddr[10]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[10]), .O(s_amesg[11])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[12]_i_1 (.I0(s_axi_araddr[11]), - .I1(s_axi_awaddr[11]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[11]), .O(s_amesg[12])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[13]_i_1 (.I0(s_axi_araddr[12]), - .I1(s_axi_awaddr[12]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[12]), .O(s_amesg[13])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[14]_i_1 (.I0(s_axi_araddr[13]), - .I1(s_axi_awaddr[13]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[13]), .O(s_amesg[14])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[15]_i_1 (.I0(s_axi_araddr[14]), - .I1(s_axi_awaddr[14]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[14]), .O(s_amesg[15])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[16]_i_1 (.I0(s_axi_araddr[15]), - .I1(s_axi_awaddr[15]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[15]), .O(s_amesg[16])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[17]_i_1 (.I0(s_axi_araddr[16]), - .I1(s_axi_awaddr[16]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[16]), .O(s_amesg[17])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[18]_i_1 (.I0(s_axi_araddr[17]), - .I1(s_axi_awaddr[17]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[17]), .O(s_amesg[18])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[19]_i_1 (.I0(s_axi_araddr[18]), - .I1(s_axi_awaddr[18]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[18]), .O(s_amesg[19])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[1]_i_1 (.I0(s_axi_araddr[0]), - .I1(s_axi_awaddr[0]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[0]), .O(s_amesg[1])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[20]_i_1 (.I0(s_axi_araddr[19]), - .I1(s_axi_awaddr[19]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[19]), .O(s_amesg[20])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[21]_i_1 (.I0(s_axi_araddr[20]), - .I1(s_axi_awaddr[20]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[20]), .O(s_amesg[21])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[22]_i_1 (.I0(s_axi_araddr[21]), - .I1(s_axi_awaddr[21]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[21]), .O(s_amesg[22])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[23]_i_1 (.I0(s_axi_araddr[22]), - .I1(s_axi_awaddr[22]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[22]), .O(s_amesg[23])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[24]_i_1 (.I0(s_axi_araddr[23]), - .I1(s_axi_awaddr[23]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[23]), .O(s_amesg[24])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[25]_i_1 (.I0(s_axi_araddr[24]), - .I1(s_axi_awaddr[24]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[24]), .O(s_amesg[25])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[26]_i_1 (.I0(s_axi_araddr[25]), - .I1(s_axi_awaddr[25]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[25]), .O(s_amesg[26])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[27]_i_1 (.I0(s_axi_araddr[26]), - .I1(s_axi_awaddr[26]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[26]), .O(s_amesg[27])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[28]_i_1 (.I0(s_axi_araddr[27]), - .I1(s_axi_awaddr[27]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[27]), .O(s_amesg[28])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[29]_i_1 (.I0(s_axi_araddr[28]), - .I1(s_axi_awaddr[28]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[28]), .O(s_amesg[29])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[2]_i_1 (.I0(s_axi_araddr[1]), - .I1(s_axi_awaddr[1]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[1]), .O(s_amesg[2])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[30]_i_1 (.I0(s_axi_araddr[29]), - .I1(s_axi_awaddr[29]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[29]), .O(s_amesg[30])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[31]_i_1 (.I0(s_axi_araddr[30]), - .I1(s_axi_awaddr[30]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[30]), .O(s_amesg[31])); LUT1 #( .INIT(2'h1)) \gen_no_arbiter.m_amesg_i[32]_i_1 (.I0(aresetn_d), - .O(SR)); + .O(reset)); LUT1 #( .INIT(2'h1)) \gen_no_arbiter.m_amesg_i[32]_i_2 (.I0(aa_grant_any), .O(p_0_in1_in)); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[32]_i_3 (.I0(s_axi_araddr[31]), - .I1(s_axi_awaddr[31]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[31]), .O(s_amesg[32])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[3]_i_1 (.I0(s_axi_araddr[2]), - .I1(s_axi_awaddr[2]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[2]), .O(s_amesg[3])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[46]_i_1 (.I0(s_axi_arprot[0]), - .I1(s_axi_awprot[0]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awprot[0]), .O(s_amesg[46])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[47]_i_1 (.I0(s_axi_arprot[1]), - .I1(s_axi_awprot[1]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awprot[1]), .O(s_amesg[47])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[48]_i_1 (.I0(s_axi_arprot[2]), - .I1(s_axi_awprot[2]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awprot[2]), .O(s_amesg[48])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[4]_i_1 (.I0(s_axi_araddr[3]), - .I1(s_axi_awaddr[3]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[3]), .O(s_amesg[4])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[5]_i_1 (.I0(s_axi_araddr[4]), - .I1(s_axi_awaddr[4]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[4]), .O(s_amesg[5])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[6]_i_1 (.I0(s_axi_araddr[5]), - .I1(s_axi_awaddr[5]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[5]), .O(s_amesg[6])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[7]_i_1 (.I0(s_axi_araddr[6]), - .I1(s_axi_awaddr[6]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[6]), .O(s_amesg[7])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[8]_i_1 (.I0(s_axi_araddr[7]), - .I1(s_axi_awaddr[7]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[7]), .O(s_amesg[8])); LUT4 #( - .INIT(16'hCCAC)) + .INIT(16'hFB08)) \gen_no_arbiter.m_amesg_i[9]_i_1 (.I0(s_axi_araddr[8]), - .I1(s_axi_awaddr[8]), - .I2(s_axi_arvalid), - .I3(s_awvalid_reg), + .I1(s_axi_arvalid), + .I2(s_awvalid_reg), + .I3(s_axi_awaddr[8]), .O(s_amesg[9])); FDRE \gen_no_arbiter.m_amesg_i_reg[10] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[10]), - .Q(Q[9]), - .R(SR)); + .Q(\m_axi_arprot[2] [9]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[11] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[11]), - .Q(Q[10]), - .R(SR)); + .Q(\m_axi_arprot[2] [10]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[12] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[12]), - .Q(Q[11]), - .R(SR)); + .Q(\m_axi_arprot[2] [11]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[13] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[13]), - .Q(Q[12]), - .R(SR)); + .Q(\m_axi_arprot[2] [12]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[14] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[14]), - .Q(Q[13]), - .R(SR)); + .Q(\m_axi_arprot[2] [13]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[15] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[15]), - .Q(Q[14]), - .R(SR)); + .Q(\m_axi_arprot[2] [14]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[16] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[16]), - .Q(Q[15]), - .R(SR)); + .Q(\m_axi_arprot[2] [15]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[17] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[17]), - .Q(Q[16]), - .R(SR)); + .Q(\m_axi_arprot[2] [16]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[18] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[18]), - .Q(Q[17]), - .R(SR)); + .Q(\m_axi_arprot[2] [17]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[19] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[19]), - .Q(Q[18]), - .R(SR)); + .Q(\m_axi_arprot[2] [18]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[1] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[1]), - .Q(Q[0]), - .R(SR)); + .Q(\m_axi_arprot[2] [0]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[20] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[20]), - .Q(Q[19]), - .R(SR)); + .Q(\m_axi_arprot[2] [19]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[21] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[21]), - .Q(Q[20]), - .R(SR)); + .Q(\m_axi_arprot[2] [20]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[22] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[22]), - .Q(Q[21]), - .R(SR)); + .Q(\m_axi_arprot[2] [21]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[23] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[23]), - .Q(Q[22]), - .R(SR)); + .Q(\m_axi_arprot[2] [22]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[24] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[24]), - .Q(Q[23]), - .R(SR)); + .Q(\m_axi_arprot[2] [23]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[25] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[25]), - .Q(Q[24]), - .R(SR)); + .Q(\m_axi_arprot[2] [24]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[26] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[26]), - .Q(Q[25]), - .R(SR)); + .Q(\m_axi_arprot[2] [25]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[27] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[27]), - .Q(Q[26]), - .R(SR)); + .Q(\m_axi_arprot[2] [26]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[28] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[28]), - .Q(Q[27]), - .R(SR)); + .Q(\m_axi_arprot[2] [27]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[29] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[29]), - .Q(Q[28]), - .R(SR)); + .Q(\m_axi_arprot[2] [28]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[2] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[2]), - .Q(Q[1]), - .R(SR)); + .Q(\m_axi_arprot[2] [1]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[30] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[30]), - .Q(Q[29]), - .R(SR)); + .Q(\m_axi_arprot[2] [29]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[31] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[31]), - .Q(Q[30]), - .R(SR)); + .Q(\m_axi_arprot[2] [30]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[32] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[32]), - .Q(Q[31]), - .R(SR)); + .Q(\m_axi_arprot[2] [31]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[3] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[3]), - .Q(Q[2]), - .R(SR)); + .Q(\m_axi_arprot[2] [2]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[46] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[46]), - .Q(Q[32]), - .R(SR)); + .Q(\m_axi_arprot[2] [32]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[47] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[47]), - .Q(Q[33]), - .R(SR)); + .Q(\m_axi_arprot[2] [33]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[48] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[48]), - .Q(Q[34]), - .R(SR)); + .Q(\m_axi_arprot[2] [34]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[4] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[4]), - .Q(Q[3]), - .R(SR)); + .Q(\m_axi_arprot[2] [3]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[5] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[5]), - .Q(Q[4]), - .R(SR)); + .Q(\m_axi_arprot[2] [4]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[6] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[6]), - .Q(Q[5]), - .R(SR)); + .Q(\m_axi_arprot[2] [5]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[7] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[7]), - .Q(Q[6]), - .R(SR)); + .Q(\m_axi_arprot[2] [6]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[8] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[8]), - .Q(Q[7]), - .R(SR)); + .Q(\m_axi_arprot[2] [7]), + .R(reset)); FDRE \gen_no_arbiter.m_amesg_i_reg[9] (.C(aclk), .CE(p_0_in1_in), .D(s_amesg[9]), - .Q(Q[8]), - .R(SR)); + .Q(\m_axi_arprot[2] [8]), + .R(reset)); LUT6 #( - .INIT(64'h0008880888888888)) + .INIT(64'h00000000F0FE0000)) \gen_no_arbiter.m_grant_hot_i[0]_i_1 - (.I0(\gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ), - .I1(aresetn_d), - .I2(aa_awready), - .I3(aa_grant_rnw), - .I4(\m_ready_d_reg[0]_1 ), - .I5(m_valid_i), - .O(\gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair5" *) - LUT4 #( - .INIT(16'hF0FE)) - \gen_no_arbiter.m_grant_hot_i[0]_i_2 (.I0(s_axi_arvalid), .I1(s_axi_awvalid), .I2(aa_grant_any), .I3(m_valid_i), - .O(\gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 )); + .I4(aresetn_d), + .I5(\gen_no_arbiter.m_valid_i_i_2_n_0 ), + .O(\gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 )); FDRE \gen_no_arbiter.m_grant_hot_i_reg[0] (.C(aclk), .CE(1'b1), .D(\gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ), .Q(aa_grant_any), .R(1'b0)); - LUT5 #( - .INIT(32'h47FF4700)) + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT3 #( + .INIT(8'h4E)) \gen_no_arbiter.m_valid_i_i_1 - (.I0(\m_ready_d_reg[0]_1 ), - .I1(aa_grant_rnw), - .I2(aa_awready), - .I3(m_valid_i), - .I4(aa_grant_any), + (.I0(m_valid_i), + .I1(aa_grant_any), + .I2(\gen_no_arbiter.m_valid_i_i_2_n_0 ), .O(\gen_no_arbiter.m_valid_i_i_1_n_0 )); + LUT6 #( + .INIT(64'h88888888888888F8)) + \gen_no_arbiter.m_valid_i_i_2 + (.I0(m_ready_d0), + .I1(\m_payload_i_reg[0] ), + .I2(m_ready_d0_0), + .I3(\m_ready_d_reg[0]_1 ), + .I4(\m_ready_d_reg[2] ), + .I5(\s_axi_wready[0]_INST_0_i_2_n_0 ), + .O(\gen_no_arbiter.m_valid_i_i_2_n_0 )); FDRE \gen_no_arbiter.m_valid_i_reg (.C(aclk), .CE(1'b1), .D(\gen_no_arbiter.m_valid_i_i_1_n_0 ), .Q(m_valid_i), - .R(SR)); - (* SOFT_HLUTNM = "soft_lutpair5" *) - LUT3 #( - .INIT(8'h20)) + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT2 #( + .INIT(4'h2)) \gen_no_arbiter.s_ready_i[0]_i_1 - (.I0(aresetn_d), + (.I0(aa_grant_any), .I1(m_valid_i), - .I2(aa_grant_any), - .O(s_ready_i0)); + .O(m_valid_i4_out)); FDRE \gen_no_arbiter.s_ready_i_reg[0] (.C(aclk), .CE(1'b1), - .D(s_ready_i0), + .D(m_valid_i4_out), .Q(s_ready_i), - .R(1'b0)); - LUT6 #( - .INIT(64'hFFFFFFFF55575555)) + .R(reset)); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT3 #( + .INIT(8'hBF)) \m_atarget_enc[0]_i_1 - (.I0(match), - .I1(\m_atarget_hot[9]_i_3_n_0 ), - .I2(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3 ), - .I3(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_4 ), - .I4(\m_atarget_hot[9]_i_6_n_0 ), - .I5(target_mi_enc[0]), + (.I0(\m_atarget_enc[0]_i_2_n_0 ), + .I1(\m_atarget_enc[0]_i_3_n_0 ), + .I2(\m_atarget_hot[11]_i_2_n_0 ), .O(\m_atarget_enc_reg[0] )); - (* SOFT_HLUTNM = "soft_lutpair6" *) - LUT4 #( - .INIT(16'hFFFE)) + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT5 #( + .INIT(32'hAAAAAAAB)) \m_atarget_enc[0]_i_2 - (.I0(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3 ), - .I1(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1 ), - .I2(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_5 ), - .I3(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_7 ), - .O(target_mi_enc[0])); - LUT6 #( - .INIT(64'hAA2A000000000000)) + (.I0(\m_atarget_hot[1]_i_2_n_0 ), + .I1(\m_atarget_hot[4]_i_2_n_0 ), + .I2(\m_axi_arprot[2] [23]), + .I3(\m_axi_arprot[2] [22]), + .I4(\m_atarget_hot[3]_i_3_n_0 ), + .O(\m_atarget_enc[0]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFF1FFFFFFFFF)) + \m_atarget_enc[0]_i_3 + (.I0(\m_axi_arprot[2] [16]), + .I1(\m_axi_arprot[2] [17]), + .I2(\m_atarget_hot[10]_i_3_n_0 ), + .I3(\m_axi_arprot[2] [18]), + .I4(\m_axi_arprot[2] [19]), + .I5(\m_atarget_hot[4]_i_3_n_0 ), + .O(\m_atarget_enc[0]_i_3_n_0 )); + LUT5 #( + .INIT(32'hFFFEFFFF)) \m_atarget_enc[1]_i_1 - (.I0(target_mi_enc[1]), - .I1(\m_atarget_hot[9]_i_6_n_0 ), - .I2(\m_atarget_hot[8]_i_2_n_0 ), - .I3(\m_atarget_hot[9]_i_3_n_0 ), - .I4(match), - .I5(aresetn_d), - .O(\m_atarget_enc_reg[2] [0])); - LUT4 #( - .INIT(16'hFFFE)) + (.I0(\m_atarget_enc[1]_i_2_n_0 ), + .I1(\m_atarget_hot[2]_i_2_n_0 ), + .I2(\m_atarget_hot[10]_i_2_n_0 ), + .I3(\m_atarget_hot[3]_i_2_n_0 ), + .I4(\m_atarget_hot[11]_i_2_n_0 ), + .O(\m_atarget_enc_reg[1] )); + LUT5 #( + .INIT(32'h23002000)) \m_atarget_enc[1]_i_2 - (.I0(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3 ), - .I1(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2 ), - .I2(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_6 ), - .I3(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_7 ), - .O(target_mi_enc[1])); - LUT6 #( - .INIT(64'hAA2A000000000000)) + (.I0(\m_atarget_hot[0]_i_2_n_0 ), + .I1(\m_atarget_enc[1]_i_3_n_0 ), + .I2(\m_axi_arprot[2] [16]), + .I3(\m_atarget_hot[10]_i_3_n_0 ), + .I4(\m_atarget_hot[4]_i_3_n_0 ), + .O(\m_atarget_enc[1]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT3 #( + .INIT(8'hEF)) + \m_atarget_enc[1]_i_3 + (.I0(\m_axi_arprot[2] [19]), + .I1(\m_axi_arprot[2] [18]), + .I2(\m_axi_arprot[2] [17]), + .O(\m_atarget_enc[1]_i_3_n_0 )); + LUT1 #( + .INIT(2'h1)) \m_atarget_enc[2]_i_1 - (.I0(target_mi_enc[2]), - .I1(\m_atarget_hot[9]_i_6_n_0 ), - .I2(\m_atarget_hot[8]_i_2_n_0 ), - .I3(\m_atarget_hot[9]_i_3_n_0 ), - .I4(match), - .I5(aresetn_d), - .O(\m_atarget_enc_reg[2] [1])); - LUT6 #( - .INIT(64'h8CCC000080000000)) - \m_atarget_enc[2]_i_2 - (.I0(\gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ), - .I1(\m_atarget_enc[2]_i_3_n_0 ), - .I2(Q[17]), - .I3(Q[16]), - .I4(\gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ), - .I5(\gen_addr_decoder.addr_decoder_inst/gen_target[7].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ), - .O(target_mi_enc[2])); - LUT2 #( - .INIT(4'h1)) - \m_atarget_enc[2]_i_3 - (.I0(Q[19]), - .I1(Q[18]), - .O(\m_atarget_enc[2]_i_3_n_0 )); + (.I0(\m_atarget_enc[3]_i_3_n_0 ), + .O(\m_atarget_enc_reg[2] )); LUT6 #( - .INIT(64'hFFFFFFFF55575555)) + .INIT(64'h000000000B030000)) \m_atarget_enc[3]_i_1 - (.I0(match), - .I1(\m_atarget_hot[9]_i_3_n_0 ), - .I2(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3 ), - .I3(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_4 ), - .I4(\m_atarget_hot[9]_i_6_n_0 ), - .I5(target_mi_enc[3]), + (.I0(\m_atarget_enc[3]_i_2_n_0 ), + .I1(\m_atarget_hot[0]_i_2_n_0 ), + .I2(\m_atarget_hot[3]_i_2_n_0 ), + .I3(\m_atarget_hot[4]_i_2_n_0 ), + .I4(\m_atarget_enc[3]_i_3_n_0 ), + .I5(\m_atarget_hot[2]_i_2_n_0 ), .O(\m_atarget_enc_reg[3] )); - LUT6 #( - .INIT(64'hAA2A000000000000)) + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT5 #( + .INIT(32'hFFFFFFDF)) + \m_atarget_enc[3]_i_2 + (.I0(\m_axi_arprot[2] [16]), + .I1(\m_axi_arprot[2] [17]), + .I2(\m_atarget_hot[10]_i_3_n_0 ), + .I3(\m_axi_arprot[2] [18]), + .I4(\m_axi_arprot[2] [19]), + .O(\m_atarget_enc[3]_i_2_n_0 )); + LUT6 #( + .INIT(64'hDCCCFFFFDFFFFFFF)) + \m_atarget_enc[3]_i_3 + (.I0(\m_atarget_hot[0]_i_2_n_0 ), + .I1(\m_atarget_enc[3]_i_4_n_0 ), + .I2(\m_axi_arprot[2] [17]), + .I3(\m_axi_arprot[2] [16]), + .I4(\m_atarget_hot[10]_i_3_n_0 ), + .I5(\m_atarget_hot[4]_i_3_n_0 ), + .O(\m_atarget_enc[3]_i_3_n_0 )); + LUT2 #( + .INIT(4'hE)) + \m_atarget_enc[3]_i_4 + (.I0(\m_axi_arprot[2] [18]), + .I1(\m_axi_arprot[2] [19]), + .O(\m_atarget_enc[3]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT4 #( + .INIT(16'h4000)) \m_atarget_hot[0]_i_1 - (.I0(aa_grant_any), - .I1(\m_atarget_hot[9]_i_6_n_0 ), - .I2(\m_atarget_hot[8]_i_2_n_0 ), - .I3(\m_atarget_hot[9]_i_3_n_0 ), - .I4(match), - .I5(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0 ), + (.I0(\m_atarget_hot[4]_i_2_n_0 ), + .I1(\m_atarget_hot[0]_i_2_n_0 ), + .I2(\m_atarget_hot[11]_i_2_n_0 ), + .I3(aa_grant_any), .O(D[0])); LUT6 #( - .INIT(64'h0000000200000000)) + .INIT(64'h0000001000000000)) \m_atarget_hot[0]_i_2 - (.I0(\gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ), - .I1(Q[18]), - .I2(Q[19]), - .I3(Q[17]), - .I4(Q[16]), - .I5(\gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ), - .O(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0 )); - LUT6 #( - .INIT(64'hAA2A000000000000)) - \m_atarget_hot[1]_i_1 + (.I0(\m_axi_arprot[2] [22]), + .I1(\m_axi_arprot[2] [23]), + .I2(\m_axi_arprot[2] [21]), + .I3(\m_axi_arprot[2] [20]), + .I4(\m_axi_arprot[2] [25]), + .I5(\m_axi_arprot[2] [24]), + .O(\m_atarget_hot[0]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT3 #( + .INIT(8'h80)) + \m_atarget_hot[10]_i_1 + (.I0(\m_atarget_hot[10]_i_2_n_0 ), + .I1(\m_atarget_hot[11]_i_2_n_0 ), + .I2(aa_grant_any), + .O(D[10])); + LUT6 #( + .INIT(64'h0000000040000000)) + \m_atarget_hot[10]_i_2 + (.I0(\m_axi_arprot[2] [17]), + .I1(\m_axi_arprot[2] [16]), + .I2(\m_atarget_hot[0]_i_2_n_0 ), + .I3(\m_atarget_hot[10]_i_3_n_0 ), + .I4(\m_axi_arprot[2] [18]), + .I5(\m_axi_arprot[2] [19]), + .O(\m_atarget_hot[10]_i_2_n_0 )); + LUT6 #( + .INIT(64'h0000000100000000)) + \m_atarget_hot[10]_i_3 + (.I0(\m_axi_arprot[2] [28]), + .I1(\m_axi_arprot[2] [29]), + .I2(\m_axi_arprot[2] [26]), + .I3(\m_axi_arprot[2] [27]), + .I4(\m_axi_arprot[2] [31]), + .I5(\m_axi_arprot[2] [30]), + .O(\m_atarget_hot[10]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT2 #( + .INIT(4'h2)) + \m_atarget_hot[11]_i_1 (.I0(aa_grant_any), - .I1(\m_atarget_hot[9]_i_6_n_0 ), - .I2(\m_atarget_hot[8]_i_2_n_0 ), - .I3(\m_atarget_hot[9]_i_3_n_0 ), - .I4(match), - .I5(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1 ), + .I1(\m_atarget_hot[11]_i_2_n_0 ), + .O(D[11])); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFEFF)) + \m_atarget_hot[11]_i_2 + (.I0(\m_atarget_hot[9]_i_2_n_0 ), + .I1(\m_atarget_hot[11]_i_3_n_0 ), + .I2(\m_atarget_hot[2]_i_2_n_0 ), + .I3(\m_atarget_enc[3]_i_3_n_0 ), + .I4(\m_atarget_hot[11]_i_4_n_0 ), + .I5(\m_atarget_enc[0]_i_2_n_0 ), + .O(\m_atarget_hot[11]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT5 #( + .INIT(32'h00004000)) + \m_atarget_hot[11]_i_3 + (.I0(\m_axi_arprot[2] [19]), + .I1(\m_axi_arprot[2] [18]), + .I2(\m_atarget_hot[10]_i_3_n_0 ), + .I3(\m_atarget_hot[0]_i_2_n_0 ), + .I4(\m_axi_arprot[2] [17]), + .O(\m_atarget_hot[11]_i_3_n_0 )); + LUT6 #( + .INIT(64'h0000000000000200)) + \m_atarget_hot[11]_i_4 + (.I0(\m_atarget_hot[0]_i_2_n_0 ), + .I1(\m_axi_arprot[2] [19]), + .I2(\m_axi_arprot[2] [18]), + .I3(\m_atarget_hot[10]_i_3_n_0 ), + .I4(\m_axi_arprot[2] [17]), + .I5(\m_axi_arprot[2] [16]), + .O(\m_atarget_hot[11]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT3 #( + .INIT(8'h80)) + \m_atarget_hot[1]_i_1 + (.I0(\m_atarget_hot[1]_i_2_n_0 ), + .I1(\m_atarget_hot[11]_i_2_n_0 ), + .I2(aa_grant_any), .O(D[1])); LUT6 #( .INIT(64'h0000020000000000)) \m_atarget_hot[1]_i_2 - (.I0(\gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ), - .I1(Q[18]), - .I2(Q[19]), - .I3(Q[16]), - .I4(Q[17]), - .I5(\gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ), - .O(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1 )); - LUT6 #( - .INIT(64'hAA2A000000000000)) + (.I0(\m_atarget_hot[0]_i_2_n_0 ), + .I1(\m_axi_arprot[2] [19]), + .I2(\m_axi_arprot[2] [18]), + .I3(\m_atarget_hot[10]_i_3_n_0 ), + .I4(\m_axi_arprot[2] [17]), + .I5(\m_axi_arprot[2] [16]), + .O(\m_atarget_hot[1]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT3 #( + .INIT(8'h80)) \m_atarget_hot[2]_i_1 - (.I0(aa_grant_any), - .I1(\m_atarget_hot[9]_i_6_n_0 ), - .I2(\m_atarget_hot[8]_i_2_n_0 ), - .I3(\m_atarget_hot[9]_i_3_n_0 ), - .I4(match), - .I5(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2 ), + (.I0(\m_atarget_hot[2]_i_2_n_0 ), + .I1(\m_atarget_hot[11]_i_2_n_0 ), + .I2(aa_grant_any), .O(D[2])); LUT6 #( - .INIT(64'h0000020000000000)) + .INIT(64'h0000000000000800)) \m_atarget_hot[2]_i_2 - (.I0(\gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ), - .I1(Q[18]), - .I2(Q[19]), - .I3(Q[17]), - .I4(Q[16]), - .I5(\gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ), - .O(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2 )); - (* SOFT_HLUTNM = "soft_lutpair20" *) + (.I0(\m_atarget_hot[0]_i_2_n_0 ), + .I1(\m_atarget_hot[10]_i_3_n_0 ), + .I2(\m_axi_arprot[2] [16]), + .I3(\m_axi_arprot[2] [17]), + .I4(\m_axi_arprot[2] [18]), + .I5(\m_axi_arprot[2] [19]), + .O(\m_atarget_hot[2]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair26" *) LUT3 #( .INIT(8'h80)) \m_atarget_hot[3]_i_1 - (.I0(aa_grant_any), - .I1(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3 ), - .I2(match), + (.I0(\m_atarget_hot[3]_i_2_n_0 ), + .I1(\m_atarget_hot[11]_i_2_n_0 ), + .I2(aa_grant_any), .O(D[3])); - (* SOFT_HLUTNM = "soft_lutpair20" *) - LUT3 #( - .INIT(8'h80)) + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'h0001)) + \m_atarget_hot[3]_i_2 + (.I0(\m_atarget_hot[3]_i_3_n_0 ), + .I1(\m_axi_arprot[2] [22]), + .I2(\m_axi_arprot[2] [23]), + .I3(\m_atarget_hot[4]_i_2_n_0 ), + .O(\m_atarget_hot[3]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFFDF)) + \m_atarget_hot[3]_i_3 + (.I0(\m_axi_arprot[2] [25]), + .I1(\m_axi_arprot[2] [21]), + .I2(\m_axi_arprot[2] [24]), + .I3(\m_axi_arprot[2] [20]), + .O(\m_atarget_hot[3]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT4 #( + .INIT(16'h4000)) \m_atarget_hot[4]_i_1 - (.I0(aa_grant_any), - .I1(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_4 ), - .I2(match), + (.I0(\m_atarget_hot[4]_i_2_n_0 ), + .I1(\m_atarget_hot[4]_i_3_n_0 ), + .I2(\m_atarget_hot[11]_i_2_n_0 ), + .I3(aa_grant_any), .O(D[4])); - LUT6 #( - .INIT(64'hAA2A000000000000)) + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT5 #( + .INIT(32'hFFFFFFEF)) + \m_atarget_hot[4]_i_2 + (.I0(\m_axi_arprot[2] [16]), + .I1(\m_axi_arprot[2] [17]), + .I2(\m_atarget_hot[10]_i_3_n_0 ), + .I3(\m_axi_arprot[2] [18]), + .I4(\m_axi_arprot[2] [19]), + .O(\m_atarget_hot[4]_i_2_n_0 )); + LUT6 #( + .INIT(64'h0000080000000000)) + \m_atarget_hot[4]_i_3 + (.I0(\m_axi_arprot[2] [23]), + .I1(\m_axi_arprot[2] [22]), + .I2(\m_axi_arprot[2] [20]), + .I3(\m_axi_arprot[2] [24]), + .I4(\m_axi_arprot[2] [21]), + .I5(\m_axi_arprot[2] [25]), + .O(\m_atarget_hot[4]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT3 #( + .INIT(8'h80)) \m_atarget_hot[5]_i_1 - (.I0(aa_grant_any), - .I1(\m_atarget_hot[9]_i_6_n_0 ), - .I2(\m_atarget_hot[8]_i_2_n_0 ), - .I3(\m_atarget_hot[9]_i_3_n_0 ), - .I4(match), - .I5(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_5 ), + (.I0(\m_atarget_hot[5]_i_2_n_0 ), + .I1(\m_atarget_hot[11]_i_2_n_0 ), + .I2(aa_grant_any), .O(D[5])); LUT6 #( .INIT(64'h0000020000000000)) \m_atarget_hot[5]_i_2 - (.I0(\gen_addr_decoder.addr_decoder_inst/gen_target[7].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ), - .I1(Q[18]), - .I2(Q[19]), - .I3(Q[16]), - .I4(Q[17]), - .I5(\gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ), - .O(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_5 )); - LUT6 #( - .INIT(64'hAA2A000000000000)) + (.I0(\m_atarget_hot[4]_i_3_n_0 ), + .I1(\m_axi_arprot[2] [19]), + .I2(\m_axi_arprot[2] [18]), + .I3(\m_atarget_hot[10]_i_3_n_0 ), + .I4(\m_axi_arprot[2] [17]), + .I5(\m_axi_arprot[2] [16]), + .O(\m_atarget_hot[5]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT3 #( + .INIT(8'h80)) \m_atarget_hot[6]_i_1 - (.I0(aa_grant_any), - .I1(\m_atarget_hot[9]_i_6_n_0 ), - .I2(\m_atarget_hot[8]_i_2_n_0 ), - .I3(\m_atarget_hot[9]_i_3_n_0 ), - .I4(match), - .I5(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_6 ), + (.I0(\m_atarget_hot[6]_i_2_n_0 ), + .I1(\m_atarget_hot[11]_i_2_n_0 ), + .I2(aa_grant_any), .O(D[6])); LUT6 #( - .INIT(64'h0200000000000000)) + .INIT(64'h0000008000000000)) \m_atarget_hot[6]_i_2 - (.I0(\gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ), - .I1(Q[18]), - .I2(Q[19]), - .I3(Q[17]), - .I4(Q[16]), - .I5(\gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ), - .O(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_6 )); - LUT6 #( - .INIT(64'hAA2A000000000000)) + (.I0(\m_atarget_hot[0]_i_2_n_0 ), + .I1(\m_atarget_hot[10]_i_3_n_0 ), + .I2(\m_axi_arprot[2] [17]), + .I3(\m_axi_arprot[2] [18]), + .I4(\m_axi_arprot[2] [19]), + .I5(\m_axi_arprot[2] [16]), + .O(\m_atarget_hot[6]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT3 #( + .INIT(8'h80)) \m_atarget_hot[7]_i_1 - (.I0(aa_grant_any), - .I1(\m_atarget_hot[9]_i_6_n_0 ), - .I2(\m_atarget_hot[8]_i_2_n_0 ), - .I3(\m_atarget_hot[9]_i_3_n_0 ), - .I4(match), - .I5(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_7 ), + (.I0(\m_atarget_hot[7]_i_2_n_0 ), + .I1(\m_atarget_hot[11]_i_2_n_0 ), + .I2(aa_grant_any), .O(D[7])); LUT6 #( - .INIT(64'h0000020000000000)) + .INIT(64'h0000000000000800)) \m_atarget_hot[7]_i_2 - (.I0(\gen_addr_decoder.addr_decoder_inst/gen_target[7].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ), - .I1(Q[18]), - .I2(Q[19]), - .I3(Q[17]), - .I4(Q[16]), - .I5(\gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ), - .O(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_7 )); - LUT6 #( - .INIT(64'hAA2A000000000000)) + (.I0(\m_atarget_hot[4]_i_3_n_0 ), + .I1(\m_atarget_hot[10]_i_3_n_0 ), + .I2(\m_axi_arprot[2] [16]), + .I3(\m_axi_arprot[2] [17]), + .I4(\m_axi_arprot[2] [18]), + .I5(\m_axi_arprot[2] [19]), + .O(\m_atarget_hot[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT3 #( + .INIT(8'h80)) \m_atarget_hot[8]_i_1 - (.I0(aa_grant_any), - .I1(\m_atarget_hot[9]_i_6_n_0 ), - .I2(\m_atarget_hot[8]_i_2_n_0 ), - .I3(\m_atarget_hot[9]_i_3_n_0 ), - .I4(match), - .I5(target_mi_enc[3]), + (.I0(\m_atarget_hot[8]_i_2_n_0 ), + .I1(\m_atarget_hot[11]_i_2_n_0 ), + .I2(aa_grant_any), .O(D[8])); - (* SOFT_HLUTNM = "soft_lutpair6" *) - LUT2 #( - .INIT(4'h1)) + LUT6 #( + .INIT(64'h0000000010000000)) \m_atarget_hot[8]_i_2 - (.I0(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_4 ), - .I1(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3 ), + (.I0(\m_axi_arprot[2] [17]), + .I1(\m_axi_arprot[2] [16]), + .I2(\m_atarget_hot[0]_i_2_n_0 ), + .I3(\m_atarget_hot[10]_i_3_n_0 ), + .I4(\m_axi_arprot[2] [18]), + .I5(\m_axi_arprot[2] [19]), .O(\m_atarget_hot[8]_i_2_n_0 )); - LUT6 #( - .INIT(64'h0000020000000000)) - \m_atarget_hot[8]_i_3 - (.I0(\gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ), - .I1(Q[19]), - .I2(Q[17]), - .I3(Q[18]), - .I4(Q[16]), - .I5(\gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ), - .O(target_mi_enc[3])); - LUT6 #( - .INIT(64'h0001000000000000)) - \m_atarget_hot[8]_i_4 - (.I0(Q[25]), - .I1(Q[22]), - .I2(Q[23]), - .I3(Q[20]), - .I4(Q[21]), - .I5(Q[24]), - .O(\gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 )); - LUT6 #( - .INIT(64'h2222222A22222222)) + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT3 #( + .INIT(8'h80)) \m_atarget_hot[9]_i_1 - (.I0(aa_grant_any), - .I1(match), - .I2(\m_atarget_hot[9]_i_3_n_0 ), - .I3(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3 ), - .I4(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_4 ), - .I5(\m_atarget_hot[9]_i_6_n_0 ), + (.I0(\m_atarget_hot[9]_i_2_n_0 ), + .I1(\m_atarget_hot[11]_i_2_n_0 ), + .I2(aa_grant_any), .O(D[9])); LUT6 #( - .INIT(64'h0000000000000100)) - \m_atarget_hot[9]_i_10 - (.I0(Q[31]), - .I1(Q[28]), - .I2(Q[29]), - .I3(Q[30]), - .I4(Q[26]), - .I5(Q[27]), - .O(\gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 )); - LUT6 #( - .INIT(64'h0400000000000000)) - \m_atarget_hot[9]_i_11 - (.I0(Q[21]), - .I1(Q[24]), - .I2(Q[20]), - .I3(Q[25]), - .I4(Q[22]), - .I5(Q[23]), - .O(\gen_addr_decoder.addr_decoder_inst/gen_target[7].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 )); - LUT4 #( - .INIT(16'hFEFF)) + .INIT(64'h0000008000000000)) \m_atarget_hot[9]_i_2 - (.I0(\m_atarget_hot[9]_i_7_n_0 ), - .I1(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3 ), - .I2(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_4 ), - .I3(\m_atarget_hot[9]_i_8_n_0 ), - .O(match)); - LUT6 #( - .INIT(64'hFFFFFFFFFFFFFF02)) - \m_atarget_hot[9]_i_3 - (.I0(\m_atarget_hot[9]_i_8_n_0 ), - .I1(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_4 ), - .I2(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3 ), - .I3(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0 ), - .I4(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2 ), - .I5(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1 ), - .O(\m_atarget_hot[9]_i_3_n_0 )); - LUT6 #( - .INIT(64'h0000000200000000)) - \m_atarget_hot[9]_i_4 - (.I0(\gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3__4 ), - .I1(Q[18]), - .I2(Q[19]), - .I3(Q[17]), - .I4(Q[16]), - .I5(\gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ), - .O(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3 )); - LUT6 #( - .INIT(64'h0000000200000000)) - \m_atarget_hot[9]_i_5 - (.I0(\gen_addr_decoder.addr_decoder_inst/gen_target[7].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ), - .I1(Q[18]), - .I2(Q[19]), - .I3(Q[17]), - .I4(Q[16]), - .I5(\gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ), - .O(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_4 )); - (* SOFT_HLUTNM = "soft_lutpair7" *) - LUT4 #( - .INIT(16'h0001)) - \m_atarget_hot[9]_i_6 - (.I0(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_7 ), - .I1(target_mi_enc[3]), - .I2(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_5 ), - .I3(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_6 ), - .O(\m_atarget_hot[9]_i_6_n_0 )); - LUT6 #( - .INIT(64'h0002020200000000)) - \m_atarget_hot[9]_i_7 - (.I0(\gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ), - .I1(Q[18]), - .I2(Q[19]), - .I3(Q[16]), - .I4(Q[17]), - .I5(\gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ), - .O(\m_atarget_hot[9]_i_7_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair7" *) - LUT4 #( - .INIT(16'h0001)) - \m_atarget_hot[9]_i_8 - (.I0(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_7 ), - .I1(target_mi_enc[3]), - .I2(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_6 ), - .I3(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_5 ), - .O(\m_atarget_hot[9]_i_8_n_0 )); - LUT6 #( - .INIT(64'h0001000000000000)) - \m_atarget_hot[9]_i_9 - (.I0(Q[23]), - .I1(Q[21]), - .I2(Q[22]), - .I3(Q[20]), - .I4(Q[25]), - .I5(Q[24]), - .O(\gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3__4 )); - (* SOFT_HLUTNM = "soft_lutpair14" *) + (.I0(\m_atarget_hot[4]_i_3_n_0 ), + .I1(\m_atarget_hot[10]_i_3_n_0 ), + .I2(\m_axi_arprot[2] [17]), + .I3(\m_axi_arprot[2] [18]), + .I4(\m_axi_arprot[2] [19]), + .I5(\m_axi_arprot[2] [16]), + .O(\m_atarget_hot[9]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair20" *) LUT4 #( - .INIT(16'h2000)) + .INIT(16'h0080)) \m_axi_arvalid[0]_INST_0 - (.I0(\m_atarget_hot_reg[9] [0]), - .I1(m_ready_d[1]), - .I2(aa_grant_rnw), - .I3(m_valid_i), + (.I0(Q[0]), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(m_ready_d_1[1]), .O(m_axi_arvalid[0])); - (* SOFT_HLUTNM = "soft_lutpair13" *) + (* SOFT_HLUTNM = "soft_lutpair12" *) LUT4 #( - .INIT(16'h2000)) + .INIT(16'h0080)) + \m_axi_arvalid[10]_INST_0 + (.I0(Q[10]), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(m_ready_d_1[1]), + .O(m_axi_arvalid[10])); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT4 #( + .INIT(16'h0080)) \m_axi_arvalid[1]_INST_0 - (.I0(\m_atarget_hot_reg[9] [1]), - .I1(m_ready_d[1]), - .I2(aa_grant_rnw), - .I3(m_valid_i), + (.I0(Q[1]), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(m_ready_d_1[1]), .O(m_axi_arvalid[1])); - (* SOFT_HLUTNM = "soft_lutpair13" *) + (* SOFT_HLUTNM = "soft_lutpair18" *) LUT4 #( - .INIT(16'h2000)) + .INIT(16'h0080)) \m_axi_arvalid[2]_INST_0 - (.I0(\m_atarget_hot_reg[9] [2]), - .I1(m_ready_d[1]), - .I2(aa_grant_rnw), - .I3(m_valid_i), + (.I0(Q[2]), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(m_ready_d_1[1]), .O(m_axi_arvalid[2])); - (* SOFT_HLUTNM = "soft_lutpair12" *) + (* SOFT_HLUTNM = "soft_lutpair17" *) LUT4 #( - .INIT(16'h2000)) + .INIT(16'h0080)) \m_axi_arvalid[3]_INST_0 - (.I0(\m_atarget_hot_reg[9] [3]), - .I1(m_ready_d[1]), - .I2(aa_grant_rnw), - .I3(m_valid_i), + (.I0(Q[3]), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(m_ready_d_1[1]), .O(m_axi_arvalid[3])); - (* SOFT_HLUTNM = "soft_lutpair12" *) + (* SOFT_HLUTNM = "soft_lutpair16" *) LUT4 #( - .INIT(16'h2000)) + .INIT(16'h0080)) \m_axi_arvalid[4]_INST_0 - (.I0(\m_atarget_hot_reg[9] [4]), - .I1(m_ready_d[1]), - .I2(aa_grant_rnw), - .I3(m_valid_i), + (.I0(Q[4]), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(m_ready_d_1[1]), .O(m_axi_arvalid[4])); - (* SOFT_HLUTNM = "soft_lutpair11" *) + (* SOFT_HLUTNM = "soft_lutpair19" *) LUT4 #( - .INIT(16'h2000)) + .INIT(16'h0080)) \m_axi_arvalid[5]_INST_0 - (.I0(\m_atarget_hot_reg[9] [5]), - .I1(m_ready_d[1]), - .I2(aa_grant_rnw), - .I3(m_valid_i), + (.I0(Q[5]), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(m_ready_d_1[1]), .O(m_axi_arvalid[5])); - (* SOFT_HLUTNM = "soft_lutpair11" *) + (* SOFT_HLUTNM = "soft_lutpair15" *) LUT4 #( - .INIT(16'h2000)) + .INIT(16'h0080)) \m_axi_arvalid[6]_INST_0 - (.I0(\m_atarget_hot_reg[9] [6]), - .I1(m_ready_d[1]), - .I2(aa_grant_rnw), - .I3(m_valid_i), + (.I0(Q[6]), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(m_ready_d_1[1]), .O(m_axi_arvalid[6])); - (* SOFT_HLUTNM = "soft_lutpair10" *) + (* SOFT_HLUTNM = "soft_lutpair14" *) LUT4 #( - .INIT(16'h2000)) + .INIT(16'h0080)) \m_axi_arvalid[7]_INST_0 - (.I0(\m_atarget_hot_reg[9] [7]), - .I1(m_ready_d[1]), - .I2(aa_grant_rnw), - .I3(m_valid_i), + (.I0(Q[7]), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(m_ready_d_1[1]), .O(m_axi_arvalid[7])); - (* SOFT_HLUTNM = "soft_lutpair9" *) + (* SOFT_HLUTNM = "soft_lutpair13" *) LUT4 #( - .INIT(16'h2000)) + .INIT(16'h0080)) \m_axi_arvalid[8]_INST_0 - (.I0(\m_atarget_hot_reg[9] [8]), - .I1(m_ready_d[1]), - .I2(aa_grant_rnw), - .I3(m_valid_i), + (.I0(Q[8]), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(m_ready_d_1[1]), .O(m_axi_arvalid[8])); - (* SOFT_HLUTNM = "soft_lutpair14" *) + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT4 #( + .INIT(16'h0080)) + \m_axi_arvalid[9]_INST_0 + (.I0(Q[9]), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(m_ready_d_1[1]), + .O(m_axi_arvalid[9])); + (* SOFT_HLUTNM = "soft_lutpair20" *) LUT4 #( .INIT(16'h0020)) \m_axi_awvalid[0]_INST_0 - (.I0(\m_atarget_hot_reg[9] [0]), - .I1(m_ready_d_0[2]), + (.I0(Q[0]), + .I1(aa_grant_rnw), .I2(m_valid_i), - .I3(aa_grant_rnw), + .I3(m_ready_d[2]), .O(m_axi_awvalid[0])); - (* SOFT_HLUTNM = "soft_lutpair16" *) + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT4 #( + .INIT(16'h0020)) + \m_axi_awvalid[10]_INST_0 + (.I0(Q[10]), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(m_ready_d[2]), + .O(m_axi_awvalid[10])); + (* SOFT_HLUTNM = "soft_lutpair21" *) LUT4 #( .INIT(16'h0020)) \m_axi_awvalid[1]_INST_0 - (.I0(\m_atarget_hot_reg[9] [1]), - .I1(m_ready_d_0[2]), + (.I0(Q[1]), + .I1(aa_grant_rnw), .I2(m_valid_i), - .I3(aa_grant_rnw), + .I3(m_ready_d[2]), .O(m_axi_awvalid[1])); - (* SOFT_HLUTNM = "soft_lutpair17" *) + (* SOFT_HLUTNM = "soft_lutpair18" *) LUT4 #( .INIT(16'h0020)) \m_axi_awvalid[2]_INST_0 - (.I0(\m_atarget_hot_reg[9] [2]), - .I1(m_ready_d_0[2]), + (.I0(Q[2]), + .I1(aa_grant_rnw), .I2(m_valid_i), - .I3(aa_grant_rnw), + .I3(m_ready_d[2]), .O(m_axi_awvalid[2])); - (* SOFT_HLUTNM = "soft_lutpair18" *) + (* SOFT_HLUTNM = "soft_lutpair17" *) LUT4 #( .INIT(16'h0020)) \m_axi_awvalid[3]_INST_0 - (.I0(\m_atarget_hot_reg[9] [3]), - .I1(m_ready_d_0[2]), + (.I0(Q[3]), + .I1(aa_grant_rnw), .I2(m_valid_i), - .I3(aa_grant_rnw), + .I3(m_ready_d[2]), .O(m_axi_awvalid[3])); - (* SOFT_HLUTNM = "soft_lutpair19" *) + (* SOFT_HLUTNM = "soft_lutpair16" *) LUT4 #( .INIT(16'h0020)) \m_axi_awvalid[4]_INST_0 - (.I0(\m_atarget_hot_reg[9] [4]), - .I1(m_ready_d_0[2]), + (.I0(Q[4]), + .I1(aa_grant_rnw), .I2(m_valid_i), - .I3(aa_grant_rnw), + .I3(m_ready_d[2]), .O(m_axi_awvalid[4])); - (* SOFT_HLUTNM = "soft_lutpair18" *) + (* SOFT_HLUTNM = "soft_lutpair19" *) LUT4 #( .INIT(16'h0020)) \m_axi_awvalid[5]_INST_0 - (.I0(\m_atarget_hot_reg[9] [5]), - .I1(m_ready_d_0[2]), + (.I0(Q[5]), + .I1(aa_grant_rnw), .I2(m_valid_i), - .I3(aa_grant_rnw), + .I3(m_ready_d[2]), .O(m_axi_awvalid[5])); - (* SOFT_HLUTNM = "soft_lutpair17" *) + (* SOFT_HLUTNM = "soft_lutpair15" *) LUT4 #( .INIT(16'h0020)) \m_axi_awvalid[6]_INST_0 - (.I0(\m_atarget_hot_reg[9] [6]), - .I1(m_ready_d_0[2]), + (.I0(Q[6]), + .I1(aa_grant_rnw), .I2(m_valid_i), - .I3(aa_grant_rnw), + .I3(m_ready_d[2]), .O(m_axi_awvalid[6])); - (* SOFT_HLUTNM = "soft_lutpair16" *) + (* SOFT_HLUTNM = "soft_lutpair14" *) LUT4 #( .INIT(16'h0020)) \m_axi_awvalid[7]_INST_0 - (.I0(\m_atarget_hot_reg[9] [7]), - .I1(m_ready_d_0[2]), + (.I0(Q[7]), + .I1(aa_grant_rnw), .I2(m_valid_i), - .I3(aa_grant_rnw), + .I3(m_ready_d[2]), .O(m_axi_awvalid[7])); - (* SOFT_HLUTNM = "soft_lutpair19" *) + (* SOFT_HLUTNM = "soft_lutpair13" *) LUT4 #( .INIT(16'h0020)) \m_axi_awvalid[8]_INST_0 - (.I0(\m_atarget_hot_reg[9] [8]), - .I1(m_ready_d_0[2]), + (.I0(Q[8]), + .I1(aa_grant_rnw), .I2(m_valid_i), - .I3(aa_grant_rnw), + .I3(m_ready_d[2]), .O(m_axi_awvalid[8])); - LUT5 #( - .INIT(32'h00200000)) - \m_axi_bready[0]_INST_0 - (.I0(\m_atarget_hot_reg[9] [0]), + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT4 #( + .INIT(16'h0020)) + \m_axi_awvalid[9]_INST_0 + (.I0(Q[9]), .I1(aa_grant_rnw), .I2(m_valid_i), - .I3(m_ready_d_0[0]), - .I4(s_axi_bready), + .I3(m_ready_d[2]), + .O(m_axi_awvalid[9])); + LUT5 #( + .INIT(32'h00000800)) + \m_axi_bready[0]_INST_0 + (.I0(Q[0]), + .I1(s_axi_bready), + .I2(m_ready_d[0]), + .I3(m_valid_i), + .I4(aa_grant_rnw), .O(m_axi_bready[0])); + (* SOFT_HLUTNM = "soft_lutpair0" *) LUT5 #( - .INIT(32'h00200000)) + .INIT(32'h00000800)) + \m_axi_bready[10]_INST_0 + (.I0(Q[10]), + .I1(s_axi_bready), + .I2(m_ready_d[0]), + .I3(m_valid_i), + .I4(aa_grant_rnw), + .O(m_axi_bready[10])); + LUT5 #( + .INIT(32'h00000800)) \m_axi_bready[1]_INST_0 - (.I0(\m_atarget_hot_reg[9] [1]), - .I1(aa_grant_rnw), - .I2(m_valid_i), - .I3(m_ready_d_0[0]), - .I4(s_axi_bready), + (.I0(Q[1]), + .I1(s_axi_bready), + .I2(m_ready_d[0]), + .I3(m_valid_i), + .I4(aa_grant_rnw), .O(m_axi_bready[1])); - (* SOFT_HLUTNM = "soft_lutpair3" *) LUT5 #( - .INIT(32'h00200000)) + .INIT(32'h00000800)) \m_axi_bready[2]_INST_0 - (.I0(\m_atarget_hot_reg[9] [2]), - .I1(aa_grant_rnw), - .I2(m_valid_i), - .I3(m_ready_d_0[0]), - .I4(s_axi_bready), + (.I0(Q[2]), + .I1(s_axi_bready), + .I2(m_ready_d[0]), + .I3(m_valid_i), + .I4(aa_grant_rnw), .O(m_axi_bready[2])); - (* SOFT_HLUTNM = "soft_lutpair2" *) LUT5 #( - .INIT(32'h00200000)) + .INIT(32'h00000800)) \m_axi_bready[3]_INST_0 - (.I0(\m_atarget_hot_reg[9] [3]), - .I1(aa_grant_rnw), - .I2(m_valid_i), - .I3(m_ready_d_0[0]), - .I4(s_axi_bready), + (.I0(Q[3]), + .I1(s_axi_bready), + .I2(m_ready_d[0]), + .I3(m_valid_i), + .I4(aa_grant_rnw), .O(m_axi_bready[3])); LUT5 #( - .INIT(32'h00200000)) + .INIT(32'h00000800)) \m_axi_bready[4]_INST_0 - (.I0(\m_atarget_hot_reg[9] [4]), - .I1(aa_grant_rnw), - .I2(m_valid_i), - .I3(m_ready_d_0[0]), - .I4(s_axi_bready), + (.I0(Q[4]), + .I1(s_axi_bready), + .I2(m_ready_d[0]), + .I3(m_valid_i), + .I4(aa_grant_rnw), .O(m_axi_bready[4])); LUT5 #( - .INIT(32'h00200000)) + .INIT(32'h00000800)) \m_axi_bready[5]_INST_0 - (.I0(\m_atarget_hot_reg[9] [5]), - .I1(aa_grant_rnw), - .I2(m_valid_i), - .I3(m_ready_d_0[0]), - .I4(s_axi_bready), + (.I0(Q[5]), + .I1(s_axi_bready), + .I2(m_ready_d[0]), + .I3(m_valid_i), + .I4(aa_grant_rnw), .O(m_axi_bready[5])); LUT5 #( - .INIT(32'h00200000)) + .INIT(32'h00000800)) \m_axi_bready[6]_INST_0 - (.I0(\m_atarget_hot_reg[9] [6]), - .I1(aa_grant_rnw), - .I2(m_valid_i), - .I3(m_ready_d_0[0]), - .I4(s_axi_bready), + (.I0(Q[6]), + .I1(s_axi_bready), + .I2(m_ready_d[0]), + .I3(m_valid_i), + .I4(aa_grant_rnw), .O(m_axi_bready[6])); LUT5 #( - .INIT(32'h00200000)) + .INIT(32'h00000800)) \m_axi_bready[7]_INST_0 - (.I0(\m_atarget_hot_reg[9] [7]), - .I1(aa_grant_rnw), - .I2(m_valid_i), - .I3(m_ready_d_0[0]), - .I4(s_axi_bready), + (.I0(Q[7]), + .I1(s_axi_bready), + .I2(m_ready_d[0]), + .I3(m_valid_i), + .I4(aa_grant_rnw), .O(m_axi_bready[7])); LUT5 #( - .INIT(32'h00200000)) + .INIT(32'h00000800)) \m_axi_bready[8]_INST_0 - (.I0(\m_atarget_hot_reg[9] [8]), - .I1(aa_grant_rnw), - .I2(m_valid_i), - .I3(m_ready_d_0[0]), - .I4(s_axi_bready), + (.I0(Q[8]), + .I1(s_axi_bready), + .I2(m_ready_d[0]), + .I3(m_valid_i), + .I4(aa_grant_rnw), .O(m_axi_bready[8])); LUT5 #( .INIT(32'h00000800)) - \m_axi_wvalid[0]_INST_0 - (.I0(\m_atarget_hot_reg[9] [0]), - .I1(s_axi_wvalid), - .I2(aa_grant_rnw), + \m_axi_bready[9]_INST_0 + (.I0(Q[9]), + .I1(s_axi_bready), + .I2(m_ready_d[0]), .I3(m_valid_i), - .I4(m_ready_d_0[1]), + .I4(aa_grant_rnw), + .O(m_axi_bready[9])); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT5 #( + .INIT(32'h00002000)) + \m_axi_wvalid[0]_INST_0 + (.I0(Q[0]), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(s_axi_wvalid), + .I4(m_ready_d[1]), .O(m_axi_wvalid[0])); + LUT5 #( + .INIT(32'h00002000)) + \m_axi_wvalid[10]_INST_0 + (.I0(Q[10]), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(s_axi_wvalid), + .I4(m_ready_d[1]), + .O(m_axi_wvalid[10])); (* SOFT_HLUTNM = "soft_lutpair1" *) LUT5 #( - .INIT(32'h00000800)) + .INIT(32'h00002000)) \m_axi_wvalid[1]_INST_0 - (.I0(\m_atarget_hot_reg[9] [1]), - .I1(s_axi_wvalid), - .I2(aa_grant_rnw), - .I3(m_valid_i), - .I4(m_ready_d_0[1]), + (.I0(Q[1]), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(s_axi_wvalid), + .I4(m_ready_d[1]), .O(m_axi_wvalid[1])); LUT5 #( - .INIT(32'h00000800)) + .INIT(32'h00002000)) \m_axi_wvalid[2]_INST_0 - (.I0(\m_atarget_hot_reg[9] [2]), - .I1(s_axi_wvalid), - .I2(aa_grant_rnw), - .I3(m_valid_i), - .I4(m_ready_d_0[1]), + (.I0(Q[2]), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(s_axi_wvalid), + .I4(m_ready_d[1]), .O(m_axi_wvalid[2])); LUT5 #( - .INIT(32'h00000800)) + .INIT(32'h00002000)) \m_axi_wvalid[3]_INST_0 - (.I0(\m_atarget_hot_reg[9] [3]), - .I1(s_axi_wvalid), - .I2(aa_grant_rnw), - .I3(m_valid_i), - .I4(m_ready_d_0[1]), + (.I0(Q[3]), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(s_axi_wvalid), + .I4(m_ready_d[1]), .O(m_axi_wvalid[3])); LUT5 #( - .INIT(32'h00000800)) + .INIT(32'h00002000)) \m_axi_wvalid[4]_INST_0 - (.I0(\m_atarget_hot_reg[9] [4]), - .I1(s_axi_wvalid), - .I2(aa_grant_rnw), - .I3(m_valid_i), - .I4(m_ready_d_0[1]), + (.I0(Q[4]), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(s_axi_wvalid), + .I4(m_ready_d[1]), .O(m_axi_wvalid[4])); - (* SOFT_HLUTNM = "soft_lutpair0" *) + (* SOFT_HLUTNM = "soft_lutpair2" *) LUT5 #( - .INIT(32'h00000800)) + .INIT(32'h00002000)) \m_axi_wvalid[5]_INST_0 - (.I0(\m_atarget_hot_reg[9] [5]), - .I1(s_axi_wvalid), - .I2(aa_grant_rnw), - .I3(m_valid_i), - .I4(m_ready_d_0[1]), + (.I0(Q[5]), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(s_axi_wvalid), + .I4(m_ready_d[1]), .O(m_axi_wvalid[5])); LUT5 #( - .INIT(32'h00000800)) + .INIT(32'h00002000)) \m_axi_wvalid[6]_INST_0 - (.I0(\m_atarget_hot_reg[9] [6]), - .I1(s_axi_wvalid), - .I2(aa_grant_rnw), - .I3(m_valid_i), - .I4(m_ready_d_0[1]), + (.I0(Q[6]), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(s_axi_wvalid), + .I4(m_ready_d[1]), .O(m_axi_wvalid[6])); LUT5 #( - .INIT(32'h00000800)) + .INIT(32'h00002000)) \m_axi_wvalid[7]_INST_0 - (.I0(\m_atarget_hot_reg[9] [7]), - .I1(s_axi_wvalid), - .I2(aa_grant_rnw), - .I3(m_valid_i), - .I4(m_ready_d_0[1]), + (.I0(Q[7]), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(s_axi_wvalid), + .I4(m_ready_d[1]), .O(m_axi_wvalid[7])); LUT5 #( - .INIT(32'h00000800)) + .INIT(32'h00002000)) \m_axi_wvalid[8]_INST_0 - (.I0(\m_atarget_hot_reg[9] [8]), - .I1(s_axi_wvalid), - .I2(aa_grant_rnw), - .I3(m_valid_i), - .I4(m_ready_d_0[1]), + (.I0(Q[8]), + .I1(aa_grant_rnw), + .I2(m_valid_i), + .I3(s_axi_wvalid), + .I4(m_ready_d[1]), .O(m_axi_wvalid[8])); - (* SOFT_HLUTNM = "soft_lutpair4" *) LUT5 #( - .INIT(32'h0800FFFF)) - \m_payload_i[34]_i_1 - (.I0(m_valid_i), + .INIT(32'h00002000)) + \m_axi_wvalid[9]_INST_0 + (.I0(Q[9]), .I1(aa_grant_rnw), - .I2(m_ready_d[0]), - .I3(s_axi_rready), - .I4(sr_rvalid), - .O(E)); - (* SOFT_HLUTNM = "soft_lutpair4" *) - LUT3 #( - .INIT(8'h08)) + .I2(m_valid_i), + .I3(s_axi_wvalid), + .I4(m_ready_d[1]), + .O(m_axi_wvalid[9])); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT5 #( + .INIT(32'h0080FFFF)) + \m_payload_i[34]_i_1 + (.I0(aa_grant_rnw), + .I1(m_valid_i), + .I2(s_axi_rready), + .I3(m_ready_d_1[0]), + .I4(sr_rvalid), + .O(E)); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT2 #( + .INIT(4'h7)) \m_ready_d[0]_i_2 - (.I0(m_valid_i), - .I1(aa_grant_rnw), - .I2(m_ready_d[0]), - .O(\m_ready_d_reg[0] )); - (* SOFT_HLUTNM = "soft_lutpair3" *) - LUT3 #( - .INIT(8'h04)) - \m_ready_d[0]_i_2__0 (.I0(aa_grant_rnw), .I1(m_valid_i), - .I2(m_ready_d_0[0]), .O(\m_ready_d_reg[0]_0 )); - (* SOFT_HLUTNM = "soft_lutpair9" *) LUT3 #( - .INIT(8'h08)) + .INIT(8'h4F)) + \m_ready_d[0]_i_3 + (.I0(\m_ready_d_reg[1]_0 ), + .I1(m_ready_d0), + .I2(aresetn_d), + .O(\m_ready_d_reg[0] )); + LUT6 #( + .INIT(64'hAAAAFFBFAAAAFFFF)) \m_ready_d[1]_i_2 - (.I0(m_valid_i), - .I1(aa_grant_rnw), - .I2(m_ready_d[1]), + (.I0(\m_ready_d_reg[2] ), + .I1(s_axi_bready), + .I2(m_valid_i), + .I3(aa_grant_rnw), + .I4(m_ready_d[0]), + .I5(\m_atarget_enc_reg[2]_0 ), .O(\m_ready_d_reg[1] )); - (* SOFT_HLUTNM = "soft_lutpair1" *) - LUT3 #( - .INIT(8'h04)) - \m_ready_d[1]_i_2__0 - (.I0(aa_grant_rnw), - .I1(m_valid_i), - .I2(m_ready_d_0[1]), - .O(\m_ready_d_reg[1]_0 )); - LUT6 #( - .INIT(64'hA808FFFFA8080000)) - \m_ready_d[1]_i_5 - (.I0(\m_ready_d[1]_i_7_n_0 ), - .I1(m_axi_arready[1]), - .I2(m_atarget_enc[2]), - .I3(m_axi_arready[4]), - .I4(m_atarget_enc[1]), - .I5(\m_ready_d[1]_i_8_n_0 ), - .O(\m_ready_d_reg[1]_1 )); LUT6 #( - .INIT(64'hA808FFFFA8080000)) - \m_ready_d[1]_i_6 - (.I0(\m_ready_d[1]_i_7_n_0 ), - .I1(m_axi_arready[2]), - .I2(m_atarget_enc[2]), - .I3(m_axi_arready[5]), - .I4(m_atarget_enc[1]), - .I5(\gen_axilite.s_axi_arready_i_reg ), - .O(\m_ready_d_reg[1]_2 )); - (* SOFT_HLUTNM = "soft_lutpair10" *) - LUT4 #( - .INIT(16'h0040)) - \m_ready_d[1]_i_7 - (.I0(m_ready_d[1]), - .I1(aa_grant_rnw), + .INIT(64'hFFFFFFFF55555455)) + \m_ready_d[1]_i_2__0 + (.I0(\m_ready_d_reg[0]_0 ), + .I1(\m_atarget_enc_reg[2]_6 ), + .I2(\m_atarget_enc_reg[2]_7 ), + .I3(\m_atarget_enc_reg[3]_4 ), + .I4(\m_atarget_enc_reg[2]_8 ), + .I5(m_ready_d_1[1]), + .O(m_ready_d0)); + LUT6 #( + .INIT(64'h1555555555555555)) + \m_ready_d[1]_i_3 + (.I0(m_ready_d_1[0]), + .I1(s_axi_rready), .I2(m_valid_i), - .I3(m_atarget_enc[3]), - .O(\m_ready_d[1]_i_7_n_0 )); - LUT6 #( - .INIT(64'h00CC88C0000088C0)) - \m_ready_d[1]_i_8 - (.I0(m_axi_arready[6]), - .I1(\m_ready_d_reg[1] ), - .I2(m_axi_arready[0]), - .I3(m_atarget_enc[3]), - .I4(m_atarget_enc[2]), - .I5(m_axi_arready[3]), - .O(\m_ready_d[1]_i_8_n_0 )); - LUT6 #( - .INIT(64'h30BB000000880000)) - \m_ready_d[2]_i_10 - (.I0(\m_atarget_enc_reg[2]_0 ), - .I1(m_atarget_enc[1]), - .I2(m_axi_wready[6]), - .I3(m_atarget_enc[3]), - .I4(\m_ready_d_reg[1]_0 ), - .I5(\m_atarget_enc_reg[2]_1 ), - .O(\m_ready_d[2]_i_10_n_0 )); - LUT6 #( - .INIT(64'h30BB000000880000)) - \m_ready_d[2]_i_11 - (.I0(\m_atarget_enc_reg[2]_2 ), - .I1(m_atarget_enc[1]), - .I2(m_axi_bvalid[6]), - .I3(m_atarget_enc[3]), - .I4(\m_ready_d_reg[0]_0 ), - .I5(\m_atarget_enc_reg[2]_3 ), - .O(\m_ready_d[2]_i_11_n_0 )); + .I3(aa_grant_rnw), + .I4(sr_rvalid), + .I5(\m_payload_i_reg[0]_0 ), + .O(\m_ready_d_reg[1]_0 )); LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) + .INIT(64'hFFFFFFFF54550000)) \m_ready_d[2]_i_2 - (.I0(\m_ready_d[2]_i_4_n_0 ), - .I1(\gen_axilite.s_axi_awready_i_reg_0 ), - .I2(m_atarget_enc[0]), - .I3(\m_ready_d[2]_i_6_n_0 ), - .I4(m_atarget_enc[1]), - .I5(\m_ready_d[2]_i_7_n_0 ), - .O(mi_awready_mux)); - LUT6 #( - .INIT(64'hEEE0EEE0EEE00000)) - \m_ready_d[2]_i_3 - (.I0(p_0_out__0[1]), - .I1(m_ready_d_0[1]), - .I2(m_ready_d_0[2]), - .I3(mi_awready_mux), - .I4(m_ready_d_0[0]), - .I5(p_0_out__0[0]), - .O(aa_awready)); + (.I0(\s_axi_wready[0]_INST_0_i_2_n_0 ), + .I1(\m_atarget_enc_reg[2]_1 ), + .I2(\m_atarget_enc_reg[2]_2 ), + .I3(\m_atarget_enc_reg[3]_0 ), + .I4(s_axi_wvalid), + .I5(m_ready_d[1]), + .O(m_ready_d0_0)); LUT5 #( - .INIT(32'h44400040)) + .INIT(32'h00000001)) \m_ready_d[2]_i_4 - (.I0(m_atarget_enc[3]), - .I1(\gen_axilite.s_axi_bvalid_i_reg ), - .I2(m_axi_awready[2]), - .I3(m_atarget_enc[2]), - .I4(m_axi_awready[5]), - .O(\m_ready_d[2]_i_4_n_0 )); - LUT5 #( - .INIT(32'h44400040)) + (.I0(m_ready_d[2]), + .I1(\m_ready_d[2]_i_6_n_0 ), + .I2(\m_ready_d[2]_i_7_n_0 ), + .I3(\m_ready_d[2]_i_8_n_0 ), + .I4(\m_atarget_enc_reg[2]_4 ), + .O(\m_ready_d_reg[2] )); + LUT6 #( + .INIT(64'h0000000000003B38)) \m_ready_d[2]_i_6 - (.I0(m_atarget_enc[3]), - .I1(\gen_axilite.s_axi_bvalid_i_reg ), - .I2(m_axi_awready[1]), - .I3(m_atarget_enc[2]), - .I4(m_axi_awready[4]), + (.I0(m_axi_awready[3]), + .I1(m_atarget_enc[2]), + .I2(m_atarget_enc[3]), + .I3(m_axi_awready[1]), + .I4(\gen_axilite.s_axi_bvalid_i_reg_0 ), + .I5(\m_atarget_enc_reg[3]_2 ), .O(\m_ready_d[2]_i_6_n_0 )); LUT6 #( - .INIT(64'h00CC88C0000088C0)) + .INIT(64'h0000000000003B38)) \m_ready_d[2]_i_7 - (.I0(m_axi_awready[6]), - .I1(\gen_axilite.s_axi_bvalid_i_reg ), - .I2(m_axi_awready[0]), - .I3(m_atarget_enc[3]), - .I4(m_atarget_enc[2]), - .I5(m_axi_awready[3]), + (.I0(m_axi_awready[2]), + .I1(m_atarget_enc[2]), + .I2(m_atarget_enc[3]), + .I3(m_axi_awready[0]), + .I4(\gen_axilite.s_axi_bvalid_i_reg_0 ), + .I5(\m_atarget_enc_reg[3]_3 ), .O(\m_ready_d[2]_i_7_n_0 )); LUT6 #( - .INIT(64'hA8A8A8080808A808)) + .INIT(64'h00000000000000B0)) \m_ready_d[2]_i_8 - (.I0(p_4_in), - .I1(\m_ready_d[2]_i_10_n_0 ), - .I2(m_atarget_enc[0]), - .I3(\gen_axilite.s_axi_awready_i_reg ), - .I4(m_atarget_enc[1]), - .I5(\s_axi_wready[0]_INST_0_i_2_n_0 ), - .O(p_0_out__0[1])); - LUT6 #( - .INIT(64'hA8A8A8080808A808)) - \m_ready_d[2]_i_9 - (.I0(p_3_in), - .I1(\m_ready_d[2]_i_11_n_0 ), - .I2(m_atarget_enc[0]), - .I3(\gen_axilite.s_axi_bvalid_i_reg_1 ), - .I4(m_atarget_enc[1]), - .I5(\s_axi_bvalid[0]_INST_0_i_2_n_0 ), - .O(p_0_out__0[0])); - MUXF7 \m_ready_d_reg[1]_i_4 - (.I0(\m_ready_d_reg[1]_1 ), - .I1(\m_ready_d_reg[1]_2 ), - .O(mi_arready_mux), - .S(m_atarget_enc[0])); - LUT6 #( - .INIT(64'hA808FFFFA8080000)) - m_valid_i_i_3 - (.I0(m_valid_i_i_5_n_0), - .I1(m_axi_rvalid[1]), - .I2(m_atarget_enc[2]), - .I3(m_axi_rvalid[4]), - .I4(m_atarget_enc[1]), - .I5(m_valid_i_i_6_n_0), - .O(m_valid_i_i_3_n_0)); - LUT6 #( - .INIT(64'hA808FFFFA8080000)) - m_valid_i_i_4 - (.I0(m_valid_i_i_5_n_0), - .I1(m_axi_rvalid[2]), - .I2(m_atarget_enc[2]), - .I3(m_axi_rvalid[5]), - .I4(m_atarget_enc[1]), - .I5(\gen_axilite.s_axi_rvalid_i_reg ), - .O(m_valid_i_i_4_n_0)); - (* SOFT_HLUTNM = "soft_lutpair15" *) - LUT4 #( - .INIT(16'h0040)) - m_valid_i_i_5 - (.I0(m_ready_d[0]), + (.I0(m_axi_awready[4]), + .I1(m_atarget_enc[3]), + .I2(m_atarget_enc[1]), + .I3(m_atarget_enc[0]), + .I4(\gen_axilite.s_axi_bvalid_i_reg_0 ), + .I5(\m_atarget_enc_reg[2]_5 ), + .O(\m_ready_d[2]_i_8_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT3 #( + .INIT(8'h08)) + m_valid_i_i_7 + (.I0(m_valid_i), .I1(aa_grant_rnw), - .I2(m_valid_i), - .I3(m_atarget_enc[3]), - .O(m_valid_i_i_5_n_0)); - LUT6 #( - .INIT(64'h00CC88C0000088C0)) - m_valid_i_i_6 - (.I0(m_axi_rvalid[6]), - .I1(\m_ready_d_reg[0] ), - .I2(m_axi_rvalid[0]), - .I3(m_atarget_enc[3]), - .I4(m_atarget_enc[2]), - .I5(m_axi_rvalid[3]), - .O(m_valid_i_i_6_n_0)); - MUXF7 m_valid_i_reg_i_2 - (.I0(m_valid_i_i_3_n_0), - .I1(m_valid_i_i_4_n_0), - .O(aa_rvalid), - .S(m_atarget_enc[0])); - (* SOFT_HLUTNM = "soft_lutpair8" *) + .I2(m_ready_d_1[0]), + .O(s_ready_i_reg)); + (* SOFT_HLUTNM = "soft_lutpair10" *) LUT4 #( .INIT(16'h0040)) \s_arvalid_reg[0]_i_1 @@ -2079,11 +2054,11 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_addr_arbiter_sasd .Q(\s_arvalid_reg_reg_n_0_[0] ), .R(1'b0)); LUT6 #( - .INIT(64'h0000000000A20000)) + .INIT(64'h0000000000D00000)) \s_awvalid_reg[0]_i_1 - (.I0(s_axi_awvalid), - .I1(s_axi_arvalid), - .I2(s_awvalid_reg), + (.I0(s_axi_arvalid), + .I1(s_awvalid_reg), + .I2(s_axi_awvalid), .I3(\s_arvalid_reg_reg_n_0_[0] ), .I4(aresetn_d), .I5(s_ready_i), @@ -2094,132 +2069,77 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_addr_arbiter_sasd .D(\s_awvalid_reg[0]_i_1_n_0 ), .Q(s_awvalid_reg), .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair28" *) LUT2 #( .INIT(4'h8)) \s_axi_arready[0]_INST_0 - (.I0(aa_grant_rnw), - .I1(s_ready_i), + (.I0(s_ready_i), + .I1(aa_grant_rnw), .O(s_axi_arready)); - (* SOFT_HLUTNM = "soft_lutpair8" *) + (* SOFT_HLUTNM = "soft_lutpair10" *) LUT2 #( .INIT(4'h2)) \s_axi_awready[0]_INST_0 (.I0(s_ready_i), .I1(aa_grant_rnw), .O(s_axi_awready)); - LUT2 #( - .INIT(4'h8)) + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT5 #( + .INIT(32'h00400000)) \s_axi_bvalid[0]_INST_0 - (.I0(aa_grant_any), - .I1(aa_bvalid), + (.I0(aa_grant_rnw), + .I1(m_valid_i), + .I2(aa_grant_any), + .I3(m_ready_d[0]), + .I4(\m_atarget_enc_reg[2]_0 ), .O(s_axi_bvalid)); - LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) - \s_axi_bvalid[0]_INST_0_i_1 - (.I0(\s_axi_bvalid[0]_INST_0_i_2_n_0 ), - .I1(\gen_axilite.s_axi_bvalid_i_reg_1 ), - .I2(m_atarget_enc[0]), - .I3(\s_axi_bvalid[0]_INST_0_i_4_n_0 ), - .I4(m_atarget_enc[1]), - .I5(\s_axi_bvalid[0]_INST_0_i_5_n_0 ), - .O(aa_bvalid)); - LUT5 #( - .INIT(32'h44400040)) - \s_axi_bvalid[0]_INST_0_i_2 - (.I0(m_atarget_enc[3]), - .I1(\m_ready_d_reg[0]_0 ), - .I2(m_axi_bvalid[2]), - .I3(m_atarget_enc[2]), - .I4(m_axi_bvalid[5]), - .O(\s_axi_bvalid[0]_INST_0_i_2_n_0 )); - LUT5 #( - .INIT(32'h44400040)) - \s_axi_bvalid[0]_INST_0_i_4 - (.I0(m_atarget_enc[3]), - .I1(\m_ready_d_reg[0]_0 ), - .I2(m_axi_bvalid[1]), - .I3(m_atarget_enc[2]), - .I4(m_axi_bvalid[4]), - .O(\s_axi_bvalid[0]_INST_0_i_4_n_0 )); - LUT6 #( - .INIT(64'h00CC88C0000088C0)) - \s_axi_bvalid[0]_INST_0_i_5 - (.I0(m_axi_bvalid[6]), - .I1(\m_ready_d_reg[0]_0 ), - .I2(m_axi_bvalid[0]), - .I3(m_atarget_enc[3]), - .I4(m_atarget_enc[2]), - .I5(m_axi_bvalid[3]), - .O(\s_axi_bvalid[0]_INST_0_i_5_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair21" *) LUT2 #( .INIT(4'h8)) \s_axi_rvalid[0]_INST_0 (.I0(aa_grant_any), .I1(sr_rvalid), .O(s_axi_rvalid)); - (* SOFT_HLUTNM = "soft_lutpair21" *) + (* SOFT_HLUTNM = "soft_lutpair29" *) LUT2 #( - .INIT(4'h8)) + .INIT(4'h2)) \s_axi_wready[0]_INST_0 (.I0(aa_grant_any), - .I1(aa_wready), + .I1(\s_axi_wready[0]_INST_0_i_1_n_0 ), .O(s_axi_wready)); LUT6 #( - .INIT(64'hAFA0CFCFAFA0C0C0)) + .INIT(64'hEEEFEEEEEEEEEEEE)) \s_axi_wready[0]_INST_0_i_1 (.I0(\s_axi_wready[0]_INST_0_i_2_n_0 ), - .I1(\gen_axilite.s_axi_awready_i_reg ), - .I2(m_atarget_enc[0]), - .I3(\s_axi_wready[0]_INST_0_i_4_n_0 ), - .I4(m_atarget_enc[1]), - .I5(\s_axi_wready[0]_INST_0_i_5_n_0 ), - .O(aa_wready)); - LUT5 #( - .INIT(32'h44400040)) + .I1(m_ready_d[1]), + .I2(\m_atarget_enc_reg[2]_1 ), + .I3(\m_atarget_enc_reg[2]_2 ), + .I4(\m_atarget_enc_reg[3]_1 ), + .I5(\m_atarget_enc_reg[2]_3 ), + .O(\s_axi_wready[0]_INST_0_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT2 #( + .INIT(4'hB)) \s_axi_wready[0]_INST_0_i_2 - (.I0(m_atarget_enc[3]), - .I1(\m_ready_d_reg[1]_0 ), - .I2(m_axi_wready[2]), - .I3(m_atarget_enc[2]), - .I4(m_axi_wready[5]), + (.I0(aa_grant_rnw), + .I1(m_valid_i), .O(\s_axi_wready[0]_INST_0_i_2_n_0 )); - LUT5 #( - .INIT(32'h44400040)) - \s_axi_wready[0]_INST_0_i_4 - (.I0(m_atarget_enc[3]), - .I1(\m_ready_d_reg[1]_0 ), - .I2(m_axi_wready[1]), - .I3(m_atarget_enc[2]), - .I4(m_axi_wready[4]), - .O(\s_axi_wready[0]_INST_0_i_4_n_0 )); - LUT6 #( - .INIT(64'h00CC88C0000088C0)) - \s_axi_wready[0]_INST_0_i_5 - (.I0(m_axi_wready[6]), - .I1(\m_ready_d_reg[1]_0 ), - .I2(m_axi_wready[0]), - .I3(m_atarget_enc[3]), - .I4(m_atarget_enc[2]), - .I5(m_axi_wready[3]), - .O(\s_axi_wready[0]_INST_0_i_5_n_0 )); endmodule (* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "32" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_PROTOCOL = "2" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_CONNECTIVITY_MODE = "0" *) (* C_DEBUG = "1" *) -(* C_FAMILY = "zynq" *) (* C_M_AXI_ADDR_WIDTH = "288'b000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000" *) (* C_M_AXI_BASE_ADDR = "576'b000000000000000000000000000000000100000100100100000000000000000000000000000000000000000000000000010000111100001000000000000000000000000000000000000000000000000001000001001000110000000000000000000000000000000000000000000000000100001111000001000000000000000000000000000000000000000000000000010000111100000000000000000000000000000000000000000000000000000001000011000000000000000000000000000000000000000000000000000000000100000100100010000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000" *) -(* C_M_AXI_READ_CONNECTIVITY = "288'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_READ_ISSUING = "288'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_SECURE = "288'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) -(* C_M_AXI_WRITE_CONNECTIVITY = "288'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_WRITE_ISSUING = "288'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_NUM_ADDR_RANGES = "1" *) -(* C_NUM_MASTER_SLOTS = "9" *) (* C_NUM_SLAVE_SLOTS = "1" *) (* C_R_REGISTER = "1" *) +(* C_FAMILY = "zynq" *) (* C_M_AXI_ADDR_WIDTH = "352'b0000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000" *) (* C_M_AXI_BASE_ADDR = "704'b00000000000000000000000000000000010000010010010100000000000000000000000000000000000000000000000001000011110000110000000000000000000000000000000000000000000000000100000100100100000000000000000000000000000000000000000000000000010000111100001000000000000000000000000000000000000000000000000001000001001000110000000000000000000000000000000000000000000000000100001111000001000000000000000000000000000000000000000000000000010000111100000000000000000000000000000000000000000000000000000001000011000000000000000000000000000000000000000000000000000000000100000100100010000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000" *) +(* C_M_AXI_READ_CONNECTIVITY = "352'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_READ_ISSUING = "352'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_SECURE = "352'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) +(* C_M_AXI_WRITE_CONNECTIVITY = "352'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_WRITE_ISSUING = "352'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_NUM_ADDR_RANGES = "1" *) +(* C_NUM_MASTER_SLOTS = "11" *) (* C_NUM_SLAVE_SLOTS = "1" *) (* C_R_REGISTER = "1" *) (* C_S_AXI_ARB_PRIORITY = "0" *) (* C_S_AXI_BASE_ID = "0" *) (* C_S_AXI_READ_ACCEPTANCE = "1" *) (* C_S_AXI_SINGLE_THREAD = "1" *) (* C_S_AXI_THREAD_ID_WIDTH = "0" *) (* C_S_AXI_WRITE_ACCEPTANCE = "1" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "axi_crossbar_v2_1_12_axi_crossbar" *) (* P_ADDR_DECODE = "1" *) (* P_AXI3 = "1" *) (* P_AXI4 = "0" *) (* P_AXILITE = "2" *) (* P_AXILITE_SIZE = "3'b010" *) (* P_FAMILY = "zynq" *) (* P_INCR = "2'b01" *) -(* P_LEN = "8" *) (* P_LOCK = "1" *) (* P_M_AXI_ERR_MODE = "288'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) -(* P_M_AXI_SUPPORTS_READ = "9'b111111111" *) (* P_M_AXI_SUPPORTS_WRITE = "9'b111111111" *) (* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *) +(* P_LEN = "8" *) (* P_LOCK = "1" *) (* P_M_AXI_ERR_MODE = "352'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) +(* P_M_AXI_SUPPORTS_READ = "11'b11111111111" *) (* P_M_AXI_SUPPORTS_WRITE = "11'b11111111111" *) (* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *) (* P_RANGE_CHECK = "1" *) (* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* P_S_AXI_SUPPORTS_READ = "1'b1" *) (* P_S_AXI_SUPPORTS_WRITE = "1'b1" *) module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar @@ -2358,71 +2278,71 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar output [0:0]s_axi_ruser; output [0:0]s_axi_rvalid; input [0:0]s_axi_rready; - output [8:0]m_axi_awid; - output [287:0]m_axi_awaddr; - output [71:0]m_axi_awlen; - output [26:0]m_axi_awsize; - output [17:0]m_axi_awburst; - output [8:0]m_axi_awlock; - output [35:0]m_axi_awcache; - output [26:0]m_axi_awprot; - output [35:0]m_axi_awregion; - output [35:0]m_axi_awqos; - output [8:0]m_axi_awuser; - output [8:0]m_axi_awvalid; - input [8:0]m_axi_awready; - output [8:0]m_axi_wid; - output [287:0]m_axi_wdata; - output [35:0]m_axi_wstrb; - output [8:0]m_axi_wlast; - output [8:0]m_axi_wuser; - output [8:0]m_axi_wvalid; - input [8:0]m_axi_wready; - input [8:0]m_axi_bid; - input [17:0]m_axi_bresp; - input [8:0]m_axi_buser; - input [8:0]m_axi_bvalid; - output [8:0]m_axi_bready; - output [8:0]m_axi_arid; - output [287:0]m_axi_araddr; - output [71:0]m_axi_arlen; - output [26:0]m_axi_arsize; - output [17:0]m_axi_arburst; - output [8:0]m_axi_arlock; - output [35:0]m_axi_arcache; - output [26:0]m_axi_arprot; - output [35:0]m_axi_arregion; - output [35:0]m_axi_arqos; - output [8:0]m_axi_aruser; - output [8:0]m_axi_arvalid; - input [8:0]m_axi_arready; - input [8:0]m_axi_rid; - input [287:0]m_axi_rdata; - input [17:0]m_axi_rresp; - input [8:0]m_axi_rlast; - input [8:0]m_axi_ruser; - input [8:0]m_axi_rvalid; - output [8:0]m_axi_rready; + output [10:0]m_axi_awid; + output [351:0]m_axi_awaddr; + output [87:0]m_axi_awlen; + output [32:0]m_axi_awsize; + output [21:0]m_axi_awburst; + output [10:0]m_axi_awlock; + output [43:0]m_axi_awcache; + output [32:0]m_axi_awprot; + output [43:0]m_axi_awregion; + output [43:0]m_axi_awqos; + output [10:0]m_axi_awuser; + output [10:0]m_axi_awvalid; + input [10:0]m_axi_awready; + output [10:0]m_axi_wid; + output [351:0]m_axi_wdata; + output [43:0]m_axi_wstrb; + output [10:0]m_axi_wlast; + output [10:0]m_axi_wuser; + output [10:0]m_axi_wvalid; + input [10:0]m_axi_wready; + input [10:0]m_axi_bid; + input [21:0]m_axi_bresp; + input [10:0]m_axi_buser; + input [10:0]m_axi_bvalid; + output [10:0]m_axi_bready; + output [10:0]m_axi_arid; + output [351:0]m_axi_araddr; + output [87:0]m_axi_arlen; + output [32:0]m_axi_arsize; + output [21:0]m_axi_arburst; + output [10:0]m_axi_arlock; + output [43:0]m_axi_arcache; + output [32:0]m_axi_arprot; + output [43:0]m_axi_arregion; + output [43:0]m_axi_arqos; + output [10:0]m_axi_aruser; + output [10:0]m_axi_arvalid; + input [10:0]m_axi_arready; + input [10:0]m_axi_rid; + input [351:0]m_axi_rdata; + input [21:0]m_axi_rresp; + input [10:0]m_axi_rlast; + input [10:0]m_axi_ruser; + input [10:0]m_axi_rvalid; + output [10:0]m_axi_rready; wire \ ; wire aclk; wire aresetn; wire [15:0]\^m_axi_araddr ; wire [2:0]\^m_axi_arprot ; - wire [8:0]m_axi_arready; - wire [8:0]m_axi_arvalid; - wire [287:272]\^m_axi_awaddr ; - wire [8:0]m_axi_awready; - wire [8:0]m_axi_awvalid; - wire [8:0]m_axi_bready; - wire [17:0]m_axi_bresp; - wire [8:0]m_axi_bvalid; - wire [287:0]m_axi_rdata; - wire [8:0]m_axi_rready; - wire [17:0]m_axi_rresp; - wire [8:0]m_axi_rvalid; - wire [8:0]m_axi_wready; - wire [8:0]m_axi_wvalid; + wire [10:0]m_axi_arready; + wire [10:0]m_axi_arvalid; + wire [351:336]\^m_axi_awaddr ; + wire [10:0]m_axi_awready; + wire [10:0]m_axi_awvalid; + wire [10:0]m_axi_bready; + wire [21:0]m_axi_bresp; + wire [10:0]m_axi_bvalid; + wire [351:0]m_axi_rdata; + wire [10:0]m_axi_rready; + wire [21:0]m_axi_rresp; + wire [10:0]m_axi_rvalid; + wire [10:0]m_axi_wready; + wire [10:0]m_axi_wvalid; wire [31:0]s_axi_araddr; wire [2:0]s_axi_arprot; wire [0:0]s_axi_arready; @@ -2443,24 +2363,32 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar wire [3:0]s_axi_wstrb; wire [0:0]s_axi_wvalid; - assign m_axi_araddr[287:272] = \^m_axi_awaddr [287:272]; + assign m_axi_araddr[351:336] = \^m_axi_awaddr [351:336]; + assign m_axi_araddr[335:320] = \^m_axi_araddr [15:0]; + assign m_axi_araddr[319:304] = \^m_axi_awaddr [351:336]; + assign m_axi_araddr[303:288] = \^m_axi_araddr [15:0]; + assign m_axi_araddr[287:272] = \^m_axi_awaddr [351:336]; assign m_axi_araddr[271:256] = \^m_axi_araddr [15:0]; - assign m_axi_araddr[255:240] = \^m_axi_awaddr [287:272]; + assign m_axi_araddr[255:240] = \^m_axi_awaddr [351:336]; assign m_axi_araddr[239:224] = \^m_axi_araddr [15:0]; - assign m_axi_araddr[223:208] = \^m_axi_awaddr [287:272]; + assign m_axi_araddr[223:208] = \^m_axi_awaddr [351:336]; assign m_axi_araddr[207:192] = \^m_axi_araddr [15:0]; - assign m_axi_araddr[191:176] = \^m_axi_awaddr [287:272]; + assign m_axi_araddr[191:176] = \^m_axi_awaddr [351:336]; assign m_axi_araddr[175:160] = \^m_axi_araddr [15:0]; - assign m_axi_araddr[159:144] = \^m_axi_awaddr [287:272]; + assign m_axi_araddr[159:144] = \^m_axi_awaddr [351:336]; assign m_axi_araddr[143:128] = \^m_axi_araddr [15:0]; - assign m_axi_araddr[127:112] = \^m_axi_awaddr [287:272]; + assign m_axi_araddr[127:112] = \^m_axi_awaddr [351:336]; assign m_axi_araddr[111:96] = \^m_axi_araddr [15:0]; - assign m_axi_araddr[95:80] = \^m_axi_awaddr [287:272]; + assign m_axi_araddr[95:80] = \^m_axi_awaddr [351:336]; assign m_axi_araddr[79:64] = \^m_axi_araddr [15:0]; - assign m_axi_araddr[63:48] = \^m_axi_awaddr [287:272]; + assign m_axi_araddr[63:48] = \^m_axi_awaddr [351:336]; assign m_axi_araddr[47:32] = \^m_axi_araddr [15:0]; - assign m_axi_araddr[31:16] = \^m_axi_awaddr [287:272]; + assign m_axi_araddr[31:16] = \^m_axi_awaddr [351:336]; assign m_axi_araddr[15:0] = \^m_axi_araddr [15:0]; + assign m_axi_arburst[21] = \ ; + assign m_axi_arburst[20] = \ ; + assign m_axi_arburst[19] = \ ; + assign m_axi_arburst[18] = \ ; assign m_axi_arburst[17] = \ ; assign m_axi_arburst[16] = \ ; assign m_axi_arburst[15] = \ ; @@ -2479,6 +2407,14 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar assign m_axi_arburst[2] = \ ; assign m_axi_arburst[1] = \ ; assign m_axi_arburst[0] = \ ; + assign m_axi_arcache[43] = \ ; + assign m_axi_arcache[42] = \ ; + assign m_axi_arcache[41] = \ ; + assign m_axi_arcache[40] = \ ; + assign m_axi_arcache[39] = \ ; + assign m_axi_arcache[38] = \ ; + assign m_axi_arcache[37] = \ ; + assign m_axi_arcache[36] = \ ; assign m_axi_arcache[35] = \ ; assign m_axi_arcache[34] = \ ; assign m_axi_arcache[33] = \ ; @@ -2515,6 +2451,8 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar assign m_axi_arcache[2] = \ ; assign m_axi_arcache[1] = \ ; assign m_axi_arcache[0] = \ ; + assign m_axi_arid[10] = \ ; + assign m_axi_arid[9] = \ ; assign m_axi_arid[8] = \ ; assign m_axi_arid[7] = \ ; assign m_axi_arid[6] = \ ; @@ -2524,6 +2462,22 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar assign m_axi_arid[2] = \ ; assign m_axi_arid[1] = \ ; assign m_axi_arid[0] = \ ; + assign m_axi_arlen[87] = \ ; + assign m_axi_arlen[86] = \ ; + assign m_axi_arlen[85] = \ ; + assign m_axi_arlen[84] = \ ; + assign m_axi_arlen[83] = \ ; + assign m_axi_arlen[82] = \ ; + assign m_axi_arlen[81] = \ ; + assign m_axi_arlen[80] = \ ; + assign m_axi_arlen[79] = \ ; + assign m_axi_arlen[78] = \ ; + assign m_axi_arlen[77] = \ ; + assign m_axi_arlen[76] = \ ; + assign m_axi_arlen[75] = \ ; + assign m_axi_arlen[74] = \ ; + assign m_axi_arlen[73] = \ ; + assign m_axi_arlen[72] = \ ; assign m_axi_arlen[71] = \ ; assign m_axi_arlen[70] = \ ; assign m_axi_arlen[69] = \ ; @@ -2596,6 +2550,8 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar assign m_axi_arlen[2] = \ ; assign m_axi_arlen[1] = \ ; assign m_axi_arlen[0] = \ ; + assign m_axi_arlock[10] = \ ; + assign m_axi_arlock[9] = \ ; assign m_axi_arlock[8] = \ ; assign m_axi_arlock[7] = \ ; assign m_axi_arlock[6] = \ ; @@ -2605,6 +2561,8 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar assign m_axi_arlock[2] = \ ; assign m_axi_arlock[1] = \ ; assign m_axi_arlock[0] = \ ; + assign m_axi_arprot[32:30] = \^m_axi_arprot [2:0]; + assign m_axi_arprot[29:27] = \^m_axi_arprot [2:0]; assign m_axi_arprot[26:24] = \^m_axi_arprot [2:0]; assign m_axi_arprot[23:21] = \^m_axi_arprot [2:0]; assign m_axi_arprot[20:18] = \^m_axi_arprot [2:0]; @@ -2614,6 +2572,14 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar assign m_axi_arprot[8:6] = \^m_axi_arprot [2:0]; assign m_axi_arprot[5:3] = \^m_axi_arprot [2:0]; assign m_axi_arprot[2:0] = \^m_axi_arprot [2:0]; + assign m_axi_arqos[43] = \ ; + assign m_axi_arqos[42] = \ ; + assign m_axi_arqos[41] = \ ; + assign m_axi_arqos[40] = \ ; + assign m_axi_arqos[39] = \ ; + assign m_axi_arqos[38] = \ ; + assign m_axi_arqos[37] = \ ; + assign m_axi_arqos[36] = \ ; assign m_axi_arqos[35] = \ ; assign m_axi_arqos[34] = \ ; assign m_axi_arqos[33] = \ ; @@ -2650,6 +2616,14 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar assign m_axi_arqos[2] = \ ; assign m_axi_arqos[1] = \ ; assign m_axi_arqos[0] = \ ; + assign m_axi_arregion[43] = \ ; + assign m_axi_arregion[42] = \ ; + assign m_axi_arregion[41] = \ ; + assign m_axi_arregion[40] = \ ; + assign m_axi_arregion[39] = \ ; + assign m_axi_arregion[38] = \ ; + assign m_axi_arregion[37] = \ ; + assign m_axi_arregion[36] = \ ; assign m_axi_arregion[35] = \ ; assign m_axi_arregion[34] = \ ; assign m_axi_arregion[33] = \ ; @@ -2686,6 +2660,12 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar assign m_axi_arregion[2] = \ ; assign m_axi_arregion[1] = \ ; assign m_axi_arregion[0] = \ ; + assign m_axi_arsize[32] = \ ; + assign m_axi_arsize[31] = \ ; + assign m_axi_arsize[30] = \ ; + assign m_axi_arsize[29] = \ ; + assign m_axi_arsize[28] = \ ; + assign m_axi_arsize[27] = \ ; assign m_axi_arsize[26] = \ ; assign m_axi_arsize[25] = \ ; assign m_axi_arsize[24] = \ ; @@ -2713,6 +2693,8 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar assign m_axi_arsize[2] = \ ; assign m_axi_arsize[1] = \ ; assign m_axi_arsize[0] = \ ; + assign m_axi_aruser[10] = \ ; + assign m_axi_aruser[9] = \ ; assign m_axi_aruser[8] = \ ; assign m_axi_aruser[7] = \ ; assign m_axi_aruser[6] = \ ; @@ -2722,24 +2704,32 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar assign m_axi_aruser[2] = \ ; assign m_axi_aruser[1] = \ ; assign m_axi_aruser[0] = \ ; - assign m_axi_awaddr[287:272] = \^m_axi_awaddr [287:272]; + assign m_axi_awaddr[351:336] = \^m_axi_awaddr [351:336]; + assign m_axi_awaddr[335:320] = \^m_axi_araddr [15:0]; + assign m_axi_awaddr[319:304] = \^m_axi_awaddr [351:336]; + assign m_axi_awaddr[303:288] = \^m_axi_araddr [15:0]; + assign m_axi_awaddr[287:272] = \^m_axi_awaddr [351:336]; assign m_axi_awaddr[271:256] = \^m_axi_araddr [15:0]; - assign m_axi_awaddr[255:240] = \^m_axi_awaddr [287:272]; + assign m_axi_awaddr[255:240] = \^m_axi_awaddr [351:336]; assign m_axi_awaddr[239:224] = \^m_axi_araddr [15:0]; - assign m_axi_awaddr[223:208] = \^m_axi_awaddr [287:272]; + assign m_axi_awaddr[223:208] = \^m_axi_awaddr [351:336]; assign m_axi_awaddr[207:192] = \^m_axi_araddr [15:0]; - assign m_axi_awaddr[191:176] = \^m_axi_awaddr [287:272]; + assign m_axi_awaddr[191:176] = \^m_axi_awaddr [351:336]; assign m_axi_awaddr[175:160] = \^m_axi_araddr [15:0]; - assign m_axi_awaddr[159:144] = \^m_axi_awaddr [287:272]; + assign m_axi_awaddr[159:144] = \^m_axi_awaddr [351:336]; assign m_axi_awaddr[143:128] = \^m_axi_araddr [15:0]; - assign m_axi_awaddr[127:112] = \^m_axi_awaddr [287:272]; + assign m_axi_awaddr[127:112] = \^m_axi_awaddr [351:336]; assign m_axi_awaddr[111:96] = \^m_axi_araddr [15:0]; - assign m_axi_awaddr[95:80] = \^m_axi_awaddr [287:272]; + assign m_axi_awaddr[95:80] = \^m_axi_awaddr [351:336]; assign m_axi_awaddr[79:64] = \^m_axi_araddr [15:0]; - assign m_axi_awaddr[63:48] = \^m_axi_awaddr [287:272]; + assign m_axi_awaddr[63:48] = \^m_axi_awaddr [351:336]; assign m_axi_awaddr[47:32] = \^m_axi_araddr [15:0]; - assign m_axi_awaddr[31:16] = \^m_axi_awaddr [287:272]; + assign m_axi_awaddr[31:16] = \^m_axi_awaddr [351:336]; assign m_axi_awaddr[15:0] = \^m_axi_araddr [15:0]; + assign m_axi_awburst[21] = \ ; + assign m_axi_awburst[20] = \ ; + assign m_axi_awburst[19] = \ ; + assign m_axi_awburst[18] = \ ; assign m_axi_awburst[17] = \ ; assign m_axi_awburst[16] = \ ; assign m_axi_awburst[15] = \ ; @@ -2758,6 +2748,14 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar assign m_axi_awburst[2] = \ ; assign m_axi_awburst[1] = \ ; assign m_axi_awburst[0] = \ ; + assign m_axi_awcache[43] = \ ; + assign m_axi_awcache[42] = \ ; + assign m_axi_awcache[41] = \ ; + assign m_axi_awcache[40] = \ ; + assign m_axi_awcache[39] = \ ; + assign m_axi_awcache[38] = \ ; + assign m_axi_awcache[37] = \ ; + assign m_axi_awcache[36] = \ ; assign m_axi_awcache[35] = \ ; assign m_axi_awcache[34] = \ ; assign m_axi_awcache[33] = \ ; @@ -2794,6 +2792,8 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar assign m_axi_awcache[2] = \ ; assign m_axi_awcache[1] = \ ; assign m_axi_awcache[0] = \ ; + assign m_axi_awid[10] = \ ; + assign m_axi_awid[9] = \ ; assign m_axi_awid[8] = \ ; assign m_axi_awid[7] = \ ; assign m_axi_awid[6] = \ ; @@ -2803,6 +2803,22 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar assign m_axi_awid[2] = \ ; assign m_axi_awid[1] = \ ; assign m_axi_awid[0] = \ ; + assign m_axi_awlen[87] = \ ; + assign m_axi_awlen[86] = \ ; + assign m_axi_awlen[85] = \ ; + assign m_axi_awlen[84] = \ ; + assign m_axi_awlen[83] = \ ; + assign m_axi_awlen[82] = \ ; + assign m_axi_awlen[81] = \ ; + assign m_axi_awlen[80] = \ ; + assign m_axi_awlen[79] = \ ; + assign m_axi_awlen[78] = \ ; + assign m_axi_awlen[77] = \ ; + assign m_axi_awlen[76] = \ ; + assign m_axi_awlen[75] = \ ; + assign m_axi_awlen[74] = \ ; + assign m_axi_awlen[73] = \ ; + assign m_axi_awlen[72] = \ ; assign m_axi_awlen[71] = \ ; assign m_axi_awlen[70] = \ ; assign m_axi_awlen[69] = \ ; @@ -2875,6 +2891,8 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar assign m_axi_awlen[2] = \ ; assign m_axi_awlen[1] = \ ; assign m_axi_awlen[0] = \ ; + assign m_axi_awlock[10] = \ ; + assign m_axi_awlock[9] = \ ; assign m_axi_awlock[8] = \ ; assign m_axi_awlock[7] = \ ; assign m_axi_awlock[6] = \ ; @@ -2884,6 +2902,8 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar assign m_axi_awlock[2] = \ ; assign m_axi_awlock[1] = \ ; assign m_axi_awlock[0] = \ ; + assign m_axi_awprot[32:30] = \^m_axi_arprot [2:0]; + assign m_axi_awprot[29:27] = \^m_axi_arprot [2:0]; assign m_axi_awprot[26:24] = \^m_axi_arprot [2:0]; assign m_axi_awprot[23:21] = \^m_axi_arprot [2:0]; assign m_axi_awprot[20:18] = \^m_axi_arprot [2:0]; @@ -2893,6 +2913,14 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar assign m_axi_awprot[8:6] = \^m_axi_arprot [2:0]; assign m_axi_awprot[5:3] = \^m_axi_arprot [2:0]; assign m_axi_awprot[2:0] = \^m_axi_arprot [2:0]; + assign m_axi_awqos[43] = \ ; + assign m_axi_awqos[42] = \ ; + assign m_axi_awqos[41] = \ ; + assign m_axi_awqos[40] = \ ; + assign m_axi_awqos[39] = \ ; + assign m_axi_awqos[38] = \ ; + assign m_axi_awqos[37] = \ ; + assign m_axi_awqos[36] = \ ; assign m_axi_awqos[35] = \ ; assign m_axi_awqos[34] = \ ; assign m_axi_awqos[33] = \ ; @@ -2929,6 +2957,14 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar assign m_axi_awqos[2] = \ ; assign m_axi_awqos[1] = \ ; assign m_axi_awqos[0] = \ ; + assign m_axi_awregion[43] = \ ; + assign m_axi_awregion[42] = \ ; + assign m_axi_awregion[41] = \ ; + assign m_axi_awregion[40] = \ ; + assign m_axi_awregion[39] = \ ; + assign m_axi_awregion[38] = \ ; + assign m_axi_awregion[37] = \ ; + assign m_axi_awregion[36] = \ ; assign m_axi_awregion[35] = \ ; assign m_axi_awregion[34] = \ ; assign m_axi_awregion[33] = \ ; @@ -2965,6 +3001,12 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar assign m_axi_awregion[2] = \ ; assign m_axi_awregion[1] = \ ; assign m_axi_awregion[0] = \ ; + assign m_axi_awsize[32] = \ ; + assign m_axi_awsize[31] = \ ; + assign m_axi_awsize[30] = \ ; + assign m_axi_awsize[29] = \ ; + assign m_axi_awsize[28] = \ ; + assign m_axi_awsize[27] = \ ; assign m_axi_awsize[26] = \ ; assign m_axi_awsize[25] = \ ; assign m_axi_awsize[24] = \ ; @@ -2992,6 +3034,8 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar assign m_axi_awsize[2] = \ ; assign m_axi_awsize[1] = \ ; assign m_axi_awsize[0] = \ ; + assign m_axi_awuser[10] = \ ; + assign m_axi_awuser[9] = \ ; assign m_axi_awuser[8] = \ ; assign m_axi_awuser[7] = \ ; assign m_axi_awuser[6] = \ ; @@ -3001,6 +3045,8 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar assign m_axi_awuser[2] = \ ; assign m_axi_awuser[1] = \ ; assign m_axi_awuser[0] = \ ; + assign m_axi_wdata[351:320] = s_axi_wdata; + assign m_axi_wdata[319:288] = s_axi_wdata; assign m_axi_wdata[287:256] = s_axi_wdata; assign m_axi_wdata[255:224] = s_axi_wdata; assign m_axi_wdata[223:192] = s_axi_wdata; @@ -3010,6 +3056,8 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar assign m_axi_wdata[95:64] = s_axi_wdata; assign m_axi_wdata[63:32] = s_axi_wdata; assign m_axi_wdata[31:0] = s_axi_wdata; + assign m_axi_wid[10] = \ ; + assign m_axi_wid[9] = \ ; assign m_axi_wid[8] = \ ; assign m_axi_wid[7] = \ ; assign m_axi_wid[6] = \ ; @@ -3019,6 +3067,8 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar assign m_axi_wid[2] = \ ; assign m_axi_wid[1] = \ ; assign m_axi_wid[0] = \ ; + assign m_axi_wlast[10] = \ ; + assign m_axi_wlast[9] = \ ; assign m_axi_wlast[8] = \ ; assign m_axi_wlast[7] = \ ; assign m_axi_wlast[6] = \ ; @@ -3028,6 +3078,8 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar assign m_axi_wlast[2] = \ ; assign m_axi_wlast[1] = \ ; assign m_axi_wlast[0] = \ ; + assign m_axi_wstrb[43:40] = s_axi_wstrb; + assign m_axi_wstrb[39:36] = s_axi_wstrb; assign m_axi_wstrb[35:32] = s_axi_wstrb; assign m_axi_wstrb[31:28] = s_axi_wstrb; assign m_axi_wstrb[27:24] = s_axi_wstrb; @@ -3037,6 +3089,8 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar assign m_axi_wstrb[11:8] = s_axi_wstrb; assign m_axi_wstrb[7:4] = s_axi_wstrb; assign m_axi_wstrb[3:0] = s_axi_wstrb; + assign m_axi_wuser[10] = \ ; + assign m_axi_wuser[9] = \ ; assign m_axi_wuser[8] = \ ; assign m_axi_wuser[7] = \ ; assign m_axi_wuser[6] = \ ; @@ -3090,91 +3144,89 @@ endmodule (* ORIG_REF_NAME = "axi_crossbar_v2_1_12_crossbar_sasd" *) module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_crossbar_sasd - (s_axi_awready, - Q, + (Q, \s_axi_rdata[31] , - s_axi_arready, - m_axi_arvalid, - m_axi_bready, - s_axi_wready, s_axi_bvalid, - s_axi_rvalid, + s_axi_wready, + m_axi_bready, + m_axi_awvalid, m_axi_wvalid, + m_axi_arvalid, s_axi_bresp, - m_axi_awvalid, + s_axi_awready, + s_axi_arready, + s_axi_rvalid, m_axi_rready, - s_axi_rready, + m_axi_rresp, aresetn, aclk, + s_axi_rready, s_axi_wvalid, s_axi_bready, - m_axi_arready, - m_axi_rvalid, - m_axi_rresp, - m_axi_rdata, - m_axi_bresp, m_axi_awready, - m_axi_wready, + m_axi_bresp, + m_axi_rdata, + m_axi_rvalid, + m_axi_arready, m_axi_bvalid, - s_axi_araddr, - s_axi_awaddr, - s_axi_arvalid, + m_axi_wready, s_axi_arprot, + s_axi_arvalid, s_axi_awprot, + s_axi_araddr, + s_axi_awaddr, s_axi_awvalid); - output [0:0]s_axi_awready; output [34:0]Q; output [33:0]\s_axi_rdata[31] ; - output [0:0]s_axi_arready; - output [8:0]m_axi_arvalid; - output [8:0]m_axi_bready; - output [0:0]s_axi_wready; output [0:0]s_axi_bvalid; - output [0:0]s_axi_rvalid; - output [8:0]m_axi_wvalid; + output [0:0]s_axi_wready; + output [10:0]m_axi_bready; + output [10:0]m_axi_awvalid; + output [10:0]m_axi_wvalid; + output [10:0]m_axi_arvalid; output [1:0]s_axi_bresp; - output [8:0]m_axi_awvalid; - output [8:0]m_axi_rready; - input [0:0]s_axi_rready; + output [0:0]s_axi_awready; + output [0:0]s_axi_arready; + output [0:0]s_axi_rvalid; + output [10:0]m_axi_rready; + input [21:0]m_axi_rresp; input aresetn; input aclk; + input [0:0]s_axi_rready; input [0:0]s_axi_wvalid; input [0:0]s_axi_bready; - input [8:0]m_axi_arready; - input [8:0]m_axi_rvalid; - input [17:0]m_axi_rresp; - input [287:0]m_axi_rdata; - input [17:0]m_axi_bresp; - input [8:0]m_axi_awready; - input [8:0]m_axi_wready; - input [8:0]m_axi_bvalid; - input [31:0]s_axi_araddr; - input [31:0]s_axi_awaddr; - input [0:0]s_axi_arvalid; + input [10:0]m_axi_awready; + input [21:0]m_axi_bresp; + input [351:0]m_axi_rdata; + input [10:0]m_axi_rvalid; + input [10:0]m_axi_arready; + input [10:0]m_axi_bvalid; + input [10:0]m_axi_wready; input [2:0]s_axi_arprot; + input [0:0]s_axi_arvalid; input [2:0]s_axi_awprot; + input [31:0]s_axi_araddr; + input [31:0]s_axi_awaddr; input [0:0]s_axi_awvalid; wire [34:0]Q; - wire aa_awready; - wire aa_bvalid; wire aa_grant_rnw; wire aa_rready; - wire aa_rvalid; - wire aa_wready; wire aclk; - wire addr_arbiter_inst_n_10; - wire addr_arbiter_inst_n_108; + wire addr_arbiter_inst_n_115; + wire addr_arbiter_inst_n_116; wire addr_arbiter_inst_n_22; wire addr_arbiter_inst_n_23; wire addr_arbiter_inst_n_3; + wire addr_arbiter_inst_n_35; wire addr_arbiter_inst_n_4; + wire addr_arbiter_inst_n_47; + wire addr_arbiter_inst_n_48; wire addr_arbiter_inst_n_5; - wire addr_arbiter_inst_n_6; - wire addr_arbiter_inst_n_61; - wire addr_arbiter_inst_n_62; - wire addr_arbiter_inst_n_7; - wire addr_arbiter_inst_n_8; + wire addr_arbiter_inst_n_50; + wire addr_arbiter_inst_n_51; + wire addr_arbiter_inst_n_52; + wire addr_arbiter_inst_n_64; wire addr_arbiter_inst_n_9; wire aresetn; wire aresetn_d; @@ -3183,35 +3235,44 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_crossbar_sasd wire \gen_decerr.decerr_slave_inst_n_4 ; wire \gen_decerr.decerr_slave_inst_n_5 ; wire \gen_decerr.decerr_slave_inst_n_6 ; + wire \gen_decerr.decerr_slave_inst_n_7 ; + wire \gen_decerr.decerr_slave_inst_n_8 ; wire [3:0]m_atarget_enc; - wire [9:0]m_atarget_hot; - wire [9:0]m_atarget_hot0; - wire [8:0]m_axi_arready; - wire [8:0]m_axi_arvalid; - wire [8:0]m_axi_awready; - wire [8:0]m_axi_awvalid; - wire [8:0]m_axi_bready; - wire [17:0]m_axi_bresp; - wire [8:0]m_axi_bvalid; - wire [287:0]m_axi_rdata; - wire [8:0]m_axi_rready; - wire [17:0]m_axi_rresp; - wire [8:0]m_axi_rvalid; - wire [8:0]m_axi_wready; - wire [8:0]m_axi_wvalid; + wire [11:0]m_atarget_hot; + wire [11:0]m_atarget_hot0; + wire [10:0]m_axi_arready; + wire [10:0]m_axi_arvalid; + wire [10:0]m_axi_awready; + wire [10:0]m_axi_awvalid; + wire [10:0]m_axi_bready; + wire [21:0]m_axi_bresp; + wire [10:0]m_axi_bvalid; + wire [351:0]m_axi_rdata; + wire [10:0]m_axi_rready; + wire [21:0]m_axi_rresp; + wire [10:0]m_axi_rvalid; + wire [10:0]m_axi_wready; + wire [10:0]m_axi_wvalid; wire [1:0]m_ready_d; - wire [2:0]m_ready_d_0; + wire [1:1]m_ready_d0; + wire [1:1]m_ready_d0_0; + wire [2:0]m_ready_d_1; wire m_valid_i; - wire mi_arready_mux; - wire mi_awready_mux; - wire [9:9]mi_bvalid; - wire [9:9]mi_wready; - wire p_4_in; + wire [11:11]mi_bvalid; + wire [11:11]mi_wready; + wire p_1_in; wire reg_slice_r_n_2; - wire reg_slice_r_n_3; - wire reg_slice_r_n_4; - wire reg_slice_r_n_5; - wire reg_slice_r_n_6; + wire reg_slice_r_n_37; + wire reg_slice_r_n_38; + wire reg_slice_r_n_39; + wire reg_slice_r_n_40; + wire reg_slice_r_n_41; + wire reg_slice_r_n_42; + wire reg_slice_r_n_43; + wire reg_slice_r_n_44; + wire reg_slice_r_n_45; + wire reg_slice_r_n_46; + wire reg_slice_r_n_47; wire reset; wire [31:0]s_axi_araddr; wire [2:0]s_axi_arprot; @@ -3223,79 +3284,94 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_crossbar_sasd wire [0:0]s_axi_awvalid; wire [0:0]s_axi_bready; wire [1:0]s_axi_bresp; - wire \s_axi_bresp[0]_INST_0_i_1_n_0 ; - wire \s_axi_bresp[0]_INST_0_i_2_n_0 ; wire \s_axi_bresp[0]_INST_0_i_3_n_0 ; wire \s_axi_bresp[0]_INST_0_i_4_n_0 ; + wire \s_axi_bresp[0]_INST_0_i_5_n_0 ; + wire \s_axi_bresp[0]_INST_0_i_6_n_0 ; + wire \s_axi_bresp[0]_INST_0_i_7_n_0 ; wire \s_axi_bresp[1]_INST_0_i_3_n_0 ; wire \s_axi_bresp[1]_INST_0_i_4_n_0 ; wire \s_axi_bresp[1]_INST_0_i_5_n_0 ; - wire \s_axi_bresp[1]_INST_0_i_8_n_0 ; + wire \s_axi_bresp[1]_INST_0_i_6_n_0 ; + wire \s_axi_bresp[1]_INST_0_i_7_n_0 ; wire [0:0]s_axi_bvalid; wire [33:0]\s_axi_rdata[31] ; wire [0:0]s_axi_rready; wire [0:0]s_axi_rvalid; wire [0:0]s_axi_wready; + wire \s_axi_wready[0]_INST_0_i_5_n_0 ; wire [0:0]s_axi_wvalid; wire splitter_ar_n_0; + wire splitter_ar_n_1; + wire splitter_ar_n_2; wire splitter_aw_n_0; wire splitter_aw_n_1; + wire splitter_aw_n_10; + wire splitter_aw_n_11; + wire splitter_aw_n_12; wire splitter_aw_n_2; wire splitter_aw_n_3; + wire splitter_aw_n_4; + wire splitter_aw_n_5; + wire splitter_aw_n_6; + wire splitter_aw_n_7; + wire splitter_aw_n_8; + wire splitter_aw_n_9; wire sr_rvalid; Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_addr_arbiter_sasd addr_arbiter_inst (.D(m_atarget_hot0), - .E(addr_arbiter_inst_n_6), - .Q(Q), - .SR(reset), - .aa_awready(aa_awready), - .aa_bvalid(aa_bvalid), + .E(p_1_in), + .Q(m_atarget_hot), .aa_grant_rnw(aa_grant_rnw), - .aa_rvalid(aa_rvalid), - .aa_wready(aa_wready), .aclk(aclk), .aresetn_d(aresetn_d), - .\gen_axilite.s_axi_arready_i_reg (\gen_decerr.decerr_slave_inst_n_2 ), - .\gen_axilite.s_axi_awready_i_reg (\gen_decerr.decerr_slave_inst_n_5 ), - .\gen_axilite.s_axi_awready_i_reg_0 (\gen_decerr.decerr_slave_inst_n_4 ), - .\gen_axilite.s_axi_bvalid_i_reg (addr_arbiter_inst_n_8), - .\gen_axilite.s_axi_bvalid_i_reg_0 (addr_arbiter_inst_n_108), - .\gen_axilite.s_axi_bvalid_i_reg_1 (\gen_decerr.decerr_slave_inst_n_6 ), - .\gen_axilite.s_axi_rvalid_i_reg (\gen_decerr.decerr_slave_inst_n_3 ), + .\gen_axilite.s_axi_bvalid_i_reg (addr_arbiter_inst_n_23), + .\gen_axilite.s_axi_bvalid_i_reg_0 (addr_arbiter_inst_n_35), + .\gen_axilite.s_axi_bvalid_i_reg_1 (addr_arbiter_inst_n_47), + .\gen_axilite.s_axi_bvalid_i_reg_2 (addr_arbiter_inst_n_116), + .\gen_axilite.s_axi_rvalid_i_reg (addr_arbiter_inst_n_64), .m_atarget_enc(m_atarget_enc), - .\m_atarget_enc_reg[0] (addr_arbiter_inst_n_3), - .\m_atarget_enc_reg[2] ({addr_arbiter_inst_n_22,addr_arbiter_inst_n_23}), - .\m_atarget_enc_reg[2]_0 (splitter_aw_n_1), - .\m_atarget_enc_reg[2]_1 (splitter_aw_n_0), - .\m_atarget_enc_reg[2]_2 (splitter_aw_n_3), - .\m_atarget_enc_reg[2]_3 (splitter_aw_n_2), - .\m_atarget_enc_reg[3] (addr_arbiter_inst_n_4), - .\m_atarget_hot_reg[9] (m_atarget_hot), - .m_axi_arready({m_axi_arready[8:6],m_axi_arready[4:2],m_axi_arready[0]}), + .\m_atarget_enc_reg[0] (addr_arbiter_inst_n_4), + .\m_atarget_enc_reg[1] (addr_arbiter_inst_n_3), + .\m_atarget_enc_reg[2] (addr_arbiter_inst_n_115), + .\m_atarget_enc_reg[2]_0 (\gen_decerr.decerr_slave_inst_n_5 ), + .\m_atarget_enc_reg[2]_1 (splitter_aw_n_3), + .\m_atarget_enc_reg[2]_2 (splitter_aw_n_2), + .\m_atarget_enc_reg[2]_3 (\gen_decerr.decerr_slave_inst_n_8 ), + .\m_atarget_enc_reg[2]_4 (\gen_decerr.decerr_slave_inst_n_3 ), + .\m_atarget_enc_reg[2]_5 (splitter_aw_n_10), + .\m_atarget_enc_reg[2]_6 (splitter_ar_n_2), + .\m_atarget_enc_reg[2]_7 (\gen_decerr.decerr_slave_inst_n_6 ), + .\m_atarget_enc_reg[2]_8 (splitter_ar_n_1), + .\m_atarget_enc_reg[3] (addr_arbiter_inst_n_5), + .\m_atarget_enc_reg[3]_0 (\gen_decerr.decerr_slave_inst_n_7 ), + .\m_atarget_enc_reg[3]_1 (\s_axi_wready[0]_INST_0_i_5_n_0 ), + .\m_atarget_enc_reg[3]_2 (splitter_aw_n_7), + .\m_atarget_enc_reg[3]_3 (splitter_aw_n_12), + .\m_atarget_enc_reg[3]_4 (splitter_ar_n_0), + .\m_axi_arprot[2] (Q), .m_axi_arvalid(m_axi_arvalid), - .m_axi_awready({m_axi_awready[8:6],m_axi_awready[4:2],m_axi_awready[0]}), + .m_axi_awready({m_axi_awready[10],m_axi_awready[5:4],m_axi_awready[1:0]}), .m_axi_awvalid(m_axi_awvalid), .m_axi_bready(m_axi_bready), - .m_axi_bvalid({m_axi_bvalid[8:6],m_axi_bvalid[4:2],m_axi_bvalid[0]}), - .m_axi_rvalid({m_axi_rvalid[8:6],m_axi_rvalid[4:2],m_axi_rvalid[0]}), - .m_axi_wready({m_axi_wready[8:6],m_axi_wready[4:2],m_axi_wready[0]}), .m_axi_wvalid(m_axi_wvalid), - .m_ready_d(m_ready_d), - .m_ready_d_0(m_ready_d_0), - .\m_ready_d_reg[0] (addr_arbiter_inst_n_7), - .\m_ready_d_reg[0]_0 (addr_arbiter_inst_n_10), - .\m_ready_d_reg[0]_1 (splitter_ar_n_0), - .\m_ready_d_reg[1] (addr_arbiter_inst_n_5), - .\m_ready_d_reg[1]_0 (addr_arbiter_inst_n_9), - .\m_ready_d_reg[1]_1 (addr_arbiter_inst_n_61), - .\m_ready_d_reg[1]_2 (addr_arbiter_inst_n_62), + .\m_payload_i_reg[0] (reg_slice_r_n_2), + .\m_payload_i_reg[0]_0 (reg_slice_r_n_37), + .m_ready_d(m_ready_d_1), + .m_ready_d0(m_ready_d0_0), + .m_ready_d0_0(m_ready_d0), + .m_ready_d_1(m_ready_d), + .\m_ready_d_reg[0] (addr_arbiter_inst_n_50), + .\m_ready_d_reg[0]_0 (addr_arbiter_inst_n_52), + .\m_ready_d_reg[0]_1 (\gen_decerr.decerr_slave_inst_n_2 ), + .\m_ready_d_reg[1] (addr_arbiter_inst_n_22), + .\m_ready_d_reg[1]_0 (addr_arbiter_inst_n_51), + .\m_ready_d_reg[2] (addr_arbiter_inst_n_9), .m_valid_i(m_valid_i), - .mi_arready_mux(mi_arready_mux), - .mi_awready_mux(mi_awready_mux), .mi_bvalid(mi_bvalid), .mi_wready(mi_wready), - .p_4_in(p_4_in), + .reset(reset), .s_axi_araddr(s_axi_araddr), .s_axi_arprot(s_axi_arprot), .s_axi_arready(s_axi_arready), @@ -3310,6 +3386,7 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_crossbar_sasd .s_axi_rvalid(s_axi_rvalid), .s_axi_wready(s_axi_wready), .s_axi_wvalid(s_axi_wvalid), + .s_ready_i_reg(addr_arbiter_inst_n_48), .sr_rvalid(sr_rvalid)); FDRE #( .INIT(1'b0)) @@ -3320,53 +3397,65 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_crossbar_sasd .Q(aresetn_d), .R(1'b0)); Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_decerr_slave \gen_decerr.decerr_slave_inst - (.Q(m_atarget_hot[9]), - .SR(reset), + (.Q(m_atarget_hot[11]), .aa_rready(aa_rready), .aclk(aclk), .aresetn_d(aresetn_d), - .\gen_axilite.s_axi_bvalid_i_reg_0 (addr_arbiter_inst_n_108), - .\gen_no_arbiter.grant_rnw_reg (addr_arbiter_inst_n_8), - .\gen_no_arbiter.grant_rnw_reg_0 (addr_arbiter_inst_n_9), - .\gen_no_arbiter.grant_rnw_reg_1 (addr_arbiter_inst_n_10), - .\gen_no_arbiter.m_valid_i_reg (addr_arbiter_inst_n_5), - .\gen_no_arbiter.m_valid_i_reg_0 (addr_arbiter_inst_n_7), - .m_atarget_enc(m_atarget_enc[3:2]), - .m_axi_arready({m_axi_arready[5],m_axi_arready[1]}), - .m_axi_awready({m_axi_awready[5],m_axi_awready[1]}), - .m_axi_bvalid({m_axi_bvalid[5],m_axi_bvalid[1]}), - .m_axi_rvalid({m_axi_rvalid[5],m_axi_rvalid[1]}), - .m_axi_wready({m_axi_wready[5],m_axi_wready[1]}), - .\m_ready_d_reg[0] (\gen_decerr.decerr_slave_inst_n_6 ), - .\m_ready_d_reg[1] (\gen_decerr.decerr_slave_inst_n_2 ), - .\m_ready_d_reg[1]_0 (\gen_decerr.decerr_slave_inst_n_5 ), - .\m_ready_d_reg[2] (\gen_decerr.decerr_slave_inst_n_4 ), - .m_valid_i_reg(\gen_decerr.decerr_slave_inst_n_3 ), + .\gen_no_arbiter.grant_rnw_reg (addr_arbiter_inst_n_23), + .\gen_no_arbiter.m_valid_i_reg (addr_arbiter_inst_n_48), + .m_atarget_enc(m_atarget_enc), + .\m_atarget_enc_reg[0] (reg_slice_r_n_45), + .\m_atarget_enc_reg[1] (splitter_aw_n_11), + .\m_atarget_enc_reg[2] (splitter_aw_n_0), + .\m_atarget_enc_reg[2]_0 (splitter_aw_n_5), + .\m_atarget_enc_reg[2]_1 (splitter_aw_n_6), + .\m_atarget_enc_reg[2]_2 (reg_slice_r_n_44), + .\m_atarget_enc_reg[2]_3 (splitter_aw_n_9), + .\m_atarget_enc_reg[2]_4 (splitter_aw_n_8), + .\m_atarget_enc_reg[3] (reg_slice_r_n_43), + .\m_atarget_enc_reg[3]_0 (reg_slice_r_n_46), + .\m_atarget_hot_reg[11] (addr_arbiter_inst_n_116), + .m_axi_arready({m_axi_arready[7],m_axi_arready[3]}), + .m_axi_awready({m_axi_awready[7],m_axi_awready[3]}), + .m_axi_bvalid({m_axi_bvalid[7],m_axi_bvalid[3]}), + .m_axi_rvalid({m_axi_rvalid[7],m_axi_rvalid[3]}), + .m_axi_wready({m_axi_wready[8:7],m_axi_wready[3]}), + .m_ready_d(m_ready_d_1[0]), + .\m_ready_d_reg[1] (\gen_decerr.decerr_slave_inst_n_5 ), + .\m_ready_d_reg[1]_0 (\gen_decerr.decerr_slave_inst_n_6 ), + .\m_ready_d_reg[1]_1 (addr_arbiter_inst_n_64), + .\m_ready_d_reg[1]_2 (addr_arbiter_inst_n_47), + .\m_ready_d_reg[2] (\gen_decerr.decerr_slave_inst_n_2 ), + .\m_ready_d_reg[2]_0 (\gen_decerr.decerr_slave_inst_n_3 ), + .\m_ready_d_reg[2]_1 (\gen_decerr.decerr_slave_inst_n_7 ), + .\m_ready_d_reg[2]_2 (addr_arbiter_inst_n_35), .mi_bvalid(mi_bvalid), .mi_wready(mi_wready), - .p_4_in(p_4_in)); + .reset(reset), + .\s_axi_wready[0] (\gen_decerr.decerr_slave_inst_n_8 ), + .s_ready_i_reg(\gen_decerr.decerr_slave_inst_n_4 )); FDRE \m_atarget_enc_reg[0] (.C(aclk), .CE(1'b1), - .D(addr_arbiter_inst_n_3), + .D(addr_arbiter_inst_n_4), .Q(m_atarget_enc[0]), .R(reset)); FDRE \m_atarget_enc_reg[1] (.C(aclk), .CE(1'b1), - .D(addr_arbiter_inst_n_23), + .D(addr_arbiter_inst_n_3), .Q(m_atarget_enc[1]), - .R(1'b0)); + .R(reset)); FDRE \m_atarget_enc_reg[2] (.C(aclk), .CE(1'b1), - .D(addr_arbiter_inst_n_22), + .D(addr_arbiter_inst_n_115), .Q(m_atarget_enc[2]), - .R(1'b0)); + .R(reset)); FDRE \m_atarget_enc_reg[3] (.C(aclk), .CE(1'b1), - .D(addr_arbiter_inst_n_4), + .D(addr_arbiter_inst_n_5), .Q(m_atarget_enc[3]), .R(reset)); FDRE \m_atarget_hot_reg[0] @@ -3375,6 +3464,18 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_crossbar_sasd .D(m_atarget_hot0[0]), .Q(m_atarget_hot[0]), .R(reset)); + FDRE \m_atarget_hot_reg[10] + (.C(aclk), + .CE(1'b1), + .D(m_atarget_hot0[10]), + .Q(m_atarget_hot[10]), + .R(reset)); + FDRE \m_atarget_hot_reg[11] + (.C(aclk), + .CE(1'b1), + .D(m_atarget_hot0[11]), + .Q(m_atarget_hot[11]), + .R(reset)); FDRE \m_atarget_hot_reg[1] (.C(aclk), .CE(1'b1), @@ -3430,252 +3531,342 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_crossbar_sasd .Q(m_atarget_hot[9]), .R(reset)); Arty_Z7_20_xbar_0_axi_register_slice_v2_1_11_axic_register_slice reg_slice_r - (.E(addr_arbiter_inst_n_6), - .Q(m_atarget_hot[8:0]), - .SR(reset), + (.E(p_1_in), + .Q({\s_axi_rdata[31] ,reg_slice_r_n_37}), .aa_grant_rnw(aa_grant_rnw), .aa_rready(aa_rready), - .aa_rvalid(aa_rvalid), .aclk(aclk), + .\gen_no_arbiter.m_grant_hot_i_reg[0] (reg_slice_r_n_2), .m_atarget_enc(m_atarget_enc), + .\m_atarget_enc_reg[0] (splitter_aw_n_1), + .\m_atarget_enc_reg[1] (splitter_aw_n_4), + .\m_atarget_hot_reg[10] (m_atarget_hot[10:0]), .m_axi_rdata(m_axi_rdata), .m_axi_rready(m_axi_rready), .m_axi_rresp(m_axi_rresp), + .m_axi_rvalid({m_axi_rvalid[10:8],m_axi_rvalid[6:4],m_axi_rvalid[2:0]}), + .\m_payload_i_reg[1]_0 (reg_slice_r_n_41), + .\m_payload_i_reg[2]_0 (reg_slice_r_n_39), + .\m_payload_i_reg[2]_1 (reg_slice_r_n_40), .m_ready_d(m_ready_d[0]), - .\m_ready_d_reg[1] (reg_slice_r_n_2), + .\m_ready_d_reg[2] (reg_slice_r_n_45), .m_valid_i(m_valid_i), - .\s_axi_rdata[31] (\s_axi_rdata[31] ), + .reset(reset), .s_axi_rready(s_axi_rready), - .\skid_buffer_reg[1]_0 (reg_slice_r_n_3), - .\skid_buffer_reg[1]_1 (reg_slice_r_n_4), - .\skid_buffer_reg[1]_2 (reg_slice_r_n_5), - .\skid_buffer_reg[1]_3 (reg_slice_r_n_6), + .s_ready_i_reg_0(reg_slice_r_n_43), + .s_ready_i_reg_1(reg_slice_r_n_44), + .s_ready_i_reg_2(reg_slice_r_n_46), + .s_ready_i_reg_3(reg_slice_r_n_47), + .s_ready_i_reg_4(\gen_decerr.decerr_slave_inst_n_4 ), + .\skid_buffer_reg[30]_0 (reg_slice_r_n_38), + .\skid_buffer_reg[9]_0 (reg_slice_r_n_42), .sr_rvalid(sr_rvalid)); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'hFFFFFFFFFFFF4F44)) \s_axi_bresp[0]_INST_0 - (.I0(reg_slice_r_n_3), - .I1(m_axi_bresp[2]), - .I2(reg_slice_r_n_4), - .I3(m_axi_bresp[4]), - .I4(\s_axi_bresp[0]_INST_0_i_1_n_0 ), - .I5(\s_axi_bresp[0]_INST_0_i_2_n_0 ), + (.I0(reg_slice_r_n_38), + .I1(m_axi_bresp[18]), + .I2(reg_slice_r_n_40), + .I3(m_axi_bresp[14]), + .I4(\s_axi_bresp[0]_INST_0_i_3_n_0 ), + .I5(\s_axi_bresp[0]_INST_0_i_4_n_0 ), .O(s_axi_bresp[0])); LUT6 #( - .INIT(64'hAABAAAABAABAAAAA)) - \s_axi_bresp[0]_INST_0_i_1 - (.I0(\s_axi_bresp[0]_INST_0_i_3_n_0 ), - .I1(m_atarget_enc[1]), - .I2(m_atarget_enc[0]), - .I3(m_atarget_enc[2]), - .I4(m_atarget_enc[3]), - .I5(m_axi_bresp[0]), - .O(\s_axi_bresp[0]_INST_0_i_1_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) - \s_axi_bresp[0]_INST_0_i_2 - (.I0(reg_slice_r_n_5), - .I1(m_axi_bresp[8]), - .I2(reg_slice_r_n_6), - .I3(m_axi_bresp[6]), - .I4(\s_axi_bresp[0]_INST_0_i_4_n_0 ), - .O(\s_axi_bresp[0]_INST_0_i_2_n_0 )); - LUT6 #( - .INIT(64'h0000A000000C0000)) + .INIT(64'h30000C0830000008)) \s_axi_bresp[0]_INST_0_i_3 - (.I0(m_axi_bresp[14]), - .I1(m_axi_bresp[16]), - .I2(m_atarget_enc[0]), - .I3(m_atarget_enc[2]), - .I4(m_atarget_enc[3]), - .I5(m_atarget_enc[1]), - .O(\s_axi_bresp[0]_INST_0_i_3_n_0 )); - LUT6 #( - .INIT(64'h000C0A0000000000)) - \s_axi_bresp[0]_INST_0_i_4 - (.I0(m_axi_bresp[10]), - .I1(m_axi_bresp[12]), + (.I0(m_axi_bresp[8]), + .I1(m_atarget_enc[2]), .I2(m_atarget_enc[3]), .I3(m_atarget_enc[0]), .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + .I5(m_axi_bresp[10]), + .O(\s_axi_bresp[0]_INST_0_i_3_n_0 )); + LUT5 #( + .INIT(32'hFEFEFFFE)) + \s_axi_bresp[0]_INST_0_i_4 + (.I0(\s_axi_bresp[0]_INST_0_i_5_n_0 ), + .I1(\s_axi_bresp[0]_INST_0_i_6_n_0 ), + .I2(\s_axi_bresp[0]_INST_0_i_7_n_0 ), + .I3(m_axi_bresp[12]), + .I4(reg_slice_r_n_39), .O(\s_axi_bresp[0]_INST_0_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'h00000C8000000080)) + \s_axi_bresp[0]_INST_0_i_5 + (.I0(m_axi_bresp[6]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[0]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_bresp[20]), + .O(\s_axi_bresp[0]_INST_0_i_5_n_0 )); + LUT6 #( + .INIT(64'h0000020300000200)) + \s_axi_bresp[0]_INST_0_i_6 + (.I0(m_axi_bresp[16]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[0]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_bresp[0]), + .O(\s_axi_bresp[0]_INST_0_i_6_n_0 )); + LUT6 #( + .INIT(64'h0000002C00000020)) + \s_axi_bresp[0]_INST_0_i_7 + (.I0(m_axi_bresp[4]), + .I1(m_atarget_enc[0]), + .I2(m_atarget_enc[1]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_bresp[2]), + .O(\s_axi_bresp[0]_INST_0_i_7_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF4F44)) \s_axi_bresp[1]_INST_0 - (.I0(reg_slice_r_n_3), - .I1(m_axi_bresp[3]), - .I2(reg_slice_r_n_4), - .I3(m_axi_bresp[5]), + (.I0(reg_slice_r_n_41), + .I1(m_axi_bresp[1]), + .I2(reg_slice_r_n_42), + .I3(m_axi_bresp[17]), .I4(\s_axi_bresp[1]_INST_0_i_3_n_0 ), .I5(\s_axi_bresp[1]_INST_0_i_4_n_0 ), .O(s_axi_bresp[1])); LUT6 #( - .INIT(64'hAABAAAABAABAAAAA)) + .INIT(64'h30000C0830000008)) \s_axi_bresp[1]_INST_0_i_3 - (.I0(\s_axi_bresp[1]_INST_0_i_5_n_0 ), - .I1(m_atarget_enc[1]), - .I2(m_atarget_enc[0]), - .I3(m_atarget_enc[2]), - .I4(m_atarget_enc[3]), - .I5(m_axi_bresp[1]), + (.I0(m_axi_bresp[9]), + .I1(m_atarget_enc[2]), + .I2(m_atarget_enc[3]), + .I3(m_atarget_enc[0]), + .I4(m_atarget_enc[1]), + .I5(m_axi_bresp[11]), .O(\s_axi_bresp[1]_INST_0_i_3_n_0 )); LUT5 #( - .INIT(32'hFFFFF888)) + .INIT(32'hFEFEFFFE)) \s_axi_bresp[1]_INST_0_i_4 - (.I0(reg_slice_r_n_5), - .I1(m_axi_bresp[9]), - .I2(reg_slice_r_n_6), - .I3(m_axi_bresp[7]), - .I4(\s_axi_bresp[1]_INST_0_i_8_n_0 ), + (.I0(\s_axi_bresp[1]_INST_0_i_5_n_0 ), + .I1(\s_axi_bresp[1]_INST_0_i_6_n_0 ), + .I2(\s_axi_bresp[1]_INST_0_i_7_n_0 ), + .I3(m_axi_bresp[19]), + .I4(reg_slice_r_n_38), .O(\s_axi_bresp[1]_INST_0_i_4_n_0 )); LUT6 #( - .INIT(64'h0000A000000C0000)) + .INIT(64'h00000C8000000080)) \s_axi_bresp[1]_INST_0_i_5 - (.I0(m_axi_bresp[15]), - .I1(m_axi_bresp[17]), + (.I0(m_axi_bresp[7]), + .I1(m_atarget_enc[1]), .I2(m_atarget_enc[0]), - .I3(m_atarget_enc[2]), - .I4(m_atarget_enc[3]), - .I5(m_atarget_enc[1]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_bresp[21]), .O(\s_axi_bresp[1]_INST_0_i_5_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) - \s_axi_bresp[1]_INST_0_i_8 - (.I0(m_axi_bresp[11]), - .I1(m_axi_bresp[13]), + .INIT(64'h08000C0008000000)) + \s_axi_bresp[1]_INST_0_i_6 + (.I0(m_axi_bresp[15]), + .I1(m_atarget_enc[2]), .I2(m_atarget_enc[3]), - .I3(m_atarget_enc[0]), - .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), - .O(\s_axi_bresp[1]_INST_0_i_8_n_0 )); + .I3(m_atarget_enc[1]), + .I4(m_atarget_enc[0]), + .I5(m_axi_bresp[13]), + .O(\s_axi_bresp[1]_INST_0_i_6_n_0 )); + LUT6 #( + .INIT(64'h0000002C00000020)) + \s_axi_bresp[1]_INST_0_i_7 + (.I0(m_axi_bresp[3]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[0]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_bresp[5]), + .O(\s_axi_bresp[1]_INST_0_i_7_n_0 )); + LUT6 #( + .INIT(64'hFCDCFCDFFFDCFFDF)) + \s_axi_wready[0]_INST_0_i_5 + (.I0(m_axi_wready[8]), + .I1(reg_slice_r_n_47), + .I2(m_atarget_enc[3]), + .I3(m_atarget_enc[2]), + .I4(m_axi_wready[0]), + .I5(m_axi_wready[4]), + .O(\s_axi_wready[0]_INST_0_i_5_n_0 )); Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_splitter__parameterized0 splitter_ar - (.aclk(aclk), + (.Q(reg_slice_r_n_37), + .aclk(aclk), .aresetn_d(aresetn_d), - .\gen_no_arbiter.m_valid_i_reg (splitter_ar_n_0), - .\gen_no_arbiter.m_valid_i_reg_0 (addr_arbiter_inst_n_5), - .\gen_no_arbiter.m_valid_i_reg_1 (addr_arbiter_inst_n_7), - .m_atarget_enc(m_atarget_enc[0]), - .\m_atarget_enc_reg[2] (addr_arbiter_inst_n_62), - .\m_atarget_enc_reg[2]_0 (addr_arbiter_inst_n_61), - .\m_payload_i_reg[0] (reg_slice_r_n_2), + .aresetn_d_reg(addr_arbiter_inst_n_50), + .\gen_no_arbiter.grant_rnw_reg (addr_arbiter_inst_n_52), + .m_atarget_enc(m_atarget_enc[3:2]), + .\m_atarget_enc_reg[0] (splitter_aw_n_1), + .\m_atarget_enc_reg[0]_0 (reg_slice_r_n_47), + .\m_atarget_enc_reg[1] (splitter_aw_n_4), + .m_axi_arready({m_axi_arready[10:8],m_axi_arready[6:4],m_axi_arready[2:0]}), .m_ready_d(m_ready_d), - .mi_arready_mux(mi_arready_mux)); + .m_ready_d0(m_ready_d0_0), + .\m_ready_d_reg[0]_0 (addr_arbiter_inst_n_51), + .\m_ready_d_reg[1]_0 (splitter_ar_n_0), + .\m_ready_d_reg[1]_1 (splitter_ar_n_1), + .\m_ready_d_reg[1]_2 (splitter_ar_n_2), + .s_axi_rready(s_axi_rready), + .sr_rvalid(sr_rvalid)); Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_splitter splitter_aw - (.aa_awready(aa_awready), - .aa_bvalid(aa_bvalid), - .aa_grant_rnw(aa_grant_rnw), - .aa_wready(aa_wready), - .aclk(aclk), + (.aclk(aclk), .aresetn_d(aresetn_d), - .\gen_no_arbiter.grant_rnw_reg (addr_arbiter_inst_n_9), - .\gen_no_arbiter.grant_rnw_reg_0 (addr_arbiter_inst_n_10), - .\gen_no_arbiter.m_valid_i_reg (splitter_aw_n_0), - .\gen_no_arbiter.m_valid_i_reg_0 (splitter_aw_n_1), - .\gen_no_arbiter.m_valid_i_reg_1 (splitter_aw_n_2), - .\gen_no_arbiter.m_valid_i_reg_2 (splitter_aw_n_3), - .m_atarget_enc(m_atarget_enc[3:2]), - .m_axi_bvalid({m_axi_bvalid[6],m_axi_bvalid[4],m_axi_bvalid[2],m_axi_bvalid[0]}), - .m_axi_wready({m_axi_wready[6],m_axi_wready[4],m_axi_wready[2],m_axi_wready[0]}), - .m_ready_d(m_ready_d_0), - .m_valid_i(m_valid_i), - .mi_awready_mux(mi_awready_mux), - .s_axi_bready(s_axi_bready), - .s_axi_wvalid(s_axi_wvalid)); + .\gen_no_arbiter.m_valid_i_reg (addr_arbiter_inst_n_22), + .m_atarget_enc(m_atarget_enc), + .\m_atarget_enc_reg[0] (reg_slice_r_n_47), + .m_axi_awready({m_axi_awready[9:8],m_axi_awready[6],m_axi_awready[2]}), + .m_axi_bvalid({m_axi_bvalid[10:8],m_axi_bvalid[6:4],m_axi_bvalid[2:0]}), + .m_axi_wready({m_axi_wready[10:9],m_axi_wready[7:0]}), + .m_ready_d(m_ready_d_1), + .m_ready_d0(m_ready_d0), + .\m_ready_d_reg[0]_0 (\gen_decerr.decerr_slave_inst_n_2 ), + .\m_ready_d_reg[2]_0 (splitter_aw_n_0), + .\m_ready_d_reg[2]_1 (splitter_aw_n_1), + .\m_ready_d_reg[2]_10 (splitter_aw_n_10), + .\m_ready_d_reg[2]_11 (splitter_aw_n_11), + .\m_ready_d_reg[2]_12 (splitter_aw_n_12), + .\m_ready_d_reg[2]_13 (addr_arbiter_inst_n_9), + .\m_ready_d_reg[2]_2 (splitter_aw_n_2), + .\m_ready_d_reg[2]_3 (splitter_aw_n_3), + .\m_ready_d_reg[2]_4 (splitter_aw_n_4), + .\m_ready_d_reg[2]_5 (splitter_aw_n_5), + .\m_ready_d_reg[2]_6 (splitter_aw_n_6), + .\m_ready_d_reg[2]_7 (splitter_aw_n_7), + .\m_ready_d_reg[2]_8 (splitter_aw_n_8), + .\m_ready_d_reg[2]_9 (splitter_aw_n_9)); endmodule (* ORIG_REF_NAME = "axi_crossbar_v2_1_12_decerr_slave" *) module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_decerr_slave (mi_bvalid, mi_wready, - \m_ready_d_reg[1] , - m_valid_i_reg, \m_ready_d_reg[2] , + \m_ready_d_reg[2]_0 , + s_ready_i_reg, + \m_ready_d_reg[1] , \m_ready_d_reg[1]_0 , - \m_ready_d_reg[0] , - SR, - \gen_axilite.s_axi_bvalid_i_reg_0 , + \m_ready_d_reg[2]_1 , + \s_axi_wready[0] , + reset, + \m_atarget_hot_reg[11] , aclk, + \m_atarget_enc_reg[2] , + \m_atarget_enc_reg[2]_0 , + \m_atarget_enc_reg[2]_1 , + m_ready_d, + \gen_no_arbiter.grant_rnw_reg , + \m_ready_d_reg[2]_2 , + m_axi_awready, + m_atarget_enc, + \m_atarget_enc_reg[2]_2 , + \m_atarget_enc_reg[3] , + \m_atarget_enc_reg[3]_0 , \gen_no_arbiter.m_valid_i_reg , + aa_rready, + m_axi_bvalid, + \m_atarget_enc_reg[0] , m_axi_arready, - m_atarget_enc, - \gen_no_arbiter.m_valid_i_reg_0 , m_axi_rvalid, - \gen_no_arbiter.grant_rnw_reg , - m_axi_awready, - \gen_no_arbiter.grant_rnw_reg_0 , + \m_atarget_enc_reg[2]_3 , + \m_atarget_enc_reg[1] , m_axi_wready, - \gen_no_arbiter.grant_rnw_reg_1 , - m_axi_bvalid, - aa_rready, + \m_atarget_enc_reg[2]_4 , + \m_ready_d_reg[1]_1 , Q, aresetn_d, - p_4_in); + \m_ready_d_reg[1]_2 ); output [0:0]mi_bvalid; output [0:0]mi_wready; - output \m_ready_d_reg[1] ; - output m_valid_i_reg; output \m_ready_d_reg[2] ; + output \m_ready_d_reg[2]_0 ; + output s_ready_i_reg; + output \m_ready_d_reg[1] ; output \m_ready_d_reg[1]_0 ; - output \m_ready_d_reg[0] ; - input [0:0]SR; - input \gen_axilite.s_axi_bvalid_i_reg_0 ; + output \m_ready_d_reg[2]_1 ; + output \s_axi_wready[0] ; + input reset; + input \m_atarget_hot_reg[11] ; input aclk; - input \gen_no_arbiter.m_valid_i_reg ; - input [1:0]m_axi_arready; - input [1:0]m_atarget_enc; - input \gen_no_arbiter.m_valid_i_reg_0 ; - input [1:0]m_axi_rvalid; + input \m_atarget_enc_reg[2] ; + input \m_atarget_enc_reg[2]_0 ; + input \m_atarget_enc_reg[2]_1 ; + input [0:0]m_ready_d; input \gen_no_arbiter.grant_rnw_reg ; + input \m_ready_d_reg[2]_2 ; input [1:0]m_axi_awready; - input \gen_no_arbiter.grant_rnw_reg_0 ; - input [1:0]m_axi_wready; - input \gen_no_arbiter.grant_rnw_reg_1 ; - input [1:0]m_axi_bvalid; + input [3:0]m_atarget_enc; + input \m_atarget_enc_reg[2]_2 ; + input \m_atarget_enc_reg[3] ; + input \m_atarget_enc_reg[3]_0 ; + input \gen_no_arbiter.m_valid_i_reg ; input aa_rready; + input [1:0]m_axi_bvalid; + input \m_atarget_enc_reg[0] ; + input [1:0]m_axi_arready; + input [1:0]m_axi_rvalid; + input \m_atarget_enc_reg[2]_3 ; + input \m_atarget_enc_reg[1] ; + input [2:0]m_axi_wready; + input \m_atarget_enc_reg[2]_4 ; + input \m_ready_d_reg[1]_1 ; input [0:0]Q; input aresetn_d; - input p_4_in; + input \m_ready_d_reg[1]_2 ; wire [0:0]Q; - wire [0:0]SR; wire aa_rready; wire aclk; wire aresetn_d; wire \gen_axilite.s_axi_arready_i_i_1_n_0 ; wire \gen_axilite.s_axi_awready_i_i_1_n_0 ; - wire \gen_axilite.s_axi_bvalid_i_reg_0 ; wire \gen_axilite.s_axi_rvalid_i_i_1_n_0 ; wire \gen_no_arbiter.grant_rnw_reg ; - wire \gen_no_arbiter.grant_rnw_reg_0 ; - wire \gen_no_arbiter.grant_rnw_reg_1 ; wire \gen_no_arbiter.m_valid_i_reg ; - wire \gen_no_arbiter.m_valid_i_reg_0 ; - wire [1:0]m_atarget_enc; + wire [3:0]m_atarget_enc; + wire \m_atarget_enc_reg[0] ; + wire \m_atarget_enc_reg[1] ; + wire \m_atarget_enc_reg[2] ; + wire \m_atarget_enc_reg[2]_0 ; + wire \m_atarget_enc_reg[2]_1 ; + wire \m_atarget_enc_reg[2]_2 ; + wire \m_atarget_enc_reg[2]_3 ; + wire \m_atarget_enc_reg[2]_4 ; + wire \m_atarget_enc_reg[3] ; + wire \m_atarget_enc_reg[3]_0 ; + wire \m_atarget_hot_reg[11] ; wire [1:0]m_axi_arready; wire [1:0]m_axi_awready; wire [1:0]m_axi_bvalid; wire [1:0]m_axi_rvalid; - wire [1:0]m_axi_wready; - wire \m_ready_d_reg[0] ; + wire [2:0]m_axi_wready; + wire [0:0]m_ready_d; + wire \m_ready_d[2]_i_12_n_0 ; wire \m_ready_d_reg[1] ; wire \m_ready_d_reg[1]_0 ; + wire \m_ready_d_reg[1]_1 ; + wire \m_ready_d_reg[1]_2 ; wire \m_ready_d_reg[2] ; - wire m_valid_i_reg; - wire [9:9]mi_arready; + wire \m_ready_d_reg[2]_0 ; + wire \m_ready_d_reg[2]_1 ; + wire \m_ready_d_reg[2]_2 ; + wire m_valid_i_i_3_n_0; + wire [11:11]mi_arready; wire [0:0]mi_bvalid; - wire [9:9]mi_rvalid; + wire [11:11]mi_rvalid; wire [0:0]mi_wready; - wire p_4_in; + wire reset; + wire \s_axi_bvalid[0]_INST_0_i_3_n_0 ; + wire \s_axi_wready[0] ; + wire s_ready_i_reg; LUT5 #( - .INIT(32'h88882AAA)) + .INIT(32'h882A88AA)) \gen_axilite.s_axi_arready_i_i_1 (.I0(aresetn_d), .I1(mi_arready), .I2(Q), - .I3(\gen_no_arbiter.m_valid_i_reg ), - .I4(mi_rvalid), + .I3(mi_rvalid), + .I4(\m_ready_d_reg[1]_1 ), .O(\gen_axilite.s_axi_arready_i_i_1_n_0 )); FDRE \gen_axilite.s_axi_arready_i_reg (.C(aclk), @@ -3684,12 +3875,12 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_decerr_slave .Q(mi_arready), .R(1'b0)); LUT5 #( - .INIT(32'hBFFF4000)) + .INIT(32'hEFFF1000)) \gen_axilite.s_axi_awready_i_i_1 (.I0(mi_bvalid), - .I1(\gen_no_arbiter.grant_rnw_reg ), - .I2(p_4_in), - .I3(Q), + .I1(\m_ready_d_reg[2]_2 ), + .I2(Q), + .I3(\m_ready_d_reg[1]_2 ), .I4(mi_wready), .O(\gen_axilite.s_axi_awready_i_i_1_n_0 )); FDRE \gen_axilite.s_axi_awready_i_reg @@ -3697,19 +3888,19 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_decerr_slave .CE(1'b1), .D(\gen_axilite.s_axi_awready_i_i_1_n_0 ), .Q(mi_wready), - .R(SR)); + .R(reset)); FDRE \gen_axilite.s_axi_bvalid_i_reg (.C(aclk), .CE(1'b1), - .D(\gen_axilite.s_axi_bvalid_i_reg_0 ), + .D(\m_atarget_hot_reg[11] ), .Q(mi_bvalid), - .R(SR)); + .R(reset)); LUT5 #( - .INIT(32'h74CC44CC)) + .INIT(32'h5CF050F0)) \gen_axilite.s_axi_rvalid_i_i_1 (.I0(aa_rready), - .I1(mi_rvalid), - .I2(\gen_no_arbiter.m_valid_i_reg ), + .I1(\m_ready_d_reg[1]_1 ), + .I2(mi_rvalid), .I3(Q), .I4(mi_arready), .O(\gen_axilite.s_axi_rvalid_i_i_1_n_0 )); @@ -3718,188 +3909,263 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_decerr_slave .CE(1'b1), .D(\gen_axilite.s_axi_rvalid_i_i_1_n_0 ), .Q(mi_rvalid), - .R(SR)); + .R(reset)); LUT6 #( - .INIT(64'h00CC88C0000088C0)) - \m_ready_d[1]_i_9 - (.I0(mi_arready), - .I1(\gen_no_arbiter.m_valid_i_reg ), + .INIT(64'h003300B8000000B8)) + \m_ready_d[1]_i_5 + (.I0(m_axi_arready[1]), + .I1(m_atarget_enc[2]), .I2(m_axi_arready[0]), - .I3(m_atarget_enc[1]), - .I4(m_atarget_enc[0]), - .I5(m_axi_arready[1]), - .O(\m_ready_d_reg[1] )); - LUT6 #( - .INIT(64'h00CC88C0000088C0)) - \m_ready_d[2]_i_5 + .I3(\m_atarget_enc_reg[0] ), + .I4(m_atarget_enc[3]), + .I5(mi_arready), + .O(\m_ready_d_reg[1]_0 )); + LUT4 #( + .INIT(16'h4FFF)) + \m_ready_d[2]_i_12 (.I0(mi_wready), - .I1(\gen_no_arbiter.grant_rnw_reg ), - .I2(m_axi_awready[0]), - .I3(m_atarget_enc[1]), - .I4(m_atarget_enc[0]), - .I5(m_axi_awready[1]), + .I1(m_atarget_enc[3]), + .I2(m_atarget_enc[1]), + .I3(m_atarget_enc[0]), + .O(\m_ready_d[2]_i_12_n_0 )); + LUT6 #( + .INIT(64'h0000FFFF00000001)) + \m_ready_d[2]_i_3 + (.I0(\m_atarget_enc_reg[2] ), + .I1(\s_axi_bvalid[0]_INST_0_i_3_n_0 ), + .I2(\m_atarget_enc_reg[2]_0 ), + .I3(\m_atarget_enc_reg[2]_1 ), + .I4(m_ready_d), + .I5(\gen_no_arbiter.grant_rnw_reg ), .O(\m_ready_d_reg[2] )); LUT6 #( - .INIT(64'h00CC88C0000088C0)) - m_valid_i_i_7 + .INIT(64'hEFEEEFEEEFEE0000)) + \m_ready_d[2]_i_5 + (.I0(\m_atarget_enc_reg[2]_3 ), + .I1(\m_atarget_enc_reg[1] ), + .I2(m_axi_wready[2]), + .I3(m_atarget_enc[3]), + .I4(\m_ready_d[2]_i_12_n_0 ), + .I5(\m_atarget_enc_reg[2]_4 ), + .O(\m_ready_d_reg[2]_1 )); + LUT6 #( + .INIT(64'h0011101100111000)) + \m_ready_d[2]_i_9 + (.I0(\m_ready_d[2]_i_12_n_0 ), + .I1(\m_ready_d_reg[2]_2 ), + .I2(m_axi_awready[1]), + .I3(m_atarget_enc[2]), + .I4(m_atarget_enc[3]), + .I5(m_axi_awready[0]), + .O(\m_ready_d_reg[2]_0 )); + LUT6 #( + .INIT(64'hDFFF0000FFFFFFFF)) + m_valid_i_i_2 + (.I0(m_valid_i_i_3_n_0), + .I1(\m_atarget_enc_reg[2]_2 ), + .I2(\m_atarget_enc_reg[3] ), + .I3(\m_atarget_enc_reg[3]_0 ), + .I4(\gen_no_arbiter.m_valid_i_reg ), + .I5(aa_rready), + .O(s_ready_i_reg)); + LUT6 #( + .INIT(64'hFCDCFCDFFFDCFFDF)) + m_valid_i_i_3 (.I0(mi_rvalid), - .I1(\gen_no_arbiter.m_valid_i_reg_0 ), - .I2(m_axi_rvalid[0]), - .I3(m_atarget_enc[1]), - .I4(m_atarget_enc[0]), + .I1(\m_atarget_enc_reg[0] ), + .I2(m_atarget_enc[3]), + .I3(m_atarget_enc[2]), + .I4(m_axi_rvalid[0]), .I5(m_axi_rvalid[1]), - .O(m_valid_i_reg)); + .O(m_valid_i_i_3_n_0)); + LUT4 #( + .INIT(16'hFFFE)) + \s_axi_bvalid[0]_INST_0_i_1 + (.I0(\m_atarget_enc_reg[2] ), + .I1(\s_axi_bvalid[0]_INST_0_i_3_n_0 ), + .I2(\m_atarget_enc_reg[2]_0 ), + .I3(\m_atarget_enc_reg[2]_1 ), + .O(\m_ready_d_reg[1] )); LUT6 #( - .INIT(64'h00CC88C0000088C0)) + .INIT(64'h003300B8000000B8)) \s_axi_bvalid[0]_INST_0_i_3 - (.I0(mi_bvalid), - .I1(\gen_no_arbiter.grant_rnw_reg_1 ), + (.I0(m_axi_bvalid[1]), + .I1(m_atarget_enc[2]), .I2(m_axi_bvalid[0]), - .I3(m_atarget_enc[1]), - .I4(m_atarget_enc[0]), - .I5(m_axi_bvalid[1]), - .O(\m_ready_d_reg[0] )); + .I3(\m_atarget_enc_reg[0] ), + .I4(m_atarget_enc[3]), + .I5(mi_bvalid), + .O(\s_axi_bvalid[0]_INST_0_i_3_n_0 )); LUT6 #( - .INIT(64'h00CC88C0000088C0)) - \s_axi_wready[0]_INST_0_i_3 - (.I0(mi_wready), - .I1(\gen_no_arbiter.grant_rnw_reg_0 ), - .I2(m_axi_wready[0]), - .I3(m_atarget_enc[1]), - .I4(m_atarget_enc[0]), - .I5(m_axi_wready[1]), - .O(\m_ready_d_reg[1]_0 )); + .INIT(64'hFFAAFF1BFFFFFF1B)) + \s_axi_wready[0]_INST_0_i_6 + (.I0(m_atarget_enc[2]), + .I1(m_axi_wready[0]), + .I2(m_axi_wready[1]), + .I3(\m_atarget_enc_reg[0] ), + .I4(m_atarget_enc[3]), + .I5(mi_wready), + .O(\s_axi_wready[0] )); endmodule (* ORIG_REF_NAME = "axi_crossbar_v2_1_12_splitter" *) module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_splitter - (\gen_no_arbiter.m_valid_i_reg , - \gen_no_arbiter.m_valid_i_reg_0 , - \gen_no_arbiter.m_valid_i_reg_1 , - \gen_no_arbiter.m_valid_i_reg_2 , + (\m_ready_d_reg[2]_0 , + \m_ready_d_reg[2]_1 , + \m_ready_d_reg[2]_2 , + \m_ready_d_reg[2]_3 , + \m_ready_d_reg[2]_4 , + \m_ready_d_reg[2]_5 , + \m_ready_d_reg[2]_6 , + \m_ready_d_reg[2]_7 , + \m_ready_d_reg[2]_8 , + \m_ready_d_reg[2]_9 , + \m_ready_d_reg[2]_10 , + \m_ready_d_reg[2]_11 , + \m_ready_d_reg[2]_12 , m_ready_d, - m_axi_wready, - m_atarget_enc, m_axi_bvalid, - m_valid_i, - aa_grant_rnw, - mi_awready_mux, + m_atarget_enc, + m_axi_wready, + \m_atarget_enc_reg[0] , + m_axi_awready, aresetn_d, - aa_awready, - aa_wready, - \gen_no_arbiter.grant_rnw_reg , - s_axi_wvalid, - aa_bvalid, - s_axi_bready, - \gen_no_arbiter.grant_rnw_reg_0 , + m_ready_d0, + \m_ready_d_reg[0]_0 , + \m_ready_d_reg[2]_13 , + \gen_no_arbiter.m_valid_i_reg , aclk); - output \gen_no_arbiter.m_valid_i_reg ; - output \gen_no_arbiter.m_valid_i_reg_0 ; - output \gen_no_arbiter.m_valid_i_reg_1 ; - output \gen_no_arbiter.m_valid_i_reg_2 ; + output \m_ready_d_reg[2]_0 ; + output \m_ready_d_reg[2]_1 ; + output \m_ready_d_reg[2]_2 ; + output \m_ready_d_reg[2]_3 ; + output \m_ready_d_reg[2]_4 ; + output \m_ready_d_reg[2]_5 ; + output \m_ready_d_reg[2]_6 ; + output \m_ready_d_reg[2]_7 ; + output \m_ready_d_reg[2]_8 ; + output \m_ready_d_reg[2]_9 ; + output \m_ready_d_reg[2]_10 ; + output \m_ready_d_reg[2]_11 ; + output \m_ready_d_reg[2]_12 ; output [2:0]m_ready_d; - input [3:0]m_axi_wready; - input [1:0]m_atarget_enc; - input [3:0]m_axi_bvalid; - input m_valid_i; - input aa_grant_rnw; - input mi_awready_mux; + input [8:0]m_axi_bvalid; + input [3:0]m_atarget_enc; + input [9:0]m_axi_wready; + input \m_atarget_enc_reg[0] ; + input [3:0]m_axi_awready; input aresetn_d; - input aa_awready; - input aa_wready; - input \gen_no_arbiter.grant_rnw_reg ; - input [0:0]s_axi_wvalid; - input aa_bvalid; - input [0:0]s_axi_bready; - input \gen_no_arbiter.grant_rnw_reg_0 ; + input [0:0]m_ready_d0; + input \m_ready_d_reg[0]_0 ; + input \m_ready_d_reg[2]_13 ; + input \gen_no_arbiter.m_valid_i_reg ; input aclk; - wire aa_awready; - wire aa_bvalid; - wire aa_grant_rnw; - wire aa_wready; wire aclk; wire aresetn_d; - wire \gen_no_arbiter.grant_rnw_reg ; - wire \gen_no_arbiter.grant_rnw_reg_0 ; wire \gen_no_arbiter.m_valid_i_reg ; - wire \gen_no_arbiter.m_valid_i_reg_0 ; - wire \gen_no_arbiter.m_valid_i_reg_1 ; - wire \gen_no_arbiter.m_valid_i_reg_2 ; - wire [1:0]m_atarget_enc; - wire [3:0]m_axi_bvalid; - wire [3:0]m_axi_wready; + wire [3:0]m_atarget_enc; + wire \m_atarget_enc_reg[0] ; + wire [3:0]m_axi_awready; + wire [8:0]m_axi_bvalid; + wire [9:0]m_axi_wready; wire [2:0]m_ready_d; + wire [0:0]m_ready_d0; wire \m_ready_d[0]_i_1_n_0 ; wire \m_ready_d[1]_i_1_n_0 ; wire \m_ready_d[2]_i_1_n_0 ; - wire m_valid_i; - wire mi_awready_mux; - wire [0:0]s_axi_bready; - wire [0:0]s_axi_wvalid; + wire \m_ready_d_reg[0]_0 ; + wire \m_ready_d_reg[2]_0 ; + wire \m_ready_d_reg[2]_1 ; + wire \m_ready_d_reg[2]_10 ; + wire \m_ready_d_reg[2]_11 ; + wire \m_ready_d_reg[2]_12 ; + wire \m_ready_d_reg[2]_13 ; + wire \m_ready_d_reg[2]_2 ; + wire \m_ready_d_reg[2]_3 ; + wire \m_ready_d_reg[2]_4 ; + wire \m_ready_d_reg[2]_5 ; + wire \m_ready_d_reg[2]_6 ; + wire \m_ready_d_reg[2]_7 ; + wire \m_ready_d_reg[2]_8 ; + wire \m_ready_d_reg[2]_9 ; - LUT6 #( - .INIT(64'h00000000FF800000)) + (* SOFT_HLUTNM = "soft_lutpair61" *) + LUT4 #( + .INIT(16'h4404)) \m_ready_d[0]_i_1 - (.I0(aa_bvalid), - .I1(s_axi_bready), - .I2(\gen_no_arbiter.grant_rnw_reg_0 ), - .I3(m_ready_d[0]), - .I4(aresetn_d), - .I5(aa_awready), + (.I0(\m_ready_d_reg[0]_0 ), + .I1(aresetn_d), + .I2(m_ready_d0), + .I3(\gen_no_arbiter.m_valid_i_reg ), .O(\m_ready_d[0]_i_1_n_0 )); - LUT6 #( - .INIT(64'h00000000FF800000)) + LUT3 #( + .INIT(8'h80)) \m_ready_d[1]_i_1 - (.I0(aa_wready), - .I1(\gen_no_arbiter.grant_rnw_reg ), - .I2(s_axi_wvalid), - .I3(m_ready_d[1]), - .I4(aresetn_d), - .I5(aa_awready), + (.I0(aresetn_d), + .I1(m_ready_d0), + .I2(\gen_no_arbiter.m_valid_i_reg ), .O(\m_ready_d[1]_i_1_n_0 )); - LUT6 #( - .INIT(64'h00000000AEAA0000)) + (* SOFT_HLUTNM = "soft_lutpair61" *) + LUT4 #( + .INIT(16'h00A2)) \m_ready_d[2]_i_1 - (.I0(m_ready_d[2]), - .I1(m_valid_i), - .I2(aa_grant_rnw), - .I3(mi_awready_mux), - .I4(aresetn_d), - .I5(aa_awready), + (.I0(aresetn_d), + .I1(m_ready_d0), + .I2(\m_ready_d_reg[0]_0 ), + .I3(\m_ready_d_reg[2]_13 ), .O(\m_ready_d[2]_i_1_n_0 )); - (* SOFT_HLUTNM = "soft_lutpair44" *) - LUT3 #( - .INIT(8'hB8)) - \m_ready_d[2]_i_12 - (.I0(m_axi_wready[3]), + LUT4 #( + .INIT(16'h5053)) + \m_ready_d[2]_i_10 + (.I0(m_axi_wready[4]), + .I1(m_axi_wready[0]), + .I2(m_atarget_enc[2]), + .I3(m_atarget_enc[3]), + .O(\m_ready_d_reg[2]_9 )); + (* SOFT_HLUTNM = "soft_lutpair59" *) + LUT4 #( + .INIT(16'hFEEE)) + \m_ready_d[2]_i_11 + (.I0(m_atarget_enc[1]), .I1(m_atarget_enc[0]), - .I2(m_axi_wready[1]), - .O(\gen_no_arbiter.m_valid_i_reg_0 )); + .I2(m_atarget_enc[3]), + .I3(m_atarget_enc[2]), + .O(\m_ready_d_reg[2]_11 )); LUT4 #( - .INIT(16'h3B38)) + .INIT(16'hF053)) \m_ready_d[2]_i_13 - (.I0(m_axi_wready[2]), - .I1(m_atarget_enc[0]), - .I2(m_atarget_enc[1]), - .I3(m_axi_wready[0]), - .O(\gen_no_arbiter.m_valid_i_reg )); - (* SOFT_HLUTNM = "soft_lutpair44" *) - LUT3 #( - .INIT(8'hB8)) + (.I0(m_axi_wready[7]), + .I1(m_axi_wready[3]), + .I2(m_atarget_enc[2]), + .I3(m_atarget_enc[3]), + .O(\m_ready_d_reg[2]_8 )); + (* SOFT_HLUTNM = "soft_lutpair59" *) + LUT4 #( + .INIT(16'hFF4F)) \m_ready_d[2]_i_14 - (.I0(m_axi_bvalid[3]), - .I1(m_atarget_enc[0]), - .I2(m_axi_bvalid[1]), - .O(\gen_no_arbiter.m_valid_i_reg_2 )); + (.I0(m_axi_awready[3]), + .I1(m_atarget_enc[3]), + .I2(m_atarget_enc[0]), + .I3(m_atarget_enc[1]), + .O(\m_ready_d_reg[2]_7 )); + (* SOFT_HLUTNM = "soft_lutpair60" *) LUT4 #( - .INIT(16'h3B38)) + .INIT(16'hFFF4)) \m_ready_d[2]_i_15 - (.I0(m_axi_bvalid[2]), - .I1(m_atarget_enc[0]), + (.I0(m_axi_awready[2]), + .I1(m_atarget_enc[3]), .I2(m_atarget_enc[1]), - .I3(m_axi_bvalid[0]), - .O(\gen_no_arbiter.m_valid_i_reg_1 )); + .I3(m_atarget_enc[0]), + .O(\m_ready_d_reg[2]_12 )); + LUT4 #( + .INIT(16'hF053)) + \m_ready_d[2]_i_16 + (.I0(m_axi_awready[1]), + .I1(m_axi_awready[0]), + .I2(m_atarget_enc[2]), + .I3(m_atarget_enc[3]), + .O(\m_ready_d_reg[2]_10 )); FDRE \m_ready_d_reg[0] (.C(aclk), .CE(1'b1), @@ -3918,77 +4184,178 @@ module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_splitter .D(\m_ready_d[2]_i_1_n_0 ), .Q(m_ready_d[2]), .R(1'b0)); + LUT6 #( + .INIT(64'h003300B8000000B8)) + \s_axi_bvalid[0]_INST_0_i_2 + (.I0(m_axi_bvalid[5]), + .I1(m_atarget_enc[2]), + .I2(m_axi_bvalid[2]), + .I3(\m_ready_d_reg[2]_1 ), + .I4(m_atarget_enc[3]), + .I5(m_axi_bvalid[8]), + .O(\m_ready_d_reg[2]_0 )); + LUT6 #( + .INIT(64'h003300B8000000B8)) + \s_axi_bvalid[0]_INST_0_i_4 + (.I0(m_axi_bvalid[4]), + .I1(m_atarget_enc[2]), + .I2(m_axi_bvalid[1]), + .I3(\m_ready_d_reg[2]_4 ), + .I4(m_atarget_enc[3]), + .I5(m_axi_bvalid[7]), + .O(\m_ready_d_reg[2]_5 )); + LUT6 #( + .INIT(64'h003300B8000000B8)) + \s_axi_bvalid[0]_INST_0_i_5 + (.I0(m_axi_bvalid[3]), + .I1(m_atarget_enc[2]), + .I2(m_axi_bvalid[0]), + .I3(\m_atarget_enc_reg[0] ), + .I4(m_atarget_enc[3]), + .I5(m_axi_bvalid[6]), + .O(\m_ready_d_reg[2]_6 )); + LUT6 #( + .INIT(64'h003300B8000000B8)) + \s_axi_wready[0]_INST_0_i_3 + (.I0(m_axi_wready[5]), + .I1(m_atarget_enc[2]), + .I2(m_axi_wready[1]), + .I3(\m_ready_d_reg[2]_4 ), + .I4(m_atarget_enc[3]), + .I5(m_axi_wready[8]), + .O(\m_ready_d_reg[2]_3 )); + LUT6 #( + .INIT(64'h003300B8000000B8)) + \s_axi_wready[0]_INST_0_i_4 + (.I0(m_axi_wready[6]), + .I1(m_atarget_enc[2]), + .I2(m_axi_wready[2]), + .I3(\m_ready_d_reg[2]_1 ), + .I4(m_atarget_enc[3]), + .I5(m_axi_wready[9]), + .O(\m_ready_d_reg[2]_2 )); + LUT2 #( + .INIT(4'hB)) + \s_axi_wready[0]_INST_0_i_7 + (.I0(m_atarget_enc[1]), + .I1(m_atarget_enc[0]), + .O(\m_ready_d_reg[2]_4 )); + (* SOFT_HLUTNM = "soft_lutpair60" *) + LUT2 #( + .INIT(4'hB)) + \s_axi_wready[0]_INST_0_i_8 + (.I0(m_atarget_enc[0]), + .I1(m_atarget_enc[1]), + .O(\m_ready_d_reg[2]_1 )); endmodule (* ORIG_REF_NAME = "axi_crossbar_v2_1_12_splitter" *) module Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_splitter__parameterized0 - (\gen_no_arbiter.m_valid_i_reg , + (\m_ready_d_reg[1]_0 , + \m_ready_d_reg[1]_1 , + \m_ready_d_reg[1]_2 , m_ready_d, - \m_payload_i_reg[0] , - \m_atarget_enc_reg[2] , + m_axi_arready, + \m_atarget_enc_reg[0] , m_atarget_enc, - \m_atarget_enc_reg[2]_0 , - \gen_no_arbiter.m_valid_i_reg_0 , + \m_atarget_enc_reg[0]_0 , + \m_atarget_enc_reg[1] , aresetn_d, - mi_arready_mux, - \gen_no_arbiter.m_valid_i_reg_1 , + m_ready_d0, + \m_ready_d_reg[0]_0 , + s_axi_rready, + \gen_no_arbiter.grant_rnw_reg , + sr_rvalid, + Q, + aresetn_d_reg, aclk); - output \gen_no_arbiter.m_valid_i_reg ; + output \m_ready_d_reg[1]_0 ; + output \m_ready_d_reg[1]_1 ; + output \m_ready_d_reg[1]_2 ; output [1:0]m_ready_d; - input \m_payload_i_reg[0] ; - input \m_atarget_enc_reg[2] ; - input [0:0]m_atarget_enc; - input \m_atarget_enc_reg[2]_0 ; - input \gen_no_arbiter.m_valid_i_reg_0 ; + input [8:0]m_axi_arready; + input \m_atarget_enc_reg[0] ; + input [1:0]m_atarget_enc; + input \m_atarget_enc_reg[0]_0 ; + input \m_atarget_enc_reg[1] ; input aresetn_d; - input mi_arready_mux; - input \gen_no_arbiter.m_valid_i_reg_1 ; + input [0:0]m_ready_d0; + input \m_ready_d_reg[0]_0 ; + input [0:0]s_axi_rready; + input \gen_no_arbiter.grant_rnw_reg ; + input sr_rvalid; + input [0:0]Q; + input aresetn_d_reg; input aclk; + wire [0:0]Q; wire aclk; wire aresetn_d; - wire \gen_no_arbiter.m_valid_i_reg ; - wire \gen_no_arbiter.m_valid_i_reg_0 ; - wire \gen_no_arbiter.m_valid_i_reg_1 ; - wire [0:0]m_atarget_enc; - wire \m_atarget_enc_reg[2] ; - wire \m_atarget_enc_reg[2]_0 ; - wire \m_payload_i_reg[0] ; + wire aresetn_d_reg; + wire \gen_no_arbiter.grant_rnw_reg ; + wire [1:0]m_atarget_enc; + wire \m_atarget_enc_reg[0] ; + wire \m_atarget_enc_reg[0]_0 ; + wire \m_atarget_enc_reg[1] ; + wire [8:0]m_axi_arready; wire [1:0]m_ready_d; + wire [0:0]m_ready_d0; wire \m_ready_d[0]_i_1_n_0 ; wire \m_ready_d[1]_i_1_n_0 ; - wire mi_arready_mux; + wire \m_ready_d_reg[0]_0 ; + wire \m_ready_d_reg[1]_0 ; + wire \m_ready_d_reg[1]_1 ; + wire \m_ready_d_reg[1]_2 ; + wire [0:0]s_axi_rready; + wire sr_rvalid; LUT6 #( - .INIT(64'hEEEEEEEEE0EEE000)) - \gen_no_arbiter.m_valid_i_i_2 - (.I0(\m_payload_i_reg[0] ), - .I1(m_ready_d[0]), - .I2(\m_atarget_enc_reg[2] ), - .I3(m_atarget_enc), - .I4(\m_atarget_enc_reg[2]_0 ), - .I5(m_ready_d[1]), - .O(\gen_no_arbiter.m_valid_i_reg )); - LUT6 #( - .INIT(64'h000000000000CC80)) + .INIT(64'h00000000AEAAAAAA)) \m_ready_d[0]_i_1 - (.I0(\gen_no_arbiter.m_valid_i_reg_1 ), - .I1(aresetn_d), - .I2(\m_payload_i_reg[0] ), - .I3(m_ready_d[0]), - .I4(mi_arready_mux), - .I5(m_ready_d[1]), + (.I0(m_ready_d[0]), + .I1(s_axi_rready), + .I2(\gen_no_arbiter.grant_rnw_reg ), + .I3(sr_rvalid), + .I4(Q), + .I5(aresetn_d_reg), .O(\m_ready_d[0]_i_1_n_0 )); - LUT6 #( - .INIT(64'h000C000C00080000)) + LUT3 #( + .INIT(8'h80)) \m_ready_d[1]_i_1 - (.I0(\gen_no_arbiter.m_valid_i_reg_0 ), - .I1(aresetn_d), - .I2(\m_payload_i_reg[0] ), - .I3(m_ready_d[0]), - .I4(mi_arready_mux), - .I5(m_ready_d[1]), + (.I0(aresetn_d), + .I1(m_ready_d0), + .I2(\m_ready_d_reg[0]_0 ), .O(\m_ready_d[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'h003300B8000000B8)) + \m_ready_d[1]_i_4 + (.I0(m_axi_arready[4]), + .I1(m_atarget_enc[0]), + .I2(m_axi_arready[1]), + .I3(\m_atarget_enc_reg[1] ), + .I4(m_atarget_enc[1]), + .I5(m_axi_arready[7]), + .O(\m_ready_d_reg[1]_2 )); + LUT6 #( + .INIT(64'hFCDCFCDFFFDCFFDF)) + \m_ready_d[1]_i_6 + (.I0(m_axi_arready[8]), + .I1(\m_atarget_enc_reg[0] ), + .I2(m_atarget_enc[1]), + .I3(m_atarget_enc[0]), + .I4(m_axi_arready[2]), + .I5(m_axi_arready[5]), + .O(\m_ready_d_reg[1]_0 )); + LUT6 #( + .INIT(64'h003300B8000000B8)) + \m_ready_d[1]_i_7 + (.I0(m_axi_arready[3]), + .I1(m_atarget_enc[0]), + .I2(m_axi_arready[0]), + .I3(\m_atarget_enc_reg[0]_0 ), + .I4(m_atarget_enc[1]), + .I5(m_axi_arready[6]), + .O(\m_ready_d_reg[1]_1 )); FDRE \m_ready_d_reg[0] (.C(aclk), .CE(1'b1), @@ -4007,181 +4374,279 @@ endmodule module Arty_Z7_20_xbar_0_axi_register_slice_v2_1_11_axic_register_slice (sr_rvalid, aa_rready, - \m_ready_d_reg[1] , - \skid_buffer_reg[1]_0 , - \skid_buffer_reg[1]_1 , - \skid_buffer_reg[1]_2 , - \skid_buffer_reg[1]_3 , + \gen_no_arbiter.m_grant_hot_i_reg[0] , + Q, + \skid_buffer_reg[30]_0 , + \m_payload_i_reg[2]_0 , + \m_payload_i_reg[2]_1 , + \m_payload_i_reg[1]_0 , + \skid_buffer_reg[9]_0 , + s_ready_i_reg_0, + s_ready_i_reg_1, + \m_ready_d_reg[2] , + s_ready_i_reg_2, + s_ready_i_reg_3, m_axi_rready, - \s_axi_rdata[31] , aclk, - aa_rvalid, + s_ready_i_reg_4, E, + m_axi_rresp, + m_atarget_enc, s_axi_rready, m_ready_d, - aa_grant_rnw, m_valid_i, - m_axi_rresp, - m_atarget_enc, + aa_grant_rnw, m_axi_rdata, - Q, - SR); + m_axi_rvalid, + \m_atarget_enc_reg[0] , + \m_atarget_enc_reg[1] , + \m_atarget_hot_reg[10] , + reset); output sr_rvalid; output aa_rready; - output \m_ready_d_reg[1] ; - output \skid_buffer_reg[1]_0 ; - output \skid_buffer_reg[1]_1 ; - output \skid_buffer_reg[1]_2 ; - output \skid_buffer_reg[1]_3 ; - output [8:0]m_axi_rready; - output [33:0]\s_axi_rdata[31] ; + output \gen_no_arbiter.m_grant_hot_i_reg[0] ; + output [34:0]Q; + output \skid_buffer_reg[30]_0 ; + output \m_payload_i_reg[2]_0 ; + output \m_payload_i_reg[2]_1 ; + output \m_payload_i_reg[1]_0 ; + output \skid_buffer_reg[9]_0 ; + output s_ready_i_reg_0; + output s_ready_i_reg_1; + output \m_ready_d_reg[2] ; + output s_ready_i_reg_2; + output s_ready_i_reg_3; + output [10:0]m_axi_rready; input aclk; - input aa_rvalid; + input s_ready_i_reg_4; input [0:0]E; + input [21:0]m_axi_rresp; + input [3:0]m_atarget_enc; input [0:0]s_axi_rready; input [0:0]m_ready_d; - input aa_grant_rnw; input m_valid_i; - input [17:0]m_axi_rresp; - input [3:0]m_atarget_enc; - input [287:0]m_axi_rdata; - input [8:0]Q; - input [0:0]SR; + input aa_grant_rnw; + input [351:0]m_axi_rdata; + input [8:0]m_axi_rvalid; + input \m_atarget_enc_reg[0] ; + input \m_atarget_enc_reg[1] ; + input [10:0]\m_atarget_hot_reg[10] ; + input reset; wire [0:0]E; - wire [8:0]Q; - wire [0:0]SR; + wire [34:0]Q; wire aa_grant_rnw; - wire [34:0]aa_rmesg; wire aa_rready; - wire aa_rvalid; wire aclk; wire \aresetn_d_reg_n_0_[0] ; wire \aresetn_d_reg_n_0_[1] ; + wire \gen_no_arbiter.m_grant_hot_i_reg[0] ; wire [3:0]m_atarget_enc; - wire [287:0]m_axi_rdata; - wire [8:0]m_axi_rready; - wire [17:0]m_axi_rresp; - wire \m_payload_i_reg_n_0_[0] ; + wire \m_atarget_enc_reg[0] ; + wire \m_atarget_enc_reg[1] ; + wire [10:0]\m_atarget_hot_reg[10] ; + wire [351:0]m_axi_rdata; + wire [10:0]m_axi_rready; + wire [21:0]m_axi_rresp; + wire [8:0]m_axi_rvalid; + wire \m_payload_i[1]_i_2_n_0 ; + wire \m_payload_i[1]_i_3_n_0 ; + wire \m_payload_i[1]_i_4_n_0 ; + wire \m_payload_i[1]_i_5_n_0 ; + wire \m_payload_i[1]_i_6_n_0 ; + wire \m_payload_i[1]_i_7_n_0 ; + wire \m_payload_i[1]_i_8_n_0 ; + wire \m_payload_i[1]_i_9_n_0 ; + wire \m_payload_i[2]_i_2_n_0 ; + wire \m_payload_i[2]_i_3_n_0 ; + wire \m_payload_i[2]_i_4_n_0 ; + wire \m_payload_i[2]_i_5_n_0 ; + wire \m_payload_i[2]_i_6_n_0 ; + wire \m_payload_i[2]_i_7_n_0 ; + wire \m_payload_i_reg[1]_0 ; + wire \m_payload_i_reg[2]_0 ; + wire \m_payload_i_reg[2]_1 ; wire [0:0]m_ready_d; - wire \m_ready_d_reg[1] ; + wire \m_ready_d_reg[2] ; wire m_valid_i; wire m_valid_i_i_1_n_0; - wire [33:0]\s_axi_rdata[31] ; + wire reset; wire [0:0]s_axi_rready; wire s_ready_i_i_1_n_0; + wire s_ready_i_reg_0; + wire s_ready_i_reg_1; + wire s_ready_i_reg_2; + wire s_ready_i_reg_3; + wire s_ready_i_reg_4; wire [34:0]skid_buffer; + wire \skid_buffer[0]_i_1_n_0 ; + wire \skid_buffer[10]_i_1_n_0 ; wire \skid_buffer[10]_i_2_n_0 ; wire \skid_buffer[10]_i_3_n_0 ; wire \skid_buffer[10]_i_4_n_0 ; + wire \skid_buffer[10]_i_5_n_0 ; + wire \skid_buffer[11]_i_1_n_0 ; wire \skid_buffer[11]_i_2_n_0 ; wire \skid_buffer[11]_i_3_n_0 ; wire \skid_buffer[11]_i_4_n_0 ; + wire \skid_buffer[11]_i_5_n_0 ; + wire \skid_buffer[12]_i_1_n_0 ; wire \skid_buffer[12]_i_2_n_0 ; wire \skid_buffer[12]_i_3_n_0 ; wire \skid_buffer[12]_i_4_n_0 ; + wire \skid_buffer[12]_i_5_n_0 ; + wire \skid_buffer[13]_i_1_n_0 ; wire \skid_buffer[13]_i_2_n_0 ; wire \skid_buffer[13]_i_3_n_0 ; wire \skid_buffer[13]_i_4_n_0 ; + wire \skid_buffer[13]_i_5_n_0 ; + wire \skid_buffer[14]_i_1_n_0 ; wire \skid_buffer[14]_i_2_n_0 ; wire \skid_buffer[14]_i_3_n_0 ; wire \skid_buffer[14]_i_4_n_0 ; + wire \skid_buffer[14]_i_5_n_0 ; + wire \skid_buffer[15]_i_1_n_0 ; wire \skid_buffer[15]_i_2_n_0 ; wire \skid_buffer[15]_i_3_n_0 ; wire \skid_buffer[15]_i_4_n_0 ; + wire \skid_buffer[15]_i_5_n_0 ; + wire \skid_buffer[16]_i_1_n_0 ; wire \skid_buffer[16]_i_2_n_0 ; wire \skid_buffer[16]_i_3_n_0 ; wire \skid_buffer[16]_i_4_n_0 ; + wire \skid_buffer[16]_i_5_n_0 ; + wire \skid_buffer[17]_i_1_n_0 ; wire \skid_buffer[17]_i_2_n_0 ; wire \skid_buffer[17]_i_3_n_0 ; wire \skid_buffer[17]_i_4_n_0 ; + wire \skid_buffer[17]_i_5_n_0 ; + wire \skid_buffer[18]_i_1_n_0 ; wire \skid_buffer[18]_i_2_n_0 ; wire \skid_buffer[18]_i_3_n_0 ; wire \skid_buffer[18]_i_4_n_0 ; + wire \skid_buffer[18]_i_5_n_0 ; + wire \skid_buffer[19]_i_1_n_0 ; wire \skid_buffer[19]_i_2_n_0 ; wire \skid_buffer[19]_i_3_n_0 ; wire \skid_buffer[19]_i_4_n_0 ; - wire \skid_buffer[1]_i_2_n_0 ; - wire \skid_buffer[1]_i_3_n_0 ; - wire \skid_buffer[1]_i_4_n_0 ; - wire \skid_buffer[1]_i_5_n_0 ; + wire \skid_buffer[19]_i_5_n_0 ; + wire \skid_buffer[20]_i_1_n_0 ; wire \skid_buffer[20]_i_2_n_0 ; wire \skid_buffer[20]_i_3_n_0 ; wire \skid_buffer[20]_i_4_n_0 ; + wire \skid_buffer[20]_i_5_n_0 ; + wire \skid_buffer[21]_i_1_n_0 ; wire \skid_buffer[21]_i_2_n_0 ; wire \skid_buffer[21]_i_3_n_0 ; wire \skid_buffer[21]_i_4_n_0 ; + wire \skid_buffer[21]_i_5_n_0 ; + wire \skid_buffer[22]_i_1_n_0 ; wire \skid_buffer[22]_i_2_n_0 ; wire \skid_buffer[22]_i_3_n_0 ; wire \skid_buffer[22]_i_4_n_0 ; + wire \skid_buffer[22]_i_5_n_0 ; + wire \skid_buffer[23]_i_1_n_0 ; wire \skid_buffer[23]_i_2_n_0 ; wire \skid_buffer[23]_i_3_n_0 ; wire \skid_buffer[23]_i_4_n_0 ; + wire \skid_buffer[23]_i_5_n_0 ; + wire \skid_buffer[24]_i_1_n_0 ; wire \skid_buffer[24]_i_2_n_0 ; wire \skid_buffer[24]_i_3_n_0 ; wire \skid_buffer[24]_i_4_n_0 ; + wire \skid_buffer[24]_i_5_n_0 ; + wire \skid_buffer[25]_i_1_n_0 ; wire \skid_buffer[25]_i_2_n_0 ; wire \skid_buffer[25]_i_3_n_0 ; wire \skid_buffer[25]_i_4_n_0 ; + wire \skid_buffer[25]_i_5_n_0 ; + wire \skid_buffer[26]_i_1_n_0 ; wire \skid_buffer[26]_i_2_n_0 ; wire \skid_buffer[26]_i_3_n_0 ; wire \skid_buffer[26]_i_4_n_0 ; + wire \skid_buffer[26]_i_5_n_0 ; + wire \skid_buffer[27]_i_1_n_0 ; wire \skid_buffer[27]_i_2_n_0 ; wire \skid_buffer[27]_i_3_n_0 ; wire \skid_buffer[27]_i_4_n_0 ; + wire \skid_buffer[27]_i_5_n_0 ; + wire \skid_buffer[28]_i_1_n_0 ; wire \skid_buffer[28]_i_2_n_0 ; wire \skid_buffer[28]_i_3_n_0 ; wire \skid_buffer[28]_i_4_n_0 ; + wire \skid_buffer[28]_i_5_n_0 ; + wire \skid_buffer[28]_i_6_n_0 ; + wire \skid_buffer[29]_i_1_n_0 ; wire \skid_buffer[29]_i_2_n_0 ; wire \skid_buffer[29]_i_3_n_0 ; wire \skid_buffer[29]_i_4_n_0 ; - wire \skid_buffer[2]_i_2_n_0 ; - wire \skid_buffer[2]_i_3_n_0 ; - wire \skid_buffer[2]_i_4_n_0 ; - wire \skid_buffer[2]_i_5_n_0 ; + wire \skid_buffer[29]_i_5_n_0 ; + wire \skid_buffer[30]_i_1_n_0 ; wire \skid_buffer[30]_i_2_n_0 ; wire \skid_buffer[30]_i_3_n_0 ; wire \skid_buffer[30]_i_4_n_0 ; + wire \skid_buffer[30]_i_5_n_0 ; + wire \skid_buffer[31]_i_1_n_0 ; wire \skid_buffer[31]_i_2_n_0 ; wire \skid_buffer[31]_i_3_n_0 ; wire \skid_buffer[31]_i_4_n_0 ; + wire \skid_buffer[31]_i_5_n_0 ; + wire \skid_buffer[31]_i_6_n_0 ; + wire \skid_buffer[32]_i_1_n_0 ; wire \skid_buffer[32]_i_2_n_0 ; wire \skid_buffer[32]_i_3_n_0 ; wire \skid_buffer[32]_i_4_n_0 ; + wire \skid_buffer[32]_i_5_n_0 ; + wire \skid_buffer[32]_i_6_n_0 ; + wire \skid_buffer[33]_i_1_n_0 ; wire \skid_buffer[33]_i_2_n_0 ; wire \skid_buffer[33]_i_3_n_0 ; wire \skid_buffer[33]_i_4_n_0 ; + wire \skid_buffer[33]_i_5_n_0 ; + wire \skid_buffer[34]_i_1_n_0 ; wire \skid_buffer[34]_i_2_n_0 ; wire \skid_buffer[34]_i_3_n_0 ; wire \skid_buffer[34]_i_4_n_0 ; wire \skid_buffer[34]_i_5_n_0 ; wire \skid_buffer[34]_i_6_n_0 ; wire \skid_buffer[34]_i_7_n_0 ; + wire \skid_buffer[3]_i_1_n_0 ; wire \skid_buffer[3]_i_2_n_0 ; wire \skid_buffer[3]_i_3_n_0 ; wire \skid_buffer[3]_i_4_n_0 ; + wire \skid_buffer[3]_i_5_n_0 ; + wire \skid_buffer[4]_i_1_n_0 ; wire \skid_buffer[4]_i_2_n_0 ; wire \skid_buffer[4]_i_3_n_0 ; wire \skid_buffer[4]_i_4_n_0 ; + wire \skid_buffer[4]_i_5_n_0 ; + wire \skid_buffer[5]_i_1_n_0 ; wire \skid_buffer[5]_i_2_n_0 ; wire \skid_buffer[5]_i_3_n_0 ; wire \skid_buffer[5]_i_4_n_0 ; + wire \skid_buffer[5]_i_5_n_0 ; + wire \skid_buffer[6]_i_1_n_0 ; wire \skid_buffer[6]_i_2_n_0 ; wire \skid_buffer[6]_i_3_n_0 ; wire \skid_buffer[6]_i_4_n_0 ; + wire \skid_buffer[6]_i_5_n_0 ; + wire \skid_buffer[7]_i_1_n_0 ; wire \skid_buffer[7]_i_2_n_0 ; wire \skid_buffer[7]_i_3_n_0 ; wire \skid_buffer[7]_i_4_n_0 ; + wire \skid_buffer[7]_i_5_n_0 ; + wire \skid_buffer[8]_i_1_n_0 ; wire \skid_buffer[8]_i_2_n_0 ; wire \skid_buffer[8]_i_3_n_0 ; wire \skid_buffer[8]_i_4_n_0 ; + wire \skid_buffer[8]_i_5_n_0 ; + wire \skid_buffer[9]_i_1_n_0 ; wire \skid_buffer[9]_i_2_n_0 ; wire \skid_buffer[9]_i_3_n_0 ; wire \skid_buffer[9]_i_4_n_0 ; - wire \skid_buffer_reg[1]_0 ; - wire \skid_buffer_reg[1]_1 ; - wire \skid_buffer_reg[1]_2 ; - wire \skid_buffer_reg[1]_3 ; + wire \skid_buffer[9]_i_5_n_0 ; + wire \skid_buffer_reg[30]_0 ; + wire \skid_buffer_reg[9]_0 ; wire \skid_buffer_reg_n_0_[0] ; wire \skid_buffer_reg_n_0_[10] ; wire \skid_buffer_reg_n_0_[11] ; @@ -4226,7 +4691,7 @@ module Arty_Z7_20_xbar_0_axi_register_slice_v2_1_11_axic_register_slice .CE(1'b1), .D(1'b1), .Q(\aresetn_d_reg_n_0_[0] ), - .R(SR)); + .R(reset)); FDRE #( .INIT(1'b0)) \aresetn_d_reg[1] @@ -4234,625 +4699,831 @@ module Arty_Z7_20_xbar_0_axi_register_slice_v2_1_11_axic_register_slice .CE(1'b1), .D(\aresetn_d_reg_n_0_[0] ), .Q(\aresetn_d_reg_n_0_[1] ), - .R(SR)); - (* SOFT_HLUTNM = "soft_lutpair40" *) + .R(reset)); + LUT6 #( + .INIT(64'hFF80000000000000)) + \gen_no_arbiter.m_valid_i_i_3 + (.I0(Q[0]), + .I1(sr_rvalid), + .I2(s_axi_rready), + .I3(m_ready_d), + .I4(m_valid_i), + .I5(aa_grant_rnw), + .O(\gen_no_arbiter.m_grant_hot_i_reg[0] )); LUT2 #( .INIT(4'h8)) \m_axi_rready[0]_INST_0 - (.I0(Q[0]), - .I1(aa_rready), + (.I0(aa_rready), + .I1(\m_atarget_hot_reg[10] [0]), .O(m_axi_rready[0])); - (* SOFT_HLUTNM = "soft_lutpair40" *) + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_rready[10]_INST_0 + (.I0(aa_rready), + .I1(\m_atarget_hot_reg[10] [10]), + .O(m_axi_rready[10])); + (* SOFT_HLUTNM = "soft_lutpair58" *) LUT2 #( .INIT(4'h8)) \m_axi_rready[1]_INST_0 - (.I0(Q[1]), - .I1(aa_rready), + (.I0(aa_rready), + .I1(\m_atarget_hot_reg[10] [1]), .O(m_axi_rready[1])); - (* SOFT_HLUTNM = "soft_lutpair41" *) + (* SOFT_HLUTNM = "soft_lutpair58" *) LUT2 #( .INIT(4'h8)) \m_axi_rready[2]_INST_0 - (.I0(Q[2]), - .I1(aa_rready), + (.I0(aa_rready), + .I1(\m_atarget_hot_reg[10] [2]), .O(m_axi_rready[2])); - (* SOFT_HLUTNM = "soft_lutpair41" *) + (* SOFT_HLUTNM = "soft_lutpair57" *) LUT2 #( .INIT(4'h8)) \m_axi_rready[3]_INST_0 - (.I0(Q[3]), - .I1(aa_rready), + (.I0(aa_rready), + .I1(\m_atarget_hot_reg[10] [3]), .O(m_axi_rready[3])); - (* SOFT_HLUTNM = "soft_lutpair42" *) + (* SOFT_HLUTNM = "soft_lutpair57" *) LUT2 #( .INIT(4'h8)) \m_axi_rready[4]_INST_0 - (.I0(Q[4]), - .I1(aa_rready), + (.I0(aa_rready), + .I1(\m_atarget_hot_reg[10] [4]), .O(m_axi_rready[4])); - (* SOFT_HLUTNM = "soft_lutpair42" *) + (* SOFT_HLUTNM = "soft_lutpair56" *) LUT2 #( .INIT(4'h8)) \m_axi_rready[5]_INST_0 - (.I0(Q[5]), - .I1(aa_rready), + (.I0(aa_rready), + .I1(\m_atarget_hot_reg[10] [5]), .O(m_axi_rready[5])); - (* SOFT_HLUTNM = "soft_lutpair43" *) + (* SOFT_HLUTNM = "soft_lutpair56" *) LUT2 #( .INIT(4'h8)) \m_axi_rready[6]_INST_0 - (.I0(Q[6]), - .I1(aa_rready), + (.I0(aa_rready), + .I1(\m_atarget_hot_reg[10] [6]), .O(m_axi_rready[6])); - (* SOFT_HLUTNM = "soft_lutpair43" *) + (* SOFT_HLUTNM = "soft_lutpair55" *) LUT2 #( .INIT(4'h8)) \m_axi_rready[7]_INST_0 - (.I0(Q[7]), - .I1(aa_rready), + (.I0(aa_rready), + .I1(\m_atarget_hot_reg[10] [7]), .O(m_axi_rready[7])); + (* SOFT_HLUTNM = "soft_lutpair55" *) LUT2 #( .INIT(4'h8)) \m_axi_rready[8]_INST_0 - (.I0(Q[8]), - .I1(aa_rready), + (.I0(aa_rready), + .I1(\m_atarget_hot_reg[10] [8]), .O(m_axi_rready[8])); - LUT5 #( - .INIT(32'h5757FF00)) + (* SOFT_HLUTNM = "soft_lutpair53" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_rready[9]_INST_0 + (.I0(aa_rready), + .I1(\m_atarget_hot_reg[10] [9]), + .O(m_axi_rready[9])); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT4 #( + .INIT(16'h7F70)) \m_payload_i[0]_i_1 - (.I0(m_atarget_enc[3]), - .I1(m_atarget_enc[2]), - .I2(m_atarget_enc[1]), + (.I0(m_atarget_enc[2]), + .I1(m_atarget_enc[3]), + .I2(aa_rready), .I3(\skid_buffer_reg_n_0_[0] ), - .I4(aa_rready), .O(skid_buffer[0])); - (* SOFT_HLUTNM = "soft_lutpair32" *) + (* SOFT_HLUTNM = "soft_lutpair39" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[10]_i_1 - (.I0(aa_rmesg[10]), - .I1(\skid_buffer_reg_n_0_[10] ), - .I2(aa_rready), + (.I0(\skid_buffer[10]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[10] ), .O(skid_buffer[10])); - (* SOFT_HLUTNM = "soft_lutpair33" *) + (* SOFT_HLUTNM = "soft_lutpair38" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[11]_i_1 - (.I0(aa_rmesg[11]), - .I1(\skid_buffer_reg_n_0_[11] ), - .I2(aa_rready), + (.I0(\skid_buffer[11]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[11] ), .O(skid_buffer[11])); - (* SOFT_HLUTNM = "soft_lutpair34" *) + (* SOFT_HLUTNM = "soft_lutpair37" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[12]_i_1 - (.I0(aa_rmesg[12]), - .I1(\skid_buffer_reg_n_0_[12] ), - .I2(aa_rready), + (.I0(\skid_buffer[12]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[12] ), .O(skid_buffer[12])); - (* SOFT_HLUTNM = "soft_lutpair35" *) + (* SOFT_HLUTNM = "soft_lutpair42" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[13]_i_1 - (.I0(aa_rmesg[13]), - .I1(\skid_buffer_reg_n_0_[13] ), - .I2(aa_rready), + (.I0(\skid_buffer[13]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[13] ), .O(skid_buffer[13])); - (* SOFT_HLUTNM = "soft_lutpair36" *) + (* SOFT_HLUTNM = "soft_lutpair43" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[14]_i_1 - (.I0(aa_rmesg[14]), - .I1(\skid_buffer_reg_n_0_[14] ), - .I2(aa_rready), + (.I0(\skid_buffer[14]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[14] ), .O(skid_buffer[14])); - (* SOFT_HLUTNM = "soft_lutpair37" *) + (* SOFT_HLUTNM = "soft_lutpair44" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[15]_i_1 - (.I0(aa_rmesg[15]), - .I1(\skid_buffer_reg_n_0_[15] ), - .I2(aa_rready), + (.I0(\skid_buffer[15]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[15] ), .O(skid_buffer[15])); - (* SOFT_HLUTNM = "soft_lutpair38" *) + (* SOFT_HLUTNM = "soft_lutpair45" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[16]_i_1 - (.I0(aa_rmesg[16]), - .I1(\skid_buffer_reg_n_0_[16] ), - .I2(aa_rready), + (.I0(\skid_buffer[16]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[16] ), .O(skid_buffer[16])); - (* SOFT_HLUTNM = "soft_lutpair38" *) + (* SOFT_HLUTNM = "soft_lutpair46" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[17]_i_1 - (.I0(aa_rmesg[17]), - .I1(\skid_buffer_reg_n_0_[17] ), - .I2(aa_rready), + (.I0(\skid_buffer[17]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[17] ), .O(skid_buffer[17])); - (* SOFT_HLUTNM = "soft_lutpair37" *) + (* SOFT_HLUTNM = "soft_lutpair47" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[18]_i_1 - (.I0(aa_rmesg[18]), - .I1(\skid_buffer_reg_n_0_[18] ), - .I2(aa_rready), + (.I0(\skid_buffer[18]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[18] ), .O(skid_buffer[18])); - (* SOFT_HLUTNM = "soft_lutpair36" *) + (* SOFT_HLUTNM = "soft_lutpair48" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[19]_i_1 - (.I0(aa_rmesg[19]), - .I1(\skid_buffer_reg_n_0_[19] ), - .I2(aa_rready), + (.I0(\skid_buffer[19]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[19] ), .O(skid_buffer[19])); - (* SOFT_HLUTNM = "soft_lutpair23" *) - LUT3 #( - .INIT(8'hAC)) + LUT6 #( + .INIT(64'hFFFFFFFFFFFF00A8)) \m_payload_i[1]_i_1 - (.I0(aa_rmesg[1]), - .I1(\skid_buffer_reg_n_0_[1] ), - .I2(aa_rready), + (.I0(m_axi_rresp[6]), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[1] ), + .I3(\m_payload_i[1]_i_2_n_0 ), + .I4(\m_payload_i[1]_i_3_n_0 ), + .I5(\m_payload_i[1]_i_4_n_0 ), .O(skid_buffer[1])); - (* SOFT_HLUTNM = "soft_lutpair35" *) + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT4 #( + .INIT(16'hFFF7)) + \m_payload_i[1]_i_2 + (.I0(m_atarget_enc[1]), + .I1(m_atarget_enc[0]), + .I2(m_atarget_enc[3]), + .I3(m_atarget_enc[2]), + .O(\m_payload_i[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'h4F4F4F0044444400)) + \m_payload_i[1]_i_3 + (.I0(\m_payload_i_reg[2]_0 ), + .I1(m_axi_rresp[12]), + .I2(\m_payload_i_reg[1]_0 ), + .I3(\skid_buffer_reg_n_0_[1] ), + .I4(aa_rready), + .I5(m_axi_rresp[0]), + .O(\m_payload_i[1]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFF4FFF4FFF40000)) + \m_payload_i[1]_i_4 + (.I0(\m_payload_i[1]_i_5_n_0 ), + .I1(m_axi_rresp[20]), + .I2(\m_payload_i[1]_i_6_n_0 ), + .I3(\m_payload_i[1]_i_7_n_0 ), + .I4(aa_rready), + .I5(\skid_buffer_reg_n_0_[1] ), + .O(\m_payload_i[1]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT4 #( + .INIT(16'hFFDF)) + \m_payload_i[1]_i_5 + (.I0(m_atarget_enc[1]), + .I1(m_atarget_enc[0]), + .I2(m_atarget_enc[3]), + .I3(m_atarget_enc[2]), + .O(\m_payload_i[1]_i_5_n_0 )); + LUT5 #( + .INIT(32'hAEAEFFAE)) + \m_payload_i[1]_i_6 + (.I0(\m_payload_i[1]_i_8_n_0 ), + .I1(m_axi_rresp[14]), + .I2(\m_payload_i_reg[2]_1 ), + .I3(m_axi_rresp[16]), + .I4(\skid_buffer_reg[9]_0 ), + .O(\m_payload_i[1]_i_6_n_0 )); + LUT5 #( + .INIT(32'hFFFF22F2)) + \m_payload_i[1]_i_7 + (.I0(m_axi_rresp[18]), + .I1(\skid_buffer_reg[30]_0 ), + .I2(m_axi_rresp[8]), + .I3(\skid_buffer[32]_i_6_n_0 ), + .I4(\m_payload_i[1]_i_9_n_0 ), + .O(\m_payload_i[1]_i_7_n_0 )); + LUT6 #( + .INIT(64'h0020C000FFFFFFFF)) + \m_payload_i[1]_i_8 + (.I0(m_axi_rresp[10]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[0]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(aa_rready), + .O(\m_payload_i[1]_i_8_n_0 )); + LUT6 #( + .INIT(64'h0000002C00000020)) + \m_payload_i[1]_i_9 + (.I0(m_axi_rresp[4]), + .I1(m_atarget_enc[0]), + .I2(m_atarget_enc[1]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rresp[2]), + .O(\m_payload_i[1]_i_9_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair49" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[20]_i_1 - (.I0(aa_rmesg[20]), - .I1(\skid_buffer_reg_n_0_[20] ), - .I2(aa_rready), + (.I0(\skid_buffer[20]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[20] ), .O(skid_buffer[20])); - (* SOFT_HLUTNM = "soft_lutpair34" *) + (* SOFT_HLUTNM = "soft_lutpair50" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[21]_i_1 - (.I0(aa_rmesg[21]), - .I1(\skid_buffer_reg_n_0_[21] ), - .I2(aa_rready), + (.I0(\skid_buffer[21]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[21] ), .O(skid_buffer[21])); - (* SOFT_HLUTNM = "soft_lutpair33" *) + (* SOFT_HLUTNM = "soft_lutpair51" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[22]_i_1 - (.I0(aa_rmesg[22]), - .I1(\skid_buffer_reg_n_0_[22] ), - .I2(aa_rready), + (.I0(\skid_buffer[22]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[22] ), .O(skid_buffer[22])); - (* SOFT_HLUTNM = "soft_lutpair32" *) + (* SOFT_HLUTNM = "soft_lutpair52" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[23]_i_1 - (.I0(aa_rmesg[23]), - .I1(\skid_buffer_reg_n_0_[23] ), - .I2(aa_rready), + (.I0(\skid_buffer[23]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[23] ), .O(skid_buffer[23])); - (* SOFT_HLUTNM = "soft_lutpair31" *) + (* SOFT_HLUTNM = "soft_lutpair53" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[24]_i_1 - (.I0(aa_rmesg[24]), - .I1(\skid_buffer_reg_n_0_[24] ), - .I2(aa_rready), + (.I0(\skid_buffer[24]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[24] ), .O(skid_buffer[24])); - (* SOFT_HLUTNM = "soft_lutpair30" *) + (* SOFT_HLUTNM = "soft_lutpair52" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[25]_i_1 - (.I0(aa_rmesg[25]), - .I1(\skid_buffer_reg_n_0_[25] ), - .I2(aa_rready), + (.I0(\skid_buffer[25]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[25] ), .O(skid_buffer[25])); - (* SOFT_HLUTNM = "soft_lutpair29" *) + (* SOFT_HLUTNM = "soft_lutpair51" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[26]_i_1 - (.I0(aa_rmesg[26]), - .I1(\skid_buffer_reg_n_0_[26] ), - .I2(aa_rready), + (.I0(\skid_buffer[26]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[26] ), .O(skid_buffer[26])); - (* SOFT_HLUTNM = "soft_lutpair28" *) + (* SOFT_HLUTNM = "soft_lutpair50" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[27]_i_1 - (.I0(aa_rmesg[27]), - .I1(\skid_buffer_reg_n_0_[27] ), - .I2(aa_rready), + (.I0(\skid_buffer[27]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[27] ), .O(skid_buffer[27])); - (* SOFT_HLUTNM = "soft_lutpair27" *) + (* SOFT_HLUTNM = "soft_lutpair49" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[28]_i_1 - (.I0(aa_rmesg[28]), - .I1(\skid_buffer_reg_n_0_[28] ), - .I2(aa_rready), + (.I0(\skid_buffer[28]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[28] ), .O(skid_buffer[28])); - (* SOFT_HLUTNM = "soft_lutpair26" *) + (* SOFT_HLUTNM = "soft_lutpair48" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[29]_i_1 - (.I0(aa_rmesg[29]), - .I1(\skid_buffer_reg_n_0_[29] ), - .I2(aa_rready), + (.I0(\skid_buffer[29]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[29] ), .O(skid_buffer[29])); - (* SOFT_HLUTNM = "soft_lutpair24" *) + (* SOFT_HLUTNM = "soft_lutpair37" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'h32)) \m_payload_i[2]_i_1 - (.I0(aa_rmesg[2]), - .I1(\skid_buffer_reg_n_0_[2] ), - .I2(aa_rready), + (.I0(aa_rready), + .I1(\m_payload_i[2]_i_2_n_0 ), + .I2(\skid_buffer_reg_n_0_[2] ), .O(skid_buffer[2])); - (* SOFT_HLUTNM = "soft_lutpair39" *) + LUT6 #( + .INIT(64'h00000000B0BB0000)) + \m_payload_i[2]_i_2 + (.I0(\m_payload_i_reg[2]_0 ), + .I1(m_axi_rresp[13]), + .I2(\m_payload_i_reg[2]_1 ), + .I3(m_axi_rresp[15]), + .I4(\m_payload_i[2]_i_3_n_0 ), + .I5(\m_payload_i[2]_i_4_n_0 ), + .O(\m_payload_i[2]_i_2_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAAA0AAA2AAA)) + \m_payload_i[2]_i_3 + (.I0(aa_rready), + .I1(m_axi_rresp[7]), + .I2(m_atarget_enc[1]), + .I3(m_atarget_enc[0]), + .I4(m_atarget_enc[3]), + .I5(m_atarget_enc[2]), + .O(\m_payload_i[2]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFBAFFBABA)) + \m_payload_i[2]_i_4 + (.I0(\m_payload_i[2]_i_5_n_0 ), + .I1(\m_payload_i_reg[1]_0 ), + .I2(m_axi_rresp[1]), + .I3(\skid_buffer_reg[30]_0 ), + .I4(m_axi_rresp[19]), + .I5(\m_payload_i[2]_i_6_n_0 ), + .O(\m_payload_i[2]_i_4_n_0 )); + LUT6 #( + .INIT(64'h00000C0800000008)) + \m_payload_i[2]_i_5 + (.I0(m_axi_rresp[9]), + .I1(m_atarget_enc[2]), + .I2(m_atarget_enc[3]), + .I3(m_atarget_enc[0]), + .I4(m_atarget_enc[1]), + .I5(m_axi_rresp[11]), + .O(\m_payload_i[2]_i_5_n_0 )); + LUT5 #( + .INIT(32'hFFFF22F2)) + \m_payload_i[2]_i_6 + (.I0(m_axi_rresp[21]), + .I1(\m_payload_i[1]_i_5_n_0 ), + .I2(m_axi_rresp[17]), + .I3(\skid_buffer_reg[9]_0 ), + .I4(\m_payload_i[2]_i_7_n_0 ), + .O(\m_payload_i[2]_i_6_n_0 )); + LUT6 #( + .INIT(64'h0000002C00000020)) + \m_payload_i[2]_i_7 + (.I0(m_axi_rresp[5]), + .I1(m_atarget_enc[0]), + .I2(m_atarget_enc[1]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rresp[3]), + .O(\m_payload_i[2]_i_7_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair47" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[30]_i_1 - (.I0(aa_rmesg[30]), - .I1(\skid_buffer_reg_n_0_[30] ), - .I2(aa_rready), + (.I0(\skid_buffer[30]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[30] ), .O(skid_buffer[30])); - (* SOFT_HLUTNM = "soft_lutpair25" *) + (* SOFT_HLUTNM = "soft_lutpair46" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[31]_i_1 - (.I0(aa_rmesg[31]), - .I1(\skid_buffer_reg_n_0_[31] ), - .I2(aa_rready), + (.I0(\skid_buffer[31]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[31] ), .O(skid_buffer[31])); - (* SOFT_HLUTNM = "soft_lutpair39" *) + (* SOFT_HLUTNM = "soft_lutpair45" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[32]_i_1 - (.I0(aa_rmesg[32]), - .I1(\skid_buffer_reg_n_0_[32] ), - .I2(aa_rready), + (.I0(\skid_buffer[32]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[32] ), .O(skid_buffer[32])); - (* SOFT_HLUTNM = "soft_lutpair24" *) + (* SOFT_HLUTNM = "soft_lutpair44" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[33]_i_1 - (.I0(aa_rmesg[33]), - .I1(\skid_buffer_reg_n_0_[33] ), - .I2(aa_rready), + (.I0(\skid_buffer[33]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[33] ), .O(skid_buffer[33])); - (* SOFT_HLUTNM = "soft_lutpair23" *) + (* SOFT_HLUTNM = "soft_lutpair43" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[34]_i_2 - (.I0(aa_rmesg[34]), - .I1(\skid_buffer_reg_n_0_[34] ), - .I2(aa_rready), + (.I0(\skid_buffer[34]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[34] ), .O(skid_buffer[34])); - (* SOFT_HLUTNM = "soft_lutpair25" *) + (* SOFT_HLUTNM = "soft_lutpair38" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[3]_i_1 - (.I0(aa_rmesg[3]), - .I1(\skid_buffer_reg_n_0_[3] ), - .I2(aa_rready), + (.I0(\skid_buffer[3]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[3] ), .O(skid_buffer[3])); - (* SOFT_HLUTNM = "soft_lutpair26" *) + (* SOFT_HLUTNM = "soft_lutpair39" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[4]_i_1 - (.I0(aa_rmesg[4]), - .I1(\skid_buffer_reg_n_0_[4] ), - .I2(aa_rready), + (.I0(\skid_buffer[4]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[4] ), .O(skid_buffer[4])); - (* SOFT_HLUTNM = "soft_lutpair27" *) + (* SOFT_HLUTNM = "soft_lutpair40" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[5]_i_1 - (.I0(aa_rmesg[5]), - .I1(\skid_buffer_reg_n_0_[5] ), - .I2(aa_rready), + (.I0(\skid_buffer[5]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[5] ), .O(skid_buffer[5])); - (* SOFT_HLUTNM = "soft_lutpair28" *) + (* SOFT_HLUTNM = "soft_lutpair41" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[6]_i_1 - (.I0(aa_rmesg[6]), - .I1(\skid_buffer_reg_n_0_[6] ), - .I2(aa_rready), + (.I0(\skid_buffer[6]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[6] ), .O(skid_buffer[6])); - (* SOFT_HLUTNM = "soft_lutpair29" *) + (* SOFT_HLUTNM = "soft_lutpair42" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[7]_i_1 - (.I0(aa_rmesg[7]), - .I1(\skid_buffer_reg_n_0_[7] ), - .I2(aa_rready), + (.I0(\skid_buffer[7]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[7] ), .O(skid_buffer[7])); - (* SOFT_HLUTNM = "soft_lutpair30" *) + (* SOFT_HLUTNM = "soft_lutpair41" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[8]_i_1 - (.I0(aa_rmesg[8]), - .I1(\skid_buffer_reg_n_0_[8] ), - .I2(aa_rready), + (.I0(\skid_buffer[8]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[8] ), .O(skid_buffer[8])); - (* SOFT_HLUTNM = "soft_lutpair31" *) + (* SOFT_HLUTNM = "soft_lutpair40" *) LUT3 #( - .INIT(8'hAC)) + .INIT(8'hB8)) \m_payload_i[9]_i_1 - (.I0(aa_rmesg[9]), - .I1(\skid_buffer_reg_n_0_[9] ), - .I2(aa_rready), + (.I0(\skid_buffer[9]_i_1_n_0 ), + .I1(aa_rready), + .I2(\skid_buffer_reg_n_0_[9] ), .O(skid_buffer[9])); FDRE \m_payload_i_reg[0] (.C(aclk), .CE(E), .D(skid_buffer[0]), - .Q(\m_payload_i_reg_n_0_[0] ), + .Q(Q[0]), .R(1'b0)); FDRE \m_payload_i_reg[10] (.C(aclk), .CE(E), .D(skid_buffer[10]), - .Q(\s_axi_rdata[31] [9]), + .Q(Q[10]), .R(1'b0)); FDRE \m_payload_i_reg[11] (.C(aclk), .CE(E), .D(skid_buffer[11]), - .Q(\s_axi_rdata[31] [10]), + .Q(Q[11]), .R(1'b0)); FDRE \m_payload_i_reg[12] (.C(aclk), .CE(E), .D(skid_buffer[12]), - .Q(\s_axi_rdata[31] [11]), + .Q(Q[12]), .R(1'b0)); FDRE \m_payload_i_reg[13] (.C(aclk), .CE(E), .D(skid_buffer[13]), - .Q(\s_axi_rdata[31] [12]), + .Q(Q[13]), .R(1'b0)); FDRE \m_payload_i_reg[14] (.C(aclk), .CE(E), .D(skid_buffer[14]), - .Q(\s_axi_rdata[31] [13]), + .Q(Q[14]), .R(1'b0)); FDRE \m_payload_i_reg[15] (.C(aclk), .CE(E), .D(skid_buffer[15]), - .Q(\s_axi_rdata[31] [14]), + .Q(Q[15]), .R(1'b0)); FDRE \m_payload_i_reg[16] (.C(aclk), .CE(E), .D(skid_buffer[16]), - .Q(\s_axi_rdata[31] [15]), + .Q(Q[16]), .R(1'b0)); FDRE \m_payload_i_reg[17] (.C(aclk), .CE(E), .D(skid_buffer[17]), - .Q(\s_axi_rdata[31] [16]), + .Q(Q[17]), .R(1'b0)); FDRE \m_payload_i_reg[18] (.C(aclk), .CE(E), .D(skid_buffer[18]), - .Q(\s_axi_rdata[31] [17]), + .Q(Q[18]), .R(1'b0)); FDRE \m_payload_i_reg[19] (.C(aclk), .CE(E), .D(skid_buffer[19]), - .Q(\s_axi_rdata[31] [18]), + .Q(Q[19]), .R(1'b0)); FDRE \m_payload_i_reg[1] (.C(aclk), .CE(E), .D(skid_buffer[1]), - .Q(\s_axi_rdata[31] [0]), + .Q(Q[1]), .R(1'b0)); FDRE \m_payload_i_reg[20] (.C(aclk), .CE(E), .D(skid_buffer[20]), - .Q(\s_axi_rdata[31] [19]), + .Q(Q[20]), .R(1'b0)); FDRE \m_payload_i_reg[21] (.C(aclk), .CE(E), .D(skid_buffer[21]), - .Q(\s_axi_rdata[31] [20]), + .Q(Q[21]), .R(1'b0)); FDRE \m_payload_i_reg[22] (.C(aclk), .CE(E), .D(skid_buffer[22]), - .Q(\s_axi_rdata[31] [21]), + .Q(Q[22]), .R(1'b0)); FDRE \m_payload_i_reg[23] (.C(aclk), .CE(E), .D(skid_buffer[23]), - .Q(\s_axi_rdata[31] [22]), + .Q(Q[23]), .R(1'b0)); FDRE \m_payload_i_reg[24] (.C(aclk), .CE(E), .D(skid_buffer[24]), - .Q(\s_axi_rdata[31] [23]), + .Q(Q[24]), .R(1'b0)); FDRE \m_payload_i_reg[25] (.C(aclk), .CE(E), .D(skid_buffer[25]), - .Q(\s_axi_rdata[31] [24]), + .Q(Q[25]), .R(1'b0)); FDRE \m_payload_i_reg[26] (.C(aclk), .CE(E), .D(skid_buffer[26]), - .Q(\s_axi_rdata[31] [25]), + .Q(Q[26]), .R(1'b0)); FDRE \m_payload_i_reg[27] (.C(aclk), .CE(E), .D(skid_buffer[27]), - .Q(\s_axi_rdata[31] [26]), + .Q(Q[27]), .R(1'b0)); FDRE \m_payload_i_reg[28] (.C(aclk), .CE(E), .D(skid_buffer[28]), - .Q(\s_axi_rdata[31] [27]), + .Q(Q[28]), .R(1'b0)); FDRE \m_payload_i_reg[29] (.C(aclk), .CE(E), .D(skid_buffer[29]), - .Q(\s_axi_rdata[31] [28]), + .Q(Q[29]), .R(1'b0)); FDRE \m_payload_i_reg[2] (.C(aclk), .CE(E), .D(skid_buffer[2]), - .Q(\s_axi_rdata[31] [1]), + .Q(Q[2]), .R(1'b0)); FDRE \m_payload_i_reg[30] (.C(aclk), .CE(E), .D(skid_buffer[30]), - .Q(\s_axi_rdata[31] [29]), + .Q(Q[30]), .R(1'b0)); FDRE \m_payload_i_reg[31] (.C(aclk), .CE(E), .D(skid_buffer[31]), - .Q(\s_axi_rdata[31] [30]), + .Q(Q[31]), .R(1'b0)); FDRE \m_payload_i_reg[32] (.C(aclk), .CE(E), .D(skid_buffer[32]), - .Q(\s_axi_rdata[31] [31]), + .Q(Q[32]), .R(1'b0)); FDRE \m_payload_i_reg[33] (.C(aclk), .CE(E), .D(skid_buffer[33]), - .Q(\s_axi_rdata[31] [32]), + .Q(Q[33]), .R(1'b0)); FDRE \m_payload_i_reg[34] (.C(aclk), .CE(E), .D(skid_buffer[34]), - .Q(\s_axi_rdata[31] [33]), + .Q(Q[34]), .R(1'b0)); FDRE \m_payload_i_reg[3] (.C(aclk), .CE(E), .D(skid_buffer[3]), - .Q(\s_axi_rdata[31] [2]), + .Q(Q[3]), .R(1'b0)); FDRE \m_payload_i_reg[4] (.C(aclk), .CE(E), .D(skid_buffer[4]), - .Q(\s_axi_rdata[31] [3]), + .Q(Q[4]), .R(1'b0)); FDRE \m_payload_i_reg[5] (.C(aclk), .CE(E), .D(skid_buffer[5]), - .Q(\s_axi_rdata[31] [4]), + .Q(Q[5]), .R(1'b0)); FDRE \m_payload_i_reg[6] (.C(aclk), .CE(E), .D(skid_buffer[6]), - .Q(\s_axi_rdata[31] [5]), + .Q(Q[6]), .R(1'b0)); FDRE \m_payload_i_reg[7] (.C(aclk), .CE(E), .D(skid_buffer[7]), - .Q(\s_axi_rdata[31] [6]), + .Q(Q[7]), .R(1'b0)); FDRE \m_payload_i_reg[8] (.C(aclk), .CE(E), .D(skid_buffer[8]), - .Q(\s_axi_rdata[31] [7]), + .Q(Q[8]), .R(1'b0)); FDRE \m_payload_i_reg[9] (.C(aclk), .CE(E), .D(skid_buffer[9]), - .Q(\s_axi_rdata[31] [8]), + .Q(Q[9]), .R(1'b0)); - LUT6 #( - .INIT(64'h0800000000000000)) - \m_ready_d[1]_i_3 - (.I0(\m_payload_i_reg_n_0_[0] ), - .I1(s_axi_rready), - .I2(m_ready_d), - .I3(aa_grant_rnw), - .I4(m_valid_i), - .I5(sr_rvalid), - .O(\m_ready_d_reg[1] )); - (* SOFT_HLUTNM = "soft_lutpair22" *) - LUT4 #( - .INIT(16'h8AAA)) + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT3 #( + .INIT(8'hA2)) m_valid_i_i_1 (.I0(\aresetn_d_reg_n_0_[1] ), - .I1(aa_rvalid), - .I2(E), - .I3(aa_rready), + .I1(E), + .I2(s_ready_i_reg_4), .O(m_valid_i_i_1_n_0)); + LUT6 #( + .INIT(64'h003300B8000000B8)) + m_valid_i_i_4 + (.I0(m_axi_rvalid[4]), + .I1(m_atarget_enc[2]), + .I2(m_axi_rvalid[1]), + .I3(\m_atarget_enc_reg[1] ), + .I4(m_atarget_enc[3]), + .I5(m_axi_rvalid[7]), + .O(s_ready_i_reg_1)); + LUT6 #( + .INIT(64'hFCDCFCDFFFDCFFDF)) + m_valid_i_i_5 + (.I0(m_axi_rvalid[8]), + .I1(\m_atarget_enc_reg[0] ), + .I2(m_atarget_enc[3]), + .I3(m_atarget_enc[2]), + .I4(m_axi_rvalid[2]), + .I5(m_axi_rvalid[5]), + .O(s_ready_i_reg_0)); + LUT6 #( + .INIT(64'hFCDCFCDFFFDCFFDF)) + m_valid_i_i_6 + (.I0(m_axi_rvalid[6]), + .I1(s_ready_i_reg_3), + .I2(m_atarget_enc[3]), + .I3(m_atarget_enc[2]), + .I4(m_axi_rvalid[0]), + .I5(m_axi_rvalid[3]), + .O(s_ready_i_reg_2)); FDRE m_valid_i_reg (.C(aclk), .CE(1'b1), .D(m_valid_i_i_1_n_0), .Q(sr_rvalid), .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT4 #( + .INIT(16'hFFDF)) + \s_axi_bresp[0]_INST_0_i_1 + (.I0(m_atarget_enc[0]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[3]), + .I3(m_atarget_enc[2]), + .O(\skid_buffer_reg[30]_0 )); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT4 #( + .INIT(16'hDFFF)) + \s_axi_bresp[0]_INST_0_i_2 + (.I0(m_atarget_enc[2]), + .I1(m_atarget_enc[3]), + .I2(m_atarget_enc[1]), + .I3(m_atarget_enc[0]), + .O(\m_payload_i_reg[2]_1 )); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT4 #( + .INIT(16'hFFDF)) + \s_axi_bresp[0]_INST_0_i_8 + (.I0(m_atarget_enc[2]), + .I1(m_atarget_enc[3]), + .I2(m_atarget_enc[1]), + .I3(m_atarget_enc[0]), + .O(\m_payload_i_reg[2]_0 )); + (* SOFT_HLUTNM = "soft_lutpair31" *) LUT4 #( - .INIT(16'h0010)) + .INIT(16'hFFFE)) \s_axi_bresp[1]_INST_0_i_1 - (.I0(m_atarget_enc[3]), - .I1(m_atarget_enc[2]), - .I2(m_atarget_enc[0]), - .I3(m_atarget_enc[1]), - .O(\skid_buffer_reg[1]_0 )); + (.I0(m_atarget_enc[1]), + .I1(m_atarget_enc[0]), + .I2(m_atarget_enc[3]), + .I3(m_atarget_enc[2]), + .O(\m_payload_i_reg[1]_0 )); + (* SOFT_HLUTNM = "soft_lutpair31" *) LUT4 #( - .INIT(16'h0010)) + .INIT(16'hFFEF)) \s_axi_bresp[1]_INST_0_i_2 - (.I0(m_atarget_enc[3]), - .I1(m_atarget_enc[2]), - .I2(m_atarget_enc[1]), - .I3(m_atarget_enc[0]), - .O(\skid_buffer_reg[1]_1 )); - LUT4 #( - .INIT(16'h0010)) - \s_axi_bresp[1]_INST_0_i_6 - (.I0(m_atarget_enc[3]), + (.I0(m_atarget_enc[1]), .I1(m_atarget_enc[0]), - .I2(m_atarget_enc[2]), - .I3(m_atarget_enc[1]), - .O(\skid_buffer_reg[1]_2 )); - LUT4 #( - .INIT(16'h1000)) - \s_axi_bresp[1]_INST_0_i_7 - (.I0(m_atarget_enc[3]), - .I1(m_atarget_enc[2]), - .I2(m_atarget_enc[0]), - .I3(m_atarget_enc[1]), - .O(\skid_buffer_reg[1]_3 )); - (* SOFT_HLUTNM = "soft_lutpair22" *) - LUT4 #( - .INIT(16'hAA08)) + .I2(m_atarget_enc[3]), + .I3(m_atarget_enc[2]), + .O(\skid_buffer_reg[9]_0 )); + (* SOFT_HLUTNM = "soft_lutpair54" *) + LUT2 #( + .INIT(4'h7)) + \s_axi_wready[0]_INST_0_i_10 + (.I0(m_atarget_enc[0]), + .I1(m_atarget_enc[1]), + .O(\m_ready_d_reg[2] )); + (* SOFT_HLUTNM = "soft_lutpair54" *) + LUT2 #( + .INIT(4'hE)) + \s_axi_wready[0]_INST_0_i_9 + (.I0(m_atarget_enc[0]), + .I1(m_atarget_enc[1]), + .O(s_ready_i_reg_3)); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT3 #( + .INIT(8'hA2)) s_ready_i_i_1 (.I0(\aresetn_d_reg_n_0_[0] ), - .I1(aa_rready), - .I2(aa_rvalid), - .I3(E), + .I1(s_ready_i_reg_4), + .I2(E), .O(s_ready_i_i_1_n_0)); FDRE s_ready_i_reg (.C(aclk), @@ -4860,1591 +5531,1861 @@ module Arty_Z7_20_xbar_0_axi_register_slice_v2_1_11_axic_register_slice .D(s_ready_i_i_1_n_0), .Q(aa_rready), .R(1'b0)); - LUT3 #( - .INIT(8'h57)) + LUT2 #( + .INIT(4'h7)) \skid_buffer[0]_i_1 - (.I0(m_atarget_enc[3]), - .I1(m_atarget_enc[2]), - .I2(m_atarget_enc[1]), - .O(aa_rmesg[0])); + (.I0(m_atarget_enc[2]), + .I1(m_atarget_enc[3]), + .O(\skid_buffer[0]_i_1_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'hFFFEFFFEFFFFFFFE)) \skid_buffer[10]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), - .I1(m_axi_rdata[39]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[71]), - .I4(\skid_buffer[10]_i_2_n_0 ), - .I5(\skid_buffer[10]_i_3_n_0 ), - .O(aa_rmesg[10])); - LUT6 #( - .INIT(64'hFFFFF888F888F888)) + (.I0(\skid_buffer[10]_i_2_n_0 ), + .I1(\skid_buffer[10]_i_3_n_0 ), + .I2(\skid_buffer[10]_i_4_n_0 ), + .I3(\skid_buffer[10]_i_5_n_0 ), + .I4(m_axi_rdata[71]), + .I5(\skid_buffer[31]_i_2_n_0 ), + .O(\skid_buffer[10]_i_1_n_0 )); + LUT6 #( + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[10]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[263]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[231]), - .I4(m_axi_rdata[7]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_axi_rdata[39]), + .I1(\skid_buffer[34]_i_2_n_0 ), + .I2(m_axi_rdata[103]), + .I3(\m_payload_i[1]_i_2_n_0 ), + .I4(\skid_buffer[32]_i_6_n_0 ), + .I5(m_axi_rdata[135]), .O(\skid_buffer[10]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'h00200C0000200000)) \skid_buffer[10]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[135]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[103]), - .I4(\skid_buffer[10]_i_4_n_0 ), + (.I0(m_axi_rdata[199]), + .I1(m_atarget_enc[0]), + .I2(m_atarget_enc[1]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[295]), .O(\skid_buffer[10]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h08000C0008000000)) \skid_buffer[10]_i_4 - (.I0(m_axi_rdata[167]), - .I1(m_axi_rdata[199]), + (.I0(m_axi_rdata[231]), + .I1(m_atarget_enc[2]), .I2(m_atarget_enc[3]), .I3(m_atarget_enc[0]), .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + .I5(m_axi_rdata[167]), .O(\skid_buffer[10]_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'h22F2FFFF22F222F2)) + \skid_buffer[10]_i_5 + (.I0(m_axi_rdata[327]), + .I1(\m_payload_i[1]_i_5_n_0 ), + .I2(m_axi_rdata[7]), + .I3(\m_payload_i_reg[1]_0 ), + .I4(\skid_buffer_reg[9]_0 ), + .I5(m_axi_rdata[263]), + .O(\skid_buffer[10]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFEFFFEFFFFFFFE)) \skid_buffer[11]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), - .I1(m_axi_rdata[40]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[72]), - .I4(\skid_buffer[11]_i_2_n_0 ), - .I5(\skid_buffer[11]_i_3_n_0 ), - .O(aa_rmesg[11])); - LUT6 #( - .INIT(64'hFFFFF888F888F888)) + (.I0(\skid_buffer[11]_i_2_n_0 ), + .I1(\skid_buffer[11]_i_3_n_0 ), + .I2(\skid_buffer[11]_i_4_n_0 ), + .I3(\skid_buffer[11]_i_5_n_0 ), + .I4(m_axi_rdata[72]), + .I5(\skid_buffer[31]_i_2_n_0 ), + .O(\skid_buffer[11]_i_1_n_0 )); + LUT6 #( + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[11]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[264]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[232]), - .I4(m_axi_rdata[8]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_axi_rdata[40]), + .I1(\skid_buffer[34]_i_2_n_0 ), + .I2(m_axi_rdata[136]), + .I3(\skid_buffer[32]_i_6_n_0 ), + .I4(\m_payload_i[1]_i_2_n_0 ), + .I5(m_axi_rdata[104]), .O(\skid_buffer[11]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'h00080C0000080000)) \skid_buffer[11]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[136]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[104]), - .I4(\skid_buffer[11]_i_4_n_0 ), + (.I0(m_axi_rdata[200]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[0]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[328]), .O(\skid_buffer[11]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h08000C0008000000)) \skid_buffer[11]_i_4 - (.I0(m_axi_rdata[168]), - .I1(m_axi_rdata[200]), + (.I0(m_axi_rdata[232]), + .I1(m_atarget_enc[2]), .I2(m_atarget_enc[3]), .I3(m_atarget_enc[0]), .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + .I5(m_axi_rdata[168]), .O(\skid_buffer[11]_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'h22F2FFFF22F222F2)) + \skid_buffer[11]_i_5 + (.I0(m_axi_rdata[296]), + .I1(\skid_buffer_reg[30]_0 ), + .I2(m_axi_rdata[8]), + .I3(\m_payload_i_reg[1]_0 ), + .I4(\skid_buffer_reg[9]_0 ), + .I5(m_axi_rdata[264]), + .O(\skid_buffer[11]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF4F44)) \skid_buffer[12]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), + (.I0(\skid_buffer[34]_i_2_n_0 ), .I1(m_axi_rdata[41]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[73]), + .I2(\skid_buffer[32]_i_6_n_0 ), + .I3(m_axi_rdata[137]), .I4(\skid_buffer[12]_i_2_n_0 ), .I5(\skid_buffer[12]_i_3_n_0 ), - .O(aa_rmesg[12])); + .O(\skid_buffer[12]_i_1_n_0 )); LUT6 #( - .INIT(64'hFFFFF888F888F888)) + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[12]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[265]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[233]), - .I4(m_axi_rdata[9]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_axi_rdata[265]), + .I1(\skid_buffer_reg[9]_0 ), + .I2(m_axi_rdata[201]), + .I3(\m_payload_i_reg[2]_0 ), + .I4(\skid_buffer[31]_i_2_n_0 ), + .I5(m_axi_rdata[73]), .O(\skid_buffer[12]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'hEFEEEFEEFFFFEFEE)) \skid_buffer[12]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[137]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[105]), - .I4(\skid_buffer[12]_i_4_n_0 ), + (.I0(\skid_buffer[12]_i_4_n_0 ), + .I1(\skid_buffer[12]_i_5_n_0 ), + .I2(\skid_buffer_reg[30]_0 ), + .I3(m_axi_rdata[297]), + .I4(m_axi_rdata[233]), + .I5(\m_payload_i_reg[2]_1 ), .O(\skid_buffer[12]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h02000C0002000000)) \skid_buffer[12]_i_4 - (.I0(m_axi_rdata[169]), - .I1(m_axi_rdata[201]), + (.I0(m_axi_rdata[105]), + .I1(m_atarget_enc[2]), .I2(m_atarget_enc[3]), .I3(m_atarget_enc[0]), .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + .I5(m_axi_rdata[169]), .O(\skid_buffer[12]_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'h00000C0200000002)) + \skid_buffer[12]_i_5 + (.I0(m_axi_rdata[9]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[0]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[329]), + .O(\skid_buffer[12]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF4F44)) \skid_buffer[13]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), + (.I0(\skid_buffer[34]_i_2_n_0 ), .I1(m_axi_rdata[42]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[74]), + .I2(\m_payload_i[1]_i_2_n_0 ), + .I3(m_axi_rdata[106]), .I4(\skid_buffer[13]_i_2_n_0 ), .I5(\skid_buffer[13]_i_3_n_0 ), - .O(aa_rmesg[13])); + .O(\skid_buffer[13]_i_1_n_0 )); LUT6 #( - .INIT(64'hFFFFF888F888F888)) + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[13]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[266]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[234]), - .I4(m_axi_rdata[10]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_axi_rdata[170]), + .I1(\skid_buffer[34]_i_5_n_0 ), + .I2(m_axi_rdata[234]), + .I3(\m_payload_i_reg[2]_1 ), + .I4(\skid_buffer[31]_i_2_n_0 ), + .I5(m_axi_rdata[74]), .O(\skid_buffer[13]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'hEFEEEFEEFFFFEFEE)) \skid_buffer[13]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[138]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[106]), - .I4(\skid_buffer[13]_i_4_n_0 ), + (.I0(\skid_buffer[13]_i_4_n_0 ), + .I1(\skid_buffer[13]_i_5_n_0 ), + .I2(\m_payload_i_reg[1]_0 ), + .I3(m_axi_rdata[10]), + .I4(m_axi_rdata[202]), + .I5(\m_payload_i_reg[2]_0 ), .O(\skid_buffer[13]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h0002030000020000)) \skid_buffer[13]_i_4 - (.I0(m_axi_rdata[170]), - .I1(m_axi_rdata[202]), - .I2(m_atarget_enc[3]), - .I3(m_atarget_enc[0]), - .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + (.I0(m_axi_rdata[138]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[0]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[266]), .O(\skid_buffer[13]_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'h00002C0000002000)) + \skid_buffer[13]_i_5 + (.I0(m_axi_rdata[298]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[0]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[330]), + .O(\skid_buffer[13]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF4F44)) \skid_buffer[14]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), + (.I0(\skid_buffer[34]_i_2_n_0 ), .I1(m_axi_rdata[43]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[75]), + .I2(\m_payload_i[1]_i_2_n_0 ), + .I3(m_axi_rdata[107]), .I4(\skid_buffer[14]_i_2_n_0 ), .I5(\skid_buffer[14]_i_3_n_0 ), - .O(aa_rmesg[14])); + .O(\skid_buffer[14]_i_1_n_0 )); LUT6 #( - .INIT(64'hFFFFF888F888F888)) + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[14]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[267]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[235]), - .I4(m_axi_rdata[11]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_axi_rdata[267]), + .I1(\skid_buffer_reg[9]_0 ), + .I2(m_axi_rdata[171]), + .I3(\skid_buffer[34]_i_5_n_0 ), + .I4(\skid_buffer[31]_i_2_n_0 ), + .I5(m_axi_rdata[75]), .O(\skid_buffer[14]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'hEFEEEFEEFFFFEFEE)) \skid_buffer[14]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[139]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[107]), - .I4(\skid_buffer[14]_i_4_n_0 ), + (.I0(\skid_buffer[14]_i_4_n_0 ), + .I1(\skid_buffer[14]_i_5_n_0 ), + .I2(\m_payload_i_reg[1]_0 ), + .I3(m_axi_rdata[11]), + .I4(m_axi_rdata[235]), + .I5(\m_payload_i_reg[2]_1 ), .O(\skid_buffer[14]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h00000C0800000008)) \skid_buffer[14]_i_4 - (.I0(m_axi_rdata[171]), - .I1(m_axi_rdata[203]), + (.I0(m_axi_rdata[139]), + .I1(m_atarget_enc[2]), .I2(m_atarget_enc[3]), - .I3(m_atarget_enc[0]), - .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + .I3(m_atarget_enc[1]), + .I4(m_atarget_enc[0]), + .I5(m_axi_rdata[203]), .O(\skid_buffer[14]_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'h00002C0000002000)) + \skid_buffer[14]_i_5 + (.I0(m_axi_rdata[331]), + .I1(m_atarget_enc[0]), + .I2(m_atarget_enc[1]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[299]), + .O(\skid_buffer[14]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFEFFFEFFFFFFFE)) \skid_buffer[15]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), - .I1(m_axi_rdata[44]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[76]), - .I4(\skid_buffer[15]_i_2_n_0 ), - .I5(\skid_buffer[15]_i_3_n_0 ), - .O(aa_rmesg[15])); - LUT6 #( - .INIT(64'hFFFFF888F888F888)) + (.I0(\skid_buffer[15]_i_2_n_0 ), + .I1(\skid_buffer[15]_i_3_n_0 ), + .I2(\skid_buffer[15]_i_4_n_0 ), + .I3(\skid_buffer[15]_i_5_n_0 ), + .I4(m_axi_rdata[140]), + .I5(\skid_buffer[32]_i_6_n_0 ), + .O(\skid_buffer[15]_i_1_n_0 )); + LUT6 #( + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[15]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[268]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[236]), - .I4(m_axi_rdata[12]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_axi_rdata[108]), + .I1(\m_payload_i[1]_i_2_n_0 ), + .I2(m_axi_rdata[44]), + .I3(\skid_buffer[34]_i_2_n_0 ), + .I4(\skid_buffer[31]_i_2_n_0 ), + .I5(m_axi_rdata[76]), .O(\skid_buffer[15]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'h0020000300200000)) \skid_buffer[15]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[140]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[108]), - .I4(\skid_buffer[15]_i_4_n_0 ), + (.I0(m_axi_rdata[172]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[0]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[12]), .O(\skid_buffer[15]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h00000C2000000020)) \skid_buffer[15]_i_4 - (.I0(m_axi_rdata[172]), - .I1(m_axi_rdata[204]), + (.I0(m_axi_rdata[268]), + .I1(m_atarget_enc[2]), .I2(m_atarget_enc[3]), - .I3(m_atarget_enc[0]), - .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + .I3(m_atarget_enc[1]), + .I4(m_atarget_enc[0]), + .I5(m_axi_rdata[204]), .O(\skid_buffer[15]_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'h22F2FFFF22F222F2)) + \skid_buffer[15]_i_5 + (.I0(m_axi_rdata[300]), + .I1(\skid_buffer_reg[30]_0 ), + .I2(m_axi_rdata[332]), + .I3(\m_payload_i[1]_i_5_n_0 ), + .I4(\m_payload_i_reg[2]_1 ), + .I5(m_axi_rdata[236]), + .O(\skid_buffer[15]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF4F44)) \skid_buffer[16]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), + (.I0(\skid_buffer[34]_i_2_n_0 ), .I1(m_axi_rdata[45]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[77]), + .I2(\m_payload_i[1]_i_2_n_0 ), + .I3(m_axi_rdata[109]), .I4(\skid_buffer[16]_i_2_n_0 ), .I5(\skid_buffer[16]_i_3_n_0 ), - .O(aa_rmesg[16])); + .O(\skid_buffer[16]_i_1_n_0 )); LUT6 #( - .INIT(64'hFFFFF888F888F888)) + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[16]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[269]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[237]), - .I4(m_axi_rdata[13]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_axi_rdata[269]), + .I1(\skid_buffer_reg[9]_0 ), + .I2(m_axi_rdata[205]), + .I3(\m_payload_i_reg[2]_0 ), + .I4(\skid_buffer[31]_i_2_n_0 ), + .I5(m_axi_rdata[77]), .O(\skid_buffer[16]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'hEFEEEFEEFFFFEFEE)) \skid_buffer[16]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[141]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[109]), - .I4(\skid_buffer[16]_i_4_n_0 ), + (.I0(\skid_buffer[16]_i_4_n_0 ), + .I1(\skid_buffer[16]_i_5_n_0 ), + .I2(\m_payload_i[1]_i_5_n_0 ), + .I3(m_axi_rdata[333]), + .I4(m_axi_rdata[237]), + .I5(\m_payload_i_reg[2]_1 ), .O(\skid_buffer[16]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h00000C0800000008)) \skid_buffer[16]_i_4 - (.I0(m_axi_rdata[173]), - .I1(m_axi_rdata[205]), + (.I0(m_axi_rdata[141]), + .I1(m_atarget_enc[2]), .I2(m_atarget_enc[3]), .I3(m_atarget_enc[0]), .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + .I5(m_axi_rdata[173]), .O(\skid_buffer[16]_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'h0000200300002000)) + \skid_buffer[16]_i_5 + (.I0(m_axi_rdata[301]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[0]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[13]), + .O(\skid_buffer[16]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF4F44)) \skid_buffer[17]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), + (.I0(\skid_buffer[34]_i_2_n_0 ), .I1(m_axi_rdata[46]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[78]), + .I2(\skid_buffer[32]_i_6_n_0 ), + .I3(m_axi_rdata[142]), .I4(\skid_buffer[17]_i_2_n_0 ), .I5(\skid_buffer[17]_i_3_n_0 ), - .O(aa_rmesg[17])); + .O(\skid_buffer[17]_i_1_n_0 )); LUT6 #( - .INIT(64'hFFFFF888F888F888)) + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[17]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[270]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[238]), - .I4(m_axi_rdata[14]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_axi_rdata[270]), + .I1(\skid_buffer_reg[9]_0 ), + .I2(m_axi_rdata[206]), + .I3(\m_payload_i_reg[2]_0 ), + .I4(\skid_buffer[31]_i_2_n_0 ), + .I5(m_axi_rdata[78]), .O(\skid_buffer[17]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'hEFEEEFEEFFFFEFEE)) \skid_buffer[17]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[142]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[110]), - .I4(\skid_buffer[17]_i_4_n_0 ), + (.I0(\skid_buffer[17]_i_4_n_0 ), + .I1(\skid_buffer[17]_i_5_n_0 ), + .I2(\skid_buffer_reg[30]_0 ), + .I3(m_axi_rdata[302]), + .I4(m_axi_rdata[238]), + .I5(\m_payload_i_reg[2]_1 ), .O(\skid_buffer[17]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h02000C0002000000)) \skid_buffer[17]_i_4 - (.I0(m_axi_rdata[174]), - .I1(m_axi_rdata[206]), + (.I0(m_axi_rdata[110]), + .I1(m_atarget_enc[2]), .I2(m_atarget_enc[3]), .I3(m_atarget_enc[0]), .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + .I5(m_axi_rdata[174]), .O(\skid_buffer[17]_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'h0000080300000800)) + \skid_buffer[17]_i_5 + (.I0(m_axi_rdata[334]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[0]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[14]), + .O(\skid_buffer[17]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF4F44)) \skid_buffer[18]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), + (.I0(\skid_buffer[34]_i_2_n_0 ), .I1(m_axi_rdata[47]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[79]), + .I2(\m_payload_i[1]_i_2_n_0 ), + .I3(m_axi_rdata[111]), .I4(\skid_buffer[18]_i_2_n_0 ), .I5(\skid_buffer[18]_i_3_n_0 ), - .O(aa_rmesg[18])); + .O(\skid_buffer[18]_i_1_n_0 )); LUT6 #( - .INIT(64'hFFFFF888F888F888)) + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[18]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[271]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[239]), - .I4(m_axi_rdata[15]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_axi_rdata[271]), + .I1(\skid_buffer_reg[9]_0 ), + .I2(m_axi_rdata[207]), + .I3(\m_payload_i_reg[2]_0 ), + .I4(\skid_buffer[31]_i_2_n_0 ), + .I5(m_axi_rdata[79]), .O(\skid_buffer[18]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'hEFEEEFEEFFFFEFEE)) \skid_buffer[18]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[143]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[111]), - .I4(\skid_buffer[18]_i_4_n_0 ), + (.I0(\skid_buffer[18]_i_4_n_0 ), + .I1(\skid_buffer[18]_i_5_n_0 ), + .I2(\m_payload_i_reg[1]_0 ), + .I3(m_axi_rdata[15]), + .I4(m_axi_rdata[239]), + .I5(\m_payload_i_reg[2]_1 ), .O(\skid_buffer[18]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h00000C0800000008)) \skid_buffer[18]_i_4 - (.I0(m_axi_rdata[175]), - .I1(m_axi_rdata[207]), + (.I0(m_axi_rdata[143]), + .I1(m_atarget_enc[2]), .I2(m_atarget_enc[3]), .I3(m_atarget_enc[0]), .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + .I5(m_axi_rdata[175]), .O(\skid_buffer[18]_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'h00002C0000002000)) + \skid_buffer[18]_i_5 + (.I0(m_axi_rdata[303]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[0]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[335]), + .O(\skid_buffer[18]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFEFFFEFFFFFFFE)) \skid_buffer[19]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), - .I1(m_axi_rdata[48]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[80]), - .I4(\skid_buffer[19]_i_2_n_0 ), - .I5(\skid_buffer[19]_i_3_n_0 ), - .O(aa_rmesg[19])); - LUT6 #( - .INIT(64'hFFFFF888F888F888)) + (.I0(\skid_buffer[19]_i_2_n_0 ), + .I1(\skid_buffer[19]_i_3_n_0 ), + .I2(\skid_buffer[19]_i_4_n_0 ), + .I3(\skid_buffer[19]_i_5_n_0 ), + .I4(m_axi_rdata[48]), + .I5(\skid_buffer[34]_i_2_n_0 ), + .O(\skid_buffer[19]_i_1_n_0 )); + LUT6 #( + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[19]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[272]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[240]), - .I4(m_axi_rdata[16]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_axi_rdata[80]), + .I1(\skid_buffer[31]_i_2_n_0 ), + .I2(m_axi_rdata[112]), + .I3(\m_payload_i[1]_i_2_n_0 ), + .I4(\skid_buffer[32]_i_6_n_0 ), + .I5(m_axi_rdata[144]), .O(\skid_buffer[19]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'h0008000300080000)) \skid_buffer[19]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[144]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[112]), - .I4(\skid_buffer[19]_i_4_n_0 ), + (.I0(m_axi_rdata[208]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[0]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[16]), .O(\skid_buffer[19]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h08000C0008000000)) \skid_buffer[19]_i_4 - (.I0(m_axi_rdata[176]), - .I1(m_axi_rdata[208]), + (.I0(m_axi_rdata[240]), + .I1(m_atarget_enc[2]), .I2(m_atarget_enc[3]), .I3(m_atarget_enc[0]), .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + .I5(m_axi_rdata[176]), .O(\skid_buffer[19]_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) - \skid_buffer[1]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), - .I1(m_axi_rresp[2]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rresp[4]), - .I4(\skid_buffer[1]_i_2_n_0 ), - .I5(\skid_buffer[1]_i_3_n_0 ), - .O(aa_rmesg[1])); - LUT6 #( - .INIT(64'hAABAAAABAABAAAAA)) - \skid_buffer[1]_i_2 - (.I0(\skid_buffer[1]_i_4_n_0 ), - .I1(m_atarget_enc[1]), - .I2(m_atarget_enc[0]), - .I3(m_atarget_enc[2]), - .I4(m_atarget_enc[3]), - .I5(m_axi_rresp[0]), - .O(\skid_buffer[1]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) - \skid_buffer[1]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rresp[8]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rresp[6]), - .I4(\skid_buffer[1]_i_5_n_0 ), - .O(\skid_buffer[1]_i_3_n_0 )); - LUT6 #( - .INIT(64'h0000A000000C0000)) - \skid_buffer[1]_i_4 - (.I0(m_axi_rresp[14]), - .I1(m_axi_rresp[16]), - .I2(m_atarget_enc[0]), - .I3(m_atarget_enc[2]), - .I4(m_atarget_enc[3]), - .I5(m_atarget_enc[1]), - .O(\skid_buffer[1]_i_4_n_0 )); - LUT6 #( - .INIT(64'h000C0A0000000000)) - \skid_buffer[1]_i_5 - (.I0(m_axi_rresp[10]), - .I1(m_axi_rresp[12]), - .I2(m_atarget_enc[3]), + .INIT(64'h00000CAF00000CA0)) + \skid_buffer[19]_i_5 + (.I0(m_axi_rdata[336]), + .I1(m_axi_rdata[304]), + .I2(m_atarget_enc[1]), .I3(m_atarget_enc[0]), - .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), - .O(\skid_buffer[1]_i_5_n_0 )); + .I4(\skid_buffer[28]_i_6_n_0 ), + .I5(m_axi_rdata[272]), + .O(\skid_buffer[19]_i_5_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'hFFFFFFFFFFFF4F44)) \skid_buffer[20]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), + (.I0(\skid_buffer[34]_i_2_n_0 ), .I1(m_axi_rdata[49]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[81]), + .I2(\skid_buffer[32]_i_6_n_0 ), + .I3(m_axi_rdata[145]), .I4(\skid_buffer[20]_i_2_n_0 ), .I5(\skid_buffer[20]_i_3_n_0 ), - .O(aa_rmesg[20])); + .O(\skid_buffer[20]_i_1_n_0 )); LUT6 #( - .INIT(64'hFFFFF888F888F888)) + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[20]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[273]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[241]), - .I4(m_axi_rdata[17]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_axi_rdata[273]), + .I1(\skid_buffer_reg[9]_0 ), + .I2(m_axi_rdata[209]), + .I3(\m_payload_i_reg[2]_0 ), + .I4(\skid_buffer[31]_i_2_n_0 ), + .I5(m_axi_rdata[81]), .O(\skid_buffer[20]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'hEFEEEFEEFFFFEFEE)) \skid_buffer[20]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[145]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[113]), - .I4(\skid_buffer[20]_i_4_n_0 ), + (.I0(\skid_buffer[20]_i_4_n_0 ), + .I1(\skid_buffer[20]_i_5_n_0 ), + .I2(\skid_buffer_reg[30]_0 ), + .I3(m_axi_rdata[305]), + .I4(m_axi_rdata[241]), + .I5(\m_payload_i_reg[2]_1 ), .O(\skid_buffer[20]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h02000C0002000000)) \skid_buffer[20]_i_4 - (.I0(m_axi_rdata[177]), - .I1(m_axi_rdata[209]), + (.I0(m_axi_rdata[113]), + .I1(m_atarget_enc[2]), .I2(m_atarget_enc[3]), .I3(m_atarget_enc[0]), .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + .I5(m_axi_rdata[177]), .O(\skid_buffer[20]_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'h0000080300000800)) + \skid_buffer[20]_i_5 + (.I0(m_axi_rdata[337]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[0]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[17]), + .O(\skid_buffer[20]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFEFFFEFFFFFFFE)) \skid_buffer[21]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), - .I1(m_axi_rdata[50]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[82]), - .I4(\skid_buffer[21]_i_2_n_0 ), - .I5(\skid_buffer[21]_i_3_n_0 ), - .O(aa_rmesg[21])); - LUT6 #( - .INIT(64'hFFFFF888F888F888)) + (.I0(\skid_buffer[21]_i_2_n_0 ), + .I1(\skid_buffer[21]_i_3_n_0 ), + .I2(\skid_buffer[21]_i_4_n_0 ), + .I3(\skid_buffer[21]_i_5_n_0 ), + .I4(m_axi_rdata[114]), + .I5(\m_payload_i[1]_i_2_n_0 ), + .O(\skid_buffer[21]_i_1_n_0 )); + LUT6 #( + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[21]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[274]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[242]), - .I4(m_axi_rdata[18]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_axi_rdata[146]), + .I1(\skid_buffer[32]_i_6_n_0 ), + .I2(m_axi_rdata[82]), + .I3(\skid_buffer[31]_i_2_n_0 ), + .I4(\skid_buffer[34]_i_2_n_0 ), + .I5(m_axi_rdata[50]), .O(\skid_buffer[21]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'h0020000300200000)) \skid_buffer[21]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[146]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[114]), - .I4(\skid_buffer[21]_i_4_n_0 ), + (.I0(m_axi_rdata[178]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[0]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[18]), .O(\skid_buffer[21]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h00000C2000000020)) \skid_buffer[21]_i_4 - (.I0(m_axi_rdata[178]), - .I1(m_axi_rdata[210]), + (.I0(m_axi_rdata[274]), + .I1(m_atarget_enc[2]), .I2(m_atarget_enc[3]), - .I3(m_atarget_enc[0]), - .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + .I3(m_atarget_enc[1]), + .I4(m_atarget_enc[0]), + .I5(m_axi_rdata[210]), .O(\skid_buffer[21]_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'h22F2FFFF22F222F2)) + \skid_buffer[21]_i_5 + (.I0(m_axi_rdata[338]), + .I1(\m_payload_i[1]_i_5_n_0 ), + .I2(m_axi_rdata[306]), + .I3(\skid_buffer_reg[30]_0 ), + .I4(\m_payload_i_reg[2]_1 ), + .I5(m_axi_rdata[242]), + .O(\skid_buffer[21]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFEFFFEFFFFFFFE)) \skid_buffer[22]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), - .I1(m_axi_rdata[51]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[83]), - .I4(\skid_buffer[22]_i_2_n_0 ), - .I5(\skid_buffer[22]_i_3_n_0 ), - .O(aa_rmesg[22])); - LUT6 #( - .INIT(64'hFFFFF888F888F888)) + (.I0(\skid_buffer[22]_i_2_n_0 ), + .I1(\skid_buffer[22]_i_3_n_0 ), + .I2(\skid_buffer[22]_i_4_n_0 ), + .I3(\skid_buffer[22]_i_5_n_0 ), + .I4(m_axi_rdata[115]), + .I5(\m_payload_i[1]_i_2_n_0 ), + .O(\skid_buffer[22]_i_1_n_0 )); + LUT6 #( + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[22]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[275]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[243]), - .I4(m_axi_rdata[19]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_axi_rdata[83]), + .I1(\skid_buffer[31]_i_2_n_0 ), + .I2(m_axi_rdata[51]), + .I3(\skid_buffer[34]_i_2_n_0 ), + .I4(\skid_buffer[32]_i_6_n_0 ), + .I5(m_axi_rdata[147]), .O(\skid_buffer[22]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'h00080C0000080000)) \skid_buffer[22]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[147]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[115]), - .I4(\skid_buffer[22]_i_4_n_0 ), + (.I0(m_axi_rdata[179]), + .I1(m_atarget_enc[0]), + .I2(m_atarget_enc[1]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[307]), .O(\skid_buffer[22]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h00000C2000000020)) \skid_buffer[22]_i_4 - (.I0(m_axi_rdata[179]), - .I1(m_axi_rdata[211]), + (.I0(m_axi_rdata[275]), + .I1(m_atarget_enc[2]), .I2(m_atarget_enc[3]), - .I3(m_atarget_enc[0]), - .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + .I3(m_atarget_enc[1]), + .I4(m_atarget_enc[0]), + .I5(m_axi_rdata[211]), .O(\skid_buffer[22]_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'h22F2FFFF22F222F2)) + \skid_buffer[22]_i_5 + (.I0(m_axi_rdata[19]), + .I1(\m_payload_i_reg[1]_0 ), + .I2(m_axi_rdata[339]), + .I3(\m_payload_i[1]_i_5_n_0 ), + .I4(\m_payload_i_reg[2]_1 ), + .I5(m_axi_rdata[243]), + .O(\skid_buffer[22]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF4F44)) \skid_buffer[23]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), + (.I0(\skid_buffer[34]_i_2_n_0 ), .I1(m_axi_rdata[52]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[84]), + .I2(\m_payload_i[1]_i_2_n_0 ), + .I3(m_axi_rdata[116]), .I4(\skid_buffer[23]_i_2_n_0 ), .I5(\skid_buffer[23]_i_3_n_0 ), - .O(aa_rmesg[23])); + .O(\skid_buffer[23]_i_1_n_0 )); LUT6 #( - .INIT(64'hFFFFF888F888F888)) + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[23]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[276]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[244]), - .I4(m_axi_rdata[20]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_axi_rdata[276]), + .I1(\skid_buffer_reg[9]_0 ), + .I2(m_axi_rdata[180]), + .I3(\skid_buffer[34]_i_5_n_0 ), + .I4(\skid_buffer[31]_i_2_n_0 ), + .I5(m_axi_rdata[84]), .O(\skid_buffer[23]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'hEFEEEFEEFFFFEFEE)) \skid_buffer[23]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[148]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[116]), - .I4(\skid_buffer[23]_i_4_n_0 ), + (.I0(\skid_buffer[23]_i_4_n_0 ), + .I1(\skid_buffer[23]_i_5_n_0 ), + .I2(\m_payload_i_reg[1]_0 ), + .I3(m_axi_rdata[20]), + .I4(m_axi_rdata[244]), + .I5(\m_payload_i_reg[2]_1 ), .O(\skid_buffer[23]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h00000C0800000008)) \skid_buffer[23]_i_4 - (.I0(m_axi_rdata[180]), - .I1(m_axi_rdata[212]), + (.I0(m_axi_rdata[148]), + .I1(m_atarget_enc[2]), .I2(m_atarget_enc[3]), - .I3(m_atarget_enc[0]), - .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + .I3(m_atarget_enc[1]), + .I4(m_atarget_enc[0]), + .I5(m_axi_rdata[212]), .O(\skid_buffer[23]_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'h00002C0000002000)) + \skid_buffer[23]_i_5 + (.I0(m_axi_rdata[308]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[0]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[340]), + .O(\skid_buffer[23]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFEFFFEFFFFFFFE)) \skid_buffer[24]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), - .I1(m_axi_rdata[53]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[85]), - .I4(\skid_buffer[24]_i_2_n_0 ), - .I5(\skid_buffer[24]_i_3_n_0 ), - .O(aa_rmesg[24])); - LUT6 #( - .INIT(64'hFFFFF888F888F888)) + (.I0(\skid_buffer[24]_i_2_n_0 ), + .I1(\skid_buffer[24]_i_3_n_0 ), + .I2(\skid_buffer[24]_i_4_n_0 ), + .I3(\skid_buffer[24]_i_5_n_0 ), + .I4(m_axi_rdata[117]), + .I5(\m_payload_i[1]_i_2_n_0 ), + .O(\skid_buffer[24]_i_1_n_0 )); + LUT6 #( + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[24]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[277]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[245]), - .I4(m_axi_rdata[21]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_axi_rdata[149]), + .I1(\skid_buffer[32]_i_6_n_0 ), + .I2(m_axi_rdata[85]), + .I3(\skid_buffer[31]_i_2_n_0 ), + .I4(\skid_buffer[34]_i_2_n_0 ), + .I5(m_axi_rdata[53]), .O(\skid_buffer[24]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'h00200C0000200000)) \skid_buffer[24]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[149]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[117]), - .I4(\skid_buffer[24]_i_4_n_0 ), + (.I0(m_axi_rdata[213]), + .I1(m_atarget_enc[0]), + .I2(m_atarget_enc[1]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[309]), .O(\skid_buffer[24]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h00000C2000000020)) \skid_buffer[24]_i_4 - (.I0(m_axi_rdata[181]), - .I1(m_axi_rdata[213]), + (.I0(m_axi_rdata[277]), + .I1(m_atarget_enc[2]), .I2(m_atarget_enc[3]), .I3(m_atarget_enc[0]), .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + .I5(m_axi_rdata[181]), .O(\skid_buffer[24]_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'h22F2FFFF22F222F2)) + \skid_buffer[24]_i_5 + (.I0(m_axi_rdata[21]), + .I1(\m_payload_i_reg[1]_0 ), + .I2(m_axi_rdata[341]), + .I3(\m_payload_i[1]_i_5_n_0 ), + .I4(\m_payload_i_reg[2]_1 ), + .I5(m_axi_rdata[245]), + .O(\skid_buffer[24]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF4F44)) \skid_buffer[25]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), + (.I0(\skid_buffer[34]_i_2_n_0 ), .I1(m_axi_rdata[54]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[86]), + .I2(\m_payload_i[1]_i_2_n_0 ), + .I3(m_axi_rdata[118]), .I4(\skid_buffer[25]_i_2_n_0 ), .I5(\skid_buffer[25]_i_3_n_0 ), - .O(aa_rmesg[25])); + .O(\skid_buffer[25]_i_1_n_0 )); LUT6 #( - .INIT(64'hFFFFF888F888F888)) + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[25]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[278]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[246]), - .I4(m_axi_rdata[22]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_axi_rdata[278]), + .I1(\skid_buffer_reg[9]_0 ), + .I2(m_axi_rdata[214]), + .I3(\m_payload_i_reg[2]_0 ), + .I4(\skid_buffer[31]_i_2_n_0 ), + .I5(m_axi_rdata[86]), .O(\skid_buffer[25]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'hEFEEEFEEFFFFEFEE)) \skid_buffer[25]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[150]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[118]), - .I4(\skid_buffer[25]_i_4_n_0 ), + (.I0(\skid_buffer[25]_i_4_n_0 ), + .I1(\skid_buffer[25]_i_5_n_0 ), + .I2(\m_payload_i[1]_i_5_n_0 ), + .I3(m_axi_rdata[342]), + .I4(m_axi_rdata[246]), + .I5(\m_payload_i_reg[2]_1 ), .O(\skid_buffer[25]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h00000C0800000008)) \skid_buffer[25]_i_4 - (.I0(m_axi_rdata[182]), - .I1(m_axi_rdata[214]), + (.I0(m_axi_rdata[150]), + .I1(m_atarget_enc[2]), .I2(m_atarget_enc[3]), .I3(m_atarget_enc[0]), .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + .I5(m_axi_rdata[182]), .O(\skid_buffer[25]_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'h0000200300002000)) + \skid_buffer[25]_i_5 + (.I0(m_axi_rdata[310]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[0]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[22]), + .O(\skid_buffer[25]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFEFFFEFFFFFFFE)) \skid_buffer[26]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), - .I1(m_axi_rdata[55]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[87]), - .I4(\skid_buffer[26]_i_2_n_0 ), - .I5(\skid_buffer[26]_i_3_n_0 ), - .O(aa_rmesg[26])); - LUT6 #( - .INIT(64'hFFFFF888F888F888)) + (.I0(\skid_buffer[26]_i_2_n_0 ), + .I1(\skid_buffer[26]_i_3_n_0 ), + .I2(\skid_buffer[26]_i_4_n_0 ), + .I3(\skid_buffer[26]_i_5_n_0 ), + .I4(m_axi_rdata[87]), + .I5(\skid_buffer[31]_i_2_n_0 ), + .O(\skid_buffer[26]_i_1_n_0 )); + LUT6 #( + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[26]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[279]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[247]), - .I4(m_axi_rdata[23]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_axi_rdata[55]), + .I1(\skid_buffer[34]_i_2_n_0 ), + .I2(m_axi_rdata[151]), + .I3(\skid_buffer[32]_i_6_n_0 ), + .I4(\m_payload_i[1]_i_2_n_0 ), + .I5(m_axi_rdata[119]), .O(\skid_buffer[26]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'h00200C0000200000)) \skid_buffer[26]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[151]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[119]), - .I4(\skid_buffer[26]_i_4_n_0 ), + (.I0(m_axi_rdata[215]), + .I1(m_atarget_enc[0]), + .I2(m_atarget_enc[1]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[311]), .O(\skid_buffer[26]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h00000C2000000020)) \skid_buffer[26]_i_4 - (.I0(m_axi_rdata[183]), - .I1(m_axi_rdata[215]), + (.I0(m_axi_rdata[279]), + .I1(m_atarget_enc[2]), .I2(m_atarget_enc[3]), .I3(m_atarget_enc[0]), .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + .I5(m_axi_rdata[183]), .O(\skid_buffer[26]_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'h22F2FFFF22F222F2)) + \skid_buffer[26]_i_5 + (.I0(m_axi_rdata[343]), + .I1(\m_payload_i[1]_i_5_n_0 ), + .I2(m_axi_rdata[23]), + .I3(\m_payload_i_reg[1]_0 ), + .I4(\m_payload_i_reg[2]_1 ), + .I5(m_axi_rdata[247]), + .O(\skid_buffer[26]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFEFFFEFFFFFFFE)) \skid_buffer[27]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), - .I1(m_axi_rdata[56]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[88]), - .I4(\skid_buffer[27]_i_2_n_0 ), - .I5(\skid_buffer[27]_i_3_n_0 ), - .O(aa_rmesg[27])); - LUT6 #( - .INIT(64'hFFFFF888F888F888)) + (.I0(\skid_buffer[27]_i_2_n_0 ), + .I1(\skid_buffer[27]_i_3_n_0 ), + .I2(\skid_buffer[27]_i_4_n_0 ), + .I3(\skid_buffer[27]_i_5_n_0 ), + .I4(m_axi_rdata[120]), + .I5(\m_payload_i[1]_i_2_n_0 ), + .O(\skid_buffer[27]_i_1_n_0 )); + LUT6 #( + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[27]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[280]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[248]), - .I4(m_axi_rdata[24]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_axi_rdata[152]), + .I1(\skid_buffer[32]_i_6_n_0 ), + .I2(m_axi_rdata[56]), + .I3(\skid_buffer[34]_i_2_n_0 ), + .I4(\skid_buffer[31]_i_2_n_0 ), + .I5(m_axi_rdata[88]), .O(\skid_buffer[27]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'h0020000300200000)) \skid_buffer[27]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[152]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[120]), - .I4(\skid_buffer[27]_i_4_n_0 ), + (.I0(m_axi_rdata[184]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[0]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[24]), .O(\skid_buffer[27]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h08000C0008000000)) \skid_buffer[27]_i_4 - (.I0(m_axi_rdata[184]), - .I1(m_axi_rdata[216]), + (.I0(m_axi_rdata[248]), + .I1(m_atarget_enc[2]), .I2(m_atarget_enc[3]), - .I3(m_atarget_enc[0]), - .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + .I3(m_atarget_enc[1]), + .I4(m_atarget_enc[0]), + .I5(m_axi_rdata[216]), .O(\skid_buffer[27]_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'h00000ACF00000AC0)) + \skid_buffer[27]_i_5 + (.I0(m_axi_rdata[312]), + .I1(m_axi_rdata[344]), + .I2(m_atarget_enc[1]), + .I3(m_atarget_enc[0]), + .I4(\skid_buffer[28]_i_6_n_0 ), + .I5(m_axi_rdata[280]), + .O(\skid_buffer[27]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFEFFFEFFFFFFFE)) \skid_buffer[28]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), - .I1(m_axi_rdata[57]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[89]), - .I4(\skid_buffer[28]_i_2_n_0 ), - .I5(\skid_buffer[28]_i_3_n_0 ), - .O(aa_rmesg[28])); - LUT6 #( - .INIT(64'hFFFFF888F888F888)) + (.I0(\skid_buffer[28]_i_2_n_0 ), + .I1(\skid_buffer[28]_i_3_n_0 ), + .I2(\skid_buffer[28]_i_4_n_0 ), + .I3(\skid_buffer[28]_i_5_n_0 ), + .I4(m_axi_rdata[57]), + .I5(\skid_buffer[34]_i_2_n_0 ), + .O(\skid_buffer[28]_i_1_n_0 )); + LUT6 #( + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[28]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[281]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[249]), - .I4(m_axi_rdata[25]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_axi_rdata[89]), + .I1(\skid_buffer[31]_i_2_n_0 ), + .I2(m_axi_rdata[153]), + .I3(\skid_buffer[32]_i_6_n_0 ), + .I4(\m_payload_i[1]_i_2_n_0 ), + .I5(m_axi_rdata[121]), .O(\skid_buffer[28]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'h0008000300080000)) \skid_buffer[28]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[153]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[121]), - .I4(\skid_buffer[28]_i_4_n_0 ), + (.I0(m_axi_rdata[217]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[0]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[25]), .O(\skid_buffer[28]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h08000C0008000000)) \skid_buffer[28]_i_4 - (.I0(m_axi_rdata[185]), - .I1(m_axi_rdata[217]), + (.I0(m_axi_rdata[249]), + .I1(m_atarget_enc[2]), .I2(m_atarget_enc[3]), .I3(m_atarget_enc[0]), .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + .I5(m_axi_rdata[185]), .O(\skid_buffer[28]_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'h00000CAF00000CA0)) + \skid_buffer[28]_i_5 + (.I0(m_axi_rdata[345]), + .I1(m_axi_rdata[313]), + .I2(m_atarget_enc[1]), + .I3(m_atarget_enc[0]), + .I4(\skid_buffer[28]_i_6_n_0 ), + .I5(m_axi_rdata[281]), + .O(\skid_buffer[28]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT2 #( + .INIT(4'hB)) + \skid_buffer[28]_i_6 + (.I0(m_atarget_enc[2]), + .I1(m_atarget_enc[3]), + .O(\skid_buffer[28]_i_6_n_0 )); + LUT6 #( + .INIT(64'hFFFEFFFEFFFFFFFE)) \skid_buffer[29]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), - .I1(m_axi_rdata[58]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[90]), - .I4(\skid_buffer[29]_i_2_n_0 ), - .I5(\skid_buffer[29]_i_3_n_0 ), - .O(aa_rmesg[29])); - LUT6 #( - .INIT(64'hFFFFF888F888F888)) + (.I0(\skid_buffer[29]_i_2_n_0 ), + .I1(\skid_buffer[29]_i_3_n_0 ), + .I2(\skid_buffer[29]_i_4_n_0 ), + .I3(\skid_buffer[29]_i_5_n_0 ), + .I4(m_axi_rdata[154]), + .I5(\skid_buffer[32]_i_6_n_0 ), + .O(\skid_buffer[29]_i_1_n_0 )); + LUT6 #( + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[29]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[282]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[250]), - .I4(m_axi_rdata[26]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_axi_rdata[122]), + .I1(\m_payload_i[1]_i_2_n_0 ), + .I2(m_axi_rdata[90]), + .I3(\skid_buffer[31]_i_2_n_0 ), + .I4(\skid_buffer[34]_i_2_n_0 ), + .I5(m_axi_rdata[58]), .O(\skid_buffer[29]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'h00080C0000080000)) \skid_buffer[29]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[154]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[122]), - .I4(\skid_buffer[29]_i_4_n_0 ), + (.I0(m_axi_rdata[186]), + .I1(m_atarget_enc[0]), + .I2(m_atarget_enc[1]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[314]), .O(\skid_buffer[29]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h00000C2000000020)) \skid_buffer[29]_i_4 - (.I0(m_axi_rdata[186]), - .I1(m_axi_rdata[218]), + (.I0(m_axi_rdata[282]), + .I1(m_atarget_enc[2]), .I2(m_atarget_enc[3]), - .I3(m_atarget_enc[0]), - .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + .I3(m_atarget_enc[1]), + .I4(m_atarget_enc[0]), + .I5(m_axi_rdata[218]), .O(\skid_buffer[29]_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) - \skid_buffer[2]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), - .I1(m_axi_rresp[3]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rresp[5]), - .I4(\skid_buffer[2]_i_2_n_0 ), - .I5(\skid_buffer[2]_i_3_n_0 ), - .O(aa_rmesg[2])); - LUT6 #( - .INIT(64'hAABAAAABAABAAAAA)) - \skid_buffer[2]_i_2 - (.I0(\skid_buffer[2]_i_4_n_0 ), - .I1(m_atarget_enc[1]), - .I2(m_atarget_enc[0]), - .I3(m_atarget_enc[2]), - .I4(m_atarget_enc[3]), - .I5(m_axi_rresp[1]), - .O(\skid_buffer[2]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) - \skid_buffer[2]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rresp[9]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rresp[7]), - .I4(\skid_buffer[2]_i_5_n_0 ), - .O(\skid_buffer[2]_i_3_n_0 )); - LUT6 #( - .INIT(64'h0000A000000C0000)) - \skid_buffer[2]_i_4 - (.I0(m_axi_rresp[15]), - .I1(m_axi_rresp[17]), - .I2(m_atarget_enc[0]), - .I3(m_atarget_enc[2]), - .I4(m_atarget_enc[3]), - .I5(m_atarget_enc[1]), - .O(\skid_buffer[2]_i_4_n_0 )); - LUT6 #( - .INIT(64'h000C0A0000000000)) - \skid_buffer[2]_i_5 - (.I0(m_axi_rresp[11]), - .I1(m_axi_rresp[13]), - .I2(m_atarget_enc[3]), - .I3(m_atarget_enc[0]), - .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), - .O(\skid_buffer[2]_i_5_n_0 )); - LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'h22F2FFFF22F222F2)) + \skid_buffer[29]_i_5 + (.I0(m_axi_rdata[26]), + .I1(\m_payload_i_reg[1]_0 ), + .I2(m_axi_rdata[346]), + .I3(\m_payload_i[1]_i_5_n_0 ), + .I4(\m_payload_i_reg[2]_1 ), + .I5(m_axi_rdata[250]), + .O(\skid_buffer[29]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF4F44)) \skid_buffer[30]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), + (.I0(\skid_buffer[34]_i_2_n_0 ), .I1(m_axi_rdata[59]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[91]), + .I2(\skid_buffer[32]_i_6_n_0 ), + .I3(m_axi_rdata[155]), .I4(\skid_buffer[30]_i_2_n_0 ), .I5(\skid_buffer[30]_i_3_n_0 ), - .O(aa_rmesg[30])); + .O(\skid_buffer[30]_i_1_n_0 )); LUT6 #( - .INIT(64'hFFFFF888F888F888)) + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[30]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[283]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[251]), - .I4(m_axi_rdata[27]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_axi_rdata[283]), + .I1(\skid_buffer_reg[9]_0 ), + .I2(m_axi_rdata[187]), + .I3(\skid_buffer[34]_i_5_n_0 ), + .I4(\skid_buffer[31]_i_2_n_0 ), + .I5(m_axi_rdata[91]), .O(\skid_buffer[30]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'hEFEEEFEEFFFFEFEE)) \skid_buffer[30]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[155]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[123]), - .I4(\skid_buffer[30]_i_4_n_0 ), + (.I0(\skid_buffer[30]_i_4_n_0 ), + .I1(\skid_buffer[30]_i_5_n_0 ), + .I2(\skid_buffer_reg[30]_0 ), + .I3(m_axi_rdata[315]), + .I4(m_axi_rdata[251]), + .I5(\m_payload_i_reg[2]_1 ), .O(\skid_buffer[30]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h02000C0002000000)) \skid_buffer[30]_i_4 - (.I0(m_axi_rdata[187]), - .I1(m_axi_rdata[219]), + (.I0(m_axi_rdata[123]), + .I1(m_atarget_enc[2]), .I2(m_atarget_enc[3]), - .I3(m_atarget_enc[0]), - .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + .I3(m_atarget_enc[1]), + .I4(m_atarget_enc[0]), + .I5(m_axi_rdata[219]), .O(\skid_buffer[30]_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) - \skid_buffer[31]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), - .I1(m_axi_rdata[60]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[92]), - .I4(\skid_buffer[31]_i_2_n_0 ), - .I5(\skid_buffer[31]_i_3_n_0 ), - .O(aa_rmesg[31])); + .INIT(64'h0000080300000800)) + \skid_buffer[30]_i_5 + (.I0(m_axi_rdata[347]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[0]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[27]), + .O(\skid_buffer[30]_i_5_n_0 )); LUT6 #( - .INIT(64'hFFFFF888F888F888)) + .INIT(64'hFFFFFFFFFFFF4F44)) + \skid_buffer[31]_i_1 + (.I0(\skid_buffer[31]_i_2_n_0 ), + .I1(m_axi_rdata[92]), + .I2(\m_payload_i[1]_i_2_n_0 ), + .I3(m_axi_rdata[124]), + .I4(\skid_buffer[31]_i_3_n_0 ), + .I5(\skid_buffer[31]_i_4_n_0 ), + .O(\skid_buffer[31]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFFFD)) \skid_buffer[31]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[284]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[252]), - .I4(m_axi_rdata[28]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_atarget_enc[1]), + .I1(m_atarget_enc[0]), + .I2(m_atarget_enc[3]), + .I3(m_atarget_enc[2]), .O(\skid_buffer[31]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[31]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[156]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[124]), - .I4(\skid_buffer[31]_i_4_n_0 ), + (.I0(m_axi_rdata[188]), + .I1(\skid_buffer[34]_i_5_n_0 ), + .I2(m_axi_rdata[252]), + .I3(\m_payload_i_reg[2]_1 ), + .I4(\skid_buffer[34]_i_2_n_0 ), + .I5(m_axi_rdata[60]), .O(\skid_buffer[31]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'hEFEEEFEEFFFFEFEE)) \skid_buffer[31]_i_4 - (.I0(m_axi_rdata[188]), - .I1(m_axi_rdata[220]), - .I2(m_atarget_enc[3]), - .I3(m_atarget_enc[0]), - .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + (.I0(\skid_buffer[31]_i_5_n_0 ), + .I1(\skid_buffer[31]_i_6_n_0 ), + .I2(\m_payload_i_reg[1]_0 ), + .I3(m_axi_rdata[28]), + .I4(m_axi_rdata[220]), + .I5(\m_payload_i_reg[2]_0 ), .O(\skid_buffer[31]_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'h0002030000020000)) + \skid_buffer[31]_i_5 + (.I0(m_axi_rdata[156]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[0]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[284]), + .O(\skid_buffer[31]_i_5_n_0 )); + LUT6 #( + .INIT(64'h00002C0000002000)) + \skid_buffer[31]_i_6 + (.I0(m_axi_rdata[316]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[0]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[348]), + .O(\skid_buffer[31]_i_6_n_0 )); + LUT6 #( + .INIT(64'hFFFEFFFEFFFFFFFE)) \skid_buffer[32]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), - .I1(m_axi_rdata[61]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[93]), - .I4(\skid_buffer[32]_i_2_n_0 ), - .I5(\skid_buffer[32]_i_3_n_0 ), - .O(aa_rmesg[32])); - LUT6 #( - .INIT(64'hFFFFF888F888F888)) + (.I0(\skid_buffer[32]_i_2_n_0 ), + .I1(\skid_buffer[32]_i_3_n_0 ), + .I2(\skid_buffer[32]_i_4_n_0 ), + .I3(\skid_buffer[32]_i_5_n_0 ), + .I4(m_axi_rdata[157]), + .I5(\skid_buffer[32]_i_6_n_0 ), + .O(\skid_buffer[32]_i_1_n_0 )); + LUT6 #( + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[32]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[285]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[253]), - .I4(m_axi_rdata[29]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_axi_rdata[93]), + .I1(\skid_buffer[31]_i_2_n_0 ), + .I2(m_axi_rdata[61]), + .I3(\skid_buffer[34]_i_2_n_0 ), + .I4(\m_payload_i[1]_i_2_n_0 ), + .I5(m_axi_rdata[125]), .O(\skid_buffer[32]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'h00080C0000080000)) \skid_buffer[32]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[157]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[125]), - .I4(\skid_buffer[32]_i_4_n_0 ), + (.I0(m_axi_rdata[189]), + .I1(m_atarget_enc[0]), + .I2(m_atarget_enc[1]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[317]), .O(\skid_buffer[32]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h08000C0008000000)) \skid_buffer[32]_i_4 - (.I0(m_axi_rdata[189]), - .I1(m_axi_rdata[221]), + (.I0(m_axi_rdata[253]), + .I1(m_atarget_enc[2]), .I2(m_atarget_enc[3]), - .I3(m_atarget_enc[0]), - .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + .I3(m_atarget_enc[1]), + .I4(m_atarget_enc[0]), + .I5(m_axi_rdata[221]), .O(\skid_buffer[32]_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'h22F2FFFF22F222F2)) + \skid_buffer[32]_i_5 + (.I0(m_axi_rdata[29]), + .I1(\m_payload_i_reg[1]_0 ), + .I2(m_axi_rdata[349]), + .I3(\m_payload_i[1]_i_5_n_0 ), + .I4(\skid_buffer_reg[9]_0 ), + .I5(m_axi_rdata[285]), + .O(\skid_buffer[32]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT4 #( + .INIT(16'hFFFD)) + \skid_buffer[32]_i_6 + (.I0(m_atarget_enc[2]), + .I1(m_atarget_enc[3]), + .I2(m_atarget_enc[1]), + .I3(m_atarget_enc[0]), + .O(\skid_buffer[32]_i_6_n_0 )); + LUT6 #( + .INIT(64'hFFFEFFFEFFFFFFFE)) \skid_buffer[33]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), - .I1(m_axi_rdata[62]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[94]), - .I4(\skid_buffer[33]_i_2_n_0 ), - .I5(\skid_buffer[33]_i_3_n_0 ), - .O(aa_rmesg[33])); - LUT6 #( - .INIT(64'hFFFFF888F888F888)) + (.I0(\skid_buffer[33]_i_2_n_0 ), + .I1(\skid_buffer[33]_i_3_n_0 ), + .I2(\skid_buffer[33]_i_4_n_0 ), + .I3(\skid_buffer[33]_i_5_n_0 ), + .I4(m_axi_rdata[126]), + .I5(\m_payload_i[1]_i_2_n_0 ), + .O(\skid_buffer[33]_i_1_n_0 )); + LUT6 #( + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[33]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[286]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[254]), - .I4(m_axi_rdata[30]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_axi_rdata[158]), + .I1(\skid_buffer[32]_i_6_n_0 ), + .I2(m_axi_rdata[94]), + .I3(\skid_buffer[31]_i_2_n_0 ), + .I4(\skid_buffer[34]_i_2_n_0 ), + .I5(m_axi_rdata[62]), .O(\skid_buffer[33]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'h0020000300200000)) \skid_buffer[33]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[158]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[126]), - .I4(\skid_buffer[33]_i_4_n_0 ), + (.I0(m_axi_rdata[190]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[0]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[30]), .O(\skid_buffer[33]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h00000C2000000020)) \skid_buffer[33]_i_4 - (.I0(m_axi_rdata[190]), - .I1(m_axi_rdata[222]), + (.I0(m_axi_rdata[286]), + .I1(m_atarget_enc[2]), .I2(m_atarget_enc[3]), - .I3(m_atarget_enc[0]), - .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + .I3(m_atarget_enc[1]), + .I4(m_atarget_enc[0]), + .I5(m_axi_rdata[222]), .O(\skid_buffer[33]_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'h22F2FFFF22F222F2)) + \skid_buffer[33]_i_5 + (.I0(m_axi_rdata[318]), + .I1(\skid_buffer_reg[30]_0 ), + .I2(m_axi_rdata[350]), + .I3(\m_payload_i[1]_i_5_n_0 ), + .I4(\m_payload_i_reg[2]_1 ), + .I5(m_axi_rdata[254]), + .O(\skid_buffer[33]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF4F44)) \skid_buffer[34]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), + (.I0(\skid_buffer[34]_i_2_n_0 ), .I1(m_axi_rdata[63]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[95]), - .I4(\skid_buffer[34]_i_2_n_0 ), - .I5(\skid_buffer[34]_i_3_n_0 ), - .O(aa_rmesg[34])); - LUT6 #( - .INIT(64'hFFFFF888F888F888)) + .I2(\m_payload_i[1]_i_2_n_0 ), + .I3(m_axi_rdata[127]), + .I4(\skid_buffer[34]_i_3_n_0 ), + .I5(\skid_buffer[34]_i_4_n_0 ), + .O(\skid_buffer[34]_i_1_n_0 )); + LUT4 #( + .INIT(16'hFFFD)) \skid_buffer[34]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[287]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[255]), - .I4(m_axi_rdata[31]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_atarget_enc[0]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[3]), + .I3(m_atarget_enc[2]), .O(\skid_buffer[34]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[34]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[159]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[127]), - .I4(\skid_buffer[34]_i_7_n_0 ), + (.I0(m_axi_rdata[287]), + .I1(\skid_buffer_reg[9]_0 ), + .I2(m_axi_rdata[191]), + .I3(\skid_buffer[34]_i_5_n_0 ), + .I4(\skid_buffer[31]_i_2_n_0 ), + .I5(m_axi_rdata[95]), .O(\skid_buffer[34]_i_3_n_0 )); - LUT4 #( - .INIT(16'h0010)) + LUT6 #( + .INIT(64'hEFEEEFEEFFFFEFEE)) \skid_buffer[34]_i_4 - (.I0(m_atarget_enc[0]), - .I1(m_atarget_enc[2]), - .I2(m_atarget_enc[3]), - .I3(m_atarget_enc[1]), + (.I0(\skid_buffer[34]_i_6_n_0 ), + .I1(\skid_buffer[34]_i_7_n_0 ), + .I2(\m_payload_i[1]_i_5_n_0 ), + .I3(m_axi_rdata[351]), + .I4(m_axi_rdata[255]), + .I5(\m_payload_i_reg[2]_1 ), .O(\skid_buffer[34]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair32" *) LUT4 #( - .INIT(16'h2000)) + .INIT(16'hFFDF)) \skid_buffer[34]_i_5 (.I0(m_atarget_enc[2]), .I1(m_atarget_enc[3]), .I2(m_atarget_enc[0]), .I3(m_atarget_enc[1]), .O(\skid_buffer[34]_i_5_n_0 )); - LUT4 #( - .INIT(16'h0001)) + LUT6 #( + .INIT(64'h00000C0800000008)) \skid_buffer[34]_i_6 - (.I0(m_atarget_enc[3]), + (.I0(m_axi_rdata[159]), .I1(m_atarget_enc[2]), - .I2(m_atarget_enc[0]), + .I2(m_atarget_enc[3]), .I3(m_atarget_enc[1]), + .I4(m_atarget_enc[0]), + .I5(m_axi_rdata[223]), .O(\skid_buffer[34]_i_6_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h0000200300002000)) \skid_buffer[34]_i_7 - (.I0(m_axi_rdata[191]), - .I1(m_axi_rdata[223]), - .I2(m_atarget_enc[3]), - .I3(m_atarget_enc[0]), - .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + (.I0(m_axi_rdata[319]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[0]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[31]), .O(\skid_buffer[34]_i_7_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'hFFFFFFFFFFFF4F44)) \skid_buffer[3]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), + (.I0(\skid_buffer[34]_i_2_n_0 ), .I1(m_axi_rdata[32]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[64]), + .I2(\skid_buffer[32]_i_6_n_0 ), + .I3(m_axi_rdata[128]), .I4(\skid_buffer[3]_i_2_n_0 ), .I5(\skid_buffer[3]_i_3_n_0 ), - .O(aa_rmesg[3])); + .O(\skid_buffer[3]_i_1_n_0 )); LUT6 #( - .INIT(64'hFFFFF888F888F888)) + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[3]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[256]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[224]), - .I4(m_axi_rdata[0]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_axi_rdata[192]), + .I1(\m_payload_i_reg[2]_0 ), + .I2(m_axi_rdata[224]), + .I3(\m_payload_i_reg[2]_1 ), + .I4(\skid_buffer[31]_i_2_n_0 ), + .I5(m_axi_rdata[64]), .O(\skid_buffer[3]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'hEFEEEFEEFFFFEFEE)) \skid_buffer[3]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[128]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[96]), - .I4(\skid_buffer[3]_i_4_n_0 ), + (.I0(\skid_buffer[3]_i_4_n_0 ), + .I1(\skid_buffer[3]_i_5_n_0 ), + .I2(\m_payload_i[1]_i_5_n_0 ), + .I3(m_axi_rdata[320]), + .I4(m_axi_rdata[160]), + .I5(\skid_buffer[34]_i_5_n_0 ), .O(\skid_buffer[3]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h0000038000000080)) \skid_buffer[3]_i_4 - (.I0(m_axi_rdata[160]), - .I1(m_axi_rdata[192]), - .I2(m_atarget_enc[3]), - .I3(m_atarget_enc[0]), - .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + (.I0(m_axi_rdata[96]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[0]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[256]), .O(\skid_buffer[3]_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'h00000C0200000002)) + \skid_buffer[3]_i_5 + (.I0(m_axi_rdata[0]), + .I1(m_atarget_enc[0]), + .I2(m_atarget_enc[1]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[288]), + .O(\skid_buffer[3]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF4F44)) \skid_buffer[4]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), + (.I0(\skid_buffer[34]_i_2_n_0 ), .I1(m_axi_rdata[33]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[65]), + .I2(\skid_buffer[32]_i_6_n_0 ), + .I3(m_axi_rdata[129]), .I4(\skid_buffer[4]_i_2_n_0 ), .I5(\skid_buffer[4]_i_3_n_0 ), - .O(aa_rmesg[4])); + .O(\skid_buffer[4]_i_1_n_0 )); LUT6 #( - .INIT(64'hFFFFF888F888F888)) + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[4]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[257]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[225]), - .I4(m_axi_rdata[1]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_axi_rdata[193]), + .I1(\m_payload_i_reg[2]_0 ), + .I2(m_axi_rdata[225]), + .I3(\m_payload_i_reg[2]_1 ), + .I4(\skid_buffer[31]_i_2_n_0 ), + .I5(m_axi_rdata[65]), .O(\skid_buffer[4]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'hEFEEEFEEFFFFEFEE)) \skid_buffer[4]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[129]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[97]), - .I4(\skid_buffer[4]_i_4_n_0 ), + (.I0(\skid_buffer[4]_i_4_n_0 ), + .I1(\skid_buffer[4]_i_5_n_0 ), + .I2(\skid_buffer_reg[30]_0 ), + .I3(m_axi_rdata[289]), + .I4(m_axi_rdata[161]), + .I5(\skid_buffer[34]_i_5_n_0 ), .O(\skid_buffer[4]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h0000038000000080)) \skid_buffer[4]_i_4 - (.I0(m_axi_rdata[161]), - .I1(m_axi_rdata[193]), - .I2(m_atarget_enc[3]), - .I3(m_atarget_enc[0]), - .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + (.I0(m_axi_rdata[97]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[0]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[257]), .O(\skid_buffer[4]_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'h00000C0200000002)) + \skid_buffer[4]_i_5 + (.I0(m_axi_rdata[1]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[0]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[321]), + .O(\skid_buffer[4]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFEFFFEFFFFFFFE)) \skid_buffer[5]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), - .I1(m_axi_rdata[34]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[66]), - .I4(\skid_buffer[5]_i_2_n_0 ), - .I5(\skid_buffer[5]_i_3_n_0 ), - .O(aa_rmesg[5])); - LUT6 #( - .INIT(64'hFFFFF888F888F888)) + (.I0(\skid_buffer[5]_i_2_n_0 ), + .I1(\skid_buffer[5]_i_3_n_0 ), + .I2(\skid_buffer[5]_i_4_n_0 ), + .I3(\skid_buffer[5]_i_5_n_0 ), + .I4(m_axi_rdata[66]), + .I5(\skid_buffer[31]_i_2_n_0 ), + .O(\skid_buffer[5]_i_1_n_0 )); + LUT6 #( + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[5]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[258]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[226]), - .I4(m_axi_rdata[2]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_axi_rdata[34]), + .I1(\skid_buffer[34]_i_2_n_0 ), + .I2(m_axi_rdata[98]), + .I3(\m_payload_i[1]_i_2_n_0 ), + .I4(\skid_buffer[32]_i_6_n_0 ), + .I5(m_axi_rdata[130]), .O(\skid_buffer[5]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'h00200C0000200000)) \skid_buffer[5]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[130]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[98]), - .I4(\skid_buffer[5]_i_4_n_0 ), + (.I0(m_axi_rdata[194]), + .I1(m_atarget_enc[0]), + .I2(m_atarget_enc[1]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[290]), .O(\skid_buffer[5]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h08000C0008000000)) \skid_buffer[5]_i_4 - (.I0(m_axi_rdata[162]), - .I1(m_axi_rdata[194]), + (.I0(m_axi_rdata[226]), + .I1(m_atarget_enc[2]), .I2(m_atarget_enc[3]), .I3(m_atarget_enc[0]), .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + .I5(m_axi_rdata[162]), .O(\skid_buffer[5]_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'h22F2FFFF22F222F2)) + \skid_buffer[5]_i_5 + (.I0(m_axi_rdata[322]), + .I1(\m_payload_i[1]_i_5_n_0 ), + .I2(m_axi_rdata[2]), + .I3(\m_payload_i_reg[1]_0 ), + .I4(\skid_buffer_reg[9]_0 ), + .I5(m_axi_rdata[258]), + .O(\skid_buffer[5]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFEFFFEFFFFFFFE)) \skid_buffer[6]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), - .I1(m_axi_rdata[35]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[67]), - .I4(\skid_buffer[6]_i_2_n_0 ), - .I5(\skid_buffer[6]_i_3_n_0 ), - .O(aa_rmesg[6])); - LUT6 #( - .INIT(64'hFFFFF888F888F888)) + (.I0(\skid_buffer[6]_i_2_n_0 ), + .I1(\skid_buffer[6]_i_3_n_0 ), + .I2(\skid_buffer[6]_i_4_n_0 ), + .I3(\skid_buffer[6]_i_5_n_0 ), + .I4(m_axi_rdata[99]), + .I5(\m_payload_i[1]_i_2_n_0 ), + .O(\skid_buffer[6]_i_1_n_0 )); + LUT6 #( + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[6]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[259]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[227]), - .I4(m_axi_rdata[3]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_axi_rdata[131]), + .I1(\skid_buffer[32]_i_6_n_0 ), + .I2(m_axi_rdata[35]), + .I3(\skid_buffer[34]_i_2_n_0 ), + .I4(\skid_buffer[31]_i_2_n_0 ), + .I5(m_axi_rdata[67]), .O(\skid_buffer[6]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'h0008000300080000)) \skid_buffer[6]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[131]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[99]), - .I4(\skid_buffer[6]_i_4_n_0 ), + (.I0(m_axi_rdata[195]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[0]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[3]), .O(\skid_buffer[6]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h08000C0008000000)) \skid_buffer[6]_i_4 - (.I0(m_axi_rdata[163]), - .I1(m_axi_rdata[195]), + (.I0(m_axi_rdata[227]), + .I1(m_atarget_enc[2]), .I2(m_atarget_enc[3]), .I3(m_atarget_enc[0]), .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + .I5(m_axi_rdata[163]), .O(\skid_buffer[6]_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'h00000ACF00000AC0)) + \skid_buffer[6]_i_5 + (.I0(m_axi_rdata[291]), + .I1(m_axi_rdata[323]), + .I2(m_atarget_enc[1]), + .I3(m_atarget_enc[0]), + .I4(\skid_buffer[28]_i_6_n_0 ), + .I5(m_axi_rdata[259]), + .O(\skid_buffer[6]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFEFFFEFFFFFFFE)) \skid_buffer[7]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), - .I1(m_axi_rdata[36]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[68]), - .I4(\skid_buffer[7]_i_2_n_0 ), - .I5(\skid_buffer[7]_i_3_n_0 ), - .O(aa_rmesg[7])); - LUT6 #( - .INIT(64'hFFFFF888F888F888)) + (.I0(\skid_buffer[7]_i_2_n_0 ), + .I1(\skid_buffer[7]_i_3_n_0 ), + .I2(\skid_buffer[7]_i_4_n_0 ), + .I3(\skid_buffer[7]_i_5_n_0 ), + .I4(m_axi_rdata[68]), + .I5(\skid_buffer[31]_i_2_n_0 ), + .O(\skid_buffer[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[7]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[260]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[228]), - .I4(m_axi_rdata[4]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_axi_rdata[36]), + .I1(\skid_buffer[34]_i_2_n_0 ), + .I2(m_axi_rdata[100]), + .I3(\m_payload_i[1]_i_2_n_0 ), + .I4(\skid_buffer[32]_i_6_n_0 ), + .I5(m_axi_rdata[132]), .O(\skid_buffer[7]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'h00200C0000200000)) \skid_buffer[7]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[132]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[100]), - .I4(\skid_buffer[7]_i_4_n_0 ), + (.I0(m_axi_rdata[196]), + .I1(m_atarget_enc[0]), + .I2(m_atarget_enc[1]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[292]), .O(\skid_buffer[7]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h08000C0008000000)) \skid_buffer[7]_i_4 - (.I0(m_axi_rdata[164]), - .I1(m_axi_rdata[196]), + (.I0(m_axi_rdata[228]), + .I1(m_atarget_enc[2]), .I2(m_atarget_enc[3]), .I3(m_atarget_enc[0]), .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + .I5(m_axi_rdata[164]), .O(\skid_buffer[7]_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'h22F2FFFF22F222F2)) + \skid_buffer[7]_i_5 + (.I0(m_axi_rdata[324]), + .I1(\m_payload_i[1]_i_5_n_0 ), + .I2(m_axi_rdata[4]), + .I3(\m_payload_i_reg[1]_0 ), + .I4(\skid_buffer_reg[9]_0 ), + .I5(m_axi_rdata[260]), + .O(\skid_buffer[7]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFEFFFEFFFFFFFE)) \skid_buffer[8]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), - .I1(m_axi_rdata[37]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[69]), - .I4(\skid_buffer[8]_i_2_n_0 ), - .I5(\skid_buffer[8]_i_3_n_0 ), - .O(aa_rmesg[8])); - LUT6 #( - .INIT(64'hFFFFF888F888F888)) + (.I0(\skid_buffer[8]_i_2_n_0 ), + .I1(\skid_buffer[8]_i_3_n_0 ), + .I2(\skid_buffer[8]_i_4_n_0 ), + .I3(\skid_buffer[8]_i_5_n_0 ), + .I4(m_axi_rdata[69]), + .I5(\skid_buffer[31]_i_2_n_0 ), + .O(\skid_buffer[8]_i_1_n_0 )); + LUT6 #( + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[8]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[261]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[229]), - .I4(m_axi_rdata[5]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_axi_rdata[37]), + .I1(\skid_buffer[34]_i_2_n_0 ), + .I2(m_axi_rdata[101]), + .I3(\m_payload_i[1]_i_2_n_0 ), + .I4(\skid_buffer[32]_i_6_n_0 ), + .I5(m_axi_rdata[133]), .O(\skid_buffer[8]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'h00080C0000080000)) \skid_buffer[8]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[133]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[101]), - .I4(\skid_buffer[8]_i_4_n_0 ), + (.I0(m_axi_rdata[197]), + .I1(m_atarget_enc[1]), + .I2(m_atarget_enc[0]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[325]), .O(\skid_buffer[8]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h00000C2000000020)) \skid_buffer[8]_i_4 - (.I0(m_axi_rdata[165]), - .I1(m_axi_rdata[197]), + (.I0(m_axi_rdata[261]), + .I1(m_atarget_enc[2]), .I2(m_atarget_enc[3]), .I3(m_atarget_enc[0]), .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + .I5(m_axi_rdata[165]), .O(\skid_buffer[8]_i_4_n_0 )); LUT6 #( - .INIT(64'hFFFFFFFFFFFFF888)) + .INIT(64'h22F2FFFF22F222F2)) + \skid_buffer[8]_i_5 + (.I0(m_axi_rdata[293]), + .I1(\skid_buffer_reg[30]_0 ), + .I2(m_axi_rdata[5]), + .I3(\m_payload_i_reg[1]_0 ), + .I4(\m_payload_i_reg[2]_1 ), + .I5(m_axi_rdata[229]), + .O(\skid_buffer[8]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF4F44)) \skid_buffer[9]_i_1 - (.I0(\skid_buffer_reg[1]_0 ), + (.I0(\skid_buffer[34]_i_2_n_0 ), .I1(m_axi_rdata[38]), - .I2(\skid_buffer_reg[1]_1 ), - .I3(m_axi_rdata[70]), + .I2(\m_payload_i[1]_i_2_n_0 ), + .I3(m_axi_rdata[102]), .I4(\skid_buffer[9]_i_2_n_0 ), .I5(\skid_buffer[9]_i_3_n_0 ), - .O(aa_rmesg[9])); + .O(\skid_buffer[9]_i_1_n_0 )); LUT6 #( - .INIT(64'hFFFFF888F888F888)) + .INIT(64'h22F2FFFF22F222F2)) \skid_buffer[9]_i_2 - (.I0(\skid_buffer[34]_i_4_n_0 ), - .I1(m_axi_rdata[262]), - .I2(\skid_buffer[34]_i_5_n_0 ), - .I3(m_axi_rdata[230]), - .I4(m_axi_rdata[6]), - .I5(\skid_buffer[34]_i_6_n_0 ), + (.I0(m_axi_rdata[262]), + .I1(\skid_buffer_reg[9]_0 ), + .I2(m_axi_rdata[198]), + .I3(\m_payload_i_reg[2]_0 ), + .I4(\skid_buffer[31]_i_2_n_0 ), + .I5(m_axi_rdata[70]), .O(\skid_buffer[9]_i_2_n_0 )); - LUT5 #( - .INIT(32'hFFFFF888)) + LUT6 #( + .INIT(64'hEFEEEFEEFFFFEFEE)) \skid_buffer[9]_i_3 - (.I0(\skid_buffer_reg[1]_2 ), - .I1(m_axi_rdata[134]), - .I2(\skid_buffer_reg[1]_3 ), - .I3(m_axi_rdata[102]), - .I4(\skid_buffer[9]_i_4_n_0 ), + (.I0(\skid_buffer[9]_i_4_n_0 ), + .I1(\skid_buffer[9]_i_5_n_0 ), + .I2(\m_payload_i[1]_i_5_n_0 ), + .I3(m_axi_rdata[326]), + .I4(m_axi_rdata[230]), + .I5(\m_payload_i_reg[2]_1 ), .O(\skid_buffer[9]_i_3_n_0 )); LUT6 #( - .INIT(64'h000C0A0000000000)) + .INIT(64'h00000C0800000008)) \skid_buffer[9]_i_4 - (.I0(m_axi_rdata[166]), - .I1(m_axi_rdata[198]), + (.I0(m_axi_rdata[134]), + .I1(m_atarget_enc[2]), .I2(m_atarget_enc[3]), .I3(m_atarget_enc[0]), .I4(m_atarget_enc[1]), - .I5(m_atarget_enc[2]), + .I5(m_axi_rdata[166]), .O(\skid_buffer[9]_i_4_n_0 )); + LUT6 #( + .INIT(64'h00000C0200000002)) + \skid_buffer[9]_i_5 + (.I0(m_axi_rdata[6]), + .I1(m_atarget_enc[0]), + .I2(m_atarget_enc[1]), + .I3(m_atarget_enc[3]), + .I4(m_atarget_enc[2]), + .I5(m_axi_rdata[294]), + .O(\skid_buffer[9]_i_5_n_0 )); FDRE \skid_buffer_reg[0] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[0]), + .D(\skid_buffer[0]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[0] ), .R(1'b0)); FDRE \skid_buffer_reg[10] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[10]), + .D(\skid_buffer[10]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[10] ), .R(1'b0)); FDRE \skid_buffer_reg[11] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[11]), + .D(\skid_buffer[11]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[11] ), .R(1'b0)); FDRE \skid_buffer_reg[12] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[12]), + .D(\skid_buffer[12]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[12] ), .R(1'b0)); FDRE \skid_buffer_reg[13] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[13]), + .D(\skid_buffer[13]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[13] ), .R(1'b0)); FDRE \skid_buffer_reg[14] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[14]), + .D(\skid_buffer[14]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[14] ), .R(1'b0)); FDRE \skid_buffer_reg[15] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[15]), + .D(\skid_buffer[15]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[15] ), .R(1'b0)); FDRE \skid_buffer_reg[16] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[16]), + .D(\skid_buffer[16]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[16] ), .R(1'b0)); FDRE \skid_buffer_reg[17] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[17]), + .D(\skid_buffer[17]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[17] ), .R(1'b0)); FDRE \skid_buffer_reg[18] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[18]), + .D(\skid_buffer[18]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[18] ), .R(1'b0)); FDRE \skid_buffer_reg[19] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[19]), + .D(\skid_buffer[19]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[19] ), .R(1'b0)); FDRE \skid_buffer_reg[1] (.C(aclk), - .CE(aa_rready), - .D(aa_rmesg[1]), + .CE(1'b1), + .D(skid_buffer[1]), .Q(\skid_buffer_reg_n_0_[1] ), .R(1'b0)); FDRE \skid_buffer_reg[20] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[20]), + .D(\skid_buffer[20]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[20] ), .R(1'b0)); FDRE \skid_buffer_reg[21] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[21]), + .D(\skid_buffer[21]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[21] ), .R(1'b0)); FDRE \skid_buffer_reg[22] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[22]), + .D(\skid_buffer[22]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[22] ), .R(1'b0)); FDRE \skid_buffer_reg[23] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[23]), + .D(\skid_buffer[23]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[23] ), .R(1'b0)); FDRE \skid_buffer_reg[24] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[24]), + .D(\skid_buffer[24]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[24] ), .R(1'b0)); FDRE \skid_buffer_reg[25] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[25]), + .D(\skid_buffer[25]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[25] ), .R(1'b0)); FDRE \skid_buffer_reg[26] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[26]), + .D(\skid_buffer[26]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[26] ), .R(1'b0)); FDRE \skid_buffer_reg[27] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[27]), + .D(\skid_buffer[27]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[27] ), .R(1'b0)); FDRE \skid_buffer_reg[28] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[28]), + .D(\skid_buffer[28]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[28] ), .R(1'b0)); FDRE \skid_buffer_reg[29] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[29]), + .D(\skid_buffer[29]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[29] ), .R(1'b0)); FDRE \skid_buffer_reg[2] (.C(aclk), - .CE(aa_rready), - .D(aa_rmesg[2]), + .CE(1'b1), + .D(skid_buffer[2]), .Q(\skid_buffer_reg_n_0_[2] ), .R(1'b0)); FDRE \skid_buffer_reg[30] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[30]), + .D(\skid_buffer[30]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[30] ), .R(1'b0)); FDRE \skid_buffer_reg[31] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[31]), + .D(\skid_buffer[31]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[31] ), .R(1'b0)); FDRE \skid_buffer_reg[32] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[32]), + .D(\skid_buffer[32]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[32] ), .R(1'b0)); FDRE \skid_buffer_reg[33] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[33]), + .D(\skid_buffer[33]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[33] ), .R(1'b0)); FDRE \skid_buffer_reg[34] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[34]), + .D(\skid_buffer[34]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[34] ), .R(1'b0)); FDRE \skid_buffer_reg[3] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[3]), + .D(\skid_buffer[3]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[3] ), .R(1'b0)); FDRE \skid_buffer_reg[4] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[4]), + .D(\skid_buffer[4]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[4] ), .R(1'b0)); FDRE \skid_buffer_reg[5] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[5]), + .D(\skid_buffer[5]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[5] ), .R(1'b0)); FDRE \skid_buffer_reg[6] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[6]), + .D(\skid_buffer[6]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[6] ), .R(1'b0)); FDRE \skid_buffer_reg[7] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[7]), + .D(\skid_buffer[7]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[7] ), .R(1'b0)); FDRE \skid_buffer_reg[8] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[8]), + .D(\skid_buffer[8]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[8] ), .R(1'b0)); FDRE \skid_buffer_reg[9] (.C(aclk), .CE(aa_rready), - .D(aa_rmesg[9]), + .D(\skid_buffer[9]_i_1_n_0 ), .Q(\skid_buffer_reg_n_0_[9] ), .R(1'b0)); endmodule diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0_sim_netlist.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0_sim_netlist.vhdl index 8a23494..da846aa 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0_sim_netlist.vhdl +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 --- Date : Fri Feb 24 16:02:41 2017 +-- Date : Sat Mar 04 18:54:14 2017 -- Host : WK73 running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim --- c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0_sim_netlist.vhdl +-- C:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0_sim_netlist.vhdl -- Design : Arty_Z7_20_xbar_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. @@ -16,71 +16,73 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_addr_arbiter_sasd is port ( + reset : out STD_LOGIC; m_valid_i : out STD_LOGIC; - SR : out STD_LOGIC_VECTOR ( 0 to 0 ); aa_grant_rnw : out STD_LOGIC; + \m_atarget_enc_reg[1]\ : out STD_LOGIC; \m_atarget_enc_reg[0]\ : out STD_LOGIC; \m_atarget_enc_reg[3]\ : out STD_LOGIC; + s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_ready_d0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_ready_d0_0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + \m_ready_d_reg[2]\ : out STD_LOGIC; + s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_bready : out STD_LOGIC_VECTOR ( 10 downto 0 ); \m_ready_d_reg[1]\ : out STD_LOGIC; + \gen_axilite.s_axi_bvalid_i_reg\ : out STD_LOGIC; + m_axi_awvalid : out STD_LOGIC_VECTOR ( 10 downto 0 ); + \gen_axilite.s_axi_bvalid_i_reg_0\ : out STD_LOGIC; + m_axi_wvalid : out STD_LOGIC_VECTOR ( 10 downto 0 ); + \gen_axilite.s_axi_bvalid_i_reg_1\ : out STD_LOGIC; + s_ready_i_reg : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); \m_ready_d_reg[0]\ : out STD_LOGIC; - \gen_axilite.s_axi_bvalid_i_reg\ : out STD_LOGIC; \m_ready_d_reg[1]_0\ : out STD_LOGIC; \m_ready_d_reg[0]_0\ : out STD_LOGIC; + m_axi_arvalid : out STD_LOGIC_VECTOR ( 10 downto 0 ); + \gen_axilite.s_axi_rvalid_i_reg\ : out STD_LOGIC; s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 ); - D : out STD_LOGIC_VECTOR ( 9 downto 0 ); - \m_atarget_enc_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); - Q : out STD_LOGIC_VECTOR ( 34 downto 0 ); s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 ); - mi_arready_mux : out STD_LOGIC; - \m_ready_d_reg[1]_1\ : out STD_LOGIC; - \m_ready_d_reg[1]_2\ : out STD_LOGIC; - m_axi_arvalid : out STD_LOGIC_VECTOR ( 8 downto 0 ); - aa_rvalid : out STD_LOGIC; - aa_awready : out STD_LOGIC; - mi_awready_mux : out STD_LOGIC; - m_axi_bready : out STD_LOGIC_VECTOR ( 8 downto 0 ); - s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 ); - aa_wready : out STD_LOGIC; - s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); - aa_bvalid : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); - p_4_in : out STD_LOGIC; - m_axi_wvalid : out STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_awvalid : out STD_LOGIC_VECTOR ( 8 downto 0 ); - \gen_axilite.s_axi_bvalid_i_reg_0\ : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 11 downto 0 ); + \m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 34 downto 0 ); + \m_atarget_enc_reg[2]\ : out STD_LOGIC; + \gen_axilite.s_axi_bvalid_i_reg_2\ : out STD_LOGIC; aclk : in STD_LOGIC; - m_ready_d : in STD_LOGIC_VECTOR ( 1 downto 0 ); - m_atarget_enc : in STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); - sr_rvalid : in STD_LOGIC; - m_ready_d_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ); - aresetn_d : in STD_LOGIC; - m_axi_arready : in STD_LOGIC_VECTOR ( 6 downto 0 ); - \gen_axilite.s_axi_arready_i_reg\ : in STD_LOGIC; - \m_atarget_hot_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); - m_axi_rvalid : in STD_LOGIC_VECTOR ( 6 downto 0 ); - \gen_axilite.s_axi_rvalid_i_reg\ : in STD_LOGIC; - \gen_axilite.s_axi_bvalid_i_reg_1\ : in STD_LOGIC; - s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); - \gen_axilite.s_axi_awready_i_reg\ : in STD_LOGIC; - s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); - \gen_axilite.s_axi_awready_i_reg_0\ : in STD_LOGIC; - m_axi_awready : in STD_LOGIC_VECTOR ( 6 downto 0 ); + m_ready_d : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_atarget_enc_reg[2]_0\ : in STD_LOGIC; - m_axi_wready : in STD_LOGIC_VECTOR ( 6 downto 0 ); + \m_payload_i_reg[0]\ : in STD_LOGIC; + \m_ready_d_reg[0]_1\ : in STD_LOGIC; \m_atarget_enc_reg[2]_1\ : in STD_LOGIC; \m_atarget_enc_reg[2]_2\ : in STD_LOGIC; - m_axi_bvalid : in STD_LOGIC_VECTOR ( 6 downto 0 ); + \m_atarget_enc_reg[3]_0\ : in STD_LOGIC; + s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + \m_atarget_enc_reg[3]_1\ : in STD_LOGIC; \m_atarget_enc_reg[2]_3\ : in STD_LOGIC; - s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); + \m_atarget_enc_reg[2]_4\ : in STD_LOGIC; + m_axi_awready : in STD_LOGIC_VECTOR ( 4 downto 0 ); + m_atarget_enc : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \m_atarget_enc_reg[2]_5\ : in STD_LOGIC; + \m_atarget_enc_reg[3]_2\ : in STD_LOGIC; + \m_atarget_enc_reg[3]_3\ : in STD_LOGIC; + m_ready_d_1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); + sr_rvalid : in STD_LOGIC; + aresetn_d : in STD_LOGIC; + \m_payload_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \m_atarget_enc_reg[2]_6\ : in STD_LOGIC; + \m_atarget_enc_reg[2]_7\ : in STD_LOGIC; + \m_atarget_enc_reg[3]_4\ : in STD_LOGIC; + \m_atarget_enc_reg[2]_8\ : in STD_LOGIC; s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); - mi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); mi_wready : in STD_LOGIC_VECTOR ( 0 to 0 ); - \m_ready_d_reg[0]_1\ : in STD_LOGIC; + mi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; @@ -88,191 +90,199 @@ entity Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_addr_arbiter_sasd is end Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_addr_arbiter_sasd; architecture STRUCTURE of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_addr_arbiter_sasd is - signal \^q\ : STD_LOGIC_VECTOR ( 34 downto 0 ); - signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \^aa_awready\ : STD_LOGIC; - signal \^aa_bvalid\ : STD_LOGIC; signal aa_grant_any : STD_LOGIC; signal \^aa_grant_rnw\ : STD_LOGIC; - signal \^aa_wready\ : STD_LOGIC; - signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\ : STD_LOGIC; - signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\ : STD_LOGIC; - signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2\ : STD_LOGIC; - signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\ : STD_LOGIC; - signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_4\ : STD_LOGIC; - signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_5\ : STD_LOGIC; - signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_6\ : STD_LOGIC; - signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_7\ : STD_LOGIC; - signal \gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3__4\ : STD_LOGIC; - signal \gen_addr_decoder.addr_decoder_inst/gen_target[7].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\ : STD_LOGIC; - signal \gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\ : STD_LOGIC; - signal \gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\ : STD_LOGIC; signal \^gen_axilite.s_axi_bvalid_i_reg\ : STD_LOGIC; + signal \^gen_axilite.s_axi_bvalid_i_reg_0\ : STD_LOGIC; + signal \^gen_axilite.s_axi_bvalid_i_reg_1\ : STD_LOGIC; signal \gen_no_arbiter.grant_rnw_i_1_n_0\ : STD_LOGIC; signal \gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0\ : STD_LOGIC; - signal \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0\ : STD_LOGIC; signal \gen_no_arbiter.m_valid_i_i_1_n_0\ : STD_LOGIC; - signal \m_atarget_enc[2]_i_3_n_0\ : STD_LOGIC; + signal \gen_no_arbiter.m_valid_i_i_2_n_0\ : STD_LOGIC; + signal \m_atarget_enc[0]_i_2_n_0\ : STD_LOGIC; + signal \m_atarget_enc[0]_i_3_n_0\ : STD_LOGIC; + signal \m_atarget_enc[1]_i_2_n_0\ : STD_LOGIC; + signal \m_atarget_enc[1]_i_3_n_0\ : STD_LOGIC; + signal \m_atarget_enc[3]_i_2_n_0\ : STD_LOGIC; + signal \m_atarget_enc[3]_i_3_n_0\ : STD_LOGIC; + signal \m_atarget_enc[3]_i_4_n_0\ : STD_LOGIC; + signal \m_atarget_hot[0]_i_2_n_0\ : STD_LOGIC; + signal \m_atarget_hot[10]_i_2_n_0\ : STD_LOGIC; + signal \m_atarget_hot[10]_i_3_n_0\ : STD_LOGIC; + signal \m_atarget_hot[11]_i_2_n_0\ : STD_LOGIC; + signal \m_atarget_hot[11]_i_3_n_0\ : STD_LOGIC; + signal \m_atarget_hot[11]_i_4_n_0\ : STD_LOGIC; + signal \m_atarget_hot[1]_i_2_n_0\ : STD_LOGIC; + signal \m_atarget_hot[2]_i_2_n_0\ : STD_LOGIC; + signal \m_atarget_hot[3]_i_2_n_0\ : STD_LOGIC; + signal \m_atarget_hot[3]_i_3_n_0\ : STD_LOGIC; + signal \m_atarget_hot[4]_i_2_n_0\ : STD_LOGIC; + signal \m_atarget_hot[4]_i_3_n_0\ : STD_LOGIC; + signal \m_atarget_hot[5]_i_2_n_0\ : STD_LOGIC; + signal \m_atarget_hot[6]_i_2_n_0\ : STD_LOGIC; + signal \m_atarget_hot[7]_i_2_n_0\ : STD_LOGIC; signal \m_atarget_hot[8]_i_2_n_0\ : STD_LOGIC; - signal \m_atarget_hot[9]_i_3_n_0\ : STD_LOGIC; - signal \m_atarget_hot[9]_i_6_n_0\ : STD_LOGIC; - signal \m_atarget_hot[9]_i_7_n_0\ : STD_LOGIC; - signal \m_atarget_hot[9]_i_8_n_0\ : STD_LOGIC; - signal \m_ready_d[1]_i_7_n_0\ : STD_LOGIC; - signal \m_ready_d[1]_i_8_n_0\ : STD_LOGIC; - signal \m_ready_d[2]_i_10_n_0\ : STD_LOGIC; - signal \m_ready_d[2]_i_11_n_0\ : STD_LOGIC; - signal \m_ready_d[2]_i_4_n_0\ : STD_LOGIC; + signal \m_atarget_hot[9]_i_2_n_0\ : STD_LOGIC; + signal \^m_axi_arprot[2]\ : STD_LOGIC_VECTOR ( 34 downto 0 ); + signal \^m_ready_d0\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^m_ready_d0_0\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \m_ready_d[2]_i_6_n_0\ : STD_LOGIC; signal \m_ready_d[2]_i_7_n_0\ : STD_LOGIC; - signal \^m_ready_d_reg[0]\ : STD_LOGIC; + signal \m_ready_d[2]_i_8_n_0\ : STD_LOGIC; signal \^m_ready_d_reg[0]_0\ : STD_LOGIC; - signal \^m_ready_d_reg[1]\ : STD_LOGIC; signal \^m_ready_d_reg[1]_0\ : STD_LOGIC; - signal \^m_ready_d_reg[1]_1\ : STD_LOGIC; - signal \^m_ready_d_reg[1]_2\ : STD_LOGIC; + signal \^m_ready_d_reg[2]\ : STD_LOGIC; signal \^m_valid_i\ : STD_LOGIC; - signal m_valid_i_i_3_n_0 : STD_LOGIC; - signal m_valid_i_i_4_n_0 : STD_LOGIC; - signal m_valid_i_i_5_n_0 : STD_LOGIC; - signal m_valid_i_i_6_n_0 : STD_LOGIC; - signal match : STD_LOGIC; - signal \^mi_awready_mux\ : STD_LOGIC; + signal m_valid_i4_out : STD_LOGIC; signal p_0_in1_in : STD_LOGIC; - signal \p_0_out__0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal p_3_in : STD_LOGIC; - signal \^p_4_in\ : STD_LOGIC; + signal \^reset\ : STD_LOGIC; signal s_amesg : STD_LOGIC_VECTOR ( 48 downto 1 ); signal \s_arvalid_reg[0]_i_1_n_0\ : STD_LOGIC; signal \s_arvalid_reg_reg_n_0_[0]\ : STD_LOGIC; signal s_awvalid_reg : STD_LOGIC; signal \s_awvalid_reg[0]_i_1_n_0\ : STD_LOGIC; - signal \s_axi_bvalid[0]_INST_0_i_2_n_0\ : STD_LOGIC; - signal \s_axi_bvalid[0]_INST_0_i_4_n_0\ : STD_LOGIC; - signal \s_axi_bvalid[0]_INST_0_i_5_n_0\ : STD_LOGIC; + signal \s_axi_wready[0]_INST_0_i_1_n_0\ : STD_LOGIC; signal \s_axi_wready[0]_INST_0_i_2_n_0\ : STD_LOGIC; - signal \s_axi_wready[0]_INST_0_i_4_n_0\ : STD_LOGIC; - signal \s_axi_wready[0]_INST_0_i_5_n_0\ : STD_LOGIC; signal s_ready_i : STD_LOGIC; - signal s_ready_i0 : STD_LOGIC; - signal target_mi_enc : STD_LOGIC_VECTOR ( 3 downto 0 ); attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \gen_axilite.s_axi_bvalid_i_i_2\ : label is "soft_lutpair2"; - attribute SOFT_HLUTNM of \gen_axilite.s_axi_bvalid_i_i_3\ : label is "soft_lutpair0"; - attribute SOFT_HLUTNM of \gen_axilite.s_axi_bvalid_i_i_4\ : label is "soft_lutpair15"; - attribute SOFT_HLUTNM of \gen_no_arbiter.m_grant_hot_i[0]_i_2\ : label is "soft_lutpair5"; - attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_1\ : label is "soft_lutpair5"; - attribute SOFT_HLUTNM of \m_atarget_enc[0]_i_2\ : label is "soft_lutpair6"; - attribute SOFT_HLUTNM of \m_atarget_hot[3]_i_1\ : label is "soft_lutpair20"; - attribute SOFT_HLUTNM of \m_atarget_hot[4]_i_1\ : label is "soft_lutpair20"; - attribute SOFT_HLUTNM of \m_atarget_hot[8]_i_2\ : label is "soft_lutpair6"; - attribute SOFT_HLUTNM of \m_atarget_hot[9]_i_6\ : label is "soft_lutpair7"; - attribute SOFT_HLUTNM of \m_atarget_hot[9]_i_8\ : label is "soft_lutpair7"; - attribute SOFT_HLUTNM of \m_axi_arvalid[0]_INST_0\ : label is "soft_lutpair14"; - attribute SOFT_HLUTNM of \m_axi_arvalid[1]_INST_0\ : label is "soft_lutpair13"; - attribute SOFT_HLUTNM of \m_axi_arvalid[2]_INST_0\ : label is "soft_lutpair13"; - attribute SOFT_HLUTNM of \m_axi_arvalid[3]_INST_0\ : label is "soft_lutpair12"; - attribute SOFT_HLUTNM of \m_axi_arvalid[4]_INST_0\ : label is "soft_lutpair12"; - attribute SOFT_HLUTNM of \m_axi_arvalid[5]_INST_0\ : label is "soft_lutpair11"; - attribute SOFT_HLUTNM of \m_axi_arvalid[6]_INST_0\ : label is "soft_lutpair11"; - attribute SOFT_HLUTNM of \m_axi_arvalid[7]_INST_0\ : label is "soft_lutpair10"; - attribute SOFT_HLUTNM of \m_axi_arvalid[8]_INST_0\ : label is "soft_lutpair9"; - attribute SOFT_HLUTNM of \m_axi_awvalid[0]_INST_0\ : label is "soft_lutpair14"; - attribute SOFT_HLUTNM of \m_axi_awvalid[1]_INST_0\ : label is "soft_lutpair16"; - attribute SOFT_HLUTNM of \m_axi_awvalid[2]_INST_0\ : label is "soft_lutpair17"; - attribute SOFT_HLUTNM of \m_axi_awvalid[3]_INST_0\ : label is "soft_lutpair18"; - attribute SOFT_HLUTNM of \m_axi_awvalid[4]_INST_0\ : label is "soft_lutpair19"; - attribute SOFT_HLUTNM of \m_axi_awvalid[5]_INST_0\ : label is "soft_lutpair18"; - attribute SOFT_HLUTNM of \m_axi_awvalid[6]_INST_0\ : label is "soft_lutpair17"; - attribute SOFT_HLUTNM of \m_axi_awvalid[7]_INST_0\ : label is "soft_lutpair16"; - attribute SOFT_HLUTNM of \m_axi_awvalid[8]_INST_0\ : label is "soft_lutpair19"; - attribute SOFT_HLUTNM of \m_axi_bready[2]_INST_0\ : label is "soft_lutpair3"; - attribute SOFT_HLUTNM of \m_axi_bready[3]_INST_0\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \gen_axilite.s_axi_bvalid_i_i_2\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \gen_axilite.s_axi_bvalid_i_i_3\ : label is "soft_lutpair22"; + attribute SOFT_HLUTNM of \gen_axilite.s_axi_bvalid_i_i_4\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \gen_axilite.s_axi_rvalid_i_i_2\ : label is "soft_lutpair28"; + attribute SOFT_HLUTNM of \gen_no_arbiter.m_valid_i_i_1\ : label is "soft_lutpair22"; + attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_1\ : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of \m_atarget_enc[0]_i_1\ : label is "soft_lutpair27"; + attribute SOFT_HLUTNM of \m_atarget_enc[0]_i_2\ : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \m_atarget_enc[1]_i_3\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \m_atarget_enc[3]_i_2\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \m_atarget_hot[0]_i_1\ : label is "soft_lutpair9"; + attribute SOFT_HLUTNM of \m_atarget_hot[10]_i_1\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \m_atarget_hot[11]_i_1\ : label is "soft_lutpair29"; + attribute SOFT_HLUTNM of \m_atarget_hot[11]_i_3\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \m_atarget_hot[1]_i_1\ : label is "soft_lutpair24"; + attribute SOFT_HLUTNM of \m_atarget_hot[2]_i_1\ : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of \m_atarget_hot[3]_i_1\ : label is "soft_lutpair26"; + attribute SOFT_HLUTNM of \m_atarget_hot[3]_i_2\ : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \m_atarget_hot[4]_i_1\ : label is "soft_lutpair9"; + attribute SOFT_HLUTNM of \m_atarget_hot[4]_i_2\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \m_atarget_hot[5]_i_1\ : label is "soft_lutpair27"; + attribute SOFT_HLUTNM of \m_atarget_hot[6]_i_1\ : label is "soft_lutpair26"; + attribute SOFT_HLUTNM of \m_atarget_hot[7]_i_1\ : label is "soft_lutpair24"; + attribute SOFT_HLUTNM of \m_atarget_hot[8]_i_1\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \m_atarget_hot[9]_i_1\ : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of \m_axi_arvalid[0]_INST_0\ : label is "soft_lutpair20"; + attribute SOFT_HLUTNM of \m_axi_arvalid[10]_INST_0\ : label is "soft_lutpair12"; + attribute SOFT_HLUTNM of \m_axi_arvalid[1]_INST_0\ : label is "soft_lutpair21"; + attribute SOFT_HLUTNM of \m_axi_arvalid[2]_INST_0\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \m_axi_arvalid[3]_INST_0\ : label is "soft_lutpair17"; + attribute SOFT_HLUTNM of \m_axi_arvalid[4]_INST_0\ : label is "soft_lutpair16"; + attribute SOFT_HLUTNM of \m_axi_arvalid[5]_INST_0\ : label is "soft_lutpair19"; + attribute SOFT_HLUTNM of \m_axi_arvalid[6]_INST_0\ : label is "soft_lutpair15"; + attribute SOFT_HLUTNM of \m_axi_arvalid[7]_INST_0\ : label is "soft_lutpair14"; + attribute SOFT_HLUTNM of \m_axi_arvalid[8]_INST_0\ : label is "soft_lutpair13"; + attribute SOFT_HLUTNM of \m_axi_arvalid[9]_INST_0\ : label is "soft_lutpair11"; + attribute SOFT_HLUTNM of \m_axi_awvalid[0]_INST_0\ : label is "soft_lutpair20"; + attribute SOFT_HLUTNM of \m_axi_awvalid[10]_INST_0\ : label is "soft_lutpair12"; + attribute SOFT_HLUTNM of \m_axi_awvalid[1]_INST_0\ : label is "soft_lutpair21"; + attribute SOFT_HLUTNM of \m_axi_awvalid[2]_INST_0\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \m_axi_awvalid[3]_INST_0\ : label is "soft_lutpair17"; + attribute SOFT_HLUTNM of \m_axi_awvalid[4]_INST_0\ : label is "soft_lutpair16"; + attribute SOFT_HLUTNM of \m_axi_awvalid[5]_INST_0\ : label is "soft_lutpair19"; + attribute SOFT_HLUTNM of \m_axi_awvalid[6]_INST_0\ : label is "soft_lutpair15"; + attribute SOFT_HLUTNM of \m_axi_awvalid[7]_INST_0\ : label is "soft_lutpair14"; + attribute SOFT_HLUTNM of \m_axi_awvalid[8]_INST_0\ : label is "soft_lutpair13"; + attribute SOFT_HLUTNM of \m_axi_awvalid[9]_INST_0\ : label is "soft_lutpair11"; + attribute SOFT_HLUTNM of \m_axi_bready[10]_INST_0\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \m_axi_wvalid[0]_INST_0\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \m_axi_wvalid[1]_INST_0\ : label is "soft_lutpair1"; - attribute SOFT_HLUTNM of \m_axi_wvalid[5]_INST_0\ : label is "soft_lutpair0"; - attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair4"; - attribute SOFT_HLUTNM of \m_ready_d[0]_i_2\ : label is "soft_lutpair4"; - attribute SOFT_HLUTNM of \m_ready_d[0]_i_2__0\ : label is "soft_lutpair3"; - attribute SOFT_HLUTNM of \m_ready_d[1]_i_2\ : label is "soft_lutpair9"; - attribute SOFT_HLUTNM of \m_ready_d[1]_i_2__0\ : label is "soft_lutpair1"; - attribute SOFT_HLUTNM of \m_ready_d[1]_i_7\ : label is "soft_lutpair10"; - attribute SOFT_HLUTNM of m_valid_i_i_5 : label is "soft_lutpair15"; - attribute SOFT_HLUTNM of \s_arvalid_reg[0]_i_1\ : label is "soft_lutpair8"; - attribute SOFT_HLUTNM of \s_axi_awready[0]_INST_0\ : label is "soft_lutpair8"; - attribute SOFT_HLUTNM of \s_axi_rvalid[0]_INST_0\ : label is "soft_lutpair21"; - attribute SOFT_HLUTNM of \s_axi_wready[0]_INST_0\ : label is "soft_lutpair21"; + attribute SOFT_HLUTNM of \m_axi_wvalid[5]_INST_0\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of \m_ready_d[0]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of m_valid_i_i_7 : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of \s_arvalid_reg[0]_i_1\ : label is "soft_lutpair10"; + attribute SOFT_HLUTNM of \s_axi_arready[0]_INST_0\ : label is "soft_lutpair28"; + attribute SOFT_HLUTNM of \s_axi_awready[0]_INST_0\ : label is "soft_lutpair10"; + attribute SOFT_HLUTNM of \s_axi_bvalid[0]_INST_0\ : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of \s_axi_wready[0]_INST_0\ : label is "soft_lutpair29"; + attribute SOFT_HLUTNM of \s_axi_wready[0]_INST_0_i_2\ : label is "soft_lutpair2"; begin - Q(34 downto 0) <= \^q\(34 downto 0); - SR(0) <= \^sr\(0); - aa_awready <= \^aa_awready\; - aa_bvalid <= \^aa_bvalid\; aa_grant_rnw <= \^aa_grant_rnw\; - aa_wready <= \^aa_wready\; \gen_axilite.s_axi_bvalid_i_reg\ <= \^gen_axilite.s_axi_bvalid_i_reg\; - \m_ready_d_reg[0]\ <= \^m_ready_d_reg[0]\; + \gen_axilite.s_axi_bvalid_i_reg_0\ <= \^gen_axilite.s_axi_bvalid_i_reg_0\; + \gen_axilite.s_axi_bvalid_i_reg_1\ <= \^gen_axilite.s_axi_bvalid_i_reg_1\; + \m_axi_arprot[2]\(34 downto 0) <= \^m_axi_arprot[2]\(34 downto 0); + m_ready_d0(0) <= \^m_ready_d0\(0); + m_ready_d0_0(0) <= \^m_ready_d0_0\(0); \m_ready_d_reg[0]_0\ <= \^m_ready_d_reg[0]_0\; - \m_ready_d_reg[1]\ <= \^m_ready_d_reg[1]\; \m_ready_d_reg[1]_0\ <= \^m_ready_d_reg[1]_0\; - \m_ready_d_reg[1]_1\ <= \^m_ready_d_reg[1]_1\; - \m_ready_d_reg[1]_2\ <= \^m_ready_d_reg[1]_2\; + \m_ready_d_reg[2]\ <= \^m_ready_d_reg[2]\; m_valid_i <= \^m_valid_i\; - mi_awready_mux <= \^mi_awready_mux\; - p_4_in <= \^p_4_in\; + reset <= \^reset\; \gen_axilite.s_axi_bvalid_i_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"7C4C4C4C4C4C4C4C" + INIT => X"AFAFAFAF30000000" ) port map ( - I0 => p_3_in, - I1 => mi_bvalid(0), - I2 => \m_atarget_hot_reg[9]\(9), - I3 => \^p_4_in\, - I4 => \^gen_axilite.s_axi_bvalid_i_reg\, - I5 => mi_wready(0), - O => \gen_axilite.s_axi_bvalid_i_reg_0\ + I0 => \^gen_axilite.s_axi_bvalid_i_reg\, + I1 => \^gen_axilite.s_axi_bvalid_i_reg_0\, + I2 => Q(11), + I3 => \^gen_axilite.s_axi_bvalid_i_reg_1\, + I4 => mi_wready(0), + I5 => mi_bvalid(0), + O => \gen_axilite.s_axi_bvalid_i_reg_2\ ); \gen_axilite.s_axi_bvalid_i_i_2\: unisim.vcomponents.LUT4 generic map( - INIT => X"0020" + INIT => X"FBFF" ) port map ( - I0 => s_axi_bready(0), - I1 => m_ready_d_0(0), - I2 => \^m_valid_i\, - I3 => \^aa_grant_rnw\, - O => p_3_in + I0 => \^aa_grant_rnw\, + I1 => \^m_valid_i\, + I2 => m_ready_d(0), + I3 => s_axi_bready(0), + O => \^gen_axilite.s_axi_bvalid_i_reg\ ); -\gen_axilite.s_axi_bvalid_i_i_3\: unisim.vcomponents.LUT4 +\gen_axilite.s_axi_bvalid_i_i_3\: unisim.vcomponents.LUT3 generic map( - INIT => X"0400" + INIT => X"FB" ) port map ( - I0 => m_ready_d_0(1), + I0 => m_ready_d(2), I1 => \^m_valid_i\, I2 => \^aa_grant_rnw\, - I3 => s_axi_wvalid(0), - O => \^p_4_in\ + O => \^gen_axilite.s_axi_bvalid_i_reg_0\ + ); +\gen_axilite.s_axi_bvalid_i_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0040" + ) + port map ( + I0 => m_ready_d(1), + I1 => s_axi_wvalid(0), + I2 => \^m_valid_i\, + I3 => \^aa_grant_rnw\, + O => \^gen_axilite.s_axi_bvalid_i_reg_1\ ); -\gen_axilite.s_axi_bvalid_i_i_4\: unisim.vcomponents.LUT3 +\gen_axilite.s_axi_rvalid_i_i_2\: unisim.vcomponents.LUT3 generic map( - INIT => X"04" + INIT => X"40" ) port map ( - I0 => \^aa_grant_rnw\, + I0 => m_ready_d_1(1), I1 => \^m_valid_i\, - I2 => m_ready_d_0(2), - O => \^gen_axilite.s_axi_bvalid_i_reg\ + I2 => \^aa_grant_rnw\, + O => \gen_axilite.s_axi_rvalid_i_reg\ ); \gen_no_arbiter.grant_rnw_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFF4700000044" + INIT => X"FDFDFCFF01010000" ) port map ( I0 => s_awvalid_reg, - I1 => s_axi_arvalid(0), - I2 => s_axi_awvalid(0), - I3 => aa_grant_any, - I4 => \^m_valid_i\, + I1 => \^m_valid_i\, + I2 => aa_grant_any, + I3 => s_axi_awvalid(0), + I4 => s_axi_arvalid(0), I5 => \^aa_grant_rnw\, O => \gen_no_arbiter.grant_rnw_i_1_n_0\ ); @@ -282,270 +292,270 @@ begin CE => '1', D => \gen_no_arbiter.grant_rnw_i_1_n_0\, Q => \^aa_grant_rnw\, - R => \^sr\(0) + R => \^reset\ ); \gen_no_arbiter.m_amesg_i[10]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(9), - I1 => s_axi_awaddr(9), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(9), O => s_amesg(10) ); \gen_no_arbiter.m_amesg_i[11]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(10), - I1 => s_axi_awaddr(10), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(10), O => s_amesg(11) ); \gen_no_arbiter.m_amesg_i[12]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(11), - I1 => s_axi_awaddr(11), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(11), O => s_amesg(12) ); \gen_no_arbiter.m_amesg_i[13]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(12), - I1 => s_axi_awaddr(12), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(12), O => s_amesg(13) ); \gen_no_arbiter.m_amesg_i[14]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(13), - I1 => s_axi_awaddr(13), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(13), O => s_amesg(14) ); \gen_no_arbiter.m_amesg_i[15]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(14), - I1 => s_axi_awaddr(14), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(14), O => s_amesg(15) ); \gen_no_arbiter.m_amesg_i[16]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(15), - I1 => s_axi_awaddr(15), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(15), O => s_amesg(16) ); \gen_no_arbiter.m_amesg_i[17]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(16), - I1 => s_axi_awaddr(16), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(16), O => s_amesg(17) ); \gen_no_arbiter.m_amesg_i[18]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(17), - I1 => s_axi_awaddr(17), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(17), O => s_amesg(18) ); \gen_no_arbiter.m_amesg_i[19]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(18), - I1 => s_axi_awaddr(18), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(18), O => s_amesg(19) ); \gen_no_arbiter.m_amesg_i[1]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(0), - I1 => s_axi_awaddr(0), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(0), O => s_amesg(1) ); \gen_no_arbiter.m_amesg_i[20]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(19), - I1 => s_axi_awaddr(19), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(19), O => s_amesg(20) ); \gen_no_arbiter.m_amesg_i[21]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(20), - I1 => s_axi_awaddr(20), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(20), O => s_amesg(21) ); \gen_no_arbiter.m_amesg_i[22]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(21), - I1 => s_axi_awaddr(21), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(21), O => s_amesg(22) ); \gen_no_arbiter.m_amesg_i[23]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(22), - I1 => s_axi_awaddr(22), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(22), O => s_amesg(23) ); \gen_no_arbiter.m_amesg_i[24]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(23), - I1 => s_axi_awaddr(23), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(23), O => s_amesg(24) ); \gen_no_arbiter.m_amesg_i[25]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(24), - I1 => s_axi_awaddr(24), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(24), O => s_amesg(25) ); \gen_no_arbiter.m_amesg_i[26]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(25), - I1 => s_axi_awaddr(25), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(25), O => s_amesg(26) ); \gen_no_arbiter.m_amesg_i[27]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(26), - I1 => s_axi_awaddr(26), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(26), O => s_amesg(27) ); \gen_no_arbiter.m_amesg_i[28]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(27), - I1 => s_axi_awaddr(27), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(27), O => s_amesg(28) ); \gen_no_arbiter.m_amesg_i[29]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(28), - I1 => s_axi_awaddr(28), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(28), O => s_amesg(29) ); \gen_no_arbiter.m_amesg_i[2]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(1), - I1 => s_axi_awaddr(1), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(1), O => s_amesg(2) ); \gen_no_arbiter.m_amesg_i[30]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(29), - I1 => s_axi_awaddr(29), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(29), O => s_amesg(30) ); \gen_no_arbiter.m_amesg_i[31]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(30), - I1 => s_axi_awaddr(30), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(30), O => s_amesg(31) ); \gen_no_arbiter.m_amesg_i[32]_i_1\: unisim.vcomponents.LUT1 @@ -554,7 +564,7 @@ begin ) port map ( I0 => aresetn_d, - O => \^sr\(0) + O => \^reset\ ); \gen_no_arbiter.m_amesg_i[32]_i_2\: unisim.vcomponents.LUT1 generic map( @@ -566,123 +576,123 @@ begin ); \gen_no_arbiter.m_amesg_i[32]_i_3\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(31), - I1 => s_axi_awaddr(31), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(31), O => s_amesg(32) ); \gen_no_arbiter.m_amesg_i[3]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(2), - I1 => s_axi_awaddr(2), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(2), O => s_amesg(3) ); \gen_no_arbiter.m_amesg_i[46]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_arprot(0), - I1 => s_axi_awprot(0), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awprot(0), O => s_amesg(46) ); \gen_no_arbiter.m_amesg_i[47]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_arprot(1), - I1 => s_axi_awprot(1), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awprot(1), O => s_amesg(47) ); \gen_no_arbiter.m_amesg_i[48]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_arprot(2), - I1 => s_axi_awprot(2), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awprot(2), O => s_amesg(48) ); \gen_no_arbiter.m_amesg_i[4]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(3), - I1 => s_axi_awaddr(3), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(3), O => s_amesg(4) ); \gen_no_arbiter.m_amesg_i[5]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(4), - I1 => s_axi_awaddr(4), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(4), O => s_amesg(5) ); \gen_no_arbiter.m_amesg_i[6]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(5), - I1 => s_axi_awaddr(5), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(5), O => s_amesg(6) ); \gen_no_arbiter.m_amesg_i[7]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(6), - I1 => s_axi_awaddr(6), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(6), O => s_amesg(7) ); \gen_no_arbiter.m_amesg_i[8]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(7), - I1 => s_axi_awaddr(7), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(7), O => s_amesg(8) ); \gen_no_arbiter.m_amesg_i[9]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"CCAC" + INIT => X"FB08" ) port map ( I0 => s_axi_araddr(8), - I1 => s_axi_awaddr(8), - I2 => s_axi_arvalid(0), - I3 => s_awvalid_reg, + I1 => s_axi_arvalid(0), + I2 => s_awvalid_reg, + I3 => s_axi_awaddr(8), O => s_amesg(9) ); \gen_no_arbiter.m_amesg_i_reg[10]\: unisim.vcomponents.FDRE @@ -690,304 +700,293 @@ begin C => aclk, CE => p_0_in1_in, D => s_amesg(10), - Q => \^q\(9), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(9), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(11), - Q => \^q\(10), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(10), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(12), - Q => \^q\(11), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(11), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(13), - Q => \^q\(12), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(12), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(14), - Q => \^q\(13), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(13), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(15), - Q => \^q\(14), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(14), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(16), - Q => \^q\(15), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(15), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(17), - Q => \^q\(16), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(16), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(18), - Q => \^q\(17), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(17), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(19), - Q => \^q\(18), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(18), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(1), - Q => \^q\(0), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(0), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(20), - Q => \^q\(19), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(19), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(21), - Q => \^q\(20), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(20), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(22), - Q => \^q\(21), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(21), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(23), - Q => \^q\(22), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(22), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(24), - Q => \^q\(23), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(23), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(25), - Q => \^q\(24), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(24), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(26), - Q => \^q\(25), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(25), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(27), - Q => \^q\(26), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(26), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(28), - Q => \^q\(27), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(27), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(29), - Q => \^q\(28), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(28), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(2), - Q => \^q\(1), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(1), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(30), - Q => \^q\(29), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(29), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(31), - Q => \^q\(30), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(30), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(32), - Q => \^q\(31), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(31), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(3), - Q => \^q\(2), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(2), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(46), - Q => \^q\(32), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(32), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(47), - Q => \^q\(33), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(33), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[48]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(48), - Q => \^q\(34), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(34), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(4), - Q => \^q\(3), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(3), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(5), - Q => \^q\(4), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(4), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(6), - Q => \^q\(5), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(5), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(7), - Q => \^q\(6), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(6), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(8), - Q => \^q\(7), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(7), + R => \^reset\ ); \gen_no_arbiter.m_amesg_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_0_in1_in, D => s_amesg(9), - Q => \^q\(8), - R => \^sr\(0) + Q => \^m_axi_arprot[2]\(8), + R => \^reset\ ); \gen_no_arbiter.m_grant_hot_i[0]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"0008880888888888" - ) - port map ( - I0 => \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0\, - I1 => aresetn_d, - I2 => \^aa_awready\, - I3 => \^aa_grant_rnw\, - I4 => \m_ready_d_reg[0]_1\, - I5 => \^m_valid_i\, - O => \gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0\ - ); -\gen_no_arbiter.m_grant_hot_i[0]_i_2\: unisim.vcomponents.LUT4 - generic map( - INIT => X"F0FE" + INIT => X"00000000F0FE0000" ) port map ( I0 => s_axi_arvalid(0), I1 => s_axi_awvalid(0), I2 => aa_grant_any, I3 => \^m_valid_i\, - O => \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0\ + I4 => aresetn_d, + I5 => \gen_no_arbiter.m_valid_i_i_2_n_0\, + O => \gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0\ ); \gen_no_arbiter.m_grant_hot_i_reg[0]\: unisim.vcomponents.FDRE port map ( @@ -997,620 +996,666 @@ begin Q => aa_grant_any, R => '0' ); -\gen_no_arbiter.m_valid_i_i_1\: unisim.vcomponents.LUT5 +\gen_no_arbiter.m_valid_i_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"47FF4700" + INIT => X"4E" ) port map ( - I0 => \m_ready_d_reg[0]_1\, - I1 => \^aa_grant_rnw\, - I2 => \^aa_awready\, - I3 => \^m_valid_i\, - I4 => aa_grant_any, + I0 => \^m_valid_i\, + I1 => aa_grant_any, + I2 => \gen_no_arbiter.m_valid_i_i_2_n_0\, O => \gen_no_arbiter.m_valid_i_i_1_n_0\ ); +\gen_no_arbiter.m_valid_i_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888888888888F8" + ) + port map ( + I0 => \^m_ready_d0\(0), + I1 => \m_payload_i_reg[0]\, + I2 => \^m_ready_d0_0\(0), + I3 => \m_ready_d_reg[0]_1\, + I4 => \^m_ready_d_reg[2]\, + I5 => \s_axi_wready[0]_INST_0_i_2_n_0\, + O => \gen_no_arbiter.m_valid_i_i_2_n_0\ + ); \gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \gen_no_arbiter.m_valid_i_i_1_n_0\, Q => \^m_valid_i\, - R => \^sr\(0) + R => \^reset\ ); -\gen_no_arbiter.s_ready_i[0]_i_1\: unisim.vcomponents.LUT3 +\gen_no_arbiter.s_ready_i[0]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"20" + INIT => X"2" ) port map ( - I0 => aresetn_d, + I0 => aa_grant_any, I1 => \^m_valid_i\, - I2 => aa_grant_any, - O => s_ready_i0 + O => m_valid_i4_out ); \gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', - D => s_ready_i0, + D => m_valid_i4_out, Q => s_ready_i, - R => '0' + R => \^reset\ ); -\m_atarget_enc[0]_i_1\: unisim.vcomponents.LUT6 +\m_atarget_enc[0]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"FFFFFFFF55575555" + INIT => X"BF" ) port map ( - I0 => match, - I1 => \m_atarget_hot[9]_i_3_n_0\, - I2 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\, - I3 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_4\, - I4 => \m_atarget_hot[9]_i_6_n_0\, - I5 => target_mi_enc(0), + I0 => \m_atarget_enc[0]_i_2_n_0\, + I1 => \m_atarget_enc[0]_i_3_n_0\, + I2 => \m_atarget_hot[11]_i_2_n_0\, O => \m_atarget_enc_reg[0]\ ); -\m_atarget_enc[0]_i_2\: unisim.vcomponents.LUT4 +\m_atarget_enc[0]_i_2\: unisim.vcomponents.LUT5 generic map( - INIT => X"FFFE" + INIT => X"AAAAAAAB" ) port map ( - I0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\, - I1 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\, - I2 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_5\, - I3 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_7\, - O => target_mi_enc(0) + I0 => \m_atarget_hot[1]_i_2_n_0\, + I1 => \m_atarget_hot[4]_i_2_n_0\, + I2 => \^m_axi_arprot[2]\(23), + I3 => \^m_axi_arprot[2]\(22), + I4 => \m_atarget_hot[3]_i_3_n_0\, + O => \m_atarget_enc[0]_i_2_n_0\ ); -\m_atarget_enc[1]_i_1\: unisim.vcomponents.LUT6 +\m_atarget_enc[0]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"AA2A000000000000" + INIT => X"FFFFFF1FFFFFFFFF" ) port map ( - I0 => target_mi_enc(1), - I1 => \m_atarget_hot[9]_i_6_n_0\, - I2 => \m_atarget_hot[8]_i_2_n_0\, - I3 => \m_atarget_hot[9]_i_3_n_0\, - I4 => match, - I5 => aresetn_d, - O => \m_atarget_enc_reg[2]\(0) + I0 => \^m_axi_arprot[2]\(16), + I1 => \^m_axi_arprot[2]\(17), + I2 => \m_atarget_hot[10]_i_3_n_0\, + I3 => \^m_axi_arprot[2]\(18), + I4 => \^m_axi_arprot[2]\(19), + I5 => \m_atarget_hot[4]_i_3_n_0\, + O => \m_atarget_enc[0]_i_3_n_0\ ); -\m_atarget_enc[1]_i_2\: unisim.vcomponents.LUT4 +\m_atarget_enc[1]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"FFFE" + INIT => X"FFFEFFFF" ) port map ( - I0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\, - I1 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2\, - I2 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_6\, - I3 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_7\, - O => target_mi_enc(1) + I0 => \m_atarget_enc[1]_i_2_n_0\, + I1 => \m_atarget_hot[2]_i_2_n_0\, + I2 => \m_atarget_hot[10]_i_2_n_0\, + I3 => \m_atarget_hot[3]_i_2_n_0\, + I4 => \m_atarget_hot[11]_i_2_n_0\, + O => \m_atarget_enc_reg[1]\ ); -\m_atarget_enc[2]_i_1\: unisim.vcomponents.LUT6 +\m_atarget_enc[1]_i_2\: unisim.vcomponents.LUT5 generic map( - INIT => X"AA2A000000000000" + INIT => X"23002000" ) port map ( - I0 => target_mi_enc(2), - I1 => \m_atarget_hot[9]_i_6_n_0\, - I2 => \m_atarget_hot[8]_i_2_n_0\, - I3 => \m_atarget_hot[9]_i_3_n_0\, - I4 => match, - I5 => aresetn_d, - O => \m_atarget_enc_reg[2]\(1) + I0 => \m_atarget_hot[0]_i_2_n_0\, + I1 => \m_atarget_enc[1]_i_3_n_0\, + I2 => \^m_axi_arprot[2]\(16), + I3 => \m_atarget_hot[10]_i_3_n_0\, + I4 => \m_atarget_hot[4]_i_3_n_0\, + O => \m_atarget_enc[1]_i_2_n_0\ ); -\m_atarget_enc[2]_i_2\: unisim.vcomponents.LUT6 +\m_atarget_enc[1]_i_3\: unisim.vcomponents.LUT3 generic map( - INIT => X"8CCC000080000000" + INIT => X"EF" ) port map ( - I0 => \gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\, - I1 => \m_atarget_enc[2]_i_3_n_0\, - I2 => \^q\(17), - I3 => \^q\(16), - I4 => \gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\, - I5 => \gen_addr_decoder.addr_decoder_inst/gen_target[7].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\, - O => target_mi_enc(2) + I0 => \^m_axi_arprot[2]\(19), + I1 => \^m_axi_arprot[2]\(18), + I2 => \^m_axi_arprot[2]\(17), + O => \m_atarget_enc[1]_i_3_n_0\ ); -\m_atarget_enc[2]_i_3\: unisim.vcomponents.LUT2 +\m_atarget_enc[2]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( - I0 => \^q\(19), - I1 => \^q\(18), - O => \m_atarget_enc[2]_i_3_n_0\ + I0 => \m_atarget_enc[3]_i_3_n_0\, + O => \m_atarget_enc_reg[2]\ ); \m_atarget_enc[3]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFF55575555" + INIT => X"000000000B030000" ) port map ( - I0 => match, - I1 => \m_atarget_hot[9]_i_3_n_0\, - I2 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\, - I3 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_4\, - I4 => \m_atarget_hot[9]_i_6_n_0\, - I5 => target_mi_enc(3), + I0 => \m_atarget_enc[3]_i_2_n_0\, + I1 => \m_atarget_hot[0]_i_2_n_0\, + I2 => \m_atarget_hot[3]_i_2_n_0\, + I3 => \m_atarget_hot[4]_i_2_n_0\, + I4 => \m_atarget_enc[3]_i_3_n_0\, + I5 => \m_atarget_hot[2]_i_2_n_0\, O => \m_atarget_enc_reg[3]\ ); -\m_atarget_hot[0]_i_1\: unisim.vcomponents.LUT6 +\m_atarget_enc[3]_i_2\: unisim.vcomponents.LUT5 generic map( - INIT => X"AA2A000000000000" + INIT => X"FFFFFFDF" ) port map ( - I0 => aa_grant_any, - I1 => \m_atarget_hot[9]_i_6_n_0\, - I2 => \m_atarget_hot[8]_i_2_n_0\, - I3 => \m_atarget_hot[9]_i_3_n_0\, - I4 => match, - I5 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\, - O => D(0) + I0 => \^m_axi_arprot[2]\(16), + I1 => \^m_axi_arprot[2]\(17), + I2 => \m_atarget_hot[10]_i_3_n_0\, + I3 => \^m_axi_arprot[2]\(18), + I4 => \^m_axi_arprot[2]\(19), + O => \m_atarget_enc[3]_i_2_n_0\ ); -\m_atarget_hot[0]_i_2\: unisim.vcomponents.LUT6 +\m_atarget_enc[3]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"0000000200000000" + INIT => X"DCCCFFFFDFFFFFFF" ) port map ( - I0 => \gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\, - I1 => \^q\(18), - I2 => \^q\(19), - I3 => \^q\(17), - I4 => \^q\(16), - I5 => \gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\, - O => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\ + I0 => \m_atarget_hot[0]_i_2_n_0\, + I1 => \m_atarget_enc[3]_i_4_n_0\, + I2 => \^m_axi_arprot[2]\(17), + I3 => \^m_axi_arprot[2]\(16), + I4 => \m_atarget_hot[10]_i_3_n_0\, + I5 => \m_atarget_hot[4]_i_3_n_0\, + O => \m_atarget_enc[3]_i_3_n_0\ ); -\m_atarget_hot[1]_i_1\: unisim.vcomponents.LUT6 +\m_atarget_enc[3]_i_4\: unisim.vcomponents.LUT2 generic map( - INIT => X"AA2A000000000000" + INIT => X"E" ) port map ( - I0 => aa_grant_any, - I1 => \m_atarget_hot[9]_i_6_n_0\, - I2 => \m_atarget_hot[8]_i_2_n_0\, - I3 => \m_atarget_hot[9]_i_3_n_0\, - I4 => match, - I5 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\, - O => D(1) + I0 => \^m_axi_arprot[2]\(18), + I1 => \^m_axi_arprot[2]\(19), + O => \m_atarget_enc[3]_i_4_n_0\ ); -\m_atarget_hot[1]_i_2\: unisim.vcomponents.LUT6 +\m_atarget_hot[0]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"0000020000000000" + INIT => X"4000" ) port map ( - I0 => \gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\, - I1 => \^q\(18), - I2 => \^q\(19), - I3 => \^q\(16), - I4 => \^q\(17), - I5 => \gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\, - O => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\ + I0 => \m_atarget_hot[4]_i_2_n_0\, + I1 => \m_atarget_hot[0]_i_2_n_0\, + I2 => \m_atarget_hot[11]_i_2_n_0\, + I3 => aa_grant_any, + O => D(0) ); -\m_atarget_hot[2]_i_1\: unisim.vcomponents.LUT6 +\m_atarget_hot[0]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"AA2A000000000000" + INIT => X"0000001000000000" ) port map ( - I0 => aa_grant_any, - I1 => \m_atarget_hot[9]_i_6_n_0\, - I2 => \m_atarget_hot[8]_i_2_n_0\, - I3 => \m_atarget_hot[9]_i_3_n_0\, - I4 => match, - I5 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2\, - O => D(2) + I0 => \^m_axi_arprot[2]\(22), + I1 => \^m_axi_arprot[2]\(23), + I2 => \^m_axi_arprot[2]\(21), + I3 => \^m_axi_arprot[2]\(20), + I4 => \^m_axi_arprot[2]\(25), + I5 => \^m_axi_arprot[2]\(24), + O => \m_atarget_hot[0]_i_2_n_0\ ); -\m_atarget_hot[2]_i_2\: unisim.vcomponents.LUT6 +\m_atarget_hot[10]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"0000020000000000" + INIT => X"80" ) port map ( - I0 => \gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\, - I1 => \^q\(18), - I2 => \^q\(19), - I3 => \^q\(17), - I4 => \^q\(16), - I5 => \gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\, - O => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2\ + I0 => \m_atarget_hot[10]_i_2_n_0\, + I1 => \m_atarget_hot[11]_i_2_n_0\, + I2 => aa_grant_any, + O => D(10) ); -\m_atarget_hot[3]_i_1\: unisim.vcomponents.LUT3 +\m_atarget_hot[10]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"80" + INIT => X"0000000040000000" ) port map ( - I0 => aa_grant_any, - I1 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\, - I2 => match, - O => D(3) + I0 => \^m_axi_arprot[2]\(17), + I1 => \^m_axi_arprot[2]\(16), + I2 => \m_atarget_hot[0]_i_2_n_0\, + I3 => \m_atarget_hot[10]_i_3_n_0\, + I4 => \^m_axi_arprot[2]\(18), + I5 => \^m_axi_arprot[2]\(19), + O => \m_atarget_hot[10]_i_2_n_0\ ); -\m_atarget_hot[4]_i_1\: unisim.vcomponents.LUT3 +\m_atarget_hot[10]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"80" + INIT => X"0000000100000000" ) port map ( - I0 => aa_grant_any, - I1 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_4\, - I2 => match, - O => D(4) + I0 => \^m_axi_arprot[2]\(28), + I1 => \^m_axi_arprot[2]\(29), + I2 => \^m_axi_arprot[2]\(26), + I3 => \^m_axi_arprot[2]\(27), + I4 => \^m_axi_arprot[2]\(31), + I5 => \^m_axi_arprot[2]\(30), + O => \m_atarget_hot[10]_i_3_n_0\ ); -\m_atarget_hot[5]_i_1\: unisim.vcomponents.LUT6 +\m_atarget_hot[11]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"AA2A000000000000" + INIT => X"2" ) port map ( I0 => aa_grant_any, - I1 => \m_atarget_hot[9]_i_6_n_0\, - I2 => \m_atarget_hot[8]_i_2_n_0\, - I3 => \m_atarget_hot[9]_i_3_n_0\, - I4 => match, - I5 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_5\, - O => D(5) + I1 => \m_atarget_hot[11]_i_2_n_0\, + O => D(11) ); -\m_atarget_hot[5]_i_2\: unisim.vcomponents.LUT6 +\m_atarget_hot[11]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"0000020000000000" + INIT => X"FFFFFFFFFFFFFEFF" ) port map ( - I0 => \gen_addr_decoder.addr_decoder_inst/gen_target[7].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\, - I1 => \^q\(18), - I2 => \^q\(19), - I3 => \^q\(16), - I4 => \^q\(17), - I5 => \gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\, - O => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_5\ + I0 => \m_atarget_hot[9]_i_2_n_0\, + I1 => \m_atarget_hot[11]_i_3_n_0\, + I2 => \m_atarget_hot[2]_i_2_n_0\, + I3 => \m_atarget_enc[3]_i_3_n_0\, + I4 => \m_atarget_hot[11]_i_4_n_0\, + I5 => \m_atarget_enc[0]_i_2_n_0\, + O => \m_atarget_hot[11]_i_2_n_0\ ); -\m_atarget_hot[6]_i_1\: unisim.vcomponents.LUT6 +\m_atarget_hot[11]_i_3\: unisim.vcomponents.LUT5 generic map( - INIT => X"AA2A000000000000" + INIT => X"00004000" ) port map ( - I0 => aa_grant_any, - I1 => \m_atarget_hot[9]_i_6_n_0\, - I2 => \m_atarget_hot[8]_i_2_n_0\, - I3 => \m_atarget_hot[9]_i_3_n_0\, - I4 => match, - I5 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_6\, - O => D(6) + I0 => \^m_axi_arprot[2]\(19), + I1 => \^m_axi_arprot[2]\(18), + I2 => \m_atarget_hot[10]_i_3_n_0\, + I3 => \m_atarget_hot[0]_i_2_n_0\, + I4 => \^m_axi_arprot[2]\(17), + O => \m_atarget_hot[11]_i_3_n_0\ ); -\m_atarget_hot[6]_i_2\: unisim.vcomponents.LUT6 +\m_atarget_hot[11]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"0200000000000000" + INIT => X"0000000000000200" ) port map ( - I0 => \gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\, - I1 => \^q\(18), - I2 => \^q\(19), - I3 => \^q\(17), - I4 => \^q\(16), - I5 => \gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\, - O => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_6\ + I0 => \m_atarget_hot[0]_i_2_n_0\, + I1 => \^m_axi_arprot[2]\(19), + I2 => \^m_axi_arprot[2]\(18), + I3 => \m_atarget_hot[10]_i_3_n_0\, + I4 => \^m_axi_arprot[2]\(17), + I5 => \^m_axi_arprot[2]\(16), + O => \m_atarget_hot[11]_i_4_n_0\ ); -\m_atarget_hot[7]_i_1\: unisim.vcomponents.LUT6 +\m_atarget_hot[1]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AA2A000000000000" + INIT => X"80" ) port map ( - I0 => aa_grant_any, - I1 => \m_atarget_hot[9]_i_6_n_0\, - I2 => \m_atarget_hot[8]_i_2_n_0\, - I3 => \m_atarget_hot[9]_i_3_n_0\, - I4 => match, - I5 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_7\, - O => D(7) + I0 => \m_atarget_hot[1]_i_2_n_0\, + I1 => \m_atarget_hot[11]_i_2_n_0\, + I2 => aa_grant_any, + O => D(1) ); -\m_atarget_hot[7]_i_2\: unisim.vcomponents.LUT6 +\m_atarget_hot[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0000020000000000" ) port map ( - I0 => \gen_addr_decoder.addr_decoder_inst/gen_target[7].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\, - I1 => \^q\(18), - I2 => \^q\(19), - I3 => \^q\(17), - I4 => \^q\(16), - I5 => \gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\, - O => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_7\ + I0 => \m_atarget_hot[0]_i_2_n_0\, + I1 => \^m_axi_arprot[2]\(19), + I2 => \^m_axi_arprot[2]\(18), + I3 => \m_atarget_hot[10]_i_3_n_0\, + I4 => \^m_axi_arprot[2]\(17), + I5 => \^m_axi_arprot[2]\(16), + O => \m_atarget_hot[1]_i_2_n_0\ ); -\m_atarget_hot[8]_i_1\: unisim.vcomponents.LUT6 +\m_atarget_hot[2]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AA2A000000000000" + INIT => X"80" ) port map ( - I0 => aa_grant_any, - I1 => \m_atarget_hot[9]_i_6_n_0\, - I2 => \m_atarget_hot[8]_i_2_n_0\, - I3 => \m_atarget_hot[9]_i_3_n_0\, - I4 => match, - I5 => target_mi_enc(3), - O => D(8) + I0 => \m_atarget_hot[2]_i_2_n_0\, + I1 => \m_atarget_hot[11]_i_2_n_0\, + I2 => aa_grant_any, + O => D(2) ); -\m_atarget_hot[8]_i_2\: unisim.vcomponents.LUT2 +\m_atarget_hot[2]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"1" + INIT => X"0000000000000800" ) port map ( - I0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_4\, - I1 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\, - O => \m_atarget_hot[8]_i_2_n_0\ + I0 => \m_atarget_hot[0]_i_2_n_0\, + I1 => \m_atarget_hot[10]_i_3_n_0\, + I2 => \^m_axi_arprot[2]\(16), + I3 => \^m_axi_arprot[2]\(17), + I4 => \^m_axi_arprot[2]\(18), + I5 => \^m_axi_arprot[2]\(19), + O => \m_atarget_hot[2]_i_2_n_0\ ); -\m_atarget_hot[8]_i_3\: unisim.vcomponents.LUT6 +\m_atarget_hot[3]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"0000020000000000" + INIT => X"80" ) port map ( - I0 => \gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\, - I1 => \^q\(19), - I2 => \^q\(17), - I3 => \^q\(18), - I4 => \^q\(16), - I5 => \gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\, - O => target_mi_enc(3) + I0 => \m_atarget_hot[3]_i_2_n_0\, + I1 => \m_atarget_hot[11]_i_2_n_0\, + I2 => aa_grant_any, + O => D(3) ); -\m_atarget_hot[8]_i_4\: unisim.vcomponents.LUT6 +\m_atarget_hot[3]_i_2\: unisim.vcomponents.LUT4 generic map( - INIT => X"0001000000000000" + INIT => X"0001" ) port map ( - I0 => \^q\(25), - I1 => \^q\(22), - I2 => \^q\(23), - I3 => \^q\(20), - I4 => \^q\(21), - I5 => \^q\(24), - O => \gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\ + I0 => \m_atarget_hot[3]_i_3_n_0\, + I1 => \^m_axi_arprot[2]\(22), + I2 => \^m_axi_arprot[2]\(23), + I3 => \m_atarget_hot[4]_i_2_n_0\, + O => \m_atarget_hot[3]_i_2_n_0\ ); -\m_atarget_hot[9]_i_1\: unisim.vcomponents.LUT6 +\m_atarget_hot[3]_i_3\: unisim.vcomponents.LUT4 generic map( - INIT => X"2222222A22222222" + INIT => X"FFDF" ) port map ( - I0 => aa_grant_any, - I1 => match, - I2 => \m_atarget_hot[9]_i_3_n_0\, - I3 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\, - I4 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_4\, - I5 => \m_atarget_hot[9]_i_6_n_0\, - O => D(9) + I0 => \^m_axi_arprot[2]\(25), + I1 => \^m_axi_arprot[2]\(21), + I2 => \^m_axi_arprot[2]\(24), + I3 => \^m_axi_arprot[2]\(20), + O => \m_atarget_hot[3]_i_3_n_0\ ); -\m_atarget_hot[9]_i_10\: unisim.vcomponents.LUT6 +\m_atarget_hot[4]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"0000000000000100" + INIT => X"4000" ) port map ( - I0 => \^q\(31), - I1 => \^q\(28), - I2 => \^q\(29), - I3 => \^q\(30), - I4 => \^q\(26), - I5 => \^q\(27), - O => \gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\ + I0 => \m_atarget_hot[4]_i_2_n_0\, + I1 => \m_atarget_hot[4]_i_3_n_0\, + I2 => \m_atarget_hot[11]_i_2_n_0\, + I3 => aa_grant_any, + O => D(4) ); -\m_atarget_hot[9]_i_11\: unisim.vcomponents.LUT6 +\m_atarget_hot[4]_i_2\: unisim.vcomponents.LUT5 generic map( - INIT => X"0400000000000000" + INIT => X"FFFFFFEF" ) port map ( - I0 => \^q\(21), - I1 => \^q\(24), - I2 => \^q\(20), - I3 => \^q\(25), - I4 => \^q\(22), - I5 => \^q\(23), - O => \gen_addr_decoder.addr_decoder_inst/gen_target[7].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\ + I0 => \^m_axi_arprot[2]\(16), + I1 => \^m_axi_arprot[2]\(17), + I2 => \m_atarget_hot[10]_i_3_n_0\, + I3 => \^m_axi_arprot[2]\(18), + I4 => \^m_axi_arprot[2]\(19), + O => \m_atarget_hot[4]_i_2_n_0\ ); -\m_atarget_hot[9]_i_2\: unisim.vcomponents.LUT4 +\m_atarget_hot[4]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FEFF" + INIT => X"0000080000000000" ) port map ( - I0 => \m_atarget_hot[9]_i_7_n_0\, - I1 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\, - I2 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_4\, - I3 => \m_atarget_hot[9]_i_8_n_0\, - O => match + I0 => \^m_axi_arprot[2]\(23), + I1 => \^m_axi_arprot[2]\(22), + I2 => \^m_axi_arprot[2]\(20), + I3 => \^m_axi_arprot[2]\(24), + I4 => \^m_axi_arprot[2]\(21), + I5 => \^m_axi_arprot[2]\(25), + O => \m_atarget_hot[4]_i_3_n_0\ ); -\m_atarget_hot[9]_i_3\: unisim.vcomponents.LUT6 +\m_atarget_hot[5]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"FFFFFFFFFFFFFF02" + INIT => X"80" ) port map ( - I0 => \m_atarget_hot[9]_i_8_n_0\, - I1 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_4\, - I2 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\, - I3 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\, - I4 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2\, - I5 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\, - O => \m_atarget_hot[9]_i_3_n_0\ + I0 => \m_atarget_hot[5]_i_2_n_0\, + I1 => \m_atarget_hot[11]_i_2_n_0\, + I2 => aa_grant_any, + O => D(5) ); -\m_atarget_hot[9]_i_4\: unisim.vcomponents.LUT6 +\m_atarget_hot[5]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"0000000200000000" + INIT => X"0000020000000000" ) port map ( - I0 => \gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3__4\, - I1 => \^q\(18), - I2 => \^q\(19), - I3 => \^q\(17), - I4 => \^q\(16), - I5 => \gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\, - O => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\ + I0 => \m_atarget_hot[4]_i_3_n_0\, + I1 => \^m_axi_arprot[2]\(19), + I2 => \^m_axi_arprot[2]\(18), + I3 => \m_atarget_hot[10]_i_3_n_0\, + I4 => \^m_axi_arprot[2]\(17), + I5 => \^m_axi_arprot[2]\(16), + O => \m_atarget_hot[5]_i_2_n_0\ ); -\m_atarget_hot[9]_i_5\: unisim.vcomponents.LUT6 +\m_atarget_hot[6]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"0000000200000000" + INIT => X"80" ) port map ( - I0 => \gen_addr_decoder.addr_decoder_inst/gen_target[7].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\, - I1 => \^q\(18), - I2 => \^q\(19), - I3 => \^q\(17), - I4 => \^q\(16), - I5 => \gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\, - O => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_4\ - ); -\m_atarget_hot[9]_i_6\: unisim.vcomponents.LUT4 + I0 => \m_atarget_hot[6]_i_2_n_0\, + I1 => \m_atarget_hot[11]_i_2_n_0\, + I2 => aa_grant_any, + O => D(6) + ); +\m_atarget_hot[6]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"0001" + INIT => X"0000008000000000" ) port map ( - I0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_7\, - I1 => target_mi_enc(3), - I2 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_5\, - I3 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_6\, - O => \m_atarget_hot[9]_i_6_n_0\ + I0 => \m_atarget_hot[0]_i_2_n_0\, + I1 => \m_atarget_hot[10]_i_3_n_0\, + I2 => \^m_axi_arprot[2]\(17), + I3 => \^m_axi_arprot[2]\(18), + I4 => \^m_axi_arprot[2]\(19), + I5 => \^m_axi_arprot[2]\(16), + O => \m_atarget_hot[6]_i_2_n_0\ ); -\m_atarget_hot[9]_i_7\: unisim.vcomponents.LUT6 +\m_atarget_hot[7]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"0002020200000000" + INIT => X"80" ) port map ( - I0 => \gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\, - I1 => \^q\(18), - I2 => \^q\(19), - I3 => \^q\(16), - I4 => \^q\(17), - I5 => \gen_addr_decoder.addr_decoder_inst/gen_target[8].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\, - O => \m_atarget_hot[9]_i_7_n_0\ + I0 => \m_atarget_hot[7]_i_2_n_0\, + I1 => \m_atarget_hot[11]_i_2_n_0\, + I2 => aa_grant_any, + O => D(7) ); -\m_atarget_hot[9]_i_8\: unisim.vcomponents.LUT4 +\m_atarget_hot[7]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"0001" + INIT => X"0000000000000800" + ) + port map ( + I0 => \m_atarget_hot[4]_i_3_n_0\, + I1 => \m_atarget_hot[10]_i_3_n_0\, + I2 => \^m_axi_arprot[2]\(16), + I3 => \^m_axi_arprot[2]\(17), + I4 => \^m_axi_arprot[2]\(18), + I5 => \^m_axi_arprot[2]\(19), + O => \m_atarget_hot[7]_i_2_n_0\ + ); +\m_atarget_hot[8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" ) port map ( - I0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_7\, - I1 => target_mi_enc(3), - I2 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_6\, - I3 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_5\, - O => \m_atarget_hot[9]_i_8_n_0\ + I0 => \m_atarget_hot[8]_i_2_n_0\, + I1 => \m_atarget_hot[11]_i_2_n_0\, + I2 => aa_grant_any, + O => D(8) ); -\m_atarget_hot[9]_i_9\: unisim.vcomponents.LUT6 +\m_atarget_hot[8]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"0001000000000000" + INIT => X"0000000010000000" ) port map ( - I0 => \^q\(23), - I1 => \^q\(21), - I2 => \^q\(22), - I3 => \^q\(20), - I4 => \^q\(25), - I5 => \^q\(24), - O => \gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3__4\ + I0 => \^m_axi_arprot[2]\(17), + I1 => \^m_axi_arprot[2]\(16), + I2 => \m_atarget_hot[0]_i_2_n_0\, + I3 => \m_atarget_hot[10]_i_3_n_0\, + I4 => \^m_axi_arprot[2]\(18), + I5 => \^m_axi_arprot[2]\(19), + O => \m_atarget_hot[8]_i_2_n_0\ + ); +\m_atarget_hot[9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \m_atarget_hot[9]_i_2_n_0\, + I1 => \m_atarget_hot[11]_i_2_n_0\, + I2 => aa_grant_any, + O => D(9) + ); +\m_atarget_hot[9]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000008000000000" + ) + port map ( + I0 => \m_atarget_hot[4]_i_3_n_0\, + I1 => \m_atarget_hot[10]_i_3_n_0\, + I2 => \^m_axi_arprot[2]\(17), + I3 => \^m_axi_arprot[2]\(18), + I4 => \^m_axi_arprot[2]\(19), + I5 => \^m_axi_arprot[2]\(16), + O => \m_atarget_hot[9]_i_2_n_0\ ); \m_axi_arvalid[0]_INST_0\: unisim.vcomponents.LUT4 generic map( - INIT => X"2000" + INIT => X"0080" ) port map ( - I0 => \m_atarget_hot_reg[9]\(0), - I1 => m_ready_d(1), - I2 => \^aa_grant_rnw\, - I3 => \^m_valid_i\, + I0 => Q(0), + I1 => \^aa_grant_rnw\, + I2 => \^m_valid_i\, + I3 => m_ready_d_1(1), O => m_axi_arvalid(0) ); +\m_axi_arvalid[10]_INST_0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0080" + ) + port map ( + I0 => Q(10), + I1 => \^aa_grant_rnw\, + I2 => \^m_valid_i\, + I3 => m_ready_d_1(1), + O => m_axi_arvalid(10) + ); \m_axi_arvalid[1]_INST_0\: unisim.vcomponents.LUT4 generic map( - INIT => X"2000" + INIT => X"0080" ) port map ( - I0 => \m_atarget_hot_reg[9]\(1), - I1 => m_ready_d(1), - I2 => \^aa_grant_rnw\, - I3 => \^m_valid_i\, + I0 => Q(1), + I1 => \^aa_grant_rnw\, + I2 => \^m_valid_i\, + I3 => m_ready_d_1(1), O => m_axi_arvalid(1) ); \m_axi_arvalid[2]_INST_0\: unisim.vcomponents.LUT4 generic map( - INIT => X"2000" + INIT => X"0080" ) port map ( - I0 => \m_atarget_hot_reg[9]\(2), - I1 => m_ready_d(1), - I2 => \^aa_grant_rnw\, - I3 => \^m_valid_i\, + I0 => Q(2), + I1 => \^aa_grant_rnw\, + I2 => \^m_valid_i\, + I3 => m_ready_d_1(1), O => m_axi_arvalid(2) ); \m_axi_arvalid[3]_INST_0\: unisim.vcomponents.LUT4 generic map( - INIT => X"2000" + INIT => X"0080" ) port map ( - I0 => \m_atarget_hot_reg[9]\(3), - I1 => m_ready_d(1), - I2 => \^aa_grant_rnw\, - I3 => \^m_valid_i\, + I0 => Q(3), + I1 => \^aa_grant_rnw\, + I2 => \^m_valid_i\, + I3 => m_ready_d_1(1), O => m_axi_arvalid(3) ); \m_axi_arvalid[4]_INST_0\: unisim.vcomponents.LUT4 generic map( - INIT => X"2000" + INIT => X"0080" ) port map ( - I0 => \m_atarget_hot_reg[9]\(4), - I1 => m_ready_d(1), - I2 => \^aa_grant_rnw\, - I3 => \^m_valid_i\, + I0 => Q(4), + I1 => \^aa_grant_rnw\, + I2 => \^m_valid_i\, + I3 => m_ready_d_1(1), O => m_axi_arvalid(4) ); \m_axi_arvalid[5]_INST_0\: unisim.vcomponents.LUT4 generic map( - INIT => X"2000" + INIT => X"0080" ) port map ( - I0 => \m_atarget_hot_reg[9]\(5), - I1 => m_ready_d(1), - I2 => \^aa_grant_rnw\, - I3 => \^m_valid_i\, + I0 => Q(5), + I1 => \^aa_grant_rnw\, + I2 => \^m_valid_i\, + I3 => m_ready_d_1(1), O => m_axi_arvalid(5) ); \m_axi_arvalid[6]_INST_0\: unisim.vcomponents.LUT4 generic map( - INIT => X"2000" + INIT => X"0080" ) port map ( - I0 => \m_atarget_hot_reg[9]\(6), - I1 => m_ready_d(1), - I2 => \^aa_grant_rnw\, - I3 => \^m_valid_i\, + I0 => Q(6), + I1 => \^aa_grant_rnw\, + I2 => \^m_valid_i\, + I3 => m_ready_d_1(1), O => m_axi_arvalid(6) ); \m_axi_arvalid[7]_INST_0\: unisim.vcomponents.LUT4 generic map( - INIT => X"2000" + INIT => X"0080" ) port map ( - I0 => \m_atarget_hot_reg[9]\(7), - I1 => m_ready_d(1), - I2 => \^aa_grant_rnw\, - I3 => \^m_valid_i\, + I0 => Q(7), + I1 => \^aa_grant_rnw\, + I2 => \^m_valid_i\, + I3 => m_ready_d_1(1), O => m_axi_arvalid(7) ); \m_axi_arvalid[8]_INST_0\: unisim.vcomponents.LUT4 generic map( - INIT => X"2000" + INIT => X"0080" ) port map ( - I0 => \m_atarget_hot_reg[9]\(8), - I1 => m_ready_d(1), - I2 => \^aa_grant_rnw\, - I3 => \^m_valid_i\, + I0 => Q(8), + I1 => \^aa_grant_rnw\, + I2 => \^m_valid_i\, + I3 => m_ready_d_1(1), O => m_axi_arvalid(8) ); +\m_axi_arvalid[9]_INST_0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0080" + ) + port map ( + I0 => Q(9), + I1 => \^aa_grant_rnw\, + I2 => \^m_valid_i\, + I3 => m_ready_d_1(1), + O => m_axi_arvalid(9) + ); \m_axi_awvalid[0]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"0020" ) port map ( - I0 => \m_atarget_hot_reg[9]\(0), - I1 => m_ready_d_0(2), + I0 => Q(0), + I1 => \^aa_grant_rnw\, I2 => \^m_valid_i\, - I3 => \^aa_grant_rnw\, + I3 => m_ready_d(2), O => m_axi_awvalid(0) ); +\m_axi_awvalid[10]_INST_0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0020" + ) + port map ( + I0 => Q(10), + I1 => \^aa_grant_rnw\, + I2 => \^m_valid_i\, + I3 => m_ready_d(2), + O => m_axi_awvalid(10) + ); \m_axi_awvalid[1]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"0020" ) port map ( - I0 => \m_atarget_hot_reg[9]\(1), - I1 => m_ready_d_0(2), + I0 => Q(1), + I1 => \^aa_grant_rnw\, I2 => \^m_valid_i\, - I3 => \^aa_grant_rnw\, + I3 => m_ready_d(2), O => m_axi_awvalid(1) ); \m_axi_awvalid[2]_INST_0\: unisim.vcomponents.LUT4 @@ -1618,10 +1663,10 @@ begin INIT => X"0020" ) port map ( - I0 => \m_atarget_hot_reg[9]\(2), - I1 => m_ready_d_0(2), + I0 => Q(2), + I1 => \^aa_grant_rnw\, I2 => \^m_valid_i\, - I3 => \^aa_grant_rnw\, + I3 => m_ready_d(2), O => m_axi_awvalid(2) ); \m_axi_awvalid[3]_INST_0\: unisim.vcomponents.LUT4 @@ -1629,10 +1674,10 @@ begin INIT => X"0020" ) port map ( - I0 => \m_atarget_hot_reg[9]\(3), - I1 => m_ready_d_0(2), + I0 => Q(3), + I1 => \^aa_grant_rnw\, I2 => \^m_valid_i\, - I3 => \^aa_grant_rnw\, + I3 => m_ready_d(2), O => m_axi_awvalid(3) ); \m_axi_awvalid[4]_INST_0\: unisim.vcomponents.LUT4 @@ -1640,10 +1685,10 @@ begin INIT => X"0020" ) port map ( - I0 => \m_atarget_hot_reg[9]\(4), - I1 => m_ready_d_0(2), + I0 => Q(4), + I1 => \^aa_grant_rnw\, I2 => \^m_valid_i\, - I3 => \^aa_grant_rnw\, + I3 => m_ready_d(2), O => m_axi_awvalid(4) ); \m_axi_awvalid[5]_INST_0\: unisim.vcomponents.LUT4 @@ -1651,10 +1696,10 @@ begin INIT => X"0020" ) port map ( - I0 => \m_atarget_hot_reg[9]\(5), - I1 => m_ready_d_0(2), + I0 => Q(5), + I1 => \^aa_grant_rnw\, I2 => \^m_valid_i\, - I3 => \^aa_grant_rnw\, + I3 => m_ready_d(2), O => m_axi_awvalid(5) ); \m_axi_awvalid[6]_INST_0\: unisim.vcomponents.LUT4 @@ -1662,10 +1707,10 @@ begin INIT => X"0020" ) port map ( - I0 => \m_atarget_hot_reg[9]\(6), - I1 => m_ready_d_0(2), + I0 => Q(6), + I1 => \^aa_grant_rnw\, I2 => \^m_valid_i\, - I3 => \^aa_grant_rnw\, + I3 => m_ready_d(2), O => m_axi_awvalid(6) ); \m_axi_awvalid[7]_INST_0\: unisim.vcomponents.LUT4 @@ -1673,10 +1718,10 @@ begin INIT => X"0020" ) port map ( - I0 => \m_atarget_hot_reg[9]\(7), - I1 => m_ready_d_0(2), + I0 => Q(7), + I1 => \^aa_grant_rnw\, I2 => \^m_valid_i\, - I3 => \^aa_grant_rnw\, + I3 => m_ready_d(2), O => m_axi_awvalid(7) ); \m_axi_awvalid[8]_INST_0\: unisim.vcomponents.LUT4 @@ -1684,508 +1729,430 @@ begin INIT => X"0020" ) port map ( - I0 => \m_atarget_hot_reg[9]\(8), - I1 => m_ready_d_0(2), + I0 => Q(8), + I1 => \^aa_grant_rnw\, I2 => \^m_valid_i\, - I3 => \^aa_grant_rnw\, + I3 => m_ready_d(2), O => m_axi_awvalid(8) ); -\m_axi_bready[0]_INST_0\: unisim.vcomponents.LUT5 +\m_axi_awvalid[9]_INST_0\: unisim.vcomponents.LUT4 generic map( - INIT => X"00200000" + INIT => X"0020" ) port map ( - I0 => \m_atarget_hot_reg[9]\(0), + I0 => Q(9), I1 => \^aa_grant_rnw\, I2 => \^m_valid_i\, - I3 => m_ready_d_0(0), - I4 => s_axi_bready(0), + I3 => m_ready_d(2), + O => m_axi_awvalid(9) + ); +\m_axi_bready[0]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000800" + ) + port map ( + I0 => Q(0), + I1 => s_axi_bready(0), + I2 => m_ready_d(0), + I3 => \^m_valid_i\, + I4 => \^aa_grant_rnw\, O => m_axi_bready(0) ); +\m_axi_bready[10]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000800" + ) + port map ( + I0 => Q(10), + I1 => s_axi_bready(0), + I2 => m_ready_d(0), + I3 => \^m_valid_i\, + I4 => \^aa_grant_rnw\, + O => m_axi_bready(10) + ); \m_axi_bready[1]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"00200000" + INIT => X"00000800" ) port map ( - I0 => \m_atarget_hot_reg[9]\(1), - I1 => \^aa_grant_rnw\, - I2 => \^m_valid_i\, - I3 => m_ready_d_0(0), - I4 => s_axi_bready(0), + I0 => Q(1), + I1 => s_axi_bready(0), + I2 => m_ready_d(0), + I3 => \^m_valid_i\, + I4 => \^aa_grant_rnw\, O => m_axi_bready(1) ); \m_axi_bready[2]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"00200000" + INIT => X"00000800" ) port map ( - I0 => \m_atarget_hot_reg[9]\(2), - I1 => \^aa_grant_rnw\, - I2 => \^m_valid_i\, - I3 => m_ready_d_0(0), - I4 => s_axi_bready(0), + I0 => Q(2), + I1 => s_axi_bready(0), + I2 => m_ready_d(0), + I3 => \^m_valid_i\, + I4 => \^aa_grant_rnw\, O => m_axi_bready(2) ); \m_axi_bready[3]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"00200000" + INIT => X"00000800" ) port map ( - I0 => \m_atarget_hot_reg[9]\(3), - I1 => \^aa_grant_rnw\, - I2 => \^m_valid_i\, - I3 => m_ready_d_0(0), - I4 => s_axi_bready(0), + I0 => Q(3), + I1 => s_axi_bready(0), + I2 => m_ready_d(0), + I3 => \^m_valid_i\, + I4 => \^aa_grant_rnw\, O => m_axi_bready(3) ); \m_axi_bready[4]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"00200000" + INIT => X"00000800" ) port map ( - I0 => \m_atarget_hot_reg[9]\(4), - I1 => \^aa_grant_rnw\, - I2 => \^m_valid_i\, - I3 => m_ready_d_0(0), - I4 => s_axi_bready(0), + I0 => Q(4), + I1 => s_axi_bready(0), + I2 => m_ready_d(0), + I3 => \^m_valid_i\, + I4 => \^aa_grant_rnw\, O => m_axi_bready(4) ); \m_axi_bready[5]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"00200000" + INIT => X"00000800" ) port map ( - I0 => \m_atarget_hot_reg[9]\(5), - I1 => \^aa_grant_rnw\, - I2 => \^m_valid_i\, - I3 => m_ready_d_0(0), - I4 => s_axi_bready(0), + I0 => Q(5), + I1 => s_axi_bready(0), + I2 => m_ready_d(0), + I3 => \^m_valid_i\, + I4 => \^aa_grant_rnw\, O => m_axi_bready(5) ); \m_axi_bready[6]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"00200000" + INIT => X"00000800" ) port map ( - I0 => \m_atarget_hot_reg[9]\(6), - I1 => \^aa_grant_rnw\, - I2 => \^m_valid_i\, - I3 => m_ready_d_0(0), - I4 => s_axi_bready(0), + I0 => Q(6), + I1 => s_axi_bready(0), + I2 => m_ready_d(0), + I3 => \^m_valid_i\, + I4 => \^aa_grant_rnw\, O => m_axi_bready(6) ); \m_axi_bready[7]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"00200000" + INIT => X"00000800" ) port map ( - I0 => \m_atarget_hot_reg[9]\(7), - I1 => \^aa_grant_rnw\, - I2 => \^m_valid_i\, - I3 => m_ready_d_0(0), - I4 => s_axi_bready(0), + I0 => Q(7), + I1 => s_axi_bready(0), + I2 => m_ready_d(0), + I3 => \^m_valid_i\, + I4 => \^aa_grant_rnw\, O => m_axi_bready(7) ); \m_axi_bready[8]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"00200000" + INIT => X"00000800" ) port map ( - I0 => \m_atarget_hot_reg[9]\(8), - I1 => \^aa_grant_rnw\, - I2 => \^m_valid_i\, - I3 => m_ready_d_0(0), - I4 => s_axi_bready(0), + I0 => Q(8), + I1 => s_axi_bready(0), + I2 => m_ready_d(0), + I3 => \^m_valid_i\, + I4 => \^aa_grant_rnw\, O => m_axi_bready(8) ); -\m_axi_wvalid[0]_INST_0\: unisim.vcomponents.LUT5 +\m_axi_bready[9]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"00000800" ) port map ( - I0 => \m_atarget_hot_reg[9]\(0), - I1 => s_axi_wvalid(0), - I2 => \^aa_grant_rnw\, + I0 => Q(9), + I1 => s_axi_bready(0), + I2 => m_ready_d(0), I3 => \^m_valid_i\, - I4 => m_ready_d_0(1), + I4 => \^aa_grant_rnw\, + O => m_axi_bready(9) + ); +\m_axi_wvalid[0]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00002000" + ) + port map ( + I0 => Q(0), + I1 => \^aa_grant_rnw\, + I2 => \^m_valid_i\, + I3 => s_axi_wvalid(0), + I4 => m_ready_d(1), O => m_axi_wvalid(0) ); +\m_axi_wvalid[10]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00002000" + ) + port map ( + I0 => Q(10), + I1 => \^aa_grant_rnw\, + I2 => \^m_valid_i\, + I3 => s_axi_wvalid(0), + I4 => m_ready_d(1), + O => m_axi_wvalid(10) + ); \m_axi_wvalid[1]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"00000800" + INIT => X"00002000" ) port map ( - I0 => \m_atarget_hot_reg[9]\(1), - I1 => s_axi_wvalid(0), - I2 => \^aa_grant_rnw\, - I3 => \^m_valid_i\, - I4 => m_ready_d_0(1), + I0 => Q(1), + I1 => \^aa_grant_rnw\, + I2 => \^m_valid_i\, + I3 => s_axi_wvalid(0), + I4 => m_ready_d(1), O => m_axi_wvalid(1) ); \m_axi_wvalid[2]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"00000800" + INIT => X"00002000" ) port map ( - I0 => \m_atarget_hot_reg[9]\(2), - I1 => s_axi_wvalid(0), - I2 => \^aa_grant_rnw\, - I3 => \^m_valid_i\, - I4 => m_ready_d_0(1), + I0 => Q(2), + I1 => \^aa_grant_rnw\, + I2 => \^m_valid_i\, + I3 => s_axi_wvalid(0), + I4 => m_ready_d(1), O => m_axi_wvalid(2) ); \m_axi_wvalid[3]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"00000800" + INIT => X"00002000" ) port map ( - I0 => \m_atarget_hot_reg[9]\(3), - I1 => s_axi_wvalid(0), - I2 => \^aa_grant_rnw\, - I3 => \^m_valid_i\, - I4 => m_ready_d_0(1), + I0 => Q(3), + I1 => \^aa_grant_rnw\, + I2 => \^m_valid_i\, + I3 => s_axi_wvalid(0), + I4 => m_ready_d(1), O => m_axi_wvalid(3) ); \m_axi_wvalid[4]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"00000800" + INIT => X"00002000" ) port map ( - I0 => \m_atarget_hot_reg[9]\(4), - I1 => s_axi_wvalid(0), - I2 => \^aa_grant_rnw\, - I3 => \^m_valid_i\, - I4 => m_ready_d_0(1), + I0 => Q(4), + I1 => \^aa_grant_rnw\, + I2 => \^m_valid_i\, + I3 => s_axi_wvalid(0), + I4 => m_ready_d(1), O => m_axi_wvalid(4) ); \m_axi_wvalid[5]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"00000800" + INIT => X"00002000" ) port map ( - I0 => \m_atarget_hot_reg[9]\(5), - I1 => s_axi_wvalid(0), - I2 => \^aa_grant_rnw\, - I3 => \^m_valid_i\, - I4 => m_ready_d_0(1), + I0 => Q(5), + I1 => \^aa_grant_rnw\, + I2 => \^m_valid_i\, + I3 => s_axi_wvalid(0), + I4 => m_ready_d(1), O => m_axi_wvalid(5) ); \m_axi_wvalid[6]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"00000800" + INIT => X"00002000" ) port map ( - I0 => \m_atarget_hot_reg[9]\(6), - I1 => s_axi_wvalid(0), - I2 => \^aa_grant_rnw\, - I3 => \^m_valid_i\, - I4 => m_ready_d_0(1), + I0 => Q(6), + I1 => \^aa_grant_rnw\, + I2 => \^m_valid_i\, + I3 => s_axi_wvalid(0), + I4 => m_ready_d(1), O => m_axi_wvalid(6) ); \m_axi_wvalid[7]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"00000800" + INIT => X"00002000" ) port map ( - I0 => \m_atarget_hot_reg[9]\(7), - I1 => s_axi_wvalid(0), - I2 => \^aa_grant_rnw\, - I3 => \^m_valid_i\, - I4 => m_ready_d_0(1), + I0 => Q(7), + I1 => \^aa_grant_rnw\, + I2 => \^m_valid_i\, + I3 => s_axi_wvalid(0), + I4 => m_ready_d(1), O => m_axi_wvalid(7) ); \m_axi_wvalid[8]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"00000800" + INIT => X"00002000" ) port map ( - I0 => \m_atarget_hot_reg[9]\(8), - I1 => s_axi_wvalid(0), - I2 => \^aa_grant_rnw\, - I3 => \^m_valid_i\, - I4 => m_ready_d_0(1), - O => m_axi_wvalid(8) - ); -\m_payload_i[34]_i_1\: unisim.vcomponents.LUT5 - generic map( - INIT => X"0800FFFF" - ) - port map ( - I0 => \^m_valid_i\, + I0 => Q(8), I1 => \^aa_grant_rnw\, - I2 => m_ready_d(0), - I3 => s_axi_rready(0), - I4 => sr_rvalid, - O => E(0) + I2 => \^m_valid_i\, + I3 => s_axi_wvalid(0), + I4 => m_ready_d(1), + O => m_axi_wvalid(8) ); -\m_ready_d[0]_i_2\: unisim.vcomponents.LUT3 +\m_axi_wvalid[9]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"08" + INIT => X"00002000" ) port map ( - I0 => \^m_valid_i\, + I0 => Q(9), I1 => \^aa_grant_rnw\, - I2 => m_ready_d(0), - O => \^m_ready_d_reg[0]\ + I2 => \^m_valid_i\, + I3 => s_axi_wvalid(0), + I4 => m_ready_d(1), + O => m_axi_wvalid(9) ); -\m_ready_d[0]_i_2__0\: unisim.vcomponents.LUT3 +\m_payload_i[34]_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"04" + INIT => X"0080FFFF" ) port map ( I0 => \^aa_grant_rnw\, I1 => \^m_valid_i\, - I2 => m_ready_d_0(0), - O => \^m_ready_d_reg[0]_0\ - ); -\m_ready_d[1]_i_2\: unisim.vcomponents.LUT3 - generic map( - INIT => X"08" - ) - port map ( - I0 => \^m_valid_i\, - I1 => \^aa_grant_rnw\, - I2 => m_ready_d(1), - O => \^m_ready_d_reg[1]\ + I2 => s_axi_rready(0), + I3 => m_ready_d_1(0), + I4 => sr_rvalid, + O => E(0) ); -\m_ready_d[1]_i_2__0\: unisim.vcomponents.LUT3 +\m_ready_d[0]_i_2\: unisim.vcomponents.LUT2 generic map( - INIT => X"04" + INIT => X"7" ) port map ( I0 => \^aa_grant_rnw\, I1 => \^m_valid_i\, - I2 => m_ready_d_0(1), - O => \^m_ready_d_reg[1]_0\ - ); -\m_ready_d[1]_i_5\: unisim.vcomponents.LUT6 - generic map( - INIT => X"A808FFFFA8080000" - ) - port map ( - I0 => \m_ready_d[1]_i_7_n_0\, - I1 => m_axi_arready(1), - I2 => m_atarget_enc(2), - I3 => m_axi_arready(4), - I4 => m_atarget_enc(1), - I5 => \m_ready_d[1]_i_8_n_0\, - O => \^m_ready_d_reg[1]_1\ + O => \^m_ready_d_reg[0]_0\ ); -\m_ready_d[1]_i_6\: unisim.vcomponents.LUT6 +\m_ready_d[0]_i_3\: unisim.vcomponents.LUT3 generic map( - INIT => X"A808FFFFA8080000" + INIT => X"4F" ) port map ( - I0 => \m_ready_d[1]_i_7_n_0\, - I1 => m_axi_arready(2), - I2 => m_atarget_enc(2), - I3 => m_axi_arready(5), - I4 => m_atarget_enc(1), - I5 => \gen_axilite.s_axi_arready_i_reg\, - O => \^m_ready_d_reg[1]_2\ + I0 => \^m_ready_d_reg[1]_0\, + I1 => \^m_ready_d0\(0), + I2 => aresetn_d, + O => \m_ready_d_reg[0]\ ); -\m_ready_d[1]_i_7\: unisim.vcomponents.LUT4 +\m_ready_d[1]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"0040" + INIT => X"AAAAFFBFAAAAFFFF" ) port map ( - I0 => m_ready_d(1), - I1 => \^aa_grant_rnw\, + I0 => \^m_ready_d_reg[2]\, + I1 => s_axi_bready(0), I2 => \^m_valid_i\, - I3 => m_atarget_enc(3), - O => \m_ready_d[1]_i_7_n_0\ - ); -\m_ready_d[1]_i_8\: unisim.vcomponents.LUT6 - generic map( - INIT => X"00CC88C0000088C0" - ) - port map ( - I0 => m_axi_arready(6), - I1 => \^m_ready_d_reg[1]\, - I2 => m_axi_arready(0), - I3 => m_atarget_enc(3), - I4 => m_atarget_enc(2), - I5 => m_axi_arready(3), - O => \m_ready_d[1]_i_8_n_0\ + I3 => \^aa_grant_rnw\, + I4 => m_ready_d(0), + I5 => \m_atarget_enc_reg[2]_0\, + O => \m_ready_d_reg[1]\ ); -\m_ready_d[2]_i_10\: unisim.vcomponents.LUT6 +\m_ready_d[1]_i_2__0\: unisim.vcomponents.LUT6 generic map( - INIT => X"30BB000000880000" + INIT => X"FFFFFFFF55555455" ) port map ( - I0 => \m_atarget_enc_reg[2]_0\, - I1 => m_atarget_enc(1), - I2 => m_axi_wready(6), - I3 => m_atarget_enc(3), - I4 => \^m_ready_d_reg[1]_0\, - I5 => \m_atarget_enc_reg[2]_1\, - O => \m_ready_d[2]_i_10_n_0\ + I0 => \^m_ready_d_reg[0]_0\, + I1 => \m_atarget_enc_reg[2]_6\, + I2 => \m_atarget_enc_reg[2]_7\, + I3 => \m_atarget_enc_reg[3]_4\, + I4 => \m_atarget_enc_reg[2]_8\, + I5 => m_ready_d_1(1), + O => \^m_ready_d0\(0) ); -\m_ready_d[2]_i_11\: unisim.vcomponents.LUT6 +\m_ready_d[1]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"30BB000000880000" + INIT => X"1555555555555555" ) port map ( - I0 => \m_atarget_enc_reg[2]_2\, - I1 => m_atarget_enc(1), - I2 => m_axi_bvalid(6), - I3 => m_atarget_enc(3), - I4 => \^m_ready_d_reg[0]_0\, - I5 => \m_atarget_enc_reg[2]_3\, - O => \m_ready_d[2]_i_11_n_0\ + I0 => m_ready_d_1(0), + I1 => s_axi_rready(0), + I2 => \^m_valid_i\, + I3 => \^aa_grant_rnw\, + I4 => sr_rvalid, + I5 => \m_payload_i_reg[0]_0\(0), + O => \^m_ready_d_reg[1]_0\ ); \m_ready_d[2]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"AFA0CFCFAFA0C0C0" + INIT => X"FFFFFFFF54550000" ) port map ( - I0 => \m_ready_d[2]_i_4_n_0\, - I1 => \gen_axilite.s_axi_awready_i_reg_0\, - I2 => m_atarget_enc(0), - I3 => \m_ready_d[2]_i_6_n_0\, - I4 => m_atarget_enc(1), - I5 => \m_ready_d[2]_i_7_n_0\, - O => \^mi_awready_mux\ - ); -\m_ready_d[2]_i_3\: unisim.vcomponents.LUT6 - generic map( - INIT => X"EEE0EEE0EEE00000" - ) - port map ( - I0 => \p_0_out__0\(1), - I1 => m_ready_d_0(1), - I2 => m_ready_d_0(2), - I3 => \^mi_awready_mux\, - I4 => m_ready_d_0(0), - I5 => \p_0_out__0\(0), - O => \^aa_awready\ + I0 => \s_axi_wready[0]_INST_0_i_2_n_0\, + I1 => \m_atarget_enc_reg[2]_1\, + I2 => \m_atarget_enc_reg[2]_2\, + I3 => \m_atarget_enc_reg[3]_0\, + I4 => s_axi_wvalid(0), + I5 => m_ready_d(1), + O => \^m_ready_d0_0\(0) ); \m_ready_d[2]_i_4\: unisim.vcomponents.LUT5 generic map( - INIT => X"44400040" + INIT => X"00000001" ) port map ( - I0 => m_atarget_enc(3), - I1 => \^gen_axilite.s_axi_bvalid_i_reg\, - I2 => m_axi_awready(2), - I3 => m_atarget_enc(2), - I4 => m_axi_awready(5), - O => \m_ready_d[2]_i_4_n_0\ + I0 => m_ready_d(2), + I1 => \m_ready_d[2]_i_6_n_0\, + I2 => \m_ready_d[2]_i_7_n_0\, + I3 => \m_ready_d[2]_i_8_n_0\, + I4 => \m_atarget_enc_reg[2]_4\, + O => \^m_ready_d_reg[2]\ ); -\m_ready_d[2]_i_6\: unisim.vcomponents.LUT5 +\m_ready_d[2]_i_6\: unisim.vcomponents.LUT6 generic map( - INIT => X"44400040" + INIT => X"0000000000003B38" ) port map ( - I0 => m_atarget_enc(3), - I1 => \^gen_axilite.s_axi_bvalid_i_reg\, - I2 => m_axi_awready(1), - I3 => m_atarget_enc(2), - I4 => m_axi_awready(4), + I0 => m_axi_awready(3), + I1 => m_atarget_enc(2), + I2 => m_atarget_enc(3), + I3 => m_axi_awready(1), + I4 => \^gen_axilite.s_axi_bvalid_i_reg_0\, + I5 => \m_atarget_enc_reg[3]_2\, O => \m_ready_d[2]_i_6_n_0\ ); \m_ready_d[2]_i_7\: unisim.vcomponents.LUT6 generic map( - INIT => X"00CC88C0000088C0" + INIT => X"0000000000003B38" ) port map ( - I0 => m_axi_awready(6), - I1 => \^gen_axilite.s_axi_bvalid_i_reg\, - I2 => m_axi_awready(0), - I3 => m_atarget_enc(3), - I4 => m_atarget_enc(2), - I5 => m_axi_awready(3), + I0 => m_axi_awready(2), + I1 => m_atarget_enc(2), + I2 => m_atarget_enc(3), + I3 => m_axi_awready(0), + I4 => \^gen_axilite.s_axi_bvalid_i_reg_0\, + I5 => \m_atarget_enc_reg[3]_3\, O => \m_ready_d[2]_i_7_n_0\ ); \m_ready_d[2]_i_8\: unisim.vcomponents.LUT6 generic map( - INIT => X"A8A8A8080808A808" + INIT => X"00000000000000B0" ) port map ( - I0 => \^p_4_in\, - I1 => \m_ready_d[2]_i_10_n_0\, - I2 => m_atarget_enc(0), - I3 => \gen_axilite.s_axi_awready_i_reg\, - I4 => m_atarget_enc(1), - I5 => \s_axi_wready[0]_INST_0_i_2_n_0\, - O => \p_0_out__0\(1) - ); -\m_ready_d[2]_i_9\: unisim.vcomponents.LUT6 - generic map( - INIT => X"A8A8A8080808A808" - ) - port map ( - I0 => p_3_in, - I1 => \m_ready_d[2]_i_11_n_0\, - I2 => m_atarget_enc(0), - I3 => \gen_axilite.s_axi_bvalid_i_reg_1\, - I4 => m_atarget_enc(1), - I5 => \s_axi_bvalid[0]_INST_0_i_2_n_0\, - O => \p_0_out__0\(0) - ); -\m_ready_d_reg[1]_i_4\: unisim.vcomponents.MUXF7 - port map ( - I0 => \^m_ready_d_reg[1]_1\, - I1 => \^m_ready_d_reg[1]_2\, - O => mi_arready_mux, - S => m_atarget_enc(0) - ); -m_valid_i_i_3: unisim.vcomponents.LUT6 - generic map( - INIT => X"A808FFFFA8080000" - ) - port map ( - I0 => m_valid_i_i_5_n_0, - I1 => m_axi_rvalid(1), - I2 => m_atarget_enc(2), - I3 => m_axi_rvalid(4), - I4 => m_atarget_enc(1), - I5 => m_valid_i_i_6_n_0, - O => m_valid_i_i_3_n_0 - ); -m_valid_i_i_4: unisim.vcomponents.LUT6 - generic map( - INIT => X"A808FFFFA8080000" - ) - port map ( - I0 => m_valid_i_i_5_n_0, - I1 => m_axi_rvalid(2), - I2 => m_atarget_enc(2), - I3 => m_axi_rvalid(5), - I4 => m_atarget_enc(1), - I5 => \gen_axilite.s_axi_rvalid_i_reg\, - O => m_valid_i_i_4_n_0 + I0 => m_axi_awready(4), + I1 => m_atarget_enc(3), + I2 => m_atarget_enc(1), + I3 => m_atarget_enc(0), + I4 => \^gen_axilite.s_axi_bvalid_i_reg_0\, + I5 => \m_atarget_enc_reg[2]_5\, + O => \m_ready_d[2]_i_8_n_0\ ); -m_valid_i_i_5: unisim.vcomponents.LUT4 +m_valid_i_i_7: unisim.vcomponents.LUT3 generic map( - INIT => X"0040" + INIT => X"08" ) port map ( - I0 => m_ready_d(0), + I0 => \^m_valid_i\, I1 => \^aa_grant_rnw\, - I2 => \^m_valid_i\, - I3 => m_atarget_enc(3), - O => m_valid_i_i_5_n_0 - ); -m_valid_i_i_6: unisim.vcomponents.LUT6 - generic map( - INIT => X"00CC88C0000088C0" - ) - port map ( - I0 => m_axi_rvalid(6), - I1 => \^m_ready_d_reg[0]\, - I2 => m_axi_rvalid(0), - I3 => m_atarget_enc(3), - I4 => m_atarget_enc(2), - I5 => m_axi_rvalid(3), - O => m_valid_i_i_6_n_0 - ); -m_valid_i_reg_i_2: unisim.vcomponents.MUXF7 - port map ( - I0 => m_valid_i_i_3_n_0, - I1 => m_valid_i_i_4_n_0, - O => aa_rvalid, - S => m_atarget_enc(0) + I2 => m_ready_d_1(0), + O => s_ready_i_reg ); \s_arvalid_reg[0]_i_1\: unisim.vcomponents.LUT4 generic map( @@ -2208,12 +2175,12 @@ m_valid_i_reg_i_2: unisim.vcomponents.MUXF7 ); \s_awvalid_reg[0]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"0000000000A20000" + INIT => X"0000000000D00000" ) port map ( - I0 => s_axi_awvalid(0), - I1 => s_axi_arvalid(0), - I2 => s_awvalid_reg, + I0 => s_axi_arvalid(0), + I1 => s_awvalid_reg, + I2 => s_axi_awvalid(0), I3 => \s_arvalid_reg_reg_n_0_[0]\, I4 => aresetn_d, I5 => s_ready_i, @@ -2232,8 +2199,8 @@ m_valid_i_reg_i_2: unisim.vcomponents.MUXF7 INIT => X"8" ) port map ( - I0 => \^aa_grant_rnw\, - I1 => s_ready_i, + I0 => s_ready_i, + I1 => \^aa_grant_rnw\, O => s_axi_arready(0) ); \s_axi_awready[0]_INST_0\: unisim.vcomponents.LUT2 @@ -2245,65 +2212,18 @@ m_valid_i_reg_i_2: unisim.vcomponents.MUXF7 I1 => \^aa_grant_rnw\, O => s_axi_awready(0) ); -\s_axi_bvalid[0]_INST_0\: unisim.vcomponents.LUT2 +\s_axi_bvalid[0]_INST_0\: unisim.vcomponents.LUT5 generic map( - INIT => X"8" + INIT => X"00400000" ) port map ( - I0 => aa_grant_any, - I1 => \^aa_bvalid\, + I0 => \^aa_grant_rnw\, + I1 => \^m_valid_i\, + I2 => aa_grant_any, + I3 => m_ready_d(0), + I4 => \m_atarget_enc_reg[2]_0\, O => s_axi_bvalid(0) ); -\s_axi_bvalid[0]_INST_0_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => \s_axi_bvalid[0]_INST_0_i_2_n_0\, - I1 => \gen_axilite.s_axi_bvalid_i_reg_1\, - I2 => m_atarget_enc(0), - I3 => \s_axi_bvalid[0]_INST_0_i_4_n_0\, - I4 => m_atarget_enc(1), - I5 => \s_axi_bvalid[0]_INST_0_i_5_n_0\, - O => \^aa_bvalid\ - ); -\s_axi_bvalid[0]_INST_0_i_2\: unisim.vcomponents.LUT5 - generic map( - INIT => X"44400040" - ) - port map ( - I0 => m_atarget_enc(3), - I1 => \^m_ready_d_reg[0]_0\, - I2 => m_axi_bvalid(2), - I3 => m_atarget_enc(2), - I4 => m_axi_bvalid(5), - O => \s_axi_bvalid[0]_INST_0_i_2_n_0\ - ); -\s_axi_bvalid[0]_INST_0_i_4\: unisim.vcomponents.LUT5 - generic map( - INIT => X"44400040" - ) - port map ( - I0 => m_atarget_enc(3), - I1 => \^m_ready_d_reg[0]_0\, - I2 => m_axi_bvalid(1), - I3 => m_atarget_enc(2), - I4 => m_axi_bvalid(4), - O => \s_axi_bvalid[0]_INST_0_i_4_n_0\ - ); -\s_axi_bvalid[0]_INST_0_i_5\: unisim.vcomponents.LUT6 - generic map( - INIT => X"00CC88C0000088C0" - ) - port map ( - I0 => m_axi_bvalid(6), - I1 => \^m_ready_d_reg[0]_0\, - I2 => m_axi_bvalid(0), - I3 => m_atarget_enc(3), - I4 => m_atarget_enc(2), - I5 => m_axi_bvalid(3), - O => \s_axi_bvalid[0]_INST_0_i_5_n_0\ - ); \s_axi_rvalid[0]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"8" @@ -2313,64 +2233,36 @@ m_valid_i_reg_i_2: unisim.vcomponents.MUXF7 I1 => sr_rvalid, O => s_axi_rvalid(0) ); -\s_axi_wready[0]_INST_0\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => aa_grant_any, - I1 => \^aa_wready\, - O => s_axi_wready(0) - ); -\s_axi_wready[0]_INST_0_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AFA0CFCFAFA0C0C0" - ) - port map ( - I0 => \s_axi_wready[0]_INST_0_i_2_n_0\, - I1 => \gen_axilite.s_axi_awready_i_reg\, - I2 => m_atarget_enc(0), - I3 => \s_axi_wready[0]_INST_0_i_4_n_0\, - I4 => m_atarget_enc(1), - I5 => \s_axi_wready[0]_INST_0_i_5_n_0\, - O => \^aa_wready\ - ); -\s_axi_wready[0]_INST_0_i_2\: unisim.vcomponents.LUT5 +\s_axi_wready[0]_INST_0\: unisim.vcomponents.LUT2 generic map( - INIT => X"44400040" + INIT => X"2" ) port map ( - I0 => m_atarget_enc(3), - I1 => \^m_ready_d_reg[1]_0\, - I2 => m_axi_wready(2), - I3 => m_atarget_enc(2), - I4 => m_axi_wready(5), - O => \s_axi_wready[0]_INST_0_i_2_n_0\ + I0 => aa_grant_any, + I1 => \s_axi_wready[0]_INST_0_i_1_n_0\, + O => s_axi_wready(0) ); -\s_axi_wready[0]_INST_0_i_4\: unisim.vcomponents.LUT5 +\s_axi_wready[0]_INST_0_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"44400040" + INIT => X"EEEFEEEEEEEEEEEE" ) port map ( - I0 => m_atarget_enc(3), - I1 => \^m_ready_d_reg[1]_0\, - I2 => m_axi_wready(1), - I3 => m_atarget_enc(2), - I4 => m_axi_wready(4), - O => \s_axi_wready[0]_INST_0_i_4_n_0\ + I0 => \s_axi_wready[0]_INST_0_i_2_n_0\, + I1 => m_ready_d(1), + I2 => \m_atarget_enc_reg[2]_1\, + I3 => \m_atarget_enc_reg[2]_2\, + I4 => \m_atarget_enc_reg[3]_1\, + I5 => \m_atarget_enc_reg[2]_3\, + O => \s_axi_wready[0]_INST_0_i_1_n_0\ ); -\s_axi_wready[0]_INST_0_i_5\: unisim.vcomponents.LUT6 +\s_axi_wready[0]_INST_0_i_2\: unisim.vcomponents.LUT2 generic map( - INIT => X"00CC88C0000088C0" + INIT => X"B" ) port map ( - I0 => m_axi_wready(6), - I1 => \^m_ready_d_reg[1]_0\, - I2 => m_axi_wready(0), - I3 => m_atarget_enc(3), - I4 => m_atarget_enc(2), - I5 => m_axi_wready(3), - O => \s_axi_wready[0]_INST_0_i_5_n_0\ + I0 => \^aa_grant_rnw\, + I1 => \^m_valid_i\, + O => \s_axi_wready[0]_INST_0_i_2_n_0\ ); end STRUCTURE; library IEEE; @@ -2381,29 +2273,41 @@ entity Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_decerr_slave is port ( mi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); mi_wready : out STD_LOGIC_VECTOR ( 0 to 0 ); - \m_ready_d_reg[1]\ : out STD_LOGIC; - m_valid_i_reg : out STD_LOGIC; \m_ready_d_reg[2]\ : out STD_LOGIC; + \m_ready_d_reg[2]_0\ : out STD_LOGIC; + s_ready_i_reg : out STD_LOGIC; + \m_ready_d_reg[1]\ : out STD_LOGIC; \m_ready_d_reg[1]_0\ : out STD_LOGIC; - \m_ready_d_reg[0]\ : out STD_LOGIC; - SR : in STD_LOGIC_VECTOR ( 0 to 0 ); - \gen_axilite.s_axi_bvalid_i_reg_0\ : in STD_LOGIC; + \m_ready_d_reg[2]_1\ : out STD_LOGIC; + \s_axi_wready[0]\ : out STD_LOGIC; + reset : in STD_LOGIC; + \m_atarget_hot_reg[11]\ : in STD_LOGIC; aclk : in STD_LOGIC; - \gen_no_arbiter.m_valid_i_reg\ : in STD_LOGIC; - m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 ); - m_atarget_enc : in STD_LOGIC_VECTOR ( 1 downto 0 ); - \gen_no_arbiter.m_valid_i_reg_0\ : in STD_LOGIC; - m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \m_atarget_enc_reg[2]\ : in STD_LOGIC; + \m_atarget_enc_reg[2]_0\ : in STD_LOGIC; + \m_atarget_enc_reg[2]_1\ : in STD_LOGIC; + m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_no_arbiter.grant_rnw_reg\ : in STD_LOGIC; + \m_ready_d_reg[2]_2\ : in STD_LOGIC; m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 ); - \gen_no_arbiter.grant_rnw_reg_0\ : in STD_LOGIC; - m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 ); - \gen_no_arbiter.grant_rnw_reg_1\ : in STD_LOGIC; - m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_atarget_enc : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \m_atarget_enc_reg[2]_2\ : in STD_LOGIC; + \m_atarget_enc_reg[3]\ : in STD_LOGIC; + \m_atarget_enc_reg[3]_0\ : in STD_LOGIC; + \gen_no_arbiter.m_valid_i_reg\ : in STD_LOGIC; aa_rready : in STD_LOGIC; + m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \m_atarget_enc_reg[0]\ : in STD_LOGIC; + m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \m_atarget_enc_reg[2]_3\ : in STD_LOGIC; + \m_atarget_enc_reg[1]\ : in STD_LOGIC; + m_axi_wready : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \m_atarget_enc_reg[2]_4\ : in STD_LOGIC; + \m_ready_d_reg[1]_1\ : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 0 to 0 ); aresetn_d : in STD_LOGIC; - p_4_in : in STD_LOGIC + \m_ready_d_reg[1]_2\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_decerr_slave : entity is "axi_crossbar_v2_1_12_decerr_slave"; @@ -2413,23 +2317,26 @@ architecture STRUCTURE of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_decerr_slave is signal \gen_axilite.s_axi_arready_i_i_1_n_0\ : STD_LOGIC; signal \gen_axilite.s_axi_awready_i_i_1_n_0\ : STD_LOGIC; signal \gen_axilite.s_axi_rvalid_i_i_1_n_0\ : STD_LOGIC; - signal mi_arready : STD_LOGIC_VECTOR ( 9 to 9 ); + signal \m_ready_d[2]_i_12_n_0\ : STD_LOGIC; + signal m_valid_i_i_3_n_0 : STD_LOGIC; + signal mi_arready : STD_LOGIC_VECTOR ( 11 to 11 ); signal \^mi_bvalid\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal mi_rvalid : STD_LOGIC_VECTOR ( 9 to 9 ); + signal mi_rvalid : STD_LOGIC_VECTOR ( 11 to 11 ); signal \^mi_wready\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \s_axi_bvalid[0]_INST_0_i_3_n_0\ : STD_LOGIC; begin mi_bvalid(0) <= \^mi_bvalid\(0); mi_wready(0) <= \^mi_wready\(0); \gen_axilite.s_axi_arready_i_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"88882AAA" + INIT => X"882A88AA" ) port map ( I0 => aresetn_d, - I1 => mi_arready(9), + I1 => mi_arready(11), I2 => Q(0), - I3 => \gen_no_arbiter.m_valid_i_reg\, - I4 => mi_rvalid(9), + I3 => mi_rvalid(11), + I4 => \m_ready_d_reg[1]_1\, O => \gen_axilite.s_axi_arready_i_i_1_n_0\ ); \gen_axilite.s_axi_arready_i_reg\: unisim.vcomponents.FDRE @@ -2437,18 +2344,18 @@ begin C => aclk, CE => '1', D => \gen_axilite.s_axi_arready_i_i_1_n_0\, - Q => mi_arready(9), + Q => mi_arready(11), R => '0' ); \gen_axilite.s_axi_awready_i_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"BFFF4000" + INIT => X"EFFF1000" ) port map ( I0 => \^mi_bvalid\(0), - I1 => \gen_no_arbiter.grant_rnw_reg\, - I2 => p_4_in, - I3 => Q(0), + I1 => \m_ready_d_reg[2]_2\, + I2 => Q(0), + I3 => \m_ready_d_reg[1]_2\, I4 => \^mi_wready\(0), O => \gen_axilite.s_axi_awready_i_i_1_n_0\ ); @@ -2458,26 +2365,26 @@ begin CE => '1', D => \gen_axilite.s_axi_awready_i_i_1_n_0\, Q => \^mi_wready\(0), - R => SR(0) + R => reset ); \gen_axilite.s_axi_bvalid_i_reg\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', - D => \gen_axilite.s_axi_bvalid_i_reg_0\, + D => \m_atarget_hot_reg[11]\, Q => \^mi_bvalid\(0), - R => SR(0) + R => reset ); \gen_axilite.s_axi_rvalid_i_i_1\: unisim.vcomponents.LUT5 generic map( - INIT => X"74CC44CC" + INIT => X"5CF050F0" ) port map ( I0 => aa_rready, - I1 => mi_rvalid(9), - I2 => \gen_no_arbiter.m_valid_i_reg\, + I1 => \m_ready_d_reg[1]_1\, + I2 => mi_rvalid(11), I3 => Q(0), - I4 => mi_arready(9), + I4 => mi_arready(11), O => \gen_axilite.s_axi_rvalid_i_i_1_n_0\ ); \gen_axilite.s_axi_rvalid_i_reg\: unisim.vcomponents.FDRE @@ -2485,73 +2392,134 @@ begin C => aclk, CE => '1', D => \gen_axilite.s_axi_rvalid_i_i_1_n_0\, - Q => mi_rvalid(9), - R => SR(0) + Q => mi_rvalid(11), + R => reset ); -\m_ready_d[1]_i_9\: unisim.vcomponents.LUT6 +\m_ready_d[1]_i_5\: unisim.vcomponents.LUT6 generic map( - INIT => X"00CC88C0000088C0" + INIT => X"003300B8000000B8" ) port map ( - I0 => mi_arready(9), - I1 => \gen_no_arbiter.m_valid_i_reg\, + I0 => m_axi_arready(1), + I1 => m_atarget_enc(2), I2 => m_axi_arready(0), - I3 => m_atarget_enc(1), - I4 => m_atarget_enc(0), - I5 => m_axi_arready(1), - O => \m_ready_d_reg[1]\ + I3 => \m_atarget_enc_reg[0]\, + I4 => m_atarget_enc(3), + I5 => mi_arready(11), + O => \m_ready_d_reg[1]_0\ ); -\m_ready_d[2]_i_5\: unisim.vcomponents.LUT6 +\m_ready_d[2]_i_12\: unisim.vcomponents.LUT4 generic map( - INIT => X"00CC88C0000088C0" + INIT => X"4FFF" ) port map ( I0 => \^mi_wready\(0), - I1 => \gen_no_arbiter.grant_rnw_reg\, - I2 => m_axi_awready(0), - I3 => m_atarget_enc(1), - I4 => m_atarget_enc(0), - I5 => m_axi_awready(1), + I1 => m_atarget_enc(3), + I2 => m_atarget_enc(1), + I3 => m_atarget_enc(0), + O => \m_ready_d[2]_i_12_n_0\ + ); +\m_ready_d[2]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000FFFF00000001" + ) + port map ( + I0 => \m_atarget_enc_reg[2]\, + I1 => \s_axi_bvalid[0]_INST_0_i_3_n_0\, + I2 => \m_atarget_enc_reg[2]_0\, + I3 => \m_atarget_enc_reg[2]_1\, + I4 => m_ready_d(0), + I5 => \gen_no_arbiter.grant_rnw_reg\, O => \m_ready_d_reg[2]\ ); -m_valid_i_i_7: unisim.vcomponents.LUT6 +\m_ready_d[2]_i_5\: unisim.vcomponents.LUT6 generic map( - INIT => X"00CC88C0000088C0" + INIT => X"EFEEEFEEEFEE0000" ) port map ( - I0 => mi_rvalid(9), - I1 => \gen_no_arbiter.m_valid_i_reg_0\, - I2 => m_axi_rvalid(0), - I3 => m_atarget_enc(1), - I4 => m_atarget_enc(0), + I0 => \m_atarget_enc_reg[2]_3\, + I1 => \m_atarget_enc_reg[1]\, + I2 => m_axi_wready(2), + I3 => m_atarget_enc(3), + I4 => \m_ready_d[2]_i_12_n_0\, + I5 => \m_atarget_enc_reg[2]_4\, + O => \m_ready_d_reg[2]_1\ + ); +\m_ready_d[2]_i_9\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0011101100111000" + ) + port map ( + I0 => \m_ready_d[2]_i_12_n_0\, + I1 => \m_ready_d_reg[2]_2\, + I2 => m_axi_awready(1), + I3 => m_atarget_enc(2), + I4 => m_atarget_enc(3), + I5 => m_axi_awready(0), + O => \m_ready_d_reg[2]_0\ + ); +m_valid_i_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"DFFF0000FFFFFFFF" + ) + port map ( + I0 => m_valid_i_i_3_n_0, + I1 => \m_atarget_enc_reg[2]_2\, + I2 => \m_atarget_enc_reg[3]\, + I3 => \m_atarget_enc_reg[3]_0\, + I4 => \gen_no_arbiter.m_valid_i_reg\, + I5 => aa_rready, + O => s_ready_i_reg + ); +m_valid_i_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"FCDCFCDFFFDCFFDF" + ) + port map ( + I0 => mi_rvalid(11), + I1 => \m_atarget_enc_reg[0]\, + I2 => m_atarget_enc(3), + I3 => m_atarget_enc(2), + I4 => m_axi_rvalid(0), I5 => m_axi_rvalid(1), - O => m_valid_i_reg + O => m_valid_i_i_3_n_0 + ); +\s_axi_bvalid[0]_INST_0_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \m_atarget_enc_reg[2]\, + I1 => \s_axi_bvalid[0]_INST_0_i_3_n_0\, + I2 => \m_atarget_enc_reg[2]_0\, + I3 => \m_atarget_enc_reg[2]_1\, + O => \m_ready_d_reg[1]\ ); \s_axi_bvalid[0]_INST_0_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"00CC88C0000088C0" + INIT => X"003300B8000000B8" ) port map ( - I0 => \^mi_bvalid\(0), - I1 => \gen_no_arbiter.grant_rnw_reg_1\, + I0 => m_axi_bvalid(1), + I1 => m_atarget_enc(2), I2 => m_axi_bvalid(0), - I3 => m_atarget_enc(1), - I4 => m_atarget_enc(0), - I5 => m_axi_bvalid(1), - O => \m_ready_d_reg[0]\ + I3 => \m_atarget_enc_reg[0]\, + I4 => m_atarget_enc(3), + I5 => \^mi_bvalid\(0), + O => \s_axi_bvalid[0]_INST_0_i_3_n_0\ ); -\s_axi_wready[0]_INST_0_i_3\: unisim.vcomponents.LUT6 +\s_axi_wready[0]_INST_0_i_6\: unisim.vcomponents.LUT6 generic map( - INIT => X"00CC88C0000088C0" + INIT => X"FFAAFF1BFFFFFF1B" ) port map ( - I0 => \^mi_wready\(0), - I1 => \gen_no_arbiter.grant_rnw_reg_0\, - I2 => m_axi_wready(0), - I3 => m_atarget_enc(1), - I4 => m_atarget_enc(0), - I5 => m_axi_wready(1), - O => \m_ready_d_reg[1]_0\ + I0 => m_atarget_enc(2), + I1 => m_axi_wready(0), + I2 => m_axi_wready(1), + I3 => \m_atarget_enc_reg[0]\, + I4 => m_atarget_enc(3), + I5 => \^mi_wready\(0), + O => \s_axi_wready[0]\ ); end STRUCTURE; library IEEE; @@ -2560,25 +2528,30 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_splitter is port ( - \gen_no_arbiter.m_valid_i_reg\ : out STD_LOGIC; - \gen_no_arbiter.m_valid_i_reg_0\ : out STD_LOGIC; - \gen_no_arbiter.m_valid_i_reg_1\ : out STD_LOGIC; - \gen_no_arbiter.m_valid_i_reg_2\ : out STD_LOGIC; + \m_ready_d_reg[2]_0\ : out STD_LOGIC; + \m_ready_d_reg[2]_1\ : out STD_LOGIC; + \m_ready_d_reg[2]_2\ : out STD_LOGIC; + \m_ready_d_reg[2]_3\ : out STD_LOGIC; + \m_ready_d_reg[2]_4\ : out STD_LOGIC; + \m_ready_d_reg[2]_5\ : out STD_LOGIC; + \m_ready_d_reg[2]_6\ : out STD_LOGIC; + \m_ready_d_reg[2]_7\ : out STD_LOGIC; + \m_ready_d_reg[2]_8\ : out STD_LOGIC; + \m_ready_d_reg[2]_9\ : out STD_LOGIC; + \m_ready_d_reg[2]_10\ : out STD_LOGIC; + \m_ready_d_reg[2]_11\ : out STD_LOGIC; + \m_ready_d_reg[2]_12\ : out STD_LOGIC; m_ready_d : out STD_LOGIC_VECTOR ( 2 downto 0 ); - m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 ); - m_atarget_enc : in STD_LOGIC_VECTOR ( 1 downto 0 ); - m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 ); - m_valid_i : in STD_LOGIC; - aa_grant_rnw : in STD_LOGIC; - mi_awready_mux : in STD_LOGIC; + m_axi_bvalid : in STD_LOGIC_VECTOR ( 8 downto 0 ); + m_atarget_enc : in STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_wready : in STD_LOGIC_VECTOR ( 9 downto 0 ); + \m_atarget_enc_reg[0]\ : in STD_LOGIC; + m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 ); aresetn_d : in STD_LOGIC; - aa_awready : in STD_LOGIC; - aa_wready : in STD_LOGIC; - \gen_no_arbiter.grant_rnw_reg\ : in STD_LOGIC; - s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); - aa_bvalid : in STD_LOGIC; - s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); - \gen_no_arbiter.grant_rnw_reg_0\ : in STD_LOGIC; + m_ready_d0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + \m_ready_d_reg[0]_0\ : in STD_LOGIC; + \m_ready_d_reg[2]_13\ : in STD_LOGIC; + \gen_no_arbiter.m_valid_i_reg\ : in STD_LOGIC; aclk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; @@ -2586,102 +2559,125 @@ entity Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_splitter is end Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_splitter; architecture STRUCTURE of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_splitter is - signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC; signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC; signal \m_ready_d[2]_i_1_n_0\ : STD_LOGIC; + signal \^m_ready_d_reg[2]_1\ : STD_LOGIC; + signal \^m_ready_d_reg[2]_4\ : STD_LOGIC; attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \m_ready_d[2]_i_12\ : label is "soft_lutpair44"; - attribute SOFT_HLUTNM of \m_ready_d[2]_i_14\ : label is "soft_lutpair44"; + attribute SOFT_HLUTNM of \m_ready_d[0]_i_1\ : label is "soft_lutpair61"; + attribute SOFT_HLUTNM of \m_ready_d[2]_i_1\ : label is "soft_lutpair61"; + attribute SOFT_HLUTNM of \m_ready_d[2]_i_11\ : label is "soft_lutpair59"; + attribute SOFT_HLUTNM of \m_ready_d[2]_i_14\ : label is "soft_lutpair59"; + attribute SOFT_HLUTNM of \m_ready_d[2]_i_15\ : label is "soft_lutpair60"; + attribute SOFT_HLUTNM of \s_axi_wready[0]_INST_0_i_8\ : label is "soft_lutpair60"; begin - m_ready_d(2 downto 0) <= \^m_ready_d\(2 downto 0); -\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6 + \m_ready_d_reg[2]_1\ <= \^m_ready_d_reg[2]_1\; + \m_ready_d_reg[2]_4\ <= \^m_ready_d_reg[2]_4\; +\m_ready_d[0]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"00000000FF800000" + INIT => X"4404" ) port map ( - I0 => aa_bvalid, - I1 => s_axi_bready(0), - I2 => \gen_no_arbiter.grant_rnw_reg_0\, - I3 => \^m_ready_d\(0), - I4 => aresetn_d, - I5 => aa_awready, + I0 => \m_ready_d_reg[0]_0\, + I1 => aresetn_d, + I2 => m_ready_d0(0), + I3 => \gen_no_arbiter.m_valid_i_reg\, O => \m_ready_d[0]_i_1_n_0\ ); -\m_ready_d[1]_i_1\: unisim.vcomponents.LUT6 +\m_ready_d[1]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"00000000FF800000" + INIT => X"80" ) port map ( - I0 => aa_wready, - I1 => \gen_no_arbiter.grant_rnw_reg\, - I2 => s_axi_wvalid(0), - I3 => \^m_ready_d\(1), - I4 => aresetn_d, - I5 => aa_awready, + I0 => aresetn_d, + I1 => m_ready_d0(0), + I2 => \gen_no_arbiter.m_valid_i_reg\, O => \m_ready_d[1]_i_1_n_0\ ); -\m_ready_d[2]_i_1\: unisim.vcomponents.LUT6 +\m_ready_d[2]_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"00000000AEAA0000" + INIT => X"00A2" ) port map ( - I0 => \^m_ready_d\(2), - I1 => m_valid_i, - I2 => aa_grant_rnw, - I3 => mi_awready_mux, - I4 => aresetn_d, - I5 => aa_awready, + I0 => aresetn_d, + I1 => m_ready_d0(0), + I2 => \m_ready_d_reg[0]_0\, + I3 => \m_ready_d_reg[2]_13\, O => \m_ready_d[2]_i_1_n_0\ ); -\m_ready_d[2]_i_12\: unisim.vcomponents.LUT3 +\m_ready_d[2]_i_10\: unisim.vcomponents.LUT4 generic map( - INIT => X"B8" + INIT => X"5053" + ) + port map ( + I0 => m_axi_wready(4), + I1 => m_axi_wready(0), + I2 => m_atarget_enc(2), + I3 => m_atarget_enc(3), + O => \m_ready_d_reg[2]_9\ + ); +\m_ready_d[2]_i_11\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FEEE" ) port map ( - I0 => m_axi_wready(3), + I0 => m_atarget_enc(1), I1 => m_atarget_enc(0), - I2 => m_axi_wready(1), - O => \gen_no_arbiter.m_valid_i_reg_0\ + I2 => m_atarget_enc(3), + I3 => m_atarget_enc(2), + O => \m_ready_d_reg[2]_11\ ); \m_ready_d[2]_i_13\: unisim.vcomponents.LUT4 generic map( - INIT => X"3B38" + INIT => X"F053" ) port map ( - I0 => m_axi_wready(2), - I1 => m_atarget_enc(0), - I2 => m_atarget_enc(1), - I3 => m_axi_wready(0), - O => \gen_no_arbiter.m_valid_i_reg\ + I0 => m_axi_wready(7), + I1 => m_axi_wready(3), + I2 => m_atarget_enc(2), + I3 => m_atarget_enc(3), + O => \m_ready_d_reg[2]_8\ ); -\m_ready_d[2]_i_14\: unisim.vcomponents.LUT3 +\m_ready_d[2]_i_14\: unisim.vcomponents.LUT4 generic map( - INIT => X"B8" + INIT => X"FF4F" ) port map ( - I0 => m_axi_bvalid(3), - I1 => m_atarget_enc(0), - I2 => m_axi_bvalid(1), - O => \gen_no_arbiter.m_valid_i_reg_2\ + I0 => m_axi_awready(3), + I1 => m_atarget_enc(3), + I2 => m_atarget_enc(0), + I3 => m_atarget_enc(1), + O => \m_ready_d_reg[2]_7\ ); \m_ready_d[2]_i_15\: unisim.vcomponents.LUT4 generic map( - INIT => X"3B38" + INIT => X"FFF4" ) port map ( - I0 => m_axi_bvalid(2), - I1 => m_atarget_enc(0), + I0 => m_axi_awready(2), + I1 => m_atarget_enc(3), I2 => m_atarget_enc(1), - I3 => m_axi_bvalid(0), - O => \gen_no_arbiter.m_valid_i_reg_1\ + I3 => m_atarget_enc(0), + O => \m_ready_d_reg[2]_12\ + ); +\m_ready_d[2]_i_16\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F053" + ) + port map ( + I0 => m_axi_awready(1), + I1 => m_axi_awready(0), + I2 => m_atarget_enc(2), + I3 => m_atarget_enc(3), + O => \m_ready_d_reg[2]_10\ ); \m_ready_d_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_ready_d[0]_i_1_n_0\, - Q => \^m_ready_d\(0), + Q => m_ready_d(0), R => '0' ); \m_ready_d_reg[1]\: unisim.vcomponents.FDRE @@ -2689,7 +2685,7 @@ begin C => aclk, CE => '1', D => \m_ready_d[1]_i_1_n_0\, - Q => \^m_ready_d\(1), + Q => m_ready_d(1), R => '0' ); \m_ready_d_reg[2]\: unisim.vcomponents.FDRE @@ -2697,9 +2693,92 @@ begin C => aclk, CE => '1', D => \m_ready_d[2]_i_1_n_0\, - Q => \^m_ready_d\(2), + Q => m_ready_d(2), R => '0' ); +\s_axi_bvalid[0]_INST_0_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"003300B8000000B8" + ) + port map ( + I0 => m_axi_bvalid(5), + I1 => m_atarget_enc(2), + I2 => m_axi_bvalid(2), + I3 => \^m_ready_d_reg[2]_1\, + I4 => m_atarget_enc(3), + I5 => m_axi_bvalid(8), + O => \m_ready_d_reg[2]_0\ + ); +\s_axi_bvalid[0]_INST_0_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"003300B8000000B8" + ) + port map ( + I0 => m_axi_bvalid(4), + I1 => m_atarget_enc(2), + I2 => m_axi_bvalid(1), + I3 => \^m_ready_d_reg[2]_4\, + I4 => m_atarget_enc(3), + I5 => m_axi_bvalid(7), + O => \m_ready_d_reg[2]_5\ + ); +\s_axi_bvalid[0]_INST_0_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"003300B8000000B8" + ) + port map ( + I0 => m_axi_bvalid(3), + I1 => m_atarget_enc(2), + I2 => m_axi_bvalid(0), + I3 => \m_atarget_enc_reg[0]\, + I4 => m_atarget_enc(3), + I5 => m_axi_bvalid(6), + O => \m_ready_d_reg[2]_6\ + ); +\s_axi_wready[0]_INST_0_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"003300B8000000B8" + ) + port map ( + I0 => m_axi_wready(5), + I1 => m_atarget_enc(2), + I2 => m_axi_wready(1), + I3 => \^m_ready_d_reg[2]_4\, + I4 => m_atarget_enc(3), + I5 => m_axi_wready(8), + O => \m_ready_d_reg[2]_3\ + ); +\s_axi_wready[0]_INST_0_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"003300B8000000B8" + ) + port map ( + I0 => m_axi_wready(6), + I1 => m_atarget_enc(2), + I2 => m_axi_wready(2), + I3 => \^m_ready_d_reg[2]_1\, + I4 => m_atarget_enc(3), + I5 => m_axi_wready(9), + O => \m_ready_d_reg[2]_2\ + ); +\s_axi_wready[0]_INST_0_i_7\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => m_atarget_enc(1), + I1 => m_atarget_enc(0), + O => \^m_ready_d_reg[2]_4\ + ); +\s_axi_wready[0]_INST_0_i_8\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => m_atarget_enc(0), + I1 => m_atarget_enc(1), + O => \^m_ready_d_reg[2]_1\ + ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; @@ -2707,16 +2786,23 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_splitter__parameterized0\ is port ( - \gen_no_arbiter.m_valid_i_reg\ : out STD_LOGIC; + \m_ready_d_reg[1]_0\ : out STD_LOGIC; + \m_ready_d_reg[1]_1\ : out STD_LOGIC; + \m_ready_d_reg[1]_2\ : out STD_LOGIC; m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 ); - \m_payload_i_reg[0]\ : in STD_LOGIC; - \m_atarget_enc_reg[2]\ : in STD_LOGIC; - m_atarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 ); - \m_atarget_enc_reg[2]_0\ : in STD_LOGIC; - \gen_no_arbiter.m_valid_i_reg_0\ : in STD_LOGIC; + m_axi_arready : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \m_atarget_enc_reg[0]\ : in STD_LOGIC; + m_atarget_enc : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \m_atarget_enc_reg[0]_0\ : in STD_LOGIC; + \m_atarget_enc_reg[1]\ : in STD_LOGIC; aresetn_d : in STD_LOGIC; - mi_arready_mux : in STD_LOGIC; - \gen_no_arbiter.m_valid_i_reg_1\ : in STD_LOGIC; + m_ready_d0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + \m_ready_d_reg[0]_0\ : in STD_LOGIC; + s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_no_arbiter.grant_rnw_reg\ : in STD_LOGIC; + sr_rvalid : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + aresetn_d_reg : in STD_LOGIC; aclk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; @@ -2729,44 +2815,67 @@ architecture STRUCTURE of \Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_splitter__para signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC; begin m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0); -\gen_no_arbiter.m_valid_i_i_2\: unisim.vcomponents.LUT6 +\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"EEEEEEEEE0EEE000" + INIT => X"00000000AEAAAAAA" ) port map ( - I0 => \m_payload_i_reg[0]\, - I1 => \^m_ready_d\(0), - I2 => \m_atarget_enc_reg[2]\, - I3 => m_atarget_enc(0), - I4 => \m_atarget_enc_reg[2]_0\, - I5 => \^m_ready_d\(1), - O => \gen_no_arbiter.m_valid_i_reg\ + I0 => \^m_ready_d\(0), + I1 => s_axi_rready(0), + I2 => \gen_no_arbiter.grant_rnw_reg\, + I3 => sr_rvalid, + I4 => Q(0), + I5 => aresetn_d_reg, + O => \m_ready_d[0]_i_1_n_0\ ); -\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6 +\m_ready_d[1]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"000000000000CC80" + INIT => X"80" ) port map ( - I0 => \gen_no_arbiter.m_valid_i_reg_1\, - I1 => aresetn_d, - I2 => \m_payload_i_reg[0]\, - I3 => \^m_ready_d\(0), - I4 => mi_arready_mux, - I5 => \^m_ready_d\(1), - O => \m_ready_d[0]_i_1_n_0\ + I0 => aresetn_d, + I1 => m_ready_d0(0), + I2 => \m_ready_d_reg[0]_0\, + O => \m_ready_d[1]_i_1_n_0\ ); -\m_ready_d[1]_i_1\: unisim.vcomponents.LUT6 +\m_ready_d[1]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C000C00080000" + INIT => X"003300B8000000B8" ) port map ( - I0 => \gen_no_arbiter.m_valid_i_reg_0\, - I1 => aresetn_d, - I2 => \m_payload_i_reg[0]\, - I3 => \^m_ready_d\(0), - I4 => mi_arready_mux, - I5 => \^m_ready_d\(1), - O => \m_ready_d[1]_i_1_n_0\ + I0 => m_axi_arready(4), + I1 => m_atarget_enc(0), + I2 => m_axi_arready(1), + I3 => \m_atarget_enc_reg[1]\, + I4 => m_atarget_enc(1), + I5 => m_axi_arready(7), + O => \m_ready_d_reg[1]_2\ + ); +\m_ready_d[1]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FCDCFCDFFFDCFFDF" + ) + port map ( + I0 => m_axi_arready(8), + I1 => \m_atarget_enc_reg[0]\, + I2 => m_atarget_enc(1), + I3 => m_atarget_enc(0), + I4 => m_axi_arready(2), + I5 => m_axi_arready(5), + O => \m_ready_d_reg[1]_0\ + ); +\m_ready_d[1]_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"003300B8000000B8" + ) + port map ( + I0 => m_axi_arready(3), + I1 => m_atarget_enc(0), + I2 => m_axi_arready(0), + I3 => \m_atarget_enc_reg[0]_0\, + I4 => m_atarget_enc(1), + I5 => m_axi_arready(6), + O => \m_ready_d_reg[1]_1\ ); \m_ready_d_reg[0]\: unisim.vcomponents.FDRE port map ( @@ -2793,150 +2902,233 @@ entity Arty_Z7_20_xbar_0_axi_register_slice_v2_1_11_axic_register_slice is port ( sr_rvalid : out STD_LOGIC; aa_rready : out STD_LOGIC; - \m_ready_d_reg[1]\ : out STD_LOGIC; - \skid_buffer_reg[1]_0\ : out STD_LOGIC; - \skid_buffer_reg[1]_1\ : out STD_LOGIC; - \skid_buffer_reg[1]_2\ : out STD_LOGIC; - \skid_buffer_reg[1]_3\ : out STD_LOGIC; - m_axi_rready : out STD_LOGIC_VECTOR ( 8 downto 0 ); - \s_axi_rdata[31]\ : out STD_LOGIC_VECTOR ( 33 downto 0 ); + \gen_no_arbiter.m_grant_hot_i_reg[0]\ : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 34 downto 0 ); + \skid_buffer_reg[30]_0\ : out STD_LOGIC; + \m_payload_i_reg[2]_0\ : out STD_LOGIC; + \m_payload_i_reg[2]_1\ : out STD_LOGIC; + \m_payload_i_reg[1]_0\ : out STD_LOGIC; + \skid_buffer_reg[9]_0\ : out STD_LOGIC; + s_ready_i_reg_0 : out STD_LOGIC; + s_ready_i_reg_1 : out STD_LOGIC; + \m_ready_d_reg[2]\ : out STD_LOGIC; + s_ready_i_reg_2 : out STD_LOGIC; + s_ready_i_reg_3 : out STD_LOGIC; + m_axi_rready : out STD_LOGIC_VECTOR ( 10 downto 0 ); aclk : in STD_LOGIC; - aa_rvalid : in STD_LOGIC; + s_ready_i_reg_4 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 21 downto 0 ); + m_atarget_enc : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 ); - aa_grant_rnw : in STD_LOGIC; m_valid_i : in STD_LOGIC; - m_axi_rresp : in STD_LOGIC_VECTOR ( 17 downto 0 ); - m_atarget_enc : in STD_LOGIC_VECTOR ( 3 downto 0 ); - m_axi_rdata : in STD_LOGIC_VECTOR ( 287 downto 0 ); - Q : in STD_LOGIC_VECTOR ( 8 downto 0 ); - SR : in STD_LOGIC_VECTOR ( 0 to 0 ) + aa_grant_rnw : in STD_LOGIC; + m_axi_rdata : in STD_LOGIC_VECTOR ( 351 downto 0 ); + m_axi_rvalid : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \m_atarget_enc_reg[0]\ : in STD_LOGIC; + \m_atarget_enc_reg[1]\ : in STD_LOGIC; + \m_atarget_hot_reg[10]\ : in STD_LOGIC_VECTOR ( 10 downto 0 ); + reset : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of Arty_Z7_20_xbar_0_axi_register_slice_v2_1_11_axic_register_slice : entity is "axi_register_slice_v2_1_11_axic_register_slice"; end Arty_Z7_20_xbar_0_axi_register_slice_v2_1_11_axic_register_slice; architecture STRUCTURE of Arty_Z7_20_xbar_0_axi_register_slice_v2_1_11_axic_register_slice is - signal aa_rmesg : STD_LOGIC_VECTOR ( 34 downto 0 ); + signal \^q\ : STD_LOGIC_VECTOR ( 34 downto 0 ); signal \^aa_rready\ : STD_LOGIC; signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC; signal \aresetn_d_reg_n_0_[1]\ : STD_LOGIC; - signal \m_payload_i_reg_n_0_[0]\ : STD_LOGIC; + signal \m_payload_i[1]_i_2_n_0\ : STD_LOGIC; + signal \m_payload_i[1]_i_3_n_0\ : STD_LOGIC; + signal \m_payload_i[1]_i_4_n_0\ : STD_LOGIC; + signal \m_payload_i[1]_i_5_n_0\ : STD_LOGIC; + signal \m_payload_i[1]_i_6_n_0\ : STD_LOGIC; + signal \m_payload_i[1]_i_7_n_0\ : STD_LOGIC; + signal \m_payload_i[1]_i_8_n_0\ : STD_LOGIC; + signal \m_payload_i[1]_i_9_n_0\ : STD_LOGIC; + signal \m_payload_i[2]_i_2_n_0\ : STD_LOGIC; + signal \m_payload_i[2]_i_3_n_0\ : STD_LOGIC; + signal \m_payload_i[2]_i_4_n_0\ : STD_LOGIC; + signal \m_payload_i[2]_i_5_n_0\ : STD_LOGIC; + signal \m_payload_i[2]_i_6_n_0\ : STD_LOGIC; + signal \m_payload_i[2]_i_7_n_0\ : STD_LOGIC; + signal \^m_payload_i_reg[1]_0\ : STD_LOGIC; + signal \^m_payload_i_reg[2]_0\ : STD_LOGIC; + signal \^m_payload_i_reg[2]_1\ : STD_LOGIC; signal m_valid_i_i_1_n_0 : STD_LOGIC; signal s_ready_i_i_1_n_0 : STD_LOGIC; + signal \^s_ready_i_reg_3\ : STD_LOGIC; signal skid_buffer : STD_LOGIC_VECTOR ( 34 downto 0 ); + signal \skid_buffer[0]_i_1_n_0\ : STD_LOGIC; + signal \skid_buffer[10]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[10]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[10]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[10]_i_4_n_0\ : STD_LOGIC; + signal \skid_buffer[10]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[11]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[11]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[11]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[11]_i_4_n_0\ : STD_LOGIC; + signal \skid_buffer[11]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[12]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[12]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[12]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[12]_i_4_n_0\ : STD_LOGIC; + signal \skid_buffer[12]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[13]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[13]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[13]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[13]_i_4_n_0\ : STD_LOGIC; + signal \skid_buffer[13]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[14]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[14]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[14]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[14]_i_4_n_0\ : STD_LOGIC; + signal \skid_buffer[14]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[15]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[15]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[15]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[15]_i_4_n_0\ : STD_LOGIC; + signal \skid_buffer[15]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[16]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[16]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[16]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[16]_i_4_n_0\ : STD_LOGIC; + signal \skid_buffer[16]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[17]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[17]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[17]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[17]_i_4_n_0\ : STD_LOGIC; + signal \skid_buffer[17]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[18]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[18]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[18]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[18]_i_4_n_0\ : STD_LOGIC; + signal \skid_buffer[18]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[19]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[19]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[19]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[19]_i_4_n_0\ : STD_LOGIC; - signal \skid_buffer[1]_i_2_n_0\ : STD_LOGIC; - signal \skid_buffer[1]_i_3_n_0\ : STD_LOGIC; - signal \skid_buffer[1]_i_4_n_0\ : STD_LOGIC; - signal \skid_buffer[1]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[19]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[20]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[20]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[20]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[20]_i_4_n_0\ : STD_LOGIC; + signal \skid_buffer[20]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[21]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[21]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[21]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[21]_i_4_n_0\ : STD_LOGIC; + signal \skid_buffer[21]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[22]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[22]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[22]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[22]_i_4_n_0\ : STD_LOGIC; + signal \skid_buffer[22]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[23]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[23]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[23]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[23]_i_4_n_0\ : STD_LOGIC; + signal \skid_buffer[23]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[24]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[24]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[24]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[24]_i_4_n_0\ : STD_LOGIC; + signal \skid_buffer[24]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[25]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[25]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[25]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[25]_i_4_n_0\ : STD_LOGIC; + signal \skid_buffer[25]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[26]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[26]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[26]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[26]_i_4_n_0\ : STD_LOGIC; + signal \skid_buffer[26]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[27]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[27]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[27]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[27]_i_4_n_0\ : STD_LOGIC; + signal \skid_buffer[27]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[28]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[28]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[28]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[28]_i_4_n_0\ : STD_LOGIC; + signal \skid_buffer[28]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[28]_i_6_n_0\ : STD_LOGIC; + signal \skid_buffer[29]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[29]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[29]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[29]_i_4_n_0\ : STD_LOGIC; - signal \skid_buffer[2]_i_2_n_0\ : STD_LOGIC; - signal \skid_buffer[2]_i_3_n_0\ : STD_LOGIC; - signal \skid_buffer[2]_i_4_n_0\ : STD_LOGIC; - signal \skid_buffer[2]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[29]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[30]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[30]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[30]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[30]_i_4_n_0\ : STD_LOGIC; + signal \skid_buffer[30]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[31]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[31]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[31]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[31]_i_4_n_0\ : STD_LOGIC; + signal \skid_buffer[31]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[31]_i_6_n_0\ : STD_LOGIC; + signal \skid_buffer[32]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[32]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[32]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[32]_i_4_n_0\ : STD_LOGIC; + signal \skid_buffer[32]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[32]_i_6_n_0\ : STD_LOGIC; + signal \skid_buffer[33]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[33]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[33]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[33]_i_4_n_0\ : STD_LOGIC; + signal \skid_buffer[33]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[34]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[34]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[34]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[34]_i_4_n_0\ : STD_LOGIC; signal \skid_buffer[34]_i_5_n_0\ : STD_LOGIC; signal \skid_buffer[34]_i_6_n_0\ : STD_LOGIC; signal \skid_buffer[34]_i_7_n_0\ : STD_LOGIC; + signal \skid_buffer[3]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[3]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[3]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[3]_i_4_n_0\ : STD_LOGIC; + signal \skid_buffer[3]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[4]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[4]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[4]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[4]_i_4_n_0\ : STD_LOGIC; + signal \skid_buffer[4]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[5]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[5]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[5]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[5]_i_4_n_0\ : STD_LOGIC; + signal \skid_buffer[5]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[6]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[6]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[6]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[6]_i_4_n_0\ : STD_LOGIC; + signal \skid_buffer[6]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[7]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[7]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[7]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[7]_i_4_n_0\ : STD_LOGIC; + signal \skid_buffer[7]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[8]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[8]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[8]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[8]_i_4_n_0\ : STD_LOGIC; + signal \skid_buffer[8]_i_5_n_0\ : STD_LOGIC; + signal \skid_buffer[9]_i_1_n_0\ : STD_LOGIC; signal \skid_buffer[9]_i_2_n_0\ : STD_LOGIC; signal \skid_buffer[9]_i_3_n_0\ : STD_LOGIC; signal \skid_buffer[9]_i_4_n_0\ : STD_LOGIC; - signal \^skid_buffer_reg[1]_0\ : STD_LOGIC; - signal \^skid_buffer_reg[1]_1\ : STD_LOGIC; - signal \^skid_buffer_reg[1]_2\ : STD_LOGIC; - signal \^skid_buffer_reg[1]_3\ : STD_LOGIC; + signal \skid_buffer[9]_i_5_n_0\ : STD_LOGIC; + signal \^skid_buffer_reg[30]_0\ : STD_LOGIC; + signal \^skid_buffer_reg[9]_0\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; @@ -2974,56 +3166,73 @@ architecture STRUCTURE of Arty_Z7_20_xbar_0_axi_register_slice_v2_1_11_axic_regi signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; signal \^sr_rvalid\ : STD_LOGIC; attribute SOFT_HLUTNM : string; - attribute SOFT_HLUTNM of \m_axi_rready[0]_INST_0\ : label is "soft_lutpair40"; - attribute SOFT_HLUTNM of \m_axi_rready[1]_INST_0\ : label is "soft_lutpair40"; - attribute SOFT_HLUTNM of \m_axi_rready[2]_INST_0\ : label is "soft_lutpair41"; - attribute SOFT_HLUTNM of \m_axi_rready[3]_INST_0\ : label is "soft_lutpair41"; - attribute SOFT_HLUTNM of \m_axi_rready[4]_INST_0\ : label is "soft_lutpair42"; - attribute SOFT_HLUTNM of \m_axi_rready[5]_INST_0\ : label is "soft_lutpair42"; - attribute SOFT_HLUTNM of \m_axi_rready[6]_INST_0\ : label is "soft_lutpair43"; - attribute SOFT_HLUTNM of \m_axi_rready[7]_INST_0\ : label is "soft_lutpair43"; - attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair32"; - attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair33"; - attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair34"; - attribute SOFT_HLUTNM of \m_payload_i[13]_i_1\ : label is "soft_lutpair35"; - attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair36"; - attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair37"; - attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair38"; - attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair38"; - attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair37"; - attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair36"; - attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair23"; - attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair35"; - attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair34"; - attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair33"; - attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair32"; - attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair31"; - attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair30"; - attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair29"; - attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair28"; - attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair27"; - attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair26"; - attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair24"; - attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair39"; - attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair25"; - attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair39"; - attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair24"; - attribute SOFT_HLUTNM of \m_payload_i[34]_i_2\ : label is "soft_lutpair23"; - attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair25"; - attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair26"; - attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair27"; - attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair28"; - attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair29"; - attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair30"; - attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair31"; - attribute SOFT_HLUTNM of m_valid_i_i_1 : label is "soft_lutpair22"; - attribute SOFT_HLUTNM of s_ready_i_i_1 : label is "soft_lutpair22"; + attribute SOFT_HLUTNM of \m_axi_rready[10]_INST_0\ : label is "soft_lutpair35"; + attribute SOFT_HLUTNM of \m_axi_rready[1]_INST_0\ : label is "soft_lutpair58"; + attribute SOFT_HLUTNM of \m_axi_rready[2]_INST_0\ : label is "soft_lutpair58"; + attribute SOFT_HLUTNM of \m_axi_rready[3]_INST_0\ : label is "soft_lutpair57"; + attribute SOFT_HLUTNM of \m_axi_rready[4]_INST_0\ : label is "soft_lutpair57"; + attribute SOFT_HLUTNM of \m_axi_rready[5]_INST_0\ : label is "soft_lutpair56"; + attribute SOFT_HLUTNM of \m_axi_rready[6]_INST_0\ : label is "soft_lutpair56"; + attribute SOFT_HLUTNM of \m_axi_rready[7]_INST_0\ : label is "soft_lutpair55"; + attribute SOFT_HLUTNM of \m_axi_rready[8]_INST_0\ : label is "soft_lutpair55"; + attribute SOFT_HLUTNM of \m_axi_rready[9]_INST_0\ : label is "soft_lutpair53"; + attribute SOFT_HLUTNM of \m_payload_i[0]_i_1\ : label is "soft_lutpair35"; + attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair39"; + attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair38"; + attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair37"; + attribute SOFT_HLUTNM of \m_payload_i[13]_i_1\ : label is "soft_lutpair42"; + attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair43"; + attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair44"; + attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair45"; + attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair46"; + attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair47"; + attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair48"; + attribute SOFT_HLUTNM of \m_payload_i[1]_i_2\ : label is "soft_lutpair32"; + attribute SOFT_HLUTNM of \m_payload_i[1]_i_5\ : label is "soft_lutpair30"; + attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair49"; + attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair50"; + attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair51"; + attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair52"; + attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair53"; + attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair52"; + attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair51"; + attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair50"; + attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair49"; + attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair48"; + attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair37"; + attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair47"; + attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair46"; + attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair45"; + attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair44"; + attribute SOFT_HLUTNM of \m_payload_i[34]_i_2\ : label is "soft_lutpair43"; + attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair38"; + attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair39"; + attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair40"; + attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair41"; + attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair42"; + attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair41"; + attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair40"; + attribute SOFT_HLUTNM of m_valid_i_i_1 : label is "soft_lutpair36"; + attribute SOFT_HLUTNM of \s_axi_bresp[0]_INST_0_i_1\ : label is "soft_lutpair33"; + attribute SOFT_HLUTNM of \s_axi_bresp[0]_INST_0_i_2\ : label is "soft_lutpair34"; + attribute SOFT_HLUTNM of \s_axi_bresp[0]_INST_0_i_8\ : label is "soft_lutpair30"; + attribute SOFT_HLUTNM of \s_axi_bresp[1]_INST_0_i_1\ : label is "soft_lutpair31"; + attribute SOFT_HLUTNM of \s_axi_bresp[1]_INST_0_i_2\ : label is "soft_lutpair31"; + attribute SOFT_HLUTNM of \s_axi_wready[0]_INST_0_i_10\ : label is "soft_lutpair54"; + attribute SOFT_HLUTNM of \s_axi_wready[0]_INST_0_i_9\ : label is "soft_lutpair54"; + attribute SOFT_HLUTNM of s_ready_i_i_1 : label is "soft_lutpair36"; + attribute SOFT_HLUTNM of \skid_buffer[28]_i_6\ : label is "soft_lutpair34"; + attribute SOFT_HLUTNM of \skid_buffer[32]_i_6\ : label is "soft_lutpair33"; + attribute SOFT_HLUTNM of \skid_buffer[34]_i_5\ : label is "soft_lutpair32"; begin + Q(34 downto 0) <= \^q\(34 downto 0); aa_rready <= \^aa_rready\; - \skid_buffer_reg[1]_0\ <= \^skid_buffer_reg[1]_0\; - \skid_buffer_reg[1]_1\ <= \^skid_buffer_reg[1]_1\; - \skid_buffer_reg[1]_2\ <= \^skid_buffer_reg[1]_2\; - \skid_buffer_reg[1]_3\ <= \^skid_buffer_reg[1]_3\; + \m_payload_i_reg[1]_0\ <= \^m_payload_i_reg[1]_0\; + \m_payload_i_reg[2]_0\ <= \^m_payload_i_reg[2]_0\; + \m_payload_i_reg[2]_1\ <= \^m_payload_i_reg[2]_1\; + s_ready_i_reg_3 <= \^s_ready_i_reg_3\; + \skid_buffer_reg[30]_0\ <= \^skid_buffer_reg[30]_0\; + \skid_buffer_reg[9]_0\ <= \^skid_buffer_reg[9]_0\; sr_rvalid <= \^sr_rvalid\; \aresetn_d_reg[0]\: unisim.vcomponents.FDRE generic map( @@ -3034,7 +3243,7 @@ begin CE => '1', D => '1', Q => \aresetn_d_reg_n_0_[0]\, - R => SR(0) + R => reset ); \aresetn_d_reg[1]\: unisim.vcomponents.FDRE generic map( @@ -3045,24 +3254,46 @@ begin CE => '1', D => \aresetn_d_reg_n_0_[0]\, Q => \aresetn_d_reg_n_0_[1]\, - R => SR(0) + R => reset + ); +\gen_no_arbiter.m_valid_i_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF80000000000000" + ) + port map ( + I0 => \^q\(0), + I1 => \^sr_rvalid\, + I2 => s_axi_rready(0), + I3 => m_ready_d(0), + I4 => m_valid_i, + I5 => aa_grant_rnw, + O => \gen_no_arbiter.m_grant_hot_i_reg[0]\ ); \m_axi_rready[0]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( - I0 => Q(0), - I1 => \^aa_rready\, + I0 => \^aa_rready\, + I1 => \m_atarget_hot_reg[10]\(0), O => m_axi_rready(0) ); +\m_axi_rready[10]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_rready\, + I1 => \m_atarget_hot_reg[10]\(10), + O => m_axi_rready(10) + ); \m_axi_rready[1]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( - I0 => Q(1), - I1 => \^aa_rready\, + I0 => \^aa_rready\, + I1 => \m_atarget_hot_reg[10]\(1), O => m_axi_rready(1) ); \m_axi_rready[2]_INST_0\: unisim.vcomponents.LUT2 @@ -3070,8 +3301,8 @@ begin INIT => X"8" ) port map ( - I0 => Q(2), - I1 => \^aa_rready\, + I0 => \^aa_rready\, + I1 => \m_atarget_hot_reg[10]\(2), O => m_axi_rready(2) ); \m_axi_rready[3]_INST_0\: unisim.vcomponents.LUT2 @@ -3079,8 +3310,8 @@ begin INIT => X"8" ) port map ( - I0 => Q(3), - I1 => \^aa_rready\, + I0 => \^aa_rready\, + I1 => \m_atarget_hot_reg[10]\(3), O => m_axi_rready(3) ); \m_axi_rready[4]_INST_0\: unisim.vcomponents.LUT2 @@ -3088,8 +3319,8 @@ begin INIT => X"8" ) port map ( - I0 => Q(4), - I1 => \^aa_rready\, + I0 => \^aa_rready\, + I1 => \m_atarget_hot_reg[10]\(4), O => m_axi_rready(4) ); \m_axi_rready[5]_INST_0\: unisim.vcomponents.LUT2 @@ -3097,8 +3328,8 @@ begin INIT => X"8" ) port map ( - I0 => Q(5), - I1 => \^aa_rready\, + I0 => \^aa_rready\, + I1 => \m_atarget_hot_reg[10]\(5), O => m_axi_rready(5) ); \m_axi_rready[6]_INST_0\: unisim.vcomponents.LUT2 @@ -3106,8 +3337,8 @@ begin INIT => X"8" ) port map ( - I0 => Q(6), - I1 => \^aa_rready\, + I0 => \^aa_rready\, + I1 => \m_atarget_hot_reg[10]\(6), O => m_axi_rready(6) ); \m_axi_rready[7]_INST_0\: unisim.vcomponents.LUT2 @@ -3115,8 +3346,8 @@ begin INIT => X"8" ) port map ( - I0 => Q(7), - I1 => \^aa_rready\, + I0 => \^aa_rready\, + I1 => \m_atarget_hot_reg[10]\(7), O => m_axi_rready(7) ); \m_axi_rready[8]_INST_0\: unisim.vcomponents.LUT2 @@ -3124,360 +3355,546 @@ begin INIT => X"8" ) port map ( - I0 => Q(8), - I1 => \^aa_rready\, + I0 => \^aa_rready\, + I1 => \m_atarget_hot_reg[10]\(8), O => m_axi_rready(8) ); -\m_payload_i[0]_i_1\: unisim.vcomponents.LUT5 +\m_axi_rready[9]_INST_0\: unisim.vcomponents.LUT2 generic map( - INIT => X"5757FF00" + INIT => X"8" ) port map ( - I0 => m_atarget_enc(3), - I1 => m_atarget_enc(2), - I2 => m_atarget_enc(1), + I0 => \^aa_rready\, + I1 => \m_atarget_hot_reg[10]\(9), + O => m_axi_rready(9) + ); +\m_payload_i[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F70" + ) + port map ( + I0 => m_atarget_enc(2), + I1 => m_atarget_enc(3), + I2 => \^aa_rready\, I3 => \skid_buffer_reg_n_0_[0]\, - I4 => \^aa_rready\, O => skid_buffer(0) ); \m_payload_i[10]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(10), - I1 => \skid_buffer_reg_n_0_[10]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[10]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[10]\, O => skid_buffer(10) ); \m_payload_i[11]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(11), - I1 => \skid_buffer_reg_n_0_[11]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[11]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[11]\, O => skid_buffer(11) ); \m_payload_i[12]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(12), - I1 => \skid_buffer_reg_n_0_[12]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[12]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[12]\, O => skid_buffer(12) ); \m_payload_i[13]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(13), - I1 => \skid_buffer_reg_n_0_[13]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[13]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[13]\, O => skid_buffer(13) ); \m_payload_i[14]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(14), - I1 => \skid_buffer_reg_n_0_[14]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[14]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[14]\, O => skid_buffer(14) ); \m_payload_i[15]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(15), - I1 => \skid_buffer_reg_n_0_[15]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[15]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[15]\, O => skid_buffer(15) ); \m_payload_i[16]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(16), - I1 => \skid_buffer_reg_n_0_[16]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[16]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[16]\, O => skid_buffer(16) ); \m_payload_i[17]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(17), - I1 => \skid_buffer_reg_n_0_[17]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[17]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[17]\, O => skid_buffer(17) ); \m_payload_i[18]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(18), - I1 => \skid_buffer_reg_n_0_[18]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[18]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[18]\, O => skid_buffer(18) ); \m_payload_i[19]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(19), - I1 => \skid_buffer_reg_n_0_[19]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[19]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[19]\, O => skid_buffer(19) ); -\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3 +\m_payload_i[1]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"AC" + INIT => X"FFFFFFFFFFFF00A8" ) port map ( - I0 => aa_rmesg(1), - I1 => \skid_buffer_reg_n_0_[1]\, - I2 => \^aa_rready\, + I0 => m_axi_rresp(6), + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[1]\, + I3 => \m_payload_i[1]_i_2_n_0\, + I4 => \m_payload_i[1]_i_3_n_0\, + I5 => \m_payload_i[1]_i_4_n_0\, O => skid_buffer(1) ); +\m_payload_i[1]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFF7" + ) + port map ( + I0 => m_atarget_enc(1), + I1 => m_atarget_enc(0), + I2 => m_atarget_enc(3), + I3 => m_atarget_enc(2), + O => \m_payload_i[1]_i_2_n_0\ + ); +\m_payload_i[1]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4F4F4F0044444400" + ) + port map ( + I0 => \^m_payload_i_reg[2]_0\, + I1 => m_axi_rresp(12), + I2 => \^m_payload_i_reg[1]_0\, + I3 => \skid_buffer_reg_n_0_[1]\, + I4 => \^aa_rready\, + I5 => m_axi_rresp(0), + O => \m_payload_i[1]_i_3_n_0\ + ); +\m_payload_i[1]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFF4FFF4FFF40000" + ) + port map ( + I0 => \m_payload_i[1]_i_5_n_0\, + I1 => m_axi_rresp(20), + I2 => \m_payload_i[1]_i_6_n_0\, + I3 => \m_payload_i[1]_i_7_n_0\, + I4 => \^aa_rready\, + I5 => \skid_buffer_reg_n_0_[1]\, + O => \m_payload_i[1]_i_4_n_0\ + ); +\m_payload_i[1]_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFDF" + ) + port map ( + I0 => m_atarget_enc(1), + I1 => m_atarget_enc(0), + I2 => m_atarget_enc(3), + I3 => m_atarget_enc(2), + O => \m_payload_i[1]_i_5_n_0\ + ); +\m_payload_i[1]_i_6\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AEAEFFAE" + ) + port map ( + I0 => \m_payload_i[1]_i_8_n_0\, + I1 => m_axi_rresp(14), + I2 => \^m_payload_i_reg[2]_1\, + I3 => m_axi_rresp(16), + I4 => \^skid_buffer_reg[9]_0\, + O => \m_payload_i[1]_i_6_n_0\ + ); +\m_payload_i[1]_i_7\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF22F2" + ) + port map ( + I0 => m_axi_rresp(18), + I1 => \^skid_buffer_reg[30]_0\, + I2 => m_axi_rresp(8), + I3 => \skid_buffer[32]_i_6_n_0\, + I4 => \m_payload_i[1]_i_9_n_0\, + O => \m_payload_i[1]_i_7_n_0\ + ); +\m_payload_i[1]_i_8\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0020C000FFFFFFFF" + ) + port map ( + I0 => m_axi_rresp(10), + I1 => m_atarget_enc(1), + I2 => m_atarget_enc(0), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => \^aa_rready\, + O => \m_payload_i[1]_i_8_n_0\ + ); +\m_payload_i[1]_i_9\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000002C00000020" + ) + port map ( + I0 => m_axi_rresp(4), + I1 => m_atarget_enc(0), + I2 => m_atarget_enc(1), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rresp(2), + O => \m_payload_i[1]_i_9_n_0\ + ); \m_payload_i[20]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(20), - I1 => \skid_buffer_reg_n_0_[20]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[20]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[20]\, O => skid_buffer(20) ); \m_payload_i[21]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(21), - I1 => \skid_buffer_reg_n_0_[21]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[21]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[21]\, O => skid_buffer(21) ); \m_payload_i[22]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(22), - I1 => \skid_buffer_reg_n_0_[22]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[22]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[22]\, O => skid_buffer(22) ); \m_payload_i[23]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(23), - I1 => \skid_buffer_reg_n_0_[23]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[23]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[23]\, O => skid_buffer(23) ); \m_payload_i[24]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(24), - I1 => \skid_buffer_reg_n_0_[24]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[24]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[24]\, O => skid_buffer(24) ); \m_payload_i[25]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(25), - I1 => \skid_buffer_reg_n_0_[25]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[25]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[25]\, O => skid_buffer(25) ); \m_payload_i[26]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(26), - I1 => \skid_buffer_reg_n_0_[26]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[26]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[26]\, O => skid_buffer(26) ); \m_payload_i[27]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(27), - I1 => \skid_buffer_reg_n_0_[27]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[27]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[27]\, O => skid_buffer(27) ); \m_payload_i[28]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(28), - I1 => \skid_buffer_reg_n_0_[28]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[28]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[28]\, O => skid_buffer(28) ); \m_payload_i[29]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(29), - I1 => \skid_buffer_reg_n_0_[29]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[29]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[29]\, O => skid_buffer(29) ); \m_payload_i[2]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"32" ) port map ( - I0 => aa_rmesg(2), - I1 => \skid_buffer_reg_n_0_[2]\, - I2 => \^aa_rready\, + I0 => \^aa_rready\, + I1 => \m_payload_i[2]_i_2_n_0\, + I2 => \skid_buffer_reg_n_0_[2]\, O => skid_buffer(2) ); +\m_payload_i[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000B0BB0000" + ) + port map ( + I0 => \^m_payload_i_reg[2]_0\, + I1 => m_axi_rresp(13), + I2 => \^m_payload_i_reg[2]_1\, + I3 => m_axi_rresp(15), + I4 => \m_payload_i[2]_i_3_n_0\, + I5 => \m_payload_i[2]_i_4_n_0\, + O => \m_payload_i[2]_i_2_n_0\ + ); +\m_payload_i[2]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAA0AAA2AAA" + ) + port map ( + I0 => \^aa_rready\, + I1 => m_axi_rresp(7), + I2 => m_atarget_enc(1), + I3 => m_atarget_enc(0), + I4 => m_atarget_enc(3), + I5 => m_atarget_enc(2), + O => \m_payload_i[2]_i_3_n_0\ + ); +\m_payload_i[2]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFBAFFBABA" + ) + port map ( + I0 => \m_payload_i[2]_i_5_n_0\, + I1 => \^m_payload_i_reg[1]_0\, + I2 => m_axi_rresp(1), + I3 => \^skid_buffer_reg[30]_0\, + I4 => m_axi_rresp(19), + I5 => \m_payload_i[2]_i_6_n_0\, + O => \m_payload_i[2]_i_4_n_0\ + ); +\m_payload_i[2]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000C0800000008" + ) + port map ( + I0 => m_axi_rresp(9), + I1 => m_atarget_enc(2), + I2 => m_atarget_enc(3), + I3 => m_atarget_enc(0), + I4 => m_atarget_enc(1), + I5 => m_axi_rresp(11), + O => \m_payload_i[2]_i_5_n_0\ + ); +\m_payload_i[2]_i_6\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF22F2" + ) + port map ( + I0 => m_axi_rresp(21), + I1 => \m_payload_i[1]_i_5_n_0\, + I2 => m_axi_rresp(17), + I3 => \^skid_buffer_reg[9]_0\, + I4 => \m_payload_i[2]_i_7_n_0\, + O => \m_payload_i[2]_i_6_n_0\ + ); +\m_payload_i[2]_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000002C00000020" + ) + port map ( + I0 => m_axi_rresp(5), + I1 => m_atarget_enc(0), + I2 => m_atarget_enc(1), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rresp(3), + O => \m_payload_i[2]_i_7_n_0\ + ); \m_payload_i[30]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(30), - I1 => \skid_buffer_reg_n_0_[30]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[30]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[30]\, O => skid_buffer(30) ); \m_payload_i[31]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(31), - I1 => \skid_buffer_reg_n_0_[31]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[31]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[31]\, O => skid_buffer(31) ); \m_payload_i[32]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(32), - I1 => \skid_buffer_reg_n_0_[32]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[32]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[32]\, O => skid_buffer(32) ); \m_payload_i[33]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(33), - I1 => \skid_buffer_reg_n_0_[33]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[33]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[33]\, O => skid_buffer(33) ); \m_payload_i[34]_i_2\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(34), - I1 => \skid_buffer_reg_n_0_[34]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[34]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[34]\, O => skid_buffer(34) ); \m_payload_i[3]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(3), - I1 => \skid_buffer_reg_n_0_[3]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[3]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[3]\, O => skid_buffer(3) ); \m_payload_i[4]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(4), - I1 => \skid_buffer_reg_n_0_[4]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[4]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[4]\, O => skid_buffer(4) ); \m_payload_i[5]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(5), - I1 => \skid_buffer_reg_n_0_[5]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[5]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[5]\, O => skid_buffer(5) ); \m_payload_i[6]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(6), - I1 => \skid_buffer_reg_n_0_[6]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[6]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[6]\, O => skid_buffer(6) ); \m_payload_i[7]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(7), - I1 => \skid_buffer_reg_n_0_[7]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[7]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[7]\, O => skid_buffer(7) ); \m_payload_i[8]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(8), - I1 => \skid_buffer_reg_n_0_[8]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[8]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[8]\, O => skid_buffer(8) ); \m_payload_i[9]_i_1\: unisim.vcomponents.LUT3 generic map( - INIT => X"AC" + INIT => X"B8" ) port map ( - I0 => aa_rmesg(9), - I1 => \skid_buffer_reg_n_0_[9]\, - I2 => \^aa_rready\, + I0 => \skid_buffer[9]_i_1_n_0\, + I1 => \^aa_rready\, + I2 => \skid_buffer_reg_n_0_[9]\, O => skid_buffer(9) ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE @@ -3485,7 +3902,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(0), - Q => \m_payload_i_reg_n_0_[0]\, + Q => \^q\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE @@ -3493,7 +3910,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(10), - Q => \s_axi_rdata[31]\(9), + Q => \^q\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE @@ -3501,7 +3918,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(11), - Q => \s_axi_rdata[31]\(10), + Q => \^q\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE @@ -3509,7 +3926,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(12), - Q => \s_axi_rdata[31]\(11), + Q => \^q\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE @@ -3517,7 +3934,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(13), - Q => \s_axi_rdata[31]\(12), + Q => \^q\(13), R => '0' ); \m_payload_i_reg[14]\: unisim.vcomponents.FDRE @@ -3525,7 +3942,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(14), - Q => \s_axi_rdata[31]\(13), + Q => \^q\(14), R => '0' ); \m_payload_i_reg[15]\: unisim.vcomponents.FDRE @@ -3533,7 +3950,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(15), - Q => \s_axi_rdata[31]\(14), + Q => \^q\(15), R => '0' ); \m_payload_i_reg[16]\: unisim.vcomponents.FDRE @@ -3541,7 +3958,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(16), - Q => \s_axi_rdata[31]\(15), + Q => \^q\(16), R => '0' ); \m_payload_i_reg[17]\: unisim.vcomponents.FDRE @@ -3549,7 +3966,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(17), - Q => \s_axi_rdata[31]\(16), + Q => \^q\(17), R => '0' ); \m_payload_i_reg[18]\: unisim.vcomponents.FDRE @@ -3557,7 +3974,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(18), - Q => \s_axi_rdata[31]\(17), + Q => \^q\(18), R => '0' ); \m_payload_i_reg[19]\: unisim.vcomponents.FDRE @@ -3565,7 +3982,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(19), - Q => \s_axi_rdata[31]\(18), + Q => \^q\(19), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE @@ -3573,7 +3990,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(1), - Q => \s_axi_rdata[31]\(0), + Q => \^q\(1), R => '0' ); \m_payload_i_reg[20]\: unisim.vcomponents.FDRE @@ -3581,7 +3998,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(20), - Q => \s_axi_rdata[31]\(19), + Q => \^q\(20), R => '0' ); \m_payload_i_reg[21]\: unisim.vcomponents.FDRE @@ -3589,7 +4006,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(21), - Q => \s_axi_rdata[31]\(20), + Q => \^q\(21), R => '0' ); \m_payload_i_reg[22]\: unisim.vcomponents.FDRE @@ -3597,7 +4014,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(22), - Q => \s_axi_rdata[31]\(21), + Q => \^q\(22), R => '0' ); \m_payload_i_reg[23]\: unisim.vcomponents.FDRE @@ -3605,7 +4022,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(23), - Q => \s_axi_rdata[31]\(22), + Q => \^q\(23), R => '0' ); \m_payload_i_reg[24]\: unisim.vcomponents.FDRE @@ -3613,7 +4030,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(24), - Q => \s_axi_rdata[31]\(23), + Q => \^q\(24), R => '0' ); \m_payload_i_reg[25]\: unisim.vcomponents.FDRE @@ -3621,7 +4038,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(25), - Q => \s_axi_rdata[31]\(24), + Q => \^q\(25), R => '0' ); \m_payload_i_reg[26]\: unisim.vcomponents.FDRE @@ -3629,7 +4046,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(26), - Q => \s_axi_rdata[31]\(25), + Q => \^q\(26), R => '0' ); \m_payload_i_reg[27]\: unisim.vcomponents.FDRE @@ -3637,7 +4054,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(27), - Q => \s_axi_rdata[31]\(26), + Q => \^q\(27), R => '0' ); \m_payload_i_reg[28]\: unisim.vcomponents.FDRE @@ -3645,7 +4062,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(28), - Q => \s_axi_rdata[31]\(27), + Q => \^q\(28), R => '0' ); \m_payload_i_reg[29]\: unisim.vcomponents.FDRE @@ -3653,7 +4070,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(29), - Q => \s_axi_rdata[31]\(28), + Q => \^q\(29), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE @@ -3661,7 +4078,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(2), - Q => \s_axi_rdata[31]\(1), + Q => \^q\(2), R => '0' ); \m_payload_i_reg[30]\: unisim.vcomponents.FDRE @@ -3669,7 +4086,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(30), - Q => \s_axi_rdata[31]\(29), + Q => \^q\(30), R => '0' ); \m_payload_i_reg[31]\: unisim.vcomponents.FDRE @@ -3677,7 +4094,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(31), - Q => \s_axi_rdata[31]\(30), + Q => \^q\(31), R => '0' ); \m_payload_i_reg[32]\: unisim.vcomponents.FDRE @@ -3685,7 +4102,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(32), - Q => \s_axi_rdata[31]\(31), + Q => \^q\(32), R => '0' ); \m_payload_i_reg[33]\: unisim.vcomponents.FDRE @@ -3693,7 +4110,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(33), - Q => \s_axi_rdata[31]\(32), + Q => \^q\(33), R => '0' ); \m_payload_i_reg[34]\: unisim.vcomponents.FDRE @@ -3701,7 +4118,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(34), - Q => \s_axi_rdata[31]\(33), + Q => \^q\(34), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE @@ -3709,7 +4126,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(3), - Q => \s_axi_rdata[31]\(2), + Q => \^q\(3), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE @@ -3717,7 +4134,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(4), - Q => \s_axi_rdata[31]\(3), + Q => \^q\(4), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE @@ -3725,7 +4142,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(5), - Q => \s_axi_rdata[31]\(4), + Q => \^q\(5), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE @@ -3733,7 +4150,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(6), - Q => \s_axi_rdata[31]\(5), + Q => \^q\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE @@ -3741,7 +4158,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(7), - Q => \s_axi_rdata[31]\(6), + Q => \^q\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE @@ -3749,7 +4166,7 @@ begin C => aclk, CE => E(0), D => skid_buffer(8), - Q => \s_axi_rdata[31]\(7), + Q => \^q\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE @@ -3757,32 +4174,57 @@ begin C => aclk, CE => E(0), D => skid_buffer(9), - Q => \s_axi_rdata[31]\(8), + Q => \^q\(9), R => '0' ); -\m_ready_d[1]_i_3\: unisim.vcomponents.LUT6 +m_valid_i_i_1: unisim.vcomponents.LUT3 generic map( - INIT => X"0800000000000000" + INIT => X"A2" ) port map ( - I0 => \m_payload_i_reg_n_0_[0]\, - I1 => s_axi_rready(0), - I2 => m_ready_d(0), - I3 => aa_grant_rnw, - I4 => m_valid_i, - I5 => \^sr_rvalid\, - O => \m_ready_d_reg[1]\ + I0 => \aresetn_d_reg_n_0_[1]\, + I1 => E(0), + I2 => s_ready_i_reg_4, + O => m_valid_i_i_1_n_0 ); -m_valid_i_i_1: unisim.vcomponents.LUT4 +m_valid_i_i_4: unisim.vcomponents.LUT6 generic map( - INIT => X"8AAA" + INIT => X"003300B8000000B8" ) port map ( - I0 => \aresetn_d_reg_n_0_[1]\, - I1 => aa_rvalid, - I2 => E(0), - I3 => \^aa_rready\, - O => m_valid_i_i_1_n_0 + I0 => m_axi_rvalid(4), + I1 => m_atarget_enc(2), + I2 => m_axi_rvalid(1), + I3 => \m_atarget_enc_reg[1]\, + I4 => m_atarget_enc(3), + I5 => m_axi_rvalid(7), + O => s_ready_i_reg_1 + ); +m_valid_i_i_5: unisim.vcomponents.LUT6 + generic map( + INIT => X"FCDCFCDFFFDCFFDF" + ) + port map ( + I0 => m_axi_rvalid(8), + I1 => \m_atarget_enc_reg[0]\, + I2 => m_atarget_enc(3), + I3 => m_atarget_enc(2), + I4 => m_axi_rvalid(2), + I5 => m_axi_rvalid(5), + O => s_ready_i_reg_0 + ); +m_valid_i_i_6: unisim.vcomponents.LUT6 + generic map( + INIT => X"FCDCFCDFFFDCFFDF" + ) + port map ( + I0 => m_axi_rvalid(6), + I1 => \^s_ready_i_reg_3\, + I2 => m_atarget_enc(3), + I3 => m_atarget_enc(2), + I4 => m_axi_rvalid(0), + I5 => m_axi_rvalid(3), + O => s_ready_i_reg_2 ); m_valid_i_reg: unisim.vcomponents.FDRE port map ( @@ -3792,59 +4234,87 @@ m_valid_i_reg: unisim.vcomponents.FDRE Q => \^sr_rvalid\, R => '0' ); -\s_axi_bresp[1]_INST_0_i_1\: unisim.vcomponents.LUT4 +\s_axi_bresp[0]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"0010" + INIT => X"FFDF" ) port map ( - I0 => m_atarget_enc(3), - I1 => m_atarget_enc(2), - I2 => m_atarget_enc(0), - I3 => m_atarget_enc(1), - O => \^skid_buffer_reg[1]_0\ + I0 => m_atarget_enc(0), + I1 => m_atarget_enc(1), + I2 => m_atarget_enc(3), + I3 => m_atarget_enc(2), + O => \^skid_buffer_reg[30]_0\ ); -\s_axi_bresp[1]_INST_0_i_2\: unisim.vcomponents.LUT4 +\s_axi_bresp[0]_INST_0_i_2\: unisim.vcomponents.LUT4 generic map( - INIT => X"0010" + INIT => X"DFFF" ) port map ( - I0 => m_atarget_enc(3), - I1 => m_atarget_enc(2), + I0 => m_atarget_enc(2), + I1 => m_atarget_enc(3), + I2 => m_atarget_enc(1), + I3 => m_atarget_enc(0), + O => \^m_payload_i_reg[2]_1\ + ); +\s_axi_bresp[0]_INST_0_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFDF" + ) + port map ( + I0 => m_atarget_enc(2), + I1 => m_atarget_enc(3), I2 => m_atarget_enc(1), I3 => m_atarget_enc(0), - O => \^skid_buffer_reg[1]_1\ + O => \^m_payload_i_reg[2]_0\ ); -\s_axi_bresp[1]_INST_0_i_6\: unisim.vcomponents.LUT4 +\s_axi_bresp[1]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( - INIT => X"0010" + INIT => X"FFFE" ) port map ( - I0 => m_atarget_enc(3), + I0 => m_atarget_enc(1), I1 => m_atarget_enc(0), - I2 => m_atarget_enc(2), - I3 => m_atarget_enc(1), - O => \^skid_buffer_reg[1]_2\ + I2 => m_atarget_enc(3), + I3 => m_atarget_enc(2), + O => \^m_payload_i_reg[1]_0\ ); -\s_axi_bresp[1]_INST_0_i_7\: unisim.vcomponents.LUT4 +\s_axi_bresp[1]_INST_0_i_2\: unisim.vcomponents.LUT4 generic map( - INIT => X"1000" + INIT => X"FFEF" ) port map ( - I0 => m_atarget_enc(3), - I1 => m_atarget_enc(2), - I2 => m_atarget_enc(0), - I3 => m_atarget_enc(1), - O => \^skid_buffer_reg[1]_3\ + I0 => m_atarget_enc(1), + I1 => m_atarget_enc(0), + I2 => m_atarget_enc(3), + I3 => m_atarget_enc(2), + O => \^skid_buffer_reg[9]_0\ ); -s_ready_i_i_1: unisim.vcomponents.LUT4 +\s_axi_wready[0]_INST_0_i_10\: unisim.vcomponents.LUT2 generic map( - INIT => X"AA08" + INIT => X"7" + ) + port map ( + I0 => m_atarget_enc(0), + I1 => m_atarget_enc(1), + O => \m_ready_d_reg[2]\ + ); +\s_axi_wready[0]_INST_0_i_9\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => m_atarget_enc(0), + I1 => m_atarget_enc(1), + O => \^s_ready_i_reg_3\ + ); +s_ready_i_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"A2" ) port map ( I0 => \aresetn_d_reg_n_0_[0]\, - I1 => \^aa_rready\, - I2 => aa_rvalid, - I3 => E(0), + I1 => s_ready_i_reg_4, + I2 => E(0), O => s_ready_i_i_1_n_0 ); s_ready_i_reg: unisim.vcomponents.FDRE @@ -3855,1420 +4325,1659 @@ s_ready_i_reg: unisim.vcomponents.FDRE Q => \^aa_rready\, R => '0' ); -\skid_buffer[0]_i_1\: unisim.vcomponents.LUT3 +\skid_buffer[0]_i_1\: unisim.vcomponents.LUT2 generic map( - INIT => X"57" + INIT => X"7" ) port map ( - I0 => m_atarget_enc(3), - I1 => m_atarget_enc(2), - I2 => m_atarget_enc(1), - O => aa_rmesg(0) + I0 => m_atarget_enc(2), + I1 => m_atarget_enc(3), + O => \skid_buffer[0]_i_1_n_0\ ); \skid_buffer[10]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFEFFFEFFFFFFFE" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, - I1 => m_axi_rdata(39), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(71), - I4 => \skid_buffer[10]_i_2_n_0\, - I5 => \skid_buffer[10]_i_3_n_0\, - O => aa_rmesg(10) + I0 => \skid_buffer[10]_i_2_n_0\, + I1 => \skid_buffer[10]_i_3_n_0\, + I2 => \skid_buffer[10]_i_4_n_0\, + I3 => \skid_buffer[10]_i_5_n_0\, + I4 => m_axi_rdata(71), + I5 => \skid_buffer[31]_i_2_n_0\, + O => \skid_buffer[10]_i_1_n_0\ ); \skid_buffer[10]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(263), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(231), - I4 => m_axi_rdata(7), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_axi_rdata(39), + I1 => \skid_buffer[34]_i_2_n_0\, + I2 => m_axi_rdata(103), + I3 => \m_payload_i[1]_i_2_n_0\, + I4 => \skid_buffer[32]_i_6_n_0\, + I5 => m_axi_rdata(135), O => \skid_buffer[10]_i_2_n_0\ ); -\skid_buffer[10]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[10]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"00200C0000200000" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(135), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(103), - I4 => \skid_buffer[10]_i_4_n_0\, + I0 => m_axi_rdata(199), + I1 => m_atarget_enc(0), + I2 => m_atarget_enc(1), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(295), O => \skid_buffer[10]_i_3_n_0\ ); \skid_buffer[10]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"08000C0008000000" ) port map ( - I0 => m_axi_rdata(167), - I1 => m_axi_rdata(199), + I0 => m_axi_rdata(231), + I1 => m_atarget_enc(2), I2 => m_atarget_enc(3), I3 => m_atarget_enc(0), I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I5 => m_axi_rdata(167), O => \skid_buffer[10]_i_4_n_0\ ); +\skid_buffer[10]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"22F2FFFF22F222F2" + ) + port map ( + I0 => m_axi_rdata(327), + I1 => \m_payload_i[1]_i_5_n_0\, + I2 => m_axi_rdata(7), + I3 => \^m_payload_i_reg[1]_0\, + I4 => \^skid_buffer_reg[9]_0\, + I5 => m_axi_rdata(263), + O => \skid_buffer[10]_i_5_n_0\ + ); \skid_buffer[11]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFEFFFEFFFFFFFE" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, - I1 => m_axi_rdata(40), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(72), - I4 => \skid_buffer[11]_i_2_n_0\, - I5 => \skid_buffer[11]_i_3_n_0\, - O => aa_rmesg(11) + I0 => \skid_buffer[11]_i_2_n_0\, + I1 => \skid_buffer[11]_i_3_n_0\, + I2 => \skid_buffer[11]_i_4_n_0\, + I3 => \skid_buffer[11]_i_5_n_0\, + I4 => m_axi_rdata(72), + I5 => \skid_buffer[31]_i_2_n_0\, + O => \skid_buffer[11]_i_1_n_0\ ); \skid_buffer[11]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(264), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(232), - I4 => m_axi_rdata(8), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_axi_rdata(40), + I1 => \skid_buffer[34]_i_2_n_0\, + I2 => m_axi_rdata(136), + I3 => \skid_buffer[32]_i_6_n_0\, + I4 => \m_payload_i[1]_i_2_n_0\, + I5 => m_axi_rdata(104), O => \skid_buffer[11]_i_2_n_0\ ); -\skid_buffer[11]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[11]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"00080C0000080000" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(136), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(104), - I4 => \skid_buffer[11]_i_4_n_0\, + I0 => m_axi_rdata(200), + I1 => m_atarget_enc(1), + I2 => m_atarget_enc(0), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(328), O => \skid_buffer[11]_i_3_n_0\ ); \skid_buffer[11]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"08000C0008000000" ) port map ( - I0 => m_axi_rdata(168), - I1 => m_axi_rdata(200), + I0 => m_axi_rdata(232), + I1 => m_atarget_enc(2), I2 => m_atarget_enc(3), I3 => m_atarget_enc(0), I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I5 => m_axi_rdata(168), O => \skid_buffer[11]_i_4_n_0\ ); +\skid_buffer[11]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"22F2FFFF22F222F2" + ) + port map ( + I0 => m_axi_rdata(296), + I1 => \^skid_buffer_reg[30]_0\, + I2 => m_axi_rdata(8), + I3 => \^m_payload_i_reg[1]_0\, + I4 => \^skid_buffer_reg[9]_0\, + I5 => m_axi_rdata(264), + O => \skid_buffer[11]_i_5_n_0\ + ); \skid_buffer[12]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFFFFFFFFFF4F44" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, + I0 => \skid_buffer[34]_i_2_n_0\, I1 => m_axi_rdata(41), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(73), + I2 => \skid_buffer[32]_i_6_n_0\, + I3 => m_axi_rdata(137), I4 => \skid_buffer[12]_i_2_n_0\, I5 => \skid_buffer[12]_i_3_n_0\, - O => aa_rmesg(12) + O => \skid_buffer[12]_i_1_n_0\ ); \skid_buffer[12]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(265), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(233), - I4 => m_axi_rdata(9), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_axi_rdata(265), + I1 => \^skid_buffer_reg[9]_0\, + I2 => m_axi_rdata(201), + I3 => \^m_payload_i_reg[2]_0\, + I4 => \skid_buffer[31]_i_2_n_0\, + I5 => m_axi_rdata(73), O => \skid_buffer[12]_i_2_n_0\ ); -\skid_buffer[12]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[12]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"EFEEEFEEFFFFEFEE" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(137), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(105), - I4 => \skid_buffer[12]_i_4_n_0\, + I0 => \skid_buffer[12]_i_4_n_0\, + I1 => \skid_buffer[12]_i_5_n_0\, + I2 => \^skid_buffer_reg[30]_0\, + I3 => m_axi_rdata(297), + I4 => m_axi_rdata(233), + I5 => \^m_payload_i_reg[2]_1\, O => \skid_buffer[12]_i_3_n_0\ ); \skid_buffer[12]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"02000C0002000000" ) port map ( - I0 => m_axi_rdata(169), - I1 => m_axi_rdata(201), + I0 => m_axi_rdata(105), + I1 => m_atarget_enc(2), I2 => m_atarget_enc(3), I3 => m_atarget_enc(0), I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I5 => m_axi_rdata(169), O => \skid_buffer[12]_i_4_n_0\ ); +\skid_buffer[12]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000C0200000002" + ) + port map ( + I0 => m_axi_rdata(9), + I1 => m_atarget_enc(1), + I2 => m_atarget_enc(0), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(329), + O => \skid_buffer[12]_i_5_n_0\ + ); \skid_buffer[13]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFFFFFFFFFF4F44" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, + I0 => \skid_buffer[34]_i_2_n_0\, I1 => m_axi_rdata(42), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(74), + I2 => \m_payload_i[1]_i_2_n_0\, + I3 => m_axi_rdata(106), I4 => \skid_buffer[13]_i_2_n_0\, I5 => \skid_buffer[13]_i_3_n_0\, - O => aa_rmesg(13) + O => \skid_buffer[13]_i_1_n_0\ ); \skid_buffer[13]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(266), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(234), - I4 => m_axi_rdata(10), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_axi_rdata(170), + I1 => \skid_buffer[34]_i_5_n_0\, + I2 => m_axi_rdata(234), + I3 => \^m_payload_i_reg[2]_1\, + I4 => \skid_buffer[31]_i_2_n_0\, + I5 => m_axi_rdata(74), O => \skid_buffer[13]_i_2_n_0\ ); -\skid_buffer[13]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[13]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"EFEEEFEEFFFFEFEE" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(138), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(106), - I4 => \skid_buffer[13]_i_4_n_0\, + I0 => \skid_buffer[13]_i_4_n_0\, + I1 => \skid_buffer[13]_i_5_n_0\, + I2 => \^m_payload_i_reg[1]_0\, + I3 => m_axi_rdata(10), + I4 => m_axi_rdata(202), + I5 => \^m_payload_i_reg[2]_0\, O => \skid_buffer[13]_i_3_n_0\ ); \skid_buffer[13]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"0002030000020000" ) port map ( - I0 => m_axi_rdata(170), - I1 => m_axi_rdata(202), - I2 => m_atarget_enc(3), - I3 => m_atarget_enc(0), - I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I0 => m_axi_rdata(138), + I1 => m_atarget_enc(1), + I2 => m_atarget_enc(0), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(266), O => \skid_buffer[13]_i_4_n_0\ ); +\skid_buffer[13]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00002C0000002000" + ) + port map ( + I0 => m_axi_rdata(298), + I1 => m_atarget_enc(1), + I2 => m_atarget_enc(0), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(330), + O => \skid_buffer[13]_i_5_n_0\ + ); \skid_buffer[14]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFFFFFFFFFF4F44" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, + I0 => \skid_buffer[34]_i_2_n_0\, I1 => m_axi_rdata(43), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(75), + I2 => \m_payload_i[1]_i_2_n_0\, + I3 => m_axi_rdata(107), I4 => \skid_buffer[14]_i_2_n_0\, I5 => \skid_buffer[14]_i_3_n_0\, - O => aa_rmesg(14) + O => \skid_buffer[14]_i_1_n_0\ ); \skid_buffer[14]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(267), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(235), - I4 => m_axi_rdata(11), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_axi_rdata(267), + I1 => \^skid_buffer_reg[9]_0\, + I2 => m_axi_rdata(171), + I3 => \skid_buffer[34]_i_5_n_0\, + I4 => \skid_buffer[31]_i_2_n_0\, + I5 => m_axi_rdata(75), O => \skid_buffer[14]_i_2_n_0\ ); -\skid_buffer[14]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[14]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"EFEEEFEEFFFFEFEE" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(139), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(107), - I4 => \skid_buffer[14]_i_4_n_0\, + I0 => \skid_buffer[14]_i_4_n_0\, + I1 => \skid_buffer[14]_i_5_n_0\, + I2 => \^m_payload_i_reg[1]_0\, + I3 => m_axi_rdata(11), + I4 => m_axi_rdata(235), + I5 => \^m_payload_i_reg[2]_1\, O => \skid_buffer[14]_i_3_n_0\ ); \skid_buffer[14]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"00000C0800000008" ) port map ( - I0 => m_axi_rdata(171), - I1 => m_axi_rdata(203), + I0 => m_axi_rdata(139), + I1 => m_atarget_enc(2), I2 => m_atarget_enc(3), - I3 => m_atarget_enc(0), - I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I3 => m_atarget_enc(1), + I4 => m_atarget_enc(0), + I5 => m_axi_rdata(203), O => \skid_buffer[14]_i_4_n_0\ ); +\skid_buffer[14]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00002C0000002000" + ) + port map ( + I0 => m_axi_rdata(331), + I1 => m_atarget_enc(0), + I2 => m_atarget_enc(1), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(299), + O => \skid_buffer[14]_i_5_n_0\ + ); \skid_buffer[15]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFEFFFEFFFFFFFE" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, - I1 => m_axi_rdata(44), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(76), - I4 => \skid_buffer[15]_i_2_n_0\, - I5 => \skid_buffer[15]_i_3_n_0\, - O => aa_rmesg(15) + I0 => \skid_buffer[15]_i_2_n_0\, + I1 => \skid_buffer[15]_i_3_n_0\, + I2 => \skid_buffer[15]_i_4_n_0\, + I3 => \skid_buffer[15]_i_5_n_0\, + I4 => m_axi_rdata(140), + I5 => \skid_buffer[32]_i_6_n_0\, + O => \skid_buffer[15]_i_1_n_0\ ); \skid_buffer[15]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(268), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(236), - I4 => m_axi_rdata(12), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_axi_rdata(108), + I1 => \m_payload_i[1]_i_2_n_0\, + I2 => m_axi_rdata(44), + I3 => \skid_buffer[34]_i_2_n_0\, + I4 => \skid_buffer[31]_i_2_n_0\, + I5 => m_axi_rdata(76), O => \skid_buffer[15]_i_2_n_0\ ); -\skid_buffer[15]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[15]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"0020000300200000" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(140), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(108), - I4 => \skid_buffer[15]_i_4_n_0\, + I0 => m_axi_rdata(172), + I1 => m_atarget_enc(1), + I2 => m_atarget_enc(0), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(12), O => \skid_buffer[15]_i_3_n_0\ ); \skid_buffer[15]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"00000C2000000020" ) port map ( - I0 => m_axi_rdata(172), - I1 => m_axi_rdata(204), + I0 => m_axi_rdata(268), + I1 => m_atarget_enc(2), I2 => m_atarget_enc(3), - I3 => m_atarget_enc(0), - I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I3 => m_atarget_enc(1), + I4 => m_atarget_enc(0), + I5 => m_axi_rdata(204), O => \skid_buffer[15]_i_4_n_0\ ); +\skid_buffer[15]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"22F2FFFF22F222F2" + ) + port map ( + I0 => m_axi_rdata(300), + I1 => \^skid_buffer_reg[30]_0\, + I2 => m_axi_rdata(332), + I3 => \m_payload_i[1]_i_5_n_0\, + I4 => \^m_payload_i_reg[2]_1\, + I5 => m_axi_rdata(236), + O => \skid_buffer[15]_i_5_n_0\ + ); \skid_buffer[16]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFFFFFFFFFF4F44" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, + I0 => \skid_buffer[34]_i_2_n_0\, I1 => m_axi_rdata(45), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(77), + I2 => \m_payload_i[1]_i_2_n_0\, + I3 => m_axi_rdata(109), I4 => \skid_buffer[16]_i_2_n_0\, I5 => \skid_buffer[16]_i_3_n_0\, - O => aa_rmesg(16) + O => \skid_buffer[16]_i_1_n_0\ ); \skid_buffer[16]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(269), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(237), - I4 => m_axi_rdata(13), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_axi_rdata(269), + I1 => \^skid_buffer_reg[9]_0\, + I2 => m_axi_rdata(205), + I3 => \^m_payload_i_reg[2]_0\, + I4 => \skid_buffer[31]_i_2_n_0\, + I5 => m_axi_rdata(77), O => \skid_buffer[16]_i_2_n_0\ ); -\skid_buffer[16]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[16]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"EFEEEFEEFFFFEFEE" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(141), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(109), - I4 => \skid_buffer[16]_i_4_n_0\, + I0 => \skid_buffer[16]_i_4_n_0\, + I1 => \skid_buffer[16]_i_5_n_0\, + I2 => \m_payload_i[1]_i_5_n_0\, + I3 => m_axi_rdata(333), + I4 => m_axi_rdata(237), + I5 => \^m_payload_i_reg[2]_1\, O => \skid_buffer[16]_i_3_n_0\ ); \skid_buffer[16]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"00000C0800000008" ) port map ( - I0 => m_axi_rdata(173), - I1 => m_axi_rdata(205), + I0 => m_axi_rdata(141), + I1 => m_atarget_enc(2), I2 => m_atarget_enc(3), I3 => m_atarget_enc(0), I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I5 => m_axi_rdata(173), O => \skid_buffer[16]_i_4_n_0\ ); +\skid_buffer[16]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000200300002000" + ) + port map ( + I0 => m_axi_rdata(301), + I1 => m_atarget_enc(1), + I2 => m_atarget_enc(0), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(13), + O => \skid_buffer[16]_i_5_n_0\ + ); \skid_buffer[17]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFFFFFFFFFF4F44" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, + I0 => \skid_buffer[34]_i_2_n_0\, I1 => m_axi_rdata(46), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(78), + I2 => \skid_buffer[32]_i_6_n_0\, + I3 => m_axi_rdata(142), I4 => \skid_buffer[17]_i_2_n_0\, I5 => \skid_buffer[17]_i_3_n_0\, - O => aa_rmesg(17) + O => \skid_buffer[17]_i_1_n_0\ ); \skid_buffer[17]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(270), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(238), - I4 => m_axi_rdata(14), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_axi_rdata(270), + I1 => \^skid_buffer_reg[9]_0\, + I2 => m_axi_rdata(206), + I3 => \^m_payload_i_reg[2]_0\, + I4 => \skid_buffer[31]_i_2_n_0\, + I5 => m_axi_rdata(78), O => \skid_buffer[17]_i_2_n_0\ ); -\skid_buffer[17]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[17]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"EFEEEFEEFFFFEFEE" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(142), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(110), - I4 => \skid_buffer[17]_i_4_n_0\, + I0 => \skid_buffer[17]_i_4_n_0\, + I1 => \skid_buffer[17]_i_5_n_0\, + I2 => \^skid_buffer_reg[30]_0\, + I3 => m_axi_rdata(302), + I4 => m_axi_rdata(238), + I5 => \^m_payload_i_reg[2]_1\, O => \skid_buffer[17]_i_3_n_0\ ); \skid_buffer[17]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"02000C0002000000" ) port map ( - I0 => m_axi_rdata(174), - I1 => m_axi_rdata(206), + I0 => m_axi_rdata(110), + I1 => m_atarget_enc(2), I2 => m_atarget_enc(3), I3 => m_atarget_enc(0), I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I5 => m_axi_rdata(174), O => \skid_buffer[17]_i_4_n_0\ ); +\skid_buffer[17]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000080300000800" + ) + port map ( + I0 => m_axi_rdata(334), + I1 => m_atarget_enc(1), + I2 => m_atarget_enc(0), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(14), + O => \skid_buffer[17]_i_5_n_0\ + ); \skid_buffer[18]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFFFFFFFFFF4F44" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, + I0 => \skid_buffer[34]_i_2_n_0\, I1 => m_axi_rdata(47), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(79), + I2 => \m_payload_i[1]_i_2_n_0\, + I3 => m_axi_rdata(111), I4 => \skid_buffer[18]_i_2_n_0\, I5 => \skid_buffer[18]_i_3_n_0\, - O => aa_rmesg(18) + O => \skid_buffer[18]_i_1_n_0\ ); \skid_buffer[18]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(271), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(239), - I4 => m_axi_rdata(15), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_axi_rdata(271), + I1 => \^skid_buffer_reg[9]_0\, + I2 => m_axi_rdata(207), + I3 => \^m_payload_i_reg[2]_0\, + I4 => \skid_buffer[31]_i_2_n_0\, + I5 => m_axi_rdata(79), O => \skid_buffer[18]_i_2_n_0\ ); -\skid_buffer[18]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[18]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"EFEEEFEEFFFFEFEE" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(143), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(111), - I4 => \skid_buffer[18]_i_4_n_0\, + I0 => \skid_buffer[18]_i_4_n_0\, + I1 => \skid_buffer[18]_i_5_n_0\, + I2 => \^m_payload_i_reg[1]_0\, + I3 => m_axi_rdata(15), + I4 => m_axi_rdata(239), + I5 => \^m_payload_i_reg[2]_1\, O => \skid_buffer[18]_i_3_n_0\ ); \skid_buffer[18]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"00000C0800000008" ) port map ( - I0 => m_axi_rdata(175), - I1 => m_axi_rdata(207), + I0 => m_axi_rdata(143), + I1 => m_atarget_enc(2), I2 => m_atarget_enc(3), I3 => m_atarget_enc(0), I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I5 => m_axi_rdata(175), O => \skid_buffer[18]_i_4_n_0\ ); +\skid_buffer[18]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00002C0000002000" + ) + port map ( + I0 => m_axi_rdata(303), + I1 => m_atarget_enc(1), + I2 => m_atarget_enc(0), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(335), + O => \skid_buffer[18]_i_5_n_0\ + ); \skid_buffer[19]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFEFFFEFFFFFFFE" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, - I1 => m_axi_rdata(48), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(80), - I4 => \skid_buffer[19]_i_2_n_0\, - I5 => \skid_buffer[19]_i_3_n_0\, - O => aa_rmesg(19) + I0 => \skid_buffer[19]_i_2_n_0\, + I1 => \skid_buffer[19]_i_3_n_0\, + I2 => \skid_buffer[19]_i_4_n_0\, + I3 => \skid_buffer[19]_i_5_n_0\, + I4 => m_axi_rdata(48), + I5 => \skid_buffer[34]_i_2_n_0\, + O => \skid_buffer[19]_i_1_n_0\ ); \skid_buffer[19]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(272), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(240), - I4 => m_axi_rdata(16), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_axi_rdata(80), + I1 => \skid_buffer[31]_i_2_n_0\, + I2 => m_axi_rdata(112), + I3 => \m_payload_i[1]_i_2_n_0\, + I4 => \skid_buffer[32]_i_6_n_0\, + I5 => m_axi_rdata(144), O => \skid_buffer[19]_i_2_n_0\ ); -\skid_buffer[19]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[19]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"0008000300080000" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(144), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(112), - I4 => \skid_buffer[19]_i_4_n_0\, + I0 => m_axi_rdata(208), + I1 => m_atarget_enc(1), + I2 => m_atarget_enc(0), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(16), O => \skid_buffer[19]_i_3_n_0\ ); \skid_buffer[19]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"08000C0008000000" ) port map ( - I0 => m_axi_rdata(176), - I1 => m_axi_rdata(208), + I0 => m_axi_rdata(240), + I1 => m_atarget_enc(2), I2 => m_atarget_enc(3), I3 => m_atarget_enc(0), I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I5 => m_axi_rdata(176), O => \skid_buffer[19]_i_4_n_0\ ); -\skid_buffer[1]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFFFFFFFFFF888" - ) - port map ( - I0 => \^skid_buffer_reg[1]_0\, - I1 => m_axi_rresp(2), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rresp(4), - I4 => \skid_buffer[1]_i_2_n_0\, - I5 => \skid_buffer[1]_i_3_n_0\, - O => aa_rmesg(1) - ); -\skid_buffer[1]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"AABAAAABAABAAAAA" - ) - port map ( - I0 => \skid_buffer[1]_i_4_n_0\, - I1 => m_atarget_enc(1), - I2 => m_atarget_enc(0), - I3 => m_atarget_enc(2), - I4 => m_atarget_enc(3), - I5 => m_axi_rresp(0), - O => \skid_buffer[1]_i_2_n_0\ - ); -\skid_buffer[1]_i_3\: unisim.vcomponents.LUT5 - generic map( - INIT => X"FFFFF888" - ) - port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rresp(8), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rresp(6), - I4 => \skid_buffer[1]_i_5_n_0\, - O => \skid_buffer[1]_i_3_n_0\ - ); -\skid_buffer[1]_i_4\: unisim.vcomponents.LUT6 - generic map( - INIT => X"0000A000000C0000" - ) - port map ( - I0 => m_axi_rresp(14), - I1 => m_axi_rresp(16), - I2 => m_atarget_enc(0), - I3 => m_atarget_enc(2), - I4 => m_atarget_enc(3), - I5 => m_atarget_enc(1), - O => \skid_buffer[1]_i_4_n_0\ - ); -\skid_buffer[1]_i_5\: unisim.vcomponents.LUT6 +\skid_buffer[19]_i_5\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"00000CAF00000CA0" ) port map ( - I0 => m_axi_rresp(10), - I1 => m_axi_rresp(12), - I2 => m_atarget_enc(3), + I0 => m_axi_rdata(336), + I1 => m_axi_rdata(304), + I2 => m_atarget_enc(1), I3 => m_atarget_enc(0), - I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), - O => \skid_buffer[1]_i_5_n_0\ + I4 => \skid_buffer[28]_i_6_n_0\, + I5 => m_axi_rdata(272), + O => \skid_buffer[19]_i_5_n_0\ ); \skid_buffer[20]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFFFFFFFFFF4F44" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, + I0 => \skid_buffer[34]_i_2_n_0\, I1 => m_axi_rdata(49), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(81), + I2 => \skid_buffer[32]_i_6_n_0\, + I3 => m_axi_rdata(145), I4 => \skid_buffer[20]_i_2_n_0\, I5 => \skid_buffer[20]_i_3_n_0\, - O => aa_rmesg(20) + O => \skid_buffer[20]_i_1_n_0\ ); \skid_buffer[20]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(273), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(241), - I4 => m_axi_rdata(17), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_axi_rdata(273), + I1 => \^skid_buffer_reg[9]_0\, + I2 => m_axi_rdata(209), + I3 => \^m_payload_i_reg[2]_0\, + I4 => \skid_buffer[31]_i_2_n_0\, + I5 => m_axi_rdata(81), O => \skid_buffer[20]_i_2_n_0\ ); -\skid_buffer[20]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[20]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"EFEEEFEEFFFFEFEE" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(145), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(113), - I4 => \skid_buffer[20]_i_4_n_0\, + I0 => \skid_buffer[20]_i_4_n_0\, + I1 => \skid_buffer[20]_i_5_n_0\, + I2 => \^skid_buffer_reg[30]_0\, + I3 => m_axi_rdata(305), + I4 => m_axi_rdata(241), + I5 => \^m_payload_i_reg[2]_1\, O => \skid_buffer[20]_i_3_n_0\ ); \skid_buffer[20]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"02000C0002000000" ) port map ( - I0 => m_axi_rdata(177), - I1 => m_axi_rdata(209), + I0 => m_axi_rdata(113), + I1 => m_atarget_enc(2), I2 => m_atarget_enc(3), I3 => m_atarget_enc(0), I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I5 => m_axi_rdata(177), O => \skid_buffer[20]_i_4_n_0\ ); +\skid_buffer[20]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000080300000800" + ) + port map ( + I0 => m_axi_rdata(337), + I1 => m_atarget_enc(1), + I2 => m_atarget_enc(0), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(17), + O => \skid_buffer[20]_i_5_n_0\ + ); \skid_buffer[21]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFEFFFEFFFFFFFE" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, - I1 => m_axi_rdata(50), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(82), - I4 => \skid_buffer[21]_i_2_n_0\, - I5 => \skid_buffer[21]_i_3_n_0\, - O => aa_rmesg(21) + I0 => \skid_buffer[21]_i_2_n_0\, + I1 => \skid_buffer[21]_i_3_n_0\, + I2 => \skid_buffer[21]_i_4_n_0\, + I3 => \skid_buffer[21]_i_5_n_0\, + I4 => m_axi_rdata(114), + I5 => \m_payload_i[1]_i_2_n_0\, + O => \skid_buffer[21]_i_1_n_0\ ); \skid_buffer[21]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(274), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(242), - I4 => m_axi_rdata(18), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_axi_rdata(146), + I1 => \skid_buffer[32]_i_6_n_0\, + I2 => m_axi_rdata(82), + I3 => \skid_buffer[31]_i_2_n_0\, + I4 => \skid_buffer[34]_i_2_n_0\, + I5 => m_axi_rdata(50), O => \skid_buffer[21]_i_2_n_0\ ); -\skid_buffer[21]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[21]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"0020000300200000" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(146), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(114), - I4 => \skid_buffer[21]_i_4_n_0\, + I0 => m_axi_rdata(178), + I1 => m_atarget_enc(1), + I2 => m_atarget_enc(0), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(18), O => \skid_buffer[21]_i_3_n_0\ ); \skid_buffer[21]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"00000C2000000020" ) port map ( - I0 => m_axi_rdata(178), - I1 => m_axi_rdata(210), + I0 => m_axi_rdata(274), + I1 => m_atarget_enc(2), I2 => m_atarget_enc(3), - I3 => m_atarget_enc(0), - I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I3 => m_atarget_enc(1), + I4 => m_atarget_enc(0), + I5 => m_axi_rdata(210), O => \skid_buffer[21]_i_4_n_0\ ); +\skid_buffer[21]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"22F2FFFF22F222F2" + ) + port map ( + I0 => m_axi_rdata(338), + I1 => \m_payload_i[1]_i_5_n_0\, + I2 => m_axi_rdata(306), + I3 => \^skid_buffer_reg[30]_0\, + I4 => \^m_payload_i_reg[2]_1\, + I5 => m_axi_rdata(242), + O => \skid_buffer[21]_i_5_n_0\ + ); \skid_buffer[22]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFEFFFEFFFFFFFE" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, - I1 => m_axi_rdata(51), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(83), - I4 => \skid_buffer[22]_i_2_n_0\, - I5 => \skid_buffer[22]_i_3_n_0\, - O => aa_rmesg(22) + I0 => \skid_buffer[22]_i_2_n_0\, + I1 => \skid_buffer[22]_i_3_n_0\, + I2 => \skid_buffer[22]_i_4_n_0\, + I3 => \skid_buffer[22]_i_5_n_0\, + I4 => m_axi_rdata(115), + I5 => \m_payload_i[1]_i_2_n_0\, + O => \skid_buffer[22]_i_1_n_0\ ); \skid_buffer[22]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(275), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(243), - I4 => m_axi_rdata(19), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_axi_rdata(83), + I1 => \skid_buffer[31]_i_2_n_0\, + I2 => m_axi_rdata(51), + I3 => \skid_buffer[34]_i_2_n_0\, + I4 => \skid_buffer[32]_i_6_n_0\, + I5 => m_axi_rdata(147), O => \skid_buffer[22]_i_2_n_0\ ); -\skid_buffer[22]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[22]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"00080C0000080000" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(147), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(115), - I4 => \skid_buffer[22]_i_4_n_0\, + I0 => m_axi_rdata(179), + I1 => m_atarget_enc(0), + I2 => m_atarget_enc(1), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(307), O => \skid_buffer[22]_i_3_n_0\ ); \skid_buffer[22]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"00000C2000000020" ) port map ( - I0 => m_axi_rdata(179), - I1 => m_axi_rdata(211), + I0 => m_axi_rdata(275), + I1 => m_atarget_enc(2), I2 => m_atarget_enc(3), - I3 => m_atarget_enc(0), - I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I3 => m_atarget_enc(1), + I4 => m_atarget_enc(0), + I5 => m_axi_rdata(211), O => \skid_buffer[22]_i_4_n_0\ ); +\skid_buffer[22]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"22F2FFFF22F222F2" + ) + port map ( + I0 => m_axi_rdata(19), + I1 => \^m_payload_i_reg[1]_0\, + I2 => m_axi_rdata(339), + I3 => \m_payload_i[1]_i_5_n_0\, + I4 => \^m_payload_i_reg[2]_1\, + I5 => m_axi_rdata(243), + O => \skid_buffer[22]_i_5_n_0\ + ); \skid_buffer[23]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFFFFFFFFFF4F44" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, + I0 => \skid_buffer[34]_i_2_n_0\, I1 => m_axi_rdata(52), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(84), + I2 => \m_payload_i[1]_i_2_n_0\, + I3 => m_axi_rdata(116), I4 => \skid_buffer[23]_i_2_n_0\, I5 => \skid_buffer[23]_i_3_n_0\, - O => aa_rmesg(23) + O => \skid_buffer[23]_i_1_n_0\ ); \skid_buffer[23]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(276), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(244), - I4 => m_axi_rdata(20), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_axi_rdata(276), + I1 => \^skid_buffer_reg[9]_0\, + I2 => m_axi_rdata(180), + I3 => \skid_buffer[34]_i_5_n_0\, + I4 => \skid_buffer[31]_i_2_n_0\, + I5 => m_axi_rdata(84), O => \skid_buffer[23]_i_2_n_0\ ); -\skid_buffer[23]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[23]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"EFEEEFEEFFFFEFEE" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(148), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(116), - I4 => \skid_buffer[23]_i_4_n_0\, + I0 => \skid_buffer[23]_i_4_n_0\, + I1 => \skid_buffer[23]_i_5_n_0\, + I2 => \^m_payload_i_reg[1]_0\, + I3 => m_axi_rdata(20), + I4 => m_axi_rdata(244), + I5 => \^m_payload_i_reg[2]_1\, O => \skid_buffer[23]_i_3_n_0\ ); \skid_buffer[23]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"00000C0800000008" ) port map ( - I0 => m_axi_rdata(180), - I1 => m_axi_rdata(212), + I0 => m_axi_rdata(148), + I1 => m_atarget_enc(2), I2 => m_atarget_enc(3), - I3 => m_atarget_enc(0), - I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I3 => m_atarget_enc(1), + I4 => m_atarget_enc(0), + I5 => m_axi_rdata(212), O => \skid_buffer[23]_i_4_n_0\ ); +\skid_buffer[23]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00002C0000002000" + ) + port map ( + I0 => m_axi_rdata(308), + I1 => m_atarget_enc(1), + I2 => m_atarget_enc(0), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(340), + O => \skid_buffer[23]_i_5_n_0\ + ); \skid_buffer[24]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFEFFFEFFFFFFFE" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, - I1 => m_axi_rdata(53), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(85), - I4 => \skid_buffer[24]_i_2_n_0\, - I5 => \skid_buffer[24]_i_3_n_0\, - O => aa_rmesg(24) + I0 => \skid_buffer[24]_i_2_n_0\, + I1 => \skid_buffer[24]_i_3_n_0\, + I2 => \skid_buffer[24]_i_4_n_0\, + I3 => \skid_buffer[24]_i_5_n_0\, + I4 => m_axi_rdata(117), + I5 => \m_payload_i[1]_i_2_n_0\, + O => \skid_buffer[24]_i_1_n_0\ ); \skid_buffer[24]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(277), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(245), - I4 => m_axi_rdata(21), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_axi_rdata(149), + I1 => \skid_buffer[32]_i_6_n_0\, + I2 => m_axi_rdata(85), + I3 => \skid_buffer[31]_i_2_n_0\, + I4 => \skid_buffer[34]_i_2_n_0\, + I5 => m_axi_rdata(53), O => \skid_buffer[24]_i_2_n_0\ ); -\skid_buffer[24]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[24]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"00200C0000200000" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(149), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(117), - I4 => \skid_buffer[24]_i_4_n_0\, + I0 => m_axi_rdata(213), + I1 => m_atarget_enc(0), + I2 => m_atarget_enc(1), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(309), O => \skid_buffer[24]_i_3_n_0\ ); \skid_buffer[24]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"00000C2000000020" ) port map ( - I0 => m_axi_rdata(181), - I1 => m_axi_rdata(213), + I0 => m_axi_rdata(277), + I1 => m_atarget_enc(2), I2 => m_atarget_enc(3), I3 => m_atarget_enc(0), I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I5 => m_axi_rdata(181), O => \skid_buffer[24]_i_4_n_0\ ); +\skid_buffer[24]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"22F2FFFF22F222F2" + ) + port map ( + I0 => m_axi_rdata(21), + I1 => \^m_payload_i_reg[1]_0\, + I2 => m_axi_rdata(341), + I3 => \m_payload_i[1]_i_5_n_0\, + I4 => \^m_payload_i_reg[2]_1\, + I5 => m_axi_rdata(245), + O => \skid_buffer[24]_i_5_n_0\ + ); \skid_buffer[25]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFFFFFFFFFF4F44" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, + I0 => \skid_buffer[34]_i_2_n_0\, I1 => m_axi_rdata(54), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(86), + I2 => \m_payload_i[1]_i_2_n_0\, + I3 => m_axi_rdata(118), I4 => \skid_buffer[25]_i_2_n_0\, I5 => \skid_buffer[25]_i_3_n_0\, - O => aa_rmesg(25) + O => \skid_buffer[25]_i_1_n_0\ ); \skid_buffer[25]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(278), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(246), - I4 => m_axi_rdata(22), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_axi_rdata(278), + I1 => \^skid_buffer_reg[9]_0\, + I2 => m_axi_rdata(214), + I3 => \^m_payload_i_reg[2]_0\, + I4 => \skid_buffer[31]_i_2_n_0\, + I5 => m_axi_rdata(86), O => \skid_buffer[25]_i_2_n_0\ ); -\skid_buffer[25]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[25]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"EFEEEFEEFFFFEFEE" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(150), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(118), - I4 => \skid_buffer[25]_i_4_n_0\, + I0 => \skid_buffer[25]_i_4_n_0\, + I1 => \skid_buffer[25]_i_5_n_0\, + I2 => \m_payload_i[1]_i_5_n_0\, + I3 => m_axi_rdata(342), + I4 => m_axi_rdata(246), + I5 => \^m_payload_i_reg[2]_1\, O => \skid_buffer[25]_i_3_n_0\ ); \skid_buffer[25]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"00000C0800000008" ) port map ( - I0 => m_axi_rdata(182), - I1 => m_axi_rdata(214), + I0 => m_axi_rdata(150), + I1 => m_atarget_enc(2), I2 => m_atarget_enc(3), I3 => m_atarget_enc(0), I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I5 => m_axi_rdata(182), O => \skid_buffer[25]_i_4_n_0\ ); +\skid_buffer[25]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000200300002000" + ) + port map ( + I0 => m_axi_rdata(310), + I1 => m_atarget_enc(1), + I2 => m_atarget_enc(0), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(22), + O => \skid_buffer[25]_i_5_n_0\ + ); \skid_buffer[26]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFEFFFEFFFFFFFE" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, - I1 => m_axi_rdata(55), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(87), - I4 => \skid_buffer[26]_i_2_n_0\, - I5 => \skid_buffer[26]_i_3_n_0\, - O => aa_rmesg(26) + I0 => \skid_buffer[26]_i_2_n_0\, + I1 => \skid_buffer[26]_i_3_n_0\, + I2 => \skid_buffer[26]_i_4_n_0\, + I3 => \skid_buffer[26]_i_5_n_0\, + I4 => m_axi_rdata(87), + I5 => \skid_buffer[31]_i_2_n_0\, + O => \skid_buffer[26]_i_1_n_0\ ); \skid_buffer[26]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(279), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(247), - I4 => m_axi_rdata(23), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_axi_rdata(55), + I1 => \skid_buffer[34]_i_2_n_0\, + I2 => m_axi_rdata(151), + I3 => \skid_buffer[32]_i_6_n_0\, + I4 => \m_payload_i[1]_i_2_n_0\, + I5 => m_axi_rdata(119), O => \skid_buffer[26]_i_2_n_0\ ); -\skid_buffer[26]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[26]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"00200C0000200000" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(151), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(119), - I4 => \skid_buffer[26]_i_4_n_0\, + I0 => m_axi_rdata(215), + I1 => m_atarget_enc(0), + I2 => m_atarget_enc(1), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(311), O => \skid_buffer[26]_i_3_n_0\ ); \skid_buffer[26]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"00000C2000000020" ) port map ( - I0 => m_axi_rdata(183), - I1 => m_axi_rdata(215), + I0 => m_axi_rdata(279), + I1 => m_atarget_enc(2), I2 => m_atarget_enc(3), I3 => m_atarget_enc(0), I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I5 => m_axi_rdata(183), O => \skid_buffer[26]_i_4_n_0\ ); +\skid_buffer[26]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"22F2FFFF22F222F2" + ) + port map ( + I0 => m_axi_rdata(343), + I1 => \m_payload_i[1]_i_5_n_0\, + I2 => m_axi_rdata(23), + I3 => \^m_payload_i_reg[1]_0\, + I4 => \^m_payload_i_reg[2]_1\, + I5 => m_axi_rdata(247), + O => \skid_buffer[26]_i_5_n_0\ + ); \skid_buffer[27]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFEFFFEFFFFFFFE" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, - I1 => m_axi_rdata(56), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(88), - I4 => \skid_buffer[27]_i_2_n_0\, - I5 => \skid_buffer[27]_i_3_n_0\, - O => aa_rmesg(27) + I0 => \skid_buffer[27]_i_2_n_0\, + I1 => \skid_buffer[27]_i_3_n_0\, + I2 => \skid_buffer[27]_i_4_n_0\, + I3 => \skid_buffer[27]_i_5_n_0\, + I4 => m_axi_rdata(120), + I5 => \m_payload_i[1]_i_2_n_0\, + O => \skid_buffer[27]_i_1_n_0\ ); \skid_buffer[27]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(280), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(248), - I4 => m_axi_rdata(24), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_axi_rdata(152), + I1 => \skid_buffer[32]_i_6_n_0\, + I2 => m_axi_rdata(56), + I3 => \skid_buffer[34]_i_2_n_0\, + I4 => \skid_buffer[31]_i_2_n_0\, + I5 => m_axi_rdata(88), O => \skid_buffer[27]_i_2_n_0\ ); -\skid_buffer[27]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[27]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"0020000300200000" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(152), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(120), - I4 => \skid_buffer[27]_i_4_n_0\, + I0 => m_axi_rdata(184), + I1 => m_atarget_enc(1), + I2 => m_atarget_enc(0), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(24), O => \skid_buffer[27]_i_3_n_0\ ); \skid_buffer[27]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"08000C0008000000" ) port map ( - I0 => m_axi_rdata(184), - I1 => m_axi_rdata(216), + I0 => m_axi_rdata(248), + I1 => m_atarget_enc(2), I2 => m_atarget_enc(3), - I3 => m_atarget_enc(0), - I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I3 => m_atarget_enc(1), + I4 => m_atarget_enc(0), + I5 => m_axi_rdata(216), O => \skid_buffer[27]_i_4_n_0\ ); +\skid_buffer[27]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000ACF00000AC0" + ) + port map ( + I0 => m_axi_rdata(312), + I1 => m_axi_rdata(344), + I2 => m_atarget_enc(1), + I3 => m_atarget_enc(0), + I4 => \skid_buffer[28]_i_6_n_0\, + I5 => m_axi_rdata(280), + O => \skid_buffer[27]_i_5_n_0\ + ); \skid_buffer[28]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFEFFFEFFFFFFFE" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, - I1 => m_axi_rdata(57), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(89), - I4 => \skid_buffer[28]_i_2_n_0\, - I5 => \skid_buffer[28]_i_3_n_0\, - O => aa_rmesg(28) + I0 => \skid_buffer[28]_i_2_n_0\, + I1 => \skid_buffer[28]_i_3_n_0\, + I2 => \skid_buffer[28]_i_4_n_0\, + I3 => \skid_buffer[28]_i_5_n_0\, + I4 => m_axi_rdata(57), + I5 => \skid_buffer[34]_i_2_n_0\, + O => \skid_buffer[28]_i_1_n_0\ ); \skid_buffer[28]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(281), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(249), - I4 => m_axi_rdata(25), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_axi_rdata(89), + I1 => \skid_buffer[31]_i_2_n_0\, + I2 => m_axi_rdata(153), + I3 => \skid_buffer[32]_i_6_n_0\, + I4 => \m_payload_i[1]_i_2_n_0\, + I5 => m_axi_rdata(121), O => \skid_buffer[28]_i_2_n_0\ ); -\skid_buffer[28]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[28]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"0008000300080000" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(153), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(121), - I4 => \skid_buffer[28]_i_4_n_0\, + I0 => m_axi_rdata(217), + I1 => m_atarget_enc(1), + I2 => m_atarget_enc(0), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(25), O => \skid_buffer[28]_i_3_n_0\ ); \skid_buffer[28]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"08000C0008000000" ) port map ( - I0 => m_axi_rdata(185), - I1 => m_axi_rdata(217), + I0 => m_axi_rdata(249), + I1 => m_atarget_enc(2), I2 => m_atarget_enc(3), I3 => m_atarget_enc(0), I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I5 => m_axi_rdata(185), O => \skid_buffer[28]_i_4_n_0\ ); -\skid_buffer[29]_i_1\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFFFFFFFFFF888" - ) - port map ( - I0 => \^skid_buffer_reg[1]_0\, - I1 => m_axi_rdata(58), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(90), - I4 => \skid_buffer[29]_i_2_n_0\, - I5 => \skid_buffer[29]_i_3_n_0\, - O => aa_rmesg(29) - ); -\skid_buffer[29]_i_2\: unisim.vcomponents.LUT6 - generic map( - INIT => X"FFFFF888F888F888" - ) - port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(282), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(250), - I4 => m_axi_rdata(26), - I5 => \skid_buffer[34]_i_6_n_0\, - O => \skid_buffer[29]_i_2_n_0\ - ); -\skid_buffer[29]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[28]_i_5\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"00000CAF00000CA0" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(154), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(122), - I4 => \skid_buffer[29]_i_4_n_0\, - O => \skid_buffer[29]_i_3_n_0\ + I0 => m_axi_rdata(345), + I1 => m_axi_rdata(313), + I2 => m_atarget_enc(1), + I3 => m_atarget_enc(0), + I4 => \skid_buffer[28]_i_6_n_0\, + I5 => m_axi_rdata(281), + O => \skid_buffer[28]_i_5_n_0\ ); -\skid_buffer[29]_i_4\: unisim.vcomponents.LUT6 +\skid_buffer[28]_i_6\: unisim.vcomponents.LUT2 generic map( - INIT => X"000C0A0000000000" + INIT => X"B" ) port map ( - I0 => m_axi_rdata(186), - I1 => m_axi_rdata(218), - I2 => m_atarget_enc(3), - I3 => m_atarget_enc(0), - I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), - O => \skid_buffer[29]_i_4_n_0\ + I0 => m_atarget_enc(2), + I1 => m_atarget_enc(3), + O => \skid_buffer[28]_i_6_n_0\ ); -\skid_buffer[2]_i_1\: unisim.vcomponents.LUT6 +\skid_buffer[29]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFEFFFEFFFFFFFE" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, - I1 => m_axi_rresp(3), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rresp(5), - I4 => \skid_buffer[2]_i_2_n_0\, - I5 => \skid_buffer[2]_i_3_n_0\, - O => aa_rmesg(2) + I0 => \skid_buffer[29]_i_2_n_0\, + I1 => \skid_buffer[29]_i_3_n_0\, + I2 => \skid_buffer[29]_i_4_n_0\, + I3 => \skid_buffer[29]_i_5_n_0\, + I4 => m_axi_rdata(154), + I5 => \skid_buffer[32]_i_6_n_0\, + O => \skid_buffer[29]_i_1_n_0\ ); -\skid_buffer[2]_i_2\: unisim.vcomponents.LUT6 +\skid_buffer[29]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"AABAAAABAABAAAAA" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \skid_buffer[2]_i_4_n_0\, - I1 => m_atarget_enc(1), - I2 => m_atarget_enc(0), - I3 => m_atarget_enc(2), - I4 => m_atarget_enc(3), - I5 => m_axi_rresp(1), - O => \skid_buffer[2]_i_2_n_0\ + I0 => m_axi_rdata(122), + I1 => \m_payload_i[1]_i_2_n_0\, + I2 => m_axi_rdata(90), + I3 => \skid_buffer[31]_i_2_n_0\, + I4 => \skid_buffer[34]_i_2_n_0\, + I5 => m_axi_rdata(58), + O => \skid_buffer[29]_i_2_n_0\ ); -\skid_buffer[2]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[29]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"00080C0000080000" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rresp(9), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rresp(7), - I4 => \skid_buffer[2]_i_5_n_0\, - O => \skid_buffer[2]_i_3_n_0\ + I0 => m_axi_rdata(186), + I1 => m_atarget_enc(0), + I2 => m_atarget_enc(1), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(314), + O => \skid_buffer[29]_i_3_n_0\ ); -\skid_buffer[2]_i_4\: unisim.vcomponents.LUT6 +\skid_buffer[29]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"0000A000000C0000" + INIT => X"00000C2000000020" ) port map ( - I0 => m_axi_rresp(15), - I1 => m_axi_rresp(17), - I2 => m_atarget_enc(0), - I3 => m_atarget_enc(2), - I4 => m_atarget_enc(3), - I5 => m_atarget_enc(1), - O => \skid_buffer[2]_i_4_n_0\ + I0 => m_axi_rdata(282), + I1 => m_atarget_enc(2), + I2 => m_atarget_enc(3), + I3 => m_atarget_enc(1), + I4 => m_atarget_enc(0), + I5 => m_axi_rdata(218), + O => \skid_buffer[29]_i_4_n_0\ ); -\skid_buffer[2]_i_5\: unisim.vcomponents.LUT6 +\skid_buffer[29]_i_5\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => m_axi_rresp(11), - I1 => m_axi_rresp(13), - I2 => m_atarget_enc(3), - I3 => m_atarget_enc(0), - I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), - O => \skid_buffer[2]_i_5_n_0\ + I0 => m_axi_rdata(26), + I1 => \^m_payload_i_reg[1]_0\, + I2 => m_axi_rdata(346), + I3 => \m_payload_i[1]_i_5_n_0\, + I4 => \^m_payload_i_reg[2]_1\, + I5 => m_axi_rdata(250), + O => \skid_buffer[29]_i_5_n_0\ ); \skid_buffer[30]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFFFFFFFFFF4F44" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, + I0 => \skid_buffer[34]_i_2_n_0\, I1 => m_axi_rdata(59), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(91), + I2 => \skid_buffer[32]_i_6_n_0\, + I3 => m_axi_rdata(155), I4 => \skid_buffer[30]_i_2_n_0\, I5 => \skid_buffer[30]_i_3_n_0\, - O => aa_rmesg(30) + O => \skid_buffer[30]_i_1_n_0\ ); \skid_buffer[30]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(283), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(251), - I4 => m_axi_rdata(27), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_axi_rdata(283), + I1 => \^skid_buffer_reg[9]_0\, + I2 => m_axi_rdata(187), + I3 => \skid_buffer[34]_i_5_n_0\, + I4 => \skid_buffer[31]_i_2_n_0\, + I5 => m_axi_rdata(91), O => \skid_buffer[30]_i_2_n_0\ ); -\skid_buffer[30]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[30]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"EFEEEFEEFFFFEFEE" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(155), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(123), - I4 => \skid_buffer[30]_i_4_n_0\, + I0 => \skid_buffer[30]_i_4_n_0\, + I1 => \skid_buffer[30]_i_5_n_0\, + I2 => \^skid_buffer_reg[30]_0\, + I3 => m_axi_rdata(315), + I4 => m_axi_rdata(251), + I5 => \^m_payload_i_reg[2]_1\, O => \skid_buffer[30]_i_3_n_0\ ); \skid_buffer[30]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"02000C0002000000" ) port map ( - I0 => m_axi_rdata(187), - I1 => m_axi_rdata(219), + I0 => m_axi_rdata(123), + I1 => m_atarget_enc(2), I2 => m_atarget_enc(3), - I3 => m_atarget_enc(0), - I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I3 => m_atarget_enc(1), + I4 => m_atarget_enc(0), + I5 => m_axi_rdata(219), O => \skid_buffer[30]_i_4_n_0\ ); +\skid_buffer[30]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000080300000800" + ) + port map ( + I0 => m_axi_rdata(347), + I1 => m_atarget_enc(1), + I2 => m_atarget_enc(0), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(27), + O => \skid_buffer[30]_i_5_n_0\ + ); \skid_buffer[31]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFFFFFFFFFF4F44" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, - I1 => m_axi_rdata(60), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(92), - I4 => \skid_buffer[31]_i_2_n_0\, - I5 => \skid_buffer[31]_i_3_n_0\, - O => aa_rmesg(31) + I0 => \skid_buffer[31]_i_2_n_0\, + I1 => m_axi_rdata(92), + I2 => \m_payload_i[1]_i_2_n_0\, + I3 => m_axi_rdata(124), + I4 => \skid_buffer[31]_i_3_n_0\, + I5 => \skid_buffer[31]_i_4_n_0\, + O => \skid_buffer[31]_i_1_n_0\ ); -\skid_buffer[31]_i_2\: unisim.vcomponents.LUT6 +\skid_buffer[31]_i_2\: unisim.vcomponents.LUT4 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"FFFD" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(284), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(252), - I4 => m_axi_rdata(28), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_atarget_enc(1), + I1 => m_atarget_enc(0), + I2 => m_atarget_enc(3), + I3 => m_atarget_enc(2), O => \skid_buffer[31]_i_2_n_0\ ); -\skid_buffer[31]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[31]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(156), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(124), - I4 => \skid_buffer[31]_i_4_n_0\, + I0 => m_axi_rdata(188), + I1 => \skid_buffer[34]_i_5_n_0\, + I2 => m_axi_rdata(252), + I3 => \^m_payload_i_reg[2]_1\, + I4 => \skid_buffer[34]_i_2_n_0\, + I5 => m_axi_rdata(60), O => \skid_buffer[31]_i_3_n_0\ ); \skid_buffer[31]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"EFEEEFEEFFFFEFEE" ) port map ( - I0 => m_axi_rdata(188), - I1 => m_axi_rdata(220), - I2 => m_atarget_enc(3), - I3 => m_atarget_enc(0), - I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I0 => \skid_buffer[31]_i_5_n_0\, + I1 => \skid_buffer[31]_i_6_n_0\, + I2 => \^m_payload_i_reg[1]_0\, + I3 => m_axi_rdata(28), + I4 => m_axi_rdata(220), + I5 => \^m_payload_i_reg[2]_0\, O => \skid_buffer[31]_i_4_n_0\ ); +\skid_buffer[31]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0002030000020000" + ) + port map ( + I0 => m_axi_rdata(156), + I1 => m_atarget_enc(1), + I2 => m_atarget_enc(0), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(284), + O => \skid_buffer[31]_i_5_n_0\ + ); +\skid_buffer[31]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00002C0000002000" + ) + port map ( + I0 => m_axi_rdata(316), + I1 => m_atarget_enc(1), + I2 => m_atarget_enc(0), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(348), + O => \skid_buffer[31]_i_6_n_0\ + ); \skid_buffer[32]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFEFFFEFFFFFFFE" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, - I1 => m_axi_rdata(61), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(93), - I4 => \skid_buffer[32]_i_2_n_0\, - I5 => \skid_buffer[32]_i_3_n_0\, - O => aa_rmesg(32) + I0 => \skid_buffer[32]_i_2_n_0\, + I1 => \skid_buffer[32]_i_3_n_0\, + I2 => \skid_buffer[32]_i_4_n_0\, + I3 => \skid_buffer[32]_i_5_n_0\, + I4 => m_axi_rdata(157), + I5 => \skid_buffer[32]_i_6_n_0\, + O => \skid_buffer[32]_i_1_n_0\ ); \skid_buffer[32]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(285), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(253), - I4 => m_axi_rdata(29), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_axi_rdata(93), + I1 => \skid_buffer[31]_i_2_n_0\, + I2 => m_axi_rdata(61), + I3 => \skid_buffer[34]_i_2_n_0\, + I4 => \m_payload_i[1]_i_2_n_0\, + I5 => m_axi_rdata(125), O => \skid_buffer[32]_i_2_n_0\ ); -\skid_buffer[32]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[32]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"00080C0000080000" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(157), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(125), - I4 => \skid_buffer[32]_i_4_n_0\, + I0 => m_axi_rdata(189), + I1 => m_atarget_enc(0), + I2 => m_atarget_enc(1), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(317), O => \skid_buffer[32]_i_3_n_0\ ); \skid_buffer[32]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"08000C0008000000" ) port map ( - I0 => m_axi_rdata(189), - I1 => m_axi_rdata(221), + I0 => m_axi_rdata(253), + I1 => m_atarget_enc(2), I2 => m_atarget_enc(3), - I3 => m_atarget_enc(0), - I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I3 => m_atarget_enc(1), + I4 => m_atarget_enc(0), + I5 => m_axi_rdata(221), O => \skid_buffer[32]_i_4_n_0\ ); +\skid_buffer[32]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"22F2FFFF22F222F2" + ) + port map ( + I0 => m_axi_rdata(29), + I1 => \^m_payload_i_reg[1]_0\, + I2 => m_axi_rdata(349), + I3 => \m_payload_i[1]_i_5_n_0\, + I4 => \^skid_buffer_reg[9]_0\, + I5 => m_axi_rdata(285), + O => \skid_buffer[32]_i_5_n_0\ + ); +\skid_buffer[32]_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFD" + ) + port map ( + I0 => m_atarget_enc(2), + I1 => m_atarget_enc(3), + I2 => m_atarget_enc(1), + I3 => m_atarget_enc(0), + O => \skid_buffer[32]_i_6_n_0\ + ); \skid_buffer[33]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFEFFFEFFFFFFFE" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, - I1 => m_axi_rdata(62), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(94), - I4 => \skid_buffer[33]_i_2_n_0\, - I5 => \skid_buffer[33]_i_3_n_0\, - O => aa_rmesg(33) + I0 => \skid_buffer[33]_i_2_n_0\, + I1 => \skid_buffer[33]_i_3_n_0\, + I2 => \skid_buffer[33]_i_4_n_0\, + I3 => \skid_buffer[33]_i_5_n_0\, + I4 => m_axi_rdata(126), + I5 => \m_payload_i[1]_i_2_n_0\, + O => \skid_buffer[33]_i_1_n_0\ ); \skid_buffer[33]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(286), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(254), - I4 => m_axi_rdata(30), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_axi_rdata(158), + I1 => \skid_buffer[32]_i_6_n_0\, + I2 => m_axi_rdata(94), + I3 => \skid_buffer[31]_i_2_n_0\, + I4 => \skid_buffer[34]_i_2_n_0\, + I5 => m_axi_rdata(62), O => \skid_buffer[33]_i_2_n_0\ ); -\skid_buffer[33]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[33]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"0020000300200000" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(158), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(126), - I4 => \skid_buffer[33]_i_4_n_0\, + I0 => m_axi_rdata(190), + I1 => m_atarget_enc(1), + I2 => m_atarget_enc(0), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(30), O => \skid_buffer[33]_i_3_n_0\ ); \skid_buffer[33]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"00000C2000000020" ) port map ( - I0 => m_axi_rdata(190), - I1 => m_axi_rdata(222), + I0 => m_axi_rdata(286), + I1 => m_atarget_enc(2), I2 => m_atarget_enc(3), - I3 => m_atarget_enc(0), - I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I3 => m_atarget_enc(1), + I4 => m_atarget_enc(0), + I5 => m_axi_rdata(222), O => \skid_buffer[33]_i_4_n_0\ ); +\skid_buffer[33]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"22F2FFFF22F222F2" + ) + port map ( + I0 => m_axi_rdata(318), + I1 => \^skid_buffer_reg[30]_0\, + I2 => m_axi_rdata(350), + I3 => \m_payload_i[1]_i_5_n_0\, + I4 => \^m_payload_i_reg[2]_1\, + I5 => m_axi_rdata(254), + O => \skid_buffer[33]_i_5_n_0\ + ); \skid_buffer[34]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFFFFFFFFFF4F44" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, + I0 => \skid_buffer[34]_i_2_n_0\, I1 => m_axi_rdata(63), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(95), - I4 => \skid_buffer[34]_i_2_n_0\, - I5 => \skid_buffer[34]_i_3_n_0\, - O => aa_rmesg(34) + I2 => \m_payload_i[1]_i_2_n_0\, + I3 => m_axi_rdata(127), + I4 => \skid_buffer[34]_i_3_n_0\, + I5 => \skid_buffer[34]_i_4_n_0\, + O => \skid_buffer[34]_i_1_n_0\ ); -\skid_buffer[34]_i_2\: unisim.vcomponents.LUT6 +\skid_buffer[34]_i_2\: unisim.vcomponents.LUT4 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"FFFD" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(287), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(255), - I4 => m_axi_rdata(31), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_atarget_enc(0), + I1 => m_atarget_enc(1), + I2 => m_atarget_enc(3), + I3 => m_atarget_enc(2), O => \skid_buffer[34]_i_2_n_0\ ); -\skid_buffer[34]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[34]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(159), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(127), - I4 => \skid_buffer[34]_i_7_n_0\, + I0 => m_axi_rdata(287), + I1 => \^skid_buffer_reg[9]_0\, + I2 => m_axi_rdata(191), + I3 => \skid_buffer[34]_i_5_n_0\, + I4 => \skid_buffer[31]_i_2_n_0\, + I5 => m_axi_rdata(95), O => \skid_buffer[34]_i_3_n_0\ ); -\skid_buffer[34]_i_4\: unisim.vcomponents.LUT4 +\skid_buffer[34]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"0010" + INIT => X"EFEEEFEEFFFFEFEE" ) port map ( - I0 => m_atarget_enc(0), - I1 => m_atarget_enc(2), - I2 => m_atarget_enc(3), - I3 => m_atarget_enc(1), + I0 => \skid_buffer[34]_i_6_n_0\, + I1 => \skid_buffer[34]_i_7_n_0\, + I2 => \m_payload_i[1]_i_5_n_0\, + I3 => m_axi_rdata(351), + I4 => m_axi_rdata(255), + I5 => \^m_payload_i_reg[2]_1\, O => \skid_buffer[34]_i_4_n_0\ ); \skid_buffer[34]_i_5\: unisim.vcomponents.LUT4 generic map( - INIT => X"2000" + INIT => X"FFDF" ) port map ( I0 => m_atarget_enc(2), @@ -5277,392 +5986,492 @@ s_ready_i_reg: unisim.vcomponents.FDRE I3 => m_atarget_enc(1), O => \skid_buffer[34]_i_5_n_0\ ); -\skid_buffer[34]_i_6\: unisim.vcomponents.LUT4 +\skid_buffer[34]_i_6\: unisim.vcomponents.LUT6 generic map( - INIT => X"0001" + INIT => X"00000C0800000008" ) port map ( - I0 => m_atarget_enc(3), + I0 => m_axi_rdata(159), I1 => m_atarget_enc(2), - I2 => m_atarget_enc(0), + I2 => m_atarget_enc(3), I3 => m_atarget_enc(1), + I4 => m_atarget_enc(0), + I5 => m_axi_rdata(223), O => \skid_buffer[34]_i_6_n_0\ ); \skid_buffer[34]_i_7\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"0000200300002000" ) port map ( - I0 => m_axi_rdata(191), - I1 => m_axi_rdata(223), - I2 => m_atarget_enc(3), - I3 => m_atarget_enc(0), - I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I0 => m_axi_rdata(319), + I1 => m_atarget_enc(1), + I2 => m_atarget_enc(0), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(31), O => \skid_buffer[34]_i_7_n_0\ ); \skid_buffer[3]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFFFFFFFFFF4F44" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, + I0 => \skid_buffer[34]_i_2_n_0\, I1 => m_axi_rdata(32), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(64), + I2 => \skid_buffer[32]_i_6_n_0\, + I3 => m_axi_rdata(128), I4 => \skid_buffer[3]_i_2_n_0\, I5 => \skid_buffer[3]_i_3_n_0\, - O => aa_rmesg(3) + O => \skid_buffer[3]_i_1_n_0\ ); \skid_buffer[3]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(256), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(224), - I4 => m_axi_rdata(0), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_axi_rdata(192), + I1 => \^m_payload_i_reg[2]_0\, + I2 => m_axi_rdata(224), + I3 => \^m_payload_i_reg[2]_1\, + I4 => \skid_buffer[31]_i_2_n_0\, + I5 => m_axi_rdata(64), O => \skid_buffer[3]_i_2_n_0\ ); -\skid_buffer[3]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[3]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"EFEEEFEEFFFFEFEE" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(128), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(96), - I4 => \skid_buffer[3]_i_4_n_0\, + I0 => \skid_buffer[3]_i_4_n_0\, + I1 => \skid_buffer[3]_i_5_n_0\, + I2 => \m_payload_i[1]_i_5_n_0\, + I3 => m_axi_rdata(320), + I4 => m_axi_rdata(160), + I5 => \skid_buffer[34]_i_5_n_0\, O => \skid_buffer[3]_i_3_n_0\ ); \skid_buffer[3]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"0000038000000080" ) port map ( - I0 => m_axi_rdata(160), - I1 => m_axi_rdata(192), - I2 => m_atarget_enc(3), - I3 => m_atarget_enc(0), - I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I0 => m_axi_rdata(96), + I1 => m_atarget_enc(1), + I2 => m_atarget_enc(0), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(256), O => \skid_buffer[3]_i_4_n_0\ ); +\skid_buffer[3]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000C0200000002" + ) + port map ( + I0 => m_axi_rdata(0), + I1 => m_atarget_enc(0), + I2 => m_atarget_enc(1), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(288), + O => \skid_buffer[3]_i_5_n_0\ + ); \skid_buffer[4]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFFFFFFFFFF4F44" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, + I0 => \skid_buffer[34]_i_2_n_0\, I1 => m_axi_rdata(33), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(65), + I2 => \skid_buffer[32]_i_6_n_0\, + I3 => m_axi_rdata(129), I4 => \skid_buffer[4]_i_2_n_0\, I5 => \skid_buffer[4]_i_3_n_0\, - O => aa_rmesg(4) + O => \skid_buffer[4]_i_1_n_0\ ); \skid_buffer[4]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(257), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(225), - I4 => m_axi_rdata(1), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_axi_rdata(193), + I1 => \^m_payload_i_reg[2]_0\, + I2 => m_axi_rdata(225), + I3 => \^m_payload_i_reg[2]_1\, + I4 => \skid_buffer[31]_i_2_n_0\, + I5 => m_axi_rdata(65), O => \skid_buffer[4]_i_2_n_0\ ); -\skid_buffer[4]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[4]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"EFEEEFEEFFFFEFEE" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(129), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(97), - I4 => \skid_buffer[4]_i_4_n_0\, + I0 => \skid_buffer[4]_i_4_n_0\, + I1 => \skid_buffer[4]_i_5_n_0\, + I2 => \^skid_buffer_reg[30]_0\, + I3 => m_axi_rdata(289), + I4 => m_axi_rdata(161), + I5 => \skid_buffer[34]_i_5_n_0\, O => \skid_buffer[4]_i_3_n_0\ ); \skid_buffer[4]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"0000038000000080" ) port map ( - I0 => m_axi_rdata(161), - I1 => m_axi_rdata(193), - I2 => m_atarget_enc(3), - I3 => m_atarget_enc(0), - I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I0 => m_axi_rdata(97), + I1 => m_atarget_enc(1), + I2 => m_atarget_enc(0), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(257), O => \skid_buffer[4]_i_4_n_0\ ); +\skid_buffer[4]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000C0200000002" + ) + port map ( + I0 => m_axi_rdata(1), + I1 => m_atarget_enc(1), + I2 => m_atarget_enc(0), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(321), + O => \skid_buffer[4]_i_5_n_0\ + ); \skid_buffer[5]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFEFFFEFFFFFFFE" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, - I1 => m_axi_rdata(34), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(66), - I4 => \skid_buffer[5]_i_2_n_0\, - I5 => \skid_buffer[5]_i_3_n_0\, - O => aa_rmesg(5) + I0 => \skid_buffer[5]_i_2_n_0\, + I1 => \skid_buffer[5]_i_3_n_0\, + I2 => \skid_buffer[5]_i_4_n_0\, + I3 => \skid_buffer[5]_i_5_n_0\, + I4 => m_axi_rdata(66), + I5 => \skid_buffer[31]_i_2_n_0\, + O => \skid_buffer[5]_i_1_n_0\ ); \skid_buffer[5]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(258), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(226), - I4 => m_axi_rdata(2), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_axi_rdata(34), + I1 => \skid_buffer[34]_i_2_n_0\, + I2 => m_axi_rdata(98), + I3 => \m_payload_i[1]_i_2_n_0\, + I4 => \skid_buffer[32]_i_6_n_0\, + I5 => m_axi_rdata(130), O => \skid_buffer[5]_i_2_n_0\ ); -\skid_buffer[5]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[5]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"00200C0000200000" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(130), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(98), - I4 => \skid_buffer[5]_i_4_n_0\, + I0 => m_axi_rdata(194), + I1 => m_atarget_enc(0), + I2 => m_atarget_enc(1), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(290), O => \skid_buffer[5]_i_3_n_0\ ); \skid_buffer[5]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"08000C0008000000" ) port map ( - I0 => m_axi_rdata(162), - I1 => m_axi_rdata(194), + I0 => m_axi_rdata(226), + I1 => m_atarget_enc(2), I2 => m_atarget_enc(3), I3 => m_atarget_enc(0), I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I5 => m_axi_rdata(162), O => \skid_buffer[5]_i_4_n_0\ ); +\skid_buffer[5]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"22F2FFFF22F222F2" + ) + port map ( + I0 => m_axi_rdata(322), + I1 => \m_payload_i[1]_i_5_n_0\, + I2 => m_axi_rdata(2), + I3 => \^m_payload_i_reg[1]_0\, + I4 => \^skid_buffer_reg[9]_0\, + I5 => m_axi_rdata(258), + O => \skid_buffer[5]_i_5_n_0\ + ); \skid_buffer[6]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFEFFFEFFFFFFFE" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, - I1 => m_axi_rdata(35), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(67), - I4 => \skid_buffer[6]_i_2_n_0\, - I5 => \skid_buffer[6]_i_3_n_0\, - O => aa_rmesg(6) + I0 => \skid_buffer[6]_i_2_n_0\, + I1 => \skid_buffer[6]_i_3_n_0\, + I2 => \skid_buffer[6]_i_4_n_0\, + I3 => \skid_buffer[6]_i_5_n_0\, + I4 => m_axi_rdata(99), + I5 => \m_payload_i[1]_i_2_n_0\, + O => \skid_buffer[6]_i_1_n_0\ ); \skid_buffer[6]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(259), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(227), - I4 => m_axi_rdata(3), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_axi_rdata(131), + I1 => \skid_buffer[32]_i_6_n_0\, + I2 => m_axi_rdata(35), + I3 => \skid_buffer[34]_i_2_n_0\, + I4 => \skid_buffer[31]_i_2_n_0\, + I5 => m_axi_rdata(67), O => \skid_buffer[6]_i_2_n_0\ ); -\skid_buffer[6]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[6]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"0008000300080000" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(131), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(99), - I4 => \skid_buffer[6]_i_4_n_0\, + I0 => m_axi_rdata(195), + I1 => m_atarget_enc(1), + I2 => m_atarget_enc(0), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(3), O => \skid_buffer[6]_i_3_n_0\ ); \skid_buffer[6]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"08000C0008000000" ) port map ( - I0 => m_axi_rdata(163), - I1 => m_axi_rdata(195), + I0 => m_axi_rdata(227), + I1 => m_atarget_enc(2), I2 => m_atarget_enc(3), I3 => m_atarget_enc(0), I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I5 => m_axi_rdata(163), O => \skid_buffer[6]_i_4_n_0\ ); +\skid_buffer[6]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000ACF00000AC0" + ) + port map ( + I0 => m_axi_rdata(291), + I1 => m_axi_rdata(323), + I2 => m_atarget_enc(1), + I3 => m_atarget_enc(0), + I4 => \skid_buffer[28]_i_6_n_0\, + I5 => m_axi_rdata(259), + O => \skid_buffer[6]_i_5_n_0\ + ); \skid_buffer[7]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFEFFFEFFFFFFFE" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, - I1 => m_axi_rdata(36), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(68), - I4 => \skid_buffer[7]_i_2_n_0\, - I5 => \skid_buffer[7]_i_3_n_0\, - O => aa_rmesg(7) + I0 => \skid_buffer[7]_i_2_n_0\, + I1 => \skid_buffer[7]_i_3_n_0\, + I2 => \skid_buffer[7]_i_4_n_0\, + I3 => \skid_buffer[7]_i_5_n_0\, + I4 => m_axi_rdata(68), + I5 => \skid_buffer[31]_i_2_n_0\, + O => \skid_buffer[7]_i_1_n_0\ ); \skid_buffer[7]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(260), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(228), - I4 => m_axi_rdata(4), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_axi_rdata(36), + I1 => \skid_buffer[34]_i_2_n_0\, + I2 => m_axi_rdata(100), + I3 => \m_payload_i[1]_i_2_n_0\, + I4 => \skid_buffer[32]_i_6_n_0\, + I5 => m_axi_rdata(132), O => \skid_buffer[7]_i_2_n_0\ ); -\skid_buffer[7]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[7]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"00200C0000200000" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(132), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(100), - I4 => \skid_buffer[7]_i_4_n_0\, + I0 => m_axi_rdata(196), + I1 => m_atarget_enc(0), + I2 => m_atarget_enc(1), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(292), O => \skid_buffer[7]_i_3_n_0\ ); \skid_buffer[7]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"08000C0008000000" ) port map ( - I0 => m_axi_rdata(164), - I1 => m_axi_rdata(196), + I0 => m_axi_rdata(228), + I1 => m_atarget_enc(2), I2 => m_atarget_enc(3), I3 => m_atarget_enc(0), I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I5 => m_axi_rdata(164), O => \skid_buffer[7]_i_4_n_0\ ); +\skid_buffer[7]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"22F2FFFF22F222F2" + ) + port map ( + I0 => m_axi_rdata(324), + I1 => \m_payload_i[1]_i_5_n_0\, + I2 => m_axi_rdata(4), + I3 => \^m_payload_i_reg[1]_0\, + I4 => \^skid_buffer_reg[9]_0\, + I5 => m_axi_rdata(260), + O => \skid_buffer[7]_i_5_n_0\ + ); \skid_buffer[8]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFEFFFEFFFFFFFE" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, - I1 => m_axi_rdata(37), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(69), - I4 => \skid_buffer[8]_i_2_n_0\, - I5 => \skid_buffer[8]_i_3_n_0\, - O => aa_rmesg(8) + I0 => \skid_buffer[8]_i_2_n_0\, + I1 => \skid_buffer[8]_i_3_n_0\, + I2 => \skid_buffer[8]_i_4_n_0\, + I3 => \skid_buffer[8]_i_5_n_0\, + I4 => m_axi_rdata(69), + I5 => \skid_buffer[31]_i_2_n_0\, + O => \skid_buffer[8]_i_1_n_0\ ); \skid_buffer[8]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(261), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(229), - I4 => m_axi_rdata(5), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_axi_rdata(37), + I1 => \skid_buffer[34]_i_2_n_0\, + I2 => m_axi_rdata(101), + I3 => \m_payload_i[1]_i_2_n_0\, + I4 => \skid_buffer[32]_i_6_n_0\, + I5 => m_axi_rdata(133), O => \skid_buffer[8]_i_2_n_0\ ); -\skid_buffer[8]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[8]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"00080C0000080000" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(133), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(101), - I4 => \skid_buffer[8]_i_4_n_0\, + I0 => m_axi_rdata(197), + I1 => m_atarget_enc(1), + I2 => m_atarget_enc(0), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(325), O => \skid_buffer[8]_i_3_n_0\ ); \skid_buffer[8]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"00000C2000000020" ) port map ( - I0 => m_axi_rdata(165), - I1 => m_axi_rdata(197), + I0 => m_axi_rdata(261), + I1 => m_atarget_enc(2), I2 => m_atarget_enc(3), I3 => m_atarget_enc(0), I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I5 => m_axi_rdata(165), O => \skid_buffer[8]_i_4_n_0\ ); +\skid_buffer[8]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"22F2FFFF22F222F2" + ) + port map ( + I0 => m_axi_rdata(293), + I1 => \^skid_buffer_reg[30]_0\, + I2 => m_axi_rdata(5), + I3 => \^m_payload_i_reg[1]_0\, + I4 => \^m_payload_i_reg[2]_1\, + I5 => m_axi_rdata(229), + O => \skid_buffer[8]_i_5_n_0\ + ); \skid_buffer[9]_i_1\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFFFFFFFFFF4F44" ) port map ( - I0 => \^skid_buffer_reg[1]_0\, + I0 => \skid_buffer[34]_i_2_n_0\, I1 => m_axi_rdata(38), - I2 => \^skid_buffer_reg[1]_1\, - I3 => m_axi_rdata(70), + I2 => \m_payload_i[1]_i_2_n_0\, + I3 => m_axi_rdata(102), I4 => \skid_buffer[9]_i_2_n_0\, I5 => \skid_buffer[9]_i_3_n_0\, - O => aa_rmesg(9) + O => \skid_buffer[9]_i_1_n_0\ ); \skid_buffer[9]_i_2\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888F888F888" + INIT => X"22F2FFFF22F222F2" ) port map ( - I0 => \skid_buffer[34]_i_4_n_0\, - I1 => m_axi_rdata(262), - I2 => \skid_buffer[34]_i_5_n_0\, - I3 => m_axi_rdata(230), - I4 => m_axi_rdata(6), - I5 => \skid_buffer[34]_i_6_n_0\, + I0 => m_axi_rdata(262), + I1 => \^skid_buffer_reg[9]_0\, + I2 => m_axi_rdata(198), + I3 => \^m_payload_i_reg[2]_0\, + I4 => \skid_buffer[31]_i_2_n_0\, + I5 => m_axi_rdata(70), O => \skid_buffer[9]_i_2_n_0\ ); -\skid_buffer[9]_i_3\: unisim.vcomponents.LUT5 +\skid_buffer[9]_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFF888" + INIT => X"EFEEEFEEFFFFEFEE" ) port map ( - I0 => \^skid_buffer_reg[1]_2\, - I1 => m_axi_rdata(134), - I2 => \^skid_buffer_reg[1]_3\, - I3 => m_axi_rdata(102), - I4 => \skid_buffer[9]_i_4_n_0\, + I0 => \skid_buffer[9]_i_4_n_0\, + I1 => \skid_buffer[9]_i_5_n_0\, + I2 => \m_payload_i[1]_i_5_n_0\, + I3 => m_axi_rdata(326), + I4 => m_axi_rdata(230), + I5 => \^m_payload_i_reg[2]_1\, O => \skid_buffer[9]_i_3_n_0\ ); \skid_buffer[9]_i_4\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"00000C0800000008" ) port map ( - I0 => m_axi_rdata(166), - I1 => m_axi_rdata(198), + I0 => m_axi_rdata(134), + I1 => m_atarget_enc(2), I2 => m_atarget_enc(3), I3 => m_atarget_enc(0), I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), + I5 => m_axi_rdata(166), O => \skid_buffer[9]_i_4_n_0\ ); +\skid_buffer[9]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000C0200000002" + ) + port map ( + I0 => m_axi_rdata(6), + I1 => m_atarget_enc(0), + I2 => m_atarget_enc(1), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_rdata(294), + O => \skid_buffer[9]_i_5_n_0\ + ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(0), + D => \skid_buffer[0]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); @@ -5670,7 +6479,7 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(10), + D => \skid_buffer[10]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); @@ -5678,7 +6487,7 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(11), + D => \skid_buffer[11]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); @@ -5686,7 +6495,7 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(12), + D => \skid_buffer[12]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); @@ -5694,7 +6503,7 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(13), + D => \skid_buffer[13]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); @@ -5702,7 +6511,7 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(14), + D => \skid_buffer[14]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[14]\, R => '0' ); @@ -5710,7 +6519,7 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(15), + D => \skid_buffer[15]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[15]\, R => '0' ); @@ -5718,7 +6527,7 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(16), + D => \skid_buffer[16]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[16]\, R => '0' ); @@ -5726,7 +6535,7 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(17), + D => \skid_buffer[17]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[17]\, R => '0' ); @@ -5734,7 +6543,7 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(18), + D => \skid_buffer[18]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[18]\, R => '0' ); @@ -5742,15 +6551,15 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(19), + D => \skid_buffer[19]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[19]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, - CE => \^aa_rready\, - D => aa_rmesg(1), + CE => '1', + D => skid_buffer(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); @@ -5758,7 +6567,7 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(20), + D => \skid_buffer[20]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[20]\, R => '0' ); @@ -5766,7 +6575,7 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(21), + D => \skid_buffer[21]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[21]\, R => '0' ); @@ -5774,7 +6583,7 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(22), + D => \skid_buffer[22]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[22]\, R => '0' ); @@ -5782,7 +6591,7 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(23), + D => \skid_buffer[23]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[23]\, R => '0' ); @@ -5790,7 +6599,7 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(24), + D => \skid_buffer[24]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[24]\, R => '0' ); @@ -5798,7 +6607,7 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(25), + D => \skid_buffer[25]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[25]\, R => '0' ); @@ -5806,7 +6615,7 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(26), + D => \skid_buffer[26]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[26]\, R => '0' ); @@ -5814,7 +6623,7 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(27), + D => \skid_buffer[27]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[27]\, R => '0' ); @@ -5822,7 +6631,7 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(28), + D => \skid_buffer[28]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[28]\, R => '0' ); @@ -5830,15 +6639,15 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(29), + D => \skid_buffer[29]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[29]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, - CE => \^aa_rready\, - D => aa_rmesg(2), + CE => '1', + D => skid_buffer(2), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); @@ -5846,7 +6655,7 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(30), + D => \skid_buffer[30]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[30]\, R => '0' ); @@ -5854,7 +6663,7 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(31), + D => \skid_buffer[31]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[31]\, R => '0' ); @@ -5862,7 +6671,7 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(32), + D => \skid_buffer[32]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[32]\, R => '0' ); @@ -5870,7 +6679,7 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(33), + D => \skid_buffer[33]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[33]\, R => '0' ); @@ -5878,7 +6687,7 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(34), + D => \skid_buffer[34]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[34]\, R => '0' ); @@ -5886,7 +6695,7 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(3), + D => \skid_buffer[3]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); @@ -5894,7 +6703,7 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(4), + D => \skid_buffer[4]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); @@ -5902,7 +6711,7 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(5), + D => \skid_buffer[5]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); @@ -5910,7 +6719,7 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(6), + D => \skid_buffer[6]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); @@ -5918,7 +6727,7 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(7), + D => \skid_buffer[7]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); @@ -5926,7 +6735,7 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(8), + D => \skid_buffer[8]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); @@ -5934,7 +6743,7 @@ s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^aa_rready\, - D => aa_rmesg(9), + D => \skid_buffer[9]_i_1_n_0\, Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); @@ -5945,37 +6754,37 @@ library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_crossbar_sasd is port ( - s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 ); Q : out STD_LOGIC_VECTOR ( 34 downto 0 ); \s_axi_rdata[31]\ : out STD_LOGIC_VECTOR ( 33 downto 0 ); - s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_arvalid : out STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_bready : out STD_LOGIC_VECTOR ( 8 downto 0 ); - s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); - s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_wvalid : out STD_LOGIC_VECTOR ( 8 downto 0 ); + s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_bready : out STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_awvalid : out STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_wvalid : out STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_arvalid : out STD_LOGIC_VECTOR ( 10 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); - m_axi_awvalid : out STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_rready : out STD_LOGIC_VECTOR ( 8 downto 0 ); - s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rready : out STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 21 downto 0 ); aresetn : in STD_LOGIC; aclk : in STD_LOGIC; + s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_arready : in STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_rvalid : in STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_rresp : in STD_LOGIC_VECTOR ( 17 downto 0 ); - m_axi_rdata : in STD_LOGIC_VECTOR ( 287 downto 0 ); - m_axi_bresp : in STD_LOGIC_VECTOR ( 17 downto 0 ); - m_axi_awready : in STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_wready : in STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_bvalid : in STD_LOGIC_VECTOR ( 8 downto 0 ); - s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awready : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_bresp : in STD_LOGIC_VECTOR ( 21 downto 0 ); + m_axi_rdata : in STD_LOGIC_VECTOR ( 351 downto 0 ); + m_axi_rvalid : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_arready : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_bvalid : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_wready : in STD_LOGIC_VECTOR ( 10 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; @@ -5983,24 +6792,22 @@ entity Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_crossbar_sasd is end Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_crossbar_sasd; architecture STRUCTURE of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_crossbar_sasd is - signal aa_awready : STD_LOGIC; - signal aa_bvalid : STD_LOGIC; signal aa_grant_rnw : STD_LOGIC; signal aa_rready : STD_LOGIC; - signal aa_rvalid : STD_LOGIC; - signal aa_wready : STD_LOGIC; - signal addr_arbiter_inst_n_10 : STD_LOGIC; - signal addr_arbiter_inst_n_108 : STD_LOGIC; + signal addr_arbiter_inst_n_115 : STD_LOGIC; + signal addr_arbiter_inst_n_116 : STD_LOGIC; signal addr_arbiter_inst_n_22 : STD_LOGIC; signal addr_arbiter_inst_n_23 : STD_LOGIC; signal addr_arbiter_inst_n_3 : STD_LOGIC; + signal addr_arbiter_inst_n_35 : STD_LOGIC; signal addr_arbiter_inst_n_4 : STD_LOGIC; + signal addr_arbiter_inst_n_47 : STD_LOGIC; + signal addr_arbiter_inst_n_48 : STD_LOGIC; signal addr_arbiter_inst_n_5 : STD_LOGIC; - signal addr_arbiter_inst_n_6 : STD_LOGIC; - signal addr_arbiter_inst_n_61 : STD_LOGIC; - signal addr_arbiter_inst_n_62 : STD_LOGIC; - signal addr_arbiter_inst_n_7 : STD_LOGIC; - signal addr_arbiter_inst_n_8 : STD_LOGIC; + signal addr_arbiter_inst_n_50 : STD_LOGIC; + signal addr_arbiter_inst_n_51 : STD_LOGIC; + signal addr_arbiter_inst_n_52 : STD_LOGIC; + signal addr_arbiter_inst_n_64 : STD_LOGIC; signal addr_arbiter_inst_n_9 : STD_LOGIC; signal aresetn_d : STD_LOGIC; signal \gen_decerr.decerr_slave_inst_n_2\ : STD_LOGIC; @@ -6008,102 +6815,117 @@ architecture STRUCTURE of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_crossbar_sasd i signal \gen_decerr.decerr_slave_inst_n_4\ : STD_LOGIC; signal \gen_decerr.decerr_slave_inst_n_5\ : STD_LOGIC; signal \gen_decerr.decerr_slave_inst_n_6\ : STD_LOGIC; + signal \gen_decerr.decerr_slave_inst_n_7\ : STD_LOGIC; + signal \gen_decerr.decerr_slave_inst_n_8\ : STD_LOGIC; signal m_atarget_enc : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal m_atarget_hot : STD_LOGIC_VECTOR ( 9 downto 0 ); - signal m_atarget_hot0 : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal m_atarget_hot : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal m_atarget_hot0 : STD_LOGIC_VECTOR ( 11 downto 0 ); signal m_ready_d : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal m_ready_d_0 : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal m_ready_d0 : STD_LOGIC_VECTOR ( 1 to 1 ); + signal m_ready_d0_0 : STD_LOGIC_VECTOR ( 1 to 1 ); + signal m_ready_d_1 : STD_LOGIC_VECTOR ( 2 downto 0 ); signal m_valid_i : STD_LOGIC; - signal mi_arready_mux : STD_LOGIC; - signal mi_awready_mux : STD_LOGIC; - signal mi_bvalid : STD_LOGIC_VECTOR ( 9 to 9 ); - signal mi_wready : STD_LOGIC_VECTOR ( 9 to 9 ); - signal p_4_in : STD_LOGIC; + signal mi_bvalid : STD_LOGIC_VECTOR ( 11 to 11 ); + signal mi_wready : STD_LOGIC_VECTOR ( 11 to 11 ); + signal p_1_in : STD_LOGIC; signal reg_slice_r_n_2 : STD_LOGIC; - signal reg_slice_r_n_3 : STD_LOGIC; - signal reg_slice_r_n_4 : STD_LOGIC; - signal reg_slice_r_n_5 : STD_LOGIC; - signal reg_slice_r_n_6 : STD_LOGIC; + signal reg_slice_r_n_37 : STD_LOGIC; + signal reg_slice_r_n_38 : STD_LOGIC; + signal reg_slice_r_n_39 : STD_LOGIC; + signal reg_slice_r_n_40 : STD_LOGIC; + signal reg_slice_r_n_41 : STD_LOGIC; + signal reg_slice_r_n_42 : STD_LOGIC; + signal reg_slice_r_n_43 : STD_LOGIC; + signal reg_slice_r_n_44 : STD_LOGIC; + signal reg_slice_r_n_45 : STD_LOGIC; + signal reg_slice_r_n_46 : STD_LOGIC; + signal reg_slice_r_n_47 : STD_LOGIC; signal reset : STD_LOGIC; - signal \s_axi_bresp[0]_INST_0_i_1_n_0\ : STD_LOGIC; - signal \s_axi_bresp[0]_INST_0_i_2_n_0\ : STD_LOGIC; signal \s_axi_bresp[0]_INST_0_i_3_n_0\ : STD_LOGIC; signal \s_axi_bresp[0]_INST_0_i_4_n_0\ : STD_LOGIC; + signal \s_axi_bresp[0]_INST_0_i_5_n_0\ : STD_LOGIC; + signal \s_axi_bresp[0]_INST_0_i_6_n_0\ : STD_LOGIC; + signal \s_axi_bresp[0]_INST_0_i_7_n_0\ : STD_LOGIC; signal \s_axi_bresp[1]_INST_0_i_3_n_0\ : STD_LOGIC; signal \s_axi_bresp[1]_INST_0_i_4_n_0\ : STD_LOGIC; signal \s_axi_bresp[1]_INST_0_i_5_n_0\ : STD_LOGIC; - signal \s_axi_bresp[1]_INST_0_i_8_n_0\ : STD_LOGIC; + signal \s_axi_bresp[1]_INST_0_i_6_n_0\ : STD_LOGIC; + signal \s_axi_bresp[1]_INST_0_i_7_n_0\ : STD_LOGIC; + signal \s_axi_wready[0]_INST_0_i_5_n_0\ : STD_LOGIC; signal splitter_ar_n_0 : STD_LOGIC; + signal splitter_ar_n_1 : STD_LOGIC; + signal splitter_ar_n_2 : STD_LOGIC; signal splitter_aw_n_0 : STD_LOGIC; signal splitter_aw_n_1 : STD_LOGIC; + signal splitter_aw_n_10 : STD_LOGIC; + signal splitter_aw_n_11 : STD_LOGIC; + signal splitter_aw_n_12 : STD_LOGIC; signal splitter_aw_n_2 : STD_LOGIC; signal splitter_aw_n_3 : STD_LOGIC; + signal splitter_aw_n_4 : STD_LOGIC; + signal splitter_aw_n_5 : STD_LOGIC; + signal splitter_aw_n_6 : STD_LOGIC; + signal splitter_aw_n_7 : STD_LOGIC; + signal splitter_aw_n_8 : STD_LOGIC; + signal splitter_aw_n_9 : STD_LOGIC; signal sr_rvalid : STD_LOGIC; begin addr_arbiter_inst: entity work.Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_addr_arbiter_sasd port map ( - D(9 downto 0) => m_atarget_hot0(9 downto 0), - E(0) => addr_arbiter_inst_n_6, - Q(34 downto 0) => Q(34 downto 0), - SR(0) => reset, - aa_awready => aa_awready, - aa_bvalid => aa_bvalid, + D(11 downto 0) => m_atarget_hot0(11 downto 0), + E(0) => p_1_in, + Q(11 downto 0) => m_atarget_hot(11 downto 0), aa_grant_rnw => aa_grant_rnw, - aa_rvalid => aa_rvalid, - aa_wready => aa_wready, aclk => aclk, aresetn_d => aresetn_d, - \gen_axilite.s_axi_arready_i_reg\ => \gen_decerr.decerr_slave_inst_n_2\, - \gen_axilite.s_axi_awready_i_reg\ => \gen_decerr.decerr_slave_inst_n_5\, - \gen_axilite.s_axi_awready_i_reg_0\ => \gen_decerr.decerr_slave_inst_n_4\, - \gen_axilite.s_axi_bvalid_i_reg\ => addr_arbiter_inst_n_8, - \gen_axilite.s_axi_bvalid_i_reg_0\ => addr_arbiter_inst_n_108, - \gen_axilite.s_axi_bvalid_i_reg_1\ => \gen_decerr.decerr_slave_inst_n_6\, - \gen_axilite.s_axi_rvalid_i_reg\ => \gen_decerr.decerr_slave_inst_n_3\, + \gen_axilite.s_axi_bvalid_i_reg\ => addr_arbiter_inst_n_23, + \gen_axilite.s_axi_bvalid_i_reg_0\ => addr_arbiter_inst_n_35, + \gen_axilite.s_axi_bvalid_i_reg_1\ => addr_arbiter_inst_n_47, + \gen_axilite.s_axi_bvalid_i_reg_2\ => addr_arbiter_inst_n_116, + \gen_axilite.s_axi_rvalid_i_reg\ => addr_arbiter_inst_n_64, m_atarget_enc(3 downto 0) => m_atarget_enc(3 downto 0), - \m_atarget_enc_reg[0]\ => addr_arbiter_inst_n_3, - \m_atarget_enc_reg[2]\(1) => addr_arbiter_inst_n_22, - \m_atarget_enc_reg[2]\(0) => addr_arbiter_inst_n_23, - \m_atarget_enc_reg[2]_0\ => splitter_aw_n_1, - \m_atarget_enc_reg[2]_1\ => splitter_aw_n_0, - \m_atarget_enc_reg[2]_2\ => splitter_aw_n_3, - \m_atarget_enc_reg[2]_3\ => splitter_aw_n_2, - \m_atarget_enc_reg[3]\ => addr_arbiter_inst_n_4, - \m_atarget_hot_reg[9]\(9 downto 0) => m_atarget_hot(9 downto 0), - m_axi_arready(6 downto 4) => m_axi_arready(8 downto 6), - m_axi_arready(3 downto 1) => m_axi_arready(4 downto 2), - m_axi_arready(0) => m_axi_arready(0), - m_axi_arvalid(8 downto 0) => m_axi_arvalid(8 downto 0), - m_axi_awready(6 downto 4) => m_axi_awready(8 downto 6), - m_axi_awready(3 downto 1) => m_axi_awready(4 downto 2), - m_axi_awready(0) => m_axi_awready(0), - m_axi_awvalid(8 downto 0) => m_axi_awvalid(8 downto 0), - m_axi_bready(8 downto 0) => m_axi_bready(8 downto 0), - m_axi_bvalid(6 downto 4) => m_axi_bvalid(8 downto 6), - m_axi_bvalid(3 downto 1) => m_axi_bvalid(4 downto 2), - m_axi_bvalid(0) => m_axi_bvalid(0), - m_axi_rvalid(6 downto 4) => m_axi_rvalid(8 downto 6), - m_axi_rvalid(3 downto 1) => m_axi_rvalid(4 downto 2), - m_axi_rvalid(0) => m_axi_rvalid(0), - m_axi_wready(6 downto 4) => m_axi_wready(8 downto 6), - m_axi_wready(3 downto 1) => m_axi_wready(4 downto 2), - m_axi_wready(0) => m_axi_wready(0), - m_axi_wvalid(8 downto 0) => m_axi_wvalid(8 downto 0), - m_ready_d(1 downto 0) => m_ready_d(1 downto 0), - m_ready_d_0(2 downto 0) => m_ready_d_0(2 downto 0), - \m_ready_d_reg[0]\ => addr_arbiter_inst_n_7, - \m_ready_d_reg[0]_0\ => addr_arbiter_inst_n_10, - \m_ready_d_reg[0]_1\ => splitter_ar_n_0, - \m_ready_d_reg[1]\ => addr_arbiter_inst_n_5, - \m_ready_d_reg[1]_0\ => addr_arbiter_inst_n_9, - \m_ready_d_reg[1]_1\ => addr_arbiter_inst_n_61, - \m_ready_d_reg[1]_2\ => addr_arbiter_inst_n_62, + \m_atarget_enc_reg[0]\ => addr_arbiter_inst_n_4, + \m_atarget_enc_reg[1]\ => addr_arbiter_inst_n_3, + \m_atarget_enc_reg[2]\ => addr_arbiter_inst_n_115, + \m_atarget_enc_reg[2]_0\ => \gen_decerr.decerr_slave_inst_n_5\, + \m_atarget_enc_reg[2]_1\ => splitter_aw_n_3, + \m_atarget_enc_reg[2]_2\ => splitter_aw_n_2, + \m_atarget_enc_reg[2]_3\ => \gen_decerr.decerr_slave_inst_n_8\, + \m_atarget_enc_reg[2]_4\ => \gen_decerr.decerr_slave_inst_n_3\, + \m_atarget_enc_reg[2]_5\ => splitter_aw_n_10, + \m_atarget_enc_reg[2]_6\ => splitter_ar_n_2, + \m_atarget_enc_reg[2]_7\ => \gen_decerr.decerr_slave_inst_n_6\, + \m_atarget_enc_reg[2]_8\ => splitter_ar_n_1, + \m_atarget_enc_reg[3]\ => addr_arbiter_inst_n_5, + \m_atarget_enc_reg[3]_0\ => \gen_decerr.decerr_slave_inst_n_7\, + \m_atarget_enc_reg[3]_1\ => \s_axi_wready[0]_INST_0_i_5_n_0\, + \m_atarget_enc_reg[3]_2\ => splitter_aw_n_7, + \m_atarget_enc_reg[3]_3\ => splitter_aw_n_12, + \m_atarget_enc_reg[3]_4\ => splitter_ar_n_0, + \m_axi_arprot[2]\(34 downto 0) => Q(34 downto 0), + m_axi_arvalid(10 downto 0) => m_axi_arvalid(10 downto 0), + m_axi_awready(4) => m_axi_awready(10), + m_axi_awready(3 downto 2) => m_axi_awready(5 downto 4), + m_axi_awready(1 downto 0) => m_axi_awready(1 downto 0), + m_axi_awvalid(10 downto 0) => m_axi_awvalid(10 downto 0), + m_axi_bready(10 downto 0) => m_axi_bready(10 downto 0), + m_axi_wvalid(10 downto 0) => m_axi_wvalid(10 downto 0), + \m_payload_i_reg[0]\ => reg_slice_r_n_2, + \m_payload_i_reg[0]_0\(0) => reg_slice_r_n_37, + m_ready_d(2 downto 0) => m_ready_d_1(2 downto 0), + m_ready_d0(0) => m_ready_d0_0(1), + m_ready_d0_0(0) => m_ready_d0(1), + m_ready_d_1(1 downto 0) => m_ready_d(1 downto 0), + \m_ready_d_reg[0]\ => addr_arbiter_inst_n_50, + \m_ready_d_reg[0]_0\ => addr_arbiter_inst_n_52, + \m_ready_d_reg[0]_1\ => \gen_decerr.decerr_slave_inst_n_2\, + \m_ready_d_reg[1]\ => addr_arbiter_inst_n_22, + \m_ready_d_reg[1]_0\ => addr_arbiter_inst_n_51, + \m_ready_d_reg[2]\ => addr_arbiter_inst_n_9, m_valid_i => m_valid_i, - mi_arready_mux => mi_arready_mux, - mi_awready_mux => mi_awready_mux, - mi_bvalid(0) => mi_bvalid(9), - mi_wready(0) => mi_wready(9), - p_4_in => p_4_in, + mi_bvalid(0) => mi_bvalid(11), + mi_wready(0) => mi_wready(11), + reset => reset, s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arready(0) => s_axi_arready(0), @@ -6118,6 +6940,7 @@ addr_arbiter_inst: entity work.Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_addr_arbit s_axi_rvalid(0) => s_axi_rvalid(0), s_axi_wready(0) => s_axi_wready(0), s_axi_wvalid(0) => s_axi_wvalid(0), + s_ready_i_reg => addr_arbiter_inst_n_48, sr_rvalid => sr_rvalid ); aresetn_d_reg: unisim.vcomponents.FDRE @@ -6133,42 +6956,54 @@ aresetn_d_reg: unisim.vcomponents.FDRE ); \gen_decerr.decerr_slave_inst\: entity work.Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_decerr_slave port map ( - Q(0) => m_atarget_hot(9), - SR(0) => reset, + Q(0) => m_atarget_hot(11), aa_rready => aa_rready, aclk => aclk, aresetn_d => aresetn_d, - \gen_axilite.s_axi_bvalid_i_reg_0\ => addr_arbiter_inst_n_108, - \gen_no_arbiter.grant_rnw_reg\ => addr_arbiter_inst_n_8, - \gen_no_arbiter.grant_rnw_reg_0\ => addr_arbiter_inst_n_9, - \gen_no_arbiter.grant_rnw_reg_1\ => addr_arbiter_inst_n_10, - \gen_no_arbiter.m_valid_i_reg\ => addr_arbiter_inst_n_5, - \gen_no_arbiter.m_valid_i_reg_0\ => addr_arbiter_inst_n_7, - m_atarget_enc(1 downto 0) => m_atarget_enc(3 downto 2), - m_axi_arready(1) => m_axi_arready(5), - m_axi_arready(0) => m_axi_arready(1), - m_axi_awready(1) => m_axi_awready(5), - m_axi_awready(0) => m_axi_awready(1), - m_axi_bvalid(1) => m_axi_bvalid(5), - m_axi_bvalid(0) => m_axi_bvalid(1), - m_axi_rvalid(1) => m_axi_rvalid(5), - m_axi_rvalid(0) => m_axi_rvalid(1), - m_axi_wready(1) => m_axi_wready(5), - m_axi_wready(0) => m_axi_wready(1), - \m_ready_d_reg[0]\ => \gen_decerr.decerr_slave_inst_n_6\, - \m_ready_d_reg[1]\ => \gen_decerr.decerr_slave_inst_n_2\, - \m_ready_d_reg[1]_0\ => \gen_decerr.decerr_slave_inst_n_5\, - \m_ready_d_reg[2]\ => \gen_decerr.decerr_slave_inst_n_4\, - m_valid_i_reg => \gen_decerr.decerr_slave_inst_n_3\, - mi_bvalid(0) => mi_bvalid(9), - mi_wready(0) => mi_wready(9), - p_4_in => p_4_in + \gen_no_arbiter.grant_rnw_reg\ => addr_arbiter_inst_n_23, + \gen_no_arbiter.m_valid_i_reg\ => addr_arbiter_inst_n_48, + m_atarget_enc(3 downto 0) => m_atarget_enc(3 downto 0), + \m_atarget_enc_reg[0]\ => reg_slice_r_n_45, + \m_atarget_enc_reg[1]\ => splitter_aw_n_11, + \m_atarget_enc_reg[2]\ => splitter_aw_n_0, + \m_atarget_enc_reg[2]_0\ => splitter_aw_n_5, + \m_atarget_enc_reg[2]_1\ => splitter_aw_n_6, + \m_atarget_enc_reg[2]_2\ => reg_slice_r_n_44, + \m_atarget_enc_reg[2]_3\ => splitter_aw_n_9, + \m_atarget_enc_reg[2]_4\ => splitter_aw_n_8, + \m_atarget_enc_reg[3]\ => reg_slice_r_n_43, + \m_atarget_enc_reg[3]_0\ => reg_slice_r_n_46, + \m_atarget_hot_reg[11]\ => addr_arbiter_inst_n_116, + m_axi_arready(1) => m_axi_arready(7), + m_axi_arready(0) => m_axi_arready(3), + m_axi_awready(1) => m_axi_awready(7), + m_axi_awready(0) => m_axi_awready(3), + m_axi_bvalid(1) => m_axi_bvalid(7), + m_axi_bvalid(0) => m_axi_bvalid(3), + m_axi_rvalid(1) => m_axi_rvalid(7), + m_axi_rvalid(0) => m_axi_rvalid(3), + m_axi_wready(2 downto 1) => m_axi_wready(8 downto 7), + m_axi_wready(0) => m_axi_wready(3), + m_ready_d(0) => m_ready_d_1(0), + \m_ready_d_reg[1]\ => \gen_decerr.decerr_slave_inst_n_5\, + \m_ready_d_reg[1]_0\ => \gen_decerr.decerr_slave_inst_n_6\, + \m_ready_d_reg[1]_1\ => addr_arbiter_inst_n_64, + \m_ready_d_reg[1]_2\ => addr_arbiter_inst_n_47, + \m_ready_d_reg[2]\ => \gen_decerr.decerr_slave_inst_n_2\, + \m_ready_d_reg[2]_0\ => \gen_decerr.decerr_slave_inst_n_3\, + \m_ready_d_reg[2]_1\ => \gen_decerr.decerr_slave_inst_n_7\, + \m_ready_d_reg[2]_2\ => addr_arbiter_inst_n_35, + mi_bvalid(0) => mi_bvalid(11), + mi_wready(0) => mi_wready(11), + reset => reset, + \s_axi_wready[0]\ => \gen_decerr.decerr_slave_inst_n_8\, + s_ready_i_reg => \gen_decerr.decerr_slave_inst_n_4\ ); \m_atarget_enc_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', - D => addr_arbiter_inst_n_3, + D => addr_arbiter_inst_n_4, Q => m_atarget_enc(0), R => reset ); @@ -6176,23 +7011,23 @@ aresetn_d_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', - D => addr_arbiter_inst_n_23, + D => addr_arbiter_inst_n_3, Q => m_atarget_enc(1), - R => '0' + R => reset ); \m_atarget_enc_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', - D => addr_arbiter_inst_n_22, + D => addr_arbiter_inst_n_115, Q => m_atarget_enc(2), - R => '0' + R => reset ); \m_atarget_enc_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', - D => addr_arbiter_inst_n_4, + D => addr_arbiter_inst_n_5, Q => m_atarget_enc(3), R => reset ); @@ -6204,6 +7039,22 @@ aresetn_d_reg: unisim.vcomponents.FDRE Q => m_atarget_hot(0), R => reset ); +\m_atarget_hot_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => m_atarget_hot0(10), + Q => m_atarget_hot(10), + R => reset + ); +\m_atarget_hot_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => m_atarget_hot0(11), + Q => m_atarget_hot(11), + R => reset + ); \m_atarget_hot_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, @@ -6278,198 +7129,262 @@ aresetn_d_reg: unisim.vcomponents.FDRE ); reg_slice_r: entity work.Arty_Z7_20_xbar_0_axi_register_slice_v2_1_11_axic_register_slice port map ( - E(0) => addr_arbiter_inst_n_6, - Q(8 downto 0) => m_atarget_hot(8 downto 0), - SR(0) => reset, + E(0) => p_1_in, + Q(34 downto 1) => \s_axi_rdata[31]\(33 downto 0), + Q(0) => reg_slice_r_n_37, aa_grant_rnw => aa_grant_rnw, aa_rready => aa_rready, - aa_rvalid => aa_rvalid, aclk => aclk, + \gen_no_arbiter.m_grant_hot_i_reg[0]\ => reg_slice_r_n_2, m_atarget_enc(3 downto 0) => m_atarget_enc(3 downto 0), - m_axi_rdata(287 downto 0) => m_axi_rdata(287 downto 0), - m_axi_rready(8 downto 0) => m_axi_rready(8 downto 0), - m_axi_rresp(17 downto 0) => m_axi_rresp(17 downto 0), + \m_atarget_enc_reg[0]\ => splitter_aw_n_1, + \m_atarget_enc_reg[1]\ => splitter_aw_n_4, + \m_atarget_hot_reg[10]\(10 downto 0) => m_atarget_hot(10 downto 0), + m_axi_rdata(351 downto 0) => m_axi_rdata(351 downto 0), + m_axi_rready(10 downto 0) => m_axi_rready(10 downto 0), + m_axi_rresp(21 downto 0) => m_axi_rresp(21 downto 0), + m_axi_rvalid(8 downto 6) => m_axi_rvalid(10 downto 8), + m_axi_rvalid(5 downto 3) => m_axi_rvalid(6 downto 4), + m_axi_rvalid(2 downto 0) => m_axi_rvalid(2 downto 0), + \m_payload_i_reg[1]_0\ => reg_slice_r_n_41, + \m_payload_i_reg[2]_0\ => reg_slice_r_n_39, + \m_payload_i_reg[2]_1\ => reg_slice_r_n_40, m_ready_d(0) => m_ready_d(0), - \m_ready_d_reg[1]\ => reg_slice_r_n_2, + \m_ready_d_reg[2]\ => reg_slice_r_n_45, m_valid_i => m_valid_i, - \s_axi_rdata[31]\(33 downto 0) => \s_axi_rdata[31]\(33 downto 0), + reset => reset, s_axi_rready(0) => s_axi_rready(0), - \skid_buffer_reg[1]_0\ => reg_slice_r_n_3, - \skid_buffer_reg[1]_1\ => reg_slice_r_n_4, - \skid_buffer_reg[1]_2\ => reg_slice_r_n_5, - \skid_buffer_reg[1]_3\ => reg_slice_r_n_6, + s_ready_i_reg_0 => reg_slice_r_n_43, + s_ready_i_reg_1 => reg_slice_r_n_44, + s_ready_i_reg_2 => reg_slice_r_n_46, + s_ready_i_reg_3 => reg_slice_r_n_47, + s_ready_i_reg_4 => \gen_decerr.decerr_slave_inst_n_4\, + \skid_buffer_reg[30]_0\ => reg_slice_r_n_38, + \skid_buffer_reg[9]_0\ => reg_slice_r_n_42, sr_rvalid => sr_rvalid ); \s_axi_bresp[0]_INST_0\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFFFFFFFFFF4F44" ) port map ( - I0 => reg_slice_r_n_3, - I1 => m_axi_bresp(2), - I2 => reg_slice_r_n_4, - I3 => m_axi_bresp(4), - I4 => \s_axi_bresp[0]_INST_0_i_1_n_0\, - I5 => \s_axi_bresp[0]_INST_0_i_2_n_0\, + I0 => reg_slice_r_n_38, + I1 => m_axi_bresp(18), + I2 => reg_slice_r_n_40, + I3 => m_axi_bresp(14), + I4 => \s_axi_bresp[0]_INST_0_i_3_n_0\, + I5 => \s_axi_bresp[0]_INST_0_i_4_n_0\, O => s_axi_bresp(0) ); -\s_axi_bresp[0]_INST_0_i_1\: unisim.vcomponents.LUT6 +\s_axi_bresp[0]_INST_0_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"AABAAAABAABAAAAA" + INIT => X"30000C0830000008" ) port map ( - I0 => \s_axi_bresp[0]_INST_0_i_3_n_0\, - I1 => m_atarget_enc(1), - I2 => m_atarget_enc(0), - I3 => m_atarget_enc(2), - I4 => m_atarget_enc(3), - I5 => m_axi_bresp(0), - O => \s_axi_bresp[0]_INST_0_i_1_n_0\ + I0 => m_axi_bresp(8), + I1 => m_atarget_enc(2), + I2 => m_atarget_enc(3), + I3 => m_atarget_enc(0), + I4 => m_atarget_enc(1), + I5 => m_axi_bresp(10), + O => \s_axi_bresp[0]_INST_0_i_3_n_0\ ); -\s_axi_bresp[0]_INST_0_i_2\: unisim.vcomponents.LUT5 +\s_axi_bresp[0]_INST_0_i_4\: unisim.vcomponents.LUT5 generic map( - INIT => X"FFFFF888" + INIT => X"FEFEFFFE" ) port map ( - I0 => reg_slice_r_n_5, - I1 => m_axi_bresp(8), - I2 => reg_slice_r_n_6, - I3 => m_axi_bresp(6), - I4 => \s_axi_bresp[0]_INST_0_i_4_n_0\, - O => \s_axi_bresp[0]_INST_0_i_2_n_0\ + I0 => \s_axi_bresp[0]_INST_0_i_5_n_0\, + I1 => \s_axi_bresp[0]_INST_0_i_6_n_0\, + I2 => \s_axi_bresp[0]_INST_0_i_7_n_0\, + I3 => m_axi_bresp(12), + I4 => reg_slice_r_n_39, + O => \s_axi_bresp[0]_INST_0_i_4_n_0\ ); -\s_axi_bresp[0]_INST_0_i_3\: unisim.vcomponents.LUT6 +\s_axi_bresp[0]_INST_0_i_5\: unisim.vcomponents.LUT6 generic map( - INIT => X"0000A000000C0000" + INIT => X"00000C8000000080" ) port map ( - I0 => m_axi_bresp(14), - I1 => m_axi_bresp(16), + I0 => m_axi_bresp(6), + I1 => m_atarget_enc(1), I2 => m_atarget_enc(0), - I3 => m_atarget_enc(2), - I4 => m_atarget_enc(3), - I5 => m_atarget_enc(1), - O => \s_axi_bresp[0]_INST_0_i_3_n_0\ + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_bresp(20), + O => \s_axi_bresp[0]_INST_0_i_5_n_0\ ); -\s_axi_bresp[0]_INST_0_i_4\: unisim.vcomponents.LUT6 +\s_axi_bresp[0]_INST_0_i_6\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"0000020300000200" ) port map ( - I0 => m_axi_bresp(10), - I1 => m_axi_bresp(12), - I2 => m_atarget_enc(3), - I3 => m_atarget_enc(0), - I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), - O => \s_axi_bresp[0]_INST_0_i_4_n_0\ + I0 => m_axi_bresp(16), + I1 => m_atarget_enc(1), + I2 => m_atarget_enc(0), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_bresp(0), + O => \s_axi_bresp[0]_INST_0_i_6_n_0\ + ); +\s_axi_bresp[0]_INST_0_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000002C00000020" + ) + port map ( + I0 => m_axi_bresp(4), + I1 => m_atarget_enc(0), + I2 => m_atarget_enc(1), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_bresp(2), + O => \s_axi_bresp[0]_INST_0_i_7_n_0\ ); \s_axi_bresp[1]_INST_0\: unisim.vcomponents.LUT6 generic map( - INIT => X"FFFFFFFFFFFFF888" + INIT => X"FFFFFFFFFFFF4F44" ) port map ( - I0 => reg_slice_r_n_3, - I1 => m_axi_bresp(3), - I2 => reg_slice_r_n_4, - I3 => m_axi_bresp(5), + I0 => reg_slice_r_n_41, + I1 => m_axi_bresp(1), + I2 => reg_slice_r_n_42, + I3 => m_axi_bresp(17), I4 => \s_axi_bresp[1]_INST_0_i_3_n_0\, I5 => \s_axi_bresp[1]_INST_0_i_4_n_0\, O => s_axi_bresp(1) ); \s_axi_bresp[1]_INST_0_i_3\: unisim.vcomponents.LUT6 generic map( - INIT => X"AABAAAABAABAAAAA" + INIT => X"30000C0830000008" ) port map ( - I0 => \s_axi_bresp[1]_INST_0_i_5_n_0\, - I1 => m_atarget_enc(1), - I2 => m_atarget_enc(0), - I3 => m_atarget_enc(2), - I4 => m_atarget_enc(3), - I5 => m_axi_bresp(1), + I0 => m_axi_bresp(9), + I1 => m_atarget_enc(2), + I2 => m_atarget_enc(3), + I3 => m_atarget_enc(0), + I4 => m_atarget_enc(1), + I5 => m_axi_bresp(11), O => \s_axi_bresp[1]_INST_0_i_3_n_0\ ); \s_axi_bresp[1]_INST_0_i_4\: unisim.vcomponents.LUT5 generic map( - INIT => X"FFFFF888" + INIT => X"FEFEFFFE" ) port map ( - I0 => reg_slice_r_n_5, - I1 => m_axi_bresp(9), - I2 => reg_slice_r_n_6, - I3 => m_axi_bresp(7), - I4 => \s_axi_bresp[1]_INST_0_i_8_n_0\, + I0 => \s_axi_bresp[1]_INST_0_i_5_n_0\, + I1 => \s_axi_bresp[1]_INST_0_i_6_n_0\, + I2 => \s_axi_bresp[1]_INST_0_i_7_n_0\, + I3 => m_axi_bresp(19), + I4 => reg_slice_r_n_38, O => \s_axi_bresp[1]_INST_0_i_4_n_0\ ); \s_axi_bresp[1]_INST_0_i_5\: unisim.vcomponents.LUT6 generic map( - INIT => X"0000A000000C0000" + INIT => X"00000C8000000080" ) port map ( - I0 => m_axi_bresp(15), - I1 => m_axi_bresp(17), + I0 => m_axi_bresp(7), + I1 => m_atarget_enc(1), I2 => m_atarget_enc(0), - I3 => m_atarget_enc(2), - I4 => m_atarget_enc(3), - I5 => m_atarget_enc(1), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_bresp(21), O => \s_axi_bresp[1]_INST_0_i_5_n_0\ ); -\s_axi_bresp[1]_INST_0_i_8\: unisim.vcomponents.LUT6 +\s_axi_bresp[1]_INST_0_i_6\: unisim.vcomponents.LUT6 generic map( - INIT => X"000C0A0000000000" + INIT => X"08000C0008000000" ) port map ( - I0 => m_axi_bresp(11), - I1 => m_axi_bresp(13), + I0 => m_axi_bresp(15), + I1 => m_atarget_enc(2), I2 => m_atarget_enc(3), - I3 => m_atarget_enc(0), - I4 => m_atarget_enc(1), - I5 => m_atarget_enc(2), - O => \s_axi_bresp[1]_INST_0_i_8_n_0\ + I3 => m_atarget_enc(1), + I4 => m_atarget_enc(0), + I5 => m_axi_bresp(13), + O => \s_axi_bresp[1]_INST_0_i_6_n_0\ + ); +\s_axi_bresp[1]_INST_0_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000002C00000020" + ) + port map ( + I0 => m_axi_bresp(3), + I1 => m_atarget_enc(1), + I2 => m_atarget_enc(0), + I3 => m_atarget_enc(3), + I4 => m_atarget_enc(2), + I5 => m_axi_bresp(5), + O => \s_axi_bresp[1]_INST_0_i_7_n_0\ + ); +\s_axi_wready[0]_INST_0_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FCDCFCDFFFDCFFDF" + ) + port map ( + I0 => m_axi_wready(8), + I1 => reg_slice_r_n_47, + I2 => m_atarget_enc(3), + I3 => m_atarget_enc(2), + I4 => m_axi_wready(0), + I5 => m_axi_wready(4), + O => \s_axi_wready[0]_INST_0_i_5_n_0\ ); splitter_ar: entity work.\Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_splitter__parameterized0\ port map ( + Q(0) => reg_slice_r_n_37, aclk => aclk, aresetn_d => aresetn_d, - \gen_no_arbiter.m_valid_i_reg\ => splitter_ar_n_0, - \gen_no_arbiter.m_valid_i_reg_0\ => addr_arbiter_inst_n_5, - \gen_no_arbiter.m_valid_i_reg_1\ => addr_arbiter_inst_n_7, - m_atarget_enc(0) => m_atarget_enc(0), - \m_atarget_enc_reg[2]\ => addr_arbiter_inst_n_62, - \m_atarget_enc_reg[2]_0\ => addr_arbiter_inst_n_61, - \m_payload_i_reg[0]\ => reg_slice_r_n_2, + aresetn_d_reg => addr_arbiter_inst_n_50, + \gen_no_arbiter.grant_rnw_reg\ => addr_arbiter_inst_n_52, + m_atarget_enc(1 downto 0) => m_atarget_enc(3 downto 2), + \m_atarget_enc_reg[0]\ => splitter_aw_n_1, + \m_atarget_enc_reg[0]_0\ => reg_slice_r_n_47, + \m_atarget_enc_reg[1]\ => splitter_aw_n_4, + m_axi_arready(8 downto 6) => m_axi_arready(10 downto 8), + m_axi_arready(5 downto 3) => m_axi_arready(6 downto 4), + m_axi_arready(2 downto 0) => m_axi_arready(2 downto 0), m_ready_d(1 downto 0) => m_ready_d(1 downto 0), - mi_arready_mux => mi_arready_mux + m_ready_d0(0) => m_ready_d0_0(1), + \m_ready_d_reg[0]_0\ => addr_arbiter_inst_n_51, + \m_ready_d_reg[1]_0\ => splitter_ar_n_0, + \m_ready_d_reg[1]_1\ => splitter_ar_n_1, + \m_ready_d_reg[1]_2\ => splitter_ar_n_2, + s_axi_rready(0) => s_axi_rready(0), + sr_rvalid => sr_rvalid ); splitter_aw: entity work.Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_splitter port map ( - aa_awready => aa_awready, - aa_bvalid => aa_bvalid, - aa_grant_rnw => aa_grant_rnw, - aa_wready => aa_wready, aclk => aclk, aresetn_d => aresetn_d, - \gen_no_arbiter.grant_rnw_reg\ => addr_arbiter_inst_n_9, - \gen_no_arbiter.grant_rnw_reg_0\ => addr_arbiter_inst_n_10, - \gen_no_arbiter.m_valid_i_reg\ => splitter_aw_n_0, - \gen_no_arbiter.m_valid_i_reg_0\ => splitter_aw_n_1, - \gen_no_arbiter.m_valid_i_reg_1\ => splitter_aw_n_2, - \gen_no_arbiter.m_valid_i_reg_2\ => splitter_aw_n_3, - m_atarget_enc(1 downto 0) => m_atarget_enc(3 downto 2), - m_axi_bvalid(3) => m_axi_bvalid(6), - m_axi_bvalid(2) => m_axi_bvalid(4), - m_axi_bvalid(1) => m_axi_bvalid(2), - m_axi_bvalid(0) => m_axi_bvalid(0), - m_axi_wready(3) => m_axi_wready(6), - m_axi_wready(2) => m_axi_wready(4), - m_axi_wready(1) => m_axi_wready(2), - m_axi_wready(0) => m_axi_wready(0), - m_ready_d(2 downto 0) => m_ready_d_0(2 downto 0), - m_valid_i => m_valid_i, - mi_awready_mux => mi_awready_mux, - s_axi_bready(0) => s_axi_bready(0), - s_axi_wvalid(0) => s_axi_wvalid(0) + \gen_no_arbiter.m_valid_i_reg\ => addr_arbiter_inst_n_22, + m_atarget_enc(3 downto 0) => m_atarget_enc(3 downto 0), + \m_atarget_enc_reg[0]\ => reg_slice_r_n_47, + m_axi_awready(3 downto 2) => m_axi_awready(9 downto 8), + m_axi_awready(1) => m_axi_awready(6), + m_axi_awready(0) => m_axi_awready(2), + m_axi_bvalid(8 downto 6) => m_axi_bvalid(10 downto 8), + m_axi_bvalid(5 downto 3) => m_axi_bvalid(6 downto 4), + m_axi_bvalid(2 downto 0) => m_axi_bvalid(2 downto 0), + m_axi_wready(9 downto 8) => m_axi_wready(10 downto 9), + m_axi_wready(7 downto 0) => m_axi_wready(7 downto 0), + m_ready_d(2 downto 0) => m_ready_d_1(2 downto 0), + m_ready_d0(0) => m_ready_d0(1), + \m_ready_d_reg[0]_0\ => \gen_decerr.decerr_slave_inst_n_2\, + \m_ready_d_reg[2]_0\ => splitter_aw_n_0, + \m_ready_d_reg[2]_1\ => splitter_aw_n_1, + \m_ready_d_reg[2]_10\ => splitter_aw_n_10, + \m_ready_d_reg[2]_11\ => splitter_aw_n_11, + \m_ready_d_reg[2]_12\ => splitter_aw_n_12, + \m_ready_d_reg[2]_13\ => addr_arbiter_inst_n_9, + \m_ready_d_reg[2]_2\ => splitter_aw_n_2, + \m_ready_d_reg[2]_3\ => splitter_aw_n_3, + \m_ready_d_reg[2]_4\ => splitter_aw_n_4, + \m_ready_d_reg[2]_5\ => splitter_aw_n_5, + \m_ready_d_reg[2]_6\ => splitter_aw_n_6, + \m_ready_d_reg[2]_7\ => splitter_aw_n_7, + \m_ready_d_reg[2]_8\ => splitter_aw_n_8, + \m_ready_d_reg[2]_9\ => splitter_aw_n_9 ); end STRUCTURE; library IEEE; @@ -6523,51 +7438,51 @@ entity Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar is s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_awid : out STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_awaddr : out STD_LOGIC_VECTOR ( 287 downto 0 ); - m_axi_awlen : out STD_LOGIC_VECTOR ( 71 downto 0 ); - m_axi_awsize : out STD_LOGIC_VECTOR ( 26 downto 0 ); - m_axi_awburst : out STD_LOGIC_VECTOR ( 17 downto 0 ); - m_axi_awlock : out STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_awcache : out STD_LOGIC_VECTOR ( 35 downto 0 ); - m_axi_awprot : out STD_LOGIC_VECTOR ( 26 downto 0 ); - m_axi_awregion : out STD_LOGIC_VECTOR ( 35 downto 0 ); - m_axi_awqos : out STD_LOGIC_VECTOR ( 35 downto 0 ); - m_axi_awuser : out STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_awvalid : out STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_awready : in STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_wid : out STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_wdata : out STD_LOGIC_VECTOR ( 287 downto 0 ); - m_axi_wstrb : out STD_LOGIC_VECTOR ( 35 downto 0 ); - m_axi_wlast : out STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_wuser : out STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_wvalid : out STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_wready : in STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_bid : in STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_bresp : in STD_LOGIC_VECTOR ( 17 downto 0 ); - m_axi_buser : in STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_bvalid : in STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_bready : out STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_arid : out STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_araddr : out STD_LOGIC_VECTOR ( 287 downto 0 ); - m_axi_arlen : out STD_LOGIC_VECTOR ( 71 downto 0 ); - m_axi_arsize : out STD_LOGIC_VECTOR ( 26 downto 0 ); - m_axi_arburst : out STD_LOGIC_VECTOR ( 17 downto 0 ); - m_axi_arlock : out STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_arcache : out STD_LOGIC_VECTOR ( 35 downto 0 ); - m_axi_arprot : out STD_LOGIC_VECTOR ( 26 downto 0 ); - m_axi_arregion : out STD_LOGIC_VECTOR ( 35 downto 0 ); - m_axi_arqos : out STD_LOGIC_VECTOR ( 35 downto 0 ); - m_axi_aruser : out STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_arvalid : out STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_arready : in STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_rid : in STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_rdata : in STD_LOGIC_VECTOR ( 287 downto 0 ); - m_axi_rresp : in STD_LOGIC_VECTOR ( 17 downto 0 ); - m_axi_rlast : in STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_ruser : in STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_rvalid : in STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_rready : out STD_LOGIC_VECTOR ( 8 downto 0 ) + m_axi_awid : out STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_awaddr : out STD_LOGIC_VECTOR ( 351 downto 0 ); + m_axi_awlen : out STD_LOGIC_VECTOR ( 87 downto 0 ); + m_axi_awsize : out STD_LOGIC_VECTOR ( 32 downto 0 ); + m_axi_awburst : out STD_LOGIC_VECTOR ( 21 downto 0 ); + m_axi_awlock : out STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_awcache : out STD_LOGIC_VECTOR ( 43 downto 0 ); + m_axi_awprot : out STD_LOGIC_VECTOR ( 32 downto 0 ); + m_axi_awregion : out STD_LOGIC_VECTOR ( 43 downto 0 ); + m_axi_awqos : out STD_LOGIC_VECTOR ( 43 downto 0 ); + m_axi_awuser : out STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_awvalid : out STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_awready : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_wid : out STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_wdata : out STD_LOGIC_VECTOR ( 351 downto 0 ); + m_axi_wstrb : out STD_LOGIC_VECTOR ( 43 downto 0 ); + m_axi_wlast : out STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_wuser : out STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_wvalid : out STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_wready : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_bid : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_bresp : in STD_LOGIC_VECTOR ( 21 downto 0 ); + m_axi_buser : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_bvalid : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_bready : out STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_arid : out STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_araddr : out STD_LOGIC_VECTOR ( 351 downto 0 ); + m_axi_arlen : out STD_LOGIC_VECTOR ( 87 downto 0 ); + m_axi_arsize : out STD_LOGIC_VECTOR ( 32 downto 0 ); + m_axi_arburst : out STD_LOGIC_VECTOR ( 21 downto 0 ); + m_axi_arlock : out STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_arcache : out STD_LOGIC_VECTOR ( 43 downto 0 ); + m_axi_arprot : out STD_LOGIC_VECTOR ( 32 downto 0 ); + m_axi_arregion : out STD_LOGIC_VECTOR ( 43 downto 0 ); + m_axi_arqos : out STD_LOGIC_VECTOR ( 43 downto 0 ); + m_axi_aruser : out STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_arvalid : out STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_arready : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_rid : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_rdata : in STD_LOGIC_VECTOR ( 351 downto 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 21 downto 0 ); + m_axi_rlast : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_ruser : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_rvalid : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_rready : out STD_LOGIC_VECTOR ( 10 downto 0 ) ); attribute C_AXI_ADDR_WIDTH : integer; attribute C_AXI_ADDR_WIDTH of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 32; @@ -6596,23 +7511,23 @@ entity Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar is attribute C_FAMILY : string; attribute C_FAMILY of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "zynq"; attribute C_M_AXI_ADDR_WIDTH : string; - attribute C_M_AXI_ADDR_WIDTH of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "288'b000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000"; + attribute C_M_AXI_ADDR_WIDTH of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "352'b0000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000"; attribute C_M_AXI_BASE_ADDR : string; - attribute C_M_AXI_BASE_ADDR of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "576'b000000000000000000000000000000000100000100100100000000000000000000000000000000000000000000000000010000111100001000000000000000000000000000000000000000000000000001000001001000110000000000000000000000000000000000000000000000000100001111000001000000000000000000000000000000000000000000000000010000111100000000000000000000000000000000000000000000000000000001000011000000000000000000000000000000000000000000000000000000000100000100100010000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000"; + attribute C_M_AXI_BASE_ADDR of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "704'b00000000000000000000000000000000010000010010010100000000000000000000000000000000000000000000000001000011110000110000000000000000000000000000000000000000000000000100000100100100000000000000000000000000000000000000000000000000010000111100001000000000000000000000000000000000000000000000000001000001001000110000000000000000000000000000000000000000000000000100001111000001000000000000000000000000000000000000000000000000010000111100000000000000000000000000000000000000000000000000000001000011000000000000000000000000000000000000000000000000000000000100000100100010000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000"; attribute C_M_AXI_READ_CONNECTIVITY : string; - attribute C_M_AXI_READ_CONNECTIVITY of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "288'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"; + attribute C_M_AXI_READ_CONNECTIVITY of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "352'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"; attribute C_M_AXI_READ_ISSUING : string; - attribute C_M_AXI_READ_ISSUING of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "288'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"; + attribute C_M_AXI_READ_ISSUING of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "352'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"; attribute C_M_AXI_SECURE : string; - attribute C_M_AXI_SECURE of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "288'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute C_M_AXI_SECURE of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "352'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; attribute C_M_AXI_WRITE_CONNECTIVITY : string; - attribute C_M_AXI_WRITE_CONNECTIVITY of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "288'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"; + attribute C_M_AXI_WRITE_CONNECTIVITY of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "352'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"; attribute C_M_AXI_WRITE_ISSUING : string; - attribute C_M_AXI_WRITE_ISSUING of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "288'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"; + attribute C_M_AXI_WRITE_ISSUING of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "352'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"; attribute C_NUM_ADDR_RANGES : integer; attribute C_NUM_ADDR_RANGES of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1; attribute C_NUM_MASTER_SLOTS : integer; - attribute C_NUM_MASTER_SLOTS of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 9; + attribute C_NUM_MASTER_SLOTS of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 11; attribute C_NUM_SLAVE_SLOTS : integer; attribute C_NUM_SLAVE_SLOTS of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1; attribute C_R_REGISTER : integer; @@ -6652,11 +7567,11 @@ entity Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar is attribute P_LOCK : integer; attribute P_LOCK of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1; attribute P_M_AXI_ERR_MODE : string; - attribute P_M_AXI_ERR_MODE of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "288'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute P_M_AXI_ERR_MODE of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "352'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; attribute P_M_AXI_SUPPORTS_READ : string; - attribute P_M_AXI_SUPPORTS_READ of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "9'b111111111"; + attribute P_M_AXI_SUPPORTS_READ of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "11'b11111111111"; attribute P_M_AXI_SUPPORTS_WRITE : string; - attribute P_M_AXI_SUPPORTS_WRITE of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "9'b111111111"; + attribute P_M_AXI_SUPPORTS_WRITE of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "11'b11111111111"; attribute P_ONES : string; attribute P_ONES of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "65'b11111111111111111111111111111111111111111111111111111111111111111"; attribute P_RANGE_CHECK : integer; @@ -6675,30 +7590,38 @@ architecture STRUCTURE of Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar is signal \\ : STD_LOGIC; signal \^m_axi_araddr\ : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \^m_axi_arprot\ : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal \^m_axi_awaddr\ : STD_LOGIC_VECTOR ( 287 downto 272 ); + signal \^m_axi_awaddr\ : STD_LOGIC_VECTOR ( 351 downto 336 ); signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 ); begin \^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0); \^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0); - m_axi_araddr(287 downto 272) <= \^m_axi_awaddr\(287 downto 272); + m_axi_araddr(351 downto 336) <= \^m_axi_awaddr\(351 downto 336); + m_axi_araddr(335 downto 320) <= \^m_axi_araddr\(15 downto 0); + m_axi_araddr(319 downto 304) <= \^m_axi_awaddr\(351 downto 336); + m_axi_araddr(303 downto 288) <= \^m_axi_araddr\(15 downto 0); + m_axi_araddr(287 downto 272) <= \^m_axi_awaddr\(351 downto 336); m_axi_araddr(271 downto 256) <= \^m_axi_araddr\(15 downto 0); - m_axi_araddr(255 downto 240) <= \^m_axi_awaddr\(287 downto 272); + m_axi_araddr(255 downto 240) <= \^m_axi_awaddr\(351 downto 336); m_axi_araddr(239 downto 224) <= \^m_axi_araddr\(15 downto 0); - m_axi_araddr(223 downto 208) <= \^m_axi_awaddr\(287 downto 272); + m_axi_araddr(223 downto 208) <= \^m_axi_awaddr\(351 downto 336); m_axi_araddr(207 downto 192) <= \^m_axi_araddr\(15 downto 0); - m_axi_araddr(191 downto 176) <= \^m_axi_awaddr\(287 downto 272); + m_axi_araddr(191 downto 176) <= \^m_axi_awaddr\(351 downto 336); m_axi_araddr(175 downto 160) <= \^m_axi_araddr\(15 downto 0); - m_axi_araddr(159 downto 144) <= \^m_axi_awaddr\(287 downto 272); + m_axi_araddr(159 downto 144) <= \^m_axi_awaddr\(351 downto 336); m_axi_araddr(143 downto 128) <= \^m_axi_araddr\(15 downto 0); - m_axi_araddr(127 downto 112) <= \^m_axi_awaddr\(287 downto 272); + m_axi_araddr(127 downto 112) <= \^m_axi_awaddr\(351 downto 336); m_axi_araddr(111 downto 96) <= \^m_axi_araddr\(15 downto 0); - m_axi_araddr(95 downto 80) <= \^m_axi_awaddr\(287 downto 272); + m_axi_araddr(95 downto 80) <= \^m_axi_awaddr\(351 downto 336); m_axi_araddr(79 downto 64) <= \^m_axi_araddr\(15 downto 0); - m_axi_araddr(63 downto 48) <= \^m_axi_awaddr\(287 downto 272); + m_axi_araddr(63 downto 48) <= \^m_axi_awaddr\(351 downto 336); m_axi_araddr(47 downto 32) <= \^m_axi_araddr\(15 downto 0); - m_axi_araddr(31 downto 16) <= \^m_axi_awaddr\(287 downto 272); + m_axi_araddr(31 downto 16) <= \^m_axi_awaddr\(351 downto 336); m_axi_araddr(15 downto 0) <= \^m_axi_araddr\(15 downto 0); + m_axi_arburst(21) <= \\; + m_axi_arburst(20) <= \\; + m_axi_arburst(19) <= \\; + m_axi_arburst(18) <= \\; m_axi_arburst(17) <= \\; m_axi_arburst(16) <= \\; m_axi_arburst(15) <= \\; @@ -6717,6 +7640,14 @@ begin m_axi_arburst(2) <= \\; m_axi_arburst(1) <= \\; m_axi_arburst(0) <= \\; + m_axi_arcache(43) <= \\; + m_axi_arcache(42) <= \\; + m_axi_arcache(41) <= \\; + m_axi_arcache(40) <= \\; + m_axi_arcache(39) <= \\; + m_axi_arcache(38) <= \\; + m_axi_arcache(37) <= \\; + m_axi_arcache(36) <= \\; m_axi_arcache(35) <= \\; m_axi_arcache(34) <= \\; m_axi_arcache(33) <= \\; @@ -6753,6 +7684,8 @@ begin m_axi_arcache(2) <= \\; m_axi_arcache(1) <= \\; m_axi_arcache(0) <= \\; + m_axi_arid(10) <= \\; + m_axi_arid(9) <= \\; m_axi_arid(8) <= \\; m_axi_arid(7) <= \\; m_axi_arid(6) <= \\; @@ -6762,6 +7695,22 @@ begin m_axi_arid(2) <= \\; m_axi_arid(1) <= \\; m_axi_arid(0) <= \\; + m_axi_arlen(87) <= \\; + m_axi_arlen(86) <= \\; + m_axi_arlen(85) <= \\; + m_axi_arlen(84) <= \\; + m_axi_arlen(83) <= \\; + m_axi_arlen(82) <= \\; + m_axi_arlen(81) <= \\; + m_axi_arlen(80) <= \\; + m_axi_arlen(79) <= \\; + m_axi_arlen(78) <= \\; + m_axi_arlen(77) <= \\; + m_axi_arlen(76) <= \\; + m_axi_arlen(75) <= \\; + m_axi_arlen(74) <= \\; + m_axi_arlen(73) <= \\; + m_axi_arlen(72) <= \\; m_axi_arlen(71) <= \\; m_axi_arlen(70) <= \\; m_axi_arlen(69) <= \\; @@ -6834,6 +7783,8 @@ begin m_axi_arlen(2) <= \\; m_axi_arlen(1) <= \\; m_axi_arlen(0) <= \\; + m_axi_arlock(10) <= \\; + m_axi_arlock(9) <= \\; m_axi_arlock(8) <= \\; m_axi_arlock(7) <= \\; m_axi_arlock(6) <= \\; @@ -6843,6 +7794,8 @@ begin m_axi_arlock(2) <= \\; m_axi_arlock(1) <= \\; m_axi_arlock(0) <= \\; + m_axi_arprot(32 downto 30) <= \^m_axi_arprot\(2 downto 0); + m_axi_arprot(29 downto 27) <= \^m_axi_arprot\(2 downto 0); m_axi_arprot(26 downto 24) <= \^m_axi_arprot\(2 downto 0); m_axi_arprot(23 downto 21) <= \^m_axi_arprot\(2 downto 0); m_axi_arprot(20 downto 18) <= \^m_axi_arprot\(2 downto 0); @@ -6852,6 +7805,14 @@ begin m_axi_arprot(8 downto 6) <= \^m_axi_arprot\(2 downto 0); m_axi_arprot(5 downto 3) <= \^m_axi_arprot\(2 downto 0); m_axi_arprot(2 downto 0) <= \^m_axi_arprot\(2 downto 0); + m_axi_arqos(43) <= \\; + m_axi_arqos(42) <= \\; + m_axi_arqos(41) <= \\; + m_axi_arqos(40) <= \\; + m_axi_arqos(39) <= \\; + m_axi_arqos(38) <= \\; + m_axi_arqos(37) <= \\; + m_axi_arqos(36) <= \\; m_axi_arqos(35) <= \\; m_axi_arqos(34) <= \\; m_axi_arqos(33) <= \\; @@ -6888,6 +7849,14 @@ begin m_axi_arqos(2) <= \\; m_axi_arqos(1) <= \\; m_axi_arqos(0) <= \\; + m_axi_arregion(43) <= \\; + m_axi_arregion(42) <= \\; + m_axi_arregion(41) <= \\; + m_axi_arregion(40) <= \\; + m_axi_arregion(39) <= \\; + m_axi_arregion(38) <= \\; + m_axi_arregion(37) <= \\; + m_axi_arregion(36) <= \\; m_axi_arregion(35) <= \\; m_axi_arregion(34) <= \\; m_axi_arregion(33) <= \\; @@ -6924,6 +7893,12 @@ begin m_axi_arregion(2) <= \\; m_axi_arregion(1) <= \\; m_axi_arregion(0) <= \\; + m_axi_arsize(32) <= \\; + m_axi_arsize(31) <= \\; + m_axi_arsize(30) <= \\; + m_axi_arsize(29) <= \\; + m_axi_arsize(28) <= \\; + m_axi_arsize(27) <= \\; m_axi_arsize(26) <= \\; m_axi_arsize(25) <= \\; m_axi_arsize(24) <= \\; @@ -6951,6 +7926,8 @@ begin m_axi_arsize(2) <= \\; m_axi_arsize(1) <= \\; m_axi_arsize(0) <= \\; + m_axi_aruser(10) <= \\; + m_axi_aruser(9) <= \\; m_axi_aruser(8) <= \\; m_axi_aruser(7) <= \\; m_axi_aruser(6) <= \\; @@ -6960,24 +7937,32 @@ begin m_axi_aruser(2) <= \\; m_axi_aruser(1) <= \\; m_axi_aruser(0) <= \\; - m_axi_awaddr(287 downto 272) <= \^m_axi_awaddr\(287 downto 272); + m_axi_awaddr(351 downto 336) <= \^m_axi_awaddr\(351 downto 336); + m_axi_awaddr(335 downto 320) <= \^m_axi_araddr\(15 downto 0); + m_axi_awaddr(319 downto 304) <= \^m_axi_awaddr\(351 downto 336); + m_axi_awaddr(303 downto 288) <= \^m_axi_araddr\(15 downto 0); + m_axi_awaddr(287 downto 272) <= \^m_axi_awaddr\(351 downto 336); m_axi_awaddr(271 downto 256) <= \^m_axi_araddr\(15 downto 0); - m_axi_awaddr(255 downto 240) <= \^m_axi_awaddr\(287 downto 272); + m_axi_awaddr(255 downto 240) <= \^m_axi_awaddr\(351 downto 336); m_axi_awaddr(239 downto 224) <= \^m_axi_araddr\(15 downto 0); - m_axi_awaddr(223 downto 208) <= \^m_axi_awaddr\(287 downto 272); + m_axi_awaddr(223 downto 208) <= \^m_axi_awaddr\(351 downto 336); m_axi_awaddr(207 downto 192) <= \^m_axi_araddr\(15 downto 0); - m_axi_awaddr(191 downto 176) <= \^m_axi_awaddr\(287 downto 272); + m_axi_awaddr(191 downto 176) <= \^m_axi_awaddr\(351 downto 336); m_axi_awaddr(175 downto 160) <= \^m_axi_araddr\(15 downto 0); - m_axi_awaddr(159 downto 144) <= \^m_axi_awaddr\(287 downto 272); + m_axi_awaddr(159 downto 144) <= \^m_axi_awaddr\(351 downto 336); m_axi_awaddr(143 downto 128) <= \^m_axi_araddr\(15 downto 0); - m_axi_awaddr(127 downto 112) <= \^m_axi_awaddr\(287 downto 272); + m_axi_awaddr(127 downto 112) <= \^m_axi_awaddr\(351 downto 336); m_axi_awaddr(111 downto 96) <= \^m_axi_araddr\(15 downto 0); - m_axi_awaddr(95 downto 80) <= \^m_axi_awaddr\(287 downto 272); + m_axi_awaddr(95 downto 80) <= \^m_axi_awaddr\(351 downto 336); m_axi_awaddr(79 downto 64) <= \^m_axi_araddr\(15 downto 0); - m_axi_awaddr(63 downto 48) <= \^m_axi_awaddr\(287 downto 272); + m_axi_awaddr(63 downto 48) <= \^m_axi_awaddr\(351 downto 336); m_axi_awaddr(47 downto 32) <= \^m_axi_araddr\(15 downto 0); - m_axi_awaddr(31 downto 16) <= \^m_axi_awaddr\(287 downto 272); + m_axi_awaddr(31 downto 16) <= \^m_axi_awaddr\(351 downto 336); m_axi_awaddr(15 downto 0) <= \^m_axi_araddr\(15 downto 0); + m_axi_awburst(21) <= \\; + m_axi_awburst(20) <= \\; + m_axi_awburst(19) <= \\; + m_axi_awburst(18) <= \\; m_axi_awburst(17) <= \\; m_axi_awburst(16) <= \\; m_axi_awburst(15) <= \\; @@ -6996,6 +7981,14 @@ begin m_axi_awburst(2) <= \\; m_axi_awburst(1) <= \\; m_axi_awburst(0) <= \\; + m_axi_awcache(43) <= \\; + m_axi_awcache(42) <= \\; + m_axi_awcache(41) <= \\; + m_axi_awcache(40) <= \\; + m_axi_awcache(39) <= \\; + m_axi_awcache(38) <= \\; + m_axi_awcache(37) <= \\; + m_axi_awcache(36) <= \\; m_axi_awcache(35) <= \\; m_axi_awcache(34) <= \\; m_axi_awcache(33) <= \\; @@ -7032,6 +8025,8 @@ begin m_axi_awcache(2) <= \\; m_axi_awcache(1) <= \\; m_axi_awcache(0) <= \\; + m_axi_awid(10) <= \\; + m_axi_awid(9) <= \\; m_axi_awid(8) <= \\; m_axi_awid(7) <= \\; m_axi_awid(6) <= \\; @@ -7041,6 +8036,22 @@ begin m_axi_awid(2) <= \\; m_axi_awid(1) <= \\; m_axi_awid(0) <= \\; + m_axi_awlen(87) <= \\; + m_axi_awlen(86) <= \\; + m_axi_awlen(85) <= \\; + m_axi_awlen(84) <= \\; + m_axi_awlen(83) <= \\; + m_axi_awlen(82) <= \\; + m_axi_awlen(81) <= \\; + m_axi_awlen(80) <= \\; + m_axi_awlen(79) <= \\; + m_axi_awlen(78) <= \\; + m_axi_awlen(77) <= \\; + m_axi_awlen(76) <= \\; + m_axi_awlen(75) <= \\; + m_axi_awlen(74) <= \\; + m_axi_awlen(73) <= \\; + m_axi_awlen(72) <= \\; m_axi_awlen(71) <= \\; m_axi_awlen(70) <= \\; m_axi_awlen(69) <= \\; @@ -7113,6 +8124,8 @@ begin m_axi_awlen(2) <= \\; m_axi_awlen(1) <= \\; m_axi_awlen(0) <= \\; + m_axi_awlock(10) <= \\; + m_axi_awlock(9) <= \\; m_axi_awlock(8) <= \\; m_axi_awlock(7) <= \\; m_axi_awlock(6) <= \\; @@ -7122,6 +8135,8 @@ begin m_axi_awlock(2) <= \\; m_axi_awlock(1) <= \\; m_axi_awlock(0) <= \\; + m_axi_awprot(32 downto 30) <= \^m_axi_arprot\(2 downto 0); + m_axi_awprot(29 downto 27) <= \^m_axi_arprot\(2 downto 0); m_axi_awprot(26 downto 24) <= \^m_axi_arprot\(2 downto 0); m_axi_awprot(23 downto 21) <= \^m_axi_arprot\(2 downto 0); m_axi_awprot(20 downto 18) <= \^m_axi_arprot\(2 downto 0); @@ -7131,6 +8146,14 @@ begin m_axi_awprot(8 downto 6) <= \^m_axi_arprot\(2 downto 0); m_axi_awprot(5 downto 3) <= \^m_axi_arprot\(2 downto 0); m_axi_awprot(2 downto 0) <= \^m_axi_arprot\(2 downto 0); + m_axi_awqos(43) <= \\; + m_axi_awqos(42) <= \\; + m_axi_awqos(41) <= \\; + m_axi_awqos(40) <= \\; + m_axi_awqos(39) <= \\; + m_axi_awqos(38) <= \\; + m_axi_awqos(37) <= \\; + m_axi_awqos(36) <= \\; m_axi_awqos(35) <= \\; m_axi_awqos(34) <= \\; m_axi_awqos(33) <= \\; @@ -7167,6 +8190,14 @@ begin m_axi_awqos(2) <= \\; m_axi_awqos(1) <= \\; m_axi_awqos(0) <= \\; + m_axi_awregion(43) <= \\; + m_axi_awregion(42) <= \\; + m_axi_awregion(41) <= \\; + m_axi_awregion(40) <= \\; + m_axi_awregion(39) <= \\; + m_axi_awregion(38) <= \\; + m_axi_awregion(37) <= \\; + m_axi_awregion(36) <= \\; m_axi_awregion(35) <= \\; m_axi_awregion(34) <= \\; m_axi_awregion(33) <= \\; @@ -7203,6 +8234,12 @@ begin m_axi_awregion(2) <= \\; m_axi_awregion(1) <= \\; m_axi_awregion(0) <= \\; + m_axi_awsize(32) <= \\; + m_axi_awsize(31) <= \\; + m_axi_awsize(30) <= \\; + m_axi_awsize(29) <= \\; + m_axi_awsize(28) <= \\; + m_axi_awsize(27) <= \\; m_axi_awsize(26) <= \\; m_axi_awsize(25) <= \\; m_axi_awsize(24) <= \\; @@ -7230,6 +8267,8 @@ begin m_axi_awsize(2) <= \\; m_axi_awsize(1) <= \\; m_axi_awsize(0) <= \\; + m_axi_awuser(10) <= \\; + m_axi_awuser(9) <= \\; m_axi_awuser(8) <= \\; m_axi_awuser(7) <= \\; m_axi_awuser(6) <= \\; @@ -7239,6 +8278,8 @@ begin m_axi_awuser(2) <= \\; m_axi_awuser(1) <= \\; m_axi_awuser(0) <= \\; + m_axi_wdata(351 downto 320) <= \^s_axi_wdata\(31 downto 0); + m_axi_wdata(319 downto 288) <= \^s_axi_wdata\(31 downto 0); m_axi_wdata(287 downto 256) <= \^s_axi_wdata\(31 downto 0); m_axi_wdata(255 downto 224) <= \^s_axi_wdata\(31 downto 0); m_axi_wdata(223 downto 192) <= \^s_axi_wdata\(31 downto 0); @@ -7248,6 +8289,8 @@ begin m_axi_wdata(95 downto 64) <= \^s_axi_wdata\(31 downto 0); m_axi_wdata(63 downto 32) <= \^s_axi_wdata\(31 downto 0); m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0); + m_axi_wid(10) <= \\; + m_axi_wid(9) <= \\; m_axi_wid(8) <= \\; m_axi_wid(7) <= \\; m_axi_wid(6) <= \\; @@ -7257,6 +8300,8 @@ begin m_axi_wid(2) <= \\; m_axi_wid(1) <= \\; m_axi_wid(0) <= \\; + m_axi_wlast(10) <= \\; + m_axi_wlast(9) <= \\; m_axi_wlast(8) <= \\; m_axi_wlast(7) <= \\; m_axi_wlast(6) <= \\; @@ -7266,6 +8311,8 @@ begin m_axi_wlast(2) <= \\; m_axi_wlast(1) <= \\; m_axi_wlast(0) <= \\; + m_axi_wstrb(43 downto 40) <= \^s_axi_wstrb\(3 downto 0); + m_axi_wstrb(39 downto 36) <= \^s_axi_wstrb\(3 downto 0); m_axi_wstrb(35 downto 32) <= \^s_axi_wstrb\(3 downto 0); m_axi_wstrb(31 downto 28) <= \^s_axi_wstrb\(3 downto 0); m_axi_wstrb(27 downto 24) <= \^s_axi_wstrb\(3 downto 0); @@ -7275,6 +8322,8 @@ begin m_axi_wstrb(11 downto 8) <= \^s_axi_wstrb\(3 downto 0); m_axi_wstrb(7 downto 4) <= \^s_axi_wstrb\(3 downto 0); m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0); + m_axi_wuser(10) <= \\; + m_axi_wuser(9) <= \\; m_axi_wuser(8) <= \\; m_axi_wuser(7) <= \\; m_axi_wuser(6) <= \\; @@ -7296,23 +8345,23 @@ GND: unisim.vcomponents.GND \gen_sasd.crossbar_sasd_0\: entity work.Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_crossbar_sasd port map ( Q(34 downto 32) => \^m_axi_arprot\(2 downto 0), - Q(31 downto 16) => \^m_axi_awaddr\(287 downto 272), + Q(31 downto 16) => \^m_axi_awaddr\(351 downto 336), Q(15 downto 0) => \^m_axi_araddr\(15 downto 0), aclk => aclk, aresetn => aresetn, - m_axi_arready(8 downto 0) => m_axi_arready(8 downto 0), - m_axi_arvalid(8 downto 0) => m_axi_arvalid(8 downto 0), - m_axi_awready(8 downto 0) => m_axi_awready(8 downto 0), - m_axi_awvalid(8 downto 0) => m_axi_awvalid(8 downto 0), - m_axi_bready(8 downto 0) => m_axi_bready(8 downto 0), - m_axi_bresp(17 downto 0) => m_axi_bresp(17 downto 0), - m_axi_bvalid(8 downto 0) => m_axi_bvalid(8 downto 0), - m_axi_rdata(287 downto 0) => m_axi_rdata(287 downto 0), - m_axi_rready(8 downto 0) => m_axi_rready(8 downto 0), - m_axi_rresp(17 downto 0) => m_axi_rresp(17 downto 0), - m_axi_rvalid(8 downto 0) => m_axi_rvalid(8 downto 0), - m_axi_wready(8 downto 0) => m_axi_wready(8 downto 0), - m_axi_wvalid(8 downto 0) => m_axi_wvalid(8 downto 0), + m_axi_arready(10 downto 0) => m_axi_arready(10 downto 0), + m_axi_arvalid(10 downto 0) => m_axi_arvalid(10 downto 0), + m_axi_awready(10 downto 0) => m_axi_awready(10 downto 0), + m_axi_awvalid(10 downto 0) => m_axi_awvalid(10 downto 0), + m_axi_bready(10 downto 0) => m_axi_bready(10 downto 0), + m_axi_bresp(21 downto 0) => m_axi_bresp(21 downto 0), + m_axi_bvalid(10 downto 0) => m_axi_bvalid(10 downto 0), + m_axi_rdata(351 downto 0) => m_axi_rdata(351 downto 0), + m_axi_rready(10 downto 0) => m_axi_rready(10 downto 0), + m_axi_rresp(21 downto 0) => m_axi_rresp(21 downto 0), + m_axi_rvalid(10 downto 0) => m_axi_rvalid(10 downto 0), + m_axi_wready(10 downto 0) => m_axi_wready(10 downto 0), + m_axi_wvalid(10 downto 0) => m_axi_wvalid(10 downto 0), s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arready(0) => s_axi_arready(0), @@ -7359,25 +8408,25 @@ entity Arty_Z7_20_xbar_0 is s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_awaddr : out STD_LOGIC_VECTOR ( 287 downto 0 ); - m_axi_awprot : out STD_LOGIC_VECTOR ( 26 downto 0 ); - m_axi_awvalid : out STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_awready : in STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_wdata : out STD_LOGIC_VECTOR ( 287 downto 0 ); - m_axi_wstrb : out STD_LOGIC_VECTOR ( 35 downto 0 ); - m_axi_wvalid : out STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_wready : in STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_bresp : in STD_LOGIC_VECTOR ( 17 downto 0 ); - m_axi_bvalid : in STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_bready : out STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_araddr : out STD_LOGIC_VECTOR ( 287 downto 0 ); - m_axi_arprot : out STD_LOGIC_VECTOR ( 26 downto 0 ); - m_axi_arvalid : out STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_arready : in STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_rdata : in STD_LOGIC_VECTOR ( 287 downto 0 ); - m_axi_rresp : in STD_LOGIC_VECTOR ( 17 downto 0 ); - m_axi_rvalid : in STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_rready : out STD_LOGIC_VECTOR ( 8 downto 0 ) + m_axi_awaddr : out STD_LOGIC_VECTOR ( 351 downto 0 ); + m_axi_awprot : out STD_LOGIC_VECTOR ( 32 downto 0 ); + m_axi_awvalid : out STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_awready : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_wdata : out STD_LOGIC_VECTOR ( 351 downto 0 ); + m_axi_wstrb : out STD_LOGIC_VECTOR ( 43 downto 0 ); + m_axi_wvalid : out STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_wready : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_bresp : in STD_LOGIC_VECTOR ( 21 downto 0 ); + m_axi_bvalid : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_bready : out STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_araddr : out STD_LOGIC_VECTOR ( 351 downto 0 ); + m_axi_arprot : out STD_LOGIC_VECTOR ( 32 downto 0 ); + m_axi_arvalid : out STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_arready : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_rdata : in STD_LOGIC_VECTOR ( 351 downto 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 21 downto 0 ); + m_axi_rvalid : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_rready : out STD_LOGIC_VECTOR ( 10 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of Arty_Z7_20_xbar_0 : entity is true; @@ -7390,27 +8439,27 @@ entity Arty_Z7_20_xbar_0 is end Arty_Z7_20_xbar_0; architecture STRUCTURE of Arty_Z7_20_xbar_0 is - signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 ); - signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 35 downto 0 ); - signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 ); - signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 71 downto 0 ); - signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 ); - signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 35 downto 0 ); - signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 35 downto 0 ); - signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 26 downto 0 ); - signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 ); - signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 ); - signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 35 downto 0 ); - signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 ); - signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 71 downto 0 ); - signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 ); - signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 35 downto 0 ); - signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 35 downto 0 ); - signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 26 downto 0 ); - signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 ); - signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 ); - signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 ); - signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 ); + signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 43 downto 0 ); + signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 87 downto 0 ); + signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 43 downto 0 ); + signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 43 downto 0 ); + signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 32 downto 0 ); + signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 ); + signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 43 downto 0 ); + signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 87 downto 0 ); + signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 43 downto 0 ); + signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 43 downto 0 ); + signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 32 downto 0 ); + signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); @@ -7443,23 +8492,23 @@ architecture STRUCTURE of Arty_Z7_20_xbar_0 is attribute C_FAMILY : string; attribute C_FAMILY of inst : label is "zynq"; attribute C_M_AXI_ADDR_WIDTH : string; - attribute C_M_AXI_ADDR_WIDTH of inst : label is "288'b000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000"; + attribute C_M_AXI_ADDR_WIDTH of inst : label is "352'b0000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000"; attribute C_M_AXI_BASE_ADDR : string; - attribute C_M_AXI_BASE_ADDR of inst : label is "576'b000000000000000000000000000000000100000100100100000000000000000000000000000000000000000000000000010000111100001000000000000000000000000000000000000000000000000001000001001000110000000000000000000000000000000000000000000000000100001111000001000000000000000000000000000000000000000000000000010000111100000000000000000000000000000000000000000000000000000001000011000000000000000000000000000000000000000000000000000000000100000100100010000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000"; + attribute C_M_AXI_BASE_ADDR of inst : label is "704'b00000000000000000000000000000000010000010010010100000000000000000000000000000000000000000000000001000011110000110000000000000000000000000000000000000000000000000100000100100100000000000000000000000000000000000000000000000000010000111100001000000000000000000000000000000000000000000000000001000001001000110000000000000000000000000000000000000000000000000100001111000001000000000000000000000000000000000000000000000000010000111100000000000000000000000000000000000000000000000000000001000011000000000000000000000000000000000000000000000000000000000100000100100010000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000"; attribute C_M_AXI_READ_CONNECTIVITY : string; - attribute C_M_AXI_READ_CONNECTIVITY of inst : label is "288'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"; + attribute C_M_AXI_READ_CONNECTIVITY of inst : label is "352'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"; attribute C_M_AXI_READ_ISSUING : string; - attribute C_M_AXI_READ_ISSUING of inst : label is "288'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"; + attribute C_M_AXI_READ_ISSUING of inst : label is "352'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"; attribute C_M_AXI_SECURE : string; - attribute C_M_AXI_SECURE of inst : label is "288'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute C_M_AXI_SECURE of inst : label is "352'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; attribute C_M_AXI_WRITE_CONNECTIVITY : string; - attribute C_M_AXI_WRITE_CONNECTIVITY of inst : label is "288'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"; + attribute C_M_AXI_WRITE_CONNECTIVITY of inst : label is "352'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"; attribute C_M_AXI_WRITE_ISSUING : string; - attribute C_M_AXI_WRITE_ISSUING of inst : label is "288'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"; + attribute C_M_AXI_WRITE_ISSUING of inst : label is "352'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001"; attribute C_NUM_ADDR_RANGES : integer; attribute C_NUM_ADDR_RANGES of inst : label is 1; attribute C_NUM_MASTER_SLOTS : integer; - attribute C_NUM_MASTER_SLOTS of inst : label is 9; + attribute C_NUM_MASTER_SLOTS of inst : label is 11; attribute C_NUM_SLAVE_SLOTS : integer; attribute C_NUM_SLAVE_SLOTS of inst : label is 1; attribute C_R_REGISTER : integer; @@ -7496,11 +8545,11 @@ architecture STRUCTURE of Arty_Z7_20_xbar_0 is attribute P_LOCK : integer; attribute P_LOCK of inst : label is 1; attribute P_M_AXI_ERR_MODE : string; - attribute P_M_AXI_ERR_MODE of inst : label is "288'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute P_M_AXI_ERR_MODE of inst : label is "352'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; attribute P_M_AXI_SUPPORTS_READ : string; - attribute P_M_AXI_SUPPORTS_READ of inst : label is "9'b111111111"; + attribute P_M_AXI_SUPPORTS_READ of inst : label is "11'b11111111111"; attribute P_M_AXI_SUPPORTS_WRITE : string; - attribute P_M_AXI_SUPPORTS_WRITE of inst : label is "9'b111111111"; + attribute P_M_AXI_SUPPORTS_WRITE of inst : label is "11'b11111111111"; attribute P_ONES : string; attribute P_ONES of inst : label is "65'b11111111111111111111111111111111111111111111111111111111111111111"; attribute P_RANGE_CHECK : integer; @@ -7518,51 +8567,51 @@ inst: entity work.Arty_Z7_20_xbar_0_axi_crossbar_v2_1_12_axi_crossbar port map ( aclk => aclk, aresetn => aresetn, - m_axi_araddr(287 downto 0) => m_axi_araddr(287 downto 0), - m_axi_arburst(17 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(17 downto 0), - m_axi_arcache(35 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(35 downto 0), - m_axi_arid(8 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(8 downto 0), - m_axi_arlen(71 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(71 downto 0), - m_axi_arlock(8 downto 0) => NLW_inst_m_axi_arlock_UNCONNECTED(8 downto 0), - m_axi_arprot(26 downto 0) => m_axi_arprot(26 downto 0), - m_axi_arqos(35 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(35 downto 0), - m_axi_arready(8 downto 0) => m_axi_arready(8 downto 0), - m_axi_arregion(35 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(35 downto 0), - m_axi_arsize(26 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(26 downto 0), - m_axi_aruser(8 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(8 downto 0), - m_axi_arvalid(8 downto 0) => m_axi_arvalid(8 downto 0), - m_axi_awaddr(287 downto 0) => m_axi_awaddr(287 downto 0), - m_axi_awburst(17 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(17 downto 0), - m_axi_awcache(35 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(35 downto 0), - m_axi_awid(8 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(8 downto 0), - m_axi_awlen(71 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(71 downto 0), - m_axi_awlock(8 downto 0) => NLW_inst_m_axi_awlock_UNCONNECTED(8 downto 0), - m_axi_awprot(26 downto 0) => m_axi_awprot(26 downto 0), - m_axi_awqos(35 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(35 downto 0), - m_axi_awready(8 downto 0) => m_axi_awready(8 downto 0), - m_axi_awregion(35 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(35 downto 0), - m_axi_awsize(26 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(26 downto 0), - m_axi_awuser(8 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(8 downto 0), - m_axi_awvalid(8 downto 0) => m_axi_awvalid(8 downto 0), - m_axi_bid(8 downto 0) => B"000000000", - m_axi_bready(8 downto 0) => m_axi_bready(8 downto 0), - m_axi_bresp(17 downto 0) => m_axi_bresp(17 downto 0), - m_axi_buser(8 downto 0) => B"000000000", - m_axi_bvalid(8 downto 0) => m_axi_bvalid(8 downto 0), - m_axi_rdata(287 downto 0) => m_axi_rdata(287 downto 0), - m_axi_rid(8 downto 0) => B"000000000", - m_axi_rlast(8 downto 0) => B"111111111", - m_axi_rready(8 downto 0) => m_axi_rready(8 downto 0), - m_axi_rresp(17 downto 0) => m_axi_rresp(17 downto 0), - m_axi_ruser(8 downto 0) => B"000000000", - m_axi_rvalid(8 downto 0) => m_axi_rvalid(8 downto 0), - m_axi_wdata(287 downto 0) => m_axi_wdata(287 downto 0), - m_axi_wid(8 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(8 downto 0), - m_axi_wlast(8 downto 0) => NLW_inst_m_axi_wlast_UNCONNECTED(8 downto 0), - m_axi_wready(8 downto 0) => m_axi_wready(8 downto 0), - m_axi_wstrb(35 downto 0) => m_axi_wstrb(35 downto 0), - m_axi_wuser(8 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(8 downto 0), - m_axi_wvalid(8 downto 0) => m_axi_wvalid(8 downto 0), + m_axi_araddr(351 downto 0) => m_axi_araddr(351 downto 0), + m_axi_arburst(21 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(21 downto 0), + m_axi_arcache(43 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(43 downto 0), + m_axi_arid(10 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(10 downto 0), + m_axi_arlen(87 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(87 downto 0), + m_axi_arlock(10 downto 0) => NLW_inst_m_axi_arlock_UNCONNECTED(10 downto 0), + m_axi_arprot(32 downto 0) => m_axi_arprot(32 downto 0), + m_axi_arqos(43 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(43 downto 0), + m_axi_arready(10 downto 0) => m_axi_arready(10 downto 0), + m_axi_arregion(43 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(43 downto 0), + m_axi_arsize(32 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(32 downto 0), + m_axi_aruser(10 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(10 downto 0), + m_axi_arvalid(10 downto 0) => m_axi_arvalid(10 downto 0), + m_axi_awaddr(351 downto 0) => m_axi_awaddr(351 downto 0), + m_axi_awburst(21 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(21 downto 0), + m_axi_awcache(43 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(43 downto 0), + m_axi_awid(10 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(10 downto 0), + m_axi_awlen(87 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(87 downto 0), + m_axi_awlock(10 downto 0) => NLW_inst_m_axi_awlock_UNCONNECTED(10 downto 0), + m_axi_awprot(32 downto 0) => m_axi_awprot(32 downto 0), + m_axi_awqos(43 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(43 downto 0), + m_axi_awready(10 downto 0) => m_axi_awready(10 downto 0), + m_axi_awregion(43 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(43 downto 0), + m_axi_awsize(32 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(32 downto 0), + m_axi_awuser(10 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(10 downto 0), + m_axi_awvalid(10 downto 0) => m_axi_awvalid(10 downto 0), + m_axi_bid(10 downto 0) => B"00000000000", + m_axi_bready(10 downto 0) => m_axi_bready(10 downto 0), + m_axi_bresp(21 downto 0) => m_axi_bresp(21 downto 0), + m_axi_buser(10 downto 0) => B"00000000000", + m_axi_bvalid(10 downto 0) => m_axi_bvalid(10 downto 0), + m_axi_rdata(351 downto 0) => m_axi_rdata(351 downto 0), + m_axi_rid(10 downto 0) => B"00000000000", + m_axi_rlast(10 downto 0) => B"11111111111", + m_axi_rready(10 downto 0) => m_axi_rready(10 downto 0), + m_axi_rresp(21 downto 0) => m_axi_rresp(21 downto 0), + m_axi_ruser(10 downto 0) => B"00000000000", + m_axi_rvalid(10 downto 0) => m_axi_rvalid(10 downto 0), + m_axi_wdata(351 downto 0) => m_axi_wdata(351 downto 0), + m_axi_wid(10 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(10 downto 0), + m_axi_wlast(10 downto 0) => NLW_inst_m_axi_wlast_UNCONNECTED(10 downto 0), + m_axi_wready(10 downto 0) => m_axi_wready(10 downto 0), + m_axi_wstrb(43 downto 0) => m_axi_wstrb(43 downto 0), + m_axi_wuser(10 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(10 downto 0), + m_axi_wvalid(10 downto 0) => m_axi_wvalid(10 downto 0), s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => B"00", s_axi_arcache(3 downto 0) => B"0000", diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0_stub.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0_stub.v index a907ba4..e011068 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0_stub.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -// Date : Fri Feb 24 16:02:41 2017 +// Date : Sat Mar 04 18:54:13 2017 // Host : WK73 running 64-bit Service Pack 1 (build 7601) // Command : write_verilog -force -mode synth_stub -// c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0_stub.v +// C:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0_stub.v // Design : Arty_Z7_20_xbar_0 // Purpose : Stub declaration of top-level module interface // Device : xc7z020clg400-1 @@ -21,7 +21,7 @@ module Arty_Z7_20_xbar_0(aclk, aresetn, s_axi_awaddr, s_axi_awprot, m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready) -/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[287:0],m_axi_awprot[26:0],m_axi_awvalid[8:0],m_axi_awready[8:0],m_axi_wdata[287:0],m_axi_wstrb[35:0],m_axi_wvalid[8:0],m_axi_wready[8:0],m_axi_bresp[17:0],m_axi_bvalid[8:0],m_axi_bready[8:0],m_axi_araddr[287:0],m_axi_arprot[26:0],m_axi_arvalid[8:0],m_axi_arready[8:0],m_axi_rdata[287:0],m_axi_rresp[17:0],m_axi_rvalid[8:0],m_axi_rready[8:0]" */; +/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[351:0],m_axi_awprot[32:0],m_axi_awvalid[10:0],m_axi_awready[10:0],m_axi_wdata[351:0],m_axi_wstrb[43:0],m_axi_wvalid[10:0],m_axi_wready[10:0],m_axi_bresp[21:0],m_axi_bvalid[10:0],m_axi_bready[10:0],m_axi_araddr[351:0],m_axi_arprot[32:0],m_axi_arvalid[10:0],m_axi_arready[10:0],m_axi_rdata[351:0],m_axi_rresp[21:0],m_axi_rvalid[10:0],m_axi_rready[10:0]" */; input aclk; input aresetn; input [31:0]s_axi_awaddr; @@ -43,23 +43,23 @@ module Arty_Z7_20_xbar_0(aclk, aresetn, s_axi_awaddr, s_axi_awprot, output [1:0]s_axi_rresp; output [0:0]s_axi_rvalid; input [0:0]s_axi_rready; - output [287:0]m_axi_awaddr; - output [26:0]m_axi_awprot; - output [8:0]m_axi_awvalid; - input [8:0]m_axi_awready; - output [287:0]m_axi_wdata; - output [35:0]m_axi_wstrb; - output [8:0]m_axi_wvalid; - input [8:0]m_axi_wready; - input [17:0]m_axi_bresp; - input [8:0]m_axi_bvalid; - output [8:0]m_axi_bready; - output [287:0]m_axi_araddr; - output [26:0]m_axi_arprot; - output [8:0]m_axi_arvalid; - input [8:0]m_axi_arready; - input [287:0]m_axi_rdata; - input [17:0]m_axi_rresp; - input [8:0]m_axi_rvalid; - output [8:0]m_axi_rready; + output [351:0]m_axi_awaddr; + output [32:0]m_axi_awprot; + output [10:0]m_axi_awvalid; + input [10:0]m_axi_awready; + output [351:0]m_axi_wdata; + output [43:0]m_axi_wstrb; + output [10:0]m_axi_wvalid; + input [10:0]m_axi_wready; + input [21:0]m_axi_bresp; + input [10:0]m_axi_bvalid; + output [10:0]m_axi_bready; + output [351:0]m_axi_araddr; + output [32:0]m_axi_arprot; + output [10:0]m_axi_arvalid; + input [10:0]m_axi_arready; + input [351:0]m_axi_rdata; + input [21:0]m_axi_rresp; + input [10:0]m_axi_rvalid; + output [10:0]m_axi_rready; endmodule diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0_stub.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0_stub.vhdl index 62631d5..cc2da76 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0_stub.vhdl +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 --- Date : Fri Feb 24 16:02:41 2017 +-- Date : Sat Mar 04 18:54:13 2017 -- Host : WK73 running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode synth_stub --- c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0_stub.vhdl +-- C:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/Arty_Z7_20_xbar_0_stub.vhdl -- Design : Arty_Z7_20_xbar_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7z020clg400-1 @@ -35,25 +35,25 @@ entity Arty_Z7_20_xbar_0 is s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axi_awaddr : out STD_LOGIC_VECTOR ( 287 downto 0 ); - m_axi_awprot : out STD_LOGIC_VECTOR ( 26 downto 0 ); - m_axi_awvalid : out STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_awready : in STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_wdata : out STD_LOGIC_VECTOR ( 287 downto 0 ); - m_axi_wstrb : out STD_LOGIC_VECTOR ( 35 downto 0 ); - m_axi_wvalid : out STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_wready : in STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_bresp : in STD_LOGIC_VECTOR ( 17 downto 0 ); - m_axi_bvalid : in STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_bready : out STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_araddr : out STD_LOGIC_VECTOR ( 287 downto 0 ); - m_axi_arprot : out STD_LOGIC_VECTOR ( 26 downto 0 ); - m_axi_arvalid : out STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_arready : in STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_rdata : in STD_LOGIC_VECTOR ( 287 downto 0 ); - m_axi_rresp : in STD_LOGIC_VECTOR ( 17 downto 0 ); - m_axi_rvalid : in STD_LOGIC_VECTOR ( 8 downto 0 ); - m_axi_rready : out STD_LOGIC_VECTOR ( 8 downto 0 ) + m_axi_awaddr : out STD_LOGIC_VECTOR ( 351 downto 0 ); + m_axi_awprot : out STD_LOGIC_VECTOR ( 32 downto 0 ); + m_axi_awvalid : out STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_awready : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_wdata : out STD_LOGIC_VECTOR ( 351 downto 0 ); + m_axi_wstrb : out STD_LOGIC_VECTOR ( 43 downto 0 ); + m_axi_wvalid : out STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_wready : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_bresp : in STD_LOGIC_VECTOR ( 21 downto 0 ); + m_axi_bvalid : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_bready : out STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_araddr : out STD_LOGIC_VECTOR ( 351 downto 0 ); + m_axi_arprot : out STD_LOGIC_VECTOR ( 32 downto 0 ); + m_axi_arvalid : out STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_arready : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_rdata : in STD_LOGIC_VECTOR ( 351 downto 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 21 downto 0 ); + m_axi_rvalid : in STD_LOGIC_VECTOR ( 10 downto 0 ); + m_axi_rready : out STD_LOGIC_VECTOR ( 10 downto 0 ) ); end Arty_Z7_20_xbar_0; @@ -62,7 +62,7 @@ architecture stub of Arty_Z7_20_xbar_0 is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[287:0],m_axi_awprot[26:0],m_axi_awvalid[8:0],m_axi_awready[8:0],m_axi_wdata[287:0],m_axi_wstrb[35:0],m_axi_wvalid[8:0],m_axi_wready[8:0],m_axi_bresp[17:0],m_axi_bvalid[8:0],m_axi_bready[8:0],m_axi_araddr[287:0],m_axi_arprot[26:0],m_axi_arvalid[8:0],m_axi_arready[8:0],m_axi_rdata[287:0],m_axi_rresp[17:0],m_axi_rvalid[8:0],m_axi_rready[8:0]"; +attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[351:0],m_axi_awprot[32:0],m_axi_awvalid[10:0],m_axi_awready[10:0],m_axi_wdata[351:0],m_axi_wstrb[43:0],m_axi_wvalid[10:0],m_axi_wready[10:0],m_axi_bresp[21:0],m_axi_bvalid[10:0],m_axi_bready[10:0],m_axi_araddr[351:0],m_axi_arprot[32:0],m_axi_arvalid[10:0],m_axi_arready[10:0],m_axi_rdata[351:0],m_axi_rresp[21:0],m_axi_rvalid[10:0],m_axi_rready[10:0]"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4"; begin diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/sim/Arty_Z7_20_xbar_0.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/sim/Arty_Z7_20_xbar_0.v index adaa8a5..e4ceb13 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/sim/Arty_Z7_20_xbar_0.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/sim/Arty_Z7_20_xbar_0.v @@ -139,74 +139,74 @@ output wire [0 : 0] s_axi_rvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) input wire [0 : 0] s_axi_rready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI AWADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI AWADDR [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI AWADDR [31:0] [223:192], xilinx.com:interface:aximm:1.0 M07_AXI AWADDR [31:0] [255:22\ -4], xilinx.com:interface:aximm:1.0 M08_AXI AWADDR [31:0] [287:256]" *) -output wire [287 : 0] m_axi_awaddr; +4], xilinx.com:interface:aximm:1.0 M08_AXI AWADDR [31:0] [287:256], xilinx.com:interface:aximm:1.0 M09_AXI AWADDR [31:0] [319:288], xilinx.com:interface:aximm:1.0 M10_AXI AWADDR [31:0] [351:320]" *) +output wire [351 : 0] m_axi_awaddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI AWPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI AWPROT [2:0] [17:15], xilinx.com:interface:aximm:1.0 M06_AXI AWPROT [2:0] [20:18], xilinx.com:interface:aximm:1.0 M07_AXI AWPROT [2:0] [23:21], xilinx.com:interfac\ -e:aximm:1.0 M08_AXI AWPROT [2:0] [26:24]" *) -output wire [26 : 0] m_axi_awprot; +e:aximm:1.0 M08_AXI AWPROT [2:0] [26:24], xilinx.com:interface:aximm:1.0 M09_AXI AWPROT [2:0] [29:27], xilinx.com:interface:aximm:1.0 M10_AXI AWPROT [2:0] [32:30]" *) +output wire [32 : 0] m_axi_awprot; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI AWVALID [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI AWVALID [0:0] [7:7], xilinx.com:interface\ -:aximm:1.0 M08_AXI AWVALID [0:0] [8:8]" *) -output wire [8 : 0] m_axi_awvalid; +:aximm:1.0 M08_AXI AWVALID [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI AWVALID [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI AWVALID [0:0] [10:10]" *) +output wire [10 : 0] m_axi_awvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI AWREADY [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI AWREADY [0:0] [7:7], xilinx.com:interface\ -:aximm:1.0 M08_AXI AWREADY [0:0] [8:8]" *) -input wire [8 : 0] m_axi_awready; +:aximm:1.0 M08_AXI AWREADY [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI AWREADY [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI AWREADY [0:0] [10:10]" *) +input wire [10 : 0] m_axi_awready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI WDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI WDATA [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI WDATA [31:0] [223:192], xilinx.com:interface:aximm:1.0 M07_AXI WDATA [31:0] [255:224], xili\ -nx.com:interface:aximm:1.0 M08_AXI WDATA [31:0] [287:256]" *) -output wire [287 : 0] m_axi_wdata; +nx.com:interface:aximm:1.0 M08_AXI WDATA [31:0] [287:256], xilinx.com:interface:aximm:1.0 M09_AXI WDATA [31:0] [319:288], xilinx.com:interface:aximm:1.0 M10_AXI WDATA [31:0] [351:320]" *) +output wire [351 : 0] m_axi_wdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12], xilinx.com:interface:aximm:1.0 M04_AXI WSTRB [3:0] [19:16], xilinx.com:interface:aximm:1.0 M05_AXI WSTRB [3:0] [23:20], xilinx.com:interface:aximm:1.0 M06_AXI WSTRB [3:0] [27:24], xilinx.com:interface:aximm:1.0 M07_AXI WSTRB [3:0] [31:28], xilinx.com:interface:axim\ -m:1.0 M08_AXI WSTRB [3:0] [35:32]" *) -output wire [35 : 0] m_axi_wstrb; +m:1.0 M08_AXI WSTRB [3:0] [35:32], xilinx.com:interface:aximm:1.0 M09_AXI WSTRB [3:0] [39:36], xilinx.com:interface:aximm:1.0 M10_AXI WSTRB [3:0] [43:40]" *) +output wire [43 : 0] m_axi_wstrb; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI WVALID [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI WVALID [0:0] [7:7], xilinx.com:interface:aximm:1\ -.0 M08_AXI WVALID [0:0] [8:8]" *) -output wire [8 : 0] m_axi_wvalid; +.0 M08_AXI WVALID [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI WVALID [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI WVALID [0:0] [10:10]" *) +output wire [10 : 0] m_axi_wvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI WREADY [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI WREADY [0:0] [7:7], xilinx.com:interface:aximm:1\ -.0 M08_AXI WREADY [0:0] [8:8]" *) -input wire [8 : 0] m_axi_wready; +.0 M08_AXI WREADY [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI WREADY [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI WREADY [0:0] [10:10]" *) +input wire [10 : 0] m_axi_wready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI BRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI BRESP [1:0] [11:10], xilinx.com:interface:aximm:1.0 M06_AXI BRESP [1:0] [13:12], xilinx.com:interface:aximm:1.0 M07_AXI BRESP [1:0] [15:14], xilinx.com:interface:aximm:1.0\ - M08_AXI BRESP [1:0] [17:16]" *) -input wire [17 : 0] m_axi_bresp; + M08_AXI BRESP [1:0] [17:16], xilinx.com:interface:aximm:1.0 M09_AXI BRESP [1:0] [19:18], xilinx.com:interface:aximm:1.0 M10_AXI BRESP [1:0] [21:20]" *) +input wire [21 : 0] m_axi_bresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI BVALID [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI BVALID [0:0] [7:7], xilinx.com:interface:aximm:1\ -.0 M08_AXI BVALID [0:0] [8:8]" *) -input wire [8 : 0] m_axi_bvalid; +.0 M08_AXI BVALID [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI BVALID [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI BVALID [0:0] [10:10]" *) +input wire [10 : 0] m_axi_bvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI BREADY [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI BREADY [0:0] [7:7], xilinx.com:interface:aximm:1\ -.0 M08_AXI BREADY [0:0] [8:8]" *) -output wire [8 : 0] m_axi_bready; +.0 M08_AXI BREADY [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI BREADY [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI BREADY [0:0] [10:10]" *) +output wire [10 : 0] m_axi_bready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI ARADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI ARADDR [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI ARADDR [31:0] [223:192], xilinx.com:interface:aximm:1.0 M07_AXI ARADDR [31:0] [255:22\ -4], xilinx.com:interface:aximm:1.0 M08_AXI ARADDR [31:0] [287:256]" *) -output wire [287 : 0] m_axi_araddr; +4], xilinx.com:interface:aximm:1.0 M08_AXI ARADDR [31:0] [287:256], xilinx.com:interface:aximm:1.0 M09_AXI ARADDR [31:0] [319:288], xilinx.com:interface:aximm:1.0 M10_AXI ARADDR [31:0] [351:320]" *) +output wire [351 : 0] m_axi_araddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI ARPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI ARPROT [2:0] [17:15], xilinx.com:interface:aximm:1.0 M06_AXI ARPROT [2:0] [20:18], xilinx.com:interface:aximm:1.0 M07_AXI ARPROT [2:0] [23:21], xilinx.com:interfac\ -e:aximm:1.0 M08_AXI ARPROT [2:0] [26:24]" *) -output wire [26 : 0] m_axi_arprot; +e:aximm:1.0 M08_AXI ARPROT [2:0] [26:24], xilinx.com:interface:aximm:1.0 M09_AXI ARPROT [2:0] [29:27], xilinx.com:interface:aximm:1.0 M10_AXI ARPROT [2:0] [32:30]" *) +output wire [32 : 0] m_axi_arprot; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI ARVALID [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI ARVALID [0:0] [7:7], xilinx.com:interface\ -:aximm:1.0 M08_AXI ARVALID [0:0] [8:8]" *) -output wire [8 : 0] m_axi_arvalid; +:aximm:1.0 M08_AXI ARVALID [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI ARVALID [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI ARVALID [0:0] [10:10]" *) +output wire [10 : 0] m_axi_arvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI ARREADY [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI ARREADY [0:0] [7:7], xilinx.com:interface\ -:aximm:1.0 M08_AXI ARREADY [0:0] [8:8]" *) -input wire [8 : 0] m_axi_arready; +:aximm:1.0 M08_AXI ARREADY [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI ARREADY [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI ARREADY [0:0] [10:10]" *) +input wire [10 : 0] m_axi_arready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI RDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI RDATA [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI RDATA [31:0] [223:192], xilinx.com:interface:aximm:1.0 M07_AXI RDATA [31:0] [255:224], xili\ -nx.com:interface:aximm:1.0 M08_AXI RDATA [31:0] [287:256]" *) -input wire [287 : 0] m_axi_rdata; +nx.com:interface:aximm:1.0 M08_AXI RDATA [31:0] [287:256], xilinx.com:interface:aximm:1.0 M09_AXI RDATA [31:0] [319:288], xilinx.com:interface:aximm:1.0 M10_AXI RDATA [31:0] [351:320]" *) +input wire [351 : 0] m_axi_rdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI RRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI RRESP [1:0] [11:10], xilinx.com:interface:aximm:1.0 M06_AXI RRESP [1:0] [13:12], xilinx.com:interface:aximm:1.0 M07_AXI RRESP [1:0] [15:14], xilinx.com:interface:aximm:1.0\ - M08_AXI RRESP [1:0] [17:16]" *) -input wire [17 : 0] m_axi_rresp; + M08_AXI RRESP [1:0] [17:16], xilinx.com:interface:aximm:1.0 M09_AXI RRESP [1:0] [19:18], xilinx.com:interface:aximm:1.0 M10_AXI RRESP [1:0] [21:20]" *) +input wire [21 : 0] m_axi_rresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI RVALID [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI RVALID [0:0] [7:7], xilinx.com:interface:aximm:1\ -.0 M08_AXI RVALID [0:0] [8:8]" *) -input wire [8 : 0] m_axi_rvalid; +.0 M08_AXI RVALID [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI RVALID [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI RVALID [0:0] [10:10]" *) +input wire [10 : 0] m_axi_rvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI RREADY [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI RREADY [0:0] [7:7], xilinx.com:interface:aximm:1\ -.0 M08_AXI RREADY [0:0] [8:8]" *) -output wire [8 : 0] m_axi_rready; +.0 M08_AXI RREADY [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI RREADY [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI RREADY [0:0] [10:10]" *) +output wire [10 : 0] m_axi_rready; axi_crossbar_v2_1_12_axi_crossbar #( .C_FAMILY("zynq"), .C_NUM_SLAVE_SLOTS(1), - .C_NUM_MASTER_SLOTS(9), + .C_NUM_MASTER_SLOTS(11), .C_AXI_ID_WIDTH(1), .C_AXI_ADDR_WIDTH(32), .C_AXI_DATA_WIDTH(32), .C_AXI_PROTOCOL(2), .C_NUM_ADDR_RANGES(1), - .C_M_AXI_BASE_ADDR(576'H00000000412400000000000043c2000000000000412300000000000043c100000000000043c000000000000043000000000000004122000000000000412100000000000041200000), - .C_M_AXI_ADDR_WIDTH(288'H000000100000001000000010000000100000001000000010000000100000001000000010), + .C_M_AXI_BASE_ADDR(704'H00000000412500000000000043c3000000000000412400000000000043c2000000000000412300000000000043c100000000000043c000000000000043000000000000004122000000000000412100000000000041200000), + .C_M_AXI_ADDR_WIDTH(352'H0000001000000010000000100000001000000010000000100000001000000010000000100000001000000010), .C_S_AXI_BASE_ID(32'H00000000), .C_S_AXI_THREAD_ID_WIDTH(32'H00000000), .C_AXI_SUPPORTS_USER_SIGNALS(0), @@ -215,16 +215,16 @@ output wire [8 : 0] m_axi_rready; .C_AXI_WUSER_WIDTH(1), .C_AXI_RUSER_WIDTH(1), .C_AXI_BUSER_WIDTH(1), - .C_M_AXI_WRITE_CONNECTIVITY(288'H000000010000000100000001000000010000000100000001000000010000000100000001), - .C_M_AXI_READ_CONNECTIVITY(288'H000000010000000100000001000000010000000100000001000000010000000100000001), + .C_M_AXI_WRITE_CONNECTIVITY(352'H0000000100000001000000010000000100000001000000010000000100000001000000010000000100000001), + .C_M_AXI_READ_CONNECTIVITY(352'H0000000100000001000000010000000100000001000000010000000100000001000000010000000100000001), .C_R_REGISTER(1), .C_S_AXI_SINGLE_THREAD(32'H00000001), .C_S_AXI_WRITE_ACCEPTANCE(32'H00000001), .C_S_AXI_READ_ACCEPTANCE(32'H00000001), - .C_M_AXI_WRITE_ISSUING(288'H000000010000000100000001000000010000000100000001000000010000000100000001), - .C_M_AXI_READ_ISSUING(288'H000000010000000100000001000000010000000100000001000000010000000100000001), + .C_M_AXI_WRITE_ISSUING(352'H0000000100000001000000010000000100000001000000010000000100000001000000010000000100000001), + .C_M_AXI_READ_ISSUING(352'H0000000100000001000000010000000100000001000000010000000100000001000000010000000100000001), .C_S_AXI_ARB_PRIORITY(32'H00000000), - .C_M_AXI_SECURE(288'H000000000000000000000000000000000000000000000000000000000000000000000000), + .C_M_AXI_SECURE(352'H0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .C_CONNECTIVITY_MODE(0) ) inst ( .aclk(aclk), @@ -292,9 +292,9 @@ output wire [8 : 0] m_axi_rready; .m_axi_wuser(), .m_axi_wvalid(m_axi_wvalid), .m_axi_wready(m_axi_wready), - .m_axi_bid(9'H000), + .m_axi_bid(11'H000), .m_axi_bresp(m_axi_bresp), - .m_axi_buser(9'H000), + .m_axi_buser(11'H000), .m_axi_bvalid(m_axi_bvalid), .m_axi_bready(m_axi_bready), .m_axi_arid(), @@ -310,11 +310,11 @@ output wire [8 : 0] m_axi_rready; .m_axi_aruser(), .m_axi_arvalid(m_axi_arvalid), .m_axi_arready(m_axi_arready), - .m_axi_rid(9'H000), + .m_axi_rid(11'H000), .m_axi_rdata(m_axi_rdata), .m_axi_rresp(m_axi_rresp), - .m_axi_rlast(9'H1FF), - .m_axi_ruser(9'H000), + .m_axi_rlast(11'H7FF), + .m_axi_ruser(11'H000), .m_axi_rvalid(m_axi_rvalid), .m_axi_rready(m_axi_rready) ); diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/synth/Arty_Z7_20_xbar_0.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/synth/Arty_Z7_20_xbar_0.v index 978a027..f47c2d4 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/synth/Arty_Z7_20_xbar_0.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_0/synth/Arty_Z7_20_xbar_0.v @@ -52,9 +52,10 @@ (* X_CORE_INFO = "axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4" *) (* CHECK_LICENSE_TYPE = "Arty_Z7_20_xbar_0,axi_crossbar_v2_1_12_axi_crossbar,{}" *) -(* CORE_GENERATION_INFO = "Arty_Z7_20_xbar_0,axi_crossbar_v2_1_12_axi_crossbar,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_crossbar,x_ipVersion=2.1,x_ipCoreRevision=12,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_NUM_SLAVE_SLOTS=1,C_NUM_MASTER_SLOTS=9,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_PROTOCOL=2,C_NUM_ADDR_RANGES=1,C_M_AXI_BASE_ADDR=0x00000000412400000000000043c2000000000000412300000000000043c100000000000043c000000000000043000000000000004122000000000\ -000412100000000000041200000,C_M_AXI_ADDR_WIDTH=0x000000100000001000000010000000100000001000000010000000100000001000000010,C_S_AXI_BASE_ID=0x00000000,C_S_AXI_THREAD_ID_WIDTH=0x00000000,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_M_AXI_WRITE_CONNECTIVITY=0x000000010000000100000001000000010000000100000001000000010000000100000001,C_M_AXI_READ_CONNECTIVITY=0x000000010000000100000001000000010000000100000001000000\ -010000000100000001,C_R_REGISTER=1,C_S_AXI_SINGLE_THREAD=0x00000001,C_S_AXI_WRITE_ACCEPTANCE=0x00000001,C_S_AXI_READ_ACCEPTANCE=0x00000001,C_M_AXI_WRITE_ISSUING=0x000000010000000100000001000000010000000100000001000000010000000100000001,C_M_AXI_READ_ISSUING=0x000000010000000100000001000000010000000100000001000000010000000100000001,C_S_AXI_ARB_PRIORITY=0x00000000,C_M_AXI_SECURE=0x000000000000000000000000000000000000000000000000000000000000000000000000,C_CONNECTIVITY_MODE=0}" *) +(* CORE_GENERATION_INFO = "Arty_Z7_20_xbar_0,axi_crossbar_v2_1_12_axi_crossbar,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_crossbar,x_ipVersion=2.1,x_ipCoreRevision=12,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_NUM_SLAVE_SLOTS=1,C_NUM_MASTER_SLOTS=11,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_PROTOCOL=2,C_NUM_ADDR_RANGES=1,C_M_AXI_BASE_ADDR=0x00000000412500000000000043c3000000000000412400000000000043c2000000000000412300000000000043c100000000000043c000000000\ +000043000000000000004122000000000000412100000000000041200000,C_M_AXI_ADDR_WIDTH=0x0000001000000010000000100000001000000010000000100000001000000010000000100000001000000010,C_S_AXI_BASE_ID=0x00000000,C_S_AXI_THREAD_ID_WIDTH=0x00000000,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_M_AXI_WRITE_CONNECTIVITY=0x0000000100000001000000010000000100000001000000010000000100000001000000010000000100000001,C_M_AXI_READ_CONN\ +ECTIVITY=0x0000000100000001000000010000000100000001000000010000000100000001000000010000000100000001,C_R_REGISTER=1,C_S_AXI_SINGLE_THREAD=0x00000001,C_S_AXI_WRITE_ACCEPTANCE=0x00000001,C_S_AXI_READ_ACCEPTANCE=0x00000001,C_M_AXI_WRITE_ISSUING=0x0000000100000001000000010000000100000001000000010000000100000001000000010000000100000001,C_M_AXI_READ_ISSUING=0x0000000100000001000000010000000100000001000000010000000100000001000000010000000100000001,C_S_AXI_ARB_PRIORITY=0x00000000,C_M_AXI_SECURE=0x0000000\ +000000000000000000000000000000000000000000000000000000000000000000000000000000000,C_CONNECTIVITY_MODE=0}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) module Arty_Z7_20_xbar_0 ( aclk, @@ -142,74 +143,74 @@ output wire [0 : 0] s_axi_rvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) input wire [0 : 0] s_axi_rready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI AWADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI AWADDR [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI AWADDR [31:0] [223:192], xilinx.com:interface:aximm:1.0 M07_AXI AWADDR [31:0] [255:22\ -4], xilinx.com:interface:aximm:1.0 M08_AXI AWADDR [31:0] [287:256]" *) -output wire [287 : 0] m_axi_awaddr; +4], xilinx.com:interface:aximm:1.0 M08_AXI AWADDR [31:0] [287:256], xilinx.com:interface:aximm:1.0 M09_AXI AWADDR [31:0] [319:288], xilinx.com:interface:aximm:1.0 M10_AXI AWADDR [31:0] [351:320]" *) +output wire [351 : 0] m_axi_awaddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI AWPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI AWPROT [2:0] [17:15], xilinx.com:interface:aximm:1.0 M06_AXI AWPROT [2:0] [20:18], xilinx.com:interface:aximm:1.0 M07_AXI AWPROT [2:0] [23:21], xilinx.com:interfac\ -e:aximm:1.0 M08_AXI AWPROT [2:0] [26:24]" *) -output wire [26 : 0] m_axi_awprot; +e:aximm:1.0 M08_AXI AWPROT [2:0] [26:24], xilinx.com:interface:aximm:1.0 M09_AXI AWPROT [2:0] [29:27], xilinx.com:interface:aximm:1.0 M10_AXI AWPROT [2:0] [32:30]" *) +output wire [32 : 0] m_axi_awprot; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI AWVALID [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI AWVALID [0:0] [7:7], xilinx.com:interface\ -:aximm:1.0 M08_AXI AWVALID [0:0] [8:8]" *) -output wire [8 : 0] m_axi_awvalid; +:aximm:1.0 M08_AXI AWVALID [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI AWVALID [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI AWVALID [0:0] [10:10]" *) +output wire [10 : 0] m_axi_awvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI AWREADY [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI AWREADY [0:0] [7:7], xilinx.com:interface\ -:aximm:1.0 M08_AXI AWREADY [0:0] [8:8]" *) -input wire [8 : 0] m_axi_awready; +:aximm:1.0 M08_AXI AWREADY [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI AWREADY [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI AWREADY [0:0] [10:10]" *) +input wire [10 : 0] m_axi_awready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI WDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI WDATA [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI WDATA [31:0] [223:192], xilinx.com:interface:aximm:1.0 M07_AXI WDATA [31:0] [255:224], xili\ -nx.com:interface:aximm:1.0 M08_AXI WDATA [31:0] [287:256]" *) -output wire [287 : 0] m_axi_wdata; +nx.com:interface:aximm:1.0 M08_AXI WDATA [31:0] [287:256], xilinx.com:interface:aximm:1.0 M09_AXI WDATA [31:0] [319:288], xilinx.com:interface:aximm:1.0 M10_AXI WDATA [31:0] [351:320]" *) +output wire [351 : 0] m_axi_wdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12], xilinx.com:interface:aximm:1.0 M04_AXI WSTRB [3:0] [19:16], xilinx.com:interface:aximm:1.0 M05_AXI WSTRB [3:0] [23:20], xilinx.com:interface:aximm:1.0 M06_AXI WSTRB [3:0] [27:24], xilinx.com:interface:aximm:1.0 M07_AXI WSTRB [3:0] [31:28], xilinx.com:interface:axim\ -m:1.0 M08_AXI WSTRB [3:0] [35:32]" *) -output wire [35 : 0] m_axi_wstrb; +m:1.0 M08_AXI WSTRB [3:0] [35:32], xilinx.com:interface:aximm:1.0 M09_AXI WSTRB [3:0] [39:36], xilinx.com:interface:aximm:1.0 M10_AXI WSTRB [3:0] [43:40]" *) +output wire [43 : 0] m_axi_wstrb; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI WVALID [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI WVALID [0:0] [7:7], xilinx.com:interface:aximm:1\ -.0 M08_AXI WVALID [0:0] [8:8]" *) -output wire [8 : 0] m_axi_wvalid; +.0 M08_AXI WVALID [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI WVALID [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI WVALID [0:0] [10:10]" *) +output wire [10 : 0] m_axi_wvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI WREADY [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI WREADY [0:0] [7:7], xilinx.com:interface:aximm:1\ -.0 M08_AXI WREADY [0:0] [8:8]" *) -input wire [8 : 0] m_axi_wready; +.0 M08_AXI WREADY [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI WREADY [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI WREADY [0:0] [10:10]" *) +input wire [10 : 0] m_axi_wready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI BRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI BRESP [1:0] [11:10], xilinx.com:interface:aximm:1.0 M06_AXI BRESP [1:0] [13:12], xilinx.com:interface:aximm:1.0 M07_AXI BRESP [1:0] [15:14], xilinx.com:interface:aximm:1.0\ - M08_AXI BRESP [1:0] [17:16]" *) -input wire [17 : 0] m_axi_bresp; + M08_AXI BRESP [1:0] [17:16], xilinx.com:interface:aximm:1.0 M09_AXI BRESP [1:0] [19:18], xilinx.com:interface:aximm:1.0 M10_AXI BRESP [1:0] [21:20]" *) +input wire [21 : 0] m_axi_bresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI BVALID [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI BVALID [0:0] [7:7], xilinx.com:interface:aximm:1\ -.0 M08_AXI BVALID [0:0] [8:8]" *) -input wire [8 : 0] m_axi_bvalid; +.0 M08_AXI BVALID [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI BVALID [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI BVALID [0:0] [10:10]" *) +input wire [10 : 0] m_axi_bvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI BREADY [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI BREADY [0:0] [7:7], xilinx.com:interface:aximm:1\ -.0 M08_AXI BREADY [0:0] [8:8]" *) -output wire [8 : 0] m_axi_bready; +.0 M08_AXI BREADY [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI BREADY [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI BREADY [0:0] [10:10]" *) +output wire [10 : 0] m_axi_bready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI ARADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI ARADDR [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI ARADDR [31:0] [223:192], xilinx.com:interface:aximm:1.0 M07_AXI ARADDR [31:0] [255:22\ -4], xilinx.com:interface:aximm:1.0 M08_AXI ARADDR [31:0] [287:256]" *) -output wire [287 : 0] m_axi_araddr; +4], xilinx.com:interface:aximm:1.0 M08_AXI ARADDR [31:0] [287:256], xilinx.com:interface:aximm:1.0 M09_AXI ARADDR [31:0] [319:288], xilinx.com:interface:aximm:1.0 M10_AXI ARADDR [31:0] [351:320]" *) +output wire [351 : 0] m_axi_araddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI ARPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI ARPROT [2:0] [17:15], xilinx.com:interface:aximm:1.0 M06_AXI ARPROT [2:0] [20:18], xilinx.com:interface:aximm:1.0 M07_AXI ARPROT [2:0] [23:21], xilinx.com:interfac\ -e:aximm:1.0 M08_AXI ARPROT [2:0] [26:24]" *) -output wire [26 : 0] m_axi_arprot; +e:aximm:1.0 M08_AXI ARPROT [2:0] [26:24], xilinx.com:interface:aximm:1.0 M09_AXI ARPROT [2:0] [29:27], xilinx.com:interface:aximm:1.0 M10_AXI ARPROT [2:0] [32:30]" *) +output wire [32 : 0] m_axi_arprot; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI ARVALID [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI ARVALID [0:0] [7:7], xilinx.com:interface\ -:aximm:1.0 M08_AXI ARVALID [0:0] [8:8]" *) -output wire [8 : 0] m_axi_arvalid; +:aximm:1.0 M08_AXI ARVALID [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI ARVALID [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI ARVALID [0:0] [10:10]" *) +output wire [10 : 0] m_axi_arvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI ARREADY [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI ARREADY [0:0] [7:7], xilinx.com:interface\ -:aximm:1.0 M08_AXI ARREADY [0:0] [8:8]" *) -input wire [8 : 0] m_axi_arready; +:aximm:1.0 M08_AXI ARREADY [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI ARREADY [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI ARREADY [0:0] [10:10]" *) +input wire [10 : 0] m_axi_arready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI RDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI RDATA [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI RDATA [31:0] [223:192], xilinx.com:interface:aximm:1.0 M07_AXI RDATA [31:0] [255:224], xili\ -nx.com:interface:aximm:1.0 M08_AXI RDATA [31:0] [287:256]" *) -input wire [287 : 0] m_axi_rdata; +nx.com:interface:aximm:1.0 M08_AXI RDATA [31:0] [287:256], xilinx.com:interface:aximm:1.0 M09_AXI RDATA [31:0] [319:288], xilinx.com:interface:aximm:1.0 M10_AXI RDATA [31:0] [351:320]" *) +input wire [351 : 0] m_axi_rdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI RRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI RRESP [1:0] [11:10], xilinx.com:interface:aximm:1.0 M06_AXI RRESP [1:0] [13:12], xilinx.com:interface:aximm:1.0 M07_AXI RRESP [1:0] [15:14], xilinx.com:interface:aximm:1.0\ - M08_AXI RRESP [1:0] [17:16]" *) -input wire [17 : 0] m_axi_rresp; + M08_AXI RRESP [1:0] [17:16], xilinx.com:interface:aximm:1.0 M09_AXI RRESP [1:0] [19:18], xilinx.com:interface:aximm:1.0 M10_AXI RRESP [1:0] [21:20]" *) +input wire [21 : 0] m_axi_rresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI RVALID [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI RVALID [0:0] [7:7], xilinx.com:interface:aximm:1\ -.0 M08_AXI RVALID [0:0] [8:8]" *) -input wire [8 : 0] m_axi_rvalid; +.0 M08_AXI RVALID [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI RVALID [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI RVALID [0:0] [10:10]" *) +input wire [10 : 0] m_axi_rvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI RREADY [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI RREADY [0:0] [7:7], xilinx.com:interface:aximm:1\ -.0 M08_AXI RREADY [0:0] [8:8]" *) -output wire [8 : 0] m_axi_rready; +.0 M08_AXI RREADY [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI RREADY [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI RREADY [0:0] [10:10]" *) +output wire [10 : 0] m_axi_rready; axi_crossbar_v2_1_12_axi_crossbar #( .C_FAMILY("zynq"), .C_NUM_SLAVE_SLOTS(1), - .C_NUM_MASTER_SLOTS(9), + .C_NUM_MASTER_SLOTS(11), .C_AXI_ID_WIDTH(1), .C_AXI_ADDR_WIDTH(32), .C_AXI_DATA_WIDTH(32), .C_AXI_PROTOCOL(2), .C_NUM_ADDR_RANGES(1), - .C_M_AXI_BASE_ADDR(576'H00000000412400000000000043c2000000000000412300000000000043c100000000000043c000000000000043000000000000004122000000000000412100000000000041200000), - .C_M_AXI_ADDR_WIDTH(288'H000000100000001000000010000000100000001000000010000000100000001000000010), + .C_M_AXI_BASE_ADDR(704'H00000000412500000000000043c3000000000000412400000000000043c2000000000000412300000000000043c100000000000043c000000000000043000000000000004122000000000000412100000000000041200000), + .C_M_AXI_ADDR_WIDTH(352'H0000001000000010000000100000001000000010000000100000001000000010000000100000001000000010), .C_S_AXI_BASE_ID(32'H00000000), .C_S_AXI_THREAD_ID_WIDTH(32'H00000000), .C_AXI_SUPPORTS_USER_SIGNALS(0), @@ -218,16 +219,16 @@ output wire [8 : 0] m_axi_rready; .C_AXI_WUSER_WIDTH(1), .C_AXI_RUSER_WIDTH(1), .C_AXI_BUSER_WIDTH(1), - .C_M_AXI_WRITE_CONNECTIVITY(288'H000000010000000100000001000000010000000100000001000000010000000100000001), - .C_M_AXI_READ_CONNECTIVITY(288'H000000010000000100000001000000010000000100000001000000010000000100000001), + .C_M_AXI_WRITE_CONNECTIVITY(352'H0000000100000001000000010000000100000001000000010000000100000001000000010000000100000001), + .C_M_AXI_READ_CONNECTIVITY(352'H0000000100000001000000010000000100000001000000010000000100000001000000010000000100000001), .C_R_REGISTER(1), .C_S_AXI_SINGLE_THREAD(32'H00000001), .C_S_AXI_WRITE_ACCEPTANCE(32'H00000001), .C_S_AXI_READ_ACCEPTANCE(32'H00000001), - .C_M_AXI_WRITE_ISSUING(288'H000000010000000100000001000000010000000100000001000000010000000100000001), - .C_M_AXI_READ_ISSUING(288'H000000010000000100000001000000010000000100000001000000010000000100000001), + .C_M_AXI_WRITE_ISSUING(352'H0000000100000001000000010000000100000001000000010000000100000001000000010000000100000001), + .C_M_AXI_READ_ISSUING(352'H0000000100000001000000010000000100000001000000010000000100000001000000010000000100000001), .C_S_AXI_ARB_PRIORITY(32'H00000000), - .C_M_AXI_SECURE(288'H000000000000000000000000000000000000000000000000000000000000000000000000), + .C_M_AXI_SECURE(352'H0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .C_CONNECTIVITY_MODE(0) ) inst ( .aclk(aclk), @@ -295,9 +296,9 @@ output wire [8 : 0] m_axi_rready; .m_axi_wuser(), .m_axi_wvalid(m_axi_wvalid), .m_axi_wready(m_axi_wready), - .m_axi_bid(9'H000), + .m_axi_bid(11'H000), .m_axi_bresp(m_axi_bresp), - .m_axi_buser(9'H000), + .m_axi_buser(11'H000), .m_axi_bvalid(m_axi_bvalid), .m_axi_bready(m_axi_bready), .m_axi_arid(), @@ -313,11 +314,11 @@ output wire [8 : 0] m_axi_rready; .m_axi_aruser(), .m_axi_arvalid(m_axi_arvalid), .m_axi_arready(m_axi_arready), - .m_axi_rid(9'H000), + .m_axi_rid(11'H000), .m_axi_rdata(m_axi_rdata), .m_axi_rresp(m_axi_rresp), - .m_axi_rlast(9'H1FF), - .m_axi_ruser(9'H000), + .m_axi_rlast(11'H7FF), + .m_axi_ruser(11'H000), .m_axi_rvalid(m_axi_rvalid), .m_axi_rready(m_axi_rready) ); diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_1/Arty_Z7_20_xbar_1.dcp b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_1/Arty_Z7_20_xbar_1.dcp new file mode 100644 index 0000000..a1e21d4 Binary files /dev/null and b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_1/Arty_Z7_20_xbar_1.dcp differ diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_1/Arty_Z7_20_xbar_1.xci b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_1/Arty_Z7_20_xbar_1.xci new file mode 100644 index 0000000..9b7e017 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_1/Arty_Z7_20_xbar_1.xci @@ -0,0 +1,1592 @@ + + + xilinx.com + xci + unknown + 1.0 + + + Arty_Z7_20_xbar_1 + + + M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI + ARESETN + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 + 118181816 + 0.000 + 32 + 0 + 0 + 0 + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 + 64 + 118181816 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 32 + 8 + 1 + 8 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 256 + 2 + 1 + 2 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + ACTIVE_LOW + INTERCONNECT + 32 + 0 + 0 + 0 + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 + 64 + 118181816 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 256 + 2 + 1 + 8 + 1 + 0.000 + AXI4 + READ_ONLY + 0 + 0 + 1 + 0 + 0 + 32 + 0 + 0 + 0 + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 + 64 + 118181816 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 256 + 2 + 1 + 2 + 1 + 0.000 + AXI4 + WRITE_ONLY + 0 + 0 + 1 + 0 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 0 + 1 + 0 + 1 + 1 + zynq + 0x0000001d + 0x0000000000000000 + 0x00000001 + 0x00000008 + 0x00000000 + 0x00000002 + 0x00000008 + 1 + 1 + 2 + 0 + 0x0000000000000000 + 0x0000000100000000 + 0x0000000200000002 + 0x0000000000000000 + 0x0000000000000000 + 0x0000000200000002 + 1 + 32 + 0 + 0 + 0 + SAMD + Arty_Z7_20_xbar_1 + 64 + 1 + 29 + 0x0000000000000000 + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 8 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 8 + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 4 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 4 + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 4 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 4 + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 4 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 4 + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 4 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 4 + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 4 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 4 + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 4 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 4 + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 4 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 4 + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 4 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 4 + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 4 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 4 + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 4 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 4 + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 4 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 4 + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 4 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 4 + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 4 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 4 + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 4 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 4 + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 0xffffffffffffffff + 0 + 4 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 4 + 1 + 2 + AXI4 + 0 + 0 + 0 + 0x00000000 + 2 + 0 + 0 + 2 + 0 + 0x00000001 + 2 + 0 + 0 + 2 + 0 + 0x00000002 + 2 + 0 + 0 + 2 + 0 + 0x00000003 + 2 + 0 + 0 + 2 + 0 + 0x00000004 + 2 + 0 + 0 + 2 + 0 + 0x00000005 + 2 + 0 + 0 + 2 + 0 + 0x00000006 + 2 + 0 + 0 + 2 + 0 + 0x00000007 + 2 + 0 + 0 + 2 + 0 + 0x00000008 + 2 + 0 + 0 + 2 + 0 + 0x00000009 + 2 + 0 + 0 + 2 + 0 + 0x0000000a + 2 + 0 + 0 + 2 + 0 + 0x0000000b + 2 + 0 + 0 + 2 + 0 + 0x0000000c + 2 + 0 + 0 + 2 + 0 + 0x0000000d + 2 + 0 + 0 + 2 + 0 + 0x0000000e + 2 + 0 + 0 + 2 + 0 + 0x0000000f + 2 + 0 + 0 + 2 + 0 + 0 + zynq + digilentinc.com:arty-z7-20:part0:1.0 + xc7z020 + clg400 + VHDL + + MIXED + -1 + + TRUE + TRUE + 24c1bb45055188db + IP_Integrator + 12 + TRUE + . + + ../../ipshared + 2016.4 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_1/Arty_Z7_20_xbar_1.xml b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_1/Arty_Z7_20_xbar_1.xml new file mode 100644 index 0000000..3bca688 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_1/Arty_Z7_20_xbar_1.xml @@ -0,0 +1,35237 @@ + + + xilinx.com + customized_ip + Arty_Z7_20_xbar_1 + 1.0 + + + RSTIF + RSTIF + + + + + + + RST + + + aresetn + + + + + + POLARITY + ACTIVE_LOW + + + TYPE + INTERCONNECT + + + + + CLKIF + CLKIF + + + + + + + CLK + + + aclk + + + + + + FREQ_HZ + aclk frequency + aclk frequency + 118181816 + + + PHASE + 0.000 + + + CLK_DOMAIN + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 + + + ASSOCIATED_BUSIF + M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI + + + ASSOCIATED_RESET + ARESETN + + + + + S00_AXI + S00_AXI + + + + + + + AWID + + + s_axi_awid + + 0 + 0 + + + + + + AWADDR + + + s_axi_awaddr + + 31 + 0 + + + + + + AWLEN + + + s_axi_awlen + + 7 + 0 + + + + + + AWSIZE + + + s_axi_awsize + + 2 + 0 + + + + + + AWBURST + + + s_axi_awburst + + 1 + 0 + + + + + + AWLOCK + + + s_axi_awlock + + 0 + 0 + + + + + + AWCACHE + + + s_axi_awcache + + 3 + 0 + + + + + + AWPROT + + + s_axi_awprot + + 2 + 0 + + + + + + AWQOS + + + s_axi_awqos + + 3 + 0 + + + + + + AWUSER + + + s_axi_awuser + + 0 + 0 + + + + + + AWVALID + + + s_axi_awvalid + + 0 + 0 + + + + + + AWREADY + + + s_axi_awready + + 0 + 0 + + + + + + WID + + + s_axi_wid + + 0 + 0 + + + + + + WDATA + + + s_axi_wdata + + 63 + 0 + + + + + + WSTRB + + + s_axi_wstrb + + 7 + 0 + + + + + + WLAST + + + s_axi_wlast + + 0 + 0 + + + + + + WUSER + + + s_axi_wuser + + 0 + 0 + + + + + + WVALID + + + s_axi_wvalid + + 0 + 0 + + + + + + WREADY + + + s_axi_wready + + 0 + 0 + + + + + + BID + + + s_axi_bid + + 0 + 0 + + + + + + BRESP + + + s_axi_bresp + + 1 + 0 + + + + + + BUSER + + + s_axi_buser + + 0 + 0 + + + + + + BVALID + + + s_axi_bvalid + + 0 + 0 + + + + + + BREADY + + + s_axi_bready + + 0 + 0 + + + + + + ARID + + + s_axi_arid + + 0 + 0 + + + + + + ARADDR + + + s_axi_araddr + + 31 + 0 + + + + + + ARLEN + + + s_axi_arlen + + 7 + 0 + + + + + + ARSIZE + + + s_axi_arsize + + 2 + 0 + + + + + + ARBURST + + + s_axi_arburst + + 1 + 0 + + + + + + ARLOCK + + + s_axi_arlock + + 0 + 0 + + + + + + ARCACHE + + + s_axi_arcache + + 3 + 0 + + + + + + ARPROT + + + s_axi_arprot + + 2 + 0 + + + + + + ARQOS + + + s_axi_arqos + + 3 + 0 + + + + + + ARUSER + + + s_axi_aruser + + 0 + 0 + + + + + + ARVALID + + + s_axi_arvalid + + 0 + 0 + + + + + + ARREADY + + + s_axi_arready + + 0 + 0 + + + + + + RID + + + s_axi_rid + + 0 + 0 + + + + + + RDATA + + + s_axi_rdata + + 63 + 0 + + + + + + RRESP + + + s_axi_rresp + + 1 + 0 + + + + + + RLAST + + + s_axi_rlast + + 0 + 0 + + + + + + RUSER + + + s_axi_ruser + + 0 + 0 + + + + + + RVALID + + + s_axi_rvalid + + 0 + 0 + + + + + + RREADY + + + s_axi_rready + + 0 + 0 + + + + + + + DATA_WIDTH + 64 + + + PROTOCOL + AXI4 + + + FREQ_HZ + 118181816 + + + ID_WIDTH + 1 + + + ADDR_WIDTH + 32 + + + AWUSER_WIDTH + 0 + + + ARUSER_WIDTH + 0 + + + WUSER_WIDTH + 0 + + + RUSER_WIDTH + 0 + + + BUSER_WIDTH + 0 + + + READ_WRITE_MODE + READ_ONLY + + + HAS_BURST + 1 + + + HAS_LOCK + 1 + + + HAS_PROT + 1 + + + HAS_CACHE + 1 + + + HAS_QOS + 1 + + + HAS_REGION + 0 + + + HAS_WSTRB + 1 + + + HAS_BRESP + 1 + + + HAS_RRESP + 1 + + + SUPPORTS_NARROW_BURST + 1 + + + NUM_READ_OUTSTANDING + 2 + + + NUM_WRITE_OUTSTANDING + 8 + + + MAX_BURST_LENGTH + 256 + + + PHASE + 0.000 + + + CLK_DOMAIN + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 + + + NUM_READ_THREADS + 1 + + + NUM_WRITE_THREADS + 1 + + + RUSER_BITS_PER_BYTE + 0 + + + WUSER_BITS_PER_BYTE + 0 + + + + + + true + + + + + + M00_AXI + M00_AXI + + + + + + + AWID + + + m_axi_awid + + 0 + 0 + + + + + + AWADDR + + + m_axi_awaddr + + 31 + 0 + + + + + + AWLEN + + + m_axi_awlen + + 7 + 0 + + + + + + AWSIZE + + + m_axi_awsize + + 2 + 0 + + + + + + AWBURST + + + m_axi_awburst + + 1 + 0 + + + + + + AWLOCK + + + m_axi_awlock + + 0 + 0 + + + + + + AWCACHE + + + m_axi_awcache + + 3 + 0 + + + + + + AWPROT + + + m_axi_awprot + + 2 + 0 + + + + + + AWREGION + + + m_axi_awregion + + 3 + 0 + + + + + + AWQOS + + + m_axi_awqos + + 3 + 0 + + + + + + AWUSER + + + m_axi_awuser + + 0 + 0 + + + + + + AWVALID + + + m_axi_awvalid + + 0 + 0 + + + + + + AWREADY + + + m_axi_awready + + 0 + 0 + + + + + + WID + + + m_axi_wid + + 0 + 0 + + + + + + WDATA + + + m_axi_wdata + + 63 + 0 + + + + + + WSTRB + + + m_axi_wstrb + + 7 + 0 + + + + + + WLAST + + + m_axi_wlast + + 0 + 0 + + + + + + WUSER + + + m_axi_wuser + + 0 + 0 + + + + + + WVALID + + + m_axi_wvalid + + 0 + 0 + + + + + + WREADY + + + m_axi_wready + + 0 + 0 + + + + + + BID + + + m_axi_bid + + 0 + 0 + + + + + + BRESP + + + m_axi_bresp + + 1 + 0 + + + + + + BUSER + + + m_axi_buser + + 0 + 0 + + + + + + BVALID + + + m_axi_bvalid + + 0 + 0 + + + + + + BREADY + + + m_axi_bready + + 0 + 0 + + + + + + ARID + + + m_axi_arid + + 0 + 0 + + + + + + ARADDR + + + m_axi_araddr + + 31 + 0 + + + + + + ARLEN + + + m_axi_arlen + + 7 + 0 + + + + + + ARSIZE + + + m_axi_arsize + + 2 + 0 + + + + + + ARBURST + + + m_axi_arburst + + 1 + 0 + + + + + + ARLOCK + + + m_axi_arlock + + 0 + 0 + + + + + + ARCACHE + + + m_axi_arcache + + 3 + 0 + + + + + + ARPROT + + + m_axi_arprot + + 2 + 0 + + + + + + ARREGION + + + m_axi_arregion + + 3 + 0 + + + + + + ARQOS + + + m_axi_arqos + + 3 + 0 + + + + + + ARUSER + + + m_axi_aruser + + 0 + 0 + + + + + + ARVALID + + + m_axi_arvalid + + 0 + 0 + + + + + + ARREADY + + + m_axi_arready + + 0 + 0 + + + + + + RID + + + m_axi_rid + + 0 + 0 + + + + + + RDATA + + + m_axi_rdata + + 63 + 0 + + + + + + RRESP + + + m_axi_rresp + + 1 + 0 + + + + + + RLAST + + + m_axi_rlast + + 0 + 0 + + + + + + RUSER + + + m_axi_ruser + + 0 + 0 + + + + + + RVALID + + + m_axi_rvalid + + 0 + 0 + + + + + + RREADY + + + m_axi_rready + + 0 + 0 + + + + + + + DATA_WIDTH + 64 + + + PROTOCOL + AXI4 + + + FREQ_HZ + 118181816 + + + ID_WIDTH + 1 + + + ADDR_WIDTH + 32 + + + AWUSER_WIDTH + 0 + + + ARUSER_WIDTH + 0 + + + WUSER_WIDTH + 0 + + + RUSER_WIDTH + 0 + + + BUSER_WIDTH + 0 + + + READ_WRITE_MODE + READ_WRITE + + + HAS_BURST + 0 + + + HAS_LOCK + 0 + + + HAS_PROT + 1 + + + HAS_CACHE + 0 + + + HAS_QOS + 0 + + + HAS_REGION + 0 + + + HAS_WSTRB + 1 + + + HAS_BRESP + 1 + + + HAS_RRESP + 1 + + + SUPPORTS_NARROW_BURST + 0 + + + NUM_READ_OUTSTANDING + 8 + + + NUM_WRITE_OUTSTANDING + 8 + + + MAX_BURST_LENGTH + 32 + + + PHASE + 0.000 + + + CLK_DOMAIN + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 + + + NUM_READ_THREADS + 1 + + + NUM_WRITE_THREADS + 1 + + + RUSER_BITS_PER_BYTE + 0 + + + WUSER_BITS_PER_BYTE + 0 + + + + + + true + + + + + + S01_AXI + S01_AXI + + + + + + + AWID + + + s_axi_awid + + 1 + 1 + + + + + + AWADDR + + + s_axi_awaddr + + 63 + 32 + + + + + + AWLEN + + + s_axi_awlen + + 15 + 8 + + + + + + AWSIZE + + + s_axi_awsize + + 5 + 3 + + + + + + AWBURST + + + s_axi_awburst + + 3 + 2 + + + + + + AWLOCK + + + s_axi_awlock + + 1 + 1 + + + + + + AWCACHE + + + s_axi_awcache + + 7 + 4 + + + + + + AWPROT + + + s_axi_awprot + + 5 + 3 + + + + + + AWQOS + + + s_axi_awqos + + 7 + 4 + + + + + + AWUSER + + + s_axi_awuser + + 1 + 1 + + + + + + AWVALID + + + s_axi_awvalid + + 1 + 1 + + + + + + AWREADY + + + s_axi_awready + + 1 + 1 + + + + + + WID + + + s_axi_wid + + 1 + 1 + + + + + + WDATA + + + s_axi_wdata + + 127 + 64 + + + + + + WSTRB + + + s_axi_wstrb + + 15 + 8 + + + + + + WLAST + + + s_axi_wlast + + 1 + 1 + + + + + + WUSER + + + s_axi_wuser + + 1 + 1 + + + + + + WVALID + + + s_axi_wvalid + + 1 + 1 + + + + + + WREADY + + + s_axi_wready + + 1 + 1 + + + + + + BID + + + s_axi_bid + + 1 + 1 + + + + + + BRESP + + + s_axi_bresp + + 3 + 2 + + + + + + BUSER + + + s_axi_buser + + 1 + 1 + + + + + + BVALID + + + s_axi_bvalid + + 1 + 1 + + + + + + BREADY + + + s_axi_bready + + 1 + 1 + + + + + + ARID + + + s_axi_arid + + 1 + 1 + + + + + + ARADDR + + + s_axi_araddr + + 63 + 32 + + + + + + ARLEN + + + s_axi_arlen + + 15 + 8 + + + + + + ARSIZE + + + s_axi_arsize + + 5 + 3 + + + + + + ARBURST + + + s_axi_arburst + + 3 + 2 + + + + + + ARLOCK + + + s_axi_arlock + + 1 + 1 + + + + + + ARCACHE + + + s_axi_arcache + + 7 + 4 + + + + + + ARPROT + + + s_axi_arprot + + 5 + 3 + + + + + + ARQOS + + + s_axi_arqos + + 7 + 4 + + + + + + ARUSER + + + s_axi_aruser + + 1 + 1 + + + + + + ARVALID + + + s_axi_arvalid + + 1 + 1 + + + + + + ARREADY + + + s_axi_arready + + 1 + 1 + + + + + + RID + + + s_axi_rid + + 1 + 1 + + + + + + RDATA + + + s_axi_rdata + + 127 + 64 + + + + + + RRESP + + + s_axi_rresp + + 3 + 2 + + + + + + RLAST + + + s_axi_rlast + + 1 + 1 + + + + + + RUSER + + + s_axi_ruser + + 1 + 1 + + + + + + RVALID + + + s_axi_rvalid + + 1 + 1 + + + + + + RREADY + + + s_axi_rready + + 1 + 1 + + + + + + + DATA_WIDTH + 64 + + + PROTOCOL + AXI4 + + + FREQ_HZ + 118181816 + + + ID_WIDTH + 1 + + + ADDR_WIDTH + 32 + + + AWUSER_WIDTH + 0 + + + ARUSER_WIDTH + 0 + + + WUSER_WIDTH + 0 + + + RUSER_WIDTH + 0 + + + BUSER_WIDTH + 0 + + + READ_WRITE_MODE + WRITE_ONLY + + + HAS_BURST + 1 + + + HAS_LOCK + 1 + + + HAS_PROT + 1 + + + HAS_CACHE + 1 + + + HAS_QOS + 1 + + + HAS_REGION + 0 + + + HAS_WSTRB + 1 + + + HAS_BRESP + 1 + + + HAS_RRESP + 1 + + + SUPPORTS_NARROW_BURST + 1 + + + NUM_READ_OUTSTANDING + 2 + + + NUM_WRITE_OUTSTANDING + 2 + + + MAX_BURST_LENGTH + 256 + + + PHASE + 0.000 + + + CLK_DOMAIN + Arty_Z7_20_processing_system7_0_0_FCLK_CLK1 + + + NUM_READ_THREADS + 1 + + + NUM_WRITE_THREADS + 1 + + + RUSER_BITS_PER_BYTE + 0 + + + WUSER_BITS_PER_BYTE + 0 + + + + + + true + + + + + + M01_AXI + M01_AXI + + + + + + + AWID + + + m_axi_awid + + 1 + 1 + + + + + + AWADDR + + + m_axi_awaddr + + 63 + 32 + + + + + + AWLEN + + + m_axi_awlen + + 15 + 8 + + + + + + AWSIZE + + + m_axi_awsize + + 5 + 3 + + + + + + AWBURST + + + m_axi_awburst + + 3 + 2 + + + + + + AWLOCK + + + m_axi_awlock + + 1 + 1 + + + + + + AWCACHE + + + m_axi_awcache + + 7 + 4 + + + + + + AWPROT + + + m_axi_awprot + + 5 + 3 + + + + + + AWREGION + + + m_axi_awregion + + 7 + 4 + + + + + + AWQOS + + + m_axi_awqos + + 7 + 4 + + + + + + AWUSER + + + m_axi_awuser + + 1 + 1 + + + + + + AWVALID + + + m_axi_awvalid + + 1 + 1 + + + + + + AWREADY + + + m_axi_awready + + 1 + 1 + + + + + + WID + + + m_axi_wid + + 1 + 1 + + + + + + WDATA + + + m_axi_wdata + + 127 + 64 + + + + + + WSTRB + + + m_axi_wstrb + + 15 + 8 + + + + + + WLAST + + + m_axi_wlast + + 1 + 1 + + + + + + WUSER + + + m_axi_wuser + + 1 + 1 + + + + + + WVALID + + + m_axi_wvalid + + 1 + 1 + + + + + + WREADY + + + m_axi_wready + + 1 + 1 + + + + + + BID + + + m_axi_bid + + 1 + 1 + + + + + + BRESP + + + m_axi_bresp + + 3 + 2 + + + + + + BUSER + + + m_axi_buser + + 1 + 1 + + + + + + BVALID + + + m_axi_bvalid + + 1 + 1 + + + + + + BREADY + + + m_axi_bready + + 1 + 1 + + + + + + ARID + + + m_axi_arid + + 1 + 1 + + + + + + ARADDR + + + m_axi_araddr + + 63 + 32 + + + + + + ARLEN + + + m_axi_arlen + + 15 + 8 + + + + + + ARSIZE + + + m_axi_arsize + + 5 + 3 + + + + + + ARBURST + + + m_axi_arburst + + 3 + 2 + + + + + + ARLOCK + + + m_axi_arlock + + 1 + 1 + + + + + + ARCACHE + + + m_axi_arcache + + 7 + 4 + + + + + + ARPROT + + + m_axi_arprot + + 5 + 3 + + + + + + ARREGION + + + m_axi_arregion + + 7 + 4 + + + + + + ARQOS + + + m_axi_arqos + + 7 + 4 + + + + + + ARUSER + + + m_axi_aruser + + 1 + 1 + + + + + + ARVALID + + + m_axi_arvalid + + 1 + 1 + + + + + + ARREADY + + + m_axi_arready + + 1 + 1 + + + + + + RID + + + m_axi_rid + + 1 + 1 + + + + + + RDATA + + + m_axi_rdata + + 127 + 64 + + + + + + RRESP + + + m_axi_rresp + + 3 + 2 + + + + + + RLAST + + + m_axi_rlast + + 1 + 1 + + + + + + RUSER + + + m_axi_ruser + + 1 + 1 + + + + + + RVALID + + + m_axi_rvalid + + 1 + 1 + + + + + + RREADY + + + m_axi_rready + + 1 + 1 + + + + + + + DATA_WIDTH + 32 + + + PROTOCOL + AXI4 + + + FREQ_HZ + 100000000 + + + ID_WIDTH + 1 + + + ADDR_WIDTH + 32 + + + AWUSER_WIDTH + 0 + + + ARUSER_WIDTH + 0 + + + WUSER_WIDTH + 0 + + + RUSER_WIDTH + 0 + + + BUSER_WIDTH + 0 + + + READ_WRITE_MODE + READ_WRITE + + + HAS_BURST + 1 + + + HAS_LOCK + 1 + + + HAS_PROT + 1 + + + HAS_CACHE + 1 + + + HAS_QOS + 1 + + + HAS_REGION + 1 + + + HAS_WSTRB + 1 + + + HAS_BRESP + 1 + + + HAS_RRESP + 1 + + + SUPPORTS_NARROW_BURST + 1 + + + NUM_READ_OUTSTANDING + 2 + + + NUM_WRITE_OUTSTANDING + 2 + + + MAX_BURST_LENGTH + 256 + + + PHASE + 0.000 + + + CLK_DOMAIN + + + + NUM_READ_THREADS + 1 + + + NUM_WRITE_THREADS + 1 + + + RUSER_BITS_PER_BYTE + 0 + + + WUSER_BITS_PER_BYTE + 0 + + + + + + false + + + + + + S02_AXI + S02_AXI + + + + + + + AWID + + + s_axi_awid + + 2 + 2 + + + + + + AWADDR + + + s_axi_awaddr + + 95 + 64 + + + + + + AWLEN + + + s_axi_awlen + + 23 + 16 + + + + + + AWSIZE + + + s_axi_awsize + + 8 + 6 + + + + + + AWBURST + + + s_axi_awburst + + 5 + 4 + + + + + + AWLOCK + + + s_axi_awlock + + 2 + 2 + + + + + + AWCACHE + + + s_axi_awcache + + 11 + 8 + + + + + + AWPROT + + + s_axi_awprot + + 8 + 6 + + + + + + AWQOS + + + s_axi_awqos + + 11 + 8 + + + + + + AWUSER + + + s_axi_awuser + + 2 + 2 + + + + + + AWVALID + + + s_axi_awvalid + + 2 + 2 + + + + + + AWREADY + + + s_axi_awready + + 2 + 2 + + + + + + WID + + + s_axi_wid + + 2 + 2 + + + + + + WDATA + + + s_axi_wdata + + 191 + 128 + + + + + + WSTRB + + + s_axi_wstrb + + 23 + 16 + + + + + + WLAST + + + s_axi_wlast + + 2 + 2 + + + + + + WUSER + + + s_axi_wuser + + 2 + 2 + + + + + + WVALID + + + s_axi_wvalid + + 2 + 2 + + + + + + WREADY + + + s_axi_wready + + 2 + 2 + + + + + + BID + + + s_axi_bid + + 2 + 2 + + + + + + BRESP + + + s_axi_bresp + + 5 + 4 + + + + + + BUSER + + + s_axi_buser + + 2 + 2 + + + + + + BVALID + + + s_axi_bvalid + + 2 + 2 + + + + + + BREADY + + + s_axi_bready + + 2 + 2 + + + + + + ARID + + + s_axi_arid + + 2 + 2 + + + + + + ARADDR + + + s_axi_araddr + + 95 + 64 + + + + + + ARLEN + + + s_axi_arlen + + 23 + 16 + + + + + + ARSIZE + + + s_axi_arsize + + 8 + 6 + + + + + + ARBURST + + + s_axi_arburst + + 5 + 4 + + + + + + ARLOCK + + + s_axi_arlock + + 2 + 2 + + + + + + ARCACHE + + + s_axi_arcache + + 11 + 8 + + + + + + ARPROT + + + s_axi_arprot + + 8 + 6 + + + + + + ARQOS + + + s_axi_arqos + + 11 + 8 + + + + + + ARUSER + + + s_axi_aruser + + 2 + 2 + + + + + + ARVALID + + + s_axi_arvalid + + 2 + 2 + + + + + + ARREADY + + + s_axi_arready + + 2 + 2 + + + + + + RID + + + s_axi_rid + + 2 + 2 + + + + + + RDATA + + + s_axi_rdata + + 191 + 128 + + + + + + RRESP + + + s_axi_rresp + + 5 + 4 + + + + + + RLAST + + + s_axi_rlast + + 2 + 2 + + + + + + RUSER + + + s_axi_ruser + + 2 + 2 + + + + + + RVALID + + + s_axi_rvalid + + 2 + 2 + + + + + + RREADY + + + s_axi_rready + + 2 + 2 + + + + + + + + false + + + + + + M02_AXI + M02_AXI + + + + + + + AWID + + + m_axi_awid + + 2 + 2 + + + + + + AWADDR + + + m_axi_awaddr + + 95 + 64 + + + + + + AWLEN + + + m_axi_awlen + + 23 + 16 + + + + + + AWSIZE + + + m_axi_awsize + + 8 + 6 + + + + + + AWBURST + + + m_axi_awburst + + 5 + 4 + + + + + + AWLOCK + + + m_axi_awlock + + 2 + 2 + + + + + + AWCACHE + + + m_axi_awcache + + 11 + 8 + + + + + + AWPROT + + + m_axi_awprot + + 8 + 6 + + + + + + AWREGION + + + m_axi_awregion + + 11 + 8 + + + + + + AWQOS + + + m_axi_awqos + + 11 + 8 + + + + + + AWUSER + + + m_axi_awuser + + 2 + 2 + + + + + + AWVALID + + + m_axi_awvalid + + 2 + 2 + + + + + + AWREADY + + + m_axi_awready + + 2 + 2 + + + + + + WID + + + m_axi_wid + + 2 + 2 + + + + + + WDATA + + + m_axi_wdata + + 191 + 128 + + + + + + WSTRB + + + m_axi_wstrb + + 23 + 16 + + + + + + WLAST + + + m_axi_wlast + + 2 + 2 + + + + + + WUSER + + + m_axi_wuser + + 2 + 2 + + + + + + WVALID + + + m_axi_wvalid + + 2 + 2 + + + + + + WREADY + + + m_axi_wready + + 2 + 2 + + + + + + BID + + + m_axi_bid + + 2 + 2 + + + + + + BRESP + + + m_axi_bresp + + 5 + 4 + + + + + + BUSER + + + m_axi_buser + + 2 + 2 + + + + + + BVALID + + + m_axi_bvalid + + 2 + 2 + + + + + + BREADY + + + m_axi_bready + + 2 + 2 + + + + + + ARID + + + m_axi_arid + + 2 + 2 + + + + + + ARADDR + + + m_axi_araddr + + 95 + 64 + + + + + + ARLEN + + + m_axi_arlen + + 23 + 16 + + + + + + ARSIZE + + + m_axi_arsize + + 8 + 6 + + + + + + ARBURST + + + m_axi_arburst + + 5 + 4 + + + + + + ARLOCK + + + m_axi_arlock + + 2 + 2 + + + + + + ARCACHE + + + m_axi_arcache + + 11 + 8 + + + + + + ARPROT + + + m_axi_arprot + + 8 + 6 + + + + + + ARREGION + + + m_axi_arregion + + 11 + 8 + + + + + + ARQOS + + + m_axi_arqos + + 11 + 8 + + + + + + ARUSER + + + m_axi_aruser + + 2 + 2 + + + + + + ARVALID + + + m_axi_arvalid + + 2 + 2 + + + + + + ARREADY + + + m_axi_arready + + 2 + 2 + + + + + + RID + + + m_axi_rid + + 2 + 2 + + + + + + RDATA + + + m_axi_rdata + + 191 + 128 + + + + + + RRESP + + + m_axi_rresp + + 5 + 4 + + + + + + RLAST + + + m_axi_rlast + + 2 + 2 + + + + + + RUSER + + + m_axi_ruser + + 2 + 2 + + + + + + RVALID + + + m_axi_rvalid + + 2 + 2 + + + + + + RREADY + + + m_axi_rready + + 2 + 2 + + + + + + + + false + + + + + + S03_AXI + S03_AXI + + + + + + + AWID + + + s_axi_awid + + 3 + 3 + + + + + + AWADDR + + + s_axi_awaddr + + 127 + 96 + + + + + + AWLEN + + + s_axi_awlen + + 31 + 24 + + + + + + AWSIZE + + + s_axi_awsize + + 11 + 9 + + + + + + AWBURST + + + s_axi_awburst + + 7 + 6 + + + + + + AWLOCK + + + s_axi_awlock + + 3 + 3 + + + + + + AWCACHE + + + s_axi_awcache + + 15 + 12 + + + + + + AWPROT + + + s_axi_awprot + + 11 + 9 + + + + + + AWQOS + + + s_axi_awqos + + 15 + 12 + + + + + + AWUSER + + + s_axi_awuser + + 3 + 3 + + + + + + AWVALID + + + s_axi_awvalid + + 3 + 3 + + + + + + AWREADY + + + s_axi_awready + + 3 + 3 + + + + + + WID + + + s_axi_wid + + 3 + 3 + + + + + + WDATA + + + s_axi_wdata + + 255 + 192 + + + + + + WSTRB + + + s_axi_wstrb + + 31 + 24 + + + + + + WLAST + + + s_axi_wlast + + 3 + 3 + + + + + + WUSER + + + s_axi_wuser + + 3 + 3 + + + + + + WVALID + + + s_axi_wvalid + + 3 + 3 + + + + + + WREADY + + + s_axi_wready + + 3 + 3 + + + + + + BID + + + s_axi_bid + + 3 + 3 + + + + + + BRESP + + + s_axi_bresp + + 7 + 6 + + + + + + BUSER + + + s_axi_buser + + 3 + 3 + + + + + + BVALID + + + s_axi_bvalid + + 3 + 3 + + + + + + BREADY + + + s_axi_bready + + 3 + 3 + + + + + + ARID + + + s_axi_arid + + 3 + 3 + + + + + + ARADDR + + + s_axi_araddr + + 127 + 96 + + + + + + ARLEN + + + s_axi_arlen + + 31 + 24 + + + + + + ARSIZE + + + s_axi_arsize + + 11 + 9 + + + + + + ARBURST + + + s_axi_arburst + + 7 + 6 + + + + + + ARLOCK + + + s_axi_arlock + + 3 + 3 + + + + + + ARCACHE + + + s_axi_arcache + + 15 + 12 + + + + + + ARPROT + + + s_axi_arprot + + 11 + 9 + + + + + + ARQOS + + + s_axi_arqos + + 15 + 12 + + + + + + ARUSER + + + s_axi_aruser + + 3 + 3 + + + + + + ARVALID + + + s_axi_arvalid + + 3 + 3 + + + + + + ARREADY + + + s_axi_arready + + 3 + 3 + + + + + + RID + + + s_axi_rid + + 3 + 3 + + + + + + RDATA + + + s_axi_rdata + + 255 + 192 + + + + + + RRESP + + + s_axi_rresp + + 7 + 6 + + + + + + RLAST + + + s_axi_rlast + + 3 + 3 + + + + + + RUSER + + + s_axi_ruser + + 3 + 3 + + + + + + RVALID + + + s_axi_rvalid + + 3 + 3 + + + + + + RREADY + + + s_axi_rready + + 3 + 3 + + + + + + + + false + + + + + + M03_AXI + M03_AXI + + + + + + + AWID + + + m_axi_awid + + 3 + 3 + + + + + + AWADDR + + + m_axi_awaddr + + 127 + 96 + + + + + + AWLEN + + + m_axi_awlen + + 31 + 24 + + + + + + AWSIZE + + + m_axi_awsize + + 11 + 9 + + + + + + AWBURST + + + m_axi_awburst + + 7 + 6 + + + + + + AWLOCK + + + m_axi_awlock + + 3 + 3 + + + + + + AWCACHE + + + m_axi_awcache + + 15 + 12 + + + + + + AWPROT + + + m_axi_awprot + + 11 + 9 + + + + + + AWREGION + + + m_axi_awregion + + 15 + 12 + + + + + + AWQOS + + + m_axi_awqos + + 15 + 12 + + + + + + AWUSER + + + m_axi_awuser + + 3 + 3 + + + + + + AWVALID + + + m_axi_awvalid + + 3 + 3 + + + + + + AWREADY + + + m_axi_awready + + 3 + 3 + + + + + + WID + + + m_axi_wid + + 3 + 3 + + + + + + WDATA + + + m_axi_wdata + + 255 + 192 + + + + + + WSTRB + + + m_axi_wstrb + + 31 + 24 + + + + + + WLAST + + + m_axi_wlast + + 3 + 3 + + + + + + WUSER + + + m_axi_wuser + + 3 + 3 + + + + + + WVALID + + + m_axi_wvalid + + 3 + 3 + + + + + + WREADY + + + m_axi_wready + + 3 + 3 + + + + + + BID + + + m_axi_bid + + 3 + 3 + + + + + + BRESP + + + m_axi_bresp + + 7 + 6 + + + + + + BUSER + + + m_axi_buser + + 3 + 3 + + + + + + BVALID + + + m_axi_bvalid + + 3 + 3 + + + + + + BREADY + + + m_axi_bready + + 3 + 3 + + + + + + ARID + + + m_axi_arid + + 3 + 3 + + + + + + ARADDR + + + m_axi_araddr + + 127 + 96 + + + + + + ARLEN + + + m_axi_arlen + + 31 + 24 + + + + + + ARSIZE + + + m_axi_arsize + + 11 + 9 + + + + + + ARBURST + + + m_axi_arburst + + 7 + 6 + + + + + + ARLOCK + + + m_axi_arlock + + 3 + 3 + + + + + + ARCACHE + + + m_axi_arcache + + 15 + 12 + + + + + + ARPROT + + + m_axi_arprot + + 11 + 9 + + + + + + ARREGION + + + m_axi_arregion + + 15 + 12 + + + + + + ARQOS + + + m_axi_arqos + + 15 + 12 + + + + + + ARUSER + + + m_axi_aruser + + 3 + 3 + + + + + + ARVALID + + + m_axi_arvalid + + 3 + 3 + + + + + + ARREADY + + + m_axi_arready + + 3 + 3 + + + + + + RID + + + m_axi_rid + + 3 + 3 + + + + + + RDATA + + + m_axi_rdata + + 255 + 192 + + + + + + RRESP + + + m_axi_rresp + + 7 + 6 + + + + + + RLAST + + + m_axi_rlast + + 3 + 3 + + + + + + RUSER + + + m_axi_ruser + + 3 + 3 + + + + + + RVALID + + + m_axi_rvalid + + 3 + 3 + + + + + + RREADY + + + m_axi_rready + + 3 + 3 + + + + + + + + false + + + + + + S04_AXI + S04_AXI + + + + + + + AWID + + + s_axi_awid + + 4 + 4 + + + + + + AWADDR + + + s_axi_awaddr + + 159 + 128 + + + + + + AWLEN + + + s_axi_awlen + + 39 + 32 + + + + + + AWSIZE + + + s_axi_awsize + + 14 + 12 + + + + + + AWBURST + + + s_axi_awburst + + 9 + 8 + + + + + + AWLOCK + + + s_axi_awlock + + 4 + 4 + + + + + + AWCACHE + + + s_axi_awcache + + 19 + 16 + + + + + + AWPROT + + + s_axi_awprot + + 14 + 12 + + + + + + AWQOS + + + s_axi_awqos + + 19 + 16 + + + + + + AWUSER + + + s_axi_awuser + + 4 + 4 + + + + + + AWVALID + + + s_axi_awvalid + + 4 + 4 + + + + + + AWREADY + + + s_axi_awready + + 4 + 4 + + + + + + WID + + + s_axi_wid + + 4 + 4 + + + + + + WDATA + + + s_axi_wdata + + 319 + 256 + + + + + + WSTRB + + + s_axi_wstrb + + 39 + 32 + + + + + + WLAST + + + s_axi_wlast + + 4 + 4 + + + + + + WUSER + + + s_axi_wuser + + 4 + 4 + + + + + + WVALID + + + s_axi_wvalid + + 4 + 4 + + + + + + WREADY + + + s_axi_wready + + 4 + 4 + + + + + + BID + + + s_axi_bid + + 4 + 4 + + + + + + BRESP + + + s_axi_bresp + + 9 + 8 + + + + + + BUSER + + + s_axi_buser + + 4 + 4 + + + + + + BVALID + + + s_axi_bvalid + + 4 + 4 + + + + + + BREADY + + + s_axi_bready + + 4 + 4 + + + + + + ARID + + + s_axi_arid + + 4 + 4 + + + + + + ARADDR + + + s_axi_araddr + + 159 + 128 + + + + + + ARLEN + + + s_axi_arlen + + 39 + 32 + + + + + + ARSIZE + + + s_axi_arsize + + 14 + 12 + + + + + + ARBURST + + + s_axi_arburst + + 9 + 8 + + + + + + ARLOCK + + + s_axi_arlock + + 4 + 4 + + + + + + ARCACHE + + + s_axi_arcache + + 19 + 16 + + + + + + ARPROT + + + s_axi_arprot + + 14 + 12 + + + + + + ARQOS + + + s_axi_arqos + + 19 + 16 + + + + + + ARUSER + + + s_axi_aruser + + 4 + 4 + + + + + + ARVALID + + + s_axi_arvalid + + 4 + 4 + + + + + + ARREADY + + + s_axi_arready + + 4 + 4 + + + + + + RID + + + s_axi_rid + + 4 + 4 + + + + + + RDATA + + + s_axi_rdata + + 319 + 256 + + + + + + RRESP + + + s_axi_rresp + + 9 + 8 + + + + + + RLAST + + + s_axi_rlast + + 4 + 4 + + + + + + RUSER + + + s_axi_ruser + + 4 + 4 + + + + + + RVALID + + + s_axi_rvalid + + 4 + 4 + + + + + + RREADY + + + s_axi_rready + + 4 + 4 + + + + + + + + false + + + + + + M04_AXI + M04_AXI + + + + + + + AWID + + + m_axi_awid + + 4 + 4 + + + + + + AWADDR + + + m_axi_awaddr + + 159 + 128 + + + + + + AWLEN + + + m_axi_awlen + + 39 + 32 + + + + + + AWSIZE + + + m_axi_awsize + + 14 + 12 + + + + + + AWBURST + + + m_axi_awburst + + 9 + 8 + + + + + + AWLOCK + + + m_axi_awlock + + 4 + 4 + + + + + + AWCACHE + + + m_axi_awcache + + 19 + 16 + + + + + + AWPROT + + + m_axi_awprot + + 14 + 12 + + + + + + AWREGION + + + m_axi_awregion + + 19 + 16 + + + + + + AWQOS + + + m_axi_awqos + + 19 + 16 + + + + + + AWUSER + + + m_axi_awuser + + 4 + 4 + + + + + + AWVALID + + + m_axi_awvalid + + 4 + 4 + + + + + + AWREADY + + + m_axi_awready + + 4 + 4 + + + + + + WID + + + m_axi_wid + + 4 + 4 + + + + + + WDATA + + + m_axi_wdata + + 319 + 256 + + + + + + WSTRB + + + m_axi_wstrb + + 39 + 32 + + + + + + WLAST + + + m_axi_wlast + + 4 + 4 + + + + + + WUSER + + + m_axi_wuser + + 4 + 4 + + + + + + WVALID + + + m_axi_wvalid + + 4 + 4 + + + + + + WREADY + + + m_axi_wready + + 4 + 4 + + + + + + BID + + + m_axi_bid + + 4 + 4 + + + + + + BRESP + + + m_axi_bresp + + 9 + 8 + + + + + + BUSER + + + m_axi_buser + + 4 + 4 + + + + + + BVALID + + + m_axi_bvalid + + 4 + 4 + + + + + + BREADY + + + m_axi_bready + + 4 + 4 + + + + + + ARID + + + m_axi_arid + + 4 + 4 + + + + + + ARADDR + + + m_axi_araddr + + 159 + 128 + + + + + + ARLEN + + + m_axi_arlen + + 39 + 32 + + + + + + ARSIZE + + + m_axi_arsize + + 14 + 12 + + + + + + ARBURST + + + m_axi_arburst + + 9 + 8 + + + + + + ARLOCK + + + m_axi_arlock + + 4 + 4 + + + + + + ARCACHE + + + m_axi_arcache + + 19 + 16 + + + + + + ARPROT + + + m_axi_arprot + + 14 + 12 + + + + + + ARREGION + + + m_axi_arregion + + 19 + 16 + + + + + + ARQOS + + + m_axi_arqos + + 19 + 16 + + + + + + ARUSER + + + m_axi_aruser + + 4 + 4 + + + + + + ARVALID + + + m_axi_arvalid + + 4 + 4 + + + + + + ARREADY + + + m_axi_arready + + 4 + 4 + + + + + + RID + + + m_axi_rid + + 4 + 4 + + + + + + RDATA + + + m_axi_rdata + + 319 + 256 + + + + + + RRESP + + + m_axi_rresp + + 9 + 8 + + + + + + RLAST + + + m_axi_rlast + + 4 + 4 + + + + + + RUSER + + + m_axi_ruser + + 4 + 4 + + + + + + RVALID + + + m_axi_rvalid + + 4 + 4 + + + + + + RREADY + + + m_axi_rready + + 4 + 4 + + + + + + + + false + + + + + + S05_AXI + S05_AXI + + + + + + + AWID + + + s_axi_awid + + 5 + 5 + + + + + + AWADDR + + + s_axi_awaddr + + 191 + 160 + + + + + + AWLEN + + + s_axi_awlen + + 47 + 40 + + + + + + AWSIZE + + + s_axi_awsize + + 17 + 15 + + + + + + AWBURST + + + s_axi_awburst + + 11 + 10 + + + + + + AWLOCK + + + s_axi_awlock + + 5 + 5 + + + + + + AWCACHE + + + s_axi_awcache + + 23 + 20 + + + + + + AWPROT + + + s_axi_awprot + + 17 + 15 + + + + + + AWQOS + + + s_axi_awqos + + 23 + 20 + + + + + + AWUSER + + + s_axi_awuser + + 5 + 5 + + + + + + AWVALID + + + s_axi_awvalid + + 5 + 5 + + + + + + AWREADY + + + s_axi_awready + + 5 + 5 + + + + + + WID + + + s_axi_wid + + 5 + 5 + + + + + + WDATA + + + s_axi_wdata + + 383 + 320 + + + + + + WSTRB + + + s_axi_wstrb + + 47 + 40 + + + + + + WLAST + + + s_axi_wlast + + 5 + 5 + + + + + + WUSER + + + s_axi_wuser + + 5 + 5 + + + + + + WVALID + + + s_axi_wvalid + + 5 + 5 + + + + + + WREADY + + + s_axi_wready + + 5 + 5 + + + + + + BID + + + s_axi_bid + + 5 + 5 + + + + + + BRESP + + + s_axi_bresp + + 11 + 10 + + + + + + BUSER + + + s_axi_buser + + 5 + 5 + + + + + + BVALID + + + s_axi_bvalid + + 5 + 5 + + + + + + BREADY + + + s_axi_bready + + 5 + 5 + + + + + + ARID + + + s_axi_arid + + 5 + 5 + + + + + + ARADDR + + + s_axi_araddr + + 191 + 160 + + + + + + ARLEN + + + s_axi_arlen + + 47 + 40 + + + + + + ARSIZE + + + s_axi_arsize + + 17 + 15 + + + + + + ARBURST + + + s_axi_arburst + + 11 + 10 + + + + + + ARLOCK + + + s_axi_arlock + + 5 + 5 + + + + + + ARCACHE + + + s_axi_arcache + + 23 + 20 + + + + + + ARPROT + + + s_axi_arprot + + 17 + 15 + + + + + + ARQOS + + + s_axi_arqos + + 23 + 20 + + + + + + ARUSER + + + s_axi_aruser + + 5 + 5 + + + + + + ARVALID + + + s_axi_arvalid + + 5 + 5 + + + + + + ARREADY + + + s_axi_arready + + 5 + 5 + + + + + + RID + + + s_axi_rid + + 5 + 5 + + + + + + RDATA + + + s_axi_rdata + + 383 + 320 + + + + + + RRESP + + + s_axi_rresp + + 11 + 10 + + + + + + RLAST + + + s_axi_rlast + + 5 + 5 + + + + + + RUSER + + + s_axi_ruser + + 5 + 5 + + + + + + RVALID + + + s_axi_rvalid + + 5 + 5 + + + + + + RREADY + + + s_axi_rready + + 5 + 5 + + + + + + + + false + + + + + + M05_AXI + M05_AXI + + + + + + + AWID + + + m_axi_awid + + 5 + 5 + + + + + + AWADDR + + + m_axi_awaddr + + 191 + 160 + + + + + + AWLEN + + + m_axi_awlen + + 47 + 40 + + + + + + AWSIZE + + + m_axi_awsize + + 17 + 15 + + + + + + AWBURST + + + m_axi_awburst + + 11 + 10 + + + + + + AWLOCK + + + m_axi_awlock + + 5 + 5 + + + + + + AWCACHE + + + m_axi_awcache + + 23 + 20 + + + + + + AWPROT + + + m_axi_awprot + + 17 + 15 + + + + + + AWREGION + + + m_axi_awregion + + 23 + 20 + + + + + + AWQOS + + + m_axi_awqos + + 23 + 20 + + + + + + AWUSER + + + m_axi_awuser + + 5 + 5 + + + + + + AWVALID + + + m_axi_awvalid + + 5 + 5 + + + + + + AWREADY + + + m_axi_awready + + 5 + 5 + + + + + + WID + + + m_axi_wid + + 5 + 5 + + + + + + WDATA + + + m_axi_wdata + + 383 + 320 + + + + + + WSTRB + + + m_axi_wstrb + + 47 + 40 + + + + + + WLAST + + + m_axi_wlast + + 5 + 5 + + + + + + WUSER + + + m_axi_wuser + + 5 + 5 + + + + + + WVALID + + + m_axi_wvalid + + 5 + 5 + + + + + + WREADY + + + m_axi_wready + + 5 + 5 + + + + + + BID + + + m_axi_bid + + 5 + 5 + + + + + + BRESP + + + m_axi_bresp + + 11 + 10 + + + + + + BUSER + + + m_axi_buser + + 5 + 5 + + + + + + BVALID + + + m_axi_bvalid + + 5 + 5 + + + + + + BREADY + + + m_axi_bready + + 5 + 5 + + + + + + ARID + + + m_axi_arid + + 5 + 5 + + + + + + ARADDR + + + m_axi_araddr + + 191 + 160 + + + + + + ARLEN + + + m_axi_arlen + + 47 + 40 + + + + + + ARSIZE + + + m_axi_arsize + + 17 + 15 + + + + + + ARBURST + + + m_axi_arburst + + 11 + 10 + + + + + + ARLOCK + + + m_axi_arlock + + 5 + 5 + + + + + + ARCACHE + + + m_axi_arcache + + 23 + 20 + + + + + + ARPROT + + + m_axi_arprot + + 17 + 15 + + + + + + ARREGION + + + m_axi_arregion + + 23 + 20 + + + + + + ARQOS + + + m_axi_arqos + + 23 + 20 + + + + + + ARUSER + + + m_axi_aruser + + 5 + 5 + + + + + + ARVALID + + + m_axi_arvalid + + 5 + 5 + + + + + + ARREADY + + + m_axi_arready + + 5 + 5 + + + + + + RID + + + m_axi_rid + + 5 + 5 + + + + + + RDATA + + + m_axi_rdata + + 383 + 320 + + + + + + RRESP + + + m_axi_rresp + + 11 + 10 + + + + + + RLAST + + + m_axi_rlast + + 5 + 5 + + + + + + RUSER + + + m_axi_ruser + + 5 + 5 + + + + + + RVALID + + + m_axi_rvalid + + 5 + 5 + + + + + + RREADY + + + m_axi_rready + + 5 + 5 + + + + + + + + false + + + + + + S06_AXI + S06_AXI + + + + + + + AWID + + + s_axi_awid + + 6 + 6 + + + + + + AWADDR + + + s_axi_awaddr + + 223 + 192 + + + + + + AWLEN + + + s_axi_awlen + + 55 + 48 + + + + + + AWSIZE + + + s_axi_awsize + + 20 + 18 + + + + + + AWBURST + + + s_axi_awburst + + 13 + 12 + + + + + + AWLOCK + + + s_axi_awlock + + 6 + 6 + + + + + + AWCACHE + + + s_axi_awcache + + 27 + 24 + + + + + + AWPROT + + + s_axi_awprot + + 20 + 18 + + + + + + AWQOS + + + s_axi_awqos + + 27 + 24 + + + + + + AWUSER + + + s_axi_awuser + + 6 + 6 + + + + + + AWVALID + + + s_axi_awvalid + + 6 + 6 + + + + + + AWREADY + + + s_axi_awready + + 6 + 6 + + + + + + WID + + + s_axi_wid + + 6 + 6 + + + + + + WDATA + + + s_axi_wdata + + 447 + 384 + + + + + + WSTRB + + + s_axi_wstrb + + 55 + 48 + + + + + + WLAST + + + s_axi_wlast + + 6 + 6 + + + + + + WUSER + + + s_axi_wuser + + 6 + 6 + + + + + + WVALID + + + s_axi_wvalid + + 6 + 6 + + + + + + WREADY + + + s_axi_wready + + 6 + 6 + + + + + + BID + + + s_axi_bid + + 6 + 6 + + + + + + BRESP + + + s_axi_bresp + + 13 + 12 + + + + + + BUSER + + + s_axi_buser + + 6 + 6 + + + + + + BVALID + + + s_axi_bvalid + + 6 + 6 + + + + + + BREADY + + + s_axi_bready + + 6 + 6 + + + + + + ARID + + + s_axi_arid + + 6 + 6 + + + + + + ARADDR + + + s_axi_araddr + + 223 + 192 + + + + + + ARLEN + + + s_axi_arlen + + 55 + 48 + + + + + + ARSIZE + + + s_axi_arsize + + 20 + 18 + + + + + + ARBURST + + + s_axi_arburst + + 13 + 12 + + + + + + ARLOCK + + + s_axi_arlock + + 6 + 6 + + + + + + ARCACHE + + + s_axi_arcache + + 27 + 24 + + + + + + ARPROT + + + s_axi_arprot + + 20 + 18 + + + + + + ARQOS + + + s_axi_arqos + + 27 + 24 + + + + + + ARUSER + + + s_axi_aruser + + 6 + 6 + + + + + + ARVALID + + + s_axi_arvalid + + 6 + 6 + + + + + + ARREADY + + + s_axi_arready + + 6 + 6 + + + + + + RID + + + s_axi_rid + + 6 + 6 + + + + + + RDATA + + + s_axi_rdata + + 447 + 384 + + + + + + RRESP + + + s_axi_rresp + + 13 + 12 + + + + + + RLAST + + + s_axi_rlast + + 6 + 6 + + + + + + RUSER + + + s_axi_ruser + + 6 + 6 + + + + + + RVALID + + + s_axi_rvalid + + 6 + 6 + + + + + + RREADY + + + s_axi_rready + + 6 + 6 + + + + + + + + false + + + + + + M06_AXI + M06_AXI + + + + + + + AWID + + + m_axi_awid + + 6 + 6 + + + + + + AWADDR + + + m_axi_awaddr + + 223 + 192 + + + + + + AWLEN + + + m_axi_awlen + + 55 + 48 + + + + + + AWSIZE + + + m_axi_awsize + + 20 + 18 + + + + + + AWBURST + + + m_axi_awburst + + 13 + 12 + + + + + + AWLOCK + + + m_axi_awlock + + 6 + 6 + + + + + + AWCACHE + + + m_axi_awcache + + 27 + 24 + + + + + + AWPROT + + + m_axi_awprot + + 20 + 18 + + + + + + AWREGION + + + m_axi_awregion + + 27 + 24 + + + + + + AWQOS + + + m_axi_awqos + + 27 + 24 + + + + + + AWUSER + + + m_axi_awuser + + 6 + 6 + + + + + + AWVALID + + + m_axi_awvalid + + 6 + 6 + + + + + + AWREADY + + + m_axi_awready + + 6 + 6 + + + + + + WID + + + m_axi_wid + + 6 + 6 + + + + + + WDATA + + + m_axi_wdata + + 447 + 384 + + + + + + WSTRB + + + m_axi_wstrb + + 55 + 48 + + + + + + WLAST + + + m_axi_wlast + + 6 + 6 + + + + + + WUSER + + + m_axi_wuser + + 6 + 6 + + + + + + WVALID + + + m_axi_wvalid + + 6 + 6 + + + + + + WREADY + + + m_axi_wready + + 6 + 6 + + + + + + BID + + + m_axi_bid + + 6 + 6 + + + + + + BRESP + + + m_axi_bresp + + 13 + 12 + + + + + + BUSER + + + m_axi_buser + + 6 + 6 + + + + + + BVALID + + + m_axi_bvalid + + 6 + 6 + + + + + + BREADY + + + m_axi_bready + + 6 + 6 + + + + + + ARID + + + m_axi_arid + + 6 + 6 + + + + + + ARADDR + + + m_axi_araddr + + 223 + 192 + + + + + + ARLEN + + + m_axi_arlen + + 55 + 48 + + + + + + ARSIZE + + + m_axi_arsize + + 20 + 18 + + + + + + ARBURST + + + m_axi_arburst + + 13 + 12 + + + + + + ARLOCK + + + m_axi_arlock + + 6 + 6 + + + + + + ARCACHE + + + m_axi_arcache + + 27 + 24 + + + + + + ARPROT + + + m_axi_arprot + + 20 + 18 + + + + + + ARREGION + + + m_axi_arregion + + 27 + 24 + + + + + + ARQOS + + + m_axi_arqos + + 27 + 24 + + + + + + ARUSER + + + m_axi_aruser + + 6 + 6 + + + + + + ARVALID + + + m_axi_arvalid + + 6 + 6 + + + + + + ARREADY + + + m_axi_arready + + 6 + 6 + + + + + + RID + + + m_axi_rid + + 6 + 6 + + + + + + RDATA + + + m_axi_rdata + + 447 + 384 + + + + + + RRESP + + + m_axi_rresp + + 13 + 12 + + + + + + RLAST + + + m_axi_rlast + + 6 + 6 + + + + + + RUSER + + + m_axi_ruser + + 6 + 6 + + + + + + RVALID + + + m_axi_rvalid + + 6 + 6 + + + + + + RREADY + + + m_axi_rready + + 6 + 6 + + + + + + + + false + + + + + + S07_AXI + S07_AXI + + + + + + + AWID + + + s_axi_awid + + 7 + 7 + + + + + + AWADDR + + + s_axi_awaddr + + 255 + 224 + + + + + + AWLEN + + + s_axi_awlen + + 63 + 56 + + + + + + AWSIZE + + + s_axi_awsize + + 23 + 21 + + + + + + AWBURST + + + s_axi_awburst + + 15 + 14 + + + + + + AWLOCK + + + s_axi_awlock + + 7 + 7 + + + + + + AWCACHE + + + s_axi_awcache + + 31 + 28 + + + + + + AWPROT + + + s_axi_awprot + + 23 + 21 + + + + + + AWQOS + + + s_axi_awqos + + 31 + 28 + + + + + + AWUSER + + + s_axi_awuser + + 7 + 7 + + + + + + AWVALID + + + s_axi_awvalid + + 7 + 7 + + + + + + AWREADY + + + s_axi_awready + + 7 + 7 + + + + + + WID + + + s_axi_wid + + 7 + 7 + + + + + + WDATA + + + s_axi_wdata + + 511 + 448 + + + + + + WSTRB + + + s_axi_wstrb + + 63 + 56 + + + + + + WLAST + + + s_axi_wlast + + 7 + 7 + + + + + + WUSER + + + s_axi_wuser + + 7 + 7 + + + + + + WVALID + + + s_axi_wvalid + + 7 + 7 + + + + + + WREADY + + + s_axi_wready + + 7 + 7 + + + + + + BID + + + s_axi_bid + + 7 + 7 + + + + + + BRESP + + + s_axi_bresp + + 15 + 14 + + + + + + BUSER + + + s_axi_buser + + 7 + 7 + + + + + + BVALID + + + s_axi_bvalid + + 7 + 7 + + + + + + BREADY + + + s_axi_bready + + 7 + 7 + + + + + + ARID + + + s_axi_arid + + 7 + 7 + + + + + + ARADDR + + + s_axi_araddr + + 255 + 224 + + + + + + ARLEN + + + s_axi_arlen + + 63 + 56 + + + + + + ARSIZE + + + s_axi_arsize + + 23 + 21 + + + + + + ARBURST + + + s_axi_arburst + + 15 + 14 + + + + + + ARLOCK + + + s_axi_arlock + + 7 + 7 + + + + + + ARCACHE + + + s_axi_arcache + + 31 + 28 + + + + + + ARPROT + + + s_axi_arprot + + 23 + 21 + + + + + + ARQOS + + + s_axi_arqos + + 31 + 28 + + + + + + ARUSER + + + s_axi_aruser + + 7 + 7 + + + + + + ARVALID + + + s_axi_arvalid + + 7 + 7 + + + + + + ARREADY + + + s_axi_arready + + 7 + 7 + + + + + + RID + + + s_axi_rid + + 7 + 7 + + + + + + RDATA + + + s_axi_rdata + + 511 + 448 + + + + + + RRESP + + + s_axi_rresp + + 15 + 14 + + + + + + RLAST + + + s_axi_rlast + + 7 + 7 + + + + + + RUSER + + + s_axi_ruser + + 7 + 7 + + + + + + RVALID + + + s_axi_rvalid + + 7 + 7 + + + + + + RREADY + + + s_axi_rready + + 7 + 7 + + + + + + + + false + + + + + + M07_AXI + M07_AXI + + + + + + + AWID + + + m_axi_awid + + 7 + 7 + + + + + + AWADDR + + + m_axi_awaddr + + 255 + 224 + + + + + + AWLEN + + + m_axi_awlen + + 63 + 56 + + + + + + AWSIZE + + + m_axi_awsize + + 23 + 21 + + + + + + AWBURST + + + m_axi_awburst + + 15 + 14 + + + + + + AWLOCK + + + m_axi_awlock + + 7 + 7 + + + + + + AWCACHE + + + m_axi_awcache + + 31 + 28 + + + + + + AWPROT + + + m_axi_awprot + + 23 + 21 + + + + + + AWREGION + + + m_axi_awregion + + 31 + 28 + + + + + + AWQOS + + + m_axi_awqos + + 31 + 28 + + + + + + AWUSER + + + m_axi_awuser + + 7 + 7 + + + + + + AWVALID + + + m_axi_awvalid + + 7 + 7 + + + + + + AWREADY + + + m_axi_awready + + 7 + 7 + + + + + + WID + + + m_axi_wid + + 7 + 7 + + + + + + WDATA + + + m_axi_wdata + + 511 + 448 + + + + + + WSTRB + + + m_axi_wstrb + + 63 + 56 + + + + + + WLAST + + + m_axi_wlast + + 7 + 7 + + + + + + WUSER + + + m_axi_wuser + + 7 + 7 + + + + + + WVALID + + + m_axi_wvalid + + 7 + 7 + + + + + + WREADY + + + m_axi_wready + + 7 + 7 + + + + + + BID + + + m_axi_bid + + 7 + 7 + + + + + + BRESP + + + m_axi_bresp + + 15 + 14 + + + + + + BUSER + + + m_axi_buser + + 7 + 7 + + + + + + BVALID + + + m_axi_bvalid + + 7 + 7 + + + + + + BREADY + + + m_axi_bready + + 7 + 7 + + + + + + ARID + + + m_axi_arid + + 7 + 7 + + + + + + ARADDR + + + m_axi_araddr + + 255 + 224 + + + + + + ARLEN + + + m_axi_arlen + + 63 + 56 + + + + + + ARSIZE + + + m_axi_arsize + + 23 + 21 + + + + + + ARBURST + + + m_axi_arburst + + 15 + 14 + + + + + + ARLOCK + + + m_axi_arlock + + 7 + 7 + + + + + + ARCACHE + + + m_axi_arcache + + 31 + 28 + + + + + + ARPROT + + + m_axi_arprot + + 23 + 21 + + + + + + ARREGION + + + m_axi_arregion + + 31 + 28 + + + + + + ARQOS + + + m_axi_arqos + + 31 + 28 + + + + + + ARUSER + + + m_axi_aruser + + 7 + 7 + + + + + + ARVALID + + + m_axi_arvalid + + 7 + 7 + + + + + + ARREADY + + + m_axi_arready + + 7 + 7 + + + + + + RID + + + m_axi_rid + + 7 + 7 + + + + + + RDATA + + + m_axi_rdata + + 511 + 448 + + + + + + RRESP + + + m_axi_rresp + + 15 + 14 + + + + + + RLAST + + + m_axi_rlast + + 7 + 7 + + + + + + RUSER + + + m_axi_ruser + + 7 + 7 + + + + + + RVALID + + + m_axi_rvalid + + 7 + 7 + + + + + + RREADY + + + m_axi_rready + + 7 + 7 + + + + + + + + false + + + + + + S08_AXI + S08_AXI + + + + + + + AWID + + + s_axi_awid + + 8 + 8 + + + + + + AWADDR + + + s_axi_awaddr + + 287 + 256 + + + + + + AWLEN + + + s_axi_awlen + + 71 + 64 + + + + + + AWSIZE + + + s_axi_awsize + + 26 + 24 + + + + + + AWBURST + + + s_axi_awburst + + 17 + 16 + + + + + + AWLOCK + + + s_axi_awlock + + 8 + 8 + + + + + + AWCACHE + + + s_axi_awcache + + 35 + 32 + + + + + + AWPROT + + + s_axi_awprot + + 26 + 24 + + + + + + AWQOS + + + s_axi_awqos + + 35 + 32 + + + + + + AWUSER + + + s_axi_awuser + + 8 + 8 + + + + + + AWVALID + + + s_axi_awvalid + + 8 + 8 + + + + + + AWREADY + + + s_axi_awready + + 8 + 8 + + + + + + WID + + + s_axi_wid + + 8 + 8 + + + + + + WDATA + + + s_axi_wdata + + 575 + 512 + + + + + + WSTRB + + + s_axi_wstrb + + 71 + 64 + + + + + + WLAST + + + s_axi_wlast + + 8 + 8 + + + + + + WUSER + + + s_axi_wuser + + 8 + 8 + + + + + + WVALID + + + s_axi_wvalid + + 8 + 8 + + + + + + WREADY + + + s_axi_wready + + 8 + 8 + + + + + + BID + + + s_axi_bid + + 8 + 8 + + + + + + BRESP + + + s_axi_bresp + + 17 + 16 + + + + + + BUSER + + + s_axi_buser + + 8 + 8 + + + + + + BVALID + + + s_axi_bvalid + + 8 + 8 + + + + + + BREADY + + + s_axi_bready + + 8 + 8 + + + + + + ARID + + + s_axi_arid + + 8 + 8 + + + + + + ARADDR + + + s_axi_araddr + + 287 + 256 + + + + + + ARLEN + + + s_axi_arlen + + 71 + 64 + + + + + + ARSIZE + + + s_axi_arsize + + 26 + 24 + + + + + + ARBURST + + + s_axi_arburst + + 17 + 16 + + + + + + ARLOCK + + + s_axi_arlock + + 8 + 8 + + + + + + ARCACHE + + + s_axi_arcache + + 35 + 32 + + + + + + ARPROT + + + s_axi_arprot + + 26 + 24 + + + + + + ARQOS + + + s_axi_arqos + + 35 + 32 + + + + + + ARUSER + + + s_axi_aruser + + 8 + 8 + + + + + + ARVALID + + + s_axi_arvalid + + 8 + 8 + + + + + + ARREADY + + + s_axi_arready + + 8 + 8 + + + + + + RID + + + s_axi_rid + + 8 + 8 + + + + + + RDATA + + + s_axi_rdata + + 575 + 512 + + + + + + RRESP + + + s_axi_rresp + + 17 + 16 + + + + + + RLAST + + + s_axi_rlast + + 8 + 8 + + + + + + RUSER + + + s_axi_ruser + + 8 + 8 + + + + + + RVALID + + + s_axi_rvalid + + 8 + 8 + + + + + + RREADY + + + s_axi_rready + + 8 + 8 + + + + + + + + false + + + + + + M08_AXI + M08_AXI + + + + + + + AWID + + + m_axi_awid + + 8 + 8 + + + + + + AWADDR + + + m_axi_awaddr + + 287 + 256 + + + + + + AWLEN + + + m_axi_awlen + + 71 + 64 + + + + + + AWSIZE + + + m_axi_awsize + + 26 + 24 + + + + + + AWBURST + + + m_axi_awburst + + 17 + 16 + + + + + + AWLOCK + + + m_axi_awlock + + 8 + 8 + + + + + + AWCACHE + + + m_axi_awcache + + 35 + 32 + + + + + + AWPROT + + + m_axi_awprot + + 26 + 24 + + + + + + AWREGION + + + m_axi_awregion + + 35 + 32 + + + + + + AWQOS + + + m_axi_awqos + + 35 + 32 + + + + + + AWUSER + + + m_axi_awuser + + 8 + 8 + + + + + + AWVALID + + + m_axi_awvalid + + 8 + 8 + + + + + + AWREADY + + + m_axi_awready + + 8 + 8 + + + + + + WID + + + m_axi_wid + + 8 + 8 + + + + + + WDATA + + + m_axi_wdata + + 575 + 512 + + + + + + WSTRB + + + m_axi_wstrb + + 71 + 64 + + + + + + WLAST + + + m_axi_wlast + + 8 + 8 + + + + + + WUSER + + + m_axi_wuser + + 8 + 8 + + + + + + WVALID + + + m_axi_wvalid + + 8 + 8 + + + + + + WREADY + + + m_axi_wready + + 8 + 8 + + + + + + BID + + + m_axi_bid + + 8 + 8 + + + + + + BRESP + + + m_axi_bresp + + 17 + 16 + + + + + + BUSER + + + m_axi_buser + + 8 + 8 + + + + + + BVALID + + + m_axi_bvalid + + 8 + 8 + + + + + + BREADY + + + m_axi_bready + + 8 + 8 + + + + + + ARID + + + m_axi_arid + + 8 + 8 + + + + + + ARADDR + + + m_axi_araddr + + 287 + 256 + + + + + + ARLEN + + + m_axi_arlen + + 71 + 64 + + + + + + ARSIZE + + + m_axi_arsize + + 26 + 24 + + + + + + ARBURST + + + m_axi_arburst + + 17 + 16 + + + + + + ARLOCK + + + m_axi_arlock + + 8 + 8 + + + + + + ARCACHE + + + m_axi_arcache + + 35 + 32 + + + + + + ARPROT + + + m_axi_arprot + + 26 + 24 + + + + + + ARREGION + + + m_axi_arregion + + 35 + 32 + + + + + + ARQOS + + + m_axi_arqos + + 35 + 32 + + + + + + ARUSER + + + m_axi_aruser + + 8 + 8 + + + + + + ARVALID + + + m_axi_arvalid + + 8 + 8 + + + + + + ARREADY + + + m_axi_arready + + 8 + 8 + + + + + + RID + + + m_axi_rid + + 8 + 8 + + + + + + RDATA + + + m_axi_rdata + + 575 + 512 + + + + + + RRESP + + + m_axi_rresp + + 17 + 16 + + + + + + RLAST + + + m_axi_rlast + + 8 + 8 + + + + + + RUSER + + + m_axi_ruser + + 8 + 8 + + + + + + RVALID + + + m_axi_rvalid + + 8 + 8 + + + + + + RREADY + + + m_axi_rready + + 8 + 8 + + + + + + + + false + + + + + + S09_AXI + S09_AXI + + + + + + + AWID + + + s_axi_awid + + 9 + 9 + + + + + + AWADDR + + + s_axi_awaddr + + 319 + 288 + + + + + + AWLEN + + + s_axi_awlen + + 79 + 72 + + + + + + AWSIZE + + + s_axi_awsize + + 29 + 27 + + + + + + AWBURST + + + s_axi_awburst + + 19 + 18 + + + + + + AWLOCK + + + s_axi_awlock + + 9 + 9 + + + + + + AWCACHE + + + s_axi_awcache + + 39 + 36 + + + + + + AWPROT + + + s_axi_awprot + + 29 + 27 + + + + + + AWQOS + + + s_axi_awqos + + 39 + 36 + + + + + + AWUSER + + + s_axi_awuser + + 9 + 9 + + + + + + AWVALID + + + s_axi_awvalid + + 9 + 9 + + + + + + AWREADY + + + s_axi_awready + + 9 + 9 + + + + + + WID + + + s_axi_wid + + 9 + 9 + + + + + + WDATA + + + s_axi_wdata + + 639 + 576 + + + + + + WSTRB + + + s_axi_wstrb + + 79 + 72 + + + + + + WLAST + + + s_axi_wlast + + 9 + 9 + + + + + + WUSER + + + s_axi_wuser + + 9 + 9 + + + + + + WVALID + + + s_axi_wvalid + + 9 + 9 + + + + + + WREADY + + + s_axi_wready + + 9 + 9 + + + + + + BID + + + s_axi_bid + + 9 + 9 + + + + + + BRESP + + + s_axi_bresp + + 19 + 18 + + + + + + BUSER + + + s_axi_buser + + 9 + 9 + + + + + + BVALID + + + s_axi_bvalid + + 9 + 9 + + + + + + BREADY + + + s_axi_bready + + 9 + 9 + + + + + + ARID + + + s_axi_arid + + 9 + 9 + + + + + + ARADDR + + + s_axi_araddr + + 319 + 288 + + + + + + ARLEN + + + s_axi_arlen + + 79 + 72 + + + + + + ARSIZE + + + s_axi_arsize + + 29 + 27 + + + + + + ARBURST + + + s_axi_arburst + + 19 + 18 + + + + + + ARLOCK + + + s_axi_arlock + + 9 + 9 + + + + + + ARCACHE + + + s_axi_arcache + + 39 + 36 + + + + + + ARPROT + + + s_axi_arprot + + 29 + 27 + + + + + + ARQOS + + + s_axi_arqos + + 39 + 36 + + + + + + ARUSER + + + s_axi_aruser + + 9 + 9 + + + + + + ARVALID + + + s_axi_arvalid + + 9 + 9 + + + + + + ARREADY + + + s_axi_arready + + 9 + 9 + + + + + + RID + + + s_axi_rid + + 9 + 9 + + + + + + RDATA + + + s_axi_rdata + + 639 + 576 + + + + + + RRESP + + + s_axi_rresp + + 19 + 18 + + + + + + RLAST + + + s_axi_rlast + + 9 + 9 + + + + + + RUSER + + + s_axi_ruser + + 9 + 9 + + + + + + RVALID + + + s_axi_rvalid + + 9 + 9 + + + + + + RREADY + + + s_axi_rready + + 9 + 9 + + + + + + + + false + + + + + + M09_AXI + M09_AXI + + + + + + + AWID + + + m_axi_awid + + 9 + 9 + + + + + + AWADDR + + + m_axi_awaddr + + 319 + 288 + + + + + + AWLEN + + + m_axi_awlen + + 79 + 72 + + + + + + AWSIZE + + + m_axi_awsize + + 29 + 27 + + + + + + AWBURST + + + m_axi_awburst + + 19 + 18 + + + + + + AWLOCK + + + m_axi_awlock + + 9 + 9 + + + + + + AWCACHE + + + m_axi_awcache + + 39 + 36 + + + + + + AWPROT + + + m_axi_awprot + + 29 + 27 + + + + + + AWREGION + + + m_axi_awregion + + 39 + 36 + + + + + + AWQOS + + + m_axi_awqos + + 39 + 36 + + + + + + AWUSER + + + m_axi_awuser + + 9 + 9 + + + + + + AWVALID + + + m_axi_awvalid + + 9 + 9 + + + + + + AWREADY + + + m_axi_awready + + 9 + 9 + + + + + + WID + + + m_axi_wid + + 9 + 9 + + + + + + WDATA + + + m_axi_wdata + + 639 + 576 + + + + + + WSTRB + + + m_axi_wstrb + + 79 + 72 + + + + + + WLAST + + + m_axi_wlast + + 9 + 9 + + + + + + WUSER + + + m_axi_wuser + + 9 + 9 + + + + + + WVALID + + + m_axi_wvalid + + 9 + 9 + + + + + + WREADY + + + m_axi_wready + + 9 + 9 + + + + + + BID + + + m_axi_bid + + 9 + 9 + + + + + + BRESP + + + m_axi_bresp + + 19 + 18 + + + + + + BUSER + + + m_axi_buser + + 9 + 9 + + + + + + BVALID + + + m_axi_bvalid + + 9 + 9 + + + + + + BREADY + + + m_axi_bready + + 9 + 9 + + + + + + ARID + + + m_axi_arid + + 9 + 9 + + + + + + ARADDR + + + m_axi_araddr + + 319 + 288 + + + + + + ARLEN + + + m_axi_arlen + + 79 + 72 + + + + + + ARSIZE + + + m_axi_arsize + + 29 + 27 + + + + + + ARBURST + + + m_axi_arburst + + 19 + 18 + + + + + + ARLOCK + + + m_axi_arlock + + 9 + 9 + + + + + + ARCACHE + + + m_axi_arcache + + 39 + 36 + + + + + + ARPROT + + + m_axi_arprot + + 29 + 27 + + + + + + ARREGION + + + m_axi_arregion + + 39 + 36 + + + + + + ARQOS + + + m_axi_arqos + + 39 + 36 + + + + + + ARUSER + + + m_axi_aruser + + 9 + 9 + + + + + + ARVALID + + + m_axi_arvalid + + 9 + 9 + + + + + + ARREADY + + + m_axi_arready + + 9 + 9 + + + + + + RID + + + m_axi_rid + + 9 + 9 + + + + + + RDATA + + + m_axi_rdata + + 639 + 576 + + + + + + RRESP + + + m_axi_rresp + + 19 + 18 + + + + + + RLAST + + + m_axi_rlast + + 9 + 9 + + + + + + RUSER + + + m_axi_ruser + + 9 + 9 + + + + + + RVALID + + + m_axi_rvalid + + 9 + 9 + + + + + + RREADY + + + m_axi_rready + + 9 + 9 + + + + + + + + false + + + + + + S10_AXI + S10_AXI + + + + + + + AWID + + + s_axi_awid + + 10 + 10 + + + + + + AWADDR + + + s_axi_awaddr + + 351 + 320 + + + + + + AWLEN + + + s_axi_awlen + + 87 + 80 + + + + + + AWSIZE + + + s_axi_awsize + + 32 + 30 + + + + + + AWBURST + + + s_axi_awburst + + 21 + 20 + + + + + + AWLOCK + + + s_axi_awlock + + 10 + 10 + + + + + + AWCACHE + + + s_axi_awcache + + 43 + 40 + + + + + + AWPROT + + + s_axi_awprot + + 32 + 30 + + + + + + AWQOS + + + s_axi_awqos + + 43 + 40 + + + + + + AWUSER + + + s_axi_awuser + + 10 + 10 + + + + + + AWVALID + + + s_axi_awvalid + + 10 + 10 + + + + + + AWREADY + + + s_axi_awready + + 10 + 10 + + + + + + WID + + + s_axi_wid + + 10 + 10 + + + + + + WDATA + + + s_axi_wdata + + 703 + 640 + + + + + + WSTRB + + + s_axi_wstrb + + 87 + 80 + + + + + + WLAST + + + s_axi_wlast + + 10 + 10 + + + + + + WUSER + + + s_axi_wuser + + 10 + 10 + + + + + + WVALID + + + s_axi_wvalid + + 10 + 10 + + + + + + WREADY + + + s_axi_wready + + 10 + 10 + + + + + + BID + + + s_axi_bid + + 10 + 10 + + + + + + BRESP + + + s_axi_bresp + + 21 + 20 + + + + + + BUSER + + + s_axi_buser + + 10 + 10 + + + + + + BVALID + + + s_axi_bvalid + + 10 + 10 + + + + + + BREADY + + + s_axi_bready + + 10 + 10 + + + + + + ARID + + + s_axi_arid + + 10 + 10 + + + + + + ARADDR + + + s_axi_araddr + + 351 + 320 + + + + + + ARLEN + + + s_axi_arlen + + 87 + 80 + + + + + + ARSIZE + + + s_axi_arsize + + 32 + 30 + + + + + + ARBURST + + + s_axi_arburst + + 21 + 20 + + + + + + ARLOCK + + + s_axi_arlock + + 10 + 10 + + + + + + ARCACHE + + + s_axi_arcache + + 43 + 40 + + + + + + ARPROT + + + s_axi_arprot + + 32 + 30 + + + + + + ARQOS + + + s_axi_arqos + + 43 + 40 + + + + + + ARUSER + + + s_axi_aruser + + 10 + 10 + + + + + + ARVALID + + + s_axi_arvalid + + 10 + 10 + + + + + + ARREADY + + + s_axi_arready + + 10 + 10 + + + + + + RID + + + s_axi_rid + + 10 + 10 + + + + + + RDATA + + + s_axi_rdata + + 703 + 640 + + + + + + RRESP + + + s_axi_rresp + + 21 + 20 + + + + + + RLAST + + + s_axi_rlast + + 10 + 10 + + + + + + RUSER + + + s_axi_ruser + + 10 + 10 + + + + + + RVALID + + + s_axi_rvalid + + 10 + 10 + + + + + + RREADY + + + s_axi_rready + + 10 + 10 + + + + + + + + false + + + + + + M10_AXI + M10_AXI + + + + + + + AWID + + + m_axi_awid + + 10 + 10 + + + + + + AWADDR + + + m_axi_awaddr + + 351 + 320 + + + + + + AWLEN + + + m_axi_awlen + + 87 + 80 + + + + + + AWSIZE + + + m_axi_awsize + + 32 + 30 + + + + + + AWBURST + + + m_axi_awburst + + 21 + 20 + + + + + + AWLOCK + + + m_axi_awlock + + 10 + 10 + + + + + + AWCACHE + + + m_axi_awcache + + 43 + 40 + + + + + + AWPROT + + + m_axi_awprot + + 32 + 30 + + + + + + AWREGION + + + m_axi_awregion + + 43 + 40 + + + + + + AWQOS + + + m_axi_awqos + + 43 + 40 + + + + + + AWUSER + + + m_axi_awuser + + 10 + 10 + + + + + + AWVALID + + + m_axi_awvalid + + 10 + 10 + + + + + + AWREADY + + + m_axi_awready + + 10 + 10 + + + + + + WID + + + m_axi_wid + + 10 + 10 + + + + + + WDATA + + + m_axi_wdata + + 703 + 640 + + + + + + WSTRB + + + m_axi_wstrb + + 87 + 80 + + + + + + WLAST + + + m_axi_wlast + + 10 + 10 + + + + + + WUSER + + + m_axi_wuser + + 10 + 10 + + + + + + WVALID + + + m_axi_wvalid + + 10 + 10 + + + + + + WREADY + + + m_axi_wready + + 10 + 10 + + + + + + BID + + + m_axi_bid + + 10 + 10 + + + + + + BRESP + + + m_axi_bresp + + 21 + 20 + + + + + + BUSER + + + m_axi_buser + + 10 + 10 + + + + + + BVALID + + + m_axi_bvalid + + 10 + 10 + + + + + + BREADY + + + m_axi_bready + + 10 + 10 + + + + + + ARID + + + m_axi_arid + + 10 + 10 + + + + + + ARADDR + + + m_axi_araddr + + 351 + 320 + + + + + + ARLEN + + + m_axi_arlen + + 87 + 80 + + + + + + ARSIZE + + + m_axi_arsize + + 32 + 30 + + + + + + ARBURST + + + m_axi_arburst + + 21 + 20 + + + + + + ARLOCK + + + m_axi_arlock + + 10 + 10 + + + + + + ARCACHE + + + m_axi_arcache + + 43 + 40 + + + + + + ARPROT + + + m_axi_arprot + + 32 + 30 + + + + + + ARREGION + + + m_axi_arregion + + 43 + 40 + + + + + + ARQOS + + + m_axi_arqos + + 43 + 40 + + + + + + ARUSER + + + m_axi_aruser + + 10 + 10 + + + + + + ARVALID + + + m_axi_arvalid + + 10 + 10 + + + + + + ARREADY + + + m_axi_arready + + 10 + 10 + + + + + + RID + + + m_axi_rid + + 10 + 10 + + + + + + RDATA + + + m_axi_rdata + + 703 + 640 + + + + + + RRESP + + + m_axi_rresp + + 21 + 20 + + + + + + RLAST + + + m_axi_rlast + + 10 + 10 + + + + + + RUSER + + + m_axi_ruser + + 10 + 10 + + + + + + RVALID + + + m_axi_rvalid + + 10 + 10 + + + + + + RREADY + + + m_axi_rready + + 10 + 10 + + + + + + + + false + + + + + + S11_AXI + S11_AXI + + + + + + + AWID + + + s_axi_awid + + 11 + 11 + + + + + + AWADDR + + + s_axi_awaddr + + 383 + 352 + + + + + + AWLEN + + + s_axi_awlen + + 95 + 88 + + + + + + AWSIZE + + + s_axi_awsize + + 35 + 33 + + + + + + AWBURST + + + s_axi_awburst + + 23 + 22 + + + + + + AWLOCK + + + s_axi_awlock + + 11 + 11 + + + + + + AWCACHE + + + s_axi_awcache + + 47 + 44 + + + + + + AWPROT + + + s_axi_awprot + + 35 + 33 + + + + + + AWQOS + + + s_axi_awqos + + 47 + 44 + + + + + + AWUSER + + + s_axi_awuser + + 11 + 11 + + + + + + AWVALID + + + s_axi_awvalid + + 11 + 11 + + + + + + AWREADY + + + s_axi_awready + + 11 + 11 + + + + + + WID + + + s_axi_wid + + 11 + 11 + + + + + + WDATA + + + s_axi_wdata + + 767 + 704 + + + + + + WSTRB + + + s_axi_wstrb + + 95 + 88 + + + + + + WLAST + + + s_axi_wlast + + 11 + 11 + + + + + + WUSER + + + s_axi_wuser + + 11 + 11 + + + + + + WVALID + + + s_axi_wvalid + + 11 + 11 + + + + + + WREADY + + + s_axi_wready + + 11 + 11 + + + + + + BID + + + s_axi_bid + + 11 + 11 + + + + + + BRESP + + + s_axi_bresp + + 23 + 22 + + + + + + BUSER + + + s_axi_buser + + 11 + 11 + + + + + + BVALID + + + s_axi_bvalid + + 11 + 11 + + + + + + BREADY + + + s_axi_bready + + 11 + 11 + + + + + + ARID + + + s_axi_arid + + 11 + 11 + + + + + + ARADDR + + + s_axi_araddr + + 383 + 352 + + + + + + ARLEN + + + s_axi_arlen + + 95 + 88 + + + + + + ARSIZE + + + s_axi_arsize + + 35 + 33 + + + + + + ARBURST + + + s_axi_arburst + + 23 + 22 + + + + + + ARLOCK + + + s_axi_arlock + + 11 + 11 + + + + + + ARCACHE + + + s_axi_arcache + + 47 + 44 + + + + + + ARPROT + + + s_axi_arprot + + 35 + 33 + + + + + + ARQOS + + + s_axi_arqos + + 47 + 44 + + + + + + ARUSER + + + s_axi_aruser + + 11 + 11 + + + + + + ARVALID + + + s_axi_arvalid + + 11 + 11 + + + + + + ARREADY + + + s_axi_arready + + 11 + 11 + + + + + + RID + + + s_axi_rid + + 11 + 11 + + + + + + RDATA + + + s_axi_rdata + + 767 + 704 + + + + + + RRESP + + + s_axi_rresp + + 23 + 22 + + + + + + RLAST + + + s_axi_rlast + + 11 + 11 + + + + + + RUSER + + + s_axi_ruser + + 11 + 11 + + + + + + RVALID + + + s_axi_rvalid + + 11 + 11 + + + + + + RREADY + + + s_axi_rready + + 11 + 11 + + + + + + + + false + + + + + + M11_AXI + M11_AXI + + + + + + + AWID + + + m_axi_awid + + 11 + 11 + + + + + + AWADDR + + + m_axi_awaddr + + 383 + 352 + + + + + + AWLEN + + + m_axi_awlen + + 95 + 88 + + + + + + AWSIZE + + + m_axi_awsize + + 35 + 33 + + + + + + AWBURST + + + m_axi_awburst + + 23 + 22 + + + + + + AWLOCK + + + m_axi_awlock + + 11 + 11 + + + + + + AWCACHE + + + m_axi_awcache + + 47 + 44 + + + + + + AWPROT + + + m_axi_awprot + + 35 + 33 + + + + + + AWREGION + + + m_axi_awregion + + 47 + 44 + + + + + + AWQOS + + + m_axi_awqos + + 47 + 44 + + + + + + AWUSER + + + m_axi_awuser + + 11 + 11 + + + + + + AWVALID + + + m_axi_awvalid + + 11 + 11 + + + + + + AWREADY + + + m_axi_awready + + 11 + 11 + + + + + + WID + + + m_axi_wid + + 11 + 11 + + + + + + WDATA + + + m_axi_wdata + + 767 + 704 + + + + + + WSTRB + + + m_axi_wstrb + + 95 + 88 + + + + + + WLAST + + + m_axi_wlast + + 11 + 11 + + + + + + WUSER + + + m_axi_wuser + + 11 + 11 + + + + + + WVALID + + + m_axi_wvalid + + 11 + 11 + + + + + + WREADY + + + m_axi_wready + + 11 + 11 + + + + + + BID + + + m_axi_bid + + 11 + 11 + + + + + + BRESP + + + m_axi_bresp + + 23 + 22 + + + + + + BUSER + + + m_axi_buser + + 11 + 11 + + + + + + BVALID + + + m_axi_bvalid + + 11 + 11 + + + + + + BREADY + + + m_axi_bready + + 11 + 11 + + + + + + ARID + + + m_axi_arid + + 11 + 11 + + + + + + ARADDR + + + m_axi_araddr + + 383 + 352 + + + + + + ARLEN + + + m_axi_arlen + + 95 + 88 + + + + + + ARSIZE + + + m_axi_arsize + + 35 + 33 + + + + + + ARBURST + + + m_axi_arburst + + 23 + 22 + + + + + + ARLOCK + + + m_axi_arlock + + 11 + 11 + + + + + + ARCACHE + + + m_axi_arcache + + 47 + 44 + + + + + + ARPROT + + + m_axi_arprot + + 35 + 33 + + + + + + ARREGION + + + m_axi_arregion + + 47 + 44 + + + + + + ARQOS + + + m_axi_arqos + + 47 + 44 + + + + + + ARUSER + + + m_axi_aruser + + 11 + 11 + + + + + + ARVALID + + + m_axi_arvalid + + 11 + 11 + + + + + + ARREADY + + + m_axi_arready + + 11 + 11 + + + + + + RID + + + m_axi_rid + + 11 + 11 + + + + + + RDATA + + + m_axi_rdata + + 767 + 704 + + + + + + RRESP + + + m_axi_rresp + + 23 + 22 + + + + + + RLAST + + + m_axi_rlast + + 11 + 11 + + + + + + RUSER + + + m_axi_ruser + + 11 + 11 + + + + + + RVALID + + + m_axi_rvalid + + 11 + 11 + + + + + + RREADY + + + m_axi_rready + + 11 + 11 + + + + + + + + false + + + + + + S12_AXI + S12_AXI + + + + + + + AWID + + + s_axi_awid + + 12 + 12 + + + + + + AWADDR + + + s_axi_awaddr + + 415 + 384 + + + + + + AWLEN + + + s_axi_awlen + + 103 + 96 + + + + + + AWSIZE + + + s_axi_awsize + + 38 + 36 + + + + + + AWBURST + + + s_axi_awburst + + 25 + 24 + + + + + + AWLOCK + + + s_axi_awlock + + 12 + 12 + + + + + + AWCACHE + + + s_axi_awcache + + 51 + 48 + + + + + + AWPROT + + + s_axi_awprot + + 38 + 36 + + + + + + AWQOS + + + s_axi_awqos + + 51 + 48 + + + + + + AWUSER + + + s_axi_awuser + + 12 + 12 + + + + + + AWVALID + + + s_axi_awvalid + + 12 + 12 + + + + + + AWREADY + + + s_axi_awready + + 12 + 12 + + + + + + WID + + + s_axi_wid + + 12 + 12 + + + + + + WDATA + + + s_axi_wdata + + 831 + 768 + + + + + + WSTRB + + + s_axi_wstrb + + 103 + 96 + + + + + + WLAST + + + s_axi_wlast + + 12 + 12 + + + + + + WUSER + + + s_axi_wuser + + 12 + 12 + + + + + + WVALID + + + s_axi_wvalid + + 12 + 12 + + + + + + WREADY + + + s_axi_wready + + 12 + 12 + + + + + + BID + + + s_axi_bid + + 12 + 12 + + + + + + BRESP + + + s_axi_bresp + + 25 + 24 + + + + + + BUSER + + + s_axi_buser + + 12 + 12 + + + + + + BVALID + + + s_axi_bvalid + + 12 + 12 + + + + + + BREADY + + + s_axi_bready + + 12 + 12 + + + + + + ARID + + + s_axi_arid + + 12 + 12 + + + + + + ARADDR + + + s_axi_araddr + + 415 + 384 + + + + + + ARLEN + + + s_axi_arlen + + 103 + 96 + + + + + + ARSIZE + + + s_axi_arsize + + 38 + 36 + + + + + + ARBURST + + + s_axi_arburst + + 25 + 24 + + + + + + ARLOCK + + + s_axi_arlock + + 12 + 12 + + + + + + ARCACHE + + + s_axi_arcache + + 51 + 48 + + + + + + ARPROT + + + s_axi_arprot + + 38 + 36 + + + + + + ARQOS + + + s_axi_arqos + + 51 + 48 + + + + + + ARUSER + + + s_axi_aruser + + 12 + 12 + + + + + + ARVALID + + + s_axi_arvalid + + 12 + 12 + + + + + + ARREADY + + + s_axi_arready + + 12 + 12 + + + + + + RID + + + s_axi_rid + + 12 + 12 + + + + + + RDATA + + + s_axi_rdata + + 831 + 768 + + + + + + RRESP + + + s_axi_rresp + + 25 + 24 + + + + + + RLAST + + + s_axi_rlast + + 12 + 12 + + + + + + RUSER + + + s_axi_ruser + + 12 + 12 + + + + + + RVALID + + + s_axi_rvalid + + 12 + 12 + + + + + + RREADY + + + s_axi_rready + + 12 + 12 + + + + + + + + false + + + + + + M12_AXI + M12_AXI + + + + + + + AWID + + + m_axi_awid + + 12 + 12 + + + + + + AWADDR + + + m_axi_awaddr + + 415 + 384 + + + + + + AWLEN + + + m_axi_awlen + + 103 + 96 + + + + + + AWSIZE + + + m_axi_awsize + + 38 + 36 + + + + + + AWBURST + + + m_axi_awburst + + 25 + 24 + + + + + + AWLOCK + + + m_axi_awlock + + 12 + 12 + + + + + + AWCACHE + + + m_axi_awcache + + 51 + 48 + + + + + + AWPROT + + + m_axi_awprot + + 38 + 36 + + + + + + AWREGION + + + m_axi_awregion + + 51 + 48 + + + + + + AWQOS + + + m_axi_awqos + + 51 + 48 + + + + + + AWUSER + + + m_axi_awuser + + 12 + 12 + + + + + + AWVALID + + + m_axi_awvalid + + 12 + 12 + + + + + + AWREADY + + + m_axi_awready + + 12 + 12 + + + + + + WID + + + m_axi_wid + + 12 + 12 + + + + + + WDATA + + + m_axi_wdata + + 831 + 768 + + + + + + WSTRB + + + m_axi_wstrb + + 103 + 96 + + + + + + WLAST + + + m_axi_wlast + + 12 + 12 + + + + + + WUSER + + + m_axi_wuser + + 12 + 12 + + + + + + WVALID + + + m_axi_wvalid + + 12 + 12 + + + + + + WREADY + + + m_axi_wready + + 12 + 12 + + + + + + BID + + + m_axi_bid + + 12 + 12 + + + + + + BRESP + + + m_axi_bresp + + 25 + 24 + + + + + + BUSER + + + m_axi_buser + + 12 + 12 + + + + + + BVALID + + + m_axi_bvalid + + 12 + 12 + + + + + + BREADY + + + m_axi_bready + + 12 + 12 + + + + + + ARID + + + m_axi_arid + + 12 + 12 + + + + + + ARADDR + + + m_axi_araddr + + 415 + 384 + + + + + + ARLEN + + + m_axi_arlen + + 103 + 96 + + + + + + ARSIZE + + + m_axi_arsize + + 38 + 36 + + + + + + ARBURST + + + m_axi_arburst + + 25 + 24 + + + + + + ARLOCK + + + m_axi_arlock + + 12 + 12 + + + + + + ARCACHE + + + m_axi_arcache + + 51 + 48 + + + + + + ARPROT + + + m_axi_arprot + + 38 + 36 + + + + + + ARREGION + + + m_axi_arregion + + 51 + 48 + + + + + + ARQOS + + + m_axi_arqos + + 51 + 48 + + + + + + ARUSER + + + m_axi_aruser + + 12 + 12 + + + + + + ARVALID + + + m_axi_arvalid + + 12 + 12 + + + + + + ARREADY + + + m_axi_arready + + 12 + 12 + + + + + + RID + + + m_axi_rid + + 12 + 12 + + + + + + RDATA + + + m_axi_rdata + + 831 + 768 + + + + + + RRESP + + + m_axi_rresp + + 25 + 24 + + + + + + RLAST + + + m_axi_rlast + + 12 + 12 + + + + + + RUSER + + + m_axi_ruser + + 12 + 12 + + + + + + RVALID + + + m_axi_rvalid + + 12 + 12 + + + + + + RREADY + + + m_axi_rready + + 12 + 12 + + + + + + + + false + + + + + + S13_AXI + S13_AXI + + + + + + + AWID + + + s_axi_awid + + 13 + 13 + + + + + + AWADDR + + + s_axi_awaddr + + 447 + 416 + + + + + + AWLEN + + + s_axi_awlen + + 111 + 104 + + + + + + AWSIZE + + + s_axi_awsize + + 41 + 39 + + + + + + AWBURST + + + s_axi_awburst + + 27 + 26 + + + + + + AWLOCK + + + s_axi_awlock + + 13 + 13 + + + + + + AWCACHE + + + s_axi_awcache + + 55 + 52 + + + + + + AWPROT + + + s_axi_awprot + + 41 + 39 + + + + + + AWQOS + + + s_axi_awqos + + 55 + 52 + + + + + + AWUSER + + + s_axi_awuser + + 13 + 13 + + + + + + AWVALID + + + s_axi_awvalid + + 13 + 13 + + + + + + AWREADY + + + s_axi_awready + + 13 + 13 + + + + + + WID + + + s_axi_wid + + 13 + 13 + + + + + + WDATA + + + s_axi_wdata + + 895 + 832 + + + + + + WSTRB + + + s_axi_wstrb + + 111 + 104 + + + + + + WLAST + + + s_axi_wlast + + 13 + 13 + + + + + + WUSER + + + s_axi_wuser + + 13 + 13 + + + + + + WVALID + + + s_axi_wvalid + + 13 + 13 + + + + + + WREADY + + + s_axi_wready + + 13 + 13 + + + + + + BID + + + s_axi_bid + + 13 + 13 + + + + + + BRESP + + + s_axi_bresp + + 27 + 26 + + + + + + BUSER + + + s_axi_buser + + 13 + 13 + + + + + + BVALID + + + s_axi_bvalid + + 13 + 13 + + + + + + BREADY + + + s_axi_bready + + 13 + 13 + + + + + + ARID + + + s_axi_arid + + 13 + 13 + + + + + + ARADDR + + + s_axi_araddr + + 447 + 416 + + + + + + ARLEN + + + s_axi_arlen + + 111 + 104 + + + + + + ARSIZE + + + s_axi_arsize + + 41 + 39 + + + + + + ARBURST + + + s_axi_arburst + + 27 + 26 + + + + + + ARLOCK + + + s_axi_arlock + + 13 + 13 + + + + + + ARCACHE + + + s_axi_arcache + + 55 + 52 + + + + + + ARPROT + + + s_axi_arprot + + 41 + 39 + + + + + + ARQOS + + + s_axi_arqos + + 55 + 52 + + + + + + ARUSER + + + s_axi_aruser + + 13 + 13 + + + + + + ARVALID + + + s_axi_arvalid + + 13 + 13 + + + + + + ARREADY + + + s_axi_arready + + 13 + 13 + + + + + + RID + + + s_axi_rid + + 13 + 13 + + + + + + RDATA + + + s_axi_rdata + + 895 + 832 + + + + + + RRESP + + + s_axi_rresp + + 27 + 26 + + + + + + RLAST + + + s_axi_rlast + + 13 + 13 + + + + + + RUSER + + + s_axi_ruser + + 13 + 13 + + + + + + RVALID + + + s_axi_rvalid + + 13 + 13 + + + + + + RREADY + + + s_axi_rready + + 13 + 13 + + + + + + + + false + + + + + + M13_AXI + M13_AXI + + + + + + + AWID + + + m_axi_awid + + 13 + 13 + + + + + + AWADDR + + + m_axi_awaddr + + 447 + 416 + + + + + + AWLEN + + + m_axi_awlen + + 111 + 104 + + + + + + AWSIZE + + + m_axi_awsize + + 41 + 39 + + + + + + AWBURST + + + m_axi_awburst + + 27 + 26 + + + + + + AWLOCK + + + m_axi_awlock + + 13 + 13 + + + + + + AWCACHE + + + m_axi_awcache + + 55 + 52 + + + + + + AWPROT + + + m_axi_awprot + + 41 + 39 + + + + + + AWREGION + + + m_axi_awregion + + 55 + 52 + + + + + + AWQOS + + + m_axi_awqos + + 55 + 52 + + + + + + AWUSER + + + m_axi_awuser + + 13 + 13 + + + + + + AWVALID + + + m_axi_awvalid + + 13 + 13 + + + + + + AWREADY + + + m_axi_awready + + 13 + 13 + + + + + + WID + + + m_axi_wid + + 13 + 13 + + + + + + WDATA + + + m_axi_wdata + + 895 + 832 + + + + + + WSTRB + + + m_axi_wstrb + + 111 + 104 + + + + + + WLAST + + + m_axi_wlast + + 13 + 13 + + + + + + WUSER + + + m_axi_wuser + + 13 + 13 + + + + + + WVALID + + + m_axi_wvalid + + 13 + 13 + + + + + + WREADY + + + m_axi_wready + + 13 + 13 + + + + + + BID + + + m_axi_bid + + 13 + 13 + + + + + + BRESP + + + m_axi_bresp + + 27 + 26 + + + + + + BUSER + + + m_axi_buser + + 13 + 13 + + + + + + BVALID + + + m_axi_bvalid + + 13 + 13 + + + + + + BREADY + + + m_axi_bready + + 13 + 13 + + + + + + ARID + + + m_axi_arid + + 13 + 13 + + + + + + ARADDR + + + m_axi_araddr + + 447 + 416 + + + + + + ARLEN + + + m_axi_arlen + + 111 + 104 + + + + + + ARSIZE + + + m_axi_arsize + + 41 + 39 + + + + + + ARBURST + + + m_axi_arburst + + 27 + 26 + + + + + + ARLOCK + + + m_axi_arlock + + 13 + 13 + + + + + + ARCACHE + + + m_axi_arcache + + 55 + 52 + + + + + + ARPROT + + + m_axi_arprot + + 41 + 39 + + + + + + ARREGION + + + m_axi_arregion + + 55 + 52 + + + + + + ARQOS + + + m_axi_arqos + + 55 + 52 + + + + + + ARUSER + + + m_axi_aruser + + 13 + 13 + + + + + + ARVALID + + + m_axi_arvalid + + 13 + 13 + + + + + + ARREADY + + + m_axi_arready + + 13 + 13 + + + + + + RID + + + m_axi_rid + + 13 + 13 + + + + + + RDATA + + + m_axi_rdata + + 895 + 832 + + + + + + RRESP + + + m_axi_rresp + + 27 + 26 + + + + + + RLAST + + + m_axi_rlast + + 13 + 13 + + + + + + RUSER + + + m_axi_ruser + + 13 + 13 + + + + + + RVALID + + + m_axi_rvalid + + 13 + 13 + + + + + + RREADY + + + m_axi_rready + + 13 + 13 + + + + + + + + false + + + + + + S14_AXI + S14_AXI + + + + + + + AWID + + + s_axi_awid + + 14 + 14 + + + + + + AWADDR + + + s_axi_awaddr + + 479 + 448 + + + + + + AWLEN + + + s_axi_awlen + + 119 + 112 + + + + + + AWSIZE + + + s_axi_awsize + + 44 + 42 + + + + + + AWBURST + + + s_axi_awburst + + 29 + 28 + + + + + + AWLOCK + + + s_axi_awlock + + 14 + 14 + + + + + + AWCACHE + + + s_axi_awcache + + 59 + 56 + + + + + + AWPROT + + + s_axi_awprot + + 44 + 42 + + + + + + AWQOS + + + s_axi_awqos + + 59 + 56 + + + + + + AWUSER + + + s_axi_awuser + + 14 + 14 + + + + + + AWVALID + + + s_axi_awvalid + + 14 + 14 + + + + + + AWREADY + + + s_axi_awready + + 14 + 14 + + + + + + WID + + + s_axi_wid + + 14 + 14 + + + + + + WDATA + + + s_axi_wdata + + 959 + 896 + + + + + + WSTRB + + + s_axi_wstrb + + 119 + 112 + + + + + + WLAST + + + s_axi_wlast + + 14 + 14 + + + + + + WUSER + + + s_axi_wuser + + 14 + 14 + + + + + + WVALID + + + s_axi_wvalid + + 14 + 14 + + + + + + WREADY + + + s_axi_wready + + 14 + 14 + + + + + + BID + + + s_axi_bid + + 14 + 14 + + + + + + BRESP + + + s_axi_bresp + + 29 + 28 + + + + + + BUSER + + + s_axi_buser + + 14 + 14 + + + + + + BVALID + + + s_axi_bvalid + + 14 + 14 + + + + + + BREADY + + + s_axi_bready + + 14 + 14 + + + + + + ARID + + + s_axi_arid + + 14 + 14 + + + + + + ARADDR + + + s_axi_araddr + + 479 + 448 + + + + + + ARLEN + + + s_axi_arlen + + 119 + 112 + + + + + + ARSIZE + + + s_axi_arsize + + 44 + 42 + + + + + + ARBURST + + + s_axi_arburst + + 29 + 28 + + + + + + ARLOCK + + + s_axi_arlock + + 14 + 14 + + + + + + ARCACHE + + + s_axi_arcache + + 59 + 56 + + + + + + ARPROT + + + s_axi_arprot + + 44 + 42 + + + + + + ARQOS + + + s_axi_arqos + + 59 + 56 + + + + + + ARUSER + + + s_axi_aruser + + 14 + 14 + + + + + + ARVALID + + + s_axi_arvalid + + 14 + 14 + + + + + + ARREADY + + + s_axi_arready + + 14 + 14 + + + + + + RID + + + s_axi_rid + + 14 + 14 + + + + + + RDATA + + + s_axi_rdata + + 959 + 896 + + + + + + RRESP + + + s_axi_rresp + + 29 + 28 + + + + + + RLAST + + + s_axi_rlast + + 14 + 14 + + + + + + RUSER + + + s_axi_ruser + + 14 + 14 + + + + + + RVALID + + + s_axi_rvalid + + 14 + 14 + + + + + + RREADY + + + s_axi_rready + + 14 + 14 + + + + + + + + false + + + + + + M14_AXI + M14_AXI + + + + + + + AWID + + + m_axi_awid + + 14 + 14 + + + + + + AWADDR + + + m_axi_awaddr + + 479 + 448 + + + + + + AWLEN + + + m_axi_awlen + + 119 + 112 + + + + + + AWSIZE + + + m_axi_awsize + + 44 + 42 + + + + + + AWBURST + + + m_axi_awburst + + 29 + 28 + + + + + + AWLOCK + + + m_axi_awlock + + 14 + 14 + + + + + + AWCACHE + + + m_axi_awcache + + 59 + 56 + + + + + + AWPROT + + + m_axi_awprot + + 44 + 42 + + + + + + AWREGION + + + m_axi_awregion + + 59 + 56 + + + + + + AWQOS + + + m_axi_awqos + + 59 + 56 + + + + + + AWUSER + + + m_axi_awuser + + 14 + 14 + + + + + + AWVALID + + + m_axi_awvalid + + 14 + 14 + + + + + + AWREADY + + + m_axi_awready + + 14 + 14 + + + + + + WID + + + m_axi_wid + + 14 + 14 + + + + + + WDATA + + + m_axi_wdata + + 959 + 896 + + + + + + WSTRB + + + m_axi_wstrb + + 119 + 112 + + + + + + WLAST + + + m_axi_wlast + + 14 + 14 + + + + + + WUSER + + + m_axi_wuser + + 14 + 14 + + + + + + WVALID + + + m_axi_wvalid + + 14 + 14 + + + + + + WREADY + + + m_axi_wready + + 14 + 14 + + + + + + BID + + + m_axi_bid + + 14 + 14 + + + + + + BRESP + + + m_axi_bresp + + 29 + 28 + + + + + + BUSER + + + m_axi_buser + + 14 + 14 + + + + + + BVALID + + + m_axi_bvalid + + 14 + 14 + + + + + + BREADY + + + m_axi_bready + + 14 + 14 + + + + + + ARID + + + m_axi_arid + + 14 + 14 + + + + + + ARADDR + + + m_axi_araddr + + 479 + 448 + + + + + + ARLEN + + + m_axi_arlen + + 119 + 112 + + + + + + ARSIZE + + + m_axi_arsize + + 44 + 42 + + + + + + ARBURST + + + m_axi_arburst + + 29 + 28 + + + + + + ARLOCK + + + m_axi_arlock + + 14 + 14 + + + + + + ARCACHE + + + m_axi_arcache + + 59 + 56 + + + + + + ARPROT + + + m_axi_arprot + + 44 + 42 + + + + + + ARREGION + + + m_axi_arregion + + 59 + 56 + + + + + + ARQOS + + + m_axi_arqos + + 59 + 56 + + + + + + ARUSER + + + m_axi_aruser + + 14 + 14 + + + + + + ARVALID + + + m_axi_arvalid + + 14 + 14 + + + + + + ARREADY + + + m_axi_arready + + 14 + 14 + + + + + + RID + + + m_axi_rid + + 14 + 14 + + + + + + RDATA + + + m_axi_rdata + + 959 + 896 + + + + + + RRESP + + + m_axi_rresp + + 29 + 28 + + + + + + RLAST + + + m_axi_rlast + + 14 + 14 + + + + + + RUSER + + + m_axi_ruser + + 14 + 14 + + + + + + RVALID + + + m_axi_rvalid + + 14 + 14 + + + + + + RREADY + + + m_axi_rready + + 14 + 14 + + + + + + + + false + + + + + + S15_AXI + S15_AXI + + + + + + + AWID + + + s_axi_awid + + 15 + 15 + + + + + + AWADDR + + + s_axi_awaddr + + 511 + 480 + + + + + + AWLEN + + + s_axi_awlen + + 127 + 120 + + + + + + AWSIZE + + + s_axi_awsize + + 47 + 45 + + + + + + AWBURST + + + s_axi_awburst + + 31 + 30 + + + + + + AWLOCK + + + s_axi_awlock + + 15 + 15 + + + + + + AWCACHE + + + s_axi_awcache + + 63 + 60 + + + + + + AWPROT + + + s_axi_awprot + + 47 + 45 + + + + + + AWQOS + + + s_axi_awqos + + 63 + 60 + + + + + + AWUSER + + + s_axi_awuser + + 15 + 15 + + + + + + AWVALID + + + s_axi_awvalid + + 15 + 15 + + + + + + AWREADY + + + s_axi_awready + + 15 + 15 + + + + + + WID + + + s_axi_wid + + 15 + 15 + + + + + + WDATA + + + s_axi_wdata + + 1023 + 960 + + + + + + WSTRB + + + s_axi_wstrb + + 127 + 120 + + + + + + WLAST + + + s_axi_wlast + + 15 + 15 + + + + + + WUSER + + + s_axi_wuser + + 15 + 15 + + + + + + WVALID + + + s_axi_wvalid + + 15 + 15 + + + + + + WREADY + + + s_axi_wready + + 15 + 15 + + + + + + BID + + + s_axi_bid + + 15 + 15 + + + + + + BRESP + + + s_axi_bresp + + 31 + 30 + + + + + + BUSER + + + s_axi_buser + + 15 + 15 + + + + + + BVALID + + + s_axi_bvalid + + 15 + 15 + + + + + + BREADY + + + s_axi_bready + + 15 + 15 + + + + + + ARID + + + s_axi_arid + + 15 + 15 + + + + + + ARADDR + + + s_axi_araddr + + 511 + 480 + + + + + + ARLEN + + + s_axi_arlen + + 127 + 120 + + + + + + ARSIZE + + + s_axi_arsize + + 47 + 45 + + + + + + ARBURST + + + s_axi_arburst + + 31 + 30 + + + + + + ARLOCK + + + s_axi_arlock + + 15 + 15 + + + + + + ARCACHE + + + s_axi_arcache + + 63 + 60 + + + + + + ARPROT + + + s_axi_arprot + + 47 + 45 + + + + + + ARQOS + + + s_axi_arqos + + 63 + 60 + + + + + + ARUSER + + + s_axi_aruser + + 15 + 15 + + + + + + ARVALID + + + s_axi_arvalid + + 15 + 15 + + + + + + ARREADY + + + s_axi_arready + + 15 + 15 + + + + + + RID + + + s_axi_rid + + 15 + 15 + + + + + + RDATA + + + s_axi_rdata + + 1023 + 960 + + + + + + RRESP + + + s_axi_rresp + + 31 + 30 + + + + + + RLAST + + + s_axi_rlast + + 15 + 15 + + + + + + RUSER + + + s_axi_ruser + + 15 + 15 + + + + + + RVALID + + + s_axi_rvalid + + 15 + 15 + + + + + + RREADY + + + s_axi_rready + + 15 + 15 + + + + + + + + false + + + + + + M15_AXI + M15_AXI + + + + + + + AWID + + + m_axi_awid + + 15 + 15 + + + + + + AWADDR + + + m_axi_awaddr + + 511 + 480 + + + + + + AWLEN + + + m_axi_awlen + + 127 + 120 + + + + + + AWSIZE + + + m_axi_awsize + + 47 + 45 + + + + + + AWBURST + + + m_axi_awburst + + 31 + 30 + + + + + + AWLOCK + + + m_axi_awlock + + 15 + 15 + + + + + + AWCACHE + + + m_axi_awcache + + 63 + 60 + + + + + + AWPROT + + + m_axi_awprot + + 47 + 45 + + + + + + AWREGION + + + m_axi_awregion + + 63 + 60 + + + + + + AWQOS + + + m_axi_awqos + + 63 + 60 + + + + + + AWUSER + + + m_axi_awuser + + 15 + 15 + + + + + + AWVALID + + + m_axi_awvalid + + 15 + 15 + + + + + + AWREADY + + + m_axi_awready + + 15 + 15 + + + + + + WID + + + m_axi_wid + + 15 + 15 + + + + + + WDATA + + + m_axi_wdata + + 1023 + 960 + + + + + + WSTRB + + + m_axi_wstrb + + 127 + 120 + + + + + + WLAST + + + m_axi_wlast + + 15 + 15 + + + + + + WUSER + + + m_axi_wuser + + 15 + 15 + + + + + + WVALID + + + m_axi_wvalid + + 15 + 15 + + + + + + WREADY + + + m_axi_wready + + 15 + 15 + + + + + + BID + + + m_axi_bid + + 15 + 15 + + + + + + BRESP + + + m_axi_bresp + + 31 + 30 + + + + + + BUSER + + + m_axi_buser + + 15 + 15 + + + + + + BVALID + + + m_axi_bvalid + + 15 + 15 + + + + + + BREADY + + + m_axi_bready + + 15 + 15 + + + + + + ARID + + + m_axi_arid + + 15 + 15 + + + + + + ARADDR + + + m_axi_araddr + + 511 + 480 + + + + + + ARLEN + + + m_axi_arlen + + 127 + 120 + + + + + + ARSIZE + + + m_axi_arsize + + 47 + 45 + + + + + + ARBURST + + + m_axi_arburst + + 31 + 30 + + + + + + ARLOCK + + + m_axi_arlock + + 15 + 15 + + + + + + ARCACHE + + + m_axi_arcache + + 63 + 60 + + + + + + ARPROT + + + m_axi_arprot + + 47 + 45 + + + + + + ARREGION + + + m_axi_arregion + + 63 + 60 + + + + + + ARQOS + + + m_axi_arqos + + 63 + 60 + + + + + + ARUSER + + + m_axi_aruser + + 15 + 15 + + + + + + ARVALID + + + m_axi_arvalid + + 15 + 15 + + + + + + ARREADY + + + m_axi_arready + + 15 + 15 + + + + + + RID + + + m_axi_rid + + 15 + 15 + + + + + + RDATA + + + m_axi_rdata + + 1023 + 960 + + + + + + RRESP + + + m_axi_rresp + + 31 + 30 + + + + + + RLAST + + + m_axi_rlast + + 15 + 15 + + + + + + RUSER + + + m_axi_ruser + + 15 + 15 + + + + + + RVALID + + + m_axi_rvalid + + 15 + 15 + + + + + + RREADY + + + m_axi_rready + + 15 + 15 + + + + + + + + false + + + + + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Mon Mar 06 19:29:28 UTC 2017 + + + boundaryCRC + ef8d5b32 + + + boundaryCRCversion + 1 + + + customizationCRC + 57a7a63f + + + customizationCRCversion + 6 + + + + + xilinx_verilogsynthesis + Verilog Synthesis + verilogSource:vivado.xilinx.com:synthesis + verilog + + xilinx_verilogsynthesis_xilinx_com_ip_generic_baseblocks_2_1__ref_view_fileset + + + xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + + xilinx_verilogsynthesis_xilinx_com_ip_axi_register_slice_2_1__ref_view_fileset + + + xilinx_verilogsynthesis_xilinx_com_ip_blk_mem_gen_8_3__ref_view_fileset + + + xilinx_verilogsynthesis_xilinx_com_ip_fifo_generator_13_1__ref_view_fileset + + + xilinx_verilogsynthesis_xilinx_com_ip_axi_data_fifo_2_1__ref_view_fileset + + + xilinx_verilogsynthesis_view_fileset + + + + GENtimestamp + Fri Feb 24 23:58:22 UTC 2017 + + + boundaryCRC + ef8d5b32 + + + boundaryCRCversion + 1 + + + customizationCRC + 57a7a63f + + + customizationCRCversion + 6 + + + + + xilinx_synthesisconstraints + Synthesis Constraints + :vivado.xilinx.com:synthesis.constraints + + xilinx_synthesisconstraints_view_fileset + + + + GENtimestamp + Mon Mar 06 19:29:16 UTC 2017 + + + boundaryCRC + ef8d5b32 + + + boundaryCRCversion + 1 + + + customizationCRC + 57a7a63f + + + customizationCRCversion + 6 + + + + + xilinx_verilogsynthesiswrapper + Verilog Synthesis Wrapper + verilogSource:vivado.xilinx.com:synthesis.wrapper + verilog + + xilinx_verilogsynthesiswrapper_view_fileset + + + + GENtimestamp + Mon Mar 06 19:29:16 UTC 2017 + + + boundaryCRC + ef8d5b32 + + + boundaryCRCversion + 1 + + + customizationCRC + 57a7a63f + + + customizationCRCversion + 6 + + + + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_generic_baseblocks_2_1__ref_view_fileset + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_register_slice_2_1__ref_view_fileset + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_fifo_generator_13_1__ref_view_fileset + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_data_fifo_2_1__ref_view_fileset + + + xilinx_verilogbehavioralsimulation_view_fileset + + + + GENtimestamp + Fri Feb 24 23:58:22 UTC 2017 + + + boundaryCRC + ef8d5b32 + + + boundaryCRCversion + 1 + + + customizationCRC + 97389796 + + + customizationCRCversion + 6 + + + + + xilinx_verilogsimulationwrapper + Verilog Simulation Wrapper + verilogSource:vivado.xilinx.com:simulation.wrapper + verilog + + xilinx_verilogsimulationwrapper_view_fileset + + + + GENtimestamp + Mon Mar 06 19:29:16 UTC 2017 + + + boundaryCRC + ef8d5b32 + + + boundaryCRCversion + 1 + + + customizationCRC + 97389796 + + + customizationCRCversion + 6 + + + + + + + aclk + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + aresetn + + in + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_awid + + in + + 1 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0 + + + + + + true + + + + + + s_axi_awaddr + + in + + 63 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0000000000000000 + + + + + s_axi_awlen + + in + + 15 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0000 + + + + + + true + + + + + + s_axi_awsize + + in + + 5 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x00 + + + + + + true + + + + + + s_axi_awburst + + in + + 3 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0 + + + + + + true + + + + + + s_axi_awlock + + in + + 1 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0 + + + + + + true + + + + + + s_axi_awcache + + in + + 7 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x00 + + + + + + true + + + + + + s_axi_awprot + + in + + 5 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x00 + + + + + s_axi_awqos + + in + + 7 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x00 + + + + + + true + + + + + + s_axi_awuser + + in + + 1 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0 + + + + + + false + + + + + + s_axi_awvalid + + in + + 1 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0 + + + + + + true + + + + + + s_axi_awready + + out + + 1 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_wid + + in + + 1 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0 + + + + + + false + + + + + + s_axi_wdata + + in + + 127 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x00000000000000000000000000000000 + + + + + s_axi_wstrb + + in + + 15 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0xFFFF + + + + + s_axi_wlast + + in + + 1 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x3 + + + + + + true + + + + + + s_axi_wuser + + in + + 1 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0 + + + + + + false + + + + + + s_axi_wvalid + + in + + 1 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0 + + + + + + true + + + + + + s_axi_wready + + out + + 1 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_bid + + out + + 1 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + s_axi_bresp + + out + + 3 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_buser + + out + + 1 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + s_axi_bvalid + + out + + 1 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + s_axi_bready + + in + + 1 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0 + + + + + s_axi_arid + + in + + 1 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0 + + + + + + true + + + + + + s_axi_araddr + + in + + 63 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0000000000000000 + + + + + s_axi_arlen + + in + + 15 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0000 + + + + + + true + + + + + + s_axi_arsize + + in + + 5 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x00 + + + + + + true + + + + + + s_axi_arburst + + in + + 3 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0 + + + + + + true + + + + + + s_axi_arlock + + in + + 1 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0 + + + + + + true + + + + + + s_axi_arcache + + in + + 7 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x00 + + + + + + true + + + + + + s_axi_arprot + + in + + 5 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x00 + + + + + s_axi_arqos + + in + + 7 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x00 + + + + + + true + + + + + + s_axi_aruser + + in + + 1 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0 + + + + + + false + + + + + + s_axi_arvalid + + in + + 1 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0 + + + + + + true + + + + + + s_axi_arready + + out + + 1 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_rid + + out + + 1 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + s_axi_rdata + + out + + 127 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_rresp + + out + + 3 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + s_axi_rlast + + out + + 1 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + s_axi_ruser + + out + + 1 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + s_axi_rvalid + + out + + 1 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + s_axi_rready + + in + + 1 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0 + + + + + m_axi_awid + + out + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_awaddr + + out + + 31 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_awlen + + out + + 7 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_awsize + + out + + 2 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_awburst + + out + + 1 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_awlock + + out + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_awcache + + out + + 3 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_awprot + + out + + 2 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_awregion + + out + + 3 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_awqos + + out + + 3 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_awuser + + out + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_awvalid + + out + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_awready + + in + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0 + + + + + m_axi_wid + + out + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_wdata + + out + + 63 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_wstrb + + out + + 7 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_wlast + + out + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_wuser + + out + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_wvalid + + out + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_wready + + in + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0 + + + + + m_axi_bid + + in + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0 + + + + + + true + + + + + + m_axi_bresp + + in + + 1 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0 + + + + + m_axi_buser + + in + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0 + + + + + + false + + + + + + m_axi_bvalid + + in + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0 + + + + + + true + + + + + + m_axi_bready + + out + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_arid + + out + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_araddr + + out + + 31 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_arlen + + out + + 7 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_arsize + + out + + 2 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_arburst + + out + + 1 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_arlock + + out + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_arcache + + out + + 3 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_arprot + + out + + 2 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + m_axi_arregion + + out + + 3 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_arqos + + out + + 3 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_aruser + + out + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + false + + + + + + m_axi_arvalid + + out + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + true + + + + + + m_axi_arready + + in + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0 + + + + + m_axi_rid + + in + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0 + + + + + + true + + + + + + m_axi_rdata + + in + + 63 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0000000000000000 + + + + + m_axi_rresp + + in + + 1 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0 + + + + + m_axi_rlast + + in + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x1 + + + + + + true + + + + + + m_axi_ruser + + in + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0 + + + + + + false + + + + + + m_axi_rvalid + + in + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + 0x0 + + + + + + true + + + + + + m_axi_rready + + out + + 0 + 0 + + + + wire + xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation + + + + + + + + C_FAMILY + zynq + + + C_NUM_SLAVE_SLOTS + 2 + + + C_NUM_MASTER_SLOTS + 1 + + + C_AXI_ID_WIDTH + 1 + + + C_AXI_ADDR_WIDTH + 32 + + + C_AXI_DATA_WIDTH + 64 + + + C_AXI_PROTOCOL + 0 + + + C_NUM_ADDR_RANGES + 1 + + + C_M_AXI_BASE_ADDR + 0x0000000000000000 + + + C_M_AXI_ADDR_WIDTH + 0x0000001d + + + C_S_AXI_BASE_ID + 0x0000000100000000 + + + C_S_AXI_THREAD_ID_WIDTH + 0x0000000000000000 + + + C_AXI_SUPPORTS_USER_SIGNALS + 0 + + + C_AXI_AWUSER_WIDTH + 1 + + + C_AXI_ARUSER_WIDTH + 1 + + + C_AXI_WUSER_WIDTH + 1 + + + C_AXI_RUSER_WIDTH + 1 + + + C_AXI_BUSER_WIDTH + 1 + + + C_M_AXI_WRITE_CONNECTIVITY + 0x00000002 + + + C_M_AXI_READ_CONNECTIVITY + 0x00000001 + + + C_R_REGISTER + 0 + + + C_S_AXI_SINGLE_THREAD + 0x0000000000000000 + + + C_S_AXI_WRITE_ACCEPTANCE + 0x0000000200000002 + + + C_S_AXI_READ_ACCEPTANCE + 0x0000000200000002 + + + C_M_AXI_WRITE_ISSUING + 0x00000008 + + + C_M_AXI_READ_ISSUING + 0x00000008 + + + C_S_AXI_ARB_PRIORITY + 0x0000000000000000 + + + C_M_AXI_SECURE + 0x00000000 + + + C_CONNECTIVITY_MODE + 1 + + + + + + choice_list_40181835 + 32 + 64 + 128 + 256 + 512 + 1024 + + + choice_list_7235ff92 + AXI4 + AXI3 + AXI4LITE + + + choice_pairs_12c5c5a3 + 0 + 1 + 7 + 8 + + + choice_pairs_37189c7b + 0 + 1 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_6c89085d + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + + + choice_pairs_d73d287f + SASD + SAMD + + + choice_pairs_d9a0b468 + 0 + 1 + + + choice_pairs_dd3f402c + 0 + 1 + 2 + + + + + xilinx_externalfiles_view_fileset + + Arty_Z7_20_xbar_1.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + Arty_Z7_20_xbar_1_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Arty_Z7_20_xbar_1_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + Arty_Z7_20_xbar_1_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + Arty_Z7_20_xbar_1_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx_verilogsynthesis_xilinx_com_ip_generic_baseblocks_2_1__ref_view_fileset + + ../../ipshared/7ee0/hdl/generic_baseblocks_v2_1_vl_rfs.v + verilogSource + generic_baseblocks_v2_1_0 + + + + + + + + + + + xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + ../../ipshared/7e3a/hdl/axi_infrastructure_v1_1_0.vh + verilogSource + true + axi_infrastructure_v1_1_0 + + + ../../ipshared/7e3a/hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogsynthesis_xilinx_com_ip_axi_register_slice_2_1__ref_view_fileset + + ../../ipshared/0b6b/hdl/axi_register_slice_v2_1_vl_rfs.v + verilogSource + axi_register_slice_v2_1_11 + + + + + + + + + + + xilinx_verilogsynthesis_xilinx_com_ip_blk_mem_gen_8_3__ref_view_fileset + + ../../ipshared/6273/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd + vhdlSource + blk_mem_gen_v8_3_5 + + + + + + + + + + + xilinx_verilogsynthesis_xilinx_com_ip_fifo_generator_13_1__ref_view_fileset + + ../../ipshared/564d/hdl/fifo_generator_v13_1_vhsyn_rfs.vhd + vhdlSource + fifo_generator_v13_1_3 + + + + + + + + + + + xilinx_verilogsynthesis_xilinx_com_ip_axi_data_fifo_2_1__ref_view_fileset + + ../../ipshared/39ba/hdl/axi_data_fifo_v2_1_vl_rfs.v + verilogSource + axi_data_fifo_v2_1_10 + + + + + + + + + + + xilinx_verilogsynthesis_view_fileset + + ../../ipshared/896d/hdl/axi_crossbar_v2_1_vl_rfs.v + verilogSource + axi_crossbar_v2_1_12 + + + + xilinx_synthesisconstraints_view_fileset + + Arty_Z7_20_xbar_1_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/Arty_Z7_20_xbar_1.v + verilogSource + xil_defaultlib + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_generic_baseblocks_2_1__ref_view_fileset + + ../../ipshared/7ee0/hdl/generic_baseblocks_v2_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + generic_baseblocks_v2_1_0 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset + + ../../ipshared/7e3a/hdl/axi_infrastructure_v1_1_0.vh + verilogSource + USED_IN_ipstatic + true + axi_infrastructure_v1_1_0 + + + ../../ipshared/7e3a/hdl/axi_infrastructure_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axi_infrastructure_v1_1_0 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_register_slice_2_1__ref_view_fileset + + ../../ipshared/0b6b/hdl/axi_register_slice_v2_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axi_register_slice_v2_1_11 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_fifo_generator_13_1__ref_view_fileset + + ../../ipshared/564d/simulation/fifo_generator_vlog_beh.v + verilogSource + USED_IN_ipstatic + fifo_generator_v13_1_3 + fifo_generator_vlog_beh + + + ../../ipshared/564d/hdl/fifo_generator_v13_1_rfs.vhd + vhdlSource + USED_IN_ipstatic + fifo_generator_v13_1_3 + + + ../../ipshared/564d/hdl/fifo_generator_v13_1_rfs.v + verilogSource + USED_IN_ipstatic + fifo_generator_v13_1_3 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axi_data_fifo_2_1__ref_view_fileset + + ../../ipshared/39ba/hdl/axi_data_fifo_v2_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axi_data_fifo_v2_1_10 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + ../../ipshared/896d/hdl/axi_crossbar_v2_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axi_crossbar_v2_1_12 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/Arty_Z7_20_xbar_1.v + verilogSource + xil_defaultlib + + + + The AXI Crossbar IP provides the infrastructure to connect multiple AXI4/AXI3/AXI4-Lite masters and slaves. + + + ADDR_RANGES + Number of Address Ranges + 1 + + + + true + + + + + + NUM_SI + Number of Slave Interfaces + 2 + + + + true + + + + + + NUM_MI + Number of Master Interfaces + 1 + + + + true + + + + + + ADDR_WIDTH + Address Width + 32 + + + + true + + + + + + STRATEGY + Crossbar Optimization Strategy + 0 + + + + true + + + + + + PROTOCOL + Protocol + AXI4 + + + + true + + + + + + DATA_WIDTH + Data Width + 64 + + + + true + + + + + + CONNECTIVITY_MODE + Connectivity Mode + SAMD + + + + true + + + + + + ID_WIDTH + ID Width + 1 + + + + true + + + + + + AWUSER_WIDTH + AWUSER Signal Width + 0 + + + + true + + + + + + ARUSER_WIDTH + ARUSER Signal Width + 0 + + + + true + + + + + + WUSER_WIDTH + WUSER Signal Width + 0 + + + + true + + + + + + RUSER_WIDTH + RUSER Signal Width + 0 + + + + true + + + + + + BUSER_WIDTH + BUSER Signal Width + 0 + + + + true + + + + + + R_REGISTER + Read Channel Register Slice + 0 + + + + false + + + + + + M00_S00_READ_CONNECTIVITY + My M00_S00_READ_CONNECTIVITY + 1 + + + + true + + + + + + M00_S01_READ_CONNECTIVITY + My M00_S01_READ_CONNECTIVITY + 0 + + + + true + + + + + + M00_S02_READ_CONNECTIVITY + My M00_S02_READ_CONNECTIVITY + 1 + + + + true + + + + + + M00_S03_READ_CONNECTIVITY + My M00_S03_READ_CONNECTIVITY + 1 + + + + true + + + + + + M00_S04_READ_CONNECTIVITY + My M00_S04_READ_CONNECTIVITY + 1 + + + + true + + + + + + M00_S05_READ_CONNECTIVITY + My M00_S05_READ_CONNECTIVITY + 1 + + + + true + + + + + + M00_S06_READ_CONNECTIVITY + My M00_S06_READ_CONNECTIVITY + 1 + + + + true + + + + + + M00_S07_READ_CONNECTIVITY + My M00_S07_READ_CONNECTIVITY + 1 + + + + true + + + + + + M00_S08_READ_CONNECTIVITY + My M00_S08_READ_CONNECTIVITY + 1 + + + + true + + + + + + M00_S09_READ_CONNECTIVITY + My M00_S09_READ_CONNECTIVITY + 1 + + + + true + + + + + + M00_S10_READ_CONNECTIVITY + My M00_S10_READ_CONNECTIVITY + 1 + + + + true + + + + + + M00_S11_READ_CONNECTIVITY + My M00_S11_READ_CONNECTIVITY + 1 + + + + true + + + + + + M00_S12_READ_CONNECTIVITY + My M00_S12_READ_CONNECTIVITY + 1 + + + + true + + + + + + M00_S13_READ_CONNECTIVITY + My M00_S13_READ_CONNECTIVITY + 1 + + + + true + + + + + + M00_S14_READ_CONNECTIVITY + My M00_S14_READ_CONNECTIVITY + 1 + + + + true + + + + + + M00_S15_READ_CONNECTIVITY + My M00_S15_READ_CONNECTIVITY + 1 + + + + true + + + + + + M01_S00_READ_CONNECTIVITY + My M01_S00_READ_CONNECTIVITY + 1 + + + + true + + + + + + M01_S01_READ_CONNECTIVITY + My M01_S01_READ_CONNECTIVITY + 1 + + + + true + + + + + + M01_S02_READ_CONNECTIVITY + My M01_S02_READ_CONNECTIVITY + 1 + + + + true + + + + + + M01_S03_READ_CONNECTIVITY + My M01_S03_READ_CONNECTIVITY + 1 + + + + true + + + + + + M01_S04_READ_CONNECTIVITY + My M01_S04_READ_CONNECTIVITY + 1 + + + + true + + + + + + M01_S05_READ_CONNECTIVITY + My M01_S05_READ_CONNECTIVITY + 1 + + + + true + + + + + + M01_S06_READ_CONNECTIVITY + My M01_S06_READ_CONNECTIVITY + 1 + + + + true + + + + + + M01_S07_READ_CONNECTIVITY + My M01_S07_READ_CONNECTIVITY + 1 + + + + true + + + + + + M01_S08_READ_CONNECTIVITY + My M01_S08_READ_CONNECTIVITY + 1 + + + + true + + + + + + M01_S09_READ_CONNECTIVITY + My M01_S09_READ_CONNECTIVITY + 1 + + + + true + + + + + + M01_S10_READ_CONNECTIVITY + My M01_S10_READ_CONNECTIVITY + 1 + + + + true + + + + + + M01_S11_READ_CONNECTIVITY + My M01_S11_READ_CONNECTIVITY + 1 + + + + true + + + + + + M01_S12_READ_CONNECTIVITY + My M01_S12_READ_CONNECTIVITY + 1 + + + + true + + + + + + M01_S13_READ_CONNECTIVITY + My M01_S13_READ_CONNECTIVITY + 1 + + + + true + + + + + + M01_S14_READ_CONNECTIVITY + My M01_S14_READ_CONNECTIVITY + 1 + + + + true + + + + + + M01_S15_READ_CONNECTIVITY + My M01_S15_READ_CONNECTIVITY + 1 + + + + true + + + + + + M02_S00_READ_CONNECTIVITY + My M02_S00_READ_CONNECTIVITY + 1 + + + + true + + + + + + M02_S01_READ_CONNECTIVITY + My M02_S01_READ_CONNECTIVITY + 1 + + + + true + + + + + + M02_S02_READ_CONNECTIVITY + My M02_S02_READ_CONNECTIVITY + 1 + + + + true + + + + + + M02_S03_READ_CONNECTIVITY + My M02_S03_READ_CONNECTIVITY + 1 + + + + true + + + + + + M02_S04_READ_CONNECTIVITY + My M02_S04_READ_CONNECTIVITY + 1 + + + + true + + + + + + M02_S05_READ_CONNECTIVITY + My M02_S05_READ_CONNECTIVITY + 1 + + + + true + + + + + + M02_S06_READ_CONNECTIVITY + My M02_S06_READ_CONNECTIVITY + 1 + + + + true + + + + + + M02_S07_READ_CONNECTIVITY + My M02_S07_READ_CONNECTIVITY + 1 + + + + true + + + + + + M02_S08_READ_CONNECTIVITY + My M02_S08_READ_CONNECTIVITY + 1 + + + + true + + + + + + M02_S09_READ_CONNECTIVITY + My M02_S09_READ_CONNECTIVITY + 1 + + + + true + + + + + + M02_S10_READ_CONNECTIVITY + My M02_S10_READ_CONNECTIVITY + 1 + + + + true + + + + + + M02_S11_READ_CONNECTIVITY + My M02_S11_READ_CONNECTIVITY + 1 + + + + true + + + + + + M02_S12_READ_CONNECTIVITY + My M02_S12_READ_CONNECTIVITY + 1 + + + + true + + + + + + M02_S13_READ_CONNECTIVITY + My M02_S13_READ_CONNECTIVITY + 1 + + + + true + + + + + + M02_S14_READ_CONNECTIVITY + My M02_S14_READ_CONNECTIVITY + 1 + + + + true + + + + + + M02_S15_READ_CONNECTIVITY + My M02_S15_READ_CONNECTIVITY + 1 + + + + true + + + + + + M03_S00_READ_CONNECTIVITY + My M03_S00_READ_CONNECTIVITY + 1 + + + + true + + + + + + M03_S01_READ_CONNECTIVITY + My M03_S01_READ_CONNECTIVITY + 1 + + + + true + + + + + + M03_S02_READ_CONNECTIVITY + My M03_S02_READ_CONNECTIVITY + 1 + + + + true + + + + + + M03_S03_READ_CONNECTIVITY + My M03_S03_READ_CONNECTIVITY + 1 + + + + true + + + + + + M03_S04_READ_CONNECTIVITY + My M03_S04_READ_CONNECTIVITY + 1 + + + + true + + + + + + M03_S05_READ_CONNECTIVITY + My M03_S05_READ_CONNECTIVITY + 1 + + + + true + + + + + + M03_S06_READ_CONNECTIVITY + My M03_S06_READ_CONNECTIVITY + 1 + + + + true + + + + + + M03_S07_READ_CONNECTIVITY + My M03_S07_READ_CONNECTIVITY + 1 + + + + true + + + + + + M03_S08_READ_CONNECTIVITY + My M03_S08_READ_CONNECTIVITY + 1 + + + + true + + + + + + M03_S09_READ_CONNECTIVITY + My M03_S09_READ_CONNECTIVITY + 1 + + + + true + + + + + + M03_S10_READ_CONNECTIVITY + My M03_S10_READ_CONNECTIVITY + 1 + + + + true + + + + + + M03_S11_READ_CONNECTIVITY + My M03_S11_READ_CONNECTIVITY + 1 + + + + true + + + + + + M03_S12_READ_CONNECTIVITY + My M03_S12_READ_CONNECTIVITY + 1 + + + + true + + + + + + M03_S13_READ_CONNECTIVITY + My M03_S13_READ_CONNECTIVITY + 1 + + + + true + + + + + + M03_S14_READ_CONNECTIVITY + My M03_S14_READ_CONNECTIVITY + 1 + + + + true + + + + + + M03_S15_READ_CONNECTIVITY + My M03_S15_READ_CONNECTIVITY + 1 + + + + true + + + + + + M04_S00_READ_CONNECTIVITY + My M04_S00_READ_CONNECTIVITY + 1 + + + + true + + + + + + M04_S01_READ_CONNECTIVITY + My M04_S01_READ_CONNECTIVITY + 1 + + + + true + + + + + + M04_S02_READ_CONNECTIVITY + My M04_S02_READ_CONNECTIVITY + 1 + + + + true + + + + + + M04_S03_READ_CONNECTIVITY + My M04_S03_READ_CONNECTIVITY + 1 + + + + true + + + + + + M04_S04_READ_CONNECTIVITY + My M04_S04_READ_CONNECTIVITY + 1 + + + + true + + + + + + M04_S05_READ_CONNECTIVITY + My M04_S05_READ_CONNECTIVITY + 1 + + + + true + + + + + + M04_S06_READ_CONNECTIVITY + My M04_S06_READ_CONNECTIVITY + 1 + + + + true + + + + + + M04_S07_READ_CONNECTIVITY + My M04_S07_READ_CONNECTIVITY + 1 + + + + true + + + + + + M04_S08_READ_CONNECTIVITY + My M04_S08_READ_CONNECTIVITY + 1 + + + + true + + + + + + M04_S09_READ_CONNECTIVITY + My M04_S09_READ_CONNECTIVITY + 1 + + + + true + + + + + + M04_S10_READ_CONNECTIVITY + My M04_S10_READ_CONNECTIVITY + 1 + + + + true + + + + + + M04_S11_READ_CONNECTIVITY + My M04_S11_READ_CONNECTIVITY + 1 + + + + true + + + + + + M04_S12_READ_CONNECTIVITY + My M04_S12_READ_CONNECTIVITY + 1 + + + + true + + + + + + M04_S13_READ_CONNECTIVITY + My M04_S13_READ_CONNECTIVITY + 1 + + + + true + + + + + + M04_S14_READ_CONNECTIVITY + My M04_S14_READ_CONNECTIVITY + 1 + + + + true + + + + + + M04_S15_READ_CONNECTIVITY + My M04_S15_READ_CONNECTIVITY + 1 + + + + true + + + + + + M05_S00_READ_CONNECTIVITY + My M05_S00_READ_CONNECTIVITY + 1 + + + + true + + + + + + M05_S01_READ_CONNECTIVITY + My M05_S01_READ_CONNECTIVITY + 1 + + + + true + + + + + + M05_S02_READ_CONNECTIVITY + My M05_S02_READ_CONNECTIVITY + 1 + + + + true + + + + + + M05_S03_READ_CONNECTIVITY + My M05_S03_READ_CONNECTIVITY + 1 + + + + true + + + + + + M05_S04_READ_CONNECTIVITY + My M05_S04_READ_CONNECTIVITY + 1 + + + + true + + + + + + M05_S05_READ_CONNECTIVITY + My M05_S05_READ_CONNECTIVITY + 1 + + + + true + + + + + + M05_S06_READ_CONNECTIVITY + My M05_S06_READ_CONNECTIVITY + 1 + + + + true + + + + + + M05_S07_READ_CONNECTIVITY + My M05_S07_READ_CONNECTIVITY + 1 + + + + true + + + + + + M05_S08_READ_CONNECTIVITY + My M05_S08_READ_CONNECTIVITY + 1 + + + + true + + + + + + M05_S09_READ_CONNECTIVITY + My M05_S09_READ_CONNECTIVITY + 1 + + + + true + + + + + + M05_S10_READ_CONNECTIVITY + My M05_S10_READ_CONNECTIVITY + 1 + + + + true + + + + + + M05_S11_READ_CONNECTIVITY + My M05_S11_READ_CONNECTIVITY + 1 + + + + true + + + + + + M05_S12_READ_CONNECTIVITY + My M05_S12_READ_CONNECTIVITY + 1 + + + + true + + + + + + M05_S13_READ_CONNECTIVITY + My M05_S13_READ_CONNECTIVITY + 1 + + + + true + + + + + + M05_S14_READ_CONNECTIVITY + My M05_S14_READ_CONNECTIVITY + 1 + + + + true + + + + + + M05_S15_READ_CONNECTIVITY + My M05_S15_READ_CONNECTIVITY + 1 + + + + true + + + + + + M06_S00_READ_CONNECTIVITY + My M06_S00_READ_CONNECTIVITY + 1 + + + + true + + + + + + M06_S01_READ_CONNECTIVITY + My M06_S01_READ_CONNECTIVITY + 1 + + + + true + + + + + + M06_S02_READ_CONNECTIVITY + My M06_S02_READ_CONNECTIVITY + 1 + + + + true + + + + + + M06_S03_READ_CONNECTIVITY + My M06_S03_READ_CONNECTIVITY + 1 + + + + true + + + + + + M06_S04_READ_CONNECTIVITY + My M06_S04_READ_CONNECTIVITY + 1 + + + + true + + + + + + M06_S05_READ_CONNECTIVITY + My M06_S05_READ_CONNECTIVITY + 1 + + + + true + + + + + + M06_S06_READ_CONNECTIVITY + My M06_S06_READ_CONNECTIVITY + 1 + + + + true + + + + + + M06_S07_READ_CONNECTIVITY + My M06_S07_READ_CONNECTIVITY + 1 + + + + true + + + + + + M06_S08_READ_CONNECTIVITY + My M06_S08_READ_CONNECTIVITY + 1 + + + + true + + + + + + M06_S09_READ_CONNECTIVITY + My M06_S09_READ_CONNECTIVITY + 1 + + + + true + + + + + + M06_S10_READ_CONNECTIVITY + My M06_S10_READ_CONNECTIVITY + 1 + + + + true + + + + + + M06_S11_READ_CONNECTIVITY + My M06_S11_READ_CONNECTIVITY + 1 + + + + true + + + + + + M06_S12_READ_CONNECTIVITY + My M06_S12_READ_CONNECTIVITY + 1 + + + + true + + + + + + M06_S13_READ_CONNECTIVITY + My M06_S13_READ_CONNECTIVITY + 1 + + + + true + + + + + + M06_S14_READ_CONNECTIVITY + My M06_S14_READ_CONNECTIVITY + 1 + + + + true + + + + + + M06_S15_READ_CONNECTIVITY + My M06_S15_READ_CONNECTIVITY + 1 + + + + true + + + + + + M07_S00_READ_CONNECTIVITY + My M07_S00_READ_CONNECTIVITY + 1 + + + + true + + + + + + M07_S01_READ_CONNECTIVITY + My M07_S01_READ_CONNECTIVITY + 1 + + + + true + + + + + + M07_S02_READ_CONNECTIVITY + My M07_S02_READ_CONNECTIVITY + 1 + + + + true + + + + + + M07_S03_READ_CONNECTIVITY + My M07_S03_READ_CONNECTIVITY + 1 + + + + true + + + + + + M07_S04_READ_CONNECTIVITY + My M07_S04_READ_CONNECTIVITY + 1 + + + + true + + + + + + M07_S05_READ_CONNECTIVITY + My M07_S05_READ_CONNECTIVITY + 1 + + + + true + + + + + + M07_S06_READ_CONNECTIVITY + My M07_S06_READ_CONNECTIVITY + 1 + + + + true + + + + + + M07_S07_READ_CONNECTIVITY + My M07_S07_READ_CONNECTIVITY + 1 + + + + true + + + + + + M07_S08_READ_CONNECTIVITY + My M07_S08_READ_CONNECTIVITY + 1 + + + + true + + + + + + M07_S09_READ_CONNECTIVITY + My M07_S09_READ_CONNECTIVITY + 1 + + + + true + + + + + + M07_S10_READ_CONNECTIVITY + My M07_S10_READ_CONNECTIVITY + 1 + + + + true + + + + + + M07_S11_READ_CONNECTIVITY + My M07_S11_READ_CONNECTIVITY + 1 + + + + true + + + + + + M07_S12_READ_CONNECTIVITY + My M07_S12_READ_CONNECTIVITY + 1 + + + + true + + + + + + M07_S13_READ_CONNECTIVITY + My M07_S13_READ_CONNECTIVITY + 1 + + + + true + + + + + + M07_S14_READ_CONNECTIVITY + My M07_S14_READ_CONNECTIVITY + 1 + + + + true + + + + + + M07_S15_READ_CONNECTIVITY + My M07_S15_READ_CONNECTIVITY + 1 + + + + true + + + + + + M08_S00_READ_CONNECTIVITY + My M08_S00_READ_CONNECTIVITY + 1 + + + + true + + + + + + M08_S01_READ_CONNECTIVITY + My M08_S01_READ_CONNECTIVITY + 1 + + + + true + + + + + + M08_S02_READ_CONNECTIVITY + My M08_S02_READ_CONNECTIVITY + 1 + + + + true + + + + + + M08_S03_READ_CONNECTIVITY + My M08_S03_READ_CONNECTIVITY + 1 + + + + true + + + + + + M08_S04_READ_CONNECTIVITY + My M08_S04_READ_CONNECTIVITY + 1 + + + + true + + + + + + M08_S05_READ_CONNECTIVITY + My M08_S05_READ_CONNECTIVITY + 1 + + + + true + + + + + + M08_S06_READ_CONNECTIVITY + My M08_S06_READ_CONNECTIVITY + 1 + + + + true + + + + + + M08_S07_READ_CONNECTIVITY + My M08_S07_READ_CONNECTIVITY + 1 + + + + true + + + + + + M08_S08_READ_CONNECTIVITY + My M08_S08_READ_CONNECTIVITY + 1 + + + + true + + + + + + M08_S09_READ_CONNECTIVITY + My M08_S09_READ_CONNECTIVITY + 1 + + + + true + + + + + + M08_S10_READ_CONNECTIVITY + My M08_S10_READ_CONNECTIVITY + 1 + + + + true + + + + + + M08_S11_READ_CONNECTIVITY + My M08_S11_READ_CONNECTIVITY + 1 + + + + true + + + + + + M08_S12_READ_CONNECTIVITY + My M08_S12_READ_CONNECTIVITY + 1 + + + + true + + + + + + M08_S13_READ_CONNECTIVITY + My M08_S13_READ_CONNECTIVITY + 1 + + + + true + + + + + + M08_S14_READ_CONNECTIVITY + My M08_S14_READ_CONNECTIVITY + 1 + + + + true + + + + + + M08_S15_READ_CONNECTIVITY + My M08_S15_READ_CONNECTIVITY + 1 + + + + true + + + + + + M09_S00_READ_CONNECTIVITY + My M09_S00_READ_CONNECTIVITY + 1 + + + + true + + + + + + M09_S01_READ_CONNECTIVITY + My M09_S01_READ_CONNECTIVITY + 1 + + + + true + + + + + + M09_S02_READ_CONNECTIVITY + My M09_S02_READ_CONNECTIVITY + 1 + + + + true + + + + + + M09_S03_READ_CONNECTIVITY + My M09_S03_READ_CONNECTIVITY + 1 + + + + true + + + + + + M09_S04_READ_CONNECTIVITY + My M09_S04_READ_CONNECTIVITY + 1 + + + + true + + + + + + M09_S05_READ_CONNECTIVITY + My M09_S05_READ_CONNECTIVITY + 1 + + + + true + + + + + + M09_S06_READ_CONNECTIVITY + My M09_S06_READ_CONNECTIVITY + 1 + + + + true + + + + + + M09_S07_READ_CONNECTIVITY + My M09_S07_READ_CONNECTIVITY + 1 + + + + true + + + + + + M09_S08_READ_CONNECTIVITY + My M09_S08_READ_CONNECTIVITY + 1 + + + + true + + + + + + M09_S09_READ_CONNECTIVITY + My M09_S09_READ_CONNECTIVITY + 1 + + + + true + + + + + + M09_S10_READ_CONNECTIVITY + My M09_S10_READ_CONNECTIVITY + 1 + + + + true + + + + + + M09_S11_READ_CONNECTIVITY + My M09_S11_READ_CONNECTIVITY + 1 + + + + true + + + + + + M09_S12_READ_CONNECTIVITY + My M09_S12_READ_CONNECTIVITY + 1 + + + + true + + + + + + M09_S13_READ_CONNECTIVITY + My M09_S13_READ_CONNECTIVITY + 1 + + + + true + + + + + + M09_S14_READ_CONNECTIVITY + My M09_S14_READ_CONNECTIVITY + 1 + + + + true + + + + + + M09_S15_READ_CONNECTIVITY + My M09_S15_READ_CONNECTIVITY + 1 + + + + true + + + + + + M10_S00_READ_CONNECTIVITY + My M10_S00_READ_CONNECTIVITY + 1 + + + + true + + + + + + M10_S01_READ_CONNECTIVITY + My M10_S01_READ_CONNECTIVITY + 1 + + + + true + + + + + + M10_S02_READ_CONNECTIVITY + My M10_S02_READ_CONNECTIVITY + 1 + + + + true + + + + + + M10_S03_READ_CONNECTIVITY + My M10_S03_READ_CONNECTIVITY + 1 + + + + true + + + + + + M10_S04_READ_CONNECTIVITY + My M10_S04_READ_CONNECTIVITY + 1 + + + + true + + + + + + M10_S05_READ_CONNECTIVITY + My M10_S05_READ_CONNECTIVITY + 1 + + + + true + + + + + + M10_S06_READ_CONNECTIVITY + My M10_S06_READ_CONNECTIVITY + 1 + + + + true + + + + + + M10_S07_READ_CONNECTIVITY + My M10_S07_READ_CONNECTIVITY + 1 + + + + true + + + + + + M10_S08_READ_CONNECTIVITY + My M10_S08_READ_CONNECTIVITY + 1 + + + + true + + + + + + M10_S09_READ_CONNECTIVITY + My M10_S09_READ_CONNECTIVITY + 1 + + + + true + + + + + + M10_S10_READ_CONNECTIVITY + My M10_S10_READ_CONNECTIVITY + 1 + + + + true + + + + + + M10_S11_READ_CONNECTIVITY + My M10_S11_READ_CONNECTIVITY + 1 + + + + true + + + + + + M10_S12_READ_CONNECTIVITY + My M10_S12_READ_CONNECTIVITY + 1 + + + + true + + + + + + M10_S13_READ_CONNECTIVITY + My M10_S13_READ_CONNECTIVITY + 1 + + + + true + + + + + + M10_S14_READ_CONNECTIVITY + My M10_S14_READ_CONNECTIVITY + 1 + + + + true + + + + + + M10_S15_READ_CONNECTIVITY + My M10_S15_READ_CONNECTIVITY + 1 + + + + true + + + + + + M11_S00_READ_CONNECTIVITY + My M11_S00_READ_CONNECTIVITY + 1 + + + + true + + + + + + M11_S01_READ_CONNECTIVITY + My M11_S01_READ_CONNECTIVITY + 1 + + + + true + + + + + + M11_S02_READ_CONNECTIVITY + My M11_S02_READ_CONNECTIVITY + 1 + + + + true + + + + + + M11_S03_READ_CONNECTIVITY + My M11_S03_READ_CONNECTIVITY + 1 + + + + true + + + + + + M11_S04_READ_CONNECTIVITY + My M11_S04_READ_CONNECTIVITY + 1 + + + + true + + + + + + M11_S05_READ_CONNECTIVITY + My M11_S05_READ_CONNECTIVITY + 1 + + + + true + + + + + + M11_S06_READ_CONNECTIVITY + My M11_S06_READ_CONNECTIVITY + 1 + + + + true + + + + + + M11_S07_READ_CONNECTIVITY + My M11_S07_READ_CONNECTIVITY + 1 + + + + true + + + + + + M11_S08_READ_CONNECTIVITY + My M11_S08_READ_CONNECTIVITY + 1 + + + + true + + + + + + M11_S09_READ_CONNECTIVITY + My M11_S09_READ_CONNECTIVITY + 1 + + + + true + + + + + + M11_S10_READ_CONNECTIVITY + My M11_S10_READ_CONNECTIVITY + 1 + + + + true + + + + + + M11_S11_READ_CONNECTIVITY + My M11_S11_READ_CONNECTIVITY + 1 + + + + true + + + + + + M11_S12_READ_CONNECTIVITY + My M11_S12_READ_CONNECTIVITY + 1 + + + + true + + + + + + M11_S13_READ_CONNECTIVITY + My M11_S13_READ_CONNECTIVITY + 1 + + + + true + + + + + + M11_S14_READ_CONNECTIVITY + My M11_S14_READ_CONNECTIVITY + 1 + + + + true + + + + + + M11_S15_READ_CONNECTIVITY + My M11_S15_READ_CONNECTIVITY + 1 + + + + true + + + + + + M12_S00_READ_CONNECTIVITY + My M12_S00_READ_CONNECTIVITY + 1 + + + + true + + + + + + M12_S01_READ_CONNECTIVITY + My M12_S01_READ_CONNECTIVITY + 1 + + + + true + + + + + + M12_S02_READ_CONNECTIVITY + My M12_S02_READ_CONNECTIVITY + 1 + + + + true + + + + + + M12_S03_READ_CONNECTIVITY + My M12_S03_READ_CONNECTIVITY + 1 + + + + true + + + + + + M12_S04_READ_CONNECTIVITY + My M12_S04_READ_CONNECTIVITY + 1 + + + + true + + + + + + M12_S05_READ_CONNECTIVITY + My M12_S05_READ_CONNECTIVITY + 1 + + + + true + + + + + + M12_S06_READ_CONNECTIVITY + My M12_S06_READ_CONNECTIVITY + 1 + + + + true + + + + + + M12_S07_READ_CONNECTIVITY + My M12_S07_READ_CONNECTIVITY + 1 + + + + true + + + + + + M12_S08_READ_CONNECTIVITY + My M12_S08_READ_CONNECTIVITY + 1 + + + + true + + + + + + M12_S09_READ_CONNECTIVITY + My M12_S09_READ_CONNECTIVITY + 1 + + + + true + + + + + + M12_S10_READ_CONNECTIVITY + My M12_S10_READ_CONNECTIVITY + 1 + + + + true + + + + + + M12_S11_READ_CONNECTIVITY + My M12_S11_READ_CONNECTIVITY + 1 + + + + true + + + + + + M12_S12_READ_CONNECTIVITY + My M12_S12_READ_CONNECTIVITY + 1 + + + + true + + + + + + M12_S13_READ_CONNECTIVITY + My M12_S13_READ_CONNECTIVITY + 1 + + + + true + + + + + + M12_S14_READ_CONNECTIVITY + My M12_S14_READ_CONNECTIVITY + 1 + + + + true + + + + + + M12_S15_READ_CONNECTIVITY + My M12_S15_READ_CONNECTIVITY + 1 + + + + true + + + + + + M13_S00_READ_CONNECTIVITY + My M13_S00_READ_CONNECTIVITY + 1 + + + + true + + + + + + M13_S01_READ_CONNECTIVITY + My M13_S01_READ_CONNECTIVITY + 1 + + + + true + + + + + + M13_S02_READ_CONNECTIVITY + My M13_S02_READ_CONNECTIVITY + 1 + + + + true + + + + + + M13_S03_READ_CONNECTIVITY + My M13_S03_READ_CONNECTIVITY + 1 + + + + true + + + + + + M13_S04_READ_CONNECTIVITY + My M13_S04_READ_CONNECTIVITY + 1 + + + + true + + + + + + M13_S05_READ_CONNECTIVITY + My M13_S05_READ_CONNECTIVITY + 1 + + + + true + + + + + + M13_S06_READ_CONNECTIVITY + My M13_S06_READ_CONNECTIVITY + 1 + + + + true + + + + + + M13_S07_READ_CONNECTIVITY + My M13_S07_READ_CONNECTIVITY + 1 + + + + true + + + + + + M13_S08_READ_CONNECTIVITY + My M13_S08_READ_CONNECTIVITY + 1 + + + + true + + + + + + M13_S09_READ_CONNECTIVITY + My M13_S09_READ_CONNECTIVITY + 1 + + + + true + + + + + + M13_S10_READ_CONNECTIVITY + My M13_S10_READ_CONNECTIVITY + 1 + + + + true + + + + + + M13_S11_READ_CONNECTIVITY + My M13_S11_READ_CONNECTIVITY + 1 + + + + true + + + + + + M13_S12_READ_CONNECTIVITY + My M13_S12_READ_CONNECTIVITY + 1 + + + + true + + + + + + M13_S13_READ_CONNECTIVITY + My M13_S13_READ_CONNECTIVITY + 1 + + + + true + + + + + + M13_S14_READ_CONNECTIVITY + My M13_S14_READ_CONNECTIVITY + 1 + + + + true + + + + + + M13_S15_READ_CONNECTIVITY + My M13_S15_READ_CONNECTIVITY + 1 + + + + true + + + + + + M14_S00_READ_CONNECTIVITY + My M14_S00_READ_CONNECTIVITY + 1 + + + + true + + + + + + M14_S01_READ_CONNECTIVITY + My M14_S01_READ_CONNECTIVITY + 1 + + + + true + + + + + + M14_S02_READ_CONNECTIVITY + My M14_S02_READ_CONNECTIVITY + 1 + + + + true + + + + + + M14_S03_READ_CONNECTIVITY + My M14_S03_READ_CONNECTIVITY + 1 + + + + true + + + + + + M14_S04_READ_CONNECTIVITY + My M14_S04_READ_CONNECTIVITY + 1 + + + + true + + + + + + M14_S05_READ_CONNECTIVITY + My M14_S05_READ_CONNECTIVITY + 1 + + + + true + + + + + + M14_S06_READ_CONNECTIVITY + My M14_S06_READ_CONNECTIVITY + 1 + + + + true + + + + + + M14_S07_READ_CONNECTIVITY + My M14_S07_READ_CONNECTIVITY + 1 + + + + true + + + + + + M14_S08_READ_CONNECTIVITY + My M14_S08_READ_CONNECTIVITY + 1 + + + + true + + + + + + M14_S09_READ_CONNECTIVITY + My M14_S09_READ_CONNECTIVITY + 1 + + + + true + + + + + + M14_S10_READ_CONNECTIVITY + My M14_S10_READ_CONNECTIVITY + 1 + + + + true + + + + + + M14_S11_READ_CONNECTIVITY + My M14_S11_READ_CONNECTIVITY + 1 + + + + true + + + + + + M14_S12_READ_CONNECTIVITY + My M14_S12_READ_CONNECTIVITY + 1 + + + + true + + + + + + M14_S13_READ_CONNECTIVITY + My M14_S13_READ_CONNECTIVITY + 1 + + + + true + + + + + + M14_S14_READ_CONNECTIVITY + My M14_S14_READ_CONNECTIVITY + 1 + + + + true + + + + + + M14_S15_READ_CONNECTIVITY + My M14_S15_READ_CONNECTIVITY + 1 + + + + true + + + + + + M15_S00_READ_CONNECTIVITY + My M15_S00_READ_CONNECTIVITY + 1 + + + + true + + + + + + M15_S01_READ_CONNECTIVITY + My M15_S01_READ_CONNECTIVITY + 1 + + + + true + + + + + + M15_S02_READ_CONNECTIVITY + My M15_S02_READ_CONNECTIVITY + 1 + + + + true + + + + + + M15_S03_READ_CONNECTIVITY + My M15_S03_READ_CONNECTIVITY + 1 + + + + true + + + + + + M15_S04_READ_CONNECTIVITY + My M15_S04_READ_CONNECTIVITY + 1 + + + + true + + + + + + M15_S05_READ_CONNECTIVITY + My M15_S05_READ_CONNECTIVITY + 1 + + + + true + + + + + + M15_S06_READ_CONNECTIVITY + My M15_S06_READ_CONNECTIVITY + 1 + + + + true + + + + + + M15_S07_READ_CONNECTIVITY + My M15_S07_READ_CONNECTIVITY + 1 + + + + true + + + + + + M15_S08_READ_CONNECTIVITY + My M15_S08_READ_CONNECTIVITY + 1 + + + + true + + + + + + M15_S09_READ_CONNECTIVITY + My M15_S09_READ_CONNECTIVITY + 1 + + + + true + + + + + + M15_S10_READ_CONNECTIVITY + My M15_S10_READ_CONNECTIVITY + 1 + + + + true + + + + + + M15_S11_READ_CONNECTIVITY + My M15_S11_READ_CONNECTIVITY + 1 + + + + true + + + + + + M15_S12_READ_CONNECTIVITY + My M15_S12_READ_CONNECTIVITY + 1 + + + + true + + + + + + M15_S13_READ_CONNECTIVITY + My M15_S13_READ_CONNECTIVITY + 1 + + + + true + + + + + + M15_S14_READ_CONNECTIVITY + My M15_S14_READ_CONNECTIVITY + 1 + + + + true + + + + + + M15_S15_READ_CONNECTIVITY + My M15_S15_READ_CONNECTIVITY + 1 + + + + true + + + + + + M00_S00_WRITE_CONNECTIVITY + My M00_S00_WRITE_CONNECTIVITY + 0 + + + + true + + + + + + M00_S01_WRITE_CONNECTIVITY + My M00_S01_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M00_S02_WRITE_CONNECTIVITY + My M00_S02_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M00_S03_WRITE_CONNECTIVITY + My M00_S03_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M00_S04_WRITE_CONNECTIVITY + My M00_S04_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M00_S05_WRITE_CONNECTIVITY + My M00_S05_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M00_S06_WRITE_CONNECTIVITY + My M00_S06_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M00_S07_WRITE_CONNECTIVITY + My M00_S07_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M00_S08_WRITE_CONNECTIVITY + My M00_S08_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M00_S09_WRITE_CONNECTIVITY + My M00_S09_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M00_S10_WRITE_CONNECTIVITY + My M00_S10_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M00_S11_WRITE_CONNECTIVITY + My M00_S11_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M00_S12_WRITE_CONNECTIVITY + My M00_S12_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M00_S13_WRITE_CONNECTIVITY + My M00_S13_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M00_S14_WRITE_CONNECTIVITY + My M00_S14_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M00_S15_WRITE_CONNECTIVITY + My M00_S15_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M01_S00_WRITE_CONNECTIVITY + My M01_S00_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M01_S01_WRITE_CONNECTIVITY + My M01_S01_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M01_S02_WRITE_CONNECTIVITY + My M01_S02_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M01_S03_WRITE_CONNECTIVITY + My M01_S03_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M01_S04_WRITE_CONNECTIVITY + My M01_S04_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M01_S05_WRITE_CONNECTIVITY + My M01_S05_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M01_S06_WRITE_CONNECTIVITY + My M01_S06_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M01_S07_WRITE_CONNECTIVITY + My M01_S07_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M01_S08_WRITE_CONNECTIVITY + My M01_S08_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M01_S09_WRITE_CONNECTIVITY + My M01_S09_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M01_S10_WRITE_CONNECTIVITY + My M01_S10_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M01_S11_WRITE_CONNECTIVITY + My M01_S11_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M01_S12_WRITE_CONNECTIVITY + My M01_S12_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M01_S13_WRITE_CONNECTIVITY + My M01_S13_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M01_S14_WRITE_CONNECTIVITY + My M01_S14_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M01_S15_WRITE_CONNECTIVITY + My M01_S15_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M02_S00_WRITE_CONNECTIVITY + My M02_S00_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M02_S01_WRITE_CONNECTIVITY + My M02_S01_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M02_S02_WRITE_CONNECTIVITY + My M02_S02_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M02_S03_WRITE_CONNECTIVITY + My M02_S03_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M02_S04_WRITE_CONNECTIVITY + My M02_S04_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M02_S05_WRITE_CONNECTIVITY + My M02_S05_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M02_S06_WRITE_CONNECTIVITY + My M02_S06_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M02_S07_WRITE_CONNECTIVITY + My M02_S07_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M02_S08_WRITE_CONNECTIVITY + My M02_S08_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M02_S09_WRITE_CONNECTIVITY + My M02_S09_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M02_S10_WRITE_CONNECTIVITY + My M02_S10_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M02_S11_WRITE_CONNECTIVITY + My M02_S11_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M02_S12_WRITE_CONNECTIVITY + My M02_S12_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M02_S13_WRITE_CONNECTIVITY + My M02_S13_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M02_S14_WRITE_CONNECTIVITY + My M02_S14_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M02_S15_WRITE_CONNECTIVITY + My M02_S15_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M03_S00_WRITE_CONNECTIVITY + My M03_S00_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M03_S01_WRITE_CONNECTIVITY + My M03_S01_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M03_S02_WRITE_CONNECTIVITY + My M03_S02_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M03_S03_WRITE_CONNECTIVITY + My M03_S03_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M03_S04_WRITE_CONNECTIVITY + My M03_S04_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M03_S05_WRITE_CONNECTIVITY + My M03_S05_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M03_S06_WRITE_CONNECTIVITY + My M03_S06_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M03_S07_WRITE_CONNECTIVITY + My M03_S07_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M03_S08_WRITE_CONNECTIVITY + My M03_S08_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M03_S09_WRITE_CONNECTIVITY + My M03_S09_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M03_S10_WRITE_CONNECTIVITY + My M03_S10_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M03_S11_WRITE_CONNECTIVITY + My M03_S11_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M03_S12_WRITE_CONNECTIVITY + My M03_S12_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M03_S13_WRITE_CONNECTIVITY + My M03_S13_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M03_S14_WRITE_CONNECTIVITY + My M03_S14_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M03_S15_WRITE_CONNECTIVITY + My M03_S15_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M04_S00_WRITE_CONNECTIVITY + My M04_S00_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M04_S01_WRITE_CONNECTIVITY + My M04_S01_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M04_S02_WRITE_CONNECTIVITY + My M04_S02_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M04_S03_WRITE_CONNECTIVITY + My M04_S03_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M04_S04_WRITE_CONNECTIVITY + My M04_S04_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M04_S05_WRITE_CONNECTIVITY + My M04_S05_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M04_S06_WRITE_CONNECTIVITY + My M04_S06_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M04_S07_WRITE_CONNECTIVITY + My M04_S07_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M04_S08_WRITE_CONNECTIVITY + My M04_S08_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M04_S09_WRITE_CONNECTIVITY + My M04_S09_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M04_S10_WRITE_CONNECTIVITY + My M04_S10_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M04_S11_WRITE_CONNECTIVITY + My M04_S11_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M04_S12_WRITE_CONNECTIVITY + My M04_S12_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M04_S13_WRITE_CONNECTIVITY + My M04_S13_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M04_S14_WRITE_CONNECTIVITY + My M04_S14_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M04_S15_WRITE_CONNECTIVITY + My M04_S15_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M05_S00_WRITE_CONNECTIVITY + My M05_S00_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M05_S01_WRITE_CONNECTIVITY + My M05_S01_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M05_S02_WRITE_CONNECTIVITY + My M05_S02_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M05_S03_WRITE_CONNECTIVITY + My M05_S03_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M05_S04_WRITE_CONNECTIVITY + My M05_S04_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M05_S05_WRITE_CONNECTIVITY + My M05_S05_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M05_S06_WRITE_CONNECTIVITY + My M05_S06_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M05_S07_WRITE_CONNECTIVITY + My M05_S07_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M05_S08_WRITE_CONNECTIVITY + My M05_S08_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M05_S09_WRITE_CONNECTIVITY + My M05_S09_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M05_S10_WRITE_CONNECTIVITY + My M05_S10_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M05_S11_WRITE_CONNECTIVITY + My M05_S11_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M05_S12_WRITE_CONNECTIVITY + My M05_S12_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M05_S13_WRITE_CONNECTIVITY + My M05_S13_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M05_S14_WRITE_CONNECTIVITY + My M05_S14_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M05_S15_WRITE_CONNECTIVITY + My M05_S15_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M06_S00_WRITE_CONNECTIVITY + My M06_S00_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M06_S01_WRITE_CONNECTIVITY + My M06_S01_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M06_S02_WRITE_CONNECTIVITY + My M06_S02_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M06_S03_WRITE_CONNECTIVITY + My M06_S03_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M06_S04_WRITE_CONNECTIVITY + My M06_S04_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M06_S05_WRITE_CONNECTIVITY + My M06_S05_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M06_S06_WRITE_CONNECTIVITY + My M06_S06_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M06_S07_WRITE_CONNECTIVITY + My M06_S07_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M06_S08_WRITE_CONNECTIVITY + My M06_S08_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M06_S09_WRITE_CONNECTIVITY + My M06_S09_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M06_S10_WRITE_CONNECTIVITY + My M06_S10_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M06_S11_WRITE_CONNECTIVITY + My M06_S11_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M06_S12_WRITE_CONNECTIVITY + My M06_S12_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M06_S13_WRITE_CONNECTIVITY + My M06_S13_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M06_S14_WRITE_CONNECTIVITY + My M06_S14_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M06_S15_WRITE_CONNECTIVITY + My M06_S15_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M07_S00_WRITE_CONNECTIVITY + My M07_S00_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M07_S01_WRITE_CONNECTIVITY + My M07_S01_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M07_S02_WRITE_CONNECTIVITY + My M07_S02_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M07_S03_WRITE_CONNECTIVITY + My M07_S03_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M07_S04_WRITE_CONNECTIVITY + My M07_S04_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M07_S05_WRITE_CONNECTIVITY + My M07_S05_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M07_S06_WRITE_CONNECTIVITY + My M07_S06_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M07_S07_WRITE_CONNECTIVITY + My M07_S07_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M07_S08_WRITE_CONNECTIVITY + My M07_S08_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M07_S09_WRITE_CONNECTIVITY + My M07_S09_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M07_S10_WRITE_CONNECTIVITY + My M07_S10_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M07_S11_WRITE_CONNECTIVITY + My M07_S11_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M07_S12_WRITE_CONNECTIVITY + My M07_S12_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M07_S13_WRITE_CONNECTIVITY + My M07_S13_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M07_S14_WRITE_CONNECTIVITY + My M07_S14_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M07_S15_WRITE_CONNECTIVITY + My M07_S15_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M08_S00_WRITE_CONNECTIVITY + My M08_S00_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M08_S01_WRITE_CONNECTIVITY + My M08_S01_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M08_S02_WRITE_CONNECTIVITY + My M08_S02_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M08_S03_WRITE_CONNECTIVITY + My M08_S03_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M08_S04_WRITE_CONNECTIVITY + My M08_S04_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M08_S05_WRITE_CONNECTIVITY + My M08_S05_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M08_S06_WRITE_CONNECTIVITY + My M08_S06_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M08_S07_WRITE_CONNECTIVITY + My M08_S07_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M08_S08_WRITE_CONNECTIVITY + My M08_S08_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M08_S09_WRITE_CONNECTIVITY + My M08_S09_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M08_S10_WRITE_CONNECTIVITY + My M08_S10_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M08_S11_WRITE_CONNECTIVITY + My M08_S11_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M08_S12_WRITE_CONNECTIVITY + My M08_S12_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M08_S13_WRITE_CONNECTIVITY + My M08_S13_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M08_S14_WRITE_CONNECTIVITY + My M08_S14_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M08_S15_WRITE_CONNECTIVITY + My M08_S15_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M09_S00_WRITE_CONNECTIVITY + My M09_S00_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M09_S01_WRITE_CONNECTIVITY + My M09_S01_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M09_S02_WRITE_CONNECTIVITY + My M09_S02_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M09_S03_WRITE_CONNECTIVITY + My M09_S03_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M09_S04_WRITE_CONNECTIVITY + My M09_S04_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M09_S05_WRITE_CONNECTIVITY + My M09_S05_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M09_S06_WRITE_CONNECTIVITY + My M09_S06_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M09_S07_WRITE_CONNECTIVITY + My M09_S07_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M09_S08_WRITE_CONNECTIVITY + My M09_S08_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M09_S09_WRITE_CONNECTIVITY + My M09_S09_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M09_S10_WRITE_CONNECTIVITY + My M09_S10_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M09_S11_WRITE_CONNECTIVITY + My M09_S11_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M09_S12_WRITE_CONNECTIVITY + My M09_S12_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M09_S13_WRITE_CONNECTIVITY + My M09_S13_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M09_S14_WRITE_CONNECTIVITY + My M09_S14_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M09_S15_WRITE_CONNECTIVITY + My M09_S15_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M10_S00_WRITE_CONNECTIVITY + My M10_S00_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M10_S01_WRITE_CONNECTIVITY + My M10_S01_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M10_S02_WRITE_CONNECTIVITY + My M10_S02_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M10_S03_WRITE_CONNECTIVITY + My M10_S03_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M10_S04_WRITE_CONNECTIVITY + My M10_S04_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M10_S05_WRITE_CONNECTIVITY + My M10_S05_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M10_S06_WRITE_CONNECTIVITY + My M10_S06_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M10_S07_WRITE_CONNECTIVITY + My M10_S07_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M10_S08_WRITE_CONNECTIVITY + My M10_S08_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M10_S09_WRITE_CONNECTIVITY + My M10_S09_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M10_S10_WRITE_CONNECTIVITY + My M10_S10_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M10_S11_WRITE_CONNECTIVITY + My M10_S11_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M10_S12_WRITE_CONNECTIVITY + My M10_S12_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M10_S13_WRITE_CONNECTIVITY + My M10_S13_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M10_S14_WRITE_CONNECTIVITY + My M10_S14_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M10_S15_WRITE_CONNECTIVITY + My M10_S15_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M11_S00_WRITE_CONNECTIVITY + My M11_S00_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M11_S01_WRITE_CONNECTIVITY + My M11_S01_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M11_S02_WRITE_CONNECTIVITY + My M11_S02_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M11_S03_WRITE_CONNECTIVITY + My M11_S03_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M11_S04_WRITE_CONNECTIVITY + My M11_S04_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M11_S05_WRITE_CONNECTIVITY + My M11_S05_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M11_S06_WRITE_CONNECTIVITY + My M11_S06_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M11_S07_WRITE_CONNECTIVITY + My M11_S07_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M11_S08_WRITE_CONNECTIVITY + My M11_S08_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M11_S09_WRITE_CONNECTIVITY + My M11_S09_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M11_S10_WRITE_CONNECTIVITY + My M11_S10_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M11_S11_WRITE_CONNECTIVITY + My M11_S11_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M11_S12_WRITE_CONNECTIVITY + My M11_S12_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M11_S13_WRITE_CONNECTIVITY + My M11_S13_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M11_S14_WRITE_CONNECTIVITY + My M11_S14_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M11_S15_WRITE_CONNECTIVITY + My M11_S15_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M12_S00_WRITE_CONNECTIVITY + My M12_S00_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M12_S01_WRITE_CONNECTIVITY + My M12_S01_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M12_S02_WRITE_CONNECTIVITY + My M12_S02_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M12_S03_WRITE_CONNECTIVITY + My M12_S03_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M12_S04_WRITE_CONNECTIVITY + My M12_S04_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M12_S05_WRITE_CONNECTIVITY + My M12_S05_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M12_S06_WRITE_CONNECTIVITY + My M12_S06_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M12_S07_WRITE_CONNECTIVITY + My M12_S07_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M12_S08_WRITE_CONNECTIVITY + My M12_S08_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M12_S09_WRITE_CONNECTIVITY + My M12_S09_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M12_S10_WRITE_CONNECTIVITY + My M12_S10_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M12_S11_WRITE_CONNECTIVITY + My M12_S11_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M12_S12_WRITE_CONNECTIVITY + My M12_S12_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M12_S13_WRITE_CONNECTIVITY + My M12_S13_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M12_S14_WRITE_CONNECTIVITY + My M12_S14_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M12_S15_WRITE_CONNECTIVITY + My M12_S15_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M13_S00_WRITE_CONNECTIVITY + My M13_S00_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M13_S01_WRITE_CONNECTIVITY + My M13_S01_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M13_S02_WRITE_CONNECTIVITY + My M13_S02_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M13_S03_WRITE_CONNECTIVITY + My M13_S03_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M13_S04_WRITE_CONNECTIVITY + My M13_S04_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M13_S05_WRITE_CONNECTIVITY + My M13_S05_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M13_S06_WRITE_CONNECTIVITY + My M13_S06_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M13_S07_WRITE_CONNECTIVITY + My M13_S07_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M13_S08_WRITE_CONNECTIVITY + My M13_S08_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M13_S09_WRITE_CONNECTIVITY + My M13_S09_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M13_S10_WRITE_CONNECTIVITY + My M13_S10_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M13_S11_WRITE_CONNECTIVITY + My M13_S11_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M13_S12_WRITE_CONNECTIVITY + My M13_S12_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M13_S13_WRITE_CONNECTIVITY + My M13_S13_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M13_S14_WRITE_CONNECTIVITY + My M13_S14_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M13_S15_WRITE_CONNECTIVITY + My M13_S15_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M14_S00_WRITE_CONNECTIVITY + My M14_S00_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M14_S01_WRITE_CONNECTIVITY + My M14_S01_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M14_S02_WRITE_CONNECTIVITY + My M14_S02_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M14_S03_WRITE_CONNECTIVITY + My M14_S03_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M14_S04_WRITE_CONNECTIVITY + My M14_S04_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M14_S05_WRITE_CONNECTIVITY + My M14_S05_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M14_S06_WRITE_CONNECTIVITY + My M14_S06_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M14_S07_WRITE_CONNECTIVITY + My M14_S07_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M14_S08_WRITE_CONNECTIVITY + My M14_S08_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M14_S09_WRITE_CONNECTIVITY + My M14_S09_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M14_S10_WRITE_CONNECTIVITY + My M14_S10_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M14_S11_WRITE_CONNECTIVITY + My M14_S11_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M14_S12_WRITE_CONNECTIVITY + My M14_S12_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M14_S13_WRITE_CONNECTIVITY + My M14_S13_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M14_S14_WRITE_CONNECTIVITY + My M14_S14_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M14_S15_WRITE_CONNECTIVITY + My M14_S15_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M15_S00_WRITE_CONNECTIVITY + My M15_S00_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M15_S01_WRITE_CONNECTIVITY + My M15_S01_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M15_S02_WRITE_CONNECTIVITY + My M15_S02_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M15_S03_WRITE_CONNECTIVITY + My M15_S03_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M15_S04_WRITE_CONNECTIVITY + My M15_S04_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M15_S05_WRITE_CONNECTIVITY + My M15_S05_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M15_S06_WRITE_CONNECTIVITY + My M15_S06_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M15_S07_WRITE_CONNECTIVITY + My M15_S07_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M15_S08_WRITE_CONNECTIVITY + My M15_S08_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M15_S09_WRITE_CONNECTIVITY + My M15_S09_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M15_S10_WRITE_CONNECTIVITY + My M15_S10_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M15_S11_WRITE_CONNECTIVITY + My M15_S11_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M15_S12_WRITE_CONNECTIVITY + My M15_S12_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M15_S13_WRITE_CONNECTIVITY + My M15_S13_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M15_S14_WRITE_CONNECTIVITY + My M15_S14_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + M15_S15_WRITE_CONNECTIVITY + My M15_S15_WRITE_CONNECTIVITY + 1 + + + + true + + + + + + S00_THREAD_ID_WIDTH + My S00_THREAD_ID_WIDTH + 0 + + + + true + + + + + + S01_THREAD_ID_WIDTH + My S01_THREAD_ID_WIDTH + 0 + + + + true + + + + + + S02_THREAD_ID_WIDTH + My S02_THREAD_ID_WIDTH + 0 + + + + true + + + + + + S03_THREAD_ID_WIDTH + My S03_THREAD_ID_WIDTH + 0 + + + + true + + + + + + S04_THREAD_ID_WIDTH + My S04_THREAD_ID_WIDTH + 0 + + + + true + + + + + + S05_THREAD_ID_WIDTH + My S05_THREAD_ID_WIDTH + 0 + + + + true + + + + + + S06_THREAD_ID_WIDTH + My S06_THREAD_ID_WIDTH + 0 + + + + true + + + + + + S07_THREAD_ID_WIDTH + My S07_THREAD_ID_WIDTH + 0 + + + + true + + + + + + S08_THREAD_ID_WIDTH + My S08_THREAD_ID_WIDTH + 0 + + + + true + + + + + + S09_THREAD_ID_WIDTH + My S09_THREAD_ID_WIDTH + 0 + + + + true + + + + + + S10_THREAD_ID_WIDTH + My S10_THREAD_ID_WIDTH + 0 + + + + true + + + + + + S11_THREAD_ID_WIDTH + My S11_THREAD_ID_WIDTH + 0 + + + + true + + + + + + S12_THREAD_ID_WIDTH + My S12_THREAD_ID_WIDTH + 0 + + + + true + + + + + + S13_THREAD_ID_WIDTH + My S13_THREAD_ID_WIDTH + 0 + + + + true + + + + + + S14_THREAD_ID_WIDTH + My S14_THREAD_ID_WIDTH + 0 + + + + true + + + + + + S15_THREAD_ID_WIDTH + My S15_THREAD_ID_WIDTH + 0 + + + + true + + + + + + S00_WRITE_ACCEPTANCE + My S00_WRITE_ACCEPTANCE + 2 + + + + true + + + + + + S01_WRITE_ACCEPTANCE + My S01_WRITE_ACCEPTANCE + 2 + + + + true + + + + + + S02_WRITE_ACCEPTANCE + My S02_WRITE_ACCEPTANCE + 2 + + + + true + + + + + + S03_WRITE_ACCEPTANCE + My S03_WRITE_ACCEPTANCE + 2 + + + + true + + + + + + S04_WRITE_ACCEPTANCE + My S04_WRITE_ACCEPTANCE + 2 + + + + true + + + + + + S05_WRITE_ACCEPTANCE + My S05_WRITE_ACCEPTANCE + 2 + + + + true + + + + + + S06_WRITE_ACCEPTANCE + My S06_WRITE_ACCEPTANCE + 2 + + + + true + + + + + + S07_WRITE_ACCEPTANCE + My S07_WRITE_ACCEPTANCE + 2 + + + + true + + + + + + S08_WRITE_ACCEPTANCE + My S08_WRITE_ACCEPTANCE + 2 + + + + true + + + + + + S09_WRITE_ACCEPTANCE + My S09_WRITE_ACCEPTANCE + 2 + + + + true + + + + + + S10_WRITE_ACCEPTANCE + My S10_WRITE_ACCEPTANCE + 2 + + + + true + + + + + + S11_WRITE_ACCEPTANCE + My S11_WRITE_ACCEPTANCE + 2 + + + + true + + + + + + S12_WRITE_ACCEPTANCE + My S12_WRITE_ACCEPTANCE + 2 + + + + true + + + + + + S13_WRITE_ACCEPTANCE + My S13_WRITE_ACCEPTANCE + 2 + + + + true + + + + + + S14_WRITE_ACCEPTANCE + My S14_WRITE_ACCEPTANCE + 2 + + + + true + + + + + + S15_WRITE_ACCEPTANCE + My S15_WRITE_ACCEPTANCE + 2 + + + + true + + + + + + S00_READ_ACCEPTANCE + My S00_READ_ACCEPTANCE + 2 + + + + true + + + + + + S01_READ_ACCEPTANCE + My S01_READ_ACCEPTANCE + 2 + + + + true + + + + + + S02_READ_ACCEPTANCE + My S02_READ_ACCEPTANCE + 2 + + + + true + + + + + + S03_READ_ACCEPTANCE + My S03_READ_ACCEPTANCE + 2 + + + + true + + + + + + S04_READ_ACCEPTANCE + My S04_READ_ACCEPTANCE + 2 + + + + true + + + + + + S05_READ_ACCEPTANCE + My S05_READ_ACCEPTANCE + 2 + + + + true + + + + + + S06_READ_ACCEPTANCE + My S06_READ_ACCEPTANCE + 2 + + + + true + + + + + + S07_READ_ACCEPTANCE + My S07_READ_ACCEPTANCE + 2 + + + + true + + + + + + S08_READ_ACCEPTANCE + My S08_READ_ACCEPTANCE + 2 + + + + true + + + + + + S09_READ_ACCEPTANCE + My S09_READ_ACCEPTANCE + 2 + + + + true + + + + + + S10_READ_ACCEPTANCE + My S10_READ_ACCEPTANCE + 2 + + + + true + + + + + + S11_READ_ACCEPTANCE + My S11_READ_ACCEPTANCE + 2 + + + + true + + + + + + S12_READ_ACCEPTANCE + My S12_READ_ACCEPTANCE + 2 + + + + true + + + + + + S13_READ_ACCEPTANCE + My S13_READ_ACCEPTANCE + 2 + + + + true + + + + + + S14_READ_ACCEPTANCE + My S14_READ_ACCEPTANCE + 2 + + + + true + + + + + + S15_READ_ACCEPTANCE + My S15_READ_ACCEPTANCE + 2 + + + + true + + + + + + M00_WRITE_ISSUING + My M00_WRITE_ISSUING + 8 + + + + true + + + + + + M01_WRITE_ISSUING + My M01_WRITE_ISSUING + 4 + + + + true + + + + + + M02_WRITE_ISSUING + My M02_WRITE_ISSUING + 4 + + + + true + + + + + + M03_WRITE_ISSUING + My M03_WRITE_ISSUING + 4 + + + + true + + + + + + M04_WRITE_ISSUING + My M04_WRITE_ISSUING + 4 + + + + true + + + + + + M05_WRITE_ISSUING + My M05_WRITE_ISSUING + 4 + + + + true + + + + + + M06_WRITE_ISSUING + My M06_WRITE_ISSUING + 4 + + + + true + + + + + + M07_WRITE_ISSUING + My M07_WRITE_ISSUING + 4 + + + + true + + + + + + M08_WRITE_ISSUING + My M08_WRITE_ISSUING + 4 + + + + true + + + + + + M09_WRITE_ISSUING + My M09_WRITE_ISSUING + 4 + + + + true + + + + + + M10_WRITE_ISSUING + My M10_WRITE_ISSUING + 4 + + + + true + + + + + + M11_WRITE_ISSUING + My M11_WRITE_ISSUING + 4 + + + + true + + + + + + M12_WRITE_ISSUING + My M12_WRITE_ISSUING + 4 + + + + true + + + + + + M13_WRITE_ISSUING + My M13_WRITE_ISSUING + 4 + + + + true + + + + + + M14_WRITE_ISSUING + My M14_WRITE_ISSUING + 4 + + + + true + + + + + + M15_WRITE_ISSUING + My M15_WRITE_ISSUING + 4 + + + + true + + + + + + M00_READ_ISSUING + My M00_READ_ISSUING + 8 + + + + true + + + + + + M01_READ_ISSUING + My M01_READ_ISSUING + 4 + + + + true + + + + + + M02_READ_ISSUING + My M02_READ_ISSUING + 4 + + + + true + + + + + + M03_READ_ISSUING + My M03_READ_ISSUING + 4 + + + + true + + + + + + M04_READ_ISSUING + My M04_READ_ISSUING + 4 + + + + true + + + + + + M05_READ_ISSUING + My M05_READ_ISSUING + 4 + + + + true + + + + + + M06_READ_ISSUING + My M06_READ_ISSUING + 4 + + + + true + + + + + + M07_READ_ISSUING + My M07_READ_ISSUING + 4 + + + + true + + + + + + M08_READ_ISSUING + My M08_READ_ISSUING + 4 + + + + true + + + + + + M09_READ_ISSUING + My M09_READ_ISSUING + 4 + + + + true + + + + + + M10_READ_ISSUING + My M10_READ_ISSUING + 4 + + + + true + + + + + + M11_READ_ISSUING + My M11_READ_ISSUING + 4 + + + + true + + + + + + M12_READ_ISSUING + My M12_READ_ISSUING + 4 + + + + true + + + + + + M13_READ_ISSUING + My M13_READ_ISSUING + 4 + + + + true + + + + + + M14_READ_ISSUING + My M14_READ_ISSUING + 4 + + + + true + + + + + + M15_READ_ISSUING + My M15_READ_ISSUING + 4 + + + + true + + + + + + S00_ARB_PRIORITY + My S00_ARB_PRIORITY + 0 + + + + true + + + + + + S01_ARB_PRIORITY + My S01_ARB_PRIORITY + 0 + + + + true + + + + + + S02_ARB_PRIORITY + My S02_ARB_PRIORITY + 0 + + + + true + + + + + + S03_ARB_PRIORITY + My S03_ARB_PRIORITY + 0 + + + + true + + + + + + S04_ARB_PRIORITY + My S04_ARB_PRIORITY + 0 + + + + true + + + + + + S05_ARB_PRIORITY + My S05_ARB_PRIORITY + 0 + + + + true + + + + + + S06_ARB_PRIORITY + My S06_ARB_PRIORITY + 0 + + + + true + + + + + + S07_ARB_PRIORITY + My S07_ARB_PRIORITY + 0 + + + + true + + + + + + S08_ARB_PRIORITY + My S08_ARB_PRIORITY + 0 + + + + true + + + + + + S09_ARB_PRIORITY + My S09_ARB_PRIORITY + 0 + + + + true + + + + + + S10_ARB_PRIORITY + My S10_ARB_PRIORITY + 0 + + + + true + + + + + + S11_ARB_PRIORITY + My S11_ARB_PRIORITY + 0 + + + + true + + + + + + S12_ARB_PRIORITY + My S12_ARB_PRIORITY + 0 + + + + true + + + + + + S13_ARB_PRIORITY + My S13_ARB_PRIORITY + 0 + + + + true + + + + + + S14_ARB_PRIORITY + My S14_ARB_PRIORITY + 0 + + + + true + + + + + + S15_ARB_PRIORITY + My S15_ARB_PRIORITY + 0 + + + + true + + + + + + M00_ERR_MODE + My M00_ERR_MODE + 0 + + + + true + + + + + + M01_ERR_MODE + My M01_ERR_MODE + 0 + + + + true + + + + + + M02_ERR_MODE + My M02_ERR_MODE + 0 + + + + true + + + + + + M03_ERR_MODE + My M03_ERR_MODE + 0 + + + + true + + + + + + M04_ERR_MODE + My M04_ERR_MODE + 0 + + + + true + + + + + + M05_ERR_MODE + My M05_ERR_MODE + 0 + + + + true + + + + + + M06_ERR_MODE + My M06_ERR_MODE + 0 + + + + true + + + + + + M07_ERR_MODE + My M07_ERR_MODE + 0 + + + + true + + + + + + M08_ERR_MODE + My M08_ERR_MODE + 0 + + + + true + + + + + + M09_ERR_MODE + My M09_ERR_MODE + 0 + + + + true + + + + + + M10_ERR_MODE + My M10_ERR_MODE + 0 + + + + true + + + + + + M11_ERR_MODE + My M11_ERR_MODE + 0 + + + + true + + + + + + M12_ERR_MODE + My M12_ERR_MODE + 0 + + + + true + + + + + + M13_ERR_MODE + My M13_ERR_MODE + 0 + + + + true + + + + + + M14_ERR_MODE + My M14_ERR_MODE + 0 + + + + true + + + + + + M15_ERR_MODE + My M15_ERR_MODE + 0 + + + + true + + + + + + S00_SINGLE_THREAD + My S00_SINGLE_THREAD + 0 + + + + true + + + + + + S01_SINGLE_THREAD + My S01_SINGLE_THREAD + 0 + + + + true + + + + + + S02_SINGLE_THREAD + My S02_SINGLE_THREAD + 0 + + + + true + + + + + + S03_SINGLE_THREAD + My S03_SINGLE_THREAD + 0 + + + + true + + + + + + S04_SINGLE_THREAD + My S04_SINGLE_THREAD + 0 + + + + true + + + + + + S05_SINGLE_THREAD + My S05_SINGLE_THREAD + 0 + + + + true + + + + + + S06_SINGLE_THREAD + My S06_SINGLE_THREAD + 0 + + + + true + + + + + + S07_SINGLE_THREAD + My S07_SINGLE_THREAD + 0 + + + + true + + + + + + S08_SINGLE_THREAD + My S08_SINGLE_THREAD + 0 + + + + true + + + + + + S09_SINGLE_THREAD + My S09_SINGLE_THREAD + 0 + + + + true + + + + + + S10_SINGLE_THREAD + My S10_SINGLE_THREAD + 0 + + + + true + + + + + + S11_SINGLE_THREAD + My S11_SINGLE_THREAD + 0 + + + + true + + + + + + S12_SINGLE_THREAD + My S12_SINGLE_THREAD + 0 + + + + true + + + + + + S13_SINGLE_THREAD + My S13_SINGLE_THREAD + 0 + + + + true + + + + + + S14_SINGLE_THREAD + My S14_SINGLE_THREAD + 0 + + + + true + + + + + + S15_SINGLE_THREAD + My S15_SINGLE_THREAD + 0 + + + + true + + + + + + M00_SECURE + My M00_SECURE + 0 + + + + true + + + + + + M01_SECURE + My M01_SECURE + 0 + + + + true + + + + + + M02_SECURE + My M02_SECURE + 0 + + + + true + + + + + + M03_SECURE + My M03_SECURE + 0 + + + + true + + + + + + M04_SECURE + My M04_SECURE + 0 + + + + true + + + + + + M05_SECURE + My M05_SECURE + 0 + + + + true + + + + + + M06_SECURE + My M06_SECURE + 0 + + + + true + + + + + + M07_SECURE + My M07_SECURE + 0 + + + + true + + + + + + M08_SECURE + My M08_SECURE + 0 + + + + true + + + + + + M09_SECURE + My M09_SECURE + 0 + + + + true + + + + + + M10_SECURE + My M10_SECURE + 0 + + + + true + + + + + + M11_SECURE + My M11_SECURE + 0 + + + + true + + + + + + M12_SECURE + My M12_SECURE + 0 + + + + true + + + + + + M13_SECURE + My M13_SECURE + 0 + + + + true + + + + + + M14_SECURE + My M14_SECURE + 0 + + + + true + + + + + + M15_SECURE + My M15_SECURE + 0 + + + + true + + + + + + S00_BASE_ID + My S00_BASE_ID + 0x00000000 + + + + true + + + + + + S01_BASE_ID + My S01_BASE_ID + 0x00000001 + + + + true + + + + + + S02_BASE_ID + My S02_BASE_ID + 0x00000002 + + + + true + + + + + + S03_BASE_ID + My S03_BASE_ID + 0x00000003 + + + + true + + + + + + S04_BASE_ID + My S04_BASE_ID + 0x00000004 + + + + true + + + + + + S05_BASE_ID + My S05_BASE_ID + 0x00000005 + + + + true + + + + + + S06_BASE_ID + My S06_BASE_ID + 0x00000006 + + + + true + + + + + + S07_BASE_ID + My S07_BASE_ID + 0x00000007 + + + + true + + + + + + S08_BASE_ID + My S08_BASE_ID + 0x00000008 + + + + true + + + + + + S09_BASE_ID + My S09_BASE_ID + 0x00000009 + + + + true + + + + + + S10_BASE_ID + My S10_BASE_ID + 0x0000000a + + + + true + + + + + + S11_BASE_ID + My S11_BASE_ID + 0x0000000b + + + + true + + + + + + S12_BASE_ID + My S12_BASE_ID + 0x0000000c + + + + true + + + + + + S13_BASE_ID + My S13_BASE_ID + 0x0000000d + + + + true + + + + + + S14_BASE_ID + My S14_BASE_ID + 0x0000000e + + + + true + + + + + + S15_BASE_ID + My S15_BASE_ID + 0x0000000f + + + + true + + + + + + M00_A00_BASE_ADDR + My M00_A00_BASE_ADDR + 0x0000000000000000 + + + + true + + + + + + M00_A01_BASE_ADDR + My M00_A01_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M00_A02_BASE_ADDR + My M00_A02_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M00_A03_BASE_ADDR + My M00_A03_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M00_A04_BASE_ADDR + My M00_A04_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M00_A05_BASE_ADDR + My M00_A05_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M00_A06_BASE_ADDR + My M00_A06_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M00_A07_BASE_ADDR + My M00_A07_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M00_A08_BASE_ADDR + My M00_A08_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M00_A09_BASE_ADDR + My M00_A09_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M00_A10_BASE_ADDR + My M00_A10_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M00_A11_BASE_ADDR + My M00_A11_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M00_A12_BASE_ADDR + My M00_A12_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M00_A13_BASE_ADDR + My M00_A13_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M00_A14_BASE_ADDR + My M00_A14_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M00_A15_BASE_ADDR + My M00_A15_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M01_A00_BASE_ADDR + My M01_A00_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M01_A01_BASE_ADDR + My M01_A01_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M01_A02_BASE_ADDR + My M01_A02_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M01_A03_BASE_ADDR + My M01_A03_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M01_A04_BASE_ADDR + My M01_A04_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M01_A05_BASE_ADDR + My M01_A05_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M01_A06_BASE_ADDR + My M01_A06_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M01_A07_BASE_ADDR + My M01_A07_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M01_A08_BASE_ADDR + My M01_A08_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M01_A09_BASE_ADDR + My M01_A09_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M01_A10_BASE_ADDR + My M01_A10_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M01_A11_BASE_ADDR + My M01_A11_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M01_A12_BASE_ADDR + My M01_A12_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M01_A13_BASE_ADDR + My M01_A13_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M01_A14_BASE_ADDR + My M01_A14_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M01_A15_BASE_ADDR + My M01_A15_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M02_A00_BASE_ADDR + My M02_A00_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M02_A01_BASE_ADDR + My M02_A01_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M02_A02_BASE_ADDR + My M02_A02_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M02_A03_BASE_ADDR + My M02_A03_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M02_A04_BASE_ADDR + My M02_A04_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M02_A05_BASE_ADDR + My M02_A05_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M02_A06_BASE_ADDR + My M02_A06_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M02_A07_BASE_ADDR + My M02_A07_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M02_A08_BASE_ADDR + My M02_A08_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M02_A09_BASE_ADDR + My M02_A09_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M02_A10_BASE_ADDR + My M02_A10_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M02_A11_BASE_ADDR + My M02_A11_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M02_A12_BASE_ADDR + My M02_A12_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M02_A13_BASE_ADDR + My M02_A13_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M02_A14_BASE_ADDR + My M02_A14_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M02_A15_BASE_ADDR + My M02_A15_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M03_A00_BASE_ADDR + My M03_A00_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M03_A01_BASE_ADDR + My M03_A01_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M03_A02_BASE_ADDR + My M03_A02_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M03_A03_BASE_ADDR + My M03_A03_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M03_A04_BASE_ADDR + My M03_A04_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M03_A05_BASE_ADDR + My M03_A05_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M03_A06_BASE_ADDR + My M03_A06_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M03_A07_BASE_ADDR + My M03_A07_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M03_A08_BASE_ADDR + My M03_A08_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M03_A09_BASE_ADDR + My M03_A09_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M03_A10_BASE_ADDR + My M03_A10_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M03_A11_BASE_ADDR + My M03_A11_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M03_A12_BASE_ADDR + My M03_A12_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M03_A13_BASE_ADDR + My M03_A13_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M03_A14_BASE_ADDR + My M03_A14_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M03_A15_BASE_ADDR + My M03_A15_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M04_A00_BASE_ADDR + My M04_A00_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M04_A01_BASE_ADDR + My M04_A01_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M04_A02_BASE_ADDR + My M04_A02_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M04_A03_BASE_ADDR + My M04_A03_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M04_A04_BASE_ADDR + My M04_A04_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M04_A05_BASE_ADDR + My M04_A05_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M04_A06_BASE_ADDR + My M04_A06_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M04_A07_BASE_ADDR + My M04_A07_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M04_A08_BASE_ADDR + My M04_A08_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M04_A09_BASE_ADDR + My M04_A09_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M04_A10_BASE_ADDR + My M04_A10_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M04_A11_BASE_ADDR + My M04_A11_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M04_A12_BASE_ADDR + My M04_A12_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M04_A13_BASE_ADDR + My M04_A13_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M04_A14_BASE_ADDR + My M04_A14_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M04_A15_BASE_ADDR + My M04_A15_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M05_A00_BASE_ADDR + My M05_A00_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M05_A01_BASE_ADDR + My M05_A01_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M05_A02_BASE_ADDR + My M05_A02_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M05_A03_BASE_ADDR + My M05_A03_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M05_A04_BASE_ADDR + My M05_A04_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M05_A05_BASE_ADDR + My M05_A05_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M05_A06_BASE_ADDR + My M05_A06_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M05_A07_BASE_ADDR + My M05_A07_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M05_A08_BASE_ADDR + My M05_A08_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M05_A09_BASE_ADDR + My M05_A09_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M05_A10_BASE_ADDR + My M05_A10_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M05_A11_BASE_ADDR + My M05_A11_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M05_A12_BASE_ADDR + My M05_A12_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M05_A13_BASE_ADDR + My M05_A13_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M05_A14_BASE_ADDR + My M05_A14_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M05_A15_BASE_ADDR + My M05_A15_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M06_A00_BASE_ADDR + My M06_A00_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M06_A01_BASE_ADDR + My M06_A01_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M06_A02_BASE_ADDR + My M06_A02_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M06_A03_BASE_ADDR + My M06_A03_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M06_A04_BASE_ADDR + My M06_A04_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M06_A05_BASE_ADDR + My M06_A05_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M06_A06_BASE_ADDR + My M06_A06_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M06_A07_BASE_ADDR + My M06_A07_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M06_A08_BASE_ADDR + My M06_A08_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M06_A09_BASE_ADDR + My M06_A09_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M06_A10_BASE_ADDR + My M06_A10_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M06_A11_BASE_ADDR + My M06_A11_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M06_A12_BASE_ADDR + My M06_A12_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M06_A13_BASE_ADDR + My M06_A13_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M06_A14_BASE_ADDR + My M06_A14_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M06_A15_BASE_ADDR + My M06_A15_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M07_A00_BASE_ADDR + My M07_A00_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M07_A01_BASE_ADDR + My M07_A01_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M07_A02_BASE_ADDR + My M07_A02_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M07_A03_BASE_ADDR + My M07_A03_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M07_A04_BASE_ADDR + My M07_A04_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M07_A05_BASE_ADDR + My M07_A05_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M07_A06_BASE_ADDR + My M07_A06_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M07_A07_BASE_ADDR + My M07_A07_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M07_A08_BASE_ADDR + My M07_A08_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M07_A09_BASE_ADDR + My M07_A09_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M07_A10_BASE_ADDR + My M07_A10_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M07_A11_BASE_ADDR + My M07_A11_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M07_A12_BASE_ADDR + My M07_A12_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M07_A13_BASE_ADDR + My M07_A13_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M07_A14_BASE_ADDR + My M07_A14_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M07_A15_BASE_ADDR + My M07_A15_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M08_A00_BASE_ADDR + My M08_A00_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M08_A01_BASE_ADDR + My M08_A01_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M08_A02_BASE_ADDR + My M08_A02_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M08_A03_BASE_ADDR + My M08_A03_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M08_A04_BASE_ADDR + My M08_A04_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M08_A05_BASE_ADDR + My M08_A05_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M08_A06_BASE_ADDR + My M08_A06_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M08_A07_BASE_ADDR + My M08_A07_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M08_A08_BASE_ADDR + My M08_A08_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M08_A09_BASE_ADDR + My M08_A09_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M08_A10_BASE_ADDR + My M08_A10_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M08_A11_BASE_ADDR + My M08_A11_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M08_A12_BASE_ADDR + My M08_A12_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M08_A13_BASE_ADDR + My M08_A13_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M08_A14_BASE_ADDR + My M08_A14_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M08_A15_BASE_ADDR + My M08_A15_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M09_A00_BASE_ADDR + My M09_A00_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M09_A01_BASE_ADDR + My M09_A01_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M09_A02_BASE_ADDR + My M09_A02_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M09_A03_BASE_ADDR + My M09_A03_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M09_A04_BASE_ADDR + My M09_A04_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M09_A05_BASE_ADDR + My M09_A05_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M09_A06_BASE_ADDR + My M09_A06_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M09_A07_BASE_ADDR + My M09_A07_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M09_A08_BASE_ADDR + My M09_A08_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M09_A09_BASE_ADDR + My M09_A09_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M09_A10_BASE_ADDR + My M09_A10_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M09_A11_BASE_ADDR + My M09_A11_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M09_A12_BASE_ADDR + My M09_A12_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M09_A13_BASE_ADDR + My M09_A13_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M09_A14_BASE_ADDR + My M09_A14_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M09_A15_BASE_ADDR + My M09_A15_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M10_A00_BASE_ADDR + My M10_A00_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M10_A01_BASE_ADDR + My M10_A01_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M10_A02_BASE_ADDR + My M10_A02_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M10_A03_BASE_ADDR + My M10_A03_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M10_A04_BASE_ADDR + My M10_A04_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M10_A05_BASE_ADDR + My M10_A05_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M10_A06_BASE_ADDR + My M10_A06_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M10_A07_BASE_ADDR + My M10_A07_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M10_A08_BASE_ADDR + My M10_A08_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M10_A09_BASE_ADDR + My M10_A09_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M10_A10_BASE_ADDR + My M10_A10_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M10_A11_BASE_ADDR + My M10_A11_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M10_A12_BASE_ADDR + My M10_A12_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M10_A13_BASE_ADDR + My M10_A13_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M10_A14_BASE_ADDR + My M10_A14_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M10_A15_BASE_ADDR + My M10_A15_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M11_A00_BASE_ADDR + My M11_A00_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M11_A01_BASE_ADDR + My M11_A01_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M11_A02_BASE_ADDR + My M11_A02_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M11_A03_BASE_ADDR + My M11_A03_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M11_A04_BASE_ADDR + My M11_A04_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M11_A05_BASE_ADDR + My M11_A05_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M11_A06_BASE_ADDR + My M11_A06_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M11_A07_BASE_ADDR + My M11_A07_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M11_A08_BASE_ADDR + My M11_A08_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M11_A09_BASE_ADDR + My M11_A09_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M11_A10_BASE_ADDR + My M11_A10_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M11_A11_BASE_ADDR + My M11_A11_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M11_A12_BASE_ADDR + My M11_A12_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M11_A13_BASE_ADDR + My M11_A13_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M11_A14_BASE_ADDR + My M11_A14_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M11_A15_BASE_ADDR + My M11_A15_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M12_A00_BASE_ADDR + My M12_A00_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M12_A01_BASE_ADDR + My M12_A01_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M12_A02_BASE_ADDR + My M12_A02_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M12_A03_BASE_ADDR + My M12_A03_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M12_A04_BASE_ADDR + My M12_A04_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M12_A05_BASE_ADDR + My M12_A05_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M12_A06_BASE_ADDR + My M12_A06_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M12_A07_BASE_ADDR + My M12_A07_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M12_A08_BASE_ADDR + My M12_A08_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M12_A09_BASE_ADDR + My M12_A09_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M12_A10_BASE_ADDR + My M12_A10_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M12_A11_BASE_ADDR + My M12_A11_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M12_A12_BASE_ADDR + My M12_A12_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M12_A13_BASE_ADDR + My M12_A13_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M12_A14_BASE_ADDR + My M12_A14_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M12_A15_BASE_ADDR + My M12_A15_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M13_A00_BASE_ADDR + My M13_A00_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M13_A01_BASE_ADDR + My M13_A01_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M13_A02_BASE_ADDR + My M13_A02_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M13_A03_BASE_ADDR + My M13_A03_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M13_A04_BASE_ADDR + My M13_A04_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M13_A05_BASE_ADDR + My M13_A05_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M13_A06_BASE_ADDR + My M13_A06_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M13_A07_BASE_ADDR + My M13_A07_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M13_A08_BASE_ADDR + My M13_A08_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M13_A09_BASE_ADDR + My M13_A09_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M13_A10_BASE_ADDR + My M13_A10_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M13_A11_BASE_ADDR + My M13_A11_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M13_A12_BASE_ADDR + My M13_A12_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M13_A13_BASE_ADDR + My M13_A13_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M13_A14_BASE_ADDR + My M13_A14_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M13_A15_BASE_ADDR + My M13_A15_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M14_A00_BASE_ADDR + My M14_A00_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M14_A01_BASE_ADDR + My M14_A01_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M14_A02_BASE_ADDR + My M14_A02_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M14_A03_BASE_ADDR + My M14_A03_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M14_A04_BASE_ADDR + My M14_A04_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M14_A05_BASE_ADDR + My M14_A05_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M14_A06_BASE_ADDR + My M14_A06_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M14_A07_BASE_ADDR + My M14_A07_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M14_A08_BASE_ADDR + My M14_A08_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M14_A09_BASE_ADDR + My M14_A09_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M14_A10_BASE_ADDR + My M14_A10_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M14_A11_BASE_ADDR + My M14_A11_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M14_A12_BASE_ADDR + My M14_A12_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M14_A13_BASE_ADDR + My M14_A13_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M14_A14_BASE_ADDR + My M14_A14_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M14_A15_BASE_ADDR + My M14_A15_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M15_A00_BASE_ADDR + My M15_A00_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M15_A01_BASE_ADDR + My M15_A01_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M15_A02_BASE_ADDR + My M15_A02_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M15_A03_BASE_ADDR + My M15_A03_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M15_A04_BASE_ADDR + My M15_A04_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M15_A05_BASE_ADDR + My M15_A05_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M15_A06_BASE_ADDR + My M15_A06_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M15_A07_BASE_ADDR + My M15_A07_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M15_A08_BASE_ADDR + My M15_A08_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M15_A09_BASE_ADDR + My M15_A09_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M15_A10_BASE_ADDR + My M15_A10_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M15_A11_BASE_ADDR + My M15_A11_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M15_A12_BASE_ADDR + My M15_A12_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M15_A13_BASE_ADDR + My M15_A13_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M15_A14_BASE_ADDR + My M15_A14_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M15_A15_BASE_ADDR + My M15_A15_BASE_ADDR + 0xffffffffffffffff + + + + true + + + + + + M00_A00_ADDR_WIDTH + My M00_A00_ADDR_WIDTH + 29 + + + + true + + + + + + M00_A01_ADDR_WIDTH + My M00_A01_ADDR_WIDTH + 0 + + + + true + + + + + + M00_A02_ADDR_WIDTH + My M00_A02_ADDR_WIDTH + 0 + + + + true + + + + + + M00_A03_ADDR_WIDTH + My M00_A03_ADDR_WIDTH + 0 + + + + true + + + + + + M00_A04_ADDR_WIDTH + My M00_A04_ADDR_WIDTH + 0 + + + + true + + + + + + M00_A05_ADDR_WIDTH + My M00_A05_ADDR_WIDTH + 0 + + + + true + + + + + + M00_A06_ADDR_WIDTH + My M00_A06_ADDR_WIDTH + 0 + + + + true + + + + + + M00_A07_ADDR_WIDTH + My M00_A07_ADDR_WIDTH + 0 + + + + true + + + + + + M00_A08_ADDR_WIDTH + My M00_A08_ADDR_WIDTH + 0 + + + + true + + + + + + M00_A09_ADDR_WIDTH + My M00_A09_ADDR_WIDTH + 0 + + + + true + + + + + + M00_A10_ADDR_WIDTH + My M00_A10_ADDR_WIDTH + 0 + + + + true + + + + + + M00_A11_ADDR_WIDTH + My M00_A11_ADDR_WIDTH + 0 + + + + true + + + + + + M00_A12_ADDR_WIDTH + My M00_A12_ADDR_WIDTH + 0 + + + + true + + + + + + M00_A13_ADDR_WIDTH + My M00_A13_ADDR_WIDTH + 0 + + + + true + + + + + + M00_A14_ADDR_WIDTH + My M00_A14_ADDR_WIDTH + 0 + + + + true + + + + + + M00_A15_ADDR_WIDTH + My M00_A15_ADDR_WIDTH + 0 + + + + true + + + + + + M01_A00_ADDR_WIDTH + My M01_A00_ADDR_WIDTH + 0 + + + + true + + + + + + M01_A01_ADDR_WIDTH + My M01_A01_ADDR_WIDTH + 0 + + + + true + + + + + + M01_A02_ADDR_WIDTH + My M01_A02_ADDR_WIDTH + 0 + + + + true + + + + + + M01_A03_ADDR_WIDTH + My M01_A03_ADDR_WIDTH + 0 + + + + true + + + + + + M01_A04_ADDR_WIDTH + My M01_A04_ADDR_WIDTH + 0 + + + + true + + + + + + M01_A05_ADDR_WIDTH + My M01_A05_ADDR_WIDTH + 0 + + + + true + + + + + + M01_A06_ADDR_WIDTH + My M01_A06_ADDR_WIDTH + 0 + + + + true + + + + + + M01_A07_ADDR_WIDTH + My M01_A07_ADDR_WIDTH + 0 + + + + true + + + + + + M01_A08_ADDR_WIDTH + My M01_A08_ADDR_WIDTH + 0 + + + + true + + + + + + M01_A09_ADDR_WIDTH + My M01_A09_ADDR_WIDTH + 0 + + + + true + + + + + + M01_A10_ADDR_WIDTH + My M01_A10_ADDR_WIDTH + 0 + + + + true + + + + + + M01_A11_ADDR_WIDTH + My M01_A11_ADDR_WIDTH + 0 + + + + true + + + + + + M01_A12_ADDR_WIDTH + My M01_A12_ADDR_WIDTH + 0 + + + + true + + + + + + M01_A13_ADDR_WIDTH + My M01_A13_ADDR_WIDTH + 0 + + + + true + + + + + + M01_A14_ADDR_WIDTH + My M01_A14_ADDR_WIDTH + 0 + + + + true + + + + + + M01_A15_ADDR_WIDTH + My M01_A15_ADDR_WIDTH + 0 + + + + true + + + + + + M02_A00_ADDR_WIDTH + My M02_A00_ADDR_WIDTH + 0 + + + + true + + + + + + M02_A01_ADDR_WIDTH + My M02_A01_ADDR_WIDTH + 0 + + + + true + + + + + + M02_A02_ADDR_WIDTH + My M02_A02_ADDR_WIDTH + 0 + + + + true + + + + + + M02_A03_ADDR_WIDTH + My M02_A03_ADDR_WIDTH + 0 + + + + true + + + + + + M02_A04_ADDR_WIDTH + My M02_A04_ADDR_WIDTH + 0 + + + + true + + + + + + M02_A05_ADDR_WIDTH + My M02_A05_ADDR_WIDTH + 0 + + + + true + + + + + + M02_A06_ADDR_WIDTH + My M02_A06_ADDR_WIDTH + 0 + + + + true + + + + + + M02_A07_ADDR_WIDTH + My M02_A07_ADDR_WIDTH + 0 + + + + true + + + + + + M02_A08_ADDR_WIDTH + My M02_A08_ADDR_WIDTH + 0 + + + + true + + + + + + M02_A09_ADDR_WIDTH + My M02_A09_ADDR_WIDTH + 0 + + + + true + + + + + + M02_A10_ADDR_WIDTH + My M02_A10_ADDR_WIDTH + 0 + + + + true + + + + + + M02_A11_ADDR_WIDTH + My M02_A11_ADDR_WIDTH + 0 + + + + true + + + + + + M02_A12_ADDR_WIDTH + My M02_A12_ADDR_WIDTH + 0 + + + + true + + + + + + M02_A13_ADDR_WIDTH + My M02_A13_ADDR_WIDTH + 0 + + + + true + + + + + + M02_A14_ADDR_WIDTH + My M02_A14_ADDR_WIDTH + 0 + + + + true + + + + + + M02_A15_ADDR_WIDTH + My M02_A15_ADDR_WIDTH + 0 + + + + true + + + + + + M03_A00_ADDR_WIDTH + My M03_A00_ADDR_WIDTH + 0 + + + + true + + + + + + M03_A01_ADDR_WIDTH + My M03_A01_ADDR_WIDTH + 0 + + + + true + + + + + + M03_A02_ADDR_WIDTH + My M03_A02_ADDR_WIDTH + 0 + + + + true + + + + + + M03_A03_ADDR_WIDTH + My M03_A03_ADDR_WIDTH + 0 + + + + true + + + + + + M03_A04_ADDR_WIDTH + My M03_A04_ADDR_WIDTH + 0 + + + + true + + + + + + M03_A05_ADDR_WIDTH + My M03_A05_ADDR_WIDTH + 0 + + + + true + + + + + + M03_A06_ADDR_WIDTH + My M03_A06_ADDR_WIDTH + 0 + + + + true + + + + + + M03_A07_ADDR_WIDTH + My M03_A07_ADDR_WIDTH + 0 + + + + true + + + + + + M03_A08_ADDR_WIDTH + My M03_A08_ADDR_WIDTH + 0 + + + + true + + + + + + M03_A09_ADDR_WIDTH + My M03_A09_ADDR_WIDTH + 0 + + + + true + + + + + + M03_A10_ADDR_WIDTH + My M03_A10_ADDR_WIDTH + 0 + + + + true + + + + + + M03_A11_ADDR_WIDTH + My M03_A11_ADDR_WIDTH + 0 + + + + true + + + + + + M03_A12_ADDR_WIDTH + My M03_A12_ADDR_WIDTH + 0 + + + + true + + + + + + M03_A13_ADDR_WIDTH + My M03_A13_ADDR_WIDTH + 0 + + + + true + + + + + + M03_A14_ADDR_WIDTH + My M03_A14_ADDR_WIDTH + 0 + + + + true + + + + + + M03_A15_ADDR_WIDTH + My M03_A15_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A00_ADDR_WIDTH + My M04_A00_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A01_ADDR_WIDTH + My M04_A01_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A02_ADDR_WIDTH + My M04_A02_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A03_ADDR_WIDTH + My M04_A03_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A04_ADDR_WIDTH + My M04_A04_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A05_ADDR_WIDTH + My M04_A05_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A06_ADDR_WIDTH + My M04_A06_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A07_ADDR_WIDTH + My M04_A07_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A08_ADDR_WIDTH + My M04_A08_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A09_ADDR_WIDTH + My M04_A09_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A10_ADDR_WIDTH + My M04_A10_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A11_ADDR_WIDTH + My M04_A11_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A12_ADDR_WIDTH + My M04_A12_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A13_ADDR_WIDTH + My M04_A13_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A14_ADDR_WIDTH + My M04_A14_ADDR_WIDTH + 0 + + + + true + + + + + + M04_A15_ADDR_WIDTH + My M04_A15_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A00_ADDR_WIDTH + My M05_A00_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A01_ADDR_WIDTH + My M05_A01_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A02_ADDR_WIDTH + My M05_A02_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A03_ADDR_WIDTH + My M05_A03_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A04_ADDR_WIDTH + My M05_A04_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A05_ADDR_WIDTH + My M05_A05_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A06_ADDR_WIDTH + My M05_A06_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A07_ADDR_WIDTH + My M05_A07_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A08_ADDR_WIDTH + My M05_A08_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A09_ADDR_WIDTH + My M05_A09_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A10_ADDR_WIDTH + My M05_A10_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A11_ADDR_WIDTH + My M05_A11_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A12_ADDR_WIDTH + My M05_A12_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A13_ADDR_WIDTH + My M05_A13_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A14_ADDR_WIDTH + My M05_A14_ADDR_WIDTH + 0 + + + + true + + + + + + M05_A15_ADDR_WIDTH + My M05_A15_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A00_ADDR_WIDTH + My M06_A00_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A01_ADDR_WIDTH + My M06_A01_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A02_ADDR_WIDTH + My M06_A02_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A03_ADDR_WIDTH + My M06_A03_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A04_ADDR_WIDTH + My M06_A04_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A05_ADDR_WIDTH + My M06_A05_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A06_ADDR_WIDTH + My M06_A06_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A07_ADDR_WIDTH + My M06_A07_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A08_ADDR_WIDTH + My M06_A08_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A09_ADDR_WIDTH + My M06_A09_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A10_ADDR_WIDTH + My M06_A10_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A11_ADDR_WIDTH + My M06_A11_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A12_ADDR_WIDTH + My M06_A12_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A13_ADDR_WIDTH + My M06_A13_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A14_ADDR_WIDTH + My M06_A14_ADDR_WIDTH + 0 + + + + true + + + + + + M06_A15_ADDR_WIDTH + My M06_A15_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A00_ADDR_WIDTH + My M07_A00_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A01_ADDR_WIDTH + My M07_A01_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A02_ADDR_WIDTH + My M07_A02_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A03_ADDR_WIDTH + My M07_A03_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A04_ADDR_WIDTH + My M07_A04_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A05_ADDR_WIDTH + My M07_A05_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A06_ADDR_WIDTH + My M07_A06_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A07_ADDR_WIDTH + My M07_A07_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A08_ADDR_WIDTH + My M07_A08_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A09_ADDR_WIDTH + My M07_A09_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A10_ADDR_WIDTH + My M07_A10_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A11_ADDR_WIDTH + My M07_A11_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A12_ADDR_WIDTH + My M07_A12_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A13_ADDR_WIDTH + My M07_A13_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A14_ADDR_WIDTH + My M07_A14_ADDR_WIDTH + 0 + + + + true + + + + + + M07_A15_ADDR_WIDTH + My M07_A15_ADDR_WIDTH + 0 + + + + true + + + + + + M08_A00_ADDR_WIDTH + My M08_A00_ADDR_WIDTH + 0 + + + + true + + + + + + M08_A01_ADDR_WIDTH + My M08_A01_ADDR_WIDTH + 0 + + + + true + + + + + + M08_A02_ADDR_WIDTH + My M08_A02_ADDR_WIDTH + 0 + + + + true + + + + + + M08_A03_ADDR_WIDTH + My M08_A03_ADDR_WIDTH + 0 + + + + true + + + + + + M08_A04_ADDR_WIDTH + My M08_A04_ADDR_WIDTH + 0 + + + + true + + + + + + M08_A05_ADDR_WIDTH + My M08_A05_ADDR_WIDTH + 0 + + + + true + + + + + + M08_A06_ADDR_WIDTH + My M08_A06_ADDR_WIDTH + 0 + + + + true + + + + + + M08_A07_ADDR_WIDTH + My M08_A07_ADDR_WIDTH + 0 + + + + true + + + + + + M08_A08_ADDR_WIDTH + My M08_A08_ADDR_WIDTH + 0 + + + + true + + + + + + M08_A09_ADDR_WIDTH + My M08_A09_ADDR_WIDTH + 0 + + + + true + + + + + + M08_A10_ADDR_WIDTH + My M08_A10_ADDR_WIDTH + 0 + + + + true + + + + + + M08_A11_ADDR_WIDTH + My M08_A11_ADDR_WIDTH + 0 + + + + true + + + + + + M08_A12_ADDR_WIDTH + My M08_A12_ADDR_WIDTH + 0 + + + + true + + + + + + M08_A13_ADDR_WIDTH + My M08_A13_ADDR_WIDTH + 0 + + + + true + + + + + + M08_A14_ADDR_WIDTH + My M08_A14_ADDR_WIDTH + 0 + + + + true + + + + + + M08_A15_ADDR_WIDTH + My M08_A15_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A00_ADDR_WIDTH + My M09_A00_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A01_ADDR_WIDTH + My M09_A01_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A02_ADDR_WIDTH + My M09_A02_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A03_ADDR_WIDTH + My M09_A03_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A04_ADDR_WIDTH + My M09_A04_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A05_ADDR_WIDTH + My M09_A05_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A06_ADDR_WIDTH + My M09_A06_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A07_ADDR_WIDTH + My M09_A07_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A08_ADDR_WIDTH + My M09_A08_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A09_ADDR_WIDTH + My M09_A09_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A10_ADDR_WIDTH + My M09_A10_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A11_ADDR_WIDTH + My M09_A11_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A12_ADDR_WIDTH + My M09_A12_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A13_ADDR_WIDTH + My M09_A13_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A14_ADDR_WIDTH + My M09_A14_ADDR_WIDTH + 0 + + + + true + + + + + + M09_A15_ADDR_WIDTH + My M09_A15_ADDR_WIDTH + 0 + + + + true + + + + + + M10_A00_ADDR_WIDTH + My M10_A00_ADDR_WIDTH + 0 + + + + true + + + + + + M10_A01_ADDR_WIDTH + My M10_A01_ADDR_WIDTH + 0 + + + + true + + + + + + M10_A02_ADDR_WIDTH + My M10_A02_ADDR_WIDTH + 0 + + + + true + + + + + + M10_A03_ADDR_WIDTH + My M10_A03_ADDR_WIDTH + 0 + + + + true + + + + + + M10_A04_ADDR_WIDTH + My M10_A04_ADDR_WIDTH + 0 + + + + true + + + + + + M10_A05_ADDR_WIDTH + My M10_A05_ADDR_WIDTH + 0 + + + + true + + + + + + M10_A06_ADDR_WIDTH + My M10_A06_ADDR_WIDTH + 0 + + + + true + + + + + + M10_A07_ADDR_WIDTH + My M10_A07_ADDR_WIDTH + 0 + + + + true + + + + + + M10_A08_ADDR_WIDTH + My M10_A08_ADDR_WIDTH + 0 + + + + true + + + + + + M10_A09_ADDR_WIDTH + My M10_A09_ADDR_WIDTH + 0 + + + + true + + + + + + M10_A10_ADDR_WIDTH + My M10_A10_ADDR_WIDTH + 0 + + + + true + + + + + + M10_A11_ADDR_WIDTH + My M10_A11_ADDR_WIDTH + 0 + + + + true + + + + + + M10_A12_ADDR_WIDTH + My M10_A12_ADDR_WIDTH + 0 + + + + true + + + + + + M10_A13_ADDR_WIDTH + My M10_A13_ADDR_WIDTH + 0 + + + + true + + + + + + M10_A14_ADDR_WIDTH + My M10_A14_ADDR_WIDTH + 0 + + + + true + + + + + + M10_A15_ADDR_WIDTH + My M10_A15_ADDR_WIDTH + 0 + + + + true + + + + + + M11_A00_ADDR_WIDTH + My M11_A00_ADDR_WIDTH + 0 + + + + true + + + + + + M11_A01_ADDR_WIDTH + My M11_A01_ADDR_WIDTH + 0 + + + + true + + + + + + M11_A02_ADDR_WIDTH + My M11_A02_ADDR_WIDTH + 0 + + + + true + + + + + + M11_A03_ADDR_WIDTH + My M11_A03_ADDR_WIDTH + 0 + + + + true + + + + + + M11_A04_ADDR_WIDTH + My M11_A04_ADDR_WIDTH + 0 + + + + true + + + + + + M11_A05_ADDR_WIDTH + My M11_A05_ADDR_WIDTH + 0 + + + + true + + + + + + M11_A06_ADDR_WIDTH + My M11_A06_ADDR_WIDTH + 0 + + + + true + + + + + + M11_A07_ADDR_WIDTH + My M11_A07_ADDR_WIDTH + 0 + + + + true + + + + + + M11_A08_ADDR_WIDTH + My M11_A08_ADDR_WIDTH + 0 + + + + true + + + + + + M11_A09_ADDR_WIDTH + My M11_A09_ADDR_WIDTH + 0 + + + + true + + + + + + M11_A10_ADDR_WIDTH + My M11_A10_ADDR_WIDTH + 0 + + + + true + + + + + + M11_A11_ADDR_WIDTH + My M11_A11_ADDR_WIDTH + 0 + + + + true + + + + + + M11_A12_ADDR_WIDTH + My M11_A12_ADDR_WIDTH + 0 + + + + true + + + + + + M11_A13_ADDR_WIDTH + My M11_A13_ADDR_WIDTH + 0 + + + + true + + + + + + M11_A14_ADDR_WIDTH + My M11_A14_ADDR_WIDTH + 0 + + + + true + + + + + + M11_A15_ADDR_WIDTH + My M11_A15_ADDR_WIDTH + 0 + + + + true + + + + + + M12_A00_ADDR_WIDTH + My M12_A00_ADDR_WIDTH + 0 + + + + true + + + + + + M12_A01_ADDR_WIDTH + My M12_A01_ADDR_WIDTH + 0 + + + + true + + + + + + M12_A02_ADDR_WIDTH + My M12_A02_ADDR_WIDTH + 0 + + + + true + + + + + + M12_A03_ADDR_WIDTH + My M12_A03_ADDR_WIDTH + 0 + + + + true + + + + + + M12_A04_ADDR_WIDTH + My M12_A04_ADDR_WIDTH + 0 + + + + true + + + + + + M12_A05_ADDR_WIDTH + My M12_A05_ADDR_WIDTH + 0 + + + + true + + + + + + M12_A06_ADDR_WIDTH + My M12_A06_ADDR_WIDTH + 0 + + + + true + + + + + + M12_A07_ADDR_WIDTH + My M12_A07_ADDR_WIDTH + 0 + + + + true + + + + + + M12_A08_ADDR_WIDTH + My M12_A08_ADDR_WIDTH + 0 + + + + true + + + + + + M12_A09_ADDR_WIDTH + My M12_A09_ADDR_WIDTH + 0 + + + + true + + + + + + M12_A10_ADDR_WIDTH + My M12_A10_ADDR_WIDTH + 0 + + + + true + + + + + + M12_A11_ADDR_WIDTH + My M12_A11_ADDR_WIDTH + 0 + + + + true + + + + + + M12_A12_ADDR_WIDTH + My M12_A12_ADDR_WIDTH + 0 + + + + true + + + + + + M12_A13_ADDR_WIDTH + My M12_A13_ADDR_WIDTH + 0 + + + + true + + + + + + M12_A14_ADDR_WIDTH + My M12_A14_ADDR_WIDTH + 0 + + + + true + + + + + + M12_A15_ADDR_WIDTH + My M12_A15_ADDR_WIDTH + 0 + + + + true + + + + + + M13_A00_ADDR_WIDTH + My M13_A00_ADDR_WIDTH + 0 + + + + true + + + + + + M13_A01_ADDR_WIDTH + My M13_A01_ADDR_WIDTH + 0 + + + + true + + + + + + M13_A02_ADDR_WIDTH + My M13_A02_ADDR_WIDTH + 0 + + + + true + + + + + + M13_A03_ADDR_WIDTH + My M13_A03_ADDR_WIDTH + 0 + + + + true + + + + + + M13_A04_ADDR_WIDTH + My M13_A04_ADDR_WIDTH + 0 + + + + true + + + + + + M13_A05_ADDR_WIDTH + My M13_A05_ADDR_WIDTH + 0 + + + + true + + + + + + M13_A06_ADDR_WIDTH + My M13_A06_ADDR_WIDTH + 0 + + + + true + + + + + + M13_A07_ADDR_WIDTH + My M13_A07_ADDR_WIDTH + 0 + + + + true + + + + + + M13_A08_ADDR_WIDTH + My M13_A08_ADDR_WIDTH + 0 + + + + true + + + + + + M13_A09_ADDR_WIDTH + My M13_A09_ADDR_WIDTH + 0 + + + + true + + + + + + M13_A10_ADDR_WIDTH + My M13_A10_ADDR_WIDTH + 0 + + + + true + + + + + + M13_A11_ADDR_WIDTH + My M13_A11_ADDR_WIDTH + 0 + + + + true + + + + + + M13_A12_ADDR_WIDTH + My M13_A12_ADDR_WIDTH + 0 + + + + true + + + + + + M13_A13_ADDR_WIDTH + My M13_A13_ADDR_WIDTH + 0 + + + + true + + + + + + M13_A14_ADDR_WIDTH + My M13_A14_ADDR_WIDTH + 0 + + + + true + + + + + + M13_A15_ADDR_WIDTH + My M13_A15_ADDR_WIDTH + 0 + + + + true + + + + + + M14_A00_ADDR_WIDTH + My M14_A00_ADDR_WIDTH + 0 + + + + true + + + + + + M14_A01_ADDR_WIDTH + My M14_A01_ADDR_WIDTH + 0 + + + + true + + + + + + M14_A02_ADDR_WIDTH + My M14_A02_ADDR_WIDTH + 0 + + + + true + + + + + + M14_A03_ADDR_WIDTH + My M14_A03_ADDR_WIDTH + 0 + + + + true + + + + + + M14_A04_ADDR_WIDTH + My M14_A04_ADDR_WIDTH + 0 + + + + true + + + + + + M14_A05_ADDR_WIDTH + My M14_A05_ADDR_WIDTH + 0 + + + + true + + + + + + M14_A06_ADDR_WIDTH + My M14_A06_ADDR_WIDTH + 0 + + + + true + + + + + + M14_A07_ADDR_WIDTH + My M14_A07_ADDR_WIDTH + 0 + + + + true + + + + + + M14_A08_ADDR_WIDTH + My M14_A08_ADDR_WIDTH + 0 + + + + true + + + + + + M14_A09_ADDR_WIDTH + My M14_A09_ADDR_WIDTH + 0 + + + + true + + + + + + M14_A10_ADDR_WIDTH + My M14_A10_ADDR_WIDTH + 0 + + + + true + + + + + + M14_A11_ADDR_WIDTH + My M14_A11_ADDR_WIDTH + 0 + + + + true + + + + + + M14_A12_ADDR_WIDTH + My M14_A12_ADDR_WIDTH + 0 + + + + true + + + + + + M14_A13_ADDR_WIDTH + My M14_A13_ADDR_WIDTH + 0 + + + + true + + + + + + M14_A14_ADDR_WIDTH + My M14_A14_ADDR_WIDTH + 0 + + + + true + + + + + + M14_A15_ADDR_WIDTH + My M14_A15_ADDR_WIDTH + 0 + + + + true + + + + + + M15_A00_ADDR_WIDTH + My M15_A00_ADDR_WIDTH + 0 + + + + true + + + + + + M15_A01_ADDR_WIDTH + My M15_A01_ADDR_WIDTH + 0 + + + + true + + + + + + M15_A02_ADDR_WIDTH + My M15_A02_ADDR_WIDTH + 0 + + + + true + + + + + + M15_A03_ADDR_WIDTH + My M15_A03_ADDR_WIDTH + 0 + + + + true + + + + + + M15_A04_ADDR_WIDTH + My M15_A04_ADDR_WIDTH + 0 + + + + true + + + + + + M15_A05_ADDR_WIDTH + My M15_A05_ADDR_WIDTH + 0 + + + + true + + + + + + M15_A06_ADDR_WIDTH + My M15_A06_ADDR_WIDTH + 0 + + + + true + + + + + + M15_A07_ADDR_WIDTH + My M15_A07_ADDR_WIDTH + 0 + + + + true + + + + + + M15_A08_ADDR_WIDTH + My M15_A08_ADDR_WIDTH + 0 + + + + true + + + + + + M15_A09_ADDR_WIDTH + My M15_A09_ADDR_WIDTH + 0 + + + + true + + + + + + M15_A10_ADDR_WIDTH + My M15_A10_ADDR_WIDTH + 0 + + + + true + + + + + + M15_A11_ADDR_WIDTH + My M15_A11_ADDR_WIDTH + 0 + + + + true + + + + + + M15_A12_ADDR_WIDTH + My M15_A12_ADDR_WIDTH + 0 + + + + true + + + + + + M15_A13_ADDR_WIDTH + My M15_A13_ADDR_WIDTH + 0 + + + + true + + + + + + M15_A14_ADDR_WIDTH + My M15_A14_ADDR_WIDTH + 0 + + + + true + + + + + + M15_A15_ADDR_WIDTH + My M15_A15_ADDR_WIDTH + 0 + + + + true + + + + + + Component_Name + Arty_Z7_20_xbar_1 + + + + + AXI Crossbar + 12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2016.4 + + + + + + + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_1/Arty_Z7_20_xbar_1_ooc.xdc b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_1/Arty_Z7_20_xbar_1_ooc.xdc new file mode 100644 index 0000000..6259de8 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_1/Arty_Z7_20_xbar_1_ooc.xdc @@ -0,0 +1,57 @@ +# (c) Copyright 2012-2017 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +# DO NOT MODIFY THIS FILE. +# ######################################################### +# +# This XDC is used only in OOC mode for synthesis, implementation +# +# ######################################################### + + +create_clock -period 8.462 -name aclk [get_ports aclk] + + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_1/Arty_Z7_20_xbar_1_sim_netlist.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_1/Arty_Z7_20_xbar_1_sim_netlist.v new file mode 100644 index 0000000..6e37c90 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_1/Arty_Z7_20_xbar_1_sim_netlist.v @@ -0,0 +1,9369 @@ +// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +// Date : Sat Mar 04 18:57:49 2017 +// Host : WK73 running 64-bit Service Pack 1 (build 7601) +// Command : write_verilog -force -mode funcsim -rename_top Arty_Z7_20_xbar_1 -prefix +// Arty_Z7_20_xbar_1_ Arty_Z7_20_xbar_1_sim_netlist.v +// Design : Arty_Z7_20_xbar_1 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z020clg400-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "Arty_Z7_20_xbar_1,axi_crossbar_v2_1_12_axi_crossbar,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4" *) +(* NotValidForBitStream *) +module Arty_Z7_20_xbar_1 + (aclk, + aresetn, + s_axi_awid, + s_axi_awaddr, + s_axi_awlen, + s_axi_awsize, + s_axi_awburst, + s_axi_awlock, + s_axi_awcache, + s_axi_awprot, + s_axi_awqos, + s_axi_awvalid, + s_axi_awready, + s_axi_wdata, + s_axi_wstrb, + s_axi_wlast, + s_axi_wvalid, + s_axi_wready, + s_axi_bid, + s_axi_bresp, + s_axi_bvalid, + s_axi_bready, + s_axi_arid, + s_axi_araddr, + s_axi_arlen, + s_axi_arsize, + s_axi_arburst, + s_axi_arlock, + s_axi_arcache, + s_axi_arprot, + s_axi_arqos, + s_axi_arvalid, + s_axi_arready, + s_axi_rid, + s_axi_rdata, + s_axi_rresp, + s_axi_rlast, + s_axi_rvalid, + s_axi_rready, + m_axi_awid, + m_axi_awaddr, + m_axi_awlen, + m_axi_awsize, + m_axi_awburst, + m_axi_awlock, + m_axi_awcache, + m_axi_awprot, + m_axi_awregion, + m_axi_awqos, + m_axi_awvalid, + m_axi_awready, + m_axi_wdata, + m_axi_wstrb, + m_axi_wlast, + m_axi_wvalid, + m_axi_wready, + m_axi_bid, + m_axi_bresp, + m_axi_bvalid, + m_axi_bready, + m_axi_arid, + m_axi_araddr, + m_axi_arlen, + m_axi_arsize, + m_axi_arburst, + m_axi_arlock, + m_axi_arcache, + m_axi_arprot, + m_axi_arregion, + m_axi_arqos, + m_axi_arvalid, + m_axi_arready, + m_axi_rid, + m_axi_rdata, + m_axi_rresp, + m_axi_rlast, + m_axi_rvalid, + m_axi_rready); + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) input aclk; + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) input aresetn; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWID [0:0] [1:1]" *) input [1:0]s_axi_awid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI AWADDR [31:0] [63:32]" *) input [63:0]s_axi_awaddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLEN [7:0] [15:8]" *) input [15:0]s_axi_awlen; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE [2:0] [5:3]" *) input [5:0]s_axi_awsize; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI AWBURST [1:0] [3:2]" *) input [3:0]s_axi_awburst; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK [0:0] [1:1]" *) input [1:0]s_axi_awlock; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE [3:0] [7:4]" *) input [7:0]s_axi_awcache; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWPROT [2:0] [5:3]" *) input [5:0]s_axi_awprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWQOS [3:0] [7:4]" *) input [7:0]s_axi_awqos; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWVALID [0:0] [1:1]" *) input [1:0]s_axi_awvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWREADY [0:0] [1:1]" *) output [1:0]s_axi_awready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI WDATA [63:0] [127:64]" *) input [127:0]s_axi_wdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI WSTRB [7:0] [15:8]" *) input [15:0]s_axi_wstrb; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WLAST [0:0] [1:1]" *) input [1:0]s_axi_wlast; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WVALID [0:0] [1:1]" *) input [1:0]s_axi_wvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WREADY [0:0] [1:1]" *) output [1:0]s_axi_wready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BID [0:0] [1:1]" *) output [1:0]s_axi_bid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI BRESP [1:0] [3:2]" *) output [3:0]s_axi_bresp; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BVALID [0:0] [1:1]" *) output [1:0]s_axi_bvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BREADY [0:0] [1:1]" *) input [1:0]s_axi_bready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARID [0:0] [1:1]" *) input [1:0]s_axi_arid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI ARADDR [31:0] [63:32]" *) input [63:0]s_axi_araddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLEN [7:0] [15:8]" *) input [15:0]s_axi_arlen; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE [2:0] [5:3]" *) input [5:0]s_axi_arsize; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI ARBURST [1:0] [3:2]" *) input [3:0]s_axi_arburst; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK [0:0] [1:1]" *) input [1:0]s_axi_arlock; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE [3:0] [7:4]" *) input [7:0]s_axi_arcache; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARPROT [2:0] [5:3]" *) input [5:0]s_axi_arprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARQOS [3:0] [7:4]" *) input [7:0]s_axi_arqos; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARVALID [0:0] [1:1]" *) input [1:0]s_axi_arvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARREADY [0:0] [1:1]" *) output [1:0]s_axi_arready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RID [0:0] [1:1]" *) output [1:0]s_axi_rid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI RDATA [63:0] [127:64]" *) output [127:0]s_axi_rdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI RRESP [1:0] [3:2]" *) output [3:0]s_axi_rresp; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RLAST [0:0] [1:1]" *) output [1:0]s_axi_rlast; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RVALID [0:0] [1:1]" *) output [1:0]s_axi_rvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RREADY [0:0] [1:1]" *) input [1:0]s_axi_rready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWID" *) output [0:0]m_axi_awid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR" *) output [31:0]m_axi_awaddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN" *) output [7:0]m_axi_awlen; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE" *) output [2:0]m_axi_awsize; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST" *) output [1:0]m_axi_awburst; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK" *) output [0:0]m_axi_awlock; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE" *) output [3:0]m_axi_awcache; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT" *) output [2:0]m_axi_awprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION" *) output [3:0]m_axi_awregion; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS" *) output [3:0]m_axi_awqos; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID" *) output [0:0]m_axi_awvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY" *) input [0:0]m_axi_awready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA" *) output [63:0]m_axi_wdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB" *) output [7:0]m_axi_wstrb; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST" *) output [0:0]m_axi_wlast; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID" *) output [0:0]m_axi_wvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY" *) input [0:0]m_axi_wready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BID" *) input [0:0]m_axi_bid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP" *) input [1:0]m_axi_bresp; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID" *) input [0:0]m_axi_bvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY" *) output [0:0]m_axi_bready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARID" *) output [0:0]m_axi_arid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR" *) output [31:0]m_axi_araddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN" *) output [7:0]m_axi_arlen; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE" *) output [2:0]m_axi_arsize; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST" *) output [1:0]m_axi_arburst; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK" *) output [0:0]m_axi_arlock; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE" *) output [3:0]m_axi_arcache; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT" *) output [2:0]m_axi_arprot; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION" *) output [3:0]m_axi_arregion; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS" *) output [3:0]m_axi_arqos; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID" *) output [0:0]m_axi_arvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY" *) input [0:0]m_axi_arready; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RID" *) input [0:0]m_axi_rid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA" *) input [63:0]m_axi_rdata; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP" *) input [1:0]m_axi_rresp; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST" *) input [0:0]m_axi_rlast; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID" *) input [0:0]m_axi_rvalid; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY" *) output [0:0]m_axi_rready; + + wire aclk; + wire aresetn; + wire [31:0]m_axi_araddr; + wire [1:0]m_axi_arburst; + wire [3:0]m_axi_arcache; + wire [0:0]m_axi_arid; + wire [7:0]m_axi_arlen; + wire [0:0]m_axi_arlock; + wire [2:0]m_axi_arprot; + wire [3:0]m_axi_arqos; + wire [0:0]m_axi_arready; + wire [3:0]m_axi_arregion; + wire [2:0]m_axi_arsize; + wire [0:0]m_axi_arvalid; + wire [31:0]m_axi_awaddr; + wire [1:0]m_axi_awburst; + wire [3:0]m_axi_awcache; + wire [0:0]m_axi_awid; + wire [7:0]m_axi_awlen; + wire [0:0]m_axi_awlock; + wire [2:0]m_axi_awprot; + wire [3:0]m_axi_awqos; + wire [0:0]m_axi_awready; + wire [3:0]m_axi_awregion; + wire [2:0]m_axi_awsize; + wire [0:0]m_axi_awvalid; + wire [0:0]m_axi_bid; + wire [0:0]m_axi_bready; + wire [1:0]m_axi_bresp; + wire [0:0]m_axi_bvalid; + wire [63:0]m_axi_rdata; + wire [0:0]m_axi_rid; + wire [0:0]m_axi_rlast; + wire [0:0]m_axi_rready; + wire [1:0]m_axi_rresp; + wire [0:0]m_axi_rvalid; + wire [63:0]m_axi_wdata; + wire [0:0]m_axi_wlast; + wire [0:0]m_axi_wready; + wire [7:0]m_axi_wstrb; + wire [0:0]m_axi_wvalid; + wire [63:0]s_axi_araddr; + wire [3:0]s_axi_arburst; + wire [7:0]s_axi_arcache; + wire [1:0]s_axi_arid; + wire [15:0]s_axi_arlen; + wire [1:0]s_axi_arlock; + wire [5:0]s_axi_arprot; + wire [7:0]s_axi_arqos; + wire [1:0]s_axi_arready; + wire [5:0]s_axi_arsize; + wire [1:0]s_axi_arvalid; + wire [63:0]s_axi_awaddr; + wire [3:0]s_axi_awburst; + wire [7:0]s_axi_awcache; + wire [1:0]s_axi_awid; + wire [15:0]s_axi_awlen; + wire [1:0]s_axi_awlock; + wire [5:0]s_axi_awprot; + wire [7:0]s_axi_awqos; + wire [1:0]s_axi_awready; + wire [5:0]s_axi_awsize; + wire [1:0]s_axi_awvalid; + wire [1:0]s_axi_bid; + wire [1:0]s_axi_bready; + wire [3:0]s_axi_bresp; + wire [1:0]s_axi_bvalid; + wire [127:0]s_axi_rdata; + wire [1:0]s_axi_rid; + wire [1:0]s_axi_rlast; + wire [1:0]s_axi_rready; + wire [3:0]s_axi_rresp; + wire [1:0]s_axi_rvalid; + wire [127:0]s_axi_wdata; + wire [1:0]s_axi_wlast; + wire [1:0]s_axi_wready; + wire [15:0]s_axi_wstrb; + wire [1:0]s_axi_wvalid; + wire [0:0]NLW_inst_m_axi_aruser_UNCONNECTED; + wire [0:0]NLW_inst_m_axi_awuser_UNCONNECTED; + wire [0:0]NLW_inst_m_axi_wid_UNCONNECTED; + wire [0:0]NLW_inst_m_axi_wuser_UNCONNECTED; + wire [1:0]NLW_inst_s_axi_buser_UNCONNECTED; + wire [1:0]NLW_inst_s_axi_ruser_UNCONNECTED; + + (* C_AXI_ADDR_WIDTH = "32" *) + (* C_AXI_ARUSER_WIDTH = "1" *) + (* C_AXI_AWUSER_WIDTH = "1" *) + (* C_AXI_BUSER_WIDTH = "1" *) + (* C_AXI_DATA_WIDTH = "64" *) + (* C_AXI_ID_WIDTH = "1" *) + (* C_AXI_PROTOCOL = "0" *) + (* C_AXI_RUSER_WIDTH = "1" *) + (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *) + (* C_AXI_WUSER_WIDTH = "1" *) + (* C_CONNECTIVITY_MODE = "1" *) + (* C_DEBUG = "1" *) + (* C_FAMILY = "zynq" *) + (* C_M_AXI_ADDR_WIDTH = "29" *) + (* C_M_AXI_BASE_ADDR = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) + (* C_M_AXI_READ_CONNECTIVITY = "1" *) + (* C_M_AXI_READ_ISSUING = "8" *) + (* C_M_AXI_SECURE = "0" *) + (* C_M_AXI_WRITE_CONNECTIVITY = "2" *) + (* C_M_AXI_WRITE_ISSUING = "8" *) + (* C_NUM_ADDR_RANGES = "1" *) + (* C_NUM_MASTER_SLOTS = "1" *) + (* C_NUM_SLAVE_SLOTS = "2" *) + (* C_R_REGISTER = "0" *) + (* C_S_AXI_ARB_PRIORITY = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) + (* C_S_AXI_BASE_ID = "64'b0000000000000000000000000000000100000000000000000000000000000000" *) + (* C_S_AXI_READ_ACCEPTANCE = "64'b0000000000000000000000000000001000000000000000000000000000000010" *) + (* C_S_AXI_SINGLE_THREAD = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) + (* C_S_AXI_THREAD_ID_WIDTH = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) + (* C_S_AXI_WRITE_ACCEPTANCE = "64'b0000000000000000000000000000001000000000000000000000000000000010" *) + (* DowngradeIPIdentifiedWarnings = "yes" *) + (* P_ADDR_DECODE = "1" *) + (* P_AXI3 = "1" *) + (* P_AXI4 = "0" *) + (* P_AXILITE = "2" *) + (* P_AXILITE_SIZE = "3'b010" *) + (* P_FAMILY = "zynq" *) + (* P_INCR = "2'b01" *) + (* P_LEN = "8" *) + (* P_LOCK = "1" *) + (* P_M_AXI_ERR_MODE = "32'b00000000000000000000000000000000" *) + (* P_M_AXI_SUPPORTS_READ = "1'b1" *) + (* P_M_AXI_SUPPORTS_WRITE = "1'b1" *) + (* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *) + (* P_RANGE_CHECK = "1" *) + (* P_S_AXI_BASE_ID = "128'b00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000" *) + (* P_S_AXI_HIGH_ID = "128'b00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000" *) + (* P_S_AXI_SUPPORTS_READ = "2'b01" *) + (* P_S_AXI_SUPPORTS_WRITE = "2'b10" *) + Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar inst + (.aclk(aclk), + .aresetn(aresetn), + .m_axi_araddr(m_axi_araddr), + .m_axi_arburst(m_axi_arburst), + .m_axi_arcache(m_axi_arcache), + .m_axi_arid(m_axi_arid), + .m_axi_arlen(m_axi_arlen), + .m_axi_arlock(m_axi_arlock), + .m_axi_arprot(m_axi_arprot), + .m_axi_arqos(m_axi_arqos), + .m_axi_arready(m_axi_arready), + .m_axi_arregion(m_axi_arregion), + .m_axi_arsize(m_axi_arsize), + .m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[0]), + .m_axi_arvalid(m_axi_arvalid), + .m_axi_awaddr(m_axi_awaddr), + .m_axi_awburst(m_axi_awburst), + .m_axi_awcache(m_axi_awcache), + .m_axi_awid(m_axi_awid), + .m_axi_awlen(m_axi_awlen), + .m_axi_awlock(m_axi_awlock), + .m_axi_awprot(m_axi_awprot), + .m_axi_awqos(m_axi_awqos), + .m_axi_awready(m_axi_awready), + .m_axi_awregion(m_axi_awregion), + .m_axi_awsize(m_axi_awsize), + .m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[0]), + .m_axi_awvalid(m_axi_awvalid), + .m_axi_bid(m_axi_bid), + .m_axi_bready(m_axi_bready), + .m_axi_bresp(m_axi_bresp), + .m_axi_buser(1'b0), + .m_axi_bvalid(m_axi_bvalid), + .m_axi_rdata(m_axi_rdata), + .m_axi_rid(m_axi_rid), + .m_axi_rlast(m_axi_rlast), + .m_axi_rready(m_axi_rready), + .m_axi_rresp(m_axi_rresp), + .m_axi_ruser(1'b0), + .m_axi_rvalid(m_axi_rvalid), + .m_axi_wdata(m_axi_wdata), + .m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[0]), + .m_axi_wlast(m_axi_wlast), + .m_axi_wready(m_axi_wready), + .m_axi_wstrb(m_axi_wstrb), + .m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[0]), + .m_axi_wvalid(m_axi_wvalid), + .s_axi_araddr(s_axi_araddr), + .s_axi_arburst(s_axi_arburst), + .s_axi_arcache(s_axi_arcache), + .s_axi_arid(s_axi_arid), + .s_axi_arlen(s_axi_arlen), + .s_axi_arlock(s_axi_arlock), + .s_axi_arprot(s_axi_arprot), + .s_axi_arqos(s_axi_arqos), + .s_axi_arready(s_axi_arready), + .s_axi_arsize(s_axi_arsize), + .s_axi_aruser({1'b0,1'b0}), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awburst(s_axi_awburst), + .s_axi_awcache(s_axi_awcache), + .s_axi_awid(s_axi_awid), + .s_axi_awlen(s_axi_awlen), + .s_axi_awlock(s_axi_awlock), + .s_axi_awprot(s_axi_awprot), + .s_axi_awqos(s_axi_awqos), + .s_axi_awready(s_axi_awready), + .s_axi_awsize(s_axi_awsize), + .s_axi_awuser({1'b0,1'b0}), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_bid(s_axi_bid), + .s_axi_bready(s_axi_bready), + .s_axi_bresp(s_axi_bresp), + .s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[1:0]), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_rdata(s_axi_rdata), + .s_axi_rid(s_axi_rid), + .s_axi_rlast(s_axi_rlast), + .s_axi_rready(s_axi_rready), + .s_axi_rresp(s_axi_rresp), + .s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[1:0]), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_wdata(s_axi_wdata), + .s_axi_wid({1'b0,1'b0}), + .s_axi_wlast(s_axi_wlast), + .s_axi_wready(s_axi_wready), + .s_axi_wstrb(s_axi_wstrb), + .s_axi_wuser({1'b0,1'b0}), + .s_axi_wvalid(s_axi_wvalid)); +endmodule + +module Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_addr_arbiter + (aa_mi_arvalid, + \s_axi_arready[0] , + Q, + \gen_single_thread.active_target_hot_reg[0] , + \gen_single_thread.active_target_enc_reg[0] , + \gen_master_slots[0].r_issuing_cnt_reg[0] , + \gen_master_slots[1].r_issuing_cnt_reg[8] , + \gen_arbiter.m_target_hot_i_reg[0]_0 , + E, + \gen_arbiter.qual_reg_reg[0]_0 , + \gen_axi.s_axi_rlast_i_reg , + \m_axi_arqos[3] , + m_axi_arvalid, + SR, + \gen_master_slots[0].r_issuing_cnt_reg[3] , + aclk, + st_aa_arvalid_qual, + valid_qual_i1__0, + mi_arready, + m_axi_arready, + aresetn_d, + D, + active_target_hot, + active_target_enc, + s_axi_arvalid, + \gen_master_slots[0].r_issuing_cnt_reg[3]_0 , + m_valid_i_reg, + p_11_in); + output aa_mi_arvalid; + output \s_axi_arready[0] ; + output [0:0]Q; + output \gen_single_thread.active_target_hot_reg[0] ; + output \gen_single_thread.active_target_enc_reg[0] ; + output \gen_master_slots[0].r_issuing_cnt_reg[0] ; + output \gen_master_slots[1].r_issuing_cnt_reg[8] ; + output [0:0]\gen_arbiter.m_target_hot_i_reg[0]_0 ; + output [0:0]E; + output \gen_arbiter.qual_reg_reg[0]_0 ; + output \gen_axi.s_axi_rlast_i_reg ; + output [56:0]\m_axi_arqos[3] ; + output [0:0]m_axi_arvalid; + input [0:0]SR; + input \gen_master_slots[0].r_issuing_cnt_reg[3] ; + input aclk; + input [0:0]st_aa_arvalid_qual; + input valid_qual_i1__0; + input [0:0]mi_arready; + input [0:0]m_axi_arready; + input aresetn_d; + input [56:0]D; + input [0:0]active_target_hot; + input active_target_enc; + input [0:0]s_axi_arvalid; + input [3:0]\gen_master_slots[0].r_issuing_cnt_reg[3]_0 ; + input m_valid_i_reg; + input p_11_in; + + wire [56:0]D; + wire [0:0]E; + wire [0:0]Q; + wire [0:0]SR; + wire [0:0]aa_mi_artarget_hot; + wire aa_mi_arvalid; + wire aclk; + wire active_target_enc; + wire [0:0]active_target_hot; + wire aresetn_d; + wire \gen_arbiter.any_grant_i_1__0_n_0 ; + wire \gen_arbiter.any_grant_i_2__0_n_0 ; + wire \gen_arbiter.any_grant_i_3_n_0 ; + wire \gen_arbiter.any_grant_reg_n_0 ; + wire \gen_arbiter.grant_hot[0]_i_1_n_0 ; + wire \gen_arbiter.grant_hot_reg_n_0_[0] ; + wire \gen_arbiter.last_rr_hot[0]_i_1_n_0 ; + wire \gen_arbiter.last_rr_hot[1]_i_2_n_0 ; + wire \gen_arbiter.last_rr_hot[1]_i_3_n_0 ; + wire \gen_arbiter.last_rr_hot_reg_n_0_[0] ; + wire \gen_arbiter.m_target_hot_i[1]_i_1__0_n_0 ; + wire [0:0]\gen_arbiter.m_target_hot_i_reg[0]_0 ; + wire \gen_arbiter.m_valid_i_i_1__0_n_0 ; + wire \gen_arbiter.qual_reg_reg[0]_0 ; + wire \gen_arbiter.s_ready_i[0]_i_1_n_0 ; + wire \gen_axi.s_axi_rlast_i_i_4_n_0 ; + wire \gen_axi.s_axi_rlast_i_reg ; + wire \gen_master_slots[0].r_issuing_cnt_reg[0] ; + wire \gen_master_slots[0].r_issuing_cnt_reg[3] ; + wire [3:0]\gen_master_slots[0].r_issuing_cnt_reg[3]_0 ; + wire \gen_master_slots[1].r_issuing_cnt_reg[8] ; + wire \gen_single_thread.active_target_enc_reg[0] ; + wire \gen_single_thread.active_target_hot_reg[0] ; + wire grant_hot; + wire [56:0]\m_axi_arqos[3] ; + wire [0:0]m_axi_arready; + wire [0:0]m_axi_arvalid; + wire m_valid_i_reg; + wire [0:0]mi_arready; + wire p_11_in; + wire p_1_in; + wire p_2_in; + wire [0:0]qual_reg; + wire \s_axi_arready[0] ; + wire [0:0]s_axi_arvalid; + wire [0:0]st_aa_arvalid_qual; + wire valid_qual_i1__0; + + LUT6 #( + .INIT(64'h00000000EAAA2AAA)) + \gen_arbiter.any_grant_i_1__0 + (.I0(\gen_arbiter.any_grant_reg_n_0 ), + .I1(st_aa_arvalid_qual), + .I2(\gen_arbiter.any_grant_i_2__0_n_0 ), + .I3(valid_qual_i1__0), + .I4(\gen_arbiter.last_rr_hot[0]_i_1_n_0 ), + .I5(\gen_arbiter.any_grant_i_3_n_0 ), + .O(\gen_arbiter.any_grant_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h000E0000)) + \gen_arbiter.any_grant_i_2__0 + (.I0(p_2_in), + .I1(\gen_arbiter.last_rr_hot_reg_n_0_[0] ), + .I2(\gen_arbiter.any_grant_reg_n_0 ), + .I3(aa_mi_arvalid), + .I4(\gen_arbiter.last_rr_hot[1]_i_3_n_0 ), + .O(\gen_arbiter.any_grant_i_2__0_n_0 )); + LUT6 #( + .INIT(64'hFFD5D5D555555555)) + \gen_arbiter.any_grant_i_3 + (.I0(aresetn_d), + .I1(Q), + .I2(mi_arready), + .I3(m_axi_arready), + .I4(aa_mi_artarget_hot), + .I5(aa_mi_arvalid), + .O(\gen_arbiter.any_grant_i_3_n_0 )); + FDRE \gen_arbiter.any_grant_reg + (.C(aclk), + .CE(1'b1), + .D(\gen_arbiter.any_grant_i_1__0_n_0 ), + .Q(\gen_arbiter.any_grant_reg_n_0 ), + .R(1'b0)); + LUT6 #( + .INIT(64'h00000000EAAA2AAA)) + \gen_arbiter.grant_hot[0]_i_1 + (.I0(\gen_arbiter.grant_hot_reg_n_0_[0] ), + .I1(st_aa_arvalid_qual), + .I2(\gen_arbiter.any_grant_i_2__0_n_0 ), + .I3(valid_qual_i1__0), + .I4(\gen_arbiter.last_rr_hot[0]_i_1_n_0 ), + .I5(\gen_arbiter.any_grant_i_3_n_0 ), + .O(\gen_arbiter.grant_hot[0]_i_1_n_0 )); + FDRE \gen_arbiter.grant_hot_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\gen_arbiter.grant_hot[0]_i_1_n_0 ), + .Q(\gen_arbiter.grant_hot_reg_n_0_[0] ), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h40404000)) + \gen_arbiter.last_rr_hot[0]_i_1 + (.I0(\s_axi_arready[0] ), + .I1(qual_reg), + .I2(s_axi_arvalid), + .I3(\gen_arbiter.last_rr_hot_reg_n_0_[0] ), + .I4(p_2_in), + .O(\gen_arbiter.last_rr_hot[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0008000000000000)) + \gen_arbiter.last_rr_hot[1]_i_1 + (.I0(valid_qual_i1__0), + .I1(\gen_arbiter.last_rr_hot[1]_i_2_n_0 ), + .I2(\gen_arbiter.any_grant_reg_n_0 ), + .I3(aa_mi_arvalid), + .I4(\gen_arbiter.last_rr_hot[1]_i_3_n_0 ), + .I5(st_aa_arvalid_qual), + .O(grant_hot)); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT2 #( + .INIT(4'hE)) + \gen_arbiter.last_rr_hot[1]_i_2 + (.I0(p_2_in), + .I1(\gen_arbiter.last_rr_hot_reg_n_0_[0] ), + .O(\gen_arbiter.last_rr_hot[1]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT3 #( + .INIT(8'h08)) + \gen_arbiter.last_rr_hot[1]_i_3 + (.I0(s_axi_arvalid), + .I1(qual_reg), + .I2(\s_axi_arready[0] ), + .O(\gen_arbiter.last_rr_hot[1]_i_3_n_0 )); + FDRE \gen_arbiter.last_rr_hot_reg[0] + (.C(aclk), + .CE(grant_hot), + .D(\gen_arbiter.last_rr_hot[0]_i_1_n_0 ), + .Q(\gen_arbiter.last_rr_hot_reg_n_0_[0] ), + .R(SR)); + FDSE \gen_arbiter.last_rr_hot_reg[1] + (.C(aclk), + .CE(grant_hot), + .D(1'b0), + .Q(p_2_in), + .S(SR)); + LUT1 #( + .INIT(2'h1)) + \gen_arbiter.m_mesg_i[32]_i_1 + (.I0(aa_mi_arvalid), + .O(p_1_in)); + FDRE \gen_arbiter.m_mesg_i_reg[10] + (.C(aclk), + .CE(p_1_in), + .D(D[9]), + .Q(\m_axi_arqos[3] [9]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[11] + (.C(aclk), + .CE(p_1_in), + .D(D[10]), + .Q(\m_axi_arqos[3] [10]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[12] + (.C(aclk), + .CE(p_1_in), + .D(D[11]), + .Q(\m_axi_arqos[3] [11]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[13] + (.C(aclk), + .CE(p_1_in), + .D(D[12]), + .Q(\m_axi_arqos[3] [12]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[14] + (.C(aclk), + .CE(p_1_in), + .D(D[13]), + .Q(\m_axi_arqos[3] [13]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[15] + (.C(aclk), + .CE(p_1_in), + .D(D[14]), + .Q(\m_axi_arqos[3] [14]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[16] + (.C(aclk), + .CE(p_1_in), + .D(D[15]), + .Q(\m_axi_arqos[3] [15]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[17] + (.C(aclk), + .CE(p_1_in), + .D(D[16]), + .Q(\m_axi_arqos[3] [16]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[18] + (.C(aclk), + .CE(p_1_in), + .D(D[17]), + .Q(\m_axi_arqos[3] [17]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[19] + (.C(aclk), + .CE(p_1_in), + .D(D[18]), + .Q(\m_axi_arqos[3] [18]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[1] + (.C(aclk), + .CE(p_1_in), + .D(D[0]), + .Q(\m_axi_arqos[3] [0]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[20] + (.C(aclk), + .CE(p_1_in), + .D(D[19]), + .Q(\m_axi_arqos[3] [19]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[21] + (.C(aclk), + .CE(p_1_in), + .D(D[20]), + .Q(\m_axi_arqos[3] [20]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[22] + (.C(aclk), + .CE(p_1_in), + .D(D[21]), + .Q(\m_axi_arqos[3] [21]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[23] + (.C(aclk), + .CE(p_1_in), + .D(D[22]), + .Q(\m_axi_arqos[3] [22]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[24] + (.C(aclk), + .CE(p_1_in), + .D(D[23]), + .Q(\m_axi_arqos[3] [23]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[25] + (.C(aclk), + .CE(p_1_in), + .D(D[24]), + .Q(\m_axi_arqos[3] [24]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[26] + (.C(aclk), + .CE(p_1_in), + .D(D[25]), + .Q(\m_axi_arqos[3] [25]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[27] + (.C(aclk), + .CE(p_1_in), + .D(D[26]), + .Q(\m_axi_arqos[3] [26]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[28] + (.C(aclk), + .CE(p_1_in), + .D(D[27]), + .Q(\m_axi_arqos[3] [27]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[29] + (.C(aclk), + .CE(p_1_in), + .D(D[28]), + .Q(\m_axi_arqos[3] [28]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[2] + (.C(aclk), + .CE(p_1_in), + .D(D[1]), + .Q(\m_axi_arqos[3] [1]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[30] + (.C(aclk), + .CE(p_1_in), + .D(D[29]), + .Q(\m_axi_arqos[3] [29]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[31] + (.C(aclk), + .CE(p_1_in), + .D(D[30]), + .Q(\m_axi_arqos[3] [30]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[32] + (.C(aclk), + .CE(p_1_in), + .D(D[31]), + .Q(\m_axi_arqos[3] [31]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[33] + (.C(aclk), + .CE(p_1_in), + .D(D[32]), + .Q(\m_axi_arqos[3] [32]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[34] + (.C(aclk), + .CE(p_1_in), + .D(D[33]), + .Q(\m_axi_arqos[3] [33]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[35] + (.C(aclk), + .CE(p_1_in), + .D(D[34]), + .Q(\m_axi_arqos[3] [34]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[36] + (.C(aclk), + .CE(p_1_in), + .D(D[35]), + .Q(\m_axi_arqos[3] [35]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[37] + (.C(aclk), + .CE(p_1_in), + .D(D[36]), + .Q(\m_axi_arqos[3] [36]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[38] + (.C(aclk), + .CE(p_1_in), + .D(D[37]), + .Q(\m_axi_arqos[3] [37]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[39] + (.C(aclk), + .CE(p_1_in), + .D(D[38]), + .Q(\m_axi_arqos[3] [38]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[3] + (.C(aclk), + .CE(p_1_in), + .D(D[2]), + .Q(\m_axi_arqos[3] [2]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[40] + (.C(aclk), + .CE(p_1_in), + .D(D[39]), + .Q(\m_axi_arqos[3] [39]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[41] + (.C(aclk), + .CE(p_1_in), + .D(D[40]), + .Q(\m_axi_arqos[3] [40]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[42] + (.C(aclk), + .CE(p_1_in), + .D(D[41]), + .Q(\m_axi_arqos[3] [41]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[43] + (.C(aclk), + .CE(p_1_in), + .D(D[42]), + .Q(\m_axi_arqos[3] [42]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[44] + (.C(aclk), + .CE(p_1_in), + .D(D[43]), + .Q(\m_axi_arqos[3] [43]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[46] + (.C(aclk), + .CE(p_1_in), + .D(D[44]), + .Q(\m_axi_arqos[3] [44]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[47] + (.C(aclk), + .CE(p_1_in), + .D(D[45]), + .Q(\m_axi_arqos[3] [45]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[48] + (.C(aclk), + .CE(p_1_in), + .D(D[46]), + .Q(\m_axi_arqos[3] [46]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[4] + (.C(aclk), + .CE(p_1_in), + .D(D[3]), + .Q(\m_axi_arqos[3] [3]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[53] + (.C(aclk), + .CE(p_1_in), + .D(D[47]), + .Q(\m_axi_arqos[3] [47]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[54] + (.C(aclk), + .CE(p_1_in), + .D(D[48]), + .Q(\m_axi_arqos[3] [48]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[55] + (.C(aclk), + .CE(p_1_in), + .D(D[49]), + .Q(\m_axi_arqos[3] [49]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[56] + (.C(aclk), + .CE(p_1_in), + .D(D[50]), + .Q(\m_axi_arqos[3] [50]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[57] + (.C(aclk), + .CE(p_1_in), + .D(D[51]), + .Q(\m_axi_arqos[3] [51]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[58] + (.C(aclk), + .CE(p_1_in), + .D(D[52]), + .Q(\m_axi_arqos[3] [52]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[59] + (.C(aclk), + .CE(p_1_in), + .D(D[53]), + .Q(\m_axi_arqos[3] [53]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[5] + (.C(aclk), + .CE(p_1_in), + .D(D[4]), + .Q(\m_axi_arqos[3] [4]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[60] + (.C(aclk), + .CE(p_1_in), + .D(D[54]), + .Q(\m_axi_arqos[3] [54]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[61] + (.C(aclk), + .CE(p_1_in), + .D(D[55]), + .Q(\m_axi_arqos[3] [55]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[62] + (.C(aclk), + .CE(p_1_in), + .D(D[56]), + .Q(\m_axi_arqos[3] [56]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[6] + (.C(aclk), + .CE(p_1_in), + .D(D[5]), + .Q(\m_axi_arqos[3] [5]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[7] + (.C(aclk), + .CE(p_1_in), + .D(D[6]), + .Q(\m_axi_arqos[3] [6]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[8] + (.C(aclk), + .CE(p_1_in), + .D(D[7]), + .Q(\m_axi_arqos[3] [7]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[9] + (.C(aclk), + .CE(p_1_in), + .D(D[8]), + .Q(\m_axi_arqos[3] [8]), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT3 #( + .INIT(8'h01)) + \gen_arbiter.m_target_hot_i[0]_i_1__0 + (.I0(D[31]), + .I1(D[30]), + .I2(D[29]), + .O(\gen_arbiter.m_target_hot_i_reg[0]_0 )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT3 #( + .INIT(8'hFE)) + \gen_arbiter.m_target_hot_i[1]_i_1__0 + (.I0(D[29]), + .I1(D[30]), + .I2(D[31]), + .O(\gen_arbiter.m_target_hot_i[1]_i_1__0_n_0 )); + FDRE \gen_arbiter.m_target_hot_i_reg[0] + (.C(aclk), + .CE(grant_hot), + .D(\gen_arbiter.m_target_hot_i_reg[0]_0 ), + .Q(aa_mi_artarget_hot), + .R(SR)); + FDRE \gen_arbiter.m_target_hot_i_reg[1] + (.C(aclk), + .CE(grant_hot), + .D(\gen_arbiter.m_target_hot_i[1]_i_1__0_n_0 ), + .Q(Q), + .R(SR)); + LUT6 #( + .INIT(64'h003F3F3FAAAAAAAA)) + \gen_arbiter.m_valid_i_i_1__0 + (.I0(\gen_arbiter.any_grant_reg_n_0 ), + .I1(Q), + .I2(mi_arready), + .I3(m_axi_arready), + .I4(aa_mi_artarget_hot), + .I5(aa_mi_arvalid), + .O(\gen_arbiter.m_valid_i_i_1__0_n_0 )); + FDRE \gen_arbiter.m_valid_i_reg + (.C(aclk), + .CE(1'b1), + .D(\gen_arbiter.m_valid_i_i_1__0_n_0 ), + .Q(aa_mi_arvalid), + .R(SR)); + LUT3 #( + .INIT(8'hFE)) + \gen_arbiter.qual_reg[0]_i_4 + (.I0(\gen_master_slots[0].r_issuing_cnt_reg[3]_0 [2]), + .I1(\gen_master_slots[0].r_issuing_cnt_reg[3]_0 [1]), + .I2(\gen_master_slots[0].r_issuing_cnt_reg[3]_0 [0]), + .O(\gen_arbiter.qual_reg_reg[0]_0 )); + FDRE \gen_arbiter.qual_reg_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\gen_master_slots[0].r_issuing_cnt_reg[3] ), + .Q(qual_reg), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT4 #( + .INIT(16'h0800)) + \gen_arbiter.s_ready_i[0]_i_1 + (.I0(\gen_arbiter.grant_hot_reg_n_0_[0] ), + .I1(aresetn_d), + .I2(aa_mi_arvalid), + .I3(\gen_arbiter.any_grant_reg_n_0 ), + .O(\gen_arbiter.s_ready_i[0]_i_1_n_0 )); + FDRE \gen_arbiter.s_ready_i_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\gen_arbiter.s_ready_i[0]_i_1_n_0 ), + .Q(\s_axi_arready[0] ), + .R(1'b0)); + LUT4 #( + .INIT(16'h0002)) + \gen_axi.s_axi_rlast_i_i_2 + (.I0(\gen_axi.s_axi_rlast_i_i_4_n_0 ), + .I1(p_11_in), + .I2(\m_axi_arqos[3] [32]), + .I3(\m_axi_arqos[3] [33]), + .O(\gen_axi.s_axi_rlast_i_reg )); + LUT6 #( + .INIT(64'h0000000000000001)) + \gen_axi.s_axi_rlast_i_i_4 + (.I0(\m_axi_arqos[3] [34]), + .I1(\m_axi_arqos[3] [35]), + .I2(\m_axi_arqos[3] [36]), + .I3(\m_axi_arqos[3] [37]), + .I4(\m_axi_arqos[3] [39]), + .I5(\m_axi_arqos[3] [38]), + .O(\gen_axi.s_axi_rlast_i_i_4_n_0 )); + LUT6 #( + .INIT(64'h0000FFFFFFFE0000)) + \gen_master_slots[0].r_issuing_cnt[3]_i_1 + (.I0(\gen_master_slots[0].r_issuing_cnt_reg[3]_0 [3]), + .I1(\gen_master_slots[0].r_issuing_cnt_reg[3]_0 [2]), + .I2(\gen_master_slots[0].r_issuing_cnt_reg[3]_0 [1]), + .I3(\gen_master_slots[0].r_issuing_cnt_reg[3]_0 [0]), + .I4(\gen_master_slots[0].r_issuing_cnt_reg[0] ), + .I5(m_valid_i_reg), + .O(E)); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h7F)) + \gen_master_slots[0].r_issuing_cnt[3]_i_3 + (.I0(aa_mi_arvalid), + .I1(aa_mi_artarget_hot), + .I2(m_axi_arready), + .O(\gen_master_slots[0].r_issuing_cnt_reg[0] )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT3 #( + .INIT(8'h7F)) + \gen_master_slots[1].r_issuing_cnt[8]_i_2 + (.I0(aa_mi_arvalid), + .I1(Q), + .I2(mi_arready), + .O(\gen_master_slots[1].r_issuing_cnt_reg[8] )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hFEFFFE00)) + \gen_single_thread.active_target_enc[0]_i_1__0 + (.I0(D[29]), + .I1(D[30]), + .I2(D[31]), + .I3(\s_axi_arready[0] ), + .I4(active_target_enc), + .O(\gen_single_thread.active_target_enc_reg[0] )); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT5 #( + .INIT(32'h01FF0100)) + \gen_single_thread.active_target_hot[0]_i_1__0 + (.I0(D[31]), + .I1(D[30]), + .I2(D[29]), + .I3(\s_axi_arready[0] ), + .I4(active_target_hot), + .O(\gen_single_thread.active_target_hot_reg[0] )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_arvalid[0]_INST_0 + (.I0(aa_mi_artarget_hot), + .I1(aa_mi_arvalid), + .O(m_axi_arvalid)); +endmodule + +(* ORIG_REF_NAME = "axi_crossbar_v2_1_12_addr_arbiter" *) +module Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_addr_arbiter_0 + (aa_wm_awgrant_enc, + SR, + aa_sa_awvalid, + ss_aa_awready, + \storage_data1_reg[0] , + Q, + sa_wm_awvalid, + \gen_master_slots[1].w_issuing_cnt_reg[8] , + \m_ready_d_reg[1] , + sel_4, + E, + D, + \gen_arbiter.qual_reg_reg[1]_0 , + m_axi_awvalid, + \storage_data1_reg[0]_0 , + m_valid_i_reg, + \m_ready_d_reg[1]_0 , + \m_axi_awqos[3] , + aclk, + \m_ready_d_reg[0] , + st_aa_awvalid_qual, + valid_qual_i111_in, + \gen_arbiter.m_valid_i_reg_0 , + aa_sa_awready, + aresetn_d, + out, + m_ready_d, + mi_awready, + m_ready_d_0, + s_axi_awvalid, + s_axi_awaddr, + \gen_master_slots[0].w_issuing_cnt_reg[3] , + \gen_single_thread.active_target_hot_reg[0] , + m_axi_awready, + s_axi_awqos, + s_axi_awcache, + s_axi_awburst, + s_axi_awprot, + s_axi_awlock, + s_axi_awsize, + s_axi_awlen); + output aa_wm_awgrant_enc; + output [0:0]SR; + output aa_sa_awvalid; + output [0:0]ss_aa_awready; + output \storage_data1_reg[0] ; + output [1:0]Q; + output [0:0]sa_wm_awvalid; + output \gen_master_slots[1].w_issuing_cnt_reg[8] ; + output \m_ready_d_reg[1] ; + output sel_4; + output [0:0]E; + output [2:0]D; + output \gen_arbiter.qual_reg_reg[1]_0 ; + output [0:0]m_axi_awvalid; + output \storage_data1_reg[0]_0 ; + output m_valid_i_reg; + output \m_ready_d_reg[1]_0 ; + output [57:0]\m_axi_awqos[3] ; + input aclk; + input \m_ready_d_reg[0] ; + input [0:0]st_aa_awvalid_qual; + input valid_qual_i111_in; + input \gen_arbiter.m_valid_i_reg_0 ; + input aa_sa_awready; + input aresetn_d; + input [1:0]out; + input [1:0]m_ready_d; + input [0:0]mi_awready; + input [0:0]m_ready_d_0; + input [0:0]s_axi_awvalid; + input [31:0]s_axi_awaddr; + input [3:0]\gen_master_slots[0].w_issuing_cnt_reg[3] ; + input \gen_single_thread.active_target_hot_reg[0] ; + input [0:0]m_axi_awready; + input [3:0]s_axi_awqos; + input [3:0]s_axi_awcache; + input [1:0]s_axi_awburst; + input [2:0]s_axi_awprot; + input [0:0]s_axi_awlock; + input [2:0]s_axi_awsize; + input [7:0]s_axi_awlen; + + wire [2:0]D; + wire [0:0]E; + wire [1:0]Q; + wire [0:0]SR; + wire aa_sa_awready; + wire aa_sa_awvalid; + wire aa_wm_awgrant_enc; + wire aclk; + wire aresetn_d; + wire \gen_arbiter.any_grant_i_1_n_0 ; + wire \gen_arbiter.any_grant_reg_n_0 ; + wire \gen_arbiter.grant_hot[1]_i_1_n_0 ; + wire \gen_arbiter.grant_hot[1]_i_2_n_0 ; + wire \gen_arbiter.grant_hot_reg_n_0_[1] ; + wire \gen_arbiter.m_grant_enc_i[0]_i_2_n_0 ; + wire \gen_arbiter.m_valid_i_i_1_n_0 ; + wire \gen_arbiter.m_valid_i_reg_0 ; + wire \gen_arbiter.qual_reg_reg[1]_0 ; + wire \gen_arbiter.s_ready_i[1]_i_1_n_0 ; + wire \gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0 ; + wire \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0 ; + wire [3:0]\gen_master_slots[0].w_issuing_cnt_reg[3] ; + wire \gen_master_slots[1].w_issuing_cnt_reg[8] ; + wire \gen_single_thread.active_target_hot_reg[0] ; + wire grant_hot; + wire [57:0]\m_axi_awqos[3] ; + wire [0:0]m_axi_awready; + wire [0:0]m_axi_awvalid; + wire [62:1]m_mesg_mux; + wire [1:0]m_ready_d; + wire [0:0]m_ready_d_0; + wire \m_ready_d_reg[0] ; + wire \m_ready_d_reg[1] ; + wire \m_ready_d_reg[1]_0 ; + wire [1:0]m_target_hot_mux; + wire m_valid_i_reg; + wire [0:0]mi_awready; + wire [1:0]out; + wire p_1_in; + wire p_2_in; + wire [1:1]qual_reg; + wire [31:0]s_axi_awaddr; + wire [1:0]s_axi_awburst; + wire [3:0]s_axi_awcache; + wire [7:0]s_axi_awlen; + wire [0:0]s_axi_awlock; + wire [2:0]s_axi_awprot; + wire [3:0]s_axi_awqos; + wire [2:0]s_axi_awsize; + wire [0:0]s_axi_awvalid; + wire [0:0]sa_wm_awvalid; + wire sel_4; + wire [0:0]ss_aa_awready; + wire [0:0]st_aa_awvalid_qual; + wire \storage_data1_reg[0] ; + wire \storage_data1_reg[0]_0 ; + wire valid_qual_i111_in; + + LUT6 #( + .INIT(64'h00000000F0F8F0F0)) + \gen_arbiter.any_grant_i_1 + (.I0(st_aa_awvalid_qual), + .I1(\gen_arbiter.m_grant_enc_i[0]_i_2_n_0 ), + .I2(\gen_arbiter.any_grant_reg_n_0 ), + .I3(aa_sa_awvalid), + .I4(valid_qual_i111_in), + .I5(\gen_arbiter.m_valid_i_reg_0 ), + .O(\gen_arbiter.any_grant_i_1_n_0 )); + FDRE \gen_arbiter.any_grant_reg + (.C(aclk), + .CE(1'b1), + .D(\gen_arbiter.any_grant_i_1_n_0 ), + .Q(\gen_arbiter.any_grant_reg_n_0 ), + .R(1'b0)); + LUT6 #( + .INIT(64'h00000000EAAAAAAA)) + \gen_arbiter.grant_hot[1]_i_1 + (.I0(\gen_arbiter.grant_hot_reg_n_0_[1] ), + .I1(st_aa_awvalid_qual), + .I2(\gen_arbiter.m_grant_enc_i[0]_i_2_n_0 ), + .I3(\gen_arbiter.grant_hot[1]_i_2_n_0 ), + .I4(valid_qual_i111_in), + .I5(\gen_arbiter.m_valid_i_reg_0 ), + .O(\gen_arbiter.grant_hot[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT2 #( + .INIT(4'h1)) + \gen_arbiter.grant_hot[1]_i_2 + (.I0(\gen_arbiter.any_grant_reg_n_0 ), + .I1(aa_sa_awvalid), + .O(\gen_arbiter.grant_hot[1]_i_2_n_0 )); + FDRE \gen_arbiter.grant_hot_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\gen_arbiter.grant_hot[1]_i_1_n_0 ), + .Q(\gen_arbiter.grant_hot_reg_n_0_[1] ), + .R(1'b0)); + FDSE \gen_arbiter.last_rr_hot_reg[1] + (.C(aclk), + .CE(grant_hot), + .D(\gen_arbiter.m_grant_enc_i[0]_i_2_n_0 ), + .Q(p_2_in), + .S(SR)); + LUT5 #( + .INIT(32'h02000000)) + \gen_arbiter.m_grant_enc_i[0]_i_1 + (.I0(valid_qual_i111_in), + .I1(aa_sa_awvalid), + .I2(\gen_arbiter.any_grant_reg_n_0 ), + .I3(\gen_arbiter.m_grant_enc_i[0]_i_2_n_0 ), + .I4(st_aa_awvalid_qual), + .O(grant_hot)); + LUT5 #( + .INIT(32'h00000080)) + \gen_arbiter.m_grant_enc_i[0]_i_2 + (.I0(s_axi_awvalid), + .I1(p_2_in), + .I2(qual_reg), + .I3(m_ready_d_0), + .I4(ss_aa_awready), + .O(\gen_arbiter.m_grant_enc_i[0]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT3 #( + .INIT(8'hFE)) + \gen_arbiter.m_grant_enc_i[0]_i_5 + (.I0(\gen_master_slots[0].w_issuing_cnt_reg[3] [2]), + .I1(\gen_master_slots[0].w_issuing_cnt_reg[3] [1]), + .I2(\gen_master_slots[0].w_issuing_cnt_reg[3] [0]), + .O(\gen_arbiter.qual_reg_reg[1]_0 )); + FDRE \gen_arbiter.m_grant_enc_i_reg[0] + (.C(aclk), + .CE(grant_hot), + .D(\gen_arbiter.m_grant_enc_i[0]_i_2_n_0 ), + .Q(aa_wm_awgrant_enc), + .R(SR)); + LUT1 #( + .INIT(2'h1)) + \gen_arbiter.m_mesg_i[0]_i_1 + (.I0(aresetn_d), + .O(SR)); + LUT1 #( + .INIT(2'h1)) + \gen_arbiter.m_mesg_i[0]_i_2 + (.I0(aa_sa_awvalid), + .O(p_1_in)); + (* SOFT_HLUTNM = "soft_lutpair38" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[10]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[9]), + .O(m_mesg_mux[10])); + (* SOFT_HLUTNM = "soft_lutpair37" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[11]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[10]), + .O(m_mesg_mux[11])); + (* SOFT_HLUTNM = "soft_lutpair37" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[12]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[11]), + .O(m_mesg_mux[12])); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[13]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[12]), + .O(m_mesg_mux[13])); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[14]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[13]), + .O(m_mesg_mux[14])); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[15]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[14]), + .O(m_mesg_mux[15])); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[16]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[15]), + .O(m_mesg_mux[16])); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[17]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[16]), + .O(m_mesg_mux[17])); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[18]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[17]), + .O(m_mesg_mux[18])); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[19]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[18]), + .O(m_mesg_mux[19])); + (* SOFT_HLUTNM = "soft_lutpair42" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[1]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[0]), + .O(m_mesg_mux[1])); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[20]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[19]), + .O(m_mesg_mux[20])); + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[21]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[20]), + .O(m_mesg_mux[21])); + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[22]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[21]), + .O(m_mesg_mux[22])); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[23]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[22]), + .O(m_mesg_mux[23])); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[24]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[23]), + .O(m_mesg_mux[24])); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[25]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[24]), + .O(m_mesg_mux[25])); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[26]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[25]), + .O(m_mesg_mux[26])); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[27]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[26]), + .O(m_mesg_mux[27])); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[28]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[27]), + .O(m_mesg_mux[28])); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[29]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[28]), + .O(m_mesg_mux[29])); + (* SOFT_HLUTNM = "soft_lutpair42" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[2]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[1]), + .O(m_mesg_mux[2])); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[30]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[29]), + .O(m_mesg_mux[30])); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[31]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[30]), + .O(m_mesg_mux[31])); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[32]_i_1__0 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[31]), + .O(m_mesg_mux[32])); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[33]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awlen[0]), + .O(m_mesg_mux[33])); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[34]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awlen[1]), + .O(m_mesg_mux[34])); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[35]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awlen[2]), + .O(m_mesg_mux[35])); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[36]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awlen[3]), + .O(m_mesg_mux[36])); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[37]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awlen[4]), + .O(m_mesg_mux[37])); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[38]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awlen[5]), + .O(m_mesg_mux[38])); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[39]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awlen[6]), + .O(m_mesg_mux[39])); + (* SOFT_HLUTNM = "soft_lutpair41" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[3]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[2]), + .O(m_mesg_mux[3])); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[40]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awlen[7]), + .O(m_mesg_mux[40])); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[41]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awsize[0]), + .O(m_mesg_mux[41])); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[42]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awsize[1]), + .O(m_mesg_mux[42])); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[43]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awsize[2]), + .O(m_mesg_mux[43])); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[44]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awlock), + .O(m_mesg_mux[44])); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[46]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awprot[0]), + .O(m_mesg_mux[46])); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[47]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awprot[1]), + .O(m_mesg_mux[47])); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[48]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awprot[2]), + .O(m_mesg_mux[48])); + (* SOFT_HLUTNM = "soft_lutpair41" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[4]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[3]), + .O(m_mesg_mux[4])); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[53]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awburst[0]), + .O(m_mesg_mux[53])); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[54]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awburst[1]), + .O(m_mesg_mux[54])); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[55]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awcache[0]), + .O(m_mesg_mux[55])); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[56]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awcache[1]), + .O(m_mesg_mux[56])); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[57]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awcache[2]), + .O(m_mesg_mux[57])); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[58]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awcache[3]), + .O(m_mesg_mux[58])); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[59]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awqos[0]), + .O(m_mesg_mux[59])); + (* SOFT_HLUTNM = "soft_lutpair40" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[5]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[4]), + .O(m_mesg_mux[5])); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[60]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awqos[1]), + .O(m_mesg_mux[60])); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[61]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awqos[2]), + .O(m_mesg_mux[61])); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[62]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awqos[3]), + .O(m_mesg_mux[62])); + (* SOFT_HLUTNM = "soft_lutpair40" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[6]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[5]), + .O(m_mesg_mux[6])); + (* SOFT_HLUTNM = "soft_lutpair39" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[7]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[6]), + .O(m_mesg_mux[7])); + (* SOFT_HLUTNM = "soft_lutpair39" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[8]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[7]), + .O(m_mesg_mux[8])); + (* SOFT_HLUTNM = "soft_lutpair38" *) + LUT2 #( + .INIT(4'h8)) + \gen_arbiter.m_mesg_i[9]_i_1 + (.I0(aa_wm_awgrant_enc), + .I1(s_axi_awaddr[8]), + .O(m_mesg_mux[9])); + FDRE \gen_arbiter.m_mesg_i_reg[0] + (.C(aclk), + .CE(p_1_in), + .D(aa_wm_awgrant_enc), + .Q(\m_axi_awqos[3] [0]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[10] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[10]), + .Q(\m_axi_awqos[3] [10]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[11] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[11]), + .Q(\m_axi_awqos[3] [11]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[12] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[12]), + .Q(\m_axi_awqos[3] [12]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[13] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[13]), + .Q(\m_axi_awqos[3] [13]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[14] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[14]), + .Q(\m_axi_awqos[3] [14]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[15] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[15]), + .Q(\m_axi_awqos[3] [15]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[16] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[16]), + .Q(\m_axi_awqos[3] [16]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[17] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[17]), + .Q(\m_axi_awqos[3] [17]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[18] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[18]), + .Q(\m_axi_awqos[3] [18]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[19] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[19]), + .Q(\m_axi_awqos[3] [19]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[1] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[1]), + .Q(\m_axi_awqos[3] [1]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[20] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[20]), + .Q(\m_axi_awqos[3] [20]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[21] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[21]), + .Q(\m_axi_awqos[3] [21]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[22] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[22]), + .Q(\m_axi_awqos[3] [22]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[23] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[23]), + .Q(\m_axi_awqos[3] [23]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[24] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[24]), + .Q(\m_axi_awqos[3] [24]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[25] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[25]), + .Q(\m_axi_awqos[3] [25]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[26] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[26]), + .Q(\m_axi_awqos[3] [26]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[27] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[27]), + .Q(\m_axi_awqos[3] [27]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[28] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[28]), + .Q(\m_axi_awqos[3] [28]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[29] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[29]), + .Q(\m_axi_awqos[3] [29]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[2] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[2]), + .Q(\m_axi_awqos[3] [2]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[30] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[30]), + .Q(\m_axi_awqos[3] [30]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[31] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[31]), + .Q(\m_axi_awqos[3] [31]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[32] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[32]), + .Q(\m_axi_awqos[3] [32]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[33] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[33]), + .Q(\m_axi_awqos[3] [33]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[34] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[34]), + .Q(\m_axi_awqos[3] [34]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[35] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[35]), + .Q(\m_axi_awqos[3] [35]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[36] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[36]), + .Q(\m_axi_awqos[3] [36]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[37] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[37]), + .Q(\m_axi_awqos[3] [37]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[38] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[38]), + .Q(\m_axi_awqos[3] [38]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[39] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[39]), + .Q(\m_axi_awqos[3] [39]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[3] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[3]), + .Q(\m_axi_awqos[3] [3]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[40] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[40]), + .Q(\m_axi_awqos[3] [40]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[41] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[41]), + .Q(\m_axi_awqos[3] [41]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[42] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[42]), + .Q(\m_axi_awqos[3] [42]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[43] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[43]), + .Q(\m_axi_awqos[3] [43]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[44] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[44]), + .Q(\m_axi_awqos[3] [44]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[46] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[46]), + .Q(\m_axi_awqos[3] [45]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[47] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[47]), + .Q(\m_axi_awqos[3] [46]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[48] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[48]), + .Q(\m_axi_awqos[3] [47]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[4] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[4]), + .Q(\m_axi_awqos[3] [4]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[53] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[53]), + .Q(\m_axi_awqos[3] [48]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[54] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[54]), + .Q(\m_axi_awqos[3] [49]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[55] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[55]), + .Q(\m_axi_awqos[3] [50]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[56] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[56]), + .Q(\m_axi_awqos[3] [51]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[57] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[57]), + .Q(\m_axi_awqos[3] [52]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[58] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[58]), + .Q(\m_axi_awqos[3] [53]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[59] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[59]), + .Q(\m_axi_awqos[3] [54]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[5] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[5]), + .Q(\m_axi_awqos[3] [5]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[60] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[60]), + .Q(\m_axi_awqos[3] [55]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[61] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[61]), + .Q(\m_axi_awqos[3] [56]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[62] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[62]), + .Q(\m_axi_awqos[3] [57]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[6] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[6]), + .Q(\m_axi_awqos[3] [6]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[7] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[7]), + .Q(\m_axi_awqos[3] [7]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[8] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[8]), + .Q(\m_axi_awqos[3] [8]), + .R(SR)); + FDRE \gen_arbiter.m_mesg_i_reg[9] + (.C(aclk), + .CE(p_1_in), + .D(m_mesg_mux[9]), + .Q(\m_axi_awqos[3] [9]), + .R(SR)); + LUT6 #( + .INIT(64'h1000000000000000)) + \gen_arbiter.m_target_hot_i[0]_i_1 + (.I0(ss_aa_awready), + .I1(m_ready_d_0), + .I2(qual_reg), + .I3(p_2_in), + .I4(s_axi_awvalid), + .I5(sel_4), + .O(m_target_hot_mux[0])); + LUT6 #( + .INIT(64'h0000000010000000)) + \gen_arbiter.m_target_hot_i[1]_i_1 + (.I0(ss_aa_awready), + .I1(m_ready_d_0), + .I2(qual_reg), + .I3(p_2_in), + .I4(s_axi_awvalid), + .I5(sel_4), + .O(m_target_hot_mux[1])); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT3 #( + .INIT(8'h01)) + \gen_arbiter.m_target_hot_i[1]_i_2 + (.I0(s_axi_awaddr[31]), + .I1(s_axi_awaddr[30]), + .I2(s_axi_awaddr[29]), + .O(sel_4)); + FDRE \gen_arbiter.m_target_hot_i_reg[0] + (.C(aclk), + .CE(grant_hot), + .D(m_target_hot_mux[0]), + .Q(Q[0]), + .R(SR)); + FDRE \gen_arbiter.m_target_hot_i_reg[1] + (.C(aclk), + .CE(grant_hot), + .D(m_target_hot_mux[1]), + .Q(Q[1]), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT3 #( + .INIT(8'h5C)) + \gen_arbiter.m_valid_i_i_1 + (.I0(aa_sa_awready), + .I1(\gen_arbiter.any_grant_reg_n_0 ), + .I2(aa_sa_awvalid), + .O(\gen_arbiter.m_valid_i_i_1_n_0 )); + FDRE \gen_arbiter.m_valid_i_reg + (.C(aclk), + .CE(1'b1), + .D(\gen_arbiter.m_valid_i_i_1_n_0 ), + .Q(aa_sa_awvalid), + .R(SR)); + FDRE \gen_arbiter.qual_reg_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\m_ready_d_reg[0] ), + .Q(qual_reg), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT4 #( + .INIT(16'h0800)) + \gen_arbiter.s_ready_i[1]_i_1 + (.I0(\gen_arbiter.grant_hot_reg_n_0_[1] ), + .I1(aresetn_d), + .I2(aa_sa_awvalid), + .I3(\gen_arbiter.any_grant_reg_n_0 ), + .O(\gen_arbiter.s_ready_i[1]_i_1_n_0 )); + FDRE \gen_arbiter.s_ready_i_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\gen_arbiter.s_ready_i[1]_i_1_n_0 ), + .Q(ss_aa_awready), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT4 #( + .INIT(16'hDFFF)) + \gen_axi.write_cs[0]_i_2 + (.I0(mi_awready), + .I1(m_ready_d[1]), + .I2(aa_sa_awvalid), + .I3(Q[1]), + .O(\gen_master_slots[1].w_issuing_cnt_reg[8] )); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT3 #( + .INIT(8'h69)) + \gen_master_slots[0].w_issuing_cnt[1]_i_1 + (.I0(\gen_master_slots[0].w_issuing_cnt_reg[3] [1]), + .I1(\gen_master_slots[0].w_issuing_cnt_reg[3] [0]), + .I2(\gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0 ), + .O(D[0])); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT4 #( + .INIT(16'h6AA9)) + \gen_master_slots[0].w_issuing_cnt[2]_i_1 + (.I0(\gen_master_slots[0].w_issuing_cnt_reg[3] [2]), + .I1(\gen_master_slots[0].w_issuing_cnt_reg[3] [0]), + .I2(\gen_master_slots[0].w_issuing_cnt_reg[3] [1]), + .I3(\gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0 ), + .O(D[1])); + LUT6 #( + .INIT(64'h0000FFFFFFFE0000)) + \gen_master_slots[0].w_issuing_cnt[3]_i_1 + (.I0(\gen_master_slots[0].w_issuing_cnt_reg[3] [3]), + .I1(\gen_master_slots[0].w_issuing_cnt_reg[3] [2]), + .I2(\gen_master_slots[0].w_issuing_cnt_reg[3] [1]), + .I3(\gen_master_slots[0].w_issuing_cnt_reg[3] [0]), + .I4(\gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0 ), + .I5(\gen_single_thread.active_target_hot_reg[0] ), + .O(E)); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT5 #( + .INIT(32'h6AAAAAA9)) + \gen_master_slots[0].w_issuing_cnt[3]_i_2 + (.I0(\gen_master_slots[0].w_issuing_cnt_reg[3] [3]), + .I1(\gen_master_slots[0].w_issuing_cnt_reg[3] [1]), + .I2(\gen_master_slots[0].w_issuing_cnt_reg[3] [2]), + .I3(\gen_master_slots[0].w_issuing_cnt_reg[3] [0]), + .I4(\gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0 ), + .O(D[2])); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT4 #( + .INIT(16'hDFFF)) + \gen_master_slots[0].w_issuing_cnt[3]_i_3 + (.I0(m_axi_awready), + .I1(m_ready_d[1]), + .I2(aa_sa_awvalid), + .I3(Q[0]), + .O(\gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT5 #( + .INIT(32'h00800000)) + \gen_master_slots[0].w_issuing_cnt[3]_i_5 + (.I0(\gen_single_thread.active_target_hot_reg[0] ), + .I1(Q[0]), + .I2(aa_sa_awvalid), + .I3(m_ready_d[1]), + .I4(m_axi_awready), + .O(\gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT3 #( + .INIT(8'h08)) + \m_axi_awvalid[0]_INST_0 + (.I0(aa_sa_awvalid), + .I1(Q[0]), + .I2(m_ready_d[1]), + .O(m_axi_awvalid)); + LUT2 #( + .INIT(4'h7)) + \m_ready_d[1]_i_2 + (.I0(Q[0]), + .I1(aa_sa_awvalid), + .O(\m_ready_d_reg[1]_0 )); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT2 #( + .INIT(4'h7)) + \m_ready_d[1]_i_3 + (.I0(Q[1]), + .I1(aa_sa_awvalid), + .O(\m_ready_d_reg[1] )); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT3 #( + .INIT(8'h08)) + m_valid_i_i_1 + (.I0(aa_sa_awvalid), + .I1(Q[1]), + .I2(m_ready_d[0]), + .O(sa_wm_awvalid)); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT3 #( + .INIT(8'hF7)) + m_valid_i_i_1__1 + (.I0(aa_sa_awvalid), + .I1(Q[0]), + .I2(m_ready_d[0]), + .O(m_valid_i_reg)); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT4 #( + .INIT(16'h2000)) + \storage_data1[0]_i_3 + (.I0(out[0]), + .I1(m_ready_d[0]), + .I2(Q[0]), + .I3(aa_sa_awvalid), + .O(\storage_data1_reg[0] )); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT4 #( + .INIT(16'h2000)) + \storage_data1[0]_i_4 + (.I0(out[1]), + .I1(m_ready_d[0]), + .I2(Q[0]), + .I3(aa_sa_awvalid), + .O(\storage_data1_reg[0]_0 )); +endmodule + +(* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) +(* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) +(* C_AXI_PROTOCOL = "0" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *) +(* C_AXI_WUSER_WIDTH = "1" *) (* C_CONNECTIVITY_MODE = "1" *) (* C_DEBUG = "1" *) +(* C_FAMILY = "zynq" *) (* C_M_AXI_ADDR_WIDTH = "29" *) (* C_M_AXI_BASE_ADDR = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) +(* C_M_AXI_READ_CONNECTIVITY = "1" *) (* C_M_AXI_READ_ISSUING = "8" *) (* C_M_AXI_SECURE = "0" *) +(* C_M_AXI_WRITE_CONNECTIVITY = "2" *) (* C_M_AXI_WRITE_ISSUING = "8" *) (* C_NUM_ADDR_RANGES = "1" *) +(* C_NUM_MASTER_SLOTS = "1" *) (* C_NUM_SLAVE_SLOTS = "2" *) (* C_R_REGISTER = "0" *) +(* C_S_AXI_ARB_PRIORITY = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_S_AXI_BASE_ID = "64'b0000000000000000000000000000000100000000000000000000000000000000" *) (* C_S_AXI_READ_ACCEPTANCE = "64'b0000000000000000000000000000001000000000000000000000000000000010" *) +(* C_S_AXI_SINGLE_THREAD = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_S_AXI_THREAD_ID_WIDTH = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_S_AXI_WRITE_ACCEPTANCE = "64'b0000000000000000000000000000001000000000000000000000000000000010" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) (* P_ADDR_DECODE = "1" *) (* P_AXI3 = "1" *) +(* P_AXI4 = "0" *) (* P_AXILITE = "2" *) (* P_AXILITE_SIZE = "3'b010" *) +(* P_FAMILY = "zynq" *) (* P_INCR = "2'b01" *) (* P_LEN = "8" *) +(* P_LOCK = "1" *) (* P_M_AXI_ERR_MODE = "32'b00000000000000000000000000000000" *) (* P_M_AXI_SUPPORTS_READ = "1'b1" *) +(* P_M_AXI_SUPPORTS_WRITE = "1'b1" *) (* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *) (* P_RANGE_CHECK = "1" *) +(* P_S_AXI_BASE_ID = "128'b00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000" *) (* P_S_AXI_HIGH_ID = "128'b00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000" *) (* P_S_AXI_SUPPORTS_READ = "2'b01" *) +(* P_S_AXI_SUPPORTS_WRITE = "2'b10" *) +module Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar + (aclk, + aresetn, + s_axi_awid, + s_axi_awaddr, + s_axi_awlen, + s_axi_awsize, + s_axi_awburst, + s_axi_awlock, + s_axi_awcache, + s_axi_awprot, + s_axi_awqos, + s_axi_awuser, + s_axi_awvalid, + s_axi_awready, + s_axi_wid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wlast, + s_axi_wuser, + s_axi_wvalid, + s_axi_wready, + s_axi_bid, + s_axi_bresp, + s_axi_buser, + s_axi_bvalid, + s_axi_bready, + s_axi_arid, + s_axi_araddr, + s_axi_arlen, + s_axi_arsize, + s_axi_arburst, + s_axi_arlock, + s_axi_arcache, + s_axi_arprot, + s_axi_arqos, + s_axi_aruser, + s_axi_arvalid, + s_axi_arready, + s_axi_rid, + s_axi_rdata, + s_axi_rresp, + s_axi_rlast, + s_axi_ruser, + s_axi_rvalid, + s_axi_rready, + m_axi_awid, + m_axi_awaddr, + m_axi_awlen, + m_axi_awsize, + m_axi_awburst, + m_axi_awlock, + m_axi_awcache, + m_axi_awprot, + m_axi_awregion, + m_axi_awqos, + m_axi_awuser, + m_axi_awvalid, + m_axi_awready, + m_axi_wid, + m_axi_wdata, + m_axi_wstrb, + m_axi_wlast, + m_axi_wuser, + m_axi_wvalid, + m_axi_wready, + m_axi_bid, + m_axi_bresp, + m_axi_buser, + m_axi_bvalid, + m_axi_bready, + m_axi_arid, + m_axi_araddr, + m_axi_arlen, + m_axi_arsize, + m_axi_arburst, + m_axi_arlock, + m_axi_arcache, + m_axi_arprot, + m_axi_arregion, + m_axi_arqos, + m_axi_aruser, + m_axi_arvalid, + m_axi_arready, + m_axi_rid, + m_axi_rdata, + m_axi_rresp, + m_axi_rlast, + m_axi_ruser, + m_axi_rvalid, + m_axi_rready); + input aclk; + input aresetn; + input [1:0]s_axi_awid; + input [63:0]s_axi_awaddr; + input [15:0]s_axi_awlen; + input [5:0]s_axi_awsize; + input [3:0]s_axi_awburst; + input [1:0]s_axi_awlock; + input [7:0]s_axi_awcache; + input [5:0]s_axi_awprot; + input [7:0]s_axi_awqos; + input [1:0]s_axi_awuser; + input [1:0]s_axi_awvalid; + output [1:0]s_axi_awready; + input [1:0]s_axi_wid; + input [127:0]s_axi_wdata; + input [15:0]s_axi_wstrb; + input [1:0]s_axi_wlast; + input [1:0]s_axi_wuser; + input [1:0]s_axi_wvalid; + output [1:0]s_axi_wready; + output [1:0]s_axi_bid; + output [3:0]s_axi_bresp; + output [1:0]s_axi_buser; + output [1:0]s_axi_bvalid; + input [1:0]s_axi_bready; + input [1:0]s_axi_arid; + input [63:0]s_axi_araddr; + input [15:0]s_axi_arlen; + input [5:0]s_axi_arsize; + input [3:0]s_axi_arburst; + input [1:0]s_axi_arlock; + input [7:0]s_axi_arcache; + input [5:0]s_axi_arprot; + input [7:0]s_axi_arqos; + input [1:0]s_axi_aruser; + input [1:0]s_axi_arvalid; + output [1:0]s_axi_arready; + output [1:0]s_axi_rid; + output [127:0]s_axi_rdata; + output [3:0]s_axi_rresp; + output [1:0]s_axi_rlast; + output [1:0]s_axi_ruser; + output [1:0]s_axi_rvalid; + input [1:0]s_axi_rready; + output [0:0]m_axi_awid; + output [31:0]m_axi_awaddr; + output [7:0]m_axi_awlen; + output [2:0]m_axi_awsize; + output [1:0]m_axi_awburst; + output [0:0]m_axi_awlock; + output [3:0]m_axi_awcache; + output [2:0]m_axi_awprot; + output [3:0]m_axi_awregion; + output [3:0]m_axi_awqos; + output [0:0]m_axi_awuser; + output [0:0]m_axi_awvalid; + input [0:0]m_axi_awready; + output [0:0]m_axi_wid; + output [63:0]m_axi_wdata; + output [7:0]m_axi_wstrb; + output [0:0]m_axi_wlast; + output [0:0]m_axi_wuser; + output [0:0]m_axi_wvalid; + input [0:0]m_axi_wready; + input [0:0]m_axi_bid; + input [1:0]m_axi_bresp; + input [0:0]m_axi_buser; + input [0:0]m_axi_bvalid; + output [0:0]m_axi_bready; + output [0:0]m_axi_arid; + output [31:0]m_axi_araddr; + output [7:0]m_axi_arlen; + output [2:0]m_axi_arsize; + output [1:0]m_axi_arburst; + output [0:0]m_axi_arlock; + output [3:0]m_axi_arcache; + output [2:0]m_axi_arprot; + output [3:0]m_axi_arregion; + output [3:0]m_axi_arqos; + output [0:0]m_axi_aruser; + output [0:0]m_axi_arvalid; + input [0:0]m_axi_arready; + input [0:0]m_axi_rid; + input [63:0]m_axi_rdata; + input [1:0]m_axi_rresp; + input [0:0]m_axi_rlast; + input [0:0]m_axi_ruser; + input [0:0]m_axi_rvalid; + output [0:0]m_axi_rready; + + wire \ ; + wire aclk; + wire aresetn; + wire \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state[1]_i_1_n_0 ; + wire \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state[2]_i_1_n_0 ; + (* RTL_KEEP = "yes" *) wire \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[2] ; + (* RTL_KEEP = "yes" *) wire \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3] ; + wire \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i ; + (* RTL_KEEP = "yes" *) wire \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in ; + (* RTL_KEEP = "yes" *) wire \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in ; + wire \gen_master_slots[0].gen_mi_write.wdata_mux_w/m_aready__1 ; + (* RTL_KEEP = "yes" *) wire \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[2] ; + (* RTL_KEEP = "yes" *) wire \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3] ; + wire \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i ; + (* RTL_KEEP = "yes" *) wire \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in ; + (* RTL_KEEP = "yes" *) wire \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in ; + wire \gen_samd.crossbar_samd_n_1 ; + wire \gen_samd.crossbar_samd_n_131 ; + wire \gen_samd.crossbar_samd_n_132 ; + wire \gen_samd.crossbar_samd_n_192 ; + wire \gen_samd.crossbar_samd_n_193 ; + wire \gen_samd.crossbar_samd_n_194 ; + wire \gen_samd.crossbar_samd_n_195 ; + wire \gen_samd.crossbar_samd_n_3 ; + wire \gen_slave_slots[1].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1 ; + wire [31:0]m_axi_araddr; + wire [1:0]m_axi_arburst; + wire [3:0]m_axi_arcache; + wire [7:0]m_axi_arlen; + wire [0:0]m_axi_arlock; + wire [2:0]m_axi_arprot; + wire [3:0]m_axi_arqos; + wire [0:0]m_axi_arready; + wire [2:0]m_axi_arsize; + wire [0:0]m_axi_arvalid; + wire [31:0]m_axi_awaddr; + wire [1:0]m_axi_awburst; + wire [3:0]m_axi_awcache; + wire [0:0]m_axi_awid; + wire [7:0]m_axi_awlen; + wire [0:0]m_axi_awlock; + wire [2:0]m_axi_awprot; + wire [3:0]m_axi_awqos; + wire [0:0]m_axi_awready; + wire [2:0]m_axi_awsize; + wire [0:0]m_axi_awvalid; + wire [0:0]m_axi_bid; + wire [0:0]m_axi_bready; + wire [1:0]m_axi_bresp; + wire [0:0]m_axi_bvalid; + wire [63:0]m_axi_rdata; + wire [0:0]m_axi_rlast; + wire [0:0]m_axi_rready; + wire [1:0]m_axi_rresp; + wire [0:0]m_axi_rvalid; + wire [63:0]m_axi_wdata; + wire [0:0]m_axi_wlast; + wire [0:0]m_axi_wready; + wire [7:0]m_axi_wstrb; + wire [0:0]m_axi_wvalid; + wire [63:0]s_axi_araddr; + wire [3:0]s_axi_arburst; + wire [7:0]s_axi_arcache; + wire [15:0]s_axi_arlen; + wire [1:0]s_axi_arlock; + wire [5:0]s_axi_arprot; + wire [7:0]s_axi_arqos; + wire [0:0]\^s_axi_arready ; + wire [5:0]s_axi_arsize; + wire [1:0]s_axi_arvalid; + wire [63:0]s_axi_awaddr; + wire [3:0]s_axi_awburst; + wire [7:0]s_axi_awcache; + wire [15:0]s_axi_awlen; + wire [1:0]s_axi_awlock; + wire [5:0]s_axi_awprot; + wire [7:0]s_axi_awqos; + wire [1:1]\^s_axi_awready ; + wire [5:0]s_axi_awsize; + wire [1:0]s_axi_awvalid; + wire [1:0]s_axi_bready; + wire [3:2]\^s_axi_bresp ; + wire [1:1]\^s_axi_bvalid ; + wire [63:0]\^s_axi_rdata ; + wire [0:0]\^s_axi_rlast ; + wire [1:0]s_axi_rready; + wire [1:0]\^s_axi_rresp ; + wire [0:0]\^s_axi_rvalid ; + wire [127:0]s_axi_wdata; + wire [1:0]s_axi_wlast; + wire [1:1]\^s_axi_wready ; + wire [15:0]s_axi_wstrb; + wire [1:0]s_axi_wvalid; + + assign m_axi_arid[0] = \ ; + assign m_axi_arregion[3] = \ ; + assign m_axi_arregion[2] = \ ; + assign m_axi_arregion[1] = \ ; + assign m_axi_arregion[0] = \ ; + assign m_axi_aruser[0] = \ ; + assign m_axi_awregion[3] = \ ; + assign m_axi_awregion[2] = \ ; + assign m_axi_awregion[1] = \ ; + assign m_axi_awregion[0] = \ ; + assign m_axi_awuser[0] = \ ; + assign m_axi_wid[0] = \ ; + assign m_axi_wuser[0] = \ ; + assign s_axi_arready[1] = \ ; + assign s_axi_arready[0] = \^s_axi_arready [0]; + assign s_axi_awready[1] = \^s_axi_awready [1]; + assign s_axi_awready[0] = \ ; + assign s_axi_bid[1] = \ ; + assign s_axi_bid[0] = \ ; + assign s_axi_bresp[3:2] = \^s_axi_bresp [3:2]; + assign s_axi_bresp[1] = \ ; + assign s_axi_bresp[0] = \ ; + assign s_axi_buser[1] = \ ; + assign s_axi_buser[0] = \ ; + assign s_axi_bvalid[1] = \^s_axi_bvalid [1]; + assign s_axi_bvalid[0] = \ ; + assign s_axi_rdata[127] = \ ; + assign s_axi_rdata[126] = \ ; + assign s_axi_rdata[125] = \ ; + assign s_axi_rdata[124] = \ ; + assign s_axi_rdata[123] = \ ; + assign s_axi_rdata[122] = \ ; + assign s_axi_rdata[121] = \ ; + assign s_axi_rdata[120] = \ ; + assign s_axi_rdata[119] = \ ; + assign s_axi_rdata[118] = \ ; + assign s_axi_rdata[117] = \ ; + assign s_axi_rdata[116] = \ ; + assign s_axi_rdata[115] = \ ; + assign s_axi_rdata[114] = \ ; + assign s_axi_rdata[113] = \ ; + assign s_axi_rdata[112] = \ ; + assign s_axi_rdata[111] = \ ; + assign s_axi_rdata[110] = \ ; + assign s_axi_rdata[109] = \ ; + assign s_axi_rdata[108] = \ ; + assign s_axi_rdata[107] = \ ; + assign s_axi_rdata[106] = \ ; + assign s_axi_rdata[105] = \ ; + assign s_axi_rdata[104] = \ ; + assign s_axi_rdata[103] = \ ; + assign s_axi_rdata[102] = \ ; + assign s_axi_rdata[101] = \ ; + assign s_axi_rdata[100] = \ ; + assign s_axi_rdata[99] = \ ; + assign s_axi_rdata[98] = \ ; + assign s_axi_rdata[97] = \ ; + assign s_axi_rdata[96] = \ ; + assign s_axi_rdata[95] = \ ; + assign s_axi_rdata[94] = \ ; + assign s_axi_rdata[93] = \ ; + assign s_axi_rdata[92] = \ ; + assign s_axi_rdata[91] = \ ; + assign s_axi_rdata[90] = \ ; + assign s_axi_rdata[89] = \ ; + assign s_axi_rdata[88] = \ ; + assign s_axi_rdata[87] = \ ; + assign s_axi_rdata[86] = \ ; + assign s_axi_rdata[85] = \ ; + assign s_axi_rdata[84] = \ ; + assign s_axi_rdata[83] = \ ; + assign s_axi_rdata[82] = \ ; + assign s_axi_rdata[81] = \ ; + assign s_axi_rdata[80] = \ ; + assign s_axi_rdata[79] = \ ; + assign s_axi_rdata[78] = \ ; + assign s_axi_rdata[77] = \ ; + assign s_axi_rdata[76] = \ ; + assign s_axi_rdata[75] = \ ; + assign s_axi_rdata[74] = \ ; + assign s_axi_rdata[73] = \ ; + assign s_axi_rdata[72] = \ ; + assign s_axi_rdata[71] = \ ; + assign s_axi_rdata[70] = \ ; + assign s_axi_rdata[69] = \ ; + assign s_axi_rdata[68] = \ ; + assign s_axi_rdata[67] = \ ; + assign s_axi_rdata[66] = \ ; + assign s_axi_rdata[65] = \ ; + assign s_axi_rdata[64] = \ ; + assign s_axi_rdata[63:0] = \^s_axi_rdata [63:0]; + assign s_axi_rid[1] = \ ; + assign s_axi_rid[0] = \ ; + assign s_axi_rlast[1] = \ ; + assign s_axi_rlast[0] = \^s_axi_rlast [0]; + assign s_axi_rresp[3] = \ ; + assign s_axi_rresp[2] = \ ; + assign s_axi_rresp[1:0] = \^s_axi_rresp [1:0]; + assign s_axi_ruser[1] = \ ; + assign s_axi_ruser[0] = \ ; + assign s_axi_rvalid[1] = \ ; + assign s_axi_rvalid[0] = \^s_axi_rvalid [0]; + assign s_axi_wready[1] = \^s_axi_wready [1]; + assign s_axi_wready[0] = \ ; + GND GND + (.G(\ )); + LUT6 #( + .INIT(64'h0A0A0A0A4A0A0A0A)) + \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state[1]_i_1 + (.I0(\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in ), + .I1(\gen_master_slots[0].gen_mi_write.wdata_mux_w/m_aready__1 ), + .I2(\gen_samd.crossbar_samd_n_1 ), + .I3(\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3] ), + .I4(\gen_samd.crossbar_samd_n_3 ), + .I5(\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in ), + .O(\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'hA0A0A0A0B5F5F5F5)) + \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state[2]_i_1 + (.I0(\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in ), + .I1(\gen_master_slots[0].gen_mi_write.wdata_mux_w/m_aready__1 ), + .I2(\gen_samd.crossbar_samd_n_1 ), + .I3(\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3] ), + .I4(\gen_samd.crossbar_samd_n_3 ), + .I5(\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in ), + .O(\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state[2]_i_1_n_0 )); + (* KEEP = "yes" *) + FDSE #( + .INIT(1'b1)) + \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0] + (.C(aclk), + .CE(\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i ), + .D(\gen_samd.crossbar_samd_n_132 ), + .Q(\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in ), + .S(\gen_slave_slots[1].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1 )); + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1] + (.C(aclk), + .CE(\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i ), + .D(\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state[1]_i_1_n_0 ), + .Q(\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in ), + .R(\gen_slave_slots[1].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1 )); + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[2] + (.C(aclk), + .CE(\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i ), + .D(\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state[2]_i_1_n_0 ), + .Q(\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[2] ), + .R(\gen_slave_slots[1].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1 )); + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3] + (.C(aclk), + .CE(\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i ), + .D(\gen_samd.crossbar_samd_n_131 ), + .Q(\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3] ), + .R(\gen_slave_slots[1].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1 )); + (* KEEP = "yes" *) + FDSE #( + .INIT(1'b1)) + \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0] + (.C(aclk), + .CE(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i ), + .D(\gen_samd.crossbar_samd_n_195 ), + .Q(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in ), + .S(\gen_slave_slots[1].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1 )); + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1] + (.C(aclk), + .CE(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i ), + .D(\gen_samd.crossbar_samd_n_194 ), + .Q(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in ), + .R(\gen_slave_slots[1].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1 )); + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[2] + (.C(aclk), + .CE(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i ), + .D(\gen_samd.crossbar_samd_n_193 ), + .Q(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[2] ), + .R(\gen_slave_slots[1].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1 )); + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3] + (.C(aclk), + .CE(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i ), + .D(\gen_samd.crossbar_samd_n_192 ), + .Q(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3] ), + .R(\gen_slave_slots[1].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1 )); + Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_crossbar \gen_samd.crossbar_samd + (.D({\gen_samd.crossbar_samd_n_131 ,\gen_samd.crossbar_samd_n_132 }), + .E(\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i ), + .Q({m_axi_awqos,m_axi_awcache,m_axi_awburst,m_axi_awprot,m_axi_awlock,m_axi_awsize,m_axi_awlen,m_axi_awaddr,m_axi_awid}), + .aclk(aclk), + .areset_d1(\gen_slave_slots[1].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1 ), + .aresetn(aresetn), + .\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3] ({\gen_samd.crossbar_samd_n_192 ,\gen_samd.crossbar_samd_n_193 ,\gen_samd.crossbar_samd_n_194 ,\gen_samd.crossbar_samd_n_195 }), + .\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 ({\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3] ,\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in ,\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in }), + .m_aready__1(\gen_master_slots[0].gen_mi_write.wdata_mux_w/m_aready__1 ), + .\m_axi_arqos[3] ({m_axi_arqos,m_axi_arcache,m_axi_arburst,m_axi_arprot,m_axi_arlock,m_axi_arsize,m_axi_arlen,m_axi_araddr}), + .m_axi_arready(m_axi_arready), + .m_axi_arvalid(m_axi_arvalid), + .m_axi_awready(m_axi_awready), + .m_axi_awvalid(m_axi_awvalid), + .m_axi_bid(m_axi_bid), + .m_axi_bready(m_axi_bready), + .m_axi_bresp(m_axi_bresp), + .m_axi_bvalid(m_axi_bvalid), + .m_axi_rdata(m_axi_rdata), + .m_axi_rlast(m_axi_rlast), + .\m_axi_rready[0] (m_axi_rready), + .m_axi_rresp(m_axi_rresp), + .m_axi_rvalid(m_axi_rvalid), + .m_axi_wdata(m_axi_wdata), + .m_axi_wlast(m_axi_wlast), + .m_axi_wready(m_axi_wready), + .m_axi_wstrb(m_axi_wstrb), + .m_axi_wvalid(m_axi_wvalid), + .m_valid_i_reg(\gen_samd.crossbar_samd_n_1 ), + .m_valid_i_reg_0(\gen_samd.crossbar_samd_n_3 ), + .m_valid_i_reg_1(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i ), + .out({\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3] ,\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in ,\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in }), + .s_axi_araddr(s_axi_araddr[31:0]), + .\s_axi_arqos[3] ({s_axi_arqos[3:0],s_axi_arcache[3:0],s_axi_arburst[1:0],s_axi_arprot[2:0],s_axi_arlock[0],s_axi_arsize[2:0],s_axi_arlen[7:0]}), + .\s_axi_arready[0] (\^s_axi_arready ), + .s_axi_arvalid(s_axi_arvalid[0]), + .s_axi_awaddr(s_axi_awaddr[63:32]), + .s_axi_awburst(s_axi_awburst[3:2]), + .s_axi_awcache(s_axi_awcache[7:4]), + .s_axi_awlen(s_axi_awlen[15:8]), + .s_axi_awlock(s_axi_awlock[1]), + .s_axi_awprot(s_axi_awprot[5:3]), + .s_axi_awqos(s_axi_awqos[7:4]), + .s_axi_awready(\^s_axi_awready ), + .s_axi_awsize(s_axi_awsize[5:3]), + .s_axi_awvalid(s_axi_awvalid[1]), + .s_axi_bready(s_axi_bready[1]), + .s_axi_bresp(\^s_axi_bresp ), + .\s_axi_bvalid[1] (\^s_axi_bvalid ), + .s_axi_rdata(\^s_axi_rdata ), + .s_axi_rlast(\^s_axi_rlast ), + .s_axi_rready(s_axi_rready[0]), + .s_axi_rresp(\^s_axi_rresp ), + .s_axi_rvalid(\^s_axi_rvalid ), + .s_axi_wdata(s_axi_wdata[127:64]), + .s_axi_wlast(s_axi_wlast[1]), + .s_axi_wready(\^s_axi_wready ), + .s_axi_wstrb(s_axi_wstrb[15:8]), + .s_axi_wvalid(s_axi_wvalid[1])); +endmodule + +module Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_crossbar + (E, + m_valid_i_reg, + m_aready__1, + m_valid_i_reg_0, + m_axi_bready, + \m_axi_rready[0] , + m_valid_i_reg_1, + areset_d1, + \s_axi_arready[0] , + Q, + s_axi_rdata, + D, + \m_axi_arqos[3] , + s_axi_awready, + \s_axi_bvalid[1] , + \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3] , + s_axi_rlast, + s_axi_rvalid, + s_axi_wready, + m_axi_wvalid, + m_axi_awvalid, + s_axi_rresp, + s_axi_bresp, + m_axi_wstrb, + m_axi_wdata, + m_axi_wlast, + m_axi_arvalid, + aclk, + out, + \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 , + aresetn, + m_axi_arready, + s_axi_bready, + s_axi_rready, + s_axi_araddr, + m_axi_bvalid, + s_axi_awvalid, + m_axi_rvalid, + \s_axi_arqos[3] , + m_axi_bid, + m_axi_bresp, + m_axi_rlast, + m_axi_rresp, + m_axi_rdata, + m_axi_awready, + s_axi_wlast, + s_axi_awaddr, + s_axi_arvalid, + s_axi_wvalid, + m_axi_wready, + s_axi_awqos, + s_axi_awcache, + s_axi_awburst, + s_axi_awprot, + s_axi_awlock, + s_axi_awsize, + s_axi_awlen, + s_axi_wstrb, + s_axi_wdata); + output [0:0]E; + output m_valid_i_reg; + output m_aready__1; + output m_valid_i_reg_0; + output [0:0]m_axi_bready; + output \m_axi_rready[0] ; + output [0:0]m_valid_i_reg_1; + output areset_d1; + output \s_axi_arready[0] ; + output [57:0]Q; + output [63:0]s_axi_rdata; + output [1:0]D; + output [56:0]\m_axi_arqos[3] ; + output [0:0]s_axi_awready; + output \s_axi_bvalid[1] ; + output [3:0]\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3] ; + output [0:0]s_axi_rlast; + output [0:0]s_axi_rvalid; + output [0:0]s_axi_wready; + output [0:0]m_axi_wvalid; + output [0:0]m_axi_awvalid; + output [1:0]s_axi_rresp; + output [1:0]s_axi_bresp; + output [7:0]m_axi_wstrb; + output [63:0]m_axi_wdata; + output [0:0]m_axi_wlast; + output [0:0]m_axi_arvalid; + input aclk; + input [2:0]out; + input [2:0]\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 ; + input aresetn; + input [0:0]m_axi_arready; + input [0:0]s_axi_bready; + input [0:0]s_axi_rready; + input [31:0]s_axi_araddr; + input [0:0]m_axi_bvalid; + input [0:0]s_axi_awvalid; + input [0:0]m_axi_rvalid; + input [24:0]\s_axi_arqos[3] ; + input [0:0]m_axi_bid; + input [1:0]m_axi_bresp; + input [0:0]m_axi_rlast; + input [1:0]m_axi_rresp; + input [63:0]m_axi_rdata; + input [0:0]m_axi_awready; + input [0:0]s_axi_wlast; + input [31:0]s_axi_awaddr; + input [0:0]s_axi_arvalid; + input [0:0]s_axi_wvalid; + input [0:0]m_axi_wready; + input [3:0]s_axi_awqos; + input [3:0]s_axi_awcache; + input [1:0]s_axi_awburst; + input [2:0]s_axi_awprot; + input [0:0]s_axi_awlock; + input [2:0]s_axi_awsize; + input [7:0]s_axi_awlen; + input [7:0]s_axi_wstrb; + input [63:0]s_axi_wdata; + + wire [1:0]D; + wire [0:0]E; + wire [57:0]Q; + wire [1:1]aa_mi_artarget_hot; + wire aa_mi_arvalid; + wire [1:0]aa_mi_awtarget_hot; + wire aa_sa_awready; + wire aa_sa_awvalid; + wire aa_wm_awgrant_enc; + wire aclk; + wire active_target_enc; + wire active_target_enc_3; + wire [0:0]active_target_hot; + wire [0:0]active_target_hot_2; + wire addr_arbiter_ar_n_10; + wire addr_arbiter_ar_n_3; + wire addr_arbiter_ar_n_4; + wire addr_arbiter_ar_n_5; + wire addr_arbiter_ar_n_6; + wire addr_arbiter_ar_n_8; + wire addr_arbiter_ar_n_9; + wire addr_arbiter_aw_n_11; + wire addr_arbiter_aw_n_12; + wire addr_arbiter_aw_n_13; + wire addr_arbiter_aw_n_14; + wire addr_arbiter_aw_n_15; + wire addr_arbiter_aw_n_17; + wire addr_arbiter_aw_n_19; + wire addr_arbiter_aw_n_4; + wire addr_arbiter_aw_n_8; + wire addr_arbiter_aw_n_9; + wire areset_d1; + wire aresetn; + wire aresetn_d; + wire \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ; + wire \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_0 ; + wire \gen_master_slots[0].gen_mi_write.wdata_mux_w_n_5 ; + wire \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0 ; + wire \gen_master_slots[0].reg_slice_mi_n_1 ; + wire \gen_master_slots[0].reg_slice_mi_n_6 ; + wire \gen_master_slots[0].reg_slice_mi_n_75 ; + wire \gen_master_slots[0].reg_slice_mi_n_76 ; + wire \gen_master_slots[0].reg_slice_mi_n_77 ; + wire \gen_master_slots[0].reg_slice_mi_n_78 ; + wire \gen_master_slots[0].reg_slice_mi_n_79 ; + wire \gen_master_slots[0].reg_slice_mi_n_80 ; + wire \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0 ; + wire [3:0]\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3] ; + wire [2:0]\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 ; + wire \gen_master_slots[1].gen_mi_write.wdata_mux_w_n_5 ; + wire \gen_master_slots[1].reg_slice_mi_n_10 ; + wire \gen_master_slots[1].reg_slice_mi_n_3 ; + wire \gen_master_slots[1].reg_slice_mi_n_4 ; + wire \gen_master_slots[1].reg_slice_mi_n_8 ; + wire \gen_slave_slots[1].gen_si_write.splitter_aw_si_n_0 ; + wire \gen_slave_slots[1].gen_si_write.splitter_aw_si_n_3 ; + wire \gen_slave_slots[1].gen_si_write.splitter_aw_si_n_5 ; + wire \gen_slave_slots[1].gen_si_write.splitter_aw_si_n_6 ; + wire \gen_slave_slots[1].gen_si_write.wdata_router_w_n_4 ; + wire \gen_slave_slots[1].gen_si_write.wdata_router_w_n_5 ; + wire m_aready__1; + wire m_avalid; + wire m_avalid_5; + wire [56:0]\m_axi_arqos[3] ; + wire [0:0]m_axi_arready; + wire [0:0]m_axi_arvalid; + wire [0:0]m_axi_awready; + wire [0:0]m_axi_awvalid; + wire [0:0]m_axi_bid; + wire [0:0]m_axi_bready; + wire [1:0]m_axi_bresp; + wire [0:0]m_axi_bvalid; + wire [63:0]m_axi_rdata; + wire [0:0]m_axi_rlast; + wire \m_axi_rready[0] ; + wire [1:0]m_axi_rresp; + wire [0:0]m_axi_rvalid; + wire [63:0]m_axi_wdata; + wire [0:0]m_axi_wlast; + wire [0:0]m_axi_wready; + wire [7:0]m_axi_wstrb; + wire [0:0]m_axi_wvalid; + wire [1:0]m_ready_d; + wire [1:0]m_ready_d_6; + wire m_select_enc; + wire m_select_enc_4; + wire m_valid_i_reg; + wire m_valid_i_reg_0; + wire [0:0]m_valid_i_reg_1; + wire [1:1]mi_arready; + wire [1:1]mi_awready; + wire mi_bready_1; + wire mi_rready_1; + wire [2:0]out; + wire p_10_in; + wire p_11_in; + wire p_13_in; + wire p_17_in; + wire p_1_in; + wire p_20_in; + wire p_28_out; + wire p_30_out; + wire p_52_out; + wire p_54_out; + wire p_58_out; + wire p_61_out; + wire [8:0]r_issuing_cnt; + wire \r_pipe/p_1_in ; + wire \r_pipe/p_1_in_1 ; + wire reset; + wire [31:0]s_axi_araddr; + wire [24:0]\s_axi_arqos[3] ; + wire \s_axi_arready[0] ; + wire [0:0]s_axi_arvalid; + wire [31:0]s_axi_awaddr; + wire [1:0]s_axi_awburst; + wire [3:0]s_axi_awcache; + wire [7:0]s_axi_awlen; + wire [0:0]s_axi_awlock; + wire [2:0]s_axi_awprot; + wire [3:0]s_axi_awqos; + wire [0:0]s_axi_awready; + wire [2:0]s_axi_awsize; + wire [0:0]s_axi_awvalid; + wire [0:0]s_axi_bready; + wire [1:0]s_axi_bresp; + wire \s_axi_bvalid[1] ; + wire [63:0]s_axi_rdata; + wire [0:0]s_axi_rlast; + wire [0:0]s_axi_rready; + wire [1:0]s_axi_rresp; + wire [0:0]s_axi_rvalid; + wire [63:0]s_axi_wdata; + wire [0:0]s_axi_wlast; + wire [0:0]s_axi_wready; + wire [7:0]s_axi_wstrb; + wire [0:0]s_axi_wvalid; + wire [1:1]sa_wm_awvalid; + wire splitter_aw_mi_n_1; + wire [1:1]ss_aa_awready; + wire [1:1]ss_wr_awready; + wire [0:0]st_aa_arvalid_qual; + wire [1:1]st_aa_awvalid_qual; + wire [1:0]st_mr_rmesg; + wire valid_qual_i111_in; + wire valid_qual_i1__0; + wire [8:0]w_issuing_cnt; + wire write_cs0__0; + + Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_addr_arbiter addr_arbiter_ar + (.D({\s_axi_arqos[3] ,s_axi_araddr}), + .E(addr_arbiter_ar_n_8), + .Q(aa_mi_artarget_hot), + .SR(reset), + .aa_mi_arvalid(aa_mi_arvalid), + .aclk(aclk), + .active_target_enc(active_target_enc), + .active_target_hot(active_target_hot), + .aresetn_d(aresetn_d), + .\gen_arbiter.m_target_hot_i_reg[0]_0 (\gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ), + .\gen_arbiter.qual_reg_reg[0]_0 (addr_arbiter_ar_n_9), + .\gen_axi.s_axi_rlast_i_reg (addr_arbiter_ar_n_10), + .\gen_master_slots[0].r_issuing_cnt_reg[0] (addr_arbiter_ar_n_5), + .\gen_master_slots[0].r_issuing_cnt_reg[3] (\gen_master_slots[1].reg_slice_mi_n_8 ), + .\gen_master_slots[0].r_issuing_cnt_reg[3]_0 (r_issuing_cnt[3:0]), + .\gen_master_slots[1].r_issuing_cnt_reg[8] (addr_arbiter_ar_n_6), + .\gen_single_thread.active_target_enc_reg[0] (addr_arbiter_ar_n_4), + .\gen_single_thread.active_target_hot_reg[0] (addr_arbiter_ar_n_3), + .\m_axi_arqos[3] (\m_axi_arqos[3] ), + .m_axi_arready(m_axi_arready), + .m_axi_arvalid(m_axi_arvalid), + .m_valid_i_reg(\gen_master_slots[0].reg_slice_mi_n_80 ), + .mi_arready(mi_arready), + .p_11_in(p_11_in), + .\s_axi_arready[0] (\s_axi_arready[0] ), + .s_axi_arvalid(s_axi_arvalid), + .st_aa_arvalid_qual(st_aa_arvalid_qual), + .valid_qual_i1__0(valid_qual_i1__0)); + Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_addr_arbiter_0 addr_arbiter_aw + (.D({addr_arbiter_aw_n_12,addr_arbiter_aw_n_13,addr_arbiter_aw_n_14}), + .E(addr_arbiter_aw_n_11), + .Q(aa_mi_awtarget_hot), + .SR(reset), + .aa_sa_awready(aa_sa_awready), + .aa_sa_awvalid(aa_sa_awvalid), + .aa_wm_awgrant_enc(aa_wm_awgrant_enc), + .aclk(aclk), + .aresetn_d(aresetn_d), + .\gen_arbiter.m_valid_i_reg_0 (splitter_aw_mi_n_1), + .\gen_arbiter.qual_reg_reg[1]_0 (addr_arbiter_aw_n_15), + .\gen_master_slots[0].w_issuing_cnt_reg[3] (w_issuing_cnt[3:0]), + .\gen_master_slots[1].w_issuing_cnt_reg[8] (addr_arbiter_aw_n_8), + .\gen_single_thread.active_target_hot_reg[0] (\gen_master_slots[0].reg_slice_mi_n_75 ), + .\m_axi_awqos[3] (Q), + .m_axi_awready(m_axi_awready), + .m_axi_awvalid(m_axi_awvalid), + .m_ready_d(m_ready_d_6), + .m_ready_d_0(m_ready_d[0]), + .\m_ready_d_reg[0] (\gen_slave_slots[1].gen_si_write.splitter_aw_si_n_5 ), + .\m_ready_d_reg[1] (addr_arbiter_aw_n_9), + .\m_ready_d_reg[1]_0 (addr_arbiter_aw_n_19), + .m_valid_i_reg(m_valid_i_reg), + .mi_awready(mi_awready), + .out(out[1:0]), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awburst(s_axi_awburst), + .s_axi_awcache(s_axi_awcache), + .s_axi_awlen(s_axi_awlen), + .s_axi_awlock(s_axi_awlock), + .s_axi_awprot(s_axi_awprot), + .s_axi_awqos(s_axi_awqos), + .s_axi_awsize(s_axi_awsize), + .s_axi_awvalid(s_axi_awvalid), + .sa_wm_awvalid(sa_wm_awvalid), + .sel_4(\gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_0 ), + .ss_aa_awready(ss_aa_awready), + .st_aa_awvalid_qual(st_aa_awvalid_qual), + .\storage_data1_reg[0] (addr_arbiter_aw_n_4), + .\storage_data1_reg[0]_0 (addr_arbiter_aw_n_17), + .valid_qual_i111_in(valid_qual_i111_in)); + FDRE #( + .INIT(1'b0)) + aresetn_d_reg + (.C(aclk), + .CE(1'b1), + .D(aresetn), + .Q(aresetn_d), + .R(1'b0)); + Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_decerr_slave \gen_decerr_slave.decerr_slave_inst + (.Q(Q[0]), + .SR(reset), + .aa_mi_arvalid(aa_mi_arvalid), + .aclk(aclk), + .aresetn_d(aresetn_d), + .\gen_arbiter.m_mesg_i_reg[40] (\m_axi_arqos[3] [39:32]), + .\gen_arbiter.m_target_hot_i_reg[1] (aa_mi_artarget_hot), + .\gen_axi.read_cs_reg[0]_0 (addr_arbiter_ar_n_10), + .\gen_axi.s_axi_awready_i_reg_0 (addr_arbiter_aw_n_8), + .mi_arready(mi_arready), + .mi_awready(mi_awready), + .mi_bready_1(mi_bready_1), + .mi_rready_1(mi_rready_1), + .p_10_in(p_10_in), + .p_11_in(p_11_in), + .p_13_in(p_13_in), + .p_17_in(p_17_in), + .p_20_in(p_20_in), + .write_cs0__0(write_cs0__0)); + Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_wdata_mux \gen_master_slots[0].gen_mi_write.wdata_mux_w + (.D(D), + .E(E), + .Q(aa_mi_awtarget_hot[0]), + .SR(reset), + .aa_sa_awvalid(aa_sa_awvalid), + .aa_wm_awgrant_enc(aa_wm_awgrant_enc), + .aclk(aclk), + .\gen_arbiter.m_valid_i_reg (m_valid_i_reg), + .\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0] (addr_arbiter_aw_n_4), + .\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1] (addr_arbiter_aw_n_17), + .in1(areset_d1), + .m_avalid(m_avalid_5), + .m_axi_wdata(m_axi_wdata), + .m_axi_wlast(m_axi_wlast), + .m_axi_wready(m_axi_wready), + .m_axi_wstrb(m_axi_wstrb), + .m_axi_wvalid(m_axi_wvalid), + .m_ready_d(m_ready_d_6[0]), + .m_select_enc(m_select_enc_4), + .m_valid_i_reg(m_valid_i_reg_0), + .m_valid_i_reg_0(\gen_slave_slots[1].gen_si_write.wdata_router_w_n_4 ), + .out(out), + .s_axi_wdata(s_axi_wdata), + .s_axi_wlast(s_axi_wlast), + .s_axi_wstrb(s_axi_wstrb), + .s_axi_wvalid(s_axi_wvalid), + .s_ready_i_reg(\gen_master_slots[0].gen_mi_write.wdata_mux_w_n_5 ), + .\storage_data1_reg[0] (m_aready__1)); + LUT1 #( + .INIT(2'h1)) + \gen_master_slots[0].r_issuing_cnt[0]_i_1 + (.I0(r_issuing_cnt[0]), + .O(\gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0 )); + FDRE \gen_master_slots[0].r_issuing_cnt_reg[0] + (.C(aclk), + .CE(addr_arbiter_ar_n_8), + .D(\gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0 ), + .Q(r_issuing_cnt[0]), + .R(reset)); + FDRE \gen_master_slots[0].r_issuing_cnt_reg[1] + (.C(aclk), + .CE(addr_arbiter_ar_n_8), + .D(\gen_master_slots[0].reg_slice_mi_n_79 ), + .Q(r_issuing_cnt[1]), + .R(reset)); + FDRE \gen_master_slots[0].r_issuing_cnt_reg[2] + (.C(aclk), + .CE(addr_arbiter_ar_n_8), + .D(\gen_master_slots[0].reg_slice_mi_n_78 ), + .Q(r_issuing_cnt[2]), + .R(reset)); + FDRE \gen_master_slots[0].r_issuing_cnt_reg[3] + (.C(aclk), + .CE(addr_arbiter_ar_n_8), + .D(\gen_master_slots[0].reg_slice_mi_n_77 ), + .Q(r_issuing_cnt[3]), + .R(reset)); + Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axi_register_slice \gen_master_slots[0].reg_slice_mi + (.D({\gen_master_slots[0].reg_slice_mi_n_77 ,\gen_master_slots[0].reg_slice_mi_n_78 ,\gen_master_slots[0].reg_slice_mi_n_79 }), + .E(\r_pipe/p_1_in_1 ), + .Q({p_54_out,st_mr_rmesg}), + .aclk(aclk), + .active_target_enc(active_target_enc), + .active_target_enc_1(active_target_enc_3), + .active_target_hot(active_target_hot_2), + .active_target_hot_0(active_target_hot), + .aresetn(aresetn), + .\gen_arbiter.m_valid_i_reg (addr_arbiter_ar_n_5), + .\gen_arbiter.qual_reg_reg[0] (\gen_master_slots[0].reg_slice_mi_n_76 ), + .\gen_master_slots[0].r_issuing_cnt_reg[0] (\gen_master_slots[0].reg_slice_mi_n_80 ), + .\gen_master_slots[0].r_issuing_cnt_reg[3] (r_issuing_cnt[3:0]), + .\gen_master_slots[0].w_issuing_cnt_reg[0] (\gen_master_slots[0].reg_slice_mi_n_75 ), + .m_axi_bid(m_axi_bid), + .m_axi_bready(m_axi_bready), + .m_axi_bresp(m_axi_bresp), + .m_axi_bvalid(m_axi_bvalid), + .m_axi_rdata(m_axi_rdata), + .m_axi_rlast(m_axi_rlast), + .\m_axi_rready[0] (\m_axi_rready[0] ), + .m_axi_rresp(m_axi_rresp), + .m_axi_rvalid(m_axi_rvalid), + .m_valid_i_reg(\gen_master_slots[0].reg_slice_mi_n_1 ), + .p_1_in(p_1_in), + .p_30_out(p_30_out), + .p_52_out(p_52_out), + .p_58_out(p_58_out), + .p_61_out(p_61_out), + .s_axi_bready(s_axi_bready), + .s_axi_bresp(s_axi_bresp), + .s_axi_rdata(s_axi_rdata), + .s_axi_rready(s_axi_rready), + .s_ready_i_reg(\gen_master_slots[0].reg_slice_mi_n_6 )); + LUT1 #( + .INIT(2'h1)) + \gen_master_slots[0].w_issuing_cnt[0]_i_1 + (.I0(w_issuing_cnt[0]), + .O(\gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0 )); + FDRE \gen_master_slots[0].w_issuing_cnt_reg[0] + (.C(aclk), + .CE(addr_arbiter_aw_n_11), + .D(\gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0 ), + .Q(w_issuing_cnt[0]), + .R(reset)); + FDRE \gen_master_slots[0].w_issuing_cnt_reg[1] + (.C(aclk), + .CE(addr_arbiter_aw_n_11), + .D(addr_arbiter_aw_n_14), + .Q(w_issuing_cnt[1]), + .R(reset)); + FDRE \gen_master_slots[0].w_issuing_cnt_reg[2] + (.C(aclk), + .CE(addr_arbiter_aw_n_11), + .D(addr_arbiter_aw_n_13), + .Q(w_issuing_cnt[2]), + .R(reset)); + FDRE \gen_master_slots[0].w_issuing_cnt_reg[3] + (.C(aclk), + .CE(addr_arbiter_aw_n_11), + .D(addr_arbiter_aw_n_12), + .Q(w_issuing_cnt[3]), + .R(reset)); + Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_wdata_mux__parameterized0 \gen_master_slots[1].gen_mi_write.wdata_mux_w + (.Q(aa_mi_awtarget_hot[1]), + .SR(reset), + .aa_sa_awvalid(aa_sa_awvalid), + .aa_wm_awgrant_enc(aa_wm_awgrant_enc), + .aclk(aclk), + .\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3] (\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3] ), + .\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 (\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 ), + .in1(areset_d1), + .m_avalid(m_avalid), + .m_avalid_1(m_avalid_5), + .m_ready_d(m_ready_d_6[0]), + .m_select_enc(m_select_enc), + .m_select_enc_0(m_select_enc_4), + .m_valid_i_reg(m_valid_i_reg_1), + .p_10_in(p_10_in), + .s_axi_wlast(s_axi_wlast), + .s_axi_wready(s_axi_wready), + .s_axi_wvalid(s_axi_wvalid), + .s_ready_i_reg(\gen_master_slots[1].gen_mi_write.wdata_mux_w_n_5 ), + .sa_wm_awvalid(sa_wm_awvalid), + .\storage_data1_reg[0] (\gen_slave_slots[1].gen_si_write.wdata_router_w_n_5 ), + .\storage_data1_reg[0]_0 (\gen_master_slots[0].gen_mi_write.wdata_mux_w_n_5 ), + .write_cs0__0(write_cs0__0)); + FDRE \gen_master_slots[1].r_issuing_cnt_reg[8] + (.C(aclk), + .CE(1'b1), + .D(\gen_master_slots[1].reg_slice_mi_n_4 ), + .Q(r_issuing_cnt[8]), + .R(reset)); + Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axi_register_slice_1 \gen_master_slots[1].reg_slice_mi + (.Q({p_54_out,st_mr_rmesg}), + .aclk(aclk), + .active_target_enc(active_target_enc_3), + .active_target_enc_0(active_target_enc), + .active_target_hot(active_target_hot_2), + .\aresetn_d_reg[1] (\gen_master_slots[0].reg_slice_mi_n_1 ), + .\aresetn_d_reg[1]_0 (\gen_master_slots[0].reg_slice_mi_n_6 ), + .\gen_arbiter.m_valid_i_reg (addr_arbiter_ar_n_6), + .\gen_arbiter.qual_reg_reg[0] (\gen_master_slots[1].reg_slice_mi_n_8 ), + .\gen_arbiter.qual_reg_reg[0]_0 (\gen_master_slots[1].reg_slice_mi_n_10 ), + .\gen_axi.s_axi_awready_i_reg (addr_arbiter_aw_n_8), + .\gen_master_slots[0].r_issuing_cnt_reg[2] (addr_arbiter_ar_n_9), + .\gen_master_slots[0].w_issuing_cnt_reg[2] (addr_arbiter_aw_n_15), + .\gen_master_slots[1].r_issuing_cnt_reg[8] (\gen_master_slots[1].reg_slice_mi_n_4 ), + .\gen_master_slots[1].w_issuing_cnt_reg[8] (\gen_master_slots[1].reg_slice_mi_n_3 ), + .\gen_single_thread.active_target_hot_reg[0] (\gen_master_slots[0].reg_slice_mi_n_75 ), + .m_valid_i_reg(\gen_master_slots[0].reg_slice_mi_n_80 ), + .mi_bready_1(mi_bready_1), + .mi_rready_1(mi_rready_1), + .p_11_in(p_11_in), + .p_13_in(p_13_in), + .p_17_in(p_17_in), + .p_1_in(p_1_in), + .p_1_in_1(\r_pipe/p_1_in ), + .p_20_in(p_20_in), + .p_28_out(p_28_out), + .p_30_out(p_30_out), + .p_58_out(p_58_out), + .p_61_out(p_61_out), + .r_issuing_cnt({r_issuing_cnt[8],r_issuing_cnt[3]}), + .\s_axi_araddr[29] (\gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_bready(s_axi_bready), + .\s_axi_bvalid[1] (\s_axi_bvalid[1] ), + .s_axi_rlast(s_axi_rlast), + .s_axi_rready(s_axi_rready), + .s_axi_rresp(s_axi_rresp), + .sel_4(\gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_0 ), + .st_aa_arvalid_qual(st_aa_arvalid_qual), + .valid_qual_i111_in(valid_qual_i111_in), + .valid_qual_i1__0(valid_qual_i1__0), + .w_issuing_cnt({w_issuing_cnt[8],w_issuing_cnt[3]})); + FDRE \gen_master_slots[1].w_issuing_cnt_reg[8] + (.C(aclk), + .CE(1'b1), + .D(\gen_master_slots[1].reg_slice_mi_n_3 ), + .Q(w_issuing_cnt[8]), + .R(reset)); + Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_si_transactor \gen_slave_slots[0].gen_si_read.si_transactor_ar + (.E(\r_pipe/p_1_in_1 ), + .Q(p_54_out), + .SR(reset), + .aclk(aclk), + .active_target_enc(active_target_enc), + .active_target_hot(active_target_hot), + .\gen_arbiter.s_ready_i_reg[0] (addr_arbiter_ar_n_4), + .\gen_arbiter.s_ready_i_reg[0]_0 (addr_arbiter_ar_n_3), + .\gen_arbiter.s_ready_i_reg[0]_1 (\s_axi_arready[0] ), + .\m_payload_i_reg[66] (\gen_master_slots[0].reg_slice_mi_n_76 ), + .m_valid_i_reg(\gen_master_slots[1].reg_slice_mi_n_10 ), + .p_1_in(\r_pipe/p_1_in ), + .p_28_out(p_28_out), + .p_30_out(p_30_out), + .p_52_out(p_52_out), + .\s_axi_araddr[29] (\gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ), + .s_axi_rready(s_axi_rready), + .s_axi_rvalid(s_axi_rvalid), + .st_aa_arvalid_qual(st_aa_arvalid_qual)); + Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_si_transactor__parameterized0 \gen_slave_slots[1].gen_si_write.si_transactor_aw + (.SR(reset), + .aclk(aclk), + .active_target_enc(active_target_enc_3), + .active_target_hot(active_target_hot_2), + .\m_payload_i_reg[2] (\s_axi_bvalid[1] ), + .s_axi_awready(s_axi_awready), + .s_axi_bready(s_axi_bready), + .s_ready_i_reg(\gen_slave_slots[1].gen_si_write.splitter_aw_si_n_3 ), + .s_ready_i_reg_0(\gen_slave_slots[1].gen_si_write.splitter_aw_si_n_0 ), + .sel_4(\gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_0 ), + .st_aa_awvalid_qual(st_aa_awvalid_qual)); + Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_splitter \gen_slave_slots[1].gen_si_write.splitter_aw_si + (.aclk(aclk), + .active_target_enc(active_target_enc_3), + .active_target_hot(active_target_hot_2), + .aresetn_d(aresetn_d), + .\gen_arbiter.qual_reg_reg[1] (\gen_slave_slots[1].gen_si_write.splitter_aw_si_n_5 ), + .\gen_rep[0].fifoaddr_reg[0] (\gen_slave_slots[1].gen_si_write.splitter_aw_si_n_6 ), + .\gen_single_thread.active_target_enc_reg[0] (\gen_slave_slots[1].gen_si_write.splitter_aw_si_n_3 ), + .\gen_single_thread.active_target_hot_reg[0] (\gen_slave_slots[1].gen_si_write.splitter_aw_si_n_0 ), + .m_ready_d(m_ready_d), + .s_axi_awready(s_axi_awready), + .s_axi_awvalid(s_axi_awvalid), + .sel_4(\gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_0 ), + .ss_aa_awready(ss_aa_awready), + .ss_wr_awready(ss_wr_awready), + .st_aa_awvalid_qual(st_aa_awvalid_qual), + .valid_qual_i111_in(valid_qual_i111_in)); + Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_wdata_router \gen_slave_slots[1].gen_si_write.wdata_router_w + (.SR(reset), + .SS(areset_d1), + .aclk(aclk), + .\gen_rep[0].fifoaddr_reg[0] (\gen_slave_slots[1].gen_si_write.wdata_router_w_n_5 ), + .m_avalid(m_avalid_5), + .m_avalid_1(m_avalid), + .m_ready_d(m_ready_d[1]), + .\m_ready_d_reg[1] (\gen_slave_slots[1].gen_si_write.splitter_aw_si_n_6 ), + .m_select_enc(m_select_enc_4), + .m_select_enc_0(m_select_enc), + .m_valid_i_reg(\gen_master_slots[1].gen_mi_write.wdata_mux_w_n_5 ), + .p_10_in(p_10_in), + .s_axi_awaddr(s_axi_awaddr[31:29]), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_wlast(s_axi_wlast), + .s_axi_wvalid(s_axi_wvalid), + .s_ready_i_reg(\gen_slave_slots[1].gen_si_write.wdata_router_w_n_4 ), + .ss_wr_awready(ss_wr_awready), + .\storage_data1_reg[0] (\gen_master_slots[0].gen_mi_write.wdata_mux_w_n_5 )); + Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_splitter_2 splitter_aw_mi + (.Q(aa_mi_awtarget_hot), + .aa_sa_awready(aa_sa_awready), + .aa_sa_awvalid(aa_sa_awvalid), + .aclk(aclk), + .aresetn_d(aresetn_d), + .\gen_arbiter.any_grant_reg (splitter_aw_mi_n_1), + .\gen_arbiter.m_target_hot_i_reg[0] (addr_arbiter_aw_n_19), + .\gen_arbiter.m_target_hot_i_reg[1] (addr_arbiter_aw_n_9), + .m_axi_awready(m_axi_awready), + .m_ready_d(m_ready_d_6), + .mi_awready(mi_awready)); +endmodule + +module Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_decerr_slave + (mi_awready, + p_10_in, + p_20_in, + p_17_in, + p_11_in, + p_13_in, + mi_arready, + SR, + aclk, + \gen_axi.s_axi_awready_i_reg_0 , + mi_bready_1, + write_cs0__0, + Q, + mi_rready_1, + aa_mi_arvalid, + \gen_arbiter.m_target_hot_i_reg[1] , + \gen_axi.read_cs_reg[0]_0 , + \gen_arbiter.m_mesg_i_reg[40] , + aresetn_d); + output [0:0]mi_awready; + output p_10_in; + output p_20_in; + output p_17_in; + output p_11_in; + output p_13_in; + output [0:0]mi_arready; + input [0:0]SR; + input aclk; + input \gen_axi.s_axi_awready_i_reg_0 ; + input mi_bready_1; + input write_cs0__0; + input [0:0]Q; + input mi_rready_1; + input aa_mi_arvalid; + input [0:0]\gen_arbiter.m_target_hot_i_reg[1] ; + input \gen_axi.read_cs_reg[0]_0 ; + input [7:0]\gen_arbiter.m_mesg_i_reg[40] ; + input aresetn_d; + + wire [0:0]Q; + wire [0:0]SR; + wire aa_mi_arvalid; + wire aclk; + wire aresetn_d; + wire [7:0]\gen_arbiter.m_mesg_i_reg[40] ; + wire [0:0]\gen_arbiter.m_target_hot_i_reg[1] ; + wire \gen_axi.read_cnt[4]_i_2_n_0 ; + wire \gen_axi.read_cnt[5]_i_2_n_0 ; + wire \gen_axi.read_cnt[7]_i_1_n_0 ; + wire \gen_axi.read_cnt[7]_i_3_n_0 ; + wire [7:1]\gen_axi.read_cnt_reg__0 ; + wire [0:0]\gen_axi.read_cnt_reg__0__0 ; + wire \gen_axi.read_cs[0]_i_1_n_0 ; + wire \gen_axi.read_cs_reg[0]_0 ; + wire \gen_axi.s_axi_arready_i_i_1_n_0 ; + wire \gen_axi.s_axi_arready_i_i_2_n_0 ; + wire \gen_axi.s_axi_awready_i_i_1_n_0 ; + wire \gen_axi.s_axi_awready_i_reg_0 ; + wire \gen_axi.s_axi_bid_i[0]_i_1_n_0 ; + wire \gen_axi.s_axi_bvalid_i_i_1_n_0 ; + wire \gen_axi.s_axi_rlast_i_i_1_n_0 ; + wire \gen_axi.s_axi_rlast_i_i_3_n_0 ; + wire \gen_axi.s_axi_rlast_i_i_5_n_0 ; + wire \gen_axi.s_axi_wready_i_i_1_n_0 ; + wire \gen_axi.write_cs[0]_i_1_n_0 ; + wire \gen_axi.write_cs[1]_i_1_n_0 ; + wire [0:0]mi_arready; + wire [0:0]mi_awready; + wire mi_bready_1; + wire mi_rready_1; + wire [7:0]p_0_in; + wire p_10_in; + wire p_11_in; + wire p_13_in; + wire p_17_in; + wire p_20_in; + wire s_axi_rid_i; + wire [1:0]write_cs; + wire write_cs0__0; + + (* SOFT_HLUTNM = "soft_lutpair47" *) + LUT3 #( + .INIT(8'h74)) + \gen_axi.read_cnt[0]_i_1 + (.I0(\gen_axi.read_cnt_reg__0__0 ), + .I1(p_11_in), + .I2(\gen_arbiter.m_mesg_i_reg[40] [0]), + .O(p_0_in[0])); + (* SOFT_HLUTNM = "soft_lutpair47" *) + LUT4 #( + .INIT(16'hE22E)) + \gen_axi.read_cnt[1]_i_1 + (.I0(\gen_arbiter.m_mesg_i_reg[40] [1]), + .I1(p_11_in), + .I2(\gen_axi.read_cnt_reg__0__0 ), + .I3(\gen_axi.read_cnt_reg__0 [1]), + .O(p_0_in[1])); + LUT5 #( + .INIT(32'hFC03AAAA)) + \gen_axi.read_cnt[2]_i_1 + (.I0(\gen_arbiter.m_mesg_i_reg[40] [2]), + .I1(\gen_axi.read_cnt_reg__0__0 ), + .I2(\gen_axi.read_cnt_reg__0 [1]), + .I3(\gen_axi.read_cnt_reg__0 [2]), + .I4(p_11_in), + .O(p_0_in[2])); + LUT6 #( + .INIT(64'hFFFC0003AAAAAAAA)) + \gen_axi.read_cnt[3]_i_1 + (.I0(\gen_arbiter.m_mesg_i_reg[40] [3]), + .I1(\gen_axi.read_cnt_reg__0 [2]), + .I2(\gen_axi.read_cnt_reg__0 [1]), + .I3(\gen_axi.read_cnt_reg__0__0 ), + .I4(\gen_axi.read_cnt_reg__0 [3]), + .I5(p_11_in), + .O(p_0_in[3])); + LUT4 #( + .INIT(16'hC3AA)) + \gen_axi.read_cnt[4]_i_1 + (.I0(\gen_arbiter.m_mesg_i_reg[40] [4]), + .I1(\gen_axi.read_cnt[4]_i_2_n_0 ), + .I2(\gen_axi.read_cnt_reg__0 [4]), + .I3(p_11_in), + .O(p_0_in[4])); + (* SOFT_HLUTNM = "soft_lutpair46" *) + LUT4 #( + .INIT(16'hFFFE)) + \gen_axi.read_cnt[4]_i_2 + (.I0(\gen_axi.read_cnt_reg__0 [2]), + .I1(\gen_axi.read_cnt_reg__0 [1]), + .I2(\gen_axi.read_cnt_reg__0__0 ), + .I3(\gen_axi.read_cnt_reg__0 [3]), + .O(\gen_axi.read_cnt[4]_i_2_n_0 )); + LUT4 #( + .INIT(16'hC3AA)) + \gen_axi.read_cnt[5]_i_1 + (.I0(\gen_arbiter.m_mesg_i_reg[40] [5]), + .I1(\gen_axi.read_cnt_reg__0 [5]), + .I2(\gen_axi.read_cnt[5]_i_2_n_0 ), + .I3(p_11_in), + .O(p_0_in[5])); + (* SOFT_HLUTNM = "soft_lutpair46" *) + LUT5 #( + .INIT(32'hFFFFFFFE)) + \gen_axi.read_cnt[5]_i_2 + (.I0(\gen_axi.read_cnt_reg__0 [3]), + .I1(\gen_axi.read_cnt_reg__0__0 ), + .I2(\gen_axi.read_cnt_reg__0 [1]), + .I3(\gen_axi.read_cnt_reg__0 [2]), + .I4(\gen_axi.read_cnt_reg__0 [4]), + .O(\gen_axi.read_cnt[5]_i_2_n_0 )); + LUT4 #( + .INIT(16'hC3AA)) + \gen_axi.read_cnt[6]_i_1 + (.I0(\gen_arbiter.m_mesg_i_reg[40] [6]), + .I1(\gen_axi.read_cnt[7]_i_3_n_0 ), + .I2(\gen_axi.read_cnt_reg__0 [6]), + .I3(p_11_in), + .O(p_0_in[6])); + LUT6 #( + .INIT(64'h8F80808080808080)) + \gen_axi.read_cnt[7]_i_1 + (.I0(\gen_axi.s_axi_arready_i_i_2_n_0 ), + .I1(mi_rready_1), + .I2(p_11_in), + .I3(aa_mi_arvalid), + .I4(\gen_arbiter.m_target_hot_i_reg[1] ), + .I5(mi_arready), + .O(\gen_axi.read_cnt[7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair45" *) + LUT5 #( + .INIT(32'hFCAA03AA)) + \gen_axi.read_cnt[7]_i_2 + (.I0(\gen_arbiter.m_mesg_i_reg[40] [7]), + .I1(\gen_axi.read_cnt[7]_i_3_n_0 ), + .I2(\gen_axi.read_cnt_reg__0 [6]), + .I3(p_11_in), + .I4(\gen_axi.read_cnt_reg__0 [7]), + .O(p_0_in[7])); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \gen_axi.read_cnt[7]_i_3 + (.I0(\gen_axi.read_cnt_reg__0 [5]), + .I1(\gen_axi.read_cnt_reg__0 [4]), + .I2(\gen_axi.read_cnt_reg__0 [2]), + .I3(\gen_axi.read_cnt_reg__0 [1]), + .I4(\gen_axi.read_cnt_reg__0__0 ), + .I5(\gen_axi.read_cnt_reg__0 [3]), + .O(\gen_axi.read_cnt[7]_i_3_n_0 )); + FDRE \gen_axi.read_cnt_reg[0] + (.C(aclk), + .CE(\gen_axi.read_cnt[7]_i_1_n_0 ), + .D(p_0_in[0]), + .Q(\gen_axi.read_cnt_reg__0__0 ), + .R(SR)); + FDRE \gen_axi.read_cnt_reg[1] + (.C(aclk), + .CE(\gen_axi.read_cnt[7]_i_1_n_0 ), + .D(p_0_in[1]), + .Q(\gen_axi.read_cnt_reg__0 [1]), + .R(SR)); + FDRE \gen_axi.read_cnt_reg[2] + (.C(aclk), + .CE(\gen_axi.read_cnt[7]_i_1_n_0 ), + .D(p_0_in[2]), + .Q(\gen_axi.read_cnt_reg__0 [2]), + .R(SR)); + FDRE \gen_axi.read_cnt_reg[3] + (.C(aclk), + .CE(\gen_axi.read_cnt[7]_i_1_n_0 ), + .D(p_0_in[3]), + .Q(\gen_axi.read_cnt_reg__0 [3]), + .R(SR)); + FDRE \gen_axi.read_cnt_reg[4] + (.C(aclk), + .CE(\gen_axi.read_cnt[7]_i_1_n_0 ), + .D(p_0_in[4]), + .Q(\gen_axi.read_cnt_reg__0 [4]), + .R(SR)); + FDRE \gen_axi.read_cnt_reg[5] + (.C(aclk), + .CE(\gen_axi.read_cnt[7]_i_1_n_0 ), + .D(p_0_in[5]), + .Q(\gen_axi.read_cnt_reg__0 [5]), + .R(SR)); + FDRE \gen_axi.read_cnt_reg[6] + (.C(aclk), + .CE(\gen_axi.read_cnt[7]_i_1_n_0 ), + .D(p_0_in[6]), + .Q(\gen_axi.read_cnt_reg__0 [6]), + .R(SR)); + FDRE \gen_axi.read_cnt_reg[7] + (.C(aclk), + .CE(\gen_axi.read_cnt[7]_i_1_n_0 ), + .D(p_0_in[7]), + .Q(\gen_axi.read_cnt_reg__0 [7]), + .R(SR)); + LUT6 #( + .INIT(64'hBFB0B0B0B0B0B0B0)) + \gen_axi.read_cs[0]_i_1 + (.I0(\gen_axi.s_axi_arready_i_i_2_n_0 ), + .I1(mi_rready_1), + .I2(p_11_in), + .I3(aa_mi_arvalid), + .I4(\gen_arbiter.m_target_hot_i_reg[1] ), + .I5(mi_arready), + .O(\gen_axi.read_cs[0]_i_1_n_0 )); + FDRE \gen_axi.read_cs_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\gen_axi.read_cs[0]_i_1_n_0 ), + .Q(p_11_in), + .R(SR)); + LUT6 #( + .INIT(64'h00000000BFBB0000)) + \gen_axi.s_axi_arready_i_i_1 + (.I0(mi_arready), + .I1(p_11_in), + .I2(\gen_axi.s_axi_arready_i_i_2_n_0 ), + .I3(mi_rready_1), + .I4(aresetn_d), + .I5(s_axi_rid_i), + .O(\gen_axi.s_axi_arready_i_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair45" *) + LUT3 #( + .INIT(8'hFE)) + \gen_axi.s_axi_arready_i_i_2 + (.I0(\gen_axi.read_cnt[7]_i_3_n_0 ), + .I1(\gen_axi.read_cnt_reg__0 [7]), + .I2(\gen_axi.read_cnt_reg__0 [6]), + .O(\gen_axi.s_axi_arready_i_i_2_n_0 )); + LUT4 #( + .INIT(16'h0080)) + \gen_axi.s_axi_arready_i_i_3 + (.I0(mi_arready), + .I1(\gen_arbiter.m_target_hot_i_reg[1] ), + .I2(aa_mi_arvalid), + .I3(p_11_in), + .O(s_axi_rid_i)); + FDRE \gen_axi.s_axi_arready_i_reg + (.C(aclk), + .CE(1'b1), + .D(\gen_axi.s_axi_arready_i_i_1_n_0 ), + .Q(mi_arready), + .R(1'b0)); + LUT5 #( + .INIT(32'hFFFA00CA)) + \gen_axi.s_axi_awready_i_i_1 + (.I0(\gen_axi.s_axi_awready_i_reg_0 ), + .I1(mi_bready_1), + .I2(write_cs[1]), + .I3(write_cs[0]), + .I4(mi_awready), + .O(\gen_axi.s_axi_awready_i_i_1_n_0 )); + FDRE \gen_axi.s_axi_awready_i_reg + (.C(aclk), + .CE(1'b1), + .D(\gen_axi.s_axi_awready_i_i_1_n_0 ), + .Q(mi_awready), + .R(SR)); + LUT5 #( + .INIT(32'hFFFE0002)) + \gen_axi.s_axi_bid_i[0]_i_1 + (.I0(Q), + .I1(write_cs[1]), + .I2(write_cs[0]), + .I3(\gen_axi.s_axi_awready_i_reg_0 ), + .I4(p_20_in), + .O(\gen_axi.s_axi_bid_i[0]_i_1_n_0 )); + FDRE \gen_axi.s_axi_bid_i_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\gen_axi.s_axi_bid_i[0]_i_1_n_0 ), + .Q(p_20_in), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair44" *) + LUT5 #( + .INIT(32'hF5FF00C0)) + \gen_axi.s_axi_bvalid_i_i_1 + (.I0(mi_bready_1), + .I1(write_cs0__0), + .I2(write_cs[0]), + .I3(write_cs[1]), + .I4(p_17_in), + .O(\gen_axi.s_axi_bvalid_i_i_1_n_0 )); + FDRE \gen_axi.s_axi_bvalid_i_reg + (.C(aclk), + .CE(1'b1), + .D(\gen_axi.s_axi_bvalid_i_i_1_n_0 ), + .Q(p_17_in), + .R(SR)); + LUT5 #( + .INIT(32'hF8FFF800)) + \gen_axi.s_axi_rlast_i_i_1 + (.I0(p_11_in), + .I1(\gen_axi.s_axi_arready_i_i_2_n_0 ), + .I2(\gen_axi.read_cs_reg[0]_0 ), + .I3(\gen_axi.s_axi_rlast_i_i_3_n_0 ), + .I4(p_13_in), + .O(\gen_axi.s_axi_rlast_i_i_1_n_0 )); + LUT5 #( + .INIT(32'hFFFF0100)) + \gen_axi.s_axi_rlast_i_i_3 + (.I0(\gen_axi.read_cnt_reg__0 [3]), + .I1(\gen_axi.read_cnt_reg__0 [2]), + .I2(\gen_axi.read_cnt_reg__0 [1]), + .I3(\gen_axi.s_axi_rlast_i_i_5_n_0 ), + .I4(s_axi_rid_i), + .O(\gen_axi.s_axi_rlast_i_i_3_n_0 )); + LUT6 #( + .INIT(64'h0001000000000000)) + \gen_axi.s_axi_rlast_i_i_5 + (.I0(\gen_axi.read_cnt_reg__0 [4]), + .I1(\gen_axi.read_cnt_reg__0 [5]), + .I2(\gen_axi.read_cnt_reg__0 [6]), + .I3(\gen_axi.read_cnt_reg__0 [7]), + .I4(mi_rready_1), + .I5(p_11_in), + .O(\gen_axi.s_axi_rlast_i_i_5_n_0 )); + FDRE \gen_axi.s_axi_rlast_i_reg + (.C(aclk), + .CE(1'b1), + .D(\gen_axi.s_axi_rlast_i_i_1_n_0 ), + .Q(p_13_in), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair43" *) + LUT5 #( + .INIT(32'hFF5F0003)) + \gen_axi.s_axi_wready_i_i_1 + (.I0(write_cs0__0), + .I1(\gen_axi.s_axi_awready_i_reg_0 ), + .I2(write_cs[0]), + .I3(write_cs[1]), + .I4(p_10_in), + .O(\gen_axi.s_axi_wready_i_i_1_n_0 )); + FDRE \gen_axi.s_axi_wready_i_reg + (.C(aclk), + .CE(1'b1), + .D(\gen_axi.s_axi_wready_i_i_1_n_0 ), + .Q(p_10_in), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair43" *) + LUT4 #( + .INIT(16'hC1F1)) + \gen_axi.write_cs[0]_i_1 + (.I0(\gen_axi.s_axi_awready_i_reg_0 ), + .I1(write_cs[1]), + .I2(write_cs[0]), + .I3(write_cs0__0), + .O(\gen_axi.write_cs[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair44" *) + LUT4 #( + .INIT(16'hC8EA)) + \gen_axi.write_cs[1]_i_1 + (.I0(write_cs[1]), + .I1(write_cs[0]), + .I2(write_cs0__0), + .I3(mi_bready_1), + .O(\gen_axi.write_cs[1]_i_1_n_0 )); + FDRE \gen_axi.write_cs_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\gen_axi.write_cs[0]_i_1_n_0 ), + .Q(write_cs[0]), + .R(SR)); + FDRE \gen_axi.write_cs_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\gen_axi.write_cs[1]_i_1_n_0 ), + .Q(write_cs[1]), + .R(SR)); +endmodule + +module Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_si_transactor + (active_target_enc, + active_target_hot, + st_aa_arvalid_qual, + s_axi_rvalid, + E, + p_1_in, + SR, + \gen_arbiter.s_ready_i_reg[0] , + aclk, + \gen_arbiter.s_ready_i_reg[0]_0 , + s_axi_rready, + p_52_out, + m_valid_i_reg, + \m_payload_i_reg[66] , + \s_axi_araddr[29] , + Q, + p_30_out, + p_28_out, + \gen_arbiter.s_ready_i_reg[0]_1 ); + output active_target_enc; + output [0:0]active_target_hot; + output [0:0]st_aa_arvalid_qual; + output [0:0]s_axi_rvalid; + output [0:0]E; + output p_1_in; + input [0:0]SR; + input \gen_arbiter.s_ready_i_reg[0] ; + input aclk; + input \gen_arbiter.s_ready_i_reg[0]_0 ; + input [0:0]s_axi_rready; + input p_52_out; + input m_valid_i_reg; + input \m_payload_i_reg[66] ; + input [0:0]\s_axi_araddr[29] ; + input [0:0]Q; + input p_30_out; + input p_28_out; + input \gen_arbiter.s_ready_i_reg[0]_1 ; + + wire [0:0]E; + wire [0:0]Q; + wire [0:0]SR; + wire [1:0]accept_cnt; + wire aclk; + wire active_target_enc; + wire [0:0]active_target_hot; + wire \gen_arbiter.s_ready_i_reg[0] ; + wire \gen_arbiter.s_ready_i_reg[0]_0 ; + wire \gen_arbiter.s_ready_i_reg[0]_1 ; + wire \gen_single_thread.accept_cnt[0]_i_1_n_0 ; + wire \gen_single_thread.accept_cnt[1]_i_1_n_0 ; + wire \gen_single_thread.accept_cnt[1]_i_3_n_0 ; + wire \m_payload_i_reg[66] ; + wire m_valid_i_reg; + wire p_1_in; + wire p_28_out; + wire p_2_in; + wire p_30_out; + wire p_52_out; + wire [0:0]\s_axi_araddr[29] ; + wire [0:0]s_axi_rready; + wire [0:0]s_axi_rvalid; + wire [0:0]st_aa_arvalid_qual; + + LUT6 #( + .INIT(64'h0055FFF7FFF70055)) + \gen_arbiter.qual_reg[0]_i_3 + (.I0(accept_cnt[1]), + .I1(m_valid_i_reg), + .I2(\m_payload_i_reg[66] ), + .I3(accept_cnt[0]), + .I4(active_target_enc), + .I5(\s_axi_araddr[29] ), + .O(st_aa_arvalid_qual)); + (* SOFT_HLUTNM = "soft_lutpair160" *) + LUT4 #( + .INIT(16'hA54A)) + \gen_single_thread.accept_cnt[0]_i_1 + (.I0(\gen_arbiter.s_ready_i_reg[0]_1 ), + .I1(accept_cnt[1]), + .I2(p_2_in), + .I3(accept_cnt[0]), + .O(\gen_single_thread.accept_cnt[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair160" *) + LUT4 #( + .INIT(16'h9CC4)) + \gen_single_thread.accept_cnt[1]_i_1 + (.I0(p_2_in), + .I1(accept_cnt[1]), + .I2(accept_cnt[0]), + .I3(\gen_arbiter.s_ready_i_reg[0]_1 ), + .O(\gen_single_thread.accept_cnt[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'hF454040454540404)) + \gen_single_thread.accept_cnt[1]_i_2 + (.I0(\gen_single_thread.accept_cnt[1]_i_3_n_0 ), + .I1(Q), + .I2(active_target_enc), + .I3(s_axi_rready), + .I4(p_30_out), + .I5(p_28_out), + .O(p_2_in)); + (* SOFT_HLUTNM = "soft_lutpair162" *) + LUT3 #( + .INIT(8'h7F)) + \gen_single_thread.accept_cnt[1]_i_3 + (.I0(s_axi_rready), + .I1(active_target_hot), + .I2(p_52_out), + .O(\gen_single_thread.accept_cnt[1]_i_3_n_0 )); + FDRE \gen_single_thread.accept_cnt_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\gen_single_thread.accept_cnt[0]_i_1_n_0 ), + .Q(accept_cnt[0]), + .R(SR)); + FDRE \gen_single_thread.accept_cnt_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\gen_single_thread.accept_cnt[1]_i_1_n_0 ), + .Q(accept_cnt[1]), + .R(SR)); + FDRE \gen_single_thread.active_target_enc_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\gen_arbiter.s_ready_i_reg[0] ), + .Q(active_target_enc), + .R(SR)); + FDRE \gen_single_thread.active_target_hot_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\gen_arbiter.s_ready_i_reg[0]_0 ), + .Q(active_target_hot), + .R(SR)); + (* SOFT_HLUTNM = "soft_lutpair162" *) + LUT3 #( + .INIT(8'h8F)) + \m_payload_i[66]_i_1 + (.I0(s_axi_rready), + .I1(active_target_hot), + .I2(p_52_out), + .O(E)); + (* SOFT_HLUTNM = "soft_lutpair161" *) + LUT3 #( + .INIT(8'h8F)) + \m_payload_i[66]_i_2__0 + (.I0(s_axi_rready), + .I1(active_target_enc), + .I2(p_28_out), + .O(p_1_in)); + (* SOFT_HLUTNM = "soft_lutpair161" *) + LUT4 #( + .INIT(16'hF888)) + \s_axi_rvalid[0]_INST_0 + (.I0(p_28_out), + .I1(active_target_enc), + .I2(active_target_hot), + .I3(p_52_out), + .O(s_axi_rvalid)); +endmodule + +(* ORIG_REF_NAME = "axi_crossbar_v2_1_12_si_transactor" *) +module Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_si_transactor__parameterized0 + (active_target_enc, + active_target_hot, + st_aa_awvalid_qual, + SR, + s_ready_i_reg, + aclk, + s_ready_i_reg_0, + s_axi_bready, + \m_payload_i_reg[2] , + sel_4, + s_axi_awready); + output active_target_enc; + output [0:0]active_target_hot; + output [0:0]st_aa_awvalid_qual; + input [0:0]SR; + input s_ready_i_reg; + input aclk; + input s_ready_i_reg_0; + input [0:0]s_axi_bready; + input \m_payload_i_reg[2] ; + input sel_4; + input [0:0]s_axi_awready; + + wire [0:0]SR; + wire [1:0]accept_cnt; + wire aclk; + wire active_target_enc; + wire [0:0]active_target_hot; + wire \gen_single_thread.accept_cnt[0]_i_1__0_n_0 ; + wire \gen_single_thread.accept_cnt[1]_i_1__0_n_0 ; + wire \m_payload_i_reg[2] ; + wire [0:0]s_axi_awready; + wire [0:0]s_axi_bready; + wire s_ready_i_reg; + wire s_ready_i_reg_0; + wire sel_4; + wire [0:0]st_aa_awvalid_qual; + + LUT6 #( + .INIT(64'h0055FFD5FFD50055)) + \gen_arbiter.m_grant_enc_i[0]_i_4 + (.I0(accept_cnt[1]), + .I1(s_axi_bready), + .I2(\m_payload_i_reg[2] ), + .I3(accept_cnt[0]), + .I4(active_target_enc), + .I5(sel_4), + .O(st_aa_awvalid_qual)); + (* SOFT_HLUTNM = "soft_lutpair163" *) + LUT5 #( + .INIT(32'hC03F3F80)) + \gen_single_thread.accept_cnt[0]_i_1__0 + (.I0(accept_cnt[1]), + .I1(\m_payload_i_reg[2] ), + .I2(s_axi_bready), + .I3(s_axi_awready), + .I4(accept_cnt[0]), + .O(\gen_single_thread.accept_cnt[0]_i_1__0_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair163" *) + LUT5 #( + .INIT(32'hD52ABF00)) + \gen_single_thread.accept_cnt[1]_i_1__0 + (.I0(s_axi_awready), + .I1(s_axi_bready), + .I2(\m_payload_i_reg[2] ), + .I3(accept_cnt[1]), + .I4(accept_cnt[0]), + .O(\gen_single_thread.accept_cnt[1]_i_1__0_n_0 )); + FDRE \gen_single_thread.accept_cnt_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\gen_single_thread.accept_cnt[0]_i_1__0_n_0 ), + .Q(accept_cnt[0]), + .R(SR)); + FDRE \gen_single_thread.accept_cnt_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\gen_single_thread.accept_cnt[1]_i_1__0_n_0 ), + .Q(accept_cnt[1]), + .R(SR)); + FDRE \gen_single_thread.active_target_enc_reg[0] + (.C(aclk), + .CE(1'b1), + .D(s_ready_i_reg), + .Q(active_target_enc), + .R(SR)); + FDRE \gen_single_thread.active_target_hot_reg[0] + (.C(aclk), + .CE(1'b1), + .D(s_ready_i_reg_0), + .Q(active_target_hot), + .R(SR)); +endmodule + +module Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_splitter + (\gen_single_thread.active_target_hot_reg[0] , + m_ready_d, + \gen_single_thread.active_target_enc_reg[0] , + s_axi_awready, + \gen_arbiter.qual_reg_reg[1] , + \gen_rep[0].fifoaddr_reg[0] , + sel_4, + ss_wr_awready, + ss_aa_awready, + active_target_hot, + active_target_enc, + s_axi_awvalid, + valid_qual_i111_in, + st_aa_awvalid_qual, + aresetn_d, + aclk); + output \gen_single_thread.active_target_hot_reg[0] ; + output [1:0]m_ready_d; + output \gen_single_thread.active_target_enc_reg[0] ; + output [0:0]s_axi_awready; + output \gen_arbiter.qual_reg_reg[1] ; + output \gen_rep[0].fifoaddr_reg[0] ; + input sel_4; + input [0:0]ss_wr_awready; + input [0:0]ss_aa_awready; + input [0:0]active_target_hot; + input active_target_enc; + input [0:0]s_axi_awvalid; + input valid_qual_i111_in; + input [0:0]st_aa_awvalid_qual; + input aresetn_d; + input aclk; + + wire aclk; + wire active_target_enc; + wire [0:0]active_target_hot; + wire aresetn_d; + wire \gen_arbiter.qual_reg_reg[1] ; + wire \gen_rep[0].fifoaddr_reg[0] ; + wire \gen_single_thread.active_target_enc_reg[0] ; + wire \gen_single_thread.active_target_hot_reg[0] ; + wire [1:0]m_ready_d; + wire \m_ready_d[0]_i_1_n_0 ; + wire \m_ready_d[1]_i_1_n_0 ; + wire [0:0]s_axi_awready; + wire [0:0]s_axi_awvalid; + wire sel_4; + wire [0:0]ss_aa_awready; + wire [0:0]ss_wr_awready; + wire [0:0]st_aa_awvalid_qual; + wire valid_qual_i111_in; + + (* SOFT_HLUTNM = "soft_lutpair164" *) + LUT2 #( + .INIT(4'hB)) + \FSM_onehot_state[2]_i_2 + (.I0(m_ready_d[1]), + .I1(s_axi_awvalid), + .O(\gen_rep[0].fifoaddr_reg[0] )); + LUT4 #( + .INIT(16'hFDDD)) + \gen_arbiter.qual_reg[1]_i_1 + (.I0(s_axi_awvalid), + .I1(m_ready_d[0]), + .I2(valid_qual_i111_in), + .I3(st_aa_awvalid_qual), + .O(\gen_arbiter.qual_reg_reg[1] )); + LUT6 #( + .INIT(64'h575757FF54545400)) + \gen_single_thread.active_target_enc[0]_i_1 + (.I0(sel_4), + .I1(ss_wr_awready), + .I2(m_ready_d[1]), + .I3(ss_aa_awready), + .I4(m_ready_d[0]), + .I5(active_target_enc), + .O(\gen_single_thread.active_target_enc_reg[0] )); + LUT6 #( + .INIT(64'hABABABFFA8A8A800)) + \gen_single_thread.active_target_hot[0]_i_1 + (.I0(sel_4), + .I1(ss_wr_awready), + .I2(m_ready_d[1]), + .I3(ss_aa_awready), + .I4(m_ready_d[0]), + .I5(active_target_hot), + .O(\gen_single_thread.active_target_hot_reg[0] )); + LUT6 #( + .INIT(64'h000C000C00080000)) + \m_ready_d[0]_i_1 + (.I0(s_axi_awvalid), + .I1(aresetn_d), + .I2(ss_wr_awready), + .I3(m_ready_d[1]), + .I4(ss_aa_awready), + .I5(m_ready_d[0]), + .O(\m_ready_d[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h000000000000CC80)) + \m_ready_d[1]_i_1 + (.I0(s_axi_awvalid), + .I1(aresetn_d), + .I2(ss_wr_awready), + .I3(m_ready_d[1]), + .I4(ss_aa_awready), + .I5(m_ready_d[0]), + .O(\m_ready_d[1]_i_1_n_0 )); + FDRE \m_ready_d_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\m_ready_d[0]_i_1_n_0 ), + .Q(m_ready_d[0]), + .R(1'b0)); + FDRE \m_ready_d_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\m_ready_d[1]_i_1_n_0 ), + .Q(m_ready_d[1]), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair164" *) + LUT4 #( + .INIT(16'hEEE0)) + \s_axi_awready[1]_INST_0 + (.I0(ss_wr_awready), + .I1(m_ready_d[1]), + .I2(ss_aa_awready), + .I3(m_ready_d[0]), + .O(s_axi_awready)); +endmodule + +(* ORIG_REF_NAME = "axi_crossbar_v2_1_12_splitter" *) +module Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_splitter_2 + (aa_sa_awready, + \gen_arbiter.any_grant_reg , + m_ready_d, + aresetn_d, + aa_sa_awvalid, + mi_awready, + m_axi_awready, + Q, + \gen_arbiter.m_target_hot_i_reg[0] , + \gen_arbiter.m_target_hot_i_reg[1] , + aclk); + output aa_sa_awready; + output \gen_arbiter.any_grant_reg ; + output [1:0]m_ready_d; + input aresetn_d; + input aa_sa_awvalid; + input [0:0]mi_awready; + input [0:0]m_axi_awready; + input [1:0]Q; + input \gen_arbiter.m_target_hot_i_reg[0] ; + input \gen_arbiter.m_target_hot_i_reg[1] ; + input aclk; + + wire [1:0]Q; + wire aa_sa_awready; + wire aa_sa_awvalid; + wire aclk; + wire aresetn_d; + wire \gen_arbiter.any_grant_reg ; + wire \gen_arbiter.m_target_hot_i_reg[0] ; + wire \gen_arbiter.m_target_hot_i_reg[1] ; + wire [0:0]m_axi_awready; + wire [1:0]m_ready_d; + wire \m_ready_d[0]_i_1_n_0 ; + wire \m_ready_d[1]_i_1_n_0 ; + wire \m_ready_d[1]_i_4_n_0 ; + wire [0:0]mi_awready; + + (* SOFT_HLUTNM = "soft_lutpair167" *) + LUT3 #( + .INIT(8'h8F)) + \gen_arbiter.any_grant_i_2 + (.I0(aa_sa_awready), + .I1(aa_sa_awvalid), + .I2(aresetn_d), + .O(\gen_arbiter.any_grant_reg )); + LUT6 #( + .INIT(64'h00000000FCF80000)) + \m_ready_d[0]_i_1 + (.I0(Q[1]), + .I1(aa_sa_awvalid), + .I2(m_ready_d[0]), + .I3(Q[0]), + .I4(aresetn_d), + .I5(aa_sa_awready), + .O(\m_ready_d[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFCFFCCFFF0AA00)) + \m_ready_d[0]_i_2 + (.I0(m_ready_d[0]), + .I1(mi_awready), + .I2(m_axi_awready), + .I3(m_ready_d[1]), + .I4(Q[0]), + .I5(Q[1]), + .O(aa_sa_awready)); + LUT6 #( + .INIT(64'h00000000FFFF2F22)) + \m_ready_d[1]_i_1 + (.I0(m_axi_awready), + .I1(\gen_arbiter.m_target_hot_i_reg[0] ), + .I2(\gen_arbiter.m_target_hot_i_reg[1] ), + .I3(mi_awready), + .I4(m_ready_d[1]), + .I5(\m_ready_d[1]_i_4_n_0 ), + .O(\m_ready_d[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair167" *) + LUT2 #( + .INIT(4'hB)) + \m_ready_d[1]_i_4 + (.I0(aa_sa_awready), + .I1(aresetn_d), + .O(\m_ready_d[1]_i_4_n_0 )); + FDRE \m_ready_d_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\m_ready_d[0]_i_1_n_0 ), + .Q(m_ready_d[0]), + .R(1'b0)); + FDRE \m_ready_d_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\m_ready_d[1]_i_1_n_0 ), + .Q(m_ready_d[1]), + .R(1'b0)); +endmodule + +module Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_wdata_mux + (E, + \storage_data1_reg[0] , + m_valid_i_reg, + D, + s_ready_i_reg, + m_axi_wvalid, + m_axi_wstrb, + m_axi_wdata, + m_axi_wlast, + aa_wm_awgrant_enc, + aclk, + out, + \gen_arbiter.m_valid_i_reg , + in1, + m_ready_d, + Q, + aa_sa_awvalid, + \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0] , + \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1] , + m_select_enc, + m_axi_wready, + s_axi_wvalid, + m_avalid, + m_valid_i_reg_0, + s_axi_wlast, + s_axi_wstrb, + s_axi_wdata, + SR); + output [0:0]E; + output \storage_data1_reg[0] ; + output m_valid_i_reg; + output [1:0]D; + output s_ready_i_reg; + output [0:0]m_axi_wvalid; + output [7:0]m_axi_wstrb; + output [63:0]m_axi_wdata; + output [0:0]m_axi_wlast; + input aa_wm_awgrant_enc; + input aclk; + input [2:0]out; + input \gen_arbiter.m_valid_i_reg ; + input in1; + input [0:0]m_ready_d; + input [0:0]Q; + input aa_sa_awvalid; + input \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0] ; + input \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1] ; + input m_select_enc; + input [0:0]m_axi_wready; + input [0:0]s_axi_wvalid; + input m_avalid; + input m_valid_i_reg_0; + input [0:0]s_axi_wlast; + input [7:0]s_axi_wstrb; + input [63:0]s_axi_wdata; + input [0:0]SR; + + wire [1:0]D; + wire [0:0]E; + wire [0:0]Q; + wire [0:0]SR; + wire aa_sa_awvalid; + wire aa_wm_awgrant_enc; + wire aclk; + wire \gen_arbiter.m_valid_i_reg ; + wire \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0] ; + wire \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1] ; + wire in1; + wire m_avalid; + wire [63:0]m_axi_wdata; + wire [0:0]m_axi_wlast; + wire [0:0]m_axi_wready; + wire [7:0]m_axi_wstrb; + wire [0:0]m_axi_wvalid; + wire [0:0]m_ready_d; + wire m_select_enc; + wire m_valid_i_reg; + wire m_valid_i_reg_0; + wire [2:0]out; + wire [63:0]s_axi_wdata; + wire [0:0]s_axi_wlast; + wire [7:0]s_axi_wstrb; + wire [0:0]s_axi_wvalid; + wire s_ready_i_reg; + wire \storage_data1_reg[0] ; + + Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized0 \gen_wmux.wmux_aw_fifo + (.D(D), + .E(E), + .Q(Q), + .SR(SR), + .aa_sa_awvalid(aa_sa_awvalid), + .aa_wm_awgrant_enc(aa_wm_awgrant_enc), + .aclk(aclk), + .\gen_arbiter.m_valid_i_reg (\gen_arbiter.m_valid_i_reg ), + .\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0] (\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0] ), + .\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1] (\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1] ), + .in1(in1), + .m_avalid(m_avalid), + .m_axi_wdata(m_axi_wdata), + .m_axi_wlast(m_axi_wlast), + .m_axi_wready(m_axi_wready), + .m_axi_wstrb(m_axi_wstrb), + .m_axi_wvalid(m_axi_wvalid), + .m_ready_d(m_ready_d), + .m_select_enc(m_select_enc), + .m_valid_i_reg_0(m_valid_i_reg), + .m_valid_i_reg_1(m_valid_i_reg_0), + .out(out), + .s_axi_wdata(s_axi_wdata), + .s_axi_wlast(s_axi_wlast), + .s_axi_wstrb(s_axi_wstrb), + .s_axi_wvalid(s_axi_wvalid), + .s_ready_i_reg(s_ready_i_reg), + .\storage_data1_reg[0]_0 (\storage_data1_reg[0] )); +endmodule + +(* ORIG_REF_NAME = "axi_crossbar_v2_1_12_wdata_mux" *) +module Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_wdata_mux__parameterized0 + (m_valid_i_reg, + m_avalid, + m_select_enc, + write_cs0__0, + s_axi_wready, + s_ready_i_reg, + \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3] , + aa_wm_awgrant_enc, + aclk, + \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 , + sa_wm_awvalid, + \storage_data1_reg[0] , + in1, + p_10_in, + \storage_data1_reg[0]_0 , + m_select_enc_0, + m_avalid_1, + s_axi_wlast, + s_axi_wvalid, + SR, + m_ready_d, + Q, + aa_sa_awvalid); + output [0:0]m_valid_i_reg; + output m_avalid; + output m_select_enc; + output write_cs0__0; + output [0:0]s_axi_wready; + output s_ready_i_reg; + output [3:0]\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3] ; + input aa_wm_awgrant_enc; + input aclk; + input [2:0]\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 ; + input [0:0]sa_wm_awvalid; + input \storage_data1_reg[0] ; + input in1; + input p_10_in; + input \storage_data1_reg[0]_0 ; + input m_select_enc_0; + input m_avalid_1; + input [0:0]s_axi_wlast; + input [0:0]s_axi_wvalid; + input [0:0]SR; + input [0:0]m_ready_d; + input [0:0]Q; + input aa_sa_awvalid; + + wire [0:0]Q; + wire [0:0]SR; + wire aa_sa_awvalid; + wire aa_wm_awgrant_enc; + wire aclk; + wire [3:0]\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3] ; + wire [2:0]\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 ; + wire in1; + wire m_avalid; + wire m_avalid_1; + wire [0:0]m_ready_d; + wire m_select_enc; + wire m_select_enc_0; + wire [0:0]m_valid_i_reg; + wire p_10_in; + wire [0:0]s_axi_wlast; + wire [0:0]s_axi_wready; + wire [0:0]s_axi_wvalid; + wire s_ready_i_reg; + wire [0:0]sa_wm_awvalid; + wire \storage_data1_reg[0] ; + wire \storage_data1_reg[0]_0 ; + wire write_cs0__0; + + Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized1 \gen_wmux.wmux_aw_fifo + (.Q(Q), + .SR(SR), + .aa_sa_awvalid(aa_sa_awvalid), + .aa_wm_awgrant_enc(aa_wm_awgrant_enc), + .aclk(aclk), + .\gen_axi.s_axi_wready_i_reg (m_avalid), + .\gen_axi.s_axi_wready_i_reg_0 (write_cs0__0), + .\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3] (\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3] ), + .\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 (\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 ), + .in1(in1), + .m_avalid_1(m_avalid_1), + .m_ready_d(m_ready_d), + .m_select_enc_0(m_select_enc_0), + .m_valid_i_reg_0(m_valid_i_reg), + .p_10_in(p_10_in), + .s_axi_wlast(s_axi_wlast), + .s_axi_wready(s_axi_wready), + .s_axi_wvalid(s_axi_wvalid), + .s_ready_i_reg(s_ready_i_reg), + .sa_wm_awvalid(sa_wm_awvalid), + .\storage_data1_reg[0]_0 (m_select_enc), + .\storage_data1_reg[0]_1 (\storage_data1_reg[0] ), + .\storage_data1_reg[0]_2 (\storage_data1_reg[0]_0 )); +endmodule + +module Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_wdata_router + (SS, + m_avalid, + ss_wr_awready, + m_select_enc, + s_ready_i_reg, + \gen_rep[0].fifoaddr_reg[0] , + aclk, + SR, + s_axi_awvalid, + m_ready_d, + s_axi_awaddr, + m_valid_i_reg, + \storage_data1_reg[0] , + s_axi_wvalid, + s_axi_wlast, + m_select_enc_0, + m_avalid_1, + p_10_in, + \m_ready_d_reg[1] ); + output [0:0]SS; + output m_avalid; + output [0:0]ss_wr_awready; + output m_select_enc; + output s_ready_i_reg; + output \gen_rep[0].fifoaddr_reg[0] ; + input aclk; + input [0:0]SR; + input [0:0]s_axi_awvalid; + input [0:0]m_ready_d; + input [2:0]s_axi_awaddr; + input m_valid_i_reg; + input \storage_data1_reg[0] ; + input [0:0]s_axi_wvalid; + input [0:0]s_axi_wlast; + input m_select_enc_0; + input m_avalid_1; + input p_10_in; + input \m_ready_d_reg[1] ; + + wire [0:0]SR; + wire [0:0]SS; + wire aclk; + wire \gen_rep[0].fifoaddr_reg[0] ; + wire m_avalid; + wire m_avalid_1; + wire [0:0]m_ready_d; + wire \m_ready_d_reg[1] ; + wire m_select_enc; + wire m_select_enc_0; + wire m_valid_i_reg; + wire p_10_in; + wire [2:0]s_axi_awaddr; + wire [0:0]s_axi_awvalid; + wire [0:0]s_axi_wlast; + wire [0:0]s_axi_wvalid; + wire s_ready_i_reg; + wire [0:0]ss_wr_awready; + wire \storage_data1_reg[0] ; + + Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_axic_reg_srl_fifo wrouter_aw_fifo + (.SR(SS), + .aclk(aclk), + .aresetn_d_reg(SR), + .\gen_rep[0].fifoaddr_reg[0]_0 (\gen_rep[0].fifoaddr_reg[0] ), + .m_avalid_1(m_avalid_1), + .m_ready_d(m_ready_d), + .\m_ready_d_reg[1] (\m_ready_d_reg[1] ), + .m_select_enc(m_select_enc), + .m_select_enc_0(m_select_enc_0), + .m_valid_i_reg_0(m_valid_i_reg), + .p_10_in(p_10_in), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_wlast(s_axi_wlast), + .s_axi_wvalid(s_axi_wvalid), + .s_ready_i_reg_0(ss_wr_awready), + .s_ready_i_reg_1(s_ready_i_reg), + .\storage_data1_reg[0]_0 (m_avalid), + .\storage_data1_reg[0]_1 (\storage_data1_reg[0] )); +endmodule + +module Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_axic_reg_srl_fifo + (SR, + \storage_data1_reg[0]_0 , + s_ready_i_reg_0, + m_select_enc, + s_ready_i_reg_1, + \gen_rep[0].fifoaddr_reg[0]_0 , + aclk, + aresetn_d_reg, + s_axi_awvalid, + m_ready_d, + s_axi_awaddr, + m_valid_i_reg_0, + \storage_data1_reg[0]_1 , + s_axi_wvalid, + s_axi_wlast, + m_select_enc_0, + m_avalid_1, + p_10_in, + \m_ready_d_reg[1] ); + output [0:0]SR; + output \storage_data1_reg[0]_0 ; + output s_ready_i_reg_0; + output m_select_enc; + output s_ready_i_reg_1; + output \gen_rep[0].fifoaddr_reg[0]_0 ; + input aclk; + input [0:0]aresetn_d_reg; + input [0:0]s_axi_awvalid; + input [0:0]m_ready_d; + input [2:0]s_axi_awaddr; + input m_valid_i_reg_0; + input \storage_data1_reg[0]_1 ; + input [0:0]s_axi_wvalid; + input [0:0]s_axi_wlast; + input m_select_enc_0; + input m_avalid_1; + input p_10_in; + input \m_ready_d_reg[1] ; + + wire \FSM_onehot_state[0]_i_1_n_0 ; + wire \FSM_onehot_state[1]_i_1_n_0 ; + wire \FSM_onehot_state[2]_i_1_n_0 ; + wire \FSM_onehot_state[2]_i_3_n_0 ; + wire \FSM_onehot_state[3]_i_2_n_0 ; + wire \FSM_onehot_state[3]_i_3_n_0 ; + wire \FSM_onehot_state[3]_i_4_n_0 ; + wire \FSM_onehot_state[3]_i_5_n_0 ; + (* RTL_KEEP = "yes" *) wire \FSM_onehot_state_reg_n_0_[2] ; + (* RTL_KEEP = "yes" *) wire \FSM_onehot_state_reg_n_0_[3] ; + wire [0:0]SR; + wire aclk; + wire [0:0]aresetn_d_reg; + wire [1:0]fifoaddr; + wire \gen_rep[0].fifoaddr[0]_i_1_n_0 ; + wire \gen_rep[0].fifoaddr[1]_i_1_n_0 ; + wire \gen_rep[0].fifoaddr_reg[0]_0 ; + wire \gen_srls[0].gen_rep[0].srl_nx1_n_1 ; + wire m_aready__1; + wire m_avalid_1; + wire [0:0]m_ready_d; + wire \m_ready_d_reg[1] ; + wire m_select_enc; + wire m_select_enc_0; + wire m_valid_i; + wire m_valid_i_i_1_n_0; + wire m_valid_i_i_2_n_0; + wire m_valid_i_reg_0; + (* RTL_KEEP = "yes" *) wire p_0_in8_in; + wire p_10_in; + (* RTL_KEEP = "yes" *) wire p_9_in; + wire push; + wire [2:0]s_axi_awaddr; + wire [0:0]s_axi_awvalid; + wire [0:0]s_axi_wlast; + wire [0:0]s_axi_wvalid; + wire s_ready_i_i_1_n_0; + wire s_ready_i_reg_0; + wire s_ready_i_reg_1; + wire \storage_data1_reg[0]_0 ; + wire \storage_data1_reg[0]_1 ; + + LUT5 #( + .INIT(32'h51000000)) + \FSM_onehot_state[0]_i_1 + (.I0(p_9_in), + .I1(s_axi_awvalid), + .I2(m_ready_d), + .I3(m_aready__1), + .I4(p_0_in8_in), + .O(\FSM_onehot_state[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h4444444444444744)) + \FSM_onehot_state[1]_i_1 + (.I0(\m_ready_d_reg[1] ), + .I1(p_9_in), + .I2(push), + .I3(\FSM_onehot_state[3]_i_5_n_0 ), + .I4(\FSM_onehot_state[2]_i_3_n_0 ), + .I5(p_0_in8_in), + .O(\FSM_onehot_state[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'h88888888BBBBB8BB)) + \FSM_onehot_state[2]_i_1 + (.I0(\m_ready_d_reg[1] ), + .I1(p_9_in), + .I2(push), + .I3(\FSM_onehot_state[3]_i_5_n_0 ), + .I4(\FSM_onehot_state[2]_i_3_n_0 ), + .I5(p_0_in8_in), + .O(\FSM_onehot_state[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'h57FFFFFFFFFFFFFF)) + \FSM_onehot_state[2]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[3] ), + .I1(m_valid_i_reg_0), + .I2(\storage_data1_reg[0]_1 ), + .I3(s_axi_wvalid), + .I4(\storage_data1_reg[0]_0 ), + .I5(s_axi_wlast), + .O(\FSM_onehot_state[2]_i_3_n_0 )); + LUT6 #( + .INIT(64'hEFEEEEEEEEEEEEEE)) + \FSM_onehot_state[3]_i_1 + (.I0(\FSM_onehot_state[3]_i_3_n_0 ), + .I1(\FSM_onehot_state[3]_i_4_n_0 ), + .I2(push), + .I3(\FSM_onehot_state[3]_i_5_n_0 ), + .I4(m_aready__1), + .I5(\FSM_onehot_state_reg_n_0_[3] ), + .O(m_valid_i)); + LUT5 #( + .INIT(32'h000008AA)) + \FSM_onehot_state[3]_i_2 + (.I0(p_0_in8_in), + .I1(s_axi_awvalid), + .I2(m_ready_d), + .I3(m_aready__1), + .I4(p_9_in), + .O(\FSM_onehot_state[3]_i_2_n_0 )); + LUT6 #( + .INIT(64'h808080002A2A2AAA)) + \FSM_onehot_state[3]_i_3 + (.I0(p_0_in8_in), + .I1(s_axi_wlast), + .I2(s_ready_i_reg_1), + .I3(\storage_data1_reg[0]_1 ), + .I4(m_valid_i_reg_0), + .I5(\m_ready_d_reg[1] ), + .O(\FSM_onehot_state[3]_i_3_n_0 )); + LUT3 #( + .INIT(8'h08)) + \FSM_onehot_state[3]_i_4 + (.I0(p_9_in), + .I1(s_axi_awvalid), + .I2(m_ready_d), + .O(\FSM_onehot_state[3]_i_4_n_0 )); + LUT2 #( + .INIT(4'h1)) + \FSM_onehot_state[3]_i_5 + (.I0(fifoaddr[0]), + .I1(fifoaddr[1]), + .O(\FSM_onehot_state[3]_i_5_n_0 )); + LUT5 #( + .INIT(32'h80808000)) + \FSM_onehot_state[3]_i_6 + (.I0(s_axi_wlast), + .I1(\storage_data1_reg[0]_0 ), + .I2(s_axi_wvalid), + .I3(\storage_data1_reg[0]_1 ), + .I4(m_valid_i_reg_0), + .O(m_aready__1)); + (* KEEP = "yes" *) + FDSE #( + .INIT(1'b1)) + \FSM_onehot_state_reg[0] + (.C(aclk), + .CE(m_valid_i), + .D(\FSM_onehot_state[0]_i_1_n_0 ), + .Q(p_9_in), + .S(SR)); + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[1] + (.C(aclk), + .CE(m_valid_i), + .D(\FSM_onehot_state[1]_i_1_n_0 ), + .Q(p_0_in8_in), + .R(SR)); + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[2] + (.C(aclk), + .CE(m_valid_i), + .D(\FSM_onehot_state[2]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[2] ), + .R(SR)); + (* KEEP = "yes" *) + FDRE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[3] + (.C(aclk), + .CE(m_valid_i), + .D(\FSM_onehot_state[3]_i_2_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[3] ), + .R(SR)); + FDRE areset_d1_reg + (.C(aclk), + .CE(1'b1), + .D(aresetn_d_reg), + .Q(SR), + .R(1'b0)); + LUT6 #( + .INIT(64'h5AFB51FBA504AE04)) + \gen_rep[0].fifoaddr[0]_i_1 + (.I0(m_aready__1), + .I1(p_0_in8_in), + .I2(\m_ready_d_reg[1] ), + .I3(\FSM_onehot_state_reg_n_0_[3] ), + .I4(s_ready_i_reg_0), + .I5(fifoaddr[0]), + .O(\gen_rep[0].fifoaddr[0]_i_1_n_0 )); + LUT5 #( + .INIT(32'hD5BF2A40)) + \gen_rep[0].fifoaddr[1]_i_1 + (.I0(fifoaddr[0]), + .I1(m_aready__1), + .I2(\FSM_onehot_state_reg_n_0_[3] ), + .I3(push), + .I4(fifoaddr[1]), + .O(\gen_rep[0].fifoaddr[1]_i_1_n_0 )); + (* syn_keep = "1" *) + FDSE \gen_rep[0].fifoaddr_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\gen_rep[0].fifoaddr[0]_i_1_n_0 ), + .Q(fifoaddr[0]), + .S(aresetn_d_reg)); + (* syn_keep = "1" *) + FDSE \gen_rep[0].fifoaddr_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\gen_rep[0].fifoaddr[1]_i_1_n_0 ), + .Q(fifoaddr[1]), + .S(aresetn_d_reg)); + Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_ndeep_srl \gen_srls[0].gen_rep[0].srl_nx1 + (.\FSM_onehot_state_reg[0] (\FSM_onehot_state[3]_i_4_n_0 ), + .aclk(aclk), + .fifoaddr(fifoaddr), + .m_aready__1(m_aready__1), + .m_ready_d(m_ready_d), + .m_select_enc(m_select_enc), + .m_valid_i_reg(m_valid_i_reg_0), + .m_valid_i_reg_0(\storage_data1_reg[0]_0 ), + .out0({p_0_in8_in,\FSM_onehot_state_reg_n_0_[3] }), + .push(push), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_wlast(s_axi_wlast), + .s_axi_wvalid(s_axi_wvalid), + .s_ready_i_reg(s_ready_i_reg_1), + .s_ready_i_reg_0(s_ready_i_reg_0), + .\storage_data1_reg[0] (\gen_srls[0].gen_rep[0].srl_nx1_n_1 ), + .\storage_data1_reg[0]_0 (\storage_data1_reg[0]_1 )); + LUT6 #( + .INIT(64'hEFEEEEEEEEEEEEEE)) + m_valid_i_i_1 + (.I0(m_valid_i_i_2_n_0), + .I1(\FSM_onehot_state[3]_i_4_n_0 ), + .I2(push), + .I3(\FSM_onehot_state[3]_i_5_n_0 ), + .I4(m_aready__1), + .I5(\FSM_onehot_state_reg_n_0_[3] ), + .O(m_valid_i_i_1_n_0)); + LUT6 #( + .INIT(64'h000000002A2A2AAA)) + m_valid_i_i_2 + (.I0(p_0_in8_in), + .I1(s_axi_wlast), + .I2(s_ready_i_reg_1), + .I3(\storage_data1_reg[0]_1 ), + .I4(m_valid_i_reg_0), + .I5(\m_ready_d_reg[1] ), + .O(m_valid_i_i_2_n_0)); + LUT6 #( + .INIT(64'h7FFFFFFFFFFFFFFF)) + m_valid_i_i_2__0 + (.I0(s_ready_i_reg_1), + .I1(m_select_enc), + .I2(s_axi_wlast), + .I3(m_select_enc_0), + .I4(m_avalid_1), + .I5(p_10_in), + .O(\gen_rep[0].fifoaddr_reg[0]_0 )); + FDRE m_valid_i_reg + (.C(aclk), + .CE(m_valid_i), + .D(m_valid_i_i_1_n_0), + .Q(\storage_data1_reg[0]_0 ), + .R(SR)); + LUT6 #( + .INIT(64'hFFFFDFFFDDDDDDDD)) + s_ready_i_i_1 + (.I0(\FSM_onehot_state[2]_i_3_n_0 ), + .I1(SR), + .I2(push), + .I3(fifoaddr[1]), + .I4(fifoaddr[0]), + .I5(s_ready_i_reg_0), + .O(s_ready_i_i_1_n_0)); + FDRE s_ready_i_reg + (.C(aclk), + .CE(1'b1), + .D(s_ready_i_i_1_n_0), + .Q(s_ready_i_reg_0), + .R(aresetn_d_reg)); + FDRE \storage_data1_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\gen_srls[0].gen_rep[0].srl_nx1_n_1 ), + .Q(m_select_enc), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "axi_data_fifo_v2_1_10_axic_reg_srl_fifo" *) +module Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized0 + (E, + \storage_data1_reg[0]_0 , + m_valid_i_reg_0, + D, + s_ready_i_reg, + m_axi_wvalid, + m_axi_wstrb, + m_axi_wdata, + m_axi_wlast, + aa_wm_awgrant_enc, + aclk, + out, + \gen_arbiter.m_valid_i_reg , + in1, + m_ready_d, + Q, + aa_sa_awvalid, + \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0] , + \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1] , + m_select_enc, + m_axi_wready, + s_axi_wvalid, + m_avalid, + m_valid_i_reg_1, + s_axi_wlast, + s_axi_wstrb, + s_axi_wdata, + SR); + output [0:0]E; + output \storage_data1_reg[0]_0 ; + output m_valid_i_reg_0; + output [1:0]D; + output s_ready_i_reg; + output [0:0]m_axi_wvalid; + output [7:0]m_axi_wstrb; + output [63:0]m_axi_wdata; + output [0:0]m_axi_wlast; + input aa_wm_awgrant_enc; + input aclk; + input [2:0]out; + input \gen_arbiter.m_valid_i_reg ; + input in1; + input [0:0]m_ready_d; + input [0:0]Q; + input aa_sa_awvalid; + input \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0] ; + input \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1] ; + input m_select_enc; + input [0:0]m_axi_wready; + input [0:0]s_axi_wvalid; + input m_avalid; + input m_valid_i_reg_1; + input [0:0]s_axi_wlast; + input [7:0]s_axi_wstrb; + input [63:0]s_axi_wdata; + input [0:0]SR; + + wire [1:0]D; + wire [0:0]E; + wire [0:0]Q; + wire [0:0]SR; + wire aa_sa_awvalid; + wire aa_wm_awgrant_enc; + wire aclk; + wire [2:0]fifoaddr; + wire \gen_arbiter.m_valid_i_reg ; + wire \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0] ; + wire \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1] ; + wire \gen_rep[0].fifoaddr[0]_i_1_n_0 ; + wire \gen_rep[0].fifoaddr[1]_i_1_n_0 ; + wire \gen_rep[0].fifoaddr[2]_i_1_n_0 ; + wire \gen_srls[0].gen_rep[0].srl_nx1_n_1 ; + wire in1; + wire m_avalid; + wire m_avalid_0; + wire [63:0]m_axi_wdata; + wire [0:0]m_axi_wlast; + wire [0:0]m_axi_wready; + wire [7:0]m_axi_wstrb; + wire [0:0]m_axi_wvalid; + wire [0:0]m_ready_d; + wire m_select_enc; + wire m_select_enc_1; + wire m_valid_i_n_0; + wire m_valid_i_reg_0; + wire m_valid_i_reg_1; + wire [2:0]out; + wire push; + wire [63:0]s_axi_wdata; + wire [0:0]s_axi_wlast; + wire [7:0]s_axi_wstrb; + wire [0:0]s_axi_wvalid; + wire s_ready_i_reg; + wire \storage_data1_reg[0]_0 ; + + LUT6 #( + .INIT(64'h4555000000000000)) + \FSM_onehot_state[0]_i_1 + (.I0(out[0]), + .I1(m_ready_d), + .I2(Q), + .I3(aa_sa_awvalid), + .I4(\storage_data1_reg[0]_0 ), + .I5(out[1]), + .O(D[0])); + LUT6 #( + .INIT(64'hE3E2E322E322E322)) + \FSM_onehot_state[3]_i_1 + (.I0(out[0]), + .I1(\gen_arbiter.m_valid_i_reg ), + .I2(\storage_data1_reg[0]_0 ), + .I3(out[1]), + .I4(out[2]), + .I5(m_valid_i_reg_0), + .O(E)); + LUT6 #( + .INIT(64'h000000002000AAAA)) + \FSM_onehot_state[3]_i_2 + (.I0(out[1]), + .I1(m_ready_d), + .I2(Q), + .I3(aa_sa_awvalid), + .I4(\storage_data1_reg[0]_0 ), + .I5(out[0]), + .O(D[1])); + LUT5 #( + .INIT(32'h5AFBA504)) + \gen_rep[0].fifoaddr[0]_i_1 + (.I0(\storage_data1_reg[0]_0 ), + .I1(out[1]), + .I2(\gen_arbiter.m_valid_i_reg ), + .I3(out[2]), + .I4(fifoaddr[0]), + .O(\gen_rep[0].fifoaddr[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'hBFBFF5F740400A08)) + \gen_rep[0].fifoaddr[1]_i_1 + (.I0(fifoaddr[0]), + .I1(out[2]), + .I2(\gen_arbiter.m_valid_i_reg ), + .I3(out[1]), + .I4(\storage_data1_reg[0]_0 ), + .I5(fifoaddr[1]), + .O(\gen_rep[0].fifoaddr[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'hF777EFFF08881000)) + \gen_rep[0].fifoaddr[2]_i_1 + (.I0(fifoaddr[1]), + .I1(fifoaddr[0]), + .I2(\storage_data1_reg[0]_0 ), + .I3(out[2]), + .I4(push), + .I5(fifoaddr[2]), + .O(\gen_rep[0].fifoaddr[2]_i_1_n_0 )); + (* syn_keep = "1" *) + FDSE \gen_rep[0].fifoaddr_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\gen_rep[0].fifoaddr[0]_i_1_n_0 ), + .Q(fifoaddr[0]), + .S(SR)); + (* syn_keep = "1" *) + FDSE \gen_rep[0].fifoaddr_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\gen_rep[0].fifoaddr[1]_i_1_n_0 ), + .Q(fifoaddr[1]), + .S(SR)); + (* syn_keep = "1" *) + FDSE \gen_rep[0].fifoaddr_reg[2] + (.C(aclk), + .CE(1'b1), + .D(\gen_rep[0].fifoaddr[2]_i_1_n_0 ), + .Q(fifoaddr[2]), + .S(SR)); + Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_ndeep_srl__parameterized8 \gen_srls[0].gen_rep[0].srl_nx1 + (.A(fifoaddr), + .aa_wm_awgrant_enc(aa_wm_awgrant_enc), + .aclk(aclk), + .\gen_arbiter.m_valid_i_reg (\gen_arbiter.m_valid_i_reg ), + .\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0] (\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0] ), + .\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1] (\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1] ), + .m_avalid_0(m_avalid_0), + .m_axi_wready(m_axi_wready), + .m_select_enc(m_select_enc), + .m_select_enc_1(m_select_enc_1), + .m_valid_i_reg(m_valid_i_reg_1), + .out(out[2:1]), + .push(push), + .s_axi_wlast(s_axi_wlast), + .\storage_data1_reg[0] (\gen_srls[0].gen_rep[0].srl_nx1_n_1 ), + .\storage_data1_reg[0]_0 (\storage_data1_reg[0]_0 )); + (* SOFT_HLUTNM = "soft_lutpair84" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[0]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[0]), + .O(m_axi_wdata[0])); + (* SOFT_HLUTNM = "soft_lutpair79" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[10]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[10]), + .O(m_axi_wdata[10])); + (* SOFT_HLUTNM = "soft_lutpair78" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[11]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[11]), + .O(m_axi_wdata[11])); + (* SOFT_HLUTNM = "soft_lutpair78" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[12]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[12]), + .O(m_axi_wdata[12])); + (* SOFT_HLUTNM = "soft_lutpair77" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[13]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[13]), + .O(m_axi_wdata[13])); + (* SOFT_HLUTNM = "soft_lutpair77" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[14]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[14]), + .O(m_axi_wdata[14])); + (* SOFT_HLUTNM = "soft_lutpair76" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[15]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[15]), + .O(m_axi_wdata[15])); + (* SOFT_HLUTNM = "soft_lutpair76" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[16]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[16]), + .O(m_axi_wdata[16])); + (* SOFT_HLUTNM = "soft_lutpair75" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[17]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[17]), + .O(m_axi_wdata[17])); + (* SOFT_HLUTNM = "soft_lutpair75" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[18]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[18]), + .O(m_axi_wdata[18])); + (* SOFT_HLUTNM = "soft_lutpair74" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[19]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[19]), + .O(m_axi_wdata[19])); + (* SOFT_HLUTNM = "soft_lutpair83" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[1]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[1]), + .O(m_axi_wdata[1])); + (* SOFT_HLUTNM = "soft_lutpair74" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[20]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[20]), + .O(m_axi_wdata[20])); + (* SOFT_HLUTNM = "soft_lutpair73" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[21]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[21]), + .O(m_axi_wdata[21])); + (* SOFT_HLUTNM = "soft_lutpair73" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[22]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[22]), + .O(m_axi_wdata[22])); + (* SOFT_HLUTNM = "soft_lutpair72" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[23]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[23]), + .O(m_axi_wdata[23])); + (* SOFT_HLUTNM = "soft_lutpair72" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[24]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[24]), + .O(m_axi_wdata[24])); + (* SOFT_HLUTNM = "soft_lutpair71" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[25]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[25]), + .O(m_axi_wdata[25])); + (* SOFT_HLUTNM = "soft_lutpair71" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[26]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[26]), + .O(m_axi_wdata[26])); + (* SOFT_HLUTNM = "soft_lutpair70" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[27]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[27]), + .O(m_axi_wdata[27])); + (* SOFT_HLUTNM = "soft_lutpair70" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[28]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[28]), + .O(m_axi_wdata[28])); + (* SOFT_HLUTNM = "soft_lutpair69" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[29]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[29]), + .O(m_axi_wdata[29])); + (* SOFT_HLUTNM = "soft_lutpair83" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[2]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[2]), + .O(m_axi_wdata[2])); + (* SOFT_HLUTNM = "soft_lutpair69" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[30]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[30]), + .O(m_axi_wdata[30])); + (* SOFT_HLUTNM = "soft_lutpair68" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[31]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[31]), + .O(m_axi_wdata[31])); + (* SOFT_HLUTNM = "soft_lutpair68" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[32]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[32]), + .O(m_axi_wdata[32])); + (* SOFT_HLUTNM = "soft_lutpair67" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[33]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[33]), + .O(m_axi_wdata[33])); + (* SOFT_HLUTNM = "soft_lutpair67" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[34]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[34]), + .O(m_axi_wdata[34])); + (* SOFT_HLUTNM = "soft_lutpair66" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[35]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[35]), + .O(m_axi_wdata[35])); + (* SOFT_HLUTNM = "soft_lutpair66" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[36]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[36]), + .O(m_axi_wdata[36])); + (* SOFT_HLUTNM = "soft_lutpair65" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[37]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[37]), + .O(m_axi_wdata[37])); + (* SOFT_HLUTNM = "soft_lutpair65" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[38]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[38]), + .O(m_axi_wdata[38])); + (* SOFT_HLUTNM = "soft_lutpair64" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[39]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[39]), + .O(m_axi_wdata[39])); + (* SOFT_HLUTNM = "soft_lutpair82" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[3]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[3]), + .O(m_axi_wdata[3])); + (* SOFT_HLUTNM = "soft_lutpair64" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[40]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[40]), + .O(m_axi_wdata[40])); + (* SOFT_HLUTNM = "soft_lutpair63" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[41]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[41]), + .O(m_axi_wdata[41])); + (* SOFT_HLUTNM = "soft_lutpair63" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[42]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[42]), + .O(m_axi_wdata[42])); + (* SOFT_HLUTNM = "soft_lutpair62" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[43]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[43]), + .O(m_axi_wdata[43])); + (* SOFT_HLUTNM = "soft_lutpair62" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[44]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[44]), + .O(m_axi_wdata[44])); + (* SOFT_HLUTNM = "soft_lutpair61" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[45]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[45]), + .O(m_axi_wdata[45])); + (* SOFT_HLUTNM = "soft_lutpair61" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[46]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[46]), + .O(m_axi_wdata[46])); + (* SOFT_HLUTNM = "soft_lutpair60" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[47]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[47]), + .O(m_axi_wdata[47])); + (* SOFT_HLUTNM = "soft_lutpair60" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[48]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[48]), + .O(m_axi_wdata[48])); + (* SOFT_HLUTNM = "soft_lutpair59" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[49]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[49]), + .O(m_axi_wdata[49])); + (* SOFT_HLUTNM = "soft_lutpair82" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[4]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[4]), + .O(m_axi_wdata[4])); + (* SOFT_HLUTNM = "soft_lutpair59" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[50]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[50]), + .O(m_axi_wdata[50])); + (* SOFT_HLUTNM = "soft_lutpair58" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[51]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[51]), + .O(m_axi_wdata[51])); + (* SOFT_HLUTNM = "soft_lutpair58" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[52]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[52]), + .O(m_axi_wdata[52])); + (* SOFT_HLUTNM = "soft_lutpair57" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[53]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[53]), + .O(m_axi_wdata[53])); + (* SOFT_HLUTNM = "soft_lutpair57" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[54]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[54]), + .O(m_axi_wdata[54])); + (* SOFT_HLUTNM = "soft_lutpair56" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[55]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[55]), + .O(m_axi_wdata[55])); + (* SOFT_HLUTNM = "soft_lutpair56" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[56]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[56]), + .O(m_axi_wdata[56])); + (* SOFT_HLUTNM = "soft_lutpair55" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[57]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[57]), + .O(m_axi_wdata[57])); + (* SOFT_HLUTNM = "soft_lutpair55" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[58]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[58]), + .O(m_axi_wdata[58])); + (* SOFT_HLUTNM = "soft_lutpair54" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[59]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[59]), + .O(m_axi_wdata[59])); + (* SOFT_HLUTNM = "soft_lutpair81" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[5]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[5]), + .O(m_axi_wdata[5])); + (* SOFT_HLUTNM = "soft_lutpair54" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[60]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[60]), + .O(m_axi_wdata[60])); + (* SOFT_HLUTNM = "soft_lutpair53" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[61]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[61]), + .O(m_axi_wdata[61])); + (* SOFT_HLUTNM = "soft_lutpair53" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[62]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[62]), + .O(m_axi_wdata[62])); + (* SOFT_HLUTNM = "soft_lutpair52" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[63]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[63]), + .O(m_axi_wdata[63])); + (* SOFT_HLUTNM = "soft_lutpair81" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[6]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[6]), + .O(m_axi_wdata[6])); + (* SOFT_HLUTNM = "soft_lutpair80" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[7]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[7]), + .O(m_axi_wdata[7])); + (* SOFT_HLUTNM = "soft_lutpair80" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[8]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[8]), + .O(m_axi_wdata[8])); + (* SOFT_HLUTNM = "soft_lutpair79" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wdata[9]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wdata[9]), + .O(m_axi_wdata[9])); + (* SOFT_HLUTNM = "soft_lutpair84" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wlast[0]_INST_0 + (.I0(s_axi_wlast), + .I1(m_select_enc_1), + .O(m_axi_wlast)); + (* SOFT_HLUTNM = "soft_lutpair52" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wstrb[0]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wstrb[0]), + .O(m_axi_wstrb[0])); + (* SOFT_HLUTNM = "soft_lutpair51" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wstrb[1]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wstrb[1]), + .O(m_axi_wstrb[1])); + (* SOFT_HLUTNM = "soft_lutpair51" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wstrb[2]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wstrb[2]), + .O(m_axi_wstrb[2])); + (* SOFT_HLUTNM = "soft_lutpair50" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wstrb[3]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wstrb[3]), + .O(m_axi_wstrb[3])); + (* SOFT_HLUTNM = "soft_lutpair50" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wstrb[4]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wstrb[4]), + .O(m_axi_wstrb[4])); + (* SOFT_HLUTNM = "soft_lutpair49" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wstrb[5]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wstrb[5]), + .O(m_axi_wstrb[5])); + (* SOFT_HLUTNM = "soft_lutpair49" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wstrb[6]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wstrb[6]), + .O(m_axi_wstrb[6])); + (* SOFT_HLUTNM = "soft_lutpair48" *) + LUT2 #( + .INIT(4'h8)) + \m_axi_wstrb[7]_INST_0 + (.I0(m_select_enc_1), + .I1(s_axi_wstrb[7]), + .O(m_axi_wstrb[7])); + LUT5 #( + .INIT(32'h08000000)) + \m_axi_wvalid[0]_INST_0 + (.I0(m_avalid_0), + .I1(m_select_enc_1), + .I2(m_select_enc), + .I3(s_axi_wvalid), + .I4(m_avalid), + .O(m_axi_wvalid)); + LUT6 #( + .INIT(64'hE3E2232223222322)) + m_valid_i + (.I0(out[0]), + .I1(\gen_arbiter.m_valid_i_reg ), + .I2(\storage_data1_reg[0]_0 ), + .I3(out[1]), + .I4(out[2]), + .I5(m_valid_i_reg_0), + .O(m_valid_i_n_0)); + LUT6 #( + .INIT(64'h2000000000000000)) + m_valid_i_i_2__1 + (.I0(m_select_enc_1), + .I1(m_select_enc), + .I2(m_valid_i_reg_1), + .I3(s_axi_wlast), + .I4(m_axi_wready), + .I5(m_avalid_0), + .O(\storage_data1_reg[0]_0 )); + LUT3 #( + .INIT(8'h01)) + m_valid_i_i_3 + (.I0(fifoaddr[1]), + .I1(fifoaddr[0]), + .I2(fifoaddr[2]), + .O(m_valid_i_reg_0)); + FDRE m_valid_i_reg + (.C(aclk), + .CE(E), + .D(m_valid_i_n_0), + .Q(m_avalid_0), + .R(in1)); + (* SOFT_HLUTNM = "soft_lutpair48" *) + LUT4 #( + .INIT(16'h4000)) + \s_axi_wready[1]_INST_0_i_1 + (.I0(m_select_enc), + .I1(m_axi_wready), + .I2(m_select_enc_1), + .I3(m_avalid_0), + .O(s_ready_i_reg)); + FDRE \storage_data1_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\gen_srls[0].gen_rep[0].srl_nx1_n_1 ), + .Q(m_select_enc_1), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "axi_data_fifo_v2_1_10_axic_reg_srl_fifo" *) +module Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized1 + (m_valid_i_reg_0, + \gen_axi.s_axi_wready_i_reg , + \storage_data1_reg[0]_0 , + \gen_axi.s_axi_wready_i_reg_0 , + s_axi_wready, + s_ready_i_reg, + \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3] , + aa_wm_awgrant_enc, + aclk, + \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 , + sa_wm_awvalid, + \storage_data1_reg[0]_1 , + in1, + p_10_in, + \storage_data1_reg[0]_2 , + m_select_enc_0, + m_avalid_1, + s_axi_wlast, + s_axi_wvalid, + SR, + m_ready_d, + Q, + aa_sa_awvalid); + output [0:0]m_valid_i_reg_0; + output \gen_axi.s_axi_wready_i_reg ; + output \storage_data1_reg[0]_0 ; + output \gen_axi.s_axi_wready_i_reg_0 ; + output [0:0]s_axi_wready; + output s_ready_i_reg; + output [3:0]\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3] ; + input aa_wm_awgrant_enc; + input aclk; + input [2:0]\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 ; + input [0:0]sa_wm_awvalid; + input \storage_data1_reg[0]_1 ; + input in1; + input p_10_in; + input \storage_data1_reg[0]_2 ; + input m_select_enc_0; + input m_avalid_1; + input [0:0]s_axi_wlast; + input [0:0]s_axi_wvalid; + input [0:0]SR; + input [0:0]m_ready_d; + input [0:0]Q; + input aa_sa_awvalid; + + wire [0:0]Q; + wire [0:0]SR; + wire aa_sa_awvalid; + wire aa_wm_awgrant_enc; + wire aclk; + wire [1:0]fifoaddr; + wire \gen_axi.s_axi_wready_i_reg ; + wire \gen_axi.s_axi_wready_i_reg_0 ; + wire [3:0]\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3] ; + wire [2:0]\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 ; + wire \gen_rep[0].fifoaddr[0]_i_1_n_0 ; + wire \gen_rep[0].fifoaddr[1]_i_1_n_0 ; + wire \gen_srls[0].gen_rep[0].srl_nx1_n_0 ; + wire in1; + wire load_s1; + wire m_avalid_1; + wire [0:0]m_ready_d; + wire m_select_enc_0; + wire m_valid_i_i_3__0_n_0; + wire m_valid_i_n_0; + wire [0:0]m_valid_i_reg_0; + wire p_0_in3_out; + wire p_10_in; + wire [0:0]s_axi_wlast; + wire [0:0]s_axi_wready; + wire [0:0]s_axi_wvalid; + wire s_ready_i_reg; + wire [0:0]sa_wm_awvalid; + wire \storage_data1_reg[0]_0 ; + wire \storage_data1_reg[0]_1 ; + wire \storage_data1_reg[0]_2 ; + + LUT6 #( + .INIT(64'h1011111100000000)) + \FSM_onehot_state[0]_i_1 + (.I0(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 [0]), + .I1(\storage_data1_reg[0]_1 ), + .I2(m_ready_d), + .I3(Q), + .I4(aa_sa_awvalid), + .I5(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 [1]), + .O(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3] [0])); + LUT6 #( + .INIT(64'h0800080008FF0800)) + \FSM_onehot_state[1]_i_1 + (.I0(aa_sa_awvalid), + .I1(Q), + .I2(m_ready_d), + .I3(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 [0]), + .I4(p_0_in3_out), + .I5(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 [1]), + .O(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3] [1])); + LUT6 #( + .INIT(64'hBF00BF00BF00BFFF)) + \FSM_onehot_state[2]_i_1 + (.I0(m_ready_d), + .I1(Q), + .I2(aa_sa_awvalid), + .I3(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 [0]), + .I4(p_0_in3_out), + .I5(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 [1]), + .O(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3] [2])); + LUT5 #( + .INIT(32'h08000000)) + \FSM_onehot_state[2]_i_2__0 + (.I0(m_valid_i_i_3__0_n_0), + .I1(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 [2]), + .I2(sa_wm_awvalid), + .I3(p_10_in), + .I4(\gen_axi.s_axi_wready_i_reg_0 ), + .O(p_0_in3_out)); + LUT6 #( + .INIT(64'hCB8BCB88CB88CB88)) + \FSM_onehot_state[3]_i_1 + (.I0(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 [0]), + .I1(sa_wm_awvalid), + .I2(\storage_data1_reg[0]_1 ), + .I3(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 [1]), + .I4(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 [2]), + .I5(m_valid_i_i_3__0_n_0), + .O(m_valid_i_reg_0)); + LUT6 #( + .INIT(64'h000000008A888888)) + \FSM_onehot_state[3]_i_2 + (.I0(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 [1]), + .I1(\storage_data1_reg[0]_1 ), + .I2(m_ready_d), + .I3(Q), + .I4(aa_sa_awvalid), + .I5(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 [0]), + .O(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3] [3])); + LUT6 #( + .INIT(64'h8000000000000000)) + \gen_axi.write_cs[1]_i_2 + (.I0(\gen_axi.s_axi_wready_i_reg ), + .I1(\storage_data1_reg[0]_0 ), + .I2(s_axi_wlast), + .I3(m_select_enc_0), + .I4(s_axi_wvalid), + .I5(m_avalid_1), + .O(\gen_axi.s_axi_wready_i_reg_0 )); + LUT4 #( + .INIT(16'h8000)) + \gen_primitive_shifter.gen_srls[0].srl_inst_i_4 + (.I0(\gen_axi.s_axi_wready_i_reg ), + .I1(m_select_enc_0), + .I2(\storage_data1_reg[0]_0 ), + .I3(p_10_in), + .O(s_ready_i_reg)); + LUT5 #( + .INIT(32'h5A7FA580)) + \gen_rep[0].fifoaddr[0]_i_1 + (.I0(\storage_data1_reg[0]_1 ), + .I1(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 [1]), + .I2(sa_wm_awvalid), + .I3(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 [2]), + .I4(fifoaddr[0]), + .O(\gen_rep[0].fifoaddr[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h5F7FFBFBA0800404)) + \gen_rep[0].fifoaddr[1]_i_1 + (.I0(fifoaddr[0]), + .I1(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 [2]), + .I2(sa_wm_awvalid), + .I3(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 [1]), + .I4(\storage_data1_reg[0]_1 ), + .I5(fifoaddr[1]), + .O(\gen_rep[0].fifoaddr[1]_i_1_n_0 )); + (* syn_keep = "1" *) + FDSE \gen_rep[0].fifoaddr_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\gen_rep[0].fifoaddr[0]_i_1_n_0 ), + .Q(fifoaddr[0]), + .S(SR)); + (* syn_keep = "1" *) + FDSE \gen_rep[0].fifoaddr_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\gen_rep[0].fifoaddr[1]_i_1_n_0 ), + .Q(fifoaddr[1]), + .S(SR)); + Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_ndeep_srl_3 \gen_srls[0].gen_rep[0].srl_nx1 + (.A(fifoaddr), + .aa_wm_awgrant_enc(aa_wm_awgrant_enc), + .aclk(aclk), + .\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3] (\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 [2:1]), + .load_s1(load_s1), + .m_valid_i_reg(\gen_axi.s_axi_wready_i_reg_0 ), + .p_10_in(p_10_in), + .sa_wm_awvalid(sa_wm_awvalid), + .\storage_data1_reg[0] (\gen_srls[0].gen_rep[0].srl_nx1_n_0 ), + .\storage_data1_reg[0]_0 (\storage_data1_reg[0]_0 )); + LUT6 #( + .INIT(64'hCB8BC888C888C888)) + m_valid_i + (.I0(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 [0]), + .I1(sa_wm_awvalid), + .I2(\storage_data1_reg[0]_1 ), + .I3(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 [1]), + .I4(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 [2]), + .I5(m_valid_i_i_3__0_n_0), + .O(m_valid_i_n_0)); + LUT2 #( + .INIT(4'h1)) + m_valid_i_i_3__0 + (.I0(fifoaddr[0]), + .I1(fifoaddr[1]), + .O(m_valid_i_i_3__0_n_0)); + FDRE m_valid_i_reg + (.C(aclk), + .CE(m_valid_i_reg_0), + .D(m_valid_i_n_0), + .Q(\gen_axi.s_axi_wready_i_reg ), + .R(in1)); + LUT6 #( + .INIT(64'hEAAAAAAA00000000)) + \s_axi_wready[1]_INST_0 + (.I0(\storage_data1_reg[0]_2 ), + .I1(\gen_axi.s_axi_wready_i_reg ), + .I2(m_select_enc_0), + .I3(\storage_data1_reg[0]_0 ), + .I4(p_10_in), + .I5(m_avalid_1), + .O(s_axi_wready)); + LUT6 #( + .INIT(64'hFCCCA000ECCCA000)) + \storage_data1[0]_i_2 + (.I0(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 [2]), + .I1(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 [0]), + .I2(\gen_axi.s_axi_wready_i_reg_0 ), + .I3(p_10_in), + .I4(sa_wm_awvalid), + .I5(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0 [1]), + .O(load_s1)); + FDRE \storage_data1_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\gen_srls[0].gen_rep[0].srl_nx1_n_0 ), + .Q(\storage_data1_reg[0]_0 ), + .R(1'b0)); +endmodule + +module Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_ndeep_srl + (push, + \storage_data1_reg[0] , + s_ready_i_reg, + fifoaddr, + aclk, + out0, + \FSM_onehot_state_reg[0] , + m_aready__1, + m_select_enc, + s_axi_awaddr, + s_axi_wlast, + \storage_data1_reg[0]_0 , + m_valid_i_reg, + m_valid_i_reg_0, + s_axi_wvalid, + s_axi_awvalid, + m_ready_d, + s_ready_i_reg_0); + output push; + output \storage_data1_reg[0] ; + output s_ready_i_reg; + input [1:0]fifoaddr; + input aclk; + input [1:0]out0; + input \FSM_onehot_state_reg[0] ; + input m_aready__1; + input m_select_enc; + input [2:0]s_axi_awaddr; + input [0:0]s_axi_wlast; + input \storage_data1_reg[0]_0 ; + input m_valid_i_reg; + input m_valid_i_reg_0; + input [0:0]s_axi_wvalid; + input [0:0]s_axi_awvalid; + input [0:0]m_ready_d; + input s_ready_i_reg_0; + + wire \FSM_onehot_state_reg[0] ; + wire aclk; + wire [1:0]fifoaddr; + wire \gen_primitive_shifter.gen_srls[0].srl_inst_i_2_n_0 ; + wire \gen_primitive_shifter.gen_srls[0].srl_inst_i_5_n_0 ; + wire \gen_primitive_shifter.gen_srls[0].srl_inst_i_6_n_0 ; + wire m_aready__1; + wire [0:0]m_ready_d; + wire m_select_enc; + wire m_valid_i_reg; + wire m_valid_i_reg_0; + wire [1:0]out0; + wire push; + wire [2:0]s_axi_awaddr; + wire [0:0]s_axi_awvalid; + wire [0:0]s_axi_wlast; + wire [0:0]s_axi_wvalid; + wire s_ready_i_reg; + wire s_ready_i_reg_0; + wire \storage_data1[0]_i_2__0_n_0 ; + wire \storage_data1_reg[0] ; + wire \storage_data1_reg[0]_0 ; + wire storage_data2; + + (* BOX_TYPE = "PRIMITIVE" *) + (* XILINX_LEGACY_PRIM = "SRLC32E" *) + (* srl_bus_name = "inst/\gen_samd.crossbar_samd/gen_slave_slots[1].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls " *) + (* srl_name = "inst/\gen_samd.crossbar_samd/gen_slave_slots[1].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst " *) + SRL16E #( + .INIT(16'h0000), + .IS_CLK_INVERTED(1'b0)) + \gen_primitive_shifter.gen_srls[0].srl_inst + (.A0(fifoaddr[0]), + .A1(fifoaddr[1]), + .A2(1'b0), + .A3(1'b0), + .CE(push), + .CLK(aclk), + .D(\gen_primitive_shifter.gen_srls[0].srl_inst_i_2_n_0 ), + .Q(storage_data2)); + LUT6 #( + .INIT(64'hFFFFFFFF777F0000)) + \gen_primitive_shifter.gen_srls[0].srl_inst_i_1__0 + (.I0(s_axi_wlast), + .I1(s_ready_i_reg), + .I2(\storage_data1_reg[0]_0 ), + .I3(m_valid_i_reg), + .I4(\gen_primitive_shifter.gen_srls[0].srl_inst_i_5_n_0 ), + .I5(\gen_primitive_shifter.gen_srls[0].srl_inst_i_6_n_0 ), + .O(push)); + (* SOFT_HLUTNM = "soft_lutpair165" *) + LUT3 #( + .INIT(8'hFE)) + \gen_primitive_shifter.gen_srls[0].srl_inst_i_2 + (.I0(s_axi_awaddr[0]), + .I1(s_axi_awaddr[1]), + .I2(s_axi_awaddr[2]), + .O(\gen_primitive_shifter.gen_srls[0].srl_inst_i_2_n_0 )); + LUT2 #( + .INIT(4'h8)) + \gen_primitive_shifter.gen_srls[0].srl_inst_i_3 + (.I0(m_valid_i_reg_0), + .I1(s_axi_wvalid), + .O(s_ready_i_reg)); + (* SOFT_HLUTNM = "soft_lutpair166" *) + LUT3 #( + .INIT(8'h08)) + \gen_primitive_shifter.gen_srls[0].srl_inst_i_5 + (.I0(out0[1]), + .I1(s_axi_awvalid), + .I2(m_ready_d), + .O(\gen_primitive_shifter.gen_srls[0].srl_inst_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair166" *) + LUT4 #( + .INIT(16'h0080)) + \gen_primitive_shifter.gen_srls[0].srl_inst_i_6 + (.I0(s_ready_i_reg_0), + .I1(out0[0]), + .I2(s_axi_awvalid), + .I3(m_ready_d), + .O(\gen_primitive_shifter.gen_srls[0].srl_inst_i_6_n_0 )); + LUT6 #( + .INIT(64'hAAAFABAFAAA0A8A0)) + \storage_data1[0]_i_1 + (.I0(\storage_data1[0]_i_2__0_n_0 ), + .I1(out0[0]), + .I2(\FSM_onehot_state_reg[0] ), + .I3(m_aready__1), + .I4(\gen_primitive_shifter.gen_srls[0].srl_inst_i_5_n_0 ), + .I5(m_select_enc), + .O(\storage_data1_reg[0] )); + (* SOFT_HLUTNM = "soft_lutpair165" *) + LUT5 #( + .INIT(32'hBBBBBBB8)) + \storage_data1[0]_i_2__0 + (.I0(storage_data2), + .I1(out0[0]), + .I2(s_axi_awaddr[0]), + .I3(s_axi_awaddr[1]), + .I4(s_axi_awaddr[2]), + .O(\storage_data1[0]_i_2__0_n_0 )); +endmodule + +(* ORIG_REF_NAME = "axi_data_fifo_v2_1_10_ndeep_srl" *) +module Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_ndeep_srl_3 + (\storage_data1_reg[0] , + aa_wm_awgrant_enc, + A, + aclk, + \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3] , + load_s1, + \storage_data1_reg[0]_0 , + m_valid_i_reg, + p_10_in, + sa_wm_awvalid); + output \storage_data1_reg[0] ; + input aa_wm_awgrant_enc; + input [1:0]A; + input aclk; + input [1:0]\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3] ; + input load_s1; + input \storage_data1_reg[0]_0 ; + input m_valid_i_reg; + input p_10_in; + input [0:0]sa_wm_awvalid; + + wire [1:0]A; + wire aa_wm_awgrant_enc; + wire aclk; + wire [1:0]\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3] ; + wire load_s1; + wire m_valid_i_reg; + wire p_10_in; + wire push; + wire [0:0]sa_wm_awvalid; + wire \storage_data1_reg[0] ; + wire \storage_data1_reg[0]_0 ; + wire storage_data2; + + (* BOX_TYPE = "PRIMITIVE" *) + (* XILINX_LEGACY_PRIM = "SRLC32E" *) + (* srl_bus_name = "inst/\gen_samd.crossbar_samd/gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls " *) + (* srl_name = "inst/\gen_samd.crossbar_samd/gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst " *) + SRL16E #( + .INIT(16'h0000), + .IS_CLK_INVERTED(1'b0)) + \gen_primitive_shifter.gen_srls[0].srl_inst + (.A0(A[0]), + .A1(A[1]), + .A2(1'b0), + .A3(1'b0), + .CE(push), + .CLK(aclk), + .D(aa_wm_awgrant_enc), + .Q(storage_data2)); + LUT5 #( + .INIT(32'hFF007000)) + \gen_primitive_shifter.gen_srls[0].srl_inst_i_1 + (.I0(m_valid_i_reg), + .I1(p_10_in), + .I2(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3] [0]), + .I3(sa_wm_awvalid), + .I4(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3] [1]), + .O(push)); + LUT5 #( + .INIT(32'hB8FFB800)) + \storage_data1[0]_i_1__1 + (.I0(storage_data2), + .I1(\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3] [1]), + .I2(aa_wm_awgrant_enc), + .I3(load_s1), + .I4(\storage_data1_reg[0]_0 ), + .O(\storage_data1_reg[0] )); +endmodule + +(* ORIG_REF_NAME = "axi_data_fifo_v2_1_10_ndeep_srl" *) +module Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_ndeep_srl__parameterized8 + (push, + \storage_data1_reg[0] , + aa_wm_awgrant_enc, + A, + aclk, + out, + \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0] , + \storage_data1_reg[0]_0 , + \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1] , + m_select_enc_1, + m_valid_i_reg, + \gen_arbiter.m_valid_i_reg , + m_avalid_0, + m_axi_wready, + s_axi_wlast, + m_select_enc); + output push; + output \storage_data1_reg[0] ; + input aa_wm_awgrant_enc; + input [2:0]A; + input aclk; + input [1:0]out; + input \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0] ; + input \storage_data1_reg[0]_0 ; + input \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1] ; + input m_select_enc_1; + input m_valid_i_reg; + input \gen_arbiter.m_valid_i_reg ; + input m_avalid_0; + input [0:0]m_axi_wready; + input [0:0]s_axi_wlast; + input m_select_enc; + + wire [2:0]A; + wire aa_wm_awgrant_enc; + wire aclk; + wire \gen_arbiter.m_valid_i_reg ; + wire \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0] ; + wire \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1] ; + wire \gen_primitive_shifter.gen_srls[0].srl_inst_i_2__0_n_0 ; + wire \gen_primitive_shifter.gen_srls[0].srl_inst_i_3__0_n_0 ; + wire m_avalid_0; + wire [0:0]m_axi_wready; + wire m_select_enc; + wire m_select_enc_1; + wire m_valid_i_reg; + wire [1:0]out; + wire push; + wire [0:0]s_axi_wlast; + wire \storage_data1[0]_i_2__1_n_0 ; + wire \storage_data1_reg[0] ; + wire \storage_data1_reg[0]_0 ; + wire storage_data2; + + (* BOX_TYPE = "PRIMITIVE" *) + (* XILINX_LEGACY_PRIM = "SRLC32E" *) + (* srl_bus_name = "inst/\gen_samd.crossbar_samd/gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls " *) + (* srl_name = "inst/\gen_samd.crossbar_samd/gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst " *) + SRL16E #( + .INIT(16'h0000), + .IS_CLK_INVERTED(1'b0)) + \gen_primitive_shifter.gen_srls[0].srl_inst + (.A0(A[0]), + .A1(A[1]), + .A2(A[2]), + .A3(1'b0), + .CE(push), + .CLK(aclk), + .D(aa_wm_awgrant_enc), + .Q(storage_data2)); + LUT6 #( + .INIT(64'h0000FFFF00007F00)) + \gen_primitive_shifter.gen_srls[0].srl_inst_i_1__1 + (.I0(\gen_primitive_shifter.gen_srls[0].srl_inst_i_2__0_n_0 ), + .I1(m_valid_i_reg), + .I2(\gen_primitive_shifter.gen_srls[0].srl_inst_i_3__0_n_0 ), + .I3(out[0]), + .I4(\gen_arbiter.m_valid_i_reg ), + .I5(out[1]), + .O(push)); + LUT2 #( + .INIT(4'h2)) + \gen_primitive_shifter.gen_srls[0].srl_inst_i_2__0 + (.I0(m_select_enc_1), + .I1(m_select_enc), + .O(\gen_primitive_shifter.gen_srls[0].srl_inst_i_2__0_n_0 )); + LUT3 #( + .INIT(8'h80)) + \gen_primitive_shifter.gen_srls[0].srl_inst_i_3__0 + (.I0(m_avalid_0), + .I1(m_axi_wready), + .I2(s_axi_wlast), + .O(\gen_primitive_shifter.gen_srls[0].srl_inst_i_3__0_n_0 )); + LUT6 #( + .INIT(64'hAAAFABAFAAA0A8A0)) + \storage_data1[0]_i_1__0 + (.I0(\storage_data1[0]_i_2__1_n_0 ), + .I1(out[1]), + .I2(\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0] ), + .I3(\storage_data1_reg[0]_0 ), + .I4(\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1] ), + .I5(m_select_enc_1), + .O(\storage_data1_reg[0] )); + LUT3 #( + .INIT(8'hB8)) + \storage_data1[0]_i_2__1 + (.I0(storage_data2), + .I1(out[1]), + .I2(aa_wm_awgrant_enc), + .O(\storage_data1[0]_i_2__1_n_0 )); +endmodule + +module Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axi_register_slice + (p_58_out, + m_valid_i_reg, + m_axi_bready, + p_1_in, + p_52_out, + \m_axi_rready[0] , + s_ready_i_reg, + p_61_out, + s_axi_rdata, + Q, + \gen_master_slots[0].w_issuing_cnt_reg[0] , + \gen_arbiter.qual_reg_reg[0] , + D, + \gen_master_slots[0].r_issuing_cnt_reg[0] , + s_axi_bresp, + aclk, + aresetn, + s_axi_bready, + active_target_hot, + m_axi_bvalid, + active_target_hot_0, + s_axi_rready, + m_axi_rvalid, + active_target_enc, + p_30_out, + \gen_master_slots[0].r_issuing_cnt_reg[3] , + \gen_arbiter.m_valid_i_reg , + active_target_enc_1, + m_axi_rlast, + m_axi_rresp, + m_axi_rdata, + m_axi_bid, + m_axi_bresp, + E); + output p_58_out; + output m_valid_i_reg; + output [0:0]m_axi_bready; + output p_1_in; + output p_52_out; + output \m_axi_rready[0] ; + output s_ready_i_reg; + output p_61_out; + output [63:0]s_axi_rdata; + output [2:0]Q; + output \gen_master_slots[0].w_issuing_cnt_reg[0] ; + output \gen_arbiter.qual_reg_reg[0] ; + output [2:0]D; + output \gen_master_slots[0].r_issuing_cnt_reg[0] ; + output [1:0]s_axi_bresp; + input aclk; + input aresetn; + input [0:0]s_axi_bready; + input [0:0]active_target_hot; + input [0:0]m_axi_bvalid; + input [0:0]active_target_hot_0; + input [0:0]s_axi_rready; + input [0:0]m_axi_rvalid; + input active_target_enc; + input p_30_out; + input [3:0]\gen_master_slots[0].r_issuing_cnt_reg[3] ; + input \gen_arbiter.m_valid_i_reg ; + input active_target_enc_1; + input [0:0]m_axi_rlast; + input [1:0]m_axi_rresp; + input [63:0]m_axi_rdata; + input [0:0]m_axi_bid; + input [1:0]m_axi_bresp; + input [0:0]E; + + wire [2:0]D; + wire [0:0]E; + wire [2:0]Q; + wire aclk; + wire active_target_enc; + wire active_target_enc_1; + wire [0:0]active_target_hot; + wire [0:0]active_target_hot_0; + wire aresetn; + wire \gen_arbiter.m_valid_i_reg ; + wire \gen_arbiter.qual_reg_reg[0] ; + wire \gen_master_slots[0].r_issuing_cnt_reg[0] ; + wire [3:0]\gen_master_slots[0].r_issuing_cnt_reg[3] ; + wire \gen_master_slots[0].w_issuing_cnt_reg[0] ; + wire [0:0]m_axi_bid; + wire [0:0]m_axi_bready; + wire [1:0]m_axi_bresp; + wire [0:0]m_axi_bvalid; + wire [63:0]m_axi_rdata; + wire [0:0]m_axi_rlast; + wire \m_axi_rready[0] ; + wire [1:0]m_axi_rresp; + wire [0:0]m_axi_rvalid; + wire m_valid_i_reg; + wire p_1_in; + wire p_30_out; + wire p_52_out; + wire p_58_out; + wire p_61_out; + wire [0:0]s_axi_bready; + wire [1:0]s_axi_bresp; + wire [63:0]s_axi_rdata; + wire [0:0]s_axi_rready; + wire s_ready_i_reg; + + Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized1_4 b_pipe + (.aclk(aclk), + .active_target_enc_1(active_target_enc_1), + .active_target_hot(active_target_hot), + .aresetn(aresetn), + .\gen_master_slots[0].w_issuing_cnt_reg[0] (\gen_master_slots[0].w_issuing_cnt_reg[0] ), + .m_axi_bid(m_axi_bid), + .m_axi_bready(m_axi_bready), + .m_axi_bresp(m_axi_bresp), + .m_axi_bvalid(m_axi_bvalid), + .m_valid_i_reg_0(m_valid_i_reg), + .p_1_in(p_1_in), + .s_axi_bready(s_axi_bready), + .s_axi_bresp(s_axi_bresp), + .s_ready_i_reg_0(p_58_out), + .s_ready_i_reg_1(s_ready_i_reg), + .s_ready_i_reg_2(p_61_out)); + Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2_5 r_pipe + (.D(D), + .E(E), + .Q(Q), + .aclk(aclk), + .active_target_enc(active_target_enc), + .active_target_hot_0(active_target_hot_0), + .\aresetn_d_reg[1] (m_valid_i_reg), + .\gen_arbiter.m_valid_i_reg (\gen_arbiter.m_valid_i_reg ), + .\gen_arbiter.qual_reg_reg[0] (\gen_arbiter.qual_reg_reg[0] ), + .\gen_master_slots[0].r_issuing_cnt_reg[0] (\gen_master_slots[0].r_issuing_cnt_reg[0] ), + .\gen_master_slots[0].r_issuing_cnt_reg[3] (\gen_master_slots[0].r_issuing_cnt_reg[3] ), + .m_axi_rdata(m_axi_rdata), + .m_axi_rlast(m_axi_rlast), + .\m_axi_rready[0] (\m_axi_rready[0] ), + .m_axi_rresp(m_axi_rresp), + .m_axi_rvalid(m_axi_rvalid), + .m_valid_i_reg_0(p_52_out), + .p_1_in(p_1_in), + .p_30_out(p_30_out), + .s_axi_rdata(s_axi_rdata), + .s_axi_rready(s_axi_rready)); +endmodule + +(* ORIG_REF_NAME = "axi_register_slice_v2_1_11_axi_register_slice" *) +module Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axi_register_slice_1 + (mi_bready_1, + p_28_out, + mi_rready_1, + \gen_master_slots[1].w_issuing_cnt_reg[8] , + \gen_master_slots[1].r_issuing_cnt_reg[8] , + p_30_out, + \s_axi_bvalid[1] , + valid_qual_i111_in, + \gen_arbiter.qual_reg_reg[0] , + valid_qual_i1__0, + \gen_arbiter.qual_reg_reg[0]_0 , + s_axi_rlast, + s_axi_rresp, + \aresetn_d_reg[1] , + aclk, + p_1_in, + p_20_in, + s_axi_bready, + active_target_enc, + \gen_axi.s_axi_awready_i_reg , + w_issuing_cnt, + active_target_enc_0, + s_axi_rready, + \gen_arbiter.m_valid_i_reg , + r_issuing_cnt, + p_17_in, + \aresetn_d_reg[1]_0 , + p_11_in, + p_61_out, + p_58_out, + active_target_hot, + \gen_master_slots[0].w_issuing_cnt_reg[2] , + sel_4, + \gen_single_thread.active_target_hot_reg[0] , + st_aa_arvalid_qual, + s_axi_arvalid, + \gen_master_slots[0].r_issuing_cnt_reg[2] , + \s_axi_araddr[29] , + m_valid_i_reg, + Q, + p_13_in, + p_1_in_1); + output mi_bready_1; + output p_28_out; + output mi_rready_1; + output \gen_master_slots[1].w_issuing_cnt_reg[8] ; + output \gen_master_slots[1].r_issuing_cnt_reg[8] ; + output p_30_out; + output \s_axi_bvalid[1] ; + output valid_qual_i111_in; + output \gen_arbiter.qual_reg_reg[0] ; + output valid_qual_i1__0; + output \gen_arbiter.qual_reg_reg[0]_0 ; + output [0:0]s_axi_rlast; + output [1:0]s_axi_rresp; + input \aresetn_d_reg[1] ; + input aclk; + input p_1_in; + input p_20_in; + input [0:0]s_axi_bready; + input active_target_enc; + input \gen_axi.s_axi_awready_i_reg ; + input [1:0]w_issuing_cnt; + input active_target_enc_0; + input [0:0]s_axi_rready; + input \gen_arbiter.m_valid_i_reg ; + input [1:0]r_issuing_cnt; + input p_17_in; + input \aresetn_d_reg[1]_0 ; + input p_11_in; + input p_61_out; + input p_58_out; + input [0:0]active_target_hot; + input \gen_master_slots[0].w_issuing_cnt_reg[2] ; + input sel_4; + input \gen_single_thread.active_target_hot_reg[0] ; + input [0:0]st_aa_arvalid_qual; + input [0:0]s_axi_arvalid; + input \gen_master_slots[0].r_issuing_cnt_reg[2] ; + input [0:0]\s_axi_araddr[29] ; + input m_valid_i_reg; + input [2:0]Q; + input p_13_in; + input p_1_in_1; + + wire [2:0]Q; + wire aclk; + wire active_target_enc; + wire active_target_enc_0; + wire [0:0]active_target_hot; + wire \aresetn_d_reg[1] ; + wire \aresetn_d_reg[1]_0 ; + wire \gen_arbiter.m_valid_i_reg ; + wire \gen_arbiter.qual_reg_reg[0] ; + wire \gen_arbiter.qual_reg_reg[0]_0 ; + wire \gen_axi.s_axi_awready_i_reg ; + wire \gen_master_slots[0].r_issuing_cnt_reg[2] ; + wire \gen_master_slots[0].w_issuing_cnt_reg[2] ; + wire \gen_master_slots[1].r_issuing_cnt_reg[8] ; + wire \gen_master_slots[1].w_issuing_cnt_reg[8] ; + wire \gen_single_thread.active_target_hot_reg[0] ; + wire m_valid_i_reg; + wire mi_bready_1; + wire mi_rready_1; + wire p_11_in; + wire p_13_in; + wire p_17_in; + wire p_1_in; + wire p_1_in_1; + wire p_20_in; + wire p_28_out; + wire p_30_out; + wire p_58_out; + wire p_61_out; + wire [1:0]r_issuing_cnt; + wire [0:0]\s_axi_araddr[29] ; + wire [0:0]s_axi_arvalid; + wire [0:0]s_axi_bready; + wire \s_axi_bvalid[1] ; + wire [0:0]s_axi_rlast; + wire [0:0]s_axi_rready; + wire [1:0]s_axi_rresp; + wire sel_4; + wire [0:0]st_aa_arvalid_qual; + wire valid_qual_i111_in; + wire valid_qual_i1__0; + wire [1:0]w_issuing_cnt; + + Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized1 b_pipe + (.aclk(aclk), + .active_target_enc(active_target_enc), + .active_target_hot(active_target_hot), + .\aresetn_d_reg[1] (\aresetn_d_reg[1] ), + .\aresetn_d_reg[1]_0 (\aresetn_d_reg[1]_0 ), + .\gen_axi.s_axi_awready_i_reg (\gen_axi.s_axi_awready_i_reg ), + .\gen_master_slots[0].w_issuing_cnt_reg[2] (\gen_master_slots[0].w_issuing_cnt_reg[2] ), + .\gen_master_slots[1].w_issuing_cnt_reg[8] (\gen_master_slots[1].w_issuing_cnt_reg[8] ), + .\gen_single_thread.active_target_hot_reg[0] (\gen_single_thread.active_target_hot_reg[0] ), + .mi_bready_1(mi_bready_1), + .p_17_in(p_17_in), + .p_1_in(p_1_in), + .p_20_in(p_20_in), + .p_58_out(p_58_out), + .p_61_out(p_61_out), + .s_axi_bready(s_axi_bready), + .\s_axi_bvalid[1] (\s_axi_bvalid[1] ), + .sel_4(sel_4), + .valid_qual_i111_in(valid_qual_i111_in), + .w_issuing_cnt(w_issuing_cnt)); + Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2 r_pipe + (.Q(Q), + .aclk(aclk), + .active_target_enc_0(active_target_enc_0), + .\aresetn_d_reg[1] (\aresetn_d_reg[1] ), + .\gen_arbiter.m_valid_i_reg (\gen_arbiter.m_valid_i_reg ), + .\gen_arbiter.qual_reg_reg[0] (\gen_arbiter.qual_reg_reg[0] ), + .\gen_arbiter.qual_reg_reg[0]_0 (\gen_arbiter.qual_reg_reg[0]_0 ), + .\gen_master_slots[0].r_issuing_cnt_reg[2] (\gen_master_slots[0].r_issuing_cnt_reg[2] ), + .\gen_master_slots[1].r_issuing_cnt_reg[8] (\gen_master_slots[1].r_issuing_cnt_reg[8] ), + .\gen_master_slots[1].r_issuing_cnt_reg[8]_0 (p_30_out), + .m_valid_i_reg_0(p_28_out), + .m_valid_i_reg_1(m_valid_i_reg), + .p_11_in(p_11_in), + .p_13_in(p_13_in), + .p_1_in(p_1_in), + .p_1_in_1(p_1_in_1), + .r_issuing_cnt(r_issuing_cnt), + .\s_axi_araddr[29] (\s_axi_araddr[29] ), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_rlast(s_axi_rlast), + .s_axi_rready(s_axi_rready), + .s_axi_rresp(s_axi_rresp), + .\skid_buffer_reg[64]_0 (mi_rready_1), + .st_aa_arvalid_qual(st_aa_arvalid_qual), + .valid_qual_i1__0(valid_qual_i1__0)); +endmodule + +(* ORIG_REF_NAME = "axi_register_slice_v2_1_11_axic_register_slice" *) +module Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized1 + (mi_bready_1, + \gen_master_slots[1].w_issuing_cnt_reg[8] , + \s_axi_bvalid[1] , + valid_qual_i111_in, + \aresetn_d_reg[1] , + aclk, + p_1_in, + p_20_in, + s_axi_bready, + active_target_enc, + \gen_axi.s_axi_awready_i_reg , + w_issuing_cnt, + p_17_in, + \aresetn_d_reg[1]_0 , + p_61_out, + p_58_out, + active_target_hot, + \gen_master_slots[0].w_issuing_cnt_reg[2] , + sel_4, + \gen_single_thread.active_target_hot_reg[0] ); + output mi_bready_1; + output \gen_master_slots[1].w_issuing_cnt_reg[8] ; + output \s_axi_bvalid[1] ; + output valid_qual_i111_in; + input \aresetn_d_reg[1] ; + input aclk; + input p_1_in; + input p_20_in; + input [0:0]s_axi_bready; + input active_target_enc; + input \gen_axi.s_axi_awready_i_reg ; + input [1:0]w_issuing_cnt; + input p_17_in; + input \aresetn_d_reg[1]_0 ; + input p_61_out; + input p_58_out; + input [0:0]active_target_hot; + input \gen_master_slots[0].w_issuing_cnt_reg[2] ; + input sel_4; + input \gen_single_thread.active_target_hot_reg[0] ; + + wire aclk; + wire active_target_enc; + wire [0:0]active_target_hot; + wire \aresetn_d_reg[1] ; + wire \aresetn_d_reg[1]_0 ; + wire \gen_arbiter.m_grant_enc_i[0]_i_6_n_0 ; + wire \gen_axi.s_axi_awready_i_reg ; + wire \gen_master_slots[0].w_issuing_cnt_reg[2] ; + wire \gen_master_slots[1].w_issuing_cnt_reg[8] ; + wire \gen_single_thread.active_target_hot_reg[0] ; + wire \m_payload_i[2]_i_1__0_n_0 ; + wire m_valid_i_i_1__0_n_0; + wire mi_bready_1; + wire p_17_in; + wire p_1_in; + wire p_20_in; + wire p_34_out; + wire p_37_out; + wire p_58_out; + wire p_61_out; + wire [0:0]s_axi_bready; + wire \s_axi_bvalid[1] ; + wire s_ready_i_i_1__1_n_0; + wire sel_4; + wire valid_qual_i111_in; + wire [1:0]w_issuing_cnt; + + LUT6 #( + .INIT(64'hAA3FFF3FFF3FFF3F)) + \gen_arbiter.m_grant_enc_i[0]_i_3 + (.I0(\gen_master_slots[0].w_issuing_cnt_reg[2] ), + .I1(\gen_arbiter.m_grant_enc_i[0]_i_6_n_0 ), + .I2(w_issuing_cnt[1]), + .I3(sel_4), + .I4(w_issuing_cnt[0]), + .I5(\gen_single_thread.active_target_hot_reg[0] ), + .O(valid_qual_i111_in)); + (* SOFT_HLUTNM = "soft_lutpair155" *) + LUT4 #( + .INIT(16'h7FFF)) + \gen_arbiter.m_grant_enc_i[0]_i_6 + (.I0(p_37_out), + .I1(active_target_enc), + .I2(s_axi_bready), + .I3(p_34_out), + .O(\gen_arbiter.m_grant_enc_i[0]_i_6_n_0 )); + LUT6 #( + .INIT(64'h7FFF800000007FFF)) + \gen_master_slots[1].w_issuing_cnt[8]_i_1 + (.I0(p_34_out), + .I1(s_axi_bready), + .I2(active_target_enc), + .I3(p_37_out), + .I4(\gen_axi.s_axi_awready_i_reg ), + .I5(w_issuing_cnt[1]), + .O(\gen_master_slots[1].w_issuing_cnt_reg[8] )); + (* SOFT_HLUTNM = "soft_lutpair155" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[2]_i_1__0 + (.I0(p_37_out), + .I1(p_34_out), + .I2(p_20_in), + .O(\m_payload_i[2]_i_1__0_n_0 )); + FDRE \m_payload_i_reg[2] + (.C(aclk), + .CE(1'b1), + .D(\m_payload_i[2]_i_1__0_n_0 ), + .Q(p_37_out), + .R(1'b0)); + LUT5 #( + .INIT(32'h8BBBBBBB)) + m_valid_i_i_1__0 + (.I0(p_17_in), + .I1(mi_bready_1), + .I2(s_axi_bready), + .I3(active_target_enc), + .I4(p_37_out), + .O(m_valid_i_i_1__0_n_0)); + FDRE m_valid_i_reg + (.C(aclk), + .CE(1'b1), + .D(m_valid_i_i_1__0_n_0), + .Q(p_34_out), + .R(\aresetn_d_reg[1] )); + LUT6 #( + .INIT(64'hFF80808080808080)) + \s_axi_bvalid[1]_INST_0 + (.I0(p_37_out), + .I1(p_34_out), + .I2(active_target_enc), + .I3(p_61_out), + .I4(p_58_out), + .I5(active_target_hot), + .O(\s_axi_bvalid[1] )); + LUT6 #( + .INIT(64'h800080FFFFFFFFFF)) + s_ready_i_i_1__1 + (.I0(p_37_out), + .I1(active_target_enc), + .I2(s_axi_bready), + .I3(p_34_out), + .I4(p_17_in), + .I5(\aresetn_d_reg[1]_0 ), + .O(s_ready_i_i_1__1_n_0)); + FDRE s_ready_i_reg + (.C(aclk), + .CE(1'b1), + .D(s_ready_i_i_1__1_n_0), + .Q(mi_bready_1), + .R(p_1_in)); +endmodule + +(* ORIG_REF_NAME = "axi_register_slice_v2_1_11_axic_register_slice" *) +module Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized1_4 + (s_ready_i_reg_0, + m_valid_i_reg_0, + m_axi_bready, + p_1_in, + s_ready_i_reg_1, + s_ready_i_reg_2, + \gen_master_slots[0].w_issuing_cnt_reg[0] , + s_axi_bresp, + aclk, + aresetn, + s_axi_bready, + active_target_hot, + m_axi_bvalid, + active_target_enc_1, + m_axi_bid, + m_axi_bresp); + output s_ready_i_reg_0; + output m_valid_i_reg_0; + output [0:0]m_axi_bready; + output p_1_in; + output s_ready_i_reg_1; + output s_ready_i_reg_2; + output \gen_master_slots[0].w_issuing_cnt_reg[0] ; + output [1:0]s_axi_bresp; + input aclk; + input aresetn; + input [0:0]s_axi_bready; + input [0:0]active_target_hot; + input [0:0]m_axi_bvalid; + input active_target_enc_1; + input [0:0]m_axi_bid; + input [1:0]m_axi_bresp; + + wire aclk; + wire active_target_enc_1; + wire [0:0]active_target_hot; + wire aresetn; + wire \aresetn_d[1]_i_1_n_0 ; + wire \gen_master_slots[0].w_issuing_cnt_reg[0] ; + wire [0:0]m_axi_bid; + wire [0:0]m_axi_bready; + wire [1:0]m_axi_bresp; + wire [0:0]m_axi_bvalid; + wire \m_payload_i[0]_i_1_n_0 ; + wire \m_payload_i[1]_i_1_n_0 ; + wire \m_payload_i[2]_i_1_n_0 ; + wire m_valid_i_i_2_n_0; + wire m_valid_i_reg_0; + wire [1:1]p_0_in; + wire p_1_in; + wire [0:0]s_axi_bready; + wire [1:0]s_axi_bresp; + wire s_ready_i_i_2_n_0; + wire s_ready_i_reg_0; + wire s_ready_i_reg_1; + wire s_ready_i_reg_2; + wire [1:0]st_mr_bmesg; + + LUT2 #( + .INIT(4'h8)) + \aresetn_d[1]_i_1 + (.I0(p_0_in), + .I1(aresetn), + .O(\aresetn_d[1]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \aresetn_d_reg[0] + (.C(aclk), + .CE(1'b1), + .D(aresetn), + .Q(p_0_in), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \aresetn_d_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\aresetn_d[1]_i_1_n_0 ), + .Q(s_ready_i_reg_1), + .R(1'b0)); + (* SOFT_HLUTNM = "soft_lutpair85" *) + LUT4 #( + .INIT(16'h7FFF)) + \gen_master_slots[0].w_issuing_cnt[3]_i_4 + (.I0(s_axi_bready), + .I1(active_target_hot), + .I2(s_ready_i_reg_2), + .I3(s_ready_i_reg_0), + .O(\gen_master_slots[0].w_issuing_cnt_reg[0] )); + (* SOFT_HLUTNM = "soft_lutpair86" *) + LUT3 #( + .INIT(8'hE2)) + \m_payload_i[0]_i_1 + (.I0(m_axi_bresp[0]), + .I1(s_ready_i_reg_0), + .I2(st_mr_bmesg[0]), + .O(\m_payload_i[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair86" *) + LUT3 #( + .INIT(8'hE2)) + \m_payload_i[1]_i_1 + (.I0(m_axi_bresp[1]), + .I1(s_ready_i_reg_0), + .I2(st_mr_bmesg[1]), + .O(\m_payload_i[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair85" *) + LUT3 #( + .INIT(8'hE2)) + \m_payload_i[2]_i_1 + (.I0(m_axi_bid), + .I1(s_ready_i_reg_0), + .I2(s_ready_i_reg_2), + .O(\m_payload_i[2]_i_1_n_0 )); + FDRE \m_payload_i_reg[0] + (.C(aclk), + .CE(1'b1), + .D(\m_payload_i[0]_i_1_n_0 ), + .Q(st_mr_bmesg[0]), + .R(1'b0)); + FDRE \m_payload_i_reg[1] + (.C(aclk), + .CE(1'b1), + .D(\m_payload_i[1]_i_1_n_0 ), + .Q(st_mr_bmesg[1]), + .R(1'b0)); + FDRE \m_payload_i_reg[2] + (.C(aclk), + .CE(1'b1), + .D(\m_payload_i[2]_i_1_n_0 ), + .Q(s_ready_i_reg_2), + .R(1'b0)); + LUT1 #( + .INIT(2'h1)) + m_valid_i_i_1__4 + (.I0(s_ready_i_reg_1), + .O(m_valid_i_reg_0)); + LUT5 #( + .INIT(32'h8BBBBBBB)) + m_valid_i_i_2 + (.I0(m_axi_bvalid), + .I1(m_axi_bready), + .I2(s_ready_i_reg_2), + .I3(active_target_hot), + .I4(s_axi_bready), + .O(m_valid_i_i_2_n_0)); + FDRE m_valid_i_reg + (.C(aclk), + .CE(1'b1), + .D(m_valid_i_i_2_n_0), + .Q(s_ready_i_reg_0), + .R(m_valid_i_reg_0)); + (* SOFT_HLUTNM = "soft_lutpair87" *) + LUT2 #( + .INIT(4'hE)) + \s_axi_bresp[2]_INST_0 + (.I0(st_mr_bmesg[0]), + .I1(active_target_enc_1), + .O(s_axi_bresp[0])); + (* SOFT_HLUTNM = "soft_lutpair87" *) + LUT2 #( + .INIT(4'hE)) + \s_axi_bresp[3]_INST_0 + (.I0(st_mr_bmesg[1]), + .I1(active_target_enc_1), + .O(s_axi_bresp[1])); + LUT1 #( + .INIT(2'h1)) + s_ready_i_i_1__0 + (.I0(p_0_in), + .O(p_1_in)); + LUT6 #( + .INIT(64'h800080FFFFFFFFFF)) + s_ready_i_i_2 + (.I0(s_axi_bready), + .I1(active_target_hot), + .I2(s_ready_i_reg_2), + .I3(s_ready_i_reg_0), + .I4(m_axi_bvalid), + .I5(s_ready_i_reg_1), + .O(s_ready_i_i_2_n_0)); + FDRE s_ready_i_reg + (.C(aclk), + .CE(1'b1), + .D(s_ready_i_i_2_n_0), + .Q(m_axi_bready), + .R(p_1_in)); +endmodule + +(* ORIG_REF_NAME = "axi_register_slice_v2_1_11_axic_register_slice" *) +module Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2 + (m_valid_i_reg_0, + \skid_buffer_reg[64]_0 , + \gen_master_slots[1].r_issuing_cnt_reg[8] , + \gen_master_slots[1].r_issuing_cnt_reg[8]_0 , + \gen_arbiter.qual_reg_reg[0] , + valid_qual_i1__0, + \gen_arbiter.qual_reg_reg[0]_0 , + s_axi_rlast, + s_axi_rresp, + \aresetn_d_reg[1] , + aclk, + p_1_in, + active_target_enc_0, + s_axi_rready, + \gen_arbiter.m_valid_i_reg , + r_issuing_cnt, + p_11_in, + st_aa_arvalid_qual, + s_axi_arvalid, + \gen_master_slots[0].r_issuing_cnt_reg[2] , + \s_axi_araddr[29] , + m_valid_i_reg_1, + Q, + p_13_in, + p_1_in_1); + output m_valid_i_reg_0; + output \skid_buffer_reg[64]_0 ; + output \gen_master_slots[1].r_issuing_cnt_reg[8] ; + output \gen_master_slots[1].r_issuing_cnt_reg[8]_0 ; + output \gen_arbiter.qual_reg_reg[0] ; + output valid_qual_i1__0; + output \gen_arbiter.qual_reg_reg[0]_0 ; + output [0:0]s_axi_rlast; + output [1:0]s_axi_rresp; + input \aresetn_d_reg[1] ; + input aclk; + input p_1_in; + input active_target_enc_0; + input [0:0]s_axi_rready; + input \gen_arbiter.m_valid_i_reg ; + input [1:0]r_issuing_cnt; + input p_11_in; + input [0:0]st_aa_arvalid_qual; + input [0:0]s_axi_arvalid; + input \gen_master_slots[0].r_issuing_cnt_reg[2] ; + input [0:0]\s_axi_araddr[29] ; + input m_valid_i_reg_1; + input [2:0]Q; + input p_13_in; + input p_1_in_1; + + wire [2:0]Q; + wire aclk; + wire active_target_enc_0; + wire \aresetn_d_reg[1] ; + wire \gen_arbiter.m_valid_i_reg ; + wire \gen_arbiter.qual_reg_reg[0] ; + wire \gen_arbiter.qual_reg_reg[0]_0 ; + wire \gen_master_slots[0].r_issuing_cnt_reg[2] ; + wire \gen_master_slots[1].r_issuing_cnt_reg[8] ; + wire \gen_master_slots[1].r_issuing_cnt_reg[8]_0 ; + wire \m_payload_i[64]_i_1_n_0 ; + wire \m_payload_i[65]_i_1_n_0 ; + wire \m_payload_i[66]_i_1_n_0 ; + wire m_valid_i0; + wire m_valid_i_reg_0; + wire m_valid_i_reg_1; + wire p_11_in; + wire p_13_in; + wire p_1_in; + wire p_1_in_1; + wire [1:0]r_issuing_cnt; + wire [0:0]\s_axi_araddr[29] ; + wire [0:0]s_axi_arvalid; + wire [0:0]s_axi_rlast; + wire [0:0]s_axi_rready; + wire [1:0]s_axi_rresp; + wire s_ready_i_i_1__3_n_0; + wire [66:64]skid_buffer; + wire \skid_buffer_reg[64]_0 ; + wire \skid_buffer_reg_n_0_[64] ; + wire \skid_buffer_reg_n_0_[65] ; + wire \skid_buffer_reg_n_0_[66] ; + wire [0:0]st_aa_arvalid_qual; + wire [68:67]st_mr_rmesg; + wire valid_qual_i1__0; + + LUT3 #( + .INIT(8'h8F)) + \gen_arbiter.qual_reg[0]_i_1 + (.I0(valid_qual_i1__0), + .I1(st_aa_arvalid_qual), + .I2(s_axi_arvalid), + .O(\gen_arbiter.qual_reg_reg[0] )); + LUT6 #( + .INIT(64'hBBBB0FFFFFFF0FFF)) + \gen_arbiter.qual_reg[0]_i_2 + (.I0(\gen_master_slots[0].r_issuing_cnt_reg[2] ), + .I1(r_issuing_cnt[0]), + .I2(r_issuing_cnt[1]), + .I3(\gen_arbiter.qual_reg_reg[0]_0 ), + .I4(\s_axi_araddr[29] ), + .I5(m_valid_i_reg_1), + .O(valid_qual_i1__0)); + (* SOFT_HLUTNM = "soft_lutpair157" *) + LUT4 #( + .INIT(16'h7FFF)) + \gen_arbiter.qual_reg[0]_i_5 + (.I0(m_valid_i_reg_0), + .I1(\gen_master_slots[1].r_issuing_cnt_reg[8]_0 ), + .I2(s_axi_rready), + .I3(active_target_enc_0), + .O(\gen_arbiter.qual_reg_reg[0]_0 )); + LUT6 #( + .INIT(64'h7FFF800000007FFF)) + \gen_master_slots[1].r_issuing_cnt[8]_i_1 + (.I0(active_target_enc_0), + .I1(s_axi_rready), + .I2(\gen_master_slots[1].r_issuing_cnt_reg[8]_0 ), + .I3(m_valid_i_reg_0), + .I4(\gen_arbiter.m_valid_i_reg ), + .I5(r_issuing_cnt[1]), + .O(\gen_master_slots[1].r_issuing_cnt_reg[8] )); + LUT6 #( + .INIT(64'hEFFFEEEEE000EEEE)) + \m_payload_i[64]_i_1 + (.I0(\skid_buffer_reg[64]_0 ), + .I1(\skid_buffer_reg_n_0_[64] ), + .I2(s_axi_rready), + .I3(active_target_enc_0), + .I4(m_valid_i_reg_0), + .I5(st_mr_rmesg[67]), + .O(\m_payload_i[64]_i_1_n_0 )); + LUT6 #( + .INIT(64'hEFFFEEEEE000EEEE)) + \m_payload_i[65]_i_1 + (.I0(\skid_buffer_reg_n_0_[65] ), + .I1(\skid_buffer_reg[64]_0 ), + .I2(s_axi_rready), + .I3(active_target_enc_0), + .I4(m_valid_i_reg_0), + .I5(st_mr_rmesg[68]), + .O(\m_payload_i[65]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair156" *) + LUT5 #( + .INIT(32'hB8FFB800)) + \m_payload_i[66]_i_1 + (.I0(p_13_in), + .I1(\skid_buffer_reg[64]_0 ), + .I2(\skid_buffer_reg_n_0_[66] ), + .I3(p_1_in_1), + .I4(\gen_master_slots[1].r_issuing_cnt_reg[8]_0 ), + .O(\m_payload_i[66]_i_1_n_0 )); + FDRE \m_payload_i_reg[64] + (.C(aclk), + .CE(1'b1), + .D(\m_payload_i[64]_i_1_n_0 ), + .Q(st_mr_rmesg[67]), + .R(1'b0)); + FDRE \m_payload_i_reg[65] + (.C(aclk), + .CE(1'b1), + .D(\m_payload_i[65]_i_1_n_0 ), + .Q(st_mr_rmesg[68]), + .R(1'b0)); + FDRE \m_payload_i_reg[66] + (.C(aclk), + .CE(1'b1), + .D(\m_payload_i[66]_i_1_n_0 ), + .Q(\gen_master_slots[1].r_issuing_cnt_reg[8]_0 ), + .R(1'b0)); + LUT5 #( + .INIT(32'hDDFDFDFD)) + m_valid_i_i_1__3 + (.I0(\skid_buffer_reg[64]_0 ), + .I1(p_11_in), + .I2(m_valid_i_reg_0), + .I3(active_target_enc_0), + .I4(s_axi_rready), + .O(m_valid_i0)); + FDRE m_valid_i_reg + (.C(aclk), + .CE(1'b1), + .D(m_valid_i0), + .Q(m_valid_i_reg_0), + .R(\aresetn_d_reg[1] )); + (* SOFT_HLUTNM = "soft_lutpair157" *) + LUT3 #( + .INIT(8'hB8)) + \s_axi_rlast[0]_INST_0 + (.I0(\gen_master_slots[1].r_issuing_cnt_reg[8]_0 ), + .I1(active_target_enc_0), + .I2(Q[2]), + .O(s_axi_rlast)); + (* SOFT_HLUTNM = "soft_lutpair158" *) + LUT3 #( + .INIT(8'hB8)) + \s_axi_rresp[0]_INST_0 + (.I0(st_mr_rmesg[67]), + .I1(active_target_enc_0), + .I2(Q[0]), + .O(s_axi_rresp[0])); + (* SOFT_HLUTNM = "soft_lutpair158" *) + LUT3 #( + .INIT(8'hB8)) + \s_axi_rresp[1]_INST_0 + (.I0(st_mr_rmesg[68]), + .I1(active_target_enc_0), + .I2(Q[1]), + .O(s_axi_rresp[1])); + LUT5 #( + .INIT(32'hD5D5FFD5)) + s_ready_i_i_1__3 + (.I0(m_valid_i_reg_0), + .I1(active_target_enc_0), + .I2(s_axi_rready), + .I3(\skid_buffer_reg[64]_0 ), + .I4(p_11_in), + .O(s_ready_i_i_1__3_n_0)); + FDRE s_ready_i_reg + (.C(aclk), + .CE(1'b1), + .D(s_ready_i_i_1__3_n_0), + .Q(\skid_buffer_reg[64]_0 ), + .R(p_1_in)); + (* SOFT_HLUTNM = "soft_lutpair159" *) + LUT2 #( + .INIT(4'hE)) + \skid_buffer[64]_i_1 + (.I0(\skid_buffer_reg[64]_0 ), + .I1(\skid_buffer_reg_n_0_[64] ), + .O(skid_buffer[64])); + (* SOFT_HLUTNM = "soft_lutpair159" *) + LUT2 #( + .INIT(4'hE)) + \skid_buffer[65]_i_1 + (.I0(\skid_buffer_reg_n_0_[65] ), + .I1(\skid_buffer_reg[64]_0 ), + .O(skid_buffer[65])); + (* SOFT_HLUTNM = "soft_lutpair156" *) + LUT3 #( + .INIT(8'hB8)) + \skid_buffer[66]_i_1 + (.I0(p_13_in), + .I1(\skid_buffer_reg[64]_0 ), + .I2(\skid_buffer_reg_n_0_[66] ), + .O(skid_buffer[66])); + FDRE \skid_buffer_reg[64] + (.C(aclk), + .CE(1'b1), + .D(skid_buffer[64]), + .Q(\skid_buffer_reg_n_0_[64] ), + .R(1'b0)); + FDRE \skid_buffer_reg[65] + (.C(aclk), + .CE(1'b1), + .D(skid_buffer[65]), + .Q(\skid_buffer_reg_n_0_[65] ), + .R(1'b0)); + FDRE \skid_buffer_reg[66] + (.C(aclk), + .CE(1'b1), + .D(skid_buffer[66]), + .Q(\skid_buffer_reg_n_0_[66] ), + .R(1'b0)); +endmodule + +(* ORIG_REF_NAME = "axi_register_slice_v2_1_11_axic_register_slice" *) +module Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2_5 + (m_valid_i_reg_0, + \m_axi_rready[0] , + s_axi_rdata, + \gen_arbiter.qual_reg_reg[0] , + Q, + D, + \gen_master_slots[0].r_issuing_cnt_reg[0] , + \aresetn_d_reg[1] , + aclk, + p_1_in, + active_target_hot_0, + s_axi_rready, + m_axi_rvalid, + active_target_enc, + p_30_out, + \gen_master_slots[0].r_issuing_cnt_reg[3] , + \gen_arbiter.m_valid_i_reg , + m_axi_rlast, + m_axi_rresp, + m_axi_rdata, + E); + output m_valid_i_reg_0; + output \m_axi_rready[0] ; + output [63:0]s_axi_rdata; + output \gen_arbiter.qual_reg_reg[0] ; + output [2:0]Q; + output [2:0]D; + output \gen_master_slots[0].r_issuing_cnt_reg[0] ; + input \aresetn_d_reg[1] ; + input aclk; + input p_1_in; + input [0:0]active_target_hot_0; + input [0:0]s_axi_rready; + input [0:0]m_axi_rvalid; + input active_target_enc; + input p_30_out; + input [3:0]\gen_master_slots[0].r_issuing_cnt_reg[3] ; + input \gen_arbiter.m_valid_i_reg ; + input [0:0]m_axi_rlast; + input [1:0]m_axi_rresp; + input [63:0]m_axi_rdata; + input [0:0]E; + + wire [2:0]D; + wire [0:0]E; + wire [2:0]Q; + wire aclk; + wire active_target_enc; + wire [0:0]active_target_hot_0; + wire \aresetn_d_reg[1] ; + wire \gen_arbiter.m_valid_i_reg ; + wire \gen_arbiter.qual_reg_reg[0] ; + wire \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0 ; + wire \gen_master_slots[0].r_issuing_cnt_reg[0] ; + wire [3:0]\gen_master_slots[0].r_issuing_cnt_reg[3] ; + wire [63:0]m_axi_rdata; + wire [0:0]m_axi_rlast; + wire \m_axi_rready[0] ; + wire [1:0]m_axi_rresp; + wire [0:0]m_axi_rvalid; + wire m_valid_i0; + wire m_valid_i_reg_0; + wire p_1_in; + wire p_30_out; + wire [63:0]s_axi_rdata; + wire [0:0]s_axi_rready; + wire s_ready_i_i_1__2_n_0; + wire [66:0]skid_buffer; + wire \skid_buffer_reg_n_0_[0] ; + wire \skid_buffer_reg_n_0_[10] ; + wire \skid_buffer_reg_n_0_[11] ; + wire \skid_buffer_reg_n_0_[12] ; + wire \skid_buffer_reg_n_0_[13] ; + wire \skid_buffer_reg_n_0_[14] ; + wire \skid_buffer_reg_n_0_[15] ; + wire \skid_buffer_reg_n_0_[16] ; + wire \skid_buffer_reg_n_0_[17] ; + wire \skid_buffer_reg_n_0_[18] ; + wire \skid_buffer_reg_n_0_[19] ; + wire \skid_buffer_reg_n_0_[1] ; + wire \skid_buffer_reg_n_0_[20] ; + wire \skid_buffer_reg_n_0_[21] ; + wire \skid_buffer_reg_n_0_[22] ; + wire \skid_buffer_reg_n_0_[23] ; + wire \skid_buffer_reg_n_0_[24] ; + wire \skid_buffer_reg_n_0_[25] ; + wire \skid_buffer_reg_n_0_[26] ; + wire \skid_buffer_reg_n_0_[27] ; + wire \skid_buffer_reg_n_0_[28] ; + wire \skid_buffer_reg_n_0_[29] ; + wire \skid_buffer_reg_n_0_[2] ; + wire \skid_buffer_reg_n_0_[30] ; + wire \skid_buffer_reg_n_0_[31] ; + wire \skid_buffer_reg_n_0_[32] ; + wire \skid_buffer_reg_n_0_[33] ; + wire \skid_buffer_reg_n_0_[34] ; + wire \skid_buffer_reg_n_0_[35] ; + wire \skid_buffer_reg_n_0_[36] ; + wire \skid_buffer_reg_n_0_[37] ; + wire \skid_buffer_reg_n_0_[38] ; + wire \skid_buffer_reg_n_0_[39] ; + wire \skid_buffer_reg_n_0_[3] ; + wire \skid_buffer_reg_n_0_[40] ; + wire \skid_buffer_reg_n_0_[41] ; + wire \skid_buffer_reg_n_0_[42] ; + wire \skid_buffer_reg_n_0_[43] ; + wire \skid_buffer_reg_n_0_[44] ; + wire \skid_buffer_reg_n_0_[45] ; + wire \skid_buffer_reg_n_0_[46] ; + wire \skid_buffer_reg_n_0_[47] ; + wire \skid_buffer_reg_n_0_[48] ; + wire \skid_buffer_reg_n_0_[49] ; + wire \skid_buffer_reg_n_0_[4] ; + wire \skid_buffer_reg_n_0_[50] ; + wire \skid_buffer_reg_n_0_[51] ; + wire \skid_buffer_reg_n_0_[52] ; + wire \skid_buffer_reg_n_0_[53] ; + wire \skid_buffer_reg_n_0_[54] ; + wire \skid_buffer_reg_n_0_[55] ; + wire \skid_buffer_reg_n_0_[56] ; + wire \skid_buffer_reg_n_0_[57] ; + wire \skid_buffer_reg_n_0_[58] ; + wire \skid_buffer_reg_n_0_[59] ; + wire \skid_buffer_reg_n_0_[5] ; + wire \skid_buffer_reg_n_0_[60] ; + wire \skid_buffer_reg_n_0_[61] ; + wire \skid_buffer_reg_n_0_[62] ; + wire \skid_buffer_reg_n_0_[63] ; + wire \skid_buffer_reg_n_0_[64] ; + wire \skid_buffer_reg_n_0_[65] ; + wire \skid_buffer_reg_n_0_[66] ; + wire \skid_buffer_reg_n_0_[6] ; + wire \skid_buffer_reg_n_0_[7] ; + wire \skid_buffer_reg_n_0_[8] ; + wire \skid_buffer_reg_n_0_[9] ; + wire [66:3]st_mr_rmesg; + + LUT6 #( + .INIT(64'hE200000000000000)) + \gen_arbiter.qual_reg[0]_i_6 + (.I0(Q[2]), + .I1(active_target_enc), + .I2(p_30_out), + .I3(m_valid_i_reg_0), + .I4(active_target_hot_0), + .I5(s_axi_rready), + .O(\gen_arbiter.qual_reg_reg[0] )); + LUT3 #( + .INIT(8'h69)) + \gen_master_slots[0].r_issuing_cnt[1]_i_1 + (.I0(\gen_master_slots[0].r_issuing_cnt_reg[3] [1]), + .I1(\gen_master_slots[0].r_issuing_cnt_reg[3] [0]), + .I2(\gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0 ), + .O(D[0])); + (* SOFT_HLUTNM = "soft_lutpair88" *) + LUT4 #( + .INIT(16'h6AA9)) + \gen_master_slots[0].r_issuing_cnt[2]_i_1 + (.I0(\gen_master_slots[0].r_issuing_cnt_reg[3] [2]), + .I1(\gen_master_slots[0].r_issuing_cnt_reg[3] [0]), + .I2(\gen_master_slots[0].r_issuing_cnt_reg[3] [1]), + .I3(\gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0 ), + .O(D[1])); + (* SOFT_HLUTNM = "soft_lutpair88" *) + LUT5 #( + .INIT(32'h6AAAAAA9)) + \gen_master_slots[0].r_issuing_cnt[3]_i_2 + (.I0(\gen_master_slots[0].r_issuing_cnt_reg[3] [3]), + .I1(\gen_master_slots[0].r_issuing_cnt_reg[3] [1]), + .I2(\gen_master_slots[0].r_issuing_cnt_reg[3] [2]), + .I3(\gen_master_slots[0].r_issuing_cnt_reg[3] [0]), + .I4(\gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0 ), + .O(D[2])); + (* SOFT_HLUTNM = "soft_lutpair89" *) + LUT4 #( + .INIT(16'h7FFF)) + \gen_master_slots[0].r_issuing_cnt[3]_i_4 + (.I0(m_valid_i_reg_0), + .I1(active_target_hot_0), + .I2(s_axi_rready), + .I3(Q[2]), + .O(\gen_master_slots[0].r_issuing_cnt_reg[0] )); + (* SOFT_HLUTNM = "soft_lutpair89" *) + LUT5 #( + .INIT(32'h00007FFF)) + \gen_master_slots[0].r_issuing_cnt[3]_i_5 + (.I0(Q[2]), + .I1(s_axi_rready), + .I2(active_target_hot_0), + .I3(m_valid_i_reg_0), + .I4(\gen_arbiter.m_valid_i_reg ), + .O(\gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0 )); + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[0]_i_1 + (.I0(m_axi_rdata[0]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[0] ), + .O(skid_buffer[0])); + (* SOFT_HLUTNM = "soft_lutpair118" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[10]_i_1 + (.I0(m_axi_rdata[10]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[10] ), + .O(skid_buffer[10])); + (* SOFT_HLUTNM = "soft_lutpair117" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[11]_i_1 + (.I0(m_axi_rdata[11]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[11] ), + .O(skid_buffer[11])); + (* SOFT_HLUTNM = "soft_lutpair117" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[12]_i_1 + (.I0(m_axi_rdata[12]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[12] ), + .O(skid_buffer[12])); + (* SOFT_HLUTNM = "soft_lutpair116" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[13]_i_1 + (.I0(m_axi_rdata[13]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[13] ), + .O(skid_buffer[13])); + (* SOFT_HLUTNM = "soft_lutpair116" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[14]_i_1 + (.I0(m_axi_rdata[14]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[14] ), + .O(skid_buffer[14])); + (* SOFT_HLUTNM = "soft_lutpair115" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[15]_i_1 + (.I0(m_axi_rdata[15]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[15] ), + .O(skid_buffer[15])); + (* SOFT_HLUTNM = "soft_lutpair115" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[16]_i_1 + (.I0(m_axi_rdata[16]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[16] ), + .O(skid_buffer[16])); + (* SOFT_HLUTNM = "soft_lutpair114" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[17]_i_1 + (.I0(m_axi_rdata[17]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[17] ), + .O(skid_buffer[17])); + (* SOFT_HLUTNM = "soft_lutpair114" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[18]_i_1 + (.I0(m_axi_rdata[18]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[18] ), + .O(skid_buffer[18])); + (* SOFT_HLUTNM = "soft_lutpair113" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[19]_i_1 + (.I0(m_axi_rdata[19]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[19] ), + .O(skid_buffer[19])); + (* SOFT_HLUTNM = "soft_lutpair122" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[1]_i_1 + (.I0(m_axi_rdata[1]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[1] ), + .O(skid_buffer[1])); + (* SOFT_HLUTNM = "soft_lutpair113" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[20]_i_1 + (.I0(m_axi_rdata[20]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[20] ), + .O(skid_buffer[20])); + (* SOFT_HLUTNM = "soft_lutpair112" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[21]_i_1 + (.I0(m_axi_rdata[21]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[21] ), + .O(skid_buffer[21])); + (* SOFT_HLUTNM = "soft_lutpair112" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[22]_i_1 + (.I0(m_axi_rdata[22]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[22] ), + .O(skid_buffer[22])); + (* SOFT_HLUTNM = "soft_lutpair111" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[23]_i_1 + (.I0(m_axi_rdata[23]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[23] ), + .O(skid_buffer[23])); + (* SOFT_HLUTNM = "soft_lutpair111" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[24]_i_1 + (.I0(m_axi_rdata[24]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[24] ), + .O(skid_buffer[24])); + (* SOFT_HLUTNM = "soft_lutpair110" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[25]_i_1 + (.I0(m_axi_rdata[25]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[25] ), + .O(skid_buffer[25])); + (* SOFT_HLUTNM = "soft_lutpair110" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[26]_i_1 + (.I0(m_axi_rdata[26]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[26] ), + .O(skid_buffer[26])); + (* SOFT_HLUTNM = "soft_lutpair109" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[27]_i_1 + (.I0(m_axi_rdata[27]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[27] ), + .O(skid_buffer[27])); + (* SOFT_HLUTNM = "soft_lutpair109" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[28]_i_1 + (.I0(m_axi_rdata[28]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[28] ), + .O(skid_buffer[28])); + (* SOFT_HLUTNM = "soft_lutpair108" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[29]_i_1 + (.I0(m_axi_rdata[29]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[29] ), + .O(skid_buffer[29])); + (* SOFT_HLUTNM = "soft_lutpair122" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[2]_i_1 + (.I0(m_axi_rdata[2]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[2] ), + .O(skid_buffer[2])); + (* SOFT_HLUTNM = "soft_lutpair108" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[30]_i_1 + (.I0(m_axi_rdata[30]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[30] ), + .O(skid_buffer[30])); + (* SOFT_HLUTNM = "soft_lutpair107" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[31]_i_1 + (.I0(m_axi_rdata[31]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[31] ), + .O(skid_buffer[31])); + (* SOFT_HLUTNM = "soft_lutpair107" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[32]_i_1 + (.I0(m_axi_rdata[32]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[32] ), + .O(skid_buffer[32])); + (* SOFT_HLUTNM = "soft_lutpair106" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[33]_i_1 + (.I0(m_axi_rdata[33]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[33] ), + .O(skid_buffer[33])); + (* SOFT_HLUTNM = "soft_lutpair106" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[34]_i_1 + (.I0(m_axi_rdata[34]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[34] ), + .O(skid_buffer[34])); + (* SOFT_HLUTNM = "soft_lutpair105" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[35]_i_1 + (.I0(m_axi_rdata[35]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[35] ), + .O(skid_buffer[35])); + (* SOFT_HLUTNM = "soft_lutpair105" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[36]_i_1 + (.I0(m_axi_rdata[36]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[36] ), + .O(skid_buffer[36])); + (* SOFT_HLUTNM = "soft_lutpair104" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[37]_i_1 + (.I0(m_axi_rdata[37]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[37] ), + .O(skid_buffer[37])); + (* SOFT_HLUTNM = "soft_lutpair104" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[38]_i_1 + (.I0(m_axi_rdata[38]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[38] ), + .O(skid_buffer[38])); + (* SOFT_HLUTNM = "soft_lutpair103" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[39]_i_1 + (.I0(m_axi_rdata[39]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[39] ), + .O(skid_buffer[39])); + (* SOFT_HLUTNM = "soft_lutpair121" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[3]_i_1 + (.I0(m_axi_rdata[3]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[3] ), + .O(skid_buffer[3])); + (* SOFT_HLUTNM = "soft_lutpair103" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[40]_i_1 + (.I0(m_axi_rdata[40]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[40] ), + .O(skid_buffer[40])); + (* SOFT_HLUTNM = "soft_lutpair102" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[41]_i_1 + (.I0(m_axi_rdata[41]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[41] ), + .O(skid_buffer[41])); + (* SOFT_HLUTNM = "soft_lutpair102" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[42]_i_1 + (.I0(m_axi_rdata[42]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[42] ), + .O(skid_buffer[42])); + (* SOFT_HLUTNM = "soft_lutpair101" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[43]_i_1 + (.I0(m_axi_rdata[43]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[43] ), + .O(skid_buffer[43])); + (* SOFT_HLUTNM = "soft_lutpair101" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[44]_i_1 + (.I0(m_axi_rdata[44]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[44] ), + .O(skid_buffer[44])); + (* SOFT_HLUTNM = "soft_lutpair100" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[45]_i_1 + (.I0(m_axi_rdata[45]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[45] ), + .O(skid_buffer[45])); + (* SOFT_HLUTNM = "soft_lutpair100" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[46]_i_1 + (.I0(m_axi_rdata[46]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[46] ), + .O(skid_buffer[46])); + (* SOFT_HLUTNM = "soft_lutpair99" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[47]_i_1 + (.I0(m_axi_rdata[47]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[47] ), + .O(skid_buffer[47])); + (* SOFT_HLUTNM = "soft_lutpair99" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[48]_i_1 + (.I0(m_axi_rdata[48]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[48] ), + .O(skid_buffer[48])); + (* SOFT_HLUTNM = "soft_lutpair98" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[49]_i_1 + (.I0(m_axi_rdata[49]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[49] ), + .O(skid_buffer[49])); + (* SOFT_HLUTNM = "soft_lutpair121" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[4]_i_1 + (.I0(m_axi_rdata[4]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[4] ), + .O(skid_buffer[4])); + (* SOFT_HLUTNM = "soft_lutpair98" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[50]_i_1 + (.I0(m_axi_rdata[50]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[50] ), + .O(skid_buffer[50])); + (* SOFT_HLUTNM = "soft_lutpair97" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[51]_i_1 + (.I0(m_axi_rdata[51]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[51] ), + .O(skid_buffer[51])); + (* SOFT_HLUTNM = "soft_lutpair97" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[52]_i_1 + (.I0(m_axi_rdata[52]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[52] ), + .O(skid_buffer[52])); + (* SOFT_HLUTNM = "soft_lutpair96" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[53]_i_1 + (.I0(m_axi_rdata[53]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[53] ), + .O(skid_buffer[53])); + (* SOFT_HLUTNM = "soft_lutpair96" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[54]_i_1 + (.I0(m_axi_rdata[54]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[54] ), + .O(skid_buffer[54])); + (* SOFT_HLUTNM = "soft_lutpair95" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[55]_i_1 + (.I0(m_axi_rdata[55]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[55] ), + .O(skid_buffer[55])); + (* SOFT_HLUTNM = "soft_lutpair95" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[56]_i_1 + (.I0(m_axi_rdata[56]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[56] ), + .O(skid_buffer[56])); + (* SOFT_HLUTNM = "soft_lutpair94" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[57]_i_1 + (.I0(m_axi_rdata[57]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[57] ), + .O(skid_buffer[57])); + (* SOFT_HLUTNM = "soft_lutpair94" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[58]_i_1 + (.I0(m_axi_rdata[58]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[58] ), + .O(skid_buffer[58])); + (* SOFT_HLUTNM = "soft_lutpair93" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[59]_i_1 + (.I0(m_axi_rdata[59]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[59] ), + .O(skid_buffer[59])); + (* SOFT_HLUTNM = "soft_lutpair120" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[5]_i_1 + (.I0(m_axi_rdata[5]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[5] ), + .O(skid_buffer[5])); + (* SOFT_HLUTNM = "soft_lutpair93" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[60]_i_1 + (.I0(m_axi_rdata[60]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[60] ), + .O(skid_buffer[60])); + (* SOFT_HLUTNM = "soft_lutpair92" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[61]_i_1 + (.I0(m_axi_rdata[61]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[61] ), + .O(skid_buffer[61])); + (* SOFT_HLUTNM = "soft_lutpair92" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[62]_i_1 + (.I0(m_axi_rdata[62]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[62] ), + .O(skid_buffer[62])); + (* SOFT_HLUTNM = "soft_lutpair91" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[63]_i_1 + (.I0(m_axi_rdata[63]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[63] ), + .O(skid_buffer[63])); + (* SOFT_HLUTNM = "soft_lutpair91" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[64]_i_1 + (.I0(m_axi_rresp[0]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[64] ), + .O(skid_buffer[64])); + (* SOFT_HLUTNM = "soft_lutpair90" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[65]_i_1 + (.I0(m_axi_rresp[1]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[65] ), + .O(skid_buffer[65])); + (* SOFT_HLUTNM = "soft_lutpair90" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[66]_i_2 + (.I0(m_axi_rlast), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[66] ), + .O(skid_buffer[66])); + (* SOFT_HLUTNM = "soft_lutpair120" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[6]_i_1 + (.I0(m_axi_rdata[6]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[6] ), + .O(skid_buffer[6])); + (* SOFT_HLUTNM = "soft_lutpair119" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[7]_i_1 + (.I0(m_axi_rdata[7]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[7] ), + .O(skid_buffer[7])); + (* SOFT_HLUTNM = "soft_lutpair119" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[8]_i_1 + (.I0(m_axi_rdata[8]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[8] ), + .O(skid_buffer[8])); + (* SOFT_HLUTNM = "soft_lutpair118" *) + LUT3 #( + .INIT(8'hB8)) + \m_payload_i[9]_i_1 + (.I0(m_axi_rdata[9]), + .I1(\m_axi_rready[0] ), + .I2(\skid_buffer_reg_n_0_[9] ), + .O(skid_buffer[9])); + FDRE \m_payload_i_reg[0] + (.C(aclk), + .CE(E), + .D(skid_buffer[0]), + .Q(st_mr_rmesg[3]), + .R(1'b0)); + FDRE \m_payload_i_reg[10] + (.C(aclk), + .CE(E), + .D(skid_buffer[10]), + .Q(st_mr_rmesg[13]), + .R(1'b0)); + FDRE \m_payload_i_reg[11] + (.C(aclk), + .CE(E), + .D(skid_buffer[11]), + .Q(st_mr_rmesg[14]), + .R(1'b0)); + FDRE \m_payload_i_reg[12] + (.C(aclk), + .CE(E), + .D(skid_buffer[12]), + .Q(st_mr_rmesg[15]), + .R(1'b0)); + FDRE \m_payload_i_reg[13] + (.C(aclk), + .CE(E), + .D(skid_buffer[13]), + .Q(st_mr_rmesg[16]), + .R(1'b0)); + FDRE \m_payload_i_reg[14] + (.C(aclk), + .CE(E), + .D(skid_buffer[14]), + .Q(st_mr_rmesg[17]), + .R(1'b0)); + FDRE \m_payload_i_reg[15] + (.C(aclk), + .CE(E), + .D(skid_buffer[15]), + .Q(st_mr_rmesg[18]), + .R(1'b0)); + FDRE \m_payload_i_reg[16] + (.C(aclk), + .CE(E), + .D(skid_buffer[16]), + .Q(st_mr_rmesg[19]), + .R(1'b0)); + FDRE \m_payload_i_reg[17] + (.C(aclk), + .CE(E), + .D(skid_buffer[17]), + .Q(st_mr_rmesg[20]), + .R(1'b0)); + FDRE \m_payload_i_reg[18] + (.C(aclk), + .CE(E), + .D(skid_buffer[18]), + .Q(st_mr_rmesg[21]), + .R(1'b0)); + FDRE \m_payload_i_reg[19] + (.C(aclk), + .CE(E), + .D(skid_buffer[19]), + .Q(st_mr_rmesg[22]), + .R(1'b0)); + FDRE \m_payload_i_reg[1] + (.C(aclk), + .CE(E), + .D(skid_buffer[1]), + .Q(st_mr_rmesg[4]), + .R(1'b0)); + FDRE \m_payload_i_reg[20] + (.C(aclk), + .CE(E), + .D(skid_buffer[20]), + .Q(st_mr_rmesg[23]), + .R(1'b0)); + FDRE \m_payload_i_reg[21] + (.C(aclk), + .CE(E), + .D(skid_buffer[21]), + .Q(st_mr_rmesg[24]), + .R(1'b0)); + FDRE \m_payload_i_reg[22] + (.C(aclk), + .CE(E), + .D(skid_buffer[22]), + .Q(st_mr_rmesg[25]), + .R(1'b0)); + FDRE \m_payload_i_reg[23] + (.C(aclk), + .CE(E), + .D(skid_buffer[23]), + .Q(st_mr_rmesg[26]), + .R(1'b0)); + FDRE \m_payload_i_reg[24] + (.C(aclk), + .CE(E), + .D(skid_buffer[24]), + .Q(st_mr_rmesg[27]), + .R(1'b0)); + FDRE \m_payload_i_reg[25] + (.C(aclk), + .CE(E), + .D(skid_buffer[25]), + .Q(st_mr_rmesg[28]), + .R(1'b0)); + FDRE \m_payload_i_reg[26] + (.C(aclk), + .CE(E), + .D(skid_buffer[26]), + .Q(st_mr_rmesg[29]), + .R(1'b0)); + FDRE \m_payload_i_reg[27] + (.C(aclk), + .CE(E), + .D(skid_buffer[27]), + .Q(st_mr_rmesg[30]), + .R(1'b0)); + FDRE \m_payload_i_reg[28] + (.C(aclk), + .CE(E), + .D(skid_buffer[28]), + .Q(st_mr_rmesg[31]), + .R(1'b0)); + FDRE \m_payload_i_reg[29] + (.C(aclk), + .CE(E), + .D(skid_buffer[29]), + .Q(st_mr_rmesg[32]), + .R(1'b0)); + FDRE \m_payload_i_reg[2] + (.C(aclk), + .CE(E), + .D(skid_buffer[2]), + .Q(st_mr_rmesg[5]), + .R(1'b0)); + FDRE \m_payload_i_reg[30] + (.C(aclk), + .CE(E), + .D(skid_buffer[30]), + .Q(st_mr_rmesg[33]), + .R(1'b0)); + FDRE \m_payload_i_reg[31] + (.C(aclk), + .CE(E), + .D(skid_buffer[31]), + .Q(st_mr_rmesg[34]), + .R(1'b0)); + FDRE \m_payload_i_reg[32] + (.C(aclk), + .CE(E), + .D(skid_buffer[32]), + .Q(st_mr_rmesg[35]), + .R(1'b0)); + FDRE \m_payload_i_reg[33] + (.C(aclk), + .CE(E), + .D(skid_buffer[33]), + .Q(st_mr_rmesg[36]), + .R(1'b0)); + FDRE \m_payload_i_reg[34] + (.C(aclk), + .CE(E), + .D(skid_buffer[34]), + .Q(st_mr_rmesg[37]), + .R(1'b0)); + FDRE \m_payload_i_reg[35] + (.C(aclk), + .CE(E), + .D(skid_buffer[35]), + .Q(st_mr_rmesg[38]), + .R(1'b0)); + FDRE \m_payload_i_reg[36] + (.C(aclk), + .CE(E), + .D(skid_buffer[36]), + .Q(st_mr_rmesg[39]), + .R(1'b0)); + FDRE \m_payload_i_reg[37] + (.C(aclk), + .CE(E), + .D(skid_buffer[37]), + .Q(st_mr_rmesg[40]), + .R(1'b0)); + FDRE \m_payload_i_reg[38] + (.C(aclk), + .CE(E), + .D(skid_buffer[38]), + .Q(st_mr_rmesg[41]), + .R(1'b0)); + FDRE \m_payload_i_reg[39] + (.C(aclk), + .CE(E), + .D(skid_buffer[39]), + .Q(st_mr_rmesg[42]), + .R(1'b0)); + FDRE \m_payload_i_reg[3] + (.C(aclk), + .CE(E), + .D(skid_buffer[3]), + .Q(st_mr_rmesg[6]), + .R(1'b0)); + FDRE \m_payload_i_reg[40] + (.C(aclk), + .CE(E), + .D(skid_buffer[40]), + .Q(st_mr_rmesg[43]), + .R(1'b0)); + FDRE \m_payload_i_reg[41] + (.C(aclk), + .CE(E), + .D(skid_buffer[41]), + .Q(st_mr_rmesg[44]), + .R(1'b0)); + FDRE \m_payload_i_reg[42] + (.C(aclk), + .CE(E), + .D(skid_buffer[42]), + .Q(st_mr_rmesg[45]), + .R(1'b0)); + FDRE \m_payload_i_reg[43] + (.C(aclk), + .CE(E), + .D(skid_buffer[43]), + .Q(st_mr_rmesg[46]), + .R(1'b0)); + FDRE \m_payload_i_reg[44] + (.C(aclk), + .CE(E), + .D(skid_buffer[44]), + .Q(st_mr_rmesg[47]), + .R(1'b0)); + FDRE \m_payload_i_reg[45] + (.C(aclk), + .CE(E), + .D(skid_buffer[45]), + .Q(st_mr_rmesg[48]), + .R(1'b0)); + FDRE \m_payload_i_reg[46] + (.C(aclk), + .CE(E), + .D(skid_buffer[46]), + .Q(st_mr_rmesg[49]), + .R(1'b0)); + FDRE \m_payload_i_reg[47] + (.C(aclk), + .CE(E), + .D(skid_buffer[47]), + .Q(st_mr_rmesg[50]), + .R(1'b0)); + FDRE \m_payload_i_reg[48] + (.C(aclk), + .CE(E), + .D(skid_buffer[48]), + .Q(st_mr_rmesg[51]), + .R(1'b0)); + FDRE \m_payload_i_reg[49] + (.C(aclk), + .CE(E), + .D(skid_buffer[49]), + .Q(st_mr_rmesg[52]), + .R(1'b0)); + FDRE \m_payload_i_reg[4] + (.C(aclk), + .CE(E), + .D(skid_buffer[4]), + .Q(st_mr_rmesg[7]), + .R(1'b0)); + FDRE \m_payload_i_reg[50] + (.C(aclk), + .CE(E), + .D(skid_buffer[50]), + .Q(st_mr_rmesg[53]), + .R(1'b0)); + FDRE \m_payload_i_reg[51] + (.C(aclk), + .CE(E), + .D(skid_buffer[51]), + .Q(st_mr_rmesg[54]), + .R(1'b0)); + FDRE \m_payload_i_reg[52] + (.C(aclk), + .CE(E), + .D(skid_buffer[52]), + .Q(st_mr_rmesg[55]), + .R(1'b0)); + FDRE \m_payload_i_reg[53] + (.C(aclk), + .CE(E), + .D(skid_buffer[53]), + .Q(st_mr_rmesg[56]), + .R(1'b0)); + FDRE \m_payload_i_reg[54] + (.C(aclk), + .CE(E), + .D(skid_buffer[54]), + .Q(st_mr_rmesg[57]), + .R(1'b0)); + FDRE \m_payload_i_reg[55] + (.C(aclk), + .CE(E), + .D(skid_buffer[55]), + .Q(st_mr_rmesg[58]), + .R(1'b0)); + FDRE \m_payload_i_reg[56] + (.C(aclk), + .CE(E), + .D(skid_buffer[56]), + .Q(st_mr_rmesg[59]), + .R(1'b0)); + FDRE \m_payload_i_reg[57] + (.C(aclk), + .CE(E), + .D(skid_buffer[57]), + .Q(st_mr_rmesg[60]), + .R(1'b0)); + FDRE \m_payload_i_reg[58] + (.C(aclk), + .CE(E), + .D(skid_buffer[58]), + .Q(st_mr_rmesg[61]), + .R(1'b0)); + FDRE \m_payload_i_reg[59] + (.C(aclk), + .CE(E), + .D(skid_buffer[59]), + .Q(st_mr_rmesg[62]), + .R(1'b0)); + FDRE \m_payload_i_reg[5] + (.C(aclk), + .CE(E), + .D(skid_buffer[5]), + .Q(st_mr_rmesg[8]), + .R(1'b0)); + FDRE \m_payload_i_reg[60] + (.C(aclk), + .CE(E), + .D(skid_buffer[60]), + .Q(st_mr_rmesg[63]), + .R(1'b0)); + FDRE \m_payload_i_reg[61] + (.C(aclk), + .CE(E), + .D(skid_buffer[61]), + .Q(st_mr_rmesg[64]), + .R(1'b0)); + FDRE \m_payload_i_reg[62] + (.C(aclk), + .CE(E), + .D(skid_buffer[62]), + .Q(st_mr_rmesg[65]), + .R(1'b0)); + FDRE \m_payload_i_reg[63] + (.C(aclk), + .CE(E), + .D(skid_buffer[63]), + .Q(st_mr_rmesg[66]), + .R(1'b0)); + FDRE \m_payload_i_reg[64] + (.C(aclk), + .CE(E), + .D(skid_buffer[64]), + .Q(Q[0]), + .R(1'b0)); + FDRE \m_payload_i_reg[65] + (.C(aclk), + .CE(E), + .D(skid_buffer[65]), + .Q(Q[1]), + .R(1'b0)); + FDRE \m_payload_i_reg[66] + (.C(aclk), + .CE(E), + .D(skid_buffer[66]), + .Q(Q[2]), + .R(1'b0)); + FDRE \m_payload_i_reg[6] + (.C(aclk), + .CE(E), + .D(skid_buffer[6]), + .Q(st_mr_rmesg[9]), + .R(1'b0)); + FDRE \m_payload_i_reg[7] + (.C(aclk), + .CE(E), + .D(skid_buffer[7]), + .Q(st_mr_rmesg[10]), + .R(1'b0)); + FDRE \m_payload_i_reg[8] + (.C(aclk), + .CE(E), + .D(skid_buffer[8]), + .Q(st_mr_rmesg[11]), + .R(1'b0)); + FDRE \m_payload_i_reg[9] + (.C(aclk), + .CE(E), + .D(skid_buffer[9]), + .Q(st_mr_rmesg[12]), + .R(1'b0)); + LUT5 #( + .INIT(32'hDDFDFDFD)) + m_valid_i_i_1__2 + (.I0(\m_axi_rready[0] ), + .I1(m_axi_rvalid), + .I2(m_valid_i_reg_0), + .I3(active_target_hot_0), + .I4(s_axi_rready), + .O(m_valid_i0)); + FDRE m_valid_i_reg + (.C(aclk), + .CE(1'b1), + .D(m_valid_i0), + .Q(m_valid_i_reg_0), + .R(\aresetn_d_reg[1] )); + (* SOFT_HLUTNM = "soft_lutpair154" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[0]_INST_0 + (.I0(st_mr_rmesg[3]), + .I1(active_target_enc), + .O(s_axi_rdata[0])); + (* SOFT_HLUTNM = "soft_lutpair149" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[10]_INST_0 + (.I0(st_mr_rmesg[13]), + .I1(active_target_enc), + .O(s_axi_rdata[10])); + (* SOFT_HLUTNM = "soft_lutpair149" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[11]_INST_0 + (.I0(st_mr_rmesg[14]), + .I1(active_target_enc), + .O(s_axi_rdata[11])); + (* SOFT_HLUTNM = "soft_lutpair148" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[12]_INST_0 + (.I0(st_mr_rmesg[15]), + .I1(active_target_enc), + .O(s_axi_rdata[12])); + (* SOFT_HLUTNM = "soft_lutpair148" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[13]_INST_0 + (.I0(st_mr_rmesg[16]), + .I1(active_target_enc), + .O(s_axi_rdata[13])); + (* SOFT_HLUTNM = "soft_lutpair147" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[14]_INST_0 + (.I0(st_mr_rmesg[17]), + .I1(active_target_enc), + .O(s_axi_rdata[14])); + (* SOFT_HLUTNM = "soft_lutpair147" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[15]_INST_0 + (.I0(st_mr_rmesg[18]), + .I1(active_target_enc), + .O(s_axi_rdata[15])); + (* SOFT_HLUTNM = "soft_lutpair146" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[16]_INST_0 + (.I0(st_mr_rmesg[19]), + .I1(active_target_enc), + .O(s_axi_rdata[16])); + (* SOFT_HLUTNM = "soft_lutpair146" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[17]_INST_0 + (.I0(st_mr_rmesg[20]), + .I1(active_target_enc), + .O(s_axi_rdata[17])); + (* SOFT_HLUTNM = "soft_lutpair145" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[18]_INST_0 + (.I0(st_mr_rmesg[21]), + .I1(active_target_enc), + .O(s_axi_rdata[18])); + (* SOFT_HLUTNM = "soft_lutpair145" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[19]_INST_0 + (.I0(st_mr_rmesg[22]), + .I1(active_target_enc), + .O(s_axi_rdata[19])); + (* SOFT_HLUTNM = "soft_lutpair154" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[1]_INST_0 + (.I0(st_mr_rmesg[4]), + .I1(active_target_enc), + .O(s_axi_rdata[1])); + (* SOFT_HLUTNM = "soft_lutpair144" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[20]_INST_0 + (.I0(st_mr_rmesg[23]), + .I1(active_target_enc), + .O(s_axi_rdata[20])); + (* SOFT_HLUTNM = "soft_lutpair144" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[21]_INST_0 + (.I0(st_mr_rmesg[24]), + .I1(active_target_enc), + .O(s_axi_rdata[21])); + (* SOFT_HLUTNM = "soft_lutpair143" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[22]_INST_0 + (.I0(st_mr_rmesg[25]), + .I1(active_target_enc), + .O(s_axi_rdata[22])); + (* SOFT_HLUTNM = "soft_lutpair143" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[23]_INST_0 + (.I0(st_mr_rmesg[26]), + .I1(active_target_enc), + .O(s_axi_rdata[23])); + (* SOFT_HLUTNM = "soft_lutpair142" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[24]_INST_0 + (.I0(st_mr_rmesg[27]), + .I1(active_target_enc), + .O(s_axi_rdata[24])); + (* SOFT_HLUTNM = "soft_lutpair142" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[25]_INST_0 + (.I0(st_mr_rmesg[28]), + .I1(active_target_enc), + .O(s_axi_rdata[25])); + (* SOFT_HLUTNM = "soft_lutpair141" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[26]_INST_0 + (.I0(st_mr_rmesg[29]), + .I1(active_target_enc), + .O(s_axi_rdata[26])); + (* SOFT_HLUTNM = "soft_lutpair141" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[27]_INST_0 + (.I0(st_mr_rmesg[30]), + .I1(active_target_enc), + .O(s_axi_rdata[27])); + (* SOFT_HLUTNM = "soft_lutpair140" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[28]_INST_0 + (.I0(st_mr_rmesg[31]), + .I1(active_target_enc), + .O(s_axi_rdata[28])); + (* SOFT_HLUTNM = "soft_lutpair140" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[29]_INST_0 + (.I0(st_mr_rmesg[32]), + .I1(active_target_enc), + .O(s_axi_rdata[29])); + (* SOFT_HLUTNM = "soft_lutpair153" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[2]_INST_0 + (.I0(st_mr_rmesg[5]), + .I1(active_target_enc), + .O(s_axi_rdata[2])); + (* SOFT_HLUTNM = "soft_lutpair139" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[30]_INST_0 + (.I0(st_mr_rmesg[33]), + .I1(active_target_enc), + .O(s_axi_rdata[30])); + (* SOFT_HLUTNM = "soft_lutpair139" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[31]_INST_0 + (.I0(st_mr_rmesg[34]), + .I1(active_target_enc), + .O(s_axi_rdata[31])); + (* SOFT_HLUTNM = "soft_lutpair138" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[32]_INST_0 + (.I0(st_mr_rmesg[35]), + .I1(active_target_enc), + .O(s_axi_rdata[32])); + (* SOFT_HLUTNM = "soft_lutpair138" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[33]_INST_0 + (.I0(st_mr_rmesg[36]), + .I1(active_target_enc), + .O(s_axi_rdata[33])); + (* SOFT_HLUTNM = "soft_lutpair137" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[34]_INST_0 + (.I0(st_mr_rmesg[37]), + .I1(active_target_enc), + .O(s_axi_rdata[34])); + (* SOFT_HLUTNM = "soft_lutpair137" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[35]_INST_0 + (.I0(st_mr_rmesg[38]), + .I1(active_target_enc), + .O(s_axi_rdata[35])); + (* SOFT_HLUTNM = "soft_lutpair136" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[36]_INST_0 + (.I0(st_mr_rmesg[39]), + .I1(active_target_enc), + .O(s_axi_rdata[36])); + (* SOFT_HLUTNM = "soft_lutpair136" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[37]_INST_0 + (.I0(st_mr_rmesg[40]), + .I1(active_target_enc), + .O(s_axi_rdata[37])); + (* SOFT_HLUTNM = "soft_lutpair135" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[38]_INST_0 + (.I0(st_mr_rmesg[41]), + .I1(active_target_enc), + .O(s_axi_rdata[38])); + (* SOFT_HLUTNM = "soft_lutpair135" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[39]_INST_0 + (.I0(st_mr_rmesg[42]), + .I1(active_target_enc), + .O(s_axi_rdata[39])); + (* SOFT_HLUTNM = "soft_lutpair153" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[3]_INST_0 + (.I0(st_mr_rmesg[6]), + .I1(active_target_enc), + .O(s_axi_rdata[3])); + (* SOFT_HLUTNM = "soft_lutpair134" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[40]_INST_0 + (.I0(st_mr_rmesg[43]), + .I1(active_target_enc), + .O(s_axi_rdata[40])); + (* SOFT_HLUTNM = "soft_lutpair134" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[41]_INST_0 + (.I0(st_mr_rmesg[44]), + .I1(active_target_enc), + .O(s_axi_rdata[41])); + (* SOFT_HLUTNM = "soft_lutpair133" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[42]_INST_0 + (.I0(st_mr_rmesg[45]), + .I1(active_target_enc), + .O(s_axi_rdata[42])); + (* SOFT_HLUTNM = "soft_lutpair133" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[43]_INST_0 + (.I0(st_mr_rmesg[46]), + .I1(active_target_enc), + .O(s_axi_rdata[43])); + (* SOFT_HLUTNM = "soft_lutpair132" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[44]_INST_0 + (.I0(st_mr_rmesg[47]), + .I1(active_target_enc), + .O(s_axi_rdata[44])); + (* SOFT_HLUTNM = "soft_lutpair132" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[45]_INST_0 + (.I0(st_mr_rmesg[48]), + .I1(active_target_enc), + .O(s_axi_rdata[45])); + (* SOFT_HLUTNM = "soft_lutpair131" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[46]_INST_0 + (.I0(st_mr_rmesg[49]), + .I1(active_target_enc), + .O(s_axi_rdata[46])); + (* SOFT_HLUTNM = "soft_lutpair131" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[47]_INST_0 + (.I0(st_mr_rmesg[50]), + .I1(active_target_enc), + .O(s_axi_rdata[47])); + (* SOFT_HLUTNM = "soft_lutpair130" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[48]_INST_0 + (.I0(st_mr_rmesg[51]), + .I1(active_target_enc), + .O(s_axi_rdata[48])); + (* SOFT_HLUTNM = "soft_lutpair130" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[49]_INST_0 + (.I0(st_mr_rmesg[52]), + .I1(active_target_enc), + .O(s_axi_rdata[49])); + (* SOFT_HLUTNM = "soft_lutpair152" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[4]_INST_0 + (.I0(st_mr_rmesg[7]), + .I1(active_target_enc), + .O(s_axi_rdata[4])); + (* SOFT_HLUTNM = "soft_lutpair129" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[50]_INST_0 + (.I0(st_mr_rmesg[53]), + .I1(active_target_enc), + .O(s_axi_rdata[50])); + (* SOFT_HLUTNM = "soft_lutpair129" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[51]_INST_0 + (.I0(st_mr_rmesg[54]), + .I1(active_target_enc), + .O(s_axi_rdata[51])); + (* SOFT_HLUTNM = "soft_lutpair128" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[52]_INST_0 + (.I0(st_mr_rmesg[55]), + .I1(active_target_enc), + .O(s_axi_rdata[52])); + (* SOFT_HLUTNM = "soft_lutpair128" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[53]_INST_0 + (.I0(st_mr_rmesg[56]), + .I1(active_target_enc), + .O(s_axi_rdata[53])); + (* SOFT_HLUTNM = "soft_lutpair127" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[54]_INST_0 + (.I0(st_mr_rmesg[57]), + .I1(active_target_enc), + .O(s_axi_rdata[54])); + (* SOFT_HLUTNM = "soft_lutpair127" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[55]_INST_0 + (.I0(st_mr_rmesg[58]), + .I1(active_target_enc), + .O(s_axi_rdata[55])); + (* SOFT_HLUTNM = "soft_lutpair126" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[56]_INST_0 + (.I0(st_mr_rmesg[59]), + .I1(active_target_enc), + .O(s_axi_rdata[56])); + (* SOFT_HLUTNM = "soft_lutpair126" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[57]_INST_0 + (.I0(st_mr_rmesg[60]), + .I1(active_target_enc), + .O(s_axi_rdata[57])); + (* SOFT_HLUTNM = "soft_lutpair125" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[58]_INST_0 + (.I0(st_mr_rmesg[61]), + .I1(active_target_enc), + .O(s_axi_rdata[58])); + (* SOFT_HLUTNM = "soft_lutpair125" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[59]_INST_0 + (.I0(st_mr_rmesg[62]), + .I1(active_target_enc), + .O(s_axi_rdata[59])); + (* SOFT_HLUTNM = "soft_lutpair152" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[5]_INST_0 + (.I0(st_mr_rmesg[8]), + .I1(active_target_enc), + .O(s_axi_rdata[5])); + (* SOFT_HLUTNM = "soft_lutpair124" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[60]_INST_0 + (.I0(st_mr_rmesg[63]), + .I1(active_target_enc), + .O(s_axi_rdata[60])); + (* SOFT_HLUTNM = "soft_lutpair124" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[61]_INST_0 + (.I0(st_mr_rmesg[64]), + .I1(active_target_enc), + .O(s_axi_rdata[61])); + (* SOFT_HLUTNM = "soft_lutpair123" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[62]_INST_0 + (.I0(st_mr_rmesg[65]), + .I1(active_target_enc), + .O(s_axi_rdata[62])); + (* SOFT_HLUTNM = "soft_lutpair123" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[63]_INST_0 + (.I0(st_mr_rmesg[66]), + .I1(active_target_enc), + .O(s_axi_rdata[63])); + (* SOFT_HLUTNM = "soft_lutpair151" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[6]_INST_0 + (.I0(st_mr_rmesg[9]), + .I1(active_target_enc), + .O(s_axi_rdata[6])); + (* SOFT_HLUTNM = "soft_lutpair151" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[7]_INST_0 + (.I0(st_mr_rmesg[10]), + .I1(active_target_enc), + .O(s_axi_rdata[7])); + (* SOFT_HLUTNM = "soft_lutpair150" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[8]_INST_0 + (.I0(st_mr_rmesg[11]), + .I1(active_target_enc), + .O(s_axi_rdata[8])); + (* SOFT_HLUTNM = "soft_lutpair150" *) + LUT2 #( + .INIT(4'h2)) + \s_axi_rdata[9]_INST_0 + (.I0(st_mr_rmesg[12]), + .I1(active_target_enc), + .O(s_axi_rdata[9])); + LUT5 #( + .INIT(32'hD5D5FFD5)) + s_ready_i_i_1__2 + (.I0(m_valid_i_reg_0), + .I1(active_target_hot_0), + .I2(s_axi_rready), + .I3(\m_axi_rready[0] ), + .I4(m_axi_rvalid), + .O(s_ready_i_i_1__2_n_0)); + FDRE s_ready_i_reg + (.C(aclk), + .CE(1'b1), + .D(s_ready_i_i_1__2_n_0), + .Q(\m_axi_rready[0] ), + .R(p_1_in)); + FDRE \skid_buffer_reg[0] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[0]), + .Q(\skid_buffer_reg_n_0_[0] ), + .R(1'b0)); + FDRE \skid_buffer_reg[10] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[10]), + .Q(\skid_buffer_reg_n_0_[10] ), + .R(1'b0)); + FDRE \skid_buffer_reg[11] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[11]), + .Q(\skid_buffer_reg_n_0_[11] ), + .R(1'b0)); + FDRE \skid_buffer_reg[12] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[12]), + .Q(\skid_buffer_reg_n_0_[12] ), + .R(1'b0)); + FDRE \skid_buffer_reg[13] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[13]), + .Q(\skid_buffer_reg_n_0_[13] ), + .R(1'b0)); + FDRE \skid_buffer_reg[14] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[14]), + .Q(\skid_buffer_reg_n_0_[14] ), + .R(1'b0)); + FDRE \skid_buffer_reg[15] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[15]), + .Q(\skid_buffer_reg_n_0_[15] ), + .R(1'b0)); + FDRE \skid_buffer_reg[16] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[16]), + .Q(\skid_buffer_reg_n_0_[16] ), + .R(1'b0)); + FDRE \skid_buffer_reg[17] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[17]), + .Q(\skid_buffer_reg_n_0_[17] ), + .R(1'b0)); + FDRE \skid_buffer_reg[18] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[18]), + .Q(\skid_buffer_reg_n_0_[18] ), + .R(1'b0)); + FDRE \skid_buffer_reg[19] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[19]), + .Q(\skid_buffer_reg_n_0_[19] ), + .R(1'b0)); + FDRE \skid_buffer_reg[1] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[1]), + .Q(\skid_buffer_reg_n_0_[1] ), + .R(1'b0)); + FDRE \skid_buffer_reg[20] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[20]), + .Q(\skid_buffer_reg_n_0_[20] ), + .R(1'b0)); + FDRE \skid_buffer_reg[21] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[21]), + .Q(\skid_buffer_reg_n_0_[21] ), + .R(1'b0)); + FDRE \skid_buffer_reg[22] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[22]), + .Q(\skid_buffer_reg_n_0_[22] ), + .R(1'b0)); + FDRE \skid_buffer_reg[23] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[23]), + .Q(\skid_buffer_reg_n_0_[23] ), + .R(1'b0)); + FDRE \skid_buffer_reg[24] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[24]), + .Q(\skid_buffer_reg_n_0_[24] ), + .R(1'b0)); + FDRE \skid_buffer_reg[25] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[25]), + .Q(\skid_buffer_reg_n_0_[25] ), + .R(1'b0)); + FDRE \skid_buffer_reg[26] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[26]), + .Q(\skid_buffer_reg_n_0_[26] ), + .R(1'b0)); + FDRE \skid_buffer_reg[27] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[27]), + .Q(\skid_buffer_reg_n_0_[27] ), + .R(1'b0)); + FDRE \skid_buffer_reg[28] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[28]), + .Q(\skid_buffer_reg_n_0_[28] ), + .R(1'b0)); + FDRE \skid_buffer_reg[29] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[29]), + .Q(\skid_buffer_reg_n_0_[29] ), + .R(1'b0)); + FDRE \skid_buffer_reg[2] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[2]), + .Q(\skid_buffer_reg_n_0_[2] ), + .R(1'b0)); + FDRE \skid_buffer_reg[30] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[30]), + .Q(\skid_buffer_reg_n_0_[30] ), + .R(1'b0)); + FDRE \skid_buffer_reg[31] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[31]), + .Q(\skid_buffer_reg_n_0_[31] ), + .R(1'b0)); + FDRE \skid_buffer_reg[32] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[32]), + .Q(\skid_buffer_reg_n_0_[32] ), + .R(1'b0)); + FDRE \skid_buffer_reg[33] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[33]), + .Q(\skid_buffer_reg_n_0_[33] ), + .R(1'b0)); + FDRE \skid_buffer_reg[34] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[34]), + .Q(\skid_buffer_reg_n_0_[34] ), + .R(1'b0)); + FDRE \skid_buffer_reg[35] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[35]), + .Q(\skid_buffer_reg_n_0_[35] ), + .R(1'b0)); + FDRE \skid_buffer_reg[36] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[36]), + .Q(\skid_buffer_reg_n_0_[36] ), + .R(1'b0)); + FDRE \skid_buffer_reg[37] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[37]), + .Q(\skid_buffer_reg_n_0_[37] ), + .R(1'b0)); + FDRE \skid_buffer_reg[38] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[38]), + .Q(\skid_buffer_reg_n_0_[38] ), + .R(1'b0)); + FDRE \skid_buffer_reg[39] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[39]), + .Q(\skid_buffer_reg_n_0_[39] ), + .R(1'b0)); + FDRE \skid_buffer_reg[3] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[3]), + .Q(\skid_buffer_reg_n_0_[3] ), + .R(1'b0)); + FDRE \skid_buffer_reg[40] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[40]), + .Q(\skid_buffer_reg_n_0_[40] ), + .R(1'b0)); + FDRE \skid_buffer_reg[41] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[41]), + .Q(\skid_buffer_reg_n_0_[41] ), + .R(1'b0)); + FDRE \skid_buffer_reg[42] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[42]), + .Q(\skid_buffer_reg_n_0_[42] ), + .R(1'b0)); + FDRE \skid_buffer_reg[43] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[43]), + .Q(\skid_buffer_reg_n_0_[43] ), + .R(1'b0)); + FDRE \skid_buffer_reg[44] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[44]), + .Q(\skid_buffer_reg_n_0_[44] ), + .R(1'b0)); + FDRE \skid_buffer_reg[45] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[45]), + .Q(\skid_buffer_reg_n_0_[45] ), + .R(1'b0)); + FDRE \skid_buffer_reg[46] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[46]), + .Q(\skid_buffer_reg_n_0_[46] ), + .R(1'b0)); + FDRE \skid_buffer_reg[47] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[47]), + .Q(\skid_buffer_reg_n_0_[47] ), + .R(1'b0)); + FDRE \skid_buffer_reg[48] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[48]), + .Q(\skid_buffer_reg_n_0_[48] ), + .R(1'b0)); + FDRE \skid_buffer_reg[49] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[49]), + .Q(\skid_buffer_reg_n_0_[49] ), + .R(1'b0)); + FDRE \skid_buffer_reg[4] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[4]), + .Q(\skid_buffer_reg_n_0_[4] ), + .R(1'b0)); + FDRE \skid_buffer_reg[50] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[50]), + .Q(\skid_buffer_reg_n_0_[50] ), + .R(1'b0)); + FDRE \skid_buffer_reg[51] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[51]), + .Q(\skid_buffer_reg_n_0_[51] ), + .R(1'b0)); + FDRE \skid_buffer_reg[52] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[52]), + .Q(\skid_buffer_reg_n_0_[52] ), + .R(1'b0)); + FDRE \skid_buffer_reg[53] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[53]), + .Q(\skid_buffer_reg_n_0_[53] ), + .R(1'b0)); + FDRE \skid_buffer_reg[54] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[54]), + .Q(\skid_buffer_reg_n_0_[54] ), + .R(1'b0)); + FDRE \skid_buffer_reg[55] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[55]), + .Q(\skid_buffer_reg_n_0_[55] ), + .R(1'b0)); + FDRE \skid_buffer_reg[56] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[56]), + .Q(\skid_buffer_reg_n_0_[56] ), + .R(1'b0)); + FDRE \skid_buffer_reg[57] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[57]), + .Q(\skid_buffer_reg_n_0_[57] ), + .R(1'b0)); + FDRE \skid_buffer_reg[58] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[58]), + .Q(\skid_buffer_reg_n_0_[58] ), + .R(1'b0)); + FDRE \skid_buffer_reg[59] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[59]), + .Q(\skid_buffer_reg_n_0_[59] ), + .R(1'b0)); + FDRE \skid_buffer_reg[5] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[5]), + .Q(\skid_buffer_reg_n_0_[5] ), + .R(1'b0)); + FDRE \skid_buffer_reg[60] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[60]), + .Q(\skid_buffer_reg_n_0_[60] ), + .R(1'b0)); + FDRE \skid_buffer_reg[61] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[61]), + .Q(\skid_buffer_reg_n_0_[61] ), + .R(1'b0)); + FDRE \skid_buffer_reg[62] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[62]), + .Q(\skid_buffer_reg_n_0_[62] ), + .R(1'b0)); + FDRE \skid_buffer_reg[63] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[63]), + .Q(\skid_buffer_reg_n_0_[63] ), + .R(1'b0)); + FDRE \skid_buffer_reg[64] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rresp[0]), + .Q(\skid_buffer_reg_n_0_[64] ), + .R(1'b0)); + FDRE \skid_buffer_reg[65] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rresp[1]), + .Q(\skid_buffer_reg_n_0_[65] ), + .R(1'b0)); + FDRE \skid_buffer_reg[66] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rlast), + .Q(\skid_buffer_reg_n_0_[66] ), + .R(1'b0)); + FDRE \skid_buffer_reg[6] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[6]), + .Q(\skid_buffer_reg_n_0_[6] ), + .R(1'b0)); + FDRE \skid_buffer_reg[7] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[7]), + .Q(\skid_buffer_reg_n_0_[7] ), + .R(1'b0)); + FDRE \skid_buffer_reg[8] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[8]), + .Q(\skid_buffer_reg_n_0_[8] ), + .R(1'b0)); + FDRE \skid_buffer_reg[9] + (.C(aclk), + .CE(\m_axi_rready[0] ), + .D(m_axi_rdata[9]), + .Q(\skid_buffer_reg_n_0_[9] ), + .R(1'b0)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_1/Arty_Z7_20_xbar_1_sim_netlist.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_1/Arty_Z7_20_xbar_1_sim_netlist.vhdl new file mode 100644 index 0000000..5f79db1 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_1/Arty_Z7_20_xbar_1_sim_netlist.vhdl @@ -0,0 +1,10589 @@ +-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +-- Date : Sat Mar 04 18:57:49 2017 +-- Host : WK73 running 64-bit Service Pack 1 (build 7601) +-- Command : write_vhdl -force -mode funcsim -rename_top Arty_Z7_20_xbar_1 -prefix +-- Arty_Z7_20_xbar_1_ Arty_Z7_20_xbar_1_sim_netlist.vhdl +-- Design : Arty_Z7_20_xbar_1 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z020clg400-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_addr_arbiter is + port ( + aa_mi_arvalid : out STD_LOGIC; + \s_axi_arready[0]\ : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_single_thread.active_target_hot_reg[0]\ : out STD_LOGIC; + \gen_single_thread.active_target_enc_reg[0]\ : out STD_LOGIC; + \gen_master_slots[0].r_issuing_cnt_reg[0]\ : out STD_LOGIC; + \gen_master_slots[1].r_issuing_cnt_reg[8]\ : out STD_LOGIC; + \gen_arbiter.m_target_hot_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_arbiter.qual_reg_reg[0]_0\ : out STD_LOGIC; + \gen_axi.s_axi_rlast_i_reg\ : out STD_LOGIC; + \m_axi_arqos[3]\ : out STD_LOGIC_VECTOR ( 56 downto 0 ); + m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_master_slots[0].r_issuing_cnt_reg[3]\ : in STD_LOGIC; + aclk : in STD_LOGIC; + st_aa_arvalid_qual : in STD_LOGIC_VECTOR ( 0 to 0 ); + \valid_qual_i1__0\ : in STD_LOGIC; + mi_arready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 ); + aresetn_d : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 56 downto 0 ); + active_target_hot : in STD_LOGIC_VECTOR ( 0 to 0 ); + active_target_enc : in STD_LOGIC; + s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_master_slots[0].r_issuing_cnt_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + m_valid_i_reg : in STD_LOGIC; + p_11_in : in STD_LOGIC + ); +end Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_addr_arbiter; + +architecture STRUCTURE of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_addr_arbiter is + signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal aa_mi_artarget_hot : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^aa_mi_arvalid\ : STD_LOGIC; + signal \gen_arbiter.any_grant_i_1__0_n_0\ : STD_LOGIC; + signal \gen_arbiter.any_grant_i_2__0_n_0\ : STD_LOGIC; + signal \gen_arbiter.any_grant_i_3_n_0\ : STD_LOGIC; + signal \gen_arbiter.any_grant_reg_n_0\ : STD_LOGIC; + signal \gen_arbiter.grant_hot[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_arbiter.grant_hot_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_arbiter.last_rr_hot[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_arbiter.last_rr_hot[1]_i_2_n_0\ : STD_LOGIC; + signal \gen_arbiter.last_rr_hot[1]_i_3_n_0\ : STD_LOGIC; + signal \gen_arbiter.last_rr_hot_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_arbiter.m_target_hot_i[1]_i_1__0_n_0\ : STD_LOGIC; + signal \^gen_arbiter.m_target_hot_i_reg[0]_0\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \gen_arbiter.m_valid_i_i_1__0_n_0\ : STD_LOGIC; + signal \gen_arbiter.s_ready_i[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_axi.s_axi_rlast_i_i_4_n_0\ : STD_LOGIC; + signal \^gen_master_slots[0].r_issuing_cnt_reg[0]\ : STD_LOGIC; + signal grant_hot : STD_LOGIC; + signal \^m_axi_arqos[3]\ : STD_LOGIC_VECTOR ( 56 downto 0 ); + signal p_1_in : STD_LOGIC; + signal p_2_in : STD_LOGIC; + signal qual_reg : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^s_axi_arready[0]\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \gen_arbiter.any_grant_i_2__0\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \gen_arbiter.last_rr_hot[0]_i_1\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \gen_arbiter.last_rr_hot[1]_i_2\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \gen_arbiter.last_rr_hot[1]_i_3\ : label is "soft_lutpair2"; + attribute SOFT_HLUTNM of \gen_arbiter.m_target_hot_i[0]_i_1__0\ : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \gen_arbiter.m_target_hot_i[1]_i_1__0\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \gen_arbiter.s_ready_i[0]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_3\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[8]_i_2\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \gen_single_thread.active_target_enc[0]_i_1__0\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \gen_single_thread.active_target_hot[0]_i_1__0\ : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \m_axi_arvalid[0]_INST_0\ : label is "soft_lutpair4"; +begin + Q(0) <= \^q\(0); + aa_mi_arvalid <= \^aa_mi_arvalid\; + \gen_arbiter.m_target_hot_i_reg[0]_0\(0) <= \^gen_arbiter.m_target_hot_i_reg[0]_0\(0); + \gen_master_slots[0].r_issuing_cnt_reg[0]\ <= \^gen_master_slots[0].r_issuing_cnt_reg[0]\; + \m_axi_arqos[3]\(56 downto 0) <= \^m_axi_arqos[3]\(56 downto 0); + \s_axi_arready[0]\ <= \^s_axi_arready[0]\; +\gen_arbiter.any_grant_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000EAAA2AAA" + ) + port map ( + I0 => \gen_arbiter.any_grant_reg_n_0\, + I1 => st_aa_arvalid_qual(0), + I2 => \gen_arbiter.any_grant_i_2__0_n_0\, + I3 => \valid_qual_i1__0\, + I4 => \gen_arbiter.last_rr_hot[0]_i_1_n_0\, + I5 => \gen_arbiter.any_grant_i_3_n_0\, + O => \gen_arbiter.any_grant_i_1__0_n_0\ + ); +\gen_arbiter.any_grant_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000E0000" + ) + port map ( + I0 => p_2_in, + I1 => \gen_arbiter.last_rr_hot_reg_n_0_[0]\, + I2 => \gen_arbiter.any_grant_reg_n_0\, + I3 => \^aa_mi_arvalid\, + I4 => \gen_arbiter.last_rr_hot[1]_i_3_n_0\, + O => \gen_arbiter.any_grant_i_2__0_n_0\ + ); +\gen_arbiter.any_grant_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFD5D5D555555555" + ) + port map ( + I0 => aresetn_d, + I1 => \^q\(0), + I2 => mi_arready(0), + I3 => m_axi_arready(0), + I4 => aa_mi_artarget_hot(0), + I5 => \^aa_mi_arvalid\, + O => \gen_arbiter.any_grant_i_3_n_0\ + ); +\gen_arbiter.any_grant_reg\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \gen_arbiter.any_grant_i_1__0_n_0\, + Q => \gen_arbiter.any_grant_reg_n_0\, + R => '0' + ); +\gen_arbiter.grant_hot[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000EAAA2AAA" + ) + port map ( + I0 => \gen_arbiter.grant_hot_reg_n_0_[0]\, + I1 => st_aa_arvalid_qual(0), + I2 => \gen_arbiter.any_grant_i_2__0_n_0\, + I3 => \valid_qual_i1__0\, + I4 => \gen_arbiter.last_rr_hot[0]_i_1_n_0\, + I5 => \gen_arbiter.any_grant_i_3_n_0\, + O => \gen_arbiter.grant_hot[0]_i_1_n_0\ + ); +\gen_arbiter.grant_hot_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \gen_arbiter.grant_hot[0]_i_1_n_0\, + Q => \gen_arbiter.grant_hot_reg_n_0_[0]\, + R => '0' + ); +\gen_arbiter.last_rr_hot[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"40404000" + ) + port map ( + I0 => \^s_axi_arready[0]\, + I1 => qual_reg(0), + I2 => s_axi_arvalid(0), + I3 => \gen_arbiter.last_rr_hot_reg_n_0_[0]\, + I4 => p_2_in, + O => \gen_arbiter.last_rr_hot[0]_i_1_n_0\ + ); +\gen_arbiter.last_rr_hot[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0008000000000000" + ) + port map ( + I0 => \valid_qual_i1__0\, + I1 => \gen_arbiter.last_rr_hot[1]_i_2_n_0\, + I2 => \gen_arbiter.any_grant_reg_n_0\, + I3 => \^aa_mi_arvalid\, + I4 => \gen_arbiter.last_rr_hot[1]_i_3_n_0\, + I5 => st_aa_arvalid_qual(0), + O => grant_hot + ); +\gen_arbiter.last_rr_hot[1]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => p_2_in, + I1 => \gen_arbiter.last_rr_hot_reg_n_0_[0]\, + O => \gen_arbiter.last_rr_hot[1]_i_2_n_0\ + ); +\gen_arbiter.last_rr_hot[1]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => s_axi_arvalid(0), + I1 => qual_reg(0), + I2 => \^s_axi_arready[0]\, + O => \gen_arbiter.last_rr_hot[1]_i_3_n_0\ + ); +\gen_arbiter.last_rr_hot_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => grant_hot, + D => \gen_arbiter.last_rr_hot[0]_i_1_n_0\, + Q => \gen_arbiter.last_rr_hot_reg_n_0_[0]\, + R => SR(0) + ); +\gen_arbiter.last_rr_hot_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => aclk, + CE => grant_hot, + D => '0', + Q => p_2_in, + S => SR(0) + ); +\gen_arbiter.m_mesg_i[32]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^aa_mi_arvalid\, + O => p_1_in + ); +\gen_arbiter.m_mesg_i_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(9), + Q => \^m_axi_arqos[3]\(9), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(10), + Q => \^m_axi_arqos[3]\(10), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(11), + Q => \^m_axi_arqos[3]\(11), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(12), + Q => \^m_axi_arqos[3]\(12), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(13), + Q => \^m_axi_arqos[3]\(13), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(14), + Q => \^m_axi_arqos[3]\(14), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(15), + Q => \^m_axi_arqos[3]\(15), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(16), + Q => \^m_axi_arqos[3]\(16), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(17), + Q => \^m_axi_arqos[3]\(17), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(18), + Q => \^m_axi_arqos[3]\(18), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(0), + Q => \^m_axi_arqos[3]\(0), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(19), + Q => \^m_axi_arqos[3]\(19), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(20), + Q => \^m_axi_arqos[3]\(20), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(21), + Q => \^m_axi_arqos[3]\(21), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(22), + Q => \^m_axi_arqos[3]\(22), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(23), + Q => \^m_axi_arqos[3]\(23), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(24), + Q => \^m_axi_arqos[3]\(24), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[26]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(25), + Q => \^m_axi_arqos[3]\(25), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[27]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(26), + Q => \^m_axi_arqos[3]\(26), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[28]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(27), + Q => \^m_axi_arqos[3]\(27), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[29]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(28), + Q => \^m_axi_arqos[3]\(28), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(1), + Q => \^m_axi_arqos[3]\(1), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(29), + Q => \^m_axi_arqos[3]\(29), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(30), + Q => \^m_axi_arqos[3]\(30), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[32]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(31), + Q => \^m_axi_arqos[3]\(31), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[33]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(32), + Q => \^m_axi_arqos[3]\(32), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[34]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(33), + Q => \^m_axi_arqos[3]\(33), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[35]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(34), + Q => \^m_axi_arqos[3]\(34), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[36]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(35), + Q => \^m_axi_arqos[3]\(35), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[37]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(36), + Q => \^m_axi_arqos[3]\(36), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[38]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(37), + Q => \^m_axi_arqos[3]\(37), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[39]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(38), + Q => \^m_axi_arqos[3]\(38), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(2), + Q => \^m_axi_arqos[3]\(2), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[40]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(39), + Q => \^m_axi_arqos[3]\(39), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[41]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(40), + Q => \^m_axi_arqos[3]\(40), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[42]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(41), + Q => \^m_axi_arqos[3]\(41), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[43]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(42), + Q => \^m_axi_arqos[3]\(42), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[44]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(43), + Q => \^m_axi_arqos[3]\(43), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[46]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(44), + Q => \^m_axi_arqos[3]\(44), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[47]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(45), + Q => \^m_axi_arqos[3]\(45), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[48]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(46), + Q => \^m_axi_arqos[3]\(46), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(3), + Q => \^m_axi_arqos[3]\(3), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[53]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(47), + Q => \^m_axi_arqos[3]\(47), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[54]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(48), + Q => \^m_axi_arqos[3]\(48), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[55]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(49), + Q => \^m_axi_arqos[3]\(49), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[56]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(50), + Q => \^m_axi_arqos[3]\(50), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[57]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(51), + Q => \^m_axi_arqos[3]\(51), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[58]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(52), + Q => \^m_axi_arqos[3]\(52), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[59]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(53), + Q => \^m_axi_arqos[3]\(53), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(4), + Q => \^m_axi_arqos[3]\(4), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[60]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(54), + Q => \^m_axi_arqos[3]\(54), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[61]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(55), + Q => \^m_axi_arqos[3]\(55), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[62]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(56), + Q => \^m_axi_arqos[3]\(56), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(5), + Q => \^m_axi_arqos[3]\(5), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(6), + Q => \^m_axi_arqos[3]\(6), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(7), + Q => \^m_axi_arqos[3]\(7), + R => SR(0) + ); +\gen_arbiter.m_mesg_i_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => D(8), + Q => \^m_axi_arqos[3]\(8), + R => SR(0) + ); +\gen_arbiter.m_target_hot_i[0]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"01" + ) + port map ( + I0 => D(31), + I1 => D(30), + I2 => D(29), + O => \^gen_arbiter.m_target_hot_i_reg[0]_0\(0) + ); +\gen_arbiter.m_target_hot_i[1]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => D(29), + I1 => D(30), + I2 => D(31), + O => \gen_arbiter.m_target_hot_i[1]_i_1__0_n_0\ + ); +\gen_arbiter.m_target_hot_i_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => grant_hot, + D => \^gen_arbiter.m_target_hot_i_reg[0]_0\(0), + Q => aa_mi_artarget_hot(0), + R => SR(0) + ); +\gen_arbiter.m_target_hot_i_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => grant_hot, + D => \gen_arbiter.m_target_hot_i[1]_i_1__0_n_0\, + Q => \^q\(0), + R => SR(0) + ); +\gen_arbiter.m_valid_i_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"003F3F3FAAAAAAAA" + ) + port map ( + I0 => \gen_arbiter.any_grant_reg_n_0\, + I1 => \^q\(0), + I2 => mi_arready(0), + I3 => m_axi_arready(0), + I4 => aa_mi_artarget_hot(0), + I5 => \^aa_mi_arvalid\, + O => \gen_arbiter.m_valid_i_i_1__0_n_0\ + ); +\gen_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \gen_arbiter.m_valid_i_i_1__0_n_0\, + Q => \^aa_mi_arvalid\, + R => SR(0) + ); +\gen_arbiter.qual_reg[0]_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => \gen_master_slots[0].r_issuing_cnt_reg[3]_0\(2), + I1 => \gen_master_slots[0].r_issuing_cnt_reg[3]_0\(1), + I2 => \gen_master_slots[0].r_issuing_cnt_reg[3]_0\(0), + O => \gen_arbiter.qual_reg_reg[0]_0\ + ); +\gen_arbiter.qual_reg_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \gen_master_slots[0].r_issuing_cnt_reg[3]\, + Q => qual_reg(0), + R => SR(0) + ); +\gen_arbiter.s_ready_i[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0800" + ) + port map ( + I0 => \gen_arbiter.grant_hot_reg_n_0_[0]\, + I1 => aresetn_d, + I2 => \^aa_mi_arvalid\, + I3 => \gen_arbiter.any_grant_reg_n_0\, + O => \gen_arbiter.s_ready_i[0]_i_1_n_0\ + ); +\gen_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \gen_arbiter.s_ready_i[0]_i_1_n_0\, + Q => \^s_axi_arready[0]\, + R => '0' + ); +\gen_axi.s_axi_rlast_i_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0002" + ) + port map ( + I0 => \gen_axi.s_axi_rlast_i_i_4_n_0\, + I1 => p_11_in, + I2 => \^m_axi_arqos[3]\(32), + I3 => \^m_axi_arqos[3]\(33), + O => \gen_axi.s_axi_rlast_i_reg\ + ); +\gen_axi.s_axi_rlast_i_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000001" + ) + port map ( + I0 => \^m_axi_arqos[3]\(34), + I1 => \^m_axi_arqos[3]\(35), + I2 => \^m_axi_arqos[3]\(36), + I3 => \^m_axi_arqos[3]\(37), + I4 => \^m_axi_arqos[3]\(39), + I5 => \^m_axi_arqos[3]\(38), + O => \gen_axi.s_axi_rlast_i_i_4_n_0\ + ); +\gen_master_slots[0].r_issuing_cnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000FFFFFFFE0000" + ) + port map ( + I0 => \gen_master_slots[0].r_issuing_cnt_reg[3]_0\(3), + I1 => \gen_master_slots[0].r_issuing_cnt_reg[3]_0\(2), + I2 => \gen_master_slots[0].r_issuing_cnt_reg[3]_0\(1), + I3 => \gen_master_slots[0].r_issuing_cnt_reg[3]_0\(0), + I4 => \^gen_master_slots[0].r_issuing_cnt_reg[0]\, + I5 => m_valid_i_reg, + O => E(0) + ); +\gen_master_slots[0].r_issuing_cnt[3]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"7F" + ) + port map ( + I0 => \^aa_mi_arvalid\, + I1 => aa_mi_artarget_hot(0), + I2 => m_axi_arready(0), + O => \^gen_master_slots[0].r_issuing_cnt_reg[0]\ + ); +\gen_master_slots[1].r_issuing_cnt[8]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"7F" + ) + port map ( + I0 => \^aa_mi_arvalid\, + I1 => \^q\(0), + I2 => mi_arready(0), + O => \gen_master_slots[1].r_issuing_cnt_reg[8]\ + ); +\gen_single_thread.active_target_enc[0]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FEFFFE00" + ) + port map ( + I0 => D(29), + I1 => D(30), + I2 => D(31), + I3 => \^s_axi_arready[0]\, + I4 => active_target_enc, + O => \gen_single_thread.active_target_enc_reg[0]\ + ); +\gen_single_thread.active_target_hot[0]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01FF0100" + ) + port map ( + I0 => D(31), + I1 => D(30), + I2 => D(29), + I3 => \^s_axi_arready[0]\, + I4 => active_target_hot(0), + O => \gen_single_thread.active_target_hot_reg[0]\ + ); +\m_axi_arvalid[0]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => aa_mi_artarget_hot(0), + I1 => \^aa_mi_arvalid\, + O => m_axi_arvalid(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_addr_arbiter_0 is + port ( + aa_wm_awgrant_enc : out STD_LOGIC; + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + aa_sa_awvalid : out STD_LOGIC; + ss_aa_awready : out STD_LOGIC_VECTOR ( 0 to 0 ); + \storage_data1_reg[0]\ : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); + sa_wm_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_master_slots[1].w_issuing_cnt_reg[8]\ : out STD_LOGIC; + \m_ready_d_reg[1]\ : out STD_LOGIC; + sel_4 : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \gen_arbiter.qual_reg_reg[1]_0\ : out STD_LOGIC; + m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + \storage_data1_reg[0]_0\ : out STD_LOGIC; + m_valid_i_reg : out STD_LOGIC; + \m_ready_d_reg[1]_0\ : out STD_LOGIC; + \m_axi_awqos[3]\ : out STD_LOGIC_VECTOR ( 57 downto 0 ); + aclk : in STD_LOGIC; + \m_ready_d_reg[0]\ : in STD_LOGIC; + st_aa_awvalid_qual : in STD_LOGIC_VECTOR ( 0 to 0 ); + valid_qual_i111_in : in STD_LOGIC; + \gen_arbiter.m_valid_i_reg_0\ : in STD_LOGIC; + aa_sa_awready : in STD_LOGIC; + aresetn_d : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_ready_d : in STD_LOGIC_VECTOR ( 1 downto 0 ); + mi_awready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_ready_d_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + \gen_master_slots[0].w_issuing_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \gen_single_thread.active_target_hot_reg[0]\ : in STD_LOGIC; + m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_addr_arbiter_0 : entity is "axi_crossbar_v2_1_12_addr_arbiter"; +end Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_addr_arbiter_0; + +architecture STRUCTURE of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_addr_arbiter_0 is + signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^aa_sa_awvalid\ : STD_LOGIC; + signal \^aa_wm_awgrant_enc\ : STD_LOGIC; + signal \gen_arbiter.any_grant_i_1_n_0\ : STD_LOGIC; + signal \gen_arbiter.any_grant_reg_n_0\ : STD_LOGIC; + signal \gen_arbiter.grant_hot[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_arbiter.grant_hot[1]_i_2_n_0\ : STD_LOGIC; + signal \gen_arbiter.grant_hot_reg_n_0_[1]\ : STD_LOGIC; + signal \gen_arbiter.m_grant_enc_i[0]_i_2_n_0\ : STD_LOGIC; + signal \gen_arbiter.m_valid_i_i_1_n_0\ : STD_LOGIC; + signal \gen_arbiter.s_ready_i[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0\ : STD_LOGIC; + signal \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\ : STD_LOGIC; + signal grant_hot : STD_LOGIC; + signal m_mesg_mux : STD_LOGIC_VECTOR ( 62 downto 1 ); + signal m_target_hot_mux : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal p_1_in : STD_LOGIC; + signal p_2_in : STD_LOGIC; + signal qual_reg : STD_LOGIC_VECTOR ( 1 to 1 ); + signal \^sel_4\ : STD_LOGIC; + signal \^ss_aa_awready\ : STD_LOGIC_VECTOR ( 0 to 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \gen_arbiter.grant_hot[1]_i_2\ : label is "soft_lutpair9"; + attribute SOFT_HLUTNM of \gen_arbiter.m_grant_enc_i[0]_i_5\ : label is "soft_lutpair13"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[10]_i_1\ : label is "soft_lutpair38"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[11]_i_1\ : label is "soft_lutpair37"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[12]_i_1\ : label is "soft_lutpair37"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[13]_i_1\ : label is "soft_lutpair36"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[14]_i_1\ : label is "soft_lutpair36"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[15]_i_1\ : label is "soft_lutpair35"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[16]_i_1\ : label is "soft_lutpair35"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[17]_i_1\ : label is "soft_lutpair34"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[18]_i_1\ : label is "soft_lutpair34"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[19]_i_1\ : label is "soft_lutpair33"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[1]_i_1\ : label is "soft_lutpair42"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[20]_i_1\ : label is "soft_lutpair33"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[21]_i_1\ : label is "soft_lutpair32"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[22]_i_1\ : label is "soft_lutpair32"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[23]_i_1\ : label is "soft_lutpair31"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[24]_i_1\ : label is "soft_lutpair31"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[25]_i_1\ : label is "soft_lutpair30"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[26]_i_1\ : label is "soft_lutpair30"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[27]_i_1\ : label is "soft_lutpair29"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[28]_i_1\ : label is "soft_lutpair29"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[29]_i_1\ : label is "soft_lutpair28"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[2]_i_1\ : label is "soft_lutpair42"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[30]_i_1\ : label is "soft_lutpair28"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[31]_i_1\ : label is "soft_lutpair27"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[32]_i_1__0\ : label is "soft_lutpair14"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[33]_i_1\ : label is "soft_lutpair27"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[34]_i_1\ : label is "soft_lutpair26"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[35]_i_1\ : label is "soft_lutpair26"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[36]_i_1\ : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[37]_i_1\ : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[38]_i_1\ : label is "soft_lutpair24"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[39]_i_1\ : label is "soft_lutpair24"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[3]_i_1\ : label is "soft_lutpair41"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[40]_i_1\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[41]_i_1\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[42]_i_1\ : label is "soft_lutpair22"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[43]_i_1\ : label is "soft_lutpair22"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[44]_i_1\ : label is "soft_lutpair21"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[46]_i_1\ : label is "soft_lutpair21"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[47]_i_1\ : label is "soft_lutpair20"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[48]_i_1\ : label is "soft_lutpair20"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[4]_i_1\ : label is "soft_lutpair41"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[53]_i_1\ : label is "soft_lutpair19"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[54]_i_1\ : label is "soft_lutpair19"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[55]_i_1\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[56]_i_1\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[57]_i_1\ : label is "soft_lutpair17"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[58]_i_1\ : label is "soft_lutpair17"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[59]_i_1\ : label is "soft_lutpair16"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[5]_i_1\ : label is "soft_lutpair40"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[60]_i_1\ : label is "soft_lutpair16"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[61]_i_1\ : label is "soft_lutpair15"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[62]_i_1\ : label is "soft_lutpair15"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[6]_i_1\ : label is "soft_lutpair40"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[7]_i_1\ : label is "soft_lutpair39"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[8]_i_1\ : label is "soft_lutpair39"; + attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[9]_i_1\ : label is "soft_lutpair38"; + attribute SOFT_HLUTNM of \gen_arbiter.m_target_hot_i[1]_i_2\ : label is "soft_lutpair14"; + attribute SOFT_HLUTNM of \gen_arbiter.m_valid_i_i_1\ : label is "soft_lutpair12"; + attribute SOFT_HLUTNM of \gen_arbiter.s_ready_i[1]_i_1\ : label is "soft_lutpair9"; + attribute SOFT_HLUTNM of \gen_axi.write_cs[0]_i_2\ : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[1]_i_1\ : label is "soft_lutpair13"; + attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[2]_i_1\ : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_2\ : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_3\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_5\ : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of \m_axi_awvalid[0]_INST_0\ : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of \m_ready_d[1]_i_3\ : label is "soft_lutpair12"; + attribute SOFT_HLUTNM of m_valid_i_i_1 : label is "soft_lutpair11"; + attribute SOFT_HLUTNM of \m_valid_i_i_1__1\ : label is "soft_lutpair10"; + attribute SOFT_HLUTNM of \storage_data1[0]_i_3\ : label is "soft_lutpair11"; + attribute SOFT_HLUTNM of \storage_data1[0]_i_4\ : label is "soft_lutpair10"; +begin + Q(1 downto 0) <= \^q\(1 downto 0); + SR(0) <= \^sr\(0); + aa_sa_awvalid <= \^aa_sa_awvalid\; + aa_wm_awgrant_enc <= \^aa_wm_awgrant_enc\; + sel_4 <= \^sel_4\; + ss_aa_awready(0) <= \^ss_aa_awready\(0); +\gen_arbiter.any_grant_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000F0F8F0F0" + ) + port map ( + I0 => st_aa_awvalid_qual(0), + I1 => \gen_arbiter.m_grant_enc_i[0]_i_2_n_0\, + I2 => \gen_arbiter.any_grant_reg_n_0\, + I3 => \^aa_sa_awvalid\, + I4 => valid_qual_i111_in, + I5 => \gen_arbiter.m_valid_i_reg_0\, + O => \gen_arbiter.any_grant_i_1_n_0\ + ); +\gen_arbiter.any_grant_reg\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \gen_arbiter.any_grant_i_1_n_0\, + Q => \gen_arbiter.any_grant_reg_n_0\, + R => '0' + ); +\gen_arbiter.grant_hot[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000EAAAAAAA" + ) + port map ( + I0 => \gen_arbiter.grant_hot_reg_n_0_[1]\, + I1 => st_aa_awvalid_qual(0), + I2 => \gen_arbiter.m_grant_enc_i[0]_i_2_n_0\, + I3 => \gen_arbiter.grant_hot[1]_i_2_n_0\, + I4 => valid_qual_i111_in, + I5 => \gen_arbiter.m_valid_i_reg_0\, + O => \gen_arbiter.grant_hot[1]_i_1_n_0\ + ); +\gen_arbiter.grant_hot[1]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_arbiter.any_grant_reg_n_0\, + I1 => \^aa_sa_awvalid\, + O => \gen_arbiter.grant_hot[1]_i_2_n_0\ + ); +\gen_arbiter.grant_hot_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \gen_arbiter.grant_hot[1]_i_1_n_0\, + Q => \gen_arbiter.grant_hot_reg_n_0_[1]\, + R => '0' + ); +\gen_arbiter.last_rr_hot_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => aclk, + CE => grant_hot, + D => \gen_arbiter.m_grant_enc_i[0]_i_2_n_0\, + Q => p_2_in, + S => \^sr\(0) + ); +\gen_arbiter.m_grant_enc_i[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"02000000" + ) + port map ( + I0 => valid_qual_i111_in, + I1 => \^aa_sa_awvalid\, + I2 => \gen_arbiter.any_grant_reg_n_0\, + I3 => \gen_arbiter.m_grant_enc_i[0]_i_2_n_0\, + I4 => st_aa_awvalid_qual(0), + O => grant_hot + ); +\gen_arbiter.m_grant_enc_i[0]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000080" + ) + port map ( + I0 => s_axi_awvalid(0), + I1 => p_2_in, + I2 => qual_reg(1), + I3 => m_ready_d_0(0), + I4 => \^ss_aa_awready\(0), + O => \gen_arbiter.m_grant_enc_i[0]_i_2_n_0\ + ); +\gen_arbiter.m_grant_enc_i[0]_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => \gen_master_slots[0].w_issuing_cnt_reg[3]\(2), + I1 => \gen_master_slots[0].w_issuing_cnt_reg[3]\(1), + I2 => \gen_master_slots[0].w_issuing_cnt_reg[3]\(0), + O => \gen_arbiter.qual_reg_reg[1]_0\ + ); +\gen_arbiter.m_grant_enc_i_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => grant_hot, + D => \gen_arbiter.m_grant_enc_i[0]_i_2_n_0\, + Q => \^aa_wm_awgrant_enc\, + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => aresetn_d, + O => \^sr\(0) + ); +\gen_arbiter.m_mesg_i[0]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^aa_sa_awvalid\, + O => p_1_in + ); +\gen_arbiter.m_mesg_i[10]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(9), + O => m_mesg_mux(10) + ); +\gen_arbiter.m_mesg_i[11]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(10), + O => m_mesg_mux(11) + ); +\gen_arbiter.m_mesg_i[12]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(11), + O => m_mesg_mux(12) + ); +\gen_arbiter.m_mesg_i[13]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(12), + O => m_mesg_mux(13) + ); +\gen_arbiter.m_mesg_i[14]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(13), + O => m_mesg_mux(14) + ); +\gen_arbiter.m_mesg_i[15]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(14), + O => m_mesg_mux(15) + ); +\gen_arbiter.m_mesg_i[16]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(15), + O => m_mesg_mux(16) + ); +\gen_arbiter.m_mesg_i[17]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(16), + O => m_mesg_mux(17) + ); +\gen_arbiter.m_mesg_i[18]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(17), + O => m_mesg_mux(18) + ); +\gen_arbiter.m_mesg_i[19]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(18), + O => m_mesg_mux(19) + ); +\gen_arbiter.m_mesg_i[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(0), + O => m_mesg_mux(1) + ); +\gen_arbiter.m_mesg_i[20]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(19), + O => m_mesg_mux(20) + ); +\gen_arbiter.m_mesg_i[21]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(20), + O => m_mesg_mux(21) + ); +\gen_arbiter.m_mesg_i[22]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(21), + O => m_mesg_mux(22) + ); +\gen_arbiter.m_mesg_i[23]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(22), + O => m_mesg_mux(23) + ); +\gen_arbiter.m_mesg_i[24]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(23), + O => m_mesg_mux(24) + ); +\gen_arbiter.m_mesg_i[25]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(24), + O => m_mesg_mux(25) + ); +\gen_arbiter.m_mesg_i[26]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(25), + O => m_mesg_mux(26) + ); +\gen_arbiter.m_mesg_i[27]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(26), + O => m_mesg_mux(27) + ); +\gen_arbiter.m_mesg_i[28]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(27), + O => m_mesg_mux(28) + ); +\gen_arbiter.m_mesg_i[29]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(28), + O => m_mesg_mux(29) + ); +\gen_arbiter.m_mesg_i[2]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(1), + O => m_mesg_mux(2) + ); +\gen_arbiter.m_mesg_i[30]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(29), + O => m_mesg_mux(30) + ); +\gen_arbiter.m_mesg_i[31]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(30), + O => m_mesg_mux(31) + ); +\gen_arbiter.m_mesg_i[32]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(31), + O => m_mesg_mux(32) + ); +\gen_arbiter.m_mesg_i[33]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awlen(0), + O => m_mesg_mux(33) + ); +\gen_arbiter.m_mesg_i[34]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awlen(1), + O => m_mesg_mux(34) + ); +\gen_arbiter.m_mesg_i[35]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awlen(2), + O => m_mesg_mux(35) + ); +\gen_arbiter.m_mesg_i[36]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awlen(3), + O => m_mesg_mux(36) + ); +\gen_arbiter.m_mesg_i[37]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awlen(4), + O => m_mesg_mux(37) + ); +\gen_arbiter.m_mesg_i[38]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awlen(5), + O => m_mesg_mux(38) + ); +\gen_arbiter.m_mesg_i[39]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awlen(6), + O => m_mesg_mux(39) + ); +\gen_arbiter.m_mesg_i[3]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(2), + O => m_mesg_mux(3) + ); +\gen_arbiter.m_mesg_i[40]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awlen(7), + O => m_mesg_mux(40) + ); +\gen_arbiter.m_mesg_i[41]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awsize(0), + O => m_mesg_mux(41) + ); +\gen_arbiter.m_mesg_i[42]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awsize(1), + O => m_mesg_mux(42) + ); +\gen_arbiter.m_mesg_i[43]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awsize(2), + O => m_mesg_mux(43) + ); +\gen_arbiter.m_mesg_i[44]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awlock(0), + O => m_mesg_mux(44) + ); +\gen_arbiter.m_mesg_i[46]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awprot(0), + O => m_mesg_mux(46) + ); +\gen_arbiter.m_mesg_i[47]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awprot(1), + O => m_mesg_mux(47) + ); +\gen_arbiter.m_mesg_i[48]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awprot(2), + O => m_mesg_mux(48) + ); +\gen_arbiter.m_mesg_i[4]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(3), + O => m_mesg_mux(4) + ); +\gen_arbiter.m_mesg_i[53]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awburst(0), + O => m_mesg_mux(53) + ); +\gen_arbiter.m_mesg_i[54]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awburst(1), + O => m_mesg_mux(54) + ); +\gen_arbiter.m_mesg_i[55]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awcache(0), + O => m_mesg_mux(55) + ); +\gen_arbiter.m_mesg_i[56]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awcache(1), + O => m_mesg_mux(56) + ); +\gen_arbiter.m_mesg_i[57]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awcache(2), + O => m_mesg_mux(57) + ); +\gen_arbiter.m_mesg_i[58]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awcache(3), + O => m_mesg_mux(58) + ); +\gen_arbiter.m_mesg_i[59]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awqos(0), + O => m_mesg_mux(59) + ); +\gen_arbiter.m_mesg_i[5]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(4), + O => m_mesg_mux(5) + ); +\gen_arbiter.m_mesg_i[60]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awqos(1), + O => m_mesg_mux(60) + ); +\gen_arbiter.m_mesg_i[61]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awqos(2), + O => m_mesg_mux(61) + ); +\gen_arbiter.m_mesg_i[62]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awqos(3), + O => m_mesg_mux(62) + ); +\gen_arbiter.m_mesg_i[6]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(5), + O => m_mesg_mux(6) + ); +\gen_arbiter.m_mesg_i[7]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(6), + O => m_mesg_mux(7) + ); +\gen_arbiter.m_mesg_i[8]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(7), + O => m_mesg_mux(8) + ); +\gen_arbiter.m_mesg_i[9]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^aa_wm_awgrant_enc\, + I1 => s_axi_awaddr(8), + O => m_mesg_mux(9) + ); +\gen_arbiter.m_mesg_i_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => \^aa_wm_awgrant_enc\, + Q => \m_axi_awqos[3]\(0), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(10), + Q => \m_axi_awqos[3]\(10), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(11), + Q => \m_axi_awqos[3]\(11), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(12), + Q => \m_axi_awqos[3]\(12), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(13), + Q => \m_axi_awqos[3]\(13), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(14), + Q => \m_axi_awqos[3]\(14), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(15), + Q => \m_axi_awqos[3]\(15), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(16), + Q => \m_axi_awqos[3]\(16), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(17), + Q => \m_axi_awqos[3]\(17), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(18), + Q => \m_axi_awqos[3]\(18), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(19), + Q => \m_axi_awqos[3]\(19), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(1), + Q => \m_axi_awqos[3]\(1), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(20), + Q => \m_axi_awqos[3]\(20), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(21), + Q => \m_axi_awqos[3]\(21), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(22), + Q => \m_axi_awqos[3]\(22), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(23), + Q => \m_axi_awqos[3]\(23), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(24), + Q => \m_axi_awqos[3]\(24), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(25), + Q => \m_axi_awqos[3]\(25), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[26]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(26), + Q => \m_axi_awqos[3]\(26), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[27]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(27), + Q => \m_axi_awqos[3]\(27), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[28]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(28), + Q => \m_axi_awqos[3]\(28), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[29]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(29), + Q => \m_axi_awqos[3]\(29), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(2), + Q => \m_axi_awqos[3]\(2), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(30), + Q => \m_axi_awqos[3]\(30), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(31), + Q => \m_axi_awqos[3]\(31), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[32]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(32), + Q => \m_axi_awqos[3]\(32), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[33]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(33), + Q => \m_axi_awqos[3]\(33), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[34]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(34), + Q => \m_axi_awqos[3]\(34), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[35]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(35), + Q => \m_axi_awqos[3]\(35), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[36]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(36), + Q => \m_axi_awqos[3]\(36), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[37]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(37), + Q => \m_axi_awqos[3]\(37), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[38]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(38), + Q => \m_axi_awqos[3]\(38), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[39]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(39), + Q => \m_axi_awqos[3]\(39), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(3), + Q => \m_axi_awqos[3]\(3), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[40]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(40), + Q => \m_axi_awqos[3]\(40), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[41]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(41), + Q => \m_axi_awqos[3]\(41), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[42]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(42), + Q => \m_axi_awqos[3]\(42), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[43]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(43), + Q => \m_axi_awqos[3]\(43), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[44]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(44), + Q => \m_axi_awqos[3]\(44), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[46]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(46), + Q => \m_axi_awqos[3]\(45), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[47]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(47), + Q => \m_axi_awqos[3]\(46), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[48]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(48), + Q => \m_axi_awqos[3]\(47), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(4), + Q => \m_axi_awqos[3]\(4), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[53]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(53), + Q => \m_axi_awqos[3]\(48), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[54]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(54), + Q => \m_axi_awqos[3]\(49), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[55]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(55), + Q => \m_axi_awqos[3]\(50), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[56]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(56), + Q => \m_axi_awqos[3]\(51), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[57]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(57), + Q => \m_axi_awqos[3]\(52), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[58]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(58), + Q => \m_axi_awqos[3]\(53), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[59]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(59), + Q => \m_axi_awqos[3]\(54), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(5), + Q => \m_axi_awqos[3]\(5), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[60]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(60), + Q => \m_axi_awqos[3]\(55), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[61]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(61), + Q => \m_axi_awqos[3]\(56), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[62]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(62), + Q => \m_axi_awqos[3]\(57), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(6), + Q => \m_axi_awqos[3]\(6), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(7), + Q => \m_axi_awqos[3]\(7), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(8), + Q => \m_axi_awqos[3]\(8), + R => \^sr\(0) + ); +\gen_arbiter.m_mesg_i_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => p_1_in, + D => m_mesg_mux(9), + Q => \m_axi_awqos[3]\(9), + R => \^sr\(0) + ); +\gen_arbiter.m_target_hot_i[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1000000000000000" + ) + port map ( + I0 => \^ss_aa_awready\(0), + I1 => m_ready_d_0(0), + I2 => qual_reg(1), + I3 => p_2_in, + I4 => s_axi_awvalid(0), + I5 => \^sel_4\, + O => m_target_hot_mux(0) + ); +\gen_arbiter.m_target_hot_i[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000010000000" + ) + port map ( + I0 => \^ss_aa_awready\(0), + I1 => m_ready_d_0(0), + I2 => qual_reg(1), + I3 => p_2_in, + I4 => s_axi_awvalid(0), + I5 => \^sel_4\, + O => m_target_hot_mux(1) + ); +\gen_arbiter.m_target_hot_i[1]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"01" + ) + port map ( + I0 => s_axi_awaddr(31), + I1 => s_axi_awaddr(30), + I2 => s_axi_awaddr(29), + O => \^sel_4\ + ); +\gen_arbiter.m_target_hot_i_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => grant_hot, + D => m_target_hot_mux(0), + Q => \^q\(0), + R => \^sr\(0) + ); +\gen_arbiter.m_target_hot_i_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => grant_hot, + D => m_target_hot_mux(1), + Q => \^q\(1), + R => \^sr\(0) + ); +\gen_arbiter.m_valid_i_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"5C" + ) + port map ( + I0 => aa_sa_awready, + I1 => \gen_arbiter.any_grant_reg_n_0\, + I2 => \^aa_sa_awvalid\, + O => \gen_arbiter.m_valid_i_i_1_n_0\ + ); +\gen_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \gen_arbiter.m_valid_i_i_1_n_0\, + Q => \^aa_sa_awvalid\, + R => \^sr\(0) + ); +\gen_arbiter.qual_reg_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \m_ready_d_reg[0]\, + Q => qual_reg(1), + R => \^sr\(0) + ); +\gen_arbiter.s_ready_i[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0800" + ) + port map ( + I0 => \gen_arbiter.grant_hot_reg_n_0_[1]\, + I1 => aresetn_d, + I2 => \^aa_sa_awvalid\, + I3 => \gen_arbiter.any_grant_reg_n_0\, + O => \gen_arbiter.s_ready_i[1]_i_1_n_0\ + ); +\gen_arbiter.s_ready_i_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \gen_arbiter.s_ready_i[1]_i_1_n_0\, + Q => \^ss_aa_awready\(0), + R => '0' + ); +\gen_axi.write_cs[0]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"DFFF" + ) + port map ( + I0 => mi_awready(0), + I1 => m_ready_d(1), + I2 => \^aa_sa_awvalid\, + I3 => \^q\(1), + O => \gen_master_slots[1].w_issuing_cnt_reg[8]\ + ); +\gen_master_slots[0].w_issuing_cnt[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"69" + ) + port map ( + I0 => \gen_master_slots[0].w_issuing_cnt_reg[3]\(1), + I1 => \gen_master_slots[0].w_issuing_cnt_reg[3]\(0), + I2 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\, + O => D(0) + ); +\gen_master_slots[0].w_issuing_cnt[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AA9" + ) + port map ( + I0 => \gen_master_slots[0].w_issuing_cnt_reg[3]\(2), + I1 => \gen_master_slots[0].w_issuing_cnt_reg[3]\(0), + I2 => \gen_master_slots[0].w_issuing_cnt_reg[3]\(1), + I3 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\, + O => D(1) + ); +\gen_master_slots[0].w_issuing_cnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000FFFFFFFE0000" + ) + port map ( + I0 => \gen_master_slots[0].w_issuing_cnt_reg[3]\(3), + I1 => \gen_master_slots[0].w_issuing_cnt_reg[3]\(2), + I2 => \gen_master_slots[0].w_issuing_cnt_reg[3]\(1), + I3 => \gen_master_slots[0].w_issuing_cnt_reg[3]\(0), + I4 => \gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0\, + I5 => \gen_single_thread.active_target_hot_reg[0]\, + O => E(0) + ); +\gen_master_slots[0].w_issuing_cnt[3]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAAAAA9" + ) + port map ( + I0 => \gen_master_slots[0].w_issuing_cnt_reg[3]\(3), + I1 => \gen_master_slots[0].w_issuing_cnt_reg[3]\(1), + I2 => \gen_master_slots[0].w_issuing_cnt_reg[3]\(2), + I3 => \gen_master_slots[0].w_issuing_cnt_reg[3]\(0), + I4 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\, + O => D(2) + ); +\gen_master_slots[0].w_issuing_cnt[3]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"DFFF" + ) + port map ( + I0 => m_axi_awready(0), + I1 => m_ready_d(1), + I2 => \^aa_sa_awvalid\, + I3 => \^q\(0), + O => \gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0\ + ); +\gen_master_slots[0].w_issuing_cnt[3]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00800000" + ) + port map ( + I0 => \gen_single_thread.active_target_hot_reg[0]\, + I1 => \^q\(0), + I2 => \^aa_sa_awvalid\, + I3 => m_ready_d(1), + I4 => m_axi_awready(0), + O => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\ + ); +\m_axi_awvalid[0]_INST_0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => \^aa_sa_awvalid\, + I1 => \^q\(0), + I2 => m_ready_d(1), + O => m_axi_awvalid(0) + ); +\m_ready_d[1]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"7" + ) + port map ( + I0 => \^q\(0), + I1 => \^aa_sa_awvalid\, + O => \m_ready_d_reg[1]_0\ + ); +\m_ready_d[1]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"7" + ) + port map ( + I0 => \^q\(1), + I1 => \^aa_sa_awvalid\, + O => \m_ready_d_reg[1]\ + ); +m_valid_i_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => \^aa_sa_awvalid\, + I1 => \^q\(1), + I2 => m_ready_d(0), + O => sa_wm_awvalid(0) + ); +\m_valid_i_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"F7" + ) + port map ( + I0 => \^aa_sa_awvalid\, + I1 => \^q\(0), + I2 => m_ready_d(0), + O => m_valid_i_reg + ); +\storage_data1[0]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2000" + ) + port map ( + I0 => \out\(0), + I1 => m_ready_d(0), + I2 => \^q\(0), + I3 => \^aa_sa_awvalid\, + O => \storage_data1_reg[0]\ + ); +\storage_data1[0]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2000" + ) + port map ( + I0 => \out\(1), + I1 => m_ready_d(0), + I2 => \^q\(0), + I3 => \^aa_sa_awvalid\, + O => \storage_data1_reg[0]_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_decerr_slave is + port ( + mi_awready : out STD_LOGIC_VECTOR ( 0 to 0 ); + p_10_in : out STD_LOGIC; + p_20_in : out STD_LOGIC; + p_17_in : out STD_LOGIC; + p_11_in : out STD_LOGIC; + p_13_in : out STD_LOGIC; + mi_arready : out STD_LOGIC_VECTOR ( 0 to 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + aclk : in STD_LOGIC; + \gen_axi.s_axi_awready_i_reg_0\ : in STD_LOGIC; + mi_bready_1 : in STD_LOGIC; + \write_cs0__0\ : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + mi_rready_1 : in STD_LOGIC; + aa_mi_arvalid : in STD_LOGIC; + \gen_arbiter.m_target_hot_i_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_axi.read_cs_reg[0]_0\ : in STD_LOGIC; + \gen_arbiter.m_mesg_i_reg[40]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + aresetn_d : in STD_LOGIC + ); +end Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_decerr_slave; + +architecture STRUCTURE of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_decerr_slave is + signal \gen_axi.read_cnt[4]_i_2_n_0\ : STD_LOGIC; + signal \gen_axi.read_cnt[5]_i_2_n_0\ : STD_LOGIC; + signal \gen_axi.read_cnt[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_axi.read_cnt[7]_i_3_n_0\ : STD_LOGIC; + signal \gen_axi.read_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 1 ); + signal \gen_axi.read_cnt_reg__0__0\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \gen_axi.read_cs[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_axi.s_axi_arready_i_i_1_n_0\ : STD_LOGIC; + signal \gen_axi.s_axi_arready_i_i_2_n_0\ : STD_LOGIC; + signal \gen_axi.s_axi_awready_i_i_1_n_0\ : STD_LOGIC; + signal \gen_axi.s_axi_bid_i[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_axi.s_axi_bvalid_i_i_1_n_0\ : STD_LOGIC; + signal \gen_axi.s_axi_rlast_i_i_1_n_0\ : STD_LOGIC; + signal \gen_axi.s_axi_rlast_i_i_3_n_0\ : STD_LOGIC; + signal \gen_axi.s_axi_rlast_i_i_5_n_0\ : STD_LOGIC; + signal \gen_axi.s_axi_wready_i_i_1_n_0\ : STD_LOGIC; + signal \gen_axi.write_cs[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_axi.write_cs[1]_i_1_n_0\ : STD_LOGIC; + signal \^mi_arready\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^mi_awready\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \^p_10_in\ : STD_LOGIC; + signal \^p_11_in\ : STD_LOGIC; + signal \^p_13_in\ : STD_LOGIC; + signal \^p_17_in\ : STD_LOGIC; + signal \^p_20_in\ : STD_LOGIC; + signal s_axi_rid_i : STD_LOGIC; + signal write_cs : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \gen_axi.read_cnt[0]_i_1\ : label is "soft_lutpair47"; + attribute SOFT_HLUTNM of \gen_axi.read_cnt[1]_i_1\ : label is "soft_lutpair47"; + attribute SOFT_HLUTNM of \gen_axi.read_cnt[4]_i_2\ : label is "soft_lutpair46"; + attribute SOFT_HLUTNM of \gen_axi.read_cnt[5]_i_2\ : label is "soft_lutpair46"; + attribute SOFT_HLUTNM of \gen_axi.read_cnt[7]_i_2\ : label is "soft_lutpair45"; + attribute SOFT_HLUTNM of \gen_axi.s_axi_arready_i_i_2\ : label is "soft_lutpair45"; + attribute SOFT_HLUTNM of \gen_axi.s_axi_bvalid_i_i_1\ : label is "soft_lutpair44"; + attribute SOFT_HLUTNM of \gen_axi.s_axi_wready_i_i_1\ : label is "soft_lutpair43"; + attribute SOFT_HLUTNM of \gen_axi.write_cs[0]_i_1\ : label is "soft_lutpair43"; + attribute SOFT_HLUTNM of \gen_axi.write_cs[1]_i_1\ : label is "soft_lutpair44"; +begin + mi_arready(0) <= \^mi_arready\(0); + mi_awready(0) <= \^mi_awready\(0); + p_10_in <= \^p_10_in\; + p_11_in <= \^p_11_in\; + p_13_in <= \^p_13_in\; + p_17_in <= \^p_17_in\; + p_20_in <= \^p_20_in\; +\gen_axi.read_cnt[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"74" + ) + port map ( + I0 => \gen_axi.read_cnt_reg__0__0\(0), + I1 => \^p_11_in\, + I2 => \gen_arbiter.m_mesg_i_reg[40]\(0), + O => p_0_in(0) + ); +\gen_axi.read_cnt[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E22E" + ) + port map ( + I0 => \gen_arbiter.m_mesg_i_reg[40]\(1), + I1 => \^p_11_in\, + I2 => \gen_axi.read_cnt_reg__0__0\(0), + I3 => \gen_axi.read_cnt_reg__0\(1), + O => p_0_in(1) + ); +\gen_axi.read_cnt[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FC03AAAA" + ) + port map ( + I0 => \gen_arbiter.m_mesg_i_reg[40]\(2), + I1 => \gen_axi.read_cnt_reg__0__0\(0), + I2 => \gen_axi.read_cnt_reg__0\(1), + I3 => \gen_axi.read_cnt_reg__0\(2), + I4 => \^p_11_in\, + O => p_0_in(2) + ); +\gen_axi.read_cnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFC0003AAAAAAAA" + ) + port map ( + I0 => \gen_arbiter.m_mesg_i_reg[40]\(3), + I1 => \gen_axi.read_cnt_reg__0\(2), + I2 => \gen_axi.read_cnt_reg__0\(1), + I3 => \gen_axi.read_cnt_reg__0__0\(0), + I4 => \gen_axi.read_cnt_reg__0\(3), + I5 => \^p_11_in\, + O => p_0_in(3) + ); +\gen_axi.read_cnt[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"C3AA" + ) + port map ( + I0 => \gen_arbiter.m_mesg_i_reg[40]\(4), + I1 => \gen_axi.read_cnt[4]_i_2_n_0\, + I2 => \gen_axi.read_cnt_reg__0\(4), + I3 => \^p_11_in\, + O => p_0_in(4) + ); +\gen_axi.read_cnt[4]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \gen_axi.read_cnt_reg__0\(2), + I1 => \gen_axi.read_cnt_reg__0\(1), + I2 => \gen_axi.read_cnt_reg__0__0\(0), + I3 => \gen_axi.read_cnt_reg__0\(3), + O => \gen_axi.read_cnt[4]_i_2_n_0\ + ); +\gen_axi.read_cnt[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"C3AA" + ) + port map ( + I0 => \gen_arbiter.m_mesg_i_reg[40]\(5), + I1 => \gen_axi.read_cnt_reg__0\(5), + I2 => \gen_axi.read_cnt[5]_i_2_n_0\, + I3 => \^p_11_in\, + O => p_0_in(5) + ); +\gen_axi.read_cnt[5]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => \gen_axi.read_cnt_reg__0\(3), + I1 => \gen_axi.read_cnt_reg__0__0\(0), + I2 => \gen_axi.read_cnt_reg__0\(1), + I3 => \gen_axi.read_cnt_reg__0\(2), + I4 => \gen_axi.read_cnt_reg__0\(4), + O => \gen_axi.read_cnt[5]_i_2_n_0\ + ); +\gen_axi.read_cnt[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"C3AA" + ) + port map ( + I0 => \gen_arbiter.m_mesg_i_reg[40]\(6), + I1 => \gen_axi.read_cnt[7]_i_3_n_0\, + I2 => \gen_axi.read_cnt_reg__0\(6), + I3 => \^p_11_in\, + O => p_0_in(6) + ); +\gen_axi.read_cnt[7]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8F80808080808080" + ) + port map ( + I0 => \gen_axi.s_axi_arready_i_i_2_n_0\, + I1 => mi_rready_1, + I2 => \^p_11_in\, + I3 => aa_mi_arvalid, + I4 => \gen_arbiter.m_target_hot_i_reg[1]\(0), + I5 => \^mi_arready\(0), + O => \gen_axi.read_cnt[7]_i_1_n_0\ + ); +\gen_axi.read_cnt[7]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FCAA03AA" + ) + port map ( + I0 => \gen_arbiter.m_mesg_i_reg[40]\(7), + I1 => \gen_axi.read_cnt[7]_i_3_n_0\, + I2 => \gen_axi.read_cnt_reg__0\(6), + I3 => \^p_11_in\, + I4 => \gen_axi.read_cnt_reg__0\(7), + O => p_0_in(7) + ); +\gen_axi.read_cnt[7]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => \gen_axi.read_cnt_reg__0\(5), + I1 => \gen_axi.read_cnt_reg__0\(4), + I2 => \gen_axi.read_cnt_reg__0\(2), + I3 => \gen_axi.read_cnt_reg__0\(1), + I4 => \gen_axi.read_cnt_reg__0__0\(0), + I5 => \gen_axi.read_cnt_reg__0\(3), + O => \gen_axi.read_cnt[7]_i_3_n_0\ + ); +\gen_axi.read_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \gen_axi.read_cnt[7]_i_1_n_0\, + D => p_0_in(0), + Q => \gen_axi.read_cnt_reg__0__0\(0), + R => SR(0) + ); +\gen_axi.read_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \gen_axi.read_cnt[7]_i_1_n_0\, + D => p_0_in(1), + Q => \gen_axi.read_cnt_reg__0\(1), + R => SR(0) + ); +\gen_axi.read_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \gen_axi.read_cnt[7]_i_1_n_0\, + D => p_0_in(2), + Q => \gen_axi.read_cnt_reg__0\(2), + R => SR(0) + ); +\gen_axi.read_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \gen_axi.read_cnt[7]_i_1_n_0\, + D => p_0_in(3), + Q => \gen_axi.read_cnt_reg__0\(3), + R => SR(0) + ); +\gen_axi.read_cnt_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \gen_axi.read_cnt[7]_i_1_n_0\, + D => p_0_in(4), + Q => \gen_axi.read_cnt_reg__0\(4), + R => SR(0) + ); +\gen_axi.read_cnt_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \gen_axi.read_cnt[7]_i_1_n_0\, + D => p_0_in(5), + Q => \gen_axi.read_cnt_reg__0\(5), + R => SR(0) + ); +\gen_axi.read_cnt_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \gen_axi.read_cnt[7]_i_1_n_0\, + D => p_0_in(6), + Q => \gen_axi.read_cnt_reg__0\(6), + R => SR(0) + ); +\gen_axi.read_cnt_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \gen_axi.read_cnt[7]_i_1_n_0\, + D => p_0_in(7), + Q => \gen_axi.read_cnt_reg__0\(7), + R => SR(0) + ); +\gen_axi.read_cs[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BFB0B0B0B0B0B0B0" + ) + port map ( + I0 => \gen_axi.s_axi_arready_i_i_2_n_0\, + I1 => mi_rready_1, + I2 => \^p_11_in\, + I3 => aa_mi_arvalid, + I4 => \gen_arbiter.m_target_hot_i_reg[1]\(0), + I5 => \^mi_arready\(0), + O => \gen_axi.read_cs[0]_i_1_n_0\ + ); +\gen_axi.read_cs_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \gen_axi.read_cs[0]_i_1_n_0\, + Q => \^p_11_in\, + R => SR(0) + ); +\gen_axi.s_axi_arready_i_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000BFBB0000" + ) + port map ( + I0 => \^mi_arready\(0), + I1 => \^p_11_in\, + I2 => \gen_axi.s_axi_arready_i_i_2_n_0\, + I3 => mi_rready_1, + I4 => aresetn_d, + I5 => s_axi_rid_i, + O => \gen_axi.s_axi_arready_i_i_1_n_0\ + ); +\gen_axi.s_axi_arready_i_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => \gen_axi.read_cnt[7]_i_3_n_0\, + I1 => \gen_axi.read_cnt_reg__0\(7), + I2 => \gen_axi.read_cnt_reg__0\(6), + O => \gen_axi.s_axi_arready_i_i_2_n_0\ + ); +\gen_axi.s_axi_arready_i_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0080" + ) + port map ( + I0 => \^mi_arready\(0), + I1 => \gen_arbiter.m_target_hot_i_reg[1]\(0), + I2 => aa_mi_arvalid, + I3 => \^p_11_in\, + O => s_axi_rid_i + ); +\gen_axi.s_axi_arready_i_reg\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \gen_axi.s_axi_arready_i_i_1_n_0\, + Q => \^mi_arready\(0), + R => '0' + ); +\gen_axi.s_axi_awready_i_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFA00CA" + ) + port map ( + I0 => \gen_axi.s_axi_awready_i_reg_0\, + I1 => mi_bready_1, + I2 => write_cs(1), + I3 => write_cs(0), + I4 => \^mi_awready\(0), + O => \gen_axi.s_axi_awready_i_i_1_n_0\ + ); +\gen_axi.s_axi_awready_i_reg\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \gen_axi.s_axi_awready_i_i_1_n_0\, + Q => \^mi_awready\(0), + R => SR(0) + ); +\gen_axi.s_axi_bid_i[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFE0002" + ) + port map ( + I0 => Q(0), + I1 => write_cs(1), + I2 => write_cs(0), + I3 => \gen_axi.s_axi_awready_i_reg_0\, + I4 => \^p_20_in\, + O => \gen_axi.s_axi_bid_i[0]_i_1_n_0\ + ); +\gen_axi.s_axi_bid_i_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \gen_axi.s_axi_bid_i[0]_i_1_n_0\, + Q => \^p_20_in\, + R => SR(0) + ); +\gen_axi.s_axi_bvalid_i_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F5FF00C0" + ) + port map ( + I0 => mi_bready_1, + I1 => \write_cs0__0\, + I2 => write_cs(0), + I3 => write_cs(1), + I4 => \^p_17_in\, + O => \gen_axi.s_axi_bvalid_i_i_1_n_0\ + ); +\gen_axi.s_axi_bvalid_i_reg\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \gen_axi.s_axi_bvalid_i_i_1_n_0\, + Q => \^p_17_in\, + R => SR(0) + ); +\gen_axi.s_axi_rlast_i_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F8FFF800" + ) + port map ( + I0 => \^p_11_in\, + I1 => \gen_axi.s_axi_arready_i_i_2_n_0\, + I2 => \gen_axi.read_cs_reg[0]_0\, + I3 => \gen_axi.s_axi_rlast_i_i_3_n_0\, + I4 => \^p_13_in\, + O => \gen_axi.s_axi_rlast_i_i_1_n_0\ + ); +\gen_axi.s_axi_rlast_i_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0100" + ) + port map ( + I0 => \gen_axi.read_cnt_reg__0\(3), + I1 => \gen_axi.read_cnt_reg__0\(2), + I2 => \gen_axi.read_cnt_reg__0\(1), + I3 => \gen_axi.s_axi_rlast_i_i_5_n_0\, + I4 => s_axi_rid_i, + O => \gen_axi.s_axi_rlast_i_i_3_n_0\ + ); +\gen_axi.s_axi_rlast_i_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0001000000000000" + ) + port map ( + I0 => \gen_axi.read_cnt_reg__0\(4), + I1 => \gen_axi.read_cnt_reg__0\(5), + I2 => \gen_axi.read_cnt_reg__0\(6), + I3 => \gen_axi.read_cnt_reg__0\(7), + I4 => mi_rready_1, + I5 => \^p_11_in\, + O => \gen_axi.s_axi_rlast_i_i_5_n_0\ + ); +\gen_axi.s_axi_rlast_i_reg\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \gen_axi.s_axi_rlast_i_i_1_n_0\, + Q => \^p_13_in\, + R => SR(0) + ); +\gen_axi.s_axi_wready_i_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FF5F0003" + ) + port map ( + I0 => \write_cs0__0\, + I1 => \gen_axi.s_axi_awready_i_reg_0\, + I2 => write_cs(0), + I3 => write_cs(1), + I4 => \^p_10_in\, + O => \gen_axi.s_axi_wready_i_i_1_n_0\ + ); +\gen_axi.s_axi_wready_i_reg\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \gen_axi.s_axi_wready_i_i_1_n_0\, + Q => \^p_10_in\, + R => SR(0) + ); +\gen_axi.write_cs[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"C1F1" + ) + port map ( + I0 => \gen_axi.s_axi_awready_i_reg_0\, + I1 => write_cs(1), + I2 => write_cs(0), + I3 => \write_cs0__0\, + O => \gen_axi.write_cs[0]_i_1_n_0\ + ); +\gen_axi.write_cs[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"C8EA" + ) + port map ( + I0 => write_cs(1), + I1 => write_cs(0), + I2 => \write_cs0__0\, + I3 => mi_bready_1, + O => \gen_axi.write_cs[1]_i_1_n_0\ + ); +\gen_axi.write_cs_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \gen_axi.write_cs[0]_i_1_n_0\, + Q => write_cs(0), + R => SR(0) + ); +\gen_axi.write_cs_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \gen_axi.write_cs[1]_i_1_n_0\, + Q => write_cs(1), + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_si_transactor is + port ( + active_target_enc : out STD_LOGIC; + active_target_hot : out STD_LOGIC_VECTOR ( 0 to 0 ); + st_aa_arvalid_qual : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + p_1_in : out STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_arbiter.s_ready_i_reg[0]\ : in STD_LOGIC; + aclk : in STD_LOGIC; + \gen_arbiter.s_ready_i_reg[0]_0\ : in STD_LOGIC; + s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); + p_52_out : in STD_LOGIC; + m_valid_i_reg : in STD_LOGIC; + \m_payload_i_reg[66]\ : in STD_LOGIC; + \s_axi_araddr[29]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + p_30_out : in STD_LOGIC; + p_28_out : in STD_LOGIC; + \gen_arbiter.s_ready_i_reg[0]_1\ : in STD_LOGIC + ); +end Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_si_transactor; + +architecture STRUCTURE of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_si_transactor is + signal accept_cnt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^active_target_enc\ : STD_LOGIC; + signal \^active_target_hot\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \gen_single_thread.accept_cnt[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_single_thread.accept_cnt[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_single_thread.accept_cnt[1]_i_3_n_0\ : STD_LOGIC; + signal p_2_in : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \gen_single_thread.accept_cnt[0]_i_1\ : label is "soft_lutpair160"; + attribute SOFT_HLUTNM of \gen_single_thread.accept_cnt[1]_i_1\ : label is "soft_lutpair160"; + attribute SOFT_HLUTNM of \gen_single_thread.accept_cnt[1]_i_3\ : label is "soft_lutpair162"; + attribute SOFT_HLUTNM of \m_payload_i[66]_i_1\ : label is "soft_lutpair162"; + attribute SOFT_HLUTNM of \m_payload_i[66]_i_2__0\ : label is "soft_lutpair161"; + attribute SOFT_HLUTNM of \s_axi_rvalid[0]_INST_0\ : label is "soft_lutpair161"; +begin + active_target_enc <= \^active_target_enc\; + active_target_hot(0) <= \^active_target_hot\(0); +\gen_arbiter.qual_reg[0]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0055FFF7FFF70055" + ) + port map ( + I0 => accept_cnt(1), + I1 => m_valid_i_reg, + I2 => \m_payload_i_reg[66]\, + I3 => accept_cnt(0), + I4 => \^active_target_enc\, + I5 => \s_axi_araddr[29]\(0), + O => st_aa_arvalid_qual(0) + ); +\gen_single_thread.accept_cnt[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"A54A" + ) + port map ( + I0 => \gen_arbiter.s_ready_i_reg[0]_1\, + I1 => accept_cnt(1), + I2 => p_2_in, + I3 => accept_cnt(0), + O => \gen_single_thread.accept_cnt[0]_i_1_n_0\ + ); +\gen_single_thread.accept_cnt[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9CC4" + ) + port map ( + I0 => p_2_in, + I1 => accept_cnt(1), + I2 => accept_cnt(0), + I3 => \gen_arbiter.s_ready_i_reg[0]_1\, + O => \gen_single_thread.accept_cnt[1]_i_1_n_0\ + ); +\gen_single_thread.accept_cnt[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F454040454540404" + ) + port map ( + I0 => \gen_single_thread.accept_cnt[1]_i_3_n_0\, + I1 => Q(0), + I2 => \^active_target_enc\, + I3 => s_axi_rready(0), + I4 => p_30_out, + I5 => p_28_out, + O => p_2_in + ); +\gen_single_thread.accept_cnt[1]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"7F" + ) + port map ( + I0 => s_axi_rready(0), + I1 => \^active_target_hot\(0), + I2 => p_52_out, + O => \gen_single_thread.accept_cnt[1]_i_3_n_0\ + ); +\gen_single_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \gen_single_thread.accept_cnt[0]_i_1_n_0\, + Q => accept_cnt(0), + R => SR(0) + ); +\gen_single_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \gen_single_thread.accept_cnt[1]_i_1_n_0\, + Q => accept_cnt(1), + R => SR(0) + ); +\gen_single_thread.active_target_enc_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \gen_arbiter.s_ready_i_reg[0]\, + Q => \^active_target_enc\, + R => SR(0) + ); +\gen_single_thread.active_target_hot_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \gen_arbiter.s_ready_i_reg[0]_0\, + Q => \^active_target_hot\(0), + R => SR(0) + ); +\m_payload_i[66]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8F" + ) + port map ( + I0 => s_axi_rready(0), + I1 => \^active_target_hot\(0), + I2 => p_52_out, + O => E(0) + ); +\m_payload_i[66]_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8F" + ) + port map ( + I0 => s_axi_rready(0), + I1 => \^active_target_enc\, + I2 => p_28_out, + O => p_1_in + ); +\s_axi_rvalid[0]_INST_0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F888" + ) + port map ( + I0 => p_28_out, + I1 => \^active_target_enc\, + I2 => \^active_target_hot\(0), + I3 => p_52_out, + O => s_axi_rvalid(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_si_transactor__parameterized0\ is + port ( + active_target_enc : out STD_LOGIC; + active_target_hot : out STD_LOGIC_VECTOR ( 0 to 0 ); + st_aa_awvalid_qual : out STD_LOGIC_VECTOR ( 0 to 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_ready_i_reg : in STD_LOGIC; + aclk : in STD_LOGIC; + s_ready_i_reg_0 : in STD_LOGIC; + s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); + \m_payload_i_reg[2]\ : in STD_LOGIC; + sel_4 : in STD_LOGIC; + s_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_si_transactor__parameterized0\ : entity is "axi_crossbar_v2_1_12_si_transactor"; +end \Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_si_transactor__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_si_transactor__parameterized0\ is + signal accept_cnt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^active_target_enc\ : STD_LOGIC; + signal \gen_single_thread.accept_cnt[0]_i_1__0_n_0\ : STD_LOGIC; + signal \gen_single_thread.accept_cnt[1]_i_1__0_n_0\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \gen_single_thread.accept_cnt[0]_i_1__0\ : label is "soft_lutpair163"; + attribute SOFT_HLUTNM of \gen_single_thread.accept_cnt[1]_i_1__0\ : label is "soft_lutpair163"; +begin + active_target_enc <= \^active_target_enc\; +\gen_arbiter.m_grant_enc_i[0]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0055FFD5FFD50055" + ) + port map ( + I0 => accept_cnt(1), + I1 => s_axi_bready(0), + I2 => \m_payload_i_reg[2]\, + I3 => accept_cnt(0), + I4 => \^active_target_enc\, + I5 => sel_4, + O => st_aa_awvalid_qual(0) + ); +\gen_single_thread.accept_cnt[0]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"C03F3F80" + ) + port map ( + I0 => accept_cnt(1), + I1 => \m_payload_i_reg[2]\, + I2 => s_axi_bready(0), + I3 => s_axi_awready(0), + I4 => accept_cnt(0), + O => \gen_single_thread.accept_cnt[0]_i_1__0_n_0\ + ); +\gen_single_thread.accept_cnt[1]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D52ABF00" + ) + port map ( + I0 => s_axi_awready(0), + I1 => s_axi_bready(0), + I2 => \m_payload_i_reg[2]\, + I3 => accept_cnt(1), + I4 => accept_cnt(0), + O => \gen_single_thread.accept_cnt[1]_i_1__0_n_0\ + ); +\gen_single_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \gen_single_thread.accept_cnt[0]_i_1__0_n_0\, + Q => accept_cnt(0), + R => SR(0) + ); +\gen_single_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \gen_single_thread.accept_cnt[1]_i_1__0_n_0\, + Q => accept_cnt(1), + R => SR(0) + ); +\gen_single_thread.active_target_enc_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => s_ready_i_reg, + Q => \^active_target_enc\, + R => SR(0) + ); +\gen_single_thread.active_target_hot_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => s_ready_i_reg_0, + Q => active_target_hot(0), + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_splitter is + port ( + \gen_single_thread.active_target_hot_reg[0]\ : out STD_LOGIC; + m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_single_thread.active_target_enc_reg[0]\ : out STD_LOGIC; + s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_arbiter.qual_reg_reg[1]\ : out STD_LOGIC; + \gen_rep[0].fifoaddr_reg[0]\ : out STD_LOGIC; + sel_4 : in STD_LOGIC; + ss_wr_awready : in STD_LOGIC_VECTOR ( 0 to 0 ); + ss_aa_awready : in STD_LOGIC_VECTOR ( 0 to 0 ); + active_target_hot : in STD_LOGIC_VECTOR ( 0 to 0 ); + active_target_enc : in STD_LOGIC; + s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + valid_qual_i111_in : in STD_LOGIC; + st_aa_awvalid_qual : in STD_LOGIC_VECTOR ( 0 to 0 ); + aresetn_d : in STD_LOGIC; + aclk : in STD_LOGIC + ); +end Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_splitter; + +architecture STRUCTURE of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_splitter is + signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC; + signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_onehot_state[2]_i_2\ : label is "soft_lutpair164"; + attribute SOFT_HLUTNM of \s_axi_awready[1]_INST_0\ : label is "soft_lutpair164"; +begin + m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0); +\FSM_onehot_state[2]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^m_ready_d\(1), + I1 => s_axi_awvalid(0), + O => \gen_rep[0].fifoaddr_reg[0]\ + ); +\gen_arbiter.qual_reg[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FDDD" + ) + port map ( + I0 => s_axi_awvalid(0), + I1 => \^m_ready_d\(0), + I2 => valid_qual_i111_in, + I3 => st_aa_awvalid_qual(0), + O => \gen_arbiter.qual_reg_reg[1]\ + ); +\gen_single_thread.active_target_enc[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"575757FF54545400" + ) + port map ( + I0 => sel_4, + I1 => ss_wr_awready(0), + I2 => \^m_ready_d\(1), + I3 => ss_aa_awready(0), + I4 => \^m_ready_d\(0), + I5 => active_target_enc, + O => \gen_single_thread.active_target_enc_reg[0]\ + ); +\gen_single_thread.active_target_hot[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"ABABABFFA8A8A800" + ) + port map ( + I0 => sel_4, + I1 => ss_wr_awready(0), + I2 => \^m_ready_d\(1), + I3 => ss_aa_awready(0), + I4 => \^m_ready_d\(0), + I5 => active_target_hot(0), + O => \gen_single_thread.active_target_hot_reg[0]\ + ); +\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000C000C00080000" + ) + port map ( + I0 => s_axi_awvalid(0), + I1 => aresetn_d, + I2 => ss_wr_awready(0), + I3 => \^m_ready_d\(1), + I4 => ss_aa_awready(0), + I5 => \^m_ready_d\(0), + O => \m_ready_d[0]_i_1_n_0\ + ); +\m_ready_d[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000000CC80" + ) + port map ( + I0 => s_axi_awvalid(0), + I1 => aresetn_d, + I2 => ss_wr_awready(0), + I3 => \^m_ready_d\(1), + I4 => ss_aa_awready(0), + I5 => \^m_ready_d\(0), + O => \m_ready_d[1]_i_1_n_0\ + ); +\m_ready_d_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \m_ready_d[0]_i_1_n_0\, + Q => \^m_ready_d\(0), + R => '0' + ); +\m_ready_d_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \m_ready_d[1]_i_1_n_0\, + Q => \^m_ready_d\(1), + R => '0' + ); +\s_axi_awready[1]_INST_0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EEE0" + ) + port map ( + I0 => ss_wr_awready(0), + I1 => \^m_ready_d\(1), + I2 => ss_aa_awready(0), + I3 => \^m_ready_d\(0), + O => s_axi_awready(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_splitter_2 is + port ( + aa_sa_awready : out STD_LOGIC; + \gen_arbiter.any_grant_reg\ : out STD_LOGIC; + m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 ); + aresetn_d : in STD_LOGIC; + aa_sa_awvalid : in STD_LOGIC; + mi_awready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_arbiter.m_target_hot_i_reg[0]\ : in STD_LOGIC; + \gen_arbiter.m_target_hot_i_reg[1]\ : in STD_LOGIC; + aclk : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_splitter_2 : entity is "axi_crossbar_v2_1_12_splitter"; +end Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_splitter_2; + +architecture STRUCTURE of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_splitter_2 is + signal \^aa_sa_awready\ : STD_LOGIC; + signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC; + signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC; + signal \m_ready_d[1]_i_4_n_0\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \gen_arbiter.any_grant_i_2\ : label is "soft_lutpair167"; + attribute SOFT_HLUTNM of \m_ready_d[1]_i_4\ : label is "soft_lutpair167"; +begin + aa_sa_awready <= \^aa_sa_awready\; + m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0); +\gen_arbiter.any_grant_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8F" + ) + port map ( + I0 => \^aa_sa_awready\, + I1 => aa_sa_awvalid, + I2 => aresetn_d, + O => \gen_arbiter.any_grant_reg\ + ); +\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FCF80000" + ) + port map ( + I0 => Q(1), + I1 => aa_sa_awvalid, + I2 => \^m_ready_d\(0), + I3 => Q(0), + I4 => aresetn_d, + I5 => \^aa_sa_awready\, + O => \m_ready_d[0]_i_1_n_0\ + ); +\m_ready_d[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFCFFCCFFF0AA00" + ) + port map ( + I0 => \^m_ready_d\(0), + I1 => mi_awready(0), + I2 => m_axi_awready(0), + I3 => \^m_ready_d\(1), + I4 => Q(0), + I5 => Q(1), + O => \^aa_sa_awready\ + ); +\m_ready_d[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FFFF2F22" + ) + port map ( + I0 => m_axi_awready(0), + I1 => \gen_arbiter.m_target_hot_i_reg[0]\, + I2 => \gen_arbiter.m_target_hot_i_reg[1]\, + I3 => mi_awready(0), + I4 => \^m_ready_d\(1), + I5 => \m_ready_d[1]_i_4_n_0\, + O => \m_ready_d[1]_i_1_n_0\ + ); +\m_ready_d[1]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^aa_sa_awready\, + I1 => aresetn_d, + O => \m_ready_d[1]_i_4_n_0\ + ); +\m_ready_d_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \m_ready_d[0]_i_1_n_0\, + Q => \^m_ready_d\(0), + R => '0' + ); +\m_ready_d_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \m_ready_d[1]_i_1_n_0\, + Q => \^m_ready_d\(1), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_ndeep_srl is + port ( + push : out STD_LOGIC; + \storage_data1_reg[0]\ : out STD_LOGIC; + s_ready_i_reg : out STD_LOGIC; + fifoaddr : in STD_LOGIC_VECTOR ( 1 downto 0 ); + aclk : in STD_LOGIC; + out0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \FSM_onehot_state_reg[0]\ : in STD_LOGIC; + \m_aready__1\ : in STD_LOGIC; + m_select_enc : in STD_LOGIC; + s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 ); + \storage_data1_reg[0]_0\ : in STD_LOGIC; + m_valid_i_reg : in STD_LOGIC; + m_valid_i_reg_0 : in STD_LOGIC; + s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_ready_i_reg_0 : in STD_LOGIC + ); +end Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_ndeep_srl; + +architecture STRUCTURE of Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_ndeep_srl is + signal \gen_primitive_shifter.gen_srls[0].srl_inst_i_2_n_0\ : STD_LOGIC; + signal \gen_primitive_shifter.gen_srls[0].srl_inst_i_5_n_0\ : STD_LOGIC; + signal \gen_primitive_shifter.gen_srls[0].srl_inst_i_6_n_0\ : STD_LOGIC; + signal \^push\ : STD_LOGIC; + signal \^s_ready_i_reg\ : STD_LOGIC; + signal \storage_data1[0]_i_2__0_n_0\ : STD_LOGIC; + signal storage_data2 : STD_LOGIC; + attribute BOX_TYPE : string; + attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "SRLC32E"; + attribute srl_bus_name : string; + attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[1].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls "; + attribute srl_name : string; + attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[1].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst "; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \gen_primitive_shifter.gen_srls[0].srl_inst_i_2\ : label is "soft_lutpair165"; + attribute SOFT_HLUTNM of \gen_primitive_shifter.gen_srls[0].srl_inst_i_5\ : label is "soft_lutpair166"; + attribute SOFT_HLUTNM of \gen_primitive_shifter.gen_srls[0].srl_inst_i_6\ : label is "soft_lutpair166"; + attribute SOFT_HLUTNM of \storage_data1[0]_i_2__0\ : label is "soft_lutpair165"; +begin + push <= \^push\; + s_ready_i_reg <= \^s_ready_i_reg\; +\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000", + IS_CLK_INVERTED => '0' + ) + port map ( + A0 => fifoaddr(0), + A1 => fifoaddr(1), + A2 => '0', + A3 => '0', + CE => \^push\, + CLK => aclk, + D => \gen_primitive_shifter.gen_srls[0].srl_inst_i_2_n_0\, + Q => storage_data2 + ); +\gen_primitive_shifter.gen_srls[0].srl_inst_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF777F0000" + ) + port map ( + I0 => s_axi_wlast(0), + I1 => \^s_ready_i_reg\, + I2 => \storage_data1_reg[0]_0\, + I3 => m_valid_i_reg, + I4 => \gen_primitive_shifter.gen_srls[0].srl_inst_i_5_n_0\, + I5 => \gen_primitive_shifter.gen_srls[0].srl_inst_i_6_n_0\, + O => \^push\ + ); +\gen_primitive_shifter.gen_srls[0].srl_inst_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => s_axi_awaddr(0), + I1 => s_axi_awaddr(1), + I2 => s_axi_awaddr(2), + O => \gen_primitive_shifter.gen_srls[0].srl_inst_i_2_n_0\ + ); +\gen_primitive_shifter.gen_srls[0].srl_inst_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_valid_i_reg_0, + I1 => s_axi_wvalid(0), + O => \^s_ready_i_reg\ + ); +\gen_primitive_shifter.gen_srls[0].srl_inst_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => out0(1), + I1 => s_axi_awvalid(0), + I2 => m_ready_d(0), + O => \gen_primitive_shifter.gen_srls[0].srl_inst_i_5_n_0\ + ); +\gen_primitive_shifter.gen_srls[0].srl_inst_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0080" + ) + port map ( + I0 => s_ready_i_reg_0, + I1 => out0(0), + I2 => s_axi_awvalid(0), + I3 => m_ready_d(0), + O => \gen_primitive_shifter.gen_srls[0].srl_inst_i_6_n_0\ + ); +\storage_data1[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAFABAFAAA0A8A0" + ) + port map ( + I0 => \storage_data1[0]_i_2__0_n_0\, + I1 => out0(0), + I2 => \FSM_onehot_state_reg[0]\, + I3 => \m_aready__1\, + I4 => \gen_primitive_shifter.gen_srls[0].srl_inst_i_5_n_0\, + I5 => m_select_enc, + O => \storage_data1_reg[0]\ + ); +\storage_data1[0]_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBBBBBB8" + ) + port map ( + I0 => storage_data2, + I1 => out0(0), + I2 => s_axi_awaddr(0), + I3 => s_axi_awaddr(1), + I4 => s_axi_awaddr(2), + O => \storage_data1[0]_i_2__0_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_ndeep_srl_3 is + port ( + \storage_data1_reg[0]\ : out STD_LOGIC; + aa_wm_awgrant_enc : in STD_LOGIC; + A : in STD_LOGIC_VECTOR ( 1 downto 0 ); + aclk : in STD_LOGIC; + \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + load_s1 : in STD_LOGIC; + \storage_data1_reg[0]_0\ : in STD_LOGIC; + m_valid_i_reg : in STD_LOGIC; + p_10_in : in STD_LOGIC; + sa_wm_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_ndeep_srl_3 : entity is "axi_data_fifo_v2_1_10_ndeep_srl"; +end Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_ndeep_srl_3; + +architecture STRUCTURE of Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_ndeep_srl_3 is + signal push : STD_LOGIC; + signal storage_data2 : STD_LOGIC; + attribute BOX_TYPE : string; + attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "SRLC32E"; + attribute srl_bus_name : string; + attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls "; + attribute srl_name : string; + attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst "; +begin +\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000", + IS_CLK_INVERTED => '0' + ) + port map ( + A0 => A(0), + A1 => A(1), + A2 => '0', + A3 => '0', + CE => push, + CLK => aclk, + D => aa_wm_awgrant_enc, + Q => storage_data2 + ); +\gen_primitive_shifter.gen_srls[0].srl_inst_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FF007000" + ) + port map ( + I0 => m_valid_i_reg, + I1 => p_10_in, + I2 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(0), + I3 => sa_wm_awvalid(0), + I4 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(1), + O => push + ); +\storage_data1[0]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8FFB800" + ) + port map ( + I0 => storage_data2, + I1 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(1), + I2 => aa_wm_awgrant_enc, + I3 => load_s1, + I4 => \storage_data1_reg[0]_0\, + O => \storage_data1_reg[0]\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_ndeep_srl__parameterized8\ is + port ( + push : out STD_LOGIC; + \storage_data1_reg[0]\ : out STD_LOGIC; + aa_wm_awgrant_enc : in STD_LOGIC; + A : in STD_LOGIC_VECTOR ( 2 downto 0 ); + aclk : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\ : in STD_LOGIC; + \storage_data1_reg[0]_0\ : in STD_LOGIC; + \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\ : in STD_LOGIC; + m_select_enc_1 : in STD_LOGIC; + m_valid_i_reg : in STD_LOGIC; + \gen_arbiter.m_valid_i_reg\ : in STD_LOGIC; + m_avalid_0 : in STD_LOGIC; + m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_select_enc : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_ndeep_srl__parameterized8\ : entity is "axi_data_fifo_v2_1_10_ndeep_srl"; +end \Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_ndeep_srl__parameterized8\; + +architecture STRUCTURE of \Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_ndeep_srl__parameterized8\ is + signal \gen_primitive_shifter.gen_srls[0].srl_inst_i_2__0_n_0\ : STD_LOGIC; + signal \gen_primitive_shifter.gen_srls[0].srl_inst_i_3__0_n_0\ : STD_LOGIC; + signal \^push\ : STD_LOGIC; + signal \storage_data1[0]_i_2__1_n_0\ : STD_LOGIC; + signal storage_data2 : STD_LOGIC; + attribute BOX_TYPE : string; + attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE"; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "SRLC32E"; + attribute srl_bus_name : string; + attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls "; + attribute srl_name : string; + attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst "; +begin + push <= \^push\; +\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRL16E + generic map( + INIT => X"0000", + IS_CLK_INVERTED => '0' + ) + port map ( + A0 => A(0), + A1 => A(1), + A2 => A(2), + A3 => '0', + CE => \^push\, + CLK => aclk, + D => aa_wm_awgrant_enc, + Q => storage_data2 + ); +\gen_primitive_shifter.gen_srls[0].srl_inst_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000FFFF00007F00" + ) + port map ( + I0 => \gen_primitive_shifter.gen_srls[0].srl_inst_i_2__0_n_0\, + I1 => m_valid_i_reg, + I2 => \gen_primitive_shifter.gen_srls[0].srl_inst_i_3__0_n_0\, + I3 => \out\(0), + I4 => \gen_arbiter.m_valid_i_reg\, + I5 => \out\(1), + O => \^push\ + ); +\gen_primitive_shifter.gen_srls[0].srl_inst_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => m_select_enc_1, + I1 => m_select_enc, + O => \gen_primitive_shifter.gen_srls[0].srl_inst_i_2__0_n_0\ + ); +\gen_primitive_shifter.gen_srls[0].srl_inst_i_3__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => m_avalid_0, + I1 => m_axi_wready(0), + I2 => s_axi_wlast(0), + O => \gen_primitive_shifter.gen_srls[0].srl_inst_i_3__0_n_0\ + ); +\storage_data1[0]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAFABAFAAA0A8A0" + ) + port map ( + I0 => \storage_data1[0]_i_2__1_n_0\, + I1 => \out\(1), + I2 => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\, + I3 => \storage_data1_reg[0]_0\, + I4 => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\, + I5 => m_select_enc_1, + O => \storage_data1_reg[0]\ + ); +\storage_data1[0]_i_2__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => storage_data2, + I1 => \out\(1), + I2 => aa_wm_awgrant_enc, + O => \storage_data1[0]_i_2__1_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized1\ is + port ( + mi_bready_1 : out STD_LOGIC; + \gen_master_slots[1].w_issuing_cnt_reg[8]\ : out STD_LOGIC; + \s_axi_bvalid[1]\ : out STD_LOGIC; + valid_qual_i111_in : out STD_LOGIC; + \aresetn_d_reg[1]\ : in STD_LOGIC; + aclk : in STD_LOGIC; + p_1_in : in STD_LOGIC; + p_20_in : in STD_LOGIC; + s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); + active_target_enc : in STD_LOGIC; + \gen_axi.s_axi_awready_i_reg\ : in STD_LOGIC; + w_issuing_cnt : in STD_LOGIC_VECTOR ( 1 downto 0 ); + p_17_in : in STD_LOGIC; + \aresetn_d_reg[1]_0\ : in STD_LOGIC; + p_61_out : in STD_LOGIC; + p_58_out : in STD_LOGIC; + active_target_hot : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_master_slots[0].w_issuing_cnt_reg[2]\ : in STD_LOGIC; + sel_4 : in STD_LOGIC; + \gen_single_thread.active_target_hot_reg[0]\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_11_axic_register_slice"; +end \Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized1\; + +architecture STRUCTURE of \Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized1\ is + signal \gen_arbiter.m_grant_enc_i[0]_i_6_n_0\ : STD_LOGIC; + signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC; + signal \m_valid_i_i_1__0_n_0\ : STD_LOGIC; + signal \^mi_bready_1\ : STD_LOGIC; + signal p_34_out : STD_LOGIC; + signal p_37_out : STD_LOGIC; + signal \s_ready_i_i_1__1_n_0\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \gen_arbiter.m_grant_enc_i[0]_i_6\ : label is "soft_lutpair155"; + attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair155"; +begin + mi_bready_1 <= \^mi_bready_1\; +\gen_arbiter.m_grant_enc_i[0]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AA3FFF3FFF3FFF3F" + ) + port map ( + I0 => \gen_master_slots[0].w_issuing_cnt_reg[2]\, + I1 => \gen_arbiter.m_grant_enc_i[0]_i_6_n_0\, + I2 => w_issuing_cnt(1), + I3 => sel_4, + I4 => w_issuing_cnt(0), + I5 => \gen_single_thread.active_target_hot_reg[0]\, + O => valid_qual_i111_in + ); +\gen_arbiter.m_grant_enc_i[0]_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => p_37_out, + I1 => active_target_enc, + I2 => s_axi_bready(0), + I3 => p_34_out, + O => \gen_arbiter.m_grant_enc_i[0]_i_6_n_0\ + ); +\gen_master_slots[1].w_issuing_cnt[8]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFF800000007FFF" + ) + port map ( + I0 => p_34_out, + I1 => s_axi_bready(0), + I2 => active_target_enc, + I3 => p_37_out, + I4 => \gen_axi.s_axi_awready_i_reg\, + I5 => w_issuing_cnt(1), + O => \gen_master_slots[1].w_issuing_cnt_reg[8]\ + ); +\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => p_37_out, + I1 => p_34_out, + I2 => p_20_in, + O => \m_payload_i[2]_i_1__0_n_0\ + ); +\m_payload_i_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \m_payload_i[2]_i_1__0_n_0\, + Q => p_37_out, + R => '0' + ); +\m_valid_i_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"8BBBBBBB" + ) + port map ( + I0 => p_17_in, + I1 => \^mi_bready_1\, + I2 => s_axi_bready(0), + I3 => active_target_enc, + I4 => p_37_out, + O => \m_valid_i_i_1__0_n_0\ + ); +m_valid_i_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \m_valid_i_i_1__0_n_0\, + Q => p_34_out, + R => \aresetn_d_reg[1]\ + ); +\s_axi_bvalid[1]_INST_0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF80808080808080" + ) + port map ( + I0 => p_37_out, + I1 => p_34_out, + I2 => active_target_enc, + I3 => p_61_out, + I4 => p_58_out, + I5 => active_target_hot(0), + O => \s_axi_bvalid[1]\ + ); +\s_ready_i_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"800080FFFFFFFFFF" + ) + port map ( + I0 => p_37_out, + I1 => active_target_enc, + I2 => s_axi_bready(0), + I3 => p_34_out, + I4 => p_17_in, + I5 => \aresetn_d_reg[1]_0\, + O => \s_ready_i_i_1__1_n_0\ + ); +s_ready_i_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_ready_i_i_1__1_n_0\, + Q => \^mi_bready_1\, + R => p_1_in + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized1_4\ is + port ( + s_ready_i_reg_0 : out STD_LOGIC; + m_valid_i_reg_0 : out STD_LOGIC; + m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 ); + p_1_in : out STD_LOGIC; + s_ready_i_reg_1 : out STD_LOGIC; + s_ready_i_reg_2 : out STD_LOGIC; + \gen_master_slots[0].w_issuing_cnt_reg[0]\ : out STD_LOGIC; + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + aclk : in STD_LOGIC; + aresetn : in STD_LOGIC; + s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); + active_target_hot : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + active_target_enc_1 : in STD_LOGIC; + m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized1_4\ : entity is "axi_register_slice_v2_1_11_axic_register_slice"; +end \Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized1_4\; + +architecture STRUCTURE of \Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized1_4\ is + signal \aresetn_d[1]_i_1_n_0\ : STD_LOGIC; + signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \m_payload_i[0]_i_1_n_0\ : STD_LOGIC; + signal \m_payload_i[1]_i_1_n_0\ : STD_LOGIC; + signal \m_payload_i[2]_i_1_n_0\ : STD_LOGIC; + signal m_valid_i_i_2_n_0 : STD_LOGIC; + signal \^m_valid_i_reg_0\ : STD_LOGIC; + signal p_0_in : STD_LOGIC_VECTOR ( 1 to 1 ); + signal \^p_1_in\ : STD_LOGIC; + signal s_ready_i_i_2_n_0 : STD_LOGIC; + signal \^s_ready_i_reg_0\ : STD_LOGIC; + signal \^s_ready_i_reg_1\ : STD_LOGIC; + signal \^s_ready_i_reg_2\ : STD_LOGIC; + signal st_mr_bmesg : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_4\ : label is "soft_lutpair85"; + attribute SOFT_HLUTNM of \m_payload_i[0]_i_1\ : label is "soft_lutpair86"; + attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair86"; + attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair85"; + attribute SOFT_HLUTNM of \s_axi_bresp[2]_INST_0\ : label is "soft_lutpair87"; + attribute SOFT_HLUTNM of \s_axi_bresp[3]_INST_0\ : label is "soft_lutpair87"; +begin + m_axi_bready(0) <= \^m_axi_bready\(0); + m_valid_i_reg_0 <= \^m_valid_i_reg_0\; + p_1_in <= \^p_1_in\; + s_ready_i_reg_0 <= \^s_ready_i_reg_0\; + s_ready_i_reg_1 <= \^s_ready_i_reg_1\; + s_ready_i_reg_2 <= \^s_ready_i_reg_2\; +\aresetn_d[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => p_0_in(1), + I1 => aresetn, + O => \aresetn_d[1]_i_1_n_0\ + ); +\aresetn_d_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => aresetn, + Q => p_0_in(1), + R => '0' + ); +\aresetn_d_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => \aresetn_d[1]_i_1_n_0\, + Q => \^s_ready_i_reg_1\, + R => '0' + ); +\gen_master_slots[0].w_issuing_cnt[3]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => s_axi_bready(0), + I1 => active_target_hot(0), + I2 => \^s_ready_i_reg_2\, + I3 => \^s_ready_i_reg_0\, + O => \gen_master_slots[0].w_issuing_cnt_reg[0]\ + ); +\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E2" + ) + port map ( + I0 => m_axi_bresp(0), + I1 => \^s_ready_i_reg_0\, + I2 => st_mr_bmesg(0), + O => \m_payload_i[0]_i_1_n_0\ + ); +\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E2" + ) + port map ( + I0 => m_axi_bresp(1), + I1 => \^s_ready_i_reg_0\, + I2 => st_mr_bmesg(1), + O => \m_payload_i[1]_i_1_n_0\ + ); +\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E2" + ) + port map ( + I0 => m_axi_bid(0), + I1 => \^s_ready_i_reg_0\, + I2 => \^s_ready_i_reg_2\, + O => \m_payload_i[2]_i_1_n_0\ + ); +\m_payload_i_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \m_payload_i[0]_i_1_n_0\, + Q => st_mr_bmesg(0), + R => '0' + ); +\m_payload_i_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \m_payload_i[1]_i_1_n_0\, + Q => st_mr_bmesg(1), + R => '0' + ); +\m_payload_i_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \m_payload_i[2]_i_1_n_0\, + Q => \^s_ready_i_reg_2\, + R => '0' + ); +\m_valid_i_i_1__4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^s_ready_i_reg_1\, + O => \^m_valid_i_reg_0\ + ); +m_valid_i_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"8BBBBBBB" + ) + port map ( + I0 => m_axi_bvalid(0), + I1 => \^m_axi_bready\(0), + I2 => \^s_ready_i_reg_2\, + I3 => active_target_hot(0), + I4 => s_axi_bready(0), + O => m_valid_i_i_2_n_0 + ); +m_valid_i_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => m_valid_i_i_2_n_0, + Q => \^s_ready_i_reg_0\, + R => \^m_valid_i_reg_0\ + ); +\s_axi_bresp[2]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => st_mr_bmesg(0), + I1 => active_target_enc_1, + O => s_axi_bresp(0) + ); +\s_axi_bresp[3]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => st_mr_bmesg(1), + I1 => active_target_enc_1, + O => s_axi_bresp(1) + ); +\s_ready_i_i_1__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => p_0_in(1), + O => \^p_1_in\ + ); +s_ready_i_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"800080FFFFFFFFFF" + ) + port map ( + I0 => s_axi_bready(0), + I1 => active_target_hot(0), + I2 => \^s_ready_i_reg_2\, + I3 => \^s_ready_i_reg_0\, + I4 => m_axi_bvalid(0), + I5 => \^s_ready_i_reg_1\, + O => s_ready_i_i_2_n_0 + ); +s_ready_i_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => s_ready_i_i_2_n_0, + Q => \^m_axi_bready\(0), + R => \^p_1_in\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ is + port ( + m_valid_i_reg_0 : out STD_LOGIC; + \skid_buffer_reg[64]_0\ : out STD_LOGIC; + \gen_master_slots[1].r_issuing_cnt_reg[8]\ : out STD_LOGIC; + \gen_master_slots[1].r_issuing_cnt_reg[8]_0\ : out STD_LOGIC; + \gen_arbiter.qual_reg_reg[0]\ : out STD_LOGIC; + \valid_qual_i1__0\ : out STD_LOGIC; + \gen_arbiter.qual_reg_reg[0]_0\ : out STD_LOGIC; + s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \aresetn_d_reg[1]\ : in STD_LOGIC; + aclk : in STD_LOGIC; + p_1_in : in STD_LOGIC; + active_target_enc_0 : in STD_LOGIC; + s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_arbiter.m_valid_i_reg\ : in STD_LOGIC; + r_issuing_cnt : in STD_LOGIC_VECTOR ( 1 downto 0 ); + p_11_in : in STD_LOGIC; + st_aa_arvalid_qual : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_master_slots[0].r_issuing_cnt_reg[2]\ : in STD_LOGIC; + \s_axi_araddr[29]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_valid_i_reg_1 : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); + p_13_in : in STD_LOGIC; + p_1_in_1 : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_11_axic_register_slice"; +end \Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\; + +architecture STRUCTURE of \Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ is + signal \^gen_arbiter.qual_reg_reg[0]_0\ : STD_LOGIC; + signal \^gen_master_slots[1].r_issuing_cnt_reg[8]_0\ : STD_LOGIC; + signal \m_payload_i[64]_i_1_n_0\ : STD_LOGIC; + signal \m_payload_i[65]_i_1_n_0\ : STD_LOGIC; + signal \m_payload_i[66]_i_1_n_0\ : STD_LOGIC; + signal m_valid_i0 : STD_LOGIC; + signal \^m_valid_i_reg_0\ : STD_LOGIC; + signal \s_ready_i_i_1__3_n_0\ : STD_LOGIC; + signal skid_buffer : STD_LOGIC_VECTOR ( 66 downto 64 ); + signal \^skid_buffer_reg[64]_0\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[65]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[66]\ : STD_LOGIC; + signal st_mr_rmesg : STD_LOGIC_VECTOR ( 68 downto 67 ); + signal \^valid_qual_i1__0\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \gen_arbiter.qual_reg[0]_i_5\ : label is "soft_lutpair157"; + attribute SOFT_HLUTNM of \m_payload_i[66]_i_1\ : label is "soft_lutpair156"; + attribute SOFT_HLUTNM of \s_axi_rlast[0]_INST_0\ : label is "soft_lutpair157"; + attribute SOFT_HLUTNM of \s_axi_rresp[0]_INST_0\ : label is "soft_lutpair158"; + attribute SOFT_HLUTNM of \s_axi_rresp[1]_INST_0\ : label is "soft_lutpair158"; + attribute SOFT_HLUTNM of \skid_buffer[64]_i_1\ : label is "soft_lutpair159"; + attribute SOFT_HLUTNM of \skid_buffer[65]_i_1\ : label is "soft_lutpair159"; + attribute SOFT_HLUTNM of \skid_buffer[66]_i_1\ : label is "soft_lutpair156"; +begin + \gen_arbiter.qual_reg_reg[0]_0\ <= \^gen_arbiter.qual_reg_reg[0]_0\; + \gen_master_slots[1].r_issuing_cnt_reg[8]_0\ <= \^gen_master_slots[1].r_issuing_cnt_reg[8]_0\; + m_valid_i_reg_0 <= \^m_valid_i_reg_0\; + \skid_buffer_reg[64]_0\ <= \^skid_buffer_reg[64]_0\; + \valid_qual_i1__0\ <= \^valid_qual_i1__0\; +\gen_arbiter.qual_reg[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8F" + ) + port map ( + I0 => \^valid_qual_i1__0\, + I1 => st_aa_arvalid_qual(0), + I2 => s_axi_arvalid(0), + O => \gen_arbiter.qual_reg_reg[0]\ + ); +\gen_arbiter.qual_reg[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBB0FFFFFFF0FFF" + ) + port map ( + I0 => \gen_master_slots[0].r_issuing_cnt_reg[2]\, + I1 => r_issuing_cnt(0), + I2 => r_issuing_cnt(1), + I3 => \^gen_arbiter.qual_reg_reg[0]_0\, + I4 => \s_axi_araddr[29]\(0), + I5 => m_valid_i_reg_1, + O => \^valid_qual_i1__0\ + ); +\gen_arbiter.qual_reg[0]_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => \^m_valid_i_reg_0\, + I1 => \^gen_master_slots[1].r_issuing_cnt_reg[8]_0\, + I2 => s_axi_rready(0), + I3 => active_target_enc_0, + O => \^gen_arbiter.qual_reg_reg[0]_0\ + ); +\gen_master_slots[1].r_issuing_cnt[8]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFF800000007FFF" + ) + port map ( + I0 => active_target_enc_0, + I1 => s_axi_rready(0), + I2 => \^gen_master_slots[1].r_issuing_cnt_reg[8]_0\, + I3 => \^m_valid_i_reg_0\, + I4 => \gen_arbiter.m_valid_i_reg\, + I5 => r_issuing_cnt(1), + O => \gen_master_slots[1].r_issuing_cnt_reg[8]\ + ); +\m_payload_i[64]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EFFFEEEEE000EEEE" + ) + port map ( + I0 => \^skid_buffer_reg[64]_0\, + I1 => \skid_buffer_reg_n_0_[64]\, + I2 => s_axi_rready(0), + I3 => active_target_enc_0, + I4 => \^m_valid_i_reg_0\, + I5 => st_mr_rmesg(67), + O => \m_payload_i[64]_i_1_n_0\ + ); +\m_payload_i[65]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EFFFEEEEE000EEEE" + ) + port map ( + I0 => \skid_buffer_reg_n_0_[65]\, + I1 => \^skid_buffer_reg[64]_0\, + I2 => s_axi_rready(0), + I3 => active_target_enc_0, + I4 => \^m_valid_i_reg_0\, + I5 => st_mr_rmesg(68), + O => \m_payload_i[65]_i_1_n_0\ + ); +\m_payload_i[66]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8FFB800" + ) + port map ( + I0 => p_13_in, + I1 => \^skid_buffer_reg[64]_0\, + I2 => \skid_buffer_reg_n_0_[66]\, + I3 => p_1_in_1, + I4 => \^gen_master_slots[1].r_issuing_cnt_reg[8]_0\, + O => \m_payload_i[66]_i_1_n_0\ + ); +\m_payload_i_reg[64]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \m_payload_i[64]_i_1_n_0\, + Q => st_mr_rmesg(67), + R => '0' + ); +\m_payload_i_reg[65]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \m_payload_i[65]_i_1_n_0\, + Q => st_mr_rmesg(68), + R => '0' + ); +\m_payload_i_reg[66]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \m_payload_i[66]_i_1_n_0\, + Q => \^gen_master_slots[1].r_issuing_cnt_reg[8]_0\, + R => '0' + ); +\m_valid_i_i_1__3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"DDFDFDFD" + ) + port map ( + I0 => \^skid_buffer_reg[64]_0\, + I1 => p_11_in, + I2 => \^m_valid_i_reg_0\, + I3 => active_target_enc_0, + I4 => s_axi_rready(0), + O => m_valid_i0 + ); +m_valid_i_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => m_valid_i0, + Q => \^m_valid_i_reg_0\, + R => \aresetn_d_reg[1]\ + ); +\s_axi_rlast[0]_INST_0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \^gen_master_slots[1].r_issuing_cnt_reg[8]_0\, + I1 => active_target_enc_0, + I2 => Q(2), + O => s_axi_rlast(0) + ); +\s_axi_rresp[0]_INST_0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => st_mr_rmesg(67), + I1 => active_target_enc_0, + I2 => Q(0), + O => s_axi_rresp(0) + ); +\s_axi_rresp[1]_INST_0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => st_mr_rmesg(68), + I1 => active_target_enc_0, + I2 => Q(1), + O => s_axi_rresp(1) + ); +\s_ready_i_i_1__3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D5D5FFD5" + ) + port map ( + I0 => \^m_valid_i_reg_0\, + I1 => active_target_enc_0, + I2 => s_axi_rready(0), + I3 => \^skid_buffer_reg[64]_0\, + I4 => p_11_in, + O => \s_ready_i_i_1__3_n_0\ + ); +s_ready_i_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_ready_i_i_1__3_n_0\, + Q => \^skid_buffer_reg[64]_0\, + R => p_1_in + ); +\skid_buffer[64]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^skid_buffer_reg[64]_0\, + I1 => \skid_buffer_reg_n_0_[64]\, + O => skid_buffer(64) + ); +\skid_buffer[65]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \skid_buffer_reg_n_0_[65]\, + I1 => \^skid_buffer_reg[64]_0\, + O => skid_buffer(65) + ); +\skid_buffer[66]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => p_13_in, + I1 => \^skid_buffer_reg[64]_0\, + I2 => \skid_buffer_reg_n_0_[66]\, + O => skid_buffer(66) + ); +\skid_buffer_reg[64]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => skid_buffer(64), + Q => \skid_buffer_reg_n_0_[64]\, + R => '0' + ); +\skid_buffer_reg[65]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => skid_buffer(65), + Q => \skid_buffer_reg_n_0_[65]\, + R => '0' + ); +\skid_buffer_reg[66]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => skid_buffer(66), + Q => \skid_buffer_reg_n_0_[66]\, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2_5\ is + port ( + m_valid_i_reg_0 : out STD_LOGIC; + \m_axi_rready[0]\ : out STD_LOGIC; + s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + \gen_arbiter.qual_reg_reg[0]\ : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \gen_master_slots[0].r_issuing_cnt_reg[0]\ : out STD_LOGIC; + \aresetn_d_reg[1]\ : in STD_LOGIC; + aclk : in STD_LOGIC; + p_1_in : in STD_LOGIC; + active_target_hot_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + active_target_enc : in STD_LOGIC; + p_30_out : in STD_LOGIC; + \gen_master_slots[0].r_issuing_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \gen_arbiter.m_valid_i_reg\ : in STD_LOGIC; + m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2_5\ : entity is "axi_register_slice_v2_1_11_axic_register_slice"; +end \Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2_5\; + +architecture STRUCTURE of \Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2_5\ is + signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\ : STD_LOGIC; + signal \^m_axi_rready[0]\ : STD_LOGIC; + signal m_valid_i0 : STD_LOGIC; + signal \^m_valid_i_reg_0\ : STD_LOGIC; + signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC; + signal skid_buffer : STD_LOGIC_VECTOR ( 66 downto 0 ); + signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[65]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[66]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; + signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; + signal st_mr_rmesg : STD_LOGIC_VECTOR ( 66 downto 3 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[2]_i_1\ : label is "soft_lutpair88"; + attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_2\ : label is "soft_lutpair88"; + attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_4\ : label is "soft_lutpair89"; + attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_5\ : label is "soft_lutpair89"; + attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair118"; + attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair117"; + attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair117"; + attribute SOFT_HLUTNM of \m_payload_i[13]_i_1\ : label is "soft_lutpair116"; + attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair116"; + attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair115"; + attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair115"; + attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair114"; + attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair114"; + attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair113"; + attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair122"; + attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair113"; + attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair112"; + attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair112"; + attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair111"; + attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair111"; + attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair110"; + attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair110"; + attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair109"; + attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair109"; + attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair108"; + attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair122"; + attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair108"; + attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair107"; + attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair107"; + attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair106"; + attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair106"; + attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair105"; + attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair105"; + attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair104"; + attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair104"; + attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair103"; + attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair121"; + attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair103"; + attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair102"; + attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair102"; + attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair101"; + attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair101"; + attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair100"; + attribute SOFT_HLUTNM of \m_payload_i[46]_i_1\ : label is "soft_lutpair100"; + attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair99"; + attribute SOFT_HLUTNM of \m_payload_i[48]_i_1\ : label is "soft_lutpair99"; + attribute SOFT_HLUTNM of \m_payload_i[49]_i_1\ : label is "soft_lutpair98"; + attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair121"; + attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair98"; + attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair97"; + attribute SOFT_HLUTNM of \m_payload_i[52]_i_1\ : label is "soft_lutpair97"; + attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair96"; + attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair96"; + attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair95"; + attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair95"; + attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair94"; + attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair94"; + attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair93"; + attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair120"; + attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair93"; + attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair92"; + attribute SOFT_HLUTNM of \m_payload_i[62]_i_1\ : label is "soft_lutpair92"; + attribute SOFT_HLUTNM of \m_payload_i[63]_i_1\ : label is "soft_lutpair91"; + attribute SOFT_HLUTNM of \m_payload_i[64]_i_1\ : label is "soft_lutpair91"; + attribute SOFT_HLUTNM of \m_payload_i[65]_i_1\ : label is "soft_lutpair90"; + attribute SOFT_HLUTNM of \m_payload_i[66]_i_2\ : label is "soft_lutpair90"; + attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair120"; + attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair119"; + attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair119"; + attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair118"; + attribute SOFT_HLUTNM of \s_axi_rdata[0]_INST_0\ : label is "soft_lutpair154"; + attribute SOFT_HLUTNM of \s_axi_rdata[10]_INST_0\ : label is "soft_lutpair149"; + attribute SOFT_HLUTNM of \s_axi_rdata[11]_INST_0\ : label is "soft_lutpair149"; + attribute SOFT_HLUTNM of \s_axi_rdata[12]_INST_0\ : label is "soft_lutpair148"; + attribute SOFT_HLUTNM of \s_axi_rdata[13]_INST_0\ : label is "soft_lutpair148"; + attribute SOFT_HLUTNM of \s_axi_rdata[14]_INST_0\ : label is "soft_lutpair147"; + attribute SOFT_HLUTNM of \s_axi_rdata[15]_INST_0\ : label is "soft_lutpair147"; + attribute SOFT_HLUTNM of \s_axi_rdata[16]_INST_0\ : label is "soft_lutpair146"; + attribute SOFT_HLUTNM of \s_axi_rdata[17]_INST_0\ : label is "soft_lutpair146"; + attribute SOFT_HLUTNM of \s_axi_rdata[18]_INST_0\ : label is "soft_lutpair145"; + attribute SOFT_HLUTNM of \s_axi_rdata[19]_INST_0\ : label is "soft_lutpair145"; + attribute SOFT_HLUTNM of \s_axi_rdata[1]_INST_0\ : label is "soft_lutpair154"; + attribute SOFT_HLUTNM of \s_axi_rdata[20]_INST_0\ : label is "soft_lutpair144"; + attribute SOFT_HLUTNM of \s_axi_rdata[21]_INST_0\ : label is "soft_lutpair144"; + attribute SOFT_HLUTNM of \s_axi_rdata[22]_INST_0\ : label is "soft_lutpair143"; + attribute SOFT_HLUTNM of \s_axi_rdata[23]_INST_0\ : label is "soft_lutpair143"; + attribute SOFT_HLUTNM of \s_axi_rdata[24]_INST_0\ : label is "soft_lutpair142"; + attribute SOFT_HLUTNM of \s_axi_rdata[25]_INST_0\ : label is "soft_lutpair142"; + attribute SOFT_HLUTNM of \s_axi_rdata[26]_INST_0\ : label is "soft_lutpair141"; + attribute SOFT_HLUTNM of \s_axi_rdata[27]_INST_0\ : label is "soft_lutpair141"; + attribute SOFT_HLUTNM of \s_axi_rdata[28]_INST_0\ : label is "soft_lutpair140"; + attribute SOFT_HLUTNM of \s_axi_rdata[29]_INST_0\ : label is "soft_lutpair140"; + attribute SOFT_HLUTNM of \s_axi_rdata[2]_INST_0\ : label is "soft_lutpair153"; + attribute SOFT_HLUTNM of \s_axi_rdata[30]_INST_0\ : label is "soft_lutpair139"; + attribute SOFT_HLUTNM of \s_axi_rdata[31]_INST_0\ : label is "soft_lutpair139"; + attribute SOFT_HLUTNM of \s_axi_rdata[32]_INST_0\ : label is "soft_lutpair138"; + attribute SOFT_HLUTNM of \s_axi_rdata[33]_INST_0\ : label is "soft_lutpair138"; + attribute SOFT_HLUTNM of \s_axi_rdata[34]_INST_0\ : label is "soft_lutpair137"; + attribute SOFT_HLUTNM of \s_axi_rdata[35]_INST_0\ : label is "soft_lutpair137"; + attribute SOFT_HLUTNM of \s_axi_rdata[36]_INST_0\ : label is "soft_lutpair136"; + attribute SOFT_HLUTNM of \s_axi_rdata[37]_INST_0\ : label is "soft_lutpair136"; + attribute SOFT_HLUTNM of \s_axi_rdata[38]_INST_0\ : label is "soft_lutpair135"; + attribute SOFT_HLUTNM of \s_axi_rdata[39]_INST_0\ : label is "soft_lutpair135"; + attribute SOFT_HLUTNM of \s_axi_rdata[3]_INST_0\ : label is "soft_lutpair153"; + attribute SOFT_HLUTNM of \s_axi_rdata[40]_INST_0\ : label is "soft_lutpair134"; + attribute SOFT_HLUTNM of \s_axi_rdata[41]_INST_0\ : label is "soft_lutpair134"; + attribute SOFT_HLUTNM of \s_axi_rdata[42]_INST_0\ : label is "soft_lutpair133"; + attribute SOFT_HLUTNM of \s_axi_rdata[43]_INST_0\ : label is "soft_lutpair133"; + attribute SOFT_HLUTNM of \s_axi_rdata[44]_INST_0\ : label is "soft_lutpair132"; + attribute SOFT_HLUTNM of \s_axi_rdata[45]_INST_0\ : label is "soft_lutpair132"; + attribute SOFT_HLUTNM of \s_axi_rdata[46]_INST_0\ : label is "soft_lutpair131"; + attribute SOFT_HLUTNM of \s_axi_rdata[47]_INST_0\ : label is "soft_lutpair131"; + attribute SOFT_HLUTNM of \s_axi_rdata[48]_INST_0\ : label is "soft_lutpair130"; + attribute SOFT_HLUTNM of \s_axi_rdata[49]_INST_0\ : label is "soft_lutpair130"; + attribute SOFT_HLUTNM of \s_axi_rdata[4]_INST_0\ : label is "soft_lutpair152"; + attribute SOFT_HLUTNM of \s_axi_rdata[50]_INST_0\ : label is "soft_lutpair129"; + attribute SOFT_HLUTNM of \s_axi_rdata[51]_INST_0\ : label is "soft_lutpair129"; + attribute SOFT_HLUTNM of \s_axi_rdata[52]_INST_0\ : label is "soft_lutpair128"; + attribute SOFT_HLUTNM of \s_axi_rdata[53]_INST_0\ : label is "soft_lutpair128"; + attribute SOFT_HLUTNM of \s_axi_rdata[54]_INST_0\ : label is "soft_lutpair127"; + attribute SOFT_HLUTNM of \s_axi_rdata[55]_INST_0\ : label is "soft_lutpair127"; + attribute SOFT_HLUTNM of \s_axi_rdata[56]_INST_0\ : label is "soft_lutpair126"; + attribute SOFT_HLUTNM of \s_axi_rdata[57]_INST_0\ : label is "soft_lutpair126"; + attribute SOFT_HLUTNM of \s_axi_rdata[58]_INST_0\ : label is "soft_lutpair125"; + attribute SOFT_HLUTNM of \s_axi_rdata[59]_INST_0\ : label is "soft_lutpair125"; + attribute SOFT_HLUTNM of \s_axi_rdata[5]_INST_0\ : label is "soft_lutpair152"; + attribute SOFT_HLUTNM of \s_axi_rdata[60]_INST_0\ : label is "soft_lutpair124"; + attribute SOFT_HLUTNM of \s_axi_rdata[61]_INST_0\ : label is "soft_lutpair124"; + attribute SOFT_HLUTNM of \s_axi_rdata[62]_INST_0\ : label is "soft_lutpair123"; + attribute SOFT_HLUTNM of \s_axi_rdata[63]_INST_0\ : label is "soft_lutpair123"; + attribute SOFT_HLUTNM of \s_axi_rdata[6]_INST_0\ : label is "soft_lutpair151"; + attribute SOFT_HLUTNM of \s_axi_rdata[7]_INST_0\ : label is "soft_lutpair151"; + attribute SOFT_HLUTNM of \s_axi_rdata[8]_INST_0\ : label is "soft_lutpair150"; + attribute SOFT_HLUTNM of \s_axi_rdata[9]_INST_0\ : label is "soft_lutpair150"; +begin + Q(2 downto 0) <= \^q\(2 downto 0); + \m_axi_rready[0]\ <= \^m_axi_rready[0]\; + m_valid_i_reg_0 <= \^m_valid_i_reg_0\; +\gen_arbiter.qual_reg[0]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"E200000000000000" + ) + port map ( + I0 => \^q\(2), + I1 => active_target_enc, + I2 => p_30_out, + I3 => \^m_valid_i_reg_0\, + I4 => active_target_hot_0(0), + I5 => s_axi_rready(0), + O => \gen_arbiter.qual_reg_reg[0]\ + ); +\gen_master_slots[0].r_issuing_cnt[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"69" + ) + port map ( + I0 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(1), + I1 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(0), + I2 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\, + O => D(0) + ); +\gen_master_slots[0].r_issuing_cnt[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AA9" + ) + port map ( + I0 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(2), + I1 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(0), + I2 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(1), + I3 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\, + O => D(1) + ); +\gen_master_slots[0].r_issuing_cnt[3]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAAAAA9" + ) + port map ( + I0 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(3), + I1 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(1), + I2 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(2), + I3 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(0), + I4 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\, + O => D(2) + ); +\gen_master_slots[0].r_issuing_cnt[3]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => \^m_valid_i_reg_0\, + I1 => active_target_hot_0(0), + I2 => s_axi_rready(0), + I3 => \^q\(2), + O => \gen_master_slots[0].r_issuing_cnt_reg[0]\ + ); +\gen_master_slots[0].r_issuing_cnt[3]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00007FFF" + ) + port map ( + I0 => \^q\(2), + I1 => s_axi_rready(0), + I2 => active_target_hot_0(0), + I3 => \^m_valid_i_reg_0\, + I4 => \gen_arbiter.m_valid_i_reg\, + O => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\ + ); +\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(0), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[0]\, + O => skid_buffer(0) + ); +\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(10), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[10]\, + O => skid_buffer(10) + ); +\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(11), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[11]\, + O => skid_buffer(11) + ); +\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(12), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[12]\, + O => skid_buffer(12) + ); +\m_payload_i[13]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(13), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[13]\, + O => skid_buffer(13) + ); +\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(14), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[14]\, + O => skid_buffer(14) + ); +\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(15), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[15]\, + O => skid_buffer(15) + ); +\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(16), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[16]\, + O => skid_buffer(16) + ); +\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(17), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[17]\, + O => skid_buffer(17) + ); +\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(18), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[18]\, + O => skid_buffer(18) + ); +\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(19), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[19]\, + O => skid_buffer(19) + ); +\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(1), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[1]\, + O => skid_buffer(1) + ); +\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(20), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[20]\, + O => skid_buffer(20) + ); +\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(21), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[21]\, + O => skid_buffer(21) + ); +\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(22), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[22]\, + O => skid_buffer(22) + ); +\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(23), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[23]\, + O => skid_buffer(23) + ); +\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(24), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[24]\, + O => skid_buffer(24) + ); +\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(25), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[25]\, + O => skid_buffer(25) + ); +\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(26), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[26]\, + O => skid_buffer(26) + ); +\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(27), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[27]\, + O => skid_buffer(27) + ); +\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(28), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[28]\, + O => skid_buffer(28) + ); +\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(29), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[29]\, + O => skid_buffer(29) + ); +\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(2), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[2]\, + O => skid_buffer(2) + ); +\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(30), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[30]\, + O => skid_buffer(30) + ); +\m_payload_i[31]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(31), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[31]\, + O => skid_buffer(31) + ); +\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(32), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[32]\, + O => skid_buffer(32) + ); +\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(33), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[33]\, + O => skid_buffer(33) + ); +\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(34), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[34]\, + O => skid_buffer(34) + ); +\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(35), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[35]\, + O => skid_buffer(35) + ); +\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(36), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[36]\, + O => skid_buffer(36) + ); +\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(37), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[37]\, + O => skid_buffer(37) + ); +\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(38), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[38]\, + O => skid_buffer(38) + ); +\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(39), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[39]\, + O => skid_buffer(39) + ); +\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(3), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[3]\, + O => skid_buffer(3) + ); +\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(40), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[40]\, + O => skid_buffer(40) + ); +\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(41), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[41]\, + O => skid_buffer(41) + ); +\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(42), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[42]\, + O => skid_buffer(42) + ); +\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(43), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[43]\, + O => skid_buffer(43) + ); +\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(44), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[44]\, + O => skid_buffer(44) + ); +\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(45), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[45]\, + O => skid_buffer(45) + ); +\m_payload_i[46]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(46), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[46]\, + O => skid_buffer(46) + ); +\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(47), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[47]\, + O => skid_buffer(47) + ); +\m_payload_i[48]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(48), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[48]\, + O => skid_buffer(48) + ); +\m_payload_i[49]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(49), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[49]\, + O => skid_buffer(49) + ); +\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(4), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[4]\, + O => skid_buffer(4) + ); +\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(50), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[50]\, + O => skid_buffer(50) + ); +\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(51), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[51]\, + O => skid_buffer(51) + ); +\m_payload_i[52]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(52), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[52]\, + O => skid_buffer(52) + ); +\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(53), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[53]\, + O => skid_buffer(53) + ); +\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(54), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[54]\, + O => skid_buffer(54) + ); +\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(55), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[55]\, + O => skid_buffer(55) + ); +\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(56), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[56]\, + O => skid_buffer(56) + ); +\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(57), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[57]\, + O => skid_buffer(57) + ); +\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(58), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[58]\, + O => skid_buffer(58) + ); +\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(59), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[59]\, + O => skid_buffer(59) + ); +\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(5), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[5]\, + O => skid_buffer(5) + ); +\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(60), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[60]\, + O => skid_buffer(60) + ); +\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(61), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[61]\, + O => skid_buffer(61) + ); +\m_payload_i[62]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(62), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[62]\, + O => skid_buffer(62) + ); +\m_payload_i[63]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(63), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[63]\, + O => skid_buffer(63) + ); +\m_payload_i[64]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rresp(0), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[64]\, + O => skid_buffer(64) + ); +\m_payload_i[65]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rresp(1), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[65]\, + O => skid_buffer(65) + ); +\m_payload_i[66]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rlast(0), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[66]\, + O => skid_buffer(66) + ); +\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(6), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[6]\, + O => skid_buffer(6) + ); +\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(7), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[7]\, + O => skid_buffer(7) + ); +\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(8), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[8]\, + O => skid_buffer(8) + ); +\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => m_axi_rdata(9), + I1 => \^m_axi_rready[0]\, + I2 => \skid_buffer_reg_n_0_[9]\, + O => skid_buffer(9) + ); +\m_payload_i_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(0), + Q => st_mr_rmesg(3), + R => '0' + ); +\m_payload_i_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(10), + Q => st_mr_rmesg(13), + R => '0' + ); +\m_payload_i_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(11), + Q => st_mr_rmesg(14), + R => '0' + ); +\m_payload_i_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(12), + Q => st_mr_rmesg(15), + R => '0' + ); +\m_payload_i_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(13), + Q => st_mr_rmesg(16), + R => '0' + ); +\m_payload_i_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(14), + Q => st_mr_rmesg(17), + R => '0' + ); +\m_payload_i_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(15), + Q => st_mr_rmesg(18), + R => '0' + ); +\m_payload_i_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(16), + Q => st_mr_rmesg(19), + R => '0' + ); +\m_payload_i_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(17), + Q => st_mr_rmesg(20), + R => '0' + ); +\m_payload_i_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(18), + Q => st_mr_rmesg(21), + R => '0' + ); +\m_payload_i_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(19), + Q => st_mr_rmesg(22), + R => '0' + ); +\m_payload_i_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(1), + Q => st_mr_rmesg(4), + R => '0' + ); +\m_payload_i_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(20), + Q => st_mr_rmesg(23), + R => '0' + ); +\m_payload_i_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(21), + Q => st_mr_rmesg(24), + R => '0' + ); +\m_payload_i_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(22), + Q => st_mr_rmesg(25), + R => '0' + ); +\m_payload_i_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(23), + Q => st_mr_rmesg(26), + R => '0' + ); +\m_payload_i_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(24), + Q => st_mr_rmesg(27), + R => '0' + ); +\m_payload_i_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(25), + Q => st_mr_rmesg(28), + R => '0' + ); +\m_payload_i_reg[26]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(26), + Q => st_mr_rmesg(29), + R => '0' + ); +\m_payload_i_reg[27]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(27), + Q => st_mr_rmesg(30), + R => '0' + ); +\m_payload_i_reg[28]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(28), + Q => st_mr_rmesg(31), + R => '0' + ); +\m_payload_i_reg[29]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(29), + Q => st_mr_rmesg(32), + R => '0' + ); +\m_payload_i_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(2), + Q => st_mr_rmesg(5), + R => '0' + ); +\m_payload_i_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(30), + Q => st_mr_rmesg(33), + R => '0' + ); +\m_payload_i_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(31), + Q => st_mr_rmesg(34), + R => '0' + ); +\m_payload_i_reg[32]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(32), + Q => st_mr_rmesg(35), + R => '0' + ); +\m_payload_i_reg[33]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(33), + Q => st_mr_rmesg(36), + R => '0' + ); +\m_payload_i_reg[34]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(34), + Q => st_mr_rmesg(37), + R => '0' + ); +\m_payload_i_reg[35]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(35), + Q => st_mr_rmesg(38), + R => '0' + ); +\m_payload_i_reg[36]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(36), + Q => st_mr_rmesg(39), + R => '0' + ); +\m_payload_i_reg[37]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(37), + Q => st_mr_rmesg(40), + R => '0' + ); +\m_payload_i_reg[38]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(38), + Q => st_mr_rmesg(41), + R => '0' + ); +\m_payload_i_reg[39]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(39), + Q => st_mr_rmesg(42), + R => '0' + ); +\m_payload_i_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(3), + Q => st_mr_rmesg(6), + R => '0' + ); +\m_payload_i_reg[40]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(40), + Q => st_mr_rmesg(43), + R => '0' + ); +\m_payload_i_reg[41]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(41), + Q => st_mr_rmesg(44), + R => '0' + ); +\m_payload_i_reg[42]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(42), + Q => st_mr_rmesg(45), + R => '0' + ); +\m_payload_i_reg[43]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(43), + Q => st_mr_rmesg(46), + R => '0' + ); +\m_payload_i_reg[44]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(44), + Q => st_mr_rmesg(47), + R => '0' + ); +\m_payload_i_reg[45]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(45), + Q => st_mr_rmesg(48), + R => '0' + ); +\m_payload_i_reg[46]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(46), + Q => st_mr_rmesg(49), + R => '0' + ); +\m_payload_i_reg[47]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(47), + Q => st_mr_rmesg(50), + R => '0' + ); +\m_payload_i_reg[48]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(48), + Q => st_mr_rmesg(51), + R => '0' + ); +\m_payload_i_reg[49]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(49), + Q => st_mr_rmesg(52), + R => '0' + ); +\m_payload_i_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(4), + Q => st_mr_rmesg(7), + R => '0' + ); +\m_payload_i_reg[50]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(50), + Q => st_mr_rmesg(53), + R => '0' + ); +\m_payload_i_reg[51]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(51), + Q => st_mr_rmesg(54), + R => '0' + ); +\m_payload_i_reg[52]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(52), + Q => st_mr_rmesg(55), + R => '0' + ); +\m_payload_i_reg[53]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(53), + Q => st_mr_rmesg(56), + R => '0' + ); +\m_payload_i_reg[54]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(54), + Q => st_mr_rmesg(57), + R => '0' + ); +\m_payload_i_reg[55]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(55), + Q => st_mr_rmesg(58), + R => '0' + ); +\m_payload_i_reg[56]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(56), + Q => st_mr_rmesg(59), + R => '0' + ); +\m_payload_i_reg[57]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(57), + Q => st_mr_rmesg(60), + R => '0' + ); +\m_payload_i_reg[58]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(58), + Q => st_mr_rmesg(61), + R => '0' + ); +\m_payload_i_reg[59]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(59), + Q => st_mr_rmesg(62), + R => '0' + ); +\m_payload_i_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(5), + Q => st_mr_rmesg(8), + R => '0' + ); +\m_payload_i_reg[60]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(60), + Q => st_mr_rmesg(63), + R => '0' + ); +\m_payload_i_reg[61]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(61), + Q => st_mr_rmesg(64), + R => '0' + ); +\m_payload_i_reg[62]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(62), + Q => st_mr_rmesg(65), + R => '0' + ); +\m_payload_i_reg[63]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(63), + Q => st_mr_rmesg(66), + R => '0' + ); +\m_payload_i_reg[64]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(64), + Q => \^q\(0), + R => '0' + ); +\m_payload_i_reg[65]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(65), + Q => \^q\(1), + R => '0' + ); +\m_payload_i_reg[66]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(66), + Q => \^q\(2), + R => '0' + ); +\m_payload_i_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(6), + Q => st_mr_rmesg(9), + R => '0' + ); +\m_payload_i_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(7), + Q => st_mr_rmesg(10), + R => '0' + ); +\m_payload_i_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(8), + Q => st_mr_rmesg(11), + R => '0' + ); +\m_payload_i_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => E(0), + D => skid_buffer(9), + Q => st_mr_rmesg(12), + R => '0' + ); +\m_valid_i_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"DDFDFDFD" + ) + port map ( + I0 => \^m_axi_rready[0]\, + I1 => m_axi_rvalid(0), + I2 => \^m_valid_i_reg_0\, + I3 => active_target_hot_0(0), + I4 => s_axi_rready(0), + O => m_valid_i0 + ); +m_valid_i_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => m_valid_i0, + Q => \^m_valid_i_reg_0\, + R => \aresetn_d_reg[1]\ + ); +\s_axi_rdata[0]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(3), + I1 => active_target_enc, + O => s_axi_rdata(0) + ); +\s_axi_rdata[10]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(13), + I1 => active_target_enc, + O => s_axi_rdata(10) + ); +\s_axi_rdata[11]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(14), + I1 => active_target_enc, + O => s_axi_rdata(11) + ); +\s_axi_rdata[12]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(15), + I1 => active_target_enc, + O => s_axi_rdata(12) + ); +\s_axi_rdata[13]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(16), + I1 => active_target_enc, + O => s_axi_rdata(13) + ); +\s_axi_rdata[14]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(17), + I1 => active_target_enc, + O => s_axi_rdata(14) + ); +\s_axi_rdata[15]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(18), + I1 => active_target_enc, + O => s_axi_rdata(15) + ); +\s_axi_rdata[16]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(19), + I1 => active_target_enc, + O => s_axi_rdata(16) + ); +\s_axi_rdata[17]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(20), + I1 => active_target_enc, + O => s_axi_rdata(17) + ); +\s_axi_rdata[18]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(21), + I1 => active_target_enc, + O => s_axi_rdata(18) + ); +\s_axi_rdata[19]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(22), + I1 => active_target_enc, + O => s_axi_rdata(19) + ); +\s_axi_rdata[1]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(4), + I1 => active_target_enc, + O => s_axi_rdata(1) + ); +\s_axi_rdata[20]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(23), + I1 => active_target_enc, + O => s_axi_rdata(20) + ); +\s_axi_rdata[21]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(24), + I1 => active_target_enc, + O => s_axi_rdata(21) + ); +\s_axi_rdata[22]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(25), + I1 => active_target_enc, + O => s_axi_rdata(22) + ); +\s_axi_rdata[23]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(26), + I1 => active_target_enc, + O => s_axi_rdata(23) + ); +\s_axi_rdata[24]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(27), + I1 => active_target_enc, + O => s_axi_rdata(24) + ); +\s_axi_rdata[25]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(28), + I1 => active_target_enc, + O => s_axi_rdata(25) + ); +\s_axi_rdata[26]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(29), + I1 => active_target_enc, + O => s_axi_rdata(26) + ); +\s_axi_rdata[27]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(30), + I1 => active_target_enc, + O => s_axi_rdata(27) + ); +\s_axi_rdata[28]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(31), + I1 => active_target_enc, + O => s_axi_rdata(28) + ); +\s_axi_rdata[29]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(32), + I1 => active_target_enc, + O => s_axi_rdata(29) + ); +\s_axi_rdata[2]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(5), + I1 => active_target_enc, + O => s_axi_rdata(2) + ); +\s_axi_rdata[30]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(33), + I1 => active_target_enc, + O => s_axi_rdata(30) + ); +\s_axi_rdata[31]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(34), + I1 => active_target_enc, + O => s_axi_rdata(31) + ); +\s_axi_rdata[32]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(35), + I1 => active_target_enc, + O => s_axi_rdata(32) + ); +\s_axi_rdata[33]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(36), + I1 => active_target_enc, + O => s_axi_rdata(33) + ); +\s_axi_rdata[34]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(37), + I1 => active_target_enc, + O => s_axi_rdata(34) + ); +\s_axi_rdata[35]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(38), + I1 => active_target_enc, + O => s_axi_rdata(35) + ); +\s_axi_rdata[36]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(39), + I1 => active_target_enc, + O => s_axi_rdata(36) + ); +\s_axi_rdata[37]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(40), + I1 => active_target_enc, + O => s_axi_rdata(37) + ); +\s_axi_rdata[38]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(41), + I1 => active_target_enc, + O => s_axi_rdata(38) + ); +\s_axi_rdata[39]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(42), + I1 => active_target_enc, + O => s_axi_rdata(39) + ); +\s_axi_rdata[3]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(6), + I1 => active_target_enc, + O => s_axi_rdata(3) + ); +\s_axi_rdata[40]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(43), + I1 => active_target_enc, + O => s_axi_rdata(40) + ); +\s_axi_rdata[41]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(44), + I1 => active_target_enc, + O => s_axi_rdata(41) + ); +\s_axi_rdata[42]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(45), + I1 => active_target_enc, + O => s_axi_rdata(42) + ); +\s_axi_rdata[43]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(46), + I1 => active_target_enc, + O => s_axi_rdata(43) + ); +\s_axi_rdata[44]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(47), + I1 => active_target_enc, + O => s_axi_rdata(44) + ); +\s_axi_rdata[45]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(48), + I1 => active_target_enc, + O => s_axi_rdata(45) + ); +\s_axi_rdata[46]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(49), + I1 => active_target_enc, + O => s_axi_rdata(46) + ); +\s_axi_rdata[47]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(50), + I1 => active_target_enc, + O => s_axi_rdata(47) + ); +\s_axi_rdata[48]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(51), + I1 => active_target_enc, + O => s_axi_rdata(48) + ); +\s_axi_rdata[49]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(52), + I1 => active_target_enc, + O => s_axi_rdata(49) + ); +\s_axi_rdata[4]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(7), + I1 => active_target_enc, + O => s_axi_rdata(4) + ); +\s_axi_rdata[50]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(53), + I1 => active_target_enc, + O => s_axi_rdata(50) + ); +\s_axi_rdata[51]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(54), + I1 => active_target_enc, + O => s_axi_rdata(51) + ); +\s_axi_rdata[52]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(55), + I1 => active_target_enc, + O => s_axi_rdata(52) + ); +\s_axi_rdata[53]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(56), + I1 => active_target_enc, + O => s_axi_rdata(53) + ); +\s_axi_rdata[54]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(57), + I1 => active_target_enc, + O => s_axi_rdata(54) + ); +\s_axi_rdata[55]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(58), + I1 => active_target_enc, + O => s_axi_rdata(55) + ); +\s_axi_rdata[56]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(59), + I1 => active_target_enc, + O => s_axi_rdata(56) + ); +\s_axi_rdata[57]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(60), + I1 => active_target_enc, + O => s_axi_rdata(57) + ); +\s_axi_rdata[58]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(61), + I1 => active_target_enc, + O => s_axi_rdata(58) + ); +\s_axi_rdata[59]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(62), + I1 => active_target_enc, + O => s_axi_rdata(59) + ); +\s_axi_rdata[5]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(8), + I1 => active_target_enc, + O => s_axi_rdata(5) + ); +\s_axi_rdata[60]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(63), + I1 => active_target_enc, + O => s_axi_rdata(60) + ); +\s_axi_rdata[61]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(64), + I1 => active_target_enc, + O => s_axi_rdata(61) + ); +\s_axi_rdata[62]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(65), + I1 => active_target_enc, + O => s_axi_rdata(62) + ); +\s_axi_rdata[63]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(66), + I1 => active_target_enc, + O => s_axi_rdata(63) + ); +\s_axi_rdata[6]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(9), + I1 => active_target_enc, + O => s_axi_rdata(6) + ); +\s_axi_rdata[7]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(10), + I1 => active_target_enc, + O => s_axi_rdata(7) + ); +\s_axi_rdata[8]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(11), + I1 => active_target_enc, + O => s_axi_rdata(8) + ); +\s_axi_rdata[9]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => st_mr_rmesg(12), + I1 => active_target_enc, + O => s_axi_rdata(9) + ); +\s_ready_i_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D5D5FFD5" + ) + port map ( + I0 => \^m_valid_i_reg_0\, + I1 => active_target_hot_0(0), + I2 => s_axi_rready(0), + I3 => \^m_axi_rready[0]\, + I4 => m_axi_rvalid(0), + O => \s_ready_i_i_1__2_n_0\ + ); +s_ready_i_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \s_ready_i_i_1__2_n_0\, + Q => \^m_axi_rready[0]\, + R => p_1_in + ); +\skid_buffer_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(0), + Q => \skid_buffer_reg_n_0_[0]\, + R => '0' + ); +\skid_buffer_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(10), + Q => \skid_buffer_reg_n_0_[10]\, + R => '0' + ); +\skid_buffer_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(11), + Q => \skid_buffer_reg_n_0_[11]\, + R => '0' + ); +\skid_buffer_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(12), + Q => \skid_buffer_reg_n_0_[12]\, + R => '0' + ); +\skid_buffer_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(13), + Q => \skid_buffer_reg_n_0_[13]\, + R => '0' + ); +\skid_buffer_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(14), + Q => \skid_buffer_reg_n_0_[14]\, + R => '0' + ); +\skid_buffer_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(15), + Q => \skid_buffer_reg_n_0_[15]\, + R => '0' + ); +\skid_buffer_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(16), + Q => \skid_buffer_reg_n_0_[16]\, + R => '0' + ); +\skid_buffer_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(17), + Q => \skid_buffer_reg_n_0_[17]\, + R => '0' + ); +\skid_buffer_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(18), + Q => \skid_buffer_reg_n_0_[18]\, + R => '0' + ); +\skid_buffer_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(19), + Q => \skid_buffer_reg_n_0_[19]\, + R => '0' + ); +\skid_buffer_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(1), + Q => \skid_buffer_reg_n_0_[1]\, + R => '0' + ); +\skid_buffer_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(20), + Q => \skid_buffer_reg_n_0_[20]\, + R => '0' + ); +\skid_buffer_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(21), + Q => \skid_buffer_reg_n_0_[21]\, + R => '0' + ); +\skid_buffer_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(22), + Q => \skid_buffer_reg_n_0_[22]\, + R => '0' + ); +\skid_buffer_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(23), + Q => \skid_buffer_reg_n_0_[23]\, + R => '0' + ); +\skid_buffer_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(24), + Q => \skid_buffer_reg_n_0_[24]\, + R => '0' + ); +\skid_buffer_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(25), + Q => \skid_buffer_reg_n_0_[25]\, + R => '0' + ); +\skid_buffer_reg[26]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(26), + Q => \skid_buffer_reg_n_0_[26]\, + R => '0' + ); +\skid_buffer_reg[27]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(27), + Q => \skid_buffer_reg_n_0_[27]\, + R => '0' + ); +\skid_buffer_reg[28]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(28), + Q => \skid_buffer_reg_n_0_[28]\, + R => '0' + ); +\skid_buffer_reg[29]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(29), + Q => \skid_buffer_reg_n_0_[29]\, + R => '0' + ); +\skid_buffer_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(2), + Q => \skid_buffer_reg_n_0_[2]\, + R => '0' + ); +\skid_buffer_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(30), + Q => \skid_buffer_reg_n_0_[30]\, + R => '0' + ); +\skid_buffer_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(31), + Q => \skid_buffer_reg_n_0_[31]\, + R => '0' + ); +\skid_buffer_reg[32]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(32), + Q => \skid_buffer_reg_n_0_[32]\, + R => '0' + ); +\skid_buffer_reg[33]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(33), + Q => \skid_buffer_reg_n_0_[33]\, + R => '0' + ); +\skid_buffer_reg[34]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(34), + Q => \skid_buffer_reg_n_0_[34]\, + R => '0' + ); +\skid_buffer_reg[35]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(35), + Q => \skid_buffer_reg_n_0_[35]\, + R => '0' + ); +\skid_buffer_reg[36]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(36), + Q => \skid_buffer_reg_n_0_[36]\, + R => '0' + ); +\skid_buffer_reg[37]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(37), + Q => \skid_buffer_reg_n_0_[37]\, + R => '0' + ); +\skid_buffer_reg[38]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(38), + Q => \skid_buffer_reg_n_0_[38]\, + R => '0' + ); +\skid_buffer_reg[39]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(39), + Q => \skid_buffer_reg_n_0_[39]\, + R => '0' + ); +\skid_buffer_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(3), + Q => \skid_buffer_reg_n_0_[3]\, + R => '0' + ); +\skid_buffer_reg[40]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(40), + Q => \skid_buffer_reg_n_0_[40]\, + R => '0' + ); +\skid_buffer_reg[41]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(41), + Q => \skid_buffer_reg_n_0_[41]\, + R => '0' + ); +\skid_buffer_reg[42]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(42), + Q => \skid_buffer_reg_n_0_[42]\, + R => '0' + ); +\skid_buffer_reg[43]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(43), + Q => \skid_buffer_reg_n_0_[43]\, + R => '0' + ); +\skid_buffer_reg[44]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(44), + Q => \skid_buffer_reg_n_0_[44]\, + R => '0' + ); +\skid_buffer_reg[45]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(45), + Q => \skid_buffer_reg_n_0_[45]\, + R => '0' + ); +\skid_buffer_reg[46]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(46), + Q => \skid_buffer_reg_n_0_[46]\, + R => '0' + ); +\skid_buffer_reg[47]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(47), + Q => \skid_buffer_reg_n_0_[47]\, + R => '0' + ); +\skid_buffer_reg[48]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(48), + Q => \skid_buffer_reg_n_0_[48]\, + R => '0' + ); +\skid_buffer_reg[49]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(49), + Q => \skid_buffer_reg_n_0_[49]\, + R => '0' + ); +\skid_buffer_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(4), + Q => \skid_buffer_reg_n_0_[4]\, + R => '0' + ); +\skid_buffer_reg[50]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(50), + Q => \skid_buffer_reg_n_0_[50]\, + R => '0' + ); +\skid_buffer_reg[51]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(51), + Q => \skid_buffer_reg_n_0_[51]\, + R => '0' + ); +\skid_buffer_reg[52]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(52), + Q => \skid_buffer_reg_n_0_[52]\, + R => '0' + ); +\skid_buffer_reg[53]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(53), + Q => \skid_buffer_reg_n_0_[53]\, + R => '0' + ); +\skid_buffer_reg[54]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(54), + Q => \skid_buffer_reg_n_0_[54]\, + R => '0' + ); +\skid_buffer_reg[55]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(55), + Q => \skid_buffer_reg_n_0_[55]\, + R => '0' + ); +\skid_buffer_reg[56]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(56), + Q => \skid_buffer_reg_n_0_[56]\, + R => '0' + ); +\skid_buffer_reg[57]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(57), + Q => \skid_buffer_reg_n_0_[57]\, + R => '0' + ); +\skid_buffer_reg[58]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(58), + Q => \skid_buffer_reg_n_0_[58]\, + R => '0' + ); +\skid_buffer_reg[59]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(59), + Q => \skid_buffer_reg_n_0_[59]\, + R => '0' + ); +\skid_buffer_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(5), + Q => \skid_buffer_reg_n_0_[5]\, + R => '0' + ); +\skid_buffer_reg[60]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(60), + Q => \skid_buffer_reg_n_0_[60]\, + R => '0' + ); +\skid_buffer_reg[61]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(61), + Q => \skid_buffer_reg_n_0_[61]\, + R => '0' + ); +\skid_buffer_reg[62]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(62), + Q => \skid_buffer_reg_n_0_[62]\, + R => '0' + ); +\skid_buffer_reg[63]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(63), + Q => \skid_buffer_reg_n_0_[63]\, + R => '0' + ); +\skid_buffer_reg[64]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rresp(0), + Q => \skid_buffer_reg_n_0_[64]\, + R => '0' + ); +\skid_buffer_reg[65]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rresp(1), + Q => \skid_buffer_reg_n_0_[65]\, + R => '0' + ); +\skid_buffer_reg[66]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rlast(0), + Q => \skid_buffer_reg_n_0_[66]\, + R => '0' + ); +\skid_buffer_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(6), + Q => \skid_buffer_reg_n_0_[6]\, + R => '0' + ); +\skid_buffer_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(7), + Q => \skid_buffer_reg_n_0_[7]\, + R => '0' + ); +\skid_buffer_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(8), + Q => \skid_buffer_reg_n_0_[8]\, + R => '0' + ); +\skid_buffer_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_axi_rready[0]\, + D => m_axi_rdata(9), + Q => \skid_buffer_reg_n_0_[9]\, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_axic_reg_srl_fifo is + port ( + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + \storage_data1_reg[0]_0\ : out STD_LOGIC; + s_ready_i_reg_0 : out STD_LOGIC; + m_select_enc : out STD_LOGIC; + s_ready_i_reg_1 : out STD_LOGIC; + \gen_rep[0].fifoaddr_reg[0]_0\ : out STD_LOGIC; + aclk : in STD_LOGIC; + aresetn_d_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_valid_i_reg_0 : in STD_LOGIC; + \storage_data1_reg[0]_1\ : in STD_LOGIC; + s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_select_enc_0 : in STD_LOGIC; + m_avalid_1 : in STD_LOGIC; + p_10_in : in STD_LOGIC; + \m_ready_d_reg[1]\ : in STD_LOGIC + ); +end Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_axic_reg_srl_fifo; + +architecture STRUCTURE of Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_axic_reg_srl_fifo is + signal \FSM_onehot_state[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_state[1]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_state[2]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_state[2]_i_3_n_0\ : STD_LOGIC; + signal \FSM_onehot_state[3]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_state[3]_i_3_n_0\ : STD_LOGIC; + signal \FSM_onehot_state[3]_i_4_n_0\ : STD_LOGIC; + signal \FSM_onehot_state[3]_i_5_n_0\ : STD_LOGIC; + signal \FSM_onehot_state_reg_n_0_[2]\ : STD_LOGIC; + attribute RTL_KEEP : string; + attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[2]\ : signal is "yes"; + signal \FSM_onehot_state_reg_n_0_[3]\ : STD_LOGIC; + attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[3]\ : signal is "yes"; + signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal fifoaddr : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \gen_rep[0].fifoaddr[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_rep[0].fifoaddr[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_srls[0].gen_rep[0].srl_nx1_n_1\ : STD_LOGIC; + signal \m_aready__1\ : STD_LOGIC; + signal \^m_select_enc\ : STD_LOGIC; + signal m_valid_i : STD_LOGIC; + signal m_valid_i_i_1_n_0 : STD_LOGIC; + signal m_valid_i_i_2_n_0 : STD_LOGIC; + signal p_0_in8_in : STD_LOGIC; + attribute RTL_KEEP of p_0_in8_in : signal is "yes"; + signal p_9_in : STD_LOGIC; + attribute RTL_KEEP of p_9_in : signal is "yes"; + signal push : STD_LOGIC; + signal s_ready_i_i_1_n_0 : STD_LOGIC; + signal \^s_ready_i_reg_0\ : STD_LOGIC; + signal \^s_ready_i_reg_1\ : STD_LOGIC; + signal \^storage_data1_reg[0]_0\ : STD_LOGIC; + attribute KEEP : string; + attribute KEEP of \FSM_onehot_state_reg[0]\ : label is "yes"; + attribute KEEP of \FSM_onehot_state_reg[1]\ : label is "yes"; + attribute KEEP of \FSM_onehot_state_reg[2]\ : label is "yes"; + attribute KEEP of \FSM_onehot_state_reg[3]\ : label is "yes"; + attribute syn_keep : string; + attribute syn_keep of \gen_rep[0].fifoaddr_reg[0]\ : label is "1"; + attribute syn_keep of \gen_rep[0].fifoaddr_reg[1]\ : label is "1"; +begin + SR(0) <= \^sr\(0); + m_select_enc <= \^m_select_enc\; + s_ready_i_reg_0 <= \^s_ready_i_reg_0\; + s_ready_i_reg_1 <= \^s_ready_i_reg_1\; + \storage_data1_reg[0]_0\ <= \^storage_data1_reg[0]_0\; +\FSM_onehot_state[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"51000000" + ) + port map ( + I0 => p_9_in, + I1 => s_axi_awvalid(0), + I2 => m_ready_d(0), + I3 => \m_aready__1\, + I4 => p_0_in8_in, + O => \FSM_onehot_state[0]_i_1_n_0\ + ); +\FSM_onehot_state[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4444444444444744" + ) + port map ( + I0 => \m_ready_d_reg[1]\, + I1 => p_9_in, + I2 => push, + I3 => \FSM_onehot_state[3]_i_5_n_0\, + I4 => \FSM_onehot_state[2]_i_3_n_0\, + I5 => p_0_in8_in, + O => \FSM_onehot_state[1]_i_1_n_0\ + ); +\FSM_onehot_state[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888888BBBBB8BB" + ) + port map ( + I0 => \m_ready_d_reg[1]\, + I1 => p_9_in, + I2 => push, + I3 => \FSM_onehot_state[3]_i_5_n_0\, + I4 => \FSM_onehot_state[2]_i_3_n_0\, + I5 => p_0_in8_in, + O => \FSM_onehot_state[2]_i_1_n_0\ + ); +\FSM_onehot_state[2]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"57FFFFFFFFFFFFFF" + ) + port map ( + I0 => \FSM_onehot_state_reg_n_0_[3]\, + I1 => m_valid_i_reg_0, + I2 => \storage_data1_reg[0]_1\, + I3 => s_axi_wvalid(0), + I4 => \^storage_data1_reg[0]_0\, + I5 => s_axi_wlast(0), + O => \FSM_onehot_state[2]_i_3_n_0\ + ); +\FSM_onehot_state[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EFEEEEEEEEEEEEEE" + ) + port map ( + I0 => \FSM_onehot_state[3]_i_3_n_0\, + I1 => \FSM_onehot_state[3]_i_4_n_0\, + I2 => push, + I3 => \FSM_onehot_state[3]_i_5_n_0\, + I4 => \m_aready__1\, + I5 => \FSM_onehot_state_reg_n_0_[3]\, + O => m_valid_i + ); +\FSM_onehot_state[3]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000008AA" + ) + port map ( + I0 => p_0_in8_in, + I1 => s_axi_awvalid(0), + I2 => m_ready_d(0), + I3 => \m_aready__1\, + I4 => p_9_in, + O => \FSM_onehot_state[3]_i_2_n_0\ + ); +\FSM_onehot_state[3]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"808080002A2A2AAA" + ) + port map ( + I0 => p_0_in8_in, + I1 => s_axi_wlast(0), + I2 => \^s_ready_i_reg_1\, + I3 => \storage_data1_reg[0]_1\, + I4 => m_valid_i_reg_0, + I5 => \m_ready_d_reg[1]\, + O => \FSM_onehot_state[3]_i_3_n_0\ + ); +\FSM_onehot_state[3]_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => p_9_in, + I1 => s_axi_awvalid(0), + I2 => m_ready_d(0), + O => \FSM_onehot_state[3]_i_4_n_0\ + ); +\FSM_onehot_state[3]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => fifoaddr(0), + I1 => fifoaddr(1), + O => \FSM_onehot_state[3]_i_5_n_0\ + ); +\FSM_onehot_state[3]_i_6\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80808000" + ) + port map ( + I0 => s_axi_wlast(0), + I1 => \^storage_data1_reg[0]_0\, + I2 => s_axi_wvalid(0), + I3 => \storage_data1_reg[0]_1\, + I4 => m_valid_i_reg_0, + O => \m_aready__1\ + ); +\FSM_onehot_state_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => aclk, + CE => m_valid_i, + D => \FSM_onehot_state[0]_i_1_n_0\, + Q => p_9_in, + S => \^sr\(0) + ); +\FSM_onehot_state_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => m_valid_i, + D => \FSM_onehot_state[1]_i_1_n_0\, + Q => p_0_in8_in, + R => \^sr\(0) + ); +\FSM_onehot_state_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => m_valid_i, + D => \FSM_onehot_state[2]_i_1_n_0\, + Q => \FSM_onehot_state_reg_n_0_[2]\, + R => \^sr\(0) + ); +\FSM_onehot_state_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => m_valid_i, + D => \FSM_onehot_state[3]_i_2_n_0\, + Q => \FSM_onehot_state_reg_n_0_[3]\, + R => \^sr\(0) + ); +areset_d1_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => aresetn_d_reg(0), + Q => \^sr\(0), + R => '0' + ); +\gen_rep[0].fifoaddr[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5AFB51FBA504AE04" + ) + port map ( + I0 => \m_aready__1\, + I1 => p_0_in8_in, + I2 => \m_ready_d_reg[1]\, + I3 => \FSM_onehot_state_reg_n_0_[3]\, + I4 => \^s_ready_i_reg_0\, + I5 => fifoaddr(0), + O => \gen_rep[0].fifoaddr[0]_i_1_n_0\ + ); +\gen_rep[0].fifoaddr[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D5BF2A40" + ) + port map ( + I0 => fifoaddr(0), + I1 => \m_aready__1\, + I2 => \FSM_onehot_state_reg_n_0_[3]\, + I3 => push, + I4 => fifoaddr(1), + O => \gen_rep[0].fifoaddr[1]_i_1_n_0\ + ); +\gen_rep[0].fifoaddr_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => aclk, + CE => '1', + D => \gen_rep[0].fifoaddr[0]_i_1_n_0\, + Q => fifoaddr(0), + S => aresetn_d_reg(0) + ); +\gen_rep[0].fifoaddr_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => aclk, + CE => '1', + D => \gen_rep[0].fifoaddr[1]_i_1_n_0\, + Q => fifoaddr(1), + S => aresetn_d_reg(0) + ); +\gen_srls[0].gen_rep[0].srl_nx1\: entity work.Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_ndeep_srl + port map ( + \FSM_onehot_state_reg[0]\ => \FSM_onehot_state[3]_i_4_n_0\, + aclk => aclk, + fifoaddr(1 downto 0) => fifoaddr(1 downto 0), + \m_aready__1\ => \m_aready__1\, + m_ready_d(0) => m_ready_d(0), + m_select_enc => \^m_select_enc\, + m_valid_i_reg => m_valid_i_reg_0, + m_valid_i_reg_0 => \^storage_data1_reg[0]_0\, + out0(1) => p_0_in8_in, + out0(0) => \FSM_onehot_state_reg_n_0_[3]\, + push => push, + s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0), + s_axi_awvalid(0) => s_axi_awvalid(0), + s_axi_wlast(0) => s_axi_wlast(0), + s_axi_wvalid(0) => s_axi_wvalid(0), + s_ready_i_reg => \^s_ready_i_reg_1\, + s_ready_i_reg_0 => \^s_ready_i_reg_0\, + \storage_data1_reg[0]\ => \gen_srls[0].gen_rep[0].srl_nx1_n_1\, + \storage_data1_reg[0]_0\ => \storage_data1_reg[0]_1\ + ); +m_valid_i_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"EFEEEEEEEEEEEEEE" + ) + port map ( + I0 => m_valid_i_i_2_n_0, + I1 => \FSM_onehot_state[3]_i_4_n_0\, + I2 => push, + I3 => \FSM_onehot_state[3]_i_5_n_0\, + I4 => \m_aready__1\, + I5 => \FSM_onehot_state_reg_n_0_[3]\, + O => m_valid_i_i_1_n_0 + ); +m_valid_i_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000002A2A2AAA" + ) + port map ( + I0 => p_0_in8_in, + I1 => s_axi_wlast(0), + I2 => \^s_ready_i_reg_1\, + I3 => \storage_data1_reg[0]_1\, + I4 => m_valid_i_reg_0, + I5 => \m_ready_d_reg[1]\, + O => m_valid_i_i_2_n_0 + ); +\m_valid_i_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFFFFFFFFFFFFFF" + ) + port map ( + I0 => \^s_ready_i_reg_1\, + I1 => \^m_select_enc\, + I2 => s_axi_wlast(0), + I3 => m_select_enc_0, + I4 => m_avalid_1, + I5 => p_10_in, + O => \gen_rep[0].fifoaddr_reg[0]_0\ + ); +m_valid_i_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => m_valid_i, + D => m_valid_i_i_1_n_0, + Q => \^storage_data1_reg[0]_0\, + R => \^sr\(0) + ); +s_ready_i_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFDFFFDDDDDDDD" + ) + port map ( + I0 => \FSM_onehot_state[2]_i_3_n_0\, + I1 => \^sr\(0), + I2 => push, + I3 => fifoaddr(1), + I4 => fifoaddr(0), + I5 => \^s_ready_i_reg_0\, + O => s_ready_i_i_1_n_0 + ); +s_ready_i_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => s_ready_i_i_1_n_0, + Q => \^s_ready_i_reg_0\, + R => aresetn_d_reg(0) + ); +\storage_data1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \gen_srls[0].gen_rep[0].srl_nx1_n_1\, + Q => \^m_select_enc\, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized0\ is + port ( + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \storage_data1_reg[0]_0\ : out STD_LOGIC; + m_valid_i_reg_0 : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_ready_i_reg : out STD_LOGIC; + m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 ); + aa_wm_awgrant_enc : in STD_LOGIC; + aclk : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \gen_arbiter.m_valid_i_reg\ : in STD_LOGIC; + in1 : in STD_LOGIC; + m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + aa_sa_awvalid : in STD_LOGIC; + \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\ : in STD_LOGIC; + \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\ : in STD_LOGIC; + m_select_enc : in STD_LOGIC; + m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_avalid : in STD_LOGIC; + m_valid_i_reg_1 : in STD_LOGIC; + s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized0\ : entity is "axi_data_fifo_v2_1_10_axic_reg_srl_fifo"; +end \Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized0\ is + signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal fifoaddr : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \gen_rep[0].fifoaddr[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_rep[0].fifoaddr[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_rep[0].fifoaddr[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_srls[0].gen_rep[0].srl_nx1_n_1\ : STD_LOGIC; + signal m_avalid_0 : STD_LOGIC; + signal m_select_enc_1 : STD_LOGIC; + signal m_valid_i_n_0 : STD_LOGIC; + signal \^m_valid_i_reg_0\ : STD_LOGIC; + signal push : STD_LOGIC; + signal \^storage_data1_reg[0]_0\ : STD_LOGIC; + attribute syn_keep : string; + attribute syn_keep of \gen_rep[0].fifoaddr_reg[0]\ : label is "1"; + attribute syn_keep of \gen_rep[0].fifoaddr_reg[1]\ : label is "1"; + attribute syn_keep of \gen_rep[0].fifoaddr_reg[2]\ : label is "1"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \m_axi_wdata[0]_INST_0\ : label is "soft_lutpair84"; + attribute SOFT_HLUTNM of \m_axi_wdata[10]_INST_0\ : label is "soft_lutpair79"; + attribute SOFT_HLUTNM of \m_axi_wdata[11]_INST_0\ : label is "soft_lutpair78"; + attribute SOFT_HLUTNM of \m_axi_wdata[12]_INST_0\ : label is "soft_lutpair78"; + attribute SOFT_HLUTNM of \m_axi_wdata[13]_INST_0\ : label is "soft_lutpair77"; + attribute SOFT_HLUTNM of \m_axi_wdata[14]_INST_0\ : label is "soft_lutpair77"; + attribute SOFT_HLUTNM of \m_axi_wdata[15]_INST_0\ : label is "soft_lutpair76"; + attribute SOFT_HLUTNM of \m_axi_wdata[16]_INST_0\ : label is "soft_lutpair76"; + attribute SOFT_HLUTNM of \m_axi_wdata[17]_INST_0\ : label is "soft_lutpair75"; + attribute SOFT_HLUTNM of \m_axi_wdata[18]_INST_0\ : label is "soft_lutpair75"; + attribute SOFT_HLUTNM of \m_axi_wdata[19]_INST_0\ : label is "soft_lutpair74"; + attribute SOFT_HLUTNM of \m_axi_wdata[1]_INST_0\ : label is "soft_lutpair83"; + attribute SOFT_HLUTNM of \m_axi_wdata[20]_INST_0\ : label is "soft_lutpair74"; + attribute SOFT_HLUTNM of \m_axi_wdata[21]_INST_0\ : label is "soft_lutpair73"; + attribute SOFT_HLUTNM of \m_axi_wdata[22]_INST_0\ : label is "soft_lutpair73"; + attribute SOFT_HLUTNM of \m_axi_wdata[23]_INST_0\ : label is "soft_lutpair72"; + attribute SOFT_HLUTNM of \m_axi_wdata[24]_INST_0\ : label is "soft_lutpair72"; + attribute SOFT_HLUTNM of \m_axi_wdata[25]_INST_0\ : label is "soft_lutpair71"; + attribute SOFT_HLUTNM of \m_axi_wdata[26]_INST_0\ : label is "soft_lutpair71"; + attribute SOFT_HLUTNM of \m_axi_wdata[27]_INST_0\ : label is "soft_lutpair70"; + attribute SOFT_HLUTNM of \m_axi_wdata[28]_INST_0\ : label is "soft_lutpair70"; + attribute SOFT_HLUTNM of \m_axi_wdata[29]_INST_0\ : label is "soft_lutpair69"; + attribute SOFT_HLUTNM of \m_axi_wdata[2]_INST_0\ : label is "soft_lutpair83"; + attribute SOFT_HLUTNM of \m_axi_wdata[30]_INST_0\ : label is "soft_lutpair69"; + attribute SOFT_HLUTNM of \m_axi_wdata[31]_INST_0\ : label is "soft_lutpair68"; + attribute SOFT_HLUTNM of \m_axi_wdata[32]_INST_0\ : label is "soft_lutpair68"; + attribute SOFT_HLUTNM of \m_axi_wdata[33]_INST_0\ : label is "soft_lutpair67"; + attribute SOFT_HLUTNM of \m_axi_wdata[34]_INST_0\ : label is "soft_lutpair67"; + attribute SOFT_HLUTNM of \m_axi_wdata[35]_INST_0\ : label is "soft_lutpair66"; + attribute SOFT_HLUTNM of \m_axi_wdata[36]_INST_0\ : label is "soft_lutpair66"; + attribute SOFT_HLUTNM of \m_axi_wdata[37]_INST_0\ : label is "soft_lutpair65"; + attribute SOFT_HLUTNM of \m_axi_wdata[38]_INST_0\ : label is "soft_lutpair65"; + attribute SOFT_HLUTNM of \m_axi_wdata[39]_INST_0\ : label is "soft_lutpair64"; + attribute SOFT_HLUTNM of \m_axi_wdata[3]_INST_0\ : label is "soft_lutpair82"; + attribute SOFT_HLUTNM of \m_axi_wdata[40]_INST_0\ : label is "soft_lutpair64"; + attribute SOFT_HLUTNM of \m_axi_wdata[41]_INST_0\ : label is "soft_lutpair63"; + attribute SOFT_HLUTNM of \m_axi_wdata[42]_INST_0\ : label is "soft_lutpair63"; + attribute SOFT_HLUTNM of \m_axi_wdata[43]_INST_0\ : label is "soft_lutpair62"; + attribute SOFT_HLUTNM of \m_axi_wdata[44]_INST_0\ : label is "soft_lutpair62"; + attribute SOFT_HLUTNM of \m_axi_wdata[45]_INST_0\ : label is "soft_lutpair61"; + attribute SOFT_HLUTNM of \m_axi_wdata[46]_INST_0\ : label is "soft_lutpair61"; + attribute SOFT_HLUTNM of \m_axi_wdata[47]_INST_0\ : label is "soft_lutpair60"; + attribute SOFT_HLUTNM of \m_axi_wdata[48]_INST_0\ : label is "soft_lutpair60"; + attribute SOFT_HLUTNM of \m_axi_wdata[49]_INST_0\ : label is "soft_lutpair59"; + attribute SOFT_HLUTNM of \m_axi_wdata[4]_INST_0\ : label is "soft_lutpair82"; + attribute SOFT_HLUTNM of \m_axi_wdata[50]_INST_0\ : label is "soft_lutpair59"; + attribute SOFT_HLUTNM of \m_axi_wdata[51]_INST_0\ : label is "soft_lutpair58"; + attribute SOFT_HLUTNM of \m_axi_wdata[52]_INST_0\ : label is "soft_lutpair58"; + attribute SOFT_HLUTNM of \m_axi_wdata[53]_INST_0\ : label is "soft_lutpair57"; + attribute SOFT_HLUTNM of \m_axi_wdata[54]_INST_0\ : label is "soft_lutpair57"; + attribute SOFT_HLUTNM of \m_axi_wdata[55]_INST_0\ : label is "soft_lutpair56"; + attribute SOFT_HLUTNM of \m_axi_wdata[56]_INST_0\ : label is "soft_lutpair56"; + attribute SOFT_HLUTNM of \m_axi_wdata[57]_INST_0\ : label is "soft_lutpair55"; + attribute SOFT_HLUTNM of \m_axi_wdata[58]_INST_0\ : label is "soft_lutpair55"; + attribute SOFT_HLUTNM of \m_axi_wdata[59]_INST_0\ : label is "soft_lutpair54"; + attribute SOFT_HLUTNM of \m_axi_wdata[5]_INST_0\ : label is "soft_lutpair81"; + attribute SOFT_HLUTNM of \m_axi_wdata[60]_INST_0\ : label is "soft_lutpair54"; + attribute SOFT_HLUTNM of \m_axi_wdata[61]_INST_0\ : label is "soft_lutpair53"; + attribute SOFT_HLUTNM of \m_axi_wdata[62]_INST_0\ : label is "soft_lutpair53"; + attribute SOFT_HLUTNM of \m_axi_wdata[63]_INST_0\ : label is "soft_lutpair52"; + attribute SOFT_HLUTNM of \m_axi_wdata[6]_INST_0\ : label is "soft_lutpair81"; + attribute SOFT_HLUTNM of \m_axi_wdata[7]_INST_0\ : label is "soft_lutpair80"; + attribute SOFT_HLUTNM of \m_axi_wdata[8]_INST_0\ : label is "soft_lutpair80"; + attribute SOFT_HLUTNM of \m_axi_wdata[9]_INST_0\ : label is "soft_lutpair79"; + attribute SOFT_HLUTNM of \m_axi_wlast[0]_INST_0\ : label is "soft_lutpair84"; + attribute SOFT_HLUTNM of \m_axi_wstrb[0]_INST_0\ : label is "soft_lutpair52"; + attribute SOFT_HLUTNM of \m_axi_wstrb[1]_INST_0\ : label is "soft_lutpair51"; + attribute SOFT_HLUTNM of \m_axi_wstrb[2]_INST_0\ : label is "soft_lutpair51"; + attribute SOFT_HLUTNM of \m_axi_wstrb[3]_INST_0\ : label is "soft_lutpair50"; + attribute SOFT_HLUTNM of \m_axi_wstrb[4]_INST_0\ : label is "soft_lutpair50"; + attribute SOFT_HLUTNM of \m_axi_wstrb[5]_INST_0\ : label is "soft_lutpair49"; + attribute SOFT_HLUTNM of \m_axi_wstrb[6]_INST_0\ : label is "soft_lutpair49"; + attribute SOFT_HLUTNM of \m_axi_wstrb[7]_INST_0\ : label is "soft_lutpair48"; + attribute SOFT_HLUTNM of \s_axi_wready[1]_INST_0_i_1\ : label is "soft_lutpair48"; +begin + E(0) <= \^e\(0); + m_valid_i_reg_0 <= \^m_valid_i_reg_0\; + \storage_data1_reg[0]_0\ <= \^storage_data1_reg[0]_0\; +\FSM_onehot_state[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4555000000000000" + ) + port map ( + I0 => \out\(0), + I1 => m_ready_d(0), + I2 => Q(0), + I3 => aa_sa_awvalid, + I4 => \^storage_data1_reg[0]_0\, + I5 => \out\(1), + O => D(0) + ); +\FSM_onehot_state[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"E3E2E322E322E322" + ) + port map ( + I0 => \out\(0), + I1 => \gen_arbiter.m_valid_i_reg\, + I2 => \^storage_data1_reg[0]_0\, + I3 => \out\(1), + I4 => \out\(2), + I5 => \^m_valid_i_reg_0\, + O => \^e\(0) + ); +\FSM_onehot_state[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000002000AAAA" + ) + port map ( + I0 => \out\(1), + I1 => m_ready_d(0), + I2 => Q(0), + I3 => aa_sa_awvalid, + I4 => \^storage_data1_reg[0]_0\, + I5 => \out\(0), + O => D(1) + ); +\gen_rep[0].fifoaddr[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"5AFBA504" + ) + port map ( + I0 => \^storage_data1_reg[0]_0\, + I1 => \out\(1), + I2 => \gen_arbiter.m_valid_i_reg\, + I3 => \out\(2), + I4 => fifoaddr(0), + O => \gen_rep[0].fifoaddr[0]_i_1_n_0\ + ); +\gen_rep[0].fifoaddr[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BFBFF5F740400A08" + ) + port map ( + I0 => fifoaddr(0), + I1 => \out\(2), + I2 => \gen_arbiter.m_valid_i_reg\, + I3 => \out\(1), + I4 => \^storage_data1_reg[0]_0\, + I5 => fifoaddr(1), + O => \gen_rep[0].fifoaddr[1]_i_1_n_0\ + ); +\gen_rep[0].fifoaddr[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F777EFFF08881000" + ) + port map ( + I0 => fifoaddr(1), + I1 => fifoaddr(0), + I2 => \^storage_data1_reg[0]_0\, + I3 => \out\(2), + I4 => push, + I5 => fifoaddr(2), + O => \gen_rep[0].fifoaddr[2]_i_1_n_0\ + ); +\gen_rep[0].fifoaddr_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => aclk, + CE => '1', + D => \gen_rep[0].fifoaddr[0]_i_1_n_0\, + Q => fifoaddr(0), + S => SR(0) + ); +\gen_rep[0].fifoaddr_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => aclk, + CE => '1', + D => \gen_rep[0].fifoaddr[1]_i_1_n_0\, + Q => fifoaddr(1), + S => SR(0) + ); +\gen_rep[0].fifoaddr_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => aclk, + CE => '1', + D => \gen_rep[0].fifoaddr[2]_i_1_n_0\, + Q => fifoaddr(2), + S => SR(0) + ); +\gen_srls[0].gen_rep[0].srl_nx1\: entity work.\Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_ndeep_srl__parameterized8\ + port map ( + A(2 downto 0) => fifoaddr(2 downto 0), + aa_wm_awgrant_enc => aa_wm_awgrant_enc, + aclk => aclk, + \gen_arbiter.m_valid_i_reg\ => \gen_arbiter.m_valid_i_reg\, + \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\ => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\, + \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\ => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\, + m_avalid_0 => m_avalid_0, + m_axi_wready(0) => m_axi_wready(0), + m_select_enc => m_select_enc, + m_select_enc_1 => m_select_enc_1, + m_valid_i_reg => m_valid_i_reg_1, + \out\(1 downto 0) => \out\(2 downto 1), + push => push, + s_axi_wlast(0) => s_axi_wlast(0), + \storage_data1_reg[0]\ => \gen_srls[0].gen_rep[0].srl_nx1_n_1\, + \storage_data1_reg[0]_0\ => \^storage_data1_reg[0]_0\ + ); +\m_axi_wdata[0]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(0), + O => m_axi_wdata(0) + ); +\m_axi_wdata[10]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(10), + O => m_axi_wdata(10) + ); +\m_axi_wdata[11]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(11), + O => m_axi_wdata(11) + ); +\m_axi_wdata[12]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(12), + O => m_axi_wdata(12) + ); +\m_axi_wdata[13]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(13), + O => m_axi_wdata(13) + ); +\m_axi_wdata[14]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(14), + O => m_axi_wdata(14) + ); +\m_axi_wdata[15]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(15), + O => m_axi_wdata(15) + ); +\m_axi_wdata[16]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(16), + O => m_axi_wdata(16) + ); +\m_axi_wdata[17]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(17), + O => m_axi_wdata(17) + ); +\m_axi_wdata[18]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(18), + O => m_axi_wdata(18) + ); +\m_axi_wdata[19]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(19), + O => m_axi_wdata(19) + ); +\m_axi_wdata[1]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(1), + O => m_axi_wdata(1) + ); +\m_axi_wdata[20]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(20), + O => m_axi_wdata(20) + ); +\m_axi_wdata[21]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(21), + O => m_axi_wdata(21) + ); +\m_axi_wdata[22]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(22), + O => m_axi_wdata(22) + ); +\m_axi_wdata[23]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(23), + O => m_axi_wdata(23) + ); +\m_axi_wdata[24]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(24), + O => m_axi_wdata(24) + ); +\m_axi_wdata[25]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(25), + O => m_axi_wdata(25) + ); +\m_axi_wdata[26]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(26), + O => m_axi_wdata(26) + ); +\m_axi_wdata[27]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(27), + O => m_axi_wdata(27) + ); +\m_axi_wdata[28]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(28), + O => m_axi_wdata(28) + ); +\m_axi_wdata[29]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(29), + O => m_axi_wdata(29) + ); +\m_axi_wdata[2]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(2), + O => m_axi_wdata(2) + ); +\m_axi_wdata[30]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(30), + O => m_axi_wdata(30) + ); +\m_axi_wdata[31]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(31), + O => m_axi_wdata(31) + ); +\m_axi_wdata[32]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(32), + O => m_axi_wdata(32) + ); +\m_axi_wdata[33]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(33), + O => m_axi_wdata(33) + ); +\m_axi_wdata[34]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(34), + O => m_axi_wdata(34) + ); +\m_axi_wdata[35]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(35), + O => m_axi_wdata(35) + ); +\m_axi_wdata[36]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(36), + O => m_axi_wdata(36) + ); +\m_axi_wdata[37]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(37), + O => m_axi_wdata(37) + ); +\m_axi_wdata[38]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(38), + O => m_axi_wdata(38) + ); +\m_axi_wdata[39]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(39), + O => m_axi_wdata(39) + ); +\m_axi_wdata[3]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(3), + O => m_axi_wdata(3) + ); +\m_axi_wdata[40]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(40), + O => m_axi_wdata(40) + ); +\m_axi_wdata[41]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(41), + O => m_axi_wdata(41) + ); +\m_axi_wdata[42]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(42), + O => m_axi_wdata(42) + ); +\m_axi_wdata[43]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(43), + O => m_axi_wdata(43) + ); +\m_axi_wdata[44]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(44), + O => m_axi_wdata(44) + ); +\m_axi_wdata[45]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(45), + O => m_axi_wdata(45) + ); +\m_axi_wdata[46]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(46), + O => m_axi_wdata(46) + ); +\m_axi_wdata[47]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(47), + O => m_axi_wdata(47) + ); +\m_axi_wdata[48]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(48), + O => m_axi_wdata(48) + ); +\m_axi_wdata[49]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(49), + O => m_axi_wdata(49) + ); +\m_axi_wdata[4]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(4), + O => m_axi_wdata(4) + ); +\m_axi_wdata[50]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(50), + O => m_axi_wdata(50) + ); +\m_axi_wdata[51]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(51), + O => m_axi_wdata(51) + ); +\m_axi_wdata[52]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(52), + O => m_axi_wdata(52) + ); +\m_axi_wdata[53]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(53), + O => m_axi_wdata(53) + ); +\m_axi_wdata[54]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(54), + O => m_axi_wdata(54) + ); +\m_axi_wdata[55]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(55), + O => m_axi_wdata(55) + ); +\m_axi_wdata[56]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(56), + O => m_axi_wdata(56) + ); +\m_axi_wdata[57]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(57), + O => m_axi_wdata(57) + ); +\m_axi_wdata[58]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(58), + O => m_axi_wdata(58) + ); +\m_axi_wdata[59]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(59), + O => m_axi_wdata(59) + ); +\m_axi_wdata[5]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(5), + O => m_axi_wdata(5) + ); +\m_axi_wdata[60]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(60), + O => m_axi_wdata(60) + ); +\m_axi_wdata[61]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(61), + O => m_axi_wdata(61) + ); +\m_axi_wdata[62]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(62), + O => m_axi_wdata(62) + ); +\m_axi_wdata[63]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(63), + O => m_axi_wdata(63) + ); +\m_axi_wdata[6]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(6), + O => m_axi_wdata(6) + ); +\m_axi_wdata[7]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(7), + O => m_axi_wdata(7) + ); +\m_axi_wdata[8]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(8), + O => m_axi_wdata(8) + ); +\m_axi_wdata[9]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wdata(9), + O => m_axi_wdata(9) + ); +\m_axi_wlast[0]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => s_axi_wlast(0), + I1 => m_select_enc_1, + O => m_axi_wlast(0) + ); +\m_axi_wstrb[0]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wstrb(0), + O => m_axi_wstrb(0) + ); +\m_axi_wstrb[1]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wstrb(1), + O => m_axi_wstrb(1) + ); +\m_axi_wstrb[2]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wstrb(2), + O => m_axi_wstrb(2) + ); +\m_axi_wstrb[3]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wstrb(3), + O => m_axi_wstrb(3) + ); +\m_axi_wstrb[4]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wstrb(4), + O => m_axi_wstrb(4) + ); +\m_axi_wstrb[5]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wstrb(5), + O => m_axi_wstrb(5) + ); +\m_axi_wstrb[6]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wstrb(6), + O => m_axi_wstrb(6) + ); +\m_axi_wstrb[7]_INST_0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => m_select_enc_1, + I1 => s_axi_wstrb(7), + O => m_axi_wstrb(7) + ); +\m_axi_wvalid[0]_INST_0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"08000000" + ) + port map ( + I0 => m_avalid_0, + I1 => m_select_enc_1, + I2 => m_select_enc, + I3 => s_axi_wvalid(0), + I4 => m_avalid, + O => m_axi_wvalid(0) + ); +m_valid_i: unisim.vcomponents.LUT6 + generic map( + INIT => X"E3E2232223222322" + ) + port map ( + I0 => \out\(0), + I1 => \gen_arbiter.m_valid_i_reg\, + I2 => \^storage_data1_reg[0]_0\, + I3 => \out\(1), + I4 => \out\(2), + I5 => \^m_valid_i_reg_0\, + O => m_valid_i_n_0 + ); +\m_valid_i_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2000000000000000" + ) + port map ( + I0 => m_select_enc_1, + I1 => m_select_enc, + I2 => m_valid_i_reg_1, + I3 => s_axi_wlast(0), + I4 => m_axi_wready(0), + I5 => m_avalid_0, + O => \^storage_data1_reg[0]_0\ + ); +m_valid_i_i_3: unisim.vcomponents.LUT3 + generic map( + INIT => X"01" + ) + port map ( + I0 => fifoaddr(1), + I1 => fifoaddr(0), + I2 => fifoaddr(2), + O => \^m_valid_i_reg_0\ + ); +m_valid_i_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^e\(0), + D => m_valid_i_n_0, + Q => m_avalid_0, + R => in1 + ); +\s_axi_wready[1]_INST_0_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4000" + ) + port map ( + I0 => m_select_enc, + I1 => m_axi_wready(0), + I2 => m_select_enc_1, + I3 => m_avalid_0, + O => s_ready_i_reg + ); +\storage_data1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \gen_srls[0].gen_rep[0].srl_nx1_n_1\, + Q => m_select_enc_1, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized1\ is + port ( + m_valid_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_axi.s_axi_wready_i_reg\ : out STD_LOGIC; + \storage_data1_reg[0]_0\ : out STD_LOGIC; + \gen_axi.s_axi_wready_i_reg_0\ : out STD_LOGIC; + s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_ready_i_reg : out STD_LOGIC; + \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + aa_wm_awgrant_enc : in STD_LOGIC; + aclk : in STD_LOGIC; + \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + sa_wm_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + \storage_data1_reg[0]_1\ : in STD_LOGIC; + in1 : in STD_LOGIC; + p_10_in : in STD_LOGIC; + \storage_data1_reg[0]_2\ : in STD_LOGIC; + m_select_enc_0 : in STD_LOGIC; + m_avalid_1 : in STD_LOGIC; + s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + aa_sa_awvalid : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized1\ : entity is "axi_data_fifo_v2_1_10_axic_reg_srl_fifo"; +end \Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized1\; + +architecture STRUCTURE of \Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized1\ is + signal fifoaddr : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^gen_axi.s_axi_wready_i_reg\ : STD_LOGIC; + signal \^gen_axi.s_axi_wready_i_reg_0\ : STD_LOGIC; + signal \gen_rep[0].fifoaddr[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_rep[0].fifoaddr[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_srls[0].gen_rep[0].srl_nx1_n_0\ : STD_LOGIC; + signal load_s1 : STD_LOGIC; + signal \m_valid_i_i_3__0_n_0\ : STD_LOGIC; + signal m_valid_i_n_0 : STD_LOGIC; + signal \^m_valid_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal p_0_in3_out : STD_LOGIC; + signal \^storage_data1_reg[0]_0\ : STD_LOGIC; + attribute syn_keep : string; + attribute syn_keep of \gen_rep[0].fifoaddr_reg[0]\ : label is "1"; + attribute syn_keep of \gen_rep[0].fifoaddr_reg[1]\ : label is "1"; +begin + \gen_axi.s_axi_wready_i_reg\ <= \^gen_axi.s_axi_wready_i_reg\; + \gen_axi.s_axi_wready_i_reg_0\ <= \^gen_axi.s_axi_wready_i_reg_0\; + m_valid_i_reg_0(0) <= \^m_valid_i_reg_0\(0); + \storage_data1_reg[0]_0\ <= \^storage_data1_reg[0]_0\; +\FSM_onehot_state[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1011111100000000" + ) + port map ( + I0 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(0), + I1 => \storage_data1_reg[0]_1\, + I2 => m_ready_d(0), + I3 => Q(0), + I4 => aa_sa_awvalid, + I5 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(1), + O => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(0) + ); +\FSM_onehot_state[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0800080008FF0800" + ) + port map ( + I0 => aa_sa_awvalid, + I1 => Q(0), + I2 => m_ready_d(0), + I3 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(0), + I4 => p_0_in3_out, + I5 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(1), + O => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(1) + ); +\FSM_onehot_state[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BF00BF00BF00BFFF" + ) + port map ( + I0 => m_ready_d(0), + I1 => Q(0), + I2 => aa_sa_awvalid, + I3 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(0), + I4 => p_0_in3_out, + I5 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(1), + O => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(2) + ); +\FSM_onehot_state[2]_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"08000000" + ) + port map ( + I0 => \m_valid_i_i_3__0_n_0\, + I1 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(2), + I2 => sa_wm_awvalid(0), + I3 => p_10_in, + I4 => \^gen_axi.s_axi_wready_i_reg_0\, + O => p_0_in3_out + ); +\FSM_onehot_state[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CB8BCB88CB88CB88" + ) + port map ( + I0 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(0), + I1 => sa_wm_awvalid(0), + I2 => \storage_data1_reg[0]_1\, + I3 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(1), + I4 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(2), + I5 => \m_valid_i_i_3__0_n_0\, + O => \^m_valid_i_reg_0\(0) + ); +\FSM_onehot_state[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000008A888888" + ) + port map ( + I0 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(1), + I1 => \storage_data1_reg[0]_1\, + I2 => m_ready_d(0), + I3 => Q(0), + I4 => aa_sa_awvalid, + I5 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(0), + O => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(3) + ); +\gen_axi.write_cs[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => \^gen_axi.s_axi_wready_i_reg\, + I1 => \^storage_data1_reg[0]_0\, + I2 => s_axi_wlast(0), + I3 => m_select_enc_0, + I4 => s_axi_wvalid(0), + I5 => m_avalid_1, + O => \^gen_axi.s_axi_wready_i_reg_0\ + ); +\gen_primitive_shifter.gen_srls[0].srl_inst_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => \^gen_axi.s_axi_wready_i_reg\, + I1 => m_select_enc_0, + I2 => \^storage_data1_reg[0]_0\, + I3 => p_10_in, + O => s_ready_i_reg + ); +\gen_rep[0].fifoaddr[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"5A7FA580" + ) + port map ( + I0 => \storage_data1_reg[0]_1\, + I1 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(1), + I2 => sa_wm_awvalid(0), + I3 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(2), + I4 => fifoaddr(0), + O => \gen_rep[0].fifoaddr[0]_i_1_n_0\ + ); +\gen_rep[0].fifoaddr[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5F7FFBFBA0800404" + ) + port map ( + I0 => fifoaddr(0), + I1 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(2), + I2 => sa_wm_awvalid(0), + I3 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(1), + I4 => \storage_data1_reg[0]_1\, + I5 => fifoaddr(1), + O => \gen_rep[0].fifoaddr[1]_i_1_n_0\ + ); +\gen_rep[0].fifoaddr_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => aclk, + CE => '1', + D => \gen_rep[0].fifoaddr[0]_i_1_n_0\, + Q => fifoaddr(0), + S => SR(0) + ); +\gen_rep[0].fifoaddr_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => aclk, + CE => '1', + D => \gen_rep[0].fifoaddr[1]_i_1_n_0\, + Q => fifoaddr(1), + S => SR(0) + ); +\gen_srls[0].gen_rep[0].srl_nx1\: entity work.Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_ndeep_srl_3 + port map ( + A(1 downto 0) => fifoaddr(1 downto 0), + aa_wm_awgrant_enc => aa_wm_awgrant_enc, + aclk => aclk, + \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(1 downto 0) => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(2 downto 1), + load_s1 => load_s1, + m_valid_i_reg => \^gen_axi.s_axi_wready_i_reg_0\, + p_10_in => p_10_in, + sa_wm_awvalid(0) => sa_wm_awvalid(0), + \storage_data1_reg[0]\ => \gen_srls[0].gen_rep[0].srl_nx1_n_0\, + \storage_data1_reg[0]_0\ => \^storage_data1_reg[0]_0\ + ); +m_valid_i: unisim.vcomponents.LUT6 + generic map( + INIT => X"CB8BC888C888C888" + ) + port map ( + I0 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(0), + I1 => sa_wm_awvalid(0), + I2 => \storage_data1_reg[0]_1\, + I3 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(1), + I4 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(2), + I5 => \m_valid_i_i_3__0_n_0\, + O => m_valid_i_n_0 + ); +\m_valid_i_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => fifoaddr(0), + I1 => fifoaddr(1), + O => \m_valid_i_i_3__0_n_0\ + ); +m_valid_i_reg: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => \^m_valid_i_reg_0\(0), + D => m_valid_i_n_0, + Q => \^gen_axi.s_axi_wready_i_reg\, + R => in1 + ); +\s_axi_wready[1]_INST_0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EAAAAAAA00000000" + ) + port map ( + I0 => \storage_data1_reg[0]_2\, + I1 => \^gen_axi.s_axi_wready_i_reg\, + I2 => m_select_enc_0, + I3 => \^storage_data1_reg[0]_0\, + I4 => p_10_in, + I5 => m_avalid_1, + O => s_axi_wready(0) + ); +\storage_data1[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FCCCA000ECCCA000" + ) + port map ( + I0 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(2), + I1 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(0), + I2 => \^gen_axi.s_axi_wready_i_reg_0\, + I3 => p_10_in, + I4 => sa_wm_awvalid(0), + I5 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(1), + O => load_s1 + ); +\storage_data1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \gen_srls[0].gen_rep[0].srl_nx1_n_0\, + Q => \^storage_data1_reg[0]_0\, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axi_register_slice is + port ( + p_58_out : out STD_LOGIC; + m_valid_i_reg : out STD_LOGIC; + m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 ); + p_1_in : out STD_LOGIC; + p_52_out : out STD_LOGIC; + \m_axi_rready[0]\ : out STD_LOGIC; + s_ready_i_reg : out STD_LOGIC; + p_61_out : out STD_LOGIC; + s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \gen_master_slots[0].w_issuing_cnt_reg[0]\ : out STD_LOGIC; + \gen_arbiter.qual_reg_reg[0]\ : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \gen_master_slots[0].r_issuing_cnt_reg[0]\ : out STD_LOGIC; + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + aclk : in STD_LOGIC; + aresetn : in STD_LOGIC; + s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); + active_target_hot : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + active_target_hot_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + active_target_enc : in STD_LOGIC; + p_30_out : in STD_LOGIC; + \gen_master_slots[0].r_issuing_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \gen_arbiter.m_valid_i_reg\ : in STD_LOGIC; + active_target_enc_1 : in STD_LOGIC; + m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); +end Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axi_register_slice; + +architecture STRUCTURE of Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axi_register_slice is + signal \^m_valid_i_reg\ : STD_LOGIC; + signal \^p_1_in\ : STD_LOGIC; +begin + m_valid_i_reg <= \^m_valid_i_reg\; + p_1_in <= \^p_1_in\; +b_pipe: entity work.\Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized1_4\ + port map ( + aclk => aclk, + active_target_enc_1 => active_target_enc_1, + active_target_hot(0) => active_target_hot(0), + aresetn => aresetn, + \gen_master_slots[0].w_issuing_cnt_reg[0]\ => \gen_master_slots[0].w_issuing_cnt_reg[0]\, + m_axi_bid(0) => m_axi_bid(0), + m_axi_bready(0) => m_axi_bready(0), + m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), + m_axi_bvalid(0) => m_axi_bvalid(0), + m_valid_i_reg_0 => \^m_valid_i_reg\, + p_1_in => \^p_1_in\, + s_axi_bready(0) => s_axi_bready(0), + s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0), + s_ready_i_reg_0 => p_58_out, + s_ready_i_reg_1 => s_ready_i_reg, + s_ready_i_reg_2 => p_61_out + ); +r_pipe: entity work.\Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2_5\ + port map ( + D(2 downto 0) => D(2 downto 0), + E(0) => E(0), + Q(2 downto 0) => Q(2 downto 0), + aclk => aclk, + active_target_enc => active_target_enc, + active_target_hot_0(0) => active_target_hot_0(0), + \aresetn_d_reg[1]\ => \^m_valid_i_reg\, + \gen_arbiter.m_valid_i_reg\ => \gen_arbiter.m_valid_i_reg\, + \gen_arbiter.qual_reg_reg[0]\ => \gen_arbiter.qual_reg_reg[0]\, + \gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].r_issuing_cnt_reg[0]\, + \gen_master_slots[0].r_issuing_cnt_reg[3]\(3 downto 0) => \gen_master_slots[0].r_issuing_cnt_reg[3]\(3 downto 0), + m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0), + m_axi_rlast(0) => m_axi_rlast(0), + \m_axi_rready[0]\ => \m_axi_rready[0]\, + m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0), + m_axi_rvalid(0) => m_axi_rvalid(0), + m_valid_i_reg_0 => p_52_out, + p_1_in => \^p_1_in\, + p_30_out => p_30_out, + s_axi_rdata(63 downto 0) => s_axi_rdata(63 downto 0), + s_axi_rready(0) => s_axi_rready(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axi_register_slice_1 is + port ( + mi_bready_1 : out STD_LOGIC; + p_28_out : out STD_LOGIC; + mi_rready_1 : out STD_LOGIC; + \gen_master_slots[1].w_issuing_cnt_reg[8]\ : out STD_LOGIC; + \gen_master_slots[1].r_issuing_cnt_reg[8]\ : out STD_LOGIC; + p_30_out : out STD_LOGIC; + \s_axi_bvalid[1]\ : out STD_LOGIC; + valid_qual_i111_in : out STD_LOGIC; + \gen_arbiter.qual_reg_reg[0]\ : out STD_LOGIC; + \valid_qual_i1__0\ : out STD_LOGIC; + \gen_arbiter.qual_reg_reg[0]_0\ : out STD_LOGIC; + s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \aresetn_d_reg[1]\ : in STD_LOGIC; + aclk : in STD_LOGIC; + p_1_in : in STD_LOGIC; + p_20_in : in STD_LOGIC; + s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); + active_target_enc : in STD_LOGIC; + \gen_axi.s_axi_awready_i_reg\ : in STD_LOGIC; + w_issuing_cnt : in STD_LOGIC_VECTOR ( 1 downto 0 ); + active_target_enc_0 : in STD_LOGIC; + s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_arbiter.m_valid_i_reg\ : in STD_LOGIC; + r_issuing_cnt : in STD_LOGIC_VECTOR ( 1 downto 0 ); + p_17_in : in STD_LOGIC; + \aresetn_d_reg[1]_0\ : in STD_LOGIC; + p_11_in : in STD_LOGIC; + p_61_out : in STD_LOGIC; + p_58_out : in STD_LOGIC; + active_target_hot : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_master_slots[0].w_issuing_cnt_reg[2]\ : in STD_LOGIC; + sel_4 : in STD_LOGIC; + \gen_single_thread.active_target_hot_reg[0]\ : in STD_LOGIC; + st_aa_arvalid_qual : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_master_slots[0].r_issuing_cnt_reg[2]\ : in STD_LOGIC; + \s_axi_araddr[29]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_valid_i_reg : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); + p_13_in : in STD_LOGIC; + p_1_in_1 : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axi_register_slice_1 : entity is "axi_register_slice_v2_1_11_axi_register_slice"; +end Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axi_register_slice_1; + +architecture STRUCTURE of Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axi_register_slice_1 is +begin +b_pipe: entity work.\Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized1\ + port map ( + aclk => aclk, + active_target_enc => active_target_enc, + active_target_hot(0) => active_target_hot(0), + \aresetn_d_reg[1]\ => \aresetn_d_reg[1]\, + \aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\, + \gen_axi.s_axi_awready_i_reg\ => \gen_axi.s_axi_awready_i_reg\, + \gen_master_slots[0].w_issuing_cnt_reg[2]\ => \gen_master_slots[0].w_issuing_cnt_reg[2]\, + \gen_master_slots[1].w_issuing_cnt_reg[8]\ => \gen_master_slots[1].w_issuing_cnt_reg[8]\, + \gen_single_thread.active_target_hot_reg[0]\ => \gen_single_thread.active_target_hot_reg[0]\, + mi_bready_1 => mi_bready_1, + p_17_in => p_17_in, + p_1_in => p_1_in, + p_20_in => p_20_in, + p_58_out => p_58_out, + p_61_out => p_61_out, + s_axi_bready(0) => s_axi_bready(0), + \s_axi_bvalid[1]\ => \s_axi_bvalid[1]\, + sel_4 => sel_4, + valid_qual_i111_in => valid_qual_i111_in, + w_issuing_cnt(1 downto 0) => w_issuing_cnt(1 downto 0) + ); +r_pipe: entity work.\Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ + port map ( + Q(2 downto 0) => Q(2 downto 0), + aclk => aclk, + active_target_enc_0 => active_target_enc_0, + \aresetn_d_reg[1]\ => \aresetn_d_reg[1]\, + \gen_arbiter.m_valid_i_reg\ => \gen_arbiter.m_valid_i_reg\, + \gen_arbiter.qual_reg_reg[0]\ => \gen_arbiter.qual_reg_reg[0]\, + \gen_arbiter.qual_reg_reg[0]_0\ => \gen_arbiter.qual_reg_reg[0]_0\, + \gen_master_slots[0].r_issuing_cnt_reg[2]\ => \gen_master_slots[0].r_issuing_cnt_reg[2]\, + \gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].r_issuing_cnt_reg[8]\, + \gen_master_slots[1].r_issuing_cnt_reg[8]_0\ => p_30_out, + m_valid_i_reg_0 => p_28_out, + m_valid_i_reg_1 => m_valid_i_reg, + p_11_in => p_11_in, + p_13_in => p_13_in, + p_1_in => p_1_in, + p_1_in_1 => p_1_in_1, + r_issuing_cnt(1 downto 0) => r_issuing_cnt(1 downto 0), + \s_axi_araddr[29]\(0) => \s_axi_araddr[29]\(0), + s_axi_arvalid(0) => s_axi_arvalid(0), + s_axi_rlast(0) => s_axi_rlast(0), + s_axi_rready(0) => s_axi_rready(0), + s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0), + \skid_buffer_reg[64]_0\ => mi_rready_1, + st_aa_arvalid_qual(0) => st_aa_arvalid_qual(0), + \valid_qual_i1__0\ => \valid_qual_i1__0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_wdata_mux is + port ( + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \storage_data1_reg[0]\ : out STD_LOGIC; + m_valid_i_reg : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_ready_i_reg : out STD_LOGIC; + m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 ); + aa_wm_awgrant_enc : in STD_LOGIC; + aclk : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \gen_arbiter.m_valid_i_reg\ : in STD_LOGIC; + in1 : in STD_LOGIC; + m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + aa_sa_awvalid : in STD_LOGIC; + \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\ : in STD_LOGIC; + \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\ : in STD_LOGIC; + m_select_enc : in STD_LOGIC; + m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_avalid : in STD_LOGIC; + m_valid_i_reg_0 : in STD_LOGIC; + s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); +end Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_wdata_mux; + +architecture STRUCTURE of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_wdata_mux is +begin +\gen_wmux.wmux_aw_fifo\: entity work.\Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized0\ + port map ( + D(1 downto 0) => D(1 downto 0), + E(0) => E(0), + Q(0) => Q(0), + SR(0) => SR(0), + aa_sa_awvalid => aa_sa_awvalid, + aa_wm_awgrant_enc => aa_wm_awgrant_enc, + aclk => aclk, + \gen_arbiter.m_valid_i_reg\ => \gen_arbiter.m_valid_i_reg\, + \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\ => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\, + \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\ => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\, + in1 => in1, + m_avalid => m_avalid, + m_axi_wdata(63 downto 0) => m_axi_wdata(63 downto 0), + m_axi_wlast(0) => m_axi_wlast(0), + m_axi_wready(0) => m_axi_wready(0), + m_axi_wstrb(7 downto 0) => m_axi_wstrb(7 downto 0), + m_axi_wvalid(0) => m_axi_wvalid(0), + m_ready_d(0) => m_ready_d(0), + m_select_enc => m_select_enc, + m_valid_i_reg_0 => m_valid_i_reg, + m_valid_i_reg_1 => m_valid_i_reg_0, + \out\(2 downto 0) => \out\(2 downto 0), + s_axi_wdata(63 downto 0) => s_axi_wdata(63 downto 0), + s_axi_wlast(0) => s_axi_wlast(0), + s_axi_wstrb(7 downto 0) => s_axi_wstrb(7 downto 0), + s_axi_wvalid(0) => s_axi_wvalid(0), + s_ready_i_reg => s_ready_i_reg, + \storage_data1_reg[0]_0\ => \storage_data1_reg[0]\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_wdata_mux__parameterized0\ is + port ( + m_valid_i_reg : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_avalid : out STD_LOGIC; + m_select_enc : out STD_LOGIC; + \write_cs0__0\ : out STD_LOGIC; + s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_ready_i_reg : out STD_LOGIC; + \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + aa_wm_awgrant_enc : in STD_LOGIC; + aclk : in STD_LOGIC; + \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + sa_wm_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + \storage_data1_reg[0]\ : in STD_LOGIC; + in1 : in STD_LOGIC; + p_10_in : in STD_LOGIC; + \storage_data1_reg[0]_0\ : in STD_LOGIC; + m_select_enc_0 : in STD_LOGIC; + m_avalid_1 : in STD_LOGIC; + s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 ); + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + aa_sa_awvalid : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_wdata_mux__parameterized0\ : entity is "axi_crossbar_v2_1_12_wdata_mux"; +end \Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_wdata_mux__parameterized0\; + +architecture STRUCTURE of \Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_wdata_mux__parameterized0\ is +begin +\gen_wmux.wmux_aw_fifo\: entity work.\Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized1\ + port map ( + Q(0) => Q(0), + SR(0) => SR(0), + aa_sa_awvalid => aa_sa_awvalid, + aa_wm_awgrant_enc => aa_wm_awgrant_enc, + aclk => aclk, + \gen_axi.s_axi_wready_i_reg\ => m_avalid, + \gen_axi.s_axi_wready_i_reg_0\ => \write_cs0__0\, + \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(3 downto 0) => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(3 downto 0), + \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(2 downto 0) => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(2 downto 0), + in1 => in1, + m_avalid_1 => m_avalid_1, + m_ready_d(0) => m_ready_d(0), + m_select_enc_0 => m_select_enc_0, + m_valid_i_reg_0(0) => m_valid_i_reg(0), + p_10_in => p_10_in, + s_axi_wlast(0) => s_axi_wlast(0), + s_axi_wready(0) => s_axi_wready(0), + s_axi_wvalid(0) => s_axi_wvalid(0), + s_ready_i_reg => s_ready_i_reg, + sa_wm_awvalid(0) => sa_wm_awvalid(0), + \storage_data1_reg[0]_0\ => m_select_enc, + \storage_data1_reg[0]_1\ => \storage_data1_reg[0]\, + \storage_data1_reg[0]_2\ => \storage_data1_reg[0]_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_wdata_router is + port ( + SS : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_avalid : out STD_LOGIC; + ss_wr_awready : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_select_enc : out STD_LOGIC; + s_ready_i_reg : out STD_LOGIC; + \gen_rep[0].fifoaddr_reg[0]\ : out STD_LOGIC; + aclk : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); + m_valid_i_reg : in STD_LOGIC; + \storage_data1_reg[0]\ : in STD_LOGIC; + s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_select_enc_0 : in STD_LOGIC; + m_avalid_1 : in STD_LOGIC; + p_10_in : in STD_LOGIC; + \m_ready_d_reg[1]\ : in STD_LOGIC + ); +end Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_wdata_router; + +architecture STRUCTURE of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_wdata_router is +begin +wrouter_aw_fifo: entity work.Arty_Z7_20_xbar_1_axi_data_fifo_v2_1_10_axic_reg_srl_fifo + port map ( + SR(0) => SS(0), + aclk => aclk, + aresetn_d_reg(0) => SR(0), + \gen_rep[0].fifoaddr_reg[0]_0\ => \gen_rep[0].fifoaddr_reg[0]\, + m_avalid_1 => m_avalid_1, + m_ready_d(0) => m_ready_d(0), + \m_ready_d_reg[1]\ => \m_ready_d_reg[1]\, + m_select_enc => m_select_enc, + m_select_enc_0 => m_select_enc_0, + m_valid_i_reg_0 => m_valid_i_reg, + p_10_in => p_10_in, + s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0), + s_axi_awvalid(0) => s_axi_awvalid(0), + s_axi_wlast(0) => s_axi_wlast(0), + s_axi_wvalid(0) => s_axi_wvalid(0), + s_ready_i_reg_0 => ss_wr_awready(0), + s_ready_i_reg_1 => s_ready_i_reg, + \storage_data1_reg[0]_0\ => m_avalid, + \storage_data1_reg[0]_1\ => \storage_data1_reg[0]\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_crossbar is + port ( + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_valid_i_reg : out STD_LOGIC; + \m_aready__1\ : out STD_LOGIC; + m_valid_i_reg_0 : out STD_LOGIC; + m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 ); + \m_axi_rready[0]\ : out STD_LOGIC; + m_valid_i_reg_1 : out STD_LOGIC_VECTOR ( 0 to 0 ); + areset_d1 : out STD_LOGIC; + \s_axi_arready[0]\ : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 57 downto 0 ); + s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + D : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \m_axi_arqos[3]\ : out STD_LOGIC_VECTOR ( 56 downto 0 ); + s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 ); + \s_axi_bvalid[1]\ : out STD_LOGIC; + \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + aclk : in STD_LOGIC; + \out\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + aresetn : in STD_LOGIC; + m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + \s_axi_arqos[3]\ : in STD_LOGIC_VECTOR ( 24 downto 0 ); + m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 ) + ); +end Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_crossbar; + +architecture STRUCTURE of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_crossbar is + signal \^q\ : STD_LOGIC_VECTOR ( 57 downto 0 ); + signal aa_mi_artarget_hot : STD_LOGIC_VECTOR ( 1 to 1 ); + signal aa_mi_arvalid : STD_LOGIC; + signal aa_mi_awtarget_hot : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal aa_sa_awready : STD_LOGIC; + signal aa_sa_awvalid : STD_LOGIC; + signal aa_wm_awgrant_enc : STD_LOGIC; + signal active_target_enc : STD_LOGIC; + signal active_target_enc_3 : STD_LOGIC; + signal active_target_hot : STD_LOGIC_VECTOR ( 0 to 0 ); + signal active_target_hot_2 : STD_LOGIC_VECTOR ( 0 to 0 ); + signal addr_arbiter_ar_n_10 : STD_LOGIC; + signal addr_arbiter_ar_n_3 : STD_LOGIC; + signal addr_arbiter_ar_n_4 : STD_LOGIC; + signal addr_arbiter_ar_n_5 : STD_LOGIC; + signal addr_arbiter_ar_n_6 : STD_LOGIC; + signal addr_arbiter_ar_n_8 : STD_LOGIC; + signal addr_arbiter_ar_n_9 : STD_LOGIC; + signal addr_arbiter_aw_n_11 : STD_LOGIC; + signal addr_arbiter_aw_n_12 : STD_LOGIC; + signal addr_arbiter_aw_n_13 : STD_LOGIC; + signal addr_arbiter_aw_n_14 : STD_LOGIC; + signal addr_arbiter_aw_n_15 : STD_LOGIC; + signal addr_arbiter_aw_n_17 : STD_LOGIC; + signal addr_arbiter_aw_n_19 : STD_LOGIC; + signal addr_arbiter_aw_n_4 : STD_LOGIC; + signal addr_arbiter_aw_n_8 : STD_LOGIC; + signal addr_arbiter_aw_n_9 : STD_LOGIC; + signal \^areset_d1\ : STD_LOGIC; + signal aresetn_d : STD_LOGIC; + signal \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\ : STD_LOGIC; + signal \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_0\ : STD_LOGIC; + signal \gen_master_slots[0].gen_mi_write.wdata_mux_w_n_5\ : STD_LOGIC; + signal \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_master_slots[0].reg_slice_mi_n_1\ : STD_LOGIC; + signal \gen_master_slots[0].reg_slice_mi_n_6\ : STD_LOGIC; + signal \gen_master_slots[0].reg_slice_mi_n_75\ : STD_LOGIC; + signal \gen_master_slots[0].reg_slice_mi_n_76\ : STD_LOGIC; + signal \gen_master_slots[0].reg_slice_mi_n_77\ : STD_LOGIC; + signal \gen_master_slots[0].reg_slice_mi_n_78\ : STD_LOGIC; + signal \gen_master_slots[0].reg_slice_mi_n_79\ : STD_LOGIC; + signal \gen_master_slots[0].reg_slice_mi_n_80\ : STD_LOGIC; + signal \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_master_slots[1].gen_mi_write.wdata_mux_w_n_5\ : STD_LOGIC; + signal \gen_master_slots[1].reg_slice_mi_n_10\ : STD_LOGIC; + signal \gen_master_slots[1].reg_slice_mi_n_3\ : STD_LOGIC; + signal \gen_master_slots[1].reg_slice_mi_n_4\ : STD_LOGIC; + signal \gen_master_slots[1].reg_slice_mi_n_8\ : STD_LOGIC; + signal \gen_slave_slots[1].gen_si_write.splitter_aw_si_n_0\ : STD_LOGIC; + signal \gen_slave_slots[1].gen_si_write.splitter_aw_si_n_3\ : STD_LOGIC; + signal \gen_slave_slots[1].gen_si_write.splitter_aw_si_n_5\ : STD_LOGIC; + signal \gen_slave_slots[1].gen_si_write.splitter_aw_si_n_6\ : STD_LOGIC; + signal \gen_slave_slots[1].gen_si_write.wdata_router_w_n_4\ : STD_LOGIC; + signal \gen_slave_slots[1].gen_si_write.wdata_router_w_n_5\ : STD_LOGIC; + signal m_avalid : STD_LOGIC; + signal m_avalid_5 : STD_LOGIC; + signal \^m_axi_arqos[3]\ : STD_LOGIC_VECTOR ( 56 downto 0 ); + signal m_ready_d : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m_ready_d_6 : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal m_select_enc : STD_LOGIC; + signal m_select_enc_4 : STD_LOGIC; + signal \^m_valid_i_reg\ : STD_LOGIC; + signal mi_arready : STD_LOGIC_VECTOR ( 1 to 1 ); + signal mi_awready : STD_LOGIC_VECTOR ( 1 to 1 ); + signal mi_bready_1 : STD_LOGIC; + signal mi_rready_1 : STD_LOGIC; + signal p_10_in : STD_LOGIC; + signal p_11_in : STD_LOGIC; + signal p_13_in : STD_LOGIC; + signal p_17_in : STD_LOGIC; + signal p_1_in : STD_LOGIC; + signal p_20_in : STD_LOGIC; + signal p_28_out : STD_LOGIC; + signal p_30_out : STD_LOGIC; + signal p_52_out : STD_LOGIC; + signal p_54_out : STD_LOGIC; + signal p_58_out : STD_LOGIC; + signal p_61_out : STD_LOGIC; + signal r_issuing_cnt : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal \r_pipe/p_1_in\ : STD_LOGIC; + signal \r_pipe/p_1_in_1\ : STD_LOGIC; + signal reset : STD_LOGIC; + signal \^s_axi_arready[0]\ : STD_LOGIC; + signal \^s_axi_awready\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^s_axi_bvalid[1]\ : STD_LOGIC; + signal sa_wm_awvalid : STD_LOGIC_VECTOR ( 1 to 1 ); + signal splitter_aw_mi_n_1 : STD_LOGIC; + signal ss_aa_awready : STD_LOGIC_VECTOR ( 1 to 1 ); + signal ss_wr_awready : STD_LOGIC_VECTOR ( 1 to 1 ); + signal st_aa_arvalid_qual : STD_LOGIC_VECTOR ( 0 to 0 ); + signal st_aa_awvalid_qual : STD_LOGIC_VECTOR ( 1 to 1 ); + signal st_mr_rmesg : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal valid_qual_i111_in : STD_LOGIC; + signal \valid_qual_i1__0\ : STD_LOGIC; + signal w_issuing_cnt : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal \write_cs0__0\ : STD_LOGIC; +begin + Q(57 downto 0) <= \^q\(57 downto 0); + areset_d1 <= \^areset_d1\; + \m_axi_arqos[3]\(56 downto 0) <= \^m_axi_arqos[3]\(56 downto 0); + m_valid_i_reg <= \^m_valid_i_reg\; + \s_axi_arready[0]\ <= \^s_axi_arready[0]\; + s_axi_awready(0) <= \^s_axi_awready\(0); + \s_axi_bvalid[1]\ <= \^s_axi_bvalid[1]\; +addr_arbiter_ar: entity work.Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_addr_arbiter + port map ( + D(56 downto 32) => \s_axi_arqos[3]\(24 downto 0), + D(31 downto 0) => s_axi_araddr(31 downto 0), + E(0) => addr_arbiter_ar_n_8, + Q(0) => aa_mi_artarget_hot(1), + SR(0) => reset, + aa_mi_arvalid => aa_mi_arvalid, + aclk => aclk, + active_target_enc => active_target_enc, + active_target_hot(0) => active_target_hot(0), + aresetn_d => aresetn_d, + \gen_arbiter.m_target_hot_i_reg[0]_0\(0) => \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\, + \gen_arbiter.qual_reg_reg[0]_0\ => addr_arbiter_ar_n_9, + \gen_axi.s_axi_rlast_i_reg\ => addr_arbiter_ar_n_10, + \gen_master_slots[0].r_issuing_cnt_reg[0]\ => addr_arbiter_ar_n_5, + \gen_master_slots[0].r_issuing_cnt_reg[3]\ => \gen_master_slots[1].reg_slice_mi_n_8\, + \gen_master_slots[0].r_issuing_cnt_reg[3]_0\(3 downto 0) => r_issuing_cnt(3 downto 0), + \gen_master_slots[1].r_issuing_cnt_reg[8]\ => addr_arbiter_ar_n_6, + \gen_single_thread.active_target_enc_reg[0]\ => addr_arbiter_ar_n_4, + \gen_single_thread.active_target_hot_reg[0]\ => addr_arbiter_ar_n_3, + \m_axi_arqos[3]\(56 downto 0) => \^m_axi_arqos[3]\(56 downto 0), + m_axi_arready(0) => m_axi_arready(0), + m_axi_arvalid(0) => m_axi_arvalid(0), + m_valid_i_reg => \gen_master_slots[0].reg_slice_mi_n_80\, + mi_arready(0) => mi_arready(1), + p_11_in => p_11_in, + \s_axi_arready[0]\ => \^s_axi_arready[0]\, + s_axi_arvalid(0) => s_axi_arvalid(0), + st_aa_arvalid_qual(0) => st_aa_arvalid_qual(0), + \valid_qual_i1__0\ => \valid_qual_i1__0\ + ); +addr_arbiter_aw: entity work.Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_addr_arbiter_0 + port map ( + D(2) => addr_arbiter_aw_n_12, + D(1) => addr_arbiter_aw_n_13, + D(0) => addr_arbiter_aw_n_14, + E(0) => addr_arbiter_aw_n_11, + Q(1 downto 0) => aa_mi_awtarget_hot(1 downto 0), + SR(0) => reset, + aa_sa_awready => aa_sa_awready, + aa_sa_awvalid => aa_sa_awvalid, + aa_wm_awgrant_enc => aa_wm_awgrant_enc, + aclk => aclk, + aresetn_d => aresetn_d, + \gen_arbiter.m_valid_i_reg_0\ => splitter_aw_mi_n_1, + \gen_arbiter.qual_reg_reg[1]_0\ => addr_arbiter_aw_n_15, + \gen_master_slots[0].w_issuing_cnt_reg[3]\(3 downto 0) => w_issuing_cnt(3 downto 0), + \gen_master_slots[1].w_issuing_cnt_reg[8]\ => addr_arbiter_aw_n_8, + \gen_single_thread.active_target_hot_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_75\, + \m_axi_awqos[3]\(57 downto 0) => \^q\(57 downto 0), + m_axi_awready(0) => m_axi_awready(0), + m_axi_awvalid(0) => m_axi_awvalid(0), + m_ready_d(1 downto 0) => m_ready_d_6(1 downto 0), + m_ready_d_0(0) => m_ready_d(0), + \m_ready_d_reg[0]\ => \gen_slave_slots[1].gen_si_write.splitter_aw_si_n_5\, + \m_ready_d_reg[1]\ => addr_arbiter_aw_n_9, + \m_ready_d_reg[1]_0\ => addr_arbiter_aw_n_19, + m_valid_i_reg => \^m_valid_i_reg\, + mi_awready(0) => mi_awready(1), + \out\(1 downto 0) => \out\(1 downto 0), + s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), + s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), + s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0), + s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0), + s_axi_awlock(0) => s_axi_awlock(0), + s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), + s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0), + s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0), + s_axi_awvalid(0) => s_axi_awvalid(0), + sa_wm_awvalid(0) => sa_wm_awvalid(1), + sel_4 => \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_0\, + ss_aa_awready(0) => ss_aa_awready(1), + st_aa_awvalid_qual(0) => st_aa_awvalid_qual(1), + \storage_data1_reg[0]\ => addr_arbiter_aw_n_4, + \storage_data1_reg[0]_0\ => addr_arbiter_aw_n_17, + valid_qual_i111_in => valid_qual_i111_in + ); +aresetn_d_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => '1', + D => aresetn, + Q => aresetn_d, + R => '0' + ); +\gen_decerr_slave.decerr_slave_inst\: entity work.Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_decerr_slave + port map ( + Q(0) => \^q\(0), + SR(0) => reset, + aa_mi_arvalid => aa_mi_arvalid, + aclk => aclk, + aresetn_d => aresetn_d, + \gen_arbiter.m_mesg_i_reg[40]\(7 downto 0) => \^m_axi_arqos[3]\(39 downto 32), + \gen_arbiter.m_target_hot_i_reg[1]\(0) => aa_mi_artarget_hot(1), + \gen_axi.read_cs_reg[0]_0\ => addr_arbiter_ar_n_10, + \gen_axi.s_axi_awready_i_reg_0\ => addr_arbiter_aw_n_8, + mi_arready(0) => mi_arready(1), + mi_awready(0) => mi_awready(1), + mi_bready_1 => mi_bready_1, + mi_rready_1 => mi_rready_1, + p_10_in => p_10_in, + p_11_in => p_11_in, + p_13_in => p_13_in, + p_17_in => p_17_in, + p_20_in => p_20_in, + \write_cs0__0\ => \write_cs0__0\ + ); +\gen_master_slots[0].gen_mi_write.wdata_mux_w\: entity work.Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_wdata_mux + port map ( + D(1 downto 0) => D(1 downto 0), + E(0) => E(0), + Q(0) => aa_mi_awtarget_hot(0), + SR(0) => reset, + aa_sa_awvalid => aa_sa_awvalid, + aa_wm_awgrant_enc => aa_wm_awgrant_enc, + aclk => aclk, + \gen_arbiter.m_valid_i_reg\ => \^m_valid_i_reg\, + \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\ => addr_arbiter_aw_n_4, + \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\ => addr_arbiter_aw_n_17, + in1 => \^areset_d1\, + m_avalid => m_avalid_5, + m_axi_wdata(63 downto 0) => m_axi_wdata(63 downto 0), + m_axi_wlast(0) => m_axi_wlast(0), + m_axi_wready(0) => m_axi_wready(0), + m_axi_wstrb(7 downto 0) => m_axi_wstrb(7 downto 0), + m_axi_wvalid(0) => m_axi_wvalid(0), + m_ready_d(0) => m_ready_d_6(0), + m_select_enc => m_select_enc_4, + m_valid_i_reg => m_valid_i_reg_0, + m_valid_i_reg_0 => \gen_slave_slots[1].gen_si_write.wdata_router_w_n_4\, + \out\(2 downto 0) => \out\(2 downto 0), + s_axi_wdata(63 downto 0) => s_axi_wdata(63 downto 0), + s_axi_wlast(0) => s_axi_wlast(0), + s_axi_wstrb(7 downto 0) => s_axi_wstrb(7 downto 0), + s_axi_wvalid(0) => s_axi_wvalid(0), + s_ready_i_reg => \gen_master_slots[0].gen_mi_write.wdata_mux_w_n_5\, + \storage_data1_reg[0]\ => \m_aready__1\ + ); +\gen_master_slots[0].r_issuing_cnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => r_issuing_cnt(0), + O => \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\ + ); +\gen_master_slots[0].r_issuing_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => addr_arbiter_ar_n_8, + D => \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\, + Q => r_issuing_cnt(0), + R => reset + ); +\gen_master_slots[0].r_issuing_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => addr_arbiter_ar_n_8, + D => \gen_master_slots[0].reg_slice_mi_n_79\, + Q => r_issuing_cnt(1), + R => reset + ); +\gen_master_slots[0].r_issuing_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => addr_arbiter_ar_n_8, + D => \gen_master_slots[0].reg_slice_mi_n_78\, + Q => r_issuing_cnt(2), + R => reset + ); +\gen_master_slots[0].r_issuing_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => addr_arbiter_ar_n_8, + D => \gen_master_slots[0].reg_slice_mi_n_77\, + Q => r_issuing_cnt(3), + R => reset + ); +\gen_master_slots[0].reg_slice_mi\: entity work.Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axi_register_slice + port map ( + D(2) => \gen_master_slots[0].reg_slice_mi_n_77\, + D(1) => \gen_master_slots[0].reg_slice_mi_n_78\, + D(0) => \gen_master_slots[0].reg_slice_mi_n_79\, + E(0) => \r_pipe/p_1_in_1\, + Q(2) => p_54_out, + Q(1 downto 0) => st_mr_rmesg(1 downto 0), + aclk => aclk, + active_target_enc => active_target_enc, + active_target_enc_1 => active_target_enc_3, + active_target_hot(0) => active_target_hot_2(0), + active_target_hot_0(0) => active_target_hot(0), + aresetn => aresetn, + \gen_arbiter.m_valid_i_reg\ => addr_arbiter_ar_n_5, + \gen_arbiter.qual_reg_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_76\, + \gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_80\, + \gen_master_slots[0].r_issuing_cnt_reg[3]\(3 downto 0) => r_issuing_cnt(3 downto 0), + \gen_master_slots[0].w_issuing_cnt_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_75\, + m_axi_bid(0) => m_axi_bid(0), + m_axi_bready(0) => m_axi_bready(0), + m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), + m_axi_bvalid(0) => m_axi_bvalid(0), + m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0), + m_axi_rlast(0) => m_axi_rlast(0), + \m_axi_rready[0]\ => \m_axi_rready[0]\, + m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0), + m_axi_rvalid(0) => m_axi_rvalid(0), + m_valid_i_reg => \gen_master_slots[0].reg_slice_mi_n_1\, + p_1_in => p_1_in, + p_30_out => p_30_out, + p_52_out => p_52_out, + p_58_out => p_58_out, + p_61_out => p_61_out, + s_axi_bready(0) => s_axi_bready(0), + s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0), + s_axi_rdata(63 downto 0) => s_axi_rdata(63 downto 0), + s_axi_rready(0) => s_axi_rready(0), + s_ready_i_reg => \gen_master_slots[0].reg_slice_mi_n_6\ + ); +\gen_master_slots[0].w_issuing_cnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => w_issuing_cnt(0), + O => \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\ + ); +\gen_master_slots[0].w_issuing_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => addr_arbiter_aw_n_11, + D => \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\, + Q => w_issuing_cnt(0), + R => reset + ); +\gen_master_slots[0].w_issuing_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => addr_arbiter_aw_n_11, + D => addr_arbiter_aw_n_14, + Q => w_issuing_cnt(1), + R => reset + ); +\gen_master_slots[0].w_issuing_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => addr_arbiter_aw_n_11, + D => addr_arbiter_aw_n_13, + Q => w_issuing_cnt(2), + R => reset + ); +\gen_master_slots[0].w_issuing_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => addr_arbiter_aw_n_11, + D => addr_arbiter_aw_n_12, + Q => w_issuing_cnt(3), + R => reset + ); +\gen_master_slots[1].gen_mi_write.wdata_mux_w\: entity work.\Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_wdata_mux__parameterized0\ + port map ( + Q(0) => aa_mi_awtarget_hot(1), + SR(0) => reset, + aa_sa_awvalid => aa_sa_awvalid, + aa_wm_awgrant_enc => aa_wm_awgrant_enc, + aclk => aclk, + \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(3 downto 0) => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(3 downto 0), + \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(2 downto 0) => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(2 downto 0), + in1 => \^areset_d1\, + m_avalid => m_avalid, + m_avalid_1 => m_avalid_5, + m_ready_d(0) => m_ready_d_6(0), + m_select_enc => m_select_enc, + m_select_enc_0 => m_select_enc_4, + m_valid_i_reg(0) => m_valid_i_reg_1(0), + p_10_in => p_10_in, + s_axi_wlast(0) => s_axi_wlast(0), + s_axi_wready(0) => s_axi_wready(0), + s_axi_wvalid(0) => s_axi_wvalid(0), + s_ready_i_reg => \gen_master_slots[1].gen_mi_write.wdata_mux_w_n_5\, + sa_wm_awvalid(0) => sa_wm_awvalid(1), + \storage_data1_reg[0]\ => \gen_slave_slots[1].gen_si_write.wdata_router_w_n_5\, + \storage_data1_reg[0]_0\ => \gen_master_slots[0].gen_mi_write.wdata_mux_w_n_5\, + \write_cs0__0\ => \write_cs0__0\ + ); +\gen_master_slots[1].r_issuing_cnt_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \gen_master_slots[1].reg_slice_mi_n_4\, + Q => r_issuing_cnt(8), + R => reset + ); +\gen_master_slots[1].reg_slice_mi\: entity work.Arty_Z7_20_xbar_1_axi_register_slice_v2_1_11_axi_register_slice_1 + port map ( + Q(2) => p_54_out, + Q(1 downto 0) => st_mr_rmesg(1 downto 0), + aclk => aclk, + active_target_enc => active_target_enc_3, + active_target_enc_0 => active_target_enc, + active_target_hot(0) => active_target_hot_2(0), + \aresetn_d_reg[1]\ => \gen_master_slots[0].reg_slice_mi_n_1\, + \aresetn_d_reg[1]_0\ => \gen_master_slots[0].reg_slice_mi_n_6\, + \gen_arbiter.m_valid_i_reg\ => addr_arbiter_ar_n_6, + \gen_arbiter.qual_reg_reg[0]\ => \gen_master_slots[1].reg_slice_mi_n_8\, + \gen_arbiter.qual_reg_reg[0]_0\ => \gen_master_slots[1].reg_slice_mi_n_10\, + \gen_axi.s_axi_awready_i_reg\ => addr_arbiter_aw_n_8, + \gen_master_slots[0].r_issuing_cnt_reg[2]\ => addr_arbiter_ar_n_9, + \gen_master_slots[0].w_issuing_cnt_reg[2]\ => addr_arbiter_aw_n_15, + \gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].reg_slice_mi_n_4\, + \gen_master_slots[1].w_issuing_cnt_reg[8]\ => \gen_master_slots[1].reg_slice_mi_n_3\, + \gen_single_thread.active_target_hot_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_75\, + m_valid_i_reg => \gen_master_slots[0].reg_slice_mi_n_80\, + mi_bready_1 => mi_bready_1, + mi_rready_1 => mi_rready_1, + p_11_in => p_11_in, + p_13_in => p_13_in, + p_17_in => p_17_in, + p_1_in => p_1_in, + p_1_in_1 => \r_pipe/p_1_in\, + p_20_in => p_20_in, + p_28_out => p_28_out, + p_30_out => p_30_out, + p_58_out => p_58_out, + p_61_out => p_61_out, + r_issuing_cnt(1) => r_issuing_cnt(8), + r_issuing_cnt(0) => r_issuing_cnt(3), + \s_axi_araddr[29]\(0) => \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\, + s_axi_arvalid(0) => s_axi_arvalid(0), + s_axi_bready(0) => s_axi_bready(0), + \s_axi_bvalid[1]\ => \^s_axi_bvalid[1]\, + s_axi_rlast(0) => s_axi_rlast(0), + s_axi_rready(0) => s_axi_rready(0), + s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0), + sel_4 => \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_0\, + st_aa_arvalid_qual(0) => st_aa_arvalid_qual(0), + valid_qual_i111_in => valid_qual_i111_in, + \valid_qual_i1__0\ => \valid_qual_i1__0\, + w_issuing_cnt(1) => w_issuing_cnt(8), + w_issuing_cnt(0) => w_issuing_cnt(3) + ); +\gen_master_slots[1].w_issuing_cnt_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => aclk, + CE => '1', + D => \gen_master_slots[1].reg_slice_mi_n_3\, + Q => w_issuing_cnt(8), + R => reset + ); +\gen_slave_slots[0].gen_si_read.si_transactor_ar\: entity work.Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_si_transactor + port map ( + E(0) => \r_pipe/p_1_in_1\, + Q(0) => p_54_out, + SR(0) => reset, + aclk => aclk, + active_target_enc => active_target_enc, + active_target_hot(0) => active_target_hot(0), + \gen_arbiter.s_ready_i_reg[0]\ => addr_arbiter_ar_n_4, + \gen_arbiter.s_ready_i_reg[0]_0\ => addr_arbiter_ar_n_3, + \gen_arbiter.s_ready_i_reg[0]_1\ => \^s_axi_arready[0]\, + \m_payload_i_reg[66]\ => \gen_master_slots[0].reg_slice_mi_n_76\, + m_valid_i_reg => \gen_master_slots[1].reg_slice_mi_n_10\, + p_1_in => \r_pipe/p_1_in\, + p_28_out => p_28_out, + p_30_out => p_30_out, + p_52_out => p_52_out, + \s_axi_araddr[29]\(0) => \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\, + s_axi_rready(0) => s_axi_rready(0), + s_axi_rvalid(0) => s_axi_rvalid(0), + st_aa_arvalid_qual(0) => st_aa_arvalid_qual(0) + ); +\gen_slave_slots[1].gen_si_write.si_transactor_aw\: entity work.\Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_si_transactor__parameterized0\ + port map ( + SR(0) => reset, + aclk => aclk, + active_target_enc => active_target_enc_3, + active_target_hot(0) => active_target_hot_2(0), + \m_payload_i_reg[2]\ => \^s_axi_bvalid[1]\, + s_axi_awready(0) => \^s_axi_awready\(0), + s_axi_bready(0) => s_axi_bready(0), + s_ready_i_reg => \gen_slave_slots[1].gen_si_write.splitter_aw_si_n_3\, + s_ready_i_reg_0 => \gen_slave_slots[1].gen_si_write.splitter_aw_si_n_0\, + sel_4 => \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_0\, + st_aa_awvalid_qual(0) => st_aa_awvalid_qual(1) + ); +\gen_slave_slots[1].gen_si_write.splitter_aw_si\: entity work.Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_splitter + port map ( + aclk => aclk, + active_target_enc => active_target_enc_3, + active_target_hot(0) => active_target_hot_2(0), + aresetn_d => aresetn_d, + \gen_arbiter.qual_reg_reg[1]\ => \gen_slave_slots[1].gen_si_write.splitter_aw_si_n_5\, + \gen_rep[0].fifoaddr_reg[0]\ => \gen_slave_slots[1].gen_si_write.splitter_aw_si_n_6\, + \gen_single_thread.active_target_enc_reg[0]\ => \gen_slave_slots[1].gen_si_write.splitter_aw_si_n_3\, + \gen_single_thread.active_target_hot_reg[0]\ => \gen_slave_slots[1].gen_si_write.splitter_aw_si_n_0\, + m_ready_d(1 downto 0) => m_ready_d(1 downto 0), + s_axi_awready(0) => \^s_axi_awready\(0), + s_axi_awvalid(0) => s_axi_awvalid(0), + sel_4 => \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_0\, + ss_aa_awready(0) => ss_aa_awready(1), + ss_wr_awready(0) => ss_wr_awready(1), + st_aa_awvalid_qual(0) => st_aa_awvalid_qual(1), + valid_qual_i111_in => valid_qual_i111_in + ); +\gen_slave_slots[1].gen_si_write.wdata_router_w\: entity work.Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_wdata_router + port map ( + SR(0) => reset, + SS(0) => \^areset_d1\, + aclk => aclk, + \gen_rep[0].fifoaddr_reg[0]\ => \gen_slave_slots[1].gen_si_write.wdata_router_w_n_5\, + m_avalid => m_avalid_5, + m_avalid_1 => m_avalid, + m_ready_d(0) => m_ready_d(1), + \m_ready_d_reg[1]\ => \gen_slave_slots[1].gen_si_write.splitter_aw_si_n_6\, + m_select_enc => m_select_enc_4, + m_select_enc_0 => m_select_enc, + m_valid_i_reg => \gen_master_slots[1].gen_mi_write.wdata_mux_w_n_5\, + p_10_in => p_10_in, + s_axi_awaddr(2 downto 0) => s_axi_awaddr(31 downto 29), + s_axi_awvalid(0) => s_axi_awvalid(0), + s_axi_wlast(0) => s_axi_wlast(0), + s_axi_wvalid(0) => s_axi_wvalid(0), + s_ready_i_reg => \gen_slave_slots[1].gen_si_write.wdata_router_w_n_4\, + ss_wr_awready(0) => ss_wr_awready(1), + \storage_data1_reg[0]\ => \gen_master_slots[0].gen_mi_write.wdata_mux_w_n_5\ + ); +splitter_aw_mi: entity work.Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_splitter_2 + port map ( + Q(1 downto 0) => aa_mi_awtarget_hot(1 downto 0), + aa_sa_awready => aa_sa_awready, + aa_sa_awvalid => aa_sa_awvalid, + aclk => aclk, + aresetn_d => aresetn_d, + \gen_arbiter.any_grant_reg\ => splitter_aw_mi_n_1, + \gen_arbiter.m_target_hot_i_reg[0]\ => addr_arbiter_aw_n_19, + \gen_arbiter.m_target_hot_i_reg[1]\ => addr_arbiter_aw_n_9, + m_axi_awready(0) => m_axi_awready(0), + m_ready_d(1 downto 0) => m_ready_d_6(1 downto 0), + mi_awready(0) => mi_awready(1) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar is + port ( + aclk : in STD_LOGIC; + aresetn : in STD_LOGIC; + s_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 15 downto 0 ); + s_axi_awsize : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_awburst : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awcache : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_awqos : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_awuser : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awvalid : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awready : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_wid : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 ); + s_axi_wlast : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_wuser : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_wvalid : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_wready : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bid : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bresp : out STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_buser : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bready : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axi_arlen : in STD_LOGIC_VECTOR ( 15 downto 0 ); + s_axi_arsize : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_arburst : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arcache : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_arprot : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_arqos : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_aruser : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arvalid : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arready : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rid : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_rlast : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_ruser : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rvalid : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rready : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rready : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute C_AXI_ADDR_WIDTH : integer; + attribute C_AXI_ADDR_WIDTH of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 32; + attribute C_AXI_ARUSER_WIDTH : integer; + attribute C_AXI_ARUSER_WIDTH of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1; + attribute C_AXI_AWUSER_WIDTH : integer; + attribute C_AXI_AWUSER_WIDTH of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1; + attribute C_AXI_BUSER_WIDTH : integer; + attribute C_AXI_BUSER_WIDTH of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1; + attribute C_AXI_DATA_WIDTH : integer; + attribute C_AXI_DATA_WIDTH of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 64; + attribute C_AXI_ID_WIDTH : integer; + attribute C_AXI_ID_WIDTH of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1; + attribute C_AXI_PROTOCOL : integer; + attribute C_AXI_PROTOCOL of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 0; + attribute C_AXI_RUSER_WIDTH : integer; + attribute C_AXI_RUSER_WIDTH of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1; + attribute C_AXI_SUPPORTS_USER_SIGNALS : integer; + attribute C_AXI_SUPPORTS_USER_SIGNALS of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 0; + attribute C_AXI_WUSER_WIDTH : integer; + attribute C_AXI_WUSER_WIDTH of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1; + attribute C_CONNECTIVITY_MODE : integer; + attribute C_CONNECTIVITY_MODE of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1; + attribute C_DEBUG : integer; + attribute C_DEBUG of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1; + attribute C_FAMILY : string; + attribute C_FAMILY of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "zynq"; + attribute C_M_AXI_ADDR_WIDTH : integer; + attribute C_M_AXI_ADDR_WIDTH of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 29; + attribute C_M_AXI_BASE_ADDR : string; + attribute C_M_AXI_BASE_ADDR of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000"; + attribute C_M_AXI_READ_CONNECTIVITY : integer; + attribute C_M_AXI_READ_CONNECTIVITY of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1; + attribute C_M_AXI_READ_ISSUING : integer; + attribute C_M_AXI_READ_ISSUING of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 8; + attribute C_M_AXI_SECURE : integer; + attribute C_M_AXI_SECURE of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 0; + attribute C_M_AXI_WRITE_CONNECTIVITY : integer; + attribute C_M_AXI_WRITE_CONNECTIVITY of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 2; + attribute C_M_AXI_WRITE_ISSUING : integer; + attribute C_M_AXI_WRITE_ISSUING of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 8; + attribute C_NUM_ADDR_RANGES : integer; + attribute C_NUM_ADDR_RANGES of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1; + attribute C_NUM_MASTER_SLOTS : integer; + attribute C_NUM_MASTER_SLOTS of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1; + attribute C_NUM_SLAVE_SLOTS : integer; + attribute C_NUM_SLAVE_SLOTS of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 2; + attribute C_R_REGISTER : integer; + attribute C_R_REGISTER of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 0; + attribute C_S_AXI_ARB_PRIORITY : string; + attribute C_S_AXI_ARB_PRIORITY of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000"; + attribute C_S_AXI_BASE_ID : string; + attribute C_S_AXI_BASE_ID of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "64'b0000000000000000000000000000000100000000000000000000000000000000"; + attribute C_S_AXI_READ_ACCEPTANCE : string; + attribute C_S_AXI_READ_ACCEPTANCE of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "64'b0000000000000000000000000000001000000000000000000000000000000010"; + attribute C_S_AXI_SINGLE_THREAD : string; + attribute C_S_AXI_SINGLE_THREAD of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000"; + attribute C_S_AXI_THREAD_ID_WIDTH : string; + attribute C_S_AXI_THREAD_ID_WIDTH of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000"; + attribute C_S_AXI_WRITE_ACCEPTANCE : string; + attribute C_S_AXI_WRITE_ACCEPTANCE of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "64'b0000000000000000000000000000001000000000000000000000000000000010"; + attribute DowngradeIPIdentifiedWarnings : string; + attribute DowngradeIPIdentifiedWarnings of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "yes"; + attribute P_ADDR_DECODE : integer; + attribute P_ADDR_DECODE of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1; + attribute P_AXI3 : integer; + attribute P_AXI3 of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1; + attribute P_AXI4 : integer; + attribute P_AXI4 of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 0; + attribute P_AXILITE : integer; + attribute P_AXILITE of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 2; + attribute P_AXILITE_SIZE : string; + attribute P_AXILITE_SIZE of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "3'b010"; + attribute P_FAMILY : string; + attribute P_FAMILY of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "zynq"; + attribute P_INCR : string; + attribute P_INCR of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "2'b01"; + attribute P_LEN : integer; + attribute P_LEN of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 8; + attribute P_LOCK : integer; + attribute P_LOCK of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1; + attribute P_M_AXI_ERR_MODE : string; + attribute P_M_AXI_ERR_MODE of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "32'b00000000000000000000000000000000"; + attribute P_M_AXI_SUPPORTS_READ : string; + attribute P_M_AXI_SUPPORTS_READ of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "1'b1"; + attribute P_M_AXI_SUPPORTS_WRITE : string; + attribute P_M_AXI_SUPPORTS_WRITE of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "1'b1"; + attribute P_ONES : string; + attribute P_ONES of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "65'b11111111111111111111111111111111111111111111111111111111111111111"; + attribute P_RANGE_CHECK : integer; + attribute P_RANGE_CHECK of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1; + attribute P_S_AXI_BASE_ID : string; + attribute P_S_AXI_BASE_ID of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "128'b00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000"; + attribute P_S_AXI_HIGH_ID : string; + attribute P_S_AXI_HIGH_ID of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "128'b00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000"; + attribute P_S_AXI_SUPPORTS_READ : string; + attribute P_S_AXI_SUPPORTS_READ of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "2'b01"; + attribute P_S_AXI_SUPPORTS_WRITE : string; + attribute P_S_AXI_SUPPORTS_WRITE of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "2'b10"; +end Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar; + +architecture STRUCTURE of Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar is + signal \\ : STD_LOGIC; + signal \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[2]\ : STD_LOGIC; + attribute RTL_KEEP : string; + attribute RTL_KEEP of \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[2]\ : signal is "yes"; + signal \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3]\ : STD_LOGIC; + attribute RTL_KEEP of \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3]\ : signal is "yes"; + signal \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i\ : STD_LOGIC; + signal \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in\ : STD_LOGIC; + attribute RTL_KEEP of \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in\ : signal is "yes"; + signal \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in\ : STD_LOGIC; + attribute RTL_KEEP of \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in\ : signal is "yes"; + signal \gen_master_slots[0].gen_mi_write.wdata_mux_w/m_aready__1\ : STD_LOGIC; + signal \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[2]\ : STD_LOGIC; + attribute RTL_KEEP of \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[2]\ : signal is "yes"; + signal \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3]\ : STD_LOGIC; + attribute RTL_KEEP of \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3]\ : signal is "yes"; + signal \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i\ : STD_LOGIC; + signal \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in\ : STD_LOGIC; + attribute RTL_KEEP of \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in\ : signal is "yes"; + signal \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in\ : STD_LOGIC; + attribute RTL_KEEP of \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in\ : signal is "yes"; + signal \gen_samd.crossbar_samd_n_1\ : STD_LOGIC; + signal \gen_samd.crossbar_samd_n_131\ : STD_LOGIC; + signal \gen_samd.crossbar_samd_n_132\ : STD_LOGIC; + signal \gen_samd.crossbar_samd_n_192\ : STD_LOGIC; + signal \gen_samd.crossbar_samd_n_193\ : STD_LOGIC; + signal \gen_samd.crossbar_samd_n_194\ : STD_LOGIC; + signal \gen_samd.crossbar_samd_n_195\ : STD_LOGIC; + signal \gen_samd.crossbar_samd_n_3\ : STD_LOGIC; + signal \gen_slave_slots[1].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1\ : STD_LOGIC; + signal \^s_axi_arready\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^s_axi_awready\ : STD_LOGIC_VECTOR ( 1 to 1 ); + signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \^s_axi_bvalid\ : STD_LOGIC_VECTOR ( 1 to 1 ); + signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal \^s_axi_rlast\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^s_axi_rresp\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^s_axi_rvalid\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^s_axi_wready\ : STD_LOGIC_VECTOR ( 1 to 1 ); + attribute KEEP : string; + attribute KEEP of \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\ : label is "yes"; + attribute KEEP of \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\ : label is "yes"; + attribute KEEP of \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[2]\ : label is "yes"; + attribute KEEP of \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\ : label is "yes"; + attribute KEEP of \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\ : label is "yes"; + attribute KEEP of \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\ : label is "yes"; + attribute KEEP of \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[2]\ : label is "yes"; + attribute KEEP of \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\ : label is "yes"; +begin + m_axi_arid(0) <= \\; + m_axi_arregion(3) <= \\; + m_axi_arregion(2) <= \\; + m_axi_arregion(1) <= \\; + m_axi_arregion(0) <= \\; + m_axi_aruser(0) <= \\; + m_axi_awregion(3) <= \\; + m_axi_awregion(2) <= \\; + m_axi_awregion(1) <= \\; + m_axi_awregion(0) <= \\; + m_axi_awuser(0) <= \\; + m_axi_wid(0) <= \\; + m_axi_wuser(0) <= \\; + s_axi_arready(1) <= \\; + s_axi_arready(0) <= \^s_axi_arready\(0); + s_axi_awready(1) <= \^s_axi_awready\(1); + s_axi_awready(0) <= \\; + s_axi_bid(1) <= \\; + s_axi_bid(0) <= \\; + s_axi_bresp(3 downto 2) <= \^s_axi_bresp\(3 downto 2); + s_axi_bresp(1) <= \\; + s_axi_bresp(0) <= \\; + s_axi_buser(1) <= \\; + s_axi_buser(0) <= \\; + s_axi_bvalid(1) <= \^s_axi_bvalid\(1); + s_axi_bvalid(0) <= \\; + s_axi_rdata(127) <= \\; + s_axi_rdata(126) <= \\; + s_axi_rdata(125) <= \\; + s_axi_rdata(124) <= \\; + s_axi_rdata(123) <= \\; + s_axi_rdata(122) <= \\; + s_axi_rdata(121) <= \\; + s_axi_rdata(120) <= \\; + s_axi_rdata(119) <= \\; + s_axi_rdata(118) <= \\; + s_axi_rdata(117) <= \\; + s_axi_rdata(116) <= \\; + s_axi_rdata(115) <= \\; + s_axi_rdata(114) <= \\; + s_axi_rdata(113) <= \\; + s_axi_rdata(112) <= \\; + s_axi_rdata(111) <= \\; + s_axi_rdata(110) <= \\; + s_axi_rdata(109) <= \\; + s_axi_rdata(108) <= \\; + s_axi_rdata(107) <= \\; + s_axi_rdata(106) <= \\; + s_axi_rdata(105) <= \\; + s_axi_rdata(104) <= \\; + s_axi_rdata(103) <= \\; + s_axi_rdata(102) <= \\; + s_axi_rdata(101) <= \\; + s_axi_rdata(100) <= \\; + s_axi_rdata(99) <= \\; + s_axi_rdata(98) <= \\; + s_axi_rdata(97) <= \\; + s_axi_rdata(96) <= \\; + s_axi_rdata(95) <= \\; + s_axi_rdata(94) <= \\; + s_axi_rdata(93) <= \\; + s_axi_rdata(92) <= \\; + s_axi_rdata(91) <= \\; + s_axi_rdata(90) <= \\; + s_axi_rdata(89) <= \\; + s_axi_rdata(88) <= \\; + s_axi_rdata(87) <= \\; + s_axi_rdata(86) <= \\; + s_axi_rdata(85) <= \\; + s_axi_rdata(84) <= \\; + s_axi_rdata(83) <= \\; + s_axi_rdata(82) <= \\; + s_axi_rdata(81) <= \\; + s_axi_rdata(80) <= \\; + s_axi_rdata(79) <= \\; + s_axi_rdata(78) <= \\; + s_axi_rdata(77) <= \\; + s_axi_rdata(76) <= \\; + s_axi_rdata(75) <= \\; + s_axi_rdata(74) <= \\; + s_axi_rdata(73) <= \\; + s_axi_rdata(72) <= \\; + s_axi_rdata(71) <= \\; + s_axi_rdata(70) <= \\; + s_axi_rdata(69) <= \\; + s_axi_rdata(68) <= \\; + s_axi_rdata(67) <= \\; + s_axi_rdata(66) <= \\; + s_axi_rdata(65) <= \\; + s_axi_rdata(64) <= \\; + s_axi_rdata(63 downto 0) <= \^s_axi_rdata\(63 downto 0); + s_axi_rid(1) <= \\; + s_axi_rid(0) <= \\; + s_axi_rlast(1) <= \\; + s_axi_rlast(0) <= \^s_axi_rlast\(0); + s_axi_rresp(3) <= \\; + s_axi_rresp(2) <= \\; + s_axi_rresp(1 downto 0) <= \^s_axi_rresp\(1 downto 0); + s_axi_ruser(1) <= \\; + s_axi_ruser(0) <= \\; + s_axi_rvalid(1) <= \\; + s_axi_rvalid(0) <= \^s_axi_rvalid\(0); + s_axi_wready(1) <= \^s_axi_wready\(1); + s_axi_wready(0) <= \\; +GND: unisim.vcomponents.GND + port map ( + G => \\ + ); +\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0A0A0A0A4A0A0A0A" + ) + port map ( + I0 => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in\, + I1 => \gen_master_slots[0].gen_mi_write.wdata_mux_w/m_aready__1\, + I2 => \gen_samd.crossbar_samd_n_1\, + I3 => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3]\, + I4 => \gen_samd.crossbar_samd_n_3\, + I5 => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in\, + O => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state[1]_i_1_n_0\ + ); +\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"A0A0A0A0B5F5F5F5" + ) + port map ( + I0 => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in\, + I1 => \gen_master_slots[0].gen_mi_write.wdata_mux_w/m_aready__1\, + I2 => \gen_samd.crossbar_samd_n_1\, + I3 => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3]\, + I4 => \gen_samd.crossbar_samd_n_3\, + I5 => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in\, + O => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state[2]_i_1_n_0\ + ); +\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => aclk, + CE => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i\, + D => \gen_samd.crossbar_samd_n_132\, + Q => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in\, + S => \gen_slave_slots[1].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1\ + ); +\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i\, + D => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state[1]_i_1_n_0\, + Q => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in\, + R => \gen_slave_slots[1].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1\ + ); +\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i\, + D => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state[2]_i_1_n_0\, + Q => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[2]\, + R => \gen_slave_slots[1].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1\ + ); +\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i\, + D => \gen_samd.crossbar_samd_n_131\, + Q => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3]\, + R => \gen_slave_slots[1].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1\ + ); +\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => aclk, + CE => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i\, + D => \gen_samd.crossbar_samd_n_195\, + Q => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in\, + S => \gen_slave_slots[1].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1\ + ); +\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i\, + D => \gen_samd.crossbar_samd_n_194\, + Q => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in\, + R => \gen_slave_slots[1].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1\ + ); +\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i\, + D => \gen_samd.crossbar_samd_n_193\, + Q => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[2]\, + R => \gen_slave_slots[1].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1\ + ); +\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => aclk, + CE => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i\, + D => \gen_samd.crossbar_samd_n_192\, + Q => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3]\, + R => \gen_slave_slots[1].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1\ + ); +\gen_samd.crossbar_samd\: entity work.Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_crossbar + port map ( + D(1) => \gen_samd.crossbar_samd_n_131\, + D(0) => \gen_samd.crossbar_samd_n_132\, + E(0) => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i\, + Q(57 downto 54) => m_axi_awqos(3 downto 0), + Q(53 downto 50) => m_axi_awcache(3 downto 0), + Q(49 downto 48) => m_axi_awburst(1 downto 0), + Q(47 downto 45) => m_axi_awprot(2 downto 0), + Q(44) => m_axi_awlock(0), + Q(43 downto 41) => m_axi_awsize(2 downto 0), + Q(40 downto 33) => m_axi_awlen(7 downto 0), + Q(32 downto 1) => m_axi_awaddr(31 downto 0), + Q(0) => m_axi_awid(0), + aclk => aclk, + areset_d1 => \gen_slave_slots[1].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1\, + aresetn => aresetn, + \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(3) => \gen_samd.crossbar_samd_n_192\, + \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(2) => \gen_samd.crossbar_samd_n_193\, + \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(1) => \gen_samd.crossbar_samd_n_194\, + \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(0) => \gen_samd.crossbar_samd_n_195\, + \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(2) => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3]\, + \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(1) => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in\, + \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(0) => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in\, + \m_aready__1\ => \gen_master_slots[0].gen_mi_write.wdata_mux_w/m_aready__1\, + \m_axi_arqos[3]\(56 downto 53) => m_axi_arqos(3 downto 0), + \m_axi_arqos[3]\(52 downto 49) => m_axi_arcache(3 downto 0), + \m_axi_arqos[3]\(48 downto 47) => m_axi_arburst(1 downto 0), + \m_axi_arqos[3]\(46 downto 44) => m_axi_arprot(2 downto 0), + \m_axi_arqos[3]\(43) => m_axi_arlock(0), + \m_axi_arqos[3]\(42 downto 40) => m_axi_arsize(2 downto 0), + \m_axi_arqos[3]\(39 downto 32) => m_axi_arlen(7 downto 0), + \m_axi_arqos[3]\(31 downto 0) => m_axi_araddr(31 downto 0), + m_axi_arready(0) => m_axi_arready(0), + m_axi_arvalid(0) => m_axi_arvalid(0), + m_axi_awready(0) => m_axi_awready(0), + m_axi_awvalid(0) => m_axi_awvalid(0), + m_axi_bid(0) => m_axi_bid(0), + m_axi_bready(0) => m_axi_bready(0), + m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), + m_axi_bvalid(0) => m_axi_bvalid(0), + m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0), + m_axi_rlast(0) => m_axi_rlast(0), + \m_axi_rready[0]\ => m_axi_rready(0), + m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0), + m_axi_rvalid(0) => m_axi_rvalid(0), + m_axi_wdata(63 downto 0) => m_axi_wdata(63 downto 0), + m_axi_wlast(0) => m_axi_wlast(0), + m_axi_wready(0) => m_axi_wready(0), + m_axi_wstrb(7 downto 0) => m_axi_wstrb(7 downto 0), + m_axi_wvalid(0) => m_axi_wvalid(0), + m_valid_i_reg => \gen_samd.crossbar_samd_n_1\, + m_valid_i_reg_0 => \gen_samd.crossbar_samd_n_3\, + m_valid_i_reg_1(0) => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i\, + \out\(2) => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3]\, + \out\(1) => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in\, + \out\(0) => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in\, + s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), + \s_axi_arqos[3]\(24 downto 21) => s_axi_arqos(3 downto 0), + \s_axi_arqos[3]\(20 downto 17) => s_axi_arcache(3 downto 0), + \s_axi_arqos[3]\(16 downto 15) => s_axi_arburst(1 downto 0), + \s_axi_arqos[3]\(14 downto 12) => s_axi_arprot(2 downto 0), + \s_axi_arqos[3]\(11) => s_axi_arlock(0), + \s_axi_arqos[3]\(10 downto 8) => s_axi_arsize(2 downto 0), + \s_axi_arqos[3]\(7 downto 0) => s_axi_arlen(7 downto 0), + \s_axi_arready[0]\ => \^s_axi_arready\(0), + s_axi_arvalid(0) => s_axi_arvalid(0), + s_axi_awaddr(31 downto 0) => s_axi_awaddr(63 downto 32), + s_axi_awburst(1 downto 0) => s_axi_awburst(3 downto 2), + s_axi_awcache(3 downto 0) => s_axi_awcache(7 downto 4), + s_axi_awlen(7 downto 0) => s_axi_awlen(15 downto 8), + s_axi_awlock(0) => s_axi_awlock(1), + s_axi_awprot(2 downto 0) => s_axi_awprot(5 downto 3), + s_axi_awqos(3 downto 0) => s_axi_awqos(7 downto 4), + s_axi_awready(0) => \^s_axi_awready\(1), + s_axi_awsize(2 downto 0) => s_axi_awsize(5 downto 3), + s_axi_awvalid(0) => s_axi_awvalid(1), + s_axi_bready(0) => s_axi_bready(1), + s_axi_bresp(1 downto 0) => \^s_axi_bresp\(3 downto 2), + \s_axi_bvalid[1]\ => \^s_axi_bvalid\(1), + s_axi_rdata(63 downto 0) => \^s_axi_rdata\(63 downto 0), + s_axi_rlast(0) => \^s_axi_rlast\(0), + s_axi_rready(0) => s_axi_rready(0), + s_axi_rresp(1 downto 0) => \^s_axi_rresp\(1 downto 0), + s_axi_rvalid(0) => \^s_axi_rvalid\(0), + s_axi_wdata(63 downto 0) => s_axi_wdata(127 downto 64), + s_axi_wlast(0) => s_axi_wlast(1), + s_axi_wready(0) => \^s_axi_wready\(1), + s_axi_wstrb(7 downto 0) => s_axi_wstrb(15 downto 8), + s_axi_wvalid(0) => s_axi_wvalid(1) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity Arty_Z7_20_xbar_1 is + port ( + aclk : in STD_LOGIC; + aresetn : in STD_LOGIC; + s_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 15 downto 0 ); + s_axi_awsize : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_awburst : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awcache : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_awqos : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_awvalid : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awready : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 ); + s_axi_wlast : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_wvalid : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_wready : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bid : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bresp : out STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_bvalid : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bready : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axi_arlen : in STD_LOGIC_VECTOR ( 15 downto 0 ); + s_axi_arsize : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_arburst : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arcache : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_arprot : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_arqos : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_arvalid : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arready : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rid : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_rlast : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rvalid : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rready : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rready : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of Arty_Z7_20_xbar_1 : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of Arty_Z7_20_xbar_1 : entity is "Arty_Z7_20_xbar_1,axi_crossbar_v2_1_12_axi_crossbar,{}"; + attribute DowngradeIPIdentifiedWarnings : string; + attribute DowngradeIPIdentifiedWarnings of Arty_Z7_20_xbar_1 : entity is "yes"; + attribute X_CORE_INFO : string; + attribute X_CORE_INFO of Arty_Z7_20_xbar_1 : entity is "axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4"; +end Arty_Z7_20_xbar_1; + +architecture STRUCTURE of Arty_Z7_20_xbar_1 is + signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute C_AXI_ADDR_WIDTH : integer; + attribute C_AXI_ADDR_WIDTH of inst : label is 32; + attribute C_AXI_ARUSER_WIDTH : integer; + attribute C_AXI_ARUSER_WIDTH of inst : label is 1; + attribute C_AXI_AWUSER_WIDTH : integer; + attribute C_AXI_AWUSER_WIDTH of inst : label is 1; + attribute C_AXI_BUSER_WIDTH : integer; + attribute C_AXI_BUSER_WIDTH of inst : label is 1; + attribute C_AXI_DATA_WIDTH : integer; + attribute C_AXI_DATA_WIDTH of inst : label is 64; + attribute C_AXI_ID_WIDTH : integer; + attribute C_AXI_ID_WIDTH of inst : label is 1; + attribute C_AXI_PROTOCOL : integer; + attribute C_AXI_PROTOCOL of inst : label is 0; + attribute C_AXI_RUSER_WIDTH : integer; + attribute C_AXI_RUSER_WIDTH of inst : label is 1; + attribute C_AXI_SUPPORTS_USER_SIGNALS : integer; + attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0; + attribute C_AXI_WUSER_WIDTH : integer; + attribute C_AXI_WUSER_WIDTH of inst : label is 1; + attribute C_CONNECTIVITY_MODE : integer; + attribute C_CONNECTIVITY_MODE of inst : label is 1; + attribute C_DEBUG : integer; + attribute C_DEBUG of inst : label is 1; + attribute C_FAMILY : string; + attribute C_FAMILY of inst : label is "zynq"; + attribute C_M_AXI_ADDR_WIDTH : integer; + attribute C_M_AXI_ADDR_WIDTH of inst : label is 29; + attribute C_M_AXI_BASE_ADDR : string; + attribute C_M_AXI_BASE_ADDR of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000"; + attribute C_M_AXI_READ_CONNECTIVITY : integer; + attribute C_M_AXI_READ_CONNECTIVITY of inst : label is 1; + attribute C_M_AXI_READ_ISSUING : integer; + attribute C_M_AXI_READ_ISSUING of inst : label is 8; + attribute C_M_AXI_SECURE : integer; + attribute C_M_AXI_SECURE of inst : label is 0; + attribute C_M_AXI_WRITE_CONNECTIVITY : integer; + attribute C_M_AXI_WRITE_CONNECTIVITY of inst : label is 2; + attribute C_M_AXI_WRITE_ISSUING : integer; + attribute C_M_AXI_WRITE_ISSUING of inst : label is 8; + attribute C_NUM_ADDR_RANGES : integer; + attribute C_NUM_ADDR_RANGES of inst : label is 1; + attribute C_NUM_MASTER_SLOTS : integer; + attribute C_NUM_MASTER_SLOTS of inst : label is 1; + attribute C_NUM_SLAVE_SLOTS : integer; + attribute C_NUM_SLAVE_SLOTS of inst : label is 2; + attribute C_R_REGISTER : integer; + attribute C_R_REGISTER of inst : label is 0; + attribute C_S_AXI_ARB_PRIORITY : string; + attribute C_S_AXI_ARB_PRIORITY of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000"; + attribute C_S_AXI_BASE_ID : string; + attribute C_S_AXI_BASE_ID of inst : label is "64'b0000000000000000000000000000000100000000000000000000000000000000"; + attribute C_S_AXI_READ_ACCEPTANCE : string; + attribute C_S_AXI_READ_ACCEPTANCE of inst : label is "64'b0000000000000000000000000000001000000000000000000000000000000010"; + attribute C_S_AXI_SINGLE_THREAD : string; + attribute C_S_AXI_SINGLE_THREAD of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000"; + attribute C_S_AXI_THREAD_ID_WIDTH : string; + attribute C_S_AXI_THREAD_ID_WIDTH of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000"; + attribute C_S_AXI_WRITE_ACCEPTANCE : string; + attribute C_S_AXI_WRITE_ACCEPTANCE of inst : label is "64'b0000000000000000000000000000001000000000000000000000000000000010"; + attribute DowngradeIPIdentifiedWarnings of inst : label is "yes"; + attribute P_ADDR_DECODE : integer; + attribute P_ADDR_DECODE of inst : label is 1; + attribute P_AXI3 : integer; + attribute P_AXI3 of inst : label is 1; + attribute P_AXI4 : integer; + attribute P_AXI4 of inst : label is 0; + attribute P_AXILITE : integer; + attribute P_AXILITE of inst : label is 2; + attribute P_AXILITE_SIZE : string; + attribute P_AXILITE_SIZE of inst : label is "3'b010"; + attribute P_FAMILY : string; + attribute P_FAMILY of inst : label is "zynq"; + attribute P_INCR : string; + attribute P_INCR of inst : label is "2'b01"; + attribute P_LEN : integer; + attribute P_LEN of inst : label is 8; + attribute P_LOCK : integer; + attribute P_LOCK of inst : label is 1; + attribute P_M_AXI_ERR_MODE : string; + attribute P_M_AXI_ERR_MODE of inst : label is "32'b00000000000000000000000000000000"; + attribute P_M_AXI_SUPPORTS_READ : string; + attribute P_M_AXI_SUPPORTS_READ of inst : label is "1'b1"; + attribute P_M_AXI_SUPPORTS_WRITE : string; + attribute P_M_AXI_SUPPORTS_WRITE of inst : label is "1'b1"; + attribute P_ONES : string; + attribute P_ONES of inst : label is "65'b11111111111111111111111111111111111111111111111111111111111111111"; + attribute P_RANGE_CHECK : integer; + attribute P_RANGE_CHECK of inst : label is 1; + attribute P_S_AXI_BASE_ID : string; + attribute P_S_AXI_BASE_ID of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000"; + attribute P_S_AXI_HIGH_ID : string; + attribute P_S_AXI_HIGH_ID of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000"; + attribute P_S_AXI_SUPPORTS_READ : string; + attribute P_S_AXI_SUPPORTS_READ of inst : label is "2'b01"; + attribute P_S_AXI_SUPPORTS_WRITE : string; + attribute P_S_AXI_SUPPORTS_WRITE of inst : label is "2'b10"; +begin +inst: entity work.Arty_Z7_20_xbar_1_axi_crossbar_v2_1_12_axi_crossbar + port map ( + aclk => aclk, + aresetn => aresetn, + m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0), + m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0), + m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0), + m_axi_arid(0) => m_axi_arid(0), + m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0), + m_axi_arlock(0) => m_axi_arlock(0), + m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0), + m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0), + m_axi_arready(0) => m_axi_arready(0), + m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0), + m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0), + m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0), + m_axi_arvalid(0) => m_axi_arvalid(0), + m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0), + m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0), + m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0), + m_axi_awid(0) => m_axi_awid(0), + m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0), + m_axi_awlock(0) => m_axi_awlock(0), + m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0), + m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0), + m_axi_awready(0) => m_axi_awready(0), + m_axi_awregion(3 downto 0) => m_axi_awregion(3 downto 0), + m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0), + m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0), + m_axi_awvalid(0) => m_axi_awvalid(0), + m_axi_bid(0) => m_axi_bid(0), + m_axi_bready(0) => m_axi_bready(0), + m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), + m_axi_buser(0) => '0', + m_axi_bvalid(0) => m_axi_bvalid(0), + m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0), + m_axi_rid(0) => m_axi_rid(0), + m_axi_rlast(0) => m_axi_rlast(0), + m_axi_rready(0) => m_axi_rready(0), + m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0), + m_axi_ruser(0) => '0', + m_axi_rvalid(0) => m_axi_rvalid(0), + m_axi_wdata(63 downto 0) => m_axi_wdata(63 downto 0), + m_axi_wid(0) => NLW_inst_m_axi_wid_UNCONNECTED(0), + m_axi_wlast(0) => m_axi_wlast(0), + m_axi_wready(0) => m_axi_wready(0), + m_axi_wstrb(7 downto 0) => m_axi_wstrb(7 downto 0), + m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0), + m_axi_wvalid(0) => m_axi_wvalid(0), + s_axi_araddr(63 downto 0) => s_axi_araddr(63 downto 0), + s_axi_arburst(3 downto 0) => s_axi_arburst(3 downto 0), + s_axi_arcache(7 downto 0) => s_axi_arcache(7 downto 0), + s_axi_arid(1 downto 0) => s_axi_arid(1 downto 0), + s_axi_arlen(15 downto 0) => s_axi_arlen(15 downto 0), + s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0), + s_axi_arprot(5 downto 0) => s_axi_arprot(5 downto 0), + s_axi_arqos(7 downto 0) => s_axi_arqos(7 downto 0), + s_axi_arready(1 downto 0) => s_axi_arready(1 downto 0), + s_axi_arsize(5 downto 0) => s_axi_arsize(5 downto 0), + s_axi_aruser(1 downto 0) => B"00", + s_axi_arvalid(1 downto 0) => s_axi_arvalid(1 downto 0), + s_axi_awaddr(63 downto 0) => s_axi_awaddr(63 downto 0), + s_axi_awburst(3 downto 0) => s_axi_awburst(3 downto 0), + s_axi_awcache(7 downto 0) => s_axi_awcache(7 downto 0), + s_axi_awid(1 downto 0) => s_axi_awid(1 downto 0), + s_axi_awlen(15 downto 0) => s_axi_awlen(15 downto 0), + s_axi_awlock(1 downto 0) => s_axi_awlock(1 downto 0), + s_axi_awprot(5 downto 0) => s_axi_awprot(5 downto 0), + s_axi_awqos(7 downto 0) => s_axi_awqos(7 downto 0), + s_axi_awready(1 downto 0) => s_axi_awready(1 downto 0), + s_axi_awsize(5 downto 0) => s_axi_awsize(5 downto 0), + s_axi_awuser(1 downto 0) => B"00", + s_axi_awvalid(1 downto 0) => s_axi_awvalid(1 downto 0), + s_axi_bid(1 downto 0) => s_axi_bid(1 downto 0), + s_axi_bready(1 downto 0) => s_axi_bready(1 downto 0), + s_axi_bresp(3 downto 0) => s_axi_bresp(3 downto 0), + s_axi_buser(1 downto 0) => NLW_inst_s_axi_buser_UNCONNECTED(1 downto 0), + s_axi_bvalid(1 downto 0) => s_axi_bvalid(1 downto 0), + s_axi_rdata(127 downto 0) => s_axi_rdata(127 downto 0), + s_axi_rid(1 downto 0) => s_axi_rid(1 downto 0), + s_axi_rlast(1 downto 0) => s_axi_rlast(1 downto 0), + s_axi_rready(1 downto 0) => s_axi_rready(1 downto 0), + s_axi_rresp(3 downto 0) => s_axi_rresp(3 downto 0), + s_axi_ruser(1 downto 0) => NLW_inst_s_axi_ruser_UNCONNECTED(1 downto 0), + s_axi_rvalid(1 downto 0) => s_axi_rvalid(1 downto 0), + s_axi_wdata(127 downto 0) => s_axi_wdata(127 downto 0), + s_axi_wid(1 downto 0) => B"00", + s_axi_wlast(1 downto 0) => s_axi_wlast(1 downto 0), + s_axi_wready(1 downto 0) => s_axi_wready(1 downto 0), + s_axi_wstrb(15 downto 0) => s_axi_wstrb(15 downto 0), + s_axi_wuser(1 downto 0) => B"00", + s_axi_wvalid(1 downto 0) => s_axi_wvalid(1 downto 0) + ); +end STRUCTURE; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_1/Arty_Z7_20_xbar_1_stub.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_1/Arty_Z7_20_xbar_1_stub.v new file mode 100644 index 0000000..1cf6a2f --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_1/Arty_Z7_20_xbar_1_stub.v @@ -0,0 +1,109 @@ +// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +// Date : Sat Mar 04 18:57:49 2017 +// Host : WK73 running 64-bit Service Pack 1 (build 7601) +// Command : write_verilog -force -mode synth_stub -rename_top Arty_Z7_20_xbar_1 -prefix +// Arty_Z7_20_xbar_1_ Arty_Z7_20_xbar_1_stub.v +// Design : Arty_Z7_20_xbar_1 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z020clg400-1 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4" *) +module Arty_Z7_20_xbar_1(aclk, aresetn, s_axi_awid, s_axi_awaddr, + s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot, + s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast, + s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid, + s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, + s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp, + s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize, + m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion, m_axi_awqos, + m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid, + m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_arid, m_axi_araddr, + m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot, + m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata, + m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready) +/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[1:0],s_axi_awaddr[63:0],s_axi_awlen[15:0],s_axi_awsize[5:0],s_axi_awburst[3:0],s_axi_awlock[1:0],s_axi_awcache[7:0],s_axi_awprot[5:0],s_axi_awqos[7:0],s_axi_awvalid[1:0],s_axi_awready[1:0],s_axi_wdata[127:0],s_axi_wstrb[15:0],s_axi_wlast[1:0],s_axi_wvalid[1:0],s_axi_wready[1:0],s_axi_bid[1:0],s_axi_bresp[3:0],s_axi_bvalid[1:0],s_axi_bready[1:0],s_axi_arid[1:0],s_axi_araddr[63:0],s_axi_arlen[15:0],s_axi_arsize[5:0],s_axi_arburst[3:0],s_axi_arlock[1:0],s_axi_arcache[7:0],s_axi_arprot[5:0],s_axi_arqos[7:0],s_axi_arvalid[1:0],s_axi_arready[1:0],s_axi_rid[1:0],s_axi_rdata[127:0],s_axi_rresp[3:0],s_axi_rlast[1:0],s_axi_rvalid[1:0],s_axi_rready[1:0],m_axi_awid[0:0],m_axi_awaddr[31:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[0:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awregion[3:0],m_axi_awqos[3:0],m_axi_awvalid[0:0],m_axi_awready[0:0],m_axi_wdata[63:0],m_axi_wstrb[7:0],m_axi_wlast[0:0],m_axi_wvalid[0:0],m_axi_wready[0:0],m_axi_bid[0:0],m_axi_bresp[1:0],m_axi_bvalid[0:0],m_axi_bready[0:0],m_axi_arid[0:0],m_axi_araddr[31:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[0:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arregion[3:0],m_axi_arqos[3:0],m_axi_arvalid[0:0],m_axi_arready[0:0],m_axi_rid[0:0],m_axi_rdata[63:0],m_axi_rresp[1:0],m_axi_rlast[0:0],m_axi_rvalid[0:0],m_axi_rready[0:0]" */; + input aclk; + input aresetn; + input [1:0]s_axi_awid; + input [63:0]s_axi_awaddr; + input [15:0]s_axi_awlen; + input [5:0]s_axi_awsize; + input [3:0]s_axi_awburst; + input [1:0]s_axi_awlock; + input [7:0]s_axi_awcache; + input [5:0]s_axi_awprot; + input [7:0]s_axi_awqos; + input [1:0]s_axi_awvalid; + output [1:0]s_axi_awready; + input [127:0]s_axi_wdata; + input [15:0]s_axi_wstrb; + input [1:0]s_axi_wlast; + input [1:0]s_axi_wvalid; + output [1:0]s_axi_wready; + output [1:0]s_axi_bid; + output [3:0]s_axi_bresp; + output [1:0]s_axi_bvalid; + input [1:0]s_axi_bready; + input [1:0]s_axi_arid; + input [63:0]s_axi_araddr; + input [15:0]s_axi_arlen; + input [5:0]s_axi_arsize; + input [3:0]s_axi_arburst; + input [1:0]s_axi_arlock; + input [7:0]s_axi_arcache; + input [5:0]s_axi_arprot; + input [7:0]s_axi_arqos; + input [1:0]s_axi_arvalid; + output [1:0]s_axi_arready; + output [1:0]s_axi_rid; + output [127:0]s_axi_rdata; + output [3:0]s_axi_rresp; + output [1:0]s_axi_rlast; + output [1:0]s_axi_rvalid; + input [1:0]s_axi_rready; + output [0:0]m_axi_awid; + output [31:0]m_axi_awaddr; + output [7:0]m_axi_awlen; + output [2:0]m_axi_awsize; + output [1:0]m_axi_awburst; + output [0:0]m_axi_awlock; + output [3:0]m_axi_awcache; + output [2:0]m_axi_awprot; + output [3:0]m_axi_awregion; + output [3:0]m_axi_awqos; + output [0:0]m_axi_awvalid; + input [0:0]m_axi_awready; + output [63:0]m_axi_wdata; + output [7:0]m_axi_wstrb; + output [0:0]m_axi_wlast; + output [0:0]m_axi_wvalid; + input [0:0]m_axi_wready; + input [0:0]m_axi_bid; + input [1:0]m_axi_bresp; + input [0:0]m_axi_bvalid; + output [0:0]m_axi_bready; + output [0:0]m_axi_arid; + output [31:0]m_axi_araddr; + output [7:0]m_axi_arlen; + output [2:0]m_axi_arsize; + output [1:0]m_axi_arburst; + output [0:0]m_axi_arlock; + output [3:0]m_axi_arcache; + output [2:0]m_axi_arprot; + output [3:0]m_axi_arregion; + output [3:0]m_axi_arqos; + output [0:0]m_axi_arvalid; + input [0:0]m_axi_arready; + input [0:0]m_axi_rid; + input [63:0]m_axi_rdata; + input [1:0]m_axi_rresp; + input [0:0]m_axi_rlast; + input [0:0]m_axi_rvalid; + output [0:0]m_axi_rready; +endmodule diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_1/Arty_Z7_20_xbar_1_stub.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_1/Arty_Z7_20_xbar_1_stub.vhdl new file mode 100644 index 0000000..13b8906 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_1/Arty_Z7_20_xbar_1_stub.vhdl @@ -0,0 +1,107 @@ +-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 +-- Date : Sat Mar 04 18:57:49 2017 +-- Host : WK73 running 64-bit Service Pack 1 (build 7601) +-- Command : write_vhdl -force -mode synth_stub -rename_top Arty_Z7_20_xbar_1 -prefix +-- Arty_Z7_20_xbar_1_ Arty_Z7_20_xbar_1_stub.vhdl +-- Design : Arty_Z7_20_xbar_1 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z020clg400-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Arty_Z7_20_xbar_1 is + Port ( + aclk : in STD_LOGIC; + aresetn : in STD_LOGIC; + s_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 15 downto 0 ); + s_axi_awsize : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_awburst : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awcache : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_awqos : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_awvalid : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awready : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 ); + s_axi_wlast : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_wvalid : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_wready : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bid : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bresp : out STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_bvalid : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bready : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axi_arlen : in STD_LOGIC_VECTOR ( 15 downto 0 ); + s_axi_arsize : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_arburst : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arcache : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_arprot : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_arqos : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_arvalid : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arready : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rid : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_rlast : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rvalid : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rready : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_rready : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + +end Arty_Z7_20_xbar_1; + +architecture stub of Arty_Z7_20_xbar_1 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awid[1:0],s_axi_awaddr[63:0],s_axi_awlen[15:0],s_axi_awsize[5:0],s_axi_awburst[3:0],s_axi_awlock[1:0],s_axi_awcache[7:0],s_axi_awprot[5:0],s_axi_awqos[7:0],s_axi_awvalid[1:0],s_axi_awready[1:0],s_axi_wdata[127:0],s_axi_wstrb[15:0],s_axi_wlast[1:0],s_axi_wvalid[1:0],s_axi_wready[1:0],s_axi_bid[1:0],s_axi_bresp[3:0],s_axi_bvalid[1:0],s_axi_bready[1:0],s_axi_arid[1:0],s_axi_araddr[63:0],s_axi_arlen[15:0],s_axi_arsize[5:0],s_axi_arburst[3:0],s_axi_arlock[1:0],s_axi_arcache[7:0],s_axi_arprot[5:0],s_axi_arqos[7:0],s_axi_arvalid[1:0],s_axi_arready[1:0],s_axi_rid[1:0],s_axi_rdata[127:0],s_axi_rresp[3:0],s_axi_rlast[1:0],s_axi_rvalid[1:0],s_axi_rready[1:0],m_axi_awid[0:0],m_axi_awaddr[31:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[0:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awregion[3:0],m_axi_awqos[3:0],m_axi_awvalid[0:0],m_axi_awready[0:0],m_axi_wdata[63:0],m_axi_wstrb[7:0],m_axi_wlast[0:0],m_axi_wvalid[0:0],m_axi_wready[0:0],m_axi_bid[0:0],m_axi_bresp[1:0],m_axi_bvalid[0:0],m_axi_bready[0:0],m_axi_arid[0:0],m_axi_araddr[31:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[0:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arregion[3:0],m_axi_arqos[3:0],m_axi_arvalid[0:0],m_axi_arready[0:0],m_axi_rid[0:0],m_axi_rdata[63:0],m_axi_rresp[1:0],m_axi_rlast[0:0],m_axi_rvalid[0:0],m_axi_rready[0:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4"; +begin +end; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_1/sim/Arty_Z7_20_xbar_1.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_1/sim/Arty_Z7_20_xbar_1.v new file mode 100644 index 0000000..4a202ef --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_1/sim/Arty_Z7_20_xbar_1.v @@ -0,0 +1,416 @@ +// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:axi_crossbar:2.1 +// IP Revision: 12 + +`timescale 1ns/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module Arty_Z7_20_xbar_1 ( + aclk, + aresetn, + s_axi_awid, + s_axi_awaddr, + s_axi_awlen, + s_axi_awsize, + s_axi_awburst, + s_axi_awlock, + s_axi_awcache, + s_axi_awprot, + s_axi_awqos, + s_axi_awvalid, + s_axi_awready, + s_axi_wdata, + s_axi_wstrb, + s_axi_wlast, + s_axi_wvalid, + s_axi_wready, + s_axi_bid, + s_axi_bresp, + s_axi_bvalid, + s_axi_bready, + s_axi_arid, + s_axi_araddr, + s_axi_arlen, + s_axi_arsize, + s_axi_arburst, + s_axi_arlock, + s_axi_arcache, + s_axi_arprot, + s_axi_arqos, + s_axi_arvalid, + s_axi_arready, + s_axi_rid, + s_axi_rdata, + s_axi_rresp, + s_axi_rlast, + s_axi_rvalid, + s_axi_rready, + m_axi_awid, + m_axi_awaddr, + m_axi_awlen, + m_axi_awsize, + m_axi_awburst, + m_axi_awlock, + m_axi_awcache, + m_axi_awprot, + m_axi_awregion, + m_axi_awqos, + m_axi_awvalid, + m_axi_awready, + m_axi_wdata, + m_axi_wstrb, + m_axi_wlast, + m_axi_wvalid, + m_axi_wready, + m_axi_bid, + m_axi_bresp, + m_axi_bvalid, + m_axi_bready, + m_axi_arid, + m_axi_araddr, + m_axi_arlen, + m_axi_arsize, + m_axi_arburst, + m_axi_arlock, + m_axi_arcache, + m_axi_arprot, + m_axi_arregion, + m_axi_arqos, + m_axi_arvalid, + m_axi_arready, + m_axi_rid, + m_axi_rdata, + m_axi_rresp, + m_axi_rlast, + m_axi_rvalid, + m_axi_rready +); + +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) +input wire aclk; +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) +input wire aresetn; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWID [0:0] [1:1]" *) +input wire [1 : 0] s_axi_awid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI AWADDR [31:0] [63:32]" *) +input wire [63 : 0] s_axi_awaddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLEN [7:0] [15:8]" *) +input wire [15 : 0] s_axi_awlen; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE [2:0] [5:3]" *) +input wire [5 : 0] s_axi_awsize; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI AWBURST [1:0] [3:2]" *) +input wire [3 : 0] s_axi_awburst; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK [0:0] [1:1]" *) +input wire [1 : 0] s_axi_awlock; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE [3:0] [7:4]" *) +input wire [7 : 0] s_axi_awcache; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWPROT [2:0] [5:3]" *) +input wire [5 : 0] s_axi_awprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWQOS [3:0] [7:4]" *) +input wire [7 : 0] s_axi_awqos; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWVALID [0:0] [1:1]" *) +input wire [1 : 0] s_axi_awvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWREADY [0:0] [1:1]" *) +output wire [1 : 0] s_axi_awready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI WDATA [63:0] [127:64]" *) +input wire [127 : 0] s_axi_wdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI WSTRB [7:0] [15:8]" *) +input wire [15 : 0] s_axi_wstrb; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WLAST [0:0] [1:1]" *) +input wire [1 : 0] s_axi_wlast; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WVALID [0:0] [1:1]" *) +input wire [1 : 0] s_axi_wvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WREADY [0:0] [1:1]" *) +output wire [1 : 0] s_axi_wready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BID [0:0] [1:1]" *) +output wire [1 : 0] s_axi_bid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI BRESP [1:0] [3:2]" *) +output wire [3 : 0] s_axi_bresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BVALID [0:0] [1:1]" *) +output wire [1 : 0] s_axi_bvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BREADY [0:0] [1:1]" *) +input wire [1 : 0] s_axi_bready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARID [0:0] [1:1]" *) +input wire [1 : 0] s_axi_arid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI ARADDR [31:0] [63:32]" *) +input wire [63 : 0] s_axi_araddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLEN [7:0] [15:8]" *) +input wire [15 : 0] s_axi_arlen; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE [2:0] [5:3]" *) +input wire [5 : 0] s_axi_arsize; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI ARBURST [1:0] [3:2]" *) +input wire [3 : 0] s_axi_arburst; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK [0:0] [1:1]" *) +input wire [1 : 0] s_axi_arlock; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE [3:0] [7:4]" *) +input wire [7 : 0] s_axi_arcache; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARPROT [2:0] [5:3]" *) +input wire [5 : 0] s_axi_arprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARQOS [3:0] [7:4]" *) +input wire [7 : 0] s_axi_arqos; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARVALID [0:0] [1:1]" *) +input wire [1 : 0] s_axi_arvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARREADY [0:0] [1:1]" *) +output wire [1 : 0] s_axi_arready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RID [0:0] [1:1]" *) +output wire [1 : 0] s_axi_rid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI RDATA [63:0] [127:64]" *) +output wire [127 : 0] s_axi_rdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI RRESP [1:0] [3:2]" *) +output wire [3 : 0] s_axi_rresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RLAST [0:0] [1:1]" *) +output wire [1 : 0] s_axi_rlast; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RVALID [0:0] [1:1]" *) +output wire [1 : 0] s_axi_rvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RREADY [0:0] [1:1]" *) +input wire [1 : 0] s_axi_rready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWID" *) +output wire [0 : 0] m_axi_awid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR" *) +output wire [31 : 0] m_axi_awaddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN" *) +output wire [7 : 0] m_axi_awlen; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE" *) +output wire [2 : 0] m_axi_awsize; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST" *) +output wire [1 : 0] m_axi_awburst; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK" *) +output wire [0 : 0] m_axi_awlock; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE" *) +output wire [3 : 0] m_axi_awcache; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT" *) +output wire [2 : 0] m_axi_awprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION" *) +output wire [3 : 0] m_axi_awregion; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS" *) +output wire [3 : 0] m_axi_awqos; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID" *) +output wire [0 : 0] m_axi_awvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY" *) +input wire [0 : 0] m_axi_awready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA" *) +output wire [63 : 0] m_axi_wdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB" *) +output wire [7 : 0] m_axi_wstrb; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST" *) +output wire [0 : 0] m_axi_wlast; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID" *) +output wire [0 : 0] m_axi_wvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY" *) +input wire [0 : 0] m_axi_wready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BID" *) +input wire [0 : 0] m_axi_bid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP" *) +input wire [1 : 0] m_axi_bresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID" *) +input wire [0 : 0] m_axi_bvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY" *) +output wire [0 : 0] m_axi_bready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARID" *) +output wire [0 : 0] m_axi_arid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR" *) +output wire [31 : 0] m_axi_araddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN" *) +output wire [7 : 0] m_axi_arlen; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE" *) +output wire [2 : 0] m_axi_arsize; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST" *) +output wire [1 : 0] m_axi_arburst; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK" *) +output wire [0 : 0] m_axi_arlock; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE" *) +output wire [3 : 0] m_axi_arcache; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT" *) +output wire [2 : 0] m_axi_arprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION" *) +output wire [3 : 0] m_axi_arregion; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS" *) +output wire [3 : 0] m_axi_arqos; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID" *) +output wire [0 : 0] m_axi_arvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY" *) +input wire [0 : 0] m_axi_arready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RID" *) +input wire [0 : 0] m_axi_rid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA" *) +input wire [63 : 0] m_axi_rdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP" *) +input wire [1 : 0] m_axi_rresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST" *) +input wire [0 : 0] m_axi_rlast; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID" *) +input wire [0 : 0] m_axi_rvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY" *) +output wire [0 : 0] m_axi_rready; + + axi_crossbar_v2_1_12_axi_crossbar #( + .C_FAMILY("zynq"), + .C_NUM_SLAVE_SLOTS(2), + .C_NUM_MASTER_SLOTS(1), + .C_AXI_ID_WIDTH(1), + .C_AXI_ADDR_WIDTH(32), + .C_AXI_DATA_WIDTH(64), + .C_AXI_PROTOCOL(0), + .C_NUM_ADDR_RANGES(1), + .C_M_AXI_BASE_ADDR(64'H0000000000000000), + .C_M_AXI_ADDR_WIDTH(32'H0000001d), + .C_S_AXI_BASE_ID(64'H0000000100000000), + .C_S_AXI_THREAD_ID_WIDTH(64'H0000000000000000), + .C_AXI_SUPPORTS_USER_SIGNALS(0), + .C_AXI_AWUSER_WIDTH(1), + .C_AXI_ARUSER_WIDTH(1), + .C_AXI_WUSER_WIDTH(1), + .C_AXI_RUSER_WIDTH(1), + .C_AXI_BUSER_WIDTH(1), + .C_M_AXI_WRITE_CONNECTIVITY(32'H00000002), + .C_M_AXI_READ_CONNECTIVITY(32'H00000001), + .C_R_REGISTER(0), + .C_S_AXI_SINGLE_THREAD(64'H0000000000000000), + .C_S_AXI_WRITE_ACCEPTANCE(64'H0000000200000002), + .C_S_AXI_READ_ACCEPTANCE(64'H0000000200000002), + .C_M_AXI_WRITE_ISSUING(32'H00000008), + .C_M_AXI_READ_ISSUING(32'H00000008), + .C_S_AXI_ARB_PRIORITY(64'H0000000000000000), + .C_M_AXI_SECURE(32'H00000000), + .C_CONNECTIVITY_MODE(1) + ) inst ( + .aclk(aclk), + .aresetn(aresetn), + .s_axi_awid(s_axi_awid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awlen(s_axi_awlen), + .s_axi_awsize(s_axi_awsize), + .s_axi_awburst(s_axi_awburst), + .s_axi_awlock(s_axi_awlock), + .s_axi_awcache(s_axi_awcache), + .s_axi_awprot(s_axi_awprot), + .s_axi_awqos(s_axi_awqos), + .s_axi_awuser(2'H0), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_awready(s_axi_awready), + .s_axi_wid(2'H0), + .s_axi_wdata(s_axi_wdata), + .s_axi_wstrb(s_axi_wstrb), + .s_axi_wlast(s_axi_wlast), + .s_axi_wuser(2'H0), + .s_axi_wvalid(s_axi_wvalid), + .s_axi_wready(s_axi_wready), + .s_axi_bid(s_axi_bid), + .s_axi_bresp(s_axi_bresp), + .s_axi_buser(), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_bready(s_axi_bready), + .s_axi_arid(s_axi_arid), + .s_axi_araddr(s_axi_araddr), + .s_axi_arlen(s_axi_arlen), + .s_axi_arsize(s_axi_arsize), + .s_axi_arburst(s_axi_arburst), + .s_axi_arlock(s_axi_arlock), + .s_axi_arcache(s_axi_arcache), + .s_axi_arprot(s_axi_arprot), + .s_axi_arqos(s_axi_arqos), + .s_axi_aruser(2'H0), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_arready(s_axi_arready), + .s_axi_rid(s_axi_rid), + .s_axi_rdata(s_axi_rdata), + .s_axi_rresp(s_axi_rresp), + .s_axi_rlast(s_axi_rlast), + .s_axi_ruser(), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_rready(s_axi_rready), + .m_axi_awid(m_axi_awid), + .m_axi_awaddr(m_axi_awaddr), + .m_axi_awlen(m_axi_awlen), + .m_axi_awsize(m_axi_awsize), + .m_axi_awburst(m_axi_awburst), + .m_axi_awlock(m_axi_awlock), + .m_axi_awcache(m_axi_awcache), + .m_axi_awprot(m_axi_awprot), + .m_axi_awregion(m_axi_awregion), + .m_axi_awqos(m_axi_awqos), + .m_axi_awuser(), + .m_axi_awvalid(m_axi_awvalid), + .m_axi_awready(m_axi_awready), + .m_axi_wid(), + .m_axi_wdata(m_axi_wdata), + .m_axi_wstrb(m_axi_wstrb), + .m_axi_wlast(m_axi_wlast), + .m_axi_wuser(), + .m_axi_wvalid(m_axi_wvalid), + .m_axi_wready(m_axi_wready), + .m_axi_bid(m_axi_bid), + .m_axi_bresp(m_axi_bresp), + .m_axi_buser(1'H0), + .m_axi_bvalid(m_axi_bvalid), + .m_axi_bready(m_axi_bready), + .m_axi_arid(m_axi_arid), + .m_axi_araddr(m_axi_araddr), + .m_axi_arlen(m_axi_arlen), + .m_axi_arsize(m_axi_arsize), + .m_axi_arburst(m_axi_arburst), + .m_axi_arlock(m_axi_arlock), + .m_axi_arcache(m_axi_arcache), + .m_axi_arprot(m_axi_arprot), + .m_axi_arregion(m_axi_arregion), + .m_axi_arqos(m_axi_arqos), + .m_axi_aruser(), + .m_axi_arvalid(m_axi_arvalid), + .m_axi_arready(m_axi_arready), + .m_axi_rid(m_axi_rid), + .m_axi_rdata(m_axi_rdata), + .m_axi_rresp(m_axi_rresp), + .m_axi_rlast(m_axi_rlast), + .m_axi_ruser(1'H0), + .m_axi_rvalid(m_axi_rvalid), + .m_axi_rready(m_axi_rready) + ); +endmodule diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_1/synth/Arty_Z7_20_xbar_1.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_1/synth/Arty_Z7_20_xbar_1.v new file mode 100644 index 0000000..52ea9b0 --- /dev/null +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xbar_1/synth/Arty_Z7_20_xbar_1.v @@ -0,0 +1,419 @@ +// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:axi_crossbar:2.1 +// IP Revision: 12 + +(* X_CORE_INFO = "axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4" *) +(* CHECK_LICENSE_TYPE = "Arty_Z7_20_xbar_1,axi_crossbar_v2_1_12_axi_crossbar,{}" *) +(* CORE_GENERATION_INFO = "Arty_Z7_20_xbar_1,axi_crossbar_v2_1_12_axi_crossbar,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_crossbar,x_ipVersion=2.1,x_ipCoreRevision=12,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_NUM_SLAVE_SLOTS=2,C_NUM_MASTER_SLOTS=1,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_PROTOCOL=0,C_NUM_ADDR_RANGES=1,C_M_AXI_BASE_ADDR=0x0000000000000000,C_M_AXI_ADDR_WIDTH=0x0000001d,C_S_AXI_BASE_ID=0x0000000100000000,C_S_AXI_THREAD_ID_WIDTH=0x000000000\ +0000000,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_M_AXI_WRITE_CONNECTIVITY=0x00000002,C_M_AXI_READ_CONNECTIVITY=0x00000001,C_R_REGISTER=0,C_S_AXI_SINGLE_THREAD=0x0000000000000000,C_S_AXI_WRITE_ACCEPTANCE=0x0000000200000002,C_S_AXI_READ_ACCEPTANCE=0x0000000200000002,C_M_AXI_WRITE_ISSUING=0x00000008,C_M_AXI_READ_ISSUING=0x00000008,C_S_AXI_ARB_PRIORITY=0x0000000000000000,C_M_AXI_SECURE=0x00000000,C_CONNECTIV\ +ITY_MODE=1}" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module Arty_Z7_20_xbar_1 ( + aclk, + aresetn, + s_axi_awid, + s_axi_awaddr, + s_axi_awlen, + s_axi_awsize, + s_axi_awburst, + s_axi_awlock, + s_axi_awcache, + s_axi_awprot, + s_axi_awqos, + s_axi_awvalid, + s_axi_awready, + s_axi_wdata, + s_axi_wstrb, + s_axi_wlast, + s_axi_wvalid, + s_axi_wready, + s_axi_bid, + s_axi_bresp, + s_axi_bvalid, + s_axi_bready, + s_axi_arid, + s_axi_araddr, + s_axi_arlen, + s_axi_arsize, + s_axi_arburst, + s_axi_arlock, + s_axi_arcache, + s_axi_arprot, + s_axi_arqos, + s_axi_arvalid, + s_axi_arready, + s_axi_rid, + s_axi_rdata, + s_axi_rresp, + s_axi_rlast, + s_axi_rvalid, + s_axi_rready, + m_axi_awid, + m_axi_awaddr, + m_axi_awlen, + m_axi_awsize, + m_axi_awburst, + m_axi_awlock, + m_axi_awcache, + m_axi_awprot, + m_axi_awregion, + m_axi_awqos, + m_axi_awvalid, + m_axi_awready, + m_axi_wdata, + m_axi_wstrb, + m_axi_wlast, + m_axi_wvalid, + m_axi_wready, + m_axi_bid, + m_axi_bresp, + m_axi_bvalid, + m_axi_bready, + m_axi_arid, + m_axi_araddr, + m_axi_arlen, + m_axi_arsize, + m_axi_arburst, + m_axi_arlock, + m_axi_arcache, + m_axi_arprot, + m_axi_arregion, + m_axi_arqos, + m_axi_arvalid, + m_axi_arready, + m_axi_rid, + m_axi_rdata, + m_axi_rresp, + m_axi_rlast, + m_axi_rvalid, + m_axi_rready +); + +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) +input wire aclk; +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) +input wire aresetn; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWID [0:0] [1:1]" *) +input wire [1 : 0] s_axi_awid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI AWADDR [31:0] [63:32]" *) +input wire [63 : 0] s_axi_awaddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLEN [7:0] [15:8]" *) +input wire [15 : 0] s_axi_awlen; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE [2:0] [5:3]" *) +input wire [5 : 0] s_axi_awsize; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI AWBURST [1:0] [3:2]" *) +input wire [3 : 0] s_axi_awburst; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK [0:0] [1:1]" *) +input wire [1 : 0] s_axi_awlock; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE [3:0] [7:4]" *) +input wire [7 : 0] s_axi_awcache; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWPROT [2:0] [5:3]" *) +input wire [5 : 0] s_axi_awprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWQOS [3:0] [7:4]" *) +input wire [7 : 0] s_axi_awqos; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWVALID [0:0] [1:1]" *) +input wire [1 : 0] s_axi_awvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWREADY [0:0] [1:1]" *) +output wire [1 : 0] s_axi_awready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI WDATA [63:0] [127:64]" *) +input wire [127 : 0] s_axi_wdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI WSTRB [7:0] [15:8]" *) +input wire [15 : 0] s_axi_wstrb; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WLAST [0:0] [1:1]" *) +input wire [1 : 0] s_axi_wlast; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WVALID [0:0] [1:1]" *) +input wire [1 : 0] s_axi_wvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WREADY [0:0] [1:1]" *) +output wire [1 : 0] s_axi_wready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BID [0:0] [1:1]" *) +output wire [1 : 0] s_axi_bid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI BRESP [1:0] [3:2]" *) +output wire [3 : 0] s_axi_bresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BVALID [0:0] [1:1]" *) +output wire [1 : 0] s_axi_bvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BREADY [0:0] [1:1]" *) +input wire [1 : 0] s_axi_bready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARID [0:0] [1:1]" *) +input wire [1 : 0] s_axi_arid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI ARADDR [31:0] [63:32]" *) +input wire [63 : 0] s_axi_araddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLEN [7:0] [15:8]" *) +input wire [15 : 0] s_axi_arlen; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE [2:0] [5:3]" *) +input wire [5 : 0] s_axi_arsize; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI ARBURST [1:0] [3:2]" *) +input wire [3 : 0] s_axi_arburst; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK [0:0] [1:1]" *) +input wire [1 : 0] s_axi_arlock; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE [3:0] [7:4]" *) +input wire [7 : 0] s_axi_arcache; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARPROT [2:0] [5:3]" *) +input wire [5 : 0] s_axi_arprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARQOS [3:0] [7:4]" *) +input wire [7 : 0] s_axi_arqos; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARVALID [0:0] [1:1]" *) +input wire [1 : 0] s_axi_arvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARREADY [0:0] [1:1]" *) +output wire [1 : 0] s_axi_arready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RID [0:0] [1:1]" *) +output wire [1 : 0] s_axi_rid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI RDATA [63:0] [127:64]" *) +output wire [127 : 0] s_axi_rdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI RRESP [1:0] [3:2]" *) +output wire [3 : 0] s_axi_rresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RLAST [0:0] [1:1]" *) +output wire [1 : 0] s_axi_rlast; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RVALID [0:0] [1:1]" *) +output wire [1 : 0] s_axi_rvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RREADY [0:0] [1:1]" *) +input wire [1 : 0] s_axi_rready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWID" *) +output wire [0 : 0] m_axi_awid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR" *) +output wire [31 : 0] m_axi_awaddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN" *) +output wire [7 : 0] m_axi_awlen; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE" *) +output wire [2 : 0] m_axi_awsize; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST" *) +output wire [1 : 0] m_axi_awburst; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK" *) +output wire [0 : 0] m_axi_awlock; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE" *) +output wire [3 : 0] m_axi_awcache; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT" *) +output wire [2 : 0] m_axi_awprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION" *) +output wire [3 : 0] m_axi_awregion; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS" *) +output wire [3 : 0] m_axi_awqos; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID" *) +output wire [0 : 0] m_axi_awvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY" *) +input wire [0 : 0] m_axi_awready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA" *) +output wire [63 : 0] m_axi_wdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB" *) +output wire [7 : 0] m_axi_wstrb; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST" *) +output wire [0 : 0] m_axi_wlast; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID" *) +output wire [0 : 0] m_axi_wvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY" *) +input wire [0 : 0] m_axi_wready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BID" *) +input wire [0 : 0] m_axi_bid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP" *) +input wire [1 : 0] m_axi_bresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID" *) +input wire [0 : 0] m_axi_bvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY" *) +output wire [0 : 0] m_axi_bready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARID" *) +output wire [0 : 0] m_axi_arid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR" *) +output wire [31 : 0] m_axi_araddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN" *) +output wire [7 : 0] m_axi_arlen; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE" *) +output wire [2 : 0] m_axi_arsize; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST" *) +output wire [1 : 0] m_axi_arburst; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK" *) +output wire [0 : 0] m_axi_arlock; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE" *) +output wire [3 : 0] m_axi_arcache; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT" *) +output wire [2 : 0] m_axi_arprot; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION" *) +output wire [3 : 0] m_axi_arregion; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS" *) +output wire [3 : 0] m_axi_arqos; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID" *) +output wire [0 : 0] m_axi_arvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY" *) +input wire [0 : 0] m_axi_arready; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RID" *) +input wire [0 : 0] m_axi_rid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA" *) +input wire [63 : 0] m_axi_rdata; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP" *) +input wire [1 : 0] m_axi_rresp; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST" *) +input wire [0 : 0] m_axi_rlast; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID" *) +input wire [0 : 0] m_axi_rvalid; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY" *) +output wire [0 : 0] m_axi_rready; + + axi_crossbar_v2_1_12_axi_crossbar #( + .C_FAMILY("zynq"), + .C_NUM_SLAVE_SLOTS(2), + .C_NUM_MASTER_SLOTS(1), + .C_AXI_ID_WIDTH(1), + .C_AXI_ADDR_WIDTH(32), + .C_AXI_DATA_WIDTH(64), + .C_AXI_PROTOCOL(0), + .C_NUM_ADDR_RANGES(1), + .C_M_AXI_BASE_ADDR(64'H0000000000000000), + .C_M_AXI_ADDR_WIDTH(32'H0000001d), + .C_S_AXI_BASE_ID(64'H0000000100000000), + .C_S_AXI_THREAD_ID_WIDTH(64'H0000000000000000), + .C_AXI_SUPPORTS_USER_SIGNALS(0), + .C_AXI_AWUSER_WIDTH(1), + .C_AXI_ARUSER_WIDTH(1), + .C_AXI_WUSER_WIDTH(1), + .C_AXI_RUSER_WIDTH(1), + .C_AXI_BUSER_WIDTH(1), + .C_M_AXI_WRITE_CONNECTIVITY(32'H00000002), + .C_M_AXI_READ_CONNECTIVITY(32'H00000001), + .C_R_REGISTER(0), + .C_S_AXI_SINGLE_THREAD(64'H0000000000000000), + .C_S_AXI_WRITE_ACCEPTANCE(64'H0000000200000002), + .C_S_AXI_READ_ACCEPTANCE(64'H0000000200000002), + .C_M_AXI_WRITE_ISSUING(32'H00000008), + .C_M_AXI_READ_ISSUING(32'H00000008), + .C_S_AXI_ARB_PRIORITY(64'H0000000000000000), + .C_M_AXI_SECURE(32'H00000000), + .C_CONNECTIVITY_MODE(1) + ) inst ( + .aclk(aclk), + .aresetn(aresetn), + .s_axi_awid(s_axi_awid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awlen(s_axi_awlen), + .s_axi_awsize(s_axi_awsize), + .s_axi_awburst(s_axi_awburst), + .s_axi_awlock(s_axi_awlock), + .s_axi_awcache(s_axi_awcache), + .s_axi_awprot(s_axi_awprot), + .s_axi_awqos(s_axi_awqos), + .s_axi_awuser(2'H0), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_awready(s_axi_awready), + .s_axi_wid(2'H0), + .s_axi_wdata(s_axi_wdata), + .s_axi_wstrb(s_axi_wstrb), + .s_axi_wlast(s_axi_wlast), + .s_axi_wuser(2'H0), + .s_axi_wvalid(s_axi_wvalid), + .s_axi_wready(s_axi_wready), + .s_axi_bid(s_axi_bid), + .s_axi_bresp(s_axi_bresp), + .s_axi_buser(), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_bready(s_axi_bready), + .s_axi_arid(s_axi_arid), + .s_axi_araddr(s_axi_araddr), + .s_axi_arlen(s_axi_arlen), + .s_axi_arsize(s_axi_arsize), + .s_axi_arburst(s_axi_arburst), + .s_axi_arlock(s_axi_arlock), + .s_axi_arcache(s_axi_arcache), + .s_axi_arprot(s_axi_arprot), + .s_axi_arqos(s_axi_arqos), + .s_axi_aruser(2'H0), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_arready(s_axi_arready), + .s_axi_rid(s_axi_rid), + .s_axi_rdata(s_axi_rdata), + .s_axi_rresp(s_axi_rresp), + .s_axi_rlast(s_axi_rlast), + .s_axi_ruser(), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_rready(s_axi_rready), + .m_axi_awid(m_axi_awid), + .m_axi_awaddr(m_axi_awaddr), + .m_axi_awlen(m_axi_awlen), + .m_axi_awsize(m_axi_awsize), + .m_axi_awburst(m_axi_awburst), + .m_axi_awlock(m_axi_awlock), + .m_axi_awcache(m_axi_awcache), + .m_axi_awprot(m_axi_awprot), + .m_axi_awregion(m_axi_awregion), + .m_axi_awqos(m_axi_awqos), + .m_axi_awuser(), + .m_axi_awvalid(m_axi_awvalid), + .m_axi_awready(m_axi_awready), + .m_axi_wid(), + .m_axi_wdata(m_axi_wdata), + .m_axi_wstrb(m_axi_wstrb), + .m_axi_wlast(m_axi_wlast), + .m_axi_wuser(), + .m_axi_wvalid(m_axi_wvalid), + .m_axi_wready(m_axi_wready), + .m_axi_bid(m_axi_bid), + .m_axi_bresp(m_axi_bresp), + .m_axi_buser(1'H0), + .m_axi_bvalid(m_axi_bvalid), + .m_axi_bready(m_axi_bready), + .m_axi_arid(m_axi_arid), + .m_axi_araddr(m_axi_araddr), + .m_axi_arlen(m_axi_arlen), + .m_axi_arsize(m_axi_arsize), + .m_axi_arburst(m_axi_arburst), + .m_axi_arlock(m_axi_arlock), + .m_axi_arcache(m_axi_arcache), + .m_axi_arprot(m_axi_arprot), + .m_axi_arregion(m_axi_arregion), + .m_axi_arqos(m_axi_arqos), + .m_axi_aruser(), + .m_axi_arvalid(m_axi_arvalid), + .m_axi_arready(m_axi_arready), + .m_axi_rid(m_axi_rid), + .m_axi_rdata(m_axi_rdata), + .m_axi_rresp(m_axi_rresp), + .m_axi_rlast(m_axi_rlast), + .m_axi_ruser(1'H0), + .m_axi_rvalid(m_axi_rvalid), + .m_axi_rready(m_axi_rready) + ); +endmodule diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0.dcp b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0.dcp index 020f300..f5cfab7 100644 Binary files a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0.dcp and b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0.dcp differ diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0.xci b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0.xci index 9c5c981..420a709 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0.xci +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0.xci @@ -41,8 +41,8 @@ 1 1 1 - 7 - 7 + 8 + 8 Arty_Z7_20_xlconcat_0_0 1 1 @@ -76,8 +76,8 @@ 1 1 1 - 7 - 7 + 8 + 8 zynq digilentinc.com:arty-z7-20:part0:1.0 xc7z020 @@ -108,6 +108,7 @@ + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0.xml b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0.xml index 476c4bf..4d030d7 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0.xml +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0.xml @@ -21,7 +21,7 @@ boundaryCRC - e4e2f846 + e7c5d8c7 boundaryCRCversion @@ -29,7 +29,7 @@ customizationCRC - 323e764d + ab58a5b4 customizationCRCversion @@ -48,11 +48,11 @@ GENtimestamp - Fri Feb 24 23:58:29 UTC 2017 + Sun Mar 05 02:51:33 UTC 2017 boundaryCRC - e4e2f846 + e7c5d8c7 boundaryCRCversion @@ -60,7 +60,7 @@ customizationCRC - 323e764d + ab58a5b4 customizationCRCversion @@ -83,7 +83,7 @@ boundaryCRC - e4e2f846 + e7c5d8c7 boundaryCRCversion @@ -91,7 +91,7 @@ customizationCRC - 2d5fb5ac + 086ed9c3 customizationCRCversion @@ -110,11 +110,11 @@ GENtimestamp - Fri Feb 24 23:58:29 UTC 2017 + Sun Mar 05 02:51:33 UTC 2017 boundaryCRC - e4e2f846 + e7c5d8c7 boundaryCRCversion @@ -122,7 +122,7 @@ customizationCRC - 2d5fb5ac + 086ed9c3 customizationCRCversion @@ -140,11 +140,11 @@ GENtimestamp - Sat Feb 25 00:05:15 UTC 2017 + Sun Mar 05 02:54:05 UTC 2017 boundaryCRC - e4e2f846 + e7c5d8c7 boundaryCRCversion @@ -152,7 +152,7 @@ customizationCRC - 323e764d + ab58a5b4 customizationCRCversion @@ -349,7 +349,7 @@ - false + true @@ -935,7 +935,7 @@ out - 6 + 7 0 @@ -1112,12 +1112,12 @@ dout_width Dout Width - 7 + 8 NUM_PORTS Number of Ports - 7 + 8 @@ -1196,7 +1196,7 @@ NUM_PORTS Number of Ports - 7 + 8 IN0_WIDTH @@ -1365,7 +1365,7 @@ dout_width Dout Width - 7 + 8 @@ -1380,6 +1380,7 @@ + diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0_sim_netlist.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0_sim_netlist.v index 4007e92..a30bcf4 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0_sim_netlist.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0_sim_netlist.v @@ -1,10 +1,10 @@ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -// Date : Fri Feb 24 16:05:15 2017 +// Date : Sat Mar 04 18:54:05 2017 // Host : WK73 running 64-bit Service Pack 1 (build 7601) // Command : write_verilog -force -mode funcsim -// c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0_sim_netlist.v +// C:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0_sim_netlist.v // Design : Arty_Z7_20_xlconcat_0_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -22,6 +22,7 @@ module Arty_Z7_20_xlconcat_0_0 In4, In5, In6, + In7, dout); input [0:0]In0; input [0:0]In1; @@ -30,7 +31,8 @@ module Arty_Z7_20_xlconcat_0_0 input [0:0]In4; input [0:0]In5; input [0:0]In6; - output [6:0]dout; + input [0:0]In7; + output [7:0]dout; wire [0:0]In0; wire [0:0]In1; @@ -39,7 +41,9 @@ module Arty_Z7_20_xlconcat_0_0 wire [0:0]In4; wire [0:0]In5; wire [0:0]In6; + wire [0:0]In7; + assign dout[7] = In7; assign dout[6] = In6; assign dout[5] = In5; assign dout[4] = In4; diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0_sim_netlist.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0_sim_netlist.vhdl index 4116e3a..0a441ae 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0_sim_netlist.vhdl +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0_sim_netlist.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 --- Date : Fri Feb 24 16:05:15 2017 +-- Date : Sat Mar 04 18:54:05 2017 -- Host : WK73 running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim --- c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0_sim_netlist.vhdl +-- C:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0_sim_netlist.vhdl -- Design : Arty_Z7_20_xlconcat_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. @@ -23,7 +23,8 @@ entity Arty_Z7_20_xlconcat_0_0 is In4 : in STD_LOGIC_VECTOR ( 0 to 0 ); In5 : in STD_LOGIC_VECTOR ( 0 to 0 ); In6 : in STD_LOGIC_VECTOR ( 0 to 0 ); - dout : out STD_LOGIC_VECTOR ( 6 downto 0 ) + In7 : in STD_LOGIC_VECTOR ( 0 to 0 ); + dout : out STD_LOGIC_VECTOR ( 7 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of Arty_Z7_20_xlconcat_0_0 : entity is true; @@ -43,6 +44,7 @@ architecture STRUCTURE of Arty_Z7_20_xlconcat_0_0 is signal \^in4\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^in5\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^in6\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^in7\ : STD_LOGIC_VECTOR ( 0 to 0 ); begin \^in0\(0) <= In0(0); \^in1\(0) <= In1(0); @@ -51,6 +53,8 @@ begin \^in4\(0) <= In4(0); \^in5\(0) <= In5(0); \^in6\(0) <= In6(0); + \^in7\(0) <= In7(0); + dout(7) <= \^in7\(0); dout(6) <= \^in6\(0); dout(5) <= \^in5\(0); dout(4) <= \^in4\(0); diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0_stub.v b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0_stub.v index 893df43..2446540 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0_stub.v +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -// Date : Fri Feb 24 16:05:15 2017 +// Date : Sat Mar 04 18:54:05 2017 // Host : WK73 running 64-bit Service Pack 1 (build 7601) // Command : write_verilog -force -mode synth_stub -// c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0_stub.v +// C:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0_stub.v // Design : Arty_Z7_20_xlconcat_0_0 // Purpose : Stub declaration of top-level module interface // Device : xc7z020clg400-1 @@ -14,8 +14,8 @@ // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. (* x_core_info = "xlconcat,Vivado 2016.4" *) -module Arty_Z7_20_xlconcat_0_0(In0, In1, In2, In3, In4, In5, In6, dout) -/* synthesis syn_black_box black_box_pad_pin="In0[0:0],In1[0:0],In2[0:0],In3[0:0],In4[0:0],In5[0:0],In6[0:0],dout[6:0]" */; +module Arty_Z7_20_xlconcat_0_0(In0, In1, In2, In3, In4, In5, In6, In7, dout) +/* synthesis syn_black_box black_box_pad_pin="In0[0:0],In1[0:0],In2[0:0],In3[0:0],In4[0:0],In5[0:0],In6[0:0],In7[0:0],dout[7:0]" */; input [0:0]In0; input [0:0]In1; input [0:0]In2; @@ -23,5 +23,6 @@ module Arty_Z7_20_xlconcat_0_0(In0, In1, In2, In3, In4, In5, In6, dout) input [0:0]In4; input [0:0]In5; input [0:0]In6; - output [6:0]dout; + input [0:0]In7; + output [7:0]dout; endmodule diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0_stub.vhdl b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0_stub.vhdl index 240085a..027e2a0 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0_stub.vhdl +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 --- Date : Fri Feb 24 16:05:15 2017 +-- Date : Sat Mar 04 18:54:05 2017 -- Host : WK73 running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode synth_stub --- c:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0_stub.vhdl +-- C:/sam_work/git/digilent/Arty-Z7-20-base/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/Arty_Z7_20_xlconcat_0_0_stub.vhdl -- Design : Arty_Z7_20_xlconcat_0_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7z020clg400-1 @@ -21,7 +21,8 @@ entity Arty_Z7_20_xlconcat_0_0 is In4 : in STD_LOGIC_VECTOR ( 0 to 0 ); In5 : in STD_LOGIC_VECTOR ( 0 to 0 ); In6 : in STD_LOGIC_VECTOR ( 0 to 0 ); - dout : out STD_LOGIC_VECTOR ( 6 downto 0 ) + In7 : in STD_LOGIC_VECTOR ( 0 to 0 ); + dout : out STD_LOGIC_VECTOR ( 7 downto 0 ) ); end Arty_Z7_20_xlconcat_0_0; @@ -30,7 +31,7 @@ architecture stub of Arty_Z7_20_xlconcat_0_0 is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "In0[0:0],In1[0:0],In2[0:0],In3[0:0],In4[0:0],In5[0:0],In6[0:0],dout[6:0]"; +attribute black_box_pad_pin of stub : architecture is "In0[0:0],In1[0:0],In2[0:0],In3[0:0],In4[0:0],In5[0:0],In6[0:0],In7[0:0],dout[7:0]"; attribute x_core_info : string; attribute x_core_info of stub : architecture is "xlconcat,Vivado 2016.4"; begin diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/sim/Arty_Z7_20_xlconcat_0_0.vhd b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/sim/Arty_Z7_20_xlconcat_0_0.vhd index 47daafa..a5204b2 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/sim/Arty_Z7_20_xlconcat_0_0.vhd +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/sim/Arty_Z7_20_xlconcat_0_0.vhd @@ -65,7 +65,8 @@ ENTITY Arty_Z7_20_xlconcat_0_0 IS In4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); - dout : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) + In7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END Arty_Z7_20_xlconcat_0_0; @@ -142,7 +143,7 @@ ARCHITECTURE Arty_Z7_20_xlconcat_0_0_arch OF Arty_Z7_20_xlconcat_0_0 IS In29 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In30 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In31 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); - dout : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) + dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT xlconcat; BEGIN @@ -180,8 +181,8 @@ BEGIN IN29_WIDTH => 1, IN30_WIDTH => 1, IN31_WIDTH => 1, - dout_width => 7, - NUM_PORTS => 7 + dout_width => 8, + NUM_PORTS => 8 ) PORT MAP ( In0 => In0, @@ -191,7 +192,7 @@ BEGIN In4 => In4, In5 => In5, In6 => In6, - In7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), + In7 => In7, In8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), diff --git a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/synth/Arty_Z7_20_xlconcat_0_0.vhd b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/synth/Arty_Z7_20_xlconcat_0_0.vhd index 5e7d515..23f12d2 100644 --- a/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/synth/Arty_Z7_20_xlconcat_0_0.vhd +++ b/src/bd/Arty_Z7_20/ip/Arty_Z7_20_xlconcat_0_0/synth/Arty_Z7_20_xlconcat_0_0.vhd @@ -65,7 +65,8 @@ ENTITY Arty_Z7_20_xlconcat_0_0 IS In4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); - dout : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) + In7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END Arty_Z7_20_xlconcat_0_0; @@ -142,7 +143,7 @@ ARCHITECTURE Arty_Z7_20_xlconcat_0_0_arch OF Arty_Z7_20_xlconcat_0_0 IS In29 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In30 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In31 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); - dout : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) + dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT xlconcat; ATTRIBUTE X_CORE_INFO : STRING; @@ -151,7 +152,7 @@ ARCHITECTURE Arty_Z7_20_xlconcat_0_0_arch OF Arty_Z7_20_xlconcat_0_0 IS ATTRIBUTE CHECK_LICENSE_TYPE OF Arty_Z7_20_xlconcat_0_0_arch : ARCHITECTURE IS "Arty_Z7_20_xlconcat_0_0,xlconcat,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF Arty_Z7_20_xlconcat_0_0_arch: ARCHITECTURE IS "Arty_Z7_20_xlconcat_0_0,xlconcat,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH=1,IN24_WID" & -"TH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=7,NUM_PORTS=7}"; +"TH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=8,NUM_PORTS=8}"; BEGIN U0 : xlconcat GENERIC MAP ( @@ -187,8 +188,8 @@ BEGIN IN29_WIDTH => 1, IN30_WIDTH => 1, IN31_WIDTH => 1, - dout_width => 7, - NUM_PORTS => 7 + dout_width => 8, + NUM_PORTS => 8 ) PORT MAP ( In0 => In0, @@ -198,7 +199,7 @@ BEGIN In4 => In4, In5 => In5, In6 => In6, - In7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), + In7 => In7, In8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), diff --git a/src/bd/Arty_Z7_20/ipshared/953b/hdl/v_rgb2ycrcb_v7_1_vh_rfs.vhd b/src/bd/Arty_Z7_20/ipshared/953b/hdl/v_rgb2ycrcb_v7_1_vh_rfs.vhd new file mode 100644 index 0000000..2338dc2 --- /dev/null +++ b/src/bd/Arty_Z7_20/ipshared/953b/hdl/v_rgb2ycrcb_v7_1_vh_rfs.vhd @@ -0,0 +1,4387 @@ +`protect begin_protected +`protect version = 1 +`protect encrypt_agent = "XILINX" +`protect encrypt_agent_info = "Xilinx Encryption Tool 2015" +`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) +`protect key_block +CWCn7aoA5o/cJqqf5KWJtR3Fp8LEPwtQvtXu4vnJ1ZwiJqsbt+xR5NQAM1gxLLR+Y0KUgbHCgq9Z +rPh2gLqiIw== + +`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`protect key_block +V+E7k23Mqx7KprVKi3qcd3PvGCoEuPi1J0AlX5/pUNiNuVKoitbchZxzJ8KhodztMae4s8E28eoC +GTeEbsVVJhW7Qenxw6UOqITI3+E5k0cenIVhkVofjA4dDpA/CKwWp3RVOjlS7OhPzUdrW/xYArN9 +C8XFIf064lpwTmjgsqU= + +`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`protect key_block +WEeAO/1r7ctuCgaTzXThE97go3wMndS0+gXGlTQpO20meAqKxIcqp2kbClhXPu+Ztac3k8wZ1wX+ +7zvd7uVhweJHvDo7SW/gcdO2oUivOQ6kq/oq/BVlY0WTo83JvjgUDJMollqN7xP9KuX4nCNZ+c/3 +/36WaGkK11lyfZJWHfY= + +`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +rd09asbzVIAtBXGDkNWbpMNuul1bPWfA1pcoNfPW/ICp4/eRb4OQ2bt+AvP5qxehFep2+RXr3Pqj +KbPATSY1ffg3xHZwmGjM/Bk0D9Zg5FuzvWywvVRTw9VvZmpKJcYzsnBzIXnRQbzdfZqTpqJkYe6h +S4elpRQctRQzdWm9sWToBE8mMfo229eUjjG3qUQWpaREq9z8GAHf5GJa7dfGfNdKLWm1Wg0N6rZK +oMCWsY2eua+UAb1eH2VZDBeFmyxyLLx777q1l5WavUpAgDY6mKFxgm+lbDwqC9dUjBt7ceVEHShr +6taaoSuFvlm3RY5THwBBc5IcuW4adBFgXtxFow== + +`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +GZbbiA6Xx6yRHvk0LJ3DTJtk7SXEZLlH5mr6ibr2P4XoSjw3hxnA19C6IQItwDvrv3co8UJP4z/j +G0r3S/kPEpiTS3aLtJrDnp5uw4jSF9/IH3Fd/1ejjlFE1r4hAv5PhZ0TG4haGv5mmQDXHaFEiBC9 +8yWM0aM7tWlXsyHshgRwnhXzO4mtnNnpszaHQtwj4ExuyqhYC6nMcPF1Z3wZqrp2+WD7cY5jTGJs +TrP8QltG/ggrBGnJ3PiljOJ371BSVEl6OvDEsiw+vO6CgOnxMSTZl/amPGICD4t6uIvr4h0F/Iy2 +oUlNG+IaJOEVuTmh/pkMpyApVnCNb7RZ9rvVKg== + +`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +KM+7kryxFZqKHqA1lfea6kzrtTrd0VU3gq1Mh+xNMhAhKNHlrlkGsAhSQGX6NaW8S9VhbCf3nPiL +p2mE3HnSDoQM56ifM6MzUIyScHWIfPBAZ+LxdfN4QOcSX69ycupmKjX1CfWDSNEsSL1fVF1jTF8f ++2/6GaQRALGzXSvamRdxA72pkyHdV5oJHl8D8Q6ubshrNpTuWnI2ajMT6HcRS7wtD2ZwOzV02OfD +f2JW5KEtuMmJVd+AJbxuvglfbsaAYMYFFYLX/NACzLiT815TB6vn88B8TBfqAivLRtFH9Tkiui3x +IeuXj12/dKOgiZHcVltWRkOlZNlHdGr56y2GnA== + +`protect data_method = "AES128-CBC" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 246912) +`protect data_block ++UbgJmGc6exYu1LnOpt87PGwwFjOV9zEcihkj+/wUG7QkMmfW1e26RV6Yl8rheMRWi4vE55piaLR +3hoyur8SySzUuTBK191RDP0Ue1ktjweyEFGrav01F5/ERTEWrTPROwSs2k4xXBMrtFVUHamRcqcV +09OOINvz/O7kWupJu38YapblCGavzmz/htytNByKSWJRBAvswkxB5WlkF9i3qy8lFZEsumQzNY+P +BweC2MTEKI9KMHLJjtKH7IYkd+8DtIKmD/Dk1V26BbbuyIBCSMhdJH/FlfAkOEDMu+v/D/eCCJ8O +UahTy/eGjCUGLiJWD4+kp9rTX6T5qk3vLfRx6USs7/qdsz46p6Vg3MtL+AuA9V8hyHwklL56DI0j +uuVoCBehiBOwWyG6xTPC3iupVXwF7xtr7G4Y35IkpBK1ZUqySmv/k8LOpuBNdhyGwawXOMv6qaT5 +MnwB0lMn+Krklx3N4dCPUExqoPLd9eM6zB9qP8KW87A4iqCFaSyUNLhRhZI5jCJyPbPV8y/Kw3+f +ez6EpDlUFHl29d+pn6nvFiuC9Bb2i8Xc90NF+eRNJYhbyHc42CxRixOHNwS2oz9/Sf0zdmS244lp +SryQsTCF9nTdHV182QhbQB/NDPO8lUrvmgMcqfosdQXV4sU7byLD9el7RNxM0sCmr8Wn7t1Ayn3F +CbYdLo/qzJMFIVE8+pfvnw2xtqCDDMN7utnvZR5gCrOD41DatvmQObkI4Jm3leuG9r3QmlcKAVpx +EVKz+P0vrdt2hrqpZjKNGHXEh6c2pdgvkVwYNnCZNGjntueg8B4hB1hmgq3UtbXUGhXsE9p7GSAD +pnCViY2AY3eCGXYDnrRk07iOohZhbQrSI4rEhsDY706k3S0jXwyuU1LLd/yHzDshXfg+k1VL0exf +i/wzK14RUqU+o2CPk3iW7PE54X/Z5exCN9XhgJ3+AGdNRJdBQBkBc2hKRlRHAtgceyPOiRxqPZ7t +UkrXhRCGtTdgpsWv1RCBADq1YtcqP+hZfwd0uRtoMpCpDd69LD+uAxZIQQ8YyQEXhkDfKAccQRMO +JQxZqETUKmZ3CLbCyMlRRLNyxK8zgzU8uF6xl1rsFCH/7+JzHziE3ijodzR6qR/mo6k6PQY3QhjL +yvS1PA5yytCB8nYrZqq3p0yZgnN/YUHr+BzVVgW+Wxn/P5RohVob5sC6GF08pUTdFczrL6SrPZGs +ZochlUWCUlYQVrfGjgD0uxxdKSsr5Gs3kSF8NGl5QsMXihXn/aw73jmy+WdZUPbmYPgTMbaGmXva +P2K0r1VKr/sZPUAckgagxU6MjADR+dpIZelxtk+iBKle0Qv4E/oGHFNgFWUolPBmGurwDZffLaM1 +nz6qAZ8myFyLPO3q/QrIFpwv8rFBVMMiUg6zdYnA8WCvL4rnmOIOPa4nLpIsSONYJ/i1rPETpnh0 +OysLpHCol3pNbNvFSyvuo+1cOeR4SlM5y2E0Rx058wTM5R6q6kpjBq62OQrxGMzBbleAlPTD+sjc +7QBsAYs2XphV/ImjFQmRgSSgNRYESmZGZzn6l3FOycUNFz9d8Swo2WkVK5IT3XTcWe/QY8vcdvUe +2dxYLYu3EFaYFI31dutDgTOUMv3+0vUCfy3DlBVVgOr83G9wvONvbMiZeExGUYsa5lItevCEUjMo +Sgz3KumU99ZlkQ/7hcNFpGYeFI3KbTOKO5Db3mjix6Ic8gW+tC/u5/dCAdEmGnYfYf5B6fZu/VDX ++RdN3Uf4AyCfrkjnApsWPA7gbZrpW1XkFhYVEj/YJ56bD9aZ0EFnEjw+6EVKzmqy2KegTQWc1kbJ +NT14M/L5YYuw/B6Re2TQDKxwOpVBubwZtAHcNFT96W4EhfaPSI4ZGrRlvzZGtuYQ2iryrBVLuNob +iq8fxBkxOv+o1CycJvvMYTKKWJK33TJKuSP84Z7eB6tJZmEjJhFh5B6bzwz5NycmFpy0j3H/Vm1r +WwKM2iURdu1G+9P13F0uvuM3EEvcnrVLLOzjyKrW1GIjRAZZ8kavtaAC0jGFC6wxIcigm4Ls1kip +gUvtjPD5r6CLjfU7HyR8ehZNFetQ2npHsObGy5ZBWWgemLjvuHfmZjWDium5qUZGXqZQYJLDS7Ef +EyDtbr9d21k3lc9Bp4XmZbdQ6mHQfGJvTBLuRkNGmvdpYJR4mTC8Pqo94GadwKWSDTkAwyrRQDuu +WUeLmwGqKZIL9n12U6waQZabCRtGlzvPFktVqkv4osIuG8UMEJRhBIWNUja3NTckvBA849wGIJ/e +FhXlrt1FBglwBLdYcckB3NiaN1VEeFjEs2E9vK209erbxxLBDEHtHUSytBsWFEuJkPrZj8uv21kZ +zcg1APfn22rueQKNLFgt0iooe7qJL5eAmcBfKrW0M7Hcf+eCeE4ilHCyySYsUMl7z5LZnt3AuqTs +t3+6hYDWriqGQRAsjdbCypZT4QVe2NxukAslcDEc+/p4WwZpJjof798yJRu9bV2I5A5QumjcMIFi +40+skKotRMTi5Msb6gchKovFwQyrAh3PGle9Jiw/oaWIR/TIJpR9nwgLYE5RWBJRqgezgGAAYh2/ +a9j968otJKFQ1u8wcBYOY0KN2NSxceSRkseFnadlE+sK5gh1MP+kAA2EUSFl5v8gxJE9zcxPL4tq +bzLrF7GwhY2qTk3X8Mj48Pe2XaVAWBa7BGWVvX8jV+HTiTTrgZ4LD2t4BCb9Zzmyg8U1OYvzrNkd +n9cpGdu5vgwl7a+yNBCVWXVgM/gZ4gATA+S9OWI/YTK/bkLQCLZ3YDTUaR0nSswR3dFuWjInNtc2 +bntN+KflRW/N+qMXK1OqxJHkjjbfAWA00xBMtDmTWHAOOeoR+7mTvGjciLIIiJytZInkZnJTN3/z +KRYJN3+d+mnUlG5I+QiAyawirvgtZcAZArQsevjQlQUKzDFG2LnzLIWxDpVvo4zp7alhyrZlbgr8 +pNFy/ikldW6qPgcDWwE9D0MrwpLHNogt5LjSmdgL712ukCXKY9S+ADaUp2zyUtzYlQgS98uhKmAr +mhqE8Db0rvI6VpcOO2FYhUJ2npda07ErPzOluJEsVONTPd/UBqWnezLBdGYaQSQneW4liu40M7Pt +5wXRbJDz/YnW9/Ltc4xPyPHN8SjUbADhVxRtYNu4IymosQmLgxOzCi0XmkwLjf33ANk9kfo7rOvE +V9LeGGI/OnZxOoJ9Nqm8vigJzIz/UO/v3Ofj4NvQkP0YTHqHg2X9FKHPCcm+uUlv+oAkXYMm7yx1 +tUposypZ4bqs5y0mFLIvL3K5B9fOYtYUoQLhqNFR1/kx6mKH8XhnXmA/NuRGtQ+RJP0ebCDzGy3Y +yBLnKXTgmD1MHzseZoKTcbtdqKFs8uGQn2bs95n3rKT2/rpDoP8PBHAsfFuitpwRbIGILW9emlmD +w5LnifWxOgTylHB8SY15FqPbtfEpawr5/oWTCMHE8GiPXOrBg7lpaCU0c/poRF2z0lE63Rq8UlCF +054dZpnTte71Upxl/wnSfMkyiBxWeFplqbANxVo/Af9U6lV6/wc46wgU76NdslvMId4JtUYa4dhg +3nzYKkAjmWJbdTNikyIzvjJLKLaz0UdcAlFlEcmjmErPdojXqBBWbMchMSoh3uvpsjFT8RPjXuzK +U34mygjKmN+IsNY3AFi8BVyMVMyEQ3EBcwksZlY226eLg0wlvoDcYs2a3V1jNDoKE6afgmTHVt/8 +KhLObQWClucUgnuejHJfuwrKrzv5HTuo7ghJb/XVJ/om+C5pmOOHCC2uvaksTy0JmJWzOsi+aiDs +0QH3a2VCpMmOEKXI/QUMEo3z/nO/g+HxGRT/Xr/cE6ckV2gIjFBoBdEM64Myq93w38l9r+aD/+Wh +183+RZk+eGHR78W4VXy3KmC2qQWzqBGwSlcvwraOZTXLAY6XhoUllr8fmBHo9G3fh0z8h1P5er+v +cDEuv7tYCFSEfM62jTvN5OjMs9V5SCAGbxDyuimHUhyYltOKHzCzLn5GaU3j5HrSZtG0a9ftvOsN +BiLcWVrVjY9TwiKlavVODlHNQ9rmwk80YJTX4c8m3FDs0Cspym8B6kp7n+Rn+CAHZxs8Rhy3K0sH +/uLl2cXF8Jb85FVi2OUfEpWpL6obnlOGWDdUMh1yM1d3G4whDVoIbepVml5fIqVi9+vol1K5mVZS +FNCcVnhINfrrjibSOhxP8Pw2BMd94dBBYceJuaeHLqIqbV0YHplxjCrH0q92NlWOf81JXrhsdCqK +oXg5hhFl8kMSAhXx/KCWhM+ehXchYiqv+1bfZ2LbveDhJ/91ET6h6JL3sjutdV6qG7Ox7NCax3x8 +WBUnAgZJ6WO3p5im3SJxIt6pKkEShb5jMbfs2AstmYeTBIUtEh3IA9cyPa6Di7pQI6c7Aiw5aSB8 +JnlWhVKJkDcAUyNGoSTYabjpdhyyfAvfXhbCctSaKPQEFoRoZ/mA+wrjEvsgS6wZFZhmB1puvkm3 +hSPT8SPgSjk1ybEby+Ytn1yrG2+pn2Er6pQJuPzpjr4Wpiz4DGdR0quV3TzLEn/rKkRQYCxc1Gch +x1VN4NaO6ewRxfwPanL/N/IKvoBgkwXsi4f8kw6Px8tLtiEcV4RHGBBDuDi67qLPoNboZhEcQSEl +wHiDovhcOTlGs9SXKOFfBWHE5NVuD93zgfVLr61ZGuCJlPpLQ6uQp3qvooAlajl27X55aZzy9A7I +u2kgdqa4d1eX/tzUqjPuBIszPx9/GiYq75acmTK9LW8KZerOFwQkae0mkjPnAkndBTVyLE4mOIde +Tuu+Mc6MWrz0PBmslCD9udqwqOeXFBPWXWvyHK+ZOS/bU7luE+E9S81Lug38DuP/rFhs+eZHA1Kz +F104E7xdeMn0jAdojTEyXRWdn2B7X2B4qtGvS+VzzLn+tgpskJQaa9v1tcSL3FUtul2QGKqnTv7+ +2/pY0ueSSVNnkB7AYIxyzsU3JMlF/2azJD4A0klxsGU9FPXLWapMoRop0AzkNgbrpHSIVZuESoPR +5XTAIdHrj5aCpE3jPJZvtyNA+QeFZZkxsYfbD84Aah+IwaA1qoAG8hoNFaV8YOGXXfL4/x8KdHlX +cmxnUljAtOvCUEKr9SGoaOdeI2TjhglPoKh/ZRPJcTn5tdWzd5xvU6CsW3kTJayxkMgOLiUF+cpx +7GcTiAZH99bZeUCo/0qXXQ9lJJP6uRLs6GxCsFNApdp/5s8MoqU+unXxNWg3xPbuT4uDpWFAtpJH +pa4Jgz50Xmf4+fESg2Lefc+OJSNzvIVsoktj84mcjp25ytl22wHGZDDlx3VqC0OXxS+M7SoqUMTc +Y0d8xX8Y5iAp8SIpUXBLIqb0QjnmgHjlGRxZ6yo0MlgTz4DzYP/h7jilE5AwBdHEr87tov7zTIqs +gK8vtag+17JAMgW+BUvKP47Ze/zyG5Xw6TEhtYD3JtfPF4XD2DQGQqFg89nf2FS90hsTWXVAjTWD +umQ62rluhvwLduqr5qFol8huk7WskwxMs39HSOZ724sod5erwW2+9p4aaXb6BF2AFMTSB2jQ4aH8 +TeVLbKGJ6F2QiuuKfmdpTPD7OuPbGk3PHrSy0a19vBLbk//DUc5Wv/E6vIbSxyKrpAysB+UkJGHg +DKfJy4S3fdM46FQf1y5H6IzprYpWZAuIkViS5jUJSfXaDhh2YWEgYLLAASv8o/bcgwQ/Nswy+FK7 +3f82Pl/fH5h55mMGC+lUp2nHJdMcftHLZpdtqcHeRQrM+PUV4oND1ASOtbEjTsPBU1Fa0WjW8qeL +Ogm8tA0h6YadK6SZ+H+P54DOB0uwp9tWnGjCtYmbsp8/Rf0Co0mIItMeZD03dvBGnF+MdLoiItxC +vzLJ4ZMZ8h37AtkgABOmgXGP5FQxpDvrIXJTEWzUzepPw48qdndNOjU8vupvjmLx/W2zTu5SzXar +KeXzOGQBjhztIaC7XfPQpLKlFVy445Xsza7fY6BT1/ZJdMFxHbHSe3wSj9YTVslGUNDi2bZNEUPh +M2Y80c//tsQt6YYqrhNIxy315nDDj4+saW+T1IZVjbyvqCk7R26plSMkWRpGJZ7viGTfPNUeTBCL +llJswzUoiOwaC6857O26l0igA9xPxpl6iwPDwY7/PADexNtgJ/vsF9C3IPUSw9A2BhI93xDUD6WQ +3ZrleyoUIA5y0HN2Up5g8q5yui7Wc2ZGA1nQOzfiPllA7sqVR8OX2ejXRNBlX7U6JQ/3mFf/yPh6 +wh7L1wuAQPWdn7/w8a4/oFADvkIwRwO+2qLSNEYnoRNceh2Y5FomOunHYXbxE/iGD1pIlM39cBLD +2w8Yl7MsgjBW60yT/8DayFAmNrd84yAUZjPy221zPUQOywH62oEzQkOua9e08CDZPM1oSEIgXLJr +3cFWwj1IWOR3PcTZqUwi6pzKgAUNpflog2ZYEKsexbic88fLM5mp1NT2rex1sUqs/fLDMKE1WXrx +04HCW0IFOHLHFvPnnvUoXK/vHAzghjEt6ZR0ytweLcdQ220n/w39me8vMyOBqENeMT3+Oe9fNzS1 +UZldFjA3N/OifSvZ+uN6ScWDLft3BNOqRnc+m6bZvFPP9+0HdkjjOJvM2mRVahQb/c9OyZu3XAKJ +VSYljeJWrR1yv7pLeP6OuqLIqe82pZizVnSmA3KeM6v0cW/VUKVmXXVm227bfMr8lKJyNGpXjezI +y4+65qhgW086ZHZG78coq18O1RjjNdNWrHiNpgcSK0lZPUvC6aHg5X+QGkkrYG9LxJb4Lc+o1Da5 +nZKBfZvpiWnoZWWfQRJB7u7p7W0l6FN5UvFn6eqbP9B9/BfbxynD54QmJ0ndvwLVI9xVdCVItvrE +yrrFIDzMkpAp/PnFQLtNRlOJDogZYq2OYZ1PH0e/J/xNDr5dr7+qWev3rATOBVLdeW9QJ1GjgfYq +0mNU5UtXXGIs7Ey68N+imrLMfIT3qR84mHVCzcMOlyYKqy9OVbBVXGBBTboYbvp7HpUSL/4ut21H +lxmGLHJzSPpSLARAZQErMxcmimhw7PbIs7NptUemFub4i++GYFBXJBxbRbSE7J/+bz0oy8UVy+/a +yFgcOsf1iUi2rSpzsQaSwgslsl7QJfKw/vfu0dTBZoUlm6xYmG60xnWJBeiFyiSzGz8XEIAjHCcs +gRe0bc8PmPptWrnH07JIpMeUPagVP5R3huom1inrgJfSx44lYnQPMIfHxnX88JS28aFGxRi7m4HQ +bW2xUb0VW900khtzZYMt1vUhMTlu3ojKYcXIXJP7gmZ8LPoKCJdCXp7/g+nTwpg+jsuv6JfutjT/ +qiAzvCACkfoMZkGWBi2EAipogc0H1oSsZUuY1GzzuaGbuwzP9kxJq9plCyVGu8FawewKOia5MlS7 +tM0nNmjYnL/vyvrS5ghvTT98PInk/M/JbiYmXFxJnPWr3vYwjLVEB7UMJgM0vy9f5yxDwk/6OvuU +47tjvOFtkxmAA1xpeCy3UH1I0oI1QcBeKK+/vQfynaS+bsYo35lGW9k1ZzTpQZHTGmqzek0bo08r +lBmzQ/AOn8y2p/6sM/qrPSBx3ibjE07vsMtYXC+RmYM2bGhU8PH0w2kwgu84vInqbH1s0ZQsjOHw +os2MXgPhI+BBdoTpH7ze3XUZiY7F+z5ULP/j9xaOg+l9+ttn9szbRAKO6evS/B4rCeyOGrCGolTv +M++cxvNRSi/gK0/XZDhO2OeUfNpfu08Xvn/hJJDliMI02PoT8zXRhrL58XMO1JHMQ78cvMJ8QuYq +Eehw/aoiV76mB6II1U8NoWDKXvTE2+/Skdb9jnHRVb300bZuonaMjHAQFSOjdnTVLOGiR+d7HLKm +/HadPPNDuwVtEb/Mx9IVH1gcnp5aQJg+XiFEm+ec1t33uVK13vFsWudaJbJn9Bqx5FqvIvURFQki +B//b8d7ZsdDpFOB5sV+EmqISjdkHp9Tg8oEQp37t/1vLANAO/XRYWCkZC3wnztpoy38nX3G1M1sk +FRLPBHI3BJCuhmuOeWqs54eSx+ch09g5LkEpYdEzf7alhDZBDa76OArIaBKXKA+xKEI8X93OaJz+ +5RMI1M+HpTulZipIGYbAZOrTxtSRF/MSAYgOkj+hOV29TQThKIo30f089J48f3TYQw8ORXLEciLH +R7gu6+JW97hJv6U3fLz5qRYFpJdHzXkDux4ohswOKKwj1ILBBZGTgptl/+9TYEX9vzMRI02oPm0T +6lrXlWr/SAWwumsbIBMqhqzqQAPnsQgjUAssqsTDFta8aC30E0p5/Yl/++Nj6WU3bgDpV8d2K62O +4x/NPMofsRGvKFxTea7eA3eM9NYWkDXinBzaYKE8CGH7KarredlTN+SeABYlabllVnuaLYLYQzBy +t9BvZr0tnd8sK5C7S58H/mQNPbFdU5J5J6nPUPbHHjfISw7y3zlhEOIpljX7zM3vX5rEd1Vtz47P +2MrBfO6IUO+bdGdadViAjCjJlj/Drm2ryeghk1AtAMZP/J90/hKwBMmfzf5X686ZvCSMw2sZCmrm +uF0JTjHC3canHeAMLKRcMFlCgXVYxpIqEjcUA1RNJ4gDZouL3SwFYLDJenm7knIJQfz2pMnMXqBY +bnSh4GUODg5J7bU25yPENFk4LikPXzDLLAu1MpzGD2peupzlc3yku+dtbav2kP7TG37X90RsGgny +psQMG6f7uGv3JeagRUhVJ3XofcI0j3wGfHXLYYcafTSWUvoM/7STHymQUCgNVgy3wpjd+M01DIi1 +/8u4eicMICrigX4URrNF++U2zNBiJZvA1zuxiPT3LxOvPIPxH7vEbI7s+TrrmvU4TcqjpAyZKPDq +ACXH1Aig/nkcEPvTyPpwO6CBKiKP4tG88BDAHaxgOXlTyQWig8pbhFEl6ni55Et/VnbpUppKj/2p +rVfy/RvzPmsiT2snASipGxK/sMBP7yDZK+DZ71eFxoBzU690i4fQcewBXfUPMS5wOqKjHloCf0K5 +DdTNrvbgUARQW4rM+AkZIKbh1DTtTvR90A/0Ky7aVdjz+oKs+OEwled913LbrHvxyUSknlyeGYCq +Wbde3NxyKwU7qAvFFjKqBob279mfnwvbExqfdnR39yoz+CLOgt4pBonXk8v50mJqWWVPK9EHlWyg +BWfwUIG0rBGv+A9mJbsyQ2vJQSj2TqsuNgMKrtwNbTHCk/sQ0osNT5qwbUqGF/TsAKUWhLciufZO +mAmla3c2gxcJ6mzft7NHl9fh+o1cMsNsb/mLwNXw58ccminnNEUeNS7Zh0TZNEZsGWxTX42ndmqh +SPBfQwtHmhXCudDoMsSslcl0jv7uBE7BY9oMV0fEGiiSsnW5aADfEA3jaPWJl7DThpuNMWe5YCdy +bo7NNvnsZLIRkrgnSZPhZ8LTvJVpIiunYb22cPO62ZeoVo4sA6dGjR43ik514U02cI5YnsYFwW3W +fVtdP9e8BhWIcl5V/6b7V93+z6x10JTFmC/4XenOwj1x4d9HNQqpu25RZuGfs6v3euLIM4BnSS5v +FD/bPNEvVthVKEq+YK5G+ZpqLaIucb+uDwH4p2x1oFqTSDz51F1Y3Yoo18xEud/kDbwFEUSaq6na +pAySRjRekg2qqVfOb4o0SUxnhYhV2nsLU7nJyAOkggKjlIj/qazqcOv5NB/2kuSDqkCoRbOk86MP +ZAK2YDGthJPvKaYGYhvJAeb8x0ar21rAqW7QoPpQFrYoR+ErsAM0bLe+ZBzIuR+qXlLqoviHaQBB +EgwjITSBKQVAZnpMQh3WD9b80++Qgu4AjbDciujpCdAl/J/df2D07JjSga/ivSjqHaReLk4t1bGO +EErenC2geS+JqjddT3mez6Xo6yEtt9K1fDcTP74oco8+RIIH/WfHLdzdKMs46FKLLiABxOqOF2Xl +s4ZAsDkhPCLDvkuUU3GG1D0OgVtecl7GObBiePTL33Gkos6NPHbXJni/WyrdQuvVMGE+CcRuKWFN +/kcL8wDgA8tkFuHgPGT317s4Hy5nv6uyFpikKzAGzmzwvSfEXFB9rV3DjCL79+5VxN0mcWqao8EN +SH9dw7/r0TcfMkqGoajHzi0ohL45IBapnhTjujqTLTAUKVmEozjJdF2t39a3ZuBmmARvGyaR5sQV +spyDEX+2nNv/EmBd+W/cy2txZoyqNojILyXonNwXd1ydgzgBKNeX/Q4waJOdCvIB/9qo8EMrFNJD +0jwT6YpekCVe6Uy6KN2GWmAmdTMw3vFEXaAeNDl31p0C2KnDr6P7GiSJv7bujRh+6m2qrl3PabTH ++PPKdxQkq+IyyKMnEODCdPqgvChgGRm8xEksAAV3LSHkHWTm/YSOuI++vbqtD92IbpHje7Ak40XV +37fewdE71W6G9G3QI3MY7DgnxsUMpMrW+i08eQnZIzhCj0HWTrS9O0JQyPCKIeRTKuWHtkO/UNcP +GmXNrzlg3gHz6/c1L4g8bOpkPsZsVk1d0conLVGuuGs4fIkOCk2Z77ejoTUI2JHs1iUrIAoAYofV +xO2hTLka4Q6W0jnQ6jUaLGbhJMZGPvKat43gICE6uQ2Hzdeyj7iRIC8Ke7SRXVPvFoNQ+4ue4Wpi +YVFYwmqLWd0jP7JdY2g33v6Xryey2D4KxN4yIEvzcebeMuEwf0iU3/h/KgxBWk6M58HVbAq6Vppt +Mo49OsK35sZr80jSi+GQSt+8zYWmCnbjM31E5z1zyrccj/vfPzYlgY1oWDaXRL2ynB2sqEUsRus6 +Ydbsrquvcd24XkI5CVM6k9oOehHe+YYjKdKItgerWiLjclmPzBnEIK5JEXWb9XZOOQD6W0nsjPCK +61Xce3IwIbHZFr9VEwTkR7XFb2L9KT8xL+Gr9RKuIKI/MG7u6WufWOIn0qs1j//kQCQXR683yM6H +s56dvnM6fbLXWULTHFYb4GO2wr4eABOJafmR4Ju1iOFifCW6uBzaNcyQQurolcaJeXnrpGCqNPU6 +Xefn3GP3naBFuoGGiFA0p27KbEREAtCVBvvulngsMcik8OdNr+d25i98EdKMJFg5NWXGvZX/vqA2 +Oqzgt2ue96QEhulxaN3ZSNi21Z2IUmcLTVVPaqdQq/UURqbyi6NPbUcUaebPqWXf2+U0jTV5cpYd +7Zz5JeJG1TaahXhpIsVPb0uoZkucY0S1S0H/sIOKfwFMEL2aUOnxBX1tQXvypcT678fkVxP2wcDu +sY/O3nNHAiNLJqp/5hyyt2sZ6xdFkXX2IW1nx9Kl6V05dY8aDTpS9rYduPJoI/786X2p+G64zQiI +zDTKhQKXwnBwjjymmp1SNfDlyqlqj9ZZhYkSDgnRiRddw51rneeVfX/ptAIreRPA6Sq1glKsF4KC +ruKBlSfYwFeObOQjbLrc3eM+46W7+Q/3dDKwlAoxFbVFC+HCqXrbgfqS7nco9m98y8ojyZXE4Hjs +j7b46JwuyFIPlLmAX5SXTil1aTRHh4g8tZoNu+NvS5tfQTTqpesg2XuJ1WBIMmdnJrV+6aef6pzk +9Hh5/6ovi8EQxe+do8Hjf3vn1V8IZnSMdNQJzOKeMsuau34+aJLcbokn6H4iLXqcfXGVSp2zRdaR +9e02OcVIJ1m1JLqlNuf2kLgesjG+76Wht8E7pje07ziGxlD4VAlfiqcPu+fKzJlZXgRERCRrxTpy +qn6liArLZpxcDZ/jGGZBmG27loZeZsoYFg5vGbYFgz1aBrFRdTRg4LnvOu/wlfvT2Yz22scVGWWq +rKZbidmO9bO8htchCzQ0K1PDWiMkeVJeoRAfZpQq2kWoF27215iAvCi31325hcSR0mJqKROIhWKf +Rxk5iIhMwuiG+e9ZDLT1q/Dyo5BfuB0dSUAioaY4+rzf1+qZXOWWbvfI1isrK2hFpp7uhVGS7MzV +j5s+p7cuCyn9J2ZPvePtULfmrlJhsqyf667C7Ozb/yQIjxmvGQLBLzGof55prOc7DTmgi1gSK2jc +dZ0lzZ7rz+gS47EjpgbmzDkOxe+XCcIbxArBF3c0tvWzw3vuZCiK346WdFiR1gk7oHuR784nl3Mk +yjvXEadOv6O+SlKH7KT1f7IfuDxsZ8YP01tvEwCU4EU7szeO7inLxHppAAQQWzZhVeYEmpcApc3X +Ym0oik0x9DdMcybA6GAIxpaSBY0gDxGfBizZll4Jf9AbpHc4vkO/QZTiqH5B5OHl+m2XcTl3x4bb +Yfv+JfCB73i0ZmcIoGWapPeyQQLQp1N8RdKJiPg9vDk5czyiwKXCEY1MTj7JpscF5Z5QroI4Ph1W +nm5QOoO2ZP20zrj4ugfqQtqpqjBNsN7IAWTjYstVHidOzaTA0TdAMA/OyM3XVbdVExnW9lE+k9mC +FLOd3AmGLIDjxQbr1+OWIBlssvSdESzd+G3XLW4SptP5MbHWDm4cLwUNUtWHEh71srYL/Zk/cmdZ +EXy7ZCDjmPUSN02DNP/I4UqVkTA7nN0n1kVR1wipbgvLAihktLz/6wawiuc9z5xdFZ2WTLv9z4fo +mCwgysFB28XPE6eEwQi/HRhPElCRQ5awr4tXk9+t8TstFaVWZGobeYo/qfA6LMtmUGB6PF9H9nfV +FH4zNKsZn79zo9PnRKY3uBDNT5j3EWNwxC2bK/fmtmRwSIo4T+noTkWbcuaK+lsqIJQ3XeJBZJ1K +7s+iSiCZrw4/HE8urpoGST9Tv3/eJKIAKSnjFMzrflThXKiKQXde0/9qo0AEPwekgSX2pHAcj7iP +2tVQHEudaq5y2oHa6jA+d5V+FmZDaDidxTnftL0gX4PAhUx+LJeWgfIG9WqJULTYzJSN3bj1uipa +IJi5GwqyjNcpQBiuw1iTzg5U8mEBxHnxS/pfX+7B90u4eXxFhHTerz7DPfQ4VeuC2kOdb24gpgVV +krS6Qz1R66L4kLJCZ1E2RJB9vUcgPNQYydazO0S8/eTn2qg5dHMZca5vHScjVOPWmi2TxR1A9z4b +x98guVdUqF4LW0kzXCMfNK4BBsE+IuuBvbMvO0Ko6+xkIlyDD9DltyOezb3NMLfvZIB4JNoKX2Ev +MbhX+xjJ6vOsuAprluhI1XuyXtxrYVDy2QhAYCnzRfVNPUMosehO8uEkG0o3gNxwSCzls1/b1WXt +Dh2PAE6pqYHoH7C+Ln1bJD/4TNo8FexO+6qj3AeSAjRQ2KgXIhFBu3p7XtgcIH6bjnmIHZf0E34G +GNBbZQ6pFAWSVNZyx+Am6BGgy6ndHaIHibbRCbXmwx6vbsvyUNCLySkr8AFZiAaADAeMswG4QFoX +4gczpFlmCQN2RwG9B8WXd3uYn+IHx9zfKaceI0Gx0CkbAGDbSx6i+KX8eBBueeNGJDcicH8kWUEW +ZCXe+YvX5nDCrvMSmWvZSkt/OpqPXrGBZz65ajZAaF5EkuCyFUDLQWQO/KmukqG+rgT4H93euXcp +K3U3lnCZxOcERgYpZ79dWjdW4mIixWPMIYDSdlIU3aAKjYto2wOUkoopiHJKMdCJhcDnUomYuYCI +eEONFKhk/Y1Q+48j9A1B5324OOOOz3MvvX1kKibTDhZNiNQIWUj/ve+/7cGk+VYyhsCDmIIc+Quk +pC4Wtz8C6dBrgZ2mhtsHVhBEpcOcZ3TlV/jw4c4TiwbxGDVhEZmP9hAg7Laxzo4mdhgWsdYUKz8l +X2PVvW0jJHVwtFeYOgytB90AgwM7xzpzjHRys8KpUhc833Nu0PHDZYhmhZSFps6JONOxcrIRUIAJ +vRZTRv3UkUa7VrUx8VHVjYBVj1Wa7t4Jk1mh+fp3UyJm6dx4Wtm0hnY3inoUcX6x3gS4RO9ZIsAa +i9zRLrLf+vQuPZ0Tc4rUx3rKlUggQOW5+wEv5oRINNre2oCd50ZCjm4IudrAbEUp0QTsxhrL8xHC +XqHhMzbaJKRwLY+d9AMRuG7jNyIt/zA1kpeHVnLGFVRDeBgd0EYiJ5loubcXmMdXvFUWthOQaqha +l2EimNrVBuYRAWfgtDTADjPoSb4L5uzXY6V4n+pGigDUQWh97gnuOhsSsHapDj/N9MDaSDWojXdw +PX2jVFpW6cG6FOpOoZPZAHWbDxJEONo4wZrKD1aGwflLVg6loZ9CD0yhvQ9OO5w6GzNT8i5kHm/j +KvbCaa8nHm/LTVKFaHuls8ozvc/2ObEvGj3hZpTXEJdCMkspzHglAjXXKg1zerRIdka8PeF7PrDk +KbmHJnjzbWwmwlTHltXpU0vD0gyYHTa88muRAk5Jgjg5p3aGwePfD2qm68ANxSYOMniz3GPO9Aj3 +PGpY0l6SMkoPsEyvsYDHb3TispsilWlszO68f7Q/0NAT3t13Uns8Yvu57sL9PlN02WsEfDvdWJ1r +znTBPvHztli45wq8khlRcC5qSDn7DKJCJiiwH9S9klAnt0g/AmyXs50g5LYAoCDNpquKNM9yEXAY +64r06yj0Qibkn3CVOIkE2A8IOy5/kz7U5OGDCYSo0P6enDFaQX19GK5LXvMUPZU+RkXhoMCWGA1z +9Rs0aPq9sm+CmZMXdxTHaHaCcUnp6Fb6d+rSEJoOoWhnOp8hz4tt0inmQxZG5ocdncO70Cm22IMl +PMbL4vfCmiuKC54AymlUQgmppo400X37bSqsWo8pIV9gnRjpFOrbbknJbYkNNtH2gfewi+SBA137 +iNOuTN4vBGp47dxdwXtzhKLh1ilNSboJeeop7h8wPoys6YnPBz4Aubq2J1vDvjp/WZqfGUK+Z1/m +bWOkPcH/v6QOOAH9uq9hNHelXwcACQRo/Z+X8VXfWNBkWEljfhA7H3YFfkYabU7T+xQ2j4gfrur9 +e/FlzrGdkWLtJ2P8s7Goxbs/GsyKi91VvRUchgr+CSlW4/Z4tWwQKS70mOlY96J/dlfPIYk08zjs +dqoPbbmay2HE0vGx/RaEwH8BjAbyRGsX6LeSUtlUhO2qk+h1QFohbSVMgyW7nWzuVfI8KJ/M+AKn +LKrRsYlE+v8sUxISZki58e3zuv8+pZp2NgLUOO6RExTi8ptGlB7OrStjqVOJfmjJ1hWj7Rg596Y0 +MffADaCnQK5naIrWSt3r4h+VSpbhR4HgmW48Ziq+Xdl/t2RQLGrVapQ7Lw7xFwiyWRcqou62OekU +/IFgu/Yh8kXb5Ldrp1MdVZ9YTgB+CaUBM1wA7zhGdWg/ixwX8+9C8HVUEOFeo2xbDHIZ5qKFFgY7 +AUwAW9/jP7cTofvsMABFap90hzdwFpGG6xK5TDS5yhpRV3DbcMbGV2gToLnXmijAzAbeWZeH4FOf +v9IvW/5M6oxetmMgrNY+XRiX6VAUlwnVi3U1HCARrCHjyRshYzHoyr4u9AFOAZMQ9KT6DyTQ+g94 +Tqc0z9vWYzIg1qY1gLayRhycCg9kNaGQV2UZB88sr4osg68udwYjGRPDpz3TiAqhI96qr3J0HUJK +ZWt4fozuOWBhzdXsnk+RI4vUl0uFaxLkIo3lbFYvDS64OdRHsc1Mspy28ZV1CRjsFysTGWYk0B42 +vhCta8fL1lR48acg6393hPHkffcdKqhlFFPcxVeJHok+zRecEnivWPKjVyB9ms1P23OwVLX9kyOF +TqoJNd9A6JuRheuekEOEeeDCwG1wiKNzRNegQu1k6da0Cg8bhsIGmbSRamolAgZQm0B9yCshUdV1 +7UZRhfq3rgliCdacnnIW/eSpQZEIrl20s35qsVKJqXbDlpbPAMCcdVyjM32RcmCHWDQoZKJB0bcO +qhvHeCmECatEu7bK1ihyWk8Zd8ZfaaG6vYC7TwIRP5F0XLeZI+QOyK9nNKfAOSqQb+n2oTS/dUcd +d7Z11mRdAdFw0mklWkUPpuAysQr8XAzSgA/ARmohgCJ7zQLz+H3m0GDnb0oD8WbAmflpEZGqjPnp +Dljz7B8xqRbwR2wT1LjCwc2Lf7RU7zJC54SJFNLSO8++SlM/XXa47m669iMYtK74/o2HjB13L1iW +9Z/Y73leXkYS8yjY/ZC7DVPlDoliKUWBA2z5QEiYZV/a12qYs03X7cgXdoFmm+HQ3OquvGiJ3UMc +thRPM3tB80/8qFHcQpFT1kwenH6TJRimFf2nomXYOw+X4J02Uzh+iQqhxIVeX9B7TdP3jskhCte7 +b6JLvB7fraDsuzB4msIu4EQolzX0QpKI/xZl1qje8iOuRu0o1BPDQmyRuqABdr84KGpH6I4YeEcq +zSH/fKg9nYbmQufiZI9jAOuirg0r7/1tG1JxvZUnHq1Nm9W0P5hyd6bNNaGBB4jPgpTQ7ZpSz0VR +yoF7dnBbA56pZfS2FxvD2CAE43KyuDuLsihDpjrYd09QTZhJA9C8ZvWK2ec5awDx8Vct1dQQTpKd +btAmfFa3t1shTiV8Wg+EM6v2mjzKG+pZRMQMELbE/4DF1ag5AMnchSg9uqHdgyTD5zs+lNQfskXg +3A02gY6eSvFBFOTGf0E2gav9MGmfy74+KIo1Q4YNHhioMWopNHHc1Sp8qTVUS1+zw4wgyhuRk8oD +hq55wlWsNLsKITbVsK86m/Z/ERzOyiKAg8PkckJN9aNLJspZu4As6PY4ml4yzQlhdwmcmZBS/HY0 +EHE+oBb2TaLaPwlvcSyXpzeW/4piWZANkjfywo+WvNj8b7MMpxLjXsOjbn3sx2uHntZVjLoH8P9i +QuC+OjrJBleXeWipHQYi3O0eQwERh1c5lIaODrNIGGdcbEQlK+R2NHAHuPB3udTbhw2bv//gxdsp +M1MTONkI4GNeFWLBmXhPQ2wot4TDbga7yIwVm9dwgtkDJpMAPwKXGNuAY6++5Jy2g9K1QoHx5/AA +IondGQ/Xs74Nv0FcCRrg+FNSwC7sxu1tQsuOfqBPCuLw5rwHYePecJXnvNZbpad6Laz6uMC7dfDO +tpHb9rZnos3zf+OqRFiROpBuo1e0qcs+rH4URo+supcwkjKpjew2irAmWA9wVgAdwWtHhZqVej12 +MdmI1hv3F41y9E2lSxad0nzyNud7Yu6uQbPJbBhGFFw23XmgPgL0huOsOv8wJdSZuwG47lNgeLkZ +WbvGRrDU18BDqtj/AgKgfQSW70Az3bKVkr/tJ0gF+Ezd9TfgUnDQMAUj+kWOgPMjLOa0xJTshriL +t6a06qUH0hQJ3h0WiTZhuJ2151sL1P267qhH8C69qCCD8bIEZzBcNawHZhmfZmbHKKywCYFWBm5V +1BZLyRo0BbWGZeeRwijOUHsFSR8Nl5/Xw1C3ElFXJFfX6C36nsnsl6+J+OBBUl94y/9/+cuIYtQ+ +4dIVYdsU4lpCKsNCYOdJt0vaAko6x/eKEVBOmvGXJeaCcssPdUKdK/wDL/P2FxwE22YuQYKaObju +no6ebn82jfnU4cviJvXcdK1uPWDxITOCFW4NiLQ3ARV36kdKn6RlULGE8VnQSoXl6/2rVyK24mG5 +VYMCw1wZR8wOFPYw5kVxJsCe5NGom2+lAul7kfxlMvp8ZDoliwEhX/CVJAwodEvdbjfdAeTOGRRO +8Muw5x3ajMlzoOpfB82c5kwcK0ZDF9dYCafIQyp6yo2u3qIiy+FvhBlK9UeptT292vTvBmU0I4Qc +0vPCrY+PW2LGfLGh2eZlhBNk4zUml5RKYEo6SCq1nLAokyIbn1BOoXkb4fA1pKe45tz31YVgBNAp +ajUohCPUmD81D544mzDTteDsqW9mUv3FRj+CprSy3zbKwlUf4IfVJO5+/OlRHeKi6t4EKnljXMF5 +vmVABM/l+Uuca1/50nJb0W2sHeICVJ7IHXnQkAU8YmHvJJFJrwF8emuzOrHQSUI25l7eel/kF1IB +gtA7bE1kKKeGnzqfEGDUqdE/5XWxaFeBTCGTOP4eLvcT9YdbhUDT/AoHpjwWo4I0q2zfNLIVHPgC +t7HjYGPZS5Ede6M/OPPWlY7u7++98+mfOexxiuR2b1ABWQrRpDYDG4kP4f0zZojmYuBIjjdywoIg +i5JkyGOSvHK9yutPjf4qCGLMRxYln7cJcOKwIEqjr3ampOcPTiBHNo7aWc8rPdtMMe3NFxo2YEBM +eW4WlXKPTCObqrsfDqU/t64OHQmKCkq7pRHnw9TK/UttbOVBTX2AgGRHmrQN1/opXIRIvYgbZIQ/ +NujJzBJNZY3NxEXFg3DzXR+pn0MEtuqsMVBjGGRz2g+9CE0guUywRCuv8ZL+aAsTfOaCPjG76E3i +C5lPv0X4Z4ZTMZCfTcbWIpanxo2LmESr7/mWJhm2eZXNWDO5assKeybi8FO7GBuiH0CjJvK2rW4Q +6ijAjxSoRmFVKNU50rBXT9cvOSRq0s8o7DgavR35ZOPwgyHRMiDe3SzV6z2rfkNCI1V/qU0TOsro +mI6nPrzdyOKBJWxnsnJ2y5Bi8Uw00X97XGcr55xGYs9z+rRYbEPeb4PLOD0f4/28ghES+3CGmq08 +gO4chB0Mb9M+oZlBdLkPqPvpB+6acRzm8OJ2uul06VlWZuUKbs5xLdX7eXAj8QyJOrhEVG0uzfbo +4eI4rSowzY/VmVZIeXQ5lMoMav4yByV/zdMYQAlLKYhJhpfQ1IMd+ubmZCuZXP38orCLXZQI/Txi +jy9ZZJ0ZT6+zCeRMC6msnC/1fE3kP7CK348Geq0GnfYKYT3D71L/G1UGgaCdCMA4thJfhjb/N1Yh +ZyKM9qSmgjgju3Uae7sumhLW3y254NtIOMHdYt0Ue46/mU1HMDTqAady8SddWholWDVJ1YkcyQrc +6hQYPcrtiWmG+mU2iHm4Wnoz9IU7/RJ7fNIb+kjo0BC4SalmlLM5Ff3IpMrZSZNK/WQPgH5vPy7l +vxXdP/HA6xHMoqQ019c+7LVWMzlN5M1tqqMlXJ24nwuzxGa9/V6tthw6eGW7aGA9UEQfXW53TOAp +5Js7aHlAL8fvEk7z8CSerHBUY6qMWpdJP/qWiUygSpryT9jcUQ418r1bZc1n4euWfyfbPQ0DU5lM +VA7ZhtgluDVFvc8UnYeYgUtN0qvHEqVqX4DSmVVMIX69MH1IwhRE38nZj1T/rxT+otYrzDt2WODd +59JubrcaFZLp6LLjm2S6C2fuKAro6InvP+VW75HaBSm6W6cC2MzN/zCq0pG1Y35LTuB1T7EK03U6 +IaZGkPsKmGd+9XfyM3pz/PITKAAlUH4Ghb6jNWAqwzcC5cmdrWZm8I1Oj07bFMNolIYoaZx5vVzb +7Qx+ctCIV5DgYT1jvznhRhpaeCBMiPikZr8InfRReFOWoAW/s9u9C/cufJbG/Kh66mSgSZ0F5XXp +NiUJX35jmBfS8qWwZIwMtaNQlaGy+PuNDhZhJuwiMGzrVXl2q8oHA9myypJsFxcT1GroRx4AIfZD +hjsnmZIHRv7r0UYPPPPI5s8z0vnYA9uouhv4o6CfU0Kl0DhbluK8qLj9bMWudrxDns+xpkdQ/I+B +2jkpxpqwvu+aa2kIlRCNCNNLuLnr2KQo5o+DDjHGGsrUHb5p1nv1Z9wjIRQGougoWujjN880zRKo +CfG157GSI2yUuB4okNdsZ9d8k3QgAFpE76aGDsUHIR25esRqnwsp84G1pXJ++ly/8EfNi834kn4U +BE8yCRsow8nh5FUBM+VqUIhTX0OgotCtHTV5GeHkI9DDW9TbqV+cxueV5PWsn19Gw1rIvmrkdi7j +bQ/yGbiMzC82J6bW1mVuxdVHpIfDq/zbm64ffRuPFqpvviU24djwWoTrPjZuxVeNU1CrD4Pcul6N +jpwK/00ORMMlJOD4cHL5jQ1q9058Z5O+KxQH4y220AcpwN+1B/BsfXoW+2ZvewBQvYI8HgezYyvJ +YeEQZn/hQ36Ey1MkALvIND3PtouuEgyurWLrbdLacfAoN5EqT6BEqykEpasmBoni2R4/ctkixUoN ++KqlbfpdJRn7KcRXCbIMozId1xxdoE9LOpUMem1CGtNqYQ0gPDRGsHZzRSOKtjLzpjNQdu/qkM17 +btLMXh72yZ6lfuCZa1IlsSs7zQOFqfF6Yw0KKa6LEuSHapqzB/gjgydW7TmR0NBhqfF0pKwAXfBW +QPN12zWEoIzzHgWmoAIcn6IoJF+sQVI3IEuZtc+h1JEJFXfe3SOJBOdDcCGHhKZ6U6rvE1f3HxdG +eG6/ov8BRMKGsCcYoAqGtYp2OarFp/2T/lJtQ8ncXEDDkYwFiN+WI7GeFMphkLeOcpWRzd2Wmu7a +tJRO30jDkmmsoQrDSkeCS36OtZgSNoICRQ1DxjiQ86ntYgZeqzIhQHKPx7s296Wu2CzJRoqfuPrl +W4pHJrBYyEPfF3soBtiym5aBptuHOO3hNQ4e57N3iHLLW+owkXSRgfbHphAKQhvl7M2u1wl2xfx5 +Z/pV6h9I1BBE035qYfGcqO9HZXV4e38fPcUwUkjZfOYKQqvuznQsNA7lTh6RFynNQlhgfMq3gf79 +oVxHjNqLZNe76yOyHQskzfN37a9tZwX9qKAnDbGo5A8w2ZybzvUa3yckMvIc9F0uB1CKzbPEaZKF +6ch8i6P+MsAMVsPriD4uPYijprziWfYiBkFlnOlVP0SKGQdFqutFPgdTjwDg1nmLsE4zIkSb64cc +ulO0Wn/bJb9cpW6MA/bQkgOlz0Aluemjr7TKFym22mG4V99s1ylfOkpMKculs8m0JL+qo4VRGwIN +Zmdwsyy2SVWnA0bYANqgH+Mahazc9fUGA6HngtjAmtE4SUhsACpdwBpB4ED1GHUE67GjTQ0TT/dV +9twk17WQ5Lxj55q5iu6MCKrRfRIDlA7/+JQPw0ivSyYLxA8UMmXGnpr74tRskm1yvOiH47neDYBk +2Gmu1RexSHBb5mgnm67ISwrKNY4uqx7l/GRfxmQXxReZ7z1HIdIsUmMTc4q1XCx7ltJ8HFS0hhLT +Yxrln/GgTuZWyz8wigA6PKtaJfGa6KL9ItFPtUhb9m3SLX+9vIuA9rdkWZLq+dzRba8QO3MAW9YS +tzgsjY1gSTxtWJo16auv/1fCS3Ukg3OiyuB9ud1ld+1qt2D+7fsDIrTsk2/GHRnq9lGK1CcZSiG1 +ulVPSbtUXnjBRL/zIRPmI0k+BtTNGC310mcVRYT25ynQzvmKeVYaQ+VEqPVwmIVy05+eDQheYB/u +/iBGw2VY+yWoGr5zvr5loHJsIDEg9FrWgBc63V4tg11rdInGKfuW89cGGt6U30AA628cwlTcD8hd +QxVAVDbn906bF05L2TyL41iKp37Y36r6Cvr0m1/t0FSGfRp+pJbOEkgSB1MmQChHSgTqFHnzf9Pm +JfOcqoKWOyAlwoIEaiN2J82GnPy5t8th3a+SvStR9OwA5VfxfZF1DIc8DAyWd75xjfaY25bixgoK +07OOsyu/j77Wl+jyuY1UTU9+aPQdckiscmKv9bj5MUZKo8CqGjxH1+tnBPuEVjMLlYAAfl7VOQpr +3Y+vdrWP6FtEkv/jgx0STQGk0RKdyXDKTgOq9vurflgzYN6l5ypAP6eCXVG9Xj7+PhiQ1ZmpDSwn +zgRK4MameXtSNZJUYoAdT0/JMOGkoQa+xWhWZPPh6oT4tVjWuKRHwU2kjxYN8ifFrPCjjEejKAjf +b6T6Bkih1uvFbW9oO1e8UbgXbt/H+gnJ/QQHvczxL/BXUTwr/5HHzDCmYduAN7glz9Ib87PVFKg3 +az+x7jL0dbnKgIxv0BjiAaKm4sSpsq0SAr3Zyh9ucrwUjDYC3pIkx0lVSoFD3Spae4KJEg6pEZcJ +rluzzZRU9qTwq5kLJaIlsO5De7xP/ZYIk/lOkk3wKyTm02X8gzPz36UCsnzkTknzBMv0bmJBjqcR +7XMPpfOnBXKygmIdrJ84vIPZLay+n/PkntV6b7j0JkV3e1vpiV3A63/0xBPF5/UKH0EqmfZhZ/tu +9OD/n64hoJgm5rb71e36gGm/X/2SUJosUWIiLMgK9fMINDhOeAMwiyF0bw5RiKvmy9HYVJ3Gec6t +sqN7Ar/QzY2o5BLn6s8ReBFg/tkYxjElqmXtHd37R2HQbWkC6JOebQmo0U9s1MB3KMLE2hGROirm +1dah0N8mQPQAHw6xENskt1IwZRR/nMZb+1ZcD1pxvQ9DNWKSSoT51qMyMl3J7CRECdvMSi6fsJXV +yPrByioiU4jjqCQ9duPuI+2+ECQKElD9R92oV/NElF6SlTs2cOIEM/iFPjI/KJ+RUXkbk5FjL5Cs +jjdmCV65jI4RhiB1JFyDxMQXyZoQgT7XNwSR8HaI4Yx7KoN0FHeB4Rxj6kbozk69OlTFCaVPfu9B +1xEFe6X+dJXcqEj9OGb6ZJZPOzlmm31iL90ZIGYGxCLsDEHm67ecDwTD86jq9t8b2UQF/UM5863f +IJECwXvW2kK/wcYYeY7oV2DAIfD4efv7feFqVT8OFdjl3soU6vCmXWK4XQ+caZRPWjldVoCzd6a9 +ADamZd/MPj+Wbvw3liG7dklGPW4o4GIkgNcfQXsbb4jaVoMSbS6gBBcgUOwBV+P8o2dpFoB9kQuU +54L56f7g5XzPnm1jW54fOUdkjmO3A5wYMQaKAxluD0iLbSzmn09F3QVE/LGXfmCqPLDty8Ptzwjy +8vuCZ7Hij4x5qEJfqQ+9ullIq7M5AT5ib6o2lzLmdMnj9admkGl8NIMamWHYNpVwL09oadTi1mF/ +U26/q7bGnfMbhxsLIXb3S6aTFH/VYgefwBp9sahIiFCPwaieW5wynPb7QK/yRozQ/AGv0Bv8oU9o +ES6EU8hGGGdgH6nnh3IgJD0hEeVb1NIPyKobmVJaGBFidqwEKEe+j1mth1kCgR8UQAAE/KnAXItp +gV61jksOsWz1b0PDDVC9afClQKf6bD2FkjoQH+Y73YOmBWDevNiNo2DVqKtDa4W6QQU0136hCmcF +LRT/urMFvOurnJ6qHxdCKZlMlodGlIBdUgrAG3/Xu3TO/60axf8K5fPBGgbDMMvrQ8RDHnRMFxkd +hLvG792XE9I80F2K7i7NO6RQOOIfOWOJepsO+AgpjVm9z7BsTTGiJof4/c72dpah1QAaM15FDIsF +Nka47YoUUKayBPnWxlT/vzOmRrd/Th3+RwrAdJ3ifecE9nslg+MdJxwyVNuNCJCmJbLkmapH4Vmm +gbdKrb60ixsuBRdwWqdC+ywodM0C8EVd3wZrYSeaSskMZluhcCQGl6lv9pBqqieBFKhqfp6vrC1S +6GBaW/J+RZB08S1pY548A3V+vh1nbf2P4I4v3LBiXg/36yirVi+zCkko0LCRtK9/XXqv129veqAa +T6iwRctFS5Zmw9YMuo/y5Oqb7FPRAgcyE7qvJ/pKMS92RwtJgGqierhKVtVCCl0JjhsVhOM80QUF +iwkZF7/C7+6SZekUZvFmNGiUo5OoiaFJWgQgdjcEJZ1zPwwrB8b3xy+PwrNAMQf9v4QpFUmVowck +JsKjojZV+W+GrVupKjmlLirkPVmOSZdfBVufLdw7J5pKMEiVT0WDDvB/py/HaCMSSg9zBlHaLJfP +3Ts1ib9JpwYPWpR1rVRE8vYPlv7Z7Z0NXRXcz1vxebwh3pd+M7zu2S2FJ+Jw1OPHPW/aVP93HUht +dY+uEuzU7M6ikQw1ulywOLjSGagD9y6AY8lW7NXqHD9AjSDBG+tebBS2KTiwansa4CZ9zpJvxNhi +gn8SlCTiahQsMwqp+qQQGgcwCnaHiJ6hkckLRbsTHUMQkTlzriVMGFcnbBUlKK6MeujoWQwQudYL +tBbe4Blx02MZ0e5+SJomrAL6F/d4P/2Lc/B4kWCQtqnis4rRtUKfv6N9BLmuI3Yorvgs1BIGgOQm +S6VUtaLZvv8LzPrJE01WblfyQkn0ggPvh+y9qRJohzK3RarnDRfkwpBNUM3ezQrcKRAvKeCX4i4M +lusT5CLvuDuxa53C+ybt3bQSW9XLjs9zhYll1fQvej/czhuJWi7D8oCRVSCf+MeUxwmC+iGc43Rr +1KUDrui2m3IvTZMRHnr1QtUeJuKPO4lgzH+/C4BxwVGnmTPLmylU9VBvdHaU3GbVu0ttG/PxE6tc +WUiikRcr6ODWA8khpZd0JOOHeZOZgY5A4SCukgkE8vroCYW+zns5DVe0+ZXEZ6Zky3sGpBpUBDIr +esTy8yEI4XEZaed8RSQzTkDuvBTWUi5KSSWpd9/Z4bpk0zgE9ttMff65Z3qLh6d62INlPN52KA4y +762s72D3G18zFBsjWlpYXRmTn128g6NpVSWLpaYWr94etOlh0dYlad1+oHeO963AiEw5LS1zfRrW +cijEnhQcdOM6nRe9kSLKpa5fDX1ACSkedqT+qqUdpvs5PsWfL6ty03OoH/9+cDqmRMro2DXiamGo +gVtGgZHmY8ct8AlDQA6J+knIDGbgHRbLXDr2IjaJS/tq8MdxpLWlTH6eo8MKv0i1yYtVSfONDyec +KGkXdJjuUnCfmIV2Ex2xdbf/v7wtJ7KtWZmJmE7o9iwyLP8K7d1xlMZITtkcCA8IU/CxQlW6Fd1l +y+Lg0bli0wGB0RZH55xf0dWXtDl4kWZan9Ytf1RXW1LQVJHDTb0Fz0V/c2b/THZ4LAjFVv2HmKeE +Iy5ZAOoKNCPD0qDDwR4a6yqzruCs6RnjXSaTt3iRDbaRd0bG1zIKR/TNTzxJ4/EbK+sSUq+ti5Ek +KAiAhwF+LdYQPOC9WlGKph5ez2nbmVa2/74sMq320GkWH1y1vzc81WDf2KKGwGzdpl3HU3e7FQYs +CDcp/LuN1s/r9F4FCY+JE+2Wv+2C1ZBuw2mSs6NDhdaApIBKu2QOa+FxxIGIdlnMFIRTSfDqPZPx +VXwJQTzVRb4Fz9/DKsSvJgjGBYobNqYUAlXuprV4VOdeTng08T/SsssO3pESaXGSkX76YPdV9rQU +mCG/o98v1zrJHrKY44jJJxtR1qrF0p5ePoDdc4HZaHbf3bmKov0nPSGrkXhgCWsCzeDy/cb6CFTy +C88XuuAq76/35feaZYkKhXz2W9v3j0vJBgrCLsQYC8iMjt9WcJP6XKbpcR+p/R5JDc/Y7RUBIFZA +vajg6XB65DoG7kvs/MjUQDlbgJslHvWXxDqmqlLcgGdxIlOlVF/jFku+DMvevpksRH37IZxHD1kV +niRKw7XLoSi5d2qsvquTjIVciIcIlYu1qoLahP6nulFU58hRijp5hLCa4NRrUvSQk5MbLx98V+dx +j6Gqt1h+5tpVKRI0swacTL64+6PqQh5OxHez74JnRbFJ/wlpY1pv+DO0Dl6NwzHDkjAdQeTC5YNG +f6XWrUfMc1ea7S7m5lRJ1Jn3FPRNzap9Pxq3C+pvx24AAQ91R/a56KmNnZ1+3tSvMbRxm1l9RFHx +rB9myOBaqpUImZ9ZCUb3RNUtlWKiYdFOrLXl7BEbwHXRPkSVO5rcBLuH5ptO8NYy/PTkGa9D/1IO +csFVQOmSYZHZbcAI0qeYkR8g05BI9gcIl9Xk2HaZKlLlQgy/25yu3XnU4jTNO4a9sRAov+FMMJIz +mbIipa3UIbNNRnDZHGBNG9NSyNjYrHUVroba97bL1uHqH/hBJdu0Fy1TzyrQfHLE1ZYmCUR6VExZ +GnasRCAq3sj6xESZjfP25pSV8soCwN/8O84XKZw5V8/m4eTKDtWLmlHrV5pnc22RYA2Zb9deUBZW +3DPHl2X/0IXh1M7YTkEPHsiaB/1z7NCID2BHM2nJKMp2atBwRAd4Ls8G5WQKHPZQvhCITppN2bMo +bahjm4Yyill7rLKVMvjLl2kSP0dLnV10Fp6ZIxwtvCx9JNQtWpR+vMz/rVzNsrwV1mXYcRjgIvUG +Frq6g2OFS452MCG/0w45ShDLpZIbI7cO2sBu+fTMCpv1k8vqFd7fo0LRm3R65Wxk9jTLmZj4keC3 +FYPoSSaW58PAFKyVB8H3vxoiowAXB0qgqcIpJY4HmWYj0pN9DD50CsitOI6ScQQSOAiU3jKXngTI ++pSpCEIO8+5nETob7SDEYI4rpH2/hMuYlwz41/CW0GXQJnRgEWIrdnTgstpOtKgM4y1MQAjFUivm +oZRiZomPYtBs0TvaKht+Cifq0/fd2KQv/RO04ShrAnABlQvqXG4IMLdRL1ysJWzlLTxIZI1s9Tj7 +Kt78zWZ9CFtKEOIhwRww7DbYGMVwwTfXnB/5Zga7tll3QG2Lb3dwnsRyiNao7bkrkpVqenljf4K8 +um4SxGH0Nd7vmc5SH2kFDE5A6AEVtddneBhYGl8J6t/4cgFpWQ3AZSb1pDbeseVdmSjhdARAxK7i +VKHin70bD4VDW0qJSltMSFEr/iQ0/VJJrHXKCDahMX+Fn/mLCtW6UUtBjPmmggo2D3K78johmovS +6DMEs77UkgmYxG0pI3Xh+VRfsiFggS6jUDQyXVb+XJWVxyy1yGHKBR7AmrX5MjGFrBMlheca6q3A +9VbyYbSdM65N2PU/QusrsaDUHeS/yTRe6y168O38TUXUsJlk6ygH+87X4/K50fgXmW70YXiMzza+ +dvZT1eIirJdwFZDXAgM3fcORjZouKgPp91BxtAQXscnqd7iXRaxZtehYPop4wdXrka7Vrsdcnc/e +SEbgOg/PUssQspdLeWEnsd4Y08EKrYbKm9py+aPPZVqGqOsMM2gz/y9ysI2FkeSwfNy3/EpO1JyA +jP8GMDubwZ5kJSWf9V6eqfmVYcKspR2dNa8rVlCNtn4Zqyq8AhTr8hzOGfRxP+vNFiE/RP/0Kx5t +y164GpXKG0WxOE+8eV9a7p9lceznD8N4zUyGYtmaBUtCn5vmSFkWFpN7+opIMhaAZighamaN+Qt+ +evnYdN27IhRzdZNAcHJEuOLX4mzuZWF8RV42GJ6u3vrCPLAWuEam1nGId/+1AKeDF+bwabU6LMrV +n3uXmGOc2IF9CojjeXH+hPu6W3fToGCcOYka5PpvSzPtAwepRY3qsuEByDpqaspJcE/L1AxkX7ag +MZpsmdUiwweoOvuOcu14affwj/cWSX5PGJEvGERzEmpSOLWNHWOucjP4mYY/anp1Q3UHkM7WcuOY +GgU9AEsDsdeyPZs4KTAL6wUc7Oja69PLDZ4eVj1/AWsR5651z1bWwMnIPoMZw9biv9iMX2g0djq7 +VBTmoVmmO7q+fKrSMJseF4U9IYcGfDHCzant6q7OONt9DPNutArWpRGAm6KGHFsT5PSq4qnaXaBD +/d8QwJ0jOlR/C3u4uWepNsxjPNmg1Gv1i9+BC96cLzGLM2S13nIvd5oNjmvyyPWJl4jdWORxPUBt +M0gdpZDBD7KoYETMSlfnfW9Bbg5XWXtILuuCLsc/BKfPbt6L0v9VZLOrk920s5z9uyeftGYsAjt9 +WAKYFDZHYnLwWnutQIXXEZ+GggUubaZFmZ0aQalM7dajOU33ieD5/+QEpnlxRTEwinmGReKCTrKj +SDlRntnf7cNDLYz6x91CAkewnnjp8Gu4cMLJ5jm86btrEuJXOshUinRCz1qjhuEbcJNSh1dU7zzM +jLa6/HcEvcBSmdHUp1jbsXVmbhsDmR7VnDcn+HQvJZti4BYi75JnnfXrtYl0J5EsajgCfxW1QFqs +/qxgKl3MUlDshPhRI/ppBw3CNp808YizycmOUn3rAQaNDBNzOOEO416TDWF3DrPgTA7A23PYTbLC +T8ay2GPQgFZtNPdrSPGARNq6qgdj3+lcF0JVgt6EoPlTR+iCNWugWzEuXvDGXeMNjK049N3ANd2F +e74eDVE0kpfgTFrpQK0p933BWvkEEMGFmjoJNcTAkUIsxPhcl0YXS/DRTEWtCgPye3CUIYRm/FMA +yyjVhsWjfJsdvSuVNNqq1UmhHCc3jFe65ikBCjFTt15N54tGUpNsfMd6M2eStBF006EXB32GSkAr +FFdvhZhaeXNI+7WHidM/8GnfMhcwWudDsWqipb0xdVccRLYvE1PDaJ6FsUX+5Nvkw5q8/jf0FwbI +tXiGftuUmt8SFTj90hIcWXlpePnsqVvFQdap5x5MAP76OApKYSOxP3gNc2PXC/CyFc18KH7lDE/n +pcvAUTPf3lN3msQ7YSVWtpij+n5qajufZTIi82pRP1rlJafb0lC3qrUXicvkGSQdqTTWOXu35eqx +8mu8IL0rZ8ggEOt4V3J1zXqYPAukRDgEEEb6y7QBJ61PP62YdKzQgPC2epBVN2gDwLi6f5yCEwn8 +t59esDwi/Oe5kNZs5yJ9XVTg1hFcOBpaN7JGiwBprFvCbOBLXmrGxX6WmnChrYx/VI5fUTuJEZyV +0si2DU+0G2/z8r9dlrTZBWoxDykbFL85WUviug4+Cpr8o4G7WdPyDpxW0tusNnUdUQ4/MLLEi9kE +jNjYlFl9LrOjVxVZ+HL7Bg2XEKMIaa1wKwLmfzRAFlEjksbHBBY0VDPnBs3QHirF+ZcaCivzzy9Z +BqB/Lc/lHHbN3wz0ZKqfiiAeOhckqaKCPIWdDD6Xwj42LH1oE6GDlTwfGtN1TjL1z/S66QSGjIHT +tIJWslmsDJTZAXDZyg0EdvZGia+8yXoSHjGkUX8U6U2GfGfaFI2c2+KGBo7zRfnNWFEpwB5xSj+O +9IVHERcLhSh8JR10Ne88TjM2Q/NR3lh6TpKOPHDhnjLpSzHSlRRs/STZPJxPMRyVXleoHlQQZCw+ +cD1batMR4k2/yf8nSyNDu4gMsorfVbd60VUkytbSoGnkEcvSqDFmo5jHBuGMsJz5tAenS+kaoIdm +t69zYV6ToAzCKjrOeUwg7uHymfPcb3QoKL3cManBdmX6ScfP8gN9+rbKA7vHVLu6mxuwwsQ72UrB +5VXwauX7heRhjPl/7H/0yt6PnDo/MmY/P3reepKgB0Fp6SB5KCsiZEEWo8Fkk1pQVfc4aUSXb969 +omJ2rDF+ma+plYBHaurmYMYNyUwoeflRLi8qCldWiRh8/hNhxedalV2WgIKSTvgBxGYiRnNK18Ex +FRnxioQj/odENI/rwWS2l9hvrTFAg2BARkCAE4tf3Sxux41AI7He6770b63Gta57YvcsRTAPAz6u +DIYYKwR0284XKjaLoe+X1t/2G7yEOjJJ5AW1yh44Sg6oGMuCLqp3FGMUAbVwP4GQSpbeUN9dMJs6 +7sifhuYbnwgMy5FLDB8CLNjZZUb2GHpQf7pS4T4hTJo4hFW4Tcqxa7WsvFRG+STZylcglstHPId/ +IhKVganFrDJCstFeOpnsfcAOkE6z3pMSu1hCgaGfRxa6ifJn571hUj+m2OkZuoMWUJC3EAviFDNB +3voqUBY4XVtTkBJHyCw/RbfFbaLn0vBcg9sMKLiHoLW05T80DwFEhKx9q3gS+YWqm1J2IJzt9r2f +LMBvJk74S5VdJ0CEn92TdTrAy/DTyOqS1a5Fvytlwwv36yVE7iBOEI0k9or/luCyoCm/OFLD2m0u +3Kdhyi1/7bgxHyulA+tFn64loQvEQ/XR88aXnhjJBIMWfjE7CN0XdCMuA55TkfbUwIyNFKaSrBQS +8ZxsjmuXAg9K+ad1FFeX1xnVIwkQn0bAyJIpkalkYE49GEirDYL9zLGaq7YV83ePUw2JQo6LS7gu +yAcWjW9T8YwB9rz1qMLoQ/tA/euNkTx8pHw5WagtHV4vadVusv7QrPmx+Wti/MeIMLZrbOq3dkg1 +swIqFUDvGBT8frj+edQ+h8MrA53xnhgjp3gXuChuAir2nsEq6mcnQamldc9b3GtmvrXOsDUEDISk +kCeeeTS9Dp7noe7HyWa8xmmq9Km9VvALp81xuT9cfAFwRe0ab3vNOgrV9K9S69l7HM0wKOtCdaAr +Lw1Zn1Q1qigjCYdA0GR9IA0RG6XP2W36jscWboYWgFNmkwrtdaWWbt/bLuzw8YK1bmGB11jN4q19 +kxjxtOmuRBVBEOt0rGIZnHERcSptAqTf8Xqk8390TIdJWtKfm8qzHzr41Y9rs2Zp4IaoQCxq2fpd +CkHsTgyWczqPLacfOkDiJIl6YV3PJVsAd3Uw96U+Nugta291o8CBAZoBisKfCIjKbG+FR+8fTEdY +GB+fFWV92HPo+5ZLxreRb7TSwnTpQfy6aySmsGUsiQdAPeZXryOGgscHSqj+9HIBAmR/7Do7oa7+ +AoyxaOm9Y0oJGl2idYrVnK3JaiAQ6V51uNDP3w5yzhD06Hz5yMUHekvrvjoL/M60aje6rhycKp/+ +nUgtwRj4NJ6m8tzepg1zkzfkP1i4YTTosmmiUM3qMnbb2ohbQa12VuGnMREB1ZsJwS9z5vF16tf0 +cJRXYdb9yuZiS89VMkttiUBLvsIKtyK0zWL12bqPsUQqQuN4lvB5zoVq0ECuoAc9kmNsXTIuKCG1 +cRcFKqwU08vr3NVcuUzXIybyDa6k+wTiCvi5qPb3nmZ4qRExcpvjUXZX0NRkKNhHl754aVikNYBe ++qQG2J/1LhUm9rmKfgSLFngyIMYD95B2hFbdNb2Kd3J5dALSn209CvsqCRTDEwFJf7NQpDPUp4nF +OIGcFkhA3to3WHxK4twCerMOxVMm3OIyIAAadsArHEv7L8ZhUv7k4y4SfWk+0V5WZxCwLgcMmtFR +3+yKyW7A89klrz6CDqE9ph3l9w8TSM5OG+UnWkc7EsJlkAwXijeFwlrdxrTtDmpLAclhMtWcIViK +/ImZRiaKqzHSIh2p0msjpa5ftOgcR7Lov2xHkH6Yr8mCNvjS/yZIa9QLrHIBRRAIv85//D8POIgv +t5D1xaDWHZiemf7jL0lUXZWPNyuLOiYziTcEFX2GozxZDKIktOSUQs1Vf7+pQYzm+4uLHTlIF2sa +fGCRaWJL5VnODVd25OPE/XK4+w72HoR5yFuGVkCOppuk/H78gFUhtjkBkI8U5K0Z57MwJK4kDZnL +fOUHqEVOzw70Yc1Q5QHQKlE1y6biSAG5U5nAcf+znuuZlTu6us1X6N/xmeYdtDo8vbENLRGQDT+Y +vqe3eRyhhrFmI2cgOgoMFOA5yjrVoYDh9lXz1iRXNo3mObitt5wOiSRqtv7TjFIvQD8sKSSWKp5q +FOTs3fVUxOU0U/aoMOOfAZ1hwerLEcCE9tW3O0amCUh4E0TxmFgHdo+TOrE0y7G79NfXRT6NLIxx +suDd3dfxjCQA5X2+OlwKZfsNCoSycPNuziBqtD8rh+wEQgbxRyh3z7BRtG4tfJG0krinKiIwJqw9 +fuhAZ+GMI+RC/0dMc0inuj9ONt7uX+qrw0VZDFdpiVGF3xb3gd4CERBBXjC2igezgC6Zwla0+HUc ++zHO8v4ziX45KqvwbH5VhoRDectZMn8RuOuHb5GG1XUiaX7Qtk4hZ0cT7UeLo6nk7wdnE6qWCPps +9g4dzHcxD0AKybiSxDAYuHTYddtakXiU4hI99vc38O83nBFhPCyNq25tAvDNt9oVy+Mo6rmV4M3k +r84niUbUjvNaYGDu1OKGIt5Qbz82kal8UVUPhxYs6jCoONBPYLJUVU2bnG1FFMvLQDT0MTUDq6m7 +s54LIDovgVdQsi3wBD+IjCx4wXr9gEgzv2Au+fontSRLC/Jd2z0fSIWBnPcoto9HkYZZYeRbISoZ +X3W7EK0ZHkw4cd4ZYPppgOz9CcAvvpmvXPqobAdjcjGWNeeXX6um7SZpXYVU4nUIJv0cLut2byzQ +fwKqoY/EPGel9OLEEJz5I94WPUMyaGmmMYXP62eHt94p2CTlr2Csghe7OudZj+/cr/Qk2S3of6G2 +KZDvkMd64PPaL8lXcbl8b1yuLA1SFUifPu4yR635Sc0BpuWs6z1fWb1U7xFsqfmuPcKQ6JO98rMc +FMMT37OGyBIKDQ/MKkzHowF+dWumq8lxTejTnVef/S0zz8aNeCTr6dUl2kuk56dP4xCgIz7d00Zb +Rpz1VIDbJYhhfzjhPP1FyTYMw2WG3pnpNLSVWilZab9cRcnGsfc9vaqbCVj+c1ylqy8Wb0GaM7To +uF7cGKST8gXjJ9Ug++cl7XlLoGiQ+xeVwLkiT2LrCaqZABAXZZDANFQ59X5xsc777Yn7ATNgIk7X +5v4/x4HXnS40rVuWkI6Y9XsLRDN0uiUu1Aoi8CAlo+W0GA/qwesFsAPkHUrIfDuob6MsP6Nk84De +mGnDatc8xEcvf2CHhCsSi+4wHbIzLigjkFvAInEjn4fsejzQ7ZhjDYEeOtNXpdLH3l2pgQzXQiYh +4QirLSKj60LF1b6WbP9nNXRjiNaseVHL+z4faKERFv4oVwZneWFMR1Oonf+OFHVjJACxubZNibRi +IJqnXtA2kQdnDtD/sqVk3mrXNhRDam5xyl6z0VbL9gDGFlf11Iqy6pAv8H2zRy+fGP0jvLffpGJB +gkLH8qokwEIzGSyrL6kUtwVofIydM4Huz14wdQUVkgPCG6yhzwtcZrFPy7+ejz2wRvWq0eWmg5ZK +JV+mIdB7/myOO502ZOpRuSazQ0/kXklZYItB7xUpndtzKHIYb3v3/CHJIqr++6asIfLab3zZW8BD +Pjck7rb0fdfICmsJNwonmjTPD4Auz6qaAWRn+m35FhjjqUDzTOeEIYx1LLi0PU5lL4cQgO4IGitl +uqOMsnfHBExDL3McWlsziJPrFSy23mihQzKZ+IHccB6PSGAlzSPaMdKKcGgvZECol+7X19EjebVy +qhhSXkAl4WeaFIbYcq6PBKrDdvCVh6QHKkBWCZbFqr4WJpmyg7GUU8KuXXOhU5i5TJaUBnUunrl/ +Aj7BbTL6uOzn3EdnrepclzWy2BiKZoEio/TxGnHFkW0btJ7WHZVa3H8LoiTzK2fTJTDq9RIPTb8V +vTSGIFrc4W7ls4JIXJ+sZ7vjrUgsenzCYmG6xSsYXYgqLOktHH2w5UMkFWG8jwssiC0ExkTEdfMp +OppYnsP3Y3YrsDIsXN2rM9LBjhiqHWdjON+C2zDp763LtGmhOxRpNnDsR5J00x+ZbmueGrqrQXLA +YPY1YF6GOtFHRyR2N8zWOA/SRIr1preq1blUvcVRKj8saREBGljL9Wiu0vW1eDBIINMRv+wF3VcB +zs65d1RaVe4IBI7ytbrCZ1Z2A2XH3E9sSemtNe4ATA6zgKoeFKT4QyZ0VingNLlWSaAEXWygKWRU +YpGJVqtLsFoRycRjOThkE3MFiDi+jHWg+XGD3mGNpFDpA7mDhsV+SFpc728Q8xffRnFkWrgoBOat +KUu22x0XjEDWZr2gBFXOWYPtxV1HfqWyyYUvLJerqHiw/D6hF6hTjico0787ceROAHyNcqLHzLET +DHz1sfgfaUN+mJiTIYW+7sbb7JydSyj17TqC/mIS4nTQFSaR3zltv/h7TaGG/fwFRNCXZ5tub6Rh +J8/zN39jors3yefD9/wCbgJvl66LkuNwGvKN5wewKKRm3LOjhUFfhVKvT/moJYzhJWir06YdHV/x +umPJ9ejvqM08Lm46J3h7c/OzuUK3dzaKWOZgbh1RrCv0RAbfPpSdEtCOwtPkDev7RBwF5h6FqHIB +tXdnPPmskURYnBB/WqLsAFe+569fS8U3bCYXzB7l5VP+3Q0VkmYQzjfzTHtx/BGAVLlY4DmX/q/j +eGJ4M8xYVNGQnc39Tjv6kt7hIYiJPccVRnFmd6g2H6ot22PtPSgRX/6OgLlDFFtV+wqraqp237Ts +eL5dJrNi6ku8Nf+tqSPpk6zG5qE+SBn22YBRpkGpBqRds8P0NCR3m5PKqwvmALqcUSYSp8gehwh+ +nBT5/Mx1i8VL0/+mRpcNI+8Tmu14ebfFSQjN9IHCf/6MB8gngmYB+V5nTloIExbv59TEgYM/5GJY ++msyQdCwFZT5nfkabnyWHGRz/fgddqXlkYlBGbUpnW4m75gDZo/VjJnBiWUpR5J3bgTGApVgDnOI +zm2YP7t1AHBYu7KCmW3t/TqO6Rb6MXNieX8dYcOr0KiaUTbrnxPhLpCgaGvy0xeo7JoxrzsDLV75 +RIIK3bWlZAtseWwwHG5rIilx+smTR98osMZCC7vTdhBYR0ki/+oAbbR6xKa1wu6RbNfp47iR0BDM +2zT24htMtPteDRGvuBezcJcK1SAm4d9DgS/+TFoWX0yab4lxqtOUVKbTWUQQnLqMwsatOoNgZ3R9 +VLJnWLH1nVGonvQR7HNA5fjGbZ97OdDm9DPDcbVsufcUGRPBCxqur/tGd8JuNrjb2OFiM3cw8XF9 +2WQmzAt9+hascXvQxmaXOhMhUpdO6CYm+OlJ1hkyfKbODF8WE8COwmwAH+y0iwMA2NVgLRhLhA8U +sErxnlxxMYjv2F9ZL5KnLoGOB4h2IsUFIj+9cnq2tdrZzWUM8eH5WdBtZQSYKBjx/Ct4ySvRy1Om +kuUv5ygwuCZTw6TboSQquMNHocEaASnP/2KMTVvxlrmQoWT7sF6xV2cMotf/4qESZqf0Y27JUC/e +4jj0HXJZNfx4zF0fWaitWqAvM0ZWvjNcaM2ZVqGDmpM+04M4BYr1wt6IyfV1ArL8QuDZebRaieqs +ya+nwfYtTflFPpmBQuwtlaVLEMmTfrDFC/oPpn0aYv6sAqaqEVIhdJKhDuiheplx1HJinof669E6 +juXtnF0+9pL/SPFJzz3IZ6pk77OaU2hA0EIOe8TaNUJ9cv0+v2QympWhzW1IPaRRXXps3kfs2XV8 +xCHk9T0z8UNm9MRxgIX3GKkgT9iObnOFJZZnMFhv3Gcy8fcIdPJL97jSQotMlwmn5UZxs0ymkO2s +oFkKssoMLq2LMg9DKiB3rsoq+u/rWEyRjNnHYhndOKFRN9DMQ3MrAQa0vnv6gvuI3l2K2Get7RhW +IVFt3/gWhTZ+S/meNK6dzODtgMzTHKzWV/pFwNwDjEY50fScv1ZsM35yRtj4oCezIX9WiZUIjbHQ +7J4CoeYUnXWjYE4zxoMkSUpHbEqXPHRgejfWTP3ofE6fud0RKhO1SyehRvhxC3+o7Y7hfUcTdgqm +BzlsiReAWhoiIgrfkhUsC54aR340+rzqmMc1Hvf8eg3V2f63KYltMO0u4BufPym5+pzCMeEGxqif +PZHLlG5ZQcPl9HZfb6cbUPaxGAIQ8hc3I4DsDZUybAo21wgJKPY6RMuUUTcNSJrCMUidvV+IYKTf +ywSF19vS+v8Pv1NwSAzga8BRthp65XlExylrJiFT1tealb6Cp1wgcs0RlfLVMLO9mnmW2ho5pk21 +Z2NmxTK1qlTpSrc9CHxldXhVW64DleIjYEew43QJ+NSZL2WuPm5CpEGHql7v2c3PTQE9xUy4Sh+u +51cvuu33YfRbC3buwEwF2djIpHoyEpvpwXHb30qAIEf2k5RbUQataDTGb7lL3kuKx78o54N7+SLL +RLb4H4fQRU+5VtxVarCUKkvvkMTK2aOaD9Ee4y8ifZqL1h1INufEuAsoOE9jkHt+lM6o9RUNy+F/ +6kmln23+WQy1K5kDOUlg04jMc/ZSK76sT3YN7gByTWBqdgDRa7YjmcbfG6d/Re78ZsgCTPnKDe5c +ZIJ2jmKBvHbYwyVTrecVT1fCMJGHWaYQU8JxiwS8Wp5ZPBSxFX38MiTZ8kDgiSbepTAPhDMBAl59 +LSUv3uG89FBl0EJwrbyzUiwQ+DxD78y80R9s1QE6aSfxATxvGfvUUryV5OG6U554uLGzvLVIJ2Qu +mOCxAH0Xe4FuMBzPf9sDPKt5Lwk78FUCWJ4Tyrxk68r3OCceZmq/xOpI7ot67/9EDz9PP1KmHjCr +EzKTQpeD3g52hCYhM8op6SuvtXDWeM/rEtPgH50miWxpW1YHYpG9aUHf74/5TgLNqceuQc5v1tol +vTmMAXFijhh23KBp+L4SUNu0Q1KB4K7DfzpP4aKcRYpL1sHs9cvTAIdL9reA7buj8DqSB39bTTbH +otNMXybBPqhYm7SbAbslSKUzt7DH+RkVlhmeDbfmJi+4GmOTM4j46+o4K+nxMdVjhG+Ixxy/Xs8w +2h12Tjjt4aN3sGWm8iuPuPiARk3/oRgIOSMN0SLv/qyGjj98Lu/1RZMpyqCmyp8nPoLANQU8GnQv +ZhjZ6lmvmznfNvglzgH3IRLhg6QWT4n6eOOWqQsfVwGULB1kzoBHMpRRFevhGsZ/RSjY2ewSUQ/5 +BZrxV0kQLBUGWuDRVUR4omSVG2FPBjmL242/z4Dr3zLR6UnzovFBEMqGMAIRWaoFHnr5GkhdLjIm +EVi1BZRgxPVHZK2/H0NgUPTLV8HALJ+I0Ka2t+T7j7RuTrNZCmK134Y9WjsFb6UbKYZr/nAdAylJ +wFoQfIfKdDFrx01+V41Ne+0R/3Ju7hDUw4OSmKj70EkZkxQC/iyv2ieATnX3IHxAn/tjBfdqp/KW +C5N7b4YmEeI6vPzBf7Poz8YWz+kr9gCTzKGxPT7y/LvXymwRVwULSHgU76GNxUjltR2/PjFNE0Cj +f5Bu+DW2JcWyUW9smByoxRVNGHayDvjQjF5duYcyqivn1EDzg793qsgNQ5/qImzEygRsMKIKyA48 +N+glk0ypoQLendJ91mIuT3d7LAW1FDcvot44f04TtyaknMoeQsw68bGsx6Ojxk3OWWvEfFGJHB7o +JixYAZDZDku7jzpNvjNvke64L0yBpjtbfvuIqI0AhftyQKKCdajZ4Ewwsf4A+lmmZAgi4Xnj4GgF +sz+J9ORrMv5WxTYzQeuQLWPRGtrNXyEo7tly756FGs0mr6HL/e3gwxzM3IJP4slkTjnSFZ2Lh8ax +4h8x7CEzhEvFtHy+aM1lxdKoyfRe5M+KmKI33quoLyzfN2AnsfEpc+hNtucEetvyJQPGE5B/G+Vf +E7Y1fqYj7t2an13XjDXnzTEjgq4Lt4AdgehRec3YfVL7zMLkZpn2tW2vhc4Hd27SC08UDN2A1MqV +FpOpnnE/ZjyUUopWdZhhCF78houNAbATvBbGKsPGP37MaqCCwZ8QHJZ5AY6n8P9Nt9uNpMOMLO0l +drzK0290xi7bR/1h8iVj976yy2IQ9/XjZuRqvPY8YHzEeH5R/PzRv7vYEw/7b3BAP4YiQ0sVCpdE +uaJVknoukMb8Lxps4rYjX+9n7a4D1EBpEF+8NK+4th5wr0GItbg7bCw5tfxnNcmjPvj+808sL24f +g9HFiI5alslF8vLqWsjUmQuJ2mSyn4pKKGv35NKIkkUbPJHgGrrL/wh3JdsMN1xAlrEb08wT1cNe ++r9Ej0ocvX0mrxc5vvsO92yYxDI1tp4PpHsc0vDebTTsTbgQgQ/cnwD4q6vk5VzPMIcNDs/jr/CK +463x05rQyrz4VBzbfd67Vpby9/w7JPU4OLO/Dzwz2u3MrATISCFdH03o+8TPS2heGteuE8SFYP5S +2L3HriIFVjPopMDCI7nQhrIRedDI2l0EU31sC/0JtL0a1mKjj+McI4IxMcvxXujef8LrKaKqAi4V +ecpR1dX0SfgAHMDvgc/Mo9Oa+iGPVNU474Api7/SYGpxu4XA1NfsAVHOkAAS5juXAOZA0t65ibNK +1XaYYsDzQ62ILNkif1wOZMWPscqgPdysb89akBHwxybUzrUs9UI78nXJooM1uz7IY2wp8qhiCXf9 +37h2TLAF+5rxbeQ7EysEpiPZuBLSGLttN52B7zT47rcOu0pL402YmPEY1coznrTfaxvM0wJ2SDDt +lNge/fBLo1AdrMEPZZ58HGl9NOeK1eafPguhYs+t00XSYCmgjsCXOb4h+Bve61Rpf49+I/XEJMGj +nXUasL2baWm/Hbd5u7JVWF9EhjsKsX/s5OkyTpY6RHK97Ln2VtnOcNqW2FjBegP4UJsp1OswpuYy +ZuP423SztGk4idPdRRQr2/jv+6VvEUJQTUZBGCPQMr7u0DfCSWnE/VCgpRb/hZwbzMS1geVGEj7k +p1arhCsIqGs7QE3uKozsr4PaerFDYfE+DL2F7h3ptIn8D35m3c56Bhbouy7rE457FGkCGxOoF9QY +QM8SaW/X2XX/GX0oLePOYmxzTwYmriiKg7XbB5tnZScDlcq9nAv29dKAsJeqFgrDmA26vLVraJ+t +sWvshkhjlyk6SeSo+ne208ia7PQfvb8yw1182RzQBcYPtdOKaLR7ueRBF/+AlTdLzrvbFIk9aDGy +gwRRi3lHE2s2/LHxG36ldjVHXRPNxzImoXWzpzJ9xH3R8QgGnBdpD7s0w5RbVqCQlPlVA4euAuEd +j980oSCp/GAfNTMc5Q1/EYHSUCnU//nyPYXj2I9SXInAgnB69EV1CZUecYATBryyGCji01cagfYd +MZU1i5bufC3c858VB/gD5tkGBC0mIosm/xG4HB5kcuz0i+mvI20HQjWxUANGttGt2yfD2w0zinUB +ns/HEOBZ29qTC5L2fTsnnCBSqaw+33g4u3s3p8XQmQxY4oNTOvIv723XmhU9fI4KMtvlM9x72V/a +JEW7ws8T1J8R2yAS4dxphEV1Z+Xn8n0uPFO6ZXo7ElV1Pie4AjcKLD0sLL97FGRZhHrWFHB3GHQY +p1QshyYrUD97tEHZqUCRpggSi3hlMNj2WKgbVQ5c8JJbR1jhvdsrRPTK6jvAf4DpsL5Vv7Y7t/oA +I0kZUsn2Z0TEHh+lCljHIy2UE318b7yQwtNh32AQyvBiWIUT/tZL0lg1V/i7fv1atDdByQTGjUet +ryNuyQvFSlbP2whvTyGCkJDSUfsZ5VnVLcgQSM8wVFjFRxYv4OQWHeMkJS13Dhz2y0VE1XOs5IAZ +Yo7hyFiBWnLjoXVi/Tc0jaa3l5IVG59qB5GolyQsDhUBGgbz6nlsc3YEDEJU8WfOIKgc6r1k6zps +xEjKGhpa01X63QydqOaDatoJWZEEX7/sldxQdR1apA++31+GLEvLR0N7wbmtuu74M8deiV/YGHUb +eUvPdycKpg9FNkXYJUJIU1rEJgxNUfr7oF2w/2Cu4JpQ70krZc7tM+/mPngAca5iHVlrep8cZuqV +5TOIwanqEnq2BZlrOp421+SbioCyn6qj0Kk1EnekHwJTvFQAuMTMosL54I6xwBwxgC+nOgD0jMvq +3dkt1SdOoSySUVPr1lzRWauqf1QVOeBHrotbl4Xy0Dys5RnCUFfHFUF/ZLqZ/OF2zVRhCHHKAlCA +JJHmF/zxhlETp44DkEbmARhG2XSATdqU2lUyMBSYUCIkmr446GYREhn6LzshZxSe9gkjZOOcfaaS +D9T6V0zeFwu0KbB6uvOIFBZSnvToi6nCfgn50LSfna83sMAvEf0CTJHiGl0rKJ2DXEneYf8/amgc +Jn5qSu9CTa7xyNAsVW4o2MOH2UZurFc36FQloRo5GbEs5UnKxR2r0qGaVjsy+APKuJkkSTph3hAp +6fveYYcTkvyzSmFOSYlrRxtmFJQBZLKdLqWLArzkhnX11BJTHr4bEHhYyG0wK+NSrGO6OIOJFtIo +uxhwlnARONaAaQ026g+CeL2bT979tHsTNwM8dwlV5yHPzuSg5lCUcvmnKgdXAq1zLkJCk0btlra6 +pxwmuhH2xI8M/78OQOs4HNiHe5959lidVKD/rkYg8bEbtUJnMKN1xR+vVrdBiE4jUvuReIW5PUSj +GJfL+Ijbwusfg0FvICjUEQH4vXuf7KT/h+ZS1VlJ117np9p47QRBSLhzV+Tw6uo7M3omB8DD7s1o +JUb1akxXnAIDhwdfUIxUJkxL1KA9c5Y7lqt4L0XsrXurJKDNv+SrVdZAEfCibPKOW+//Zd4F2swv +3BDrrdqfFSI89l5XbpkG63SvtYK+KUKnF+OqbzFq1hWjQ66juz6KHwyEq2psmGyBrfGiQtc/BGy7 +E24zXx+YDpZEG3F2G36RgyquS3mNuYLwXwi9Ri4LXDy4P0zkv+qXQg50gTHOIIYiRIwI+8JO5pyL +CEfiABiB4HvDvX1g0wogs0wW10n8nfehmLjBowgey0NKN8F2xuT7X+jhBYaQrHVb0R55hLbh2/Ms +eI36k8zGpiAFxntgOLWIUqmxYsQYKY+bE6knkC8I/DZRNTDN2pjwt1t+MDcdJ0KTsWfPnfzhmhRz +bTGJxMLzV8k95znue2IxfmY015V9k8kWUAdJc9AMx25ZGpNd9jhhL6VOkV1Fsz0NBylXj4crenEi +cvP5A/nOBH9QzyEPvAQv4fzNjQlcjQ9JqNmN1RR8IOdNPeM5pR6SGqPiHP3cc1vHTUzXJavbGKo5 +e9AEp7HP1XqOTuu+4Ezq081KM6tT7XKF1sVMBUoe4toZHvrVOxk6BH9+dwjDla/SK8hsy0tYdX25 +U/PgUS+KLPAk8CsS8M48Nghun1fjvJNtsZXapsQilwTQspbGPv0GslXoxB/49pHWDdEP+ZZpe8EE +99WV29LX9uoFQI3YcNVrax5ePr8kxSN2EC70NIIVLO3eJzQb0WraR5sHntFxIU/9o5aJd3WrxG53 +q+I4PwH+gyp0R7YXsKow2OAv6n63zVKLzzJrxFWiEfbApNKzsudsknIM1HiB77t/S5D+TArtwPrt +OempNZxcyWNM+0CTdCP9IEGoB84j4wEUEJEU3B+byhYOYrzBr9sTMQs6KMcFqT9XiCF335APdDyA +TCEKoZipHfWaRE8636K1RJ0VoJg52bW39BTaBu3L7tIDlwgUwn12G4cZZs8SyhKlfPHAAFkA0Dx5 +AfSl7AhUxlL4/LeuuQX7bTZuuYlQlNEu+50LG0HERgepFuCletntqhIGSb3YL0D3qY4BZw3pIcrv +p4QreIbsTvE1PmQQJV7VsyRsDU0MEQIwjDXRm/2Qijw8a3VOe9kFGUL0DbD0CWznHd24vqTIYNwL +sYRtSfT4DoWEoOt+ldV8ZnTX1lUuVaU4ongtqRKlgzYwR9CD/mQ1a+nqmWmY8pNdO9z2e1SRM5SG +zPybvzqLWJzkDfxJyK+Dyfl4oyVDaKAiSm5H4LSH05QYrPXH0btnV3fey5i/lLh0QElH73lg4RPU +r/LCAvTHXs/Fqrk1BTGEOvaPyERRKAWHGAuMwG7dNBDkTNrwb6hyq+3cEYZEM5VmcTluWiExEKKc +H6ta99ohW0G9bH6VRJe+ivX5zl6Wqcz8it14hHx7a66KXOG4CB54c6FtZzW+Fjqcx2fMLEoGEJuX ++f6ZE65YSw7viiWIrEcG9J4k2LemVi+gs++tIuNJfvRPfAllVlzBYQrgvR/OwHJ5Rikwrma/XyuM +auLwo8pG2dXGPdJadsjSei26K2FVf0aNIMIriDUKzOx2cVog08zXAotrZePqiKq5KNDoio6k08hE +7SGGp9bEOAtmju7OIh+Ktz73ATDUHniW1QWj17GnJUsaEy6YhwQjQEl54b/wF4WgCVE8ut5d1bm2 +szHS+oTKIblzuzsl7vJPDPVjDbzkS2meo9YKMsbD16cpmVi+c/qwfCkXH3l+2VDdXxo4SSZ7zFWc +efRUfSswsbCK7EyN86wDA9tK7+NOMoKuWch0LRcQMFVdsFXZ6eTOCMj/sgLLBT53p4X+4408U30D +3j1JTlhEg9sL6q1b53dXBTrY0OQVR/DPdIcIV6MYb2CArxVGbuK/snSLwCwDOed77SdcrZoI5aJA +l2eVf4gfJOiGcNYD8jhzYjRnpTAC1RXjtArDyTVom23V+ORFEIKgCgLw4+ylIyHd6yNwYD6iGDa9 +9TKYwvRpz7ikBET+qZDQ9UgpAJf/Crn65K0gJ5THLZWk93XUF566CEZWMsP/TKAnR84UYeyriI8c +BY2hbzpyaix51ZUNlHVTGlmsU6ddY4bHAv4Fgyvqv7xgy002xzVA2mbrNAZCc246i2MSLYA7el4V +qNNwvmH43DDzBBH4JfqXHCpBgVMvjvefTjjFvWVpVk2cMjT9Vs6c92J+IZ9kz7FXysR9Mj7JkCqW +5F1k46yNjqCS6HWsb+K/pRF72oN8kisKQ0/+UwZUa+wgHu/wI7Ly+Cij/sHdKpCeHCSpcd/pBXuM +gIEH/e6vtFU+qKmvEpG5pSDArG9DquU+67e5cpnpoDgT8gQSAuWbAhA2fneTg4gCxE/6cLlkkJz/ +Ng2GH3dz3OABjLgZX7yva3v0LhVeeh6WRla/9DLgpx3cgRq2kiKD71i0KfL3Hfk4I5C0GZoJMsu3 +YoQNnxL63xmeJc1W48j0xhV8m4mk2h4xZiYxxH/AJV+48L+vwFcjrLGwUybQzgdUZpenfrv9gW/O ++WODoda1PGu70huk0p+Mc09dHM7QXtecd1/Wwg5MH0UnwKDuxnx5izVybvX83honmAz2GMZbq3Pc +uWGjv15cVg3xEgWn0vc2VI8kDoPb6xgT3syZ72L/zF8d5b/QHlIeI+yc3qeAX3S+I/rn5NhgfqOW +IXRrISE6WpcV3W2Nmznzg6tm9YDqYsQEMzFbEejoFw99yyNHigSNIiIWWOUcnaOuoh09nYw0pELV +wvlwdtjOUz1wVaLff2n9zMz4LnXWK69xmeHZSJkZesPJwmxyovvK8o1G10ul7XfeY7XCkkFPtRmU +/pfhbmZCQNVYdyiCyAbKnHU7ka5NMLFvtk4feGXY+YVj8dPcWlB76wdQSVoMY1yWidB/K7B8TsK4 +YAvNae+1M2+LSnpZ25obPqxFK/zsS/8xAZ3Zsm5sQ9zOG+by+Eeadjy5Gaa5vnAjvIh+bNSYeSh0 +tE+ToVXi51JIgFry/h145l9YQlVeeCqESZFBDb/i+DPbZVL93VzJ/2XkXYEHnR5jIazW80yyymAl +Ji/6BMUV4RJ37sZsuLyhAzIAIil7c+d3IrBBAJxzCOBUhuRLU5kDmh5YbVcWWLrqZ7p+UC4Om7ou +CBEB6/8p5aaNT209/tQ+xNpNSHZFo39y4Z5aRoLAKxQZiUfnYbpegAfUpvm6pdJVFpOWuXAJP3sd +b6Jjc3xBXojB9+rkEMdjifdAvA6OkwqmPTAeD+w3EU/9QXYGdzNAC1bwphNFh0wZoBYSoBF7xAdc ++JtVrQg1Vbi4NjvkSV+0iYqLOOQADXhbIw822vLynnL82Q/4xpp6oL8Vtj9fO/5EA/GWOnbCGfMq +qLtZnDoqpKzYyyqm7gF5pcF2ccEoHM4zwc7oE2NOJWKITg7e75KV++yh5IBNVuSFqXFHgEzHwCl+ +C0SkA5MGj0txDttD9O8QojxFGIuuHL5ucwUYmQhA9zhnqiXOoImzz/p4oPcAFY6cvE8zD2qmUFT8 +Ja1vc21R325vbekj4YY3wKDyRZ/6AYcN6WjQZq4jsgOmRTVda6igRs49TMhuQx77Ka67THfdoGza +UlID5SN+YBu5jAkTu0nsMI1aLb8Y0C34bGQa23f4zq9YMRV5los6GwoW6N2XaBArI0+MVKIZP7wR +/QlkjAYgxEdrHA6vx4bsQ15mz5/eXIH0WBu/L3Sj8Wdc5WHwpPVWWIeUqpTgX+SJHxvrUClT7OW0 ++lgpx7Gso+HL2uib7m0++X4w5rFUVV2pee7EnvnU6D4qcTC8osif26OWXMBQD7Du88fkMOwgq3N9 +FNXQks9O7YlucXi0euypV0jOt64E7s1Bqy0Gu+lYq1V/QOgn/zXKmcF54HiWPLAlu2EzsDWozr8S +4m2UVGyS4aRECsqDVnKRdzGVZExSCQXcZ+ucjjl/nCCn4fRpQGxKkkHNpVI9pe1Tzgs0/54ZnL0/ +v7hr+WAeBofkQXiEIbpT/0Oei6FzKr9CrrnggSApxVbFwQmSEAhQb4oWEp3RdQS+AEumyr3nTy7f +GNRZfG4OnK5ygNKYE8yKSCWdFZP3WJDVNDbNnrix/yzWD9yHisw/Avysa2ZMaSvh4HWe4k7Lk2kM +IlED2Msh3sE1FE0GECx59CT666iyGAWDJrkDXtKeQzLnURBeAqWeSL3odRDvRZcJH9juQDrHoBJ5 +OkmWqV0lskrFxDxRfch6J0hUBj8c85huqdO3ERDLGIUsZrzB1qbNE6kOh2px6MRzapvho7tk0m4G +GgBqfhO2/byesSJ2sbZdrSRLHesPhxkdL2AMpqVgZppMiPve3IOR2jopQFMbo/xPn+Q0v4GYlMls +PwrdUlz5lnasqial2a/fOvbUrzVNS0rQIB7Sb9zLQh/VkmEUVF2dtr8XwMBQLAFCZa1Iz3BnNO2u +8lBlRzGyf9+q/5gA1Xg775thh2ZRZYCbs6gZ8JP3p/MXicaJOoZHo6mBnZU+/nB8ZS5Ok9yALrvG +jUlArcq8SFN6IJ6f7Ru6p3piuGOY5To9RGIWX5IESuawgbcIxCyL3DPknBUCtMt+9vAfGCMbVYeR +aVggJtnmr492QQmgsJZM0/x02xeUdjBj7g1BsdvDeqJgpRUZTzARcDi1AnX8WKmKEQgFCqI+epf1 +00bDV62h7ZvYx9GkavlF9IAvKAofkVw3TXR5yTcZipUT04UaprpzHQKhrpYZO+/FIO7filCM07fp +Gm9IrwOEBm166o86sROuIIgEscUk2arcVUDGXudtnnKOjBRFLzQnup7JyCYKT5RTohxYKgve8yYR +R3OYitXFyeV1iNsY2AMlsuU7RNG7G1rTnFJ5g6wgQGfnYjZfHauxopqzxh0ivq6Wzr3yyz8BWd55 +cCDf+NMqxPNdNm38eT0u2eu+vMYc/THut2Ci03VYvCn6VB2Gwzknvc/JE4C16nmIberrs7hG86JU +ka4yVZucbZF6VYXOdHQYOzbC2/DWUkg1Gzw/CZ0k2kJKSnCkJfmcUZd8o73r0EVKGLa/AgQb8e76 +0i2wqxdMQmzKoEpcwVSf1RHW3A/ru5c4o2PYwQ3Wdqx9EyP3m01OHuj9qcDk0Pe8Vu+Xjma53Lu+ +NO/bRVjzgKjWIU3moOW+mB+0F5fFmJPDGXHDFoRmJ9HCDpiC+9VuVUpiR+N1agfjLSQSjwWV5AMQ +zdkls2WzJcVaUbP2FBunbGxpuOWW8kpisZZQ0KLLiWPyLiRH0+PCSHHpvT9e1vdsIwGekOj1RR/R +TMKouI5cM1NDs/y64mG3vBq/nB76vCC8LF7N90qe7K+9LMJup6VTgNbjAh1Gs27jpgptVVGxzBHR +euzgkkxEBjUIhM9nNG5CXG1p1iFOHuY0y2aTalaE0ouRNVSWa7gUPWdXPrcWXJvviKoP4NIEm0bQ +eTdduYwR9YTtf4mAsbsm+inN+j1ktngJeb6GJWpd9cTQ6gRc1eaLgeomtFElp7lJq5Wqko4v7dIr +iz0yPwRSt5fo+UJ9WrCEkgDvdh4jD7kHgRIbxCSvtNTlqGHf4vSX3t7RdKU5dvPgVTjCguae7l90 +79aDa0YVC32J6D9vE9BU3fayaSSuqocaGpa6ke8qb4jCqDkHBF5cp2E7eq8c340cZ3iJyO0kMvKR +D4mFpFUc4o023HQBrnjYpuAeY/wTmUbZCYCXv33ZcwOshzTXI+pu3wq3IC5ykKuL4WYpFRlByxqT +QArHQT3/QXOEuGjBbQB9F1zm/YHcWIYuGLkW+lVkEFJA7zPlHvDp8SzmlT89S9rV/GAyrA81xtA+ +2NCC4F78bN0GjAceaUDFri0oBRByVXMAJ0IkWOZsvehqAb64xt8+LxC9TQa15I1uOM2LqgDQwrxl +yM09FR+TAzzhds0ONNFVFnG0fOVg6kFgh1163uUSsFo8TaRDld0y0AvxyYJX4ali5hXwBC23+50F +VC06cUY1KyVLqtF2A6Q5UhPq+50HtcRWCkxqt2nLVn2R1L6/q5n68bsViP7Snn5jJ4cj7e/RhJeK +h22hdJJtYt5J3Q9O05Yj2JUlS04f5SpaH6Id+ubatUwIxFjsgC3B2FbwbV9HHIVt1IhYiUQ0yb8Y +4aeS0hgytBdIFjCNnDk5UeRt11Hs/4b/MFJeFaMz1ibLFyqHs9LRFrdbJI2YvK19uvW/EDKXmboa +UYJlwfV39XSgJT/DnCxkwRaiTDcEWI7/MCjiKR2zpg20VVLXpwR9lEjQJcEvZPAVFx4D79C67Eal +PbTTldtZGi3PZGXw0GIa3r5QluKKFg1GB4hkYwlRWxIDjdbkszv+mFpUyFtDv+ZiSfHD8WlyDlSa +bVZOZmqOGIKCiy6z+G97Z6vRNSlva1LFpRmp1OZledXE3TMvGDA/YZiM3/E/mlG/L/GsW7g2J+x7 +qcVi7EEFvIguPzKyHETZDp38zTZHHifkKNROYv72lEBYOhHg+ScfkuBLfJ9GW2ihi6nhzSgu6vod +9MgVaSOFGxQzI4dLh59CkNxgz/vfndcK/16ENzO2tvE7vC+rYlSeiPSFIHLdfzw+o+BBP2B6b91Z +pS2dMm7cJGpH53G531im4e4cekoNeBLen/FlYr30Fab3ToHfyk/cXgYR9w4+c9H4WdlCc2BeonDX +qCFO3+VG6/TvZ3XJ7ecu14hNBDMpU2IknihKpVh4KFWiZ8aBkhZNFeDvye6lLvK1GZIoIhRLrQVf +jlfk6///sLp9GWgTnUfO5WOJ2FfAh22aFf7p+yOMmIjedJel/NN0eNHRNQJHZswZkzg2FdWNKNHs +7RtZAlvmYdKbDnhdjbrJaTHUecAoJDF9DjAMey4d+pY4UmMLMT9DZ31PXBV+uXTIbDoxjhkoiPEW +fIlaoeh4NhUwJDQSVfQPpapDv51km14HIyZNnI+Szq9rUJY6nKegWB+F5Zp0BklxFUuC45bHx2XK +Uc1rgN/6DFUXD4z1ySWis1Hj11nCGIUj5iWZLF/3CSU+kws/vKptZHjiLPmoKOjf3Cj2DN0mT8Pj +FP3ZJsC9gcpNJ/kkjVfr0oiYkJG62Aq23Fd14uY6zoU2mvEqvNNPgfzGhipo2rVAnng8GFV05I1+ ++58LYh02iwjvbXC6uq70P/01uMKQXcCW3XrlKb0hjVRpva2NniTWvLgSjy4HB6WseqBVDWI4PC0K +/4QlKPECFDTi+g85WeZeiicawWq76TZ7mVO9dN/siWbt9US9XLdHmT5zjM3JPBuaByVgtvy3R/nn +/xEXldtPEG6n9/30Pusr8rR4Y8iWW5k0SOX8a2SUWTGw+pYCf4nEgn/8VctJvWbxzHDs4kh7jp+C +IKlU87zXtLu6E2KoxJiMnoBPDdF/8fz0pG7K2BXs24S/XViwQHZrzVovXh5WmpYAgxYN61ZT1XMi +0+0TuC2W+sjxQow1oscOmnsBbORfgmIDQ1Aybwt2RaQSIV/o97dpGIOkTia1/EVfoNTyq7zjAm/n +7lB5N4FDaYPbqCCG8nMgf6IL4qlroKVm5ReeWSu1aTYeppOJhnAWJDriYiX+1YKWPC82W9PcIUEC +Ke1Mj471+yC0C/49MWYkazTuBdBGpeQDPW6Id3wgfQQ0SUN+/I+na0vbsulOi2tXaVH0jljbl+Ex +V0f1RIZrMjj/vVYWeD+Nlw+imBEOJilgJK6FpjMZOR6CDNPt2FqtWms0vGDUvlAV/OG2Ep/2cSa1 +eAI3cB2rNIBdiGiENgMF1WSPil3FQnPW82xyAWPqQC0et2c8+5ikYpxQjEW6WHOdOu2DKn9wYDFh +Zkzsr50MxexPNSW1P91H28xG+oWIg+kY1DhLkBbuZx11625GpF4M6PVIA3t2CbavIHacQqfurWsn +8pNpby5Tq4HsHRXYh33dzim6IAARJ2BkBpz9kX6PLEpj6DTwlAITVQJZ6FGwkBgLrjFxpoFggkKI +DYripOHzeLJ+HIT/+PThJUNWTPm0+hLANVAhtZN2oWgnPmkqhPnXilVM5AfABsqD6qwF4LjePiTy +dirfRd4BN6CyTdNC5vYWmDuql+pVMb79E2qsY1H2iWo8yJsCd6eagyVa8RdOt7dxJCThUzVQ7VJ9 +XKM8YX9JQRV1yfF22zmWCYhjYs/QAhvVxduSob61V31YkeuL/nyf8j+iaiAuQzU+egkPk2h26F/O +0lRkX9MraXXhRhBZi1haai58Wyu0gnGHf9mo9LRpTnYmoUPcguDKG8y7DO/Ii1hS9qmjeIuUPCpT +wwDM181UUql134eD+WuevZiZ99vsnW5H85GDt6EWrXDiYXDpA7uDljNKzr59Eoj2MvAeri+uvXNN +ZrrS41qkff+JyijGZJRNFPyeLBkQA86w1QEYIxRCIbT/z2iu3tjmN3oEOduRENTGO5D0kj+hMKYo +AVg2Ktzw5yQsIcFEGnsDWIhCxSc/gF9glUGlVyOyQ4EmwcBKneV3SICYAvJVtCjBUQaHwgEZ3Ppo +Vjh//vYfTV9hlNiEzavtjsr/B748ExJhDAgTCWnlJKNrUwYkJfpp0rP9gBOyUAwoF50OwABI0fuI +XbyDSwLTnXJv59CN0wZtqjQ1FlSF3DefCLYSQUlTzRBcq/ekhdTRN70DIR3iVUr8h4DkLPlxhoSc +0OpMBcWo/OJSAVzDtBcQ+PTBqz9GAlC3uRYygHpP2HUedam82wwUKQb+9iFgjLHKxx8/y+ux1v11 +MDdp9NHUaNk36TkjLznKvJpf1vUz4lQ6hOZbHy7eQdc+bGQ0xoS8pWsuxA4AOyxJHo+xcPi0VtV+ +KZS/p0uiHVkwm2fEI94mJA0IRV5gX5jTh5/59QQjMHVFcmlP0yyolCIWOToPudxd7e/g8ERseLO7 +hSWpXgvnJKpHmwLB4riSmzTj/ByAaKNGIhmprfp07bvOBvnRtNQ1jDBPDtiiQ0XYtkvsDuBlpp5d +gHo3wVgxBoRmv7ceQySmg+lwy1tcmPZCXG3LMsvS46g1oeFl/aQPRmi+umshp9jfYkTWuz/btlRH +t3i6oS9+B5KFquEJl8PCoqwJNrcZ7DJZ6z+f7gRrvPOb3uAljL7uYLcCkop4ue0ZmJx4MFNrebBk +sN7BrYOrHf3GUKnE/F4Npmez696SaXQyMUtZp7HxtDK/nPGgkt2+eM+FmrW1zUV/pFU1JV/Itg+u +UlrWytUF5WkfZ8WzMlHhGypIoNDpQL0E5AiEuW1lMYICKHMINQTPkJ+yPfZ1vERwA5NXgTcLIZK7 +VhuBXqR0iVyESp1HebjCD/coHnudwI/ufMDvsIAr6XQoI12PD0p3Quov5lIC9ycIm2p5gQMy3KHR +rpAHSHItprqnDVjJRakKFwYmdZJWNp5vACnKibDxL7XdUFFu7335BcjJH8M3oeKJ/oa5l/guc0qn +nadnHRa0e1w9d/gp3z/ADIRTl26T68rQWnrAFn8z8qOI0vocvBvv3M6qc5quDS5eyYOTx/2zOIVb +8r4NKFmpRWorgyW5hMbd0iVDSM2zBpm+LWK/rKNwqShPngXOTIO84MX5HjS8dDtbiD3De4EP/zPf +FxmVx1dfHIify6VMGykpwTN4oLLb+BVsMIIXMHEL+Z1FA0Zv9eRvFF8mktqQ+fN0SLW8qQ+E3Ozj +i0xg2C2i0vqtrT+ywR4KjVMaSub/iM0z3ACqp4BWAb03/hfLcNmhREVG9jaUKF3gxqIngWWx8cBn +Giu3jRJtOdbXu4veJZNZdrVApRwpVOQCQi6l2AtV+9SHUAE7rXDKSRevHsVH01wFQC8NjnKvZdxJ +/QBVEF2WrGaRTlNTq7bpa/BUUHbAVOBbyKhGsKFeuwo3aNQwiETv/SaNdpf41LZh5+K71lbBeOf+ +BZIjqKcsf824N2WMcdGbE8UvA/8iLRDNdylPHoZ/1gRgp0sU9ojsWPeodWBsdLvUz5ZjlF0NfFz/ +tbDD7ct1S5rx8BRJBFsoZsH7HD5Xcjxm4oXHcCQhPoj+06f8NdPm7Nl/smBFCewS1tURFodPUAAx +RABrUsDaFJa7MnBy3D1ptFXxGA7gYN2aL8CC3CJTtEW9unzyATEKOfUQvyakT0BFcR2LqVZPb0Jq +zr01XJQZmimTJxZIR4iSsWLryhb1PeU8GAAfviS3LBOamZTwrjl0aK4dGDEHH3Fdj9nX5PW4s9zU +smUEL7y3s+T3gMIE2S2WGAyr/SwQ7Vhvah63QeOlLil6e1EvwUtBJfD6uj+kCAzaN6pH5iHGPsMJ +OKwWIP8Pot7jy1TbzhBgYcVu8FtZWrtZZ9qWle2lvYbnjYgZ4qFH/uEPIXDG/IESEkze1spqjpTf +aSBq4cqTvwf+gf3jZR6gCe79DRIPKtarbwLpc9H0jHkB8UeirOu/FNlTmJbzge48tNuuTPkFyY/T +j9q3fOEe0VXoJb/8zEHVGNu9deIEmLNwWtlrROqVozkmKy4ZNNc6PuzALqlmHe/2rQaIFVHToDti +ML7bZyRDRpaxJeQXQ0TeFMYthTwP7ty/HWLxjiq5A9Orev5IITSHBr7l7id7zWzKbnldf4NkTBeM +aNCZb+UtWil67iBRyBlUKnAx5uKinolg7pxnJHJouItM0jy5gPl9DT7XoiS6/HE58Ocg+L412hUf +lEQo+A1g0tEnhbk4hre2QQy0Rc6hc2tx6FS1bj0LMjfoQ+NuM46D8Q1FmCsVZ4TmlMCUyjpw8WTS +ToO80vAL0WmIw4/lNZl1q1y+z02FyPC4tsGQ69LNZWvBrTrmlWDOMh4h5WqcTAowPpB86xOEabcA +7Y2X4wc4KkPV+tHGAggDvkJYPpJipV/7nNa8GBbD3uG+a3MiKzHs5Pmcd98GHIPqSr7VKtYduAc+ +0giLtGidJ91+JgI36+XwXQxwYaIJtkdbhO+SHJwsjcINiIQyMGMMbXVp/ug3PUKNt5WNhHlz1/UE +jOP7U9oI6ATnbHbJo68VKoaQCRxS/shxAyOS+FUVWDwP8xG8o6GITfOZyPQxH9jvBh1sh03zBAv5 +F+STQ256zorv1YODROriJnTaYf2B++inGiQpAz5NNfnbSqS4jiAr7ydhCgB21u/PGaHYYWEk5OVf +f/JKw+lkldDelfDs8zEEHFChct4V27VrT001qcwgHj7bNem2ubamx/xjfUvASub28gMkNuiHHuBs +qfV0PNjnlaeQlxr1DtvA3z6m76kTzAxc+OozYF4F5QKVnyKAkjilOSG/ZFPOLYYwsHQeYZwQok4X +g9+rsjIPTRzqEw1euPtWJTkguIW/ZfGGxdWuD8qvKobGut+N/UA65awX7ohq1M+9I4D1Mt5mJe0y +eXIJXU7UH6Kn7qLp5O7Onke0ePVMapqHxU8s+8OPLE5iHCq63kObqDpK34M6y4mDIW0uSs8oayiH +ceyNKdrEoR36XDjGc+JQ4tyRWUS2qq2GJF6004yRkmbZDGJzundoQiq6D14IP2I3//zEDqKOGlxP +mkZlEjxyoDB3riM7PWQejKgT3S0vnI2xs4pJZQlD+775eB5Eey3rrkjazysEucRIWuXY8/IU0S9Q +56bOyr8hJp60f4CZiElnBxl4VWfIzxx4K5mbEuXcKvf26R9rnnfQT9xpeuArrdxDGTY81opTI8wU +bSZv4Q8e9Attz+prTH0YFsWXcVxmjOoOUf7NIOBGCRZv1pwCmeTV7NRYkdynOeBbpGvYX8Z80uiP +HRlHA6zzPJLEguLkcOZfkgzEbpN+4KfhbRShmj2E0iLugix0Yk6KkbLnBFeG6MdEkzvJgLLkVAaR +nzbchE7QbJ4BXOdm0DSiSwVYCdFiNLqzScjwBuVLfDsiGjk+XupZ3TyM0ADgyudkqCZ7/tMv9YxO +ASQ9YWfW9lDgKWRtPROybtZrVp1rG2hf+ak1n+N5z3WRaZxkgp03KaQ/8Yzv6/Z3S3hu/FQC6+zw +RQLtchtdu4khJNigfRd3Y/15dSsCtyqIouTMhd4rUAnj5XL72PA40EtZzDYDhmu9534IrvdGOQl7 +wsbuQH8Hux/Pu8Y6H6yVcs3/eLGMl8JvDVgdd8E9iiVh3UtWLkIbKNMcBW4fy+nCIENzyGLOtJXx +t7gQDqZ+kFt/FchgrzkAA4PEjkP7wTUPP4JNwxEWuUXZmfx20T0EYqOiFRD1XX5/5D9c+vOYAfp/ +ma8JdUZts5eekPoHdFggZxL1tsmPNyVaW7kFgNDtNRheaDuEMITOi6ky1dbJDoERz5wvl4Si1X/l +S14gUraLBiTDcKTKFX+JT1MnP9fb7mnK29Z54Kf4WR5qxmD/+j1whnnLCVfYJ8+98zjjN/ZX0EUw +MBv9Z83+86HWB/lvA4IjZ3IuwYYObQz5pSkOhqRbVD+HfXHM6qorKy803Tu5W2qFdpexS5+etD54 +xXpyQ6JElZjGNxuaIBSmBRpRxSkwTfrvKIQ+z8i5qVebEq2E3wg93gxY3MAxhWvGv36XzWSt+vHE +NuBghcCtw9d3ytLiHm1CwrimqKS2FKMXiQbhmbbW7owvGeNudJU+0hMWxPFWORCK0qflRA8h6L5h +iw5SpyVuf1YjasqzrODCPz2dheQ/ezHSsPFxLdSCE5yO6+L7rFhbdv2qkhO2H8JzY3OuTGb2AXXg +chyimYtnxb2+7jOPSd+ttvfNIehCXCx99PQKfCYo4KuFFfRkkSc/gI4/eul7iR6mWdmL00xs01GO +xYyXltG25RVElZazJDJ+iSW1UIVSUAiZXgYOkjWDad61+d5dGASlG6PZifsazeOI8WnqjrM8owdw +ssqNGxBVf+j91bPNbIpP95++tdlOK2jemT599s7ml7xIKNClRdJNsw8jeU6GdJCPEJzTrG45LEA5 +u8UEENLSp+t9V7aOD382Luf3i6qD30AfS60mBIOm+1J4uqH2NhdywAyRfNHBmrD0KkXgOPY6DeWW +dxkXJsUaiwMSnxFb5aWv4Yg6WDy4LWWETVRChjGI9zVAC+WUm8UXr2+MOfG/vys3PKK5xgG1TYlY +e7byI+7bXYb9xYMPneelIxkUh17Txo3UwiQiGizKgmHlkPk7AiWA8+K7Kjw/+QZE1fFGDLCWbSia +A4bmal8t6q2nMjKsj3GixjzxMC+gkue2+Ocd9q3ddPm0D7m2TXD/+BAXQmhd6BpSnIop0Ywp1Fjn +XOPc5wkYi0DqrAYUgdBWnP700MeQ+oxonR6ux3tKF2gmMEM6YocgFKKO4mYqrDNMYmmE5CFwYbrW +tsb2v9LzD2KommbKtLQMyj3rBJ6CQ3G2QUO6yD0HcwmIaS0zk6lSCTV/0M5H/bHufWK4nKcthAJR +rDXldim6AtRym7hrv3POuMgXoy9byPtiUNHA+IQ961SNYWWpKjCOGRpR4Fy/6QpSgBD/djcESh8U +vKIewUtlwX5ECwQHHxrx+eyDnugflRLint5CNnmqW5yWdaWUIJlsU+DYDOyJ21HTBW9FVBirqsPe +iMtCc7GoQ2rFB5WBFtZ5dup4h6wjCvrtyKVPFYP6twSp+TG5cHOjyOO8ChZSWmgTBhQNLhMoj1MO +/BOzEb4dTHy9mwEUVH7cc0O0RTXS46Gms1KRW+KncIMnTbU+rrRsKNNV1olQVWFhR4t35/SyOaRd +qEtADv9dAoMGNWD9QaNxB2NGA1F5KNvWqCnDqBVXYwaMGsZupxRKNE3jfOOILBbKAGZLb8yCymi2 +ntY4TOGr6O7cJM624q00Wzswn8DdK08Uqh8iQtpAMOMgasUIxANATI3LHzHQtKaaUoM0min5hYnz +Cie5+/PLbqvCiCz4/o1w7XWsxTjyH4H92xVjZevIKYFQogSimdIkx8Mp+mc6AtKpx7ZCzNTJEzVv +kpXd1uWH13fMq0XbbEhx3pzI7+/vaxUWzrbJ+w74jP7sxML5qHZB79t+JzsDcmar/c3XseBU595Z +rL6H0QRJU2jyxRL/0UEfDtuQfVfmvyfGJ0PHC+STgZ6RMaB789npbP0VsVftyH/5M3Pfu23M+lCg +Q6dD4akhHvNg5OGX5qBxBgiOqRWzW8XGDFPjgz6iGd5z/L67MqOsvhGyIDVWx0FFfFjrX5L8AuoS +Vga5j9Mhc9x1z4bdCCP5sYOb0b1jV0LHITXPZbCKpJlgllM65+a940338uG9oks60y5omU79Aunl +USSKojpOuV0gI500eFmz/ILkJdp/AQllBrGHeqY5evl2ZmkrmLZRgbT29Y5Z8kz0BB/knIdkdqWP +p1gt/BN6Sj/jBS+XopHY/LeXPUxE8rOObbcQxjlUSS0Kcz5prl1iQQErEZGkouoIUXsQUUWvP5RT +DSYf//GthIlyF4MCvCD07LFqAScP4xdOnSHSSv6OfIx8xAGxXqv3/GCDrAOP+YFHobA4Rhifin37 +mkaUgr9/ULSTXgBGLfld+J+9onDn+qMg1oV5Up9Zk1fg+bOQelBgkE2KVBKnOta1Bv5eGXOsYA7v +VEtdjbmYMYfAKCYwtpre7NN6urcOzvHKVE5NY/YrtzoXe8BUf8Uca8DOxoKsDuMw70Yx0X3tK2wt +u6uQaU59BeGUesMmrSjZk+VEBSD3ybFMNDeSLbkpDaQnA5GOGByWtnhnryvuKmCwFomwRlnV7JBI +EUVMX7XdCV0Vk5TC2xTTI8qVaueN04afx8pRauSER16fUNy4cRRncbWA52L//J/qsDKVPOii57jN +kpJcc2/6b5jhMfIZvPAQLOWofSyZE/3S5Kks+d2/LI0/qRIYIzAHDU6hXLx9qwzmSbub5TJ1uR36 +WURikJaIRJPFcYX0jO4QQEZ7sICSCw70Jyfg0J6oA1N8xmrdpi1lN+EtNOxMUUji6U23ucWO9TLa +PkxG/4wfAljMmZ65q2wnssRVXnOUNhOJglftT/CALECLwJn0vkEmnveov+743VVUvbNDCzXvNfaH +JyHD73rgmnHJNECmy2/Y6YTk2Ek4ukKNKwoWgLPY8IUSW7XzpQViQmM3CYxroKTrZ4ZiVkExZWb9 +RdR/aa+10PCf2cLDpns1COLXMj/00EBXiT518LFTbMKANo8ttfl5SydPLU+xmt0oA708bzLlpaFc +JGFeKBL8Wc0lEG7FMDuuja15Y4StsCnCe13XKLiPmgm0qOXQwbjE48BQijPAFJDfc+5O2rpwjJH3 +bSz2lHAajzgErvch7PdqVn/7R1Q+H3L1nBY5UxjW/cYNtwgcARRjkenI3r6tXhZrXo9D9hy9/n3W +M25F7Jfl3i+tILcnf+5iyxqHeZ7icOFcYkiG2JsjeixkvpyqkPd/3bvnU/4QyTYlRZ57IBndvqzV +Etig4GZXqxN7IY4fYxJdURSCJ3Y+fdVMLMrmKq0LhnZZchKLjjI221pRmxcAl2Q0WuovnYJuduGf +3Y/Id7+RFPdSja1vDmr5SoFC++qVMehBSh/KUfX6+IFq+nR0bBimmYUN57RfJXOiZkKIBr+Um+pI +mmKC3pTINmdscs2OeKtOOjmaRWIjA/v5r5QmF8pU8VtodIAmf/I/bx4FXpMSRoxUccYD1JopIidV +EjQ0RfDsNfHG7RhEgDRUBdCv+WsQ4Cic5pQqUr6VG/MzNhyNJw62X7NtpYqSzZJpgYjNFN1RHkTo +Cjm39fBuyDl3GjcB9XkcSL4gbwfAzxMI1ez+Ti3Qpe51J3+sOrGYbQ0T2XoQLysWyc1EAIjHvY6O +wtCnXTPr8tVu4R9STNAeG9crAUXMSQSdECQDSCtjvZBNX56cl3yQVnlFu0qkvtZg0v9fbc61Z7WJ +CxQFzEc227kbKeqzb6M8Ooks/pc1qeN4aJHy5jUoUl9p9um0OICQNZDlabjqojuRxnqRCgmFyYQk +Txk1BVpXvK5hV3YVN4fi+e0x3aaj9JepLebc4ZITPKp/JtAaYUOaTaUAs5pbPjy0iBfaVGDj9K2C +z9jLEq5BdX6OhrKT1NoRMKPkHLV6F+6Pd5d1caEZ8XBbjfzsAj7fNp3WrjwGkeqwzUAseTQyncld +/O0ncc/goBH6sELbIOmFP3vULqDGP13Xix/11AFSaFLQtbnjS7JqLo5FLH8H61/URQ5H7n5PnGCW +kQK8nK2TFVi+MYi0eGhJh0uy/B0C8MEG/plWC9LKui0KVS7bZkwuSjQymtnnG4zgtlm/LK+05Tb8 +ft4bSehGB+FWtzIu/qZjcBNKZI5WavEg72znqidFIlM/zSk/naya+u2LilOFWQwWlsQGchF3bZLZ +mjAeVTzQGxEY6Fp20AZtrs7iVdeR7Pi7YAcImFzBO39E1u31yiefj5w8ZIWXpye2qEXDjKZMquw3 +14pyG/yJ7z4bzwUROaH/CkHP6RU4rGXhOSr1Tis5oT55Giln4Q6qzMVISkJUqL0iRHwGIBs24/UA +ZhkHt3G+q7S8f7aHy8KuglYou2W2/SkDM+zVc2ZDT76Rn4pGi0Qtt1Q5bk+i3FONUQrcqaZrDuOZ +O5IwvGpapHUSHex0Fztwsk0U8U8PvxGYPGz+nEDUMPnBz2qCut37fjG+y9d7olmCSYQNBh00rgdb +wAOoSxIFiQIeLUGizz+KCaPoAtp+gfMh293W95KT0+SM7/YHM+vLqbYPJip9Rp0Y+DYzGEOFlmar +1/km8HjisQRy90xM9hEtMzVGBcnAjzN6YPVNbCLIFDQQa679oIiEAopbrPkS5xUK1lWg76PXfPlu +fRzK4CxEosHzql3FBQwAZW4KHuKMspS6UQKrLKzF+YAMIsAPYSyXK3NbYlgU+qOcFo0PuDTjgGyF +VoB601t611xeP5WXAdOLKo6VDLdO/2evQV4T7VaE6IoVZhd43LmFIZOAyJqBgyxcs6DO2mthg7zU +QOAAXpT8Tfj6UCB+L3G5fWjcuq/hfhksLm/NjyKe4Jt6k9M2mweQR9LBkZLNEytZQvz2zkJxLkHs +kiJSHLr/FfFNoKIRPDAbWfmW5DIIjD9FIfxn3Ev0YcrvLNV3slFhPIUvQwZmEw60imwFf0j/0s7k +8vmX2GOikzlG5MePp1MzfHK7U7s2U5oJOa9lX0j7QUVUk7Tb4WuGlaG3fAgGPefi9N4uq2DHEhzV +ah9uTM1oD0Rj916M2bch6KpK7e0Ma+9WC5FuQWGHMoxrazEo3CdiFArG/N2KoBr2Z4ihfNBzCBsf +W/xJZQJuaapKCg2prDwOccPUNxESXT7wo4FeCsCbzYKhF4MaBylLs6w5G5tK6ouWl8h4LRzSdZnW +g/jG03xpeQuBMX2NK9rYFCCUR4Ri7+82SUd6VvcZ05R6IMOtIpRpvRgJgizIVMaSozySuMOpnohQ +GkWn3IJDYGQwLA0+pfQmfVdGmJmxmX8wIQ+XIeI9DjbCmXvIsrO5fGt/6O2ZZCaNXksvmqOx92wk +cBSahQHFt134wJ+sp67ElzT+ZAK4WLRUTdzmtwcgXfQLngTSdtNwyjKxsHaSCnDvJ3FaOulRRl00 +eA7BJtLRjsN/R9H5d9n2d3MJSbCFqxVnTD+cqpYrQVZfkcHm/u9brXd/NCGy9eMgXqDFbXz3iG+B +YVfaB4LkUd9xpMaNbKOUH64XS0wtaiV112b1gWdWPJ5ohQJpjR5SJ5yYscaolGOChi41TYFimqBY +tnQa3+o7LQaRTjHvt87ICXemX0VENp4bdJJpgoV32vWDIGokj1I6OwEkNb5QSWRiMBxqVzL9KuyK +Mqod5q0OSubGLS05zQcutxeY8nyCeL0Y7G9CBZnXmWfPTXX/txQmvIHYFqG1GADi9rF0pRfBaac/ +gPeCGZLMMgIGs/jk4J+Jr/0qByJPidOeWJW/QEP5tlksfvOuc38FzU2FGPrqxv6jzQLJxlfokXMN +W3UQE+XqEACaBlcCarfBaaXzljHdyNmKaiPFh7iV5p88BVPXmtno51yES6p8cs5CU+ZcN3mQ4sP4 +LbPrYzIaz6e1SridDTZenIOsLINNXHJTwDoOmfXYo/+0+S4q24F/NhBH0HDJG3VPN8IBNN9id+v7 +5IiGkLP05PD8hx6G0mfaY95ra43F7g6CJ4psk+SKivTgvk2hT9mow1pdmZHTIKwP/DdZDWtpe11e +9M0t7ySRkaT2nPkzlP3b6P+cbY4X14sHn+UtQHZDSqdMWqzMBxuWc2/pDgVBGJizBikmMS1+vO+M +T4buQVxPJ08By8eNf/jYWrI/imP290YKjq3PwKeqz4QZbLp+VSPvtSWisgZogoNLh9qXdGXXIS2+ +2JtfTuZm78kYwGFk764rVReyWReSF7FOSSFNr7AlhnetGTRZ/QRauQB9GtWglse6tdgza5ki0dVi +5eNTZBQT3NVMvhV67aAiFM9Rp0ztCMGHPeEreymZ1REUSRhl+Ib6Pxlb9Xf0M9dPuQm8dq2hJGNh +MNNRQAY+DexMJ7m1OTIejj7zcr+irpLh5hVOSjQ3e4nehna2+NXyiYJpZYRpIvN7jlasx4aOVrVH +eWQSBtS14F1sEXPN6iRK8nnrwaQv327vswBs2d4sQubJcsy9+ltjvhyVW7PNe6NjlHFJcOzq3WCA +08G7W0iYgX789q5+HVuOdzSOi+lTREkuKW/ScE+BlDeCtXnMxhU7hqRig9Qvfk8hV6yZA/vd4bVu +CXmA2BTklzp+It6zVLDKsX1VRbv5hf9lrilm69eAGyoqovQFxDZKttqdUKpPDEbFHl4T5zEZRkQd +KCCcbmWP5TaJrCE4m4seeNB0ALl4ahBNs4b2eOLM81TzxGY96/F8BAUV0AvBe2GkfjphGMqGM3B0 +3d+V4FIf+1AECPYSHGtcD7rwMVfcvsZ3llpFIfWZjuF5NcPGk7g74iaxBkjYjUebk+v2J6b6efCu +WkkULVVow+hipd+qsFEpopnNqQaSXSGww1Y6M5xxrDqEAOO9VumTwD/u42Ib7TRnKk/IFEVCU+sV +xkJsNtwsmdT9fZAHuxBHGNoPf3Q2nSRo8V9dz+89js2OwtRE59USrT7kWhD3cAhQZRIWkPQjz9lJ +/zZUsIE6qKs0OR9UjVluACRoJMrC6xEN6Oky4KOXt6JtoeX+G+3L1YEu2NhmgMpuY0izQ0I5upOj +35YLsiM6IRdF3rH+nt2WfrhA91YMmN5XwhUFWSWbcy9+NtRQ3EX61vQxD5QxvmLGg7PcYsDR+El0 ++jtuLneWWDd7pC48BdlNVcY2GBhflf5BUNlQvzqQACl5j7hmTFoi7Zkl0vnWelbEQCVsSrGjU1J8 +vPe0Tk8qMteD9RvGdbqQbuYRXMfFAr9aqXAcqReerq7KH0H8h5ylSpjf8XbNXWMm+WO5AulWcMAT +/xdPYf/LRJPSZIMR9KEdDUKsYsEkEyGYpg56iZdndNTNXeqB4v++UP5po7XXSlRRYalSgvfKD4WM +hf6eCnIwn6mevT7HcWP5kbbG7EM/WMCIRc+McpIvU8K+oWEhSGiBixQPpKAUZply/We2RjWClC0c +hojWVj5obM1mvqXkx1IDOAVQFFxv5NO3qsLngwfhvGMWJlDYjfZ7RPzq2xK9c7+G9ETiBVdZOLYG +piJJi2owvtzdDNWYzQN1xaIxYTwl1ioyjpkPSNrOHycuXRMdn/U0QCUwjfdVP2Gh51k0rS1WYTt3 +/gZ97+M90yYvsZPPxvB1joNYwkicJKoNUJJOoTJDizbt/FAF7Vnb5H+aq5B6qI8uR3UXNvRL7rjw +b4LG044dRAZNVwF+MPzkt9ix86ic2ppak+pPzeDo67ogodIoI5rhqHn7Bper6FGIduM3SSNglb2G +KcEI4BF0r51TakYDF5U01BPsgQu/3AL+5whgDN7VUtPesq6m3j/eBZAtcE7olHSwS3auOWhmDiwO +sVPoPHO+4PaW/frv0wbdPJrHAx5mn/0FCUGizTXaSIptTxMNf1GFPNqgyDcsc0Z3OT8A8Bcl9pTA +bfelVtNBg1J5uPQg4Xrf2XBKmzD/nvLDi08numlc70cxQh3kAsUAFo0YhbOp+dCGl0/iYEICF58A +ANLnpekaofvvOJ1Dgyhb9GdP4vaPp321JtAXvU3lMGtDH54wSyIQloyuJEOX4Mt9EmdHSBZmhNcY +SK5OxL/NnuvYQlpHXof0FkJxoeI0/wVtF8T5wyXzKQw1NFWpVxvsoIDnvYg/JYkAvsBH5SfEor8A +hdUroWNlchXKQmK3jC+9goRD4Fon5vZFgOCKdFdSfN/mxNBnmijNdAwEPtk5ID8eN5G3AoOrdGmK +/iil8Tek24tCPi1tyL8xyhCF0ghUqdUmhOos+DW3Z3xylKk5biwcDqEt6SC2nHLS73hmgGREOZsD +8Q1FLExbL6xuVJWcnbSc6gQbmquvsyuGOZ4asWyz21KKETfbSdgWguMfP9gXWyxr25ay7bOQI5eH +PU+HPqWAgGoliG9u3tQHcwImkcYovZv49vSXuR14edeIa6dVwQZXiqMJofLGgw28D4IMaFP8SxWg +bUS7Et+RDzm48xdutcwiIj/WbPgCBjD+E5VqxGTUjcuxMFnKyo9Ig9J4jJryDzLq9xAZuY7E1y1/ +BMYyZw3b427XU8Qks/sSZoPWXBD7JJsd+SPWxBoMhyLiq6MI9b//QPLuy+P1g7sXF2kpg7kGT2rj +8FKX+kE8uUgzTxrtF+8kRTxalsc+rAEAzo+eo+O+nnVd3BUH+2YyQuMsRCR1v2yLWJQX2qTL3vpO +Xfbkp00GIUJPuABJaG364Kl6pxQnz+EEjSTAvkCTNLJkSNe2vB/4Ojv6tCbsxuOji7sr8QO/Ojcj +eCMNo0olxHaLv84QzwwHkLdSBYtdZ3aZqqGnEKGhxnt0tKpshKLU+ia7T7mbVmoz4zRmMFcEkrXx +5Q+HdYcJuNLZoa8HWkyoUn/O1zZePkVusLA8lMvPL0l0mfLsgH2PFMkYqoR6LY82W9m1OA2URcm8 +OQ4gHZTCoPq7eB9Rv9p8aH0Rl506dgZGA62MoSFXuvOKv+bshU9ergIO2lt6yRNAV+7imm/ao4OL +iypUF7ZXx3jYU5OdIlNXqfHdP6xHbtq1YOHA16NZmFDXGPDfQtjxSs5yuf5S1qZZR7eR9HdjK+nx +UeQVnfXR/9cIpvz85TAr5MiiMfwOtrxPqe5tfD3QaksFhFTvmRk1qLUcYO3NQNcT5teUUx6qEL+S +p18OIEIRPhb86SoODbIWAzkMWAGibXBbC9bvuPSgrpsYseq0X679X0hW1kxpxIWNFodCTz8dPH86 +78+0DVLjCjDLOwrNbhK45zVq+SZta2xvuME/zCnrzTBkOHoVuBVqPNWgEvDkWjUzkvlhyRKMFMs5 +ryEDgM6fXw7fqYeq3rTGA86cRK7JfBhNRNjJ10LmpFSLIQqx8BHnMr+uAsc0rXp2w8ICiHsimqiD +JtK/LVteCGq0i44+2kTaxSz4aW9NQyKVpepb+9BCS+YYQZ3pXWvuYE2O4DkPcUX5Ktq67EsRfPNW +qVIR9N6iqaP3fyNl+52Wxv+xiJ6t9ZYoofv7o1ypxeqLawCdm4KHwFq8ZnA0gDg8d11DmPPdCa0S +OToe9D2+c8iaRDftG6ax2+Zjwh4Vm6Zm7D4ZoNRIc13/QlwYYGG1sorQ4SqfJQ139yRW1rPyIG8p +YWQ56WjBlAYK3G2HPE/p+ub3bHl2N+JxQL7wmtobkXQ0drmooEqAAMdPA94wNyX2ght4olpdiSia +haGJK5gBoQxPGznbqMDUqjmz4BJT3T1DperebtX3rtJhv0zPZmYpQX9gGC5qW6WSUU+1M8a4eVzn +dtPKujMsHY21t2vR1bijBhsbY/ULpz5FFmQ2Wh8pdsPWhu6QRCYseHli91AWAjbRXQqMwFK5jRzQ +Yyrat0tB/YIIwYL8vRhWD/doJjPvWdsSlK8rn8v0n+ZwQtdgd4GJTQpXT7F7vV24bbl2MfLHftUo +0loYqG7BBpMe/2vU1+mDEId4sMKx7Ls92yQY3K7xHTu62hhtnAYCzbUc9r0eMu3SZKWNKxrAyPyO +4i9taqMJdNnCYySmOYeLYrR+seA+ohzYidoMF3cm044uUzvKMvB6MudeNwmXfpmRJoxSOA535jqZ +bfNK9fOi92E3AeJfTKAr2txJg/kRSPESpoL1d/kMXZsAZBDtLIf8Y7+GMITWFUV2B0QVAnQy9FPS +06h4wK8pC83QRjRIIwk1R0UUIRp+bM7ojs3g/oVTORQ21+FLKiUzG2+VstDp2sR7MgMRmVcHtUMr +l+evQdE2IFP7vCu4pkMwe0EYe638Dh35UhDo6nA8Ye29LSKvxw2onIcdQpV6AAPN+XkRgQU78AZF +EokxG9+qTCPZ3vHY0tE9Ekcab3k2B2cFwVlu51itz5lPHz5Aq+8SXuUjGpxUdrUz47GkyjBFqCM2 +cjYNKVIlRCthWUNUrxUmXHPyQbIf3myKb+P6hDmG/eel1aIjI7LrZHwI4AGFVyJ4JiduZg/GbgyX +6IGPKU32rGFGYN60ASbIxBfNeAxzGf7u6La5ehZ+Bo4TpRLCHItied7ccsCpZbxnhNB6ePVHqtvS +p7wGw/SPELaEniA2fiTPBTpCN4Cd0OFUE/R3+gjRG1QT9szyip0C/rcRfvHRvhvKEw49gEDst+f6 +nHJ589wpv3USIy0E48tgd8TV0JeKP/r2XLczj8dUFC+CC+Xi8MW+deQLtxVH+/X1N2XD6Z5mnh9C +igbQllCf4XTJDGnK5E39Mq+JIhkpy7AQxvxQaWc0JMr5VtXjZddKM5IakM8Ayf42i4k3M2MmCRaN +vDomZe0jIzuhzVSlpQjtlefO7anqzObG191ZzzZWOUO6ZF3iZSm0eOXLsx8ajAg1GE6MSbFIIdD/ +bov3syK2I5XDPzD28OHOmSAFBnL4JUo+9Jahvg9I5T2En+g9PJohzfz2MJYQlOViHnrK0i2AglFP +96FQTq58fPrPsF56M/Dp0OnTLZOudusKPLdav6KZeT6ploIONhp0uXntDQEOPcppZJciWOr6fmFE +WmiPrKsufV8uu9nP3+eN/A+AKUyowKhnEpjBa9s5S0nSdMUF6u9Vmv+6VZzcG1vgQE3YmP/S22tU +u+pXTaY8XifQNHyMu9G8kDeLRPRIAa/H2KKk49HLTrIHa1bxE10nIYkYB2ejxbx65z2Pt3eSnuaK +N3ib8+D5pYP54OQkpzUiH/xHg0+c6fKloVIZ1AIwJHGRpCl5zSlzOZHXZZ7+knwjHG9pOg4EnOfc +2x76KiTENHzxzoD2oMgTAR94uWbnPRNVK64p1NBCHd2LDuzurhsC2iFXbfC/2Dx6g/XxogIij0iw +gC3txj3C72E6igK0j4/n7ZcvneuzSmTTPB/qMrM2iHSJ05yGJYm2WDupAvz1QZDDXXNIogjybcYJ +KJs0aU9ZeE1JOC/KErGA2hALESuHdsxjZTuDY8n/TKxeqhc4tOFa/+lnUY6az19QW5xasJJSuOYm +XW4tX5jqwi0LW+fV/afz09MJ0rNMhAQyMIl5XhL8vObWBjU26mo3GIvkN4ESE+FHtxpuyc4j4dmw +XP0iOP/ONDFstAB6/Hh8z4AyUdzc3JW6HYFJJUSpnj4YRmkRUpcJErxT46TomjtbB8hCVfjWKcy/ +bR1Sd2fES7l1T31U8iIndtHCrrl7jOyp3TFpR5XqbyaYV/jF5Uz06O2gPgMHxPYhP4BZd97gogJX +OQaYt/G211uVqyh6dJcoy4rA3R0BRnluIWEU1DmO4OsHUAPyl1sQ0ozKhXtjYJgOujLb5aKkmpDh +ZC0gCyOKJtIVfqoydX5LrUVdmAUkBPFB/E5I0sls5aoZ504oP71CN7AbEwds+IIFvsXVD9DfU2ch +Xd39p7scJeXzhsH5bDql5ziuWht6cQdT5mlAlqdL79vw79hMJLZKbghUTUcJ55TfqC1nrE/S1VPK +AkKiNwSG/xwcO3ZW9YDnj6GxKcaLvrBxHEub6EJdbpvyINRCm+9AToOsSWescDIDwjLfkLa7/FEd +g1Y3o0bLsZsGs2plDMEkNZt+rBQ7NYAtDBfaDSeZGdZXuWl6FA3DmS8ULGFlDuz3k+pE3xjwJiDt +Xh4IAtJUvaKDclItCh/RdmMUYZ1Fw8xVttFfDq59LdDivv7iS7Ngi1fK+TMghluqPzK9eLFCgS+U +1QkTSsoBnRelrMVShuxcr39BGbktF585uS6MEtZqDDby1cUp4i26eN/m+odRlboScX0gQGPb4IT+ +4LlGjy9xQPiJxJc+E7cw/+BZ+TNc1hMXdFtV0F6vjD8GRwqrngM9o7ouMIjUub1k8V3twV6KO7Vg +gQ8fL3FSh8IeUE+ifWzH/CpcYE0P+SV+lq+YHCuUVAtoQlFufE/EAOozZ0Ai+N+lvokFERwMEBrM +i7mKuK2Sy7i8EMt+pC9uDUx5EQKuHZaSHRrUJNd3EUE/Dqbv8pqNn72MdfvMvNNrGMwbjZNWyOks +fS/AfykrXfOdzyH3q64mP7UQs1F0YBPcR8OSiwoeBuCv28TzVk8jzWtfE3BubpPEZs+LZjv8kmwy +qNLgCBifpo1ec9XrwQGDi5xtS2yir3DNBAnExI1uVQjWqKspjyVz+run4DQ6TcrOOI9JX1uvE+1Q +V/Zm1fxyJmkGIoGbhcjv58u/Q31eMzgFqxEGVwLHyo3aeiTB0mMqyXEB364r6Fox6NytEsSF61/t +g3CMtO8JvwrCipbJJR7XoXFA/9u59DS95bnXzhrPWNBS+eVMpGTrfnrweVz9AFe29UKdZUjNlgaW +iKeP5Zm34SlkAawhjnA9VMa8jD0Ofe/bmE7newCMROIw98idGvgzqWL9CMO9naZUvjpz2gEhi/KA +G62MiWfGN1BL+tnElCTZJll+n40bMx7yAQhQV19e4gc9yN/oU0cBXEkMAY+97zw8Fui8Y5q4/4+V +DoFxBo1UA1KqIP91VMEIhvMVX1L1TM/Ee1uSjYu/p98iq13CX4/UpSzlhLm9Vbq2f45P+Cm2g7BT +TMqmup/TN4tB1icQDkwSgSO/r/D0UsQ+5YlXKjI7CfkbSm//wJcF0KwcbdxfIUS4deAzb0KtKstF +S9EV2UxTHWgJ3R1Z47u6c9RQLXp+9uNC/cxEpudsiqWg0YUoh/8a6HfjrXRFTY7QSMAoCd9j3VpC +ZuBwVCFrsnBOl9h20s7QrMBnhHHgdEtbU8aTUvXTeS49jM2kIPzjMJplMTC3f7pMQ8zTtlN/CUHL +V1wqg1hbUCx5qYPGlppqe5hsONyMgCotGPTbppyVRoGWeN6o7oiNhMsj1xHrXeOooPsCSFdqmf7v +7dMgSeYwPKlHVMhABqQPN6auyjEADJTasvD54TnkUXTX4/WkJoU8nxhyV2tb2DVR7STPaHkq1R1R +wp4SSPEykZ7tf0eSHgPmN9dUOE4awBXS4W3iZHcffQrVC5IQKUMgpmCzVnMwgxo0gxJAxSrbATEc +x6kGukOrWPyZRGf67uQSkaf6MSo38cUCDkN6ZhQlIbL+fF/3P9hAXreguXfCvU/NEHSNmSRba1u+ +1WTbTE/P0bJy0fDQZ7Mxj0L67aUE/82GkXI7JNNkMX22tw9JzeJD+4k6OSjavmYD+rBgi4+bwXmM +VS22mnl8SNWhLzWZt0PnfgaLIkprasF/VKOcTCRiXiF/yqtXyve9r1bt9CVDaPkExTcjsdZWQeHu +rD52uGww4bOH1i6kfNKGICH3D5CjNWkWexkPm0jky4+/QvBxbmPSEJ2C7+jwy7gV9ybcddSHDIpc +m3IToDQrjJgFZuhRVAK4euVvNW6E4++Rs1ZIWX6oRfbpDjlvwM6CMGBtVOXX+4S1CaJxIdZW+adJ +XTG0n/NeU03047mmOzJDSYuByiabTRlUWefAgqSo+okzWR7KxqDrM2jk+7qG2ZQrURJtYtFJxGgI +dnSMFZ9ltsjWsgTL8M/ZHuCAPVocizB0zoMkGuv8+mg+9fQBh6S93jd2LtYanZQirDvrJhnpI79Y +2+9n19Cd+Ss+IO8okPBj39zx1ETYrnw/srZhhEKxyAZMBorWjULJc3vaIbqhsJJRGAn+U7TYw4kq +VSqQq7HKdQnccm8sARI+fkwXe7oTFHqDAB8kLrYzcOSgg5/ex99hz4KOudqQRmIzMHLo97400aed +Dr8tCME8IsVojln7z3MolnvNS3gDoyxCw+g+rKq0XwZcEoc6YMiGCorAK9VYt7k7Y4hx6xx+C0qt +x2RkJHCWedwEQ046RkeJAqB4IxMrUjtStiZCZIMxzfuhTjg+0Q+RTXw47ubZY5651OtAVLfq8buU +cmlfLNhN4y3ZEijR8/Y/mYUOFETHctl8yMQeX5C/wf3C4cVVIAm2TCawbGAe4Zv2JblnfG51lJSc +ynN0sAgyOraMIiwqTeNpS3ncp3IyZDueqNF+TitjobGL+2WcyrDbhM73NyORrvloKG28Rm3Nvc12 +IcWjN1Wzj3f8L7WNZYafQDw7jVxFAafiVdnCkkdMFlMjwY3A4Y6Sb7kyvPMtu7ULORxPfGm8x6KT +RoxXwxxGrc7gIx4LldcRBux0FrxfNuypKo1uqw2qrZ9JyCwtlI5jDFMpV/KDxNTqp3ygLruc8PYa +nOzJXq8wc/W0lOJgs8phUMJCdZPCSxrwUvFWhykhQWNV3Kkz7yI8/nMdKgD58PzdpHCDWp8AGLbC +RGxraAuD3IGvSd0DYWXFY4recsJry5pIJDOldylnl7aWLQ1Bn+sj5OEIVxG/deSsQ84DBkhvLGQa +c/gwyCz0cow/HHimY3hpsU6VFao5dwsIOYIGgItkqypnASyiQK1vB8WGH9bP4aTbw6OIsrwNfAce +AtAW4zGwNXnPGZvvSvFfzdstMY0M4d3fvcUb2eIzmMIRBWcZ3zBD69N/D6YH3ehWKq6iInIDDGid +WvHF9Z8AFTOyFNeBed/bJ1gGY38bEQXRefP3v4t9KLZN9HzDTXY9qXbbw0/iGKx2S5riFhlu+9Zc +Hk1+OTTmkJP2TcUj9ffGEil6jjFq2xg7FOp+8c99XGIu8SZrNni0GOD7p5Pw2fGk6DiZiGJJuhTM +0nUYGGXRn1/W/SQVyI8ui+ZA+fvTI5xnUf5RDUNFrWVhuOnngTxIDLHqHfMZ69vETfMztLSJkkBN +anmhIVv5tGyEPmJIeBJpUBrn4bNlIfkqFPgULP+ZcJ7MpHYuxcRklkSRtrCsd3YgZY4d6x6KvRWc +NV7xugUyYchaTo7ZXeG453y+/QQ41PYiY2TwK+2btJlZvG46qLjkMKwUEGBKOiW8DrUuYHWLL6gU +WvPrG8drxLCOKzervgiJkkI25K7SH+yVmGk9K4Bd8T+uD2lH48RWItryEAfxxNuBpr1ie84gZFm2 +oud9o/mIb30eMVvAM5qVL2P6duROh7vUF5xkCWOHSJDvYy/e/QWmE7bd3xhJwnuP06qjJI8GGO2b +nu6qgBmw3g7p1R/tzw3j2oreD+wVia5b69cn2axZ+E0L5FTGuqQQh1hSWcRu/aHm+nVQgSrg+f77 +Pr0HLn5eHKFkV7FCCRwyQNN0+e7zEUSUUFC0fPc1jH7n6wlFRJrv7C3VWbsvBcZbfyQM3Y62AQOD +Vi2fO8+joLuW4hEOVhwLFI4iz91I93cVS7ros/2q2/4nRcoA12YvGUk9e189Lmxgpqt6Y5X7lgID +/UvLEPoFuuO7bsIoKxw0cg7IBgw9yosb6efejkP2pLfb1cX/SRNcFLXRxG73nGBICg7wuNH0oPX5 +1MHKZoPaMkTnXyDA9Ftllrv5j4EeVWFYSR/8eNZneBYmhbTISOgPPGcdjYsmz6RxOc4fec24uIa1 +sEiqIcYgGrUTfyGBdg+sB/PTxj1KbjA2ITg0wn7aC5syvZshQBsAkMu/7cBI8ud1zbeyuog/XWCz +q4B6zU2h5cI41H6hJJW7IGGmG8JZpatXFqqMFLvx5xG8v6ccm7NDJJkbXVnMQvAU9ICSlFn1S/dy +alJ/9ldI34K7fY5TUqwSO75EUsqp5/pAwPbst5KtkwnSYPk7jdMDd/pHjBxeE/BotXmlZUupopAr +Jt5F9zpvlYfTc1KVK8TDagJ3zK6Z7rYYFfhZ2jBsG2fHK7kmduM27u1PEU66EUfuklPBKoO5n1uR +HCj81HOERthtXCemEZjzOzmrk/Ow9b3TGqh9m/bl2M/8JT+OXqGT8s22vAPkJHMQNJVrgEJ6ST+R +pLoEu15Gf4xqOpCEobp1keCH/M2VA9hVN8k7m+uAtIjGP9hZIo/ocYeCCe5DrVXKCq7jOY8G6emE +ItpbUX9Sd7g6Xuxr75m/shp4AAh+YrbTL31JT2HmLGl5zkiPwZkAF5Px0axmanCb8P9MFixQlI++ +Po2TlD8dzOY6pUZswlZxghd8/BoEdYSzSUvrUxrt5g+XqG0lKxku9fVegeb+l6pRggFOxpJo+7nZ +8Vpeg/8AgvlTh4B9eoCoFpmNqc1HH+IL/q4c57Dl5g0hKZAhrV77toc3wVZzkFao60YWMXdr289A +x6xH/TazFoXDGE4GwWjiwpl+I0T/qxH0u5lyZrjVSeXU8Hi19+SWBVYYgVLn+9sbZ7aPesuPHgQt +BMHohkERB2ZJOlqYpTKBD11v/UMhrMLPM5HOI7raXG+S/zYKXkqEEzLQvXkvAQ/RtYESocBt4YZe +UKd4lBo9E7d4krGn4FL/JU1Vh6zJvBQ1SwyRR2T0DofQuboyO83AUQDw8qLK3zLQ7Zt5KfOonT1r +qFd/lxO9jnsMWdJWKriuS+T9P76K5LskvCH1uUlFMRkqaeYACtyvjcPFV9TvAm0NoGXcIrjui62a +yvOL/MvhofbqqcV8furstEIFnaIiCJJhtPtg5D6LGn1J3HYASG/hINaUdpmXICoy/BC7mo8I4nwT +gzv+hX/XY4Iu0rxb7iBj3vVNOP7rF8KLR1PPlhu9N1S/osqAt3CkgS3/mePBYxzVMa5zwOighiIu +rR6FYIqcihoSLF1PyUh2yHqkZKcEPKJs2enrGEtGFX5NXW/S1E/IRt4hHGfnyMJmFHD7xFQSWPms ++hpykkKkxODKajQA9KhY+M7ak6GdQ9k3nFJuTdnGC9CQ1VudcrcLjJSc/bnKHWpKiq53DDRB5HZ7 +fl8Ih/PD2xUXJ3AAE6nu0v3QSE7z9CJ7xb2zMBWx54el3uoIm1DCJagCD2BnhH3hmPFv7RPy0wWl +HbCb0OjNdvNYHoo2k1Dr1GUVBR5YbFJBuVTdOWel8U/3bcX8pCXGw1BaxKxqDKlNJTXhVT5Q6K5q +JPtzYLYIxJYGM9xELPD/aQR+Qb6jLVY8pdJM5yja04yNLZfoOUsRN3mqFxkeb/dwG+yOMTWTLCKi +hvv7n3xH9UEmIRGEhH/KdN4Z0LlrhASJqxdRDup9fD4sNi/n7lTfh/+vDjSEjNsi4VoDwYhAghkx +CmZeR6dY21s5/wxTOpgqHJq7n7wyDwnumnSFGn0XODOSC1A29cweZOBy4SHx1GPrQy0Sp5MVq9Ci +VNLcFbHg7/zwrQcX7bccX1zgfc/zsuXm0Q3yPTdrYmz3yb5ChXTt0WrHlDgbZThLGOmIVJfI0KRO +nKRI9rf0JlfJfYua7RbGjtg4nMn063zyH0atJSjC+Q8Fxi78jEkPj6cqTgI7jyS0F1OuLFF3jFE1 +zg4pQEsmCMOQTUVoLDHIU4yTEni00o8cT7Ftijj2PMzRAhip/lkyxT0Bg4M4Tf+9WvBJXC7K7znW +pTA+/nQ3aM7PpLdN5iYREVE2m1ZAUY3JwUWfTTwdv7X/v0mECI8yizivVU6J41QWVcg5F9yVwe1Y +LUzQKK/7J/hQwuK6d52GxTZjRaDq+xtfgtd9HB/9ini4IazhjJHfVAqQSueoNjq+nF8qv2xD/Zos +/gaEZuI2LrCXiH/zStJ6ao10EzCumfqBHKi20oVgwhFqgjZl82e4B+SKH9NutjyNB6pTEIRG88Wo +e56lFVPLTcUJUvu6eZwPUFB9De0fY4FO1zBJrHBJ6p3VfEQa0zM1F+5E1yXBC+43dnbXPH0x73nI +EsUU6pHX5qHcwobCI1Ac24O5s1vh2Pn99E/xFIPhS5mdrcY/bBj9elwP1tpSkl/kqnGBXQKC72Hv +MNjntxXakYdPlkP3uWs3j2CF14c6zxk6Gwdtn0qPxM1V0WXaighqndODqB95YmT8I1HjyWasTy90 +/54vqUYrRGC/j+m9j88xjCL/kYRjrgkszXZ4/9pSOKwxv0gMKtKIDDBbBxdBKylddIDfSXf6wgb5 +T9ut9t38VgUWtqr+7UKpubUdLAx6+Z+037MRaC+rHfCJjjlRDnloufxmjpCjamnzOpIHLDux0UgR +LW+BxR9m+9VOO7euzpQQfJcblcyCGFlfkDRm/aKafJUXYDKHRhFxe6t/HU80s8ijih2tnTgVyXKV +HLjmZU/4vMfweEcnok7dnTZ81GIh9A1Kuqj4Fxpr9ZorWJnFhjCW2JZj+zvpwDIFK1I/5pUWygRs +iFNp34SA5L+VeJwyeFCpVAHisDJ7TjFJwmKAwS9l+NY7N1zkmyHXnWvfP7Ku8oFxyJ67Ld1X8CGR +51nLvHYaPQRaPKRBE8PoSm9k9i/vft0p5EeL/YJXZ52Mu/8bkVqW4q1iIt1DP3+FzT7qskUGZAoM +Pj3fjbFm8Lq+ppabR7aJ/ekEzKnqliMjAqHZnssDtEW1ZSd5agwWMnSjKMQYnIqb6vbcD43s6AbU +6gsb3zpj67S5SXBdkU2ZJWGC3UPb5uJyqI/E+KNI5e07afPYyYvYX5oloDfknYK094lSUR+TM/Ek +vk28u9guNcTn/BXhsxpw8ikaGYZS8zCaigloqCQnIU1zTerC7ykqQvlndKn0wuwBgC9o1aCnoYcG +1oO6ZF1e7AoUqSXvuIUGeIovubMcz+mGbDUblfeGxZjsct/6JZXyl7izTfnlAj0/RyjN1NMXFv/D +TTKIfrrM6po5EzACDWMz782QUSPrGbe5MYm3NnF53bWOSBEWD3A2bTTCa6zKt1cWyvqoaC77Unp9 +4MBUyPl8g6LX2eQ2k913w/rhyf4X/6b/3Jaxw4k6ejIbtsqkoISFp6ERXbMlTEpQVaCobWtaFCwA +INKiRZHndvM+lJtr8LNicfsX3C/5Sh0MJefsaUBn5AxQo8Nk+KNT0kDPEweXgJPiKV3w9biT+OxH +a1cN+32EAdr6ZXuKkzURC++1+snsgTcHBzAMC8bkmc7CaKUdATUonHsT3/wdwYaGXpDKeo8TPAaW +++qYDvWTSClE+YqSFTqTSbSz2ECxoeoE3G7N7JzxjMdwm5bzzvkz5Aehdb7ymtbGu0QbZr5uOk/C +USYvcdvYe6ubi5e12y8ohXsuphc6BavUjEjMntWJH2a74I+YwInvG7XBX4cTcE1SPzxYBYN328ZL +4mpcALMfNlGjgIgPEPwL8DsaKWTix/lcxediU00DduvxGyHBqr2Yz4p4mKX5muRScRTBihEd/q0F +q7iM9X1RWoIQi4HeojJZb9/2/lXD0DgzMd24i/MZRbspAXwFS98yibbYJukFUvgZdfM1TgyAgUBM +dBF+c/W2FNQerf6v6xNPgik3qf2ye0w0HCj9G5Fjx2hlPWJghQ+Nsm8hSxPPf3z2XyRDxae958nJ +9r0QQHZ2eGGjYZeiiFteoZM3WBTaBv5k5xp5cvaKKllrgTHaMAaoSmMZ+HkUD3r0vgsmKCt65S/V +JJzypIRRKxW4kFn4S6Nb7coz6449xZGxTGwW2cLzn6g8djuFl7Y6Xsekn3NVokm6GFKqMiJMgu+3 +Q0Gu+WOTAOx/EvgOUF8f0ih8CUU+xe5T+SLlL5tYP+0QivSKrjelwYfLK2Yc1r+7Gjd/6+H+xg9B +QmBSsbHf4Mi3oISv6RNbn2SUvCW6rISDfZTyAgY+atIRFWXZuBnSC2kZH5Ot9eR0HWQ1LuP5BtCM +nLlZukZQS78EpRNAbd/BR6MTGeAvtY6vkfiL6F1z0OgxXKDYDsw1RowCynLqDnYRYXHuc5/UBqrX +UyPo+wn15ghvQvzj5U6sMgyhANIfVr9qBFsNF2AxTwZSOC2tWVs4arDHns2fW6FGlmGwDa0slp/r +RcDgK3w5G6rqjtI58kyEgrKWMzLnjr3ScQCosfz2fJIjmVLttE3QWSoTSR2fFZP9hSToPWk6JGl2 +MAvQrgOSbX+cf+mbwrEF/a1NCFr3IjQJ63yC0tuThd4TobvirbpdVIaZUsTv2i8eGznu+DOp8m3c ++ybgNf+Ygg9riAnMhzBt4j/6Lyb6PmZgeXgFEnVk+/nyfgs9q3+dyC1nEzhk6eCR6tz92ll57oej +7jtop++C3klPZJeFbKHog1rAwl0tWMZ8XHQhu5nm8N6kO6YvH1Zl8UF/bzYK6eAUktIa4r38+8pV +MyggDWoUFTfHtS1UljiU1WHz8MkYeYIWP5z8FcAia54Qkurb/Y0k5Rps1P4i02C8mUV5Mtm5R+0I +XX54DQYmTUaNafoTXQY6QEbrYcG75g49DMjhgwLHPujxPdtVk9baHRK36wMrSWLDr08+styyytkX +FlLgOj41H7pBodlt1JBbpxxZIWxdFaJsytAh6u9sn8yk2FmI1NJ6P4BbjUKaqEAsqEBkpj63Zrek +8bUSvHLCLaFdJyrvcWaPN81YHO5zBNzPOvjUjNDTWqUFBRg0Lx9SzUbJDyn8jvLQjhmKTXKbzPo7 +HYU1fts4qm2LYRFm9gsOKOvhLdXMi8EptXSIiBBVSYJ7NGQZiQPCSidF04zfzmvvfw6QEV4fgzMb +6Ns4Ddc9S9wOLpj93XBEzvkO3R+i6WD5TlmbkQrK77eREEBr9ZZ7Coi1YJ/o8pQtXig3hWGk8IbP +UbUpo2dM1rgKzFN7IrYNtV1uKV4JGrreZikE2WLWcCxStMGaRvJwMfbk4HXrBIFAjF75mbenD1FA +CbKJ2fkwGWwv1M1wIUFoDHGgXSeEjTxSuC4mAbiyv2DGUCUTJONx2LHRGzlsvn1U7vLa960zQbmS +fGlWupwRpZf4ledwSDXqI6nIrI1NXOsfsc8NQBipfl6bAZwCbu3/hkfkliqHPZoCgM2OHlb/bWTH +k4gpwSYz5UTnOQMSzjNYpsnbkXBQPJtMLicFHfd6VjiQvOCS1ejIbERynyhTGcTutLAMS5yruAl7 +nl6jdWLS2K6snWJdxapqtMbn6NtEMHHhFxYUyPmxZ1Hm6f0norHHnCBEbf7R94n2G7fO8UfN7boz +bvklM4TVkHxB3t80yGzWrPJKu7il0IysNAobMzV9YuoRDCdrUQq4DPrUUbj+Eka+b6ZhGghdAOGE +N86/g0G3Aji8yswonJ3lohxBy72iZGuACwFKhu1FCRr1GfxG1lWjEvSlL40H8z5yhDG1pLK4qUdc +1h6e1AKIF0faBAmiNqvtmzrF2tDvHiFxU4wHzv81sdPpme4NRHy+hN8wC5H84BXD2/jQcejueU/v +mBlVbi7HbUJQ7pjsaaKFvbKB+WHBXZaHknI+g75mz7sWcu4negSG6CoZBSDBoxFZzEB0+B6q+QSp +/z9PmJCuLQWxRceZmKfHNM72wWRb4prZ7r/i5vv9gF8IgRLdzGorq2V0BS7bDKKWwi69l3FLyVWv +x+34vWXrC19Vc+i3s/lyms6WGwOwNNYwyCSW5QTj9attrnuhpNHf3XHjfe+gm+bRpiOrlZusLlq4 +iSavoTSXwDW8NTp3OXuu7TcEH2iopCRvUhXlxUVGfepmq/ZvKbSh60QE7Rg19oyQJKRvd+VrWyqg +r4PDoVlW/ezRDmgLrl8be+Cu2mD5qZhEVpxKWslBX7olWlr6bl/vtXUED39IBjx1/DGJQRuYLamV +ytHttZX/X9viDmqY0nFvA1kuzwJT8DUCbFwpVEK8W4M9E17PofAZRjPUQf9jHVnt3jT2zBow2j8o +4OnQzUsYusSdS6Jzfzkcne32GNx8Q39hfX8MYlUcqD5xcojlRrpboOwZVt5Jh7F7kGjMebypxSsS +Z18wP5aBONo2hBRh9xQd96X3S/SsXF0fuoh0avK4RRlhIYuTxIuwCL2ZmQIGA0z2+TMduY9JC9ew +IQmoK+3DFTgJXpmf52pD24pd1uKKwkonuvx1HXQel2oyQunucNIXjE1uXVASxLHTXhveWMW95spL +p+JJPbLsWYTLi9l3LEs0clNdPr2n/rB5jQARhIIOZH0hfXPq/Jxg+WWdHT/0yaqgdZd0s1QENcPe +F58DKeCxHg3+SL2tu7ncrFhqT7PHXnU9524jbQ0jT1BR8xSRfuJNBtucQLIfjHxGtRw0Bm9wR32s +01MYmvdJdMnMcKD1PO55mIN/N8gNtqWzNuSU/k2W8RxTdm2tPFP7Mg4BOkrXwJe6IhXADo84en9U +sCAJtuu3n5T3q2O6YXea88t300Trcyy/O+eKntl7yTEAbcetgH1NUc+2HtDr/Q/MItizjkcIFI8d +gC9Z7m+wFvc4NP85BJIJ6GnGBrD02VXbpOcDiFR2OAESvdmuvpXkVBSzOUtACmuI6VRi6KVXfUGi +cn3JRMFgFrl1aJOg3TiB1S0UVmD/qm75cx9IFZu3wNjTDHHmVRHL4oGlcgLmZwvdvr/rhY0Fulu8 +jwXdIScxgci+O+7ZqOLKz92aeqOTRUCNzpGfm2Xi9/YDoB1QDWH6rIekiSWeQWyWuOQCcO40+9JB +/vaXcyxW/XTSAabj2TUqqBmT7G39SlLxsm5ZZJuXxvJmW/KHKRi7bNrU9bDR6I700bLJHe2440XR +xPXYuEytJXofg3bn4lRRPwdj7vBDLwOXsG22Gsk6hEAVY39hkWvzrs8z6VZFK7JVM/FXbU7cf9In +OSp8FyygQYihgZERYaZxhsmHQTSj/izuzbotl8Mnr8hBoL/pgEtjNQbjwah2RB3WVqVcjS3+GzT9 +Ngm6ndeZCr2nxqTOBEd7JlfCVzoBni86VLVebTxCtfaTlxrwJzSErTFmStc1RDN3GcGQwr9Hbh/a +JkFvVcqfu9DgBI+xMtJpp7FnVqKnVu8sGAY3/bEs9QBtZI/NZPe/yDHVPKGWOHPryw4VtHRC1Kol +EGnS9XU1CUh7vnwYSpO1fd2bCuswJn2ElBaZ0JG7Fyvmk3kUZvFePT+DNeQcipGDu152aE090UFU +bvHFCuLQQIfr66ZFnjpLDJlt6uEMhpw9BGTZrfkw8bT88ZiatHZ7bMFSkJlwK76WR0YSVswQOr93 +cJLdxya3m+xHQDmLxHpMY2B7QX9TSKaUGj/3wCgP7Y1wUxo+3nm2odAcn8o0B0921NqZfGZ30S7L +4gUipDu/HQrqw7zkDFykJ1n6Zl2+Vijce4OdgGPkGA3auTzKFmq/M2s6FTLMoihNxCzVmsFJYohA +SB5+HPBLVk93EPpea74J1VNbrUUh8u8ib9f5S7nL8Lv+BWM0Xu2A3lyf7Vl3JPWUkZ4H7JYmOlQw +XziDy+/r87Z57CJ0tCgyN12YBLMlt6ZDc2ZIXSIHW6eSPn7ouPSqis1WmOz0ZKZaK12Dded57aKq +WR4gy3z4Nw/5Vp+S5quSsuGCQ7WJwgJ8fXJXPJw2Y/xGU3IUE8cVXvkn/UuP1b+mBaO6bQxd1r5W +6mNXny9ff3Lorwt/bTMG29+NQxe+YuppbSlLWOtMc4Ms+uQH56jxlVIkd4/Coyrn1PntzJ24gAY7 +7UG+eUgZ+l4Q+b9SzRxep4kSkbYXFNSoxaRsZs10LZ6QR+qUL6i4osBFdZFCfmx5zodCNJEk4Sde +/zGbSQgtJWNbZXEVcNAKmVm4ArGgNQueSeH+gvx40aP5EfjXTJwGB7LVSzTzABov017/ucawXw6l +g57PZ0AMl+zqWkqXwcb5A7pEjFj4VxXA7lOoCRfJ2VgpMt296bERNjaNU8sx2a+t44lbiKd+XjcB +EQsZgufk+ln31vAXa1aDhrFHqWSqz+qv1/gcNfzkRTroL/4nQ7HAghdCqrT5/1jfunNVu8IzzRJi +jYHBhLcGwkkyxXFdX1CGTZdxAT6uV0WcloVq5zFnUWlolnrlvNcHzgf6kQDBdW9yYf5NojSxASlG +o/3pSBbpAysg3Bipm5jDHjwCVD2GCYjGfBEAHwTvl+l/v5B4JIK+J2va/uulrwq8/hv5ozJPdIn9 +YBpFCh1aqsVSqPHiy3RWhFFZdQEi/FfYjt7K3xx2jEt0BNmAvPwW85zk9rbUQjXVSprnlEK6lK6T ++BEf77u+J32fYZZsdkcQrtISX/JowKnUs5XbnUlfhJJd3KEkQIFXRFi7hNlwIHqEV7CqmMmOJASz +3WRUDuKtqagh1MA7h0MeRhU2fc4w0DEc9AiZK4i/EvycTG54YqE88VGdkeF/iq2wvx6EntQvU404 +g9DKH0TM+MQjKyT9Aik3hxSmN9Zt0L50yhoacGE0D+fqgJrPt27zuk25rQdCK2ZXHqjKImqOnFTa +LgrwW2cBCXN+r0uyXvzLrir6qRtVmzRg5wQ+tl/W5Rk83F+ekgzjoI7WwSr9Vhh3ZrvhYPfqsKVW +EcSUUoVIy6oeWtt0jADVjL0gLbSyRcklpNj1ip576Q9YzP+XQEnFemFw/GXOIDX+CVL517s0plrj +2tDnP1vWyLnBEGMm6oHXxLRy+VrNPFyZ4fMa2BNMdETSeGgIqLq7R6XYnf8DmS5RWa2iJL8j5OuK +y4sAMVNdGjLUSlwnNxfX3q9TDmylEwMpfqNGJSGslGl8JMCp6csNik2lYVCgRsVDIIgAktyOeLwW +guhFDz3XYH6TyTpwdK2ec4R7F9InvtzlnealRop76WU3I2Ul8nYilex6mWRM7Xy0aXnV1lu1O8pq +ugsbKUXwrhcVAjH3l8IF+dFwSz3O6vWk9Nk1GWhvD7JcOxIWTxCbgjtGdgoUOiMRoBWH0FCnbiRK +yINfOowIDeaJavQd8RlSc8wwIBnqHUhaqATlJhB2GgZzHJ/jjK1YMfSaYepEVHeZqNMHZzr5yWWB +c64SMVlROKYzE7apyvB/5V3dn3vVG0x3dPv5bW4C2gMnDiIUqXgP6a1Sy/fcqaAzxkFWcteT4hCK ++aiqnPAk5N22yyzFXrKLXiwqEHAugo2IUsoWVMEWYyydUvcrzvT3opwuElyFxEpQ2FRgJPOROE4Q +/CQkjUu1YNUehnt9bejnS/bkCgR0RN5R5JHLDeR3WYYtbZNaBpvMuYKk6eTkNvQz07NPmeURo02d +f7yu5behClyTxoWdzNRB+c2PtxqFKEWDYxOpDGGqT1NCPyuE3przc3vFSi54w3dUROOD94dh8kKt +03q2KJ5G8dj/n1VrcPHzy0dMCWMw3wFz29W9P5edQIFsjJUhBDqSTxyNqVoE1qzkoY9OhmhGSsop +aUB4EZpTj5r2/tXby//Y9fe1GyzEO7+zPoATgSXwc8vbgojvk7sl6hQyhVesAW/dudck+Kxuo7Li ++LUdOkVmlyr7/+0q1ZNXVW1zph5fuqx/I/oQjVbwzxbB7c8GehN099VgLmLC0yxA3Ol+Heh1HIve +Xmxyk+6k545fUyVZZ5B0oKKeYcOVzR6bDJ3H1likkBkLCeTDuBHTR+BZK66nfM80eZzy7q+iml59 +pO2dRQLdyJLnFTxvGfOmKYXG6eAJD7On0Z6XNGAGZjaNKL4MF9TZ3T9iK3zMV71jH366vLIW9ZGS +ui7PYb142Ck/rdxtmllxXuFpuCfJFbLfBaKHI3EvdQz9McyNUR7V6XkEdn02hTX+is/O1BvhESnv +yvjJJtf0KOwia2b7L95e/Wxd0HLqIRZixdj9skGNZWTebx4bOmTztOomjH5dGgPdKuVCvmWRHilv +WoZqkE2LAg3tpmcLLyRAu3fMwxGjoEg50Kd2mdGW8B7BECY5f6gN1Dv99EG5tpsYn1RcA7fPpxTD +VGT8FIFML/opwcsmCDNrd5vsG2IYT9CqNIgBc9m4FjaYn6yPL0+y2qNp4DK9cek06kVLA7rIUJwb +O3DiMvsSaZmu6QR7FWs2Y68nOIJZRNMgZ2k5yLOgSzYIuILf8qzaon/ObFkEYBBg/TFpyLk7N7Oz +mvdPpe6QS5L8rRIXgCmspWmZ1MbsmcSBzQ0+q3bEgQgJ1k6E2bfQI/0Di/7ZX9zQwyMbE8vlYMU/ +kIJYe/WcLmWtWruVFoYlI/FYzHWvCxHpn1oxF2mKnV6cuZuSSibu1ssVCS9+OZxxJ9EjbV7UfNRm +TQJTRnmbS5+cQCTS06dkPorJOOGB2u18EhtCngoZtVHqqH7hmCt24EGMiLYjvnapSYHFB4PW4/rc +WTdTNHxMcFg2tWUooGCoRBeNOKBuwn5WwtuP/qujovDGQV/XDBmMGR1yMfC8u1eL56obFmyW1T3w +sl0ja/tpThEjaF3yJNBu0KBEt/uMSGWAV8OzQAOPL5feZclJKR2cBOx0G7IS+HY7JD0j75YP7snd +uy9pJ9haUF6OZ84PdHR2c9D3sVf2iJDJFCgb7+jC3jciZRSinkCIteFa/kWAdxlC6LQQQ6yE0W2w +2S20UFfWGhfNqSubEj0zzJr5HLoXZGtp6cPSyhX+HoqbT5j+HJVOq+hwWcWWUf8FEU9DWvLZI692 +3AGJ+dmwlregFnDPH0IBZkJitXWI0z6qGi0qKOXcc/JSDtW9vNDhueAHeuH/VIH0jijBEMbj77pW +3Fb6YNiCbZ8oCFhvpb6n3sV7SODgM5KEACKPdALYhYAu8vSVIqke59WNpIiflfUX7fg57e9P80/5 +QeEENvbkxLfhEjEnI6BYo2aCgQy2BIgpBJMAzuR8ZczAghB6aOkqr7MIDQ21PD6bo6q3UhJqSfDp +0q8M7Jq6vUOr+hMBnhNIsUV4rT+lmJXrnSO/Z2CgGMaHeJFBf4TgCPTbT6b8GiBAVm0eAl4YRsHQ +Fr3XNSFnIpuem3GjJpQ4rWuezUrPZPEtXaItCCMP4kYDzf4fLg31JPOr9XSqT8GFVT427zr+lMxg +9rHY/H4Axepd/nE/nEd1lfUwqkEOa3yWk4y8CWnp2cHhIypiceQpdGVUZcxxNH8/hcumzrimUpiU +T2TNpVFHcr2IBnghwG9c6XPtTtiaWD0qBE4rYYqlvTKBpRZB4Lsa8kc+9S158orS5GYT0vI9Mr67 +T56XS1I0iBGoVzmvzOTKQc7U00sEnBcZM2Y4+B/kXJ30e40uouWL0plcAySHucvj2mRIGpNVp/C/ +7EQh+IBWjMtjRim4aYpOmbHMN/9NDHYp+5sfrYwMHPZOGJ+Fx1ab715c37gcHG6JExyG9CkwRN7r +ALyjqcfQkV9bdWaMDEF0HHHgkTh9vyNRLzP3hUrEMwt1CjMuydSnh9wtpyDDq6lH2c+xSLzx1Ajp +jizdCKQj0bFhZ0l5/f7QY2r01+IKzSvG6fmxTVgDRokKwyfzmv3aUkduqJjwKIDKWAIE2rrMUqJ5 +EWiAEVMapq92XVA9GEr/nJLVnmSvJ2cDFY6bneCRdpgUprPpsIHvuIhOMAmbXk3XelGu0fWIRI+x +C/48SCFpqYxwxveueUmPOL9Ijn11fUuKroz/E+ScY/y2J8aBvpmR4Ij3+C9F/r573XaDBDHICAe6 +BJItdSfWqiqvkgN/6CT6A6wgWxJHTSRFlfMLos8iJHH9TH3iwBIFapATU0j8goXl/+vRDpDmHItg +gYLhU1bsVbO8ZETuonhVnoEmko774WeX4p3Vkf5qSVx0KrLUA2FroHErWsDbDoZiYHA5tsXU546i +SytuYJ1Uf2uRAjsWsPoL+YmYnGbQiDCb8P8PlhNoh4qLFphGwf0hGn2h5/Eq5sJzlH8xjsiAbzZc +2WBFU3C7kpZVax2yXsCUsguNU7jYj1++OF9aWnU0zsHhwnwyaU963o/wF6v2zpCIFDisywz7GkZv +mUagv42PbH465C2QpbLfEbJ1r1c148ak5+RVXfXMje7HNKyupeaGx6kkJhq2b2Ez9jiqh/PlOxGT +qDE5ug3JAcbzMF50PslDkdmYUwDGDVya+7If27tPPbzfhK7tD1n5AFy2MZMrcWnNtFq7sNvhwoDo +ghtuP6USbDQW5eFZ8ssAVCVcLS389dAB/4CD7WBEnqv5v4zgmzCaC7uNdup91dboPYvfjRl0A26h +a4mJN2rG9Voenq14pVyYxVTdf/RSch/JkjTPWp+/mVdAwSotklODQNMUFWyM9JVGhsWVhC70taXi +ZLRmwtmiZrMO8FgThoVVUXZOQHFrrCdFZc2VlzdW0dfYgBtCG9nLoSN91c5DGr+uiAA+m5/gq3WK +AbbaK9aGzHiQSxFqNWs6Ttya/P2UFFnTaRbMqvZ7hiGkM0QeAw8i217sL/deyIQfdzxWqL4I4NLM +b/qBjuvyA6v2srBe4uRcx2yGNffL9oW8RG0xwtl0c6ODyjqI/RO+kTWPZqbN67+kZFwSy1pDa51i +xTcFQCxM+GwblFbq1DDUa8+NKBMRIP1ByCdpJINhYnpUc2NfzjHHxlJ7LjNmrewV9eckYgcNjCVc +v2rU0K4i7CupVOvOMy23WHsOGSFzgLvYch9N/81BVftYlTiXBRSrUf3hCC4S8LX3XTsgyoZhpe2l +6u/C9/i4LRzg5esa7hpvcKKTv7/AY1LUEQp88WTAlWy4qyODvShKfgadizyereOX+iZwh6E9gQRx +t0Ct2Zecmhrp1zbalJsoae16Up5FRZ1v98sPQD6EykLWn+dqVjwSYUTls6kgVBpvFO7VzlDJDD9e +KfA1mes5t3IYDfLsnSDtLvOeYcVeICeqL6Ix9fDhQa6AhIJbeww4pGrK2cMt6ipF2slDNi9dcuxq +q1lTpaQaCOOLC/k4pU5idYYWibMVRYY9IEm67t/iMILq8gotnKOch25CQ4N2ys6a1Bn227VrBDw8 +p5s9Ci/xB9CIMiEj7kNhlC32Y4Wi97WRVyFFt0/T94bMWEDvRrvB1Gxd5B0M89tEOXC/6a2jeWmI +c6H5E4qs4eDj6xEuh2il5uKdp1TyeMYNiRyfVSIQnw/ZUoiK8LNwfyNWVAdIobBicLlkL2/E2UdF +Ab2h04ZJ3QQR46bZMLWvzCnop9VU8H3TUK1rIbmZEtv2R9GyJQAfbDM8ZUtKSYHfPsel16bGIHXz +Lua0BZUNqn4MevbEdPYfGuyDua4neSTE9XDrmyTab0UH3jjvZKEdxvWZhEm2IyHiwXH/LzHuKJaY +JJkq2ig3p74Nl3PygQWzV+l1UdCjiX0FTKi1MWlIezt36UH8aIMgOMJr1soKeG3q9EfE/xEzUVe4 +h18AEvs0bqXb90zkOqcCAuj/Iqej41NDH63HIQxWQkxfltvFAnWQRt4oIgag3KO6R6eujv6Nuo4h +snSuiqklMGapcE3g3EjnMD3Q/mik20e2Z+mXY1nh5WM+GZKr4tERRGxCXHLcyR12tIyWQZDt49C6 +HdZJ4L0unA91jXwVNJ3vzx3Kly5hfYzk5N/ncj0ZB12A8fpAHzkWypMTKXw30DJb2hbhlxR+oTCm +X1QpgfnTw93SY56bvczB5rL8VIFcZtIf6IRcWzgh7fEeBoMpVjRo8n2Dug+uDj9c6G5BQRdoliNT +uhHlgLYX5vo/IoNrMiliKUGw+oTqdueWe+6yKNms0XkrxuTzm9b6xcOnIwBKoKRhbGNFNHquUlVe +D3jsHyQMY/WWxt/Hhn7eyNL266oLm656s9VSJcoQa80Oa0SiKwDbKWerMNczhgOpr6eC/kp/iYlL +GB25CRj4pphYw21IGsRbheBusvi2dkhdBkJZLQDhU8/xukwXiYtJYi/EsgJ/FTv1AnKNPfGu8pHV +UodMH1pxkUCn8lzqBZfyraAQacqhUaXWE3NvERIlOhCw2TgNonoJkfSVIGYhwzisrSQCLiJRTCG1 +LNpHXSEIdBDlzSSa49cquoqisa3yIe8YIBtyqwxTDKDJdOMwZ4VvWrQHKOES45WoJN6Kehr1Co0p +6+cT/Tz/hBD1RgBarF8ZKRqF+07Y39UrL8pfnhdtTNHPoa33bU0MI9TXNqXdiZRXRiB95GcTcQHD +iIWHwHaYAtdcyPiTg3xTwTnh4b3qnrmirazae3u+eN1E/T0t/QVewfrQZbyo62+N5TKuLXZflT7F +b7HTQXzE7OkvwzjTouD3puHfcxyNb2wj4YuF6aUEmlW6zZVvGw0EmHoEI32XwBdt5fp5Bh6SmXAx +WMzn3QKTfORTkCm/cRczyrz5VT/BLFYxodD+TZnoJ183ygdJfJwE5mhZ3ony4V02B7O9zJUiYr/w +TC/MKsDFvvlOQAgGkTZ2Ztsun9oXh1BQAc3Bivk5F2FKh/SFFI1jp6BykypJW5j2camlkP545i6O +ghlWsW2yYcjkIISMiWUAbSwb+71Tatzq+q9BiwXC3eG2MnwUlYud/oR7F+ZVMpspM+wVNDw03jOr +4fWPFFtbYnFGkFLWj9xa7IuqpCRl7UOwdJhosAhJdzXBzFiIOYHuNAt3VdedEqutQB3utRMRDIO1 +hRmW2XOc7ctJ8SOjeCZ3hgGcmqDRaEwVw0xu5z86TNqS2+B9NKeosp+JrGidgAXaamtgxm13cQx8 +Y1df/8zRoZhgqhgmLdBcJg9ATHzlb6s7tqGCOsvcP4wb9qy5taNyZpIY1SEk4frsPbf64J4GzxMz +Gj72pMFRQsnnZYapMNrL/e1uvGT+p79UOt4osVU0nwjYxC0vHvIDx9ApNvbKS1Nii16eUI6Fw4iH +d1R4VgA+CUUkSDQL+fM/DX9vaa/qHV9N4j02pf8lMX66cr/4YJ++hmDSYXjNzmZMLY5N/YPOHchy +OfiEB6ASE6PbwAVpr9hASi93q4G8LHjM1UDEueobGWPrNk/RK9elEqr4+Knh/jfXtbIWmfRQ/Aat +2zRWp2TOO/BRAzdXmETrXHPrJHyG9d54d2QXzfm6xlu0uY0PrNaOyMXs04iQd9GfGmep8IdO/7xc +mL4CYhs8AkoIv0wiNMZrwn7rIgWubE0JGdcZlCC2VY6u0sDKV9hAbCvfINbxnCQgI6B6DfEArAuS +bs5+ELsSZ2BOcyk7ZKKz5Qep5a9Y+fmb3+Z5Jt7ZaAZMlZMsnW+S0yY4I8vRLHre2X4pRKqeXKbt +r5BlUYoZSRF7ljT1cfK+ZFgBNdYCSb6qckmH53LKeh2IggjLX0UN1P3n1ZLLZe3TgLnmQQGQJKX8 +Kkj8puLm8YAllHxzllzVjdk/TLeVaCBe3fqtnwwEQkPDr/LLq7sp3R8CHMGX+V9rAvaGcV+pdJMx +LaPZpJufMi1ef42OFy50HTvd/yzDwNDhh5UbfLHsBmiNfctV665IXiavmNFc5L2bBc6Px5Xpeu9B +7WkQHEVccUInRL8llkg0Og21Prgt6HktAmrkjFrHtbOzXJrdX4sH1/n966eodBvQQAWB6WdVpBVn +HUQWQyTAfsH/30lSYwMfQ6P9AWSqVntVGUqaTIdq1YeB1JMUjT6stnKFeLykVu9JkO5gvPoYFKAt +ibwu7riTdHdBe6D/sujfaRVOQr2amAFq1qKn6jd4XSXaUCe/ofKrN33HusmsKKeZ/F6FPI3P7NnN +TLCbx9L+3MlMfcIk6FxT41YmciRdxJBpwajYUELCQB4pO9dy8oKjy/ZOd2xvkrt70U8bQivGvB5u +pNfXuhnPPgKl4RpzQMPXj/LSlWDhQ0Y1WL+AHSsJKxDinIa9+kZqUY95FAi1UPkV9BwohUIDKe9V +FbHhhj5EX8Rlj+A+5BKxEugXI647SKo03uDG/jm3Cn0pK1fQRh5dyXXhAi0pU6KzjlxoV7pL1WhZ +LyDBLN09kcELwRlM1RJhKtjYhYA4fhV0tXUHJpwi8st1ITzkr3zJBghkg2pvtWJ49jcp56OBgGLb +SAVnALEB9y4x0Osg/pTgRv6TvTAKJDYsBEI5PaOSLS7J9PV0O8Uoc5jH67HD6/C/PrjKvlFfCKYi +HMtRfqXnkj/F1ZHVBRmOoIInCsZ+35XwBBHEd9KsK5Tg8a2076RmOguQhdCzbeFJUq0Y/dB7BkjH +HtjVAGMsLWM3B/lNtMs0B2ypqLuHc56yHdoPWIuqRq6NJNtrGWzWwSYOSsjHf9Q3ckqNwu21YmsL +w2p+QunaW4jC4yagjYoekE9WIL9ef+4UaYNCRD36RHVOnFCg9QXue1VodeoBpPkb6gdSLmaVXl35 +BDe4M2m4/iYSNt01uFBpAF2YRK5oENzUG7uUgsUm0tnN31qKK2ZTjGICrzfdh8VvK2Jf0l+UuMcE +Qj9rkChry+3NLYVyRbHgzoSbPNLSbr991ZoNUBUkFoFnOWw2ZElE0Z/p9AYEvAOb1SCA7qctfxGZ +/Tvir9HLi14E23w+/HIP91rLtUZlHOS2QZnVWZHfg/TU6J0VZz/oV4mi6w+6bC1WR35gEhAShkp9 +ML5zzHByBSGLgFRh67Cuxbv7UnKQW9aviRunIeT5KTJkqp4mD1N0IazsPHrqz7RpKFCt+FJaDpZe +2ucdPkna1fm6iQ4O9OqexOOkH7ikO5rfxbdNvs3df76ZbDASF2meJ0txlfsGxDPLS+mjBidXxUMl +vk9E/5nhIVMoJtI2H/eaJPXTMEt2/O5hfUYrL7YIDJVqIDE01w6UdmFb0KEOH6kEHz/iyql6+3c7 +vzDc6Bw5FFVjh62enWKwXy1LQWXH80fddse7g6LnYKtTKROcz2Co+2xp1xR6mkWugMZhhV69zrXz +FY8/K1w7wmEjgt+7DxgzMNd9ILAnG6grHAv5rPBA5jnUhDuXaGC7esuSbFmzyiy8fsEES/7cBWw7 +1T0SUf44y0GfVelAg0+CAG3gQN0ZZ2b7wGDCUeKpm3A2XFw7Hg4HE1X//GRFt99BRejjccD5C1oG +/wlFxLXKbRTmmcOI5wr3l6jAJ85mZtr2vrwgAtZv6ZRd75P+F3qne1X7mCVqHKSI1Q2LJfN3MOFO +V7mJ4ukc09piMbNo1EzzIEuTWF5oDWLgDB20p6ASObi2l3ZPbdEVCTC2XQAMYdxR4Qy+/oNwvamQ +gTelHndnsD7SAXzZLsFp6YHr63TQ+999YzJ9waHd7gpu0KHozLgR2OpArTvmmI3WRXF5ySyfT1h9 +ziHQskQuSrlQNZ7L+XwhPGSDmUq5llPjRgUN6FxuV9ID62dISp4QrC558tmlU4xS2tX3fRh5dCJj +o1isIyW8K144+8RuEQ/7F77KuY1Y4jUf48Y6hcGoCapRDeLnxGlueTVTzveYDSfGfe4j2TiJv+tg +/IZa+bWcywLP4pAThq04uISv776owZm5kzzEkhbWNGUUDQrEeZ4IMQXIeD3i+JYPuuz9H/zuabax +DRlyZBqD/6OvzK5YLFJdO3Q0nA8XuqrqAow6MoOKZEUXwtqbZ+asUKLxB4H+wj7zKjfzStvp+tSn +kUXG7AgMndtmAfSZ0EBcsBkBvFckRdo+o9G2VUKKAM6Yk6In9MNZArw6pQZYbwjC5+sbpFt7zYUQ +BKVaTPERELi5DfTnTn4ESuE5yY/zvynQCaNIXha+BST+34kQIl9q9bQx3vLNeosROyvNnHlji+oN +y/zFfC0BQFK/QxErYl73mbb3AfbBVOgevDTzUU18FCm1qBYYmnYHV5slgSgBJ7nSsoWFNxD0S1R7 +g/OngNWuKCsFIh9Vtxbqc+vEQKir1UD6Ez2vj2AoJIyNJH3uD3qEiKcU9HIhA2gpX2A+pH96B5au +J6mojjPCsmybHywLd7SR+ue0wB748LhGifZ/vleTvDdl5ehRtde3LeKutXLB7Ai/nfXbz0ISG4ZU +ZmQC6c6E2GsJpf3TKTtlAYOwo6FJUfR+C36N+Y0LgjS4xyUl+by3hni6bgg/q26GmncA5rlhwj05 +y0fl0L8XoaZh7e8Nk1ky9lTPLCrnF5D+VWPcU4+b5Dk+ruv8BUNLG6aieIzYV0SBrQ+LmIg9EJeg +2Wv3hjSe/7z84REg7fKZ8LmhWyIWkQIWc9hm2c81jqdTIykpGv6VeNlvP9Nxt8LaJG65odxfIsdd +vUz0M1HjXOHsQRa1eyg6M5ZHIqerWKJbMN7GTYGrFjNImYZU1HxyWywD2Do8wlEpa5apxAys92nN +Y6kMmnrbWpRYnY2m1zmXtnq4xIhwkqoQ3hHZJpkcHW35y//rC+VXASPUSiwwMWftgbWBf8vGDlY0 +cK2YcAF+5FLTzNHEphKZZIDJqM38ES9lhgwDJF4YwYKEPg4L+jTm0cxoXMEJs+sgZcwxM0+I3Pm1 +LSRdcV41LTYoSzZelhcvRD08wrRPM0Aj3yc48J/oqan3gz/SGvR3pMBVME5UnyhajTYx7wGeGM1c +vTGgzF8eBLhf6lK6KFMtPl5uFTAq7EShqWJDgGFTEpQq4ISl0i9wliPpsk5yLHMhXmr/o0lQPgAl +RYcAZyuqtdo8pntgAN/ytKYNPxDdzvygmBEt6hSCLLGC8Phy8Vuwb60OMcrYgj0iVNFrm11SsaG6 +sNVQQUV2YuNDZlry0km/vY0GYXUSgywo24DZHw8li36rvVFjWDOwMH/hZaIYo29AJ1A065gbsYOp +knj+zsRggZ+hR8uSj6WGCQbt7QcvFMZVIyZ+odr4Lw1xUIBMbYI506zc+6SeXk5QGxwNv7zvBXZh +TBrKOPo7T7d9URl4HdeG9W8xAjQ+zYqet2rvup9WQvED+0x7X4oezM5jkPzbuq5YXEmTBMBukca1 +hjJRB6kllwNjb0f9ZTkSzrojfJigFR8jlrIWJ/vSS3LByRX8HwNbc6xxLFD/KQk7dsP99EuOdOJI +ry1qCam/p3iYlhb4Z9iLftq1V2Emu3HWyVu9K3pAHMDlyGxMkmSOcy4Kj/XEfOl6Y+DTDvCdfmIG +25yhPX8tQkLsDDrgrUaHbuGKH0ecM3ZFnNr2jzcDDklqoZGBDqg7i6UTwDP5ljYuNGUyU1YcHb08 +gGhISKPrg3wJxlfB6tgCSJs+gH9p7LcKD8lZCLuCHa1n7NstQIJYWZeSbEZwjSKunqwaQDHeAfO7 +WcR7BVj0kyYoS4lLbDfMubdM7W0T5f+ZB1AC6MwsDIW5bS1l5MsFRJmtOMpXT793WM2R84ZMtLqi +uCaUELmRshAHcs7aAKr8uzuloPBsTWNB9LF5PYXk8LMOrz2P8lWxhJxx3DUtbzlw94G2aNe/5HcJ +Q92Yr26tBVKcCn3W1gmFXeUyxaM5grGxe2TzfsYLWt+Furd+q6UCtfR8pxT5+dY269FltlWcbhsP +Qd7W2prclwtRtKjop0+vNWI+oD+sj88aWXQJG69verdlH6Ok4yQYSZbExKVHijxbXHbDCySY0MqG +Y2Zwworoi9LowqHAT4ULedMVSqe8RaIDiCgC7IblLMcf8GAJiaTbEDzff91Vdm/Tx2Q2btPebxH8 +SUCpLTDSIPVBrj8DZSIKxI617bsSZypAK/OQhq/A8bOiR/30I6y+VAqn/t31YTCtUhdF0dMH4JYo +1jdn+YxP6B8089oo8gBzXJg5Dd253Q1SaYyzq52C5r8uMdKa2uFnGNg9nhuQ8jWT6+fLBE+HxNC/ +7/xafDcbY704HqbUuywJ4fhA51vpz8Cds9ewUFHZaVgP4iQYhox6OuRcCWP6fvRLk1V8d/f0DKmd +ozqRpBkucNZ8V4/8CdGlhSDU4WMZoA7KC/PfhiTg8e2JQlmFBq+ea6RDf0bvvB55M9SuX9D1EkBk +dVjL9RtyqAMEUPGVreUWPQ93jA1jegFvI0DzYcqPCjWxydrVN8QofoPzKTvn+Qw1JFiI4ca1ErK8 +nqCDV8wlu0cc9Cdpz/ZxH64a4VUOK6dv9xJ2uEpLQvZZJTm04dw0ebaxsAfiJ86u5RAB/4W3bhyd +2lIrqC6x0LbfI1anBKjWfpSHXwE0AB1BOzWHmdok31WRPBEwN7b5fekPHMYsjL9/veKmxOYW5pGm +WAolPTpZswfEGBywf4597OXEUcXaCuM9GQZBEPZFCZ13WcKcFDZrrTvQl646H3/AusbPVuKvqDHg +6bPsTJ6lUXbjJ4U4JfkDG/HyanGLafYv6Bn++2YnrWOGKcYk6FBZz43qjUIHKUt4oY8SbYnRDBFI +9829z6n1CODFXYqEovfpANo0exKUSZ4oygOklUbroK4YVkDAPBGmEuhr3tAZtvDSH5kTCuVjxyLP +VafYIoiDA647hAZe5pSi5oDF6jNlzYBuO12HU2EJCHd9M189x2RGBnUP+CpUfVOnFeiGG+o1qJRp +YUOSkQtvAofuz/AgydFHcubNP4niSN3ldhwDLEWRAbXyrAOZJBTnf/akoD85w6kfVJ8bSFyqamAU +Sn2CFZ/EIL5cGLqnLRvkFJ2f72m2y1nOUfFvelyP/VmN0P/VK6RwB9KJco4qWKZW4Xns+t9qJO1o +EHmy0tRjpNkcD/PfaX47kzANL8GVBueaD8j/00iICu24dk97cna9rsJE6J3aBKWhDN1CcOPUzRcD +HqHcu5F2chrFy6BySKAswkX17tFGyDBkT6yqKnv5n+l4qcmyA75GUeLtkxSvexRUJc/wqyFU4XVZ +syESjxM7Fe9oglUGcH7mgaBN5PDKYp9jx3crtDnvCW5ZJg+n+Qnnj+WKfdO+NShGxbfXtS0OXnS1 +hbDhWb0jKr5cAmCjv3p/VqD/SczQ+NNY8oAt7sdR2cUUg38D8CjZlw31WAeLMl8CG2UB464qa2JP +HPNVbHQgmmKY6qa3A2aqCa795FYxJ5iXZih10xqHcuxqP8R3uiOb2NU0XotSnwZLB3PFeWuY5RAA +lmOH8DRtrrjE0ingK+WDONRksc8IGuPgjBETywx2wzeC2WF8VLbqzPaJVvL06tpXpdAeUmkn6pye +/ivj2qs44ybMPm5R+QIY+NFWVWge71yt015G84HiMieqX5J5L9CDxC6FNDwxyEmfSbw/0Hwbud3q +lyYruGoxTJiNA8J7horAYuRRwWT2nd0zIZ9GA34Yp0mfjGGKwILh67k0Ayjdc5XbX32TsGS3MWbg +cVbHZi9h8DYye4O6K7yZotgCvgd7Z+AuHByx0rCP7k91mB2WHNqlw1GOAbh5pPAfF9jqOMIzbKnA +jhopunGLyprS8o/dL6SBlp3kv2aznIiYXwIA4DHFKKYzzXXeHXwWpcQ55vVNlTqG3ErP1dTrAL2L +K0gbgbnzvOW4lIo1jgIzuq+VfW9F8hLkOFb7QLSDjQ55SZ+jFPoQW2SQeh+Tu5OxwfvZmoRgHTmo +E9LdVqU2Q2fDG7nWqG/hEw2nMsIXL66rLJGjIJQ21TnqqLLC3ApMA5NtHlR6O20LeC4QRrkRzyRB +kisNMnhMRKKSDDXotywjo4v4yzCJrDGYUrYWc+tr2YL1zWfTyqNcZ73eSG9Pngfg8JNjZgiInzDW +m3GlNwCEsWJSAncKv8V8+oGGs/lNOqYLVp+GRovse+lGEmrI95JSFO8EQ85/Eomvk+G8FuMzym4h +SeXdgWpRYJ8GwJWOKSedjveBkBhWK+VtOEbv5XuJo6xLYuUkUg93hMNz0NQayuaGQ4A19tNMquMS +GYVJCNw/HbrIWCO5gDAQHJCRj05xonJRM73zRXZTZvxIPwIRbBvA1NW68VUkS9RxksNJbB+IA1hu +Gn5RPxejK4sWewBs50q+gx3v1mFaB9XlI52X0Un9krq/DxRkqjewOR0qwLUAOdRWmXtrHb3Eo6Rw +VGPBStG4fX2JUrioLQzfIjKOAD/FloJHnTkpaZlrILBB5NCouwsKf6jbUnhOEPeADuUDlBs4Xw8P +/aw2lhqdYp+2LY4RvSyVOiAFDI1ifRQ2NdnseLH1te12RwxCoUJMWTFQ1sJ4xHamHnKMn2ewK3sj ++Xi9bWj+9skv0DVDiMJOd0AjPg89YyV34j9bjHGsMQIsBWYgQ5MVGdmNq6Z2C3HHonzlVfNX1RMO +yiYd8PazSdRr8l4JElgoEx0OcUorveZeSZHecbMV+p1xntF92iu/pVRjd6fXPuUUsm/1/+opLwuW +tQ14up5DzpiTGXrYWeqZjlb6YX64oKgRUdxkoTuOojex8+Z6e5/J5r7qW1Ayc0zqayLKEn4GIS/J +7oQInOSGpV1rbQudhX0NxhFjf02COXcZ2rtRVj2awq4HEVmNWSQL/9tQSNGZrDe3iJwDs61NQBI7 +Uc7MEZUOLNmi6T8XCanh/kWZ24Q3B3YWm0QXG3N2LAp1qq0qk7LMFSGyENKkmwN08Q7b94u6R8lM +1szaUjUxOpr9Vz1vsfqsyYEFWX0kzTKosXGVcDq7lmIiVcNgmv0qjv/z7+C2WuHG7+MwssQUNurd +t8infZun16CAZfQwQEY+mDKo5SVrJX37zqW+BQzZY0GCOTG2k6qbII3DVcx9wZ703HnjT+vKukZl +3J0ZHHPVyiA6pNHZrDupq/6834+dbwCxXjOfMthkPfYXfEU0t/qTom5gG7Q4q/iZwjO0dBVk6IM3 +dCRX8wamphsg2Ow6RCkfRbAlSh7O7sBB3yEFpMRKqcdo0MH3alX912/OH3MwtDjOLR4QqUi5BC18 +VQVxe+0bBArxXHmWBfS31gsYMbPy5XXiNAEz8l5oouaBye8uTa5tIMk4xVz3mK7AgQj1PxG08sGp +bt40TbB6xun2nZT3OA33LcA2Bc3SlEYiV4tgSkUHPz14mSGtGqSLq2aaQ2GdXa4nbwF5LiiwCd4T ++u4SPRkjuYqJTMTxf7q6QWwXyZy9vTVHl13LiBr385PkxOY0YDTyKnltcgKROYqgmBzsJVwAmFQT +g3k4ilPdnTeG6wT1XfUbwusYng/j+qMFZCftbSQj2++EIr3kGo/MxJ0hTdP1MoZDpxtDNlhHUmSa +7Beg4coTWZprtPxdvRSQmr5Kt5Q1g+NxitpL5SLF73z0jAJ1QDy46cb2raJ143JnrXS6i8eqA2aX +3pDqeSLvR6765XrwB8ctyVFacH7EaHRKMrFMXbeMlAr8qdWBws9YJUHoJqLvIJfTIeTuKuIjdyi/ +iKOI+NwgMvA/d3lSG4QyyeHhL02mvxvAn+3VmV93f8WSZjb4btvIaICFyhu7WSFq+Qx8uLfrk2aT +F04VNzdkvWqi6OceEDGR+tOpZjFT8t/FszxsrVm9CyCEjxBorZvMbjRSP/HgZ+qqgdrp7ULvEkGv +IRyB5E10f7g+w5LrNGsRo60V8XApa0dTKeb6Di/9INRkN4Fm/70do20pSw5Jchiybq9e8usdLh4g +gvnxXgBgeTb9CgJnxPAKEXFeEwOCdJMbQmo5bpnj7CDJxH3nRR1k/n9yXjms9QYrbHOMqrbF6WAh +nqixtZ6ZaFvLHG5v7rQiY2B5zincXavQ3qXKxHtBe1Ymhs1OJ+IlOFRXTsg1vgBLji/wi2WSFel6 +ZL/kK194fnCfwPEyqFyzS+khFVBALJlJ1QIQbtJkDfUD7NalgBhMzc47h2CeXz2QIgs5hqfKpqvx +qWbRaQxsF/pRWo5wJB4z5T0WTJjKJA3/Lh6KH+eKjhZb5BmVNUBE88i8GZpAlpmu7naiQIpWHj4H +2katL1A4crYPboL2/DVpuEKz9sFzx5DNm6WTTy8afz/Uu2KJcX+Bl/A64yNs4/12qngA6HUBl+2i +vnKBvthqRLIDmn8i9ZHjjRi/ju7ylspMd7DFA4fd3EBEVG7bvb7LrfwZCyA/6FBth+YYIuFsao8R +u7GFSv5JvpVSwPxwf5xXVCMwXRHwXihqw9uLRVATU78fqgo/L2HYju+62+Il+wecUcERIfcIbQhM +bxXA596QDtONDykfW9C2mc3WMCeQP56HquzzzM023cbZQuzSD6wG2Rcc6lIwrN6l9zsfm+hZUfIX +PK5DN6noaPx1F9ObNphiX9GZ2gypH5iRFxeKl+pv54TSoQv3yjrZ63u7pffjjdj5rfkXVoqbBKgx +0bH+0tqzO4VQzCWzM5T8Qt1QZ+JrjAvxLG3O14Jma4d28Ql9ekEZdBYzLbvlimKjUrSgQhRcZBCY +1bLufaTU8vu5P7B8jw+VZXGIvz+yKnQ51d1d7WG33pgjjpVmLmZpaT4i8omFTim4tLiTRtDZ1P90 +Jv0KpaKUADC+/fFOATh4GQ6Ol2VpX8OdmsIl2odgnyHgifK5dmBMBiiKb4WrppuC6a3xcY/s3Wlk +ShJ6/okig1Xzhkeyh+VwTJDVPtFhWuzYjkD/CX0yOrRhAh49QQT9NFQna+tfBR8S68X+zUZAqvki +a1AUFLRmnbIw5S5P90t7IdtehwL9BF8nnxTvUzyydvLzwj3bhWFpKS2RX3cpy5GUA5QIA+0aUDqW +y/929PSIIhqjARQlKm5jI9aJhLdFTvL3Fq89osk+7nDK+VkvSnC2asfqamdgTPxfvKqdiNkT61GO +6agBTb0ztoUfj3s1bHlBHGsX3KmJqv3WF360ZndjfO+eoWzn4KOen3U9C4tnZkUog+T/GfuOOECY +QbE/BpL49r8diGymJRUaHACR6/xZ9p4fdiFUZqRrgsvNDU8zl06knpc2069Q86JI9YN3u/JOw79y +mBSr5AgGEso7dkji07rFw/blr2oybqU5YgYaTH8aaN9tk7lWTcZeUqdPNNR4BqmFXucHd/zgEkdc +ABjlux84i/rqsIkNgSPKkX15gxaM51h+l+7o36bDEmbK3s8hDy/tP2tMtGtnVZXPsPtsWg6S3bi8 +5XnOUMNALaA6xX0leFpb6haUgHDTCgSAk4mujAjIzyZd0S1PKawF+1n5fIk1/xllRq2vFQtIuJ2E +Aafu3tad9DexS1vNWnOIox0ZNpJk1yDvXjUif334PuijUAm4E2e91CwXWIv5ooDpUx9OSu0rSOXW +RVvVycykINQqT1VV12xPL7r8/HgXiKJOfJlw9tRIWXzGsBBQaspSAUZUz5T5bw9tTDm5PG/TuAtq +sKkG0gPeRM8+aesfPmWpdljNQhd80mTr3tgc9hv7D9Nojz9gBUCXiy+8YIuqul5euTSACkkMsA42 +Ps05AK1DRjlgwBg8YDo1VkonxBg7tm1y+p0HrOqMonPmsZMRJI6No1aMbT0tHJGVumVZXOHk3VPv +Q4fC5yjgiAKtts5O0l0BgaIOpfP1JeZNpAJ/vg9W0OF2WS+0QqXUr8cu85XcF4JxMbC/OEWGbPF9 +auBk8Z/gS7tK0rRbDWtE8zOPeFvAJmDT7dELQfdXhXF+A5KBWRPWAzTzPVuW6KnuEIDl0zXFrnkL +Jw1wJ1QjZDnGlJ3Viq70KLhu0RaxwJVwTpjDSTcoWpFpHBheJ6vgtjPpnM9KudSWgJXnxmCq2Jy1 +R4coTV7g8G24uahG2rVx8v3cChsyqPfTIDrxyvtxP66kEl+kb5vhY26uPCQrLV4Bdj3nGMvO5krF +Ef26f3LnZ5lHRmYfUb7FNsBlNK4bWTzIkIwGi6ekaFxdSPX4j78qSIHLUjTE+GEktREQiGrC9EHM +hh6gnjMFzgkGSxmtNBePOWPc3fPAqYYnkomfA/I0kSCFeTaAndljWTRoTY/ZbJCIeXftDB04LaPY +i0srr6P2qdXFeFHEpBmkLwvjPPMf2a80FP73rPNFy9ZaOHUaPqXTJXnXuga4+Cwii6eba1NHGRhM +jVn4YO/o3jDvDE1CVL2WUQdq9zfwThOL+BapubIyVRb/CEz7i7LyJImigGSUmzyneCgx+dtZReyc +4iJKig8nhvcHTOqjG0+WwGWuHbn6Ra+Qls6b90W/DxTx53EPq7bpNtSLjAQ6dHBpbuKrrvWUn3MD +y6qXKCwIxthtRTGfCL+429lKoXXEdgdUP0QGVR9ZHYxHyQi8wPHoxsqFafhqkR9sqEwHPOFS/zxH +NKjq1IJJmTxfOhB1XdySJCtucCHeIB5O8nRhqWbx4lIBsEKzOruzidnOLDq1mTOdGDnpjmdL9Uqg +gr5WoiI+fWfBLvg6UnPk+ezNennNC2kacwFaSJdCcuGn22hf5FfcihMdNEUD8aMwjVb6qQUGB/gS +Q9+o/alpoficqrhJ5bj8aVa3L5GVntSYXmnbnONVQjy1HeHrVvUFSrOIXmXeviXuOwz8c3J5KFn/ +msVXtsCVxRfXIBMpP5MLGq/sW31YmrO/jzNkwkbQfRVD55M+OD1ivu/cPmhr7t0ef4wsU5tmeiu5 +jZNh7wHJL/G2u/iRR5LVX07L8MP4buU8OOPcKgi/3bNAoPSeH8Vv4r9qK8XBnxXycqav9fKZR7Tg +rjrPnpIbRyxFn/HGRmwNNIsEA56J7Up/CiRCyBN+VKwZgv3lCTJ8lOuxPydEEdgsjfMahWO3W/jv +KhU669XkcpfJRA8QW/pjsz4cfrdP38QvKxdRPDG55I+GHz3jS9KzUY/BrliwleXseceva6TBiE4Q ++AkXs3CSdJ0vuYzlfouq5y8gvd+tp/UR8uGusthH3Eiio/tRzlwMrvS+L7EzTMmQqQIu/D/S69t6 +hUwyYozp44VtDE9xmj06lkypyo8VPv4tRforJbnRFNZwblA8LDnz0JAcqsDRo3gAT0YXq3PeV5NM +XLNar4SvSnM0XdgGMrIuBd9DfeF/WaZnj8JiESEj0e5TGzYeaXtODYhX5I/H9TBfhNT5hMOwAbyT +U27BXeJUd1OINsRqz8B4yp8JvbiaQapk363oFHEUm6TU1nqL5StQ5EZHar+C5K1vK4382rC9JnbF +yy3DjQtTAEGTq5AwmjeoruZu5zS7SCx2ZgokTag3j1cST07bx54b4ZEPls932ObMmQMMnTMJWLc1 +SliB2TXup+lroEbgKSEN5CXGGt86qPBGEmm0mredkQGOc3g3Mxa24qgoa63k5LDUvxifvjdW7u96 +onO7VZIwNym9Cu29hJ75GFE1qYvMuFeiTBg818foa9YJXtLXEpZmFhdld2VW/EEHee/7f8P9WjFq +YT3zROQOBfKpOz3ob3qwvV3bWKPp6KPRlmBJIAO71EeRok2kVOrujhlmL2Or+KyxlnWOLyXqi9Se +b4V7OhFe4ZFnodKpOFNwZb+oIhz8g4phGVsdxs4zsiZEdhdJH5v8mnxLTrZvEkh+9hX1evzMz3vI +fiuJkRg1JfvH/aLeHzqCZ4iBaUJOT+lFvWsm7xKfHSrBUWW6p9NGbDWPP73iilNAwVxDKklkaqYG +QVovbbtKJJBouopejcxXo342OzDjPrgCCBQIyPjtm7ZkNA+smtuooSh/J/Gy+WRK/P4jBstvRs11 +JprwTy2Mj/h/NeCFzB/hy6iIWfDdMu4+8NJizKFPMMtHVP6iLXhpQmid+Y99TSp8PWq2ijvznpZz +b/qUNWGEoNgoyVz2Vj2xhArLbaeN7idvd5UKQRZ4+9yeqOiIbcDOrdCLFaeLDqi2gTPvRRLOoLDL +m2mfWdFoHrI4OGN9IABP3U4YF+VshaGJ4Y625ocULufnu9giJSmkKLNfPMArtHLbEUyrhX5qsIlm +6QbItSKrcrL2DQCvN5JdadjaqhogoXAKLZiNO7/JRtv2VWPjBJdMz8a7xuF5HkgTep/q+snX9QUr +1BIGnuRzhZQmLdwPEykC0IWLFb4wfv+OVURkSiHzm78HWGNwsWVQatNnMGxWIvHOAfKQ8btgIUyQ +qve8cg6rzUzR+GU2HbcgaDXnSdxWWYz1szN5CCTWmH/Wx7glZpwHto4zVe5Ulblxes0fs/ipFU+O +V7k887QNwU8nNSIkrlUd83OM0WnYBluESI4PFhiDjhKFmU2SmNjUVftAa4CuXNZaPM6U5ySOzQY9 +ZV+h1zTP9lUfsuFuvsHrqQfHgVzLogoPlFM2Dc1URKFi+gmITBw9HI+4+3/jjIW9tVCBlctESG4J +P2f4vp2g4gCwj48CulfqgyidSOdLTAgjpBHk07XSuxoaOwG3f2C+68GOFn4VaDKCarkgTentcSMm +OIl+K9kIiLWMA3bYUu5eKGxqRgPv8e0dGSxG5IV6vB5yGRw5gujCKKmynR1rV+2MIbFjULczPoMp +XPPFkIRUvtMLqJg8zeb0wg3KPJjCOVSxnoEsjr3cr+wxIicDcVsicS5+cGPkympj3IPXLiFz3ZTu +J5sBP61L/vOGlUvp2c8hSdnF1FqcEURLtrAi1G7dyp2WHP6yl7KPTMc6XqWeo1LEOMLO/Uc8GORK +Elf0RdFcI527NNpViDRVoCXiwwRpqnOT6ZLjHGJKvs5Y5Q93/xHVfBURHaPtzhe60T7m6EWe363V +XRwaopowpGmnlWKfKFco8IKenQ4WM9Uc6OktBm6Zi1fFGcKcP4t+R84NBendqjvbd0YND/gCaIIL +9xly13ZgcLohn9a9NU/To47zjIjvZ2rpWn+0f9ujfLte6g++Ve7y9kVo0sV/FfQBOlC0oXZcc8tu +zlnWgYwy+FhUprK0LIUOTbiZ03dxZstYhhNe/3BKhw3GpBL576VBNFPAF52BPQUWy/B9GA8uNZzZ +O5L73m7yMcUeMc1SiZHW+wQFfRpowzj8r5HgzrelUclDybKRkUjkAtIJHCNjMFFI1FI8zWyQrlSm +Y0SsA8dzEn96BBRpnkzICDBdcM3XxfW29Q5UrePnuR+Xn18z1fE4sjxPCsGRhgQN2JASqkri/lTL +YADhYTblvLg0OwHlMJbyyK5F2Z7zxv2ROJSCjGQnOlfhOZZCUlzlT6+hQB1FnA19rB8G8ZXcQ1dU +Ft1ZWG3qWSrrzl3echv2bg4EJWEZ4QiQBiMH7PW4+yHo6kc+dXnWMB19H4qR8U0+EPh7g1eq29yV +t+z3JSs7csz9Yf0+FsDlB5I1L0jDiOP7nIKfJF1PH8wPik/kdARv+3L6PYR6LVjZrdJXFZm+lT9r +HopwEuRCDhlsJ+hE9LuqhDcfTqB4ipIiEkP1ApPwjDAsywPO/XDUo/NCjea4WSMS+EG/t5OSjPwV +49/uH8y6ouOxerQFOtsU7wzy+qGyMiPwCCwzGavKhyh1NDjK67CPmnLCGH49nKiKbgvD8rQ7WTfF +0/ULcCR44so/LB2T5Gl0NoxnEyXDHC7IX8aPL4d2nMwcl50hL703hHeigANUYGG24B4zdZLiFAgQ +J3AQYrOQ/k9svD0yRzTwExCk4J0lmF/SpYOjN3gEdb7X/MgziHKjwkcPa4nEYK93NTGcQrO56tSJ +DO+kitQzSYlDXIfZll+hHs4rP5Uh6kMp6u2plSRv6GZl2PeA1wQaLVMxtHYvlxHxnWD6inOGxeFi +0JTYW2AB1Tyua3nSPE23jGVcYrrY38/qtcsVU/PkjGtoGDq1OBD1ZR/4e4dDCN76lkcivmfpBKzx +EuRL/xZCpkLX0FEnXAI4zN3jT65bjKrNJ/Pd3txWIBgmLAAp6ae9HYqn6wcEEweKf+rfrlvgRtfm +SAidtUnpY8tf+us/IIFg4E8KTiUWCtsXA8Vv0NVgeA4aKpnmH3m+NesvDIdbXTKUO3NEoCujT6nm +38Lt1CyB/JKlzGi+BUvu9VIP88+/YrQdlags4dXMVJX+JAVcyDGxnMFf6nmXVksu0ecNTCEmzaEs +LVb7Mt2J58sRy6GxFUFjyj+wKWNmkjkeI2yMYCASK/YgHOjkh6TTa9Qzzqul/yNcEBULTBSyccFb +tho+tapGQTqHIjG90XEPzArSnNLEgH2NjjvI2hGYWAkzJNPnYTgI0XLY9EzCjjLx6RsAthA8Kby8 +s6hzYp38HO6eXWl1+hHdejODffROAJTlysudb+mGJTMxw+4cpM+650R1m27aXKAZbzjMxI70mKnP +2RAHeK3JRjzNErYo/VgaXqRGFQEtoAceEM8vJ3Jy85ModVW1iwr3nohxNNPlC+yMWGndLCvF3jA9 +Fdmf42H4RVdxzDCFsMoKiE7qSnDmc7JzaDoyRnX2S0vuQ/2ztG0jl4PVE2OrmVlWWkKaYXFtHowi +e6j+EWV2wV60M1UzG4sAwj4sOO2xE3O3CjIBC/0qQyO+OuW6PKlwYxqQFxzIOS2UlyPxrIr1JpOf +znQ6aWEaLFXB+xss8kTm1k3yFTohPiSBLbQhe8vx19DB8lbZ6a5Lt3e5f1/91C9047CHwlBnpwSd +/22zgksfL8fEdKoqbg3BP1VZ2ZAGywAjlndwq4ALYfZGrzxzQMhPCUm7gx47JNsgR4DgfNy23Kms +Wq4k5oi2iNnYjuel7cDqGm30UFzr+KE3B53x4lq6dj/Zlc9bWQA9RtzIanME55A4ZGeFRgdQfd88 +Wl+luqAeGcg/FrtbNaNIdgN2Q8wcQj1LXs+FbN42BL0YNSb8yziaGqGOvJAb9TVIwCL1NjyuZ3ru +X8t+ZLdAhckMk0/caxdgnuJZtmZGH13TwNcoTVjNe3pE57OJt3X24LGWFESyMSnL3fIVNr6wDPnN +3SbCw7BMb/tlPZL9LRmPm+W/TBuGNRY+DwvpT51/1MCB0RtID64U8bOoCdbJX4j1iSjQsU0acEpt +yND2AJwUD6Nv2sv/CRP4PCNXa1whJ9PbANky+267gdhPwvv0os+Fo1lmAC1dw8Blvz3Fbnbb0U+9 +68wUZSDA0IfJbg5HVS+XWUWgxHuhmwXDuDZ/x0OObS7Dfh8GyShMsgyAaOKcPp7MQohhs9vuPztd +TvLSXJIlbPjSIVLOnpf4NntBCtjdS25bPmCa9ZO7Dr6WDuktHBaxJhd9B48VrZ1eO8mMxYhki0ts +FNdkTC3lVX0cy0ENz/fBKC/BmIJOCh9Y8+q9AJKm8xtpe1+HGaG6z3fAhFPvnaSl6uTP5ymmzQBg ++ll5Q81oDGPmXp7rsIOB8EHIo+AxAjjNSt7DwJcLgDkAH4J3S/9wJGindGWfhnc+iW2y9vC8HdO+ +fFC7t0YeeXT/66kvC2UfwRO5TfAnFy0thltTDnAEXOEaec+4+dkzsx0r0jPZKNZeVq/YIFctr/es +sC+GY3PS8B7lXNVCm8gD3rT1crrfc9XmvE0qtTItRX29WVaeffNnfuTEcVai0KiSdNwZ15so1zQZ +Z+Pil7nWSaSyMbE22RfSVo1Cj9g4k7LxLWj/48j72klXkqtY17VLRM2cTs0V+nUnj6uS8wiNGR0X +WjOregAsj5VCWPxB99L78ThuUd2SDmi+6dzSrhn4Kp0Hl7eqOJHVhvAa1qMlYUU1ZIbjqdmanM6R +TNLv7NL1jjzBemmhng/EZ2+bwmni3MTb/lsO4R62Rc+3tVavRBHuAqyYPCHmUVj2Oj2EJ4wIVs5H +HaNyJPAtB6J6lBsH/VtdCi3traDPlNCVqR6vTSsKtuMvgLKekHQ1FND3GkQ0DEvLu3sNAMdcbep6 +Mfy6tXvQjpThcNViW9byvLglCzig30/xrm8/eoBRhYQwUUBxhIpimhgOswOPgNB27X2VhvGPSDEk +6XYcnC9pjDgO/vUBU24fnpfqDXd1MYf8wN4UNch4BC+2Ar0zQJVfjrsqUspLeYa/xmj6fWnZxuV5 +1Ny2PXyjBUsxtFLc9911TeLLlC5QVTkiUanFjIFH+0deLjRkxPkgI1jzV11YQBE24wVuV5YE5Mjd +rkWoBav56Diyy+vUIssq0AZVCWSTalaToMWTzNPQIvBC1VwfnBJ/FOsIkDJNUADKoJaVnAJf2EYf +J0KZUpvwPeWtwU6b3BW0AxNIpAvzyACZ2M6xHx58os+EuzEQ2no4zH9NF2jECNtJyIZ+npnSJjdj +y94dbud3tjfbrnUIgL7TrSguKJQSR31ORklVmMjWCvi4a11RJiF2jSPAudL4iL/ta/d8eLATJ+FX +2vBXXT172bj30yUzf3x3z6sZxoqvRY6LdBd5cH6XXORys6xa7DNesYr7vUwrnvVWbtXIc9/bl29C +kGcCTafQ1bR0XN59UYBj00NMCHwFlNdZbcBKKmtu5JbCyej5SSPHXqutKp6TX1jgwPV76CZm0ro3 +CmU9y1MSyJY/AKwfCrO9rnWkGlzrpbzqHG8Xxh4rJ5YvPYY+vWloI4/ZxKsEtafiHfE+ajjRmVQs +5dRZzqkW+HTHnrJ/FXXIGfxZWbe3DNy/vePLfV8wkq74BlfLr2BAllBuIcLf6p2/ML9K5n3oU4qb +XHmbXfS//zUjvD/COymwv0GgDTSciMba88w+ydM32qWqZBxVrEDuEwyBykHJALKJxv7oog+1B/y/ +Yrpx4ycatFDX3IExJGXi33nDpBBRpf1HlFVSxkLaKmG4Unk5447TVdiGPp17mr4tL3wAnUcpoqBx +ZqNxRBCY3B/tO/oVz/zG7F8z9SElZk/MNf7CE2UcCgmcIuIMONyRnXdp6e+opyfS3HU4FxDyDX/p +x0m68P3UinUrvjNpM/tP1jZ3sDaZta9TviqlGVgPWea1+Ka6Vetf/lv94oyuLbdZySVAYPUdJzqS +MrqP/WHv2O858MsaPjFSj5LURRaDXmxywe5nouRU5hsdoVQLZXtpdRuinOYu9FNYh7fJac1Y9Src +DdGeYAH/ZoIIdBSAD36zpCNV8lpAL8pl1fvhdWyqrUNClxs5hzXiVNUUuBBumg0e3kv968W87ho6 +6AOH4UzuV8RseB4MKHjyhYVSXGfYG3yg0FIDBtASSfPUSF5GWgFt6A5XVv0RauyHymi3MjkikJCh +kDSBYhbY//Sg65g2XJqcm4yk9yV32ukWIkxxH/nSEsrw6W7+YxX98116argi6MxA16VQv8ASooLq +5lVrESb2X3yEUUGsC1XbhwNZe6rzFhowPtZovZyKfuDZrIxg8vHBQjWnajv6yNFUMuWmPeDrXAO2 +hxfjxqWo4nAx8E3NNZ36yCwlsIMy22/VCb16+QFtgtZbrOkLpeuTJVlVyu+OjRh7guEBw8Ra+FRY +eVjMCp0kwYdlF232pEF1gAL8ZRPLLpB7wuAxvyILEVteQR4aVcEsIHTewRgpoVzKmtM2IMBX5Z3E +UinI0z3cvIAjfhBT+LjfLagLee22eQq1uriybixKh/DJI4rkcZvdfyASfh8s/PEori6tk5tDeKbF ++N+hg+5+Pm4jWXEjqr9WF3UYG0+4WpmLRQdIC/SnY/WnBdOAL2tPcUr3PWpyKD1kE0MnlaO2QX9g +rQX4N08lpAd3gkSv36zXVBcuaTUDYiNYF6zgmR21ip1uexiMaI3pRxAQLgYEAWgED6/WwxY1Bm6R +MSdf8xuwjyEuNWCsqL09BF0BlG3dJNwgHQLepEeHlkn85x6yq+2w2jZYP9dhzeCLgBQngInbyHwn +1W/vWO8RADGQ14TRbXplgHBWlW3V/jIa4aP7vPKguwLi2OBEWua/36Yv7s9f6YzcAA/bSmcitHZC +hR2bvAfKrZ/DQU5AFnfUv9vPgnVIP0FeYp3HzwFBCxKu9J8Cl5CYsPkrG3qe7X6HQqP0dpZ6FD5R +OUren/ZfS/c90SlWXoEuow75XgcUfEaYG1ApiUjJ5vxCPrA7MKlgywBlFP0CXRotP6CYMUV9p078 +alU9VfC7swpjP8NDZW+jLxA2CcopIzQQz60mwnXSmfhBWzr3hg1IG/AlDzl1T9oAtL/Yxp3vpqpG +YTepPS9GN7l30m+V8Nlj0JBin+KMJC4lLiv0rVR9ZXN2JfStY9x/U53Kxi1jixsYjvbHd+swVqJh +r2UNXBlpfLu7gHZN9fSPpCyP1SxO8VyC6w0tjJCyYWuvbj7Dz1ejK7NZYfGOsVVcJjK/TILpcQSS +p5ETdz8CNpUtjKZ6bHDZwCnX/9BHXOhvIPFgeqYWv364GOeCbqrvxY4dSJztOEqKDhLTLXdLwv5f +wTdqToAWKTlQJCW4zlOuZRTP+B3Dwd8M1oq+H4WieWbzisbDdhULPN0SqTGu39NqZkCntBpwJUZ6 +xUBQUnlwQnrojs5HxRT7gdYMDK7pivUp1y9+RunZdlZcoHI3g05wbGDvtt78FrRcBS/m5Fk361Mp +iGt6mhSXaSF1PvwlGI8gLp27/aSVs96WW3P+LNGlRXS9pCcML136jzLhOP9YFChx8GjAznCYP1SO +uC0YbDcJc6mmCh9B/HFzWDsSO2+mFii3SYEfDPMFYTsHisvokGtM05KHlYc98cfFeAZPh09A0XxK +LD1hYN0k7816rtpGVMWrhs9YWUc8AwWqECTn1Aqx4eklXaljPOGl9dSdKofDumZ7PTIqObqNpbS1 +HHurhdX+7GhXxHQzMm1D5I7iTzQq/N+ku1OBqDRrM5mDgqOFAkV176Mmuhdbhh9Py3BY+/Q4bch8 +NVb3x7YYA2aDGdgToOq+HI8CCVU19WBNNTs/XBF0IBNFcYAYLktwHy2nP9Jd2EB105kHAY30qXcE +tWgOioSv9uda6l0Hp9a4kgWcL5fp0UjeiLnvG2o4aTXqE03/kaw2rMSHw22xUyXO9gHvC6MOrPUP +vBEDyPfDRD4o9T79/BC7SfjLI/02jit2xO20TML8PZTMz+4AgfQqjKpBf5U5s1akXsm5LR0HUMxq +ymBNqvEtaIMuoCLnWuTegImZnC/mIXHFr+l0OL4QEwT//VRfQ1404jhcanvdo5yWz23u/Gep7uwA +3Ado7Ftr6TUxRiP++qjCAYa1jvKU2HA/O4HQuqGBunikbIQl+tWq1bj1rwys7TgHdsdTU3MYuXZg +AbAD+FDg9JOKdxdDbQzFDnkW4hMXcP8qMyPVaVcmUMjjgJp43dl80YuQM2toJ0ItfN+0K0BFzPBA +N4lhL5v05THNRH5q5WoWd5uO85n92APduGXrXgBmVE5MAWclXxo7sENmxG8t048IPvORAE6cTBxJ +jiH56c2yVXflUldYBci+Co4ESEitdCLu+blJf76h4YVPIyVf43YXGLJxGRpwVnpI3mq4HIZZDsQt +/CCueZzglxNgndw/NpwlhLAxSzELhw/Zd1vbaDlXyvs1eu7FrmBrdDEV/2IJkN5gcS7Fa5hnRB5u +Ugr5C6YszaBdikXxUtoSGcI/ybu4mmM18BCmIF8qxqVmIzawHyiUuDY08Ts1w4gtS3aDxv8Dx1Rp +T/tUTGSbSz/pFilTP6SM+UtCBTgbeEe5+lDVuVSVjUOnf2VRD2KjOb5rYMFsT6cHW4kVt3uDYExw +HDJW5Svz1GSHy7v9XrhFqU0nVISSYZBLeXubOIN4PnzNnsNoKMwrRBZ7cJa7Zih+N85vpEtsBhW1 +SmyA3nZSQG2M2l/Ds+uUHauYJ5rLSn/zvysMY2PoYKoe03mphvSRyfeu2BH9Cc0QlTBbjPfYUTmI +cnQ1QOW/l3V5ZHnLLDi4xQjs5k7jPdKpOw4PVvICRbMOYBBDUUl63cY6tz7YKgkliFHlAQzLnafm +OB2uBkdu9/IEx22v3xMupdu9GJPgdty2CJhkAT5VRXKPm/+KHcz0nNqew+mq5oxWqybMEKD872l+ +JYywueajKTvxN38m21fs9jem0tt7yltUD0X0wXt0T0LJxOiNp4fUryQQQhxLN5zQHyot731fPO9J +RV0YZOtZm7AOIX/hueYGprnk+k1HQ7R/RcQCdvCnUS7D+2GZLlaFoZoqCjMF/B/wtXAP5W3bMNuD +86Q07OO24Fbd333PZGp00UokOWOcdqrTNBOM79fInhHyzl7gZAnQAiebl/xrORDZGLHOH2YTLDGE +lt0NqxljgutakNCae0C/mW9TtuYFnzao22HNdUDMjDMMAab3jSIIEs0NjpYsBwjXB9STrdmv7P33 +4Dw+QSgTJjKCx79Bq8oOXh5R4zMEZG+Eo4F40OSVD9zUJ3oGOPOikgcM9lOZNuQlYKLTtwLQfw8y +f5Hlkfa0eAXHyBSZmAgG2U5/TIA0bdlwQHtmJti05czTg9aAXeidISmlVYT5/b2PVp4PEKsTpgIe +vPyliOqnm7dFI2XfmBVu5QiuuSJhDX5BMgHNdkShXYmI9wYS6sphgCHTTR2u8qmtpTgwZm8dgfFr +rX6IZWVeIH4fhynFS1mW8SmWz8gM6phlvfAs98GPJV/nRYLxWih7gwpw6ay1eF+TymfqU0r6CWtZ +iWa0GH4AzAEYW1GSe6jf5JFslgTMmHQsae43gH6f7nNTzZGxSP9GzV9dOvA4u2BIiNv7yvpgvyUb +NWf/lI0INM+kaXv8e9KgGG4RlX4t/Rq9uQSB80vOzucrwRW441/Lvk40o5zCG0CM2Iwhs4mLNplP +y/6Se+H6C94Wc1qZsSirTtkaaTURLwFP56Bgb3/37GzLskPc749Zwh0N28Q9wa+jPlEs/LgZxW5n +5dlnsGTcbmG1sgC/Wu0MFrBnApRiar1+JC7JmAjDu6jWfk4y/gRG+f5CpDxEO7z86zeAdGMUvjg2 +1NT48UILHxdBgBcr6vRkALnIM0dHCpa+DsLmvRcUr7a8I9mAocbk9ggkJ8igWfld4ldNckiV1rH6 +KDEqas8+jF8x8CocZ5YKk0Vpu+tVaWWDKoUdciGWDDxJgjQOmUVOGiqBsyesRLtAc9iHaj8nTFIi +q7wXKotC1W4sZ+Zi0Oj+aFCRiOitrIBweyga4Pxxco/pIb71UpiYmxHRFT61ZLFC4f2u0bSp8aZb +zepU0sP/D0VonZp0EvWUPXFluq74+faonVY6w6hh4dojB5/AjZINExGBwvvw1t3fukj5SLAUJ/lW +bbBLK29ebn/fTxJgUw2PV+QvBjKbyXf+4OLeCSXY63g17wBtGGuv2zAMwR9NgSGqffgOW+iYhjL6 +OAFVSkW/JWueAIpQLRuqgeGAYl4tb4q2HppDAqQBWKSywZJUDiQuyB6Z07fS+3LHEA2ycKIp12B+ +UEYvduYZ3U/ASzDQW7paqMb+Ji8eCEZgurDXJCa5NzqfmVT0X7GNFzxdv9b42QErcsWaWdjpTpc3 +0Zw+7XolWYqJOcZqxft80uHwE4KWMukJ4uHnjF36qdaw9inPLHxF5p+Ka2iFYFfXbckOnE1HzfQi +Vd+4x2pjb9MCHrnQmnJKNgVzW6OqtAtkSjsUEOrSF+VXAVR2EcTXjWxbAgTwQIuoqWdGaF/OfV5J +ZnJDRMtIgedI/ACqHJErWspCjct89TwypIy3+K98+hhjbmBJ6if5IRzGf2qIWgtMGeLWqHXGQ/b/ +nG0aJ1xmvydOIWM3eUfLXqLwHjnTJGNd9MyKcew8k9MRyjaRoQvmzXNTv1gGfWrCge/weYPGEdic +yM7SESvKzGvkze6+4Eb4lOzhsP83HqjP49uStsOLaJmy4+/mVVgxUH1L2n++o4RnF2hvRPgYZg1v +Ws5ym/GFEIdp2Xoj08O6HqX443yDfw2b6+PwZBBMZtQBuNK7NPfhmwjA/1YKjd5ayqp0QuN05iUn +3Ie+K4GPDnX9s3/Ws0pXRcwy5n+Aym6clo/JnspzPUyOEoUrwRbUxlHkZgQhLPjbWUovnSeXmPk/ +7zgind13VclQkR/JN2la3duoMaWmWbF/jqChYWW8Gv8LHrJOr5Rn7+NBbfeePJyWErMdkVPf4gNF +0KMDwAosoaRC+8ewM3zDx8Nia0ATeW8Mb60rDgOZKwLG7gER7PSJ3JEJqDzdNgR9n4iDF4+ZdjsH +3NO2Sq7AAEkZbm8DYqzx8nUuKKimWUFCw4hcr36Cgk3EjR4rDXkmTA2MTMemKYQrYBU2TG3pMHgE +x+Ate28b9GotP5/YEe97UQjvwPETw85ybL3JgWsjdUtIp62EoymkbS1sZMo3/FjckukwL4Xm3tas +QcsYaIb0QcIiG8gL5tFQFLn9CcPSyv0cN9osi5rvEzkJCiyU/0pR22tdLfaeFkXb/T7PgBBBzArR +iFlU/2SooAQDuy/Y9cKp4Ade4SayiMzjXq8dCT6GK5/ssEvrD4N65fe0QMACh1ncSS2jSPM7H1ww +YN4VxlcCN+mzg2eXB7Nm8mqOgNhgaX7YxEdPFP/28MzgT9uC43zrA9dz+KyFLYhZMy4xnuv04ha0 +ZVPdkMTFBJIuOUgK5DomosXOq+LTBTla7FbPJzNGSlecizj2NFkDZKnrYMcisOGEUXR4D6ZGdQ4g +MepH+QhxQMe/lf+wuDnDLm8KHtEV6tQWhyVxNjiDSX4eXjpdJPuTUsDDjhKofF+5njJa8EmonST8 +Ubs+IIraEbkBiybPUsJQ5wBbWHv9iC6OpuSOiPc7Xk4c9qbKRdUU6u8L0epMY0WmO/NlHVMSI7fa +MYTphOIfKPd9EdEMRDrhBoZdwjkAbkP+xDJHaNiOTeBg5Apfkp0KLJA+OUyC2E4t1B5wZbgya4Vl +gkCIw6n6+GggM+QbV1mGyy9Urskjd9fHRvRQRe14mavhxPXV3Fb0FxYkjy5aO9G8ecLFfI2g1hd5 +hqSJg0YYsy0XYjb3S6GdVKp1y+KMBrm3ME8bdRTFIO3gSWa9Xjue+qzhda9poU5lJfO8x3gBozDh +rGqwKqa+aQTIIVXllBxqjmuxc4HRGHCePTAY5PXTlP4gvxowx+RihBf9WssE7I9bfZ8DIKExZyUe +/uRqTvEUSnmnDhUo6vQlnjV6HvRzE4gPpJg/e+iPQtYGm+DgtOw/Zlj4Ppwu6vuyMzCiUaT5ryQp +QgWWwH1pyFU9wI2xLctOOmbfGqRkBECgHAebfDSroVdhDZPRNKYox/0/54kxBXrKzUgtDDxbaU8r +waBDBBo/nMEAOXBi1bRa/BVjmyP5zOeJMjV0YGTwa0iS/b1LMW5zk/A/ExHkSNV6rSg+ussJOcMj +yeuINq/YCLrvlYrp1cJ5l9AdDyuhE0GDb7Wr/EjDItaCbzDHFUcd0duhP0+sbQSeRabbHQlGVsTq +SX9JcuWU/bpk0rDzViTnJTPTpM3hk6d8OHtkrdLbMu/Prx+tX3ActT2sIjJ4t0rXWdc2qeSFFEgY +egMbS9uDdcFvFMCzdvqBtIdsP4Lo5sJ68gxzsHcpnXq8vmPEWTkC7+47rLiRbw/5jm6v0Ef0zhsT +Fo+NT+XaQ9mf2aSF/r/XZ9S8xLPg53zrSSpi7QfpDzKW88cmeHGn7jT27TeD5zHfYhrkmhYp9jIX ++gPf0Un+w6IngYhOMf509veOpm0tAI6QTly4RWXP7SDzbqKcZ1wN5rl+7PCA5BuBIOC7oP4taVx3 +kNRbKXkwtsWeoRz5HNDVK+woijdreU5Okh30CfeDQfIx2qfISWmfgCAMmIpwtpzO9nh3IueVCtSf +U6chz5TYNvsoue26nR6v2hFPfw7lUuRN79w6ZSOe6ZjEqIWR1UUdsvyXGOICjnYGUVEDdUdSNQAn +DjS3rWQqXzAjjItJCZhybI6XVBcX0MFrNs7X5yd20TXOm2cXRSF/u5HjiYakYz4ZGAaXexw1DUGC ++5BpvlBcuQj1gB2Y1s/CI3Hx4DrahxRsPF5A6vlgHUaJysSsJbkhceYu9eJ4s2Ap3PV1s/dofivK +HqeMTE3R0t/QgK6xyxfGDRFi+RVfmr36SJ3bKR+BXfgBlNKuvtvny92BlgKWd4RAq8tfccuXWOyZ +dCKez81UvqfKIp+AJjXK9fhY/pKxADlolX/CPlKLpmHkgJx3dpQkKitht+1w1W4MvvbgIMvzmyxB +0KKaK8Z1WjiORyueXfGxddjs46zbv3/e/vSgYwVtM45aDqZDZd1zvbJlUmjwpe/7p3gZS7gGAazR +GHGD75WLkTrysoHT4T7r1yDVDo1b++pTmf40oqq2e+/DbF6z4EEw8QIgrf0PEH72T8IKDYpN73fW +fzoKR8hV5FOaGKCer3kxSHlEvJOqwEub0i/sy98GGXTQW9GWY4Dw3ViKLOLcwHchy7LdKEnLa9el +0Ft9rsrR47Eg2VKYRqlehFg96i1AVmC7uxg168q+bwPHpw68iuZHEEKj4JhuCUdsUWoCweOZ+PKq +LDJzGGIsfjbyisFG4SGNZ0LuN4OLorcA2BsVKVo+SLDBMfKVo+UN/3I9anxB0pYO7Zmo+WgOFo0c +jeKJw4OEzS2C3nCc7ivpLay6wIYaGGJGWX9jeMAQiluTfCbI0a4dpdt+4sKGLNU2zOBmVjoSjJLT +YdTnNbX/wRe9oXNl9AIWxUal8FHYyWoYWNv/dga06kGiSWrqr+rr8KShG84EVgPnB9WOluYlWnwx +sm40MiWu4MDfPK+9nb2Ub1CvUpHcjEqu0W2nVnUEGqP8oKilcyMk5pQsFU6P41Ofpbt0RrEFCf2T +pZ8xw0uiU7PeM7U8ugsc4Gf/RE7idC/rbU+F8H49tz6LIftN1zpW09t2mn2DkNxU/mU2mOM0aiX2 +dreep2f8v4tMEiEkQZJvnVs1JacMhGzLN9CRTp3vSk6+xni+1SJBMvbyaszkFaThRGW8zmWVY0H2 +nTOjWrqqBQP6mNTIgla6JWGWjcc6KfUS4QkM0v1LUYFT0bFbuXLXXy2qQRBO90IwfrmzD8hukrYp +YBkIavVaRCiouO2CZmfG7F/Aj/2gLGd8fTVr2Of/JOY9xCCuxxIV0wZwVZPkVHnFUNh01DP0isXf +f46ZEnyqWy7Pcz0nPY9bxvAP20ZwPZb/qOZ20/ateukosrSR+ngApsCI7Nz35wUmROJfSKMPNzgi +mjuN4u6rty1KCVC6oMr4J9qkehd0ZCNdBtMCNVGZEXWd+Yq4mRxYuOeQO7MrNkXB+nDnB5kSlTwH +5bT//QivCZkXPz3QQH2N6RoCSt7xbTufY9WyzYykFwDb4ahl0rJYONQfhgdrd1aD+4hkwL1MFr9d +SWbwIRvY/q1FIHOdwLTXCHtKcZwfxHEaBaXTEXMKVLYgcrlsXiGOF26CQBzUyM+3IhOa2zXfjtgK +noZo8HKnpDoMFOXwxKecSB7okIqRGdMgWL5+2IAO4I1DaZwEhCFLf6XVWSn5N/xnseGXVjIuShLc +CWvDJoWTV2s7T75ukjnSqvevOOYcYP0peuIX2EPsW/9P90IOZBnH+KDRTDqsBq0IlzMXzGLVvqA8 +Jt7yBi9pu4hAQgNlI7uIoEC1pb5vxFLsqWTPWIre3RLw9RXbz9oDSKCYsMxsWp+B2SCFIfEnhDd5 +xmkLGBdn7+kAcnNbdshb0+MSSXW3zaX2VXh2k3+Nw5USuHJrrsBCaNMBDbqqTWhYFkzCwwZUZGNb +Gpxmeyowb1QGNIPHlfboQ2cTvCvSynjI+bPrkwxJ6E9v5+c5JiE8pbn8rx62la/WUIYfXqrMcfL8 +lCyuFOMEgWqRXtaMt409LprJL9pHkF9lqunlo8LqzoOyqZizpwOdyEGgYxGhH2gqLOr+pdB3KG0+ +SYnpHufsyO/Gfym5Xs7mCjai6cwwAzDAJYpL0Pxk3ub8x0aWn6H0+6kxzhvT0clEKt4ck3mVdzBl +yM1IIq1dz+wOsH8kHF6U1+HccJ4FKyZDCjNcHEsp/cUJn+s/gHNvTKccnJhOTmhfd6iz+G3PzYys +N7Js/n8jJZkKYqwG+HVG/vPN6UXfB6LEA27DhGGFsAChPr5Qamh+wzeyK3eghvethJcQkWWvwvN4 +2/SBaQ7BxQGAGLNrEFagBfGriXEMUKYwUwWkhtc+dvyKbEhqC00PS/0MXKxYy6/CkjyDsCIQ2rgx +2mJmbdTJylyAcR9XARy1lrOV6bGHDUemrko753995v17lWTa72bjmQEX1a8O3lpOx4Bzlg+EOo7G +VTYf3KsjmvWiwjmSx39EyYB/MyHA3zacjD8M63UA5HH3G4vW6HPGevA3j0wXMOQGCutPrdOz3c+Q +IT4JadkGwn4kJ+773xLdSul+Z8LgNTAd90268+Yn1IEKkkXAwujhyRWEFQ8NTGrTybKHow5rmJQk +pa56lwEcCgU5wzLpE03/rLfmsioE9WjuNXlaLV+ieSvadDnkcPTzCz7Yj71fPUt2HuCWRc2thyiT +3HtegbxRxcSHm0WgFY8FkpEiY7uRxdA0GoW2DhYN4ATd44MWCrKXtl+PQMnHjMJDpQCXVJVsOT2r +v762Px3FmAsuHt+LEMBMsrKUtXp8MjxUMEQh29j86ZdioeNGAEz2s8N89lxW1GEJM4ea78lkHoq/ +42Rl1UqUG+VYj0y8si54MJUXES8HSGpMAPCbYLTswApUug2EkH43IjNgrt7NYzCKmg+kZwjQbSxu +oQPdyhNil0t+drw8PND6sjWpZvCL1JQfQwWSq3JSIPPohNMHY4oB1WasQ+U61xapwa+pJmDfw0Kz +V75m/layF/4SAnSyakyWO/W93K9vR/1wVYZMtCR7mSaEDEsSDscAVWgBdUJykbypRb8ClW3rCZf8 +pMZZwvWjDTr5sOaJgl+Q3piQ/Dv6g0QFoTMM5HXFmC++q8fGOj9A8Azyxqcw2kHRZXFHXYW2AZrk +x3qsOBDqJOniqvceGBaRtuN/9Km61F40uXYLIAAwz5jher6/p4usvxVmCE+1sTOE5nF5JyN4WM+o +DLkicqbdZFuVASbd+bYVv7Ecxa6KdoetwkZ5UWei235gKV5+wn9uMzQI49M9ndrIc3M3IPrmCF17 +2ozlz97jfMtr2O4ONX+kFffffSAmGAkBTI4asiL/iB8GQMSBFVDbgAjVtHXVZQb+sXIAHAqDmVEu +9dP3qEhdC0h3Ji86gDsFQXFKSwD7gH1VsEa7ihTQGjXWdlTB1/CViALteoTujlJDK4t3TddJAha8 +po3mOajIstOTKxjFkypqzCOH/nSfVVpmhUZZPR7+2CDrlwEFx18ggWkaTDf7Fus7Vt+KPcNM8a/M +eQhIUutf0eLBgZRO04txCarKV9OcbCmY/ly5u6Bwu5QHOFi+loC/UttQIwRC7sfZU66ZApGS55XG +7bRy4bAMWRULqFNw7EeQu6+v8N1hm79439qedVql92gs5nNR2tTa8lzbWRZHqH9oVFSODDUFCANR +F238VaA67o10HfqY32aHw8BGA9aYn5v2qR7kP3MiUFHy78sGPvrYmIFJjxtbc5QAg8qx07/WNl8p +1V9eQw7a69/3nio7d4q3mzx9lS5PD+UE/4NkX554SO3tG6dPZM+9FVAxB8FulJ5La8LVrDBckKZZ +GcnVPDMGKPP8tW2qIkLoLWtLaKBVrmGrtxB160Rz8xmhfZJ93OknX/aJsjBuVpNmSG9ldB1Juqkh +Oy0TlwYBu6gSDRaTw6Kn3Vj6Co0lOhTmx3xpuSbiMJLjD2B/DJ/++MA3r0ZSi9JPxjEu0G7I4B2/ +amilLFQ8YZfILECnRQ5elLdOESoejRKXNirsCK0liYuZlvVyNCYHpjXMQ/O9fLG2IW1MXnUyYjJs +5ntp25wYkS3PycOZfNn1MBjVqb5lQBYmKhKff4YsnfQfKq9ICt5Xu3UMQYUPS9S+2MfmveOGA41W +klEwB6CkIBnw+ZSDnk9GDNyzPJ4KZ31jT5tdgsjdTgIFeAO6fMYitE9yZCtbUxgOIpNAl2nY/4JH +5X0PLDAzTi97cIADVz39OzcXM8ye74O3vM8LCu/zS7jywI6CI0cGtgbKAYWmONROFOFoPjn9QgPQ +a/oEgUPfoFDKQvqN+R3AiaUUeyINvr3aqPdRFa21L3O1d5mDcj0WCb4Z24tgxa4f8EuRhwf92E/8 +dPeZkYrQO14h42gdrnsGd1Zs5I2n/Au3DUuhgykXStp3VQItwtgOASnhfWJYa1m9zzhEdO2xF2T1 +1rfKbdsC0II7Jc8U/YKxO9ZsDp71wb6R8SplUKPLASwy2TMkkPMMYD5swoo4GHIs2JmygvliYpKf +m1EDmiCandKr3j+WQTHCGE8lOoQlBKJ6Fq4ZELsRt65ypYuRssl3Iy47+GcYuuPzBEsKAeRowFhd +1sKF/eI7V591Yy9PKr71V2aeVSHksAcwFAoNGK3tRH6FUxYvSA25M6EfFEQ/84cRFpJkS8KU5+zN +NXFTQQhN9jAj7EtFL7KLmDiR9gBsXMuV3uKzYhJeMVC7nh7fNnzk4X2W9J/IEONUzgNoZiCsLpJt +na+tYnyaGOx1jJ7i3Bdo1wh+9m+bvcIDIP+BB3SuWtYet/jHEDQWYCH+i9QFpgqlEZlOx8fkto8p +uHIiwHK0lhgPrQx6e8NlyM+lvhmM+3chiFt5DsZvXow6cBODKPbwXCoEQzWRkGeKXaBcx1IA6uAY +oSZwwk1iKKs9Hl407sWuCx9V8vKBxcrlfUR5hH+EvkCN9karoExl3MdPsciwfOnLp4TzpqE82Jpn +xdlhs/LrzeM59T3YISdHa56XzLTKUKfnp35TKW5yYaFCeh+u2q7QptOxrYb38O+OfbYWcEZSZvQb +MiexmAwMVXfg/BdMyIQasN78/OKszNt4XLDANNNFGiw72vct6ZkMwCSVhEEEudg2iObn/wXb6oIs +9/wy9ETyK3NLix/tyt07cLpGecm8dzxsU5LsVT+zTiSzr0tdJ2XrUqiTyepoldF76rSOm/700FBB +ZfA/bFi5I99DncWg6dwT+L1I1HFW7BE8cz5LQwHkx7iSBJN9DUazZtXgdvpMEypHghf/zopVE3Mt +LqxdC2O5Pbk96eQwkyvGgo6pc+LAxlXBdOH/VUj6GdfChBIJLmZUpykPUey2beD4meTfDDRPSXLB +AT4zEEKVIKjrOvh9GwynPguEvHmVBilj7wT+KS+g6xiuSLjIt35V2wQrrtwzGfwDawu0qmdiagS3 +24AFcc7zU8kMSbcZR+ROtVkKRrqOeP8DWqNS1WdomwkB2U7+L6VHDL25fLGaBJkl9mjXSQuIHl/w +IfpOhG+7fGDF6OtcdcijQsLYnhQVbHam7rU8vXzb9coAm3Yej1KMuRVXAkZjo/YlKMWWro6pxl/o +hLA13gD63Nhc2Gtg3ZGPZXVntD1H9+rUXzdX61k0JzhIkoYn7VtDSFQDUqhUPZnkDVRE3WuGDo6S +7SN5UCOEeVrhvQUwEi0wPVY9+07eVjWnRx7dQrnwh/9Gxdc4PR5ZSQ3DqOi7oDRG4U4FGHTopPUl +esSfW698xpzYJaFNyEZEnPtRMNwmrpPeG7s4r4R9njJ9Ee/567yz5pEAMyF/zS4Lf+NAnD5cA5vp +LbavmTCi00AxNnu36BssGtOG3KLK2wPhGkuDozUub4oZLBN+TRSVKJx4A7f4VvcKq8t1ZkS3tnW2 +/GMNR8zwkLuv6UlwSjpthLxVos9hWEUIVbel82jm1lCnAUBwqG4cUFnK+yl6DakHlM8atltH6jSa +47al1BWhpet3cBuL9y4PT9YwzbFHkIrUTsXwyNtkx9TVEBRs1wOvENkMOfH/tL7PAyrTkvTKuUQb +afnUbe5zlQP9ktr0S1z1DuGtGuFmpS5ojM5w9izhHPZpAMP+/SFicIjYUuFnaNShSDToWDa65w/T +sNGx+TfUlJ4AfwSEYSb2xsMIPOsJm2C2Tgxl+TuC2HqFLwW87g76UcDs2bqL9kX6KWsxcgBYzTv8 +2gac+crxUWnP6ZoEOhjMAwCsRfGC8cBux2QyVVPUeQYY6W/SNrHjHUumntAhlQ46pBWN4PVmCG/+ +BWLLkOVPnCeh80xCDrnqyTGxnybj9963HOpp3GQYKKBT7dW0AU0d9lrZlrK0Zeznqbb/ZUiUQsPk +Pc9TJdbbcdMnRodrTblk/Rj/FhdcXFi7m+mI7Xw7MQnlQmQH2p6tHvb1FpvvI77hQZMWj2oea76b +0/bHu5ZMZNCmrXuVpsbA/CA7InCCKg+DvOYgqgfRA7K0/Hf1dGvU9R03WVFc8sno/9vlS/G90b93 +PNj6EOZwfU/FR5fn0ZRjsY0bp8ZoHRGHA6rYrYvJ/8KmWWkiNALEXs8/M7o66mJ/rI6l1rO2GVoJ +C3KzE4GH+uWpFtDwT2NwRHf46yWomdJ74PolIxA4q2cJPVz8RdV1fK5SEVCBtw68Tuu8y8Nc6Nn4 +i60jMj54JddhMG7IuJcMjX8BHX+KzzBXMvd0Qf71Xj2AWwRLWaWmlNBws0hbK3z3a5EGqeQuUtIs +nK4o2/pCkMhHWDfe05lCJ0BbUdOeRsw+I3kbHYmc8Jw2N9zTU5rE135TsBZ4mPxtj55ZmrOPDcEr +igiaiI+WtZvnw1rmDKanBzWBaW969zxCMke4FEVMcno0FI4JHVFqSfgLbc3Sx57nuXm/Q2IILMWE +ByI9u+UHLXxQOnhDMWz6BtFVIWpII2fv27yO3gg69QwstyOdR0ApZd2VbgeuH/AAdU6KBQ2SpsZW +/AIUW4LGls93zzazDCrRQDbk+kBDdP5/qyRoiP/iBnZ040NYKiK5GrpSoGuBw7jMFtf5/lq2Fqan +X53zquID8m8GrnaUcoBxyPSOU6HllD+6wiwt8SofF+0z+pGrj239d+8Nl6ZwhvjfS6M62xU5/Cum +9g93iQtpWRL1x3w/M+51qiFff+EYaMm6whJm5rXQuGhBI+V98wyVTOV3QFFK/hke23uT0WQ3yTG6 +MXSHijOshB7VV2/bDNyaEqfWNNFSY8ugul3SMIyhDgcT8QEDeE+fntjzqUIvVBIFPibgjlHzZQay +Zl4a2EZD8ARcqm5iMepEkNvTo9cvoWSOlddQpZP88g2hgY1GLaucxq1PlwFJSKvGvmhkCkSj/1Nz +WjplfT8itTgYQnPoUzu83lD7ztABA2ZOS5EE+8coMBsoAFZ4BEiWHjY8dQvWgxDVBvFfpXF6YxEr +CwS9o4BkrtBKIoaurje4oc+eM0pQHGiaCiUNh+ZjQcZoDbUreQu9XOhUUYuKU8pofNWwisBD7j3Q +V4YL2IOB7QafNYfn5HMxBR5u8WSOkI8HbMJVw9o/fED+qRc4EA1K9qVvTuwHZ8s8JZYN0dT0wMGf +aQKdwVSdpcxv4GQe1aql/QSEnegnIdCNOGIzSWryKrIXl2HbEAxFP9GNX/3GPx8X5jltkFJrU+WG +uGn7EYpXEPnPPtOyRMEa3TFQVnPqoBbmOU0stbpZR5fUeo3eRuK2GTyP4RSYHSqMA0LGD+eh9IUV +ammT/JLp4Ax/V50tJZwMkpZUXeZGb2cRPZfXoGHXr/JSHcqzoJV0ONBuJBUrYKZ1SAUotHYZjtFR +RioWHWWxCHsmsS2fiGNDvM5FPeAb/XrPq/5ExOXhAQawGxQa6ISYfQSRSR0JnrUzhOkwbAPuSoRU +ECBwx6C+fjQ+ON5W23VJfAJXms51KYdLRKhIUy0f4p1UHCqkaImpHBz7dPxDTRDJJPHPvNdGO3Ro +Zc77lbmpwcjUDS4n36ah5NqgCx2A2h6Ag3Yy8BBDJRjzSc6+P0RBVOd3hhhc91qFjZNaPczDNzWZ +HdVm7GGF56Hz+vN5F01x5VBJcuXhdQuU4SFhWR1Epz0y6GbUxYti1vfu7ZG7hkgFIx24OZSY0RH2 +7lR9oREGixdqmbid/V/MZAF77JdX8RydgtAw2+hzLBj7TKNPybJ3r6Rv8oixvauNm5G8MTbnMFNz +JsfirNSY1J3KNFGyheTsfBugr5RWcm9b2FNxJo/mSBI7mPrMB+IUcGYDSCuWeojtX7FkUlOBh+YE +eAlX+DKlwpi1DFh1JguSRYNtEuI+0ga8nPhOmYq6IcEagbJBpP2NojDGkjQpu4h6ciC4M6kpBdmo +Aqwk5JDjFJbZ+HMnKz7AOXEflpK4NoUeM7QksvZW/wDlyRnA/0oiNzMDt2oaaDmYhByr1gAKsUOq +0T55Fla67kKGUPVxxuawzfqNtQLUSddkesk8yIuqDGlyfUUaczYZrgBkPiRVrGFpHqe5+6U35nug +88Cp80H0BsCfUZ58bJeoqSTl9tno1hfcnv1xay/An/tZXtsYE/IKezgZgj9ap9JSR4zlRrDVHr7Y +f+AvhK6B0sSvRW3PJgahYm1EeFVi2JNhfq7GcpQtmZyByJRA1C9jojMcBLMRpFejkVlCPKGPfWWc +bLJuaZREyCVjmZvBUlN2rfRgYFxCtzEyW/gO020J7WFz2drj3hh0XymaPc5BrE2bQvPb7VyFr8SQ +9h4DyT9YA2TcJCgkKJ7HDfN+6praEmjqyas+B8k2OMgdYPhYyS7+cSfgGAm9tppEo5dyKd/Od5v/ +OsNSMXHNM89KkOIxKYc6SuWcfS9RMK9jnpUaKYo/m6IsC0fTd282PrS+21eCwT8eLvn5ZksTxREe +m3FoSPRc+SN7JF+irA0bARJpRSzxbSP+XKfWpMI71CQL3i04pKvKOGsoB6FMTgEcuqUAZn+scBFd +0T+LdXm6rGaKfqO+p36//ydyr6YKS+Sjt/VmbwjigaabmE7u2paIwTJQ6f8VKapscgTstmaYgNQV +bR5Wd5imS5m75rNQ6UjCTvHhBHyJj7entv46LeH7bESc31drA5HQisWmZfmlssXyFc78/5iRh6EM +pXvxki1WzaU3DZkB0Uo1kNZ9LGDUGU2W0RplCuvfZFXIjZNv4gOk1GUacx/03vtMOyM2aJHA3/ox +syK1Ph7ms9gwQit/qZDYp17paYGYr5V/ysdW9m0X0klP+F1eTwgt5S4dE3YR03Fy1eNCANDbvu8+ +31fw0AtKFpk9MKdpURTBaa6xoP+VgClFy2JzS8U6UH9jO1/KVzO4NroMLTbVewIPAX9QyJMNihdp +OeT6bvbRq3Xt92wAdn32iWRPUEdwGcxeqbbFQzR89TsaC/G3Ns5YtOa/wfdC/rj+qlVb2FzC7eJl +DqJxSPuug1Z8RhiPd3pWlxHkR/lAaA2eMURGFpVyVYZeNV86jEkFtZ+fVLoHOrcnOemryWdBDhtM +uBASggoLYh6EdxQ9XR66cdTTMP4vxlGxTus1H/+3jJIp+BhrzyRud1TTrQ6FR2W/Vut1n6TenimY +AgwBgD2bSAIEcba2J3qiMI+85iXbZw63aqNXQYUnqiHNpjO8XkRPWWxSw9PQJUsSwcF1/8jkrfmg +fL9aGwGo9flPx9d1ijhoPyfk/LJSCRZzwd7eLofFq6vSIpfapg821t/bskJPkOF336QDlPJr8T6W +C2yE4KwP76WLB1OPbQ1RunyWhihtWE52YyuQigKWvbSa+tnCaF8Xz4MfbM61rq9jbJUuDYpUtH6b +pZnUMC+v6aYozGF0pthC3SSFmmTMfvg5H8d+V4b1kMs60QW8o/klzAN833eOvX2bgfVpL9KqafUa +w48ZqK4vkQI0WcKxQsOHxpUOH28dByhO9xuKjjOuQujZwLqmfx75vUDxIdf3N2QrPBWYVm1dHbNx +IFjYH4+Diytpm7LNEXo4TKiondd9ANwkLpEfiV1GxftFQzDQ2D/S9WMNBgSCRm0rFBhTHpXU+kzw +AfMdRpkNk6Qw1t9JlkOqkXWHyP5be0aEhUakuQkgSy93Z7acIh+4b0ZoEe5oFXzJP3QcprGWCXjc +dAtTTb+idvlnNyou4oTK1rD2MYsgWNUTUMVn5eYNy1o+uiVBOaWYkmnSvK/FMXdvsGl+a34YDPPF +mXPuGoAcONRyfIGVYOMeGPrjBN5DJdsvbKOmvzhe+jEI3v/ycEIpOvIrgDIwfK1IMEbOJbmZz5KX +Z+8aBCewWGjp/LT9JLkjZQu065yH8+y2xSntwc7lD+91cCWbZgF6xwVzzuUuKZeUafY0IeP/j0ou +39aKnw9/lrt7bmutJDcZXi4vPdjxB2HTe7drnD1B2nOjp79wTN+l7tH0ymYJ8HGdzfCPIYFinKeC +7xD08vwzmjExswHh0X5MWVdK2pIxCPMDpDxW4yUG1jeMNAx++rKQ0C7GKsJ7SuR0GqktO2yO2t0S +O3qPj2rquYlxULk0aOp9ysEVLqaSuKKT1Au05ZcTtfS1o0j4tVUT3f9JMK8J1bHJcQgKWRuyCG8u +Sm6qFfxy/Ez/x8MhUkL/B8y82td0+owJcXIXpJZJp1GSNz4k4M0NkYUMbge1CycMdYjlzwIGtE5K +n3sZyuoHZbrv3fzGdFjE+c12wV/eKTThOTU6zTEhMoc40iB4CvXD2G98JgaQtnV3nM6crRnTgEL8 +ALs2NuO+YqjZ9/DnMdyOGupB0LxWOo4L43dtsBiLi0SUjmyFFRUGq7k0s1oyDBISSozILXaiC9jA +CliA5+a0KVqTYd/xqXfu1t6GqyM4Ydfp05kOCNAI3lM+zTT9EpuKH5wDEVNAM8gREDNgYeuqoIPi +8BdK4racj1Wqf6aIyD6HmeGxOCMnKqv7gaFAy0oegAdhPfpAV0bwz0BJt8VN+TKdOWyarkDMh3RO +CFv70XIaJPLh+4lRVHkVGf2bGRDjyG0MvfnnXX4Li/q3W2uJTrlIcNmJGcgsqv/lIht04iW0hHDq +Q4fHX/B/yGyzNiA6potvQfOoVWQExzwY5Hc+ukUgP4l+UGCrNi5VB/Ggzrg75OaziPrnjM+wr/GB ++rvr3KMsxJHZJ5aZLlbBDcv03dTG4Gn6Uy872fRmD/NfOpf/aySGo4wZPjHGyo4gb2DC8lYCN8/F +yCYe+jPL9IY3IKV4rHrvJCOGaUa79JwIn5iIPkazkmCDV8Dt3KpqYP4nLOJ0xeAflRwJwdUiigtE +nHfKNVQkLMGNlqkU/RzYRSSAEsmg25vmvEK0QkIQ0XB2/mIwhVPGzO7yziEsI7mW9XBAhUxvTf44 +koAOrAbIHeKCMt2+ZOyKaKkKVychn5s10hQ+jJWyFY+7b+wLuY4kYVUeyrMF72KoqEKCTuqo1bBp +yoXYte1ptnOXGvawpn1xmUzSNfMnSmAtxjL4mazxnmkMZQRzRb/RzsuTJ0PHBO7AkSBBnSkYvytK +yKL/Y5ZGD22xlXO/mkTicRldEz/YDPaYxjtwjHtnybzoINndCMOTAEVbg7mzXxZQ5Y45+9RNWWiZ +/lojH3SO/JnwHSkZ/1cy2fqhqSfif04BSDzKTRk6FNjJ97pNf46AeFHR3muy2zML2Q+QJrzRY1WI +OdmKnBNsAj9fTh+ZMURnkBV7yDI4/cp3Kx2E8SsZHkBfO431me2EQfekqnj/gRs+t43fHFdzCD5K +u6gMMEcNkhOfWO9AkMo1bxOutMfgPCLZD9g02+72fH0WrELoNrHm+HU4p/dSbwk0PkX/HSjSLr5e +fswIrC21GYhpCB3oEZ1E2gwtj+rYAeZJfyjdEiO9J+m0gJjevCCJBXyF2qekAtR+87yuvTgxT2Pa +dew+DCpjoe3lG2cyVQti2HUp98VpJ5o5PJeBp9cVhxvorm6h03hhgkfi4YNqibCvJyqGQL2NAYZ3 +EugAth9QHO5wIwZ/xnQIVw55F44KUIWLmIxQtQDBfotU8BkO0ZgHDKHTXmqGUAK6OKOW8GPCwkIK +VOw4kGquk+2JBPwBXL3aPij8o7ld3iuxbS90bp8KeygF8ClGpEp9OonjFft09F/5MfKCZ+sxxVW/ +u12wyZDShRvgE7D9yRjWqFjeo+bLYIr2d0jfWLLUxDRWuuP3s97pIa6knFsRZMO2ucOYGwVIGUOL +eIc2ot27mQym4TkaK9OMEMHkMs+W7eI4CQHx1B+jMuIyFLAYD3RHdbjQ/1X0ds2191MeQJuds/DZ +v73mIw3DECn9R/FetQtB5Sro9qtOLZ2Gw3P7mZAwUYSVEkca8k7Q1mOZuc4YtE3PJ8h066esqKC+ +wM3YXXS87TcGDMfqrWe6ACP8KdoJSnM+QbmZiYm6vXgkFhe9M+FIZKlviTVwcOr0yCeHhe9t9Epi +tCApTomEHwRZkdbT0EMgRCjY7HwvspuM5ImX+I8FMDQJhOFXrvl/UEpMvs8T6OedjxgT9ADylKOt +qsfJSQEzOmwkzxbmHQ67iQb/X/+6ltSTjPH9+lDr/k+vWYDKuMYGRnkyPxI5Fmlep8VYyB8w4M9f +R13ow3/TLHiazTFaBpzBwEq7gMLF6Uy1aRoKuU8OpQZdyHAdyPFMSIVqF4jXxNwM+bYag73QUXcx +BDY900EIdMtrx23/7Q6Sq52Eh38KJqi5Gu/owaoaxVmWC4QGWPTjLYtN6myMA/cUZM6Psn4lx4ni +DqOLEiXrsB0+2aXGrBY1CLYjQa9hlmqmgsxQ+YFN3YyXT8Xwehx8/Tq43QCOVb30Zcrbsku5hzr1 +VAWlfXangwDNxIkVbvKx3Jzren7+R4HihGhDyBl9rdonsUH65+dEWjThyjtsBs3tn9ZgJ54WRQUr +OTCgTsfHFMGdNaxYi/2uF8+6PWx9XA0oJHkATXxI1nsWyvz9szam2J2pYU9aKRPZHL0JeJjL6J+6 +G4Uq9RCZjKfmxb32jI/t9tdlLEBW2/JXaI6qU8s4kWLcrvsBYtRa8xrf0ZjFAXjmuAyY9RCuA/uQ +bgtiTXCl0mEu55Fa4ns8AxC2Z0w/X/xxMmjdvYDtReWE0G8DQofrAfyU90SggF47C9ubzGpucQ6x ++lLh5Z8BUiLS90I4irKc6ankyxOZ8TqjbvEBrUVlKQlmfWLe6GBsSVkUEhJJNcPgMrHOU07pH40m +x90yqHUloDGeVhjArd9QLOBBbXEaSn+oEQ1+Sbx3/Ij9wrXdljtNTBOC9v8rcLynTYi4TRUHm38F +oJZ3OCt0JbRI+KOZlDW3ypW7hqusH9WPQizacEI/dvnLNHBXAs7PgIPZwBvjPan3a55LiNSA4ieC +WGma9p4lZqWa+G1A5ntUPih7SaNZT0oZjYt5WLUJv8I9IzTrt7e9xyZYxw+uj+haMrc5FdteIIsE +rtzpAZCFb1pRRwYCroYHKXeTgzrEpiwC0L30lFPtWTrt3sl3fqHEqNlicAIfCIobJmKwtFW8GfgQ +JzKuzgxsvp/tu328+fbJSwcEcY7rEKgxCl0vFFDFvN86O4TqFOgXIBVw/umye8Sk3oi8L0yPEdgy +et5oAQCRiFs3wv+sFcffFwwTeJttfQlK4c3pqsQbcHwrHLcjeC3nk53Dnd4kuwK1c8UsK/rPxWIi +7S5ELN5WMtR5ZPyPtu1FPekuGVQVKaRUZcbvNYqGSdTf24k2jkBXAAgSNyJ/7b38Pr+fv4B8xY5n +gf2C9mykYEOYSq+dBIwgKV4gDhx5ZO2yQd+z+FaWlClfK9xwRG4YvuqR4ZNjuweKS82HxeHRZIFw +FrpJbaENSAqyATpx7RSj4TmpFg2dR5w/k+itUFCwfwfQTB6qZ9OhFtmwSIByL8rJPzYhuRIiA2Zm +os74aJ3ZM/3imP1cTXnluDvAEW6YNDU7D2yP+vnH8i2EfsOgpWUZ1jRe3ihdcjA75F9G6QqDK+4m +i2B2fulekuCcIIhOeq2SHiV2HpX7ByJq4kemELxccR+PfVyforGwlJTgO9SDYhJ4DFsE10tvV3jX +61tOTVwiwdqoMEMrLiDDq0ocFd1kzZ/RAhISnuln1W6wrIq1Ynw30hU4ATHJfDDqcEWc6g6DaVEo +4ldSKXbAjvK9us8j720sz/hntRDOCPYHHndxtDOaO2XsXval4NMmxaLDL57pXxXkndrZI6Za0jSy +Ks3hjuDy5eIuZRaMfQU0u8xu4a+fsq7479wJGWjmm+I5bMt4AXkS2c2ZovGUwOERXZXtWHSvQiqw +qHQCzNTxbhxJTmEQ94jfvzz9JLbMyA6vxkf92LOT/W2kx8P+Fd8aIHFKD2PGsYalPpEao8gXjTSY +W2nBoFIJdoOQ43Td/3oetHPipcLNkIdFiRrY4uEuIWbNdYFk4lM+plW8JcnzLHDrlVM6WO6eM7Zz +6zjK4xlj+LSYFqOlwjAGiEA0rb6l4c5dG5qP59kJ1f8hYM4fX5vS7adWOIQn2qORwdP3wv3BRvM8 +ftt/8bGsPxFVmeTf2sCWageoQQbge1p38LmKB9TaKWdXHzTSYEfgYsHJyElq6UGlMl8YhGYNVVC9 +RORYjwX3cNBoOY5Br/k9zh4rItWOugB4h2785CUYeeIXMOlZYxaQxDFgbGFlWcR1MbQNsP1HD5lF +SRpjaRFVq9iRdZ567UZCTn2bTMVNo+f8p6GJf2HSACnsu55xxu+uV/fLJjHOzbynqcJpKg5DjE+A +spi4Zuj/3rBRp6aiJKi5y+JgI4ma5Q1WnJnMd5awf4/vUtzXt/JGlRB9sdxMwkpYRlgtziC7zaTH +ER/3rCWE5l559B2zOMpUEsanQ4Fv2lCoKyyyIKyBuyU1hC0QSDtUltfp+31olGYpXJYDu9G54cRs +JjrwnfCrepjxemwi7mGyMhH2R2yvsEJItNkMuwlZANAQDGr1/OEWZ2K9lP6OUDgV+qXk+ZkQXB6M +0f1Z/xTtxAaIh/XtfhrsOjuieW2Heyaclwadlzc6n4w6cOl0s/mybR3dYMzXdJJ87L5nVzF8MULP +1PA5g0sAlb91rJ5AmDKSGOw+rcYvORCO/JF0fqancQYv7eGO9hFlEoaynZgbbo7sOsoPdmkkCDia +Sm0D/QWDGVdHAmHRueOoCGMjOTgHu87UCdj+h4wWxqbw5sg/Of11FQ43FKanv+GycYIQxrsWtG9n +krRF/BWB/bXqWDj9oFRMnkGSmBX+HYmSyd1XpW50Wy1SFsng88SfR50AjbkieC1DidqsvaX4S3BB +i8GIOVB7RtgSn2ltDauyYnniDpBqOkdNk/8HbfdE9yL7kw2XCnIqzZ9S+N1+8vw1iP0BqK2i4ygE +0Y3hIiQJGpbOpR6CZ9hHb/nZjXC5GqUluxjz4jNNGWJyP/kjpcEAzRBqSoTrsFgcg1sB2G0Tlyxb +mvfAMgIgENsoxPSAdz/MLR9YSmiOCYEBHWbDG6TGnQNd0OxswPNYrYQDHsAIVzyR9otw+TCHRu3V +ARM61UH8JRUQjDx+WW7h9V5SQ3nZiU5QP2d8xMSjJcDTUCsZSNcMiAORy+oR5twG9LxPjE/weYr5 +F9OK/o1dqQdGzK41DBXakPF0n7bljOcjt7s4Cp7YRURaubAMnlhlTK3Uc4sVjVHPfcLWnBA618ny +A9TlEk4BeD04e/oA2y+XXY37jVWbGAX6+6eGT1ZUcSL0XAqqGAtWLF6EP3cET9wgSE6bLP3cIUdD +XGv3B/b+JhOuUzvj+nh1zrlPx0QJNFPN/edn9W13ywnaMis+citbJ6aIbNIczvv0SIHr8ZvFnP3k +ByAt9s9CqnR6/xdN34wwkCFcwmjFC1o/369MC3UOXBlflrKEnMqeQAexOoxrL3VksZeoPC6320WO +lv81xrfiiZT7FIVjtteUsDgIR/LqLBESP20wEHOy/oUhnICmbDUvBE1fGMAi4790ejnUPELua6Dp +Zd0a+voibUUVRfU3ZAlNUFq9fm7e4dwHr8C5/iaIswNtxcuZ35qxISmjPmE9wfSDwu0Ta6qSugdy ++bY/Y4KL6kLCBuWEvCEO9wLSk0MBztBZxNXR0DarsmfoNLqd0+MTfDqTWwxvuX2m4tn1ReRNxEpA +ZJYH8IpHUhRF+BveK2411F7Qv+WcDRbCIBbjb37Ko0Cdx5MX1Id739h8eHAJvTF0FV2pCr8Z/SB1 +kfK9WDL9aWw1ImBq6gZUQcuSmZKsY2n2uYi75Ex3TzWJtG5plnDnxS7e6P5ZwjebX2wfO6G4gmGa +7QcGYF7Q0GxkRxZAmMM7dNFxcU4Uz1UmYmvWYley50AErBHuneFRVyahYLSHmZo4W5gTXwqGTIAs +jMaK7Up2DGdkCPfs3RfflVdqeU7CUWaFEhWJG5PzliFBw4KNux+9nk9jm7gtHVDmb02VOpEHUu46 +96YHi+xBIGHenlM3VtzhXmDSCpcsHmmtwfHnvBQRoLgUy36EBPPHa2l/P1/HzVY7ztWPMWjyy9q0 +eQiNryYpU3kWY7PSLdjkzwScATH05sxhgBeVQaNc97nU+eg/6h7YG9/OjDt/43AN0nZuN9jZR+tG +Xf+zoUsCzZyLPeQRrQDOTvhnMwEwXujF2e2WfA5+My/c5v5T4/ZmPik7Erhj8FvI/1+5Jxf8mZId +WtoH/DRc+EjNTwzPYaaVzcjjongw+cNL9TmBO4L4arkt4c33od6G3eBlskKm/bbkHXDYFAwb5VN1 +vSuGB1fxnK182UWzIUTYp2UkHE26AMSs+ewwBaSxfY/wOqmW3a0+qjZ7qV7voecXKWYqc5zBX5KJ +LX3EDtr9z4sqWf2VVUVpddyMBgrQ36vVpe2hWLxOTbqKJfGDceuz5l43um/PDldNhxcgZy8Jk2bm +pqabHs+hfBzhyK3WWcRf+7xG26qcDmD7BtMXN2RLGwSuZqNejDNgLmkS/j4CtbZ1g1AJ7rnj6qEd +MNsE7eImgUKDqDgM1d9sok3Qnkn0xg9OVnS6dutPBJY5TvwfURXweCOPfz17ZOGJEcmYo2OwX4Tz +JCDjg5EmKYwgBDfQ4j1/KV/RehFIuhpFvomZyMK8mCJzXkkf6kwt+TMOCrGBDVfpXKfql6M/YVbO +P3i/ydw9nyAaHtNwTl6Za75CNtB3kCkU/7w4irM0qGU2aiCKBZ8XG/NYepovzb/xTs3qX8ZAQKVY +QonjPHNUsPj0QCfVVvWSCuJCEtbPu7nrMGkRzPJxyE9ATnmhcvTkk1Up0aIT/UrgmOjlfzu5KVa+ +AxG+7kREGU3fwGfPnVpwqqNMFqt9l0icb0/NJK48zD9EVtnkg2Rw0Zn3nhezPW7sSB9vUDIP9TeP +1yM1JSC6Qt3fWnWpM78EF1NFTnJuYmpYlSkg8q+y9vTiXVIA+jPyK7qSesDhftFZXLDU+l1p2s7e +xCkTdZ2z4JFmSt1+vkbrswkZG1YmSrYQF9eu40A0p0EEokeFIIev9EUNpU/50SgvjPBxGwbZvk8L +IkEbCqR3E0KjoQr34Tm0wodv05DsvLQ+XLaM8H872B2wJbK+k9U7tT8Ep2Zw0DDsnXDR8dYHp+yJ +e25qjKeIL1QFVNHIDba95fBf1RoETy5GxJL0V+XDyWX5DS8klAZW6wriJCbh0sPnq7Kkklf45Wm5 +CO4Ouq0jcSPli1AXsF1P4zZdS3cBjTwExzcSZlBi4A7zfTRdFiGLnrZERRQFOiomv7Pz22u/NUoa +Oyl99TCmQ5rdFaStUUakD02A4XAs0Afz3eVzC6RguiDOMcviVjYlR4N6C9LNxi5eB4nUTe7GwbFp +Be8YpMDbtCDV//5PN9Bwd8mqyMZV4I9diZr/gnEGikrbbKTHbVMILZub06a4NaTKrimk44rM5dPf +m+VuYio5ZBdmkzMTIDJXzu3C1XJpQxdAYHC15g2ibRoeSCLbYA3yd9XuKuKKsfVPyrYmlWBPENiH +fxWeXlSrvWNSwBPEI/doBX/iY8zYb2qqhYcd6vul1XSzxmZMa4XJ1X4F5W3T3bjouhyya6Xsg96U +kR2Xu0EyYYJcHDXmW8we39dbvGuiZY4hjKq3olIHUaHCNK7LAirqlgUa2MmqQQKRQcrLNWvEYYKS +AU3DBE0cs3+OxFyyz0WINkGDYEVmoiAfEtjfnl6rr1LRCODNRWVG6qFbUsEPkYQ+0u3DzUlS9RbR +snH/T4/JzLbWOa9fnNPrAd0ckDAwwkW4ooRfn3tlS9YRDP7AifTu8ATU+/yeqszz3ailVolwbC2H ++oxqXYQY17R+ioS9K2C3Ilyk/3QGYeiraYsNzttSz9QcWMPNqtp83ut1rPx6BxaT066rLtL0vBvs +krH1kMrZG6S4LRmP2EYp3ZhrSSnTv4+aKItA+2bKR7n2OIg7LCyzoIfhWisgfoOCYb7DnYN3HaQ8 +Z8ey0K1aasTzINm/XYZ8nTaEkaK9OKdQjQCGCYSXKrzUVnNNa3aclRcnkF9Z0dWIvnaaGEPyTyj9 +Jm0E3ZxYDdHpRzse4HRabGmyTBqpRkB5Mpf/AeqU6jBcCBboYN1J7l+TL8MZcMC4C3dtnRVoUXrp +NRS/mRIbir+D/vASHBLU4SNkTW903NudrdVYK998KkYz7awK6YRGcWfULoLg/AUDYd1HpJCmlKuv +gOb4riGLHoNx8JzvBCiOZT3P0+6eLBmcY0Dx5w9CywkUR3+xyDQwGlNGempKiTEkfc53hnSdrjJK +8XB6wlHM9YertIijKkCbMme0FR3w7jI1Hs+L3NAMwSWyMowos+YbHCqDup+hZ6iQQa0umavrVhOK +UEEIrB6tTNg7WzOB0Mq7EwxD1e1nK6BIFAP2FFFCFTKXW7VzalAshvaS08QClpKLxaCMRHrUSuwb +hB6aNtvN9trrAiZdtzhI8+uNsHvLpMurbbSj7SzK4W4HwGix3qZ23Z69/WD3jNSmEU5I5MoAgOoZ +YAUBtrB+zmqBoQSladXAEdeuCesitzXEz2Wgi1t2QeTF+rBfBAs1Iyfqh9YDefXEUpl5/2n9nua7 +Gz/b1EfI4xPElXykquzbpqnQpuw/kVK7F0FLnYBuOvprSyTcM+mCKuk1ZwwFUpfdT/u4+hXpXQ3r +2q8VslGCWLvzRxV0Jh3bAIscagV9MWeUck2DmCV9zv2YdtdcC87eT2h0z/otXfediuY/uKAwMtsy +VaT1MJtkMgWPeKmqAWt2Y5da7sW3qbbRtc1ZhY1zEZomv7ZkFvtkcUhd6TMlgOSMH9bowbOhOE0A +qTXuGbSD1pnOq1ft++hVjRK60meeinlZFSIGtBvSWo0eL22mImtD4tuRH7sqTL1G8XM3JcP/7/cY +aJ+G0WKrzEZQ8y8bOxOnbyr/qK9LLNjIpjEgBoO6j/KEZGD3Aq/ZUlq94PlDkANwo6LzoaOVVxsX +ubiTiwbI0wrOStwq2E9m33jCGdBff94k+parlTsOOOTLcOA5yUjD1dbxKXE6lfWyU9vvU4d1G+nN +WkxzfSGKPLn8wc1DDpyNcKwYjOUV1VaQVHifII0qjzgtfLqMme3FaN/qGxPj9DkF1HPk3c9gEwgx +R7tIlZHTqFG7d+fxUB+ycr7MFO1raHna2CIU4ufIpZ+qMEWq80T7WNKir4s3ATvKmIUVIgqv1a2Y +Wnv4ed1JUWrQdOmAYtAKZ91/HujA1as8zKm37/piaj708BIQt88NvVXlNTbxVMFWG0QxjZfv67EZ +1+h6BTvWZ/D+b8EYtCTCx8JprQLH+/IkACK40EWVEovbO11VIzU59FaPkrm4OP2GvcxvU26doB+6 +L3EI6vGAuIrtnzmJIV73ERRjhYSGJMgaaLsE80jQNHlYc+GalXmUs2EAIwoPnxqIedbxAEOBrKej +QdO0UZpVn/WWbR7C0H7V8dL9F4BO6GgL5JassdhKD7OZl/L8VEP6OLXaSGLtQqVZTDTwP5I6wy5f +z+jQK0VGjEmYWtQKZPjVdVKt4KNxfRgopsh7eSvUWwnXNPfhSecGriMNF+zsvtY+li6Pqrv51Sfw +jvqt1Idx3v4jLcxAtZ50ESfGNM77C8k1RlIL0MtPYsFchgKcKZTX+yfM6UhgP94HXnmoIhTyutNc +TzfYuTkf7ROTRRU0gElvUdNvaL4MSJIT77+lyF+PJvT1BRNWiixbDxeBOyLDZsZvha8dN5oAv8iM +nzW0sDmvBBHh6YPMPgfg5Hlf7pOwSlvZ/3gjRNBS5gVIcAi2S54EBqRntQc4Zd3f7Ore+F6KYs9n +pqN1biYdjcpb/SFVW8yPYFsorhiHj4QNBJEsVShcQuwArbZ2RB3ZW8v+yCW+u6O7IBUgZpGz9Go5 +abdDeZSHptMAU1qCKpXNA/WNbPDC8/zywaU/8vPkh0nj46eLsGKrytayGauPN6eytI4lCGosIAzR +1F4mnDS0pBbJMpbevnsT4EOcXrCxMnfz3EuCdARD4rFnJ3+VKRGEAKr67MiYAz1S16T8dtjiUL4r +B/IH20z7DAHldWFthqaysNjHT38r4BxJOhcZnfNkAZfwMP/M/9rL2qcDdqNoDh6fa81NJJGLqSSV +YD4VnTYP6BiVC8hlkIfNRdPAfQvdMm0Pw6x7PpF7v6c01HAi6usnLjd/lRclKF/xClY91LYFdB0k +Xmn+zHo4KnqSFaZuKdzp+iUEU+PrKiDafr6ts97rzoeRrrSE/mzy4TawScnTrFGmE8xbEkc864de +BYibYxAnF2lbA5NSTXojDvIo8bRU1i3rSfXBKtaEFDiBCUP+kZ7ZOk7R9ZPBTenj1JnzddFWo1p9 +mYf3I2fZvsXvNJIDLjjPdGruapQi4m25r6RivjyvTb34U2oJPUkZ56+nlYcLUWYi/WqedAvnDGC6 +IhT3L1RXX8ELLfcF4HB7x5l8LMMGdE1CpGZsWWGKK75DDZ2JZS3Oj+nUmbEt2nxlqd3eM3ppCTaE +P9drHqRImF3cYX6pnPB2ELBV0OiyOyD+MePSbtiw8G0UPHYkLaq4FXQgimKygQKsg9mIGEvEBp5f +Vns3iwEUpyy2Pj7n/Li9Gpw8+C83SXfSW6DtlRx+iKYsIk17D+PpYx+P+mU3xOzwDdY1tIOB2cc3 +nM+cIkwy4e1aN0g1fpEeQGTVdFxB7yNrVPDnl1Xlyxjr/8JJ4wzbI5HUqSb4E0LWMPLX1KSdtOpt +cm/lmNuqb8hhhqiSTDIlb2wb04QucxEB/qmes7ER9Z3XHCPZrxiy6fI7REcYeR3Y1GtrWI5kWykx +JwPq6z99CsrS0TivUIZt3iSehEhENbG0bLoyMn4MdvnSGl+/l7AEyF5Yh+/kGKUjgcNqLjxRgNGB +PT9v3ycLz0EQ7jaTqnDqusGMSbWGTL/ik7DIcruo3fnlyFM1WKt5zWmlpWuWKuVVO8rLhww0bdSl +Z4TN/qPUcd1TuGUEPpt/wzmCAQmLz+tYqibJ0akm8gSUVx67VIMj2X5d+Gt+9ZcACsg/z9pP22RW +gMQODNXrlVSY8ZtvJ55lcwM0qp0baAHrUz3r8PxBGmtkxAeA67nklQ+qRp3AnWIUH0/IV2QGRFu4 +D1H1diTQyq19lR9Aend3cQ1s/P4Vya29/K6cwrE4oPmsYiO896ZYP7FzVB7snatYyCLhKI8fQfUN +xxL0c5WbJyqBr8PlWBnDErSSacBqp0DKVuOxaZ8iDX5U4E6pVoue5cfo7PG5Ncg0c6Keo1QEr9jd +lQ4sQs2SjxdoK3rLIlNGMbbWnf8mRIyj5CXD235xs3Ra37qGmgWM0sa58K4p8FJie5KM+kAy7T1/ +B3vAtQhv/XkXEs9c1CODCAKUOpFVw+KHJVK8ds3YQeFEiOkc4G5u/l/YIoFb2Mvk7/ufk5BpMsoR +l7Kk+pCyv1zGHSzTAQxOCdq622ERo9ZOOuuC66xb+yyavT09Dx+fqEDPVbCR9tAOedLGWJFwQR/O +vpXnn9zI46e/4vaAgWCZ0aokMZyN/6RoAqzIFU5Cn3euSsVGNvRLi5mzgv5MDN2OZNpbCSRWhpot +UkWYNj3ZYsJI4UxpoJ9j9B79Rxj66f2t4eolTowGtXiFGA6XVrCsxoFncwlRL1r09gdkQKA3mBD0 +9P4YkOBXeOBBgQO+HT7YVmY8gXAhM1XA7JxmDx+ZGfkOGneGHPU3HDypNSGpl8icoJTrvWEzJY4C +eBJpNRCNdK8GaH+m24Ooh8BT89tL6tCx+KFmzZ/OoF6TE9GuoUyDc7+N1ZvxPiq3NrKeTdpAlQKs +bCHrY/20biUi/lhSHKj8f+7JU266CUlDOh0+p5IGNuB1XUhIg+qChFpzuC+uO44aIaAxFkokiI3j +p+r6qsljCuhk72wQqcV5foiJUWgGcjg/bxO4MjilLg5DhhMdiCcz0Ip1P1hfOBgzb8hvE/qAdHle +VNloIV1SsV9SdF6GqedmH31Q4Ofe0ugKl8PDk11FRs0tnPWl0RzbiWBJgYoulrCYgkwSKuSgUpa+ +TlszxWe7rLZwl1iSjoP7GmSpZJDxZfH5bs41oxuFpZ+VzqcTnw91s31JHcD/J2Uxy0KrS21aq7Oh +Xu8J6iFZY8Y4sjfFjtPckjFcC4Bc0GkTKiMqQ6aoQp8IsvVKoYZgvQFgaekiNeD3hkmoJ1lzQdj/ +uDQrKlTyakypqcGnSkKeqFLUXkZ/B7yZ5i6iYicUEb2PM05nG6+udMxrnm1hWJu7BNF7Sc0EDI8V +0k4dtt6nncfB1LGYhjVaunVojAcMfiPzfBfHykenZjhJrdbRWAukWW0xamDCCI+0S9H/YDLVBYWo +PGyNf4bkRRb+hzdlnyTkqNSQKm7pVpu5j85j7aWO6IZjZq7aRGpqCAiPFESwBU4OfBai2smDwm1Z +93xnAeHTQ8ufFT+dt5s2DjUAgxzVxl3cHHj4gD4hR9KRBGWkjysDnAt6BHoQ9dUMFaMMTVhI+pGL +E09o+7J+AftXbEk08gc1j7No5Nm9fcd3ORuxaIwhjv2H2unxZPbUDH8weJhHiXdPwMtFpWC3Vkyp +jHJXUJfOpo58LPoVtHdQSy7b3D/IeBCcwnCRPRFI316b+79WUcB+QHIj7BkQU2HmBHWY+AWZGOVy +wJmuMWS04z8SWZfpkzdJMPok4xafn43zXIcsmKrTUQc2tW4kbVjB5UmDY4JsjCcWt+L+mtdrhKXC +syyZ8ACPyxkuqh5edsN0kyST2eEbZgvbCcoAAqldsoybSIlycWxntTj4yvzUItgVe2aNYwGah+bV +U9yKvq4mB0k8WXztJmcRWzQwIOOfbaa2kukm+3c13Z4ErwcFg93o1Dr2u4RaJKHpPOBghrwL7r5b +9WyFBcMvZFwViU+Yd04i0fQwrEg0+wEUmMbt5cp4lQTMwXLp0DOCE+fYQVQa4hL2JQ2hKdbpe8Aw +VgDlCRQL31J+MYvn0mXmJbzobcMSAxwD6dSc/8df6CwgDHzluqmwPMgs03cRf6s/D0JixfCXAOWS +B9oX2IcOUJafWQFov6TKokYv2N8AqFmR80Cm9cQ5Dhl4JTnNJCe0RVrJwV2Ja628mf1tOs1HxycE +tUK3uIKVRsXAUtuRHkxrlB2JtY9DeiN3le3VSxnIWrP9CtoBBa5ipeIqHnHSg9ObBahppsawbMv7 +kh1Lzp+DD8I3dOU7QjBMLJ0jpEhOFnuRaGqDQNqUjkBqcaBB0uG9YtRdpzoYux+czktlHp2UO/QM +qfLo4o8aGS9XV72Lwl1P/tUf4HTMcopBM8M34VhYpbMlgwYTM79qoxSMLbJ6gGTE3RBt8KoBOwlW ++ohZ+EZ6TqvY4LZcyEf/BroKrE8wWhl2fBPI+IMFbgGuewGM5KzRPscVayXxp0+W6jRQPtfE/Lqs +nIFRXm931BVbMUGD0OMfPayXyItA0g9Hj2q7zndIAtf46LWZORZpRbwJ77A85iXHMgfM4CkaZpvZ +BGGWCXkNIVZNNqwfMXsipDX15TAnNBS/CA6II7l5S0q+yuKgyCuwt90cWew9yqawnJnDa28B2QTs +3dUSjF5asGSbbpHD6HgaohUGJPJiiaIOvqgwYmUCz0FZuRxv5tjMFSTWnKK5NPzG9nn1f9loZnQh +pce6Pdshi1KAy944fKKOm3lUqAUnol9g07LO3D/qGq9JAyCRbjsUxarBuYaq3Bd+VCxOOLqNYjmQ +DxEbe9bRICrW1zbZRA8KE7RsqFsSJ0nFiwJLMDi1su4/NDk0BtQVdD11oNjSuwUMyRkXS0uvpPwD +AI2OrV7Zusl8kfL84ImkLm0ZXTOz9CERtibu1zb4jptONvs4rk6tiK/tuSrsMAFzwo5Wo/ObsaHh +idilw/vArPuafYiGtv+8hPqHDx6PUNLkqXMo1X84xygNE0DTCZSZUbhMTLs6BMHpXNUxS2Bpg0Qm +Tl2Wpl0lTodqrxDzpf/7e8STX3KNLVKClXqh+aWTJCufLUoAzTVbomv2sgQeaB+S8/6DRRySjMXT +f3eP+KVkdQ/Tbm+7EKnYeoJhlJhxnpHS1VKi4khH0HLW7rC0XB67i2JVX60snfYv9GNKgNpNHQpu +cBamL6ZI6NTwrDu7bMD6wi+zJMgQOe8zNvr/Zdf/sLUgIltors0we0EvS0KS05uXQydzvsXjGuzd +5mwqHqLdrb0COcwaQxGuA3wvbT0s+/VkPr5B7EeiIX9puZnggMgZiFNGMSwbhIHS+htDtNpMi7ho +PdzzkFbo3bSa7exh0px2ZrvVrKEILR6QkOhJ6UWiaksIwfFI0jx+XDPl7iHE8WxQP0zxSZrpiLvN +QH+uPIEUz7IKzGHBbuvqPNCCHfVLemNbWQb/WIYc3dKhnM2OoL95jV9zW45upWlWKz0eFAMK/FMq +Y2jTjyUuV5RoHILL0dSOWvphKIlylSzRzPayQIKVbWtPJjrX63Ud0LJBz7l0VoeQQFiM7SzuGs2E ++gZZUHPq5TqBO6z21VcramgUCsU+NxeGKNdunnN3Sr9GecrKqjUJriiL8GMlcRaOmKDQtsrYwxtW +r515g1eWZsnA14DO5vofX5hvJTvoPlvDpM2vXzVtSZD0vbXQOXnfrKzPmBZT7au6twese2DkIGVf +SH6eZsVMXA3thiKnziMn4nOkfy99d8TEC3vKovdYycUZ9rNmvFDwbb7tgEyo1YMtzEp9JFWb05Mi +T+Z28QJGnkKhc9V8pDuLf1EU8sYn7arob49Ho9pCpLX9bLJtvb3kpTc8n5vPBuBeIbb5szQFeZHC +pnT8GGuMSQDWxqJSztCfIVS4ZJHOPULp+zmnxVxajJ+1/jA5o+kip8e3Yn9zeTT4VdEcrtY3/Joq +urcpMnu2zYFgV4RuEEJJk1KsS4WxsAL/CzFxi11BEXO5xIYT0J4pKMNg45ieI3/n6XXmr2OAYOXP +V1IDHRveyjpDMcL1tAi3E6G/JpNHMqxpju9yJbV70ayv82AG9ov5ePfoD+Wzdmm4lNlPIzgnYHO6 +6uzlx5jMm7u0p5cn1bKdOl15QeauhkzaGgAZfmgBW8WoQSR7wDgeWHAdBT2qyE2BJzlgtXtnqL61 +vZ6nsABU1HKHVl5Jy6I4ssyODizzLeVJEbadE4yUgI5f56XvJmFyIs5gjk32aHj14DRv8IelYhNY +7H9EeubBNSziIlpEXP88Egt4vmsmUh9tmFzj9XWpYlEVNvEAFgB3/V4rTgm4uzPVaSPvm2c3jvkn +Le/3UBuKAzxT72iQxRyH53/Tsggd+QTIfAfb0aCYYkwSwZ6xKIvLXDjh2E4FtTpghaE4FtHUfNqV +mjkglE5ROs4ifU6cedsrvKznkYDUJxORJVSMuzCpU6OXML+RnaIzsyAYQ+kZ/NFeUGBfzqDU3jy0 +fuHrmALJ+4sxC37rMQrhJyCdA8GBIDOzFNd9aJ9QjDJr2QoMCiThW9zNGM4GlVRaA2OXvgHWHABg +qaRkoYonSGZWz6jeVyJTM1xC5rNAmKDuCpqUcmtbWS2dfq72FmRDJaj6OS+tbMNtYRg9RbqYm+H2 +hNkF6APD2FDGl840+6IqSvmhAQavYy5N868w/QR74g5Dt7n1+oFAJeGPnwOQVpBhMYFW9xFjsFaS +3AJRRC/qmEC1pmjXKzO4eHNlXrZRlgC144BjeP195RpVM7olGqYSmtyYjzp5vwJ7dGugokc7PVgm +IesQFGMQ/20VtyNOxrgPCp2F7Ar4PA5aaIMDT6UnKl2CApvk8kKkBE1eNPuEKsbJF+i4REDthvzt +XShze+eAJ8yMOTPpad+BmRDCkG7xNpAsivDP19Cf70MwfhKlNY8DaecxWzxyrQhEDdXOPcmnkksx +xqWnd+5yXBPVxcP4hZn0bDoyWR9SpMeR6B4Id5aJM+nFV36xSghH10NTSIWRsiPe92EmV3qzypCW +t+4lbnYZRQGD/ZCPO5kxZUkPpq7gq9VvaF03p79jnk27F4U8iamJPtUkODYsHB9DA3w0UG/Lpt/T +DKdzZe8OX49nva44zImcxhlKvLS4yp9zItSnQMyBhPMejOUBNjoBobNGntg9SYA5Y1DHAItzmuFH +wqs3qH7knLDqUU/us/papG5ZPAu/6NkDQQ4rWMvXXpLL50+q1ixnpsI65uqWycvIgD3LjIHoZ9hu +svXOeS12RZdf0fdDkj3YQP1NMKiVnVTiCfrFKKQFLE6DTmUqBj4SnnT//Rdzd2AtzT4vAoesxgy8 +5Db11rWxZExAK/xM9whghXb5MnrKz42VNfCjj1x8yLp9BfQaXYJDtSDWe3VOlX36L6E1esGyoxig +8NvKDmiOWvZPzfRbaURMkjXP/yknyiYKd0/sCJhqcGaEPf3Kb/UTyhOoLyTOacn2wl1lJsVxrNMX +7wtThLHGIgBZ5+3k2lZmFw8eA/xflpmC7hSUy7JWZTjQ5MQZVVJrxmAcwfBoPuYXiSOG0hfiGpdP +7nLZr96jBpmGyDwANhHhkdJRiqO22nRpf7lLxLaQeQro3f71IO7Ed2d1wvSNlVx2PERLQHxlS17O +lsU0uPR33eP4mDK03BEBiZ+2QsnZv0ygTSOZ1/Vy1WSvNpz4NsLKhrd0IwCzbfWSFVh4ZeCQpoFD +TcKQuexJhGPDem32iqA9b21EUKWY0q0jE0abfUzXILy2e0CeATA7cAnl/0DSVa2/ZHT0l2n7+slZ +S8W7fYfC/jQmaFyEdLLkQvcXtF3EhLvtbcDMx0MbfohVHQPTII7rXoBkzPxVUnTxEAHEYaCZ74XI +3/QHT830OoLHmzAFlqEu+pbn8dwLUqeZKWLWss/ZI4UHRtTVeG0SP4RtqHpmTUbyC0jbdBtYkQnI +BNHDnl/EQVbPcKIOUXWJDldF//a/RWFrVwuwx98FEoFN98efXRoAnCNdAiRYauK34KhXnktH/D9R +FNftjojvSOUHFgGjNjqMzUTrspgq6cb/qkkRFkSutibumH5q2ChzZZMn7hSd6RBIL1n2vAWxXAeO +nBqSzVM35ZfeA2it17o6vzGbRhAOGw5Co+nO3BhmrYh8a23Kr1WYWTGTwIUi6WaYsxA18bgWtngd +j4Je6Po8zWQKVfbe4bleusVRii+B6ybPJNGe3GCYecyN38e87f/RrS/3cs0+dCGSn8+FB7yQfy8G +UXSaiYBzBjce5z7wfgWWUnA/rr7ZEC9w6KpBTyJToihShpYRwDqp/lEwDQUqo8X7WUJmvIjWlSKJ +u+KvwEwBKqX2bNLoWtimKenK6r6kqH9F+nPIW4/YLHddGWBcCcd5k8VQfUkicFhlR6r+l5FigJFq +oUXmxUKmKdutKEv/1HIFfp0vBH7k4b6p/h1SpYyJwiQ+lkTI+0A8MxeAkuTcg0ZcrEhLuMpIe9bE +bIfwBhj9h34xkY1Kt6pJANDAoGanbrVsgO8cgbojdLbSSvqV+mh/y5MiIUrjWsISvfa6uQspoN6k +I9IwFJ7Tb8UcGWW9ngu0omtcG2DtSFiM0dKJnZ9mLaWdKXw+oTOVqyCJ9P+ZghsHAF3yieAyOskL +VlSpjRPGa/KvcYh1KLj0TCOVdZFWnsB5GjLMS09g21POlAladS6H8bUGoE/rvqaMdaegMuCKC+Am +5ecN910VNqyrVQaInNYjmMX1a6QE1bfoKWChNbTNDMANtYH2ZDXjf++n3WjofVh7+UooCvRaeA47 +eJL9lf58UJxZArTP/hrETf2SG7daigG4d03QnjH7fSRDwNx/oJl73OB/RSmSjz16mBrdpMxvCkxU +vRuPDGIRRNofiDqpU1PtzRsVkV/KQ48QcZ8ytd9R9dTvilVbCC4OJWlJ1/g0gOGbCQiN6RO/WTv0 +HBrsIkGsN9f82IDpH4jhuOwaX7Rx+e0ltGSzXQsjVG6bwl40t0VAuZa0uriY5pQOEeKanKgStK8v +b1u1TmzIvOsGvQN9mVg8DV2QACCK4baW/efLKfc3ocObN388OSOcvFqn5+WLsqfd42m4yaVIVuZ2 +RATORIDBO4X5miU6Os6gYw2MHt/KXvuXgMO2AV/ZGSRhJjq9+jK1L/6D0DPWlZjGYFmaNBeV71ED +PyZcC1rU/7vMU7H2xzIZeGlEd64ArbtNzXzbxrITYTPs7mLSlT5s2XuAsuAqbsepSVtmIxgrSFR3 +ncvSOVdmiHZXKVd4mgKOCEexTqvy3x9/xGr096ENlha54iWKQRnxaKyaE/mH6mBFsawgONa+uksD +WhsEUUmE2QZnv3Iq77+h70PdLGCXC2QPW8x8lP6nUxax2hIibpdxi9wBs2aJ0c9qJ4dpPX/9sU0b +TFTmxMvelOf9DHX0xWZOwcQzjfqfgVTV/cB4iKSGC1BDIuKc+/pnyBNwrD2eku1Bc7lnOog8anP6 +toKOSk83130ZELOo5ULh8knFo30cm675hYpdnSGZwB2tEfvX/R+Zwia1c/j8BkYgZG5MUQ/UuShq +kR0KGl5/BLwxarbpvfa28ZQILiPfk34t2mmMzxId8OBP+iusUZZ72R/M5UvX/HY9LqvmgAbTFIzI +zTj/p3CaUn3w1WwSRz5l7iYnjztHS66hdzYcrIYlxHJ20cwdcVOHCuHK8I7HIa8aFp9P32yHDHbP +xmS0AbruVj/HgvUYM03WYPg/TqU2bm7A7BowB9rgZpNB1B9VeTi4iA45UGuFdMw9Uv4XTriHfDe3 +2xm9q5kY3IB9VyGWsarHFhdvYm8czOEqqxWATLPpScvhMqhWq1DLOOhnD87QRF93tJySvVexJADb +xVVA9lZpmfvTo4JNCCy2yY5p4ZGCLQ2Q9GwojD3sGJTNJEmtY4EFjp7WZP6O7xTVv6PhZ5Gqbx2E +klKjuweButfkElYh8tJzlPm1fmAjWJmYU/SwTcJSldMNvwYfC+h5Sv8uc9+RoC7zwG68SPsdeetf +YdSNUBBKsjCJJZ7/1/kpmfBN/yFyJm+4CVjpBY0V5R6x2iE+s31hpUwxnThqCd4wGTPVhZXDjmLc +exKvLp3Kbns2dOJBHVXpc5H1qTwM9wuB3elh1Qg5jO64E9Om4q4Esb+GCEKEYUqiGgsYnmCCSqtb +ulifHoqlHiub1+cT6dBGmFqkC+0l9J/gfhUOGaXgIhjrbkT2A40QxUOj7b30tYxStVrfmZ5BLzIr +Kd2bku8Zt/53kiaWI0pKCpDrDEkQtWRQvjPn1v1ab1t2rqWRvpEEWJc8RdnHBTF5S4D6xcJBWehG +3usBJxqRlLGg5IMP0q2DApQiqlOQD1yXHNP9rcUCtMGEq7gdBwPgvTorUzBuHqRtnt1hLoX/tk8g +p7+4ASzqwPLgqE/qf/nzFgAttpLWJtWHrGUaJIXfV8aNrfV1FWC4FIwcCH9AMXH1JQzJQRnIBHyr +5vV+txGt9StC6LUR6klHwIvCvDK3FbzKnpr05OQYvFuR57E4rTyv39rkeL9mhbh7cwjTjjeDSYya +nSmF0obJc9fHhsbfh96kMLngDzyPPSLy+u/F9yrvYnhLlOuugoo5iCmkc1k5h8DCwirSOP6cb0nR +/XYbPoBZkHcdkXY/gHnGbeRaOEJ1L9o2clwd6lnhAUQa/3qcwW0CSVnFm0sPnUxjsQfkhLu2g11l +6HQTX87gIDn9/yMT4yL4oeE8rEZTiFpZ9bVx8U1X6yRuACPS+bk11+witqDlic2TuTRDkACVPdQP +uI3uGHfK6jRPBpaGrh7RWPrCGnQSNh2XkxkvDWaMzPNrhlzoLukakcS1Nq0uy52p2xdoJE9y+cWl +vVBe+Gub7RG8jxyJDp662NvMlmVKyDsnu8Wd+n9ygNh7Gvd3pVZPWgP2toTT1sLVwEZ/EeQ0wtJQ +XMAM3H75IbYIsP3K7cIWwsrXUZBC27QeQgKAcFsc4MMlNHFXjc9Z8wznMrWpuA4cH1fFDTwmdkJI +FPNDtfh2WnwGCkd7y60mdbJAwMMMDPzyTCTA1iEOEL0laE2bNs9eJG37cwyGAhIWdWKRdeATLZ6Z +OuBC0hl9TMjP5id8uyUAvh+k/+VeMIT+3QY+4ZfAWJguWlMgHx6x6wDmbNcKMRZ1sY1l7Nnu94GM +Rpfw3BOUwwivlGBQLF2NNwvVHQN9Z1wi84wgxjUlUDH1XAksLP14fToInN68NKZI03hlAxA88qhR +G/k8WkmBs+8XUSJZpYe18uXeVE/nD+p7lirlRkljbIEB7az/LvnnWqD//c1EWxj7NnYXOd8YJfxl +81zgJBI92xnXMbXJ5R8AYB4JWmSVLowmVjckpsuDVChU0E+/CbpvkRWtV0t6HukNSnWQOnBABlbC +NjZwhA5o8DGEJlmk56KUCoNayNZDuMKCHAtaX0qZ98vaTCgy+j8HSpvn9BXsLPTpWv+OEte7tx+o +GPi9W8Fci/AxShtDyWoegL+kK4VD0doKEYQcXByu+EHsIAbYlLe6USpXClCQtzQdLIBH30lyoO/c +xoSqWH00JPnxMHRukEbxhBp6kzM/n/2wWS98Qub4l95NfQPzUDA671/kBjgOp35Oej9Dc7G30QMG +4O64Kk81HZ+gzIJ+dub/mFAXhHt052zvIfC7dCXZw7giR9TYhGUkahR5s5EaYsDnTpM3RSHIwLKc +fdSku2MedJu/Jcka1efRvHe539xNRUhof0oQr7Inu2zKvSCYctu/utVcG1CUTSDqtrNTIBPF8rjE +CPpKDWvqdu/f/kC6py0Px7Toibk6k/HOheVLPrZyar8SDGvmbsrPCJIQFc2JiE7EROeGDprs27om +gkdGmcg3z3MHaRK88AYiLYNIZbmLgGsByAAtyfltO4gSVOTYjd+xhtAbiyapLIUj9tMt+vRJGhQS +HYy5brOWkVEaOCzSHeMtVW9rfQDM85roOt1X9By85NignH4PoBaGJ/jfbHL74i29BEYq42wDdQHv +37nb6R2xucuTiHn1EbdrhNQG1CFwIupWDwjEXcOUaQ0lZLg5ZBYCLtajkaM3gr3VxBmrK0VoK/sA +ShgMzFIcbzvLEhnwXTpBlHcdwrTWRf/iicJ5+67yG80+oaqmI/WttOm4IvmULpT4NqmR6tWIU/mA +UCL7/caLY8vdIDu43CBjpZ7HxeBRNNRpm/b2Zs8NLfhZQ2Ba1HaYjVewszFrpfKVJTh8ZncW6d9Z +fU6bPNx4i13QRs1nVUKEinK9XQUsfxeOlCP9lhR3xhxc676CmI3ZSeYJkQy9OlpAH0L0NgsHPFIm +BhM0z2RsaxfoG5pY+CLe3VAgF2vLHFiMnUEbErRSR6mDgf353u0zsk8Ye9igaj4LcjrXK/02uPu/ +mjmjT2goeoPOg1JaP4jMih8fkiP6j7Ng2HcE8E398hJ92qkdXrRqjH0YHSVe1iItiCMkwG6dQ5Bh +MXtTUHAZNDIeAWzoUbc41+7xrwbGIb7UhQpQI3mmzcrVD7fNGragJmuy+k3u2p9+9s3zpnCgvS6y +cJftkf6JuCy64H8+3yIHo99nRq6JCgk8vIs1mXBVbbaHPmZdQjoOJ4kkAZQ0ioFqrhuRPTaJTvJe +WrDC7YPj10UNEgNLRAx480Gk1rKcg4HGHz9IndAYAcpTZ6uW66nCrWXB2FN6J383Ff8teZCqRy7D +ISFWV64ltr17qgMJmYRBYE95IG70EHHmaavTSf7JSMRGNXomc3971hwQNDQR6fQ3nVLa4zZdXCMy +Ne1/QK9MC5rCuptLAeMQdGsX//OLMA1sWZNquxvTN1Z8Kr6X+2uZKW8d1WSoM7JaHf2rdSDQ33wG +Nvqc6abL7iobotTn3HHKxhTcdCTFvQrhuIIWB8RCx/Phha8k1xvZu/8ZrWOA4o0DAbAwgBCCM33m +sB4fk3L37gDU70H0JG/GeFktI9l/FNZAfsNSrpxNgDXipvCQeqMIfCSvQwUA6hCm3Wq5toI2mC+U +BzKNUFB5TS95T/SHz2yYOXNhS2sxYbCF122z4xwgQMuvwGPuCrxSHXle8ECew7ZpcYNskC/ynFRB +3wlBHiowCIgGoHAUtm3+Exb67Xu4RiKl/bvSUxYJSCYSXmZgFtdkMp9hDJ1kqZ1BA6vTNpYuTQtX +M2buTkuvD6otvqdOxLaDB5hLzyYmMhdIJ7XusoUxZlLtoqVZgczP8wxWRaqcBihuUgZjphx0bdQ4 +ETOgaIvDBpyNqIQME+y5NP5kI3RFGO8ZWqQdv29S6sS6dS43bB24y0t+nZCAs7Kijh0bZl4Di3E+ +OW2DQAasFvlnxs19f2uDFMT+YrSHdRmrevGE+Ivi8rF5vZd455++Yu5wcGqHZBdEPXzhjHqhNx0T +7Rj4Wea7Hjy2YzKUl/EFQbcsW47zoHjni6Z2r+cg6jrh0YLVvl1SrGdyUxS+S0IaVRR4nP5oKIvI +tIRZzGyMHHD1vmgFODdlWg+nNjceDzj39IpzdVr2uqJvabzfV1/3XeuGPvoS/har25OyNpN7UiLd +A3RreX4v6WrgCgPi82n8yV/fWYvqwW4pgbNGYXkWiobVGsSF7ZTAOOnRysdvwv1U0K+yLRaaYz+/ +6sXsxdmnoJd+uNZuTokH6clvD3cjJKocBeVrQDbwn/eFWuADKHCR7LGntmLDHSb8jbFn5cubIlUh +iJfXeoFwzz60A1ZKoZdSGkFa+z7jB4eL0lFy05OffWKMnQjZ5HynCweA7AtAC9kcn84XPcWb+lFy +9a2B+yPaqgInivCfqUjEdeMALELdWxNikbU1JJtwlvnzBLz9vwTaeVzhWUIpQY2n+WBcoHbYljDK +m1js+f9wrAJg3CjhDJuGuTt8Bb5udMJJQbIGVLeHrrpR2jLDy/8c8aYUYFnbF8sOOQpVuJ2xwSCp +qSwgKWg+expTgHK2oYu88LDBsn/5KbDStDPBiu91VyLrPsiibAgUJEMXz08QQD87nPoMJxjeag80 +OIz37dKnmFvSGZBbGhDZGMaIqrqZgakLEBW7cvCjvayjCH1/7Dwriiez/XCEVN9wMmZnfXPqozy0 +FjaXJbt+gyckJJyTJVJuAbs7INq4aYnIsvCroO8pDGHIJY4bX3JeMl8FFhRLVAauKbE69RElWs7Q +Fvm2A1tTBIEazVeFMOipmdewlmNroYxgKLtrAmtfiLb254agvB9jWlOVj103vIXkuUsiSSLdfQej +B5naf6x7R/nyaWRl0rON0FeyyYYIeCNVOEh42ORaih6xjp6X6n01EOL4TDtPeiYu5K1rJRRDEOBK +q6urlo62/h9IpnevoRjx0o/PTEdMWiR0e4fvVQ40CoC7ITniLKtgHIZ3OskMk/JMc4hhJmEsBrGw ++U4we/EUjE/3oPVOKd50kTeQ+e+wznX3D9Xik+OJRK5QT9cF9c8uodMFwqer+iYyWhtCr3VA/1ij +KV01uE8D8wvHUUp49/ArXy2ImTZ7RvA4AjwP0uPUY3FG680IrKBRihFr0UP/xVRrcSODpAmsX1yy +Lw8DPdDmFuNRMSNzJpX+qdn0rXQ4Ri1LP5dwlasdsZxEyOPifZfBQvclNJ8mjkCKgvd/3rTVq6Fd +zZ896N2Y0ILc0MejXPkG5swbTanapHYb4trLbzviqE22JaiwOOQOI6FlNKrYv1xA+enkBcv7GKpW +AZl+ShisXa3pfjFtND+5dmtZj+kZU+u0w/pxoIdtlmFbQKCTcrG1gEhOV7UeFm7uxVGYR5ERhq2h +NsxipdnbnSoeZvKB4ZcsIiq9NFA1mgh+9N61RWsFhHmv7kqXEFEPXPGA/LC4IOD9ZiNH7UEzDdRW +xDnibwXF9mYawYEA9Pz0J5ywJj9rTgPwo/CTH2LSMJv+87UQ7ZnOmRRB30BHf3h+VezaC731k6Un +9AgGA1M4qXB+9NBzDKvzd26JLpBL6jtebX2Fx/F4US00ggKDNpDndh2lheDzrB0juzWXVov9X1bB +NU19QnhGUS1r1mIH/sH/8/s7RvMxWHbhYIaEWjX9FYJ0qU48mwOTjrFjv32WBL59ujVFjIPP8Qwa +g8bqz+RWLsVILY0AAc0Jo74Q7PrhkrkeZR9t6WihdyZ1C5oiXgZ331V9WLSrl5hxLjU/2eJ3jsrD +6fgI22VQY+pZBWUl9xCtrzpfYBKZ3yhk+qDikzeGTbOB1fFqw0dCaSvp/ewVYzZ5JHtR58hYXn5J +ARAieonkBIsO2Mmrf2qDEeN7pmJ419IFmfU2+z2CZGjA5aI1OhOgSQCOk8nylbpUrX1uJ8pde3hf +kpD6Y6f8cfxwVvoNhwy22zuLieJD7CemMdsCRZ2akeOczsnkKucGOMgy2yXbVzviy6k4vOf79Kps +IT6nmHsXAWqZ9zfbCspbXLVvnIfPtDKar6SWGmQoiQTBj70APsecOY12xGaq99k1JzHWLWFp7uGW +yI/jL3SZEslpsqroBCOS9Gq9n7soqwNK19BhJdrVncB96GzTjucX8BFKhlrD+/Wwe3tI5scSE3j8 +0Hz8GIHdfTs8M9F38ZMbG7nK565hJE16oEN0GbplgOcYjKD4SWD4Tv2cffGthFU1YbJ0F1tkKGbe +/VjjiPC8ob7VoAL8e4Pid8lXbHg8tHawrLxBblH8gQ/yesVqPttW4+n3msKkNptH2m31/d5wgn7H +3bsV8asybfYxC0piMO1WolgbrFEakRZhet/g2szOuGqnQFDmh+3KZfSKwFDweCErsJLAdpZD+ScZ +PrpNCfzQtlNao+ch1z9+U7UGnQbk3r1do1FxK6VjTHVj3Wzrw7NVqvuZhrlptTJRxJBemWZ0AkA2 +3Tfy8iofcqW7AgHJtredDmcQErRRv8FPswNBafD2Tb1XjgowVlPyQgEXJB6VB0PKdkge+PA7H9ua +gNT40L+x/Wi8vo23hk7rnxfFaDG3EAmsRKXiD8EsP5vZzAbMPKFr1l6LXhmIZKouINhmuE4P0yQf +Ati+0rX0aPvmExbUE6U5UytSukYbKb2gH9GT0Izb3IrniX+LnZw1ebFS+wWB0LY4JCKyBgM+boun +lQ9ny0pMbeE5bdbfyRjaGdSAEMa9wav9dfF2syH9ny4Jen0voC7hfk/GwBvt7zcxkwisg2GLRqP6 +3qMwM+ETYyH2Rsl+WvUsZz1x38i149JWImdeupgqZOUTygjcZvxR+EbF/4c3MrpxAMpD86I8DAwr +79F+z8X8HRqn9XlL3+I+SBHdzbJ2ClQY2sbWeWAf9/pdlasmSNwE4J+lSM/pQGvSg4JXwQrZ0CYr +Hut5moDzp5AaN3Sjhg7KBPPrapO51dNxRdaRXcXNuvXKcfS/a5dr+h5u5dBRRUiAzCTqygmB/6lH +zBnS7b2lfN/x17uPpnRiatVoUtm5DH4RIP+TI67ii8/eAfv9I+FlnbGgxD7jNQg5O8ahqK5wYSpi +c7BQiEJl5n0x4d6Xi06QTI7tjJCDdidwjtcVq/bI8nR08sXvUkS8dQAaAYZjK+lAAY1UbT1T3kFA +qOHKao+sDE5hoF3Ts7i4N4fGGtUzcQeeO0qSDjSwDizZqDv2oCjlUUPoVXZm1za64IXjWXGJHtlF +zY+MjySIU1yl0iXknO+gMyL8SbB/dpkUkAGsk8V+z6YxqBTW4I1atL4tlTQ4eFBY1JrwZyPR0Ewr +wKaO7QRp00tnryKVt24JBl5EkRz4/F7R2E6f7ap6HDaP5I1Qo/KPHnM1o1fz6OcUjtBTvDzC2I6k +3YJfW/v2Wt2MZWf0z1cFoq8Wcv1Fa+m9syzSnjHNz+O0L/XZzit/stvlBOrtulr7J//Zi3uS2Kte +WowntGiANTU+AB36aYk1rq2S64/OBEUezpiMj/pJNQS9qISRO7CHcLDDsPbflVGKN0P1+sZ4PXsn +cZJo04h5nLqfROH0FgnaI6k1cqy+za9McvpMMX+LLNDwMjXc5VCYhN3H7awkXf6I+w/spD2wbc8x +ZvrGKiPGYIZPBmi0g0DspOS1QfsH/KStI4zWo1wGPjQoVaKT214RGh85SrTPreygdOwxkEHAZeIJ +zIX81neTKoDrGIZLSaVywx15P9GREDBmqXUbPLa53wETnZrpfCkBDvlvwhGfyssZ9GwRS5Er/Qf4 +tBgJJKyR7uT5a/RPklMS1hvmS+ykltNsQL2V4RCvXo6nK6CU/DsNuIaynAI6N6hPSyGQdqgnYtct ++fkz/BF1WXZrE/xU5lUu83/tkvaCroe6aV/5pqCuP8ZeHlVAzlk96qWiy2RAEzWyF5YkM4WfgAme +udJj0eqcvyxk5S1AOImyLyk0JohZRJ9UvoXqbNxfqhhEb5Eo+EhasSgbjZy5eJdzvCh+uzCNS2Sf +A9emUYaf+Cy0JY5ISeDcmcPrg9t0E+aAh4KZPRuccID/6hbzPfjRopiUxlTauwcYkvuxxNUUnT8y +AB/kXFenDr3V/eoGKXv1yQ1VjvsgBp5QfcWfc9zXrv6rFg9Z/E7SXDmOvPl6tJM+iukJCmt9gml3 +1vKrhAPxfqlkEJGa5R0ftd52Tbu7qruYTSKwXUUXl5eDUyhF0qYOGeqxuV2mbSPF3L1k7wow6x48 +yZRr26qF53sELAbOmSZis4mfF67VNkKt6/zTc+J8h8AyG5Xi277zw8VhyFHJzrqvuikV038S6fGB +D4KkvoLnthkct2buCFJxtD1cwzhdfY8uj+UEwla/mlCKlxsM1gXwQFrYf4prXOHqzUdz5NpH0kRo +rI3NTeRW+rI7k8f5o7hKRqBtFDy5LzXH5ojJscws/wur8tmvDQmUL1x3ea8pLl1kgRr3BY0Nt4XX +vfR8+kFvZb4IMo5bDrgJwArvsbr9sOsyNLNnkLGReUTdU/GI5xryzpmsLAsGKpcYmLWFrsvVmcAG +h3xDSZx1mJGOZbQemr+8UrbWVtiOPEWlvEJ9D4KVLoOyw3clIJ3SAeOxOSGkl6Q0nZxXWm9UwU59 +BtsYM96SByDwLGT7ZaC4UmwQGGmhJkn1Fk7Ut9oSI4NQM4L/7CR+1l+sGFN326xliL0JVLPBQ0TG +S5hlrpJae2nvHhMgIeN3RyLhegfDXG5EkdCYYbvi1O0E4c2RlgqMp43ekA4c9Ho4NqTDLlnm7Gp/ +i2EOyquCsgY2iAWPuFlTKLFP165PslVbqVRi6eHX7jVr3/wvPrsZJMci9OVtY+YF1PyP+oRrKth5 +YSUTWa1YRsUhfTFdzfAKdhEhrFlG97y17kREGObGjADfsQkESv4BMi7oKqshWJ7a+k3ImbD8y/gu +w8sO89nf7zrNBLgUrZn6bNvTeJxIsSG2SF63qzJwR0YjHXa11QVExX57yMz9hZYhsOPG94nYXT7h +ZbUIJPLIoCIzVztdTwAlHUEGyMspJTQ+OP+U4jDIrSEm4+mOyyVoFV1cxuCG/FIkVYi8Qt7jHVA/ +FPx8MhLEObzKGjq8QS5KLSLeOiLMCPkMCoOu+IUPfc98JTEXu6sySHfSyjrqqW4cRWgnxuAa7xN2 +ulF+invqlqmuOsK+SnK3+AtDvxmNGiBLl+GIrtg/wifQSR3W9d51VjweDbBS0altZP3rJ5Y7DYaa +8IsLlZ13Dnc6r7QOPXSENCOMQ0fAJ1Pwv7XB58RfUsea0e3/nQyk2oEfGC/+0IM6jgH2VAgY0ASR +09GK3p+A7rbdhndspTg+LdhkvL8QzrlPqpFlHhZjAe9I+Cbiac9MIIe8PWHtWCg6Vh+s0yeLs4UE +3azr/0dKDo1+jqNQdOl/hdeFKVGZxc1WpNhmb0z+6h2fOPQBe3bJeO2mqNcT1dttHdhiwP3MEMMA +zJgz9NJENkYiy98P7/L8YUTpKK8SwfSIjxdKuaDdjI8mBZI6COSU4GPm+CHtvkhSGwnwajg5Iw2n +dyXtGXTvqvlFGkStk1WjA2c8GvJTo3/eBF04yieTNLYo8XZgFqsg3AfZ2cdmSvYWyay/SRJ6SIJS +0ymjOHjdDbxWQpkpWW8lQv8/rQzfBrTyx+0yuikltA1H3dXw8UCQtrrDv8/bg+ofoJZAQpEP+0YK +e3FlEWfSOfYiElTtqr6jYILkGaIhClxBm7K+njSp2AyLCXVLRQrs05axodT2bAsjYlKDWKTdaSAc +A3E0slKRtabU8QLy0s1pA67WJwX5Gxz/MVtBXLxY/Lj+1jML2tvkh/JKwy2Wyc68RmdcX72TtkFt +UGnnfZUtIdNd47NK+aKWu2mnCnNRTVmfo2wv7VMg0BLyWJ0xxgvQyrl4ZRWZB9DUoHh4dAdbiKJ1 +byKHM1f/Vjwo4o5qTqLCP6ZnGBSoVlf2ho6sU1gZ7DL+UiHcvzTqyyUs0r7JtBADE+oOHct88aKd +NjG6cKO8kXcUSbmWhM9p8jbNB18LF+4eM78FfKYXN3ilTR4v9+cgf22o7/pYIaaUdSeR2uL6+ZdH +eOI2Nps7vznoI0ge/Q+njF2yLRbdRz+fmTeLygKS2hNYuBxbbizs1mt1+goa5EDxRbKy10RO/ZmM +v4jbSJesi4u/Hmp2AdbE2deSDY8upVfT+taDnkMVREj1EKDlKKmxISjmnRbF48NtDMXvtzoxbjP7 +ShRYItGA7jxctmT0uhYZ3DKPfLq7qDAG66tbtTJHMGEE9TCgq8tChMnD1SFtCtXscDif74Zi7CNd +ADmoXnIIZ5ukgIsPlk4IND91wQV6BgMupdL9s2rUVeysIbjXYp2kYWvRWNF3ZJ0HJDLmIehvqu/0 +E+WpCsQweuMp7ZWOV+KOu3xcG+kBaFk4FJjaMdik3A6iobVI8eQQefDGJslHsP23aIOc3wBS4t9u +S8qCTTEJkTaQNx2mooh/FwHY0sYoBSwSxgyBswRk4xv6wPiIpuxCdgmDFnqtQd2fE/FAmTC3Km/c +WI0I08p+I9Lz0Aaw9Gy/pU3UYnSVgDNrOU8sO3BlCI5OGRweivQpgYKe/lOyZK6VJ2fGkqR7X23Z +lNHTLw4FdS49JmKVuVLFx44hIzW+IwkL7IYpPQN+rwfC3yXdLvvOd2P2FSPaabnJwtvzYUBifEnX +12eoFlKIdMChiYLjbC9n+Ev/er+k7Yp5M1i+ztTm7OHPb12W4GpJOeKrDutgTP4+4+q3Qgd8+9Uh +8kS9Y+pySfmjLNsfy0aDgG81YAzYRheI3ihOfh6jQE066e/vZLjrqK9mVwqSM16jlHblc4zl/+pi +4J6S32sQoyrX+uim8czwCU7v08iX0n4bmwmURs7MmP4Cp6E+Dygd7x2DYHv/CvBbW9VLSpidWce7 +RnCh3/1EslIgM1a5eUDkNkryw3603BlGxz3mEKcgr2LbgeVYfvm+cxlkImQNej+uvzgkcYhCVcBM +UVtmuxVgMtzMWKrXbu2Y6903DPIZW0QsAInx+u9w8l34+/BNrcW4OOhir9vBiStszRZeO2VQXP1n +nB9nFXsASx9c8joWFJkKLr9KDRY4d/cDa0QHA2vO2/6l/MU6c6XgOOBp5JtzFS5bXJnx+w0amaBw +PDt1m0X5mYIXW911NNK3QAuyTPhwUcm7jkJ8VrbyYbFt8M6o2iYyv6+fd0mLDW5nF0EuyHaWVDLm +C1ZwO9OO2ADcI2hsycu/9uRxrw3+Nf1NqM6dPcpUjpT27v6iZXC+FfWBodf1eQz6jr1OtwFfQTK0 +R8UgWMWmgJiiHZmHSA6gzZvP5tSY3hwEagpcBVzr7j9K70x8Y1aqAvkxGgx9k/q2L1DfEH8XCjo+ +qfs5uQBFZWbYTnEqPJXblZalqbZBJbHXtaizIb0tuF/KrlN7Rjmwv6aD7xiscXei3aa4F6vw/TVD +z1G24sigsle0mPVBkL/V6KV73pCuY9KJQ9ef0gWDBj0bhxPIQsVQlg86wLu7R70RcLhTN7pBhp8i +3A1CeLNiY0Np+D8vgVQ3PRc8nzsUXvcwWkFdyk8OlgMQryhBnV7s7q46JLDk00WoSckvQyWAN10l +2oE6fDd2zlaqrBT7rsy1li9Z9H6+Mg56TxoRZziuiZg8Viv2CzS4JczqKi1e5/oU/K7U67HSV3nj +ayL0IqSTEgrfLsd+ml1RtBiw39cbWo0LeckwcMxp3U6dxM+OBCPseyh6okejSmpIignApp+roFZv +B+ANhmO5ZqeG1SHoN5bqo5qKpoMtvLXEBlWtTxdLLzTVbzMItpsNTJE5vDhvyZoZT6UOW2Gw/AgL +QVs9AX7IVGCfeWpGxNKgxlzq1i32uK+ABY56p52oQWyqevgqHTnpabqnxuqBNyPIxX4zdRbNvhV3 +cFLwEr/3ZWh29NnWwdiqq+H5ikJzCDrmYKl1iPiiF/wSTz4A+zg81V2YEb4Y2+E4uwMpX0pKf358 +rrl+LL3DDUUecRqeZdbx5GFpuJpQpaTVhrWy5th6y3BrXNxH3mAZEa1j014yiKoS8/p/OizR+Ncy +TRDjZM/goRNqOKFbuRQeNcLFagxaRE5AyZYrpya2WcDkCmi/hszk8MZKJ2ZTvHQvxVCyIxgrDG6l +MvJ8UvQ72IYJ6FBv48qS51PyMgCIq0g4hfqB1CjcxA8AFGJ8NIXEDf3xuZZJ0GkRjCk0dGy1h6w9 +E10FQhGgCr7dxIS0cDUpeLCZlvZ7pNKuPCHuN5/VmfXKc71saqa6BpGMBLIj5/n6+NJlwemDF/Hh +qExu6J4N4dnXtQBs5m/Rv+0pBesjOZsdgTNJbHVtI84UdUJgUjaUGrwYRbspEN5LhlbIYORBlobY +DXwkzk6BmbN+Wp6KNUosZlKyf6zj1La16fut9ytE5BJ0f0nq1gkuWXg8MiU9X1BkIyYiL5gomWeH +k6FGxZ9CBbkJHCfqugfQe33ZSnzEXXIwskN5Zos+t9Fx8NKPqW2GqhBvICr26jvFvqcVr1Fb706G +if+TdhqllX8h1JpiFhhCPcr1oyFYoGroy9d6sJVWBwmOt+UpY87CVOEu0qk0NOPL6INWtbyYW83o +HA1jmNywdg2vlKtqm9j++jjEluzmxufS4WRwsREkjgEVbsOq2XpWgLYBl/tQqA8gMVPspOQjp1nX +c8aYHMwiGbJIea0rRxLdWRPuNUG+pLsF3aIfw+YjlnTozOcm8R8UFCu8Q55hNn28enod0Gq7mTFM +Y5PRHhxI3lMtbUmJ8ny4LVg+bdA+sXJJELHaoX8pfiq4uPWp6uxDzn82YUDQMRntyvwB4medNhSU +pUM0hq6DJA8zwunfVXDN9bC7wU/OSeMncClSWG2aPkW0Gy5AqqDhKZAwPdSNtjGYGrifYUb6noao +QH6yyiNpVxR28VefkGonpBFlt9kHc6hSCnvkodEqx+ghptX3mXq58sesHMA3a7aX8MyGt7pdryG8 +L37aoa1zvBAqmv9FiR7rWk8rv1zg3CR+WKVEk9Dw/PznIvYOZ+5oLKLUI+3slAiiOEoS1Cblkkes +6w5/exvZVkg2itVG0Ji8vAAWdMaOe2IXR5iZg66wYcLo8cJNIQar8q58/3gHeL7IguMyO3TbKdJz +g01ZYHi2aQjc7Tt+NtXcQ9ygp3+MbDVKJUNoOJ8sqOoykrl7waP0d/3QychMgW+bnqtNvaTy2nJp +6oRauCaC8j45KWP4bK9kN+4lRFgGBn/9w6Z05HnuhfjjX7jA4um6yDcgOARWk4kdJOnfw4M7UIH7 +Wi4sl2M/NGD7oXIeqxCuFQHodhUntfS5xeUn+/Ms3wQ4WEt4BRq9AeoVx4E6ULa+/sQ4L/0vT4zu +x1xRlPClxNYLumYUeO2kEF5cyV27wK7Tkcz0LSnlEKmOICDQux98/l3t6gSjn3n4IMn1gv26K2PO +oaFTwMS3A1VXDPQUB1w2fo8Lg9CNPsHeqpbrYlQa8XOcZ/bOxCUoX4OouDoKYhemFhSuLzKxw0vD +/9XPp2VRbR78WiFquYotAr5wbgdgh25zeEncQAeakEcf5L264uw3NcTpHxHR7+mc6uVjx1vl1yIl +XMcrXHeOgshTdbAmJ6FdMv4DDQgL9FahZfEw/SGprrRDEeQeaWlSSc1ytNNonGxjSy3Bn3saDoRT +V/Hmwt/sYdiBaC5ifMw5M+9dlxel/XRbLsEzCKJ8gAZD2SLLTv3YLryfja55OK7SFD10EveLyl7j +MZ2ZxU/Jwk7iQP6ooyUTsBKQOgZPnlY0aIQ//zN53UFFQl+91GKye/o+9vwGCl3GuTZ4rmGNL2Pm +aTLaXz5KA+2FMSSxMMY+0LZbEEup72jhd9XcsMKTrN+W2uXHaHRM9pSvWFtmj0fiZxF18OvxQN7+ +hnsuVHFKfGpAkIQ3BY/1t05+Q6sqnSM+qVF5oavJAKcT6a5SWM8U8ej0Qr7Px4yr6aQvAoIt1wGO +ijebWu7+CHCv7I76XkBloYf57r0vHBIGjgexsmn5M/f5P4+qumt4CQzXQ9GLN/gLctE0sWq9khRw +Zot8zE16G3K6WeFJ69VyJizclBxc8muK51cytkA9MItpcrnfEDBIgT35OKPtKUWkll3/Do/elFRq +QSFioopXmo0XWmRIabwFFMWMgSZb0C8iyhruHzIRP4nRuHxJI7xKMQmzMdHDWVkhjuoS9u681IK4 +aetU7C9j9xAYbpvyxZeznufEXsC2JhIz4oti9wbrznO1voDWjhdwC0s3ltgcQ0FkQLWnN5f2T7Qu +BEfcw2rDL44MlRBFu09QxiIuLTbwhnCY5dwjHDAtPEmr4mwmDHMnL0quOc5IVoC95GyqGu1j3V+h +mw3KKkbUopQf14cfXSmh0q/hfSFGVMLYM3LkT8nIHwc4O9JiQrFXBxG7Ss2JTYouHQlIEYaHTHI5 +BORjXv91j/fIqIoQ6K1KNbXlLKBQ14fTXF0m6kcesFvqR76GvI87lobXhUQcAMIRPeZ42U9leKtR +OhTNrvQ0dlQbfL+3RLurFejyBKJTbZW5SvRhVfrxE3iiFKOT0Hbif+XIzuz30LY6wPIdnj/3KsQU +6W8HIMN84L70NEf9DoCRtBzBXl0nTbLA0/mf5FE7IUiwd3N6TFJ7XGaFtdZasz3wobABvxI5a2BY +3XwFnFIKUC40wd/oXHSA2DMHBkqWkliP9Ueu3lemoxl49Pwg5X7at6+Pog3vkbmPqLG3U/J2UiFi +hsxJbg2apaAvwuOg0DOVeXobY1tn1zbfRaxOqGVwr0ZhlvmhXSxErKYPhqmlMN3jQ7/y47ly/xxn +tGHqwyx35wVdJ0SQoR8ASDcbQmnIhkkI7lkxhNZqN7S495/3vg84amWrlcdTFNQlSYqedpfgvcy9 +4OQ7lVd6QY5GqvlMiL5TXNIgSKvwpjjk08r+PCT6nA/6OmX9UFh9qt+UzUNy7EFNQeAQf5sM7Imv +RR1xImtxL7FiMmm9AGi4PaIUsoaOASXlQmGh6mjf6yJj8FqS0K5j81zVAd3unxj7NCFmed5SHRnb +3yZLMJCPPfgVquJHrP870M0NMwHgO1v05i5DEPOeyQvQxNop1NPrpxElV7YHF4sKDk3EltE8aVvJ +s41mVohO8PprV9j2ZmSpHgu2MeRSwACQO8afpwtD142+GrA0ynKuFobCdVKOtZkDqoCLfWGNAjxm +RIKTbqmE/3/FNKULvKMio5rImb5/duLzolOvsCEGwjKSdIMVoT33D+Fp+SRqp4YGWzL7lLY0d+Qy +SNsucVEJ/44kL99ctmi+6CoThxx3Hth/fV0l25Pz76/z0M8ZG6phCnWzqv6TgahJGokGrt8QR0H2 +05pw4R917DLs4dsy9rZ5TZS8BGe8sD82a8gzCA2Bx+403ik4HhggqnTWy0vcXmdT+ltZp3BYRR7M +I0vOFJmDk7kwfuR1a88QFVkj9+KyoSXyugpRhcWyD50Q9qmoo08En9uF+063sVOZlvf978HgINJK +MjZv2r2yhY3FVMWNOp/0e9vnv8SwtnOc8uv4BQNIZoEmdlYJVgmLCG8VgReH/NAlcwqCdjsF7+0w ++YW1l5ghN3Nkwowkrb9KGbrm/zCkKaTrdpiQFRgLf50dLFiTXR8YD2bL6OLoIbHRyPD8ttrx7fMg +VoM7ncje8T6YSMW9u0VNpaki82c6PCrUK7Ao1XRSIchQriz/pQ+iceUK8E2TUdPsP1OYoXhFXCmx +RvpY7ECjBQXswVFG+yg3KELLrkgOBPC8wiTq2zP5i22wuoDfwe9rEofwiiWqZ1rgT2JPKxkCeCfb +f+IOmdRgdZl2zZQZeKhE6psSBKo9QLcjf4FiVXeAawowCYSI0dWVc7gTMYVu3Uk7yUE3xOIgs8cn +49WyQYUupevsX15lpI022/ofprlaGLM+eqavTPGurpk5rkT4ppeKg1qJfF3esvS00pYKC986wHng +T8Yg7bWYSgFWOWVz4kEo7AVq7Gz9SeElprZr9fyXd9Xy3LeZ9oAgzZbQ4xTBAfOwW7gubmcd7ISQ +sHhwFERRNmHOyEUqWG7JGdNmK7Fm10yjUCS4si2HX5xdjiofed2/ADZVvUSxT6w1pi1kXoFQsnGD +gN7ooJ4/ycyu6sDSwGV0yavSQI2d6TNsx1cYiCoJo+BDg5xqbHvJySWslWvgLaucZ2sE9elI8fWa +mV0v9eBLdeNprdKkeNxE2zdEGt/8Ez6Ga63V8knhjUuvXL3pf5xV0OVkL7XYPe18LN0sGk0wVkE6 +dkq5ruQMSXZEf+WNouXZiO/LZwEZ9cfLoYD6XlyhLnzt5snad9DGyaXYbK0t7qKptSQ9SiE+Pdu2 +hcE4vUPpAGTdivg++gt9LcDrsg0C16QBjJrC1EM9/MVukNSu+/fpirTH48OThDS/295dKBq8qRN7 +z5r7xWadjr2szUjJWoStKO3MeOrdjevVcHkpsoh8C3j5McrFyzdSnXk5TOPs0HJck2c6B5pOGHsf +YZf/0rWjnS9T0GuepO6Uoi61oAnZ6ri62+WPZCIKfXX2RvGhbRzDwTnGWv52KudjlGA8CIO5bn9u +40d9bdAU94ncn9QpO3p0+AKQr83LsdntCP+7I6NOnWDzRGCbShv/XTG1tlkMI4goAsEck6CDcT1n +F26JKZiWI0GJt1k8d6OMFnyiC4HNo4hXLSobSSh2dHDnpfJnK8m5eLlqHAnWGB3BG9KdsM0DMKfk +oqBhm+rUDrGlkOFCDPWTZuunDRZ2k/18IYwwrOVcRviaT8GMTJr1BMqv9IHuPYASDczVJbz3jBHc +Pob/ZcFtRGbxEzdVY8nJfQs/6zRSBEYQvAuq2HTxfqkJ5oOFnwEr7pPDeRBawqCUu783WE0jLDAT +4Sm9LgssXQJjXjRrx6dPTXg+7SJQgH9PK+gFziZIFaFImiYfQUz1qxGFwbcqXYDz9z+t/grFA3Lz +OQFE5nQwMHUXgFbSCCNtNqLAdhC5Ndtlyao0vF/nc2Roj571m88s9GGq+xRv/zj89eSgnoBJWw+U +Hf5ipZHgO05qJC64i74rWPhRqFnmLHo//fdsXGnZXA/5gIl/EvyToq5l6DFW7tA7bp1oYAbfiOiG +jO49K/1wnqlnKOk0tqisIG6rCE6PuX68cHs4qVQDCn8ac3CwzdJpRyPIdXeYvxrWH4BnD0XDSBR/ +MFKu75/ToR+OQ/qI3r1MW67FZm0G7XwNEl9827jegi8sQviII9ZpBfhSywb3S1++vZ9Lx3vKGRQs +RZc4TIO4wJ6+JZ5xiOO1U+v0YfNvM4T/1uGeLLN6N6hWm6Ekun7AXhMZiduZnI4yPDYnx/CJpYdG +ughR2lu34DIHiZHLATMRuCteYD/lqc1BtgURpjnGm94C1bc3Rna5i3/d7T3vtEZBuqEA15fPFhk7 +DZmeXnRkTbXoYlMtcMMKWAyjf6NdZx8HaNoY/G0LWEwOlCGBHNTSm0sm6plM8289bcQFxWzmYdbX +Pv7zjUXm3O2O85RyK3pY13Dfh+0dxlUC3kS/nW128ldxQPtwY6bZuywA0ZQNgjYvkyehWc0LyEpx +tJtttv67KAWSC6NsygZe9xWQ96YSVmRTKwrhoxurGftYHdsPVQyC09aD6PcqDMfykZytsKEgKhGG +UwHemY7a4ndLZCB35M/RhO6EZ9Vy4T6zvjs+klv9Gwl07HRrCkdJy68jrefxh8dRf02O7+yRNyBC +gWrCdVScUN2iy0ViPZA5IANog0iH/3qWMTYJh/qrs7Yz3o+x7v+/XUcZzR2RBlV5nHaiNPTElZ1Q +g4F2Efe/nbcfArGJOE4QfZm6tiD4N1zNPZHlnxmBaB910Deb6Y+LsWKi/Dk2qqGrbyhuGGfgd1YF +248M99Wr9DEIEDf3gHNshqLYmvBUCUvn6yRsSbgKftqid2RrQgB4JS9qHx5qJ73rcM4L1X1Mi9J5 +BZUgmOpZc1Egn87HwspoQEg5OLcGLDGPSercrSQnjfGe4b8fBaWfnevB7wpimrJ5EBJAt+B/hEMP +pNeJ908AML4ZssTeV9GAox8kJNW07ZA0sFoLihKpiKVB87y6L4Rp/59uUkTYIrX3+L5ymS6AKkAQ +wfFHH5iOxshOYpgps7mvlB0+tbvs4DKHLgg7Fpyxawa/xixC0GP/QZ7zxB4xjD707K/WP0R2C6Bd +T7cnorYsZ9yrp0C1NU1FvOYLv2TQUFDz6Kf5NM2nLSQoSVM9KdKj+AAIvukSAY8lcw1k0KLdvZCH +g0Frc6musSxkCYowGNrvMxa18UlQGZuQSRTCTiEMy201VDpgDxzcW1i7JNr3t8KZAlleVNh9Vmih +eQfMkazNAbCobkst1zlmsmckEZW/cD5ot39KkHbg37oGcMYYRPLJ+JX6/lDZH7jfS27B2FqyIhfe +YmDVi6U2f9wMgjyTbYQQ5AeYrUx4ficjYIsXuBhURI9eL00Eie5ITHaMF/0fKT6pVAwzV1UJ3TJS +C/G3QUqo3lQrGUWEoXJKnLZVkvEH5m1QDcSGwPw2TU/YL/GEbBUMeiPWLYD+IaL5EFmDgyUVDZn1 +r2KEd84OciAP3rPd0FY7dbJuz+skQIDnw2lgbC/ivpaw3KkmJg2sgbaY8nRO/A0sg4IvM75nbNWC +Ls6We84PDZAmYwLijk3tSXxVXpXsQR3bMkMa35LO7EsaE5DUGW6wBbVgeqfwK/lQJfGRWGerIpPC +ItVt+MpIJpGrTpn0A/C3z6JK7RXB1+Koj+9libZbF9zbbjzYlX7QWwLeC9KzC+liZDPyk6WVGTe+ +6M5DLWoIJSKpvHtymHZeYTqaKN8OXwCS934LNUsoIgSmx2wb++5r11wJgcV9g6r7FGLxpEY8H1+L +jv7sju7s+/G3oCOzsFaWiJ5Nla9L0MtpxhjvJVWfbtw/s0oSlwiiNSL6Ta01UT0kmdwibHphJ0AL +a6Qk6VsJcNgX2YPnN34IxOeYDGlGEXqfGpPdJnu8zgzfX+kZLOaoQf3Kw0HcBQrk9OipF9jXL88u +jYN/yrFwt3beNHzG1Ylr2f/eE173ltSDBt1PBMMDH3AMODkbxoz3z8OPnqqt5+yhdhyqZHKdqyW0 +pfg8+J9UE4WEjuZzvJZmnzMvBdjQY1beevVXRS/BLPH7+wGBOoxkoZXZ1X7i21gI/kVRkQQIDGU0 +EvR6uJraG+lex3pB/+UW7xi2Xlzw2CUhf8sX+7CEOUdsrSqfx4A8Z6leOuuFJjIVjYL2OQEqw+wq +Re7YhGONt/J1iROCc23FR8aIlBOaVGjQIGtfLN64wAUtHYXz/QYLkLi7lTyMDpx7oNvM/feU40iv +0iZg35lP7boebqywvegY2uHIJN7UB7fZJlowbLldSt3eg0dElYYwiklfTjrQTVxSCXs3WrhxWYqg +UJOuKTVG715l3Ew4C8NFXnSclho8EGt2nHuBiXIUlnXXUVpJzpQz25DDSH+BHr2mhLfO78mYGtz4 +tVWb2sTzNpYdf0yWCuG/d+dBv5ebqO9rwB94F8ZX9vASDNDlgcXPDI3W7SvG6N2hjE6f+30cyyeY +jIV6lhlrqEE7v+KjBi4Azl9TvqaJuEWRGVuMW776I618SBC+Iy7s5tVWLY9yN9wBCFugbfu+mMml +C7TsxjsPVchv3M46S9T36Os4x76tIu/g8kbM5VtpS6mv/8D8GM27j7DONb1SLf12W8LqL0I169v7 +4rurqPWBlP9SwY/57BjyF+fKsOBWwtpGBaUn2RpzigadU/s1wpNMNwTplJtKXqTpXXDZ9LdhQAJK +sL3KD/b25ju3qViniGKkj36d01ySgv0u2fRkVRRUBTVNEBgutmbJpBwth9s5jrZaiLW6X0RaXT73 +6awFN0Okd0bw3gy8sdCW95TstQozNzj5bU/Op4xWRR9dBLv10Jp8Ushq7J4IHuIoKaCgNFxKdwtW +vlHcC1iDlMao47F2/NRDf71YUkx6BXh8cawaahcw4Oic1tG8wPjGEbN0t2BKE9FtRrWHA3cAI3/7 +C1xIXc8G4wSY5gw8gK2YeEJvpkRRtveh7jdEB2rExwnunieTVTEqtc2I5u9dYHyvez2sSOZB7mPE +0IAnEQGAmJE5frs15qbwi2kVMGZpivmmzqTkz6TpwNMin4bJxVda9TIvmb0YVNF4/ugbVeEko23X +rbGJQ1bU/67PPiZVR5JBWvTA07LIAMte4AmrweuoeYHeL7OD3B6fVIB/PG6GXv/c6lknfAVYKpCw +NztrS2jWXWgsinDptXrhsOjRnSqb1k0QjVQP4xhGzMwCHLGP7WZxzDk6tsoJUgDObSizkcJ158qI +dHIZYjLWLH+h2KSJn6huq/GA6aHC8fJmsZLqY8dhXQRjMMV6tSzrV0G/LwfdyreYoq1Hd8PekvZ6 +Mn1GSfeZlbes6Q9zrJOLTPYA1tWXmg1RLOjaI3TEn5BV6XfR/N6s0VlPyEYwlSxRG+LZdca9jC/8 +PxKBI5UOTxionBJn8VB1z4vMKaigBR+nm4hLgR6gvOkdSuFwX/lQmrnJp7kBxjhFPQmhvsOrXpph +F18px6GriMvjYStlalBbibT0ffzDMR4EgXR0AAMCD2ILXaylyVShZF5jQUgjHbgYsAXa4np3G5iG +UbNeK2N2gfpOt3+ZoeQ4vMYPJWX3IGl5+yGjfOzh4i0aqVbIol/dqwFw78Af0r2i1ifcJ8tzWXHK +AiP32zQ+sAcv6OA6vITJQwqLWyriymGKy/6wG9S+0M4T33TRijTQx7BgfzvdhG6tS3nElRsUnZ86 +MsyO07GJK1uOOHjEimMOiY27E8uTYA8Ce+h/2LRkzGFsuDBfH3Tpe7IfMt87jTUnfw/+aFv4GETp +yyKtO+DV6EnE8LolNGenlREZqRiHetI5fKTJTz1haxkuqsIH3so5e7p5U/7f5H6L28OgSHM+somY +VFPWcFYhZgU7k29J71ea5YfTAwyPmVJB0JO3RIBYWD7bZJr2BQwTw2ZF4g26LsMfi9zz1QxOiDIp +r8mgsOdsvSRq2P+EiyszGXKHCYMd/SLtaAgEQ+OdHfK1oBoAi6EM81I8YGo9p8CezGXXVr6ZAA59 +IVYkfQl2dOj97a7HYf5ioWJSihNLfOUOwqGM+WkOj2NE8X/ufrO/LTeCSx29zxQgTP/wiA0iXrnT +jsTV2RViwezM1nGSzLX5hBkyW33LAfKXxQa50gQ+aaFV6DsARpNq1+TfJca5SpVV+eKexD8RbGp1 +TPoLl5J2o3gdC3/wuyR7BjRWM6CoHQssC7xBrX+OBaSMKWL/0XV3tuQIU3SuY1g1PO1/CeeYq989 +vMu339TF6E8lOogOFQcNqV3tsJ4NhiTfCR56Tgb4+dO1hOHk5tggtLEIbCXdSLg4O8VP4EHVPqv9 +dn+YkFwkse7D6yMEewRy2sClnMEiVIHE6xE1soowaxySw/lcqpmJ3ch2lC9y1rdQXXQQEzQhaiYL +OHpl1W6Pd8UaD6SziYW3jw3fhLMR7lqNjfssIwJqBCQT857mmaXOcGxpJeEdZ8lvqBGoHffSEJ0D +w198dyDYBxTKzYu5CjJ3HxP4eV3cBgZpRurdGanS5iDYffKt76PySelzJ9hLP1OQQrZE8EvSwdWO +MAgMlJBzEL74nT00ff/l2ZEbL215WOQrE1zYViT+I88kP9ULvot2xjFmpODGHNDFooO7ZMRCyydz +g1Php9n6MW7sovM81Zp6qV+HcaBN3OhNaFEVwssxatg/c4SddabtQx/Gmkg0F+HmK4yExWngWeBb +eWwhpfdPP0g83kn+iEBCbA6zEcAi2sXBoqBKoEDJBOyScTT1cuWHK/Y1gMyaEXbvvFfrD6b9XWnK +CLnWBrKOWN1x33/J5ruyPtLZmYOWN2LE9vSePo8OQAePWZEWWEgtXpmv/YQFQSJnx37OdXDikpce +N1QYfbYcA7amBXb6EEfGHqsRoZr2lPTMHutg6XWgbQitrzAOAtIWpXHB9R/vdXWq2qln5bpUaReM +zezsT9hfp25Ql22iO5A4fVc32ZiDRPxdcgk5sT2NeE9EyaJAquRB8pDr+IfPJ7u4FbWRxecBHW2n +bB/6U/1qXQm5JAI8SiBvJsw9N4IlgojOC1dDkiCIq44U5BKoYR0sHO2W51jlWcbDdFZQcLa9XhxR +TGI6vy3R47vn1c6apMGC9x+MJpc8S80Ck0UWwI3HEt0WTWVU1FLskF4Q7b1DLCkqWA54Nh8qfCF2 +RNFDLJUX58hhtSto0WKfe9kQ4dZDVNK1E7xSwlfdhdobAZZpgtkHwYo25xpl2IvhNIELtOM46jaA +iT68ZDmaZFbK3m5nytoANmjdI53OJP/IDqzBTeAzqngRo5T/8Y2IPaYwqegKgbdNCP492u6hYhk1 +SkacxN4NuYBVlLsTX1q2ofiSkwqfcjpRwCe588CQltALFrL/Psm01v1jZi6e4rnMVlaCeqVbi0bN +Z1u42mNmbVV7+IJJwjsXxCGS4LYliuQhtX3S8y9971cTDaO9Hb2Fp8krbjk0NTF4UFtZsP+8JHrR +L8/MYxhMwNezbv8q85JuYHNtYr6zdJpGFtseE9fjKzx0U5rFLpv0dczqj2zCWTcHbEMub1MCxk0J +ytLQc+c5xipQW/G1+aEy8vHWTt1Eb+WYUX6gZrdWteUaEfuljeMJHv3VmVHUgaD3fsmC2y/R85oV +Z2wMSHkmRr6uc8MeXbcpfs1XUqcly11htkqg8zpGXSVMvkIUwm/Oo2pOOcoYZE8nWIeBirq/PSr6 +9TelEeyerooFWgA1Np21hFcQR3pVQ5f5Xrfsw7Pmbt41GtdZYkrMF8f2XpRcs5RkXgvnclDSzEej +pdc7OAukGsF93soKRFKTsSkSrSGOTUKoqCQ89s9iqz+9l02Gg7BEDJTGAQBptgOroztJi/MLf3fp ++iWMSmno+raENesXgZ3hSGCnAZdxmQw0qmB7biAcD85y0RQuhPrQ3kF7jhHz7Wn/uv+iAmBMfErC +l2b0caW8iGFYd3PC0982bW2nENRjf5AJQAnuPhWGUA0xLOVyJR5LOsVgK+wDnFdwnP7CmY0lAefb +EsGyKB0/5XYmrhp4+Jbl51CINcHNZQKbi+YsqzRFS0IqvpxroU8FlAqfwVGp6Wy+fVG0YVQ225cp +tx1r+5L61jF6c3dYyGH/ldxTY5EHuWDzP1yuzXF/xexOiPJBIqX08TzVIhwYCrIxUozL4GDOzfMF +emo4CIE5EmS8wg0CEXa+xkxwpnlh11EGtC3elKS/CdLNgdC7NF+IuZvqL5LT9qNtxIdEs+dDCaRs +Gx7tFWHeZ8GUAXUim3W4pUz4DXCUHg4SHkb8nTg0KsTy/wJGoc73v+TcBol/RjIjikY64PoHcqhb +ETAT8ncn9p89VWFdL/FIw020ZhJA7EiZX61BWXn1pBJSMXR74VG6LOm1fvs0zbJ4PlBVD8Efmex3 +781Q0yAsOrdu/qgwXvV9JQBk97iw0Q7UUp0Fa6jViOBVuws9NgJnqk0wkcQ94QRiwKNM2VfPULT+ +J+1eL31gSOGH5D14HYxZDzt7DknWzAhkjXxi9g8R/KsxuyFsgFnRa7lw0Qg+GohgMJBTGyojy1V8 +phs6fDa7SbHtDdUUAww4IvrpB/CpPNn5kFVc6HVWkBYLjLD/FgEMgw1wzw3hmN5kFtAHRPLt489i +Y8Xt4+ArO2VNyyiUhgei2w6sINOFWX2xoYM130fTrZirmdOnNtGF4SLg818uKn5eOa2ZRwxqbGhQ +k1238yLsr1epulwlWuMKsGsNkZnWE0POH1wimdfEfNxsTEDAefv0pa0pm/Gllrjcwgl8bb/015tS +k59yJsaGpQVW3FloK66hOEbZhffxGpYUDxxKNk0C82v/kVZCCI0g1i+BERlDR3uPT1i5jgMDhHWa +6fxrCXRK4lgei5RH1BRtVEq/KEOHlW+Mg3sgFloD2itHI7Dr87argYJEBap2RrT0Hd6T6rYM+JBp +8j0LiddXHjIz2kOKz+zN0b6vH9YinEa32j7xGVMdW192MS6TRWYuk31pFIRcyZbTqJOmps7cIRla +YXaWNgIq6wcs6LazIHEkQSyXzTWIaoqQl8Ilc/GA9tu1R4TrKVwBh1VDGXDrjDAjXs8mhZyLCwG+ +1UJHPIy1Qw07K/+bmFfNUsFd8WglZwRzBKimbArgi42X1DjZnkSIHtcans7b2mUxhgloCqBkrA5z +wnEo5LQ+/Q8XAPkiR5Tl2BI3cEOVxkZ8nr4jPnV04zyf/Dc8X10GI7ek+B84oJSyztiPtc6NaFLb +W4oJabQk6h3ib8HQ2y89ER/nN15f10hcn81JWE/9LEsDsB11A6LMqkKCbuXiF5deg7cbWfX//5Xy +Y6a+2wNJVNtDl2MTuCPqzmuIs3ZcjLt5oRGsrkLKxUr9sB5+VDGEWpb/7vSek8JZGjzGrLKwwMMQ +7INQtWUDryLGvYYOX5jShCf3n3RbZ16J2L2GDG0YSWkD5XhA49PAnsPM/1VzX8KQ3zH0EeLuPyZE +bDmo0r78sCucukybKF3klLPRYDgF14uUMUNcpfVkTI6movH90gY6KTlzTqlu8BXSTeYfK+QuMYie +bzDu1Lq4yLA9VEusEM19JrPBSs6DvpGAC900EIamRFESWhY28a7GgxeVUKNPN4KTLQRePzraf6M6 +DdvY5UpEzaMhBoZlwnd9qOct9AF6pq2/fnYyYafTT2u0UXGx4Jqed8SXg2Zsxa+7NzBii01+o+V7 +HFOmwqkwZZ/T1VN7R0u0WDUE2YyxIRHLV2VvfhPku+KiUrLCSMxWkOKQKdsXl8ARFrnIxAgHNwa4 +RUSG//LsSS3hli5UhyJO6Rj8slU4XB3nLSi1e/waF+GyNpovRyYAk0nFSWCNKx90LT2s5Lp/Tw27 +jq1dIzIT0s/IXhHKPs4IFKcd4y1R/Bt4/32TRBs4MyHMVsEgwAWJsMGLt4dRFn0td3qRHGpy6PoJ +U/vFkkwjq6hIqZfSY09rPGiVI24qX7yeAsidVDg08xvaaTsj8DRCfiWZwJU4gUiSu3RVp4lzDhgl +67s4uEXWR3G5QcwBKS1MPKi49ezurW7qP8O3q1GwTc/RmAVcqNVykCidME6ubRNF0O8eE8Csp3wr +SQ8HKSIRtSGgkbvaVpM3ldWKX5KGsunbKWhI5SVbBaifKflyQooNfV43Ka+i/9PM0GOrsE13Fulu +J5OIYFnvIHlhfFLXD1RY1xZ4ggZYZvuh8A3L/K4eLnIRoBejROrRNZukuaZs2rUZQNkW0isVzEyG +qhd3gk/M7K6G8LTLvmZyCn2MW9hpR6ChtKxcECi/5tjGMYVNE3hgYWOjMSuO8BFpmpPeD2/y4NUc +u493oJjgKxe4QDJXrs0kfSOO/N6bav3puAr7DGLUQka07CtlI6TCe9XWbmo5tOpHSVVebP4lRtR8 +WUVQUQLvKl3k4DosZQtnO5Maxci4g8PUk1RKtWUx7xH9iO3Rn975jqLM0nZMYTzqo/08/x3liZcQ +MJAIUSzy090ro2OF+Ztcl5Vh29zmm/6yFD9YfDGPpMTnC7CPnKQyd8g3jhmcqXPyQVvYlf5YAYXD +OLx30fqi1yJfZMP2ycs3ho4qn92q2nW8+XJUZ5/3AWvq/vTy30dGNTZE/RXfZLOHcts24wnunRnl +UixGMacZOQw78/s9bmyZOqcqEk5JD3/Cn5cFf12UqjXa+mw2DaQSz4GRyUrVbpfPx5uQAqx91vIH +Fgmj2/lUcp0a/P8f8zolnDFQIHpmOxwlbmiVyKjmp+2kVwoqxDKVeISXyvWAsLILSQsbHdof5OZ1 +r+5a3N3kr2B1kFbsBLNp9NPPRRLl873Uf3ICQdnjBj3wOdSMZm04uXdCNrVjo2Y496nFpQLdzgUV +ZJ4I33JOFKmFBvzylMqFGtwmSk1srMDMWaG8/t+wZjG1+/Xvv4DlBljEqgCErdAM1KyBwJWg/job +Gou/zHz8qenCPfHL3S1am0RVCxt9UYxJaNDHXyoeqDtzyLfTWbd5vyA5kYQYJu4suInLNyI1IMho +9TBuBnDZGdb1HRDEOeSl/BR0J5A29JxKHoMfsYk3uB0ZcloBg9beQxWFg0psYyPI7qsdqIOnzlj+ +DimthZACxpEPWf+eY5X+BRQiuatwHJ/dqFyUlRul5r+WnZx9Cy45QSbbJI7kTE1hxB2uger+n20R +j6sCtzbKqC/eWkhr63tjGadKxyI7V2hon/xuYLEqZWDhE0Lz/DKkzw9kmzCwhly8N/awiWYBqwXs +PnlMgjSOpmWnERXupRCnZ7wQiIP3wJ5BmeFZOwJDfzfbS+bH+UdClv5VdErERZcPGOHt/9z4NyWO +CP9ZixabaWaozeFf/X5f2ZH0kaBEy4oc3M26zqRYVfp+yAgRQ5288znAk9XOqorLl4WCPzrVs85c +WExZ/Hr//nn2/Ed6Iaz0u5K7S6aJGdoi17WnmRSw3rquoEUfuv6OHKZTinjMPXUjI1YJEK55FVwx +fhMtynkAQ7FgZtMaZxtr+C9vXnQntmE8E4QGbAWexZEfnm+jTTjVPqxlPtU3p+LpP66JDVR83JT0 +V5WBpjHmtuQxDgsSQ0L0WU/ml+uxQyYzD0oNOG3+SkmtoG0y2AfRnXOcmL1IlRX4FerN3TqsJMXd +KNs5d8p/xBYq8hngFAT2GhaddrrCRP8JJf0FySksFJnqMMfX+oOnF6P4YOvbMhJFupdu5/4EvV41 +h4uPx2vfjK38UR6OeddQyTYMm/jnf0IKynm8+UYac2XojAxxXzwoJUsiJqdlVvbh8o+BwC8OQraN +dhFBbbQoq6fMJPL9zErufiKR/IIYlgmHZda3Kb1QgJHTbpqEo8GZ2b2ZbRmssUm36o/zN3lWpRHr +eaiy8+iwk7fsmgf3sntzbWXSgAYr9zUuAxfn9OJ/7wj4a7GT2W96mVbndj+MjMaSFLqVKbzRf6uh +3/NTK2d+BrrAykjXeoGDSnS1olyu0RQ++D9i5S8V/7a1QteiQzjMcy38gAgdyckRIkB+93GdUvwu +613w9R0Qh0w8+hwX9t6PP2T0wVgJaA5wwH8xoByXqIO+uaTkhmO+lAb9ZmLRIfla6b/gQjIIOPCv +/9l6jHK+cezRd7v0+HsCvWCyh2HNzlgNErBbznn+73ukeuHHXT08CCYrhVGEkRaPJzxTGT6y1MSq +IRkZ7otcPLgcOLzDrm+m3yBEUfDwez+Hdulhmg2OdzCHZGpAMLMSgDBYURl80PCilFKTGFfwFgYD +rK+9aeXahgn/nAtWzjOW9AakD3ItqAu4xFrVg30pk96kxL/LvWtTygsXERd0Y51qXezCy3QXMNbp +vRmbqodQCGar0AaL1amyTMMeXT785NY/tS35FOSnVzZXGPiGX2m9zRpFleuAHevIpEIAio0tqxc4 +p0rOXQOt4ExBWp6QI4ixCc5fsTj4Y0v35fgVKYphrQ/wUTZR00I0KYLnjFn3L1EN7at8YqFcqJ7a +cGR2Xm7mdUZgnCV2ZW3WvbzinGDRFnZ0YpRLbDrxkQ5SGzPiVvwQxvZc0d2ZfwfeGWfSAWO8++wt +q9geqYt4A0x9y+BNtgRzuAIO831bueUVollex3c7n6x+N5UUpgSosY9x8L2LsA7V9ojjtFW9daV/ +J4wfKG/RDn4vzTkBoYB809eZkt8E1E9vn5dix6Ed+z0QhUbL3TBgVOpVA6EqbA57GdWsTF8ccoIx +j6vCWVpt7AEh6WAiJGC+dpoecnIgaKTkOs8irqLAMfeptVLc9jbUirrNtMN7IH9/24s0ZQobT5QL +1sIrAkA7cAFvJp75800cnSVzgdJFwR6DMO02Zm3cZ1Za2D5AZcyuOW7tjuACaR5LeXhzNRSFEVBG +HmKHrCtAVlezPSA6vZDaYpT93HDEUA+9e3jYa7hSgnO1zYUVmTKDDkT3ICN1pKzoGKrdyKJkLiBz ++niRxeYseOBpyRsu+exj2x5cNs7sNX1i56SuBDeoMeTx8YlUx5w4UMHbWoWBR9TV2nwtg6qXbyuK +XYhNk2O352t1RSV2qybgAm1m0YlJJyDrY2wne/vd0jBNlWwNGpSjzrUnETt6ngTyCFGjtuhVccCm +7cWslUqekHPbeF2QFcYJ1uSU5TTfc/LTtTw8PsvOymPkCAPH/z6iQPWDokotFdbI2rArgG49fn/q +0J+7f589vrwrllgdWt/jVWVB3QEfoNdOrZmooDR0SmMsjIzDdRareLp15vrDVqqrqDO+agGzHMXH +BUEPYJSDdJUO0XH2fCdCj2PfZq+5mxP0RAbOWBWnFSyHLgfShvOB4ks8xWgG7lql5p/WhTlcS7TH +eKQI8xCvSE1EKQTF6D/PttpS2xRnu+Et1b1LNp9nKm2dSWsej8vtBfHVG/WWms0AXMWZwohIzQ1t +VPu9cH/MJoe95yXKCE5oZsPqSbUleGC10hDTunQKUq8hB4risCC7+ahMxlbb9XdSWht3lSJFjO4p +Sn99qDdTDr29OZkDKjVSPzj7H1v6Kl9yi4nYbDposdJ9Bmn9pQ412RYfpVTR+4NJeFaQSNm00ZGt +UttrpX9GwLPr6thSc8MeQTAJGruxliUIIrlDvRZBOY8CtBjldZlXIhrSiGgC09MVjdLw48HwX/wh +nrp2ZzOkILfjvW5TQBQaix0HgoowETiybvJVhrNrYLEVxmTMc2VQ4A2OUgakl4Jjkwy7kOAw/s95 +aKMucQw8l3plwMnJsJiiF0VqOkUi5g1IT2V1QYf2p+ALuiFETDKVPU/lvuvIBtDWsBEZBAnIW+MT +QuOw1hfw0dRfS40ghN5Blb7o6JM7sdyEsNPf8aj3NaIj3q64Dk1PnuecCfkoJW4lLXKAw3T2tBJW +Ii6ju+3oeQ3sOJ5BiarwQwydRXMqIiIi86zDACbCZL3hiU3EOfgtDcIToLujWxHdCfUO3d9wq0fr ++vcABwmtpGxJTGO/G4/uJEGXtLPMhAoRzIoW3tfIh7wevUKIi1lH8wIb5lW2I1wnOkOBI/DR8I56 +s2NWbLLoBIk7xUs3t2tdqW1y+ZZQOVbyQW2uK3uehDqgHkdmOqDUgNAHU1AxCLYY5U+onIp2woby +o/Y3DT18q/vU7A3pFw5B7QMdxT4ivEI4xEFoWJ74GLdcNgK2ggi1t1WXIRy/pSNzcLnfFhsYzCs/ +wptVmLG75+ZxXlAUKozw+o9YWhOiKa8BHXdaBdQtxEs+GKCsJ6xwQny3K+V7rjGOI3d2LeYpsaBL +pGHWDj41s6F5niOSv+yASg+pcq1YAyJLLGv+296Up6qMZ5JVTG0jgAizvz2DAcaHcjF208vyqtRC +cO8QUcTyCYaQGTnWK1Mk2KEloDsF/QraqrRbE/sP2WT5zZxW8tReIfLah/RUqDl8MoJqikyAsxEj +3NSnwypWr/R4voCK5GDZaADlMmiBv35FD/ySwiQTqnUHdVYvW2vMe/hgP8KtxZoA6imsYWHP6H0M +OVJfgERZT0Bi++ixare7Txe2OtJ6nRcGaWYhK0wPbU1R+84riyAZCOGiVkcMzpFfYW5m8pBIViXi +rs6CTC7aJIh7n+F5o1A7k0GHG6SswhsoEGyqHeRkXo0//85jv+wrO0rGW7dHqTB5mg7d9HYnHIyg ++BKueRz7vuEDoGxOPU73C2paedstx0ctQfyvJdpVsw9XZwO5k6+ZoZkxDOx3p0lM9CkpzoAKZL0z +i/mx1ICT2YPwPo2MoIwYgJEWLOeCoppul2TUs3zRIcJCL2Zym2DW07yUzd2DR9aIrp1uTJymoiWJ +ahS+rlpFTpAJbn19TA/SEsuUN0cdZfP8QXIux6X0riZgmT3qe3RtpkfIUuMIwz1HUkXk5zI2fcZM +DFUHMiYnqHZVrlzkPUlCpJBl5pYdrswad+6Hi3i8G/ObzS1Xw/b/NroVgRgWSL0VPxHdkmN/04rr +rnPZwhHvJ5C9O23DTXJ/FlTPpXJOTNCqFqCFgSEEncw8d5xggu4JkaHi/2BZ8vAjlOfrlezknQ1e +PvYW32DxPbVSz6SnNUTCNf3cE/NH79Age77hVMdm6XuV5Sl5RS+Xxq3FYX8nyKHRaY4VQd9rwniM +aDZUMk4UjlQGHMitpuKd54vsouWsxu61DTN0yOnFkkXZa/dlluKmwDBMf46KGGts77Fxqmn0Rz06 +27kixDj47RgOJ7802kelOFdD8S/44OasuEtC4WGnvHOpdXkWuHVEkPt5ylLLGjTI/pHR11mTOwZJ +3P/kJ2kMUEeAOxODgjpBtx9bZxZgeyXuE8CF77QZiB2K+cAGx7kOz3AH19+mRysoKLOqHBLPq988 +0ZYT7CYeNdeDaSF5l3ExWWeYGuuXBdiMKPOlUx6p5XsB+rVSdDYY0xhyOVB0llHTRQgh+I3j0ZlZ +6X4jkyHlm/4erWCTKecZzeg2VfNdSridtJk//3ymeMDBlVXA1Ep271yu2+P96EOEzyaviGnqpSUy +LnmHDCEMV2Icm4djUUrmK+/K2bBkc9N8UZB08mQlFIjSkpV7U40WEWd2vXmooted/mQeiCiT7ZLB +bA2H3g9GQOw9kAOGOJyYVTzvwwME5WKnwQNt//d7qdlOAPpdyZQiatf2RneHtcNXKs8HceZ4hGzS +TngyTIMWs8X30lEK0NINgbo6sJYVe/L0d8xCYg81+el7H0Mizff5BVMdSp+Vko73oPHeEa1DA/cM +10FR+NXMApZ8Y99G3dPhsuMChFwqGrOzEg6QSYb9hcTK+/suog0gSZBkX+qWf4n4qp2Cw+/Y1HON +z/AUUHFAfIhJS29VDa/ZwPo1dcuAZdJxLz7N10tS6NhqNmBxdGpF/rAvGDs/556w88U0rVvOU6IG +PRQL2YSr2BPeO+Dvrao2F4Vrn4a/ypgcbQYQSGStQxHOn+1LlMMG/QBiInHXVRL8jBjRRbzqCLlK +bPd8udr6OcMoHfNg1iOXoXf8eIrGwjQ4hj+u/4fAk8ATfDZepbOEZ3ak86f9Jp3p7f0FfekSJYZR +9C9WffRDkyjGDOOUx18DlSPh7Gi6KMJxcrzuouwhv42EqWpBBCY8DgVrlRU512K6gvIaxPwjSZX4 +qbVoevU3Yoa5LXfqYHG0kbYqC7yRp05f27r3gchXSq4WxLaVS/q/u7BIBpWlcz07eYYP/khNPAJk +Edw+EvqT1V1c5BAzE/8h06Fdkk1+E2VXOUYorUDdCZBe+I8PFGh1w78s88Qi1SjoeCXJjR825nM4 +5AF5Ocu1vrDcuWnubEE/awTPLh7sj8OiLMhuoYIuyN8JvtXXbbOUBKicvA4o26zUT04NRYMDzG/z +NxL7YOPx3eZ9KkMVNAHVOiqzjfKVEYfNiKQqLK2X/HineWddY0TWlnKqOIO/C3owoHp7kLatG0Js +kPqDCmnDGE6ugBT9/gEU1vUv75I4PmffdES/cCyJD+uIf3FrVpNOH8coaaJNn6lfUmqmeLnZF8X/ +TMC8jKlMre0f5k7B3kTjqTFSADrEdwL7Kf0Ld5JoxrUfOsgG0iyb8bCMjW32IRqxTzziJWNFL1Ja +IS5AivaeeMf1E9XEwUSLY9PPkEX7G2PrdUgeG8Rm99htwXw/L676bH02gmwmRQD8CkcrWlk0ER6N +sAn6x283CJNc+FT9Mv/r/1yW/rZFuseOH096EfjrZ8ppi/MQFW8P2hXi5TXzPKp7BSeScBBO9h2G ++hn0/fRYYziQ0iZ8DwvW0Ts9XJ07ORv17tImiQHjzJuUcXdXtdEVOoxG7jyLpWQ+O3nyYeCsALw3 +Lo7haAmTGGM3j+/4GKvDtqD7RCibTXmiS1N4EQbCYcTWPbijrtYBYA/xifRHHDFEBPwT/AQrJcr2 +4jRQLUCktBzvoyyqxuDkQUb6yhUX75LDV6Pln2JN6qc99ZltrzvsLV42+Co/OkOXJYOI+m7qknKE +c0WBzFiPhtFqtDp/MNSHMr/9c+ChT2jsSMIX8tMb0JcCPc9qmr0Qae3GPURSdKsUv4He2hM2IikH +/0cQk5NvMrqz1Z1oA5RxIA7jvorgsfJi8miDWf/N5JMbjiXnF/yFGjzNqXWAaXIovegWJYTMitUh +2gK8N6h4vRBrxSALQ+ewP3L378UPsm5zIp53elMyZtuKBVDm31AujFuxiEoVIYnbO7KhVuvstvLY +g8GZzCa9yrbQxkD+T+vdRXOdqOPHHu+JKi7/CDq5PuHrnhswXEl7peHKj2CFnuw07L4yIprOhmr5 +SxExPKuu+lMPhxPDoOq7UPgqU7iCXQWKMFaDc7WeC+ZS8eKDVLkDkf6j1UAzhNhnB6ZYzupthEAZ +x01aLxc0coCShCsbuRyDo5+vzE5gEyeNjBubsMdTs1HbehLjK5vCoRl7jZJ+SlHGyLxqrq7UBCgO +ATcwljnBy0aYXkrvtYEWM0TYbwuqvAgj35nl2eMzMKeXNdV1BC0sn/hnaB2QKpIBcp6O9CGiz9Sm +f7kxwenj9U/6JiMH2jkFF2VPKIU84CNHJjtZgSL9gga7ChOkHECcFLlShpdEi14Pm0ccNCKyhC9Z +t1dOOQoEVSzJvcNSDqXZK4oWPMUBoV0iCgqM98Ge+wxE5ylOCWMO5CpTphj+Y4qtsUYqQKUMzqbQ +uaqtTw4WixU+o8iioozkOAydsw6HSK6yS30P7/AY5lzSSo1205SFzbBXHBGSdK0CxvXeupCJXQUH +Gv9PlQuH66Lr6TVSy3ZnebWtlQdzfqzeyNEcphGch6Xrsm6noK3prMaOJZj1DO7B8o0LgV4fxAiV +0RpA1tzVK0qteTcq1U/XG2IRr5D9k+iogP60J9JcCg2Pdqxw2V0drHl5bZ/01m7UVItl7u/n1LAN +UYdcYeUQkSqJKFN0lVbEzHyWTCtNhSKug8pQdiHC0fBrcvmz3kx10z/iEGkuYRoyCmwoy8s9PTPv +lE9wth+4CVBeDeq7lyv2HDawdczINqA8MWegieQSm66toT7nhXpYpAU1IIaZI3Ac5dYyH4QsODiU +tia24nqpILiynvamYGFALVOU5ZsuAeMxtggT1Vk78BL69kCHrQl85fgeEvuHi+BfAlAJXGoMsBsw +qKeI2EKDaTBpUdNW1P7WRe00GTZMNw6JNd2cbqZNVLKSRaaea+kRew7+2ROy+a+JSY5B/AMggoHt +yphAGDW7ZnJ6nwtpLBAD5wX6T2xuDMhhdXxmMrVaF9RtK1rzvpmZC6BTRiVUMCxk65OOwQPrAVMS +/EmX6Igu1Uazxd1PpLF5mH5K0LdVDca37Chd+O0Z/LeloWH/jDeCDXNs6BoOu+2sXD85+xLLSj1+ +age8NASw0w3L7ZfzOfZ3nuH+E9KixCROLoGNLnSersUujQpvX6iam6gvhHVt+7rhPjDzIcNILkH6 +9SUZuigaKlk/X85f3+mhrJ5JRjy8c7VJzsZzKsZOuaXmW9K+GicL9dy8BF68D9e2qppSuxpV49c7 +yLadQr9PrJ4C+R6vwQ971WMWwwG9yCOv5e6NfnDfYRGlNOIiMt3ofxmni52qycd2pDgxpHwC3K/6 +DHaW5efRCGAid71zC37JsSy029t8gzd5ZeD7oN/hf1FQwiJ6/IQFa5/o81itLDcY6lreGWwh2M/j +Tw0WouTRFuJAZyuuUWX2XRsPDhx1Q+mv17yaxb1dsa1McBBgtQxgVmI3FT0ixfw08trl83zY49l/ +nNwuU0YZQF9h3BheZJwIsbo7rzvRWJUfNcXzF3w7c8saVLt7obsi5LsaT8ewtn3a9kWR29+uNSfz +MkueRtb/sXfp3aLdxpr/Wj+5r7L4QWbOHC2g5HdabmlZVkPtMcVfUyO+F/fD4HEOywcISPMT0hYd +WwBsr+EFMc5S+TYd+xKDojCRuWfT3UE+gl7+NnmmwLNkQiniSDmm0A48dpnDUBa86ARzGZ4EpUvy +AF663gAXzFQIs6PQPOEF/3yR5VJlcmxzeiGQBGRbhQUjMQZ8reXGh1uwqC1EXKed2umF6QD51c7u +BxrCEc4eWSpfNhu2G4MgkckzAJC4ZHbMrmbVs6Uo0Qtb2un2l/OEtXAQfG6jmZxXYGp7IH+qEuNA +/XiNcQJ1nQtv/dS6eTUMr+hIDqaImR8/XkuZhI+fNezo3iV83mZ5QXjI6wIbMvN2H9C64DPKR6WC +LeQCOrm9MkuxkCE6BoszozYJ25q7h/jVW1DGWBakIa76ojZAceCJewTJCrFjFqk9H2IvQGCQ4qAg +SU6kul5LEGc6YBHrbjde9yJv3LClczcAVDih5InvigqGjE9Y44chBvtWG9yd1nZPZFKOQE8OfYPm +RpDCA0cYH2oC9gEknDPZMuzP+Qcv4V2Mz/6uJUCqslLt1ynWf+CeCUrRurFNwf7lG2t7Cl5LTbyc +1ftcSSmoyTH9HbYKMr1ApozOIsnSKCxItxss9lzaE4CytA1Dhz/wyRgML7k5ddNFEMKQh2TqsTqy +5CKgVDFxTbNeXUFs7vEFp1NiUOvY7XU1CXkIWcsNTGSDOvDxtFv2+CV/vlLbnEKhsBmgL/CeuZoh +XodTRvczHi2dnydWIHZpNkER4dWy0ST42jQu1tsQAPhewaCjao1ZA7ZfbWnH3Uj4sNIo6cmjlM6f +lS6Xd/tdc2BN08PY8XecYkkKSL/Rqkr1ydh8FHU1pt9hHjKx0giDEj/2/oxvszoccSOLaSLIgA1M ++X1QJ9fOoAjetj9bGCjx2e+gKB3PcXeoJfA8SQ/MDknPBiWIS2UcojU9Nye3P8c+i5whu0IypvVW +PuAM33Js27Ek63Y4EheuTG0WpkQ/c+IJTOBZbHKewAT0Ptth29CJK88uJrEbQ6b/OXQPvVIj14d5 +OO+faDiUE/eiGJLmjnnxkYANzfMJoX+4qz1RkiQR8Rrgnt55vqP0XKkNLVIVGdWuT8FH4I8S6FRA +olEcKUIVH1bbCdJgduEN5KjLxrsCMDZ57KWS40etrP+xgfAYkGB2CbOr/LZx+0fQbfEDmOj6HsQe +wy2qCnlJT5YlSW5sz+WhKESdF/n9ghu8QCwGldTT1HYSassWGCQR/KCzpIpjMDipPL3xRHjk97ue +YVdmPCLX2MIECFipBTxQW7mCDFZ4avBDGOaQBAITwgUvrROFM58XIFVrIaTLDNV+JSOU+6LiEND7 +v69ZJMf5GhjEvOnb6pBpAlAc43hRrdqYLqhWPu++/JxzxgWOej4oktiTbBBE60qbihLFvuVXXbhO +yqY7nejh8qWhLlc9HjnSBBnUpUw1Pub9z+bMLDXmzhT7jeavOY4Ht/AnQPbeZNsARRHiXSs6cbAc +dk3lraGLQlFpzzdWld5r+gv2/kv3+1xC86l7fF2fGwx04zmDQrQofh2YhV7QFoZIPLfIShw3hIvS +W3UfArBs3udcThFqQod1T7pScGw3/DzaFLIk2oCkgHf0X1qVEoeMxp4SpwU6rSM4ZOayPbl3K4DP +KMpnJGGS+5CYircRr2yGqKcPWRWh6+3bVoYI8TY7KVB2APzIDw6SkJJflSvBFPKEEesYmHKxUXA6 +/+HFOZiQiBiX67AMngWIJ6byIEUfaa0BclaOitfHU7K+g1LE/ltByNy4CHh9DVGBWPncRwefLC8p +NNeQDdElrFtq68XADshuugyea3LojX/NY04+Gc5JbI15ZpkGWMZM2c5wtrYOgPrIdaCFQErGqHBO +z5pnIK3N7K/r/3bJa8puTr8frF7nytQkbFhSx0g27DBk1XE4nEh7Es74yos1Vv8huyjr3uR/+17x +2zBl5sXwzpgCcVuFx1jKBkWum0kOXwMzKy5g1MszRt+dkXJgj2XY/4UgGp9LFJamdLZ4MRq+gSga +dgfVGc2jy0r0JUhspA2mRbGBJ4hCoG+CDo25d40qsYcQcudw7HtfUCtLaEC7MMpX1GgK7akPlSY/ +AtW38xPtQ5K0sALef9orDcpzEpt2lvqT5NPi3mXPsg06dpci7yKLxtqGinCCdwFAYH6S/HuFz+0x +csiMDKAl0H1K5bnR41bQFjIbRTsx0paz8P0Ah2/Ar6NuS0j+ISHzkFDPtFxkD+f0M/T1o+/dZJ+2 +BBwS33f1MwJ6CqH6aKcM8Zm+fS0ukv+icitKSjgjZgHlSVF6LDsGjmNM+UMLQj4tNZv3Amx+LkQz +93TVJPYPqZOfKbtL2cgtBMZ+aHzXPiKCXT9Q1Ek4nHdSFjtl1fLImFrq4BYU2T+SOmSQ35Qw9Ocx +sAEiJrk6fzXtAjoNLbGOVKEj7jVbEoTadinCWk+3TBYRigKzaiqltPjAGi8GoQNXoFDUB2GWbae3 +Lqa+QN5HRiSzajbhAt/TdghH7z7tOH1fQ91uc72TsG1Up3VBKN4ZMJIu8M5LZj5LgQn17LojCYI3 +lLbH9he9s9Ro97nIlA3lamPzCXSAOezFo2pGvIDhbc18Ikhc40fKpCA9xpuUw+x5YaLnz2w/zLNm +F9ms0riHMyWR7r0g3DCuYnjlj2suHShEPcGNrHO4U9J4r1DeQshBrsvwDKbKG/Y/fn/iNRrh9mv2 +yAUKC/F60GRID7ftgog4jNmgSH1nnjsQILukoSBiZudjkG24exp+f5n9f7/o4gECnnZKNfmtxuGc +vq5adPUZ6q/8dBKdQkU6RQPYUrs+XxyeY6wenU8fZzJLk+2+63n/gz6A+VdWSOh6Imr7l/GomDKp +hEUwj8PFIv5WLO69Xah1JL4BSrSV4wipbBmkZ/KJ0IU/PqjF3ZTnPWhQ7lw18NNpB/bJb8CoD50O +711vpdBr09u0MuT35ATfb7bavllHU/apq7sW/3Ob7Mf1E+sd5bBlrSjvfp0YH80lppRYw1ZX1Qdj +ogVjX5xmwHd0rbKNZMJ5shsihvXWZUGPycb3n8Yjl0K+efhqre+/XTrBdowDzLlWGf37rrzGcxcc +IpP3Yi8vr5ZE3I8lqCubh9Oy/H+zKozV6ngDgSM7ryTSQnAwy9UQwU4k+jhq627p/lIDzC3ggIR5 +bgJlMP1ep2mPuakGFE3tdJiRe97V4rsFjcBQDE5tstyovoThkYbo1/cIf2QUeF3wUyc2IFHOqntt +yltJQieXyK4eSzWVFzuiDFCkY3pPYEOmSQRgAqlYIbGt/chdgB0kNOGvv8Pazrcb3czhAc6ztURw +xxzS5wn4BTm/ggPke7b+6A9E2FkOXOXSqhwXL3SAM2s/jp9EvN9wGTcfShCol18P8BUctnEk9qKI +62flDka6v/x9OmVwcouIwP3fp2yw648PcN6WleskbXFknj0z/2jIQRoncfb1vM5N0Txqt5ldAjoA +xSWsx1q7dG3ys/Vw7pTdcV2NqUnDe3CQjdrH33eWF5TgVv9K9GtIalSPS+YlXP+zEKPHo0uGrc/f +7wsSCpa/LgmTdr8rLR1w6rFaclG5/mPq0oZeov3QMWaxi6jTPh5cHhe68ADyNb7cthuj3aMZCGub +fNExJhujoC0JvdOEXQ5eNPyHjrMxJbln02VtRaqnPBCXx+TGowQkCaypUVFFHOHlsQd+Ow5oWpHl +/HK2dEgjeHMh1Z6p/LbViUj2hkNmrAu3slO1i1kV1kvBlqyW8UMWObxpFPUaWFXJ8fwY3UVqOZhn +xbiOEjNWONNnF9kJp2aMU4xkx5bLoA5CJPr/k+MW0zIuK6uh/6zx+ULgfcGFQslt3texYOGoLvbc +uD0QDmzxNRe2f+MtCqJOHfKPgk+gm3R01VEgDwqCElrKL6HT+bkebcshnIIrc6FRslgu0R0fZHAC +qqLtp6M0Rp6u2OwI4euRM+WQerH/cG09US9qeEyjFRnrUgil4n93QIinAaX4HLZX07dXSHApisgC +HwwHaVnHoLd4vp3+M8CzgfQdr8ngMmHgywyZs7dp8PUrHf7RbhBbuiuZvZU6O2a0yM9s9Qk5Pa2I +j9xK5idu5n07Zv3vJ17t+/NNHs0bsTxxXXy6D6AOLOfagnNgL0H+yKzn9lsmwDdGO1OHZNiS8MVg +awCFO3a2vwKRk0POuQIvEQhNwuQN0p3676GnJqnxdC4ga4qMJN3AXGlUf/OgY7+tifkONQaw6KRr +76hfhyHK4UC/iQZOLh6qOtjxnn3nAszvgCaIlgvbktr8rbjRuExo0c3D8l73AEm438WZjJfHDAVV +BYoOiUcmVr8NUtf3cS7UdxmwlFRgmvxVgi9Lxc6I8xdDR5pfMKlepsZiwv5/yX1W/0SPu6lG/OfK +q8ZN3QDHaBZKcSm9uTAUeON3zUuJAAZnUcTI/M9dpRzybnorQ+9RS6mQPH3XT35HE+WJlVrcrXRA +mvTrFr9MfU3BSnxxfOcwyImd9aLvCj4dYEDi+ukXh5NpGgHk0vnegygf7P5PPMe3nTqBMiIFO4Ex +rqkEyLjYDZubdCM92QcDMmlSau6uMkLfIFG3bIS4xCdPCVIzVHVjge8bDhF1cZFHtH1PIV8LETNJ ++cVOEGOOEIwUmVsRLwQMgJGbbNYe4qE5TKuJ4vE4/1pQDvB9+N3329B+C7BzbX4nAp7NDUBzXUqT +qGGA6chYVYZ3MBaW5nQwBdhgUC4DWGoequmVTTQUfHAvU3VXvdFfkthqGsBzqq61xdPVQAWmzbcy +1HuVOs6Qd/NbRxK575ClPdIvov09Jh15aFuTSSKK1tLwB5GFk/8hnbk+qt01YW971FOEUMIWaLVf +NFEID/qGcpZY/78Won2BlVlEe90uuFM26AUxnqEgrNRu6NOcAKoksrWNIx4i7868qZsM557fl0uU +043MW0LZ31af4223xf9GuKR+xUXZ6RRYIOkeoyeKc5Ws051CFGTLXGbYTkj9TWzYbS1WvdJw8If1 +FrNdcSejLdnRHglwBQoyEcAsCFrys92lXGYC+Wn0D+yzF7C0RBoPHfZR2nJ4Gg7ilY62zUOd9Vam +KrGSNVMLx+dvtHqdl3TYQhop7rHKf9XsSROcNSqLYOkZHfV6LYn78hxGI05jNBA+6LUES3mcie08 +W9lclkFzk2O8A/Gq2bRNRxuJi2tEq/BdVLAisFr8LHyyT7q4HKuaqy9SjclVYftWPdU/R21Yv0en +Ex+13KXHK2vrgwEkhQZi4fHRGhb88j2VZhLW3C8jbddkyUk8O2XAweNqoYFMKsZid8vwDakzdEbL +I7GWfPFhvYEtt02rg3Zq8e9tS6LrvvgWV7U+6g7r2bx9c3HXowsp75axxYWqp5nEd5AIXuvPGWPg +xmPoYiBFGBwOGA2P5AxCKFYJLftA7dE6jQ03LzxRDn6sd0KtSENf1TRH9WXYnnkqPUobto13wFjp +WtboKhuBQm2lxCC4GmroZCJmVGxOv2+IbjOa+HX9QvbQsyr2G7S8cx6kLHtHAtX8UinBj6P4dfwE +GMBKXMJLVl0r3uo53//nr6cmjmvTRoZjtJiMroZbVxab/G9ORDfmIBBMfkxSHUq6ja2mQa2yfZ8J +IWoJ1XiNl+nXAXRf+W2dSg/42GO2t7yn7JJya9j7ZHL4AFKG0Qm+Mkm/vhwK/pUIjx7HxE2ue/WJ +ZaIvfXVnBclfHHzfCB7ieIdZZq2YI0sqCiDov3b+Yvg+GlthdsbbZbjo1IuuAYvI9qb5j6VA+OLC +Bj6yV8UUYbx01j7hW37dXWw+TGRBqg1/Fxa7KAMhUiG85UlNVJAO6hpNh9J0pVjNLDmWc6K+1HU/ +aB/JHJZl/XJjSSKkNpn+YdyL7inSDzZoubqJs4OGC89/jObHnTL75yExFzH59o9WGBZiU+qAZvev +5bSs/j8JSR6vwMqnHQzvdJt25UdX7GBE+FrzMFBnDdf8E3TFFteh+V66lBJk8NSGSSPOlmVttMcK +l6+AxZiYy407XsHCjkSJfGPa1vhw6A7GLlaWxm45nYfJw2cJnRlI2D081/9j/ZuquG8oP2YoAMIq +oqMifwpo1bZBm+5WpMbTpM9u8o9pnavjfBgRdxTDfG07fTcaGwCw2rl5z2HSPZdMYvxCb0RCAJVY +SfXIrk/ykXAELaKdrM9tmm517kdZe2Obu48YX36BN02F8wJVnQ884B8BlUvDH0nsVG3qfubIhsNc +6LaiEO+RHgZNjzeTg1F6asP2BPzyRJJA7tz3yiWZfLPTNdfcaBIGHX0y9lgeWx/TRIzVHW5trV7W +6LeyiFM8UJMAgIfL2aMcx+jUsYIKi5nEqx7wJs/72BnWlN9kmWxjNKYaCpJicN9t7/DJ/TRBISTd +Z8Sndt62/FwzdDpSr+O205Dk0os7O0yPyKXhLVV8umDO6udWy+Blhcy2BvTn4/BmlWets+NNEdHZ +Lu0bxZntQUam4KtxqMlvOUKsKQKnkHLZT7JZBRFZ3jYUwqcidtDGCaslz0wh1CjkphMBFyTSoVr7 +o3W0o5qJDGsLI2GV2YGgpMrIwNtO7IPbmVGYtL9uHy7sYQI30NunpWD+RPwi6VkA0GPhlpMxvjOK +1uUoODKgtO4el1Ulapp10sYPnN15NBcbspYvK8IFxPYIN09oVhKLyQfNed8O3W0U5/+51O4nwXHq +1UuGzXXdiKkFoyzmutqBb6mSUPXAk1SBEkpycIXBZuFIviAM/dzFrGI1Tj/h405/7FFTAK7GCcwn +uf2qjYbNZ/1JwfVKdTANrTlFWlUaT57Qj5XldtvoWfDyFpFN45/hH35lChdvrEHJaUqIlVD74vIC +1wJlHX6vMoA9WwBlqxksrKDEhQ3UYnojkjw3iY1zXj/vwKldE2dSN5r8hFm7qlG9U9EbnHvdQVzk +qbJyyw54bI7iQmpq0GUQhwRyBbB5jONXjB3nqtCx/pvufdFEu6i3OitkVVPX/BA4VZwECRd1XKeJ +Ke+CqbGCwggGlxMRKWJD9KSy+VA83CnKyFiWhTeHUBkysEmLa88HbSFme4i2FC8D9SmWtZT/xZSO +UJ1zbmCqxIBO3hM4aRmUMtnvPTOsfINAzrujKUZQAcBFFqn2TJZDwZ5DIRc6zynTZZNR0SzQqOlc +PZMj6VBz0r4yoXX4EhAYqzEpz77TOxin4V8brwNMKh5oAqB3nZnqTCUjIjjD8FbI6maMQtZNMU6W +J5Mpy8ZgKwFojNpOECKA0wNjuRhCXZxZyQEOEiB85x2yltNlPn5R1pgyX2xJwJ+HfCDZT8r5eU+B +DJGh/mfrHENUSj7dq3689zeXMzT+hkvedIcxwv4QequtOEkAKpzT9iqkCCQJAL4QwBZwLd/zOWbE +WWDELY+DbIlY65OE6RhT/dANknsAw+39bYjBxMNnMQdZHnkmPpt/Q5/BxJnnB8HpSLSWHYRvohOj +W843C7rXjQpMJY+J8GtEcWFIeOtPUZA9HDAfGhjOUmb/9rdNbIo7G+WxNZWTWWpEKIBkS/j6+X+W +2rXvZasGiwAFgiTCl1Efi91CoN4vD9NWNJ5cqA4VWi1d9QC3SY0kf8GTKsLk/xVMbYyO8D8m7dBr +NBR6vp3hna99VvDzRmN2PvG+//LdIXqD/CFAmiFhwQT6ue4NFRhH2KN9xaRFSf0D16RCha2uAAbk +rRKT47HFFi26XFaTryuHxiiIsgWbqQxQprwk4loVzll+lNBdrVmRoLJlAKhx6Pl//j2NU8j6EDoz ++mAEpeaQS/K033ztPfN9/EHLL3xmJtIpfyepqey+zcDfOScIZb2Krw7QR+9oSiyJ5W9c2Y/KCylU +7hkTiIWpCH+Fxx0uDkYSDQ8vOJeA+/46rJzP0qpy5h3xykaknca4+76DxM7B241D1GKQRI3gMJRT +WWovKOzIpSQ7PyCmKtzCfFKZY2XmSDTZcEodcb8y/xOZpR2SverK9sGY1LRDxLm/pJVERVMFoTkj +zEfdf4mxhHzohDkE/x7VVneE/Zob6Roh8etisuHlYMOu7/JM3l3fTA6LGS8jBeIsIFG/U1LaKAn6 +Bdp4w7UW4BQ5vEkHHcDsbDutYr/no2zGhj5KNrzH5azMEXeX4LeIhTwld/aldJKMs293LNQt96IX +LNU0M+q7VVhMFMbqU/BAxfYCOS0SuYdXdonBhBrYdiJq4dPg8uptyvUTN8B//ssghq1mL7qWIGXT +CtMsndd7bC8sRoozn5+t9bo/o69+VQBubvMA27axr4WZv1DaL0nAmb98aBRLgSP7n0ddcjLnDaEO +wTAiZfpEh//c587wJnNr0jgTfQZv7eJ5qS39HJsIb8gJR9SRg93emPHbY9OU1Fol8PfxePiG6LCA +Ujk+x3MS7lbkypICY8jfYwqz8hQtruUhNtzFMe7auX0hvvKhllLU4Y3I++HUDnwfAjD/ICQ2XF9G +N/h7OR4qsrHl4LRku/o3eilehNJzi72CB+wnam+Dk4liNA75NYLuzVt4lN6ciOlfkXbXJ6lwjs1g +a9rSC4H5qfJeWMyOp36+486gM2/GFKDLbxCcsGbqyx1EPHeL/b02NxVqDqGpyhbWM7Gm0NpxnXfI +S3ctASi210arn4e3wzl1ILFI6deHeJ4nrpM1F/Yr9R0MbEtZ182nfqmTqQJ9bmFVjIPqHewMrzX2 +WfBDkm7u+n/OgTqFY/VuwnLqwy/x59C80NOBGhZHYKvjKKhpg+pfJ2T1GmOu5T2BwJ75ZuzouJGF +y9j0TUCTy797Ks7nRWtvu9JX4PlOTSYCdvscfZdWIIcdzaMo30vFRDY5uDgDgTRaMou74baoVMTp +e+8WUhg6BH2BOSNLChC8Jo/ttjcmjCUESsEEgEfePrjDMUBrUALHPfgNwANQdrW1RQ7/qpEBoS6H +L2DbvzMz5F9GPl5cW+gcbCdHYv98SQ7ORQWpzLh45hgQSqAfbCwZ2hSQFWlVx02DRfOsBj0Lu7xO +cPfXNFHDKWIdSH79CtZJcpLgdruF3eFRKsJ/BPmhvkUt0hC5P+5nyOhn5pgUenjaxtddlctPHDpI +y1fCnCupPf15kEXAf93dR9Dx6rxhylNCreBffa15pgavXr+4+XPHYMpZXEuWG7PCiBYNunE4sHM1 +9SV5qNe6qfZiq9+UATi4sg2vN6IM57TtyDPhPTDkz5u7Qjqcv4yBgBCNKb4jEOpBev4M7Rb8IgMg +R/bSqbezn5C+3eT1oFETqFo0MgpB+MmaQclTaXq8f8u+KOZl+wyaOmj6GN0XwBwimROXXhnB+oCL +CNm11xnJz27qQuxD4aaaWBK/unDjfNVuUJL7Dsq0NrMp7lprYMsV9t+F6M5xr+rNLtt6YrQ7t5oc +fpjsQGAZv8QpokPCVXHJAKvP2L+lTXLH3Hnq6R328AKopP6twRCpIb3C60ocH1tib8JKItwPzUMZ +BIx1NG4VsA4/d/0myjcxCmNOVcx/tYLBi7LN84Tiwl5B8d5ok/wm4ch6LT6d/cryM6DbFGHpNy7a +jKisO2XwCK4Assui1brmiH+Wx+u19XGhoFj4cWYeqyZr/HiJFYKlvYoSOJxyGNlBJz9o4KGjKGvE +hUYSXkn6/mMzTjAaxI1LtpWN/LeQaOFLJUYUPyiRWKxslHqLRAd8ZMd8qWF3j5zu2tBwyX3eJldF +Mc1ha7nOVmf0fAnQ4YkvCSaKARHJrcGPCr7SemS50LlqNap6zSiPqU73zWxCeKZo5OU478kocjNT +nRDg95tA22o1GzrnH1O4DFQs+NLUXZtc0aoQLHi868wZf3cr6koy04+Y+a5h/vUDgFuRYSE96V3u +A6T4ocPTtMitTf+x2cWGwbAOS9ZjfZ9vBwS393BZ33dvsvyU2Czsswo2KtoGJ5qxSG03VM0N+EDe +kToufqmIfFWjPNZnjk9eIVHzKs0VOVIGZp1zFgDAAlKu+/XaarbGJ+PyGRjBxcghuZorJmkk2Q/i +sq7hwUSiOaJ6r8gnF07ZmVX0UI1G1VN6tVpLpgZEkzHeTKgMYpf//hEtfDpDtzP8rlW0ApdpQdoJ +EgQ9bts7UYh03Pyst/jyIxRCFdNNSV+IyVtGNH+nX3fiNQEm+ZCeHet8qX9LMehm0fLKQGQZ2EM/ +lJoHGNQiBsUEfZjpuYKyK56kttUei2YigdtVGn7mILnoiLL9klfYQlNi8kyL4ig6T8/Zsa47zrVs +GYpoYj+/deEfYUAaV0QCIdf3BjrgEbfX2lXHrAnjkU6bRqMfTIqCnAxfMo/Vf20IVEpmkrV1ni3p +d1n+1l7DFogBV2dM7dy5ln+Qtuo0WTNKtKGKH8Ey4J6m2mQMgG+4PZmOGpOuddPxgfaWgV8VuBEW ++K1sTSnc2EVZxv86Ihbt2eIyEULdqK+XGGq29dp2gZl++306pXJ5r6/YMVU8l6WScSChw/2yKk1S +uN7kaimOVpvkcAffobF3TzLmSI5hmMEbTuFwwE9fK4eC/HmeqIJJvekuJed+Vu/FvMV4EmG14vux +fXoKHk28dvy+zO1D0D7f2FMcsFs8OTE3Q1Qwu62K1FmbRKYCBegCw7c/G3vCKLvFBhsJMVJ2+DxQ +hPJl/zUR33xZFXlm48Qo0IFV+9QDy4MLBGflc1AkcwRHS7FeFfVSwn6hirPqpeHj7LYRTwdOdjSR +1sh53ISQ9UyvnWWU1XQ9W0TV970evLr31MMQ12oU3L9R5LxdwPWV/owdVtx+y55mR2wspzL9n7bX +Yw8Dm+OZe2kyGIyJsqSCSmy/dcV3+1jsdcvJ31+uP5L1q+gIbTHM9S7QAo5S5NmlNhfRqz5xP/9x +aju46+0f9Ss1HilJl6iqHX6DU9gu0m/bKyX7jJjpQ2FlCRrSef3iSBvVPuMN98YSIXf9RRqzkHQm +KlKj+Nn2T2HCbjvn2AARqwP09+3QzyW38SJJkSEH+iSB4jttoMMYJsgfHvQ7ZRkdXGfu9nr5joCU +kI6AnRwUN1u+cR6kJ+ipgLDQ9Mqi3sVCU6PYYwZVFdPHFHV+VOKJzVUJI9y84A1/LjtndLd1t8rR +fjgyokyv53+JC+RYXkW1Su2t8GbBMmAK0owv/ng0oTTsjrAfpBE11YlZz1i1+doQ+7oyYsvpJgYS +wl+35aTiHNiCCRCRd9TOCT3UVtmTSbsQCB+onyCY8HLz0peJ7DAFVFcHV8sTEzPpeD1XqOKaThPQ +Wui1lwdaZc08yDu1EKiZZtj3dgyudNSUMIUPaBeZh67NhQOG1H7k5VHygW6vnJHqzO0an8PLNhUc +M4grxZRDHeCWe3tJIjQWYiqEpo5K7NI0zMHmb2QqApuZGBF5LUlyEppB4CCHJgsMtYXeP89fwe8w +OOIuHdYREV9F/XcHTEM0l6QElI+w7FvNG5hpz8t6e8UeXXxWL8wIgZhmbCJEtLGH6uJlUuc/h93H +FCnIxbeNIfYcWXS5ZNuu3cwCgNRtlGe1r33diw30U+BtJsDEKQA/03+x5yTh7/SYF72aybUhkXK9 +R3s/bY6BxlcF+HsngFpnluGNUbmPJHybAorIofC8XJEJYMlYLrJBFzbEfIy3sOXE8QeXShTOVHR/ +q97tN5xW/f8jHcwI+XY3WDNKpvUBJwZXBCKyMh00447MQfqgp8u+7W3TDn8Sd+zvrRUIerG2vU2q +i4dTH2o/LwcwGZ1nj+Fda4S+C/8ulN8hzGeoeBh/GWGDQKikT9RT+nFY9SBKP1pUPKzdGfcd1uLs +GVvsc/5SV6Ju8WJ2fSbxldbDepsWeooKyzb+dn0wmaOwffyZ8Ldl85RTA0J7KX0baUOlQbAz21w3 +bpkc1X329kdPUfdP0IKUi24fflTNsisng3FGru5XLx4TzQbdfQkFTH/10dHlX9cW/iSSeHEIVpT0 +HJ7Kv7s00HU04K2lcFRSd8FOWLZTgPEoqgMZjKNWDp7WNqKKwYk3rH8AfeYuyv7cPnNh2DYKzMNI +dZpTDKaUhCDZwyLfZ3pufQn6hkVqYUWyuysk7p+8nn7d6vq1Rrvnvf7x6W0oq0BDubn3ReMPTCE7 +RtJKZNh46WRuril9EXmAViTvICuc+N23iLKfnt2bWi/8pPzseziDU1WYymxaCanYumv1fs7dzn7C +EGGUagfsuoSsmxn4+B7VuOmUYd5xgV691oDAFD1vjpIb8wEz5iKipl6qA9tS8tAE4uZi7VK0LtVP +T5AViVNK/H+PFyNPLo5K6/4zn22gwlGFFKoqEjTAMO56aUGbzaLLWJPe5/WTDE6glz5/Hiqx3Zmr +iTZc++FqAFv0GDCF9Nuwcjc7k/nskWhv4e9Rk6QJYBuw93iPwCjLUj3mRNGAnJhEoo/gicdnt+it +NYhhsg5+n9MYhspZMF0c7LkaVO+eYh2z+PB4QfB8OpHJnFGqaHsIF3E4fCGJi3oB4dqb0NO49RCm +552LYbzgRPBnRkRcw0oKpI/dGG2fUe85Vf1e1/jeBLKl1hnHducJJ7Ht7vn4TswQZxhqAlPy9Ucy +LLo/dVQ982i8/imlvSdF8kJQZn4+YiPu1xepk3hlQ37WevUNZBDaEk2N5fVWzc5ScXvm3tUIMJb+ +zWwkmx+oRXUJdLNpN/o9BZ0aqJwUQ92fUxhIjBdtYQOuKVOfRpyD2ho7gJYnRv4MlRMYe1LGaCY8 +SNOoXhngTpU6Epj07iFImHQ/DFnQzWqW2B/UO/3vWQcd9Ut7pfbwb7JtsHQM0CcSlZCaFKIlDeKR +N5/5pV87sFTgcXQ010cP4AzUqZKayT6qyjjCLwqWiYWi3l3GnwfdaoPybYFdN8eULb1MuOgF6BXn +Brv3mzuiPBVZxra1uGaf0HwsGrIJKeF8ahpacT3LOytjzJjEQ9nF5dpk7BMMfbIusQ0YQ9pgcOBd +2wjT2rSyAos3wKSLzR9P9bd5izCsZ1gyL2/JPtJcKueVVjAcpQO+07jY5AlFW0Llu46t0UYmUn7u +W9Aj88iDypNreRcUe/7HiT0HS7DQykTSCy0dxOelBn8O/bZ1VoA5xaP5ISWeTqPpUbQFxQew8lvM +ZuAKU8YrCqLaIJyQvoIzN3/VO8mFizegmbl2no9I99PlAoWuUO92h/oPvAIx/NwoH+ZIfFJ7G75O +nTegLBweCeaSSTKKoiLWVbsR1M2NnzITr8FaKc5WNWDIgHxE7MHZKbRr57vDgpnAK3YH21Lqj0+t +3ITipAVB2GMgFxpdulnMHBKctLrPhchdCiNfNRC/VqEt9eUEztRE2YT0xrlwQq2x5yeH3KiwhU6K +9Geiqt94nrK5XPssppykR3GiUy2vkKKTJuuy1LcY3e5jjy6fdvjHbpZrF5jnhiYG828b7U0/t12+ +jpW2sb33YFwXS/YYAHc7JRBwc4YSIj289vfWyrbOg6KRFFxHbElk2T8OE0CGqgrIyeIsx1lMwoQI +4Q+VHQTniHb1cWJm606SFORZJPbPG2IF22ovZk0VgCZ5BHa4gVSWEqGx6AGSPZTJ552lrN/byv4Y +TE8HgXdTikjkqClUgHdqOqJp3SxnHK44ZlaRk5/7DurrRRKwqzyRoA9bR782D38ctsMzNtaYWGVM +w1J+ByueqWxojlfZpqv7PRnSNyRYB5HnLQU3mi9Ze7KuOzMjekaMzmqjkURVCcCIerP5np5GGdUC +uZ6bKS8l/HBL7wSuLjB8UqbmjPb6e4KeCkHCBhhGFaBQj3U3cO13Sx9xXvimHa5MmALf9AHt5mtw +c+yTrl3PdpPe9QXOiXL2peBwBgKmQKZIIe+kZeFZvvIS/gJEQEJo0MIPm2V3SMes8riBxfSY8OyD +1OlGaENsrpiBw9QEBbi/jQ5souImJeXapUjd6yUVHk8VjSom6Uo58LaYPCGGepr/wENVyVF+2dTm +J6pO4hNlYCK6Tp7/5+IOErtV5c7/TvC3fNdNwEsM0BGZRMk5BKTZRp79+jKIrJjPlPdbCseL8vWU +jVKFlSIitUHCiZ40pSKjugaeWvdxoxLEyaARImq9jlrs6IDGaCuHwwit5/wcb6wUTsjL+MC7FEGb +zzNDWE+sHy4lk96ssMe6g4m5IWA8RrbuTHk64X26FGBODd/2OqqPiyXLB9tiGdM9dmsp5Ssn699L +4ETJO/TxvoxEnJAP2v3WbPaV85wPYAw8pyM6DIw7dhGSFAwZ2X/o0/Zn54Pe9gbWXt5Jkj4roaam +2U7H6wO3hB1gaDOFEQuJsBzlBOcHjgqlj20pJINoNYpylhSYvLliYcMVc0yHiE0SwrdQGjqifpfb ++H2JCEtjTb22YDPlgapy5JARTBwpbMO7lg9AgvNOPrxOZ5XOPIbtCwE7yeopvy4KA7t4eH84yLJn +/mWeek6xOasW9hSKZ2YZZ2HVgewpTJtt5JyZxZ5HzE5UajZEnNXYVohkr5q/D0WS3Qz6GDDz6NEq +zGG2Dsi4JnnzNaL46hcaasnPwAJDu/TbnItnZ7zlt9droCuDvOydvAcAkITsiEfXltj3Kof4MGHM +W8kcv59VwEDnl+J9g0lc0hhjrenLdCr7DCUvoa5kXt/VzQMEBw5S6BG5PljAqx9KU8rF28dKXDbE +NBt4IVrw+TwEGrBj1CmyUICfCsUXbq85N+uTe7FcviRDCDO7m35VnlF9NMu780jau2HZGvD976of +HHZV1ZXqXhqgugquJq/Np60ZYomsqbIdMlL9aVoYkKMJordjFGXRkilWC3Ijh4fZVusffpZ64IRI +NW0bfKRQM+VB3q/1FPxh1vSnmFVECG85mA0vqF7oGzVZsE75LlNV2VtxM79gsG0nvZtsCoN/ePJY +fOCWJTl79udFbPdeazcr71bVtGpYN81DIpOO/TvesOxRz8/q/OsubkTBUiL4bp/2Pfz2Auakb8au +1+00pDgGJDdr+WdGpIvvIX6UUFqrMm6V8drmBNCMIJebupKVQ86drpihVGVY0zIwuL4GsLAmraIH +yeYLe1SEXVURlcxEgUNej4DN9PdZV5g740MLANuksWtwHrot+ZIfwiHiIFXNQWJTZVboQu1cFqYz +dt9NISTN4BxN+XDbDN5ij3rFv7u0oncm4lXjsYg2HdijzprwGnJkOKFTPkIzcQ29f0UCHInB6N/z +aFg2eWi8snol5nzUgjZGDVGE03zbTxLDMTcaH/acSrBuzDa2Oybds/5/reePwQQl5heWizDpp5Dv +p7szxlfIAYRCayzkIiF8P+42jdSZO5/mAwlIs9rTC2fcsmp+p7AoGBKw6rakk6zACN+uFqFZS1y/ +eZ1tZH78OAAv15flie3wTDyAwFKktkdwDIaT6c28l0ubJL8d+MOkj1a6bdUCroQ+kfGMjdm+J3Mu +6ySIDYz2kzMKBiveQLP0IoQNMq0/+XOSEwLPpEWsG73uhwr8UF1wFmIo+mczy68TXAKLEQqbWEYS +qdmzyHE5aiafHSdhdB+ZgI2lHzCBXolVMhPaIiwjG/7UILTYS+FdTagDjtGvwUHn+wXz8qSuyyil +PUI8TE/NH2CsDU7UzpZH6VdpeDK9U0lZQTwVWUD5iMAmHOwDtHx+a93YqrVXJfeWqvMqGjMJI8/K +zG/uCSnC3wjk9ytrz4kC8Q6uyHjfhesJpA4JowaOd1T0i5Pizpy/AfBC4mmw0GaDwc7MZgci4ZDC +Tp6PZ4khzdqa+6uJVRmN2CREHTPul5UEXiCBv6KDKpijPiIyfmmdPWbD19YtTEiFjDJk95xqhl7B +sUzPV3H/Kw1iekNa6jZ7zC/ehT2/mkOI8KoyEX6JW7DRSjsj0ZlIVOUeXDaGGyHhLHOCu3hV1Sze +jQNFCRwvm2tI0W5WSlzWM/QHZE+leJ5YxIyNLTKfdWJNNltAlaMJFcvsLFTvPSPUL8f0vW57EGlf +lERsnlYX3MqhozcMQrfpNDo8ofdSVDKp007Y7BDZWTSg5iwScLK8v8jeXd+ccOjBrKSWSWaSZqNZ +la7gVX45K0oGpOybL87RjOV2DaW3BPpzXLTHPbiL0IFcytjxenI3sio4qM5XwEVIhtCLnvuhb5g9 +FR/gEmyIBDcmT5FpJZ1Ffu6vhGlALv4dUpo2iRfwcdU1AQTs+ljKDf4IkfEMHlAvXQT1NcNxqe5N +nFbao9Sa4ZodDFCkRbZZJdea/3lA62CTEque/sx9KI4OniJ8jJFHMJr1xHIK4YjU6MK4b+ax8kIj +fOAOG5cjpfacf63I9SBmQGSgIQ3UcrAF6jRAmKfU/PTSgFk6t1tHb/CBwPmhqyOYPyN+lJqlAUg4 +dJqSE9kosIwIos5DMn6Czo9ghzTWrhOCJ3m40VMij7bZpqtA9SUu+hi1rBd4ZrEwmFbhc8im8JbM +dtGg3adCA/Aqleb9fmU0SSI99HDDeut5kKNdRqAU+o1gIVZsBJUX8UyhZwhnOw+Rx19E/KMuI4g0 +8a337WJjnzjcCg+BokWBn4fWw2ZcyQz48hUGAiXASbkS8Bbh2rZ46FCImjUTzFtjL4LIk51x10yu +ASuHVgaFyI63s4YR/Sf9xA9teSk1vOD7F1kqmlqfp10/Z4or1IJWmDM18eE0v34eclixKX2sPcMu +ffxpJy0DT0pRowduh7nGSee/4JjK2ewvmP2W1S0Qr1W1SZyBVLDOFREfrvarBfGiZtHMp4nYXdH1 +cHUsx1mWEMmg2PVFiYuC8/8OmcMzr9wq0wosffELHpLzSYsmyZDHV9JR7xtNBPZ3PLuzkhZ66sQk +jUNXDFC/GiJe07DSZGbhH+EpH6RpPgsZ/iI8+ohdbZiQPPCu4wZOKynB1LwCfq0RmC7320zTCawk +K5O1ZO3BuJe1uiOGkMm7Gk/q6uYYLTSRxy6mVisJEtKuICrGfQDnuKKJa8mFH5F0YrSQiNIqEwy9 +3fr/ZsYjPyITf2/VghMNMX6KxXwleOyj1/FwNnQ8inLax6alClr39UtPOttaxk50JDVl+CoZx0Mh +FYV+kWhHEl/sgpfBCk611ghlmPh5u/Xg7Fb03qNxivVkDF5Tz7h9EfFAc9mckZVQY5ZpE0OZeU85 +bjRfWsjOtiDqD0lgGsLxsmLkzaPhmK3AqqcPBOzkS+rWjYyb7YBfhuI4PJHheevCKNL58il15X0O +K1JQ4CRGUPZyci7Y+lEksa8jvbtJFsSGr7YrrYP/oZbzbWdVw2D7HQRLJV/VBJDdj53Dn5acFPPU +ZwDAayxI9+VowcVgUmMdEfklU4KU97UNjoIG6GlAypVmQY8eB8zAfVrmZvz2wnetXWqZa9wNHhMl +oIFCD+Vf99wrr5ZmD+6vRqiw2+dThcXo9ycUwEgQL+HXgfslZ38WrPvwuFV1ometl3ez4NnCqVdZ +oYw4KTQdVq4xtB+NZmvpuEb2nqJS2cPHgpQUU4tYuKSoKSfLnpeQDMu3bksNv3a1hEza0lGq+IG3 +cY6XytyyKtBY6V7UfGa2xy25Jt8QPrqtUySP7boDZmfsrjn+vELxqiZ3iJxcOpAl5/+vgTLfksHz +X0Ql1388tzcnVIavOUMmHhR8T63VSZdGmuSssGd0leYEbmKnpDoeyB8O4fkYB0n3GmNJ/gOCE53L +kL5nsWooHRibXtqETXYh4Fzur1WQgcI+vY+Hudo8DMn1U9+nJlLfDv4AqFJ3ylOjChOpVjOgxOTt +uJMJ6LxJDc/r9l7Yw5muI4IjCGd5OfdFybS1cKnG6wNGOah5zfprEwbWx1/+zuTUGhgnN2eutRJ1 +g63SRCmEG5bd4C+D6yi+qtdC0ZHJGxnPAKwgGipyeMhLzt2YguBul/T9QDmc+A/si6QSsVgwBe60 +onsPoOFp6nNhcr7WDoIDbBgXSSExTexuHo1haTLI1vGzAhyWWxZEPlfOkQS57ij9ndNfEr68zzT0 +Ispj4yqTX3iZ3EB8EkFmXMknt4gUGchBS3ws/VmtwAVP2xvj//OvpvxwWj11xIvYqrVMFFmE63+d +mvEmQ4Q622TrjhkP5HXKjwwtCrgh41u+z1wrl1AJfDuZcpmFGJ2EgukZgy77rNol1RrrLgvCj4/Q +dX+fTf9PnPdLub/VFMZnZipvRP35mLZZqdAcxTvyBblQStS7vY5MahhNr5IJ/JBsCQwIcPduqIMd +qULL2H8MuA4dbf0tFUN21bZ/wvr4uqo0WQEABrjSliixvv9C4MdVIRnpS2+0pVR8XB/V9b+f1Pu2 +IiVvWpP/uwdzawGCcRyBDcAzYtoqyebqQcOmx5s9vQT5KyQCglLisa11E7UExSdo8Azmcimh0YCM +K9IJEsilPC4fsoVP3xUIentSGwYUcmUpf/EGKrbkEzYQO3QGNf0e88NhvMXz+W56m3zpIL5uIeOf +KGPSxpCP7FHcbL/Ca6TOx68XyZjEID8ajpMDb1qptUfnuCiBPws/E4F5V7oH7A52YBdO+ryiXunE +MhHL/iXM2gC45MNepm2QfTXjDvko5pNeh8ZkxxHRwFmEmoCQiWpQDkXhdCQAQrVLnCQfZmgj1nYq +sboh6+EsLPY87GmZ6M8H1nd4FQHtm9vQs5TFmzvkj2ad88pJ1hocKRELoh4xUVDNAkJhuq85qhTa +vYEZbBtgASJ5CtgxxN3QQYDEjTSAAT23BHt3JxrR6yideet1GnTdwJPsiTIQz6eLu9FiS4IsccaM +ciB1fi4i7pTrDfrGEkxYnWOd3lDLcEflu81PTwSh5j34eAjKk3QKo6BkAzIti2VDUJYLTt6rckQ0 +soWv3up+jplZbkrg/sd8XBTZrr7YJ8eCSduOb5cwZswaiX/NRfymCY3KtX90hr09LcdA+GJryjGd +zEeu/5HT+AoSRJZ+oImt+UoWnHxvgxDLjutiCuSowlLyQGpifau5iMvUD8ZO6BUx+3OL3bJ0eRKv +gpL7FUQp0waBl25WD87sVnsJr0KMKXsthuV6RlXZBWQae660PU/f4RF7q7h6375LOMfN36CxQ+Uj +NyElyZfhnCBLqUSwWYv149BGEzcPCMlVrKV6yFmyZho6jaqdrV97RWHwpj43xQZfBiOwjgOdpg+b +ODTWnjXjpnBsLQf+zCjgpOxPjuIsdKWxMi9lri5ogfP/6Nz0ic9+tQxvsh3BmHISLv0loVrXriAJ +t5qKHbTgEgNgi8/XLcSkGT4Bfzpl4mQIIGp5V785UZCRnyL9eePkrj7WJn2buy21JIRsYVCqAxXI +paOlzqZfzI3a+sERdlRjVZbbvIILj6egDbCI2agLmQ+I1RkBoNP2GY6/rVjKqZSn7KBDVIWKrnit +bGnF++7fr+Jgc99DbE/1oPkUfvMiKwVZ2V2VnsO8+dehOVXU1voHT3FTQ9KC+JrJXPKDrZtFl+9n +0/x0KfAzZrJSpfcsYBwkCx6YbxTqYdeJADz3NWzhAIEMzaILEoSVMyDKvImfH7BDU/YoKIfuo02v +5Zpqh7ID1uwyED7j86oK0DYwTPSpGgCsPW0yL/YZiJ1rj/TeWZfUKgW3QkE6bhMQ/gS75tOss6wg +PGF31iYXn45LXWoJAOaBA4sLIv+jyJDiKfnDnngbby8yq58xkuulFlOj3mgmtpQTejdW9NW3/aQt +8FjDFn6ndK2PRqitzAPaJKkccJ5e6yhxOhJ78lEN26eRRNtmp/EqdOCZygwf4tP3tTdocNvEcRIK +VrgwdDpugLpiImoY7Ov78vG3PAmolkQu8JFEPOT5QgXmyQFsQqSAmVT3VjhCeCYTbbvONDMOtNEq +MvIbszDwONlkRBP5cInG77JNDu7FPcUzyu9r2Yi+bfhy1LglqXFOBthxBSCxvOPOmwVpBWn7CHaT +xZ46ouwnuToI2J+6nA77+n/ohgdR5lzWG0c1cv1zhK3QL582Qy3xRORr38phaLWMHITZirtoi3T3 +oCJR8mc9YARWMnMYZ7GOy+aSPrhZ0mfD/uQCsfCxKUhsAp8hWGUx3+lIGSHIkHyIcKQfjcHXIzp3 +9t2SgrEqs5I7Vn0X49+1NuZ+255KgqZdJ/b77n3miI7b4LvCeNtw5GH2UE1EXRr2RHBAv1hMMPmD +CRzzNm9wS0StzsUbDBrCVjRw6ci9oC4OGyPGFmlEhyW9z66iMcaaHeAW0Gmgz8HvVANwbyJf/kcB +BNtfQj0Uv/qLSCLoLfUJ+hPP95gT0f0+QHt7c1j1F6pEwTRUN3tHqyi7xs2GB0d44HKKJv6UTiC8 +BFPwhG0jK/WC05rJ76v1fInQt3mydfy1pt99OPwehsZwV4aWvex2aRQbsD2XA6efUDzL30MW1Ucj +zkP6bdPFsv+0CMbD+NbnWLK2gs2FX6roh+7qlo7XhvAfXIQoSe9zczyWRx/IhXDgJ1LM4IygAVSf +RvvsduDGDc5lDqHwJeE8UR+8uVNuURkvpUbhmWAKP3EijHtLe4pxPxJV9Mhzw5aZZTzSGAXOr7g1 +QeTyqiehVh3kIznSYppr2T8J7YMSL5aB92b4HWu3P8bSN0Uretic/lEusYhJGSH6fnHuXGccq6cb +uZJ3cWh63YsX2i1b8v4XxpR0H1Q9koS5GSx6Y07J+ghCMKkwSYe99aJQzc8sJT+TNX/KLmBHFTZk +n4pNccPkYNv3XYmAi07uJbgDm+RXFfpzAEn9hgJZ1ex3yvHMRJNMCgfHzxhx47kDs6AV1Tir432M +NixXEw+wbwNtYwx5r5MvGhKN/x7AdN/glggEtUXKA+C/rQzbuOzfZUKlbbEFA3n+Y3dBSqyHP0A6 +7kMmxiP2lC3qIUi+e4HXjr+LXTnRAnM3H57QRMsEO7GRLHrVwSewN+J+5aAnn+iI7KZpVE5lzWpc +z5FVZzMA+qJP5hAii3aXOWfBt9oGW2hKpdFHRkgQkr1PCCaip4aPXvdEByOdbB2ey/9jDU8kxZ7+ +amkIUySWQlJS2myyMgKwM6gHkvfyeJNem/zAJFQxUPLf7H8DlmPgJfUOawWG+ABt7ZvIoifIzSHa +ynD2QxYrXmW49I+KvyvY2ty6T9cU7ClAnLwXRUfx+kySidFYBi+pIHVWfsBTj4jIoINMhJnV7X6/ +3j00uPFTawg8GGo8EgxQWwcpGD+qbtB+9IfsPBWXoJqpnfboHbncsV87LzfN4YH8C1bZsoZioLNm +6hymjaTaYNUNNT9H2DeetajOtaAUhkGk6Q8OPYynSziRfEgloFo+IUB/uCi9lWjW9HPZQd6HLfU+ +aZbDxjilqzXEuQ+kHIx1FHvnCxfBMwvE8EWLj6L2H3V8qC5yvANA9p1OOgaXAh1jIWcKq37t3UtL +D0ddezifT2uW946zJ1cGr1R61eW++NQ6XNtd/96Vo7HlJgOsYxLFFZ3IFrhuHQuycM50A0vDxTcm +vGab9xdCqDOgAzt2SYhOO4bVLvN+dK9ylGe3YUcXDz67w0CXDgKgNiqVTLtqMXxWIT9/cQJ0TIcO +/LeLZWDvEEzv2tASGbJliojd8Cs5Kk/U4yWxU7vQpShw89ER7FAd5NFN2VqhuwQWIv81RYWnsM0s +MoUNU5iJPsdKgZRJWqm/QGuaDiS3VggaivsIhH2w7lHQcC+BI7ZLTewssNSVJM25Yv+8+nvTgCtO +fDQ29Q58quBmscZMTiVPwqGHlbGb2beDdt4u6hPKy8LPkW3HjXCO/rZXcskNPv/t57sZfgzTgfrb +fDQE5bm8xb1WsWCTMfk0buHjF1BMEFv7rO9gS5V6uqeAAeF9LwWOizQUmcg7J1tIp/JCEYC5VTzL +n6KC09Kpd7Ady+mnsTv9lLdLT2rzO/LFvcK5G1P+PWLUP1NnW9pJeT1lyZ6GEU1ojryyaPZDGm1D +lzd13YGOUmBoCSgfgx+Dp4ltyhxo7uq3eBw3Q1vgdyBGY6sPXbnqbT7g5gMRLnrLt29S7pM/fs0Y +v9VRu1djkkHsG8De1ItNHJ1pqRGtbgnuJZ1W77v86bF4QiESCSfdCp5sY6SIJ+KjF1IqxecxT9U7 +PltKP5+z2bT0pSmG+tC4cqqjDRt65hcia1S84RukeULXwA4wFJ7howSJ9+eDPbuLxRBYI3b3L6bL +HOuQ4axinOwt1aspGKyXwYZT+6oN4QiSKYB0MDhO25wdlcIvOCRVIstCyjaZUbcOSp6FDkJ129eZ +WyMvs0N2FssZAoi1v9gHLHXzuRu5ITZyubhrfMN7ziWbu75KFWhDz4t3V8axvjVRClAT+xNoNxDw +ZatAjJ7uDoYI6b0Iy7B5uaE220QhDbXyNt24E6XJHAYCb/DRUpkcadZEaAfyBCmsFKlAXdocLXfO +2O58WG7WKfFsPytCUkkfdBUQGP0XXpsW373knSZ7FUcywUnWQO2VUuXwOB6HdbUD/Z2hvZQC8GiL +cwu7gVb7Wb3QfwRckJg+/lFL24m7fBHri2MsrjNJwDt/0FcVaW0lU/4zNhqAG8xOs8JQZkGiIPxq +DhuGARvjDhHUY7KPX2w4E6jFXVDMD+5Qt8+ilLAGC3Ir5YcqNsdW39BeXY+RfrZu7hN/PCuZSqlY +yWS6FWJV00GR8lTZrGijX7w1HTOGNnSMUKKYZOpkNoFMfuLjNkYUp8na/zgkKNHPcmbzUrO1Ngbr +JRDeiu82EhmJ7xYM/QcQEmKQN7f8ZEHBfjCu2r7y3rqM2iAvGvQHLQVdlBL6tPgVQcSyuhUYFzW0 +ui8hDOq9L5rMnrFQLIX9VDjiYrqiVoJheRVyId3nud/LgY8AyDMr1y2mrngpmBsVm/rJWfS4WRIu +Rg+uXR2jEJNVckluBBmc2mzffKHDPnmxA1mkMcBf5fddqxHQDHD4xktfPNA6WVafWLD+6Bz9X0L7 +eVz2pnRzbou5NI3JFOwSNRTqOYqJOnwpUszi7GOLyf1PXOJ9ZrQQcFaCzj0LsaoLNoQsEt5Np1tn +W3uIZApxE+0dUdrePMF+O7Hy4L5hmJyOavJL7KQ/ScWWU/CuTw3ZWu0Sukm2cPoqtcyJWwGqOlVL +25J1ZcRF0y6alf1XDKE9GQwkZhtq34L/SsIUihad6VezMBGKnubfaJ3QVqXShbKOpkABdVVSDo6k +YdTYgJBqakQWfGZcqNlZyFsPdC0n3wbhiSrT/sEfiQUnCU7P2v6vPP19nWBRgRqMK8cWNeTlFw82 +L0Z8DQz3TNJ0Sv9YhYx8lnWAyCzBRYLBNxT/ylpUkml3vE8qDX0nSnCR/i+UYigvqGCLGyonROH8 +r7OStGDP1kovS4nbJ3LdYGA1Jp5FIj5ro/kC6oIzzFcITG8N9xc2sPAM5U3EY9jU+w31MNXWWt3t +T/Rc7dn2Qz9/HQb8Llwg2rZbcVGSMmz3oiczUvBpWCxDGUACCV/a/FVYRyb5+9UbibWkaLiqAg37 +21MoAutXsaKJ37PxRIXCcQq/ASq6oBmUBpoFWtbTTOIgGjM7uEvSvdTSp4mqy2NlSaJAxjsMLAr7 +pDSbgXgL02W/5OpTHbWuaHoJcifkDad7698Zohu7ZuNyOeNGAfSLeuniE1mWIzlThnHJxZO5zBTi +BvgvzJCMYOPc9MXCJF0NsVWqLqm14ytjkuLu8AW6n6bPBXu+fxZQPD0OV/fbpFoSNK+PRG6OQkcd +SMhWYmQbBiIhNGVftigB2G6+b5IYuiyW988AK6OSwwhWQxZHbRkqc8qmUSB8v6uPNI/cM5Od+kbi +Jh1QQGYYxWj0GnSVVLdGNXhIdsKqP816WaJlIqi4wsxBSwFiQl1SWLR1sV7j4uu1T4+XzIBEdvzt +qyhb7VEMDzeX+dqNbq2fzJKGt3A+wp6suuhggmWhWlMhVJ2Cpb9Z/Ppt8s3JtsgcMQqka6y02lKt +x9/z26qhTioW+YsEliOngeFmoqKklv8eXLilVOC/q5Rd+dvdlWs+9rpeObmKYUkWAoaxxSxF/8Xj +JNPmwyfLTgd7wzKbR4f4Cj4h3iU2RDRcXnN7Sy5+OTNj91kddDyONTMNjYe3vnawWdrpxtrFhP8V +BSR523/SkicSd16k5mG1RJ1681LwLPY8yo/movy8mmS4ptdaUK0nnWg5a9JowqBJf+jsFyUwcLOg +LmJVIzOPkRABhCpgqQy4ucsOJ0kN+NAzNELpsWRuqiUCLgFfLsvsWMVyqazBt8zOYAVODhd/oLH6 +hlcUiV7gOf0FTpQtcQvxRes+L53nNHzijUHyruoyE/UDqKVIuEKPDpXOa9D+N+npdT5xQqqFA7/3 +hKnYatA+XOlsKO15LTVKP9vmhm+fWtKIDz7GN5lCsUaZWMtS6VWYan8T5exnsBVa/FfP+codBiXb +wYQZjx33p/uIP26axa95YFdP+27ZVSdmVY1IlkVdeNRMFuowh1xvqoSmfX0wisG4EaJfL7/lXMyL +gBr5SdmufmgAjXOacQf/oQOnJGKKktmZhq86JVKisnK0o2fCSSHBJG1kHIGp9bp6iqTbstLCqWcI +ELMOH8TyrUVtrCaGDsVAypTIvXx3V2wAp87jKL6cmGha+x/egdmtI6OF53Q3hQPtjT0ATNHY/vAR +mJXKD1nWmH1Pt5pD39U5Hj9g7/BKueqAN26IJcvkli5/pbqE/MxNLiQcYEWJvDvDgkvt3ust3TdA +LXmkVMWNU79/oneRveKmxgeZO8ggZosYUYX1misggZJwZx9qesQcVbkYa56GMr57G1DpvWAMTzLo +V1XuuICurrDvDaY+rNDzDV7KNJ8LVX5ox+QhZie/MQO6wUmV/dLbpB+qm56BqcDg7CPsb9Bny1jd +PAXHVT36VTWOnNjIHbbWLdlpjrGfgTBwHXL4+3MFXCZ0bPcDCip2LRFLlQj2YgC4e/v2OPcAKYID +KlnU4MPMDotriiif/G3irJPNuBJnbYZMYCX9XkAo1bU1Wl/5umz0KDsQv0mf5j8Y8lyY1GN7tXHj +oa9BdHhuzLBTTAiNFJewDxB0vdaxvmlh4/vWuHiOaIyXA4rjRIKi508JFHWS4F+5Lt2fVLJoOUtV +DIfMNjf4AJten8kjBQSRPtaB+3hDSldQVfQgC4jW/xCDljPkuSsXDoo6Dl2v9yQCcqeuSqbPDhMI +qwOSXtH9abJLKvr+fsUaX2OiIYlPGZrInQefbnh1vDjpe6VjxRtSKpfTNEL48Fh923PZ0Yt+AimG ++F83LFLMaSMPw8ExPtQ/i6nhDOwhQd4ZRR/bSsgys2RgSSatjyRg9n9ZtyTAANsPz3bSK5xGGd0N +ValB1JuMiJNfLvux+CoLhc1yFHAPe9rdBMU9UDkL1aCzEY1zGx9nbDBlfl+4YStJNJlqPuhRnc3q +0y7unqXu1bht1LT0pthqX8L1uwlfbIPjnj0yraRNCySF/rnSEeP9mJOWl1t/knpubKuAHPj65RGQ +8cxQpx+I5PvsAi3GFTjUiOnvLWKQ0VFZA0LS9iyDt9wmDAN3lmrtcEHvdDuvNp2XmbQ/Fu0N4QvE +SPxn8+lxePjKWlpEqkn3LQeDbPXiGS3z83hi18amAzmZhQbfYNVKuLrOku/DJkZLVP6+nB6UtgzG +hgRjS2l737Vdbfs/Ns9xe9gzYZ+D7j58+5TnTvzm5IDfv5p9thMMWuySeQzvJexUUE4WV/mKbQCA +K1NuZ9gEsxFJfqjJdVr8evwC//YMio4ND5XMvezgrPJz+dbPm6DjOBpQsJbGIgH5Mb8cgo/NkE0l +iuWOJxTCBwYm/RBT6l3Z/kSmCf3Te9SJ4JK8sPH9VOZuO0LRH3X60eMivF1S4R26ysFkNALTdmHj +pM1SQTF2B0NNeffEhuh+hQhHHYPZLvmLZ9uXzApU5oGn57zfQ31uySeM9ZQj1Pmw8mCYFwodWKwe ++Y8EV1Faj9dITz9FkfBTgIfZJ2G5iTjljR5eU+pI4Yq4YUMk+T2rP7JFYe33IqKfefqnLuBCUvOY +hKfzpDMatlmgqxmsZCWbofVawv83wMAGlWhMsGIqgcJbGmarEOz2vkJsWUqUe/z+jMPn6qPB1eVA +TvxgN929zjNdkpQ3OdF0EAKRzctfCFr/xgdAJQ9zV/aNEjqUrTiq7rV+IMQzHUOphaHFob8qxRW0 +0t5pXcwIkPgFuTw5jIrNYz9M1NlJ7EoR6F2zOwx9qUhF0JCCUznuFgC/6le4t7ifZO4+u80UIuyT +sIzzb0sGwQ8j435cBYOm6adrB5sfnJsGHObWZV5JRn0RgQzwIgLFxJ5mHismBpJsCeTJYASFCTFb ++C7p1KAE3i+k02AwMDS1CsHGrZPlTuKjYi5nB4RQ3ep2btTSEQKh9G13GfSwiVSgZPfWxztDkIYu +1D7FmW6lcgaXiLD48RzqEvjjz7sCG8wycsb+QFS9GkAdbsFN7CPb8KOoleK705xdR20/ut6zQd+o +DcJ66/zx5QD8z4+kBl1tVNv/wqZNBy/1sL9q2zWWXfTgFfeeTxhOz/SJje9KWNr3/qWcaAMyqYbM +e/Q7/Jv407dYYZlRaKHWWy4eM7/Ds28nCdJijHmCC/P8XxEpLgRfaIhzu8uodxhYOgNkMTHcT2sf +Q1W/G/oVTbSTghRxcWWLpZwbrNdawCqMqhpv9bTHvhrabMhUlFqizks0RH9JyM4rBV2TxB6qSO+f ++rOBmcxPNkhahq871DurKzAmSe1TapwbwOe5zx/qvPRIM9+jwoHwsj9g5DBBl9i3qgOvOY/zKul2 +szn/yHgOuH5dSOF7+1K8bCKNPJAVqeXa8QOR+h4/DtES+D0b1nSc1FmeszWGRJGGYOLnZ1dKao/J +W6kS38DwMtpoz82DpTndtCGHruc4J/zJkCaPld9hV11yFLv317qUZnhyzdwh/2omDr2wqKHbiHj1 +rnai93SfRE9QfRGrJLIeP6+MJsQpqmYd1E0VoT6RG79LLQb1nc/n0Zg78DITZQD+kwbu2Q39JeQ4 +/jfICICh3hAMk1LU0IhgGF3p0YkjFmwjl0eIwJmUpLzAdERgiG72P5Wi8FAPwR/rPTgztHaV6s0S +NUMA2pbSnQkMnvXXElQrPkVRnB98U3pD38WxQoIqAiIMUxURph6ft0JvIKXROysPuLvfZhhSsf2R +jIJJu/P/xw7sCAIp7hG4RMi/elMZzYolDf3pBYbJjvoqi03bPSovWgwp7wOoIfayQXZS1HFIiuRY +DyQGyQHT1DKa3t4+YzfsHDlOabDSbSWs1YMin4yj8mWRkEwyLID5ahYSUkH6IQoNXWrYA45Wn7cK +l+1qV7mhxUtrL71orakSHMub6xquONJ4erSzrUgkjGMSoR/5dfurgzp0U8Dj0vQeyPMIiWkwDcjZ +QQcVtoPNHuYpMql7oz0eszE7IJqhfDqfW6/QH3EWSSf8GTyWYcq+rDI/w3JWPn/KZVqF/6xw88RU +XilSZDlULmBu1wrZF6KHxUY4HtRmbcJ/uavuEFdASH1foNikdn/aFzsYR1P+tAArkxgkwjIWoYVh +FTDYDv4w5q68UVNRJxihDGI3dtGAzbYuN5sAp6F1t1vwJLThIKFS1pt+6UEQpZZYRzHHSqr9Ihsp +p/HIOI/hmuq4uQ9AXCCVPBexX/cHbMf95BA3jIGUQ/5tdb7ULz/vjuiy0TuIEHxLic9DyWW+xzSz +oLKjcIrxM9TwkG7NRggNgkiL86dGf+W08mW3acXHrBnXJD40dA1t7LeAwvDvID0L6jGITSQ60JqY +/v4zH1rBfB5dVPul2prDseIPZyfLCaFdzaBfPs0FIWUdXjw3caA2VPBJ859GeAVu4fYKnww32VBa +0UisuTHeyyYdgq8lwU9JQszPeBvcKYB+bYbBiV30r2XL5UyYHLmFbWixeisp0+hDpwT1Pw7TIe+O +3XIsveGzi1w/dC2yHntyKJEeLWTKKKdrGX9KC2L15yYJAnVgu0Z9ImB9oZ6pQyY6Ol2+IZYuSmzX +T16LY+qhcXWRy3aGLzou7+9axrj15VlzitpePCXqz+S2FUs8Vylsdc/0+eaFATqWAv6AAHVZdFRL +IP5iaU4EDd7ONH8flBkWFQ2zJ/ZkUWbsOPyGWYR/w+ooQuIWPkl+3pu9ld+suHfy9VqHu6GUX7zm +5np5OoouEOs7+YSClibg/xbsvwXzx4ERtjMp4r0SrOP5RdOhWxAF2hUNcBFQLEFIEmv7QucScl3b +UtRzGj7aPmt+KYccZW2MoCC6WpL2Gps9d8D1XakJUgDm0GAVTgxNC80ikwkoBCntnIbyKj/j4HoT +Nd1yC9RCU77g1JMJqVPfr7ERzDJ9rXrQ3rid36b5J5AIHrt0mOWH2t8e4sFaH2DhY7Zwpr3DBMRB +4AT4kA4HkXOdpAO4IaIe6hj64X/TgDcnasNafnFTMt/ssRoUzIDiL234/L3GsaKyGtaHINwq+Haf +beLMPIAZ1NthvHxdgeC0DIzSh6GGUvWJmy4En3LkW0jxAoUV3W5DSZB0t0l4RJtIf8ZbmpCWLz3h +Yor/FgdnZBCQ1SDEnN/C3Y3NNFFLQYNhNXS4tfc1A25xwyKO15m0rKx7qxC7h0PjmNtPtsdeDkz7 +dglFEBAMq3//rZDFpHdVvRh8BpXodzrVIebjQVAeXqoo/jAkGdID3yp5zeRCAYQaniKHWLGY816L +vOW+1jZzMbb8bFT65e2IBVwgNNu36Z4sne7trlHclNiYpBaUtHp4GcQa3gSHC0z3TSlCzvM7/OGP +DrKYGQS6awkn46wsCvk+pEbT8fB9hH7q8ktT0QWvhg9KAdGFKc/QDjowrakpXNsOEFvUcryPNNXB +SbWTAslm16JD2WlC0WLZJNSAKFK2GPcED0tlV44o1A507TYpbn5nHtsKcQ86hqeryg53Fr0emSQ6 +PUC4gXfRilrWqJg77BLwBflPrzSwAyUGHRKLS12l7xasCHDFk/j4ptPKQIW8L5iLjRBrlJj6rsAj +LALvl05X+Z8EXQhgPxcABQruLFxeX9kzYKiOGVMeevzVq1K8n0yTNdRJmNXvIndk8O4kbnmVlss3 +0rE3oHFP9XKskzfC49vdUIHLtNcV7XK/ll1MBrWjpRvRJ9iMftE5FV7NAyON2FvnECEuIIkyAomF ++S3+8Vp6RXxVkGtZcFziFYtfWZFZNkCqwEok0i3ZepIcneUCObeVq99jFHLVoYnohq6+ax29sZ4n +NEMlDMWlinAyT0qAHzthF47anEr0+G4Ogz5gZdw8BRbIuWeGdLcArSDWH7KVqEi8IHitQfU1uuKl ++s8gn0eJNz81CANxeAr6cg7Q3dBRJfmolqpDIf50ebkyDHaaQsACqRDuD7GDJNNH4wKNUgJ1mIFp +awQF+ekRXKsFMQjHApqV4buhakjGAwr6qtAYKcWGDDYCJ+fj4M1VNHueB++Dbz1428Y0GlgYTHcM +lZ/gHdgcHghJaPyhIqNKbkArHZSd3l2nk9meXwZuaZCmzu2A/lbZ8TJReEBNsbsnfKsLoYOZjE00 +9Y9CEFrwDKReOji8eSsUa+Ya/QWTtFV32X00of3YH+2dtjRB8Z9WX8nzV3fY1NRC2cgJQFnO81uC +1zWg1wKnhBsmJFl10QWhiBePT3E8FqWPAOV56tVHt3s45NJJ31InXtgkKmxB54UxVS3kEK07t4rS +yeJc1jCCEbzub12WkZhQFdx2O7zx7FNI4BhsifX82VtAjVgcpKVzrYLevXrwAB6umHglOQ6dKG0C +kkpyOQ7By3KMtZ8wNzywmcjANEQMNfMEq6ySKSzljrD9pfyuJT8eVDoLfVlzsro6IqtmIilUbuDI +04yS5hxAXi7NpsPJgdxxlbF6DEwwSv+gI5d4zBNTSkP5W5LU+IkQlcqNJsAn/WpMYsRpELH6Tpev +NJitZhRBzuQPJ2J3YV3IfPflfzfiIA+VWcin1RfAhDlqIeTVYDVeGnxd7GX2V5Xk8duIbpHW85sI +T0S62jjIvRb7UY0YqoAzsEZ3hgMkBJhT7wFbDA1GhgvgP9e6LhiSETCBCalob1MOfqBRI4gjd+qI +9dq0do0DpyUX0/GA4YmFm8E430YVRls9b6neos6xz6vvw1mUqb5RT47+K/tHAD81OydPZz4fhVhV +Flt2EiM/GNjWjmNAVgp5V85ltDyR8CBX4eY0ag0/JoWMMiXgAZHB0fUKyKdkR4KDIou2SXNsEoCf +CWLX9T9HI0no1zpt+sw6NzwkBpVcNCqk7VCFiOaItna0JNZjajZcgtL9NCiQXARyyeu/yl+ANBxV +po00pLoNOboajldxlhdy/pmKaKPwECLXJTQbqQRWktMqWmPspJMeW7yMS7hjvpWq9u5THhNsofiT +MCdiq5ez9JucMVtnfBU4cK7FYRNUygRzlfuU5O1cL+yfCvpt+HaJGqeUPnLkZF/VIsysINNt35fy +XseN2ok40LIYSF5Wa0K40vNVCLSyqzt8csGpwE06iukPi4zLGoMxjliobPaxcaM72IQVvRXocS0A +rbXsLqNrUrpE/jZyCYB6+Ryq8O+q0TOIILDrPs5VhUGX4THxeyZWKSvxeNw/wZNnT2HIoPAxzGPu +NSDltbV/zybpWInzGzVIy9+KboyZHqmn8GULzSSgu31YuXAnnWHU5dyByxfVCcYKCHtqC1v9oCK6 +gvY8ujlgBHdAOAYrWEBfC5vFhsldznBs9zuHMmPt32kLMjtVcE+D//g5HSr2X36aydDS+IfwOcqr +v0WvrbrDquX4FfPsp6wPax6zky12TzBcN1KH54feFHhNU7K+mNNINkD1aiokrfapxNEGO/XnO8NR +FeManrDueTaAUgewGJscKAkLnOuzrughwZ9k4G2RaIljodjD7XjNQivEozEevmvhiYlz0V5LZDsP +lGGe07OLhTF926HiWvldDPwqEJ4rken0LVkXqI4Dh19NQeikF/Ys/vYm+OoAJzdqPqtR2VhdV15t +4l4eP3BGH3yIFLO20vhkusD8xN9g+PEEDWQDRhunb/VaJfDUrWd2tdVCVxxhijRG8XCAABBqpGDm +pOQuUISZP9SjQTinEVsIiBoL8EN0h3YtT2jKAVN1xWBMbukFscb+O87KeV8MdOymwwJkS9R2Ldmg +HlXyrsopPhT8/nA8KulTTNCW0empHQZUCWEUnneIT+kUhKB8k9lHfvG9Yt/pW9LNGLKWkJq/J2F0 +HMYC6Zao79LOuKHZfZi7PmZUyT5Sk4MDx7dnIjgqUWyNd9YNr7qB1Iii3msNHTSgrYlLrixZwUBr +vaZX/4KDutyIqPibi3JNREhXOD9YzgVcu2RbrNcpX4kK+jO92M1nrTdU45CKqJUrrwWc2yzcCmJB +oy4vzaNomJKJ49uOK8uh5vPiI8DABk2Ky7c1CTpZ6BnX12ErMKmpLmrxCtQgkwemPal+ybctiVFP +RFisFRBijaBvN/JU9aFG9bVwoxToY3vwekeJzpeX86geRJkVYsA4WDRVz/t1JaYPrXzxY27Bcztd +3WPcCsPw7O5UtpnYlm2nf1rfQybWmfd+wLlDHsNGf4et61cnlEVIpabGxZjz0K07uobV5cuJgCoz +Qk+qEmnLifQU12CkLKxlQo4lVrzXrw+r0CEzY/4Jq6vODv4GjeqDZysUl5Rs/MhFP91KcbfTD9G3 +pUOEczoTNNljhmG6ZBjXFdW9W3eQPR3SZ76vJ1d914kCtAPNzbJBbDQpuL1CJv+CLIkUuKmQKywf +4ZT+92wA0pXKLRAL14L+jGPvD3BlJKOPjBRCOsmG+8lR37iS5/+oaOMgUUv5GsxTpsZqWsSr8Pu/ +ymrEDKBFpb1eiS4VMYc9Ke3YE7FUOVvssbrR5e+Du9foEWYFlh4x9y112pyYAQn7FQAcqgHyQEqw +LEsIcj7l/PBvoWk0IeFC97R5gWa3NbHQQAqwcK96QC5M5jjX6CC7rMP/Idac+Ru21TCQ7e8HV1Cf +UsmwyPGZacVbM3YUDUhG5OOOJ36ykq552k4tH/w7Qwu0gRaGf6u0+3wcdcDwgq6BJsg9eJgK08nN +7m73MEsjDW+Sqqpe8YfVNaRwYoYyRvtbgomjZNsirZAk3NTJ/4k91JTgWUgsrpBpAlAeB7AGTr/U +e1sSWbxfZB0edKJW+dJcIAPUWDJPpcKE/DCl0VdSrE6+R7CPznMpxxXYYbNFWNCfIRdztemD4jtC +1zWn3astlGiH9akKT5FVWvHLtFpiZJHcLV07Wfz1vU5Dor57MUz7CgTc9HPfxgQ/lAFpJ9YW1fJw +EgJt9EzF3FGLD0z5llI2SppXy6NJaUsmHvIjk3WuHUZiSqFyBQ7OeZkwIot8GeoQPrstwfBFz++r +/uFYGKld7sND75tWw/aqamlYBISavthHYorPUOM1EMZwO/V/eggBuncxWnco4TNPSEkzPy+6a4Ib +CWNPr04RvllA+8iD0u4zvSsKvtaGoB7LayRz3+cxRMXLnJjUs3yEqkGJQU+E8otClLZsd8wh3NR3 +PI3TBr181RpcnFzaIJCQ9Go2PVKQXI4nOuythOu4Hids+e28DM3EA3lGpr/v07FO3FuGLJWvPSg4 +/CTNlRKIjBr/P6bXLQ7zAXkwjjLBalpsHjksGnFEhmdZOPOAr3MnbCb5VEN4DCJAtOQ5BFvyxVJ7 +vKJhYrsaLX96pqc5vhjrj1nn8MI/fpQdz8/Y3/o8Jqn2J6QhY0Z667rPlxJhAI0guKrBOzZlcYXy +f9FJnrhSsR6ObAHFSOr3CSA67v6OfmUPePUh9HHwHnKjL/TswY2hsqTAjmnLXiXoqbkJhF9DneRm +q6yqNLhDOkewUoBbtTrw7/9Kzpc0xPUFi6UVMb6+XbsixrM3I0kEbO39SPX4w1tawNw6wytTG0DT +720ecdu2bw/ZyU5ApTWKbbukrrmrlEjp8f9m1IKJ0b1v+NbqIS678c1jKPwCOkShQ+59cjrbxKnA +CLdkI8yup0NAdAGfgBMtaKLZ52S/X7LWPVfzpcTSBYkCRX+iB6jM88boASlrz0QXbI0MY2aJY8Sk +YAcdKDuKv/ETKt2AtzMAFElofqrpQqHzAGeH3LAsfsJKBGx9rEjxy+JS1zP2Mr+K5sG9AysliC/1 +DpgyeqmzhzqUGI97HhrxsmZZLmcCFn+9Qvtsv7q96LCur6kdnWlxjgwBsBNtS2wN6JFOvNwFM1PE +Z294M3C/hv15Hvt6zpIJpkfDUMUI8bBBgWRCG9LUvx4+LYElKN3/zQyExOb5hvcYKzkaNO1o7bXK +DBRffAd+n0DfnUVOXxZi4MufT0G9E8gODalQKhz4y4yb3EdwcHipxE+eLjqDiBlbMjMfG8NUTU6m +1LTB4xuZx5fZZXNoqz2PjIp/lkQiNvSwZzzmIVvnkllp3uBjndVAY33KWi3rmD0G5YMJ1HDR8ze2 +jTVfARsErb8D8J+dw8daXwKXzKubkbllGUliW4hatf7+Lo3E/4xnEwRdHG4Fy6KfPVwZDnZZSLOE +4ZBecz8ko8OJkRyEvnhsu9KptI7G+O1zU1Faof6DD2b0VFtfiOXwGJgtkT8vNV85WcZmRl5Lqm3S +09tDn5RbhrFI8s7H0Hizhw0j2k8kkoEQ7eYwTHsm9Ul+6PzN2Pj+0MQOmjqsM71tO3v4yoqEC8f4 +QXaT4V4MxwddW0kYWZ9bYXFEYgdDkBVXiRze6BH+OwI4szvxvsgKUzRexrucprNxKPw7lWQnm3Ny +RUE93D71GUtabj2sPLcch24Wi4M3ukuQJLU/OZaJWfdXvXpd0bRiSm8+7ge7KdQ7LI+iEGS7020k +VvWvaHgY5KFrClAxWS53gII9JlDhozQ+KEMXaXvrA+f92GvbO583PzX1e/+mXrnZGpVNnFTsT4nk +FNAQ1tGl+7D5a3b4tYtNxzH3UUDtJEdv8iWaf7Gk2PKNQRg4qOCpS4h7MpX4wCf2S/m+4fhxhYZm +iS4Bw3siw1SiZI5nO/AkIcrtjWm4+xSnRt/iXp/bkd5RZQKyGvr+upOWXIgXytvAXKVt/U5kQGOK +aje8TLM//J76pMdmTIScEhm6eIamckzQvEQMQSl/Rp9NPtJhDjrP/txeyqHwlTP+wpsoV+E+OqhS +aHw3Cn5f+8nwD9K3uQm6paTIMw6Te/iI+wz1EDWhQOcpdjPFMnG6kwhpO5s/DY9DbFVQcZ/7tmMV +oqwFGY+woyKOospBsx49ugrW4I53EF2ku6EC/NoYNPHDWoOYBL/s35Dy1iTgE37fqXx6yHBQQhnm +n/X60901uVzOLRiK1v+D9UxiLduzzM95ooGspJkevR/X32Be5LCBLM8RBEu9E0MKXRQJR1NCmpXB +1vDyc8+PPPN5lp8kKl/n0jPXtE0dDa32Fo1yKNKBAx8PW1vFl8axCjCC+C7ORGRUY5RFaEicWh/P +UCqUK/bJbIPdIW4nR3qOrQXH22KKJftLpihDql1JCMDzS+POXQ6iewpNNDcVBzXGiZiR2kcxhMGa +lP5wyj9JKJ5kjbnEn3l348u3j9WHcjyi3wm+easnj3L60C3/1CctZHknSl47dRzU7WzTeOSVd+ip +AVsSUAJI4h2ZE0n1mH5RC4QwirtDMINjlv6PH9R24pSpxSyCKcd7+emrqYxdUOIJEnnP68SgB2qC +sRFYAGEJAfgEgmWNihX7nJuNdNgQsTFm2/ymIsXXLQm+KICkGxPojDPIuHY+Kot05tKxNxz4XTWN +ItzE7LD1DPOyOSVVeoQzmjOk1ns0LAtijcYA6HuNJiXIPELsA4nW3Mn6TFs5gTQFrVu8+9MhsJO1 +I37struDT3JF7u7Rwiypx312V3bhyVSIpaDQGHidskVGrAcijdaCQJL5FQp97zQa8ULlsSCLQUGR +0KcfiVgKkn97eXJbJcrffJZItXbApNWYqHE9K8xWHS3z4VWvCYK/hCgwPupFhHXPWCtZ9+5wWVbK +T85xbWzCJe0XxGQ89eiB4TX9voqZIySZdA3UghxsKbGM6kasnU86k3MSKaSi1o6MRSO1h3o/+Vfg +AuAS585WvUbSyMn3M1wVWq2x4LyEO8ovTg50Ok4OyWqlUMxAj+Dw3vrbYu4ioTMg1/H2ycJ8j1wC +AzpPoat2+/EUTARQxqnxUI5eAmGYyeXjLFrHLjrmnvOzpgiZPyqKXTApYY+qwUX6Dr/CQOdb3Iy1 +w7OEfqtNzqVcTcFuO0GsD4vbuupSwhXCSWb9Kmti3oP1vu34/f+ArBicknT8uQhKWjNzOdGM9kEl +pIH4aTZMpnthJgcTpHwsq7xnL7VkWdYJhmkhM4QUlH/hgRVleNhpc+Ouu/EoH/nlavGQ9AjjwkPY +LeNrTfd+mQQw7CahqFf6DE8A5iNrga3VLfJzaZvpNpVd85B0hv4rC/mj4sosrO3OJrTbpiTp2pka +Pyw9wyYx8YTembxtVyZeyJ5IfaqB1UAxpd/pW40Tldr22XNtcScfrH+i9VSGOTcwT0BCkcC3T6Ql +WiM8xph5BNHarIkrH0qlFJqQmXIMrGAjmlyFCHZ67B1hv5NrXn/PCRZ+H8Pfg8obpzjHUH7c52+a +mwEizc6lTdJeA8XI+NbF5Kf5bS24crIHn6vbhTZ7hvw5JuhtUUf2Li0zuuWEExJdXa0kHMIusYbp +HKDiphamV1RCpMqtHJL+9xTqxRD2Tyz/WUl8x0yU0Ey9Eg7zVQ1pFvz9Cy0QBDfGL1GRcpGOhekt +j8o1cQZy9d4UZIMGOdRqUDI825+ff/1V42rqABhGuPpv6Xynuj8FSCpOh9gzPCwH5l1f5OX1ZJ4V +/27G8GKzvchILCOpfbANykFqqossRQt/iifjMc4BAYBesJsxSI3qXQZVGk2GKfQGTuA/wsjz95RW +SUtZUv+3P6GBUVskzgWaI3ohTaDVUksIVL8T6cziC2isRBJ9SoLsM+3PWfSJcKgr3YkEl3ZXbYsI +bbZTK5XCo62NRLKQCkqxYV5g9MYMgWyX9KVfTT7RYoDGwIkPV2B4gvUyQNVg41aYMF1wEijgJd/9 +P3qGXqXQ5HV3D+vMQlQncZzuRaFC4NcjMoIYh8X/fUGl7KkEfa/ymaixUJ8itlvDDj1vQBILRzcP +Mw0Jnt4bsrHAARPL2PvBJ1DyC7GHtIt+ZGszDh3Zn6wthd4pZdl5IJuHSnMMN7C4EEVhyKJH4n2U +OANh35GbGf/xg2neZIHjYGW7kBN26iuc+y/JCax/fPqSI2BrSxRpywJFy8HGrFgBwB9LjSUVrnyM +8ZAT3AJA3jDq5Fpl4HjADAVQMVD18mCkhpFCNE3HxjC6D/ThDteQXs18B3FvvZOsB3anOKHxqUxI +58q34cwGooYOsa5L1+jwGJSNx0hwhb6x1v1NKMvz8X9/dJ6xTrB9Obita/aTFFMNiUbvQIag8xDp +1DJIKgJwKLT7Hw1WWEaVbdCN3/T4ceTDBnu2eAnGDdlZvU5bOdMWO4zOXiXQnFNEUG+kpN5UPxE/ +hcQTaZImSBdPd9ekn5WN1urI/uCNYT6Zf6C/UiW1gujsZTH7R8pjaLguJlnmlnJDOvJDVbSHDkEo +HopcahicGTGPxogDYgAmkbqDXOwlbM+C8CFtmTeHYBKhYWEw5UVRmnpYCY+TPkspvB6gvAVa2+rg +pqnWg6DUH8tCNkCOT+zad2fYJ54Njqd1PtH2Hk2W/eeDz/X2zheXBd/it5a1Ykt69Eq86E4sPnCD +G92OO+6I5EmgBzjL79DqH9rAMWZ6v/ViKRVw8EAGMSBvy+GVD+Z4ndSuMYIVyDlPHk85Y3rHs64B +CIUwenjgVdAlQ2bhcXvuj069jddmf5oifWJ/fz1sJk81I/8q0OhiXq+18yQhbpmOei0wwyCMBgcp +nAjR6SuLAxWJL/VCiVT7jg7DLYtb0L67fu771PJ9BRbbe7POt7zBinhCqlUBNYYjkm8zU226p+j6 ++FfvTBAnbfG+/FpXrEAKnRCRu09ebNh3X32Zzuy+mMyiBtlinFi+rn7j/JW8t25grKb3o1Lgz9lq +PifnX0FuczYFgu57cCLy7mlbw8aHcICWEKrfsiwS+Z3iN0l033AWeQo5qLtmNqzyiTMES3ESjMWv ++K4QMKwMH9yWPWvvkYdmdR9Ag0+YQiM6GXw7icu2GKbldV3Y5HVvho8JfQ/e57J0mmS/ZfNGjLen +m7NYrzEOwFT3Y6PRTS8roGt4j3zkpjoiSDD+Z98MQeCrJJE6yKSYRUCUVHLKnTxGuhOlZnPrixJa +nttLx9iDkv8+/Dws3uVVgMDon1fj94L3lYITK1vLyDiKbCtNgt+cLFJqmuxdVKLbuLbJYeWKAbkK +nDVuDslvV5nhKOpQgc2/cbdqa+N4+AD7M3MLCLME3f/qDIGD+rcmCOTZ9ZGdJWVwFOb48n50y5dq +kUCQfuN+aUNRbBwXIGHzobm3Yfrsex/erkaIwG9BVlop4D8M0PFpvXV5w9yYTNkfhtai4LKjjypb +F79on6xdoCc/9s2Z5H1W/2wTtKPhdHWrAvXhQYvpVHcCvZUzfCIHE0MITwuqqs473TxaxHPVyN8V +FtdYaVA0Pi4gpfk5MNh/wTmF5FQtJobg9gcEAs59Uk2ohSBvSO2pe8zTnMTn7uA9o7eWdK7rGovA +sYZ3ApAK8rFgDcKrHTtRedWzWSbE3QUOsBF+JRyJw8YlJDqQHoW2RXw7WHj9pcfAgeDnoq31Pwzf +dTacm9dzX/uDFKnMJhpP26Tgfw5ofyMiq17PsGrzHrQ2WvFTO57WjBa3erVmzM+Yb1So6HvgfyNv +fH02ZfL3o3hqFUUwl5PP2QssKmvYkoWeAjjC/yQfNU6pgqcxH3+kNVT1rmnJGhDBR488MmyF7PA6 +qeEl6+sO9gx7Z4rWtWlVnR0KWKwM4Wy1yB9dRkeAQXej81/P677z7T+LPVDhIxi48wUmq3MOy8V6 +1Jxs6CfPyhF72bUAgp1pn+xK8ttLJegPdwWpwFxgW7FiTJJEpxapEcVy1/F/psA+of95ey+jxcVa +WnSLdfwSfFkTgPhgdmGtPc8lnOcXK1bdpe18Cw1UttW7UU1Mg01j/aD0EatGfAG4DpcSoG7OVAnf +NgKiHbuHR2Mz0KwFbXP0kz6+ZwzZRECAOpB09XlOASuscY8pAqmqiXYT0YL3Dy2Ruo4iZcmOvo9r +2Ca/qfgouY2mMJ8h5u1ewMO1U9yU7rd5uu19+eFD18Fst243VfX3CuL1zAV+tAJbZsIo9PhQtdMK +PYt11WAXQJ4qBsz/Kj6f2jNsxayBv8uZ3iTlxNKbbDI7ALpWpCh7yzJY5vlaku65JJrHjrVtFDgV +eGE9UvGwxs37IEBqDupPvUNRL2UBodYzeEMLlptV48q6UxjBwQY5Lr2IkrF/sGJ45fU7fiY7MS/v +DmJSbIgYcjoFuVkXpnxW69xwmFiJ7hSAwhwVOR08roLkLmPXmzHi1AmIySfxGtZjFd81r0+7cWwc +/Bd8NHLFlwf561/xnIeaIktPG9ty7yfeqz/72fUp6XMdZHyiIqkIJbU03QmknGtEyEIKAQVsROjJ +SRvkOfiHG4wcGD/VFCFxdKuyctYkM/WJ/dujgkEc672nj6hTotO0miS+EYT+MidmMUmNhtYFkxEz +YG6004BsGp6su9tkQQ4bnd7hghFoZ1hrXqtzalKAvBpp62KSBetb1MZq1OlAuFjhJsY+yyx9nqRe +knNwiHinRKccc2SUu+Dig7raZfqsfuO3RJQWuJEZS8NgxNCx/DyYnUhekXGttCmDBBDY1NzrxlUM +MuU14Hx+ilq98Yve+ys2kWyzU5jZwMbPSy/Rm77sNtAanTlg5Ru3lLTpQpoSzSAOyFr6iL/S3w/b +jL03tcTqL0GJFWuKtfTAXN2FM1iULfBenVhaw7FUV9PLtalsQqYb3pruj5HMFdihbDk3kjkVdVyd +lw4F963dMXWhvvPW5dBiH0z8ADWB/aDz4BcFtFW2oMcL7uT3pnVXVEXueZkjB644MRq8Em0MznGo +uuVSvele7FPYWihjX1IebLAmp2BYmAeFJDKthjtxBfSfwdqbHro8umnLa0IP0SGWgvUa7YIvf8kU +6OQcETiZ3HOJ5jXiDSlxvTg7+EvRKLded+dmtLfdvTXIftBAJLfeTv65yyqt87hD2JyYYptnlGYU +JK+/QH/ZAo2gH7oUTV0lgp6Bt+cW4N1ITqITNYV+Ju1oOOW4LBWm9SH+WvTUEMEHL5UG41gWUuhr +XAdbdpu4oFgMwLtGDeHuSmM8Ny472zLdOuSoDOQiMQVgCv8w5kMxc42tPhJnL9sJDWZsEUmmU7Sr +FH6wsGFHV8fdegSMYbp7BTv1MzJxjVdxKLYd+W8jqWyUFt0fJ7+gjEea0efwAxEWeSx+QAB6b1Vv +RjD13JwqowSMbVdBJYRllL1u4lmP3vTCjgxnwmiN4E/1Bd55uY3uSFcYZzofnC/vU97K0f/niDbb +saTUV2UxXY1t/z6rBiIwShu21icGVwczNhf5EgirtoXMtA32O3dn/cUL4IcpYAGQBwGA2amrHOuz +r4LW7eR6J42bhdYxGcdDMpfaI1I2ExYdzROwwJPHFWB1/Ywy8hcWV6Y/4tT3y107wjK/p2yIOCsI +5e7hdkV8PAPpGyorcv+gwgUYtC0FvZ2uIAjkELnY3GWuQPD594F82HOgUHTkTBKIA+7XZiF30yje +I72hvdAP6lOb2WoWXHIcTNT+/IPCGvgZ6hVwP2dd02ALjTrEjR/ZOFwM7GjZisQroiBUPT/fPo25 +l3iORdv9vC4dK2DR7G5sG8IbWLYAfaKFWgSSlxV5Ag8ZrA5kp5Y65GAVT+CUfErRNwbFU/8Dojxs +g8rTiPzrdC2pVz2+IjIKmH9ROOu4FfOzxyjHoE/6QYOyFmuz7Ra8Fsa2kLJhWji+TzkoGczSSp5r +PsP6pNiRYqNTZhBddXFtAiYSx5KkZhrQ9HjCoyUl+mLpHegiGvK6HUbelzsVkkhgErYeHcPMvRhv +rDmU17xrxFccgD+ha7druFd5m2cK4biSpV4KUAdC6yHgwzvfn+uoY4K6Qohgm00WiBdPfNK6gqND +FS9vaaik9YIKJQ6gJwm29TndGfxpbUuwamce4QeTneSgWQ16VQ9I2cWMJZCvW9rpJEkgjfMrY5Eh +ghm6rNZ5FyRxScIKPrCi7TGNQjv0mwEQ/UsauEtZHrk4/1XBnhoQb+YeES1k5f/Hc//0pLGoLorw +AsE5GbVQbdc0ziDPLt5NCH2ScjRvfPJS3aig7b1sWBwyUDt3MMqEBRQ3RkP32LyYZVqecU0fp5Xv +nNPpysi8nLcCNMDvpgEnu8u0t99GGRcJhRDBGZ5hfbunH5A32SxF722JpCFZNjR3Kd9O4ASyfMob +G6eYsgPEyUgnGO+9uKJzIkGCJUqrJmf9WvRcr6kO/WeebOYJqJ76DwIj2HWpaxQTihkPQDAi+1mL +5VEmHZy5KBEb6YM5bsa35PgSGhaEHljvGDpwsqw79P67aTQXhRqbnwdap8TSxEVTDf7nXQGX1I6/ +yEYqo6a8o9XjaM5nJRNxaSBXViV38SItZEksYyGqhgMz5g2pQQAs5UfYMzd6xLWb1GwSwzO6DaMU +V0kovjfxhAbsGdAnPjEsNZqoXQ1S/swttQOtQ1USn4YpV0We6lnbYPWpxGv5aAiuyfmcH5rYpAAc +Cn+nQz+kPZgbVEcj6IMOivQbQwPper0F+PG/vyJh8VrBCcmhMkAZrg+dYXl3rn4tztrdE4MnCPHc +OOr8PsJwO4wwcEeMelnPjiCsE1gcMQ3HO9Y/0DCO8/BfYCBv/trWpa150yq4xLT1l17NFJV//3XF +JLsxxw1OJjGBbIMfkQvbjgnSHwbrrm5c7X0DB6rFdaxQc/jAKRbzVC/by/DPfZQJmQ2EsF16jgP4 +Jzkz0J3ULGhddtfn+eU9FKHzWI2yE1YAzUin5KDKzfmXa/wZIoBMxc95vyXfwewoGHc9A2QrsCzf +HlPdMOSkIKFwbMHwsADwADgoTj3cnz699V8zPYmvrNgH5+VeBIQhqSyW4s/4z/JtO1bB77rOUKBK +EUk97zQoR6313v9ZWxpTzHKh6PpNegsLxe1/uMTmfMRd2SfFcuZDpaG/eMozic6AuxvVohvpzTF/ +zV8+/JPf4UVVNA+DCkfTpsFXkXKeAylIV7tvtA0PxGVoN4ZvV/BJ8LFN/ZR7SXz4BEvdMHmIgvEA +vBqb4D245yUFH/9CoMSmlEKExI8jrjpB1kxYd7f406cjkGcNEbPRFgNECu5bzBlM+CyVNgq1CfZY ++tABFjEls3q7/gvGGinoVEjzQHeCIVnFuYflqSBtBnC3FYIssfy3cVY5kY4cjOijoQ1H2ZEEjhr3 +fNoAa33w1CMUeBOGaLZbjThYRGh1oxqPIrTPj1mjWwxZLO5Lkj3OSYRYs0NnHiEG2J9gBI3JKycO +EOjC/yJ5xNMhSMgMeKsMruQSuZQ2hbYIsXRGcQ8Wv9w7V5x2+QTzYCsddlxaBUYmBG1S9ildJv/b +IjLYk79tkN+SRylwCa74ogeDe01lsWqaE6pb+lzS7siNfzTdrcgcQDmfHg5sC9yTk1lBNjMPDLPs +SFmJFMis4waoBomi4DRR1WgA+d7NfeaT1IPg6adF7EZgEjZuRRwnaRvl6ynVi8eA42dPksBXWawz +LbHRw8hOeFXwWO5z2Tij9Sn9AVuEA9LydyrGgrrYEzHqhMGtX9UVLEXNJ6nGRVaZfUo7YRvcGld2 +GIT73WUg71ANkZIrWwostyUTSl24Mdl0ScRlXu0hrYA25YtB9plHwVUX3jm5ufKcZLHuLAgJU2fS +fduIX1hOWZ/onOrjI9NCguXkRxddLE2yWmB5L1nJU3KEEf74ntaUOMlyhfwMB+urt292aiHTSa3a +KtXirjZqSm4qgq6mEBQNPwIHUcm4TvFt8FhfmV33SPp3Hb2qX4yG5ZEsKHe59rePe9DA2ooRTrK1 +ifeGibNR3uXf3VV96sV95hkEIhTbxmevj/xcr21HeZxYHtoVyDFkCAltVYXQRCncyMu/dR4o7PBT +vQtryKtzqKNuCahtyTGHF46yCse6zVR8XFHfAVJQIlqQpxIRt8H8BRPWdU9OrXgjSny3ocaW5Bws +Xpu80pJFDJjGBlElgN421OQ/KhnihEmMdGcArBMm1Y2z0p7pTnTz4bt7Th31Atk9uwNvcSYWQRgQ +S0eaS59vu0kqnO0I7PgXII2PyDRPYRYEPcr37CPLlhxY32WCG+i6i3MpAznrTsX5KrCfjBguG10e +2y+SurekhNuHon0roGvRNPSMyPuLZ7F62umfv+HrEOosRiCXQbu++OXHGU0LyJPurdDOtTMrwm3D +rFo9y+y0YnXj0lNlDg9eThFholpclXtnQqJqFJyB6Mm5LHr28ozrok0s8UZqBm7ZqZhvDN6lXAeb +k99xIelPxYfD77vJu+mQJ6jSlGegljWzBzF60zcEjWzu7jgmGl5seGDV8Q5kg6ibvN7C49pFIY3z +jd4BD1sJgLATtUn3P3kplrFOqDMw/Rnn8kMqzjfV4H9Pjyjuf8WCCdnQWbSM3O53I8JXd1XrAUMn +AadkE789Qg6ooKZC6V36NzVb5XWf1UWcph9o7GgT52unhCTY6VVflfc5iPSIjW+U+Civ+gQvRfpM +MdtAa5M0ayhvlp9+1b/U3neFuecmhnAjTfLiYddIgQUYlf+sGmLuKjT7f5hzeytWxRfzFDZoHyda +hFhUTczxGm+o62E8/jER8LVLTxvG3xHuNAPnYqSzdERnHSUWLJgZdCb5G88V9f49qYr5YP2JfayL +3WLc2ZOD1DyJATc/239hoVzgKxp7GO1EGEuKFfXy/ZhqM32UDwVimVQh7h+yghoiw4+QFFhCmyVt +TxdeA8AaKhMnujzwmrkwc8KvD+4cXlSkokf/1HyQ4OAkl2xkz+xvberaab2XBRjN3YyiGdW7mC3A +PWJnDU9AY5Rvkp7FGYzfCZNFc7Q2gB7CDS1dtSydInK6ej3naiXvl43hiKlYvBFJbepP5Zfi0jeI +2vpH1SX6/9bgVSTjaJG0yLzWBJQc4/g+3cV8Atyyz5oGYnJMg7y+ndTf48nL+3UxDB2cnG7S/kKf +Ncd9iAh1LLKv122ZEKydkBgBU7w7xqNbzLn6Hvy7IfyGBrXxSdJBZmo4MMAgtyV+pH8+b7Dt+rnS +H2PE3isxmQL6xANeStewJD0LpjU423mgKB1W/jGFdfGzjJJytld/Nx5I59PmzTpU8rOWV0O7BJTs +A440qNdNb4sjqXEmBDYgQbUb4pd4x8ISSavIP4CY4ohawrKmhL6DSFFXx5WE8tzAdJHIJr9XnQP/ +Lf9ud9BtxsAB7I6ae7jXcVHqu1hmMGaxUSWyI2OyI//uObKCs6bESXnnOYvge9my3BLAtzxj9yuH +Pytpc4PujU/0GGaTy2JGraoc/shCOK9JLn3p3I2/LX079+K3xNilPS7nYXrEmB/AMkUcQ+2UZ4wS +fCYHvyEMymUeQ5eIxkny1pmCvlQEoE1zKziT3zL3qU7AoPQo4dr6OXfl/ivIkfZJEQbDnmw2ZgN3 +Ye0HmsupYM2AYnExzjSGhm4sOL9ac3ApAkVmCOM2P0wuwfMeO/dHJc/s9Zf29tVCkl6ShQ0sbsVy +fxfMcY/DSZL4z12k4Hj70Dm9CIB4SCe2XcHsj2KEmIEkOQwAUePHnLYv8/MJQNlBRu1haulH/OPR +4djIYffYGlekKIcLGJ/SDobxgHvL7FChOzk+r5xD77LIxHWMjZ/0sOxawhKThv2GThhuqTtNCQ/s +1tyZoeDOZLiQhVjOYbt6XgYanFNiGqBQMvwCWw9NU9mkleWpxodY9cv2ezswt3LCOKaa483zfFQG +EDghi8F/cJo0cHC073e1+FgqV24JyY47DpqzMsExcf0LDagvTLqxTf3gcizdKKU31KR4TdYuqgjl +b5EXAgVmufK/RCB6hAzyBZVs/gDIl6dpC5PCHOTncPRzFWbDHydyoyz8b4BHcS395UbmZBdwgpj1 +afJaC39mT9phjzt5VVcE5OVXc8kWC/wE4tgFhiS551JF4UK0LGExsO5nbSmpQ0Fd6Nyt22VqmURy +Qr9Xw+7Dqf71nOcGBJhXfqCT0l+dKC7B4ykW6g2b84qeoTPHGIkusW2PjxfHHhKhhLDjql4/qlSJ +ICCe0OP/hQl1H4PcQmKrEOsf5hRyJAoedWMkhuV5qalAa4/Cmxj9Xisr1ukj+UyNOXZGWNGOptVd +xAFAjl8Zf4qioBu1NUotG7Ykj3Qs7BNUWNe9k6uDOYSIQu580qc1YaF0JlVDqUKXHk4hzBQ5R+F4 +JFYDsr7Dnu6Xtngp0LvfGZl0IG3Vh6O704E6J6l/g5xcUFgZKDlgpcXc/q00fa/SAFWYfzFQjl58 +Er1jjhfcGNjmSozLlsdpabZeJqIpp7X8CevOK56RbNEch/mmzNh/wd5Up0/ruDRmDatGEXXw+lQ6 +y6yE8l6xuy8WZac+2QZo/DGSLxRfadSXCRT1OgkDok0gXfu2IfaVs2LoEMqwNMHV5fGZlcJ6v1Ck +AZp+u1LfO4DmcB9R4H3ade1oI/69KdJoqBi7VdaIBcKel2YwqOCYVRo+jXHi58a2gBOjY3FB9zXL +8uYNLqk6g0thhE4drcKrgIdNt0sqauAzrAsvlbXvwhJdHbrkyPBbNa4QkxPsNtvOf27Cbhe+5TvI +ReqIdioQNtV6koyVONyRkKXbUQol417TfoaHgoay96ptI05satNuAjyOY8MMuW9ngpi7SJNPEzxs +87OmQbAj4y4mBHmLwZ8o1mQCybVkSg0yv0VCQaeKG/obKxRk9aSXgeT/RCdIMsAA8bXcnSUIW6cz +fObnWTzOJIwZIrIf5y2mjGUg9fuILHnZY0lChIZV/eEPljeFL5PlYBM9xan2TIuR5CHcxikZ0+zy +RnTc6/byNYlYk5VCmaXt50gvGsYuOXZ+QPo3ZZhJnizguW+HghA/XkVENRmFtTp8WMsscQLDaVCf +YlWqXCN8N8V4g0cqo8fjqmG5NKhBbthmeK4LA7VhyexdCbknKSLM0MdvZztLxULhjPv7ltTWtyv5 +HyxR2HwZde26Y/NxQgL0fs+9MZSjt3fOiIVV2HVIe9umbXfXan1+gkL8hs1bPFtkBsSEgbgfrfMq +FnD5H6zG1n/fP3l413Y7MpijzHk7r3eS94miD2Tdysi3188+E0RJbQ6b0cSKeGFDZZw2+hnPHGuz +NbNrMzfOkkrbbvSGFjfdUhAoZyASAz/objezVVSO92xNwkq2JG0Ovib8cTeh1wIvkJFMFtyTRJlR +LZV5b6+ow+dkAGBlLkQKaMkn2m1Q7ANgWnMKBBNB/ErOgug7g0h9Jv8gXxQ2zs8XwiRbdo60fndZ +I/AT3C2rqd9s5GRPcCaE8JbkKMNtqTfH9/LDIKP4u9yqm5t/LG/OEt29EaTLBQACMHzu4ANNPp3c +NBBoTxudzwgfMevE1Ol4Zlkl8gi6k3B7BctYrMoYn7KYXXOR/qDJN3O7qlpo/9PweKn+mHutblPF +6lD1AsJpi1+IUE6N+5cWSXf2u59iFtgOMdauSdLY+yztNCcc6Jhr440hXL9h3PaDIUmXMp2xZPQD +fwBSOOXivYtoR3jqgkGnuqKvYya/p3O7FHs1cXYX2pOO+LezjYec5IxpQS5PbWYgEa9k7j2+ab5+ +KCo+z3vho7NG5pWwbchVtG5uSFixImcVu+SXMOj19lK46byWuqODVHVrBNrV0Pev+QyDS9TapFIa +DO7/MZ7wE9YAdEJjhhzxrfReturLgV0uK1A8k9bzX2IWhjyWxMpxxYqaeZvo/qwlaNpR8LK00lpS +SL+h5FLRx4ExBE/15B4LvlmxzXDZ4dZCYIxLhxvLTpTBrjL80FnU22BXqho/Dq4z63Yt7AO8KBbZ +KbGwX800cipm53KJzwS7mbcpA6unggYCB2yDzElr6kOSCN1ujnt4tGjUMfqrcSKXzZblXvYONGv6 +jOEUnzhkBO72QYKl7HjX9+JPA/l8i61fyZhmDmnY4+3Jqv2w13GCrpI1mYWQTLLTTMiFLPPvhaIU +CENOa+xuBiq0jHN+o796o4mFjIF9yC7oW1HPER32PGyCLWRufUm1O4e1O8fNTsklhyP8GhwH9lLi +3KpNkI6e48zfdRapntzt6eX0bhInT3HlOPc16H1sXzSeD2mTfhEV8F7P+aoikE2V6IqrXlq5+t1p +gwzIiFmg+h/Z+7M6c8n6GZoepliLC5X9CTw6C7+za5+QK9f7evDpvFNRdV+gjLik4Jz+1i2wfUaE +kr4Cjx/PY0MDZvk76iKt0VeNlagFLdecnThSE/I9bDAJvwandzBhdOzpMD5k/ZtTqWD9mUVnfvL9 +wZu37Wqtn4sAlAyqPIrFvy51U601jjLAkfZIrg7pmMmawomJY0U00FZxGjz6edfkzwfu0z44xQmT +jzSyf++MNAEhXZOyqdjr9x0FrfnVuIOEk57S/tQ4BSAqCflk33IowdEG463fSBLO0kfmQZ/Ap5LP +GfDzwMjQlxa3LObRsx08d2bzBWjq7tcrT4SRv8lbqu1Ewd0VFTLJFMWRFw1ThKonLdOnY7qU/dAZ +ARDK2wv6n5mkv/7F4zGWDFmZcKZeJISNXfIDKxi08TeLtLGYJ5YjHE764usT1m31W/ogP87LNli1 +izwxS7Vfq/CeweF5deOVAh/j9LTuxYKSb+n/xXPXwRYO81+ikzlIZG449P/7RmqnTNTH7BFC/tsd +gFn0mJSy1oYdzKd+S+Ok0NRyw73tOXFfGlbfB83nrfHCFA5zOgJAxPtdanlUndE/nT0xLIMQS7V9 +vmjsoSBUHRPm8dDoFxD9B+zGQaOBTP2Y2JDDUb+6VWn1GnDNV8Xl6WdtTrUKBulLpKLClw5ApbLH +fWqzs04WA8ET8nIxv7APQm48K/pndhy03SWRnkolarPBgoFRUmOX3/7toNol9DkjT3h5sVKQiKtM +ZjlQedDxza58b2zrP+XCVNcOTVzPa1XSkVJhd4VMBjmK/TE5AVIrMwlSwag22BKsi94k4wczMrIh +W5Uo1eBWp5Qcu1+hiSXdp+1inJeI4q9TUUEqDP1ohn0Ln5Cy4+Pu/QZKfQiPdDvWfFtAyOMk4OvS +5h5FyiLnM7A41ZF5WtdlwD4aIy6PUO6hH7b8FCsrwEaNBo8SRMcpYfpEGWW7+M7p8YMDa1KKdk3H +p9PJKQwd+H9F87BBx22ByUdoKILcbropU/kZTpgeNESEnYeF3s5OCxN95h2+bvn9mIkuzFAwozpN +rSCVy6/2a8t4ODmw+oDCBeDEITMcEIAQ1/8/7a2jjdEJBiozcfrMGYp249v+OpCEkZeXc/ak9tDg +04t8jbYO2nW/74DbP8bsjplHgLaTulA0jU5kKaPbIiavcXLI8lXNdHObnK3tNvAMkpXRf50Q+nxR +iiELNn9OEyhdaaaRmy8gC2pEMypVIDDfoVOlbkkXFelRUhPzF1/dw9hlbyG3kITZKo0Tm2/sHmKC +icJL9eQ89YRRl2yCvNN95Mx9tj4thup7XXhrd+9ga2/GMpplgMdznrcAheLyGz5Y31z5vY57c+BM +A5LngYUbFW3tn4Cbo2dyYyRUszNVUYCYkUUfC0kywqyqSmCb2CWhzkR/1Bn1P0RjTu2+8+pNUSdM +3y4VZC0vBNF1A6pCRMucR7in0yB/riA5aNP9wSrDd/46o/PanAckf/So1HEH/9nFFJVSji/xo8DT +SMmWKtswH3Pe5PXz2mYeFRC20nub/E0tSjAEZaWpmIQvOkX7cWWzT7EkowOSG77Y+pj3n9nANSjl +xtH77jWf5GSGKbh82kKpytCna1qUfNE2y9bMLbbisnLuF/5MwM10rtLNhF9s341AN5RF/Fk4hAo8 +d9tVlHkz3g9XEeMRitthDSJgJl/zxcq09Dm6TLQ5sopef1G6u5rnd0yFv8Yq3/C/j8CEeeeWoPPP +LwZKiKRa0ur7rwxI5pFtUk/KnjVpBABzE8DS1suE1ulIjoHR9TGbDnyRKIVaxgvi+b0ELto5SN5X +iJEwgPfzY8+GeMtS5+1w6QEn5m8Z+3f1GzPc/39WUOWRrNoTxnWIruiK5p9yaf5/3reNYJlZHmUE +74thmkOP6+XGvAqvEk4TadqDchbg0ZOwHlK/jjMI6lOhqFZLLbRL32eu3S+tm2YjDw7OvreT8RCp +URLrL1nYDG0uHeY4fupI6mgksSeiQdlapYdhf4Di94wzG/sfJDq38J3diqn83e2reHy0BK5aDpDv +bbDWJX1pmJJO9K+xVcvuO1X1H2lUjJhcQqDrD7BBcSIL81Ut4HX9ds6ilt53UV+dbrtiqGlYIiZB +Bix2fdmCYjEKFJsMfppUwbuEfFGJ0iCgCT0FeBpf9Tu2PrJ4BgjVYBAL4L8A4bHP0MPuFCe0BOJh +sXD/qJtBidU1V3xsrHEcP3P6bQei42wxMldeKkvGQtnAMo4eoS9yerBDOG6EgEfT7/ehBkoaWJVg +64E0kR71HsjY0wC1y6S4MOWzDCXkZRrCiADbcrnThHakAQbbYGbmo40PpTzMUiqvfoKp9PxTXMsi +PcY2/ZxpHoN9+0b75ZH6aUff60rs0/XAAV6oX3yoYA5spXGXuryXDrLqjIhQ1MNfaCc6H9J+yQMz +7yf9e86ygshu9WeXyHGsfxvyLCA1eD7dvu3zHEp/hlG8XhlTUAf4fZD9GjVXbMJhGEav61t3wzhV +SgH7zS8i+LABWoRk1f7WiBgwNzgvJK3w49+bHj5hftfGifXQP3zIhQcp5YzAYRDkhJCbvCmfm4J7 +iq1DhgFXNdIQ2XNlUqct8PVtN7/vV+Odh4xd6a/a5+FhZd55F8tU9uepE6BJnIVERpsttt/G8uXq +cm09SE8Jak5TBPqIztTbvfxykNtoMO9F+SqHmM2ENeh9wKwr88iIYR93mN3aMAwOA4evhAKr8fX/ +38i8nwgZv01j+XtV28bfDEm6E03Wte2H24suBpfov1YOqUKMp/kruY89/zJQwNS2FkwtfqUuMX8a +8crzMR8l0uxcbcsjYdtYR0AEjH7ZuSBuPFMKyuZZgwLAM9/XCEJIKJw2nLWv9RNb2dayuuIiX6CX +bX9YgPnjAVFtKmkDeDcdydctdSxKr5+s9pdMNeHGL1YoY36Y6Mi1pM1n7t62PKsxYqjRfNZZWJ71 +SYpH2Zd4Nkyn9B10zWPz0MVgI2weoONHN/99SMmxkvA+gPavjzckVp8bm2Ax+g2T6J362Wcx/2MB +GtRDDzgt09fTJlgPiom+bS0ozpEZDw2scnhZsvXPRZJQabKps+Pqq8pDYutgTvkuwS0llvRfU4hF +69YEq4x1yJj/Zt4i3IylnsqEZjgQGEj86S8CFSz06BMW+WtcXQ2/hp5e9pfAMK8ncHKcsv20lCXJ +oBIWMdEFV579JLDyLpp5iIol95OV0tLOZ47q1O0fo8QyJnL2lQG2WLxzzmbdYaSJjNZCy9pI+DyN +vYb8vAOARoRJFVE7AA/THi11PpBmX8+PrVALNSqOi+V96ZnCLlgg97bpBulI+NqHNObl0GN2GydY +OgeyBn1A+ol0HqZHxexM31Zlos/XOiwl/FgLY3L+xNijCYyRr1UdZG4sys5W6/SlmY0orIbgKt6k +Rsaw33cuUAaEP7NNSmIQrj2O/+dzB+CeetFgcjpDeU5CREe/kw+Nn4oLRNHGY3iVs0yzKxIFu4te +h9wjXHYsVZyzl3+2T84SBzKMw2QBCm6qD2KJpb/UAszSLfMEhMIJhOVQ4xSqUcRGyjLXRbrnMTIe +gCq8tSjHqC8kad1o6PiP6Zc6xbw/o1VdCSnHAUZMFEYnIWAvZDDxrWdzfoczVpY87IYVRQQxuS4F +7PCxgqm5IMb1NEt6NhWEPxqxFA/0Xc4O9rlIwBzH1s6FAh7SncFUxq5TIUqk2RrGz28XwDEmZ9zu +8iAVbXXJEK7ijTAqpX2vggnlE8UhMfh33LERQgX8IAQAuHHzDWYxLcfJrqXwpm9nF0+bweOMYGSp +W22x8isDMIZD7pbSto0MR3h3DLym2E9pF1vV3IGNcc2y5BguZ8G9M+s2t4K0TVdA4OdRU32DXXGr +mVMIQ3tjghNM9+yIqr120GU9HTb3SU2ZtoNO0mQ4GPFoQux/REaEHyK2slrCjR143rK6lQgzhGH5 +Nn/Uy5GOM8MVUEwnOX7CTK7wlioaPwSShRlmWNoFANMY/ofwLwL941nAm3RGxAyNKjq6MW7dM7lP +bR6W2VTaCatZLMvNvV3EXklTRVE4HkDUvEJL6xEokFmVxdIC2sSL9cH1uAOVM9f5MYB+EYnvUidy +0ZeYWy0iC1BXa3S1tT9fgjrYT5JJJItOINE1K02LXerYg7gRAORn2D8Ras9yVEIRPfUqqRipq24W +NWkAY2RTgOIZPW3iX36vLw8klvmKg+X/Rq8Dgdk1w51dqcDjyXx+svie9z/mptiwd94V3/r6tNKd +oL860Vt5K1+iu4wDD+kIJIvQkUYv1oIZv2P6+a20UklBWIEsV9tV7rKXr4gOFFDP7mNdjdzaKpAS +UI2RvugFw6FSlWTfP6emCiB9EEZMHj+ykA4h7oCGbCR2gTyq35fyfQUXqq51a/W00C1qgHNC30uo ++F7B124TMkojBZ7VJbdvLLRdfaCyUCAgQ5bCHlAAhcjDG0/By1WkUGPuWed64wmD0/bbnYjl2UcI +CuIo80hqmEDsP0CBMVlGJCj6tPHBn8PbVLveUyJFjztDD5JZc7ekwN63QKI1TA0gzxmoFHUg7kNe +sP+Vh7x5iSfwtz7BP1O2uqi0Gbkoq9Ky2Qdf0FWkse0h1RANu69J71VXE4J32l3AxLxpN03Owbdo +UvVBVrwgqhGu69hLdxpzAa4lXLEk563ryrDqJy6Et9rtt5lwsMnXLNgfx5LFTqiPxLIDyv+FcDid +G3NiNJ+PEMnpZezR24xPIt90l/dOieJM//caVfJWbS5CnvtPkTOeq+2pwFDibRvwjVZD/H+VxLqK +w37Zusu4CpPhHKCeUryaigpFZi2thXZAyPmLKFvxlV+MJubo1gB5FXSiTPv1MAgGvnIAjWBsG/ye +zEajmGd7z69oGe5mOSnKHf6tBcnCVHXEMUkkF1CAI3WsuKD4f+VeO+atjr9ACDNsEP+uLvzJBe2W +a0tfCf7Ni7CTbfarVfPK25pynmf0Nf49+kGTlRvljcP2HVs+KuZU3+cTPm4zJJgJBSRM9AhYt9j6 +zdkFkmnYOCj37wrexbqC0a2F6lzdO7J0Xb7Ha7F/KITjPDU4hSa17lpjGGMxyqPRbqSWzVb2iPB2 +2132NolCSTPkSlAvaq/AklQq/9IFu1yAFP5aZsLEc6gEYBEzTY0fo1N6EcPvH6LjtbA7hMUuNtoy +8qFJBK2VawtxULuBj0PXhxSItKkbPgofUkrhdcE/QHxX0OPYA64cq1eFOrVjG0tZ4F1zqFjQTp1z +Fkb37/3aMdIeDNXkEm19wEUVWXmoMWrz00JmdkWT1gSaJ7g4E1CMK3P7ZGDwhyFIhvL6l10deevz +uSVbZzl6DBn2DSXZuQ3LFQakSzstGcK/oKXF1Cfu0mTctU8x7FMcAtTHbgg0lDRXZ30ODg3cNoZ6 +0VyGThHrOQLY0UsqZ9/0jlFl6s9/5VkqgoeUSvSFnoKCJ/K2x0l3Cx9Sj7kCAurmYov6/ovdKJjG +JIYstmPi2pjGNGCJ8qLMai4WCJnkdfHlvKU7AO7ANHe6qeWMU+99LeReoLm1JnjXyAkHJz5274VC +uEU74d1yPkyrmXOCMBCl2PokG/fSZ191woYjBqXK7665UP3wLHN4irINf8HCrbdRgRD2Av2Tacph +oIJrWlbMeRlOGL6CyQe5Ko3nMqQRZ3RN0JkXdt+Sm0mEYW6c+6hZpCRgyIKUfA2qtoLU3UPOaA+C +bFBSlEaKcpFbL434zKKK5+oW3AVw39RVO2fo22dHbkvr3YTCWAReanPeM18Qu0H5w8niCL7miTeP +gIBFJ6fEgFgqrvDBNsIueLXo0oGaclRL/+3+ABN+NPw5Ol+4Hov1+dNWSnSTpDpFhZ+lVPRtUtYR +AsluPqWDIL6xntv3O7oPPh2H7Ma9kvHoEIxAexyQ961hOWQcd1CBWaHPTS651SR3Qy9qPxcPG5PW +g1+QrYSiDAR47ufnyksgIbQIenFmrGK4Opkb7+I3xvbiqaG1LpkeVTNZI/rJd/ZmFc57iU58QEfv ++1orIEJr7wCGP5/PEj7c+YmKSA7kKFhcGHEEqgMTduw1vxgBzHv/UzE+bOYKcRpSD3XNPja9SfVE +3CQBHrWk6XtxHXoVu8P98Kem2vDhWnjvnmgSFcG5k4aHEVb0hvFsSv9oX0ZiFBksxo552Hgh7iO8 +hLuHPXCbITM5jk/Q2A8CZkoC6nsY2DoCB5UYpx/JujojL3T8CruOTx+H4fnq27hqNVvrFEncE9rD +vzzztMCRHfcSbnf0G3lfidCEAy8tEX8iRUzdjWlt2W/7aMo6/vhsa00ncYscotX0ubdGZ2YZ0QLS +BgpW0NkQkcu7NNTUA/ZvVzzj2UZ+WjbH+xqGDUhBJeBg/J3QbUNDv/2Y1QJDjOaiiCRnUhaAyzZu +BS16iTc6EAUWm/weGn69p4z287xR7IzLmN9dfEhW+XlWUy1O0GuSHOS1Af0OKtGuYD3fTuwKcrza +UC1uqhwms2A5a/GlD6HpfXOjYW2bv6WqcF7gvGdu1Pkj4cwh8U63Uc00evMgHwFfyDGxm9hOrGT5 +PD2RgtT3ejWyBU0tSWxdFAbRuu7px+nb3X2QOyFc+zvx3G2smSEvsG1+jIemReIIajt7ZHFuA3F0 +LRanTJIYd1rO2jgN8Bq6t9Wt/aBl/3LcTZ2Y6D7npWv8VhABncDfgGZq6ICq8dN9+BzTRQu7w4fi +Ue1JGqghKXGXyEk3sdhu+lYITjlvYoVpFDV/UCaj4GVVD4tvi6fiq5kBfP0Lb9HzOdNBc/vn20n/ +Q31kr8m1I2CNYiLlUKlVjCVnSqyx2ZP4cVfa81z9f6yosjPGlRa4WV4CjL76KuQf69PwBJ4w8YeI +lVjhKmqdeLGEKSrbt8puSxKOEZONIm0uF/X2B901lXrqxTcEImEWcjJx5FQL+qxpk03ALby+st3B +0bug1uA7OfIz1CMKvPKqeggpxclZcDkUFbufFyTQTHWiAimh1+f3zlD88kDWhrmPm3IDVqkOvbVt +cmidj7jAoE/09V3w8pJ2LC9blhEuGV0NZ3E5+tPC1CfVlII1pwOeqN8wEibPTKbedFmOaj+S0NBH +ZpN8+r9RJ+Etfh4RhMO/bBOMuD5NQTk64uosG0AU+tgJP7SmfnFc+mIIpDPW6fminnUFhKpcK2+c +2tk+LaaAw5vuJy5Ekqjhr8z973k4bjyZhGr24a01/pEOm5DrQDWZDN0xNmAxFa4x9piWE0vN1jVL +AGUa+DwZwEVNI0zBWUDWkFQxh3lRuyaRGggmk+50vpAHQj38VJBhmZz/r8uOmQ6DU0iFsAyu+Zwy +kzYEUoi/0Pf2iYpdzhjdECEOqW/4fHUwKf/+vHfZ6fMgoCmLzHphFB3I7NqQadmzdbbQbQh/wH0V +n97c2ZprB+Ew4RdcwmgAcW0nuWZ/+csxBmg6n14uB5fTJvRkNk8Ee41i33E0+aKVvNdkteHvu9Pr +oURY3wemXAs32zs36P5ft8h/7SXlKs5gTIV3Jj2DmwlIXi/ttbsmm87lL19nTtr+zxRuTaow1itU +dArszxgKGdsuSMlBSdFJqGpRq9RnH/379vGYASaFte5u/ScFvjO7L9Q+LhFsoxQpmnaMoVphAs1R +Eq7ZsG9ohMcruBMdpaQPBjEGmyGnqMyUpQCr4+10JHkJt6nMA12dmUNeIbBDDWwlvNt+Ajlir9s8 +OpLgu7P8CSl2KcpyfOmOAF/2Hu424IDWMPmsI2Kb/3wBB7NMHAxWMwXlmV53VtH1K4Ginp/637dz +9x923dXOUwxOj2oOTsoaGA19A5NSd5uJ3KeOMQoW2pdUZNsDDcSpcgsE3FBG4saav2FVUo2tabu/ +ganUBl9vQx6FEH/6cTQuGWDZOyIJsa/NtdkjMVqSfZdE8+UDtioTdrvnFCxAV5foWeuhuhUUs9lp +TcDOuqJJVejcGTBlsO9vp3QjxT3kVkZY01eRsoZxUE+6bD2S22tgPniU2/GoGmOwi9MidSquBfIG +/yG3xlIxJD1pK4ccjoaJIohuJYMShdBeQw1tUbct562Zr6QRyNGNup0tBRplaeIH7YG/ZUMMw7qb +B7D0y5SvQgwJSwl0A7qEU16j9cv1VF+eUuXbD7WSdIQCBpM6GRIzqSg78R7jHuYQZNggnI/vNW3X +GC9EaqPqLfuGDcnKCuluLGU8IZ8lGDTvR4pScC6/6MDQxcfUnHBGb1tfY1xP2r00TDGoa2vNwt2/ +kQSsKG7AHIyDANx55TRhT9+hHnLzI9dhgoPzBg+m3yYFjwQmye7Cy2NjTS+myEEZ2lqLr/5vgeDv +p7+KyKTSyj4gXa9xQWbdvAmDsjxRSBQ8gVnBZJ9EhQQlIWJofT7dEo7MzzmgIQ5ILQTA8G7pnpuG +dX2lwZrVLbBFrO5vAPDJU3ZBHtCFLqWgXTGtEZYnjmNCDlxupk920QDLNjLemD7l7SvFzAkTz+l9 +FXrNur84kvByec0BxMPMdBdIs5d6WuSSAqWqER8t/nXBYHfLWDfCtDB8aFENj7HBYqCKf5o0g0Zq ++lzcSyx2J3wdebmt/9zg4NLeC3UyqRlMAT5x4odPw8gyoSXBrzVQ9h1n+bnphAtUu3cJI/B/Q34T +8vkGKDvxEO5+xHJdNMeiN2CeY3u63mv9+I5o3LaPdhR383VMGIm2aNhyo152hpytUiyaN6J2ubk1 +AFrU98gmwbH14cRJ6KDsdqNpSSculaaoctz58bZU/spFb0TKJ5BJXed5ghR/D4LPr6HpAdemeShg +D9zGiicF+is26MzckbieMRPfSP8k0XnqDQ9IJE167/QVoaojS1FSkEdEGfzTTIrNO8JF/02E5iEf +UgDq23Moa+bB+m/U6IN5vLC3LG/1As2r2JgKCRn9wJanU4ZWIvKh+WsBHG4G6q/n04xdzxOQqYpe +vWHhr6d5HoU+BC9VVaf+UiFpJ7c42DbFQLPeRhuMrGO23jXjUdeJIcgUQu/A8BXl8YeRYDtZ7F0f +QKvi7whRUbAMrs0FvCKcxNfObSH3nu6y3Ey5jKfL02HydsoR9+FI/T3gRtrxEjsPcOB7ULA91HtA +qQQkUetm7ccZdJNlQUO+qhNYBM0g/TQwhaHz9RLbVEyJkaWfzxYdowMOYQPrQvVoNVSCeRIh2ONX +i3UC8JwjBdcDVBhG/9irYgsa1wmFQxMEQLf/OgPNrO1PiN8YGD3YxWeuU02soQ9U9JdKJ9SaQdUl ++iJbGnP4rvUNzWF7vQJxErZQWM2wMbQRfdtTH64o6Ccp0K9sgl6hbHljg6MJfdGxxDf49Izsa9tl +cDq8EGExm3mMekpPOVV8DXZ/UFjyFFRGJznLdVxiur0mAdG8ZbK5jkcvYs7l6XMGde6XNspsCHqM +QX49f3+uqUKwzNt26zTqb69Nm9OIY/ejL58lHrw0xNAmQ3IebcT5cHT/6A/bhjBkcecHMdgI5xBz +Yo/qfZ4J3Oe9m60ik0o1VbMFGZKpvlEXZFgu+/o9iNx8tTA+iGY8gtpKVjfNxgJy3AyfbCh76Wjv +kHDY4hPIHvdE6ksuGqQkiJ4GtLsEFQN9vh7w9AI+XFAI7oEcvNnJN/JEsUoeYonB+YAVqce8U9La +xORA61myN/IiyRPBQEXo70VN2deb5hsWcPs/GNlb0FSbA3HZn6FOkFhkppPYDvRb3j7pPBAN4k7A +YexmejYLFZmjH6hOETZleaoh+np/WIaZ2yFXHF9jyQwjYU51OuK0VnB6V92pHSlqYYWpJw7Ax4mX +nkf6WHg8lRvrDrWX6fe6kSWG16n6o0H8bRpgQwYcy/x4JRPuqH+kjoV5jnSnYxSinerGBtKj5ps5 +pWn0tyI2MkHKrfojz/BWjrDRdP2b6L2o913cIgo3wSa5OYnxdZRiAWOktSSaoVoFZKq+NIGAe7rI +uiz2Lz19+7upZkamtBEyaXDj7v8636GQuEWOCl8sL7GdaW+YNvI36NrUzQJOpsobjW0H44r6mZOm +aawYEZqH/GydclQenltIzmm5luvzMJSSxFPfA5KIKgSZfq2ujBMKtcJC0qf+ms945Ke+KlcwYREN +w4LpeBkvz48N/N/x1IMnDlPmpOY8e+e/gAXDIz23pzgYWhrbn9tp4Ckt0aZ1w6dHgeBwtm8O5ixn +riA/nDnZdSONK5Sc6sh2Zu0b0mqLCV0wvaTVjlSD0zOWruq01VIjq8lbX3Ml1F49fjF5w8X8e/BC +mng8EZmJI30SWrVlbTXcb7ro/culo6tbvqHunsSG3hMYwgykernPb00FXnDQXVkcEf7GY4JG4QFq +Vlv6s76yMBf+sA1AlzW34Dl17r9rTvtgXNtx8l8EwfRg5yRvZ9x9Pj5TdiwOVJsPomERX9mbHuiY +ovk3CJxqDJf4PpP3JJ2T6ONInmXhqO8Q94WL22e0AwkG13VieB3vDxQbBIO4HtrtFiKVJm3/Kq3n +YXG31baocFRMcyCO+ttpIOZZovZO/Sp5ceDXkQuVM2fFxFw1EV2gtuMvqxNXVaFwBmT72D7FDOlh +fwYNINo/r4IhXM/2Yh3mETHlXE01ZyNuNLNRDT0oot47f2493Kimbq5dtmsZLtbhY9O8z4wPA7ZM +BoeJyhfrHCxndNsDvn9W7tsoH59OIg0PKboW6/8WKpmxYBpw7X2pD0X/dS7QsXBfOXAPJhN3rwOL +yrXFLpqdftmtAZpnIHqDouEQYpcjytvjBAmMYL9bRDU6X5B7NALkhuuIlg4cqhvSlV21ZhvT/n0x +j44lyI6s3w6Xzh+Cmxi9BIwuxhruyxo90/2LyTuKFlnMigM3etVzcl4M7wlFzpJT0SlDWaMN1O8N +EPSxRXt2eoZ6iyNqU8jx/sXLmxedmhlJbi+OMAT0Qc2CwlNgefx+VbisKKyYtAQZS7QKoMbOhm8t +DFfvlzxMQOeUxZqXB/8dY5Tpl7bqUzT967uU11q9DnO6TqrpLifjCgdm556BbLHLthWhaaAspOn7 +e9OU66kGuHnxz27h452jrD2KNGAW7MDIMb9X+gMpnAX9CrcVhDYe3iAOKyoSwlTueACZSPCYlm62 +33Wfl9nQdBLF1Te8QO3g/KpavfDuh0YTDWRGcpgCJGe1gdIPeWYZ+kvTs3HRXXGSkolB9Bspqx0S +IoGDE1D/HyUE1bwdJjc+OR7kvPAQPtDEbY7l9Pq1a5cNtFTjs+aC1Y/g3GoYUnvjnOuo6EJn1FT6 +U1nk4MJgI7L0eQ9cNrDFYuXZyNXNBtLFBfVFBBmsjyIHazVd74wd+RlwfG5P0st8TsGqgCBvykrh +npkb7EoOh4FaBSq/kxvId3oKw5Uufm8AQ3n/1muZQuuJKzkda0P83vyenl3/Snw5AA1OWOjs4EmG +RK55lhTFVqX1Ci8mAXjUGqQ2gCGma9mdQLpIBbekanWCFLsbt2ShoDo/DTzn02I4aedL4V8i54qs +8uJrTDGxHtmAj+uVfNGLHn+6IX1CnTUxd1ZqgovSlWDf6VmGJVoBAowPo3Q9f7kUPM7FoLfzHE0G +vZVtvUsFD2iUSe/spSgEv5IiuodXkiidQOSFejjFFd/3EcxionNpKVoNzwpz3SR0oqUQxgQ/OC1M +5jJZaNUx7K1YQVgSyI5Gko7nDqLsuwgcWHONRNGHblIz7D61yMhZmRMN+Je+kspwoNUx+tPPrVhE +1o4MRDZd5ggr20e1395Jef6KHBBKjIOvxPTb7xQ59qE0bvnRELszP+DqKS7l4zCigCVAODYub/Tt +b/xz1I2M6fmXJnRwljhiHs2lvhkhh/Jq7gPqyysUU2iflyLTxyBSglANP44xcNjzOPu2pI44N1yt +A2trnvHafBPMSnubwSAMfmVBCO/mHedmX84pkj8hJBTvF3xzKFrTlAa9e7T56Z1v5rJHBpeZeJkI +t8uJ5shSj7VwrDocG6xihoD4OkVzxJZKuwBMMlurQJGy054WbOLUeOiru0dUO8CxOOLsDKB5HJzz +wD9nJ5BHaa3egJ3Uybo+8b9dz6Ij7CtW9n2SxinDgnETXpXTSeUJchkK0jQfBo6eZTVgc0jb+6kb +Ec8RfqA0MdEgFIqzGCWFkJ+PlQqdxnZ4liqbmarPbaWt/8nF/B/L8o3H/f4R/Wom+4Q9ThUMWasc +ByIJK369KpNax6n8m9W3ZjhdxIa23EW8xWc8G8AO/cAhMACBQzYGSJPN3nuYRzj6ekcqu+9qvOgN +riiL5AZhLKPdwzqeEO76q092p5OB2CIEXHGg9JfiHxhBTTaopPfpgAuZhMegqq3wyV+tKipdDueK +DGIY8q18Hj0QIx2z1SCgueF9bJeqzbG7qZgs8uhEHdFnf/T+jkCVURko4kc6vgCo+lnwjuiCwAst +dDe1krgxZQ4bBZduQgG54PJE8iNE0JwRJbmiT3c42BSdWqabeVQAHo7nyhOjTI2cGk1ArxJkGLim +SXGo3h67AMXGkFhkUh07/Hkq7/8YgJn6TAb6sT57VpOBrO4JIY+ghuf10vDpQfWMg+lh0prI+x8h +8TbSvNNzD6+ucqIIGNTZjAWyAn03KwMCDao3CNIw4lZAcC1+82zePdeUBAd5tKAv5Wn65wIr2N2v +6Ge7BnE4LooCD6UQYEHSxTGgqRUyc5IwI/30PVU0vHXqR5VLDu8mzLGMWSjpqLUk21QQ+WeXTO0P +mx8wAs94AEe5NcV5QooXaLcRjn8zt2y7bfdjk+9D4yNYk+/SY/HHnjQpP4oxw2yhYiTqMz1+XIYI +UXcV0DYVLKeU5JPs2I4BXUJSylzwYa+vVTDm3MkGvarlPZB7G2vfpARROH+2p303FHZIaSJXMfaU +RRhzpu9PSbficQA1OBco8ZFqbZGDaTWAq0kdmZ+8wJDGh0Eu9evdP7Gf7NgoYhptJAG3OfguVLIg +49Bt1fMfscfHTI4R4dLVmVQECfJv4buXvGHiqGe/bLgq/r8WrhzamzMwMOYVINNwvDO7rzctCiek +rk9BijWfypV6rElxG8GLC2DZI0ROyLxRdmuGs+121wR4Ew3Dp2xVnvD2O2j8W1TUfL6mC5VNcksv +pDUkKvFK0tv/3sgJtLkCWhseNUYcpMsjMLAT7bHtBPNS3MnwEvNt7acsKWEb3lJD0dEeL02EeCu1 +T/IfI/uv2U+4Gny64JRZ37BinjYRZ3p6DL/UGNFkWS18mJkmKfkn8PXfUYF/5WIdkpq++TA1rJs9 +9MzvQ4arLpC+D+ksvhFlshwIMvN51ugTNAwAKsvkK9zOAptNwGXTe6e+XVX/Pzo0kAIAQ2Muf2CU +Wmq5Rm/6UIemm9vpTiryc/fozfB3RFVSdedWOpaRgXCqru/O1k0a9cLUgbt99AH160+KeoCoQYaO +x0BtBGIw+QbEdKagAS6SHN/Hu4UBngwc5ZCpKD3l7s3S+w8Z0NzGFUPDS1G0028Wj3WBl9s3oyTv +lT96NAA+rvjU38tpbN/z7QpWnX46ZePzOAaMrcuje6bg05MCFuco7OG/1u6ttBtY7u75/Rq3a8hJ +tr3ulHT7CIRuCE1YurPFP2kofewBbhRMubcnTBnpHySsoydnCZUs8EHd7jK/f8V7aN+6TNGi+G9c +oR5GS5WHQvLFrMhmVtXdEZlPYdgMlh5stOAmH4e8YFZO7IW3CxJPCVeSZpC4afjFUK6AfF3v6dGT +0htLe0JRO6mCLvgHAYHuj3uYKikS1RMYF/JB9FLHMrFOwO67lZr5mEUC7qd3wYCkegLyefc6NfkV ++rwIwJ+uoiye6tRVEeCIvLnxWsJ131qPaOaTWnGVYI0l4xWW4cNzaTq1IIARL28v8scsSZ1mFsHw +Hvt3uz1sk68+iMmTZ8fxrZiG38ORNN0NNBkeO9DofonAiOedu4jnnFQ09Ff0f0JQh7wse6ZBTvws +1Za7sqaTVZzxzdIIvzoOWGsaAENrD3dZKfMXJtWj0rNftoQgATL+91q06bjeRWA+0L01ild+w1UM +1gISpwCpHVFXe/inRATAVpzH+aCoj9tIn8GuFcP3txA2MuIMu5gwYHEawiQlpzhNOHw6ARyB+3sT +XGKkZ6OUM2NQ5vcaNZGmFw6Bnf7R8o//ZC5nE7EmEYGbp2JvaGf+CxMmq9ERQrCum0b+BokpSy+B +7tcgVqn9KrNkYZxgHJHmv3KcFzvBqxEJl6f+FEvWmehK7HVzk1hshrRW85jF8MjJ/GX9Qve45F4s +tzYC1S4TKo58M3Q6vXnZ6WEFWRgB9Az9MlYLZIhO6ls6cuaNNzJgewew1tezylb6nlkd5L01vdy1 +0oMGjEasxPuneImT0BrFiJd0K9G26IW/ke8eAAe7DC2uoCGTH+B6E9FL7eVoE75MRmSxE6JfUv/c +wv+QAXtxsTYsCvAmoU8+bpINVGQlSCLm3tVHrmXtUvwdkSzIwlMQHHUbUXvzL2nHcK5t2/QQpoDi +OKViVGOOzvY3eLifaqQru2t+zpIxceyQ7OrVr/3Rzjt6zvxbZidm58zZNLJ+T4Qje/gJOlT+CkMh +jAwIujd4hkyvo6wvhGFrExmGwJkhaFqPzyKB7YFQkGMaivAER7I22aHC/U+j6MUUwdTJRtpEcG6C +aWDKkrb+XTgH2RportW6scb+egeJDXe0z+jWEPtTCT4KJVRUfSNInABoNk3sbsLwCuHsL1CWaaAD +Sh3aOWF+6iwoNq1lynI4mrSYjRd2JK7IEG1CrZjWUnASzV6v58z3gpvnxUKX7TY5enol02R0/OT1 +tIwJpJXkU2owS8mi9HwvU0GzyS8DA3kPZ7iMY6Tj661nt8Edvul8KGr27KgHsmjOAdivIaEY2rTy +sjtR5Gwr9HZYjRWojSdH1ZJPFkiGwF7VtoPMvl/vHz8jZAB/c4BAb4JKJAX6U2UvHh9Ct/ZWKV/Y +/FP753uoKxEV2NUi9u9hGie0dp0kGMM7DDUE1RNXyvd6C9uLUbxctwykorm8DtJVW9pJpRxUkMbv +F+rfHcM5cjjM2Giruy7BZeownsJ+0IPivV8vYLAt4dFRCZ5vz91NOJBNDBPhd2bUEd19gk1wUcqq +6hcSDrriAARq3eFfGLm80Ug5h2PCX0s+GVmH5kBwsQBu/yDHkBv4NIdvjrMR7bjqEIGSRgfww330 +2AjcxP8DMiksOVUJZnEK9kKbHcJqYKJQd6vUgVhTNhlulhrOdb60rPd5AsSviymGqrqkp6IVgSkS +c2jKW72jqw47r2iTtpZwRuXfhaFvTmX+8uariBAltOBmQ0P6xEgWUHGspbOjDZZD/bGh8Su/BTEh +IsIJHvFf8BSkOyMljf3avj8KoAFUHkOmyJYWRZqE+QDwkDh1Nlqrv1hlZpahtv0OxGbyJnsAiEGv +ByLS/xjCvp2f0LcvF0Olz6zCJAvv+Oxt/X5jqRppX4SinzGwlS79HQEiZVN3Y29vwEXNdtiAlwIo +8Y78JIu+69tEFVlM3q7xfsqKXPSW4ONmT708fPgEJItZHa+bbO92WTFwMAXSU7hNCl6fNkjk1wRG +j1dtzVHcGU2E2rNbUJDFQpRlJRCJWXvnTs+DiOBP7VEc8acHxrKC5rgr6TU6PmVcsM+DCpTbGAT/ +OeRB4S9PXd3aGeP/xu1RxaeLLkeahhLjF3kzyoIYgIIakYmg03IQ1bnvHhbb8ZREKGiffO2HjEKY +CjQND9TCqnstqap7fq+Qu8H1kwJ+QaSiI3BrPL+MktJilo2HuKUjdznFOk+sL9dS8CGp1qBEEo0z +sBP5VkQapdeVIjBuaM6Hi7Sb2JSzwM/yZoQtu5kW+JirQ9dasgtlc6tYodjE2MnQhYPX3JFDZw5t +0sDdguFlgoIxMXYEBoaxgWCqtOOFN1oTWWcceXKTp44gSpQgq5zRvJlr8MTutWslTiYmBzIl+bHn +hoU8XPba61rIfgZ8JfZbkojY98SoBTUR/xcstOPzLl9yy1iC1VLolAOGX2l3GWlnRw0lXdlPOM5T +2i6eiyv87XfOsf2PXJjodE60hhGkBo5Jq8m/8kiQyZY1MoQ7V7sEXUSlp8coFic2X54ykfmYokau +G/MfV+qNtpWb5Nz9cWP417zju6NPsnWcd8QTgp0+QNWc5uh/TF7bF5OOEMkuneNLeOyrS2HCvt7o +rDu+J9vN0BgTArYyWQ4IzmAylssylzKGXMX87DYoEpF/1MWChnMf3Fxw9gEOAbYh/nDoF0/WhoWm +7SHmt0Cn3k2jMzuQq8Badg/bwHBr229J6GqVJoMNvi9+XZEVZidS5WbN/8YThGiT/siu1MP5xett +9hi92HJpFI47IB+l1hzTlOIr0wSXnDD+dIDz2/LE0ozue9iV4g/0EJMKlBFfe0eDE0rFUZlnu0CG +Kmm9DOu98v74QFgTrZzoAToPTWEstWbrANbwFdfxY7Nre8v31gPJq0f6JHNKxaOLmrwoKB+EnIPL +0F7PvHY7EHstJlCBMvMfBg7r50UPRM/JU04dGkRjRwAZKoDl9REtyxjVJGbMtFFCcmOE2hUFWi/x +77pIsqvvtKeMajDQbYJYVF6SPRrqoEEC7QV7TCjGqtgWMAohfrNfa/c08P62AS4cAQECHzvI2Frg +NJ/hlIDDmFP18RSFFShTpsuxPS2AtIDcaSt64S4VeAi+9g6wfBZIHwHl5n9UoLHeHNCtIAy5lEQZ +53V+D/38zF1kXU88dvgkv+mqYG3bCQI5L3/O5K2+gGt0Cb2tgF9f0MuNDVYiE3rQydk1wO36PQUv +4TGO5IBTC0elrheSptL38W9tTUy4AbzonNXb2l7caDeZeHRhgcECoNClfpaQT5AnKv3E5mIp+FuT +wt43pslkUhhoZc1e+OdJ3nyVF9AbLA8KnUgEDcdI8CQdeZutcJThAZAAiw/beuWcFIc2cZFk4giJ +dSMc7jjcycb79hYxs0T9dPGYGbebZaoH3i6eCoMckyF9sR9EJiktISmdEbRXGM3f2nlN0rNXWAd9 +yxmwUcfrfHB4qqU1pPJOtjLyE3P+ouhBPx+Vjw8h940FTm6Kj7Cg6o32COYdEYp/3sdklC3YfxFo +IP6w4KqQjotWyyIV6JBiiW8uJO79S47tOmzXWouZ1DaiVS2Vol8znAPDOS3bmGKpb1/xr9gIfx2E +m/S0JxS4Y/eq84cjtMw2mxUyZOxXMEs5bziBQjsTFRYAB3DCsyk8hnNmdBj/D+NvmsPTGUxc8fkx +mMVQmlBGhipdbpNZTTvlDd7O1BjXssy7pZqlhqEQVJAFvRUQHJ2DRAAjp1VmsjyudSaLGabWFcbv +43Fnte/R4DggaQ5srEwwGKaX3RU9SrI/JP5sVZueVfisr9st1cnJmTXGbwTgDjYHXsSzXJtSrgzx +ZJPoKptiLaHYbZBQepYVzwwiYez38DFmIeadIoFFNaD4n1E+JBBA2bABejCTPFho1apMXGn7odKk +fqmF1bcl9IDD9KzqMSQP3lfKbjrhtXj45bgrqvryukL/5hdbTaDPpZcclqjpW38ovEL97JU3SyOt +NCJcHnwOy+Mrz/P32WVGP/rXwG3K4nu++8QymTTueH/Tzo5WnK8npq1ohR4bmP95ovY1PWL0Psrz +NXoUqXGDC7MUQ2UeRaFau5UO70elvHtNL6AvznRQKUvJJ8lSh5dUhpxgv05Mvz9jRAyMYf7GUXNP +2G9vAOihvm0ZbmpcyLw3TjVuCHCmCZyd+3K2cpFS/IebqyqImjnWQ9BGI0LITVH0b7m+kA7sUkNI +DrMIo9veoeVKRIliA5JwbJ//aH5yFTudfYihNZcZPZME8HgNklbrR7TvysdPDp6HxfkSMI4V7n0M +ux2T6N73cWpWkKxvy91itwIDRUVnxLXZYkVhHsdyayqRt52U1m+qf1aZi4iFmqbzCJxd2B+HZEq6 +uthNUSuxoo690zzeEvy+GekmILddvp1Gj+iEqJTxdv7uB3hHO5+K+BA71mM2mdFMsYwKZK3cjmvE +sCbTMrDvdbd8Y50PpoKs6nt5byBYcjIBn+EMRPE254yIXrAmFTDtvkmzWUu2MU5dO8XR/DyQT4sx +f4V4OxAfUlzj+sl1+63GFsVW0ZOQOKp7rVC1rTTmgkRoKvAQDxtckMB8ppbJP3pFcE4gXI7uBUej +o223LnFEOpaXf6DaoqnraiqqqufGCzHl4rk+OXU81t9ZULoxZ0dlQn7G9fd83ZIwwV4DS0RHJqNb +miCBnopoUeSiBXZ0XzuUvoqDy4itndb/TwJbWUxOgAnMtgm64B8B2IOeavSfaBvkzSP9cAHS4RvA +8xIW5RutfDeLxZK7iFz4i0WLK+/EF9ynM/awOaR+Y0qyJk3QTM7zRlyqnPFSTRBePcIDvAeYRThA +92NmIz3xdski/uEFJvk4l45fcccOr5G+LBldOu2LpYNdBaAPUsLbm3PsLEWrdbCnZHHewKSiVLxp +hlfXQ7cUQ08lRGdSfr784tgNnROSroZRbW6ufaKtL2Gn5IFd1wE4dEnX46oiCL75A6uetI3vG0MR +X741nJJHUF+TpvlbvQrgPdE1mZaxQ/dZQRByBjrEMinTrMXWb8z7sDbby/Ak8sFHki7/5fFK5fsJ +2TlAb62HGtued4HZYcdUgMttx0Z/TuXfnQujPkG+62JfzGZO8xiHzitOPrVyfPbL6YTtiTEMerYO +Ne+3TfqpirSZWdoxkb7TOZWjex9owRKytfEsXrtUt/bcyN9wz4e6hOmH0BnkP7cyrQcyY3QUugVG +I+QDwSLte/YVujNm/OBS9QcXRJKolNPLOrigGcO2oG4PLMqzpnV1Fy/WO3gl5UiZhMNMf0QqhyF0 +De28OGHLjum9QGiLHWgdmTXLaa7sjVHnaAPNlgIkAe7ssKkzMSK3vOGb9Bt3ciY9erA+HnksMVab +pzFJIYwSyc6O/ktFgO6oX2HB2nGc0scCDLpuRttzhEuEcBBHBZe1O4OyLK2aOzAlzM9jgXmko221 +8fa9mXFq1JXyUau2Pnez7mhVdg+5BMvjaL0x0Lz85PHLtOqwfA/Gz/3HoJrmgZ/3PRVRAjrZpfOP +EsoCG52fhvPGWPSJseffYWIVXUJ4pY71At0Nkq9fRPpLW9zXPjJJKaZnUnZLlbfR3mJ+cQwxCYgh +Uk93mUI5wDWEv0rHPie175NQot//kxiwcP8F3veqZVc7ROWtK+NPcMvwzY7nMYTy2TI8gCCZYftX +opAuRqTSMHfvV/X41+Y9mo3OBmYV9kkU5KKYGvudGTlvxVfPYzQ68gWIqOATUWgik0Fg+YWlMQOQ +ytm4dP0z/COI8LRUiGuAAHHq9gFHsPl4YXC89BrM1HW8jO0bozHFof1FmhLaAlLhwrL/LCvfzJdo +Hvfd9Mp13R9azku90CmR/UehOrAYjXnpMWiiro/urYKz4yUKN1A2wCUGWpfci7hRk8d/Wab/fhiI +OL5+dc/n+j31Vy9N6yhR0XbxPmO8bvvj7nRacvgBOPSZHXQgzL8sfAXn1cFKShaDV4o0+wOF6IhG +VOLEO3NYTKd/qX0Bok8TTqueX12pupqW9KEcxJL39saWR1uJlW89b/YXy26P3/dB6IqDtWJLNayT +KCoj99E2Kf+UQ/3GLtTToXGoCHuFwoXK5M+9YxYOpzAs5lQ4xwhADFuYSaTK4cTn1WimbwcDXHMn +OPssgHsM7odLQPlmUM6b4KTJl1cBLzINeXcEaw2NUX6YIbwiyT00YM/MmT5bs47fO7FPCKMRm1ZO +GHiOEql1Pi7vYEu/oyuCp6tZQE4bc+lJMdZoZ4vrnzyfTGGANFbbT+/ZrvXY6wnvnriDsovPxS0N +QLhzF11/yukZLvbxyoSLyO2C4R1XOEGVA4qJJsiSD6PHEC3js4PDbPq6HAhBa/WzFl8F7O1Dlm+b +Oet/uAo0+Jq/XwSH6q6sGwRkjJoTcYUJBFJAfNNkFfH0hmHBq/3cRA72kVkHGrT5EvfYqBD28SAq ++X+IrYEYWP8YQ66n+8MFjhrCbhDrp9n4b/bEqPgFCpQhV8noPUOdR2rY1xIh6bWul9LtFSozQClJ +JBnG9mMfBpTH+JFgK7YOMvDeo4supSnbhz/ntAyVLecV/NCYuePqpE9Lq3QB5Q9TSW6q2ixLpFEF +fq69bQ04ZvQBxWB8qJjRKO58ryFoeR7zHkhmZTbbSmZYuxDs9DK8ybTHrECDLKgRxsYL5kz+iosX +fxDKVFmpc4k5KAyEKCiMzW+l9CEP/3Z/ZxyNNz4yi8GM/NlNao3OlQHpvTxR4GrmELHM4LY9WLvP +VDyVpv0zK2V4fhM22aealwmZUS2ZV6a4vd9+S7cgCmUx9lK3YjgdmOVEcnU5tFZOBUGtAYlryZbr +iVLuoWU7/+oAxU//gas3YLF7VVwLif2+zrGO66oO6whSpIoxTAdIzOS2ksbV0o72Sd6TI7a3IzzU +6CJC2M5zckQk/JeRmOwFHKzs8IJoT1rLtCRZjFsbO9VsIlLQgV+QRiMG4kx9HqI+cpdWA+GxVBea +ATK6sk5Lk3AYFTN390wbKc4tdRb1AcfdHdxkP1744kAz7Ip5DoVBydS2/diFvYMoLHOXmcNZBkeC +1/qscCdmD/KR0+95Xp99Uq8WdZEpshnm2kVztMuCcolbwgP+LueG/9NJQgqsIJ2D3D43WQoJtHD3 +5afwn+WZDH1Dqf5AiKTtPqKopNOTxhOJKUskheC9R0iOVZuuAB2kr/fBvx0KuagZybYQ57FWLD6T +DDQLXQLh7e7302ut6FMzk1hji/fBovy2f4un8l+7CdZzPbYLaOFyZseEGkBsc3slXpvg8SmILsLQ +2qQQdhq6hgPXGEIeG8lUFBZ7PVRKv9rmzTbfqB2/oBKtUlOsyQjnaTFYhi9QMgS9whaUeFH+SbFi ++bODquH28SdeDs/uxImKZLiXdXX0ITpylVyRwiqpZ/tLRpwW9msWp1aNychm+504Q7T28HxHgb5d +9mQ8qgMYE4U15a547q+yPmDC2N+HNVkRBKk6uUiGQScTGzhEsI9yVtCDInhRFgECLpU88/59i3el +znhLuTI5NdjKE4fim2BXD1YxQyBEw9BscbY/VSjaOBTlIOoyz5qY3tJrQi47u4q2pHHSrueeL8ht +dwK57IU+mEYrTUTdvhCFTmT4DFbpljdVl2arH0qu5aVfnF/96qwuPUFiV77s1c35Xlkoyxr9Tzxb +WxkzYBhGDYzh2KrhY+Qumzq6gRq2RwdzSROescqbzBwWOf26xLmdgk3lfVllDCk+vZ5kF55eqAiH +pTz3HbJTk4sAy72mQmpsR1ELrjNQZZRT/Hr79pw90SKPv29FvKdH9LS44FJdWLXQHfDWZ/2TWTpo +4ETRjoMnSaJms99kO0vS7SqlUMfUihApYCcSFqRpOAWGRNZWTvFqkN/azNSl8eJuPZW8ZnMz4T6o +xyaOgf0oNphZPctbGW93Bh3BtwfcVov9kST7LCd1vWJj9NTilCVD4YRbdHbkE/hbnnjShnBwF/Zq +YNcjixwQLba0Hhg1gkt++UKIsqZ1Nps0GCkcaRvRqu6qT3kIlMupuJ0xNeefpR/7U3Zv+Ya+gIa0 +wLi1NEz4SzO/QlvCc8FP4nZD6csXUJ7ddktaxR/XHvfzuUQ2imu875XZQzd07g8QemWf+UwkFzRH ++cC/r7mf+zEbBdhnGUDmEF4DXUCL8PRp9vG/pvo9/lWd1iWBvVO3erzJN6192TcNxaWpPjF4Aji8 +4ghUmqeArbUa0Sup646YDVvf/hq9haeI9siExB3dw5Z9d5oYvLsP1V4bD0lA0aJpkq38Opqmxq+p +D97WqrV8OPiyCo9aMAwLOzguKpmHl/P5w/mnP+0YX/LkvelaJecJ7fpv75pZ46sPvGYez9j5tdeY +XT6ubjolLv78Xsq0Wt6CML84TgPzBE/qvvORdnOMEm8hl2VN0hesom8HlJBTzXSd2ChXPyZIqpxO +HUE5IRhf2thYS+Vp0rqrtiPLX9nmS9D7gU2cLUVGMs6iRgribHxKRhpl0St54oxYRMFqzK6YvXpm +An1kQO4+3CZ4CM5Nf1eedtzaMmZJGo0s0Rel025ho+a6KI5gQ3jNtgu+5jm+fMxCPcdCf8zy4Twu +TnFQVmylMk9nJz+T5ndis1Ppbeo+WLDZJziGyzUHPUisDZfsQ7D/NGmDuxGRrot3CrUiB5IIIs2U +2JreHni2qCoLDouCTdKlI8J9gu6xxGZ5xlb7UFdjrVf9OTh2/dc/3cpBVttjrySU06XD4Fw6cL0t +Toh9DSoaUJ5WQt/UNRUMYVnaDwy8pzm+gcqxBXUrmrU1T1m4BiynUTeA0/UeBlPsMFZHMxrBnCg5 +BbGCMs/FtJk5vE+KjNrQJntKitQPzJIomi7Pa1R2TAjxU0m1snlTVGqGGOEqPQDW3jkbw0VJ250f +qjTr13bVnawzPf5LOyArUetoWLpYTcqtNIOJ8d/dkMpqVMc1zRo9rLLF++XQv917oT5ussidvFNa +IzlVIsrA78JLpfzFhfY5hRFH7B0eBgA9talnQjbtj411vU0zTFYOAUIY4m3o7fmFFDaG/EDJoLNy +0pZEBpjgKmgvsqxal7Okl+8wwvmIKL2MR4rOwmVIexe4Cl4IGQoTyZE+f/Ei9GiK3cY1aUF5TSLo +W+hvnYLNRsXYyM3vme6TzreFSAVoTg31M+noihAqUWO2Dh0q8KvIfMbtqFAJlndZTa/+23lbLKLb ++NIni3KLeZoh454a2ByJvV5kyFv3J1Qrdk1tfERIS7H7l7U8gTQeyOPs9La9SB2EaGCb7aqf0HTc +LFyGgqynll80y5teJu6mf4KUrJPQdN62kcRWWSp6UKud7XnLojFlou/zwQpTR7ytteQ6T09n+QwD +zYPTFwU4aHIeTlgieLv/hSTRguaSXys0KNrxhf1/7/PGS4Xs/0f3LMLgKC15dO3ISpGqgcEwrQe5 +NWXXv4zYHQn3AsywiK3JjrIGLL/BocEoKe13gnGj5oR4qJ+iVMFRKh0//Nb4pBNBVYmtEKtI8NOT +bXN8OV71QHoV1gABjLvGp5bMA1eLZs8AF5D6SD9x9B+YRIpZiLDBcfREiQssjjSFdy36Sq4lKEOy +Y6une78zmomlFEgbypCqADj1231tZMINVDewnaHO+cyrD3/7KwZGzei121F0TiksgT/qOxYi62pH +PoDQdnV/OQNnstpg/AKkG/t3Bw3uzlEt5Az2p+1JZ5Mugex/oe8RIsEQPtJJO/QPKHiUUu2+g0l/ +WqBm7JghvYVpBedSECK0G8QyOkzyqZZL9jJl3tg+gXz2/KgAfqkC+nu7Sm6konMzckzHNcXeGNrT +PSILOoErwhcaSGAZadedt3cKG7synDtMvIAe3nztX+gwqt9S+mjYNE2TSIsbqZpXzuH9z85plDmY +FR7b/YpE7S/0x6XPctNxv/7yJLth9LllomscVekAFix1g+l3wJubVSfL/n/oAKVx/GWBohLQzYwb +rn7MO33+ukLX4oS22/EnbRX8i6r+p4PhWfZFjj9uyiKXnYvzm/ZEgF5XI/T+XgE2kNtz07eLADzQ +mCfR0dZKPt8i2UwoD2hqLAhVYGvPyTPi+pXO4GxoFuYvZn9mLh+0ep+HzffQ2wpOIOZM56Q4JOt/ +1F+PqqXR09Oj9K2OuWZtlcCSo8+6Bupka5q++x26KK7ns2V8mvr9mZwVZvoHr+ZvYD0SBTReWAXn +iezjU2O9/jJR3Pt1SRP34ROSv3VC3Hz/YoHXvMwluMa46cnhzqpg6r+Wu/vDtRVcE9edR4zGPbbc +qoh2FimXQcEUxa4IFu23MA+g4tIlPDxpRMLbN9teNa9ycktFxvMLKquKDn96/mlkygP/f9sKhIx8 +SujIWEyXVZ0baUElgHzIVsAGtjyZbRH4qkSdwWpvP3C4g/NzJq+LxbKxkt9SBBDCZE0l+L/LTuLa +pQeQHhMNZVrPQ/RK1ZX2YaDFQgq7gUukq1cNYbP1+c7/L4X8JJhFkOv8Q4hard1xpN3FUBfvU0jv +hbB+x70kJm408Dug6WlGd/DxRTqlfuX6MXdURZowet+O0Am3qv/Q/7umjFMVIZcPZ4gw/Nrph5ob +PmWxTi9UkJqZAw2ubQo3lAsCTYKQ9EHEqR8XY3gw52tWA5P2r+Lh+0Vo8BXBUOwjPXaeoNDFt94P +u8HV31fY8QhHqxc4rg+CW+7rEuMeZwOtdev1tvJKqgrg3klrNt3YxaV9NqMSsaNUQO0yp/lkNCZU +r8fjdgGkhH8QFTY33erypFybNcEXagzvQXmpBdJsML35yt29yI8a0Rmna73L2Qe93JJ/rh/PBoBZ +bGCs8DQNbylNJl4Hd/FD+OB0wjlrHnGM9Bm326THD/rBcg/Y4qiWzvud5TRP0w9sOCuIaDe9hvmj +pY03v7muCFg2bFYf6GKQc9nxx5H7GMtlKYsbwmFPlfGR+ppJe2Q/0jMF6Tj1Hs5xQki5TURQSV7Y +7pFO1yy8V3+QSsfRRIUzvkG7b3UwRhitxz7kKKcuKChSV1c0WKabt99UcGDQrpyrosU2YRNwq5fV +07Uobj57yIWsfS9zkRniDGXetJTbOkpT/6E/DIdoPDH/5hSegImNEVSJA9CFgo0Aap108oxZVKXH +LrXYdM4Oaz7bNePDGdGV9Rk5QPCsweKP+jMZkJBY01X+iRcuiqVn/V6nLoqvsKuze0cgolOmYGYw +Xcp0MLe/rfUh/lSuHdIxciwTom7jfn6NfcTNbZ7SIjefEMqqc6MC25orgpYvcX+/KLXqZfjPL31x +MK+j960r0lhQSEfLHXZtWsXiUypmm8leB8w/dGq+znxynkL6PcSxWhJPG9MfM2QbOPuFHr3eBskx +uE+02h8qdGIaTIMOxsuefNajkpun5N/Uw+gqSmRUicI76SpHUjD5RbZTLSXQxYvFZBH3W/MursbN +5XJX1XNo0a782wuzzZmqy9/KKhc3TUiVD8TO2E5Vm51usvwNv3tSDFdhFKbJ3UdZ9s2xySBaQScG +HKCGLYOJQocKYbfjbsort5erCtAVeSPtLaUVTSvZQGmgFSxOgAXsbMvXBEGlhcEE6drJj9OCTz98 +RcdBXhokCnqwFZT5RV3AOHPV1vgquNML+BwQg05ZOrltbco9ZxP07skcsbKCxB5dGMSDi7E4ShHy +kTNLfbUxPuWgMdwpojgzbEe41IMs2xyDA3mIXpr0oL5upjDfWii7F6mCntMAy5g/IgPNfJQeG+De +CHjdaTeLZZvoydWcUeW7EFJz9fIa1GByD+OdwdYT1fB9bgwZS7m52z8iBeGxPRoBUvnPHsbU1wkd +gbt8VdGe8HXd9wXcf0IQSzdzdxf6thASkHGVauGF3MSIU4AsvDQkctwvA9lsNSJoGJCnDWfhTBty +Q5pr4bxr15UXRCrwmhNDtO9bJMaSKtyL881J+XkjgHCZhj0CWyUFiXjw0IO1yKV5uwEiQZn1JOrH +qJbFE4u13ith9/4sAumowiyE97y3qLP9SW5AC8MP9KlgazyNGGGYDEefjtkgNSB0QH4YWvfLWd0m +UCjnFO8cEsFa1vnekrDTen97EqLl4J3e2btWH/R3I19Zk80WWRWVti9ifhKb8kdx60omD1hjjbPK +ckhGn60P/gROLznlHA2DY2Lqrk/BK023JJJgSxpyndSMtP4pwIkcsJQ8ELERAEDFbogGr+MU2x5W +bNZPuhBK27doZ/CcEyiPj0o1QRrM6lmygDfjxbO5ePRAL4vBbujMFrqibMmJUB7z6lMmmi+IcTC1 +J/dcOpeNJQncbcJbQZwQjW1sefkDqIDUFW7F/vE5QpsQ5/kY3BjsaU5OGXd+N0on2Sfj56a0YDXH +f4laXBiaNcKR+ZMCpund5F2+kPFDZdbMBnNAUWDWILBap4/FFGYJZ7isUNrHpeiIBVOhrowQAcbu +a1HxPq6fFviwv+Cf/11mi4EaBBaai5BIgx6NmGzPON6oRaY6w8J0TafMONmROlgzyXVq+tlu8X/2 +d17MpdoIgDG0a/ny+hAX++DVsusmZgd1J/+omwwcwHmbRb04itKpjXvn12Qoag1gdUNnCLY7RIrm +3GZ1BoWckI2GW9K0p9kuroABp6rObp8/Sywg9wLDIk+RbGiIfXIhS+x8802D75PLpfEsI4UqD0NJ +htdg0jMYrWm6YJLEtBppn7oiqwxECmIVo7zH+22u1b4E/2olRGitGxzRc/fEyMGnkw0IHHXrqC62 +dXsqRgYLr4EBiqvr56zT9xmC8pdyIo6fVjhNCNdP2Pu9Ij0ykHJMLyXps/hOdcvWxsfhhpRAaVJs +oxQ0vfgLCFdbGiCTmm8RIlSNTYQNe26ZORreueLa7iCEdPBjdw6GbDnxu6wpKHULEIrJL0kf4ZwO +iTBkJqiT1NRTTVekiPIR8mYkkFT6Roju5n50XtZsozy9IXnncMxGx5JnDE6qZ3tem0y3UaUt3CWR +L4jYVrxjLTcZ10/Xp/hs3Wfxd5IcgGZaICRqZ+lneVe1Oonc+35H0TgcuFggbKgqbdN51PRohRHS +wsMjskjm3oDO3jM3L0ou257c18RiXOjxZscDmDF3PS4p98lYBBAkKYpsJxpk/ewZWcu88BpJpgNB +4FG1vslLdhHDuyr8EC6+CPnGQux5L/bg33fqJ5xnJ1AZa0/nqrjzTq66kr2ZO/NHvpDpqP+Z1C9o +hVYjj3rmiXZY3FlYxyfum3TX1qjaxra9larEXz3V1jLnEehUVYP5UFKk8XPwv1MeIwkTcuVjXRn5 +0FTAPJXoKnD8pIYFbWX9kZOPvGVX/X6AJJCUN4zs8xN3svJv7JnqAM4pKOdgxY65n3N/nqAN2cMr +DDCMycqTL5jLlREsHhNNNp5NHAH2K1820rj4HhqrPViHIG5WlfuToDjaC7VG5j2zrLFiD9Swxlgi +KOP2RJ6y1Ezr0yKGuJZATz6S8Pl9Jwv8FCKXODVx9SWz+W7MTTR8PKVTSpXR672dPEMfGjITPS9O +Wfg1FQAuU0I9kuthmeEBTxBPofKtGXdqD4RfWpKfTukS4sT1A7Y91QaZeE8iU6LkA90P1ZoF069V +0iLDinpRugGF+ZcznYok+7i4nGetDxuiNozVvermuvihDoDoJBcNOfJYSBywlhKp0hN4pRcUZWf8 +j201KTd+OJqsntd7cAZuHaKvrDy5QgwZdsJhmQijsoYfZGKcYToz2BDfwVtpmpA9mOyjPBKwM/Jw +kfLIkk/FjRJprS/QTEKLDmgrSt4tO7A7E/It1OX4px7eIzA3gvQpdKgDqnD3pwxxaevmyMUftK5O +bp5i+Ha6upmOag3LLdaOpMbKUcOO5It+cMQAhlUOkde4cIqtNrlUR9oz9mUIr4eDhlytU2HfipoD +U5v/KRq87xnsZBd5fG4SxiX/1h3XRauuByuqje+RU/QKuiHez2Dx4Cq3F6KWt2qFs3Qnmfnvc3k2 +lcHF68c+buNchmLAx0684IF4cYAp0dufvJzgohLa7LUJpYZGcYkg3Z4VO3Gs2IaPeLsRSniujBOc +Af6GVIUZYuy+RqT8TUK0f6s4LVhaEbERfZD37Vzg9XUQDyAYYl9h/ig6PNTCJcjo+JEPrzCJbpP4 +3qgDHDrQ/7oRE39iDpQTQc59A74qPNMKOUrbfZoepI1Y1E7ou18g9tbBoxyQnyrqatCA+1T4Pieb +SQHBIGK8XstJVG/MJrm5OyPZj/b681CV8c7xhvSO0hKjyEHBiO7jelZKkvjyccmXZ8EWxpJSgfE8 +KV3bPmTLPBo4S+sqhZ/4t1qT4KdS5u6/dUEYIHb8GB2zjcv2PBzrnJ9oWMGzUwM2mdi4YuUT4QeT +RkAiphEvy9EDkgcoSKigKOjq9UPsypwepxOBUsBnKusuDgwCmF0UZTfGOXrjtTsamhdNekeqVtl8 +jrH1w6UvmiLF1QHavsy3Br8WDmpr1LURavSTRE92vb6lihgPTCYH8vNJstmdI20M8meWPtUtPelB +OtW/+R8yvf9LqCv9CxbLvPHEOAU0jeqcqdAM8+3/RxiQ4/ObK3br0Ry9NZA+oEKMNvMwGBhxLbrY +grM6d0x3gPuKDWejyXEPE+D7x9ewQ/wj4BqHBezjPJPcmAtUpp2bWKSOciOpYx77bjKA3I9bbre5 +TDAycVefxtZIsrYHblOdG4FDBTNpBT419VrONTvrfh3evOPDDIpHcpNARJu3MbOY+tACukISAfy7 +R/52H9L0zZ4/kUWSzSgSvbemUNXdhALL9ruvtdpld1v/hk8/Xrf2BEQPFD7y6nUMvRmtlv1aGxI/ +MrtFTIN4CTF/bmMiEdZrjSbAnCkXEHjcDYfNExsgc0dwV/lxNoU3qgXxvn8HgIKMv4klCmLMDJyI +NNC+govZxOlZJwJq63inkduASKWRt2Libpp29M09L+7xSvdJKwakzzIMchwlIvwWBUm2Y6H0CMF6 +YO5zWzsw9689kwDPUJ35LE0LJXwiXIUiwCtLxyw9dKNb8bKRVeC27533BL8PcV/F3rFFmbtoPsun +j8hWS36z2puLYz5keavfJvCEwQpxVrqaOJT/GMGfhMOW6FF9nPkoZMFIzp//zpEayDczOC3VBmvF +X0FtlWPadpMX19zMFGwTfXjCQpu+7rS2TAFc9FbURs0HU8s3Z6LqyfU2ziqTrXVk4N88pSiZSDQf +WHlSqaAEuyfjJKjzhnjJ8p3XcVxvb+3c9APYS26AAogdQQd2pIPEdsXqkySuXT+AloCLTKil7Ccq +M/dSQdptKmfu/DclZu9H6NpNjpIJ9BlZS79yiqetMuqnUuGVmZQwHIuogkd97wOUAzraSszcEePA +1z4FgPifEIm4rEn24hH9rx4FRgVX39/uch1tNMG1er9S+NnfX0huXxRL+5K1R5JpPBhFU8R43D6k +9VM+C0vHHGM8dBq7IBzL/EMzg+BxFe3UxQ5nXIDoUW6q4KqXVN3xB/nIjjdq9pw/0GAKYJa5rkN5 +vNTDvFpKbk8+w6aacZoxckXkVg0ke87gXbYdqKTda7Ejo0F6Y8O3jmNX9+E+MQ9auj2b9V27tK88 +xaQ/Y5J1yFlIilFl0QfOa+tBVgl6TwHQYR3EZcA10JlT4DQ2XtRbv93/X7Ah0Nv2Q8YRQcqRXu8/ +rJM0jrEwasMjd8K/6bKEtj9rkSOHLlNTOajykQ3uqB2hPnUhYdUSGB4ySzUKjWvphcDlw9ODghvJ +8S/VoiAZIgHTegEk1vkYdxjleMFwsqh07Trnn6uSgbRoZcjlgutxo9036QuHAUwX98myF7FA0hF8 +zPFw41vPZyb5ULiopues4T/JCRv2MqqsIM6jq6Fuvzm/2gSBnI818jU1ViYdCio+UbbzJ86Kx284 +R53sILUEwCN221PvQz7XaCIiS3RKwRMI/kbvAcwCenOSEOR5i4MkHsVxluqFpn1qVlYaAyGu8O5S +G6s3hxfMkOqICzlEtEa1zEK0coUiYjE2zZJRkzDU+uDxicuCWfv+DrkMiKhif+30kBz+/eQ5pwQJ +3600Ks553Xex6NLYjSvMbN2WfvDsxfn4UKp9AXVMqCtd6QISVhopaj7vX79qwUOb2kI6Waq+DGEQ +8H8GIkm1bYmOydSUakorEH2fy6ivsLWOu+DKjIasCK9B8TiYvLfIJsUR5Ooyq7SnVvtgAckkObnt +oprgFKFGYJOXLmEqYWMiyqnoIhqzGouT8feNU5SoPub1yfJ2/a+wYVFi+4LGO2IFtga7ne/iJzgh +XCUKx2Yplc0Muis0famcY8uMNPogLjZgDUKZrV1X6jGiML5wGQQVgzpbCX6ELMJmzPRN+S+kQ8rf +ffer62u9bSQCZHe4bVNMGjvqOP/pLhdK6cfA4cLxViPn6fxirE3t6icA8iL4lCJA7c6B+i+VgWzh +hPqGT15JWpbz7c9JXqOw03Q8yQGhoVH/789xdcJG4mk3qjQ7RcD7JZtE1yyT42dpfUqncAV7Ao7w +JW428JSVveO5dNzLmCCiaXGktkYYnQ4jqvRp7J5otNrm6Mk1ckvQEQ2tkyoUIrVzV3AWJQHykwjK +miO4jrmqWGva7Virt4B5ZeLZODcLNdxiIE7rKqmvgrLsRW/oz2cBxqfUa6F4zyZ6sV7CZrIdy/Tu +1VIGm7ILSQgXdBeMROyPz0kZFAUPze+UNqLtzJDa4Byqvmoxn1yQrcxrIG/iD3AKteWUuwBS+qJ+ +IGI7XDWC3E1rwGHhIx8klG3FtjgTAE5N0fNogwA+NpyzYdxoJ6fa8LMBZo59KHyjLApyEGu+TkXs +GsqwMgauBQD9v9mBLRxSiSUmsxKUMe7wk75CqqEGfDlm45QtxfE9SLNpojugY+Fve1WTPOnX8Evl +iEkVlcFLX0hurs3kURP/lg3cAD1WvikvzHnX3O9ZaXsjOqh7UIwr34rxwPfFrySnZ0Z3nAnYR1Wo +0xtmu1WtBJw/iwHkzrKxaugqC0DLH9i4NXydCn4ZWK5YdfyaigC8wTkyZOLIO0VF+hPJdlk0KKJf +stIf7Um2eR9Z9TxN+n0GgM+D1BJNZnYKfxMDH0lVDh1rdSujK7/6V40n+/8OS9FZlx+J/T8GADHX +c8waSfU0cNQvhXTAQC5VBWS6oOQ3D5WaBpqNjUCPikJJzkCbUa8yiYc7XrI09/0vzrKFcj7WsyM9 +zG1BGXk6ZD/wRSx31NZniQh32zoym4pL+PZyMMLZVWxrmRcn/UahdkJ9FyxpYUA1uxnhBvqvVajv +RoTHMOTdWbMk0ZO3bUtjK8hx3e7x+BPPIvJC1hXmvMmDgf/uNJuD2ta5vysMHLyNhKl9ZDwPz3vK +A6yqY/lTn3a65PYP6wqUk1EH4MnHSf5XRAUQghx6xWaefPjt8Zisl7cwOPksGUV6H8T2xRgnAfoS +zrmg4MWTHJfkJrb5de2BD+hx0lPDHogl2gevs38A4WPKUY5wI1nTcR1H7/mhbN+oSKC4QYUdV1ti +G3upYf8o4WVg47sQRAFxICThas16PkqPuSFKup2dFGKf6jGmZ7HlGeV+aC3bBGe84ANlEGK/VEgj +aEqf/V2A11xPiZHHE5PWZG3FcqH7Z1qsml+jcDhnW+y1Iq12W7w6i7x+BoKLHYmeCfSSB/iRm5x/ +EAsIehS03iVeOUWVzvSe/qCXh5Tleikp/QXsQbhsGdDOgj8htbMhj5afNQS3SAPbu1P6i38uO4fE +lHTK9SHd3VlBU+tTqtQBktdG4iZ2Sd65llQrHS69psbcCZvsRzWpfBZEOm5va7mZ5I4r0hL4NszT +QGAL8vtlbawM36sbbmQYiT9fnnvGouEVHGpAsPPP7rKfIlmN6dzRwbeDUkjlWzxisCcBGaLMSBcI +juvs+PVVENwkCU5/P264pmGm1Jqn47DPeI3qOwClg7YbgirT8RHNvH9SdhhCNOvDN7lA6+FXBdPS +JDgy7hVYOlKBI3NTK7GGoyavlTZgXVMXdlXpg6AEfvtYtIrq/dgngg+pMsftko1ZBVdSqAsq+uEr +Dn4JxKPjstXzvAQaM8Ya2z9wzeaZtoljG6Y8zb0ZYuirW5N+sNZqtjmeqMSPt63qbDVyNiW/ik3W +Keno8zbtkJgo9dRyc1cJo3MsUv4AnL2yHTb1FrxcHxcAwQfZvoFo/milnEYk5nJwYDTTRUWAZZD0 +NndG5FVMJJ6asMaV01G+ou/4N+WEAb2scxjaDzrjuHp70HlnOA5BzZeR743znlatsPNxmTby+ZM6 +tzOiOyq4HOaaUYCtDC1YtZHKa+fEBnXOWq7YRvNpGR+cyR4SxJh5qVT4AAf0mrLrtHdPeDiKgdH+ +uH8MIgu6U2kIGKI6xOd9F5vWqmz1ySv0Hh8e+LuYEZ7TYUPLzjHGbMrICA/3wxLSy7D9lHtepWxX +VLFvzQon26on0scwVSJrsKRCXoUW/QNrgGP7J8dWCjw65x5ZzIIdqSPvmkK7nwkK1CcozDWj5Ina +/k92/Idf9dbafK05mTKwsOM5hfOjLBK2IzuNAB652YRbWtBAf5H2fidmVW4u1zmSOr9pcTHpmm0C +C7VOnPNNVeXUMG86RZrZlh/wRPHkAc20oV8xlJXKSE5h/kUi7kh6Pl71lqPiGTPjAnNRT7FDBgOk +5+xvHk2b4LTYPLJRAlBJyFQqvbDV6Yi23Ow1NSuBCtZgV1hK4RqupllkqcwBA2ApKrUvJ4GPds5i +P1z84Fl32wCD9qKwfMZvCDNCRPkS/oaF7p8tja9uorMl2+H5PNth0DWY96erY9vHgHfy9YxoNfnH +nlwaUBoeC5iPQEgoyOIa6ZxxaEfqFZ9FkI+oc4EfU3z2zirYqtJiuFdQQmBxY9i/mvBILs9PfB23 +g5+lBbE8TDHySoH6Wlicq4AiJpR93oWJnNq5aD3naIEPg43ZU6kVALQrWX7dcyCNDj1391iGWYVO +mx6KaougslzVTJpR0Czk4g3yeHmHPO7Phy+ui+Xe2a7C3eTHPyQrS7TnNb3SMjmOOd5bQmzH12X1 +G+nFlac6lT4K1sbdgCn0PHjVftdRNztx3yEgvHlecWTCSoVYUt82auzBIVrc2PiU2s0RXGZcTwR1 +FMFNwj2UklZjeUyQnE+OxOzPPPxAHcM8IokENBklpzo9wO1MdGuc9iAeUiCq1eAZZFgp1gB1W8AA +sRytRRjUUOC08dAP7w/xlonwvPucq9+0BAIV6BfisxQPEpTnhg5l7e+ka+jmRmcJEEA1kXqe+sdD +5AmIH1R1l+/gPWYO0zn7Np05h29hjWKXuTL+nQAaDhVTyRUFPXEjNvzRWCrgNaf9RdStmOuxxH9I +LzHwUx7PWw0CB8vCSV2SCsC05MYgOL/7FtfgY1NG3RIepkDb5fUL+3R4hdBSVC/IKHczDf2tGo6o +uDxT4UMD5rHFR271w8UxnJ2oEUtxRVHzw4G+mONWk3RY161qE41VM0KoOqJMg/H8ospqVpDCOh4/ +Hp7CgOLIFiTh1gvYTKxtvGXFj+OVUPopm47NfFeHUtB01cjLb6bjWRL7QNGY5NXwVmz0nFsTVHdi +qhdppmER92Y7zO4m/cr8dk/ic+Qjwg2cGj2KXThTZBjLdlB5LWfTrOHjPq/+qZA8Trb6fqITXB75 +gGhs3ABGFD8JPUY5MmVZGyTVw0Zdcz/9YLLgD6TdK0LaaBeFgQdOm81ID3enqk8txplZZOHw/7Vj +Rh5nhmC/T/Xgj00Y/m3tx2pNncA5/sQVIEFYAiC4aI0FDP+iN1L0Zet/OYWYID+MHgJShCabzOlY +lztyOWq/Sp20oc8iHvNDbxUZQVljK8jpWmSkExV0yMETd1B5yqgztTb9XCL52n/mkKeziOXwBFW8 +RmeR082Zh7wtxC6VKTiRCCFoPyMLxL1CbDMDAiFtqzfIWx6fJgZl/ZKebX7yhSpREf9EyJz3FkHw +Ubq8pphqe1JlRv7/fulkeU3EEfLncSx20ktueiiWbCLzwRobT7mofcFeRVieZgn4V3uz935dKBAl +EC2+YGjpFTMmJkke7rADdr4JExS6yse4xF5G1shiHyeGE1WUaaSBcDAC+B0leOkDDbhCSk7ZRJdO +mVXmI4H4ziu7zhnCDvdmB4oXpW3GqDsfC8YYsUL4euSEp7/sejbRIR7q7aQMkLK2wEU80b0XSAgR ++q5h+UUo5OTxZSefl/bgvGvc65gWwq1H6x0tg1ue+oOM9fiN4UJqrsKcNggtMaKm+xS1tPri3QUm +lBHNbX4raJAqNmcg3Etw+gafQwz4DjZIcMGbiAknGY5siTnSiuGkpu2E+6iFjteE2yQZw+aVhIGJ +SkJmcK9XpNVPbyFqCAdGbHMXkK28L9JtF5zxIyL0nVfpmMNPJMaD8/uQzogyFElYUQa1qLyfJDhQ +WiGy4yRGpmNJ5LOwskphtg+zOki2pTi2+tRsTd35VdP1KtcSfwqu2ALD4ommpN1GnjuE5QwI00j+ +wB5kK1fBiZHwUrphDysuNFDwF151DGkYu44W0PytctL06/HySc1pVLS12LjA1IIaijnkANYgz1G7 +dHtfrfM9p2WKTw1qxyESzua0i0Z1lUK1dhzVufQraKZ478nR6lNKn1aGW16LM7uOjqeCUk4jWIba +gQD2G5Bze/2TsiQou/xxj2OzSdUSQi1CpRRCkAeRAhxnFd9y1fwQN9J+NBZzKSeCu3AKwWoEMUd3 +d8h+VaYv5aW4yerSMX6XDMqVSLs3vMfEVA4LWxGh6mx8lfeQwFNsT9LJdtSil753nH9fYtWMe8by +gea4hOFyhHzEWtt5ew24Jy4HlkAA+d9qeR15mWJ7wIUGHDPeo4uCIdDzyj/da9qokcMnJtdgx66+ +6ds2OaGTY3pM60rCk2g847X2QfXRRuXl2+oMjdThZa6yVdXBL8IpV4HmOF6VOw3/ulNFguwAncgr +kKVjV61NNey33bsMrtz1ZMD13ZjS/eZ5QFj25o4crg5qbnYCIow7V+pCcEPkpUR9OXpMIcBX6oqz +YjnP/Zri0QHZoUShqUKqmWVtitVK1SFc8pH5f5Vf9n9GN7VHd4GQ/Rv9Gj8ElIhi+0hXE7zrvAlc +pyANk6ik77Fum7RK2nZE1BoZ+y8JAjBkpHEKYzUFp4aj4t4ksCQZJUfax4/TeWl9jD/qH7sLhWb3 +bdw1jzr92zpuMtUHD0jttYoorBXO2EEpnFDBk4yzL+RQ4M8Wtz5xO+nRtTs9P0mA3x3xKsRy1qWm +MvFIse5IGvhvGnoXamfC70/Rp0uLFF9mGxp9brE6o22CjJEWIRWp/AsQNJ8ErpnVWPN970OtMrvE +cXbrxrCkhKm1Gt80TFAU1GyZnUhKUiJ1dXtOVY8+SWI9mszAv2Iha3J2smprgIfXE0DX/Wfyh5RS +0WxGa5gFDnkr32VhVeisEsIhvY7LGlbMyCsWXc7m9ShaZIkNCi63B3AHRKGuY14TBSFyGohLpL2a +83phdVVwhLm/Aw33wJQnRhFQPyO1wUZPUwmPge68pyZpmnGZMfZULD1K+d0/TPjDDLFWeLbXs6Nk +Rk5SXVvOp+lpwbMUNnvLxXWJ8p5HzBeL1RB+Fyu2RcmUD7W/tEP690hCqgFEZXYD3x+CJsanPa4o +SSCqes5NCdwMFowiZnNlZus1SV3eAeabqeFWfLkAslM33/3MiHQGZ8zOYS4qGcF4BB1yos+SA91D +reNZ4C4RnAnel9GrVn4ha5c8A4D/8yUI1CFvyX0Sl72/BPgIqFUcmhgK3mHnnICyTvkN0VAvFO0+ +a5wc5gvLSh/f4WZC6bjiZqJyU6Uq5eqord17NCAQEXpJjtJNOX72OinJqGXOkBUW0oBkrEcrzjln +SWK+8Xra3niNjwZAEdBpiXVVwx7MhU/MOI9j/O2kzjqZCkqn+Zxhw7AeeMvzdmF1rdQjNmzbkij0 +X0i/s9mlpOsqwYiuNSHsBPN4TEJsnVpEj0E7j4ExORIjQVjm1rIuyDLkmhWsE2+CHfCJ3fYzyCDv +mul2kJZh3U5DZpVnfHBY7wEwEysPHq0lZVV8NIzstnC9FCn8DxRa8X0amUNz5LTeAR36qtsg1eWi +cVreqzi+Z5ebs0J45AlKVm3mPBidlVnNBzSAMZY6iPFKnMZJBfuRkz3DcCCHBPvYhD/UwAlA4gh8 +W2CzAf8pctJLPLFOUtgDWXM6XizjQ5JpYKMM5muu5xXYbjbD94cjASD8P5IL60BiVHNsOMordBN+ +b89FrMK9qyu3HhT/oDeyhMzdq9WusTNRhkwUQbkV+/79+wIkClR9Pqy24U7xOUtXJ4LddEK6xaIr +zCRGJfMPJYRevixoxbIdzDVBhNOglxauY6WxIHt3jR6sNCFO8fJ5BUNI9q1UNcdJJckWx/GNWRg+ +Vu8/G/vEGNUiQOQnPSMq8db/4nCKMl5jWx8zcgT5u8xCXrFDXQ1oh1w7nJqhrudlhHRkB1CeN7ar +zFrZR5Q3t84wZaTMUP7ZHGAGTCSsUOZyB1AFs8nz6w7ZygV6GfR66mP+YuJeCZeT7gDvSIR80Y5G +aBvL9yW0AmNDWsiC5A1Fou7jwbt6EDTlZiaqeq+tfGJZNLBbyDNd5qM0P/9qmJykMt708+dYPgt2 +YDTQw6z6nMGZkW/nyncZv4G4mrYfAI2WhTl7xuCc4rqikfO1nL/fJRL7IOriozE/QeocFhFtLZk1 +jccDhSrk093w12Mnynz/kU6FSVMGW9tJycBAudBK9YVPaQBIxwAZMWCJ6MBIxRBGtOluGD4e2+qZ +O868hlcIHsgXCorD6iM5E6DYsq62Nrvd0FF8mcMIE9SmZP8wvKDknxRPziV29mFQNH9vzvoOAOYm +iFBUH1j4QcZQwvHzV2cEdkWlllHdd/qpbCnar43n6h084MnURmPzWefcA3xUGgUHYcLFjcMrU+b0 +k9ZvrB2QdQtqtFnmfr7eT4I6Ab98FzCqnuG1n3XWPRi9ykhCOapR/6gL7tWuYIrdIk/1Y3Q2OXzJ +p0dZYrbaZi+DZSkae55jfEpZP++HhYAZQ+hDPwipnVLjlJ3pOpNRXvDdj8TVaIX5s819KctwfdAc +GiZfCY1uhMbc0mgfo+Ka4YxjCFxlVdjO4khcYBczHNJy2+cIQDuTb/8UkBCD8gvRBJJIoVbCElbt +jfniAsZzgwl6LBpej+L4lXEfAicek9/FcMrh+pukNa80iBpocCR2H87l6ahZB7Jlc9XCrs/SEi6i +AWw3yn3Tb4/gsl15R5rfAI1T+6tRpAOZg68lsmhsyJPefrbLLgVAqraHYHhGh3LhfZHDwOHEps8W +kKqRycQLY/SVAq64AW4u2UvjP4p3WfUNI8eo+mAXT7bmbzFFcA9J4ZTCPiE3GEg9bgmU96Cu9Kaz +inxQtdyvxDT1lGfl5KfVUAr7fBYOC+r4bRzzseWsROsfkeVBBkeC6Ui9OpqU3Q0ZqmTGpj/28Ff3 +OVzVe8tGblio3sWlJGyckqyYhWmKyeafgeBtMinUz0zi6XOM9Kw+3eAN0hLGjeTIGISIldPmqeeV ++uHZzTvdbqlPF+8QQCxTRMKbdlbo6+b+r1pIuqbXnqiAW1h80BAbV8r4e+8Phuw3zKPScewjA+fU +ro6V1gcaKbkBYMTq0f29qFnOFZ8v/6w6HX5sNZKHX9NVAupiFJ0DgENAZCJXchCuvyVp+9ZhBTS5 +OnYEMS3ayIuO3blQ7Qil93/g3GEipDcpYRkjtOylAXkIBM/7ghh3ZqDUUgYidBpmS1OtO2UDJbdj +o2LpLYnG4H3QzQessCyGdbBc/zyeQMsJJKIOTRkpQf29SyYQRV33EVNDptKmTSW2dCO2ul3FbpKc +gKM/KzM4C0o5nXBN53hJrk/E980kf7gURt0O9Kxv+IW54Z57JQJu+oNUQ7I3tDCaQN/8ac1x1ZP8 +b66TFx3VxIPS/cVxu1GQazjTyEnw0EWTeOgqAprVJ9w4Tjv1mRX9jOF0B995/sL0TDetlHAMJN8O +UKLe0uZzxcqKoEoA0xMiVa0hJJYqyETq91WG3e+ykKEYECw3286AHEbhJvQ4Njd76/hHq0yK2GyY +BXUPrJoWrbDvCzg0FFVmbYTnyt/v3tUA9s9pXiOlJ09MZTWAqnC/ytoPg9uKlnlPZR6wFRQx8xuf +GWH5gx8812FQ6E1EYQR02WgOv1A81yGEZ2Vjhiw97R17HeXlYHX0fGQbVN1p5TvAy3qFOn8olre6 +VsTuaBiNadkYz6un8CRH4jhnQ66dR+hPsNvWqjeR6V9LZikB0yy6l+yp9BOG2Hgjfm7BbJVPcJIp ++9metzNSjEWpHcOtF+cnNj7H0CvUroiuemt56tnLlzARFjeWlnhlQSdYzWTzTfb1l2XyS9jNN2YC +xMaREIdVYap2eEgvS/GxHxw77EuTUwdNcrlNAJlltYvhswZXfEe8C+lshi6pF6jWSAnADXi+nVLO +GHFZQM4v5VntGjdbgMgKzm/D5A22G0Fj2lKQfoQ/hGNxf3AvIvOxjFYRIEhjv2pxAfQ5ZD04qd4P +lB//EUPUupF3bKoQFDPcf6s2Zs99l/9uEHODZiC1HFErZHhKkXumiZhtdjnPy/eaZuOlfEx6n389 +gfUhk2xwk3mGi5LPoVXJcjdFzH/ksIWGKqOYcvKBByVVxlRnaGZ3fXeO1NNoqt7W2Aq/MDjZT2UH +58pTllNgqV2dF/70ZOXhtvEu8LlHRsWGZd8j2VAqAcII8kmf87u+X7QmC0Pp98j/y1zsvj00otni +vlPWDWp9qpBbrVf0Eba5Tr5Hf8agYTe/Z+/g7f6oFFHmlZ7DzWaTk2KmeZxlN4DsZsmbaihMhs0n +0r8eJ0eJdTy7lbQSfOTgPH3482fGZHPSqHoXeF171nkynnuFmp8/dqla6UxWn8AEu7YsPqb7YvS9 +5Nsk3Qrb0vF8UPAVOvM78KgiER341Z/b8UrDrgyby0+dw0J4WZBVevRl+SPMvPvfkT028EDx8awY +12cfkx9ymPxN0TnhUS5QFowJ+YJPefAVayA0wJCDUCIZoeV+pdOUDyi9dvI3Nbn+H9N7PAdBPG7Q +bYAyds+IFQhE1cEqG5BsToobl4z+TfXu4I3TdGLsvbZUKzPi78l8/4GkfMn2j85A6pMRmEYJtB53 +ahvMlSmG/EZIrGUOUSnVe/Criz8EZ1Izmcbll4pP/+EZX6rj3xOZG5v6Kja6PGpA0zXMhlAj8YeQ +Z2yjc60HV0DmYr0cAM5UqJUuRcOTsKlNnAduoxpNf+V4hMkS/UbkZYG+XYprfg5bihkgbFh/09VP +13MnG1RuPCQquqi2iQv/hYhVGUUDsph8MEjLG5nUnhU13Q7Eiy8SNy6AtOyU2KMold+STJsTJi70 ++upLgKGbLUnMPfAGgCGwk7sIKFJ4Iq8rtWEXqyFx3jAnmJolfKY/KueiPFO9QPZ1oo2cluTd5pTn ++Dpd5AQ87z6/8VSq2Mo/Cx8owJL0gBFPD8S/y3AF+zxKDjeY3tMa25A3QzO9e7uAA95cKrnlHfq2 +xSPcrd3pAEkPYls51CGpfAmiN9AYaP8/IoiJNW3AoEJ4Tnr/UEv94ibBiqWOBu+7fED7wkynqC6a +wLIPWC/ShrZ5GUKprbfVrDuBC1bDvKimhnYmS+MtALYKDA16oOfDJIqWyzToOt8E43raQ7fdnxyj +f5mATeeB/QXKPpOeEGV4fOBF7dpW7iFcPz5u+0lmUTqjy6XnzSW3K6mP3S7oZh2dkJAKUJAq5pR9 +fIqmSdlEbU9Pyz8OLJm7HgWs5+mQS33AGZYUiHOQCIqNBJOn4Z9q76bVxUkICxCWO3M45l1dwj0X +rgTGbl9oVcRgjCfitk4FeBXzT29X0oSh9bUWvMZW1pLORO/kIxahOpg/Bw4ItsinvijCh17wYvFh +IMTbMHaA8Qd04E9hCI7aCl6g9JpifMxo87c5ruKaKIpht5gGz+1A9PMzEGYrH1v7708p/pbK4zbq +wnFlCYD5EbOak5K1L+zm9CqHTSNdc2MRAH/9Zpufh4c1MpLtqoqJoFEAdKvpZwsrzYLnZ/Mzq+Qt +IW+s5GPdHnhjclE2XadSHmOeS9FTeASk3k1WXMRu1UNGMfBQ9JpW67QFgW7RRaZk4gNFWl9aRpbl +/2eO5fTLHK6HspjN7M8PSxHWNKjE26bW/+jJunNLpKfThYtpffeQxHDagv54vdFlITwrc91sxRuH +9igvsYDluw+cgiGeSy823VlY5FnLb7r+kPaK/iX4OyIfq+kOH6RqUtYDB8HPzPUMdXE2R78qfsaH +wipjJnMZH0196QeoyH75ngaEUwa/r0JXecFt+nbR2uI39qfuUCPuryeIQ7jJhN/Ds23SShoAAWao +aFHIoU5mNBNufCUSnOZ8qSxqcAq4ZXFl4yT8XLUFC4LysEjCZGuU8mGY245VQ0OKev0NLFuTFRU7 +mUEe/RRx/A2bSpEFHmFXelvuevoRDFrA/u4+XPYeL0uG9ujExdbzPmB9RSD44a6GgRyTiVhoc1yE +UnYD1vn/v2kzbw8tKGtBNbH307+xI5UWcmb6zrl6oxfEP4TnexUWvFcfgbvW586sqGGss8huJnMw +ZxuIRjB6nbQM7k9WxVkF9xvxvGP4DDiSwLb8F4HC/vL0oDNkMxOZNGr8pUmy5QpM/wVtmvcKmb3I +7V6UDKc052VyXIbdmTn+SilcnH9OMmYBM6o4Ep2tSPvLs5OIdQu1AgqLGZT7vnwAXusv4d5NLEjq +wQKXiGodpv4khSX3GqRmn6vF2Q/7zX48+I7S9SjqTyKXcwQLYeNIFwGgxvDotSQvRqu7iI50Yhk+ +STJh5ETvpkHVnM0j2OV5RUZDv8wSTl5txTIg7LfD4KjhJvbdsE8l1L4lrES5N1QoIoj+SY0+pG+0 +tOnJBHv8+GaXak2XV7ky8eUjruLwhoTPSfHCYO16e4MH2U/0P87kw2RC+o3S8WdqVbJawJvesPFr +uk14R6olXF2Xw5yH26vxuqCyTBQQGp4AEF8YSAyvM9xkFpbS8k+/UX4uyfKP5Jfj9uqvZcbbnpQl +5Gu0Wy3axZInExWRXMdinZP3QAB8aS74xIrKD0k2+1pQHQ89jzHBU/hoCiliBaSsF2QpyqHpzfb/ +my5DeZXN4IaoZCWhZOzj8mlrGVHqtDWzOgiNPlxLvZ6HsvUg56CN4+Zf5218jImgoEbY7MGTa/ZB +WJKHw51f++hTLhEvgYuY3jGkKnmmvm051imGUUjwSNcFepy46iwmSMd/PmqOm+s2Qz8XhcPgNDr9 +JckM60ebhkLQwYHJL6Jw2NZiqeLRMlGV4zXIbGtkuVWEY357lqnTGDUwL/Ez/6coLEipwiLRJVfU +n97puvRuduU8ophUvywY6HnWLhsA2vk8yiqIq9WiM7KE5GVxbH6ULbq7/O83gkomQ2XW9KUg5zSW +oq4ZV1MoUmVtdp3kbNPRpikTHoXh01Y9SgJFm20rsbUuJLzOYY8Qor/tn+m6UiRwtr/rrkUXBfKQ +e4jOW6N8r6CVaYq9inzKxq60RGyZFr3TFqZYKdSeq6QhmDVqy4q4jTuB38l36YssVtp82+pku8rd +acIur/hI4vp+TwBGF6gbd3naHd8OxIJrgEZswroBD9h0csRNDhy5PVjwv9phKbQs0aIBsewWxIiZ +oWKd8aOT4mq1SivFZ4o1dHarbU07EpYDRVKbxGAXO9qFvNY9fyroiozrTupVIQddKwcSmu0ubJNP +KUY30AG6ZVaNiqhgkIJ66YWN0muqu1DstggID46zlS8AWVJXlKJ3XV8AVb+jpLQ2p72350AKmtK4 +VR0z+9c0QBSLHpUGWrCAh9RDI0I1EbEsWxNL4iS5saEni074UdJNt23/dx2EY/x0VYBiU2GncKJW +YnGUqhNYb/5dmOKiAbQf1lmjQg6UWNZCkyH3wmaEMq605rRSOXLCntB9uiDQPSYTWlSTuy216C5C +QmeqgWo2RDFKxzp+dKeP2ChN89mnCa4v6MiYGmZQi7iLdB1F2s+j/ujdEDZDa7SNBzahASK6H2js +nBNhHZNczsQof6wV/rF086yCnh9071lgc9/qWfbw1YnOlEcOrBcgeJ/dcoaQzx8ZHEVMQmffNqvG +0V6qpLLMuOyrYP9LZrmv3ml0vfD4CJKu3ajHbRNH0DBN8rAj/zUlmKIlVicKNlWjjCp/TYFrkNQz +YYYvpsDwzZpcu/QOeEW8XKMrABERqgwNwD3eohlS22ohiR08pu81GCOZiejsJkVf6jWgdQdrxH8F +Q01KmkOn9KY4Uv8zywpOs7C1d/uEyYFlsQkBO2Tv0kgCkpxL30WfAZpD7pdmr90L2dkqtjwfrOyO +dPutZPrZ3NbKie0mGjYnbYdnCQcp0Dkad2kMhREvPgkM42UwDDvyDBmObJwaTyz/Rb9YSr0aw0L3 +tvy3I4oWTk48ElwUeHfKo1fe4Zoa/JIMqBL2lXOsPEP9NLae8o8hzTcI9NfyTfHgSKT3nrBsgiUp +iOG88zKl06k0NkVpftjOEH/wKgQ2Xhn2Hk2gO8TdKmpjHoHwFCP+zIm3VKonMrbKO1nbTjihvm1Z +LxdrJaE/VeIYnVVXO3tMkm3PlXRR6zgp1cPjjD3BCG+OUHrnS7wYJUqfKxN8ZlfuwmHhq6xOUzlt +SsG34fiouiz8z6CQlECxD7DCUmFX+O3XJanga/ANx29+C9hSIta3FL6fpiQBBrqYDmtGCd61IzXY +rj1i0Bhl6tSODwC9Qhey6dMWZm6hKjvCr9aM2wDmM1iD1jTIRhKgu+skCdvZ9EGeu+x1Gcr/8l1X +suYWwqtzTqfc+ZKvkOPXRQ4vtp22LBUy+ycGF7Nl3768KvZK9z7I1it1p76bK8HTmDjIDOCrD4G6 +hHvde/9PvCkC+g4PVD50Lq4nqsH5yJoW5xKkq1/fwSPuzQ80vQv5KiNDIkfDNkXHSHjm6rE8/Msl +xMo+VoRKGJ9WR4QFNA2GjJ5kOLjnrJAjYpy37jNi0tZmK12bmMA5OcSsgwPc4hg2CPRErlVZSwv8 +3tMMnQAG/euXM3WGhErx3VYvRzZyNpUDIseaHSXnBYhNfaxri8w/xnknWBHwTZ3KILGjtOUfITpe +peDjY175jSqIgLxKSk7wFJe9vSFxhvDfFPnxAMigPaanhr6xHj90EeYGuv4W6PAzWwWbrUlfeWZY +8CYNP8J7FG9n2PQ6qHbJeIMWl/sZrW8R6H1pc2/GnDgMWpXLQZIEYqdrYlVMnxyAshVAkd3vypL4 +drQlIwtXBgCbTylIERRzZ72bhRMIE8GVQ8D5S1CYhIfnwmDbxWlk1+RxVAnFs1FWymW6PTAVr1bd +5mxmHLw41ihv3IZPrHCETYycKriVUha7KeBZykwGh8N4P78h4RFAgIJxpVBuRfnVNZaWoFvPcE7N +p3V6cLkVCK5TcAITUslFifig4Pt5Jhdt5CFL42S/UIIB8cKy2puPnJ64/0vdYwuNF8O29g64rDth +59djq/YmKqou+qgGIHx6hGaUcDYv53gpDet54UpFvmQqZIK5bzFH+Bbgw1ITIN4upaE2vTdf4pN3 +X+V346+C2iPqgFi0IodC9yKDRsDNaLOBNSK70N5HFWSJb777l1uCdJ7jPpdVd6wDm0CdZJD2P6eh +Zmmp7cEKD9s/5wEFkTXXd0unhzNF/2oxZmgNr0lc2iU/brwizrGfj22b17Suv+40nQstojtSckZH +2K6gkr1YWZ8AADmVGIIaMNcozu1C/G6SpCyTFKw4K4TgvBMy8a9UI6LJF2K5YWEqijXPHUk1Qmhs +ZwGalLSQQxpi2EN8AUEaWqG3aR66JdTATuAgDmoCntZtQx4hvTe6rQ4LVfHrmbFtRmYmTykwfeN0 +AVJz8Cc6bcYkZuV7ozzYLL31X4JSogIfPFUAE+Qk9duGA/7h54yeEWgTCn1IR2bCU5QFF+w86vup +pGKF/LzgEkls5ToWj40F6To8szG9LwG/cg/d+AbMZwwu7KLjqFH9UBY+Ob7K18VdpMXxKsAAzCDM +V0KndKCVjWFeGWsWnD2OS6eKT3OrxoJ1iPl8kcUmV3bfI3FlWLMmNdp2Yxu5C9d+ssdt2OAU7ffX +R2ZLIcXtlPGZNFV5rOtp/FgDDriSW8oqWMI9ouZrpJZ5FtNfUmmfVXb0O36+JrAM2p5NZgmbDUdI +Z9Q+qgmPU8rv2xCS0FhE9R1tBLnRw/GF+klGOAdi+dJxxeajphBZMxlQvVGcQG2eCWHrbsb5za4T +HMv78strXKtj2ntoySQaHR4hu5rBhnlxH+pb0E2JU26T7yVGNUbn36oj9WmWDQa5OGrJD3vcBZ+6 +4KenYrO6Xy7WoHXpS6KglOCsOuuVHYlnwsfQALehyDSHP/pEmnf7QqRXNqA5mUT+3iC99PSBtXqU +mXxSX/KFyeDAdqzwvCE2ZwY4SOsPONW0vlHsp3BgQp0MEYOHWWBAnd84eHwCiS+/8rz2oy+N6t7e +jKzE7waoGHvh+0OSAPJx9LCFeSsNr8/mWmDc+4EA7tlvryN4wtGX1ZUVMet+1+AQ7dkgE1VLRf2j +YtfZD6bBRkt8WZ8Lt70WL/r4kzI4fcyIznudc2xkHmLp+8E0be2182xylKUbEn5VTGf9kx77tHdL +Vtv6gjPokzJYVvZloigcUlkP3AcV2p103oZz9Y1CLmh+4IWAA3k/c24MQrnWfZFlMf3+0DUte1TF +RlExjZDsRAZqxbcDR8VSJTEg0mAX4SPpwyuA7BbQQzevlkeC8G/iyTkV8ZFyz6pFFfaiiqyIdZTt +ofrCjZ/HsTci7CyH1GK7/crLTCL/VZMx1QMA/RCbPyZ8ThufJOV4nUjPtl6SS+FGKMljDQS4Oiux +4aujRIBnI2RDOYbPv5/FcQ9CpLYOpOmdis0kuMTKKj9+ONOnODB0SNuGs6armffYiDg8XyjAH7hD +aCrFXiZ66Mmmg0fCF0kFe3mfSzwO3BRmErx01NsNY6mfT9egAe1q+Dz4sXQB93e5g2SxCZckMqju +7Oui3KkD13ujN44q+Vp+TPA3fURlp+NCbnFyH8Doq8cEPqeF/71lk68m2XHZ+7SeC44c0SkqsVTf +bcfaDQwFY8y0tPOMsN02F3yfKxB5Kzf2hEH1ZMdNV8E+wxLNvqKVQPHF+fRm49Y8470mPy7jnFZb +xQB/gHHGTEXNgorBehAIRbeaDfpY8Vz2Q/59/zsSK8d+eLQi/E2JnGMvt5btdkq3hBzmKHrp0p76 +C/s+SMgSWsmMZfVmE7M26cUB6Ka9S5ySwIBzcC+Nq0AxmG8FbcUOVA85axHaZw3CClHP74mnJwJI +qNuV5yBhcJCPp6e+BcKGrqEpQ9UjeePFCf2nSNPaQIJbKe2IXfSAs3Bw5SjwnDTx7zN6m/4zFEur +wkephqP/xkMQH5fJ+Yt8xhGCOEpREWyhT2G+KT+Jr1FESotdmRsVpPu+HgE/WkwJGjhhEQzV+ovv +Zb/o9FJ8KpOvAhyit+OhgKePywuNTVyvwDiBC5h+Mv12PpnMvEahuUFxciNNC10sT+LIBx6sMw5U +X3dWuxE2I5fcYdHuPos6tpKTIlPha5JauSdH6+vkqWHvyozXH7czYqsVlKvhkvzxiiL+dgv87bYM +/qAeuaq5atX79F5I4P3zC7G2tNXPUkm0bsppbkWE2PNwBB1uZBGmENyL1FE43ujhe1f98wb3/9YW +TFzwByqUUhDd0ynBQBZahDPeWPAQEXHdwun+wEbtfzkxcKtIB5PgZVbP69+BQZujlGurjf55ADD6 +tYc3yPnLrbZGkYSiGK0YOmz6zaBuOKmNpNzef5exZaFG9BnX2dYR7fLSpROvbDoWGYFDiSDYNXN/ +hEuhfQF3jB3JTfiQYzapThGUxOUbqKM0Q3216cmkNxrz/AmWeh50iyy8wSuyQXONjUwNoi4P8M/T +BU6ZE3irQIf53zDf9tkWx8eVoq0FansUJ36tfPGicN/QfgeGYtkt65nic8t64PKfQD43mtRqw/rR +/z7dvQKR3t0RaxGUAoQelrKNB11Gg3xtM6j7FZNLal9IwCQA7Q7T1KSD0SiGBBI5VpP0APPbvCBD +2KEmh5PaHHOTevMYyE5A3sfbdTLJEolI7LwnF1fAvnBDCRN6oZhlntHbcwTZowoWUZs4PkktY1uN +UxYwb1lesUpXn6RQohML2T3bSHJJA2AVtmxPgceVwOVzCafbeF4AbXFuiPN6KH59gTU5lcQnF+bL +O6SrnsY+5Ae3HY2UP9++1jUxYF5U8vrfg00O7MBoIRU7hHA1zuuo4yQfxnADzZUGqxgWiqSAzgNK +YbL/CkDktBi/PfGEgQtWjGSRK+60PWr6Uaa1h1mHeiPQpMhGKqeZoFe/3lb/6w2pmtdBRmsnCFgn +R15GGvGpmGDlBxLBSifYJ2frJ/dYBxeVLfbvJ3xFrmvuFW88j5WtF9jy96TKLWBrmLE+02h4bCMm +V54comZNUCdfwhZIfGDLx5nG2q3LmDfG68cjSdN9UhkHjaibyIfbFKZ8ZsAfY5z8iASHWaTkRh5Z +5N9LfY1E2sVTTc2vwbRLTtQtJfDD4PsnE+TOZlsk2mEG4ryqGPlOZwFQJTuctGDFurakNpPUrOjt +sa5da5qFIT6KVQkQAsk7NnUxKUEEEwAncMFssJ4rOPsBsoGqYqSdFKDuqbf0NYxKLTLe55X1Ia/U +NsSQMmUV9z8DcwBZt/DzqFuSDMKbkIaY53dEdIv2ScLKWu5TNNrejG2/w9aA815ZsxdCfc07k4Py +mJN6vycX8vyN53Jdjlh6iRI/6frDE/nBOcl2fVAbEZ/zn/Jjkhfu1w3FvIWMMmO1LGhDNhboWwON +CUwDRYGiEz/0cNVt0jZq5O/2xbZcmhEds08dwlTMOOqN802enTqJco4ga4taKczRLbkw+xiVIHa+ +vfdnLH2Fb1jiz5A6CdfJ19xH0+liGieJu2jRzrYAEJfyTBflJJKln58q0EoHgD3jEm8WiA0GmX0m +UmTi3Y0Gj6SwfoJoo1kC9ci8Np337OKk+uqJ4idLxXgpAKk0Lhi1B0Q/ZO4p9sX4gCSuf3BzJFnt +zAN7HHLmqqcDQe5vCLUEg2kMZl9aPFpRuVlMWDYZ5BZjo3DL1xiaFbzPqVX+gfq8bhPEF1ep7j5k +HtA6IpRVr6fDqeXsWWvGVOZDZUmH63ihGrq6HLyvn139qdRjFFofhoe54FCGA3LWWWsNViFJXrgJ +T+329U07eiCJjTvODAaigyYiLmKbBahofumiM1a0Xjsj2vsSD1DwlQuXEyhRXpEyeiB4LyeOnlz0 +/A8/+TlgPHShjBxJ8RCxj2ynMMQNcoDXRxIlIxtXjwrKp0B6clloLzSjs7MNKX7vQKxXddpSmYsV +KjPHiXO1QNOsVEokpiNnA9OTdyzg+Z3JZAZXZjeiSLFxViJI1uDMSrNoBPJqBs04rJR/U41oAlmc +KMLt66k9nm12RID9/VBPdwkrhpgTI3jcn6+HNJ/eQVByrVKTtD4ZI8ZQ1EQnxV0YQZTR8HPGdabC +mo60AQ1y6aqatQM+ERN216chO+p9RKZUhUctpm+BnrBjbbqBBKAHGRxZ7FJ2lCaXkv7AlksJoPKO +fD4G6dSJFWHkYFnf6zYV9y2iYGJilGU/gBGJhcR1O1x0RiiytI/g/R94EurLtmp28nFrwkn++ZWK +j28fQNLNlJT5EK5+bUb85UeGT5wOKhmuNjEcAcIc2S7B0OBDcwMyC4wHMAmxVSGJVvQRTAHMJPl1 ++BPJUl0uvDibekn+uejJfyAyZ5SHoDpjhZKOAAEbJZS0Duav8pfnV4URmClW/rlJ5WM/XvZIt9gm +u6+bMUcfe/Dn6Jyqo2YjRIi6NOObeAQadvsnd8N3MN0PDUt+qzgmsSX8cuqFIOoA83LPSD4fYJPQ +bQebD1CMvosWn8ynJQg8EjkU+BcOgP/gxuR4nQZ5UggaPC07WIFk7v+LAv3GpQ6gOibNU2A8mfQ7 +/PIWKMGfQEvyUsEuWml98MfOabRAvIqfznKAx6fBQZsI/amKw0x6q7BXFbTGJY9d7Q3Wg2JJgiX2 +I5FPobGDuvHju5JdZkvYmKg9bBhRp1KryDHkWlo3VWaRheRDo+QYItNl3A76Jg+kSlDd7LHo3EpJ +vPi7SluM9PO5JYfCi4rfzOpzx+19fvhawJRb2kCKNRH0ypJNjXqd4TpFPClUYuCMwOueSCM7Plhy +XRIzq2munaVWEBtEg54Yh2a4ZQBX99H4pXSdjZP62t56xkSu5IkXC+j7VPVzbKnYgyExobvknZqY +g7h4nk8FmUMbFY20qrDEy+kDW/H9HjSfUEFwGr8Sjosp2vuBymbrt368a+M4H7WWOMo+js5Opc3i ++bwUfBJ7RPR1r9cXHwU1/dG0hrMNCV3DSqSuBuNmBP7+X60e5mguQiG/dlepDUZrYWH57GzqSpvK +qDXZA4wXdEB+uk9HMZzQ8u9AqVUoA7ui2lCEAylzhsbpCkINXbJ2gM2OTTHVu59BHIgydU88oQQr +hlefsfEJgUhcHusvWhMHhgVhqGfrRG3sDkDpoIg/2erVb6Da6C2yIjgvRib0riw3cfeihURkFpim +LujsGC8n4/JPpG1b08FnnZ4d4Xf4DhT17ZWdElciprd4ppZTznSDDBIIPff5Vg0DrBkLeHGb6uLV +GoAyLibJE8GBvsR3SyV/eJnFTTgGDmiha8YwqOa7JwB7HrPAv7GzJEgSDJvWpJzmt9yt/MqooBE1 +FqBqfnAFBdN0aBYUVU4hjVCwCKCokHmP+HCtwv34VzV7YlAjaVewiWBMAT7HA/56ebT+cPWFCvoy +cyMpQsBAAJ13G3IQSsjVGwZDhGWGqTvkbXBBbgwqqbF4BeF0CBwxYvPiPFqt+ZLZ4Pcl7ESchDQc +hj4rF+SsMgV5wtoYXh/kiSpm3iwx2kRrIozqLQYkC4IW8hF8gAZD6nKovYlDLItGVnnujGl3glIQ +8agNI1fQgYDumLj4nd5ViHuYfBdm1dsoKzXaEubhj+esf9Izf47cO3S8np91Q9orSvj1TK3mJKaW +N25oABgPeS9CqJer4v0K0DIMAjxSsJXhfkGEDF05+nmRjdpWtL+yZJva2vv9TAI0Uo7nRT36FtCW +Gbz0vO8xU+jghdQcXTzZBiAcl2JuRRIMWArq5ZykBAjKa0A4tiu3vNwNUZ7v7VO3/whtFjwn0GF9 +Lfhj3bFg4i/YJiTX1tB7LvaFIfJZiXbOvjUEXznbU9FNGl/X8QR4yzIJlhD3SMeIHF+f+pa4436n +ZP8ix/QX1wB5pCoBJDBkHPeEX3mVV28G3osPWlh3vYUZaUYlhTJeTwmExxTljK3bJ5hVEA5mDpS5 +gj5sUDIXo/lIfYwJsbbRaLR0X4bJJ/I15aMBYsSQcou/PpqojODqZjTxSKpixncfsoPhPn9NA/53 +BunWIu2z0zHXaakT3I3aIufIQiYE2s9MWLNHwZPym4v675RTLreWMXz0jKBkopJ9JxIgNLQQxFSZ +bJTcXwJezPfgSwCUnL2xfD2PIuVzff4maOuRDNCyO+KVPSWq0JYzfNwXkWX29lpO9bpQzAlu4MNE +a5RuQzPxT4JBZUCGNdxHr26WNtyavCzKl15ceN011W+6TSQR7WCy0hhH9aFArwc807mfwxz9IeZq +5QBaMiS3UtHNOL0GuYuozKQr6XnCofDZgf6EdstsP9Q/01XX1RcdCcUUNC+xMdBapDoJSk6mfrNO +5ZCKzl1ciKcg8n4K3Ta0AmiIfQhtfzhn+AJ/Huuvm6rBlG6zi4W5BJhadhtihCvzMTP6+I80hC2V ++G3Z6NcBpOplidA2O4TfvgZtE6GJIgzKO64l34mxvtbyoGDFJNoCl3rdoeFQx2dKv/aMqbFOhGyb +VUzjpCfgeDm7tNAjHrADZ+KEL1d0gHs7XOXU2KmgP722qB4fQ8K9vPHYS1Le2ZIIIvH9IyrVaNvJ +kkhA8v3yKwA0aHoJXXXD1Br/t+EZ2Ne22nycM6FQj/S/kAV3J9Z6L8i6j9mzX8lNmZ1z7TVFADxB +ZgNpoKX1csGqSTQQCsSqPJFVZh7iPVDrP504mML3r1ABxDED5g/kHEbFj97b8JLiAIquPSyYbpPk +3b2pvb6IAb3CRQwczxoE9iy2yB9Wh/EhP/UT/wymQerN6pXZJzaDoJWuVPPocWoWLO0U8JMFDP5W +OZRJ+NPSalLZrEJ846BjQCFyG7prESDf49GVFpxWmNPUM7BTinA+EGsLs5JtoSU+r0Dy3+V29MW9 +B0cR9mT446isxTLDKmhwIsVIiFjqoCWYXzJKlu4SbajNCVjAu47CQiWuUVVLppFHyTKdZNak60Br +7IX6MsEXcOJxwNW7P4fEKQkAidyrRf3lqn5yq51bD2ppA/tx6Qd4MZ5Jk200TJvfHo3Olc2nWK7Q +O4bfpXlEI+zzaXxkFya0sERsWdiIjMwV+ZB/sKoEUFHKbsDHkqkwYCrxmJke8wv54erQtp6Stlcr +pkvUdPj9bHnegsq/cZrI+rjPPfFYVcKBHRDgNahVgIV/k5dhXTtvjsC4b0mdhbnknubBek/ZGiVH +IzlrFO8F2aWy6fSEgesjuj7jBjap2Hmaju+4bsj9T+8ErHuAU5tWd8lIlc3EnQe/XmRj+33zUr4N +hGnIMP5KwxMlT4Ao/dGEv0j/8VrK4tWxVb7tEsk8wuHe3SbbDnhoX85IuYunrvbhT3xiIXEvwWdu +nRIa/5Hj4J21YZvfrZRC0an6P2TEafF9vhGim/WIAcVUUO4euvnA/bs+V6iizhWkoqhx8HjN4RLM +afVduQvRa4L6ZItQPG/o0V9VPebSyITlMGlaEsZM3UndMTgYLAi4gfEPFHGaWGFE4WFR0sfa8fF+ +SNWO4AMYxLWqIL7QdoGbcAmhc3/St0f6eGVheTN6D2DAENHwy94bWZdiJxs+l8xzsbDKpTYEUQWG +76WRLNwLgwOmH2KbGJ/OtyQ/eYSl1uGWVDtluSHsULOESo9Ccnsp2OTQ2dwzrYMJKvVlzZ/pc8CK +kKjOvfZ+0CoiAkiTnLpVe/jW6ppgR7vY2JBA09otLOK/n29976tgSiHdN/vJMLbYYUE92MLETb/Y +7dSjaibHtlEtx6Yh3EeEx9yNYXBnq/t2vn4I+sgBrqgbKDmDv0ZOovSCxEMsNfT0PtNrxDlBjKDQ +p9OSIZMXNTLnO80LQMmjKwxSxM4ElLyAZLSQjvtN7zsriOoj9wCxC2X3Ox5KQ4/aGgJj8xeV4GjH +1MRyYu8G+Eq7vTuR7gBEstlKG/RdwbkfYLOdITx9JxSDLy8LQHJm21BU7lCze72MprEk6a6bCxHl +DPc0UrjLXgKUGDbSl5+fMNfAO30ZPvmO4S7K67kYL/0vUwQ4PRaK2cDH6/k9ymkZ9H5BYgWOsedj +T5XIl91IxLh9CGPzDZaYtTk7U5+VgFAOdiOFNjZokY0NN8fRwblKeQfuQKDO6g23ljx+fQtLKxp/ +/L0NRBXbz+Iz7opcB6yhGg3C1sfvDg83gzZ2McaIq1254EPYBesCQL88Sm5dhLdz81XMUppwD1sX +iZbp8tYa43a23K5EDVvUFrW1xXSQih8wbxP4pxinFqGACpQhVl7jAJAtolN+5IC8jUuuNSyTXwmh +RFi4MwnD1OpmpdsI3tXhnFVYveP8g5RFUXgbgGCDvootvorqIcwSM9iKRVmYo9jLTUrNRrpVopLx +V89tv2WYd979r6lONHVG3RYxHQhJL3v8gVn6yHEivTogIsMYGQo/yz+E57+RNvm+gj/4G+735Lcp +wmZ4idxpvXp804CD6ty1AeS3vooCLIT6NTKNqe4P6t6bQWONrVKcgIPCft2+87eXJFlpS2PcDnXB +ezFb8KSnb+HB3PWxYyGNZdbE8jV9dLaEJFxqoH1zIAH+/zz5M7kGO+AT6BI2OGNSerQhMQw0v9C+ +JqP1mjLTGlqXY0BbhSOyvB7qbg+Xq0u9t7jm6BhIoqV3+3kG0SvZ8OTP2gESpSEqW5ervN/x6fie +Zoy3BwcOwU9NCYxiUpkfAZipSf460zdnr45JKPREnzMYWpQgEm4/udfXtWlMOinIZOIItLpmoBL2 +p+TwZyuju7y7EeuqgoCnP9mMjsCA8nOyG1a995ARTNlSA9tR9ac0JYOH5GIHSg4BSDSptSs/XU3X +iQxQMV+beW/EGTxejpa0nBsB0a0M338vwXvBBDgTlRF3CBXCHj1pu6fg2vFhl/Pv4zuk4Bz/gJaB +GE6kZNlC9l5+Bs/TsRJYATqoeNDBWGSNPPwldutZPGpM9IZV7VxVsaQDj36eNkXOG16CgJRxSw0B +X5kUscJsuAMaFyt4o8byJydePyAqJNCRvrOvLXzwnPkuCKZ7qFVjejzMZaHQP53f5ZEijVFl51cm +3tW4ENO5Nk9xIftBhdpqhi/uv26zxWwwfXn8OnyBLd/IdGLLsU8YeyO7qE+uA7gP2e2NBJBc5+91 +t2lG+ztehEzO2Oz+bBxohNwSAhW04QakuylTH/ecPp1ZR+44BbGygWVwdsnOidGNRmVTC2GEroXs +saQOXuD3c8ze8HLYn7P/ThalZWVqBtRciaw58EW/0UF9bTGGT+6BoxTaTKVgI3z2Ie99rIsMUfUP +UISwHNzcEqQMgVz2qhHYlANyV2iPGrovoudAONzq5nyxLfriYjV8bRjlds5mZ/TrUgcoBWWkhgE0 +S1s4VtQNoLY0zL6PXJwVXHukpstyyF/oc4bcxrUqwSj2SkHWYgV6FVKhiQB2Nn7IKhSKUB427XMU +ULrGVNDmAcJfV0AQ8XyMYXKSiFctHf4mv+s8TdMiK0zD3fT955nt7iBlKDqUuASUQpBDivDBSF3i +ASKCBx4Wa9VqvEZrpBhcVFSqYTdXztwxQH61+eqWoy+v415Paegjvk1jMa0r/s+SaNM/+ev940u0 +BHP9kx8PKAhfCTdlFjwYOxOPX1xh4AjszUg4dbsoD4sEMrC6EQyTANuoyGXyTdUbfaCuCBlq+zJ9 +CP/JsZ5d59m4SJZhl3pAOMyfhMP6/kIEJd7WT2yZWp3vKz0805x0LRWpkM1ynHCRoBhIwNsmSq1s +xDMwUEsZD9bT/85JsaAsaQMtT6ezGrOPTgbTx+m7gT8G2FRTlOB5MGup+KjTlvAQi0ay/pygpU00 +xJYO9eBdBocpbbiYRJR20DhG0EyhUZ1KCUHqgNoTMgtIYkqT3o0zmzom6UKp6562JjTWBKUJYpok +GQcmpH2Rhj4kC6Dq3P7cmsizuw4RxG4ylZPP6GFSAZhsljGaTURSKz07eMR5alDQPDhY5wKf/kkc +AAuwHBOVPIbgHDIrK4SDZ61b2UtQod8v9H7r0+vOGQV21x7coLNPAI7A15jwpYYTHmHL3FVOp583 +IJ4VoRtbPBEeFBk+L5t+CqiuGhDnjAhEas8Kb16NjT+5aeIDQc5T+UhFE1czv2jDnqNN4HQ8e9zm +B6H/qeW7c2w1NPCxSMufgYYSxuSasbil6aiBCIqYFUg/qkL5CtzoTEHHaLFEc+0OmOntGmiVsL6h +vmuFSvLl81MS5yvcTtQID4uyArCL8pBwX82rAKX9ssz5EvHVx+K8TOawwxa2SzMKcN/MDqDBOTL8 +3FoSbOAx43PfYMU+SiBk9Jryr/SJ5QFNBJ3QbyQJhSHuS+4hwdEBQEQqXzFAN245av/3GdfF6iOs +WDlSGCrOo3sP4GEoyvUMSIEXXtcko7cWYSqCK6fMbgUCc075p8AccghjAXkaJxZs1DvZinqM6Yj+ +B5FUCvjPOvkrvdZj8pKA/lm4SoLAC7rxNij/QMqQFsA8DgbuHoIoVCM8EviLrdd0gZBkm1AzmG9R +NiCU/a/PL+eSqov8jwc+wULWUzMOEtEWncAtyngq5rs1kajgxH2C1PONPJ9EQ0tfgNFxzkdPVfXR +8tTrQhRX0mPApH26CpeHgnGOwJr7mFjPUj/w1rCALRy+gxdtCRyXUgb/kznc4PJspvtFbVb4ChON +3zmFFYDZXi+NqPNA49lQ4/ybSRVgs7jLgC9qRTkwl1H63t8ivmXvDXViQ48PN5LfLQtMs1Se9rra +zzOuRYJntPAQ+wfgAnTc64QAnaw+iVmv7e8mYDnzxb6Wwkyvby5kolvfmjdODSdesvPjZfgYWe8p +nZi2d2uZTFhl4R/RVyCEk/idrB5AkmlWpb8UAD3s6OAkL3q85zSQGqTWjif1BKk9MF6n80RQhDe5 +EENwkXW80KN24Kv8U8JcSmbSBSY/i+PSKO8qVJzuStehHtLsSXmr2QZleUa4UV1r0Ip2aUYgl4Zd +OoehlK2SdCgkR4lrzI/JRydWLz72DLvbrcNziE7GHr7K4b0oPzMADBauZvy7wFKOWBJom1RvU6lM +1wI62fRoqLG2t9WLP+nGZLZFX7FPhok2Wrnf1wB2QFOnSXGmru2mY1EZ7j4EcEvr7PLwU70PEs4c +bjZTBq70jKbe4xMLw7kQLIYrTF1F0egQD6FYae0HM4rprZJRWb2UuAmVRUTWZvxDStzgx0htR0KE +T4+TygAQuwZHYnzBaUTMYS7xDwVfOh8JmQj6BKqVj6Rp65usZDPusnMg/ddKNzBmhRqS2JeDF+Cx +mBVqqnIMmWaTN+n0QnBUExLiK6HRFBgDYdafNTd4nydw1Pg3zquu1L/CnIGahYxQtZD88EQvqwWi +3SO2ZfxpoLniky4SfP34hUbIM3Hn3LMgBXftEvzUOpG9keQT7u9QYUA8uIKIKcUJAU2rwyEWRRo6 +ip/KvdPjjM5pWCF8LqOJ3SmfiERlEon16vDi3Ysi67ZQrkhID4wlEGfzicbGHE3i7VtAI/cD+gNN +JxNL2zsxKQiYdA29Gv8c8iBflgOBY9wou72hUZ76+KdlrtR5xN2ufmwUNzpcOxlwct94BS8w8sq8 +botHSYxr4OWR8PibqSpomJBbzr+KGYORz3LRD4NmxRwiY5ssgSPdcvUBEFkN0o8NW+21L01VPgPz +R3Kvel+O33v7+RhbcVL7Q77nlf8u3vQ7Ji6DmqpbCX7dMbQhhsdks109Z7m/WS1YwGn5ZPvu302A +zfOAs3v8OBhUdkfZ+G05RqT/qM0uoIBe53U7+arjJPB5uqdFPCeDU4biezgFsZHa6LX0ni1nuKoO +JCZZH6ijZuvNrawRDetZa2l0frkV7dc88T+rQJqNIRAAUPeM7N1wR7eyb9pLhtoGiMKfFVpKxBG1 +kE553sjIUrG+O5IWt9rH3axqez2uvUdI57Xlom4tcVBhWtXasnBz6iH2iWY0dKMyQteVkTXBt4Et ++2QIHlW79K1DYpLcqBCu/lYKWGG2oX/N6LT1V0aKk1OE14cfVY5vFN8Zoka+2TYM/KawWj1O7oIC +dHkjcDTKMfNq/5hiWV+E/sQwUrw7o7vIf7k3qyAh/HwFCKaSyJVRUMtHrI9QeUcGMnApnkJovgH3 +t8wFCAIw5tTdMTF/SPDFViJxfnjqKLvg8C0DSZtn9KgCLxQ58LKkY+kWx9tkeV2yAybDSu9tNqsp +7YX+6qRa5ZsaRnunzZs7GW6F+VVMvaU4oqaBxsXhCFDR8GQXTA+MK5r1njdvdW6QG2c9Z+GE6Qyn +C0cU16uO4Kx8YCLssfymRYHedBZRWzxJ/QRBqnxg52KLd7xamV5y02qVtWJBVq3kIxrq+hMUMuxA +IwSzDnBGKGh3DdHiFj7pYxZfKFVD9SP8cVG+M0w7nmm2rzcUGZyUPabXMyCjM6NWVGK70UgZiqKW +EKGd15MgOHn4Dp8YWN9ft13TlVHleeeJkCieEBTikGKOoD7NdA0ueoHl5sZ50Aze4duLPgcIl4al +H/69DdLuIO8i9a1C009dZm5PgDfWkhni7e1f+VzPxNgO5ox1rEUiF9+zzrBohBhjGxxiEOfhT62t +7zKvQ4XeaSd9WiVW2RTNKBd3O/xpMqiqAj7nPD3DJ5YqrYZnmtSBxsFhTIuMiUmkxSuquAtC5xJO +ZcMXyiA3wZfGZ/EqV07VNeBF/fmB+rfGk5Id3ng0BAG7Vh/ffEFTxm/cjuuweOWoVAevQt/3uFvj ++t010DWw1CgV0l2mjsustyiEipFmfKKOCnat3gBih/Swc/HZLArAz1swN/RtByPSGvdfcwIUpzTE +4Z/ER1R6dNo2XtIV72i3eBcS99gH4+NQiJ+R1+RkaF9ud3NS8ykqDNPhGAku4OGYkDUvxrHpmxpz +f3J0cVbJWFehpHa9taxu/x8QYrkLmXGANt2bV1QsthV4IyvjruK1+sdX+dha8rgCw5Ywa0Ytg2bD +/aNzn++r3eJRms6gOgf0xMb8SqQV537QPWPteOp2hTmTyE0I0Qy04JZ/UsTHxGHnjjYTTqNSkL9L +A7mJ7T10sIoQL2UFILtHoMo3tUlskZDc1zbbcb7/lgZE9lS3xpn8t/9vMj9pU4H9CSZHTqsunVn2 +Kew7QsNe/qmjhHePiodJBhKH/KBuIRkDGUt5B5LYBUelOmtR313AxbNeyqRknKY/+QpF0W+NfLkQ +FuXwZ97W90M5RcO0xql0Ywze0eFhFA6koiPizibYK00aeUoxy2HI0BKxIvLpHR3CMUFSPOsxJhxr +u8m7JMiA6dChg0Q39b23PFUI1K6XkdFZCmwdqi8+9Zy500JpfaigEIjX5pU8fzCLD69m5nvk+64k +4yl/3GTpcYuRAcCFMqbzNQ+5ttYtaDv20UkbwSWgLq1I69V1wft6UnpRFBgA592N9yHxVgrXCiK1 +nNVv6u5JdGngnI1e7k5uvUn0CeQ8Y/63uh1G9KnPH1aND7xZtTfAzlMsZa1B1eIOpiObSUh4vRg7 +2Euus036zcQtcWcqTFwLsse+rpxOzQ/a8fRST5z1IwyLSpbAOe2Iet2QERcb8jcCo1bpEvg1OAn+ +MeyPt1sZv5C+6QW15gUAIaFOIGBwBYkNl2K4x+7KDIEL4FuK13F4smsrt/GiY9H6tCf6yLfxU5F3 +ATo2knLdzOT6T7xU2JuK1esE7SGDoZLQLiJogY/XC8a27vGm3YAOrErG3c9Q5OFUob7xlCu95VWV +Ih4ZkuaGNywUL9EWdreDHFwpTbGS57/pzPgg3aqZA9ypuhB8xKp3k4HNMuXvoEjfeuwdjK3jNVra +vnUyKdxz0wezrfpOLCAzuPvvplyBY6XIb83gjJIyl4jyq07hXkObu/BO0l63oIMm8UhnC5EgN9Ct +5fgEl3jLqjlsUpbj4jobXpJrV5jZmqd5Y2/2A3oURjew8AWs1ubV5qjA84iGltJeWr1MN71aIhwI +x48D2Zcif4GWEm3OzmnmjqAWABys0pHdDdiaANjg0YehuF48DDVmuStkOwgOLkwch981ADZzAzYc +hPuu61qrt2d6koyBEkXmXl2+AFeI0Ya38JVhH+5CzRnnNJmVuB4hOkANYRwuoYetvTcSooK5kWoG +Wt8xTWCwM9BIl3TU5YRuUay3NdnHgvcNPnTqdRPXnMjWXWkTvs+4sn4zllr+bMIizlJgwpksqx8S +6RpZV+sRe91WLAItio88doTBBIzIWcToEdPefH2SnEGHW8E2eshLOQdfu1zyb9u788lN1J0x3TCS +7wv259IDMhKmRIMGm3dpqbzdu2rjfKT4yBILHuubeGKcMBjbwoMP1/oNucYFcJbgQxw23Nm406CP +s1fCyODZu2xlX9dOTPf7pA7HxHkiLl5dC7bPmXKXWLA0ryjhIltm/Lf3YJjY9YjNaXUal4jgMo+R +v5tgJMqC06Yf2No4UKYwuGX1AR2KNBdsFC++MzrWL3k5Gph2M8E7m892Dslskx9p1MDxSc7s+kS3 +6h/niMx3ueEud4ueq/3jJhn6HmZNUXGU1ytd/1xR6fDciOi9NDw7NQkexrAg1ZRfRMcXUdNc9jGL +gpUae4CBjvA47FLtjxeX5cj2STeX1b4S02Jzeud4lgG0utr/fXKVCoJ+TgV5zQTzvU7zECMzbPSZ +eVnopfWOpLho0EqdCvvoipFsaf1xuMopDWeg38ZQG6zR1eVzdEpaMIARNqd0wFSClDMJIyta9MX+ +3LOxru5H/CKNXp61soTcLOywb7EpY8Fl5zupVIxeCq7QhoGW9HzGxsyrWxmiyQvitO6DprGK5LmF +kFBbDp7Z4rBEjcKraJlAqhorp7QkDP4TThKky1BLEjgfu2CXRUyrX4zlMlfd5hbUCpy6+Kc2hlct +mKbbA70O7ZbGpMomHXCw2xVuw0Z/Hz5o3zWsjFf7G+/UyTsl7MZRv3mkav84pAMI9n822W/GQLgs +eGC3Xe+TX3kzLAGdDY9L9x/vwlQX7YmDlY+2R1v+mAAesna/HZwF2Ig/9NRNJ7K1fl94b/QmGrBe +AA2iQr+ybl1Fv5XC9ovWQNzgdx6qOgmAvc80n51+VtaQOPiJ2wz53Vivt07Urcpyu7Gdh48zTxiA +aOhAwQ9tdj3xrVZBKoCKuoqO0F0dRqhbvEXVzUlO9NUU53rOchSzLd8y3YMDJW9k97Qii6H3hoyk +zHWnftLn2KOdDoXpo6FfRhPmnLe7YNveY/Jq4eUcBiltYrsHEnHk9gDFcV+F/QPlgY4aQBfa8Ar1 +TYheyPfAGBK1mD5I5wFtubRosZN5lfEKrCE4XJd53dS4FR35fOQIy1H34GTNHF9rzKVBi+I4gsWj +3o+UK7E4y9aaVXVPgarTTbEi0WJWmTqeK+UHvrA+5x4QReovvR9XKoVPMXhwgLeR/w7GSkoaXL9o +KZek1ATG5W6OCm+mJMVtNhJAOp1oZCYeHD41IPAv9O8QK2/SlLffrOd2Nw7I4TOwxNiPwj547vXZ +/g0WYDvaMkckPwYSEnIsSvE95OcYmBfJb1AdnyZ/JJ/h/T2L31CQ5jSuWdXUJoi37A7kGdeJD3DU +d3u7zysbemlALywVPnYEA8F4hpMS0MNatUTlMA7qz+kZRPdQ0EVGAB7t0DxKOBueC/I6I4T99aeJ +ew2Ta8meIz3KPgwnwR6Nbu6s4SlxwfAAOGt7sEcHuAfjzWNxohkk7vuZNbhc551Tt4JXNdWH4X74 +LbsRHfSKHhin3YlgilahK9nkCT/kI6HPFhfse4HKef+t/fYG+I4tZigzVqOMOsC+h+gwPveszQj+ +dEMZV+7kZe9WcQLe1jH+EeKwzkxFBRp5V9UwBu1NPlITbVYcYjcCnvS83vzYvXPEXmzGFUB329gn +Jo7GfrcL2JuZWomXqIM+pXyl67sqVRVa6F4A8fgUjvtTwTaXlCNbDtAMPAiizpkascE0L2owc0Lb +l0BDbnuJtPYtwtQ8FWzktUd1hhN6hcbtgkMLXSpjiqOofe4f6tEqP1Ja+xR+YQgyFTsp25HIKp3e +IRxfEdm86u/maYM5+QCF0MvEz5kcoeHuaHh+UuvClOz7Hu3OCB9vAPoHsy4wvhztUnU0lShbdGP2 +TVr3YBF3kIN9FpZ4fX8zuI2OznhvQqMEmkDjaoJh0SyC9bqq3ZG2JSrwt0TlXsTAMVZNs35MTiIe +yrab8n5p/tA9QjphZKz6LcMACHl2Xacvfa8rHZzN13FyFIqdWE+VWr5cCdpvC+aBvp31UKHJNaRv +Fjzy/AYzbvETfkt7SAloau6A8DHo5LRX1jk3tvq3O9nmD66X4kyrs03eaYYQXMzjGsoFbl9Xj59S +D46ysmo1eiyuEhRJ9hPFAW0l/3JtXRhEWIhx85e7ypFsO7twndnBCS7rAHHXynitUtP64gaILA0H +yK57FCHcD7OfdMYVtneQmPrVDPECpeXOpxx7rW2C1PFdIeEt3ONjcZKi6UP4bksxzIIFKwjZdaRV +SwpbBzfU8o//8FIVoCNFyGaVg+ULOkVTA+8g8dft2TVmP9kbn7u0GtvqisyaCBsM/sL1MtH8h0+p +hueZlB6MJmbOgLhEJuuQDSdVTSwM7/HdvXw8XAtSS3aigBmdurhBgsNnu5UMBZKB/bgH6ugUPtxH +SDhrG1HEaZQIuKGNFC3H0e6z4K47SJClxYvWpuWa/WCUECFBCogap7cdhBel1/U66VKzduI9qSUD +KscUcQehHBHY5qyquvHMFH0HodkPo8qfrr3TYyD1awIX6+tlW3ezpBGvDRfuT0bYjExZWicArxqc +kBNICvz8AAMlFyaz/r+1eYiNokkhbsDNkdmWWVqxnbTgFbrM8q05rmEoervFV96G9xTDJotpEm1T +8+TdUxLVZ7wdfZbYE7e6mfzk19Rcr8kcWPjg4lTKwi395w2EWLyp6Kfmo3weTEGbslVO5J1iaRY3 +ADQNjd6b+yrnm63g6P/m1ldRVvMJHb2yKQh9DDoYVM+XjSbyQJC0Pk4zm9E0VPvl9hhX/ASJPbB2 +8yu20EO+IMXayH82g4NyPesxjDWtPJIE+41F4vAfiD7KyWKp7YgneuSZfRVEEm/G4aOj4eSupdh8 +gt6L61tNsnhLUC6vqInI790RTPOS3PsxSO3/v1HzLQd6hX7za0X3B5UGh8lqKqZWmUCOpPD45qW4 +5qqueVemydPQkT4I+ya4Yxi4nQ0usoeOq5wBbsxtCzjePzGkBaK+oFREWL+8UNMQE5Xvlku47T9q +Cf0g0zd54OVznTNwjiU0rlPCEHK2jx9FIipeB+a16csCnjaiASwsL+RXEGLNW8kEB1s0JsnPmqLl +0RmBk0k+Hqhg8HbaUgO3nNAFQX4ih/0wWMQvokKUabxjd0woMc7GYGolXVevgfD3eycqv1rkdBRw +jTmR3YlM/JEnHqfCqrolvwtfq7era2xvHMX2tzw3st9b+c6nbw5+o9RE3aRjqVPC6b9Qfpt0hyMo +gRHyu3pWtZ9m5xQHzBN3ef142RmXMsfKNncwpHH2rfh7PMHjsWAg4cxQoXpbkZjkZVoHT5KVY+aY +r7evNl7RWBfoFWYrw/s4VXjwcTlHfb9ZCQ10EGHlqiV0qpAPsOIaQieqcm8ewG0UFyYLZxD4kcPA +LKThBXlj1n4Cc13F73QLQg2ci0HGF1fdcpLx31w1gT8Y3l0uhFYGPjgaq8DVAJ1b2jCo0BWCbA9S +FvTSgw9R9duUCWO7HVnprE+yrzuvFRjSJqFHiJFuFxKWdWy6XN7Qy8dLZDOBnx2r12t4bP503Grd +AU9pYEgndn4ss3VTT70hNv7aQK5L+/r8o1NN0IZrSXQXHItGVf4dWn78bHkK6hx9KtQBePATxge/ +cklQtT5VLW5USeUdOF7RFnk7EkiRejHDJuJ3UqTaBteRz02kq3NS3Fly4ca+7HYLSxHuPBwXrGrI +qTjztNAPRwU231+5lE7N6Iy4j3vxniWI0084YVUtRnH1sEDADXgMapgf1eyLX3d0kV0InTuQhS02 +St8FatLXTM8NnGLvuvO4LQmBcZago9RyqgD844j40iY8r7t8lgc7lEJZpztpRcAI0/VO9L0CFmM/ +IMiC7Ap18m+IZ9ai7zXGZg1pHf91xIzK0Lt1G3JMVhgcVsQZuhIwuSJoA5sP3Pef1BvJNt0Pvkam +wDdTuMevMg7gFQ+NSMSeblCoBC/j+ZH1pT9vzWPlttqhgDc4w03FnnGkyCJsm6nZ4OmDxgla8Omc +1L1mDvuwmHCNwhk7V0dPZX1SiUBDIpatUVc1SUzEgyUzfKYoR/wu3HVwIOqQXU0qeJlxZYIInXX2 +f2GVnFDy25BOLqTB0YHJdpFsL6gDizsk82I8UJGGGDMGT5m47z4DUJEAAvazBzP3ECz5NU8Q3mhE +e1BBxdnfsZLiX9HzMtGoQmykupU24rJPTCUf8Yz+bOi2Zp9kjqkjDHlGCFTgfA9AU1O5MB9hTUW8 +kF1TwBgw/MME8uz0IbWlVCbn9u+M6ZTdYoyvdZTtHEoPyvWBhjUidXHbMuP4hUf30Lu2VTpai8Hf +vC6kH/NqsNLixLk5v9uLj/ctXfvrdksNZadmf9JtmQV6CzSkMaXYqg79lDZYRdU0IHut6TxwiaE6 +mFux+9zzP4ro3HLpz+uX4EetEg9/ULB6389jaZM4Piww0pleeqXA5r890dTb1CyuMvPwcIEVWwK/ +i+VQY9/9zCXiG0v6BGLfNahcY0AAxChoNwis7w68vzlIQzaNvG7Kla2MzYPcuer/40xRfxUkLkP0 +oV0RFeVLLbXbIWMwM7btIHWmbl5qLnNIc7yKt0vE+ONy/JXYcyIPWqO3K3lLcd9Dmruaa+ofrNs2 +9cllY1nItSjaIlrXeX38LrzkgKul8Aj5iCb/cfgF9aom4y41UMHLoz/A6HTp3P7MM7trxWtM3X8M ++S+t3NcTUcd7xAc6c2sWvMEHmn8ZTp+fMni3kXEDgp6zLUZx/kVmGtAagrLZd2aoNuAaA88MtLD2 +jNgXmmopK0glIZ6cIB1RKFJfjE6AZSPoBODYp7uwtd1ztdc3NIdrSJyQX4HIYQzGzx/Guplnw680 +n/SqaoajiA2hw7mT6YyuTM+ZVcVXkcD9lTL611ODY+a2uRpxa+yke9RNDHz0bGLEvUS4rmh09cgQ +hfQenoi652bOtzMg5xjXqpEkK3rLrhXlGaaeV2ZT6HoDAv7NSxaq1k9CJ4YHaccp8za05b9qWMZw +gzIlj6kSVmtptjD06RDo3o9ubZMqJjt83QF/ItxtH2I6lVzGzD2NHENI24OP6KiTHg9lrmgKLqaN +fWLDc76A6L0jOBEU+RfCUjrQneRHTvxyWMGmGyrc5fOt6ZigA4/gCfObMceHUnnFbpZD0jY5c6yF ++Dr6Gk1aIk2yRogAYRX09HFvpvh2DSzIzrtg+GAZGNWZpaqBENBFWc/c96+hFsmx781M5Cwheg+a +fRdaNIQhTkWmgBNeRDKBmWHXP7hiYItUtyURZZeqzSY6WKecMZ2w9C7udDqXQOUGXNc/eIV+97th +0HhcGrMdvKnLjELZNLloXMj+7fGxyBxMkRONiQOshs0XEUaL+EuFadSUrqgT1I6ob11t+n1MkLp9 +YUDaGw5YQ4yiz3HnJ0EL+JvBbeMaijx9DL+pD+e626AZFuJuHTcdMW9p6A/XLw2UjOQvvpQe/Gie +6DXYEaSI8RYhcIpNgKWT9Djz05Q4+mXMLEt5d1ZuOsTcrulg5JbLwbA/gfHv7150oy7O7oA1ABKr +v28MFdHqkBvFThjvwVmxFcAWjAYXk/7mM3sqJCa/kQhxMAbd6a8RRMvp1L0rtmTN3JBLhKJxYRUd +29uuY+pLbImDlm7s6fwDmPfXjqR5TTa2Wbs/WmWCL/JfOGcBbdiUAs1tXwi2yN0Imbytv7O2rrIh +2e73KduSoohccsTR+wiqNzepzrKDWgFEdigHRMj51yV1XeBK4eBma1dkL30FxtICiv6pxFIjHvzL +8gTbBv4JVxJ/uy2oRuaokWL9ZtA91uJHa0hTElmU2zBSI0/4OE8GkA1DjGMcRoyCpzMYWg+pwXsZ +/ZqsDv+pfTArmUxsUoMbjqLzem+nRvJp6qWqBrPfIJvgBj3Ru+o+Wy35jVFFp3PqoUUcBS6jLVBb +nxKEI7Czyqw5MYrwhN3OBfRiwJGIGGkUE+nzFh2aRZyCvUAimuZa4uZuCpcR30E7/NW4fj+VjxVC +1BtGUZeoWm2wSRIJ1cD0NSV6sxjpbq7NC5CcNHQFJ+wGR+lMKeLZsq3BQtBRZisx9x5JzB6rrH0F +7rXLqdhT+HQTQD8Mq+/Wlc4d/aaF9SQSO8hNhIwBLjbziPio7j1NuNPCvraDTXlww2WHqMLSIozU +VprtP2y1q8yv6OwWJpUR/lDVIJvodU4uf4in3XspxxNzjX59biq2135hhT+k40+pMW2NNNmBpv75 +iC0JoEV8pTMXXYWD7H8/3sDOb7Kk4Ys23zS+qk+nhFCQF38YXKbnEGb7SiJ4iy8sd6KP2oQ4BxbC +IGMd6qEohQM/Tdb0sH4ZJ0N/5ylHvI09anQYg+gre13kDLwaeddXTgogdsl4m33KDypfG4Gi3T+C +t7Yx8OkPYdGlwT48nYo2+9fr93nKk78zJx72PmkNIYDQmeolUkoO7trAIOGXy30KTMJxOFGAf3/b +oREvD7udrapnJi2Y3Qwh0h5eSxmigZTDX3R8qIytv9aey3xbeZTtCUIPyLp/Rd8hLlFeCDoxS5/0 +q4a5Z+nT+F/I4D/8aI/LB1MkOkgigblCKO/R291j6QtCQqRn9Rbf5/qjiYVWsEatsx2dlk8fB00s +x0OwRWyXyclZz1vKjlxepYjk0ebQ0w2yYEeQQzn/NK0ZXz9SNbN5oBxRvI+i37V4putUYFLp/Poc +kONhrXHA3smG/Z+QkRHhNjcuZI/ISIPj19Z7+urIMUrIUrJ96aE8Y9hppx+Vm1Ccw+4z+fZ464dZ ++ctbyIjNYFhBUAOc9Tm8jglEWNX/8FXALutuqiwsZBYoLb8eXbevbJ9DW4xYssmx/VQn5qtsyfb6 +OEVESLc69deqMgamDgnEX3ei6cm9e5TM/SfExYNcAUBhSywwPIwEPrQXMA5GC4C6pmAQcY6rYR38 +AXh7DqZfv86Askpxe2OLJEPKrLb11N94BXv3WF+jc9c9/g9sFaff8WIkAXWjkWu7RgrsLkCuZglY +hM6cf79lj1xhuQ2YKu2hC68ADwAiBVoFwi4cdsiHdZ+3XKq/R5Yqk4+lls67rBpy5Dq5w8R3AHzN +Lz+FPHB1w4b0EuzbI4+q8Wd3rMg4XnFaRFYatyiUPn7a6bD2Nb9YuAgSHyj+VvHNQf5LGwo7q/xb +iDR5NCVy32NiQDtFDU6U9WcAgr7GpoBB4g5JhqspHfRmlBXPwoUpwwNmTeXVsNNbu8iPvYtR8p5f +9AtXu97mdpcQmb5cKn2go+qwJaZQDsz+ZCiGh6UGilsOZ+UISKls9vKXt4sOXuBusuM6PIOZF2uG +79gt7uba5r0gJnjXVryi9pJSr/aEFRjb86tfXeRnLkH+egweGG1TRoOGEKi9t+aqQlhMbFY/ojiN +cbyWy17KZisVyxvdOWp9UDtFUqyiYVHXKL0vsvVcYz2rFuDAvAnl4F+AmMtJpOgc9XGHOs3JL22t +eCAojy/sIHXGSLbKXMtNib9Q08pKDTMJiA3HKtNxwnhZI49pVjg2X1UN31vvMcsijPOufY9ZTuxg +zLj5Z2w2AU0gddmRA/ua/APS8jZPivHfM1HcpZOxkMRSAjkvTcxw4WvlBJtQAmLUGC52LeLPLTmr +8LdW9lNH+el3iGjqZKvRhNlrmQjdoLNNWQwI+uwfgesJzty4PC53Ltfkjgdy3p1qIkGxGo/baG0C +VBlio0NkvbFtnkGq5ULDb/CZVPmz/KX/iXLeYbx+2adJUV9TLFyNRXwhZ4/Obz8LYKpFlLKXNrds +PSZvdaSoQd0nYCvat+Tb3fm6oRam9xjuUOI6RY4KaXk3J4G8prZ3ToLDicXjVmhuLRklOkqj6cZC +aQvRq9mnZyABxPdkIyhOHKci2xpd0q/AGlK6fp7aJYRmSI/dxL/YnURFJ7cfZNEA2Zm2jeuJCO1V +RajoYhb7lyXV6renBE5DvTqBFtjxl4gAuUeg/DT7oSGjEkRnbu3d1i2j3A4LQoi6r4/FegjWH0Ym +wX4ehQCuoS/Ko77ll6iG3ZcZKLLrHy7ZNTRFhIpkZaScZFvZbkR09iGDv8YSxzRWI6X/r1Qa5n3e +hOLXBfPZ8DEi4BOBYYzP0ofPafFEQTiGlYOWnnRtGAhxcgFpzz1da4bA6/KJpyHnLL4naMMvPYsi +0lKGo2/YXiLtITdbh8DUALjJOyFt7KQHk4HUAl5NRnbM+vP5UACTeEmcJ+hCoAy/47tAqZtJO9mv +7RZKixd4dJUgtAHz0NxjxLveHRx9JzXILA4VTBAbLdmoVWWeOBYbySRoLXMcPb8neMPRV4Ctz6Wq +mnHDKJ2zGkGmu5uUWg5mdQtkQUv6uuMSDd9BAv5/NTFsZoVCLeLtTUuiD1yVXCyPGeCBeXi8CqrU +o/drnldNxQfRnK/ehhx9R02pn4j6XpAuPqtl+kf1syOfR8d0tx0UMkGD9lIhcf+upteiFJhTdjis +o0tJUndvvRrSYbsFCOAZYb5KleaRC9ju+2ZYpr3Ezo5TgtVfh/lHOgVEgcYS3GwrcWSAwijO2u0M +44HRCZb0VNUFATOgd5YsuCGfL0//b6Dedfh5XThEFZtMbuJ2IxKzkKDXHA0nluLehvLFZrPyx+8z +FtVZFHPArSIlkBh5B5J8YqqQ6qYzYpZZ9Lee8z+WNp4QLwpCE15nxV6GASDo5pEU/JDXtDr0dDGE +bfaWFxs7W0p0fg5ZWTsH2e8nWx3Joo45mQmYGTt9iPqjVtwhjYh58cNbeEhZ7p80wzluqL78I+Kr +pAPcnL7tu9SkYT2xuBbNVE8fp1AZL6aZAj8/EgMeP5hBmPI/dQ/NuT5oUV8Z0te/WQ4/RZRXI9+8 +/nAiDKGBs3Xvr8HzjA6qnNKLoBJbhYu3T+VotPKcZk73SCEkqsYi+k/dCoYWczp4q97P6a4xw5iB +T0oGZ84X+Q+vGZLW6x0Zt9UYO4v5P66Rdz5gTV7fMcXK2zviFPBl5aZOZTZYHeMA2jFGWFSLtKR1 +0YZxfkoheP1n0zmr+im1m11LC4QJKAPpMBD6T0DecoKMBBItVD4kaEdLr6vUXWujRNPzgrxVbS9u +n+lWY9rJr08TM/mWXoHVFKfme71TAWIpykY3TI3tekfIR+YMhj9540DY9S6lVzPhpd/hIe0R1xqq +fkTbJt/ocvpJScUNEjy6JTGa5xTOZvJ2h98hDfD/TN6ZoHjje6tB8qxoc884btW1P2sgY5/OQlm8 +XqeZtkg+VFV4ZWPMzt7xN/iiEyb49xuLi0KjWwN1FggC9/r2mT8JVHDSBcYlL0WNkCCw2lCqRk54 +MCuJUNVPPuRW222gtIhRfHda5tuag1rDAGSiIjBfA5wl4o15ueDnsyp9r6Dl6ZwTT7Fdwlmy/NXo +4yn68D2XeAMYrT9F1AFDmRZLrL4jLWy7MqkKPs53Vml1J7HVl4XaQbAyGBQM+qfu+n9XUSjndF8v +o9RdkjhggOg1tXyF+HXlU7kK+x1qnU8DCCP8KpzpNyB9KcXt+MJEDxHZpVBalUz6mDk7JE7B9HAB +gs8/ccfh6v1gQhB3hKGYSuEPDz600nJkFE/zaAc3k1mI2j2dZX3011JEj3kpd03NkB0sZCEqg1sN +0T+62sTwV9+Vxhpvox+IwOdNujOl11mPQZ1IpeoN9psRm3FYxzjT7+WB8YTLfCscdvUevcpz1WGs +uKJx852yANF43sB1ruvvpFCOknRn01x8HDj8ANmpEfEXCq0LXqFov/up+zNu+GoRPTQFNtTpfA+a +gbuH0nxblJGa1rNZsmIIFTQUEuJAPMvFNmgOaP9xMCHPWHFODBgUNGOo34yeoVzkiUGvWm2wtQbf +q6SdobSbGIFTW5ZMtbkMRkJfG0h7bQ4KsvLKljbOJ0nWXbEp7JaIcGhWYxjLdOvo138ZUJbeZB0N +Trr+HRWD8/k85e9VMHVfF+/1j8y32XLWYSnJypCi15jXK2re/LveLaR0KEGCAcqHG/lK6jFn0B7p +oe4zcd13y0fxbqCMwn378+ZjlN70FaAeM/hr6uGplQpTpFK6Ku4cC4eunVjFjbR2dJVZXIqgkfKJ +XTm1OXXg21c7WhzT3sn4mSbiX8RHQooRcIKZgvt7OhZTQ4QSH/8HsF1jsEC1wfkWoNretCqLPHwX +InBwDq2ugrzyaGtMXUW2bWP+7swnQdlMosKSLt+S1ca48swNdkyINJvjTTo5kOs+np3FEvFGi9Sy +zpL09DKhHuvkKj2OS3tI9AavuP21nsSGX5p0l1SD8UKMftOuuENspMEHGDKsGdL9dWA4joBV12iH +THToLPa/XTrF0dzZGFENrDz1/oHSWLBpIS3ozvh+L/IfjwccSh8eOB+eKGbyy4ZCpcAfAIi3Heho +DSRetvcV3+VP71g2azn0HAeY59iscJTNm8cAVVnfY3ytv8buE/fl6qovQCylfwUektQYdWVYQLFG +Qd5XyM7Mbl49lMyck5q4UyEEcK4bFhK1wmUZbTcM4h/xa/bNLyNeNVkbZHMhwxfodKE01lZJIDqj +Yt+BQTbyl8oSwovaymrDvGgL2wChrllf2MeZ1nIZnqyiouyaA+coLaEBi19DbMR4mrohsfsfK/Z9 +zQF8pU5vZDavA1JZqqFV3O95a1wIP0PyVBUvB74IZZU0e4uAJBqhKtl0wPDttzzGH35r9z7NfZVz +V8YuwgqecoMjtYeMKLZm/SXnIS7fiQ8q8V9MSDKCZEI+w04ZqP8oD/AQ6aeangEIoQYmhgNvWtvw +dFupbKUdMJQIsTuRYPvr2dWgSuBAffHCqirwofBX/freZKLNrNDxWOa20HpLZ+eBvQZb2dgOmKji +B86vpwygolJDWftmP0kFGQaUYaTnNW6ETn5D+2CauAzO72lr6OFxLdtiXx8bDPVXpG5vZm4aok4H +I0On7KfTQBYIUkhNzHwkk3FkCApA9CP7yZ/iCnuXfQY7XZJlhBhs3SbdUy1aa/to/Tb1mDqsrgd7 +4AZJ+KTFiYW1WN5uzzWT91xzaAIZ+evjQUXPZjUiXrsMeLYudZjL+jDsmNzfzYTAxouxLN4bEmO0 +vpCGBT2vOuOMZmu7kJwjni8jsPXIrKhEX+/Kry4RgiFSKCmfv5b8xoblTibCOW75aV/bWByPf8HW +ZvcOJWZ9ADOsUl4GyljBK8mGv+djhWBIRgfMCGOLDABXDjRufYhmq9l0u1bTCssvSQ8xut8O2890 +xvdKDRCb3re/QebUunbMEQuZpsHiD9GhSb85V398IobhNd2KjJjpTR3oXRIiufy+c5TjNUhHJmip +jS17NbjkKlIaM5JAfJMDeOExDLuR3yqJCb3x/mqK1zq65u3xiWgiJ0z2s4UKxPnjMRUdokf2/e/W +8V4gXT+qJwtf8LsduPgWiGggu4IoQl758UiTWhlG/RvZg2xARbfIZbQzVVZGzmhw1PoFjenCHywS +jJ5ZPkCU8/8FrUlBEmkTqpivxL6Y5mM3KS3m13HZNn8YJRW+CGzgtKm7nfjivArjC7JiE0jUitOP +u8PczRGMlcv9/DvA0i7rMDN+X7AHQYq+uf3UDaJIj7L+m4LUBQxIj7NcTDBD9rX11CtY2n2mfaf2 +yzbZ+hD8X9sV9U5onhgi8l7hznzwL1WIsKbQ8gEBg1+sFMEcip8ixD177qX4xUDgIaSgM4VzhyC1 +YDMjhfeIKabaqcEJZnBa6Bn0jG0NAs/iHt1xFhXoinQqyhEyUdqyGICQCIoFKXuKlpY93AIkTaha +6IKvztdsPSQnezb4xY7J7nSg2pPwKzU7tEHU6hKG4xdJ+K9U6JlqoHh+m5O3sMYJGih1I69U6u9x +PGoaLWFREvp05lhonDN4ufZWF45x79qhE0O8OvCke+ouNN6BiwGcTwJ+ympibhhXmcdDplsXH2Bn +k4U1N9l2J26iY6JewUw3ymA6aSjalFyxfz/EgPRvwjyMzszWCFwrxS01s1dLHWprj0D36LolFEDF +OFHDez7K9fD0P0soT/g3PlHivWWowE6iiNfVaTbKUW/mgvJs3i4P4VpUvLLZ+O5GN8+JYYcUX88k +6lyt5Fl5xopIz3xw86Bu4mQMG+OrnKO9kDk+GMWqY1CTLsDQZGH3Cty6qkeBS3W2xxYjSAEf5Yqt +Z4X7CiooR9G/T1SBu2jBoYlnkLSJ59KD7DKLclwEPqZr8GjZyWjvzCxrs72c/8MkppvqgJ5M2Slw +auQeuHapNkd6hUxbwnuryLZFQ4e6ElfV7e+izSKpIMMn0m5aM18Oa3RUZdjLWMuvzZT2B8JmmXTV +c2FDNn/pkTDxyk/z/vqGGp8yCiSng4o8oVOBmJL4JSjos0wiG5vQaZnexsKMYBe5tIsbFRNFReYt +hhUh3sFbD0C/fEhswu0n9VB4/R/dZMAJ1Vy62ej2Za7IGnxVUnmO4A7oobcFD+jQYyde080GImqL +vYrzoXgnQeX4OjATn3kyRFovJNELXW/6ZLjT9C5Xmt2F8omrYR76uVvQISd+ZKLuF+LgLRQVJcsB +/2EIGv2dv26gctJ1L4hVlB85JBZlc1CK4JWoUHiKqvupeJ6LU1K9gzw1MTOJgljghL7WkE0+8FDP +1CYJSRDK3iAED7M9mSLOiP/tMTJkERQMylyQnA2CHG4SU3D8eJO+JxF9zNJeZPAozJCKJaZhAVIi +MW+U6WzQMZCyYYD0guqPvuEHJXK2N2yCxVbKjKPmE3ySxCtjc0cLqGpEem5usiHJXJuW1WqGUVS9 +M/uBEFIFm5HBhLp7TYqxwKOrF8MKWXaFpKN4uYMMpKunOF9PMuB/L+3YJ4nVttTa3E3d+EA4Ndk6 +PHAguP0zx20twwy1CnqKTJrgwCzXf3aHBBNG+5p2k6jh1mHMqYKPcQ3rO/GLiqib3/3apkeRJHkN +NnLLVFYlUGdJ6Eg3liIMbIKlv/dqE+meuAWJ1eC0kXYUXwb9qOrfoRZDUrVJ2yhCi8Y5jOFtdh4f +5aIzXg9XWNClwle+3KjJOBDxfh85eE6Edwu5Gi1j8GAv+dDErG56a2IwnjNg8ICWmP1G1tOSgWIy +ke7Xd9Z7ap3VoU6qOvI2KiznePyP9/hPCIeNlqGzlMF9sfQRbrb7J8RvjNhP8p9G8EP5IzJlPQhZ +QPAVr+b/td/QMO8elsfCEjdY1RbwbRRFQ8bahs1xllyqG+CFPWP1ddpqin/Rz2qKlPmO2YCvoaPO +Jp9AHWOpMmeCoSgcHhlrJ0n0+qrdmBmsBYFZNYUf5BKGuM4thixlMmcxy7m5KBVb1+xKbiUfWO7E +XPpCn1spYoMb7Yn4Kqfg0XnU5uPNPmVdDP8hWDNtSCyG6ilhrEbUJqKzRttr1pJfkKybTPT3Bwvj +BlNDq2pA4SS5KPbYapIjTq4qx+goNbTze5LLTJr0UJkPS7g3fARJiRCP+7khcwNQiF7+HckMWPOe +nUlWnRhUXGhqpXRZpTsz/qRqFSJgUBSSWzOQ5gRlIkS1I7JrdrLJnlxiByKCgBNQ5SngVp5970gk +k+1kCAozVxx4s0m++x92hMt4N4cSxwhBlH3GR9QyqTaj3za0jlfkSO3Q/5ZCav1Kla0iJgOXBc/x +LlGS/hwuBw8J6kDDNn4B+CDTReCN3DfLWDA321paVIFGEEhtRnmUUFGFHeAWg1QmvU3o1j/zNBgE +ibV3KCIx5Da5vpylZSf8VH1SGd2U0H/q6lrJUQl6kAvl2VA2TNj18M9OsNUPB7/gtPllc9ZrvevW +1zVdXPqm4j9J61d7cngXU7xgElfOh1bVkPNnoqri508ohis8CrYU7N30OYC0Yb5P2gF6M9KusTf+ +QYrrChYygLB1Ty579NH+0brFqdNhY5sbDrUdwmn1+8rPNUca8r4DJ1uADynLFgIYtPJUSmNG4gQJ +2mqfFE37L8MPzsxH+mf9FPg8KDDjDBm9F2ZyfiO5xY7Kcl4hFTwZnr4q0m+4/iPaHm5raVWeNnNm +6HkUMg2gQKhtd7QDGhS2wgnZlDNSxZm+dLUktkQqgzC3ZUfVu34nt4U8kzfOM3h4qtHEitElaZ5n +SuNtxHx6Gh5ratKG6MnXpe4GxOGIDbN6IG5ApnTZiv4oICd83qVHccfus4bYukwmb3LW3a7dGzOG +CtPCZ3wImfMZSvpDKOW+O0B3Q3pRx54fOG84gX+h6lfkynwrKk3JgxGyUFsJaFfLIcyWFpH1aHsm +YPlRGgsTyklV+J0urVVoNI0uOBHuK1Ir4UJ+kbqSkuuFbu3zv5RWFqgGVB/2WsgIjvN6sesydiAP +LW7lWngD2l9SomwIKgWWfm7yi/mn3dSFYjatVbeMdkAaNVAxFWAblt0RCmrFig02+cDbkFoC6TPE +oqpKNg6ObxAYPxSRUGhFm8P1hgGdmj31OO6KGU2k/v+KLEpw05GQCzkCxhw4kJG2/rFcTQ/kn6Oz +veJvl5N3/j4VXEZpif0vhoK+ucJCREADCliKvkl35G+XxxY6HsOovd6rpU495IydkZWJ7JqyBtxj +z60R/W/4VA6zqEFfS2rb0u4RJwNYkOFLWwMrl5UjUpKJGaLUeJcZZHVCJlNoj6XoOrbt6FqcR05i +WoYq5FOipyOLq2h9S2JRIr2v1eAxkJbOUem0sSLyV/nc+1j+wewaibgZInKvr6sU94F3KF3d+2W4 +sC2qC6sVnLv2KUmXnwn8mZtBtKzBz5go603REa/2XtWDEiHFWMwaWe1WbfAmLi0qcM0+eYhKPLnT +Nbb0BrNefO1J1lgISph+qrjX6ijzS8AiESL9PMsvkf0HaOPqA1z1cm/37yzGKrB/a4PeGCPiDvsy +nCEYJFffqDr2TnwC6S0lozWYdr2C036w+VWFu/kg6Wwe9C1nDP/Vj7bInXRyfA24sT66JEAKqmJm ++qIhDHcGCQVMTGdhTXzHN++tDnNkTlTUw+grzez1jmhojiIJuVoe43ndLABN7SIZTmeo0crqosxF +v5rUEbY2ywdFswMd5A9OOVxxaqbd4Z6GHFpKfWY/9MWqJMOQS2CVa+fcn4gxaXEO2eSl7yEV+HuP +uGxsrUJYQNeOyC4oEihJfy3tHA3zTmFjabdR10aai1BM42jf/G/mo75L8Uujs29A13QNMR8vLNVR +WslL5YFxaJiGkdsR4cQRnp6jaVDlmVcI6kAA532vikdIaSHctUrxb8gOrnej6GPelN66OXei7wVZ +tC+JdgtEqSmcMjWFmDS4IDi9kPqsFWmhJuJVlKVfKUBTVeKQiHvts1iN1GTYIKqB6z32uvYJIbpN +GmgPLRDQRYc2t3zolqVGNpxg0yEbq/we2t2Xn8gCo7RP6Pc7cXrvQVV6EbQLJZw6cRmpZfIFQIvn +1H2Ci/5pvGibpZDg+38gyc5opdtkSJ2qAPWPCHsiXXzVQ/2/ok5SNW11ySNzO0QuCaild+CouQJM +jemz7o1L7QalWuOMIBS+/Q8x0EJr1KBANkjOFTDQpBQBZhqP58mcvwhUmr4QIUaBm2pSBMpS9rVD +jEvwt04ZSpnL997xERe/LcnIAmE2vIoeIpHZg8wgQ/P7VddXiLbcXuJTv9zjKQxbS+feVBi+O2gf +Dv8dDS7cd6ATeDrUj5b+gF/MRrM4cxN43UuWojLKH0T5VkyCwedXEftUlhynmqTlQq8aynYY/TAj +hvrVTSxBJwUHqfn/vOubXT5/pEJc0hCjPWR5d+hjGeJYyE/1xNwB1yzbrWWUH5wXmPjqmEljkCeQ +67QzNvSKpidbzM3W6+iX5eD/1p9qS8vyFlweTQ6JB+cvIUmXbCp/GDxUa80gVpDwk8z0ikVhqZP3 +I5L0uukigBuFXPd1SFwMwg7eCwDLflK5+9uhFMTbxEDHZF2izxV7Ji0IxNCZcXMMeCROU2AUvSbn +mNP5Sr4QXXxfW5dRP8JB18eWoXcY8GMQ9HzPpnlIJZNNDxmyyUGrfXkH98G8u8GNF8RJuuA2cVYp ++HB69ig6xAJvljUI6WLoPekOEyaLCu5qJZusQIn+nGIJfmZUt8yZhoNl5Cq20iY1paxhBlHhG2T1 +RkEXWsqsYpVyaROGip5e3u6qa/CtZOXmN1/SoLAOQHmRRtFVJpnVrEluwR7McIeeKzBZ94hONDB7 +CoLja6veDpsv+/bfCP4YfSoNHLwcb1sGHrzMh2CcHPnDWF9H/gWqKqDr1ep8MroRfFH1HBusJs6o +lEaLS9DmmXVWqdyxQ0zIE5eYcghxT4h+YpjbJWbwktpYcLjDJw8AuhFR13CBdJB1QlywHtv4+Nz+ +TW0M9eSqLr0srpNh5VYHqVI/c54LrV/nRiQUAYzeV6RRuN2/yDogMB54KcTubKREAOtAo8qvI5jl +0NZoNkRTTfkoso2ZIfz70M4J97SivSZBB9gOa20Cj0apOzEpRQzMkV2L3braeYAS9AUxjMXMMS+1 +o1pJJ4Ax/20dWZZIVF3Tb2cIWoKyJC7xEK4dfX/T3kntWxdn0MXeaCdpy3YNmluhKB4nAWo4ZnDt +0Ue9lEetcbFM5uep08mFuEa96hJvzJskXCtQTZWAGEBk1Ltbj0MqQibYi1DRRyMwAHyVySRjRfW2 +tf+EIALpUJWpO8KahjUlm28dW4Oyxdesoow2FxWpbSw16nHkZ/cErIcFn6sz6tgc/kdzUR0HIAT0 +tzNheIGO88qGcUuDTSgoAxlHY8W6WyKqYYimpIombXzuZQzOq7LQlkfvMf+GCW1uMnMAMMQisqx9 +CGUZl7oNgIsNjGe+KuvFxGfe13dub0QQdbkt8O9lstuh0Hlxd8jRtZZ88b7WIUxyEjz02s+88jTh +1np7tdzjYvSabu+wahYFEedgIrcVJIe5X5fZ3E2ZWJCm/WvHNSIPAxiezO6gRzb4yGxfy03nFKRc +hVzzbnidTSvu+gbTMPiHdeS2LwnB00mrmoEwD1Wt3YqXpOfoo7sSqDITxvNuyX2moc/GPLtiDWzW +a0z03LngX36hOubesnrBKHyYJAfClSQ9dqIdLLYAreT0Xnilg/inMzjmCWZMkAgwEHPsWlnZUjrm +EQOzkuRDoeJH9sTasy6Tt8XrIYVrkQZs/9qy65y0PM8n9TvGvTZRurgEM1JfxCpwTA1Y8h3Cqm3K +8KbwJM1pwLXMc3KK8mZfEl/v485HjQfFy4EY8kvnTD4P4cCAtWMxY0dT/4PCFrzRJfLOtNGFwSVq +vshzBqh/iLNv8fikuwEFWz2cACQFcPhKno9DoTF5sc0BUz0XhT4vYSSJb/fl7hqrtR1jh3JOqC67 +HYgSzZamvjaUXsoLpbCO42eQLbsQ++ounk3mgERzZL0x4PDNm3Fsh4/gfLn6VA+feNrCpFrVZQmp +iCoGTmqnGEt0w48by0CdAzt9ILYSR0RxcELe/VxFZEbWuPu6udD4GVH9WwRENT1yjC4k1EgQnHfQ +2/4pYoqzNhr0YeXXMI1LQES6+Wq3aFcKyqfcabo1Kfz0EPc1GwhGjVg+Za6IluCQ0E5vTMNdHLpF +ggy6Z6efNWEkYEP5MDBadwbQlJ9iY0207yfpX+UfeizS2QwdDKaynR2hbTNnInI0ToECehmTH5qG +1r2P0Mwtxeq9RXtWdo4kpU/tYewYfDWj4oHQqAjSjUnuDSnRUFTc/BrYtZbQyIBJNOgGwLSF1DYP +UNDu56U/GwkcmoDmWnoJGUoHSEvtUMHSBaifDtolcGq6ckJbmAfR2EpXCBRvOLsppIzNnkhjoiKH +/F9FqziGESHcPOQ6v1lsvv1O3jLLVxqLcpJ3357N5asasxfH5rhVhz/Oy0tOfrToAGcZJ5agCzzR +WXpBfMmhH4+o1hLlKmv8K32o4HnQhRaK0cb+fHT7JHP8DfsznFeTTffdLEdmbtyzhdoMVLxLrFHi +hJIjoTAym+miKBTS5tPyDTmkLdX+ZyminA2n/a3mRbcR1Y+UHoHRXrvag06dci9CrUcasGrcQkKf +Wo3bTujnbHJDn1RpDkYpK5Dx1SPtOSpnvlXEIoy7lNOgxGbJXNJueFNI+hlSe53IMBfkBti1Bw5B +UFyvWCh0fjKKfhP+tMG1V6cTK4yd6s6UXPhDoI0T/D8xW1kb3GJnXMXltm+yFjENfGoOdxEZ5pd1 +Vny8kA5Q9tKJ5dRqlH/CELGZ/PPRGoQYzv5v38Al1I28CgGvUoyRlJX3I57mTQyBCQCGoVVPuMHR +5SKfA8m2WX7hWhW96eKdv7N9o0wN+lJZxJ0SatcryGPeqotPj0T7NdnOAr3/vZs5cQkarC0mdNqh +UlxycRiLTHXrsmp7eDnhpiZOw4jOG5P7lrzaV71Mx/EqqSnBq3kPpUAljbaLdHOyPnn70yYvf11U +v+0X7XJcC/FAjfvBMDUx7UqYJId+rESBTdqq2POGWryfkS4wKn0EAjqX7Cqgwi01eOwv8BOTMjOE +1qUowEkHNF8PrlqkmVcoee2rXCj4Y8PBLIZr2COixtvVmGFTjJP4T10LVu2S2BIo6vEjESK8i+Ix +mYS9Ri+GBh+h20M/u8Yln01w73vRhmMXq8B6Gdu3AT2VLX5gi9nSuHNeOqAmY/CgF2tMmM2h+ab6 +R0QSvxQ1mp4MJ3lUfM/0Ck93IxqXuNTuMvQEdJHjixozAWjbSsjNVr1guJoVrLnPwgiPcpTYMcfd +lTArbm2CdflpQNXlCULtr93+K1y+OmYNYA9FeY/OvkGj9hq+HWoXij6gW/tQxOT8YxZatwN95/4F +rTuEdq7/Nl0OHP44I2B9tQeGlsC2D8RcTcxNwg+Z0kcEqR/eNuXaq0XuPNCFZfs2s4kEFfiMlwOH +gI94youuNHO6ZVfxVTSDF91+oUwZOeVWIEQEKbo1ZVA+Gy+yd27k+tPiss6NDh6RDwvwGjuu6Z1F +Wo5dUV5bkG+m3gBoOhiX+iSc6Vudx4DSzeX+8iX/mHQ3YgYYOKvKG8Rp2+mPRnHh5nKCIApWLGCN +EvyPrFhFnEYkrxiYqOfHUYoSZLnO+nwtIU6T+HWFVrATHnby62QzarXMgYP3rOYvWfPB7IaMzFqI +cHldMIYWJ/iFgCHihTG53BvKZSwg/fH6up7UVaUJMku9+SHPt9OKuJRqKb+Sv6i4g3axVnofDYo6 +JlnxyYQYQX0nSqtFFUoOqIA4x3w7cCXTQzls0/f/Ytna0wkyw7F17OKGUGgonGZxPESNdFkHVIyH +aG6HPokcpBShzaMLEGe4OMgOGin9XAY6H2dZi2rzqN0unqtpTBShdRY325eqddz0CX3JpAL5mjbn +6WW03VMRpI0nvJSkF9XkbTCXr8Aghkflx+2VLnxUs+/vKgmZR2BdOf9pUYSI5gTd99bGuH30auO+ +P48Ev9xsAwlveux7oXWeK3fVIGkbLnnAyOxpuaSmEoGsxmO6o2Vf7IazKbRxKEP+0OMbq8gp7gFr +sJHorZOkUgUULj5tsyZKhPGLJZ9hRbipT6uAH9iZJiBG+JA4rmInLt9TMXvZHGm6TqyvbJDFlNjs +Et/XDYGMhM1abuqTI4j1yAmOsp5od6p03WsgOljE62MZZVGFLaS9E2rBmN9KyJwQBBC+Eh9vGEtR +8MoNhFbM0+qCak8zqMgLxcIvAKdcmonyXiS7UMJ5XQlMd/LkfdAlAvOBmln0nOo6B+P/o1py9k5D +3WtS865C8SMd4PIgD5uP+f2eq2S5PjluaVl8GDpYemtCnbUJ1AsL97bMNjUT1aadkaoiNQJ4s0F9 +c38l/TDitqD6Imgc1ZQhBVaBRY+ACkPlgOzBFPkgw9CtC1NUvAYXdTKjiDodAngqolrxYUwD3yol +9jEmGDBSTSyBuVyx6HibeOLS5lC1Sa94NwzAEUL3icTskVvJgsqXHB2CyX7cGyZTshv5fTTR4oEv +GyXoi2l7oZdOxWFVlUQloCrjJofsUdGZyyTSnYiLRksQqJxg/xcsZ6KUlZsCt56x3HiVTBCBIINR +pL0V0luEFEExia6DmWTCucAGkc+Aq7jwPs5FE1QPF0Qqu8AlLAX9O+gcZNdHJ4VCMM+djcu0U1AD +AGldpYq0yJAsHAb8LR8AcnDF/2x/ni2tfEHps20QlVeNUcD8gES7ucaKxeMDEfuKDC+LowvkRJpA +0x6a0PCZ1lUXUEpGAV9HrSayFuKIpbJoLSy6W1lF+2ce2awNbMANYcNKaV7Zk25swTiQOcQ4DqB9 +wq2cjaAdSTo9g1zyrJLbrE1SidnhgrtVSOI6K97+OZwwMZipJjO11d9wzLOzQgDDFsd65pEmxe9U +cDM4YFi9YadVP2oh+rBUcjwAhwvf32LS6K0NNALM1njS99jH0kgvHlmOLmy0jRAh3R7PYs9GqEHi +CpkMKZNogxiZa030H7sbJtYreNHNqotpA7ffdXRQHv/7npNI5tV8AynrA+hQARSIwkJoc0u3k/gP +cij2afdowvVy6Io4OxtIfLqTnXzjfEcUgvly8aGdwMSmk/KMg8iKj2HUIJz7FMpsGoHZYF7F5mSr +DIk3BxtMTRvd5alEJryESANby7RyuvNV4OdlmynaiO6ruYRdf/xBa6WyKpWAj3YWHBF1BQJsdXkb +Tf+cI31gViw2Yz+rvV9KkaFVRJv/opFDk3IS1RzVKZDuaPn8HGe7msXQJKdlYrtb+oRWlEX/5ubD +6AIh8Lw0Rr/7mH6McTGhPfsu9bCR86MO/emN/EGMFKxrlqeleVeH1NqRz7IObBsqrzZCMencmMBL +PBFEF4tZ9dXuMwxMtHNA+MQDBPZsZUF/tzn/ISsfBnEOa2GX42y1HAW5iT+aa3fV6mI/fasSCI57 +FmGxr7b1yBCjwbs0KoFAVudLNiy3gRmM83m3+4ZwD1FVyCj8yaZzXUJhThZgvW5960uRV6mY1Xxd +UNikNb//lY6ur+aPNr3sm99y2aI6bX1F35HNMYSN+D7ozR/bw4nBP7r5m2oqFYWFzqx68p5mxmO6 +vp84WrdRX+DzxJJetwYPmBaaamsj43KpZagytuQ2UFMRy97i6opQw7KoE14yP5gvnYzt6/EF7hRL +2g8h3pI6KbKVrPL4wFqYerO5dtyepwU7MlBGf5IQ6/jNVfde4/s2Nw80rhT9nZdbKCrjAHnEhQes +61l8P67guqpeCSTp7gflrij6mCmVvU41iDvxARwdYIvw2qQLddopwkGwzPvRCCHKPk2nxBdHF6v6 +gDvHNCvNfes4XJsBzBv4POSCLB0ZZipDEXL0xaVKJ1wjnzt3PlwJ8QuFCnecthHwp88lC3QFTWA5 +j45TLGKJP+Nlfp5VsPyIsFAYYcnSA4z1UTj1XmVGMl9XfDeScUF8B/HkDFipEoBkjcsuGt9bKJ2l +HLEn6tJKlGIp8wJQysH61RO44QkmWLitg0q+OFEucrYixGLVaNjdwxa19hcCQMO7rYcs9kX0cwuj +fa4ihAuVhyYaMRL9klovGyPrysF87wly+/Pbk08qlAnxDL7U1uIJt+5rkaxxNutPGeWdiTqnP7pD +/BlpdZwHEKklQkWhqwJBwr3ndvBUOPTP4I05BsJiws61+dSU8lKGF0ezv/YZYFLrXzT0ecPrnmxw +jmhrYkjQAS4WREFI9xnQ5WhaXB15RwgTnhbvnEBTW6Jjub4WzaLnbSV37lGiNTI5ek9AQv/iT+oq +/h+hxdMfBqn7GGb+jRyT7wVVDOqHquVGxzUIvkT4aSk2YF6HpbOOQJfHAekS419a7j0h5OmpSA0D +6Ww1I2FATtDUrfNLpyphkiLnqHEyazXQCHypfrgK1WUWGDvSpoRPKJTW7uPe1ZxDL0f4sIEppi+Z +MHO0kIW4XqzYPG7fSJsERvVEWddR/zGsOzxqV/CtMbILmwCsWJZaeDtlsCyBNIZBhKdRiPjQfmmg +fmxSNObsxzGr0oehX/2G9AP+HczDXem52xcIQs+QA5zpaDuq02+v+7cKgKTi1zpY+Ir4CK8np1ej +6M49S0aeoaianW2iQiEGO8Kxu97UaTMwYrthpTKDNHrkzaEBwUTSPsX3UXSgx4s5QXPo5YROBZtH +li592Mxk4hjpf9eXvdiocqUN+jd8PdVGf+P1wlmAQSW125cyEC39N+jTw/6jyUIv4jk56rOnz18y +2UgSMgkuxyfkWukM13ytRokx3WhixrP41Pm9IvvzTihmdSLgLCjD2menKZmjiJE55w4nUdbnpelD +wF0NVHVTHVkKlOyUDeOsyc5Wu91Rf7PebOQYPpxUzxhZjPF4x4VpkQbIyPyThiyqvXHbzpdONmz/ +kFSqIuUvgclYhsxy554E1Fq/Stcn/OwXdlVdDlj3WXArq2YHfr9xYW1sYRFQwd4YL6Z6SMoKkIBT +3gNy2VXALBoK6aecWXKg+b/l9wEPfNqQzxbxxV0xw+Q4ghDTsVJgf0/cAj2awmXzaeGlrtRhRkWu +hFTXrL6QBr/XR1lWbJE216vuqCBCw4lucRbN+7VCCAvB8A3FnO8qDrAedXQby/v4r8h6xP+mX237 +he5K2Ue5O2IBvD/m1AZlM3LEarOqZHf69o1xBo6D1egwmGbooMNoggE/HYWk7/fpGfizRiwlPHM7 +DswW4OGUVWRPQlWz9ywCI5uMn/ww6kSAevhakj9XCKfodccAdl+Dzhvke9vqihWmh5VkkAqgP+g/ +KGmOHZENuujF6hdVPYpU8mr9Rw1/Gr9Uh4jl204GOOkR+fTwewdVpOPtecSGcxVomZ7OYrio/Klk +u8XOvW493uxMRRgGpwuLf67JSrRBQVaRM0WVXx8A1u0TuRIq3c54L7wrNtn46PUpaPglwcwTjOl6 +YkSF7BE6ilCDZi3zbeM2qdE5k/wlDszmaTM9+LXxhwh73RMGakOEacg0KkW2tahEGs7U+4+/Ka3A +Uit8c004UbgFPQbljh8cQEE7B7CGsXNzGNDaJFQgss5/hSvJ6MdCauO7pbAU48bv1WHgx7ip2+y2 +zuR6tFl+0VzlppeTBgxsqCCmnN4scd4RooSig9OLouCYQCX8vVBuQncnmNGMCc1fPXyoNrhLFUfA +jCfOFYeQYkd0IMiJZvLMk5agsIF4QXR94KZkmxVNcbcUf0YTCTJgfWciu3gWLRk9/oISt8Us95sM +Ns6Cd9Z5eDO/sz4+uvAVUeK33qNuomssfpw+XAtKKCishaUT9B2GLzPQ9mOTs7ywqQiOywC3//R6 +PSBniP90RRj3Pb8hHYyd5zUxdqkDyxPnZjCxqFfKGT+w0TFHg9gRa588hWNLnsnls2EDo4+uWmGO +fYlPNAUvGF/KbidEBvNiabi2ygD9DgymKGb56NkHoKxvwan6Rrv2zxHpYpuokU9+SHd9Z8455fPW +4pATygBZG78l2Ia5jqPrqSLPQYDAMjmkJCexu07d7bNZvPVbYfFPpHoXK4PP7ONvjkwtw/ZsAv7A +cC+yXFl5EcUsQ6rLRjjmKvjD07vgwxbFYH8r+w/YAymnR98SrkFGVzJTC7Y0rF5c3+avJZ8nzp8J +rjMF7GCN2Txfs2VFdSG4mtve97dxbuf94itS7VHGaPfJiRu6cMJpKWxXccw0OVBxRIuZjAXImZVH +0SOfRCy4G4agWkB4BPWwgxUm6Zjxrvj995d1x7JW5ET6t3Iv5TPzzEG7mu72cDZR59KpE4skWbWE +B27ptrd+EPeZHoo//sljVur6hdi2CxzWsQbdAoKbs9vYYJgTxX8COZN16myrRaXZO8zQ4hL57HVf +43f51MPd76IzzwS0+21KfnfekH3HpDr3o/XlWmf+1/zsEwQHV/I6RMfQ0ooVgAg4+HBDMkgOoruA +XPfUny3Hd77RudbmAEEyXNuyYfjZp0KrUDN7nNGPNAm27UxUqoNxDNT78kEfFhSnQ64hQgCMSwqa +DPvMXGnsZc5o1LjM9w7R5dxWzD5lay+VpuL1wJYUBI4+NIx7Vb5mcV2msPoeYtD2RbQV7QV7FN0h +RaCrn1f2EsgH3Rz6EiSpQxpHnXK9wHNKDlGvRZO+4IgJo3rUYU5Mu515G5u1NWAcybPhb8HTcfSH ++suUm41eDK36XSiFs8ahYULxls4PyXku51ebjtLoVA2UR/tK/imi9wYNCXWH0d0MYzHa5OtipRP5 +NHM9eA5UsM7BQmO8tW/+rcY6IF4VpHkp9WxgXkCb0w9SqCn67XAgNdS886HrfZ2+fpd3hwXWXA1s +hhHmVHXRiLSgqcqimjcpHFMkUaQ3jxa412vt3PQUwcHpF0gRlEIdDzZd2Raggq7pA0QFTSTXZU4f +AOWyc8JmqGMBhGsG304hhO5NyY0m/rfosv0lEKnDxoB7gzytwODfsd9twyBnoHu8mCoDngu36Dmy +W5QoKOwFzTat9EuMqTS2/+x2f+PnA0V4T8mETcmrA89c6Hv3navldCcZ6rwWKsK+zqy1l+7dXvk4 +jk1hfGHfLC1qGZwwqrG7PfAzzgQP1T3+1Ux7O/4BoaWErgQbCN6lUm/OA5vsVA37Q6tAF8lQcap0 +CqtoIGE4GPJgfdpXVQpHoh2FQlJFn2JMk28cxrR6m9hrFpuu1YMJHlsl5107I3CPSM2TMhZ7/2cG +4wBCyQzz6bAwLoK7Xwh8y8F6RPHT/pEiivgQLmlzl9hiMzXIfHsp2s1809mSrKWT23tNTNsECL8M +KnrrBq1LNfaXKrwxcCriVs9qX5az9JjKJdvTQbPu1CVGqF441UeRGHab+vmHSG4Vho/ML/EosuAn +/9Tmq2g/rKD5GHhjI4otA7EEzekJVAi14Dvkq47cHu65wUAmnAsd1IgGc92gSdzjgLRDSJguqmM0 +Qp9iEqw3rE8QjQEOTmh6ETzA7sqgI/pwyAdzQvnZHWgowUHy7hno5xmyi4IL4wP6msonTAjVV9vn +a8oZ/A1FO742hM0FG2qVl4wcNY8YFO64yEHJ95KXAbLqZA97Jjm5M0Cvhkh8Sl16tLmWuAIMyhRX +8Z3wsrVt1pdBuAruI/VEOcsY7rqxNq19uMvRaHvpN2pCVgp1r5XQh+WWuZMuQkfzgBnGKQryJTuD +T+dNXZewmzhiG9uDJtTgU6GtEZuNQFmCXjiKN7KqEe0IKp1nTkH/8mN1E2b4jD150TRgkKQuSCEp +vlYAbPe5WOqWK+RvsV2iFgOC05AfP0urhC4PKxegK91KmJ7/k7DCd3vt1bsQ9G0jh0+ErJnW8IeK +rFe17SeTMF6oNGrQP3tf2+Tmp1S+vGocixJjlFisbb574h8rfTOdgWBLXa5S1ymwNA8mFqgWeGgz +h/fcz6hsmjbcliD1IkJz43xhpbKM5ZWNw+or03+eGo7UU58Ftdo6i0p64YrPYqSDDbFiLvW/6KO5 +sfmVQ+gJhV8uSCeb7v6MOlwkTNe+h3/u7qf6whee6KSrhCW1uCxaSz3aaOwZU0UngapgalLX8m8V +MVrb8z5BAi26z5RIrAGz9fGgrQ0wsLWn5/v7wrc7fqZJ+QGv5LBMkMhOHW+GD+EjkJwNdv71bwpA +PKm7OUiUaQ7NiuUUruLiyCSteeYpGRNb5e/QSxfSA/yEyH57KLQ5qY16PBN6Ro26erNcmci1zuoA +HTgp30oL4p8c2JDjJc+PQ5p+nejSDLPGtTh+ynWREsIeo/RDCH3x5ogLP2V9QJAggzJ1r3Y9DCFS +sZZfpjvwuPHeclcPbUxuYvo9vAmG0I8D1BHDTIKOnByIMN+8w/XKU+H3MRFU22OieFX5D2L2WXIv +u3Q6c5kVOIcopIRkO2fah367smfsqv+aXD20fLE7KJIasDB0XOCdJT2Nrn4fQex1VfF4kd7eTxHn +ltuSXARNJJDH0Ea4OqyXFy7pbn7A3xXJJU4+buCwTXNuslkDZbYdZ4PBwatyU4MaRrxeTipWwNoU +O/2ZeU1m/1N2d+QZ/062HqBtjswyd79rtckQSaBtsxt+p3gQHQVYM2u5MKyp/n/Dz5zlXJk+4NOd +XctvPI05lkh345GzpcShTl6kq1KQarQrrfKh49ylKlyHd/VknvcSv1dNpGfrVnzKyNZVQhIgzwDE +rhuJLP89MWLoq6ASz9y49XMO5S5bELT4dNealPQr9P3x7FGwSp3lXjv1RXb2Bnu68kAPTIZCKBTr ++ttjCek3nNiLxreMXNivmm+5yQoqS7N7+7VPuZocpFe/p4VwOhMhBXLbfvdAi8iu5fOycl42mffc +1ebD3QPM9SSVe6FFPVgbvqr9V55XrOMzl5+hZ8eSvszHVGCDxO4Sh8/giF/QUXvn9iVeJNeNJYkw +bKaVjIQqA56337YjvlCFgSefbS79vazdpxANgV98E5DRE+GwidaTSozeYxGR37TbKs5b80m3eNTf +rvFORDoTj6vHRSefxv+Yq5fJWGqdDAHHF6ql3LrXRfuU6kynX+HmB6AhcnkTXqGfn6dWQlGZaLt+ +0iKja0mt5vPwh3TxzyX5XszK2WRtf8TxwgC1JacM5L1PsVn5OMEVeY6rW/gbyvtIU4ENJUDmBr04 +StoBoMYwi+fQxut537iE2GaC0GGoycuQ6YX7joWVCP79XfQjkvDT60lVgX9AE3GIGpFG9a1K7Xka +gg/AbKKwotZUbcC2Wfk+9oGODy+fQHJo0sA8uoXtCpIHgLPfew4yniPL62i2QiWBg27O0E+/0d8j +/TD7DRdgogDUv5oIlvitnFohjLaOPJmb+G2woZSKA3o0SlDW4xN7OPpNFvmM3Gc//IS8zsqAmsEH +JWmiPUi2VDjx0N0dVxnIsu9bw9C5zG67cFelE1bLBJv/hD2TU2smOgd10npjzk4QHEktuxougn73 +kDvkukWTYeVeJnBrGPdDuPtM2K4knYYwsXyUN4X7/WHDrVz4E54CQIOrJxqJCmcLkP89j788rzpI +g6vqxb4PTToSubZQzZ4N8P7C49n7yy2xwQNlm5N8wln7sMKvp+Q9UAoqIa8eaEd2wbmEKCmv1TZ7 +V/vQzii5orWrDxOHFpX98a7zduhSnKZie1hN2bMcZo03ZY7RqRBQNv4IMwo81kT6pj04Q38Lg38S +TqWrdrfrFMB6d32c2tkuozl3L1aGPNDV5RbMS1SNhqRwvkJg9CDu8XRqcHR/0q3uuTNVoBzLH9it +5IRwkgljxNhFPw72UHkBBW5H/UUePWlUdW6NxyZjOpSCoHn94ch1vutbaW3B9+RscJRx01lo1Q59 +UbmKDfByCTtWZ7EjXIbfRXpv94ksVetIhvrj1iDqFcbHEm9d544EMXATlFeHzIW2L5ZHVDgEVJov +ZVelZ3EYDM//Aw8yzAnnqE8yTHvfyiEXAIXaINPADxQQF7MDjtMasfc+uRkvBazZBD2omzuj2DC5 +eVSXs+qfQhzmI0VjX2dr7+00odIBGuRXqSGPyeQx7ERJwdGNQvRAamzGUdiUBzUhX2GLngb99kdN +sXVjO4503j0z5sKHIPQQ8nS4C3v5uTM5nff+C26RbUme/6WTfW1n4JibOH0Fn83BREP1VOUBrkyY +m1WsGFZ7JYI9JUneLnJe53KIu3+LQvcvhdNdDGR7c0oCNGK5MDSjbEWuFyZFJRz6NtLwWZbNS4hy +BWk2YkKPthE2O+96qaAeoW61GEK3KpDrOPj3CE8w3nK4/OJHRcS2bQYkVNRv94bpT8g7sFROsclf +xKK6vpGb7NJacNsDlCyOWDU0kaOdM9f/F4eSTmPByYboQxbCzuq0EaeC8zV3537APsqzCGXWFnK6 +/4RlOjJ+Txo2cKEIGwewikJXNYk98sssBFsBodxgP6GO3K7Mqh4iZPLfLQf2IZjndgHZ/yS2apPl +QmVj/PKMl3Ltg5Hdn+gHJirTfhCDImTgceZUUcuxgrq3dfefx1lGuzeUrQidcDEc3DabfWK0aTUo +VINGMq/cL9UW92+yXY0vb6ZyaxSljEXbil3gywrDwoycMGs72MK1feGP7YWH6CwA4NvNUJvoeRh3 +lJgsihw5WBIc43HI/LgCXzyxHVcnmH6swaSuhccbHaWlf960xo0saOQEQh3gJT9fc/EmHjxR5qF3 +f6Qx1+u17HXmcoXZUmGuWvCKwlKJvt3znO+WOTxngLDXmAFc7DCgS37nX5uAGR0sU0bT26Im6UdY +ab7IcyjKFXHUjsBIH0GvS6QyTOwV0uSOIy3df2zuzktaBidVQV+qSYxJyWehwaYlFjhd+rCyPfHn ++hEE1BubZs8pvjm+DSZ4RbklVCN5NZ1rud8SANUQ/MoRKye7cTp1F3FLoSEIoDBJxKrwaPn1DeR/ +Q4ZAv8Dd4ylbPP8EpGpwpUR2xNa8t37wqSBgPZ+0BEwm93pUEiZqQ9hxWKUuxySu/bAyT9WNQqQE +JOMHfCtYzceS3/d+AfkF2fU/SOrXgPShZVxKERFf2yaAEmqv6OP/z5G7B/VLTMSM4nMcoLE7/x2Z +Yqeh2FDrH6WYxuUPZdXx7Zt27doh1DLGAyjCGnoYNn3L/b0qF1HCkJBPKL8Rynh8KefShgCzJApd +/+UhwfRqlmXCEtpIVFg7yq16y/mDDOCWdIOz+1nQ6/4lX4fzS+UX3E/hOsqeF5jM39TpUNp8b5VB +bW6G2VBF7AS3w/khmJcJfYXZWRxfTRuv91p7cjlYVjQrmJzgeXdZa9CHWxjq5q2+gimqz7bD6V7i +uGRNo1elE8fHlBJu0Wq79h/t0LlOTseqLnv73vMNELwpWfwTk16/HXroFUrOhvfB9nfRE1C5aMUQ +zeb5LqYsAspTHz4qaZYwR4T4EFj0e+hPaPu5cnK8pD2iVIGDvg0Gv12P22c4KbbpnZOdBz4jKavg +x4LYIFdT/E66ew3YDD6uCZ57w6MvUelIzzykqeP1r9bnZd7E1NCwjgDyQ0B2uZlvfo4br8pFmVva +TerCA/jErqOAX3LE9CtB35kB9Pt4brL1t74VF6gaZCSaUQEy/mY338wbWDZLHIkyDSuVnJwwwM+z +JEXDhRblWQ4nwFNepxQdNYXPh5rNsXDosdNdkxAUliIEpnJVO966/wdP9gttCpLwXyz9Tln1WYqT +DY5lNRjp2+VCgtJgJ3VEO+jgsM6EZWVRDw5NFRTlazVU45wnM4dJ0NvWg9Gld26Ue3jdKDa8Ub3n +JbNnuJPKnS/wP6FxjkEsg5OvFKtK2NCM75ZS7wwF9YO4RtwvIU3ANc5pvGNe6yKejZJhiN1B2/Vd +uPJJc8QHAuTj76Vdh/cgX5a8IIyuur/jscSplGbSFU5vWpBAFSXZujYNFg6QZjD+5znZrVt+cA4d +KCdeHrdt8LyN+vgxpmtJ4b0qXa/UdI9rb9odUGu9pfSsz+630f/xibN4wBGyQMZ6ZU7vAI6wETRa +XfanMjoL83VhKoOu8N7uf6tOFqnkLx3YwxiIOTb9ZzkBO+EH01bIOEf4GQX+5Hl7CTdFnxDcp2Me +RWEVfYitv+jNmFpw/gmPV4e99XboLuJhQQkccm5bUaAA3bYj5KE8ZbQPkH4zibFVuxEU+6GulCHK +EKO7FjIUi3yZwc0TtkT9SiSy7ATiWmFQWl0KXHLYAlzHk5TALO48R7q/14JDbRqfCya9TB9MuGC6 +1vV1FFvXuRG5Cab0gQi7GlfEO7S8ZxdE12S7mIpvyb5XGt6U/sulsRuoFbQED6vxaQSGPuLDsQ2/ +yhuX6N6RD8otgSlWAPd8e0RaufhmAxOG946dhNmw41tumLpQ+Fht5EsVN7coYyQ/ZhsXz0BPNQpI +dMkPbhz43n26fs1JCb27OfZoKYWv8ucN3pEOrq1p6P3yfGV3W0iDiuAyFjBfGeZ88VVRL5meUi5C +Xfi0nw3W5VZBm8m4LtIdC+H3dqkuLOeitT/P8FmLJDSDroxfYmKrbXVtaJCLWo0Rbi0tZiBo+B2t +pLYUcgaAOg3Rrcd13GgTjjkFqcOwuTV9KP0M4udbqt+A213d5Ru719bQLaqJYTMqvI4OQJNs/YVi +lZmhJSEPBkkqppw9cJRnuwrXx75kIpchNEicyI8v4bewlEfTpdsQSAgCQLCQoDyFB83OzUWeEXcX +LqZ/iRtqi5dgVSFKV+KeUlJc1xnsDmIA9yL8qQXKlrNpzDpasHREyLP7zs1ZDG0sdDqhrXCjHalE +AG/cc3zoIU1/z5zhaHjKkHUu6wnyECOw4+amoT3sxP35uN/QxRLBW0Kp7OOYHaYZdEG/dcA6fVh7 +fOpeAEwfG4aw+SbfmSOH9kXG5HA5nFDHZDfKswHhiF9uMn4sUlcLaDu1itEEN5fOjyqFd6UJNniJ +PgzxApWAuTMBJzNdOzZb/39aBRpMIBIOkPwtOoii2ly/T9AKLSRH8POpeX6ksIci0gany5iX8qvb +ivElUSGcwgn9s8H3ruYJft+4At0SWcXirq2khtHJBf2IfIr1SwQaxWVz3zW1Ry+fOS2ZrkLMOIWd +whwFAG3KS0Ksm+apIiQAPGjhhLRvtlT3gtydyLruw6dPE+VtOlQoxE43hZs9NIxPFyVdSS77lYxF +gm5PEkvO4Z3XlzqZ7DY2SB6X6E2RqDH/xXGeT29HNaB0bRNkhBXyp8v9tN5KBca+tQqaa5jZLxhw +DjF8c2IlWqGoZIsBk/miWSyUDAMWUw07CtDcw2jv4qKGKIOQDg6fljGAC5ZXcPfyqucXgN+E9l95 +PfHz3LT28D/WBstlJimfGwTZ2iZ1nM6r2gz2GUxakIUPLCG/a0eDVfyz14+cGsGLxJdlAyD18n1G +jSRMvaUiNvJlybg5JdFMfLr90jv1owhEX5q4IfrQHMOPYGoySt41oxZ5GNz8d894ACqa5KdbR7oJ +fBT6Un0vowZ8dtWAbYsoyQzJHzki1bUe8RcLLF6Nc7yW1NS6qKqbIqypllREjg8qowBs77PREIKy +TRXEaPR3l4zlThwuMUDGxzbUzv62JdfMdpiQLlh8iYPx8BFY0Gc1jUWi4TxxaFCl1V1GN5369124 +VUFPvqeojcYfD0Ae5Xy2HD/Jy2YSofU8JBJquTsDntOPbce7rZfPrtf8Uq7caY2RSMlDukAGNnyE +fuTWN35wC8Ygcev0QJ9OWYK/L55H4L3jiQt+F0A52gn06KnzgtBSI3dOjGIjZ90oUfB62NeJOrGd +SX5P7vlU6FS5WI3DT1JBeYi6R0utNIrI/NkWa3PO9HohUGooXbvtyhGUfji7WOHrWOLXlZwT/2fs +yHU6F7gPjPpVjo/4r7JRmvcXoADPhvcasW60TW9/2Xb2B81ZVseFuIwqSpVLp4rT0lSh0gsI6dlb +2ALqaUQLlg0L1GX0C9D4l+b5d1dJaIzjuKf/m5pRvHkjT5v6O37EOdImwEHCakoYKU0mypFomqcy +oglsB5sjhSyoVSP8qfZGAqbUthGQApP+m68/ZxxjbpM9JYyBvync63AahmGpzR5tDoVCqliqKsFX +cJ7FLcEomxPm9t8zBi0tceJo+aSs4vdhXtFAZszox16YibCtM5se82u/pon1Sy1XfwNMy9kIsrZf +l5zqu1J96xYsx3CxiZV4jSJn8jvnyrmBDG4rp1DMg8bDXQEgUjjsxlhMXKsL82gylgcQlFF1lR/m +I/aF46fhoI8dX2U/+zX/Z6XNE1MuPTlDAO4pV+fLVNUK041zgSSR+N25/LJfRgfvLrmN4adBzwnB +cDRySYqu+WchOMpdeVfrze3R67K1u1YN0cjUD7ywBN3e4eocb4JyMWuHbBVOxbqeicusjDHIKfLE +ReqksWq2YyzsjrbLqo2AODtYw2k9YqdBezry4aUesW7cXaYO02Hy/oh9GZbdIJ3FG1kFDs01ugI6 +jz0KSBihrPMOYM99cY6wQU6kda3WDQqq3ozUX4jLWsDuKmhhsGqrtVdMa74v6g5XXSh4mV5HvPML +TtQ/0TjcClgCMU5cEcb4q69TAhZDoJRxarzZq5EXCowsRZWD36PCt+7NQYKsICwT1kxapYtIA8JG +NW8XSORzxiB2y0/dFq7t1sP/TiXVVJDGIEyBv4UATFco5F51TZklBmjIqZ/VvcSbNUKapWIcwIsg +tACOiYXD1hkhbtNNMJaS6ySdJry0qWiHdHncumWN7ywH/PDdHXJ77Xn7VZSpO77j0BuRjJaYk+CA +RgSg6LuDhIRNl+krF/h04yLE1CgT9XhjzGCE8EoxCvNWdo/dCrnFjqKMvGnBZIKsf+z8w/Lteyfx +hjiNy4lAeL7OCzitu6zhJ/65AZgy3N6pbS9y/A9TOz6F1hvV+34m0RcVUb1SODgKgvp1sHbXEFTB +j5taM21fnIkBtqnxmGAubOFkiHOwNOOkwoGm39pKwxM8DvOlwiImX9CVp1WSerZF+vcK/EJcPNDK +n/GNJp0oiGn3PZFfoEAdduWVuzZuMJn+J6kEy8ZAdeygQrifsx09taZvDhWXW4a46wd3P6dizfQM +JoGTpZyAmuZKfB7fx45nsgvILLG7j5F18XSJN/+jesf3eMqM5dv3Jkrlv0apbt/fULBQzA7yIIWo +dLAtbHVA4Z6/+MLEImeVsLFOSIUiPNWdcqQNGfnyaIhUP7AuHkhw2wrsWLuTOzaJ+HFpi8Xtz6y5 +NoaVbKw90U+0vaLt+gPh2tX50ifF+7pkSkOmmoOSyMgmMs/43TPaSbiWmES4XFSgzU1bjz4Y7kaw +WIrbF5Q4DdaXspvb2UdSodvG3eEpSuHB+hScj0zxpWGx9wzi1dz5cWJcVHueVio23WVn4nTjRZxC +Oaz8xhzq/MzVd+dzZhrAQIxjilnRYafI/by7TY4uCifCO6L34eU9rlFrxw6O3/nAe/wEQSoBDQ49 +lBNUQTXu42SDU1bYpei9n5OZp1R/nuWIA9Jtyy4wK87Is/52uux5xTNQ7loGQ+LPf8mPlT2MrccN +HIPO6tJAOTKWJpNalj+iG6nfaK83jkib3u1NargA24jTvUEWou2lMLNV96LwC/5fbJE827VHsROn +H/3FlyGdYTQmeHHgD6MuWyCbpNF17sbAJV/fEqLEFig9ppkgEQBP4gPNF5s19Zo18yHlzwav1gCR +oMvu65oIIxHpVFqILO9KID9hZwDqfEKlk8+6MUWiBtpcmMYTn2VDixxU9HWD1CJV19EH1SYSIW2y +FOlZvfEr0XgYFWd2xfOKwNukGZAwb+2PL9oVVFXqaHQBk1YQZsGoI+mYZ+Oj4V7oztHRj0JZ1a7m +nk5JATsbCyBpsy45pYnspei37qR0L6GeFs1QV/9vGM9oZD0u5A1ZzetejQ2Ulp2+21T0E9eG613D +rFfSr721jmJSvtRk2tNgpLTMEI9BnGAObQ0iLVv0KvKtORUnMyRVX7Q0xIZWhENVTiHKnBj+P0B9 +rFOnf8nTaF2orndrui4rb+/x+seDsIbw1btxYSLTxywiknPllTtgWkHByjK2b4395Ytnh5V62G1G +LqT8NP8j6wSoH4YKlfe4grXbfZxxUjQUI9neJKbvW0t45AfFi7IM3FVtkHlnqYm670qc+ijmGozZ +XBo1hftvl+pFkujHLn0wu1n3PQeTKWYNPjY5ASft3KbO1a3t9R7Sa3Mlg9JR7zgTZy+cq+jD2Egb +nLcaCCvTQ9N3jbFZEC4X5qysY6XgQuyI6OqdNjXNUOffDViJnVVPofG9otyCWEhMYfqnp1AXOxjj +CjjWLErB5hctAiL6Zfp2AT9KebdfnKBDBzsytkkv7g2kdI7UPOlWNCPRzUHvrZQ7cuHezXcZe1o6 +nESnBnsgaEn7nK1EnMZrOoFzecTdn5u0WLzql7KfcIhy+ObnaP6FOdFIDAjAOLv2QYoMS7jNf+1p +kQvzA1/+Ic/dHuyGX/V8FxChSI3NQZhsqx/sevvZVLIX7lF8dWNjKWTPastFerF9SchLa12TLAdn +/tsFuFy4eN06vwor3XGd2TLQxcHzotqu4y/7NctTa7xDqL2FmMMVPxJiCx4ROj8KLDi/DMgj6AlT +R1F7/6YYaruxYmCC98d/kAPHoViYWDDt4Cfy2qhM9OHHljynOTngF+b3icplT0bnFYs+8M7TtvTt +OVe4Mw/V7VTZCxRlkwLuxXkB93Gxw7MoFKRhzeiOxroBdNm61ZCokPYPI/8ENKuyOByAG3egA44e +GfeF+eB0EC27CxXoda/pb7ScB3lH7pOR6ZP6xBMHSIbySF0o/GmJf7f5Kd42cu7hoY99kJWGZRgc +QLnQN9zPE1YmnhFfUrxp0S4UhHDbxy6vPpKocbLNexMr/Bt2F8shJShHZOWh53439L44myZLe+ta +hfp3y2ogVNxjSy3Gd0Ki4KS1cSj5IsG6h95FnKMPVky6I0YjJDvPUPFnzWm91vKys7lrPm5HuuqD +WABfeNotDjyhuDWCGKcjsA5zVwpLGnCn9As0e90SCnZzXgoqbig3i43W+Hs48PS4KQpGvJGApxeB +66rcJG4Jv+TcSYoljg65oeVNzbF/D31ITARdBEFPDSRLxFmeGuHqjrHUd4e3QnlOHU13hhiMIK/W +ZLpGOOm+ifO4muIMxmgD3hdGmlSdWc+8XZXPpZD8QoczYt+3WvAV8645vgA1CeJgGGNf4ObcJmeS +t/pPiTeu/5ZwwwKiOi3nun0SWGCaZ3emE6n02thUjHg/Bn+GH4dbi/zEOHHWCu6vD+vdRCpUn5mB +HdqlLLiPDgSO9P3j8QGTpSCoDmDFSh74MULruniINJH2y2iC+z/Bqym7Wr9JXpHsrtyQNpDCwzdO +q7tJ34G2z2hMG4H35NnMu376UrzeQNvdzUsFRGORV6J767j36XzF0siePW/SZ2st2RcfX+N4LYiQ +BPYSZaDtSLMDGf8kpOlKdJPRAM9dnCPHaLpQ38JPewaMp0qHcYQmU1K/EOO8V4lvSQw6xc9yPqMB +WEyU3qILe5viZD6JUsuJC689F62eoWuQ7qnWcm6nHney0c5bK3wbvr07v0QjPZN/FRMGZTdjWI6Q +lVGuhOrhunJgBpX2raxpkWx0TSduZ4G9hmOuik2eLyhOk5nySYa90b9exSUVFGowWV/kSXkEu0lU +HfQ284BQvLnf3QCFfln96+KfuvAN1wZjccbd6CIlrSAsHGn5f73Icxcn+cbt2+bZeW6diEfcqD3D +8bWwqqmUUxkrIOHMZUHr7WB7NtaIkB8U9VkkxAQj5X0urNPVTcP8u5ZAUM10qnxjN1Cw+rxnZLXU +1ECwLnG0sSec7gHb8v7x6bcv25KdZrYo98nHPxK/6iBpSplvPaGBYgq4nSrb/bLvMJh8MZ2VP6E5 +NuFs8kXdZI8Jxg79hvePArl94qRdece1DnakxYuAzuK2m3cFw3QIfcaPCRHzqaTN7xUYTOesLh5V +svSNuGxggWHa9zvp+BIKqyveaZdmMOlwbyev1wgLC1VyFiNW7L51pDXy+YMpMgpL9CkRyiA8an9a +dJXNJueNM5Ejb5OH4XQgWhgagtPyDpR3gppmwTp/KdylxuTOj592cFSFd492UqND+UG6giq5CqEn +NJdaX3G9teed5wfi2xHy4I6fJD8Wk8VKo2OYk4LaQtdcxJGMC2CYj2XyPe1B1tIej8PRfyQQ0MXK +mlTopOm2XOxBA0Cf2pqTV4bojb/91jYE8riJqBczIhs4wgADnPsr4hnJSvaQb1L/6mBEJUSRA/fC +XwtrLDagRp0KiTqgB2557JIvjGBZD6IKkZXR6FuShGSc4WpePTO5tFHkx6DVPmbxzvLdaPJOBpaX +jRGlohzCJOwwdv4rVnqOBlTmd/yCaKra7wxClaMQPxhkfkG6rjvWnTUfeH0V8kInzo5fhr46Rui1 +v398BixXajLrsrrBCC4oVaXxn4WCNSCUVh5fJOy45LLzaGOgy8wo2rRqIBqWD7ZH8xKUKrnykg7B +aFKyHlmrqMEjrNkuVBjDR9mXo2XRfs2IcuCjdV4JaQ/Vsbg8aWxrYjXskjPtsmo4UwRCXCpMG0QD +yjbsKvYr8HYULHO0cPcI/8s5eQR8VOQ6KDa7sQP72WEX2GOX9FdJMsNpRBELqeUNHvolVQFME22y +C33pCw5DuRiB0nrq41M5W9AixfZd0Jh3U/9YAjfBNihEAhHs5LZQlBS8cvnTCy1sV8QldiVBZvjb +diqPuxY5HXwLiVmoDBNjcVUcrXNmcbblxSNlXlwUKVA9Sug0G24/8oOac/mquBP0Eeu0hsaD+1K6 +ZNBSGspZT9t5ZXkIrS9Cu3TP+qo3rZ95+g0tujK4T0FlQOcfSO+SvlwAuiX4s6TMu56KIMej4I15 +vrx4tCEMp/FhAoYunzaPB2YrpYIwxV0aQRGX/mcvkA4ezjuHQjOBlH3qimvgKjBSt7aYk6uY7/lM +Y+NRdB65hTXMqR+BQZWXYhBy7vw5+yTC/uMt5F1zOtKfTjDCfxXhsqE0HsCcXNFyZll1bzr1sEgp +WbMJfT+Lvlb74GXj6iAoYgjp6yYtADEBEjQGAgAzEtHmyOF7UjadY1FNSpA+NQV3lRG2AYwavHfA +rZ6+MLrthXAdD4qXrDXVnCvzZw3FnHzNLGRb8hBHfo1jbBHrJdht7YBx81YvphJ3Wzv6jcRGEVq6 +rfTN3/aOPwHYExX6MhZMomF6aAfyZJo/+Ybqz1CimkAAGPyI5bmd3vCCnzGWQyMFnxF0Lvuyq/Qb +fvwDpAACpTUjrEu5Wk8znI7Zbfwxz84FHMmZ1LHn48LiLFVywwn2L1BD0kSTmwriwKj0q25lRaib +gSaLy9Z1RnC0KWGqYro1ZW+GXtvaFL4Qk0s0hrTxtn/XotMvGyk0PpiCsY2F4GEAAesQY4QDbs1M +4D/1DVwufj2K4JKC7sIiBIUVcPQwgqR6p7zpEQ3splaGD/h2+tZWr8GzyPmrdpZcHhkOU1IO1Pgs +i289SENmZ9EKn4Jwh+HUjQ0KMxKAZQVMMIbPTj2oVdAfC2iqvuqbWb5F53uc7XUI+dRrjaHdRf1O +S2dGSYoo4MvhRINmIitMK5TIXFjujnc5RNUyBoHQjzDqo+aRgGf7uzwm3PUynJLUtnI7skcnMj8d +QiBiaRgVSJiliuo/loUUNsJXKtnIbsFwc28VQ117KfdV38fUf/3sunq1DoavoE3sIyEZuEOTcX7l +I8j7FI3Juzk96EnRwMVejxHwZmdGnfuQ6g93sk9Dr9BeDaHxPZ4BeFWEXOVJi99S02lF3uTRXFzH +AdXN+Mo/IbGdCih9xKd5i2RItejTMJP6sATai9AgnyakNeVJjdCVSuxw47PDCwvEMfGKVWBPot+L +ta9oynaqU2Fg0Iq16ls0rn4InoaKbWJKo5UtsiDggbneGI9oRglaNYRkEQv6fqVnM96ZnMo1BE2A +UtWtr6QQng9KqBi5ZlcSKfDP0AI7RCREKRBfalX172Q5xNyYcrYp52WbE2aBg/WWDQGOy7EUBFDR +ECSOEjDG+VMjedgQ3q4Psnqd/6GoSdRtuAoRPz1qviaY9VDJfwxJp5qiIV/rY/s/UBlp0ebFTZPh +EmcbtjgL0BlOXYM9nIclN8/M4rK21Rb0pnVAeav6Z2vJGBvAXRVU2F3UrVeDIQ+5sN/Vy3dcyZWM ++V2ADoKtrjO9B6ca6pMDENwOiabUc4bZp6JNa5uKj0MDMknG39diF0LknikZCBgDbsAAwFLdus// +/tSv+ivjPItxPZ7lYU2ZJEiK1Y/h8Oou7z6nAscTbAkbCsud6CsaWmv34IPxAWah4KFMkGE/NYUD +x1W/gnceT3WKZ7IrO3NXkKgfjHCxpWAIMVcsfVJ1bfg9xjJooBTzFoBfl+x3pGIFUSgUaqsjlGt9 +lwd2A490lwy7fHjoj3ll45OiFtLRuRb5x+YoJcXaAgs1TbzjdUOwbmXEmxrybUgEnEhJqt1FVMwm +VxeDROAHWJkQIFOElUaRUGnX9u4go2JoWGbG2bQ7n1YUujIsOMhyW0KKLhXQ83xEFCFtOM2uHChK +ZTEkLBUNwHpG2GF2haa0xgPfPaJT0uJvk6162rulG6Z7wIakap+mYNjGYbSSOuPr/KGIM1Hl0LaB +ZzFS+JTwYr8zNLGVV85evdpMeFy1oAYhtCWeBSXWd+ZUOREkTwWtxOjLdz0dtMoWUyC9Z0IEUjRU +17yPiStCa/SriOoi325/HyO0XDzizj/sYaB8wk26U25LgbwjAqIisiJ09fd5HObp22ohpMIHmckv +skHl1bEIpugpYuotCE3C24m7R8h3NGxqa7Bd4AuCD5TTp8prFd5/0XcAhpa1YjCN8khQuF9F7958 +pgcyNR4wRssri1lsqY/LFGU+TTaE6fR17z5hs7iyU7mBD52A2ZOKVn+iPBm6rxVIKn24SjiySXvL +geNo1Il6P04Jy1cuD7w3rqi5y+ynh4RJIXmf16uGvwqQq55+HxD8+BGoHLlrJZNLhQKNg/uXNNal +GtM3Y9vWkLC2TSeQ/t84hrZOE/PzHhKrJRqRHy/N85SmmK8voxYCPRZA3I3jToXIWE8FhlUAvUxM ++vQXLG5QUd2A0Un7Wcdd+MzIdDfTRmJegxZEbedH/UpFzENbv4jd8PtKadGQ6wpmqQ2DVhx3WvSs +LBSrMM00uwSzHlslGzJUzby6FiBQzBYrg2QNx9cxBKQz9/1Cvs5aCPcBr9cGNaYVyGMbh01XOvfM +r6/ppa9LHjc0MQu/4cRwdATb406skV5u9Gfu/s9MjVehdKvGBRjfguD3pY5thAajGGdBV/MYTaA9 +BaEL4B1VqViotR0Abk9QX/ICUxRXBpq2hwLB5B4z3db5oucHzDfo3uqnkiTlY/spZTgs4SXTOh6n +0m2LYcIu/Wwhoe2uyPce7s2rVjlv7ZEspiuxCJ5yr82l8T9EvpZTlY1Kh3VamqLFWxGxjBvux3XW +Pbq8jbzz8NU2FsIqrTL9Erzmy+wDtNXPGV9EL6u0vQLd5OV2kuZNp4BPaRsRjY/rmQOW0M4jMCk1 +SN2pk2TjOFbC24Z5j5GGX8jxfA7f9GwSn5kEQbCbT7+HplRqEk/ohXh5i2FaBtYIlAd0Dx5dqaph +wrbTwu0/b9H4Vmy/rVqOVZOGWgeFfN16Nbwz6LtHiw6JNjZVPgzuXQROC8XAuIZOljzijD4RB46E +2mX156ylHONGBZyeRMl2rMhsi+u4JnMVVoRO3iITH5//fG7mpiT0bYfFjnqAO1/rSTCieQUysc1g +/IfKEYbbfnfjVUAtvH5dQpcKV8SX10YOuBhCV5z7PyEEFphn85d11TxsucltjViuSK+ryNHgTgLx +2gMajuNoL4q9LEDSHiYEERErO4PG+vdqVKOYtkp4C8Uj6VnumdiU+ZRh3QSkHjdYotSBr/2CEmAZ ++mFohVGBsAyRDcUX8P0KWSe6lzggyaclJ4SZjjhNdtZWrKeULI8wzLhZ/ZYfPM67dIPECL7Z7c/o +6BDYJ4mOMF7YBuaNt4N9QPDaa0V9NAZe1hUhCcL/8MxyahL/XADLo2G35zOBVi7oL8HhBJ+qazRY +tuoSGO5vtRxeMX98YNvlfW7D7oc1oGUD5owbS94A2jlS5Y5VlBOZNjsCAVpGm2Tl8Tu3Dd5dKEUw +kg/E7gAI0HBQ7Sl8tBsftOL+zVvszCzCBc+tGB3di4+ilQ5Ef3pDMyh/JtmGo/fzpZlBZUhlHU8A +ipv4KNbLMT4gTpPMu1vhEGud6H6xX/CEuXE96IbjQcTh0ZSvO0yMyL+ZVkoFPSfQ3WjRvgYe2ncb +6pe8sYxgS+uUaHuhZkx3JOi1HGzipqkzTR2KMm7kHYynt06zmfsJIXKpBKNWSbTweMfzR0A0/8Eb +xz/s6nFcinOtGIq2De1BTFZjB31aqONfaQpAFsTdEB+MUIAi2RUChPIdDTEUJSJurFUkL94l1DYk +KCNWPFL5L3uG12eNQlLpv0tJLv6RYE/Qp75w0xWFw98x/+dTB+5UaSry3v3lO7CSbJeRscX4tuuz +ZqRFD+ZkWx69vlYDt2A2JS6lPjMRrjQa1j9l1xlfq5LFswVruAkdzE4pKzByxS/yRCMsCmzle3Wr +5aFp83RVR6vMJamkEyQpVXCK00jACYCpU8a+z2D3QTc0CRxQ4M49FqREiIGxHz54cfocN6LjXuCh +v0xlcKUw6r09wcM5V0DLrX6xQApf0OBjJuZyVAfQpSM5AcjuvMgT+/H1V8bnqd0Ypqvi9gCaEYQm ++C6ghSD96+eGv1L3XyMPXywZS767mU8mIFkM/WDHbyJ6WcyrdfobY6f4LUeWJOvHDtMUeGQc1g19 +sl+UEPXMHDed28c8LbwA3RZlK1z7M789dwMICFYHLT5bicWPZK1bzUGCv20zvdEfE/tFJQWiN8i1 +0K9c+bk53h3wUNO1Eb+tc24IZ4GWwtdXk1HXAuqHMczED1FBdLpNYX0kBcEpcPdOydw6BFB0C7Vz +liEd6XrJ/eucBlxfL7JRiiswNaHncitZ7KNRf7jKycwKcC+mCD2i41oqAo7qdb6WSi5xDQssbCM4 +KEJzRdS5JedNgasb78sQlTlhWyfDoQ+XlULUd7Gzt9pUH+bRpq27PBKYEcd/bnGJ8D4ILHiwDPm+ +ZewEm39ND/ImFcqRKS8PAl7egHWCRM0eJX7GZOHUINw71QvwnAVRRtUchzPnh8I0HO3o95AvRDRV +FmWRGcxRr91b2XCPMZqRB/nFDshKOjvtI42wu5kSzfERme4nAU0CusLZdriF1u4l2Tc552XvDgiW +vkH6POcQnC1DOEvYhFVojN7f8NWEnT8x6iwp5NnilejEzFtO5l9cMhLKjbmDEh+wx8Y+bmuWRLA7 +/OWfr8XksQlp9u7OMcyXvrNiVhdMUd3ClPTs09egCfNC/zKutiRk/inGijO5S5oLUnWopAt7NyGx +ZoNHcEsCLloHqfHHuu6Gf4lPoMjNmV7DjEzVz9Ggp0uHKeOcMo7sbz0TryuBe+PqAfudgmjsH/rO +8kldHfH78z73HnsByPjHgIjaVtLenTp2gAXtkkVhvzlnHw553Bw61zJ6nH5Kw0PNUkdpy8LSqgY0 +4xm/OiPXQgz6fAa9K4S1xQlVTOVD5ykcgwN6Dq2Y0hlJJWOtNkD1m7hsWRFqL+YmRI/5BSgAd97i +xiKktDTTJ/XMfsmI18DL7TSTmtaNOiy/F5rXEiK42TJ6U2iC/2cnhN5uw89bOkF4h9SllF8PJrin +TKmD4zq7FYC9LVo03GuRvhB7p15YnSkAgLFv1+x0pDJA2/eOcrKqW8SbzdZbEAVLuKQpYVsAkvKQ +XPyqIYLpq/M0tXzcGjfwGGoP3djT/4DH4wv0SxG0NA7NPwp4nHNr8xdvzo3To5NFprYdQvcxM13W +LpEouvXlgaE6znB5+0W+QszKoBYchw4jy+MIzZDjl3XfrKheDobhSSV8kXCdegiqSG8fiPCIVxK6 +HjJsvTExemnPUQ7VBmEwo5t+L8iNrdGVDubAOA+J2wiOSgfynIXxZ5BjqWcY2AioIJD8Xd+aFsBf +cBeVvhuD9iIFeIPSpJBDmKsR0B77HZ7weftL8oI3u6hay3Dg8u+McVfW6tjrvKbRZdGOTeyL/MFR +Ojh4jC6uhCrbsofcr6U2xFnv2d+/mGy7T6FAkjbQiW1UBqLxhUXgOE3OpgQXYwRs8/e6NWKouOAb +rKuVPZhodh7RRFwAcVRsw3dvgF+MmHuKU4XkcCtEmWXnuxzSn8qNblNq+LL0qdy8BylkYdVcJAMT +99iZiJjx+Rr8nGwRCyiDrZuQM9u1I5ZzqsJeD0LaQ5vzW5rnjaL9q3NLtty1jkGeVD3GsIXzqYXr +N8eRuEYYvjM5XEXi6Rrpe9KetCShd4NQt1NAVYUoLMDYncOdoJgwGJSgs5A9sEy/RPRNRDxlHh+J +uMc8tNfEO7WruoHNRvzDyEyL37/duHP+O3+IcN8mDtw+g0wiOGNOU7wnUG669+c3N+38SdjNSVBx +E2KldWd0o7OdasDlL9Z9WmY/IlKHAOCXG4PPRxYNBqaQDFHD4YCzrb1SseTIJL4gF01f2lddcFc8 +Qk4DYspmkcKp9SeokVpnLTmvHyTmxjV5QQpzTYXoaC9U0+hB8D0VYDOitgrawt8JunDcAsmT8+Qm +aTU004SRN7iDecdejmBlOfjoAOKokR6gkbymWAWfNF4dRJYBzm6ZCU9LBi+fBxDG8lpM+2qtRHu9 +Dqan6UndAtJfNfNiEYIJ3r4QAu/B0QAxHh+wj5M3VQyPqUZ/SSvD5na0OgPH9FvNnIzqJierRyLP +icfIWyrMVtlkU1RxKTmutIi4ROX+YiDHAIUOF2Q53hXv71Kw4G1y7KCHojWCq209vbpP8abItxdX +PfjxqzCH1vkL69CscCkQ7WqYlf858SY4ltzCbOfbOuW2iAYLqHw7jBJGfgLD3o0L8YcoN6RH2Pgx +/gTVPeJ1QDle9csLjx3DxmelDVROOtqTYnlDvDfMJxBsDQQ5uGpFGnXGxEO9NXfRgSqXKv5gPcxU +Z9P9QtuFSwI6QDMMXsyAPvN0ZkSi8I+MqdXqnMnSP1NZ7jsb3AcKcVTzlzRDd4tHbWDS2CwWNn+y +lrORAfBjA4XDrt1/ouvvzsH1BVEF7TQqwJLDVPXQlTNH7ANg4wKx6pJ4pf3dIpQgVryZA593Z0wa +HeCu7CGXwEuKIay6eo/NilrztQOFyvKMCnh1MlSTi57iBIAee8AyJGXOaltJnp4rSJuafk+gjBRk +CQqtumRer+SfwJjAOMvAJbowHD+q/FwGzPcllWw5PQ1Mtk58BahYsRbHUue53ux6xszOt/35J+kV +TV0fKtg1XNvGaGeB3fzWxDed0KMk6TCrgWXjJpmUa64mMGwxpNFMFEfp3dkzxAMzA+YGdONHRuCH +I64i5vJsCwQ7lp/cb0DgEVhhw0EJK29J+Ff0l7I3/eXHIKubVXFF4wS121dsEuUeVHgw5OLVMVUI +qwWJ+7mfh9Wu3meSedPMrQku2TAdcki/10l308DMPcLiKdoMyAzr238GF+xtL10yDqRq+D3SCQeF +LzgWnbtF/PSHRbnlqQ0P2+nJlVQGH+aELekGZMgpbxdB9NKSRdqJ6i7IxHlcn56Dct9hD7+I2Xr8 +686DakBmGplRGV1Z4ALbfceGWHOjZK4z2aYnJJAfUqNADom6mRvPkhAEdbqXb6tG3ieZZpFCMOu5 +fJyYkhQ1Ry/I09HOeti23PBHYpUAh1q/aFqKYNkMUZBYWeMbsP4rhwA167I4vO5zBtGppvTOYGbN +BHF+Nmi4E4wusamoWC3GjryGI36sE0di7tXuGdhSknxsTmeBnFg714kti81NlHxJo/v39U9WAxa4 +kihEFjLFwrRQBwl6wDAgsrf0aO1Gwwo199m/2oldtIqJm3fy+KlfhEk7wesRZDCGCynyyrFGRncj +aHg81aMR7JfbF+TZHJgpJVX0PmLpcSwnAYOJIT3Cu3VcNdd3AOeqLxc9F7pQPMV4zVADhgU/MMyk +iStZ64kjI1bBgcITk8NOwu3a1zN+06vBYFqoU908oesNftPiwj2GL+FP6IG3D1IbNH2DTyf7I/QS +JFnyX5PeExNzE+cED57tFv6OIsQxz926u4Edd2lX1M0+vmuTMkzx+NrTXRXwBifUJm5+5JTamVx6 +tOqAgZ720aJ0JWPL39P0p8+jKyDVQGTgSXrJK4XZz7xY3jeZKSpoLZWjKnTORdWYKWoCIZxpk02/ +rcWGcPZoQBiSUA0XnKSxFRynb9rmWX1JMQtn8IvAPze74qZe3SaN3r9piSf8Ap+AVDYtb/oDF5AX +0cprKt6q+AcA1Mj8suJgICP9tkVXIpGcx32kbvIua6s25XQWmBNAKY/PiYcs2Wv4HoakRJ3A4P77 +vCYghb+sOFgSz7Mvjmh7Sw4OdgPNPeZrqmsoS4l/aX6Or1JeVN65KqDOL3DECOYwZ3XNwDvPp4y2 +/p0CBNlQ1JV3M+k5lQz7jLWQr2zExwXtHcaHRa4mUvRy8yFsuZZsOytcQAXsHlk9n0J4AiRoYBI5 +/o7TKh6DAPB1HzBDd+BEcyoD2H5sgC3DfPb+cWjVlJGcUGQzkiePVgs8vT5ZAS5gdUuknwcsUPYg +DVwdp2PrdAua+K5/xjWGG8shvpzk8fyXzTqU/cNJ72fpkudDFZqGCuGwdI9UsMZcKEQu6tzHjwoz +QGOIFFrEEzM6QC80VJabnU9taH1NG/qD4jHAV3Cs6kXew+3K1UFILSJwwpZm3t2xZGowp0vN54YB +x9/OMEXMi+9gskp6uY0Bh4dTjez5mZi6HvwSXsXU+mDhnuYNgvvm8oAxMwFBnUGCrNvYoqEI3nk0 +w//QCUA0UUFBlWWIV5FWH/pC+tlhL8bQ/NqBPTCJG4v3bvMrApUf+T3/gHO7PjiE7NRQf5HI3QuR +0nyLm3lHVAW+283dmdSJ9Bw0IcMPyxr3OHc8e/T4UEcoIET+Cyy10VBuE+VRITe+ljHcWXwAJZCq +2dQlMTTmKLQaoNutm1fiRHInO/h9blnmMyd/SViSUF+Gn31RBYKaSjwE/i/rU+MCGRN570LVPxl8 +tTrh0wHY9cM3WOa5NUv4xKWz30oEJh20VXZPPhIxJCSCuxFYGjl27auWfnvXlCRaPk8VQHJpZFLK +5LaQGbcN4b77//B+pJDLoOAxm3nrAxNAkwS3DFPrOl0HJKTe33/rM7FAO9bmQjuLuyNKJkRMKG5t +/OvHtwMK3/jwOf5HRkDnUXBJnqcrAeJCw3gAk3rhxteYB+j/SJx2iF5jkuXO58GOndaduAD5skOX +5PN54lXiegfbPeiByF6Ko/Wqdie1EpcTH1fb/+4BU6V6/4iXE4b44YgcFt6VIq9Oobhht2sGwyv0 +zLwPFFz0xzzMEX0ea1cbzEN6TdLdw2twECbtKy+omjO2KAzpyDjejc3f4wkD5mapARLfNt5OG3mA +5Nrgw7ZiJFlzKWjLVHUtPnuzH0UuN724HAHABJYPTY9rMpkJ/WGr4UQ3poK0Y8eYVLCOuSCJJb7r +NeZN99lyc6/OJrNGlTmj/hXVr7QKihXLKWwj+y5fwCjfbgYIXgrNV/Jbto0bELF3znSrO04Ft1L0 +cVLrIYljsbrj37ZyLmtuzIq6mcX+rSfJrBr37qRvZndJATOm9W94uO2jh6/T+65yDLpoS3PWzFdz +SeNlZ4+CIYh04npGagF11yEQ23ZNvtQAEZ8K8C9PkzUEFJkHNmmx9pPmdIH5NcnoGof7ZpfwCfD7 +bKzqt2q1x220LHbg56+2kvjD4T7EdVDlkrzCfBpomfiKREfpCdtJHgBswZkcd4ywri1T9wVhsjWv +80bj8PT1f5G5NwyV2uLLbGKWhCdLW9Fzp6h/qdEpzsNPzdaJvtr35ZcpSMchScKLt7ERBBcscLx4 +TKZiOE1UZuP//xL2OmtE9MY8rL6POV5/Mmmp9JmJlnSRRWcsW7Cx44c+KQ10Fbt1pgbE4f40GRq9 +kKxFAz3zqvIFP3n6zyUUSQZHJInmwirgcIcr20q+Leld2t02nWHvcxRV76JMi++/cjIZcpbG/uby ++FEIXN48XnvWAhUeG1iel3mKUGGQLOXFFRhs6FszL6Sb0YzR9e+zIdTH0Qa+H0MmVy9A1sF5hBuH +SE4ukvNQn7H/osv8y35CvgBzpejUEy/7qFSnND2YHKIqSW42BObIbKMOSSHjBq+0aoiYY42GzDox +Ldn+7g0dnDnWw4zFGJiGMCaWlHjx3InZD+XdE4ZS3V9QdfxMAGVmBGwv2ygkgO9TOCo87q2WrLt6 +ywua8Lj0O944t16+gwqxpuBGRWdb2OYpzVrYSNGHonQ4yvi6t4b41cJ6r/5kLCaWkC1iDPZ90Jf2 +4W+BuAaC2EcOS4Zaq03v8jK9nNNhM94Ey6ulieFOnDPEfXA+wIIeY0qwDHo4d/jUCjTY+PPp7ZWy +QZuZYypzMkR6wULuwLLv/PsyDkJL6m32YvOB+10frEPFiovMBHMcrCIKET9v4O6Yc21wadh+4jeH +Je+2M9Vs4hKNmQWGNildyJKfmrCkzmLu7lBvdB7ECcC6xQthOPmUWwfkBUefs3uFG9zFiv1WNvYj +dj0Aggpvj2Fpx8qOhMCWJf1r/WNdz/vybEH7kJVFsUZNbln3GwNsLF5KOabaVTkb/Y9ej4UrRr1p +4eTjH82anThC/pGQ181oPDigz/B+VvlC/5EU6c/U5UADBh/oqBHEgkzeYyyjiozMQTU7YOVDkDsf +BUTWMJ+K9ZZa4J78WNJ2jIva8wNB4MLNxfCTs8E5inZfNH1XMLhTBF4cdN7Mx9vdoO41elz8hxtN +A9nXZu+lQbkmgom9Ky4Q19XDAfDCDKX+aoYgyavR/820uzEfnG/nKXfMsZCHGY5ZFFRPlJA9Zd+K +D1bUo9aD0qtNM2W7DDMB4XuasQIEJIh/fifwzyA9BEwAQgKMlxD4uk7OoCEwdH2N2X2oZWBrtDEx +/dX9//+yevYYEOnwcqLExWmGI/BXaFawhDXdvu3eRVHF0H3nmt+zSGmxT4jpFOIrEmk0LSXLmBXj +cIDffVCvqFU/0TM23xrygU8SFJ3MrAI+VNKhUpsyI/YuVqbZaSv8ptjl8IB0v8NAgnECbRtnEpNb +boz1Lt4XC0X+W4NGf5cdNEYopDcpwPeqJqf76YXlOXtk/lAFSEIHR9iwkNMcB2BAS94yZDoUMzqd +712IuFpeZV8X/1kj1Zajh5awIjSOYSF3QmoDEiTQIohBm0/H/pXscL8J/d0toDdtVI87JtyMVNg0 +dHM9WPEc4dqNN2Phx+j+2ZIQ3AO7XFUVawlQI2oReZhNuVlsitn8Hwr0HG3JtTFmq5QRvZV3EPrg +bPhxYg2JdPnahjihVftW3nyVPG24hXq/+ho06NsbVBj7KMbusvMf8vRgQ2zacMSMqxd3xp0e4U3d +97qy0OhyYTGx6+kZJgnAow/nTYxp88p8MkD8BhZs+0D5kzgNJisSUs4vM7bZowCEy06uj8Qy8hzA +Ls02HJWAwdAic+LdzQFHI4Vwm0ioFQEFgYQHeofSkfiqK+J3RlcqmutZU8woBUoDnKI9sas+pXYP ++qLw6wDOTOWF1nTrk7RRI4l3sa0IVYOTli0X1UFM9evZErI4bd0Nb8JdmYUv17Nmk7oqD3dsWAQo +Ap0RZbfWVRKSaw1CzLArAobWzWSVXZwaja1iwNbU1LMGKDiKCGcL5/3HzRMjYhoSETNuXOmvPjdy +FoLh/1YnqXCJJSK/Z+CPas04ODwiM2leitjxpJMbBXhdWs1avDpkWSwdwdmdTZ8FdzWz5Nlne9zb +YCg/dUGC3k3g5gPXBRJNZ3aHfRJAkZaYO84kHdRnO2SS8bQQuxzIrdYpWDOTqcPAHo61Q5j4WyAN +zDWXx8trNKI7a3rWWaJABbV1J9cQo4EM9Ce9F4d8NOsiAzSL0eS5LfqV8GRklC52qSIMkAflJrtK +g2PYWJ3MysqK0AsIQMG/kd0a4T3dRY9nGXEFhkm4xy5KTz1dFs/NGwOHSa1ZqwS2f6WQtQKe52e7 +x6rLUZbiG7fUQ3m3covdvA8BLj07iPz107Dlkb1YSvXHNaUmVPMfSUYhb4O6BxRQR+hIygMzkCAY +e4AS+NRczUqzS3t8RI11hJZsdclzuufHn2AsvksBNK9IReW+/sptz/TWRPjejPfnOrb4KWFFKfGX +KrNwZxzPfBKPktATg7uhwnSdTZuBBcJjbteERX0nKrrd/VRHV6feRnXfIuoXtARIx2kmjqD2Ykuf +3t+WCgTIHZhVBbjxAFPHp8DaJ/2V7zerAOigvBKT8CN0UEo9BzyY1r365gMql0vzPZiU/jHpcKyK +QA/V+MXo/VMKRlsHcOQYyFV6Kc8VXcPx/SMwctlhbrMXpFuiiQCYJyDnAaaf4fT5sjNRO/tdfPZV +R5toea91fMSR3piWdqUi6lV4g0NfM0KempWV+O+dEYWTfNvACQXLGU4vjMfZ2fzRooUfzv1SH/7+ +39ZgZLaVJrUiM0xXkEVCmonrIkUTxBrsW+c5ZwCpKliSsr3Jk2S+QDkwZ3S7Jw3SUgQbUVmSaRtz +oFTUhBjXQrf+Xp13UPG6ESRG8dH8YpseJe0JsCqgsF0kmFE8n8Y88WhzH2Xn30jwCJuKuTYQ/5OU +n3rSuoHNNxO3npvu9BX7xI5EKRygT67xmsulm57NycHU8qIPCmrfz3sRGAuXcJ3NaQz/O/MmbE+q +KSzjfyH/KV1UY2EbFG9tgoADiLiPSceiPL28kGTFKS2k5F3VOfcm5/dNtxeBsVcTS2PczLsIJ2gL +HZddd8iCMUmHcVtklsP+DAOcx5KiCCRP/UIfv+/bXI8tJjrmHTukIIWqQg8Ip+PzoaWAGAOj6elk +j5yZe7INa6EYBRFmHOU9srn0qRMnanH+6nslYJxX0ZXaQY4CA9hgMAelJYGV/7MC/akSjGpijEm5 +voGkuHzYtkmN5ekgasV8NBaixHcgH3EEN3oao31yNuuqVlwEXF2+gVzrfTmqR2KTJvxsSYOBmaMu +ajlRloJ/Ahdr+2DVXwJtxH+AI2LinSvbStNLNX3TR4EdIEhZ92913IK0IclA7SX7Sw8dj8LDSkm2 +y++blS7OajA+Lv/yHsGxWJ5CnfmyFTQ0JN82nj3LrIbECC3zMH/iAA8ICjtb59qU5VZBM/ECtRkZ +hF5UVspUc1o/ofSv32lV0O6xmk3ubaP1oTn6wIoRleS4w+lsIuxz0jYmllelJ9YIXLQuj/TVke+r +zKlWM6hIYfko9WwV8hKjTS6rXTZCEyrJMtIEvHnRGK97ZdFQIW4WSKfGoqL1jQ22f481EANRRziM +r8bGO7Zyvn2aFglWoiCjPV7rZ0NAVH0aGwY2z/2L7GrMjAaJPVOwlenocnMTeXw9bC2giG14TavT +SS9zAWfOajJfzKveooN0rki9K4wmUGa/iG+QuOLqfl9QFze1F3n+U2ko4h59WCQv86uGzFVs9vU3 +7UrhInxKNO0HmAvqY04yO2fw3xUxIo0qWYDAiNOchU0yUDvYTOJsiyoe790wMXIh2P1XrAgy3yKm +8TRr75HbzpMw5Ey1sqKFLr9RubYiWf89Y9yId9iLLvbCR+1D/OGYoVhUaDn9zzz9kJQYZckx6I9A +hMS/ntGsWbKwS+A8zhouK7Jxo+QfOReE7Z9cy1Vb4olqto6SEZ2knwp0Mr6sJM06EsD4si894szO +zi4WiMLFNx+4Sn/rrTKB3r2YVK7CGB9GdoPf1CtPM5Mw6az6cLKjJaczjKT6u3En/K1QFQvOzDrb +oaOynVrC1zyhSAyupo8U7vZBv/u3nUiStGo6/QuMG4N48obN6uhuYgCiInRPpvNPTBZAD0XzC6XB +nQw4aJDAJejrOweelcVmNBr6QktAhROgjOhDW/S4zdBgCrxXOubVMXhjvYcTKNcAis5+rrFbiz0h +qlw8BRVd/BlsswJqApnlj46myHHgBOj9cHWYy7YzEb6BWZTfis0QDSvSjNzHmYMTL0DijFgzWGAG +Pyy5zS3A0KuxKO4u6UauiuUKJew/9UCSjWb1UErsvuL7zWCODWwRggT+HcjnoyHJcUqB2YECO4tT +AM4leYPXo+ZQE5A9fLMZ0BsYxmEk5c6FN/H/9XMT1XWf6XRCYAxwVYyMtrmSEvux+4bpbc9cJJ1Z +bfXUHun1rkW4hMLeMOg9ibdR2JuM2RB/OyJ+dv02zMT+ZnYnqCMakhZ06/KPl7ZlFJN3AhBe84LN +ozC6aFDHkSzK+0wRra8k0zjTjzZS3qwCFJVyXWYDDvG1WcCDi5fbpXcRrgTCig3GacMYijH2DgU2 +0Lb5G21EOnpZhJX0vLdMJmIejE21EhByUGRw8G4pO5Fy8mQMdBNecLUM7m7IPzuBQoLDQtJSMyJ6 +SApzMl7Tn0rZJTQtpiLVre4MydztEk4DUeF+0AogpEq5/ssBM+r0I+Wx6LZ6A5gTYvnU77mWbvCi +3BdATE+LkJi1ll9kaWJMnKlQoQfP0pdTUvJArx7XTCz2a3JlO2PhL10E5fUQaY8u1rtoA2/7H7wY +6GqBx2FJMmTH7CFAQZ3aGN9vDEqnEFHlgWEsWdbo9q9kLrst/41fLEeK+yD4w9F0hDvPAhQYqvQN +zHSNpPHtUxKTQdKrCNAVhLVAfg8YeZZQeq6ykM74qHP2dgYRam2f492UC3Dhur3OQNAC18cr+5PQ +ZKMzOedESUOqO7w2LNbwi1NG5DsD8krg7E1mKs+A+eB5Q3VEzLRDErvxbllIJddR7C1iGe+XP+ZE +jJQLScyNSILunmoBsCvKczRsTxs+TtsodeG6g/jSvaXRI51Q+pymWlp4mVR3ccn/IzS3yFbDf28e +LYrWpct7oYt0tz/08vGpZgxKxRjSo4jy//4NNGp4RXJgI5xnAbPxpvS7p0WoqCPMs/x/aBtIWEZd +6L7HQ4Hwp7yNTpYDcEJ7Gegrq3Wy1OmdBx5AhqiMeHUVxgrOzfLKr1XYBGA/Zc/mRsict5FSPBgt ++90+2n6VmXAhJH8d5WiMTORv/UkJdCjuHvQb5AK6B0KJSq98ZQbDcF4ZnP+BC4h5djGJrxy/l7Vu +wG/RearaJuVxoBtWo61U5YOXUlvuIOu7MAzCcChKUtssCst5R/WSw3pzitcmmcDjJjZrLJOj3/D8 +aqvhs4WYthpMFFAbK4bH/pr85ZUI7ax2sov7ae0VsEr1TTB1bmX3wh5nTvw3sTh8gzZ5IqEMSU0u +i4XxSnffJEbwjJ74ROXiHVg9bCg/rc2S8zKhx0j7P/wxCegFVG0gyvPnQxPryN28aMtmYIPzwjDW +zt4/8aYFMBLcIrlrz/fFJeBF6vvnif8LPEQCsFEdB+ItjBYBDf2EQFln31bSW8HD+pE7sZJF0cLT +NA8oW4rvQAd5J8NAvd7yRA+h5fTw5cRyM34X4oxZObrTizT3I6EmpysrIK085jCiOr5rgQtLxrHX +Zb8BwICbKL25eTzOhp4xLTdhdh1Y+bDQolkZuTGXkxW6xlzOsfllM6anv+wr9oP3oh74TXjicmsO +AzDDrN9ePfa/X/A6EJU0rlUH932XuTH7QIWToZFzr+IC3ILSpWZihy98lascNosFnyv+hRKedRwy +2spuCUHGGdMWRVNT7mNwelpyHdmHHVZfHCyCGbZd96EZG4nTsXGzCxLz4tTn9ygvC3Pyl2wIqfVS +wQKwAQu2P/LW7pviulSA/02zZMxKHXp57WIm86wgkrE0H127eEy0vOYhyej6EAxN9WNBYMw5cpwA +wn88bPcyBqMFXwyh1rTsibDOV4rjYmh0mJyrE/IHrJpKWgNe8mCzhLVNk5aP0cjearrKT+r+cFBk +wVNhpkFAq+hgoSanRgaYxZtYSYnj6fYm77UZbmPSJpF5Nztfrm32Eoolr8snydgTr/f0A+PA80yj +YiHQDufHcJPC563OhOrR9x0K0lfXSXrWXx/68UWBcjQ/yGRcNmauvZ7SzFYr8SsLbjSM8boI9Vkz +xUgNvVr7ZAnofNLdCT6IxVGkiMPtLJhdE0OkL3RqOWmu9YZuYtfIalbF7GH0kEe8IIS8/6ZObFVs +JFzvIeiOgsPJVg2sCGxn8tQgLiS4tm4aGvF1eAVVzEK536xd8wI3amU6EDVCN9LJAwW1VGkEdo2Z +tPA0Dfm83tGCf+pldAk7IPn/fEPAuUK9eoOVGDksUDzVZi3ouoU6CNQfAncAPV3lJUfJ6DDNE9Pi +FkCom3128mDTVBDLGpezlXhj6ae6o/n8Zx7Tazcpcgo2AOP+UM6nZ9ePWr+IZIdy5oxpxFHUDb9U +S6T7tYisa1jo/ffYnEN43czg7nOFHfhL0eIUAXwDkwSFMJr+0/xxeQxDe2p/3p1BlGj8JVsjR4yG +Sp87Tmz/DyTUMCWPlSnboYmbG51ulzF25/gY2rQ6PeZLR3IYYD3BXKL4JbDWuxTQNB8Iqc4OdQvF +gU3QzKgETpDJAdKRpCDtRaZdC0V93/V2u0/zJiLy9Xuu8jw/aS2ls3N/P3Yf+/ta48P/O0U3Ewsw +sqy0PPvF03WoEUAbC2dOV9VPZnv851lz+YBEecl7mAHCWJ3iB96zuJMrLynfuh1xe0IwDuNQuKdu +pGiQ5/UDrTOHifewGWdxkK/gonBvQXZq9LBjzBOOUJYceK/mNFF4e8pVKZhWkMjys4B6PVxi9d7c +cB0r/jHIBUPePvOGfDOIjiiyhePUQWKS66ylb5WCd3CxLLP8hAb9B1X8dg02cc0XirFReQicckxT +ivh5ZeOkEyanxABx8yULowSwlQbEdBv3VMNvrABhshWC/XkI9PmFgA7fFS0uG4iebgHpDCQy0D27 +TjDAvi6bbQHbyLzJf/NcOq53wZd8a0h52A6dWo1uV0rZRG4TeP6ph0WNbetJmNNn9iVzX3YOHGm4 +2e4t8N1pZQ15y8AVYXAGwSJOsYJYe8rZEq4GMRu/1zKk1eDvqgvGQyVTHbPvKqk+e2q4Kvv3mrJk +vbWqzaOXAvpyL0lATQyVLyEPMNHueHSyDStVY+7vDPlxe4brISTm8OD2Y92gYeLL+w/8u4sguE0i +5kV6KmAO82XcKV+hRlIfw/7MRaOmCtHwR2IETKpcKPXvov5IzF294mGaRDxQ7WskJJo52BoGDrXa +MpTWPslGUT+RwfIOZWd6N/kB4eaRN9obeFGQwstBVtYvhT4NUzMCeSp2ROEicNdzoqmu/Kzu3j/g +bHWRypgGSXUpVlD+ygFa5zqpGcXGI3HOGH2QKg7ISZfLA0qpOI+OTpf66RKpWsThpX6ftxq+AEv9 +FnB8S8/yBgpb+HRGz4Xz1+KgrF38a4mXYf+n4JPhuab3UC1I7uLJJIveSAX1um0vQUGF1+JTRxQP +w74yv9VDcwzTPyAQb72hlu9vjP8xZVc+nSQCPRpyz5xrGeC9/pWD3ZU56aa6Rzr2EkWIcI4ih1eq +pd+4/5H2485oDc5/o5K4XqB/B0kyN5JLnqayQ1Qhf11F4h4943bGI5PLUwR78ITwbqxPlGeHQwJX +5j5266kAz2U0gbqIbGQjehhy8hK+UaCu33AWqNUf9UhofFO8rR+JS7icz+LmSN06+BNPRPkAlRML +D155qboI/Lg1DEOkeQssqqbVFkjUix08bz8UIym9VDKyWuK7HWHlpwfgEUdqYZnAlWktpEa25G3f +FyOylfKpE4yWByTXQCjjFEDYK3fr9ZdM/g6ax2yUDqok7uIuh7KZAlS2WTGLoW5Dceh/OlGZiNpO +73hQXlYkVNoFGP9865Z7eRn4DjQjvHeTAUF830dsOk8z/eBz/OumbaeWNeG8qhDqiiwJV0ZFjKIB +yHlZvtsNNU/I5XhCgImO0+z16qEgxnQSaX1yIPIqllhO5tIK2oqNOus6M5L4JawuApaoXFtGzTKC +AwKzKgCo7w1UVSKCbW5gFz06lyl57LdT56MopqDBYvdot3VFW+dNo+lu9pK6tFiZWJqauMKa1Woh +5p9i5yTpV780R/XcVVcNcxZDBjVOPBmZ05iyTrKlNJXW3vwYrk+2IwQCoMhQRuUGu6yKkJA3js78 +or6COyxU/GBzmBAlCUcpGx2FYJPABgavQ+QQU+BJIH5oCR1iJ1QXjIi4dtCaMQbHz/Pd9Yn/rRPh +NKg3j6D8KcYHgIQPyx+nw/0pvf8GfFZYw1uszVHSGpS6ZpFQDyAjC3c5z7aAGUYmv9FYcWNjGGC4 +Nl65H4hQ2auDWdQh42FUln/VEceg4c3PqRiE9Ll5vzb7yz41b4UDdxajhm3L1BtI+RGksAVcy/EV +NIjZ5ET9VgGcyjAETV9FLiq+3hZzX4Hsbk7QvG7l4QZ2rbaYRTmjmhEyUXBqcjjWFWuYWtei5+gV +jDrnjpzwW9BTMA6tHvwa1TBl7a5lvZgu/znbWvDeBJUYf1bMYkHn4hEacuHlM3dS7fP2fVTPRkDf +NfDKqh+jtUpbE8iYusTRN0yyFyV1TlZnRvfXSM9krJqX1dNWycUGoMp6UgeXtVZG5AsN7TGeG+lN +LWwxAs2Vv3+diSIQzZ3Q3LyiteyEhQvNKGPKe+shg0apCJJ7JKCFvhnGj10HDgNjCIzgesypOTsz +0tKOorJw4iiHKj2MEbbA2gS8vEytqejblmbR5H9+yD3+9AtDui154G5O0K/OMdLV+9EgIe6VBAVH +Cb3nD2TrK2C1esWnDZOOlymCIbWm8+9iPz5wc3zZyj7JzI1N1xCTiOG7zaB5MrtKVLKJuRPOuhq6 +BOILhB6Ib7NivNdCaxvC4kmDyAVp47LI10qiNteZmXFVCxTxdV7MEiAmsT8thu0tDMjvo82pTJAy +1j54iUKEPJXCmUpM4LwBXjP8hsFTNVreaZQ3jJ3nPMU9InQVltTe52ysuy4wyYj/C/YM/6KGSiKf +OsYYV4ASRwdRUxfzQD5BI5/ZoK5BS1UjZHnd2taC5yulaDM8YFg0Gor5Z/8t2DKdeLkj39ZqXsNN +knSrubRYayzOmJEWm0/sDqYMAbgeoxeK7KV69XY1OlC5qQbNInhet2aCvI/2+qSt4OOmMRaLG1CC +jq06LuJhma6JQGMAi6phSAidhHG+YbVsdNKgon7C4WfMUdxIMsvvyo9ronEyJV5gWr92hgGWLvFV +ToVSWbzF0EROQC4OLUq2/DAV1xrN9+1YdmKNDw0a0PkjbdkpUP7AVxXOs42X43rE3HmBuUuu8MKs +vPQYt21APCl882Wtx8aIgHPWIAPNp7Iqa5CYMjYJf3Ji73xqc0M36UHe7aGA7A/7DdWAz1NRlnps ++YQ11ea0tWVVFu5czr11nTAciWviyCYIjlDmCDzr6jLL9DC5b2gJnxaZFYDqz1zMjDc1/aUtO2Iz +jaAmtljRPqT6YfnL4h9eu1b4zspBKga9gGxtbthn6l6SuJdKoWoTytKwqfgVOlIjJ1z64fPeHo1c +qsRDHZrrDjAOn7tbDKlZr90ohPKlEeXpbDZmQu9cTrrhn2+59p8Tn8U8gsyE0kqMcmAS4ViheckL +BSosZsg75SZLO1dUFfJEztbVmk3du70dnBOVLMemVAoy0DFqLXVzCtccKok+5zF2vzayBD0i/umf +D4H9rBZYfsuBLdEAIkNgdMgRcqnJfn6ivVXAFQNeDpYxefRZDZmYWfcKLIs0RkaD/XUKkeY1l+Hf +ni20hkqbu40c1jvWIP8dRGnrfOq3v1i4fkSV6Dk0knGiltvZlhV03mUsU3tij1V6scpm3c72Y+jj +JXHxUu2A7t0tHZenGEiuJtRoRGqSssQvFcgvpzD/qr5tjwtRe4T5ephjbPsgDa7/+UQZAlNOwDYV +EGNJBmKXXXa6l6ws8YjTgVPJbKEX7L8VVz0qD4pIyc9Hp6WKwvSqjMbJFULr6fdEvj4+sTUMovAX +YnrC4GSPpcG+Nm2dEdIw0mCM/vHXLrG5OKKpMctQjQHgvQg/6C4dp7M16GW55dHgRWaq6YPYWbfv +bx3DyHWqjjWIqz1tV5/e6I+N65Uerj6vnVI6/4rQA8hnI/ZdFkIKxxEHB9NNYIJF0ZmsyMM/NCaX +V6nu8nOKD++ZHcCccWsYYWDZd5VhnuQLmRIeElbBIco+EYJpCHItTlyq/ZNr68AyQcRxOB8CCQoZ +wYan4Gwb+9ChnYZbiJIRgzfIg7qloOd/dKA9AwnKl6/0TOfmdmFa44k7w2NSJuu99GfXPt/86z6d +Z0Ng5oDP6qjPEjFFoJNi9Gta7exZM08iym3Y39Nqjegd2JxxNWGkqGCo69jQQ0VKjIbzWiKn2ffZ +S9IUfo3JZeky9eHrPzcMFxvtFhsN9LdKt3wSn0ovgMOlxLTdMZy1ldla01UWmSDRz724+WY2K6BQ +bNku+dUn1yGcHlKlspFQeDXxPEaqMcfTp94tXsxKsiyMa3sFPuXfwTYgwHp8seS+iCMBGADY8/mm +shOBRO0T4LOyfKumCwLJ1SLag0q3mvdfxE6/HVjAZtSrl9a+SBRZEcswwGXVsliDtEIMU1zhThJy +7cHOhemuXjvyOoQE3Jthb/+1CAH3Rote9ywNHAD8PTAhhP2PfpD3iycpV3LfKoQemuo3B8Lh7K8T +v91Ddhg7rOoC2iU/4oa+ylx/G6hOM1AViNL3lzk0/7NfmbO7fgGYg7dK0OTmGzvA+IgyS7YTKtIG +Lv/juoB/o+HpPaylexoG6RZmKGqpu13QF4sPFSALp9aYu2dPP5VsowGJvE5cg8fPqHaoOIXsqdbe +WcGbUnamgh5JG9sle0kVXzOT6/J5ovBfmu6j1E0QTX9YtDE3amECGTLjK137hj5TGP58m0MVNzkY +jPRfEFgNVHrYL29tX1JQYhdruLHaS301gkriUiSLUfL7sU96cza4zQRqmd2Lzen2Af/bG5bATdcE +HiTBHNwmV3CKiGpCmjJ2KkVa7a6S4I+fALaT7J/aNubIenNA1vYzLLhlHysBWh/mnBGuGzNUPcoM +f30iKNhuDfiU+4GuihQNrCdJH43VNpBx/3wHpfT1LOfS+kiQdbBiepmW1DaefdR7lOI+X+U+f6Ds +RK7KOIct+yOg0oilGCT5459bLS4ho+ib8wNEWuw0KvorECLHvx//FIG1omSb7fdx/m76kqssN74o +B45Cy7fKJhYNF50QS1R9pxeNb1Ifcj1Fbx5dGMVAj+MbLnlb1jgPTCog271fPCIDKyLgFjDAYZos +quIG+DlV3YRHZrTlcuxWhXsqGDCBdt2blDiaj17IqoVSjS0Z6+/GbSi3estrlTy2Jh+tSm9eLvyq +B7ewgB8MQPAJdlp/9a31p6yuPDN+XAvGpZYNqOor7SbN+dYC/iClUSo5dRUUm+G2it3ZyCUTEfgq +OQe3fT1zz7AJWqOx+YRGXnh3Ot3TNziAnvtjXBO9BI7hNhT7UQVdqfS06nYCwwmhC/Rh5pBt6Rju +uGwspfbXFaD1EHuuP8TVQ67nvQPpqrqM+uTxawa2UyAAUW80nnn36zW4EYPDBBU/+2Ltgw6IfYcL +NDj+xoQwHwFvXJMX6n+hMmUnuhwusetPlPfQAl3x3bAmx1DsBZWsJ2kKgocGpEagpRscpvzfCXXR +SiYmn8b6Z8muV/1iVtO6H5wllwUQMzkR6YIAtY8dWvMVATZm6HgVl8w6E8vIvfApVfG/T4+56sEN +VoB9IeUu2Zw0F6tGdPnqBP2qZ84bNZ2LR/9n42y1XCmLRirD3Ai/1DCIQ1iyxGO0aVJjroQTIaAk +GgNA11DHXRTstwtx0xewN3aDcu0671yViYJDOZdlBNpktoqzGrQdBtTA6fI0chOi1VOCMvtvcab9 +9GaEmIVeigX7n9nZkOQiiAbeu33DCUZMpErHDL564ogf40qtI+wOyntoQvtxs2BepkxGc9BQd6mn +FH1FsfuuVR15rWUc2LHDXqC2ppKQSS12xy0qx50E97Bq/HYonirUNs3K828LECjBUJcC5oNwbWmL ++Iv3SwU25l1+Kd2BKHg4ZQMMpmazpNBsUf4CPhJ4JLy40WoO+Cxs7m1DPWXBv8indToLuD8+56Vd +M3GLIh5JPnYR3hxPJlDuBKTY2Zw8r3bY/c92zBmNCuoojC6tOWmAg5FOEWceAJ6cJGyHJT6Jh8Wi +WsmugI9TEMqMDsc193Gj0EnKrCEpHc3626xz29u213wsf+wo75QA4XvFCwsvUlBMeq4Sa7TYm4n4 +jijo8mQiWUA3xxZGRP7jv+02UTLMBIXnvAh+6kks2KhSveSfkB29Q2t0uyc5P81dwvYNEVdhdRT/ +kVZCXsyOFbAni7oWZMo1MU70qpZUzBvWSjRfGWz/dNvH2hu5qJSv5eMO6qSFbkCRp0PzWbhgsRJE +G6gZWiNlgPqjR7QDcHL7HtdA5E9PUchTD+winYHh3Lq9JwN6svB2eLss/u6G4ErcNrbgN7OBvx9N +gFBOU0bAEGClAjb874IqvOkggzrlyydzqsrgyHJFVAIhBoY5JUaeI2y2bzPKJiyvSwPrN/vOw668 +MYHyNlHI+P94iAoM58Yn6lV0fLBo6ZB+jfuRZtbSMH5oGgfg1/teyHzKnjweI8ke9vwltmBSbw2T +Lgsv8QEC4/bJCcOpWcJUEhGiIBFgvbtmC/DMCFtdBe4mvl8dBs/sZ6s+L+vsvFp1xy7I5gVTN/k+ +X0LQqn7A+NTRst5UQ6RbHyPvEXOk2phlgWLH35QnU2BXd3xhZVZ6vWPgZruyb7aiZbLpDRKQi93E +A2Hzv5/I/NpWza+FsCQ0sMYzMUy4rKuCIRsV06yo99eERV4L+Vf0U8fqbfsfI1qLYYc3Le0cJc7I +sU706BnuMslp6ciEqcGCxajy2f27UrW+2tSxOXfrJQfE3mEHKJa61cmlLY18TOUTDaWrfgWQ59Hw +eNq2eAP7TimBfxF8rNnZUH+vWPdlI8Ls4LYxmnQkHDWvJ7KGThvs7fFFOqQzZOR5KfBM2lzLz5g2 +fGK2M5IbO/ZCk3SCk7y9EjAwD0TmBPPAb3Ay7xxLL5+8TtKlgKH69TQCCrDLoT5t4UjpSc+lR/vT +XdSUlhudotyFzGiHr+zymUxJSFeaWXqv2PH507+SC/fgg68Qvl5OmMMznSRh90n/JHNlO/jJbsCz +gdy2ED3RmQtdAjOVVSkukiTJPiUSr9rHo3iVZ38fOhoESyohyjHE21iHmotyWlOUVdrXznpxI5Qy +VrxhAqMnA7Cl2pFIST+/W/Zj+VwhZ/BMorpRDsqI416Ptywp49vdzZIJ9o0i3rMrW92QIb/LRBAA +Om9fUAehIWN/gNrMq4j5JvmUmy5D/QRa6S5wPvEnn5ukh9BPOoyc5Q/Mt5brjs4ycYwlZmzI83Ho +UMYNTWolwfYWkDMXhi+Qz72UREtmX8PPtgw0ScDFJx/BsmazDH6En1fkLLGMh4QasePtpA2wUMBC +XAuWE4zsS5kBG4obxjcfQd5MLE2RnOqGC7TLsn2e1VLM9c4TVWMyUxrEivzFCdOaGrMvXhMY7H6z +Y2sAWT9upp1fnoV/H/FHYgkXssTdxEPGvRw6sX/k+4Q4uEV4im9qmxWl5YlVCLur9nwFojwh6LhS +1HY95uaLe3ymPtkWYUClYAIrptUi3UJOis3geBi3vEKkAVEAbW1NA5l/d2/a8SGa+iDGLVL4luUM +5U5ElSJC1dm5210xhvB2nJ0tEwc5nOtJ6vLvDEoK6H6BtfU1aigkn911GbgH5jqRlNAdY+vtnGCt +Z1UaQWIo2L1IFDAFloFyyzrYfc/dF5kn4csvkXc1oTOklM/zoAv0SF0BjLhO +`protect end_protected diff --git a/src/bd/Arty_Z7_20/ipshared/d2d3/src/ChannelBond.vhd b/src/bd/Arty_Z7_20/ipshared/d2d3/src/ChannelBond.vhd new file mode 100644 index 0000000..091545b --- /dev/null +++ b/src/bd/Arty_Z7_20/ipshared/d2d3/src/ChannelBond.vhd @@ -0,0 +1,176 @@ +------------------------------------------------------------------------------- +-- +-- File: ChannelBond.vhd +-- Author: Elod Gyorgy +-- Original Project: HDMI input on 7-series Xilinx FPGA +-- Date: 8 October 2014 +-- +------------------------------------------------------------------------------- +-- (c) 2014 Copyright Digilent Incorporated +-- All Rights Reserved +-- +-- This program is free software; distributed under the terms of BSD 3-clause +-- license ("Revised BSD License", "New BSD License", or "Modified BSD License") +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names +-- of its contributors may be used to endorse or promote products derived +-- from this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +------------------------------------------------------------------------------- +-- +-- Purpose: +-- This module de-skews data channels relative to each other. TMDS specs +-- allow 0.2 Tcharacter + 1.78ns skew between channels. To re-align the +-- channels all are buffered in FIFOs until a special marker (the beginning +-- of a blanking period) is found on all the channels. +-- +------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use work.DVI_Constants.ALL; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ChannelBond is + Port ( + PixelClk : in std_logic; + pDataInRaw : in std_logic_vector(9 downto 0); + pMeVld : in std_logic; + pOtherChVld : in std_logic_vector(1 downto 0); + pOtherChRdy : in std_logic_vector(1 downto 0); + + pDataInBnd : out std_logic_vector(9 downto 0); + pMeRdy : out std_logic + ); +end ChannelBond; + +architecture Behavioral of ChannelBond is +constant kFIFO_Depth : natural := 32; +type FIFO_t is array (0 to kFIFO_Depth-1) of std_logic_vector(9 downto 0); +signal pFIFO : FIFO_t; +signal pDataFIFO : std_logic_vector(9 downto 0); +signal pRdA, pWrA : natural range 0 to kFIFO_Depth-1; +signal pRdEn : std_logic; +signal pAllVld, pAllVld_q, pMeRdy_int: std_logic; +signal pBlnkBgnFlag, pTokenFlag, pTokenFlag_q, pAllVldBgnFlag : std_logic; +begin + +pAllVld <= pMeVld and pOtherChVld(0) and pOtherChVld(1); +pDataInBnd <= pDataFIFO; -- raw data with skew removed +pMeRdy <= pMeRdy_int; -- data is de-skewed and valid + +-- The process below should result in a dual-port distributed RAM with registered output +FIFO: process (PixelClk) +begin + if Rising_Edge(PixelClk) then + if (pAllVld = '1') then -- begin writing in FIFO as soon as all the channels have valid data + pFIFO(pWrA) <= pDataInRaw; + end if; + pDataFIFO <= pFIFO(pRdA); -- register FIFO output + end if; +end process FIFO; + +-- FIFO address counters +FIFO_WrA: process (PixelClk) +begin + if Rising_Edge(PixelClk) then + if (pAllVld = '1') then + pWrA <= pWrA + 1; + else -- when invalid data, go back to the beginning + pWrA <= 0; + end if; + end if; +end process FIFO_WrA; + +FIFO_RdA: process (PixelClk) +begin + if Rising_Edge(PixelClk) then + if (pAllVld = '0') then + pRdA <= 0; + elsif (pRdEn = '1') then + pRdA <= pRdA + 1; + end if; + end if; +end process FIFO_RdA; + +DataValidFlag: process(PixelClk) +begin + if Rising_Edge(PixelClk) then + pAllVld_q <= pAllVld; + pAllVldBgnFlag <= not pAllVld_q and pAllVld; -- this flag used below delays enabling read, thus making sure data is written first before being read + end if; +end process DataValidFlag; + +------------------------------------------------------------------------------- +-- Channel bonding is done here: +-- 1 When all the channels have valid data (ie. alignment lock), FIFO is flow-through +-- 2 When marker is found on this channel, FIFO read is paused, thus holding data +-- 3 When all channels report the marker, FIFO read begins again, thus syncing markers +------------------------------------------------------------------------------- +FIFO_RdEn: process(PixelClk) +begin + if Rising_Edge(PixelClk) then + if (pAllVld = '0') then + pRdEn <= '0'; + elsif (pAllVldBgnFlag = '1' or (pMeRdy_int = '1' and pOtherChRdy = "11")) then + pRdEn <= '1'; + elsif (pBlnkBgnFlag = '1' and not (pMeRdy_int = '1' and pOtherChRdy = "11")) then + pRdEn <= '0'; + end if; + end if; +end process FIFO_RdEn; + +-- Detect blanking period begin +TokenDetect: process(PixelClk) +begin + if Rising_Edge(PixelClk) then + if (pRdEn = '0' or pDataFIFO = kCtlTkn0 or pDataFIFO = kCtlTkn1 or pDataFIFO = kCtlTkn2 or pDataFIFO = kCtlTkn3) then + pTokenFlag <= '1'; --token flag activates on invalid data, which avoids a BlnkBgn pulse if the valid signal goes up in the middle of a blanking period + else + pTokenFlag <= '0'; + end if; + pTokenFlag_q <= pTokenFlag; + pBlnkBgnFlag <= not pTokenFlag_q and pTokenFlag; + end if; +end process TokenDetect; + +-- Ready signal when marker is received +IAmReady: process(PixelClk) +begin + if Rising_Edge(PixelClk) then + if (pAllVld = '0') then -- if not all channels are valid, we are not ready either + pMeRdy_int <= '0'; + elsif (pBlnkBgnFlag = '1') then + pMeRdy_int <= '1'; + end if; + end if; +end process IAmReady; + +end Behavioral; diff --git a/src/bd/Arty_Z7_20/ipshared/d2d3/src/DVI_Constants.vhd b/src/bd/Arty_Z7_20/ipshared/d2d3/src/DVI_Constants.vhd new file mode 100644 index 0000000..83a602e --- /dev/null +++ b/src/bd/Arty_Z7_20/ipshared/d2d3/src/DVI_Constants.vhd @@ -0,0 +1,69 @@ +------------------------------------------------------------------------------- +-- +-- File: DVI_Constants.vhd +-- Author: Elod Gyorgy +-- Original Project: HDMI input on 7-series Xilinx FPGA +-- Date: 8 October 2014 +-- +------------------------------------------------------------------------------- +-- (c) 2014 Copyright Digilent Incorporated +-- All Rights Reserved +-- +-- This program is free software; distributed under the terms of BSD 3-clause +-- license ("Revised BSD License", "New BSD License", or "Modified BSD License") +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names +-- of its contributors may be used to endorse or promote products derived +-- from this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +------------------------------------------------------------------------------- +-- +-- Purpose: +-- This package defines constants/parameters taken from the DVI specs. +-- +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +package DVI_Constants is + -- DVI Control Tokens + constant kCtlTkn0 : std_logic_vector(9 downto 0) := "1101010100"; + constant kCtlTkn1 : std_logic_vector(9 downto 0) := "0010101011"; + constant kCtlTkn2 : std_logic_vector(9 downto 0) := "0101010100"; + constant kCtlTkn3 : std_logic_vector(9 downto 0) := "1010101011"; + + constant kMinTknCntForBlank : natural := 128; --tB + constant kBlankTimeoutMs : natural := 50; +end DVI_Constants; + +package body DVI_Constants is +end DVI_Constants; diff --git a/src/bd/Arty_Z7_20/ipshared/d2d3/src/EEPROM_8b.vhd b/src/bd/Arty_Z7_20/ipshared/d2d3/src/EEPROM_8b.vhd new file mode 100644 index 0000000..53787d5 --- /dev/null +++ b/src/bd/Arty_Z7_20/ipshared/d2d3/src/EEPROM_8b.vhd @@ -0,0 +1,237 @@ +------------------------------------------------------------------------------- +-- +-- File: EEPROM_8b.vhd +-- Author: Elod Gyorgy +-- Original Project: HDMI input on 7-series Xilinx FPGA +-- Date: 15 October 2014 +-- +------------------------------------------------------------------------------- +-- (c) 2014 Copyright Digilent Incorporated +-- All Rights Reserved +-- +-- This program is free software; distributed under the terms of BSD 3-clause +-- license ("Revised BSD License", "New BSD License", or "Modified BSD License") +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names +-- of its contributors may be used to endorse or promote products derived +-- from this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +------------------------------------------------------------------------------- +-- +-- Purpose: +-- This module emulates a generic I2C EEPROM. It is byte-addressable, with +-- a customizable address width (and thus capacity). It can be made writable +-- from I2C or not, in which case all writes are ignored. +-- Providing a file name accessible by the synthesizer will initialize the +-- EEPROM with the default values from the file. +-- An example use case for this module would be a DDC EEPROM, storing EDID +-- (Extended display identification data). The I2C bus bus is compatible +-- with both standard and fast mode. +-- +------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; +use std.textio.all; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity EEPROM_8b is + Generic ( + kSampleClkFreqInMHz : natural := 100; + kSlaveAddress : std_logic_vector(7 downto 1) := "1010000"; + kAddrBits : natural range 1 to 8 := 8; -- 2**kAddrBits byte EEPROM capacity + kWritable : boolean := true; -- is it writable from I2C? + kInitFileName : string := ""); -- name of file containing init values, leave empty to init with zero + Port ( + SampleClk : in STD_LOGIC; --at least fSCL*10 + sRst : in std_logic; + -- two-wire interface + aSDA_I : in STD_LOGIC; + aSDA_O : out STD_LOGIC; + aSDA_T : out STD_LOGIC; + aSCL_I : in STD_LOGIC; + aSCL_O : out STD_LOGIC; + aSCL_T : out STD_LOGIC); +end EEPROM_8b; + +architecture Behavioral of EEPROM_8b is +constant kRAM_Width : integer := 8; +type eeprom_t is array (0 to 2**kAddrBits - 1) of std_logic_vector(kRAM_Width-1 downto 0); + +impure function InitRamFromFile (ramfilename : in string) return eeprom_t is +file ramfile : text is in ramfilename; +variable ramfileline : line; +variable ram_name : eeprom_t; +variable bitvec : bit_vector(kRAM_Width-1 downto 0); +variable good : boolean; +begin + assert good report "Reading EDID data from file " & ramfilename & "." severity NOTE; + for i in eeprom_t'range loop + readline (ramfile, ramfileline); + read (ramfileline, bitvec, good); + assert good report "Failed to parse EEPROM_8b init file " & ramfilename & "at line " & integer'image(i+1) & "." severity FAILURE; + ram_name(i) := to_stdlogicvector(bitvec); + end loop; + return ram_name; +end function; + +impure function init_from_file_or_zeroes(ramfile : string) return eeprom_t is +begin + if ramfile = "" then + return (others => (others => '0')); + else + return InitRamFromFile(ramfile); + end if; +end; + +signal eeprom : eeprom_t := init_from_file_or_zeroes(kInitFileName); +signal aEeprom_out : std_logic_vector(kRAM_Width-1 downto 0); +signal sAddr : natural range 0 to 2**kAddrBits - 1; + +type state_type is (stIdle, stRead, stWrite, stRegAddress); +signal sState, sNstate : state_type; + +signal sI2C_DataIn, sI2C_DataOut : std_logic_vector(7 downto 0); +signal sI2C_Stb, sI2C_Done, sI2C_End, sI2C_RdWrn, sWe : std_logic; +begin + +-- Instantiate the I2C Slave Transmitter +I2C_SlaveController: entity work.TWI_SlaveCtl + generic map ( + SLAVE_ADDRESS => kSlaveAddress & '0', + kSampleClkFreqInMHz => kSampleClkFreqInMHz) + port map ( + D_I => sI2C_DataOut, + D_O => sI2C_DataIn, + RD_WRN_O => sI2C_RdWrn, + END_O => sI2C_End, + DONE_O => sI2C_Done, + STB_I => sI2C_Stb, + SampleClk => SampleClk, + SRST => sRst, + --two-wire interface + SDA_I => aSDA_I, + SDA_O => aSDA_O, + SDA_T => aSDA_T, + SCL_I => aSCL_I, + SCL_O => aSCL_O, + SCL_T => aSCL_T); + +-- RAM +Writable: if kWritable generate + EEPROM_RAM: process (SampleClk) + begin + if Rising_Edge(SampleClk) then + if (sWe = '1') then + eeprom(sAddr) <= sI2C_DataIn; + end if; + end if; + end process EEPROM_RAM; +end generate Writable; + +-- ROM/RAM sync output +RegisteredOutput: process (SampleClk) +begin + if Rising_Edge(SampleClk) then + sI2C_DataOut <= eeprom(sAddr); + end if; +end process RegisteredOutput; + +RegisterAddress: process (SampleClk) +begin + if Rising_Edge(SampleClk) then + if (sI2C_Done = '1') then + if (sState = stRegAddress) then + sAddr <= to_integer(resize(unsigned(sI2C_DataIn), kAddrBits)); + elsif (sState = stRead) then + sAddr <= sAddr + 1; + end if; + end if; + end if; +end process RegisterAddress; + +--Insert the following in the architecture after the begin keyword +SyncProc: process (SampleClk) +begin + if Rising_Edge(SampleClk) then + if (sRst = '1') then + sState <= stIdle; + else + sState <= sNstate; + end if; + end if; +end process SyncProc; + +--MOORE State-Machine - Outputs based on state only +sI2C_Stb <= '1' when (sState = stRegAddress or sState = stRead or sState = stWrite) else '0'; +sWe <= '1' when (sState = stWrite) else '0'; + +NextStateDecode: process (sState, sI2C_Done, sI2C_End, sI2C_RdWrn) +begin + --declare default state for next_state to avoid latches + sNstate <= sState; + case (sState) is + when stIdle => + if (sI2C_Done = '1') then + if (sI2C_RdWrn = '1') then + sNstate <= stRead; + else + sNstate <= stRegAddress; + end if; + end if; + + when stRegAddress => + if (sI2C_End = '1') then + sNstate <= stIdle; + elsif (sI2C_Done = '1') then + sNstate <= stWrite; + end if; + + when stWrite => + if (sI2C_End = '1') then + sNstate <= stIdle; + elsif (sI2C_Done = '1') then + sNstate <= stWrite; + end if; + + when stRead => + if (sI2C_End = '1') then + sNstate <= stIdle; + elsif (sI2C_Done = '1') then + sNstate <= stRead; + end if; + + when others => + sNstate <= stIdle; + end case; +end process NextStateDecode; + +end Behavioral; diff --git a/src/bd/Arty_Z7_20/ipshared/d2d3/src/GlitchFilter.vhd b/src/bd/Arty_Z7_20/ipshared/d2d3/src/GlitchFilter.vhd new file mode 100644 index 0000000..ea09a9d --- /dev/null +++ b/src/bd/Arty_Z7_20/ipshared/d2d3/src/GlitchFilter.vhd @@ -0,0 +1,101 @@ +------------------------------------------------------------------------------- +-- +-- File: GlitchFilter.vhd +-- Author: Elod Gyorgy +-- Original Project: HDMI input on 7-series Xilinx FPGA +-- Date: 22 October 2014 +-- +------------------------------------------------------------------------------- +-- (c) 2014 Copyright Digilent Incorporated +-- All Rights Reserved +-- +-- This program is free software; distributed under the terms of BSD 3-clause +-- license ("Revised BSD License", "New BSD License", or "Modified BSD License") +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names +-- of its contributors may be used to endorse or promote products derived +-- from this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +------------------------------------------------------------------------------- +-- +-- Purpose: +-- This module filters any pulses on sIn lasting less than the number of +-- periods specified in kNoOfPeriodsToFilter. The output sOut will be +-- delayed by kNoOfPeriodsToFilter cycles, but glitch-free. +-- +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity GlitchFilter is + Generic ( + kNoOfPeriodsToFilter : natural); + Port ( + SampleClk : in STD_LOGIC; + sIn : in STD_LOGIC; + sOut : out STD_LOGIC; + sRst : in STD_LOGIC); +end GlitchFilter; + +architecture Behavioral of GlitchFilter is +signal cntPeriods : natural range 0 to kNoOfPeriodsToFilter - 1 := kNoOfPeriodsToFilter - 1; +signal sIn_q : std_logic; +begin + +Bypass: if kNoOfPeriodsToFilter = 0 generate + sOut <= sIn; +end generate Bypass; + +Filter: if kNoOfPeriodsToFilter > 0 generate + process (SampleClk) + begin + if Rising_Edge(SampleClk) then + sIn_q <= sIn; + if (cntPeriods = 0) then + sOut <= sIn_q; + end if; + end if; + end process; + + PeriodCounter: process (SampleClk) + begin + if Rising_Edge(SampleClk) then + if (sIn_q /= sIn or sRst = '1') then --edge detected + cntPeriods <= kNoOfPeriodsToFilter - 1; --reset counter + elsif (cntPeriods /= 0) then + cntPeriods <= cntPeriods - 1; --count down + end if; + end if; + end process PeriodCounter; +end generate Filter; + +end Behavioral; diff --git a/src/bd/Arty_Z7_20/ipshared/d2d3/src/InputSERDES.vhd b/src/bd/Arty_Z7_20/ipshared/d2d3/src/InputSERDES.vhd new file mode 100644 index 0000000..8d693e4 --- /dev/null +++ b/src/bd/Arty_Z7_20/ipshared/d2d3/src/InputSERDES.vhd @@ -0,0 +1,226 @@ +------------------------------------------------------------------------------- +-- +-- File: InputSERDES.vhd +-- Author: Elod Gyorgy +-- Original Project: HDMI input on 7-series Xilinx FPGA +-- Date: 8 October 2014 +-- +------------------------------------------------------------------------------- +-- (c) 2014 Copyright Digilent Incorporated +-- All Rights Reserved +-- +-- This program is free software; distributed under the terms of BSD 3-clause +-- license ("Revised BSD License", "New BSD License", or "Modified BSD License") +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names +-- of its contributors may be used to endorse or promote products derived +-- from this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +------------------------------------------------------------------------------- +-- +-- Purpose: +-- This module instantiates the Xilinx 7-series primitives necessary for +-- de-serializing the TMDS data stream. +-- +------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +library UNISIM; +use UNISIM.VComponents.all; + +entity InputSERDES is + Generic ( + kIDLY_TapWidth : natural := 5; -- number of bits for IDELAYE2 tap counter + kParallelWidth : natural := 10); -- number of parallel bits + Port ( + PixelClk : in std_logic; --Recovered TMDS clock x1 (CLKDIV) + SerialClk : in std_logic; --Recovered TMDS clock x5 (CLK) + + --Encoded serial data + sDataIn_p : in std_logic; --TMDS data channel positive + sDataIn_n : in std_logic; --TMDS data channel negative + + --Encoded parallel data (raw) + pDataIn : out STD_LOGIC_VECTOR (kParallelWidth-1 downto 0); + + --Control for phase alignment + pBitslip : in STD_LOGIC; --Bitslip for ISERDESE2 + pIDLY_LD : in STD_LOGIC; --IDELAYE2 Load + pIDLY_CE : in STD_LOGIC; --IDELAYE2 CE + pIDLY_INC : in STD_LOGIC; --IDELAYE2 Tap Increment + pIDLY_CNT : out std_logic_vector(kIDLY_TapWidth-1 downto 0); --IDELAYE2 Current Tap Count + + aRst : in STD_LOGIC + ); +end InputSERDES; + +architecture Behavioral of InputSERDES is + +signal sDataIn, sDataInDly, icascade1, icascade2, SerialClkInv : std_logic; +signal pDataIn_q : std_logic_vector(13 downto 0); --ISERDESE2 can do 1:14 at most +begin + +-- Differential input buffer for TMDS I/O standard +InputBuffer: IBUFDS + generic map ( + DIFF_TERM => FALSE, + IOSTANDARD => "TMDS_33") + port map ( + I => sDataIn_p, + IB => sDataIn_n, + O => sDataIn); + +-- Delay element for phase alignment of serial data +InputDelay: IDELAYE2 + generic map ( + CINVCTRL_SEL => "FALSE", -- TRUE, FALSE + DELAY_SRC => "IDATAIN", -- IDATAIN, DATAIN + HIGH_PERFORMANCE_MODE => "TRUE", -- TRUE, FALSE + IDELAY_TYPE => "VARIABLE", -- FIXED, VARIABLE, or VAR_LOADABLE + IDELAY_VALUE => 0, -- 0 to 31 + REFCLK_FREQUENCY => 200.0, + PIPE_SEL => "FALSE", + SIGNAL_PATTERN => "DATA") -- CLOCK, DATA + port map ( + DATAOUT => sDataInDly, -- Delayed signal + DATAIN => '0', -- Not used; IDATAIN instead + C => PixelClk, -- Clock for control signals (CE,INC...) + CE => pIDLY_CE, + INC => pIDLY_INC, + IDATAIN => sDataIn, -- Driven by IOB + LD => pIDLY_LD, + REGRST => '0', --not used in VARIABLE mode + LDPIPEEN => '0', + CNTVALUEIN => "00000", --not used in VARIABLE mode + CNTVALUEOUT => pIDLY_CNT, -- current tap value + CINVCTRL => '0'); + +--Invert locally for ISERDESE2 +SerialClkInv <= not SerialClk; + +-- De-serializer, 1:10 (1:5 DDR), master-slave cascaded +DeserializerMaster: ISERDESE2 + generic map ( + DATA_RATE => "DDR", + DATA_WIDTH => kParallelWidth, + INTERFACE_TYPE => "NETWORKING", + DYN_CLKDIV_INV_EN => "FALSE", + DYN_CLK_INV_EN => "FALSE", + NUM_CE => 2, + OFB_USED => "FALSE", + IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6 + SERDES_MODE => "MASTER") + port map ( + Q1 => pDataIn_q(0), + Q2 => pDataIn_q(1), + Q3 => pDataIn_q(2), + Q4 => pDataIn_q(3), + Q5 => pDataIn_q(4), + Q6 => pDataIn_q(5), + Q7 => pDataIn_q(6), + Q8 => pDataIn_q(7), + SHIFTOUT1 => icascade1, -- Cascade connection to Slave ISERDES + SHIFTOUT2 => icascade2, -- Cascade connection to Slave ISERDES + BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any + CE1 => '1', -- 1-bit Clock enable input + CE2 => '1', -- 1-bit Clock enable input + CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO + CLKB => SerialClkInv, -- Locally inverted clock + CLKDIV => PixelClk, -- Slow clock driven by BUFR + CLKDIVP => '0', --Not used here + D => '0', + DDLY => sDataInDly, -- 1-bit Input signal from IODELAYE1. + RST => aRst, -- 1-bit Asynchronous reset only. + SHIFTIN1 => '0', + SHIFTIN2 => '0', + -- unused connections + DYNCLKDIVSEL => '0', + DYNCLKSEL => '0', + OFB => '0', + OCLK => '0', + OCLKB => '0', + O => open); -- unregistered output of ISERDESE1 + +DeserializerSlave: ISERDESE2 + generic map ( + DATA_RATE => "DDR", + DATA_WIDTH => 10, + INTERFACE_TYPE => "NETWORKING", + DYN_CLKDIV_INV_EN => "FALSE", + DYN_CLK_INV_EN => "FALSE", + NUM_CE => 2, + OFB_USED => "FALSE", + IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6 + SERDES_MODE => "SLAVE") + port map ( + Q1 => open, --not used in cascaded mode + Q2 => open, --not used in cascaded mode + Q3 => pDataIn_q(8), + Q4 => pDataIn_q(9), + Q5 => pDataIn_q(10), + Q6 => pDataIn_q(11), + Q7 => pDataIn_q(12), + Q8 => pDataIn_q(13), + SHIFTOUT1 => open, + SHIFTOUT2 => open, + SHIFTIN1 => icascade1, -- Cascade connections from Master ISERDES + SHIFTIN2 => icascade2,-- Cascade connections from Master ISERDES + BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any + CE1 => '1', -- 1-bit Clock enable input + CE2 => '1', -- 1-bit Clock enable input + CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO + CLKB => SerialClkInv, -- Locally inverted clock + CLKDIV => PixelClk, -- Slow clock driven by BUFR + CLKDIVP => '0', --Not used here + D => '0', + DDLY => '0', -- not used in cascaded Slave mode + RST => aRst, -- 1-bit Asynchronous reset only. + -- unused connections + DYNCLKDIVSEL => '0', + DYNCLKSEL => '0', + OFB => '0', + OCLK => '0', + OCLKB => '0', + O => open); -- unregistered output of ISERDESE1 + +------------------------------------------------------------- +-- Concatenate the serdes outputs together. Keep the timesliced +-- bits together, and placing the earliest bits on the right +-- ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ... +-- the output will be 3210, 7654, ... +------------------------------------------------------------- +SliceISERDES_q: for slice_count in 0 to kParallelWidth-1 generate begin + --DVI sends least significant bit first + -- This places the first data in time on the right + pDataIn(slice_count) <= pDataIn_q(kParallelWidth-slice_count-1); +end generate SliceISERDES_q; + +end Behavioral; diff --git a/src/bd/Arty_Z7_20/ipshared/d2d3/src/PhaseAlign.vhd b/src/bd/Arty_Z7_20/ipshared/d2d3/src/PhaseAlign.vhd new file mode 100644 index 0000000..be61bb7 --- /dev/null +++ b/src/bd/Arty_Z7_20/ipshared/d2d3/src/PhaseAlign.vhd @@ -0,0 +1,394 @@ +------------------------------------------------------------------------------- +-- +-- File: PhaseAlign.vhd +-- Author: Elod Gyorgy +-- Original Project: HDMI input on 7-series Xilinx FPGA +-- Date: 7 October 2014 +-- +------------------------------------------------------------------------------- +-- (c) 2014 Copyright Digilent Incorporated +-- All Rights Reserved +-- +-- This program is free software; distributed under the terms of BSD 3-clause +-- license ("Revised BSD License", "New BSD License", or "Modified BSD License") +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names +-- of its contributors may be used to endorse or promote products derived +-- from this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +------------------------------------------------------------------------------- +-- +-- Purpose: +-- This module receives a DVI-encoded stream of 10-bit deserialized words +-- and tries to change the phase of the serial data to shift the sampling +-- event to the middle of the "eye", ie. the part of the bit period where +-- data is stable. Alignment is achieved by incrementing the tap count of +-- the IDELAYE2 primitives, delaying data by kIDLY_TapValuePs in each step. +-- In Artix-7 architecture each tap (step) accounts to 78 ps. +-- Data is considered valid when control tokens are recognized in the +-- stream. Alignment lock is achieved when the middle of the valid eye is +-- found. When this happens, pAligned will go high. If the whole range of +-- delay values had been exhausted and alignment lock could still not be +-- achieved, pError will go high. Resetting the module with pRst will +-- restart the alignment process. +-- The port pEyeSize provides an approximation of the width of the +-- eye in units of tap count. The larger the number, the better the signal +-- quality of the DVI stream. +-- Since the IDELAYE2 primitive only allows a fine alignment, the bitslip +-- feature of the ISERDES primitives complements the PhaseAlign module acting +-- as coarse alignment to find the 10-bit word boundary in the data stream. +------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use work.DVI_Constants.ALL; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity PhaseAlign is + Generic ( + kUseFastAlgorithm : boolean := false; + kCtlTknCount : natural := 128; --how many subsequent control tokens make a valid blank detection + kIDLY_TapValuePs : natural := 78; --delay in ps per tap + kIDLY_TapWidth : natural := 5); --number of bits for IDELAYE2 tap counter + Port ( + pRst : in STD_LOGIC; + pTimeoutOvf : in std_logic; --50ms timeout expired + pTimeoutRst : out std_logic; --reset timeout + PixelClk : in STD_LOGIC; + pData : in STD_LOGIC_VECTOR (9 downto 0); + pIDLY_CE : out STD_LOGIC; + pIDLY_INC : out STD_LOGIC; + pIDLY_CNT : in STD_LOGIC_VECTOR (kIDLY_TapWidth-1 downto 0); + pIDLY_LD : out STD_LOGIC; --load default tap value + pAligned : out STD_LOGIC; + pError : out STD_LOGIC; + pEyeSize : out STD_LOGIC_VECTOR(kIDLY_TapWidth-1 downto 0)); +end PhaseAlign; + +architecture Behavioral of PhaseAlign is +-- Control Token Counter +signal pCtlTknCnt : natural range 0 to kCtlTknCount-1; +signal pCtlTknRst, pCtlTknOvf : std_logic; + +-- Control Token Detection Pipeline +signal pTkn0Flag, pTkn1Flag, pTkn2Flag, pTkn3Flag : std_logic; +signal pTkn0FlagQ, pTkn1FlagQ, pTkn2FlagQ, pTkn3FlagQ : std_logic; +signal pTknFlag, pTknFlagQ, pBlankBegin : std_logic; +signal pDataQ : std_logic_vector(pData'high downto pData'low); + +constant kTapCntEnd : std_logic_vector(pIDLY_CNT'range) := (others => '0'); +constant kFastTapCntEnd : std_logic_vector(pIDLY_CNT'range) := std_logic_vector(to_unsigned(20, pIDLY_CNT'length)); -- fast search limit; if token not found in 20 taps, fail earlier and bitslip +signal pIDLY_CNT_Q : std_logic_vector(pIDLY_CNT'range); +signal pDelayOvf, pDelayFastOvf, pDelayCenter : std_logic; + +-- IDELAY increment/decrement wait counter +-- CE, INC registered outputs + CNTVALUEOUT registered input + CNTVALUEOUT registered comparison +constant kDelayWaitEnd : natural := 3; +signal pDelayWaitCnt : natural range 0 to kDelayWaitEnd - 1; +signal pDelayWaitRst, pDelayWaitOvf : std_logic; + +constant kEyeOpenCntMin : natural := 3; +constant kEyeOpenCntEnough : natural := 16; +signal pEyeOpenCnt : unsigned(kIDLY_TapWidth-1 downto 0); +signal pCenterTap : unsigned(kIDLY_TapWidth downto 0); -- 1 extra bit to increment with 1/2 for every open eye tap +signal pEyeOpenRst, pEyeOpenEn : std_logic; + +--Flags +signal pFoundJtrFlag, pFoundEyeFlag : std_logic; +--FSM +--type state_t is (ResetSt, IdleSt, TokenSt, EyeOpenSt, JtrZoneSt, DlyIncSt, DlyTstOvfSt, DlyDecSt, DlyTstCenterSt, AlignedSt, AlignErrorSt); +subtype state_t is std_logic_vector(10 downto 0); +signal pState, pStateNxt : state_t; +-- Ugh, manual state encoding, since Vivado won't tell me the result of automatic encoding; we need this for debugging. +constant ResetSt : state_t := "00000000001"; +constant IdleSt : state_t := "00000000010"; +constant TokenSt : state_t := "00000000100"; +constant EyeOpenSt : state_t := "00000001000"; +constant JtrZoneSt : state_t := "00000010000"; +constant DlyIncSt : state_t := "00000100000"; +constant DlyTstOvfSt : state_t := "00001000000"; +constant DlyDecSt : state_t := "00010000000"; +constant DlyTstCenterSt : state_t :="00100000000"; +constant AlignedSt : state_t := "01000000000"; +constant AlignErrorSt : state_t := "10000000000"; + +begin + +ControlTokenCounter: process(PixelClk) +begin + if Rising_Edge(PixelClk) then + if (pCtlTknRst = '1') then + pCtlTknCnt <= 0; + else + pCtlTknCnt <= pCtlTknCnt + 1; + -- Overflow + if (pCtlTknCnt = kCtlTknCount - 1) then + pCtlTknOvf <= '1'; + else + pCtlTknOvf <= '0'; + end if; + end if; + end if; +end process ControlTokenCounter; + +-- Control Token Detection +pTkn0Flag <= '1' when pDataQ = kCtlTkn0 else '0'; +pTkn1Flag <= '1' when pDataQ = kCtlTkn1 else '0'; +pTkn2Flag <= '1' when pDataQ = kCtlTkn2 else '0'; +pTkn3Flag <= '1' when pDataQ = kCtlTkn3 else '0'; + +-- Register pipeline +ControlTokenDetect: process(PixelClk) +begin + if Rising_Edge(PixelClk) then + pDataQ <= pData; -- level 1 + pTkn0FlagQ <= pTkn0Flag; + pTkn1FlagQ <= pTkn1Flag; + pTkn2FlagQ <= pTkn2Flag; + pTkn3FlagQ <= pTkn3Flag; -- level 2 + pTknFlag <= pTkn0Flag or pTkn1Flag or pTkn2Flag or pTkn3Flag; -- level 3 + pTknFlagQ <= pTknFlag; + pBlankBegin <= not pTknFlagQ and pTknFlag; -- level 4 + end if; +end process ControlTokenDetect; + +-- Open Eye Width Counter +EyeOpenCnt: process (PixelClk) +begin + if Rising_Edge(PixelClk) then + if (pEyeOpenRst = '1') then + pEyeOpenCnt <= (others => '0'); + pCenterTap <= unsigned(pIDLY_CNT_Q) & '1'; -- 1 extra bit for 1/2 increments; start with 1/2 + elsif (pEyeOpenEn = '1') then + pEyeOpenCnt <= pEyeOpenCnt + 1; + pCenterTap <= pCenterTap + 1; + end if; + end if; +end process EyeOpenCnt; + +pEyeSize <= std_logic_vector(pEyeOpenCnt); + +-- Tap Delay Overflow +TapDelayCnt: process (PixelClk) +begin + if Rising_Edge(PixelClk) then + pIDLY_CNT_Q <= pIDLY_CNT; + if (pIDLY_CNT_Q = kTapCntEnd) then + pDelayOvf <= '1'; + else + pDelayOvf <= '0'; + end if; + if (pIDLY_CNT_Q = kFastTapCntEnd) then + pDelayFastOvf <= '1'; + else + pDelayFastOvf <= '0'; + end if; + end if; +end process TapDelayCnt; + +-- Tap Delay Center +TapDelayCenter: process (PixelClk) +begin + if Rising_Edge(PixelClk) then + if (unsigned(pIDLY_CNT_Q) = SHIFT_RIGHT(pCenterTap, 1)) then + pDelayCenter <= '1'; + else + pDelayCenter <= '0'; + end if; + end if; +end process TapDelayCenter; + +DelayIncWaitCounter: process (PixelClk) +begin + if Rising_Edge(PixelClk) then + if (pDelayWaitRst = '1') then + pDelayWaitCnt <= 0; + else + pDelayWaitCnt <= pDelayWaitCnt + 1; + if (pDelayWaitCnt = kDelayWaitEnd - 1) then + pDelayWaitOvf <= '1'; + else + pDelayWaitOvf <= '0'; + end if; + end if; + end if; +end process DelayIncWaitCounter; + +-- FSM +FSM_Sync: process (PixelClk) +begin + if Rising_Edge(PixelClk) then + if (pRst = '1') then + pState <= ResetSt; + else + pState <= pStateNxt; + + end if; + end if; +end process FSM_Sync; + +--FSM Outputs +pTimeoutRst <= '0' when pState = IdleSt or pState = TokenSt else '1'; +pCtlTknRst <= '0' when pState = TokenSt else '1'; +pDelayWaitRst <= '0' when pState = DlyTstOvfSt or pState = DlyTstCenterSt else '1'; +pEyeOpenRst <= '1' when pState = ResetSt or (pState = JtrZoneSt and pFoundEyeFlag = '0') else '0'; +pEyeOpenEn <= '1' when pState = EyeOpenSt else '0'; + +--FSM Registered Outputs +FSM_RegOut: process (PixelClk) +begin + if Rising_Edge(PixelClk) then + if (pState = ResetSt) then + pIDLY_LD <= '1'; + else + pIDLY_LD <= '0'; + end if; + + if (pState = DlyIncSt) then + pIDLY_INC <= '1'; + pIDLY_CE <= '1'; + elsif (pState = DlyDecSt) then + pIDLY_INC <= '0'; + pIDLY_CE <= '1'; + else + pIDLY_CE <= '0'; + end if; + + if (pState = AlignedSt) then + pAligned <= '1'; + else + pAligned <= '0'; + end if; + + if (pState = AlignErrorSt) then + pError <= '1'; + else + pError <= '0'; + end if; + end if; +end process FSM_RegOut; + +FSM_Flags: process (PixelClk) +begin + if Rising_Edge(PixelClk) then + case (pState) is + when ResetSt => + pFoundEyeFlag <= '0'; + pFoundJtrFlag <= '0'; + when JtrZoneSt => + pFoundJtrFlag <= '1'; + when EyeOpenSt => + -- We consider the eye found, if we had found jitter before and the eye is at least kEyeOpenCntMin wide OR + -- We have not seen jitter yet (because tap 0 was already in the eye) and the eye is at least kEyeOpenCntEnough wide + if ((pFoundJtrFlag = '1' and pEyeOpenCnt = kEyeOpenCntMin) or (pEyeOpenCnt = kEyeOpenCntEnough)) then + pFoundEyeFlag <= '1'; + end if; + when others => + end case; + end if; +end process FSM_Flags; + +FSM_NextState: process (pState, pBlankBegin, pTimeoutOvf, pCtlTknOvf, pDelayOvf, pDelayFastOvf, pDelayWaitOvf, pDelayCenter, pFoundEyeFlag, pTknFlagQ) +begin + + pStateNxt <= pState; --default is to stay in current state + + case (pState) is + when ResetSt => + pStateNxt <= IdleSt; + + when IdleSt => -- waiting for a token with timeout + if (pBlankBegin = '1') then + pStateNxt <= TokenSt; + elsif (pTimeoutOvf = '1') then + pStateNxt <= JtrZoneSt; -- we didn't find a proper blank, must be in jitter zone + end if; + + when TokenSt => -- waiting for kCtlTknCount tokens with timeout + if (pTknFlagQ = '0') then + pStateNxt <= IdleSt; + elsif (pCtlTknOvf = '1') then + pStateNxt <= EyeOpenSt; + end if; + + when JtrZoneSt => + if (pFoundEyeFlag = '1') then + pStateNxt <= DlyDecSt; -- this jitter zone ends an open eye, go back to the middle of the eye + elsif (kUseFastAlgorithm and pDelayFastOvf = '1' and pFoundEyeFlag = '0') then + pStateNxt <= AlignErrorSt; + else + pStateNxt <= DlyIncSt; + end if; + + when EyeOpenSt => + -- If our eye is already kEyeOpenCntEnough wide, consider the search finished and consider the current tap value + -- the end of our eye = jitter zone + if (pEyeOpenCnt = kEyeOpenCntEnough) then + pStateNxt <= JtrZoneSt; + else + pStateNxt <= DlyIncSt; + end if; + + when DlyIncSt => + pStateNxt <= DlyTstOvfSt; + + when DlyTstOvfSt => + if (pDelayWaitOvf = '1') then + if (pDelayOvf = '1') then + pStateNxt <= AlignErrorSt; -- we went through all the delay taps + else + pStateNxt <= IdleSt; + end if; + end if; + + when DlyDecSt => + pStateNxt <= DlyTstCenterSt; + + when DlyTstCenterSt => + if (pDelayWaitOvf = '1') then + if (pDelayCenter = '1') then + pStateNxt <= AlignedSt; -- we went back to the center of the eye, done + else + pStateNxt <= DlyDecSt; + end if; + end if; + + when AlignedSt => + null; --stay here + + when AlignErrorSt => + null; --stay here + + when others => + pStateNxt <= ResetSt; + end case; +end process FSM_NextState; + +end Behavioral; diff --git a/src/bd/Arty_Z7_20/ipshared/d2d3/src/ResyncToBUFG.vhd b/src/bd/Arty_Z7_20/ipshared/d2d3/src/ResyncToBUFG.vhd new file mode 100644 index 0000000..60006a9 --- /dev/null +++ b/src/bd/Arty_Z7_20/ipshared/d2d3/src/ResyncToBUFG.vhd @@ -0,0 +1,102 @@ +------------------------------------------------------------------------------- +-- +-- File: ResyncToBUFG.vhd +-- Author: Elod Gyorgy +-- Original Project: HDMI input on 7-series Xilinx FPGA +-- Date: 7 July 2015 +-- +------------------------------------------------------------------------------- +-- (c) 2015 Copyright Digilent Incorporated +-- All Rights Reserved +-- +-- This program is free software; distributed under the terms of BSD 3-clause +-- license ("Revised BSD License", "New BSD License", or "Modified BSD License") +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names +-- of its contributors may be used to endorse or promote products derived +-- from this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +------------------------------------------------------------------------------- +-- +-- Purpose: +-- This module inserts a BUFG on the PixelClk path so that the pixel bus can be +-- routed globally on the device. It also synchronizes data to the new BUFG +-- clock. +-- +------------------------------------------------------------------------------- + + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +library UNISIM; +use UNISIM.VComponents.all; + +entity ResyncToBUFG is + Port ( + -- Video in + piData : in std_logic_vector(23 downto 0); + piVDE : in std_logic; + piHSync : in std_logic; + piVSync : in std_logic; + PixelClkIn : in std_logic; + -- Video out + poData : out std_logic_vector(23 downto 0); + poVDE : out std_logic; + poHSync : out std_logic; + poVSync : out std_logic; + PixelClkOut : out std_logic + ); +end ResyncToBUFG; + +architecture Behavioral of ResyncToBUFG is + +signal PixelClkInt : std_logic; + +begin +-- Insert BUFG on clock path +InstBUFG: BUFG + port map ( + O => PixelClkInt, -- 1-bit output: Clock output + I => PixelClkIn -- 1-bit input: Clock input + ); +PixelClkOut <= PixelClkInt; + +-- Try simple registering +RegisterData: process(PixelClkInt) +begin + if Rising_Edge(PixelClkInt) then + poData <= piData; + poVDE <= piVDE; + poHSync <= piHSync; + poVSync <= piVSync; + end if; +end process RegisterData; + +end Behavioral; diff --git a/src/bd/Arty_Z7_20/ipshared/d2d3/src/SyncAsync.vhd b/src/bd/Arty_Z7_20/ipshared/d2d3/src/SyncAsync.vhd new file mode 100644 index 0000000..f1d7d13 --- /dev/null +++ b/src/bd/Arty_Z7_20/ipshared/d2d3/src/SyncAsync.vhd @@ -0,0 +1,88 @@ +------------------------------------------------------------------------------- +-- +-- File: SyncAsync.vhd +-- Author: Elod Gyorgy +-- Original Project: HDMI input on 7-series Xilinx FPGA +-- Date: 20 October 2014 +-- +------------------------------------------------------------------------------- +-- (c) 2014 Copyright Digilent Incorporated +-- All Rights Reserved +-- +-- This program is free software; distributed under the terms of BSD 3-clause +-- license ("Revised BSD License", "New BSD License", or "Modified BSD License") +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names +-- of its contributors may be used to endorse or promote products derived +-- from this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +------------------------------------------------------------------------------- +-- +-- Purpose: +-- This module synchronizes the asynchronous signal (aIn) with the OutClk clock +-- domain and provides it on oOut. The number of FFs in the synchronizer chain +-- can be configured with kStages. The reset value for oOut can be configured +-- with kResetTo. The asynchronous reset (aReset) is always active-high. +-- +------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity SyncAsync is + Generic ( + kResetTo : std_logic := '0'; --value when reset and upon init + kStages : natural := 2); --double sync by default + Port ( + aReset : in STD_LOGIC; -- active-high asynchronous reset + aIn : in STD_LOGIC; + OutClk : in STD_LOGIC; + oOut : out STD_LOGIC); +end SyncAsync; + +architecture Behavioral of SyncAsync is +signal oSyncStages : std_logic_vector(kStages-1 downto 0) := (others => kResetTo); +attribute ASYNC_REG : string; +attribute ASYNC_REG of oSyncStages: signal is "TRUE"; +begin + +Sync: process (OutClk, aReset) +begin + if (aReset = '1') then + oSyncStages <= (others => kResetTo); + elsif Rising_Edge(OutClk) then + oSyncStages <= oSyncStages(oSyncStages'high-1 downto 0) & aIn; + end if; +end process Sync; +oOut <= oSyncStages(oSyncStages'high); + +end Behavioral; diff --git a/src/bd/Arty_Z7_20/ipshared/d2d3/src/SyncAsyncReset.vhd b/src/bd/Arty_Z7_20/ipshared/d2d3/src/SyncAsyncReset.vhd new file mode 100644 index 0000000..4047c51 --- /dev/null +++ b/src/bd/Arty_Z7_20/ipshared/d2d3/src/SyncAsyncReset.vhd @@ -0,0 +1,90 @@ +------------------------------------------------------------------------------- +-- +-- File: SyncAsyncReset.vhd +-- Author: Elod Gyorgy +-- Original Project: HDMI input on 7-series Xilinx FPGA +-- Date: 20 October 2014 +-- +------------------------------------------------------------------------------- +-- (c) 2014 Copyright Digilent Incorporated +-- All Rights Reserved +-- +-- This program is free software; distributed under the terms of BSD 3-clause +-- license ("Revised BSD License", "New BSD License", or "Modified BSD License") +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names +-- of its contributors may be used to endorse or promote products derived +-- from this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +------------------------------------------------------------------------------- +-- +-- Purpose: +-- This module is a reset-bridge. It takes a reset signal asynchronous to the +-- target clock domain (OutClk) and provides a safe asynchronous or synchronous +-- reset for the OutClk domain (oRst). The signal oRst is asserted immediately +-- as aRst arrives, but is de-asserted synchronously with the OutClk rising +-- edge. This means it can be used to safely reset any FF in the OutClk domain, +-- respecting recovery time specs for FFs. +-- +------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ResetBridge is + Generic ( + kPolarity : std_logic := '1'); + Port ( + aRst : in STD_LOGIC; -- asynchronous reset; active-high, if kPolarity=1 + OutClk : in STD_LOGIC; + oRst : out STD_LOGIC); +end ResetBridge; + +architecture Behavioral of ResetBridge is +signal aRst_int : std_logic; +attribute KEEP : string; +attribute KEEP of aRst_int: signal is "TRUE"; +begin + +aRst_int <= kPolarity xnor aRst; --SyncAsync uses active-high reset + +SyncAsyncx: entity work.SyncAsync + generic map ( + kResetTo => kPolarity, + kStages => 2) --use double FF synchronizer + port map ( + aReset => aRst_int, + aIn => not kPolarity, + OutClk => OutClk, + oOut => oRst); + +end Behavioral; diff --git a/src/bd/Arty_Z7_20/ipshared/d2d3/src/SyncBase.vhd b/src/bd/Arty_Z7_20/ipshared/d2d3/src/SyncBase.vhd new file mode 100644 index 0000000..d185810 --- /dev/null +++ b/src/bd/Arty_Z7_20/ipshared/d2d3/src/SyncBase.vhd @@ -0,0 +1,100 @@ +------------------------------------------------------------------------------- +-- +-- File: SyncBase.vhd +-- Author: Elod Gyorgy +-- Original Project: HDMI input on 7-series Xilinx FPGA +-- Date: 20 October 2014 +-- +------------------------------------------------------------------------------- +-- (c) 2014 Copyright Digilent Incorporated +-- All Rights Reserved +-- +-- This program is free software; distributed under the terms of BSD 3-clause +-- license ("Revised BSD License", "New BSD License", or "Modified BSD License") +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names +-- of its contributors may be used to endorse or promote products derived +-- from this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +------------------------------------------------------------------------------- +-- +-- Purpose: +-- This module synchronizes a signal (iIn) in one clock domain (InClk) with +-- another clock domain (OutClk) and provides it on oOut. +-- The number of FFs in the synchronizer chain +-- can be configured with kStages. The reset value for oOut can be configured +-- with kResetTo. The asynchronous reset (aReset) is always active-high. +-- +------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity SyncBase is + Generic ( + kResetTo : std_logic := '0'; --value when reset and upon init + kStages : natural := 2); --double sync by default + Port ( + aReset : in STD_LOGIC; -- active-high asynchronous reset + InClk : in std_logic; + iIn : in STD_LOGIC; + OutClk : in STD_LOGIC; + oOut : out STD_LOGIC); +end SyncBase; + +architecture Behavioral of SyncBase is + +signal iIn_q : std_logic; +begin + +--By re-registering iIn on its own domain, we make sure iIn_q is glitch-free +SyncSource: process(aReset, InClk) +begin + if (aReset = '1') then + iIn_q <= kResetTo; + elsif Rising_Edge(InClk) then + iIn_q <= iIn; + end if; +end process SyncSource; + +--Crossing clock boundary here +SyncAsyncx: entity work.SyncAsync + generic map ( + kResetTo => kResetTo, + kStages => kStages) + port map ( + aReset => aReset, + aIn => iIn_q, + OutClk => OutClk, + oOut => oOut); + +end Behavioral; diff --git a/src/bd/Arty_Z7_20/ipshared/d2d3/src/TMDS_Clocking.vhd b/src/bd/Arty_Z7_20/ipshared/d2d3/src/TMDS_Clocking.vhd new file mode 100644 index 0000000..c818600 --- /dev/null +++ b/src/bd/Arty_Z7_20/ipshared/d2d3/src/TMDS_Clocking.vhd @@ -0,0 +1,289 @@ +------------------------------------------------------------------------------- +-- +-- File: TMDS_Clocking.vhd +-- Author: Elod Gyorgy +-- Original Project: HDMI input on 7-series Xilinx FPGA +-- Date: 10 October 2014 +-- +------------------------------------------------------------------------------- +-- (c) 2014 Copyright Digilent Incorporated +-- All Rights Reserved +-- +-- This program is free software; distributed under the terms of BSD 3-clause +-- license ("Revised BSD License", "New BSD License", or "Modified BSD License") +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names +-- of its contributors may be used to endorse or promote products derived +-- from this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +------------------------------------------------------------------------------- +-- +-- Purpose: +-- This module instantiates all the necessary primitives to obtain a fast +-- serial clock from the TMDS Clock pins to be used for deserializing the TMDS +-- Data channels. Connect this module directly to the top-level TMDS Clock pins +-- and a 200/300 MHz reference clock. +-- +------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.math_real.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +library UNISIM; +use UNISIM.VComponents.all; + +entity TMDS_Clocking is + Generic ( + kClkRange : natural := 1); -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3, >=30MHz=4, >=25MHz=5 + Port ( + TMDS_Clk_p : in std_logic; + TMDS_Clk_n : in std_logic; + RefClk : in std_logic; -- 200MHz reference clock for IDELAY primitives; independent of DVI_Clk! + aRst : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec + SerialClk : out std_logic; + PixelClk : out std_logic; + aLocked : out std_logic); +end TMDS_Clocking; + +architecture Behavioral of TMDS_Clocking is +constant kDlyRstDelay : natural := 32; +signal aDlyLckd, rDlyRst, rBUFR_Rst, rLockLostRst : std_logic; +signal rDlyRstCnt : natural range 0 to kDlyRstDelay - 1 := kDlyRstDelay - 1; + +signal clkfbout_hdmi_clk, CLK_IN_hdmi_clk, CLK_OUT_1x_hdmi_clk, CLK_OUT_5x_hdmi_clk : std_logic; +signal clkout1b_unused, clkout2_unused, clkout2b_unused, clkout3_unused, clkout3b_unused, clkout4_unused, clkout5_unused, clkout6_unused, +drdy_unused, psdone_unused, clkfbstopped_unused, clkinstopped_unused, clkfboutb_unused, clkout0b_unused, clkout1_unused : std_logic; +signal do_unused : std_logic_vector(15 downto 0); +signal LOCKED_int, rRdyRst : std_logic; +signal aMMCM_Locked, rMMCM_Locked_ms, rMMCM_Locked, rMMCM_LckdFallingFlag, rMMCM_LckdRisingFlag : std_logic; +signal rMMCM_Reset_q : std_logic_vector(1 downto 0); +signal rMMCM_Locked_q : std_logic_vector(1 downto 0); + +begin + +-- We need a reset bridge to use the asynchronous aRst signal to reset our circuitry +-- and decrease the chance of metastability. The signal rLockLostRst can be used as +-- asynchronous reset for any flip-flop in the RefClk domain, since it will be de-asserted +-- synchronously. +LockLostReset: entity work.ResetBridge + generic map ( + kPolarity => '1') + port map ( + aRst => aRst, + OutClk => RefClk, + oRst => rLockLostRst); + +--IDELAYCTRL must be reset after configuration or refclk lost for 52ns(K7), 72ns(A7) at least +ResetIDELAYCTRL: process(rLockLostRst, RefClk) +begin + if Rising_Edge(RefClk) then + if (rLockLostRst = '1') then + rDlyRstCnt <= kDlyRstDelay - 1; + rDlyRst <= '1'; + elsif (rDlyRstCnt /= 0) then + rDlyRstCnt <= rDlyRstCnt - 1; + else + rDlyRst <= '0'; + end if; + end if; +end process; + +IDelayCtrlX: IDELAYCTRL + port map ( + RDY => aDlyLckd, + REFCLK => RefClk, + RST => rDlyRst); + +RdyLostReset: entity work.ResetBridge + generic map ( + kPolarity => '1') + port map ( + aRst => not aDlyLckd, + OutClk => RefClk, + oRst => rRdyRst); + +InputBuffer: IBUFDS + generic map ( + DIFF_TERM => FALSE, -- Differential Termination + IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards + IOSTANDARD => "TMDS_33") + port map + ( + O => CLK_IN_hdmi_clk, + I => TMDS_Clk_p, + IB => TMDS_Clk_n); + +-- The TMDS Clk channel carries a character-rate frequency reference +-- In a single Clk period a whole character (10 bits) is transmitted +-- on each data channel. For deserialization of data channel a faster, +-- serial clock needs to be generated. In 7-series architecture an +-- ISERDESE2 primitive doing a 10:1 deserialization in DDR mode needs +-- a fast 5x clock and a slow 1x clock. These two clocks are generated +-- below with an MMCME2_ADV and BUFR primitive. +-- Caveats: +-- 1. The primitive uses a multiply-by-5 and divide-by-1 to generate +-- a 5x fast clock. +-- While changes in the frequency of the TMDS Clk are tracked by the +-- MMCM, for some TMDS Clk frequencies the datasheet specs for the VCO +-- frequency limits are not met. In other words, there is no single +-- set of MMCM multiply and divide values that can work for the whole +-- range of resolutions and pixel clock frequencies. +-- For example: MMCM_FVCOMIN = 600 MHz +-- MMCM_FVCOMAX = 1200 MHz for Artix-7 -1 speed grade +-- while FVCO = FIN * MULT_F +-- The TMDS Clk for 720p resolution in 74.25 MHz +-- FVCO = 74.25 * 10 = 742.5 MHz, which is between FVCOMIN and FVCOMAX +-- However, the TMDS Clk for 1080p resolution in 148.5 MHz +-- FVCO = 148.5 * 10 = 1480 MHZ, which is above FVCOMAX +-- In the latter case, MULT_F = 5, DIVIDE_F = 5, DIVIDE = 1 would result +-- in a correct VCO frequency, while still generating 5x and 1x clocks +-- 2. The MMCM+BUFIO+BUFR combination results in the highest possible +-- frequencies. PLLE2_ADV could work only with BUFGs, which limits +-- the maximum achievable frequency. The reason is that only the MMCM +-- has dedicated route to BUFIO. +-- If a PLLE2_ADV with BUFGs are used a second CLKOUTx can be used to +-- generate the 1x clock. +DVI_ClkGenerator: MMCME2_ADV + generic map + (BANDWIDTH => "OPTIMIZED", + CLKOUT4_CASCADE => FALSE, + COMPENSATION => "ZHOLD", + STARTUP_WAIT => FALSE, + DIVCLK_DIVIDE => 1, + CLKFBOUT_MULT_F => real(kClkRange) * 5.0, + CLKFBOUT_PHASE => 0.000, + CLKFBOUT_USE_FINE_PS => FALSE, + CLKOUT0_DIVIDE_F => real(kClkRange) * 1.0, + CLKOUT0_PHASE => 0.000, + CLKOUT0_DUTY_CYCLE => 0.500, + CLKOUT0_USE_FINE_PS => FALSE, + CLKIN1_PERIOD => real(kClkRange) * 6.0, + REF_JITTER1 => 0.010) + port map + -- Output clocks + ( + CLKFBOUT => clkfbout_hdmi_clk, + CLKFBOUTB => clkfboutb_unused, + CLKOUT0 => CLK_OUT_5x_hdmi_clk, + CLKOUT0B => clkout0b_unused, + CLKOUT1 => clkout1_unused, + CLKOUT1B => clkout1b_unused, + CLKOUT2 => clkout2_unused, + CLKOUT2B => clkout2b_unused, + CLKOUT3 => clkout3_unused, + CLKOUT3B => clkout3b_unused, + CLKOUT4 => clkout4_unused, + CLKOUT5 => clkout5_unused, + CLKOUT6 => clkout6_unused, + -- Input clock control + CLKFBIN => clkfbout_hdmi_clk, + CLKIN1 => CLK_IN_hdmi_clk, + CLKIN2 => '0', + -- Tied to always select the primary input clock + CLKINSEL => '1', + -- Ports for dynamic reconfiguration + DADDR => (others => '0'), + DCLK => '0', + DEN => '0', + DI => (others => '0'), + DO => do_unused, + DRDY => drdy_unused, + DWE => '0', + -- Ports for dynamic phase shift + PSCLK => '0', + PSEN => '0', + PSINCDEC => '0', + PSDONE => psdone_unused, + -- Other control and status signals + LOCKED => aMMCM_Locked, + CLKINSTOPPED => clkinstopped_unused, + CLKFBSTOPPED => clkfbstopped_unused, + PWRDWN => '0', + RST => rMMCM_Reset_q(0)); + +-- 5x fast serial clock +SerialClkBuffer: BUFIO + port map ( + O => SerialClk, -- 1-bit output: Clock output (connect to I/O clock loads). + I => CLK_OUT_5x_hdmi_clk -- 1-bit input: Clock input (connect to an IBUF or BUFMR). + ); +-- 1x slow parallel clock +PixelClkBuffer: BUFR + generic map ( + BUFR_DIVIDE => "5", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8" + SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES" + ) + port map ( + O => PixelClk, -- 1-bit output: Clock output port + CE => '1', -- 1-bit input: Active high, clock enable (Divided modes only) + CLR => rBUFR_Rst, -- 1-bit input: Active high, asynchronous clear (Divided modes only) + I => CLK_OUT_5x_hdmi_clk -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect + ); +rBUFR_Rst <= rMMCM_LckdRisingFlag; --pulse CLR on BUFR one the clock returns + +MMCM_Reset: process(rLockLostRst, RefClk) +begin + if (rLockLostRst = '1') then + rMMCM_Reset_q <= (others => '1'); -- MMCM_RSTMINPULSE Minimum Reset Pulse Width 5.00ns = two RefClk periods min + elsif Rising_Edge(RefClk) then + if (rMMCM_LckdFallingFlag = '1') then + rMMCM_Reset_q <= (others => '1'); + else + rMMCM_Reset_q <= '0' & rMMCM_Reset_q(rMMCM_Reset_q'high downto 1); + end if; + end if; +end process MMCM_Reset; + +MMCM_LockSync: entity work.SyncAsync + port map ( + aReset => '0', + aIn => aMMCM_Locked, + OutClk => RefClk, + oOut => rMMCM_Locked); + +MMCM_LockedDetect: process(RefClk) +begin + if Rising_Edge(RefClk) then + rMMCM_Locked_q <= rMMCM_Locked & rMMCM_Locked_q(1); + rMMCM_LckdFallingFlag <= rMMCM_Locked_q(1) and not rMMCM_Locked; + rMMCM_LckdRisingFlag <= not rMMCM_Locked_q(1) and rMMCM_Locked; + end if; +end process MMCM_LockedDetect; + +GlitchFreeLocked: process(rRdyRst, RefClk) +begin + if (rRdyRst = '1') then + aLocked <= '0'; + elsif Rising_Edge(RefClk) then + aLocked <= rMMCM_Locked_q(0); + end if; +end process GlitchFreeLocked; + +end Behavioral; diff --git a/src/bd/Arty_Z7_20/ipshared/d2d3/src/TMDS_Decoder.vhd b/src/bd/Arty_Z7_20/ipshared/d2d3/src/TMDS_Decoder.vhd new file mode 100644 index 0000000..967f2dc --- /dev/null +++ b/src/bd/Arty_Z7_20/ipshared/d2d3/src/TMDS_Decoder.vhd @@ -0,0 +1,300 @@ +------------------------------------------------------------------------------- +-- +-- File: TMDS_Decoder.vhd +-- Author: Elod Gyorgy +-- Original Project: HDMI input on 7-series Xilinx FPGA +-- Date: 8 October 2014 +-- +------------------------------------------------------------------------------- +-- (c) 2014 Copyright Digilent Incorporated +-- All Rights Reserved +-- +-- This program is free software; distributed under the terms of BSD 3-clause +-- license ("Revised BSD License", "New BSD License", or "Modified BSD License") +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names +-- of its contributors may be used to endorse or promote products derived +-- from this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +------------------------------------------------------------------------------- +-- +-- Purpose: +-- This module connects to one TMDS data channel and decodes TMDS data +-- according to DVI specifications. It phase aligns the data channel, +-- deserializes the stream, eliminates skew between data channels and decodes +-- data in the end. +-- sDataIn_p/n -> buffer -> de-serialize -> channel de-skew -> decode -> pData +-- +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use work.DVI_Constants.ALL; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TMDS_Decoder is + Generic ( + kCtlTknCount : natural := 128; --how many subsequent control tokens make a valid blank detection + kTimeoutMs : natural := 50; --what is the maximum time interval for a blank to be detected + kRefClkFrqMHz : natural := 200; --what is the RefClk frequency + kIDLY_TapValuePs : natural := 78; --delay in ps per tap + kIDLY_TapWidth : natural := 5); --number of bits for IDELAYE2 tap counter + Port ( + PixelClk : in std_logic; --Recovered TMDS clock x1 (CLKDIV) + SerialClk : in std_logic; --Recovered TMDS clock x5 (CLK) + RefClk : std_logic; --200 MHz reference clock + aRst : in std_logic; --asynchronous reset; must be reset when PixelClk/SerialClk is not within spec + + --Encoded serial data + sDataIn_p : in std_logic; --TMDS data channel positive + sDataIn_n : in std_logic; --TMDS data channel negative + + --Decoded parallel data + pDataIn : out std_logic_vector(7 downto 0); + pC0 : out std_logic; + pC1 : out std_logic; + pVde : out std_logic; + + -- Channel bonding (three data channels in total) + pOtherChVld : in std_logic_vector(1 downto 0); + pOtherChRdy : in std_logic_vector(1 downto 0); + pMeVld : out std_logic; + pMeRdy : out std_logic; + + --Status and debug + pRst : in std_logic; -- Synchronous reset to restart lock procedure + pAlignErr : out std_logic; + pEyeSize : out STD_LOGIC_VECTOR(kIDLY_TapWidth-1 downto 0)); +end TMDS_Decoder; + +architecture Behavioral of TMDS_Decoder is +constant kBitslipDelay : natural := 3; --three-period delay after bitslip +signal pAlignRst, pLockLostRst_n : std_logic; +signal pBitslipCnt : natural range 0 to kBitslipDelay - 1 := kBitslipDelay - 1; +signal pDataIn8b : std_logic_vector(7 downto 0); +signal pDataInBnd : std_logic_vector(9 downto 0); +signal pDataInRaw : std_logic_vector(9 downto 0); +signal pMeRdy_int, pAligned, pAlignErr_int, pAlignErr_q, pBitslip : std_logic; +signal pIDLY_LD, pIDLY_CE, pIDLY_INC : std_logic; +signal pIDLY_CNT : std_logic_vector(kIDLY_TapWidth-1 downto 0); +-- Timeout Counter End +constant kTimeoutEnd : natural := kTimeoutMs * 1000 * kRefClkFrqMHz; +signal rTimeoutCnt : natural range 0 to kTimeoutEnd-1; +signal pTimeoutRst, pTimeoutOvf, rTimeoutRst, rTimeoutOvf : std_logic; +begin + +-- Deserialization block +InputSERDES_X: entity work.InputSERDES + generic map ( + kIDLY_TapWidth => kIDLY_TapWidth, + kParallelWidth => 10 -- TMDS uses 1:10 serialization + ) + port map ( + PixelClk => PixelClk, + SerialClk => SerialClk, + sDataIn_p => sDataIn_p, + sDataIn_n => sDataIn_n, + + --Encoded parallel data (raw) + pDataIn => pDataInRaw, + + --Control for phase alignment + pBitslip => pBitslip, + pIDLY_LD => pIDLY_LD, + pIDLY_CE => pIDLY_CE, + pIDLY_INC => pIDLY_INC, + pIDLY_CNT => pIDLY_CNT, + + aRst => aRst + ); +-- reset min two period (ISERDESE2 requirement) +-- de-assert synchronously with CLKDIV, min two period (ISERDESE2 requirement) + +--The timeout counter runs on RefClk, because it's a fixed frequency we can measure timeout +--independently of the TMDS Clk +--The xTimeoutRst and xTimeoutOvf signals need to be synchronized back-and-forth +TimeoutCounter: process(RefClk) +begin + if Rising_Edge(RefClk) then + if (rTimeoutRst = '1') then + rTimeoutCnt <= 0; + elsif (rTimeoutOvf = '0') then + rTimeoutCnt <= rTimeoutCnt + 1; + end if; + end if; +end process TimeoutCounter; + +rTimeoutOvf <= '0' when rTimeoutCnt /= kTimeoutEnd - 1 else + '1'; + +SyncBaseOvf: entity work.SyncBase + generic map ( + kResetTo => '0', + kStages => 2) --use double FF synchronizer + port map ( + aReset => aRst, + InClk => RefClk, + iIn => rTimeoutOvf, + OutClk => PixelClk, + oOut => pTimeoutOvf); + +SyncBaseRst: entity work.SyncBase + generic map ( + kResetTo => '1', + kStages => 2) --use double FF synchronizer + port map ( + aReset => aRst, + InClk => PixelClk, + iIn => pTimeoutRst, + OutClk => RefClk, + oOut => rTimeoutRst); + +-- Phase alignment controller to lock onto data stream +PhaseAlignX: entity work.PhaseAlign + generic map ( + kUseFastAlgorithm => false, + kCtlTknCount => kCtlTknCount, + kIDLY_TapValuePs => kIDLY_TapValuePs, + kIDLY_TapWidth => kIDLY_TapWidth + ) + port map ( + pRst => pAlignRst, + PixelClk => PixelClk, + pTimeoutOvf => pTimeoutOvf, + pTimeoutRst => pTimeoutRst, + pData => pDataInRaw, + pIDLY_CE => pIDLY_CE, + pIDLY_INC => pIDLY_INC, + pIDLY_CNT => pIDLY_CNT, + pIDLY_LD => pIDLY_LD, + pAligned => pAligned, + pError => pAlignErr_int, + pEyeSize => pEyeSize); + +pAlignErr <= pAlignErr_int; +pMeVld <= pAligned; + +-- Bitslip when phase alignment exhausted the whole tap range and still no lock +Bitslip: process(PixelClk) +begin + if Rising_Edge(PixelClk) then + pAlignErr_q <= pAlignErr_int; + pBitslip <= not pAlignErr_q and pAlignErr_int; -- single pulse bitslip on failed alignment attempt + end if; +end process Bitslip; + +ResetAlignment: process(PixelClk, aRst) +begin + if (aRst = '1') then + pAlignRst <= '1'; + elsif Rising_Edge(PixelClk) then + if (pRst = '1' or pBitslip = '1') then + pAlignRst <= '1'; + elsif (pBitslipCnt = 0) then + pAlignRst <= '0'; + end if; + end if; +end process ResetAlignment; + +-- Reset phase aligment module after bitslip + 3 CLKDIV cycles (ISERDESE2 requirement) +BitslipDelay: process(PixelClk) +begin + if Rising_Edge(PixelClk) then + if (pBitslip = '1') then + pBitslipCnt <= kBitslipDelay - 1; + elsif (pBitslipCnt /= 0) then + pBitslipCnt <= pBitslipCnt - 1; + end if; + end if; +end process BitslipDelay; + +-- Channel de-skew (bonding) +ChannelBondX: entity work.ChannelBond + port map ( + PixelClk => PixelClk, + pDataInRaw => pDataInRaw, + pMeVld => pAligned, + pOtherChVld => pOtherChVld, + pOtherChRdy => pOtherChRdy, + pDataInBnd => pDataInBnd, + pMeRdy => pMeRdy_int); + +pMeRdy <= pMeRdy_int; + +-- Below performs the 10B-8B decoding function +-- DVI Specification: Section 3.3.3, Figure 3-6, page 31. +pDataIn8b <= pDataInBnd(7 downto 0) when pDataInBnd(9) = '0' else + not pDataInBnd(7 downto 0); + +TMDS_Decode: process (PixelClk) +begin + if Rising_Edge(PixelClk) then + if (pMeRdy_int = '1' and pOtherChRdy = "11") then + pDataIn <= x"00"; --added for VGA-compatibility (blank pixel needed during blanking) + + case (pDataInBnd) is + --Control tokens decode straight to C0, C1 values + when kCtlTkn0 => + pC0 <= '0'; + pC1 <= '0'; + pVde <= '0'; + when kCtlTkn1 => + pC0 <= '1'; + pC1 <= '0'; + pVde <= '0'; + when kCtlTkn2 => + pC0 <= '0'; + pC1 <= '1'; + pVde <= '0'; + when kCtlTkn3 => + pC0 <= '1'; + pC1 <= '1'; + pVde <= '0'; + --If not control token, it's encoded data + when others => + pVde <= '1'; + pDataIn(0) <= pDataIn8b(0); + for iBit in 1 to 7 loop + if (pDataInBnd(8) = '1') then + pDataIn(iBit) <= pDataIn8b(iBit) xor pDataIn8b(iBit-1); + else + pDataIn(iBit) <= pDataIn8b(iBit) xnor pDataIn8b(iBit-1); + end if; + end loop; + end case; + else --if we are not aligned on all channels, gate outputs + pC0 <= '0'; + pC1 <= '0'; + pVde <= '0'; + pDataIn <= x"00"; + end if; + end if; +end process; + +end Behavioral; \ No newline at end of file diff --git a/src/bd/Arty_Z7_20/ipshared/d2d3/src/TWI_SlaveCtl.vhd b/src/bd/Arty_Z7_20/ipshared/d2d3/src/TWI_SlaveCtl.vhd new file mode 100644 index 0000000..1d64903 --- /dev/null +++ b/src/bd/Arty_Z7_20/ipshared/d2d3/src/TWI_SlaveCtl.vhd @@ -0,0 +1,337 @@ +------------------------------------------------------------------------------- +-- +-- File: TWI_SlaveCtl.vhd +-- Author: Elod Gyorgy +-- Original Project: HDMI input on 7-series Xilinx FPGA +-- Date: 22 October 2014 +-- +------------------------------------------------------------------------------- +-- (c) 2014 Copyright Digilent Incorporated +-- All Rights Reserved +-- +-- This program is free software; distributed under the terms of BSD 3-clause +-- license ("Revised BSD License", "New BSD License", or "Modified BSD License") +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names +-- of its contributors may be used to endorse or promote products derived +-- from this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +------------------------------------------------------------------------------- +-- +-- Purpose: +-- This module is a two-wire (I2C compatible) slave controller responding +-- to the address defined in SLAVE_ADDRESS. It samples the bus and +-- deserializes data. The module needs to be controlled in turn by a +-- high-level controller. +-- Status signals: +-- DONE_O active-high pulsed when the slave is addressed by a master, +-- or when a data byte is either sent or received +-- END_O active-high pulsed when the master ended the transfer +-- RD_WRN_O high when transfer is read, low when write +-- Control signals: +-- STB_I needs to be held high when the current byte needs to be +-- acknowledged; this is the case for the device address, as +-- well as every byte written to-slave +-- D_I data needs to be provided on this bus when read transaction +-- occurs; needs to be held until DONE_O +-- D_O data will appear on D_O when a write transaction occurs; +-- valid on DONE_O +-- +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.math_real.all; + +entity TWI_SlaveCtl is + generic ( + SLAVE_ADDRESS : std_logic_vector(7 downto 0) := x"A0"; -- TWI Slave address + kSampleClkFreqInMHz : natural := 100 + ); + Port ( D_I : in STD_LOGIC_VECTOR (7 downto 0); + D_O : out STD_LOGIC_VECTOR (7 downto 0); + RD_WRN_O : out STD_LOGIC; + END_O : out STD_LOGIC; + DONE_O : out STD_LOGIC; + STB_I : in STD_LOGIC; + SampleClk : in STD_LOGIC; + SRST : in STD_LOGIC; + --two-wire bus + SDA_I : in STD_LOGIC; + SDA_O : out STD_LOGIC; + SDA_T : out STD_LOGIC; + SCL_I : in STD_LOGIC; + SCL_O : out STD_LOGIC; + SCL_T : out STD_LOGIC + ); +end TWI_SlaveCtl; + +architecture Behavioral of TWI_SlaveCtl is + constant kGlitchDurationInNs : natural := 50; --tSP in I2C specs + constant kNoOfPeriodsToFilter : natural := natural(ceil(real(kGlitchDurationInNs * kSampleClkFreqInMHz) / 1000.0)); + attribute fsm_encoding: string; + type state_type is (stIdle, stAddress, stRead, stWrite, stSAck, stMAck, stTurnAround); + signal state, nstate : state_type; + attribute fsm_encoding of state: signal is "gray"; + + signal dSda, ddSda, dScl, ddScl : std_logic; + signal fStart, fStop, fSCLFalling, fSCLRising : std_logic; + signal dataByte : std_logic_vector(7 downto 0); --shift register and parallel load + signal iEnd, iDone, latchData, dataBitOut, shiftBitIn, shiftBitOut : std_logic; + signal rd_wrn, drive : std_logic; + signal bitCount : natural range 0 to 7 := 7; + signal sSda, sScl, sSdaFtr, sSclFtr : std_logic; +begin + +-- Synchronize SDA and SCL inputs +SyncSDA: entity work.SyncAsync + generic map ( + kResetTo => '1', + kStages => 2) + port map ( + aReset => '0', + aIn => SDA_I, + OutClk => SampleClk, + oOut => sSda); +SyncSCL: entity work.SyncAsync + generic map ( + kResetTo => '1', + kStages => 2) + port map ( + aReset => '0', + aIn => SCL_I, + OutClk => SampleClk, + oOut => sScl); + +-- Glitch filter as required by I2C Fast-mode specs +GlitchF_SDA: entity work.GlitchFilter + Generic map (kNoOfPeriodsToFilter) + Port map ( + SampleClk => SampleClk, + sIn => sSda, + sOut => sSdaFtr, + sRst => SRST); +GlitchF_SCL: entity work.GlitchFilter + Generic map (kNoOfPeriodsToFilter) + Port map ( + SampleClk => SampleClk, + sIn => sScl, + sOut => sSclFtr, + sRst => SRST); + +---------------------------------------------------------------------------------- +--Bus State detection +---------------------------------------------------------------------------------- +EdgeDetect: process(SampleClk) + begin + if Rising_Edge(SampleClk) then + dSda <= sSdaFtr; + ddSda <= dSda; + dScl <= sSclFtr; + ddScl <= dScl; + end if; + end process; + + fStart <= dSCL and not dSda and ddSda; --if SCL high while SDA falling, start condition + fStop <= dSCL and dSda and not ddSda; --if SCL high while SDA rising, stop condition + + fSCLFalling <= ddSCL and not dScl; -- SCL falling + fSCLRising <= not ddSCL and dScl; -- SCL rising + +---------------------------------------------------------------------------------- +-- Open-drain outputs for bi-directional SDA and SCL +---------------------------------------------------------------------------------- + SDA_T <= '1' when dataBitOut = '1' or drive = '0' else -- high-Z + '0'; --drive + SDA_O <= '0'; + + SCL_T <= '1'; -- input 4eva + SCL_O <= '0'; + +---------------------------------------------------------------------------------- +-- Title: Data byte shift register +-- Description: Stores the byte to be written or the byte read depending on the +-- transfer direction. +---------------------------------------------------------------------------------- +DATABYTE_SHREG: process (SampleClk) + begin + if Rising_Edge(SampleClk) then + if ((latchData = '1' and fSCLFalling = '1') or state = stIdle or fStart = '1') then + dataByte <= D_I; --latch data + bitCount <= 7; + elsif (shiftBitOut = '1' and fSCLFalling = '1') then + dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA; + bitCount <= bitCount - 1; + elsif (shiftBitIn = '1' and fSCLRising = '1') then + dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA; + bitCount <= bitCount - 1; + end if; + end if; + end process; + + dataBitOut <= '0' when state = stSAck else + dataByte(dataByte'high); + D_O <= dataByte; + RD_WRN_O <= rd_wrn; + +RDWRN_BIT_REG: process (SampleClk) + begin + if Rising_Edge(SampleClk) then + if (state = stAddress and bitCount = 0 and fSCLRising = '1') then + rd_wrn <= dSDA; + end if; + end if; + end process; + +SYNC_PROC: process (SampleClk) + begin + if Rising_Edge(SampleClk) then + state <= nstate; + END_O <= iEnd; + DONE_O <= iDone; + end if; + end process; + +OUTPUT_DECODE: process (nstate, state, fSCLRising, fSCLFalling, ddSDA, bitCount, rd_wrn, dataByte, fStop, fStart) + begin + iDone <= '0'; + iEnd <= '0'; + shiftBitIn <= '0'; + shiftBitOut <= '0'; + latchData <= '0'; + drive <= '0'; + + if (state = stRead or state = stSAck) then + drive <= '1'; + end if; + + if (state = stAddress or state = stWrite) then + shiftBitIn <= '1'; + end if; + + if (state = stRead) then + shiftBitOut <= '1'; + end if; + + if ((state = stSAck and rd_wrn = '1') or + (state = stMAck and ddSda = '0')) then --get the data byte for the next read + latchData <= '1'; + end if; + + if ((state = stAddress and bitCount = 0 and fSCLRising = '1' and dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) or + (state = stWrite and bitCount = 0 and fSCLRising = '1') or + (state = stRead and bitCount = 0 and fSCLFalling = '1')) then + iDone <= '1'; + end if; + + if (fStop = '1' or fStart = '1' or + (state = stMAck and fSCLRising = '1' and ddSDA = '1')) then + iEnd <= '1'; + end if; + + end process; + +NEXT_STATE_DECODE: process (state, fStart, STB_I, fSCLRising, fSCLFalling, bitCount, ddSDA, rd_wrn, dataByte, fStop) + begin + + nstate <= state; --default is to stay in current state + + case (state) is + when stIdle => + if (fStart = '1') then -- start condition received + nstate <= stAddress; + end if; + + when stAddress => + if (fStop = '1') then + nstate <= stIdle; + elsif (bitCount = 0 and fSCLRising = '1') then + if (dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) then + nstate <= stTurnAround; + else + nstate <= stIdle; + end if; + end if; + + when stTurnAround => + if (fStop = '1') then + nstate <= stIdle; + elsif (fStart = '1') then + nstate <= stAddress; + elsif (fSCLFalling = '1') then + if (STB_I = '1') then + nstate <= stSAck; --we acknowledge and continue + else + nstate <= stIdle; --don't ack and stop + end if; + end if; + + when stSAck => + if (fStop = '1') then + nstate <= stIdle; + elsif (fStart = '1') then + nstate <= stAddress; + elsif fSCLFalling = '1' then + if (rd_wrn = '1') then + nstate <= stRead; + else + nstate <= stWrite; + end if; + end if; + + when stWrite => + if (fStop = '1') then + nstate <= stIdle; + elsif (fStart = '1') then + nstate <= stAddress; + elsif (bitCount = 0 and fSCLRising = '1') then + nstate <= stTurnAround; + end if; + + when stMAck => + if (fStop = '1') then + nstate <= stIdle; + elsif (fStart = '1') then + nstate <= stAddress; + elsif (fSCLFalling = '1') then + if (ddSDA = '1') then + nstate <= stIdle; + else + nstate <= stRead; + end if; + end if; + + when stRead => + if (fStop = '1') then + nstate <= stIdle; + elsif (fStart = '1') then + nstate <= stAddress; + elsif (bitCount = 0 and fSCLFalling = '1') then + nstate <= stMAck; + end if; + + when others => + nstate <= stIdle; + end case; + end process; + +end Behavioral; + diff --git a/src/bd/Arty_Z7_20/ipshared/d2d3/src/dvi2rgb.vhd b/src/bd/Arty_Z7_20/ipshared/d2d3/src/dvi2rgb.vhd new file mode 100644 index 0000000..10f5540 --- /dev/null +++ b/src/bd/Arty_Z7_20/ipshared/d2d3/src/dvi2rgb.vhd @@ -0,0 +1,260 @@ +------------------------------------------------------------------------------- +-- +-- File: dvi2rgb.vhd +-- Author: Elod Gyorgy +-- Original Project: HDMI input on 7-series Xilinx FPGA +-- Date: 24 July 2015 +-- +------------------------------------------------------------------------------- +-- (c) 2015 Copyright Digilent Incorporated +-- All Rights Reserved +-- +-- This program is free software; distributed under the terms of BSD 3-clause +-- license ("Revised BSD License", "New BSD License", or "Modified BSD License") +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names +-- of its contributors may be used to endorse or promote products derived +-- from this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +------------------------------------------------------------------------------- +-- +-- Purpose: +-- This module connects to a top level DVI 1.0 sink interface comprised of three +-- TMDS data channels and one TMDS clock channel. It includes the necessary +-- clock infrastructure, deserialization, phase alignment, channel deskew and +-- decode logic. It outputs 24-bit RGB video data along with pixel clock and +-- synchronization signals. +-- +------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +use work.DVI_Constants.all; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity dvi2rgb is + Generic ( + kEmulateDDC : boolean := true; --will emulate a DDC EEPROM with basic EDID, if set to yes + kRstActiveHigh : boolean := true; --true, if active-high; false, if active-low + kAddBUFG : boolean := true; --true, if PixelClk should be re-buffered with BUFG + kClkRange : natural := 2; -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3) + kEdidFileName : string := "900p_edid.data"; -- Select EDID file to use + -- 7-series specific + kIDLY_TapValuePs : natural := 78; --delay in ps per tap + kIDLY_TapWidth : natural := 5); --number of bits for IDELAYE2 tap counter + Port ( + -- DVI 1.0 TMDS video interface + TMDS_Clk_p : in std_logic; + TMDS_Clk_n : in std_logic; + TMDS_Data_p : in std_logic_vector(2 downto 0); + TMDS_Data_n : in std_logic_vector(2 downto 0); + + -- Auxiliary signals + RefClk : in std_logic; --200 MHz reference clock for IDELAYCTRL, reset, lock monitoring etc. + aRst : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec + aRst_n : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec + + -- Video out + vid_pData : out std_logic_vector(23 downto 0); + vid_pVDE : out std_logic; + vid_pHSync : out std_logic; + vid_pVSync : out std_logic; + + PixelClk : out std_logic; --pixel-clock recovered from the DVI interface + + SerialClk : out std_logic; -- advanced use only; 5x PixelClk + aPixelClkLckd : out std_logic; -- advanced use only; PixelClk and SerialClk stable + + -- Optional DDC port + DDC_SDA_I : in std_logic; + DDC_SDA_O : out std_logic; + DDC_SDA_T : out std_logic; + DDC_SCL_I : in std_logic; + DDC_SCL_O : out std_logic; + DDC_SCL_T : out std_logic; + + pRst : in std_logic; -- synchronous reset; will restart locking procedure + pRst_n : in std_logic -- synchronous reset; will restart locking procedure + ); +end dvi2rgb; + +architecture Behavioral of dvi2rgb is +type dataIn_t is array (2 downto 0) of std_logic_vector(7 downto 0); +type eyeSize_t is array (2 downto 0) of std_logic_vector(kIDLY_TapWidth-1 downto 0); +signal aLocked, SerialClk_int, PixelClk_int, pLockLostRst: std_logic; +signal pRdy, pVld, pDE, pAlignErr, pC0, pC1 : std_logic_vector(2 downto 0); +signal pDataIn : dataIn_t; +signal pEyeSize : eyeSize_t; + +signal aRst_int, pRst_int : std_logic; + +signal pData : std_logic_vector(23 downto 0); +signal pVDE, pHSync, pVSync : std_logic; + +begin + +ResetActiveLow: if not kRstActiveHigh generate + aRst_int <= not aRst_n; + pRst_int <= not pRst_n; +end generate ResetActiveLow; + +ResetActiveHigh: if kRstActiveHigh generate + aRst_int <= aRst; + pRst_int <= pRst; +end generate ResetActiveHigh; + +-- Clocking infrastructure to obtain a usable fast serial clock and a slow parallel clock +TMDS_ClockingX: entity work.TMDS_Clocking + generic map ( + kClkRange => kClkRange) + port map ( + aRst => aRst_int, + RefClk => RefClk, + TMDS_Clk_p => TMDS_Clk_p, + TMDS_Clk_n => TMDS_Clk_n, + + aLocked => aLocked, + PixelClk => PixelClk_int, -- slow parallel clock + SerialClk => SerialClk_int -- fast serial clock + ); + +-- We need a reset bridge to use the asynchronous aLocked signal to reset our circuitry +-- and decrease the chance of metastability. The signal pLockLostRst can be used as +-- asynchronous reset for any flip-flop in the PixelClk domain, since it will be de-asserted +-- synchronously. +LockLostReset: entity work.ResetBridge + generic map ( + kPolarity => '1') + port map ( + aRst => not aLocked, + OutClk => PixelClk_int, + oRst => pLockLostRst); + +-- Three data channel decoders +DataDecoders: for iCh in 2 downto 0 generate + DecoderX: entity work.TMDS_Decoder + generic map ( + kCtlTknCount => kMinTknCntForBlank, --how many subsequent control tokens make a valid blank detection (DVI spec) + kTimeoutMs => kBlankTimeoutMs, --what is the maximum time interval for a blank to be detected (DVI spec) + kRefClkFrqMHz => 200, --what is the RefClk frequency + kIDLY_TapValuePs => kIDLY_TapValuePs, --delay in ps per tap + kIDLY_TapWidth => kIDLY_TapWidth) --number of bits for IDELAYE2 tap counter + port map ( + aRst => pLockLostRst, + PixelClk => PixelClk_int, + SerialClk => SerialClk_int, + RefClk => RefClk, + pRst => pRst_int, + sDataIn_p => TMDS_Data_p(iCh), + sDataIn_n => TMDS_Data_n(iCh), + pOtherChRdy(1 downto 0) => pRdy((iCh+1) mod 3) & pRdy((iCh+2) mod 3), -- tie channels together for channel de-skew + pOtherChVld(1 downto 0) => pVld((iCh+1) mod 3) & pVld((iCh+2) mod 3), -- tie channels together for channel de-skew + + pAlignErr => pAlignErr(iCh), + pC0 => pC0(iCh), + pC1 => pC1(iCh), + pMeRdy => pRdy(iCh), + pMeVld => pVld(iCh), + pVde => pDE(iCh), + pDataIn(7 downto 0) => pDataIn(iCh), + pEyeSize => pEyeSize(iCh) + ); +end generate DataDecoders; + +-- RGB Output conform DVI 1.0 +-- except that it sends blank pixel during blanking +-- for some reason video_data uses RBG packing +pData(23 downto 16) <= pDataIn(2); -- red is channel 2 +pData(7 downto 0) <= pDataIn(1); -- green is channel 1 +pData(15 downto 8) <= pDataIn(0); -- blue is channel 0 +pHSync <= pC0(0); -- channel 0 carries control signals too +pVSync <= pC1(0); -- channel 0 carries control signals too +pVDE <= pDE(0); -- since channels are aligned, all of them are either active or blanking at once + +-- Clock outputs +SerialClk <= SerialClk_int; -- fast 5x pixel clock for advanced use only +aPixelClkLckd <= aLocked; +---------------------------------------------------------------------------------- +-- Re-buffer PixelClk with a BUFG so that it can reach the whole device, unlike +-- through a BUFR. Since BUFG introduces a delay on the clock path, pixel data is +-- re-registered here. +---------------------------------------------------------------------------------- +GenerateBUFG: if kAddBUFG generate + ResyncToBUFG_X: entity work.ResyncToBUFG + port map ( + -- Video in + piData => pData, + piVDE => pVDE, + piHSync => pHSync, + piVSync => pVSync, + PixelClkIn => PixelClk_int, + -- Video out + poData => vid_pData, + poVDE => vid_pVDE, + poHSync => vid_pHSync, + poVSync => vid_pVSync, + PixelClkOut => PixelClk + ); +end generate GenerateBUFG; + +DontGenerateBUFG: if not kAddBUFG generate + vid_pData <= pData; + vid_pVDE <= pVDE; + vid_pHSync <= pHSync; + vid_pVSync <= pVSync; + PixelClk <= PixelClk_int; +end generate DontGenerateBUFG; + +---------------------------------------------------------------------------------- +-- Optional DDC EEPROM Display Data Channel - Bi-directional (DDC2B) +-- The EDID will be loaded from the file specified below in kInitFileName. +---------------------------------------------------------------------------------- +GenerateDDC: if kEmulateDDC generate + DDC_EEPROM: entity work.EEPROM_8b + generic map ( + kSampleClkFreqInMHz => 200, + kSlaveAddress => "1010000", + kAddrBits => 7, -- 128 byte EDID 1.x data + kWritable => false, + kInitFileName => kEdidFileName) -- name of file containing init values + port map( + SampleClk => RefClk, + sRst => '0', + aSDA_I => DDC_SDA_I, + aSDA_O => DDC_SDA_O, + aSDA_T => DDC_SDA_T, + aSCL_I => DDC_SCL_I, + aSCL_O => DDC_SCL_O, + aSCL_T => DDC_SCL_T); +end generate GenerateDDC; + +end Behavioral; diff --git a/src/bd/Arty_Z7_20/ui/bd_1b964757.ui b/src/bd/Arty_Z7_20/ui/bd_1b964757.ui new file mode 100644 index 0000000..429dfb4 --- /dev/null +++ b/src/bd/Arty_Z7_20/ui/bd_1b964757.ui @@ -0,0 +1,151 @@ +{ + DisplayTieOff: "1", + guistr: "# # String gsaved with Nlview 6.6.5b 2016-09-06 bk=1.3687 VDI=39 GEI=35 GUI=JA:1.6 +# -string -flagsOSRD +preplace port btns_4bits -pg 1 -y 1540 -defaultsOSRD +preplace port DDR -pg 1 -y 700 -defaultsOSRD +preplace port Vp_Vn -pg 1 -y 1480 -defaultsOSRD +preplace port shield_dp26_dp41 -pg 1 -y 1050 -defaultsOSRD +preplace port TMDS -pg 1 -y 330 -defaultsOSRD +preplace port RGBLED -pg 1 -y 660 -defaultsOSRD +preplace port shield_SPI -pg 1 -y 560 -defaultsOSRD +preplace port Vaux0 -pg 1 -y 1660 -defaultsOSRD +preplace port HDMI_HPD -pg 1 -y 1430 -defaultsOSRD +preplace port Vaux1 -pg 1 -y 1680 -defaultsOSRD +preplace port sys_clock -pg 1 -y 1560 -defaultsOSRD +preplace port shield_IIC -pg 1 -y 740 -defaultsOSRD +preplace port leds_4bits -pg 1 -y 930 -defaultsOSRD +preplace port DDC_In -pg 1 -y 1340 -defaultsOSRD +preplace port shield_dp0_dp13 -pg 1 -y 810 -defaultsOSRD +preplace port Vaux12 -pg 1 -y 1780 -defaultsOSRD +preplace port Vaux5 -pg 1 -y 1700 -defaultsOSRD +preplace port HDMI_DDC -pg 1 -y 720 -defaultsOSRD +preplace port FIXED_IO -pg 1 -y 680 -defaultsOSRD +preplace port sws_2bits -pg 1 -y 1560 -defaultsOSRD +preplace port Vaux13 -pg 1 -y 1800 -defaultsOSRD +preplace port Vaux6 -pg 1 -y 1720 -defaultsOSRD +preplace port Vaux15 -pg 1 -y 1820 -defaultsOSRD +preplace port Vaux8 -pg 1 -y 1740 -defaultsOSRD +preplace port hdmi_in_hpd -pg 1 -y 1230 -defaultsOSRD +preplace port TMDS_In -pg 1 -y 1360 -defaultsOSRD +preplace port Vaux9 -pg 1 -y 1760 -defaultsOSRD +preplace inst v_axi4s_vid_out_0 -pg 1 -lvl 12 -y 570 -defaultsOSRD +preplace inst v_tc_0 -pg 1 -lvl 11 -y 560 -defaultsOSRD +preplace inst axi_vdma_0 -pg 1 -lvl 6 -y 1060 -defaultsOSRD +preplace inst v_tc_1 -pg 1 -lvl 10 -y 1090 -defaultsOSRD +preplace inst xlconstant_0 -pg 1 -lvl 4 -y 800 -defaultsOSRD +preplace inst rst_processing_system7_0_100M -pg 1 -lvl 1 -y 1270 -defaultsOSRD +preplace inst xadc_wiz_0 -pg 1 -lvl 10 -y 1740 -defaultsOSRD +preplace inst axi_gpio_sw -pg 1 -lvl 13 -y 1560 -defaultsOSRD +preplace inst proc_sys_reset_0 -pg 1 -lvl 2 -y 1190 -defaultsOSRD +preplace inst xlconcat_0 -pg 1 -lvl 7 -y 1170 -defaultsOSRD +preplace inst axi_gpio_led -pg 1 -lvl 13 -y 930 -defaultsOSRD +preplace inst xlconcat_1 -pg 1 -lvl 9 -y 760 -defaultsOSRD +preplace inst rgb2dvi_0 -pg 1 -lvl 13 -y 330 -defaultsOSRD +preplace inst axi_gpio_hdmi -pg 1 -lvl 13 -y 1440 -defaultsOSRD +preplace inst axi_gpio_video -pg 1 -lvl 13 -y 1260 -defaultsOSRD +preplace inst proc_sys_reset_2 -pg 1 -lvl 9 -y 950 -defaultsOSRD +preplace inst axis_subset_converter_0 -pg 1 -lvl 11 -y 990 -defaultsOSRD +preplace inst axi_dynclk_0 -pg 1 -lvl 10 -y 340 -defaultsOSRD +preplace inst axis_subset_converter_1 -pg 1 -lvl 5 -y 780 -defaultsOSRD +preplace inst v_vid_in_axi4s_0 -pg 1 -lvl 3 -y 880 -defaultsOSRD +preplace inst proc_sys_reset_3 -pg 1 -lvl 9 -y 1460 -defaultsOSRD +preplace inst v_rgb2ycrcb_0 -pg 1 -lvl 4 -y 950 -defaultsOSRD +preplace inst clk_wiz_0 -pg 1 -lvl 1 -y 1550 -defaultsOSRD +preplace inst axi_gpio_shield_1 -pg 1 -lvl 13 -y 810 -defaultsOSRD +preplace inst dvi2rgb_0 -pg 1 -lvl 2 -y 1390 -defaultsOSRD +preplace inst proc_sys_reset_sysclk -pg 1 -lvl 2 -y 1570 -defaultsOSRD +preplace inst rst_processing_system7_0_142M -pg 1 -lvl 6 -y 750 -defaultsOSRD +preplace inst axi_mem_intercon -pg 1 -lvl 7 -y 810 -defaultsOSRD +preplace inst axi_gpio_shield_2 -pg 1 -lvl 13 -y 1050 -defaultsOSRD +preplace inst processing_system7_0_axi_periph -pg 1 -lvl 9 -y 310 -defaultsOSRD +preplace inst processing_system7_0 -pg 1 -lvl 8 -y 760 -defaultsOSRD +preplace netloc axi_gpio_2_GPIO 1 13 1 NJ +preplace netloc Vaux5_1 1 0 10 NJ 1700 NJ 1700 NJ 1700 NJ 1700 NJ 1700 NJ 1700 NJ 1700 NJ 1700 NJ 1700 NJ +preplace netloc axi_vdma_0_M_AXI_MM2S 1 6 1 1960 +preplace netloc axi_gpio_video_GPIO 1 13 1 NJ +preplace netloc processing_system7_0_axi_periph_M08_AXI 1 9 4 3200 420 NJ 420 NJ 420 4130J +preplace netloc processing_system7_0_FIXED_IO 1 8 6 NJ 660 NJ 660 3550J 700 NJ 700 4140J 680 NJ +preplace netloc axi_vdma_0_M_AXI_S2MM 1 6 1 1980 +preplace netloc sys_clock_1 1 0 1 NJ +preplace netloc processing_system7_0_SPI0_SS2_O 1 8 1 2750 +preplace netloc axi_vdma_0_s2mm_introut 1 6 1 1960 +preplace netloc v_vid_in_axi4s_0_video_out 1 3 1 860 +preplace netloc dvi2rgb_0_aPixelClkLckd 1 1 13 250 1310 580 1360 NJ 1360 NJ 1360 NJ 1360 NJ 1360 NJ 1360 NJ 1360 NJ 1360 NJ 1360 NJ 1360 NJ 1360 4470 +preplace netloc axi_vdma_0_M_AXIS_MM2S 1 6 5 NJ 1040 NJ 1040 NJ 1040 3260J 960 3540 +preplace netloc axis_subset_converter_1_M_AXIS 1 5 1 1540 +preplace netloc proc_sys_reset_0_peripheral_reset 1 2 1 600 +preplace netloc xlconcat_0_dout 1 7 1 2330 +preplace netloc v_tc_0_vtiming_out 1 11 1 3850 +preplace netloc processing_system7_0_GPIO_0 1 8 6 2840J 700 3200J 710 NJ 710 NJ 710 NJ 710 4470J +preplace netloc axi_gpio_0_GPIO 1 13 1 NJ +preplace netloc processing_system7_0_axi_periph_M06_AXI 1 9 4 3180 1420 NJ 1420 NJ 1420 NJ +preplace netloc processing_system7_0_DDR 1 8 6 NJ 640 NJ 640 3560J 720 NJ 720 4150J 700 NJ +preplace netloc dvi2rgb_0_DDC 1 2 12 570J 1350 NJ 1350 NJ 1350 NJ 1350 NJ 1350 NJ 1350 NJ 1350 NJ 1350 NJ 1350 NJ 1350 NJ 1350 4480J +preplace netloc axi_gpio_0_GPIO2 1 13 1 NJ +preplace netloc axi_gpio_shield_2_GPIO 1 13 1 NJ +preplace netloc Vaux12_1 1 0 10 NJ 1780 NJ 1780 NJ 1780 NJ 1780 NJ 1780 NJ 1780 NJ 1780 NJ 1780 NJ 1780 NJ +preplace netloc axi_gpio_video_ip2intc_irpt 1 6 8 2030 1340 NJ 1340 NJ 1340 NJ 1340 NJ 1340 NJ 1340 NJ 1340 4460 +preplace netloc v_tc_1_irq 1 6 5 2040 1290 NJ 1290 NJ 1290 NJ 1290 3560 +preplace netloc Vaux15_1 1 0 10 NJ 1820 NJ 1820 NJ 1820 NJ 1820 NJ 1820 NJ 1820 NJ 1820 NJ 1820 NJ 1820 NJ +preplace netloc processing_system7_0_axi_periph_M05_AXI 1 9 1 N +preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 9 -120 540 240 540 NJ 540 NJ 540 NJ 540 1560 540 NJ 540 NJ 540 2780 +preplace netloc rst_processing_system7_0_142M_peripheral_aresetn 1 6 1 1970 +preplace netloc TMDS_1_1 1 0 2 NJ 1360 NJ +preplace netloc processing_system7_0_axi_periph_M10_AXI 1 9 4 3190 1240 NJ 1240 NJ 1240 NJ +preplace netloc proc_sys_reset_0_peripheral_aresetn 1 2 8 NJ 1230 NJ 1230 NJ 1230 1530J 1250 1990J 1020 NJ 1020 2730J 1150 N +preplace netloc processing_system7_0_axi_periph_M02_AXI 1 9 4 N 250 NJ 250 NJ 250 4160J +preplace netloc processing_system7_0_axi_periph_M03_AXI 1 5 5 1570 520 NJ 520 NJ 520 2850J 630 3170 +preplace netloc Vaux13_1 1 0 10 NJ 1800 NJ 1800 NJ 1800 NJ 1800 NJ 1800 NJ 1800 NJ 1800 NJ 1800 NJ 1800 NJ +preplace netloc axi_gpio_0_ip2intc_irpt 1 6 8 2010 1560 NJ 1560 NJ 1560 NJ 1560 NJ 1560 NJ 1560 4120J 1630 4460 +preplace netloc processing_system7_0_axi_periph_M07_AXI 1 9 1 3210 +preplace netloc axi_gpio_hdmi_ip2intc_irpt 1 6 8 2000 1550 NJ 1550 NJ 1550 NJ 1550 NJ 1550 NJ 1550 4130J 1640 4480 +preplace netloc processing_system7_0_axi_periph_M09_AXI 1 9 1 3240 +preplace netloc axi_vdma_0_mm2s_introut 1 6 1 1980 +preplace netloc Vp_Vn_1 1 0 10 NJ 1480 NJ 1480 NJ 1480 NJ 1480 NJ 1480 NJ 1480 NJ 1480 NJ 1480 2740J 1640 NJ +preplace netloc processing_system7_0_IIC_0 1 8 6 2770J 850 NJ 850 NJ 850 NJ 850 4190J 720 NJ +preplace netloc processing_system7_0_IIC_1 1 8 6 2810J 820 NJ 820 NJ 820 NJ 820 4200J 730 4470J +preplace netloc processing_system7_0_axi_periph_M01_AXI 1 9 4 N 230 NJ 230 NJ 230 4180J +preplace netloc dvi2rgb_0_PixelClk 1 1 9 250 1100 610 1400 NJ 1400 NJ 1400 NJ 1400 NJ 1400 NJ 1400 2820J 1050 N +preplace netloc Vaux0_1 1 0 10 NJ 1660 NJ 1660 NJ 1660 NJ 1660 NJ 1660 NJ 1660 NJ 1660 NJ 1660 NJ 1660 NJ +preplace netloc processing_system7_0_SPI_0 1 8 6 2760J 830 3230J 740 NJ 740 NJ 740 NJ 740 4460J +preplace netloc dvi2rgb_0_RGB 1 2 1 590 +preplace netloc processing_system7_0_FCLK_CLK0 1 0 13 -110 1840 NJ 1840 NJ 1840 NJ 1840 NJ 1840 1540 1840 NJ 1840 2320 1840 2800 1840 3220 540 3580 810 NJ 810 4180 +preplace netloc axi_dynclk_0_PXL_CLK_O 1 10 3 3580 320 3860 320 4140J +preplace netloc processing_system7_0_FCLK_CLK1 1 2 10 620 530 870 530 1250 530 1550 530 2000 530 2310 530 2730 840 NJ 840 3570 690 3880J +preplace netloc v_rgb2ycrcb_0_video_out 1 4 1 1270 +preplace netloc processing_system7_0_FCLK_CLK2 1 8 1 2760 +preplace netloc rst_processing_system7_0_100M_interconnect_aresetn 1 1 8 220J 90 NJ 90 NJ 90 NJ 90 NJ 90 NJ 90 NJ 90 N +preplace netloc processing_system7_0_axi_periph_M00_AXI 1 9 4 N 210 NJ 210 NJ 210 4170J +preplace netloc clk_wiz_0_locked 1 1 1 210 +preplace netloc processing_system7_0_FCLK_CLK3 1 8 1 2740 +preplace netloc Vaux8_1 1 0 10 NJ 1740 NJ 1740 NJ 1740 NJ 1740 NJ 1740 NJ 1740 NJ 1740 NJ 1740 NJ 1740 NJ +preplace netloc v_tc_0_irq 1 6 6 2040 560 NJ 560 2820J 860 NJ 860 NJ 860 3850 +preplace netloc xadc_wiz_0_ip2intc_irpt 1 6 5 2020 1310 NJ 1310 NJ 1310 NJ 1310 3560 +preplace netloc rst_processing_system7_0_142M_interconnect_aresetn 1 6 1 1990 +preplace netloc axi_dynclk_0_LOCKED_O 1 10 3 NJ 360 NJ 360 4150 +preplace netloc Vaux6_1 1 0 10 NJ 1720 NJ 1720 NJ 1720 NJ 1720 NJ 1720 NJ 1720 NJ 1720 NJ 1720 NJ 1720 NJ +preplace netloc v_vid_in_axi4s_0_vtiming_out 1 3 7 880J 550 NJ 550 NJ 550 NJ 550 NJ 550 2790J 690 3170 +preplace netloc processing_system7_0_SPI0_SS1_O 1 8 1 2790 +preplace netloc axi_gpio_hdmi_GPIO 1 13 1 NJ +preplace netloc v_axi4s_vid_out_0_vtg_ce 1 10 3 3590 750 NJ 750 4120 +preplace netloc clk_wiz_0_clk_out1 1 1 1 N +preplace netloc axi_gpio_1_GPIO 1 13 1 NJ +preplace netloc clk_wiz_0_clk_out2 1 1 1 230 +preplace netloc processing_system7_0_M_AXI_GP0 1 8 1 2740 +preplace netloc xlconstant_0_dout 1 4 7 1260 570 NJ 570 NJ 570 NJ 570 2770J 670 NJ 670 3530J +preplace netloc Vaux1_1 1 0 10 NJ 1680 NJ 1680 NJ 1680 NJ 1680 NJ 1680 NJ 1680 NJ 1680 NJ 1680 NJ 1680 NJ +preplace netloc rgb2dvi_0_TMDS 1 13 1 NJ +preplace netloc axi_mem_intercon_M00_AXI 1 7 1 2300 +preplace netloc axis_subset_converter_0_M_AXIS 1 11 1 3870 +preplace netloc Vaux9_1 1 0 10 NJ 1760 NJ 1760 NJ 1760 NJ 1760 NJ 1760 NJ 1760 NJ 1760 NJ 1760 NJ 1760 NJ +preplace netloc processing_system7_0_axi_periph_M04_AXI 1 9 2 3260 480 NJ +preplace netloc rst_processing_system7_0_100M_peripheral_aresetn 1 1 12 220 1860 NJ 1860 NJ 1860 NJ 1860 1560 1860 NJ 1860 NJ 1860 2830 1860 3250 620 3540 830 NJ 830 4140 +preplace netloc axi_dynclk_0_PXL_CLK_5X_O 1 10 3 NJ 340 NJ 340 4130 +preplace netloc v_axi4s_vid_out_0_vid_io_out 1 12 1 4120 +levelinfo -pg 1 -140 50 410 740 1150 1400 1770 2170 2530 3010 3400 3720 4000 4330 4510 -top 0 -bot 1910 +", +} +{ + da_axi4_cnt: "5", +} \ No newline at end of file diff --git a/src/constraints/ARTY_Z7.xdc b/src/constraints/ARTY_Z7.xdc index 66041f9..6afa487 100644 --- a/src/constraints/ARTY_Z7.xdc +++ b/src/constraints/ARTY_Z7.xdc @@ -67,17 +67,17 @@ set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { shield set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { shield_spi_ss_io }]; #IO_L6P_T0_35 Sch=ck_ss #set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_25_35 Sch=crypto_sda #set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L13N_T2_MRCC_35 Sch=hdmi_rx_cec -#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVDS } [get_ports { hdmi_rx_clk_n }]; #IO_L13N_T2_MRCC_34 Sch=hdmi_rx_clk_n -#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVDS } [get_ports { hdmi_rx_clk_p }]; #IO_L13P_T2_MRCC_34 Sch=hdmi_rx_clk_p -#set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVDS } [get_ports { hdmi_rx_d_n[0] }]; #IO_L16N_T2_34 Sch=hdmi_rx_d_n[0] -#set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVDS } [get_ports { hdmi_rx_d_p[0] }]; #IO_L16P_T2_34 Sch=hdmi_rx_d_p[0] -#set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVDS } [get_ports { hdmi_rx_d_n[1] }]; #IO_L15N_T2_DQS_34 Sch=hdmi_rx_d_n[1] -#set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVDS } [get_ports { hdmi_rx_d_p[1] }]; #IO_L15P_T2_DQS_34 Sch=hdmi_rx_d_p[1] -#set_property -dict { PACKAGE_PIN P20 IOSTANDARD LVDS } [get_ports { hdmi_rx_d_n[2] }]; #IO_L14N_T2_SRCC_34 Sch=hdmi_rx_d_n[2] -#set_property -dict { PACKAGE_PIN N20 IOSTANDARD LVDS } [get_ports { hdmi_rx_d_p[2] }]; #IO_L14P_T2_SRCC_34 Sch=hdmi_rx_d_p[2] -#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpd }]; #IO_25_34 Sch=hdmi_rx_hpd -#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L11P_T1_SRCC_34 Sch=hdmi_rx_scl -#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L11N_T1_SRCC_34 Sch=hdmi_rx_sda +set_property -dict { PACKAGE_PIN P19 IOSTANDARD TMDS_33 } [get_ports { TMDS_In_clk_n }]; #IO_L13N_T2_MRCC_34 Sch=hdmi_rx_clk_n +set_property -dict { PACKAGE_PIN N18 IOSTANDARD TMDS_33 } [get_ports { TMDS_In_clk_p }]; #IO_L13P_T2_MRCC_34 Sch=hdmi_rx_clk_p +set_property -dict { PACKAGE_PIN W20 IOSTANDARD TMDS_33 } [get_ports { TMDS_In_data_n[0] }]; #IO_L16N_T2_34 Sch=hdmi_rx_d_n[0] +set_property -dict { PACKAGE_PIN V20 IOSTANDARD TMDS_33 } [get_ports { TMDS_In_data_p[0] }]; #IO_L16P_T2_34 Sch=hdmi_rx_d_p[0] +set_property -dict { PACKAGE_PIN U20 IOSTANDARD TMDS_33 } [get_ports { TMDS_In_data_n[1] }]; #IO_L15N_T2_DQS_34 Sch=hdmi_rx_d_n[1] +set_property -dict { PACKAGE_PIN T20 IOSTANDARD TMDS_33 } [get_ports { TMDS_In_data_p[1] }]; #IO_L15P_T2_DQS_34 Sch=hdmi_rx_d_p[1] +set_property -dict { PACKAGE_PIN P20 IOSTANDARD TMDS_33 } [get_ports { TMDS_In_data_n[2] }]; #IO_L14N_T2_SRCC_34 Sch=hdmi_rx_d_n[2] +set_property -dict { PACKAGE_PIN N20 IOSTANDARD TMDS_33 } [get_ports { TMDS_In_data_p[2] }]; #IO_L14P_T2_SRCC_34 Sch=hdmi_rx_d_p[2] +set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_in_hpd_tri_o }]; #IO_25_34 Sch=hdmi_rx_hpd +set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { ddc_in_scl_io }]; #IO_L11P_T1_SRCC_34 Sch=hdmi_rx_scl +set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { ddc_in_sda_io }]; #IO_L11N_T1_SRCC_34 Sch=hdmi_rx_sda #set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L19N_T3_VREF_35 Sch=hdmi_tx_cec set_property -dict { PACKAGE_PIN L17 IOSTANDARD TMDS_33 } [get_ports { TMDS_clk_n }]; #IO_L11N_T1_SRCC_35 Sch=hdmi_tx_clk_n set_property -dict { PACKAGE_PIN L16 IOSTANDARD TMDS_33 } [get_ports { TMDS_clk_p }]; #IO_L11P_T1_SRCC_35 Sch=hdmi_tx_clk_p diff --git a/src/others/SDSoC_Staging/.gitignore b/src/others/SDSoC_Staging/.gitignore new file mode 100644 index 0000000..17f8d1f --- /dev/null +++ b/src/others/SDSoC_Staging/.gitignore @@ -0,0 +1,4 @@ +include_linux/** +lib_linux/** +!include_linux/README.txt +!lib_linux/README.txt \ No newline at end of file diff --git a/src/others/SDSoC_Staging/boot_linux/fsbl.elf b/src/others/SDSoC_Staging/boot_linux/fsbl.elf new file mode 100644 index 0000000..a350758 Binary files /dev/null and b/src/others/SDSoC_Staging/boot_linux/fsbl.elf differ diff --git a/src/others/SDSoC_Staging/boot_linux/generic.readme b/src/others/SDSoC_Staging/boot_linux/generic.readme new file mode 100644 index 0000000..47bef93 --- /dev/null +++ b/src/others/SDSoC_Staging/boot_linux/generic.readme @@ -0,0 +1,8 @@ +-= SD card boot image =- + +Platform: +Application: + +1. Copy the contents of this directory to an SD card +2. Set boot mode to SD +3. Insert SD card and turn board on diff --git a/src/others/SDSoC_Staging/linux.bif b/src/others/SDSoC_Staging/boot_linux/linux.bif similarity index 100% rename from src/others/SDSoC_Staging/linux.bif rename to src/others/SDSoC_Staging/boot_linux/linux.bif diff --git a/src/others/SDSoC_Staging/boot_linux/u-boot.elf b/src/others/SDSoC_Staging/boot_linux/u-boot.elf new file mode 100644 index 0000000..41a3664 Binary files /dev/null and b/src/others/SDSoC_Staging/boot_linux/u-boot.elf differ diff --git a/src/others/SDSoC_Staging/hw_pfm_gen.tcl b/src/others/SDSoC_Staging/hw_pfm_gen.tcl index 30afe22..87112c0 100644 --- a/src/others/SDSoC_Staging/hw_pfm_gen.tcl +++ b/src/others/SDSoC_Staging/hw_pfm_gen.tcl @@ -4,7 +4,7 @@ set pfm [sdsoc::create_pfm Arty_Z7_20.hpfm] sdsoc::pfm_name $pfm "digilentinc.com" "xd" "Arty_Z7_20" "1.0" -sdsoc::pfm_description $pfm "Arty Z7-20 Board" +sdsoc::pfm_description $pfm "Arty Z7-20 Development board with support for HDMI input and HDMI output in all OS's" sdsoc::pfm_clock $pfm FCLK_CLK0 processing_system7_0 0 true rst_processing_system7_0_100M sdsoc::pfm_clock $pfm FCLK_CLK1 processing_system7_0 1 false rst_processing_system7_0_142M sdsoc::pfm_clock $pfm FCLK_CLK2 processing_system7_0 2 false proc_sys_reset_2 @@ -14,7 +14,7 @@ sdsoc::pfm_axi_port $pfm M_AXI_GP1 processing_system7_0 M_AXI_GP sdsoc::pfm_axi_port $pfm S_AXI_ACP processing_system7_0 S_AXI_ACP sdsoc::pfm_axi_port $pfm S_AXI_HP2 processing_system7_0 S_AXI_HP sdsoc::pfm_axi_port $pfm S_AXI_HP3 processing_system7_0 S_AXI_HP -for {set i 7} {$i < 16} {incr i} { +for {set i 8} {$i < 16} {incr i} { sdsoc::pfm_irq $pfm In$i xlconcat_0 } sdsoc::pfm_iodev $pfm S_AXI axi_gpio_sw uio diff --git a/src/others/SDSoC_Staging/image/image.ub b/src/others/SDSoC_Staging/image/image.ub new file mode 100644 index 0000000..8400a04 Binary files /dev/null and b/src/others/SDSoC_Staging/image/image.ub differ diff --git a/src/others/SDSoC_Staging/include_bsp/xparameters.h b/src/others/SDSoC_Staging/include_bsp/xparameters.h index 9e342e2..8f91ccb 100644 --- a/src/others/SDSoC_Staging/include_bsp/xparameters.h +++ b/src/others/SDSoC_Staging/include_bsp/xparameters.h @@ -27,29 +27,29 @@ #define XPAR_AXI_VDMA_0_DEVICE_ID 0 #define XPAR_AXI_VDMA_0_BASEADDR 0x43000000 #define XPAR_AXI_VDMA_0_HIGHADDR 0x4300FFFF -#define XPAR_AXI_VDMA_0_NUM_FSTORES 1 +#define XPAR_AXI_VDMA_0_NUM_FSTORES 3 #define XPAR_AXI_VDMA_0_INCLUDE_MM2S 1 #define XPAR_AXI_VDMA_0_INCLUDE_MM2S_DRE 0 #define XPAR_AXI_VDMA_0_M_AXI_MM2S_DATA_WIDTH 64 -#define XPAR_AXI_VDMA_0_INCLUDE_S2MM 0 +#define XPAR_AXI_VDMA_0_INCLUDE_S2MM 1 #define XPAR_AXI_VDMA_0_INCLUDE_S2MM_DRE 0 #define XPAR_AXI_VDMA_0_M_AXI_S2MM_DATA_WIDTH 64 #define XPAR_AXI_VDMA_0_AXI_MM2S_ACLK_FREQ_HZ 0 #define XPAR_AXI_VDMA_0_AXI_S2MM_ACLK_FREQ_HZ 0 #define XPAR_AXI_VDMA_0_MM2S_GENLOCK_MODE 0 #define XPAR_AXI_VDMA_0_MM2S_GENLOCK_NUM_MASTERS 1 -#define XPAR_AXI_VDMA_0_S2MM_GENLOCK_MODE 0 +#define XPAR_AXI_VDMA_0_S2MM_GENLOCK_MODE 2 #define XPAR_AXI_VDMA_0_S2MM_GENLOCK_NUM_MASTERS 1 #define XPAR_AXI_VDMA_0_INCLUDE_SG 0 #define XPAR_AXI_VDMA_0_ENABLE_VIDPRMTR_READS 1 #define XPAR_AXI_VDMA_0_USE_FSYNC 1 #define XPAR_AXI_VDMA_0_FLUSH_ON_FSYNC 1 -#define XPAR_AXI_VDMA_0_MM2S_LINEBUFFER_DEPTH 4096 -#define XPAR_AXI_VDMA_0_S2MM_LINEBUFFER_DEPTH 512 +#define XPAR_AXI_VDMA_0_MM2S_LINEBUFFER_DEPTH 2048 +#define XPAR_AXI_VDMA_0_S2MM_LINEBUFFER_DEPTH 2048 #define XPAR_AXI_VDMA_0_INCLUDE_INTERNAL_GENLOCK 1 #define XPAR_AXI_VDMA_0_S2MM_SOF_ENABLE 1 #define XPAR_AXI_VDMA_0_M_AXIS_MM2S_TDATA_WIDTH 32 -#define XPAR_AXI_VDMA_0_S_AXIS_S2MM_TDATA_WIDTH 32 +#define XPAR_AXI_VDMA_0_S_AXIS_S2MM_TDATA_WIDTH 8 #define XPAR_AXI_VDMA_0_ENABLE_DEBUG_INFO_1 0 #define XPAR_AXI_VDMA_0_ENABLE_DEBUG_INFO_5 0 #define XPAR_AXI_VDMA_0_ENABLE_DEBUG_INFO_6 1 @@ -68,29 +68,29 @@ #define XPAR_AXIVDMA_0_DEVICE_ID XPAR_AXI_VDMA_0_DEVICE_ID #define XPAR_AXIVDMA_0_BASEADDR 0x43000000 #define XPAR_AXIVDMA_0_HIGHADDR 0x4300FFFF -#define XPAR_AXIVDMA_0_NUM_FSTORES 1 +#define XPAR_AXIVDMA_0_NUM_FSTORES 3 #define XPAR_AXIVDMA_0_INCLUDE_MM2S 1 #define XPAR_AXIVDMA_0_INCLUDE_MM2S_DRE 0 #define XPAR_AXIVDMA_0_M_AXI_MM2S_DATA_WIDTH 64 -#define XPAR_AXIVDMA_0_INCLUDE_S2MM 0 +#define XPAR_AXIVDMA_0_INCLUDE_S2MM 1 #define XPAR_AXIVDMA_0_INCLUDE_S2MM_DRE 0 #define XPAR_AXIVDMA_0_M_AXI_S2MM_DATA_WIDTH 64 #define XPAR_AXIVDMA_0_AXI_MM2S_ACLK_FREQ_HZ 0 #define XPAR_AXIVDMA_0_AXI_S2MM_ACLK_FREQ_HZ 0 #define XPAR_AXIVDMA_0_MM2S_GENLOCK_MODE 0 #define XPAR_AXIVDMA_0_MM2S_GENLOCK_NUM_MASTERS 1 -#define XPAR_AXIVDMA_0_S2MM_GENLOCK_MODE 0 +#define XPAR_AXIVDMA_0_S2MM_GENLOCK_MODE 2 #define XPAR_AXIVDMA_0_S2MM_GENLOCK_NUM_MASTERS 1 #define XPAR_AXIVDMA_0_INCLUDE_SG 0 #define XPAR_AXIVDMA_0_ENABLE_VIDPRMTR_READS 1 #define XPAR_AXIVDMA_0_USE_FSYNC 1 #define XPAR_AXIVDMA_0_FLUSH_ON_FSYNC 1 -#define XPAR_AXIVDMA_0_MM2S_LINEBUFFER_DEPTH 4096 -#define XPAR_AXIVDMA_0_S2MM_LINEBUFFER_DEPTH 512 +#define XPAR_AXIVDMA_0_MM2S_LINEBUFFER_DEPTH 2048 +#define XPAR_AXIVDMA_0_S2MM_LINEBUFFER_DEPTH 2048 #define XPAR_AXIVDMA_0_INCLUDE_INTERNAL_GENLOCK 1 #define XPAR_AXIVDMA_0_S2MM_SOF_ENABLE 1 #define XPAR_AXIVDMA_0_M_AXIS_MM2S_TDATA_WIDTH 32 -#define XPAR_AXIVDMA_0_S_AXIS_S2MM_TDATA_WIDTH 32 +#define XPAR_AXIVDMA_0_S_AXIS_S2MM_TDATA_WIDTH 8 #define XPAR_AXIVDMA_0_ENABLE_DEBUG_INFO_1 0 #define XPAR_AXIVDMA_0_ENABLE_DEBUG_INFO_5 0 #define XPAR_AXIVDMA_0_ENABLE_DEBUG_INFO_6 1 @@ -296,7 +296,7 @@ /******************************************************************/ /* Definitions for driver GPIO */ -#define XPAR_XGPIO_NUM_INSTANCES 5 +#define XPAR_XGPIO_NUM_INSTANCES 6 /* Definitions for peripheral AXI_GPIO_HDMI */ #define XPAR_AXI_GPIO_HDMI_BASEADDR 0x41230000 @@ -318,7 +318,7 @@ #define XPAR_AXI_GPIO_SHIELD_1_BASEADDR 0x41210000 #define XPAR_AXI_GPIO_SHIELD_1_HIGHADDR 0x4121FFFF #define XPAR_AXI_GPIO_SHIELD_1_DEVICE_ID 2 -#define XPAR_AXI_GPIO_SHIELD_1_INTERRUPT_PRESENT 1 +#define XPAR_AXI_GPIO_SHIELD_1_INTERRUPT_PRESENT 0 #define XPAR_AXI_GPIO_SHIELD_1_IS_DUAL 0 @@ -326,7 +326,7 @@ #define XPAR_AXI_GPIO_SHIELD_2_BASEADDR 0x41240000 #define XPAR_AXI_GPIO_SHIELD_2_HIGHADDR 0x4124FFFF #define XPAR_AXI_GPIO_SHIELD_2_DEVICE_ID 3 -#define XPAR_AXI_GPIO_SHIELD_2_INTERRUPT_PRESENT 1 +#define XPAR_AXI_GPIO_SHIELD_2_INTERRUPT_PRESENT 0 #define XPAR_AXI_GPIO_SHIELD_2_IS_DUAL 0 @@ -338,6 +338,14 @@ #define XPAR_AXI_GPIO_SW_IS_DUAL 1 +/* Definitions for peripheral AXI_GPIO_VIDEO */ +#define XPAR_AXI_GPIO_VIDEO_BASEADDR 0x41250000 +#define XPAR_AXI_GPIO_VIDEO_HIGHADDR 0x4125FFFF +#define XPAR_AXI_GPIO_VIDEO_DEVICE_ID 5 +#define XPAR_AXI_GPIO_VIDEO_INTERRUPT_PRESENT 1 +#define XPAR_AXI_GPIO_VIDEO_IS_DUAL 1 + + /******************************************************************/ /* Canonical definitions for peripheral AXI_GPIO_HDMI */ @@ -358,14 +366,14 @@ #define XPAR_GPIO_2_BASEADDR 0x41210000 #define XPAR_GPIO_2_HIGHADDR 0x4121FFFF #define XPAR_GPIO_2_DEVICE_ID XPAR_AXI_GPIO_SHIELD_1_DEVICE_ID -#define XPAR_GPIO_2_INTERRUPT_PRESENT 1 +#define XPAR_GPIO_2_INTERRUPT_PRESENT 0 #define XPAR_GPIO_2_IS_DUAL 0 /* Canonical definitions for peripheral AXI_GPIO_SHIELD_2 */ #define XPAR_GPIO_3_BASEADDR 0x41240000 #define XPAR_GPIO_3_HIGHADDR 0x4124FFFF #define XPAR_GPIO_3_DEVICE_ID XPAR_AXI_GPIO_SHIELD_2_DEVICE_ID -#define XPAR_GPIO_3_INTERRUPT_PRESENT 1 +#define XPAR_GPIO_3_INTERRUPT_PRESENT 0 #define XPAR_GPIO_3_IS_DUAL 0 /* Canonical definitions for peripheral AXI_GPIO_SW */ @@ -375,6 +383,13 @@ #define XPAR_GPIO_4_INTERRUPT_PRESENT 1 #define XPAR_GPIO_4_IS_DUAL 1 +/* Canonical definitions for peripheral AXI_GPIO_VIDEO */ +#define XPAR_GPIO_5_BASEADDR 0x41250000 +#define XPAR_GPIO_5_HIGHADDR 0x4125FFFF +#define XPAR_GPIO_5_DEVICE_ID XPAR_AXI_GPIO_VIDEO_DEVICE_ID +#define XPAR_GPIO_5_INTERRUPT_PRESENT 1 +#define XPAR_GPIO_5_IS_DUAL 1 + /******************************************************************/ @@ -460,8 +475,9 @@ #define XPAR_FABRIC_V_TC_0_IRQ_INTR 63 #define XPAR_FABRIC_AXI_GPIO_SW_IP2INTC_IRPT_INTR 64 #define XPAR_FABRIC_XADC_WIZ_0_IP2INTC_IRPT_INTR 65 -#define XPAR_FABRIC_AXI_GPIO_SHIELD_1_IP2INTC_IRPT_INTR 66 -#define XPAR_FABRIC_AXI_GPIO_SHIELD_2_IP2INTC_IRPT_INTR 67 +#define XPAR_FABRIC_V_TC_1_IRQ_INTR 66 +#define XPAR_FABRIC_AXI_GPIO_VIDEO_IP2INTC_IRPT_INTR 67 +#define XPAR_FABRIC_AXI_VDMA_0_S2MM_INTROUT_INTR 68 /******************************************************************/ @@ -646,7 +662,7 @@ /******************************************************************/ /* Definitions for driver VTC */ -#define XPAR_XVTC_NUM_INSTANCES 1 +#define XPAR_XVTC_NUM_INSTANCES 2 /* Definitions for peripheral V_TC_0 */ #define XPAR_V_TC_0_DEVICE_ID 0 @@ -662,6 +678,20 @@ #define XPAR_V_TC_0_DET_ACHROMA_EN 0 +/* Definitions for peripheral V_TC_1 */ +#define XPAR_V_TC_1_DEVICE_ID 1 +#define XPAR_V_TC_1_BASEADDR 0x43C30000 +#define XPAR_V_TC_1_HIGHADDR 0x43C3FFFF +#define XPAR_V_TC_1_GENERATE_EN 0 +#define XPAR_V_TC_1_DETECT_EN 1 +#define XPAR_V_TC_1_DET_HSYNC_EN 1 +#define XPAR_V_TC_1_DET_VSYNC_EN 1 +#define XPAR_V_TC_1_DET_HBLANK_EN 0 +#define XPAR_V_TC_1_DET_VBLANK_EN 0 +#define XPAR_V_TC_1_DET_AVIDEO_EN 1 +#define XPAR_V_TC_1_DET_ACHROMA_EN 0 + + /******************************************************************/ /* Canonical definitions for peripheral V_TC_0 */ @@ -677,6 +707,19 @@ #define XPAR_VTC_0_DET_AVIDEO_EN 1 #define XPAR_VTC_0_DET_ACHROMA_EN 0 +/* Canonical definitions for peripheral V_TC_1 */ +#define XPAR_VTC_1_DEVICE_ID XPAR_V_TC_1_DEVICE_ID +#define XPAR_VTC_1_BASEADDR 0x43C30000 +#define XPAR_VTC_1_HIGHADDR 0x43C3FFFF +#define XPAR_VTC_1_GENERATE_EN 0 +#define XPAR_VTC_1_DETECT_EN 1 +#define XPAR_VTC_1_DET_HSYNC_EN 1 +#define XPAR_VTC_1_DET_VSYNC_EN 1 +#define XPAR_VTC_1_DET_HBLANK_EN 0 +#define XPAR_VTC_1_DET_VBLANK_EN 0 +#define XPAR_VTC_1_DET_AVIDEO_EN 1 +#define XPAR_VTC_1_DET_ACHROMA_EN 0 + /******************************************************************/ diff --git a/src/others/SDSoC_Staging/include_linux/README.txt b/src/others/SDSoC_Staging/include_linux/README.txt new file mode 100644 index 0000000..ba8e49a --- /dev/null +++ b/src/others/SDSoC_Staging/include_linux/README.txt @@ -0,0 +1,5 @@ +This folder is currently empty until the issues with petalinux are ironed out. +Once they are ironed out, this folder will either be a copy of the contents +found in /usr/include of the petalinux rootfs, or it will be removed and the +platform_builder.xml will link directly to the petalinux build directory of the +rootfs. diff --git a/src/others/SDSoC_Staging/lib_bsp/libxil.a b/src/others/SDSoC_Staging/lib_bsp/libxil.a deleted file mode 100644 index 5b9b996..0000000 Binary files a/src/others/SDSoC_Staging/lib_bsp/libxil.a and /dev/null differ diff --git a/src/others/SDSoC_Staging/lib_linux/README.txt b/src/others/SDSoC_Staging/lib_linux/README.txt new file mode 100644 index 0000000..94dbbfd --- /dev/null +++ b/src/others/SDSoC_Staging/lib_linux/README.txt @@ -0,0 +1,5 @@ +This folder is currently empty until the issues with petalinux are ironed out. +Once they are ironed out, this folder will either be a copy of the contents +found in /usr/lib of the petalinux rootfs, or it will be removed and the +platform_builder.xml will link directly to the petalinux build directory of the +rootfs. diff --git a/src/others/SDSoC_Staging/platform_builder.xml b/src/others/SDSoC_Staging/platform_builder.xml index ba7d8bc..d677411 100644 --- a/src/others/SDSoC_Staging/platform_builder.xml +++ b/src/others/SDSoC_Staging/platform_builder.xml @@ -1 +1 @@ - \ No newline at end of file + \ No newline at end of file diff --git a/src/others/SDSoC_Staging/prebuilt_platform/Arty_Z7_20.hdf b/src/others/SDSoC_Staging/prebuilt_platform/Arty_Z7_20.hdf index c9163d5..491b94a 100644 Binary files a/src/others/SDSoC_Staging/prebuilt_platform/Arty_Z7_20.hdf and b/src/others/SDSoC_Staging/prebuilt_platform/Arty_Z7_20.hdf differ diff --git a/src/others/SDSoC_Staging/prebuilt_platform/bitstream.bit b/src/others/SDSoC_Staging/prebuilt_platform/bitstream.bit index 986e2a6..7d257fe 100644 Binary files a/src/others/SDSoC_Staging/prebuilt_platform/bitstream.bit and b/src/others/SDSoC_Staging/prebuilt_platform/bitstream.bit differ diff --git a/src/others/SDSoC_Staging/prebuilt_platform/portinfo.c b/src/others/SDSoC_Staging/prebuilt_platform/portinfo.c index d690868..ef678ac 100644 --- a/src/others/SDSoC_Staging/prebuilt_platform/portinfo.c +++ b/src/others/SDSoC_Staging/prebuilt_platform/portinfo.c @@ -1,4 +1,4 @@ -/* File: C:/sam_work/sdx/16_4/next_test2/my_arty/Debug/_sds/p0/.cf_work/portinfo.c */ +/* File: C:/sam_work/sdx/16_4/next_test_10/platform_create/Debug/_sds/p0/.cf_work/portinfo.c */ #include "cf_lib.h" #include "cf_request.h" #include "sds_lib.h" diff --git a/src/others/SDSoC_Staging/prebuilt_platform/portinfo.h b/src/others/SDSoC_Staging/prebuilt_platform/portinfo.h index 0c18294..7934a34 100644 --- a/src/others/SDSoC_Staging/prebuilt_platform/portinfo.h +++ b/src/others/SDSoC_Staging/prebuilt_platform/portinfo.h @@ -1,6 +1,6 @@ #ifndef _SDS_PORTINFO_H #define _SDS_PORTINFO_H -/* File: C:/sam_work/sdx/16_4/next_test2/my_arty/Debug/_sds/p0/.cf_work/portinfo.h */ +/* File: C:/sam_work/sdx/16_4/next_test_10/platform_create/Debug/_sds/p0/.cf_work/portinfo.h */ #ifdef __cplusplus extern "C" { #endif